2006.257.01:32:34.51;Log Opened: Mark IV Field System Version 9.7.7 2006.257.01:32:34.51;location,TSUKUB32,-140.09,36.10,61.0 2006.257.01:32:34.51;horizon1,0.,5.,360. 2006.257.01:32:34.51;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.257.01:32:34.51;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.257.01:32:34.51;drivev11,330,270,no 2006.257.01:32:34.51;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.257.01:32:34.51;drivev13,15.000,268,10.000,10.000,10.000 2006.257.01:32:34.51;drivev21,330,270,no 2006.257.01:32:34.51;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.257.01:32:34.51;drivev23,15.000,268,10.000,10.000,10.000 2006.257.01:32:34.51;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.257.01:32:34.51;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.257.01:32:34.51;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.257.01:32:34.51;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.257.01:32:34.51;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.257.01:32:34.51;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.257.01:32:34.51;time,-0.364,101.533,rate 2006.257.01:32:34.51;flagr,200 2006.257.01:32:34.51:" JD0609 2006 TSUKUB32 T Ts 2006.257.01:32:34.51:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.257.01:32:34.51:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.257.01:32:34.51:" 108 K4-TSUKB 0 9149 2006.257.01:32:34.51:" drudg version 050216 compiled under FS 9.7.07 2006.257.01:32:34.51:" Rack=K4-2/M4 Recorder 1=K4-2 Recorder 2=none 2006.257.01:32:34.51:exper_initi 2006.257.01:32:34.51&exper_initi/proc_library 2006.257.01:32:34.51&exper_initi/sched_initi 2006.257.01:32:34.52:scan_name=257-0200,jd0609,50 2006.257.01:32:34.52:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.01:32:35.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.257.01:32:35.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.257.01:32:35.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.257.01:32:35.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.257.01:32:35.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.257.01:32:35.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.257.01:32:36.14:ready_k5 2006.257.01:32:36.14&ready_k5/obsinfo=st 2006.257.01:32:36.14&ready_k5/autoobs=1 2006.257.01:32:36.14&ready_k5/autoobs=2 2006.257.01:32:36.14&ready_k5/autoobs=3 2006.257.01:32:36.14&ready_k5/autoobs=4 2006.257.01:32:36.14&ready_k5/obsinfo 2006.257.01:32:36.14#flagr#flagr/antenna,new-source 2006.257.01:32:36.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.257.01:32:39.82/autoobs//k5ts1/ autoobs started! 2006.257.01:32:41.14#trakl#Antenna stuck 2006.257.01:32:43.44/autoobs//k5ts2/ autoobs started! 2006.257.01:32:47.30/autoobs//k5ts3/ autoobs started! 2006.257.01:32:50.81/autoobs//k5ts4/ autoobs started! 2006.257.01:32:50.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.01:32:50.83:setupk4=1 2006.257.01:32:50.83&setupk4/xlog=on 2006.257.01:32:50.83&setupk4/echo=on 2006.257.01:32:50.83&setupk4/pcalon 2006.257.01:32:50.83&setupk4/"tpicd=stop 2006.257.01:32:50.83&setupk4/"rec=synch_on 2006.257.01:32:50.83&setupk4/"rec_mode=128 2006.257.01:32:50.83&setupk4/!* 2006.257.01:32:50.83&setupk4/recpk4 2006.257.01:32:50.83&setupk4/vck44 2006.257.01:32:50.83&setupk4/ifdk4 2006.257.01:32:50.83&setupk4/!*+20s 2006.257.01:32:50.83&setupk4/"tpicd 2006.257.01:32:50.83&setupk4/echo=off 2006.257.01:32:50.83&setupk4/xlog=off 2006.257.01:32:50.83$setupk4/echo=on 2006.257.01:32:50.83$setupk4/pcalon 2006.257.01:32:50.83&pcalon/"no phase cal control is implemented here 2006.257.01:32:50.83$pcalon/"no phase cal control is implemented here 2006.257.01:32:50.83$setupk4/"tpicd=stop 2006.257.01:32:50.83$setupk4/"rec=synch_on 2006.257.01:32:50.83$setupk4/"rec_mode=128 2006.257.01:32:50.83$setupk4/!* 2006.257.01:32:50.83$setupk4/recpk4 2006.257.01:32:50.83&recpk4/recpatch= 2006.257.01:32:50.83&recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.01:32:50.83&recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.01:32:50.83$recpk4/recpatch= 2006.257.01:32:50.85$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.01:32:50.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.01:32:50.88$setupk4/vck44 2006.257.01:32:50.88&vck44/valo=1,524.99 2006.257.01:32:50.88&vck44/va=1,8 2006.257.01:32:50.88&vck44/valo=2,534.99 2006.257.01:32:50.88&vck44/va=2,7 2006.257.01:32:50.88&vck44/valo=3,564.99 2006.257.01:32:50.88&vck44/va=3,8 2006.257.01:32:50.88&vck44/valo=4,624.99 2006.257.01:32:50.88&vck44/va=4,7 2006.257.01:32:50.88&vck44/valo=5,734.99 2006.257.01:32:50.88&vck44/va=5,4 2006.257.01:32:50.88&vck44/valo=6,814.99 2006.257.01:32:50.88&vck44/va=6,4 2006.257.01:32:50.88&vck44/valo=7,864.99 2006.257.01:32:50.88&vck44/va=7,4 2006.257.01:32:50.88&vck44/valo=8,884.99 2006.257.01:32:50.88&vck44/va=8,4 2006.257.01:32:50.88&vck44/vblo=1,629.99 2006.257.01:32:50.88&vck44/vb=1,4 2006.257.01:32:50.88&vck44/vblo=2,634.99 2006.257.01:32:50.88&vck44/vb=2,5 2006.257.01:32:50.88&vck44/vblo=3,649.99 2006.257.01:32:50.88&vck44/vb=3,4 2006.257.01:32:50.88&vck44/vblo=4,679.99 2006.257.01:32:50.88&vck44/vb=4,5 2006.257.01:32:50.88&vck44/vblo=5,709.99 2006.257.01:32:50.88&vck44/vb=5,4 2006.257.01:32:50.88&vck44/vblo=6,719.99 2006.257.01:32:50.88&vck44/vb=6,4 2006.257.01:32:50.88&vck44/vblo=7,734.99 2006.257.01:32:50.88&vck44/vb=7,4 2006.257.01:32:50.88&vck44/vblo=8,744.99 2006.257.01:32:50.88&vck44/vb=8,4 2006.257.01:32:50.88&vck44/vabw=wide 2006.257.01:32:50.88&vck44/vbbw=wide 2006.257.01:32:50.88$vck44/valo=1,524.99 2006.257.01:32:50.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.01:32:50.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.01:32:50.88#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:50.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:50.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:50.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:50.88#ibcon#enter wrdev, iclass 25, count 0 2006.257.01:32:50.88#ibcon#first serial, iclass 25, count 0 2006.257.01:32:50.88#ibcon#enter sib2, iclass 25, count 0 2006.257.01:32:50.88#ibcon#flushed, iclass 25, count 0 2006.257.01:32:50.88#ibcon#about to write, iclass 25, count 0 2006.257.01:32:50.88#ibcon#wrote, iclass 25, count 0 2006.257.01:32:50.88#ibcon#about to read 3, iclass 25, count 0 2006.257.01:32:50.90#ibcon#read 3, iclass 25, count 0 2006.257.01:32:50.90#ibcon#about to read 4, iclass 25, count 0 2006.257.01:32:50.90#ibcon#read 4, iclass 25, count 0 2006.257.01:32:50.90#ibcon#about to read 5, iclass 25, count 0 2006.257.01:32:50.90#ibcon#read 5, iclass 25, count 0 2006.257.01:32:50.90#ibcon#about to read 6, iclass 25, count 0 2006.257.01:32:50.90#ibcon#read 6, iclass 25, count 0 2006.257.01:32:50.90#ibcon#end of sib2, iclass 25, count 0 2006.257.01:32:50.90#ibcon#*mode == 0, iclass 25, count 0 2006.257.01:32:50.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.01:32:50.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.01:32:50.90#ibcon#*before write, iclass 25, count 0 2006.257.01:32:50.90#ibcon#enter sib2, iclass 25, count 0 2006.257.01:32:50.90#ibcon#flushed, iclass 25, count 0 2006.257.01:32:50.90#ibcon#about to write, iclass 25, count 0 2006.257.01:32:50.90#ibcon#wrote, iclass 25, count 0 2006.257.01:32:50.90#ibcon#about to read 3, iclass 25, count 0 2006.257.01:32:50.96#ibcon#read 3, iclass 25, count 0 2006.257.01:32:50.96#ibcon#about to read 4, iclass 25, count 0 2006.257.01:32:50.96#ibcon#read 4, iclass 25, count 0 2006.257.01:32:50.96#ibcon#about to read 5, iclass 25, count 0 2006.257.01:32:50.96#ibcon#read 5, iclass 25, count 0 2006.257.01:32:50.96#ibcon#about to read 6, iclass 25, count 0 2006.257.01:32:50.96#ibcon#read 6, iclass 25, count 0 2006.257.01:32:50.96#ibcon#end of sib2, iclass 25, count 0 2006.257.01:32:50.96#ibcon#*after write, iclass 25, count 0 2006.257.01:32:50.96#ibcon#*before return 0, iclass 25, count 0 2006.257.01:32:50.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:50.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:50.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.01:32:50.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.01:32:50.96$vck44/va=1,8 2006.257.01:32:50.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.01:32:50.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.01:32:50.96#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:50.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:50.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:50.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:50.96#ibcon#enter wrdev, iclass 27, count 2 2006.257.01:32:50.96#ibcon#first serial, iclass 27, count 2 2006.257.01:32:50.96#ibcon#enter sib2, iclass 27, count 2 2006.257.01:32:50.96#ibcon#flushed, iclass 27, count 2 2006.257.01:32:50.96#ibcon#about to write, iclass 27, count 2 2006.257.01:32:50.96#ibcon#wrote, iclass 27, count 2 2006.257.01:32:50.96#ibcon#about to read 3, iclass 27, count 2 2006.257.01:32:50.98#ibcon#read 3, iclass 27, count 2 2006.257.01:32:50.98#ibcon#about to read 4, iclass 27, count 2 2006.257.01:32:50.98#ibcon#read 4, iclass 27, count 2 2006.257.01:32:50.98#ibcon#about to read 5, iclass 27, count 2 2006.257.01:32:50.98#ibcon#read 5, iclass 27, count 2 2006.257.01:32:50.98#ibcon#about to read 6, iclass 27, count 2 2006.257.01:32:50.98#ibcon#read 6, iclass 27, count 2 2006.257.01:32:50.98#ibcon#end of sib2, iclass 27, count 2 2006.257.01:32:50.98#ibcon#*mode == 0, iclass 27, count 2 2006.257.01:32:50.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.01:32:50.98#ibcon#[25=AT01-08\r\n] 2006.257.01:32:50.98#ibcon#*before write, iclass 27, count 2 2006.257.01:32:50.98#ibcon#enter sib2, iclass 27, count 2 2006.257.01:32:50.98#ibcon#flushed, iclass 27, count 2 2006.257.01:32:50.98#ibcon#about to write, iclass 27, count 2 2006.257.01:32:50.98#ibcon#wrote, iclass 27, count 2 2006.257.01:32:50.98#ibcon#about to read 3, iclass 27, count 2 2006.257.01:32:51.02#ibcon#read 3, iclass 27, count 2 2006.257.01:32:51.02#ibcon#about to read 4, iclass 27, count 2 2006.257.01:32:51.02#ibcon#read 4, iclass 27, count 2 2006.257.01:32:51.02#ibcon#about to read 5, iclass 27, count 2 2006.257.01:32:51.02#ibcon#read 5, iclass 27, count 2 2006.257.01:32:51.02#ibcon#about to read 6, iclass 27, count 2 2006.257.01:32:51.02#ibcon#read 6, iclass 27, count 2 2006.257.01:32:51.02#ibcon#end of sib2, iclass 27, count 2 2006.257.01:32:51.02#ibcon#*after write, iclass 27, count 2 2006.257.01:32:51.02#ibcon#*before return 0, iclass 27, count 2 2006.257.01:32:51.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:51.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:51.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.01:32:51.02#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:51.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:51.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:51.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:51.14#ibcon#enter wrdev, iclass 27, count 0 2006.257.01:32:51.14#ibcon#first serial, iclass 27, count 0 2006.257.01:32:51.14#ibcon#enter sib2, iclass 27, count 0 2006.257.01:32:51.14#ibcon#flushed, iclass 27, count 0 2006.257.01:32:51.14#ibcon#about to write, iclass 27, count 0 2006.257.01:32:51.14#ibcon#wrote, iclass 27, count 0 2006.257.01:32:51.14#ibcon#about to read 3, iclass 27, count 0 2006.257.01:32:51.16#ibcon#read 3, iclass 27, count 0 2006.257.01:32:51.16#ibcon#about to read 4, iclass 27, count 0 2006.257.01:32:51.16#ibcon#read 4, iclass 27, count 0 2006.257.01:32:51.16#ibcon#about to read 5, iclass 27, count 0 2006.257.01:32:51.16#ibcon#read 5, iclass 27, count 0 2006.257.01:32:51.16#ibcon#about to read 6, iclass 27, count 0 2006.257.01:32:51.16#ibcon#read 6, iclass 27, count 0 2006.257.01:32:51.16#ibcon#end of sib2, iclass 27, count 0 2006.257.01:32:51.16#ibcon#*mode == 0, iclass 27, count 0 2006.257.01:32:51.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.01:32:51.16#ibcon#[25=USB\r\n] 2006.257.01:32:51.16#ibcon#*before write, iclass 27, count 0 2006.257.01:32:51.16#ibcon#enter sib2, iclass 27, count 0 2006.257.01:32:51.16#ibcon#flushed, iclass 27, count 0 2006.257.01:32:51.16#ibcon#about to write, iclass 27, count 0 2006.257.01:32:51.16#ibcon#wrote, iclass 27, count 0 2006.257.01:32:51.16#ibcon#about to read 3, iclass 27, count 0 2006.257.01:32:51.19#ibcon#read 3, iclass 27, count 0 2006.257.01:32:51.19#ibcon#about to read 4, iclass 27, count 0 2006.257.01:32:51.19#ibcon#read 4, iclass 27, count 0 2006.257.01:32:51.19#ibcon#about to read 5, iclass 27, count 0 2006.257.01:32:51.19#ibcon#read 5, iclass 27, count 0 2006.257.01:32:51.19#ibcon#about to read 6, iclass 27, count 0 2006.257.01:32:51.19#ibcon#read 6, iclass 27, count 0 2006.257.01:32:51.19#ibcon#end of sib2, iclass 27, count 0 2006.257.01:32:51.19#ibcon#*after write, iclass 27, count 0 2006.257.01:32:51.19#ibcon#*before return 0, iclass 27, count 0 2006.257.01:32:51.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:51.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:51.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.01:32:51.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.01:32:51.19$vck44/valo=2,534.99 2006.257.01:32:51.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.01:32:51.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.01:32:51.19#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:51.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:51.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:51.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:51.19#ibcon#enter wrdev, iclass 29, count 0 2006.257.01:32:51.19#ibcon#first serial, iclass 29, count 0 2006.257.01:32:51.19#ibcon#enter sib2, iclass 29, count 0 2006.257.01:32:51.19#ibcon#flushed, iclass 29, count 0 2006.257.01:32:51.19#ibcon#about to write, iclass 29, count 0 2006.257.01:32:51.19#ibcon#wrote, iclass 29, count 0 2006.257.01:32:51.19#ibcon#about to read 3, iclass 29, count 0 2006.257.01:32:51.22#ibcon#read 3, iclass 29, count 0 2006.257.01:32:51.22#ibcon#about to read 4, iclass 29, count 0 2006.257.01:32:51.22#ibcon#read 4, iclass 29, count 0 2006.257.01:32:51.22#ibcon#about to read 5, iclass 29, count 0 2006.257.01:32:51.22#ibcon#read 5, iclass 29, count 0 2006.257.01:32:51.22#ibcon#about to read 6, iclass 29, count 0 2006.257.01:32:51.22#ibcon#read 6, iclass 29, count 0 2006.257.01:32:51.22#ibcon#end of sib2, iclass 29, count 0 2006.257.01:32:51.22#ibcon#*mode == 0, iclass 29, count 0 2006.257.01:32:51.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.01:32:51.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.01:32:51.22#ibcon#*before write, iclass 29, count 0 2006.257.01:32:51.22#ibcon#enter sib2, iclass 29, count 0 2006.257.01:32:51.22#ibcon#flushed, iclass 29, count 0 2006.257.01:32:51.22#ibcon#about to write, iclass 29, count 0 2006.257.01:32:51.22#ibcon#wrote, iclass 29, count 0 2006.257.01:32:51.22#ibcon#about to read 3, iclass 29, count 0 2006.257.01:32:51.26#ibcon#read 3, iclass 29, count 0 2006.257.01:32:51.26#ibcon#about to read 4, iclass 29, count 0 2006.257.01:32:51.26#ibcon#read 4, iclass 29, count 0 2006.257.01:32:51.26#ibcon#about to read 5, iclass 29, count 0 2006.257.01:32:51.26#ibcon#read 5, iclass 29, count 0 2006.257.01:32:51.26#ibcon#about to read 6, iclass 29, count 0 2006.257.01:32:51.26#ibcon#read 6, iclass 29, count 0 2006.257.01:32:51.26#ibcon#end of sib2, iclass 29, count 0 2006.257.01:32:51.26#ibcon#*after write, iclass 29, count 0 2006.257.01:32:51.26#ibcon#*before return 0, iclass 29, count 0 2006.257.01:32:51.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:51.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:51.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.01:32:51.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.01:32:51.26$vck44/va=2,7 2006.257.01:32:51.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.01:32:51.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.01:32:51.26#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:51.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:51.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:51.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:51.31#ibcon#enter wrdev, iclass 31, count 2 2006.257.01:32:51.31#ibcon#first serial, iclass 31, count 2 2006.257.01:32:51.31#ibcon#enter sib2, iclass 31, count 2 2006.257.01:32:51.31#ibcon#flushed, iclass 31, count 2 2006.257.01:32:51.31#ibcon#about to write, iclass 31, count 2 2006.257.01:32:51.31#ibcon#wrote, iclass 31, count 2 2006.257.01:32:51.31#ibcon#about to read 3, iclass 31, count 2 2006.257.01:32:51.34#ibcon#read 3, iclass 31, count 2 2006.257.01:32:51.34#ibcon#about to read 4, iclass 31, count 2 2006.257.01:32:51.34#ibcon#read 4, iclass 31, count 2 2006.257.01:32:51.34#ibcon#about to read 5, iclass 31, count 2 2006.257.01:32:51.34#ibcon#read 5, iclass 31, count 2 2006.257.01:32:51.34#ibcon#about to read 6, iclass 31, count 2 2006.257.01:32:51.34#ibcon#read 6, iclass 31, count 2 2006.257.01:32:51.34#ibcon#end of sib2, iclass 31, count 2 2006.257.01:32:51.34#ibcon#*mode == 0, iclass 31, count 2 2006.257.01:32:51.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.01:32:51.34#ibcon#[25=AT02-07\r\n] 2006.257.01:32:51.34#ibcon#*before write, iclass 31, count 2 2006.257.01:32:51.34#ibcon#enter sib2, iclass 31, count 2 2006.257.01:32:51.34#ibcon#flushed, iclass 31, count 2 2006.257.01:32:51.34#ibcon#about to write, iclass 31, count 2 2006.257.01:32:51.34#ibcon#wrote, iclass 31, count 2 2006.257.01:32:51.34#ibcon#about to read 3, iclass 31, count 2 2006.257.01:32:51.37#ibcon#read 3, iclass 31, count 2 2006.257.01:32:51.37#ibcon#about to read 4, iclass 31, count 2 2006.257.01:32:51.37#ibcon#read 4, iclass 31, count 2 2006.257.01:32:51.37#ibcon#about to read 5, iclass 31, count 2 2006.257.01:32:51.37#ibcon#read 5, iclass 31, count 2 2006.257.01:32:51.37#ibcon#about to read 6, iclass 31, count 2 2006.257.01:32:51.37#ibcon#read 6, iclass 31, count 2 2006.257.01:32:51.37#ibcon#end of sib2, iclass 31, count 2 2006.257.01:32:51.37#ibcon#*after write, iclass 31, count 2 2006.257.01:32:51.37#ibcon#*before return 0, iclass 31, count 2 2006.257.01:32:51.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:51.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:51.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.01:32:51.37#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:51.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:51.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:51.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:51.49#ibcon#enter wrdev, iclass 31, count 0 2006.257.01:32:51.49#ibcon#first serial, iclass 31, count 0 2006.257.01:32:51.49#ibcon#enter sib2, iclass 31, count 0 2006.257.01:32:51.49#ibcon#flushed, iclass 31, count 0 2006.257.01:32:51.49#ibcon#about to write, iclass 31, count 0 2006.257.01:32:51.49#ibcon#wrote, iclass 31, count 0 2006.257.01:32:51.49#ibcon#about to read 3, iclass 31, count 0 2006.257.01:32:51.51#ibcon#read 3, iclass 31, count 0 2006.257.01:32:51.51#ibcon#about to read 4, iclass 31, count 0 2006.257.01:32:51.51#ibcon#read 4, iclass 31, count 0 2006.257.01:32:51.51#ibcon#about to read 5, iclass 31, count 0 2006.257.01:32:51.51#ibcon#read 5, iclass 31, count 0 2006.257.01:32:51.51#ibcon#about to read 6, iclass 31, count 0 2006.257.01:32:51.51#ibcon#read 6, iclass 31, count 0 2006.257.01:32:51.51#ibcon#end of sib2, iclass 31, count 0 2006.257.01:32:51.51#ibcon#*mode == 0, iclass 31, count 0 2006.257.01:32:51.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.01:32:51.51#ibcon#[25=USB\r\n] 2006.257.01:32:51.51#ibcon#*before write, iclass 31, count 0 2006.257.01:32:51.51#ibcon#enter sib2, iclass 31, count 0 2006.257.01:32:51.51#ibcon#flushed, iclass 31, count 0 2006.257.01:32:51.51#ibcon#about to write, iclass 31, count 0 2006.257.01:32:51.51#ibcon#wrote, iclass 31, count 0 2006.257.01:32:51.51#ibcon#about to read 3, iclass 31, count 0 2006.257.01:32:51.54#ibcon#read 3, iclass 31, count 0 2006.257.01:32:51.54#ibcon#about to read 4, iclass 31, count 0 2006.257.01:32:51.54#ibcon#read 4, iclass 31, count 0 2006.257.01:32:51.54#ibcon#about to read 5, iclass 31, count 0 2006.257.01:32:51.54#ibcon#read 5, iclass 31, count 0 2006.257.01:32:51.54#ibcon#about to read 6, iclass 31, count 0 2006.257.01:32:51.54#ibcon#read 6, iclass 31, count 0 2006.257.01:32:51.54#ibcon#end of sib2, iclass 31, count 0 2006.257.01:32:51.54#ibcon#*after write, iclass 31, count 0 2006.257.01:32:51.54#ibcon#*before return 0, iclass 31, count 0 2006.257.01:32:51.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:51.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:51.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.01:32:51.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.01:32:51.54$vck44/valo=3,564.99 2006.257.01:32:51.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.01:32:51.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.01:32:51.54#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:51.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:51.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:51.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:51.54#ibcon#enter wrdev, iclass 33, count 0 2006.257.01:32:51.54#ibcon#first serial, iclass 33, count 0 2006.257.01:32:51.54#ibcon#enter sib2, iclass 33, count 0 2006.257.01:32:51.54#ibcon#flushed, iclass 33, count 0 2006.257.01:32:51.54#ibcon#about to write, iclass 33, count 0 2006.257.01:32:51.54#ibcon#wrote, iclass 33, count 0 2006.257.01:32:51.54#ibcon#about to read 3, iclass 33, count 0 2006.257.01:32:51.56#ibcon#read 3, iclass 33, count 0 2006.257.01:32:51.56#ibcon#about to read 4, iclass 33, count 0 2006.257.01:32:51.56#ibcon#read 4, iclass 33, count 0 2006.257.01:32:51.56#ibcon#about to read 5, iclass 33, count 0 2006.257.01:32:51.56#ibcon#read 5, iclass 33, count 0 2006.257.01:32:51.56#ibcon#about to read 6, iclass 33, count 0 2006.257.01:32:51.56#ibcon#read 6, iclass 33, count 0 2006.257.01:32:51.56#ibcon#end of sib2, iclass 33, count 0 2006.257.01:32:51.56#ibcon#*mode == 0, iclass 33, count 0 2006.257.01:32:51.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.01:32:51.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.01:32:51.56#ibcon#*before write, iclass 33, count 0 2006.257.01:32:51.56#ibcon#enter sib2, iclass 33, count 0 2006.257.01:32:51.56#ibcon#flushed, iclass 33, count 0 2006.257.01:32:51.56#ibcon#about to write, iclass 33, count 0 2006.257.01:32:51.56#ibcon#wrote, iclass 33, count 0 2006.257.01:32:51.56#ibcon#about to read 3, iclass 33, count 0 2006.257.01:32:51.60#ibcon#read 3, iclass 33, count 0 2006.257.01:32:51.60#ibcon#about to read 4, iclass 33, count 0 2006.257.01:32:51.60#ibcon#read 4, iclass 33, count 0 2006.257.01:32:51.60#ibcon#about to read 5, iclass 33, count 0 2006.257.01:32:51.60#ibcon#read 5, iclass 33, count 0 2006.257.01:32:51.60#ibcon#about to read 6, iclass 33, count 0 2006.257.01:32:51.60#ibcon#read 6, iclass 33, count 0 2006.257.01:32:51.60#ibcon#end of sib2, iclass 33, count 0 2006.257.01:32:51.60#ibcon#*after write, iclass 33, count 0 2006.257.01:32:51.60#ibcon#*before return 0, iclass 33, count 0 2006.257.01:32:51.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:51.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:51.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.01:32:51.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.01:32:51.60$vck44/va=3,8 2006.257.01:32:51.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.01:32:51.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.01:32:51.60#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:51.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:51.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:51.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:51.66#ibcon#enter wrdev, iclass 35, count 2 2006.257.01:32:51.66#ibcon#first serial, iclass 35, count 2 2006.257.01:32:51.66#ibcon#enter sib2, iclass 35, count 2 2006.257.01:32:51.66#ibcon#flushed, iclass 35, count 2 2006.257.01:32:51.66#ibcon#about to write, iclass 35, count 2 2006.257.01:32:51.66#ibcon#wrote, iclass 35, count 2 2006.257.01:32:51.66#ibcon#about to read 3, iclass 35, count 2 2006.257.01:32:51.69#ibcon#read 3, iclass 35, count 2 2006.257.01:32:51.69#ibcon#about to read 4, iclass 35, count 2 2006.257.01:32:51.69#ibcon#read 4, iclass 35, count 2 2006.257.01:32:51.69#ibcon#about to read 5, iclass 35, count 2 2006.257.01:32:51.69#ibcon#read 5, iclass 35, count 2 2006.257.01:32:51.69#ibcon#about to read 6, iclass 35, count 2 2006.257.01:32:51.69#ibcon#read 6, iclass 35, count 2 2006.257.01:32:51.69#ibcon#end of sib2, iclass 35, count 2 2006.257.01:32:51.69#ibcon#*mode == 0, iclass 35, count 2 2006.257.01:32:51.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.01:32:51.69#ibcon#[25=AT03-08\r\n] 2006.257.01:32:51.69#ibcon#*before write, iclass 35, count 2 2006.257.01:32:51.69#ibcon#enter sib2, iclass 35, count 2 2006.257.01:32:51.69#ibcon#flushed, iclass 35, count 2 2006.257.01:32:51.69#ibcon#about to write, iclass 35, count 2 2006.257.01:32:51.69#ibcon#wrote, iclass 35, count 2 2006.257.01:32:51.69#ibcon#about to read 3, iclass 35, count 2 2006.257.01:32:51.72#ibcon#read 3, iclass 35, count 2 2006.257.01:32:51.72#ibcon#about to read 4, iclass 35, count 2 2006.257.01:32:51.72#ibcon#read 4, iclass 35, count 2 2006.257.01:32:51.72#ibcon#about to read 5, iclass 35, count 2 2006.257.01:32:51.72#ibcon#read 5, iclass 35, count 2 2006.257.01:32:51.72#ibcon#about to read 6, iclass 35, count 2 2006.257.01:32:51.72#ibcon#read 6, iclass 35, count 2 2006.257.01:32:51.72#ibcon#end of sib2, iclass 35, count 2 2006.257.01:32:51.72#ibcon#*after write, iclass 35, count 2 2006.257.01:32:51.72#ibcon#*before return 0, iclass 35, count 2 2006.257.01:32:51.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:51.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:51.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.01:32:51.72#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:51.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:51.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:51.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:51.84#ibcon#enter wrdev, iclass 35, count 0 2006.257.01:32:51.84#ibcon#first serial, iclass 35, count 0 2006.257.01:32:51.84#ibcon#enter sib2, iclass 35, count 0 2006.257.01:32:51.84#ibcon#flushed, iclass 35, count 0 2006.257.01:32:51.84#ibcon#about to write, iclass 35, count 0 2006.257.01:32:51.84#ibcon#wrote, iclass 35, count 0 2006.257.01:32:51.84#ibcon#about to read 3, iclass 35, count 0 2006.257.01:32:51.86#ibcon#read 3, iclass 35, count 0 2006.257.01:32:51.86#ibcon#about to read 4, iclass 35, count 0 2006.257.01:32:51.86#ibcon#read 4, iclass 35, count 0 2006.257.01:32:51.86#ibcon#about to read 5, iclass 35, count 0 2006.257.01:32:51.86#ibcon#read 5, iclass 35, count 0 2006.257.01:32:51.86#ibcon#about to read 6, iclass 35, count 0 2006.257.01:32:51.86#ibcon#read 6, iclass 35, count 0 2006.257.01:32:51.86#ibcon#end of sib2, iclass 35, count 0 2006.257.01:32:51.86#ibcon#*mode == 0, iclass 35, count 0 2006.257.01:32:51.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.01:32:51.86#ibcon#[25=USB\r\n] 2006.257.01:32:51.86#ibcon#*before write, iclass 35, count 0 2006.257.01:32:51.86#ibcon#enter sib2, iclass 35, count 0 2006.257.01:32:51.86#ibcon#flushed, iclass 35, count 0 2006.257.01:32:51.86#ibcon#about to write, iclass 35, count 0 2006.257.01:32:51.86#ibcon#wrote, iclass 35, count 0 2006.257.01:32:51.86#ibcon#about to read 3, iclass 35, count 0 2006.257.01:32:51.89#ibcon#read 3, iclass 35, count 0 2006.257.01:32:51.89#ibcon#about to read 4, iclass 35, count 0 2006.257.01:32:51.89#ibcon#read 4, iclass 35, count 0 2006.257.01:32:51.89#ibcon#about to read 5, iclass 35, count 0 2006.257.01:32:51.89#ibcon#read 5, iclass 35, count 0 2006.257.01:32:51.89#ibcon#about to read 6, iclass 35, count 0 2006.257.01:32:51.89#ibcon#read 6, iclass 35, count 0 2006.257.01:32:51.89#ibcon#end of sib2, iclass 35, count 0 2006.257.01:32:51.89#ibcon#*after write, iclass 35, count 0 2006.257.01:32:51.89#ibcon#*before return 0, iclass 35, count 0 2006.257.01:32:51.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:51.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:51.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.01:32:51.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.01:32:51.89$vck44/valo=4,624.99 2006.257.01:32:51.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.01:32:51.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.01:32:51.89#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:51.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:51.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:51.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:51.89#ibcon#enter wrdev, iclass 37, count 0 2006.257.01:32:51.89#ibcon#first serial, iclass 37, count 0 2006.257.01:32:51.89#ibcon#enter sib2, iclass 37, count 0 2006.257.01:32:51.89#ibcon#flushed, iclass 37, count 0 2006.257.01:32:51.89#ibcon#about to write, iclass 37, count 0 2006.257.01:32:51.89#ibcon#wrote, iclass 37, count 0 2006.257.01:32:51.89#ibcon#about to read 3, iclass 37, count 0 2006.257.01:32:51.91#ibcon#read 3, iclass 37, count 0 2006.257.01:32:51.91#ibcon#about to read 4, iclass 37, count 0 2006.257.01:32:51.91#ibcon#read 4, iclass 37, count 0 2006.257.01:32:51.91#ibcon#about to read 5, iclass 37, count 0 2006.257.01:32:51.91#ibcon#read 5, iclass 37, count 0 2006.257.01:32:51.91#ibcon#about to read 6, iclass 37, count 0 2006.257.01:32:51.91#ibcon#read 6, iclass 37, count 0 2006.257.01:32:51.91#ibcon#end of sib2, iclass 37, count 0 2006.257.01:32:51.91#ibcon#*mode == 0, iclass 37, count 0 2006.257.01:32:51.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.01:32:51.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.01:32:51.91#ibcon#*before write, iclass 37, count 0 2006.257.01:32:51.91#ibcon#enter sib2, iclass 37, count 0 2006.257.01:32:51.91#ibcon#flushed, iclass 37, count 0 2006.257.01:32:51.91#ibcon#about to write, iclass 37, count 0 2006.257.01:32:51.91#ibcon#wrote, iclass 37, count 0 2006.257.01:32:51.91#ibcon#about to read 3, iclass 37, count 0 2006.257.01:32:51.95#ibcon#read 3, iclass 37, count 0 2006.257.01:32:51.95#ibcon#about to read 4, iclass 37, count 0 2006.257.01:32:51.95#ibcon#read 4, iclass 37, count 0 2006.257.01:32:51.95#ibcon#about to read 5, iclass 37, count 0 2006.257.01:32:51.95#ibcon#read 5, iclass 37, count 0 2006.257.01:32:51.95#ibcon#about to read 6, iclass 37, count 0 2006.257.01:32:51.95#ibcon#read 6, iclass 37, count 0 2006.257.01:32:51.95#ibcon#end of sib2, iclass 37, count 0 2006.257.01:32:51.95#ibcon#*after write, iclass 37, count 0 2006.257.01:32:51.95#ibcon#*before return 0, iclass 37, count 0 2006.257.01:32:51.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:51.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:51.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.01:32:51.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.01:32:51.95$vck44/va=4,7 2006.257.01:32:51.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.01:32:51.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.01:32:51.95#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:51.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:52.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:52.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:52.01#ibcon#enter wrdev, iclass 39, count 2 2006.257.01:32:52.01#ibcon#first serial, iclass 39, count 2 2006.257.01:32:52.01#ibcon#enter sib2, iclass 39, count 2 2006.257.01:32:52.01#ibcon#flushed, iclass 39, count 2 2006.257.01:32:52.01#ibcon#about to write, iclass 39, count 2 2006.257.01:32:52.01#ibcon#wrote, iclass 39, count 2 2006.257.01:32:52.01#ibcon#about to read 3, iclass 39, count 2 2006.257.01:32:52.03#ibcon#read 3, iclass 39, count 2 2006.257.01:32:52.03#ibcon#about to read 4, iclass 39, count 2 2006.257.01:32:52.03#ibcon#read 4, iclass 39, count 2 2006.257.01:32:52.03#ibcon#about to read 5, iclass 39, count 2 2006.257.01:32:52.03#ibcon#read 5, iclass 39, count 2 2006.257.01:32:52.03#ibcon#about to read 6, iclass 39, count 2 2006.257.01:32:52.03#ibcon#read 6, iclass 39, count 2 2006.257.01:32:52.03#ibcon#end of sib2, iclass 39, count 2 2006.257.01:32:52.03#ibcon#*mode == 0, iclass 39, count 2 2006.257.01:32:52.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.01:32:52.03#ibcon#[25=AT04-07\r\n] 2006.257.01:32:52.03#ibcon#*before write, iclass 39, count 2 2006.257.01:32:52.03#ibcon#enter sib2, iclass 39, count 2 2006.257.01:32:52.03#ibcon#flushed, iclass 39, count 2 2006.257.01:32:52.03#ibcon#about to write, iclass 39, count 2 2006.257.01:32:52.03#ibcon#wrote, iclass 39, count 2 2006.257.01:32:52.03#ibcon#about to read 3, iclass 39, count 2 2006.257.01:32:52.06#ibcon#read 3, iclass 39, count 2 2006.257.01:32:52.06#ibcon#about to read 4, iclass 39, count 2 2006.257.01:32:52.06#ibcon#read 4, iclass 39, count 2 2006.257.01:32:52.06#ibcon#about to read 5, iclass 39, count 2 2006.257.01:32:52.06#ibcon#read 5, iclass 39, count 2 2006.257.01:32:52.06#ibcon#about to read 6, iclass 39, count 2 2006.257.01:32:52.06#ibcon#read 6, iclass 39, count 2 2006.257.01:32:52.06#ibcon#end of sib2, iclass 39, count 2 2006.257.01:32:52.06#ibcon#*after write, iclass 39, count 2 2006.257.01:32:52.06#ibcon#*before return 0, iclass 39, count 2 2006.257.01:32:52.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:52.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:52.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.01:32:52.06#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:52.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:52.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:52.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:52.18#ibcon#enter wrdev, iclass 39, count 0 2006.257.01:32:52.18#ibcon#first serial, iclass 39, count 0 2006.257.01:32:52.18#ibcon#enter sib2, iclass 39, count 0 2006.257.01:32:52.18#ibcon#flushed, iclass 39, count 0 2006.257.01:32:52.18#ibcon#about to write, iclass 39, count 0 2006.257.01:32:52.18#ibcon#wrote, iclass 39, count 0 2006.257.01:32:52.18#ibcon#about to read 3, iclass 39, count 0 2006.257.01:32:52.20#ibcon#read 3, iclass 39, count 0 2006.257.01:32:52.20#ibcon#about to read 4, iclass 39, count 0 2006.257.01:32:52.20#ibcon#read 4, iclass 39, count 0 2006.257.01:32:52.20#ibcon#about to read 5, iclass 39, count 0 2006.257.01:32:52.20#ibcon#read 5, iclass 39, count 0 2006.257.01:32:52.20#ibcon#about to read 6, iclass 39, count 0 2006.257.01:32:52.20#ibcon#read 6, iclass 39, count 0 2006.257.01:32:52.20#ibcon#end of sib2, iclass 39, count 0 2006.257.01:32:52.20#ibcon#*mode == 0, iclass 39, count 0 2006.257.01:32:52.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.01:32:52.20#ibcon#[25=USB\r\n] 2006.257.01:32:52.20#ibcon#*before write, iclass 39, count 0 2006.257.01:32:52.20#ibcon#enter sib2, iclass 39, count 0 2006.257.01:32:52.20#ibcon#flushed, iclass 39, count 0 2006.257.01:32:52.20#ibcon#about to write, iclass 39, count 0 2006.257.01:32:52.20#ibcon#wrote, iclass 39, count 0 2006.257.01:32:52.20#ibcon#about to read 3, iclass 39, count 0 2006.257.01:32:52.23#ibcon#read 3, iclass 39, count 0 2006.257.01:32:52.23#ibcon#about to read 4, iclass 39, count 0 2006.257.01:32:52.23#ibcon#read 4, iclass 39, count 0 2006.257.01:32:52.23#ibcon#about to read 5, iclass 39, count 0 2006.257.01:32:52.23#ibcon#read 5, iclass 39, count 0 2006.257.01:32:52.23#ibcon#about to read 6, iclass 39, count 0 2006.257.01:32:52.23#ibcon#read 6, iclass 39, count 0 2006.257.01:32:52.23#ibcon#end of sib2, iclass 39, count 0 2006.257.01:32:52.23#ibcon#*after write, iclass 39, count 0 2006.257.01:32:52.23#ibcon#*before return 0, iclass 39, count 0 2006.257.01:32:52.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:52.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:52.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.01:32:52.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.01:32:52.23$vck44/valo=5,734.99 2006.257.01:32:52.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.01:32:52.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.01:32:52.23#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:52.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:52.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:52.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:52.23#ibcon#enter wrdev, iclass 3, count 0 2006.257.01:32:52.23#ibcon#first serial, iclass 3, count 0 2006.257.01:32:52.23#ibcon#enter sib2, iclass 3, count 0 2006.257.01:32:52.23#ibcon#flushed, iclass 3, count 0 2006.257.01:32:52.23#ibcon#about to write, iclass 3, count 0 2006.257.01:32:52.23#ibcon#wrote, iclass 3, count 0 2006.257.01:32:52.23#ibcon#about to read 3, iclass 3, count 0 2006.257.01:32:52.25#ibcon#read 3, iclass 3, count 0 2006.257.01:32:52.25#ibcon#about to read 4, iclass 3, count 0 2006.257.01:32:52.25#ibcon#read 4, iclass 3, count 0 2006.257.01:32:52.25#ibcon#about to read 5, iclass 3, count 0 2006.257.01:32:52.25#ibcon#read 5, iclass 3, count 0 2006.257.01:32:52.25#ibcon#about to read 6, iclass 3, count 0 2006.257.01:32:52.25#ibcon#read 6, iclass 3, count 0 2006.257.01:32:52.25#ibcon#end of sib2, iclass 3, count 0 2006.257.01:32:52.25#ibcon#*mode == 0, iclass 3, count 0 2006.257.01:32:52.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.01:32:52.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.01:32:52.25#ibcon#*before write, iclass 3, count 0 2006.257.01:32:52.25#ibcon#enter sib2, iclass 3, count 0 2006.257.01:32:52.25#ibcon#flushed, iclass 3, count 0 2006.257.01:32:52.25#ibcon#about to write, iclass 3, count 0 2006.257.01:32:52.25#ibcon#wrote, iclass 3, count 0 2006.257.01:32:52.25#ibcon#about to read 3, iclass 3, count 0 2006.257.01:32:52.29#ibcon#read 3, iclass 3, count 0 2006.257.01:32:52.29#ibcon#about to read 4, iclass 3, count 0 2006.257.01:32:52.29#ibcon#read 4, iclass 3, count 0 2006.257.01:32:52.29#ibcon#about to read 5, iclass 3, count 0 2006.257.01:32:52.29#ibcon#read 5, iclass 3, count 0 2006.257.01:32:52.29#ibcon#about to read 6, iclass 3, count 0 2006.257.01:32:52.29#ibcon#read 6, iclass 3, count 0 2006.257.01:32:52.29#ibcon#end of sib2, iclass 3, count 0 2006.257.01:32:52.29#ibcon#*after write, iclass 3, count 0 2006.257.01:32:52.29#ibcon#*before return 0, iclass 3, count 0 2006.257.01:32:52.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:52.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:52.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.01:32:52.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.01:32:52.29$vck44/va=5,4 2006.257.01:32:52.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.01:32:52.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.01:32:52.29#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:52.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:52.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:52.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:52.35#ibcon#enter wrdev, iclass 5, count 2 2006.257.01:32:52.35#ibcon#first serial, iclass 5, count 2 2006.257.01:32:52.35#ibcon#enter sib2, iclass 5, count 2 2006.257.01:32:52.35#ibcon#flushed, iclass 5, count 2 2006.257.01:32:52.35#ibcon#about to write, iclass 5, count 2 2006.257.01:32:52.35#ibcon#wrote, iclass 5, count 2 2006.257.01:32:52.35#ibcon#about to read 3, iclass 5, count 2 2006.257.01:32:52.37#ibcon#read 3, iclass 5, count 2 2006.257.01:32:52.37#ibcon#about to read 4, iclass 5, count 2 2006.257.01:32:52.37#ibcon#read 4, iclass 5, count 2 2006.257.01:32:52.37#ibcon#about to read 5, iclass 5, count 2 2006.257.01:32:52.37#ibcon#read 5, iclass 5, count 2 2006.257.01:32:52.37#ibcon#about to read 6, iclass 5, count 2 2006.257.01:32:52.37#ibcon#read 6, iclass 5, count 2 2006.257.01:32:52.37#ibcon#end of sib2, iclass 5, count 2 2006.257.01:32:52.37#ibcon#*mode == 0, iclass 5, count 2 2006.257.01:32:52.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.01:32:52.37#ibcon#[25=AT05-04\r\n] 2006.257.01:32:52.37#ibcon#*before write, iclass 5, count 2 2006.257.01:32:52.37#ibcon#enter sib2, iclass 5, count 2 2006.257.01:32:52.37#ibcon#flushed, iclass 5, count 2 2006.257.01:32:52.37#ibcon#about to write, iclass 5, count 2 2006.257.01:32:52.37#ibcon#wrote, iclass 5, count 2 2006.257.01:32:52.37#ibcon#about to read 3, iclass 5, count 2 2006.257.01:32:52.40#ibcon#read 3, iclass 5, count 2 2006.257.01:32:52.40#ibcon#about to read 4, iclass 5, count 2 2006.257.01:32:52.40#ibcon#read 4, iclass 5, count 2 2006.257.01:32:52.40#ibcon#about to read 5, iclass 5, count 2 2006.257.01:32:52.40#ibcon#read 5, iclass 5, count 2 2006.257.01:32:52.40#ibcon#about to read 6, iclass 5, count 2 2006.257.01:32:52.40#ibcon#read 6, iclass 5, count 2 2006.257.01:32:52.40#ibcon#end of sib2, iclass 5, count 2 2006.257.01:32:52.40#ibcon#*after write, iclass 5, count 2 2006.257.01:32:52.40#ibcon#*before return 0, iclass 5, count 2 2006.257.01:32:52.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:52.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:52.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.01:32:52.40#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:52.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:52.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:52.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:52.52#ibcon#enter wrdev, iclass 5, count 0 2006.257.01:32:52.52#ibcon#first serial, iclass 5, count 0 2006.257.01:32:52.52#ibcon#enter sib2, iclass 5, count 0 2006.257.01:32:52.52#ibcon#flushed, iclass 5, count 0 2006.257.01:32:52.52#ibcon#about to write, iclass 5, count 0 2006.257.01:32:52.52#ibcon#wrote, iclass 5, count 0 2006.257.01:32:52.52#ibcon#about to read 3, iclass 5, count 0 2006.257.01:32:52.54#ibcon#read 3, iclass 5, count 0 2006.257.01:32:52.54#ibcon#about to read 4, iclass 5, count 0 2006.257.01:32:52.54#ibcon#read 4, iclass 5, count 0 2006.257.01:32:52.54#ibcon#about to read 5, iclass 5, count 0 2006.257.01:32:52.54#ibcon#read 5, iclass 5, count 0 2006.257.01:32:52.54#ibcon#about to read 6, iclass 5, count 0 2006.257.01:32:52.54#ibcon#read 6, iclass 5, count 0 2006.257.01:32:52.54#ibcon#end of sib2, iclass 5, count 0 2006.257.01:32:52.54#ibcon#*mode == 0, iclass 5, count 0 2006.257.01:32:52.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.01:32:52.54#ibcon#[25=USB\r\n] 2006.257.01:32:52.54#ibcon#*before write, iclass 5, count 0 2006.257.01:32:52.54#ibcon#enter sib2, iclass 5, count 0 2006.257.01:32:52.54#ibcon#flushed, iclass 5, count 0 2006.257.01:32:52.54#ibcon#about to write, iclass 5, count 0 2006.257.01:32:52.54#ibcon#wrote, iclass 5, count 0 2006.257.01:32:52.54#ibcon#about to read 3, iclass 5, count 0 2006.257.01:32:52.57#ibcon#read 3, iclass 5, count 0 2006.257.01:32:52.57#ibcon#about to read 4, iclass 5, count 0 2006.257.01:32:52.57#ibcon#read 4, iclass 5, count 0 2006.257.01:32:52.57#ibcon#about to read 5, iclass 5, count 0 2006.257.01:32:52.57#ibcon#read 5, iclass 5, count 0 2006.257.01:32:52.57#ibcon#about to read 6, iclass 5, count 0 2006.257.01:32:52.57#ibcon#read 6, iclass 5, count 0 2006.257.01:32:52.57#ibcon#end of sib2, iclass 5, count 0 2006.257.01:32:52.57#ibcon#*after write, iclass 5, count 0 2006.257.01:32:52.57#ibcon#*before return 0, iclass 5, count 0 2006.257.01:32:52.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:52.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:52.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.01:32:52.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.01:32:52.57$vck44/valo=6,814.99 2006.257.01:32:52.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.01:32:52.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.01:32:52.57#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:52.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:52.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:52.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:52.57#ibcon#enter wrdev, iclass 7, count 0 2006.257.01:32:52.57#ibcon#first serial, iclass 7, count 0 2006.257.01:32:52.57#ibcon#enter sib2, iclass 7, count 0 2006.257.01:32:52.57#ibcon#flushed, iclass 7, count 0 2006.257.01:32:52.57#ibcon#about to write, iclass 7, count 0 2006.257.01:32:52.57#ibcon#wrote, iclass 7, count 0 2006.257.01:32:52.57#ibcon#about to read 3, iclass 7, count 0 2006.257.01:32:52.59#ibcon#read 3, iclass 7, count 0 2006.257.01:32:52.59#ibcon#about to read 4, iclass 7, count 0 2006.257.01:32:52.59#ibcon#read 4, iclass 7, count 0 2006.257.01:32:52.59#ibcon#about to read 5, iclass 7, count 0 2006.257.01:32:52.59#ibcon#read 5, iclass 7, count 0 2006.257.01:32:52.59#ibcon#about to read 6, iclass 7, count 0 2006.257.01:32:52.59#ibcon#read 6, iclass 7, count 0 2006.257.01:32:52.59#ibcon#end of sib2, iclass 7, count 0 2006.257.01:32:52.59#ibcon#*mode == 0, iclass 7, count 0 2006.257.01:32:52.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.01:32:52.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.01:32:52.59#ibcon#*before write, iclass 7, count 0 2006.257.01:32:52.59#ibcon#enter sib2, iclass 7, count 0 2006.257.01:32:52.59#ibcon#flushed, iclass 7, count 0 2006.257.01:32:52.59#ibcon#about to write, iclass 7, count 0 2006.257.01:32:52.59#ibcon#wrote, iclass 7, count 0 2006.257.01:32:52.59#ibcon#about to read 3, iclass 7, count 0 2006.257.01:32:52.63#ibcon#read 3, iclass 7, count 0 2006.257.01:32:52.63#ibcon#about to read 4, iclass 7, count 0 2006.257.01:32:52.63#ibcon#read 4, iclass 7, count 0 2006.257.01:32:52.63#ibcon#about to read 5, iclass 7, count 0 2006.257.01:32:52.63#ibcon#read 5, iclass 7, count 0 2006.257.01:32:52.63#ibcon#about to read 6, iclass 7, count 0 2006.257.01:32:52.63#ibcon#read 6, iclass 7, count 0 2006.257.01:32:52.63#ibcon#end of sib2, iclass 7, count 0 2006.257.01:32:52.63#ibcon#*after write, iclass 7, count 0 2006.257.01:32:52.63#ibcon#*before return 0, iclass 7, count 0 2006.257.01:32:52.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:52.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:52.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.01:32:52.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.01:32:52.63$vck44/va=6,4 2006.257.01:32:52.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.01:32:52.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.01:32:52.63#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:52.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:52.68#abcon#<5=/15 1.5 4.1 17.581001013.0\r\n> 2006.257.01:32:52.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:52.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:52.69#ibcon#enter wrdev, iclass 11, count 2 2006.257.01:32:52.69#ibcon#first serial, iclass 11, count 2 2006.257.01:32:52.69#ibcon#enter sib2, iclass 11, count 2 2006.257.01:32:52.69#ibcon#flushed, iclass 11, count 2 2006.257.01:32:52.69#ibcon#about to write, iclass 11, count 2 2006.257.01:32:52.69#ibcon#wrote, iclass 11, count 2 2006.257.01:32:52.69#ibcon#about to read 3, iclass 11, count 2 2006.257.01:32:52.70#abcon#{5=INTERFACE CLEAR} 2006.257.01:32:52.71#ibcon#read 3, iclass 11, count 2 2006.257.01:32:52.71#ibcon#about to read 4, iclass 11, count 2 2006.257.01:32:52.71#ibcon#read 4, iclass 11, count 2 2006.257.01:32:52.71#ibcon#about to read 5, iclass 11, count 2 2006.257.01:32:52.71#ibcon#read 5, iclass 11, count 2 2006.257.01:32:52.71#ibcon#about to read 6, iclass 11, count 2 2006.257.01:32:52.71#ibcon#read 6, iclass 11, count 2 2006.257.01:32:52.71#ibcon#end of sib2, iclass 11, count 2 2006.257.01:32:52.71#ibcon#*mode == 0, iclass 11, count 2 2006.257.01:32:52.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.01:32:52.71#ibcon#[25=AT06-04\r\n] 2006.257.01:32:52.71#ibcon#*before write, iclass 11, count 2 2006.257.01:32:52.71#ibcon#enter sib2, iclass 11, count 2 2006.257.01:32:52.71#ibcon#flushed, iclass 11, count 2 2006.257.01:32:52.71#ibcon#about to write, iclass 11, count 2 2006.257.01:32:52.71#ibcon#wrote, iclass 11, count 2 2006.257.01:32:52.71#ibcon#about to read 3, iclass 11, count 2 2006.257.01:32:52.74#ibcon#read 3, iclass 11, count 2 2006.257.01:32:52.74#ibcon#about to read 4, iclass 11, count 2 2006.257.01:32:52.74#ibcon#read 4, iclass 11, count 2 2006.257.01:32:52.74#ibcon#about to read 5, iclass 11, count 2 2006.257.01:32:52.74#ibcon#read 5, iclass 11, count 2 2006.257.01:32:52.74#ibcon#about to read 6, iclass 11, count 2 2006.257.01:32:52.74#ibcon#read 6, iclass 11, count 2 2006.257.01:32:52.74#ibcon#end of sib2, iclass 11, count 2 2006.257.01:32:52.74#ibcon#*after write, iclass 11, count 2 2006.257.01:32:52.74#ibcon#*before return 0, iclass 11, count 2 2006.257.01:32:52.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:52.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:52.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.01:32:52.74#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:52.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:52.76#abcon#[5=S1D000X0/0*\r\n] 2006.257.01:32:52.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:52.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:52.86#ibcon#enter wrdev, iclass 11, count 0 2006.257.01:32:52.86#ibcon#first serial, iclass 11, count 0 2006.257.01:32:52.86#ibcon#enter sib2, iclass 11, count 0 2006.257.01:32:52.86#ibcon#flushed, iclass 11, count 0 2006.257.01:32:52.86#ibcon#about to write, iclass 11, count 0 2006.257.01:32:52.86#ibcon#wrote, iclass 11, count 0 2006.257.01:32:52.86#ibcon#about to read 3, iclass 11, count 0 2006.257.01:32:52.88#ibcon#read 3, iclass 11, count 0 2006.257.01:32:52.88#ibcon#about to read 4, iclass 11, count 0 2006.257.01:32:52.88#ibcon#read 4, iclass 11, count 0 2006.257.01:32:52.88#ibcon#about to read 5, iclass 11, count 0 2006.257.01:32:52.88#ibcon#read 5, iclass 11, count 0 2006.257.01:32:52.88#ibcon#about to read 6, iclass 11, count 0 2006.257.01:32:52.88#ibcon#read 6, iclass 11, count 0 2006.257.01:32:52.88#ibcon#end of sib2, iclass 11, count 0 2006.257.01:32:52.88#ibcon#*mode == 0, iclass 11, count 0 2006.257.01:32:52.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.01:32:52.88#ibcon#[25=USB\r\n] 2006.257.01:32:52.88#ibcon#*before write, iclass 11, count 0 2006.257.01:32:52.88#ibcon#enter sib2, iclass 11, count 0 2006.257.01:32:52.88#ibcon#flushed, iclass 11, count 0 2006.257.01:32:52.88#ibcon#about to write, iclass 11, count 0 2006.257.01:32:52.88#ibcon#wrote, iclass 11, count 0 2006.257.01:32:52.88#ibcon#about to read 3, iclass 11, count 0 2006.257.01:32:52.91#ibcon#read 3, iclass 11, count 0 2006.257.01:32:52.91#ibcon#about to read 4, iclass 11, count 0 2006.257.01:32:52.91#ibcon#read 4, iclass 11, count 0 2006.257.01:32:52.91#ibcon#about to read 5, iclass 11, count 0 2006.257.01:32:52.91#ibcon#read 5, iclass 11, count 0 2006.257.01:32:52.91#ibcon#about to read 6, iclass 11, count 0 2006.257.01:32:52.91#ibcon#read 6, iclass 11, count 0 2006.257.01:32:52.91#ibcon#end of sib2, iclass 11, count 0 2006.257.01:32:52.91#ibcon#*after write, iclass 11, count 0 2006.257.01:32:52.91#ibcon#*before return 0, iclass 11, count 0 2006.257.01:32:52.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:52.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:52.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.01:32:52.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.01:32:52.91$vck44/valo=7,864.99 2006.257.01:32:52.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.01:32:52.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.01:32:52.91#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:52.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:52.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:52.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:52.91#ibcon#enter wrdev, iclass 17, count 0 2006.257.01:32:52.91#ibcon#first serial, iclass 17, count 0 2006.257.01:32:52.91#ibcon#enter sib2, iclass 17, count 0 2006.257.01:32:52.91#ibcon#flushed, iclass 17, count 0 2006.257.01:32:52.91#ibcon#about to write, iclass 17, count 0 2006.257.01:32:52.91#ibcon#wrote, iclass 17, count 0 2006.257.01:32:52.91#ibcon#about to read 3, iclass 17, count 0 2006.257.01:32:52.93#ibcon#read 3, iclass 17, count 0 2006.257.01:32:52.93#ibcon#about to read 4, iclass 17, count 0 2006.257.01:32:52.93#ibcon#read 4, iclass 17, count 0 2006.257.01:32:52.93#ibcon#about to read 5, iclass 17, count 0 2006.257.01:32:52.93#ibcon#read 5, iclass 17, count 0 2006.257.01:32:52.93#ibcon#about to read 6, iclass 17, count 0 2006.257.01:32:52.93#ibcon#read 6, iclass 17, count 0 2006.257.01:32:52.93#ibcon#end of sib2, iclass 17, count 0 2006.257.01:32:52.93#ibcon#*mode == 0, iclass 17, count 0 2006.257.01:32:52.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.01:32:52.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.01:32:52.93#ibcon#*before write, iclass 17, count 0 2006.257.01:32:52.93#ibcon#enter sib2, iclass 17, count 0 2006.257.01:32:52.93#ibcon#flushed, iclass 17, count 0 2006.257.01:32:52.93#ibcon#about to write, iclass 17, count 0 2006.257.01:32:52.93#ibcon#wrote, iclass 17, count 0 2006.257.01:32:52.93#ibcon#about to read 3, iclass 17, count 0 2006.257.01:32:52.97#ibcon#read 3, iclass 17, count 0 2006.257.01:32:52.97#ibcon#about to read 4, iclass 17, count 0 2006.257.01:32:52.97#ibcon#read 4, iclass 17, count 0 2006.257.01:32:52.97#ibcon#about to read 5, iclass 17, count 0 2006.257.01:32:52.97#ibcon#read 5, iclass 17, count 0 2006.257.01:32:52.97#ibcon#about to read 6, iclass 17, count 0 2006.257.01:32:52.97#ibcon#read 6, iclass 17, count 0 2006.257.01:32:52.97#ibcon#end of sib2, iclass 17, count 0 2006.257.01:32:52.97#ibcon#*after write, iclass 17, count 0 2006.257.01:32:52.97#ibcon#*before return 0, iclass 17, count 0 2006.257.01:32:52.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:52.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:52.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.01:32:52.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.01:32:52.97$vck44/va=7,4 2006.257.01:32:52.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.01:32:52.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.01:32:52.97#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:52.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:53.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:53.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:53.03#ibcon#enter wrdev, iclass 19, count 2 2006.257.01:32:53.03#ibcon#first serial, iclass 19, count 2 2006.257.01:32:53.03#ibcon#enter sib2, iclass 19, count 2 2006.257.01:32:53.03#ibcon#flushed, iclass 19, count 2 2006.257.01:32:53.03#ibcon#about to write, iclass 19, count 2 2006.257.01:32:53.03#ibcon#wrote, iclass 19, count 2 2006.257.01:32:53.03#ibcon#about to read 3, iclass 19, count 2 2006.257.01:32:53.05#ibcon#read 3, iclass 19, count 2 2006.257.01:32:53.05#ibcon#about to read 4, iclass 19, count 2 2006.257.01:32:53.05#ibcon#read 4, iclass 19, count 2 2006.257.01:32:53.05#ibcon#about to read 5, iclass 19, count 2 2006.257.01:32:53.05#ibcon#read 5, iclass 19, count 2 2006.257.01:32:53.05#ibcon#about to read 6, iclass 19, count 2 2006.257.01:32:53.05#ibcon#read 6, iclass 19, count 2 2006.257.01:32:53.05#ibcon#end of sib2, iclass 19, count 2 2006.257.01:32:53.05#ibcon#*mode == 0, iclass 19, count 2 2006.257.01:32:53.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.01:32:53.05#ibcon#[25=AT07-04\r\n] 2006.257.01:32:53.05#ibcon#*before write, iclass 19, count 2 2006.257.01:32:53.05#ibcon#enter sib2, iclass 19, count 2 2006.257.01:32:53.05#ibcon#flushed, iclass 19, count 2 2006.257.01:32:53.05#ibcon#about to write, iclass 19, count 2 2006.257.01:32:53.05#ibcon#wrote, iclass 19, count 2 2006.257.01:32:53.05#ibcon#about to read 3, iclass 19, count 2 2006.257.01:32:53.08#ibcon#read 3, iclass 19, count 2 2006.257.01:32:53.08#ibcon#about to read 4, iclass 19, count 2 2006.257.01:32:53.08#ibcon#read 4, iclass 19, count 2 2006.257.01:32:53.08#ibcon#about to read 5, iclass 19, count 2 2006.257.01:32:53.08#ibcon#read 5, iclass 19, count 2 2006.257.01:32:53.08#ibcon#about to read 6, iclass 19, count 2 2006.257.01:32:53.08#ibcon#read 6, iclass 19, count 2 2006.257.01:32:53.08#ibcon#end of sib2, iclass 19, count 2 2006.257.01:32:53.08#ibcon#*after write, iclass 19, count 2 2006.257.01:32:53.08#ibcon#*before return 0, iclass 19, count 2 2006.257.01:32:53.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:53.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:53.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.01:32:53.08#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:53.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:53.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:53.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:53.20#ibcon#enter wrdev, iclass 19, count 0 2006.257.01:32:53.20#ibcon#first serial, iclass 19, count 0 2006.257.01:32:53.20#ibcon#enter sib2, iclass 19, count 0 2006.257.01:32:53.20#ibcon#flushed, iclass 19, count 0 2006.257.01:32:53.20#ibcon#about to write, iclass 19, count 0 2006.257.01:32:53.20#ibcon#wrote, iclass 19, count 0 2006.257.01:32:53.20#ibcon#about to read 3, iclass 19, count 0 2006.257.01:32:53.22#ibcon#read 3, iclass 19, count 0 2006.257.01:32:53.22#ibcon#about to read 4, iclass 19, count 0 2006.257.01:32:53.22#ibcon#read 4, iclass 19, count 0 2006.257.01:32:53.22#ibcon#about to read 5, iclass 19, count 0 2006.257.01:32:53.22#ibcon#read 5, iclass 19, count 0 2006.257.01:32:53.22#ibcon#about to read 6, iclass 19, count 0 2006.257.01:32:53.22#ibcon#read 6, iclass 19, count 0 2006.257.01:32:53.22#ibcon#end of sib2, iclass 19, count 0 2006.257.01:32:53.22#ibcon#*mode == 0, iclass 19, count 0 2006.257.01:32:53.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.01:32:53.22#ibcon#[25=USB\r\n] 2006.257.01:32:53.22#ibcon#*before write, iclass 19, count 0 2006.257.01:32:53.22#ibcon#enter sib2, iclass 19, count 0 2006.257.01:32:53.22#ibcon#flushed, iclass 19, count 0 2006.257.01:32:53.22#ibcon#about to write, iclass 19, count 0 2006.257.01:32:53.22#ibcon#wrote, iclass 19, count 0 2006.257.01:32:53.22#ibcon#about to read 3, iclass 19, count 0 2006.257.01:32:53.25#ibcon#read 3, iclass 19, count 0 2006.257.01:32:53.25#ibcon#about to read 4, iclass 19, count 0 2006.257.01:32:53.25#ibcon#read 4, iclass 19, count 0 2006.257.01:32:53.25#ibcon#about to read 5, iclass 19, count 0 2006.257.01:32:53.25#ibcon#read 5, iclass 19, count 0 2006.257.01:32:53.25#ibcon#about to read 6, iclass 19, count 0 2006.257.01:32:53.25#ibcon#read 6, iclass 19, count 0 2006.257.01:32:53.25#ibcon#end of sib2, iclass 19, count 0 2006.257.01:32:53.25#ibcon#*after write, iclass 19, count 0 2006.257.01:32:53.25#ibcon#*before return 0, iclass 19, count 0 2006.257.01:32:53.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:53.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:53.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.01:32:53.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.01:32:53.25$vck44/valo=8,884.99 2006.257.01:32:53.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.01:32:53.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.01:32:53.25#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:53.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:53.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:53.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:53.25#ibcon#enter wrdev, iclass 21, count 0 2006.257.01:32:53.25#ibcon#first serial, iclass 21, count 0 2006.257.01:32:53.25#ibcon#enter sib2, iclass 21, count 0 2006.257.01:32:53.25#ibcon#flushed, iclass 21, count 0 2006.257.01:32:53.25#ibcon#about to write, iclass 21, count 0 2006.257.01:32:53.25#ibcon#wrote, iclass 21, count 0 2006.257.01:32:53.25#ibcon#about to read 3, iclass 21, count 0 2006.257.01:32:53.27#ibcon#read 3, iclass 21, count 0 2006.257.01:32:53.27#ibcon#about to read 4, iclass 21, count 0 2006.257.01:32:53.27#ibcon#read 4, iclass 21, count 0 2006.257.01:32:53.27#ibcon#about to read 5, iclass 21, count 0 2006.257.01:32:53.27#ibcon#read 5, iclass 21, count 0 2006.257.01:32:53.27#ibcon#about to read 6, iclass 21, count 0 2006.257.01:32:53.27#ibcon#read 6, iclass 21, count 0 2006.257.01:32:53.27#ibcon#end of sib2, iclass 21, count 0 2006.257.01:32:53.27#ibcon#*mode == 0, iclass 21, count 0 2006.257.01:32:53.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.01:32:53.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.01:32:53.27#ibcon#*before write, iclass 21, count 0 2006.257.01:32:53.27#ibcon#enter sib2, iclass 21, count 0 2006.257.01:32:53.27#ibcon#flushed, iclass 21, count 0 2006.257.01:32:53.27#ibcon#about to write, iclass 21, count 0 2006.257.01:32:53.27#ibcon#wrote, iclass 21, count 0 2006.257.01:32:53.27#ibcon#about to read 3, iclass 21, count 0 2006.257.01:32:53.31#ibcon#read 3, iclass 21, count 0 2006.257.01:32:53.31#ibcon#about to read 4, iclass 21, count 0 2006.257.01:32:53.31#ibcon#read 4, iclass 21, count 0 2006.257.01:32:53.31#ibcon#about to read 5, iclass 21, count 0 2006.257.01:32:53.31#ibcon#read 5, iclass 21, count 0 2006.257.01:32:53.31#ibcon#about to read 6, iclass 21, count 0 2006.257.01:32:53.31#ibcon#read 6, iclass 21, count 0 2006.257.01:32:53.31#ibcon#end of sib2, iclass 21, count 0 2006.257.01:32:53.31#ibcon#*after write, iclass 21, count 0 2006.257.01:32:53.31#ibcon#*before return 0, iclass 21, count 0 2006.257.01:32:53.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:53.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:53.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.01:32:53.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.01:32:53.31$vck44/va=8,4 2006.257.01:32:53.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.01:32:53.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.01:32:53.31#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:53.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.01:32:53.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.01:32:53.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.01:32:53.37#ibcon#enter wrdev, iclass 23, count 2 2006.257.01:32:53.37#ibcon#first serial, iclass 23, count 2 2006.257.01:32:53.37#ibcon#enter sib2, iclass 23, count 2 2006.257.01:32:53.37#ibcon#flushed, iclass 23, count 2 2006.257.01:32:53.37#ibcon#about to write, iclass 23, count 2 2006.257.01:32:53.37#ibcon#wrote, iclass 23, count 2 2006.257.01:32:53.37#ibcon#about to read 3, iclass 23, count 2 2006.257.01:32:53.39#ibcon#read 3, iclass 23, count 2 2006.257.01:32:53.39#ibcon#about to read 4, iclass 23, count 2 2006.257.01:32:53.39#ibcon#read 4, iclass 23, count 2 2006.257.01:32:53.39#ibcon#about to read 5, iclass 23, count 2 2006.257.01:32:53.39#ibcon#read 5, iclass 23, count 2 2006.257.01:32:53.39#ibcon#about to read 6, iclass 23, count 2 2006.257.01:32:53.39#ibcon#read 6, iclass 23, count 2 2006.257.01:32:53.39#ibcon#end of sib2, iclass 23, count 2 2006.257.01:32:53.39#ibcon#*mode == 0, iclass 23, count 2 2006.257.01:32:53.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.01:32:53.39#ibcon#[25=AT08-04\r\n] 2006.257.01:32:53.39#ibcon#*before write, iclass 23, count 2 2006.257.01:32:53.39#ibcon#enter sib2, iclass 23, count 2 2006.257.01:32:53.39#ibcon#flushed, iclass 23, count 2 2006.257.01:32:53.39#ibcon#about to write, iclass 23, count 2 2006.257.01:32:53.39#ibcon#wrote, iclass 23, count 2 2006.257.01:32:53.39#ibcon#about to read 3, iclass 23, count 2 2006.257.01:32:53.42#ibcon#read 3, iclass 23, count 2 2006.257.01:32:53.42#ibcon#about to read 4, iclass 23, count 2 2006.257.01:32:53.42#ibcon#read 4, iclass 23, count 2 2006.257.01:32:53.42#ibcon#about to read 5, iclass 23, count 2 2006.257.01:32:53.42#ibcon#read 5, iclass 23, count 2 2006.257.01:32:53.42#ibcon#about to read 6, iclass 23, count 2 2006.257.01:32:53.42#ibcon#read 6, iclass 23, count 2 2006.257.01:32:53.42#ibcon#end of sib2, iclass 23, count 2 2006.257.01:32:53.42#ibcon#*after write, iclass 23, count 2 2006.257.01:32:53.42#ibcon#*before return 0, iclass 23, count 2 2006.257.01:32:53.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.01:32:53.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.01:32:53.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.01:32:53.42#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:53.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.01:32:53.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.01:32:53.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.01:32:53.54#ibcon#enter wrdev, iclass 23, count 0 2006.257.01:32:53.54#ibcon#first serial, iclass 23, count 0 2006.257.01:32:53.54#ibcon#enter sib2, iclass 23, count 0 2006.257.01:32:53.54#ibcon#flushed, iclass 23, count 0 2006.257.01:32:53.54#ibcon#about to write, iclass 23, count 0 2006.257.01:32:53.54#ibcon#wrote, iclass 23, count 0 2006.257.01:32:53.54#ibcon#about to read 3, iclass 23, count 0 2006.257.01:32:53.56#ibcon#read 3, iclass 23, count 0 2006.257.01:32:53.56#ibcon#about to read 4, iclass 23, count 0 2006.257.01:32:53.56#ibcon#read 4, iclass 23, count 0 2006.257.01:32:53.56#ibcon#about to read 5, iclass 23, count 0 2006.257.01:32:53.56#ibcon#read 5, iclass 23, count 0 2006.257.01:32:53.56#ibcon#about to read 6, iclass 23, count 0 2006.257.01:32:53.56#ibcon#read 6, iclass 23, count 0 2006.257.01:32:53.56#ibcon#end of sib2, iclass 23, count 0 2006.257.01:32:53.56#ibcon#*mode == 0, iclass 23, count 0 2006.257.01:32:53.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.01:32:53.56#ibcon#[25=USB\r\n] 2006.257.01:32:53.56#ibcon#*before write, iclass 23, count 0 2006.257.01:32:53.56#ibcon#enter sib2, iclass 23, count 0 2006.257.01:32:53.56#ibcon#flushed, iclass 23, count 0 2006.257.01:32:53.56#ibcon#about to write, iclass 23, count 0 2006.257.01:32:53.56#ibcon#wrote, iclass 23, count 0 2006.257.01:32:53.56#ibcon#about to read 3, iclass 23, count 0 2006.257.01:32:53.59#ibcon#read 3, iclass 23, count 0 2006.257.01:32:53.59#ibcon#about to read 4, iclass 23, count 0 2006.257.01:32:53.59#ibcon#read 4, iclass 23, count 0 2006.257.01:32:53.59#ibcon#about to read 5, iclass 23, count 0 2006.257.01:32:53.59#ibcon#read 5, iclass 23, count 0 2006.257.01:32:53.59#ibcon#about to read 6, iclass 23, count 0 2006.257.01:32:53.59#ibcon#read 6, iclass 23, count 0 2006.257.01:32:53.59#ibcon#end of sib2, iclass 23, count 0 2006.257.01:32:53.59#ibcon#*after write, iclass 23, count 0 2006.257.01:32:53.59#ibcon#*before return 0, iclass 23, count 0 2006.257.01:32:53.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.01:32:53.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.01:32:53.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.01:32:53.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.01:32:53.59$vck44/vblo=1,629.99 2006.257.01:32:53.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.01:32:53.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.01:32:53.59#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:53.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:53.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:53.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:53.59#ibcon#enter wrdev, iclass 25, count 0 2006.257.01:32:53.59#ibcon#first serial, iclass 25, count 0 2006.257.01:32:53.59#ibcon#enter sib2, iclass 25, count 0 2006.257.01:32:53.59#ibcon#flushed, iclass 25, count 0 2006.257.01:32:53.59#ibcon#about to write, iclass 25, count 0 2006.257.01:32:53.59#ibcon#wrote, iclass 25, count 0 2006.257.01:32:53.59#ibcon#about to read 3, iclass 25, count 0 2006.257.01:32:53.61#ibcon#read 3, iclass 25, count 0 2006.257.01:32:53.61#ibcon#about to read 4, iclass 25, count 0 2006.257.01:32:53.61#ibcon#read 4, iclass 25, count 0 2006.257.01:32:53.61#ibcon#about to read 5, iclass 25, count 0 2006.257.01:32:53.61#ibcon#read 5, iclass 25, count 0 2006.257.01:32:53.61#ibcon#about to read 6, iclass 25, count 0 2006.257.01:32:53.61#ibcon#read 6, iclass 25, count 0 2006.257.01:32:53.61#ibcon#end of sib2, iclass 25, count 0 2006.257.01:32:53.61#ibcon#*mode == 0, iclass 25, count 0 2006.257.01:32:53.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.01:32:53.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.01:32:53.61#ibcon#*before write, iclass 25, count 0 2006.257.01:32:53.61#ibcon#enter sib2, iclass 25, count 0 2006.257.01:32:53.61#ibcon#flushed, iclass 25, count 0 2006.257.01:32:53.61#ibcon#about to write, iclass 25, count 0 2006.257.01:32:53.61#ibcon#wrote, iclass 25, count 0 2006.257.01:32:53.61#ibcon#about to read 3, iclass 25, count 0 2006.257.01:32:53.67#ibcon#read 3, iclass 25, count 0 2006.257.01:32:53.67#ibcon#about to read 4, iclass 25, count 0 2006.257.01:32:53.67#ibcon#read 4, iclass 25, count 0 2006.257.01:32:53.67#ibcon#about to read 5, iclass 25, count 0 2006.257.01:32:53.67#ibcon#read 5, iclass 25, count 0 2006.257.01:32:53.67#ibcon#about to read 6, iclass 25, count 0 2006.257.01:32:53.67#ibcon#read 6, iclass 25, count 0 2006.257.01:32:53.67#ibcon#end of sib2, iclass 25, count 0 2006.257.01:32:53.67#ibcon#*after write, iclass 25, count 0 2006.257.01:32:53.67#ibcon#*before return 0, iclass 25, count 0 2006.257.01:32:53.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:53.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.01:32:53.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.01:32:53.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.01:32:53.67$vck44/vb=1,4 2006.257.01:32:53.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.01:32:53.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.01:32:53.67#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:53.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:53.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:53.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:53.67#ibcon#enter wrdev, iclass 27, count 2 2006.257.01:32:53.67#ibcon#first serial, iclass 27, count 2 2006.257.01:32:53.67#ibcon#enter sib2, iclass 27, count 2 2006.257.01:32:53.67#ibcon#flushed, iclass 27, count 2 2006.257.01:32:53.67#ibcon#about to write, iclass 27, count 2 2006.257.01:32:53.67#ibcon#wrote, iclass 27, count 2 2006.257.01:32:53.67#ibcon#about to read 3, iclass 27, count 2 2006.257.01:32:53.69#ibcon#read 3, iclass 27, count 2 2006.257.01:32:53.69#ibcon#about to read 4, iclass 27, count 2 2006.257.01:32:53.69#ibcon#read 4, iclass 27, count 2 2006.257.01:32:53.69#ibcon#about to read 5, iclass 27, count 2 2006.257.01:32:53.69#ibcon#read 5, iclass 27, count 2 2006.257.01:32:53.69#ibcon#about to read 6, iclass 27, count 2 2006.257.01:32:53.69#ibcon#read 6, iclass 27, count 2 2006.257.01:32:53.69#ibcon#end of sib2, iclass 27, count 2 2006.257.01:32:53.69#ibcon#*mode == 0, iclass 27, count 2 2006.257.01:32:53.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.01:32:53.69#ibcon#[27=AT01-04\r\n] 2006.257.01:32:53.69#ibcon#*before write, iclass 27, count 2 2006.257.01:32:53.69#ibcon#enter sib2, iclass 27, count 2 2006.257.01:32:53.69#ibcon#flushed, iclass 27, count 2 2006.257.01:32:53.69#ibcon#about to write, iclass 27, count 2 2006.257.01:32:53.69#ibcon#wrote, iclass 27, count 2 2006.257.01:32:53.69#ibcon#about to read 3, iclass 27, count 2 2006.257.01:32:53.73#ibcon#read 3, iclass 27, count 2 2006.257.01:32:53.73#ibcon#about to read 4, iclass 27, count 2 2006.257.01:32:53.73#ibcon#read 4, iclass 27, count 2 2006.257.01:32:53.73#ibcon#about to read 5, iclass 27, count 2 2006.257.01:32:53.73#ibcon#read 5, iclass 27, count 2 2006.257.01:32:53.73#ibcon#about to read 6, iclass 27, count 2 2006.257.01:32:53.73#ibcon#read 6, iclass 27, count 2 2006.257.01:32:53.73#ibcon#end of sib2, iclass 27, count 2 2006.257.01:32:53.73#ibcon#*after write, iclass 27, count 2 2006.257.01:32:53.73#ibcon#*before return 0, iclass 27, count 2 2006.257.01:32:53.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:53.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.01:32:53.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.01:32:53.73#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:53.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:53.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:53.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:53.85#ibcon#enter wrdev, iclass 27, count 0 2006.257.01:32:53.85#ibcon#first serial, iclass 27, count 0 2006.257.01:32:53.85#ibcon#enter sib2, iclass 27, count 0 2006.257.01:32:53.85#ibcon#flushed, iclass 27, count 0 2006.257.01:32:53.85#ibcon#about to write, iclass 27, count 0 2006.257.01:32:53.85#ibcon#wrote, iclass 27, count 0 2006.257.01:32:53.85#ibcon#about to read 3, iclass 27, count 0 2006.257.01:32:53.87#ibcon#read 3, iclass 27, count 0 2006.257.01:32:53.87#ibcon#about to read 4, iclass 27, count 0 2006.257.01:32:53.87#ibcon#read 4, iclass 27, count 0 2006.257.01:32:53.87#ibcon#about to read 5, iclass 27, count 0 2006.257.01:32:53.87#ibcon#read 5, iclass 27, count 0 2006.257.01:32:53.87#ibcon#about to read 6, iclass 27, count 0 2006.257.01:32:53.87#ibcon#read 6, iclass 27, count 0 2006.257.01:32:53.87#ibcon#end of sib2, iclass 27, count 0 2006.257.01:32:53.87#ibcon#*mode == 0, iclass 27, count 0 2006.257.01:32:53.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.01:32:53.87#ibcon#[27=USB\r\n] 2006.257.01:32:53.87#ibcon#*before write, iclass 27, count 0 2006.257.01:32:53.87#ibcon#enter sib2, iclass 27, count 0 2006.257.01:32:53.87#ibcon#flushed, iclass 27, count 0 2006.257.01:32:53.87#ibcon#about to write, iclass 27, count 0 2006.257.01:32:53.87#ibcon#wrote, iclass 27, count 0 2006.257.01:32:53.87#ibcon#about to read 3, iclass 27, count 0 2006.257.01:32:53.90#ibcon#read 3, iclass 27, count 0 2006.257.01:32:53.90#ibcon#about to read 4, iclass 27, count 0 2006.257.01:32:53.90#ibcon#read 4, iclass 27, count 0 2006.257.01:32:53.90#ibcon#about to read 5, iclass 27, count 0 2006.257.01:32:53.90#ibcon#read 5, iclass 27, count 0 2006.257.01:32:53.90#ibcon#about to read 6, iclass 27, count 0 2006.257.01:32:53.90#ibcon#read 6, iclass 27, count 0 2006.257.01:32:53.90#ibcon#end of sib2, iclass 27, count 0 2006.257.01:32:53.90#ibcon#*after write, iclass 27, count 0 2006.257.01:32:53.90#ibcon#*before return 0, iclass 27, count 0 2006.257.01:32:53.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:53.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.01:32:53.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.01:32:53.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.01:32:53.90$vck44/vblo=2,634.99 2006.257.01:32:53.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.01:32:53.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.01:32:53.90#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:53.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:53.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:53.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:53.90#ibcon#enter wrdev, iclass 29, count 0 2006.257.01:32:53.90#ibcon#first serial, iclass 29, count 0 2006.257.01:32:53.90#ibcon#enter sib2, iclass 29, count 0 2006.257.01:32:53.90#ibcon#flushed, iclass 29, count 0 2006.257.01:32:53.90#ibcon#about to write, iclass 29, count 0 2006.257.01:32:53.90#ibcon#wrote, iclass 29, count 0 2006.257.01:32:53.90#ibcon#about to read 3, iclass 29, count 0 2006.257.01:32:53.92#ibcon#read 3, iclass 29, count 0 2006.257.01:32:53.92#ibcon#about to read 4, iclass 29, count 0 2006.257.01:32:53.92#ibcon#read 4, iclass 29, count 0 2006.257.01:32:53.92#ibcon#about to read 5, iclass 29, count 0 2006.257.01:32:53.92#ibcon#read 5, iclass 29, count 0 2006.257.01:32:53.92#ibcon#about to read 6, iclass 29, count 0 2006.257.01:32:53.92#ibcon#read 6, iclass 29, count 0 2006.257.01:32:53.92#ibcon#end of sib2, iclass 29, count 0 2006.257.01:32:53.92#ibcon#*mode == 0, iclass 29, count 0 2006.257.01:32:53.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.01:32:53.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.01:32:53.92#ibcon#*before write, iclass 29, count 0 2006.257.01:32:53.92#ibcon#enter sib2, iclass 29, count 0 2006.257.01:32:53.92#ibcon#flushed, iclass 29, count 0 2006.257.01:32:53.92#ibcon#about to write, iclass 29, count 0 2006.257.01:32:53.92#ibcon#wrote, iclass 29, count 0 2006.257.01:32:53.92#ibcon#about to read 3, iclass 29, count 0 2006.257.01:32:53.96#ibcon#read 3, iclass 29, count 0 2006.257.01:32:53.96#ibcon#about to read 4, iclass 29, count 0 2006.257.01:32:53.96#ibcon#read 4, iclass 29, count 0 2006.257.01:32:53.96#ibcon#about to read 5, iclass 29, count 0 2006.257.01:32:53.96#ibcon#read 5, iclass 29, count 0 2006.257.01:32:53.96#ibcon#about to read 6, iclass 29, count 0 2006.257.01:32:53.96#ibcon#read 6, iclass 29, count 0 2006.257.01:32:53.96#ibcon#end of sib2, iclass 29, count 0 2006.257.01:32:53.96#ibcon#*after write, iclass 29, count 0 2006.257.01:32:53.96#ibcon#*before return 0, iclass 29, count 0 2006.257.01:32:53.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:53.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.01:32:53.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.01:32:53.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.01:32:53.96$vck44/vb=2,5 2006.257.01:32:53.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.01:32:53.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.01:32:53.96#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:53.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:54.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:54.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:54.02#ibcon#enter wrdev, iclass 31, count 2 2006.257.01:32:54.02#ibcon#first serial, iclass 31, count 2 2006.257.01:32:54.02#ibcon#enter sib2, iclass 31, count 2 2006.257.01:32:54.02#ibcon#flushed, iclass 31, count 2 2006.257.01:32:54.02#ibcon#about to write, iclass 31, count 2 2006.257.01:32:54.02#ibcon#wrote, iclass 31, count 2 2006.257.01:32:54.02#ibcon#about to read 3, iclass 31, count 2 2006.257.01:32:54.04#ibcon#read 3, iclass 31, count 2 2006.257.01:32:54.04#ibcon#about to read 4, iclass 31, count 2 2006.257.01:32:54.04#ibcon#read 4, iclass 31, count 2 2006.257.01:32:54.04#ibcon#about to read 5, iclass 31, count 2 2006.257.01:32:54.04#ibcon#read 5, iclass 31, count 2 2006.257.01:32:54.04#ibcon#about to read 6, iclass 31, count 2 2006.257.01:32:54.04#ibcon#read 6, iclass 31, count 2 2006.257.01:32:54.04#ibcon#end of sib2, iclass 31, count 2 2006.257.01:32:54.04#ibcon#*mode == 0, iclass 31, count 2 2006.257.01:32:54.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.01:32:54.04#ibcon#[27=AT02-05\r\n] 2006.257.01:32:54.04#ibcon#*before write, iclass 31, count 2 2006.257.01:32:54.04#ibcon#enter sib2, iclass 31, count 2 2006.257.01:32:54.04#ibcon#flushed, iclass 31, count 2 2006.257.01:32:54.04#ibcon#about to write, iclass 31, count 2 2006.257.01:32:54.04#ibcon#wrote, iclass 31, count 2 2006.257.01:32:54.04#ibcon#about to read 3, iclass 31, count 2 2006.257.01:32:54.07#ibcon#read 3, iclass 31, count 2 2006.257.01:32:54.07#ibcon#about to read 4, iclass 31, count 2 2006.257.01:32:54.07#ibcon#read 4, iclass 31, count 2 2006.257.01:32:54.07#ibcon#about to read 5, iclass 31, count 2 2006.257.01:32:54.07#ibcon#read 5, iclass 31, count 2 2006.257.01:32:54.07#ibcon#about to read 6, iclass 31, count 2 2006.257.01:32:54.07#ibcon#read 6, iclass 31, count 2 2006.257.01:32:54.07#ibcon#end of sib2, iclass 31, count 2 2006.257.01:32:54.07#ibcon#*after write, iclass 31, count 2 2006.257.01:32:54.07#ibcon#*before return 0, iclass 31, count 2 2006.257.01:32:54.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:54.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.01:32:54.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.01:32:54.07#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:54.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:54.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:54.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:54.19#ibcon#enter wrdev, iclass 31, count 0 2006.257.01:32:54.19#ibcon#first serial, iclass 31, count 0 2006.257.01:32:54.19#ibcon#enter sib2, iclass 31, count 0 2006.257.01:32:54.19#ibcon#flushed, iclass 31, count 0 2006.257.01:32:54.19#ibcon#about to write, iclass 31, count 0 2006.257.01:32:54.19#ibcon#wrote, iclass 31, count 0 2006.257.01:32:54.19#ibcon#about to read 3, iclass 31, count 0 2006.257.01:32:54.21#ibcon#read 3, iclass 31, count 0 2006.257.01:32:54.21#ibcon#about to read 4, iclass 31, count 0 2006.257.01:32:54.21#ibcon#read 4, iclass 31, count 0 2006.257.01:32:54.21#ibcon#about to read 5, iclass 31, count 0 2006.257.01:32:54.21#ibcon#read 5, iclass 31, count 0 2006.257.01:32:54.21#ibcon#about to read 6, iclass 31, count 0 2006.257.01:32:54.21#ibcon#read 6, iclass 31, count 0 2006.257.01:32:54.21#ibcon#end of sib2, iclass 31, count 0 2006.257.01:32:54.21#ibcon#*mode == 0, iclass 31, count 0 2006.257.01:32:54.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.01:32:54.21#ibcon#[27=USB\r\n] 2006.257.01:32:54.21#ibcon#*before write, iclass 31, count 0 2006.257.01:32:54.21#ibcon#enter sib2, iclass 31, count 0 2006.257.01:32:54.21#ibcon#flushed, iclass 31, count 0 2006.257.01:32:54.21#ibcon#about to write, iclass 31, count 0 2006.257.01:32:54.21#ibcon#wrote, iclass 31, count 0 2006.257.01:32:54.21#ibcon#about to read 3, iclass 31, count 0 2006.257.01:32:54.24#ibcon#read 3, iclass 31, count 0 2006.257.01:32:54.24#ibcon#about to read 4, iclass 31, count 0 2006.257.01:32:54.24#ibcon#read 4, iclass 31, count 0 2006.257.01:32:54.24#ibcon#about to read 5, iclass 31, count 0 2006.257.01:32:54.24#ibcon#read 5, iclass 31, count 0 2006.257.01:32:54.24#ibcon#about to read 6, iclass 31, count 0 2006.257.01:32:54.24#ibcon#read 6, iclass 31, count 0 2006.257.01:32:54.24#ibcon#end of sib2, iclass 31, count 0 2006.257.01:32:54.24#ibcon#*after write, iclass 31, count 0 2006.257.01:32:54.24#ibcon#*before return 0, iclass 31, count 0 2006.257.01:32:54.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:54.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.01:32:54.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.01:32:54.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.01:32:54.24$vck44/vblo=3,649.99 2006.257.01:32:54.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.01:32:54.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.01:32:54.24#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:54.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:54.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:54.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:54.24#ibcon#enter wrdev, iclass 33, count 0 2006.257.01:32:54.24#ibcon#first serial, iclass 33, count 0 2006.257.01:32:54.24#ibcon#enter sib2, iclass 33, count 0 2006.257.01:32:54.24#ibcon#flushed, iclass 33, count 0 2006.257.01:32:54.24#ibcon#about to write, iclass 33, count 0 2006.257.01:32:54.24#ibcon#wrote, iclass 33, count 0 2006.257.01:32:54.24#ibcon#about to read 3, iclass 33, count 0 2006.257.01:32:54.26#ibcon#read 3, iclass 33, count 0 2006.257.01:32:54.26#ibcon#about to read 4, iclass 33, count 0 2006.257.01:32:54.26#ibcon#read 4, iclass 33, count 0 2006.257.01:32:54.26#ibcon#about to read 5, iclass 33, count 0 2006.257.01:32:54.26#ibcon#read 5, iclass 33, count 0 2006.257.01:32:54.26#ibcon#about to read 6, iclass 33, count 0 2006.257.01:32:54.26#ibcon#read 6, iclass 33, count 0 2006.257.01:32:54.26#ibcon#end of sib2, iclass 33, count 0 2006.257.01:32:54.26#ibcon#*mode == 0, iclass 33, count 0 2006.257.01:32:54.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.01:32:54.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.01:32:54.26#ibcon#*before write, iclass 33, count 0 2006.257.01:32:54.26#ibcon#enter sib2, iclass 33, count 0 2006.257.01:32:54.26#ibcon#flushed, iclass 33, count 0 2006.257.01:32:54.26#ibcon#about to write, iclass 33, count 0 2006.257.01:32:54.26#ibcon#wrote, iclass 33, count 0 2006.257.01:32:54.26#ibcon#about to read 3, iclass 33, count 0 2006.257.01:32:54.30#ibcon#read 3, iclass 33, count 0 2006.257.01:32:54.30#ibcon#about to read 4, iclass 33, count 0 2006.257.01:32:54.30#ibcon#read 4, iclass 33, count 0 2006.257.01:32:54.30#ibcon#about to read 5, iclass 33, count 0 2006.257.01:32:54.30#ibcon#read 5, iclass 33, count 0 2006.257.01:32:54.30#ibcon#about to read 6, iclass 33, count 0 2006.257.01:32:54.30#ibcon#read 6, iclass 33, count 0 2006.257.01:32:54.30#ibcon#end of sib2, iclass 33, count 0 2006.257.01:32:54.30#ibcon#*after write, iclass 33, count 0 2006.257.01:32:54.30#ibcon#*before return 0, iclass 33, count 0 2006.257.01:32:54.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:54.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.01:32:54.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.01:32:54.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.01:32:54.30$vck44/vb=3,4 2006.257.01:32:54.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.01:32:54.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.01:32:54.30#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:54.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:54.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:54.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:54.36#ibcon#enter wrdev, iclass 35, count 2 2006.257.01:32:54.36#ibcon#first serial, iclass 35, count 2 2006.257.01:32:54.36#ibcon#enter sib2, iclass 35, count 2 2006.257.01:32:54.36#ibcon#flushed, iclass 35, count 2 2006.257.01:32:54.36#ibcon#about to write, iclass 35, count 2 2006.257.01:32:54.36#ibcon#wrote, iclass 35, count 2 2006.257.01:32:54.36#ibcon#about to read 3, iclass 35, count 2 2006.257.01:32:54.38#ibcon#read 3, iclass 35, count 2 2006.257.01:32:54.38#ibcon#about to read 4, iclass 35, count 2 2006.257.01:32:54.38#ibcon#read 4, iclass 35, count 2 2006.257.01:32:54.38#ibcon#about to read 5, iclass 35, count 2 2006.257.01:32:54.38#ibcon#read 5, iclass 35, count 2 2006.257.01:32:54.38#ibcon#about to read 6, iclass 35, count 2 2006.257.01:32:54.38#ibcon#read 6, iclass 35, count 2 2006.257.01:32:54.38#ibcon#end of sib2, iclass 35, count 2 2006.257.01:32:54.38#ibcon#*mode == 0, iclass 35, count 2 2006.257.01:32:54.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.01:32:54.38#ibcon#[27=AT03-04\r\n] 2006.257.01:32:54.38#ibcon#*before write, iclass 35, count 2 2006.257.01:32:54.38#ibcon#enter sib2, iclass 35, count 2 2006.257.01:32:54.38#ibcon#flushed, iclass 35, count 2 2006.257.01:32:54.38#ibcon#about to write, iclass 35, count 2 2006.257.01:32:54.38#ibcon#wrote, iclass 35, count 2 2006.257.01:32:54.38#ibcon#about to read 3, iclass 35, count 2 2006.257.01:32:54.41#ibcon#read 3, iclass 35, count 2 2006.257.01:32:54.41#ibcon#about to read 4, iclass 35, count 2 2006.257.01:32:54.41#ibcon#read 4, iclass 35, count 2 2006.257.01:32:54.41#ibcon#about to read 5, iclass 35, count 2 2006.257.01:32:54.41#ibcon#read 5, iclass 35, count 2 2006.257.01:32:54.41#ibcon#about to read 6, iclass 35, count 2 2006.257.01:32:54.41#ibcon#read 6, iclass 35, count 2 2006.257.01:32:54.41#ibcon#end of sib2, iclass 35, count 2 2006.257.01:32:54.41#ibcon#*after write, iclass 35, count 2 2006.257.01:32:54.41#ibcon#*before return 0, iclass 35, count 2 2006.257.01:32:54.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:54.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.01:32:54.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.01:32:54.41#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:54.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:54.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:54.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:54.53#ibcon#enter wrdev, iclass 35, count 0 2006.257.01:32:54.53#ibcon#first serial, iclass 35, count 0 2006.257.01:32:54.53#ibcon#enter sib2, iclass 35, count 0 2006.257.01:32:54.53#ibcon#flushed, iclass 35, count 0 2006.257.01:32:54.53#ibcon#about to write, iclass 35, count 0 2006.257.01:32:54.53#ibcon#wrote, iclass 35, count 0 2006.257.01:32:54.53#ibcon#about to read 3, iclass 35, count 0 2006.257.01:32:54.55#ibcon#read 3, iclass 35, count 0 2006.257.01:32:54.55#ibcon#about to read 4, iclass 35, count 0 2006.257.01:32:54.55#ibcon#read 4, iclass 35, count 0 2006.257.01:32:54.55#ibcon#about to read 5, iclass 35, count 0 2006.257.01:32:54.55#ibcon#read 5, iclass 35, count 0 2006.257.01:32:54.55#ibcon#about to read 6, iclass 35, count 0 2006.257.01:32:54.55#ibcon#read 6, iclass 35, count 0 2006.257.01:32:54.55#ibcon#end of sib2, iclass 35, count 0 2006.257.01:32:54.55#ibcon#*mode == 0, iclass 35, count 0 2006.257.01:32:54.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.01:32:54.55#ibcon#[27=USB\r\n] 2006.257.01:32:54.55#ibcon#*before write, iclass 35, count 0 2006.257.01:32:54.55#ibcon#enter sib2, iclass 35, count 0 2006.257.01:32:54.55#ibcon#flushed, iclass 35, count 0 2006.257.01:32:54.55#ibcon#about to write, iclass 35, count 0 2006.257.01:32:54.55#ibcon#wrote, iclass 35, count 0 2006.257.01:32:54.55#ibcon#about to read 3, iclass 35, count 0 2006.257.01:32:54.58#ibcon#read 3, iclass 35, count 0 2006.257.01:32:54.58#ibcon#about to read 4, iclass 35, count 0 2006.257.01:32:54.58#ibcon#read 4, iclass 35, count 0 2006.257.01:32:54.58#ibcon#about to read 5, iclass 35, count 0 2006.257.01:32:54.58#ibcon#read 5, iclass 35, count 0 2006.257.01:32:54.58#ibcon#about to read 6, iclass 35, count 0 2006.257.01:32:54.58#ibcon#read 6, iclass 35, count 0 2006.257.01:32:54.58#ibcon#end of sib2, iclass 35, count 0 2006.257.01:32:54.58#ibcon#*after write, iclass 35, count 0 2006.257.01:32:54.58#ibcon#*before return 0, iclass 35, count 0 2006.257.01:32:54.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:54.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.01:32:54.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.01:32:54.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.01:32:54.58$vck44/vblo=4,679.99 2006.257.01:32:54.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.01:32:54.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.01:32:54.58#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:54.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:54.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:54.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:54.58#ibcon#enter wrdev, iclass 37, count 0 2006.257.01:32:54.58#ibcon#first serial, iclass 37, count 0 2006.257.01:32:54.58#ibcon#enter sib2, iclass 37, count 0 2006.257.01:32:54.58#ibcon#flushed, iclass 37, count 0 2006.257.01:32:54.58#ibcon#about to write, iclass 37, count 0 2006.257.01:32:54.58#ibcon#wrote, iclass 37, count 0 2006.257.01:32:54.58#ibcon#about to read 3, iclass 37, count 0 2006.257.01:32:54.60#ibcon#read 3, iclass 37, count 0 2006.257.01:32:54.60#ibcon#about to read 4, iclass 37, count 0 2006.257.01:32:54.60#ibcon#read 4, iclass 37, count 0 2006.257.01:32:54.60#ibcon#about to read 5, iclass 37, count 0 2006.257.01:32:54.60#ibcon#read 5, iclass 37, count 0 2006.257.01:32:54.60#ibcon#about to read 6, iclass 37, count 0 2006.257.01:32:54.60#ibcon#read 6, iclass 37, count 0 2006.257.01:32:54.60#ibcon#end of sib2, iclass 37, count 0 2006.257.01:32:54.60#ibcon#*mode == 0, iclass 37, count 0 2006.257.01:32:54.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.01:32:54.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.01:32:54.60#ibcon#*before write, iclass 37, count 0 2006.257.01:32:54.60#ibcon#enter sib2, iclass 37, count 0 2006.257.01:32:54.60#ibcon#flushed, iclass 37, count 0 2006.257.01:32:54.60#ibcon#about to write, iclass 37, count 0 2006.257.01:32:54.60#ibcon#wrote, iclass 37, count 0 2006.257.01:32:54.60#ibcon#about to read 3, iclass 37, count 0 2006.257.01:32:54.64#ibcon#read 3, iclass 37, count 0 2006.257.01:32:54.64#ibcon#about to read 4, iclass 37, count 0 2006.257.01:32:54.64#ibcon#read 4, iclass 37, count 0 2006.257.01:32:54.64#ibcon#about to read 5, iclass 37, count 0 2006.257.01:32:54.64#ibcon#read 5, iclass 37, count 0 2006.257.01:32:54.64#ibcon#about to read 6, iclass 37, count 0 2006.257.01:32:54.64#ibcon#read 6, iclass 37, count 0 2006.257.01:32:54.64#ibcon#end of sib2, iclass 37, count 0 2006.257.01:32:54.64#ibcon#*after write, iclass 37, count 0 2006.257.01:32:54.64#ibcon#*before return 0, iclass 37, count 0 2006.257.01:32:54.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:54.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.01:32:54.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.01:32:54.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.01:32:54.64$vck44/vb=4,5 2006.257.01:32:54.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.01:32:54.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.01:32:54.64#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:54.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:54.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:54.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:54.70#ibcon#enter wrdev, iclass 39, count 2 2006.257.01:32:54.70#ibcon#first serial, iclass 39, count 2 2006.257.01:32:54.70#ibcon#enter sib2, iclass 39, count 2 2006.257.01:32:54.70#ibcon#flushed, iclass 39, count 2 2006.257.01:32:54.70#ibcon#about to write, iclass 39, count 2 2006.257.01:32:54.70#ibcon#wrote, iclass 39, count 2 2006.257.01:32:54.70#ibcon#about to read 3, iclass 39, count 2 2006.257.01:32:54.72#ibcon#read 3, iclass 39, count 2 2006.257.01:32:54.72#ibcon#about to read 4, iclass 39, count 2 2006.257.01:32:54.72#ibcon#read 4, iclass 39, count 2 2006.257.01:32:54.72#ibcon#about to read 5, iclass 39, count 2 2006.257.01:32:54.72#ibcon#read 5, iclass 39, count 2 2006.257.01:32:54.72#ibcon#about to read 6, iclass 39, count 2 2006.257.01:32:54.72#ibcon#read 6, iclass 39, count 2 2006.257.01:32:54.72#ibcon#end of sib2, iclass 39, count 2 2006.257.01:32:54.72#ibcon#*mode == 0, iclass 39, count 2 2006.257.01:32:54.72#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.01:32:54.72#ibcon#[27=AT04-05\r\n] 2006.257.01:32:54.72#ibcon#*before write, iclass 39, count 2 2006.257.01:32:54.72#ibcon#enter sib2, iclass 39, count 2 2006.257.01:32:54.72#ibcon#flushed, iclass 39, count 2 2006.257.01:32:54.72#ibcon#about to write, iclass 39, count 2 2006.257.01:32:54.72#ibcon#wrote, iclass 39, count 2 2006.257.01:32:54.72#ibcon#about to read 3, iclass 39, count 2 2006.257.01:32:54.75#ibcon#read 3, iclass 39, count 2 2006.257.01:32:54.75#ibcon#about to read 4, iclass 39, count 2 2006.257.01:32:54.75#ibcon#read 4, iclass 39, count 2 2006.257.01:32:54.75#ibcon#about to read 5, iclass 39, count 2 2006.257.01:32:54.75#ibcon#read 5, iclass 39, count 2 2006.257.01:32:54.75#ibcon#about to read 6, iclass 39, count 2 2006.257.01:32:54.75#ibcon#read 6, iclass 39, count 2 2006.257.01:32:54.75#ibcon#end of sib2, iclass 39, count 2 2006.257.01:32:54.75#ibcon#*after write, iclass 39, count 2 2006.257.01:32:54.75#ibcon#*before return 0, iclass 39, count 2 2006.257.01:32:54.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:54.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.01:32:54.75#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.01:32:54.75#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:54.75#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:54.87#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:54.87#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:54.87#ibcon#enter wrdev, iclass 39, count 0 2006.257.01:32:54.87#ibcon#first serial, iclass 39, count 0 2006.257.01:32:54.87#ibcon#enter sib2, iclass 39, count 0 2006.257.01:32:54.87#ibcon#flushed, iclass 39, count 0 2006.257.01:32:54.87#ibcon#about to write, iclass 39, count 0 2006.257.01:32:54.87#ibcon#wrote, iclass 39, count 0 2006.257.01:32:54.87#ibcon#about to read 3, iclass 39, count 0 2006.257.01:32:54.89#ibcon#read 3, iclass 39, count 0 2006.257.01:32:54.89#ibcon#about to read 4, iclass 39, count 0 2006.257.01:32:54.89#ibcon#read 4, iclass 39, count 0 2006.257.01:32:54.89#ibcon#about to read 5, iclass 39, count 0 2006.257.01:32:54.89#ibcon#read 5, iclass 39, count 0 2006.257.01:32:54.89#ibcon#about to read 6, iclass 39, count 0 2006.257.01:32:54.89#ibcon#read 6, iclass 39, count 0 2006.257.01:32:54.89#ibcon#end of sib2, iclass 39, count 0 2006.257.01:32:54.89#ibcon#*mode == 0, iclass 39, count 0 2006.257.01:32:54.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.01:32:54.89#ibcon#[27=USB\r\n] 2006.257.01:32:54.89#ibcon#*before write, iclass 39, count 0 2006.257.01:32:54.89#ibcon#enter sib2, iclass 39, count 0 2006.257.01:32:54.89#ibcon#flushed, iclass 39, count 0 2006.257.01:32:54.89#ibcon#about to write, iclass 39, count 0 2006.257.01:32:54.89#ibcon#wrote, iclass 39, count 0 2006.257.01:32:54.89#ibcon#about to read 3, iclass 39, count 0 2006.257.01:32:54.92#ibcon#read 3, iclass 39, count 0 2006.257.01:32:54.92#ibcon#about to read 4, iclass 39, count 0 2006.257.01:32:54.92#ibcon#read 4, iclass 39, count 0 2006.257.01:32:54.92#ibcon#about to read 5, iclass 39, count 0 2006.257.01:32:54.92#ibcon#read 5, iclass 39, count 0 2006.257.01:32:54.92#ibcon#about to read 6, iclass 39, count 0 2006.257.01:32:54.92#ibcon#read 6, iclass 39, count 0 2006.257.01:32:54.92#ibcon#end of sib2, iclass 39, count 0 2006.257.01:32:54.92#ibcon#*after write, iclass 39, count 0 2006.257.01:32:54.92#ibcon#*before return 0, iclass 39, count 0 2006.257.01:32:54.92#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:54.92#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.01:32:54.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.01:32:54.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.01:32:54.92$vck44/vblo=5,709.99 2006.257.01:32:54.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.01:32:54.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.01:32:54.92#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:54.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:54.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:54.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:54.92#ibcon#enter wrdev, iclass 3, count 0 2006.257.01:32:54.92#ibcon#first serial, iclass 3, count 0 2006.257.01:32:54.92#ibcon#enter sib2, iclass 3, count 0 2006.257.01:32:54.92#ibcon#flushed, iclass 3, count 0 2006.257.01:32:54.92#ibcon#about to write, iclass 3, count 0 2006.257.01:32:54.92#ibcon#wrote, iclass 3, count 0 2006.257.01:32:54.92#ibcon#about to read 3, iclass 3, count 0 2006.257.01:32:54.94#ibcon#read 3, iclass 3, count 0 2006.257.01:32:54.94#ibcon#about to read 4, iclass 3, count 0 2006.257.01:32:54.94#ibcon#read 4, iclass 3, count 0 2006.257.01:32:54.94#ibcon#about to read 5, iclass 3, count 0 2006.257.01:32:54.94#ibcon#read 5, iclass 3, count 0 2006.257.01:32:54.94#ibcon#about to read 6, iclass 3, count 0 2006.257.01:32:54.94#ibcon#read 6, iclass 3, count 0 2006.257.01:32:54.94#ibcon#end of sib2, iclass 3, count 0 2006.257.01:32:54.94#ibcon#*mode == 0, iclass 3, count 0 2006.257.01:32:54.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.01:32:54.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.01:32:54.94#ibcon#*before write, iclass 3, count 0 2006.257.01:32:54.94#ibcon#enter sib2, iclass 3, count 0 2006.257.01:32:54.94#ibcon#flushed, iclass 3, count 0 2006.257.01:32:54.94#ibcon#about to write, iclass 3, count 0 2006.257.01:32:54.94#ibcon#wrote, iclass 3, count 0 2006.257.01:32:54.94#ibcon#about to read 3, iclass 3, count 0 2006.257.01:32:54.98#ibcon#read 3, iclass 3, count 0 2006.257.01:32:54.98#ibcon#about to read 4, iclass 3, count 0 2006.257.01:32:54.98#ibcon#read 4, iclass 3, count 0 2006.257.01:32:54.98#ibcon#about to read 5, iclass 3, count 0 2006.257.01:32:54.98#ibcon#read 5, iclass 3, count 0 2006.257.01:32:54.98#ibcon#about to read 6, iclass 3, count 0 2006.257.01:32:54.98#ibcon#read 6, iclass 3, count 0 2006.257.01:32:54.98#ibcon#end of sib2, iclass 3, count 0 2006.257.01:32:54.98#ibcon#*after write, iclass 3, count 0 2006.257.01:32:54.98#ibcon#*before return 0, iclass 3, count 0 2006.257.01:32:54.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:54.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.01:32:54.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.01:32:54.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.01:32:54.98$vck44/vb=5,4 2006.257.01:32:54.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.01:32:54.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.01:32:54.98#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:54.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:55.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:55.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:55.04#ibcon#enter wrdev, iclass 5, count 2 2006.257.01:32:55.04#ibcon#first serial, iclass 5, count 2 2006.257.01:32:55.04#ibcon#enter sib2, iclass 5, count 2 2006.257.01:32:55.04#ibcon#flushed, iclass 5, count 2 2006.257.01:32:55.04#ibcon#about to write, iclass 5, count 2 2006.257.01:32:55.04#ibcon#wrote, iclass 5, count 2 2006.257.01:32:55.04#ibcon#about to read 3, iclass 5, count 2 2006.257.01:32:55.06#ibcon#read 3, iclass 5, count 2 2006.257.01:32:55.06#ibcon#about to read 4, iclass 5, count 2 2006.257.01:32:55.06#ibcon#read 4, iclass 5, count 2 2006.257.01:32:55.06#ibcon#about to read 5, iclass 5, count 2 2006.257.01:32:55.06#ibcon#read 5, iclass 5, count 2 2006.257.01:32:55.06#ibcon#about to read 6, iclass 5, count 2 2006.257.01:32:55.06#ibcon#read 6, iclass 5, count 2 2006.257.01:32:55.06#ibcon#end of sib2, iclass 5, count 2 2006.257.01:32:55.06#ibcon#*mode == 0, iclass 5, count 2 2006.257.01:32:55.06#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.01:32:55.06#ibcon#[27=AT05-04\r\n] 2006.257.01:32:55.06#ibcon#*before write, iclass 5, count 2 2006.257.01:32:55.06#ibcon#enter sib2, iclass 5, count 2 2006.257.01:32:55.06#ibcon#flushed, iclass 5, count 2 2006.257.01:32:55.06#ibcon#about to write, iclass 5, count 2 2006.257.01:32:55.06#ibcon#wrote, iclass 5, count 2 2006.257.01:32:55.06#ibcon#about to read 3, iclass 5, count 2 2006.257.01:32:55.09#ibcon#read 3, iclass 5, count 2 2006.257.01:32:55.09#ibcon#about to read 4, iclass 5, count 2 2006.257.01:32:55.09#ibcon#read 4, iclass 5, count 2 2006.257.01:32:55.09#ibcon#about to read 5, iclass 5, count 2 2006.257.01:32:55.09#ibcon#read 5, iclass 5, count 2 2006.257.01:32:55.09#ibcon#about to read 6, iclass 5, count 2 2006.257.01:32:55.09#ibcon#read 6, iclass 5, count 2 2006.257.01:32:55.09#ibcon#end of sib2, iclass 5, count 2 2006.257.01:32:55.09#ibcon#*after write, iclass 5, count 2 2006.257.01:32:55.09#ibcon#*before return 0, iclass 5, count 2 2006.257.01:32:55.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:55.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.01:32:55.09#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.01:32:55.09#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:55.09#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:55.21#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:55.21#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:55.21#ibcon#enter wrdev, iclass 5, count 0 2006.257.01:32:55.21#ibcon#first serial, iclass 5, count 0 2006.257.01:32:55.21#ibcon#enter sib2, iclass 5, count 0 2006.257.01:32:55.21#ibcon#flushed, iclass 5, count 0 2006.257.01:32:55.21#ibcon#about to write, iclass 5, count 0 2006.257.01:32:55.21#ibcon#wrote, iclass 5, count 0 2006.257.01:32:55.21#ibcon#about to read 3, iclass 5, count 0 2006.257.01:32:55.23#ibcon#read 3, iclass 5, count 0 2006.257.01:32:55.23#ibcon#about to read 4, iclass 5, count 0 2006.257.01:32:55.23#ibcon#read 4, iclass 5, count 0 2006.257.01:32:55.23#ibcon#about to read 5, iclass 5, count 0 2006.257.01:32:55.23#ibcon#read 5, iclass 5, count 0 2006.257.01:32:55.23#ibcon#about to read 6, iclass 5, count 0 2006.257.01:32:55.23#ibcon#read 6, iclass 5, count 0 2006.257.01:32:55.23#ibcon#end of sib2, iclass 5, count 0 2006.257.01:32:55.23#ibcon#*mode == 0, iclass 5, count 0 2006.257.01:32:55.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.01:32:55.23#ibcon#[27=USB\r\n] 2006.257.01:32:55.23#ibcon#*before write, iclass 5, count 0 2006.257.01:32:55.23#ibcon#enter sib2, iclass 5, count 0 2006.257.01:32:55.23#ibcon#flushed, iclass 5, count 0 2006.257.01:32:55.23#ibcon#about to write, iclass 5, count 0 2006.257.01:32:55.23#ibcon#wrote, iclass 5, count 0 2006.257.01:32:55.23#ibcon#about to read 3, iclass 5, count 0 2006.257.01:32:55.26#ibcon#read 3, iclass 5, count 0 2006.257.01:32:55.26#ibcon#about to read 4, iclass 5, count 0 2006.257.01:32:55.26#ibcon#read 4, iclass 5, count 0 2006.257.01:32:55.26#ibcon#about to read 5, iclass 5, count 0 2006.257.01:32:55.26#ibcon#read 5, iclass 5, count 0 2006.257.01:32:55.26#ibcon#about to read 6, iclass 5, count 0 2006.257.01:32:55.26#ibcon#read 6, iclass 5, count 0 2006.257.01:32:55.26#ibcon#end of sib2, iclass 5, count 0 2006.257.01:32:55.26#ibcon#*after write, iclass 5, count 0 2006.257.01:32:55.26#ibcon#*before return 0, iclass 5, count 0 2006.257.01:32:55.26#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:55.26#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.01:32:55.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.01:32:55.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.01:32:55.26$vck44/vblo=6,719.99 2006.257.01:32:55.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.01:32:55.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.01:32:55.26#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:55.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:55.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:55.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:55.26#ibcon#enter wrdev, iclass 7, count 0 2006.257.01:32:55.26#ibcon#first serial, iclass 7, count 0 2006.257.01:32:55.26#ibcon#enter sib2, iclass 7, count 0 2006.257.01:32:55.26#ibcon#flushed, iclass 7, count 0 2006.257.01:32:55.26#ibcon#about to write, iclass 7, count 0 2006.257.01:32:55.26#ibcon#wrote, iclass 7, count 0 2006.257.01:32:55.26#ibcon#about to read 3, iclass 7, count 0 2006.257.01:32:55.28#ibcon#read 3, iclass 7, count 0 2006.257.01:32:55.28#ibcon#about to read 4, iclass 7, count 0 2006.257.01:32:55.28#ibcon#read 4, iclass 7, count 0 2006.257.01:32:55.28#ibcon#about to read 5, iclass 7, count 0 2006.257.01:32:55.28#ibcon#read 5, iclass 7, count 0 2006.257.01:32:55.28#ibcon#about to read 6, iclass 7, count 0 2006.257.01:32:55.28#ibcon#read 6, iclass 7, count 0 2006.257.01:32:55.28#ibcon#end of sib2, iclass 7, count 0 2006.257.01:32:55.28#ibcon#*mode == 0, iclass 7, count 0 2006.257.01:32:55.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.01:32:55.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.01:32:55.28#ibcon#*before write, iclass 7, count 0 2006.257.01:32:55.28#ibcon#enter sib2, iclass 7, count 0 2006.257.01:32:55.28#ibcon#flushed, iclass 7, count 0 2006.257.01:32:55.28#ibcon#about to write, iclass 7, count 0 2006.257.01:32:55.28#ibcon#wrote, iclass 7, count 0 2006.257.01:32:55.28#ibcon#about to read 3, iclass 7, count 0 2006.257.01:32:55.32#ibcon#read 3, iclass 7, count 0 2006.257.01:32:55.32#ibcon#about to read 4, iclass 7, count 0 2006.257.01:32:55.32#ibcon#read 4, iclass 7, count 0 2006.257.01:32:55.32#ibcon#about to read 5, iclass 7, count 0 2006.257.01:32:55.32#ibcon#read 5, iclass 7, count 0 2006.257.01:32:55.32#ibcon#about to read 6, iclass 7, count 0 2006.257.01:32:55.32#ibcon#read 6, iclass 7, count 0 2006.257.01:32:55.32#ibcon#end of sib2, iclass 7, count 0 2006.257.01:32:55.32#ibcon#*after write, iclass 7, count 0 2006.257.01:32:55.32#ibcon#*before return 0, iclass 7, count 0 2006.257.01:32:55.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:55.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.01:32:55.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.01:32:55.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.01:32:55.32$vck44/vb=6,4 2006.257.01:32:55.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.01:32:55.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.01:32:55.32#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:55.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:55.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:55.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:55.38#ibcon#enter wrdev, iclass 11, count 2 2006.257.01:32:55.38#ibcon#first serial, iclass 11, count 2 2006.257.01:32:55.38#ibcon#enter sib2, iclass 11, count 2 2006.257.01:32:55.38#ibcon#flushed, iclass 11, count 2 2006.257.01:32:55.38#ibcon#about to write, iclass 11, count 2 2006.257.01:32:55.38#ibcon#wrote, iclass 11, count 2 2006.257.01:32:55.38#ibcon#about to read 3, iclass 11, count 2 2006.257.01:32:55.40#ibcon#read 3, iclass 11, count 2 2006.257.01:32:55.40#ibcon#about to read 4, iclass 11, count 2 2006.257.01:32:55.40#ibcon#read 4, iclass 11, count 2 2006.257.01:32:55.40#ibcon#about to read 5, iclass 11, count 2 2006.257.01:32:55.40#ibcon#read 5, iclass 11, count 2 2006.257.01:32:55.40#ibcon#about to read 6, iclass 11, count 2 2006.257.01:32:55.40#ibcon#read 6, iclass 11, count 2 2006.257.01:32:55.40#ibcon#end of sib2, iclass 11, count 2 2006.257.01:32:55.40#ibcon#*mode == 0, iclass 11, count 2 2006.257.01:32:55.40#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.01:32:55.40#ibcon#[27=AT06-04\r\n] 2006.257.01:32:55.40#ibcon#*before write, iclass 11, count 2 2006.257.01:32:55.40#ibcon#enter sib2, iclass 11, count 2 2006.257.01:32:55.40#ibcon#flushed, iclass 11, count 2 2006.257.01:32:55.40#ibcon#about to write, iclass 11, count 2 2006.257.01:32:55.40#ibcon#wrote, iclass 11, count 2 2006.257.01:32:55.40#ibcon#about to read 3, iclass 11, count 2 2006.257.01:32:55.43#ibcon#read 3, iclass 11, count 2 2006.257.01:32:55.43#ibcon#about to read 4, iclass 11, count 2 2006.257.01:32:55.43#ibcon#read 4, iclass 11, count 2 2006.257.01:32:55.43#ibcon#about to read 5, iclass 11, count 2 2006.257.01:32:55.43#ibcon#read 5, iclass 11, count 2 2006.257.01:32:55.43#ibcon#about to read 6, iclass 11, count 2 2006.257.01:32:55.43#ibcon#read 6, iclass 11, count 2 2006.257.01:32:55.43#ibcon#end of sib2, iclass 11, count 2 2006.257.01:32:55.43#ibcon#*after write, iclass 11, count 2 2006.257.01:32:55.43#ibcon#*before return 0, iclass 11, count 2 2006.257.01:32:55.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:55.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.01:32:55.43#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.01:32:55.43#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:55.43#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:55.56#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:55.56#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:55.56#ibcon#enter wrdev, iclass 11, count 0 2006.257.01:32:55.56#ibcon#first serial, iclass 11, count 0 2006.257.01:32:55.56#ibcon#enter sib2, iclass 11, count 0 2006.257.01:32:55.56#ibcon#flushed, iclass 11, count 0 2006.257.01:32:55.56#ibcon#about to write, iclass 11, count 0 2006.257.01:32:55.56#ibcon#wrote, iclass 11, count 0 2006.257.01:32:55.56#ibcon#about to read 3, iclass 11, count 0 2006.257.01:32:55.58#ibcon#read 3, iclass 11, count 0 2006.257.01:32:55.58#ibcon#about to read 4, iclass 11, count 0 2006.257.01:32:55.58#ibcon#read 4, iclass 11, count 0 2006.257.01:32:55.58#ibcon#about to read 5, iclass 11, count 0 2006.257.01:32:55.58#ibcon#read 5, iclass 11, count 0 2006.257.01:32:55.58#ibcon#about to read 6, iclass 11, count 0 2006.257.01:32:55.58#ibcon#read 6, iclass 11, count 0 2006.257.01:32:55.58#ibcon#end of sib2, iclass 11, count 0 2006.257.01:32:55.58#ibcon#*mode == 0, iclass 11, count 0 2006.257.01:32:55.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.01:32:55.58#ibcon#[27=USB\r\n] 2006.257.01:32:55.58#ibcon#*before write, iclass 11, count 0 2006.257.01:32:55.58#ibcon#enter sib2, iclass 11, count 0 2006.257.01:32:55.58#ibcon#flushed, iclass 11, count 0 2006.257.01:32:55.58#ibcon#about to write, iclass 11, count 0 2006.257.01:32:55.58#ibcon#wrote, iclass 11, count 0 2006.257.01:32:55.58#ibcon#about to read 3, iclass 11, count 0 2006.257.01:32:55.61#ibcon#read 3, iclass 11, count 0 2006.257.01:32:55.61#ibcon#about to read 4, iclass 11, count 0 2006.257.01:32:55.61#ibcon#read 4, iclass 11, count 0 2006.257.01:32:55.61#ibcon#about to read 5, iclass 11, count 0 2006.257.01:32:55.61#ibcon#read 5, iclass 11, count 0 2006.257.01:32:55.61#ibcon#about to read 6, iclass 11, count 0 2006.257.01:32:55.61#ibcon#read 6, iclass 11, count 0 2006.257.01:32:55.61#ibcon#end of sib2, iclass 11, count 0 2006.257.01:32:55.61#ibcon#*after write, iclass 11, count 0 2006.257.01:32:55.61#ibcon#*before return 0, iclass 11, count 0 2006.257.01:32:55.61#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:55.61#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.01:32:55.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.01:32:55.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.01:32:55.61$vck44/vblo=7,734.99 2006.257.01:32:55.61#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.01:32:55.61#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.01:32:55.61#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:55.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.01:32:55.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.01:32:55.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.01:32:55.61#ibcon#enter wrdev, iclass 13, count 0 2006.257.01:32:55.61#ibcon#first serial, iclass 13, count 0 2006.257.01:32:55.61#ibcon#enter sib2, iclass 13, count 0 2006.257.01:32:55.61#ibcon#flushed, iclass 13, count 0 2006.257.01:32:55.61#ibcon#about to write, iclass 13, count 0 2006.257.01:32:55.61#ibcon#wrote, iclass 13, count 0 2006.257.01:32:55.61#ibcon#about to read 3, iclass 13, count 0 2006.257.01:32:55.63#ibcon#read 3, iclass 13, count 0 2006.257.01:32:55.63#ibcon#about to read 4, iclass 13, count 0 2006.257.01:32:55.63#ibcon#read 4, iclass 13, count 0 2006.257.01:32:55.63#ibcon#about to read 5, iclass 13, count 0 2006.257.01:32:55.63#ibcon#read 5, iclass 13, count 0 2006.257.01:32:55.63#ibcon#about to read 6, iclass 13, count 0 2006.257.01:32:55.63#ibcon#read 6, iclass 13, count 0 2006.257.01:32:55.63#ibcon#end of sib2, iclass 13, count 0 2006.257.01:32:55.63#ibcon#*mode == 0, iclass 13, count 0 2006.257.01:32:55.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.01:32:55.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.01:32:55.63#ibcon#*before write, iclass 13, count 0 2006.257.01:32:55.63#ibcon#enter sib2, iclass 13, count 0 2006.257.01:32:55.63#ibcon#flushed, iclass 13, count 0 2006.257.01:32:55.63#ibcon#about to write, iclass 13, count 0 2006.257.01:32:55.63#ibcon#wrote, iclass 13, count 0 2006.257.01:32:55.63#ibcon#about to read 3, iclass 13, count 0 2006.257.01:32:55.67#ibcon#read 3, iclass 13, count 0 2006.257.01:32:55.67#ibcon#about to read 4, iclass 13, count 0 2006.257.01:32:55.67#ibcon#read 4, iclass 13, count 0 2006.257.01:32:55.67#ibcon#about to read 5, iclass 13, count 0 2006.257.01:32:55.67#ibcon#read 5, iclass 13, count 0 2006.257.01:32:55.67#ibcon#about to read 6, iclass 13, count 0 2006.257.01:32:55.67#ibcon#read 6, iclass 13, count 0 2006.257.01:32:55.67#ibcon#end of sib2, iclass 13, count 0 2006.257.01:32:55.67#ibcon#*after write, iclass 13, count 0 2006.257.01:32:55.67#ibcon#*before return 0, iclass 13, count 0 2006.257.01:32:55.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.01:32:55.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.01:32:55.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.01:32:55.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.01:32:55.67$vck44/vb=7,4 2006.257.01:32:55.67#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.01:32:55.67#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.01:32:55.67#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:55.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.01:32:55.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.01:32:55.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.01:32:55.73#ibcon#enter wrdev, iclass 15, count 2 2006.257.01:32:55.73#ibcon#first serial, iclass 15, count 2 2006.257.01:32:55.73#ibcon#enter sib2, iclass 15, count 2 2006.257.01:32:55.73#ibcon#flushed, iclass 15, count 2 2006.257.01:32:55.73#ibcon#about to write, iclass 15, count 2 2006.257.01:32:55.73#ibcon#wrote, iclass 15, count 2 2006.257.01:32:55.73#ibcon#about to read 3, iclass 15, count 2 2006.257.01:32:55.75#ibcon#read 3, iclass 15, count 2 2006.257.01:32:55.75#ibcon#about to read 4, iclass 15, count 2 2006.257.01:32:55.75#ibcon#read 4, iclass 15, count 2 2006.257.01:32:55.75#ibcon#about to read 5, iclass 15, count 2 2006.257.01:32:55.75#ibcon#read 5, iclass 15, count 2 2006.257.01:32:55.75#ibcon#about to read 6, iclass 15, count 2 2006.257.01:32:55.75#ibcon#read 6, iclass 15, count 2 2006.257.01:32:55.75#ibcon#end of sib2, iclass 15, count 2 2006.257.01:32:55.75#ibcon#*mode == 0, iclass 15, count 2 2006.257.01:32:55.75#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.01:32:55.75#ibcon#[27=AT07-04\r\n] 2006.257.01:32:55.75#ibcon#*before write, iclass 15, count 2 2006.257.01:32:55.75#ibcon#enter sib2, iclass 15, count 2 2006.257.01:32:55.75#ibcon#flushed, iclass 15, count 2 2006.257.01:32:55.75#ibcon#about to write, iclass 15, count 2 2006.257.01:32:55.75#ibcon#wrote, iclass 15, count 2 2006.257.01:32:55.75#ibcon#about to read 3, iclass 15, count 2 2006.257.01:32:55.78#ibcon#read 3, iclass 15, count 2 2006.257.01:32:55.78#ibcon#about to read 4, iclass 15, count 2 2006.257.01:32:55.78#ibcon#read 4, iclass 15, count 2 2006.257.01:32:55.78#ibcon#about to read 5, iclass 15, count 2 2006.257.01:32:55.78#ibcon#read 5, iclass 15, count 2 2006.257.01:32:55.78#ibcon#about to read 6, iclass 15, count 2 2006.257.01:32:55.78#ibcon#read 6, iclass 15, count 2 2006.257.01:32:55.78#ibcon#end of sib2, iclass 15, count 2 2006.257.01:32:55.78#ibcon#*after write, iclass 15, count 2 2006.257.01:32:55.78#ibcon#*before return 0, iclass 15, count 2 2006.257.01:32:55.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.01:32:55.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.01:32:55.78#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.01:32:55.78#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:55.78#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.01:32:55.90#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.01:32:55.90#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.01:32:55.90#ibcon#enter wrdev, iclass 15, count 0 2006.257.01:32:55.90#ibcon#first serial, iclass 15, count 0 2006.257.01:32:55.90#ibcon#enter sib2, iclass 15, count 0 2006.257.01:32:55.90#ibcon#flushed, iclass 15, count 0 2006.257.01:32:55.90#ibcon#about to write, iclass 15, count 0 2006.257.01:32:55.90#ibcon#wrote, iclass 15, count 0 2006.257.01:32:55.90#ibcon#about to read 3, iclass 15, count 0 2006.257.01:32:55.92#ibcon#read 3, iclass 15, count 0 2006.257.01:32:55.92#ibcon#about to read 4, iclass 15, count 0 2006.257.01:32:55.92#ibcon#read 4, iclass 15, count 0 2006.257.01:32:55.92#ibcon#about to read 5, iclass 15, count 0 2006.257.01:32:55.92#ibcon#read 5, iclass 15, count 0 2006.257.01:32:55.92#ibcon#about to read 6, iclass 15, count 0 2006.257.01:32:55.92#ibcon#read 6, iclass 15, count 0 2006.257.01:32:55.92#ibcon#end of sib2, iclass 15, count 0 2006.257.01:32:55.92#ibcon#*mode == 0, iclass 15, count 0 2006.257.01:32:55.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.01:32:55.92#ibcon#[27=USB\r\n] 2006.257.01:32:55.92#ibcon#*before write, iclass 15, count 0 2006.257.01:32:55.92#ibcon#enter sib2, iclass 15, count 0 2006.257.01:32:55.92#ibcon#flushed, iclass 15, count 0 2006.257.01:32:55.92#ibcon#about to write, iclass 15, count 0 2006.257.01:32:55.92#ibcon#wrote, iclass 15, count 0 2006.257.01:32:55.92#ibcon#about to read 3, iclass 15, count 0 2006.257.01:32:55.95#ibcon#read 3, iclass 15, count 0 2006.257.01:32:55.95#ibcon#about to read 4, iclass 15, count 0 2006.257.01:32:55.95#ibcon#read 4, iclass 15, count 0 2006.257.01:32:55.95#ibcon#about to read 5, iclass 15, count 0 2006.257.01:32:55.95#ibcon#read 5, iclass 15, count 0 2006.257.01:32:55.95#ibcon#about to read 6, iclass 15, count 0 2006.257.01:32:55.95#ibcon#read 6, iclass 15, count 0 2006.257.01:32:55.95#ibcon#end of sib2, iclass 15, count 0 2006.257.01:32:55.95#ibcon#*after write, iclass 15, count 0 2006.257.01:32:55.95#ibcon#*before return 0, iclass 15, count 0 2006.257.01:32:55.95#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.01:32:55.95#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.01:32:55.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.01:32:55.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.01:32:55.95$vck44/vblo=8,744.99 2006.257.01:32:55.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.01:32:55.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.01:32:55.95#ibcon#ireg 17 cls_cnt 0 2006.257.01:32:55.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:55.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:55.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:55.95#ibcon#enter wrdev, iclass 17, count 0 2006.257.01:32:55.95#ibcon#first serial, iclass 17, count 0 2006.257.01:32:55.95#ibcon#enter sib2, iclass 17, count 0 2006.257.01:32:55.95#ibcon#flushed, iclass 17, count 0 2006.257.01:32:55.95#ibcon#about to write, iclass 17, count 0 2006.257.01:32:55.95#ibcon#wrote, iclass 17, count 0 2006.257.01:32:55.95#ibcon#about to read 3, iclass 17, count 0 2006.257.01:32:55.97#ibcon#read 3, iclass 17, count 0 2006.257.01:32:55.97#ibcon#about to read 4, iclass 17, count 0 2006.257.01:32:55.97#ibcon#read 4, iclass 17, count 0 2006.257.01:32:55.97#ibcon#about to read 5, iclass 17, count 0 2006.257.01:32:55.97#ibcon#read 5, iclass 17, count 0 2006.257.01:32:55.97#ibcon#about to read 6, iclass 17, count 0 2006.257.01:32:55.97#ibcon#read 6, iclass 17, count 0 2006.257.01:32:55.97#ibcon#end of sib2, iclass 17, count 0 2006.257.01:32:55.97#ibcon#*mode == 0, iclass 17, count 0 2006.257.01:32:55.97#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.01:32:55.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.01:32:55.97#ibcon#*before write, iclass 17, count 0 2006.257.01:32:55.97#ibcon#enter sib2, iclass 17, count 0 2006.257.01:32:55.97#ibcon#flushed, iclass 17, count 0 2006.257.01:32:55.97#ibcon#about to write, iclass 17, count 0 2006.257.01:32:55.97#ibcon#wrote, iclass 17, count 0 2006.257.01:32:55.97#ibcon#about to read 3, iclass 17, count 0 2006.257.01:32:56.01#ibcon#read 3, iclass 17, count 0 2006.257.01:32:56.01#ibcon#about to read 4, iclass 17, count 0 2006.257.01:32:56.01#ibcon#read 4, iclass 17, count 0 2006.257.01:32:56.01#ibcon#about to read 5, iclass 17, count 0 2006.257.01:32:56.01#ibcon#read 5, iclass 17, count 0 2006.257.01:32:56.01#ibcon#about to read 6, iclass 17, count 0 2006.257.01:32:56.01#ibcon#read 6, iclass 17, count 0 2006.257.01:32:56.01#ibcon#end of sib2, iclass 17, count 0 2006.257.01:32:56.01#ibcon#*after write, iclass 17, count 0 2006.257.01:32:56.01#ibcon#*before return 0, iclass 17, count 0 2006.257.01:32:56.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:56.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.01:32:56.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.01:32:56.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.01:32:56.01$vck44/vb=8,4 2006.257.01:32:56.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.01:32:56.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.01:32:56.01#ibcon#ireg 11 cls_cnt 2 2006.257.01:32:56.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:56.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:56.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:56.07#ibcon#enter wrdev, iclass 19, count 2 2006.257.01:32:56.07#ibcon#first serial, iclass 19, count 2 2006.257.01:32:56.07#ibcon#enter sib2, iclass 19, count 2 2006.257.01:32:56.07#ibcon#flushed, iclass 19, count 2 2006.257.01:32:56.07#ibcon#about to write, iclass 19, count 2 2006.257.01:32:56.07#ibcon#wrote, iclass 19, count 2 2006.257.01:32:56.07#ibcon#about to read 3, iclass 19, count 2 2006.257.01:32:56.09#ibcon#read 3, iclass 19, count 2 2006.257.01:32:56.09#ibcon#about to read 4, iclass 19, count 2 2006.257.01:32:56.09#ibcon#read 4, iclass 19, count 2 2006.257.01:32:56.09#ibcon#about to read 5, iclass 19, count 2 2006.257.01:32:56.09#ibcon#read 5, iclass 19, count 2 2006.257.01:32:56.09#ibcon#about to read 6, iclass 19, count 2 2006.257.01:32:56.09#ibcon#read 6, iclass 19, count 2 2006.257.01:32:56.09#ibcon#end of sib2, iclass 19, count 2 2006.257.01:32:56.09#ibcon#*mode == 0, iclass 19, count 2 2006.257.01:32:56.09#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.01:32:56.09#ibcon#[27=AT08-04\r\n] 2006.257.01:32:56.09#ibcon#*before write, iclass 19, count 2 2006.257.01:32:56.09#ibcon#enter sib2, iclass 19, count 2 2006.257.01:32:56.09#ibcon#flushed, iclass 19, count 2 2006.257.01:32:56.09#ibcon#about to write, iclass 19, count 2 2006.257.01:32:56.09#ibcon#wrote, iclass 19, count 2 2006.257.01:32:56.09#ibcon#about to read 3, iclass 19, count 2 2006.257.01:32:56.12#ibcon#read 3, iclass 19, count 2 2006.257.01:32:56.12#ibcon#about to read 4, iclass 19, count 2 2006.257.01:32:56.12#ibcon#read 4, iclass 19, count 2 2006.257.01:32:56.12#ibcon#about to read 5, iclass 19, count 2 2006.257.01:32:56.12#ibcon#read 5, iclass 19, count 2 2006.257.01:32:56.12#ibcon#about to read 6, iclass 19, count 2 2006.257.01:32:56.12#ibcon#read 6, iclass 19, count 2 2006.257.01:32:56.12#ibcon#end of sib2, iclass 19, count 2 2006.257.01:32:56.12#ibcon#*after write, iclass 19, count 2 2006.257.01:32:56.12#ibcon#*before return 0, iclass 19, count 2 2006.257.01:32:56.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:56.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.01:32:56.12#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.01:32:56.12#ibcon#ireg 7 cls_cnt 0 2006.257.01:32:56.12#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:56.14#trakl#Antenna stuck 2006.257.01:32:56.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:56.24#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:56.24#ibcon#enter wrdev, iclass 19, count 0 2006.257.01:32:56.24#ibcon#first serial, iclass 19, count 0 2006.257.01:32:56.24#ibcon#enter sib2, iclass 19, count 0 2006.257.01:32:56.24#ibcon#flushed, iclass 19, count 0 2006.257.01:32:56.24#ibcon#about to write, iclass 19, count 0 2006.257.01:32:56.24#ibcon#wrote, iclass 19, count 0 2006.257.01:32:56.24#ibcon#about to read 3, iclass 19, count 0 2006.257.01:32:56.26#ibcon#read 3, iclass 19, count 0 2006.257.01:32:56.26#ibcon#about to read 4, iclass 19, count 0 2006.257.01:32:56.26#ibcon#read 4, iclass 19, count 0 2006.257.01:32:56.26#ibcon#about to read 5, iclass 19, count 0 2006.257.01:32:56.26#ibcon#read 5, iclass 19, count 0 2006.257.01:32:56.26#ibcon#about to read 6, iclass 19, count 0 2006.257.01:32:56.26#ibcon#read 6, iclass 19, count 0 2006.257.01:32:56.26#ibcon#end of sib2, iclass 19, count 0 2006.257.01:32:56.26#ibcon#*mode == 0, iclass 19, count 0 2006.257.01:32:56.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.01:32:56.26#ibcon#[27=USB\r\n] 2006.257.01:32:56.26#ibcon#*before write, iclass 19, count 0 2006.257.01:32:56.26#ibcon#enter sib2, iclass 19, count 0 2006.257.01:32:56.26#ibcon#flushed, iclass 19, count 0 2006.257.01:32:56.26#ibcon#about to write, iclass 19, count 0 2006.257.01:32:56.26#ibcon#wrote, iclass 19, count 0 2006.257.01:32:56.26#ibcon#about to read 3, iclass 19, count 0 2006.257.01:32:56.29#ibcon#read 3, iclass 19, count 0 2006.257.01:32:56.29#ibcon#about to read 4, iclass 19, count 0 2006.257.01:32:56.29#ibcon#read 4, iclass 19, count 0 2006.257.01:32:56.29#ibcon#about to read 5, iclass 19, count 0 2006.257.01:32:56.29#ibcon#read 5, iclass 19, count 0 2006.257.01:32:56.29#ibcon#about to read 6, iclass 19, count 0 2006.257.01:32:56.29#ibcon#read 6, iclass 19, count 0 2006.257.01:32:56.29#ibcon#end of sib2, iclass 19, count 0 2006.257.01:32:56.29#ibcon#*after write, iclass 19, count 0 2006.257.01:32:56.29#ibcon#*before return 0, iclass 19, count 0 2006.257.01:32:56.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:56.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.01:32:56.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.01:32:56.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.01:32:56.29$vck44/vabw=wide 2006.257.01:32:56.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.01:32:56.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.01:32:56.29#ibcon#ireg 8 cls_cnt 0 2006.257.01:32:56.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:56.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:56.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:56.29#ibcon#enter wrdev, iclass 21, count 0 2006.257.01:32:56.29#ibcon#first serial, iclass 21, count 0 2006.257.01:32:56.29#ibcon#enter sib2, iclass 21, count 0 2006.257.01:32:56.29#ibcon#flushed, iclass 21, count 0 2006.257.01:32:56.29#ibcon#about to write, iclass 21, count 0 2006.257.01:32:56.29#ibcon#wrote, iclass 21, count 0 2006.257.01:32:56.29#ibcon#about to read 3, iclass 21, count 0 2006.257.01:32:56.31#ibcon#read 3, iclass 21, count 0 2006.257.01:32:56.31#ibcon#about to read 4, iclass 21, count 0 2006.257.01:32:56.31#ibcon#read 4, iclass 21, count 0 2006.257.01:32:56.31#ibcon#about to read 5, iclass 21, count 0 2006.257.01:32:56.31#ibcon#read 5, iclass 21, count 0 2006.257.01:32:56.31#ibcon#about to read 6, iclass 21, count 0 2006.257.01:32:56.31#ibcon#read 6, iclass 21, count 0 2006.257.01:32:56.31#ibcon#end of sib2, iclass 21, count 0 2006.257.01:32:56.31#ibcon#*mode == 0, iclass 21, count 0 2006.257.01:32:56.31#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.01:32:56.31#ibcon#[25=BW32\r\n] 2006.257.01:32:56.31#ibcon#*before write, iclass 21, count 0 2006.257.01:32:56.31#ibcon#enter sib2, iclass 21, count 0 2006.257.01:32:56.31#ibcon#flushed, iclass 21, count 0 2006.257.01:32:56.31#ibcon#about to write, iclass 21, count 0 2006.257.01:32:56.31#ibcon#wrote, iclass 21, count 0 2006.257.01:32:56.31#ibcon#about to read 3, iclass 21, count 0 2006.257.01:32:56.34#ibcon#read 3, iclass 21, count 0 2006.257.01:32:56.34#ibcon#about to read 4, iclass 21, count 0 2006.257.01:32:56.34#ibcon#read 4, iclass 21, count 0 2006.257.01:32:56.34#ibcon#about to read 5, iclass 21, count 0 2006.257.01:32:56.34#ibcon#read 5, iclass 21, count 0 2006.257.01:32:56.34#ibcon#about to read 6, iclass 21, count 0 2006.257.01:32:56.34#ibcon#read 6, iclass 21, count 0 2006.257.01:32:56.34#ibcon#end of sib2, iclass 21, count 0 2006.257.01:32:56.34#ibcon#*after write, iclass 21, count 0 2006.257.01:32:56.34#ibcon#*before return 0, iclass 21, count 0 2006.257.01:32:56.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:56.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.01:32:56.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.01:32:56.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.01:32:56.34$vck44/vbbw=wide 2006.257.01:32:56.34#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.01:32:56.34#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.01:32:56.34#ibcon#ireg 8 cls_cnt 0 2006.257.01:32:56.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.01:32:56.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.01:32:56.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.01:32:56.41#ibcon#enter wrdev, iclass 23, count 0 2006.257.01:32:56.41#ibcon#first serial, iclass 23, count 0 2006.257.01:32:56.41#ibcon#enter sib2, iclass 23, count 0 2006.257.01:32:56.41#ibcon#flushed, iclass 23, count 0 2006.257.01:32:56.41#ibcon#about to write, iclass 23, count 0 2006.257.01:32:56.41#ibcon#wrote, iclass 23, count 0 2006.257.01:32:56.41#ibcon#about to read 3, iclass 23, count 0 2006.257.01:32:56.44#ibcon#read 3, iclass 23, count 0 2006.257.01:32:56.44#ibcon#about to read 4, iclass 23, count 0 2006.257.01:32:56.44#ibcon#read 4, iclass 23, count 0 2006.257.01:32:56.44#ibcon#about to read 5, iclass 23, count 0 2006.257.01:32:56.44#ibcon#read 5, iclass 23, count 0 2006.257.01:32:56.44#ibcon#about to read 6, iclass 23, count 0 2006.257.01:32:56.44#ibcon#read 6, iclass 23, count 0 2006.257.01:32:56.44#ibcon#end of sib2, iclass 23, count 0 2006.257.01:32:56.44#ibcon#*mode == 0, iclass 23, count 0 2006.257.01:32:56.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.01:32:56.44#ibcon#[27=BW32\r\n] 2006.257.01:32:56.44#ibcon#*before write, iclass 23, count 0 2006.257.01:32:56.44#ibcon#enter sib2, iclass 23, count 0 2006.257.01:32:56.44#ibcon#flushed, iclass 23, count 0 2006.257.01:32:56.44#ibcon#about to write, iclass 23, count 0 2006.257.01:32:56.44#ibcon#wrote, iclass 23, count 0 2006.257.01:32:56.44#ibcon#about to read 3, iclass 23, count 0 2006.257.01:32:56.47#ibcon#read 3, iclass 23, count 0 2006.257.01:32:56.47#ibcon#about to read 4, iclass 23, count 0 2006.257.01:32:56.47#ibcon#read 4, iclass 23, count 0 2006.257.01:32:56.47#ibcon#about to read 5, iclass 23, count 0 2006.257.01:32:56.47#ibcon#read 5, iclass 23, count 0 2006.257.01:32:56.47#ibcon#about to read 6, iclass 23, count 0 2006.257.01:32:56.47#ibcon#read 6, iclass 23, count 0 2006.257.01:32:56.47#ibcon#end of sib2, iclass 23, count 0 2006.257.01:32:56.47#ibcon#*after write, iclass 23, count 0 2006.257.01:32:56.47#ibcon#*before return 0, iclass 23, count 0 2006.257.01:32:56.47#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.01:32:56.47#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.01:32:56.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.01:32:56.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.01:32:56.47$setupk4/ifdk4 2006.257.01:32:56.47&ifdk4/lo= 2006.257.01:32:56.47&ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.01:32:56.47&ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.01:32:56.47&ifdk4/patch= 2006.257.01:32:56.47&ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.01:32:56.47&ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.01:32:56.47$ifdk4/lo= 2006.257.01:32:56.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.01:32:56.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.01:32:56.47$ifdk4/patch= 2006.257.01:32:56.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.01:32:56.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.01:32:56.47$setupk4/!*+20s 2006.257.01:32:56.47$exper_initi/proc_library 2006.257.01:32:56.47&proc_library/" jd0609 tsukub32 ts 2006.257.01:32:56.47&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.257.01:32:56.47&proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.257.01:32:56.47$proc_library/" jd0609 tsukub32 ts 2006.257.01:32:56.47$proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.257.01:32:56.47$proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.257.01:32:56.47$exper_initi/sched_initi 2006.257.01:32:56.47&sched_initi/startcheck 2006.257.01:32:56.47$sched_initi/startcheck 2006.257.01:32:56.47&startcheck/sy=check_fsrun.pl & 2006.257.01:32:56.47&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.257.01:32:56.47$startcheck/sy=check_fsrun.pl & 2006.257.01:32:56.50$startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.257.01:33:01.63;unstow 2006.257.01:33:01.63&unstow/antenna=e 2006.257.01:33:01.63&unstow/!+10s 2006.257.01:33:01.63&unstow/antenna=m2 2006.257.01:33:01.63$unstow/antenna=e 2006.257.01:33:02.01$unstow/!+10s 2006.257.01:33:02.85#abcon#<5=/15 1.5 4.1 17.591001013.0\r\n> 2006.257.01:33:02.87#abcon#{5=INTERFACE CLEAR} 2006.257.01:33:02.95#abcon#[5=S1D000X0/0*\r\n] 2006.257.01:33:10.84$setupk4/"tpicd 2006.257.01:33:10.84$setupk4/echo=off 2006.257.01:33:10.84$setupk4/xlog=off 2006.257.01:33:10.84:"ready=1 2006.257.01:33:10.84:setupk4=1 2006.257.01:33:10.84$setupk4/echo=on 2006.257.01:33:10.84$setupk4/pcalon 2006.257.01:33:10.84$pcalon/"no phase cal control is implemented here 2006.257.01:33:10.84$setupk4/"tpicd=stop 2006.257.01:33:10.84$setupk4/"rec=synch_on 2006.257.01:33:10.84$setupk4/"rec_mode=128 2006.257.01:33:10.84$setupk4/!* 2006.257.01:33:10.84$setupk4/recpk4 2006.257.01:33:10.84$recpk4/recpatch= 2006.257.01:33:10.84$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.01:33:10.84$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.01:33:10.84$setupk4/vck44 2006.257.01:33:10.84$vck44/valo=1,524.99 2006.257.01:33:10.84#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.01:33:10.84#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.01:33:10.84#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:10.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:10.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:10.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:10.84#ibcon#enter wrdev, iclass 18, count 0 2006.257.01:33:10.84#ibcon#first serial, iclass 18, count 0 2006.257.01:33:10.84#ibcon#enter sib2, iclass 18, count 0 2006.257.01:33:10.84#ibcon#flushed, iclass 18, count 0 2006.257.01:33:10.84#ibcon#about to write, iclass 18, count 0 2006.257.01:33:10.84#ibcon#wrote, iclass 18, count 0 2006.257.01:33:10.84#ibcon#about to read 3, iclass 18, count 0 2006.257.01:33:10.86#ibcon#read 3, iclass 18, count 0 2006.257.01:33:10.86#ibcon#about to read 4, iclass 18, count 0 2006.257.01:33:10.86#ibcon#read 4, iclass 18, count 0 2006.257.01:33:10.86#ibcon#about to read 5, iclass 18, count 0 2006.257.01:33:10.86#ibcon#read 5, iclass 18, count 0 2006.257.01:33:10.86#ibcon#about to read 6, iclass 18, count 0 2006.257.01:33:10.86#ibcon#read 6, iclass 18, count 0 2006.257.01:33:10.86#ibcon#end of sib2, iclass 18, count 0 2006.257.01:33:10.86#ibcon#*mode == 0, iclass 18, count 0 2006.257.01:33:10.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.01:33:10.86#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.01:33:10.86#ibcon#*before write, iclass 18, count 0 2006.257.01:33:10.86#ibcon#enter sib2, iclass 18, count 0 2006.257.01:33:10.86#ibcon#flushed, iclass 18, count 0 2006.257.01:33:10.86#ibcon#about to write, iclass 18, count 0 2006.257.01:33:10.86#ibcon#wrote, iclass 18, count 0 2006.257.01:33:10.86#ibcon#about to read 3, iclass 18, count 0 2006.257.01:33:10.90#ibcon#read 3, iclass 18, count 0 2006.257.01:33:10.90#ibcon#about to read 4, iclass 18, count 0 2006.257.01:33:10.90#ibcon#read 4, iclass 18, count 0 2006.257.01:33:10.90#ibcon#about to read 5, iclass 18, count 0 2006.257.01:33:10.90#ibcon#read 5, iclass 18, count 0 2006.257.01:33:10.90#ibcon#about to read 6, iclass 18, count 0 2006.257.01:33:10.90#ibcon#read 6, iclass 18, count 0 2006.257.01:33:10.90#ibcon#end of sib2, iclass 18, count 0 2006.257.01:33:10.90#ibcon#*after write, iclass 18, count 0 2006.257.01:33:10.90#ibcon#*before return 0, iclass 18, count 0 2006.257.01:33:10.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:10.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:10.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.01:33:10.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.01:33:10.91$vck44/va=1,8 2006.257.01:33:10.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.01:33:10.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.01:33:10.91#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:10.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:10.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:10.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:10.91#ibcon#enter wrdev, iclass 20, count 2 2006.257.01:33:10.91#ibcon#first serial, iclass 20, count 2 2006.257.01:33:10.91#ibcon#enter sib2, iclass 20, count 2 2006.257.01:33:10.91#ibcon#flushed, iclass 20, count 2 2006.257.01:33:10.91#ibcon#about to write, iclass 20, count 2 2006.257.01:33:10.91#ibcon#wrote, iclass 20, count 2 2006.257.01:33:10.91#ibcon#about to read 3, iclass 20, count 2 2006.257.01:33:10.93#ibcon#read 3, iclass 20, count 2 2006.257.01:33:10.93#ibcon#about to read 4, iclass 20, count 2 2006.257.01:33:10.93#ibcon#read 4, iclass 20, count 2 2006.257.01:33:10.93#ibcon#about to read 5, iclass 20, count 2 2006.257.01:33:10.93#ibcon#read 5, iclass 20, count 2 2006.257.01:33:10.93#ibcon#about to read 6, iclass 20, count 2 2006.257.01:33:10.93#ibcon#read 6, iclass 20, count 2 2006.257.01:33:10.93#ibcon#end of sib2, iclass 20, count 2 2006.257.01:33:10.93#ibcon#*mode == 0, iclass 20, count 2 2006.257.01:33:10.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.01:33:10.93#ibcon#[25=AT01-08\r\n] 2006.257.01:33:10.93#ibcon#*before write, iclass 20, count 2 2006.257.01:33:10.93#ibcon#enter sib2, iclass 20, count 2 2006.257.01:33:10.93#ibcon#flushed, iclass 20, count 2 2006.257.01:33:10.93#ibcon#about to write, iclass 20, count 2 2006.257.01:33:10.93#ibcon#wrote, iclass 20, count 2 2006.257.01:33:10.93#ibcon#about to read 3, iclass 20, count 2 2006.257.01:33:10.96#ibcon#read 3, iclass 20, count 2 2006.257.01:33:10.96#ibcon#about to read 4, iclass 20, count 2 2006.257.01:33:10.96#ibcon#read 4, iclass 20, count 2 2006.257.01:33:10.96#ibcon#about to read 5, iclass 20, count 2 2006.257.01:33:10.96#ibcon#read 5, iclass 20, count 2 2006.257.01:33:10.96#ibcon#about to read 6, iclass 20, count 2 2006.257.01:33:10.96#ibcon#read 6, iclass 20, count 2 2006.257.01:33:10.96#ibcon#end of sib2, iclass 20, count 2 2006.257.01:33:10.96#ibcon#*after write, iclass 20, count 2 2006.257.01:33:10.96#ibcon#*before return 0, iclass 20, count 2 2006.257.01:33:10.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:10.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:10.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.01:33:10.96#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:10.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:11.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:11.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:11.08#ibcon#enter wrdev, iclass 20, count 0 2006.257.01:33:11.08#ibcon#first serial, iclass 20, count 0 2006.257.01:33:11.08#ibcon#enter sib2, iclass 20, count 0 2006.257.01:33:11.08#ibcon#flushed, iclass 20, count 0 2006.257.01:33:11.08#ibcon#about to write, iclass 20, count 0 2006.257.01:33:11.08#ibcon#wrote, iclass 20, count 0 2006.257.01:33:11.08#ibcon#about to read 3, iclass 20, count 0 2006.257.01:33:11.10#ibcon#read 3, iclass 20, count 0 2006.257.01:33:11.10#ibcon#about to read 4, iclass 20, count 0 2006.257.01:33:11.10#ibcon#read 4, iclass 20, count 0 2006.257.01:33:11.10#ibcon#about to read 5, iclass 20, count 0 2006.257.01:33:11.10#ibcon#read 5, iclass 20, count 0 2006.257.01:33:11.10#ibcon#about to read 6, iclass 20, count 0 2006.257.01:33:11.10#ibcon#read 6, iclass 20, count 0 2006.257.01:33:11.10#ibcon#end of sib2, iclass 20, count 0 2006.257.01:33:11.10#ibcon#*mode == 0, iclass 20, count 0 2006.257.01:33:11.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.01:33:11.10#ibcon#[25=USB\r\n] 2006.257.01:33:11.10#ibcon#*before write, iclass 20, count 0 2006.257.01:33:11.10#ibcon#enter sib2, iclass 20, count 0 2006.257.01:33:11.10#ibcon#flushed, iclass 20, count 0 2006.257.01:33:11.10#ibcon#about to write, iclass 20, count 0 2006.257.01:33:11.10#ibcon#wrote, iclass 20, count 0 2006.257.01:33:11.10#ibcon#about to read 3, iclass 20, count 0 2006.257.01:33:11.13#ibcon#read 3, iclass 20, count 0 2006.257.01:33:11.13#ibcon#about to read 4, iclass 20, count 0 2006.257.01:33:11.13#ibcon#read 4, iclass 20, count 0 2006.257.01:33:11.13#ibcon#about to read 5, iclass 20, count 0 2006.257.01:33:11.13#ibcon#read 5, iclass 20, count 0 2006.257.01:33:11.13#ibcon#about to read 6, iclass 20, count 0 2006.257.01:33:11.13#ibcon#read 6, iclass 20, count 0 2006.257.01:33:11.13#ibcon#end of sib2, iclass 20, count 0 2006.257.01:33:11.13#ibcon#*after write, iclass 20, count 0 2006.257.01:33:11.13#ibcon#*before return 0, iclass 20, count 0 2006.257.01:33:11.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:11.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:11.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.01:33:11.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.01:33:11.13$vck44/valo=2,534.99 2006.257.01:33:11.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.01:33:11.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.01:33:11.13#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:11.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:11.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:11.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:11.13#ibcon#enter wrdev, iclass 22, count 0 2006.257.01:33:11.13#ibcon#first serial, iclass 22, count 0 2006.257.01:33:11.13#ibcon#enter sib2, iclass 22, count 0 2006.257.01:33:11.13#ibcon#flushed, iclass 22, count 0 2006.257.01:33:11.13#ibcon#about to write, iclass 22, count 0 2006.257.01:33:11.13#ibcon#wrote, iclass 22, count 0 2006.257.01:33:11.13#ibcon#about to read 3, iclass 22, count 0 2006.257.01:33:11.14#trakl#Antenna stuck 2006.257.01:33:11.15#ibcon#read 3, iclass 22, count 0 2006.257.01:33:11.15#ibcon#about to read 4, iclass 22, count 0 2006.257.01:33:11.15#ibcon#read 4, iclass 22, count 0 2006.257.01:33:11.15#ibcon#about to read 5, iclass 22, count 0 2006.257.01:33:11.15#ibcon#read 5, iclass 22, count 0 2006.257.01:33:11.15#ibcon#about to read 6, iclass 22, count 0 2006.257.01:33:11.15#ibcon#read 6, iclass 22, count 0 2006.257.01:33:11.15#ibcon#end of sib2, iclass 22, count 0 2006.257.01:33:11.15#ibcon#*mode == 0, iclass 22, count 0 2006.257.01:33:11.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.01:33:11.15#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.01:33:11.15#ibcon#*before write, iclass 22, count 0 2006.257.01:33:11.15#ibcon#enter sib2, iclass 22, count 0 2006.257.01:33:11.15#ibcon#flushed, iclass 22, count 0 2006.257.01:33:11.15#ibcon#about to write, iclass 22, count 0 2006.257.01:33:11.15#ibcon#wrote, iclass 22, count 0 2006.257.01:33:11.15#ibcon#about to read 3, iclass 22, count 0 2006.257.01:33:11.19#ibcon#read 3, iclass 22, count 0 2006.257.01:33:11.19#ibcon#about to read 4, iclass 22, count 0 2006.257.01:33:11.19#ibcon#read 4, iclass 22, count 0 2006.257.01:33:11.19#ibcon#about to read 5, iclass 22, count 0 2006.257.01:33:11.19#ibcon#read 5, iclass 22, count 0 2006.257.01:33:11.19#ibcon#about to read 6, iclass 22, count 0 2006.257.01:33:11.19#ibcon#read 6, iclass 22, count 0 2006.257.01:33:11.19#ibcon#end of sib2, iclass 22, count 0 2006.257.01:33:11.19#ibcon#*after write, iclass 22, count 0 2006.257.01:33:11.19#ibcon#*before return 0, iclass 22, count 0 2006.257.01:33:11.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:11.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:11.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.01:33:11.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.01:33:11.19$vck44/va=2,7 2006.257.01:33:11.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.01:33:11.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.01:33:11.19#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:11.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:11.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:11.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:11.25#ibcon#enter wrdev, iclass 24, count 2 2006.257.01:33:11.25#ibcon#first serial, iclass 24, count 2 2006.257.01:33:11.25#ibcon#enter sib2, iclass 24, count 2 2006.257.01:33:11.25#ibcon#flushed, iclass 24, count 2 2006.257.01:33:11.25#ibcon#about to write, iclass 24, count 2 2006.257.01:33:11.25#ibcon#wrote, iclass 24, count 2 2006.257.01:33:11.25#ibcon#about to read 3, iclass 24, count 2 2006.257.01:33:11.27#ibcon#read 3, iclass 24, count 2 2006.257.01:33:11.27#ibcon#about to read 4, iclass 24, count 2 2006.257.01:33:11.27#ibcon#read 4, iclass 24, count 2 2006.257.01:33:11.27#ibcon#about to read 5, iclass 24, count 2 2006.257.01:33:11.27#ibcon#read 5, iclass 24, count 2 2006.257.01:33:11.27#ibcon#about to read 6, iclass 24, count 2 2006.257.01:33:11.27#ibcon#read 6, iclass 24, count 2 2006.257.01:33:11.27#ibcon#end of sib2, iclass 24, count 2 2006.257.01:33:11.27#ibcon#*mode == 0, iclass 24, count 2 2006.257.01:33:11.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.01:33:11.27#ibcon#[25=AT02-07\r\n] 2006.257.01:33:11.27#ibcon#*before write, iclass 24, count 2 2006.257.01:33:11.27#ibcon#enter sib2, iclass 24, count 2 2006.257.01:33:11.27#ibcon#flushed, iclass 24, count 2 2006.257.01:33:11.27#ibcon#about to write, iclass 24, count 2 2006.257.01:33:11.27#ibcon#wrote, iclass 24, count 2 2006.257.01:33:11.27#ibcon#about to read 3, iclass 24, count 2 2006.257.01:33:11.30#ibcon#read 3, iclass 24, count 2 2006.257.01:33:11.30#ibcon#about to read 4, iclass 24, count 2 2006.257.01:33:11.30#ibcon#read 4, iclass 24, count 2 2006.257.01:33:11.30#ibcon#about to read 5, iclass 24, count 2 2006.257.01:33:11.30#ibcon#read 5, iclass 24, count 2 2006.257.01:33:11.30#ibcon#about to read 6, iclass 24, count 2 2006.257.01:33:11.30#ibcon#read 6, iclass 24, count 2 2006.257.01:33:11.30#ibcon#end of sib2, iclass 24, count 2 2006.257.01:33:11.30#ibcon#*after write, iclass 24, count 2 2006.257.01:33:11.30#ibcon#*before return 0, iclass 24, count 2 2006.257.01:33:11.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:11.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:11.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.01:33:11.30#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:11.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:11.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:11.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:11.42#ibcon#enter wrdev, iclass 24, count 0 2006.257.01:33:11.42#ibcon#first serial, iclass 24, count 0 2006.257.01:33:11.42#ibcon#enter sib2, iclass 24, count 0 2006.257.01:33:11.42#ibcon#flushed, iclass 24, count 0 2006.257.01:33:11.42#ibcon#about to write, iclass 24, count 0 2006.257.01:33:11.42#ibcon#wrote, iclass 24, count 0 2006.257.01:33:11.42#ibcon#about to read 3, iclass 24, count 0 2006.257.01:33:11.44#ibcon#read 3, iclass 24, count 0 2006.257.01:33:11.44#ibcon#about to read 4, iclass 24, count 0 2006.257.01:33:11.44#ibcon#read 4, iclass 24, count 0 2006.257.01:33:11.44#ibcon#about to read 5, iclass 24, count 0 2006.257.01:33:11.44#ibcon#read 5, iclass 24, count 0 2006.257.01:33:11.44#ibcon#about to read 6, iclass 24, count 0 2006.257.01:33:11.44#ibcon#read 6, iclass 24, count 0 2006.257.01:33:11.44#ibcon#end of sib2, iclass 24, count 0 2006.257.01:33:11.44#ibcon#*mode == 0, iclass 24, count 0 2006.257.01:33:11.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.01:33:11.44#ibcon#[25=USB\r\n] 2006.257.01:33:11.44#ibcon#*before write, iclass 24, count 0 2006.257.01:33:11.44#ibcon#enter sib2, iclass 24, count 0 2006.257.01:33:11.44#ibcon#flushed, iclass 24, count 0 2006.257.01:33:11.44#ibcon#about to write, iclass 24, count 0 2006.257.01:33:11.44#ibcon#wrote, iclass 24, count 0 2006.257.01:33:11.44#ibcon#about to read 3, iclass 24, count 0 2006.257.01:33:11.47#ibcon#read 3, iclass 24, count 0 2006.257.01:33:11.47#ibcon#about to read 4, iclass 24, count 0 2006.257.01:33:11.47#ibcon#read 4, iclass 24, count 0 2006.257.01:33:11.47#ibcon#about to read 5, iclass 24, count 0 2006.257.01:33:11.47#ibcon#read 5, iclass 24, count 0 2006.257.01:33:11.47#ibcon#about to read 6, iclass 24, count 0 2006.257.01:33:11.47#ibcon#read 6, iclass 24, count 0 2006.257.01:33:11.47#ibcon#end of sib2, iclass 24, count 0 2006.257.01:33:11.47#ibcon#*after write, iclass 24, count 0 2006.257.01:33:11.47#ibcon#*before return 0, iclass 24, count 0 2006.257.01:33:11.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:11.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:11.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.01:33:11.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.01:33:11.47$vck44/valo=3,564.99 2006.257.01:33:11.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.01:33:11.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.01:33:11.47#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:11.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:11.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:11.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:11.47#ibcon#enter wrdev, iclass 26, count 0 2006.257.01:33:11.47#ibcon#first serial, iclass 26, count 0 2006.257.01:33:11.47#ibcon#enter sib2, iclass 26, count 0 2006.257.01:33:11.47#ibcon#flushed, iclass 26, count 0 2006.257.01:33:11.47#ibcon#about to write, iclass 26, count 0 2006.257.01:33:11.47#ibcon#wrote, iclass 26, count 0 2006.257.01:33:11.47#ibcon#about to read 3, iclass 26, count 0 2006.257.01:33:11.49#ibcon#read 3, iclass 26, count 0 2006.257.01:33:11.49#ibcon#about to read 4, iclass 26, count 0 2006.257.01:33:11.49#ibcon#read 4, iclass 26, count 0 2006.257.01:33:11.49#ibcon#about to read 5, iclass 26, count 0 2006.257.01:33:11.49#ibcon#read 5, iclass 26, count 0 2006.257.01:33:11.49#ibcon#about to read 6, iclass 26, count 0 2006.257.01:33:11.49#ibcon#read 6, iclass 26, count 0 2006.257.01:33:11.49#ibcon#end of sib2, iclass 26, count 0 2006.257.01:33:11.49#ibcon#*mode == 0, iclass 26, count 0 2006.257.01:33:11.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.01:33:11.49#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.01:33:11.49#ibcon#*before write, iclass 26, count 0 2006.257.01:33:11.49#ibcon#enter sib2, iclass 26, count 0 2006.257.01:33:11.49#ibcon#flushed, iclass 26, count 0 2006.257.01:33:11.49#ibcon#about to write, iclass 26, count 0 2006.257.01:33:11.49#ibcon#wrote, iclass 26, count 0 2006.257.01:33:11.49#ibcon#about to read 3, iclass 26, count 0 2006.257.01:33:11.53#ibcon#read 3, iclass 26, count 0 2006.257.01:33:11.53#ibcon#about to read 4, iclass 26, count 0 2006.257.01:33:11.53#ibcon#read 4, iclass 26, count 0 2006.257.01:33:11.53#ibcon#about to read 5, iclass 26, count 0 2006.257.01:33:11.53#ibcon#read 5, iclass 26, count 0 2006.257.01:33:11.53#ibcon#about to read 6, iclass 26, count 0 2006.257.01:33:11.53#ibcon#read 6, iclass 26, count 0 2006.257.01:33:11.53#ibcon#end of sib2, iclass 26, count 0 2006.257.01:33:11.53#ibcon#*after write, iclass 26, count 0 2006.257.01:33:11.53#ibcon#*before return 0, iclass 26, count 0 2006.257.01:33:11.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:11.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:11.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.01:33:11.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.01:33:11.53$vck44/va=3,8 2006.257.01:33:11.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.01:33:11.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.01:33:11.53#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:11.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:11.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:11.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:11.59#ibcon#enter wrdev, iclass 28, count 2 2006.257.01:33:11.59#ibcon#first serial, iclass 28, count 2 2006.257.01:33:11.59#ibcon#enter sib2, iclass 28, count 2 2006.257.01:33:11.59#ibcon#flushed, iclass 28, count 2 2006.257.01:33:11.59#ibcon#about to write, iclass 28, count 2 2006.257.01:33:11.59#ibcon#wrote, iclass 28, count 2 2006.257.01:33:11.59#ibcon#about to read 3, iclass 28, count 2 2006.257.01:33:11.61#ibcon#read 3, iclass 28, count 2 2006.257.01:33:11.61#ibcon#about to read 4, iclass 28, count 2 2006.257.01:33:11.61#ibcon#read 4, iclass 28, count 2 2006.257.01:33:11.61#ibcon#about to read 5, iclass 28, count 2 2006.257.01:33:11.61#ibcon#read 5, iclass 28, count 2 2006.257.01:33:11.61#ibcon#about to read 6, iclass 28, count 2 2006.257.01:33:11.61#ibcon#read 6, iclass 28, count 2 2006.257.01:33:11.61#ibcon#end of sib2, iclass 28, count 2 2006.257.01:33:11.61#ibcon#*mode == 0, iclass 28, count 2 2006.257.01:33:11.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.01:33:11.61#ibcon#[25=AT03-08\r\n] 2006.257.01:33:11.61#ibcon#*before write, iclass 28, count 2 2006.257.01:33:11.61#ibcon#enter sib2, iclass 28, count 2 2006.257.01:33:11.61#ibcon#flushed, iclass 28, count 2 2006.257.01:33:11.61#ibcon#about to write, iclass 28, count 2 2006.257.01:33:11.61#ibcon#wrote, iclass 28, count 2 2006.257.01:33:11.61#ibcon#about to read 3, iclass 28, count 2 2006.257.01:33:11.64#ibcon#read 3, iclass 28, count 2 2006.257.01:33:11.64#ibcon#about to read 4, iclass 28, count 2 2006.257.01:33:11.64#ibcon#read 4, iclass 28, count 2 2006.257.01:33:11.64#ibcon#about to read 5, iclass 28, count 2 2006.257.01:33:11.64#ibcon#read 5, iclass 28, count 2 2006.257.01:33:11.64#ibcon#about to read 6, iclass 28, count 2 2006.257.01:33:11.64#ibcon#read 6, iclass 28, count 2 2006.257.01:33:11.64#ibcon#end of sib2, iclass 28, count 2 2006.257.01:33:11.64#ibcon#*after write, iclass 28, count 2 2006.257.01:33:11.64#ibcon#*before return 0, iclass 28, count 2 2006.257.01:33:11.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:11.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:11.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.01:33:11.64#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:11.64#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:11.76#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:11.76#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:11.76#ibcon#enter wrdev, iclass 28, count 0 2006.257.01:33:11.76#ibcon#first serial, iclass 28, count 0 2006.257.01:33:11.76#ibcon#enter sib2, iclass 28, count 0 2006.257.01:33:11.76#ibcon#flushed, iclass 28, count 0 2006.257.01:33:11.76#ibcon#about to write, iclass 28, count 0 2006.257.01:33:11.76#ibcon#wrote, iclass 28, count 0 2006.257.01:33:11.76#ibcon#about to read 3, iclass 28, count 0 2006.257.01:33:11.78#ibcon#read 3, iclass 28, count 0 2006.257.01:33:11.78#ibcon#about to read 4, iclass 28, count 0 2006.257.01:33:11.78#ibcon#read 4, iclass 28, count 0 2006.257.01:33:11.78#ibcon#about to read 5, iclass 28, count 0 2006.257.01:33:11.78#ibcon#read 5, iclass 28, count 0 2006.257.01:33:11.78#ibcon#about to read 6, iclass 28, count 0 2006.257.01:33:11.78#ibcon#read 6, iclass 28, count 0 2006.257.01:33:11.78#ibcon#end of sib2, iclass 28, count 0 2006.257.01:33:11.78#ibcon#*mode == 0, iclass 28, count 0 2006.257.01:33:11.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.01:33:11.78#ibcon#[25=USB\r\n] 2006.257.01:33:11.78#ibcon#*before write, iclass 28, count 0 2006.257.01:33:11.78#ibcon#enter sib2, iclass 28, count 0 2006.257.01:33:11.78#ibcon#flushed, iclass 28, count 0 2006.257.01:33:11.78#ibcon#about to write, iclass 28, count 0 2006.257.01:33:11.78#ibcon#wrote, iclass 28, count 0 2006.257.01:33:11.78#ibcon#about to read 3, iclass 28, count 0 2006.257.01:33:11.81#ibcon#read 3, iclass 28, count 0 2006.257.01:33:11.81#ibcon#about to read 4, iclass 28, count 0 2006.257.01:33:11.81#ibcon#read 4, iclass 28, count 0 2006.257.01:33:11.81#ibcon#about to read 5, iclass 28, count 0 2006.257.01:33:11.81#ibcon#read 5, iclass 28, count 0 2006.257.01:33:11.81#ibcon#about to read 6, iclass 28, count 0 2006.257.01:33:11.81#ibcon#read 6, iclass 28, count 0 2006.257.01:33:11.81#ibcon#end of sib2, iclass 28, count 0 2006.257.01:33:11.81#ibcon#*after write, iclass 28, count 0 2006.257.01:33:11.81#ibcon#*before return 0, iclass 28, count 0 2006.257.01:33:11.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:11.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:11.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.01:33:11.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.01:33:11.81$vck44/valo=4,624.99 2006.257.01:33:11.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.01:33:11.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.01:33:11.81#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:11.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:11.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:11.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:11.81#ibcon#enter wrdev, iclass 30, count 0 2006.257.01:33:11.81#ibcon#first serial, iclass 30, count 0 2006.257.01:33:11.81#ibcon#enter sib2, iclass 30, count 0 2006.257.01:33:11.81#ibcon#flushed, iclass 30, count 0 2006.257.01:33:11.81#ibcon#about to write, iclass 30, count 0 2006.257.01:33:11.81#ibcon#wrote, iclass 30, count 0 2006.257.01:33:11.81#ibcon#about to read 3, iclass 30, count 0 2006.257.01:33:11.83#ibcon#read 3, iclass 30, count 0 2006.257.01:33:11.83#ibcon#about to read 4, iclass 30, count 0 2006.257.01:33:11.83#ibcon#read 4, iclass 30, count 0 2006.257.01:33:11.83#ibcon#about to read 5, iclass 30, count 0 2006.257.01:33:11.83#ibcon#read 5, iclass 30, count 0 2006.257.01:33:11.83#ibcon#about to read 6, iclass 30, count 0 2006.257.01:33:11.83#ibcon#read 6, iclass 30, count 0 2006.257.01:33:11.83#ibcon#end of sib2, iclass 30, count 0 2006.257.01:33:11.83#ibcon#*mode == 0, iclass 30, count 0 2006.257.01:33:11.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.01:33:11.83#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.01:33:11.83#ibcon#*before write, iclass 30, count 0 2006.257.01:33:11.83#ibcon#enter sib2, iclass 30, count 0 2006.257.01:33:11.83#ibcon#flushed, iclass 30, count 0 2006.257.01:33:11.83#ibcon#about to write, iclass 30, count 0 2006.257.01:33:11.83#ibcon#wrote, iclass 30, count 0 2006.257.01:33:11.83#ibcon#about to read 3, iclass 30, count 0 2006.257.01:33:11.87#ibcon#read 3, iclass 30, count 0 2006.257.01:33:11.87#ibcon#about to read 4, iclass 30, count 0 2006.257.01:33:11.87#ibcon#read 4, iclass 30, count 0 2006.257.01:33:11.87#ibcon#about to read 5, iclass 30, count 0 2006.257.01:33:11.87#ibcon#read 5, iclass 30, count 0 2006.257.01:33:11.87#ibcon#about to read 6, iclass 30, count 0 2006.257.01:33:11.87#ibcon#read 6, iclass 30, count 0 2006.257.01:33:11.87#ibcon#end of sib2, iclass 30, count 0 2006.257.01:33:11.87#ibcon#*after write, iclass 30, count 0 2006.257.01:33:11.87#ibcon#*before return 0, iclass 30, count 0 2006.257.01:33:11.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:11.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:11.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.01:33:11.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.01:33:11.87$vck44/va=4,7 2006.257.01:33:11.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.01:33:11.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.01:33:11.87#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:11.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:11.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:11.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:11.93#ibcon#enter wrdev, iclass 32, count 2 2006.257.01:33:11.93#ibcon#first serial, iclass 32, count 2 2006.257.01:33:11.93#ibcon#enter sib2, iclass 32, count 2 2006.257.01:33:11.93#ibcon#flushed, iclass 32, count 2 2006.257.01:33:11.93#ibcon#about to write, iclass 32, count 2 2006.257.01:33:11.93#ibcon#wrote, iclass 32, count 2 2006.257.01:33:11.93#ibcon#about to read 3, iclass 32, count 2 2006.257.01:33:11.95#ibcon#read 3, iclass 32, count 2 2006.257.01:33:11.95#ibcon#about to read 4, iclass 32, count 2 2006.257.01:33:11.95#ibcon#read 4, iclass 32, count 2 2006.257.01:33:11.95#ibcon#about to read 5, iclass 32, count 2 2006.257.01:33:11.95#ibcon#read 5, iclass 32, count 2 2006.257.01:33:11.95#ibcon#about to read 6, iclass 32, count 2 2006.257.01:33:11.95#ibcon#read 6, iclass 32, count 2 2006.257.01:33:11.95#ibcon#end of sib2, iclass 32, count 2 2006.257.01:33:11.95#ibcon#*mode == 0, iclass 32, count 2 2006.257.01:33:11.95#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.01:33:11.95#ibcon#[25=AT04-07\r\n] 2006.257.01:33:11.95#ibcon#*before write, iclass 32, count 2 2006.257.01:33:11.95#ibcon#enter sib2, iclass 32, count 2 2006.257.01:33:11.95#ibcon#flushed, iclass 32, count 2 2006.257.01:33:11.95#ibcon#about to write, iclass 32, count 2 2006.257.01:33:11.95#ibcon#wrote, iclass 32, count 2 2006.257.01:33:11.95#ibcon#about to read 3, iclass 32, count 2 2006.257.01:33:11.98#ibcon#read 3, iclass 32, count 2 2006.257.01:33:11.98#ibcon#about to read 4, iclass 32, count 2 2006.257.01:33:11.98#ibcon#read 4, iclass 32, count 2 2006.257.01:33:11.98#ibcon#about to read 5, iclass 32, count 2 2006.257.01:33:11.98#ibcon#read 5, iclass 32, count 2 2006.257.01:33:11.98#ibcon#about to read 6, iclass 32, count 2 2006.257.01:33:11.98#ibcon#read 6, iclass 32, count 2 2006.257.01:33:11.98#ibcon#end of sib2, iclass 32, count 2 2006.257.01:33:11.98#ibcon#*after write, iclass 32, count 2 2006.257.01:33:11.98#ibcon#*before return 0, iclass 32, count 2 2006.257.01:33:11.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:11.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:11.98#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.01:33:11.98#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:11.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:12.10#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:12.10#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:12.10#ibcon#enter wrdev, iclass 32, count 0 2006.257.01:33:12.10#ibcon#first serial, iclass 32, count 0 2006.257.01:33:12.10#ibcon#enter sib2, iclass 32, count 0 2006.257.01:33:12.10#ibcon#flushed, iclass 32, count 0 2006.257.01:33:12.10#ibcon#about to write, iclass 32, count 0 2006.257.01:33:12.10#ibcon#wrote, iclass 32, count 0 2006.257.01:33:12.10#ibcon#about to read 3, iclass 32, count 0 2006.257.01:33:12.12#ibcon#read 3, iclass 32, count 0 2006.257.01:33:12.12#ibcon#about to read 4, iclass 32, count 0 2006.257.01:33:12.12#ibcon#read 4, iclass 32, count 0 2006.257.01:33:12.12#ibcon#about to read 5, iclass 32, count 0 2006.257.01:33:12.12#ibcon#read 5, iclass 32, count 0 2006.257.01:33:12.12#ibcon#about to read 6, iclass 32, count 0 2006.257.01:33:12.12#ibcon#read 6, iclass 32, count 0 2006.257.01:33:12.12#ibcon#end of sib2, iclass 32, count 0 2006.257.01:33:12.12#ibcon#*mode == 0, iclass 32, count 0 2006.257.01:33:12.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.01:33:12.12#ibcon#[25=USB\r\n] 2006.257.01:33:12.12#ibcon#*before write, iclass 32, count 0 2006.257.01:33:12.12#ibcon#enter sib2, iclass 32, count 0 2006.257.01:33:12.12#ibcon#flushed, iclass 32, count 0 2006.257.01:33:12.12#ibcon#about to write, iclass 32, count 0 2006.257.01:33:12.12#ibcon#wrote, iclass 32, count 0 2006.257.01:33:12.12#ibcon#about to read 3, iclass 32, count 0 2006.257.01:33:12.15#ibcon#read 3, iclass 32, count 0 2006.257.01:33:12.15#ibcon#about to read 4, iclass 32, count 0 2006.257.01:33:12.15#ibcon#read 4, iclass 32, count 0 2006.257.01:33:12.15#ibcon#about to read 5, iclass 32, count 0 2006.257.01:33:12.15#ibcon#read 5, iclass 32, count 0 2006.257.01:33:12.15#ibcon#about to read 6, iclass 32, count 0 2006.257.01:33:12.15#ibcon#read 6, iclass 32, count 0 2006.257.01:33:12.15#ibcon#end of sib2, iclass 32, count 0 2006.257.01:33:12.15#ibcon#*after write, iclass 32, count 0 2006.257.01:33:12.15#ibcon#*before return 0, iclass 32, count 0 2006.257.01:33:12.15#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:12.15#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:12.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.01:33:12.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.01:33:12.15$vck44/valo=5,734.99 2006.257.01:33:12.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.01:33:12.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.01:33:12.15#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:12.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:12.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:12.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:12.15#ibcon#enter wrdev, iclass 34, count 0 2006.257.01:33:12.15#ibcon#first serial, iclass 34, count 0 2006.257.01:33:12.15#ibcon#enter sib2, iclass 34, count 0 2006.257.01:33:12.15#ibcon#flushed, iclass 34, count 0 2006.257.01:33:12.15#ibcon#about to write, iclass 34, count 0 2006.257.01:33:12.15#ibcon#wrote, iclass 34, count 0 2006.257.01:33:12.15#ibcon#about to read 3, iclass 34, count 0 2006.257.01:33:12.17#ibcon#read 3, iclass 34, count 0 2006.257.01:33:12.17#ibcon#about to read 4, iclass 34, count 0 2006.257.01:33:12.17#ibcon#read 4, iclass 34, count 0 2006.257.01:33:12.17#ibcon#about to read 5, iclass 34, count 0 2006.257.01:33:12.17#ibcon#read 5, iclass 34, count 0 2006.257.01:33:12.17#ibcon#about to read 6, iclass 34, count 0 2006.257.01:33:12.17#ibcon#read 6, iclass 34, count 0 2006.257.01:33:12.17#ibcon#end of sib2, iclass 34, count 0 2006.257.01:33:12.17#ibcon#*mode == 0, iclass 34, count 0 2006.257.01:33:12.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.01:33:12.17#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.01:33:12.17#ibcon#*before write, iclass 34, count 0 2006.257.01:33:12.17#ibcon#enter sib2, iclass 34, count 0 2006.257.01:33:12.17#ibcon#flushed, iclass 34, count 0 2006.257.01:33:12.17#ibcon#about to write, iclass 34, count 0 2006.257.01:33:12.17#ibcon#wrote, iclass 34, count 0 2006.257.01:33:12.17#ibcon#about to read 3, iclass 34, count 0 2006.257.01:33:12.21#ibcon#read 3, iclass 34, count 0 2006.257.01:33:12.21#ibcon#about to read 4, iclass 34, count 0 2006.257.01:33:12.21#ibcon#read 4, iclass 34, count 0 2006.257.01:33:12.21#ibcon#about to read 5, iclass 34, count 0 2006.257.01:33:12.21#ibcon#read 5, iclass 34, count 0 2006.257.01:33:12.21#ibcon#about to read 6, iclass 34, count 0 2006.257.01:33:12.21#ibcon#read 6, iclass 34, count 0 2006.257.01:33:12.21#ibcon#end of sib2, iclass 34, count 0 2006.257.01:33:12.21#ibcon#*after write, iclass 34, count 0 2006.257.01:33:12.21#ibcon#*before return 0, iclass 34, count 0 2006.257.01:33:12.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:12.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:12.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.01:33:12.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.01:33:12.21$vck44/va=5,4 2006.257.01:33:12.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.01:33:12.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.01:33:12.21#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:12.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:12.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:12.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:12.27#ibcon#enter wrdev, iclass 36, count 2 2006.257.01:33:12.27#ibcon#first serial, iclass 36, count 2 2006.257.01:33:12.27#ibcon#enter sib2, iclass 36, count 2 2006.257.01:33:12.27#ibcon#flushed, iclass 36, count 2 2006.257.01:33:12.27#ibcon#about to write, iclass 36, count 2 2006.257.01:33:12.27#ibcon#wrote, iclass 36, count 2 2006.257.01:33:12.27#ibcon#about to read 3, iclass 36, count 2 2006.257.01:33:12.29#ibcon#read 3, iclass 36, count 2 2006.257.01:33:12.29#ibcon#about to read 4, iclass 36, count 2 2006.257.01:33:12.29#ibcon#read 4, iclass 36, count 2 2006.257.01:33:12.29#ibcon#about to read 5, iclass 36, count 2 2006.257.01:33:12.29#ibcon#read 5, iclass 36, count 2 2006.257.01:33:12.29#ibcon#about to read 6, iclass 36, count 2 2006.257.01:33:12.29#ibcon#read 6, iclass 36, count 2 2006.257.01:33:12.29#ibcon#end of sib2, iclass 36, count 2 2006.257.01:33:12.29#ibcon#*mode == 0, iclass 36, count 2 2006.257.01:33:12.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.01:33:12.29#ibcon#[25=AT05-04\r\n] 2006.257.01:33:12.29#ibcon#*before write, iclass 36, count 2 2006.257.01:33:12.29#ibcon#enter sib2, iclass 36, count 2 2006.257.01:33:12.29#ibcon#flushed, iclass 36, count 2 2006.257.01:33:12.29#ibcon#about to write, iclass 36, count 2 2006.257.01:33:12.29#ibcon#wrote, iclass 36, count 2 2006.257.01:33:12.29#ibcon#about to read 3, iclass 36, count 2 2006.257.01:33:12.32#ibcon#read 3, iclass 36, count 2 2006.257.01:33:12.32#ibcon#about to read 4, iclass 36, count 2 2006.257.01:33:12.32#ibcon#read 4, iclass 36, count 2 2006.257.01:33:12.32#ibcon#about to read 5, iclass 36, count 2 2006.257.01:33:12.32#ibcon#read 5, iclass 36, count 2 2006.257.01:33:12.32#ibcon#about to read 6, iclass 36, count 2 2006.257.01:33:12.32#ibcon#read 6, iclass 36, count 2 2006.257.01:33:12.32#ibcon#end of sib2, iclass 36, count 2 2006.257.01:33:12.32#ibcon#*after write, iclass 36, count 2 2006.257.01:33:12.32#ibcon#*before return 0, iclass 36, count 2 2006.257.01:33:12.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:12.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:12.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.01:33:12.32#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:12.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:12.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:12.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:12.44#ibcon#enter wrdev, iclass 36, count 0 2006.257.01:33:12.44#ibcon#first serial, iclass 36, count 0 2006.257.01:33:12.44#ibcon#enter sib2, iclass 36, count 0 2006.257.01:33:12.44#ibcon#flushed, iclass 36, count 0 2006.257.01:33:12.44#ibcon#about to write, iclass 36, count 0 2006.257.01:33:12.44#ibcon#wrote, iclass 36, count 0 2006.257.01:33:12.44#ibcon#about to read 3, iclass 36, count 0 2006.257.01:33:12.46#ibcon#read 3, iclass 36, count 0 2006.257.01:33:12.46#ibcon#about to read 4, iclass 36, count 0 2006.257.01:33:12.46#ibcon#read 4, iclass 36, count 0 2006.257.01:33:12.46#ibcon#about to read 5, iclass 36, count 0 2006.257.01:33:12.46#ibcon#read 5, iclass 36, count 0 2006.257.01:33:12.46#ibcon#about to read 6, iclass 36, count 0 2006.257.01:33:12.46#ibcon#read 6, iclass 36, count 0 2006.257.01:33:12.46#ibcon#end of sib2, iclass 36, count 0 2006.257.01:33:12.46#ibcon#*mode == 0, iclass 36, count 0 2006.257.01:33:12.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.01:33:12.46#ibcon#[25=USB\r\n] 2006.257.01:33:12.46#ibcon#*before write, iclass 36, count 0 2006.257.01:33:12.46#ibcon#enter sib2, iclass 36, count 0 2006.257.01:33:12.46#ibcon#flushed, iclass 36, count 0 2006.257.01:33:12.46#ibcon#about to write, iclass 36, count 0 2006.257.01:33:12.46#ibcon#wrote, iclass 36, count 0 2006.257.01:33:12.46#ibcon#about to read 3, iclass 36, count 0 2006.257.01:33:12.49#ibcon#read 3, iclass 36, count 0 2006.257.01:33:12.49#ibcon#about to read 4, iclass 36, count 0 2006.257.01:33:12.49#ibcon#read 4, iclass 36, count 0 2006.257.01:33:12.49#ibcon#about to read 5, iclass 36, count 0 2006.257.01:33:12.49#ibcon#read 5, iclass 36, count 0 2006.257.01:33:12.49#ibcon#about to read 6, iclass 36, count 0 2006.257.01:33:12.49#ibcon#read 6, iclass 36, count 0 2006.257.01:33:12.49#ibcon#end of sib2, iclass 36, count 0 2006.257.01:33:12.49#ibcon#*after write, iclass 36, count 0 2006.257.01:33:12.49#ibcon#*before return 0, iclass 36, count 0 2006.257.01:33:12.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:12.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:12.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.01:33:12.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.01:33:12.49$vck44/valo=6,814.99 2006.257.01:33:12.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.01:33:12.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.01:33:12.49#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:12.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:12.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:12.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:12.49#ibcon#enter wrdev, iclass 38, count 0 2006.257.01:33:12.49#ibcon#first serial, iclass 38, count 0 2006.257.01:33:12.49#ibcon#enter sib2, iclass 38, count 0 2006.257.01:33:12.49#ibcon#flushed, iclass 38, count 0 2006.257.01:33:12.49#ibcon#about to write, iclass 38, count 0 2006.257.01:33:12.49#ibcon#wrote, iclass 38, count 0 2006.257.01:33:12.49#ibcon#about to read 3, iclass 38, count 0 2006.257.01:33:12.51#ibcon#read 3, iclass 38, count 0 2006.257.01:33:12.51#ibcon#about to read 4, iclass 38, count 0 2006.257.01:33:12.51#ibcon#read 4, iclass 38, count 0 2006.257.01:33:12.51#ibcon#about to read 5, iclass 38, count 0 2006.257.01:33:12.51#ibcon#read 5, iclass 38, count 0 2006.257.01:33:12.51#ibcon#about to read 6, iclass 38, count 0 2006.257.01:33:12.51#ibcon#read 6, iclass 38, count 0 2006.257.01:33:12.51#ibcon#end of sib2, iclass 38, count 0 2006.257.01:33:12.51#ibcon#*mode == 0, iclass 38, count 0 2006.257.01:33:12.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.01:33:12.51#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.01:33:12.51#ibcon#*before write, iclass 38, count 0 2006.257.01:33:12.51#ibcon#enter sib2, iclass 38, count 0 2006.257.01:33:12.51#ibcon#flushed, iclass 38, count 0 2006.257.01:33:12.51#ibcon#about to write, iclass 38, count 0 2006.257.01:33:12.51#ibcon#wrote, iclass 38, count 0 2006.257.01:33:12.51#ibcon#about to read 3, iclass 38, count 0 2006.257.01:33:12.55#ibcon#read 3, iclass 38, count 0 2006.257.01:33:12.55#ibcon#about to read 4, iclass 38, count 0 2006.257.01:33:12.55#ibcon#read 4, iclass 38, count 0 2006.257.01:33:12.55#ibcon#about to read 5, iclass 38, count 0 2006.257.01:33:12.55#ibcon#read 5, iclass 38, count 0 2006.257.01:33:12.55#ibcon#about to read 6, iclass 38, count 0 2006.257.01:33:12.55#ibcon#read 6, iclass 38, count 0 2006.257.01:33:12.55#ibcon#end of sib2, iclass 38, count 0 2006.257.01:33:12.55#ibcon#*after write, iclass 38, count 0 2006.257.01:33:12.55#ibcon#*before return 0, iclass 38, count 0 2006.257.01:33:12.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:12.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:12.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.01:33:12.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.01:33:12.55$vck44/va=6,4 2006.257.01:33:12.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.01:33:12.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.01:33:12.55#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:12.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:12.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:12.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:12.61#ibcon#enter wrdev, iclass 40, count 2 2006.257.01:33:12.61#ibcon#first serial, iclass 40, count 2 2006.257.01:33:12.61#ibcon#enter sib2, iclass 40, count 2 2006.257.01:33:12.61#ibcon#flushed, iclass 40, count 2 2006.257.01:33:12.61#ibcon#about to write, iclass 40, count 2 2006.257.01:33:12.61#ibcon#wrote, iclass 40, count 2 2006.257.01:33:12.61#ibcon#about to read 3, iclass 40, count 2 2006.257.01:33:12.63#ibcon#read 3, iclass 40, count 2 2006.257.01:33:12.63#ibcon#about to read 4, iclass 40, count 2 2006.257.01:33:12.63#ibcon#read 4, iclass 40, count 2 2006.257.01:33:12.63#ibcon#about to read 5, iclass 40, count 2 2006.257.01:33:12.63#ibcon#read 5, iclass 40, count 2 2006.257.01:33:12.63#ibcon#about to read 6, iclass 40, count 2 2006.257.01:33:12.63#ibcon#read 6, iclass 40, count 2 2006.257.01:33:12.63#ibcon#end of sib2, iclass 40, count 2 2006.257.01:33:12.63#ibcon#*mode == 0, iclass 40, count 2 2006.257.01:33:12.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.01:33:12.63#ibcon#[25=AT06-04\r\n] 2006.257.01:33:12.63#ibcon#*before write, iclass 40, count 2 2006.257.01:33:12.63#ibcon#enter sib2, iclass 40, count 2 2006.257.01:33:12.63#ibcon#flushed, iclass 40, count 2 2006.257.01:33:12.63#ibcon#about to write, iclass 40, count 2 2006.257.01:33:12.63#ibcon#wrote, iclass 40, count 2 2006.257.01:33:12.63#ibcon#about to read 3, iclass 40, count 2 2006.257.01:33:12.66#ibcon#read 3, iclass 40, count 2 2006.257.01:33:12.66#ibcon#about to read 4, iclass 40, count 2 2006.257.01:33:12.66#ibcon#read 4, iclass 40, count 2 2006.257.01:33:12.66#ibcon#about to read 5, iclass 40, count 2 2006.257.01:33:12.66#ibcon#read 5, iclass 40, count 2 2006.257.01:33:12.66#ibcon#about to read 6, iclass 40, count 2 2006.257.01:33:12.66#ibcon#read 6, iclass 40, count 2 2006.257.01:33:12.66#ibcon#end of sib2, iclass 40, count 2 2006.257.01:33:12.66#ibcon#*after write, iclass 40, count 2 2006.257.01:33:12.66#ibcon#*before return 0, iclass 40, count 2 2006.257.01:33:12.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:12.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:12.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.01:33:12.66#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:12.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:12.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:12.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:12.78#ibcon#enter wrdev, iclass 40, count 0 2006.257.01:33:12.78#ibcon#first serial, iclass 40, count 0 2006.257.01:33:12.78#ibcon#enter sib2, iclass 40, count 0 2006.257.01:33:12.78#ibcon#flushed, iclass 40, count 0 2006.257.01:33:12.78#ibcon#about to write, iclass 40, count 0 2006.257.01:33:12.78#ibcon#wrote, iclass 40, count 0 2006.257.01:33:12.78#ibcon#about to read 3, iclass 40, count 0 2006.257.01:33:12.80#ibcon#read 3, iclass 40, count 0 2006.257.01:33:12.80#ibcon#about to read 4, iclass 40, count 0 2006.257.01:33:12.80#ibcon#read 4, iclass 40, count 0 2006.257.01:33:12.80#ibcon#about to read 5, iclass 40, count 0 2006.257.01:33:12.80#ibcon#read 5, iclass 40, count 0 2006.257.01:33:12.80#ibcon#about to read 6, iclass 40, count 0 2006.257.01:33:12.80#ibcon#read 6, iclass 40, count 0 2006.257.01:33:12.80#ibcon#end of sib2, iclass 40, count 0 2006.257.01:33:12.80#ibcon#*mode == 0, iclass 40, count 0 2006.257.01:33:12.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.01:33:12.80#ibcon#[25=USB\r\n] 2006.257.01:33:12.80#ibcon#*before write, iclass 40, count 0 2006.257.01:33:12.80#ibcon#enter sib2, iclass 40, count 0 2006.257.01:33:12.80#ibcon#flushed, iclass 40, count 0 2006.257.01:33:12.80#ibcon#about to write, iclass 40, count 0 2006.257.01:33:12.80#ibcon#wrote, iclass 40, count 0 2006.257.01:33:12.80#ibcon#about to read 3, iclass 40, count 0 2006.257.01:33:12.83#ibcon#read 3, iclass 40, count 0 2006.257.01:33:12.83#ibcon#about to read 4, iclass 40, count 0 2006.257.01:33:12.83#ibcon#read 4, iclass 40, count 0 2006.257.01:33:12.83#ibcon#about to read 5, iclass 40, count 0 2006.257.01:33:12.83#ibcon#read 5, iclass 40, count 0 2006.257.01:33:12.83#ibcon#about to read 6, iclass 40, count 0 2006.257.01:33:12.83#ibcon#read 6, iclass 40, count 0 2006.257.01:33:12.83#ibcon#end of sib2, iclass 40, count 0 2006.257.01:33:12.83#ibcon#*after write, iclass 40, count 0 2006.257.01:33:12.83#ibcon#*before return 0, iclass 40, count 0 2006.257.01:33:12.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:12.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:12.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.01:33:12.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.01:33:12.83$vck44/valo=7,864.99 2006.257.01:33:12.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.01:33:12.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.01:33:12.83#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:12.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:12.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:12.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:12.83#ibcon#enter wrdev, iclass 4, count 0 2006.257.01:33:12.83#ibcon#first serial, iclass 4, count 0 2006.257.01:33:12.83#ibcon#enter sib2, iclass 4, count 0 2006.257.01:33:12.83#ibcon#flushed, iclass 4, count 0 2006.257.01:33:12.83#ibcon#about to write, iclass 4, count 0 2006.257.01:33:12.83#ibcon#wrote, iclass 4, count 0 2006.257.01:33:12.83#ibcon#about to read 3, iclass 4, count 0 2006.257.01:33:12.85#ibcon#read 3, iclass 4, count 0 2006.257.01:33:12.85#ibcon#about to read 4, iclass 4, count 0 2006.257.01:33:12.85#ibcon#read 4, iclass 4, count 0 2006.257.01:33:12.85#ibcon#about to read 5, iclass 4, count 0 2006.257.01:33:12.85#ibcon#read 5, iclass 4, count 0 2006.257.01:33:12.85#ibcon#about to read 6, iclass 4, count 0 2006.257.01:33:12.85#ibcon#read 6, iclass 4, count 0 2006.257.01:33:12.85#ibcon#end of sib2, iclass 4, count 0 2006.257.01:33:12.85#ibcon#*mode == 0, iclass 4, count 0 2006.257.01:33:12.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.01:33:12.85#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.01:33:12.85#ibcon#*before write, iclass 4, count 0 2006.257.01:33:12.85#ibcon#enter sib2, iclass 4, count 0 2006.257.01:33:12.85#ibcon#flushed, iclass 4, count 0 2006.257.01:33:12.85#ibcon#about to write, iclass 4, count 0 2006.257.01:33:12.85#ibcon#wrote, iclass 4, count 0 2006.257.01:33:12.85#ibcon#about to read 3, iclass 4, count 0 2006.257.01:33:12.89#ibcon#read 3, iclass 4, count 0 2006.257.01:33:12.89#ibcon#about to read 4, iclass 4, count 0 2006.257.01:33:12.89#ibcon#read 4, iclass 4, count 0 2006.257.01:33:12.89#ibcon#about to read 5, iclass 4, count 0 2006.257.01:33:12.89#ibcon#read 5, iclass 4, count 0 2006.257.01:33:12.89#ibcon#about to read 6, iclass 4, count 0 2006.257.01:33:12.89#ibcon#read 6, iclass 4, count 0 2006.257.01:33:12.89#ibcon#end of sib2, iclass 4, count 0 2006.257.01:33:12.89#ibcon#*after write, iclass 4, count 0 2006.257.01:33:12.89#ibcon#*before return 0, iclass 4, count 0 2006.257.01:33:12.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:12.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:12.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.01:33:12.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.01:33:12.89$vck44/va=7,4 2006.257.01:33:12.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.01:33:12.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.01:33:12.89#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:12.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:12.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:12.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:12.95#ibcon#enter wrdev, iclass 6, count 2 2006.257.01:33:12.95#ibcon#first serial, iclass 6, count 2 2006.257.01:33:12.95#ibcon#enter sib2, iclass 6, count 2 2006.257.01:33:12.95#ibcon#flushed, iclass 6, count 2 2006.257.01:33:12.95#ibcon#about to write, iclass 6, count 2 2006.257.01:33:12.95#ibcon#wrote, iclass 6, count 2 2006.257.01:33:12.95#ibcon#about to read 3, iclass 6, count 2 2006.257.01:33:12.97#ibcon#read 3, iclass 6, count 2 2006.257.01:33:12.97#ibcon#about to read 4, iclass 6, count 2 2006.257.01:33:12.97#ibcon#read 4, iclass 6, count 2 2006.257.01:33:12.97#ibcon#about to read 5, iclass 6, count 2 2006.257.01:33:12.97#ibcon#read 5, iclass 6, count 2 2006.257.01:33:12.97#ibcon#about to read 6, iclass 6, count 2 2006.257.01:33:12.97#ibcon#read 6, iclass 6, count 2 2006.257.01:33:12.97#ibcon#end of sib2, iclass 6, count 2 2006.257.01:33:12.97#ibcon#*mode == 0, iclass 6, count 2 2006.257.01:33:12.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.01:33:12.97#ibcon#[25=AT07-04\r\n] 2006.257.01:33:12.97#ibcon#*before write, iclass 6, count 2 2006.257.01:33:12.97#ibcon#enter sib2, iclass 6, count 2 2006.257.01:33:12.97#ibcon#flushed, iclass 6, count 2 2006.257.01:33:12.97#ibcon#about to write, iclass 6, count 2 2006.257.01:33:12.97#ibcon#wrote, iclass 6, count 2 2006.257.01:33:12.97#ibcon#about to read 3, iclass 6, count 2 2006.257.01:33:13.00#ibcon#read 3, iclass 6, count 2 2006.257.01:33:13.00#ibcon#about to read 4, iclass 6, count 2 2006.257.01:33:13.00#ibcon#read 4, iclass 6, count 2 2006.257.01:33:13.00#ibcon#about to read 5, iclass 6, count 2 2006.257.01:33:13.00#ibcon#read 5, iclass 6, count 2 2006.257.01:33:13.00#ibcon#about to read 6, iclass 6, count 2 2006.257.01:33:13.00#ibcon#read 6, iclass 6, count 2 2006.257.01:33:13.00#ibcon#end of sib2, iclass 6, count 2 2006.257.01:33:13.00#ibcon#*after write, iclass 6, count 2 2006.257.01:33:13.00#ibcon#*before return 0, iclass 6, count 2 2006.257.01:33:13.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:13.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:13.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.01:33:13.00#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:13.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:13.04#abcon#<5=/15 1.5 4.1 17.601001013.0\r\n> 2006.257.01:33:13.06#abcon#{5=INTERFACE CLEAR} 2006.257.01:33:13.12#abcon#[5=S1D000X0/0*\r\n] 2006.257.01:33:13.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:13.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:13.12#ibcon#enter wrdev, iclass 6, count 0 2006.257.01:33:13.12#ibcon#first serial, iclass 6, count 0 2006.257.01:33:13.12#ibcon#enter sib2, iclass 6, count 0 2006.257.01:33:13.12#ibcon#flushed, iclass 6, count 0 2006.257.01:33:13.12#ibcon#about to write, iclass 6, count 0 2006.257.01:33:13.12#ibcon#wrote, iclass 6, count 0 2006.257.01:33:13.12#ibcon#about to read 3, iclass 6, count 0 2006.257.01:33:13.14#ibcon#read 3, iclass 6, count 0 2006.257.01:33:13.14#ibcon#about to read 4, iclass 6, count 0 2006.257.01:33:13.14#ibcon#read 4, iclass 6, count 0 2006.257.01:33:13.14#ibcon#about to read 5, iclass 6, count 0 2006.257.01:33:13.14#ibcon#read 5, iclass 6, count 0 2006.257.01:33:13.14#ibcon#about to read 6, iclass 6, count 0 2006.257.01:33:13.14#ibcon#read 6, iclass 6, count 0 2006.257.01:33:13.14#ibcon#end of sib2, iclass 6, count 0 2006.257.01:33:13.14#ibcon#*mode == 0, iclass 6, count 0 2006.257.01:33:13.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.01:33:13.14#ibcon#[25=USB\r\n] 2006.257.01:33:13.14#ibcon#*before write, iclass 6, count 0 2006.257.01:33:13.14#ibcon#enter sib2, iclass 6, count 0 2006.257.01:33:13.14#ibcon#flushed, iclass 6, count 0 2006.257.01:33:13.14#ibcon#about to write, iclass 6, count 0 2006.257.01:33:13.14#ibcon#wrote, iclass 6, count 0 2006.257.01:33:13.14#ibcon#about to read 3, iclass 6, count 0 2006.257.01:33:13.17#ibcon#read 3, iclass 6, count 0 2006.257.01:33:13.17#ibcon#about to read 4, iclass 6, count 0 2006.257.01:33:13.17#ibcon#read 4, iclass 6, count 0 2006.257.01:33:13.17#ibcon#about to read 5, iclass 6, count 0 2006.257.01:33:13.17#ibcon#read 5, iclass 6, count 0 2006.257.01:33:13.17#ibcon#about to read 6, iclass 6, count 0 2006.257.01:33:13.17#ibcon#read 6, iclass 6, count 0 2006.257.01:33:13.17#ibcon#end of sib2, iclass 6, count 0 2006.257.01:33:13.17#ibcon#*after write, iclass 6, count 0 2006.257.01:33:13.17#ibcon#*before return 0, iclass 6, count 0 2006.257.01:33:13.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:13.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:13.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.01:33:13.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.01:33:13.17$vck44/valo=8,884.99 2006.257.01:33:13.17#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.01:33:13.17#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.01:33:13.17#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:13.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:13.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:13.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:13.17#ibcon#enter wrdev, iclass 14, count 0 2006.257.01:33:13.17#ibcon#first serial, iclass 14, count 0 2006.257.01:33:13.17#ibcon#enter sib2, iclass 14, count 0 2006.257.01:33:13.17#ibcon#flushed, iclass 14, count 0 2006.257.01:33:13.17#ibcon#about to write, iclass 14, count 0 2006.257.01:33:13.17#ibcon#wrote, iclass 14, count 0 2006.257.01:33:13.17#ibcon#about to read 3, iclass 14, count 0 2006.257.01:33:13.19#ibcon#read 3, iclass 14, count 0 2006.257.01:33:13.19#ibcon#about to read 4, iclass 14, count 0 2006.257.01:33:13.19#ibcon#read 4, iclass 14, count 0 2006.257.01:33:13.19#ibcon#about to read 5, iclass 14, count 0 2006.257.01:33:13.19#ibcon#read 5, iclass 14, count 0 2006.257.01:33:13.19#ibcon#about to read 6, iclass 14, count 0 2006.257.01:33:13.19#ibcon#read 6, iclass 14, count 0 2006.257.01:33:13.19#ibcon#end of sib2, iclass 14, count 0 2006.257.01:33:13.19#ibcon#*mode == 0, iclass 14, count 0 2006.257.01:33:13.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.01:33:13.19#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.01:33:13.19#ibcon#*before write, iclass 14, count 0 2006.257.01:33:13.19#ibcon#enter sib2, iclass 14, count 0 2006.257.01:33:13.19#ibcon#flushed, iclass 14, count 0 2006.257.01:33:13.19#ibcon#about to write, iclass 14, count 0 2006.257.01:33:13.19#ibcon#wrote, iclass 14, count 0 2006.257.01:33:13.19#ibcon#about to read 3, iclass 14, count 0 2006.257.01:33:13.23#ibcon#read 3, iclass 14, count 0 2006.257.01:33:13.23#ibcon#about to read 4, iclass 14, count 0 2006.257.01:33:13.23#ibcon#read 4, iclass 14, count 0 2006.257.01:33:13.23#ibcon#about to read 5, iclass 14, count 0 2006.257.01:33:13.23#ibcon#read 5, iclass 14, count 0 2006.257.01:33:13.23#ibcon#about to read 6, iclass 14, count 0 2006.257.01:33:13.23#ibcon#read 6, iclass 14, count 0 2006.257.01:33:13.23#ibcon#end of sib2, iclass 14, count 0 2006.257.01:33:13.23#ibcon#*after write, iclass 14, count 0 2006.257.01:33:13.23#ibcon#*before return 0, iclass 14, count 0 2006.257.01:33:13.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:13.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:13.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.01:33:13.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.01:33:13.23$vck44/va=8,4 2006.257.01:33:13.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.01:33:13.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.01:33:13.23#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:13.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.01:33:13.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.01:33:13.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.01:33:13.29#ibcon#enter wrdev, iclass 16, count 2 2006.257.01:33:13.29#ibcon#first serial, iclass 16, count 2 2006.257.01:33:13.29#ibcon#enter sib2, iclass 16, count 2 2006.257.01:33:13.29#ibcon#flushed, iclass 16, count 2 2006.257.01:33:13.29#ibcon#about to write, iclass 16, count 2 2006.257.01:33:13.29#ibcon#wrote, iclass 16, count 2 2006.257.01:33:13.29#ibcon#about to read 3, iclass 16, count 2 2006.257.01:33:13.31#ibcon#read 3, iclass 16, count 2 2006.257.01:33:13.31#ibcon#about to read 4, iclass 16, count 2 2006.257.01:33:13.31#ibcon#read 4, iclass 16, count 2 2006.257.01:33:13.31#ibcon#about to read 5, iclass 16, count 2 2006.257.01:33:13.31#ibcon#read 5, iclass 16, count 2 2006.257.01:33:13.31#ibcon#about to read 6, iclass 16, count 2 2006.257.01:33:13.31#ibcon#read 6, iclass 16, count 2 2006.257.01:33:13.31#ibcon#end of sib2, iclass 16, count 2 2006.257.01:33:13.31#ibcon#*mode == 0, iclass 16, count 2 2006.257.01:33:13.31#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.01:33:13.31#ibcon#[25=AT08-04\r\n] 2006.257.01:33:13.31#ibcon#*before write, iclass 16, count 2 2006.257.01:33:13.31#ibcon#enter sib2, iclass 16, count 2 2006.257.01:33:13.31#ibcon#flushed, iclass 16, count 2 2006.257.01:33:13.31#ibcon#about to write, iclass 16, count 2 2006.257.01:33:13.31#ibcon#wrote, iclass 16, count 2 2006.257.01:33:13.31#ibcon#about to read 3, iclass 16, count 2 2006.257.01:33:13.34#ibcon#read 3, iclass 16, count 2 2006.257.01:33:13.34#ibcon#about to read 4, iclass 16, count 2 2006.257.01:33:13.34#ibcon#read 4, iclass 16, count 2 2006.257.01:33:13.34#ibcon#about to read 5, iclass 16, count 2 2006.257.01:33:13.34#ibcon#read 5, iclass 16, count 2 2006.257.01:33:13.34#ibcon#about to read 6, iclass 16, count 2 2006.257.01:33:13.34#ibcon#read 6, iclass 16, count 2 2006.257.01:33:13.34#ibcon#end of sib2, iclass 16, count 2 2006.257.01:33:13.34#ibcon#*after write, iclass 16, count 2 2006.257.01:33:13.34#ibcon#*before return 0, iclass 16, count 2 2006.257.01:33:13.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.01:33:13.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.01:33:13.34#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.01:33:13.34#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:13.34#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.01:33:13.46#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.01:33:13.46#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.01:33:13.46#ibcon#enter wrdev, iclass 16, count 0 2006.257.01:33:13.46#ibcon#first serial, iclass 16, count 0 2006.257.01:33:13.46#ibcon#enter sib2, iclass 16, count 0 2006.257.01:33:13.46#ibcon#flushed, iclass 16, count 0 2006.257.01:33:13.46#ibcon#about to write, iclass 16, count 0 2006.257.01:33:13.46#ibcon#wrote, iclass 16, count 0 2006.257.01:33:13.46#ibcon#about to read 3, iclass 16, count 0 2006.257.01:33:13.48#ibcon#read 3, iclass 16, count 0 2006.257.01:33:13.48#ibcon#about to read 4, iclass 16, count 0 2006.257.01:33:13.48#ibcon#read 4, iclass 16, count 0 2006.257.01:33:13.48#ibcon#about to read 5, iclass 16, count 0 2006.257.01:33:13.48#ibcon#read 5, iclass 16, count 0 2006.257.01:33:13.48#ibcon#about to read 6, iclass 16, count 0 2006.257.01:33:13.48#ibcon#read 6, iclass 16, count 0 2006.257.01:33:13.48#ibcon#end of sib2, iclass 16, count 0 2006.257.01:33:13.48#ibcon#*mode == 0, iclass 16, count 0 2006.257.01:33:13.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.01:33:13.48#ibcon#[25=USB\r\n] 2006.257.01:33:13.48#ibcon#*before write, iclass 16, count 0 2006.257.01:33:13.48#ibcon#enter sib2, iclass 16, count 0 2006.257.01:33:13.48#ibcon#flushed, iclass 16, count 0 2006.257.01:33:13.48#ibcon#about to write, iclass 16, count 0 2006.257.01:33:13.48#ibcon#wrote, iclass 16, count 0 2006.257.01:33:13.48#ibcon#about to read 3, iclass 16, count 0 2006.257.01:33:13.51#ibcon#read 3, iclass 16, count 0 2006.257.01:33:13.51#ibcon#about to read 4, iclass 16, count 0 2006.257.01:33:13.51#ibcon#read 4, iclass 16, count 0 2006.257.01:33:13.51#ibcon#about to read 5, iclass 16, count 0 2006.257.01:33:13.51#ibcon#read 5, iclass 16, count 0 2006.257.01:33:13.51#ibcon#about to read 6, iclass 16, count 0 2006.257.01:33:13.51#ibcon#read 6, iclass 16, count 0 2006.257.01:33:13.51#ibcon#end of sib2, iclass 16, count 0 2006.257.01:33:13.51#ibcon#*after write, iclass 16, count 0 2006.257.01:33:13.51#ibcon#*before return 0, iclass 16, count 0 2006.257.01:33:13.51#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.01:33:13.51#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.01:33:13.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.01:33:13.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.01:33:13.51$vck44/vblo=1,629.99 2006.257.01:33:13.51#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.01:33:13.51#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.01:33:13.51#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:13.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:13.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:13.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:13.51#ibcon#enter wrdev, iclass 18, count 0 2006.257.01:33:13.51#ibcon#first serial, iclass 18, count 0 2006.257.01:33:13.51#ibcon#enter sib2, iclass 18, count 0 2006.257.01:33:13.51#ibcon#flushed, iclass 18, count 0 2006.257.01:33:13.51#ibcon#about to write, iclass 18, count 0 2006.257.01:33:13.51#ibcon#wrote, iclass 18, count 0 2006.257.01:33:13.51#ibcon#about to read 3, iclass 18, count 0 2006.257.01:33:13.53#ibcon#read 3, iclass 18, count 0 2006.257.01:33:13.53#ibcon#about to read 4, iclass 18, count 0 2006.257.01:33:13.53#ibcon#read 4, iclass 18, count 0 2006.257.01:33:13.53#ibcon#about to read 5, iclass 18, count 0 2006.257.01:33:13.53#ibcon#read 5, iclass 18, count 0 2006.257.01:33:13.53#ibcon#about to read 6, iclass 18, count 0 2006.257.01:33:13.53#ibcon#read 6, iclass 18, count 0 2006.257.01:33:13.53#ibcon#end of sib2, iclass 18, count 0 2006.257.01:33:13.53#ibcon#*mode == 0, iclass 18, count 0 2006.257.01:33:13.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.01:33:13.53#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.01:33:13.53#ibcon#*before write, iclass 18, count 0 2006.257.01:33:13.53#ibcon#enter sib2, iclass 18, count 0 2006.257.01:33:13.53#ibcon#flushed, iclass 18, count 0 2006.257.01:33:13.53#ibcon#about to write, iclass 18, count 0 2006.257.01:33:13.53#ibcon#wrote, iclass 18, count 0 2006.257.01:33:13.53#ibcon#about to read 3, iclass 18, count 0 2006.257.01:33:13.57#ibcon#read 3, iclass 18, count 0 2006.257.01:33:13.57#ibcon#about to read 4, iclass 18, count 0 2006.257.01:33:13.57#ibcon#read 4, iclass 18, count 0 2006.257.01:33:13.57#ibcon#about to read 5, iclass 18, count 0 2006.257.01:33:13.57#ibcon#read 5, iclass 18, count 0 2006.257.01:33:13.57#ibcon#about to read 6, iclass 18, count 0 2006.257.01:33:13.57#ibcon#read 6, iclass 18, count 0 2006.257.01:33:13.57#ibcon#end of sib2, iclass 18, count 0 2006.257.01:33:13.57#ibcon#*after write, iclass 18, count 0 2006.257.01:33:13.57#ibcon#*before return 0, iclass 18, count 0 2006.257.01:33:13.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:13.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.01:33:13.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.01:33:13.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.01:33:13.57$vck44/vb=1,4 2006.257.01:33:13.57#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.01:33:13.57#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.01:33:13.57#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:13.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:13.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:13.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:13.57#ibcon#enter wrdev, iclass 20, count 2 2006.257.01:33:13.57#ibcon#first serial, iclass 20, count 2 2006.257.01:33:13.57#ibcon#enter sib2, iclass 20, count 2 2006.257.01:33:13.57#ibcon#flushed, iclass 20, count 2 2006.257.01:33:13.57#ibcon#about to write, iclass 20, count 2 2006.257.01:33:13.57#ibcon#wrote, iclass 20, count 2 2006.257.01:33:13.57#ibcon#about to read 3, iclass 20, count 2 2006.257.01:33:13.59#ibcon#read 3, iclass 20, count 2 2006.257.01:33:13.59#ibcon#about to read 4, iclass 20, count 2 2006.257.01:33:13.59#ibcon#read 4, iclass 20, count 2 2006.257.01:33:13.59#ibcon#about to read 5, iclass 20, count 2 2006.257.01:33:13.59#ibcon#read 5, iclass 20, count 2 2006.257.01:33:13.59#ibcon#about to read 6, iclass 20, count 2 2006.257.01:33:13.59#ibcon#read 6, iclass 20, count 2 2006.257.01:33:13.59#ibcon#end of sib2, iclass 20, count 2 2006.257.01:33:13.59#ibcon#*mode == 0, iclass 20, count 2 2006.257.01:33:13.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.01:33:13.59#ibcon#[27=AT01-04\r\n] 2006.257.01:33:13.59#ibcon#*before write, iclass 20, count 2 2006.257.01:33:13.59#ibcon#enter sib2, iclass 20, count 2 2006.257.01:33:13.59#ibcon#flushed, iclass 20, count 2 2006.257.01:33:13.59#ibcon#about to write, iclass 20, count 2 2006.257.01:33:13.59#ibcon#wrote, iclass 20, count 2 2006.257.01:33:13.59#ibcon#about to read 3, iclass 20, count 2 2006.257.01:33:13.62#ibcon#read 3, iclass 20, count 2 2006.257.01:33:13.62#ibcon#about to read 4, iclass 20, count 2 2006.257.01:33:13.62#ibcon#read 4, iclass 20, count 2 2006.257.01:33:13.62#ibcon#about to read 5, iclass 20, count 2 2006.257.01:33:13.62#ibcon#read 5, iclass 20, count 2 2006.257.01:33:13.62#ibcon#about to read 6, iclass 20, count 2 2006.257.01:33:13.62#ibcon#read 6, iclass 20, count 2 2006.257.01:33:13.62#ibcon#end of sib2, iclass 20, count 2 2006.257.01:33:13.62#ibcon#*after write, iclass 20, count 2 2006.257.01:33:13.62#ibcon#*before return 0, iclass 20, count 2 2006.257.01:33:13.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:13.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.01:33:13.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.01:33:13.62#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:13.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:13.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:13.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:13.74#ibcon#enter wrdev, iclass 20, count 0 2006.257.01:33:13.74#ibcon#first serial, iclass 20, count 0 2006.257.01:33:13.74#ibcon#enter sib2, iclass 20, count 0 2006.257.01:33:13.74#ibcon#flushed, iclass 20, count 0 2006.257.01:33:13.74#ibcon#about to write, iclass 20, count 0 2006.257.01:33:13.74#ibcon#wrote, iclass 20, count 0 2006.257.01:33:13.74#ibcon#about to read 3, iclass 20, count 0 2006.257.01:33:13.76#ibcon#read 3, iclass 20, count 0 2006.257.01:33:13.76#ibcon#about to read 4, iclass 20, count 0 2006.257.01:33:13.76#ibcon#read 4, iclass 20, count 0 2006.257.01:33:13.76#ibcon#about to read 5, iclass 20, count 0 2006.257.01:33:13.76#ibcon#read 5, iclass 20, count 0 2006.257.01:33:13.76#ibcon#about to read 6, iclass 20, count 0 2006.257.01:33:13.76#ibcon#read 6, iclass 20, count 0 2006.257.01:33:13.76#ibcon#end of sib2, iclass 20, count 0 2006.257.01:33:13.76#ibcon#*mode == 0, iclass 20, count 0 2006.257.01:33:13.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.01:33:13.76#ibcon#[27=USB\r\n] 2006.257.01:33:13.76#ibcon#*before write, iclass 20, count 0 2006.257.01:33:13.76#ibcon#enter sib2, iclass 20, count 0 2006.257.01:33:13.76#ibcon#flushed, iclass 20, count 0 2006.257.01:33:13.76#ibcon#about to write, iclass 20, count 0 2006.257.01:33:13.76#ibcon#wrote, iclass 20, count 0 2006.257.01:33:13.76#ibcon#about to read 3, iclass 20, count 0 2006.257.01:33:13.79#ibcon#read 3, iclass 20, count 0 2006.257.01:33:13.79#ibcon#about to read 4, iclass 20, count 0 2006.257.01:33:13.79#ibcon#read 4, iclass 20, count 0 2006.257.01:33:13.79#ibcon#about to read 5, iclass 20, count 0 2006.257.01:33:13.79#ibcon#read 5, iclass 20, count 0 2006.257.01:33:13.79#ibcon#about to read 6, iclass 20, count 0 2006.257.01:33:13.79#ibcon#read 6, iclass 20, count 0 2006.257.01:33:13.79#ibcon#end of sib2, iclass 20, count 0 2006.257.01:33:13.79#ibcon#*after write, iclass 20, count 0 2006.257.01:33:13.79#ibcon#*before return 0, iclass 20, count 0 2006.257.01:33:13.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:13.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.01:33:13.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.01:33:13.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.01:33:13.79$vck44/vblo=2,634.99 2006.257.01:33:13.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.01:33:13.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.01:33:13.79#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:13.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:13.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:13.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:13.79#ibcon#enter wrdev, iclass 22, count 0 2006.257.01:33:13.79#ibcon#first serial, iclass 22, count 0 2006.257.01:33:13.79#ibcon#enter sib2, iclass 22, count 0 2006.257.01:33:13.79#ibcon#flushed, iclass 22, count 0 2006.257.01:33:13.79#ibcon#about to write, iclass 22, count 0 2006.257.01:33:13.79#ibcon#wrote, iclass 22, count 0 2006.257.01:33:13.79#ibcon#about to read 3, iclass 22, count 0 2006.257.01:33:13.81#ibcon#read 3, iclass 22, count 0 2006.257.01:33:13.81#ibcon#about to read 4, iclass 22, count 0 2006.257.01:33:13.81#ibcon#read 4, iclass 22, count 0 2006.257.01:33:13.81#ibcon#about to read 5, iclass 22, count 0 2006.257.01:33:13.81#ibcon#read 5, iclass 22, count 0 2006.257.01:33:13.81#ibcon#about to read 6, iclass 22, count 0 2006.257.01:33:13.81#ibcon#read 6, iclass 22, count 0 2006.257.01:33:13.81#ibcon#end of sib2, iclass 22, count 0 2006.257.01:33:13.81#ibcon#*mode == 0, iclass 22, count 0 2006.257.01:33:13.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.01:33:13.81#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.01:33:13.81#ibcon#*before write, iclass 22, count 0 2006.257.01:33:13.81#ibcon#enter sib2, iclass 22, count 0 2006.257.01:33:13.81#ibcon#flushed, iclass 22, count 0 2006.257.01:33:13.81#ibcon#about to write, iclass 22, count 0 2006.257.01:33:13.81#ibcon#wrote, iclass 22, count 0 2006.257.01:33:13.81#ibcon#about to read 3, iclass 22, count 0 2006.257.01:33:13.85#ibcon#read 3, iclass 22, count 0 2006.257.01:33:13.85#ibcon#about to read 4, iclass 22, count 0 2006.257.01:33:13.85#ibcon#read 4, iclass 22, count 0 2006.257.01:33:13.85#ibcon#about to read 5, iclass 22, count 0 2006.257.01:33:13.85#ibcon#read 5, iclass 22, count 0 2006.257.01:33:13.85#ibcon#about to read 6, iclass 22, count 0 2006.257.01:33:13.85#ibcon#read 6, iclass 22, count 0 2006.257.01:33:13.85#ibcon#end of sib2, iclass 22, count 0 2006.257.01:33:13.85#ibcon#*after write, iclass 22, count 0 2006.257.01:33:13.85#ibcon#*before return 0, iclass 22, count 0 2006.257.01:33:13.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:13.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.01:33:13.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.01:33:13.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.01:33:13.85$vck44/vb=2,5 2006.257.01:33:13.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.01:33:13.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.01:33:13.85#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:13.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:13.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:13.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:13.91#ibcon#enter wrdev, iclass 24, count 2 2006.257.01:33:13.91#ibcon#first serial, iclass 24, count 2 2006.257.01:33:13.91#ibcon#enter sib2, iclass 24, count 2 2006.257.01:33:13.91#ibcon#flushed, iclass 24, count 2 2006.257.01:33:13.91#ibcon#about to write, iclass 24, count 2 2006.257.01:33:13.91#ibcon#wrote, iclass 24, count 2 2006.257.01:33:13.91#ibcon#about to read 3, iclass 24, count 2 2006.257.01:33:13.93#ibcon#read 3, iclass 24, count 2 2006.257.01:33:13.93#ibcon#about to read 4, iclass 24, count 2 2006.257.01:33:13.93#ibcon#read 4, iclass 24, count 2 2006.257.01:33:13.93#ibcon#about to read 5, iclass 24, count 2 2006.257.01:33:13.93#ibcon#read 5, iclass 24, count 2 2006.257.01:33:13.93#ibcon#about to read 6, iclass 24, count 2 2006.257.01:33:13.93#ibcon#read 6, iclass 24, count 2 2006.257.01:33:13.93#ibcon#end of sib2, iclass 24, count 2 2006.257.01:33:13.93#ibcon#*mode == 0, iclass 24, count 2 2006.257.01:33:13.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.01:33:13.93#ibcon#[27=AT02-05\r\n] 2006.257.01:33:13.93#ibcon#*before write, iclass 24, count 2 2006.257.01:33:13.93#ibcon#enter sib2, iclass 24, count 2 2006.257.01:33:13.93#ibcon#flushed, iclass 24, count 2 2006.257.01:33:13.93#ibcon#about to write, iclass 24, count 2 2006.257.01:33:13.93#ibcon#wrote, iclass 24, count 2 2006.257.01:33:13.93#ibcon#about to read 3, iclass 24, count 2 2006.257.01:33:13.96#ibcon#read 3, iclass 24, count 2 2006.257.01:33:13.96#ibcon#about to read 4, iclass 24, count 2 2006.257.01:33:13.96#ibcon#read 4, iclass 24, count 2 2006.257.01:33:13.96#ibcon#about to read 5, iclass 24, count 2 2006.257.01:33:13.96#ibcon#read 5, iclass 24, count 2 2006.257.01:33:13.96#ibcon#about to read 6, iclass 24, count 2 2006.257.01:33:13.96#ibcon#read 6, iclass 24, count 2 2006.257.01:33:13.96#ibcon#end of sib2, iclass 24, count 2 2006.257.01:33:13.96#ibcon#*after write, iclass 24, count 2 2006.257.01:33:13.96#ibcon#*before return 0, iclass 24, count 2 2006.257.01:33:13.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:13.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.01:33:13.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.01:33:13.96#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:13.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:14.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:14.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:14.08#ibcon#enter wrdev, iclass 24, count 0 2006.257.01:33:14.08#ibcon#first serial, iclass 24, count 0 2006.257.01:33:14.08#ibcon#enter sib2, iclass 24, count 0 2006.257.01:33:14.08#ibcon#flushed, iclass 24, count 0 2006.257.01:33:14.08#ibcon#about to write, iclass 24, count 0 2006.257.01:33:14.08#ibcon#wrote, iclass 24, count 0 2006.257.01:33:14.08#ibcon#about to read 3, iclass 24, count 0 2006.257.01:33:14.10#ibcon#read 3, iclass 24, count 0 2006.257.01:33:14.10#ibcon#about to read 4, iclass 24, count 0 2006.257.01:33:14.10#ibcon#read 4, iclass 24, count 0 2006.257.01:33:14.10#ibcon#about to read 5, iclass 24, count 0 2006.257.01:33:14.10#ibcon#read 5, iclass 24, count 0 2006.257.01:33:14.10#ibcon#about to read 6, iclass 24, count 0 2006.257.01:33:14.10#ibcon#read 6, iclass 24, count 0 2006.257.01:33:14.10#ibcon#end of sib2, iclass 24, count 0 2006.257.01:33:14.10#ibcon#*mode == 0, iclass 24, count 0 2006.257.01:33:14.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.01:33:14.10#ibcon#[27=USB\r\n] 2006.257.01:33:14.10#ibcon#*before write, iclass 24, count 0 2006.257.01:33:14.10#ibcon#enter sib2, iclass 24, count 0 2006.257.01:33:14.10#ibcon#flushed, iclass 24, count 0 2006.257.01:33:14.10#ibcon#about to write, iclass 24, count 0 2006.257.01:33:14.10#ibcon#wrote, iclass 24, count 0 2006.257.01:33:14.10#ibcon#about to read 3, iclass 24, count 0 2006.257.01:33:14.13#ibcon#read 3, iclass 24, count 0 2006.257.01:33:14.13#ibcon#about to read 4, iclass 24, count 0 2006.257.01:33:14.13#ibcon#read 4, iclass 24, count 0 2006.257.01:33:14.13#ibcon#about to read 5, iclass 24, count 0 2006.257.01:33:14.13#ibcon#read 5, iclass 24, count 0 2006.257.01:33:14.13#ibcon#about to read 6, iclass 24, count 0 2006.257.01:33:14.13#ibcon#read 6, iclass 24, count 0 2006.257.01:33:14.13#ibcon#end of sib2, iclass 24, count 0 2006.257.01:33:14.13#ibcon#*after write, iclass 24, count 0 2006.257.01:33:14.13#ibcon#*before return 0, iclass 24, count 0 2006.257.01:33:14.13#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:14.13#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.01:33:14.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.01:33:14.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.01:33:14.13$vck44/vblo=3,649.99 2006.257.01:33:14.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.01:33:14.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.01:33:14.13#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:14.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:14.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:14.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:14.13#ibcon#enter wrdev, iclass 26, count 0 2006.257.01:33:14.13#ibcon#first serial, iclass 26, count 0 2006.257.01:33:14.13#ibcon#enter sib2, iclass 26, count 0 2006.257.01:33:14.13#ibcon#flushed, iclass 26, count 0 2006.257.01:33:14.13#ibcon#about to write, iclass 26, count 0 2006.257.01:33:14.13#ibcon#wrote, iclass 26, count 0 2006.257.01:33:14.13#ibcon#about to read 3, iclass 26, count 0 2006.257.01:33:14.15#ibcon#read 3, iclass 26, count 0 2006.257.01:33:14.15#ibcon#about to read 4, iclass 26, count 0 2006.257.01:33:14.15#ibcon#read 4, iclass 26, count 0 2006.257.01:33:14.15#ibcon#about to read 5, iclass 26, count 0 2006.257.01:33:14.15#ibcon#read 5, iclass 26, count 0 2006.257.01:33:14.15#ibcon#about to read 6, iclass 26, count 0 2006.257.01:33:14.15#ibcon#read 6, iclass 26, count 0 2006.257.01:33:14.15#ibcon#end of sib2, iclass 26, count 0 2006.257.01:33:14.15#ibcon#*mode == 0, iclass 26, count 0 2006.257.01:33:14.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.01:33:14.15#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.01:33:14.15#ibcon#*before write, iclass 26, count 0 2006.257.01:33:14.15#ibcon#enter sib2, iclass 26, count 0 2006.257.01:33:14.15#ibcon#flushed, iclass 26, count 0 2006.257.01:33:14.15#ibcon#about to write, iclass 26, count 0 2006.257.01:33:14.15#ibcon#wrote, iclass 26, count 0 2006.257.01:33:14.15#ibcon#about to read 3, iclass 26, count 0 2006.257.01:33:14.19#ibcon#read 3, iclass 26, count 0 2006.257.01:33:14.19#ibcon#about to read 4, iclass 26, count 0 2006.257.01:33:14.19#ibcon#read 4, iclass 26, count 0 2006.257.01:33:14.19#ibcon#about to read 5, iclass 26, count 0 2006.257.01:33:14.19#ibcon#read 5, iclass 26, count 0 2006.257.01:33:14.19#ibcon#about to read 6, iclass 26, count 0 2006.257.01:33:14.19#ibcon#read 6, iclass 26, count 0 2006.257.01:33:14.19#ibcon#end of sib2, iclass 26, count 0 2006.257.01:33:14.19#ibcon#*after write, iclass 26, count 0 2006.257.01:33:14.19#ibcon#*before return 0, iclass 26, count 0 2006.257.01:33:14.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:14.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.01:33:14.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.01:33:14.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.01:33:14.19$vck44/vb=3,4 2006.257.01:33:14.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.01:33:14.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.01:33:14.19#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:14.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:14.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:14.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:14.25#ibcon#enter wrdev, iclass 28, count 2 2006.257.01:33:14.25#ibcon#first serial, iclass 28, count 2 2006.257.01:33:14.25#ibcon#enter sib2, iclass 28, count 2 2006.257.01:33:14.25#ibcon#flushed, iclass 28, count 2 2006.257.01:33:14.25#ibcon#about to write, iclass 28, count 2 2006.257.01:33:14.25#ibcon#wrote, iclass 28, count 2 2006.257.01:33:14.25#ibcon#about to read 3, iclass 28, count 2 2006.257.01:33:14.27#ibcon#read 3, iclass 28, count 2 2006.257.01:33:14.27#ibcon#about to read 4, iclass 28, count 2 2006.257.01:33:14.27#ibcon#read 4, iclass 28, count 2 2006.257.01:33:14.27#ibcon#about to read 5, iclass 28, count 2 2006.257.01:33:14.27#ibcon#read 5, iclass 28, count 2 2006.257.01:33:14.27#ibcon#about to read 6, iclass 28, count 2 2006.257.01:33:14.27#ibcon#read 6, iclass 28, count 2 2006.257.01:33:14.27#ibcon#end of sib2, iclass 28, count 2 2006.257.01:33:14.27#ibcon#*mode == 0, iclass 28, count 2 2006.257.01:33:14.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.01:33:14.27#ibcon#[27=AT03-04\r\n] 2006.257.01:33:14.27#ibcon#*before write, iclass 28, count 2 2006.257.01:33:14.27#ibcon#enter sib2, iclass 28, count 2 2006.257.01:33:14.27#ibcon#flushed, iclass 28, count 2 2006.257.01:33:14.27#ibcon#about to write, iclass 28, count 2 2006.257.01:33:14.27#ibcon#wrote, iclass 28, count 2 2006.257.01:33:14.27#ibcon#about to read 3, iclass 28, count 2 2006.257.01:33:14.30#ibcon#read 3, iclass 28, count 2 2006.257.01:33:14.30#ibcon#about to read 4, iclass 28, count 2 2006.257.01:33:14.30#ibcon#read 4, iclass 28, count 2 2006.257.01:33:14.30#ibcon#about to read 5, iclass 28, count 2 2006.257.01:33:14.30#ibcon#read 5, iclass 28, count 2 2006.257.01:33:14.30#ibcon#about to read 6, iclass 28, count 2 2006.257.01:33:14.30#ibcon#read 6, iclass 28, count 2 2006.257.01:33:14.30#ibcon#end of sib2, iclass 28, count 2 2006.257.01:33:14.30#ibcon#*after write, iclass 28, count 2 2006.257.01:33:14.30#ibcon#*before return 0, iclass 28, count 2 2006.257.01:33:14.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:14.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.01:33:14.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.01:33:14.30#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:14.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:14.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:14.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:14.42#ibcon#enter wrdev, iclass 28, count 0 2006.257.01:33:14.42#ibcon#first serial, iclass 28, count 0 2006.257.01:33:14.42#ibcon#enter sib2, iclass 28, count 0 2006.257.01:33:14.42#ibcon#flushed, iclass 28, count 0 2006.257.01:33:14.42#ibcon#about to write, iclass 28, count 0 2006.257.01:33:14.42#ibcon#wrote, iclass 28, count 0 2006.257.01:33:14.42#ibcon#about to read 3, iclass 28, count 0 2006.257.01:33:14.44#ibcon#read 3, iclass 28, count 0 2006.257.01:33:14.44#ibcon#about to read 4, iclass 28, count 0 2006.257.01:33:14.44#ibcon#read 4, iclass 28, count 0 2006.257.01:33:14.44#ibcon#about to read 5, iclass 28, count 0 2006.257.01:33:14.44#ibcon#read 5, iclass 28, count 0 2006.257.01:33:14.44#ibcon#about to read 6, iclass 28, count 0 2006.257.01:33:14.44#ibcon#read 6, iclass 28, count 0 2006.257.01:33:14.44#ibcon#end of sib2, iclass 28, count 0 2006.257.01:33:14.44#ibcon#*mode == 0, iclass 28, count 0 2006.257.01:33:14.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.01:33:14.44#ibcon#[27=USB\r\n] 2006.257.01:33:14.44#ibcon#*before write, iclass 28, count 0 2006.257.01:33:14.44#ibcon#enter sib2, iclass 28, count 0 2006.257.01:33:14.44#ibcon#flushed, iclass 28, count 0 2006.257.01:33:14.44#ibcon#about to write, iclass 28, count 0 2006.257.01:33:14.44#ibcon#wrote, iclass 28, count 0 2006.257.01:33:14.44#ibcon#about to read 3, iclass 28, count 0 2006.257.01:33:14.47#ibcon#read 3, iclass 28, count 0 2006.257.01:33:14.47#ibcon#about to read 4, iclass 28, count 0 2006.257.01:33:14.47#ibcon#read 4, iclass 28, count 0 2006.257.01:33:14.47#ibcon#about to read 5, iclass 28, count 0 2006.257.01:33:14.47#ibcon#read 5, iclass 28, count 0 2006.257.01:33:14.47#ibcon#about to read 6, iclass 28, count 0 2006.257.01:33:14.47#ibcon#read 6, iclass 28, count 0 2006.257.01:33:14.47#ibcon#end of sib2, iclass 28, count 0 2006.257.01:33:14.47#ibcon#*after write, iclass 28, count 0 2006.257.01:33:14.47#ibcon#*before return 0, iclass 28, count 0 2006.257.01:33:14.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:14.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.01:33:14.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.01:33:14.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.01:33:14.47$vck44/vblo=4,679.99 2006.257.01:33:14.47#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.01:33:14.47#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.01:33:14.47#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:14.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:14.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:14.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:14.47#ibcon#enter wrdev, iclass 30, count 0 2006.257.01:33:14.47#ibcon#first serial, iclass 30, count 0 2006.257.01:33:14.47#ibcon#enter sib2, iclass 30, count 0 2006.257.01:33:14.47#ibcon#flushed, iclass 30, count 0 2006.257.01:33:14.47#ibcon#about to write, iclass 30, count 0 2006.257.01:33:14.47#ibcon#wrote, iclass 30, count 0 2006.257.01:33:14.47#ibcon#about to read 3, iclass 30, count 0 2006.257.01:33:14.49#ibcon#read 3, iclass 30, count 0 2006.257.01:33:14.49#ibcon#about to read 4, iclass 30, count 0 2006.257.01:33:14.49#ibcon#read 4, iclass 30, count 0 2006.257.01:33:14.49#ibcon#about to read 5, iclass 30, count 0 2006.257.01:33:14.49#ibcon#read 5, iclass 30, count 0 2006.257.01:33:14.49#ibcon#about to read 6, iclass 30, count 0 2006.257.01:33:14.49#ibcon#read 6, iclass 30, count 0 2006.257.01:33:14.49#ibcon#end of sib2, iclass 30, count 0 2006.257.01:33:14.49#ibcon#*mode == 0, iclass 30, count 0 2006.257.01:33:14.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.01:33:14.49#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.01:33:14.49#ibcon#*before write, iclass 30, count 0 2006.257.01:33:14.49#ibcon#enter sib2, iclass 30, count 0 2006.257.01:33:14.49#ibcon#flushed, iclass 30, count 0 2006.257.01:33:14.49#ibcon#about to write, iclass 30, count 0 2006.257.01:33:14.49#ibcon#wrote, iclass 30, count 0 2006.257.01:33:14.49#ibcon#about to read 3, iclass 30, count 0 2006.257.01:33:14.53#ibcon#read 3, iclass 30, count 0 2006.257.01:33:14.53#ibcon#about to read 4, iclass 30, count 0 2006.257.01:33:14.53#ibcon#read 4, iclass 30, count 0 2006.257.01:33:14.53#ibcon#about to read 5, iclass 30, count 0 2006.257.01:33:14.53#ibcon#read 5, iclass 30, count 0 2006.257.01:33:14.53#ibcon#about to read 6, iclass 30, count 0 2006.257.01:33:14.53#ibcon#read 6, iclass 30, count 0 2006.257.01:33:14.53#ibcon#end of sib2, iclass 30, count 0 2006.257.01:33:14.53#ibcon#*after write, iclass 30, count 0 2006.257.01:33:14.53#ibcon#*before return 0, iclass 30, count 0 2006.257.01:33:14.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:14.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.01:33:14.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.01:33:14.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.01:33:14.53$vck44/vb=4,5 2006.257.01:33:14.53#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.01:33:14.53#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.01:33:14.53#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:14.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:14.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:14.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:14.59#ibcon#enter wrdev, iclass 32, count 2 2006.257.01:33:14.59#ibcon#first serial, iclass 32, count 2 2006.257.01:33:14.59#ibcon#enter sib2, iclass 32, count 2 2006.257.01:33:14.59#ibcon#flushed, iclass 32, count 2 2006.257.01:33:14.59#ibcon#about to write, iclass 32, count 2 2006.257.01:33:14.59#ibcon#wrote, iclass 32, count 2 2006.257.01:33:14.59#ibcon#about to read 3, iclass 32, count 2 2006.257.01:33:14.61#ibcon#read 3, iclass 32, count 2 2006.257.01:33:14.61#ibcon#about to read 4, iclass 32, count 2 2006.257.01:33:14.61#ibcon#read 4, iclass 32, count 2 2006.257.01:33:14.61#ibcon#about to read 5, iclass 32, count 2 2006.257.01:33:14.61#ibcon#read 5, iclass 32, count 2 2006.257.01:33:14.61#ibcon#about to read 6, iclass 32, count 2 2006.257.01:33:14.61#ibcon#read 6, iclass 32, count 2 2006.257.01:33:14.61#ibcon#end of sib2, iclass 32, count 2 2006.257.01:33:14.61#ibcon#*mode == 0, iclass 32, count 2 2006.257.01:33:14.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.01:33:14.61#ibcon#[27=AT04-05\r\n] 2006.257.01:33:14.61#ibcon#*before write, iclass 32, count 2 2006.257.01:33:14.61#ibcon#enter sib2, iclass 32, count 2 2006.257.01:33:14.61#ibcon#flushed, iclass 32, count 2 2006.257.01:33:14.61#ibcon#about to write, iclass 32, count 2 2006.257.01:33:14.61#ibcon#wrote, iclass 32, count 2 2006.257.01:33:14.61#ibcon#about to read 3, iclass 32, count 2 2006.257.01:33:14.64#ibcon#read 3, iclass 32, count 2 2006.257.01:33:14.64#ibcon#about to read 4, iclass 32, count 2 2006.257.01:33:14.64#ibcon#read 4, iclass 32, count 2 2006.257.01:33:14.64#ibcon#about to read 5, iclass 32, count 2 2006.257.01:33:14.64#ibcon#read 5, iclass 32, count 2 2006.257.01:33:14.64#ibcon#about to read 6, iclass 32, count 2 2006.257.01:33:14.64#ibcon#read 6, iclass 32, count 2 2006.257.01:33:14.64#ibcon#end of sib2, iclass 32, count 2 2006.257.01:33:14.64#ibcon#*after write, iclass 32, count 2 2006.257.01:33:14.64#ibcon#*before return 0, iclass 32, count 2 2006.257.01:33:14.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:14.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.01:33:14.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.01:33:14.64#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:14.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:14.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:14.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:14.76#ibcon#enter wrdev, iclass 32, count 0 2006.257.01:33:14.76#ibcon#first serial, iclass 32, count 0 2006.257.01:33:14.76#ibcon#enter sib2, iclass 32, count 0 2006.257.01:33:14.76#ibcon#flushed, iclass 32, count 0 2006.257.01:33:14.76#ibcon#about to write, iclass 32, count 0 2006.257.01:33:14.76#ibcon#wrote, iclass 32, count 0 2006.257.01:33:14.76#ibcon#about to read 3, iclass 32, count 0 2006.257.01:33:14.78#ibcon#read 3, iclass 32, count 0 2006.257.01:33:14.78#ibcon#about to read 4, iclass 32, count 0 2006.257.01:33:14.78#ibcon#read 4, iclass 32, count 0 2006.257.01:33:14.78#ibcon#about to read 5, iclass 32, count 0 2006.257.01:33:14.78#ibcon#read 5, iclass 32, count 0 2006.257.01:33:14.78#ibcon#about to read 6, iclass 32, count 0 2006.257.01:33:14.78#ibcon#read 6, iclass 32, count 0 2006.257.01:33:14.78#ibcon#end of sib2, iclass 32, count 0 2006.257.01:33:14.78#ibcon#*mode == 0, iclass 32, count 0 2006.257.01:33:14.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.01:33:14.78#ibcon#[27=USB\r\n] 2006.257.01:33:14.78#ibcon#*before write, iclass 32, count 0 2006.257.01:33:14.78#ibcon#enter sib2, iclass 32, count 0 2006.257.01:33:14.78#ibcon#flushed, iclass 32, count 0 2006.257.01:33:14.78#ibcon#about to write, iclass 32, count 0 2006.257.01:33:14.78#ibcon#wrote, iclass 32, count 0 2006.257.01:33:14.78#ibcon#about to read 3, iclass 32, count 0 2006.257.01:33:14.81#ibcon#read 3, iclass 32, count 0 2006.257.01:33:14.81#ibcon#about to read 4, iclass 32, count 0 2006.257.01:33:14.81#ibcon#read 4, iclass 32, count 0 2006.257.01:33:14.81#ibcon#about to read 5, iclass 32, count 0 2006.257.01:33:14.81#ibcon#read 5, iclass 32, count 0 2006.257.01:33:14.81#ibcon#about to read 6, iclass 32, count 0 2006.257.01:33:14.81#ibcon#read 6, iclass 32, count 0 2006.257.01:33:14.81#ibcon#end of sib2, iclass 32, count 0 2006.257.01:33:14.81#ibcon#*after write, iclass 32, count 0 2006.257.01:33:14.81#ibcon#*before return 0, iclass 32, count 0 2006.257.01:33:14.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:14.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.01:33:14.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.01:33:14.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.01:33:14.81$vck44/vblo=5,709.99 2006.257.01:33:14.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.01:33:14.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.01:33:14.81#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:14.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:14.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:14.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:14.81#ibcon#enter wrdev, iclass 34, count 0 2006.257.01:33:14.81#ibcon#first serial, iclass 34, count 0 2006.257.01:33:14.81#ibcon#enter sib2, iclass 34, count 0 2006.257.01:33:14.81#ibcon#flushed, iclass 34, count 0 2006.257.01:33:14.81#ibcon#about to write, iclass 34, count 0 2006.257.01:33:14.81#ibcon#wrote, iclass 34, count 0 2006.257.01:33:14.81#ibcon#about to read 3, iclass 34, count 0 2006.257.01:33:14.83#ibcon#read 3, iclass 34, count 0 2006.257.01:33:14.83#ibcon#about to read 4, iclass 34, count 0 2006.257.01:33:14.83#ibcon#read 4, iclass 34, count 0 2006.257.01:33:14.83#ibcon#about to read 5, iclass 34, count 0 2006.257.01:33:14.83#ibcon#read 5, iclass 34, count 0 2006.257.01:33:14.83#ibcon#about to read 6, iclass 34, count 0 2006.257.01:33:14.83#ibcon#read 6, iclass 34, count 0 2006.257.01:33:14.83#ibcon#end of sib2, iclass 34, count 0 2006.257.01:33:14.83#ibcon#*mode == 0, iclass 34, count 0 2006.257.01:33:14.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.01:33:14.83#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.01:33:14.83#ibcon#*before write, iclass 34, count 0 2006.257.01:33:14.83#ibcon#enter sib2, iclass 34, count 0 2006.257.01:33:14.83#ibcon#flushed, iclass 34, count 0 2006.257.01:33:14.83#ibcon#about to write, iclass 34, count 0 2006.257.01:33:14.83#ibcon#wrote, iclass 34, count 0 2006.257.01:33:14.83#ibcon#about to read 3, iclass 34, count 0 2006.257.01:33:14.87#ibcon#read 3, iclass 34, count 0 2006.257.01:33:14.87#ibcon#about to read 4, iclass 34, count 0 2006.257.01:33:14.87#ibcon#read 4, iclass 34, count 0 2006.257.01:33:14.87#ibcon#about to read 5, iclass 34, count 0 2006.257.01:33:14.87#ibcon#read 5, iclass 34, count 0 2006.257.01:33:14.87#ibcon#about to read 6, iclass 34, count 0 2006.257.01:33:14.87#ibcon#read 6, iclass 34, count 0 2006.257.01:33:14.87#ibcon#end of sib2, iclass 34, count 0 2006.257.01:33:14.87#ibcon#*after write, iclass 34, count 0 2006.257.01:33:14.87#ibcon#*before return 0, iclass 34, count 0 2006.257.01:33:14.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:14.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.01:33:14.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.01:33:14.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.01:33:14.87$vck44/vb=5,4 2006.257.01:33:14.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.01:33:14.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.01:33:14.87#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:14.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:14.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:14.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:14.93#ibcon#enter wrdev, iclass 36, count 2 2006.257.01:33:14.93#ibcon#first serial, iclass 36, count 2 2006.257.01:33:14.93#ibcon#enter sib2, iclass 36, count 2 2006.257.01:33:14.93#ibcon#flushed, iclass 36, count 2 2006.257.01:33:14.93#ibcon#about to write, iclass 36, count 2 2006.257.01:33:14.93#ibcon#wrote, iclass 36, count 2 2006.257.01:33:14.93#ibcon#about to read 3, iclass 36, count 2 2006.257.01:33:14.95#ibcon#read 3, iclass 36, count 2 2006.257.01:33:14.95#ibcon#about to read 4, iclass 36, count 2 2006.257.01:33:14.95#ibcon#read 4, iclass 36, count 2 2006.257.01:33:14.95#ibcon#about to read 5, iclass 36, count 2 2006.257.01:33:14.95#ibcon#read 5, iclass 36, count 2 2006.257.01:33:14.95#ibcon#about to read 6, iclass 36, count 2 2006.257.01:33:14.95#ibcon#read 6, iclass 36, count 2 2006.257.01:33:14.95#ibcon#end of sib2, iclass 36, count 2 2006.257.01:33:14.95#ibcon#*mode == 0, iclass 36, count 2 2006.257.01:33:14.95#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.01:33:14.95#ibcon#[27=AT05-04\r\n] 2006.257.01:33:14.95#ibcon#*before write, iclass 36, count 2 2006.257.01:33:14.95#ibcon#enter sib2, iclass 36, count 2 2006.257.01:33:14.95#ibcon#flushed, iclass 36, count 2 2006.257.01:33:14.95#ibcon#about to write, iclass 36, count 2 2006.257.01:33:14.95#ibcon#wrote, iclass 36, count 2 2006.257.01:33:14.95#ibcon#about to read 3, iclass 36, count 2 2006.257.01:33:14.98#ibcon#read 3, iclass 36, count 2 2006.257.01:33:14.98#ibcon#about to read 4, iclass 36, count 2 2006.257.01:33:14.98#ibcon#read 4, iclass 36, count 2 2006.257.01:33:14.98#ibcon#about to read 5, iclass 36, count 2 2006.257.01:33:14.98#ibcon#read 5, iclass 36, count 2 2006.257.01:33:14.98#ibcon#about to read 6, iclass 36, count 2 2006.257.01:33:14.98#ibcon#read 6, iclass 36, count 2 2006.257.01:33:14.98#ibcon#end of sib2, iclass 36, count 2 2006.257.01:33:14.98#ibcon#*after write, iclass 36, count 2 2006.257.01:33:14.98#ibcon#*before return 0, iclass 36, count 2 2006.257.01:33:14.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:14.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.01:33:14.98#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.01:33:14.98#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:14.98#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:15.10#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:15.10#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:15.10#ibcon#enter wrdev, iclass 36, count 0 2006.257.01:33:15.10#ibcon#first serial, iclass 36, count 0 2006.257.01:33:15.10#ibcon#enter sib2, iclass 36, count 0 2006.257.01:33:15.10#ibcon#flushed, iclass 36, count 0 2006.257.01:33:15.10#ibcon#about to write, iclass 36, count 0 2006.257.01:33:15.10#ibcon#wrote, iclass 36, count 0 2006.257.01:33:15.10#ibcon#about to read 3, iclass 36, count 0 2006.257.01:33:15.12#ibcon#read 3, iclass 36, count 0 2006.257.01:33:15.12#ibcon#about to read 4, iclass 36, count 0 2006.257.01:33:15.12#ibcon#read 4, iclass 36, count 0 2006.257.01:33:15.12#ibcon#about to read 5, iclass 36, count 0 2006.257.01:33:15.12#ibcon#read 5, iclass 36, count 0 2006.257.01:33:15.12#ibcon#about to read 6, iclass 36, count 0 2006.257.01:33:15.12#ibcon#read 6, iclass 36, count 0 2006.257.01:33:15.12#ibcon#end of sib2, iclass 36, count 0 2006.257.01:33:15.12#ibcon#*mode == 0, iclass 36, count 0 2006.257.01:33:15.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.01:33:15.12#ibcon#[27=USB\r\n] 2006.257.01:33:15.12#ibcon#*before write, iclass 36, count 0 2006.257.01:33:15.12#ibcon#enter sib2, iclass 36, count 0 2006.257.01:33:15.12#ibcon#flushed, iclass 36, count 0 2006.257.01:33:15.12#ibcon#about to write, iclass 36, count 0 2006.257.01:33:15.12#ibcon#wrote, iclass 36, count 0 2006.257.01:33:15.12#ibcon#about to read 3, iclass 36, count 0 2006.257.01:33:15.15#ibcon#read 3, iclass 36, count 0 2006.257.01:33:15.15#ibcon#about to read 4, iclass 36, count 0 2006.257.01:33:15.15#ibcon#read 4, iclass 36, count 0 2006.257.01:33:15.15#ibcon#about to read 5, iclass 36, count 0 2006.257.01:33:15.15#ibcon#read 5, iclass 36, count 0 2006.257.01:33:15.15#ibcon#about to read 6, iclass 36, count 0 2006.257.01:33:15.15#ibcon#read 6, iclass 36, count 0 2006.257.01:33:15.15#ibcon#end of sib2, iclass 36, count 0 2006.257.01:33:15.15#ibcon#*after write, iclass 36, count 0 2006.257.01:33:15.15#ibcon#*before return 0, iclass 36, count 0 2006.257.01:33:15.15#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:15.15#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.01:33:15.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.01:33:15.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.01:33:15.15$vck44/vblo=6,719.99 2006.257.01:33:15.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.01:33:15.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.01:33:15.15#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:15.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:15.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:15.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:15.15#ibcon#enter wrdev, iclass 38, count 0 2006.257.01:33:15.15#ibcon#first serial, iclass 38, count 0 2006.257.01:33:15.15#ibcon#enter sib2, iclass 38, count 0 2006.257.01:33:15.15#ibcon#flushed, iclass 38, count 0 2006.257.01:33:15.15#ibcon#about to write, iclass 38, count 0 2006.257.01:33:15.15#ibcon#wrote, iclass 38, count 0 2006.257.01:33:15.15#ibcon#about to read 3, iclass 38, count 0 2006.257.01:33:15.17#ibcon#read 3, iclass 38, count 0 2006.257.01:33:15.17#ibcon#about to read 4, iclass 38, count 0 2006.257.01:33:15.17#ibcon#read 4, iclass 38, count 0 2006.257.01:33:15.17#ibcon#about to read 5, iclass 38, count 0 2006.257.01:33:15.17#ibcon#read 5, iclass 38, count 0 2006.257.01:33:15.17#ibcon#about to read 6, iclass 38, count 0 2006.257.01:33:15.17#ibcon#read 6, iclass 38, count 0 2006.257.01:33:15.17#ibcon#end of sib2, iclass 38, count 0 2006.257.01:33:15.17#ibcon#*mode == 0, iclass 38, count 0 2006.257.01:33:15.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.01:33:15.17#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.01:33:15.17#ibcon#*before write, iclass 38, count 0 2006.257.01:33:15.17#ibcon#enter sib2, iclass 38, count 0 2006.257.01:33:15.17#ibcon#flushed, iclass 38, count 0 2006.257.01:33:15.17#ibcon#about to write, iclass 38, count 0 2006.257.01:33:15.17#ibcon#wrote, iclass 38, count 0 2006.257.01:33:15.17#ibcon#about to read 3, iclass 38, count 0 2006.257.01:33:15.21#ibcon#read 3, iclass 38, count 0 2006.257.01:33:15.21#ibcon#about to read 4, iclass 38, count 0 2006.257.01:33:15.21#ibcon#read 4, iclass 38, count 0 2006.257.01:33:15.21#ibcon#about to read 5, iclass 38, count 0 2006.257.01:33:15.21#ibcon#read 5, iclass 38, count 0 2006.257.01:33:15.21#ibcon#about to read 6, iclass 38, count 0 2006.257.01:33:15.21#ibcon#read 6, iclass 38, count 0 2006.257.01:33:15.21#ibcon#end of sib2, iclass 38, count 0 2006.257.01:33:15.21#ibcon#*after write, iclass 38, count 0 2006.257.01:33:15.21#ibcon#*before return 0, iclass 38, count 0 2006.257.01:33:15.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:15.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.01:33:15.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.01:33:15.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.01:33:15.21$vck44/vb=6,4 2006.257.01:33:15.21#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.01:33:15.21#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.01:33:15.21#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:15.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:15.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:15.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:15.27#ibcon#enter wrdev, iclass 40, count 2 2006.257.01:33:15.27#ibcon#first serial, iclass 40, count 2 2006.257.01:33:15.27#ibcon#enter sib2, iclass 40, count 2 2006.257.01:33:15.27#ibcon#flushed, iclass 40, count 2 2006.257.01:33:15.27#ibcon#about to write, iclass 40, count 2 2006.257.01:33:15.27#ibcon#wrote, iclass 40, count 2 2006.257.01:33:15.27#ibcon#about to read 3, iclass 40, count 2 2006.257.01:33:15.29#ibcon#read 3, iclass 40, count 2 2006.257.01:33:15.29#ibcon#about to read 4, iclass 40, count 2 2006.257.01:33:15.29#ibcon#read 4, iclass 40, count 2 2006.257.01:33:15.29#ibcon#about to read 5, iclass 40, count 2 2006.257.01:33:15.29#ibcon#read 5, iclass 40, count 2 2006.257.01:33:15.29#ibcon#about to read 6, iclass 40, count 2 2006.257.01:33:15.29#ibcon#read 6, iclass 40, count 2 2006.257.01:33:15.29#ibcon#end of sib2, iclass 40, count 2 2006.257.01:33:15.29#ibcon#*mode == 0, iclass 40, count 2 2006.257.01:33:15.29#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.01:33:15.29#ibcon#[27=AT06-04\r\n] 2006.257.01:33:15.29#ibcon#*before write, iclass 40, count 2 2006.257.01:33:15.29#ibcon#enter sib2, iclass 40, count 2 2006.257.01:33:15.29#ibcon#flushed, iclass 40, count 2 2006.257.01:33:15.29#ibcon#about to write, iclass 40, count 2 2006.257.01:33:15.29#ibcon#wrote, iclass 40, count 2 2006.257.01:33:15.29#ibcon#about to read 3, iclass 40, count 2 2006.257.01:33:15.32#ibcon#read 3, iclass 40, count 2 2006.257.01:33:15.32#ibcon#about to read 4, iclass 40, count 2 2006.257.01:33:15.32#ibcon#read 4, iclass 40, count 2 2006.257.01:33:15.32#ibcon#about to read 5, iclass 40, count 2 2006.257.01:33:15.32#ibcon#read 5, iclass 40, count 2 2006.257.01:33:15.32#ibcon#about to read 6, iclass 40, count 2 2006.257.01:33:15.32#ibcon#read 6, iclass 40, count 2 2006.257.01:33:15.32#ibcon#end of sib2, iclass 40, count 2 2006.257.01:33:15.32#ibcon#*after write, iclass 40, count 2 2006.257.01:33:15.32#ibcon#*before return 0, iclass 40, count 2 2006.257.01:33:15.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:15.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.01:33:15.32#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.01:33:15.32#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:15.32#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:15.44#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:15.44#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:15.44#ibcon#enter wrdev, iclass 40, count 0 2006.257.01:33:15.44#ibcon#first serial, iclass 40, count 0 2006.257.01:33:15.44#ibcon#enter sib2, iclass 40, count 0 2006.257.01:33:15.44#ibcon#flushed, iclass 40, count 0 2006.257.01:33:15.44#ibcon#about to write, iclass 40, count 0 2006.257.01:33:15.44#ibcon#wrote, iclass 40, count 0 2006.257.01:33:15.44#ibcon#about to read 3, iclass 40, count 0 2006.257.01:33:15.46#ibcon#read 3, iclass 40, count 0 2006.257.01:33:15.46#ibcon#about to read 4, iclass 40, count 0 2006.257.01:33:15.46#ibcon#read 4, iclass 40, count 0 2006.257.01:33:15.46#ibcon#about to read 5, iclass 40, count 0 2006.257.01:33:15.46#ibcon#read 5, iclass 40, count 0 2006.257.01:33:15.46#ibcon#about to read 6, iclass 40, count 0 2006.257.01:33:15.46#ibcon#read 6, iclass 40, count 0 2006.257.01:33:15.46#ibcon#end of sib2, iclass 40, count 0 2006.257.01:33:15.46#ibcon#*mode == 0, iclass 40, count 0 2006.257.01:33:15.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.01:33:15.46#ibcon#[27=USB\r\n] 2006.257.01:33:15.46#ibcon#*before write, iclass 40, count 0 2006.257.01:33:15.46#ibcon#enter sib2, iclass 40, count 0 2006.257.01:33:15.46#ibcon#flushed, iclass 40, count 0 2006.257.01:33:15.46#ibcon#about to write, iclass 40, count 0 2006.257.01:33:15.46#ibcon#wrote, iclass 40, count 0 2006.257.01:33:15.46#ibcon#about to read 3, iclass 40, count 0 2006.257.01:33:15.49#ibcon#read 3, iclass 40, count 0 2006.257.01:33:15.49#ibcon#about to read 4, iclass 40, count 0 2006.257.01:33:15.49#ibcon#read 4, iclass 40, count 0 2006.257.01:33:15.49#ibcon#about to read 5, iclass 40, count 0 2006.257.01:33:15.49#ibcon#read 5, iclass 40, count 0 2006.257.01:33:15.49#ibcon#about to read 6, iclass 40, count 0 2006.257.01:33:15.49#ibcon#read 6, iclass 40, count 0 2006.257.01:33:15.49#ibcon#end of sib2, iclass 40, count 0 2006.257.01:33:15.49#ibcon#*after write, iclass 40, count 0 2006.257.01:33:15.49#ibcon#*before return 0, iclass 40, count 0 2006.257.01:33:15.49#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:15.49#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.01:33:15.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.01:33:15.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.01:33:15.49$vck44/vblo=7,734.99 2006.257.01:33:15.49#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.01:33:15.49#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.01:33:15.49#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:15.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:15.49#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:15.49#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:15.49#ibcon#enter wrdev, iclass 4, count 0 2006.257.01:33:15.49#ibcon#first serial, iclass 4, count 0 2006.257.01:33:15.49#ibcon#enter sib2, iclass 4, count 0 2006.257.01:33:15.49#ibcon#flushed, iclass 4, count 0 2006.257.01:33:15.49#ibcon#about to write, iclass 4, count 0 2006.257.01:33:15.49#ibcon#wrote, iclass 4, count 0 2006.257.01:33:15.49#ibcon#about to read 3, iclass 4, count 0 2006.257.01:33:15.51#ibcon#read 3, iclass 4, count 0 2006.257.01:33:15.51#ibcon#about to read 4, iclass 4, count 0 2006.257.01:33:15.51#ibcon#read 4, iclass 4, count 0 2006.257.01:33:15.51#ibcon#about to read 5, iclass 4, count 0 2006.257.01:33:15.51#ibcon#read 5, iclass 4, count 0 2006.257.01:33:15.51#ibcon#about to read 6, iclass 4, count 0 2006.257.01:33:15.51#ibcon#read 6, iclass 4, count 0 2006.257.01:33:15.51#ibcon#end of sib2, iclass 4, count 0 2006.257.01:33:15.51#ibcon#*mode == 0, iclass 4, count 0 2006.257.01:33:15.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.01:33:15.51#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.01:33:15.51#ibcon#*before write, iclass 4, count 0 2006.257.01:33:15.51#ibcon#enter sib2, iclass 4, count 0 2006.257.01:33:15.51#ibcon#flushed, iclass 4, count 0 2006.257.01:33:15.51#ibcon#about to write, iclass 4, count 0 2006.257.01:33:15.51#ibcon#wrote, iclass 4, count 0 2006.257.01:33:15.51#ibcon#about to read 3, iclass 4, count 0 2006.257.01:33:15.55#ibcon#read 3, iclass 4, count 0 2006.257.01:33:15.55#ibcon#about to read 4, iclass 4, count 0 2006.257.01:33:15.55#ibcon#read 4, iclass 4, count 0 2006.257.01:33:15.55#ibcon#about to read 5, iclass 4, count 0 2006.257.01:33:15.55#ibcon#read 5, iclass 4, count 0 2006.257.01:33:15.55#ibcon#about to read 6, iclass 4, count 0 2006.257.01:33:15.55#ibcon#read 6, iclass 4, count 0 2006.257.01:33:15.55#ibcon#end of sib2, iclass 4, count 0 2006.257.01:33:15.55#ibcon#*after write, iclass 4, count 0 2006.257.01:33:15.55#ibcon#*before return 0, iclass 4, count 0 2006.257.01:33:15.55#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:15.55#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.01:33:15.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.01:33:15.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.01:33:15.55$vck44/vb=7,4 2006.257.01:33:15.55#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.01:33:15.55#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.01:33:15.55#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:15.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:15.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:15.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:15.61#ibcon#enter wrdev, iclass 6, count 2 2006.257.01:33:15.61#ibcon#first serial, iclass 6, count 2 2006.257.01:33:15.61#ibcon#enter sib2, iclass 6, count 2 2006.257.01:33:15.61#ibcon#flushed, iclass 6, count 2 2006.257.01:33:15.61#ibcon#about to write, iclass 6, count 2 2006.257.01:33:15.61#ibcon#wrote, iclass 6, count 2 2006.257.01:33:15.61#ibcon#about to read 3, iclass 6, count 2 2006.257.01:33:15.63#ibcon#read 3, iclass 6, count 2 2006.257.01:33:15.63#ibcon#about to read 4, iclass 6, count 2 2006.257.01:33:15.63#ibcon#read 4, iclass 6, count 2 2006.257.01:33:15.63#ibcon#about to read 5, iclass 6, count 2 2006.257.01:33:15.63#ibcon#read 5, iclass 6, count 2 2006.257.01:33:15.63#ibcon#about to read 6, iclass 6, count 2 2006.257.01:33:15.63#ibcon#read 6, iclass 6, count 2 2006.257.01:33:15.63#ibcon#end of sib2, iclass 6, count 2 2006.257.01:33:15.63#ibcon#*mode == 0, iclass 6, count 2 2006.257.01:33:15.63#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.01:33:15.63#ibcon#[27=AT07-04\r\n] 2006.257.01:33:15.63#ibcon#*before write, iclass 6, count 2 2006.257.01:33:15.63#ibcon#enter sib2, iclass 6, count 2 2006.257.01:33:15.63#ibcon#flushed, iclass 6, count 2 2006.257.01:33:15.63#ibcon#about to write, iclass 6, count 2 2006.257.01:33:15.63#ibcon#wrote, iclass 6, count 2 2006.257.01:33:15.63#ibcon#about to read 3, iclass 6, count 2 2006.257.01:33:15.66#ibcon#read 3, iclass 6, count 2 2006.257.01:33:15.66#ibcon#about to read 4, iclass 6, count 2 2006.257.01:33:15.66#ibcon#read 4, iclass 6, count 2 2006.257.01:33:15.66#ibcon#about to read 5, iclass 6, count 2 2006.257.01:33:15.66#ibcon#read 5, iclass 6, count 2 2006.257.01:33:15.66#ibcon#about to read 6, iclass 6, count 2 2006.257.01:33:15.66#ibcon#read 6, iclass 6, count 2 2006.257.01:33:15.66#ibcon#end of sib2, iclass 6, count 2 2006.257.01:33:15.66#ibcon#*after write, iclass 6, count 2 2006.257.01:33:15.66#ibcon#*before return 0, iclass 6, count 2 2006.257.01:33:15.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:15.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.01:33:15.66#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.01:33:15.66#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:15.66#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:15.78#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:15.78#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:15.78#ibcon#enter wrdev, iclass 6, count 0 2006.257.01:33:15.78#ibcon#first serial, iclass 6, count 0 2006.257.01:33:15.78#ibcon#enter sib2, iclass 6, count 0 2006.257.01:33:15.78#ibcon#flushed, iclass 6, count 0 2006.257.01:33:15.78#ibcon#about to write, iclass 6, count 0 2006.257.01:33:15.78#ibcon#wrote, iclass 6, count 0 2006.257.01:33:15.78#ibcon#about to read 3, iclass 6, count 0 2006.257.01:33:15.80#ibcon#read 3, iclass 6, count 0 2006.257.01:33:15.80#ibcon#about to read 4, iclass 6, count 0 2006.257.01:33:15.80#ibcon#read 4, iclass 6, count 0 2006.257.01:33:15.80#ibcon#about to read 5, iclass 6, count 0 2006.257.01:33:15.80#ibcon#read 5, iclass 6, count 0 2006.257.01:33:15.80#ibcon#about to read 6, iclass 6, count 0 2006.257.01:33:15.80#ibcon#read 6, iclass 6, count 0 2006.257.01:33:15.80#ibcon#end of sib2, iclass 6, count 0 2006.257.01:33:15.80#ibcon#*mode == 0, iclass 6, count 0 2006.257.01:33:15.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.01:33:15.80#ibcon#[27=USB\r\n] 2006.257.01:33:15.80#ibcon#*before write, iclass 6, count 0 2006.257.01:33:15.80#ibcon#enter sib2, iclass 6, count 0 2006.257.01:33:15.80#ibcon#flushed, iclass 6, count 0 2006.257.01:33:15.80#ibcon#about to write, iclass 6, count 0 2006.257.01:33:15.80#ibcon#wrote, iclass 6, count 0 2006.257.01:33:15.80#ibcon#about to read 3, iclass 6, count 0 2006.257.01:33:15.83#ibcon#read 3, iclass 6, count 0 2006.257.01:33:15.83#ibcon#about to read 4, iclass 6, count 0 2006.257.01:33:15.83#ibcon#read 4, iclass 6, count 0 2006.257.01:33:15.83#ibcon#about to read 5, iclass 6, count 0 2006.257.01:33:15.83#ibcon#read 5, iclass 6, count 0 2006.257.01:33:15.83#ibcon#about to read 6, iclass 6, count 0 2006.257.01:33:15.83#ibcon#read 6, iclass 6, count 0 2006.257.01:33:15.83#ibcon#end of sib2, iclass 6, count 0 2006.257.01:33:15.83#ibcon#*after write, iclass 6, count 0 2006.257.01:33:15.83#ibcon#*before return 0, iclass 6, count 0 2006.257.01:33:15.83#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:15.83#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.01:33:15.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.01:33:15.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.01:33:15.83$vck44/vblo=8,744.99 2006.257.01:33:15.83#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.01:33:15.83#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.01:33:15.83#ibcon#ireg 17 cls_cnt 0 2006.257.01:33:15.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.01:33:15.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.01:33:15.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.01:33:15.83#ibcon#enter wrdev, iclass 10, count 0 2006.257.01:33:15.83#ibcon#first serial, iclass 10, count 0 2006.257.01:33:15.83#ibcon#enter sib2, iclass 10, count 0 2006.257.01:33:15.83#ibcon#flushed, iclass 10, count 0 2006.257.01:33:15.83#ibcon#about to write, iclass 10, count 0 2006.257.01:33:15.83#ibcon#wrote, iclass 10, count 0 2006.257.01:33:15.83#ibcon#about to read 3, iclass 10, count 0 2006.257.01:33:15.85#ibcon#read 3, iclass 10, count 0 2006.257.01:33:15.85#ibcon#about to read 4, iclass 10, count 0 2006.257.01:33:15.85#ibcon#read 4, iclass 10, count 0 2006.257.01:33:15.85#ibcon#about to read 5, iclass 10, count 0 2006.257.01:33:15.85#ibcon#read 5, iclass 10, count 0 2006.257.01:33:15.85#ibcon#about to read 6, iclass 10, count 0 2006.257.01:33:15.85#ibcon#read 6, iclass 10, count 0 2006.257.01:33:15.85#ibcon#end of sib2, iclass 10, count 0 2006.257.01:33:15.85#ibcon#*mode == 0, iclass 10, count 0 2006.257.01:33:15.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.01:33:15.85#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.01:33:15.85#ibcon#*before write, iclass 10, count 0 2006.257.01:33:15.85#ibcon#enter sib2, iclass 10, count 0 2006.257.01:33:15.85#ibcon#flushed, iclass 10, count 0 2006.257.01:33:15.85#ibcon#about to write, iclass 10, count 0 2006.257.01:33:15.85#ibcon#wrote, iclass 10, count 0 2006.257.01:33:15.85#ibcon#about to read 3, iclass 10, count 0 2006.257.01:33:15.89#ibcon#read 3, iclass 10, count 0 2006.257.01:33:15.89#ibcon#about to read 4, iclass 10, count 0 2006.257.01:33:15.89#ibcon#read 4, iclass 10, count 0 2006.257.01:33:15.89#ibcon#about to read 5, iclass 10, count 0 2006.257.01:33:15.89#ibcon#read 5, iclass 10, count 0 2006.257.01:33:15.89#ibcon#about to read 6, iclass 10, count 0 2006.257.01:33:15.89#ibcon#read 6, iclass 10, count 0 2006.257.01:33:15.89#ibcon#end of sib2, iclass 10, count 0 2006.257.01:33:15.89#ibcon#*after write, iclass 10, count 0 2006.257.01:33:15.89#ibcon#*before return 0, iclass 10, count 0 2006.257.01:33:15.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.01:33:15.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.01:33:15.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.01:33:15.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.01:33:15.89$vck44/vb=8,4 2006.257.01:33:15.89#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.01:33:15.89#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.01:33:15.89#ibcon#ireg 11 cls_cnt 2 2006.257.01:33:15.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.01:33:15.95#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.01:33:15.95#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.01:33:15.95#ibcon#enter wrdev, iclass 12, count 2 2006.257.01:33:15.95#ibcon#first serial, iclass 12, count 2 2006.257.01:33:15.95#ibcon#enter sib2, iclass 12, count 2 2006.257.01:33:15.95#ibcon#flushed, iclass 12, count 2 2006.257.01:33:15.95#ibcon#about to write, iclass 12, count 2 2006.257.01:33:15.95#ibcon#wrote, iclass 12, count 2 2006.257.01:33:15.95#ibcon#about to read 3, iclass 12, count 2 2006.257.01:33:15.98#ibcon#read 3, iclass 12, count 2 2006.257.01:33:15.98#ibcon#about to read 4, iclass 12, count 2 2006.257.01:33:15.98#ibcon#read 4, iclass 12, count 2 2006.257.01:33:15.98#ibcon#about to read 5, iclass 12, count 2 2006.257.01:33:15.98#ibcon#read 5, iclass 12, count 2 2006.257.01:33:15.98#ibcon#about to read 6, iclass 12, count 2 2006.257.01:33:15.98#ibcon#read 6, iclass 12, count 2 2006.257.01:33:15.98#ibcon#end of sib2, iclass 12, count 2 2006.257.01:33:15.98#ibcon#*mode == 0, iclass 12, count 2 2006.257.01:33:15.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.01:33:15.98#ibcon#[27=AT08-04\r\n] 2006.257.01:33:15.98#ibcon#*before write, iclass 12, count 2 2006.257.01:33:15.98#ibcon#enter sib2, iclass 12, count 2 2006.257.01:33:15.98#ibcon#flushed, iclass 12, count 2 2006.257.01:33:15.98#ibcon#about to write, iclass 12, count 2 2006.257.01:33:15.98#ibcon#wrote, iclass 12, count 2 2006.257.01:33:15.98#ibcon#about to read 3, iclass 12, count 2 2006.257.01:33:16.01#ibcon#read 3, iclass 12, count 2 2006.257.01:33:16.01#ibcon#about to read 4, iclass 12, count 2 2006.257.01:33:16.01#ibcon#read 4, iclass 12, count 2 2006.257.01:33:16.01#ibcon#about to read 5, iclass 12, count 2 2006.257.01:33:16.01#ibcon#read 5, iclass 12, count 2 2006.257.01:33:16.01#ibcon#about to read 6, iclass 12, count 2 2006.257.01:33:16.01#ibcon#read 6, iclass 12, count 2 2006.257.01:33:16.01#ibcon#end of sib2, iclass 12, count 2 2006.257.01:33:16.01#ibcon#*after write, iclass 12, count 2 2006.257.01:33:16.01#ibcon#*before return 0, iclass 12, count 2 2006.257.01:33:16.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.01:33:16.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.01:33:16.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.01:33:16.01#ibcon#ireg 7 cls_cnt 0 2006.257.01:33:16.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.01:33:16.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.01:33:16.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.01:33:16.13#ibcon#enter wrdev, iclass 12, count 0 2006.257.01:33:16.13#ibcon#first serial, iclass 12, count 0 2006.257.01:33:16.13#ibcon#enter sib2, iclass 12, count 0 2006.257.01:33:16.13#ibcon#flushed, iclass 12, count 0 2006.257.01:33:16.13#ibcon#about to write, iclass 12, count 0 2006.257.01:33:16.13#ibcon#wrote, iclass 12, count 0 2006.257.01:33:16.13#ibcon#about to read 3, iclass 12, count 0 2006.257.01:33:16.15#ibcon#read 3, iclass 12, count 0 2006.257.01:33:16.15#ibcon#about to read 4, iclass 12, count 0 2006.257.01:33:16.15#ibcon#read 4, iclass 12, count 0 2006.257.01:33:16.15#ibcon#about to read 5, iclass 12, count 0 2006.257.01:33:16.15#ibcon#read 5, iclass 12, count 0 2006.257.01:33:16.15#ibcon#about to read 6, iclass 12, count 0 2006.257.01:33:16.15#ibcon#read 6, iclass 12, count 0 2006.257.01:33:16.15#ibcon#end of sib2, iclass 12, count 0 2006.257.01:33:16.15#ibcon#*mode == 0, iclass 12, count 0 2006.257.01:33:16.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.01:33:16.15#ibcon#[27=USB\r\n] 2006.257.01:33:16.15#ibcon#*before write, iclass 12, count 0 2006.257.01:33:16.15#ibcon#enter sib2, iclass 12, count 0 2006.257.01:33:16.15#ibcon#flushed, iclass 12, count 0 2006.257.01:33:16.15#ibcon#about to write, iclass 12, count 0 2006.257.01:33:16.15#ibcon#wrote, iclass 12, count 0 2006.257.01:33:16.15#ibcon#about to read 3, iclass 12, count 0 2006.257.01:33:16.18#ibcon#read 3, iclass 12, count 0 2006.257.01:33:16.18#ibcon#about to read 4, iclass 12, count 0 2006.257.01:33:16.18#ibcon#read 4, iclass 12, count 0 2006.257.01:33:16.18#ibcon#about to read 5, iclass 12, count 0 2006.257.01:33:16.18#ibcon#read 5, iclass 12, count 0 2006.257.01:33:16.18#ibcon#about to read 6, iclass 12, count 0 2006.257.01:33:16.18#ibcon#read 6, iclass 12, count 0 2006.257.01:33:16.18#ibcon#end of sib2, iclass 12, count 0 2006.257.01:33:16.18#ibcon#*after write, iclass 12, count 0 2006.257.01:33:16.18#ibcon#*before return 0, iclass 12, count 0 2006.257.01:33:16.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.01:33:16.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.01:33:16.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.01:33:16.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.01:33:16.18$vck44/vabw=wide 2006.257.01:33:16.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.01:33:16.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.01:33:16.18#ibcon#ireg 8 cls_cnt 0 2006.257.01:33:16.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:16.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:16.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:16.18#ibcon#enter wrdev, iclass 14, count 0 2006.257.01:33:16.18#ibcon#first serial, iclass 14, count 0 2006.257.01:33:16.18#ibcon#enter sib2, iclass 14, count 0 2006.257.01:33:16.18#ibcon#flushed, iclass 14, count 0 2006.257.01:33:16.18#ibcon#about to write, iclass 14, count 0 2006.257.01:33:16.18#ibcon#wrote, iclass 14, count 0 2006.257.01:33:16.18#ibcon#about to read 3, iclass 14, count 0 2006.257.01:33:16.20#ibcon#read 3, iclass 14, count 0 2006.257.01:33:16.20#ibcon#about to read 4, iclass 14, count 0 2006.257.01:33:16.20#ibcon#read 4, iclass 14, count 0 2006.257.01:33:16.20#ibcon#about to read 5, iclass 14, count 0 2006.257.01:33:16.20#ibcon#read 5, iclass 14, count 0 2006.257.01:33:16.20#ibcon#about to read 6, iclass 14, count 0 2006.257.01:33:16.20#ibcon#read 6, iclass 14, count 0 2006.257.01:33:16.20#ibcon#end of sib2, iclass 14, count 0 2006.257.01:33:16.20#ibcon#*mode == 0, iclass 14, count 0 2006.257.01:33:16.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.01:33:16.20#ibcon#[25=BW32\r\n] 2006.257.01:33:16.20#ibcon#*before write, iclass 14, count 0 2006.257.01:33:16.20#ibcon#enter sib2, iclass 14, count 0 2006.257.01:33:16.20#ibcon#flushed, iclass 14, count 0 2006.257.01:33:16.20#ibcon#about to write, iclass 14, count 0 2006.257.01:33:16.20#ibcon#wrote, iclass 14, count 0 2006.257.01:33:16.20#ibcon#about to read 3, iclass 14, count 0 2006.257.01:33:16.23#ibcon#read 3, iclass 14, count 0 2006.257.01:33:16.23#ibcon#about to read 4, iclass 14, count 0 2006.257.01:33:16.23#ibcon#read 4, iclass 14, count 0 2006.257.01:33:16.23#ibcon#about to read 5, iclass 14, count 0 2006.257.01:33:16.23#ibcon#read 5, iclass 14, count 0 2006.257.01:33:16.23#ibcon#about to read 6, iclass 14, count 0 2006.257.01:33:16.23#ibcon#read 6, iclass 14, count 0 2006.257.01:33:16.23#ibcon#end of sib2, iclass 14, count 0 2006.257.01:33:16.23#ibcon#*after write, iclass 14, count 0 2006.257.01:33:16.23#ibcon#*before return 0, iclass 14, count 0 2006.257.01:33:16.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:16.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.01:33:16.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.01:33:16.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.01:33:16.23$vck44/vbbw=wide 2006.257.01:33:16.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.01:33:16.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.01:33:16.23#ibcon#ireg 8 cls_cnt 0 2006.257.01:33:16.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.01:33:16.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.01:33:16.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.01:33:16.30#ibcon#enter wrdev, iclass 16, count 0 2006.257.01:33:16.30#ibcon#first serial, iclass 16, count 0 2006.257.01:33:16.30#ibcon#enter sib2, iclass 16, count 0 2006.257.01:33:16.30#ibcon#flushed, iclass 16, count 0 2006.257.01:33:16.30#ibcon#about to write, iclass 16, count 0 2006.257.01:33:16.30#ibcon#wrote, iclass 16, count 0 2006.257.01:33:16.30#ibcon#about to read 3, iclass 16, count 0 2006.257.01:33:16.32#ibcon#read 3, iclass 16, count 0 2006.257.01:33:16.32#ibcon#about to read 4, iclass 16, count 0 2006.257.01:33:16.32#ibcon#read 4, iclass 16, count 0 2006.257.01:33:16.32#ibcon#about to read 5, iclass 16, count 0 2006.257.01:33:16.32#ibcon#read 5, iclass 16, count 0 2006.257.01:33:16.32#ibcon#about to read 6, iclass 16, count 0 2006.257.01:33:16.32#ibcon#read 6, iclass 16, count 0 2006.257.01:33:16.32#ibcon#end of sib2, iclass 16, count 0 2006.257.01:33:16.32#ibcon#*mode == 0, iclass 16, count 0 2006.257.01:33:16.32#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.01:33:16.32#ibcon#[27=BW32\r\n] 2006.257.01:33:16.32#ibcon#*before write, iclass 16, count 0 2006.257.01:33:16.32#ibcon#enter sib2, iclass 16, count 0 2006.257.01:33:16.32#ibcon#flushed, iclass 16, count 0 2006.257.01:33:16.32#ibcon#about to write, iclass 16, count 0 2006.257.01:33:16.32#ibcon#wrote, iclass 16, count 0 2006.257.01:33:16.32#ibcon#about to read 3, iclass 16, count 0 2006.257.01:33:16.35#ibcon#read 3, iclass 16, count 0 2006.257.01:33:16.35#ibcon#about to read 4, iclass 16, count 0 2006.257.01:33:16.35#ibcon#read 4, iclass 16, count 0 2006.257.01:33:16.35#ibcon#about to read 5, iclass 16, count 0 2006.257.01:33:16.35#ibcon#read 5, iclass 16, count 0 2006.257.01:33:16.35#ibcon#about to read 6, iclass 16, count 0 2006.257.01:33:16.35#ibcon#read 6, iclass 16, count 0 2006.257.01:33:16.35#ibcon#end of sib2, iclass 16, count 0 2006.257.01:33:16.35#ibcon#*after write, iclass 16, count 0 2006.257.01:33:16.35#ibcon#*before return 0, iclass 16, count 0 2006.257.01:33:16.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.01:33:16.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.01:33:16.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.01:33:16.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.01:33:16.35$setupk4/ifdk4 2006.257.01:33:16.35$ifdk4/lo= 2006.257.01:33:16.35$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.01:33:16.35$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.01:33:16.35$ifdk4/patch= 2006.257.01:33:16.35$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.01:33:16.35$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.01:33:16.35$setupk4/!*+20s 2006.257.01:33:16.35$unstow/antenna=m2 2006.257.01:33:19.14#trakl#Antenna moving 2006.257.01:33:23.21#abcon#<5=/15 1.5 4.1 17.611001013.0\r\n> 2006.257.01:33:23.23#abcon#{5=INTERFACE CLEAR} 2006.257.01:33:23.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.01:33:30.85$setupk4/"tpicd 2006.257.01:33:30.85$setupk4/echo=off 2006.257.01:33:30.85$setupk4/xlog=off 2006.257.01:33:30.85:!2006.257.01:59:50 2006.257.01:33:47.14#trakl#Source acquired 2006.257.01:33:49.14#flagr#flagr/antenna,acquired 2006.257.01:35:02.69;cable 2006.257.01:35:02.83/cable/+6.4891E-03 2006.257.01:35:59.37;cablelong 2006.257.01:35:59.51/cablelong/+7.0408E-03 2006.257.01:36:04.35;cablediff 2006.257.01:36:04.35/cablediff/551.7e-6,+ 2006.257.01:36:58.35;cable 2006.257.01:36:58.51/cable/+6.4895E-03 2006.257.01:37:06.31;wx 2006.257.01:37:06.31/wx/17.99,1012.8,100 2006.257.01:37:13.24;"Sky is rainy. 2006.257.01:37:18.50;xfe 2006.257.01:37:18.58/xfe/off,on,14.7 2006.257.01:37:23.99;clockoff 2006.257.01:37:23.99&clockoff/"gps-fmout=1p 2006.257.01:37:23.99&clockoff/fmout-gps=1p 2006.257.01:37:24.08/fmout-gps/S +4.56E-07 2006.257.01:59:50.00:preob 2006.257.01:59:50.00&preob/onsource 2006.257.01:59:50.14/onsource/TRACKING 2006.257.01:59:50.14:!2006.257.02:00:00 2006.257.02:00:00.00:"tape 2006.257.02:00:00.00:"st=record 2006.257.02:00:00.00:data_valid=on 2006.257.02:00:00.01:midob 2006.257.02:00:00.01&midob/onsource 2006.257.02:00:00.01&midob/wx 2006.257.02:00:00.01&midob/cable 2006.257.02:00:00.01&midob/va 2006.257.02:00:00.01&midob/valo 2006.257.02:00:00.01&midob/vb 2006.257.02:00:00.01&midob/vblo 2006.257.02:00:00.01&midob/vabw 2006.257.02:00:00.01&midob/vbbw 2006.257.02:00:00.01&midob/"form 2006.257.02:00:00.01&midob/xfe 2006.257.02:00:00.01&midob/ifatt 2006.257.02:00:00.01&midob/clockoff 2006.257.02:00:00.01&midob/sy=logmail 2006.257.02:00:00.02&midob/"sy=run setcl adapt & 2006.257.02:00:01.14/onsource/TRACKING 2006.257.02:00:01.14/wx/17.95,1011.9,100 2006.257.02:00:01.35/cable/+6.4867E-03 2006.257.02:00:02.44/va/01,08,usb,yes,32,34 2006.257.02:00:02.44/va/02,07,usb,yes,35,35 2006.257.02:00:02.44/va/03,08,usb,yes,31,33 2006.257.02:00:02.44/va/04,07,usb,yes,36,37 2006.257.02:00:02.44/va/05,04,usb,yes,32,32 2006.257.02:00:02.44/va/06,04,usb,yes,36,35 2006.257.02:00:02.44/va/07,04,usb,yes,37,37 2006.257.02:00:02.44/va/08,04,usb,yes,30,37 2006.257.02:00:02.67/valo/01,524.99,yes,locked 2006.257.02:00:02.67/valo/02,534.99,yes,locked 2006.257.02:00:02.67/valo/03,564.99,yes,locked 2006.257.02:00:02.67/valo/04,624.99,yes,locked 2006.257.02:00:02.67/valo/05,734.99,yes,locked 2006.257.02:00:02.67/valo/06,814.99,yes,locked 2006.257.02:00:02.67/valo/07,864.99,yes,locked 2006.257.02:00:02.67/valo/08,884.99,yes,locked 2006.257.02:00:03.76/vb/01,04,usb,yes,31,29 2006.257.02:00:03.76/vb/02,05,usb,yes,29,29 2006.257.02:00:03.76/vb/03,04,usb,yes,30,33 2006.257.02:00:03.76/vb/04,05,usb,yes,30,29 2006.257.02:00:03.76/vb/05,04,usb,yes,27,29 2006.257.02:00:03.76/vb/06,04,usb,yes,31,28 2006.257.02:00:03.76/vb/07,04,usb,yes,31,31 2006.257.02:00:03.76/vb/08,04,usb,yes,28,32 2006.257.02:00:03.99/vblo/01,629.99,yes,locked 2006.257.02:00:03.99/vblo/02,634.99,yes,locked 2006.257.02:00:03.99/vblo/03,649.99,yes,locked 2006.257.02:00:03.99/vblo/04,679.99,yes,locked 2006.257.02:00:03.99/vblo/05,709.99,yes,locked 2006.257.02:00:03.99/vblo/06,719.99,yes,locked 2006.257.02:00:03.99/vblo/07,734.99,yes,locked 2006.257.02:00:03.99/vblo/08,744.99,yes,locked 2006.257.02:00:04.14/vabw/8 2006.257.02:00:04.29/vbbw/8 2006.257.02:00:04.39/xfe/off,on,15.0 2006.257.02:00:04.76/ifatt/23,28,28,28 2006.257.02:00:05.07/fmout-gps/S +4.52E-07 2006.257.02:00:05.11:!2006.257.02:00:50 2006.257.02:00:50.01:data_valid=off 2006.257.02:00:50.02:"et 2006.257.02:00:50.02:!+3s 2006.257.02:00:53.03:"tape 2006.257.02:00:53.04:postob 2006.257.02:00:53.04&postob/cable 2006.257.02:00:53.04&postob/wx 2006.257.02:00:53.05&postob/clockoff 2006.257.02:00:53.23/cable/+6.4868E-03 2006.257.02:00:53.24/wx/17.90,1011.9,100 2006.257.02:00:53.32/fmout-gps/S +4.52E-07 2006.257.02:00:53.32:scan_name=257-0204,jd0609,40 2006.257.02:00:53.33:source=3c345,164258.81,394837.0,2000.0,cw 2006.257.02:00:54.14#flagr#flagr/antenna,new-source 2006.257.02:00:54.15:checkk5 2006.257.02:00:54.15&checkk5/chk_autoobs=1 2006.257.02:00:54.15&checkk5/chk_autoobs=2 2006.257.02:00:54.16&checkk5/chk_autoobs=3 2006.257.02:00:54.16&checkk5/chk_autoobs=4 2006.257.02:00:54.17&checkk5/chk_obsdata=1 2006.257.02:00:54.17&checkk5/chk_obsdata=2 2006.257.02:00:54.17&checkk5/chk_obsdata=3 2006.257.02:00:54.18&checkk5/chk_obsdata=4 2006.257.02:00:54.18&checkk5/k5log=1 2006.257.02:00:54.18&checkk5/k5log=2 2006.257.02:00:54.19&checkk5/k5log=3 2006.257.02:00:54.19&checkk5/k5log=4 2006.257.02:00:54.19&checkk5/obsinfo 2006.257.02:00:54.69/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:00:55.15/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:00:55.62/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:00:56.03/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:00:56.49/chk_obsdata//k5ts1/T2570200??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:00:56.95/chk_obsdata//k5ts2/T2570200??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:00:57.38/chk_obsdata//k5ts3/T2570200??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:00:57.80/chk_obsdata//k5ts4/T2570200??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:00:58.59/k5log//k5ts1_log_newline 2006.257.02:00:59.53/k5log//k5ts2_log_newline 2006.257.02:01:00.40/k5log//k5ts3_log_newline 2006.257.02:01:01.19/k5log//k5ts4_log_newline 2006.257.02:01:01.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:01:01.25:setupk4=1 2006.257.02:01:01.25$setupk4/echo=on 2006.257.02:01:01.25$setupk4/pcalon 2006.257.02:01:01.25$pcalon/"no phase cal control is implemented here 2006.257.02:01:01.25$setupk4/"tpicd=stop 2006.257.02:01:01.25$setupk4/"rec=synch_on 2006.257.02:01:01.25$setupk4/"rec_mode=128 2006.257.02:01:01.25$setupk4/!* 2006.257.02:01:01.25$setupk4/recpk4 2006.257.02:01:01.25$recpk4/recpatch= 2006.257.02:01:01.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:01:01.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:01:01.25$setupk4/vck44 2006.257.02:01:01.25$vck44/valo=1,524.99 2006.257.02:01:01.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.02:01:01.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.02:01:01.25#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:01.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:01:01.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:01:01.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:01:01.25#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:01:01.25#ibcon#first serial, iclass 11, count 0 2006.257.02:01:01.25#ibcon#enter sib2, iclass 11, count 0 2006.257.02:01:01.25#ibcon#flushed, iclass 11, count 0 2006.257.02:01:01.25#ibcon#about to write, iclass 11, count 0 2006.257.02:01:01.25#ibcon#wrote, iclass 11, count 0 2006.257.02:01:01.25#ibcon#about to read 3, iclass 11, count 0 2006.257.02:01:01.27#ibcon#read 3, iclass 11, count 0 2006.257.02:01:01.27#ibcon#about to read 4, iclass 11, count 0 2006.257.02:01:01.27#ibcon#read 4, iclass 11, count 0 2006.257.02:01:01.27#ibcon#about to read 5, iclass 11, count 0 2006.257.02:01:01.27#ibcon#read 5, iclass 11, count 0 2006.257.02:01:01.27#ibcon#about to read 6, iclass 11, count 0 2006.257.02:01:01.27#ibcon#read 6, iclass 11, count 0 2006.257.02:01:01.27#ibcon#end of sib2, iclass 11, count 0 2006.257.02:01:01.27#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:01:01.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:01:01.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:01:01.27#ibcon#*before write, iclass 11, count 0 2006.257.02:01:01.27#ibcon#enter sib2, iclass 11, count 0 2006.257.02:01:01.27#ibcon#flushed, iclass 11, count 0 2006.257.02:01:01.27#ibcon#about to write, iclass 11, count 0 2006.257.02:01:01.27#ibcon#wrote, iclass 11, count 0 2006.257.02:01:01.27#ibcon#about to read 3, iclass 11, count 0 2006.257.02:01:01.32#ibcon#read 3, iclass 11, count 0 2006.257.02:01:01.32#ibcon#about to read 4, iclass 11, count 0 2006.257.02:01:01.32#ibcon#read 4, iclass 11, count 0 2006.257.02:01:01.32#ibcon#about to read 5, iclass 11, count 0 2006.257.02:01:01.32#ibcon#read 5, iclass 11, count 0 2006.257.02:01:01.32#ibcon#about to read 6, iclass 11, count 0 2006.257.02:01:01.32#ibcon#read 6, iclass 11, count 0 2006.257.02:01:01.32#ibcon#end of sib2, iclass 11, count 0 2006.257.02:01:01.32#ibcon#*after write, iclass 11, count 0 2006.257.02:01:01.32#ibcon#*before return 0, iclass 11, count 0 2006.257.02:01:01.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:01:01.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:01:01.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:01:01.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:01:01.32$vck44/va=1,8 2006.257.02:01:01.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.02:01:01.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.02:01:01.32#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:01.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:01:01.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:01:01.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:01:01.32#ibcon#enter wrdev, iclass 13, count 2 2006.257.02:01:01.32#ibcon#first serial, iclass 13, count 2 2006.257.02:01:01.32#ibcon#enter sib2, iclass 13, count 2 2006.257.02:01:01.32#ibcon#flushed, iclass 13, count 2 2006.257.02:01:01.32#ibcon#about to write, iclass 13, count 2 2006.257.02:01:01.32#ibcon#wrote, iclass 13, count 2 2006.257.02:01:01.32#ibcon#about to read 3, iclass 13, count 2 2006.257.02:01:01.34#ibcon#read 3, iclass 13, count 2 2006.257.02:01:01.34#ibcon#about to read 4, iclass 13, count 2 2006.257.02:01:01.34#ibcon#read 4, iclass 13, count 2 2006.257.02:01:01.34#ibcon#about to read 5, iclass 13, count 2 2006.257.02:01:01.34#ibcon#read 5, iclass 13, count 2 2006.257.02:01:01.34#ibcon#about to read 6, iclass 13, count 2 2006.257.02:01:01.34#ibcon#read 6, iclass 13, count 2 2006.257.02:01:01.34#ibcon#end of sib2, iclass 13, count 2 2006.257.02:01:01.34#ibcon#*mode == 0, iclass 13, count 2 2006.257.02:01:01.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.02:01:01.34#ibcon#[25=AT01-08\r\n] 2006.257.02:01:01.34#ibcon#*before write, iclass 13, count 2 2006.257.02:01:01.34#ibcon#enter sib2, iclass 13, count 2 2006.257.02:01:01.34#ibcon#flushed, iclass 13, count 2 2006.257.02:01:01.34#ibcon#about to write, iclass 13, count 2 2006.257.02:01:01.34#ibcon#wrote, iclass 13, count 2 2006.257.02:01:01.34#ibcon#about to read 3, iclass 13, count 2 2006.257.02:01:01.37#ibcon#read 3, iclass 13, count 2 2006.257.02:01:01.37#ibcon#about to read 4, iclass 13, count 2 2006.257.02:01:01.37#ibcon#read 4, iclass 13, count 2 2006.257.02:01:01.37#ibcon#about to read 5, iclass 13, count 2 2006.257.02:01:01.37#ibcon#read 5, iclass 13, count 2 2006.257.02:01:01.37#ibcon#about to read 6, iclass 13, count 2 2006.257.02:01:01.37#ibcon#read 6, iclass 13, count 2 2006.257.02:01:01.37#ibcon#end of sib2, iclass 13, count 2 2006.257.02:01:01.37#ibcon#*after write, iclass 13, count 2 2006.257.02:01:01.37#ibcon#*before return 0, iclass 13, count 2 2006.257.02:01:01.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:01:01.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:01:01.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.02:01:01.37#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:01.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:01:01.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:01:01.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:01:01.49#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:01:01.49#ibcon#first serial, iclass 13, count 0 2006.257.02:01:01.49#ibcon#enter sib2, iclass 13, count 0 2006.257.02:01:01.49#ibcon#flushed, iclass 13, count 0 2006.257.02:01:01.49#ibcon#about to write, iclass 13, count 0 2006.257.02:01:01.49#ibcon#wrote, iclass 13, count 0 2006.257.02:01:01.49#ibcon#about to read 3, iclass 13, count 0 2006.257.02:01:01.51#ibcon#read 3, iclass 13, count 0 2006.257.02:01:01.51#ibcon#about to read 4, iclass 13, count 0 2006.257.02:01:01.51#ibcon#read 4, iclass 13, count 0 2006.257.02:01:01.51#ibcon#about to read 5, iclass 13, count 0 2006.257.02:01:01.51#ibcon#read 5, iclass 13, count 0 2006.257.02:01:01.51#ibcon#about to read 6, iclass 13, count 0 2006.257.02:01:01.51#ibcon#read 6, iclass 13, count 0 2006.257.02:01:01.51#ibcon#end of sib2, iclass 13, count 0 2006.257.02:01:01.51#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:01:01.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:01:01.51#ibcon#[25=USB\r\n] 2006.257.02:01:01.51#ibcon#*before write, iclass 13, count 0 2006.257.02:01:01.51#ibcon#enter sib2, iclass 13, count 0 2006.257.02:01:01.51#ibcon#flushed, iclass 13, count 0 2006.257.02:01:01.51#ibcon#about to write, iclass 13, count 0 2006.257.02:01:01.51#ibcon#wrote, iclass 13, count 0 2006.257.02:01:01.51#ibcon#about to read 3, iclass 13, count 0 2006.257.02:01:01.54#ibcon#read 3, iclass 13, count 0 2006.257.02:01:01.54#ibcon#about to read 4, iclass 13, count 0 2006.257.02:01:01.54#ibcon#read 4, iclass 13, count 0 2006.257.02:01:01.54#ibcon#about to read 5, iclass 13, count 0 2006.257.02:01:01.54#ibcon#read 5, iclass 13, count 0 2006.257.02:01:01.54#ibcon#about to read 6, iclass 13, count 0 2006.257.02:01:01.54#ibcon#read 6, iclass 13, count 0 2006.257.02:01:01.54#ibcon#end of sib2, iclass 13, count 0 2006.257.02:01:01.54#ibcon#*after write, iclass 13, count 0 2006.257.02:01:01.54#ibcon#*before return 0, iclass 13, count 0 2006.257.02:01:01.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:01:01.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:01:01.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:01:01.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:01:01.54$vck44/valo=2,534.99 2006.257.02:01:01.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.02:01:01.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.02:01:01.54#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:01.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:01.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:01.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:01.54#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:01:01.54#ibcon#first serial, iclass 15, count 0 2006.257.02:01:01.54#ibcon#enter sib2, iclass 15, count 0 2006.257.02:01:01.54#ibcon#flushed, iclass 15, count 0 2006.257.02:01:01.54#ibcon#about to write, iclass 15, count 0 2006.257.02:01:01.54#ibcon#wrote, iclass 15, count 0 2006.257.02:01:01.54#ibcon#about to read 3, iclass 15, count 0 2006.257.02:01:01.57#ibcon#read 3, iclass 15, count 0 2006.257.02:01:01.57#ibcon#about to read 4, iclass 15, count 0 2006.257.02:01:01.57#ibcon#read 4, iclass 15, count 0 2006.257.02:01:01.57#ibcon#about to read 5, iclass 15, count 0 2006.257.02:01:01.57#ibcon#read 5, iclass 15, count 0 2006.257.02:01:01.57#ibcon#about to read 6, iclass 15, count 0 2006.257.02:01:01.57#ibcon#read 6, iclass 15, count 0 2006.257.02:01:01.57#ibcon#end of sib2, iclass 15, count 0 2006.257.02:01:01.57#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:01:01.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:01:01.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:01:01.57#ibcon#*before write, iclass 15, count 0 2006.257.02:01:01.57#ibcon#enter sib2, iclass 15, count 0 2006.257.02:01:01.57#ibcon#flushed, iclass 15, count 0 2006.257.02:01:01.57#ibcon#about to write, iclass 15, count 0 2006.257.02:01:01.57#ibcon#wrote, iclass 15, count 0 2006.257.02:01:01.57#ibcon#about to read 3, iclass 15, count 0 2006.257.02:01:01.61#ibcon#read 3, iclass 15, count 0 2006.257.02:01:01.61#ibcon#about to read 4, iclass 15, count 0 2006.257.02:01:01.61#ibcon#read 4, iclass 15, count 0 2006.257.02:01:01.61#ibcon#about to read 5, iclass 15, count 0 2006.257.02:01:01.61#ibcon#read 5, iclass 15, count 0 2006.257.02:01:01.61#ibcon#about to read 6, iclass 15, count 0 2006.257.02:01:01.61#ibcon#read 6, iclass 15, count 0 2006.257.02:01:01.61#ibcon#end of sib2, iclass 15, count 0 2006.257.02:01:01.61#ibcon#*after write, iclass 15, count 0 2006.257.02:01:01.61#ibcon#*before return 0, iclass 15, count 0 2006.257.02:01:01.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:01.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:01.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:01:01.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:01:01.61$vck44/va=2,7 2006.257.02:01:01.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.02:01:01.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.02:01:01.61#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:01.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:01.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:01.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:01.66#ibcon#enter wrdev, iclass 17, count 2 2006.257.02:01:01.66#ibcon#first serial, iclass 17, count 2 2006.257.02:01:01.66#ibcon#enter sib2, iclass 17, count 2 2006.257.02:01:01.66#ibcon#flushed, iclass 17, count 2 2006.257.02:01:01.66#ibcon#about to write, iclass 17, count 2 2006.257.02:01:01.66#ibcon#wrote, iclass 17, count 2 2006.257.02:01:01.66#ibcon#about to read 3, iclass 17, count 2 2006.257.02:01:01.68#ibcon#read 3, iclass 17, count 2 2006.257.02:01:01.68#ibcon#about to read 4, iclass 17, count 2 2006.257.02:01:01.68#ibcon#read 4, iclass 17, count 2 2006.257.02:01:01.68#ibcon#about to read 5, iclass 17, count 2 2006.257.02:01:01.68#ibcon#read 5, iclass 17, count 2 2006.257.02:01:01.68#ibcon#about to read 6, iclass 17, count 2 2006.257.02:01:01.68#ibcon#read 6, iclass 17, count 2 2006.257.02:01:01.68#ibcon#end of sib2, iclass 17, count 2 2006.257.02:01:01.68#ibcon#*mode == 0, iclass 17, count 2 2006.257.02:01:01.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.02:01:01.68#ibcon#[25=AT02-07\r\n] 2006.257.02:01:01.68#ibcon#*before write, iclass 17, count 2 2006.257.02:01:01.68#ibcon#enter sib2, iclass 17, count 2 2006.257.02:01:01.68#ibcon#flushed, iclass 17, count 2 2006.257.02:01:01.68#ibcon#about to write, iclass 17, count 2 2006.257.02:01:01.68#ibcon#wrote, iclass 17, count 2 2006.257.02:01:01.68#ibcon#about to read 3, iclass 17, count 2 2006.257.02:01:01.71#ibcon#read 3, iclass 17, count 2 2006.257.02:01:01.71#ibcon#about to read 4, iclass 17, count 2 2006.257.02:01:01.71#ibcon#read 4, iclass 17, count 2 2006.257.02:01:01.71#ibcon#about to read 5, iclass 17, count 2 2006.257.02:01:01.71#ibcon#read 5, iclass 17, count 2 2006.257.02:01:01.71#ibcon#about to read 6, iclass 17, count 2 2006.257.02:01:01.71#ibcon#read 6, iclass 17, count 2 2006.257.02:01:01.71#ibcon#end of sib2, iclass 17, count 2 2006.257.02:01:01.71#ibcon#*after write, iclass 17, count 2 2006.257.02:01:01.71#ibcon#*before return 0, iclass 17, count 2 2006.257.02:01:01.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:01.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:01.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.02:01:01.71#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:01.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:01.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:01.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:01.83#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:01:01.83#ibcon#first serial, iclass 17, count 0 2006.257.02:01:01.83#ibcon#enter sib2, iclass 17, count 0 2006.257.02:01:01.83#ibcon#flushed, iclass 17, count 0 2006.257.02:01:01.83#ibcon#about to write, iclass 17, count 0 2006.257.02:01:01.83#ibcon#wrote, iclass 17, count 0 2006.257.02:01:01.83#ibcon#about to read 3, iclass 17, count 0 2006.257.02:01:01.85#ibcon#read 3, iclass 17, count 0 2006.257.02:01:01.85#ibcon#about to read 4, iclass 17, count 0 2006.257.02:01:01.85#ibcon#read 4, iclass 17, count 0 2006.257.02:01:01.85#ibcon#about to read 5, iclass 17, count 0 2006.257.02:01:01.85#ibcon#read 5, iclass 17, count 0 2006.257.02:01:01.85#ibcon#about to read 6, iclass 17, count 0 2006.257.02:01:01.85#ibcon#read 6, iclass 17, count 0 2006.257.02:01:01.85#ibcon#end of sib2, iclass 17, count 0 2006.257.02:01:01.85#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:01:01.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:01:01.85#ibcon#[25=USB\r\n] 2006.257.02:01:01.85#ibcon#*before write, iclass 17, count 0 2006.257.02:01:01.85#ibcon#enter sib2, iclass 17, count 0 2006.257.02:01:01.85#ibcon#flushed, iclass 17, count 0 2006.257.02:01:01.85#ibcon#about to write, iclass 17, count 0 2006.257.02:01:01.85#ibcon#wrote, iclass 17, count 0 2006.257.02:01:01.85#ibcon#about to read 3, iclass 17, count 0 2006.257.02:01:01.88#ibcon#read 3, iclass 17, count 0 2006.257.02:01:01.88#ibcon#about to read 4, iclass 17, count 0 2006.257.02:01:01.88#ibcon#read 4, iclass 17, count 0 2006.257.02:01:01.88#ibcon#about to read 5, iclass 17, count 0 2006.257.02:01:01.88#ibcon#read 5, iclass 17, count 0 2006.257.02:01:01.88#ibcon#about to read 6, iclass 17, count 0 2006.257.02:01:01.88#ibcon#read 6, iclass 17, count 0 2006.257.02:01:01.88#ibcon#end of sib2, iclass 17, count 0 2006.257.02:01:01.88#ibcon#*after write, iclass 17, count 0 2006.257.02:01:01.88#ibcon#*before return 0, iclass 17, count 0 2006.257.02:01:01.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:01.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:01.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:01:01.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:01:01.88$vck44/valo=3,564.99 2006.257.02:01:01.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.02:01:01.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.02:01:01.88#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:01.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:01.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:01.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:01.88#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:01:01.88#ibcon#first serial, iclass 19, count 0 2006.257.02:01:01.88#ibcon#enter sib2, iclass 19, count 0 2006.257.02:01:01.88#ibcon#flushed, iclass 19, count 0 2006.257.02:01:01.88#ibcon#about to write, iclass 19, count 0 2006.257.02:01:01.88#ibcon#wrote, iclass 19, count 0 2006.257.02:01:01.88#ibcon#about to read 3, iclass 19, count 0 2006.257.02:01:01.91#ibcon#read 3, iclass 19, count 0 2006.257.02:01:01.91#ibcon#about to read 4, iclass 19, count 0 2006.257.02:01:01.91#ibcon#read 4, iclass 19, count 0 2006.257.02:01:01.91#ibcon#about to read 5, iclass 19, count 0 2006.257.02:01:01.91#ibcon#read 5, iclass 19, count 0 2006.257.02:01:01.91#ibcon#about to read 6, iclass 19, count 0 2006.257.02:01:01.91#ibcon#read 6, iclass 19, count 0 2006.257.02:01:01.91#ibcon#end of sib2, iclass 19, count 0 2006.257.02:01:01.91#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:01:01.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:01:01.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:01:01.91#ibcon#*before write, iclass 19, count 0 2006.257.02:01:01.91#ibcon#enter sib2, iclass 19, count 0 2006.257.02:01:01.91#ibcon#flushed, iclass 19, count 0 2006.257.02:01:01.91#ibcon#about to write, iclass 19, count 0 2006.257.02:01:01.91#ibcon#wrote, iclass 19, count 0 2006.257.02:01:01.91#ibcon#about to read 3, iclass 19, count 0 2006.257.02:01:01.95#ibcon#read 3, iclass 19, count 0 2006.257.02:01:01.95#ibcon#about to read 4, iclass 19, count 0 2006.257.02:01:01.95#ibcon#read 4, iclass 19, count 0 2006.257.02:01:01.95#ibcon#about to read 5, iclass 19, count 0 2006.257.02:01:01.95#ibcon#read 5, iclass 19, count 0 2006.257.02:01:01.95#ibcon#about to read 6, iclass 19, count 0 2006.257.02:01:01.95#ibcon#read 6, iclass 19, count 0 2006.257.02:01:01.95#ibcon#end of sib2, iclass 19, count 0 2006.257.02:01:01.95#ibcon#*after write, iclass 19, count 0 2006.257.02:01:01.95#ibcon#*before return 0, iclass 19, count 0 2006.257.02:01:01.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:01.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:01.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:01:01.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:01:01.95$vck44/va=3,8 2006.257.02:01:01.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.02:01:01.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.02:01:01.95#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:01.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:02.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:02.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:02.00#ibcon#enter wrdev, iclass 21, count 2 2006.257.02:01:02.00#ibcon#first serial, iclass 21, count 2 2006.257.02:01:02.00#ibcon#enter sib2, iclass 21, count 2 2006.257.02:01:02.00#ibcon#flushed, iclass 21, count 2 2006.257.02:01:02.00#ibcon#about to write, iclass 21, count 2 2006.257.02:01:02.00#ibcon#wrote, iclass 21, count 2 2006.257.02:01:02.00#ibcon#about to read 3, iclass 21, count 2 2006.257.02:01:02.02#ibcon#read 3, iclass 21, count 2 2006.257.02:01:02.02#ibcon#about to read 4, iclass 21, count 2 2006.257.02:01:02.02#ibcon#read 4, iclass 21, count 2 2006.257.02:01:02.02#ibcon#about to read 5, iclass 21, count 2 2006.257.02:01:02.02#ibcon#read 5, iclass 21, count 2 2006.257.02:01:02.02#ibcon#about to read 6, iclass 21, count 2 2006.257.02:01:02.02#ibcon#read 6, iclass 21, count 2 2006.257.02:01:02.02#ibcon#end of sib2, iclass 21, count 2 2006.257.02:01:02.02#ibcon#*mode == 0, iclass 21, count 2 2006.257.02:01:02.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.02:01:02.02#ibcon#[25=AT03-08\r\n] 2006.257.02:01:02.02#ibcon#*before write, iclass 21, count 2 2006.257.02:01:02.02#ibcon#enter sib2, iclass 21, count 2 2006.257.02:01:02.02#ibcon#flushed, iclass 21, count 2 2006.257.02:01:02.02#ibcon#about to write, iclass 21, count 2 2006.257.02:01:02.02#ibcon#wrote, iclass 21, count 2 2006.257.02:01:02.02#ibcon#about to read 3, iclass 21, count 2 2006.257.02:01:02.05#ibcon#read 3, iclass 21, count 2 2006.257.02:01:02.05#ibcon#about to read 4, iclass 21, count 2 2006.257.02:01:02.05#ibcon#read 4, iclass 21, count 2 2006.257.02:01:02.05#ibcon#about to read 5, iclass 21, count 2 2006.257.02:01:02.05#ibcon#read 5, iclass 21, count 2 2006.257.02:01:02.05#ibcon#about to read 6, iclass 21, count 2 2006.257.02:01:02.05#ibcon#read 6, iclass 21, count 2 2006.257.02:01:02.05#ibcon#end of sib2, iclass 21, count 2 2006.257.02:01:02.05#ibcon#*after write, iclass 21, count 2 2006.257.02:01:02.05#ibcon#*before return 0, iclass 21, count 2 2006.257.02:01:02.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:02.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:02.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.02:01:02.05#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:02.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:02.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:02.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:02.17#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:01:02.17#ibcon#first serial, iclass 21, count 0 2006.257.02:01:02.17#ibcon#enter sib2, iclass 21, count 0 2006.257.02:01:02.17#ibcon#flushed, iclass 21, count 0 2006.257.02:01:02.17#ibcon#about to write, iclass 21, count 0 2006.257.02:01:02.17#ibcon#wrote, iclass 21, count 0 2006.257.02:01:02.17#ibcon#about to read 3, iclass 21, count 0 2006.257.02:01:02.19#ibcon#read 3, iclass 21, count 0 2006.257.02:01:02.19#ibcon#about to read 4, iclass 21, count 0 2006.257.02:01:02.19#ibcon#read 4, iclass 21, count 0 2006.257.02:01:02.19#ibcon#about to read 5, iclass 21, count 0 2006.257.02:01:02.19#ibcon#read 5, iclass 21, count 0 2006.257.02:01:02.19#ibcon#about to read 6, iclass 21, count 0 2006.257.02:01:02.19#ibcon#read 6, iclass 21, count 0 2006.257.02:01:02.19#ibcon#end of sib2, iclass 21, count 0 2006.257.02:01:02.19#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:01:02.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:01:02.19#ibcon#[25=USB\r\n] 2006.257.02:01:02.19#ibcon#*before write, iclass 21, count 0 2006.257.02:01:02.19#ibcon#enter sib2, iclass 21, count 0 2006.257.02:01:02.19#ibcon#flushed, iclass 21, count 0 2006.257.02:01:02.19#ibcon#about to write, iclass 21, count 0 2006.257.02:01:02.19#ibcon#wrote, iclass 21, count 0 2006.257.02:01:02.19#ibcon#about to read 3, iclass 21, count 0 2006.257.02:01:02.22#ibcon#read 3, iclass 21, count 0 2006.257.02:01:02.22#ibcon#about to read 4, iclass 21, count 0 2006.257.02:01:02.22#ibcon#read 4, iclass 21, count 0 2006.257.02:01:02.22#ibcon#about to read 5, iclass 21, count 0 2006.257.02:01:02.22#ibcon#read 5, iclass 21, count 0 2006.257.02:01:02.22#ibcon#about to read 6, iclass 21, count 0 2006.257.02:01:02.22#ibcon#read 6, iclass 21, count 0 2006.257.02:01:02.22#ibcon#end of sib2, iclass 21, count 0 2006.257.02:01:02.22#ibcon#*after write, iclass 21, count 0 2006.257.02:01:02.22#ibcon#*before return 0, iclass 21, count 0 2006.257.02:01:02.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:02.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:02.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:01:02.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:01:02.22$vck44/valo=4,624.99 2006.257.02:01:02.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.02:01:02.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.02:01:02.22#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:02.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:02.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:02.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:02.22#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:01:02.22#ibcon#first serial, iclass 23, count 0 2006.257.02:01:02.22#ibcon#enter sib2, iclass 23, count 0 2006.257.02:01:02.22#ibcon#flushed, iclass 23, count 0 2006.257.02:01:02.22#ibcon#about to write, iclass 23, count 0 2006.257.02:01:02.22#ibcon#wrote, iclass 23, count 0 2006.257.02:01:02.22#ibcon#about to read 3, iclass 23, count 0 2006.257.02:01:02.24#ibcon#read 3, iclass 23, count 0 2006.257.02:01:02.24#ibcon#about to read 4, iclass 23, count 0 2006.257.02:01:02.24#ibcon#read 4, iclass 23, count 0 2006.257.02:01:02.24#ibcon#about to read 5, iclass 23, count 0 2006.257.02:01:02.24#ibcon#read 5, iclass 23, count 0 2006.257.02:01:02.24#ibcon#about to read 6, iclass 23, count 0 2006.257.02:01:02.24#ibcon#read 6, iclass 23, count 0 2006.257.02:01:02.24#ibcon#end of sib2, iclass 23, count 0 2006.257.02:01:02.24#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:01:02.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:01:02.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:01:02.24#ibcon#*before write, iclass 23, count 0 2006.257.02:01:02.24#ibcon#enter sib2, iclass 23, count 0 2006.257.02:01:02.24#ibcon#flushed, iclass 23, count 0 2006.257.02:01:02.24#ibcon#about to write, iclass 23, count 0 2006.257.02:01:02.24#ibcon#wrote, iclass 23, count 0 2006.257.02:01:02.24#ibcon#about to read 3, iclass 23, count 0 2006.257.02:01:02.28#ibcon#read 3, iclass 23, count 0 2006.257.02:01:02.28#ibcon#about to read 4, iclass 23, count 0 2006.257.02:01:02.28#ibcon#read 4, iclass 23, count 0 2006.257.02:01:02.28#ibcon#about to read 5, iclass 23, count 0 2006.257.02:01:02.28#ibcon#read 5, iclass 23, count 0 2006.257.02:01:02.28#ibcon#about to read 6, iclass 23, count 0 2006.257.02:01:02.28#ibcon#read 6, iclass 23, count 0 2006.257.02:01:02.28#ibcon#end of sib2, iclass 23, count 0 2006.257.02:01:02.28#ibcon#*after write, iclass 23, count 0 2006.257.02:01:02.28#ibcon#*before return 0, iclass 23, count 0 2006.257.02:01:02.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:02.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:02.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:01:02.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:01:02.28$vck44/va=4,7 2006.257.02:01:02.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.02:01:02.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.02:01:02.28#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:02.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:02.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:02.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:02.34#ibcon#enter wrdev, iclass 25, count 2 2006.257.02:01:02.34#ibcon#first serial, iclass 25, count 2 2006.257.02:01:02.34#ibcon#enter sib2, iclass 25, count 2 2006.257.02:01:02.34#ibcon#flushed, iclass 25, count 2 2006.257.02:01:02.34#ibcon#about to write, iclass 25, count 2 2006.257.02:01:02.34#ibcon#wrote, iclass 25, count 2 2006.257.02:01:02.34#ibcon#about to read 3, iclass 25, count 2 2006.257.02:01:02.36#ibcon#read 3, iclass 25, count 2 2006.257.02:01:02.36#ibcon#about to read 4, iclass 25, count 2 2006.257.02:01:02.36#ibcon#read 4, iclass 25, count 2 2006.257.02:01:02.36#ibcon#about to read 5, iclass 25, count 2 2006.257.02:01:02.36#ibcon#read 5, iclass 25, count 2 2006.257.02:01:02.36#ibcon#about to read 6, iclass 25, count 2 2006.257.02:01:02.36#ibcon#read 6, iclass 25, count 2 2006.257.02:01:02.36#ibcon#end of sib2, iclass 25, count 2 2006.257.02:01:02.36#ibcon#*mode == 0, iclass 25, count 2 2006.257.02:01:02.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.02:01:02.36#ibcon#[25=AT04-07\r\n] 2006.257.02:01:02.36#ibcon#*before write, iclass 25, count 2 2006.257.02:01:02.36#ibcon#enter sib2, iclass 25, count 2 2006.257.02:01:02.36#ibcon#flushed, iclass 25, count 2 2006.257.02:01:02.36#ibcon#about to write, iclass 25, count 2 2006.257.02:01:02.36#ibcon#wrote, iclass 25, count 2 2006.257.02:01:02.36#ibcon#about to read 3, iclass 25, count 2 2006.257.02:01:02.39#ibcon#read 3, iclass 25, count 2 2006.257.02:01:02.39#ibcon#about to read 4, iclass 25, count 2 2006.257.02:01:02.39#ibcon#read 4, iclass 25, count 2 2006.257.02:01:02.39#ibcon#about to read 5, iclass 25, count 2 2006.257.02:01:02.39#ibcon#read 5, iclass 25, count 2 2006.257.02:01:02.39#ibcon#about to read 6, iclass 25, count 2 2006.257.02:01:02.39#ibcon#read 6, iclass 25, count 2 2006.257.02:01:02.39#ibcon#end of sib2, iclass 25, count 2 2006.257.02:01:02.39#ibcon#*after write, iclass 25, count 2 2006.257.02:01:02.39#ibcon#*before return 0, iclass 25, count 2 2006.257.02:01:02.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:02.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:02.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.02:01:02.39#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:02.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:02.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:02.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:02.51#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:01:02.51#ibcon#first serial, iclass 25, count 0 2006.257.02:01:02.51#ibcon#enter sib2, iclass 25, count 0 2006.257.02:01:02.51#ibcon#flushed, iclass 25, count 0 2006.257.02:01:02.51#ibcon#about to write, iclass 25, count 0 2006.257.02:01:02.51#ibcon#wrote, iclass 25, count 0 2006.257.02:01:02.51#ibcon#about to read 3, iclass 25, count 0 2006.257.02:01:02.53#ibcon#read 3, iclass 25, count 0 2006.257.02:01:02.53#ibcon#about to read 4, iclass 25, count 0 2006.257.02:01:02.53#ibcon#read 4, iclass 25, count 0 2006.257.02:01:02.53#ibcon#about to read 5, iclass 25, count 0 2006.257.02:01:02.53#ibcon#read 5, iclass 25, count 0 2006.257.02:01:02.53#ibcon#about to read 6, iclass 25, count 0 2006.257.02:01:02.53#ibcon#read 6, iclass 25, count 0 2006.257.02:01:02.53#ibcon#end of sib2, iclass 25, count 0 2006.257.02:01:02.53#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:01:02.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:01:02.53#ibcon#[25=USB\r\n] 2006.257.02:01:02.53#ibcon#*before write, iclass 25, count 0 2006.257.02:01:02.53#ibcon#enter sib2, iclass 25, count 0 2006.257.02:01:02.53#ibcon#flushed, iclass 25, count 0 2006.257.02:01:02.53#ibcon#about to write, iclass 25, count 0 2006.257.02:01:02.53#ibcon#wrote, iclass 25, count 0 2006.257.02:01:02.53#ibcon#about to read 3, iclass 25, count 0 2006.257.02:01:02.56#ibcon#read 3, iclass 25, count 0 2006.257.02:01:02.56#ibcon#about to read 4, iclass 25, count 0 2006.257.02:01:02.56#ibcon#read 4, iclass 25, count 0 2006.257.02:01:02.56#ibcon#about to read 5, iclass 25, count 0 2006.257.02:01:02.56#ibcon#read 5, iclass 25, count 0 2006.257.02:01:02.56#ibcon#about to read 6, iclass 25, count 0 2006.257.02:01:02.56#ibcon#read 6, iclass 25, count 0 2006.257.02:01:02.56#ibcon#end of sib2, iclass 25, count 0 2006.257.02:01:02.56#ibcon#*after write, iclass 25, count 0 2006.257.02:01:02.56#ibcon#*before return 0, iclass 25, count 0 2006.257.02:01:02.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:02.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:02.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:01:02.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:01:02.56$vck44/valo=5,734.99 2006.257.02:01:02.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.02:01:02.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.02:01:02.56#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:02.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:02.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:02.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:02.56#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:01:02.56#ibcon#first serial, iclass 27, count 0 2006.257.02:01:02.56#ibcon#enter sib2, iclass 27, count 0 2006.257.02:01:02.56#ibcon#flushed, iclass 27, count 0 2006.257.02:01:02.56#ibcon#about to write, iclass 27, count 0 2006.257.02:01:02.56#ibcon#wrote, iclass 27, count 0 2006.257.02:01:02.56#ibcon#about to read 3, iclass 27, count 0 2006.257.02:01:02.58#ibcon#read 3, iclass 27, count 0 2006.257.02:01:02.58#ibcon#about to read 4, iclass 27, count 0 2006.257.02:01:02.58#ibcon#read 4, iclass 27, count 0 2006.257.02:01:02.58#ibcon#about to read 5, iclass 27, count 0 2006.257.02:01:02.58#ibcon#read 5, iclass 27, count 0 2006.257.02:01:02.58#ibcon#about to read 6, iclass 27, count 0 2006.257.02:01:02.58#ibcon#read 6, iclass 27, count 0 2006.257.02:01:02.58#ibcon#end of sib2, iclass 27, count 0 2006.257.02:01:02.58#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:01:02.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:01:02.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:01:02.58#ibcon#*before write, iclass 27, count 0 2006.257.02:01:02.58#ibcon#enter sib2, iclass 27, count 0 2006.257.02:01:02.58#ibcon#flushed, iclass 27, count 0 2006.257.02:01:02.58#ibcon#about to write, iclass 27, count 0 2006.257.02:01:02.58#ibcon#wrote, iclass 27, count 0 2006.257.02:01:02.58#ibcon#about to read 3, iclass 27, count 0 2006.257.02:01:02.62#ibcon#read 3, iclass 27, count 0 2006.257.02:01:02.62#ibcon#about to read 4, iclass 27, count 0 2006.257.02:01:02.62#ibcon#read 4, iclass 27, count 0 2006.257.02:01:02.62#ibcon#about to read 5, iclass 27, count 0 2006.257.02:01:02.62#ibcon#read 5, iclass 27, count 0 2006.257.02:01:02.62#ibcon#about to read 6, iclass 27, count 0 2006.257.02:01:02.62#ibcon#read 6, iclass 27, count 0 2006.257.02:01:02.62#ibcon#end of sib2, iclass 27, count 0 2006.257.02:01:02.62#ibcon#*after write, iclass 27, count 0 2006.257.02:01:02.62#ibcon#*before return 0, iclass 27, count 0 2006.257.02:01:02.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:02.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:02.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:01:02.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:01:02.62$vck44/va=5,4 2006.257.02:01:02.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.02:01:02.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.02:01:02.62#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:02.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:02.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:02.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:02.68#ibcon#enter wrdev, iclass 29, count 2 2006.257.02:01:02.68#ibcon#first serial, iclass 29, count 2 2006.257.02:01:02.68#ibcon#enter sib2, iclass 29, count 2 2006.257.02:01:02.68#ibcon#flushed, iclass 29, count 2 2006.257.02:01:02.68#ibcon#about to write, iclass 29, count 2 2006.257.02:01:02.68#ibcon#wrote, iclass 29, count 2 2006.257.02:01:02.68#ibcon#about to read 3, iclass 29, count 2 2006.257.02:01:02.70#ibcon#read 3, iclass 29, count 2 2006.257.02:01:02.70#ibcon#about to read 4, iclass 29, count 2 2006.257.02:01:02.70#ibcon#read 4, iclass 29, count 2 2006.257.02:01:02.70#ibcon#about to read 5, iclass 29, count 2 2006.257.02:01:02.70#ibcon#read 5, iclass 29, count 2 2006.257.02:01:02.70#ibcon#about to read 6, iclass 29, count 2 2006.257.02:01:02.70#ibcon#read 6, iclass 29, count 2 2006.257.02:01:02.70#ibcon#end of sib2, iclass 29, count 2 2006.257.02:01:02.70#ibcon#*mode == 0, iclass 29, count 2 2006.257.02:01:02.70#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.02:01:02.70#ibcon#[25=AT05-04\r\n] 2006.257.02:01:02.70#ibcon#*before write, iclass 29, count 2 2006.257.02:01:02.70#ibcon#enter sib2, iclass 29, count 2 2006.257.02:01:02.70#ibcon#flushed, iclass 29, count 2 2006.257.02:01:02.70#ibcon#about to write, iclass 29, count 2 2006.257.02:01:02.70#ibcon#wrote, iclass 29, count 2 2006.257.02:01:02.70#ibcon#about to read 3, iclass 29, count 2 2006.257.02:01:02.73#ibcon#read 3, iclass 29, count 2 2006.257.02:01:02.73#ibcon#about to read 4, iclass 29, count 2 2006.257.02:01:02.73#ibcon#read 4, iclass 29, count 2 2006.257.02:01:02.73#ibcon#about to read 5, iclass 29, count 2 2006.257.02:01:02.73#ibcon#read 5, iclass 29, count 2 2006.257.02:01:02.73#ibcon#about to read 6, iclass 29, count 2 2006.257.02:01:02.73#ibcon#read 6, iclass 29, count 2 2006.257.02:01:02.73#ibcon#end of sib2, iclass 29, count 2 2006.257.02:01:02.73#ibcon#*after write, iclass 29, count 2 2006.257.02:01:02.73#ibcon#*before return 0, iclass 29, count 2 2006.257.02:01:02.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:02.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:02.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.02:01:02.73#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:02.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:02.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:02.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:02.85#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:01:02.85#ibcon#first serial, iclass 29, count 0 2006.257.02:01:02.85#ibcon#enter sib2, iclass 29, count 0 2006.257.02:01:02.85#ibcon#flushed, iclass 29, count 0 2006.257.02:01:02.85#ibcon#about to write, iclass 29, count 0 2006.257.02:01:02.85#ibcon#wrote, iclass 29, count 0 2006.257.02:01:02.85#ibcon#about to read 3, iclass 29, count 0 2006.257.02:01:02.87#ibcon#read 3, iclass 29, count 0 2006.257.02:01:02.87#ibcon#about to read 4, iclass 29, count 0 2006.257.02:01:02.87#ibcon#read 4, iclass 29, count 0 2006.257.02:01:02.87#ibcon#about to read 5, iclass 29, count 0 2006.257.02:01:02.87#ibcon#read 5, iclass 29, count 0 2006.257.02:01:02.87#ibcon#about to read 6, iclass 29, count 0 2006.257.02:01:02.87#ibcon#read 6, iclass 29, count 0 2006.257.02:01:02.87#ibcon#end of sib2, iclass 29, count 0 2006.257.02:01:02.87#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:01:02.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:01:02.87#ibcon#[25=USB\r\n] 2006.257.02:01:02.87#ibcon#*before write, iclass 29, count 0 2006.257.02:01:02.87#ibcon#enter sib2, iclass 29, count 0 2006.257.02:01:02.87#ibcon#flushed, iclass 29, count 0 2006.257.02:01:02.87#ibcon#about to write, iclass 29, count 0 2006.257.02:01:02.87#ibcon#wrote, iclass 29, count 0 2006.257.02:01:02.87#ibcon#about to read 3, iclass 29, count 0 2006.257.02:01:02.90#ibcon#read 3, iclass 29, count 0 2006.257.02:01:02.90#ibcon#about to read 4, iclass 29, count 0 2006.257.02:01:02.90#ibcon#read 4, iclass 29, count 0 2006.257.02:01:02.90#ibcon#about to read 5, iclass 29, count 0 2006.257.02:01:02.90#ibcon#read 5, iclass 29, count 0 2006.257.02:01:02.90#ibcon#about to read 6, iclass 29, count 0 2006.257.02:01:02.90#ibcon#read 6, iclass 29, count 0 2006.257.02:01:02.90#ibcon#end of sib2, iclass 29, count 0 2006.257.02:01:02.90#ibcon#*after write, iclass 29, count 0 2006.257.02:01:02.90#ibcon#*before return 0, iclass 29, count 0 2006.257.02:01:02.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:02.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:02.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:01:02.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:01:02.90$vck44/valo=6,814.99 2006.257.02:01:02.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.02:01:02.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.02:01:02.90#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:02.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:02.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:02.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:02.90#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:01:02.90#ibcon#first serial, iclass 31, count 0 2006.257.02:01:02.90#ibcon#enter sib2, iclass 31, count 0 2006.257.02:01:02.90#ibcon#flushed, iclass 31, count 0 2006.257.02:01:02.90#ibcon#about to write, iclass 31, count 0 2006.257.02:01:02.90#ibcon#wrote, iclass 31, count 0 2006.257.02:01:02.90#ibcon#about to read 3, iclass 31, count 0 2006.257.02:01:02.92#ibcon#read 3, iclass 31, count 0 2006.257.02:01:02.92#ibcon#about to read 4, iclass 31, count 0 2006.257.02:01:02.92#ibcon#read 4, iclass 31, count 0 2006.257.02:01:02.92#ibcon#about to read 5, iclass 31, count 0 2006.257.02:01:02.92#ibcon#read 5, iclass 31, count 0 2006.257.02:01:02.92#ibcon#about to read 6, iclass 31, count 0 2006.257.02:01:02.92#ibcon#read 6, iclass 31, count 0 2006.257.02:01:02.92#ibcon#end of sib2, iclass 31, count 0 2006.257.02:01:02.92#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:01:02.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:01:02.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:01:02.92#ibcon#*before write, iclass 31, count 0 2006.257.02:01:02.92#ibcon#enter sib2, iclass 31, count 0 2006.257.02:01:02.92#ibcon#flushed, iclass 31, count 0 2006.257.02:01:02.92#ibcon#about to write, iclass 31, count 0 2006.257.02:01:02.92#ibcon#wrote, iclass 31, count 0 2006.257.02:01:02.92#ibcon#about to read 3, iclass 31, count 0 2006.257.02:01:02.96#ibcon#read 3, iclass 31, count 0 2006.257.02:01:02.96#ibcon#about to read 4, iclass 31, count 0 2006.257.02:01:02.96#ibcon#read 4, iclass 31, count 0 2006.257.02:01:02.96#ibcon#about to read 5, iclass 31, count 0 2006.257.02:01:02.96#ibcon#read 5, iclass 31, count 0 2006.257.02:01:02.96#ibcon#about to read 6, iclass 31, count 0 2006.257.02:01:02.96#ibcon#read 6, iclass 31, count 0 2006.257.02:01:02.96#ibcon#end of sib2, iclass 31, count 0 2006.257.02:01:02.96#ibcon#*after write, iclass 31, count 0 2006.257.02:01:02.96#ibcon#*before return 0, iclass 31, count 0 2006.257.02:01:02.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:02.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:02.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:01:02.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:01:02.96$vck44/va=6,4 2006.257.02:01:02.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.02:01:02.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.02:01:02.96#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:02.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:03.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:03.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:03.02#ibcon#enter wrdev, iclass 33, count 2 2006.257.02:01:03.02#ibcon#first serial, iclass 33, count 2 2006.257.02:01:03.02#ibcon#enter sib2, iclass 33, count 2 2006.257.02:01:03.02#ibcon#flushed, iclass 33, count 2 2006.257.02:01:03.02#ibcon#about to write, iclass 33, count 2 2006.257.02:01:03.02#ibcon#wrote, iclass 33, count 2 2006.257.02:01:03.02#ibcon#about to read 3, iclass 33, count 2 2006.257.02:01:03.04#ibcon#read 3, iclass 33, count 2 2006.257.02:01:03.04#ibcon#about to read 4, iclass 33, count 2 2006.257.02:01:03.04#ibcon#read 4, iclass 33, count 2 2006.257.02:01:03.04#ibcon#about to read 5, iclass 33, count 2 2006.257.02:01:03.04#ibcon#read 5, iclass 33, count 2 2006.257.02:01:03.04#ibcon#about to read 6, iclass 33, count 2 2006.257.02:01:03.04#ibcon#read 6, iclass 33, count 2 2006.257.02:01:03.04#ibcon#end of sib2, iclass 33, count 2 2006.257.02:01:03.04#ibcon#*mode == 0, iclass 33, count 2 2006.257.02:01:03.04#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.02:01:03.04#ibcon#[25=AT06-04\r\n] 2006.257.02:01:03.04#ibcon#*before write, iclass 33, count 2 2006.257.02:01:03.04#ibcon#enter sib2, iclass 33, count 2 2006.257.02:01:03.04#ibcon#flushed, iclass 33, count 2 2006.257.02:01:03.04#ibcon#about to write, iclass 33, count 2 2006.257.02:01:03.04#ibcon#wrote, iclass 33, count 2 2006.257.02:01:03.04#ibcon#about to read 3, iclass 33, count 2 2006.257.02:01:03.07#ibcon#read 3, iclass 33, count 2 2006.257.02:01:03.07#ibcon#about to read 4, iclass 33, count 2 2006.257.02:01:03.07#ibcon#read 4, iclass 33, count 2 2006.257.02:01:03.07#ibcon#about to read 5, iclass 33, count 2 2006.257.02:01:03.07#ibcon#read 5, iclass 33, count 2 2006.257.02:01:03.07#ibcon#about to read 6, iclass 33, count 2 2006.257.02:01:03.07#ibcon#read 6, iclass 33, count 2 2006.257.02:01:03.07#ibcon#end of sib2, iclass 33, count 2 2006.257.02:01:03.07#ibcon#*after write, iclass 33, count 2 2006.257.02:01:03.07#ibcon#*before return 0, iclass 33, count 2 2006.257.02:01:03.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:03.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:03.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.02:01:03.07#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:03.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:03.19#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:03.19#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:03.19#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:01:03.19#ibcon#first serial, iclass 33, count 0 2006.257.02:01:03.19#ibcon#enter sib2, iclass 33, count 0 2006.257.02:01:03.19#ibcon#flushed, iclass 33, count 0 2006.257.02:01:03.19#ibcon#about to write, iclass 33, count 0 2006.257.02:01:03.19#ibcon#wrote, iclass 33, count 0 2006.257.02:01:03.19#ibcon#about to read 3, iclass 33, count 0 2006.257.02:01:03.21#ibcon#read 3, iclass 33, count 0 2006.257.02:01:03.21#ibcon#about to read 4, iclass 33, count 0 2006.257.02:01:03.21#ibcon#read 4, iclass 33, count 0 2006.257.02:01:03.21#ibcon#about to read 5, iclass 33, count 0 2006.257.02:01:03.21#ibcon#read 5, iclass 33, count 0 2006.257.02:01:03.21#ibcon#about to read 6, iclass 33, count 0 2006.257.02:01:03.21#ibcon#read 6, iclass 33, count 0 2006.257.02:01:03.21#ibcon#end of sib2, iclass 33, count 0 2006.257.02:01:03.21#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:01:03.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:01:03.21#ibcon#[25=USB\r\n] 2006.257.02:01:03.21#ibcon#*before write, iclass 33, count 0 2006.257.02:01:03.21#ibcon#enter sib2, iclass 33, count 0 2006.257.02:01:03.21#ibcon#flushed, iclass 33, count 0 2006.257.02:01:03.21#ibcon#about to write, iclass 33, count 0 2006.257.02:01:03.21#ibcon#wrote, iclass 33, count 0 2006.257.02:01:03.21#ibcon#about to read 3, iclass 33, count 0 2006.257.02:01:03.24#ibcon#read 3, iclass 33, count 0 2006.257.02:01:03.24#ibcon#about to read 4, iclass 33, count 0 2006.257.02:01:03.24#ibcon#read 4, iclass 33, count 0 2006.257.02:01:03.24#ibcon#about to read 5, iclass 33, count 0 2006.257.02:01:03.24#ibcon#read 5, iclass 33, count 0 2006.257.02:01:03.24#ibcon#about to read 6, iclass 33, count 0 2006.257.02:01:03.24#ibcon#read 6, iclass 33, count 0 2006.257.02:01:03.24#ibcon#end of sib2, iclass 33, count 0 2006.257.02:01:03.24#ibcon#*after write, iclass 33, count 0 2006.257.02:01:03.24#ibcon#*before return 0, iclass 33, count 0 2006.257.02:01:03.24#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:03.24#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:03.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:01:03.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:01:03.24$vck44/valo=7,864.99 2006.257.02:01:03.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.02:01:03.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.02:01:03.24#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:03.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:03.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:03.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:03.24#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:01:03.24#ibcon#first serial, iclass 35, count 0 2006.257.02:01:03.24#ibcon#enter sib2, iclass 35, count 0 2006.257.02:01:03.24#ibcon#flushed, iclass 35, count 0 2006.257.02:01:03.24#ibcon#about to write, iclass 35, count 0 2006.257.02:01:03.24#ibcon#wrote, iclass 35, count 0 2006.257.02:01:03.24#ibcon#about to read 3, iclass 35, count 0 2006.257.02:01:03.26#ibcon#read 3, iclass 35, count 0 2006.257.02:01:03.26#ibcon#about to read 4, iclass 35, count 0 2006.257.02:01:03.26#ibcon#read 4, iclass 35, count 0 2006.257.02:01:03.26#ibcon#about to read 5, iclass 35, count 0 2006.257.02:01:03.26#ibcon#read 5, iclass 35, count 0 2006.257.02:01:03.26#ibcon#about to read 6, iclass 35, count 0 2006.257.02:01:03.26#ibcon#read 6, iclass 35, count 0 2006.257.02:01:03.26#ibcon#end of sib2, iclass 35, count 0 2006.257.02:01:03.26#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:01:03.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:01:03.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:01:03.26#ibcon#*before write, iclass 35, count 0 2006.257.02:01:03.26#ibcon#enter sib2, iclass 35, count 0 2006.257.02:01:03.26#ibcon#flushed, iclass 35, count 0 2006.257.02:01:03.26#ibcon#about to write, iclass 35, count 0 2006.257.02:01:03.26#ibcon#wrote, iclass 35, count 0 2006.257.02:01:03.26#ibcon#about to read 3, iclass 35, count 0 2006.257.02:01:03.30#ibcon#read 3, iclass 35, count 0 2006.257.02:01:03.30#ibcon#about to read 4, iclass 35, count 0 2006.257.02:01:03.30#ibcon#read 4, iclass 35, count 0 2006.257.02:01:03.30#ibcon#about to read 5, iclass 35, count 0 2006.257.02:01:03.30#ibcon#read 5, iclass 35, count 0 2006.257.02:01:03.30#ibcon#about to read 6, iclass 35, count 0 2006.257.02:01:03.30#ibcon#read 6, iclass 35, count 0 2006.257.02:01:03.30#ibcon#end of sib2, iclass 35, count 0 2006.257.02:01:03.30#ibcon#*after write, iclass 35, count 0 2006.257.02:01:03.30#ibcon#*before return 0, iclass 35, count 0 2006.257.02:01:03.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:03.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:03.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:01:03.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:01:03.30$vck44/va=7,4 2006.257.02:01:03.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.02:01:03.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.02:01:03.30#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:03.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:03.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:03.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:03.36#ibcon#enter wrdev, iclass 37, count 2 2006.257.02:01:03.36#ibcon#first serial, iclass 37, count 2 2006.257.02:01:03.36#ibcon#enter sib2, iclass 37, count 2 2006.257.02:01:03.36#ibcon#flushed, iclass 37, count 2 2006.257.02:01:03.36#ibcon#about to write, iclass 37, count 2 2006.257.02:01:03.36#ibcon#wrote, iclass 37, count 2 2006.257.02:01:03.36#ibcon#about to read 3, iclass 37, count 2 2006.257.02:01:03.38#ibcon#read 3, iclass 37, count 2 2006.257.02:01:03.38#ibcon#about to read 4, iclass 37, count 2 2006.257.02:01:03.38#ibcon#read 4, iclass 37, count 2 2006.257.02:01:03.38#ibcon#about to read 5, iclass 37, count 2 2006.257.02:01:03.38#ibcon#read 5, iclass 37, count 2 2006.257.02:01:03.38#ibcon#about to read 6, iclass 37, count 2 2006.257.02:01:03.38#ibcon#read 6, iclass 37, count 2 2006.257.02:01:03.38#ibcon#end of sib2, iclass 37, count 2 2006.257.02:01:03.38#ibcon#*mode == 0, iclass 37, count 2 2006.257.02:01:03.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.02:01:03.38#ibcon#[25=AT07-04\r\n] 2006.257.02:01:03.38#ibcon#*before write, iclass 37, count 2 2006.257.02:01:03.38#ibcon#enter sib2, iclass 37, count 2 2006.257.02:01:03.38#ibcon#flushed, iclass 37, count 2 2006.257.02:01:03.38#ibcon#about to write, iclass 37, count 2 2006.257.02:01:03.38#ibcon#wrote, iclass 37, count 2 2006.257.02:01:03.38#ibcon#about to read 3, iclass 37, count 2 2006.257.02:01:03.41#ibcon#read 3, iclass 37, count 2 2006.257.02:01:03.41#ibcon#about to read 4, iclass 37, count 2 2006.257.02:01:03.41#ibcon#read 4, iclass 37, count 2 2006.257.02:01:03.41#ibcon#about to read 5, iclass 37, count 2 2006.257.02:01:03.41#ibcon#read 5, iclass 37, count 2 2006.257.02:01:03.41#ibcon#about to read 6, iclass 37, count 2 2006.257.02:01:03.41#ibcon#read 6, iclass 37, count 2 2006.257.02:01:03.41#ibcon#end of sib2, iclass 37, count 2 2006.257.02:01:03.41#ibcon#*after write, iclass 37, count 2 2006.257.02:01:03.41#ibcon#*before return 0, iclass 37, count 2 2006.257.02:01:03.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:03.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:03.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.02:01:03.41#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:03.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:03.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:03.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:03.53#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:01:03.53#ibcon#first serial, iclass 37, count 0 2006.257.02:01:03.53#ibcon#enter sib2, iclass 37, count 0 2006.257.02:01:03.53#ibcon#flushed, iclass 37, count 0 2006.257.02:01:03.53#ibcon#about to write, iclass 37, count 0 2006.257.02:01:03.53#ibcon#wrote, iclass 37, count 0 2006.257.02:01:03.53#ibcon#about to read 3, iclass 37, count 0 2006.257.02:01:03.55#ibcon#read 3, iclass 37, count 0 2006.257.02:01:03.55#ibcon#about to read 4, iclass 37, count 0 2006.257.02:01:03.55#ibcon#read 4, iclass 37, count 0 2006.257.02:01:03.55#ibcon#about to read 5, iclass 37, count 0 2006.257.02:01:03.55#ibcon#read 5, iclass 37, count 0 2006.257.02:01:03.55#ibcon#about to read 6, iclass 37, count 0 2006.257.02:01:03.55#ibcon#read 6, iclass 37, count 0 2006.257.02:01:03.55#ibcon#end of sib2, iclass 37, count 0 2006.257.02:01:03.55#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:01:03.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:01:03.55#ibcon#[25=USB\r\n] 2006.257.02:01:03.55#ibcon#*before write, iclass 37, count 0 2006.257.02:01:03.55#ibcon#enter sib2, iclass 37, count 0 2006.257.02:01:03.55#ibcon#flushed, iclass 37, count 0 2006.257.02:01:03.55#ibcon#about to write, iclass 37, count 0 2006.257.02:01:03.55#ibcon#wrote, iclass 37, count 0 2006.257.02:01:03.55#ibcon#about to read 3, iclass 37, count 0 2006.257.02:01:03.58#ibcon#read 3, iclass 37, count 0 2006.257.02:01:03.58#ibcon#about to read 4, iclass 37, count 0 2006.257.02:01:03.58#ibcon#read 4, iclass 37, count 0 2006.257.02:01:03.58#ibcon#about to read 5, iclass 37, count 0 2006.257.02:01:03.58#ibcon#read 5, iclass 37, count 0 2006.257.02:01:03.58#ibcon#about to read 6, iclass 37, count 0 2006.257.02:01:03.58#ibcon#read 6, iclass 37, count 0 2006.257.02:01:03.58#ibcon#end of sib2, iclass 37, count 0 2006.257.02:01:03.58#ibcon#*after write, iclass 37, count 0 2006.257.02:01:03.58#ibcon#*before return 0, iclass 37, count 0 2006.257.02:01:03.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:03.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:03.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:01:03.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:01:03.58$vck44/valo=8,884.99 2006.257.02:01:03.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.02:01:03.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.02:01:03.58#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:03.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:03.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:03.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:03.58#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:01:03.58#ibcon#first serial, iclass 39, count 0 2006.257.02:01:03.58#ibcon#enter sib2, iclass 39, count 0 2006.257.02:01:03.58#ibcon#flushed, iclass 39, count 0 2006.257.02:01:03.58#ibcon#about to write, iclass 39, count 0 2006.257.02:01:03.58#ibcon#wrote, iclass 39, count 0 2006.257.02:01:03.58#ibcon#about to read 3, iclass 39, count 0 2006.257.02:01:03.60#ibcon#read 3, iclass 39, count 0 2006.257.02:01:03.60#ibcon#about to read 4, iclass 39, count 0 2006.257.02:01:03.60#ibcon#read 4, iclass 39, count 0 2006.257.02:01:03.60#ibcon#about to read 5, iclass 39, count 0 2006.257.02:01:03.60#ibcon#read 5, iclass 39, count 0 2006.257.02:01:03.60#ibcon#about to read 6, iclass 39, count 0 2006.257.02:01:03.60#ibcon#read 6, iclass 39, count 0 2006.257.02:01:03.60#ibcon#end of sib2, iclass 39, count 0 2006.257.02:01:03.60#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:01:03.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:01:03.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:01:03.60#ibcon#*before write, iclass 39, count 0 2006.257.02:01:03.60#ibcon#enter sib2, iclass 39, count 0 2006.257.02:01:03.60#ibcon#flushed, iclass 39, count 0 2006.257.02:01:03.60#ibcon#about to write, iclass 39, count 0 2006.257.02:01:03.60#ibcon#wrote, iclass 39, count 0 2006.257.02:01:03.60#ibcon#about to read 3, iclass 39, count 0 2006.257.02:01:03.64#ibcon#read 3, iclass 39, count 0 2006.257.02:01:03.64#ibcon#about to read 4, iclass 39, count 0 2006.257.02:01:03.64#ibcon#read 4, iclass 39, count 0 2006.257.02:01:03.64#ibcon#about to read 5, iclass 39, count 0 2006.257.02:01:03.64#ibcon#read 5, iclass 39, count 0 2006.257.02:01:03.64#ibcon#about to read 6, iclass 39, count 0 2006.257.02:01:03.64#ibcon#read 6, iclass 39, count 0 2006.257.02:01:03.64#ibcon#end of sib2, iclass 39, count 0 2006.257.02:01:03.64#ibcon#*after write, iclass 39, count 0 2006.257.02:01:03.64#ibcon#*before return 0, iclass 39, count 0 2006.257.02:01:03.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:03.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:03.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:01:03.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:01:03.64$vck44/va=8,4 2006.257.02:01:03.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.02:01:03.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.02:01:03.64#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:03.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:03.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:03.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:03.70#ibcon#enter wrdev, iclass 3, count 2 2006.257.02:01:03.70#ibcon#first serial, iclass 3, count 2 2006.257.02:01:03.70#ibcon#enter sib2, iclass 3, count 2 2006.257.02:01:03.70#ibcon#flushed, iclass 3, count 2 2006.257.02:01:03.70#ibcon#about to write, iclass 3, count 2 2006.257.02:01:03.70#ibcon#wrote, iclass 3, count 2 2006.257.02:01:03.70#ibcon#about to read 3, iclass 3, count 2 2006.257.02:01:03.72#ibcon#read 3, iclass 3, count 2 2006.257.02:01:03.72#ibcon#about to read 4, iclass 3, count 2 2006.257.02:01:03.72#ibcon#read 4, iclass 3, count 2 2006.257.02:01:03.72#ibcon#about to read 5, iclass 3, count 2 2006.257.02:01:03.72#ibcon#read 5, iclass 3, count 2 2006.257.02:01:03.72#ibcon#about to read 6, iclass 3, count 2 2006.257.02:01:03.72#ibcon#read 6, iclass 3, count 2 2006.257.02:01:03.72#ibcon#end of sib2, iclass 3, count 2 2006.257.02:01:03.72#ibcon#*mode == 0, iclass 3, count 2 2006.257.02:01:03.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.02:01:03.72#ibcon#[25=AT08-04\r\n] 2006.257.02:01:03.72#ibcon#*before write, iclass 3, count 2 2006.257.02:01:03.72#ibcon#enter sib2, iclass 3, count 2 2006.257.02:01:03.72#ibcon#flushed, iclass 3, count 2 2006.257.02:01:03.72#ibcon#about to write, iclass 3, count 2 2006.257.02:01:03.72#ibcon#wrote, iclass 3, count 2 2006.257.02:01:03.72#ibcon#about to read 3, iclass 3, count 2 2006.257.02:01:03.75#ibcon#read 3, iclass 3, count 2 2006.257.02:01:03.75#ibcon#about to read 4, iclass 3, count 2 2006.257.02:01:03.75#ibcon#read 4, iclass 3, count 2 2006.257.02:01:03.75#ibcon#about to read 5, iclass 3, count 2 2006.257.02:01:03.75#ibcon#read 5, iclass 3, count 2 2006.257.02:01:03.75#ibcon#about to read 6, iclass 3, count 2 2006.257.02:01:03.75#ibcon#read 6, iclass 3, count 2 2006.257.02:01:03.75#ibcon#end of sib2, iclass 3, count 2 2006.257.02:01:03.75#ibcon#*after write, iclass 3, count 2 2006.257.02:01:03.75#ibcon#*before return 0, iclass 3, count 2 2006.257.02:01:03.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:03.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:03.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.02:01:03.75#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:03.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:03.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:03.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:03.87#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:01:03.87#ibcon#first serial, iclass 3, count 0 2006.257.02:01:03.87#ibcon#enter sib2, iclass 3, count 0 2006.257.02:01:03.87#ibcon#flushed, iclass 3, count 0 2006.257.02:01:03.87#ibcon#about to write, iclass 3, count 0 2006.257.02:01:03.87#ibcon#wrote, iclass 3, count 0 2006.257.02:01:03.87#ibcon#about to read 3, iclass 3, count 0 2006.257.02:01:03.89#ibcon#read 3, iclass 3, count 0 2006.257.02:01:03.89#ibcon#about to read 4, iclass 3, count 0 2006.257.02:01:03.89#ibcon#read 4, iclass 3, count 0 2006.257.02:01:03.89#ibcon#about to read 5, iclass 3, count 0 2006.257.02:01:03.89#ibcon#read 5, iclass 3, count 0 2006.257.02:01:03.89#ibcon#about to read 6, iclass 3, count 0 2006.257.02:01:03.89#ibcon#read 6, iclass 3, count 0 2006.257.02:01:03.89#ibcon#end of sib2, iclass 3, count 0 2006.257.02:01:03.89#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:01:03.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:01:03.89#ibcon#[25=USB\r\n] 2006.257.02:01:03.89#ibcon#*before write, iclass 3, count 0 2006.257.02:01:03.89#ibcon#enter sib2, iclass 3, count 0 2006.257.02:01:03.89#ibcon#flushed, iclass 3, count 0 2006.257.02:01:03.89#ibcon#about to write, iclass 3, count 0 2006.257.02:01:03.89#ibcon#wrote, iclass 3, count 0 2006.257.02:01:03.89#ibcon#about to read 3, iclass 3, count 0 2006.257.02:01:03.92#ibcon#read 3, iclass 3, count 0 2006.257.02:01:03.92#ibcon#about to read 4, iclass 3, count 0 2006.257.02:01:03.92#ibcon#read 4, iclass 3, count 0 2006.257.02:01:03.92#ibcon#about to read 5, iclass 3, count 0 2006.257.02:01:03.92#ibcon#read 5, iclass 3, count 0 2006.257.02:01:03.92#ibcon#about to read 6, iclass 3, count 0 2006.257.02:01:03.92#ibcon#read 6, iclass 3, count 0 2006.257.02:01:03.92#ibcon#end of sib2, iclass 3, count 0 2006.257.02:01:03.92#ibcon#*after write, iclass 3, count 0 2006.257.02:01:03.92#ibcon#*before return 0, iclass 3, count 0 2006.257.02:01:03.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:03.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:03.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:01:03.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:01:03.92$vck44/vblo=1,629.99 2006.257.02:01:03.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.02:01:03.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.02:01:03.92#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:03.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:03.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:03.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:03.92#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:01:03.92#ibcon#first serial, iclass 5, count 0 2006.257.02:01:03.92#ibcon#enter sib2, iclass 5, count 0 2006.257.02:01:03.92#ibcon#flushed, iclass 5, count 0 2006.257.02:01:03.92#ibcon#about to write, iclass 5, count 0 2006.257.02:01:03.92#ibcon#wrote, iclass 5, count 0 2006.257.02:01:03.92#ibcon#about to read 3, iclass 5, count 0 2006.257.02:01:03.94#ibcon#read 3, iclass 5, count 0 2006.257.02:01:03.94#ibcon#about to read 4, iclass 5, count 0 2006.257.02:01:03.94#ibcon#read 4, iclass 5, count 0 2006.257.02:01:03.94#ibcon#about to read 5, iclass 5, count 0 2006.257.02:01:03.94#ibcon#read 5, iclass 5, count 0 2006.257.02:01:03.94#ibcon#about to read 6, iclass 5, count 0 2006.257.02:01:03.94#ibcon#read 6, iclass 5, count 0 2006.257.02:01:03.94#ibcon#end of sib2, iclass 5, count 0 2006.257.02:01:03.94#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:01:03.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:01:03.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:01:03.94#ibcon#*before write, iclass 5, count 0 2006.257.02:01:03.94#ibcon#enter sib2, iclass 5, count 0 2006.257.02:01:03.94#ibcon#flushed, iclass 5, count 0 2006.257.02:01:03.94#ibcon#about to write, iclass 5, count 0 2006.257.02:01:03.94#ibcon#wrote, iclass 5, count 0 2006.257.02:01:03.94#ibcon#about to read 3, iclass 5, count 0 2006.257.02:01:03.98#ibcon#read 3, iclass 5, count 0 2006.257.02:01:03.98#ibcon#about to read 4, iclass 5, count 0 2006.257.02:01:03.98#ibcon#read 4, iclass 5, count 0 2006.257.02:01:03.98#ibcon#about to read 5, iclass 5, count 0 2006.257.02:01:03.98#ibcon#read 5, iclass 5, count 0 2006.257.02:01:03.98#ibcon#about to read 6, iclass 5, count 0 2006.257.02:01:03.98#ibcon#read 6, iclass 5, count 0 2006.257.02:01:03.98#ibcon#end of sib2, iclass 5, count 0 2006.257.02:01:03.98#ibcon#*after write, iclass 5, count 0 2006.257.02:01:03.98#ibcon#*before return 0, iclass 5, count 0 2006.257.02:01:03.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:03.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:03.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:01:03.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:01:03.98$vck44/vb=1,4 2006.257.02:01:03.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.02:01:03.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.02:01:03.98#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:03.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:01:03.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:01:03.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:01:03.98#ibcon#enter wrdev, iclass 7, count 2 2006.257.02:01:03.98#ibcon#first serial, iclass 7, count 2 2006.257.02:01:03.98#ibcon#enter sib2, iclass 7, count 2 2006.257.02:01:03.98#ibcon#flushed, iclass 7, count 2 2006.257.02:01:03.98#ibcon#about to write, iclass 7, count 2 2006.257.02:01:03.98#ibcon#wrote, iclass 7, count 2 2006.257.02:01:03.98#ibcon#about to read 3, iclass 7, count 2 2006.257.02:01:04.00#ibcon#read 3, iclass 7, count 2 2006.257.02:01:04.00#ibcon#about to read 4, iclass 7, count 2 2006.257.02:01:04.00#ibcon#read 4, iclass 7, count 2 2006.257.02:01:04.00#ibcon#about to read 5, iclass 7, count 2 2006.257.02:01:04.00#ibcon#read 5, iclass 7, count 2 2006.257.02:01:04.00#ibcon#about to read 6, iclass 7, count 2 2006.257.02:01:04.00#ibcon#read 6, iclass 7, count 2 2006.257.02:01:04.00#ibcon#end of sib2, iclass 7, count 2 2006.257.02:01:04.00#ibcon#*mode == 0, iclass 7, count 2 2006.257.02:01:04.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.02:01:04.00#ibcon#[27=AT01-04\r\n] 2006.257.02:01:04.00#ibcon#*before write, iclass 7, count 2 2006.257.02:01:04.00#ibcon#enter sib2, iclass 7, count 2 2006.257.02:01:04.00#ibcon#flushed, iclass 7, count 2 2006.257.02:01:04.00#ibcon#about to write, iclass 7, count 2 2006.257.02:01:04.00#ibcon#wrote, iclass 7, count 2 2006.257.02:01:04.00#ibcon#about to read 3, iclass 7, count 2 2006.257.02:01:04.03#ibcon#read 3, iclass 7, count 2 2006.257.02:01:04.03#ibcon#about to read 4, iclass 7, count 2 2006.257.02:01:04.03#ibcon#read 4, iclass 7, count 2 2006.257.02:01:04.03#ibcon#about to read 5, iclass 7, count 2 2006.257.02:01:04.03#ibcon#read 5, iclass 7, count 2 2006.257.02:01:04.03#ibcon#about to read 6, iclass 7, count 2 2006.257.02:01:04.03#ibcon#read 6, iclass 7, count 2 2006.257.02:01:04.03#ibcon#end of sib2, iclass 7, count 2 2006.257.02:01:04.03#ibcon#*after write, iclass 7, count 2 2006.257.02:01:04.03#ibcon#*before return 0, iclass 7, count 2 2006.257.02:01:04.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:01:04.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:01:04.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.02:01:04.03#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:04.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:01:04.04#abcon#<5=/03 3.0 8.4 17.901001011.9\r\n> 2006.257.02:01:04.06#abcon#{5=INTERFACE CLEAR} 2006.257.02:01:04.12#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:01:04.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:01:04.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:01:04.15#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:01:04.15#ibcon#first serial, iclass 7, count 0 2006.257.02:01:04.15#ibcon#enter sib2, iclass 7, count 0 2006.257.02:01:04.15#ibcon#flushed, iclass 7, count 0 2006.257.02:01:04.15#ibcon#about to write, iclass 7, count 0 2006.257.02:01:04.15#ibcon#wrote, iclass 7, count 0 2006.257.02:01:04.15#ibcon#about to read 3, iclass 7, count 0 2006.257.02:01:04.17#ibcon#read 3, iclass 7, count 0 2006.257.02:01:04.17#ibcon#about to read 4, iclass 7, count 0 2006.257.02:01:04.17#ibcon#read 4, iclass 7, count 0 2006.257.02:01:04.17#ibcon#about to read 5, iclass 7, count 0 2006.257.02:01:04.17#ibcon#read 5, iclass 7, count 0 2006.257.02:01:04.17#ibcon#about to read 6, iclass 7, count 0 2006.257.02:01:04.17#ibcon#read 6, iclass 7, count 0 2006.257.02:01:04.17#ibcon#end of sib2, iclass 7, count 0 2006.257.02:01:04.17#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:01:04.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:01:04.17#ibcon#[27=USB\r\n] 2006.257.02:01:04.17#ibcon#*before write, iclass 7, count 0 2006.257.02:01:04.17#ibcon#enter sib2, iclass 7, count 0 2006.257.02:01:04.17#ibcon#flushed, iclass 7, count 0 2006.257.02:01:04.17#ibcon#about to write, iclass 7, count 0 2006.257.02:01:04.17#ibcon#wrote, iclass 7, count 0 2006.257.02:01:04.17#ibcon#about to read 3, iclass 7, count 0 2006.257.02:01:04.20#ibcon#read 3, iclass 7, count 0 2006.257.02:01:04.20#ibcon#about to read 4, iclass 7, count 0 2006.257.02:01:04.20#ibcon#read 4, iclass 7, count 0 2006.257.02:01:04.20#ibcon#about to read 5, iclass 7, count 0 2006.257.02:01:04.20#ibcon#read 5, iclass 7, count 0 2006.257.02:01:04.20#ibcon#about to read 6, iclass 7, count 0 2006.257.02:01:04.20#ibcon#read 6, iclass 7, count 0 2006.257.02:01:04.20#ibcon#end of sib2, iclass 7, count 0 2006.257.02:01:04.20#ibcon#*after write, iclass 7, count 0 2006.257.02:01:04.20#ibcon#*before return 0, iclass 7, count 0 2006.257.02:01:04.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:01:04.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:01:04.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:01:04.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:01:04.20$vck44/vblo=2,634.99 2006.257.02:01:04.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.02:01:04.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.02:01:04.20#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:04.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:04.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:04.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:04.20#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:01:04.20#ibcon#first serial, iclass 15, count 0 2006.257.02:01:04.20#ibcon#enter sib2, iclass 15, count 0 2006.257.02:01:04.20#ibcon#flushed, iclass 15, count 0 2006.257.02:01:04.20#ibcon#about to write, iclass 15, count 0 2006.257.02:01:04.20#ibcon#wrote, iclass 15, count 0 2006.257.02:01:04.20#ibcon#about to read 3, iclass 15, count 0 2006.257.02:01:04.22#ibcon#read 3, iclass 15, count 0 2006.257.02:01:04.22#ibcon#about to read 4, iclass 15, count 0 2006.257.02:01:04.22#ibcon#read 4, iclass 15, count 0 2006.257.02:01:04.22#ibcon#about to read 5, iclass 15, count 0 2006.257.02:01:04.22#ibcon#read 5, iclass 15, count 0 2006.257.02:01:04.22#ibcon#about to read 6, iclass 15, count 0 2006.257.02:01:04.22#ibcon#read 6, iclass 15, count 0 2006.257.02:01:04.22#ibcon#end of sib2, iclass 15, count 0 2006.257.02:01:04.22#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:01:04.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:01:04.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:01:04.22#ibcon#*before write, iclass 15, count 0 2006.257.02:01:04.22#ibcon#enter sib2, iclass 15, count 0 2006.257.02:01:04.22#ibcon#flushed, iclass 15, count 0 2006.257.02:01:04.22#ibcon#about to write, iclass 15, count 0 2006.257.02:01:04.22#ibcon#wrote, iclass 15, count 0 2006.257.02:01:04.22#ibcon#about to read 3, iclass 15, count 0 2006.257.02:01:04.26#ibcon#read 3, iclass 15, count 0 2006.257.02:01:04.26#ibcon#about to read 4, iclass 15, count 0 2006.257.02:01:04.26#ibcon#read 4, iclass 15, count 0 2006.257.02:01:04.26#ibcon#about to read 5, iclass 15, count 0 2006.257.02:01:04.26#ibcon#read 5, iclass 15, count 0 2006.257.02:01:04.26#ibcon#about to read 6, iclass 15, count 0 2006.257.02:01:04.26#ibcon#read 6, iclass 15, count 0 2006.257.02:01:04.26#ibcon#end of sib2, iclass 15, count 0 2006.257.02:01:04.26#ibcon#*after write, iclass 15, count 0 2006.257.02:01:04.26#ibcon#*before return 0, iclass 15, count 0 2006.257.02:01:04.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:04.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:01:04.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:01:04.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:01:04.26$vck44/vb=2,5 2006.257.02:01:04.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.02:01:04.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.02:01:04.26#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:04.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:04.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:04.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:04.32#ibcon#enter wrdev, iclass 17, count 2 2006.257.02:01:04.32#ibcon#first serial, iclass 17, count 2 2006.257.02:01:04.32#ibcon#enter sib2, iclass 17, count 2 2006.257.02:01:04.32#ibcon#flushed, iclass 17, count 2 2006.257.02:01:04.32#ibcon#about to write, iclass 17, count 2 2006.257.02:01:04.32#ibcon#wrote, iclass 17, count 2 2006.257.02:01:04.32#ibcon#about to read 3, iclass 17, count 2 2006.257.02:01:04.34#ibcon#read 3, iclass 17, count 2 2006.257.02:01:04.34#ibcon#about to read 4, iclass 17, count 2 2006.257.02:01:04.34#ibcon#read 4, iclass 17, count 2 2006.257.02:01:04.34#ibcon#about to read 5, iclass 17, count 2 2006.257.02:01:04.34#ibcon#read 5, iclass 17, count 2 2006.257.02:01:04.34#ibcon#about to read 6, iclass 17, count 2 2006.257.02:01:04.34#ibcon#read 6, iclass 17, count 2 2006.257.02:01:04.34#ibcon#end of sib2, iclass 17, count 2 2006.257.02:01:04.34#ibcon#*mode == 0, iclass 17, count 2 2006.257.02:01:04.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.02:01:04.34#ibcon#[27=AT02-05\r\n] 2006.257.02:01:04.34#ibcon#*before write, iclass 17, count 2 2006.257.02:01:04.34#ibcon#enter sib2, iclass 17, count 2 2006.257.02:01:04.34#ibcon#flushed, iclass 17, count 2 2006.257.02:01:04.34#ibcon#about to write, iclass 17, count 2 2006.257.02:01:04.34#ibcon#wrote, iclass 17, count 2 2006.257.02:01:04.34#ibcon#about to read 3, iclass 17, count 2 2006.257.02:01:04.37#ibcon#read 3, iclass 17, count 2 2006.257.02:01:04.37#ibcon#about to read 4, iclass 17, count 2 2006.257.02:01:04.37#ibcon#read 4, iclass 17, count 2 2006.257.02:01:04.37#ibcon#about to read 5, iclass 17, count 2 2006.257.02:01:04.37#ibcon#read 5, iclass 17, count 2 2006.257.02:01:04.37#ibcon#about to read 6, iclass 17, count 2 2006.257.02:01:04.37#ibcon#read 6, iclass 17, count 2 2006.257.02:01:04.37#ibcon#end of sib2, iclass 17, count 2 2006.257.02:01:04.37#ibcon#*after write, iclass 17, count 2 2006.257.02:01:04.37#ibcon#*before return 0, iclass 17, count 2 2006.257.02:01:04.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:04.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:01:04.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.02:01:04.37#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:04.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:04.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:04.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:04.49#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:01:04.49#ibcon#first serial, iclass 17, count 0 2006.257.02:01:04.49#ibcon#enter sib2, iclass 17, count 0 2006.257.02:01:04.49#ibcon#flushed, iclass 17, count 0 2006.257.02:01:04.49#ibcon#about to write, iclass 17, count 0 2006.257.02:01:04.49#ibcon#wrote, iclass 17, count 0 2006.257.02:01:04.49#ibcon#about to read 3, iclass 17, count 0 2006.257.02:01:04.51#ibcon#read 3, iclass 17, count 0 2006.257.02:01:04.51#ibcon#about to read 4, iclass 17, count 0 2006.257.02:01:04.51#ibcon#read 4, iclass 17, count 0 2006.257.02:01:04.51#ibcon#about to read 5, iclass 17, count 0 2006.257.02:01:04.51#ibcon#read 5, iclass 17, count 0 2006.257.02:01:04.51#ibcon#about to read 6, iclass 17, count 0 2006.257.02:01:04.51#ibcon#read 6, iclass 17, count 0 2006.257.02:01:04.51#ibcon#end of sib2, iclass 17, count 0 2006.257.02:01:04.51#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:01:04.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:01:04.51#ibcon#[27=USB\r\n] 2006.257.02:01:04.51#ibcon#*before write, iclass 17, count 0 2006.257.02:01:04.51#ibcon#enter sib2, iclass 17, count 0 2006.257.02:01:04.51#ibcon#flushed, iclass 17, count 0 2006.257.02:01:04.51#ibcon#about to write, iclass 17, count 0 2006.257.02:01:04.51#ibcon#wrote, iclass 17, count 0 2006.257.02:01:04.51#ibcon#about to read 3, iclass 17, count 0 2006.257.02:01:04.54#ibcon#read 3, iclass 17, count 0 2006.257.02:01:04.54#ibcon#about to read 4, iclass 17, count 0 2006.257.02:01:04.54#ibcon#read 4, iclass 17, count 0 2006.257.02:01:04.54#ibcon#about to read 5, iclass 17, count 0 2006.257.02:01:04.54#ibcon#read 5, iclass 17, count 0 2006.257.02:01:04.54#ibcon#about to read 6, iclass 17, count 0 2006.257.02:01:04.54#ibcon#read 6, iclass 17, count 0 2006.257.02:01:04.54#ibcon#end of sib2, iclass 17, count 0 2006.257.02:01:04.54#ibcon#*after write, iclass 17, count 0 2006.257.02:01:04.54#ibcon#*before return 0, iclass 17, count 0 2006.257.02:01:04.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:04.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:01:04.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:01:04.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:01:04.54$vck44/vblo=3,649.99 2006.257.02:01:04.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.02:01:04.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.02:01:04.54#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:04.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:04.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:04.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:04.54#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:01:04.54#ibcon#first serial, iclass 19, count 0 2006.257.02:01:04.54#ibcon#enter sib2, iclass 19, count 0 2006.257.02:01:04.54#ibcon#flushed, iclass 19, count 0 2006.257.02:01:04.54#ibcon#about to write, iclass 19, count 0 2006.257.02:01:04.54#ibcon#wrote, iclass 19, count 0 2006.257.02:01:04.54#ibcon#about to read 3, iclass 19, count 0 2006.257.02:01:04.56#ibcon#read 3, iclass 19, count 0 2006.257.02:01:04.56#ibcon#about to read 4, iclass 19, count 0 2006.257.02:01:04.56#ibcon#read 4, iclass 19, count 0 2006.257.02:01:04.56#ibcon#about to read 5, iclass 19, count 0 2006.257.02:01:04.56#ibcon#read 5, iclass 19, count 0 2006.257.02:01:04.56#ibcon#about to read 6, iclass 19, count 0 2006.257.02:01:04.56#ibcon#read 6, iclass 19, count 0 2006.257.02:01:04.56#ibcon#end of sib2, iclass 19, count 0 2006.257.02:01:04.56#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:01:04.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:01:04.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:01:04.56#ibcon#*before write, iclass 19, count 0 2006.257.02:01:04.56#ibcon#enter sib2, iclass 19, count 0 2006.257.02:01:04.56#ibcon#flushed, iclass 19, count 0 2006.257.02:01:04.56#ibcon#about to write, iclass 19, count 0 2006.257.02:01:04.56#ibcon#wrote, iclass 19, count 0 2006.257.02:01:04.56#ibcon#about to read 3, iclass 19, count 0 2006.257.02:01:04.60#ibcon#read 3, iclass 19, count 0 2006.257.02:01:04.60#ibcon#about to read 4, iclass 19, count 0 2006.257.02:01:04.60#ibcon#read 4, iclass 19, count 0 2006.257.02:01:04.60#ibcon#about to read 5, iclass 19, count 0 2006.257.02:01:04.60#ibcon#read 5, iclass 19, count 0 2006.257.02:01:04.60#ibcon#about to read 6, iclass 19, count 0 2006.257.02:01:04.60#ibcon#read 6, iclass 19, count 0 2006.257.02:01:04.60#ibcon#end of sib2, iclass 19, count 0 2006.257.02:01:04.60#ibcon#*after write, iclass 19, count 0 2006.257.02:01:04.60#ibcon#*before return 0, iclass 19, count 0 2006.257.02:01:04.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:04.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:01:04.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:01:04.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:01:04.60$vck44/vb=3,4 2006.257.02:01:04.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.02:01:04.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.02:01:04.60#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:04.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:04.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:04.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:04.66#ibcon#enter wrdev, iclass 21, count 2 2006.257.02:01:04.66#ibcon#first serial, iclass 21, count 2 2006.257.02:01:04.66#ibcon#enter sib2, iclass 21, count 2 2006.257.02:01:04.66#ibcon#flushed, iclass 21, count 2 2006.257.02:01:04.66#ibcon#about to write, iclass 21, count 2 2006.257.02:01:04.66#ibcon#wrote, iclass 21, count 2 2006.257.02:01:04.66#ibcon#about to read 3, iclass 21, count 2 2006.257.02:01:04.68#ibcon#read 3, iclass 21, count 2 2006.257.02:01:04.68#ibcon#about to read 4, iclass 21, count 2 2006.257.02:01:04.68#ibcon#read 4, iclass 21, count 2 2006.257.02:01:04.68#ibcon#about to read 5, iclass 21, count 2 2006.257.02:01:04.68#ibcon#read 5, iclass 21, count 2 2006.257.02:01:04.68#ibcon#about to read 6, iclass 21, count 2 2006.257.02:01:04.68#ibcon#read 6, iclass 21, count 2 2006.257.02:01:04.68#ibcon#end of sib2, iclass 21, count 2 2006.257.02:01:04.68#ibcon#*mode == 0, iclass 21, count 2 2006.257.02:01:04.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.02:01:04.68#ibcon#[27=AT03-04\r\n] 2006.257.02:01:04.68#ibcon#*before write, iclass 21, count 2 2006.257.02:01:04.68#ibcon#enter sib2, iclass 21, count 2 2006.257.02:01:04.68#ibcon#flushed, iclass 21, count 2 2006.257.02:01:04.68#ibcon#about to write, iclass 21, count 2 2006.257.02:01:04.68#ibcon#wrote, iclass 21, count 2 2006.257.02:01:04.68#ibcon#about to read 3, iclass 21, count 2 2006.257.02:01:04.71#ibcon#read 3, iclass 21, count 2 2006.257.02:01:04.71#ibcon#about to read 4, iclass 21, count 2 2006.257.02:01:04.71#ibcon#read 4, iclass 21, count 2 2006.257.02:01:04.71#ibcon#about to read 5, iclass 21, count 2 2006.257.02:01:04.71#ibcon#read 5, iclass 21, count 2 2006.257.02:01:04.71#ibcon#about to read 6, iclass 21, count 2 2006.257.02:01:04.71#ibcon#read 6, iclass 21, count 2 2006.257.02:01:04.71#ibcon#end of sib2, iclass 21, count 2 2006.257.02:01:04.71#ibcon#*after write, iclass 21, count 2 2006.257.02:01:04.71#ibcon#*before return 0, iclass 21, count 2 2006.257.02:01:04.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:04.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:01:04.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.02:01:04.71#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:04.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:04.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:04.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:04.83#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:01:04.83#ibcon#first serial, iclass 21, count 0 2006.257.02:01:04.83#ibcon#enter sib2, iclass 21, count 0 2006.257.02:01:04.83#ibcon#flushed, iclass 21, count 0 2006.257.02:01:04.83#ibcon#about to write, iclass 21, count 0 2006.257.02:01:04.83#ibcon#wrote, iclass 21, count 0 2006.257.02:01:04.83#ibcon#about to read 3, iclass 21, count 0 2006.257.02:01:04.85#ibcon#read 3, iclass 21, count 0 2006.257.02:01:04.85#ibcon#about to read 4, iclass 21, count 0 2006.257.02:01:04.85#ibcon#read 4, iclass 21, count 0 2006.257.02:01:04.85#ibcon#about to read 5, iclass 21, count 0 2006.257.02:01:04.85#ibcon#read 5, iclass 21, count 0 2006.257.02:01:04.85#ibcon#about to read 6, iclass 21, count 0 2006.257.02:01:04.85#ibcon#read 6, iclass 21, count 0 2006.257.02:01:04.85#ibcon#end of sib2, iclass 21, count 0 2006.257.02:01:04.85#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:01:04.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:01:04.85#ibcon#[27=USB\r\n] 2006.257.02:01:04.85#ibcon#*before write, iclass 21, count 0 2006.257.02:01:04.85#ibcon#enter sib2, iclass 21, count 0 2006.257.02:01:04.85#ibcon#flushed, iclass 21, count 0 2006.257.02:01:04.85#ibcon#about to write, iclass 21, count 0 2006.257.02:01:04.85#ibcon#wrote, iclass 21, count 0 2006.257.02:01:04.85#ibcon#about to read 3, iclass 21, count 0 2006.257.02:01:04.88#ibcon#read 3, iclass 21, count 0 2006.257.02:01:04.88#ibcon#about to read 4, iclass 21, count 0 2006.257.02:01:04.88#ibcon#read 4, iclass 21, count 0 2006.257.02:01:04.88#ibcon#about to read 5, iclass 21, count 0 2006.257.02:01:04.88#ibcon#read 5, iclass 21, count 0 2006.257.02:01:04.88#ibcon#about to read 6, iclass 21, count 0 2006.257.02:01:04.88#ibcon#read 6, iclass 21, count 0 2006.257.02:01:04.88#ibcon#end of sib2, iclass 21, count 0 2006.257.02:01:04.88#ibcon#*after write, iclass 21, count 0 2006.257.02:01:04.88#ibcon#*before return 0, iclass 21, count 0 2006.257.02:01:04.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:04.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:01:04.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:01:04.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:01:04.88$vck44/vblo=4,679.99 2006.257.02:01:04.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.02:01:04.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.02:01:04.88#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:04.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:04.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:04.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:04.88#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:01:04.88#ibcon#first serial, iclass 23, count 0 2006.257.02:01:04.88#ibcon#enter sib2, iclass 23, count 0 2006.257.02:01:04.88#ibcon#flushed, iclass 23, count 0 2006.257.02:01:04.88#ibcon#about to write, iclass 23, count 0 2006.257.02:01:04.88#ibcon#wrote, iclass 23, count 0 2006.257.02:01:04.88#ibcon#about to read 3, iclass 23, count 0 2006.257.02:01:04.90#ibcon#read 3, iclass 23, count 0 2006.257.02:01:04.90#ibcon#about to read 4, iclass 23, count 0 2006.257.02:01:04.90#ibcon#read 4, iclass 23, count 0 2006.257.02:01:04.90#ibcon#about to read 5, iclass 23, count 0 2006.257.02:01:04.90#ibcon#read 5, iclass 23, count 0 2006.257.02:01:04.90#ibcon#about to read 6, iclass 23, count 0 2006.257.02:01:04.90#ibcon#read 6, iclass 23, count 0 2006.257.02:01:04.90#ibcon#end of sib2, iclass 23, count 0 2006.257.02:01:04.90#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:01:04.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:01:04.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:01:04.90#ibcon#*before write, iclass 23, count 0 2006.257.02:01:04.90#ibcon#enter sib2, iclass 23, count 0 2006.257.02:01:04.90#ibcon#flushed, iclass 23, count 0 2006.257.02:01:04.90#ibcon#about to write, iclass 23, count 0 2006.257.02:01:04.90#ibcon#wrote, iclass 23, count 0 2006.257.02:01:04.90#ibcon#about to read 3, iclass 23, count 0 2006.257.02:01:04.94#ibcon#read 3, iclass 23, count 0 2006.257.02:01:04.94#ibcon#about to read 4, iclass 23, count 0 2006.257.02:01:04.94#ibcon#read 4, iclass 23, count 0 2006.257.02:01:04.94#ibcon#about to read 5, iclass 23, count 0 2006.257.02:01:04.94#ibcon#read 5, iclass 23, count 0 2006.257.02:01:04.94#ibcon#about to read 6, iclass 23, count 0 2006.257.02:01:04.94#ibcon#read 6, iclass 23, count 0 2006.257.02:01:04.94#ibcon#end of sib2, iclass 23, count 0 2006.257.02:01:04.94#ibcon#*after write, iclass 23, count 0 2006.257.02:01:04.94#ibcon#*before return 0, iclass 23, count 0 2006.257.02:01:04.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:04.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:01:04.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:01:04.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:01:04.94$vck44/vb=4,5 2006.257.02:01:04.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.02:01:04.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.02:01:04.94#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:04.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:05.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:05.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:05.00#ibcon#enter wrdev, iclass 25, count 2 2006.257.02:01:05.00#ibcon#first serial, iclass 25, count 2 2006.257.02:01:05.00#ibcon#enter sib2, iclass 25, count 2 2006.257.02:01:05.00#ibcon#flushed, iclass 25, count 2 2006.257.02:01:05.00#ibcon#about to write, iclass 25, count 2 2006.257.02:01:05.00#ibcon#wrote, iclass 25, count 2 2006.257.02:01:05.00#ibcon#about to read 3, iclass 25, count 2 2006.257.02:01:05.02#ibcon#read 3, iclass 25, count 2 2006.257.02:01:05.02#ibcon#about to read 4, iclass 25, count 2 2006.257.02:01:05.02#ibcon#read 4, iclass 25, count 2 2006.257.02:01:05.02#ibcon#about to read 5, iclass 25, count 2 2006.257.02:01:05.02#ibcon#read 5, iclass 25, count 2 2006.257.02:01:05.02#ibcon#about to read 6, iclass 25, count 2 2006.257.02:01:05.02#ibcon#read 6, iclass 25, count 2 2006.257.02:01:05.02#ibcon#end of sib2, iclass 25, count 2 2006.257.02:01:05.02#ibcon#*mode == 0, iclass 25, count 2 2006.257.02:01:05.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.02:01:05.02#ibcon#[27=AT04-05\r\n] 2006.257.02:01:05.02#ibcon#*before write, iclass 25, count 2 2006.257.02:01:05.02#ibcon#enter sib2, iclass 25, count 2 2006.257.02:01:05.02#ibcon#flushed, iclass 25, count 2 2006.257.02:01:05.02#ibcon#about to write, iclass 25, count 2 2006.257.02:01:05.02#ibcon#wrote, iclass 25, count 2 2006.257.02:01:05.02#ibcon#about to read 3, iclass 25, count 2 2006.257.02:01:05.05#ibcon#read 3, iclass 25, count 2 2006.257.02:01:05.05#ibcon#about to read 4, iclass 25, count 2 2006.257.02:01:05.05#ibcon#read 4, iclass 25, count 2 2006.257.02:01:05.05#ibcon#about to read 5, iclass 25, count 2 2006.257.02:01:05.05#ibcon#read 5, iclass 25, count 2 2006.257.02:01:05.05#ibcon#about to read 6, iclass 25, count 2 2006.257.02:01:05.05#ibcon#read 6, iclass 25, count 2 2006.257.02:01:05.05#ibcon#end of sib2, iclass 25, count 2 2006.257.02:01:05.05#ibcon#*after write, iclass 25, count 2 2006.257.02:01:05.05#ibcon#*before return 0, iclass 25, count 2 2006.257.02:01:05.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:05.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:01:05.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.02:01:05.05#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:05.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:05.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:05.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:05.17#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:01:05.17#ibcon#first serial, iclass 25, count 0 2006.257.02:01:05.17#ibcon#enter sib2, iclass 25, count 0 2006.257.02:01:05.17#ibcon#flushed, iclass 25, count 0 2006.257.02:01:05.17#ibcon#about to write, iclass 25, count 0 2006.257.02:01:05.17#ibcon#wrote, iclass 25, count 0 2006.257.02:01:05.17#ibcon#about to read 3, iclass 25, count 0 2006.257.02:01:05.19#ibcon#read 3, iclass 25, count 0 2006.257.02:01:05.19#ibcon#about to read 4, iclass 25, count 0 2006.257.02:01:05.19#ibcon#read 4, iclass 25, count 0 2006.257.02:01:05.19#ibcon#about to read 5, iclass 25, count 0 2006.257.02:01:05.19#ibcon#read 5, iclass 25, count 0 2006.257.02:01:05.19#ibcon#about to read 6, iclass 25, count 0 2006.257.02:01:05.19#ibcon#read 6, iclass 25, count 0 2006.257.02:01:05.19#ibcon#end of sib2, iclass 25, count 0 2006.257.02:01:05.19#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:01:05.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:01:05.19#ibcon#[27=USB\r\n] 2006.257.02:01:05.19#ibcon#*before write, iclass 25, count 0 2006.257.02:01:05.19#ibcon#enter sib2, iclass 25, count 0 2006.257.02:01:05.19#ibcon#flushed, iclass 25, count 0 2006.257.02:01:05.19#ibcon#about to write, iclass 25, count 0 2006.257.02:01:05.19#ibcon#wrote, iclass 25, count 0 2006.257.02:01:05.19#ibcon#about to read 3, iclass 25, count 0 2006.257.02:01:05.22#ibcon#read 3, iclass 25, count 0 2006.257.02:01:05.22#ibcon#about to read 4, iclass 25, count 0 2006.257.02:01:05.22#ibcon#read 4, iclass 25, count 0 2006.257.02:01:05.22#ibcon#about to read 5, iclass 25, count 0 2006.257.02:01:05.22#ibcon#read 5, iclass 25, count 0 2006.257.02:01:05.22#ibcon#about to read 6, iclass 25, count 0 2006.257.02:01:05.22#ibcon#read 6, iclass 25, count 0 2006.257.02:01:05.22#ibcon#end of sib2, iclass 25, count 0 2006.257.02:01:05.22#ibcon#*after write, iclass 25, count 0 2006.257.02:01:05.22#ibcon#*before return 0, iclass 25, count 0 2006.257.02:01:05.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:05.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:01:05.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:01:05.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:01:05.22$vck44/vblo=5,709.99 2006.257.02:01:05.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.02:01:05.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.02:01:05.22#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:05.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:05.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:05.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:05.22#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:01:05.22#ibcon#first serial, iclass 27, count 0 2006.257.02:01:05.22#ibcon#enter sib2, iclass 27, count 0 2006.257.02:01:05.22#ibcon#flushed, iclass 27, count 0 2006.257.02:01:05.22#ibcon#about to write, iclass 27, count 0 2006.257.02:01:05.22#ibcon#wrote, iclass 27, count 0 2006.257.02:01:05.22#ibcon#about to read 3, iclass 27, count 0 2006.257.02:01:05.24#ibcon#read 3, iclass 27, count 0 2006.257.02:01:05.24#ibcon#about to read 4, iclass 27, count 0 2006.257.02:01:05.24#ibcon#read 4, iclass 27, count 0 2006.257.02:01:05.24#ibcon#about to read 5, iclass 27, count 0 2006.257.02:01:05.24#ibcon#read 5, iclass 27, count 0 2006.257.02:01:05.24#ibcon#about to read 6, iclass 27, count 0 2006.257.02:01:05.24#ibcon#read 6, iclass 27, count 0 2006.257.02:01:05.24#ibcon#end of sib2, iclass 27, count 0 2006.257.02:01:05.24#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:01:05.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:01:05.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:01:05.24#ibcon#*before write, iclass 27, count 0 2006.257.02:01:05.24#ibcon#enter sib2, iclass 27, count 0 2006.257.02:01:05.24#ibcon#flushed, iclass 27, count 0 2006.257.02:01:05.24#ibcon#about to write, iclass 27, count 0 2006.257.02:01:05.24#ibcon#wrote, iclass 27, count 0 2006.257.02:01:05.24#ibcon#about to read 3, iclass 27, count 0 2006.257.02:01:05.28#ibcon#read 3, iclass 27, count 0 2006.257.02:01:05.28#ibcon#about to read 4, iclass 27, count 0 2006.257.02:01:05.28#ibcon#read 4, iclass 27, count 0 2006.257.02:01:05.28#ibcon#about to read 5, iclass 27, count 0 2006.257.02:01:05.28#ibcon#read 5, iclass 27, count 0 2006.257.02:01:05.28#ibcon#about to read 6, iclass 27, count 0 2006.257.02:01:05.28#ibcon#read 6, iclass 27, count 0 2006.257.02:01:05.28#ibcon#end of sib2, iclass 27, count 0 2006.257.02:01:05.28#ibcon#*after write, iclass 27, count 0 2006.257.02:01:05.28#ibcon#*before return 0, iclass 27, count 0 2006.257.02:01:05.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:05.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:01:05.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:01:05.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:01:05.28$vck44/vb=5,4 2006.257.02:01:05.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.02:01:05.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.02:01:05.28#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:05.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:05.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:05.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:05.34#ibcon#enter wrdev, iclass 29, count 2 2006.257.02:01:05.34#ibcon#first serial, iclass 29, count 2 2006.257.02:01:05.34#ibcon#enter sib2, iclass 29, count 2 2006.257.02:01:05.34#ibcon#flushed, iclass 29, count 2 2006.257.02:01:05.34#ibcon#about to write, iclass 29, count 2 2006.257.02:01:05.34#ibcon#wrote, iclass 29, count 2 2006.257.02:01:05.34#ibcon#about to read 3, iclass 29, count 2 2006.257.02:01:05.36#ibcon#read 3, iclass 29, count 2 2006.257.02:01:05.36#ibcon#about to read 4, iclass 29, count 2 2006.257.02:01:05.36#ibcon#read 4, iclass 29, count 2 2006.257.02:01:05.36#ibcon#about to read 5, iclass 29, count 2 2006.257.02:01:05.36#ibcon#read 5, iclass 29, count 2 2006.257.02:01:05.36#ibcon#about to read 6, iclass 29, count 2 2006.257.02:01:05.36#ibcon#read 6, iclass 29, count 2 2006.257.02:01:05.36#ibcon#end of sib2, iclass 29, count 2 2006.257.02:01:05.36#ibcon#*mode == 0, iclass 29, count 2 2006.257.02:01:05.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.02:01:05.36#ibcon#[27=AT05-04\r\n] 2006.257.02:01:05.36#ibcon#*before write, iclass 29, count 2 2006.257.02:01:05.36#ibcon#enter sib2, iclass 29, count 2 2006.257.02:01:05.36#ibcon#flushed, iclass 29, count 2 2006.257.02:01:05.36#ibcon#about to write, iclass 29, count 2 2006.257.02:01:05.36#ibcon#wrote, iclass 29, count 2 2006.257.02:01:05.36#ibcon#about to read 3, iclass 29, count 2 2006.257.02:01:05.39#ibcon#read 3, iclass 29, count 2 2006.257.02:01:05.39#ibcon#about to read 4, iclass 29, count 2 2006.257.02:01:05.39#ibcon#read 4, iclass 29, count 2 2006.257.02:01:05.39#ibcon#about to read 5, iclass 29, count 2 2006.257.02:01:05.39#ibcon#read 5, iclass 29, count 2 2006.257.02:01:05.39#ibcon#about to read 6, iclass 29, count 2 2006.257.02:01:05.39#ibcon#read 6, iclass 29, count 2 2006.257.02:01:05.39#ibcon#end of sib2, iclass 29, count 2 2006.257.02:01:05.39#ibcon#*after write, iclass 29, count 2 2006.257.02:01:05.39#ibcon#*before return 0, iclass 29, count 2 2006.257.02:01:05.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:05.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:01:05.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.02:01:05.39#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:05.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:05.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:05.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:05.51#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:01:05.51#ibcon#first serial, iclass 29, count 0 2006.257.02:01:05.51#ibcon#enter sib2, iclass 29, count 0 2006.257.02:01:05.51#ibcon#flushed, iclass 29, count 0 2006.257.02:01:05.51#ibcon#about to write, iclass 29, count 0 2006.257.02:01:05.51#ibcon#wrote, iclass 29, count 0 2006.257.02:01:05.51#ibcon#about to read 3, iclass 29, count 0 2006.257.02:01:05.53#ibcon#read 3, iclass 29, count 0 2006.257.02:01:05.53#ibcon#about to read 4, iclass 29, count 0 2006.257.02:01:05.53#ibcon#read 4, iclass 29, count 0 2006.257.02:01:05.53#ibcon#about to read 5, iclass 29, count 0 2006.257.02:01:05.53#ibcon#read 5, iclass 29, count 0 2006.257.02:01:05.53#ibcon#about to read 6, iclass 29, count 0 2006.257.02:01:05.53#ibcon#read 6, iclass 29, count 0 2006.257.02:01:05.53#ibcon#end of sib2, iclass 29, count 0 2006.257.02:01:05.53#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:01:05.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:01:05.53#ibcon#[27=USB\r\n] 2006.257.02:01:05.53#ibcon#*before write, iclass 29, count 0 2006.257.02:01:05.53#ibcon#enter sib2, iclass 29, count 0 2006.257.02:01:05.53#ibcon#flushed, iclass 29, count 0 2006.257.02:01:05.53#ibcon#about to write, iclass 29, count 0 2006.257.02:01:05.53#ibcon#wrote, iclass 29, count 0 2006.257.02:01:05.53#ibcon#about to read 3, iclass 29, count 0 2006.257.02:01:05.56#ibcon#read 3, iclass 29, count 0 2006.257.02:01:05.56#ibcon#about to read 4, iclass 29, count 0 2006.257.02:01:05.56#ibcon#read 4, iclass 29, count 0 2006.257.02:01:05.56#ibcon#about to read 5, iclass 29, count 0 2006.257.02:01:05.56#ibcon#read 5, iclass 29, count 0 2006.257.02:01:05.56#ibcon#about to read 6, iclass 29, count 0 2006.257.02:01:05.56#ibcon#read 6, iclass 29, count 0 2006.257.02:01:05.56#ibcon#end of sib2, iclass 29, count 0 2006.257.02:01:05.56#ibcon#*after write, iclass 29, count 0 2006.257.02:01:05.56#ibcon#*before return 0, iclass 29, count 0 2006.257.02:01:05.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:05.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:01:05.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:01:05.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:01:05.56$vck44/vblo=6,719.99 2006.257.02:01:05.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.02:01:05.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.02:01:05.56#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:05.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:05.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:05.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:05.56#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:01:05.56#ibcon#first serial, iclass 31, count 0 2006.257.02:01:05.56#ibcon#enter sib2, iclass 31, count 0 2006.257.02:01:05.56#ibcon#flushed, iclass 31, count 0 2006.257.02:01:05.56#ibcon#about to write, iclass 31, count 0 2006.257.02:01:05.56#ibcon#wrote, iclass 31, count 0 2006.257.02:01:05.56#ibcon#about to read 3, iclass 31, count 0 2006.257.02:01:05.58#ibcon#read 3, iclass 31, count 0 2006.257.02:01:05.58#ibcon#about to read 4, iclass 31, count 0 2006.257.02:01:05.58#ibcon#read 4, iclass 31, count 0 2006.257.02:01:05.58#ibcon#about to read 5, iclass 31, count 0 2006.257.02:01:05.58#ibcon#read 5, iclass 31, count 0 2006.257.02:01:05.58#ibcon#about to read 6, iclass 31, count 0 2006.257.02:01:05.58#ibcon#read 6, iclass 31, count 0 2006.257.02:01:05.58#ibcon#end of sib2, iclass 31, count 0 2006.257.02:01:05.58#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:01:05.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:01:05.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:01:05.58#ibcon#*before write, iclass 31, count 0 2006.257.02:01:05.58#ibcon#enter sib2, iclass 31, count 0 2006.257.02:01:05.58#ibcon#flushed, iclass 31, count 0 2006.257.02:01:05.58#ibcon#about to write, iclass 31, count 0 2006.257.02:01:05.58#ibcon#wrote, iclass 31, count 0 2006.257.02:01:05.58#ibcon#about to read 3, iclass 31, count 0 2006.257.02:01:05.62#ibcon#read 3, iclass 31, count 0 2006.257.02:01:05.62#ibcon#about to read 4, iclass 31, count 0 2006.257.02:01:05.62#ibcon#read 4, iclass 31, count 0 2006.257.02:01:05.62#ibcon#about to read 5, iclass 31, count 0 2006.257.02:01:05.62#ibcon#read 5, iclass 31, count 0 2006.257.02:01:05.62#ibcon#about to read 6, iclass 31, count 0 2006.257.02:01:05.62#ibcon#read 6, iclass 31, count 0 2006.257.02:01:05.62#ibcon#end of sib2, iclass 31, count 0 2006.257.02:01:05.62#ibcon#*after write, iclass 31, count 0 2006.257.02:01:05.62#ibcon#*before return 0, iclass 31, count 0 2006.257.02:01:05.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:05.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:01:05.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:01:05.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:01:05.62$vck44/vb=6,4 2006.257.02:01:05.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.02:01:05.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.02:01:05.62#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:05.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:05.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:05.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:05.68#ibcon#enter wrdev, iclass 33, count 2 2006.257.02:01:05.68#ibcon#first serial, iclass 33, count 2 2006.257.02:01:05.68#ibcon#enter sib2, iclass 33, count 2 2006.257.02:01:05.68#ibcon#flushed, iclass 33, count 2 2006.257.02:01:05.68#ibcon#about to write, iclass 33, count 2 2006.257.02:01:05.68#ibcon#wrote, iclass 33, count 2 2006.257.02:01:05.68#ibcon#about to read 3, iclass 33, count 2 2006.257.02:01:05.70#ibcon#read 3, iclass 33, count 2 2006.257.02:01:05.70#ibcon#about to read 4, iclass 33, count 2 2006.257.02:01:05.70#ibcon#read 4, iclass 33, count 2 2006.257.02:01:05.70#ibcon#about to read 5, iclass 33, count 2 2006.257.02:01:05.70#ibcon#read 5, iclass 33, count 2 2006.257.02:01:05.70#ibcon#about to read 6, iclass 33, count 2 2006.257.02:01:05.70#ibcon#read 6, iclass 33, count 2 2006.257.02:01:05.70#ibcon#end of sib2, iclass 33, count 2 2006.257.02:01:05.70#ibcon#*mode == 0, iclass 33, count 2 2006.257.02:01:05.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.02:01:05.70#ibcon#[27=AT06-04\r\n] 2006.257.02:01:05.70#ibcon#*before write, iclass 33, count 2 2006.257.02:01:05.70#ibcon#enter sib2, iclass 33, count 2 2006.257.02:01:05.70#ibcon#flushed, iclass 33, count 2 2006.257.02:01:05.70#ibcon#about to write, iclass 33, count 2 2006.257.02:01:05.70#ibcon#wrote, iclass 33, count 2 2006.257.02:01:05.70#ibcon#about to read 3, iclass 33, count 2 2006.257.02:01:05.73#ibcon#read 3, iclass 33, count 2 2006.257.02:01:05.73#ibcon#about to read 4, iclass 33, count 2 2006.257.02:01:05.73#ibcon#read 4, iclass 33, count 2 2006.257.02:01:05.73#ibcon#about to read 5, iclass 33, count 2 2006.257.02:01:05.73#ibcon#read 5, iclass 33, count 2 2006.257.02:01:05.73#ibcon#about to read 6, iclass 33, count 2 2006.257.02:01:05.73#ibcon#read 6, iclass 33, count 2 2006.257.02:01:05.73#ibcon#end of sib2, iclass 33, count 2 2006.257.02:01:05.73#ibcon#*after write, iclass 33, count 2 2006.257.02:01:05.73#ibcon#*before return 0, iclass 33, count 2 2006.257.02:01:05.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:05.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:01:05.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.02:01:05.73#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:05.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:05.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:05.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:05.85#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:01:05.85#ibcon#first serial, iclass 33, count 0 2006.257.02:01:05.85#ibcon#enter sib2, iclass 33, count 0 2006.257.02:01:05.85#ibcon#flushed, iclass 33, count 0 2006.257.02:01:05.85#ibcon#about to write, iclass 33, count 0 2006.257.02:01:05.85#ibcon#wrote, iclass 33, count 0 2006.257.02:01:05.85#ibcon#about to read 3, iclass 33, count 0 2006.257.02:01:05.87#ibcon#read 3, iclass 33, count 0 2006.257.02:01:05.87#ibcon#about to read 4, iclass 33, count 0 2006.257.02:01:05.87#ibcon#read 4, iclass 33, count 0 2006.257.02:01:05.87#ibcon#about to read 5, iclass 33, count 0 2006.257.02:01:05.87#ibcon#read 5, iclass 33, count 0 2006.257.02:01:05.87#ibcon#about to read 6, iclass 33, count 0 2006.257.02:01:05.87#ibcon#read 6, iclass 33, count 0 2006.257.02:01:05.87#ibcon#end of sib2, iclass 33, count 0 2006.257.02:01:05.87#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:01:05.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:01:05.87#ibcon#[27=USB\r\n] 2006.257.02:01:05.87#ibcon#*before write, iclass 33, count 0 2006.257.02:01:05.87#ibcon#enter sib2, iclass 33, count 0 2006.257.02:01:05.87#ibcon#flushed, iclass 33, count 0 2006.257.02:01:05.87#ibcon#about to write, iclass 33, count 0 2006.257.02:01:05.87#ibcon#wrote, iclass 33, count 0 2006.257.02:01:05.87#ibcon#about to read 3, iclass 33, count 0 2006.257.02:01:05.90#ibcon#read 3, iclass 33, count 0 2006.257.02:01:05.90#ibcon#about to read 4, iclass 33, count 0 2006.257.02:01:05.90#ibcon#read 4, iclass 33, count 0 2006.257.02:01:05.90#ibcon#about to read 5, iclass 33, count 0 2006.257.02:01:05.90#ibcon#read 5, iclass 33, count 0 2006.257.02:01:05.90#ibcon#about to read 6, iclass 33, count 0 2006.257.02:01:05.90#ibcon#read 6, iclass 33, count 0 2006.257.02:01:05.90#ibcon#end of sib2, iclass 33, count 0 2006.257.02:01:05.90#ibcon#*after write, iclass 33, count 0 2006.257.02:01:05.90#ibcon#*before return 0, iclass 33, count 0 2006.257.02:01:05.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:05.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:01:05.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:01:05.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:01:05.90$vck44/vblo=7,734.99 2006.257.02:01:05.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.02:01:05.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.02:01:05.90#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:05.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:05.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:05.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:05.90#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:01:05.90#ibcon#first serial, iclass 35, count 0 2006.257.02:01:05.90#ibcon#enter sib2, iclass 35, count 0 2006.257.02:01:05.90#ibcon#flushed, iclass 35, count 0 2006.257.02:01:05.90#ibcon#about to write, iclass 35, count 0 2006.257.02:01:05.90#ibcon#wrote, iclass 35, count 0 2006.257.02:01:05.90#ibcon#about to read 3, iclass 35, count 0 2006.257.02:01:05.92#ibcon#read 3, iclass 35, count 0 2006.257.02:01:05.92#ibcon#about to read 4, iclass 35, count 0 2006.257.02:01:05.92#ibcon#read 4, iclass 35, count 0 2006.257.02:01:05.92#ibcon#about to read 5, iclass 35, count 0 2006.257.02:01:05.92#ibcon#read 5, iclass 35, count 0 2006.257.02:01:05.92#ibcon#about to read 6, iclass 35, count 0 2006.257.02:01:05.92#ibcon#read 6, iclass 35, count 0 2006.257.02:01:05.92#ibcon#end of sib2, iclass 35, count 0 2006.257.02:01:05.92#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:01:05.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:01:05.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:01:05.92#ibcon#*before write, iclass 35, count 0 2006.257.02:01:05.92#ibcon#enter sib2, iclass 35, count 0 2006.257.02:01:05.92#ibcon#flushed, iclass 35, count 0 2006.257.02:01:05.92#ibcon#about to write, iclass 35, count 0 2006.257.02:01:05.92#ibcon#wrote, iclass 35, count 0 2006.257.02:01:05.92#ibcon#about to read 3, iclass 35, count 0 2006.257.02:01:05.96#ibcon#read 3, iclass 35, count 0 2006.257.02:01:05.96#ibcon#about to read 4, iclass 35, count 0 2006.257.02:01:05.96#ibcon#read 4, iclass 35, count 0 2006.257.02:01:05.96#ibcon#about to read 5, iclass 35, count 0 2006.257.02:01:05.96#ibcon#read 5, iclass 35, count 0 2006.257.02:01:05.96#ibcon#about to read 6, iclass 35, count 0 2006.257.02:01:05.96#ibcon#read 6, iclass 35, count 0 2006.257.02:01:05.96#ibcon#end of sib2, iclass 35, count 0 2006.257.02:01:05.96#ibcon#*after write, iclass 35, count 0 2006.257.02:01:05.96#ibcon#*before return 0, iclass 35, count 0 2006.257.02:01:05.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:05.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:01:05.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:01:05.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:01:05.96$vck44/vb=7,4 2006.257.02:01:05.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.02:01:05.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.02:01:05.96#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:05.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:06.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:06.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:06.02#ibcon#enter wrdev, iclass 37, count 2 2006.257.02:01:06.02#ibcon#first serial, iclass 37, count 2 2006.257.02:01:06.02#ibcon#enter sib2, iclass 37, count 2 2006.257.02:01:06.02#ibcon#flushed, iclass 37, count 2 2006.257.02:01:06.02#ibcon#about to write, iclass 37, count 2 2006.257.02:01:06.02#ibcon#wrote, iclass 37, count 2 2006.257.02:01:06.02#ibcon#about to read 3, iclass 37, count 2 2006.257.02:01:06.04#ibcon#read 3, iclass 37, count 2 2006.257.02:01:06.04#ibcon#about to read 4, iclass 37, count 2 2006.257.02:01:06.04#ibcon#read 4, iclass 37, count 2 2006.257.02:01:06.04#ibcon#about to read 5, iclass 37, count 2 2006.257.02:01:06.04#ibcon#read 5, iclass 37, count 2 2006.257.02:01:06.04#ibcon#about to read 6, iclass 37, count 2 2006.257.02:01:06.04#ibcon#read 6, iclass 37, count 2 2006.257.02:01:06.04#ibcon#end of sib2, iclass 37, count 2 2006.257.02:01:06.04#ibcon#*mode == 0, iclass 37, count 2 2006.257.02:01:06.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.02:01:06.04#ibcon#[27=AT07-04\r\n] 2006.257.02:01:06.04#ibcon#*before write, iclass 37, count 2 2006.257.02:01:06.04#ibcon#enter sib2, iclass 37, count 2 2006.257.02:01:06.04#ibcon#flushed, iclass 37, count 2 2006.257.02:01:06.04#ibcon#about to write, iclass 37, count 2 2006.257.02:01:06.04#ibcon#wrote, iclass 37, count 2 2006.257.02:01:06.04#ibcon#about to read 3, iclass 37, count 2 2006.257.02:01:06.07#ibcon#read 3, iclass 37, count 2 2006.257.02:01:06.07#ibcon#about to read 4, iclass 37, count 2 2006.257.02:01:06.07#ibcon#read 4, iclass 37, count 2 2006.257.02:01:06.07#ibcon#about to read 5, iclass 37, count 2 2006.257.02:01:06.07#ibcon#read 5, iclass 37, count 2 2006.257.02:01:06.07#ibcon#about to read 6, iclass 37, count 2 2006.257.02:01:06.07#ibcon#read 6, iclass 37, count 2 2006.257.02:01:06.07#ibcon#end of sib2, iclass 37, count 2 2006.257.02:01:06.07#ibcon#*after write, iclass 37, count 2 2006.257.02:01:06.07#ibcon#*before return 0, iclass 37, count 2 2006.257.02:01:06.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:06.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:01:06.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.02:01:06.07#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:06.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:06.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:06.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:06.19#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:01:06.19#ibcon#first serial, iclass 37, count 0 2006.257.02:01:06.19#ibcon#enter sib2, iclass 37, count 0 2006.257.02:01:06.19#ibcon#flushed, iclass 37, count 0 2006.257.02:01:06.19#ibcon#about to write, iclass 37, count 0 2006.257.02:01:06.19#ibcon#wrote, iclass 37, count 0 2006.257.02:01:06.19#ibcon#about to read 3, iclass 37, count 0 2006.257.02:01:06.21#ibcon#read 3, iclass 37, count 0 2006.257.02:01:06.21#ibcon#about to read 4, iclass 37, count 0 2006.257.02:01:06.21#ibcon#read 4, iclass 37, count 0 2006.257.02:01:06.21#ibcon#about to read 5, iclass 37, count 0 2006.257.02:01:06.21#ibcon#read 5, iclass 37, count 0 2006.257.02:01:06.21#ibcon#about to read 6, iclass 37, count 0 2006.257.02:01:06.21#ibcon#read 6, iclass 37, count 0 2006.257.02:01:06.21#ibcon#end of sib2, iclass 37, count 0 2006.257.02:01:06.21#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:01:06.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:01:06.21#ibcon#[27=USB\r\n] 2006.257.02:01:06.21#ibcon#*before write, iclass 37, count 0 2006.257.02:01:06.21#ibcon#enter sib2, iclass 37, count 0 2006.257.02:01:06.21#ibcon#flushed, iclass 37, count 0 2006.257.02:01:06.21#ibcon#about to write, iclass 37, count 0 2006.257.02:01:06.21#ibcon#wrote, iclass 37, count 0 2006.257.02:01:06.21#ibcon#about to read 3, iclass 37, count 0 2006.257.02:01:06.24#ibcon#read 3, iclass 37, count 0 2006.257.02:01:06.24#ibcon#about to read 4, iclass 37, count 0 2006.257.02:01:06.24#ibcon#read 4, iclass 37, count 0 2006.257.02:01:06.24#ibcon#about to read 5, iclass 37, count 0 2006.257.02:01:06.24#ibcon#read 5, iclass 37, count 0 2006.257.02:01:06.24#ibcon#about to read 6, iclass 37, count 0 2006.257.02:01:06.24#ibcon#read 6, iclass 37, count 0 2006.257.02:01:06.24#ibcon#end of sib2, iclass 37, count 0 2006.257.02:01:06.24#ibcon#*after write, iclass 37, count 0 2006.257.02:01:06.24#ibcon#*before return 0, iclass 37, count 0 2006.257.02:01:06.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:06.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:01:06.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:01:06.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:01:06.24$vck44/vblo=8,744.99 2006.257.02:01:06.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.02:01:06.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.02:01:06.24#ibcon#ireg 17 cls_cnt 0 2006.257.02:01:06.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:06.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:06.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:06.24#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:01:06.24#ibcon#first serial, iclass 39, count 0 2006.257.02:01:06.24#ibcon#enter sib2, iclass 39, count 0 2006.257.02:01:06.24#ibcon#flushed, iclass 39, count 0 2006.257.02:01:06.24#ibcon#about to write, iclass 39, count 0 2006.257.02:01:06.24#ibcon#wrote, iclass 39, count 0 2006.257.02:01:06.24#ibcon#about to read 3, iclass 39, count 0 2006.257.02:01:06.26#ibcon#read 3, iclass 39, count 0 2006.257.02:01:06.26#ibcon#about to read 4, iclass 39, count 0 2006.257.02:01:06.26#ibcon#read 4, iclass 39, count 0 2006.257.02:01:06.26#ibcon#about to read 5, iclass 39, count 0 2006.257.02:01:06.26#ibcon#read 5, iclass 39, count 0 2006.257.02:01:06.26#ibcon#about to read 6, iclass 39, count 0 2006.257.02:01:06.26#ibcon#read 6, iclass 39, count 0 2006.257.02:01:06.26#ibcon#end of sib2, iclass 39, count 0 2006.257.02:01:06.26#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:01:06.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:01:06.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:01:06.26#ibcon#*before write, iclass 39, count 0 2006.257.02:01:06.26#ibcon#enter sib2, iclass 39, count 0 2006.257.02:01:06.26#ibcon#flushed, iclass 39, count 0 2006.257.02:01:06.26#ibcon#about to write, iclass 39, count 0 2006.257.02:01:06.26#ibcon#wrote, iclass 39, count 0 2006.257.02:01:06.26#ibcon#about to read 3, iclass 39, count 0 2006.257.02:01:06.30#ibcon#read 3, iclass 39, count 0 2006.257.02:01:06.30#ibcon#about to read 4, iclass 39, count 0 2006.257.02:01:06.30#ibcon#read 4, iclass 39, count 0 2006.257.02:01:06.30#ibcon#about to read 5, iclass 39, count 0 2006.257.02:01:06.30#ibcon#read 5, iclass 39, count 0 2006.257.02:01:06.30#ibcon#about to read 6, iclass 39, count 0 2006.257.02:01:06.30#ibcon#read 6, iclass 39, count 0 2006.257.02:01:06.30#ibcon#end of sib2, iclass 39, count 0 2006.257.02:01:06.30#ibcon#*after write, iclass 39, count 0 2006.257.02:01:06.30#ibcon#*before return 0, iclass 39, count 0 2006.257.02:01:06.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:06.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:01:06.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:01:06.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:01:06.31$vck44/vb=8,4 2006.257.02:01:06.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.02:01:06.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.02:01:06.31#ibcon#ireg 11 cls_cnt 2 2006.257.02:01:06.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:06.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:06.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:06.35#ibcon#enter wrdev, iclass 3, count 2 2006.257.02:01:06.35#ibcon#first serial, iclass 3, count 2 2006.257.02:01:06.35#ibcon#enter sib2, iclass 3, count 2 2006.257.02:01:06.35#ibcon#flushed, iclass 3, count 2 2006.257.02:01:06.35#ibcon#about to write, iclass 3, count 2 2006.257.02:01:06.35#ibcon#wrote, iclass 3, count 2 2006.257.02:01:06.35#ibcon#about to read 3, iclass 3, count 2 2006.257.02:01:06.37#ibcon#read 3, iclass 3, count 2 2006.257.02:01:06.37#ibcon#about to read 4, iclass 3, count 2 2006.257.02:01:06.37#ibcon#read 4, iclass 3, count 2 2006.257.02:01:06.37#ibcon#about to read 5, iclass 3, count 2 2006.257.02:01:06.37#ibcon#read 5, iclass 3, count 2 2006.257.02:01:06.37#ibcon#about to read 6, iclass 3, count 2 2006.257.02:01:06.37#ibcon#read 6, iclass 3, count 2 2006.257.02:01:06.37#ibcon#end of sib2, iclass 3, count 2 2006.257.02:01:06.37#ibcon#*mode == 0, iclass 3, count 2 2006.257.02:01:06.37#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.02:01:06.37#ibcon#[27=AT08-04\r\n] 2006.257.02:01:06.37#ibcon#*before write, iclass 3, count 2 2006.257.02:01:06.37#ibcon#enter sib2, iclass 3, count 2 2006.257.02:01:06.37#ibcon#flushed, iclass 3, count 2 2006.257.02:01:06.37#ibcon#about to write, iclass 3, count 2 2006.257.02:01:06.37#ibcon#wrote, iclass 3, count 2 2006.257.02:01:06.37#ibcon#about to read 3, iclass 3, count 2 2006.257.02:01:06.40#ibcon#read 3, iclass 3, count 2 2006.257.02:01:06.40#ibcon#about to read 4, iclass 3, count 2 2006.257.02:01:06.40#ibcon#read 4, iclass 3, count 2 2006.257.02:01:06.40#ibcon#about to read 5, iclass 3, count 2 2006.257.02:01:06.40#ibcon#read 5, iclass 3, count 2 2006.257.02:01:06.40#ibcon#about to read 6, iclass 3, count 2 2006.257.02:01:06.40#ibcon#read 6, iclass 3, count 2 2006.257.02:01:06.40#ibcon#end of sib2, iclass 3, count 2 2006.257.02:01:06.40#ibcon#*after write, iclass 3, count 2 2006.257.02:01:06.40#ibcon#*before return 0, iclass 3, count 2 2006.257.02:01:06.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:06.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:01:06.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.02:01:06.40#ibcon#ireg 7 cls_cnt 0 2006.257.02:01:06.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:06.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:06.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:06.52#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:01:06.52#ibcon#first serial, iclass 3, count 0 2006.257.02:01:06.52#ibcon#enter sib2, iclass 3, count 0 2006.257.02:01:06.52#ibcon#flushed, iclass 3, count 0 2006.257.02:01:06.52#ibcon#about to write, iclass 3, count 0 2006.257.02:01:06.52#ibcon#wrote, iclass 3, count 0 2006.257.02:01:06.52#ibcon#about to read 3, iclass 3, count 0 2006.257.02:01:06.54#ibcon#read 3, iclass 3, count 0 2006.257.02:01:06.54#ibcon#about to read 4, iclass 3, count 0 2006.257.02:01:06.54#ibcon#read 4, iclass 3, count 0 2006.257.02:01:06.54#ibcon#about to read 5, iclass 3, count 0 2006.257.02:01:06.54#ibcon#read 5, iclass 3, count 0 2006.257.02:01:06.54#ibcon#about to read 6, iclass 3, count 0 2006.257.02:01:06.54#ibcon#read 6, iclass 3, count 0 2006.257.02:01:06.54#ibcon#end of sib2, iclass 3, count 0 2006.257.02:01:06.54#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:01:06.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:01:06.54#ibcon#[27=USB\r\n] 2006.257.02:01:06.54#ibcon#*before write, iclass 3, count 0 2006.257.02:01:06.54#ibcon#enter sib2, iclass 3, count 0 2006.257.02:01:06.54#ibcon#flushed, iclass 3, count 0 2006.257.02:01:06.54#ibcon#about to write, iclass 3, count 0 2006.257.02:01:06.54#ibcon#wrote, iclass 3, count 0 2006.257.02:01:06.54#ibcon#about to read 3, iclass 3, count 0 2006.257.02:01:06.57#ibcon#read 3, iclass 3, count 0 2006.257.02:01:06.57#ibcon#about to read 4, iclass 3, count 0 2006.257.02:01:06.57#ibcon#read 4, iclass 3, count 0 2006.257.02:01:06.57#ibcon#about to read 5, iclass 3, count 0 2006.257.02:01:06.57#ibcon#read 5, iclass 3, count 0 2006.257.02:01:06.57#ibcon#about to read 6, iclass 3, count 0 2006.257.02:01:06.57#ibcon#read 6, iclass 3, count 0 2006.257.02:01:06.57#ibcon#end of sib2, iclass 3, count 0 2006.257.02:01:06.57#ibcon#*after write, iclass 3, count 0 2006.257.02:01:06.57#ibcon#*before return 0, iclass 3, count 0 2006.257.02:01:06.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:06.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:01:06.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:01:06.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:01:06.57$vck44/vabw=wide 2006.257.02:01:06.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.02:01:06.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.02:01:06.57#ibcon#ireg 8 cls_cnt 0 2006.257.02:01:06.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:06.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:06.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:06.57#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:01:06.57#ibcon#first serial, iclass 5, count 0 2006.257.02:01:06.57#ibcon#enter sib2, iclass 5, count 0 2006.257.02:01:06.57#ibcon#flushed, iclass 5, count 0 2006.257.02:01:06.57#ibcon#about to write, iclass 5, count 0 2006.257.02:01:06.57#ibcon#wrote, iclass 5, count 0 2006.257.02:01:06.57#ibcon#about to read 3, iclass 5, count 0 2006.257.02:01:06.59#ibcon#read 3, iclass 5, count 0 2006.257.02:01:06.59#ibcon#about to read 4, iclass 5, count 0 2006.257.02:01:06.59#ibcon#read 4, iclass 5, count 0 2006.257.02:01:06.59#ibcon#about to read 5, iclass 5, count 0 2006.257.02:01:06.59#ibcon#read 5, iclass 5, count 0 2006.257.02:01:06.59#ibcon#about to read 6, iclass 5, count 0 2006.257.02:01:06.59#ibcon#read 6, iclass 5, count 0 2006.257.02:01:06.59#ibcon#end of sib2, iclass 5, count 0 2006.257.02:01:06.59#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:01:06.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:01:06.59#ibcon#[25=BW32\r\n] 2006.257.02:01:06.59#ibcon#*before write, iclass 5, count 0 2006.257.02:01:06.59#ibcon#enter sib2, iclass 5, count 0 2006.257.02:01:06.59#ibcon#flushed, iclass 5, count 0 2006.257.02:01:06.59#ibcon#about to write, iclass 5, count 0 2006.257.02:01:06.59#ibcon#wrote, iclass 5, count 0 2006.257.02:01:06.59#ibcon#about to read 3, iclass 5, count 0 2006.257.02:01:06.62#ibcon#read 3, iclass 5, count 0 2006.257.02:01:06.62#ibcon#about to read 4, iclass 5, count 0 2006.257.02:01:06.62#ibcon#read 4, iclass 5, count 0 2006.257.02:01:06.62#ibcon#about to read 5, iclass 5, count 0 2006.257.02:01:06.62#ibcon#read 5, iclass 5, count 0 2006.257.02:01:06.62#ibcon#about to read 6, iclass 5, count 0 2006.257.02:01:06.62#ibcon#read 6, iclass 5, count 0 2006.257.02:01:06.62#ibcon#end of sib2, iclass 5, count 0 2006.257.02:01:06.62#ibcon#*after write, iclass 5, count 0 2006.257.02:01:06.62#ibcon#*before return 0, iclass 5, count 0 2006.257.02:01:06.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:06.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:01:06.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:01:06.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:01:06.62$vck44/vbbw=wide 2006.257.02:01:06.62#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.02:01:06.62#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.02:01:06.62#ibcon#ireg 8 cls_cnt 0 2006.257.02:01:06.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:01:06.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:01:06.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:01:06.69#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:01:06.69#ibcon#first serial, iclass 7, count 0 2006.257.02:01:06.69#ibcon#enter sib2, iclass 7, count 0 2006.257.02:01:06.69#ibcon#flushed, iclass 7, count 0 2006.257.02:01:06.69#ibcon#about to write, iclass 7, count 0 2006.257.02:01:06.69#ibcon#wrote, iclass 7, count 0 2006.257.02:01:06.69#ibcon#about to read 3, iclass 7, count 0 2006.257.02:01:06.71#ibcon#read 3, iclass 7, count 0 2006.257.02:01:06.71#ibcon#about to read 4, iclass 7, count 0 2006.257.02:01:06.71#ibcon#read 4, iclass 7, count 0 2006.257.02:01:06.71#ibcon#about to read 5, iclass 7, count 0 2006.257.02:01:06.71#ibcon#read 5, iclass 7, count 0 2006.257.02:01:06.71#ibcon#about to read 6, iclass 7, count 0 2006.257.02:01:06.71#ibcon#read 6, iclass 7, count 0 2006.257.02:01:06.71#ibcon#end of sib2, iclass 7, count 0 2006.257.02:01:06.71#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:01:06.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:01:06.71#ibcon#[27=BW32\r\n] 2006.257.02:01:06.71#ibcon#*before write, iclass 7, count 0 2006.257.02:01:06.71#ibcon#enter sib2, iclass 7, count 0 2006.257.02:01:06.71#ibcon#flushed, iclass 7, count 0 2006.257.02:01:06.71#ibcon#about to write, iclass 7, count 0 2006.257.02:01:06.71#ibcon#wrote, iclass 7, count 0 2006.257.02:01:06.71#ibcon#about to read 3, iclass 7, count 0 2006.257.02:01:06.74#ibcon#read 3, iclass 7, count 0 2006.257.02:01:06.74#ibcon#about to read 4, iclass 7, count 0 2006.257.02:01:06.74#ibcon#read 4, iclass 7, count 0 2006.257.02:01:06.74#ibcon#about to read 5, iclass 7, count 0 2006.257.02:01:06.74#ibcon#read 5, iclass 7, count 0 2006.257.02:01:06.74#ibcon#about to read 6, iclass 7, count 0 2006.257.02:01:06.74#ibcon#read 6, iclass 7, count 0 2006.257.02:01:06.74#ibcon#end of sib2, iclass 7, count 0 2006.257.02:01:06.74#ibcon#*after write, iclass 7, count 0 2006.257.02:01:06.74#ibcon#*before return 0, iclass 7, count 0 2006.257.02:01:06.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:01:06.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:01:06.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:01:06.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:01:06.74$setupk4/ifdk4 2006.257.02:01:06.74$ifdk4/lo= 2006.257.02:01:06.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:01:06.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:01:06.74$ifdk4/patch= 2006.257.02:01:06.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:01:06.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:01:06.74$setupk4/!*+20s 2006.257.02:01:14.21#abcon#<5=/03 3.0 8.4 17.891001011.8\r\n> 2006.257.02:01:14.23#abcon#{5=INTERFACE CLEAR} 2006.257.02:01:14.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:01:21.26$setupk4/"tpicd 2006.257.02:01:21.26$setupk4/echo=off 2006.257.02:01:21.26$setupk4/xlog=off 2006.257.02:01:21.26:!2006.257.02:03:55 2006.257.02:01:41.14#trakl#Source acquired 2006.257.02:01:43.14#flagr#flagr/antenna,acquired 2006.257.02:02:24.13#trakl#Off source 2006.257.02:02:24.13?ERROR st -7 Antenna off-source! 2006.257.02:02:24.13#trakl#az 57.160 el 24.034 azerr*cos(el) 0.0162 elerr 0.0002 2006.257.02:02:25.13#flagr#flagr/antenna,off-source 2006.257.02:02:31.13#trakl#Source re-acquired 2006.257.02:02:31.13#flagr#flagr/antenna,re-acquired 2006.257.02:03:55.00:preob 2006.257.02:03:56.13/onsource/TRACKING 2006.257.02:03:56.13:!2006.257.02:04:05 2006.257.02:04:05.00:"tape 2006.257.02:04:05.00:"st=record 2006.257.02:04:05.00:data_valid=on 2006.257.02:04:05.00:midob 2006.257.02:04:05.14/onsource/TRACKING 2006.257.02:04:05.14/wx/17.81,1011.8,99 2006.257.02:04:05.35/cable/+6.4868E-03 2006.257.02:04:06.44/va/01,08,usb,yes,33,36 2006.257.02:04:06.44/va/02,07,usb,yes,36,37 2006.257.02:04:06.44/va/03,08,usb,yes,32,34 2006.257.02:04:06.44/va/04,07,usb,yes,37,39 2006.257.02:04:06.44/va/05,04,usb,yes,33,34 2006.257.02:04:06.44/va/06,04,usb,yes,37,37 2006.257.02:04:06.44/va/07,04,usb,yes,38,39 2006.257.02:04:06.44/va/08,04,usb,yes,32,39 2006.257.02:04:06.67/valo/01,524.99,yes,locked 2006.257.02:04:06.67/valo/02,534.99,yes,locked 2006.257.02:04:06.67/valo/03,564.99,yes,locked 2006.257.02:04:06.67/valo/04,624.99,yes,locked 2006.257.02:04:06.67/valo/05,734.99,yes,locked 2006.257.02:04:06.67/valo/06,814.99,yes,locked 2006.257.02:04:06.67/valo/07,864.99,yes,locked 2006.257.02:04:06.67/valo/08,884.99,yes,locked 2006.257.02:04:07.76/vb/01,04,usb,yes,32,29 2006.257.02:04:07.76/vb/02,05,usb,yes,30,30 2006.257.02:04:07.76/vb/03,04,usb,yes,31,34 2006.257.02:04:07.76/vb/04,05,usb,yes,31,30 2006.257.02:04:07.76/vb/05,04,usb,yes,28,30 2006.257.02:04:07.76/vb/06,04,usb,yes,32,28 2006.257.02:04:07.76/vb/07,04,usb,yes,32,32 2006.257.02:04:07.76/vb/08,04,usb,yes,29,33 2006.257.02:04:07.99/vblo/01,629.99,yes,locked 2006.257.02:04:07.99/vblo/02,634.99,yes,locked 2006.257.02:04:07.99/vblo/03,649.99,yes,locked 2006.257.02:04:07.99/vblo/04,679.99,yes,locked 2006.257.02:04:07.99/vblo/05,709.99,yes,locked 2006.257.02:04:07.99/vblo/06,719.99,yes,locked 2006.257.02:04:07.99/vblo/07,734.99,yes,locked 2006.257.02:04:07.99/vblo/08,744.99,yes,locked 2006.257.02:04:08.14/vabw/8 2006.257.02:04:08.29/vbbw/8 2006.257.02:04:08.45/xfe/off,on,15.0 2006.257.02:04:08.82/ifatt/23,28,28,28 2006.257.02:04:09.08/fmout-gps/S +4.51E-07 2006.257.02:04:09.12:!2006.257.02:04:45 2006.257.02:04:45.00:data_valid=off 2006.257.02:04:45.01:"et 2006.257.02:04:45.01:!+3s 2006.257.02:04:48.02:"tape 2006.257.02:04:48.03:postob 2006.257.02:04:48.12/cable/+6.4867E-03 2006.257.02:04:48.13/wx/17.80,1011.8,100 2006.257.02:04:48.21/fmout-gps/S +4.52E-07 2006.257.02:04:48.21:scan_name=257-0206,jd0609,80 2006.257.02:04:48.22:source=3c274,123049.42,122328.0,2000.0,cw 2006.257.02:04:50.14#flagr#flagr/antenna,new-source 2006.257.02:04:50.15:checkk5 2006.257.02:04:50.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:04:51.00/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:04:51.42/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:04:51.88/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:04:52.25/chk_obsdata//k5ts1/T2570204??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.02:04:52.65/chk_obsdata//k5ts2/T2570204??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.02:04:53.09/chk_obsdata//k5ts3/T2570204??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.02:04:53.53/chk_obsdata//k5ts4/T2570204??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.02:04:54.26/k5log//k5ts1_log_newline 2006.257.02:04:55.04/k5log//k5ts2_log_newline 2006.257.02:04:55.83/k5log//k5ts3_log_newline 2006.257.02:04:57.08/k5log//k5ts4_log_newline 2006.257.02:04:57.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:04:57.11:setupk4=1 2006.257.02:04:57.11$setupk4/echo=on 2006.257.02:04:57.11$setupk4/pcalon 2006.257.02:04:57.11$pcalon/"no phase cal control is implemented here 2006.257.02:04:57.11$setupk4/"tpicd=stop 2006.257.02:04:57.11$setupk4/"rec=synch_on 2006.257.02:04:57.11$setupk4/"rec_mode=128 2006.257.02:04:57.11$setupk4/!* 2006.257.02:04:57.11$setupk4/recpk4 2006.257.02:04:57.11$recpk4/recpatch= 2006.257.02:04:57.11$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:04:57.11$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:04:57.11$setupk4/vck44 2006.257.02:04:57.11$vck44/valo=1,524.99 2006.257.02:04:57.11#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.02:04:57.11#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.02:04:57.11#ibcon#ireg 17 cls_cnt 0 2006.257.02:04:57.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:57.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:57.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:57.11#ibcon#enter wrdev, iclass 32, count 0 2006.257.02:04:57.11#ibcon#first serial, iclass 32, count 0 2006.257.02:04:57.11#ibcon#enter sib2, iclass 32, count 0 2006.257.02:04:57.11#ibcon#flushed, iclass 32, count 0 2006.257.02:04:57.11#ibcon#about to write, iclass 32, count 0 2006.257.02:04:57.11#ibcon#wrote, iclass 32, count 0 2006.257.02:04:57.11#ibcon#about to read 3, iclass 32, count 0 2006.257.02:04:57.16#ibcon#read 3, iclass 32, count 0 2006.257.02:04:57.16#ibcon#about to read 4, iclass 32, count 0 2006.257.02:04:57.16#ibcon#read 4, iclass 32, count 0 2006.257.02:04:57.16#ibcon#about to read 5, iclass 32, count 0 2006.257.02:04:57.16#ibcon#read 5, iclass 32, count 0 2006.257.02:04:57.16#ibcon#about to read 6, iclass 32, count 0 2006.257.02:04:57.16#ibcon#read 6, iclass 32, count 0 2006.257.02:04:57.16#ibcon#end of sib2, iclass 32, count 0 2006.257.02:04:57.16#ibcon#*mode == 0, iclass 32, count 0 2006.257.02:04:57.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.02:04:57.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:04:57.16#ibcon#*before write, iclass 32, count 0 2006.257.02:04:57.16#ibcon#enter sib2, iclass 32, count 0 2006.257.02:04:57.16#ibcon#flushed, iclass 32, count 0 2006.257.02:04:57.16#ibcon#about to write, iclass 32, count 0 2006.257.02:04:57.16#ibcon#wrote, iclass 32, count 0 2006.257.02:04:57.16#ibcon#about to read 3, iclass 32, count 0 2006.257.02:04:57.20#ibcon#read 3, iclass 32, count 0 2006.257.02:04:57.20#ibcon#about to read 4, iclass 32, count 0 2006.257.02:04:57.20#ibcon#read 4, iclass 32, count 0 2006.257.02:04:57.20#ibcon#about to read 5, iclass 32, count 0 2006.257.02:04:57.20#ibcon#read 5, iclass 32, count 0 2006.257.02:04:57.20#ibcon#about to read 6, iclass 32, count 0 2006.257.02:04:57.20#ibcon#read 6, iclass 32, count 0 2006.257.02:04:57.20#ibcon#end of sib2, iclass 32, count 0 2006.257.02:04:57.20#ibcon#*after write, iclass 32, count 0 2006.257.02:04:57.20#ibcon#*before return 0, iclass 32, count 0 2006.257.02:04:57.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:57.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:57.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.02:04:57.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.02:04:57.20$vck44/va=1,8 2006.257.02:04:57.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.02:04:57.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.02:04:57.20#ibcon#ireg 11 cls_cnt 2 2006.257.02:04:57.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:57.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:57.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:57.20#ibcon#enter wrdev, iclass 34, count 2 2006.257.02:04:57.20#ibcon#first serial, iclass 34, count 2 2006.257.02:04:57.20#ibcon#enter sib2, iclass 34, count 2 2006.257.02:04:57.20#ibcon#flushed, iclass 34, count 2 2006.257.02:04:57.20#ibcon#about to write, iclass 34, count 2 2006.257.02:04:57.20#ibcon#wrote, iclass 34, count 2 2006.257.02:04:57.20#ibcon#about to read 3, iclass 34, count 2 2006.257.02:04:57.23#ibcon#read 3, iclass 34, count 2 2006.257.02:04:57.23#ibcon#about to read 4, iclass 34, count 2 2006.257.02:04:57.23#ibcon#read 4, iclass 34, count 2 2006.257.02:04:57.23#ibcon#about to read 5, iclass 34, count 2 2006.257.02:04:57.23#ibcon#read 5, iclass 34, count 2 2006.257.02:04:57.23#ibcon#about to read 6, iclass 34, count 2 2006.257.02:04:57.23#ibcon#read 6, iclass 34, count 2 2006.257.02:04:57.23#ibcon#end of sib2, iclass 34, count 2 2006.257.02:04:57.23#ibcon#*mode == 0, iclass 34, count 2 2006.257.02:04:57.23#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.02:04:57.23#ibcon#[25=AT01-08\r\n] 2006.257.02:04:57.23#ibcon#*before write, iclass 34, count 2 2006.257.02:04:57.23#ibcon#enter sib2, iclass 34, count 2 2006.257.02:04:57.23#ibcon#flushed, iclass 34, count 2 2006.257.02:04:57.23#ibcon#about to write, iclass 34, count 2 2006.257.02:04:57.23#ibcon#wrote, iclass 34, count 2 2006.257.02:04:57.23#ibcon#about to read 3, iclass 34, count 2 2006.257.02:04:57.26#ibcon#read 3, iclass 34, count 2 2006.257.02:04:57.26#ibcon#about to read 4, iclass 34, count 2 2006.257.02:04:57.26#ibcon#read 4, iclass 34, count 2 2006.257.02:04:57.26#ibcon#about to read 5, iclass 34, count 2 2006.257.02:04:57.26#ibcon#read 5, iclass 34, count 2 2006.257.02:04:57.26#ibcon#about to read 6, iclass 34, count 2 2006.257.02:04:57.26#ibcon#read 6, iclass 34, count 2 2006.257.02:04:57.26#ibcon#end of sib2, iclass 34, count 2 2006.257.02:04:57.26#ibcon#*after write, iclass 34, count 2 2006.257.02:04:57.26#ibcon#*before return 0, iclass 34, count 2 2006.257.02:04:57.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:57.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:57.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.02:04:57.26#ibcon#ireg 7 cls_cnt 0 2006.257.02:04:57.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:04:57.38#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:04:57.38#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:04:57.38#ibcon#enter wrdev, iclass 34, count 0 2006.257.02:04:57.38#ibcon#first serial, iclass 34, count 0 2006.257.02:04:57.38#ibcon#enter sib2, iclass 34, count 0 2006.257.02:04:57.38#ibcon#flushed, iclass 34, count 0 2006.257.02:04:57.38#ibcon#about to write, iclass 34, count 0 2006.257.02:04:57.38#ibcon#wrote, iclass 34, count 0 2006.257.02:04:57.38#ibcon#about to read 3, iclass 34, count 0 2006.257.02:04:57.40#ibcon#read 3, iclass 34, count 0 2006.257.02:04:57.40#ibcon#about to read 4, iclass 34, count 0 2006.257.02:04:57.40#ibcon#read 4, iclass 34, count 0 2006.257.02:04:57.40#ibcon#about to read 5, iclass 34, count 0 2006.257.02:04:57.40#ibcon#read 5, iclass 34, count 0 2006.257.02:04:57.40#ibcon#about to read 6, iclass 34, count 0 2006.257.02:04:57.40#ibcon#read 6, iclass 34, count 0 2006.257.02:04:57.40#ibcon#end of sib2, iclass 34, count 0 2006.257.02:04:57.40#ibcon#*mode == 0, iclass 34, count 0 2006.257.02:04:57.40#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.02:04:57.40#ibcon#[25=USB\r\n] 2006.257.02:04:57.40#ibcon#*before write, iclass 34, count 0 2006.257.02:04:57.40#ibcon#enter sib2, iclass 34, count 0 2006.257.02:04:57.40#ibcon#flushed, iclass 34, count 0 2006.257.02:04:57.40#ibcon#about to write, iclass 34, count 0 2006.257.02:04:57.40#ibcon#wrote, iclass 34, count 0 2006.257.02:04:57.40#ibcon#about to read 3, iclass 34, count 0 2006.257.02:04:57.43#ibcon#read 3, iclass 34, count 0 2006.257.02:04:57.43#ibcon#about to read 4, iclass 34, count 0 2006.257.02:04:57.43#ibcon#read 4, iclass 34, count 0 2006.257.02:04:57.43#ibcon#about to read 5, iclass 34, count 0 2006.257.02:04:57.43#ibcon#read 5, iclass 34, count 0 2006.257.02:04:57.43#ibcon#about to read 6, iclass 34, count 0 2006.257.02:04:57.43#ibcon#read 6, iclass 34, count 0 2006.257.02:04:57.43#ibcon#end of sib2, iclass 34, count 0 2006.257.02:04:57.43#ibcon#*after write, iclass 34, count 0 2006.257.02:04:57.43#ibcon#*before return 0, iclass 34, count 0 2006.257.02:04:57.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:04:57.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:04:57.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.02:04:57.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.02:04:57.43$vck44/valo=2,534.99 2006.257.02:04:57.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.02:04:57.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.02:04:57.43#ibcon#ireg 17 cls_cnt 0 2006.257.02:04:57.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:04:57.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:04:57.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:04:57.43#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:04:57.43#ibcon#first serial, iclass 36, count 0 2006.257.02:04:57.43#ibcon#enter sib2, iclass 36, count 0 2006.257.02:04:57.43#ibcon#flushed, iclass 36, count 0 2006.257.02:04:57.43#ibcon#about to write, iclass 36, count 0 2006.257.02:04:57.43#ibcon#wrote, iclass 36, count 0 2006.257.02:04:57.43#ibcon#about to read 3, iclass 36, count 0 2006.257.02:04:57.46#ibcon#read 3, iclass 36, count 0 2006.257.02:04:57.46#ibcon#about to read 4, iclass 36, count 0 2006.257.02:04:57.46#ibcon#read 4, iclass 36, count 0 2006.257.02:04:57.46#ibcon#about to read 5, iclass 36, count 0 2006.257.02:04:57.46#ibcon#read 5, iclass 36, count 0 2006.257.02:04:57.46#ibcon#about to read 6, iclass 36, count 0 2006.257.02:04:57.46#ibcon#read 6, iclass 36, count 0 2006.257.02:04:57.46#ibcon#end of sib2, iclass 36, count 0 2006.257.02:04:57.46#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:04:57.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:04:57.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:04:57.46#ibcon#*before write, iclass 36, count 0 2006.257.02:04:57.46#ibcon#enter sib2, iclass 36, count 0 2006.257.02:04:57.46#ibcon#flushed, iclass 36, count 0 2006.257.02:04:57.46#ibcon#about to write, iclass 36, count 0 2006.257.02:04:57.46#ibcon#wrote, iclass 36, count 0 2006.257.02:04:57.46#ibcon#about to read 3, iclass 36, count 0 2006.257.02:04:57.50#ibcon#read 3, iclass 36, count 0 2006.257.02:04:57.50#ibcon#about to read 4, iclass 36, count 0 2006.257.02:04:57.50#ibcon#read 4, iclass 36, count 0 2006.257.02:04:57.50#ibcon#about to read 5, iclass 36, count 0 2006.257.02:04:57.50#ibcon#read 5, iclass 36, count 0 2006.257.02:04:57.50#ibcon#about to read 6, iclass 36, count 0 2006.257.02:04:57.50#ibcon#read 6, iclass 36, count 0 2006.257.02:04:57.50#ibcon#end of sib2, iclass 36, count 0 2006.257.02:04:57.50#ibcon#*after write, iclass 36, count 0 2006.257.02:04:57.50#ibcon#*before return 0, iclass 36, count 0 2006.257.02:04:57.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:04:57.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:04:57.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:04:57.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:04:57.50$vck44/va=2,7 2006.257.02:04:57.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.02:04:57.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.02:04:57.50#ibcon#ireg 11 cls_cnt 2 2006.257.02:04:57.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:04:57.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:04:57.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:04:57.55#ibcon#enter wrdev, iclass 38, count 2 2006.257.02:04:57.55#ibcon#first serial, iclass 38, count 2 2006.257.02:04:57.55#ibcon#enter sib2, iclass 38, count 2 2006.257.02:04:57.55#ibcon#flushed, iclass 38, count 2 2006.257.02:04:57.55#ibcon#about to write, iclass 38, count 2 2006.257.02:04:57.55#ibcon#wrote, iclass 38, count 2 2006.257.02:04:57.55#ibcon#about to read 3, iclass 38, count 2 2006.257.02:04:57.57#ibcon#read 3, iclass 38, count 2 2006.257.02:04:57.57#ibcon#about to read 4, iclass 38, count 2 2006.257.02:04:57.57#ibcon#read 4, iclass 38, count 2 2006.257.02:04:57.57#ibcon#about to read 5, iclass 38, count 2 2006.257.02:04:57.57#ibcon#read 5, iclass 38, count 2 2006.257.02:04:57.57#ibcon#about to read 6, iclass 38, count 2 2006.257.02:04:57.57#ibcon#read 6, iclass 38, count 2 2006.257.02:04:57.57#ibcon#end of sib2, iclass 38, count 2 2006.257.02:04:57.57#ibcon#*mode == 0, iclass 38, count 2 2006.257.02:04:57.57#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.02:04:57.57#ibcon#[25=AT02-07\r\n] 2006.257.02:04:57.57#ibcon#*before write, iclass 38, count 2 2006.257.02:04:57.57#ibcon#enter sib2, iclass 38, count 2 2006.257.02:04:57.57#ibcon#flushed, iclass 38, count 2 2006.257.02:04:57.57#ibcon#about to write, iclass 38, count 2 2006.257.02:04:57.57#ibcon#wrote, iclass 38, count 2 2006.257.02:04:57.57#ibcon#about to read 3, iclass 38, count 2 2006.257.02:04:57.60#ibcon#read 3, iclass 38, count 2 2006.257.02:04:57.60#ibcon#about to read 4, iclass 38, count 2 2006.257.02:04:57.60#ibcon#read 4, iclass 38, count 2 2006.257.02:04:57.60#ibcon#about to read 5, iclass 38, count 2 2006.257.02:04:57.60#ibcon#read 5, iclass 38, count 2 2006.257.02:04:57.60#ibcon#about to read 6, iclass 38, count 2 2006.257.02:04:57.60#ibcon#read 6, iclass 38, count 2 2006.257.02:04:57.60#ibcon#end of sib2, iclass 38, count 2 2006.257.02:04:57.60#ibcon#*after write, iclass 38, count 2 2006.257.02:04:57.60#ibcon#*before return 0, iclass 38, count 2 2006.257.02:04:57.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:04:57.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:04:57.60#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.02:04:57.60#ibcon#ireg 7 cls_cnt 0 2006.257.02:04:57.60#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:04:57.72#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:04:57.72#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:04:57.72#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:04:57.72#ibcon#first serial, iclass 38, count 0 2006.257.02:04:57.72#ibcon#enter sib2, iclass 38, count 0 2006.257.02:04:57.72#ibcon#flushed, iclass 38, count 0 2006.257.02:04:57.72#ibcon#about to write, iclass 38, count 0 2006.257.02:04:57.72#ibcon#wrote, iclass 38, count 0 2006.257.02:04:57.72#ibcon#about to read 3, iclass 38, count 0 2006.257.02:04:57.74#ibcon#read 3, iclass 38, count 0 2006.257.02:04:57.74#ibcon#about to read 4, iclass 38, count 0 2006.257.02:04:57.74#ibcon#read 4, iclass 38, count 0 2006.257.02:04:57.74#ibcon#about to read 5, iclass 38, count 0 2006.257.02:04:57.74#ibcon#read 5, iclass 38, count 0 2006.257.02:04:57.74#ibcon#about to read 6, iclass 38, count 0 2006.257.02:04:57.74#ibcon#read 6, iclass 38, count 0 2006.257.02:04:57.74#ibcon#end of sib2, iclass 38, count 0 2006.257.02:04:57.74#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:04:57.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:04:57.74#ibcon#[25=USB\r\n] 2006.257.02:04:57.74#ibcon#*before write, iclass 38, count 0 2006.257.02:04:57.74#ibcon#enter sib2, iclass 38, count 0 2006.257.02:04:57.74#ibcon#flushed, iclass 38, count 0 2006.257.02:04:57.74#ibcon#about to write, iclass 38, count 0 2006.257.02:04:57.74#ibcon#wrote, iclass 38, count 0 2006.257.02:04:57.74#ibcon#about to read 3, iclass 38, count 0 2006.257.02:04:57.77#ibcon#read 3, iclass 38, count 0 2006.257.02:04:57.77#ibcon#about to read 4, iclass 38, count 0 2006.257.02:04:57.77#ibcon#read 4, iclass 38, count 0 2006.257.02:04:57.77#ibcon#about to read 5, iclass 38, count 0 2006.257.02:04:57.77#ibcon#read 5, iclass 38, count 0 2006.257.02:04:57.77#ibcon#about to read 6, iclass 38, count 0 2006.257.02:04:57.77#ibcon#read 6, iclass 38, count 0 2006.257.02:04:57.77#ibcon#end of sib2, iclass 38, count 0 2006.257.02:04:57.77#ibcon#*after write, iclass 38, count 0 2006.257.02:04:57.77#ibcon#*before return 0, iclass 38, count 0 2006.257.02:04:57.77#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:04:57.77#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:04:57.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:04:57.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:04:57.77$vck44/valo=3,564.99 2006.257.02:04:57.77#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.02:04:57.77#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.02:04:57.77#ibcon#ireg 17 cls_cnt 0 2006.257.02:04:57.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:04:57.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:04:57.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:04:57.77#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:04:57.77#ibcon#first serial, iclass 40, count 0 2006.257.02:04:57.77#ibcon#enter sib2, iclass 40, count 0 2006.257.02:04:57.77#ibcon#flushed, iclass 40, count 0 2006.257.02:04:57.77#ibcon#about to write, iclass 40, count 0 2006.257.02:04:57.77#ibcon#wrote, iclass 40, count 0 2006.257.02:04:57.77#ibcon#about to read 3, iclass 40, count 0 2006.257.02:04:57.80#ibcon#read 3, iclass 40, count 0 2006.257.02:04:57.80#ibcon#about to read 4, iclass 40, count 0 2006.257.02:04:57.80#ibcon#read 4, iclass 40, count 0 2006.257.02:04:57.80#ibcon#about to read 5, iclass 40, count 0 2006.257.02:04:57.80#ibcon#read 5, iclass 40, count 0 2006.257.02:04:57.80#ibcon#about to read 6, iclass 40, count 0 2006.257.02:04:57.80#ibcon#read 6, iclass 40, count 0 2006.257.02:04:57.80#ibcon#end of sib2, iclass 40, count 0 2006.257.02:04:57.80#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:04:57.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:04:57.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:04:57.80#ibcon#*before write, iclass 40, count 0 2006.257.02:04:57.80#ibcon#enter sib2, iclass 40, count 0 2006.257.02:04:57.80#ibcon#flushed, iclass 40, count 0 2006.257.02:04:57.80#ibcon#about to write, iclass 40, count 0 2006.257.02:04:57.80#ibcon#wrote, iclass 40, count 0 2006.257.02:04:57.80#ibcon#about to read 3, iclass 40, count 0 2006.257.02:04:57.84#ibcon#read 3, iclass 40, count 0 2006.257.02:04:57.84#ibcon#about to read 4, iclass 40, count 0 2006.257.02:04:57.84#ibcon#read 4, iclass 40, count 0 2006.257.02:04:57.84#ibcon#about to read 5, iclass 40, count 0 2006.257.02:04:57.84#ibcon#read 5, iclass 40, count 0 2006.257.02:04:57.84#ibcon#about to read 6, iclass 40, count 0 2006.257.02:04:57.84#ibcon#read 6, iclass 40, count 0 2006.257.02:04:57.84#ibcon#end of sib2, iclass 40, count 0 2006.257.02:04:57.84#ibcon#*after write, iclass 40, count 0 2006.257.02:04:57.84#ibcon#*before return 0, iclass 40, count 0 2006.257.02:04:57.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:04:57.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:04:57.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:04:57.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:04:57.84$vck44/va=3,8 2006.257.02:04:57.84#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.02:04:57.84#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.02:04:57.84#ibcon#ireg 11 cls_cnt 2 2006.257.02:04:57.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:04:57.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:04:57.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:04:57.89#ibcon#enter wrdev, iclass 4, count 2 2006.257.02:04:57.89#ibcon#first serial, iclass 4, count 2 2006.257.02:04:57.89#ibcon#enter sib2, iclass 4, count 2 2006.257.02:04:57.89#ibcon#flushed, iclass 4, count 2 2006.257.02:04:57.89#ibcon#about to write, iclass 4, count 2 2006.257.02:04:57.89#ibcon#wrote, iclass 4, count 2 2006.257.02:04:57.89#ibcon#about to read 3, iclass 4, count 2 2006.257.02:04:57.91#ibcon#read 3, iclass 4, count 2 2006.257.02:04:57.91#ibcon#about to read 4, iclass 4, count 2 2006.257.02:04:57.91#ibcon#read 4, iclass 4, count 2 2006.257.02:04:57.91#ibcon#about to read 5, iclass 4, count 2 2006.257.02:04:57.91#ibcon#read 5, iclass 4, count 2 2006.257.02:04:57.91#ibcon#about to read 6, iclass 4, count 2 2006.257.02:04:57.91#ibcon#read 6, iclass 4, count 2 2006.257.02:04:57.91#ibcon#end of sib2, iclass 4, count 2 2006.257.02:04:57.91#ibcon#*mode == 0, iclass 4, count 2 2006.257.02:04:57.91#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.02:04:57.91#ibcon#[25=AT03-08\r\n] 2006.257.02:04:57.91#ibcon#*before write, iclass 4, count 2 2006.257.02:04:57.91#ibcon#enter sib2, iclass 4, count 2 2006.257.02:04:57.91#ibcon#flushed, iclass 4, count 2 2006.257.02:04:57.91#ibcon#about to write, iclass 4, count 2 2006.257.02:04:57.91#ibcon#wrote, iclass 4, count 2 2006.257.02:04:57.91#ibcon#about to read 3, iclass 4, count 2 2006.257.02:04:57.94#ibcon#read 3, iclass 4, count 2 2006.257.02:04:57.94#ibcon#about to read 4, iclass 4, count 2 2006.257.02:04:57.94#ibcon#read 4, iclass 4, count 2 2006.257.02:04:57.94#ibcon#about to read 5, iclass 4, count 2 2006.257.02:04:57.94#ibcon#read 5, iclass 4, count 2 2006.257.02:04:57.94#ibcon#about to read 6, iclass 4, count 2 2006.257.02:04:57.94#ibcon#read 6, iclass 4, count 2 2006.257.02:04:57.94#ibcon#end of sib2, iclass 4, count 2 2006.257.02:04:57.94#ibcon#*after write, iclass 4, count 2 2006.257.02:04:57.94#ibcon#*before return 0, iclass 4, count 2 2006.257.02:04:57.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:04:57.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:04:57.94#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.02:04:57.94#ibcon#ireg 7 cls_cnt 0 2006.257.02:04:57.94#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:04:58.04#abcon#<5=/03 3.8 9.2 17.801001011.8\r\n> 2006.257.02:04:58.06#abcon#{5=INTERFACE CLEAR} 2006.257.02:04:58.06#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:04:58.06#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:04:58.06#ibcon#enter wrdev, iclass 4, count 0 2006.257.02:04:58.06#ibcon#first serial, iclass 4, count 0 2006.257.02:04:58.06#ibcon#enter sib2, iclass 4, count 0 2006.257.02:04:58.06#ibcon#flushed, iclass 4, count 0 2006.257.02:04:58.06#ibcon#about to write, iclass 4, count 0 2006.257.02:04:58.06#ibcon#wrote, iclass 4, count 0 2006.257.02:04:58.06#ibcon#about to read 3, iclass 4, count 0 2006.257.02:04:58.08#ibcon#read 3, iclass 4, count 0 2006.257.02:04:58.08#ibcon#about to read 4, iclass 4, count 0 2006.257.02:04:58.08#ibcon#read 4, iclass 4, count 0 2006.257.02:04:58.08#ibcon#about to read 5, iclass 4, count 0 2006.257.02:04:58.08#ibcon#read 5, iclass 4, count 0 2006.257.02:04:58.08#ibcon#about to read 6, iclass 4, count 0 2006.257.02:04:58.08#ibcon#read 6, iclass 4, count 0 2006.257.02:04:58.08#ibcon#end of sib2, iclass 4, count 0 2006.257.02:04:58.08#ibcon#*mode == 0, iclass 4, count 0 2006.257.02:04:58.08#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.02:04:58.08#ibcon#[25=USB\r\n] 2006.257.02:04:58.08#ibcon#*before write, iclass 4, count 0 2006.257.02:04:58.08#ibcon#enter sib2, iclass 4, count 0 2006.257.02:04:58.08#ibcon#flushed, iclass 4, count 0 2006.257.02:04:58.08#ibcon#about to write, iclass 4, count 0 2006.257.02:04:58.08#ibcon#wrote, iclass 4, count 0 2006.257.02:04:58.08#ibcon#about to read 3, iclass 4, count 0 2006.257.02:04:58.11#ibcon#read 3, iclass 4, count 0 2006.257.02:04:58.11#ibcon#about to read 4, iclass 4, count 0 2006.257.02:04:58.11#ibcon#read 4, iclass 4, count 0 2006.257.02:04:58.11#ibcon#about to read 5, iclass 4, count 0 2006.257.02:04:58.11#ibcon#read 5, iclass 4, count 0 2006.257.02:04:58.11#ibcon#about to read 6, iclass 4, count 0 2006.257.02:04:58.11#ibcon#read 6, iclass 4, count 0 2006.257.02:04:58.11#ibcon#end of sib2, iclass 4, count 0 2006.257.02:04:58.11#ibcon#*after write, iclass 4, count 0 2006.257.02:04:58.11#ibcon#*before return 0, iclass 4, count 0 2006.257.02:04:58.11#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:04:58.11#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:04:58.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.02:04:58.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.02:04:58.11$vck44/valo=4,624.99 2006.257.02:04:58.11#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.02:04:58.11#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.02:04:58.11#ibcon#ireg 17 cls_cnt 0 2006.257.02:04:58.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:04:58.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:04:58.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:04:58.11#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:04:58.11#ibcon#first serial, iclass 12, count 0 2006.257.02:04:58.11#ibcon#enter sib2, iclass 12, count 0 2006.257.02:04:58.11#ibcon#flushed, iclass 12, count 0 2006.257.02:04:58.11#ibcon#about to write, iclass 12, count 0 2006.257.02:04:58.11#ibcon#wrote, iclass 12, count 0 2006.257.02:04:58.11#ibcon#about to read 3, iclass 12, count 0 2006.257.02:04:58.12#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:04:58.13#ibcon#read 3, iclass 12, count 0 2006.257.02:04:58.13#ibcon#about to read 4, iclass 12, count 0 2006.257.02:04:58.13#ibcon#read 4, iclass 12, count 0 2006.257.02:04:58.13#ibcon#about to read 5, iclass 12, count 0 2006.257.02:04:58.13#ibcon#read 5, iclass 12, count 0 2006.257.02:04:58.13#ibcon#about to read 6, iclass 12, count 0 2006.257.02:04:58.13#ibcon#read 6, iclass 12, count 0 2006.257.02:04:58.13#ibcon#end of sib2, iclass 12, count 0 2006.257.02:04:58.13#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:04:58.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:04:58.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:04:58.13#ibcon#*before write, iclass 12, count 0 2006.257.02:04:58.13#ibcon#enter sib2, iclass 12, count 0 2006.257.02:04:58.13#ibcon#flushed, iclass 12, count 0 2006.257.02:04:58.13#ibcon#about to write, iclass 12, count 0 2006.257.02:04:58.13#ibcon#wrote, iclass 12, count 0 2006.257.02:04:58.13#ibcon#about to read 3, iclass 12, count 0 2006.257.02:04:58.17#ibcon#read 3, iclass 12, count 0 2006.257.02:04:58.17#ibcon#about to read 4, iclass 12, count 0 2006.257.02:04:58.17#ibcon#read 4, iclass 12, count 0 2006.257.02:04:58.17#ibcon#about to read 5, iclass 12, count 0 2006.257.02:04:58.17#ibcon#read 5, iclass 12, count 0 2006.257.02:04:58.17#ibcon#about to read 6, iclass 12, count 0 2006.257.02:04:58.17#ibcon#read 6, iclass 12, count 0 2006.257.02:04:58.17#ibcon#end of sib2, iclass 12, count 0 2006.257.02:04:58.17#ibcon#*after write, iclass 12, count 0 2006.257.02:04:58.17#ibcon#*before return 0, iclass 12, count 0 2006.257.02:04:58.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:04:58.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:04:58.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:04:58.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:04:58.17$vck44/va=4,7 2006.257.02:04:58.17#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.02:04:58.17#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.02:04:58.17#ibcon#ireg 11 cls_cnt 2 2006.257.02:04:58.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:04:58.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:04:58.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:04:58.23#ibcon#enter wrdev, iclass 14, count 2 2006.257.02:04:58.23#ibcon#first serial, iclass 14, count 2 2006.257.02:04:58.23#ibcon#enter sib2, iclass 14, count 2 2006.257.02:04:58.23#ibcon#flushed, iclass 14, count 2 2006.257.02:04:58.23#ibcon#about to write, iclass 14, count 2 2006.257.02:04:58.23#ibcon#wrote, iclass 14, count 2 2006.257.02:04:58.23#ibcon#about to read 3, iclass 14, count 2 2006.257.02:04:58.25#ibcon#read 3, iclass 14, count 2 2006.257.02:04:58.25#ibcon#about to read 4, iclass 14, count 2 2006.257.02:04:58.25#ibcon#read 4, iclass 14, count 2 2006.257.02:04:58.25#ibcon#about to read 5, iclass 14, count 2 2006.257.02:04:58.25#ibcon#read 5, iclass 14, count 2 2006.257.02:04:58.25#ibcon#about to read 6, iclass 14, count 2 2006.257.02:04:58.25#ibcon#read 6, iclass 14, count 2 2006.257.02:04:58.25#ibcon#end of sib2, iclass 14, count 2 2006.257.02:04:58.25#ibcon#*mode == 0, iclass 14, count 2 2006.257.02:04:58.25#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.02:04:58.25#ibcon#[25=AT04-07\r\n] 2006.257.02:04:58.25#ibcon#*before write, iclass 14, count 2 2006.257.02:04:58.25#ibcon#enter sib2, iclass 14, count 2 2006.257.02:04:58.25#ibcon#flushed, iclass 14, count 2 2006.257.02:04:58.25#ibcon#about to write, iclass 14, count 2 2006.257.02:04:58.25#ibcon#wrote, iclass 14, count 2 2006.257.02:04:58.25#ibcon#about to read 3, iclass 14, count 2 2006.257.02:04:58.28#ibcon#read 3, iclass 14, count 2 2006.257.02:04:58.28#ibcon#about to read 4, iclass 14, count 2 2006.257.02:04:58.28#ibcon#read 4, iclass 14, count 2 2006.257.02:04:58.28#ibcon#about to read 5, iclass 14, count 2 2006.257.02:04:58.28#ibcon#read 5, iclass 14, count 2 2006.257.02:04:58.28#ibcon#about to read 6, iclass 14, count 2 2006.257.02:04:58.28#ibcon#read 6, iclass 14, count 2 2006.257.02:04:58.28#ibcon#end of sib2, iclass 14, count 2 2006.257.02:04:58.28#ibcon#*after write, iclass 14, count 2 2006.257.02:04:58.28#ibcon#*before return 0, iclass 14, count 2 2006.257.02:04:58.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:04:58.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:04:58.28#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.02:04:58.28#ibcon#ireg 7 cls_cnt 0 2006.257.02:04:58.28#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:04:58.40#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:04:58.40#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:04:58.40#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:04:58.40#ibcon#first serial, iclass 14, count 0 2006.257.02:04:58.40#ibcon#enter sib2, iclass 14, count 0 2006.257.02:04:58.40#ibcon#flushed, iclass 14, count 0 2006.257.02:04:58.40#ibcon#about to write, iclass 14, count 0 2006.257.02:04:58.40#ibcon#wrote, iclass 14, count 0 2006.257.02:04:58.40#ibcon#about to read 3, iclass 14, count 0 2006.257.02:04:58.42#ibcon#read 3, iclass 14, count 0 2006.257.02:04:58.42#ibcon#about to read 4, iclass 14, count 0 2006.257.02:04:58.42#ibcon#read 4, iclass 14, count 0 2006.257.02:04:58.42#ibcon#about to read 5, iclass 14, count 0 2006.257.02:04:58.42#ibcon#read 5, iclass 14, count 0 2006.257.02:04:58.42#ibcon#about to read 6, iclass 14, count 0 2006.257.02:04:58.42#ibcon#read 6, iclass 14, count 0 2006.257.02:04:58.42#ibcon#end of sib2, iclass 14, count 0 2006.257.02:04:58.42#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:04:58.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:04:58.42#ibcon#[25=USB\r\n] 2006.257.02:04:58.42#ibcon#*before write, iclass 14, count 0 2006.257.02:04:58.42#ibcon#enter sib2, iclass 14, count 0 2006.257.02:04:58.42#ibcon#flushed, iclass 14, count 0 2006.257.02:04:58.42#ibcon#about to write, iclass 14, count 0 2006.257.02:04:58.42#ibcon#wrote, iclass 14, count 0 2006.257.02:04:58.42#ibcon#about to read 3, iclass 14, count 0 2006.257.02:04:58.45#ibcon#read 3, iclass 14, count 0 2006.257.02:04:58.45#ibcon#about to read 4, iclass 14, count 0 2006.257.02:04:58.45#ibcon#read 4, iclass 14, count 0 2006.257.02:04:58.45#ibcon#about to read 5, iclass 14, count 0 2006.257.02:04:58.45#ibcon#read 5, iclass 14, count 0 2006.257.02:04:58.45#ibcon#about to read 6, iclass 14, count 0 2006.257.02:04:58.45#ibcon#read 6, iclass 14, count 0 2006.257.02:04:58.45#ibcon#end of sib2, iclass 14, count 0 2006.257.02:04:58.45#ibcon#*after write, iclass 14, count 0 2006.257.02:04:58.45#ibcon#*before return 0, iclass 14, count 0 2006.257.02:04:58.45#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:04:58.45#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:04:58.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:04:58.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:04:58.45$vck44/valo=5,734.99 2006.257.02:04:58.45#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.02:04:58.45#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.02:04:58.45#ibcon#ireg 17 cls_cnt 0 2006.257.02:04:58.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:04:58.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:04:58.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:04:58.45#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:04:58.45#ibcon#first serial, iclass 16, count 0 2006.257.02:04:58.45#ibcon#enter sib2, iclass 16, count 0 2006.257.02:04:58.45#ibcon#flushed, iclass 16, count 0 2006.257.02:04:58.45#ibcon#about to write, iclass 16, count 0 2006.257.02:04:58.45#ibcon#wrote, iclass 16, count 0 2006.257.02:04:58.45#ibcon#about to read 3, iclass 16, count 0 2006.257.02:04:58.47#ibcon#read 3, iclass 16, count 0 2006.257.02:04:58.47#ibcon#about to read 4, iclass 16, count 0 2006.257.02:04:58.47#ibcon#read 4, iclass 16, count 0 2006.257.02:04:58.47#ibcon#about to read 5, iclass 16, count 0 2006.257.02:04:58.47#ibcon#read 5, iclass 16, count 0 2006.257.02:04:58.47#ibcon#about to read 6, iclass 16, count 0 2006.257.02:04:58.47#ibcon#read 6, iclass 16, count 0 2006.257.02:04:58.47#ibcon#end of sib2, iclass 16, count 0 2006.257.02:04:58.47#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:04:58.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:04:58.47#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:04:58.47#ibcon#*before write, iclass 16, count 0 2006.257.02:04:58.47#ibcon#enter sib2, iclass 16, count 0 2006.257.02:04:58.47#ibcon#flushed, iclass 16, count 0 2006.257.02:04:58.47#ibcon#about to write, iclass 16, count 0 2006.257.02:04:58.47#ibcon#wrote, iclass 16, count 0 2006.257.02:04:58.47#ibcon#about to read 3, iclass 16, count 0 2006.257.02:04:58.51#ibcon#read 3, iclass 16, count 0 2006.257.02:04:58.51#ibcon#about to read 4, iclass 16, count 0 2006.257.02:04:58.51#ibcon#read 4, iclass 16, count 0 2006.257.02:04:58.51#ibcon#about to read 5, iclass 16, count 0 2006.257.02:04:58.51#ibcon#read 5, iclass 16, count 0 2006.257.02:04:58.51#ibcon#about to read 6, iclass 16, count 0 2006.257.02:04:58.51#ibcon#read 6, iclass 16, count 0 2006.257.02:04:58.51#ibcon#end of sib2, iclass 16, count 0 2006.257.02:04:58.51#ibcon#*after write, iclass 16, count 0 2006.257.02:04:58.51#ibcon#*before return 0, iclass 16, count 0 2006.257.02:04:58.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:04:58.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:04:58.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:04:58.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:04:58.51$vck44/va=5,4 2006.257.02:04:58.51#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.02:04:58.51#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.02:04:58.51#ibcon#ireg 11 cls_cnt 2 2006.257.02:04:58.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:04:58.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:04:58.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:04:58.57#ibcon#enter wrdev, iclass 18, count 2 2006.257.02:04:58.57#ibcon#first serial, iclass 18, count 2 2006.257.02:04:58.57#ibcon#enter sib2, iclass 18, count 2 2006.257.02:04:58.57#ibcon#flushed, iclass 18, count 2 2006.257.02:04:58.57#ibcon#about to write, iclass 18, count 2 2006.257.02:04:58.57#ibcon#wrote, iclass 18, count 2 2006.257.02:04:58.57#ibcon#about to read 3, iclass 18, count 2 2006.257.02:04:58.59#ibcon#read 3, iclass 18, count 2 2006.257.02:04:58.59#ibcon#about to read 4, iclass 18, count 2 2006.257.02:04:58.59#ibcon#read 4, iclass 18, count 2 2006.257.02:04:58.59#ibcon#about to read 5, iclass 18, count 2 2006.257.02:04:58.59#ibcon#read 5, iclass 18, count 2 2006.257.02:04:58.59#ibcon#about to read 6, iclass 18, count 2 2006.257.02:04:58.59#ibcon#read 6, iclass 18, count 2 2006.257.02:04:58.59#ibcon#end of sib2, iclass 18, count 2 2006.257.02:04:58.59#ibcon#*mode == 0, iclass 18, count 2 2006.257.02:04:58.59#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.02:04:58.59#ibcon#[25=AT05-04\r\n] 2006.257.02:04:58.59#ibcon#*before write, iclass 18, count 2 2006.257.02:04:58.59#ibcon#enter sib2, iclass 18, count 2 2006.257.02:04:58.59#ibcon#flushed, iclass 18, count 2 2006.257.02:04:58.59#ibcon#about to write, iclass 18, count 2 2006.257.02:04:58.59#ibcon#wrote, iclass 18, count 2 2006.257.02:04:58.59#ibcon#about to read 3, iclass 18, count 2 2006.257.02:04:58.62#ibcon#read 3, iclass 18, count 2 2006.257.02:04:58.62#ibcon#about to read 4, iclass 18, count 2 2006.257.02:04:58.62#ibcon#read 4, iclass 18, count 2 2006.257.02:04:58.62#ibcon#about to read 5, iclass 18, count 2 2006.257.02:04:58.62#ibcon#read 5, iclass 18, count 2 2006.257.02:04:58.62#ibcon#about to read 6, iclass 18, count 2 2006.257.02:04:58.62#ibcon#read 6, iclass 18, count 2 2006.257.02:04:58.62#ibcon#end of sib2, iclass 18, count 2 2006.257.02:04:58.62#ibcon#*after write, iclass 18, count 2 2006.257.02:04:58.62#ibcon#*before return 0, iclass 18, count 2 2006.257.02:04:58.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:04:58.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:04:58.62#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.02:04:58.62#ibcon#ireg 7 cls_cnt 0 2006.257.02:04:58.62#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:04:58.74#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:04:58.74#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:04:58.74#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:04:58.74#ibcon#first serial, iclass 18, count 0 2006.257.02:04:58.74#ibcon#enter sib2, iclass 18, count 0 2006.257.02:04:58.74#ibcon#flushed, iclass 18, count 0 2006.257.02:04:58.74#ibcon#about to write, iclass 18, count 0 2006.257.02:04:58.74#ibcon#wrote, iclass 18, count 0 2006.257.02:04:58.74#ibcon#about to read 3, iclass 18, count 0 2006.257.02:04:58.76#ibcon#read 3, iclass 18, count 0 2006.257.02:04:58.76#ibcon#about to read 4, iclass 18, count 0 2006.257.02:04:58.76#ibcon#read 4, iclass 18, count 0 2006.257.02:04:58.76#ibcon#about to read 5, iclass 18, count 0 2006.257.02:04:58.76#ibcon#read 5, iclass 18, count 0 2006.257.02:04:58.76#ibcon#about to read 6, iclass 18, count 0 2006.257.02:04:58.76#ibcon#read 6, iclass 18, count 0 2006.257.02:04:58.76#ibcon#end of sib2, iclass 18, count 0 2006.257.02:04:58.76#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:04:58.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:04:58.76#ibcon#[25=USB\r\n] 2006.257.02:04:58.76#ibcon#*before write, iclass 18, count 0 2006.257.02:04:58.76#ibcon#enter sib2, iclass 18, count 0 2006.257.02:04:58.76#ibcon#flushed, iclass 18, count 0 2006.257.02:04:58.76#ibcon#about to write, iclass 18, count 0 2006.257.02:04:58.76#ibcon#wrote, iclass 18, count 0 2006.257.02:04:58.76#ibcon#about to read 3, iclass 18, count 0 2006.257.02:04:58.79#ibcon#read 3, iclass 18, count 0 2006.257.02:04:58.79#ibcon#about to read 4, iclass 18, count 0 2006.257.02:04:58.79#ibcon#read 4, iclass 18, count 0 2006.257.02:04:58.79#ibcon#about to read 5, iclass 18, count 0 2006.257.02:04:58.79#ibcon#read 5, iclass 18, count 0 2006.257.02:04:58.79#ibcon#about to read 6, iclass 18, count 0 2006.257.02:04:58.79#ibcon#read 6, iclass 18, count 0 2006.257.02:04:58.79#ibcon#end of sib2, iclass 18, count 0 2006.257.02:04:58.79#ibcon#*after write, iclass 18, count 0 2006.257.02:04:58.79#ibcon#*before return 0, iclass 18, count 0 2006.257.02:04:58.79#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:04:58.79#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:04:58.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:04:58.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:04:58.79$vck44/valo=6,814.99 2006.257.02:04:58.79#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.02:04:58.79#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.02:04:58.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:04:58.79#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:04:58.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:04:58.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:04:58.79#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:04:58.79#ibcon#first serial, iclass 20, count 0 2006.257.02:04:58.79#ibcon#enter sib2, iclass 20, count 0 2006.257.02:04:58.79#ibcon#flushed, iclass 20, count 0 2006.257.02:04:58.79#ibcon#about to write, iclass 20, count 0 2006.257.02:04:58.79#ibcon#wrote, iclass 20, count 0 2006.257.02:04:58.79#ibcon#about to read 3, iclass 20, count 0 2006.257.02:04:58.81#ibcon#read 3, iclass 20, count 0 2006.257.02:04:58.81#ibcon#about to read 4, iclass 20, count 0 2006.257.02:04:58.81#ibcon#read 4, iclass 20, count 0 2006.257.02:04:58.81#ibcon#about to read 5, iclass 20, count 0 2006.257.02:04:58.81#ibcon#read 5, iclass 20, count 0 2006.257.02:04:58.81#ibcon#about to read 6, iclass 20, count 0 2006.257.02:04:58.81#ibcon#read 6, iclass 20, count 0 2006.257.02:04:58.81#ibcon#end of sib2, iclass 20, count 0 2006.257.02:04:58.81#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:04:58.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:04:58.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:04:58.81#ibcon#*before write, iclass 20, count 0 2006.257.02:04:58.81#ibcon#enter sib2, iclass 20, count 0 2006.257.02:04:58.81#ibcon#flushed, iclass 20, count 0 2006.257.02:04:58.81#ibcon#about to write, iclass 20, count 0 2006.257.02:04:58.81#ibcon#wrote, iclass 20, count 0 2006.257.02:04:58.81#ibcon#about to read 3, iclass 20, count 0 2006.257.02:04:58.85#ibcon#read 3, iclass 20, count 0 2006.257.02:04:58.85#ibcon#about to read 4, iclass 20, count 0 2006.257.02:04:58.85#ibcon#read 4, iclass 20, count 0 2006.257.02:04:58.85#ibcon#about to read 5, iclass 20, count 0 2006.257.02:04:58.85#ibcon#read 5, iclass 20, count 0 2006.257.02:04:58.85#ibcon#about to read 6, iclass 20, count 0 2006.257.02:04:58.85#ibcon#read 6, iclass 20, count 0 2006.257.02:04:58.85#ibcon#end of sib2, iclass 20, count 0 2006.257.02:04:58.85#ibcon#*after write, iclass 20, count 0 2006.257.02:04:58.85#ibcon#*before return 0, iclass 20, count 0 2006.257.02:04:58.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:04:58.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:04:58.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:04:58.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:04:58.85$vck44/va=6,4 2006.257.02:04:58.85#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.02:04:58.85#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.02:04:58.85#ibcon#ireg 11 cls_cnt 2 2006.257.02:04:58.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:04:58.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:04:58.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:04:58.91#ibcon#enter wrdev, iclass 22, count 2 2006.257.02:04:58.91#ibcon#first serial, iclass 22, count 2 2006.257.02:04:58.91#ibcon#enter sib2, iclass 22, count 2 2006.257.02:04:58.91#ibcon#flushed, iclass 22, count 2 2006.257.02:04:58.91#ibcon#about to write, iclass 22, count 2 2006.257.02:04:58.91#ibcon#wrote, iclass 22, count 2 2006.257.02:04:58.91#ibcon#about to read 3, iclass 22, count 2 2006.257.02:04:58.93#ibcon#read 3, iclass 22, count 2 2006.257.02:04:58.93#ibcon#about to read 4, iclass 22, count 2 2006.257.02:04:58.93#ibcon#read 4, iclass 22, count 2 2006.257.02:04:58.93#ibcon#about to read 5, iclass 22, count 2 2006.257.02:04:58.93#ibcon#read 5, iclass 22, count 2 2006.257.02:04:58.93#ibcon#about to read 6, iclass 22, count 2 2006.257.02:04:58.93#ibcon#read 6, iclass 22, count 2 2006.257.02:04:58.93#ibcon#end of sib2, iclass 22, count 2 2006.257.02:04:58.93#ibcon#*mode == 0, iclass 22, count 2 2006.257.02:04:58.93#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.02:04:58.93#ibcon#[25=AT06-04\r\n] 2006.257.02:04:58.93#ibcon#*before write, iclass 22, count 2 2006.257.02:04:58.93#ibcon#enter sib2, iclass 22, count 2 2006.257.02:04:58.93#ibcon#flushed, iclass 22, count 2 2006.257.02:04:58.93#ibcon#about to write, iclass 22, count 2 2006.257.02:04:58.93#ibcon#wrote, iclass 22, count 2 2006.257.02:04:58.93#ibcon#about to read 3, iclass 22, count 2 2006.257.02:04:58.96#ibcon#read 3, iclass 22, count 2 2006.257.02:04:58.96#ibcon#about to read 4, iclass 22, count 2 2006.257.02:04:58.96#ibcon#read 4, iclass 22, count 2 2006.257.02:04:58.96#ibcon#about to read 5, iclass 22, count 2 2006.257.02:04:58.96#ibcon#read 5, iclass 22, count 2 2006.257.02:04:58.96#ibcon#about to read 6, iclass 22, count 2 2006.257.02:04:58.96#ibcon#read 6, iclass 22, count 2 2006.257.02:04:58.96#ibcon#end of sib2, iclass 22, count 2 2006.257.02:04:58.96#ibcon#*after write, iclass 22, count 2 2006.257.02:04:58.96#ibcon#*before return 0, iclass 22, count 2 2006.257.02:04:58.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:04:58.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:04:58.96#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.02:04:58.96#ibcon#ireg 7 cls_cnt 0 2006.257.02:04:58.96#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:04:59.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:04:59.08#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:04:59.08#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:04:59.08#ibcon#first serial, iclass 22, count 0 2006.257.02:04:59.08#ibcon#enter sib2, iclass 22, count 0 2006.257.02:04:59.08#ibcon#flushed, iclass 22, count 0 2006.257.02:04:59.08#ibcon#about to write, iclass 22, count 0 2006.257.02:04:59.08#ibcon#wrote, iclass 22, count 0 2006.257.02:04:59.08#ibcon#about to read 3, iclass 22, count 0 2006.257.02:04:59.10#ibcon#read 3, iclass 22, count 0 2006.257.02:04:59.10#ibcon#about to read 4, iclass 22, count 0 2006.257.02:04:59.10#ibcon#read 4, iclass 22, count 0 2006.257.02:04:59.10#ibcon#about to read 5, iclass 22, count 0 2006.257.02:04:59.10#ibcon#read 5, iclass 22, count 0 2006.257.02:04:59.10#ibcon#about to read 6, iclass 22, count 0 2006.257.02:04:59.10#ibcon#read 6, iclass 22, count 0 2006.257.02:04:59.10#ibcon#end of sib2, iclass 22, count 0 2006.257.02:04:59.10#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:04:59.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:04:59.10#ibcon#[25=USB\r\n] 2006.257.02:04:59.10#ibcon#*before write, iclass 22, count 0 2006.257.02:04:59.10#ibcon#enter sib2, iclass 22, count 0 2006.257.02:04:59.10#ibcon#flushed, iclass 22, count 0 2006.257.02:04:59.10#ibcon#about to write, iclass 22, count 0 2006.257.02:04:59.10#ibcon#wrote, iclass 22, count 0 2006.257.02:04:59.10#ibcon#about to read 3, iclass 22, count 0 2006.257.02:04:59.13#ibcon#read 3, iclass 22, count 0 2006.257.02:04:59.13#ibcon#about to read 4, iclass 22, count 0 2006.257.02:04:59.13#ibcon#read 4, iclass 22, count 0 2006.257.02:04:59.13#ibcon#about to read 5, iclass 22, count 0 2006.257.02:04:59.13#ibcon#read 5, iclass 22, count 0 2006.257.02:04:59.13#ibcon#about to read 6, iclass 22, count 0 2006.257.02:04:59.13#ibcon#read 6, iclass 22, count 0 2006.257.02:04:59.13#ibcon#end of sib2, iclass 22, count 0 2006.257.02:04:59.13#ibcon#*after write, iclass 22, count 0 2006.257.02:04:59.13#ibcon#*before return 0, iclass 22, count 0 2006.257.02:04:59.13#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:04:59.13#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:04:59.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:04:59.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:04:59.13$vck44/valo=7,864.99 2006.257.02:04:59.13#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.02:04:59.13#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.02:04:59.13#ibcon#ireg 17 cls_cnt 0 2006.257.02:04:59.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:04:59.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:04:59.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:04:59.13#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:04:59.13#ibcon#first serial, iclass 24, count 0 2006.257.02:04:59.13#ibcon#enter sib2, iclass 24, count 0 2006.257.02:04:59.13#ibcon#flushed, iclass 24, count 0 2006.257.02:04:59.13#ibcon#about to write, iclass 24, count 0 2006.257.02:04:59.13#ibcon#wrote, iclass 24, count 0 2006.257.02:04:59.13#ibcon#about to read 3, iclass 24, count 0 2006.257.02:04:59.15#ibcon#read 3, iclass 24, count 0 2006.257.02:04:59.15#ibcon#about to read 4, iclass 24, count 0 2006.257.02:04:59.15#ibcon#read 4, iclass 24, count 0 2006.257.02:04:59.15#ibcon#about to read 5, iclass 24, count 0 2006.257.02:04:59.15#ibcon#read 5, iclass 24, count 0 2006.257.02:04:59.15#ibcon#about to read 6, iclass 24, count 0 2006.257.02:04:59.15#ibcon#read 6, iclass 24, count 0 2006.257.02:04:59.15#ibcon#end of sib2, iclass 24, count 0 2006.257.02:04:59.15#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:04:59.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:04:59.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:04:59.15#ibcon#*before write, iclass 24, count 0 2006.257.02:04:59.15#ibcon#enter sib2, iclass 24, count 0 2006.257.02:04:59.15#ibcon#flushed, iclass 24, count 0 2006.257.02:04:59.15#ibcon#about to write, iclass 24, count 0 2006.257.02:04:59.15#ibcon#wrote, iclass 24, count 0 2006.257.02:04:59.15#ibcon#about to read 3, iclass 24, count 0 2006.257.02:04:59.19#ibcon#read 3, iclass 24, count 0 2006.257.02:04:59.19#ibcon#about to read 4, iclass 24, count 0 2006.257.02:04:59.19#ibcon#read 4, iclass 24, count 0 2006.257.02:04:59.19#ibcon#about to read 5, iclass 24, count 0 2006.257.02:04:59.19#ibcon#read 5, iclass 24, count 0 2006.257.02:04:59.19#ibcon#about to read 6, iclass 24, count 0 2006.257.02:04:59.19#ibcon#read 6, iclass 24, count 0 2006.257.02:04:59.19#ibcon#end of sib2, iclass 24, count 0 2006.257.02:04:59.19#ibcon#*after write, iclass 24, count 0 2006.257.02:04:59.19#ibcon#*before return 0, iclass 24, count 0 2006.257.02:04:59.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:04:59.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:04:59.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:04:59.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:04:59.19$vck44/va=7,4 2006.257.02:04:59.19#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.02:04:59.19#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.02:04:59.19#ibcon#ireg 11 cls_cnt 2 2006.257.02:04:59.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:04:59.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:04:59.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:04:59.25#ibcon#enter wrdev, iclass 26, count 2 2006.257.02:04:59.25#ibcon#first serial, iclass 26, count 2 2006.257.02:04:59.25#ibcon#enter sib2, iclass 26, count 2 2006.257.02:04:59.25#ibcon#flushed, iclass 26, count 2 2006.257.02:04:59.25#ibcon#about to write, iclass 26, count 2 2006.257.02:04:59.25#ibcon#wrote, iclass 26, count 2 2006.257.02:04:59.25#ibcon#about to read 3, iclass 26, count 2 2006.257.02:04:59.27#ibcon#read 3, iclass 26, count 2 2006.257.02:04:59.27#ibcon#about to read 4, iclass 26, count 2 2006.257.02:04:59.27#ibcon#read 4, iclass 26, count 2 2006.257.02:04:59.27#ibcon#about to read 5, iclass 26, count 2 2006.257.02:04:59.27#ibcon#read 5, iclass 26, count 2 2006.257.02:04:59.27#ibcon#about to read 6, iclass 26, count 2 2006.257.02:04:59.27#ibcon#read 6, iclass 26, count 2 2006.257.02:04:59.27#ibcon#end of sib2, iclass 26, count 2 2006.257.02:04:59.27#ibcon#*mode == 0, iclass 26, count 2 2006.257.02:04:59.27#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.02:04:59.27#ibcon#[25=AT07-04\r\n] 2006.257.02:04:59.27#ibcon#*before write, iclass 26, count 2 2006.257.02:04:59.27#ibcon#enter sib2, iclass 26, count 2 2006.257.02:04:59.27#ibcon#flushed, iclass 26, count 2 2006.257.02:04:59.27#ibcon#about to write, iclass 26, count 2 2006.257.02:04:59.27#ibcon#wrote, iclass 26, count 2 2006.257.02:04:59.27#ibcon#about to read 3, iclass 26, count 2 2006.257.02:04:59.30#ibcon#read 3, iclass 26, count 2 2006.257.02:04:59.30#ibcon#about to read 4, iclass 26, count 2 2006.257.02:04:59.30#ibcon#read 4, iclass 26, count 2 2006.257.02:04:59.30#ibcon#about to read 5, iclass 26, count 2 2006.257.02:04:59.30#ibcon#read 5, iclass 26, count 2 2006.257.02:04:59.30#ibcon#about to read 6, iclass 26, count 2 2006.257.02:04:59.30#ibcon#read 6, iclass 26, count 2 2006.257.02:04:59.30#ibcon#end of sib2, iclass 26, count 2 2006.257.02:04:59.30#ibcon#*after write, iclass 26, count 2 2006.257.02:04:59.30#ibcon#*before return 0, iclass 26, count 2 2006.257.02:04:59.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:04:59.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:04:59.30#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.02:04:59.30#ibcon#ireg 7 cls_cnt 0 2006.257.02:04:59.30#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:04:59.42#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:04:59.42#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:04:59.42#ibcon#enter wrdev, iclass 26, count 0 2006.257.02:04:59.42#ibcon#first serial, iclass 26, count 0 2006.257.02:04:59.42#ibcon#enter sib2, iclass 26, count 0 2006.257.02:04:59.42#ibcon#flushed, iclass 26, count 0 2006.257.02:04:59.42#ibcon#about to write, iclass 26, count 0 2006.257.02:04:59.42#ibcon#wrote, iclass 26, count 0 2006.257.02:04:59.42#ibcon#about to read 3, iclass 26, count 0 2006.257.02:04:59.44#ibcon#read 3, iclass 26, count 0 2006.257.02:04:59.44#ibcon#about to read 4, iclass 26, count 0 2006.257.02:04:59.44#ibcon#read 4, iclass 26, count 0 2006.257.02:04:59.44#ibcon#about to read 5, iclass 26, count 0 2006.257.02:04:59.44#ibcon#read 5, iclass 26, count 0 2006.257.02:04:59.44#ibcon#about to read 6, iclass 26, count 0 2006.257.02:04:59.44#ibcon#read 6, iclass 26, count 0 2006.257.02:04:59.44#ibcon#end of sib2, iclass 26, count 0 2006.257.02:04:59.44#ibcon#*mode == 0, iclass 26, count 0 2006.257.02:04:59.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.02:04:59.44#ibcon#[25=USB\r\n] 2006.257.02:04:59.44#ibcon#*before write, iclass 26, count 0 2006.257.02:04:59.44#ibcon#enter sib2, iclass 26, count 0 2006.257.02:04:59.44#ibcon#flushed, iclass 26, count 0 2006.257.02:04:59.44#ibcon#about to write, iclass 26, count 0 2006.257.02:04:59.44#ibcon#wrote, iclass 26, count 0 2006.257.02:04:59.44#ibcon#about to read 3, iclass 26, count 0 2006.257.02:04:59.47#ibcon#read 3, iclass 26, count 0 2006.257.02:04:59.47#ibcon#about to read 4, iclass 26, count 0 2006.257.02:04:59.47#ibcon#read 4, iclass 26, count 0 2006.257.02:04:59.47#ibcon#about to read 5, iclass 26, count 0 2006.257.02:04:59.47#ibcon#read 5, iclass 26, count 0 2006.257.02:04:59.47#ibcon#about to read 6, iclass 26, count 0 2006.257.02:04:59.47#ibcon#read 6, iclass 26, count 0 2006.257.02:04:59.47#ibcon#end of sib2, iclass 26, count 0 2006.257.02:04:59.47#ibcon#*after write, iclass 26, count 0 2006.257.02:04:59.47#ibcon#*before return 0, iclass 26, count 0 2006.257.02:04:59.47#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:04:59.47#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:04:59.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.02:04:59.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.02:04:59.47$vck44/valo=8,884.99 2006.257.02:04:59.47#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.02:04:59.47#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.02:04:59.47#ibcon#ireg 17 cls_cnt 0 2006.257.02:04:59.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:04:59.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:04:59.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:04:59.47#ibcon#enter wrdev, iclass 28, count 0 2006.257.02:04:59.47#ibcon#first serial, iclass 28, count 0 2006.257.02:04:59.47#ibcon#enter sib2, iclass 28, count 0 2006.257.02:04:59.47#ibcon#flushed, iclass 28, count 0 2006.257.02:04:59.47#ibcon#about to write, iclass 28, count 0 2006.257.02:04:59.47#ibcon#wrote, iclass 28, count 0 2006.257.02:04:59.47#ibcon#about to read 3, iclass 28, count 0 2006.257.02:04:59.49#ibcon#read 3, iclass 28, count 0 2006.257.02:04:59.49#ibcon#about to read 4, iclass 28, count 0 2006.257.02:04:59.49#ibcon#read 4, iclass 28, count 0 2006.257.02:04:59.49#ibcon#about to read 5, iclass 28, count 0 2006.257.02:04:59.49#ibcon#read 5, iclass 28, count 0 2006.257.02:04:59.49#ibcon#about to read 6, iclass 28, count 0 2006.257.02:04:59.49#ibcon#read 6, iclass 28, count 0 2006.257.02:04:59.49#ibcon#end of sib2, iclass 28, count 0 2006.257.02:04:59.49#ibcon#*mode == 0, iclass 28, count 0 2006.257.02:04:59.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.02:04:59.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:04:59.49#ibcon#*before write, iclass 28, count 0 2006.257.02:04:59.49#ibcon#enter sib2, iclass 28, count 0 2006.257.02:04:59.49#ibcon#flushed, iclass 28, count 0 2006.257.02:04:59.49#ibcon#about to write, iclass 28, count 0 2006.257.02:04:59.49#ibcon#wrote, iclass 28, count 0 2006.257.02:04:59.49#ibcon#about to read 3, iclass 28, count 0 2006.257.02:04:59.53#ibcon#read 3, iclass 28, count 0 2006.257.02:04:59.53#ibcon#about to read 4, iclass 28, count 0 2006.257.02:04:59.53#ibcon#read 4, iclass 28, count 0 2006.257.02:04:59.53#ibcon#about to read 5, iclass 28, count 0 2006.257.02:04:59.53#ibcon#read 5, iclass 28, count 0 2006.257.02:04:59.53#ibcon#about to read 6, iclass 28, count 0 2006.257.02:04:59.53#ibcon#read 6, iclass 28, count 0 2006.257.02:04:59.53#ibcon#end of sib2, iclass 28, count 0 2006.257.02:04:59.53#ibcon#*after write, iclass 28, count 0 2006.257.02:04:59.53#ibcon#*before return 0, iclass 28, count 0 2006.257.02:04:59.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:04:59.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:04:59.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.02:04:59.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.02:04:59.53$vck44/va=8,4 2006.257.02:04:59.53#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.02:04:59.53#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.02:04:59.53#ibcon#ireg 11 cls_cnt 2 2006.257.02:04:59.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:04:59.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:04:59.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:04:59.59#ibcon#enter wrdev, iclass 30, count 2 2006.257.02:04:59.59#ibcon#first serial, iclass 30, count 2 2006.257.02:04:59.59#ibcon#enter sib2, iclass 30, count 2 2006.257.02:04:59.59#ibcon#flushed, iclass 30, count 2 2006.257.02:04:59.59#ibcon#about to write, iclass 30, count 2 2006.257.02:04:59.59#ibcon#wrote, iclass 30, count 2 2006.257.02:04:59.59#ibcon#about to read 3, iclass 30, count 2 2006.257.02:04:59.61#ibcon#read 3, iclass 30, count 2 2006.257.02:04:59.61#ibcon#about to read 4, iclass 30, count 2 2006.257.02:04:59.61#ibcon#read 4, iclass 30, count 2 2006.257.02:04:59.61#ibcon#about to read 5, iclass 30, count 2 2006.257.02:04:59.61#ibcon#read 5, iclass 30, count 2 2006.257.02:04:59.61#ibcon#about to read 6, iclass 30, count 2 2006.257.02:04:59.61#ibcon#read 6, iclass 30, count 2 2006.257.02:04:59.61#ibcon#end of sib2, iclass 30, count 2 2006.257.02:04:59.61#ibcon#*mode == 0, iclass 30, count 2 2006.257.02:04:59.61#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.02:04:59.61#ibcon#[25=AT08-04\r\n] 2006.257.02:04:59.61#ibcon#*before write, iclass 30, count 2 2006.257.02:04:59.61#ibcon#enter sib2, iclass 30, count 2 2006.257.02:04:59.61#ibcon#flushed, iclass 30, count 2 2006.257.02:04:59.61#ibcon#about to write, iclass 30, count 2 2006.257.02:04:59.61#ibcon#wrote, iclass 30, count 2 2006.257.02:04:59.61#ibcon#about to read 3, iclass 30, count 2 2006.257.02:04:59.64#ibcon#read 3, iclass 30, count 2 2006.257.02:04:59.64#ibcon#about to read 4, iclass 30, count 2 2006.257.02:04:59.64#ibcon#read 4, iclass 30, count 2 2006.257.02:04:59.64#ibcon#about to read 5, iclass 30, count 2 2006.257.02:04:59.64#ibcon#read 5, iclass 30, count 2 2006.257.02:04:59.64#ibcon#about to read 6, iclass 30, count 2 2006.257.02:04:59.64#ibcon#read 6, iclass 30, count 2 2006.257.02:04:59.64#ibcon#end of sib2, iclass 30, count 2 2006.257.02:04:59.64#ibcon#*after write, iclass 30, count 2 2006.257.02:04:59.64#ibcon#*before return 0, iclass 30, count 2 2006.257.02:04:59.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:04:59.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:04:59.64#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.02:04:59.64#ibcon#ireg 7 cls_cnt 0 2006.257.02:04:59.64#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:04:59.76#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:04:59.76#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:04:59.76#ibcon#enter wrdev, iclass 30, count 0 2006.257.02:04:59.76#ibcon#first serial, iclass 30, count 0 2006.257.02:04:59.76#ibcon#enter sib2, iclass 30, count 0 2006.257.02:04:59.76#ibcon#flushed, iclass 30, count 0 2006.257.02:04:59.76#ibcon#about to write, iclass 30, count 0 2006.257.02:04:59.76#ibcon#wrote, iclass 30, count 0 2006.257.02:04:59.76#ibcon#about to read 3, iclass 30, count 0 2006.257.02:04:59.78#ibcon#read 3, iclass 30, count 0 2006.257.02:04:59.78#ibcon#about to read 4, iclass 30, count 0 2006.257.02:04:59.78#ibcon#read 4, iclass 30, count 0 2006.257.02:04:59.78#ibcon#about to read 5, iclass 30, count 0 2006.257.02:04:59.78#ibcon#read 5, iclass 30, count 0 2006.257.02:04:59.78#ibcon#about to read 6, iclass 30, count 0 2006.257.02:04:59.78#ibcon#read 6, iclass 30, count 0 2006.257.02:04:59.78#ibcon#end of sib2, iclass 30, count 0 2006.257.02:04:59.78#ibcon#*mode == 0, iclass 30, count 0 2006.257.02:04:59.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.02:04:59.78#ibcon#[25=USB\r\n] 2006.257.02:04:59.78#ibcon#*before write, iclass 30, count 0 2006.257.02:04:59.78#ibcon#enter sib2, iclass 30, count 0 2006.257.02:04:59.78#ibcon#flushed, iclass 30, count 0 2006.257.02:04:59.78#ibcon#about to write, iclass 30, count 0 2006.257.02:04:59.78#ibcon#wrote, iclass 30, count 0 2006.257.02:04:59.78#ibcon#about to read 3, iclass 30, count 0 2006.257.02:04:59.81#ibcon#read 3, iclass 30, count 0 2006.257.02:04:59.81#ibcon#about to read 4, iclass 30, count 0 2006.257.02:04:59.81#ibcon#read 4, iclass 30, count 0 2006.257.02:04:59.81#ibcon#about to read 5, iclass 30, count 0 2006.257.02:04:59.81#ibcon#read 5, iclass 30, count 0 2006.257.02:04:59.81#ibcon#about to read 6, iclass 30, count 0 2006.257.02:04:59.81#ibcon#read 6, iclass 30, count 0 2006.257.02:04:59.81#ibcon#end of sib2, iclass 30, count 0 2006.257.02:04:59.81#ibcon#*after write, iclass 30, count 0 2006.257.02:04:59.81#ibcon#*before return 0, iclass 30, count 0 2006.257.02:04:59.81#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:04:59.81#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:04:59.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.02:04:59.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.02:04:59.81$vck44/vblo=1,629.99 2006.257.02:04:59.81#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.02:04:59.81#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.02:04:59.81#ibcon#ireg 17 cls_cnt 0 2006.257.02:04:59.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:59.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:59.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:59.81#ibcon#enter wrdev, iclass 32, count 0 2006.257.02:04:59.81#ibcon#first serial, iclass 32, count 0 2006.257.02:04:59.81#ibcon#enter sib2, iclass 32, count 0 2006.257.02:04:59.81#ibcon#flushed, iclass 32, count 0 2006.257.02:04:59.81#ibcon#about to write, iclass 32, count 0 2006.257.02:04:59.81#ibcon#wrote, iclass 32, count 0 2006.257.02:04:59.81#ibcon#about to read 3, iclass 32, count 0 2006.257.02:04:59.83#ibcon#read 3, iclass 32, count 0 2006.257.02:04:59.83#ibcon#about to read 4, iclass 32, count 0 2006.257.02:04:59.83#ibcon#read 4, iclass 32, count 0 2006.257.02:04:59.83#ibcon#about to read 5, iclass 32, count 0 2006.257.02:04:59.83#ibcon#read 5, iclass 32, count 0 2006.257.02:04:59.83#ibcon#about to read 6, iclass 32, count 0 2006.257.02:04:59.83#ibcon#read 6, iclass 32, count 0 2006.257.02:04:59.83#ibcon#end of sib2, iclass 32, count 0 2006.257.02:04:59.83#ibcon#*mode == 0, iclass 32, count 0 2006.257.02:04:59.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.02:04:59.83#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:04:59.83#ibcon#*before write, iclass 32, count 0 2006.257.02:04:59.83#ibcon#enter sib2, iclass 32, count 0 2006.257.02:04:59.83#ibcon#flushed, iclass 32, count 0 2006.257.02:04:59.83#ibcon#about to write, iclass 32, count 0 2006.257.02:04:59.83#ibcon#wrote, iclass 32, count 0 2006.257.02:04:59.83#ibcon#about to read 3, iclass 32, count 0 2006.257.02:04:59.87#ibcon#read 3, iclass 32, count 0 2006.257.02:04:59.87#ibcon#about to read 4, iclass 32, count 0 2006.257.02:04:59.87#ibcon#read 4, iclass 32, count 0 2006.257.02:04:59.87#ibcon#about to read 5, iclass 32, count 0 2006.257.02:04:59.87#ibcon#read 5, iclass 32, count 0 2006.257.02:04:59.87#ibcon#about to read 6, iclass 32, count 0 2006.257.02:04:59.87#ibcon#read 6, iclass 32, count 0 2006.257.02:04:59.87#ibcon#end of sib2, iclass 32, count 0 2006.257.02:04:59.87#ibcon#*after write, iclass 32, count 0 2006.257.02:04:59.87#ibcon#*before return 0, iclass 32, count 0 2006.257.02:04:59.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:59.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:04:59.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.02:04:59.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.02:04:59.87$vck44/vb=1,4 2006.257.02:04:59.87#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.02:04:59.87#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.02:04:59.87#ibcon#ireg 11 cls_cnt 2 2006.257.02:04:59.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:59.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:59.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:59.87#ibcon#enter wrdev, iclass 34, count 2 2006.257.02:04:59.87#ibcon#first serial, iclass 34, count 2 2006.257.02:04:59.87#ibcon#enter sib2, iclass 34, count 2 2006.257.02:04:59.87#ibcon#flushed, iclass 34, count 2 2006.257.02:04:59.87#ibcon#about to write, iclass 34, count 2 2006.257.02:04:59.87#ibcon#wrote, iclass 34, count 2 2006.257.02:04:59.87#ibcon#about to read 3, iclass 34, count 2 2006.257.02:04:59.89#ibcon#read 3, iclass 34, count 2 2006.257.02:04:59.89#ibcon#about to read 4, iclass 34, count 2 2006.257.02:04:59.89#ibcon#read 4, iclass 34, count 2 2006.257.02:04:59.89#ibcon#about to read 5, iclass 34, count 2 2006.257.02:04:59.89#ibcon#read 5, iclass 34, count 2 2006.257.02:04:59.89#ibcon#about to read 6, iclass 34, count 2 2006.257.02:04:59.89#ibcon#read 6, iclass 34, count 2 2006.257.02:04:59.89#ibcon#end of sib2, iclass 34, count 2 2006.257.02:04:59.89#ibcon#*mode == 0, iclass 34, count 2 2006.257.02:04:59.89#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.02:04:59.89#ibcon#[27=AT01-04\r\n] 2006.257.02:04:59.89#ibcon#*before write, iclass 34, count 2 2006.257.02:04:59.89#ibcon#enter sib2, iclass 34, count 2 2006.257.02:04:59.89#ibcon#flushed, iclass 34, count 2 2006.257.02:04:59.89#ibcon#about to write, iclass 34, count 2 2006.257.02:04:59.89#ibcon#wrote, iclass 34, count 2 2006.257.02:04:59.89#ibcon#about to read 3, iclass 34, count 2 2006.257.02:04:59.92#ibcon#read 3, iclass 34, count 2 2006.257.02:04:59.92#ibcon#about to read 4, iclass 34, count 2 2006.257.02:04:59.92#ibcon#read 4, iclass 34, count 2 2006.257.02:04:59.92#ibcon#about to read 5, iclass 34, count 2 2006.257.02:04:59.92#ibcon#read 5, iclass 34, count 2 2006.257.02:04:59.92#ibcon#about to read 6, iclass 34, count 2 2006.257.02:04:59.92#ibcon#read 6, iclass 34, count 2 2006.257.02:04:59.92#ibcon#end of sib2, iclass 34, count 2 2006.257.02:04:59.92#ibcon#*after write, iclass 34, count 2 2006.257.02:04:59.92#ibcon#*before return 0, iclass 34, count 2 2006.257.02:04:59.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:59.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:04:59.92#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.02:04:59.92#ibcon#ireg 7 cls_cnt 0 2006.257.02:04:59.92#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:05:00.05#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:05:00.05#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:05:00.05#ibcon#enter wrdev, iclass 34, count 0 2006.257.02:05:00.05#ibcon#first serial, iclass 34, count 0 2006.257.02:05:00.05#ibcon#enter sib2, iclass 34, count 0 2006.257.02:05:00.05#ibcon#flushed, iclass 34, count 0 2006.257.02:05:00.05#ibcon#about to write, iclass 34, count 0 2006.257.02:05:00.05#ibcon#wrote, iclass 34, count 0 2006.257.02:05:00.05#ibcon#about to read 3, iclass 34, count 0 2006.257.02:05:00.06#ibcon#read 3, iclass 34, count 0 2006.257.02:05:00.06#ibcon#about to read 4, iclass 34, count 0 2006.257.02:05:00.06#ibcon#read 4, iclass 34, count 0 2006.257.02:05:00.06#ibcon#about to read 5, iclass 34, count 0 2006.257.02:05:00.06#ibcon#read 5, iclass 34, count 0 2006.257.02:05:00.06#ibcon#about to read 6, iclass 34, count 0 2006.257.02:05:00.06#ibcon#read 6, iclass 34, count 0 2006.257.02:05:00.06#ibcon#end of sib2, iclass 34, count 0 2006.257.02:05:00.06#ibcon#*mode == 0, iclass 34, count 0 2006.257.02:05:00.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.02:05:00.06#ibcon#[27=USB\r\n] 2006.257.02:05:00.06#ibcon#*before write, iclass 34, count 0 2006.257.02:05:00.06#ibcon#enter sib2, iclass 34, count 0 2006.257.02:05:00.06#ibcon#flushed, iclass 34, count 0 2006.257.02:05:00.06#ibcon#about to write, iclass 34, count 0 2006.257.02:05:00.06#ibcon#wrote, iclass 34, count 0 2006.257.02:05:00.06#ibcon#about to read 3, iclass 34, count 0 2006.257.02:05:00.09#ibcon#read 3, iclass 34, count 0 2006.257.02:05:00.09#ibcon#about to read 4, iclass 34, count 0 2006.257.02:05:00.09#ibcon#read 4, iclass 34, count 0 2006.257.02:05:00.09#ibcon#about to read 5, iclass 34, count 0 2006.257.02:05:00.09#ibcon#read 5, iclass 34, count 0 2006.257.02:05:00.09#ibcon#about to read 6, iclass 34, count 0 2006.257.02:05:00.09#ibcon#read 6, iclass 34, count 0 2006.257.02:05:00.09#ibcon#end of sib2, iclass 34, count 0 2006.257.02:05:00.09#ibcon#*after write, iclass 34, count 0 2006.257.02:05:00.09#ibcon#*before return 0, iclass 34, count 0 2006.257.02:05:00.09#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:05:00.09#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:05:00.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.02:05:00.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.02:05:00.09$vck44/vblo=2,634.99 2006.257.02:05:00.09#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.02:05:00.09#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.02:05:00.09#ibcon#ireg 17 cls_cnt 0 2006.257.02:05:00.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:05:00.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:05:00.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:05:00.09#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:05:00.09#ibcon#first serial, iclass 36, count 0 2006.257.02:05:00.09#ibcon#enter sib2, iclass 36, count 0 2006.257.02:05:00.09#ibcon#flushed, iclass 36, count 0 2006.257.02:05:00.09#ibcon#about to write, iclass 36, count 0 2006.257.02:05:00.09#ibcon#wrote, iclass 36, count 0 2006.257.02:05:00.09#ibcon#about to read 3, iclass 36, count 0 2006.257.02:05:00.11#ibcon#read 3, iclass 36, count 0 2006.257.02:05:00.11#ibcon#about to read 4, iclass 36, count 0 2006.257.02:05:00.11#ibcon#read 4, iclass 36, count 0 2006.257.02:05:00.11#ibcon#about to read 5, iclass 36, count 0 2006.257.02:05:00.11#ibcon#read 5, iclass 36, count 0 2006.257.02:05:00.11#ibcon#about to read 6, iclass 36, count 0 2006.257.02:05:00.11#ibcon#read 6, iclass 36, count 0 2006.257.02:05:00.11#ibcon#end of sib2, iclass 36, count 0 2006.257.02:05:00.11#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:05:00.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:05:00.11#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:05:00.11#ibcon#*before write, iclass 36, count 0 2006.257.02:05:00.11#ibcon#enter sib2, iclass 36, count 0 2006.257.02:05:00.11#ibcon#flushed, iclass 36, count 0 2006.257.02:05:00.11#ibcon#about to write, iclass 36, count 0 2006.257.02:05:00.11#ibcon#wrote, iclass 36, count 0 2006.257.02:05:00.11#ibcon#about to read 3, iclass 36, count 0 2006.257.02:05:00.15#ibcon#read 3, iclass 36, count 0 2006.257.02:05:00.15#ibcon#about to read 4, iclass 36, count 0 2006.257.02:05:00.15#ibcon#read 4, iclass 36, count 0 2006.257.02:05:00.15#ibcon#about to read 5, iclass 36, count 0 2006.257.02:05:00.15#ibcon#read 5, iclass 36, count 0 2006.257.02:05:00.15#ibcon#about to read 6, iclass 36, count 0 2006.257.02:05:00.15#ibcon#read 6, iclass 36, count 0 2006.257.02:05:00.15#ibcon#end of sib2, iclass 36, count 0 2006.257.02:05:00.15#ibcon#*after write, iclass 36, count 0 2006.257.02:05:00.15#ibcon#*before return 0, iclass 36, count 0 2006.257.02:05:00.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:05:00.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:05:00.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:05:00.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:05:00.15$vck44/vb=2,5 2006.257.02:05:00.15#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.02:05:00.15#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.02:05:00.15#ibcon#ireg 11 cls_cnt 2 2006.257.02:05:00.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:05:00.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:05:00.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:05:00.21#ibcon#enter wrdev, iclass 38, count 2 2006.257.02:05:00.21#ibcon#first serial, iclass 38, count 2 2006.257.02:05:00.21#ibcon#enter sib2, iclass 38, count 2 2006.257.02:05:00.21#ibcon#flushed, iclass 38, count 2 2006.257.02:05:00.21#ibcon#about to write, iclass 38, count 2 2006.257.02:05:00.21#ibcon#wrote, iclass 38, count 2 2006.257.02:05:00.21#ibcon#about to read 3, iclass 38, count 2 2006.257.02:05:00.23#ibcon#read 3, iclass 38, count 2 2006.257.02:05:00.23#ibcon#about to read 4, iclass 38, count 2 2006.257.02:05:00.23#ibcon#read 4, iclass 38, count 2 2006.257.02:05:00.23#ibcon#about to read 5, iclass 38, count 2 2006.257.02:05:00.23#ibcon#read 5, iclass 38, count 2 2006.257.02:05:00.23#ibcon#about to read 6, iclass 38, count 2 2006.257.02:05:00.23#ibcon#read 6, iclass 38, count 2 2006.257.02:05:00.23#ibcon#end of sib2, iclass 38, count 2 2006.257.02:05:00.23#ibcon#*mode == 0, iclass 38, count 2 2006.257.02:05:00.23#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.02:05:00.23#ibcon#[27=AT02-05\r\n] 2006.257.02:05:00.23#ibcon#*before write, iclass 38, count 2 2006.257.02:05:00.23#ibcon#enter sib2, iclass 38, count 2 2006.257.02:05:00.23#ibcon#flushed, iclass 38, count 2 2006.257.02:05:00.23#ibcon#about to write, iclass 38, count 2 2006.257.02:05:00.23#ibcon#wrote, iclass 38, count 2 2006.257.02:05:00.23#ibcon#about to read 3, iclass 38, count 2 2006.257.02:05:00.26#ibcon#read 3, iclass 38, count 2 2006.257.02:05:00.26#ibcon#about to read 4, iclass 38, count 2 2006.257.02:05:00.26#ibcon#read 4, iclass 38, count 2 2006.257.02:05:00.26#ibcon#about to read 5, iclass 38, count 2 2006.257.02:05:00.26#ibcon#read 5, iclass 38, count 2 2006.257.02:05:00.26#ibcon#about to read 6, iclass 38, count 2 2006.257.02:05:00.26#ibcon#read 6, iclass 38, count 2 2006.257.02:05:00.26#ibcon#end of sib2, iclass 38, count 2 2006.257.02:05:00.26#ibcon#*after write, iclass 38, count 2 2006.257.02:05:00.26#ibcon#*before return 0, iclass 38, count 2 2006.257.02:05:00.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:05:00.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:05:00.26#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.02:05:00.26#ibcon#ireg 7 cls_cnt 0 2006.257.02:05:00.26#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:05:00.38#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:05:00.38#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:05:00.38#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:05:00.38#ibcon#first serial, iclass 38, count 0 2006.257.02:05:00.38#ibcon#enter sib2, iclass 38, count 0 2006.257.02:05:00.38#ibcon#flushed, iclass 38, count 0 2006.257.02:05:00.38#ibcon#about to write, iclass 38, count 0 2006.257.02:05:00.38#ibcon#wrote, iclass 38, count 0 2006.257.02:05:00.38#ibcon#about to read 3, iclass 38, count 0 2006.257.02:05:00.40#ibcon#read 3, iclass 38, count 0 2006.257.02:05:00.40#ibcon#about to read 4, iclass 38, count 0 2006.257.02:05:00.40#ibcon#read 4, iclass 38, count 0 2006.257.02:05:00.40#ibcon#about to read 5, iclass 38, count 0 2006.257.02:05:00.40#ibcon#read 5, iclass 38, count 0 2006.257.02:05:00.40#ibcon#about to read 6, iclass 38, count 0 2006.257.02:05:00.40#ibcon#read 6, iclass 38, count 0 2006.257.02:05:00.40#ibcon#end of sib2, iclass 38, count 0 2006.257.02:05:00.40#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:05:00.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:05:00.40#ibcon#[27=USB\r\n] 2006.257.02:05:00.40#ibcon#*before write, iclass 38, count 0 2006.257.02:05:00.40#ibcon#enter sib2, iclass 38, count 0 2006.257.02:05:00.40#ibcon#flushed, iclass 38, count 0 2006.257.02:05:00.40#ibcon#about to write, iclass 38, count 0 2006.257.02:05:00.40#ibcon#wrote, iclass 38, count 0 2006.257.02:05:00.40#ibcon#about to read 3, iclass 38, count 0 2006.257.02:05:00.43#ibcon#read 3, iclass 38, count 0 2006.257.02:05:00.43#ibcon#about to read 4, iclass 38, count 0 2006.257.02:05:00.43#ibcon#read 4, iclass 38, count 0 2006.257.02:05:00.43#ibcon#about to read 5, iclass 38, count 0 2006.257.02:05:00.43#ibcon#read 5, iclass 38, count 0 2006.257.02:05:00.43#ibcon#about to read 6, iclass 38, count 0 2006.257.02:05:00.43#ibcon#read 6, iclass 38, count 0 2006.257.02:05:00.43#ibcon#end of sib2, iclass 38, count 0 2006.257.02:05:00.43#ibcon#*after write, iclass 38, count 0 2006.257.02:05:00.43#ibcon#*before return 0, iclass 38, count 0 2006.257.02:05:00.43#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:05:00.43#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:05:00.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:05:00.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:05:00.43$vck44/vblo=3,649.99 2006.257.02:05:00.43#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.02:05:00.43#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.02:05:00.43#ibcon#ireg 17 cls_cnt 0 2006.257.02:05:00.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:05:00.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:05:00.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:05:00.43#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:05:00.43#ibcon#first serial, iclass 40, count 0 2006.257.02:05:00.43#ibcon#enter sib2, iclass 40, count 0 2006.257.02:05:00.43#ibcon#flushed, iclass 40, count 0 2006.257.02:05:00.43#ibcon#about to write, iclass 40, count 0 2006.257.02:05:00.43#ibcon#wrote, iclass 40, count 0 2006.257.02:05:00.43#ibcon#about to read 3, iclass 40, count 0 2006.257.02:05:00.45#ibcon#read 3, iclass 40, count 0 2006.257.02:05:00.45#ibcon#about to read 4, iclass 40, count 0 2006.257.02:05:00.45#ibcon#read 4, iclass 40, count 0 2006.257.02:05:00.45#ibcon#about to read 5, iclass 40, count 0 2006.257.02:05:00.45#ibcon#read 5, iclass 40, count 0 2006.257.02:05:00.45#ibcon#about to read 6, iclass 40, count 0 2006.257.02:05:00.45#ibcon#read 6, iclass 40, count 0 2006.257.02:05:00.45#ibcon#end of sib2, iclass 40, count 0 2006.257.02:05:00.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:05:00.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:05:00.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:05:00.45#ibcon#*before write, iclass 40, count 0 2006.257.02:05:00.45#ibcon#enter sib2, iclass 40, count 0 2006.257.02:05:00.45#ibcon#flushed, iclass 40, count 0 2006.257.02:05:00.45#ibcon#about to write, iclass 40, count 0 2006.257.02:05:00.45#ibcon#wrote, iclass 40, count 0 2006.257.02:05:00.45#ibcon#about to read 3, iclass 40, count 0 2006.257.02:05:00.49#ibcon#read 3, iclass 40, count 0 2006.257.02:05:00.49#ibcon#about to read 4, iclass 40, count 0 2006.257.02:05:00.49#ibcon#read 4, iclass 40, count 0 2006.257.02:05:00.49#ibcon#about to read 5, iclass 40, count 0 2006.257.02:05:00.49#ibcon#read 5, iclass 40, count 0 2006.257.02:05:00.49#ibcon#about to read 6, iclass 40, count 0 2006.257.02:05:00.49#ibcon#read 6, iclass 40, count 0 2006.257.02:05:00.49#ibcon#end of sib2, iclass 40, count 0 2006.257.02:05:00.49#ibcon#*after write, iclass 40, count 0 2006.257.02:05:00.49#ibcon#*before return 0, iclass 40, count 0 2006.257.02:05:00.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:05:00.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:05:00.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:05:00.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:05:00.49$vck44/vb=3,4 2006.257.02:05:00.49#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.02:05:00.49#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.02:05:00.49#ibcon#ireg 11 cls_cnt 2 2006.257.02:05:00.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:05:00.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:05:00.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:05:00.55#ibcon#enter wrdev, iclass 4, count 2 2006.257.02:05:00.55#ibcon#first serial, iclass 4, count 2 2006.257.02:05:00.55#ibcon#enter sib2, iclass 4, count 2 2006.257.02:05:00.55#ibcon#flushed, iclass 4, count 2 2006.257.02:05:00.55#ibcon#about to write, iclass 4, count 2 2006.257.02:05:00.55#ibcon#wrote, iclass 4, count 2 2006.257.02:05:00.55#ibcon#about to read 3, iclass 4, count 2 2006.257.02:05:00.57#ibcon#read 3, iclass 4, count 2 2006.257.02:05:00.57#ibcon#about to read 4, iclass 4, count 2 2006.257.02:05:00.57#ibcon#read 4, iclass 4, count 2 2006.257.02:05:00.57#ibcon#about to read 5, iclass 4, count 2 2006.257.02:05:00.57#ibcon#read 5, iclass 4, count 2 2006.257.02:05:00.57#ibcon#about to read 6, iclass 4, count 2 2006.257.02:05:00.57#ibcon#read 6, iclass 4, count 2 2006.257.02:05:00.57#ibcon#end of sib2, iclass 4, count 2 2006.257.02:05:00.57#ibcon#*mode == 0, iclass 4, count 2 2006.257.02:05:00.57#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.02:05:00.57#ibcon#[27=AT03-04\r\n] 2006.257.02:05:00.57#ibcon#*before write, iclass 4, count 2 2006.257.02:05:00.57#ibcon#enter sib2, iclass 4, count 2 2006.257.02:05:00.57#ibcon#flushed, iclass 4, count 2 2006.257.02:05:00.57#ibcon#about to write, iclass 4, count 2 2006.257.02:05:00.57#ibcon#wrote, iclass 4, count 2 2006.257.02:05:00.57#ibcon#about to read 3, iclass 4, count 2 2006.257.02:05:00.60#ibcon#read 3, iclass 4, count 2 2006.257.02:05:00.60#ibcon#about to read 4, iclass 4, count 2 2006.257.02:05:00.60#ibcon#read 4, iclass 4, count 2 2006.257.02:05:00.60#ibcon#about to read 5, iclass 4, count 2 2006.257.02:05:00.60#ibcon#read 5, iclass 4, count 2 2006.257.02:05:00.60#ibcon#about to read 6, iclass 4, count 2 2006.257.02:05:00.60#ibcon#read 6, iclass 4, count 2 2006.257.02:05:00.60#ibcon#end of sib2, iclass 4, count 2 2006.257.02:05:00.60#ibcon#*after write, iclass 4, count 2 2006.257.02:05:00.60#ibcon#*before return 0, iclass 4, count 2 2006.257.02:05:00.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:05:00.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:05:00.60#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.02:05:00.60#ibcon#ireg 7 cls_cnt 0 2006.257.02:05:00.60#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:05:00.72#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:05:00.72#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:05:00.72#ibcon#enter wrdev, iclass 4, count 0 2006.257.02:05:00.72#ibcon#first serial, iclass 4, count 0 2006.257.02:05:00.72#ibcon#enter sib2, iclass 4, count 0 2006.257.02:05:00.72#ibcon#flushed, iclass 4, count 0 2006.257.02:05:00.72#ibcon#about to write, iclass 4, count 0 2006.257.02:05:00.72#ibcon#wrote, iclass 4, count 0 2006.257.02:05:00.72#ibcon#about to read 3, iclass 4, count 0 2006.257.02:05:00.74#ibcon#read 3, iclass 4, count 0 2006.257.02:05:00.74#ibcon#about to read 4, iclass 4, count 0 2006.257.02:05:00.74#ibcon#read 4, iclass 4, count 0 2006.257.02:05:00.74#ibcon#about to read 5, iclass 4, count 0 2006.257.02:05:00.74#ibcon#read 5, iclass 4, count 0 2006.257.02:05:00.74#ibcon#about to read 6, iclass 4, count 0 2006.257.02:05:00.74#ibcon#read 6, iclass 4, count 0 2006.257.02:05:00.74#ibcon#end of sib2, iclass 4, count 0 2006.257.02:05:00.74#ibcon#*mode == 0, iclass 4, count 0 2006.257.02:05:00.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.02:05:00.74#ibcon#[27=USB\r\n] 2006.257.02:05:00.74#ibcon#*before write, iclass 4, count 0 2006.257.02:05:00.74#ibcon#enter sib2, iclass 4, count 0 2006.257.02:05:00.74#ibcon#flushed, iclass 4, count 0 2006.257.02:05:00.74#ibcon#about to write, iclass 4, count 0 2006.257.02:05:00.74#ibcon#wrote, iclass 4, count 0 2006.257.02:05:00.74#ibcon#about to read 3, iclass 4, count 0 2006.257.02:05:00.77#ibcon#read 3, iclass 4, count 0 2006.257.02:05:00.77#ibcon#about to read 4, iclass 4, count 0 2006.257.02:05:00.77#ibcon#read 4, iclass 4, count 0 2006.257.02:05:00.77#ibcon#about to read 5, iclass 4, count 0 2006.257.02:05:00.77#ibcon#read 5, iclass 4, count 0 2006.257.02:05:00.77#ibcon#about to read 6, iclass 4, count 0 2006.257.02:05:00.77#ibcon#read 6, iclass 4, count 0 2006.257.02:05:00.77#ibcon#end of sib2, iclass 4, count 0 2006.257.02:05:00.77#ibcon#*after write, iclass 4, count 0 2006.257.02:05:00.77#ibcon#*before return 0, iclass 4, count 0 2006.257.02:05:00.77#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:05:00.77#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:05:00.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.02:05:00.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.02:05:00.77$vck44/vblo=4,679.99 2006.257.02:05:00.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.02:05:00.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.02:05:00.77#ibcon#ireg 17 cls_cnt 0 2006.257.02:05:00.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:05:00.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:05:00.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:05:00.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.02:05:00.77#ibcon#first serial, iclass 6, count 0 2006.257.02:05:00.77#ibcon#enter sib2, iclass 6, count 0 2006.257.02:05:00.77#ibcon#flushed, iclass 6, count 0 2006.257.02:05:00.77#ibcon#about to write, iclass 6, count 0 2006.257.02:05:00.77#ibcon#wrote, iclass 6, count 0 2006.257.02:05:00.77#ibcon#about to read 3, iclass 6, count 0 2006.257.02:05:00.80#ibcon#read 3, iclass 6, count 0 2006.257.02:05:00.80#ibcon#about to read 4, iclass 6, count 0 2006.257.02:05:00.80#ibcon#read 4, iclass 6, count 0 2006.257.02:05:00.80#ibcon#about to read 5, iclass 6, count 0 2006.257.02:05:00.80#ibcon#read 5, iclass 6, count 0 2006.257.02:05:00.80#ibcon#about to read 6, iclass 6, count 0 2006.257.02:05:00.80#ibcon#read 6, iclass 6, count 0 2006.257.02:05:00.80#ibcon#end of sib2, iclass 6, count 0 2006.257.02:05:00.80#ibcon#*mode == 0, iclass 6, count 0 2006.257.02:05:00.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.02:05:00.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:05:00.80#ibcon#*before write, iclass 6, count 0 2006.257.02:05:00.80#ibcon#enter sib2, iclass 6, count 0 2006.257.02:05:00.80#ibcon#flushed, iclass 6, count 0 2006.257.02:05:00.80#ibcon#about to write, iclass 6, count 0 2006.257.02:05:00.80#ibcon#wrote, iclass 6, count 0 2006.257.02:05:00.80#ibcon#about to read 3, iclass 6, count 0 2006.257.02:05:00.84#ibcon#read 3, iclass 6, count 0 2006.257.02:05:00.84#ibcon#about to read 4, iclass 6, count 0 2006.257.02:05:00.84#ibcon#read 4, iclass 6, count 0 2006.257.02:05:00.84#ibcon#about to read 5, iclass 6, count 0 2006.257.02:05:00.84#ibcon#read 5, iclass 6, count 0 2006.257.02:05:00.84#ibcon#about to read 6, iclass 6, count 0 2006.257.02:05:00.84#ibcon#read 6, iclass 6, count 0 2006.257.02:05:00.84#ibcon#end of sib2, iclass 6, count 0 2006.257.02:05:00.84#ibcon#*after write, iclass 6, count 0 2006.257.02:05:00.84#ibcon#*before return 0, iclass 6, count 0 2006.257.02:05:00.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:05:00.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:05:00.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.02:05:00.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.02:05:00.84$vck44/vb=4,5 2006.257.02:05:00.84#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.02:05:00.84#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.02:05:00.84#ibcon#ireg 11 cls_cnt 2 2006.257.02:05:00.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:05:00.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:05:00.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:05:00.89#ibcon#enter wrdev, iclass 10, count 2 2006.257.02:05:00.89#ibcon#first serial, iclass 10, count 2 2006.257.02:05:00.89#ibcon#enter sib2, iclass 10, count 2 2006.257.02:05:00.89#ibcon#flushed, iclass 10, count 2 2006.257.02:05:00.89#ibcon#about to write, iclass 10, count 2 2006.257.02:05:00.89#ibcon#wrote, iclass 10, count 2 2006.257.02:05:00.89#ibcon#about to read 3, iclass 10, count 2 2006.257.02:05:00.91#ibcon#read 3, iclass 10, count 2 2006.257.02:05:00.91#ibcon#about to read 4, iclass 10, count 2 2006.257.02:05:00.91#ibcon#read 4, iclass 10, count 2 2006.257.02:05:00.91#ibcon#about to read 5, iclass 10, count 2 2006.257.02:05:00.91#ibcon#read 5, iclass 10, count 2 2006.257.02:05:00.91#ibcon#about to read 6, iclass 10, count 2 2006.257.02:05:00.91#ibcon#read 6, iclass 10, count 2 2006.257.02:05:00.91#ibcon#end of sib2, iclass 10, count 2 2006.257.02:05:00.91#ibcon#*mode == 0, iclass 10, count 2 2006.257.02:05:00.91#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.02:05:00.91#ibcon#[27=AT04-05\r\n] 2006.257.02:05:00.91#ibcon#*before write, iclass 10, count 2 2006.257.02:05:00.91#ibcon#enter sib2, iclass 10, count 2 2006.257.02:05:00.91#ibcon#flushed, iclass 10, count 2 2006.257.02:05:00.91#ibcon#about to write, iclass 10, count 2 2006.257.02:05:00.91#ibcon#wrote, iclass 10, count 2 2006.257.02:05:00.91#ibcon#about to read 3, iclass 10, count 2 2006.257.02:05:00.94#ibcon#read 3, iclass 10, count 2 2006.257.02:05:00.94#ibcon#about to read 4, iclass 10, count 2 2006.257.02:05:00.94#ibcon#read 4, iclass 10, count 2 2006.257.02:05:00.94#ibcon#about to read 5, iclass 10, count 2 2006.257.02:05:00.94#ibcon#read 5, iclass 10, count 2 2006.257.02:05:00.94#ibcon#about to read 6, iclass 10, count 2 2006.257.02:05:00.94#ibcon#read 6, iclass 10, count 2 2006.257.02:05:00.94#ibcon#end of sib2, iclass 10, count 2 2006.257.02:05:00.94#ibcon#*after write, iclass 10, count 2 2006.257.02:05:00.94#ibcon#*before return 0, iclass 10, count 2 2006.257.02:05:00.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:05:00.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:05:00.94#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.02:05:00.94#ibcon#ireg 7 cls_cnt 0 2006.257.02:05:00.94#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:05:01.06#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:05:01.06#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:05:01.06#ibcon#enter wrdev, iclass 10, count 0 2006.257.02:05:01.06#ibcon#first serial, iclass 10, count 0 2006.257.02:05:01.06#ibcon#enter sib2, iclass 10, count 0 2006.257.02:05:01.06#ibcon#flushed, iclass 10, count 0 2006.257.02:05:01.06#ibcon#about to write, iclass 10, count 0 2006.257.02:05:01.06#ibcon#wrote, iclass 10, count 0 2006.257.02:05:01.06#ibcon#about to read 3, iclass 10, count 0 2006.257.02:05:01.08#ibcon#read 3, iclass 10, count 0 2006.257.02:05:01.08#ibcon#about to read 4, iclass 10, count 0 2006.257.02:05:01.08#ibcon#read 4, iclass 10, count 0 2006.257.02:05:01.08#ibcon#about to read 5, iclass 10, count 0 2006.257.02:05:01.08#ibcon#read 5, iclass 10, count 0 2006.257.02:05:01.08#ibcon#about to read 6, iclass 10, count 0 2006.257.02:05:01.08#ibcon#read 6, iclass 10, count 0 2006.257.02:05:01.08#ibcon#end of sib2, iclass 10, count 0 2006.257.02:05:01.08#ibcon#*mode == 0, iclass 10, count 0 2006.257.02:05:01.08#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.02:05:01.08#ibcon#[27=USB\r\n] 2006.257.02:05:01.08#ibcon#*before write, iclass 10, count 0 2006.257.02:05:01.08#ibcon#enter sib2, iclass 10, count 0 2006.257.02:05:01.08#ibcon#flushed, iclass 10, count 0 2006.257.02:05:01.08#ibcon#about to write, iclass 10, count 0 2006.257.02:05:01.08#ibcon#wrote, iclass 10, count 0 2006.257.02:05:01.08#ibcon#about to read 3, iclass 10, count 0 2006.257.02:05:01.11#ibcon#read 3, iclass 10, count 0 2006.257.02:05:01.11#ibcon#about to read 4, iclass 10, count 0 2006.257.02:05:01.11#ibcon#read 4, iclass 10, count 0 2006.257.02:05:01.11#ibcon#about to read 5, iclass 10, count 0 2006.257.02:05:01.11#ibcon#read 5, iclass 10, count 0 2006.257.02:05:01.11#ibcon#about to read 6, iclass 10, count 0 2006.257.02:05:01.11#ibcon#read 6, iclass 10, count 0 2006.257.02:05:01.11#ibcon#end of sib2, iclass 10, count 0 2006.257.02:05:01.11#ibcon#*after write, iclass 10, count 0 2006.257.02:05:01.11#ibcon#*before return 0, iclass 10, count 0 2006.257.02:05:01.11#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:05:01.11#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:05:01.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.02:05:01.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.02:05:01.11$vck44/vblo=5,709.99 2006.257.02:05:01.11#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.02:05:01.11#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.02:05:01.11#ibcon#ireg 17 cls_cnt 0 2006.257.02:05:01.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:05:01.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:05:01.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:05:01.11#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:05:01.11#ibcon#first serial, iclass 12, count 0 2006.257.02:05:01.11#ibcon#enter sib2, iclass 12, count 0 2006.257.02:05:01.11#ibcon#flushed, iclass 12, count 0 2006.257.02:05:01.11#ibcon#about to write, iclass 12, count 0 2006.257.02:05:01.11#ibcon#wrote, iclass 12, count 0 2006.257.02:05:01.11#ibcon#about to read 3, iclass 12, count 0 2006.257.02:05:01.13#ibcon#read 3, iclass 12, count 0 2006.257.02:05:01.13#ibcon#about to read 4, iclass 12, count 0 2006.257.02:05:01.13#ibcon#read 4, iclass 12, count 0 2006.257.02:05:01.13#ibcon#about to read 5, iclass 12, count 0 2006.257.02:05:01.13#ibcon#read 5, iclass 12, count 0 2006.257.02:05:01.13#ibcon#about to read 6, iclass 12, count 0 2006.257.02:05:01.13#ibcon#read 6, iclass 12, count 0 2006.257.02:05:01.13#ibcon#end of sib2, iclass 12, count 0 2006.257.02:05:01.13#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:05:01.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:05:01.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:05:01.13#ibcon#*before write, iclass 12, count 0 2006.257.02:05:01.13#ibcon#enter sib2, iclass 12, count 0 2006.257.02:05:01.13#ibcon#flushed, iclass 12, count 0 2006.257.02:05:01.13#ibcon#about to write, iclass 12, count 0 2006.257.02:05:01.13#ibcon#wrote, iclass 12, count 0 2006.257.02:05:01.13#ibcon#about to read 3, iclass 12, count 0 2006.257.02:05:01.17#ibcon#read 3, iclass 12, count 0 2006.257.02:05:01.17#ibcon#about to read 4, iclass 12, count 0 2006.257.02:05:01.17#ibcon#read 4, iclass 12, count 0 2006.257.02:05:01.17#ibcon#about to read 5, iclass 12, count 0 2006.257.02:05:01.17#ibcon#read 5, iclass 12, count 0 2006.257.02:05:01.17#ibcon#about to read 6, iclass 12, count 0 2006.257.02:05:01.17#ibcon#read 6, iclass 12, count 0 2006.257.02:05:01.17#ibcon#end of sib2, iclass 12, count 0 2006.257.02:05:01.17#ibcon#*after write, iclass 12, count 0 2006.257.02:05:01.17#ibcon#*before return 0, iclass 12, count 0 2006.257.02:05:01.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:05:01.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:05:01.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:05:01.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:05:01.17$vck44/vb=5,4 2006.257.02:05:01.17#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.02:05:01.17#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.02:05:01.17#ibcon#ireg 11 cls_cnt 2 2006.257.02:05:01.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:05:01.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:05:01.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:05:01.23#ibcon#enter wrdev, iclass 14, count 2 2006.257.02:05:01.23#ibcon#first serial, iclass 14, count 2 2006.257.02:05:01.23#ibcon#enter sib2, iclass 14, count 2 2006.257.02:05:01.23#ibcon#flushed, iclass 14, count 2 2006.257.02:05:01.23#ibcon#about to write, iclass 14, count 2 2006.257.02:05:01.23#ibcon#wrote, iclass 14, count 2 2006.257.02:05:01.23#ibcon#about to read 3, iclass 14, count 2 2006.257.02:05:01.25#ibcon#read 3, iclass 14, count 2 2006.257.02:05:01.25#ibcon#about to read 4, iclass 14, count 2 2006.257.02:05:01.25#ibcon#read 4, iclass 14, count 2 2006.257.02:05:01.25#ibcon#about to read 5, iclass 14, count 2 2006.257.02:05:01.25#ibcon#read 5, iclass 14, count 2 2006.257.02:05:01.25#ibcon#about to read 6, iclass 14, count 2 2006.257.02:05:01.25#ibcon#read 6, iclass 14, count 2 2006.257.02:05:01.25#ibcon#end of sib2, iclass 14, count 2 2006.257.02:05:01.25#ibcon#*mode == 0, iclass 14, count 2 2006.257.02:05:01.25#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.02:05:01.25#ibcon#[27=AT05-04\r\n] 2006.257.02:05:01.25#ibcon#*before write, iclass 14, count 2 2006.257.02:05:01.25#ibcon#enter sib2, iclass 14, count 2 2006.257.02:05:01.25#ibcon#flushed, iclass 14, count 2 2006.257.02:05:01.25#ibcon#about to write, iclass 14, count 2 2006.257.02:05:01.25#ibcon#wrote, iclass 14, count 2 2006.257.02:05:01.25#ibcon#about to read 3, iclass 14, count 2 2006.257.02:05:01.28#ibcon#read 3, iclass 14, count 2 2006.257.02:05:01.28#ibcon#about to read 4, iclass 14, count 2 2006.257.02:05:01.28#ibcon#read 4, iclass 14, count 2 2006.257.02:05:01.28#ibcon#about to read 5, iclass 14, count 2 2006.257.02:05:01.28#ibcon#read 5, iclass 14, count 2 2006.257.02:05:01.28#ibcon#about to read 6, iclass 14, count 2 2006.257.02:05:01.28#ibcon#read 6, iclass 14, count 2 2006.257.02:05:01.28#ibcon#end of sib2, iclass 14, count 2 2006.257.02:05:01.28#ibcon#*after write, iclass 14, count 2 2006.257.02:05:01.28#ibcon#*before return 0, iclass 14, count 2 2006.257.02:05:01.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:05:01.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:05:01.28#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.02:05:01.28#ibcon#ireg 7 cls_cnt 0 2006.257.02:05:01.28#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:05:01.40#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:05:01.40#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:05:01.40#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:05:01.40#ibcon#first serial, iclass 14, count 0 2006.257.02:05:01.40#ibcon#enter sib2, iclass 14, count 0 2006.257.02:05:01.40#ibcon#flushed, iclass 14, count 0 2006.257.02:05:01.40#ibcon#about to write, iclass 14, count 0 2006.257.02:05:01.40#ibcon#wrote, iclass 14, count 0 2006.257.02:05:01.40#ibcon#about to read 3, iclass 14, count 0 2006.257.02:05:01.42#ibcon#read 3, iclass 14, count 0 2006.257.02:05:01.42#ibcon#about to read 4, iclass 14, count 0 2006.257.02:05:01.42#ibcon#read 4, iclass 14, count 0 2006.257.02:05:01.42#ibcon#about to read 5, iclass 14, count 0 2006.257.02:05:01.42#ibcon#read 5, iclass 14, count 0 2006.257.02:05:01.42#ibcon#about to read 6, iclass 14, count 0 2006.257.02:05:01.42#ibcon#read 6, iclass 14, count 0 2006.257.02:05:01.42#ibcon#end of sib2, iclass 14, count 0 2006.257.02:05:01.42#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:05:01.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:05:01.42#ibcon#[27=USB\r\n] 2006.257.02:05:01.42#ibcon#*before write, iclass 14, count 0 2006.257.02:05:01.42#ibcon#enter sib2, iclass 14, count 0 2006.257.02:05:01.42#ibcon#flushed, iclass 14, count 0 2006.257.02:05:01.42#ibcon#about to write, iclass 14, count 0 2006.257.02:05:01.42#ibcon#wrote, iclass 14, count 0 2006.257.02:05:01.42#ibcon#about to read 3, iclass 14, count 0 2006.257.02:05:01.45#ibcon#read 3, iclass 14, count 0 2006.257.02:05:01.45#ibcon#about to read 4, iclass 14, count 0 2006.257.02:05:01.45#ibcon#read 4, iclass 14, count 0 2006.257.02:05:01.45#ibcon#about to read 5, iclass 14, count 0 2006.257.02:05:01.45#ibcon#read 5, iclass 14, count 0 2006.257.02:05:01.45#ibcon#about to read 6, iclass 14, count 0 2006.257.02:05:01.45#ibcon#read 6, iclass 14, count 0 2006.257.02:05:01.45#ibcon#end of sib2, iclass 14, count 0 2006.257.02:05:01.45#ibcon#*after write, iclass 14, count 0 2006.257.02:05:01.45#ibcon#*before return 0, iclass 14, count 0 2006.257.02:05:01.45#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:05:01.45#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:05:01.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:05:01.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:05:01.45$vck44/vblo=6,719.99 2006.257.02:05:01.45#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.02:05:01.45#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.02:05:01.45#ibcon#ireg 17 cls_cnt 0 2006.257.02:05:01.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:05:01.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:05:01.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:05:01.45#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:05:01.45#ibcon#first serial, iclass 16, count 0 2006.257.02:05:01.45#ibcon#enter sib2, iclass 16, count 0 2006.257.02:05:01.45#ibcon#flushed, iclass 16, count 0 2006.257.02:05:01.45#ibcon#about to write, iclass 16, count 0 2006.257.02:05:01.45#ibcon#wrote, iclass 16, count 0 2006.257.02:05:01.45#ibcon#about to read 3, iclass 16, count 0 2006.257.02:05:01.48#ibcon#read 3, iclass 16, count 0 2006.257.02:05:01.48#ibcon#about to read 4, iclass 16, count 0 2006.257.02:05:01.48#ibcon#read 4, iclass 16, count 0 2006.257.02:05:01.48#ibcon#about to read 5, iclass 16, count 0 2006.257.02:05:01.48#ibcon#read 5, iclass 16, count 0 2006.257.02:05:01.48#ibcon#about to read 6, iclass 16, count 0 2006.257.02:05:01.48#ibcon#read 6, iclass 16, count 0 2006.257.02:05:01.48#ibcon#end of sib2, iclass 16, count 0 2006.257.02:05:01.48#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:05:01.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:05:01.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:05:01.48#ibcon#*before write, iclass 16, count 0 2006.257.02:05:01.48#ibcon#enter sib2, iclass 16, count 0 2006.257.02:05:01.48#ibcon#flushed, iclass 16, count 0 2006.257.02:05:01.48#ibcon#about to write, iclass 16, count 0 2006.257.02:05:01.48#ibcon#wrote, iclass 16, count 0 2006.257.02:05:01.48#ibcon#about to read 3, iclass 16, count 0 2006.257.02:05:01.52#ibcon#read 3, iclass 16, count 0 2006.257.02:05:01.52#ibcon#about to read 4, iclass 16, count 0 2006.257.02:05:01.52#ibcon#read 4, iclass 16, count 0 2006.257.02:05:01.52#ibcon#about to read 5, iclass 16, count 0 2006.257.02:05:01.52#ibcon#read 5, iclass 16, count 0 2006.257.02:05:01.52#ibcon#about to read 6, iclass 16, count 0 2006.257.02:05:01.52#ibcon#read 6, iclass 16, count 0 2006.257.02:05:01.52#ibcon#end of sib2, iclass 16, count 0 2006.257.02:05:01.52#ibcon#*after write, iclass 16, count 0 2006.257.02:05:01.52#ibcon#*before return 0, iclass 16, count 0 2006.257.02:05:01.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:05:01.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:05:01.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:05:01.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:05:01.52$vck44/vb=6,4 2006.257.02:05:01.52#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.02:05:01.52#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.02:05:01.52#ibcon#ireg 11 cls_cnt 2 2006.257.02:05:01.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:05:01.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:05:01.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:05:01.57#ibcon#enter wrdev, iclass 18, count 2 2006.257.02:05:01.57#ibcon#first serial, iclass 18, count 2 2006.257.02:05:01.57#ibcon#enter sib2, iclass 18, count 2 2006.257.02:05:01.57#ibcon#flushed, iclass 18, count 2 2006.257.02:05:01.57#ibcon#about to write, iclass 18, count 2 2006.257.02:05:01.57#ibcon#wrote, iclass 18, count 2 2006.257.02:05:01.57#ibcon#about to read 3, iclass 18, count 2 2006.257.02:05:01.59#ibcon#read 3, iclass 18, count 2 2006.257.02:05:01.59#ibcon#about to read 4, iclass 18, count 2 2006.257.02:05:01.59#ibcon#read 4, iclass 18, count 2 2006.257.02:05:01.59#ibcon#about to read 5, iclass 18, count 2 2006.257.02:05:01.59#ibcon#read 5, iclass 18, count 2 2006.257.02:05:01.59#ibcon#about to read 6, iclass 18, count 2 2006.257.02:05:01.59#ibcon#read 6, iclass 18, count 2 2006.257.02:05:01.59#ibcon#end of sib2, iclass 18, count 2 2006.257.02:05:01.59#ibcon#*mode == 0, iclass 18, count 2 2006.257.02:05:01.59#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.02:05:01.59#ibcon#[27=AT06-04\r\n] 2006.257.02:05:01.59#ibcon#*before write, iclass 18, count 2 2006.257.02:05:01.59#ibcon#enter sib2, iclass 18, count 2 2006.257.02:05:01.59#ibcon#flushed, iclass 18, count 2 2006.257.02:05:01.59#ibcon#about to write, iclass 18, count 2 2006.257.02:05:01.59#ibcon#wrote, iclass 18, count 2 2006.257.02:05:01.59#ibcon#about to read 3, iclass 18, count 2 2006.257.02:05:01.62#ibcon#read 3, iclass 18, count 2 2006.257.02:05:01.62#ibcon#about to read 4, iclass 18, count 2 2006.257.02:05:01.62#ibcon#read 4, iclass 18, count 2 2006.257.02:05:01.62#ibcon#about to read 5, iclass 18, count 2 2006.257.02:05:01.62#ibcon#read 5, iclass 18, count 2 2006.257.02:05:01.62#ibcon#about to read 6, iclass 18, count 2 2006.257.02:05:01.62#ibcon#read 6, iclass 18, count 2 2006.257.02:05:01.62#ibcon#end of sib2, iclass 18, count 2 2006.257.02:05:01.62#ibcon#*after write, iclass 18, count 2 2006.257.02:05:01.62#ibcon#*before return 0, iclass 18, count 2 2006.257.02:05:01.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:05:01.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:05:01.62#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.02:05:01.62#ibcon#ireg 7 cls_cnt 0 2006.257.02:05:01.62#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:05:01.74#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:05:01.74#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:05:01.74#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:05:01.74#ibcon#first serial, iclass 18, count 0 2006.257.02:05:01.74#ibcon#enter sib2, iclass 18, count 0 2006.257.02:05:01.74#ibcon#flushed, iclass 18, count 0 2006.257.02:05:01.74#ibcon#about to write, iclass 18, count 0 2006.257.02:05:01.74#ibcon#wrote, iclass 18, count 0 2006.257.02:05:01.74#ibcon#about to read 3, iclass 18, count 0 2006.257.02:05:01.76#ibcon#read 3, iclass 18, count 0 2006.257.02:05:01.76#ibcon#about to read 4, iclass 18, count 0 2006.257.02:05:01.76#ibcon#read 4, iclass 18, count 0 2006.257.02:05:01.76#ibcon#about to read 5, iclass 18, count 0 2006.257.02:05:01.76#ibcon#read 5, iclass 18, count 0 2006.257.02:05:01.76#ibcon#about to read 6, iclass 18, count 0 2006.257.02:05:01.76#ibcon#read 6, iclass 18, count 0 2006.257.02:05:01.76#ibcon#end of sib2, iclass 18, count 0 2006.257.02:05:01.76#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:05:01.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:05:01.76#ibcon#[27=USB\r\n] 2006.257.02:05:01.76#ibcon#*before write, iclass 18, count 0 2006.257.02:05:01.76#ibcon#enter sib2, iclass 18, count 0 2006.257.02:05:01.76#ibcon#flushed, iclass 18, count 0 2006.257.02:05:01.76#ibcon#about to write, iclass 18, count 0 2006.257.02:05:01.76#ibcon#wrote, iclass 18, count 0 2006.257.02:05:01.76#ibcon#about to read 3, iclass 18, count 0 2006.257.02:05:01.79#ibcon#read 3, iclass 18, count 0 2006.257.02:05:01.79#ibcon#about to read 4, iclass 18, count 0 2006.257.02:05:01.79#ibcon#read 4, iclass 18, count 0 2006.257.02:05:01.79#ibcon#about to read 5, iclass 18, count 0 2006.257.02:05:01.79#ibcon#read 5, iclass 18, count 0 2006.257.02:05:01.79#ibcon#about to read 6, iclass 18, count 0 2006.257.02:05:01.79#ibcon#read 6, iclass 18, count 0 2006.257.02:05:01.79#ibcon#end of sib2, iclass 18, count 0 2006.257.02:05:01.79#ibcon#*after write, iclass 18, count 0 2006.257.02:05:01.79#ibcon#*before return 0, iclass 18, count 0 2006.257.02:05:01.79#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:05:01.79#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:05:01.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:05:01.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:05:01.79$vck44/vblo=7,734.99 2006.257.02:05:01.79#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.02:05:01.79#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.02:05:01.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:05:01.79#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:05:01.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:05:01.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:05:01.79#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:05:01.79#ibcon#first serial, iclass 20, count 0 2006.257.02:05:01.79#ibcon#enter sib2, iclass 20, count 0 2006.257.02:05:01.79#ibcon#flushed, iclass 20, count 0 2006.257.02:05:01.79#ibcon#about to write, iclass 20, count 0 2006.257.02:05:01.79#ibcon#wrote, iclass 20, count 0 2006.257.02:05:01.79#ibcon#about to read 3, iclass 20, count 0 2006.257.02:05:01.81#ibcon#read 3, iclass 20, count 0 2006.257.02:05:01.81#ibcon#about to read 4, iclass 20, count 0 2006.257.02:05:01.81#ibcon#read 4, iclass 20, count 0 2006.257.02:05:01.81#ibcon#about to read 5, iclass 20, count 0 2006.257.02:05:01.81#ibcon#read 5, iclass 20, count 0 2006.257.02:05:01.81#ibcon#about to read 6, iclass 20, count 0 2006.257.02:05:01.81#ibcon#read 6, iclass 20, count 0 2006.257.02:05:01.81#ibcon#end of sib2, iclass 20, count 0 2006.257.02:05:01.81#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:05:01.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:05:01.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:05:01.81#ibcon#*before write, iclass 20, count 0 2006.257.02:05:01.81#ibcon#enter sib2, iclass 20, count 0 2006.257.02:05:01.81#ibcon#flushed, iclass 20, count 0 2006.257.02:05:01.81#ibcon#about to write, iclass 20, count 0 2006.257.02:05:01.81#ibcon#wrote, iclass 20, count 0 2006.257.02:05:01.81#ibcon#about to read 3, iclass 20, count 0 2006.257.02:05:01.85#ibcon#read 3, iclass 20, count 0 2006.257.02:05:01.85#ibcon#about to read 4, iclass 20, count 0 2006.257.02:05:01.85#ibcon#read 4, iclass 20, count 0 2006.257.02:05:01.85#ibcon#about to read 5, iclass 20, count 0 2006.257.02:05:01.85#ibcon#read 5, iclass 20, count 0 2006.257.02:05:01.85#ibcon#about to read 6, iclass 20, count 0 2006.257.02:05:01.85#ibcon#read 6, iclass 20, count 0 2006.257.02:05:01.85#ibcon#end of sib2, iclass 20, count 0 2006.257.02:05:01.85#ibcon#*after write, iclass 20, count 0 2006.257.02:05:01.85#ibcon#*before return 0, iclass 20, count 0 2006.257.02:05:01.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:05:01.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:05:01.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:05:01.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:05:01.85$vck44/vb=7,4 2006.257.02:05:01.85#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.02:05:01.85#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.02:05:01.85#ibcon#ireg 11 cls_cnt 2 2006.257.02:05:01.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:05:01.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:05:01.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:05:01.91#ibcon#enter wrdev, iclass 22, count 2 2006.257.02:05:01.91#ibcon#first serial, iclass 22, count 2 2006.257.02:05:01.91#ibcon#enter sib2, iclass 22, count 2 2006.257.02:05:01.91#ibcon#flushed, iclass 22, count 2 2006.257.02:05:01.91#ibcon#about to write, iclass 22, count 2 2006.257.02:05:01.91#ibcon#wrote, iclass 22, count 2 2006.257.02:05:01.91#ibcon#about to read 3, iclass 22, count 2 2006.257.02:05:01.93#ibcon#read 3, iclass 22, count 2 2006.257.02:05:01.93#ibcon#about to read 4, iclass 22, count 2 2006.257.02:05:01.93#ibcon#read 4, iclass 22, count 2 2006.257.02:05:01.93#ibcon#about to read 5, iclass 22, count 2 2006.257.02:05:01.93#ibcon#read 5, iclass 22, count 2 2006.257.02:05:01.93#ibcon#about to read 6, iclass 22, count 2 2006.257.02:05:01.93#ibcon#read 6, iclass 22, count 2 2006.257.02:05:01.93#ibcon#end of sib2, iclass 22, count 2 2006.257.02:05:01.93#ibcon#*mode == 0, iclass 22, count 2 2006.257.02:05:01.93#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.02:05:01.93#ibcon#[27=AT07-04\r\n] 2006.257.02:05:01.93#ibcon#*before write, iclass 22, count 2 2006.257.02:05:01.93#ibcon#enter sib2, iclass 22, count 2 2006.257.02:05:01.93#ibcon#flushed, iclass 22, count 2 2006.257.02:05:01.93#ibcon#about to write, iclass 22, count 2 2006.257.02:05:01.93#ibcon#wrote, iclass 22, count 2 2006.257.02:05:01.93#ibcon#about to read 3, iclass 22, count 2 2006.257.02:05:01.96#ibcon#read 3, iclass 22, count 2 2006.257.02:05:01.96#ibcon#about to read 4, iclass 22, count 2 2006.257.02:05:01.96#ibcon#read 4, iclass 22, count 2 2006.257.02:05:01.96#ibcon#about to read 5, iclass 22, count 2 2006.257.02:05:01.96#ibcon#read 5, iclass 22, count 2 2006.257.02:05:01.96#ibcon#about to read 6, iclass 22, count 2 2006.257.02:05:01.96#ibcon#read 6, iclass 22, count 2 2006.257.02:05:01.96#ibcon#end of sib2, iclass 22, count 2 2006.257.02:05:01.96#ibcon#*after write, iclass 22, count 2 2006.257.02:05:01.96#ibcon#*before return 0, iclass 22, count 2 2006.257.02:05:01.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:05:01.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:05:01.96#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.02:05:01.96#ibcon#ireg 7 cls_cnt 0 2006.257.02:05:01.96#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:05:02.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:05:02.08#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:05:02.08#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:05:02.08#ibcon#first serial, iclass 22, count 0 2006.257.02:05:02.08#ibcon#enter sib2, iclass 22, count 0 2006.257.02:05:02.08#ibcon#flushed, iclass 22, count 0 2006.257.02:05:02.08#ibcon#about to write, iclass 22, count 0 2006.257.02:05:02.08#ibcon#wrote, iclass 22, count 0 2006.257.02:05:02.08#ibcon#about to read 3, iclass 22, count 0 2006.257.02:05:02.10#ibcon#read 3, iclass 22, count 0 2006.257.02:05:02.10#ibcon#about to read 4, iclass 22, count 0 2006.257.02:05:02.10#ibcon#read 4, iclass 22, count 0 2006.257.02:05:02.10#ibcon#about to read 5, iclass 22, count 0 2006.257.02:05:02.10#ibcon#read 5, iclass 22, count 0 2006.257.02:05:02.10#ibcon#about to read 6, iclass 22, count 0 2006.257.02:05:02.10#ibcon#read 6, iclass 22, count 0 2006.257.02:05:02.10#ibcon#end of sib2, iclass 22, count 0 2006.257.02:05:02.10#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:05:02.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:05:02.10#ibcon#[27=USB\r\n] 2006.257.02:05:02.10#ibcon#*before write, iclass 22, count 0 2006.257.02:05:02.10#ibcon#enter sib2, iclass 22, count 0 2006.257.02:05:02.10#ibcon#flushed, iclass 22, count 0 2006.257.02:05:02.10#ibcon#about to write, iclass 22, count 0 2006.257.02:05:02.10#ibcon#wrote, iclass 22, count 0 2006.257.02:05:02.10#ibcon#about to read 3, iclass 22, count 0 2006.257.02:05:02.13#ibcon#read 3, iclass 22, count 0 2006.257.02:05:02.13#ibcon#about to read 4, iclass 22, count 0 2006.257.02:05:02.13#ibcon#read 4, iclass 22, count 0 2006.257.02:05:02.13#ibcon#about to read 5, iclass 22, count 0 2006.257.02:05:02.13#ibcon#read 5, iclass 22, count 0 2006.257.02:05:02.13#ibcon#about to read 6, iclass 22, count 0 2006.257.02:05:02.13#ibcon#read 6, iclass 22, count 0 2006.257.02:05:02.13#ibcon#end of sib2, iclass 22, count 0 2006.257.02:05:02.13#ibcon#*after write, iclass 22, count 0 2006.257.02:05:02.13#ibcon#*before return 0, iclass 22, count 0 2006.257.02:05:02.13#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:05:02.13#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:05:02.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:05:02.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:05:02.13$vck44/vblo=8,744.99 2006.257.02:05:02.13#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.02:05:02.13#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.02:05:02.13#ibcon#ireg 17 cls_cnt 0 2006.257.02:05:02.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:05:02.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:05:02.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:05:02.13#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:05:02.13#ibcon#first serial, iclass 24, count 0 2006.257.02:05:02.13#ibcon#enter sib2, iclass 24, count 0 2006.257.02:05:02.13#ibcon#flushed, iclass 24, count 0 2006.257.02:05:02.13#ibcon#about to write, iclass 24, count 0 2006.257.02:05:02.13#ibcon#wrote, iclass 24, count 0 2006.257.02:05:02.13#ibcon#about to read 3, iclass 24, count 0 2006.257.02:05:02.15#ibcon#read 3, iclass 24, count 0 2006.257.02:05:02.15#ibcon#about to read 4, iclass 24, count 0 2006.257.02:05:02.15#ibcon#read 4, iclass 24, count 0 2006.257.02:05:02.15#ibcon#about to read 5, iclass 24, count 0 2006.257.02:05:02.15#ibcon#read 5, iclass 24, count 0 2006.257.02:05:02.15#ibcon#about to read 6, iclass 24, count 0 2006.257.02:05:02.15#ibcon#read 6, iclass 24, count 0 2006.257.02:05:02.15#ibcon#end of sib2, iclass 24, count 0 2006.257.02:05:02.15#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:05:02.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:05:02.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:05:02.15#ibcon#*before write, iclass 24, count 0 2006.257.02:05:02.15#ibcon#enter sib2, iclass 24, count 0 2006.257.02:05:02.15#ibcon#flushed, iclass 24, count 0 2006.257.02:05:02.15#ibcon#about to write, iclass 24, count 0 2006.257.02:05:02.15#ibcon#wrote, iclass 24, count 0 2006.257.02:05:02.15#ibcon#about to read 3, iclass 24, count 0 2006.257.02:05:02.19#ibcon#read 3, iclass 24, count 0 2006.257.02:05:02.19#ibcon#about to read 4, iclass 24, count 0 2006.257.02:05:02.19#ibcon#read 4, iclass 24, count 0 2006.257.02:05:02.19#ibcon#about to read 5, iclass 24, count 0 2006.257.02:05:02.19#ibcon#read 5, iclass 24, count 0 2006.257.02:05:02.19#ibcon#about to read 6, iclass 24, count 0 2006.257.02:05:02.19#ibcon#read 6, iclass 24, count 0 2006.257.02:05:02.19#ibcon#end of sib2, iclass 24, count 0 2006.257.02:05:02.19#ibcon#*after write, iclass 24, count 0 2006.257.02:05:02.19#ibcon#*before return 0, iclass 24, count 0 2006.257.02:05:02.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:05:02.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:05:02.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:05:02.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:05:02.19$vck44/vb=8,4 2006.257.02:05:02.19#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.02:05:02.19#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.02:05:02.19#ibcon#ireg 11 cls_cnt 2 2006.257.02:05:02.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:05:02.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:05:02.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:05:02.25#ibcon#enter wrdev, iclass 26, count 2 2006.257.02:05:02.25#ibcon#first serial, iclass 26, count 2 2006.257.02:05:02.25#ibcon#enter sib2, iclass 26, count 2 2006.257.02:05:02.25#ibcon#flushed, iclass 26, count 2 2006.257.02:05:02.25#ibcon#about to write, iclass 26, count 2 2006.257.02:05:02.25#ibcon#wrote, iclass 26, count 2 2006.257.02:05:02.25#ibcon#about to read 3, iclass 26, count 2 2006.257.02:05:02.27#ibcon#read 3, iclass 26, count 2 2006.257.02:05:02.27#ibcon#about to read 4, iclass 26, count 2 2006.257.02:05:02.27#ibcon#read 4, iclass 26, count 2 2006.257.02:05:02.27#ibcon#about to read 5, iclass 26, count 2 2006.257.02:05:02.27#ibcon#read 5, iclass 26, count 2 2006.257.02:05:02.27#ibcon#about to read 6, iclass 26, count 2 2006.257.02:05:02.27#ibcon#read 6, iclass 26, count 2 2006.257.02:05:02.27#ibcon#end of sib2, iclass 26, count 2 2006.257.02:05:02.27#ibcon#*mode == 0, iclass 26, count 2 2006.257.02:05:02.27#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.02:05:02.27#ibcon#[27=AT08-04\r\n] 2006.257.02:05:02.27#ibcon#*before write, iclass 26, count 2 2006.257.02:05:02.27#ibcon#enter sib2, iclass 26, count 2 2006.257.02:05:02.27#ibcon#flushed, iclass 26, count 2 2006.257.02:05:02.27#ibcon#about to write, iclass 26, count 2 2006.257.02:05:02.27#ibcon#wrote, iclass 26, count 2 2006.257.02:05:02.27#ibcon#about to read 3, iclass 26, count 2 2006.257.02:05:02.30#ibcon#read 3, iclass 26, count 2 2006.257.02:05:02.30#ibcon#about to read 4, iclass 26, count 2 2006.257.02:05:02.30#ibcon#read 4, iclass 26, count 2 2006.257.02:05:02.30#ibcon#about to read 5, iclass 26, count 2 2006.257.02:05:02.30#ibcon#read 5, iclass 26, count 2 2006.257.02:05:02.30#ibcon#about to read 6, iclass 26, count 2 2006.257.02:05:02.30#ibcon#read 6, iclass 26, count 2 2006.257.02:05:02.30#ibcon#end of sib2, iclass 26, count 2 2006.257.02:05:02.30#ibcon#*after write, iclass 26, count 2 2006.257.02:05:02.30#ibcon#*before return 0, iclass 26, count 2 2006.257.02:05:02.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:05:02.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:05:02.30#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.02:05:02.30#ibcon#ireg 7 cls_cnt 0 2006.257.02:05:02.30#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:05:02.42#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:05:02.42#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:05:02.42#ibcon#enter wrdev, iclass 26, count 0 2006.257.02:05:02.42#ibcon#first serial, iclass 26, count 0 2006.257.02:05:02.42#ibcon#enter sib2, iclass 26, count 0 2006.257.02:05:02.42#ibcon#flushed, iclass 26, count 0 2006.257.02:05:02.42#ibcon#about to write, iclass 26, count 0 2006.257.02:05:02.42#ibcon#wrote, iclass 26, count 0 2006.257.02:05:02.42#ibcon#about to read 3, iclass 26, count 0 2006.257.02:05:02.44#ibcon#read 3, iclass 26, count 0 2006.257.02:05:02.44#ibcon#about to read 4, iclass 26, count 0 2006.257.02:05:02.44#ibcon#read 4, iclass 26, count 0 2006.257.02:05:02.44#ibcon#about to read 5, iclass 26, count 0 2006.257.02:05:02.44#ibcon#read 5, iclass 26, count 0 2006.257.02:05:02.44#ibcon#about to read 6, iclass 26, count 0 2006.257.02:05:02.44#ibcon#read 6, iclass 26, count 0 2006.257.02:05:02.44#ibcon#end of sib2, iclass 26, count 0 2006.257.02:05:02.44#ibcon#*mode == 0, iclass 26, count 0 2006.257.02:05:02.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.02:05:02.44#ibcon#[27=USB\r\n] 2006.257.02:05:02.44#ibcon#*before write, iclass 26, count 0 2006.257.02:05:02.44#ibcon#enter sib2, iclass 26, count 0 2006.257.02:05:02.44#ibcon#flushed, iclass 26, count 0 2006.257.02:05:02.44#ibcon#about to write, iclass 26, count 0 2006.257.02:05:02.44#ibcon#wrote, iclass 26, count 0 2006.257.02:05:02.44#ibcon#about to read 3, iclass 26, count 0 2006.257.02:05:02.47#ibcon#read 3, iclass 26, count 0 2006.257.02:05:02.47#ibcon#about to read 4, iclass 26, count 0 2006.257.02:05:02.47#ibcon#read 4, iclass 26, count 0 2006.257.02:05:02.47#ibcon#about to read 5, iclass 26, count 0 2006.257.02:05:02.47#ibcon#read 5, iclass 26, count 0 2006.257.02:05:02.47#ibcon#about to read 6, iclass 26, count 0 2006.257.02:05:02.47#ibcon#read 6, iclass 26, count 0 2006.257.02:05:02.47#ibcon#end of sib2, iclass 26, count 0 2006.257.02:05:02.47#ibcon#*after write, iclass 26, count 0 2006.257.02:05:02.47#ibcon#*before return 0, iclass 26, count 0 2006.257.02:05:02.47#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:05:02.47#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:05:02.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.02:05:02.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.02:05:02.47$vck44/vabw=wide 2006.257.02:05:02.47#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.02:05:02.47#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.02:05:02.47#ibcon#ireg 8 cls_cnt 0 2006.257.02:05:02.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:05:02.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:05:02.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:05:02.47#ibcon#enter wrdev, iclass 28, count 0 2006.257.02:05:02.47#ibcon#first serial, iclass 28, count 0 2006.257.02:05:02.47#ibcon#enter sib2, iclass 28, count 0 2006.257.02:05:02.47#ibcon#flushed, iclass 28, count 0 2006.257.02:05:02.47#ibcon#about to write, iclass 28, count 0 2006.257.02:05:02.47#ibcon#wrote, iclass 28, count 0 2006.257.02:05:02.47#ibcon#about to read 3, iclass 28, count 0 2006.257.02:05:02.49#ibcon#read 3, iclass 28, count 0 2006.257.02:05:02.49#ibcon#about to read 4, iclass 28, count 0 2006.257.02:05:02.49#ibcon#read 4, iclass 28, count 0 2006.257.02:05:02.49#ibcon#about to read 5, iclass 28, count 0 2006.257.02:05:02.49#ibcon#read 5, iclass 28, count 0 2006.257.02:05:02.49#ibcon#about to read 6, iclass 28, count 0 2006.257.02:05:02.49#ibcon#read 6, iclass 28, count 0 2006.257.02:05:02.49#ibcon#end of sib2, iclass 28, count 0 2006.257.02:05:02.49#ibcon#*mode == 0, iclass 28, count 0 2006.257.02:05:02.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.02:05:02.49#ibcon#[25=BW32\r\n] 2006.257.02:05:02.49#ibcon#*before write, iclass 28, count 0 2006.257.02:05:02.49#ibcon#enter sib2, iclass 28, count 0 2006.257.02:05:02.49#ibcon#flushed, iclass 28, count 0 2006.257.02:05:02.49#ibcon#about to write, iclass 28, count 0 2006.257.02:05:02.49#ibcon#wrote, iclass 28, count 0 2006.257.02:05:02.49#ibcon#about to read 3, iclass 28, count 0 2006.257.02:05:02.52#ibcon#read 3, iclass 28, count 0 2006.257.02:05:02.52#ibcon#about to read 4, iclass 28, count 0 2006.257.02:05:02.52#ibcon#read 4, iclass 28, count 0 2006.257.02:05:02.52#ibcon#about to read 5, iclass 28, count 0 2006.257.02:05:02.52#ibcon#read 5, iclass 28, count 0 2006.257.02:05:02.52#ibcon#about to read 6, iclass 28, count 0 2006.257.02:05:02.52#ibcon#read 6, iclass 28, count 0 2006.257.02:05:02.52#ibcon#end of sib2, iclass 28, count 0 2006.257.02:05:02.52#ibcon#*after write, iclass 28, count 0 2006.257.02:05:02.52#ibcon#*before return 0, iclass 28, count 0 2006.257.02:05:02.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:05:02.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:05:02.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.02:05:02.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.02:05:02.52$vck44/vbbw=wide 2006.257.02:05:02.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.02:05:02.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.02:05:02.52#ibcon#ireg 8 cls_cnt 0 2006.257.02:05:02.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:05:02.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:05:02.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:05:02.59#ibcon#enter wrdev, iclass 30, count 0 2006.257.02:05:02.59#ibcon#first serial, iclass 30, count 0 2006.257.02:05:02.59#ibcon#enter sib2, iclass 30, count 0 2006.257.02:05:02.59#ibcon#flushed, iclass 30, count 0 2006.257.02:05:02.59#ibcon#about to write, iclass 30, count 0 2006.257.02:05:02.59#ibcon#wrote, iclass 30, count 0 2006.257.02:05:02.59#ibcon#about to read 3, iclass 30, count 0 2006.257.02:05:02.61#ibcon#read 3, iclass 30, count 0 2006.257.02:05:02.61#ibcon#about to read 4, iclass 30, count 0 2006.257.02:05:02.61#ibcon#read 4, iclass 30, count 0 2006.257.02:05:02.61#ibcon#about to read 5, iclass 30, count 0 2006.257.02:05:02.61#ibcon#read 5, iclass 30, count 0 2006.257.02:05:02.61#ibcon#about to read 6, iclass 30, count 0 2006.257.02:05:02.61#ibcon#read 6, iclass 30, count 0 2006.257.02:05:02.61#ibcon#end of sib2, iclass 30, count 0 2006.257.02:05:02.61#ibcon#*mode == 0, iclass 30, count 0 2006.257.02:05:02.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.02:05:02.61#ibcon#[27=BW32\r\n] 2006.257.02:05:02.61#ibcon#*before write, iclass 30, count 0 2006.257.02:05:02.61#ibcon#enter sib2, iclass 30, count 0 2006.257.02:05:02.61#ibcon#flushed, iclass 30, count 0 2006.257.02:05:02.61#ibcon#about to write, iclass 30, count 0 2006.257.02:05:02.61#ibcon#wrote, iclass 30, count 0 2006.257.02:05:02.61#ibcon#about to read 3, iclass 30, count 0 2006.257.02:05:02.64#ibcon#read 3, iclass 30, count 0 2006.257.02:05:02.64#ibcon#about to read 4, iclass 30, count 0 2006.257.02:05:02.64#ibcon#read 4, iclass 30, count 0 2006.257.02:05:02.64#ibcon#about to read 5, iclass 30, count 0 2006.257.02:05:02.64#ibcon#read 5, iclass 30, count 0 2006.257.02:05:02.64#ibcon#about to read 6, iclass 30, count 0 2006.257.02:05:02.64#ibcon#read 6, iclass 30, count 0 2006.257.02:05:02.64#ibcon#end of sib2, iclass 30, count 0 2006.257.02:05:02.64#ibcon#*after write, iclass 30, count 0 2006.257.02:05:02.64#ibcon#*before return 0, iclass 30, count 0 2006.257.02:05:02.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:05:02.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:05:02.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.02:05:02.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.02:05:02.64$setupk4/ifdk4 2006.257.02:05:02.64$ifdk4/lo= 2006.257.02:05:02.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:05:02.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:05:02.64$ifdk4/patch= 2006.257.02:05:02.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:05:02.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:05:02.64$setupk4/!*+20s 2006.257.02:05:08.21#abcon#<5=/03 3.9 9.2 17.80 991011.8\r\n> 2006.257.02:05:08.23#abcon#{5=INTERFACE CLEAR} 2006.257.02:05:08.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:05:17.12$setupk4/"tpicd 2006.257.02:05:17.12$setupk4/echo=off 2006.257.02:05:17.12$setupk4/xlog=off 2006.257.02:05:17.12:!2006.257.02:06:24 2006.257.02:05:23.14#trakl#Source acquired 2006.257.02:05:24.14#flagr#flagr/antenna,acquired 2006.257.02:06:24.00:preob 2006.257.02:06:25.14/onsource/TRACKING 2006.257.02:06:25.14:!2006.257.02:06:34 2006.257.02:06:34.00:"tape 2006.257.02:06:34.00:"st=record 2006.257.02:06:34.00:data_valid=on 2006.257.02:06:34.00:midob 2006.257.02:06:34.14/onsource/TRACKING 2006.257.02:06:34.14/wx/17.82,1011.8,98 2006.257.02:06:34.20/cable/+6.4876E-03 2006.257.02:06:35.29/va/01,08,usb,yes,34,36 2006.257.02:06:35.29/va/02,07,usb,yes,36,37 2006.257.02:06:35.29/va/03,08,usb,yes,33,35 2006.257.02:06:35.29/va/04,07,usb,yes,37,39 2006.257.02:06:35.29/va/05,04,usb,yes,33,34 2006.257.02:06:35.29/va/06,04,usb,yes,37,37 2006.257.02:06:35.29/va/07,04,usb,yes,38,38 2006.257.02:06:35.29/va/08,04,usb,yes,32,39 2006.257.02:06:35.52/valo/01,524.99,yes,locked 2006.257.02:06:35.52/valo/02,534.99,yes,locked 2006.257.02:06:35.52/valo/03,564.99,yes,locked 2006.257.02:06:35.52/valo/04,624.99,yes,locked 2006.257.02:06:35.52/valo/05,734.99,yes,locked 2006.257.02:06:35.52/valo/06,814.99,yes,locked 2006.257.02:06:35.52/valo/07,864.99,yes,locked 2006.257.02:06:35.52/valo/08,884.99,yes,locked 2006.257.02:06:36.61/vb/01,04,usb,yes,38,35 2006.257.02:06:36.61/vb/02,05,usb,yes,36,36 2006.257.02:06:36.61/vb/03,04,usb,yes,37,41 2006.257.02:06:36.61/vb/04,05,usb,yes,37,36 2006.257.02:06:36.61/vb/05,04,usb,yes,33,36 2006.257.02:06:36.61/vb/06,04,usb,yes,38,34 2006.257.02:06:36.61/vb/07,04,usb,yes,38,38 2006.257.02:06:36.61/vb/08,04,usb,yes,35,39 2006.257.02:06:36.85/vblo/01,629.99,yes,locked 2006.257.02:06:36.85/vblo/02,634.99,yes,locked 2006.257.02:06:36.85/vblo/03,649.99,yes,locked 2006.257.02:06:36.85/vblo/04,679.99,yes,locked 2006.257.02:06:36.85/vblo/05,709.99,yes,locked 2006.257.02:06:36.85/vblo/06,719.99,yes,locked 2006.257.02:06:36.85/vblo/07,734.99,yes,locked 2006.257.02:06:36.85/vblo/08,744.99,yes,locked 2006.257.02:06:37.00/vabw/8 2006.257.02:06:37.15/vbbw/8 2006.257.02:06:37.25/xfe/off,on,15.0 2006.257.02:06:37.62/ifatt/23,28,28,28 2006.257.02:06:38.08/fmout-gps/S +4.52E-07 2006.257.02:06:38.12:!2006.257.02:07:54 2006.257.02:07:54.00:data_valid=off 2006.257.02:07:54.00:"et 2006.257.02:07:54.01:!+3s 2006.257.02:07:57.02:"tape 2006.257.02:07:57.02:postob 2006.257.02:07:57.15/cable/+6.4885E-03 2006.257.02:07:57.15/wx/17.81,1011.9,99 2006.257.02:07:58.08/fmout-gps/S +4.52E-07 2006.257.02:07:58.08:scan_name=257-0211,jd0609,70 2006.257.02:07:58.09:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.257.02:07:59.14#flagr#flagr/antenna,new-source 2006.257.02:07:59.15:checkk5 2006.257.02:07:59.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:07:59.98/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:08:00.42/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:08:00.88/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:08:01.30/chk_obsdata//k5ts1/T2570206??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.02:08:01.69/chk_obsdata//k5ts2/T2570206??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.02:08:02.12/chk_obsdata//k5ts3/T2570206??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.02:08:02.52/chk_obsdata//k5ts4/T2570206??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.02:08:03.25/k5log//k5ts1_log_newline 2006.257.02:08:04.24/k5log//k5ts2_log_newline 2006.257.02:08:04.97/k5log//k5ts3_log_newline 2006.257.02:08:05.77/k5log//k5ts4_log_newline 2006.257.02:08:05.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:08:05.79:setupk4=1 2006.257.02:08:05.79$setupk4/echo=on 2006.257.02:08:05.79$setupk4/pcalon 2006.257.02:08:05.79$pcalon/"no phase cal control is implemented here 2006.257.02:08:05.79$setupk4/"tpicd=stop 2006.257.02:08:05.79$setupk4/"rec=synch_on 2006.257.02:08:05.79$setupk4/"rec_mode=128 2006.257.02:08:05.79$setupk4/!* 2006.257.02:08:05.79$setupk4/recpk4 2006.257.02:08:05.79$recpk4/recpatch= 2006.257.02:08:05.80$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:08:05.80$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:08:05.80$setupk4/vck44 2006.257.02:08:05.80$vck44/valo=1,524.99 2006.257.02:08:05.80#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.02:08:05.80#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.02:08:05.80#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:05.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:05.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:05.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:05.80#ibcon#enter wrdev, iclass 30, count 0 2006.257.02:08:05.80#ibcon#first serial, iclass 30, count 0 2006.257.02:08:05.80#ibcon#enter sib2, iclass 30, count 0 2006.257.02:08:05.80#ibcon#flushed, iclass 30, count 0 2006.257.02:08:05.80#ibcon#about to write, iclass 30, count 0 2006.257.02:08:05.80#ibcon#wrote, iclass 30, count 0 2006.257.02:08:05.80#ibcon#about to read 3, iclass 30, count 0 2006.257.02:08:05.84#ibcon#read 3, iclass 30, count 0 2006.257.02:08:05.84#ibcon#about to read 4, iclass 30, count 0 2006.257.02:08:05.84#ibcon#read 4, iclass 30, count 0 2006.257.02:08:05.84#ibcon#about to read 5, iclass 30, count 0 2006.257.02:08:05.84#ibcon#read 5, iclass 30, count 0 2006.257.02:08:05.84#ibcon#about to read 6, iclass 30, count 0 2006.257.02:08:05.84#ibcon#read 6, iclass 30, count 0 2006.257.02:08:05.84#ibcon#end of sib2, iclass 30, count 0 2006.257.02:08:05.84#ibcon#*mode == 0, iclass 30, count 0 2006.257.02:08:05.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.02:08:05.84#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:08:05.84#ibcon#*before write, iclass 30, count 0 2006.257.02:08:05.84#ibcon#enter sib2, iclass 30, count 0 2006.257.02:08:05.84#ibcon#flushed, iclass 30, count 0 2006.257.02:08:05.84#ibcon#about to write, iclass 30, count 0 2006.257.02:08:05.84#ibcon#wrote, iclass 30, count 0 2006.257.02:08:05.84#ibcon#about to read 3, iclass 30, count 0 2006.257.02:08:05.88#ibcon#read 3, iclass 30, count 0 2006.257.02:08:05.88#ibcon#about to read 4, iclass 30, count 0 2006.257.02:08:05.88#ibcon#read 4, iclass 30, count 0 2006.257.02:08:05.88#ibcon#about to read 5, iclass 30, count 0 2006.257.02:08:05.88#ibcon#read 5, iclass 30, count 0 2006.257.02:08:05.88#ibcon#about to read 6, iclass 30, count 0 2006.257.02:08:05.88#ibcon#read 6, iclass 30, count 0 2006.257.02:08:05.88#ibcon#end of sib2, iclass 30, count 0 2006.257.02:08:05.88#ibcon#*after write, iclass 30, count 0 2006.257.02:08:05.88#ibcon#*before return 0, iclass 30, count 0 2006.257.02:08:05.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:05.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:05.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.02:08:05.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.02:08:05.88$vck44/va=1,8 2006.257.02:08:05.88#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.02:08:05.88#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.02:08:05.88#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:05.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:05.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:05.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:05.88#ibcon#enter wrdev, iclass 32, count 2 2006.257.02:08:05.88#ibcon#first serial, iclass 32, count 2 2006.257.02:08:05.88#ibcon#enter sib2, iclass 32, count 2 2006.257.02:08:05.88#ibcon#flushed, iclass 32, count 2 2006.257.02:08:05.88#ibcon#about to write, iclass 32, count 2 2006.257.02:08:05.88#ibcon#wrote, iclass 32, count 2 2006.257.02:08:05.88#ibcon#about to read 3, iclass 32, count 2 2006.257.02:08:05.90#ibcon#read 3, iclass 32, count 2 2006.257.02:08:05.90#ibcon#about to read 4, iclass 32, count 2 2006.257.02:08:05.90#ibcon#read 4, iclass 32, count 2 2006.257.02:08:05.90#ibcon#about to read 5, iclass 32, count 2 2006.257.02:08:05.90#ibcon#read 5, iclass 32, count 2 2006.257.02:08:05.90#ibcon#about to read 6, iclass 32, count 2 2006.257.02:08:05.90#ibcon#read 6, iclass 32, count 2 2006.257.02:08:05.90#ibcon#end of sib2, iclass 32, count 2 2006.257.02:08:05.90#ibcon#*mode == 0, iclass 32, count 2 2006.257.02:08:05.90#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.02:08:05.90#ibcon#[25=AT01-08\r\n] 2006.257.02:08:05.90#ibcon#*before write, iclass 32, count 2 2006.257.02:08:05.90#ibcon#enter sib2, iclass 32, count 2 2006.257.02:08:05.90#ibcon#flushed, iclass 32, count 2 2006.257.02:08:05.90#ibcon#about to write, iclass 32, count 2 2006.257.02:08:05.90#ibcon#wrote, iclass 32, count 2 2006.257.02:08:05.90#ibcon#about to read 3, iclass 32, count 2 2006.257.02:08:05.93#ibcon#read 3, iclass 32, count 2 2006.257.02:08:05.93#ibcon#about to read 4, iclass 32, count 2 2006.257.02:08:05.93#ibcon#read 4, iclass 32, count 2 2006.257.02:08:05.93#ibcon#about to read 5, iclass 32, count 2 2006.257.02:08:05.93#ibcon#read 5, iclass 32, count 2 2006.257.02:08:05.93#ibcon#about to read 6, iclass 32, count 2 2006.257.02:08:05.93#ibcon#read 6, iclass 32, count 2 2006.257.02:08:05.93#ibcon#end of sib2, iclass 32, count 2 2006.257.02:08:05.93#ibcon#*after write, iclass 32, count 2 2006.257.02:08:05.93#ibcon#*before return 0, iclass 32, count 2 2006.257.02:08:05.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:05.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:05.93#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.02:08:05.93#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:05.93#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:06.05#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:06.05#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:06.05#ibcon#enter wrdev, iclass 32, count 0 2006.257.02:08:06.05#ibcon#first serial, iclass 32, count 0 2006.257.02:08:06.05#ibcon#enter sib2, iclass 32, count 0 2006.257.02:08:06.05#ibcon#flushed, iclass 32, count 0 2006.257.02:08:06.05#ibcon#about to write, iclass 32, count 0 2006.257.02:08:06.05#ibcon#wrote, iclass 32, count 0 2006.257.02:08:06.05#ibcon#about to read 3, iclass 32, count 0 2006.257.02:08:06.07#ibcon#read 3, iclass 32, count 0 2006.257.02:08:06.07#ibcon#about to read 4, iclass 32, count 0 2006.257.02:08:06.07#ibcon#read 4, iclass 32, count 0 2006.257.02:08:06.07#ibcon#about to read 5, iclass 32, count 0 2006.257.02:08:06.07#ibcon#read 5, iclass 32, count 0 2006.257.02:08:06.07#ibcon#about to read 6, iclass 32, count 0 2006.257.02:08:06.07#ibcon#read 6, iclass 32, count 0 2006.257.02:08:06.07#ibcon#end of sib2, iclass 32, count 0 2006.257.02:08:06.07#ibcon#*mode == 0, iclass 32, count 0 2006.257.02:08:06.07#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.02:08:06.07#ibcon#[25=USB\r\n] 2006.257.02:08:06.07#ibcon#*before write, iclass 32, count 0 2006.257.02:08:06.07#ibcon#enter sib2, iclass 32, count 0 2006.257.02:08:06.07#ibcon#flushed, iclass 32, count 0 2006.257.02:08:06.07#ibcon#about to write, iclass 32, count 0 2006.257.02:08:06.07#ibcon#wrote, iclass 32, count 0 2006.257.02:08:06.07#ibcon#about to read 3, iclass 32, count 0 2006.257.02:08:06.10#ibcon#read 3, iclass 32, count 0 2006.257.02:08:06.10#ibcon#about to read 4, iclass 32, count 0 2006.257.02:08:06.10#ibcon#read 4, iclass 32, count 0 2006.257.02:08:06.10#ibcon#about to read 5, iclass 32, count 0 2006.257.02:08:06.10#ibcon#read 5, iclass 32, count 0 2006.257.02:08:06.10#ibcon#about to read 6, iclass 32, count 0 2006.257.02:08:06.10#ibcon#read 6, iclass 32, count 0 2006.257.02:08:06.10#ibcon#end of sib2, iclass 32, count 0 2006.257.02:08:06.10#ibcon#*after write, iclass 32, count 0 2006.257.02:08:06.10#ibcon#*before return 0, iclass 32, count 0 2006.257.02:08:06.10#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:06.10#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:06.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.02:08:06.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.02:08:06.10$vck44/valo=2,534.99 2006.257.02:08:06.10#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.02:08:06.10#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.02:08:06.10#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:06.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:06.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:06.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:06.10#ibcon#enter wrdev, iclass 34, count 0 2006.257.02:08:06.10#ibcon#first serial, iclass 34, count 0 2006.257.02:08:06.10#ibcon#enter sib2, iclass 34, count 0 2006.257.02:08:06.10#ibcon#flushed, iclass 34, count 0 2006.257.02:08:06.10#ibcon#about to write, iclass 34, count 0 2006.257.02:08:06.10#ibcon#wrote, iclass 34, count 0 2006.257.02:08:06.10#ibcon#about to read 3, iclass 34, count 0 2006.257.02:08:06.12#ibcon#read 3, iclass 34, count 0 2006.257.02:08:06.12#ibcon#about to read 4, iclass 34, count 0 2006.257.02:08:06.12#ibcon#read 4, iclass 34, count 0 2006.257.02:08:06.12#ibcon#about to read 5, iclass 34, count 0 2006.257.02:08:06.12#ibcon#read 5, iclass 34, count 0 2006.257.02:08:06.12#ibcon#about to read 6, iclass 34, count 0 2006.257.02:08:06.12#ibcon#read 6, iclass 34, count 0 2006.257.02:08:06.12#ibcon#end of sib2, iclass 34, count 0 2006.257.02:08:06.12#ibcon#*mode == 0, iclass 34, count 0 2006.257.02:08:06.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.02:08:06.12#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:08:06.12#ibcon#*before write, iclass 34, count 0 2006.257.02:08:06.12#ibcon#enter sib2, iclass 34, count 0 2006.257.02:08:06.12#ibcon#flushed, iclass 34, count 0 2006.257.02:08:06.12#ibcon#about to write, iclass 34, count 0 2006.257.02:08:06.12#ibcon#wrote, iclass 34, count 0 2006.257.02:08:06.12#ibcon#about to read 3, iclass 34, count 0 2006.257.02:08:06.16#ibcon#read 3, iclass 34, count 0 2006.257.02:08:06.16#ibcon#about to read 4, iclass 34, count 0 2006.257.02:08:06.16#ibcon#read 4, iclass 34, count 0 2006.257.02:08:06.16#ibcon#about to read 5, iclass 34, count 0 2006.257.02:08:06.16#ibcon#read 5, iclass 34, count 0 2006.257.02:08:06.16#ibcon#about to read 6, iclass 34, count 0 2006.257.02:08:06.16#ibcon#read 6, iclass 34, count 0 2006.257.02:08:06.16#ibcon#end of sib2, iclass 34, count 0 2006.257.02:08:06.16#ibcon#*after write, iclass 34, count 0 2006.257.02:08:06.16#ibcon#*before return 0, iclass 34, count 0 2006.257.02:08:06.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:06.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:06.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.02:08:06.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.02:08:06.16$vck44/va=2,7 2006.257.02:08:06.16#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.02:08:06.16#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.02:08:06.16#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:06.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:06.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:06.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:06.22#ibcon#enter wrdev, iclass 36, count 2 2006.257.02:08:06.22#ibcon#first serial, iclass 36, count 2 2006.257.02:08:06.22#ibcon#enter sib2, iclass 36, count 2 2006.257.02:08:06.22#ibcon#flushed, iclass 36, count 2 2006.257.02:08:06.22#ibcon#about to write, iclass 36, count 2 2006.257.02:08:06.22#ibcon#wrote, iclass 36, count 2 2006.257.02:08:06.22#ibcon#about to read 3, iclass 36, count 2 2006.257.02:08:06.25#ibcon#read 3, iclass 36, count 2 2006.257.02:08:06.25#ibcon#about to read 4, iclass 36, count 2 2006.257.02:08:06.25#ibcon#read 4, iclass 36, count 2 2006.257.02:08:06.25#ibcon#about to read 5, iclass 36, count 2 2006.257.02:08:06.25#ibcon#read 5, iclass 36, count 2 2006.257.02:08:06.25#ibcon#about to read 6, iclass 36, count 2 2006.257.02:08:06.25#ibcon#read 6, iclass 36, count 2 2006.257.02:08:06.25#ibcon#end of sib2, iclass 36, count 2 2006.257.02:08:06.25#ibcon#*mode == 0, iclass 36, count 2 2006.257.02:08:06.25#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.02:08:06.25#ibcon#[25=AT02-07\r\n] 2006.257.02:08:06.25#ibcon#*before write, iclass 36, count 2 2006.257.02:08:06.25#ibcon#enter sib2, iclass 36, count 2 2006.257.02:08:06.25#ibcon#flushed, iclass 36, count 2 2006.257.02:08:06.25#ibcon#about to write, iclass 36, count 2 2006.257.02:08:06.25#ibcon#wrote, iclass 36, count 2 2006.257.02:08:06.25#ibcon#about to read 3, iclass 36, count 2 2006.257.02:08:06.28#ibcon#read 3, iclass 36, count 2 2006.257.02:08:06.28#ibcon#about to read 4, iclass 36, count 2 2006.257.02:08:06.28#ibcon#read 4, iclass 36, count 2 2006.257.02:08:06.28#ibcon#about to read 5, iclass 36, count 2 2006.257.02:08:06.28#ibcon#read 5, iclass 36, count 2 2006.257.02:08:06.28#ibcon#about to read 6, iclass 36, count 2 2006.257.02:08:06.28#ibcon#read 6, iclass 36, count 2 2006.257.02:08:06.28#ibcon#end of sib2, iclass 36, count 2 2006.257.02:08:06.28#ibcon#*after write, iclass 36, count 2 2006.257.02:08:06.28#ibcon#*before return 0, iclass 36, count 2 2006.257.02:08:06.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:06.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:06.28#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.02:08:06.28#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:06.28#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:06.40#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:06.40#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:06.40#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:08:06.40#ibcon#first serial, iclass 36, count 0 2006.257.02:08:06.40#ibcon#enter sib2, iclass 36, count 0 2006.257.02:08:06.40#ibcon#flushed, iclass 36, count 0 2006.257.02:08:06.40#ibcon#about to write, iclass 36, count 0 2006.257.02:08:06.40#ibcon#wrote, iclass 36, count 0 2006.257.02:08:06.40#ibcon#about to read 3, iclass 36, count 0 2006.257.02:08:06.42#ibcon#read 3, iclass 36, count 0 2006.257.02:08:06.42#ibcon#about to read 4, iclass 36, count 0 2006.257.02:08:06.42#ibcon#read 4, iclass 36, count 0 2006.257.02:08:06.42#ibcon#about to read 5, iclass 36, count 0 2006.257.02:08:06.42#ibcon#read 5, iclass 36, count 0 2006.257.02:08:06.42#ibcon#about to read 6, iclass 36, count 0 2006.257.02:08:06.42#ibcon#read 6, iclass 36, count 0 2006.257.02:08:06.42#ibcon#end of sib2, iclass 36, count 0 2006.257.02:08:06.42#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:08:06.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:08:06.42#ibcon#[25=USB\r\n] 2006.257.02:08:06.42#ibcon#*before write, iclass 36, count 0 2006.257.02:08:06.42#ibcon#enter sib2, iclass 36, count 0 2006.257.02:08:06.42#ibcon#flushed, iclass 36, count 0 2006.257.02:08:06.42#ibcon#about to write, iclass 36, count 0 2006.257.02:08:06.42#ibcon#wrote, iclass 36, count 0 2006.257.02:08:06.42#ibcon#about to read 3, iclass 36, count 0 2006.257.02:08:06.45#ibcon#read 3, iclass 36, count 0 2006.257.02:08:06.45#ibcon#about to read 4, iclass 36, count 0 2006.257.02:08:06.45#ibcon#read 4, iclass 36, count 0 2006.257.02:08:06.45#ibcon#about to read 5, iclass 36, count 0 2006.257.02:08:06.45#ibcon#read 5, iclass 36, count 0 2006.257.02:08:06.45#ibcon#about to read 6, iclass 36, count 0 2006.257.02:08:06.45#ibcon#read 6, iclass 36, count 0 2006.257.02:08:06.45#ibcon#end of sib2, iclass 36, count 0 2006.257.02:08:06.45#ibcon#*after write, iclass 36, count 0 2006.257.02:08:06.45#ibcon#*before return 0, iclass 36, count 0 2006.257.02:08:06.45#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:06.45#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:06.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:08:06.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:08:06.45$vck44/valo=3,564.99 2006.257.02:08:06.45#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.02:08:06.45#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.02:08:06.45#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:06.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:06.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:06.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:06.45#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:08:06.45#ibcon#first serial, iclass 38, count 0 2006.257.02:08:06.45#ibcon#enter sib2, iclass 38, count 0 2006.257.02:08:06.45#ibcon#flushed, iclass 38, count 0 2006.257.02:08:06.45#ibcon#about to write, iclass 38, count 0 2006.257.02:08:06.45#ibcon#wrote, iclass 38, count 0 2006.257.02:08:06.45#ibcon#about to read 3, iclass 38, count 0 2006.257.02:08:06.48#ibcon#read 3, iclass 38, count 0 2006.257.02:08:06.48#ibcon#about to read 4, iclass 38, count 0 2006.257.02:08:06.48#ibcon#read 4, iclass 38, count 0 2006.257.02:08:06.48#ibcon#about to read 5, iclass 38, count 0 2006.257.02:08:06.48#ibcon#read 5, iclass 38, count 0 2006.257.02:08:06.48#ibcon#about to read 6, iclass 38, count 0 2006.257.02:08:06.48#ibcon#read 6, iclass 38, count 0 2006.257.02:08:06.48#ibcon#end of sib2, iclass 38, count 0 2006.257.02:08:06.48#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:08:06.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:08:06.48#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:08:06.48#ibcon#*before write, iclass 38, count 0 2006.257.02:08:06.48#ibcon#enter sib2, iclass 38, count 0 2006.257.02:08:06.48#ibcon#flushed, iclass 38, count 0 2006.257.02:08:06.48#ibcon#about to write, iclass 38, count 0 2006.257.02:08:06.48#ibcon#wrote, iclass 38, count 0 2006.257.02:08:06.48#ibcon#about to read 3, iclass 38, count 0 2006.257.02:08:06.52#ibcon#read 3, iclass 38, count 0 2006.257.02:08:06.52#ibcon#about to read 4, iclass 38, count 0 2006.257.02:08:06.52#ibcon#read 4, iclass 38, count 0 2006.257.02:08:06.52#ibcon#about to read 5, iclass 38, count 0 2006.257.02:08:06.52#ibcon#read 5, iclass 38, count 0 2006.257.02:08:06.52#ibcon#about to read 6, iclass 38, count 0 2006.257.02:08:06.52#ibcon#read 6, iclass 38, count 0 2006.257.02:08:06.52#ibcon#end of sib2, iclass 38, count 0 2006.257.02:08:06.52#ibcon#*after write, iclass 38, count 0 2006.257.02:08:06.52#ibcon#*before return 0, iclass 38, count 0 2006.257.02:08:06.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:06.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:06.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:08:06.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:08:06.52$vck44/va=3,8 2006.257.02:08:06.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.02:08:06.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.02:08:06.52#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:06.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:06.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:06.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:06.57#ibcon#enter wrdev, iclass 40, count 2 2006.257.02:08:06.57#ibcon#first serial, iclass 40, count 2 2006.257.02:08:06.57#ibcon#enter sib2, iclass 40, count 2 2006.257.02:08:06.57#ibcon#flushed, iclass 40, count 2 2006.257.02:08:06.57#ibcon#about to write, iclass 40, count 2 2006.257.02:08:06.57#ibcon#wrote, iclass 40, count 2 2006.257.02:08:06.57#ibcon#about to read 3, iclass 40, count 2 2006.257.02:08:06.59#ibcon#read 3, iclass 40, count 2 2006.257.02:08:06.59#ibcon#about to read 4, iclass 40, count 2 2006.257.02:08:06.59#ibcon#read 4, iclass 40, count 2 2006.257.02:08:06.59#ibcon#about to read 5, iclass 40, count 2 2006.257.02:08:06.59#ibcon#read 5, iclass 40, count 2 2006.257.02:08:06.59#ibcon#about to read 6, iclass 40, count 2 2006.257.02:08:06.59#ibcon#read 6, iclass 40, count 2 2006.257.02:08:06.59#ibcon#end of sib2, iclass 40, count 2 2006.257.02:08:06.59#ibcon#*mode == 0, iclass 40, count 2 2006.257.02:08:06.59#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.02:08:06.59#ibcon#[25=AT03-08\r\n] 2006.257.02:08:06.59#ibcon#*before write, iclass 40, count 2 2006.257.02:08:06.59#ibcon#enter sib2, iclass 40, count 2 2006.257.02:08:06.59#ibcon#flushed, iclass 40, count 2 2006.257.02:08:06.59#ibcon#about to write, iclass 40, count 2 2006.257.02:08:06.59#ibcon#wrote, iclass 40, count 2 2006.257.02:08:06.59#ibcon#about to read 3, iclass 40, count 2 2006.257.02:08:06.62#ibcon#read 3, iclass 40, count 2 2006.257.02:08:06.62#ibcon#about to read 4, iclass 40, count 2 2006.257.02:08:06.62#ibcon#read 4, iclass 40, count 2 2006.257.02:08:06.62#ibcon#about to read 5, iclass 40, count 2 2006.257.02:08:06.62#ibcon#read 5, iclass 40, count 2 2006.257.02:08:06.62#ibcon#about to read 6, iclass 40, count 2 2006.257.02:08:06.62#ibcon#read 6, iclass 40, count 2 2006.257.02:08:06.62#ibcon#end of sib2, iclass 40, count 2 2006.257.02:08:06.62#ibcon#*after write, iclass 40, count 2 2006.257.02:08:06.62#ibcon#*before return 0, iclass 40, count 2 2006.257.02:08:06.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:06.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:06.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.02:08:06.62#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:06.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:06.74#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:06.74#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:06.74#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:08:06.74#ibcon#first serial, iclass 40, count 0 2006.257.02:08:06.74#ibcon#enter sib2, iclass 40, count 0 2006.257.02:08:06.74#ibcon#flushed, iclass 40, count 0 2006.257.02:08:06.74#ibcon#about to write, iclass 40, count 0 2006.257.02:08:06.74#ibcon#wrote, iclass 40, count 0 2006.257.02:08:06.74#ibcon#about to read 3, iclass 40, count 0 2006.257.02:08:06.76#ibcon#read 3, iclass 40, count 0 2006.257.02:08:06.76#ibcon#about to read 4, iclass 40, count 0 2006.257.02:08:06.76#ibcon#read 4, iclass 40, count 0 2006.257.02:08:06.76#ibcon#about to read 5, iclass 40, count 0 2006.257.02:08:06.76#ibcon#read 5, iclass 40, count 0 2006.257.02:08:06.76#ibcon#about to read 6, iclass 40, count 0 2006.257.02:08:06.76#ibcon#read 6, iclass 40, count 0 2006.257.02:08:06.76#ibcon#end of sib2, iclass 40, count 0 2006.257.02:08:06.76#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:08:06.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:08:06.76#ibcon#[25=USB\r\n] 2006.257.02:08:06.76#ibcon#*before write, iclass 40, count 0 2006.257.02:08:06.76#ibcon#enter sib2, iclass 40, count 0 2006.257.02:08:06.76#ibcon#flushed, iclass 40, count 0 2006.257.02:08:06.76#ibcon#about to write, iclass 40, count 0 2006.257.02:08:06.76#ibcon#wrote, iclass 40, count 0 2006.257.02:08:06.76#ibcon#about to read 3, iclass 40, count 0 2006.257.02:08:06.79#ibcon#read 3, iclass 40, count 0 2006.257.02:08:06.79#ibcon#about to read 4, iclass 40, count 0 2006.257.02:08:06.79#ibcon#read 4, iclass 40, count 0 2006.257.02:08:06.79#ibcon#about to read 5, iclass 40, count 0 2006.257.02:08:06.79#ibcon#read 5, iclass 40, count 0 2006.257.02:08:06.79#ibcon#about to read 6, iclass 40, count 0 2006.257.02:08:06.79#ibcon#read 6, iclass 40, count 0 2006.257.02:08:06.79#ibcon#end of sib2, iclass 40, count 0 2006.257.02:08:06.79#ibcon#*after write, iclass 40, count 0 2006.257.02:08:06.79#ibcon#*before return 0, iclass 40, count 0 2006.257.02:08:06.79#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:06.79#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:06.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:08:06.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:08:06.79$vck44/valo=4,624.99 2006.257.02:08:06.79#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.02:08:06.79#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.02:08:06.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:06.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:06.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:06.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:06.79#ibcon#enter wrdev, iclass 4, count 0 2006.257.02:08:06.79#ibcon#first serial, iclass 4, count 0 2006.257.02:08:06.79#ibcon#enter sib2, iclass 4, count 0 2006.257.02:08:06.79#ibcon#flushed, iclass 4, count 0 2006.257.02:08:06.79#ibcon#about to write, iclass 4, count 0 2006.257.02:08:06.79#ibcon#wrote, iclass 4, count 0 2006.257.02:08:06.79#ibcon#about to read 3, iclass 4, count 0 2006.257.02:08:06.81#ibcon#read 3, iclass 4, count 0 2006.257.02:08:06.81#ibcon#about to read 4, iclass 4, count 0 2006.257.02:08:06.81#ibcon#read 4, iclass 4, count 0 2006.257.02:08:06.81#ibcon#about to read 5, iclass 4, count 0 2006.257.02:08:06.81#ibcon#read 5, iclass 4, count 0 2006.257.02:08:06.81#ibcon#about to read 6, iclass 4, count 0 2006.257.02:08:06.81#ibcon#read 6, iclass 4, count 0 2006.257.02:08:06.81#ibcon#end of sib2, iclass 4, count 0 2006.257.02:08:06.81#ibcon#*mode == 0, iclass 4, count 0 2006.257.02:08:06.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.02:08:06.81#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:08:06.81#ibcon#*before write, iclass 4, count 0 2006.257.02:08:06.81#ibcon#enter sib2, iclass 4, count 0 2006.257.02:08:06.81#ibcon#flushed, iclass 4, count 0 2006.257.02:08:06.81#ibcon#about to write, iclass 4, count 0 2006.257.02:08:06.81#ibcon#wrote, iclass 4, count 0 2006.257.02:08:06.81#ibcon#about to read 3, iclass 4, count 0 2006.257.02:08:06.85#ibcon#read 3, iclass 4, count 0 2006.257.02:08:06.85#ibcon#about to read 4, iclass 4, count 0 2006.257.02:08:06.85#ibcon#read 4, iclass 4, count 0 2006.257.02:08:06.85#ibcon#about to read 5, iclass 4, count 0 2006.257.02:08:06.85#ibcon#read 5, iclass 4, count 0 2006.257.02:08:06.85#ibcon#about to read 6, iclass 4, count 0 2006.257.02:08:06.85#ibcon#read 6, iclass 4, count 0 2006.257.02:08:06.85#ibcon#end of sib2, iclass 4, count 0 2006.257.02:08:06.85#ibcon#*after write, iclass 4, count 0 2006.257.02:08:06.85#ibcon#*before return 0, iclass 4, count 0 2006.257.02:08:06.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:06.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:06.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.02:08:06.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.02:08:06.85$vck44/va=4,7 2006.257.02:08:06.85#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.02:08:06.85#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.02:08:06.85#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:06.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:06.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:06.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:06.91#ibcon#enter wrdev, iclass 6, count 2 2006.257.02:08:06.91#ibcon#first serial, iclass 6, count 2 2006.257.02:08:06.91#ibcon#enter sib2, iclass 6, count 2 2006.257.02:08:06.91#ibcon#flushed, iclass 6, count 2 2006.257.02:08:06.91#ibcon#about to write, iclass 6, count 2 2006.257.02:08:06.91#ibcon#wrote, iclass 6, count 2 2006.257.02:08:06.91#ibcon#about to read 3, iclass 6, count 2 2006.257.02:08:06.93#ibcon#read 3, iclass 6, count 2 2006.257.02:08:06.93#ibcon#about to read 4, iclass 6, count 2 2006.257.02:08:06.93#ibcon#read 4, iclass 6, count 2 2006.257.02:08:06.93#ibcon#about to read 5, iclass 6, count 2 2006.257.02:08:06.93#ibcon#read 5, iclass 6, count 2 2006.257.02:08:06.93#ibcon#about to read 6, iclass 6, count 2 2006.257.02:08:06.93#ibcon#read 6, iclass 6, count 2 2006.257.02:08:06.93#ibcon#end of sib2, iclass 6, count 2 2006.257.02:08:06.93#ibcon#*mode == 0, iclass 6, count 2 2006.257.02:08:06.93#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.02:08:06.93#ibcon#[25=AT04-07\r\n] 2006.257.02:08:06.93#ibcon#*before write, iclass 6, count 2 2006.257.02:08:06.93#ibcon#enter sib2, iclass 6, count 2 2006.257.02:08:06.93#ibcon#flushed, iclass 6, count 2 2006.257.02:08:06.93#ibcon#about to write, iclass 6, count 2 2006.257.02:08:06.93#ibcon#wrote, iclass 6, count 2 2006.257.02:08:06.93#ibcon#about to read 3, iclass 6, count 2 2006.257.02:08:06.96#ibcon#read 3, iclass 6, count 2 2006.257.02:08:06.96#ibcon#about to read 4, iclass 6, count 2 2006.257.02:08:06.96#ibcon#read 4, iclass 6, count 2 2006.257.02:08:06.96#ibcon#about to read 5, iclass 6, count 2 2006.257.02:08:06.96#ibcon#read 5, iclass 6, count 2 2006.257.02:08:06.96#ibcon#about to read 6, iclass 6, count 2 2006.257.02:08:06.96#ibcon#read 6, iclass 6, count 2 2006.257.02:08:06.96#ibcon#end of sib2, iclass 6, count 2 2006.257.02:08:06.96#ibcon#*after write, iclass 6, count 2 2006.257.02:08:06.96#ibcon#*before return 0, iclass 6, count 2 2006.257.02:08:06.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:06.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:06.96#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.02:08:06.96#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:06.96#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:07.08#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:07.08#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:07.08#ibcon#enter wrdev, iclass 6, count 0 2006.257.02:08:07.08#ibcon#first serial, iclass 6, count 0 2006.257.02:08:07.08#ibcon#enter sib2, iclass 6, count 0 2006.257.02:08:07.08#ibcon#flushed, iclass 6, count 0 2006.257.02:08:07.08#ibcon#about to write, iclass 6, count 0 2006.257.02:08:07.08#ibcon#wrote, iclass 6, count 0 2006.257.02:08:07.08#ibcon#about to read 3, iclass 6, count 0 2006.257.02:08:07.10#ibcon#read 3, iclass 6, count 0 2006.257.02:08:07.10#ibcon#about to read 4, iclass 6, count 0 2006.257.02:08:07.10#ibcon#read 4, iclass 6, count 0 2006.257.02:08:07.10#ibcon#about to read 5, iclass 6, count 0 2006.257.02:08:07.10#ibcon#read 5, iclass 6, count 0 2006.257.02:08:07.10#ibcon#about to read 6, iclass 6, count 0 2006.257.02:08:07.10#ibcon#read 6, iclass 6, count 0 2006.257.02:08:07.10#ibcon#end of sib2, iclass 6, count 0 2006.257.02:08:07.10#ibcon#*mode == 0, iclass 6, count 0 2006.257.02:08:07.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.02:08:07.10#ibcon#[25=USB\r\n] 2006.257.02:08:07.10#ibcon#*before write, iclass 6, count 0 2006.257.02:08:07.10#ibcon#enter sib2, iclass 6, count 0 2006.257.02:08:07.10#ibcon#flushed, iclass 6, count 0 2006.257.02:08:07.10#ibcon#about to write, iclass 6, count 0 2006.257.02:08:07.10#ibcon#wrote, iclass 6, count 0 2006.257.02:08:07.10#ibcon#about to read 3, iclass 6, count 0 2006.257.02:08:07.13#ibcon#read 3, iclass 6, count 0 2006.257.02:08:07.13#ibcon#about to read 4, iclass 6, count 0 2006.257.02:08:07.13#ibcon#read 4, iclass 6, count 0 2006.257.02:08:07.13#ibcon#about to read 5, iclass 6, count 0 2006.257.02:08:07.13#ibcon#read 5, iclass 6, count 0 2006.257.02:08:07.13#ibcon#about to read 6, iclass 6, count 0 2006.257.02:08:07.13#ibcon#read 6, iclass 6, count 0 2006.257.02:08:07.13#ibcon#end of sib2, iclass 6, count 0 2006.257.02:08:07.13#ibcon#*after write, iclass 6, count 0 2006.257.02:08:07.13#ibcon#*before return 0, iclass 6, count 0 2006.257.02:08:07.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:07.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:07.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.02:08:07.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.02:08:07.13$vck44/valo=5,734.99 2006.257.02:08:07.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.02:08:07.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.02:08:07.13#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:07.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:07.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:07.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:07.13#ibcon#enter wrdev, iclass 10, count 0 2006.257.02:08:07.13#ibcon#first serial, iclass 10, count 0 2006.257.02:08:07.13#ibcon#enter sib2, iclass 10, count 0 2006.257.02:08:07.13#ibcon#flushed, iclass 10, count 0 2006.257.02:08:07.13#ibcon#about to write, iclass 10, count 0 2006.257.02:08:07.13#ibcon#wrote, iclass 10, count 0 2006.257.02:08:07.13#ibcon#about to read 3, iclass 10, count 0 2006.257.02:08:07.15#ibcon#read 3, iclass 10, count 0 2006.257.02:08:07.15#ibcon#about to read 4, iclass 10, count 0 2006.257.02:08:07.15#ibcon#read 4, iclass 10, count 0 2006.257.02:08:07.15#ibcon#about to read 5, iclass 10, count 0 2006.257.02:08:07.15#ibcon#read 5, iclass 10, count 0 2006.257.02:08:07.15#ibcon#about to read 6, iclass 10, count 0 2006.257.02:08:07.15#ibcon#read 6, iclass 10, count 0 2006.257.02:08:07.15#ibcon#end of sib2, iclass 10, count 0 2006.257.02:08:07.15#ibcon#*mode == 0, iclass 10, count 0 2006.257.02:08:07.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.02:08:07.15#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:08:07.15#ibcon#*before write, iclass 10, count 0 2006.257.02:08:07.15#ibcon#enter sib2, iclass 10, count 0 2006.257.02:08:07.15#ibcon#flushed, iclass 10, count 0 2006.257.02:08:07.15#ibcon#about to write, iclass 10, count 0 2006.257.02:08:07.15#ibcon#wrote, iclass 10, count 0 2006.257.02:08:07.15#ibcon#about to read 3, iclass 10, count 0 2006.257.02:08:07.19#ibcon#read 3, iclass 10, count 0 2006.257.02:08:07.19#ibcon#about to read 4, iclass 10, count 0 2006.257.02:08:07.19#ibcon#read 4, iclass 10, count 0 2006.257.02:08:07.19#ibcon#about to read 5, iclass 10, count 0 2006.257.02:08:07.19#ibcon#read 5, iclass 10, count 0 2006.257.02:08:07.19#ibcon#about to read 6, iclass 10, count 0 2006.257.02:08:07.19#ibcon#read 6, iclass 10, count 0 2006.257.02:08:07.19#ibcon#end of sib2, iclass 10, count 0 2006.257.02:08:07.19#ibcon#*after write, iclass 10, count 0 2006.257.02:08:07.19#ibcon#*before return 0, iclass 10, count 0 2006.257.02:08:07.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:07.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:07.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.02:08:07.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.02:08:07.19$vck44/va=5,4 2006.257.02:08:07.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.02:08:07.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.02:08:07.19#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:07.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:07.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:07.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:07.25#ibcon#enter wrdev, iclass 12, count 2 2006.257.02:08:07.25#ibcon#first serial, iclass 12, count 2 2006.257.02:08:07.25#ibcon#enter sib2, iclass 12, count 2 2006.257.02:08:07.25#ibcon#flushed, iclass 12, count 2 2006.257.02:08:07.25#ibcon#about to write, iclass 12, count 2 2006.257.02:08:07.25#ibcon#wrote, iclass 12, count 2 2006.257.02:08:07.25#ibcon#about to read 3, iclass 12, count 2 2006.257.02:08:07.27#ibcon#read 3, iclass 12, count 2 2006.257.02:08:07.27#ibcon#about to read 4, iclass 12, count 2 2006.257.02:08:07.27#ibcon#read 4, iclass 12, count 2 2006.257.02:08:07.27#ibcon#about to read 5, iclass 12, count 2 2006.257.02:08:07.27#ibcon#read 5, iclass 12, count 2 2006.257.02:08:07.27#ibcon#about to read 6, iclass 12, count 2 2006.257.02:08:07.27#ibcon#read 6, iclass 12, count 2 2006.257.02:08:07.27#ibcon#end of sib2, iclass 12, count 2 2006.257.02:08:07.27#ibcon#*mode == 0, iclass 12, count 2 2006.257.02:08:07.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.02:08:07.27#ibcon#[25=AT05-04\r\n] 2006.257.02:08:07.27#ibcon#*before write, iclass 12, count 2 2006.257.02:08:07.27#ibcon#enter sib2, iclass 12, count 2 2006.257.02:08:07.27#ibcon#flushed, iclass 12, count 2 2006.257.02:08:07.27#ibcon#about to write, iclass 12, count 2 2006.257.02:08:07.27#ibcon#wrote, iclass 12, count 2 2006.257.02:08:07.27#ibcon#about to read 3, iclass 12, count 2 2006.257.02:08:07.30#ibcon#read 3, iclass 12, count 2 2006.257.02:08:07.30#ibcon#about to read 4, iclass 12, count 2 2006.257.02:08:07.30#ibcon#read 4, iclass 12, count 2 2006.257.02:08:07.30#ibcon#about to read 5, iclass 12, count 2 2006.257.02:08:07.30#ibcon#read 5, iclass 12, count 2 2006.257.02:08:07.30#ibcon#about to read 6, iclass 12, count 2 2006.257.02:08:07.30#ibcon#read 6, iclass 12, count 2 2006.257.02:08:07.30#ibcon#end of sib2, iclass 12, count 2 2006.257.02:08:07.30#ibcon#*after write, iclass 12, count 2 2006.257.02:08:07.30#ibcon#*before return 0, iclass 12, count 2 2006.257.02:08:07.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:07.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:07.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.02:08:07.30#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:07.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:07.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:07.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:07.42#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:08:07.42#ibcon#first serial, iclass 12, count 0 2006.257.02:08:07.42#ibcon#enter sib2, iclass 12, count 0 2006.257.02:08:07.42#ibcon#flushed, iclass 12, count 0 2006.257.02:08:07.42#ibcon#about to write, iclass 12, count 0 2006.257.02:08:07.42#ibcon#wrote, iclass 12, count 0 2006.257.02:08:07.42#ibcon#about to read 3, iclass 12, count 0 2006.257.02:08:07.44#ibcon#read 3, iclass 12, count 0 2006.257.02:08:07.44#ibcon#about to read 4, iclass 12, count 0 2006.257.02:08:07.44#ibcon#read 4, iclass 12, count 0 2006.257.02:08:07.44#ibcon#about to read 5, iclass 12, count 0 2006.257.02:08:07.44#ibcon#read 5, iclass 12, count 0 2006.257.02:08:07.44#ibcon#about to read 6, iclass 12, count 0 2006.257.02:08:07.44#ibcon#read 6, iclass 12, count 0 2006.257.02:08:07.44#ibcon#end of sib2, iclass 12, count 0 2006.257.02:08:07.44#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:08:07.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:08:07.44#ibcon#[25=USB\r\n] 2006.257.02:08:07.44#ibcon#*before write, iclass 12, count 0 2006.257.02:08:07.44#ibcon#enter sib2, iclass 12, count 0 2006.257.02:08:07.44#ibcon#flushed, iclass 12, count 0 2006.257.02:08:07.44#ibcon#about to write, iclass 12, count 0 2006.257.02:08:07.44#ibcon#wrote, iclass 12, count 0 2006.257.02:08:07.44#ibcon#about to read 3, iclass 12, count 0 2006.257.02:08:07.47#ibcon#read 3, iclass 12, count 0 2006.257.02:08:07.47#ibcon#about to read 4, iclass 12, count 0 2006.257.02:08:07.47#ibcon#read 4, iclass 12, count 0 2006.257.02:08:07.47#ibcon#about to read 5, iclass 12, count 0 2006.257.02:08:07.47#ibcon#read 5, iclass 12, count 0 2006.257.02:08:07.47#ibcon#about to read 6, iclass 12, count 0 2006.257.02:08:07.47#ibcon#read 6, iclass 12, count 0 2006.257.02:08:07.47#ibcon#end of sib2, iclass 12, count 0 2006.257.02:08:07.47#ibcon#*after write, iclass 12, count 0 2006.257.02:08:07.47#ibcon#*before return 0, iclass 12, count 0 2006.257.02:08:07.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:07.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:07.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:08:07.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:08:07.47$vck44/valo=6,814.99 2006.257.02:08:07.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.02:08:07.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.02:08:07.47#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:07.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:07.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:07.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:07.47#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:08:07.47#ibcon#first serial, iclass 14, count 0 2006.257.02:08:07.47#ibcon#enter sib2, iclass 14, count 0 2006.257.02:08:07.47#ibcon#flushed, iclass 14, count 0 2006.257.02:08:07.47#ibcon#about to write, iclass 14, count 0 2006.257.02:08:07.47#ibcon#wrote, iclass 14, count 0 2006.257.02:08:07.47#ibcon#about to read 3, iclass 14, count 0 2006.257.02:08:07.49#ibcon#read 3, iclass 14, count 0 2006.257.02:08:07.49#ibcon#about to read 4, iclass 14, count 0 2006.257.02:08:07.49#ibcon#read 4, iclass 14, count 0 2006.257.02:08:07.49#ibcon#about to read 5, iclass 14, count 0 2006.257.02:08:07.49#ibcon#read 5, iclass 14, count 0 2006.257.02:08:07.49#ibcon#about to read 6, iclass 14, count 0 2006.257.02:08:07.49#ibcon#read 6, iclass 14, count 0 2006.257.02:08:07.49#ibcon#end of sib2, iclass 14, count 0 2006.257.02:08:07.49#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:08:07.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:08:07.49#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:08:07.49#ibcon#*before write, iclass 14, count 0 2006.257.02:08:07.49#ibcon#enter sib2, iclass 14, count 0 2006.257.02:08:07.49#ibcon#flushed, iclass 14, count 0 2006.257.02:08:07.49#ibcon#about to write, iclass 14, count 0 2006.257.02:08:07.49#ibcon#wrote, iclass 14, count 0 2006.257.02:08:07.49#ibcon#about to read 3, iclass 14, count 0 2006.257.02:08:07.53#ibcon#read 3, iclass 14, count 0 2006.257.02:08:07.53#ibcon#about to read 4, iclass 14, count 0 2006.257.02:08:07.53#ibcon#read 4, iclass 14, count 0 2006.257.02:08:07.53#ibcon#about to read 5, iclass 14, count 0 2006.257.02:08:07.53#ibcon#read 5, iclass 14, count 0 2006.257.02:08:07.53#ibcon#about to read 6, iclass 14, count 0 2006.257.02:08:07.53#ibcon#read 6, iclass 14, count 0 2006.257.02:08:07.53#ibcon#end of sib2, iclass 14, count 0 2006.257.02:08:07.53#ibcon#*after write, iclass 14, count 0 2006.257.02:08:07.53#ibcon#*before return 0, iclass 14, count 0 2006.257.02:08:07.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:07.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:07.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:08:07.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:08:07.53$vck44/va=6,4 2006.257.02:08:07.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.02:08:07.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.02:08:07.53#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:07.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:07.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:07.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:07.59#ibcon#enter wrdev, iclass 16, count 2 2006.257.02:08:07.59#ibcon#first serial, iclass 16, count 2 2006.257.02:08:07.59#ibcon#enter sib2, iclass 16, count 2 2006.257.02:08:07.59#ibcon#flushed, iclass 16, count 2 2006.257.02:08:07.59#ibcon#about to write, iclass 16, count 2 2006.257.02:08:07.59#ibcon#wrote, iclass 16, count 2 2006.257.02:08:07.59#ibcon#about to read 3, iclass 16, count 2 2006.257.02:08:07.61#ibcon#read 3, iclass 16, count 2 2006.257.02:08:07.61#ibcon#about to read 4, iclass 16, count 2 2006.257.02:08:07.61#ibcon#read 4, iclass 16, count 2 2006.257.02:08:07.61#ibcon#about to read 5, iclass 16, count 2 2006.257.02:08:07.61#ibcon#read 5, iclass 16, count 2 2006.257.02:08:07.61#ibcon#about to read 6, iclass 16, count 2 2006.257.02:08:07.61#ibcon#read 6, iclass 16, count 2 2006.257.02:08:07.61#ibcon#end of sib2, iclass 16, count 2 2006.257.02:08:07.61#ibcon#*mode == 0, iclass 16, count 2 2006.257.02:08:07.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.02:08:07.61#ibcon#[25=AT06-04\r\n] 2006.257.02:08:07.61#ibcon#*before write, iclass 16, count 2 2006.257.02:08:07.61#ibcon#enter sib2, iclass 16, count 2 2006.257.02:08:07.61#ibcon#flushed, iclass 16, count 2 2006.257.02:08:07.61#ibcon#about to write, iclass 16, count 2 2006.257.02:08:07.61#ibcon#wrote, iclass 16, count 2 2006.257.02:08:07.61#ibcon#about to read 3, iclass 16, count 2 2006.257.02:08:07.64#ibcon#read 3, iclass 16, count 2 2006.257.02:08:07.64#ibcon#about to read 4, iclass 16, count 2 2006.257.02:08:07.64#ibcon#read 4, iclass 16, count 2 2006.257.02:08:07.64#ibcon#about to read 5, iclass 16, count 2 2006.257.02:08:07.64#ibcon#read 5, iclass 16, count 2 2006.257.02:08:07.64#ibcon#about to read 6, iclass 16, count 2 2006.257.02:08:07.64#ibcon#read 6, iclass 16, count 2 2006.257.02:08:07.64#ibcon#end of sib2, iclass 16, count 2 2006.257.02:08:07.64#ibcon#*after write, iclass 16, count 2 2006.257.02:08:07.64#ibcon#*before return 0, iclass 16, count 2 2006.257.02:08:07.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:07.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:07.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.02:08:07.64#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:07.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:07.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:07.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:07.76#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:08:07.76#ibcon#first serial, iclass 16, count 0 2006.257.02:08:07.76#ibcon#enter sib2, iclass 16, count 0 2006.257.02:08:07.76#ibcon#flushed, iclass 16, count 0 2006.257.02:08:07.76#ibcon#about to write, iclass 16, count 0 2006.257.02:08:07.76#ibcon#wrote, iclass 16, count 0 2006.257.02:08:07.76#ibcon#about to read 3, iclass 16, count 0 2006.257.02:08:07.78#ibcon#read 3, iclass 16, count 0 2006.257.02:08:07.78#ibcon#about to read 4, iclass 16, count 0 2006.257.02:08:07.78#ibcon#read 4, iclass 16, count 0 2006.257.02:08:07.78#ibcon#about to read 5, iclass 16, count 0 2006.257.02:08:07.78#ibcon#read 5, iclass 16, count 0 2006.257.02:08:07.78#ibcon#about to read 6, iclass 16, count 0 2006.257.02:08:07.78#ibcon#read 6, iclass 16, count 0 2006.257.02:08:07.78#ibcon#end of sib2, iclass 16, count 0 2006.257.02:08:07.78#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:08:07.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:08:07.78#ibcon#[25=USB\r\n] 2006.257.02:08:07.78#ibcon#*before write, iclass 16, count 0 2006.257.02:08:07.78#ibcon#enter sib2, iclass 16, count 0 2006.257.02:08:07.78#ibcon#flushed, iclass 16, count 0 2006.257.02:08:07.78#ibcon#about to write, iclass 16, count 0 2006.257.02:08:07.78#ibcon#wrote, iclass 16, count 0 2006.257.02:08:07.78#ibcon#about to read 3, iclass 16, count 0 2006.257.02:08:07.81#ibcon#read 3, iclass 16, count 0 2006.257.02:08:07.81#ibcon#about to read 4, iclass 16, count 0 2006.257.02:08:07.81#ibcon#read 4, iclass 16, count 0 2006.257.02:08:07.81#ibcon#about to read 5, iclass 16, count 0 2006.257.02:08:07.81#ibcon#read 5, iclass 16, count 0 2006.257.02:08:07.81#ibcon#about to read 6, iclass 16, count 0 2006.257.02:08:07.81#ibcon#read 6, iclass 16, count 0 2006.257.02:08:07.81#ibcon#end of sib2, iclass 16, count 0 2006.257.02:08:07.81#ibcon#*after write, iclass 16, count 0 2006.257.02:08:07.81#ibcon#*before return 0, iclass 16, count 0 2006.257.02:08:07.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:07.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:07.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:08:07.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:08:07.81$vck44/valo=7,864.99 2006.257.02:08:07.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.02:08:07.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.02:08:07.81#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:07.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:07.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:07.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:07.81#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:08:07.81#ibcon#first serial, iclass 18, count 0 2006.257.02:08:07.81#ibcon#enter sib2, iclass 18, count 0 2006.257.02:08:07.81#ibcon#flushed, iclass 18, count 0 2006.257.02:08:07.81#ibcon#about to write, iclass 18, count 0 2006.257.02:08:07.81#ibcon#wrote, iclass 18, count 0 2006.257.02:08:07.81#ibcon#about to read 3, iclass 18, count 0 2006.257.02:08:07.83#ibcon#read 3, iclass 18, count 0 2006.257.02:08:07.83#ibcon#about to read 4, iclass 18, count 0 2006.257.02:08:07.83#ibcon#read 4, iclass 18, count 0 2006.257.02:08:07.83#ibcon#about to read 5, iclass 18, count 0 2006.257.02:08:07.83#ibcon#read 5, iclass 18, count 0 2006.257.02:08:07.83#ibcon#about to read 6, iclass 18, count 0 2006.257.02:08:07.83#ibcon#read 6, iclass 18, count 0 2006.257.02:08:07.83#ibcon#end of sib2, iclass 18, count 0 2006.257.02:08:07.83#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:08:07.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:08:07.83#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:08:07.83#ibcon#*before write, iclass 18, count 0 2006.257.02:08:07.83#ibcon#enter sib2, iclass 18, count 0 2006.257.02:08:07.83#ibcon#flushed, iclass 18, count 0 2006.257.02:08:07.83#ibcon#about to write, iclass 18, count 0 2006.257.02:08:07.83#ibcon#wrote, iclass 18, count 0 2006.257.02:08:07.83#ibcon#about to read 3, iclass 18, count 0 2006.257.02:08:07.87#ibcon#read 3, iclass 18, count 0 2006.257.02:08:07.87#ibcon#about to read 4, iclass 18, count 0 2006.257.02:08:07.87#ibcon#read 4, iclass 18, count 0 2006.257.02:08:07.87#ibcon#about to read 5, iclass 18, count 0 2006.257.02:08:07.87#ibcon#read 5, iclass 18, count 0 2006.257.02:08:07.87#ibcon#about to read 6, iclass 18, count 0 2006.257.02:08:07.87#ibcon#read 6, iclass 18, count 0 2006.257.02:08:07.87#ibcon#end of sib2, iclass 18, count 0 2006.257.02:08:07.87#ibcon#*after write, iclass 18, count 0 2006.257.02:08:07.87#ibcon#*before return 0, iclass 18, count 0 2006.257.02:08:07.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:07.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:07.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:08:07.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:08:07.87$vck44/va=7,4 2006.257.02:08:07.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.02:08:07.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.02:08:07.87#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:07.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:07.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:07.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:07.93#ibcon#enter wrdev, iclass 20, count 2 2006.257.02:08:07.93#ibcon#first serial, iclass 20, count 2 2006.257.02:08:07.93#ibcon#enter sib2, iclass 20, count 2 2006.257.02:08:07.93#ibcon#flushed, iclass 20, count 2 2006.257.02:08:07.93#ibcon#about to write, iclass 20, count 2 2006.257.02:08:07.93#ibcon#wrote, iclass 20, count 2 2006.257.02:08:07.93#ibcon#about to read 3, iclass 20, count 2 2006.257.02:08:07.95#ibcon#read 3, iclass 20, count 2 2006.257.02:08:07.95#ibcon#about to read 4, iclass 20, count 2 2006.257.02:08:07.95#ibcon#read 4, iclass 20, count 2 2006.257.02:08:07.95#ibcon#about to read 5, iclass 20, count 2 2006.257.02:08:07.95#ibcon#read 5, iclass 20, count 2 2006.257.02:08:07.95#ibcon#about to read 6, iclass 20, count 2 2006.257.02:08:07.95#ibcon#read 6, iclass 20, count 2 2006.257.02:08:07.95#ibcon#end of sib2, iclass 20, count 2 2006.257.02:08:07.95#ibcon#*mode == 0, iclass 20, count 2 2006.257.02:08:07.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.02:08:07.95#ibcon#[25=AT07-04\r\n] 2006.257.02:08:07.95#ibcon#*before write, iclass 20, count 2 2006.257.02:08:07.95#ibcon#enter sib2, iclass 20, count 2 2006.257.02:08:07.95#ibcon#flushed, iclass 20, count 2 2006.257.02:08:07.95#ibcon#about to write, iclass 20, count 2 2006.257.02:08:07.95#ibcon#wrote, iclass 20, count 2 2006.257.02:08:07.95#ibcon#about to read 3, iclass 20, count 2 2006.257.02:08:07.98#ibcon#read 3, iclass 20, count 2 2006.257.02:08:07.98#ibcon#about to read 4, iclass 20, count 2 2006.257.02:08:07.98#ibcon#read 4, iclass 20, count 2 2006.257.02:08:07.98#ibcon#about to read 5, iclass 20, count 2 2006.257.02:08:07.98#ibcon#read 5, iclass 20, count 2 2006.257.02:08:07.98#ibcon#about to read 6, iclass 20, count 2 2006.257.02:08:07.98#ibcon#read 6, iclass 20, count 2 2006.257.02:08:07.98#ibcon#end of sib2, iclass 20, count 2 2006.257.02:08:07.98#ibcon#*after write, iclass 20, count 2 2006.257.02:08:07.98#ibcon#*before return 0, iclass 20, count 2 2006.257.02:08:07.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:07.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:07.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.02:08:07.98#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:07.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:08.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:08.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:08.10#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:08:08.10#ibcon#first serial, iclass 20, count 0 2006.257.02:08:08.10#ibcon#enter sib2, iclass 20, count 0 2006.257.02:08:08.10#ibcon#flushed, iclass 20, count 0 2006.257.02:08:08.10#ibcon#about to write, iclass 20, count 0 2006.257.02:08:08.10#ibcon#wrote, iclass 20, count 0 2006.257.02:08:08.10#ibcon#about to read 3, iclass 20, count 0 2006.257.02:08:08.12#ibcon#read 3, iclass 20, count 0 2006.257.02:08:08.12#ibcon#about to read 4, iclass 20, count 0 2006.257.02:08:08.12#ibcon#read 4, iclass 20, count 0 2006.257.02:08:08.12#ibcon#about to read 5, iclass 20, count 0 2006.257.02:08:08.12#ibcon#read 5, iclass 20, count 0 2006.257.02:08:08.12#ibcon#about to read 6, iclass 20, count 0 2006.257.02:08:08.12#ibcon#read 6, iclass 20, count 0 2006.257.02:08:08.12#ibcon#end of sib2, iclass 20, count 0 2006.257.02:08:08.12#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:08:08.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:08:08.12#ibcon#[25=USB\r\n] 2006.257.02:08:08.12#ibcon#*before write, iclass 20, count 0 2006.257.02:08:08.12#ibcon#enter sib2, iclass 20, count 0 2006.257.02:08:08.12#ibcon#flushed, iclass 20, count 0 2006.257.02:08:08.12#ibcon#about to write, iclass 20, count 0 2006.257.02:08:08.12#ibcon#wrote, iclass 20, count 0 2006.257.02:08:08.12#ibcon#about to read 3, iclass 20, count 0 2006.257.02:08:08.15#ibcon#read 3, iclass 20, count 0 2006.257.02:08:08.15#ibcon#about to read 4, iclass 20, count 0 2006.257.02:08:08.15#ibcon#read 4, iclass 20, count 0 2006.257.02:08:08.15#ibcon#about to read 5, iclass 20, count 0 2006.257.02:08:08.15#ibcon#read 5, iclass 20, count 0 2006.257.02:08:08.15#ibcon#about to read 6, iclass 20, count 0 2006.257.02:08:08.15#ibcon#read 6, iclass 20, count 0 2006.257.02:08:08.15#ibcon#end of sib2, iclass 20, count 0 2006.257.02:08:08.15#ibcon#*after write, iclass 20, count 0 2006.257.02:08:08.15#ibcon#*before return 0, iclass 20, count 0 2006.257.02:08:08.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:08.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:08.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:08:08.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:08:08.15$vck44/valo=8,884.99 2006.257.02:08:08.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.02:08:08.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.02:08:08.15#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:08.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:08.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:08.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:08.15#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:08:08.15#ibcon#first serial, iclass 22, count 0 2006.257.02:08:08.15#ibcon#enter sib2, iclass 22, count 0 2006.257.02:08:08.15#ibcon#flushed, iclass 22, count 0 2006.257.02:08:08.15#ibcon#about to write, iclass 22, count 0 2006.257.02:08:08.15#ibcon#wrote, iclass 22, count 0 2006.257.02:08:08.15#ibcon#about to read 3, iclass 22, count 0 2006.257.02:08:08.17#ibcon#read 3, iclass 22, count 0 2006.257.02:08:08.17#ibcon#about to read 4, iclass 22, count 0 2006.257.02:08:08.17#ibcon#read 4, iclass 22, count 0 2006.257.02:08:08.17#ibcon#about to read 5, iclass 22, count 0 2006.257.02:08:08.17#ibcon#read 5, iclass 22, count 0 2006.257.02:08:08.17#ibcon#about to read 6, iclass 22, count 0 2006.257.02:08:08.17#ibcon#read 6, iclass 22, count 0 2006.257.02:08:08.17#ibcon#end of sib2, iclass 22, count 0 2006.257.02:08:08.17#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:08:08.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:08:08.17#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:08:08.17#ibcon#*before write, iclass 22, count 0 2006.257.02:08:08.17#ibcon#enter sib2, iclass 22, count 0 2006.257.02:08:08.17#ibcon#flushed, iclass 22, count 0 2006.257.02:08:08.17#ibcon#about to write, iclass 22, count 0 2006.257.02:08:08.17#ibcon#wrote, iclass 22, count 0 2006.257.02:08:08.17#ibcon#about to read 3, iclass 22, count 0 2006.257.02:08:08.21#ibcon#read 3, iclass 22, count 0 2006.257.02:08:08.21#ibcon#about to read 4, iclass 22, count 0 2006.257.02:08:08.21#ibcon#read 4, iclass 22, count 0 2006.257.02:08:08.21#ibcon#about to read 5, iclass 22, count 0 2006.257.02:08:08.21#ibcon#read 5, iclass 22, count 0 2006.257.02:08:08.21#ibcon#about to read 6, iclass 22, count 0 2006.257.02:08:08.21#ibcon#read 6, iclass 22, count 0 2006.257.02:08:08.21#ibcon#end of sib2, iclass 22, count 0 2006.257.02:08:08.21#ibcon#*after write, iclass 22, count 0 2006.257.02:08:08.21#ibcon#*before return 0, iclass 22, count 0 2006.257.02:08:08.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:08.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:08.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:08:08.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:08:08.21$vck44/va=8,4 2006.257.02:08:08.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.02:08:08.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.02:08:08.21#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:08.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:08:08.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:08:08.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:08:08.27#ibcon#enter wrdev, iclass 24, count 2 2006.257.02:08:08.27#ibcon#first serial, iclass 24, count 2 2006.257.02:08:08.27#ibcon#enter sib2, iclass 24, count 2 2006.257.02:08:08.27#ibcon#flushed, iclass 24, count 2 2006.257.02:08:08.27#ibcon#about to write, iclass 24, count 2 2006.257.02:08:08.27#ibcon#wrote, iclass 24, count 2 2006.257.02:08:08.27#ibcon#about to read 3, iclass 24, count 2 2006.257.02:08:08.29#ibcon#read 3, iclass 24, count 2 2006.257.02:08:08.29#ibcon#about to read 4, iclass 24, count 2 2006.257.02:08:08.29#ibcon#read 4, iclass 24, count 2 2006.257.02:08:08.29#ibcon#about to read 5, iclass 24, count 2 2006.257.02:08:08.29#ibcon#read 5, iclass 24, count 2 2006.257.02:08:08.29#ibcon#about to read 6, iclass 24, count 2 2006.257.02:08:08.29#ibcon#read 6, iclass 24, count 2 2006.257.02:08:08.29#ibcon#end of sib2, iclass 24, count 2 2006.257.02:08:08.29#ibcon#*mode == 0, iclass 24, count 2 2006.257.02:08:08.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.02:08:08.29#ibcon#[25=AT08-04\r\n] 2006.257.02:08:08.29#ibcon#*before write, iclass 24, count 2 2006.257.02:08:08.29#ibcon#enter sib2, iclass 24, count 2 2006.257.02:08:08.29#ibcon#flushed, iclass 24, count 2 2006.257.02:08:08.29#ibcon#about to write, iclass 24, count 2 2006.257.02:08:08.29#ibcon#wrote, iclass 24, count 2 2006.257.02:08:08.29#ibcon#about to read 3, iclass 24, count 2 2006.257.02:08:08.32#ibcon#read 3, iclass 24, count 2 2006.257.02:08:08.32#ibcon#about to read 4, iclass 24, count 2 2006.257.02:08:08.32#ibcon#read 4, iclass 24, count 2 2006.257.02:08:08.32#ibcon#about to read 5, iclass 24, count 2 2006.257.02:08:08.32#ibcon#read 5, iclass 24, count 2 2006.257.02:08:08.32#ibcon#about to read 6, iclass 24, count 2 2006.257.02:08:08.32#ibcon#read 6, iclass 24, count 2 2006.257.02:08:08.32#ibcon#end of sib2, iclass 24, count 2 2006.257.02:08:08.32#ibcon#*after write, iclass 24, count 2 2006.257.02:08:08.32#ibcon#*before return 0, iclass 24, count 2 2006.257.02:08:08.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:08:08.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:08:08.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.02:08:08.32#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:08.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:08:08.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:08:08.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:08:08.44#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:08:08.44#ibcon#first serial, iclass 24, count 0 2006.257.02:08:08.44#ibcon#enter sib2, iclass 24, count 0 2006.257.02:08:08.44#ibcon#flushed, iclass 24, count 0 2006.257.02:08:08.44#ibcon#about to write, iclass 24, count 0 2006.257.02:08:08.44#ibcon#wrote, iclass 24, count 0 2006.257.02:08:08.44#ibcon#about to read 3, iclass 24, count 0 2006.257.02:08:08.46#ibcon#read 3, iclass 24, count 0 2006.257.02:08:08.46#ibcon#about to read 4, iclass 24, count 0 2006.257.02:08:08.46#ibcon#read 4, iclass 24, count 0 2006.257.02:08:08.46#ibcon#about to read 5, iclass 24, count 0 2006.257.02:08:08.46#ibcon#read 5, iclass 24, count 0 2006.257.02:08:08.46#ibcon#about to read 6, iclass 24, count 0 2006.257.02:08:08.46#ibcon#read 6, iclass 24, count 0 2006.257.02:08:08.46#ibcon#end of sib2, iclass 24, count 0 2006.257.02:08:08.46#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:08:08.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:08:08.46#ibcon#[25=USB\r\n] 2006.257.02:08:08.46#ibcon#*before write, iclass 24, count 0 2006.257.02:08:08.46#ibcon#enter sib2, iclass 24, count 0 2006.257.02:08:08.46#ibcon#flushed, iclass 24, count 0 2006.257.02:08:08.46#ibcon#about to write, iclass 24, count 0 2006.257.02:08:08.46#ibcon#wrote, iclass 24, count 0 2006.257.02:08:08.46#ibcon#about to read 3, iclass 24, count 0 2006.257.02:08:08.49#ibcon#read 3, iclass 24, count 0 2006.257.02:08:08.49#ibcon#about to read 4, iclass 24, count 0 2006.257.02:08:08.49#ibcon#read 4, iclass 24, count 0 2006.257.02:08:08.49#ibcon#about to read 5, iclass 24, count 0 2006.257.02:08:08.49#ibcon#read 5, iclass 24, count 0 2006.257.02:08:08.49#ibcon#about to read 6, iclass 24, count 0 2006.257.02:08:08.49#ibcon#read 6, iclass 24, count 0 2006.257.02:08:08.49#ibcon#end of sib2, iclass 24, count 0 2006.257.02:08:08.49#ibcon#*after write, iclass 24, count 0 2006.257.02:08:08.49#ibcon#*before return 0, iclass 24, count 0 2006.257.02:08:08.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:08:08.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:08:08.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:08:08.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:08:08.49$vck44/vblo=1,629.99 2006.257.02:08:08.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.02:08:08.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.02:08:08.49#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:08.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:08:08.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:08:08.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:08:08.49#ibcon#enter wrdev, iclass 26, count 0 2006.257.02:08:08.49#ibcon#first serial, iclass 26, count 0 2006.257.02:08:08.49#ibcon#enter sib2, iclass 26, count 0 2006.257.02:08:08.49#ibcon#flushed, iclass 26, count 0 2006.257.02:08:08.49#ibcon#about to write, iclass 26, count 0 2006.257.02:08:08.49#ibcon#wrote, iclass 26, count 0 2006.257.02:08:08.49#ibcon#about to read 3, iclass 26, count 0 2006.257.02:08:08.51#ibcon#read 3, iclass 26, count 0 2006.257.02:08:08.51#ibcon#about to read 4, iclass 26, count 0 2006.257.02:08:08.51#ibcon#read 4, iclass 26, count 0 2006.257.02:08:08.51#ibcon#about to read 5, iclass 26, count 0 2006.257.02:08:08.51#ibcon#read 5, iclass 26, count 0 2006.257.02:08:08.51#ibcon#about to read 6, iclass 26, count 0 2006.257.02:08:08.51#ibcon#read 6, iclass 26, count 0 2006.257.02:08:08.51#ibcon#end of sib2, iclass 26, count 0 2006.257.02:08:08.51#ibcon#*mode == 0, iclass 26, count 0 2006.257.02:08:08.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.02:08:08.51#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:08:08.51#ibcon#*before write, iclass 26, count 0 2006.257.02:08:08.51#ibcon#enter sib2, iclass 26, count 0 2006.257.02:08:08.51#ibcon#flushed, iclass 26, count 0 2006.257.02:08:08.51#ibcon#about to write, iclass 26, count 0 2006.257.02:08:08.51#ibcon#wrote, iclass 26, count 0 2006.257.02:08:08.51#ibcon#about to read 3, iclass 26, count 0 2006.257.02:08:08.55#ibcon#read 3, iclass 26, count 0 2006.257.02:08:08.55#ibcon#about to read 4, iclass 26, count 0 2006.257.02:08:08.55#ibcon#read 4, iclass 26, count 0 2006.257.02:08:08.55#ibcon#about to read 5, iclass 26, count 0 2006.257.02:08:08.55#ibcon#read 5, iclass 26, count 0 2006.257.02:08:08.55#ibcon#about to read 6, iclass 26, count 0 2006.257.02:08:08.55#ibcon#read 6, iclass 26, count 0 2006.257.02:08:08.55#ibcon#end of sib2, iclass 26, count 0 2006.257.02:08:08.55#ibcon#*after write, iclass 26, count 0 2006.257.02:08:08.55#ibcon#*before return 0, iclass 26, count 0 2006.257.02:08:08.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:08:08.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:08:08.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.02:08:08.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.02:08:08.55$vck44/vb=1,4 2006.257.02:08:08.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.02:08:08.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.02:08:08.55#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:08.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:08:08.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:08:08.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:08:08.55#ibcon#enter wrdev, iclass 28, count 2 2006.257.02:08:08.55#ibcon#first serial, iclass 28, count 2 2006.257.02:08:08.55#ibcon#enter sib2, iclass 28, count 2 2006.257.02:08:08.55#ibcon#flushed, iclass 28, count 2 2006.257.02:08:08.55#ibcon#about to write, iclass 28, count 2 2006.257.02:08:08.55#ibcon#wrote, iclass 28, count 2 2006.257.02:08:08.55#ibcon#about to read 3, iclass 28, count 2 2006.257.02:08:08.57#ibcon#read 3, iclass 28, count 2 2006.257.02:08:08.57#ibcon#about to read 4, iclass 28, count 2 2006.257.02:08:08.57#ibcon#read 4, iclass 28, count 2 2006.257.02:08:08.57#ibcon#about to read 5, iclass 28, count 2 2006.257.02:08:08.57#ibcon#read 5, iclass 28, count 2 2006.257.02:08:08.57#ibcon#about to read 6, iclass 28, count 2 2006.257.02:08:08.57#ibcon#read 6, iclass 28, count 2 2006.257.02:08:08.57#ibcon#end of sib2, iclass 28, count 2 2006.257.02:08:08.57#ibcon#*mode == 0, iclass 28, count 2 2006.257.02:08:08.57#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.02:08:08.57#ibcon#[27=AT01-04\r\n] 2006.257.02:08:08.57#ibcon#*before write, iclass 28, count 2 2006.257.02:08:08.57#ibcon#enter sib2, iclass 28, count 2 2006.257.02:08:08.57#ibcon#flushed, iclass 28, count 2 2006.257.02:08:08.57#ibcon#about to write, iclass 28, count 2 2006.257.02:08:08.57#ibcon#wrote, iclass 28, count 2 2006.257.02:08:08.57#ibcon#about to read 3, iclass 28, count 2 2006.257.02:08:08.60#ibcon#read 3, iclass 28, count 2 2006.257.02:08:08.60#ibcon#about to read 4, iclass 28, count 2 2006.257.02:08:08.60#ibcon#read 4, iclass 28, count 2 2006.257.02:08:08.60#ibcon#about to read 5, iclass 28, count 2 2006.257.02:08:08.60#ibcon#read 5, iclass 28, count 2 2006.257.02:08:08.60#ibcon#about to read 6, iclass 28, count 2 2006.257.02:08:08.60#ibcon#read 6, iclass 28, count 2 2006.257.02:08:08.60#ibcon#end of sib2, iclass 28, count 2 2006.257.02:08:08.60#ibcon#*after write, iclass 28, count 2 2006.257.02:08:08.60#ibcon#*before return 0, iclass 28, count 2 2006.257.02:08:08.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:08:08.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:08:08.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.02:08:08.60#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:08.60#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:08:08.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:08:08.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:08:08.72#ibcon#enter wrdev, iclass 28, count 0 2006.257.02:08:08.72#ibcon#first serial, iclass 28, count 0 2006.257.02:08:08.72#ibcon#enter sib2, iclass 28, count 0 2006.257.02:08:08.72#ibcon#flushed, iclass 28, count 0 2006.257.02:08:08.72#ibcon#about to write, iclass 28, count 0 2006.257.02:08:08.72#ibcon#wrote, iclass 28, count 0 2006.257.02:08:08.72#ibcon#about to read 3, iclass 28, count 0 2006.257.02:08:08.74#ibcon#read 3, iclass 28, count 0 2006.257.02:08:08.74#ibcon#about to read 4, iclass 28, count 0 2006.257.02:08:08.74#ibcon#read 4, iclass 28, count 0 2006.257.02:08:08.74#ibcon#about to read 5, iclass 28, count 0 2006.257.02:08:08.74#ibcon#read 5, iclass 28, count 0 2006.257.02:08:08.74#ibcon#about to read 6, iclass 28, count 0 2006.257.02:08:08.74#ibcon#read 6, iclass 28, count 0 2006.257.02:08:08.74#ibcon#end of sib2, iclass 28, count 0 2006.257.02:08:08.74#ibcon#*mode == 0, iclass 28, count 0 2006.257.02:08:08.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.02:08:08.74#ibcon#[27=USB\r\n] 2006.257.02:08:08.74#ibcon#*before write, iclass 28, count 0 2006.257.02:08:08.74#ibcon#enter sib2, iclass 28, count 0 2006.257.02:08:08.74#ibcon#flushed, iclass 28, count 0 2006.257.02:08:08.74#ibcon#about to write, iclass 28, count 0 2006.257.02:08:08.74#ibcon#wrote, iclass 28, count 0 2006.257.02:08:08.74#ibcon#about to read 3, iclass 28, count 0 2006.257.02:08:08.77#ibcon#read 3, iclass 28, count 0 2006.257.02:08:08.77#ibcon#about to read 4, iclass 28, count 0 2006.257.02:08:08.77#ibcon#read 4, iclass 28, count 0 2006.257.02:08:08.77#ibcon#about to read 5, iclass 28, count 0 2006.257.02:08:08.77#ibcon#read 5, iclass 28, count 0 2006.257.02:08:08.77#ibcon#about to read 6, iclass 28, count 0 2006.257.02:08:08.77#ibcon#read 6, iclass 28, count 0 2006.257.02:08:08.77#ibcon#end of sib2, iclass 28, count 0 2006.257.02:08:08.77#ibcon#*after write, iclass 28, count 0 2006.257.02:08:08.77#ibcon#*before return 0, iclass 28, count 0 2006.257.02:08:08.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:08:08.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:08:08.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.02:08:08.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.02:08:08.77$vck44/vblo=2,634.99 2006.257.02:08:08.77#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.02:08:08.77#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.02:08:08.77#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:08.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:08.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:08.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:08.77#ibcon#enter wrdev, iclass 30, count 0 2006.257.02:08:08.77#ibcon#first serial, iclass 30, count 0 2006.257.02:08:08.77#ibcon#enter sib2, iclass 30, count 0 2006.257.02:08:08.77#ibcon#flushed, iclass 30, count 0 2006.257.02:08:08.77#ibcon#about to write, iclass 30, count 0 2006.257.02:08:08.77#ibcon#wrote, iclass 30, count 0 2006.257.02:08:08.77#ibcon#about to read 3, iclass 30, count 0 2006.257.02:08:08.79#ibcon#read 3, iclass 30, count 0 2006.257.02:08:08.79#ibcon#about to read 4, iclass 30, count 0 2006.257.02:08:08.79#ibcon#read 4, iclass 30, count 0 2006.257.02:08:08.79#ibcon#about to read 5, iclass 30, count 0 2006.257.02:08:08.79#ibcon#read 5, iclass 30, count 0 2006.257.02:08:08.79#ibcon#about to read 6, iclass 30, count 0 2006.257.02:08:08.79#ibcon#read 6, iclass 30, count 0 2006.257.02:08:08.79#ibcon#end of sib2, iclass 30, count 0 2006.257.02:08:08.79#ibcon#*mode == 0, iclass 30, count 0 2006.257.02:08:08.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.02:08:08.79#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:08:08.79#ibcon#*before write, iclass 30, count 0 2006.257.02:08:08.79#ibcon#enter sib2, iclass 30, count 0 2006.257.02:08:08.79#ibcon#flushed, iclass 30, count 0 2006.257.02:08:08.79#ibcon#about to write, iclass 30, count 0 2006.257.02:08:08.79#ibcon#wrote, iclass 30, count 0 2006.257.02:08:08.79#ibcon#about to read 3, iclass 30, count 0 2006.257.02:08:08.83#ibcon#read 3, iclass 30, count 0 2006.257.02:08:08.83#ibcon#about to read 4, iclass 30, count 0 2006.257.02:08:08.83#ibcon#read 4, iclass 30, count 0 2006.257.02:08:08.83#ibcon#about to read 5, iclass 30, count 0 2006.257.02:08:08.83#ibcon#read 5, iclass 30, count 0 2006.257.02:08:08.83#ibcon#about to read 6, iclass 30, count 0 2006.257.02:08:08.83#ibcon#read 6, iclass 30, count 0 2006.257.02:08:08.83#ibcon#end of sib2, iclass 30, count 0 2006.257.02:08:08.83#ibcon#*after write, iclass 30, count 0 2006.257.02:08:08.83#ibcon#*before return 0, iclass 30, count 0 2006.257.02:08:08.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:08.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:08:08.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.02:08:08.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.02:08:08.83$vck44/vb=2,5 2006.257.02:08:08.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.02:08:08.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.02:08:08.83#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:08.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:08.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:08.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:08.89#ibcon#enter wrdev, iclass 32, count 2 2006.257.02:08:08.89#ibcon#first serial, iclass 32, count 2 2006.257.02:08:08.89#ibcon#enter sib2, iclass 32, count 2 2006.257.02:08:08.89#ibcon#flushed, iclass 32, count 2 2006.257.02:08:08.89#ibcon#about to write, iclass 32, count 2 2006.257.02:08:08.89#ibcon#wrote, iclass 32, count 2 2006.257.02:08:08.89#ibcon#about to read 3, iclass 32, count 2 2006.257.02:08:08.91#ibcon#read 3, iclass 32, count 2 2006.257.02:08:08.91#ibcon#about to read 4, iclass 32, count 2 2006.257.02:08:08.91#ibcon#read 4, iclass 32, count 2 2006.257.02:08:08.91#ibcon#about to read 5, iclass 32, count 2 2006.257.02:08:08.91#ibcon#read 5, iclass 32, count 2 2006.257.02:08:08.91#ibcon#about to read 6, iclass 32, count 2 2006.257.02:08:08.91#ibcon#read 6, iclass 32, count 2 2006.257.02:08:08.91#ibcon#end of sib2, iclass 32, count 2 2006.257.02:08:08.91#ibcon#*mode == 0, iclass 32, count 2 2006.257.02:08:08.91#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.02:08:08.91#ibcon#[27=AT02-05\r\n] 2006.257.02:08:08.91#ibcon#*before write, iclass 32, count 2 2006.257.02:08:08.91#ibcon#enter sib2, iclass 32, count 2 2006.257.02:08:08.91#ibcon#flushed, iclass 32, count 2 2006.257.02:08:08.91#ibcon#about to write, iclass 32, count 2 2006.257.02:08:08.91#ibcon#wrote, iclass 32, count 2 2006.257.02:08:08.91#ibcon#about to read 3, iclass 32, count 2 2006.257.02:08:08.94#ibcon#read 3, iclass 32, count 2 2006.257.02:08:08.94#ibcon#about to read 4, iclass 32, count 2 2006.257.02:08:08.94#ibcon#read 4, iclass 32, count 2 2006.257.02:08:08.94#ibcon#about to read 5, iclass 32, count 2 2006.257.02:08:08.94#ibcon#read 5, iclass 32, count 2 2006.257.02:08:08.94#ibcon#about to read 6, iclass 32, count 2 2006.257.02:08:08.94#ibcon#read 6, iclass 32, count 2 2006.257.02:08:08.94#ibcon#end of sib2, iclass 32, count 2 2006.257.02:08:08.94#ibcon#*after write, iclass 32, count 2 2006.257.02:08:08.94#ibcon#*before return 0, iclass 32, count 2 2006.257.02:08:08.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:08.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:08:08.94#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.02:08:08.94#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:08.94#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:09.06#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:09.06#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:09.06#ibcon#enter wrdev, iclass 32, count 0 2006.257.02:08:09.06#ibcon#first serial, iclass 32, count 0 2006.257.02:08:09.06#ibcon#enter sib2, iclass 32, count 0 2006.257.02:08:09.06#ibcon#flushed, iclass 32, count 0 2006.257.02:08:09.06#ibcon#about to write, iclass 32, count 0 2006.257.02:08:09.06#ibcon#wrote, iclass 32, count 0 2006.257.02:08:09.06#ibcon#about to read 3, iclass 32, count 0 2006.257.02:08:09.08#ibcon#read 3, iclass 32, count 0 2006.257.02:08:09.08#ibcon#about to read 4, iclass 32, count 0 2006.257.02:08:09.08#ibcon#read 4, iclass 32, count 0 2006.257.02:08:09.08#ibcon#about to read 5, iclass 32, count 0 2006.257.02:08:09.08#ibcon#read 5, iclass 32, count 0 2006.257.02:08:09.08#ibcon#about to read 6, iclass 32, count 0 2006.257.02:08:09.08#ibcon#read 6, iclass 32, count 0 2006.257.02:08:09.08#ibcon#end of sib2, iclass 32, count 0 2006.257.02:08:09.08#ibcon#*mode == 0, iclass 32, count 0 2006.257.02:08:09.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.02:08:09.08#ibcon#[27=USB\r\n] 2006.257.02:08:09.08#ibcon#*before write, iclass 32, count 0 2006.257.02:08:09.08#ibcon#enter sib2, iclass 32, count 0 2006.257.02:08:09.08#ibcon#flushed, iclass 32, count 0 2006.257.02:08:09.08#ibcon#about to write, iclass 32, count 0 2006.257.02:08:09.08#ibcon#wrote, iclass 32, count 0 2006.257.02:08:09.08#ibcon#about to read 3, iclass 32, count 0 2006.257.02:08:09.11#ibcon#read 3, iclass 32, count 0 2006.257.02:08:09.11#ibcon#about to read 4, iclass 32, count 0 2006.257.02:08:09.11#ibcon#read 4, iclass 32, count 0 2006.257.02:08:09.11#ibcon#about to read 5, iclass 32, count 0 2006.257.02:08:09.11#ibcon#read 5, iclass 32, count 0 2006.257.02:08:09.11#ibcon#about to read 6, iclass 32, count 0 2006.257.02:08:09.11#ibcon#read 6, iclass 32, count 0 2006.257.02:08:09.11#ibcon#end of sib2, iclass 32, count 0 2006.257.02:08:09.11#ibcon#*after write, iclass 32, count 0 2006.257.02:08:09.11#ibcon#*before return 0, iclass 32, count 0 2006.257.02:08:09.11#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:09.11#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:08:09.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.02:08:09.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.02:08:09.11$vck44/vblo=3,649.99 2006.257.02:08:09.11#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.02:08:09.11#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.02:08:09.11#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:09.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:09.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:09.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:09.11#ibcon#enter wrdev, iclass 34, count 0 2006.257.02:08:09.11#ibcon#first serial, iclass 34, count 0 2006.257.02:08:09.11#ibcon#enter sib2, iclass 34, count 0 2006.257.02:08:09.11#ibcon#flushed, iclass 34, count 0 2006.257.02:08:09.11#ibcon#about to write, iclass 34, count 0 2006.257.02:08:09.11#ibcon#wrote, iclass 34, count 0 2006.257.02:08:09.11#ibcon#about to read 3, iclass 34, count 0 2006.257.02:08:09.13#ibcon#read 3, iclass 34, count 0 2006.257.02:08:09.13#ibcon#about to read 4, iclass 34, count 0 2006.257.02:08:09.13#ibcon#read 4, iclass 34, count 0 2006.257.02:08:09.13#ibcon#about to read 5, iclass 34, count 0 2006.257.02:08:09.13#ibcon#read 5, iclass 34, count 0 2006.257.02:08:09.13#ibcon#about to read 6, iclass 34, count 0 2006.257.02:08:09.13#ibcon#read 6, iclass 34, count 0 2006.257.02:08:09.13#ibcon#end of sib2, iclass 34, count 0 2006.257.02:08:09.13#ibcon#*mode == 0, iclass 34, count 0 2006.257.02:08:09.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.02:08:09.13#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:08:09.13#ibcon#*before write, iclass 34, count 0 2006.257.02:08:09.13#ibcon#enter sib2, iclass 34, count 0 2006.257.02:08:09.13#ibcon#flushed, iclass 34, count 0 2006.257.02:08:09.13#ibcon#about to write, iclass 34, count 0 2006.257.02:08:09.13#ibcon#wrote, iclass 34, count 0 2006.257.02:08:09.13#ibcon#about to read 3, iclass 34, count 0 2006.257.02:08:09.17#ibcon#read 3, iclass 34, count 0 2006.257.02:08:09.17#ibcon#about to read 4, iclass 34, count 0 2006.257.02:08:09.17#ibcon#read 4, iclass 34, count 0 2006.257.02:08:09.17#ibcon#about to read 5, iclass 34, count 0 2006.257.02:08:09.17#ibcon#read 5, iclass 34, count 0 2006.257.02:08:09.17#ibcon#about to read 6, iclass 34, count 0 2006.257.02:08:09.17#ibcon#read 6, iclass 34, count 0 2006.257.02:08:09.17#ibcon#end of sib2, iclass 34, count 0 2006.257.02:08:09.17#ibcon#*after write, iclass 34, count 0 2006.257.02:08:09.17#ibcon#*before return 0, iclass 34, count 0 2006.257.02:08:09.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:09.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:08:09.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.02:08:09.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.02:08:09.17$vck44/vb=3,4 2006.257.02:08:09.17#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.02:08:09.17#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.02:08:09.17#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:09.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:09.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:09.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:09.23#ibcon#enter wrdev, iclass 36, count 2 2006.257.02:08:09.23#ibcon#first serial, iclass 36, count 2 2006.257.02:08:09.23#ibcon#enter sib2, iclass 36, count 2 2006.257.02:08:09.23#ibcon#flushed, iclass 36, count 2 2006.257.02:08:09.23#ibcon#about to write, iclass 36, count 2 2006.257.02:08:09.23#ibcon#wrote, iclass 36, count 2 2006.257.02:08:09.23#ibcon#about to read 3, iclass 36, count 2 2006.257.02:08:09.25#ibcon#read 3, iclass 36, count 2 2006.257.02:08:09.25#ibcon#about to read 4, iclass 36, count 2 2006.257.02:08:09.25#ibcon#read 4, iclass 36, count 2 2006.257.02:08:09.25#ibcon#about to read 5, iclass 36, count 2 2006.257.02:08:09.25#ibcon#read 5, iclass 36, count 2 2006.257.02:08:09.25#ibcon#about to read 6, iclass 36, count 2 2006.257.02:08:09.25#ibcon#read 6, iclass 36, count 2 2006.257.02:08:09.25#ibcon#end of sib2, iclass 36, count 2 2006.257.02:08:09.25#ibcon#*mode == 0, iclass 36, count 2 2006.257.02:08:09.25#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.02:08:09.25#ibcon#[27=AT03-04\r\n] 2006.257.02:08:09.25#ibcon#*before write, iclass 36, count 2 2006.257.02:08:09.25#ibcon#enter sib2, iclass 36, count 2 2006.257.02:08:09.25#ibcon#flushed, iclass 36, count 2 2006.257.02:08:09.25#ibcon#about to write, iclass 36, count 2 2006.257.02:08:09.25#ibcon#wrote, iclass 36, count 2 2006.257.02:08:09.25#ibcon#about to read 3, iclass 36, count 2 2006.257.02:08:09.28#ibcon#read 3, iclass 36, count 2 2006.257.02:08:09.28#ibcon#about to read 4, iclass 36, count 2 2006.257.02:08:09.28#ibcon#read 4, iclass 36, count 2 2006.257.02:08:09.28#ibcon#about to read 5, iclass 36, count 2 2006.257.02:08:09.28#ibcon#read 5, iclass 36, count 2 2006.257.02:08:09.28#ibcon#about to read 6, iclass 36, count 2 2006.257.02:08:09.28#ibcon#read 6, iclass 36, count 2 2006.257.02:08:09.28#ibcon#end of sib2, iclass 36, count 2 2006.257.02:08:09.28#ibcon#*after write, iclass 36, count 2 2006.257.02:08:09.28#ibcon#*before return 0, iclass 36, count 2 2006.257.02:08:09.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:09.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:08:09.28#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.02:08:09.28#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:09.28#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:09.40#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:09.40#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:09.40#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:08:09.40#ibcon#first serial, iclass 36, count 0 2006.257.02:08:09.40#ibcon#enter sib2, iclass 36, count 0 2006.257.02:08:09.40#ibcon#flushed, iclass 36, count 0 2006.257.02:08:09.40#ibcon#about to write, iclass 36, count 0 2006.257.02:08:09.40#ibcon#wrote, iclass 36, count 0 2006.257.02:08:09.40#ibcon#about to read 3, iclass 36, count 0 2006.257.02:08:09.42#ibcon#read 3, iclass 36, count 0 2006.257.02:08:09.42#ibcon#about to read 4, iclass 36, count 0 2006.257.02:08:09.42#ibcon#read 4, iclass 36, count 0 2006.257.02:08:09.42#ibcon#about to read 5, iclass 36, count 0 2006.257.02:08:09.42#ibcon#read 5, iclass 36, count 0 2006.257.02:08:09.42#ibcon#about to read 6, iclass 36, count 0 2006.257.02:08:09.42#ibcon#read 6, iclass 36, count 0 2006.257.02:08:09.42#ibcon#end of sib2, iclass 36, count 0 2006.257.02:08:09.42#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:08:09.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:08:09.42#ibcon#[27=USB\r\n] 2006.257.02:08:09.42#ibcon#*before write, iclass 36, count 0 2006.257.02:08:09.42#ibcon#enter sib2, iclass 36, count 0 2006.257.02:08:09.42#ibcon#flushed, iclass 36, count 0 2006.257.02:08:09.42#ibcon#about to write, iclass 36, count 0 2006.257.02:08:09.42#ibcon#wrote, iclass 36, count 0 2006.257.02:08:09.42#ibcon#about to read 3, iclass 36, count 0 2006.257.02:08:09.45#ibcon#read 3, iclass 36, count 0 2006.257.02:08:09.45#ibcon#about to read 4, iclass 36, count 0 2006.257.02:08:09.45#ibcon#read 4, iclass 36, count 0 2006.257.02:08:09.45#ibcon#about to read 5, iclass 36, count 0 2006.257.02:08:09.45#ibcon#read 5, iclass 36, count 0 2006.257.02:08:09.45#ibcon#about to read 6, iclass 36, count 0 2006.257.02:08:09.45#ibcon#read 6, iclass 36, count 0 2006.257.02:08:09.45#ibcon#end of sib2, iclass 36, count 0 2006.257.02:08:09.45#ibcon#*after write, iclass 36, count 0 2006.257.02:08:09.45#ibcon#*before return 0, iclass 36, count 0 2006.257.02:08:09.45#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:09.45#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:08:09.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:08:09.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:08:09.45$vck44/vblo=4,679.99 2006.257.02:08:09.45#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.02:08:09.45#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.02:08:09.45#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:09.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:09.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:09.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:09.45#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:08:09.45#ibcon#first serial, iclass 38, count 0 2006.257.02:08:09.45#ibcon#enter sib2, iclass 38, count 0 2006.257.02:08:09.45#ibcon#flushed, iclass 38, count 0 2006.257.02:08:09.45#ibcon#about to write, iclass 38, count 0 2006.257.02:08:09.45#ibcon#wrote, iclass 38, count 0 2006.257.02:08:09.45#ibcon#about to read 3, iclass 38, count 0 2006.257.02:08:09.47#ibcon#read 3, iclass 38, count 0 2006.257.02:08:09.47#ibcon#about to read 4, iclass 38, count 0 2006.257.02:08:09.47#ibcon#read 4, iclass 38, count 0 2006.257.02:08:09.47#ibcon#about to read 5, iclass 38, count 0 2006.257.02:08:09.47#ibcon#read 5, iclass 38, count 0 2006.257.02:08:09.47#ibcon#about to read 6, iclass 38, count 0 2006.257.02:08:09.47#ibcon#read 6, iclass 38, count 0 2006.257.02:08:09.47#ibcon#end of sib2, iclass 38, count 0 2006.257.02:08:09.47#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:08:09.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:08:09.47#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:08:09.47#ibcon#*before write, iclass 38, count 0 2006.257.02:08:09.47#ibcon#enter sib2, iclass 38, count 0 2006.257.02:08:09.47#ibcon#flushed, iclass 38, count 0 2006.257.02:08:09.47#ibcon#about to write, iclass 38, count 0 2006.257.02:08:09.47#ibcon#wrote, iclass 38, count 0 2006.257.02:08:09.47#ibcon#about to read 3, iclass 38, count 0 2006.257.02:08:09.51#ibcon#read 3, iclass 38, count 0 2006.257.02:08:09.51#ibcon#about to read 4, iclass 38, count 0 2006.257.02:08:09.51#ibcon#read 4, iclass 38, count 0 2006.257.02:08:09.51#ibcon#about to read 5, iclass 38, count 0 2006.257.02:08:09.51#ibcon#read 5, iclass 38, count 0 2006.257.02:08:09.51#ibcon#about to read 6, iclass 38, count 0 2006.257.02:08:09.51#ibcon#read 6, iclass 38, count 0 2006.257.02:08:09.51#ibcon#end of sib2, iclass 38, count 0 2006.257.02:08:09.51#ibcon#*after write, iclass 38, count 0 2006.257.02:08:09.51#ibcon#*before return 0, iclass 38, count 0 2006.257.02:08:09.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:09.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:08:09.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:08:09.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:08:09.51$vck44/vb=4,5 2006.257.02:08:09.51#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.02:08:09.51#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.02:08:09.51#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:09.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:09.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:09.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:09.57#ibcon#enter wrdev, iclass 40, count 2 2006.257.02:08:09.57#ibcon#first serial, iclass 40, count 2 2006.257.02:08:09.57#ibcon#enter sib2, iclass 40, count 2 2006.257.02:08:09.57#ibcon#flushed, iclass 40, count 2 2006.257.02:08:09.57#ibcon#about to write, iclass 40, count 2 2006.257.02:08:09.57#ibcon#wrote, iclass 40, count 2 2006.257.02:08:09.57#ibcon#about to read 3, iclass 40, count 2 2006.257.02:08:09.59#ibcon#read 3, iclass 40, count 2 2006.257.02:08:09.59#ibcon#about to read 4, iclass 40, count 2 2006.257.02:08:09.59#ibcon#read 4, iclass 40, count 2 2006.257.02:08:09.59#ibcon#about to read 5, iclass 40, count 2 2006.257.02:08:09.59#ibcon#read 5, iclass 40, count 2 2006.257.02:08:09.59#ibcon#about to read 6, iclass 40, count 2 2006.257.02:08:09.59#ibcon#read 6, iclass 40, count 2 2006.257.02:08:09.59#ibcon#end of sib2, iclass 40, count 2 2006.257.02:08:09.59#ibcon#*mode == 0, iclass 40, count 2 2006.257.02:08:09.59#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.02:08:09.59#ibcon#[27=AT04-05\r\n] 2006.257.02:08:09.59#ibcon#*before write, iclass 40, count 2 2006.257.02:08:09.59#ibcon#enter sib2, iclass 40, count 2 2006.257.02:08:09.59#ibcon#flushed, iclass 40, count 2 2006.257.02:08:09.59#ibcon#about to write, iclass 40, count 2 2006.257.02:08:09.59#ibcon#wrote, iclass 40, count 2 2006.257.02:08:09.59#ibcon#about to read 3, iclass 40, count 2 2006.257.02:08:09.62#ibcon#read 3, iclass 40, count 2 2006.257.02:08:09.62#ibcon#about to read 4, iclass 40, count 2 2006.257.02:08:09.62#ibcon#read 4, iclass 40, count 2 2006.257.02:08:09.62#ibcon#about to read 5, iclass 40, count 2 2006.257.02:08:09.62#ibcon#read 5, iclass 40, count 2 2006.257.02:08:09.62#ibcon#about to read 6, iclass 40, count 2 2006.257.02:08:09.62#ibcon#read 6, iclass 40, count 2 2006.257.02:08:09.62#ibcon#end of sib2, iclass 40, count 2 2006.257.02:08:09.62#ibcon#*after write, iclass 40, count 2 2006.257.02:08:09.62#ibcon#*before return 0, iclass 40, count 2 2006.257.02:08:09.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:09.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:08:09.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.02:08:09.62#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:09.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:09.74#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:09.74#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:09.74#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:08:09.74#ibcon#first serial, iclass 40, count 0 2006.257.02:08:09.74#ibcon#enter sib2, iclass 40, count 0 2006.257.02:08:09.74#ibcon#flushed, iclass 40, count 0 2006.257.02:08:09.74#ibcon#about to write, iclass 40, count 0 2006.257.02:08:09.74#ibcon#wrote, iclass 40, count 0 2006.257.02:08:09.74#ibcon#about to read 3, iclass 40, count 0 2006.257.02:08:09.76#ibcon#read 3, iclass 40, count 0 2006.257.02:08:09.76#ibcon#about to read 4, iclass 40, count 0 2006.257.02:08:09.76#ibcon#read 4, iclass 40, count 0 2006.257.02:08:09.76#ibcon#about to read 5, iclass 40, count 0 2006.257.02:08:09.76#ibcon#read 5, iclass 40, count 0 2006.257.02:08:09.76#ibcon#about to read 6, iclass 40, count 0 2006.257.02:08:09.76#ibcon#read 6, iclass 40, count 0 2006.257.02:08:09.76#ibcon#end of sib2, iclass 40, count 0 2006.257.02:08:09.76#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:08:09.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:08:09.76#ibcon#[27=USB\r\n] 2006.257.02:08:09.76#ibcon#*before write, iclass 40, count 0 2006.257.02:08:09.76#ibcon#enter sib2, iclass 40, count 0 2006.257.02:08:09.76#ibcon#flushed, iclass 40, count 0 2006.257.02:08:09.76#ibcon#about to write, iclass 40, count 0 2006.257.02:08:09.76#ibcon#wrote, iclass 40, count 0 2006.257.02:08:09.76#ibcon#about to read 3, iclass 40, count 0 2006.257.02:08:09.79#ibcon#read 3, iclass 40, count 0 2006.257.02:08:09.79#ibcon#about to read 4, iclass 40, count 0 2006.257.02:08:09.79#ibcon#read 4, iclass 40, count 0 2006.257.02:08:09.79#ibcon#about to read 5, iclass 40, count 0 2006.257.02:08:09.79#ibcon#read 5, iclass 40, count 0 2006.257.02:08:09.79#ibcon#about to read 6, iclass 40, count 0 2006.257.02:08:09.79#ibcon#read 6, iclass 40, count 0 2006.257.02:08:09.79#ibcon#end of sib2, iclass 40, count 0 2006.257.02:08:09.79#ibcon#*after write, iclass 40, count 0 2006.257.02:08:09.79#ibcon#*before return 0, iclass 40, count 0 2006.257.02:08:09.79#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:09.79#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:08:09.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:08:09.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:08:09.79$vck44/vblo=5,709.99 2006.257.02:08:09.79#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.02:08:09.79#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.02:08:09.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:09.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:09.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:09.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:09.79#ibcon#enter wrdev, iclass 4, count 0 2006.257.02:08:09.79#ibcon#first serial, iclass 4, count 0 2006.257.02:08:09.79#ibcon#enter sib2, iclass 4, count 0 2006.257.02:08:09.79#ibcon#flushed, iclass 4, count 0 2006.257.02:08:09.79#ibcon#about to write, iclass 4, count 0 2006.257.02:08:09.79#ibcon#wrote, iclass 4, count 0 2006.257.02:08:09.79#ibcon#about to read 3, iclass 4, count 0 2006.257.02:08:09.81#ibcon#read 3, iclass 4, count 0 2006.257.02:08:09.81#ibcon#about to read 4, iclass 4, count 0 2006.257.02:08:09.81#ibcon#read 4, iclass 4, count 0 2006.257.02:08:09.81#ibcon#about to read 5, iclass 4, count 0 2006.257.02:08:09.81#ibcon#read 5, iclass 4, count 0 2006.257.02:08:09.81#ibcon#about to read 6, iclass 4, count 0 2006.257.02:08:09.81#ibcon#read 6, iclass 4, count 0 2006.257.02:08:09.81#ibcon#end of sib2, iclass 4, count 0 2006.257.02:08:09.81#ibcon#*mode == 0, iclass 4, count 0 2006.257.02:08:09.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.02:08:09.81#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:08:09.81#ibcon#*before write, iclass 4, count 0 2006.257.02:08:09.81#ibcon#enter sib2, iclass 4, count 0 2006.257.02:08:09.81#ibcon#flushed, iclass 4, count 0 2006.257.02:08:09.81#ibcon#about to write, iclass 4, count 0 2006.257.02:08:09.81#ibcon#wrote, iclass 4, count 0 2006.257.02:08:09.81#ibcon#about to read 3, iclass 4, count 0 2006.257.02:08:09.85#ibcon#read 3, iclass 4, count 0 2006.257.02:08:09.85#ibcon#about to read 4, iclass 4, count 0 2006.257.02:08:09.85#ibcon#read 4, iclass 4, count 0 2006.257.02:08:09.85#ibcon#about to read 5, iclass 4, count 0 2006.257.02:08:09.85#ibcon#read 5, iclass 4, count 0 2006.257.02:08:09.85#ibcon#about to read 6, iclass 4, count 0 2006.257.02:08:09.85#ibcon#read 6, iclass 4, count 0 2006.257.02:08:09.85#ibcon#end of sib2, iclass 4, count 0 2006.257.02:08:09.85#ibcon#*after write, iclass 4, count 0 2006.257.02:08:09.85#ibcon#*before return 0, iclass 4, count 0 2006.257.02:08:09.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:09.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:08:09.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.02:08:09.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.02:08:09.85$vck44/vb=5,4 2006.257.02:08:09.85#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.02:08:09.85#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.02:08:09.85#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:09.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:09.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:09.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:09.91#ibcon#enter wrdev, iclass 6, count 2 2006.257.02:08:09.91#ibcon#first serial, iclass 6, count 2 2006.257.02:08:09.91#ibcon#enter sib2, iclass 6, count 2 2006.257.02:08:09.91#ibcon#flushed, iclass 6, count 2 2006.257.02:08:09.91#ibcon#about to write, iclass 6, count 2 2006.257.02:08:09.91#ibcon#wrote, iclass 6, count 2 2006.257.02:08:09.91#ibcon#about to read 3, iclass 6, count 2 2006.257.02:08:09.93#ibcon#read 3, iclass 6, count 2 2006.257.02:08:09.93#ibcon#about to read 4, iclass 6, count 2 2006.257.02:08:09.93#ibcon#read 4, iclass 6, count 2 2006.257.02:08:09.93#ibcon#about to read 5, iclass 6, count 2 2006.257.02:08:09.93#ibcon#read 5, iclass 6, count 2 2006.257.02:08:09.93#ibcon#about to read 6, iclass 6, count 2 2006.257.02:08:09.93#ibcon#read 6, iclass 6, count 2 2006.257.02:08:09.93#ibcon#end of sib2, iclass 6, count 2 2006.257.02:08:09.93#ibcon#*mode == 0, iclass 6, count 2 2006.257.02:08:09.93#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.02:08:09.93#ibcon#[27=AT05-04\r\n] 2006.257.02:08:09.93#ibcon#*before write, iclass 6, count 2 2006.257.02:08:09.93#ibcon#enter sib2, iclass 6, count 2 2006.257.02:08:09.93#ibcon#flushed, iclass 6, count 2 2006.257.02:08:09.93#ibcon#about to write, iclass 6, count 2 2006.257.02:08:09.93#ibcon#wrote, iclass 6, count 2 2006.257.02:08:09.93#ibcon#about to read 3, iclass 6, count 2 2006.257.02:08:09.96#ibcon#read 3, iclass 6, count 2 2006.257.02:08:09.96#ibcon#about to read 4, iclass 6, count 2 2006.257.02:08:09.96#ibcon#read 4, iclass 6, count 2 2006.257.02:08:09.96#ibcon#about to read 5, iclass 6, count 2 2006.257.02:08:09.96#ibcon#read 5, iclass 6, count 2 2006.257.02:08:09.96#ibcon#about to read 6, iclass 6, count 2 2006.257.02:08:09.96#ibcon#read 6, iclass 6, count 2 2006.257.02:08:09.96#ibcon#end of sib2, iclass 6, count 2 2006.257.02:08:09.96#ibcon#*after write, iclass 6, count 2 2006.257.02:08:09.96#ibcon#*before return 0, iclass 6, count 2 2006.257.02:08:09.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:09.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:08:09.96#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.02:08:09.96#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:09.96#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:10.08#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:10.08#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:10.08#ibcon#enter wrdev, iclass 6, count 0 2006.257.02:08:10.08#ibcon#first serial, iclass 6, count 0 2006.257.02:08:10.08#ibcon#enter sib2, iclass 6, count 0 2006.257.02:08:10.08#ibcon#flushed, iclass 6, count 0 2006.257.02:08:10.08#ibcon#about to write, iclass 6, count 0 2006.257.02:08:10.08#ibcon#wrote, iclass 6, count 0 2006.257.02:08:10.08#ibcon#about to read 3, iclass 6, count 0 2006.257.02:08:10.10#ibcon#read 3, iclass 6, count 0 2006.257.02:08:10.10#ibcon#about to read 4, iclass 6, count 0 2006.257.02:08:10.10#ibcon#read 4, iclass 6, count 0 2006.257.02:08:10.10#ibcon#about to read 5, iclass 6, count 0 2006.257.02:08:10.10#ibcon#read 5, iclass 6, count 0 2006.257.02:08:10.10#ibcon#about to read 6, iclass 6, count 0 2006.257.02:08:10.10#ibcon#read 6, iclass 6, count 0 2006.257.02:08:10.10#ibcon#end of sib2, iclass 6, count 0 2006.257.02:08:10.10#ibcon#*mode == 0, iclass 6, count 0 2006.257.02:08:10.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.02:08:10.10#ibcon#[27=USB\r\n] 2006.257.02:08:10.10#ibcon#*before write, iclass 6, count 0 2006.257.02:08:10.10#ibcon#enter sib2, iclass 6, count 0 2006.257.02:08:10.10#ibcon#flushed, iclass 6, count 0 2006.257.02:08:10.10#ibcon#about to write, iclass 6, count 0 2006.257.02:08:10.10#ibcon#wrote, iclass 6, count 0 2006.257.02:08:10.10#ibcon#about to read 3, iclass 6, count 0 2006.257.02:08:10.13#ibcon#read 3, iclass 6, count 0 2006.257.02:08:10.13#ibcon#about to read 4, iclass 6, count 0 2006.257.02:08:10.13#ibcon#read 4, iclass 6, count 0 2006.257.02:08:10.13#ibcon#about to read 5, iclass 6, count 0 2006.257.02:08:10.13#ibcon#read 5, iclass 6, count 0 2006.257.02:08:10.13#ibcon#about to read 6, iclass 6, count 0 2006.257.02:08:10.13#ibcon#read 6, iclass 6, count 0 2006.257.02:08:10.13#ibcon#end of sib2, iclass 6, count 0 2006.257.02:08:10.13#ibcon#*after write, iclass 6, count 0 2006.257.02:08:10.13#ibcon#*before return 0, iclass 6, count 0 2006.257.02:08:10.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:10.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:08:10.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.02:08:10.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.02:08:10.13$vck44/vblo=6,719.99 2006.257.02:08:10.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.02:08:10.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.02:08:10.13#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:10.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:10.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:10.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:10.13#ibcon#enter wrdev, iclass 10, count 0 2006.257.02:08:10.13#ibcon#first serial, iclass 10, count 0 2006.257.02:08:10.13#ibcon#enter sib2, iclass 10, count 0 2006.257.02:08:10.13#ibcon#flushed, iclass 10, count 0 2006.257.02:08:10.13#ibcon#about to write, iclass 10, count 0 2006.257.02:08:10.13#ibcon#wrote, iclass 10, count 0 2006.257.02:08:10.13#ibcon#about to read 3, iclass 10, count 0 2006.257.02:08:10.15#ibcon#read 3, iclass 10, count 0 2006.257.02:08:10.15#ibcon#about to read 4, iclass 10, count 0 2006.257.02:08:10.15#ibcon#read 4, iclass 10, count 0 2006.257.02:08:10.15#ibcon#about to read 5, iclass 10, count 0 2006.257.02:08:10.15#ibcon#read 5, iclass 10, count 0 2006.257.02:08:10.15#ibcon#about to read 6, iclass 10, count 0 2006.257.02:08:10.15#ibcon#read 6, iclass 10, count 0 2006.257.02:08:10.15#ibcon#end of sib2, iclass 10, count 0 2006.257.02:08:10.15#ibcon#*mode == 0, iclass 10, count 0 2006.257.02:08:10.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.02:08:10.15#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:08:10.15#ibcon#*before write, iclass 10, count 0 2006.257.02:08:10.15#ibcon#enter sib2, iclass 10, count 0 2006.257.02:08:10.15#ibcon#flushed, iclass 10, count 0 2006.257.02:08:10.15#ibcon#about to write, iclass 10, count 0 2006.257.02:08:10.15#ibcon#wrote, iclass 10, count 0 2006.257.02:08:10.15#ibcon#about to read 3, iclass 10, count 0 2006.257.02:08:10.19#ibcon#read 3, iclass 10, count 0 2006.257.02:08:10.19#ibcon#about to read 4, iclass 10, count 0 2006.257.02:08:10.19#ibcon#read 4, iclass 10, count 0 2006.257.02:08:10.19#ibcon#about to read 5, iclass 10, count 0 2006.257.02:08:10.19#ibcon#read 5, iclass 10, count 0 2006.257.02:08:10.19#ibcon#about to read 6, iclass 10, count 0 2006.257.02:08:10.19#ibcon#read 6, iclass 10, count 0 2006.257.02:08:10.19#ibcon#end of sib2, iclass 10, count 0 2006.257.02:08:10.19#ibcon#*after write, iclass 10, count 0 2006.257.02:08:10.19#ibcon#*before return 0, iclass 10, count 0 2006.257.02:08:10.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:10.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:08:10.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.02:08:10.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.02:08:10.19$vck44/vb=6,4 2006.257.02:08:10.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.02:08:10.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.02:08:10.19#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:10.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:10.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:10.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:10.25#ibcon#enter wrdev, iclass 12, count 2 2006.257.02:08:10.25#ibcon#first serial, iclass 12, count 2 2006.257.02:08:10.25#ibcon#enter sib2, iclass 12, count 2 2006.257.02:08:10.25#ibcon#flushed, iclass 12, count 2 2006.257.02:08:10.25#ibcon#about to write, iclass 12, count 2 2006.257.02:08:10.25#ibcon#wrote, iclass 12, count 2 2006.257.02:08:10.25#ibcon#about to read 3, iclass 12, count 2 2006.257.02:08:10.27#ibcon#read 3, iclass 12, count 2 2006.257.02:08:10.27#ibcon#about to read 4, iclass 12, count 2 2006.257.02:08:10.27#ibcon#read 4, iclass 12, count 2 2006.257.02:08:10.27#ibcon#about to read 5, iclass 12, count 2 2006.257.02:08:10.27#ibcon#read 5, iclass 12, count 2 2006.257.02:08:10.27#ibcon#about to read 6, iclass 12, count 2 2006.257.02:08:10.27#ibcon#read 6, iclass 12, count 2 2006.257.02:08:10.27#ibcon#end of sib2, iclass 12, count 2 2006.257.02:08:10.27#ibcon#*mode == 0, iclass 12, count 2 2006.257.02:08:10.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.02:08:10.27#ibcon#[27=AT06-04\r\n] 2006.257.02:08:10.27#ibcon#*before write, iclass 12, count 2 2006.257.02:08:10.27#ibcon#enter sib2, iclass 12, count 2 2006.257.02:08:10.27#ibcon#flushed, iclass 12, count 2 2006.257.02:08:10.27#ibcon#about to write, iclass 12, count 2 2006.257.02:08:10.27#ibcon#wrote, iclass 12, count 2 2006.257.02:08:10.27#ibcon#about to read 3, iclass 12, count 2 2006.257.02:08:10.30#ibcon#read 3, iclass 12, count 2 2006.257.02:08:10.30#ibcon#about to read 4, iclass 12, count 2 2006.257.02:08:10.30#ibcon#read 4, iclass 12, count 2 2006.257.02:08:10.30#ibcon#about to read 5, iclass 12, count 2 2006.257.02:08:10.30#ibcon#read 5, iclass 12, count 2 2006.257.02:08:10.30#ibcon#about to read 6, iclass 12, count 2 2006.257.02:08:10.30#ibcon#read 6, iclass 12, count 2 2006.257.02:08:10.30#ibcon#end of sib2, iclass 12, count 2 2006.257.02:08:10.30#ibcon#*after write, iclass 12, count 2 2006.257.02:08:10.30#ibcon#*before return 0, iclass 12, count 2 2006.257.02:08:10.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:10.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:08:10.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.02:08:10.30#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:10.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:10.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:10.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:10.42#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:08:10.42#ibcon#first serial, iclass 12, count 0 2006.257.02:08:10.42#ibcon#enter sib2, iclass 12, count 0 2006.257.02:08:10.42#ibcon#flushed, iclass 12, count 0 2006.257.02:08:10.42#ibcon#about to write, iclass 12, count 0 2006.257.02:08:10.42#ibcon#wrote, iclass 12, count 0 2006.257.02:08:10.42#ibcon#about to read 3, iclass 12, count 0 2006.257.02:08:10.44#ibcon#read 3, iclass 12, count 0 2006.257.02:08:10.44#ibcon#about to read 4, iclass 12, count 0 2006.257.02:08:10.44#ibcon#read 4, iclass 12, count 0 2006.257.02:08:10.44#ibcon#about to read 5, iclass 12, count 0 2006.257.02:08:10.44#ibcon#read 5, iclass 12, count 0 2006.257.02:08:10.44#ibcon#about to read 6, iclass 12, count 0 2006.257.02:08:10.44#ibcon#read 6, iclass 12, count 0 2006.257.02:08:10.44#ibcon#end of sib2, iclass 12, count 0 2006.257.02:08:10.44#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:08:10.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:08:10.44#ibcon#[27=USB\r\n] 2006.257.02:08:10.44#ibcon#*before write, iclass 12, count 0 2006.257.02:08:10.44#ibcon#enter sib2, iclass 12, count 0 2006.257.02:08:10.44#ibcon#flushed, iclass 12, count 0 2006.257.02:08:10.44#ibcon#about to write, iclass 12, count 0 2006.257.02:08:10.44#ibcon#wrote, iclass 12, count 0 2006.257.02:08:10.44#ibcon#about to read 3, iclass 12, count 0 2006.257.02:08:10.47#ibcon#read 3, iclass 12, count 0 2006.257.02:08:10.47#ibcon#about to read 4, iclass 12, count 0 2006.257.02:08:10.47#ibcon#read 4, iclass 12, count 0 2006.257.02:08:10.47#ibcon#about to read 5, iclass 12, count 0 2006.257.02:08:10.47#ibcon#read 5, iclass 12, count 0 2006.257.02:08:10.47#ibcon#about to read 6, iclass 12, count 0 2006.257.02:08:10.47#ibcon#read 6, iclass 12, count 0 2006.257.02:08:10.47#ibcon#end of sib2, iclass 12, count 0 2006.257.02:08:10.47#ibcon#*after write, iclass 12, count 0 2006.257.02:08:10.47#ibcon#*before return 0, iclass 12, count 0 2006.257.02:08:10.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:10.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:08:10.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:08:10.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:08:10.47$vck44/vblo=7,734.99 2006.257.02:08:10.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.02:08:10.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.02:08:10.47#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:10.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:10.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:10.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:10.47#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:08:10.47#ibcon#first serial, iclass 14, count 0 2006.257.02:08:10.47#ibcon#enter sib2, iclass 14, count 0 2006.257.02:08:10.47#ibcon#flushed, iclass 14, count 0 2006.257.02:08:10.47#ibcon#about to write, iclass 14, count 0 2006.257.02:08:10.47#ibcon#wrote, iclass 14, count 0 2006.257.02:08:10.47#ibcon#about to read 3, iclass 14, count 0 2006.257.02:08:10.49#ibcon#read 3, iclass 14, count 0 2006.257.02:08:10.49#ibcon#about to read 4, iclass 14, count 0 2006.257.02:08:10.49#ibcon#read 4, iclass 14, count 0 2006.257.02:08:10.49#ibcon#about to read 5, iclass 14, count 0 2006.257.02:08:10.49#ibcon#read 5, iclass 14, count 0 2006.257.02:08:10.49#ibcon#about to read 6, iclass 14, count 0 2006.257.02:08:10.49#ibcon#read 6, iclass 14, count 0 2006.257.02:08:10.49#ibcon#end of sib2, iclass 14, count 0 2006.257.02:08:10.49#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:08:10.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:08:10.49#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:08:10.49#ibcon#*before write, iclass 14, count 0 2006.257.02:08:10.49#ibcon#enter sib2, iclass 14, count 0 2006.257.02:08:10.49#ibcon#flushed, iclass 14, count 0 2006.257.02:08:10.49#ibcon#about to write, iclass 14, count 0 2006.257.02:08:10.49#ibcon#wrote, iclass 14, count 0 2006.257.02:08:10.49#ibcon#about to read 3, iclass 14, count 0 2006.257.02:08:10.53#ibcon#read 3, iclass 14, count 0 2006.257.02:08:10.53#ibcon#about to read 4, iclass 14, count 0 2006.257.02:08:10.53#ibcon#read 4, iclass 14, count 0 2006.257.02:08:10.53#ibcon#about to read 5, iclass 14, count 0 2006.257.02:08:10.53#ibcon#read 5, iclass 14, count 0 2006.257.02:08:10.53#ibcon#about to read 6, iclass 14, count 0 2006.257.02:08:10.53#ibcon#read 6, iclass 14, count 0 2006.257.02:08:10.53#ibcon#end of sib2, iclass 14, count 0 2006.257.02:08:10.53#ibcon#*after write, iclass 14, count 0 2006.257.02:08:10.53#ibcon#*before return 0, iclass 14, count 0 2006.257.02:08:10.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:10.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:08:10.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:08:10.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:08:10.53$vck44/vb=7,4 2006.257.02:08:10.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.02:08:10.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.02:08:10.53#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:10.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:10.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:10.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:10.59#ibcon#enter wrdev, iclass 16, count 2 2006.257.02:08:10.59#ibcon#first serial, iclass 16, count 2 2006.257.02:08:10.59#ibcon#enter sib2, iclass 16, count 2 2006.257.02:08:10.59#ibcon#flushed, iclass 16, count 2 2006.257.02:08:10.59#ibcon#about to write, iclass 16, count 2 2006.257.02:08:10.59#ibcon#wrote, iclass 16, count 2 2006.257.02:08:10.59#ibcon#about to read 3, iclass 16, count 2 2006.257.02:08:10.61#ibcon#read 3, iclass 16, count 2 2006.257.02:08:10.61#ibcon#about to read 4, iclass 16, count 2 2006.257.02:08:10.61#ibcon#read 4, iclass 16, count 2 2006.257.02:08:10.61#ibcon#about to read 5, iclass 16, count 2 2006.257.02:08:10.61#ibcon#read 5, iclass 16, count 2 2006.257.02:08:10.61#ibcon#about to read 6, iclass 16, count 2 2006.257.02:08:10.61#ibcon#read 6, iclass 16, count 2 2006.257.02:08:10.61#ibcon#end of sib2, iclass 16, count 2 2006.257.02:08:10.61#ibcon#*mode == 0, iclass 16, count 2 2006.257.02:08:10.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.02:08:10.61#ibcon#[27=AT07-04\r\n] 2006.257.02:08:10.61#ibcon#*before write, iclass 16, count 2 2006.257.02:08:10.61#ibcon#enter sib2, iclass 16, count 2 2006.257.02:08:10.61#ibcon#flushed, iclass 16, count 2 2006.257.02:08:10.61#ibcon#about to write, iclass 16, count 2 2006.257.02:08:10.61#ibcon#wrote, iclass 16, count 2 2006.257.02:08:10.61#ibcon#about to read 3, iclass 16, count 2 2006.257.02:08:10.64#ibcon#read 3, iclass 16, count 2 2006.257.02:08:10.64#ibcon#about to read 4, iclass 16, count 2 2006.257.02:08:10.64#ibcon#read 4, iclass 16, count 2 2006.257.02:08:10.64#ibcon#about to read 5, iclass 16, count 2 2006.257.02:08:10.64#ibcon#read 5, iclass 16, count 2 2006.257.02:08:10.64#ibcon#about to read 6, iclass 16, count 2 2006.257.02:08:10.64#ibcon#read 6, iclass 16, count 2 2006.257.02:08:10.64#ibcon#end of sib2, iclass 16, count 2 2006.257.02:08:10.64#ibcon#*after write, iclass 16, count 2 2006.257.02:08:10.64#ibcon#*before return 0, iclass 16, count 2 2006.257.02:08:10.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:10.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:08:10.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.02:08:10.64#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:10.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:10.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:10.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:10.76#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:08:10.76#ibcon#first serial, iclass 16, count 0 2006.257.02:08:10.76#ibcon#enter sib2, iclass 16, count 0 2006.257.02:08:10.76#ibcon#flushed, iclass 16, count 0 2006.257.02:08:10.76#ibcon#about to write, iclass 16, count 0 2006.257.02:08:10.76#ibcon#wrote, iclass 16, count 0 2006.257.02:08:10.76#ibcon#about to read 3, iclass 16, count 0 2006.257.02:08:10.78#ibcon#read 3, iclass 16, count 0 2006.257.02:08:10.78#ibcon#about to read 4, iclass 16, count 0 2006.257.02:08:10.78#ibcon#read 4, iclass 16, count 0 2006.257.02:08:10.78#ibcon#about to read 5, iclass 16, count 0 2006.257.02:08:10.78#ibcon#read 5, iclass 16, count 0 2006.257.02:08:10.78#ibcon#about to read 6, iclass 16, count 0 2006.257.02:08:10.78#ibcon#read 6, iclass 16, count 0 2006.257.02:08:10.78#ibcon#end of sib2, iclass 16, count 0 2006.257.02:08:10.78#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:08:10.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:08:10.78#ibcon#[27=USB\r\n] 2006.257.02:08:10.78#ibcon#*before write, iclass 16, count 0 2006.257.02:08:10.78#ibcon#enter sib2, iclass 16, count 0 2006.257.02:08:10.78#ibcon#flushed, iclass 16, count 0 2006.257.02:08:10.78#ibcon#about to write, iclass 16, count 0 2006.257.02:08:10.78#ibcon#wrote, iclass 16, count 0 2006.257.02:08:10.78#ibcon#about to read 3, iclass 16, count 0 2006.257.02:08:10.81#ibcon#read 3, iclass 16, count 0 2006.257.02:08:10.81#ibcon#about to read 4, iclass 16, count 0 2006.257.02:08:10.81#ibcon#read 4, iclass 16, count 0 2006.257.02:08:10.81#ibcon#about to read 5, iclass 16, count 0 2006.257.02:08:10.81#ibcon#read 5, iclass 16, count 0 2006.257.02:08:10.81#ibcon#about to read 6, iclass 16, count 0 2006.257.02:08:10.81#ibcon#read 6, iclass 16, count 0 2006.257.02:08:10.81#ibcon#end of sib2, iclass 16, count 0 2006.257.02:08:10.81#ibcon#*after write, iclass 16, count 0 2006.257.02:08:10.81#ibcon#*before return 0, iclass 16, count 0 2006.257.02:08:10.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:10.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:08:10.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:08:10.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:08:10.81$vck44/vblo=8,744.99 2006.257.02:08:10.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.02:08:10.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.02:08:10.81#ibcon#ireg 17 cls_cnt 0 2006.257.02:08:10.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:10.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:10.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:10.81#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:08:10.81#ibcon#first serial, iclass 18, count 0 2006.257.02:08:10.81#ibcon#enter sib2, iclass 18, count 0 2006.257.02:08:10.81#ibcon#flushed, iclass 18, count 0 2006.257.02:08:10.81#ibcon#about to write, iclass 18, count 0 2006.257.02:08:10.81#ibcon#wrote, iclass 18, count 0 2006.257.02:08:10.81#ibcon#about to read 3, iclass 18, count 0 2006.257.02:08:10.83#ibcon#read 3, iclass 18, count 0 2006.257.02:08:10.83#ibcon#about to read 4, iclass 18, count 0 2006.257.02:08:10.83#ibcon#read 4, iclass 18, count 0 2006.257.02:08:10.83#ibcon#about to read 5, iclass 18, count 0 2006.257.02:08:10.83#ibcon#read 5, iclass 18, count 0 2006.257.02:08:10.83#ibcon#about to read 6, iclass 18, count 0 2006.257.02:08:10.83#ibcon#read 6, iclass 18, count 0 2006.257.02:08:10.83#ibcon#end of sib2, iclass 18, count 0 2006.257.02:08:10.83#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:08:10.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:08:10.83#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:08:10.83#ibcon#*before write, iclass 18, count 0 2006.257.02:08:10.83#ibcon#enter sib2, iclass 18, count 0 2006.257.02:08:10.83#ibcon#flushed, iclass 18, count 0 2006.257.02:08:10.83#ibcon#about to write, iclass 18, count 0 2006.257.02:08:10.83#ibcon#wrote, iclass 18, count 0 2006.257.02:08:10.83#ibcon#about to read 3, iclass 18, count 0 2006.257.02:08:10.87#ibcon#read 3, iclass 18, count 0 2006.257.02:08:10.87#ibcon#about to read 4, iclass 18, count 0 2006.257.02:08:10.87#ibcon#read 4, iclass 18, count 0 2006.257.02:08:10.87#ibcon#about to read 5, iclass 18, count 0 2006.257.02:08:10.87#ibcon#read 5, iclass 18, count 0 2006.257.02:08:10.87#ibcon#about to read 6, iclass 18, count 0 2006.257.02:08:10.87#ibcon#read 6, iclass 18, count 0 2006.257.02:08:10.87#ibcon#end of sib2, iclass 18, count 0 2006.257.02:08:10.87#ibcon#*after write, iclass 18, count 0 2006.257.02:08:10.87#ibcon#*before return 0, iclass 18, count 0 2006.257.02:08:10.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:10.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:08:10.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:08:10.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:08:10.87$vck44/vb=8,4 2006.257.02:08:10.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.02:08:10.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.02:08:10.87#ibcon#ireg 11 cls_cnt 2 2006.257.02:08:10.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:10.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:10.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:10.93#ibcon#enter wrdev, iclass 20, count 2 2006.257.02:08:10.93#ibcon#first serial, iclass 20, count 2 2006.257.02:08:10.93#ibcon#enter sib2, iclass 20, count 2 2006.257.02:08:10.93#ibcon#flushed, iclass 20, count 2 2006.257.02:08:10.93#ibcon#about to write, iclass 20, count 2 2006.257.02:08:10.93#ibcon#wrote, iclass 20, count 2 2006.257.02:08:10.93#ibcon#about to read 3, iclass 20, count 2 2006.257.02:08:10.95#ibcon#read 3, iclass 20, count 2 2006.257.02:08:10.95#ibcon#about to read 4, iclass 20, count 2 2006.257.02:08:10.95#ibcon#read 4, iclass 20, count 2 2006.257.02:08:10.95#ibcon#about to read 5, iclass 20, count 2 2006.257.02:08:10.95#ibcon#read 5, iclass 20, count 2 2006.257.02:08:10.95#ibcon#about to read 6, iclass 20, count 2 2006.257.02:08:10.95#ibcon#read 6, iclass 20, count 2 2006.257.02:08:10.95#ibcon#end of sib2, iclass 20, count 2 2006.257.02:08:10.95#ibcon#*mode == 0, iclass 20, count 2 2006.257.02:08:10.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.02:08:10.95#ibcon#[27=AT08-04\r\n] 2006.257.02:08:10.95#ibcon#*before write, iclass 20, count 2 2006.257.02:08:10.95#ibcon#enter sib2, iclass 20, count 2 2006.257.02:08:10.95#ibcon#flushed, iclass 20, count 2 2006.257.02:08:10.95#ibcon#about to write, iclass 20, count 2 2006.257.02:08:10.95#ibcon#wrote, iclass 20, count 2 2006.257.02:08:10.95#ibcon#about to read 3, iclass 20, count 2 2006.257.02:08:10.98#ibcon#read 3, iclass 20, count 2 2006.257.02:08:10.98#ibcon#about to read 4, iclass 20, count 2 2006.257.02:08:10.98#ibcon#read 4, iclass 20, count 2 2006.257.02:08:10.98#ibcon#about to read 5, iclass 20, count 2 2006.257.02:08:10.98#ibcon#read 5, iclass 20, count 2 2006.257.02:08:10.98#ibcon#about to read 6, iclass 20, count 2 2006.257.02:08:10.98#ibcon#read 6, iclass 20, count 2 2006.257.02:08:10.98#ibcon#end of sib2, iclass 20, count 2 2006.257.02:08:10.98#ibcon#*after write, iclass 20, count 2 2006.257.02:08:10.98#ibcon#*before return 0, iclass 20, count 2 2006.257.02:08:10.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:10.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:08:10.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.02:08:10.98#ibcon#ireg 7 cls_cnt 0 2006.257.02:08:10.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:11.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:11.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:11.10#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:08:11.10#ibcon#first serial, iclass 20, count 0 2006.257.02:08:11.10#ibcon#enter sib2, iclass 20, count 0 2006.257.02:08:11.10#ibcon#flushed, iclass 20, count 0 2006.257.02:08:11.10#ibcon#about to write, iclass 20, count 0 2006.257.02:08:11.10#ibcon#wrote, iclass 20, count 0 2006.257.02:08:11.10#ibcon#about to read 3, iclass 20, count 0 2006.257.02:08:11.12#ibcon#read 3, iclass 20, count 0 2006.257.02:08:11.12#ibcon#about to read 4, iclass 20, count 0 2006.257.02:08:11.12#ibcon#read 4, iclass 20, count 0 2006.257.02:08:11.12#ibcon#about to read 5, iclass 20, count 0 2006.257.02:08:11.12#ibcon#read 5, iclass 20, count 0 2006.257.02:08:11.12#ibcon#about to read 6, iclass 20, count 0 2006.257.02:08:11.12#ibcon#read 6, iclass 20, count 0 2006.257.02:08:11.12#ibcon#end of sib2, iclass 20, count 0 2006.257.02:08:11.12#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:08:11.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:08:11.12#ibcon#[27=USB\r\n] 2006.257.02:08:11.12#ibcon#*before write, iclass 20, count 0 2006.257.02:08:11.12#ibcon#enter sib2, iclass 20, count 0 2006.257.02:08:11.12#ibcon#flushed, iclass 20, count 0 2006.257.02:08:11.12#ibcon#about to write, iclass 20, count 0 2006.257.02:08:11.12#ibcon#wrote, iclass 20, count 0 2006.257.02:08:11.12#ibcon#about to read 3, iclass 20, count 0 2006.257.02:08:11.15#ibcon#read 3, iclass 20, count 0 2006.257.02:08:11.15#ibcon#about to read 4, iclass 20, count 0 2006.257.02:08:11.15#ibcon#read 4, iclass 20, count 0 2006.257.02:08:11.15#ibcon#about to read 5, iclass 20, count 0 2006.257.02:08:11.15#ibcon#read 5, iclass 20, count 0 2006.257.02:08:11.15#ibcon#about to read 6, iclass 20, count 0 2006.257.02:08:11.15#ibcon#read 6, iclass 20, count 0 2006.257.02:08:11.15#ibcon#end of sib2, iclass 20, count 0 2006.257.02:08:11.15#ibcon#*after write, iclass 20, count 0 2006.257.02:08:11.15#ibcon#*before return 0, iclass 20, count 0 2006.257.02:08:11.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:11.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:08:11.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:08:11.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:08:11.15$vck44/vabw=wide 2006.257.02:08:11.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.02:08:11.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.02:08:11.15#ibcon#ireg 8 cls_cnt 0 2006.257.02:08:11.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:11.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:11.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:11.15#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:08:11.15#ibcon#first serial, iclass 22, count 0 2006.257.02:08:11.15#ibcon#enter sib2, iclass 22, count 0 2006.257.02:08:11.15#ibcon#flushed, iclass 22, count 0 2006.257.02:08:11.15#ibcon#about to write, iclass 22, count 0 2006.257.02:08:11.15#ibcon#wrote, iclass 22, count 0 2006.257.02:08:11.15#ibcon#about to read 3, iclass 22, count 0 2006.257.02:08:11.17#ibcon#read 3, iclass 22, count 0 2006.257.02:08:11.17#ibcon#about to read 4, iclass 22, count 0 2006.257.02:08:11.17#ibcon#read 4, iclass 22, count 0 2006.257.02:08:11.17#ibcon#about to read 5, iclass 22, count 0 2006.257.02:08:11.17#ibcon#read 5, iclass 22, count 0 2006.257.02:08:11.17#ibcon#about to read 6, iclass 22, count 0 2006.257.02:08:11.17#ibcon#read 6, iclass 22, count 0 2006.257.02:08:11.17#ibcon#end of sib2, iclass 22, count 0 2006.257.02:08:11.17#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:08:11.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:08:11.17#ibcon#[25=BW32\r\n] 2006.257.02:08:11.17#ibcon#*before write, iclass 22, count 0 2006.257.02:08:11.17#ibcon#enter sib2, iclass 22, count 0 2006.257.02:08:11.17#ibcon#flushed, iclass 22, count 0 2006.257.02:08:11.17#ibcon#about to write, iclass 22, count 0 2006.257.02:08:11.17#ibcon#wrote, iclass 22, count 0 2006.257.02:08:11.17#ibcon#about to read 3, iclass 22, count 0 2006.257.02:08:11.20#ibcon#read 3, iclass 22, count 0 2006.257.02:08:11.20#ibcon#about to read 4, iclass 22, count 0 2006.257.02:08:11.20#ibcon#read 4, iclass 22, count 0 2006.257.02:08:11.20#ibcon#about to read 5, iclass 22, count 0 2006.257.02:08:11.20#ibcon#read 5, iclass 22, count 0 2006.257.02:08:11.20#ibcon#about to read 6, iclass 22, count 0 2006.257.02:08:11.20#ibcon#read 6, iclass 22, count 0 2006.257.02:08:11.20#ibcon#end of sib2, iclass 22, count 0 2006.257.02:08:11.20#ibcon#*after write, iclass 22, count 0 2006.257.02:08:11.20#ibcon#*before return 0, iclass 22, count 0 2006.257.02:08:11.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:11.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:08:11.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:08:11.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:08:11.20$vck44/vbbw=wide 2006.257.02:08:11.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.02:08:11.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.02:08:11.20#ibcon#ireg 8 cls_cnt 0 2006.257.02:08:11.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:08:11.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:08:11.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:08:11.28#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:08:11.28#ibcon#first serial, iclass 24, count 0 2006.257.02:08:11.28#ibcon#enter sib2, iclass 24, count 0 2006.257.02:08:11.28#ibcon#flushed, iclass 24, count 0 2006.257.02:08:11.28#ibcon#about to write, iclass 24, count 0 2006.257.02:08:11.28#ibcon#wrote, iclass 24, count 0 2006.257.02:08:11.28#ibcon#about to read 3, iclass 24, count 0 2006.257.02:08:11.29#ibcon#read 3, iclass 24, count 0 2006.257.02:08:11.29#ibcon#about to read 4, iclass 24, count 0 2006.257.02:08:11.29#ibcon#read 4, iclass 24, count 0 2006.257.02:08:11.29#ibcon#about to read 5, iclass 24, count 0 2006.257.02:08:11.29#ibcon#read 5, iclass 24, count 0 2006.257.02:08:11.29#ibcon#about to read 6, iclass 24, count 0 2006.257.02:08:11.29#ibcon#read 6, iclass 24, count 0 2006.257.02:08:11.29#ibcon#end of sib2, iclass 24, count 0 2006.257.02:08:11.29#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:08:11.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:08:11.29#ibcon#[27=BW32\r\n] 2006.257.02:08:11.29#ibcon#*before write, iclass 24, count 0 2006.257.02:08:11.29#ibcon#enter sib2, iclass 24, count 0 2006.257.02:08:11.29#ibcon#flushed, iclass 24, count 0 2006.257.02:08:11.29#ibcon#about to write, iclass 24, count 0 2006.257.02:08:11.29#ibcon#wrote, iclass 24, count 0 2006.257.02:08:11.29#ibcon#about to read 3, iclass 24, count 0 2006.257.02:08:11.32#ibcon#read 3, iclass 24, count 0 2006.257.02:08:11.32#ibcon#about to read 4, iclass 24, count 0 2006.257.02:08:11.32#ibcon#read 4, iclass 24, count 0 2006.257.02:08:11.32#ibcon#about to read 5, iclass 24, count 0 2006.257.02:08:11.32#ibcon#read 5, iclass 24, count 0 2006.257.02:08:11.32#ibcon#about to read 6, iclass 24, count 0 2006.257.02:08:11.32#ibcon#read 6, iclass 24, count 0 2006.257.02:08:11.32#ibcon#end of sib2, iclass 24, count 0 2006.257.02:08:11.32#ibcon#*after write, iclass 24, count 0 2006.257.02:08:11.32#ibcon#*before return 0, iclass 24, count 0 2006.257.02:08:11.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:08:11.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:08:11.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:08:11.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:08:11.32$setupk4/ifdk4 2006.257.02:08:11.32$ifdk4/lo= 2006.257.02:08:11.32$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:08:11.32$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:08:11.32$ifdk4/patch= 2006.257.02:08:11.32$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:08:11.32$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:08:11.32$setupk4/!*+20s 2006.257.02:08:14.10#abcon#<5=/03 3.7 9.2 17.80 991011.9\r\n> 2006.257.02:08:14.12#abcon#{5=INTERFACE CLEAR} 2006.257.02:08:14.18#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:08:24.27#abcon#<5=/03 3.6 9.2 17.80 981011.9\r\n> 2006.257.02:08:24.29#abcon#{5=INTERFACE CLEAR} 2006.257.02:08:24.35#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:08:25.80$setupk4/"tpicd 2006.257.02:08:25.80$setupk4/echo=off 2006.257.02:08:25.80$setupk4/xlog=off 2006.257.02:08:25.80:!2006.257.02:11:40 2006.257.02:08:43.14#trakl#Source acquired 2006.257.02:08:43.14#flagr#flagr/antenna,acquired 2006.257.02:11:40.00:preob 2006.257.02:11:41.13/onsource/TRACKING 2006.257.02:11:41.13:!2006.257.02:11:50 2006.257.02:11:50.00:"tape 2006.257.02:11:50.00:"st=record 2006.257.02:11:50.00:data_valid=on 2006.257.02:11:50.00:midob 2006.257.02:11:50.13/onsource/TRACKING 2006.257.02:11:50.13/wx/17.77,1012.0,98 2006.257.02:11:50.33/cable/+6.4867E-03 2006.257.02:11:51.42/va/01,08,usb,yes,34,37 2006.257.02:11:51.42/va/02,07,usb,yes,37,38 2006.257.02:11:51.42/va/03,08,usb,yes,33,35 2006.257.02:11:51.42/va/04,07,usb,yes,38,40 2006.257.02:11:51.42/va/05,04,usb,yes,34,35 2006.257.02:11:51.42/va/06,04,usb,yes,38,38 2006.257.02:11:51.42/va/07,04,usb,yes,39,40 2006.257.02:11:51.42/va/08,04,usb,yes,33,40 2006.257.02:11:51.65/valo/01,524.99,yes,locked 2006.257.02:11:51.65/valo/02,534.99,yes,locked 2006.257.02:11:51.65/valo/03,564.99,yes,locked 2006.257.02:11:51.65/valo/04,624.99,yes,locked 2006.257.02:11:51.65/valo/05,734.99,yes,locked 2006.257.02:11:51.65/valo/06,814.99,yes,locked 2006.257.02:11:51.65/valo/07,864.99,yes,locked 2006.257.02:11:51.65/valo/08,884.99,yes,locked 2006.257.02:11:52.74/vb/01,04,usb,yes,32,30 2006.257.02:11:52.74/vb/02,05,usb,yes,30,30 2006.257.02:11:52.74/vb/03,04,usb,yes,31,34 2006.257.02:11:52.74/vb/04,05,usb,yes,31,30 2006.257.02:11:52.74/vb/05,04,usb,yes,28,30 2006.257.02:11:52.74/vb/06,04,usb,yes,33,28 2006.257.02:11:52.74/vb/07,04,usb,yes,32,32 2006.257.02:11:52.74/vb/08,04,usb,yes,30,33 2006.257.02:11:52.98/vblo/01,629.99,yes,locked 2006.257.02:11:52.98/vblo/02,634.99,yes,locked 2006.257.02:11:52.98/vblo/03,649.99,yes,locked 2006.257.02:11:52.98/vblo/04,679.99,yes,locked 2006.257.02:11:52.98/vblo/05,709.99,yes,locked 2006.257.02:11:52.98/vblo/06,719.99,yes,locked 2006.257.02:11:52.98/vblo/07,734.99,yes,locked 2006.257.02:11:52.98/vblo/08,744.99,yes,locked 2006.257.02:11:53.13/vabw/8 2006.257.02:11:53.28/vbbw/8 2006.257.02:11:53.37/xfe/off,on,15.0 2006.257.02:11:53.75/ifatt/23,28,28,28 2006.257.02:11:54.08/fmout-gps/S +4.53E-07 2006.257.02:11:54.12:!2006.257.02:13:00 2006.257.02:13:00.00:data_valid=off 2006.257.02:13:00.00:"et 2006.257.02:13:00.01:!+3s 2006.257.02:13:03.02:"tape 2006.257.02:13:03.02:postob 2006.257.02:13:03.21/cable/+6.4863E-03 2006.257.02:13:03.21/wx/17.76,1012.0,98 2006.257.02:13:04.08/fmout-gps/S +4.55E-07 2006.257.02:13:04.08:scan_name=257-0216,jd0609,50 2006.257.02:13:04.09:source=0059+581,010245.76,582411.1,2000.0,cw 2006.257.02:13:05.14#flagr#flagr/antenna,new-source 2006.257.02:13:05.14:checkk5 2006.257.02:13:05.53/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:13:05.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:13:06.40/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:13:06.81/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:13:07.22/chk_obsdata//k5ts1/T2570211??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.02:13:07.76/chk_obsdata//k5ts2/T2570211??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.02:13:08.14/chk_obsdata//k5ts3/T2570211??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.02:13:08.57/chk_obsdata//k5ts4/T2570211??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.02:13:09.41/k5log//k5ts1_log_newline 2006.257.02:13:10.28/k5log//k5ts2_log_newline 2006.257.02:13:11.09/k5log//k5ts3_log_newline 2006.257.02:13:11.83/k5log//k5ts4_log_newline 2006.257.02:13:11.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:13:11.85:setupk4=1 2006.257.02:13:11.85$setupk4/echo=on 2006.257.02:13:11.85$setupk4/pcalon 2006.257.02:13:11.85$pcalon/"no phase cal control is implemented here 2006.257.02:13:11.85$setupk4/"tpicd=stop 2006.257.02:13:11.85$setupk4/"rec=synch_on 2006.257.02:13:11.85$setupk4/"rec_mode=128 2006.257.02:13:11.85$setupk4/!* 2006.257.02:13:11.85$setupk4/recpk4 2006.257.02:13:11.85$recpk4/recpatch= 2006.257.02:13:11.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:13:11.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:13:11.86$setupk4/vck44 2006.257.02:13:11.86$vck44/valo=1,524.99 2006.257.02:13:11.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.02:13:11.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.02:13:11.86#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:11.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:11.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:11.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:11.86#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:13:11.86#ibcon#first serial, iclass 3, count 0 2006.257.02:13:11.86#ibcon#enter sib2, iclass 3, count 0 2006.257.02:13:11.86#ibcon#flushed, iclass 3, count 0 2006.257.02:13:11.86#ibcon#about to write, iclass 3, count 0 2006.257.02:13:11.86#ibcon#wrote, iclass 3, count 0 2006.257.02:13:11.86#ibcon#about to read 3, iclass 3, count 0 2006.257.02:13:11.92#ibcon#read 3, iclass 3, count 0 2006.257.02:13:11.92#ibcon#about to read 4, iclass 3, count 0 2006.257.02:13:11.92#ibcon#read 4, iclass 3, count 0 2006.257.02:13:11.92#ibcon#about to read 5, iclass 3, count 0 2006.257.02:13:11.92#ibcon#read 5, iclass 3, count 0 2006.257.02:13:11.92#ibcon#about to read 6, iclass 3, count 0 2006.257.02:13:11.92#ibcon#read 6, iclass 3, count 0 2006.257.02:13:11.92#ibcon#end of sib2, iclass 3, count 0 2006.257.02:13:11.92#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:13:11.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:13:11.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:13:11.92#ibcon#*before write, iclass 3, count 0 2006.257.02:13:11.92#ibcon#enter sib2, iclass 3, count 0 2006.257.02:13:11.92#ibcon#flushed, iclass 3, count 0 2006.257.02:13:11.92#ibcon#about to write, iclass 3, count 0 2006.257.02:13:11.92#ibcon#wrote, iclass 3, count 0 2006.257.02:13:11.92#ibcon#about to read 3, iclass 3, count 0 2006.257.02:13:11.97#ibcon#read 3, iclass 3, count 0 2006.257.02:13:11.97#ibcon#about to read 4, iclass 3, count 0 2006.257.02:13:11.97#ibcon#read 4, iclass 3, count 0 2006.257.02:13:11.97#ibcon#about to read 5, iclass 3, count 0 2006.257.02:13:11.97#ibcon#read 5, iclass 3, count 0 2006.257.02:13:11.97#ibcon#about to read 6, iclass 3, count 0 2006.257.02:13:11.97#ibcon#read 6, iclass 3, count 0 2006.257.02:13:11.97#ibcon#end of sib2, iclass 3, count 0 2006.257.02:13:11.97#ibcon#*after write, iclass 3, count 0 2006.257.02:13:11.97#ibcon#*before return 0, iclass 3, count 0 2006.257.02:13:11.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:11.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:11.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:13:11.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:13:11.97$vck44/va=1,8 2006.257.02:13:11.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.02:13:11.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.02:13:11.97#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:11.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:11.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:11.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:11.97#ibcon#enter wrdev, iclass 5, count 2 2006.257.02:13:11.97#ibcon#first serial, iclass 5, count 2 2006.257.02:13:11.97#ibcon#enter sib2, iclass 5, count 2 2006.257.02:13:11.97#ibcon#flushed, iclass 5, count 2 2006.257.02:13:11.97#ibcon#about to write, iclass 5, count 2 2006.257.02:13:11.97#ibcon#wrote, iclass 5, count 2 2006.257.02:13:11.97#ibcon#about to read 3, iclass 5, count 2 2006.257.02:13:11.99#ibcon#read 3, iclass 5, count 2 2006.257.02:13:11.99#ibcon#about to read 4, iclass 5, count 2 2006.257.02:13:11.99#ibcon#read 4, iclass 5, count 2 2006.257.02:13:11.99#ibcon#about to read 5, iclass 5, count 2 2006.257.02:13:11.99#ibcon#read 5, iclass 5, count 2 2006.257.02:13:11.99#ibcon#about to read 6, iclass 5, count 2 2006.257.02:13:11.99#ibcon#read 6, iclass 5, count 2 2006.257.02:13:11.99#ibcon#end of sib2, iclass 5, count 2 2006.257.02:13:11.99#ibcon#*mode == 0, iclass 5, count 2 2006.257.02:13:11.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.02:13:11.99#ibcon#[25=AT01-08\r\n] 2006.257.02:13:11.99#ibcon#*before write, iclass 5, count 2 2006.257.02:13:11.99#ibcon#enter sib2, iclass 5, count 2 2006.257.02:13:11.99#ibcon#flushed, iclass 5, count 2 2006.257.02:13:11.99#ibcon#about to write, iclass 5, count 2 2006.257.02:13:11.99#ibcon#wrote, iclass 5, count 2 2006.257.02:13:11.99#ibcon#about to read 3, iclass 5, count 2 2006.257.02:13:12.02#ibcon#read 3, iclass 5, count 2 2006.257.02:13:12.02#ibcon#about to read 4, iclass 5, count 2 2006.257.02:13:12.02#ibcon#read 4, iclass 5, count 2 2006.257.02:13:12.02#ibcon#about to read 5, iclass 5, count 2 2006.257.02:13:12.02#ibcon#read 5, iclass 5, count 2 2006.257.02:13:12.02#ibcon#about to read 6, iclass 5, count 2 2006.257.02:13:12.02#ibcon#read 6, iclass 5, count 2 2006.257.02:13:12.02#ibcon#end of sib2, iclass 5, count 2 2006.257.02:13:12.02#ibcon#*after write, iclass 5, count 2 2006.257.02:13:12.02#ibcon#*before return 0, iclass 5, count 2 2006.257.02:13:12.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:12.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:12.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.02:13:12.02#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:12.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:12.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:12.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:12.14#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:13:12.14#ibcon#first serial, iclass 5, count 0 2006.257.02:13:12.14#ibcon#enter sib2, iclass 5, count 0 2006.257.02:13:12.14#ibcon#flushed, iclass 5, count 0 2006.257.02:13:12.14#ibcon#about to write, iclass 5, count 0 2006.257.02:13:12.14#ibcon#wrote, iclass 5, count 0 2006.257.02:13:12.14#ibcon#about to read 3, iclass 5, count 0 2006.257.02:13:12.16#ibcon#read 3, iclass 5, count 0 2006.257.02:13:12.16#ibcon#about to read 4, iclass 5, count 0 2006.257.02:13:12.16#ibcon#read 4, iclass 5, count 0 2006.257.02:13:12.16#ibcon#about to read 5, iclass 5, count 0 2006.257.02:13:12.16#ibcon#read 5, iclass 5, count 0 2006.257.02:13:12.16#ibcon#about to read 6, iclass 5, count 0 2006.257.02:13:12.16#ibcon#read 6, iclass 5, count 0 2006.257.02:13:12.16#ibcon#end of sib2, iclass 5, count 0 2006.257.02:13:12.16#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:13:12.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:13:12.16#ibcon#[25=USB\r\n] 2006.257.02:13:12.16#ibcon#*before write, iclass 5, count 0 2006.257.02:13:12.16#ibcon#enter sib2, iclass 5, count 0 2006.257.02:13:12.16#ibcon#flushed, iclass 5, count 0 2006.257.02:13:12.16#ibcon#about to write, iclass 5, count 0 2006.257.02:13:12.16#ibcon#wrote, iclass 5, count 0 2006.257.02:13:12.16#ibcon#about to read 3, iclass 5, count 0 2006.257.02:13:12.19#ibcon#read 3, iclass 5, count 0 2006.257.02:13:12.19#ibcon#about to read 4, iclass 5, count 0 2006.257.02:13:12.19#ibcon#read 4, iclass 5, count 0 2006.257.02:13:12.19#ibcon#about to read 5, iclass 5, count 0 2006.257.02:13:12.19#ibcon#read 5, iclass 5, count 0 2006.257.02:13:12.19#ibcon#about to read 6, iclass 5, count 0 2006.257.02:13:12.19#ibcon#read 6, iclass 5, count 0 2006.257.02:13:12.19#ibcon#end of sib2, iclass 5, count 0 2006.257.02:13:12.19#ibcon#*after write, iclass 5, count 0 2006.257.02:13:12.19#ibcon#*before return 0, iclass 5, count 0 2006.257.02:13:12.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:12.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:12.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:13:12.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:13:12.19$vck44/valo=2,534.99 2006.257.02:13:12.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.02:13:12.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.02:13:12.19#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:12.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:12.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:12.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:12.19#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:13:12.19#ibcon#first serial, iclass 7, count 0 2006.257.02:13:12.19#ibcon#enter sib2, iclass 7, count 0 2006.257.02:13:12.19#ibcon#flushed, iclass 7, count 0 2006.257.02:13:12.19#ibcon#about to write, iclass 7, count 0 2006.257.02:13:12.19#ibcon#wrote, iclass 7, count 0 2006.257.02:13:12.19#ibcon#about to read 3, iclass 7, count 0 2006.257.02:13:12.22#ibcon#read 3, iclass 7, count 0 2006.257.02:13:12.22#ibcon#about to read 4, iclass 7, count 0 2006.257.02:13:12.22#ibcon#read 4, iclass 7, count 0 2006.257.02:13:12.22#ibcon#about to read 5, iclass 7, count 0 2006.257.02:13:12.22#ibcon#read 5, iclass 7, count 0 2006.257.02:13:12.22#ibcon#about to read 6, iclass 7, count 0 2006.257.02:13:12.22#ibcon#read 6, iclass 7, count 0 2006.257.02:13:12.22#ibcon#end of sib2, iclass 7, count 0 2006.257.02:13:12.22#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:13:12.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:13:12.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:13:12.22#ibcon#*before write, iclass 7, count 0 2006.257.02:13:12.22#ibcon#enter sib2, iclass 7, count 0 2006.257.02:13:12.22#ibcon#flushed, iclass 7, count 0 2006.257.02:13:12.22#ibcon#about to write, iclass 7, count 0 2006.257.02:13:12.22#ibcon#wrote, iclass 7, count 0 2006.257.02:13:12.22#ibcon#about to read 3, iclass 7, count 0 2006.257.02:13:12.26#ibcon#read 3, iclass 7, count 0 2006.257.02:13:12.26#ibcon#about to read 4, iclass 7, count 0 2006.257.02:13:12.26#ibcon#read 4, iclass 7, count 0 2006.257.02:13:12.26#ibcon#about to read 5, iclass 7, count 0 2006.257.02:13:12.26#ibcon#read 5, iclass 7, count 0 2006.257.02:13:12.26#ibcon#about to read 6, iclass 7, count 0 2006.257.02:13:12.26#ibcon#read 6, iclass 7, count 0 2006.257.02:13:12.26#ibcon#end of sib2, iclass 7, count 0 2006.257.02:13:12.26#ibcon#*after write, iclass 7, count 0 2006.257.02:13:12.26#ibcon#*before return 0, iclass 7, count 0 2006.257.02:13:12.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:12.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:12.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:13:12.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:13:12.26$vck44/va=2,7 2006.257.02:13:12.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.02:13:12.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.02:13:12.26#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:12.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:12.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:12.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:12.31#ibcon#enter wrdev, iclass 11, count 2 2006.257.02:13:12.31#ibcon#first serial, iclass 11, count 2 2006.257.02:13:12.31#ibcon#enter sib2, iclass 11, count 2 2006.257.02:13:12.31#ibcon#flushed, iclass 11, count 2 2006.257.02:13:12.31#ibcon#about to write, iclass 11, count 2 2006.257.02:13:12.31#ibcon#wrote, iclass 11, count 2 2006.257.02:13:12.31#ibcon#about to read 3, iclass 11, count 2 2006.257.02:13:12.34#ibcon#read 3, iclass 11, count 2 2006.257.02:13:12.34#ibcon#about to read 4, iclass 11, count 2 2006.257.02:13:12.34#ibcon#read 4, iclass 11, count 2 2006.257.02:13:12.34#ibcon#about to read 5, iclass 11, count 2 2006.257.02:13:12.34#ibcon#read 5, iclass 11, count 2 2006.257.02:13:12.34#ibcon#about to read 6, iclass 11, count 2 2006.257.02:13:12.34#ibcon#read 6, iclass 11, count 2 2006.257.02:13:12.34#ibcon#end of sib2, iclass 11, count 2 2006.257.02:13:12.34#ibcon#*mode == 0, iclass 11, count 2 2006.257.02:13:12.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.02:13:12.34#ibcon#[25=AT02-07\r\n] 2006.257.02:13:12.34#ibcon#*before write, iclass 11, count 2 2006.257.02:13:12.34#ibcon#enter sib2, iclass 11, count 2 2006.257.02:13:12.34#ibcon#flushed, iclass 11, count 2 2006.257.02:13:12.34#ibcon#about to write, iclass 11, count 2 2006.257.02:13:12.34#ibcon#wrote, iclass 11, count 2 2006.257.02:13:12.34#ibcon#about to read 3, iclass 11, count 2 2006.257.02:13:12.37#ibcon#read 3, iclass 11, count 2 2006.257.02:13:12.37#ibcon#about to read 4, iclass 11, count 2 2006.257.02:13:12.37#ibcon#read 4, iclass 11, count 2 2006.257.02:13:12.37#ibcon#about to read 5, iclass 11, count 2 2006.257.02:13:12.37#ibcon#read 5, iclass 11, count 2 2006.257.02:13:12.37#ibcon#about to read 6, iclass 11, count 2 2006.257.02:13:12.37#ibcon#read 6, iclass 11, count 2 2006.257.02:13:12.37#ibcon#end of sib2, iclass 11, count 2 2006.257.02:13:12.37#ibcon#*after write, iclass 11, count 2 2006.257.02:13:12.37#ibcon#*before return 0, iclass 11, count 2 2006.257.02:13:12.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:12.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:12.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.02:13:12.37#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:12.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:12.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:12.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:12.49#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:13:12.49#ibcon#first serial, iclass 11, count 0 2006.257.02:13:12.49#ibcon#enter sib2, iclass 11, count 0 2006.257.02:13:12.49#ibcon#flushed, iclass 11, count 0 2006.257.02:13:12.49#ibcon#about to write, iclass 11, count 0 2006.257.02:13:12.49#ibcon#wrote, iclass 11, count 0 2006.257.02:13:12.49#ibcon#about to read 3, iclass 11, count 0 2006.257.02:13:12.51#ibcon#read 3, iclass 11, count 0 2006.257.02:13:12.51#ibcon#about to read 4, iclass 11, count 0 2006.257.02:13:12.51#ibcon#read 4, iclass 11, count 0 2006.257.02:13:12.51#ibcon#about to read 5, iclass 11, count 0 2006.257.02:13:12.51#ibcon#read 5, iclass 11, count 0 2006.257.02:13:12.51#ibcon#about to read 6, iclass 11, count 0 2006.257.02:13:12.51#ibcon#read 6, iclass 11, count 0 2006.257.02:13:12.51#ibcon#end of sib2, iclass 11, count 0 2006.257.02:13:12.51#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:13:12.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:13:12.51#ibcon#[25=USB\r\n] 2006.257.02:13:12.51#ibcon#*before write, iclass 11, count 0 2006.257.02:13:12.51#ibcon#enter sib2, iclass 11, count 0 2006.257.02:13:12.51#ibcon#flushed, iclass 11, count 0 2006.257.02:13:12.51#ibcon#about to write, iclass 11, count 0 2006.257.02:13:12.51#ibcon#wrote, iclass 11, count 0 2006.257.02:13:12.51#ibcon#about to read 3, iclass 11, count 0 2006.257.02:13:12.54#ibcon#read 3, iclass 11, count 0 2006.257.02:13:12.54#ibcon#about to read 4, iclass 11, count 0 2006.257.02:13:12.54#ibcon#read 4, iclass 11, count 0 2006.257.02:13:12.54#ibcon#about to read 5, iclass 11, count 0 2006.257.02:13:12.54#ibcon#read 5, iclass 11, count 0 2006.257.02:13:12.54#ibcon#about to read 6, iclass 11, count 0 2006.257.02:13:12.54#ibcon#read 6, iclass 11, count 0 2006.257.02:13:12.54#ibcon#end of sib2, iclass 11, count 0 2006.257.02:13:12.54#ibcon#*after write, iclass 11, count 0 2006.257.02:13:12.54#ibcon#*before return 0, iclass 11, count 0 2006.257.02:13:12.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:12.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:12.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:13:12.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:13:12.54$vck44/valo=3,564.99 2006.257.02:13:12.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.02:13:12.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.02:13:12.54#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:12.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:12.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:12.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:12.54#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:13:12.54#ibcon#first serial, iclass 13, count 0 2006.257.02:13:12.54#ibcon#enter sib2, iclass 13, count 0 2006.257.02:13:12.54#ibcon#flushed, iclass 13, count 0 2006.257.02:13:12.54#ibcon#about to write, iclass 13, count 0 2006.257.02:13:12.54#ibcon#wrote, iclass 13, count 0 2006.257.02:13:12.54#ibcon#about to read 3, iclass 13, count 0 2006.257.02:13:12.56#ibcon#read 3, iclass 13, count 0 2006.257.02:13:12.56#ibcon#about to read 4, iclass 13, count 0 2006.257.02:13:12.56#ibcon#read 4, iclass 13, count 0 2006.257.02:13:12.56#ibcon#about to read 5, iclass 13, count 0 2006.257.02:13:12.56#ibcon#read 5, iclass 13, count 0 2006.257.02:13:12.56#ibcon#about to read 6, iclass 13, count 0 2006.257.02:13:12.56#ibcon#read 6, iclass 13, count 0 2006.257.02:13:12.56#ibcon#end of sib2, iclass 13, count 0 2006.257.02:13:12.56#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:13:12.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:13:12.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:13:12.56#ibcon#*before write, iclass 13, count 0 2006.257.02:13:12.56#ibcon#enter sib2, iclass 13, count 0 2006.257.02:13:12.56#ibcon#flushed, iclass 13, count 0 2006.257.02:13:12.56#ibcon#about to write, iclass 13, count 0 2006.257.02:13:12.56#ibcon#wrote, iclass 13, count 0 2006.257.02:13:12.56#ibcon#about to read 3, iclass 13, count 0 2006.257.02:13:12.60#ibcon#read 3, iclass 13, count 0 2006.257.02:13:12.60#ibcon#about to read 4, iclass 13, count 0 2006.257.02:13:12.60#ibcon#read 4, iclass 13, count 0 2006.257.02:13:12.60#ibcon#about to read 5, iclass 13, count 0 2006.257.02:13:12.60#ibcon#read 5, iclass 13, count 0 2006.257.02:13:12.60#ibcon#about to read 6, iclass 13, count 0 2006.257.02:13:12.60#ibcon#read 6, iclass 13, count 0 2006.257.02:13:12.60#ibcon#end of sib2, iclass 13, count 0 2006.257.02:13:12.60#ibcon#*after write, iclass 13, count 0 2006.257.02:13:12.60#ibcon#*before return 0, iclass 13, count 0 2006.257.02:13:12.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:12.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:12.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:13:12.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:13:12.60$vck44/va=3,8 2006.257.02:13:12.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.02:13:12.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.02:13:12.60#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:12.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:12.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:12.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:12.67#ibcon#enter wrdev, iclass 15, count 2 2006.257.02:13:12.67#ibcon#first serial, iclass 15, count 2 2006.257.02:13:12.67#ibcon#enter sib2, iclass 15, count 2 2006.257.02:13:12.67#ibcon#flushed, iclass 15, count 2 2006.257.02:13:12.67#ibcon#about to write, iclass 15, count 2 2006.257.02:13:12.67#ibcon#wrote, iclass 15, count 2 2006.257.02:13:12.67#ibcon#about to read 3, iclass 15, count 2 2006.257.02:13:12.68#ibcon#read 3, iclass 15, count 2 2006.257.02:13:12.68#ibcon#about to read 4, iclass 15, count 2 2006.257.02:13:12.68#ibcon#read 4, iclass 15, count 2 2006.257.02:13:12.68#ibcon#about to read 5, iclass 15, count 2 2006.257.02:13:12.68#ibcon#read 5, iclass 15, count 2 2006.257.02:13:12.68#ibcon#about to read 6, iclass 15, count 2 2006.257.02:13:12.68#ibcon#read 6, iclass 15, count 2 2006.257.02:13:12.68#ibcon#end of sib2, iclass 15, count 2 2006.257.02:13:12.68#ibcon#*mode == 0, iclass 15, count 2 2006.257.02:13:12.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.02:13:12.68#ibcon#[25=AT03-08\r\n] 2006.257.02:13:12.68#ibcon#*before write, iclass 15, count 2 2006.257.02:13:12.68#ibcon#enter sib2, iclass 15, count 2 2006.257.02:13:12.68#ibcon#flushed, iclass 15, count 2 2006.257.02:13:12.68#ibcon#about to write, iclass 15, count 2 2006.257.02:13:12.68#ibcon#wrote, iclass 15, count 2 2006.257.02:13:12.68#ibcon#about to read 3, iclass 15, count 2 2006.257.02:13:12.71#ibcon#read 3, iclass 15, count 2 2006.257.02:13:12.71#ibcon#about to read 4, iclass 15, count 2 2006.257.02:13:12.71#ibcon#read 4, iclass 15, count 2 2006.257.02:13:12.71#ibcon#about to read 5, iclass 15, count 2 2006.257.02:13:12.71#ibcon#read 5, iclass 15, count 2 2006.257.02:13:12.71#ibcon#about to read 6, iclass 15, count 2 2006.257.02:13:12.71#ibcon#read 6, iclass 15, count 2 2006.257.02:13:12.71#ibcon#end of sib2, iclass 15, count 2 2006.257.02:13:12.71#ibcon#*after write, iclass 15, count 2 2006.257.02:13:12.71#ibcon#*before return 0, iclass 15, count 2 2006.257.02:13:12.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:12.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:12.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.02:13:12.71#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:12.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:12.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:12.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:12.83#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:13:12.83#ibcon#first serial, iclass 15, count 0 2006.257.02:13:12.83#ibcon#enter sib2, iclass 15, count 0 2006.257.02:13:12.83#ibcon#flushed, iclass 15, count 0 2006.257.02:13:12.83#ibcon#about to write, iclass 15, count 0 2006.257.02:13:12.83#ibcon#wrote, iclass 15, count 0 2006.257.02:13:12.83#ibcon#about to read 3, iclass 15, count 0 2006.257.02:13:12.85#ibcon#read 3, iclass 15, count 0 2006.257.02:13:12.85#ibcon#about to read 4, iclass 15, count 0 2006.257.02:13:12.85#ibcon#read 4, iclass 15, count 0 2006.257.02:13:12.85#ibcon#about to read 5, iclass 15, count 0 2006.257.02:13:12.85#ibcon#read 5, iclass 15, count 0 2006.257.02:13:12.85#ibcon#about to read 6, iclass 15, count 0 2006.257.02:13:12.85#ibcon#read 6, iclass 15, count 0 2006.257.02:13:12.85#ibcon#end of sib2, iclass 15, count 0 2006.257.02:13:12.85#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:13:12.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:13:12.85#ibcon#[25=USB\r\n] 2006.257.02:13:12.85#ibcon#*before write, iclass 15, count 0 2006.257.02:13:12.85#ibcon#enter sib2, iclass 15, count 0 2006.257.02:13:12.85#ibcon#flushed, iclass 15, count 0 2006.257.02:13:12.85#ibcon#about to write, iclass 15, count 0 2006.257.02:13:12.85#ibcon#wrote, iclass 15, count 0 2006.257.02:13:12.85#ibcon#about to read 3, iclass 15, count 0 2006.257.02:13:12.88#ibcon#read 3, iclass 15, count 0 2006.257.02:13:12.88#ibcon#about to read 4, iclass 15, count 0 2006.257.02:13:12.88#ibcon#read 4, iclass 15, count 0 2006.257.02:13:12.88#ibcon#about to read 5, iclass 15, count 0 2006.257.02:13:12.88#ibcon#read 5, iclass 15, count 0 2006.257.02:13:12.88#ibcon#about to read 6, iclass 15, count 0 2006.257.02:13:12.88#ibcon#read 6, iclass 15, count 0 2006.257.02:13:12.88#ibcon#end of sib2, iclass 15, count 0 2006.257.02:13:12.88#ibcon#*after write, iclass 15, count 0 2006.257.02:13:12.88#ibcon#*before return 0, iclass 15, count 0 2006.257.02:13:12.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:12.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:12.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:13:12.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:13:12.88$vck44/valo=4,624.99 2006.257.02:13:12.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.02:13:12.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.02:13:12.88#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:12.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:12.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:12.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:12.88#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:13:12.88#ibcon#first serial, iclass 17, count 0 2006.257.02:13:12.88#ibcon#enter sib2, iclass 17, count 0 2006.257.02:13:12.88#ibcon#flushed, iclass 17, count 0 2006.257.02:13:12.88#ibcon#about to write, iclass 17, count 0 2006.257.02:13:12.88#ibcon#wrote, iclass 17, count 0 2006.257.02:13:12.88#ibcon#about to read 3, iclass 17, count 0 2006.257.02:13:12.90#ibcon#read 3, iclass 17, count 0 2006.257.02:13:12.90#ibcon#about to read 4, iclass 17, count 0 2006.257.02:13:12.90#ibcon#read 4, iclass 17, count 0 2006.257.02:13:12.90#ibcon#about to read 5, iclass 17, count 0 2006.257.02:13:12.90#ibcon#read 5, iclass 17, count 0 2006.257.02:13:12.90#ibcon#about to read 6, iclass 17, count 0 2006.257.02:13:12.90#ibcon#read 6, iclass 17, count 0 2006.257.02:13:12.90#ibcon#end of sib2, iclass 17, count 0 2006.257.02:13:12.90#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:13:12.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:13:12.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:13:12.90#ibcon#*before write, iclass 17, count 0 2006.257.02:13:12.90#ibcon#enter sib2, iclass 17, count 0 2006.257.02:13:12.90#ibcon#flushed, iclass 17, count 0 2006.257.02:13:12.90#ibcon#about to write, iclass 17, count 0 2006.257.02:13:12.90#ibcon#wrote, iclass 17, count 0 2006.257.02:13:12.90#ibcon#about to read 3, iclass 17, count 0 2006.257.02:13:12.94#ibcon#read 3, iclass 17, count 0 2006.257.02:13:12.94#ibcon#about to read 4, iclass 17, count 0 2006.257.02:13:12.94#ibcon#read 4, iclass 17, count 0 2006.257.02:13:12.94#ibcon#about to read 5, iclass 17, count 0 2006.257.02:13:12.94#ibcon#read 5, iclass 17, count 0 2006.257.02:13:12.94#ibcon#about to read 6, iclass 17, count 0 2006.257.02:13:12.94#ibcon#read 6, iclass 17, count 0 2006.257.02:13:12.94#ibcon#end of sib2, iclass 17, count 0 2006.257.02:13:12.94#ibcon#*after write, iclass 17, count 0 2006.257.02:13:12.94#ibcon#*before return 0, iclass 17, count 0 2006.257.02:13:12.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:12.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:12.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:13:12.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:13:12.94$vck44/va=4,7 2006.257.02:13:12.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.02:13:12.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.02:13:12.94#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:12.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:13.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:13.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:13.00#ibcon#enter wrdev, iclass 19, count 2 2006.257.02:13:13.00#ibcon#first serial, iclass 19, count 2 2006.257.02:13:13.00#ibcon#enter sib2, iclass 19, count 2 2006.257.02:13:13.00#ibcon#flushed, iclass 19, count 2 2006.257.02:13:13.00#ibcon#about to write, iclass 19, count 2 2006.257.02:13:13.00#ibcon#wrote, iclass 19, count 2 2006.257.02:13:13.00#ibcon#about to read 3, iclass 19, count 2 2006.257.02:13:13.02#ibcon#read 3, iclass 19, count 2 2006.257.02:13:13.02#ibcon#about to read 4, iclass 19, count 2 2006.257.02:13:13.02#ibcon#read 4, iclass 19, count 2 2006.257.02:13:13.02#ibcon#about to read 5, iclass 19, count 2 2006.257.02:13:13.02#ibcon#read 5, iclass 19, count 2 2006.257.02:13:13.02#ibcon#about to read 6, iclass 19, count 2 2006.257.02:13:13.02#ibcon#read 6, iclass 19, count 2 2006.257.02:13:13.02#ibcon#end of sib2, iclass 19, count 2 2006.257.02:13:13.02#ibcon#*mode == 0, iclass 19, count 2 2006.257.02:13:13.02#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.02:13:13.02#ibcon#[25=AT04-07\r\n] 2006.257.02:13:13.02#ibcon#*before write, iclass 19, count 2 2006.257.02:13:13.02#ibcon#enter sib2, iclass 19, count 2 2006.257.02:13:13.02#ibcon#flushed, iclass 19, count 2 2006.257.02:13:13.02#ibcon#about to write, iclass 19, count 2 2006.257.02:13:13.02#ibcon#wrote, iclass 19, count 2 2006.257.02:13:13.02#ibcon#about to read 3, iclass 19, count 2 2006.257.02:13:13.05#ibcon#read 3, iclass 19, count 2 2006.257.02:13:13.05#ibcon#about to read 4, iclass 19, count 2 2006.257.02:13:13.05#ibcon#read 4, iclass 19, count 2 2006.257.02:13:13.05#ibcon#about to read 5, iclass 19, count 2 2006.257.02:13:13.05#ibcon#read 5, iclass 19, count 2 2006.257.02:13:13.05#ibcon#about to read 6, iclass 19, count 2 2006.257.02:13:13.05#ibcon#read 6, iclass 19, count 2 2006.257.02:13:13.05#ibcon#end of sib2, iclass 19, count 2 2006.257.02:13:13.05#ibcon#*after write, iclass 19, count 2 2006.257.02:13:13.05#ibcon#*before return 0, iclass 19, count 2 2006.257.02:13:13.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:13.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:13.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.02:13:13.05#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:13.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:13.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:13.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:13.17#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:13:13.17#ibcon#first serial, iclass 19, count 0 2006.257.02:13:13.17#ibcon#enter sib2, iclass 19, count 0 2006.257.02:13:13.17#ibcon#flushed, iclass 19, count 0 2006.257.02:13:13.17#ibcon#about to write, iclass 19, count 0 2006.257.02:13:13.17#ibcon#wrote, iclass 19, count 0 2006.257.02:13:13.17#ibcon#about to read 3, iclass 19, count 0 2006.257.02:13:13.19#ibcon#read 3, iclass 19, count 0 2006.257.02:13:13.19#ibcon#about to read 4, iclass 19, count 0 2006.257.02:13:13.19#ibcon#read 4, iclass 19, count 0 2006.257.02:13:13.19#ibcon#about to read 5, iclass 19, count 0 2006.257.02:13:13.19#ibcon#read 5, iclass 19, count 0 2006.257.02:13:13.19#ibcon#about to read 6, iclass 19, count 0 2006.257.02:13:13.19#ibcon#read 6, iclass 19, count 0 2006.257.02:13:13.19#ibcon#end of sib2, iclass 19, count 0 2006.257.02:13:13.19#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:13:13.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:13:13.19#ibcon#[25=USB\r\n] 2006.257.02:13:13.19#ibcon#*before write, iclass 19, count 0 2006.257.02:13:13.19#ibcon#enter sib2, iclass 19, count 0 2006.257.02:13:13.19#ibcon#flushed, iclass 19, count 0 2006.257.02:13:13.19#ibcon#about to write, iclass 19, count 0 2006.257.02:13:13.19#ibcon#wrote, iclass 19, count 0 2006.257.02:13:13.19#ibcon#about to read 3, iclass 19, count 0 2006.257.02:13:13.22#ibcon#read 3, iclass 19, count 0 2006.257.02:13:13.22#ibcon#about to read 4, iclass 19, count 0 2006.257.02:13:13.22#ibcon#read 4, iclass 19, count 0 2006.257.02:13:13.22#ibcon#about to read 5, iclass 19, count 0 2006.257.02:13:13.22#ibcon#read 5, iclass 19, count 0 2006.257.02:13:13.22#ibcon#about to read 6, iclass 19, count 0 2006.257.02:13:13.22#ibcon#read 6, iclass 19, count 0 2006.257.02:13:13.22#ibcon#end of sib2, iclass 19, count 0 2006.257.02:13:13.22#ibcon#*after write, iclass 19, count 0 2006.257.02:13:13.22#ibcon#*before return 0, iclass 19, count 0 2006.257.02:13:13.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:13.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:13.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:13:13.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:13:13.22$vck44/valo=5,734.99 2006.257.02:13:13.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.02:13:13.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.02:13:13.22#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:13.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:13.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:13.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:13.22#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:13:13.22#ibcon#first serial, iclass 21, count 0 2006.257.02:13:13.22#ibcon#enter sib2, iclass 21, count 0 2006.257.02:13:13.22#ibcon#flushed, iclass 21, count 0 2006.257.02:13:13.22#ibcon#about to write, iclass 21, count 0 2006.257.02:13:13.22#ibcon#wrote, iclass 21, count 0 2006.257.02:13:13.22#ibcon#about to read 3, iclass 21, count 0 2006.257.02:13:13.24#ibcon#read 3, iclass 21, count 0 2006.257.02:13:13.24#ibcon#about to read 4, iclass 21, count 0 2006.257.02:13:13.24#ibcon#read 4, iclass 21, count 0 2006.257.02:13:13.24#ibcon#about to read 5, iclass 21, count 0 2006.257.02:13:13.24#ibcon#read 5, iclass 21, count 0 2006.257.02:13:13.24#ibcon#about to read 6, iclass 21, count 0 2006.257.02:13:13.24#ibcon#read 6, iclass 21, count 0 2006.257.02:13:13.24#ibcon#end of sib2, iclass 21, count 0 2006.257.02:13:13.24#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:13:13.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:13:13.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:13:13.24#ibcon#*before write, iclass 21, count 0 2006.257.02:13:13.24#ibcon#enter sib2, iclass 21, count 0 2006.257.02:13:13.24#ibcon#flushed, iclass 21, count 0 2006.257.02:13:13.24#ibcon#about to write, iclass 21, count 0 2006.257.02:13:13.24#ibcon#wrote, iclass 21, count 0 2006.257.02:13:13.24#ibcon#about to read 3, iclass 21, count 0 2006.257.02:13:13.28#ibcon#read 3, iclass 21, count 0 2006.257.02:13:13.28#ibcon#about to read 4, iclass 21, count 0 2006.257.02:13:13.28#ibcon#read 4, iclass 21, count 0 2006.257.02:13:13.28#ibcon#about to read 5, iclass 21, count 0 2006.257.02:13:13.28#ibcon#read 5, iclass 21, count 0 2006.257.02:13:13.28#ibcon#about to read 6, iclass 21, count 0 2006.257.02:13:13.28#ibcon#read 6, iclass 21, count 0 2006.257.02:13:13.28#ibcon#end of sib2, iclass 21, count 0 2006.257.02:13:13.28#ibcon#*after write, iclass 21, count 0 2006.257.02:13:13.28#ibcon#*before return 0, iclass 21, count 0 2006.257.02:13:13.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:13.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:13.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:13:13.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:13:13.28$vck44/va=5,4 2006.257.02:13:13.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.02:13:13.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.02:13:13.28#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:13.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:13.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:13.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:13.34#ibcon#enter wrdev, iclass 23, count 2 2006.257.02:13:13.34#ibcon#first serial, iclass 23, count 2 2006.257.02:13:13.34#ibcon#enter sib2, iclass 23, count 2 2006.257.02:13:13.34#ibcon#flushed, iclass 23, count 2 2006.257.02:13:13.34#ibcon#about to write, iclass 23, count 2 2006.257.02:13:13.34#ibcon#wrote, iclass 23, count 2 2006.257.02:13:13.34#ibcon#about to read 3, iclass 23, count 2 2006.257.02:13:13.36#ibcon#read 3, iclass 23, count 2 2006.257.02:13:13.36#ibcon#about to read 4, iclass 23, count 2 2006.257.02:13:13.36#ibcon#read 4, iclass 23, count 2 2006.257.02:13:13.36#ibcon#about to read 5, iclass 23, count 2 2006.257.02:13:13.36#ibcon#read 5, iclass 23, count 2 2006.257.02:13:13.36#ibcon#about to read 6, iclass 23, count 2 2006.257.02:13:13.36#ibcon#read 6, iclass 23, count 2 2006.257.02:13:13.36#ibcon#end of sib2, iclass 23, count 2 2006.257.02:13:13.36#ibcon#*mode == 0, iclass 23, count 2 2006.257.02:13:13.36#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.02:13:13.36#ibcon#[25=AT05-04\r\n] 2006.257.02:13:13.36#ibcon#*before write, iclass 23, count 2 2006.257.02:13:13.36#ibcon#enter sib2, iclass 23, count 2 2006.257.02:13:13.36#ibcon#flushed, iclass 23, count 2 2006.257.02:13:13.36#ibcon#about to write, iclass 23, count 2 2006.257.02:13:13.36#ibcon#wrote, iclass 23, count 2 2006.257.02:13:13.36#ibcon#about to read 3, iclass 23, count 2 2006.257.02:13:13.39#ibcon#read 3, iclass 23, count 2 2006.257.02:13:13.39#ibcon#about to read 4, iclass 23, count 2 2006.257.02:13:13.39#ibcon#read 4, iclass 23, count 2 2006.257.02:13:13.39#ibcon#about to read 5, iclass 23, count 2 2006.257.02:13:13.39#ibcon#read 5, iclass 23, count 2 2006.257.02:13:13.39#ibcon#about to read 6, iclass 23, count 2 2006.257.02:13:13.39#ibcon#read 6, iclass 23, count 2 2006.257.02:13:13.39#ibcon#end of sib2, iclass 23, count 2 2006.257.02:13:13.39#ibcon#*after write, iclass 23, count 2 2006.257.02:13:13.39#ibcon#*before return 0, iclass 23, count 2 2006.257.02:13:13.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:13.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:13.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.02:13:13.39#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:13.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:13.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:13.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:13.51#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:13:13.51#ibcon#first serial, iclass 23, count 0 2006.257.02:13:13.51#ibcon#enter sib2, iclass 23, count 0 2006.257.02:13:13.51#ibcon#flushed, iclass 23, count 0 2006.257.02:13:13.51#ibcon#about to write, iclass 23, count 0 2006.257.02:13:13.51#ibcon#wrote, iclass 23, count 0 2006.257.02:13:13.51#ibcon#about to read 3, iclass 23, count 0 2006.257.02:13:13.53#ibcon#read 3, iclass 23, count 0 2006.257.02:13:13.53#ibcon#about to read 4, iclass 23, count 0 2006.257.02:13:13.53#ibcon#read 4, iclass 23, count 0 2006.257.02:13:13.53#ibcon#about to read 5, iclass 23, count 0 2006.257.02:13:13.53#ibcon#read 5, iclass 23, count 0 2006.257.02:13:13.53#ibcon#about to read 6, iclass 23, count 0 2006.257.02:13:13.53#ibcon#read 6, iclass 23, count 0 2006.257.02:13:13.53#ibcon#end of sib2, iclass 23, count 0 2006.257.02:13:13.53#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:13:13.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:13:13.53#ibcon#[25=USB\r\n] 2006.257.02:13:13.53#ibcon#*before write, iclass 23, count 0 2006.257.02:13:13.53#ibcon#enter sib2, iclass 23, count 0 2006.257.02:13:13.53#ibcon#flushed, iclass 23, count 0 2006.257.02:13:13.53#ibcon#about to write, iclass 23, count 0 2006.257.02:13:13.53#ibcon#wrote, iclass 23, count 0 2006.257.02:13:13.53#ibcon#about to read 3, iclass 23, count 0 2006.257.02:13:13.56#ibcon#read 3, iclass 23, count 0 2006.257.02:13:13.56#ibcon#about to read 4, iclass 23, count 0 2006.257.02:13:13.56#ibcon#read 4, iclass 23, count 0 2006.257.02:13:13.56#ibcon#about to read 5, iclass 23, count 0 2006.257.02:13:13.56#ibcon#read 5, iclass 23, count 0 2006.257.02:13:13.56#ibcon#about to read 6, iclass 23, count 0 2006.257.02:13:13.56#ibcon#read 6, iclass 23, count 0 2006.257.02:13:13.56#ibcon#end of sib2, iclass 23, count 0 2006.257.02:13:13.56#ibcon#*after write, iclass 23, count 0 2006.257.02:13:13.56#ibcon#*before return 0, iclass 23, count 0 2006.257.02:13:13.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:13.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:13.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:13:13.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:13:13.56$vck44/valo=6,814.99 2006.257.02:13:13.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.02:13:13.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.02:13:13.56#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:13.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:13.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:13.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:13.56#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:13:13.56#ibcon#first serial, iclass 25, count 0 2006.257.02:13:13.56#ibcon#enter sib2, iclass 25, count 0 2006.257.02:13:13.56#ibcon#flushed, iclass 25, count 0 2006.257.02:13:13.56#ibcon#about to write, iclass 25, count 0 2006.257.02:13:13.56#ibcon#wrote, iclass 25, count 0 2006.257.02:13:13.56#ibcon#about to read 3, iclass 25, count 0 2006.257.02:13:13.58#ibcon#read 3, iclass 25, count 0 2006.257.02:13:13.58#ibcon#about to read 4, iclass 25, count 0 2006.257.02:13:13.58#ibcon#read 4, iclass 25, count 0 2006.257.02:13:13.58#ibcon#about to read 5, iclass 25, count 0 2006.257.02:13:13.58#ibcon#read 5, iclass 25, count 0 2006.257.02:13:13.58#ibcon#about to read 6, iclass 25, count 0 2006.257.02:13:13.58#ibcon#read 6, iclass 25, count 0 2006.257.02:13:13.58#ibcon#end of sib2, iclass 25, count 0 2006.257.02:13:13.58#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:13:13.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:13:13.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:13:13.58#ibcon#*before write, iclass 25, count 0 2006.257.02:13:13.58#ibcon#enter sib2, iclass 25, count 0 2006.257.02:13:13.58#ibcon#flushed, iclass 25, count 0 2006.257.02:13:13.58#ibcon#about to write, iclass 25, count 0 2006.257.02:13:13.58#ibcon#wrote, iclass 25, count 0 2006.257.02:13:13.58#ibcon#about to read 3, iclass 25, count 0 2006.257.02:13:13.62#ibcon#read 3, iclass 25, count 0 2006.257.02:13:13.62#ibcon#about to read 4, iclass 25, count 0 2006.257.02:13:13.62#ibcon#read 4, iclass 25, count 0 2006.257.02:13:13.62#ibcon#about to read 5, iclass 25, count 0 2006.257.02:13:13.62#ibcon#read 5, iclass 25, count 0 2006.257.02:13:13.62#ibcon#about to read 6, iclass 25, count 0 2006.257.02:13:13.62#ibcon#read 6, iclass 25, count 0 2006.257.02:13:13.62#ibcon#end of sib2, iclass 25, count 0 2006.257.02:13:13.62#ibcon#*after write, iclass 25, count 0 2006.257.02:13:13.62#ibcon#*before return 0, iclass 25, count 0 2006.257.02:13:13.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:13.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:13.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:13:13.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:13:13.62$vck44/va=6,4 2006.257.02:13:13.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.02:13:13.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.02:13:13.62#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:13.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:13.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:13.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:13.68#ibcon#enter wrdev, iclass 27, count 2 2006.257.02:13:13.68#ibcon#first serial, iclass 27, count 2 2006.257.02:13:13.68#ibcon#enter sib2, iclass 27, count 2 2006.257.02:13:13.68#ibcon#flushed, iclass 27, count 2 2006.257.02:13:13.68#ibcon#about to write, iclass 27, count 2 2006.257.02:13:13.68#ibcon#wrote, iclass 27, count 2 2006.257.02:13:13.68#ibcon#about to read 3, iclass 27, count 2 2006.257.02:13:13.70#ibcon#read 3, iclass 27, count 2 2006.257.02:13:13.70#ibcon#about to read 4, iclass 27, count 2 2006.257.02:13:13.70#ibcon#read 4, iclass 27, count 2 2006.257.02:13:13.70#ibcon#about to read 5, iclass 27, count 2 2006.257.02:13:13.70#ibcon#read 5, iclass 27, count 2 2006.257.02:13:13.70#ibcon#about to read 6, iclass 27, count 2 2006.257.02:13:13.70#ibcon#read 6, iclass 27, count 2 2006.257.02:13:13.70#ibcon#end of sib2, iclass 27, count 2 2006.257.02:13:13.70#ibcon#*mode == 0, iclass 27, count 2 2006.257.02:13:13.70#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.02:13:13.70#ibcon#[25=AT06-04\r\n] 2006.257.02:13:13.70#ibcon#*before write, iclass 27, count 2 2006.257.02:13:13.70#ibcon#enter sib2, iclass 27, count 2 2006.257.02:13:13.70#ibcon#flushed, iclass 27, count 2 2006.257.02:13:13.70#ibcon#about to write, iclass 27, count 2 2006.257.02:13:13.70#ibcon#wrote, iclass 27, count 2 2006.257.02:13:13.70#ibcon#about to read 3, iclass 27, count 2 2006.257.02:13:13.73#ibcon#read 3, iclass 27, count 2 2006.257.02:13:13.73#ibcon#about to read 4, iclass 27, count 2 2006.257.02:13:13.73#ibcon#read 4, iclass 27, count 2 2006.257.02:13:13.73#ibcon#about to read 5, iclass 27, count 2 2006.257.02:13:13.73#ibcon#read 5, iclass 27, count 2 2006.257.02:13:13.73#ibcon#about to read 6, iclass 27, count 2 2006.257.02:13:13.73#ibcon#read 6, iclass 27, count 2 2006.257.02:13:13.73#ibcon#end of sib2, iclass 27, count 2 2006.257.02:13:13.73#ibcon#*after write, iclass 27, count 2 2006.257.02:13:13.73#ibcon#*before return 0, iclass 27, count 2 2006.257.02:13:13.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:13.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:13.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.02:13:13.73#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:13.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:13.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:13.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:13.85#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:13:13.85#ibcon#first serial, iclass 27, count 0 2006.257.02:13:13.85#ibcon#enter sib2, iclass 27, count 0 2006.257.02:13:13.85#ibcon#flushed, iclass 27, count 0 2006.257.02:13:13.85#ibcon#about to write, iclass 27, count 0 2006.257.02:13:13.85#ibcon#wrote, iclass 27, count 0 2006.257.02:13:13.85#ibcon#about to read 3, iclass 27, count 0 2006.257.02:13:13.87#ibcon#read 3, iclass 27, count 0 2006.257.02:13:13.87#ibcon#about to read 4, iclass 27, count 0 2006.257.02:13:13.87#ibcon#read 4, iclass 27, count 0 2006.257.02:13:13.87#ibcon#about to read 5, iclass 27, count 0 2006.257.02:13:13.87#ibcon#read 5, iclass 27, count 0 2006.257.02:13:13.87#ibcon#about to read 6, iclass 27, count 0 2006.257.02:13:13.87#ibcon#read 6, iclass 27, count 0 2006.257.02:13:13.87#ibcon#end of sib2, iclass 27, count 0 2006.257.02:13:13.87#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:13:13.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:13:13.87#ibcon#[25=USB\r\n] 2006.257.02:13:13.87#ibcon#*before write, iclass 27, count 0 2006.257.02:13:13.87#ibcon#enter sib2, iclass 27, count 0 2006.257.02:13:13.87#ibcon#flushed, iclass 27, count 0 2006.257.02:13:13.87#ibcon#about to write, iclass 27, count 0 2006.257.02:13:13.87#ibcon#wrote, iclass 27, count 0 2006.257.02:13:13.87#ibcon#about to read 3, iclass 27, count 0 2006.257.02:13:13.90#ibcon#read 3, iclass 27, count 0 2006.257.02:13:13.90#ibcon#about to read 4, iclass 27, count 0 2006.257.02:13:13.90#ibcon#read 4, iclass 27, count 0 2006.257.02:13:13.90#ibcon#about to read 5, iclass 27, count 0 2006.257.02:13:13.90#ibcon#read 5, iclass 27, count 0 2006.257.02:13:13.90#ibcon#about to read 6, iclass 27, count 0 2006.257.02:13:13.90#ibcon#read 6, iclass 27, count 0 2006.257.02:13:13.90#ibcon#end of sib2, iclass 27, count 0 2006.257.02:13:13.90#ibcon#*after write, iclass 27, count 0 2006.257.02:13:13.90#ibcon#*before return 0, iclass 27, count 0 2006.257.02:13:13.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:13.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:13.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:13:13.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:13:13.90$vck44/valo=7,864.99 2006.257.02:13:13.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.02:13:13.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.02:13:13.90#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:13.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:13.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:13.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:13.90#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:13:13.90#ibcon#first serial, iclass 29, count 0 2006.257.02:13:13.90#ibcon#enter sib2, iclass 29, count 0 2006.257.02:13:13.90#ibcon#flushed, iclass 29, count 0 2006.257.02:13:13.90#ibcon#about to write, iclass 29, count 0 2006.257.02:13:13.90#ibcon#wrote, iclass 29, count 0 2006.257.02:13:13.90#ibcon#about to read 3, iclass 29, count 0 2006.257.02:13:13.92#ibcon#read 3, iclass 29, count 0 2006.257.02:13:13.92#ibcon#about to read 4, iclass 29, count 0 2006.257.02:13:13.92#ibcon#read 4, iclass 29, count 0 2006.257.02:13:13.92#ibcon#about to read 5, iclass 29, count 0 2006.257.02:13:13.92#ibcon#read 5, iclass 29, count 0 2006.257.02:13:13.92#ibcon#about to read 6, iclass 29, count 0 2006.257.02:13:13.92#ibcon#read 6, iclass 29, count 0 2006.257.02:13:13.92#ibcon#end of sib2, iclass 29, count 0 2006.257.02:13:13.92#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:13:13.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:13:13.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:13:13.92#ibcon#*before write, iclass 29, count 0 2006.257.02:13:13.92#ibcon#enter sib2, iclass 29, count 0 2006.257.02:13:13.92#ibcon#flushed, iclass 29, count 0 2006.257.02:13:13.92#ibcon#about to write, iclass 29, count 0 2006.257.02:13:13.92#ibcon#wrote, iclass 29, count 0 2006.257.02:13:13.92#ibcon#about to read 3, iclass 29, count 0 2006.257.02:13:13.96#ibcon#read 3, iclass 29, count 0 2006.257.02:13:13.96#ibcon#about to read 4, iclass 29, count 0 2006.257.02:13:13.96#ibcon#read 4, iclass 29, count 0 2006.257.02:13:13.96#ibcon#about to read 5, iclass 29, count 0 2006.257.02:13:13.96#ibcon#read 5, iclass 29, count 0 2006.257.02:13:13.96#ibcon#about to read 6, iclass 29, count 0 2006.257.02:13:13.96#ibcon#read 6, iclass 29, count 0 2006.257.02:13:13.96#ibcon#end of sib2, iclass 29, count 0 2006.257.02:13:13.96#ibcon#*after write, iclass 29, count 0 2006.257.02:13:13.96#ibcon#*before return 0, iclass 29, count 0 2006.257.02:13:13.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:13.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:13.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:13:13.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:13:13.96$vck44/va=7,4 2006.257.02:13:13.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.02:13:13.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.02:13:13.96#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:13.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:14.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:14.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:14.02#ibcon#enter wrdev, iclass 31, count 2 2006.257.02:13:14.02#ibcon#first serial, iclass 31, count 2 2006.257.02:13:14.02#ibcon#enter sib2, iclass 31, count 2 2006.257.02:13:14.02#ibcon#flushed, iclass 31, count 2 2006.257.02:13:14.02#ibcon#about to write, iclass 31, count 2 2006.257.02:13:14.02#ibcon#wrote, iclass 31, count 2 2006.257.02:13:14.02#ibcon#about to read 3, iclass 31, count 2 2006.257.02:13:14.04#ibcon#read 3, iclass 31, count 2 2006.257.02:13:14.04#ibcon#about to read 4, iclass 31, count 2 2006.257.02:13:14.04#ibcon#read 4, iclass 31, count 2 2006.257.02:13:14.04#ibcon#about to read 5, iclass 31, count 2 2006.257.02:13:14.04#ibcon#read 5, iclass 31, count 2 2006.257.02:13:14.04#ibcon#about to read 6, iclass 31, count 2 2006.257.02:13:14.04#ibcon#read 6, iclass 31, count 2 2006.257.02:13:14.04#ibcon#end of sib2, iclass 31, count 2 2006.257.02:13:14.04#ibcon#*mode == 0, iclass 31, count 2 2006.257.02:13:14.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.02:13:14.04#ibcon#[25=AT07-04\r\n] 2006.257.02:13:14.04#ibcon#*before write, iclass 31, count 2 2006.257.02:13:14.04#ibcon#enter sib2, iclass 31, count 2 2006.257.02:13:14.04#ibcon#flushed, iclass 31, count 2 2006.257.02:13:14.04#ibcon#about to write, iclass 31, count 2 2006.257.02:13:14.04#ibcon#wrote, iclass 31, count 2 2006.257.02:13:14.04#ibcon#about to read 3, iclass 31, count 2 2006.257.02:13:14.07#ibcon#read 3, iclass 31, count 2 2006.257.02:13:14.07#ibcon#about to read 4, iclass 31, count 2 2006.257.02:13:14.07#ibcon#read 4, iclass 31, count 2 2006.257.02:13:14.07#ibcon#about to read 5, iclass 31, count 2 2006.257.02:13:14.07#ibcon#read 5, iclass 31, count 2 2006.257.02:13:14.07#ibcon#about to read 6, iclass 31, count 2 2006.257.02:13:14.07#ibcon#read 6, iclass 31, count 2 2006.257.02:13:14.07#ibcon#end of sib2, iclass 31, count 2 2006.257.02:13:14.07#ibcon#*after write, iclass 31, count 2 2006.257.02:13:14.07#ibcon#*before return 0, iclass 31, count 2 2006.257.02:13:14.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:14.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:14.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.02:13:14.07#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:14.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:14.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:14.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:14.19#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:13:14.19#ibcon#first serial, iclass 31, count 0 2006.257.02:13:14.19#ibcon#enter sib2, iclass 31, count 0 2006.257.02:13:14.19#ibcon#flushed, iclass 31, count 0 2006.257.02:13:14.19#ibcon#about to write, iclass 31, count 0 2006.257.02:13:14.19#ibcon#wrote, iclass 31, count 0 2006.257.02:13:14.19#ibcon#about to read 3, iclass 31, count 0 2006.257.02:13:14.23#ibcon#read 3, iclass 31, count 0 2006.257.02:13:14.23#ibcon#about to read 4, iclass 31, count 0 2006.257.02:13:14.23#ibcon#read 4, iclass 31, count 0 2006.257.02:13:14.23#ibcon#about to read 5, iclass 31, count 0 2006.257.02:13:14.23#ibcon#read 5, iclass 31, count 0 2006.257.02:13:14.23#ibcon#about to read 6, iclass 31, count 0 2006.257.02:13:14.23#ibcon#read 6, iclass 31, count 0 2006.257.02:13:14.23#ibcon#end of sib2, iclass 31, count 0 2006.257.02:13:14.23#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:13:14.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:13:14.23#ibcon#[25=USB\r\n] 2006.257.02:13:14.23#ibcon#*before write, iclass 31, count 0 2006.257.02:13:14.23#ibcon#enter sib2, iclass 31, count 0 2006.257.02:13:14.23#ibcon#flushed, iclass 31, count 0 2006.257.02:13:14.23#ibcon#about to write, iclass 31, count 0 2006.257.02:13:14.23#ibcon#wrote, iclass 31, count 0 2006.257.02:13:14.23#ibcon#about to read 3, iclass 31, count 0 2006.257.02:13:14.26#ibcon#read 3, iclass 31, count 0 2006.257.02:13:14.26#ibcon#about to read 4, iclass 31, count 0 2006.257.02:13:14.26#ibcon#read 4, iclass 31, count 0 2006.257.02:13:14.26#ibcon#about to read 5, iclass 31, count 0 2006.257.02:13:14.26#ibcon#read 5, iclass 31, count 0 2006.257.02:13:14.26#ibcon#about to read 6, iclass 31, count 0 2006.257.02:13:14.26#ibcon#read 6, iclass 31, count 0 2006.257.02:13:14.26#ibcon#end of sib2, iclass 31, count 0 2006.257.02:13:14.26#ibcon#*after write, iclass 31, count 0 2006.257.02:13:14.26#ibcon#*before return 0, iclass 31, count 0 2006.257.02:13:14.26#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:14.26#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:14.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:13:14.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:13:14.26$vck44/valo=8,884.99 2006.257.02:13:14.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.02:13:14.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.02:13:14.26#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:14.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:14.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:14.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:14.26#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:13:14.26#ibcon#first serial, iclass 33, count 0 2006.257.02:13:14.26#ibcon#enter sib2, iclass 33, count 0 2006.257.02:13:14.26#ibcon#flushed, iclass 33, count 0 2006.257.02:13:14.26#ibcon#about to write, iclass 33, count 0 2006.257.02:13:14.26#ibcon#wrote, iclass 33, count 0 2006.257.02:13:14.26#ibcon#about to read 3, iclass 33, count 0 2006.257.02:13:14.28#ibcon#read 3, iclass 33, count 0 2006.257.02:13:14.28#ibcon#about to read 4, iclass 33, count 0 2006.257.02:13:14.28#ibcon#read 4, iclass 33, count 0 2006.257.02:13:14.28#ibcon#about to read 5, iclass 33, count 0 2006.257.02:13:14.28#ibcon#read 5, iclass 33, count 0 2006.257.02:13:14.28#ibcon#about to read 6, iclass 33, count 0 2006.257.02:13:14.28#ibcon#read 6, iclass 33, count 0 2006.257.02:13:14.28#ibcon#end of sib2, iclass 33, count 0 2006.257.02:13:14.28#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:13:14.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:13:14.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:13:14.28#ibcon#*before write, iclass 33, count 0 2006.257.02:13:14.28#ibcon#enter sib2, iclass 33, count 0 2006.257.02:13:14.28#ibcon#flushed, iclass 33, count 0 2006.257.02:13:14.28#ibcon#about to write, iclass 33, count 0 2006.257.02:13:14.28#ibcon#wrote, iclass 33, count 0 2006.257.02:13:14.28#ibcon#about to read 3, iclass 33, count 0 2006.257.02:13:14.32#ibcon#read 3, iclass 33, count 0 2006.257.02:13:14.32#ibcon#about to read 4, iclass 33, count 0 2006.257.02:13:14.32#ibcon#read 4, iclass 33, count 0 2006.257.02:13:14.32#ibcon#about to read 5, iclass 33, count 0 2006.257.02:13:14.32#ibcon#read 5, iclass 33, count 0 2006.257.02:13:14.32#ibcon#about to read 6, iclass 33, count 0 2006.257.02:13:14.32#ibcon#read 6, iclass 33, count 0 2006.257.02:13:14.32#ibcon#end of sib2, iclass 33, count 0 2006.257.02:13:14.32#ibcon#*after write, iclass 33, count 0 2006.257.02:13:14.32#ibcon#*before return 0, iclass 33, count 0 2006.257.02:13:14.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:14.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:14.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:13:14.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:13:14.32$vck44/va=8,4 2006.257.02:13:14.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.02:13:14.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.02:13:14.32#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:14.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:13:14.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:13:14.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:13:14.38#ibcon#enter wrdev, iclass 35, count 2 2006.257.02:13:14.38#ibcon#first serial, iclass 35, count 2 2006.257.02:13:14.38#ibcon#enter sib2, iclass 35, count 2 2006.257.02:13:14.38#ibcon#flushed, iclass 35, count 2 2006.257.02:13:14.38#ibcon#about to write, iclass 35, count 2 2006.257.02:13:14.38#ibcon#wrote, iclass 35, count 2 2006.257.02:13:14.38#ibcon#about to read 3, iclass 35, count 2 2006.257.02:13:14.40#ibcon#read 3, iclass 35, count 2 2006.257.02:13:14.40#ibcon#about to read 4, iclass 35, count 2 2006.257.02:13:14.40#ibcon#read 4, iclass 35, count 2 2006.257.02:13:14.40#ibcon#about to read 5, iclass 35, count 2 2006.257.02:13:14.40#ibcon#read 5, iclass 35, count 2 2006.257.02:13:14.40#ibcon#about to read 6, iclass 35, count 2 2006.257.02:13:14.40#ibcon#read 6, iclass 35, count 2 2006.257.02:13:14.40#ibcon#end of sib2, iclass 35, count 2 2006.257.02:13:14.40#ibcon#*mode == 0, iclass 35, count 2 2006.257.02:13:14.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.02:13:14.40#ibcon#[25=AT08-04\r\n] 2006.257.02:13:14.40#ibcon#*before write, iclass 35, count 2 2006.257.02:13:14.40#ibcon#enter sib2, iclass 35, count 2 2006.257.02:13:14.40#ibcon#flushed, iclass 35, count 2 2006.257.02:13:14.40#ibcon#about to write, iclass 35, count 2 2006.257.02:13:14.40#ibcon#wrote, iclass 35, count 2 2006.257.02:13:14.40#ibcon#about to read 3, iclass 35, count 2 2006.257.02:13:14.43#ibcon#read 3, iclass 35, count 2 2006.257.02:13:14.43#ibcon#about to read 4, iclass 35, count 2 2006.257.02:13:14.43#ibcon#read 4, iclass 35, count 2 2006.257.02:13:14.43#ibcon#about to read 5, iclass 35, count 2 2006.257.02:13:14.43#ibcon#read 5, iclass 35, count 2 2006.257.02:13:14.43#ibcon#about to read 6, iclass 35, count 2 2006.257.02:13:14.43#ibcon#read 6, iclass 35, count 2 2006.257.02:13:14.43#ibcon#end of sib2, iclass 35, count 2 2006.257.02:13:14.43#ibcon#*after write, iclass 35, count 2 2006.257.02:13:14.43#ibcon#*before return 0, iclass 35, count 2 2006.257.02:13:14.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:13:14.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:13:14.43#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.02:13:14.43#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:14.43#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:13:14.55#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:13:14.55#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:13:14.55#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:13:14.55#ibcon#first serial, iclass 35, count 0 2006.257.02:13:14.55#ibcon#enter sib2, iclass 35, count 0 2006.257.02:13:14.55#ibcon#flushed, iclass 35, count 0 2006.257.02:13:14.55#ibcon#about to write, iclass 35, count 0 2006.257.02:13:14.55#ibcon#wrote, iclass 35, count 0 2006.257.02:13:14.55#ibcon#about to read 3, iclass 35, count 0 2006.257.02:13:14.57#ibcon#read 3, iclass 35, count 0 2006.257.02:13:14.57#ibcon#about to read 4, iclass 35, count 0 2006.257.02:13:14.57#ibcon#read 4, iclass 35, count 0 2006.257.02:13:14.57#ibcon#about to read 5, iclass 35, count 0 2006.257.02:13:14.57#ibcon#read 5, iclass 35, count 0 2006.257.02:13:14.57#ibcon#about to read 6, iclass 35, count 0 2006.257.02:13:14.57#ibcon#read 6, iclass 35, count 0 2006.257.02:13:14.57#ibcon#end of sib2, iclass 35, count 0 2006.257.02:13:14.57#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:13:14.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:13:14.57#ibcon#[25=USB\r\n] 2006.257.02:13:14.57#ibcon#*before write, iclass 35, count 0 2006.257.02:13:14.57#ibcon#enter sib2, iclass 35, count 0 2006.257.02:13:14.57#ibcon#flushed, iclass 35, count 0 2006.257.02:13:14.57#ibcon#about to write, iclass 35, count 0 2006.257.02:13:14.57#ibcon#wrote, iclass 35, count 0 2006.257.02:13:14.57#ibcon#about to read 3, iclass 35, count 0 2006.257.02:13:14.60#ibcon#read 3, iclass 35, count 0 2006.257.02:13:14.60#ibcon#about to read 4, iclass 35, count 0 2006.257.02:13:14.60#ibcon#read 4, iclass 35, count 0 2006.257.02:13:14.60#ibcon#about to read 5, iclass 35, count 0 2006.257.02:13:14.60#ibcon#read 5, iclass 35, count 0 2006.257.02:13:14.60#ibcon#about to read 6, iclass 35, count 0 2006.257.02:13:14.60#ibcon#read 6, iclass 35, count 0 2006.257.02:13:14.60#ibcon#end of sib2, iclass 35, count 0 2006.257.02:13:14.60#ibcon#*after write, iclass 35, count 0 2006.257.02:13:14.60#ibcon#*before return 0, iclass 35, count 0 2006.257.02:13:14.60#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:13:14.60#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:13:14.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:13:14.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:13:14.60$vck44/vblo=1,629.99 2006.257.02:13:14.60#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.02:13:14.60#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.02:13:14.60#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:14.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:13:14.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:13:14.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:13:14.60#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:13:14.60#ibcon#first serial, iclass 37, count 0 2006.257.02:13:14.60#ibcon#enter sib2, iclass 37, count 0 2006.257.02:13:14.60#ibcon#flushed, iclass 37, count 0 2006.257.02:13:14.60#ibcon#about to write, iclass 37, count 0 2006.257.02:13:14.60#ibcon#wrote, iclass 37, count 0 2006.257.02:13:14.60#ibcon#about to read 3, iclass 37, count 0 2006.257.02:13:14.62#ibcon#read 3, iclass 37, count 0 2006.257.02:13:14.62#ibcon#about to read 4, iclass 37, count 0 2006.257.02:13:14.62#ibcon#read 4, iclass 37, count 0 2006.257.02:13:14.62#ibcon#about to read 5, iclass 37, count 0 2006.257.02:13:14.62#ibcon#read 5, iclass 37, count 0 2006.257.02:13:14.62#ibcon#about to read 6, iclass 37, count 0 2006.257.02:13:14.62#ibcon#read 6, iclass 37, count 0 2006.257.02:13:14.62#ibcon#end of sib2, iclass 37, count 0 2006.257.02:13:14.62#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:13:14.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:13:14.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:13:14.62#ibcon#*before write, iclass 37, count 0 2006.257.02:13:14.62#ibcon#enter sib2, iclass 37, count 0 2006.257.02:13:14.62#ibcon#flushed, iclass 37, count 0 2006.257.02:13:14.62#ibcon#about to write, iclass 37, count 0 2006.257.02:13:14.62#ibcon#wrote, iclass 37, count 0 2006.257.02:13:14.62#ibcon#about to read 3, iclass 37, count 0 2006.257.02:13:14.66#ibcon#read 3, iclass 37, count 0 2006.257.02:13:14.66#ibcon#about to read 4, iclass 37, count 0 2006.257.02:13:14.66#ibcon#read 4, iclass 37, count 0 2006.257.02:13:14.66#ibcon#about to read 5, iclass 37, count 0 2006.257.02:13:14.66#ibcon#read 5, iclass 37, count 0 2006.257.02:13:14.66#ibcon#about to read 6, iclass 37, count 0 2006.257.02:13:14.66#ibcon#read 6, iclass 37, count 0 2006.257.02:13:14.66#ibcon#end of sib2, iclass 37, count 0 2006.257.02:13:14.66#ibcon#*after write, iclass 37, count 0 2006.257.02:13:14.66#ibcon#*before return 0, iclass 37, count 0 2006.257.02:13:14.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:13:14.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:13:14.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:13:14.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:13:14.66$vck44/vb=1,4 2006.257.02:13:14.66#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.02:13:14.66#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.02:13:14.66#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:14.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:13:14.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:13:14.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:13:14.66#ibcon#enter wrdev, iclass 39, count 2 2006.257.02:13:14.66#ibcon#first serial, iclass 39, count 2 2006.257.02:13:14.66#ibcon#enter sib2, iclass 39, count 2 2006.257.02:13:14.66#ibcon#flushed, iclass 39, count 2 2006.257.02:13:14.66#ibcon#about to write, iclass 39, count 2 2006.257.02:13:14.66#ibcon#wrote, iclass 39, count 2 2006.257.02:13:14.66#ibcon#about to read 3, iclass 39, count 2 2006.257.02:13:14.68#ibcon#read 3, iclass 39, count 2 2006.257.02:13:14.68#ibcon#about to read 4, iclass 39, count 2 2006.257.02:13:14.68#ibcon#read 4, iclass 39, count 2 2006.257.02:13:14.68#ibcon#about to read 5, iclass 39, count 2 2006.257.02:13:14.68#ibcon#read 5, iclass 39, count 2 2006.257.02:13:14.68#ibcon#about to read 6, iclass 39, count 2 2006.257.02:13:14.68#ibcon#read 6, iclass 39, count 2 2006.257.02:13:14.68#ibcon#end of sib2, iclass 39, count 2 2006.257.02:13:14.68#ibcon#*mode == 0, iclass 39, count 2 2006.257.02:13:14.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.02:13:14.68#ibcon#[27=AT01-04\r\n] 2006.257.02:13:14.68#ibcon#*before write, iclass 39, count 2 2006.257.02:13:14.68#ibcon#enter sib2, iclass 39, count 2 2006.257.02:13:14.68#ibcon#flushed, iclass 39, count 2 2006.257.02:13:14.68#ibcon#about to write, iclass 39, count 2 2006.257.02:13:14.68#ibcon#wrote, iclass 39, count 2 2006.257.02:13:14.68#ibcon#about to read 3, iclass 39, count 2 2006.257.02:13:14.71#ibcon#read 3, iclass 39, count 2 2006.257.02:13:14.71#ibcon#about to read 4, iclass 39, count 2 2006.257.02:13:14.71#ibcon#read 4, iclass 39, count 2 2006.257.02:13:14.71#ibcon#about to read 5, iclass 39, count 2 2006.257.02:13:14.71#ibcon#read 5, iclass 39, count 2 2006.257.02:13:14.71#ibcon#about to read 6, iclass 39, count 2 2006.257.02:13:14.71#ibcon#read 6, iclass 39, count 2 2006.257.02:13:14.71#ibcon#end of sib2, iclass 39, count 2 2006.257.02:13:14.71#ibcon#*after write, iclass 39, count 2 2006.257.02:13:14.71#ibcon#*before return 0, iclass 39, count 2 2006.257.02:13:14.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:13:14.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:13:14.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.02:13:14.71#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:14.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:13:14.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:13:14.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:13:14.83#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:13:14.83#ibcon#first serial, iclass 39, count 0 2006.257.02:13:14.83#ibcon#enter sib2, iclass 39, count 0 2006.257.02:13:14.83#ibcon#flushed, iclass 39, count 0 2006.257.02:13:14.83#ibcon#about to write, iclass 39, count 0 2006.257.02:13:14.83#ibcon#wrote, iclass 39, count 0 2006.257.02:13:14.83#ibcon#about to read 3, iclass 39, count 0 2006.257.02:13:14.85#ibcon#read 3, iclass 39, count 0 2006.257.02:13:14.85#ibcon#about to read 4, iclass 39, count 0 2006.257.02:13:14.85#ibcon#read 4, iclass 39, count 0 2006.257.02:13:14.85#ibcon#about to read 5, iclass 39, count 0 2006.257.02:13:14.85#ibcon#read 5, iclass 39, count 0 2006.257.02:13:14.85#ibcon#about to read 6, iclass 39, count 0 2006.257.02:13:14.85#ibcon#read 6, iclass 39, count 0 2006.257.02:13:14.85#ibcon#end of sib2, iclass 39, count 0 2006.257.02:13:14.85#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:13:14.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:13:14.85#ibcon#[27=USB\r\n] 2006.257.02:13:14.85#ibcon#*before write, iclass 39, count 0 2006.257.02:13:14.85#ibcon#enter sib2, iclass 39, count 0 2006.257.02:13:14.85#ibcon#flushed, iclass 39, count 0 2006.257.02:13:14.85#ibcon#about to write, iclass 39, count 0 2006.257.02:13:14.85#ibcon#wrote, iclass 39, count 0 2006.257.02:13:14.85#ibcon#about to read 3, iclass 39, count 0 2006.257.02:13:14.88#ibcon#read 3, iclass 39, count 0 2006.257.02:13:14.88#ibcon#about to read 4, iclass 39, count 0 2006.257.02:13:14.88#ibcon#read 4, iclass 39, count 0 2006.257.02:13:14.88#ibcon#about to read 5, iclass 39, count 0 2006.257.02:13:14.88#ibcon#read 5, iclass 39, count 0 2006.257.02:13:14.88#ibcon#about to read 6, iclass 39, count 0 2006.257.02:13:14.88#ibcon#read 6, iclass 39, count 0 2006.257.02:13:14.88#ibcon#end of sib2, iclass 39, count 0 2006.257.02:13:14.88#ibcon#*after write, iclass 39, count 0 2006.257.02:13:14.88#ibcon#*before return 0, iclass 39, count 0 2006.257.02:13:14.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:13:14.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:13:14.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:13:14.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:13:14.88$vck44/vblo=2,634.99 2006.257.02:13:14.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.02:13:14.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.02:13:14.88#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:14.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:14.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:14.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:14.88#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:13:14.88#ibcon#first serial, iclass 3, count 0 2006.257.02:13:14.88#ibcon#enter sib2, iclass 3, count 0 2006.257.02:13:14.88#ibcon#flushed, iclass 3, count 0 2006.257.02:13:14.88#ibcon#about to write, iclass 3, count 0 2006.257.02:13:14.88#ibcon#wrote, iclass 3, count 0 2006.257.02:13:14.88#ibcon#about to read 3, iclass 3, count 0 2006.257.02:13:14.90#ibcon#read 3, iclass 3, count 0 2006.257.02:13:14.90#ibcon#about to read 4, iclass 3, count 0 2006.257.02:13:14.90#ibcon#read 4, iclass 3, count 0 2006.257.02:13:14.90#ibcon#about to read 5, iclass 3, count 0 2006.257.02:13:14.90#ibcon#read 5, iclass 3, count 0 2006.257.02:13:14.90#ibcon#about to read 6, iclass 3, count 0 2006.257.02:13:14.90#ibcon#read 6, iclass 3, count 0 2006.257.02:13:14.90#ibcon#end of sib2, iclass 3, count 0 2006.257.02:13:14.90#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:13:14.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:13:14.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:13:14.90#ibcon#*before write, iclass 3, count 0 2006.257.02:13:14.90#ibcon#enter sib2, iclass 3, count 0 2006.257.02:13:14.90#ibcon#flushed, iclass 3, count 0 2006.257.02:13:14.90#ibcon#about to write, iclass 3, count 0 2006.257.02:13:14.90#ibcon#wrote, iclass 3, count 0 2006.257.02:13:14.90#ibcon#about to read 3, iclass 3, count 0 2006.257.02:13:14.94#ibcon#read 3, iclass 3, count 0 2006.257.02:13:14.94#ibcon#about to read 4, iclass 3, count 0 2006.257.02:13:14.94#ibcon#read 4, iclass 3, count 0 2006.257.02:13:14.94#ibcon#about to read 5, iclass 3, count 0 2006.257.02:13:14.94#ibcon#read 5, iclass 3, count 0 2006.257.02:13:14.94#ibcon#about to read 6, iclass 3, count 0 2006.257.02:13:14.94#ibcon#read 6, iclass 3, count 0 2006.257.02:13:14.94#ibcon#end of sib2, iclass 3, count 0 2006.257.02:13:14.94#ibcon#*after write, iclass 3, count 0 2006.257.02:13:14.94#ibcon#*before return 0, iclass 3, count 0 2006.257.02:13:14.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:14.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:13:14.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:13:14.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:13:14.94$vck44/vb=2,5 2006.257.02:13:14.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.02:13:14.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.02:13:14.94#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:14.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:15.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:15.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:15.00#ibcon#enter wrdev, iclass 5, count 2 2006.257.02:13:15.00#ibcon#first serial, iclass 5, count 2 2006.257.02:13:15.00#ibcon#enter sib2, iclass 5, count 2 2006.257.02:13:15.00#ibcon#flushed, iclass 5, count 2 2006.257.02:13:15.00#ibcon#about to write, iclass 5, count 2 2006.257.02:13:15.00#ibcon#wrote, iclass 5, count 2 2006.257.02:13:15.00#ibcon#about to read 3, iclass 5, count 2 2006.257.02:13:15.02#ibcon#read 3, iclass 5, count 2 2006.257.02:13:15.02#ibcon#about to read 4, iclass 5, count 2 2006.257.02:13:15.02#ibcon#read 4, iclass 5, count 2 2006.257.02:13:15.02#ibcon#about to read 5, iclass 5, count 2 2006.257.02:13:15.02#ibcon#read 5, iclass 5, count 2 2006.257.02:13:15.02#ibcon#about to read 6, iclass 5, count 2 2006.257.02:13:15.02#ibcon#read 6, iclass 5, count 2 2006.257.02:13:15.02#ibcon#end of sib2, iclass 5, count 2 2006.257.02:13:15.02#ibcon#*mode == 0, iclass 5, count 2 2006.257.02:13:15.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.02:13:15.02#ibcon#[27=AT02-05\r\n] 2006.257.02:13:15.02#ibcon#*before write, iclass 5, count 2 2006.257.02:13:15.02#ibcon#enter sib2, iclass 5, count 2 2006.257.02:13:15.02#ibcon#flushed, iclass 5, count 2 2006.257.02:13:15.02#ibcon#about to write, iclass 5, count 2 2006.257.02:13:15.02#ibcon#wrote, iclass 5, count 2 2006.257.02:13:15.02#ibcon#about to read 3, iclass 5, count 2 2006.257.02:13:15.05#ibcon#read 3, iclass 5, count 2 2006.257.02:13:15.05#ibcon#about to read 4, iclass 5, count 2 2006.257.02:13:15.05#ibcon#read 4, iclass 5, count 2 2006.257.02:13:15.05#ibcon#about to read 5, iclass 5, count 2 2006.257.02:13:15.05#ibcon#read 5, iclass 5, count 2 2006.257.02:13:15.05#ibcon#about to read 6, iclass 5, count 2 2006.257.02:13:15.05#ibcon#read 6, iclass 5, count 2 2006.257.02:13:15.05#ibcon#end of sib2, iclass 5, count 2 2006.257.02:13:15.05#ibcon#*after write, iclass 5, count 2 2006.257.02:13:15.05#ibcon#*before return 0, iclass 5, count 2 2006.257.02:13:15.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:15.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:13:15.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.02:13:15.05#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:15.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:15.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:15.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:15.17#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:13:15.17#ibcon#first serial, iclass 5, count 0 2006.257.02:13:15.17#ibcon#enter sib2, iclass 5, count 0 2006.257.02:13:15.17#ibcon#flushed, iclass 5, count 0 2006.257.02:13:15.17#ibcon#about to write, iclass 5, count 0 2006.257.02:13:15.17#ibcon#wrote, iclass 5, count 0 2006.257.02:13:15.17#ibcon#about to read 3, iclass 5, count 0 2006.257.02:13:15.19#ibcon#read 3, iclass 5, count 0 2006.257.02:13:15.19#ibcon#about to read 4, iclass 5, count 0 2006.257.02:13:15.19#ibcon#read 4, iclass 5, count 0 2006.257.02:13:15.19#ibcon#about to read 5, iclass 5, count 0 2006.257.02:13:15.19#ibcon#read 5, iclass 5, count 0 2006.257.02:13:15.19#ibcon#about to read 6, iclass 5, count 0 2006.257.02:13:15.19#ibcon#read 6, iclass 5, count 0 2006.257.02:13:15.19#ibcon#end of sib2, iclass 5, count 0 2006.257.02:13:15.19#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:13:15.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:13:15.19#ibcon#[27=USB\r\n] 2006.257.02:13:15.19#ibcon#*before write, iclass 5, count 0 2006.257.02:13:15.19#ibcon#enter sib2, iclass 5, count 0 2006.257.02:13:15.19#ibcon#flushed, iclass 5, count 0 2006.257.02:13:15.19#ibcon#about to write, iclass 5, count 0 2006.257.02:13:15.19#ibcon#wrote, iclass 5, count 0 2006.257.02:13:15.19#ibcon#about to read 3, iclass 5, count 0 2006.257.02:13:15.22#ibcon#read 3, iclass 5, count 0 2006.257.02:13:15.22#ibcon#about to read 4, iclass 5, count 0 2006.257.02:13:15.22#ibcon#read 4, iclass 5, count 0 2006.257.02:13:15.22#ibcon#about to read 5, iclass 5, count 0 2006.257.02:13:15.22#ibcon#read 5, iclass 5, count 0 2006.257.02:13:15.22#ibcon#about to read 6, iclass 5, count 0 2006.257.02:13:15.22#ibcon#read 6, iclass 5, count 0 2006.257.02:13:15.22#ibcon#end of sib2, iclass 5, count 0 2006.257.02:13:15.22#ibcon#*after write, iclass 5, count 0 2006.257.02:13:15.22#ibcon#*before return 0, iclass 5, count 0 2006.257.02:13:15.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:15.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:13:15.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:13:15.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:13:15.22$vck44/vblo=3,649.99 2006.257.02:13:15.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.02:13:15.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.02:13:15.22#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:15.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:15.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:15.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:15.22#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:13:15.22#ibcon#first serial, iclass 7, count 0 2006.257.02:13:15.22#ibcon#enter sib2, iclass 7, count 0 2006.257.02:13:15.22#ibcon#flushed, iclass 7, count 0 2006.257.02:13:15.22#ibcon#about to write, iclass 7, count 0 2006.257.02:13:15.22#ibcon#wrote, iclass 7, count 0 2006.257.02:13:15.22#ibcon#about to read 3, iclass 7, count 0 2006.257.02:13:15.24#ibcon#read 3, iclass 7, count 0 2006.257.02:13:15.24#ibcon#about to read 4, iclass 7, count 0 2006.257.02:13:15.24#ibcon#read 4, iclass 7, count 0 2006.257.02:13:15.24#ibcon#about to read 5, iclass 7, count 0 2006.257.02:13:15.24#ibcon#read 5, iclass 7, count 0 2006.257.02:13:15.24#ibcon#about to read 6, iclass 7, count 0 2006.257.02:13:15.24#ibcon#read 6, iclass 7, count 0 2006.257.02:13:15.24#ibcon#end of sib2, iclass 7, count 0 2006.257.02:13:15.24#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:13:15.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:13:15.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:13:15.24#ibcon#*before write, iclass 7, count 0 2006.257.02:13:15.24#ibcon#enter sib2, iclass 7, count 0 2006.257.02:13:15.24#ibcon#flushed, iclass 7, count 0 2006.257.02:13:15.24#ibcon#about to write, iclass 7, count 0 2006.257.02:13:15.24#ibcon#wrote, iclass 7, count 0 2006.257.02:13:15.24#ibcon#about to read 3, iclass 7, count 0 2006.257.02:13:15.28#ibcon#read 3, iclass 7, count 0 2006.257.02:13:15.28#ibcon#about to read 4, iclass 7, count 0 2006.257.02:13:15.28#ibcon#read 4, iclass 7, count 0 2006.257.02:13:15.28#ibcon#about to read 5, iclass 7, count 0 2006.257.02:13:15.28#ibcon#read 5, iclass 7, count 0 2006.257.02:13:15.28#ibcon#about to read 6, iclass 7, count 0 2006.257.02:13:15.28#ibcon#read 6, iclass 7, count 0 2006.257.02:13:15.28#ibcon#end of sib2, iclass 7, count 0 2006.257.02:13:15.28#ibcon#*after write, iclass 7, count 0 2006.257.02:13:15.28#ibcon#*before return 0, iclass 7, count 0 2006.257.02:13:15.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:15.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:13:15.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:13:15.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:13:15.28$vck44/vb=3,4 2006.257.02:13:15.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.02:13:15.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.02:13:15.28#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:15.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:15.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:15.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:15.34#ibcon#enter wrdev, iclass 11, count 2 2006.257.02:13:15.34#ibcon#first serial, iclass 11, count 2 2006.257.02:13:15.34#ibcon#enter sib2, iclass 11, count 2 2006.257.02:13:15.34#ibcon#flushed, iclass 11, count 2 2006.257.02:13:15.34#ibcon#about to write, iclass 11, count 2 2006.257.02:13:15.34#ibcon#wrote, iclass 11, count 2 2006.257.02:13:15.34#ibcon#about to read 3, iclass 11, count 2 2006.257.02:13:15.36#ibcon#read 3, iclass 11, count 2 2006.257.02:13:15.36#ibcon#about to read 4, iclass 11, count 2 2006.257.02:13:15.36#ibcon#read 4, iclass 11, count 2 2006.257.02:13:15.36#ibcon#about to read 5, iclass 11, count 2 2006.257.02:13:15.36#ibcon#read 5, iclass 11, count 2 2006.257.02:13:15.36#ibcon#about to read 6, iclass 11, count 2 2006.257.02:13:15.36#ibcon#read 6, iclass 11, count 2 2006.257.02:13:15.36#ibcon#end of sib2, iclass 11, count 2 2006.257.02:13:15.36#ibcon#*mode == 0, iclass 11, count 2 2006.257.02:13:15.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.02:13:15.36#ibcon#[27=AT03-04\r\n] 2006.257.02:13:15.36#ibcon#*before write, iclass 11, count 2 2006.257.02:13:15.36#ibcon#enter sib2, iclass 11, count 2 2006.257.02:13:15.36#ibcon#flushed, iclass 11, count 2 2006.257.02:13:15.36#ibcon#about to write, iclass 11, count 2 2006.257.02:13:15.36#ibcon#wrote, iclass 11, count 2 2006.257.02:13:15.36#ibcon#about to read 3, iclass 11, count 2 2006.257.02:13:15.39#ibcon#read 3, iclass 11, count 2 2006.257.02:13:15.39#ibcon#about to read 4, iclass 11, count 2 2006.257.02:13:15.39#ibcon#read 4, iclass 11, count 2 2006.257.02:13:15.39#ibcon#about to read 5, iclass 11, count 2 2006.257.02:13:15.39#ibcon#read 5, iclass 11, count 2 2006.257.02:13:15.39#ibcon#about to read 6, iclass 11, count 2 2006.257.02:13:15.39#ibcon#read 6, iclass 11, count 2 2006.257.02:13:15.39#ibcon#end of sib2, iclass 11, count 2 2006.257.02:13:15.39#ibcon#*after write, iclass 11, count 2 2006.257.02:13:15.39#ibcon#*before return 0, iclass 11, count 2 2006.257.02:13:15.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:15.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:13:15.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.02:13:15.39#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:15.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:15.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:15.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:15.51#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:13:15.51#ibcon#first serial, iclass 11, count 0 2006.257.02:13:15.51#ibcon#enter sib2, iclass 11, count 0 2006.257.02:13:15.51#ibcon#flushed, iclass 11, count 0 2006.257.02:13:15.51#ibcon#about to write, iclass 11, count 0 2006.257.02:13:15.51#ibcon#wrote, iclass 11, count 0 2006.257.02:13:15.51#ibcon#about to read 3, iclass 11, count 0 2006.257.02:13:15.53#ibcon#read 3, iclass 11, count 0 2006.257.02:13:15.53#ibcon#about to read 4, iclass 11, count 0 2006.257.02:13:15.53#ibcon#read 4, iclass 11, count 0 2006.257.02:13:15.53#ibcon#about to read 5, iclass 11, count 0 2006.257.02:13:15.53#ibcon#read 5, iclass 11, count 0 2006.257.02:13:15.53#ibcon#about to read 6, iclass 11, count 0 2006.257.02:13:15.53#ibcon#read 6, iclass 11, count 0 2006.257.02:13:15.53#ibcon#end of sib2, iclass 11, count 0 2006.257.02:13:15.53#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:13:15.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:13:15.53#ibcon#[27=USB\r\n] 2006.257.02:13:15.53#ibcon#*before write, iclass 11, count 0 2006.257.02:13:15.53#ibcon#enter sib2, iclass 11, count 0 2006.257.02:13:15.53#ibcon#flushed, iclass 11, count 0 2006.257.02:13:15.53#ibcon#about to write, iclass 11, count 0 2006.257.02:13:15.53#ibcon#wrote, iclass 11, count 0 2006.257.02:13:15.53#ibcon#about to read 3, iclass 11, count 0 2006.257.02:13:15.56#ibcon#read 3, iclass 11, count 0 2006.257.02:13:15.56#ibcon#about to read 4, iclass 11, count 0 2006.257.02:13:15.56#ibcon#read 4, iclass 11, count 0 2006.257.02:13:15.56#ibcon#about to read 5, iclass 11, count 0 2006.257.02:13:15.56#ibcon#read 5, iclass 11, count 0 2006.257.02:13:15.56#ibcon#about to read 6, iclass 11, count 0 2006.257.02:13:15.56#ibcon#read 6, iclass 11, count 0 2006.257.02:13:15.56#ibcon#end of sib2, iclass 11, count 0 2006.257.02:13:15.56#ibcon#*after write, iclass 11, count 0 2006.257.02:13:15.56#ibcon#*before return 0, iclass 11, count 0 2006.257.02:13:15.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:15.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:13:15.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:13:15.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:13:15.56$vck44/vblo=4,679.99 2006.257.02:13:15.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.02:13:15.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.02:13:15.56#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:15.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:15.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:15.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:15.56#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:13:15.56#ibcon#first serial, iclass 13, count 0 2006.257.02:13:15.56#ibcon#enter sib2, iclass 13, count 0 2006.257.02:13:15.56#ibcon#flushed, iclass 13, count 0 2006.257.02:13:15.56#ibcon#about to write, iclass 13, count 0 2006.257.02:13:15.56#ibcon#wrote, iclass 13, count 0 2006.257.02:13:15.56#ibcon#about to read 3, iclass 13, count 0 2006.257.02:13:15.58#ibcon#read 3, iclass 13, count 0 2006.257.02:13:15.58#ibcon#about to read 4, iclass 13, count 0 2006.257.02:13:15.58#ibcon#read 4, iclass 13, count 0 2006.257.02:13:15.58#ibcon#about to read 5, iclass 13, count 0 2006.257.02:13:15.58#ibcon#read 5, iclass 13, count 0 2006.257.02:13:15.58#ibcon#about to read 6, iclass 13, count 0 2006.257.02:13:15.58#ibcon#read 6, iclass 13, count 0 2006.257.02:13:15.58#ibcon#end of sib2, iclass 13, count 0 2006.257.02:13:15.58#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:13:15.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:13:15.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:13:15.58#ibcon#*before write, iclass 13, count 0 2006.257.02:13:15.58#ibcon#enter sib2, iclass 13, count 0 2006.257.02:13:15.58#ibcon#flushed, iclass 13, count 0 2006.257.02:13:15.58#ibcon#about to write, iclass 13, count 0 2006.257.02:13:15.58#ibcon#wrote, iclass 13, count 0 2006.257.02:13:15.58#ibcon#about to read 3, iclass 13, count 0 2006.257.02:13:15.62#ibcon#read 3, iclass 13, count 0 2006.257.02:13:15.62#ibcon#about to read 4, iclass 13, count 0 2006.257.02:13:15.62#ibcon#read 4, iclass 13, count 0 2006.257.02:13:15.62#ibcon#about to read 5, iclass 13, count 0 2006.257.02:13:15.62#ibcon#read 5, iclass 13, count 0 2006.257.02:13:15.62#ibcon#about to read 6, iclass 13, count 0 2006.257.02:13:15.62#ibcon#read 6, iclass 13, count 0 2006.257.02:13:15.62#ibcon#end of sib2, iclass 13, count 0 2006.257.02:13:15.62#ibcon#*after write, iclass 13, count 0 2006.257.02:13:15.62#ibcon#*before return 0, iclass 13, count 0 2006.257.02:13:15.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:15.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:13:15.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:13:15.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:13:15.62$vck44/vb=4,5 2006.257.02:13:15.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.02:13:15.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.02:13:15.62#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:15.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:15.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:15.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:15.68#ibcon#enter wrdev, iclass 15, count 2 2006.257.02:13:15.68#ibcon#first serial, iclass 15, count 2 2006.257.02:13:15.68#ibcon#enter sib2, iclass 15, count 2 2006.257.02:13:15.68#ibcon#flushed, iclass 15, count 2 2006.257.02:13:15.68#ibcon#about to write, iclass 15, count 2 2006.257.02:13:15.68#ibcon#wrote, iclass 15, count 2 2006.257.02:13:15.68#ibcon#about to read 3, iclass 15, count 2 2006.257.02:13:15.70#ibcon#read 3, iclass 15, count 2 2006.257.02:13:15.70#ibcon#about to read 4, iclass 15, count 2 2006.257.02:13:15.70#ibcon#read 4, iclass 15, count 2 2006.257.02:13:15.70#ibcon#about to read 5, iclass 15, count 2 2006.257.02:13:15.70#ibcon#read 5, iclass 15, count 2 2006.257.02:13:15.70#ibcon#about to read 6, iclass 15, count 2 2006.257.02:13:15.70#ibcon#read 6, iclass 15, count 2 2006.257.02:13:15.70#ibcon#end of sib2, iclass 15, count 2 2006.257.02:13:15.70#ibcon#*mode == 0, iclass 15, count 2 2006.257.02:13:15.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.02:13:15.70#ibcon#[27=AT04-05\r\n] 2006.257.02:13:15.70#ibcon#*before write, iclass 15, count 2 2006.257.02:13:15.70#ibcon#enter sib2, iclass 15, count 2 2006.257.02:13:15.70#ibcon#flushed, iclass 15, count 2 2006.257.02:13:15.70#ibcon#about to write, iclass 15, count 2 2006.257.02:13:15.70#ibcon#wrote, iclass 15, count 2 2006.257.02:13:15.70#ibcon#about to read 3, iclass 15, count 2 2006.257.02:13:15.73#ibcon#read 3, iclass 15, count 2 2006.257.02:13:15.73#ibcon#about to read 4, iclass 15, count 2 2006.257.02:13:15.73#ibcon#read 4, iclass 15, count 2 2006.257.02:13:15.73#ibcon#about to read 5, iclass 15, count 2 2006.257.02:13:15.73#ibcon#read 5, iclass 15, count 2 2006.257.02:13:15.73#ibcon#about to read 6, iclass 15, count 2 2006.257.02:13:15.73#ibcon#read 6, iclass 15, count 2 2006.257.02:13:15.73#ibcon#end of sib2, iclass 15, count 2 2006.257.02:13:15.73#ibcon#*after write, iclass 15, count 2 2006.257.02:13:15.73#ibcon#*before return 0, iclass 15, count 2 2006.257.02:13:15.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:15.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:13:15.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.02:13:15.73#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:15.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:15.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:15.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:15.85#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:13:15.85#ibcon#first serial, iclass 15, count 0 2006.257.02:13:15.85#ibcon#enter sib2, iclass 15, count 0 2006.257.02:13:15.85#ibcon#flushed, iclass 15, count 0 2006.257.02:13:15.85#ibcon#about to write, iclass 15, count 0 2006.257.02:13:15.85#ibcon#wrote, iclass 15, count 0 2006.257.02:13:15.85#ibcon#about to read 3, iclass 15, count 0 2006.257.02:13:15.87#ibcon#read 3, iclass 15, count 0 2006.257.02:13:15.87#ibcon#about to read 4, iclass 15, count 0 2006.257.02:13:15.87#ibcon#read 4, iclass 15, count 0 2006.257.02:13:15.87#ibcon#about to read 5, iclass 15, count 0 2006.257.02:13:15.87#ibcon#read 5, iclass 15, count 0 2006.257.02:13:15.87#ibcon#about to read 6, iclass 15, count 0 2006.257.02:13:15.87#ibcon#read 6, iclass 15, count 0 2006.257.02:13:15.87#ibcon#end of sib2, iclass 15, count 0 2006.257.02:13:15.87#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:13:15.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:13:15.87#ibcon#[27=USB\r\n] 2006.257.02:13:15.87#ibcon#*before write, iclass 15, count 0 2006.257.02:13:15.87#ibcon#enter sib2, iclass 15, count 0 2006.257.02:13:15.87#ibcon#flushed, iclass 15, count 0 2006.257.02:13:15.87#ibcon#about to write, iclass 15, count 0 2006.257.02:13:15.87#ibcon#wrote, iclass 15, count 0 2006.257.02:13:15.87#ibcon#about to read 3, iclass 15, count 0 2006.257.02:13:15.90#ibcon#read 3, iclass 15, count 0 2006.257.02:13:15.90#ibcon#about to read 4, iclass 15, count 0 2006.257.02:13:15.90#ibcon#read 4, iclass 15, count 0 2006.257.02:13:15.90#ibcon#about to read 5, iclass 15, count 0 2006.257.02:13:15.90#ibcon#read 5, iclass 15, count 0 2006.257.02:13:15.90#ibcon#about to read 6, iclass 15, count 0 2006.257.02:13:15.90#ibcon#read 6, iclass 15, count 0 2006.257.02:13:15.90#ibcon#end of sib2, iclass 15, count 0 2006.257.02:13:15.90#ibcon#*after write, iclass 15, count 0 2006.257.02:13:15.90#ibcon#*before return 0, iclass 15, count 0 2006.257.02:13:15.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:15.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:13:15.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:13:15.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:13:15.90$vck44/vblo=5,709.99 2006.257.02:13:15.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.02:13:15.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.02:13:15.90#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:15.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:15.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:15.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:15.90#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:13:15.90#ibcon#first serial, iclass 17, count 0 2006.257.02:13:15.90#ibcon#enter sib2, iclass 17, count 0 2006.257.02:13:15.90#ibcon#flushed, iclass 17, count 0 2006.257.02:13:15.90#ibcon#about to write, iclass 17, count 0 2006.257.02:13:15.90#ibcon#wrote, iclass 17, count 0 2006.257.02:13:15.90#ibcon#about to read 3, iclass 17, count 0 2006.257.02:13:15.92#ibcon#read 3, iclass 17, count 0 2006.257.02:13:15.92#ibcon#about to read 4, iclass 17, count 0 2006.257.02:13:15.92#ibcon#read 4, iclass 17, count 0 2006.257.02:13:15.92#ibcon#about to read 5, iclass 17, count 0 2006.257.02:13:15.92#ibcon#read 5, iclass 17, count 0 2006.257.02:13:15.92#ibcon#about to read 6, iclass 17, count 0 2006.257.02:13:15.92#ibcon#read 6, iclass 17, count 0 2006.257.02:13:15.92#ibcon#end of sib2, iclass 17, count 0 2006.257.02:13:15.92#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:13:15.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:13:15.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:13:15.92#ibcon#*before write, iclass 17, count 0 2006.257.02:13:15.92#ibcon#enter sib2, iclass 17, count 0 2006.257.02:13:15.92#ibcon#flushed, iclass 17, count 0 2006.257.02:13:15.92#ibcon#about to write, iclass 17, count 0 2006.257.02:13:15.92#ibcon#wrote, iclass 17, count 0 2006.257.02:13:15.92#ibcon#about to read 3, iclass 17, count 0 2006.257.02:13:15.96#ibcon#read 3, iclass 17, count 0 2006.257.02:13:15.96#ibcon#about to read 4, iclass 17, count 0 2006.257.02:13:15.96#ibcon#read 4, iclass 17, count 0 2006.257.02:13:15.96#ibcon#about to read 5, iclass 17, count 0 2006.257.02:13:15.96#ibcon#read 5, iclass 17, count 0 2006.257.02:13:15.96#ibcon#about to read 6, iclass 17, count 0 2006.257.02:13:15.96#ibcon#read 6, iclass 17, count 0 2006.257.02:13:15.96#ibcon#end of sib2, iclass 17, count 0 2006.257.02:13:15.96#ibcon#*after write, iclass 17, count 0 2006.257.02:13:15.96#ibcon#*before return 0, iclass 17, count 0 2006.257.02:13:15.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:15.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:13:15.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:13:15.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:13:15.96$vck44/vb=5,4 2006.257.02:13:15.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.02:13:15.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.02:13:15.96#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:15.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:16.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:16.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:16.02#ibcon#enter wrdev, iclass 19, count 2 2006.257.02:13:16.02#ibcon#first serial, iclass 19, count 2 2006.257.02:13:16.02#ibcon#enter sib2, iclass 19, count 2 2006.257.02:13:16.02#ibcon#flushed, iclass 19, count 2 2006.257.02:13:16.02#ibcon#about to write, iclass 19, count 2 2006.257.02:13:16.02#ibcon#wrote, iclass 19, count 2 2006.257.02:13:16.02#ibcon#about to read 3, iclass 19, count 2 2006.257.02:13:16.04#ibcon#read 3, iclass 19, count 2 2006.257.02:13:16.04#ibcon#about to read 4, iclass 19, count 2 2006.257.02:13:16.04#ibcon#read 4, iclass 19, count 2 2006.257.02:13:16.04#ibcon#about to read 5, iclass 19, count 2 2006.257.02:13:16.04#ibcon#read 5, iclass 19, count 2 2006.257.02:13:16.04#ibcon#about to read 6, iclass 19, count 2 2006.257.02:13:16.04#ibcon#read 6, iclass 19, count 2 2006.257.02:13:16.04#ibcon#end of sib2, iclass 19, count 2 2006.257.02:13:16.04#ibcon#*mode == 0, iclass 19, count 2 2006.257.02:13:16.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.02:13:16.04#ibcon#[27=AT05-04\r\n] 2006.257.02:13:16.04#ibcon#*before write, iclass 19, count 2 2006.257.02:13:16.04#ibcon#enter sib2, iclass 19, count 2 2006.257.02:13:16.04#ibcon#flushed, iclass 19, count 2 2006.257.02:13:16.04#ibcon#about to write, iclass 19, count 2 2006.257.02:13:16.04#ibcon#wrote, iclass 19, count 2 2006.257.02:13:16.04#ibcon#about to read 3, iclass 19, count 2 2006.257.02:13:16.07#ibcon#read 3, iclass 19, count 2 2006.257.02:13:16.07#ibcon#about to read 4, iclass 19, count 2 2006.257.02:13:16.07#ibcon#read 4, iclass 19, count 2 2006.257.02:13:16.07#ibcon#about to read 5, iclass 19, count 2 2006.257.02:13:16.07#ibcon#read 5, iclass 19, count 2 2006.257.02:13:16.07#ibcon#about to read 6, iclass 19, count 2 2006.257.02:13:16.07#ibcon#read 6, iclass 19, count 2 2006.257.02:13:16.07#ibcon#end of sib2, iclass 19, count 2 2006.257.02:13:16.07#ibcon#*after write, iclass 19, count 2 2006.257.02:13:16.07#ibcon#*before return 0, iclass 19, count 2 2006.257.02:13:16.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:16.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:13:16.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.02:13:16.07#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:16.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:16.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:16.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:16.19#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:13:16.19#ibcon#first serial, iclass 19, count 0 2006.257.02:13:16.19#ibcon#enter sib2, iclass 19, count 0 2006.257.02:13:16.19#ibcon#flushed, iclass 19, count 0 2006.257.02:13:16.19#ibcon#about to write, iclass 19, count 0 2006.257.02:13:16.19#ibcon#wrote, iclass 19, count 0 2006.257.02:13:16.19#ibcon#about to read 3, iclass 19, count 0 2006.257.02:13:16.21#ibcon#read 3, iclass 19, count 0 2006.257.02:13:16.21#ibcon#about to read 4, iclass 19, count 0 2006.257.02:13:16.21#ibcon#read 4, iclass 19, count 0 2006.257.02:13:16.21#ibcon#about to read 5, iclass 19, count 0 2006.257.02:13:16.21#ibcon#read 5, iclass 19, count 0 2006.257.02:13:16.21#ibcon#about to read 6, iclass 19, count 0 2006.257.02:13:16.21#ibcon#read 6, iclass 19, count 0 2006.257.02:13:16.21#ibcon#end of sib2, iclass 19, count 0 2006.257.02:13:16.21#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:13:16.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:13:16.21#ibcon#[27=USB\r\n] 2006.257.02:13:16.21#ibcon#*before write, iclass 19, count 0 2006.257.02:13:16.21#ibcon#enter sib2, iclass 19, count 0 2006.257.02:13:16.21#ibcon#flushed, iclass 19, count 0 2006.257.02:13:16.21#ibcon#about to write, iclass 19, count 0 2006.257.02:13:16.21#ibcon#wrote, iclass 19, count 0 2006.257.02:13:16.21#ibcon#about to read 3, iclass 19, count 0 2006.257.02:13:16.24#ibcon#read 3, iclass 19, count 0 2006.257.02:13:16.24#ibcon#about to read 4, iclass 19, count 0 2006.257.02:13:16.24#ibcon#read 4, iclass 19, count 0 2006.257.02:13:16.24#ibcon#about to read 5, iclass 19, count 0 2006.257.02:13:16.24#ibcon#read 5, iclass 19, count 0 2006.257.02:13:16.24#ibcon#about to read 6, iclass 19, count 0 2006.257.02:13:16.24#ibcon#read 6, iclass 19, count 0 2006.257.02:13:16.24#ibcon#end of sib2, iclass 19, count 0 2006.257.02:13:16.24#ibcon#*after write, iclass 19, count 0 2006.257.02:13:16.24#ibcon#*before return 0, iclass 19, count 0 2006.257.02:13:16.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:16.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:13:16.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:13:16.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:13:16.24$vck44/vblo=6,719.99 2006.257.02:13:16.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.02:13:16.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.02:13:16.24#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:16.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:16.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:16.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:16.24#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:13:16.24#ibcon#first serial, iclass 21, count 0 2006.257.02:13:16.24#ibcon#enter sib2, iclass 21, count 0 2006.257.02:13:16.24#ibcon#flushed, iclass 21, count 0 2006.257.02:13:16.24#ibcon#about to write, iclass 21, count 0 2006.257.02:13:16.24#ibcon#wrote, iclass 21, count 0 2006.257.02:13:16.24#ibcon#about to read 3, iclass 21, count 0 2006.257.02:13:16.26#ibcon#read 3, iclass 21, count 0 2006.257.02:13:16.26#ibcon#about to read 4, iclass 21, count 0 2006.257.02:13:16.26#ibcon#read 4, iclass 21, count 0 2006.257.02:13:16.26#ibcon#about to read 5, iclass 21, count 0 2006.257.02:13:16.26#ibcon#read 5, iclass 21, count 0 2006.257.02:13:16.26#ibcon#about to read 6, iclass 21, count 0 2006.257.02:13:16.26#ibcon#read 6, iclass 21, count 0 2006.257.02:13:16.26#ibcon#end of sib2, iclass 21, count 0 2006.257.02:13:16.26#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:13:16.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:13:16.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:13:16.26#ibcon#*before write, iclass 21, count 0 2006.257.02:13:16.26#ibcon#enter sib2, iclass 21, count 0 2006.257.02:13:16.26#ibcon#flushed, iclass 21, count 0 2006.257.02:13:16.26#ibcon#about to write, iclass 21, count 0 2006.257.02:13:16.26#ibcon#wrote, iclass 21, count 0 2006.257.02:13:16.26#ibcon#about to read 3, iclass 21, count 0 2006.257.02:13:16.30#ibcon#read 3, iclass 21, count 0 2006.257.02:13:16.30#ibcon#about to read 4, iclass 21, count 0 2006.257.02:13:16.30#ibcon#read 4, iclass 21, count 0 2006.257.02:13:16.30#ibcon#about to read 5, iclass 21, count 0 2006.257.02:13:16.30#ibcon#read 5, iclass 21, count 0 2006.257.02:13:16.30#ibcon#about to read 6, iclass 21, count 0 2006.257.02:13:16.30#ibcon#read 6, iclass 21, count 0 2006.257.02:13:16.30#ibcon#end of sib2, iclass 21, count 0 2006.257.02:13:16.30#ibcon#*after write, iclass 21, count 0 2006.257.02:13:16.30#ibcon#*before return 0, iclass 21, count 0 2006.257.02:13:16.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:16.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:13:16.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:13:16.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:13:16.30$vck44/vb=6,4 2006.257.02:13:16.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.02:13:16.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.02:13:16.30#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:16.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:16.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:16.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:16.36#ibcon#enter wrdev, iclass 23, count 2 2006.257.02:13:16.36#ibcon#first serial, iclass 23, count 2 2006.257.02:13:16.36#ibcon#enter sib2, iclass 23, count 2 2006.257.02:13:16.36#ibcon#flushed, iclass 23, count 2 2006.257.02:13:16.36#ibcon#about to write, iclass 23, count 2 2006.257.02:13:16.36#ibcon#wrote, iclass 23, count 2 2006.257.02:13:16.36#ibcon#about to read 3, iclass 23, count 2 2006.257.02:13:16.38#ibcon#read 3, iclass 23, count 2 2006.257.02:13:16.38#ibcon#about to read 4, iclass 23, count 2 2006.257.02:13:16.38#ibcon#read 4, iclass 23, count 2 2006.257.02:13:16.38#ibcon#about to read 5, iclass 23, count 2 2006.257.02:13:16.38#ibcon#read 5, iclass 23, count 2 2006.257.02:13:16.38#ibcon#about to read 6, iclass 23, count 2 2006.257.02:13:16.38#ibcon#read 6, iclass 23, count 2 2006.257.02:13:16.38#ibcon#end of sib2, iclass 23, count 2 2006.257.02:13:16.38#ibcon#*mode == 0, iclass 23, count 2 2006.257.02:13:16.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.02:13:16.38#ibcon#[27=AT06-04\r\n] 2006.257.02:13:16.38#ibcon#*before write, iclass 23, count 2 2006.257.02:13:16.38#ibcon#enter sib2, iclass 23, count 2 2006.257.02:13:16.38#ibcon#flushed, iclass 23, count 2 2006.257.02:13:16.38#ibcon#about to write, iclass 23, count 2 2006.257.02:13:16.38#ibcon#wrote, iclass 23, count 2 2006.257.02:13:16.38#ibcon#about to read 3, iclass 23, count 2 2006.257.02:13:16.41#ibcon#read 3, iclass 23, count 2 2006.257.02:13:16.41#ibcon#about to read 4, iclass 23, count 2 2006.257.02:13:16.41#ibcon#read 4, iclass 23, count 2 2006.257.02:13:16.41#ibcon#about to read 5, iclass 23, count 2 2006.257.02:13:16.41#ibcon#read 5, iclass 23, count 2 2006.257.02:13:16.41#ibcon#about to read 6, iclass 23, count 2 2006.257.02:13:16.41#ibcon#read 6, iclass 23, count 2 2006.257.02:13:16.41#ibcon#end of sib2, iclass 23, count 2 2006.257.02:13:16.41#ibcon#*after write, iclass 23, count 2 2006.257.02:13:16.41#ibcon#*before return 0, iclass 23, count 2 2006.257.02:13:16.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:16.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:13:16.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.02:13:16.41#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:16.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:16.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:16.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:16.53#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:13:16.53#ibcon#first serial, iclass 23, count 0 2006.257.02:13:16.53#ibcon#enter sib2, iclass 23, count 0 2006.257.02:13:16.53#ibcon#flushed, iclass 23, count 0 2006.257.02:13:16.53#ibcon#about to write, iclass 23, count 0 2006.257.02:13:16.53#ibcon#wrote, iclass 23, count 0 2006.257.02:13:16.53#ibcon#about to read 3, iclass 23, count 0 2006.257.02:13:16.55#ibcon#read 3, iclass 23, count 0 2006.257.02:13:16.55#ibcon#about to read 4, iclass 23, count 0 2006.257.02:13:16.55#ibcon#read 4, iclass 23, count 0 2006.257.02:13:16.55#ibcon#about to read 5, iclass 23, count 0 2006.257.02:13:16.55#ibcon#read 5, iclass 23, count 0 2006.257.02:13:16.55#ibcon#about to read 6, iclass 23, count 0 2006.257.02:13:16.55#ibcon#read 6, iclass 23, count 0 2006.257.02:13:16.55#ibcon#end of sib2, iclass 23, count 0 2006.257.02:13:16.55#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:13:16.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:13:16.55#ibcon#[27=USB\r\n] 2006.257.02:13:16.55#ibcon#*before write, iclass 23, count 0 2006.257.02:13:16.55#ibcon#enter sib2, iclass 23, count 0 2006.257.02:13:16.55#ibcon#flushed, iclass 23, count 0 2006.257.02:13:16.55#ibcon#about to write, iclass 23, count 0 2006.257.02:13:16.55#ibcon#wrote, iclass 23, count 0 2006.257.02:13:16.55#ibcon#about to read 3, iclass 23, count 0 2006.257.02:13:16.58#ibcon#read 3, iclass 23, count 0 2006.257.02:13:16.58#ibcon#about to read 4, iclass 23, count 0 2006.257.02:13:16.58#ibcon#read 4, iclass 23, count 0 2006.257.02:13:16.58#ibcon#about to read 5, iclass 23, count 0 2006.257.02:13:16.58#ibcon#read 5, iclass 23, count 0 2006.257.02:13:16.58#ibcon#about to read 6, iclass 23, count 0 2006.257.02:13:16.58#ibcon#read 6, iclass 23, count 0 2006.257.02:13:16.58#ibcon#end of sib2, iclass 23, count 0 2006.257.02:13:16.58#ibcon#*after write, iclass 23, count 0 2006.257.02:13:16.58#ibcon#*before return 0, iclass 23, count 0 2006.257.02:13:16.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:16.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:13:16.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:13:16.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:13:16.58$vck44/vblo=7,734.99 2006.257.02:13:16.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.02:13:16.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.02:13:16.58#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:16.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:16.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:16.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:16.58#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:13:16.58#ibcon#first serial, iclass 25, count 0 2006.257.02:13:16.58#ibcon#enter sib2, iclass 25, count 0 2006.257.02:13:16.58#ibcon#flushed, iclass 25, count 0 2006.257.02:13:16.58#ibcon#about to write, iclass 25, count 0 2006.257.02:13:16.58#ibcon#wrote, iclass 25, count 0 2006.257.02:13:16.58#ibcon#about to read 3, iclass 25, count 0 2006.257.02:13:16.60#ibcon#read 3, iclass 25, count 0 2006.257.02:13:16.60#ibcon#about to read 4, iclass 25, count 0 2006.257.02:13:16.60#ibcon#read 4, iclass 25, count 0 2006.257.02:13:16.60#ibcon#about to read 5, iclass 25, count 0 2006.257.02:13:16.60#ibcon#read 5, iclass 25, count 0 2006.257.02:13:16.60#ibcon#about to read 6, iclass 25, count 0 2006.257.02:13:16.60#ibcon#read 6, iclass 25, count 0 2006.257.02:13:16.60#ibcon#end of sib2, iclass 25, count 0 2006.257.02:13:16.60#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:13:16.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:13:16.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:13:16.60#ibcon#*before write, iclass 25, count 0 2006.257.02:13:16.60#ibcon#enter sib2, iclass 25, count 0 2006.257.02:13:16.60#ibcon#flushed, iclass 25, count 0 2006.257.02:13:16.60#ibcon#about to write, iclass 25, count 0 2006.257.02:13:16.60#ibcon#wrote, iclass 25, count 0 2006.257.02:13:16.60#ibcon#about to read 3, iclass 25, count 0 2006.257.02:13:16.64#ibcon#read 3, iclass 25, count 0 2006.257.02:13:16.64#ibcon#about to read 4, iclass 25, count 0 2006.257.02:13:16.64#ibcon#read 4, iclass 25, count 0 2006.257.02:13:16.64#ibcon#about to read 5, iclass 25, count 0 2006.257.02:13:16.64#ibcon#read 5, iclass 25, count 0 2006.257.02:13:16.64#ibcon#about to read 6, iclass 25, count 0 2006.257.02:13:16.64#ibcon#read 6, iclass 25, count 0 2006.257.02:13:16.64#ibcon#end of sib2, iclass 25, count 0 2006.257.02:13:16.64#ibcon#*after write, iclass 25, count 0 2006.257.02:13:16.64#ibcon#*before return 0, iclass 25, count 0 2006.257.02:13:16.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:16.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:13:16.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:13:16.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:13:16.64$vck44/vb=7,4 2006.257.02:13:16.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.02:13:16.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.02:13:16.64#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:16.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:16.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:16.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:16.70#ibcon#enter wrdev, iclass 27, count 2 2006.257.02:13:16.70#ibcon#first serial, iclass 27, count 2 2006.257.02:13:16.70#ibcon#enter sib2, iclass 27, count 2 2006.257.02:13:16.70#ibcon#flushed, iclass 27, count 2 2006.257.02:13:16.70#ibcon#about to write, iclass 27, count 2 2006.257.02:13:16.70#ibcon#wrote, iclass 27, count 2 2006.257.02:13:16.70#ibcon#about to read 3, iclass 27, count 2 2006.257.02:13:16.72#ibcon#read 3, iclass 27, count 2 2006.257.02:13:16.72#ibcon#about to read 4, iclass 27, count 2 2006.257.02:13:16.72#ibcon#read 4, iclass 27, count 2 2006.257.02:13:16.72#ibcon#about to read 5, iclass 27, count 2 2006.257.02:13:16.72#ibcon#read 5, iclass 27, count 2 2006.257.02:13:16.72#ibcon#about to read 6, iclass 27, count 2 2006.257.02:13:16.72#ibcon#read 6, iclass 27, count 2 2006.257.02:13:16.72#ibcon#end of sib2, iclass 27, count 2 2006.257.02:13:16.72#ibcon#*mode == 0, iclass 27, count 2 2006.257.02:13:16.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.02:13:16.72#ibcon#[27=AT07-04\r\n] 2006.257.02:13:16.72#ibcon#*before write, iclass 27, count 2 2006.257.02:13:16.72#ibcon#enter sib2, iclass 27, count 2 2006.257.02:13:16.72#ibcon#flushed, iclass 27, count 2 2006.257.02:13:16.72#ibcon#about to write, iclass 27, count 2 2006.257.02:13:16.72#ibcon#wrote, iclass 27, count 2 2006.257.02:13:16.72#ibcon#about to read 3, iclass 27, count 2 2006.257.02:13:16.75#ibcon#read 3, iclass 27, count 2 2006.257.02:13:16.75#ibcon#about to read 4, iclass 27, count 2 2006.257.02:13:16.75#ibcon#read 4, iclass 27, count 2 2006.257.02:13:16.75#ibcon#about to read 5, iclass 27, count 2 2006.257.02:13:16.75#ibcon#read 5, iclass 27, count 2 2006.257.02:13:16.75#ibcon#about to read 6, iclass 27, count 2 2006.257.02:13:16.75#ibcon#read 6, iclass 27, count 2 2006.257.02:13:16.75#ibcon#end of sib2, iclass 27, count 2 2006.257.02:13:16.75#ibcon#*after write, iclass 27, count 2 2006.257.02:13:16.75#ibcon#*before return 0, iclass 27, count 2 2006.257.02:13:16.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:16.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:13:16.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.02:13:16.75#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:16.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:16.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:16.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:16.87#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:13:16.87#ibcon#first serial, iclass 27, count 0 2006.257.02:13:16.87#ibcon#enter sib2, iclass 27, count 0 2006.257.02:13:16.87#ibcon#flushed, iclass 27, count 0 2006.257.02:13:16.87#ibcon#about to write, iclass 27, count 0 2006.257.02:13:16.87#ibcon#wrote, iclass 27, count 0 2006.257.02:13:16.87#ibcon#about to read 3, iclass 27, count 0 2006.257.02:13:16.89#ibcon#read 3, iclass 27, count 0 2006.257.02:13:16.89#ibcon#about to read 4, iclass 27, count 0 2006.257.02:13:16.89#ibcon#read 4, iclass 27, count 0 2006.257.02:13:16.89#ibcon#about to read 5, iclass 27, count 0 2006.257.02:13:16.89#ibcon#read 5, iclass 27, count 0 2006.257.02:13:16.89#ibcon#about to read 6, iclass 27, count 0 2006.257.02:13:16.89#ibcon#read 6, iclass 27, count 0 2006.257.02:13:16.89#ibcon#end of sib2, iclass 27, count 0 2006.257.02:13:16.89#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:13:16.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:13:16.89#ibcon#[27=USB\r\n] 2006.257.02:13:16.89#ibcon#*before write, iclass 27, count 0 2006.257.02:13:16.89#ibcon#enter sib2, iclass 27, count 0 2006.257.02:13:16.89#ibcon#flushed, iclass 27, count 0 2006.257.02:13:16.89#ibcon#about to write, iclass 27, count 0 2006.257.02:13:16.89#ibcon#wrote, iclass 27, count 0 2006.257.02:13:16.89#ibcon#about to read 3, iclass 27, count 0 2006.257.02:13:16.92#ibcon#read 3, iclass 27, count 0 2006.257.02:13:16.92#ibcon#about to read 4, iclass 27, count 0 2006.257.02:13:16.92#ibcon#read 4, iclass 27, count 0 2006.257.02:13:16.92#ibcon#about to read 5, iclass 27, count 0 2006.257.02:13:16.92#ibcon#read 5, iclass 27, count 0 2006.257.02:13:16.92#ibcon#about to read 6, iclass 27, count 0 2006.257.02:13:16.92#ibcon#read 6, iclass 27, count 0 2006.257.02:13:16.92#ibcon#end of sib2, iclass 27, count 0 2006.257.02:13:16.92#ibcon#*after write, iclass 27, count 0 2006.257.02:13:16.92#ibcon#*before return 0, iclass 27, count 0 2006.257.02:13:16.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:16.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:13:16.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:13:16.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:13:16.92$vck44/vblo=8,744.99 2006.257.02:13:16.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.02:13:16.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.02:13:16.92#ibcon#ireg 17 cls_cnt 0 2006.257.02:13:16.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:16.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:16.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:16.92#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:13:16.92#ibcon#first serial, iclass 29, count 0 2006.257.02:13:16.92#ibcon#enter sib2, iclass 29, count 0 2006.257.02:13:16.92#ibcon#flushed, iclass 29, count 0 2006.257.02:13:16.92#ibcon#about to write, iclass 29, count 0 2006.257.02:13:16.92#ibcon#wrote, iclass 29, count 0 2006.257.02:13:16.92#ibcon#about to read 3, iclass 29, count 0 2006.257.02:13:16.94#ibcon#read 3, iclass 29, count 0 2006.257.02:13:16.94#ibcon#about to read 4, iclass 29, count 0 2006.257.02:13:16.94#ibcon#read 4, iclass 29, count 0 2006.257.02:13:16.94#ibcon#about to read 5, iclass 29, count 0 2006.257.02:13:16.94#ibcon#read 5, iclass 29, count 0 2006.257.02:13:16.94#ibcon#about to read 6, iclass 29, count 0 2006.257.02:13:16.94#ibcon#read 6, iclass 29, count 0 2006.257.02:13:16.94#ibcon#end of sib2, iclass 29, count 0 2006.257.02:13:16.94#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:13:16.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:13:16.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:13:16.94#ibcon#*before write, iclass 29, count 0 2006.257.02:13:16.94#ibcon#enter sib2, iclass 29, count 0 2006.257.02:13:16.94#ibcon#flushed, iclass 29, count 0 2006.257.02:13:16.94#ibcon#about to write, iclass 29, count 0 2006.257.02:13:16.94#ibcon#wrote, iclass 29, count 0 2006.257.02:13:16.94#ibcon#about to read 3, iclass 29, count 0 2006.257.02:13:16.98#ibcon#read 3, iclass 29, count 0 2006.257.02:13:16.98#ibcon#about to read 4, iclass 29, count 0 2006.257.02:13:16.98#ibcon#read 4, iclass 29, count 0 2006.257.02:13:16.98#ibcon#about to read 5, iclass 29, count 0 2006.257.02:13:16.98#ibcon#read 5, iclass 29, count 0 2006.257.02:13:16.98#ibcon#about to read 6, iclass 29, count 0 2006.257.02:13:16.98#ibcon#read 6, iclass 29, count 0 2006.257.02:13:16.98#ibcon#end of sib2, iclass 29, count 0 2006.257.02:13:16.98#ibcon#*after write, iclass 29, count 0 2006.257.02:13:16.98#ibcon#*before return 0, iclass 29, count 0 2006.257.02:13:16.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:16.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:13:16.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:13:16.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:13:16.98$vck44/vb=8,4 2006.257.02:13:16.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.02:13:16.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.02:13:16.98#ibcon#ireg 11 cls_cnt 2 2006.257.02:13:16.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:17.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:17.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:17.04#ibcon#enter wrdev, iclass 31, count 2 2006.257.02:13:17.04#ibcon#first serial, iclass 31, count 2 2006.257.02:13:17.04#ibcon#enter sib2, iclass 31, count 2 2006.257.02:13:17.04#ibcon#flushed, iclass 31, count 2 2006.257.02:13:17.04#ibcon#about to write, iclass 31, count 2 2006.257.02:13:17.04#ibcon#wrote, iclass 31, count 2 2006.257.02:13:17.04#ibcon#about to read 3, iclass 31, count 2 2006.257.02:13:17.06#ibcon#read 3, iclass 31, count 2 2006.257.02:13:17.06#ibcon#about to read 4, iclass 31, count 2 2006.257.02:13:17.06#ibcon#read 4, iclass 31, count 2 2006.257.02:13:17.06#ibcon#about to read 5, iclass 31, count 2 2006.257.02:13:17.06#ibcon#read 5, iclass 31, count 2 2006.257.02:13:17.06#ibcon#about to read 6, iclass 31, count 2 2006.257.02:13:17.06#ibcon#read 6, iclass 31, count 2 2006.257.02:13:17.06#ibcon#end of sib2, iclass 31, count 2 2006.257.02:13:17.06#ibcon#*mode == 0, iclass 31, count 2 2006.257.02:13:17.06#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.02:13:17.06#ibcon#[27=AT08-04\r\n] 2006.257.02:13:17.06#ibcon#*before write, iclass 31, count 2 2006.257.02:13:17.06#ibcon#enter sib2, iclass 31, count 2 2006.257.02:13:17.06#ibcon#flushed, iclass 31, count 2 2006.257.02:13:17.06#ibcon#about to write, iclass 31, count 2 2006.257.02:13:17.06#ibcon#wrote, iclass 31, count 2 2006.257.02:13:17.06#ibcon#about to read 3, iclass 31, count 2 2006.257.02:13:17.09#ibcon#read 3, iclass 31, count 2 2006.257.02:13:17.09#ibcon#about to read 4, iclass 31, count 2 2006.257.02:13:17.09#ibcon#read 4, iclass 31, count 2 2006.257.02:13:17.09#ibcon#about to read 5, iclass 31, count 2 2006.257.02:13:17.09#ibcon#read 5, iclass 31, count 2 2006.257.02:13:17.09#ibcon#about to read 6, iclass 31, count 2 2006.257.02:13:17.09#ibcon#read 6, iclass 31, count 2 2006.257.02:13:17.09#ibcon#end of sib2, iclass 31, count 2 2006.257.02:13:17.09#ibcon#*after write, iclass 31, count 2 2006.257.02:13:17.09#ibcon#*before return 0, iclass 31, count 2 2006.257.02:13:17.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:17.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:13:17.09#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.02:13:17.09#ibcon#ireg 7 cls_cnt 0 2006.257.02:13:17.09#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:17.21#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:17.21#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:17.21#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:13:17.21#ibcon#first serial, iclass 31, count 0 2006.257.02:13:17.21#ibcon#enter sib2, iclass 31, count 0 2006.257.02:13:17.21#ibcon#flushed, iclass 31, count 0 2006.257.02:13:17.21#ibcon#about to write, iclass 31, count 0 2006.257.02:13:17.21#ibcon#wrote, iclass 31, count 0 2006.257.02:13:17.21#ibcon#about to read 3, iclass 31, count 0 2006.257.02:13:17.25#ibcon#read 3, iclass 31, count 0 2006.257.02:13:17.25#ibcon#about to read 4, iclass 31, count 0 2006.257.02:13:17.25#ibcon#read 4, iclass 31, count 0 2006.257.02:13:17.25#ibcon#about to read 5, iclass 31, count 0 2006.257.02:13:17.25#ibcon#read 5, iclass 31, count 0 2006.257.02:13:17.25#ibcon#about to read 6, iclass 31, count 0 2006.257.02:13:17.25#ibcon#read 6, iclass 31, count 0 2006.257.02:13:17.25#ibcon#end of sib2, iclass 31, count 0 2006.257.02:13:17.25#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:13:17.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:13:17.25#ibcon#[27=USB\r\n] 2006.257.02:13:17.25#ibcon#*before write, iclass 31, count 0 2006.257.02:13:17.25#ibcon#enter sib2, iclass 31, count 0 2006.257.02:13:17.25#ibcon#flushed, iclass 31, count 0 2006.257.02:13:17.25#ibcon#about to write, iclass 31, count 0 2006.257.02:13:17.25#ibcon#wrote, iclass 31, count 0 2006.257.02:13:17.25#ibcon#about to read 3, iclass 31, count 0 2006.257.02:13:17.28#ibcon#read 3, iclass 31, count 0 2006.257.02:13:17.28#ibcon#about to read 4, iclass 31, count 0 2006.257.02:13:17.28#ibcon#read 4, iclass 31, count 0 2006.257.02:13:17.28#ibcon#about to read 5, iclass 31, count 0 2006.257.02:13:17.28#ibcon#read 5, iclass 31, count 0 2006.257.02:13:17.28#ibcon#about to read 6, iclass 31, count 0 2006.257.02:13:17.28#ibcon#read 6, iclass 31, count 0 2006.257.02:13:17.28#ibcon#end of sib2, iclass 31, count 0 2006.257.02:13:17.28#ibcon#*after write, iclass 31, count 0 2006.257.02:13:17.28#ibcon#*before return 0, iclass 31, count 0 2006.257.02:13:17.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:17.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:13:17.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:13:17.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:13:17.28$vck44/vabw=wide 2006.257.02:13:17.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.02:13:17.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.02:13:17.28#ibcon#ireg 8 cls_cnt 0 2006.257.02:13:17.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:17.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:17.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:17.28#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:13:17.28#ibcon#first serial, iclass 33, count 0 2006.257.02:13:17.28#ibcon#enter sib2, iclass 33, count 0 2006.257.02:13:17.28#ibcon#flushed, iclass 33, count 0 2006.257.02:13:17.28#ibcon#about to write, iclass 33, count 0 2006.257.02:13:17.28#ibcon#wrote, iclass 33, count 0 2006.257.02:13:17.28#ibcon#about to read 3, iclass 33, count 0 2006.257.02:13:17.30#ibcon#read 3, iclass 33, count 0 2006.257.02:13:17.30#ibcon#about to read 4, iclass 33, count 0 2006.257.02:13:17.30#ibcon#read 4, iclass 33, count 0 2006.257.02:13:17.30#ibcon#about to read 5, iclass 33, count 0 2006.257.02:13:17.30#ibcon#read 5, iclass 33, count 0 2006.257.02:13:17.30#ibcon#about to read 6, iclass 33, count 0 2006.257.02:13:17.30#ibcon#read 6, iclass 33, count 0 2006.257.02:13:17.30#ibcon#end of sib2, iclass 33, count 0 2006.257.02:13:17.30#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:13:17.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:13:17.30#ibcon#[25=BW32\r\n] 2006.257.02:13:17.30#ibcon#*before write, iclass 33, count 0 2006.257.02:13:17.30#ibcon#enter sib2, iclass 33, count 0 2006.257.02:13:17.30#ibcon#flushed, iclass 33, count 0 2006.257.02:13:17.30#ibcon#about to write, iclass 33, count 0 2006.257.02:13:17.30#ibcon#wrote, iclass 33, count 0 2006.257.02:13:17.30#ibcon#about to read 3, iclass 33, count 0 2006.257.02:13:17.33#ibcon#read 3, iclass 33, count 0 2006.257.02:13:17.33#ibcon#about to read 4, iclass 33, count 0 2006.257.02:13:17.33#ibcon#read 4, iclass 33, count 0 2006.257.02:13:17.33#ibcon#about to read 5, iclass 33, count 0 2006.257.02:13:17.33#ibcon#read 5, iclass 33, count 0 2006.257.02:13:17.33#ibcon#about to read 6, iclass 33, count 0 2006.257.02:13:17.33#ibcon#read 6, iclass 33, count 0 2006.257.02:13:17.33#ibcon#end of sib2, iclass 33, count 0 2006.257.02:13:17.33#ibcon#*after write, iclass 33, count 0 2006.257.02:13:17.33#ibcon#*before return 0, iclass 33, count 0 2006.257.02:13:17.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:17.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:13:17.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:13:17.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:13:17.33$vck44/vbbw=wide 2006.257.02:13:17.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.02:13:17.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.02:13:17.33#ibcon#ireg 8 cls_cnt 0 2006.257.02:13:17.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:13:17.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:13:17.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:13:17.40#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:13:17.40#ibcon#first serial, iclass 35, count 0 2006.257.02:13:17.40#ibcon#enter sib2, iclass 35, count 0 2006.257.02:13:17.40#ibcon#flushed, iclass 35, count 0 2006.257.02:13:17.40#ibcon#about to write, iclass 35, count 0 2006.257.02:13:17.40#ibcon#wrote, iclass 35, count 0 2006.257.02:13:17.40#ibcon#about to read 3, iclass 35, count 0 2006.257.02:13:17.42#ibcon#read 3, iclass 35, count 0 2006.257.02:13:17.42#ibcon#about to read 4, iclass 35, count 0 2006.257.02:13:17.42#ibcon#read 4, iclass 35, count 0 2006.257.02:13:17.42#ibcon#about to read 5, iclass 35, count 0 2006.257.02:13:17.42#ibcon#read 5, iclass 35, count 0 2006.257.02:13:17.42#ibcon#about to read 6, iclass 35, count 0 2006.257.02:13:17.42#ibcon#read 6, iclass 35, count 0 2006.257.02:13:17.42#ibcon#end of sib2, iclass 35, count 0 2006.257.02:13:17.42#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:13:17.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:13:17.42#ibcon#[27=BW32\r\n] 2006.257.02:13:17.42#ibcon#*before write, iclass 35, count 0 2006.257.02:13:17.42#ibcon#enter sib2, iclass 35, count 0 2006.257.02:13:17.42#ibcon#flushed, iclass 35, count 0 2006.257.02:13:17.42#ibcon#about to write, iclass 35, count 0 2006.257.02:13:17.42#ibcon#wrote, iclass 35, count 0 2006.257.02:13:17.42#ibcon#about to read 3, iclass 35, count 0 2006.257.02:13:17.45#ibcon#read 3, iclass 35, count 0 2006.257.02:13:17.45#ibcon#about to read 4, iclass 35, count 0 2006.257.02:13:17.45#ibcon#read 4, iclass 35, count 0 2006.257.02:13:17.45#ibcon#about to read 5, iclass 35, count 0 2006.257.02:13:17.45#ibcon#read 5, iclass 35, count 0 2006.257.02:13:17.45#ibcon#about to read 6, iclass 35, count 0 2006.257.02:13:17.45#ibcon#read 6, iclass 35, count 0 2006.257.02:13:17.45#ibcon#end of sib2, iclass 35, count 0 2006.257.02:13:17.45#ibcon#*after write, iclass 35, count 0 2006.257.02:13:17.45#ibcon#*before return 0, iclass 35, count 0 2006.257.02:13:17.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:13:17.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:13:17.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:13:17.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:13:17.45$setupk4/ifdk4 2006.257.02:13:17.45$ifdk4/lo= 2006.257.02:13:17.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:13:17.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:13:17.45$ifdk4/patch= 2006.257.02:13:17.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:13:17.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:13:17.45$setupk4/!*+20s 2006.257.02:13:19.45#abcon#<5=/03 3.1 7.7 17.76 981012.1\r\n> 2006.257.02:13:19.47#abcon#{5=INTERFACE CLEAR} 2006.257.02:13:19.53#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:13:29.62#abcon#<5=/03 3.1 7.7 17.75 981012.1\r\n> 2006.257.02:13:29.64#abcon#{5=INTERFACE CLEAR} 2006.257.02:13:29.70#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:13:31.86$setupk4/"tpicd 2006.257.02:13:31.86$setupk4/echo=off 2006.257.02:13:31.86$setupk4/xlog=off 2006.257.02:13:31.86:!2006.257.02:16:10 2006.257.02:13:48.14#trakl#Source acquired 2006.257.02:13:48.14#flagr#flagr/antenna,acquired 2006.257.02:15:05.14#trakl#Off source 2006.257.02:15:05.14?ERROR st -7 Antenna off-source! 2006.257.02:15:05.14#trakl#az 345.154 el 7.678 azerr*cos(el) 0.0005 elerr -0.0168 2006.257.02:15:06.14#flagr#flagr/antenna,off-source 2006.257.02:15:11.14#trakl#Source re-acquired 2006.257.02:15:12.14#flagr#flagr/antenna,re-acquired 2006.257.02:15:32.14#trakl#Off source 2006.257.02:15:32.14?ERROR st -7 Antenna off-source! 2006.257.02:15:32.14#trakl#az 345.209 el 7.655 azerr*cos(el) -0.0012 elerr -0.0208 2006.257.02:15:33.14#flagr#flagr/antenna,off-source 2006.257.02:15:38.14#trakl#Source re-acquired 2006.257.02:15:39.14#flagr#flagr/antenna,re-acquired 2006.257.02:16:10.00:preob 2006.257.02:16:10.14/onsource/TRACKING 2006.257.02:16:10.14:!2006.257.02:16:20 2006.257.02:16:20.00:"tape 2006.257.02:16:20.00:"st=record 2006.257.02:16:20.00:data_valid=on 2006.257.02:16:20.00:midob 2006.257.02:16:21.14/onsource/TRACKING 2006.257.02:16:21.14/wx/17.77,1012.1,98 2006.257.02:16:21.21/cable/+6.4857E-03 2006.257.02:16:22.30/va/01,08,usb,yes,40,43 2006.257.02:16:22.30/va/02,07,usb,yes,43,44 2006.257.02:16:22.30/va/03,08,usb,yes,39,41 2006.257.02:16:22.30/va/04,07,usb,yes,45,47 2006.257.02:16:22.30/va/05,04,usb,yes,40,41 2006.257.02:16:22.30/va/06,04,usb,yes,44,44 2006.257.02:16:22.30/va/07,04,usb,yes,45,46 2006.257.02:16:22.30/va/08,04,usb,yes,38,46 2006.257.02:16:22.53/valo/01,524.99,yes,locked 2006.257.02:16:22.53/valo/02,534.99,yes,locked 2006.257.02:16:22.53/valo/03,564.99,yes,locked 2006.257.02:16:22.53/valo/04,624.99,yes,locked 2006.257.02:16:22.53/valo/05,734.99,yes,locked 2006.257.02:16:22.53/valo/06,814.99,yes,locked 2006.257.02:16:22.53/valo/07,864.99,yes,locked 2006.257.02:16:22.53/valo/08,884.99,yes,locked 2006.257.02:16:23.62/vb/01,04,usb,yes,35,32 2006.257.02:16:23.62/vb/02,05,usb,yes,33,32 2006.257.02:16:23.62/vb/03,04,usb,yes,34,37 2006.257.02:16:23.62/vb/04,05,usb,yes,34,33 2006.257.02:16:23.62/vb/05,04,usb,yes,31,33 2006.257.02:16:23.62/vb/06,04,usb,yes,36,32 2006.257.02:16:23.62/vb/07,04,usb,yes,35,35 2006.257.02:16:23.62/vb/08,04,usb,yes,32,36 2006.257.02:16:23.85/vblo/01,629.99,yes,locked 2006.257.02:16:23.85/vblo/02,634.99,yes,locked 2006.257.02:16:23.85/vblo/03,649.99,yes,locked 2006.257.02:16:23.85/vblo/04,679.99,yes,locked 2006.257.02:16:23.85/vblo/05,709.99,yes,locked 2006.257.02:16:23.85/vblo/06,719.99,yes,locked 2006.257.02:16:23.85/vblo/07,734.99,yes,locked 2006.257.02:16:23.85/vblo/08,744.99,yes,locked 2006.257.02:16:24.00/vabw/8 2006.257.02:16:24.15/vbbw/8 2006.257.02:16:24.24/xfe/off,on,15.0 2006.257.02:16:24.62/ifatt/23,28,28,28 2006.257.02:16:25.08/fmout-gps/S +4.57E-07 2006.257.02:16:25.12:!2006.257.02:17:10 2006.257.02:17:10.00:data_valid=off 2006.257.02:17:10.00:"et 2006.257.02:17:10.01:!+3s 2006.257.02:17:13.02:"tape 2006.257.02:17:13.02:postob 2006.257.02:17:13.17/cable/+6.4865E-03 2006.257.02:17:13.17/wx/17.78,1012.1,99 2006.257.02:17:13.23/fmout-gps/S +4.58E-07 2006.257.02:17:13.23:scan_name=257-0219,jd0609,250 2006.257.02:17:13.24:source=1803+784,180045.68,782804.0,2000.0,cw 2006.257.02:17:14.14#flagr#flagr/antenna,new-source 2006.257.02:17:14.14:checkk5 2006.257.02:17:14.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:17:14.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:17:15.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:17:15.82/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:17:16.23/chk_obsdata//k5ts1/T2570216??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:17:16.61/chk_obsdata//k5ts2/T2570216??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:17:17.11/chk_obsdata//k5ts3/T2570216??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:17:17.51/chk_obsdata//k5ts4/T2570216??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:17:18.24/k5log//k5ts1_log_newline 2006.257.02:17:19.20/k5log//k5ts2_log_newline 2006.257.02:17:20.00/k5log//k5ts3_log_newline 2006.257.02:17:20.81/k5log//k5ts4_log_newline 2006.257.02:17:20.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:17:20.84:setupk4=1 2006.257.02:17:20.84$setupk4/echo=on 2006.257.02:17:20.84$setupk4/pcalon 2006.257.02:17:20.84$pcalon/"no phase cal control is implemented here 2006.257.02:17:20.84$setupk4/"tpicd=stop 2006.257.02:17:20.84$setupk4/"rec=synch_on 2006.257.02:17:20.84$setupk4/"rec_mode=128 2006.257.02:17:20.84$setupk4/!* 2006.257.02:17:20.84$setupk4/recpk4 2006.257.02:17:20.84$recpk4/recpatch= 2006.257.02:17:20.84$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:17:20.84$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:17:20.84$setupk4/vck44 2006.257.02:17:20.84$vck44/valo=1,524.99 2006.257.02:17:20.84#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.02:17:20.84#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.02:17:20.84#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:20.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:17:20.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:17:20.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:17:20.84#ibcon#enter wrdev, iclass 32, count 0 2006.257.02:17:20.84#ibcon#first serial, iclass 32, count 0 2006.257.02:17:20.84#ibcon#enter sib2, iclass 32, count 0 2006.257.02:17:20.84#ibcon#flushed, iclass 32, count 0 2006.257.02:17:20.84#ibcon#about to write, iclass 32, count 0 2006.257.02:17:20.84#ibcon#wrote, iclass 32, count 0 2006.257.02:17:20.84#ibcon#about to read 3, iclass 32, count 0 2006.257.02:17:20.88#ibcon#read 3, iclass 32, count 0 2006.257.02:17:20.88#ibcon#about to read 4, iclass 32, count 0 2006.257.02:17:20.88#ibcon#read 4, iclass 32, count 0 2006.257.02:17:20.88#ibcon#about to read 5, iclass 32, count 0 2006.257.02:17:20.88#ibcon#read 5, iclass 32, count 0 2006.257.02:17:20.88#ibcon#about to read 6, iclass 32, count 0 2006.257.02:17:20.88#ibcon#read 6, iclass 32, count 0 2006.257.02:17:20.88#ibcon#end of sib2, iclass 32, count 0 2006.257.02:17:20.88#ibcon#*mode == 0, iclass 32, count 0 2006.257.02:17:20.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.02:17:20.88#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:17:20.88#ibcon#*before write, iclass 32, count 0 2006.257.02:17:20.88#ibcon#enter sib2, iclass 32, count 0 2006.257.02:17:20.88#ibcon#flushed, iclass 32, count 0 2006.257.02:17:20.88#ibcon#about to write, iclass 32, count 0 2006.257.02:17:20.88#ibcon#wrote, iclass 32, count 0 2006.257.02:17:20.88#ibcon#about to read 3, iclass 32, count 0 2006.257.02:17:20.93#ibcon#read 3, iclass 32, count 0 2006.257.02:17:20.93#ibcon#about to read 4, iclass 32, count 0 2006.257.02:17:20.93#ibcon#read 4, iclass 32, count 0 2006.257.02:17:20.93#ibcon#about to read 5, iclass 32, count 0 2006.257.02:17:20.93#ibcon#read 5, iclass 32, count 0 2006.257.02:17:20.93#ibcon#about to read 6, iclass 32, count 0 2006.257.02:17:20.93#ibcon#read 6, iclass 32, count 0 2006.257.02:17:20.93#ibcon#end of sib2, iclass 32, count 0 2006.257.02:17:20.93#ibcon#*after write, iclass 32, count 0 2006.257.02:17:20.93#ibcon#*before return 0, iclass 32, count 0 2006.257.02:17:20.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:17:20.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:17:20.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.02:17:20.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.02:17:20.93$vck44/va=1,8 2006.257.02:17:20.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.02:17:20.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.02:17:20.93#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:20.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:17:20.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:17:20.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:17:20.93#ibcon#enter wrdev, iclass 34, count 2 2006.257.02:17:20.93#ibcon#first serial, iclass 34, count 2 2006.257.02:17:20.93#ibcon#enter sib2, iclass 34, count 2 2006.257.02:17:20.93#ibcon#flushed, iclass 34, count 2 2006.257.02:17:20.93#ibcon#about to write, iclass 34, count 2 2006.257.02:17:20.93#ibcon#wrote, iclass 34, count 2 2006.257.02:17:20.93#ibcon#about to read 3, iclass 34, count 2 2006.257.02:17:20.95#ibcon#read 3, iclass 34, count 2 2006.257.02:17:20.95#ibcon#about to read 4, iclass 34, count 2 2006.257.02:17:20.95#ibcon#read 4, iclass 34, count 2 2006.257.02:17:20.95#ibcon#about to read 5, iclass 34, count 2 2006.257.02:17:20.95#ibcon#read 5, iclass 34, count 2 2006.257.02:17:20.95#ibcon#about to read 6, iclass 34, count 2 2006.257.02:17:20.95#ibcon#read 6, iclass 34, count 2 2006.257.02:17:20.95#ibcon#end of sib2, iclass 34, count 2 2006.257.02:17:20.95#ibcon#*mode == 0, iclass 34, count 2 2006.257.02:17:20.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.02:17:20.95#ibcon#[25=AT01-08\r\n] 2006.257.02:17:20.95#ibcon#*before write, iclass 34, count 2 2006.257.02:17:20.95#ibcon#enter sib2, iclass 34, count 2 2006.257.02:17:20.95#ibcon#flushed, iclass 34, count 2 2006.257.02:17:20.95#ibcon#about to write, iclass 34, count 2 2006.257.02:17:20.95#ibcon#wrote, iclass 34, count 2 2006.257.02:17:20.95#ibcon#about to read 3, iclass 34, count 2 2006.257.02:17:20.98#ibcon#read 3, iclass 34, count 2 2006.257.02:17:20.98#ibcon#about to read 4, iclass 34, count 2 2006.257.02:17:20.98#ibcon#read 4, iclass 34, count 2 2006.257.02:17:20.98#ibcon#about to read 5, iclass 34, count 2 2006.257.02:17:20.98#ibcon#read 5, iclass 34, count 2 2006.257.02:17:20.98#ibcon#about to read 6, iclass 34, count 2 2006.257.02:17:20.98#ibcon#read 6, iclass 34, count 2 2006.257.02:17:20.98#ibcon#end of sib2, iclass 34, count 2 2006.257.02:17:20.98#ibcon#*after write, iclass 34, count 2 2006.257.02:17:20.98#ibcon#*before return 0, iclass 34, count 2 2006.257.02:17:20.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:17:20.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:17:20.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.02:17:20.98#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:20.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:17:21.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:17:21.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:17:21.10#ibcon#enter wrdev, iclass 34, count 0 2006.257.02:17:21.10#ibcon#first serial, iclass 34, count 0 2006.257.02:17:21.10#ibcon#enter sib2, iclass 34, count 0 2006.257.02:17:21.10#ibcon#flushed, iclass 34, count 0 2006.257.02:17:21.10#ibcon#about to write, iclass 34, count 0 2006.257.02:17:21.10#ibcon#wrote, iclass 34, count 0 2006.257.02:17:21.10#ibcon#about to read 3, iclass 34, count 0 2006.257.02:17:21.12#ibcon#read 3, iclass 34, count 0 2006.257.02:17:21.12#ibcon#about to read 4, iclass 34, count 0 2006.257.02:17:21.12#ibcon#read 4, iclass 34, count 0 2006.257.02:17:21.12#ibcon#about to read 5, iclass 34, count 0 2006.257.02:17:21.12#ibcon#read 5, iclass 34, count 0 2006.257.02:17:21.12#ibcon#about to read 6, iclass 34, count 0 2006.257.02:17:21.12#ibcon#read 6, iclass 34, count 0 2006.257.02:17:21.12#ibcon#end of sib2, iclass 34, count 0 2006.257.02:17:21.12#ibcon#*mode == 0, iclass 34, count 0 2006.257.02:17:21.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.02:17:21.12#ibcon#[25=USB\r\n] 2006.257.02:17:21.12#ibcon#*before write, iclass 34, count 0 2006.257.02:17:21.12#ibcon#enter sib2, iclass 34, count 0 2006.257.02:17:21.12#ibcon#flushed, iclass 34, count 0 2006.257.02:17:21.12#ibcon#about to write, iclass 34, count 0 2006.257.02:17:21.12#ibcon#wrote, iclass 34, count 0 2006.257.02:17:21.12#ibcon#about to read 3, iclass 34, count 0 2006.257.02:17:21.15#ibcon#read 3, iclass 34, count 0 2006.257.02:17:21.15#ibcon#about to read 4, iclass 34, count 0 2006.257.02:17:21.15#ibcon#read 4, iclass 34, count 0 2006.257.02:17:21.15#ibcon#about to read 5, iclass 34, count 0 2006.257.02:17:21.15#ibcon#read 5, iclass 34, count 0 2006.257.02:17:21.15#ibcon#about to read 6, iclass 34, count 0 2006.257.02:17:21.15#ibcon#read 6, iclass 34, count 0 2006.257.02:17:21.15#ibcon#end of sib2, iclass 34, count 0 2006.257.02:17:21.15#ibcon#*after write, iclass 34, count 0 2006.257.02:17:21.15#ibcon#*before return 0, iclass 34, count 0 2006.257.02:17:21.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:17:21.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:17:21.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.02:17:21.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.02:17:21.15$vck44/valo=2,534.99 2006.257.02:17:21.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.02:17:21.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.02:17:21.15#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:21.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:21.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:21.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:21.15#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:17:21.15#ibcon#first serial, iclass 36, count 0 2006.257.02:17:21.15#ibcon#enter sib2, iclass 36, count 0 2006.257.02:17:21.15#ibcon#flushed, iclass 36, count 0 2006.257.02:17:21.15#ibcon#about to write, iclass 36, count 0 2006.257.02:17:21.15#ibcon#wrote, iclass 36, count 0 2006.257.02:17:21.15#ibcon#about to read 3, iclass 36, count 0 2006.257.02:17:21.17#ibcon#read 3, iclass 36, count 0 2006.257.02:17:21.17#ibcon#about to read 4, iclass 36, count 0 2006.257.02:17:21.17#ibcon#read 4, iclass 36, count 0 2006.257.02:17:21.17#ibcon#about to read 5, iclass 36, count 0 2006.257.02:17:21.17#ibcon#read 5, iclass 36, count 0 2006.257.02:17:21.17#ibcon#about to read 6, iclass 36, count 0 2006.257.02:17:21.17#ibcon#read 6, iclass 36, count 0 2006.257.02:17:21.17#ibcon#end of sib2, iclass 36, count 0 2006.257.02:17:21.17#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:17:21.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:17:21.17#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:17:21.17#ibcon#*before write, iclass 36, count 0 2006.257.02:17:21.17#ibcon#enter sib2, iclass 36, count 0 2006.257.02:17:21.17#ibcon#flushed, iclass 36, count 0 2006.257.02:17:21.17#ibcon#about to write, iclass 36, count 0 2006.257.02:17:21.17#ibcon#wrote, iclass 36, count 0 2006.257.02:17:21.17#ibcon#about to read 3, iclass 36, count 0 2006.257.02:17:21.21#ibcon#read 3, iclass 36, count 0 2006.257.02:17:21.21#ibcon#about to read 4, iclass 36, count 0 2006.257.02:17:21.21#ibcon#read 4, iclass 36, count 0 2006.257.02:17:21.21#ibcon#about to read 5, iclass 36, count 0 2006.257.02:17:21.21#ibcon#read 5, iclass 36, count 0 2006.257.02:17:21.21#ibcon#about to read 6, iclass 36, count 0 2006.257.02:17:21.21#ibcon#read 6, iclass 36, count 0 2006.257.02:17:21.21#ibcon#end of sib2, iclass 36, count 0 2006.257.02:17:21.21#ibcon#*after write, iclass 36, count 0 2006.257.02:17:21.21#ibcon#*before return 0, iclass 36, count 0 2006.257.02:17:21.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:21.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:21.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:17:21.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:17:21.21$vck44/va=2,7 2006.257.02:17:21.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.02:17:21.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.02:17:21.21#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:21.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:21.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:21.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:21.27#ibcon#enter wrdev, iclass 38, count 2 2006.257.02:17:21.27#ibcon#first serial, iclass 38, count 2 2006.257.02:17:21.27#ibcon#enter sib2, iclass 38, count 2 2006.257.02:17:21.27#ibcon#flushed, iclass 38, count 2 2006.257.02:17:21.27#ibcon#about to write, iclass 38, count 2 2006.257.02:17:21.27#ibcon#wrote, iclass 38, count 2 2006.257.02:17:21.27#ibcon#about to read 3, iclass 38, count 2 2006.257.02:17:21.29#ibcon#read 3, iclass 38, count 2 2006.257.02:17:21.29#ibcon#about to read 4, iclass 38, count 2 2006.257.02:17:21.29#ibcon#read 4, iclass 38, count 2 2006.257.02:17:21.29#ibcon#about to read 5, iclass 38, count 2 2006.257.02:17:21.29#ibcon#read 5, iclass 38, count 2 2006.257.02:17:21.29#ibcon#about to read 6, iclass 38, count 2 2006.257.02:17:21.29#ibcon#read 6, iclass 38, count 2 2006.257.02:17:21.29#ibcon#end of sib2, iclass 38, count 2 2006.257.02:17:21.29#ibcon#*mode == 0, iclass 38, count 2 2006.257.02:17:21.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.02:17:21.29#ibcon#[25=AT02-07\r\n] 2006.257.02:17:21.29#ibcon#*before write, iclass 38, count 2 2006.257.02:17:21.29#ibcon#enter sib2, iclass 38, count 2 2006.257.02:17:21.29#ibcon#flushed, iclass 38, count 2 2006.257.02:17:21.29#ibcon#about to write, iclass 38, count 2 2006.257.02:17:21.29#ibcon#wrote, iclass 38, count 2 2006.257.02:17:21.29#ibcon#about to read 3, iclass 38, count 2 2006.257.02:17:21.32#ibcon#read 3, iclass 38, count 2 2006.257.02:17:21.32#ibcon#about to read 4, iclass 38, count 2 2006.257.02:17:21.32#ibcon#read 4, iclass 38, count 2 2006.257.02:17:21.32#ibcon#about to read 5, iclass 38, count 2 2006.257.02:17:21.32#ibcon#read 5, iclass 38, count 2 2006.257.02:17:21.32#ibcon#about to read 6, iclass 38, count 2 2006.257.02:17:21.32#ibcon#read 6, iclass 38, count 2 2006.257.02:17:21.32#ibcon#end of sib2, iclass 38, count 2 2006.257.02:17:21.32#ibcon#*after write, iclass 38, count 2 2006.257.02:17:21.32#ibcon#*before return 0, iclass 38, count 2 2006.257.02:17:21.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:21.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:21.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.02:17:21.32#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:21.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:21.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:21.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:21.44#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:17:21.44#ibcon#first serial, iclass 38, count 0 2006.257.02:17:21.44#ibcon#enter sib2, iclass 38, count 0 2006.257.02:17:21.44#ibcon#flushed, iclass 38, count 0 2006.257.02:17:21.44#ibcon#about to write, iclass 38, count 0 2006.257.02:17:21.44#ibcon#wrote, iclass 38, count 0 2006.257.02:17:21.44#ibcon#about to read 3, iclass 38, count 0 2006.257.02:17:21.46#ibcon#read 3, iclass 38, count 0 2006.257.02:17:21.46#ibcon#about to read 4, iclass 38, count 0 2006.257.02:17:21.46#ibcon#read 4, iclass 38, count 0 2006.257.02:17:21.46#ibcon#about to read 5, iclass 38, count 0 2006.257.02:17:21.46#ibcon#read 5, iclass 38, count 0 2006.257.02:17:21.46#ibcon#about to read 6, iclass 38, count 0 2006.257.02:17:21.46#ibcon#read 6, iclass 38, count 0 2006.257.02:17:21.46#ibcon#end of sib2, iclass 38, count 0 2006.257.02:17:21.46#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:17:21.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:17:21.46#ibcon#[25=USB\r\n] 2006.257.02:17:21.46#ibcon#*before write, iclass 38, count 0 2006.257.02:17:21.46#ibcon#enter sib2, iclass 38, count 0 2006.257.02:17:21.46#ibcon#flushed, iclass 38, count 0 2006.257.02:17:21.46#ibcon#about to write, iclass 38, count 0 2006.257.02:17:21.46#ibcon#wrote, iclass 38, count 0 2006.257.02:17:21.46#ibcon#about to read 3, iclass 38, count 0 2006.257.02:17:21.49#ibcon#read 3, iclass 38, count 0 2006.257.02:17:21.49#ibcon#about to read 4, iclass 38, count 0 2006.257.02:17:21.49#ibcon#read 4, iclass 38, count 0 2006.257.02:17:21.49#ibcon#about to read 5, iclass 38, count 0 2006.257.02:17:21.49#ibcon#read 5, iclass 38, count 0 2006.257.02:17:21.49#ibcon#about to read 6, iclass 38, count 0 2006.257.02:17:21.49#ibcon#read 6, iclass 38, count 0 2006.257.02:17:21.49#ibcon#end of sib2, iclass 38, count 0 2006.257.02:17:21.49#ibcon#*after write, iclass 38, count 0 2006.257.02:17:21.49#ibcon#*before return 0, iclass 38, count 0 2006.257.02:17:21.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:21.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:21.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:17:21.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:17:21.49$vck44/valo=3,564.99 2006.257.02:17:21.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.02:17:21.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.02:17:21.49#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:21.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:21.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:21.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:21.49#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:17:21.49#ibcon#first serial, iclass 40, count 0 2006.257.02:17:21.49#ibcon#enter sib2, iclass 40, count 0 2006.257.02:17:21.49#ibcon#flushed, iclass 40, count 0 2006.257.02:17:21.49#ibcon#about to write, iclass 40, count 0 2006.257.02:17:21.49#ibcon#wrote, iclass 40, count 0 2006.257.02:17:21.49#ibcon#about to read 3, iclass 40, count 0 2006.257.02:17:21.51#ibcon#read 3, iclass 40, count 0 2006.257.02:17:21.51#ibcon#about to read 4, iclass 40, count 0 2006.257.02:17:21.51#ibcon#read 4, iclass 40, count 0 2006.257.02:17:21.51#ibcon#about to read 5, iclass 40, count 0 2006.257.02:17:21.51#ibcon#read 5, iclass 40, count 0 2006.257.02:17:21.51#ibcon#about to read 6, iclass 40, count 0 2006.257.02:17:21.51#ibcon#read 6, iclass 40, count 0 2006.257.02:17:21.51#ibcon#end of sib2, iclass 40, count 0 2006.257.02:17:21.51#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:17:21.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:17:21.51#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:17:21.51#ibcon#*before write, iclass 40, count 0 2006.257.02:17:21.51#ibcon#enter sib2, iclass 40, count 0 2006.257.02:17:21.51#ibcon#flushed, iclass 40, count 0 2006.257.02:17:21.51#ibcon#about to write, iclass 40, count 0 2006.257.02:17:21.51#ibcon#wrote, iclass 40, count 0 2006.257.02:17:21.51#ibcon#about to read 3, iclass 40, count 0 2006.257.02:17:21.56#ibcon#read 3, iclass 40, count 0 2006.257.02:17:21.56#ibcon#about to read 4, iclass 40, count 0 2006.257.02:17:21.56#ibcon#read 4, iclass 40, count 0 2006.257.02:17:21.56#ibcon#about to read 5, iclass 40, count 0 2006.257.02:17:21.56#ibcon#read 5, iclass 40, count 0 2006.257.02:17:21.56#ibcon#about to read 6, iclass 40, count 0 2006.257.02:17:21.56#ibcon#read 6, iclass 40, count 0 2006.257.02:17:21.56#ibcon#end of sib2, iclass 40, count 0 2006.257.02:17:21.56#ibcon#*after write, iclass 40, count 0 2006.257.02:17:21.56#ibcon#*before return 0, iclass 40, count 0 2006.257.02:17:21.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:21.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:21.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:17:21.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:17:21.56$vck44/va=3,8 2006.257.02:17:21.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.02:17:21.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.02:17:21.56#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:21.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:21.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:21.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:21.61#ibcon#enter wrdev, iclass 4, count 2 2006.257.02:17:21.61#ibcon#first serial, iclass 4, count 2 2006.257.02:17:21.61#ibcon#enter sib2, iclass 4, count 2 2006.257.02:17:21.61#ibcon#flushed, iclass 4, count 2 2006.257.02:17:21.61#ibcon#about to write, iclass 4, count 2 2006.257.02:17:21.61#ibcon#wrote, iclass 4, count 2 2006.257.02:17:21.61#ibcon#about to read 3, iclass 4, count 2 2006.257.02:17:21.63#ibcon#read 3, iclass 4, count 2 2006.257.02:17:21.63#ibcon#about to read 4, iclass 4, count 2 2006.257.02:17:21.63#ibcon#read 4, iclass 4, count 2 2006.257.02:17:21.63#ibcon#about to read 5, iclass 4, count 2 2006.257.02:17:21.63#ibcon#read 5, iclass 4, count 2 2006.257.02:17:21.63#ibcon#about to read 6, iclass 4, count 2 2006.257.02:17:21.63#ibcon#read 6, iclass 4, count 2 2006.257.02:17:21.63#ibcon#end of sib2, iclass 4, count 2 2006.257.02:17:21.63#ibcon#*mode == 0, iclass 4, count 2 2006.257.02:17:21.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.02:17:21.63#ibcon#[25=AT03-08\r\n] 2006.257.02:17:21.63#ibcon#*before write, iclass 4, count 2 2006.257.02:17:21.63#ibcon#enter sib2, iclass 4, count 2 2006.257.02:17:21.63#ibcon#flushed, iclass 4, count 2 2006.257.02:17:21.63#ibcon#about to write, iclass 4, count 2 2006.257.02:17:21.63#ibcon#wrote, iclass 4, count 2 2006.257.02:17:21.63#ibcon#about to read 3, iclass 4, count 2 2006.257.02:17:21.66#ibcon#read 3, iclass 4, count 2 2006.257.02:17:21.66#ibcon#about to read 4, iclass 4, count 2 2006.257.02:17:21.66#ibcon#read 4, iclass 4, count 2 2006.257.02:17:21.66#ibcon#about to read 5, iclass 4, count 2 2006.257.02:17:21.66#ibcon#read 5, iclass 4, count 2 2006.257.02:17:21.66#ibcon#about to read 6, iclass 4, count 2 2006.257.02:17:21.66#ibcon#read 6, iclass 4, count 2 2006.257.02:17:21.66#ibcon#end of sib2, iclass 4, count 2 2006.257.02:17:21.66#ibcon#*after write, iclass 4, count 2 2006.257.02:17:21.66#ibcon#*before return 0, iclass 4, count 2 2006.257.02:17:21.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:21.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:21.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.02:17:21.66#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:21.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:21.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:21.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:21.78#ibcon#enter wrdev, iclass 4, count 0 2006.257.02:17:21.78#ibcon#first serial, iclass 4, count 0 2006.257.02:17:21.78#ibcon#enter sib2, iclass 4, count 0 2006.257.02:17:21.78#ibcon#flushed, iclass 4, count 0 2006.257.02:17:21.78#ibcon#about to write, iclass 4, count 0 2006.257.02:17:21.78#ibcon#wrote, iclass 4, count 0 2006.257.02:17:21.78#ibcon#about to read 3, iclass 4, count 0 2006.257.02:17:21.80#ibcon#read 3, iclass 4, count 0 2006.257.02:17:21.80#ibcon#about to read 4, iclass 4, count 0 2006.257.02:17:21.80#ibcon#read 4, iclass 4, count 0 2006.257.02:17:21.80#ibcon#about to read 5, iclass 4, count 0 2006.257.02:17:21.80#ibcon#read 5, iclass 4, count 0 2006.257.02:17:21.80#ibcon#about to read 6, iclass 4, count 0 2006.257.02:17:21.80#ibcon#read 6, iclass 4, count 0 2006.257.02:17:21.80#ibcon#end of sib2, iclass 4, count 0 2006.257.02:17:21.80#ibcon#*mode == 0, iclass 4, count 0 2006.257.02:17:21.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.02:17:21.80#ibcon#[25=USB\r\n] 2006.257.02:17:21.80#ibcon#*before write, iclass 4, count 0 2006.257.02:17:21.80#ibcon#enter sib2, iclass 4, count 0 2006.257.02:17:21.80#ibcon#flushed, iclass 4, count 0 2006.257.02:17:21.80#ibcon#about to write, iclass 4, count 0 2006.257.02:17:21.80#ibcon#wrote, iclass 4, count 0 2006.257.02:17:21.80#ibcon#about to read 3, iclass 4, count 0 2006.257.02:17:21.83#ibcon#read 3, iclass 4, count 0 2006.257.02:17:21.83#ibcon#about to read 4, iclass 4, count 0 2006.257.02:17:21.83#ibcon#read 4, iclass 4, count 0 2006.257.02:17:21.83#ibcon#about to read 5, iclass 4, count 0 2006.257.02:17:21.83#ibcon#read 5, iclass 4, count 0 2006.257.02:17:21.83#ibcon#about to read 6, iclass 4, count 0 2006.257.02:17:21.83#ibcon#read 6, iclass 4, count 0 2006.257.02:17:21.83#ibcon#end of sib2, iclass 4, count 0 2006.257.02:17:21.83#ibcon#*after write, iclass 4, count 0 2006.257.02:17:21.83#ibcon#*before return 0, iclass 4, count 0 2006.257.02:17:21.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:21.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:21.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.02:17:21.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.02:17:21.83$vck44/valo=4,624.99 2006.257.02:17:21.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.02:17:21.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.02:17:21.83#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:21.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:21.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:21.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:21.83#ibcon#enter wrdev, iclass 6, count 0 2006.257.02:17:21.83#ibcon#first serial, iclass 6, count 0 2006.257.02:17:21.83#ibcon#enter sib2, iclass 6, count 0 2006.257.02:17:21.83#ibcon#flushed, iclass 6, count 0 2006.257.02:17:21.83#ibcon#about to write, iclass 6, count 0 2006.257.02:17:21.83#ibcon#wrote, iclass 6, count 0 2006.257.02:17:21.83#ibcon#about to read 3, iclass 6, count 0 2006.257.02:17:21.85#ibcon#read 3, iclass 6, count 0 2006.257.02:17:21.85#ibcon#about to read 4, iclass 6, count 0 2006.257.02:17:21.85#ibcon#read 4, iclass 6, count 0 2006.257.02:17:21.85#ibcon#about to read 5, iclass 6, count 0 2006.257.02:17:21.85#ibcon#read 5, iclass 6, count 0 2006.257.02:17:21.85#ibcon#about to read 6, iclass 6, count 0 2006.257.02:17:21.85#ibcon#read 6, iclass 6, count 0 2006.257.02:17:21.85#ibcon#end of sib2, iclass 6, count 0 2006.257.02:17:21.85#ibcon#*mode == 0, iclass 6, count 0 2006.257.02:17:21.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.02:17:21.85#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:17:21.85#ibcon#*before write, iclass 6, count 0 2006.257.02:17:21.85#ibcon#enter sib2, iclass 6, count 0 2006.257.02:17:21.85#ibcon#flushed, iclass 6, count 0 2006.257.02:17:21.85#ibcon#about to write, iclass 6, count 0 2006.257.02:17:21.85#ibcon#wrote, iclass 6, count 0 2006.257.02:17:21.85#ibcon#about to read 3, iclass 6, count 0 2006.257.02:17:21.90#ibcon#read 3, iclass 6, count 0 2006.257.02:17:21.90#ibcon#about to read 4, iclass 6, count 0 2006.257.02:17:21.90#ibcon#read 4, iclass 6, count 0 2006.257.02:17:21.90#ibcon#about to read 5, iclass 6, count 0 2006.257.02:17:21.90#ibcon#read 5, iclass 6, count 0 2006.257.02:17:21.90#ibcon#about to read 6, iclass 6, count 0 2006.257.02:17:21.90#ibcon#read 6, iclass 6, count 0 2006.257.02:17:21.90#ibcon#end of sib2, iclass 6, count 0 2006.257.02:17:21.90#ibcon#*after write, iclass 6, count 0 2006.257.02:17:21.90#ibcon#*before return 0, iclass 6, count 0 2006.257.02:17:21.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:21.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:21.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.02:17:21.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.02:17:21.90$vck44/va=4,7 2006.257.02:17:21.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.02:17:21.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.02:17:21.90#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:21.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:21.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:21.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:21.95#ibcon#enter wrdev, iclass 10, count 2 2006.257.02:17:21.95#ibcon#first serial, iclass 10, count 2 2006.257.02:17:21.95#ibcon#enter sib2, iclass 10, count 2 2006.257.02:17:21.95#ibcon#flushed, iclass 10, count 2 2006.257.02:17:21.95#ibcon#about to write, iclass 10, count 2 2006.257.02:17:21.95#ibcon#wrote, iclass 10, count 2 2006.257.02:17:21.95#ibcon#about to read 3, iclass 10, count 2 2006.257.02:17:21.97#ibcon#read 3, iclass 10, count 2 2006.257.02:17:21.97#ibcon#about to read 4, iclass 10, count 2 2006.257.02:17:21.97#ibcon#read 4, iclass 10, count 2 2006.257.02:17:21.97#ibcon#about to read 5, iclass 10, count 2 2006.257.02:17:21.97#ibcon#read 5, iclass 10, count 2 2006.257.02:17:21.97#ibcon#about to read 6, iclass 10, count 2 2006.257.02:17:21.97#ibcon#read 6, iclass 10, count 2 2006.257.02:17:21.97#ibcon#end of sib2, iclass 10, count 2 2006.257.02:17:21.97#ibcon#*mode == 0, iclass 10, count 2 2006.257.02:17:21.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.02:17:21.97#ibcon#[25=AT04-07\r\n] 2006.257.02:17:21.97#ibcon#*before write, iclass 10, count 2 2006.257.02:17:21.97#ibcon#enter sib2, iclass 10, count 2 2006.257.02:17:21.97#ibcon#flushed, iclass 10, count 2 2006.257.02:17:21.97#ibcon#about to write, iclass 10, count 2 2006.257.02:17:21.97#ibcon#wrote, iclass 10, count 2 2006.257.02:17:21.97#ibcon#about to read 3, iclass 10, count 2 2006.257.02:17:22.00#ibcon#read 3, iclass 10, count 2 2006.257.02:17:22.00#ibcon#about to read 4, iclass 10, count 2 2006.257.02:17:22.00#ibcon#read 4, iclass 10, count 2 2006.257.02:17:22.00#ibcon#about to read 5, iclass 10, count 2 2006.257.02:17:22.00#ibcon#read 5, iclass 10, count 2 2006.257.02:17:22.00#ibcon#about to read 6, iclass 10, count 2 2006.257.02:17:22.00#ibcon#read 6, iclass 10, count 2 2006.257.02:17:22.00#ibcon#end of sib2, iclass 10, count 2 2006.257.02:17:22.00#ibcon#*after write, iclass 10, count 2 2006.257.02:17:22.00#ibcon#*before return 0, iclass 10, count 2 2006.257.02:17:22.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:22.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:22.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.02:17:22.00#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:22.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:22.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:22.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:22.12#ibcon#enter wrdev, iclass 10, count 0 2006.257.02:17:22.12#ibcon#first serial, iclass 10, count 0 2006.257.02:17:22.12#ibcon#enter sib2, iclass 10, count 0 2006.257.02:17:22.12#ibcon#flushed, iclass 10, count 0 2006.257.02:17:22.12#ibcon#about to write, iclass 10, count 0 2006.257.02:17:22.12#ibcon#wrote, iclass 10, count 0 2006.257.02:17:22.12#ibcon#about to read 3, iclass 10, count 0 2006.257.02:17:22.14#ibcon#read 3, iclass 10, count 0 2006.257.02:17:22.14#ibcon#about to read 4, iclass 10, count 0 2006.257.02:17:22.14#ibcon#read 4, iclass 10, count 0 2006.257.02:17:22.14#ibcon#about to read 5, iclass 10, count 0 2006.257.02:17:22.14#ibcon#read 5, iclass 10, count 0 2006.257.02:17:22.14#ibcon#about to read 6, iclass 10, count 0 2006.257.02:17:22.14#ibcon#read 6, iclass 10, count 0 2006.257.02:17:22.14#ibcon#end of sib2, iclass 10, count 0 2006.257.02:17:22.14#ibcon#*mode == 0, iclass 10, count 0 2006.257.02:17:22.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.02:17:22.14#ibcon#[25=USB\r\n] 2006.257.02:17:22.14#ibcon#*before write, iclass 10, count 0 2006.257.02:17:22.14#ibcon#enter sib2, iclass 10, count 0 2006.257.02:17:22.14#ibcon#flushed, iclass 10, count 0 2006.257.02:17:22.14#ibcon#about to write, iclass 10, count 0 2006.257.02:17:22.14#ibcon#wrote, iclass 10, count 0 2006.257.02:17:22.14#ibcon#about to read 3, iclass 10, count 0 2006.257.02:17:22.17#ibcon#read 3, iclass 10, count 0 2006.257.02:17:22.17#ibcon#about to read 4, iclass 10, count 0 2006.257.02:17:22.17#ibcon#read 4, iclass 10, count 0 2006.257.02:17:22.17#ibcon#about to read 5, iclass 10, count 0 2006.257.02:17:22.17#ibcon#read 5, iclass 10, count 0 2006.257.02:17:22.17#ibcon#about to read 6, iclass 10, count 0 2006.257.02:17:22.17#ibcon#read 6, iclass 10, count 0 2006.257.02:17:22.17#ibcon#end of sib2, iclass 10, count 0 2006.257.02:17:22.17#ibcon#*after write, iclass 10, count 0 2006.257.02:17:22.17#ibcon#*before return 0, iclass 10, count 0 2006.257.02:17:22.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:22.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:22.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.02:17:22.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.02:17:22.17$vck44/valo=5,734.99 2006.257.02:17:22.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.02:17:22.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.02:17:22.17#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:22.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:22.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:22.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:22.17#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:17:22.17#ibcon#first serial, iclass 12, count 0 2006.257.02:17:22.17#ibcon#enter sib2, iclass 12, count 0 2006.257.02:17:22.17#ibcon#flushed, iclass 12, count 0 2006.257.02:17:22.17#ibcon#about to write, iclass 12, count 0 2006.257.02:17:22.17#ibcon#wrote, iclass 12, count 0 2006.257.02:17:22.17#ibcon#about to read 3, iclass 12, count 0 2006.257.02:17:22.19#ibcon#read 3, iclass 12, count 0 2006.257.02:17:22.19#ibcon#about to read 4, iclass 12, count 0 2006.257.02:17:22.19#ibcon#read 4, iclass 12, count 0 2006.257.02:17:22.19#ibcon#about to read 5, iclass 12, count 0 2006.257.02:17:22.19#ibcon#read 5, iclass 12, count 0 2006.257.02:17:22.19#ibcon#about to read 6, iclass 12, count 0 2006.257.02:17:22.19#ibcon#read 6, iclass 12, count 0 2006.257.02:17:22.19#ibcon#end of sib2, iclass 12, count 0 2006.257.02:17:22.19#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:17:22.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:17:22.19#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:17:22.19#ibcon#*before write, iclass 12, count 0 2006.257.02:17:22.19#ibcon#enter sib2, iclass 12, count 0 2006.257.02:17:22.19#ibcon#flushed, iclass 12, count 0 2006.257.02:17:22.19#ibcon#about to write, iclass 12, count 0 2006.257.02:17:22.19#ibcon#wrote, iclass 12, count 0 2006.257.02:17:22.19#ibcon#about to read 3, iclass 12, count 0 2006.257.02:17:22.23#ibcon#read 3, iclass 12, count 0 2006.257.02:17:22.23#ibcon#about to read 4, iclass 12, count 0 2006.257.02:17:22.23#ibcon#read 4, iclass 12, count 0 2006.257.02:17:22.23#ibcon#about to read 5, iclass 12, count 0 2006.257.02:17:22.23#ibcon#read 5, iclass 12, count 0 2006.257.02:17:22.23#ibcon#about to read 6, iclass 12, count 0 2006.257.02:17:22.23#ibcon#read 6, iclass 12, count 0 2006.257.02:17:22.23#ibcon#end of sib2, iclass 12, count 0 2006.257.02:17:22.23#ibcon#*after write, iclass 12, count 0 2006.257.02:17:22.23#ibcon#*before return 0, iclass 12, count 0 2006.257.02:17:22.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:22.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:22.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:17:22.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:17:22.23$vck44/va=5,4 2006.257.02:17:22.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.02:17:22.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.02:17:22.23#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:22.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:22.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:22.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:22.29#ibcon#enter wrdev, iclass 14, count 2 2006.257.02:17:22.29#ibcon#first serial, iclass 14, count 2 2006.257.02:17:22.29#ibcon#enter sib2, iclass 14, count 2 2006.257.02:17:22.29#ibcon#flushed, iclass 14, count 2 2006.257.02:17:22.29#ibcon#about to write, iclass 14, count 2 2006.257.02:17:22.29#ibcon#wrote, iclass 14, count 2 2006.257.02:17:22.29#ibcon#about to read 3, iclass 14, count 2 2006.257.02:17:22.31#ibcon#read 3, iclass 14, count 2 2006.257.02:17:22.31#ibcon#about to read 4, iclass 14, count 2 2006.257.02:17:22.31#ibcon#read 4, iclass 14, count 2 2006.257.02:17:22.31#ibcon#about to read 5, iclass 14, count 2 2006.257.02:17:22.31#ibcon#read 5, iclass 14, count 2 2006.257.02:17:22.31#ibcon#about to read 6, iclass 14, count 2 2006.257.02:17:22.31#ibcon#read 6, iclass 14, count 2 2006.257.02:17:22.31#ibcon#end of sib2, iclass 14, count 2 2006.257.02:17:22.31#ibcon#*mode == 0, iclass 14, count 2 2006.257.02:17:22.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.02:17:22.31#ibcon#[25=AT05-04\r\n] 2006.257.02:17:22.31#ibcon#*before write, iclass 14, count 2 2006.257.02:17:22.31#ibcon#enter sib2, iclass 14, count 2 2006.257.02:17:22.31#ibcon#flushed, iclass 14, count 2 2006.257.02:17:22.31#ibcon#about to write, iclass 14, count 2 2006.257.02:17:22.31#ibcon#wrote, iclass 14, count 2 2006.257.02:17:22.31#ibcon#about to read 3, iclass 14, count 2 2006.257.02:17:22.34#ibcon#read 3, iclass 14, count 2 2006.257.02:17:22.34#ibcon#about to read 4, iclass 14, count 2 2006.257.02:17:22.34#ibcon#read 4, iclass 14, count 2 2006.257.02:17:22.34#ibcon#about to read 5, iclass 14, count 2 2006.257.02:17:22.34#ibcon#read 5, iclass 14, count 2 2006.257.02:17:22.34#ibcon#about to read 6, iclass 14, count 2 2006.257.02:17:22.34#ibcon#read 6, iclass 14, count 2 2006.257.02:17:22.34#ibcon#end of sib2, iclass 14, count 2 2006.257.02:17:22.34#ibcon#*after write, iclass 14, count 2 2006.257.02:17:22.34#ibcon#*before return 0, iclass 14, count 2 2006.257.02:17:22.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:22.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:22.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.02:17:22.34#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:22.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:22.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:22.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:22.46#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:17:22.46#ibcon#first serial, iclass 14, count 0 2006.257.02:17:22.46#ibcon#enter sib2, iclass 14, count 0 2006.257.02:17:22.46#ibcon#flushed, iclass 14, count 0 2006.257.02:17:22.46#ibcon#about to write, iclass 14, count 0 2006.257.02:17:22.46#ibcon#wrote, iclass 14, count 0 2006.257.02:17:22.46#ibcon#about to read 3, iclass 14, count 0 2006.257.02:17:22.48#ibcon#read 3, iclass 14, count 0 2006.257.02:17:22.48#ibcon#about to read 4, iclass 14, count 0 2006.257.02:17:22.48#ibcon#read 4, iclass 14, count 0 2006.257.02:17:22.48#ibcon#about to read 5, iclass 14, count 0 2006.257.02:17:22.48#ibcon#read 5, iclass 14, count 0 2006.257.02:17:22.48#ibcon#about to read 6, iclass 14, count 0 2006.257.02:17:22.48#ibcon#read 6, iclass 14, count 0 2006.257.02:17:22.48#ibcon#end of sib2, iclass 14, count 0 2006.257.02:17:22.48#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:17:22.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:17:22.48#ibcon#[25=USB\r\n] 2006.257.02:17:22.48#ibcon#*before write, iclass 14, count 0 2006.257.02:17:22.48#ibcon#enter sib2, iclass 14, count 0 2006.257.02:17:22.48#ibcon#flushed, iclass 14, count 0 2006.257.02:17:22.48#ibcon#about to write, iclass 14, count 0 2006.257.02:17:22.48#ibcon#wrote, iclass 14, count 0 2006.257.02:17:22.48#ibcon#about to read 3, iclass 14, count 0 2006.257.02:17:22.51#ibcon#read 3, iclass 14, count 0 2006.257.02:17:22.51#ibcon#about to read 4, iclass 14, count 0 2006.257.02:17:22.51#ibcon#read 4, iclass 14, count 0 2006.257.02:17:22.51#ibcon#about to read 5, iclass 14, count 0 2006.257.02:17:22.51#ibcon#read 5, iclass 14, count 0 2006.257.02:17:22.51#ibcon#about to read 6, iclass 14, count 0 2006.257.02:17:22.51#ibcon#read 6, iclass 14, count 0 2006.257.02:17:22.51#ibcon#end of sib2, iclass 14, count 0 2006.257.02:17:22.51#ibcon#*after write, iclass 14, count 0 2006.257.02:17:22.51#ibcon#*before return 0, iclass 14, count 0 2006.257.02:17:22.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:22.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:22.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:17:22.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:17:22.51$vck44/valo=6,814.99 2006.257.02:17:22.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.02:17:22.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.02:17:22.51#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:22.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:22.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:22.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:22.51#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:17:22.51#ibcon#first serial, iclass 16, count 0 2006.257.02:17:22.51#ibcon#enter sib2, iclass 16, count 0 2006.257.02:17:22.51#ibcon#flushed, iclass 16, count 0 2006.257.02:17:22.51#ibcon#about to write, iclass 16, count 0 2006.257.02:17:22.51#ibcon#wrote, iclass 16, count 0 2006.257.02:17:22.51#ibcon#about to read 3, iclass 16, count 0 2006.257.02:17:22.53#ibcon#read 3, iclass 16, count 0 2006.257.02:17:22.53#ibcon#about to read 4, iclass 16, count 0 2006.257.02:17:22.53#ibcon#read 4, iclass 16, count 0 2006.257.02:17:22.53#ibcon#about to read 5, iclass 16, count 0 2006.257.02:17:22.53#ibcon#read 5, iclass 16, count 0 2006.257.02:17:22.53#ibcon#about to read 6, iclass 16, count 0 2006.257.02:17:22.53#ibcon#read 6, iclass 16, count 0 2006.257.02:17:22.53#ibcon#end of sib2, iclass 16, count 0 2006.257.02:17:22.53#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:17:22.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:17:22.53#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:17:22.53#ibcon#*before write, iclass 16, count 0 2006.257.02:17:22.53#ibcon#enter sib2, iclass 16, count 0 2006.257.02:17:22.53#ibcon#flushed, iclass 16, count 0 2006.257.02:17:22.53#ibcon#about to write, iclass 16, count 0 2006.257.02:17:22.53#ibcon#wrote, iclass 16, count 0 2006.257.02:17:22.53#ibcon#about to read 3, iclass 16, count 0 2006.257.02:17:22.58#ibcon#read 3, iclass 16, count 0 2006.257.02:17:22.58#ibcon#about to read 4, iclass 16, count 0 2006.257.02:17:22.58#ibcon#read 4, iclass 16, count 0 2006.257.02:17:22.58#ibcon#about to read 5, iclass 16, count 0 2006.257.02:17:22.58#ibcon#read 5, iclass 16, count 0 2006.257.02:17:22.58#ibcon#about to read 6, iclass 16, count 0 2006.257.02:17:22.58#ibcon#read 6, iclass 16, count 0 2006.257.02:17:22.58#ibcon#end of sib2, iclass 16, count 0 2006.257.02:17:22.58#ibcon#*after write, iclass 16, count 0 2006.257.02:17:22.58#ibcon#*before return 0, iclass 16, count 0 2006.257.02:17:22.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:22.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:22.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:17:22.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:17:22.58$vck44/va=6,4 2006.257.02:17:22.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.02:17:22.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.02:17:22.58#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:22.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:22.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:22.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:22.63#ibcon#enter wrdev, iclass 18, count 2 2006.257.02:17:22.63#ibcon#first serial, iclass 18, count 2 2006.257.02:17:22.63#ibcon#enter sib2, iclass 18, count 2 2006.257.02:17:22.63#ibcon#flushed, iclass 18, count 2 2006.257.02:17:22.63#ibcon#about to write, iclass 18, count 2 2006.257.02:17:22.63#ibcon#wrote, iclass 18, count 2 2006.257.02:17:22.63#ibcon#about to read 3, iclass 18, count 2 2006.257.02:17:22.65#ibcon#read 3, iclass 18, count 2 2006.257.02:17:22.65#ibcon#about to read 4, iclass 18, count 2 2006.257.02:17:22.65#ibcon#read 4, iclass 18, count 2 2006.257.02:17:22.65#ibcon#about to read 5, iclass 18, count 2 2006.257.02:17:22.65#ibcon#read 5, iclass 18, count 2 2006.257.02:17:22.65#ibcon#about to read 6, iclass 18, count 2 2006.257.02:17:22.65#ibcon#read 6, iclass 18, count 2 2006.257.02:17:22.65#ibcon#end of sib2, iclass 18, count 2 2006.257.02:17:22.65#ibcon#*mode == 0, iclass 18, count 2 2006.257.02:17:22.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.02:17:22.65#ibcon#[25=AT06-04\r\n] 2006.257.02:17:22.65#ibcon#*before write, iclass 18, count 2 2006.257.02:17:22.65#ibcon#enter sib2, iclass 18, count 2 2006.257.02:17:22.65#ibcon#flushed, iclass 18, count 2 2006.257.02:17:22.65#ibcon#about to write, iclass 18, count 2 2006.257.02:17:22.65#ibcon#wrote, iclass 18, count 2 2006.257.02:17:22.65#ibcon#about to read 3, iclass 18, count 2 2006.257.02:17:22.68#ibcon#read 3, iclass 18, count 2 2006.257.02:17:22.68#ibcon#about to read 4, iclass 18, count 2 2006.257.02:17:22.68#ibcon#read 4, iclass 18, count 2 2006.257.02:17:22.68#ibcon#about to read 5, iclass 18, count 2 2006.257.02:17:22.68#ibcon#read 5, iclass 18, count 2 2006.257.02:17:22.68#ibcon#about to read 6, iclass 18, count 2 2006.257.02:17:22.68#ibcon#read 6, iclass 18, count 2 2006.257.02:17:22.68#ibcon#end of sib2, iclass 18, count 2 2006.257.02:17:22.68#ibcon#*after write, iclass 18, count 2 2006.257.02:17:22.68#ibcon#*before return 0, iclass 18, count 2 2006.257.02:17:22.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:22.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:22.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.02:17:22.68#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:22.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:22.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:22.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:22.80#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:17:22.80#ibcon#first serial, iclass 18, count 0 2006.257.02:17:22.80#ibcon#enter sib2, iclass 18, count 0 2006.257.02:17:22.80#ibcon#flushed, iclass 18, count 0 2006.257.02:17:22.80#ibcon#about to write, iclass 18, count 0 2006.257.02:17:22.80#ibcon#wrote, iclass 18, count 0 2006.257.02:17:22.80#ibcon#about to read 3, iclass 18, count 0 2006.257.02:17:22.82#ibcon#read 3, iclass 18, count 0 2006.257.02:17:22.82#ibcon#about to read 4, iclass 18, count 0 2006.257.02:17:22.82#ibcon#read 4, iclass 18, count 0 2006.257.02:17:22.82#ibcon#about to read 5, iclass 18, count 0 2006.257.02:17:22.82#ibcon#read 5, iclass 18, count 0 2006.257.02:17:22.82#ibcon#about to read 6, iclass 18, count 0 2006.257.02:17:22.82#ibcon#read 6, iclass 18, count 0 2006.257.02:17:22.82#ibcon#end of sib2, iclass 18, count 0 2006.257.02:17:22.82#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:17:22.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:17:22.82#ibcon#[25=USB\r\n] 2006.257.02:17:22.82#ibcon#*before write, iclass 18, count 0 2006.257.02:17:22.82#ibcon#enter sib2, iclass 18, count 0 2006.257.02:17:22.82#ibcon#flushed, iclass 18, count 0 2006.257.02:17:22.82#ibcon#about to write, iclass 18, count 0 2006.257.02:17:22.82#ibcon#wrote, iclass 18, count 0 2006.257.02:17:22.82#ibcon#about to read 3, iclass 18, count 0 2006.257.02:17:22.85#ibcon#read 3, iclass 18, count 0 2006.257.02:17:22.85#ibcon#about to read 4, iclass 18, count 0 2006.257.02:17:22.85#ibcon#read 4, iclass 18, count 0 2006.257.02:17:22.85#ibcon#about to read 5, iclass 18, count 0 2006.257.02:17:22.85#ibcon#read 5, iclass 18, count 0 2006.257.02:17:22.85#ibcon#about to read 6, iclass 18, count 0 2006.257.02:17:22.85#ibcon#read 6, iclass 18, count 0 2006.257.02:17:22.85#ibcon#end of sib2, iclass 18, count 0 2006.257.02:17:22.85#ibcon#*after write, iclass 18, count 0 2006.257.02:17:22.85#ibcon#*before return 0, iclass 18, count 0 2006.257.02:17:22.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:22.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:22.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:17:22.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:17:22.85$vck44/valo=7,864.99 2006.257.02:17:22.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.02:17:22.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.02:17:22.85#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:22.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:22.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:22.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:22.85#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:17:22.85#ibcon#first serial, iclass 20, count 0 2006.257.02:17:22.85#ibcon#enter sib2, iclass 20, count 0 2006.257.02:17:22.85#ibcon#flushed, iclass 20, count 0 2006.257.02:17:22.85#ibcon#about to write, iclass 20, count 0 2006.257.02:17:22.85#ibcon#wrote, iclass 20, count 0 2006.257.02:17:22.85#ibcon#about to read 3, iclass 20, count 0 2006.257.02:17:22.87#ibcon#read 3, iclass 20, count 0 2006.257.02:17:22.87#ibcon#about to read 4, iclass 20, count 0 2006.257.02:17:22.87#ibcon#read 4, iclass 20, count 0 2006.257.02:17:22.87#ibcon#about to read 5, iclass 20, count 0 2006.257.02:17:22.87#ibcon#read 5, iclass 20, count 0 2006.257.02:17:22.87#ibcon#about to read 6, iclass 20, count 0 2006.257.02:17:22.87#ibcon#read 6, iclass 20, count 0 2006.257.02:17:22.87#ibcon#end of sib2, iclass 20, count 0 2006.257.02:17:22.87#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:17:22.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:17:22.87#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:17:22.87#ibcon#*before write, iclass 20, count 0 2006.257.02:17:22.87#ibcon#enter sib2, iclass 20, count 0 2006.257.02:17:22.87#ibcon#flushed, iclass 20, count 0 2006.257.02:17:22.87#ibcon#about to write, iclass 20, count 0 2006.257.02:17:22.87#ibcon#wrote, iclass 20, count 0 2006.257.02:17:22.87#ibcon#about to read 3, iclass 20, count 0 2006.257.02:17:22.91#ibcon#read 3, iclass 20, count 0 2006.257.02:17:22.91#ibcon#about to read 4, iclass 20, count 0 2006.257.02:17:22.91#ibcon#read 4, iclass 20, count 0 2006.257.02:17:22.91#ibcon#about to read 5, iclass 20, count 0 2006.257.02:17:22.91#ibcon#read 5, iclass 20, count 0 2006.257.02:17:22.91#ibcon#about to read 6, iclass 20, count 0 2006.257.02:17:22.91#ibcon#read 6, iclass 20, count 0 2006.257.02:17:22.91#ibcon#end of sib2, iclass 20, count 0 2006.257.02:17:22.91#ibcon#*after write, iclass 20, count 0 2006.257.02:17:22.91#ibcon#*before return 0, iclass 20, count 0 2006.257.02:17:22.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:22.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:22.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:17:22.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:17:22.91$vck44/va=7,4 2006.257.02:17:22.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.02:17:22.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.02:17:22.91#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:22.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:22.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:22.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:22.97#ibcon#enter wrdev, iclass 22, count 2 2006.257.02:17:22.97#ibcon#first serial, iclass 22, count 2 2006.257.02:17:22.97#ibcon#enter sib2, iclass 22, count 2 2006.257.02:17:22.97#ibcon#flushed, iclass 22, count 2 2006.257.02:17:22.97#ibcon#about to write, iclass 22, count 2 2006.257.02:17:22.97#ibcon#wrote, iclass 22, count 2 2006.257.02:17:22.97#ibcon#about to read 3, iclass 22, count 2 2006.257.02:17:22.99#ibcon#read 3, iclass 22, count 2 2006.257.02:17:22.99#ibcon#about to read 4, iclass 22, count 2 2006.257.02:17:22.99#ibcon#read 4, iclass 22, count 2 2006.257.02:17:22.99#ibcon#about to read 5, iclass 22, count 2 2006.257.02:17:22.99#ibcon#read 5, iclass 22, count 2 2006.257.02:17:22.99#ibcon#about to read 6, iclass 22, count 2 2006.257.02:17:22.99#ibcon#read 6, iclass 22, count 2 2006.257.02:17:22.99#ibcon#end of sib2, iclass 22, count 2 2006.257.02:17:22.99#ibcon#*mode == 0, iclass 22, count 2 2006.257.02:17:22.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.02:17:22.99#ibcon#[25=AT07-04\r\n] 2006.257.02:17:22.99#ibcon#*before write, iclass 22, count 2 2006.257.02:17:22.99#ibcon#enter sib2, iclass 22, count 2 2006.257.02:17:22.99#ibcon#flushed, iclass 22, count 2 2006.257.02:17:22.99#ibcon#about to write, iclass 22, count 2 2006.257.02:17:22.99#ibcon#wrote, iclass 22, count 2 2006.257.02:17:22.99#ibcon#about to read 3, iclass 22, count 2 2006.257.02:17:23.02#ibcon#read 3, iclass 22, count 2 2006.257.02:17:23.02#ibcon#about to read 4, iclass 22, count 2 2006.257.02:17:23.02#ibcon#read 4, iclass 22, count 2 2006.257.02:17:23.02#ibcon#about to read 5, iclass 22, count 2 2006.257.02:17:23.02#ibcon#read 5, iclass 22, count 2 2006.257.02:17:23.02#ibcon#about to read 6, iclass 22, count 2 2006.257.02:17:23.02#ibcon#read 6, iclass 22, count 2 2006.257.02:17:23.02#ibcon#end of sib2, iclass 22, count 2 2006.257.02:17:23.02#ibcon#*after write, iclass 22, count 2 2006.257.02:17:23.02#ibcon#*before return 0, iclass 22, count 2 2006.257.02:17:23.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:23.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:23.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.02:17:23.02#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:23.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:23.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:23.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:23.14#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:17:23.14#ibcon#first serial, iclass 22, count 0 2006.257.02:17:23.14#ibcon#enter sib2, iclass 22, count 0 2006.257.02:17:23.14#ibcon#flushed, iclass 22, count 0 2006.257.02:17:23.14#ibcon#about to write, iclass 22, count 0 2006.257.02:17:23.14#ibcon#wrote, iclass 22, count 0 2006.257.02:17:23.14#ibcon#about to read 3, iclass 22, count 0 2006.257.02:17:23.16#ibcon#read 3, iclass 22, count 0 2006.257.02:17:23.16#ibcon#about to read 4, iclass 22, count 0 2006.257.02:17:23.16#ibcon#read 4, iclass 22, count 0 2006.257.02:17:23.16#ibcon#about to read 5, iclass 22, count 0 2006.257.02:17:23.16#ibcon#read 5, iclass 22, count 0 2006.257.02:17:23.16#ibcon#about to read 6, iclass 22, count 0 2006.257.02:17:23.16#ibcon#read 6, iclass 22, count 0 2006.257.02:17:23.16#ibcon#end of sib2, iclass 22, count 0 2006.257.02:17:23.16#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:17:23.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:17:23.16#ibcon#[25=USB\r\n] 2006.257.02:17:23.16#ibcon#*before write, iclass 22, count 0 2006.257.02:17:23.16#ibcon#enter sib2, iclass 22, count 0 2006.257.02:17:23.16#ibcon#flushed, iclass 22, count 0 2006.257.02:17:23.16#ibcon#about to write, iclass 22, count 0 2006.257.02:17:23.16#ibcon#wrote, iclass 22, count 0 2006.257.02:17:23.16#ibcon#about to read 3, iclass 22, count 0 2006.257.02:17:23.19#ibcon#read 3, iclass 22, count 0 2006.257.02:17:23.19#ibcon#about to read 4, iclass 22, count 0 2006.257.02:17:23.19#ibcon#read 4, iclass 22, count 0 2006.257.02:17:23.19#ibcon#about to read 5, iclass 22, count 0 2006.257.02:17:23.19#ibcon#read 5, iclass 22, count 0 2006.257.02:17:23.19#ibcon#about to read 6, iclass 22, count 0 2006.257.02:17:23.19#ibcon#read 6, iclass 22, count 0 2006.257.02:17:23.19#ibcon#end of sib2, iclass 22, count 0 2006.257.02:17:23.19#ibcon#*after write, iclass 22, count 0 2006.257.02:17:23.19#ibcon#*before return 0, iclass 22, count 0 2006.257.02:17:23.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:23.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:23.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:17:23.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:17:23.19$vck44/valo=8,884.99 2006.257.02:17:23.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.02:17:23.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.02:17:23.19#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:23.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:23.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:23.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:23.19#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:17:23.19#ibcon#first serial, iclass 24, count 0 2006.257.02:17:23.19#ibcon#enter sib2, iclass 24, count 0 2006.257.02:17:23.19#ibcon#flushed, iclass 24, count 0 2006.257.02:17:23.19#ibcon#about to write, iclass 24, count 0 2006.257.02:17:23.19#ibcon#wrote, iclass 24, count 0 2006.257.02:17:23.19#ibcon#about to read 3, iclass 24, count 0 2006.257.02:17:23.21#ibcon#read 3, iclass 24, count 0 2006.257.02:17:23.21#ibcon#about to read 4, iclass 24, count 0 2006.257.02:17:23.21#ibcon#read 4, iclass 24, count 0 2006.257.02:17:23.21#ibcon#about to read 5, iclass 24, count 0 2006.257.02:17:23.21#ibcon#read 5, iclass 24, count 0 2006.257.02:17:23.21#ibcon#about to read 6, iclass 24, count 0 2006.257.02:17:23.21#ibcon#read 6, iclass 24, count 0 2006.257.02:17:23.21#ibcon#end of sib2, iclass 24, count 0 2006.257.02:17:23.21#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:17:23.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:17:23.21#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:17:23.21#ibcon#*before write, iclass 24, count 0 2006.257.02:17:23.21#ibcon#enter sib2, iclass 24, count 0 2006.257.02:17:23.21#ibcon#flushed, iclass 24, count 0 2006.257.02:17:23.21#ibcon#about to write, iclass 24, count 0 2006.257.02:17:23.21#ibcon#wrote, iclass 24, count 0 2006.257.02:17:23.21#ibcon#about to read 3, iclass 24, count 0 2006.257.02:17:23.25#ibcon#read 3, iclass 24, count 0 2006.257.02:17:23.25#ibcon#about to read 4, iclass 24, count 0 2006.257.02:17:23.25#ibcon#read 4, iclass 24, count 0 2006.257.02:17:23.25#ibcon#about to read 5, iclass 24, count 0 2006.257.02:17:23.25#ibcon#read 5, iclass 24, count 0 2006.257.02:17:23.25#ibcon#about to read 6, iclass 24, count 0 2006.257.02:17:23.25#ibcon#read 6, iclass 24, count 0 2006.257.02:17:23.25#ibcon#end of sib2, iclass 24, count 0 2006.257.02:17:23.25#ibcon#*after write, iclass 24, count 0 2006.257.02:17:23.25#ibcon#*before return 0, iclass 24, count 0 2006.257.02:17:23.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:23.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:23.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:17:23.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:17:23.25$vck44/va=8,4 2006.257.02:17:23.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.02:17:23.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.02:17:23.25#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:23.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:23.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:23.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:23.31#ibcon#enter wrdev, iclass 26, count 2 2006.257.02:17:23.31#ibcon#first serial, iclass 26, count 2 2006.257.02:17:23.31#ibcon#enter sib2, iclass 26, count 2 2006.257.02:17:23.31#ibcon#flushed, iclass 26, count 2 2006.257.02:17:23.31#ibcon#about to write, iclass 26, count 2 2006.257.02:17:23.31#ibcon#wrote, iclass 26, count 2 2006.257.02:17:23.31#ibcon#about to read 3, iclass 26, count 2 2006.257.02:17:23.33#ibcon#read 3, iclass 26, count 2 2006.257.02:17:23.33#ibcon#about to read 4, iclass 26, count 2 2006.257.02:17:23.33#ibcon#read 4, iclass 26, count 2 2006.257.02:17:23.33#ibcon#about to read 5, iclass 26, count 2 2006.257.02:17:23.33#ibcon#read 5, iclass 26, count 2 2006.257.02:17:23.33#ibcon#about to read 6, iclass 26, count 2 2006.257.02:17:23.33#ibcon#read 6, iclass 26, count 2 2006.257.02:17:23.33#ibcon#end of sib2, iclass 26, count 2 2006.257.02:17:23.33#ibcon#*mode == 0, iclass 26, count 2 2006.257.02:17:23.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.02:17:23.33#ibcon#[25=AT08-04\r\n] 2006.257.02:17:23.33#ibcon#*before write, iclass 26, count 2 2006.257.02:17:23.33#ibcon#enter sib2, iclass 26, count 2 2006.257.02:17:23.33#ibcon#flushed, iclass 26, count 2 2006.257.02:17:23.33#ibcon#about to write, iclass 26, count 2 2006.257.02:17:23.33#ibcon#wrote, iclass 26, count 2 2006.257.02:17:23.33#ibcon#about to read 3, iclass 26, count 2 2006.257.02:17:23.36#ibcon#read 3, iclass 26, count 2 2006.257.02:17:23.36#ibcon#about to read 4, iclass 26, count 2 2006.257.02:17:23.36#ibcon#read 4, iclass 26, count 2 2006.257.02:17:23.36#ibcon#about to read 5, iclass 26, count 2 2006.257.02:17:23.36#ibcon#read 5, iclass 26, count 2 2006.257.02:17:23.36#ibcon#about to read 6, iclass 26, count 2 2006.257.02:17:23.36#ibcon#read 6, iclass 26, count 2 2006.257.02:17:23.36#ibcon#end of sib2, iclass 26, count 2 2006.257.02:17:23.36#ibcon#*after write, iclass 26, count 2 2006.257.02:17:23.36#ibcon#*before return 0, iclass 26, count 2 2006.257.02:17:23.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:23.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:23.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.02:17:23.36#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:23.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:23.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:23.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:23.48#ibcon#enter wrdev, iclass 26, count 0 2006.257.02:17:23.48#ibcon#first serial, iclass 26, count 0 2006.257.02:17:23.48#ibcon#enter sib2, iclass 26, count 0 2006.257.02:17:23.48#ibcon#flushed, iclass 26, count 0 2006.257.02:17:23.48#ibcon#about to write, iclass 26, count 0 2006.257.02:17:23.48#ibcon#wrote, iclass 26, count 0 2006.257.02:17:23.48#ibcon#about to read 3, iclass 26, count 0 2006.257.02:17:23.50#ibcon#read 3, iclass 26, count 0 2006.257.02:17:23.50#ibcon#about to read 4, iclass 26, count 0 2006.257.02:17:23.50#ibcon#read 4, iclass 26, count 0 2006.257.02:17:23.50#ibcon#about to read 5, iclass 26, count 0 2006.257.02:17:23.50#ibcon#read 5, iclass 26, count 0 2006.257.02:17:23.50#ibcon#about to read 6, iclass 26, count 0 2006.257.02:17:23.50#ibcon#read 6, iclass 26, count 0 2006.257.02:17:23.50#ibcon#end of sib2, iclass 26, count 0 2006.257.02:17:23.50#ibcon#*mode == 0, iclass 26, count 0 2006.257.02:17:23.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.02:17:23.50#ibcon#[25=USB\r\n] 2006.257.02:17:23.50#ibcon#*before write, iclass 26, count 0 2006.257.02:17:23.50#ibcon#enter sib2, iclass 26, count 0 2006.257.02:17:23.50#ibcon#flushed, iclass 26, count 0 2006.257.02:17:23.50#ibcon#about to write, iclass 26, count 0 2006.257.02:17:23.50#ibcon#wrote, iclass 26, count 0 2006.257.02:17:23.50#ibcon#about to read 3, iclass 26, count 0 2006.257.02:17:23.53#abcon#<5=/02 2.6 6.4 17.78 981012.1\r\n> 2006.257.02:17:23.53#ibcon#read 3, iclass 26, count 0 2006.257.02:17:23.53#ibcon#about to read 4, iclass 26, count 0 2006.257.02:17:23.53#ibcon#read 4, iclass 26, count 0 2006.257.02:17:23.53#ibcon#about to read 5, iclass 26, count 0 2006.257.02:17:23.53#ibcon#read 5, iclass 26, count 0 2006.257.02:17:23.53#ibcon#about to read 6, iclass 26, count 0 2006.257.02:17:23.53#ibcon#read 6, iclass 26, count 0 2006.257.02:17:23.53#ibcon#end of sib2, iclass 26, count 0 2006.257.02:17:23.53#ibcon#*after write, iclass 26, count 0 2006.257.02:17:23.53#ibcon#*before return 0, iclass 26, count 0 2006.257.02:17:23.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:23.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:23.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.02:17:23.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.02:17:23.53$vck44/vblo=1,629.99 2006.257.02:17:23.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.02:17:23.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.02:17:23.53#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:23.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:17:23.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:17:23.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:17:23.53#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:17:23.53#ibcon#first serial, iclass 31, count 0 2006.257.02:17:23.53#ibcon#enter sib2, iclass 31, count 0 2006.257.02:17:23.53#ibcon#flushed, iclass 31, count 0 2006.257.02:17:23.53#ibcon#about to write, iclass 31, count 0 2006.257.02:17:23.53#ibcon#wrote, iclass 31, count 0 2006.257.02:17:23.53#ibcon#about to read 3, iclass 31, count 0 2006.257.02:17:23.55#abcon#{5=INTERFACE CLEAR} 2006.257.02:17:23.55#ibcon#read 3, iclass 31, count 0 2006.257.02:17:23.55#ibcon#about to read 4, iclass 31, count 0 2006.257.02:17:23.55#ibcon#read 4, iclass 31, count 0 2006.257.02:17:23.55#ibcon#about to read 5, iclass 31, count 0 2006.257.02:17:23.55#ibcon#read 5, iclass 31, count 0 2006.257.02:17:23.55#ibcon#about to read 6, iclass 31, count 0 2006.257.02:17:23.55#ibcon#read 6, iclass 31, count 0 2006.257.02:17:23.55#ibcon#end of sib2, iclass 31, count 0 2006.257.02:17:23.55#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:17:23.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:17:23.55#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:17:23.55#ibcon#*before write, iclass 31, count 0 2006.257.02:17:23.55#ibcon#enter sib2, iclass 31, count 0 2006.257.02:17:23.55#ibcon#flushed, iclass 31, count 0 2006.257.02:17:23.55#ibcon#about to write, iclass 31, count 0 2006.257.02:17:23.55#ibcon#wrote, iclass 31, count 0 2006.257.02:17:23.55#ibcon#about to read 3, iclass 31, count 0 2006.257.02:17:23.59#ibcon#read 3, iclass 31, count 0 2006.257.02:17:23.59#ibcon#about to read 4, iclass 31, count 0 2006.257.02:17:23.59#ibcon#read 4, iclass 31, count 0 2006.257.02:17:23.59#ibcon#about to read 5, iclass 31, count 0 2006.257.02:17:23.59#ibcon#read 5, iclass 31, count 0 2006.257.02:17:23.59#ibcon#about to read 6, iclass 31, count 0 2006.257.02:17:23.59#ibcon#read 6, iclass 31, count 0 2006.257.02:17:23.59#ibcon#end of sib2, iclass 31, count 0 2006.257.02:17:23.59#ibcon#*after write, iclass 31, count 0 2006.257.02:17:23.59#ibcon#*before return 0, iclass 31, count 0 2006.257.02:17:23.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:17:23.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:17:23.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:17:23.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:17:23.59$vck44/vb=1,4 2006.257.02:17:23.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.02:17:23.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.02:17:23.59#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:23.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:17:23.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:17:23.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:17:23.59#ibcon#enter wrdev, iclass 33, count 2 2006.257.02:17:23.59#ibcon#first serial, iclass 33, count 2 2006.257.02:17:23.59#ibcon#enter sib2, iclass 33, count 2 2006.257.02:17:23.59#ibcon#flushed, iclass 33, count 2 2006.257.02:17:23.59#ibcon#about to write, iclass 33, count 2 2006.257.02:17:23.59#ibcon#wrote, iclass 33, count 2 2006.257.02:17:23.59#ibcon#about to read 3, iclass 33, count 2 2006.257.02:17:23.61#ibcon#read 3, iclass 33, count 2 2006.257.02:17:23.61#ibcon#about to read 4, iclass 33, count 2 2006.257.02:17:23.61#ibcon#read 4, iclass 33, count 2 2006.257.02:17:23.61#ibcon#about to read 5, iclass 33, count 2 2006.257.02:17:23.61#ibcon#read 5, iclass 33, count 2 2006.257.02:17:23.61#ibcon#about to read 6, iclass 33, count 2 2006.257.02:17:23.61#ibcon#read 6, iclass 33, count 2 2006.257.02:17:23.61#ibcon#end of sib2, iclass 33, count 2 2006.257.02:17:23.61#ibcon#*mode == 0, iclass 33, count 2 2006.257.02:17:23.61#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.02:17:23.61#ibcon#[27=AT01-04\r\n] 2006.257.02:17:23.61#ibcon#*before write, iclass 33, count 2 2006.257.02:17:23.61#ibcon#enter sib2, iclass 33, count 2 2006.257.02:17:23.61#ibcon#flushed, iclass 33, count 2 2006.257.02:17:23.61#ibcon#about to write, iclass 33, count 2 2006.257.02:17:23.61#ibcon#wrote, iclass 33, count 2 2006.257.02:17:23.61#ibcon#about to read 3, iclass 33, count 2 2006.257.02:17:23.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:17:23.64#ibcon#read 3, iclass 33, count 2 2006.257.02:17:23.64#ibcon#about to read 4, iclass 33, count 2 2006.257.02:17:23.64#ibcon#read 4, iclass 33, count 2 2006.257.02:17:23.64#ibcon#about to read 5, iclass 33, count 2 2006.257.02:17:23.64#ibcon#read 5, iclass 33, count 2 2006.257.02:17:23.64#ibcon#about to read 6, iclass 33, count 2 2006.257.02:17:23.64#ibcon#read 6, iclass 33, count 2 2006.257.02:17:23.64#ibcon#end of sib2, iclass 33, count 2 2006.257.02:17:23.64#ibcon#*after write, iclass 33, count 2 2006.257.02:17:23.64#ibcon#*before return 0, iclass 33, count 2 2006.257.02:17:23.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:17:23.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:17:23.64#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.02:17:23.64#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:23.64#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:17:23.76#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:17:23.76#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:17:23.76#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:17:23.76#ibcon#first serial, iclass 33, count 0 2006.257.02:17:23.76#ibcon#enter sib2, iclass 33, count 0 2006.257.02:17:23.76#ibcon#flushed, iclass 33, count 0 2006.257.02:17:23.76#ibcon#about to write, iclass 33, count 0 2006.257.02:17:23.76#ibcon#wrote, iclass 33, count 0 2006.257.02:17:23.76#ibcon#about to read 3, iclass 33, count 0 2006.257.02:17:23.78#ibcon#read 3, iclass 33, count 0 2006.257.02:17:23.78#ibcon#about to read 4, iclass 33, count 0 2006.257.02:17:23.78#ibcon#read 4, iclass 33, count 0 2006.257.02:17:23.78#ibcon#about to read 5, iclass 33, count 0 2006.257.02:17:23.78#ibcon#read 5, iclass 33, count 0 2006.257.02:17:23.78#ibcon#about to read 6, iclass 33, count 0 2006.257.02:17:23.78#ibcon#read 6, iclass 33, count 0 2006.257.02:17:23.78#ibcon#end of sib2, iclass 33, count 0 2006.257.02:17:23.78#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:17:23.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:17:23.78#ibcon#[27=USB\r\n] 2006.257.02:17:23.78#ibcon#*before write, iclass 33, count 0 2006.257.02:17:23.78#ibcon#enter sib2, iclass 33, count 0 2006.257.02:17:23.78#ibcon#flushed, iclass 33, count 0 2006.257.02:17:23.78#ibcon#about to write, iclass 33, count 0 2006.257.02:17:23.78#ibcon#wrote, iclass 33, count 0 2006.257.02:17:23.78#ibcon#about to read 3, iclass 33, count 0 2006.257.02:17:23.81#ibcon#read 3, iclass 33, count 0 2006.257.02:17:23.81#ibcon#about to read 4, iclass 33, count 0 2006.257.02:17:23.81#ibcon#read 4, iclass 33, count 0 2006.257.02:17:23.81#ibcon#about to read 5, iclass 33, count 0 2006.257.02:17:23.81#ibcon#read 5, iclass 33, count 0 2006.257.02:17:23.81#ibcon#about to read 6, iclass 33, count 0 2006.257.02:17:23.81#ibcon#read 6, iclass 33, count 0 2006.257.02:17:23.81#ibcon#end of sib2, iclass 33, count 0 2006.257.02:17:23.81#ibcon#*after write, iclass 33, count 0 2006.257.02:17:23.81#ibcon#*before return 0, iclass 33, count 0 2006.257.02:17:23.81#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:17:23.81#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:17:23.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:17:23.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:17:23.81$vck44/vblo=2,634.99 2006.257.02:17:23.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.02:17:23.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.02:17:23.81#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:23.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:23.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:23.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:23.81#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:17:23.81#ibcon#first serial, iclass 36, count 0 2006.257.02:17:23.81#ibcon#enter sib2, iclass 36, count 0 2006.257.02:17:23.81#ibcon#flushed, iclass 36, count 0 2006.257.02:17:23.81#ibcon#about to write, iclass 36, count 0 2006.257.02:17:23.81#ibcon#wrote, iclass 36, count 0 2006.257.02:17:23.81#ibcon#about to read 3, iclass 36, count 0 2006.257.02:17:23.83#ibcon#read 3, iclass 36, count 0 2006.257.02:17:23.83#ibcon#about to read 4, iclass 36, count 0 2006.257.02:17:23.83#ibcon#read 4, iclass 36, count 0 2006.257.02:17:23.83#ibcon#about to read 5, iclass 36, count 0 2006.257.02:17:23.83#ibcon#read 5, iclass 36, count 0 2006.257.02:17:23.83#ibcon#about to read 6, iclass 36, count 0 2006.257.02:17:23.83#ibcon#read 6, iclass 36, count 0 2006.257.02:17:23.83#ibcon#end of sib2, iclass 36, count 0 2006.257.02:17:23.83#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:17:23.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:17:23.83#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:17:23.83#ibcon#*before write, iclass 36, count 0 2006.257.02:17:23.83#ibcon#enter sib2, iclass 36, count 0 2006.257.02:17:23.83#ibcon#flushed, iclass 36, count 0 2006.257.02:17:23.83#ibcon#about to write, iclass 36, count 0 2006.257.02:17:23.83#ibcon#wrote, iclass 36, count 0 2006.257.02:17:23.83#ibcon#about to read 3, iclass 36, count 0 2006.257.02:17:23.87#ibcon#read 3, iclass 36, count 0 2006.257.02:17:23.87#ibcon#about to read 4, iclass 36, count 0 2006.257.02:17:23.87#ibcon#read 4, iclass 36, count 0 2006.257.02:17:23.87#ibcon#about to read 5, iclass 36, count 0 2006.257.02:17:23.87#ibcon#read 5, iclass 36, count 0 2006.257.02:17:23.87#ibcon#about to read 6, iclass 36, count 0 2006.257.02:17:23.87#ibcon#read 6, iclass 36, count 0 2006.257.02:17:23.87#ibcon#end of sib2, iclass 36, count 0 2006.257.02:17:23.87#ibcon#*after write, iclass 36, count 0 2006.257.02:17:23.87#ibcon#*before return 0, iclass 36, count 0 2006.257.02:17:23.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:23.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:17:23.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:17:23.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:17:23.87$vck44/vb=2,5 2006.257.02:17:23.87#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.02:17:23.87#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.02:17:23.87#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:23.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:23.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:23.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:23.93#ibcon#enter wrdev, iclass 38, count 2 2006.257.02:17:23.93#ibcon#first serial, iclass 38, count 2 2006.257.02:17:23.93#ibcon#enter sib2, iclass 38, count 2 2006.257.02:17:23.93#ibcon#flushed, iclass 38, count 2 2006.257.02:17:23.93#ibcon#about to write, iclass 38, count 2 2006.257.02:17:23.93#ibcon#wrote, iclass 38, count 2 2006.257.02:17:23.93#ibcon#about to read 3, iclass 38, count 2 2006.257.02:17:23.95#ibcon#read 3, iclass 38, count 2 2006.257.02:17:23.95#ibcon#about to read 4, iclass 38, count 2 2006.257.02:17:23.95#ibcon#read 4, iclass 38, count 2 2006.257.02:17:23.95#ibcon#about to read 5, iclass 38, count 2 2006.257.02:17:23.95#ibcon#read 5, iclass 38, count 2 2006.257.02:17:23.95#ibcon#about to read 6, iclass 38, count 2 2006.257.02:17:23.95#ibcon#read 6, iclass 38, count 2 2006.257.02:17:23.95#ibcon#end of sib2, iclass 38, count 2 2006.257.02:17:23.95#ibcon#*mode == 0, iclass 38, count 2 2006.257.02:17:23.95#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.02:17:23.95#ibcon#[27=AT02-05\r\n] 2006.257.02:17:23.95#ibcon#*before write, iclass 38, count 2 2006.257.02:17:23.95#ibcon#enter sib2, iclass 38, count 2 2006.257.02:17:23.95#ibcon#flushed, iclass 38, count 2 2006.257.02:17:23.95#ibcon#about to write, iclass 38, count 2 2006.257.02:17:23.95#ibcon#wrote, iclass 38, count 2 2006.257.02:17:23.95#ibcon#about to read 3, iclass 38, count 2 2006.257.02:17:23.98#ibcon#read 3, iclass 38, count 2 2006.257.02:17:23.98#ibcon#about to read 4, iclass 38, count 2 2006.257.02:17:23.98#ibcon#read 4, iclass 38, count 2 2006.257.02:17:23.98#ibcon#about to read 5, iclass 38, count 2 2006.257.02:17:23.98#ibcon#read 5, iclass 38, count 2 2006.257.02:17:23.98#ibcon#about to read 6, iclass 38, count 2 2006.257.02:17:23.98#ibcon#read 6, iclass 38, count 2 2006.257.02:17:23.98#ibcon#end of sib2, iclass 38, count 2 2006.257.02:17:23.98#ibcon#*after write, iclass 38, count 2 2006.257.02:17:23.98#ibcon#*before return 0, iclass 38, count 2 2006.257.02:17:23.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:23.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:17:23.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.02:17:23.98#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:23.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:24.10#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:24.10#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:24.10#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:17:24.10#ibcon#first serial, iclass 38, count 0 2006.257.02:17:24.10#ibcon#enter sib2, iclass 38, count 0 2006.257.02:17:24.10#ibcon#flushed, iclass 38, count 0 2006.257.02:17:24.10#ibcon#about to write, iclass 38, count 0 2006.257.02:17:24.10#ibcon#wrote, iclass 38, count 0 2006.257.02:17:24.10#ibcon#about to read 3, iclass 38, count 0 2006.257.02:17:24.12#ibcon#read 3, iclass 38, count 0 2006.257.02:17:24.12#ibcon#about to read 4, iclass 38, count 0 2006.257.02:17:24.12#ibcon#read 4, iclass 38, count 0 2006.257.02:17:24.12#ibcon#about to read 5, iclass 38, count 0 2006.257.02:17:24.12#ibcon#read 5, iclass 38, count 0 2006.257.02:17:24.12#ibcon#about to read 6, iclass 38, count 0 2006.257.02:17:24.12#ibcon#read 6, iclass 38, count 0 2006.257.02:17:24.12#ibcon#end of sib2, iclass 38, count 0 2006.257.02:17:24.12#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:17:24.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:17:24.12#ibcon#[27=USB\r\n] 2006.257.02:17:24.12#ibcon#*before write, iclass 38, count 0 2006.257.02:17:24.12#ibcon#enter sib2, iclass 38, count 0 2006.257.02:17:24.12#ibcon#flushed, iclass 38, count 0 2006.257.02:17:24.12#ibcon#about to write, iclass 38, count 0 2006.257.02:17:24.12#ibcon#wrote, iclass 38, count 0 2006.257.02:17:24.12#ibcon#about to read 3, iclass 38, count 0 2006.257.02:17:24.15#ibcon#read 3, iclass 38, count 0 2006.257.02:17:24.15#ibcon#about to read 4, iclass 38, count 0 2006.257.02:17:24.15#ibcon#read 4, iclass 38, count 0 2006.257.02:17:24.15#ibcon#about to read 5, iclass 38, count 0 2006.257.02:17:24.15#ibcon#read 5, iclass 38, count 0 2006.257.02:17:24.15#ibcon#about to read 6, iclass 38, count 0 2006.257.02:17:24.15#ibcon#read 6, iclass 38, count 0 2006.257.02:17:24.15#ibcon#end of sib2, iclass 38, count 0 2006.257.02:17:24.15#ibcon#*after write, iclass 38, count 0 2006.257.02:17:24.15#ibcon#*before return 0, iclass 38, count 0 2006.257.02:17:24.15#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:24.15#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:17:24.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:17:24.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:17:24.15$vck44/vblo=3,649.99 2006.257.02:17:24.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.02:17:24.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.02:17:24.15#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:24.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:24.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:24.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:24.15#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:17:24.15#ibcon#first serial, iclass 40, count 0 2006.257.02:17:24.15#ibcon#enter sib2, iclass 40, count 0 2006.257.02:17:24.15#ibcon#flushed, iclass 40, count 0 2006.257.02:17:24.15#ibcon#about to write, iclass 40, count 0 2006.257.02:17:24.15#ibcon#wrote, iclass 40, count 0 2006.257.02:17:24.15#ibcon#about to read 3, iclass 40, count 0 2006.257.02:17:24.17#ibcon#read 3, iclass 40, count 0 2006.257.02:17:24.17#ibcon#about to read 4, iclass 40, count 0 2006.257.02:17:24.17#ibcon#read 4, iclass 40, count 0 2006.257.02:17:24.17#ibcon#about to read 5, iclass 40, count 0 2006.257.02:17:24.17#ibcon#read 5, iclass 40, count 0 2006.257.02:17:24.17#ibcon#about to read 6, iclass 40, count 0 2006.257.02:17:24.17#ibcon#read 6, iclass 40, count 0 2006.257.02:17:24.17#ibcon#end of sib2, iclass 40, count 0 2006.257.02:17:24.17#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:17:24.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:17:24.17#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:17:24.17#ibcon#*before write, iclass 40, count 0 2006.257.02:17:24.17#ibcon#enter sib2, iclass 40, count 0 2006.257.02:17:24.17#ibcon#flushed, iclass 40, count 0 2006.257.02:17:24.17#ibcon#about to write, iclass 40, count 0 2006.257.02:17:24.17#ibcon#wrote, iclass 40, count 0 2006.257.02:17:24.17#ibcon#about to read 3, iclass 40, count 0 2006.257.02:17:24.21#ibcon#read 3, iclass 40, count 0 2006.257.02:17:24.21#ibcon#about to read 4, iclass 40, count 0 2006.257.02:17:24.21#ibcon#read 4, iclass 40, count 0 2006.257.02:17:24.21#ibcon#about to read 5, iclass 40, count 0 2006.257.02:17:24.21#ibcon#read 5, iclass 40, count 0 2006.257.02:17:24.21#ibcon#about to read 6, iclass 40, count 0 2006.257.02:17:24.21#ibcon#read 6, iclass 40, count 0 2006.257.02:17:24.21#ibcon#end of sib2, iclass 40, count 0 2006.257.02:17:24.21#ibcon#*after write, iclass 40, count 0 2006.257.02:17:24.21#ibcon#*before return 0, iclass 40, count 0 2006.257.02:17:24.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:24.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:17:24.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:17:24.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:17:24.21$vck44/vb=3,4 2006.257.02:17:24.21#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.02:17:24.21#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.02:17:24.21#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:24.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:24.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:24.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:24.27#ibcon#enter wrdev, iclass 4, count 2 2006.257.02:17:24.27#ibcon#first serial, iclass 4, count 2 2006.257.02:17:24.27#ibcon#enter sib2, iclass 4, count 2 2006.257.02:17:24.27#ibcon#flushed, iclass 4, count 2 2006.257.02:17:24.27#ibcon#about to write, iclass 4, count 2 2006.257.02:17:24.27#ibcon#wrote, iclass 4, count 2 2006.257.02:17:24.27#ibcon#about to read 3, iclass 4, count 2 2006.257.02:17:24.29#ibcon#read 3, iclass 4, count 2 2006.257.02:17:24.29#ibcon#about to read 4, iclass 4, count 2 2006.257.02:17:24.29#ibcon#read 4, iclass 4, count 2 2006.257.02:17:24.29#ibcon#about to read 5, iclass 4, count 2 2006.257.02:17:24.29#ibcon#read 5, iclass 4, count 2 2006.257.02:17:24.29#ibcon#about to read 6, iclass 4, count 2 2006.257.02:17:24.29#ibcon#read 6, iclass 4, count 2 2006.257.02:17:24.29#ibcon#end of sib2, iclass 4, count 2 2006.257.02:17:24.29#ibcon#*mode == 0, iclass 4, count 2 2006.257.02:17:24.29#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.02:17:24.29#ibcon#[27=AT03-04\r\n] 2006.257.02:17:24.29#ibcon#*before write, iclass 4, count 2 2006.257.02:17:24.29#ibcon#enter sib2, iclass 4, count 2 2006.257.02:17:24.29#ibcon#flushed, iclass 4, count 2 2006.257.02:17:24.29#ibcon#about to write, iclass 4, count 2 2006.257.02:17:24.29#ibcon#wrote, iclass 4, count 2 2006.257.02:17:24.29#ibcon#about to read 3, iclass 4, count 2 2006.257.02:17:24.32#ibcon#read 3, iclass 4, count 2 2006.257.02:17:24.32#ibcon#about to read 4, iclass 4, count 2 2006.257.02:17:24.32#ibcon#read 4, iclass 4, count 2 2006.257.02:17:24.32#ibcon#about to read 5, iclass 4, count 2 2006.257.02:17:24.32#ibcon#read 5, iclass 4, count 2 2006.257.02:17:24.32#ibcon#about to read 6, iclass 4, count 2 2006.257.02:17:24.32#ibcon#read 6, iclass 4, count 2 2006.257.02:17:24.32#ibcon#end of sib2, iclass 4, count 2 2006.257.02:17:24.32#ibcon#*after write, iclass 4, count 2 2006.257.02:17:24.32#ibcon#*before return 0, iclass 4, count 2 2006.257.02:17:24.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:24.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:17:24.32#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.02:17:24.32#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:24.32#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:24.44#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:24.44#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:24.44#ibcon#enter wrdev, iclass 4, count 0 2006.257.02:17:24.44#ibcon#first serial, iclass 4, count 0 2006.257.02:17:24.44#ibcon#enter sib2, iclass 4, count 0 2006.257.02:17:24.44#ibcon#flushed, iclass 4, count 0 2006.257.02:17:24.44#ibcon#about to write, iclass 4, count 0 2006.257.02:17:24.44#ibcon#wrote, iclass 4, count 0 2006.257.02:17:24.44#ibcon#about to read 3, iclass 4, count 0 2006.257.02:17:24.46#ibcon#read 3, iclass 4, count 0 2006.257.02:17:24.46#ibcon#about to read 4, iclass 4, count 0 2006.257.02:17:24.46#ibcon#read 4, iclass 4, count 0 2006.257.02:17:24.46#ibcon#about to read 5, iclass 4, count 0 2006.257.02:17:24.46#ibcon#read 5, iclass 4, count 0 2006.257.02:17:24.46#ibcon#about to read 6, iclass 4, count 0 2006.257.02:17:24.46#ibcon#read 6, iclass 4, count 0 2006.257.02:17:24.46#ibcon#end of sib2, iclass 4, count 0 2006.257.02:17:24.46#ibcon#*mode == 0, iclass 4, count 0 2006.257.02:17:24.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.02:17:24.46#ibcon#[27=USB\r\n] 2006.257.02:17:24.46#ibcon#*before write, iclass 4, count 0 2006.257.02:17:24.46#ibcon#enter sib2, iclass 4, count 0 2006.257.02:17:24.46#ibcon#flushed, iclass 4, count 0 2006.257.02:17:24.46#ibcon#about to write, iclass 4, count 0 2006.257.02:17:24.46#ibcon#wrote, iclass 4, count 0 2006.257.02:17:24.46#ibcon#about to read 3, iclass 4, count 0 2006.257.02:17:24.49#ibcon#read 3, iclass 4, count 0 2006.257.02:17:24.49#ibcon#about to read 4, iclass 4, count 0 2006.257.02:17:24.49#ibcon#read 4, iclass 4, count 0 2006.257.02:17:24.49#ibcon#about to read 5, iclass 4, count 0 2006.257.02:17:24.49#ibcon#read 5, iclass 4, count 0 2006.257.02:17:24.49#ibcon#about to read 6, iclass 4, count 0 2006.257.02:17:24.49#ibcon#read 6, iclass 4, count 0 2006.257.02:17:24.49#ibcon#end of sib2, iclass 4, count 0 2006.257.02:17:24.49#ibcon#*after write, iclass 4, count 0 2006.257.02:17:24.49#ibcon#*before return 0, iclass 4, count 0 2006.257.02:17:24.49#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:24.49#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:17:24.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.02:17:24.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.02:17:24.49$vck44/vblo=4,679.99 2006.257.02:17:24.49#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.02:17:24.49#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.02:17:24.49#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:24.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:24.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:24.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:24.49#ibcon#enter wrdev, iclass 6, count 0 2006.257.02:17:24.49#ibcon#first serial, iclass 6, count 0 2006.257.02:17:24.49#ibcon#enter sib2, iclass 6, count 0 2006.257.02:17:24.49#ibcon#flushed, iclass 6, count 0 2006.257.02:17:24.49#ibcon#about to write, iclass 6, count 0 2006.257.02:17:24.49#ibcon#wrote, iclass 6, count 0 2006.257.02:17:24.49#ibcon#about to read 3, iclass 6, count 0 2006.257.02:17:24.51#ibcon#read 3, iclass 6, count 0 2006.257.02:17:24.51#ibcon#about to read 4, iclass 6, count 0 2006.257.02:17:24.51#ibcon#read 4, iclass 6, count 0 2006.257.02:17:24.51#ibcon#about to read 5, iclass 6, count 0 2006.257.02:17:24.51#ibcon#read 5, iclass 6, count 0 2006.257.02:17:24.51#ibcon#about to read 6, iclass 6, count 0 2006.257.02:17:24.51#ibcon#read 6, iclass 6, count 0 2006.257.02:17:24.51#ibcon#end of sib2, iclass 6, count 0 2006.257.02:17:24.51#ibcon#*mode == 0, iclass 6, count 0 2006.257.02:17:24.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.02:17:24.51#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:17:24.51#ibcon#*before write, iclass 6, count 0 2006.257.02:17:24.51#ibcon#enter sib2, iclass 6, count 0 2006.257.02:17:24.51#ibcon#flushed, iclass 6, count 0 2006.257.02:17:24.51#ibcon#about to write, iclass 6, count 0 2006.257.02:17:24.51#ibcon#wrote, iclass 6, count 0 2006.257.02:17:24.51#ibcon#about to read 3, iclass 6, count 0 2006.257.02:17:24.55#ibcon#read 3, iclass 6, count 0 2006.257.02:17:24.55#ibcon#about to read 4, iclass 6, count 0 2006.257.02:17:24.55#ibcon#read 4, iclass 6, count 0 2006.257.02:17:24.55#ibcon#about to read 5, iclass 6, count 0 2006.257.02:17:24.55#ibcon#read 5, iclass 6, count 0 2006.257.02:17:24.55#ibcon#about to read 6, iclass 6, count 0 2006.257.02:17:24.55#ibcon#read 6, iclass 6, count 0 2006.257.02:17:24.55#ibcon#end of sib2, iclass 6, count 0 2006.257.02:17:24.55#ibcon#*after write, iclass 6, count 0 2006.257.02:17:24.55#ibcon#*before return 0, iclass 6, count 0 2006.257.02:17:24.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:24.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:17:24.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.02:17:24.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.02:17:24.55$vck44/vb=4,5 2006.257.02:17:24.55#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.02:17:24.55#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.02:17:24.55#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:24.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:24.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:24.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:24.61#ibcon#enter wrdev, iclass 10, count 2 2006.257.02:17:24.61#ibcon#first serial, iclass 10, count 2 2006.257.02:17:24.61#ibcon#enter sib2, iclass 10, count 2 2006.257.02:17:24.61#ibcon#flushed, iclass 10, count 2 2006.257.02:17:24.61#ibcon#about to write, iclass 10, count 2 2006.257.02:17:24.61#ibcon#wrote, iclass 10, count 2 2006.257.02:17:24.61#ibcon#about to read 3, iclass 10, count 2 2006.257.02:17:24.63#ibcon#read 3, iclass 10, count 2 2006.257.02:17:24.63#ibcon#about to read 4, iclass 10, count 2 2006.257.02:17:24.63#ibcon#read 4, iclass 10, count 2 2006.257.02:17:24.63#ibcon#about to read 5, iclass 10, count 2 2006.257.02:17:24.63#ibcon#read 5, iclass 10, count 2 2006.257.02:17:24.63#ibcon#about to read 6, iclass 10, count 2 2006.257.02:17:24.63#ibcon#read 6, iclass 10, count 2 2006.257.02:17:24.63#ibcon#end of sib2, iclass 10, count 2 2006.257.02:17:24.63#ibcon#*mode == 0, iclass 10, count 2 2006.257.02:17:24.63#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.02:17:24.63#ibcon#[27=AT04-05\r\n] 2006.257.02:17:24.63#ibcon#*before write, iclass 10, count 2 2006.257.02:17:24.63#ibcon#enter sib2, iclass 10, count 2 2006.257.02:17:24.63#ibcon#flushed, iclass 10, count 2 2006.257.02:17:24.63#ibcon#about to write, iclass 10, count 2 2006.257.02:17:24.63#ibcon#wrote, iclass 10, count 2 2006.257.02:17:24.63#ibcon#about to read 3, iclass 10, count 2 2006.257.02:17:24.66#ibcon#read 3, iclass 10, count 2 2006.257.02:17:24.66#ibcon#about to read 4, iclass 10, count 2 2006.257.02:17:24.66#ibcon#read 4, iclass 10, count 2 2006.257.02:17:24.66#ibcon#about to read 5, iclass 10, count 2 2006.257.02:17:24.66#ibcon#read 5, iclass 10, count 2 2006.257.02:17:24.66#ibcon#about to read 6, iclass 10, count 2 2006.257.02:17:24.66#ibcon#read 6, iclass 10, count 2 2006.257.02:17:24.66#ibcon#end of sib2, iclass 10, count 2 2006.257.02:17:24.66#ibcon#*after write, iclass 10, count 2 2006.257.02:17:24.66#ibcon#*before return 0, iclass 10, count 2 2006.257.02:17:24.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:24.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:17:24.66#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.02:17:24.66#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:24.66#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:24.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:24.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:24.78#ibcon#enter wrdev, iclass 10, count 0 2006.257.02:17:24.78#ibcon#first serial, iclass 10, count 0 2006.257.02:17:24.78#ibcon#enter sib2, iclass 10, count 0 2006.257.02:17:24.78#ibcon#flushed, iclass 10, count 0 2006.257.02:17:24.78#ibcon#about to write, iclass 10, count 0 2006.257.02:17:24.78#ibcon#wrote, iclass 10, count 0 2006.257.02:17:24.78#ibcon#about to read 3, iclass 10, count 0 2006.257.02:17:24.80#ibcon#read 3, iclass 10, count 0 2006.257.02:17:24.80#ibcon#about to read 4, iclass 10, count 0 2006.257.02:17:24.80#ibcon#read 4, iclass 10, count 0 2006.257.02:17:24.80#ibcon#about to read 5, iclass 10, count 0 2006.257.02:17:24.80#ibcon#read 5, iclass 10, count 0 2006.257.02:17:24.80#ibcon#about to read 6, iclass 10, count 0 2006.257.02:17:24.80#ibcon#read 6, iclass 10, count 0 2006.257.02:17:24.80#ibcon#end of sib2, iclass 10, count 0 2006.257.02:17:24.80#ibcon#*mode == 0, iclass 10, count 0 2006.257.02:17:24.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.02:17:24.80#ibcon#[27=USB\r\n] 2006.257.02:17:24.80#ibcon#*before write, iclass 10, count 0 2006.257.02:17:24.80#ibcon#enter sib2, iclass 10, count 0 2006.257.02:17:24.80#ibcon#flushed, iclass 10, count 0 2006.257.02:17:24.80#ibcon#about to write, iclass 10, count 0 2006.257.02:17:24.80#ibcon#wrote, iclass 10, count 0 2006.257.02:17:24.80#ibcon#about to read 3, iclass 10, count 0 2006.257.02:17:24.83#ibcon#read 3, iclass 10, count 0 2006.257.02:17:24.83#ibcon#about to read 4, iclass 10, count 0 2006.257.02:17:24.83#ibcon#read 4, iclass 10, count 0 2006.257.02:17:24.83#ibcon#about to read 5, iclass 10, count 0 2006.257.02:17:24.83#ibcon#read 5, iclass 10, count 0 2006.257.02:17:24.83#ibcon#about to read 6, iclass 10, count 0 2006.257.02:17:24.83#ibcon#read 6, iclass 10, count 0 2006.257.02:17:24.83#ibcon#end of sib2, iclass 10, count 0 2006.257.02:17:24.83#ibcon#*after write, iclass 10, count 0 2006.257.02:17:24.83#ibcon#*before return 0, iclass 10, count 0 2006.257.02:17:24.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:24.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:17:24.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.02:17:24.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.02:17:24.83$vck44/vblo=5,709.99 2006.257.02:17:24.83#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.02:17:24.83#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.02:17:24.83#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:24.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:24.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:24.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:24.83#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:17:24.83#ibcon#first serial, iclass 12, count 0 2006.257.02:17:24.83#ibcon#enter sib2, iclass 12, count 0 2006.257.02:17:24.83#ibcon#flushed, iclass 12, count 0 2006.257.02:17:24.83#ibcon#about to write, iclass 12, count 0 2006.257.02:17:24.83#ibcon#wrote, iclass 12, count 0 2006.257.02:17:24.83#ibcon#about to read 3, iclass 12, count 0 2006.257.02:17:24.85#ibcon#read 3, iclass 12, count 0 2006.257.02:17:24.85#ibcon#about to read 4, iclass 12, count 0 2006.257.02:17:24.85#ibcon#read 4, iclass 12, count 0 2006.257.02:17:24.85#ibcon#about to read 5, iclass 12, count 0 2006.257.02:17:24.85#ibcon#read 5, iclass 12, count 0 2006.257.02:17:24.85#ibcon#about to read 6, iclass 12, count 0 2006.257.02:17:24.85#ibcon#read 6, iclass 12, count 0 2006.257.02:17:24.85#ibcon#end of sib2, iclass 12, count 0 2006.257.02:17:24.85#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:17:24.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:17:24.85#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:17:24.85#ibcon#*before write, iclass 12, count 0 2006.257.02:17:24.85#ibcon#enter sib2, iclass 12, count 0 2006.257.02:17:24.85#ibcon#flushed, iclass 12, count 0 2006.257.02:17:24.85#ibcon#about to write, iclass 12, count 0 2006.257.02:17:24.85#ibcon#wrote, iclass 12, count 0 2006.257.02:17:24.85#ibcon#about to read 3, iclass 12, count 0 2006.257.02:17:24.89#ibcon#read 3, iclass 12, count 0 2006.257.02:17:24.89#ibcon#about to read 4, iclass 12, count 0 2006.257.02:17:24.89#ibcon#read 4, iclass 12, count 0 2006.257.02:17:24.89#ibcon#about to read 5, iclass 12, count 0 2006.257.02:17:24.89#ibcon#read 5, iclass 12, count 0 2006.257.02:17:24.89#ibcon#about to read 6, iclass 12, count 0 2006.257.02:17:24.89#ibcon#read 6, iclass 12, count 0 2006.257.02:17:24.89#ibcon#end of sib2, iclass 12, count 0 2006.257.02:17:24.89#ibcon#*after write, iclass 12, count 0 2006.257.02:17:24.89#ibcon#*before return 0, iclass 12, count 0 2006.257.02:17:24.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:24.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:17:24.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:17:24.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:17:24.89$vck44/vb=5,4 2006.257.02:17:24.89#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.02:17:24.89#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.02:17:24.89#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:24.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:24.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:24.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:24.95#ibcon#enter wrdev, iclass 14, count 2 2006.257.02:17:24.95#ibcon#first serial, iclass 14, count 2 2006.257.02:17:24.95#ibcon#enter sib2, iclass 14, count 2 2006.257.02:17:24.95#ibcon#flushed, iclass 14, count 2 2006.257.02:17:24.95#ibcon#about to write, iclass 14, count 2 2006.257.02:17:24.95#ibcon#wrote, iclass 14, count 2 2006.257.02:17:24.95#ibcon#about to read 3, iclass 14, count 2 2006.257.02:17:24.97#ibcon#read 3, iclass 14, count 2 2006.257.02:17:24.97#ibcon#about to read 4, iclass 14, count 2 2006.257.02:17:24.97#ibcon#read 4, iclass 14, count 2 2006.257.02:17:24.97#ibcon#about to read 5, iclass 14, count 2 2006.257.02:17:24.97#ibcon#read 5, iclass 14, count 2 2006.257.02:17:24.97#ibcon#about to read 6, iclass 14, count 2 2006.257.02:17:24.97#ibcon#read 6, iclass 14, count 2 2006.257.02:17:24.97#ibcon#end of sib2, iclass 14, count 2 2006.257.02:17:24.97#ibcon#*mode == 0, iclass 14, count 2 2006.257.02:17:24.97#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.02:17:24.97#ibcon#[27=AT05-04\r\n] 2006.257.02:17:24.97#ibcon#*before write, iclass 14, count 2 2006.257.02:17:24.97#ibcon#enter sib2, iclass 14, count 2 2006.257.02:17:24.97#ibcon#flushed, iclass 14, count 2 2006.257.02:17:24.97#ibcon#about to write, iclass 14, count 2 2006.257.02:17:24.97#ibcon#wrote, iclass 14, count 2 2006.257.02:17:24.97#ibcon#about to read 3, iclass 14, count 2 2006.257.02:17:25.00#ibcon#read 3, iclass 14, count 2 2006.257.02:17:25.00#ibcon#about to read 4, iclass 14, count 2 2006.257.02:17:25.00#ibcon#read 4, iclass 14, count 2 2006.257.02:17:25.00#ibcon#about to read 5, iclass 14, count 2 2006.257.02:17:25.00#ibcon#read 5, iclass 14, count 2 2006.257.02:17:25.00#ibcon#about to read 6, iclass 14, count 2 2006.257.02:17:25.00#ibcon#read 6, iclass 14, count 2 2006.257.02:17:25.00#ibcon#end of sib2, iclass 14, count 2 2006.257.02:17:25.00#ibcon#*after write, iclass 14, count 2 2006.257.02:17:25.00#ibcon#*before return 0, iclass 14, count 2 2006.257.02:17:25.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:25.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:17:25.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.02:17:25.00#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:25.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:25.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:25.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:25.12#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:17:25.12#ibcon#first serial, iclass 14, count 0 2006.257.02:17:25.12#ibcon#enter sib2, iclass 14, count 0 2006.257.02:17:25.12#ibcon#flushed, iclass 14, count 0 2006.257.02:17:25.12#ibcon#about to write, iclass 14, count 0 2006.257.02:17:25.12#ibcon#wrote, iclass 14, count 0 2006.257.02:17:25.12#ibcon#about to read 3, iclass 14, count 0 2006.257.02:17:25.14#ibcon#read 3, iclass 14, count 0 2006.257.02:17:25.14#ibcon#about to read 4, iclass 14, count 0 2006.257.02:17:25.14#ibcon#read 4, iclass 14, count 0 2006.257.02:17:25.14#ibcon#about to read 5, iclass 14, count 0 2006.257.02:17:25.14#ibcon#read 5, iclass 14, count 0 2006.257.02:17:25.14#ibcon#about to read 6, iclass 14, count 0 2006.257.02:17:25.14#ibcon#read 6, iclass 14, count 0 2006.257.02:17:25.14#ibcon#end of sib2, iclass 14, count 0 2006.257.02:17:25.14#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:17:25.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:17:25.14#ibcon#[27=USB\r\n] 2006.257.02:17:25.14#ibcon#*before write, iclass 14, count 0 2006.257.02:17:25.14#ibcon#enter sib2, iclass 14, count 0 2006.257.02:17:25.14#ibcon#flushed, iclass 14, count 0 2006.257.02:17:25.14#ibcon#about to write, iclass 14, count 0 2006.257.02:17:25.14#ibcon#wrote, iclass 14, count 0 2006.257.02:17:25.14#ibcon#about to read 3, iclass 14, count 0 2006.257.02:17:25.17#ibcon#read 3, iclass 14, count 0 2006.257.02:17:25.17#ibcon#about to read 4, iclass 14, count 0 2006.257.02:17:25.17#ibcon#read 4, iclass 14, count 0 2006.257.02:17:25.17#ibcon#about to read 5, iclass 14, count 0 2006.257.02:17:25.17#ibcon#read 5, iclass 14, count 0 2006.257.02:17:25.17#ibcon#about to read 6, iclass 14, count 0 2006.257.02:17:25.17#ibcon#read 6, iclass 14, count 0 2006.257.02:17:25.17#ibcon#end of sib2, iclass 14, count 0 2006.257.02:17:25.17#ibcon#*after write, iclass 14, count 0 2006.257.02:17:25.17#ibcon#*before return 0, iclass 14, count 0 2006.257.02:17:25.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:25.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:17:25.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:17:25.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:17:25.17$vck44/vblo=6,719.99 2006.257.02:17:25.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.02:17:25.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.02:17:25.17#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:25.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:25.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:25.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:25.17#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:17:25.17#ibcon#first serial, iclass 16, count 0 2006.257.02:17:25.17#ibcon#enter sib2, iclass 16, count 0 2006.257.02:17:25.17#ibcon#flushed, iclass 16, count 0 2006.257.02:17:25.17#ibcon#about to write, iclass 16, count 0 2006.257.02:17:25.17#ibcon#wrote, iclass 16, count 0 2006.257.02:17:25.17#ibcon#about to read 3, iclass 16, count 0 2006.257.02:17:25.19#ibcon#read 3, iclass 16, count 0 2006.257.02:17:25.19#ibcon#about to read 4, iclass 16, count 0 2006.257.02:17:25.19#ibcon#read 4, iclass 16, count 0 2006.257.02:17:25.19#ibcon#about to read 5, iclass 16, count 0 2006.257.02:17:25.19#ibcon#read 5, iclass 16, count 0 2006.257.02:17:25.19#ibcon#about to read 6, iclass 16, count 0 2006.257.02:17:25.19#ibcon#read 6, iclass 16, count 0 2006.257.02:17:25.19#ibcon#end of sib2, iclass 16, count 0 2006.257.02:17:25.19#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:17:25.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:17:25.19#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:17:25.19#ibcon#*before write, iclass 16, count 0 2006.257.02:17:25.19#ibcon#enter sib2, iclass 16, count 0 2006.257.02:17:25.19#ibcon#flushed, iclass 16, count 0 2006.257.02:17:25.19#ibcon#about to write, iclass 16, count 0 2006.257.02:17:25.19#ibcon#wrote, iclass 16, count 0 2006.257.02:17:25.19#ibcon#about to read 3, iclass 16, count 0 2006.257.02:17:25.23#ibcon#read 3, iclass 16, count 0 2006.257.02:17:25.23#ibcon#about to read 4, iclass 16, count 0 2006.257.02:17:25.23#ibcon#read 4, iclass 16, count 0 2006.257.02:17:25.23#ibcon#about to read 5, iclass 16, count 0 2006.257.02:17:25.23#ibcon#read 5, iclass 16, count 0 2006.257.02:17:25.23#ibcon#about to read 6, iclass 16, count 0 2006.257.02:17:25.23#ibcon#read 6, iclass 16, count 0 2006.257.02:17:25.23#ibcon#end of sib2, iclass 16, count 0 2006.257.02:17:25.23#ibcon#*after write, iclass 16, count 0 2006.257.02:17:25.23#ibcon#*before return 0, iclass 16, count 0 2006.257.02:17:25.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:25.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:17:25.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:17:25.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:17:25.23$vck44/vb=6,4 2006.257.02:17:25.23#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.02:17:25.23#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.02:17:25.23#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:25.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:25.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:25.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:25.29#ibcon#enter wrdev, iclass 18, count 2 2006.257.02:17:25.29#ibcon#first serial, iclass 18, count 2 2006.257.02:17:25.29#ibcon#enter sib2, iclass 18, count 2 2006.257.02:17:25.29#ibcon#flushed, iclass 18, count 2 2006.257.02:17:25.29#ibcon#about to write, iclass 18, count 2 2006.257.02:17:25.29#ibcon#wrote, iclass 18, count 2 2006.257.02:17:25.29#ibcon#about to read 3, iclass 18, count 2 2006.257.02:17:25.31#ibcon#read 3, iclass 18, count 2 2006.257.02:17:25.31#ibcon#about to read 4, iclass 18, count 2 2006.257.02:17:25.31#ibcon#read 4, iclass 18, count 2 2006.257.02:17:25.31#ibcon#about to read 5, iclass 18, count 2 2006.257.02:17:25.31#ibcon#read 5, iclass 18, count 2 2006.257.02:17:25.31#ibcon#about to read 6, iclass 18, count 2 2006.257.02:17:25.31#ibcon#read 6, iclass 18, count 2 2006.257.02:17:25.31#ibcon#end of sib2, iclass 18, count 2 2006.257.02:17:25.31#ibcon#*mode == 0, iclass 18, count 2 2006.257.02:17:25.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.02:17:25.31#ibcon#[27=AT06-04\r\n] 2006.257.02:17:25.31#ibcon#*before write, iclass 18, count 2 2006.257.02:17:25.31#ibcon#enter sib2, iclass 18, count 2 2006.257.02:17:25.31#ibcon#flushed, iclass 18, count 2 2006.257.02:17:25.31#ibcon#about to write, iclass 18, count 2 2006.257.02:17:25.31#ibcon#wrote, iclass 18, count 2 2006.257.02:17:25.31#ibcon#about to read 3, iclass 18, count 2 2006.257.02:17:25.34#ibcon#read 3, iclass 18, count 2 2006.257.02:17:25.34#ibcon#about to read 4, iclass 18, count 2 2006.257.02:17:25.34#ibcon#read 4, iclass 18, count 2 2006.257.02:17:25.34#ibcon#about to read 5, iclass 18, count 2 2006.257.02:17:25.34#ibcon#read 5, iclass 18, count 2 2006.257.02:17:25.34#ibcon#about to read 6, iclass 18, count 2 2006.257.02:17:25.34#ibcon#read 6, iclass 18, count 2 2006.257.02:17:25.34#ibcon#end of sib2, iclass 18, count 2 2006.257.02:17:25.34#ibcon#*after write, iclass 18, count 2 2006.257.02:17:25.34#ibcon#*before return 0, iclass 18, count 2 2006.257.02:17:25.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:25.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:17:25.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.02:17:25.34#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:25.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:25.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:25.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:25.46#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:17:25.46#ibcon#first serial, iclass 18, count 0 2006.257.02:17:25.46#ibcon#enter sib2, iclass 18, count 0 2006.257.02:17:25.46#ibcon#flushed, iclass 18, count 0 2006.257.02:17:25.46#ibcon#about to write, iclass 18, count 0 2006.257.02:17:25.46#ibcon#wrote, iclass 18, count 0 2006.257.02:17:25.46#ibcon#about to read 3, iclass 18, count 0 2006.257.02:17:25.48#ibcon#read 3, iclass 18, count 0 2006.257.02:17:25.48#ibcon#about to read 4, iclass 18, count 0 2006.257.02:17:25.48#ibcon#read 4, iclass 18, count 0 2006.257.02:17:25.48#ibcon#about to read 5, iclass 18, count 0 2006.257.02:17:25.48#ibcon#read 5, iclass 18, count 0 2006.257.02:17:25.48#ibcon#about to read 6, iclass 18, count 0 2006.257.02:17:25.48#ibcon#read 6, iclass 18, count 0 2006.257.02:17:25.48#ibcon#end of sib2, iclass 18, count 0 2006.257.02:17:25.48#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:17:25.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:17:25.48#ibcon#[27=USB\r\n] 2006.257.02:17:25.48#ibcon#*before write, iclass 18, count 0 2006.257.02:17:25.48#ibcon#enter sib2, iclass 18, count 0 2006.257.02:17:25.48#ibcon#flushed, iclass 18, count 0 2006.257.02:17:25.48#ibcon#about to write, iclass 18, count 0 2006.257.02:17:25.48#ibcon#wrote, iclass 18, count 0 2006.257.02:17:25.48#ibcon#about to read 3, iclass 18, count 0 2006.257.02:17:25.51#ibcon#read 3, iclass 18, count 0 2006.257.02:17:25.51#ibcon#about to read 4, iclass 18, count 0 2006.257.02:17:25.51#ibcon#read 4, iclass 18, count 0 2006.257.02:17:25.51#ibcon#about to read 5, iclass 18, count 0 2006.257.02:17:25.51#ibcon#read 5, iclass 18, count 0 2006.257.02:17:25.51#ibcon#about to read 6, iclass 18, count 0 2006.257.02:17:25.51#ibcon#read 6, iclass 18, count 0 2006.257.02:17:25.51#ibcon#end of sib2, iclass 18, count 0 2006.257.02:17:25.51#ibcon#*after write, iclass 18, count 0 2006.257.02:17:25.51#ibcon#*before return 0, iclass 18, count 0 2006.257.02:17:25.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:25.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:17:25.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:17:25.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:17:25.51$vck44/vblo=7,734.99 2006.257.02:17:25.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.02:17:25.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.02:17:25.51#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:25.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:25.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:25.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:25.51#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:17:25.51#ibcon#first serial, iclass 20, count 0 2006.257.02:17:25.51#ibcon#enter sib2, iclass 20, count 0 2006.257.02:17:25.51#ibcon#flushed, iclass 20, count 0 2006.257.02:17:25.51#ibcon#about to write, iclass 20, count 0 2006.257.02:17:25.51#ibcon#wrote, iclass 20, count 0 2006.257.02:17:25.51#ibcon#about to read 3, iclass 20, count 0 2006.257.02:17:25.53#ibcon#read 3, iclass 20, count 0 2006.257.02:17:25.53#ibcon#about to read 4, iclass 20, count 0 2006.257.02:17:25.53#ibcon#read 4, iclass 20, count 0 2006.257.02:17:25.53#ibcon#about to read 5, iclass 20, count 0 2006.257.02:17:25.53#ibcon#read 5, iclass 20, count 0 2006.257.02:17:25.53#ibcon#about to read 6, iclass 20, count 0 2006.257.02:17:25.53#ibcon#read 6, iclass 20, count 0 2006.257.02:17:25.53#ibcon#end of sib2, iclass 20, count 0 2006.257.02:17:25.53#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:17:25.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:17:25.53#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:17:25.53#ibcon#*before write, iclass 20, count 0 2006.257.02:17:25.53#ibcon#enter sib2, iclass 20, count 0 2006.257.02:17:25.53#ibcon#flushed, iclass 20, count 0 2006.257.02:17:25.53#ibcon#about to write, iclass 20, count 0 2006.257.02:17:25.53#ibcon#wrote, iclass 20, count 0 2006.257.02:17:25.53#ibcon#about to read 3, iclass 20, count 0 2006.257.02:17:25.57#ibcon#read 3, iclass 20, count 0 2006.257.02:17:25.57#ibcon#about to read 4, iclass 20, count 0 2006.257.02:17:25.57#ibcon#read 4, iclass 20, count 0 2006.257.02:17:25.57#ibcon#about to read 5, iclass 20, count 0 2006.257.02:17:25.57#ibcon#read 5, iclass 20, count 0 2006.257.02:17:25.57#ibcon#about to read 6, iclass 20, count 0 2006.257.02:17:25.57#ibcon#read 6, iclass 20, count 0 2006.257.02:17:25.57#ibcon#end of sib2, iclass 20, count 0 2006.257.02:17:25.57#ibcon#*after write, iclass 20, count 0 2006.257.02:17:25.57#ibcon#*before return 0, iclass 20, count 0 2006.257.02:17:25.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:25.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:17:25.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:17:25.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:17:25.57$vck44/vb=7,4 2006.257.02:17:25.57#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.02:17:25.57#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.02:17:25.57#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:25.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:25.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:25.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:25.63#ibcon#enter wrdev, iclass 22, count 2 2006.257.02:17:25.63#ibcon#first serial, iclass 22, count 2 2006.257.02:17:25.63#ibcon#enter sib2, iclass 22, count 2 2006.257.02:17:25.63#ibcon#flushed, iclass 22, count 2 2006.257.02:17:25.63#ibcon#about to write, iclass 22, count 2 2006.257.02:17:25.63#ibcon#wrote, iclass 22, count 2 2006.257.02:17:25.63#ibcon#about to read 3, iclass 22, count 2 2006.257.02:17:25.65#ibcon#read 3, iclass 22, count 2 2006.257.02:17:25.65#ibcon#about to read 4, iclass 22, count 2 2006.257.02:17:25.65#ibcon#read 4, iclass 22, count 2 2006.257.02:17:25.65#ibcon#about to read 5, iclass 22, count 2 2006.257.02:17:25.65#ibcon#read 5, iclass 22, count 2 2006.257.02:17:25.65#ibcon#about to read 6, iclass 22, count 2 2006.257.02:17:25.65#ibcon#read 6, iclass 22, count 2 2006.257.02:17:25.65#ibcon#end of sib2, iclass 22, count 2 2006.257.02:17:25.65#ibcon#*mode == 0, iclass 22, count 2 2006.257.02:17:25.65#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.02:17:25.65#ibcon#[27=AT07-04\r\n] 2006.257.02:17:25.65#ibcon#*before write, iclass 22, count 2 2006.257.02:17:25.65#ibcon#enter sib2, iclass 22, count 2 2006.257.02:17:25.65#ibcon#flushed, iclass 22, count 2 2006.257.02:17:25.65#ibcon#about to write, iclass 22, count 2 2006.257.02:17:25.65#ibcon#wrote, iclass 22, count 2 2006.257.02:17:25.65#ibcon#about to read 3, iclass 22, count 2 2006.257.02:17:25.68#ibcon#read 3, iclass 22, count 2 2006.257.02:17:25.68#ibcon#about to read 4, iclass 22, count 2 2006.257.02:17:25.68#ibcon#read 4, iclass 22, count 2 2006.257.02:17:25.68#ibcon#about to read 5, iclass 22, count 2 2006.257.02:17:25.68#ibcon#read 5, iclass 22, count 2 2006.257.02:17:25.68#ibcon#about to read 6, iclass 22, count 2 2006.257.02:17:25.68#ibcon#read 6, iclass 22, count 2 2006.257.02:17:25.68#ibcon#end of sib2, iclass 22, count 2 2006.257.02:17:25.68#ibcon#*after write, iclass 22, count 2 2006.257.02:17:25.68#ibcon#*before return 0, iclass 22, count 2 2006.257.02:17:25.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:25.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:17:25.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.02:17:25.68#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:25.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:25.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:25.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:25.80#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:17:25.80#ibcon#first serial, iclass 22, count 0 2006.257.02:17:25.80#ibcon#enter sib2, iclass 22, count 0 2006.257.02:17:25.80#ibcon#flushed, iclass 22, count 0 2006.257.02:17:25.80#ibcon#about to write, iclass 22, count 0 2006.257.02:17:25.80#ibcon#wrote, iclass 22, count 0 2006.257.02:17:25.80#ibcon#about to read 3, iclass 22, count 0 2006.257.02:17:25.82#ibcon#read 3, iclass 22, count 0 2006.257.02:17:25.82#ibcon#about to read 4, iclass 22, count 0 2006.257.02:17:25.82#ibcon#read 4, iclass 22, count 0 2006.257.02:17:25.82#ibcon#about to read 5, iclass 22, count 0 2006.257.02:17:25.82#ibcon#read 5, iclass 22, count 0 2006.257.02:17:25.82#ibcon#about to read 6, iclass 22, count 0 2006.257.02:17:25.82#ibcon#read 6, iclass 22, count 0 2006.257.02:17:25.82#ibcon#end of sib2, iclass 22, count 0 2006.257.02:17:25.82#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:17:25.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:17:25.82#ibcon#[27=USB\r\n] 2006.257.02:17:25.82#ibcon#*before write, iclass 22, count 0 2006.257.02:17:25.82#ibcon#enter sib2, iclass 22, count 0 2006.257.02:17:25.82#ibcon#flushed, iclass 22, count 0 2006.257.02:17:25.82#ibcon#about to write, iclass 22, count 0 2006.257.02:17:25.82#ibcon#wrote, iclass 22, count 0 2006.257.02:17:25.82#ibcon#about to read 3, iclass 22, count 0 2006.257.02:17:25.85#ibcon#read 3, iclass 22, count 0 2006.257.02:17:25.85#ibcon#about to read 4, iclass 22, count 0 2006.257.02:17:25.85#ibcon#read 4, iclass 22, count 0 2006.257.02:17:25.85#ibcon#about to read 5, iclass 22, count 0 2006.257.02:17:25.85#ibcon#read 5, iclass 22, count 0 2006.257.02:17:25.85#ibcon#about to read 6, iclass 22, count 0 2006.257.02:17:25.85#ibcon#read 6, iclass 22, count 0 2006.257.02:17:25.85#ibcon#end of sib2, iclass 22, count 0 2006.257.02:17:25.85#ibcon#*after write, iclass 22, count 0 2006.257.02:17:25.85#ibcon#*before return 0, iclass 22, count 0 2006.257.02:17:25.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:25.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:17:25.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:17:25.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:17:25.85$vck44/vblo=8,744.99 2006.257.02:17:25.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.02:17:25.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.02:17:25.85#ibcon#ireg 17 cls_cnt 0 2006.257.02:17:25.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:25.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:25.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:25.85#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:17:25.85#ibcon#first serial, iclass 24, count 0 2006.257.02:17:25.85#ibcon#enter sib2, iclass 24, count 0 2006.257.02:17:25.85#ibcon#flushed, iclass 24, count 0 2006.257.02:17:25.85#ibcon#about to write, iclass 24, count 0 2006.257.02:17:25.85#ibcon#wrote, iclass 24, count 0 2006.257.02:17:25.85#ibcon#about to read 3, iclass 24, count 0 2006.257.02:17:25.87#ibcon#read 3, iclass 24, count 0 2006.257.02:17:25.87#ibcon#about to read 4, iclass 24, count 0 2006.257.02:17:25.87#ibcon#read 4, iclass 24, count 0 2006.257.02:17:25.87#ibcon#about to read 5, iclass 24, count 0 2006.257.02:17:25.87#ibcon#read 5, iclass 24, count 0 2006.257.02:17:25.87#ibcon#about to read 6, iclass 24, count 0 2006.257.02:17:25.87#ibcon#read 6, iclass 24, count 0 2006.257.02:17:25.87#ibcon#end of sib2, iclass 24, count 0 2006.257.02:17:25.87#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:17:25.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:17:25.87#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:17:25.87#ibcon#*before write, iclass 24, count 0 2006.257.02:17:25.87#ibcon#enter sib2, iclass 24, count 0 2006.257.02:17:25.87#ibcon#flushed, iclass 24, count 0 2006.257.02:17:25.87#ibcon#about to write, iclass 24, count 0 2006.257.02:17:25.87#ibcon#wrote, iclass 24, count 0 2006.257.02:17:25.87#ibcon#about to read 3, iclass 24, count 0 2006.257.02:17:25.92#ibcon#read 3, iclass 24, count 0 2006.257.02:17:25.92#ibcon#about to read 4, iclass 24, count 0 2006.257.02:17:25.92#ibcon#read 4, iclass 24, count 0 2006.257.02:17:25.92#ibcon#about to read 5, iclass 24, count 0 2006.257.02:17:25.92#ibcon#read 5, iclass 24, count 0 2006.257.02:17:25.92#ibcon#about to read 6, iclass 24, count 0 2006.257.02:17:25.92#ibcon#read 6, iclass 24, count 0 2006.257.02:17:25.92#ibcon#end of sib2, iclass 24, count 0 2006.257.02:17:25.92#ibcon#*after write, iclass 24, count 0 2006.257.02:17:25.92#ibcon#*before return 0, iclass 24, count 0 2006.257.02:17:25.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:25.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:17:25.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:17:25.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:17:25.92$vck44/vb=8,4 2006.257.02:17:25.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.02:17:25.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.02:17:25.92#ibcon#ireg 11 cls_cnt 2 2006.257.02:17:25.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:25.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:25.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:25.97#ibcon#enter wrdev, iclass 26, count 2 2006.257.02:17:25.97#ibcon#first serial, iclass 26, count 2 2006.257.02:17:25.97#ibcon#enter sib2, iclass 26, count 2 2006.257.02:17:25.97#ibcon#flushed, iclass 26, count 2 2006.257.02:17:25.97#ibcon#about to write, iclass 26, count 2 2006.257.02:17:25.97#ibcon#wrote, iclass 26, count 2 2006.257.02:17:25.97#ibcon#about to read 3, iclass 26, count 2 2006.257.02:17:25.99#ibcon#read 3, iclass 26, count 2 2006.257.02:17:25.99#ibcon#about to read 4, iclass 26, count 2 2006.257.02:17:25.99#ibcon#read 4, iclass 26, count 2 2006.257.02:17:25.99#ibcon#about to read 5, iclass 26, count 2 2006.257.02:17:25.99#ibcon#read 5, iclass 26, count 2 2006.257.02:17:25.99#ibcon#about to read 6, iclass 26, count 2 2006.257.02:17:25.99#ibcon#read 6, iclass 26, count 2 2006.257.02:17:25.99#ibcon#end of sib2, iclass 26, count 2 2006.257.02:17:25.99#ibcon#*mode == 0, iclass 26, count 2 2006.257.02:17:25.99#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.02:17:25.99#ibcon#[27=AT08-04\r\n] 2006.257.02:17:25.99#ibcon#*before write, iclass 26, count 2 2006.257.02:17:25.99#ibcon#enter sib2, iclass 26, count 2 2006.257.02:17:25.99#ibcon#flushed, iclass 26, count 2 2006.257.02:17:25.99#ibcon#about to write, iclass 26, count 2 2006.257.02:17:25.99#ibcon#wrote, iclass 26, count 2 2006.257.02:17:25.99#ibcon#about to read 3, iclass 26, count 2 2006.257.02:17:26.02#ibcon#read 3, iclass 26, count 2 2006.257.02:17:26.02#ibcon#about to read 4, iclass 26, count 2 2006.257.02:17:26.02#ibcon#read 4, iclass 26, count 2 2006.257.02:17:26.02#ibcon#about to read 5, iclass 26, count 2 2006.257.02:17:26.02#ibcon#read 5, iclass 26, count 2 2006.257.02:17:26.02#ibcon#about to read 6, iclass 26, count 2 2006.257.02:17:26.02#ibcon#read 6, iclass 26, count 2 2006.257.02:17:26.02#ibcon#end of sib2, iclass 26, count 2 2006.257.02:17:26.02#ibcon#*after write, iclass 26, count 2 2006.257.02:17:26.02#ibcon#*before return 0, iclass 26, count 2 2006.257.02:17:26.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:26.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:17:26.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.02:17:26.02#ibcon#ireg 7 cls_cnt 0 2006.257.02:17:26.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:26.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:26.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:26.14#ibcon#enter wrdev, iclass 26, count 0 2006.257.02:17:26.14#ibcon#first serial, iclass 26, count 0 2006.257.02:17:26.14#ibcon#enter sib2, iclass 26, count 0 2006.257.02:17:26.14#ibcon#flushed, iclass 26, count 0 2006.257.02:17:26.14#ibcon#about to write, iclass 26, count 0 2006.257.02:17:26.14#ibcon#wrote, iclass 26, count 0 2006.257.02:17:26.14#ibcon#about to read 3, iclass 26, count 0 2006.257.02:17:26.16#ibcon#read 3, iclass 26, count 0 2006.257.02:17:26.16#ibcon#about to read 4, iclass 26, count 0 2006.257.02:17:26.16#ibcon#read 4, iclass 26, count 0 2006.257.02:17:26.16#ibcon#about to read 5, iclass 26, count 0 2006.257.02:17:26.16#ibcon#read 5, iclass 26, count 0 2006.257.02:17:26.16#ibcon#about to read 6, iclass 26, count 0 2006.257.02:17:26.16#ibcon#read 6, iclass 26, count 0 2006.257.02:17:26.16#ibcon#end of sib2, iclass 26, count 0 2006.257.02:17:26.16#ibcon#*mode == 0, iclass 26, count 0 2006.257.02:17:26.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.02:17:26.16#ibcon#[27=USB\r\n] 2006.257.02:17:26.16#ibcon#*before write, iclass 26, count 0 2006.257.02:17:26.16#ibcon#enter sib2, iclass 26, count 0 2006.257.02:17:26.16#ibcon#flushed, iclass 26, count 0 2006.257.02:17:26.16#ibcon#about to write, iclass 26, count 0 2006.257.02:17:26.16#ibcon#wrote, iclass 26, count 0 2006.257.02:17:26.16#ibcon#about to read 3, iclass 26, count 0 2006.257.02:17:26.19#ibcon#read 3, iclass 26, count 0 2006.257.02:17:26.19#ibcon#about to read 4, iclass 26, count 0 2006.257.02:17:26.19#ibcon#read 4, iclass 26, count 0 2006.257.02:17:26.19#ibcon#about to read 5, iclass 26, count 0 2006.257.02:17:26.19#ibcon#read 5, iclass 26, count 0 2006.257.02:17:26.19#ibcon#about to read 6, iclass 26, count 0 2006.257.02:17:26.19#ibcon#read 6, iclass 26, count 0 2006.257.02:17:26.19#ibcon#end of sib2, iclass 26, count 0 2006.257.02:17:26.19#ibcon#*after write, iclass 26, count 0 2006.257.02:17:26.19#ibcon#*before return 0, iclass 26, count 0 2006.257.02:17:26.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:26.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:17:26.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.02:17:26.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.02:17:26.19$vck44/vabw=wide 2006.257.02:17:26.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.02:17:26.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.02:17:26.19#ibcon#ireg 8 cls_cnt 0 2006.257.02:17:26.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:17:26.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:17:26.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:17:26.19#ibcon#enter wrdev, iclass 28, count 0 2006.257.02:17:26.19#ibcon#first serial, iclass 28, count 0 2006.257.02:17:26.19#ibcon#enter sib2, iclass 28, count 0 2006.257.02:17:26.19#ibcon#flushed, iclass 28, count 0 2006.257.02:17:26.19#ibcon#about to write, iclass 28, count 0 2006.257.02:17:26.19#ibcon#wrote, iclass 28, count 0 2006.257.02:17:26.19#ibcon#about to read 3, iclass 28, count 0 2006.257.02:17:26.21#ibcon#read 3, iclass 28, count 0 2006.257.02:17:26.21#ibcon#about to read 4, iclass 28, count 0 2006.257.02:17:26.21#ibcon#read 4, iclass 28, count 0 2006.257.02:17:26.21#ibcon#about to read 5, iclass 28, count 0 2006.257.02:17:26.21#ibcon#read 5, iclass 28, count 0 2006.257.02:17:26.21#ibcon#about to read 6, iclass 28, count 0 2006.257.02:17:26.21#ibcon#read 6, iclass 28, count 0 2006.257.02:17:26.21#ibcon#end of sib2, iclass 28, count 0 2006.257.02:17:26.21#ibcon#*mode == 0, iclass 28, count 0 2006.257.02:17:26.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.02:17:26.21#ibcon#[25=BW32\r\n] 2006.257.02:17:26.21#ibcon#*before write, iclass 28, count 0 2006.257.02:17:26.21#ibcon#enter sib2, iclass 28, count 0 2006.257.02:17:26.21#ibcon#flushed, iclass 28, count 0 2006.257.02:17:26.21#ibcon#about to write, iclass 28, count 0 2006.257.02:17:26.21#ibcon#wrote, iclass 28, count 0 2006.257.02:17:26.21#ibcon#about to read 3, iclass 28, count 0 2006.257.02:17:26.24#ibcon#read 3, iclass 28, count 0 2006.257.02:17:26.24#ibcon#about to read 4, iclass 28, count 0 2006.257.02:17:26.24#ibcon#read 4, iclass 28, count 0 2006.257.02:17:26.24#ibcon#about to read 5, iclass 28, count 0 2006.257.02:17:26.24#ibcon#read 5, iclass 28, count 0 2006.257.02:17:26.24#ibcon#about to read 6, iclass 28, count 0 2006.257.02:17:26.24#ibcon#read 6, iclass 28, count 0 2006.257.02:17:26.24#ibcon#end of sib2, iclass 28, count 0 2006.257.02:17:26.24#ibcon#*after write, iclass 28, count 0 2006.257.02:17:26.24#ibcon#*before return 0, iclass 28, count 0 2006.257.02:17:26.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:17:26.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:17:26.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.02:17:26.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.02:17:26.24$vck44/vbbw=wide 2006.257.02:17:26.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.02:17:26.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.02:17:26.24#ibcon#ireg 8 cls_cnt 0 2006.257.02:17:26.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:17:26.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:17:26.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:17:26.31#ibcon#enter wrdev, iclass 30, count 0 2006.257.02:17:26.31#ibcon#first serial, iclass 30, count 0 2006.257.02:17:26.31#ibcon#enter sib2, iclass 30, count 0 2006.257.02:17:26.31#ibcon#flushed, iclass 30, count 0 2006.257.02:17:26.31#ibcon#about to write, iclass 30, count 0 2006.257.02:17:26.31#ibcon#wrote, iclass 30, count 0 2006.257.02:17:26.31#ibcon#about to read 3, iclass 30, count 0 2006.257.02:17:26.33#ibcon#read 3, iclass 30, count 0 2006.257.02:17:26.33#ibcon#about to read 4, iclass 30, count 0 2006.257.02:17:26.33#ibcon#read 4, iclass 30, count 0 2006.257.02:17:26.33#ibcon#about to read 5, iclass 30, count 0 2006.257.02:17:26.33#ibcon#read 5, iclass 30, count 0 2006.257.02:17:26.33#ibcon#about to read 6, iclass 30, count 0 2006.257.02:17:26.33#ibcon#read 6, iclass 30, count 0 2006.257.02:17:26.33#ibcon#end of sib2, iclass 30, count 0 2006.257.02:17:26.33#ibcon#*mode == 0, iclass 30, count 0 2006.257.02:17:26.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.02:17:26.33#ibcon#[27=BW32\r\n] 2006.257.02:17:26.33#ibcon#*before write, iclass 30, count 0 2006.257.02:17:26.33#ibcon#enter sib2, iclass 30, count 0 2006.257.02:17:26.33#ibcon#flushed, iclass 30, count 0 2006.257.02:17:26.33#ibcon#about to write, iclass 30, count 0 2006.257.02:17:26.33#ibcon#wrote, iclass 30, count 0 2006.257.02:17:26.33#ibcon#about to read 3, iclass 30, count 0 2006.257.02:17:26.36#ibcon#read 3, iclass 30, count 0 2006.257.02:17:26.36#ibcon#about to read 4, iclass 30, count 0 2006.257.02:17:26.36#ibcon#read 4, iclass 30, count 0 2006.257.02:17:26.36#ibcon#about to read 5, iclass 30, count 0 2006.257.02:17:26.36#ibcon#read 5, iclass 30, count 0 2006.257.02:17:26.36#ibcon#about to read 6, iclass 30, count 0 2006.257.02:17:26.36#ibcon#read 6, iclass 30, count 0 2006.257.02:17:26.36#ibcon#end of sib2, iclass 30, count 0 2006.257.02:17:26.36#ibcon#*after write, iclass 30, count 0 2006.257.02:17:26.36#ibcon#*before return 0, iclass 30, count 0 2006.257.02:17:26.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:17:26.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:17:26.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.02:17:26.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.02:17:26.36$setupk4/ifdk4 2006.257.02:17:26.36$ifdk4/lo= 2006.257.02:17:26.36$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:17:26.36$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:17:26.36$ifdk4/patch= 2006.257.02:17:26.36$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:17:26.36$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:17:26.36$setupk4/!*+20s 2006.257.02:17:33.70#abcon#<5=/02 2.6 6.4 17.79 981012.1\r\n> 2006.257.02:17:33.72#abcon#{5=INTERFACE CLEAR} 2006.257.02:17:33.78#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:17:40.85$setupk4/"tpicd 2006.257.02:17:40.85$setupk4/echo=off 2006.257.02:17:40.85$setupk4/xlog=off 2006.257.02:17:40.85:!2006.257.02:19:31 2006.257.02:19:06.13#trakl#Source acquired 2006.257.02:19:06.13#flagr#flagr/antenna,acquired 2006.257.02:19:31.00:preob 2006.257.02:19:31.13/onsource/TRACKING 2006.257.02:19:31.13:!2006.257.02:19:41 2006.257.02:19:41.00:"tape 2006.257.02:19:41.00:"st=record 2006.257.02:19:41.00:data_valid=on 2006.257.02:19:41.00:midob 2006.257.02:19:42.13/onsource/TRACKING 2006.257.02:19:42.13/wx/17.79,1012.1,99 2006.257.02:19:42.31/cable/+6.4871E-03 2006.257.02:19:43.40/va/01,08,usb,yes,32,35 2006.257.02:19:43.40/va/02,07,usb,yes,35,35 2006.257.02:19:43.40/va/03,08,usb,yes,31,33 2006.257.02:19:43.40/va/04,07,usb,yes,36,37 2006.257.02:19:43.40/va/05,04,usb,yes,32,33 2006.257.02:19:43.40/va/06,04,usb,yes,36,35 2006.257.02:19:43.40/va/07,04,usb,yes,37,37 2006.257.02:19:43.40/va/08,04,usb,yes,30,37 2006.257.02:19:43.63/valo/01,524.99,yes,locked 2006.257.02:19:43.63/valo/02,534.99,yes,locked 2006.257.02:19:43.63/valo/03,564.99,yes,locked 2006.257.02:19:43.63/valo/04,624.99,yes,locked 2006.257.02:19:43.63/valo/05,734.99,yes,locked 2006.257.02:19:43.63/valo/06,814.99,yes,locked 2006.257.02:19:43.63/valo/07,864.99,yes,locked 2006.257.02:19:43.63/valo/08,884.99,yes,locked 2006.257.02:19:44.72/vb/01,04,usb,yes,31,29 2006.257.02:19:44.72/vb/02,05,usb,yes,29,29 2006.257.02:19:44.72/vb/03,04,usb,yes,30,33 2006.257.02:19:44.72/vb/04,05,usb,yes,30,29 2006.257.02:19:44.72/vb/05,04,usb,yes,27,29 2006.257.02:19:44.72/vb/06,04,usb,yes,31,27 2006.257.02:19:44.72/vb/07,04,usb,yes,31,31 2006.257.02:19:44.72/vb/08,04,usb,yes,28,32 2006.257.02:19:44.96/vblo/01,629.99,yes,locked 2006.257.02:19:44.96/vblo/02,634.99,yes,locked 2006.257.02:19:44.96/vblo/03,649.99,yes,locked 2006.257.02:19:44.96/vblo/04,679.99,yes,locked 2006.257.02:19:44.96/vblo/05,709.99,yes,locked 2006.257.02:19:44.96/vblo/06,719.99,yes,locked 2006.257.02:19:44.96/vblo/07,734.99,yes,locked 2006.257.02:19:44.96/vblo/08,744.99,yes,locked 2006.257.02:19:45.11/vabw/8 2006.257.02:19:45.26/vbbw/8 2006.257.02:19:45.39/xfe/off,on,15.0 2006.257.02:19:45.76/ifatt/23,28,28,28 2006.257.02:19:46.08/fmout-gps/S +4.58E-07 2006.257.02:19:46.12:!2006.257.02:23:51 2006.257.02:23:51.00:data_valid=off 2006.257.02:23:51.00:"et 2006.257.02:23:51.00:!+3s 2006.257.02:23:54.01:"tape 2006.257.02:23:54.01:postob 2006.257.02:23:54.12/cable/+6.4844E-03 2006.257.02:23:54.12/wx/17.87,1011.9,98 2006.257.02:23:55.08/fmout-gps/S +4.58E-07 2006.257.02:23:55.08:scan_name=257-0233,jd0609,40 2006.257.02:23:55.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.257.02:23:56.14:checkk5 2006.257.02:23:56.14#flagr#flagr/antenna,new-source 2006.257.02:23:56.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:23:56.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:23:57.97/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:23:58.40/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:23:58.93/chk_obsdata//k5ts1/T2570219??a.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.257.02:23:59.35/chk_obsdata//k5ts2/T2570219??b.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.257.02:23:59.75/chk_obsdata//k5ts3/T2570219??c.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.257.02:24:00.13/chk_obsdata//k5ts4/T2570219??d.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.257.02:24:00.98/k5log//k5ts1_log_newline 2006.257.02:24:01.77/k5log//k5ts2_log_newline 2006.257.02:24:02.67/k5log//k5ts3_log_newline 2006.257.02:24:03.46/k5log//k5ts4_log_newline 2006.257.02:24:03.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:24:03.48:setupk4=1 2006.257.02:24:03.48$setupk4/echo=on 2006.257.02:24:03.49$setupk4/pcalon 2006.257.02:24:03.49$pcalon/"no phase cal control is implemented here 2006.257.02:24:03.49$setupk4/"tpicd=stop 2006.257.02:24:03.49$setupk4/"rec=synch_on 2006.257.02:24:03.49$setupk4/"rec_mode=128 2006.257.02:24:03.49$setupk4/!* 2006.257.02:24:03.49$setupk4/recpk4 2006.257.02:24:03.49$recpk4/recpatch= 2006.257.02:24:03.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:24:03.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:24:03.49$setupk4/vck44 2006.257.02:24:03.49$vck44/valo=1,524.99 2006.257.02:24:03.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.02:24:03.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.02:24:03.49#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:03.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:03.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:03.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:03.49#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:24:03.49#ibcon#first serial, iclass 11, count 0 2006.257.02:24:03.49#ibcon#enter sib2, iclass 11, count 0 2006.257.02:24:03.49#ibcon#flushed, iclass 11, count 0 2006.257.02:24:03.49#ibcon#about to write, iclass 11, count 0 2006.257.02:24:03.49#ibcon#wrote, iclass 11, count 0 2006.257.02:24:03.49#ibcon#about to read 3, iclass 11, count 0 2006.257.02:24:03.52#ibcon#read 3, iclass 11, count 0 2006.257.02:24:03.52#ibcon#about to read 4, iclass 11, count 0 2006.257.02:24:03.52#ibcon#read 4, iclass 11, count 0 2006.257.02:24:03.52#ibcon#about to read 5, iclass 11, count 0 2006.257.02:24:03.52#ibcon#read 5, iclass 11, count 0 2006.257.02:24:03.52#ibcon#about to read 6, iclass 11, count 0 2006.257.02:24:03.52#ibcon#read 6, iclass 11, count 0 2006.257.02:24:03.52#ibcon#end of sib2, iclass 11, count 0 2006.257.02:24:03.52#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:24:03.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:24:03.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:24:03.52#ibcon#*before write, iclass 11, count 0 2006.257.02:24:03.52#ibcon#enter sib2, iclass 11, count 0 2006.257.02:24:03.52#ibcon#flushed, iclass 11, count 0 2006.257.02:24:03.52#ibcon#about to write, iclass 11, count 0 2006.257.02:24:03.52#ibcon#wrote, iclass 11, count 0 2006.257.02:24:03.52#ibcon#about to read 3, iclass 11, count 0 2006.257.02:24:03.57#ibcon#read 3, iclass 11, count 0 2006.257.02:24:03.57#ibcon#about to read 4, iclass 11, count 0 2006.257.02:24:03.57#ibcon#read 4, iclass 11, count 0 2006.257.02:24:03.57#ibcon#about to read 5, iclass 11, count 0 2006.257.02:24:03.57#ibcon#read 5, iclass 11, count 0 2006.257.02:24:03.57#ibcon#about to read 6, iclass 11, count 0 2006.257.02:24:03.57#ibcon#read 6, iclass 11, count 0 2006.257.02:24:03.57#ibcon#end of sib2, iclass 11, count 0 2006.257.02:24:03.57#ibcon#*after write, iclass 11, count 0 2006.257.02:24:03.57#ibcon#*before return 0, iclass 11, count 0 2006.257.02:24:03.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:03.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:03.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:24:03.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:24:03.57$vck44/va=1,8 2006.257.02:24:03.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.02:24:03.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.02:24:03.57#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:03.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:03.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:03.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:03.57#ibcon#enter wrdev, iclass 13, count 2 2006.257.02:24:03.57#ibcon#first serial, iclass 13, count 2 2006.257.02:24:03.57#ibcon#enter sib2, iclass 13, count 2 2006.257.02:24:03.57#ibcon#flushed, iclass 13, count 2 2006.257.02:24:03.57#ibcon#about to write, iclass 13, count 2 2006.257.02:24:03.57#ibcon#wrote, iclass 13, count 2 2006.257.02:24:03.57#ibcon#about to read 3, iclass 13, count 2 2006.257.02:24:03.59#ibcon#read 3, iclass 13, count 2 2006.257.02:24:03.59#ibcon#about to read 4, iclass 13, count 2 2006.257.02:24:03.59#ibcon#read 4, iclass 13, count 2 2006.257.02:24:03.59#ibcon#about to read 5, iclass 13, count 2 2006.257.02:24:03.59#ibcon#read 5, iclass 13, count 2 2006.257.02:24:03.59#ibcon#about to read 6, iclass 13, count 2 2006.257.02:24:03.59#ibcon#read 6, iclass 13, count 2 2006.257.02:24:03.59#ibcon#end of sib2, iclass 13, count 2 2006.257.02:24:03.59#ibcon#*mode == 0, iclass 13, count 2 2006.257.02:24:03.59#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.02:24:03.59#ibcon#[25=AT01-08\r\n] 2006.257.02:24:03.59#ibcon#*before write, iclass 13, count 2 2006.257.02:24:03.59#ibcon#enter sib2, iclass 13, count 2 2006.257.02:24:03.59#ibcon#flushed, iclass 13, count 2 2006.257.02:24:03.59#ibcon#about to write, iclass 13, count 2 2006.257.02:24:03.59#ibcon#wrote, iclass 13, count 2 2006.257.02:24:03.59#ibcon#about to read 3, iclass 13, count 2 2006.257.02:24:03.62#ibcon#read 3, iclass 13, count 2 2006.257.02:24:03.62#ibcon#about to read 4, iclass 13, count 2 2006.257.02:24:03.62#ibcon#read 4, iclass 13, count 2 2006.257.02:24:03.62#ibcon#about to read 5, iclass 13, count 2 2006.257.02:24:03.62#ibcon#read 5, iclass 13, count 2 2006.257.02:24:03.62#ibcon#about to read 6, iclass 13, count 2 2006.257.02:24:03.62#ibcon#read 6, iclass 13, count 2 2006.257.02:24:03.62#ibcon#end of sib2, iclass 13, count 2 2006.257.02:24:03.62#ibcon#*after write, iclass 13, count 2 2006.257.02:24:03.62#ibcon#*before return 0, iclass 13, count 2 2006.257.02:24:03.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:03.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:03.62#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.02:24:03.62#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:03.62#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:03.74#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:03.74#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:03.74#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:24:03.74#ibcon#first serial, iclass 13, count 0 2006.257.02:24:03.74#ibcon#enter sib2, iclass 13, count 0 2006.257.02:24:03.74#ibcon#flushed, iclass 13, count 0 2006.257.02:24:03.74#ibcon#about to write, iclass 13, count 0 2006.257.02:24:03.74#ibcon#wrote, iclass 13, count 0 2006.257.02:24:03.74#ibcon#about to read 3, iclass 13, count 0 2006.257.02:24:03.76#ibcon#read 3, iclass 13, count 0 2006.257.02:24:03.76#ibcon#about to read 4, iclass 13, count 0 2006.257.02:24:03.76#ibcon#read 4, iclass 13, count 0 2006.257.02:24:03.76#ibcon#about to read 5, iclass 13, count 0 2006.257.02:24:03.76#ibcon#read 5, iclass 13, count 0 2006.257.02:24:03.76#ibcon#about to read 6, iclass 13, count 0 2006.257.02:24:03.76#ibcon#read 6, iclass 13, count 0 2006.257.02:24:03.76#ibcon#end of sib2, iclass 13, count 0 2006.257.02:24:03.76#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:24:03.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:24:03.76#ibcon#[25=USB\r\n] 2006.257.02:24:03.76#ibcon#*before write, iclass 13, count 0 2006.257.02:24:03.76#ibcon#enter sib2, iclass 13, count 0 2006.257.02:24:03.76#ibcon#flushed, iclass 13, count 0 2006.257.02:24:03.76#ibcon#about to write, iclass 13, count 0 2006.257.02:24:03.76#ibcon#wrote, iclass 13, count 0 2006.257.02:24:03.76#ibcon#about to read 3, iclass 13, count 0 2006.257.02:24:03.79#ibcon#read 3, iclass 13, count 0 2006.257.02:24:03.79#ibcon#about to read 4, iclass 13, count 0 2006.257.02:24:03.79#ibcon#read 4, iclass 13, count 0 2006.257.02:24:03.79#ibcon#about to read 5, iclass 13, count 0 2006.257.02:24:03.79#ibcon#read 5, iclass 13, count 0 2006.257.02:24:03.79#ibcon#about to read 6, iclass 13, count 0 2006.257.02:24:03.79#ibcon#read 6, iclass 13, count 0 2006.257.02:24:03.79#ibcon#end of sib2, iclass 13, count 0 2006.257.02:24:03.79#ibcon#*after write, iclass 13, count 0 2006.257.02:24:03.79#ibcon#*before return 0, iclass 13, count 0 2006.257.02:24:03.79#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:03.79#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:03.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:24:03.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:24:03.79$vck44/valo=2,534.99 2006.257.02:24:03.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.02:24:03.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.02:24:03.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:03.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:03.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:03.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:03.79#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:24:03.79#ibcon#first serial, iclass 15, count 0 2006.257.02:24:03.79#ibcon#enter sib2, iclass 15, count 0 2006.257.02:24:03.79#ibcon#flushed, iclass 15, count 0 2006.257.02:24:03.79#ibcon#about to write, iclass 15, count 0 2006.257.02:24:03.79#ibcon#wrote, iclass 15, count 0 2006.257.02:24:03.79#ibcon#about to read 3, iclass 15, count 0 2006.257.02:24:03.81#ibcon#read 3, iclass 15, count 0 2006.257.02:24:03.81#ibcon#about to read 4, iclass 15, count 0 2006.257.02:24:03.81#ibcon#read 4, iclass 15, count 0 2006.257.02:24:03.81#ibcon#about to read 5, iclass 15, count 0 2006.257.02:24:03.81#ibcon#read 5, iclass 15, count 0 2006.257.02:24:03.81#ibcon#about to read 6, iclass 15, count 0 2006.257.02:24:03.81#ibcon#read 6, iclass 15, count 0 2006.257.02:24:03.81#ibcon#end of sib2, iclass 15, count 0 2006.257.02:24:03.81#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:24:03.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:24:03.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:24:03.81#ibcon#*before write, iclass 15, count 0 2006.257.02:24:03.81#ibcon#enter sib2, iclass 15, count 0 2006.257.02:24:03.81#ibcon#flushed, iclass 15, count 0 2006.257.02:24:03.81#ibcon#about to write, iclass 15, count 0 2006.257.02:24:03.81#ibcon#wrote, iclass 15, count 0 2006.257.02:24:03.81#ibcon#about to read 3, iclass 15, count 0 2006.257.02:24:03.86#ibcon#read 3, iclass 15, count 0 2006.257.02:24:03.86#ibcon#about to read 4, iclass 15, count 0 2006.257.02:24:03.86#ibcon#read 4, iclass 15, count 0 2006.257.02:24:03.86#ibcon#about to read 5, iclass 15, count 0 2006.257.02:24:03.86#ibcon#read 5, iclass 15, count 0 2006.257.02:24:03.86#ibcon#about to read 6, iclass 15, count 0 2006.257.02:24:03.86#ibcon#read 6, iclass 15, count 0 2006.257.02:24:03.86#ibcon#end of sib2, iclass 15, count 0 2006.257.02:24:03.86#ibcon#*after write, iclass 15, count 0 2006.257.02:24:03.86#ibcon#*before return 0, iclass 15, count 0 2006.257.02:24:03.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:03.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:03.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:24:03.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:24:03.86$vck44/va=2,7 2006.257.02:24:03.86#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.02:24:03.86#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.02:24:03.86#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:03.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:03.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:03.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:03.91#ibcon#enter wrdev, iclass 17, count 2 2006.257.02:24:03.91#ibcon#first serial, iclass 17, count 2 2006.257.02:24:03.91#ibcon#enter sib2, iclass 17, count 2 2006.257.02:24:03.91#ibcon#flushed, iclass 17, count 2 2006.257.02:24:03.91#ibcon#about to write, iclass 17, count 2 2006.257.02:24:03.91#ibcon#wrote, iclass 17, count 2 2006.257.02:24:03.91#ibcon#about to read 3, iclass 17, count 2 2006.257.02:24:03.93#ibcon#read 3, iclass 17, count 2 2006.257.02:24:03.93#ibcon#about to read 4, iclass 17, count 2 2006.257.02:24:03.93#ibcon#read 4, iclass 17, count 2 2006.257.02:24:03.93#ibcon#about to read 5, iclass 17, count 2 2006.257.02:24:03.93#ibcon#read 5, iclass 17, count 2 2006.257.02:24:03.93#ibcon#about to read 6, iclass 17, count 2 2006.257.02:24:03.93#ibcon#read 6, iclass 17, count 2 2006.257.02:24:03.93#ibcon#end of sib2, iclass 17, count 2 2006.257.02:24:03.93#ibcon#*mode == 0, iclass 17, count 2 2006.257.02:24:03.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.02:24:03.93#ibcon#[25=AT02-07\r\n] 2006.257.02:24:03.93#ibcon#*before write, iclass 17, count 2 2006.257.02:24:03.93#ibcon#enter sib2, iclass 17, count 2 2006.257.02:24:03.93#ibcon#flushed, iclass 17, count 2 2006.257.02:24:03.93#ibcon#about to write, iclass 17, count 2 2006.257.02:24:03.93#ibcon#wrote, iclass 17, count 2 2006.257.02:24:03.93#ibcon#about to read 3, iclass 17, count 2 2006.257.02:24:03.96#ibcon#read 3, iclass 17, count 2 2006.257.02:24:03.96#ibcon#about to read 4, iclass 17, count 2 2006.257.02:24:03.96#ibcon#read 4, iclass 17, count 2 2006.257.02:24:03.96#ibcon#about to read 5, iclass 17, count 2 2006.257.02:24:03.96#ibcon#read 5, iclass 17, count 2 2006.257.02:24:03.96#ibcon#about to read 6, iclass 17, count 2 2006.257.02:24:03.96#ibcon#read 6, iclass 17, count 2 2006.257.02:24:03.96#ibcon#end of sib2, iclass 17, count 2 2006.257.02:24:03.96#ibcon#*after write, iclass 17, count 2 2006.257.02:24:03.96#ibcon#*before return 0, iclass 17, count 2 2006.257.02:24:03.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:03.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:03.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.02:24:03.96#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:03.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:04.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:04.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:04.08#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:24:04.08#ibcon#first serial, iclass 17, count 0 2006.257.02:24:04.08#ibcon#enter sib2, iclass 17, count 0 2006.257.02:24:04.08#ibcon#flushed, iclass 17, count 0 2006.257.02:24:04.08#ibcon#about to write, iclass 17, count 0 2006.257.02:24:04.08#ibcon#wrote, iclass 17, count 0 2006.257.02:24:04.08#ibcon#about to read 3, iclass 17, count 0 2006.257.02:24:04.10#ibcon#read 3, iclass 17, count 0 2006.257.02:24:04.10#ibcon#about to read 4, iclass 17, count 0 2006.257.02:24:04.10#ibcon#read 4, iclass 17, count 0 2006.257.02:24:04.10#ibcon#about to read 5, iclass 17, count 0 2006.257.02:24:04.10#ibcon#read 5, iclass 17, count 0 2006.257.02:24:04.10#ibcon#about to read 6, iclass 17, count 0 2006.257.02:24:04.10#ibcon#read 6, iclass 17, count 0 2006.257.02:24:04.10#ibcon#end of sib2, iclass 17, count 0 2006.257.02:24:04.10#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:24:04.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:24:04.10#ibcon#[25=USB\r\n] 2006.257.02:24:04.10#ibcon#*before write, iclass 17, count 0 2006.257.02:24:04.10#ibcon#enter sib2, iclass 17, count 0 2006.257.02:24:04.10#ibcon#flushed, iclass 17, count 0 2006.257.02:24:04.10#ibcon#about to write, iclass 17, count 0 2006.257.02:24:04.10#ibcon#wrote, iclass 17, count 0 2006.257.02:24:04.10#ibcon#about to read 3, iclass 17, count 0 2006.257.02:24:04.13#ibcon#read 3, iclass 17, count 0 2006.257.02:24:04.13#ibcon#about to read 4, iclass 17, count 0 2006.257.02:24:04.13#ibcon#read 4, iclass 17, count 0 2006.257.02:24:04.13#ibcon#about to read 5, iclass 17, count 0 2006.257.02:24:04.13#ibcon#read 5, iclass 17, count 0 2006.257.02:24:04.13#ibcon#about to read 6, iclass 17, count 0 2006.257.02:24:04.13#ibcon#read 6, iclass 17, count 0 2006.257.02:24:04.13#ibcon#end of sib2, iclass 17, count 0 2006.257.02:24:04.13#ibcon#*after write, iclass 17, count 0 2006.257.02:24:04.13#ibcon#*before return 0, iclass 17, count 0 2006.257.02:24:04.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:04.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:04.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:24:04.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:24:04.13$vck44/valo=3,564.99 2006.257.02:24:04.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.02:24:04.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.02:24:04.13#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:04.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:04.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:04.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:04.13#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:24:04.13#ibcon#first serial, iclass 19, count 0 2006.257.02:24:04.13#ibcon#enter sib2, iclass 19, count 0 2006.257.02:24:04.13#ibcon#flushed, iclass 19, count 0 2006.257.02:24:04.13#ibcon#about to write, iclass 19, count 0 2006.257.02:24:04.13#ibcon#wrote, iclass 19, count 0 2006.257.02:24:04.13#ibcon#about to read 3, iclass 19, count 0 2006.257.02:24:04.15#ibcon#read 3, iclass 19, count 0 2006.257.02:24:04.15#ibcon#about to read 4, iclass 19, count 0 2006.257.02:24:04.15#ibcon#read 4, iclass 19, count 0 2006.257.02:24:04.15#ibcon#about to read 5, iclass 19, count 0 2006.257.02:24:04.15#ibcon#read 5, iclass 19, count 0 2006.257.02:24:04.15#ibcon#about to read 6, iclass 19, count 0 2006.257.02:24:04.15#ibcon#read 6, iclass 19, count 0 2006.257.02:24:04.15#ibcon#end of sib2, iclass 19, count 0 2006.257.02:24:04.15#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:24:04.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:24:04.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:24:04.15#ibcon#*before write, iclass 19, count 0 2006.257.02:24:04.15#ibcon#enter sib2, iclass 19, count 0 2006.257.02:24:04.15#ibcon#flushed, iclass 19, count 0 2006.257.02:24:04.15#ibcon#about to write, iclass 19, count 0 2006.257.02:24:04.15#ibcon#wrote, iclass 19, count 0 2006.257.02:24:04.15#ibcon#about to read 3, iclass 19, count 0 2006.257.02:24:04.20#ibcon#read 3, iclass 19, count 0 2006.257.02:24:04.20#ibcon#about to read 4, iclass 19, count 0 2006.257.02:24:04.20#ibcon#read 4, iclass 19, count 0 2006.257.02:24:04.20#ibcon#about to read 5, iclass 19, count 0 2006.257.02:24:04.20#ibcon#read 5, iclass 19, count 0 2006.257.02:24:04.20#ibcon#about to read 6, iclass 19, count 0 2006.257.02:24:04.20#ibcon#read 6, iclass 19, count 0 2006.257.02:24:04.20#ibcon#end of sib2, iclass 19, count 0 2006.257.02:24:04.20#ibcon#*after write, iclass 19, count 0 2006.257.02:24:04.20#ibcon#*before return 0, iclass 19, count 0 2006.257.02:24:04.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:04.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:04.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:24:04.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:24:04.20$vck44/va=3,8 2006.257.02:24:04.20#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.02:24:04.20#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.02:24:04.20#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:04.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:04.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:04.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:04.25#ibcon#enter wrdev, iclass 21, count 2 2006.257.02:24:04.25#ibcon#first serial, iclass 21, count 2 2006.257.02:24:04.25#ibcon#enter sib2, iclass 21, count 2 2006.257.02:24:04.25#ibcon#flushed, iclass 21, count 2 2006.257.02:24:04.25#ibcon#about to write, iclass 21, count 2 2006.257.02:24:04.25#ibcon#wrote, iclass 21, count 2 2006.257.02:24:04.25#ibcon#about to read 3, iclass 21, count 2 2006.257.02:24:04.27#ibcon#read 3, iclass 21, count 2 2006.257.02:24:04.27#ibcon#about to read 4, iclass 21, count 2 2006.257.02:24:04.27#ibcon#read 4, iclass 21, count 2 2006.257.02:24:04.27#ibcon#about to read 5, iclass 21, count 2 2006.257.02:24:04.27#ibcon#read 5, iclass 21, count 2 2006.257.02:24:04.27#ibcon#about to read 6, iclass 21, count 2 2006.257.02:24:04.27#ibcon#read 6, iclass 21, count 2 2006.257.02:24:04.27#ibcon#end of sib2, iclass 21, count 2 2006.257.02:24:04.27#ibcon#*mode == 0, iclass 21, count 2 2006.257.02:24:04.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.02:24:04.27#ibcon#[25=AT03-08\r\n] 2006.257.02:24:04.27#ibcon#*before write, iclass 21, count 2 2006.257.02:24:04.27#ibcon#enter sib2, iclass 21, count 2 2006.257.02:24:04.27#ibcon#flushed, iclass 21, count 2 2006.257.02:24:04.27#ibcon#about to write, iclass 21, count 2 2006.257.02:24:04.27#ibcon#wrote, iclass 21, count 2 2006.257.02:24:04.27#ibcon#about to read 3, iclass 21, count 2 2006.257.02:24:04.30#ibcon#read 3, iclass 21, count 2 2006.257.02:24:04.30#ibcon#about to read 4, iclass 21, count 2 2006.257.02:24:04.30#ibcon#read 4, iclass 21, count 2 2006.257.02:24:04.30#ibcon#about to read 5, iclass 21, count 2 2006.257.02:24:04.30#ibcon#read 5, iclass 21, count 2 2006.257.02:24:04.30#ibcon#about to read 6, iclass 21, count 2 2006.257.02:24:04.30#ibcon#read 6, iclass 21, count 2 2006.257.02:24:04.30#ibcon#end of sib2, iclass 21, count 2 2006.257.02:24:04.30#ibcon#*after write, iclass 21, count 2 2006.257.02:24:04.30#ibcon#*before return 0, iclass 21, count 2 2006.257.02:24:04.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:04.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:04.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.02:24:04.30#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:04.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:04.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:04.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:04.42#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:24:04.42#ibcon#first serial, iclass 21, count 0 2006.257.02:24:04.42#ibcon#enter sib2, iclass 21, count 0 2006.257.02:24:04.42#ibcon#flushed, iclass 21, count 0 2006.257.02:24:04.42#ibcon#about to write, iclass 21, count 0 2006.257.02:24:04.42#ibcon#wrote, iclass 21, count 0 2006.257.02:24:04.42#ibcon#about to read 3, iclass 21, count 0 2006.257.02:24:04.44#ibcon#read 3, iclass 21, count 0 2006.257.02:24:04.44#ibcon#about to read 4, iclass 21, count 0 2006.257.02:24:04.44#ibcon#read 4, iclass 21, count 0 2006.257.02:24:04.44#ibcon#about to read 5, iclass 21, count 0 2006.257.02:24:04.44#ibcon#read 5, iclass 21, count 0 2006.257.02:24:04.44#ibcon#about to read 6, iclass 21, count 0 2006.257.02:24:04.44#ibcon#read 6, iclass 21, count 0 2006.257.02:24:04.44#ibcon#end of sib2, iclass 21, count 0 2006.257.02:24:04.44#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:24:04.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:24:04.44#ibcon#[25=USB\r\n] 2006.257.02:24:04.44#ibcon#*before write, iclass 21, count 0 2006.257.02:24:04.44#ibcon#enter sib2, iclass 21, count 0 2006.257.02:24:04.44#ibcon#flushed, iclass 21, count 0 2006.257.02:24:04.44#ibcon#about to write, iclass 21, count 0 2006.257.02:24:04.44#ibcon#wrote, iclass 21, count 0 2006.257.02:24:04.44#ibcon#about to read 3, iclass 21, count 0 2006.257.02:24:04.47#ibcon#read 3, iclass 21, count 0 2006.257.02:24:04.47#ibcon#about to read 4, iclass 21, count 0 2006.257.02:24:04.47#ibcon#read 4, iclass 21, count 0 2006.257.02:24:04.47#ibcon#about to read 5, iclass 21, count 0 2006.257.02:24:04.47#ibcon#read 5, iclass 21, count 0 2006.257.02:24:04.47#ibcon#about to read 6, iclass 21, count 0 2006.257.02:24:04.47#ibcon#read 6, iclass 21, count 0 2006.257.02:24:04.47#ibcon#end of sib2, iclass 21, count 0 2006.257.02:24:04.47#ibcon#*after write, iclass 21, count 0 2006.257.02:24:04.47#ibcon#*before return 0, iclass 21, count 0 2006.257.02:24:04.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:04.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:04.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:24:04.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:24:04.47$vck44/valo=4,624.99 2006.257.02:24:04.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.02:24:04.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.02:24:04.47#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:04.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:04.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:04.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:04.47#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:24:04.47#ibcon#first serial, iclass 23, count 0 2006.257.02:24:04.47#ibcon#enter sib2, iclass 23, count 0 2006.257.02:24:04.47#ibcon#flushed, iclass 23, count 0 2006.257.02:24:04.47#ibcon#about to write, iclass 23, count 0 2006.257.02:24:04.47#ibcon#wrote, iclass 23, count 0 2006.257.02:24:04.47#ibcon#about to read 3, iclass 23, count 0 2006.257.02:24:04.49#ibcon#read 3, iclass 23, count 0 2006.257.02:24:04.49#ibcon#about to read 4, iclass 23, count 0 2006.257.02:24:04.49#ibcon#read 4, iclass 23, count 0 2006.257.02:24:04.49#ibcon#about to read 5, iclass 23, count 0 2006.257.02:24:04.49#ibcon#read 5, iclass 23, count 0 2006.257.02:24:04.49#ibcon#about to read 6, iclass 23, count 0 2006.257.02:24:04.49#ibcon#read 6, iclass 23, count 0 2006.257.02:24:04.49#ibcon#end of sib2, iclass 23, count 0 2006.257.02:24:04.49#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:24:04.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:24:04.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:24:04.49#ibcon#*before write, iclass 23, count 0 2006.257.02:24:04.49#ibcon#enter sib2, iclass 23, count 0 2006.257.02:24:04.49#ibcon#flushed, iclass 23, count 0 2006.257.02:24:04.49#ibcon#about to write, iclass 23, count 0 2006.257.02:24:04.49#ibcon#wrote, iclass 23, count 0 2006.257.02:24:04.49#ibcon#about to read 3, iclass 23, count 0 2006.257.02:24:04.53#ibcon#read 3, iclass 23, count 0 2006.257.02:24:04.53#ibcon#about to read 4, iclass 23, count 0 2006.257.02:24:04.53#ibcon#read 4, iclass 23, count 0 2006.257.02:24:04.53#ibcon#about to read 5, iclass 23, count 0 2006.257.02:24:04.53#ibcon#read 5, iclass 23, count 0 2006.257.02:24:04.53#ibcon#about to read 6, iclass 23, count 0 2006.257.02:24:04.53#ibcon#read 6, iclass 23, count 0 2006.257.02:24:04.53#ibcon#end of sib2, iclass 23, count 0 2006.257.02:24:04.53#ibcon#*after write, iclass 23, count 0 2006.257.02:24:04.53#ibcon#*before return 0, iclass 23, count 0 2006.257.02:24:04.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:04.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:04.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:24:04.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:24:04.53$vck44/va=4,7 2006.257.02:24:04.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.02:24:04.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.02:24:04.53#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:04.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:04.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:04.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:04.59#ibcon#enter wrdev, iclass 25, count 2 2006.257.02:24:04.59#ibcon#first serial, iclass 25, count 2 2006.257.02:24:04.59#ibcon#enter sib2, iclass 25, count 2 2006.257.02:24:04.59#ibcon#flushed, iclass 25, count 2 2006.257.02:24:04.59#ibcon#about to write, iclass 25, count 2 2006.257.02:24:04.59#ibcon#wrote, iclass 25, count 2 2006.257.02:24:04.59#ibcon#about to read 3, iclass 25, count 2 2006.257.02:24:04.61#ibcon#read 3, iclass 25, count 2 2006.257.02:24:04.61#ibcon#about to read 4, iclass 25, count 2 2006.257.02:24:04.61#ibcon#read 4, iclass 25, count 2 2006.257.02:24:04.61#ibcon#about to read 5, iclass 25, count 2 2006.257.02:24:04.61#ibcon#read 5, iclass 25, count 2 2006.257.02:24:04.61#ibcon#about to read 6, iclass 25, count 2 2006.257.02:24:04.61#ibcon#read 6, iclass 25, count 2 2006.257.02:24:04.61#ibcon#end of sib2, iclass 25, count 2 2006.257.02:24:04.61#ibcon#*mode == 0, iclass 25, count 2 2006.257.02:24:04.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.02:24:04.61#ibcon#[25=AT04-07\r\n] 2006.257.02:24:04.61#ibcon#*before write, iclass 25, count 2 2006.257.02:24:04.61#ibcon#enter sib2, iclass 25, count 2 2006.257.02:24:04.61#ibcon#flushed, iclass 25, count 2 2006.257.02:24:04.61#ibcon#about to write, iclass 25, count 2 2006.257.02:24:04.61#ibcon#wrote, iclass 25, count 2 2006.257.02:24:04.61#ibcon#about to read 3, iclass 25, count 2 2006.257.02:24:04.64#ibcon#read 3, iclass 25, count 2 2006.257.02:24:04.64#ibcon#about to read 4, iclass 25, count 2 2006.257.02:24:04.64#ibcon#read 4, iclass 25, count 2 2006.257.02:24:04.64#ibcon#about to read 5, iclass 25, count 2 2006.257.02:24:04.64#ibcon#read 5, iclass 25, count 2 2006.257.02:24:04.64#ibcon#about to read 6, iclass 25, count 2 2006.257.02:24:04.64#ibcon#read 6, iclass 25, count 2 2006.257.02:24:04.64#ibcon#end of sib2, iclass 25, count 2 2006.257.02:24:04.64#ibcon#*after write, iclass 25, count 2 2006.257.02:24:04.64#ibcon#*before return 0, iclass 25, count 2 2006.257.02:24:04.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:04.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:04.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.02:24:04.64#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:04.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:04.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:04.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:04.76#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:24:04.76#ibcon#first serial, iclass 25, count 0 2006.257.02:24:04.76#ibcon#enter sib2, iclass 25, count 0 2006.257.02:24:04.76#ibcon#flushed, iclass 25, count 0 2006.257.02:24:04.76#ibcon#about to write, iclass 25, count 0 2006.257.02:24:04.76#ibcon#wrote, iclass 25, count 0 2006.257.02:24:04.76#ibcon#about to read 3, iclass 25, count 0 2006.257.02:24:04.78#ibcon#read 3, iclass 25, count 0 2006.257.02:24:04.78#ibcon#about to read 4, iclass 25, count 0 2006.257.02:24:04.78#ibcon#read 4, iclass 25, count 0 2006.257.02:24:04.78#ibcon#about to read 5, iclass 25, count 0 2006.257.02:24:04.78#ibcon#read 5, iclass 25, count 0 2006.257.02:24:04.78#ibcon#about to read 6, iclass 25, count 0 2006.257.02:24:04.78#ibcon#read 6, iclass 25, count 0 2006.257.02:24:04.78#ibcon#end of sib2, iclass 25, count 0 2006.257.02:24:04.78#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:24:04.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:24:04.78#ibcon#[25=USB\r\n] 2006.257.02:24:04.78#ibcon#*before write, iclass 25, count 0 2006.257.02:24:04.78#ibcon#enter sib2, iclass 25, count 0 2006.257.02:24:04.78#ibcon#flushed, iclass 25, count 0 2006.257.02:24:04.78#ibcon#about to write, iclass 25, count 0 2006.257.02:24:04.78#ibcon#wrote, iclass 25, count 0 2006.257.02:24:04.78#ibcon#about to read 3, iclass 25, count 0 2006.257.02:24:04.81#ibcon#read 3, iclass 25, count 0 2006.257.02:24:04.81#ibcon#about to read 4, iclass 25, count 0 2006.257.02:24:04.81#ibcon#read 4, iclass 25, count 0 2006.257.02:24:04.81#ibcon#about to read 5, iclass 25, count 0 2006.257.02:24:04.81#ibcon#read 5, iclass 25, count 0 2006.257.02:24:04.81#ibcon#about to read 6, iclass 25, count 0 2006.257.02:24:04.81#ibcon#read 6, iclass 25, count 0 2006.257.02:24:04.81#ibcon#end of sib2, iclass 25, count 0 2006.257.02:24:04.81#ibcon#*after write, iclass 25, count 0 2006.257.02:24:04.81#ibcon#*before return 0, iclass 25, count 0 2006.257.02:24:04.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:04.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:04.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:24:04.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:24:04.81$vck44/valo=5,734.99 2006.257.02:24:04.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.02:24:04.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.02:24:04.81#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:04.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:04.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:04.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:04.81#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:24:04.81#ibcon#first serial, iclass 27, count 0 2006.257.02:24:04.81#ibcon#enter sib2, iclass 27, count 0 2006.257.02:24:04.81#ibcon#flushed, iclass 27, count 0 2006.257.02:24:04.81#ibcon#about to write, iclass 27, count 0 2006.257.02:24:04.81#ibcon#wrote, iclass 27, count 0 2006.257.02:24:04.81#ibcon#about to read 3, iclass 27, count 0 2006.257.02:24:04.83#ibcon#read 3, iclass 27, count 0 2006.257.02:24:04.83#ibcon#about to read 4, iclass 27, count 0 2006.257.02:24:04.83#ibcon#read 4, iclass 27, count 0 2006.257.02:24:04.83#ibcon#about to read 5, iclass 27, count 0 2006.257.02:24:04.83#ibcon#read 5, iclass 27, count 0 2006.257.02:24:04.83#ibcon#about to read 6, iclass 27, count 0 2006.257.02:24:04.83#ibcon#read 6, iclass 27, count 0 2006.257.02:24:04.83#ibcon#end of sib2, iclass 27, count 0 2006.257.02:24:04.83#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:24:04.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:24:04.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:24:04.83#ibcon#*before write, iclass 27, count 0 2006.257.02:24:04.83#ibcon#enter sib2, iclass 27, count 0 2006.257.02:24:04.83#ibcon#flushed, iclass 27, count 0 2006.257.02:24:04.83#ibcon#about to write, iclass 27, count 0 2006.257.02:24:04.83#ibcon#wrote, iclass 27, count 0 2006.257.02:24:04.83#ibcon#about to read 3, iclass 27, count 0 2006.257.02:24:04.87#ibcon#read 3, iclass 27, count 0 2006.257.02:24:04.87#ibcon#about to read 4, iclass 27, count 0 2006.257.02:24:04.87#ibcon#read 4, iclass 27, count 0 2006.257.02:24:04.87#ibcon#about to read 5, iclass 27, count 0 2006.257.02:24:04.87#ibcon#read 5, iclass 27, count 0 2006.257.02:24:04.87#ibcon#about to read 6, iclass 27, count 0 2006.257.02:24:04.87#ibcon#read 6, iclass 27, count 0 2006.257.02:24:04.87#ibcon#end of sib2, iclass 27, count 0 2006.257.02:24:04.87#ibcon#*after write, iclass 27, count 0 2006.257.02:24:04.87#ibcon#*before return 0, iclass 27, count 0 2006.257.02:24:04.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:04.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:04.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:24:04.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:24:04.87$vck44/va=5,4 2006.257.02:24:04.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.02:24:04.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.02:24:04.87#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:04.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:04.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:04.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:04.93#ibcon#enter wrdev, iclass 29, count 2 2006.257.02:24:04.93#ibcon#first serial, iclass 29, count 2 2006.257.02:24:04.93#ibcon#enter sib2, iclass 29, count 2 2006.257.02:24:04.93#ibcon#flushed, iclass 29, count 2 2006.257.02:24:04.93#ibcon#about to write, iclass 29, count 2 2006.257.02:24:04.93#ibcon#wrote, iclass 29, count 2 2006.257.02:24:04.93#ibcon#about to read 3, iclass 29, count 2 2006.257.02:24:04.95#ibcon#read 3, iclass 29, count 2 2006.257.02:24:04.95#ibcon#about to read 4, iclass 29, count 2 2006.257.02:24:04.95#ibcon#read 4, iclass 29, count 2 2006.257.02:24:04.95#ibcon#about to read 5, iclass 29, count 2 2006.257.02:24:04.95#ibcon#read 5, iclass 29, count 2 2006.257.02:24:04.95#ibcon#about to read 6, iclass 29, count 2 2006.257.02:24:04.95#ibcon#read 6, iclass 29, count 2 2006.257.02:24:04.95#ibcon#end of sib2, iclass 29, count 2 2006.257.02:24:04.95#ibcon#*mode == 0, iclass 29, count 2 2006.257.02:24:04.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.02:24:04.95#ibcon#[25=AT05-04\r\n] 2006.257.02:24:04.95#ibcon#*before write, iclass 29, count 2 2006.257.02:24:04.95#ibcon#enter sib2, iclass 29, count 2 2006.257.02:24:04.95#ibcon#flushed, iclass 29, count 2 2006.257.02:24:04.95#ibcon#about to write, iclass 29, count 2 2006.257.02:24:04.95#ibcon#wrote, iclass 29, count 2 2006.257.02:24:04.95#ibcon#about to read 3, iclass 29, count 2 2006.257.02:24:04.98#ibcon#read 3, iclass 29, count 2 2006.257.02:24:04.98#ibcon#about to read 4, iclass 29, count 2 2006.257.02:24:04.98#ibcon#read 4, iclass 29, count 2 2006.257.02:24:04.98#ibcon#about to read 5, iclass 29, count 2 2006.257.02:24:04.98#ibcon#read 5, iclass 29, count 2 2006.257.02:24:04.98#ibcon#about to read 6, iclass 29, count 2 2006.257.02:24:04.98#ibcon#read 6, iclass 29, count 2 2006.257.02:24:04.98#ibcon#end of sib2, iclass 29, count 2 2006.257.02:24:04.98#ibcon#*after write, iclass 29, count 2 2006.257.02:24:04.98#ibcon#*before return 0, iclass 29, count 2 2006.257.02:24:04.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:04.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:04.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.02:24:04.98#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:04.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:05.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:05.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:05.10#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:24:05.10#ibcon#first serial, iclass 29, count 0 2006.257.02:24:05.10#ibcon#enter sib2, iclass 29, count 0 2006.257.02:24:05.10#ibcon#flushed, iclass 29, count 0 2006.257.02:24:05.10#ibcon#about to write, iclass 29, count 0 2006.257.02:24:05.10#ibcon#wrote, iclass 29, count 0 2006.257.02:24:05.10#ibcon#about to read 3, iclass 29, count 0 2006.257.02:24:05.12#ibcon#read 3, iclass 29, count 0 2006.257.02:24:05.12#ibcon#about to read 4, iclass 29, count 0 2006.257.02:24:05.12#ibcon#read 4, iclass 29, count 0 2006.257.02:24:05.12#ibcon#about to read 5, iclass 29, count 0 2006.257.02:24:05.12#ibcon#read 5, iclass 29, count 0 2006.257.02:24:05.12#ibcon#about to read 6, iclass 29, count 0 2006.257.02:24:05.12#ibcon#read 6, iclass 29, count 0 2006.257.02:24:05.12#ibcon#end of sib2, iclass 29, count 0 2006.257.02:24:05.12#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:24:05.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:24:05.12#ibcon#[25=USB\r\n] 2006.257.02:24:05.12#ibcon#*before write, iclass 29, count 0 2006.257.02:24:05.12#ibcon#enter sib2, iclass 29, count 0 2006.257.02:24:05.12#ibcon#flushed, iclass 29, count 0 2006.257.02:24:05.12#ibcon#about to write, iclass 29, count 0 2006.257.02:24:05.12#ibcon#wrote, iclass 29, count 0 2006.257.02:24:05.12#ibcon#about to read 3, iclass 29, count 0 2006.257.02:24:05.15#ibcon#read 3, iclass 29, count 0 2006.257.02:24:05.15#ibcon#about to read 4, iclass 29, count 0 2006.257.02:24:05.15#ibcon#read 4, iclass 29, count 0 2006.257.02:24:05.15#ibcon#about to read 5, iclass 29, count 0 2006.257.02:24:05.15#ibcon#read 5, iclass 29, count 0 2006.257.02:24:05.15#ibcon#about to read 6, iclass 29, count 0 2006.257.02:24:05.15#ibcon#read 6, iclass 29, count 0 2006.257.02:24:05.15#ibcon#end of sib2, iclass 29, count 0 2006.257.02:24:05.15#ibcon#*after write, iclass 29, count 0 2006.257.02:24:05.15#ibcon#*before return 0, iclass 29, count 0 2006.257.02:24:05.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:05.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:05.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:24:05.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:24:05.15$vck44/valo=6,814.99 2006.257.02:24:05.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.02:24:05.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.02:24:05.15#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:05.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:05.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:05.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:05.15#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:24:05.15#ibcon#first serial, iclass 31, count 0 2006.257.02:24:05.15#ibcon#enter sib2, iclass 31, count 0 2006.257.02:24:05.15#ibcon#flushed, iclass 31, count 0 2006.257.02:24:05.15#ibcon#about to write, iclass 31, count 0 2006.257.02:24:05.15#ibcon#wrote, iclass 31, count 0 2006.257.02:24:05.15#ibcon#about to read 3, iclass 31, count 0 2006.257.02:24:05.17#ibcon#read 3, iclass 31, count 0 2006.257.02:24:05.17#ibcon#about to read 4, iclass 31, count 0 2006.257.02:24:05.17#ibcon#read 4, iclass 31, count 0 2006.257.02:24:05.17#ibcon#about to read 5, iclass 31, count 0 2006.257.02:24:05.17#ibcon#read 5, iclass 31, count 0 2006.257.02:24:05.17#ibcon#about to read 6, iclass 31, count 0 2006.257.02:24:05.17#ibcon#read 6, iclass 31, count 0 2006.257.02:24:05.17#ibcon#end of sib2, iclass 31, count 0 2006.257.02:24:05.17#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:24:05.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:24:05.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:24:05.17#ibcon#*before write, iclass 31, count 0 2006.257.02:24:05.17#ibcon#enter sib2, iclass 31, count 0 2006.257.02:24:05.17#ibcon#flushed, iclass 31, count 0 2006.257.02:24:05.17#ibcon#about to write, iclass 31, count 0 2006.257.02:24:05.17#ibcon#wrote, iclass 31, count 0 2006.257.02:24:05.17#ibcon#about to read 3, iclass 31, count 0 2006.257.02:24:05.21#ibcon#read 3, iclass 31, count 0 2006.257.02:24:05.21#ibcon#about to read 4, iclass 31, count 0 2006.257.02:24:05.21#ibcon#read 4, iclass 31, count 0 2006.257.02:24:05.21#ibcon#about to read 5, iclass 31, count 0 2006.257.02:24:05.21#ibcon#read 5, iclass 31, count 0 2006.257.02:24:05.21#ibcon#about to read 6, iclass 31, count 0 2006.257.02:24:05.21#ibcon#read 6, iclass 31, count 0 2006.257.02:24:05.21#ibcon#end of sib2, iclass 31, count 0 2006.257.02:24:05.21#ibcon#*after write, iclass 31, count 0 2006.257.02:24:05.21#ibcon#*before return 0, iclass 31, count 0 2006.257.02:24:05.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:05.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:05.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:24:05.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:24:05.21$vck44/va=6,4 2006.257.02:24:05.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.02:24:05.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.02:24:05.21#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:05.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:05.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:05.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:05.27#ibcon#enter wrdev, iclass 33, count 2 2006.257.02:24:05.27#ibcon#first serial, iclass 33, count 2 2006.257.02:24:05.27#ibcon#enter sib2, iclass 33, count 2 2006.257.02:24:05.27#ibcon#flushed, iclass 33, count 2 2006.257.02:24:05.27#ibcon#about to write, iclass 33, count 2 2006.257.02:24:05.27#ibcon#wrote, iclass 33, count 2 2006.257.02:24:05.27#ibcon#about to read 3, iclass 33, count 2 2006.257.02:24:05.29#ibcon#read 3, iclass 33, count 2 2006.257.02:24:05.29#ibcon#about to read 4, iclass 33, count 2 2006.257.02:24:05.29#ibcon#read 4, iclass 33, count 2 2006.257.02:24:05.29#ibcon#about to read 5, iclass 33, count 2 2006.257.02:24:05.29#ibcon#read 5, iclass 33, count 2 2006.257.02:24:05.29#ibcon#about to read 6, iclass 33, count 2 2006.257.02:24:05.29#ibcon#read 6, iclass 33, count 2 2006.257.02:24:05.29#ibcon#end of sib2, iclass 33, count 2 2006.257.02:24:05.29#ibcon#*mode == 0, iclass 33, count 2 2006.257.02:24:05.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.02:24:05.29#ibcon#[25=AT06-04\r\n] 2006.257.02:24:05.29#ibcon#*before write, iclass 33, count 2 2006.257.02:24:05.29#ibcon#enter sib2, iclass 33, count 2 2006.257.02:24:05.29#ibcon#flushed, iclass 33, count 2 2006.257.02:24:05.29#ibcon#about to write, iclass 33, count 2 2006.257.02:24:05.29#ibcon#wrote, iclass 33, count 2 2006.257.02:24:05.29#ibcon#about to read 3, iclass 33, count 2 2006.257.02:24:05.32#ibcon#read 3, iclass 33, count 2 2006.257.02:24:05.32#ibcon#about to read 4, iclass 33, count 2 2006.257.02:24:05.32#ibcon#read 4, iclass 33, count 2 2006.257.02:24:05.32#ibcon#about to read 5, iclass 33, count 2 2006.257.02:24:05.32#ibcon#read 5, iclass 33, count 2 2006.257.02:24:05.32#ibcon#about to read 6, iclass 33, count 2 2006.257.02:24:05.32#ibcon#read 6, iclass 33, count 2 2006.257.02:24:05.32#ibcon#end of sib2, iclass 33, count 2 2006.257.02:24:05.32#ibcon#*after write, iclass 33, count 2 2006.257.02:24:05.32#ibcon#*before return 0, iclass 33, count 2 2006.257.02:24:05.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:05.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:05.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.02:24:05.32#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:05.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:05.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:05.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:05.44#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:24:05.44#ibcon#first serial, iclass 33, count 0 2006.257.02:24:05.44#ibcon#enter sib2, iclass 33, count 0 2006.257.02:24:05.44#ibcon#flushed, iclass 33, count 0 2006.257.02:24:05.44#ibcon#about to write, iclass 33, count 0 2006.257.02:24:05.44#ibcon#wrote, iclass 33, count 0 2006.257.02:24:05.44#ibcon#about to read 3, iclass 33, count 0 2006.257.02:24:05.46#ibcon#read 3, iclass 33, count 0 2006.257.02:24:05.46#ibcon#about to read 4, iclass 33, count 0 2006.257.02:24:05.46#ibcon#read 4, iclass 33, count 0 2006.257.02:24:05.46#ibcon#about to read 5, iclass 33, count 0 2006.257.02:24:05.46#ibcon#read 5, iclass 33, count 0 2006.257.02:24:05.46#ibcon#about to read 6, iclass 33, count 0 2006.257.02:24:05.46#ibcon#read 6, iclass 33, count 0 2006.257.02:24:05.46#ibcon#end of sib2, iclass 33, count 0 2006.257.02:24:05.46#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:24:05.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:24:05.46#ibcon#[25=USB\r\n] 2006.257.02:24:05.46#ibcon#*before write, iclass 33, count 0 2006.257.02:24:05.46#ibcon#enter sib2, iclass 33, count 0 2006.257.02:24:05.46#ibcon#flushed, iclass 33, count 0 2006.257.02:24:05.46#ibcon#about to write, iclass 33, count 0 2006.257.02:24:05.46#ibcon#wrote, iclass 33, count 0 2006.257.02:24:05.46#ibcon#about to read 3, iclass 33, count 0 2006.257.02:24:05.49#ibcon#read 3, iclass 33, count 0 2006.257.02:24:05.49#ibcon#about to read 4, iclass 33, count 0 2006.257.02:24:05.49#ibcon#read 4, iclass 33, count 0 2006.257.02:24:05.49#ibcon#about to read 5, iclass 33, count 0 2006.257.02:24:05.49#ibcon#read 5, iclass 33, count 0 2006.257.02:24:05.49#ibcon#about to read 6, iclass 33, count 0 2006.257.02:24:05.49#ibcon#read 6, iclass 33, count 0 2006.257.02:24:05.49#ibcon#end of sib2, iclass 33, count 0 2006.257.02:24:05.49#ibcon#*after write, iclass 33, count 0 2006.257.02:24:05.49#ibcon#*before return 0, iclass 33, count 0 2006.257.02:24:05.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:05.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:05.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:24:05.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:24:05.49$vck44/valo=7,864.99 2006.257.02:24:05.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.02:24:05.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.02:24:05.49#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:05.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:05.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:05.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:05.49#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:24:05.49#ibcon#first serial, iclass 35, count 0 2006.257.02:24:05.49#ibcon#enter sib2, iclass 35, count 0 2006.257.02:24:05.49#ibcon#flushed, iclass 35, count 0 2006.257.02:24:05.49#ibcon#about to write, iclass 35, count 0 2006.257.02:24:05.49#ibcon#wrote, iclass 35, count 0 2006.257.02:24:05.49#ibcon#about to read 3, iclass 35, count 0 2006.257.02:24:05.51#ibcon#read 3, iclass 35, count 0 2006.257.02:24:05.51#ibcon#about to read 4, iclass 35, count 0 2006.257.02:24:05.51#ibcon#read 4, iclass 35, count 0 2006.257.02:24:05.51#ibcon#about to read 5, iclass 35, count 0 2006.257.02:24:05.51#ibcon#read 5, iclass 35, count 0 2006.257.02:24:05.51#ibcon#about to read 6, iclass 35, count 0 2006.257.02:24:05.51#ibcon#read 6, iclass 35, count 0 2006.257.02:24:05.51#ibcon#end of sib2, iclass 35, count 0 2006.257.02:24:05.51#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:24:05.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:24:05.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:24:05.51#ibcon#*before write, iclass 35, count 0 2006.257.02:24:05.51#ibcon#enter sib2, iclass 35, count 0 2006.257.02:24:05.51#ibcon#flushed, iclass 35, count 0 2006.257.02:24:05.51#ibcon#about to write, iclass 35, count 0 2006.257.02:24:05.51#ibcon#wrote, iclass 35, count 0 2006.257.02:24:05.51#ibcon#about to read 3, iclass 35, count 0 2006.257.02:24:05.55#ibcon#read 3, iclass 35, count 0 2006.257.02:24:05.55#ibcon#about to read 4, iclass 35, count 0 2006.257.02:24:05.55#ibcon#read 4, iclass 35, count 0 2006.257.02:24:05.55#ibcon#about to read 5, iclass 35, count 0 2006.257.02:24:05.55#ibcon#read 5, iclass 35, count 0 2006.257.02:24:05.55#ibcon#about to read 6, iclass 35, count 0 2006.257.02:24:05.55#ibcon#read 6, iclass 35, count 0 2006.257.02:24:05.55#ibcon#end of sib2, iclass 35, count 0 2006.257.02:24:05.55#ibcon#*after write, iclass 35, count 0 2006.257.02:24:05.55#ibcon#*before return 0, iclass 35, count 0 2006.257.02:24:05.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:05.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:05.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:24:05.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:24:05.55$vck44/va=7,4 2006.257.02:24:05.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.02:24:05.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.02:24:05.55#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:05.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:05.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:05.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:05.61#ibcon#enter wrdev, iclass 37, count 2 2006.257.02:24:05.61#ibcon#first serial, iclass 37, count 2 2006.257.02:24:05.61#ibcon#enter sib2, iclass 37, count 2 2006.257.02:24:05.61#ibcon#flushed, iclass 37, count 2 2006.257.02:24:05.61#ibcon#about to write, iclass 37, count 2 2006.257.02:24:05.61#ibcon#wrote, iclass 37, count 2 2006.257.02:24:05.61#ibcon#about to read 3, iclass 37, count 2 2006.257.02:24:05.63#ibcon#read 3, iclass 37, count 2 2006.257.02:24:05.63#ibcon#about to read 4, iclass 37, count 2 2006.257.02:24:05.63#ibcon#read 4, iclass 37, count 2 2006.257.02:24:05.63#ibcon#about to read 5, iclass 37, count 2 2006.257.02:24:05.63#ibcon#read 5, iclass 37, count 2 2006.257.02:24:05.63#ibcon#about to read 6, iclass 37, count 2 2006.257.02:24:05.63#ibcon#read 6, iclass 37, count 2 2006.257.02:24:05.63#ibcon#end of sib2, iclass 37, count 2 2006.257.02:24:05.63#ibcon#*mode == 0, iclass 37, count 2 2006.257.02:24:05.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.02:24:05.63#ibcon#[25=AT07-04\r\n] 2006.257.02:24:05.63#ibcon#*before write, iclass 37, count 2 2006.257.02:24:05.63#ibcon#enter sib2, iclass 37, count 2 2006.257.02:24:05.63#ibcon#flushed, iclass 37, count 2 2006.257.02:24:05.63#ibcon#about to write, iclass 37, count 2 2006.257.02:24:05.63#ibcon#wrote, iclass 37, count 2 2006.257.02:24:05.63#ibcon#about to read 3, iclass 37, count 2 2006.257.02:24:05.66#ibcon#read 3, iclass 37, count 2 2006.257.02:24:05.66#ibcon#about to read 4, iclass 37, count 2 2006.257.02:24:05.66#ibcon#read 4, iclass 37, count 2 2006.257.02:24:05.66#ibcon#about to read 5, iclass 37, count 2 2006.257.02:24:05.66#ibcon#read 5, iclass 37, count 2 2006.257.02:24:05.66#ibcon#about to read 6, iclass 37, count 2 2006.257.02:24:05.66#ibcon#read 6, iclass 37, count 2 2006.257.02:24:05.66#ibcon#end of sib2, iclass 37, count 2 2006.257.02:24:05.66#ibcon#*after write, iclass 37, count 2 2006.257.02:24:05.66#ibcon#*before return 0, iclass 37, count 2 2006.257.02:24:05.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:05.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:05.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.02:24:05.66#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:05.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:05.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:05.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:05.78#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:24:05.78#ibcon#first serial, iclass 37, count 0 2006.257.02:24:05.78#ibcon#enter sib2, iclass 37, count 0 2006.257.02:24:05.78#ibcon#flushed, iclass 37, count 0 2006.257.02:24:05.78#ibcon#about to write, iclass 37, count 0 2006.257.02:24:05.78#ibcon#wrote, iclass 37, count 0 2006.257.02:24:05.78#ibcon#about to read 3, iclass 37, count 0 2006.257.02:24:05.80#ibcon#read 3, iclass 37, count 0 2006.257.02:24:05.80#ibcon#about to read 4, iclass 37, count 0 2006.257.02:24:05.80#ibcon#read 4, iclass 37, count 0 2006.257.02:24:05.80#ibcon#about to read 5, iclass 37, count 0 2006.257.02:24:05.80#ibcon#read 5, iclass 37, count 0 2006.257.02:24:05.80#ibcon#about to read 6, iclass 37, count 0 2006.257.02:24:05.80#ibcon#read 6, iclass 37, count 0 2006.257.02:24:05.80#ibcon#end of sib2, iclass 37, count 0 2006.257.02:24:05.80#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:24:05.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:24:05.80#ibcon#[25=USB\r\n] 2006.257.02:24:05.80#ibcon#*before write, iclass 37, count 0 2006.257.02:24:05.80#ibcon#enter sib2, iclass 37, count 0 2006.257.02:24:05.80#ibcon#flushed, iclass 37, count 0 2006.257.02:24:05.80#ibcon#about to write, iclass 37, count 0 2006.257.02:24:05.80#ibcon#wrote, iclass 37, count 0 2006.257.02:24:05.80#ibcon#about to read 3, iclass 37, count 0 2006.257.02:24:05.83#ibcon#read 3, iclass 37, count 0 2006.257.02:24:05.83#ibcon#about to read 4, iclass 37, count 0 2006.257.02:24:05.83#ibcon#read 4, iclass 37, count 0 2006.257.02:24:05.83#ibcon#about to read 5, iclass 37, count 0 2006.257.02:24:05.83#ibcon#read 5, iclass 37, count 0 2006.257.02:24:05.83#ibcon#about to read 6, iclass 37, count 0 2006.257.02:24:05.83#ibcon#read 6, iclass 37, count 0 2006.257.02:24:05.83#ibcon#end of sib2, iclass 37, count 0 2006.257.02:24:05.83#ibcon#*after write, iclass 37, count 0 2006.257.02:24:05.83#ibcon#*before return 0, iclass 37, count 0 2006.257.02:24:05.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:05.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:05.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:24:05.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:24:05.83$vck44/valo=8,884.99 2006.257.02:24:05.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.02:24:05.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.02:24:05.83#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:05.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:05.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:05.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:05.83#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:24:05.83#ibcon#first serial, iclass 39, count 0 2006.257.02:24:05.83#ibcon#enter sib2, iclass 39, count 0 2006.257.02:24:05.83#ibcon#flushed, iclass 39, count 0 2006.257.02:24:05.83#ibcon#about to write, iclass 39, count 0 2006.257.02:24:05.83#ibcon#wrote, iclass 39, count 0 2006.257.02:24:05.83#ibcon#about to read 3, iclass 39, count 0 2006.257.02:24:05.85#ibcon#read 3, iclass 39, count 0 2006.257.02:24:05.85#ibcon#about to read 4, iclass 39, count 0 2006.257.02:24:05.85#ibcon#read 4, iclass 39, count 0 2006.257.02:24:05.85#ibcon#about to read 5, iclass 39, count 0 2006.257.02:24:05.85#ibcon#read 5, iclass 39, count 0 2006.257.02:24:05.85#ibcon#about to read 6, iclass 39, count 0 2006.257.02:24:05.85#ibcon#read 6, iclass 39, count 0 2006.257.02:24:05.85#ibcon#end of sib2, iclass 39, count 0 2006.257.02:24:05.85#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:24:05.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:24:05.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:24:05.85#ibcon#*before write, iclass 39, count 0 2006.257.02:24:05.85#ibcon#enter sib2, iclass 39, count 0 2006.257.02:24:05.85#ibcon#flushed, iclass 39, count 0 2006.257.02:24:05.85#ibcon#about to write, iclass 39, count 0 2006.257.02:24:05.85#ibcon#wrote, iclass 39, count 0 2006.257.02:24:05.85#ibcon#about to read 3, iclass 39, count 0 2006.257.02:24:05.89#ibcon#read 3, iclass 39, count 0 2006.257.02:24:05.89#ibcon#about to read 4, iclass 39, count 0 2006.257.02:24:05.89#ibcon#read 4, iclass 39, count 0 2006.257.02:24:05.89#ibcon#about to read 5, iclass 39, count 0 2006.257.02:24:05.89#ibcon#read 5, iclass 39, count 0 2006.257.02:24:05.89#ibcon#about to read 6, iclass 39, count 0 2006.257.02:24:05.89#ibcon#read 6, iclass 39, count 0 2006.257.02:24:05.89#ibcon#end of sib2, iclass 39, count 0 2006.257.02:24:05.89#ibcon#*after write, iclass 39, count 0 2006.257.02:24:05.89#ibcon#*before return 0, iclass 39, count 0 2006.257.02:24:05.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:05.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:05.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:24:05.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:24:05.89$vck44/va=8,4 2006.257.02:24:05.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.02:24:05.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.02:24:05.89#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:05.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:24:05.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:24:05.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:24:05.95#ibcon#enter wrdev, iclass 3, count 2 2006.257.02:24:05.95#ibcon#first serial, iclass 3, count 2 2006.257.02:24:05.95#ibcon#enter sib2, iclass 3, count 2 2006.257.02:24:05.95#ibcon#flushed, iclass 3, count 2 2006.257.02:24:05.95#ibcon#about to write, iclass 3, count 2 2006.257.02:24:05.95#ibcon#wrote, iclass 3, count 2 2006.257.02:24:05.95#ibcon#about to read 3, iclass 3, count 2 2006.257.02:24:05.97#ibcon#read 3, iclass 3, count 2 2006.257.02:24:05.97#ibcon#about to read 4, iclass 3, count 2 2006.257.02:24:05.97#ibcon#read 4, iclass 3, count 2 2006.257.02:24:05.97#ibcon#about to read 5, iclass 3, count 2 2006.257.02:24:05.97#ibcon#read 5, iclass 3, count 2 2006.257.02:24:05.97#ibcon#about to read 6, iclass 3, count 2 2006.257.02:24:05.97#ibcon#read 6, iclass 3, count 2 2006.257.02:24:05.97#ibcon#end of sib2, iclass 3, count 2 2006.257.02:24:05.97#ibcon#*mode == 0, iclass 3, count 2 2006.257.02:24:05.97#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.02:24:05.97#ibcon#[25=AT08-04\r\n] 2006.257.02:24:05.97#ibcon#*before write, iclass 3, count 2 2006.257.02:24:05.97#ibcon#enter sib2, iclass 3, count 2 2006.257.02:24:05.97#ibcon#flushed, iclass 3, count 2 2006.257.02:24:05.97#ibcon#about to write, iclass 3, count 2 2006.257.02:24:05.97#ibcon#wrote, iclass 3, count 2 2006.257.02:24:05.97#ibcon#about to read 3, iclass 3, count 2 2006.257.02:24:06.00#ibcon#read 3, iclass 3, count 2 2006.257.02:24:06.00#ibcon#about to read 4, iclass 3, count 2 2006.257.02:24:06.00#ibcon#read 4, iclass 3, count 2 2006.257.02:24:06.00#ibcon#about to read 5, iclass 3, count 2 2006.257.02:24:06.00#ibcon#read 5, iclass 3, count 2 2006.257.02:24:06.00#ibcon#about to read 6, iclass 3, count 2 2006.257.02:24:06.00#ibcon#read 6, iclass 3, count 2 2006.257.02:24:06.00#ibcon#end of sib2, iclass 3, count 2 2006.257.02:24:06.00#ibcon#*after write, iclass 3, count 2 2006.257.02:24:06.00#ibcon#*before return 0, iclass 3, count 2 2006.257.02:24:06.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:24:06.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:24:06.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.02:24:06.00#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:06.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:24:06.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:24:06.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:24:06.12#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:24:06.12#ibcon#first serial, iclass 3, count 0 2006.257.02:24:06.12#ibcon#enter sib2, iclass 3, count 0 2006.257.02:24:06.12#ibcon#flushed, iclass 3, count 0 2006.257.02:24:06.12#ibcon#about to write, iclass 3, count 0 2006.257.02:24:06.12#ibcon#wrote, iclass 3, count 0 2006.257.02:24:06.12#ibcon#about to read 3, iclass 3, count 0 2006.257.02:24:06.14#ibcon#read 3, iclass 3, count 0 2006.257.02:24:06.14#ibcon#about to read 4, iclass 3, count 0 2006.257.02:24:06.14#ibcon#read 4, iclass 3, count 0 2006.257.02:24:06.14#ibcon#about to read 5, iclass 3, count 0 2006.257.02:24:06.14#ibcon#read 5, iclass 3, count 0 2006.257.02:24:06.14#ibcon#about to read 6, iclass 3, count 0 2006.257.02:24:06.14#ibcon#read 6, iclass 3, count 0 2006.257.02:24:06.14#ibcon#end of sib2, iclass 3, count 0 2006.257.02:24:06.14#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:24:06.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:24:06.14#ibcon#[25=USB\r\n] 2006.257.02:24:06.14#ibcon#*before write, iclass 3, count 0 2006.257.02:24:06.14#ibcon#enter sib2, iclass 3, count 0 2006.257.02:24:06.14#ibcon#flushed, iclass 3, count 0 2006.257.02:24:06.14#ibcon#about to write, iclass 3, count 0 2006.257.02:24:06.14#ibcon#wrote, iclass 3, count 0 2006.257.02:24:06.14#ibcon#about to read 3, iclass 3, count 0 2006.257.02:24:06.17#ibcon#read 3, iclass 3, count 0 2006.257.02:24:06.17#ibcon#about to read 4, iclass 3, count 0 2006.257.02:24:06.17#ibcon#read 4, iclass 3, count 0 2006.257.02:24:06.17#ibcon#about to read 5, iclass 3, count 0 2006.257.02:24:06.17#ibcon#read 5, iclass 3, count 0 2006.257.02:24:06.17#ibcon#about to read 6, iclass 3, count 0 2006.257.02:24:06.17#ibcon#read 6, iclass 3, count 0 2006.257.02:24:06.17#ibcon#end of sib2, iclass 3, count 0 2006.257.02:24:06.17#ibcon#*after write, iclass 3, count 0 2006.257.02:24:06.17#ibcon#*before return 0, iclass 3, count 0 2006.257.02:24:06.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:24:06.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:24:06.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:24:06.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:24:06.17$vck44/vblo=1,629.99 2006.257.02:24:06.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.02:24:06.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.02:24:06.17#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:06.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:24:06.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:24:06.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:24:06.17#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:24:06.17#ibcon#first serial, iclass 5, count 0 2006.257.02:24:06.17#ibcon#enter sib2, iclass 5, count 0 2006.257.02:24:06.17#ibcon#flushed, iclass 5, count 0 2006.257.02:24:06.17#ibcon#about to write, iclass 5, count 0 2006.257.02:24:06.17#ibcon#wrote, iclass 5, count 0 2006.257.02:24:06.17#ibcon#about to read 3, iclass 5, count 0 2006.257.02:24:06.19#ibcon#read 3, iclass 5, count 0 2006.257.02:24:06.19#ibcon#about to read 4, iclass 5, count 0 2006.257.02:24:06.19#ibcon#read 4, iclass 5, count 0 2006.257.02:24:06.19#ibcon#about to read 5, iclass 5, count 0 2006.257.02:24:06.19#ibcon#read 5, iclass 5, count 0 2006.257.02:24:06.19#ibcon#about to read 6, iclass 5, count 0 2006.257.02:24:06.19#ibcon#read 6, iclass 5, count 0 2006.257.02:24:06.19#ibcon#end of sib2, iclass 5, count 0 2006.257.02:24:06.19#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:24:06.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:24:06.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:24:06.19#ibcon#*before write, iclass 5, count 0 2006.257.02:24:06.19#ibcon#enter sib2, iclass 5, count 0 2006.257.02:24:06.19#ibcon#flushed, iclass 5, count 0 2006.257.02:24:06.19#ibcon#about to write, iclass 5, count 0 2006.257.02:24:06.19#ibcon#wrote, iclass 5, count 0 2006.257.02:24:06.19#ibcon#about to read 3, iclass 5, count 0 2006.257.02:24:06.23#ibcon#read 3, iclass 5, count 0 2006.257.02:24:06.23#ibcon#about to read 4, iclass 5, count 0 2006.257.02:24:06.23#ibcon#read 4, iclass 5, count 0 2006.257.02:24:06.23#ibcon#about to read 5, iclass 5, count 0 2006.257.02:24:06.23#ibcon#read 5, iclass 5, count 0 2006.257.02:24:06.23#ibcon#about to read 6, iclass 5, count 0 2006.257.02:24:06.23#ibcon#read 6, iclass 5, count 0 2006.257.02:24:06.23#ibcon#end of sib2, iclass 5, count 0 2006.257.02:24:06.23#ibcon#*after write, iclass 5, count 0 2006.257.02:24:06.23#ibcon#*before return 0, iclass 5, count 0 2006.257.02:24:06.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:24:06.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:24:06.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:24:06.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:24:06.23$vck44/vb=1,4 2006.257.02:24:06.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.02:24:06.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.02:24:06.23#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:06.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:24:06.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:24:06.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:24:06.23#ibcon#enter wrdev, iclass 7, count 2 2006.257.02:24:06.23#ibcon#first serial, iclass 7, count 2 2006.257.02:24:06.23#ibcon#enter sib2, iclass 7, count 2 2006.257.02:24:06.23#ibcon#flushed, iclass 7, count 2 2006.257.02:24:06.23#ibcon#about to write, iclass 7, count 2 2006.257.02:24:06.23#ibcon#wrote, iclass 7, count 2 2006.257.02:24:06.23#ibcon#about to read 3, iclass 7, count 2 2006.257.02:24:06.25#ibcon#read 3, iclass 7, count 2 2006.257.02:24:06.25#ibcon#about to read 4, iclass 7, count 2 2006.257.02:24:06.25#ibcon#read 4, iclass 7, count 2 2006.257.02:24:06.25#ibcon#about to read 5, iclass 7, count 2 2006.257.02:24:06.25#ibcon#read 5, iclass 7, count 2 2006.257.02:24:06.25#ibcon#about to read 6, iclass 7, count 2 2006.257.02:24:06.25#ibcon#read 6, iclass 7, count 2 2006.257.02:24:06.25#ibcon#end of sib2, iclass 7, count 2 2006.257.02:24:06.25#ibcon#*mode == 0, iclass 7, count 2 2006.257.02:24:06.25#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.02:24:06.25#ibcon#[27=AT01-04\r\n] 2006.257.02:24:06.25#ibcon#*before write, iclass 7, count 2 2006.257.02:24:06.25#ibcon#enter sib2, iclass 7, count 2 2006.257.02:24:06.25#ibcon#flushed, iclass 7, count 2 2006.257.02:24:06.25#ibcon#about to write, iclass 7, count 2 2006.257.02:24:06.25#ibcon#wrote, iclass 7, count 2 2006.257.02:24:06.25#ibcon#about to read 3, iclass 7, count 2 2006.257.02:24:06.28#ibcon#read 3, iclass 7, count 2 2006.257.02:24:06.28#ibcon#about to read 4, iclass 7, count 2 2006.257.02:24:06.28#ibcon#read 4, iclass 7, count 2 2006.257.02:24:06.28#ibcon#about to read 5, iclass 7, count 2 2006.257.02:24:06.28#ibcon#read 5, iclass 7, count 2 2006.257.02:24:06.28#ibcon#about to read 6, iclass 7, count 2 2006.257.02:24:06.28#ibcon#read 6, iclass 7, count 2 2006.257.02:24:06.28#ibcon#end of sib2, iclass 7, count 2 2006.257.02:24:06.28#ibcon#*after write, iclass 7, count 2 2006.257.02:24:06.28#ibcon#*before return 0, iclass 7, count 2 2006.257.02:24:06.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:24:06.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:24:06.28#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.02:24:06.28#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:06.28#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:24:06.40#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:24:06.40#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:24:06.40#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:24:06.40#ibcon#first serial, iclass 7, count 0 2006.257.02:24:06.40#ibcon#enter sib2, iclass 7, count 0 2006.257.02:24:06.40#ibcon#flushed, iclass 7, count 0 2006.257.02:24:06.40#ibcon#about to write, iclass 7, count 0 2006.257.02:24:06.40#ibcon#wrote, iclass 7, count 0 2006.257.02:24:06.40#ibcon#about to read 3, iclass 7, count 0 2006.257.02:24:06.42#ibcon#read 3, iclass 7, count 0 2006.257.02:24:06.42#ibcon#about to read 4, iclass 7, count 0 2006.257.02:24:06.42#ibcon#read 4, iclass 7, count 0 2006.257.02:24:06.42#ibcon#about to read 5, iclass 7, count 0 2006.257.02:24:06.42#ibcon#read 5, iclass 7, count 0 2006.257.02:24:06.42#ibcon#about to read 6, iclass 7, count 0 2006.257.02:24:06.42#ibcon#read 6, iclass 7, count 0 2006.257.02:24:06.42#ibcon#end of sib2, iclass 7, count 0 2006.257.02:24:06.42#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:24:06.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:24:06.42#ibcon#[27=USB\r\n] 2006.257.02:24:06.42#ibcon#*before write, iclass 7, count 0 2006.257.02:24:06.42#ibcon#enter sib2, iclass 7, count 0 2006.257.02:24:06.42#ibcon#flushed, iclass 7, count 0 2006.257.02:24:06.42#ibcon#about to write, iclass 7, count 0 2006.257.02:24:06.42#ibcon#wrote, iclass 7, count 0 2006.257.02:24:06.42#ibcon#about to read 3, iclass 7, count 0 2006.257.02:24:06.45#ibcon#read 3, iclass 7, count 0 2006.257.02:24:06.45#ibcon#about to read 4, iclass 7, count 0 2006.257.02:24:06.45#ibcon#read 4, iclass 7, count 0 2006.257.02:24:06.45#ibcon#about to read 5, iclass 7, count 0 2006.257.02:24:06.45#ibcon#read 5, iclass 7, count 0 2006.257.02:24:06.45#ibcon#about to read 6, iclass 7, count 0 2006.257.02:24:06.45#ibcon#read 6, iclass 7, count 0 2006.257.02:24:06.45#ibcon#end of sib2, iclass 7, count 0 2006.257.02:24:06.45#ibcon#*after write, iclass 7, count 0 2006.257.02:24:06.45#ibcon#*before return 0, iclass 7, count 0 2006.257.02:24:06.45#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:24:06.45#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:24:06.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:24:06.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:24:06.45$vck44/vblo=2,634.99 2006.257.02:24:06.45#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.02:24:06.45#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.02:24:06.45#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:06.45#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:06.45#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:06.45#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:06.45#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:24:06.45#ibcon#first serial, iclass 11, count 0 2006.257.02:24:06.45#ibcon#enter sib2, iclass 11, count 0 2006.257.02:24:06.45#ibcon#flushed, iclass 11, count 0 2006.257.02:24:06.45#ibcon#about to write, iclass 11, count 0 2006.257.02:24:06.45#ibcon#wrote, iclass 11, count 0 2006.257.02:24:06.45#ibcon#about to read 3, iclass 11, count 0 2006.257.02:24:06.47#ibcon#read 3, iclass 11, count 0 2006.257.02:24:06.47#ibcon#about to read 4, iclass 11, count 0 2006.257.02:24:06.47#ibcon#read 4, iclass 11, count 0 2006.257.02:24:06.47#ibcon#about to read 5, iclass 11, count 0 2006.257.02:24:06.47#ibcon#read 5, iclass 11, count 0 2006.257.02:24:06.47#ibcon#about to read 6, iclass 11, count 0 2006.257.02:24:06.47#ibcon#read 6, iclass 11, count 0 2006.257.02:24:06.47#ibcon#end of sib2, iclass 11, count 0 2006.257.02:24:06.47#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:24:06.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:24:06.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:24:06.47#ibcon#*before write, iclass 11, count 0 2006.257.02:24:06.47#ibcon#enter sib2, iclass 11, count 0 2006.257.02:24:06.47#ibcon#flushed, iclass 11, count 0 2006.257.02:24:06.47#ibcon#about to write, iclass 11, count 0 2006.257.02:24:06.47#ibcon#wrote, iclass 11, count 0 2006.257.02:24:06.47#ibcon#about to read 3, iclass 11, count 0 2006.257.02:24:06.51#ibcon#read 3, iclass 11, count 0 2006.257.02:24:06.51#ibcon#about to read 4, iclass 11, count 0 2006.257.02:24:06.51#ibcon#read 4, iclass 11, count 0 2006.257.02:24:06.51#ibcon#about to read 5, iclass 11, count 0 2006.257.02:24:06.51#ibcon#read 5, iclass 11, count 0 2006.257.02:24:06.51#ibcon#about to read 6, iclass 11, count 0 2006.257.02:24:06.51#ibcon#read 6, iclass 11, count 0 2006.257.02:24:06.51#ibcon#end of sib2, iclass 11, count 0 2006.257.02:24:06.51#ibcon#*after write, iclass 11, count 0 2006.257.02:24:06.51#ibcon#*before return 0, iclass 11, count 0 2006.257.02:24:06.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:06.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:24:06.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:24:06.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:24:06.51$vck44/vb=2,5 2006.257.02:24:06.51#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.02:24:06.51#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.02:24:06.51#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:06.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:06.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:06.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:06.57#ibcon#enter wrdev, iclass 13, count 2 2006.257.02:24:06.57#ibcon#first serial, iclass 13, count 2 2006.257.02:24:06.57#ibcon#enter sib2, iclass 13, count 2 2006.257.02:24:06.57#ibcon#flushed, iclass 13, count 2 2006.257.02:24:06.57#ibcon#about to write, iclass 13, count 2 2006.257.02:24:06.57#ibcon#wrote, iclass 13, count 2 2006.257.02:24:06.57#ibcon#about to read 3, iclass 13, count 2 2006.257.02:24:06.59#ibcon#read 3, iclass 13, count 2 2006.257.02:24:06.59#ibcon#about to read 4, iclass 13, count 2 2006.257.02:24:06.59#ibcon#read 4, iclass 13, count 2 2006.257.02:24:06.59#ibcon#about to read 5, iclass 13, count 2 2006.257.02:24:06.59#ibcon#read 5, iclass 13, count 2 2006.257.02:24:06.59#ibcon#about to read 6, iclass 13, count 2 2006.257.02:24:06.59#ibcon#read 6, iclass 13, count 2 2006.257.02:24:06.59#ibcon#end of sib2, iclass 13, count 2 2006.257.02:24:06.59#ibcon#*mode == 0, iclass 13, count 2 2006.257.02:24:06.59#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.02:24:06.59#ibcon#[27=AT02-05\r\n] 2006.257.02:24:06.59#ibcon#*before write, iclass 13, count 2 2006.257.02:24:06.59#ibcon#enter sib2, iclass 13, count 2 2006.257.02:24:06.59#ibcon#flushed, iclass 13, count 2 2006.257.02:24:06.59#ibcon#about to write, iclass 13, count 2 2006.257.02:24:06.59#ibcon#wrote, iclass 13, count 2 2006.257.02:24:06.59#ibcon#about to read 3, iclass 13, count 2 2006.257.02:24:06.62#ibcon#read 3, iclass 13, count 2 2006.257.02:24:06.62#ibcon#about to read 4, iclass 13, count 2 2006.257.02:24:06.62#ibcon#read 4, iclass 13, count 2 2006.257.02:24:06.62#ibcon#about to read 5, iclass 13, count 2 2006.257.02:24:06.62#ibcon#read 5, iclass 13, count 2 2006.257.02:24:06.62#ibcon#about to read 6, iclass 13, count 2 2006.257.02:24:06.62#ibcon#read 6, iclass 13, count 2 2006.257.02:24:06.62#ibcon#end of sib2, iclass 13, count 2 2006.257.02:24:06.62#ibcon#*after write, iclass 13, count 2 2006.257.02:24:06.62#ibcon#*before return 0, iclass 13, count 2 2006.257.02:24:06.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:06.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:24:06.62#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.02:24:06.62#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:06.62#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:06.74#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:06.74#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:06.74#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:24:06.74#ibcon#first serial, iclass 13, count 0 2006.257.02:24:06.74#ibcon#enter sib2, iclass 13, count 0 2006.257.02:24:06.74#ibcon#flushed, iclass 13, count 0 2006.257.02:24:06.74#ibcon#about to write, iclass 13, count 0 2006.257.02:24:06.74#ibcon#wrote, iclass 13, count 0 2006.257.02:24:06.74#ibcon#about to read 3, iclass 13, count 0 2006.257.02:24:06.76#ibcon#read 3, iclass 13, count 0 2006.257.02:24:06.76#ibcon#about to read 4, iclass 13, count 0 2006.257.02:24:06.76#ibcon#read 4, iclass 13, count 0 2006.257.02:24:06.76#ibcon#about to read 5, iclass 13, count 0 2006.257.02:24:06.76#ibcon#read 5, iclass 13, count 0 2006.257.02:24:06.76#ibcon#about to read 6, iclass 13, count 0 2006.257.02:24:06.76#ibcon#read 6, iclass 13, count 0 2006.257.02:24:06.76#ibcon#end of sib2, iclass 13, count 0 2006.257.02:24:06.76#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:24:06.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:24:06.76#ibcon#[27=USB\r\n] 2006.257.02:24:06.76#ibcon#*before write, iclass 13, count 0 2006.257.02:24:06.76#ibcon#enter sib2, iclass 13, count 0 2006.257.02:24:06.76#ibcon#flushed, iclass 13, count 0 2006.257.02:24:06.76#ibcon#about to write, iclass 13, count 0 2006.257.02:24:06.76#ibcon#wrote, iclass 13, count 0 2006.257.02:24:06.76#ibcon#about to read 3, iclass 13, count 0 2006.257.02:24:06.79#ibcon#read 3, iclass 13, count 0 2006.257.02:24:06.79#ibcon#about to read 4, iclass 13, count 0 2006.257.02:24:06.79#ibcon#read 4, iclass 13, count 0 2006.257.02:24:06.79#ibcon#about to read 5, iclass 13, count 0 2006.257.02:24:06.79#ibcon#read 5, iclass 13, count 0 2006.257.02:24:06.79#ibcon#about to read 6, iclass 13, count 0 2006.257.02:24:06.79#ibcon#read 6, iclass 13, count 0 2006.257.02:24:06.79#ibcon#end of sib2, iclass 13, count 0 2006.257.02:24:06.79#ibcon#*after write, iclass 13, count 0 2006.257.02:24:06.79#ibcon#*before return 0, iclass 13, count 0 2006.257.02:24:06.79#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:06.79#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:24:06.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:24:06.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:24:06.79$vck44/vblo=3,649.99 2006.257.02:24:06.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.02:24:06.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.02:24:06.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:06.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:06.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:06.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:06.79#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:24:06.79#ibcon#first serial, iclass 15, count 0 2006.257.02:24:06.79#ibcon#enter sib2, iclass 15, count 0 2006.257.02:24:06.79#ibcon#flushed, iclass 15, count 0 2006.257.02:24:06.79#ibcon#about to write, iclass 15, count 0 2006.257.02:24:06.79#ibcon#wrote, iclass 15, count 0 2006.257.02:24:06.79#ibcon#about to read 3, iclass 15, count 0 2006.257.02:24:06.81#ibcon#read 3, iclass 15, count 0 2006.257.02:24:06.81#ibcon#about to read 4, iclass 15, count 0 2006.257.02:24:06.81#ibcon#read 4, iclass 15, count 0 2006.257.02:24:06.81#ibcon#about to read 5, iclass 15, count 0 2006.257.02:24:06.81#ibcon#read 5, iclass 15, count 0 2006.257.02:24:06.81#ibcon#about to read 6, iclass 15, count 0 2006.257.02:24:06.81#ibcon#read 6, iclass 15, count 0 2006.257.02:24:06.81#ibcon#end of sib2, iclass 15, count 0 2006.257.02:24:06.81#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:24:06.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:24:06.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:24:06.81#ibcon#*before write, iclass 15, count 0 2006.257.02:24:06.81#ibcon#enter sib2, iclass 15, count 0 2006.257.02:24:06.81#ibcon#flushed, iclass 15, count 0 2006.257.02:24:06.81#ibcon#about to write, iclass 15, count 0 2006.257.02:24:06.81#ibcon#wrote, iclass 15, count 0 2006.257.02:24:06.81#ibcon#about to read 3, iclass 15, count 0 2006.257.02:24:06.85#ibcon#read 3, iclass 15, count 0 2006.257.02:24:06.85#ibcon#about to read 4, iclass 15, count 0 2006.257.02:24:06.85#ibcon#read 4, iclass 15, count 0 2006.257.02:24:06.85#ibcon#about to read 5, iclass 15, count 0 2006.257.02:24:06.85#ibcon#read 5, iclass 15, count 0 2006.257.02:24:06.85#ibcon#about to read 6, iclass 15, count 0 2006.257.02:24:06.85#ibcon#read 6, iclass 15, count 0 2006.257.02:24:06.85#ibcon#end of sib2, iclass 15, count 0 2006.257.02:24:06.85#ibcon#*after write, iclass 15, count 0 2006.257.02:24:06.85#ibcon#*before return 0, iclass 15, count 0 2006.257.02:24:06.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:06.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:24:06.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:24:06.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:24:06.85$vck44/vb=3,4 2006.257.02:24:06.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.02:24:06.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.02:24:06.85#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:06.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:06.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:06.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:06.91#ibcon#enter wrdev, iclass 17, count 2 2006.257.02:24:06.91#ibcon#first serial, iclass 17, count 2 2006.257.02:24:06.91#ibcon#enter sib2, iclass 17, count 2 2006.257.02:24:06.91#ibcon#flushed, iclass 17, count 2 2006.257.02:24:06.91#ibcon#about to write, iclass 17, count 2 2006.257.02:24:06.91#ibcon#wrote, iclass 17, count 2 2006.257.02:24:06.91#ibcon#about to read 3, iclass 17, count 2 2006.257.02:24:06.93#ibcon#read 3, iclass 17, count 2 2006.257.02:24:06.93#ibcon#about to read 4, iclass 17, count 2 2006.257.02:24:06.93#ibcon#read 4, iclass 17, count 2 2006.257.02:24:06.93#ibcon#about to read 5, iclass 17, count 2 2006.257.02:24:06.93#ibcon#read 5, iclass 17, count 2 2006.257.02:24:06.93#ibcon#about to read 6, iclass 17, count 2 2006.257.02:24:06.93#ibcon#read 6, iclass 17, count 2 2006.257.02:24:06.93#ibcon#end of sib2, iclass 17, count 2 2006.257.02:24:06.93#ibcon#*mode == 0, iclass 17, count 2 2006.257.02:24:06.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.02:24:06.93#ibcon#[27=AT03-04\r\n] 2006.257.02:24:06.93#ibcon#*before write, iclass 17, count 2 2006.257.02:24:06.93#ibcon#enter sib2, iclass 17, count 2 2006.257.02:24:06.93#ibcon#flushed, iclass 17, count 2 2006.257.02:24:06.93#ibcon#about to write, iclass 17, count 2 2006.257.02:24:06.93#ibcon#wrote, iclass 17, count 2 2006.257.02:24:06.93#ibcon#about to read 3, iclass 17, count 2 2006.257.02:24:06.96#ibcon#read 3, iclass 17, count 2 2006.257.02:24:06.96#ibcon#about to read 4, iclass 17, count 2 2006.257.02:24:06.96#ibcon#read 4, iclass 17, count 2 2006.257.02:24:06.96#ibcon#about to read 5, iclass 17, count 2 2006.257.02:24:06.96#ibcon#read 5, iclass 17, count 2 2006.257.02:24:06.96#ibcon#about to read 6, iclass 17, count 2 2006.257.02:24:06.96#ibcon#read 6, iclass 17, count 2 2006.257.02:24:06.96#ibcon#end of sib2, iclass 17, count 2 2006.257.02:24:06.96#ibcon#*after write, iclass 17, count 2 2006.257.02:24:06.96#ibcon#*before return 0, iclass 17, count 2 2006.257.02:24:06.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:06.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:24:06.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.02:24:06.96#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:06.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:07.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:07.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:07.08#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:24:07.08#ibcon#first serial, iclass 17, count 0 2006.257.02:24:07.08#ibcon#enter sib2, iclass 17, count 0 2006.257.02:24:07.08#ibcon#flushed, iclass 17, count 0 2006.257.02:24:07.08#ibcon#about to write, iclass 17, count 0 2006.257.02:24:07.08#ibcon#wrote, iclass 17, count 0 2006.257.02:24:07.08#ibcon#about to read 3, iclass 17, count 0 2006.257.02:24:07.10#ibcon#read 3, iclass 17, count 0 2006.257.02:24:07.10#ibcon#about to read 4, iclass 17, count 0 2006.257.02:24:07.10#ibcon#read 4, iclass 17, count 0 2006.257.02:24:07.10#ibcon#about to read 5, iclass 17, count 0 2006.257.02:24:07.10#ibcon#read 5, iclass 17, count 0 2006.257.02:24:07.10#ibcon#about to read 6, iclass 17, count 0 2006.257.02:24:07.10#ibcon#read 6, iclass 17, count 0 2006.257.02:24:07.10#ibcon#end of sib2, iclass 17, count 0 2006.257.02:24:07.10#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:24:07.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:24:07.10#ibcon#[27=USB\r\n] 2006.257.02:24:07.10#ibcon#*before write, iclass 17, count 0 2006.257.02:24:07.10#ibcon#enter sib2, iclass 17, count 0 2006.257.02:24:07.10#ibcon#flushed, iclass 17, count 0 2006.257.02:24:07.10#ibcon#about to write, iclass 17, count 0 2006.257.02:24:07.10#ibcon#wrote, iclass 17, count 0 2006.257.02:24:07.10#ibcon#about to read 3, iclass 17, count 0 2006.257.02:24:07.13#ibcon#read 3, iclass 17, count 0 2006.257.02:24:07.13#ibcon#about to read 4, iclass 17, count 0 2006.257.02:24:07.13#ibcon#read 4, iclass 17, count 0 2006.257.02:24:07.13#ibcon#about to read 5, iclass 17, count 0 2006.257.02:24:07.13#ibcon#read 5, iclass 17, count 0 2006.257.02:24:07.13#ibcon#about to read 6, iclass 17, count 0 2006.257.02:24:07.13#ibcon#read 6, iclass 17, count 0 2006.257.02:24:07.13#ibcon#end of sib2, iclass 17, count 0 2006.257.02:24:07.13#ibcon#*after write, iclass 17, count 0 2006.257.02:24:07.13#ibcon#*before return 0, iclass 17, count 0 2006.257.02:24:07.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:07.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:24:07.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:24:07.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:24:07.13$vck44/vblo=4,679.99 2006.257.02:24:07.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.02:24:07.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.02:24:07.13#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:07.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:07.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:07.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:07.13#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:24:07.13#ibcon#first serial, iclass 19, count 0 2006.257.02:24:07.13#ibcon#enter sib2, iclass 19, count 0 2006.257.02:24:07.13#ibcon#flushed, iclass 19, count 0 2006.257.02:24:07.13#ibcon#about to write, iclass 19, count 0 2006.257.02:24:07.13#ibcon#wrote, iclass 19, count 0 2006.257.02:24:07.13#ibcon#about to read 3, iclass 19, count 0 2006.257.02:24:07.15#ibcon#read 3, iclass 19, count 0 2006.257.02:24:07.15#ibcon#about to read 4, iclass 19, count 0 2006.257.02:24:07.15#ibcon#read 4, iclass 19, count 0 2006.257.02:24:07.15#ibcon#about to read 5, iclass 19, count 0 2006.257.02:24:07.15#ibcon#read 5, iclass 19, count 0 2006.257.02:24:07.15#ibcon#about to read 6, iclass 19, count 0 2006.257.02:24:07.15#ibcon#read 6, iclass 19, count 0 2006.257.02:24:07.15#ibcon#end of sib2, iclass 19, count 0 2006.257.02:24:07.15#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:24:07.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:24:07.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:24:07.15#ibcon#*before write, iclass 19, count 0 2006.257.02:24:07.15#ibcon#enter sib2, iclass 19, count 0 2006.257.02:24:07.15#ibcon#flushed, iclass 19, count 0 2006.257.02:24:07.15#ibcon#about to write, iclass 19, count 0 2006.257.02:24:07.15#ibcon#wrote, iclass 19, count 0 2006.257.02:24:07.15#ibcon#about to read 3, iclass 19, count 0 2006.257.02:24:07.19#ibcon#read 3, iclass 19, count 0 2006.257.02:24:07.19#ibcon#about to read 4, iclass 19, count 0 2006.257.02:24:07.19#ibcon#read 4, iclass 19, count 0 2006.257.02:24:07.19#ibcon#about to read 5, iclass 19, count 0 2006.257.02:24:07.19#ibcon#read 5, iclass 19, count 0 2006.257.02:24:07.19#ibcon#about to read 6, iclass 19, count 0 2006.257.02:24:07.19#ibcon#read 6, iclass 19, count 0 2006.257.02:24:07.19#ibcon#end of sib2, iclass 19, count 0 2006.257.02:24:07.19#ibcon#*after write, iclass 19, count 0 2006.257.02:24:07.19#ibcon#*before return 0, iclass 19, count 0 2006.257.02:24:07.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:07.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:24:07.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:24:07.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:24:07.19$vck44/vb=4,5 2006.257.02:24:07.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.02:24:07.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.02:24:07.19#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:07.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:07.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:07.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:07.25#ibcon#enter wrdev, iclass 21, count 2 2006.257.02:24:07.25#ibcon#first serial, iclass 21, count 2 2006.257.02:24:07.25#ibcon#enter sib2, iclass 21, count 2 2006.257.02:24:07.25#ibcon#flushed, iclass 21, count 2 2006.257.02:24:07.25#ibcon#about to write, iclass 21, count 2 2006.257.02:24:07.25#ibcon#wrote, iclass 21, count 2 2006.257.02:24:07.25#ibcon#about to read 3, iclass 21, count 2 2006.257.02:24:07.27#ibcon#read 3, iclass 21, count 2 2006.257.02:24:07.27#ibcon#about to read 4, iclass 21, count 2 2006.257.02:24:07.27#ibcon#read 4, iclass 21, count 2 2006.257.02:24:07.27#ibcon#about to read 5, iclass 21, count 2 2006.257.02:24:07.27#ibcon#read 5, iclass 21, count 2 2006.257.02:24:07.27#ibcon#about to read 6, iclass 21, count 2 2006.257.02:24:07.27#ibcon#read 6, iclass 21, count 2 2006.257.02:24:07.27#ibcon#end of sib2, iclass 21, count 2 2006.257.02:24:07.27#ibcon#*mode == 0, iclass 21, count 2 2006.257.02:24:07.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.02:24:07.27#ibcon#[27=AT04-05\r\n] 2006.257.02:24:07.27#ibcon#*before write, iclass 21, count 2 2006.257.02:24:07.27#ibcon#enter sib2, iclass 21, count 2 2006.257.02:24:07.27#ibcon#flushed, iclass 21, count 2 2006.257.02:24:07.27#ibcon#about to write, iclass 21, count 2 2006.257.02:24:07.27#ibcon#wrote, iclass 21, count 2 2006.257.02:24:07.27#ibcon#about to read 3, iclass 21, count 2 2006.257.02:24:07.30#ibcon#read 3, iclass 21, count 2 2006.257.02:24:07.30#ibcon#about to read 4, iclass 21, count 2 2006.257.02:24:07.30#ibcon#read 4, iclass 21, count 2 2006.257.02:24:07.30#ibcon#about to read 5, iclass 21, count 2 2006.257.02:24:07.30#ibcon#read 5, iclass 21, count 2 2006.257.02:24:07.30#ibcon#about to read 6, iclass 21, count 2 2006.257.02:24:07.30#ibcon#read 6, iclass 21, count 2 2006.257.02:24:07.30#ibcon#end of sib2, iclass 21, count 2 2006.257.02:24:07.30#ibcon#*after write, iclass 21, count 2 2006.257.02:24:07.30#ibcon#*before return 0, iclass 21, count 2 2006.257.02:24:07.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:07.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:24:07.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.02:24:07.30#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:07.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:07.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:07.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:07.42#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:24:07.42#ibcon#first serial, iclass 21, count 0 2006.257.02:24:07.42#ibcon#enter sib2, iclass 21, count 0 2006.257.02:24:07.42#ibcon#flushed, iclass 21, count 0 2006.257.02:24:07.42#ibcon#about to write, iclass 21, count 0 2006.257.02:24:07.42#ibcon#wrote, iclass 21, count 0 2006.257.02:24:07.42#ibcon#about to read 3, iclass 21, count 0 2006.257.02:24:07.44#ibcon#read 3, iclass 21, count 0 2006.257.02:24:07.44#ibcon#about to read 4, iclass 21, count 0 2006.257.02:24:07.44#ibcon#read 4, iclass 21, count 0 2006.257.02:24:07.44#ibcon#about to read 5, iclass 21, count 0 2006.257.02:24:07.44#ibcon#read 5, iclass 21, count 0 2006.257.02:24:07.44#ibcon#about to read 6, iclass 21, count 0 2006.257.02:24:07.44#ibcon#read 6, iclass 21, count 0 2006.257.02:24:07.44#ibcon#end of sib2, iclass 21, count 0 2006.257.02:24:07.44#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:24:07.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:24:07.44#ibcon#[27=USB\r\n] 2006.257.02:24:07.44#ibcon#*before write, iclass 21, count 0 2006.257.02:24:07.44#ibcon#enter sib2, iclass 21, count 0 2006.257.02:24:07.44#ibcon#flushed, iclass 21, count 0 2006.257.02:24:07.44#ibcon#about to write, iclass 21, count 0 2006.257.02:24:07.44#ibcon#wrote, iclass 21, count 0 2006.257.02:24:07.44#ibcon#about to read 3, iclass 21, count 0 2006.257.02:24:07.47#ibcon#read 3, iclass 21, count 0 2006.257.02:24:07.47#ibcon#about to read 4, iclass 21, count 0 2006.257.02:24:07.47#ibcon#read 4, iclass 21, count 0 2006.257.02:24:07.47#ibcon#about to read 5, iclass 21, count 0 2006.257.02:24:07.47#ibcon#read 5, iclass 21, count 0 2006.257.02:24:07.47#ibcon#about to read 6, iclass 21, count 0 2006.257.02:24:07.47#ibcon#read 6, iclass 21, count 0 2006.257.02:24:07.47#ibcon#end of sib2, iclass 21, count 0 2006.257.02:24:07.47#ibcon#*after write, iclass 21, count 0 2006.257.02:24:07.47#ibcon#*before return 0, iclass 21, count 0 2006.257.02:24:07.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:07.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:24:07.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:24:07.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:24:07.47$vck44/vblo=5,709.99 2006.257.02:24:07.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.02:24:07.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.02:24:07.47#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:07.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:07.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:07.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:07.47#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:24:07.47#ibcon#first serial, iclass 23, count 0 2006.257.02:24:07.47#ibcon#enter sib2, iclass 23, count 0 2006.257.02:24:07.47#ibcon#flushed, iclass 23, count 0 2006.257.02:24:07.47#ibcon#about to write, iclass 23, count 0 2006.257.02:24:07.47#ibcon#wrote, iclass 23, count 0 2006.257.02:24:07.47#ibcon#about to read 3, iclass 23, count 0 2006.257.02:24:07.49#ibcon#read 3, iclass 23, count 0 2006.257.02:24:07.49#ibcon#about to read 4, iclass 23, count 0 2006.257.02:24:07.49#ibcon#read 4, iclass 23, count 0 2006.257.02:24:07.49#ibcon#about to read 5, iclass 23, count 0 2006.257.02:24:07.49#ibcon#read 5, iclass 23, count 0 2006.257.02:24:07.49#ibcon#about to read 6, iclass 23, count 0 2006.257.02:24:07.49#ibcon#read 6, iclass 23, count 0 2006.257.02:24:07.49#ibcon#end of sib2, iclass 23, count 0 2006.257.02:24:07.49#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:24:07.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:24:07.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:24:07.49#ibcon#*before write, iclass 23, count 0 2006.257.02:24:07.49#ibcon#enter sib2, iclass 23, count 0 2006.257.02:24:07.49#ibcon#flushed, iclass 23, count 0 2006.257.02:24:07.49#ibcon#about to write, iclass 23, count 0 2006.257.02:24:07.49#ibcon#wrote, iclass 23, count 0 2006.257.02:24:07.49#ibcon#about to read 3, iclass 23, count 0 2006.257.02:24:07.53#ibcon#read 3, iclass 23, count 0 2006.257.02:24:07.53#ibcon#about to read 4, iclass 23, count 0 2006.257.02:24:07.53#ibcon#read 4, iclass 23, count 0 2006.257.02:24:07.53#ibcon#about to read 5, iclass 23, count 0 2006.257.02:24:07.53#ibcon#read 5, iclass 23, count 0 2006.257.02:24:07.53#ibcon#about to read 6, iclass 23, count 0 2006.257.02:24:07.53#ibcon#read 6, iclass 23, count 0 2006.257.02:24:07.53#ibcon#end of sib2, iclass 23, count 0 2006.257.02:24:07.53#ibcon#*after write, iclass 23, count 0 2006.257.02:24:07.53#ibcon#*before return 0, iclass 23, count 0 2006.257.02:24:07.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:07.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:24:07.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:24:07.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:24:07.53$vck44/vb=5,4 2006.257.02:24:07.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.02:24:07.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.02:24:07.53#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:07.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:07.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:07.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:07.59#ibcon#enter wrdev, iclass 25, count 2 2006.257.02:24:07.59#ibcon#first serial, iclass 25, count 2 2006.257.02:24:07.59#ibcon#enter sib2, iclass 25, count 2 2006.257.02:24:07.59#ibcon#flushed, iclass 25, count 2 2006.257.02:24:07.59#ibcon#about to write, iclass 25, count 2 2006.257.02:24:07.59#ibcon#wrote, iclass 25, count 2 2006.257.02:24:07.59#ibcon#about to read 3, iclass 25, count 2 2006.257.02:24:07.61#ibcon#read 3, iclass 25, count 2 2006.257.02:24:07.61#ibcon#about to read 4, iclass 25, count 2 2006.257.02:24:07.61#ibcon#read 4, iclass 25, count 2 2006.257.02:24:07.61#ibcon#about to read 5, iclass 25, count 2 2006.257.02:24:07.61#ibcon#read 5, iclass 25, count 2 2006.257.02:24:07.61#ibcon#about to read 6, iclass 25, count 2 2006.257.02:24:07.61#ibcon#read 6, iclass 25, count 2 2006.257.02:24:07.61#ibcon#end of sib2, iclass 25, count 2 2006.257.02:24:07.61#ibcon#*mode == 0, iclass 25, count 2 2006.257.02:24:07.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.02:24:07.61#ibcon#[27=AT05-04\r\n] 2006.257.02:24:07.61#ibcon#*before write, iclass 25, count 2 2006.257.02:24:07.61#ibcon#enter sib2, iclass 25, count 2 2006.257.02:24:07.61#ibcon#flushed, iclass 25, count 2 2006.257.02:24:07.61#ibcon#about to write, iclass 25, count 2 2006.257.02:24:07.61#ibcon#wrote, iclass 25, count 2 2006.257.02:24:07.61#ibcon#about to read 3, iclass 25, count 2 2006.257.02:24:07.64#ibcon#read 3, iclass 25, count 2 2006.257.02:24:07.64#ibcon#about to read 4, iclass 25, count 2 2006.257.02:24:07.64#ibcon#read 4, iclass 25, count 2 2006.257.02:24:07.64#ibcon#about to read 5, iclass 25, count 2 2006.257.02:24:07.64#ibcon#read 5, iclass 25, count 2 2006.257.02:24:07.64#ibcon#about to read 6, iclass 25, count 2 2006.257.02:24:07.64#ibcon#read 6, iclass 25, count 2 2006.257.02:24:07.64#ibcon#end of sib2, iclass 25, count 2 2006.257.02:24:07.64#ibcon#*after write, iclass 25, count 2 2006.257.02:24:07.64#ibcon#*before return 0, iclass 25, count 2 2006.257.02:24:07.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:07.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:24:07.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.02:24:07.64#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:07.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:07.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:07.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:07.76#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:24:07.76#ibcon#first serial, iclass 25, count 0 2006.257.02:24:07.76#ibcon#enter sib2, iclass 25, count 0 2006.257.02:24:07.76#ibcon#flushed, iclass 25, count 0 2006.257.02:24:07.76#ibcon#about to write, iclass 25, count 0 2006.257.02:24:07.76#ibcon#wrote, iclass 25, count 0 2006.257.02:24:07.76#ibcon#about to read 3, iclass 25, count 0 2006.257.02:24:07.78#ibcon#read 3, iclass 25, count 0 2006.257.02:24:07.78#ibcon#about to read 4, iclass 25, count 0 2006.257.02:24:07.78#ibcon#read 4, iclass 25, count 0 2006.257.02:24:07.78#ibcon#about to read 5, iclass 25, count 0 2006.257.02:24:07.78#ibcon#read 5, iclass 25, count 0 2006.257.02:24:07.78#ibcon#about to read 6, iclass 25, count 0 2006.257.02:24:07.78#ibcon#read 6, iclass 25, count 0 2006.257.02:24:07.78#ibcon#end of sib2, iclass 25, count 0 2006.257.02:24:07.78#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:24:07.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:24:07.78#ibcon#[27=USB\r\n] 2006.257.02:24:07.78#ibcon#*before write, iclass 25, count 0 2006.257.02:24:07.78#ibcon#enter sib2, iclass 25, count 0 2006.257.02:24:07.78#ibcon#flushed, iclass 25, count 0 2006.257.02:24:07.78#ibcon#about to write, iclass 25, count 0 2006.257.02:24:07.78#ibcon#wrote, iclass 25, count 0 2006.257.02:24:07.78#ibcon#about to read 3, iclass 25, count 0 2006.257.02:24:07.81#ibcon#read 3, iclass 25, count 0 2006.257.02:24:07.81#ibcon#about to read 4, iclass 25, count 0 2006.257.02:24:07.81#ibcon#read 4, iclass 25, count 0 2006.257.02:24:07.81#ibcon#about to read 5, iclass 25, count 0 2006.257.02:24:07.81#ibcon#read 5, iclass 25, count 0 2006.257.02:24:07.81#ibcon#about to read 6, iclass 25, count 0 2006.257.02:24:07.81#ibcon#read 6, iclass 25, count 0 2006.257.02:24:07.81#ibcon#end of sib2, iclass 25, count 0 2006.257.02:24:07.81#ibcon#*after write, iclass 25, count 0 2006.257.02:24:07.81#ibcon#*before return 0, iclass 25, count 0 2006.257.02:24:07.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:07.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:24:07.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:24:07.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:24:07.81$vck44/vblo=6,719.99 2006.257.02:24:07.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.02:24:07.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.02:24:07.81#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:07.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:07.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:07.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:07.81#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:24:07.81#ibcon#first serial, iclass 27, count 0 2006.257.02:24:07.81#ibcon#enter sib2, iclass 27, count 0 2006.257.02:24:07.81#ibcon#flushed, iclass 27, count 0 2006.257.02:24:07.81#ibcon#about to write, iclass 27, count 0 2006.257.02:24:07.81#ibcon#wrote, iclass 27, count 0 2006.257.02:24:07.81#ibcon#about to read 3, iclass 27, count 0 2006.257.02:24:07.83#ibcon#read 3, iclass 27, count 0 2006.257.02:24:07.83#ibcon#about to read 4, iclass 27, count 0 2006.257.02:24:07.83#ibcon#read 4, iclass 27, count 0 2006.257.02:24:07.83#ibcon#about to read 5, iclass 27, count 0 2006.257.02:24:07.83#ibcon#read 5, iclass 27, count 0 2006.257.02:24:07.83#ibcon#about to read 6, iclass 27, count 0 2006.257.02:24:07.83#ibcon#read 6, iclass 27, count 0 2006.257.02:24:07.83#ibcon#end of sib2, iclass 27, count 0 2006.257.02:24:07.83#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:24:07.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:24:07.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:24:07.83#ibcon#*before write, iclass 27, count 0 2006.257.02:24:07.83#ibcon#enter sib2, iclass 27, count 0 2006.257.02:24:07.83#ibcon#flushed, iclass 27, count 0 2006.257.02:24:07.83#ibcon#about to write, iclass 27, count 0 2006.257.02:24:07.83#ibcon#wrote, iclass 27, count 0 2006.257.02:24:07.83#ibcon#about to read 3, iclass 27, count 0 2006.257.02:24:07.87#ibcon#read 3, iclass 27, count 0 2006.257.02:24:07.87#ibcon#about to read 4, iclass 27, count 0 2006.257.02:24:07.87#ibcon#read 4, iclass 27, count 0 2006.257.02:24:07.87#ibcon#about to read 5, iclass 27, count 0 2006.257.02:24:07.87#ibcon#read 5, iclass 27, count 0 2006.257.02:24:07.87#ibcon#about to read 6, iclass 27, count 0 2006.257.02:24:07.87#ibcon#read 6, iclass 27, count 0 2006.257.02:24:07.87#ibcon#end of sib2, iclass 27, count 0 2006.257.02:24:07.87#ibcon#*after write, iclass 27, count 0 2006.257.02:24:07.87#ibcon#*before return 0, iclass 27, count 0 2006.257.02:24:07.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:07.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:24:07.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:24:07.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:24:07.87$vck44/vb=6,4 2006.257.02:24:07.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.02:24:07.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.02:24:07.87#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:07.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:07.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:07.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:07.93#ibcon#enter wrdev, iclass 29, count 2 2006.257.02:24:07.93#ibcon#first serial, iclass 29, count 2 2006.257.02:24:07.93#ibcon#enter sib2, iclass 29, count 2 2006.257.02:24:07.93#ibcon#flushed, iclass 29, count 2 2006.257.02:24:07.93#ibcon#about to write, iclass 29, count 2 2006.257.02:24:07.93#ibcon#wrote, iclass 29, count 2 2006.257.02:24:07.93#ibcon#about to read 3, iclass 29, count 2 2006.257.02:24:07.95#ibcon#read 3, iclass 29, count 2 2006.257.02:24:07.95#ibcon#about to read 4, iclass 29, count 2 2006.257.02:24:07.95#ibcon#read 4, iclass 29, count 2 2006.257.02:24:07.95#ibcon#about to read 5, iclass 29, count 2 2006.257.02:24:07.95#ibcon#read 5, iclass 29, count 2 2006.257.02:24:07.95#ibcon#about to read 6, iclass 29, count 2 2006.257.02:24:07.95#ibcon#read 6, iclass 29, count 2 2006.257.02:24:07.95#ibcon#end of sib2, iclass 29, count 2 2006.257.02:24:07.95#ibcon#*mode == 0, iclass 29, count 2 2006.257.02:24:07.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.02:24:07.95#ibcon#[27=AT06-04\r\n] 2006.257.02:24:07.95#ibcon#*before write, iclass 29, count 2 2006.257.02:24:07.95#ibcon#enter sib2, iclass 29, count 2 2006.257.02:24:07.95#ibcon#flushed, iclass 29, count 2 2006.257.02:24:07.95#ibcon#about to write, iclass 29, count 2 2006.257.02:24:07.95#ibcon#wrote, iclass 29, count 2 2006.257.02:24:07.95#ibcon#about to read 3, iclass 29, count 2 2006.257.02:24:07.98#ibcon#read 3, iclass 29, count 2 2006.257.02:24:07.98#ibcon#about to read 4, iclass 29, count 2 2006.257.02:24:07.98#ibcon#read 4, iclass 29, count 2 2006.257.02:24:07.98#ibcon#about to read 5, iclass 29, count 2 2006.257.02:24:07.98#ibcon#read 5, iclass 29, count 2 2006.257.02:24:07.98#ibcon#about to read 6, iclass 29, count 2 2006.257.02:24:07.98#ibcon#read 6, iclass 29, count 2 2006.257.02:24:07.98#ibcon#end of sib2, iclass 29, count 2 2006.257.02:24:07.98#ibcon#*after write, iclass 29, count 2 2006.257.02:24:07.98#ibcon#*before return 0, iclass 29, count 2 2006.257.02:24:07.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:07.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:24:07.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.02:24:07.98#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:07.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:08.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:08.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:08.10#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:24:08.10#ibcon#first serial, iclass 29, count 0 2006.257.02:24:08.10#ibcon#enter sib2, iclass 29, count 0 2006.257.02:24:08.10#ibcon#flushed, iclass 29, count 0 2006.257.02:24:08.10#ibcon#about to write, iclass 29, count 0 2006.257.02:24:08.10#ibcon#wrote, iclass 29, count 0 2006.257.02:24:08.10#ibcon#about to read 3, iclass 29, count 0 2006.257.02:24:08.12#ibcon#read 3, iclass 29, count 0 2006.257.02:24:08.12#ibcon#about to read 4, iclass 29, count 0 2006.257.02:24:08.12#ibcon#read 4, iclass 29, count 0 2006.257.02:24:08.12#ibcon#about to read 5, iclass 29, count 0 2006.257.02:24:08.12#ibcon#read 5, iclass 29, count 0 2006.257.02:24:08.12#ibcon#about to read 6, iclass 29, count 0 2006.257.02:24:08.12#ibcon#read 6, iclass 29, count 0 2006.257.02:24:08.12#ibcon#end of sib2, iclass 29, count 0 2006.257.02:24:08.12#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:24:08.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:24:08.12#ibcon#[27=USB\r\n] 2006.257.02:24:08.12#ibcon#*before write, iclass 29, count 0 2006.257.02:24:08.12#ibcon#enter sib2, iclass 29, count 0 2006.257.02:24:08.12#ibcon#flushed, iclass 29, count 0 2006.257.02:24:08.12#ibcon#about to write, iclass 29, count 0 2006.257.02:24:08.12#ibcon#wrote, iclass 29, count 0 2006.257.02:24:08.12#ibcon#about to read 3, iclass 29, count 0 2006.257.02:24:08.15#ibcon#read 3, iclass 29, count 0 2006.257.02:24:08.15#ibcon#about to read 4, iclass 29, count 0 2006.257.02:24:08.15#ibcon#read 4, iclass 29, count 0 2006.257.02:24:08.15#ibcon#about to read 5, iclass 29, count 0 2006.257.02:24:08.15#ibcon#read 5, iclass 29, count 0 2006.257.02:24:08.15#ibcon#about to read 6, iclass 29, count 0 2006.257.02:24:08.15#ibcon#read 6, iclass 29, count 0 2006.257.02:24:08.15#ibcon#end of sib2, iclass 29, count 0 2006.257.02:24:08.15#ibcon#*after write, iclass 29, count 0 2006.257.02:24:08.15#ibcon#*before return 0, iclass 29, count 0 2006.257.02:24:08.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:08.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:24:08.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:24:08.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:24:08.15$vck44/vblo=7,734.99 2006.257.02:24:08.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.02:24:08.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.02:24:08.15#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:08.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:08.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:08.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:08.15#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:24:08.15#ibcon#first serial, iclass 31, count 0 2006.257.02:24:08.15#ibcon#enter sib2, iclass 31, count 0 2006.257.02:24:08.15#ibcon#flushed, iclass 31, count 0 2006.257.02:24:08.15#ibcon#about to write, iclass 31, count 0 2006.257.02:24:08.15#ibcon#wrote, iclass 31, count 0 2006.257.02:24:08.15#ibcon#about to read 3, iclass 31, count 0 2006.257.02:24:08.17#ibcon#read 3, iclass 31, count 0 2006.257.02:24:08.17#ibcon#about to read 4, iclass 31, count 0 2006.257.02:24:08.17#ibcon#read 4, iclass 31, count 0 2006.257.02:24:08.17#ibcon#about to read 5, iclass 31, count 0 2006.257.02:24:08.17#ibcon#read 5, iclass 31, count 0 2006.257.02:24:08.17#ibcon#about to read 6, iclass 31, count 0 2006.257.02:24:08.17#ibcon#read 6, iclass 31, count 0 2006.257.02:24:08.17#ibcon#end of sib2, iclass 31, count 0 2006.257.02:24:08.17#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:24:08.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:24:08.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:24:08.17#ibcon#*before write, iclass 31, count 0 2006.257.02:24:08.17#ibcon#enter sib2, iclass 31, count 0 2006.257.02:24:08.17#ibcon#flushed, iclass 31, count 0 2006.257.02:24:08.17#ibcon#about to write, iclass 31, count 0 2006.257.02:24:08.17#ibcon#wrote, iclass 31, count 0 2006.257.02:24:08.17#ibcon#about to read 3, iclass 31, count 0 2006.257.02:24:08.21#ibcon#read 3, iclass 31, count 0 2006.257.02:24:08.21#ibcon#about to read 4, iclass 31, count 0 2006.257.02:24:08.21#ibcon#read 4, iclass 31, count 0 2006.257.02:24:08.21#ibcon#about to read 5, iclass 31, count 0 2006.257.02:24:08.21#ibcon#read 5, iclass 31, count 0 2006.257.02:24:08.21#ibcon#about to read 6, iclass 31, count 0 2006.257.02:24:08.21#ibcon#read 6, iclass 31, count 0 2006.257.02:24:08.21#ibcon#end of sib2, iclass 31, count 0 2006.257.02:24:08.21#ibcon#*after write, iclass 31, count 0 2006.257.02:24:08.21#ibcon#*before return 0, iclass 31, count 0 2006.257.02:24:08.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:08.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:24:08.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:24:08.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:24:08.21$vck44/vb=7,4 2006.257.02:24:08.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.02:24:08.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.02:24:08.21#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:08.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:08.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:08.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:08.27#ibcon#enter wrdev, iclass 33, count 2 2006.257.02:24:08.27#ibcon#first serial, iclass 33, count 2 2006.257.02:24:08.27#ibcon#enter sib2, iclass 33, count 2 2006.257.02:24:08.27#ibcon#flushed, iclass 33, count 2 2006.257.02:24:08.27#ibcon#about to write, iclass 33, count 2 2006.257.02:24:08.27#ibcon#wrote, iclass 33, count 2 2006.257.02:24:08.27#ibcon#about to read 3, iclass 33, count 2 2006.257.02:24:08.29#ibcon#read 3, iclass 33, count 2 2006.257.02:24:08.29#ibcon#about to read 4, iclass 33, count 2 2006.257.02:24:08.29#ibcon#read 4, iclass 33, count 2 2006.257.02:24:08.29#ibcon#about to read 5, iclass 33, count 2 2006.257.02:24:08.29#ibcon#read 5, iclass 33, count 2 2006.257.02:24:08.29#ibcon#about to read 6, iclass 33, count 2 2006.257.02:24:08.29#ibcon#read 6, iclass 33, count 2 2006.257.02:24:08.29#ibcon#end of sib2, iclass 33, count 2 2006.257.02:24:08.29#ibcon#*mode == 0, iclass 33, count 2 2006.257.02:24:08.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.02:24:08.29#ibcon#[27=AT07-04\r\n] 2006.257.02:24:08.29#ibcon#*before write, iclass 33, count 2 2006.257.02:24:08.29#ibcon#enter sib2, iclass 33, count 2 2006.257.02:24:08.29#ibcon#flushed, iclass 33, count 2 2006.257.02:24:08.29#ibcon#about to write, iclass 33, count 2 2006.257.02:24:08.29#ibcon#wrote, iclass 33, count 2 2006.257.02:24:08.29#ibcon#about to read 3, iclass 33, count 2 2006.257.02:24:08.32#ibcon#read 3, iclass 33, count 2 2006.257.02:24:08.32#ibcon#about to read 4, iclass 33, count 2 2006.257.02:24:08.32#ibcon#read 4, iclass 33, count 2 2006.257.02:24:08.32#ibcon#about to read 5, iclass 33, count 2 2006.257.02:24:08.32#ibcon#read 5, iclass 33, count 2 2006.257.02:24:08.32#ibcon#about to read 6, iclass 33, count 2 2006.257.02:24:08.32#ibcon#read 6, iclass 33, count 2 2006.257.02:24:08.32#ibcon#end of sib2, iclass 33, count 2 2006.257.02:24:08.32#ibcon#*after write, iclass 33, count 2 2006.257.02:24:08.32#ibcon#*before return 0, iclass 33, count 2 2006.257.02:24:08.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:08.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:24:08.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.02:24:08.32#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:08.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:08.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:08.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:08.44#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:24:08.44#ibcon#first serial, iclass 33, count 0 2006.257.02:24:08.44#ibcon#enter sib2, iclass 33, count 0 2006.257.02:24:08.44#ibcon#flushed, iclass 33, count 0 2006.257.02:24:08.44#ibcon#about to write, iclass 33, count 0 2006.257.02:24:08.44#ibcon#wrote, iclass 33, count 0 2006.257.02:24:08.44#ibcon#about to read 3, iclass 33, count 0 2006.257.02:24:08.46#ibcon#read 3, iclass 33, count 0 2006.257.02:24:08.46#ibcon#about to read 4, iclass 33, count 0 2006.257.02:24:08.46#ibcon#read 4, iclass 33, count 0 2006.257.02:24:08.46#ibcon#about to read 5, iclass 33, count 0 2006.257.02:24:08.46#ibcon#read 5, iclass 33, count 0 2006.257.02:24:08.46#ibcon#about to read 6, iclass 33, count 0 2006.257.02:24:08.46#ibcon#read 6, iclass 33, count 0 2006.257.02:24:08.46#ibcon#end of sib2, iclass 33, count 0 2006.257.02:24:08.46#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:24:08.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:24:08.46#ibcon#[27=USB\r\n] 2006.257.02:24:08.46#ibcon#*before write, iclass 33, count 0 2006.257.02:24:08.46#ibcon#enter sib2, iclass 33, count 0 2006.257.02:24:08.46#ibcon#flushed, iclass 33, count 0 2006.257.02:24:08.46#ibcon#about to write, iclass 33, count 0 2006.257.02:24:08.46#ibcon#wrote, iclass 33, count 0 2006.257.02:24:08.46#ibcon#about to read 3, iclass 33, count 0 2006.257.02:24:08.49#ibcon#read 3, iclass 33, count 0 2006.257.02:24:08.49#ibcon#about to read 4, iclass 33, count 0 2006.257.02:24:08.49#ibcon#read 4, iclass 33, count 0 2006.257.02:24:08.49#ibcon#about to read 5, iclass 33, count 0 2006.257.02:24:08.49#ibcon#read 5, iclass 33, count 0 2006.257.02:24:08.49#ibcon#about to read 6, iclass 33, count 0 2006.257.02:24:08.49#ibcon#read 6, iclass 33, count 0 2006.257.02:24:08.49#ibcon#end of sib2, iclass 33, count 0 2006.257.02:24:08.49#ibcon#*after write, iclass 33, count 0 2006.257.02:24:08.49#ibcon#*before return 0, iclass 33, count 0 2006.257.02:24:08.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:08.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:24:08.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:24:08.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:24:08.49$vck44/vblo=8,744.99 2006.257.02:24:08.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.02:24:08.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.02:24:08.49#ibcon#ireg 17 cls_cnt 0 2006.257.02:24:08.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:08.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:08.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:08.49#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:24:08.49#ibcon#first serial, iclass 35, count 0 2006.257.02:24:08.49#ibcon#enter sib2, iclass 35, count 0 2006.257.02:24:08.49#ibcon#flushed, iclass 35, count 0 2006.257.02:24:08.49#ibcon#about to write, iclass 35, count 0 2006.257.02:24:08.49#ibcon#wrote, iclass 35, count 0 2006.257.02:24:08.49#ibcon#about to read 3, iclass 35, count 0 2006.257.02:24:08.51#ibcon#read 3, iclass 35, count 0 2006.257.02:24:08.51#ibcon#about to read 4, iclass 35, count 0 2006.257.02:24:08.51#ibcon#read 4, iclass 35, count 0 2006.257.02:24:08.51#ibcon#about to read 5, iclass 35, count 0 2006.257.02:24:08.51#ibcon#read 5, iclass 35, count 0 2006.257.02:24:08.51#ibcon#about to read 6, iclass 35, count 0 2006.257.02:24:08.51#ibcon#read 6, iclass 35, count 0 2006.257.02:24:08.51#ibcon#end of sib2, iclass 35, count 0 2006.257.02:24:08.51#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:24:08.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:24:08.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:24:08.51#ibcon#*before write, iclass 35, count 0 2006.257.02:24:08.51#ibcon#enter sib2, iclass 35, count 0 2006.257.02:24:08.51#ibcon#flushed, iclass 35, count 0 2006.257.02:24:08.51#ibcon#about to write, iclass 35, count 0 2006.257.02:24:08.51#ibcon#wrote, iclass 35, count 0 2006.257.02:24:08.51#ibcon#about to read 3, iclass 35, count 0 2006.257.02:24:08.55#ibcon#read 3, iclass 35, count 0 2006.257.02:24:08.55#ibcon#about to read 4, iclass 35, count 0 2006.257.02:24:08.55#ibcon#read 4, iclass 35, count 0 2006.257.02:24:08.55#ibcon#about to read 5, iclass 35, count 0 2006.257.02:24:08.55#ibcon#read 5, iclass 35, count 0 2006.257.02:24:08.55#ibcon#about to read 6, iclass 35, count 0 2006.257.02:24:08.55#ibcon#read 6, iclass 35, count 0 2006.257.02:24:08.55#ibcon#end of sib2, iclass 35, count 0 2006.257.02:24:08.55#ibcon#*after write, iclass 35, count 0 2006.257.02:24:08.55#ibcon#*before return 0, iclass 35, count 0 2006.257.02:24:08.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:08.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:24:08.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:24:08.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:24:08.55$vck44/vb=8,4 2006.257.02:24:08.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.02:24:08.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.02:24:08.55#ibcon#ireg 11 cls_cnt 2 2006.257.02:24:08.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:08.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:08.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:08.61#ibcon#enter wrdev, iclass 37, count 2 2006.257.02:24:08.61#ibcon#first serial, iclass 37, count 2 2006.257.02:24:08.61#ibcon#enter sib2, iclass 37, count 2 2006.257.02:24:08.61#ibcon#flushed, iclass 37, count 2 2006.257.02:24:08.61#ibcon#about to write, iclass 37, count 2 2006.257.02:24:08.61#ibcon#wrote, iclass 37, count 2 2006.257.02:24:08.61#ibcon#about to read 3, iclass 37, count 2 2006.257.02:24:08.63#ibcon#read 3, iclass 37, count 2 2006.257.02:24:08.63#ibcon#about to read 4, iclass 37, count 2 2006.257.02:24:08.63#ibcon#read 4, iclass 37, count 2 2006.257.02:24:08.63#ibcon#about to read 5, iclass 37, count 2 2006.257.02:24:08.63#ibcon#read 5, iclass 37, count 2 2006.257.02:24:08.63#ibcon#about to read 6, iclass 37, count 2 2006.257.02:24:08.63#ibcon#read 6, iclass 37, count 2 2006.257.02:24:08.63#ibcon#end of sib2, iclass 37, count 2 2006.257.02:24:08.63#ibcon#*mode == 0, iclass 37, count 2 2006.257.02:24:08.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.02:24:08.63#ibcon#[27=AT08-04\r\n] 2006.257.02:24:08.63#ibcon#*before write, iclass 37, count 2 2006.257.02:24:08.63#ibcon#enter sib2, iclass 37, count 2 2006.257.02:24:08.63#ibcon#flushed, iclass 37, count 2 2006.257.02:24:08.63#ibcon#about to write, iclass 37, count 2 2006.257.02:24:08.63#ibcon#wrote, iclass 37, count 2 2006.257.02:24:08.63#ibcon#about to read 3, iclass 37, count 2 2006.257.02:24:08.66#ibcon#read 3, iclass 37, count 2 2006.257.02:24:08.66#ibcon#about to read 4, iclass 37, count 2 2006.257.02:24:08.66#ibcon#read 4, iclass 37, count 2 2006.257.02:24:08.66#ibcon#about to read 5, iclass 37, count 2 2006.257.02:24:08.66#ibcon#read 5, iclass 37, count 2 2006.257.02:24:08.66#ibcon#about to read 6, iclass 37, count 2 2006.257.02:24:08.66#ibcon#read 6, iclass 37, count 2 2006.257.02:24:08.66#ibcon#end of sib2, iclass 37, count 2 2006.257.02:24:08.66#ibcon#*after write, iclass 37, count 2 2006.257.02:24:08.66#ibcon#*before return 0, iclass 37, count 2 2006.257.02:24:08.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:08.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:24:08.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.02:24:08.66#ibcon#ireg 7 cls_cnt 0 2006.257.02:24:08.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:08.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:08.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:08.78#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:24:08.78#ibcon#first serial, iclass 37, count 0 2006.257.02:24:08.78#ibcon#enter sib2, iclass 37, count 0 2006.257.02:24:08.78#ibcon#flushed, iclass 37, count 0 2006.257.02:24:08.78#ibcon#about to write, iclass 37, count 0 2006.257.02:24:08.78#ibcon#wrote, iclass 37, count 0 2006.257.02:24:08.78#ibcon#about to read 3, iclass 37, count 0 2006.257.02:24:08.80#ibcon#read 3, iclass 37, count 0 2006.257.02:24:08.80#ibcon#about to read 4, iclass 37, count 0 2006.257.02:24:08.80#ibcon#read 4, iclass 37, count 0 2006.257.02:24:08.80#ibcon#about to read 5, iclass 37, count 0 2006.257.02:24:08.80#ibcon#read 5, iclass 37, count 0 2006.257.02:24:08.80#ibcon#about to read 6, iclass 37, count 0 2006.257.02:24:08.80#ibcon#read 6, iclass 37, count 0 2006.257.02:24:08.80#ibcon#end of sib2, iclass 37, count 0 2006.257.02:24:08.80#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:24:08.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:24:08.80#ibcon#[27=USB\r\n] 2006.257.02:24:08.80#ibcon#*before write, iclass 37, count 0 2006.257.02:24:08.80#ibcon#enter sib2, iclass 37, count 0 2006.257.02:24:08.80#ibcon#flushed, iclass 37, count 0 2006.257.02:24:08.80#ibcon#about to write, iclass 37, count 0 2006.257.02:24:08.80#ibcon#wrote, iclass 37, count 0 2006.257.02:24:08.80#ibcon#about to read 3, iclass 37, count 0 2006.257.02:24:08.83#ibcon#read 3, iclass 37, count 0 2006.257.02:24:08.83#ibcon#about to read 4, iclass 37, count 0 2006.257.02:24:08.83#ibcon#read 4, iclass 37, count 0 2006.257.02:24:08.83#ibcon#about to read 5, iclass 37, count 0 2006.257.02:24:08.83#ibcon#read 5, iclass 37, count 0 2006.257.02:24:08.83#ibcon#about to read 6, iclass 37, count 0 2006.257.02:24:08.83#ibcon#read 6, iclass 37, count 0 2006.257.02:24:08.83#ibcon#end of sib2, iclass 37, count 0 2006.257.02:24:08.83#ibcon#*after write, iclass 37, count 0 2006.257.02:24:08.83#ibcon#*before return 0, iclass 37, count 0 2006.257.02:24:08.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:08.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:24:08.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:24:08.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:24:08.83$vck44/vabw=wide 2006.257.02:24:08.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.02:24:08.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.02:24:08.83#ibcon#ireg 8 cls_cnt 0 2006.257.02:24:08.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:08.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:08.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:08.83#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:24:08.83#ibcon#first serial, iclass 39, count 0 2006.257.02:24:08.83#ibcon#enter sib2, iclass 39, count 0 2006.257.02:24:08.83#ibcon#flushed, iclass 39, count 0 2006.257.02:24:08.83#ibcon#about to write, iclass 39, count 0 2006.257.02:24:08.83#ibcon#wrote, iclass 39, count 0 2006.257.02:24:08.83#ibcon#about to read 3, iclass 39, count 0 2006.257.02:24:08.85#ibcon#read 3, iclass 39, count 0 2006.257.02:24:08.85#ibcon#about to read 4, iclass 39, count 0 2006.257.02:24:08.85#ibcon#read 4, iclass 39, count 0 2006.257.02:24:08.85#ibcon#about to read 5, iclass 39, count 0 2006.257.02:24:08.85#ibcon#read 5, iclass 39, count 0 2006.257.02:24:08.85#ibcon#about to read 6, iclass 39, count 0 2006.257.02:24:08.85#ibcon#read 6, iclass 39, count 0 2006.257.02:24:08.85#ibcon#end of sib2, iclass 39, count 0 2006.257.02:24:08.85#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:24:08.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:24:08.85#ibcon#[25=BW32\r\n] 2006.257.02:24:08.85#ibcon#*before write, iclass 39, count 0 2006.257.02:24:08.85#ibcon#enter sib2, iclass 39, count 0 2006.257.02:24:08.85#ibcon#flushed, iclass 39, count 0 2006.257.02:24:08.85#ibcon#about to write, iclass 39, count 0 2006.257.02:24:08.85#ibcon#wrote, iclass 39, count 0 2006.257.02:24:08.85#ibcon#about to read 3, iclass 39, count 0 2006.257.02:24:08.88#ibcon#read 3, iclass 39, count 0 2006.257.02:24:08.88#ibcon#about to read 4, iclass 39, count 0 2006.257.02:24:08.88#ibcon#read 4, iclass 39, count 0 2006.257.02:24:08.88#ibcon#about to read 5, iclass 39, count 0 2006.257.02:24:08.88#ibcon#read 5, iclass 39, count 0 2006.257.02:24:08.88#ibcon#about to read 6, iclass 39, count 0 2006.257.02:24:08.88#ibcon#read 6, iclass 39, count 0 2006.257.02:24:08.88#ibcon#end of sib2, iclass 39, count 0 2006.257.02:24:08.88#ibcon#*after write, iclass 39, count 0 2006.257.02:24:08.88#ibcon#*before return 0, iclass 39, count 0 2006.257.02:24:08.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:08.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:24:08.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:24:08.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:24:08.88$vck44/vbbw=wide 2006.257.02:24:08.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.02:24:08.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.02:24:08.88#ibcon#ireg 8 cls_cnt 0 2006.257.02:24:08.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:24:08.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:24:08.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:24:08.95#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:24:08.95#ibcon#first serial, iclass 3, count 0 2006.257.02:24:08.95#ibcon#enter sib2, iclass 3, count 0 2006.257.02:24:08.95#ibcon#flushed, iclass 3, count 0 2006.257.02:24:08.95#ibcon#about to write, iclass 3, count 0 2006.257.02:24:08.95#ibcon#wrote, iclass 3, count 0 2006.257.02:24:08.95#ibcon#about to read 3, iclass 3, count 0 2006.257.02:24:08.97#ibcon#read 3, iclass 3, count 0 2006.257.02:24:08.97#ibcon#about to read 4, iclass 3, count 0 2006.257.02:24:08.97#ibcon#read 4, iclass 3, count 0 2006.257.02:24:08.97#ibcon#about to read 5, iclass 3, count 0 2006.257.02:24:08.97#ibcon#read 5, iclass 3, count 0 2006.257.02:24:08.97#ibcon#about to read 6, iclass 3, count 0 2006.257.02:24:08.97#ibcon#read 6, iclass 3, count 0 2006.257.02:24:08.97#ibcon#end of sib2, iclass 3, count 0 2006.257.02:24:08.97#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:24:08.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:24:08.97#ibcon#[27=BW32\r\n] 2006.257.02:24:08.97#ibcon#*before write, iclass 3, count 0 2006.257.02:24:08.97#ibcon#enter sib2, iclass 3, count 0 2006.257.02:24:08.97#ibcon#flushed, iclass 3, count 0 2006.257.02:24:08.97#ibcon#about to write, iclass 3, count 0 2006.257.02:24:08.97#ibcon#wrote, iclass 3, count 0 2006.257.02:24:08.97#ibcon#about to read 3, iclass 3, count 0 2006.257.02:24:09.00#ibcon#read 3, iclass 3, count 0 2006.257.02:24:09.00#ibcon#about to read 4, iclass 3, count 0 2006.257.02:24:09.00#ibcon#read 4, iclass 3, count 0 2006.257.02:24:09.00#ibcon#about to read 5, iclass 3, count 0 2006.257.02:24:09.00#ibcon#read 5, iclass 3, count 0 2006.257.02:24:09.00#ibcon#about to read 6, iclass 3, count 0 2006.257.02:24:09.00#ibcon#read 6, iclass 3, count 0 2006.257.02:24:09.00#ibcon#end of sib2, iclass 3, count 0 2006.257.02:24:09.00#ibcon#*after write, iclass 3, count 0 2006.257.02:24:09.00#ibcon#*before return 0, iclass 3, count 0 2006.257.02:24:09.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:24:09.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:24:09.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:24:09.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:24:09.00$setupk4/ifdk4 2006.257.02:24:09.00$ifdk4/lo= 2006.257.02:24:09.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:24:09.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:24:09.00$ifdk4/patch= 2006.257.02:24:09.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:24:09.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:24:09.00$setupk4/!*+20s 2006.257.02:24:10.47#abcon#<5=/02 2.3 6.9 17.87 971011.9\r\n> 2006.257.02:24:10.49#abcon#{5=INTERFACE CLEAR} 2006.257.02:24:10.55#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:24:20.64#abcon#<5=/02 2.4 6.9 17.87 971011.9\r\n> 2006.257.02:24:20.66#abcon#{5=INTERFACE CLEAR} 2006.257.02:24:20.72#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:24:23.50$setupk4/"tpicd 2006.257.02:24:23.50$setupk4/echo=off 2006.257.02:24:23.50$setupk4/xlog=off 2006.257.02:24:23.50:!2006.257.02:33:26 2006.257.02:24:32.14#trakl#Source acquired 2006.257.02:24:33.14#flagr#flagr/antenna,acquired 2006.257.02:33:26.00:preob 2006.257.02:33:26.14/onsource/TRACKING 2006.257.02:33:26.14:!2006.257.02:33:36 2006.257.02:33:36.00:"tape 2006.257.02:33:36.00:"st=record 2006.257.02:33:36.00:data_valid=on 2006.257.02:33:36.00:midob 2006.257.02:33:36.14/onsource/TRACKING 2006.257.02:33:36.14/wx/18.09,1012.3,97 2006.257.02:33:36.35/cable/+6.4872E-03 2006.257.02:33:37.44/va/01,08,usb,yes,31,34 2006.257.02:33:37.44/va/02,07,usb,yes,34,34 2006.257.02:33:37.44/va/03,08,usb,yes,30,32 2006.257.02:33:37.44/va/04,07,usb,yes,35,36 2006.257.02:33:37.44/va/05,04,usb,yes,31,32 2006.257.02:33:37.44/va/06,04,usb,yes,35,34 2006.257.02:33:37.44/va/07,04,usb,yes,36,36 2006.257.02:33:37.44/va/08,04,usb,yes,30,36 2006.257.02:33:37.67/valo/01,524.99,yes,locked 2006.257.02:33:37.67/valo/02,534.99,yes,locked 2006.257.02:33:37.67/valo/03,564.99,yes,locked 2006.257.02:33:37.67/valo/04,624.99,yes,locked 2006.257.02:33:37.67/valo/05,734.99,yes,locked 2006.257.02:33:37.67/valo/06,814.99,yes,locked 2006.257.02:33:37.67/valo/07,864.99,yes,locked 2006.257.02:33:37.67/valo/08,884.99,yes,locked 2006.257.02:33:38.76/vb/01,04,usb,yes,31,28 2006.257.02:33:38.76/vb/02,05,usb,yes,29,29 2006.257.02:33:38.76/vb/03,04,usb,yes,30,33 2006.257.02:33:38.76/vb/04,05,usb,yes,30,29 2006.257.02:33:38.76/vb/05,04,usb,yes,27,29 2006.257.02:33:38.76/vb/06,04,usb,yes,31,27 2006.257.02:33:38.76/vb/07,04,usb,yes,31,31 2006.257.02:33:38.76/vb/08,04,usb,yes,28,32 2006.257.02:33:39.00/vblo/01,629.99,yes,locked 2006.257.02:33:39.00/vblo/02,634.99,yes,locked 2006.257.02:33:39.00/vblo/03,649.99,yes,locked 2006.257.02:33:39.00/vblo/04,679.99,yes,locked 2006.257.02:33:39.00/vblo/05,709.99,yes,locked 2006.257.02:33:39.00/vblo/06,719.99,yes,locked 2006.257.02:33:39.00/vblo/07,734.99,yes,locked 2006.257.02:33:39.00/vblo/08,744.99,yes,locked 2006.257.02:33:39.15/vabw/8 2006.257.02:33:39.30/vbbw/8 2006.257.02:33:39.39/xfe/off,on,15.5 2006.257.02:33:39.77/ifatt/23,28,28,28 2006.257.02:33:40.07/fmout-gps/S +4.56E-07 2006.257.02:33:40.11:!2006.257.02:34:16 2006.257.02:34:16.00:data_valid=off 2006.257.02:34:16.01:"et 2006.257.02:34:16.01:!+3s 2006.257.02:34:19.03:"tape 2006.257.02:34:19.04:postob 2006.257.02:34:19.20/cable/+6.4863E-03 2006.257.02:34:19.21/wx/18.12,1012.3,97 2006.257.02:34:19.28/fmout-gps/S +4.57E-07 2006.257.02:34:19.28:scan_name=257-0236,jd0609,200 2006.257.02:34:19.29:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.257.02:34:21.14#flagr#flagr/antenna,new-source 2006.257.02:34:21.15:checkk5 2006.257.02:34:21.62/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:34:22.04/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:34:22.44/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:34:22.88/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:34:23.27/chk_obsdata//k5ts1/T2570233??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.02:34:23.62/chk_obsdata//k5ts2/T2570233??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.02:34:24.22/chk_obsdata//k5ts3/T2570233??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.02:34:24.63/chk_obsdata//k5ts4/T2570233??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.02:34:25.38/k5log//k5ts1_log_newline 2006.257.02:34:26.11/k5log//k5ts2_log_newline 2006.257.02:34:26.94/k5log//k5ts3_log_newline 2006.257.02:34:27.93/k5log//k5ts4_log_newline 2006.257.02:34:27.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:34:27.96:setupk4=1 2006.257.02:34:27.96$setupk4/echo=on 2006.257.02:34:27.96$setupk4/pcalon 2006.257.02:34:27.96$pcalon/"no phase cal control is implemented here 2006.257.02:34:27.96$setupk4/"tpicd=stop 2006.257.02:34:27.96$setupk4/"rec=synch_on 2006.257.02:34:27.96$setupk4/"rec_mode=128 2006.257.02:34:27.96$setupk4/!* 2006.257.02:34:27.96$setupk4/recpk4 2006.257.02:34:27.96$recpk4/recpatch= 2006.257.02:34:27.96$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:34:27.96$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:34:27.96$setupk4/vck44 2006.257.02:34:27.96$vck44/valo=1,524.99 2006.257.02:34:27.96#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.02:34:27.96#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.02:34:27.96#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:27.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:27.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:27.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:27.96#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:34:27.96#ibcon#first serial, iclass 38, count 0 2006.257.02:34:27.96#ibcon#enter sib2, iclass 38, count 0 2006.257.02:34:27.96#ibcon#flushed, iclass 38, count 0 2006.257.02:34:27.96#ibcon#about to write, iclass 38, count 0 2006.257.02:34:27.96#ibcon#wrote, iclass 38, count 0 2006.257.02:34:27.96#ibcon#about to read 3, iclass 38, count 0 2006.257.02:34:27.99#ibcon#read 3, iclass 38, count 0 2006.257.02:34:27.99#ibcon#about to read 4, iclass 38, count 0 2006.257.02:34:27.99#ibcon#read 4, iclass 38, count 0 2006.257.02:34:27.99#ibcon#about to read 5, iclass 38, count 0 2006.257.02:34:27.99#ibcon#read 5, iclass 38, count 0 2006.257.02:34:27.99#ibcon#about to read 6, iclass 38, count 0 2006.257.02:34:27.99#ibcon#read 6, iclass 38, count 0 2006.257.02:34:27.99#ibcon#end of sib2, iclass 38, count 0 2006.257.02:34:27.99#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:34:27.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:34:27.99#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:34:27.99#ibcon#*before write, iclass 38, count 0 2006.257.02:34:27.99#ibcon#enter sib2, iclass 38, count 0 2006.257.02:34:27.99#ibcon#flushed, iclass 38, count 0 2006.257.02:34:27.99#ibcon#about to write, iclass 38, count 0 2006.257.02:34:27.99#ibcon#wrote, iclass 38, count 0 2006.257.02:34:27.99#ibcon#about to read 3, iclass 38, count 0 2006.257.02:34:28.03#ibcon#read 3, iclass 38, count 0 2006.257.02:34:28.03#ibcon#about to read 4, iclass 38, count 0 2006.257.02:34:28.03#ibcon#read 4, iclass 38, count 0 2006.257.02:34:28.03#ibcon#about to read 5, iclass 38, count 0 2006.257.02:34:28.03#ibcon#read 5, iclass 38, count 0 2006.257.02:34:28.03#ibcon#about to read 6, iclass 38, count 0 2006.257.02:34:28.03#ibcon#read 6, iclass 38, count 0 2006.257.02:34:28.03#ibcon#end of sib2, iclass 38, count 0 2006.257.02:34:28.03#ibcon#*after write, iclass 38, count 0 2006.257.02:34:28.03#ibcon#*before return 0, iclass 38, count 0 2006.257.02:34:28.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:28.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:28.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:34:28.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:34:28.03$vck44/va=1,8 2006.257.02:34:28.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.02:34:28.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.02:34:28.03#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:28.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:28.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:28.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:28.03#ibcon#enter wrdev, iclass 40, count 2 2006.257.02:34:28.03#ibcon#first serial, iclass 40, count 2 2006.257.02:34:28.03#ibcon#enter sib2, iclass 40, count 2 2006.257.02:34:28.03#ibcon#flushed, iclass 40, count 2 2006.257.02:34:28.03#ibcon#about to write, iclass 40, count 2 2006.257.02:34:28.03#ibcon#wrote, iclass 40, count 2 2006.257.02:34:28.03#ibcon#about to read 3, iclass 40, count 2 2006.257.02:34:28.05#ibcon#read 3, iclass 40, count 2 2006.257.02:34:28.05#ibcon#about to read 4, iclass 40, count 2 2006.257.02:34:28.05#ibcon#read 4, iclass 40, count 2 2006.257.02:34:28.05#ibcon#about to read 5, iclass 40, count 2 2006.257.02:34:28.05#ibcon#read 5, iclass 40, count 2 2006.257.02:34:28.05#ibcon#about to read 6, iclass 40, count 2 2006.257.02:34:28.05#ibcon#read 6, iclass 40, count 2 2006.257.02:34:28.05#ibcon#end of sib2, iclass 40, count 2 2006.257.02:34:28.05#ibcon#*mode == 0, iclass 40, count 2 2006.257.02:34:28.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.02:34:28.05#ibcon#[25=AT01-08\r\n] 2006.257.02:34:28.05#ibcon#*before write, iclass 40, count 2 2006.257.02:34:28.05#ibcon#enter sib2, iclass 40, count 2 2006.257.02:34:28.05#ibcon#flushed, iclass 40, count 2 2006.257.02:34:28.05#ibcon#about to write, iclass 40, count 2 2006.257.02:34:28.05#ibcon#wrote, iclass 40, count 2 2006.257.02:34:28.05#ibcon#about to read 3, iclass 40, count 2 2006.257.02:34:28.08#ibcon#read 3, iclass 40, count 2 2006.257.02:34:28.08#ibcon#about to read 4, iclass 40, count 2 2006.257.02:34:28.08#ibcon#read 4, iclass 40, count 2 2006.257.02:34:28.08#ibcon#about to read 5, iclass 40, count 2 2006.257.02:34:28.08#ibcon#read 5, iclass 40, count 2 2006.257.02:34:28.08#ibcon#about to read 6, iclass 40, count 2 2006.257.02:34:28.08#ibcon#read 6, iclass 40, count 2 2006.257.02:34:28.08#ibcon#end of sib2, iclass 40, count 2 2006.257.02:34:28.08#ibcon#*after write, iclass 40, count 2 2006.257.02:34:28.08#ibcon#*before return 0, iclass 40, count 2 2006.257.02:34:28.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:28.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:28.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.02:34:28.08#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:28.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:28.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:28.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:28.20#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:34:28.20#ibcon#first serial, iclass 40, count 0 2006.257.02:34:28.20#ibcon#enter sib2, iclass 40, count 0 2006.257.02:34:28.20#ibcon#flushed, iclass 40, count 0 2006.257.02:34:28.20#ibcon#about to write, iclass 40, count 0 2006.257.02:34:28.20#ibcon#wrote, iclass 40, count 0 2006.257.02:34:28.20#ibcon#about to read 3, iclass 40, count 0 2006.257.02:34:28.23#ibcon#read 3, iclass 40, count 0 2006.257.02:34:28.23#ibcon#about to read 4, iclass 40, count 0 2006.257.02:34:28.23#ibcon#read 4, iclass 40, count 0 2006.257.02:34:28.23#ibcon#about to read 5, iclass 40, count 0 2006.257.02:34:28.23#ibcon#read 5, iclass 40, count 0 2006.257.02:34:28.23#ibcon#about to read 6, iclass 40, count 0 2006.257.02:34:28.23#ibcon#read 6, iclass 40, count 0 2006.257.02:34:28.23#ibcon#end of sib2, iclass 40, count 0 2006.257.02:34:28.23#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:34:28.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:34:28.23#ibcon#[25=USB\r\n] 2006.257.02:34:28.23#ibcon#*before write, iclass 40, count 0 2006.257.02:34:28.23#ibcon#enter sib2, iclass 40, count 0 2006.257.02:34:28.23#ibcon#flushed, iclass 40, count 0 2006.257.02:34:28.23#ibcon#about to write, iclass 40, count 0 2006.257.02:34:28.23#ibcon#wrote, iclass 40, count 0 2006.257.02:34:28.23#ibcon#about to read 3, iclass 40, count 0 2006.257.02:34:28.25#ibcon#read 3, iclass 40, count 0 2006.257.02:34:28.25#ibcon#about to read 4, iclass 40, count 0 2006.257.02:34:28.25#ibcon#read 4, iclass 40, count 0 2006.257.02:34:28.25#ibcon#about to read 5, iclass 40, count 0 2006.257.02:34:28.25#ibcon#read 5, iclass 40, count 0 2006.257.02:34:28.25#ibcon#about to read 6, iclass 40, count 0 2006.257.02:34:28.25#ibcon#read 6, iclass 40, count 0 2006.257.02:34:28.25#ibcon#end of sib2, iclass 40, count 0 2006.257.02:34:28.25#ibcon#*after write, iclass 40, count 0 2006.257.02:34:28.25#ibcon#*before return 0, iclass 40, count 0 2006.257.02:34:28.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:28.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:28.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:34:28.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:34:28.25$vck44/valo=2,534.99 2006.257.02:34:28.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.02:34:28.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.02:34:28.25#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:28.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:34:28.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:34:28.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:34:28.25#ibcon#enter wrdev, iclass 4, count 0 2006.257.02:34:28.25#ibcon#first serial, iclass 4, count 0 2006.257.02:34:28.25#ibcon#enter sib2, iclass 4, count 0 2006.257.02:34:28.25#ibcon#flushed, iclass 4, count 0 2006.257.02:34:28.25#ibcon#about to write, iclass 4, count 0 2006.257.02:34:28.25#ibcon#wrote, iclass 4, count 0 2006.257.02:34:28.25#ibcon#about to read 3, iclass 4, count 0 2006.257.02:34:28.27#ibcon#read 3, iclass 4, count 0 2006.257.02:34:28.27#ibcon#about to read 4, iclass 4, count 0 2006.257.02:34:28.27#ibcon#read 4, iclass 4, count 0 2006.257.02:34:28.27#ibcon#about to read 5, iclass 4, count 0 2006.257.02:34:28.27#ibcon#read 5, iclass 4, count 0 2006.257.02:34:28.27#ibcon#about to read 6, iclass 4, count 0 2006.257.02:34:28.27#ibcon#read 6, iclass 4, count 0 2006.257.02:34:28.27#ibcon#end of sib2, iclass 4, count 0 2006.257.02:34:28.27#ibcon#*mode == 0, iclass 4, count 0 2006.257.02:34:28.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.02:34:28.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:34:28.27#ibcon#*before write, iclass 4, count 0 2006.257.02:34:28.27#ibcon#enter sib2, iclass 4, count 0 2006.257.02:34:28.27#ibcon#flushed, iclass 4, count 0 2006.257.02:34:28.27#ibcon#about to write, iclass 4, count 0 2006.257.02:34:28.27#ibcon#wrote, iclass 4, count 0 2006.257.02:34:28.27#ibcon#about to read 3, iclass 4, count 0 2006.257.02:34:28.32#ibcon#read 3, iclass 4, count 0 2006.257.02:34:28.32#ibcon#about to read 4, iclass 4, count 0 2006.257.02:34:28.32#ibcon#read 4, iclass 4, count 0 2006.257.02:34:28.32#ibcon#about to read 5, iclass 4, count 0 2006.257.02:34:28.32#ibcon#read 5, iclass 4, count 0 2006.257.02:34:28.32#ibcon#about to read 6, iclass 4, count 0 2006.257.02:34:28.32#ibcon#read 6, iclass 4, count 0 2006.257.02:34:28.32#ibcon#end of sib2, iclass 4, count 0 2006.257.02:34:28.32#ibcon#*after write, iclass 4, count 0 2006.257.02:34:28.32#ibcon#*before return 0, iclass 4, count 0 2006.257.02:34:28.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:34:28.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.02:34:28.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.02:34:28.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.02:34:28.32$vck44/va=2,7 2006.257.02:34:28.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.02:34:28.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.02:34:28.32#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:28.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:34:28.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:34:28.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:34:28.36#ibcon#enter wrdev, iclass 6, count 2 2006.257.02:34:28.36#ibcon#first serial, iclass 6, count 2 2006.257.02:34:28.36#ibcon#enter sib2, iclass 6, count 2 2006.257.02:34:28.36#ibcon#flushed, iclass 6, count 2 2006.257.02:34:28.36#ibcon#about to write, iclass 6, count 2 2006.257.02:34:28.36#ibcon#wrote, iclass 6, count 2 2006.257.02:34:28.36#ibcon#about to read 3, iclass 6, count 2 2006.257.02:34:28.38#ibcon#read 3, iclass 6, count 2 2006.257.02:34:28.38#ibcon#about to read 4, iclass 6, count 2 2006.257.02:34:28.38#ibcon#read 4, iclass 6, count 2 2006.257.02:34:28.38#ibcon#about to read 5, iclass 6, count 2 2006.257.02:34:28.38#ibcon#read 5, iclass 6, count 2 2006.257.02:34:28.38#ibcon#about to read 6, iclass 6, count 2 2006.257.02:34:28.38#ibcon#read 6, iclass 6, count 2 2006.257.02:34:28.38#ibcon#end of sib2, iclass 6, count 2 2006.257.02:34:28.38#ibcon#*mode == 0, iclass 6, count 2 2006.257.02:34:28.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.02:34:28.38#ibcon#[25=AT02-07\r\n] 2006.257.02:34:28.38#ibcon#*before write, iclass 6, count 2 2006.257.02:34:28.38#ibcon#enter sib2, iclass 6, count 2 2006.257.02:34:28.38#ibcon#flushed, iclass 6, count 2 2006.257.02:34:28.38#ibcon#about to write, iclass 6, count 2 2006.257.02:34:28.38#ibcon#wrote, iclass 6, count 2 2006.257.02:34:28.38#ibcon#about to read 3, iclass 6, count 2 2006.257.02:34:28.42#ibcon#read 3, iclass 6, count 2 2006.257.02:34:28.42#ibcon#about to read 4, iclass 6, count 2 2006.257.02:34:28.42#ibcon#read 4, iclass 6, count 2 2006.257.02:34:28.42#ibcon#about to read 5, iclass 6, count 2 2006.257.02:34:28.42#ibcon#read 5, iclass 6, count 2 2006.257.02:34:28.42#ibcon#about to read 6, iclass 6, count 2 2006.257.02:34:28.42#ibcon#read 6, iclass 6, count 2 2006.257.02:34:28.42#ibcon#end of sib2, iclass 6, count 2 2006.257.02:34:28.42#ibcon#*after write, iclass 6, count 2 2006.257.02:34:28.42#ibcon#*before return 0, iclass 6, count 2 2006.257.02:34:28.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:34:28.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.02:34:28.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.02:34:28.42#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:28.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:34:28.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:34:28.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:34:28.53#ibcon#enter wrdev, iclass 6, count 0 2006.257.02:34:28.53#ibcon#first serial, iclass 6, count 0 2006.257.02:34:28.53#ibcon#enter sib2, iclass 6, count 0 2006.257.02:34:28.53#ibcon#flushed, iclass 6, count 0 2006.257.02:34:28.53#ibcon#about to write, iclass 6, count 0 2006.257.02:34:28.53#ibcon#wrote, iclass 6, count 0 2006.257.02:34:28.53#ibcon#about to read 3, iclass 6, count 0 2006.257.02:34:28.55#ibcon#read 3, iclass 6, count 0 2006.257.02:34:28.55#ibcon#about to read 4, iclass 6, count 0 2006.257.02:34:28.55#ibcon#read 4, iclass 6, count 0 2006.257.02:34:28.55#ibcon#about to read 5, iclass 6, count 0 2006.257.02:34:28.55#ibcon#read 5, iclass 6, count 0 2006.257.02:34:28.55#ibcon#about to read 6, iclass 6, count 0 2006.257.02:34:28.55#ibcon#read 6, iclass 6, count 0 2006.257.02:34:28.55#ibcon#end of sib2, iclass 6, count 0 2006.257.02:34:28.55#ibcon#*mode == 0, iclass 6, count 0 2006.257.02:34:28.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.02:34:28.55#ibcon#[25=USB\r\n] 2006.257.02:34:28.55#ibcon#*before write, iclass 6, count 0 2006.257.02:34:28.55#ibcon#enter sib2, iclass 6, count 0 2006.257.02:34:28.55#ibcon#flushed, iclass 6, count 0 2006.257.02:34:28.55#ibcon#about to write, iclass 6, count 0 2006.257.02:34:28.55#ibcon#wrote, iclass 6, count 0 2006.257.02:34:28.55#ibcon#about to read 3, iclass 6, count 0 2006.257.02:34:28.58#ibcon#read 3, iclass 6, count 0 2006.257.02:34:28.58#ibcon#about to read 4, iclass 6, count 0 2006.257.02:34:28.58#ibcon#read 4, iclass 6, count 0 2006.257.02:34:28.58#ibcon#about to read 5, iclass 6, count 0 2006.257.02:34:28.58#ibcon#read 5, iclass 6, count 0 2006.257.02:34:28.58#ibcon#about to read 6, iclass 6, count 0 2006.257.02:34:28.58#ibcon#read 6, iclass 6, count 0 2006.257.02:34:28.58#ibcon#end of sib2, iclass 6, count 0 2006.257.02:34:28.58#ibcon#*after write, iclass 6, count 0 2006.257.02:34:28.58#ibcon#*before return 0, iclass 6, count 0 2006.257.02:34:28.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:34:28.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.02:34:28.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.02:34:28.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.02:34:28.58$vck44/valo=3,564.99 2006.257.02:34:28.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.02:34:28.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.02:34:28.58#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:28.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:28.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:28.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:28.58#ibcon#enter wrdev, iclass 10, count 0 2006.257.02:34:28.58#ibcon#first serial, iclass 10, count 0 2006.257.02:34:28.58#ibcon#enter sib2, iclass 10, count 0 2006.257.02:34:28.58#ibcon#flushed, iclass 10, count 0 2006.257.02:34:28.58#ibcon#about to write, iclass 10, count 0 2006.257.02:34:28.58#ibcon#wrote, iclass 10, count 0 2006.257.02:34:28.58#ibcon#about to read 3, iclass 10, count 0 2006.257.02:34:28.61#ibcon#read 3, iclass 10, count 0 2006.257.02:34:28.61#ibcon#about to read 4, iclass 10, count 0 2006.257.02:34:28.61#ibcon#read 4, iclass 10, count 0 2006.257.02:34:28.61#ibcon#about to read 5, iclass 10, count 0 2006.257.02:34:28.61#ibcon#read 5, iclass 10, count 0 2006.257.02:34:28.61#ibcon#about to read 6, iclass 10, count 0 2006.257.02:34:28.61#ibcon#read 6, iclass 10, count 0 2006.257.02:34:28.61#ibcon#end of sib2, iclass 10, count 0 2006.257.02:34:28.61#ibcon#*mode == 0, iclass 10, count 0 2006.257.02:34:28.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.02:34:28.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:34:28.61#ibcon#*before write, iclass 10, count 0 2006.257.02:34:28.61#ibcon#enter sib2, iclass 10, count 0 2006.257.02:34:28.61#ibcon#flushed, iclass 10, count 0 2006.257.02:34:28.61#ibcon#about to write, iclass 10, count 0 2006.257.02:34:28.61#ibcon#wrote, iclass 10, count 0 2006.257.02:34:28.61#ibcon#about to read 3, iclass 10, count 0 2006.257.02:34:28.65#ibcon#read 3, iclass 10, count 0 2006.257.02:34:28.65#ibcon#about to read 4, iclass 10, count 0 2006.257.02:34:28.65#ibcon#read 4, iclass 10, count 0 2006.257.02:34:28.65#ibcon#about to read 5, iclass 10, count 0 2006.257.02:34:28.65#ibcon#read 5, iclass 10, count 0 2006.257.02:34:28.65#ibcon#about to read 6, iclass 10, count 0 2006.257.02:34:28.65#ibcon#read 6, iclass 10, count 0 2006.257.02:34:28.65#ibcon#end of sib2, iclass 10, count 0 2006.257.02:34:28.65#ibcon#*after write, iclass 10, count 0 2006.257.02:34:28.65#ibcon#*before return 0, iclass 10, count 0 2006.257.02:34:28.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:28.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:28.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.02:34:28.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.02:34:28.65$vck44/va=3,8 2006.257.02:34:28.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.02:34:28.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.02:34:28.65#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:28.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:28.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:28.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:28.70#ibcon#enter wrdev, iclass 12, count 2 2006.257.02:34:28.70#ibcon#first serial, iclass 12, count 2 2006.257.02:34:28.70#ibcon#enter sib2, iclass 12, count 2 2006.257.02:34:28.70#ibcon#flushed, iclass 12, count 2 2006.257.02:34:28.70#ibcon#about to write, iclass 12, count 2 2006.257.02:34:28.70#ibcon#wrote, iclass 12, count 2 2006.257.02:34:28.70#ibcon#about to read 3, iclass 12, count 2 2006.257.02:34:28.72#ibcon#read 3, iclass 12, count 2 2006.257.02:34:28.72#ibcon#about to read 4, iclass 12, count 2 2006.257.02:34:28.72#ibcon#read 4, iclass 12, count 2 2006.257.02:34:28.72#ibcon#about to read 5, iclass 12, count 2 2006.257.02:34:28.72#ibcon#read 5, iclass 12, count 2 2006.257.02:34:28.72#ibcon#about to read 6, iclass 12, count 2 2006.257.02:34:28.72#ibcon#read 6, iclass 12, count 2 2006.257.02:34:28.72#ibcon#end of sib2, iclass 12, count 2 2006.257.02:34:28.72#ibcon#*mode == 0, iclass 12, count 2 2006.257.02:34:28.72#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.02:34:28.72#ibcon#[25=AT03-08\r\n] 2006.257.02:34:28.72#ibcon#*before write, iclass 12, count 2 2006.257.02:34:28.72#ibcon#enter sib2, iclass 12, count 2 2006.257.02:34:28.72#ibcon#flushed, iclass 12, count 2 2006.257.02:34:28.72#ibcon#about to write, iclass 12, count 2 2006.257.02:34:28.72#ibcon#wrote, iclass 12, count 2 2006.257.02:34:28.72#ibcon#about to read 3, iclass 12, count 2 2006.257.02:34:28.75#ibcon#read 3, iclass 12, count 2 2006.257.02:34:28.75#ibcon#about to read 4, iclass 12, count 2 2006.257.02:34:28.75#ibcon#read 4, iclass 12, count 2 2006.257.02:34:28.75#ibcon#about to read 5, iclass 12, count 2 2006.257.02:34:28.75#ibcon#read 5, iclass 12, count 2 2006.257.02:34:28.75#ibcon#about to read 6, iclass 12, count 2 2006.257.02:34:28.75#ibcon#read 6, iclass 12, count 2 2006.257.02:34:28.75#ibcon#end of sib2, iclass 12, count 2 2006.257.02:34:28.75#ibcon#*after write, iclass 12, count 2 2006.257.02:34:28.75#ibcon#*before return 0, iclass 12, count 2 2006.257.02:34:28.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:28.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:28.75#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.02:34:28.75#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:28.75#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:28.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:28.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:28.88#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:34:28.88#ibcon#first serial, iclass 12, count 0 2006.257.02:34:28.88#ibcon#enter sib2, iclass 12, count 0 2006.257.02:34:28.88#ibcon#flushed, iclass 12, count 0 2006.257.02:34:28.88#ibcon#about to write, iclass 12, count 0 2006.257.02:34:28.88#ibcon#wrote, iclass 12, count 0 2006.257.02:34:28.88#ibcon#about to read 3, iclass 12, count 0 2006.257.02:34:28.89#ibcon#read 3, iclass 12, count 0 2006.257.02:34:28.89#ibcon#about to read 4, iclass 12, count 0 2006.257.02:34:28.89#ibcon#read 4, iclass 12, count 0 2006.257.02:34:28.89#ibcon#about to read 5, iclass 12, count 0 2006.257.02:34:28.89#ibcon#read 5, iclass 12, count 0 2006.257.02:34:28.89#ibcon#about to read 6, iclass 12, count 0 2006.257.02:34:28.89#ibcon#read 6, iclass 12, count 0 2006.257.02:34:28.89#ibcon#end of sib2, iclass 12, count 0 2006.257.02:34:28.89#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:34:28.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:34:28.89#ibcon#[25=USB\r\n] 2006.257.02:34:28.89#ibcon#*before write, iclass 12, count 0 2006.257.02:34:28.89#ibcon#enter sib2, iclass 12, count 0 2006.257.02:34:28.89#ibcon#flushed, iclass 12, count 0 2006.257.02:34:28.89#ibcon#about to write, iclass 12, count 0 2006.257.02:34:28.89#ibcon#wrote, iclass 12, count 0 2006.257.02:34:28.89#ibcon#about to read 3, iclass 12, count 0 2006.257.02:34:28.92#ibcon#read 3, iclass 12, count 0 2006.257.02:34:28.92#ibcon#about to read 4, iclass 12, count 0 2006.257.02:34:28.92#ibcon#read 4, iclass 12, count 0 2006.257.02:34:28.92#ibcon#about to read 5, iclass 12, count 0 2006.257.02:34:28.92#ibcon#read 5, iclass 12, count 0 2006.257.02:34:28.92#ibcon#about to read 6, iclass 12, count 0 2006.257.02:34:28.92#ibcon#read 6, iclass 12, count 0 2006.257.02:34:28.92#ibcon#end of sib2, iclass 12, count 0 2006.257.02:34:28.92#ibcon#*after write, iclass 12, count 0 2006.257.02:34:28.92#ibcon#*before return 0, iclass 12, count 0 2006.257.02:34:28.92#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:28.92#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:28.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:34:28.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:34:28.92$vck44/valo=4,624.99 2006.257.02:34:28.92#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.02:34:28.92#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.02:34:28.92#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:28.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:28.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:28.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:28.92#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:34:28.92#ibcon#first serial, iclass 14, count 0 2006.257.02:34:28.92#ibcon#enter sib2, iclass 14, count 0 2006.257.02:34:28.92#ibcon#flushed, iclass 14, count 0 2006.257.02:34:28.92#ibcon#about to write, iclass 14, count 0 2006.257.02:34:28.92#ibcon#wrote, iclass 14, count 0 2006.257.02:34:28.92#ibcon#about to read 3, iclass 14, count 0 2006.257.02:34:28.95#ibcon#read 3, iclass 14, count 0 2006.257.02:34:28.95#ibcon#about to read 4, iclass 14, count 0 2006.257.02:34:28.95#ibcon#read 4, iclass 14, count 0 2006.257.02:34:28.95#ibcon#about to read 5, iclass 14, count 0 2006.257.02:34:28.95#ibcon#read 5, iclass 14, count 0 2006.257.02:34:28.95#ibcon#about to read 6, iclass 14, count 0 2006.257.02:34:28.95#ibcon#read 6, iclass 14, count 0 2006.257.02:34:28.95#ibcon#end of sib2, iclass 14, count 0 2006.257.02:34:28.95#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:34:28.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:34:28.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:34:28.95#ibcon#*before write, iclass 14, count 0 2006.257.02:34:28.95#ibcon#enter sib2, iclass 14, count 0 2006.257.02:34:28.95#ibcon#flushed, iclass 14, count 0 2006.257.02:34:28.95#ibcon#about to write, iclass 14, count 0 2006.257.02:34:28.95#ibcon#wrote, iclass 14, count 0 2006.257.02:34:28.95#ibcon#about to read 3, iclass 14, count 0 2006.257.02:34:28.99#ibcon#read 3, iclass 14, count 0 2006.257.02:34:28.99#ibcon#about to read 4, iclass 14, count 0 2006.257.02:34:28.99#ibcon#read 4, iclass 14, count 0 2006.257.02:34:28.99#ibcon#about to read 5, iclass 14, count 0 2006.257.02:34:28.99#ibcon#read 5, iclass 14, count 0 2006.257.02:34:28.99#ibcon#about to read 6, iclass 14, count 0 2006.257.02:34:28.99#ibcon#read 6, iclass 14, count 0 2006.257.02:34:28.99#ibcon#end of sib2, iclass 14, count 0 2006.257.02:34:28.99#ibcon#*after write, iclass 14, count 0 2006.257.02:34:28.99#ibcon#*before return 0, iclass 14, count 0 2006.257.02:34:28.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:28.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:28.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:34:28.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:34:28.99$vck44/va=4,7 2006.257.02:34:28.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.02:34:28.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.02:34:28.99#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:28.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:29.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:29.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:29.04#ibcon#enter wrdev, iclass 16, count 2 2006.257.02:34:29.04#ibcon#first serial, iclass 16, count 2 2006.257.02:34:29.04#ibcon#enter sib2, iclass 16, count 2 2006.257.02:34:29.04#ibcon#flushed, iclass 16, count 2 2006.257.02:34:29.04#ibcon#about to write, iclass 16, count 2 2006.257.02:34:29.04#ibcon#wrote, iclass 16, count 2 2006.257.02:34:29.04#ibcon#about to read 3, iclass 16, count 2 2006.257.02:34:29.06#ibcon#read 3, iclass 16, count 2 2006.257.02:34:29.06#ibcon#about to read 4, iclass 16, count 2 2006.257.02:34:29.06#ibcon#read 4, iclass 16, count 2 2006.257.02:34:29.06#ibcon#about to read 5, iclass 16, count 2 2006.257.02:34:29.06#ibcon#read 5, iclass 16, count 2 2006.257.02:34:29.06#ibcon#about to read 6, iclass 16, count 2 2006.257.02:34:29.06#ibcon#read 6, iclass 16, count 2 2006.257.02:34:29.06#ibcon#end of sib2, iclass 16, count 2 2006.257.02:34:29.06#ibcon#*mode == 0, iclass 16, count 2 2006.257.02:34:29.06#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.02:34:29.06#ibcon#[25=AT04-07\r\n] 2006.257.02:34:29.06#ibcon#*before write, iclass 16, count 2 2006.257.02:34:29.06#ibcon#enter sib2, iclass 16, count 2 2006.257.02:34:29.06#ibcon#flushed, iclass 16, count 2 2006.257.02:34:29.06#ibcon#about to write, iclass 16, count 2 2006.257.02:34:29.06#ibcon#wrote, iclass 16, count 2 2006.257.02:34:29.06#ibcon#about to read 3, iclass 16, count 2 2006.257.02:34:29.09#ibcon#read 3, iclass 16, count 2 2006.257.02:34:29.09#ibcon#about to read 4, iclass 16, count 2 2006.257.02:34:29.09#ibcon#read 4, iclass 16, count 2 2006.257.02:34:29.09#ibcon#about to read 5, iclass 16, count 2 2006.257.02:34:29.09#ibcon#read 5, iclass 16, count 2 2006.257.02:34:29.09#ibcon#about to read 6, iclass 16, count 2 2006.257.02:34:29.09#ibcon#read 6, iclass 16, count 2 2006.257.02:34:29.09#ibcon#end of sib2, iclass 16, count 2 2006.257.02:34:29.09#ibcon#*after write, iclass 16, count 2 2006.257.02:34:29.09#ibcon#*before return 0, iclass 16, count 2 2006.257.02:34:29.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:29.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:29.09#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.02:34:29.09#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:29.09#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:29.21#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:29.21#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:29.21#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:34:29.21#ibcon#first serial, iclass 16, count 0 2006.257.02:34:29.21#ibcon#enter sib2, iclass 16, count 0 2006.257.02:34:29.21#ibcon#flushed, iclass 16, count 0 2006.257.02:34:29.21#ibcon#about to write, iclass 16, count 0 2006.257.02:34:29.21#ibcon#wrote, iclass 16, count 0 2006.257.02:34:29.21#ibcon#about to read 3, iclass 16, count 0 2006.257.02:34:29.23#ibcon#read 3, iclass 16, count 0 2006.257.02:34:29.23#ibcon#about to read 4, iclass 16, count 0 2006.257.02:34:29.23#ibcon#read 4, iclass 16, count 0 2006.257.02:34:29.23#ibcon#about to read 5, iclass 16, count 0 2006.257.02:34:29.23#ibcon#read 5, iclass 16, count 0 2006.257.02:34:29.23#ibcon#about to read 6, iclass 16, count 0 2006.257.02:34:29.23#ibcon#read 6, iclass 16, count 0 2006.257.02:34:29.23#ibcon#end of sib2, iclass 16, count 0 2006.257.02:34:29.23#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:34:29.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:34:29.23#ibcon#[25=USB\r\n] 2006.257.02:34:29.23#ibcon#*before write, iclass 16, count 0 2006.257.02:34:29.23#ibcon#enter sib2, iclass 16, count 0 2006.257.02:34:29.23#ibcon#flushed, iclass 16, count 0 2006.257.02:34:29.23#ibcon#about to write, iclass 16, count 0 2006.257.02:34:29.23#ibcon#wrote, iclass 16, count 0 2006.257.02:34:29.23#ibcon#about to read 3, iclass 16, count 0 2006.257.02:34:29.26#ibcon#read 3, iclass 16, count 0 2006.257.02:34:29.26#ibcon#about to read 4, iclass 16, count 0 2006.257.02:34:29.26#ibcon#read 4, iclass 16, count 0 2006.257.02:34:29.26#ibcon#about to read 5, iclass 16, count 0 2006.257.02:34:29.26#ibcon#read 5, iclass 16, count 0 2006.257.02:34:29.26#ibcon#about to read 6, iclass 16, count 0 2006.257.02:34:29.26#ibcon#read 6, iclass 16, count 0 2006.257.02:34:29.26#ibcon#end of sib2, iclass 16, count 0 2006.257.02:34:29.26#ibcon#*after write, iclass 16, count 0 2006.257.02:34:29.26#ibcon#*before return 0, iclass 16, count 0 2006.257.02:34:29.26#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:29.26#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:29.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:34:29.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:34:29.26$vck44/valo=5,734.99 2006.257.02:34:29.26#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.02:34:29.26#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.02:34:29.26#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:29.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:29.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:29.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:29.26#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:34:29.26#ibcon#first serial, iclass 18, count 0 2006.257.02:34:29.26#ibcon#enter sib2, iclass 18, count 0 2006.257.02:34:29.26#ibcon#flushed, iclass 18, count 0 2006.257.02:34:29.26#ibcon#about to write, iclass 18, count 0 2006.257.02:34:29.26#ibcon#wrote, iclass 18, count 0 2006.257.02:34:29.26#ibcon#about to read 3, iclass 18, count 0 2006.257.02:34:29.28#ibcon#read 3, iclass 18, count 0 2006.257.02:34:29.28#ibcon#about to read 4, iclass 18, count 0 2006.257.02:34:29.28#ibcon#read 4, iclass 18, count 0 2006.257.02:34:29.28#ibcon#about to read 5, iclass 18, count 0 2006.257.02:34:29.28#ibcon#read 5, iclass 18, count 0 2006.257.02:34:29.28#ibcon#about to read 6, iclass 18, count 0 2006.257.02:34:29.28#ibcon#read 6, iclass 18, count 0 2006.257.02:34:29.28#ibcon#end of sib2, iclass 18, count 0 2006.257.02:34:29.28#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:34:29.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:34:29.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:34:29.28#ibcon#*before write, iclass 18, count 0 2006.257.02:34:29.28#ibcon#enter sib2, iclass 18, count 0 2006.257.02:34:29.28#ibcon#flushed, iclass 18, count 0 2006.257.02:34:29.28#ibcon#about to write, iclass 18, count 0 2006.257.02:34:29.28#ibcon#wrote, iclass 18, count 0 2006.257.02:34:29.28#ibcon#about to read 3, iclass 18, count 0 2006.257.02:34:29.32#ibcon#read 3, iclass 18, count 0 2006.257.02:34:29.32#ibcon#about to read 4, iclass 18, count 0 2006.257.02:34:29.32#ibcon#read 4, iclass 18, count 0 2006.257.02:34:29.32#ibcon#about to read 5, iclass 18, count 0 2006.257.02:34:29.32#ibcon#read 5, iclass 18, count 0 2006.257.02:34:29.32#ibcon#about to read 6, iclass 18, count 0 2006.257.02:34:29.32#ibcon#read 6, iclass 18, count 0 2006.257.02:34:29.32#ibcon#end of sib2, iclass 18, count 0 2006.257.02:34:29.32#ibcon#*after write, iclass 18, count 0 2006.257.02:34:29.32#ibcon#*before return 0, iclass 18, count 0 2006.257.02:34:29.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:29.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:29.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:34:29.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:34:29.32$vck44/va=5,4 2006.257.02:34:29.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.02:34:29.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.02:34:29.32#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:29.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:29.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:29.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:29.38#ibcon#enter wrdev, iclass 20, count 2 2006.257.02:34:29.38#ibcon#first serial, iclass 20, count 2 2006.257.02:34:29.38#ibcon#enter sib2, iclass 20, count 2 2006.257.02:34:29.38#ibcon#flushed, iclass 20, count 2 2006.257.02:34:29.38#ibcon#about to write, iclass 20, count 2 2006.257.02:34:29.38#ibcon#wrote, iclass 20, count 2 2006.257.02:34:29.38#ibcon#about to read 3, iclass 20, count 2 2006.257.02:34:29.40#ibcon#read 3, iclass 20, count 2 2006.257.02:34:29.40#ibcon#about to read 4, iclass 20, count 2 2006.257.02:34:29.40#ibcon#read 4, iclass 20, count 2 2006.257.02:34:29.40#ibcon#about to read 5, iclass 20, count 2 2006.257.02:34:29.40#ibcon#read 5, iclass 20, count 2 2006.257.02:34:29.40#ibcon#about to read 6, iclass 20, count 2 2006.257.02:34:29.40#ibcon#read 6, iclass 20, count 2 2006.257.02:34:29.40#ibcon#end of sib2, iclass 20, count 2 2006.257.02:34:29.40#ibcon#*mode == 0, iclass 20, count 2 2006.257.02:34:29.40#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.02:34:29.40#ibcon#[25=AT05-04\r\n] 2006.257.02:34:29.40#ibcon#*before write, iclass 20, count 2 2006.257.02:34:29.40#ibcon#enter sib2, iclass 20, count 2 2006.257.02:34:29.40#ibcon#flushed, iclass 20, count 2 2006.257.02:34:29.40#ibcon#about to write, iclass 20, count 2 2006.257.02:34:29.40#ibcon#wrote, iclass 20, count 2 2006.257.02:34:29.40#ibcon#about to read 3, iclass 20, count 2 2006.257.02:34:29.43#ibcon#read 3, iclass 20, count 2 2006.257.02:34:29.43#ibcon#about to read 4, iclass 20, count 2 2006.257.02:34:29.43#ibcon#read 4, iclass 20, count 2 2006.257.02:34:29.43#ibcon#about to read 5, iclass 20, count 2 2006.257.02:34:29.43#ibcon#read 5, iclass 20, count 2 2006.257.02:34:29.43#ibcon#about to read 6, iclass 20, count 2 2006.257.02:34:29.43#ibcon#read 6, iclass 20, count 2 2006.257.02:34:29.43#ibcon#end of sib2, iclass 20, count 2 2006.257.02:34:29.43#ibcon#*after write, iclass 20, count 2 2006.257.02:34:29.43#ibcon#*before return 0, iclass 20, count 2 2006.257.02:34:29.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:29.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:29.43#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.02:34:29.43#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:29.43#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:29.55#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:29.55#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:29.55#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:34:29.55#ibcon#first serial, iclass 20, count 0 2006.257.02:34:29.55#ibcon#enter sib2, iclass 20, count 0 2006.257.02:34:29.55#ibcon#flushed, iclass 20, count 0 2006.257.02:34:29.55#ibcon#about to write, iclass 20, count 0 2006.257.02:34:29.55#ibcon#wrote, iclass 20, count 0 2006.257.02:34:29.55#ibcon#about to read 3, iclass 20, count 0 2006.257.02:34:29.57#ibcon#read 3, iclass 20, count 0 2006.257.02:34:29.57#ibcon#about to read 4, iclass 20, count 0 2006.257.02:34:29.57#ibcon#read 4, iclass 20, count 0 2006.257.02:34:29.57#ibcon#about to read 5, iclass 20, count 0 2006.257.02:34:29.57#ibcon#read 5, iclass 20, count 0 2006.257.02:34:29.57#ibcon#about to read 6, iclass 20, count 0 2006.257.02:34:29.57#ibcon#read 6, iclass 20, count 0 2006.257.02:34:29.57#ibcon#end of sib2, iclass 20, count 0 2006.257.02:34:29.57#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:34:29.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:34:29.57#ibcon#[25=USB\r\n] 2006.257.02:34:29.57#ibcon#*before write, iclass 20, count 0 2006.257.02:34:29.57#ibcon#enter sib2, iclass 20, count 0 2006.257.02:34:29.57#ibcon#flushed, iclass 20, count 0 2006.257.02:34:29.57#ibcon#about to write, iclass 20, count 0 2006.257.02:34:29.57#ibcon#wrote, iclass 20, count 0 2006.257.02:34:29.57#ibcon#about to read 3, iclass 20, count 0 2006.257.02:34:29.60#ibcon#read 3, iclass 20, count 0 2006.257.02:34:29.60#ibcon#about to read 4, iclass 20, count 0 2006.257.02:34:29.60#ibcon#read 4, iclass 20, count 0 2006.257.02:34:29.60#ibcon#about to read 5, iclass 20, count 0 2006.257.02:34:29.60#ibcon#read 5, iclass 20, count 0 2006.257.02:34:29.60#ibcon#about to read 6, iclass 20, count 0 2006.257.02:34:29.60#ibcon#read 6, iclass 20, count 0 2006.257.02:34:29.60#ibcon#end of sib2, iclass 20, count 0 2006.257.02:34:29.60#ibcon#*after write, iclass 20, count 0 2006.257.02:34:29.60#ibcon#*before return 0, iclass 20, count 0 2006.257.02:34:29.60#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:29.60#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:29.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:34:29.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:34:29.60$vck44/valo=6,814.99 2006.257.02:34:29.60#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.02:34:29.60#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.02:34:29.60#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:29.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:29.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:29.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:29.60#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:34:29.60#ibcon#first serial, iclass 22, count 0 2006.257.02:34:29.60#ibcon#enter sib2, iclass 22, count 0 2006.257.02:34:29.60#ibcon#flushed, iclass 22, count 0 2006.257.02:34:29.60#ibcon#about to write, iclass 22, count 0 2006.257.02:34:29.60#ibcon#wrote, iclass 22, count 0 2006.257.02:34:29.60#ibcon#about to read 3, iclass 22, count 0 2006.257.02:34:29.62#ibcon#read 3, iclass 22, count 0 2006.257.02:34:29.62#ibcon#about to read 4, iclass 22, count 0 2006.257.02:34:29.62#ibcon#read 4, iclass 22, count 0 2006.257.02:34:29.62#ibcon#about to read 5, iclass 22, count 0 2006.257.02:34:29.62#ibcon#read 5, iclass 22, count 0 2006.257.02:34:29.62#ibcon#about to read 6, iclass 22, count 0 2006.257.02:34:29.62#ibcon#read 6, iclass 22, count 0 2006.257.02:34:29.62#ibcon#end of sib2, iclass 22, count 0 2006.257.02:34:29.62#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:34:29.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:34:29.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:34:29.62#ibcon#*before write, iclass 22, count 0 2006.257.02:34:29.62#ibcon#enter sib2, iclass 22, count 0 2006.257.02:34:29.62#ibcon#flushed, iclass 22, count 0 2006.257.02:34:29.62#ibcon#about to write, iclass 22, count 0 2006.257.02:34:29.62#ibcon#wrote, iclass 22, count 0 2006.257.02:34:29.62#ibcon#about to read 3, iclass 22, count 0 2006.257.02:34:29.66#ibcon#read 3, iclass 22, count 0 2006.257.02:34:29.66#ibcon#about to read 4, iclass 22, count 0 2006.257.02:34:29.66#ibcon#read 4, iclass 22, count 0 2006.257.02:34:29.66#ibcon#about to read 5, iclass 22, count 0 2006.257.02:34:29.66#ibcon#read 5, iclass 22, count 0 2006.257.02:34:29.66#ibcon#about to read 6, iclass 22, count 0 2006.257.02:34:29.66#ibcon#read 6, iclass 22, count 0 2006.257.02:34:29.66#ibcon#end of sib2, iclass 22, count 0 2006.257.02:34:29.66#ibcon#*after write, iclass 22, count 0 2006.257.02:34:29.66#ibcon#*before return 0, iclass 22, count 0 2006.257.02:34:29.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:29.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:29.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:34:29.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:34:29.66$vck44/va=6,4 2006.257.02:34:29.66#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.02:34:29.66#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.02:34:29.66#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:29.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:29.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:29.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:29.72#ibcon#enter wrdev, iclass 24, count 2 2006.257.02:34:29.72#ibcon#first serial, iclass 24, count 2 2006.257.02:34:29.72#ibcon#enter sib2, iclass 24, count 2 2006.257.02:34:29.72#ibcon#flushed, iclass 24, count 2 2006.257.02:34:29.72#ibcon#about to write, iclass 24, count 2 2006.257.02:34:29.72#ibcon#wrote, iclass 24, count 2 2006.257.02:34:29.72#ibcon#about to read 3, iclass 24, count 2 2006.257.02:34:29.74#ibcon#read 3, iclass 24, count 2 2006.257.02:34:29.74#ibcon#about to read 4, iclass 24, count 2 2006.257.02:34:29.74#ibcon#read 4, iclass 24, count 2 2006.257.02:34:29.74#ibcon#about to read 5, iclass 24, count 2 2006.257.02:34:29.74#ibcon#read 5, iclass 24, count 2 2006.257.02:34:29.74#ibcon#about to read 6, iclass 24, count 2 2006.257.02:34:29.74#ibcon#read 6, iclass 24, count 2 2006.257.02:34:29.74#ibcon#end of sib2, iclass 24, count 2 2006.257.02:34:29.74#ibcon#*mode == 0, iclass 24, count 2 2006.257.02:34:29.74#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.02:34:29.74#ibcon#[25=AT06-04\r\n] 2006.257.02:34:29.74#ibcon#*before write, iclass 24, count 2 2006.257.02:34:29.74#ibcon#enter sib2, iclass 24, count 2 2006.257.02:34:29.74#ibcon#flushed, iclass 24, count 2 2006.257.02:34:29.74#ibcon#about to write, iclass 24, count 2 2006.257.02:34:29.74#ibcon#wrote, iclass 24, count 2 2006.257.02:34:29.74#ibcon#about to read 3, iclass 24, count 2 2006.257.02:34:29.77#ibcon#read 3, iclass 24, count 2 2006.257.02:34:29.77#ibcon#about to read 4, iclass 24, count 2 2006.257.02:34:29.77#ibcon#read 4, iclass 24, count 2 2006.257.02:34:29.77#ibcon#about to read 5, iclass 24, count 2 2006.257.02:34:29.77#ibcon#read 5, iclass 24, count 2 2006.257.02:34:29.77#ibcon#about to read 6, iclass 24, count 2 2006.257.02:34:29.77#ibcon#read 6, iclass 24, count 2 2006.257.02:34:29.77#ibcon#end of sib2, iclass 24, count 2 2006.257.02:34:29.77#ibcon#*after write, iclass 24, count 2 2006.257.02:34:29.77#ibcon#*before return 0, iclass 24, count 2 2006.257.02:34:29.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:29.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:29.77#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.02:34:29.77#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:29.77#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:29.89#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:29.89#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:29.89#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:34:29.89#ibcon#first serial, iclass 24, count 0 2006.257.02:34:29.89#ibcon#enter sib2, iclass 24, count 0 2006.257.02:34:29.89#ibcon#flushed, iclass 24, count 0 2006.257.02:34:29.89#ibcon#about to write, iclass 24, count 0 2006.257.02:34:29.89#ibcon#wrote, iclass 24, count 0 2006.257.02:34:29.89#ibcon#about to read 3, iclass 24, count 0 2006.257.02:34:29.91#ibcon#read 3, iclass 24, count 0 2006.257.02:34:29.91#ibcon#about to read 4, iclass 24, count 0 2006.257.02:34:29.91#ibcon#read 4, iclass 24, count 0 2006.257.02:34:29.91#ibcon#about to read 5, iclass 24, count 0 2006.257.02:34:29.91#ibcon#read 5, iclass 24, count 0 2006.257.02:34:29.91#ibcon#about to read 6, iclass 24, count 0 2006.257.02:34:29.91#ibcon#read 6, iclass 24, count 0 2006.257.02:34:29.91#ibcon#end of sib2, iclass 24, count 0 2006.257.02:34:29.91#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:34:29.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:34:29.91#ibcon#[25=USB\r\n] 2006.257.02:34:29.91#ibcon#*before write, iclass 24, count 0 2006.257.02:34:29.91#ibcon#enter sib2, iclass 24, count 0 2006.257.02:34:29.91#ibcon#flushed, iclass 24, count 0 2006.257.02:34:29.91#ibcon#about to write, iclass 24, count 0 2006.257.02:34:29.91#ibcon#wrote, iclass 24, count 0 2006.257.02:34:29.91#ibcon#about to read 3, iclass 24, count 0 2006.257.02:34:29.94#ibcon#read 3, iclass 24, count 0 2006.257.02:34:29.94#ibcon#about to read 4, iclass 24, count 0 2006.257.02:34:29.94#ibcon#read 4, iclass 24, count 0 2006.257.02:34:29.94#ibcon#about to read 5, iclass 24, count 0 2006.257.02:34:29.94#ibcon#read 5, iclass 24, count 0 2006.257.02:34:29.94#ibcon#about to read 6, iclass 24, count 0 2006.257.02:34:29.94#ibcon#read 6, iclass 24, count 0 2006.257.02:34:29.94#ibcon#end of sib2, iclass 24, count 0 2006.257.02:34:29.94#ibcon#*after write, iclass 24, count 0 2006.257.02:34:29.94#ibcon#*before return 0, iclass 24, count 0 2006.257.02:34:29.94#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:29.94#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:29.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:34:29.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:34:29.94$vck44/valo=7,864.99 2006.257.02:34:29.94#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.02:34:29.94#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.02:34:29.94#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:29.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:29.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:29.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:29.94#ibcon#enter wrdev, iclass 26, count 0 2006.257.02:34:29.94#ibcon#first serial, iclass 26, count 0 2006.257.02:34:29.94#ibcon#enter sib2, iclass 26, count 0 2006.257.02:34:29.94#ibcon#flushed, iclass 26, count 0 2006.257.02:34:29.94#ibcon#about to write, iclass 26, count 0 2006.257.02:34:29.94#ibcon#wrote, iclass 26, count 0 2006.257.02:34:29.94#ibcon#about to read 3, iclass 26, count 0 2006.257.02:34:29.96#ibcon#read 3, iclass 26, count 0 2006.257.02:34:29.96#ibcon#about to read 4, iclass 26, count 0 2006.257.02:34:29.96#ibcon#read 4, iclass 26, count 0 2006.257.02:34:29.96#ibcon#about to read 5, iclass 26, count 0 2006.257.02:34:29.96#ibcon#read 5, iclass 26, count 0 2006.257.02:34:29.96#ibcon#about to read 6, iclass 26, count 0 2006.257.02:34:29.96#ibcon#read 6, iclass 26, count 0 2006.257.02:34:29.96#ibcon#end of sib2, iclass 26, count 0 2006.257.02:34:29.96#ibcon#*mode == 0, iclass 26, count 0 2006.257.02:34:29.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.02:34:29.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:34:29.96#ibcon#*before write, iclass 26, count 0 2006.257.02:34:29.96#ibcon#enter sib2, iclass 26, count 0 2006.257.02:34:29.96#ibcon#flushed, iclass 26, count 0 2006.257.02:34:29.96#ibcon#about to write, iclass 26, count 0 2006.257.02:34:29.96#ibcon#wrote, iclass 26, count 0 2006.257.02:34:29.96#ibcon#about to read 3, iclass 26, count 0 2006.257.02:34:30.00#ibcon#read 3, iclass 26, count 0 2006.257.02:34:30.00#ibcon#about to read 4, iclass 26, count 0 2006.257.02:34:30.00#ibcon#read 4, iclass 26, count 0 2006.257.02:34:30.00#ibcon#about to read 5, iclass 26, count 0 2006.257.02:34:30.00#ibcon#read 5, iclass 26, count 0 2006.257.02:34:30.00#ibcon#about to read 6, iclass 26, count 0 2006.257.02:34:30.00#ibcon#read 6, iclass 26, count 0 2006.257.02:34:30.00#ibcon#end of sib2, iclass 26, count 0 2006.257.02:34:30.00#ibcon#*after write, iclass 26, count 0 2006.257.02:34:30.00#ibcon#*before return 0, iclass 26, count 0 2006.257.02:34:30.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:30.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:30.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.02:34:30.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.02:34:30.00$vck44/va=7,4 2006.257.02:34:30.00#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.02:34:30.00#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.02:34:30.00#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:30.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:30.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:30.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:30.06#ibcon#enter wrdev, iclass 28, count 2 2006.257.02:34:30.06#ibcon#first serial, iclass 28, count 2 2006.257.02:34:30.06#ibcon#enter sib2, iclass 28, count 2 2006.257.02:34:30.06#ibcon#flushed, iclass 28, count 2 2006.257.02:34:30.06#ibcon#about to write, iclass 28, count 2 2006.257.02:34:30.06#ibcon#wrote, iclass 28, count 2 2006.257.02:34:30.06#ibcon#about to read 3, iclass 28, count 2 2006.257.02:34:30.08#ibcon#read 3, iclass 28, count 2 2006.257.02:34:30.08#ibcon#about to read 4, iclass 28, count 2 2006.257.02:34:30.08#ibcon#read 4, iclass 28, count 2 2006.257.02:34:30.08#ibcon#about to read 5, iclass 28, count 2 2006.257.02:34:30.08#ibcon#read 5, iclass 28, count 2 2006.257.02:34:30.08#ibcon#about to read 6, iclass 28, count 2 2006.257.02:34:30.08#ibcon#read 6, iclass 28, count 2 2006.257.02:34:30.08#ibcon#end of sib2, iclass 28, count 2 2006.257.02:34:30.08#ibcon#*mode == 0, iclass 28, count 2 2006.257.02:34:30.08#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.02:34:30.08#ibcon#[25=AT07-04\r\n] 2006.257.02:34:30.08#ibcon#*before write, iclass 28, count 2 2006.257.02:34:30.08#ibcon#enter sib2, iclass 28, count 2 2006.257.02:34:30.08#ibcon#flushed, iclass 28, count 2 2006.257.02:34:30.08#ibcon#about to write, iclass 28, count 2 2006.257.02:34:30.08#ibcon#wrote, iclass 28, count 2 2006.257.02:34:30.08#ibcon#about to read 3, iclass 28, count 2 2006.257.02:34:30.11#ibcon#read 3, iclass 28, count 2 2006.257.02:34:30.11#ibcon#about to read 4, iclass 28, count 2 2006.257.02:34:30.11#ibcon#read 4, iclass 28, count 2 2006.257.02:34:30.11#ibcon#about to read 5, iclass 28, count 2 2006.257.02:34:30.11#ibcon#read 5, iclass 28, count 2 2006.257.02:34:30.11#ibcon#about to read 6, iclass 28, count 2 2006.257.02:34:30.11#ibcon#read 6, iclass 28, count 2 2006.257.02:34:30.11#ibcon#end of sib2, iclass 28, count 2 2006.257.02:34:30.11#ibcon#*after write, iclass 28, count 2 2006.257.02:34:30.11#ibcon#*before return 0, iclass 28, count 2 2006.257.02:34:30.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:30.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:30.11#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.02:34:30.11#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:30.11#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:30.23#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:30.23#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:30.23#ibcon#enter wrdev, iclass 28, count 0 2006.257.02:34:30.23#ibcon#first serial, iclass 28, count 0 2006.257.02:34:30.23#ibcon#enter sib2, iclass 28, count 0 2006.257.02:34:30.23#ibcon#flushed, iclass 28, count 0 2006.257.02:34:30.23#ibcon#about to write, iclass 28, count 0 2006.257.02:34:30.23#ibcon#wrote, iclass 28, count 0 2006.257.02:34:30.23#ibcon#about to read 3, iclass 28, count 0 2006.257.02:34:30.25#ibcon#read 3, iclass 28, count 0 2006.257.02:34:30.25#ibcon#about to read 4, iclass 28, count 0 2006.257.02:34:30.25#ibcon#read 4, iclass 28, count 0 2006.257.02:34:30.25#ibcon#about to read 5, iclass 28, count 0 2006.257.02:34:30.25#ibcon#read 5, iclass 28, count 0 2006.257.02:34:30.25#ibcon#about to read 6, iclass 28, count 0 2006.257.02:34:30.25#ibcon#read 6, iclass 28, count 0 2006.257.02:34:30.25#ibcon#end of sib2, iclass 28, count 0 2006.257.02:34:30.25#ibcon#*mode == 0, iclass 28, count 0 2006.257.02:34:30.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.02:34:30.25#ibcon#[25=USB\r\n] 2006.257.02:34:30.25#ibcon#*before write, iclass 28, count 0 2006.257.02:34:30.25#ibcon#enter sib2, iclass 28, count 0 2006.257.02:34:30.25#ibcon#flushed, iclass 28, count 0 2006.257.02:34:30.25#ibcon#about to write, iclass 28, count 0 2006.257.02:34:30.25#ibcon#wrote, iclass 28, count 0 2006.257.02:34:30.25#ibcon#about to read 3, iclass 28, count 0 2006.257.02:34:30.28#ibcon#read 3, iclass 28, count 0 2006.257.02:34:30.28#ibcon#about to read 4, iclass 28, count 0 2006.257.02:34:30.28#ibcon#read 4, iclass 28, count 0 2006.257.02:34:30.28#ibcon#about to read 5, iclass 28, count 0 2006.257.02:34:30.28#ibcon#read 5, iclass 28, count 0 2006.257.02:34:30.28#ibcon#about to read 6, iclass 28, count 0 2006.257.02:34:30.28#ibcon#read 6, iclass 28, count 0 2006.257.02:34:30.28#ibcon#end of sib2, iclass 28, count 0 2006.257.02:34:30.28#ibcon#*after write, iclass 28, count 0 2006.257.02:34:30.28#ibcon#*before return 0, iclass 28, count 0 2006.257.02:34:30.28#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:30.28#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:30.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.02:34:30.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.02:34:30.28$vck44/valo=8,884.99 2006.257.02:34:30.28#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.02:34:30.28#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.02:34:30.28#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:30.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:30.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:30.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:30.28#ibcon#enter wrdev, iclass 30, count 0 2006.257.02:34:30.28#ibcon#first serial, iclass 30, count 0 2006.257.02:34:30.28#ibcon#enter sib2, iclass 30, count 0 2006.257.02:34:30.28#ibcon#flushed, iclass 30, count 0 2006.257.02:34:30.28#ibcon#about to write, iclass 30, count 0 2006.257.02:34:30.28#ibcon#wrote, iclass 30, count 0 2006.257.02:34:30.28#ibcon#about to read 3, iclass 30, count 0 2006.257.02:34:30.30#ibcon#read 3, iclass 30, count 0 2006.257.02:34:30.30#ibcon#about to read 4, iclass 30, count 0 2006.257.02:34:30.30#ibcon#read 4, iclass 30, count 0 2006.257.02:34:30.30#ibcon#about to read 5, iclass 30, count 0 2006.257.02:34:30.30#ibcon#read 5, iclass 30, count 0 2006.257.02:34:30.30#ibcon#about to read 6, iclass 30, count 0 2006.257.02:34:30.30#ibcon#read 6, iclass 30, count 0 2006.257.02:34:30.30#ibcon#end of sib2, iclass 30, count 0 2006.257.02:34:30.30#ibcon#*mode == 0, iclass 30, count 0 2006.257.02:34:30.30#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.02:34:30.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:34:30.30#ibcon#*before write, iclass 30, count 0 2006.257.02:34:30.30#ibcon#enter sib2, iclass 30, count 0 2006.257.02:34:30.30#ibcon#flushed, iclass 30, count 0 2006.257.02:34:30.30#ibcon#about to write, iclass 30, count 0 2006.257.02:34:30.30#ibcon#wrote, iclass 30, count 0 2006.257.02:34:30.30#ibcon#about to read 3, iclass 30, count 0 2006.257.02:34:30.34#ibcon#read 3, iclass 30, count 0 2006.257.02:34:30.34#ibcon#about to read 4, iclass 30, count 0 2006.257.02:34:30.34#ibcon#read 4, iclass 30, count 0 2006.257.02:34:30.34#ibcon#about to read 5, iclass 30, count 0 2006.257.02:34:30.34#ibcon#read 5, iclass 30, count 0 2006.257.02:34:30.34#ibcon#about to read 6, iclass 30, count 0 2006.257.02:34:30.34#ibcon#read 6, iclass 30, count 0 2006.257.02:34:30.34#ibcon#end of sib2, iclass 30, count 0 2006.257.02:34:30.34#ibcon#*after write, iclass 30, count 0 2006.257.02:34:30.34#ibcon#*before return 0, iclass 30, count 0 2006.257.02:34:30.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:30.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:30.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.02:34:30.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.02:34:30.34$vck44/va=8,4 2006.257.02:34:30.34#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.02:34:30.34#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.02:34:30.34#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:30.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:30.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:30.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:30.40#ibcon#enter wrdev, iclass 32, count 2 2006.257.02:34:30.40#ibcon#first serial, iclass 32, count 2 2006.257.02:34:30.40#ibcon#enter sib2, iclass 32, count 2 2006.257.02:34:30.40#ibcon#flushed, iclass 32, count 2 2006.257.02:34:30.40#ibcon#about to write, iclass 32, count 2 2006.257.02:34:30.40#ibcon#wrote, iclass 32, count 2 2006.257.02:34:30.40#ibcon#about to read 3, iclass 32, count 2 2006.257.02:34:30.42#ibcon#read 3, iclass 32, count 2 2006.257.02:34:30.42#ibcon#about to read 4, iclass 32, count 2 2006.257.02:34:30.42#ibcon#read 4, iclass 32, count 2 2006.257.02:34:30.42#ibcon#about to read 5, iclass 32, count 2 2006.257.02:34:30.42#ibcon#read 5, iclass 32, count 2 2006.257.02:34:30.42#ibcon#about to read 6, iclass 32, count 2 2006.257.02:34:30.42#ibcon#read 6, iclass 32, count 2 2006.257.02:34:30.42#ibcon#end of sib2, iclass 32, count 2 2006.257.02:34:30.42#ibcon#*mode == 0, iclass 32, count 2 2006.257.02:34:30.42#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.02:34:30.42#ibcon#[25=AT08-04\r\n] 2006.257.02:34:30.42#ibcon#*before write, iclass 32, count 2 2006.257.02:34:30.42#ibcon#enter sib2, iclass 32, count 2 2006.257.02:34:30.42#ibcon#flushed, iclass 32, count 2 2006.257.02:34:30.42#ibcon#about to write, iclass 32, count 2 2006.257.02:34:30.42#ibcon#wrote, iclass 32, count 2 2006.257.02:34:30.42#ibcon#about to read 3, iclass 32, count 2 2006.257.02:34:30.45#ibcon#read 3, iclass 32, count 2 2006.257.02:34:30.45#ibcon#about to read 4, iclass 32, count 2 2006.257.02:34:30.45#ibcon#read 4, iclass 32, count 2 2006.257.02:34:30.45#ibcon#about to read 5, iclass 32, count 2 2006.257.02:34:30.45#ibcon#read 5, iclass 32, count 2 2006.257.02:34:30.45#ibcon#about to read 6, iclass 32, count 2 2006.257.02:34:30.45#ibcon#read 6, iclass 32, count 2 2006.257.02:34:30.45#ibcon#end of sib2, iclass 32, count 2 2006.257.02:34:30.45#ibcon#*after write, iclass 32, count 2 2006.257.02:34:30.45#ibcon#*before return 0, iclass 32, count 2 2006.257.02:34:30.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:30.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:30.45#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.02:34:30.45#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:30.45#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:30.57#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:30.57#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:30.57#ibcon#enter wrdev, iclass 32, count 0 2006.257.02:34:30.57#ibcon#first serial, iclass 32, count 0 2006.257.02:34:30.57#ibcon#enter sib2, iclass 32, count 0 2006.257.02:34:30.57#ibcon#flushed, iclass 32, count 0 2006.257.02:34:30.57#ibcon#about to write, iclass 32, count 0 2006.257.02:34:30.57#ibcon#wrote, iclass 32, count 0 2006.257.02:34:30.57#ibcon#about to read 3, iclass 32, count 0 2006.257.02:34:30.59#ibcon#read 3, iclass 32, count 0 2006.257.02:34:30.59#ibcon#about to read 4, iclass 32, count 0 2006.257.02:34:30.59#ibcon#read 4, iclass 32, count 0 2006.257.02:34:30.59#ibcon#about to read 5, iclass 32, count 0 2006.257.02:34:30.59#ibcon#read 5, iclass 32, count 0 2006.257.02:34:30.59#ibcon#about to read 6, iclass 32, count 0 2006.257.02:34:30.59#ibcon#read 6, iclass 32, count 0 2006.257.02:34:30.59#ibcon#end of sib2, iclass 32, count 0 2006.257.02:34:30.59#ibcon#*mode == 0, iclass 32, count 0 2006.257.02:34:30.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.02:34:30.59#ibcon#[25=USB\r\n] 2006.257.02:34:30.59#ibcon#*before write, iclass 32, count 0 2006.257.02:34:30.59#ibcon#enter sib2, iclass 32, count 0 2006.257.02:34:30.59#ibcon#flushed, iclass 32, count 0 2006.257.02:34:30.59#ibcon#about to write, iclass 32, count 0 2006.257.02:34:30.59#ibcon#wrote, iclass 32, count 0 2006.257.02:34:30.59#ibcon#about to read 3, iclass 32, count 0 2006.257.02:34:30.62#ibcon#read 3, iclass 32, count 0 2006.257.02:34:30.62#ibcon#about to read 4, iclass 32, count 0 2006.257.02:34:30.62#ibcon#read 4, iclass 32, count 0 2006.257.02:34:30.62#ibcon#about to read 5, iclass 32, count 0 2006.257.02:34:30.62#ibcon#read 5, iclass 32, count 0 2006.257.02:34:30.62#ibcon#about to read 6, iclass 32, count 0 2006.257.02:34:30.62#ibcon#read 6, iclass 32, count 0 2006.257.02:34:30.62#ibcon#end of sib2, iclass 32, count 0 2006.257.02:34:30.62#ibcon#*after write, iclass 32, count 0 2006.257.02:34:30.62#ibcon#*before return 0, iclass 32, count 0 2006.257.02:34:30.62#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:30.62#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:30.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.02:34:30.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.02:34:30.62$vck44/vblo=1,629.99 2006.257.02:34:30.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.02:34:30.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.02:34:30.62#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:30.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:30.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:30.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:30.62#ibcon#enter wrdev, iclass 34, count 0 2006.257.02:34:30.62#ibcon#first serial, iclass 34, count 0 2006.257.02:34:30.62#ibcon#enter sib2, iclass 34, count 0 2006.257.02:34:30.62#ibcon#flushed, iclass 34, count 0 2006.257.02:34:30.62#ibcon#about to write, iclass 34, count 0 2006.257.02:34:30.62#ibcon#wrote, iclass 34, count 0 2006.257.02:34:30.62#ibcon#about to read 3, iclass 34, count 0 2006.257.02:34:30.65#ibcon#read 3, iclass 34, count 0 2006.257.02:34:30.65#ibcon#about to read 4, iclass 34, count 0 2006.257.02:34:30.65#ibcon#read 4, iclass 34, count 0 2006.257.02:34:30.65#ibcon#about to read 5, iclass 34, count 0 2006.257.02:34:30.65#ibcon#read 5, iclass 34, count 0 2006.257.02:34:30.65#ibcon#about to read 6, iclass 34, count 0 2006.257.02:34:30.65#ibcon#read 6, iclass 34, count 0 2006.257.02:34:30.65#ibcon#end of sib2, iclass 34, count 0 2006.257.02:34:30.65#ibcon#*mode == 0, iclass 34, count 0 2006.257.02:34:30.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.02:34:30.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:34:30.65#ibcon#*before write, iclass 34, count 0 2006.257.02:34:30.65#ibcon#enter sib2, iclass 34, count 0 2006.257.02:34:30.65#ibcon#flushed, iclass 34, count 0 2006.257.02:34:30.65#ibcon#about to write, iclass 34, count 0 2006.257.02:34:30.65#ibcon#wrote, iclass 34, count 0 2006.257.02:34:30.65#ibcon#about to read 3, iclass 34, count 0 2006.257.02:34:30.69#ibcon#read 3, iclass 34, count 0 2006.257.02:34:30.69#ibcon#about to read 4, iclass 34, count 0 2006.257.02:34:30.69#ibcon#read 4, iclass 34, count 0 2006.257.02:34:30.69#ibcon#about to read 5, iclass 34, count 0 2006.257.02:34:30.69#ibcon#read 5, iclass 34, count 0 2006.257.02:34:30.69#ibcon#about to read 6, iclass 34, count 0 2006.257.02:34:30.69#ibcon#read 6, iclass 34, count 0 2006.257.02:34:30.69#ibcon#end of sib2, iclass 34, count 0 2006.257.02:34:30.69#ibcon#*after write, iclass 34, count 0 2006.257.02:34:30.69#ibcon#*before return 0, iclass 34, count 0 2006.257.02:34:30.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:30.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:30.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.02:34:30.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.02:34:30.69$vck44/vb=1,4 2006.257.02:34:30.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.02:34:30.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.02:34:30.69#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:30.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:34:30.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:34:30.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:34:30.69#ibcon#enter wrdev, iclass 36, count 2 2006.257.02:34:30.69#ibcon#first serial, iclass 36, count 2 2006.257.02:34:30.69#ibcon#enter sib2, iclass 36, count 2 2006.257.02:34:30.69#ibcon#flushed, iclass 36, count 2 2006.257.02:34:30.69#ibcon#about to write, iclass 36, count 2 2006.257.02:34:30.69#ibcon#wrote, iclass 36, count 2 2006.257.02:34:30.69#ibcon#about to read 3, iclass 36, count 2 2006.257.02:34:30.71#ibcon#read 3, iclass 36, count 2 2006.257.02:34:30.71#ibcon#about to read 4, iclass 36, count 2 2006.257.02:34:30.71#ibcon#read 4, iclass 36, count 2 2006.257.02:34:30.71#ibcon#about to read 5, iclass 36, count 2 2006.257.02:34:30.71#ibcon#read 5, iclass 36, count 2 2006.257.02:34:30.71#ibcon#about to read 6, iclass 36, count 2 2006.257.02:34:30.71#ibcon#read 6, iclass 36, count 2 2006.257.02:34:30.71#ibcon#end of sib2, iclass 36, count 2 2006.257.02:34:30.71#ibcon#*mode == 0, iclass 36, count 2 2006.257.02:34:30.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.02:34:30.71#ibcon#[27=AT01-04\r\n] 2006.257.02:34:30.71#ibcon#*before write, iclass 36, count 2 2006.257.02:34:30.71#ibcon#enter sib2, iclass 36, count 2 2006.257.02:34:30.71#ibcon#flushed, iclass 36, count 2 2006.257.02:34:30.71#ibcon#about to write, iclass 36, count 2 2006.257.02:34:30.71#ibcon#wrote, iclass 36, count 2 2006.257.02:34:30.71#ibcon#about to read 3, iclass 36, count 2 2006.257.02:34:30.74#ibcon#read 3, iclass 36, count 2 2006.257.02:34:30.74#ibcon#about to read 4, iclass 36, count 2 2006.257.02:34:30.74#ibcon#read 4, iclass 36, count 2 2006.257.02:34:30.74#ibcon#about to read 5, iclass 36, count 2 2006.257.02:34:30.74#ibcon#read 5, iclass 36, count 2 2006.257.02:34:30.74#ibcon#about to read 6, iclass 36, count 2 2006.257.02:34:30.74#ibcon#read 6, iclass 36, count 2 2006.257.02:34:30.74#ibcon#end of sib2, iclass 36, count 2 2006.257.02:34:30.74#ibcon#*after write, iclass 36, count 2 2006.257.02:34:30.74#ibcon#*before return 0, iclass 36, count 2 2006.257.02:34:30.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:34:30.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.02:34:30.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.02:34:30.74#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:30.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:34:30.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:34:30.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:34:30.86#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:34:30.86#ibcon#first serial, iclass 36, count 0 2006.257.02:34:30.86#ibcon#enter sib2, iclass 36, count 0 2006.257.02:34:30.86#ibcon#flushed, iclass 36, count 0 2006.257.02:34:30.86#ibcon#about to write, iclass 36, count 0 2006.257.02:34:30.86#ibcon#wrote, iclass 36, count 0 2006.257.02:34:30.86#ibcon#about to read 3, iclass 36, count 0 2006.257.02:34:30.88#ibcon#read 3, iclass 36, count 0 2006.257.02:34:30.88#ibcon#about to read 4, iclass 36, count 0 2006.257.02:34:30.88#ibcon#read 4, iclass 36, count 0 2006.257.02:34:30.88#ibcon#about to read 5, iclass 36, count 0 2006.257.02:34:30.88#ibcon#read 5, iclass 36, count 0 2006.257.02:34:30.88#ibcon#about to read 6, iclass 36, count 0 2006.257.02:34:30.88#ibcon#read 6, iclass 36, count 0 2006.257.02:34:30.88#ibcon#end of sib2, iclass 36, count 0 2006.257.02:34:30.88#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:34:30.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:34:30.88#ibcon#[27=USB\r\n] 2006.257.02:34:30.88#ibcon#*before write, iclass 36, count 0 2006.257.02:34:30.88#ibcon#enter sib2, iclass 36, count 0 2006.257.02:34:30.88#ibcon#flushed, iclass 36, count 0 2006.257.02:34:30.88#ibcon#about to write, iclass 36, count 0 2006.257.02:34:30.88#ibcon#wrote, iclass 36, count 0 2006.257.02:34:30.88#ibcon#about to read 3, iclass 36, count 0 2006.257.02:34:30.91#ibcon#read 3, iclass 36, count 0 2006.257.02:34:30.91#ibcon#about to read 4, iclass 36, count 0 2006.257.02:34:30.91#ibcon#read 4, iclass 36, count 0 2006.257.02:34:30.91#ibcon#about to read 5, iclass 36, count 0 2006.257.02:34:30.91#ibcon#read 5, iclass 36, count 0 2006.257.02:34:30.91#ibcon#about to read 6, iclass 36, count 0 2006.257.02:34:30.91#ibcon#read 6, iclass 36, count 0 2006.257.02:34:30.91#ibcon#end of sib2, iclass 36, count 0 2006.257.02:34:30.91#ibcon#*after write, iclass 36, count 0 2006.257.02:34:30.91#ibcon#*before return 0, iclass 36, count 0 2006.257.02:34:30.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:34:30.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.02:34:30.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:34:30.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:34:30.91$vck44/vblo=2,634.99 2006.257.02:34:30.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.02:34:30.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.02:34:30.91#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:30.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:30.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:30.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:30.91#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:34:30.91#ibcon#first serial, iclass 38, count 0 2006.257.02:34:30.91#ibcon#enter sib2, iclass 38, count 0 2006.257.02:34:30.91#ibcon#flushed, iclass 38, count 0 2006.257.02:34:30.91#ibcon#about to write, iclass 38, count 0 2006.257.02:34:30.91#ibcon#wrote, iclass 38, count 0 2006.257.02:34:30.91#ibcon#about to read 3, iclass 38, count 0 2006.257.02:34:30.93#ibcon#read 3, iclass 38, count 0 2006.257.02:34:30.93#ibcon#about to read 4, iclass 38, count 0 2006.257.02:34:30.93#ibcon#read 4, iclass 38, count 0 2006.257.02:34:30.93#ibcon#about to read 5, iclass 38, count 0 2006.257.02:34:30.93#ibcon#read 5, iclass 38, count 0 2006.257.02:34:30.93#ibcon#about to read 6, iclass 38, count 0 2006.257.02:34:30.93#ibcon#read 6, iclass 38, count 0 2006.257.02:34:30.93#ibcon#end of sib2, iclass 38, count 0 2006.257.02:34:30.93#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:34:30.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:34:30.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:34:30.93#ibcon#*before write, iclass 38, count 0 2006.257.02:34:30.93#ibcon#enter sib2, iclass 38, count 0 2006.257.02:34:30.93#ibcon#flushed, iclass 38, count 0 2006.257.02:34:30.93#ibcon#about to write, iclass 38, count 0 2006.257.02:34:30.93#ibcon#wrote, iclass 38, count 0 2006.257.02:34:30.93#ibcon#about to read 3, iclass 38, count 0 2006.257.02:34:30.97#ibcon#read 3, iclass 38, count 0 2006.257.02:34:30.97#ibcon#about to read 4, iclass 38, count 0 2006.257.02:34:30.97#ibcon#read 4, iclass 38, count 0 2006.257.02:34:30.97#ibcon#about to read 5, iclass 38, count 0 2006.257.02:34:30.97#ibcon#read 5, iclass 38, count 0 2006.257.02:34:30.97#ibcon#about to read 6, iclass 38, count 0 2006.257.02:34:30.97#ibcon#read 6, iclass 38, count 0 2006.257.02:34:30.97#ibcon#end of sib2, iclass 38, count 0 2006.257.02:34:30.97#ibcon#*after write, iclass 38, count 0 2006.257.02:34:30.97#ibcon#*before return 0, iclass 38, count 0 2006.257.02:34:30.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:30.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:34:30.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:34:30.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:34:30.97$vck44/vb=2,5 2006.257.02:34:30.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.02:34:30.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.02:34:30.97#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:30.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:31.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:31.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:31.03#ibcon#enter wrdev, iclass 40, count 2 2006.257.02:34:31.03#ibcon#first serial, iclass 40, count 2 2006.257.02:34:31.03#ibcon#enter sib2, iclass 40, count 2 2006.257.02:34:31.03#ibcon#flushed, iclass 40, count 2 2006.257.02:34:31.03#ibcon#about to write, iclass 40, count 2 2006.257.02:34:31.03#ibcon#wrote, iclass 40, count 2 2006.257.02:34:31.03#ibcon#about to read 3, iclass 40, count 2 2006.257.02:34:31.05#ibcon#read 3, iclass 40, count 2 2006.257.02:34:31.05#ibcon#about to read 4, iclass 40, count 2 2006.257.02:34:31.05#ibcon#read 4, iclass 40, count 2 2006.257.02:34:31.05#ibcon#about to read 5, iclass 40, count 2 2006.257.02:34:31.05#ibcon#read 5, iclass 40, count 2 2006.257.02:34:31.05#ibcon#about to read 6, iclass 40, count 2 2006.257.02:34:31.05#ibcon#read 6, iclass 40, count 2 2006.257.02:34:31.05#ibcon#end of sib2, iclass 40, count 2 2006.257.02:34:31.05#ibcon#*mode == 0, iclass 40, count 2 2006.257.02:34:31.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.02:34:31.05#ibcon#[27=AT02-05\r\n] 2006.257.02:34:31.05#ibcon#*before write, iclass 40, count 2 2006.257.02:34:31.05#ibcon#enter sib2, iclass 40, count 2 2006.257.02:34:31.05#ibcon#flushed, iclass 40, count 2 2006.257.02:34:31.05#ibcon#about to write, iclass 40, count 2 2006.257.02:34:31.05#ibcon#wrote, iclass 40, count 2 2006.257.02:34:31.05#ibcon#about to read 3, iclass 40, count 2 2006.257.02:34:31.06#abcon#<5=/02 2.2 6.0 18.14 971012.3\r\n> 2006.257.02:34:31.08#abcon#{5=INTERFACE CLEAR} 2006.257.02:34:31.08#ibcon#read 3, iclass 40, count 2 2006.257.02:34:31.08#ibcon#about to read 4, iclass 40, count 2 2006.257.02:34:31.08#ibcon#read 4, iclass 40, count 2 2006.257.02:34:31.08#ibcon#about to read 5, iclass 40, count 2 2006.257.02:34:31.08#ibcon#read 5, iclass 40, count 2 2006.257.02:34:31.08#ibcon#about to read 6, iclass 40, count 2 2006.257.02:34:31.08#ibcon#read 6, iclass 40, count 2 2006.257.02:34:31.08#ibcon#end of sib2, iclass 40, count 2 2006.257.02:34:31.08#ibcon#*after write, iclass 40, count 2 2006.257.02:34:31.08#ibcon#*before return 0, iclass 40, count 2 2006.257.02:34:31.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:31.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.02:34:31.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.02:34:31.08#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:31.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:31.14#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:34:31.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:31.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:31.20#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:34:31.20#ibcon#first serial, iclass 40, count 0 2006.257.02:34:31.20#ibcon#enter sib2, iclass 40, count 0 2006.257.02:34:31.20#ibcon#flushed, iclass 40, count 0 2006.257.02:34:31.20#ibcon#about to write, iclass 40, count 0 2006.257.02:34:31.20#ibcon#wrote, iclass 40, count 0 2006.257.02:34:31.20#ibcon#about to read 3, iclass 40, count 0 2006.257.02:34:31.22#ibcon#read 3, iclass 40, count 0 2006.257.02:34:31.22#ibcon#about to read 4, iclass 40, count 0 2006.257.02:34:31.22#ibcon#read 4, iclass 40, count 0 2006.257.02:34:31.22#ibcon#about to read 5, iclass 40, count 0 2006.257.02:34:31.22#ibcon#read 5, iclass 40, count 0 2006.257.02:34:31.22#ibcon#about to read 6, iclass 40, count 0 2006.257.02:34:31.22#ibcon#read 6, iclass 40, count 0 2006.257.02:34:31.22#ibcon#end of sib2, iclass 40, count 0 2006.257.02:34:31.22#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:34:31.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:34:31.22#ibcon#[27=USB\r\n] 2006.257.02:34:31.22#ibcon#*before write, iclass 40, count 0 2006.257.02:34:31.22#ibcon#enter sib2, iclass 40, count 0 2006.257.02:34:31.22#ibcon#flushed, iclass 40, count 0 2006.257.02:34:31.22#ibcon#about to write, iclass 40, count 0 2006.257.02:34:31.22#ibcon#wrote, iclass 40, count 0 2006.257.02:34:31.22#ibcon#about to read 3, iclass 40, count 0 2006.257.02:34:31.25#ibcon#read 3, iclass 40, count 0 2006.257.02:34:31.25#ibcon#about to read 4, iclass 40, count 0 2006.257.02:34:31.25#ibcon#read 4, iclass 40, count 0 2006.257.02:34:31.25#ibcon#about to read 5, iclass 40, count 0 2006.257.02:34:31.25#ibcon#read 5, iclass 40, count 0 2006.257.02:34:31.25#ibcon#about to read 6, iclass 40, count 0 2006.257.02:34:31.25#ibcon#read 6, iclass 40, count 0 2006.257.02:34:31.25#ibcon#end of sib2, iclass 40, count 0 2006.257.02:34:31.25#ibcon#*after write, iclass 40, count 0 2006.257.02:34:31.25#ibcon#*before return 0, iclass 40, count 0 2006.257.02:34:31.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:31.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.02:34:31.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:34:31.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:34:31.25$vck44/vblo=3,649.99 2006.257.02:34:31.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.02:34:31.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.02:34:31.25#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:31.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:31.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:31.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:31.25#ibcon#enter wrdev, iclass 10, count 0 2006.257.02:34:31.25#ibcon#first serial, iclass 10, count 0 2006.257.02:34:31.25#ibcon#enter sib2, iclass 10, count 0 2006.257.02:34:31.25#ibcon#flushed, iclass 10, count 0 2006.257.02:34:31.25#ibcon#about to write, iclass 10, count 0 2006.257.02:34:31.25#ibcon#wrote, iclass 10, count 0 2006.257.02:34:31.25#ibcon#about to read 3, iclass 10, count 0 2006.257.02:34:31.27#ibcon#read 3, iclass 10, count 0 2006.257.02:34:31.27#ibcon#about to read 4, iclass 10, count 0 2006.257.02:34:31.27#ibcon#read 4, iclass 10, count 0 2006.257.02:34:31.27#ibcon#about to read 5, iclass 10, count 0 2006.257.02:34:31.27#ibcon#read 5, iclass 10, count 0 2006.257.02:34:31.27#ibcon#about to read 6, iclass 10, count 0 2006.257.02:34:31.27#ibcon#read 6, iclass 10, count 0 2006.257.02:34:31.27#ibcon#end of sib2, iclass 10, count 0 2006.257.02:34:31.27#ibcon#*mode == 0, iclass 10, count 0 2006.257.02:34:31.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.02:34:31.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:34:31.27#ibcon#*before write, iclass 10, count 0 2006.257.02:34:31.27#ibcon#enter sib2, iclass 10, count 0 2006.257.02:34:31.27#ibcon#flushed, iclass 10, count 0 2006.257.02:34:31.27#ibcon#about to write, iclass 10, count 0 2006.257.02:34:31.27#ibcon#wrote, iclass 10, count 0 2006.257.02:34:31.27#ibcon#about to read 3, iclass 10, count 0 2006.257.02:34:31.31#ibcon#read 3, iclass 10, count 0 2006.257.02:34:31.31#ibcon#about to read 4, iclass 10, count 0 2006.257.02:34:31.31#ibcon#read 4, iclass 10, count 0 2006.257.02:34:31.31#ibcon#about to read 5, iclass 10, count 0 2006.257.02:34:31.31#ibcon#read 5, iclass 10, count 0 2006.257.02:34:31.31#ibcon#about to read 6, iclass 10, count 0 2006.257.02:34:31.31#ibcon#read 6, iclass 10, count 0 2006.257.02:34:31.31#ibcon#end of sib2, iclass 10, count 0 2006.257.02:34:31.31#ibcon#*after write, iclass 10, count 0 2006.257.02:34:31.31#ibcon#*before return 0, iclass 10, count 0 2006.257.02:34:31.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:31.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.02:34:31.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.02:34:31.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.02:34:31.31$vck44/vb=3,4 2006.257.02:34:31.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.02:34:31.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.02:34:31.31#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:31.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:31.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:31.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:31.37#ibcon#enter wrdev, iclass 12, count 2 2006.257.02:34:31.37#ibcon#first serial, iclass 12, count 2 2006.257.02:34:31.37#ibcon#enter sib2, iclass 12, count 2 2006.257.02:34:31.37#ibcon#flushed, iclass 12, count 2 2006.257.02:34:31.37#ibcon#about to write, iclass 12, count 2 2006.257.02:34:31.37#ibcon#wrote, iclass 12, count 2 2006.257.02:34:31.37#ibcon#about to read 3, iclass 12, count 2 2006.257.02:34:31.39#ibcon#read 3, iclass 12, count 2 2006.257.02:34:31.39#ibcon#about to read 4, iclass 12, count 2 2006.257.02:34:31.39#ibcon#read 4, iclass 12, count 2 2006.257.02:34:31.39#ibcon#about to read 5, iclass 12, count 2 2006.257.02:34:31.39#ibcon#read 5, iclass 12, count 2 2006.257.02:34:31.39#ibcon#about to read 6, iclass 12, count 2 2006.257.02:34:31.39#ibcon#read 6, iclass 12, count 2 2006.257.02:34:31.39#ibcon#end of sib2, iclass 12, count 2 2006.257.02:34:31.39#ibcon#*mode == 0, iclass 12, count 2 2006.257.02:34:31.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.02:34:31.39#ibcon#[27=AT03-04\r\n] 2006.257.02:34:31.39#ibcon#*before write, iclass 12, count 2 2006.257.02:34:31.39#ibcon#enter sib2, iclass 12, count 2 2006.257.02:34:31.39#ibcon#flushed, iclass 12, count 2 2006.257.02:34:31.39#ibcon#about to write, iclass 12, count 2 2006.257.02:34:31.39#ibcon#wrote, iclass 12, count 2 2006.257.02:34:31.39#ibcon#about to read 3, iclass 12, count 2 2006.257.02:34:31.42#ibcon#read 3, iclass 12, count 2 2006.257.02:34:31.42#ibcon#about to read 4, iclass 12, count 2 2006.257.02:34:31.42#ibcon#read 4, iclass 12, count 2 2006.257.02:34:31.42#ibcon#about to read 5, iclass 12, count 2 2006.257.02:34:31.42#ibcon#read 5, iclass 12, count 2 2006.257.02:34:31.42#ibcon#about to read 6, iclass 12, count 2 2006.257.02:34:31.42#ibcon#read 6, iclass 12, count 2 2006.257.02:34:31.42#ibcon#end of sib2, iclass 12, count 2 2006.257.02:34:31.42#ibcon#*after write, iclass 12, count 2 2006.257.02:34:31.42#ibcon#*before return 0, iclass 12, count 2 2006.257.02:34:31.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:31.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.02:34:31.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.02:34:31.42#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:31.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:31.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:31.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:31.54#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:34:31.54#ibcon#first serial, iclass 12, count 0 2006.257.02:34:31.54#ibcon#enter sib2, iclass 12, count 0 2006.257.02:34:31.54#ibcon#flushed, iclass 12, count 0 2006.257.02:34:31.54#ibcon#about to write, iclass 12, count 0 2006.257.02:34:31.54#ibcon#wrote, iclass 12, count 0 2006.257.02:34:31.54#ibcon#about to read 3, iclass 12, count 0 2006.257.02:34:31.56#ibcon#read 3, iclass 12, count 0 2006.257.02:34:31.56#ibcon#about to read 4, iclass 12, count 0 2006.257.02:34:31.56#ibcon#read 4, iclass 12, count 0 2006.257.02:34:31.56#ibcon#about to read 5, iclass 12, count 0 2006.257.02:34:31.56#ibcon#read 5, iclass 12, count 0 2006.257.02:34:31.56#ibcon#about to read 6, iclass 12, count 0 2006.257.02:34:31.56#ibcon#read 6, iclass 12, count 0 2006.257.02:34:31.56#ibcon#end of sib2, iclass 12, count 0 2006.257.02:34:31.56#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:34:31.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:34:31.56#ibcon#[27=USB\r\n] 2006.257.02:34:31.56#ibcon#*before write, iclass 12, count 0 2006.257.02:34:31.56#ibcon#enter sib2, iclass 12, count 0 2006.257.02:34:31.56#ibcon#flushed, iclass 12, count 0 2006.257.02:34:31.56#ibcon#about to write, iclass 12, count 0 2006.257.02:34:31.56#ibcon#wrote, iclass 12, count 0 2006.257.02:34:31.56#ibcon#about to read 3, iclass 12, count 0 2006.257.02:34:31.59#ibcon#read 3, iclass 12, count 0 2006.257.02:34:31.59#ibcon#about to read 4, iclass 12, count 0 2006.257.02:34:31.59#ibcon#read 4, iclass 12, count 0 2006.257.02:34:31.59#ibcon#about to read 5, iclass 12, count 0 2006.257.02:34:31.59#ibcon#read 5, iclass 12, count 0 2006.257.02:34:31.59#ibcon#about to read 6, iclass 12, count 0 2006.257.02:34:31.59#ibcon#read 6, iclass 12, count 0 2006.257.02:34:31.59#ibcon#end of sib2, iclass 12, count 0 2006.257.02:34:31.59#ibcon#*after write, iclass 12, count 0 2006.257.02:34:31.59#ibcon#*before return 0, iclass 12, count 0 2006.257.02:34:31.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:31.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.02:34:31.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:34:31.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:34:31.59$vck44/vblo=4,679.99 2006.257.02:34:31.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.02:34:31.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.02:34:31.59#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:31.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:31.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:31.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:31.59#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:34:31.59#ibcon#first serial, iclass 14, count 0 2006.257.02:34:31.59#ibcon#enter sib2, iclass 14, count 0 2006.257.02:34:31.59#ibcon#flushed, iclass 14, count 0 2006.257.02:34:31.59#ibcon#about to write, iclass 14, count 0 2006.257.02:34:31.59#ibcon#wrote, iclass 14, count 0 2006.257.02:34:31.59#ibcon#about to read 3, iclass 14, count 0 2006.257.02:34:31.62#ibcon#read 3, iclass 14, count 0 2006.257.02:34:31.62#ibcon#about to read 4, iclass 14, count 0 2006.257.02:34:31.62#ibcon#read 4, iclass 14, count 0 2006.257.02:34:31.62#ibcon#about to read 5, iclass 14, count 0 2006.257.02:34:31.62#ibcon#read 5, iclass 14, count 0 2006.257.02:34:31.62#ibcon#about to read 6, iclass 14, count 0 2006.257.02:34:31.62#ibcon#read 6, iclass 14, count 0 2006.257.02:34:31.62#ibcon#end of sib2, iclass 14, count 0 2006.257.02:34:31.62#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:34:31.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:34:31.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:34:31.62#ibcon#*before write, iclass 14, count 0 2006.257.02:34:31.62#ibcon#enter sib2, iclass 14, count 0 2006.257.02:34:31.62#ibcon#flushed, iclass 14, count 0 2006.257.02:34:31.62#ibcon#about to write, iclass 14, count 0 2006.257.02:34:31.62#ibcon#wrote, iclass 14, count 0 2006.257.02:34:31.62#ibcon#about to read 3, iclass 14, count 0 2006.257.02:34:31.66#ibcon#read 3, iclass 14, count 0 2006.257.02:34:31.66#ibcon#about to read 4, iclass 14, count 0 2006.257.02:34:31.66#ibcon#read 4, iclass 14, count 0 2006.257.02:34:31.66#ibcon#about to read 5, iclass 14, count 0 2006.257.02:34:31.66#ibcon#read 5, iclass 14, count 0 2006.257.02:34:31.66#ibcon#about to read 6, iclass 14, count 0 2006.257.02:34:31.66#ibcon#read 6, iclass 14, count 0 2006.257.02:34:31.66#ibcon#end of sib2, iclass 14, count 0 2006.257.02:34:31.66#ibcon#*after write, iclass 14, count 0 2006.257.02:34:31.66#ibcon#*before return 0, iclass 14, count 0 2006.257.02:34:31.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:31.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.02:34:31.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:34:31.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:34:31.66$vck44/vb=4,5 2006.257.02:34:31.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.02:34:31.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.02:34:31.66#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:31.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:31.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:31.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:31.71#ibcon#enter wrdev, iclass 16, count 2 2006.257.02:34:31.71#ibcon#first serial, iclass 16, count 2 2006.257.02:34:31.71#ibcon#enter sib2, iclass 16, count 2 2006.257.02:34:31.71#ibcon#flushed, iclass 16, count 2 2006.257.02:34:31.71#ibcon#about to write, iclass 16, count 2 2006.257.02:34:31.71#ibcon#wrote, iclass 16, count 2 2006.257.02:34:31.71#ibcon#about to read 3, iclass 16, count 2 2006.257.02:34:31.73#ibcon#read 3, iclass 16, count 2 2006.257.02:34:31.73#ibcon#about to read 4, iclass 16, count 2 2006.257.02:34:31.73#ibcon#read 4, iclass 16, count 2 2006.257.02:34:31.73#ibcon#about to read 5, iclass 16, count 2 2006.257.02:34:31.73#ibcon#read 5, iclass 16, count 2 2006.257.02:34:31.73#ibcon#about to read 6, iclass 16, count 2 2006.257.02:34:31.73#ibcon#read 6, iclass 16, count 2 2006.257.02:34:31.73#ibcon#end of sib2, iclass 16, count 2 2006.257.02:34:31.73#ibcon#*mode == 0, iclass 16, count 2 2006.257.02:34:31.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.02:34:31.73#ibcon#[27=AT04-05\r\n] 2006.257.02:34:31.73#ibcon#*before write, iclass 16, count 2 2006.257.02:34:31.73#ibcon#enter sib2, iclass 16, count 2 2006.257.02:34:31.73#ibcon#flushed, iclass 16, count 2 2006.257.02:34:31.73#ibcon#about to write, iclass 16, count 2 2006.257.02:34:31.73#ibcon#wrote, iclass 16, count 2 2006.257.02:34:31.73#ibcon#about to read 3, iclass 16, count 2 2006.257.02:34:31.76#ibcon#read 3, iclass 16, count 2 2006.257.02:34:31.76#ibcon#about to read 4, iclass 16, count 2 2006.257.02:34:31.76#ibcon#read 4, iclass 16, count 2 2006.257.02:34:31.76#ibcon#about to read 5, iclass 16, count 2 2006.257.02:34:31.76#ibcon#read 5, iclass 16, count 2 2006.257.02:34:31.76#ibcon#about to read 6, iclass 16, count 2 2006.257.02:34:31.76#ibcon#read 6, iclass 16, count 2 2006.257.02:34:31.76#ibcon#end of sib2, iclass 16, count 2 2006.257.02:34:31.76#ibcon#*after write, iclass 16, count 2 2006.257.02:34:31.76#ibcon#*before return 0, iclass 16, count 2 2006.257.02:34:31.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:31.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.02:34:31.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.02:34:31.76#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:31.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:31.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:31.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:31.88#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:34:31.88#ibcon#first serial, iclass 16, count 0 2006.257.02:34:31.88#ibcon#enter sib2, iclass 16, count 0 2006.257.02:34:31.88#ibcon#flushed, iclass 16, count 0 2006.257.02:34:31.88#ibcon#about to write, iclass 16, count 0 2006.257.02:34:31.88#ibcon#wrote, iclass 16, count 0 2006.257.02:34:31.88#ibcon#about to read 3, iclass 16, count 0 2006.257.02:34:31.90#ibcon#read 3, iclass 16, count 0 2006.257.02:34:31.90#ibcon#about to read 4, iclass 16, count 0 2006.257.02:34:31.90#ibcon#read 4, iclass 16, count 0 2006.257.02:34:31.90#ibcon#about to read 5, iclass 16, count 0 2006.257.02:34:31.90#ibcon#read 5, iclass 16, count 0 2006.257.02:34:31.90#ibcon#about to read 6, iclass 16, count 0 2006.257.02:34:31.90#ibcon#read 6, iclass 16, count 0 2006.257.02:34:31.90#ibcon#end of sib2, iclass 16, count 0 2006.257.02:34:31.90#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:34:31.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:34:31.90#ibcon#[27=USB\r\n] 2006.257.02:34:31.90#ibcon#*before write, iclass 16, count 0 2006.257.02:34:31.90#ibcon#enter sib2, iclass 16, count 0 2006.257.02:34:31.90#ibcon#flushed, iclass 16, count 0 2006.257.02:34:31.90#ibcon#about to write, iclass 16, count 0 2006.257.02:34:31.90#ibcon#wrote, iclass 16, count 0 2006.257.02:34:31.90#ibcon#about to read 3, iclass 16, count 0 2006.257.02:34:31.93#ibcon#read 3, iclass 16, count 0 2006.257.02:34:31.93#ibcon#about to read 4, iclass 16, count 0 2006.257.02:34:31.93#ibcon#read 4, iclass 16, count 0 2006.257.02:34:31.93#ibcon#about to read 5, iclass 16, count 0 2006.257.02:34:31.93#ibcon#read 5, iclass 16, count 0 2006.257.02:34:31.93#ibcon#about to read 6, iclass 16, count 0 2006.257.02:34:31.93#ibcon#read 6, iclass 16, count 0 2006.257.02:34:31.93#ibcon#end of sib2, iclass 16, count 0 2006.257.02:34:31.93#ibcon#*after write, iclass 16, count 0 2006.257.02:34:31.93#ibcon#*before return 0, iclass 16, count 0 2006.257.02:34:31.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:31.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.02:34:31.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:34:31.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:34:31.93$vck44/vblo=5,709.99 2006.257.02:34:31.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.02:34:31.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.02:34:31.93#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:31.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:31.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:31.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:31.93#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:34:31.93#ibcon#first serial, iclass 18, count 0 2006.257.02:34:31.93#ibcon#enter sib2, iclass 18, count 0 2006.257.02:34:31.93#ibcon#flushed, iclass 18, count 0 2006.257.02:34:31.93#ibcon#about to write, iclass 18, count 0 2006.257.02:34:31.93#ibcon#wrote, iclass 18, count 0 2006.257.02:34:31.93#ibcon#about to read 3, iclass 18, count 0 2006.257.02:34:31.95#ibcon#read 3, iclass 18, count 0 2006.257.02:34:31.95#ibcon#about to read 4, iclass 18, count 0 2006.257.02:34:31.95#ibcon#read 4, iclass 18, count 0 2006.257.02:34:31.95#ibcon#about to read 5, iclass 18, count 0 2006.257.02:34:31.95#ibcon#read 5, iclass 18, count 0 2006.257.02:34:31.95#ibcon#about to read 6, iclass 18, count 0 2006.257.02:34:31.95#ibcon#read 6, iclass 18, count 0 2006.257.02:34:31.95#ibcon#end of sib2, iclass 18, count 0 2006.257.02:34:31.95#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:34:31.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:34:31.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:34:31.95#ibcon#*before write, iclass 18, count 0 2006.257.02:34:31.95#ibcon#enter sib2, iclass 18, count 0 2006.257.02:34:31.95#ibcon#flushed, iclass 18, count 0 2006.257.02:34:31.95#ibcon#about to write, iclass 18, count 0 2006.257.02:34:31.95#ibcon#wrote, iclass 18, count 0 2006.257.02:34:31.95#ibcon#about to read 3, iclass 18, count 0 2006.257.02:34:31.99#ibcon#read 3, iclass 18, count 0 2006.257.02:34:31.99#ibcon#about to read 4, iclass 18, count 0 2006.257.02:34:31.99#ibcon#read 4, iclass 18, count 0 2006.257.02:34:31.99#ibcon#about to read 5, iclass 18, count 0 2006.257.02:34:31.99#ibcon#read 5, iclass 18, count 0 2006.257.02:34:31.99#ibcon#about to read 6, iclass 18, count 0 2006.257.02:34:31.99#ibcon#read 6, iclass 18, count 0 2006.257.02:34:31.99#ibcon#end of sib2, iclass 18, count 0 2006.257.02:34:31.99#ibcon#*after write, iclass 18, count 0 2006.257.02:34:31.99#ibcon#*before return 0, iclass 18, count 0 2006.257.02:34:31.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:31.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.02:34:31.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:34:31.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:34:31.99$vck44/vb=5,4 2006.257.02:34:31.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.02:34:31.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.02:34:31.99#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:31.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:32.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:32.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:32.05#ibcon#enter wrdev, iclass 20, count 2 2006.257.02:34:32.05#ibcon#first serial, iclass 20, count 2 2006.257.02:34:32.05#ibcon#enter sib2, iclass 20, count 2 2006.257.02:34:32.05#ibcon#flushed, iclass 20, count 2 2006.257.02:34:32.05#ibcon#about to write, iclass 20, count 2 2006.257.02:34:32.05#ibcon#wrote, iclass 20, count 2 2006.257.02:34:32.05#ibcon#about to read 3, iclass 20, count 2 2006.257.02:34:32.07#ibcon#read 3, iclass 20, count 2 2006.257.02:34:32.07#ibcon#about to read 4, iclass 20, count 2 2006.257.02:34:32.07#ibcon#read 4, iclass 20, count 2 2006.257.02:34:32.07#ibcon#about to read 5, iclass 20, count 2 2006.257.02:34:32.07#ibcon#read 5, iclass 20, count 2 2006.257.02:34:32.07#ibcon#about to read 6, iclass 20, count 2 2006.257.02:34:32.07#ibcon#read 6, iclass 20, count 2 2006.257.02:34:32.07#ibcon#end of sib2, iclass 20, count 2 2006.257.02:34:32.07#ibcon#*mode == 0, iclass 20, count 2 2006.257.02:34:32.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.02:34:32.07#ibcon#[27=AT05-04\r\n] 2006.257.02:34:32.07#ibcon#*before write, iclass 20, count 2 2006.257.02:34:32.07#ibcon#enter sib2, iclass 20, count 2 2006.257.02:34:32.07#ibcon#flushed, iclass 20, count 2 2006.257.02:34:32.07#ibcon#about to write, iclass 20, count 2 2006.257.02:34:32.07#ibcon#wrote, iclass 20, count 2 2006.257.02:34:32.07#ibcon#about to read 3, iclass 20, count 2 2006.257.02:34:32.10#ibcon#read 3, iclass 20, count 2 2006.257.02:34:32.10#ibcon#about to read 4, iclass 20, count 2 2006.257.02:34:32.10#ibcon#read 4, iclass 20, count 2 2006.257.02:34:32.10#ibcon#about to read 5, iclass 20, count 2 2006.257.02:34:32.10#ibcon#read 5, iclass 20, count 2 2006.257.02:34:32.10#ibcon#about to read 6, iclass 20, count 2 2006.257.02:34:32.10#ibcon#read 6, iclass 20, count 2 2006.257.02:34:32.10#ibcon#end of sib2, iclass 20, count 2 2006.257.02:34:32.10#ibcon#*after write, iclass 20, count 2 2006.257.02:34:32.10#ibcon#*before return 0, iclass 20, count 2 2006.257.02:34:32.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:32.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.02:34:32.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.02:34:32.10#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:32.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:32.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:32.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:32.22#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:34:32.22#ibcon#first serial, iclass 20, count 0 2006.257.02:34:32.22#ibcon#enter sib2, iclass 20, count 0 2006.257.02:34:32.22#ibcon#flushed, iclass 20, count 0 2006.257.02:34:32.22#ibcon#about to write, iclass 20, count 0 2006.257.02:34:32.22#ibcon#wrote, iclass 20, count 0 2006.257.02:34:32.22#ibcon#about to read 3, iclass 20, count 0 2006.257.02:34:32.24#ibcon#read 3, iclass 20, count 0 2006.257.02:34:32.24#ibcon#about to read 4, iclass 20, count 0 2006.257.02:34:32.24#ibcon#read 4, iclass 20, count 0 2006.257.02:34:32.24#ibcon#about to read 5, iclass 20, count 0 2006.257.02:34:32.24#ibcon#read 5, iclass 20, count 0 2006.257.02:34:32.24#ibcon#about to read 6, iclass 20, count 0 2006.257.02:34:32.24#ibcon#read 6, iclass 20, count 0 2006.257.02:34:32.24#ibcon#end of sib2, iclass 20, count 0 2006.257.02:34:32.24#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:34:32.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:34:32.24#ibcon#[27=USB\r\n] 2006.257.02:34:32.24#ibcon#*before write, iclass 20, count 0 2006.257.02:34:32.24#ibcon#enter sib2, iclass 20, count 0 2006.257.02:34:32.24#ibcon#flushed, iclass 20, count 0 2006.257.02:34:32.24#ibcon#about to write, iclass 20, count 0 2006.257.02:34:32.24#ibcon#wrote, iclass 20, count 0 2006.257.02:34:32.24#ibcon#about to read 3, iclass 20, count 0 2006.257.02:34:32.27#ibcon#read 3, iclass 20, count 0 2006.257.02:34:32.27#ibcon#about to read 4, iclass 20, count 0 2006.257.02:34:32.27#ibcon#read 4, iclass 20, count 0 2006.257.02:34:32.27#ibcon#about to read 5, iclass 20, count 0 2006.257.02:34:32.27#ibcon#read 5, iclass 20, count 0 2006.257.02:34:32.27#ibcon#about to read 6, iclass 20, count 0 2006.257.02:34:32.27#ibcon#read 6, iclass 20, count 0 2006.257.02:34:32.27#ibcon#end of sib2, iclass 20, count 0 2006.257.02:34:32.27#ibcon#*after write, iclass 20, count 0 2006.257.02:34:32.27#ibcon#*before return 0, iclass 20, count 0 2006.257.02:34:32.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:32.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.02:34:32.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:34:32.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:34:32.27$vck44/vblo=6,719.99 2006.257.02:34:32.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.02:34:32.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.02:34:32.27#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:32.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:32.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:32.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:32.27#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:34:32.27#ibcon#first serial, iclass 22, count 0 2006.257.02:34:32.27#ibcon#enter sib2, iclass 22, count 0 2006.257.02:34:32.27#ibcon#flushed, iclass 22, count 0 2006.257.02:34:32.27#ibcon#about to write, iclass 22, count 0 2006.257.02:34:32.27#ibcon#wrote, iclass 22, count 0 2006.257.02:34:32.27#ibcon#about to read 3, iclass 22, count 0 2006.257.02:34:32.29#ibcon#read 3, iclass 22, count 0 2006.257.02:34:32.29#ibcon#about to read 4, iclass 22, count 0 2006.257.02:34:32.29#ibcon#read 4, iclass 22, count 0 2006.257.02:34:32.29#ibcon#about to read 5, iclass 22, count 0 2006.257.02:34:32.29#ibcon#read 5, iclass 22, count 0 2006.257.02:34:32.29#ibcon#about to read 6, iclass 22, count 0 2006.257.02:34:32.29#ibcon#read 6, iclass 22, count 0 2006.257.02:34:32.29#ibcon#end of sib2, iclass 22, count 0 2006.257.02:34:32.29#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:34:32.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:34:32.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:34:32.29#ibcon#*before write, iclass 22, count 0 2006.257.02:34:32.29#ibcon#enter sib2, iclass 22, count 0 2006.257.02:34:32.29#ibcon#flushed, iclass 22, count 0 2006.257.02:34:32.29#ibcon#about to write, iclass 22, count 0 2006.257.02:34:32.29#ibcon#wrote, iclass 22, count 0 2006.257.02:34:32.29#ibcon#about to read 3, iclass 22, count 0 2006.257.02:34:32.33#ibcon#read 3, iclass 22, count 0 2006.257.02:34:32.33#ibcon#about to read 4, iclass 22, count 0 2006.257.02:34:32.33#ibcon#read 4, iclass 22, count 0 2006.257.02:34:32.33#ibcon#about to read 5, iclass 22, count 0 2006.257.02:34:32.33#ibcon#read 5, iclass 22, count 0 2006.257.02:34:32.33#ibcon#about to read 6, iclass 22, count 0 2006.257.02:34:32.33#ibcon#read 6, iclass 22, count 0 2006.257.02:34:32.33#ibcon#end of sib2, iclass 22, count 0 2006.257.02:34:32.33#ibcon#*after write, iclass 22, count 0 2006.257.02:34:32.33#ibcon#*before return 0, iclass 22, count 0 2006.257.02:34:32.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:32.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:34:32.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:34:32.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:34:32.33$vck44/vb=6,4 2006.257.02:34:32.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.02:34:32.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.02:34:32.33#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:32.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:32.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:32.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:32.39#ibcon#enter wrdev, iclass 24, count 2 2006.257.02:34:32.39#ibcon#first serial, iclass 24, count 2 2006.257.02:34:32.39#ibcon#enter sib2, iclass 24, count 2 2006.257.02:34:32.39#ibcon#flushed, iclass 24, count 2 2006.257.02:34:32.39#ibcon#about to write, iclass 24, count 2 2006.257.02:34:32.39#ibcon#wrote, iclass 24, count 2 2006.257.02:34:32.39#ibcon#about to read 3, iclass 24, count 2 2006.257.02:34:32.41#ibcon#read 3, iclass 24, count 2 2006.257.02:34:32.41#ibcon#about to read 4, iclass 24, count 2 2006.257.02:34:32.41#ibcon#read 4, iclass 24, count 2 2006.257.02:34:32.41#ibcon#about to read 5, iclass 24, count 2 2006.257.02:34:32.41#ibcon#read 5, iclass 24, count 2 2006.257.02:34:32.41#ibcon#about to read 6, iclass 24, count 2 2006.257.02:34:32.41#ibcon#read 6, iclass 24, count 2 2006.257.02:34:32.41#ibcon#end of sib2, iclass 24, count 2 2006.257.02:34:32.41#ibcon#*mode == 0, iclass 24, count 2 2006.257.02:34:32.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.02:34:32.41#ibcon#[27=AT06-04\r\n] 2006.257.02:34:32.41#ibcon#*before write, iclass 24, count 2 2006.257.02:34:32.41#ibcon#enter sib2, iclass 24, count 2 2006.257.02:34:32.41#ibcon#flushed, iclass 24, count 2 2006.257.02:34:32.41#ibcon#about to write, iclass 24, count 2 2006.257.02:34:32.41#ibcon#wrote, iclass 24, count 2 2006.257.02:34:32.41#ibcon#about to read 3, iclass 24, count 2 2006.257.02:34:32.44#ibcon#read 3, iclass 24, count 2 2006.257.02:34:32.44#ibcon#about to read 4, iclass 24, count 2 2006.257.02:34:32.44#ibcon#read 4, iclass 24, count 2 2006.257.02:34:32.44#ibcon#about to read 5, iclass 24, count 2 2006.257.02:34:32.44#ibcon#read 5, iclass 24, count 2 2006.257.02:34:32.44#ibcon#about to read 6, iclass 24, count 2 2006.257.02:34:32.44#ibcon#read 6, iclass 24, count 2 2006.257.02:34:32.44#ibcon#end of sib2, iclass 24, count 2 2006.257.02:34:32.44#ibcon#*after write, iclass 24, count 2 2006.257.02:34:32.44#ibcon#*before return 0, iclass 24, count 2 2006.257.02:34:32.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:32.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.02:34:32.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.02:34:32.44#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:32.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:32.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:32.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:32.56#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:34:32.56#ibcon#first serial, iclass 24, count 0 2006.257.02:34:32.56#ibcon#enter sib2, iclass 24, count 0 2006.257.02:34:32.56#ibcon#flushed, iclass 24, count 0 2006.257.02:34:32.56#ibcon#about to write, iclass 24, count 0 2006.257.02:34:32.56#ibcon#wrote, iclass 24, count 0 2006.257.02:34:32.56#ibcon#about to read 3, iclass 24, count 0 2006.257.02:34:32.58#ibcon#read 3, iclass 24, count 0 2006.257.02:34:32.58#ibcon#about to read 4, iclass 24, count 0 2006.257.02:34:32.58#ibcon#read 4, iclass 24, count 0 2006.257.02:34:32.58#ibcon#about to read 5, iclass 24, count 0 2006.257.02:34:32.58#ibcon#read 5, iclass 24, count 0 2006.257.02:34:32.58#ibcon#about to read 6, iclass 24, count 0 2006.257.02:34:32.58#ibcon#read 6, iclass 24, count 0 2006.257.02:34:32.58#ibcon#end of sib2, iclass 24, count 0 2006.257.02:34:32.58#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:34:32.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:34:32.58#ibcon#[27=USB\r\n] 2006.257.02:34:32.58#ibcon#*before write, iclass 24, count 0 2006.257.02:34:32.58#ibcon#enter sib2, iclass 24, count 0 2006.257.02:34:32.58#ibcon#flushed, iclass 24, count 0 2006.257.02:34:32.58#ibcon#about to write, iclass 24, count 0 2006.257.02:34:32.58#ibcon#wrote, iclass 24, count 0 2006.257.02:34:32.58#ibcon#about to read 3, iclass 24, count 0 2006.257.02:34:32.61#ibcon#read 3, iclass 24, count 0 2006.257.02:34:32.61#ibcon#about to read 4, iclass 24, count 0 2006.257.02:34:32.61#ibcon#read 4, iclass 24, count 0 2006.257.02:34:32.61#ibcon#about to read 5, iclass 24, count 0 2006.257.02:34:32.61#ibcon#read 5, iclass 24, count 0 2006.257.02:34:32.61#ibcon#about to read 6, iclass 24, count 0 2006.257.02:34:32.61#ibcon#read 6, iclass 24, count 0 2006.257.02:34:32.61#ibcon#end of sib2, iclass 24, count 0 2006.257.02:34:32.61#ibcon#*after write, iclass 24, count 0 2006.257.02:34:32.61#ibcon#*before return 0, iclass 24, count 0 2006.257.02:34:32.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:32.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.02:34:32.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:34:32.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:34:32.61$vck44/vblo=7,734.99 2006.257.02:34:32.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.02:34:32.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.02:34:32.61#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:32.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:32.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:32.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:32.61#ibcon#enter wrdev, iclass 26, count 0 2006.257.02:34:32.61#ibcon#first serial, iclass 26, count 0 2006.257.02:34:32.61#ibcon#enter sib2, iclass 26, count 0 2006.257.02:34:32.61#ibcon#flushed, iclass 26, count 0 2006.257.02:34:32.61#ibcon#about to write, iclass 26, count 0 2006.257.02:34:32.61#ibcon#wrote, iclass 26, count 0 2006.257.02:34:32.61#ibcon#about to read 3, iclass 26, count 0 2006.257.02:34:32.63#ibcon#read 3, iclass 26, count 0 2006.257.02:34:32.63#ibcon#about to read 4, iclass 26, count 0 2006.257.02:34:32.63#ibcon#read 4, iclass 26, count 0 2006.257.02:34:32.63#ibcon#about to read 5, iclass 26, count 0 2006.257.02:34:32.63#ibcon#read 5, iclass 26, count 0 2006.257.02:34:32.63#ibcon#about to read 6, iclass 26, count 0 2006.257.02:34:32.63#ibcon#read 6, iclass 26, count 0 2006.257.02:34:32.63#ibcon#end of sib2, iclass 26, count 0 2006.257.02:34:32.63#ibcon#*mode == 0, iclass 26, count 0 2006.257.02:34:32.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.02:34:32.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:34:32.63#ibcon#*before write, iclass 26, count 0 2006.257.02:34:32.63#ibcon#enter sib2, iclass 26, count 0 2006.257.02:34:32.63#ibcon#flushed, iclass 26, count 0 2006.257.02:34:32.63#ibcon#about to write, iclass 26, count 0 2006.257.02:34:32.63#ibcon#wrote, iclass 26, count 0 2006.257.02:34:32.63#ibcon#about to read 3, iclass 26, count 0 2006.257.02:34:32.67#ibcon#read 3, iclass 26, count 0 2006.257.02:34:32.67#ibcon#about to read 4, iclass 26, count 0 2006.257.02:34:32.67#ibcon#read 4, iclass 26, count 0 2006.257.02:34:32.67#ibcon#about to read 5, iclass 26, count 0 2006.257.02:34:32.67#ibcon#read 5, iclass 26, count 0 2006.257.02:34:32.67#ibcon#about to read 6, iclass 26, count 0 2006.257.02:34:32.67#ibcon#read 6, iclass 26, count 0 2006.257.02:34:32.67#ibcon#end of sib2, iclass 26, count 0 2006.257.02:34:32.67#ibcon#*after write, iclass 26, count 0 2006.257.02:34:32.67#ibcon#*before return 0, iclass 26, count 0 2006.257.02:34:32.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:32.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:34:32.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.02:34:32.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.02:34:32.67$vck44/vb=7,4 2006.257.02:34:32.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.02:34:32.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.02:34:32.67#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:32.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:32.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:32.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:32.73#ibcon#enter wrdev, iclass 28, count 2 2006.257.02:34:32.73#ibcon#first serial, iclass 28, count 2 2006.257.02:34:32.73#ibcon#enter sib2, iclass 28, count 2 2006.257.02:34:32.73#ibcon#flushed, iclass 28, count 2 2006.257.02:34:32.73#ibcon#about to write, iclass 28, count 2 2006.257.02:34:32.73#ibcon#wrote, iclass 28, count 2 2006.257.02:34:32.73#ibcon#about to read 3, iclass 28, count 2 2006.257.02:34:32.75#ibcon#read 3, iclass 28, count 2 2006.257.02:34:32.75#ibcon#about to read 4, iclass 28, count 2 2006.257.02:34:32.75#ibcon#read 4, iclass 28, count 2 2006.257.02:34:32.75#ibcon#about to read 5, iclass 28, count 2 2006.257.02:34:32.75#ibcon#read 5, iclass 28, count 2 2006.257.02:34:32.75#ibcon#about to read 6, iclass 28, count 2 2006.257.02:34:32.75#ibcon#read 6, iclass 28, count 2 2006.257.02:34:32.75#ibcon#end of sib2, iclass 28, count 2 2006.257.02:34:32.75#ibcon#*mode == 0, iclass 28, count 2 2006.257.02:34:32.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.02:34:32.75#ibcon#[27=AT07-04\r\n] 2006.257.02:34:32.75#ibcon#*before write, iclass 28, count 2 2006.257.02:34:32.75#ibcon#enter sib2, iclass 28, count 2 2006.257.02:34:32.75#ibcon#flushed, iclass 28, count 2 2006.257.02:34:32.75#ibcon#about to write, iclass 28, count 2 2006.257.02:34:32.75#ibcon#wrote, iclass 28, count 2 2006.257.02:34:32.75#ibcon#about to read 3, iclass 28, count 2 2006.257.02:34:32.78#ibcon#read 3, iclass 28, count 2 2006.257.02:34:32.78#ibcon#about to read 4, iclass 28, count 2 2006.257.02:34:32.78#ibcon#read 4, iclass 28, count 2 2006.257.02:34:32.78#ibcon#about to read 5, iclass 28, count 2 2006.257.02:34:32.78#ibcon#read 5, iclass 28, count 2 2006.257.02:34:32.78#ibcon#about to read 6, iclass 28, count 2 2006.257.02:34:32.78#ibcon#read 6, iclass 28, count 2 2006.257.02:34:32.78#ibcon#end of sib2, iclass 28, count 2 2006.257.02:34:32.78#ibcon#*after write, iclass 28, count 2 2006.257.02:34:32.78#ibcon#*before return 0, iclass 28, count 2 2006.257.02:34:32.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:32.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.02:34:32.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.02:34:32.78#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:32.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:32.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:32.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:32.90#ibcon#enter wrdev, iclass 28, count 0 2006.257.02:34:32.90#ibcon#first serial, iclass 28, count 0 2006.257.02:34:32.90#ibcon#enter sib2, iclass 28, count 0 2006.257.02:34:32.90#ibcon#flushed, iclass 28, count 0 2006.257.02:34:32.90#ibcon#about to write, iclass 28, count 0 2006.257.02:34:32.90#ibcon#wrote, iclass 28, count 0 2006.257.02:34:32.90#ibcon#about to read 3, iclass 28, count 0 2006.257.02:34:32.92#ibcon#read 3, iclass 28, count 0 2006.257.02:34:32.92#ibcon#about to read 4, iclass 28, count 0 2006.257.02:34:32.92#ibcon#read 4, iclass 28, count 0 2006.257.02:34:32.92#ibcon#about to read 5, iclass 28, count 0 2006.257.02:34:32.92#ibcon#read 5, iclass 28, count 0 2006.257.02:34:32.92#ibcon#about to read 6, iclass 28, count 0 2006.257.02:34:32.92#ibcon#read 6, iclass 28, count 0 2006.257.02:34:32.92#ibcon#end of sib2, iclass 28, count 0 2006.257.02:34:32.92#ibcon#*mode == 0, iclass 28, count 0 2006.257.02:34:32.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.02:34:32.92#ibcon#[27=USB\r\n] 2006.257.02:34:32.92#ibcon#*before write, iclass 28, count 0 2006.257.02:34:32.92#ibcon#enter sib2, iclass 28, count 0 2006.257.02:34:32.92#ibcon#flushed, iclass 28, count 0 2006.257.02:34:32.92#ibcon#about to write, iclass 28, count 0 2006.257.02:34:32.92#ibcon#wrote, iclass 28, count 0 2006.257.02:34:32.92#ibcon#about to read 3, iclass 28, count 0 2006.257.02:34:32.95#ibcon#read 3, iclass 28, count 0 2006.257.02:34:32.95#ibcon#about to read 4, iclass 28, count 0 2006.257.02:34:32.95#ibcon#read 4, iclass 28, count 0 2006.257.02:34:32.95#ibcon#about to read 5, iclass 28, count 0 2006.257.02:34:32.95#ibcon#read 5, iclass 28, count 0 2006.257.02:34:32.95#ibcon#about to read 6, iclass 28, count 0 2006.257.02:34:32.95#ibcon#read 6, iclass 28, count 0 2006.257.02:34:32.95#ibcon#end of sib2, iclass 28, count 0 2006.257.02:34:32.95#ibcon#*after write, iclass 28, count 0 2006.257.02:34:32.95#ibcon#*before return 0, iclass 28, count 0 2006.257.02:34:32.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:32.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.02:34:32.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.02:34:32.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.02:34:32.95$vck44/vblo=8,744.99 2006.257.02:34:32.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.02:34:32.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.02:34:32.95#ibcon#ireg 17 cls_cnt 0 2006.257.02:34:32.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:32.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:32.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:32.95#ibcon#enter wrdev, iclass 30, count 0 2006.257.02:34:32.95#ibcon#first serial, iclass 30, count 0 2006.257.02:34:32.95#ibcon#enter sib2, iclass 30, count 0 2006.257.02:34:32.95#ibcon#flushed, iclass 30, count 0 2006.257.02:34:32.95#ibcon#about to write, iclass 30, count 0 2006.257.02:34:32.95#ibcon#wrote, iclass 30, count 0 2006.257.02:34:32.95#ibcon#about to read 3, iclass 30, count 0 2006.257.02:34:32.97#ibcon#read 3, iclass 30, count 0 2006.257.02:34:32.97#ibcon#about to read 4, iclass 30, count 0 2006.257.02:34:32.97#ibcon#read 4, iclass 30, count 0 2006.257.02:34:32.97#ibcon#about to read 5, iclass 30, count 0 2006.257.02:34:32.97#ibcon#read 5, iclass 30, count 0 2006.257.02:34:32.97#ibcon#about to read 6, iclass 30, count 0 2006.257.02:34:32.97#ibcon#read 6, iclass 30, count 0 2006.257.02:34:32.97#ibcon#end of sib2, iclass 30, count 0 2006.257.02:34:32.97#ibcon#*mode == 0, iclass 30, count 0 2006.257.02:34:32.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.02:34:32.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:34:32.97#ibcon#*before write, iclass 30, count 0 2006.257.02:34:32.97#ibcon#enter sib2, iclass 30, count 0 2006.257.02:34:32.97#ibcon#flushed, iclass 30, count 0 2006.257.02:34:32.97#ibcon#about to write, iclass 30, count 0 2006.257.02:34:32.97#ibcon#wrote, iclass 30, count 0 2006.257.02:34:32.97#ibcon#about to read 3, iclass 30, count 0 2006.257.02:34:33.01#ibcon#read 3, iclass 30, count 0 2006.257.02:34:33.01#ibcon#about to read 4, iclass 30, count 0 2006.257.02:34:33.01#ibcon#read 4, iclass 30, count 0 2006.257.02:34:33.01#ibcon#about to read 5, iclass 30, count 0 2006.257.02:34:33.01#ibcon#read 5, iclass 30, count 0 2006.257.02:34:33.01#ibcon#about to read 6, iclass 30, count 0 2006.257.02:34:33.01#ibcon#read 6, iclass 30, count 0 2006.257.02:34:33.01#ibcon#end of sib2, iclass 30, count 0 2006.257.02:34:33.01#ibcon#*after write, iclass 30, count 0 2006.257.02:34:33.01#ibcon#*before return 0, iclass 30, count 0 2006.257.02:34:33.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:33.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.02:34:33.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.02:34:33.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.02:34:33.01$vck44/vb=8,4 2006.257.02:34:33.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.02:34:33.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.02:34:33.01#ibcon#ireg 11 cls_cnt 2 2006.257.02:34:33.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:33.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:33.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:33.07#ibcon#enter wrdev, iclass 32, count 2 2006.257.02:34:33.07#ibcon#first serial, iclass 32, count 2 2006.257.02:34:33.07#ibcon#enter sib2, iclass 32, count 2 2006.257.02:34:33.07#ibcon#flushed, iclass 32, count 2 2006.257.02:34:33.07#ibcon#about to write, iclass 32, count 2 2006.257.02:34:33.07#ibcon#wrote, iclass 32, count 2 2006.257.02:34:33.07#ibcon#about to read 3, iclass 32, count 2 2006.257.02:34:33.09#ibcon#read 3, iclass 32, count 2 2006.257.02:34:33.09#ibcon#about to read 4, iclass 32, count 2 2006.257.02:34:33.09#ibcon#read 4, iclass 32, count 2 2006.257.02:34:33.09#ibcon#about to read 5, iclass 32, count 2 2006.257.02:34:33.09#ibcon#read 5, iclass 32, count 2 2006.257.02:34:33.09#ibcon#about to read 6, iclass 32, count 2 2006.257.02:34:33.09#ibcon#read 6, iclass 32, count 2 2006.257.02:34:33.09#ibcon#end of sib2, iclass 32, count 2 2006.257.02:34:33.09#ibcon#*mode == 0, iclass 32, count 2 2006.257.02:34:33.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.02:34:33.09#ibcon#[27=AT08-04\r\n] 2006.257.02:34:33.09#ibcon#*before write, iclass 32, count 2 2006.257.02:34:33.09#ibcon#enter sib2, iclass 32, count 2 2006.257.02:34:33.09#ibcon#flushed, iclass 32, count 2 2006.257.02:34:33.09#ibcon#about to write, iclass 32, count 2 2006.257.02:34:33.09#ibcon#wrote, iclass 32, count 2 2006.257.02:34:33.09#ibcon#about to read 3, iclass 32, count 2 2006.257.02:34:33.12#ibcon#read 3, iclass 32, count 2 2006.257.02:34:33.12#ibcon#about to read 4, iclass 32, count 2 2006.257.02:34:33.12#ibcon#read 4, iclass 32, count 2 2006.257.02:34:33.12#ibcon#about to read 5, iclass 32, count 2 2006.257.02:34:33.12#ibcon#read 5, iclass 32, count 2 2006.257.02:34:33.12#ibcon#about to read 6, iclass 32, count 2 2006.257.02:34:33.12#ibcon#read 6, iclass 32, count 2 2006.257.02:34:33.12#ibcon#end of sib2, iclass 32, count 2 2006.257.02:34:33.12#ibcon#*after write, iclass 32, count 2 2006.257.02:34:33.12#ibcon#*before return 0, iclass 32, count 2 2006.257.02:34:33.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:33.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.02:34:33.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.02:34:33.12#ibcon#ireg 7 cls_cnt 0 2006.257.02:34:33.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:33.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:33.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:33.24#ibcon#enter wrdev, iclass 32, count 0 2006.257.02:34:33.24#ibcon#first serial, iclass 32, count 0 2006.257.02:34:33.24#ibcon#enter sib2, iclass 32, count 0 2006.257.02:34:33.24#ibcon#flushed, iclass 32, count 0 2006.257.02:34:33.24#ibcon#about to write, iclass 32, count 0 2006.257.02:34:33.24#ibcon#wrote, iclass 32, count 0 2006.257.02:34:33.24#ibcon#about to read 3, iclass 32, count 0 2006.257.02:34:33.26#ibcon#read 3, iclass 32, count 0 2006.257.02:34:33.26#ibcon#about to read 4, iclass 32, count 0 2006.257.02:34:33.26#ibcon#read 4, iclass 32, count 0 2006.257.02:34:33.26#ibcon#about to read 5, iclass 32, count 0 2006.257.02:34:33.26#ibcon#read 5, iclass 32, count 0 2006.257.02:34:33.26#ibcon#about to read 6, iclass 32, count 0 2006.257.02:34:33.26#ibcon#read 6, iclass 32, count 0 2006.257.02:34:33.26#ibcon#end of sib2, iclass 32, count 0 2006.257.02:34:33.26#ibcon#*mode == 0, iclass 32, count 0 2006.257.02:34:33.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.02:34:33.26#ibcon#[27=USB\r\n] 2006.257.02:34:33.26#ibcon#*before write, iclass 32, count 0 2006.257.02:34:33.26#ibcon#enter sib2, iclass 32, count 0 2006.257.02:34:33.26#ibcon#flushed, iclass 32, count 0 2006.257.02:34:33.26#ibcon#about to write, iclass 32, count 0 2006.257.02:34:33.26#ibcon#wrote, iclass 32, count 0 2006.257.02:34:33.26#ibcon#about to read 3, iclass 32, count 0 2006.257.02:34:33.29#ibcon#read 3, iclass 32, count 0 2006.257.02:34:33.29#ibcon#about to read 4, iclass 32, count 0 2006.257.02:34:33.29#ibcon#read 4, iclass 32, count 0 2006.257.02:34:33.29#ibcon#about to read 5, iclass 32, count 0 2006.257.02:34:33.29#ibcon#read 5, iclass 32, count 0 2006.257.02:34:33.29#ibcon#about to read 6, iclass 32, count 0 2006.257.02:34:33.29#ibcon#read 6, iclass 32, count 0 2006.257.02:34:33.29#ibcon#end of sib2, iclass 32, count 0 2006.257.02:34:33.29#ibcon#*after write, iclass 32, count 0 2006.257.02:34:33.29#ibcon#*before return 0, iclass 32, count 0 2006.257.02:34:33.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:33.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.02:34:33.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.02:34:33.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.02:34:33.29$vck44/vabw=wide 2006.257.02:34:33.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.02:34:33.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.02:34:33.29#ibcon#ireg 8 cls_cnt 0 2006.257.02:34:33.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:33.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:33.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:33.29#ibcon#enter wrdev, iclass 34, count 0 2006.257.02:34:33.29#ibcon#first serial, iclass 34, count 0 2006.257.02:34:33.29#ibcon#enter sib2, iclass 34, count 0 2006.257.02:34:33.29#ibcon#flushed, iclass 34, count 0 2006.257.02:34:33.29#ibcon#about to write, iclass 34, count 0 2006.257.02:34:33.29#ibcon#wrote, iclass 34, count 0 2006.257.02:34:33.29#ibcon#about to read 3, iclass 34, count 0 2006.257.02:34:33.31#ibcon#read 3, iclass 34, count 0 2006.257.02:34:33.31#ibcon#about to read 4, iclass 34, count 0 2006.257.02:34:33.31#ibcon#read 4, iclass 34, count 0 2006.257.02:34:33.31#ibcon#about to read 5, iclass 34, count 0 2006.257.02:34:33.31#ibcon#read 5, iclass 34, count 0 2006.257.02:34:33.31#ibcon#about to read 6, iclass 34, count 0 2006.257.02:34:33.31#ibcon#read 6, iclass 34, count 0 2006.257.02:34:33.31#ibcon#end of sib2, iclass 34, count 0 2006.257.02:34:33.31#ibcon#*mode == 0, iclass 34, count 0 2006.257.02:34:33.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.02:34:33.31#ibcon#[25=BW32\r\n] 2006.257.02:34:33.31#ibcon#*before write, iclass 34, count 0 2006.257.02:34:33.31#ibcon#enter sib2, iclass 34, count 0 2006.257.02:34:33.31#ibcon#flushed, iclass 34, count 0 2006.257.02:34:33.31#ibcon#about to write, iclass 34, count 0 2006.257.02:34:33.31#ibcon#wrote, iclass 34, count 0 2006.257.02:34:33.31#ibcon#about to read 3, iclass 34, count 0 2006.257.02:34:33.34#ibcon#read 3, iclass 34, count 0 2006.257.02:34:33.34#ibcon#about to read 4, iclass 34, count 0 2006.257.02:34:33.34#ibcon#read 4, iclass 34, count 0 2006.257.02:34:33.34#ibcon#about to read 5, iclass 34, count 0 2006.257.02:34:33.34#ibcon#read 5, iclass 34, count 0 2006.257.02:34:33.34#ibcon#about to read 6, iclass 34, count 0 2006.257.02:34:33.34#ibcon#read 6, iclass 34, count 0 2006.257.02:34:33.34#ibcon#end of sib2, iclass 34, count 0 2006.257.02:34:33.34#ibcon#*after write, iclass 34, count 0 2006.257.02:34:33.34#ibcon#*before return 0, iclass 34, count 0 2006.257.02:34:33.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:33.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.02:34:33.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.02:34:33.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.02:34:33.34$vck44/vbbw=wide 2006.257.02:34:33.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.02:34:33.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.02:34:33.34#ibcon#ireg 8 cls_cnt 0 2006.257.02:34:33.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:34:33.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:34:33.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:34:33.41#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:34:33.41#ibcon#first serial, iclass 36, count 0 2006.257.02:34:33.41#ibcon#enter sib2, iclass 36, count 0 2006.257.02:34:33.41#ibcon#flushed, iclass 36, count 0 2006.257.02:34:33.41#ibcon#about to write, iclass 36, count 0 2006.257.02:34:33.41#ibcon#wrote, iclass 36, count 0 2006.257.02:34:33.41#ibcon#about to read 3, iclass 36, count 0 2006.257.02:34:33.43#ibcon#read 3, iclass 36, count 0 2006.257.02:34:33.43#ibcon#about to read 4, iclass 36, count 0 2006.257.02:34:33.43#ibcon#read 4, iclass 36, count 0 2006.257.02:34:33.43#ibcon#about to read 5, iclass 36, count 0 2006.257.02:34:33.43#ibcon#read 5, iclass 36, count 0 2006.257.02:34:33.43#ibcon#about to read 6, iclass 36, count 0 2006.257.02:34:33.43#ibcon#read 6, iclass 36, count 0 2006.257.02:34:33.43#ibcon#end of sib2, iclass 36, count 0 2006.257.02:34:33.43#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:34:33.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:34:33.43#ibcon#[27=BW32\r\n] 2006.257.02:34:33.43#ibcon#*before write, iclass 36, count 0 2006.257.02:34:33.43#ibcon#enter sib2, iclass 36, count 0 2006.257.02:34:33.43#ibcon#flushed, iclass 36, count 0 2006.257.02:34:33.43#ibcon#about to write, iclass 36, count 0 2006.257.02:34:33.43#ibcon#wrote, iclass 36, count 0 2006.257.02:34:33.43#ibcon#about to read 3, iclass 36, count 0 2006.257.02:34:33.46#ibcon#read 3, iclass 36, count 0 2006.257.02:34:33.46#ibcon#about to read 4, iclass 36, count 0 2006.257.02:34:33.46#ibcon#read 4, iclass 36, count 0 2006.257.02:34:33.46#ibcon#about to read 5, iclass 36, count 0 2006.257.02:34:33.46#ibcon#read 5, iclass 36, count 0 2006.257.02:34:33.46#ibcon#about to read 6, iclass 36, count 0 2006.257.02:34:33.46#ibcon#read 6, iclass 36, count 0 2006.257.02:34:33.46#ibcon#end of sib2, iclass 36, count 0 2006.257.02:34:33.46#ibcon#*after write, iclass 36, count 0 2006.257.02:34:33.46#ibcon#*before return 0, iclass 36, count 0 2006.257.02:34:33.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:34:33.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:34:33.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:34:33.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:34:33.46$setupk4/ifdk4 2006.257.02:34:33.46$ifdk4/lo= 2006.257.02:34:33.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:34:33.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:34:33.46$ifdk4/patch= 2006.257.02:34:33.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:34:33.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:34:33.46$setupk4/!*+20s 2006.257.02:34:41.23#abcon#<5=/02 2.1 6.0 18.14 971012.3\r\n> 2006.257.02:34:41.25#abcon#{5=INTERFACE CLEAR} 2006.257.02:34:41.31#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:34:47.97$setupk4/"tpicd 2006.257.02:34:47.97$setupk4/echo=off 2006.257.02:34:47.97$setupk4/xlog=off 2006.257.02:34:47.97:!2006.257.02:35:55 2006.257.02:34:52.14#trakl#Source acquired 2006.257.02:34:52.14#flagr#flagr/antenna,acquired 2006.257.02:35:55.00:preob 2006.257.02:35:56.13/onsource/TRACKING 2006.257.02:35:56.13:!2006.257.02:36:05 2006.257.02:36:05.00:"tape 2006.257.02:36:05.00:"st=record 2006.257.02:36:05.00:data_valid=on 2006.257.02:36:05.00:midob 2006.257.02:36:05.13/onsource/TRACKING 2006.257.02:36:05.13/wx/18.23,1012.4,98 2006.257.02:36:05.31/cable/+6.4863E-03 2006.257.02:36:06.40/va/01,08,usb,yes,31,33 2006.257.02:36:06.40/va/02,07,usb,yes,34,34 2006.257.02:36:06.40/va/03,08,usb,yes,30,32 2006.257.02:36:06.40/va/04,07,usb,yes,35,36 2006.257.02:36:06.40/va/05,04,usb,yes,31,31 2006.257.02:36:06.40/va/06,04,usb,yes,34,34 2006.257.02:36:06.40/va/07,04,usb,yes,35,36 2006.257.02:36:06.40/va/08,04,usb,yes,29,36 2006.257.02:36:06.63/valo/01,524.99,yes,locked 2006.257.02:36:06.63/valo/02,534.99,yes,locked 2006.257.02:36:06.63/valo/03,564.99,yes,locked 2006.257.02:36:06.63/valo/04,624.99,yes,locked 2006.257.02:36:06.63/valo/05,734.99,yes,locked 2006.257.02:36:06.63/valo/06,814.99,yes,locked 2006.257.02:36:06.63/valo/07,864.99,yes,locked 2006.257.02:36:06.63/valo/08,884.99,yes,locked 2006.257.02:36:07.72/vb/01,04,usb,yes,30,28 2006.257.02:36:07.72/vb/02,05,usb,yes,29,28 2006.257.02:36:07.72/vb/03,04,usb,yes,30,33 2006.257.02:36:07.72/vb/04,05,usb,yes,30,29 2006.257.02:36:07.72/vb/05,04,usb,yes,26,29 2006.257.02:36:07.72/vb/06,04,usb,yes,31,27 2006.257.02:36:07.72/vb/07,04,usb,yes,31,31 2006.257.02:36:07.72/vb/08,04,usb,yes,28,31 2006.257.02:36:07.96/vblo/01,629.99,yes,locked 2006.257.02:36:07.96/vblo/02,634.99,yes,locked 2006.257.02:36:07.96/vblo/03,649.99,yes,locked 2006.257.02:36:07.96/vblo/04,679.99,yes,locked 2006.257.02:36:07.96/vblo/05,709.99,yes,locked 2006.257.02:36:07.96/vblo/06,719.99,yes,locked 2006.257.02:36:07.96/vblo/07,734.99,yes,locked 2006.257.02:36:07.96/vblo/08,744.99,yes,locked 2006.257.02:36:08.11/vabw/8 2006.257.02:36:08.26/vbbw/8 2006.257.02:36:08.35/xfe/off,on,15.5 2006.257.02:36:08.73/ifatt/23,28,28,28 2006.257.02:36:09.07/fmout-gps/S +4.57E-07 2006.257.02:36:09.11:!2006.257.02:39:25 2006.257.02:39:25.00:data_valid=off 2006.257.02:39:25.00:"et 2006.257.02:39:25.00:!+3s 2006.257.02:39:28.01:"tape 2006.257.02:39:28.01:postob 2006.257.02:39:28.11/cable/+6.4870E-03 2006.257.02:39:28.11/wx/18.44,1012.4,97 2006.257.02:39:29.08/fmout-gps/S +4.60E-07 2006.257.02:39:29.08:scan_name=257-0242,jd0609,40 2006.257.02:39:29.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.257.02:39:30.14#flagr#flagr/antenna,new-source 2006.257.02:39:30.14:checkk5 2006.257.02:39:30.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:39:31.01/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:39:31.50/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:39:31.95/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:39:32.39/chk_obsdata//k5ts1/T2570236??a.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.02:39:32.78/chk_obsdata//k5ts2/T2570236??b.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.02:39:33.22/chk_obsdata//k5ts3/T2570236??c.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.02:39:33.61/chk_obsdata//k5ts4/T2570236??d.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.02:39:34.39/k5log//k5ts1_log_newline 2006.257.02:39:35.17/k5log//k5ts2_log_newline 2006.257.02:39:36.01/k5log//k5ts3_log_newline 2006.257.02:39:36.77/k5log//k5ts4_log_newline 2006.257.02:39:36.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:39:36.79:setupk4=1 2006.257.02:39:36.79$setupk4/echo=on 2006.257.02:39:36.79$setupk4/pcalon 2006.257.02:39:36.79$pcalon/"no phase cal control is implemented here 2006.257.02:39:36.79$setupk4/"tpicd=stop 2006.257.02:39:36.79$setupk4/"rec=synch_on 2006.257.02:39:36.79$setupk4/"rec_mode=128 2006.257.02:39:36.79$setupk4/!* 2006.257.02:39:36.79$setupk4/recpk4 2006.257.02:39:36.79$recpk4/recpatch= 2006.257.02:39:36.79$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:39:36.79$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:39:36.79$setupk4/vck44 2006.257.02:39:36.79$vck44/valo=1,524.99 2006.257.02:39:36.79#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.02:39:36.79#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.02:39:36.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:36.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:36.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:36.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:36.79#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:39:36.79#ibcon#first serial, iclass 17, count 0 2006.257.02:39:36.79#ibcon#enter sib2, iclass 17, count 0 2006.257.02:39:36.79#ibcon#flushed, iclass 17, count 0 2006.257.02:39:36.79#ibcon#about to write, iclass 17, count 0 2006.257.02:39:36.79#ibcon#wrote, iclass 17, count 0 2006.257.02:39:36.79#ibcon#about to read 3, iclass 17, count 0 2006.257.02:39:36.83#ibcon#read 3, iclass 17, count 0 2006.257.02:39:36.83#ibcon#about to read 4, iclass 17, count 0 2006.257.02:39:36.83#ibcon#read 4, iclass 17, count 0 2006.257.02:39:36.83#ibcon#about to read 5, iclass 17, count 0 2006.257.02:39:36.83#ibcon#read 5, iclass 17, count 0 2006.257.02:39:36.83#ibcon#about to read 6, iclass 17, count 0 2006.257.02:39:36.83#ibcon#read 6, iclass 17, count 0 2006.257.02:39:36.83#ibcon#end of sib2, iclass 17, count 0 2006.257.02:39:36.83#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:39:36.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:39:36.83#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:39:36.83#ibcon#*before write, iclass 17, count 0 2006.257.02:39:36.83#ibcon#enter sib2, iclass 17, count 0 2006.257.02:39:36.83#ibcon#flushed, iclass 17, count 0 2006.257.02:39:36.83#ibcon#about to write, iclass 17, count 0 2006.257.02:39:36.83#ibcon#wrote, iclass 17, count 0 2006.257.02:39:36.83#ibcon#about to read 3, iclass 17, count 0 2006.257.02:39:36.87#ibcon#read 3, iclass 17, count 0 2006.257.02:39:36.87#ibcon#about to read 4, iclass 17, count 0 2006.257.02:39:36.87#ibcon#read 4, iclass 17, count 0 2006.257.02:39:36.87#ibcon#about to read 5, iclass 17, count 0 2006.257.02:39:36.87#ibcon#read 5, iclass 17, count 0 2006.257.02:39:36.87#ibcon#about to read 6, iclass 17, count 0 2006.257.02:39:36.87#ibcon#read 6, iclass 17, count 0 2006.257.02:39:36.87#ibcon#end of sib2, iclass 17, count 0 2006.257.02:39:36.87#ibcon#*after write, iclass 17, count 0 2006.257.02:39:36.87#ibcon#*before return 0, iclass 17, count 0 2006.257.02:39:36.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:36.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:36.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:39:36.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:39:36.87$vck44/va=1,8 2006.257.02:39:36.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.02:39:36.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.02:39:36.87#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:36.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:36.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:36.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:36.87#ibcon#enter wrdev, iclass 19, count 2 2006.257.02:39:36.87#ibcon#first serial, iclass 19, count 2 2006.257.02:39:36.87#ibcon#enter sib2, iclass 19, count 2 2006.257.02:39:36.87#ibcon#flushed, iclass 19, count 2 2006.257.02:39:36.87#ibcon#about to write, iclass 19, count 2 2006.257.02:39:36.87#ibcon#wrote, iclass 19, count 2 2006.257.02:39:36.87#ibcon#about to read 3, iclass 19, count 2 2006.257.02:39:36.90#ibcon#read 3, iclass 19, count 2 2006.257.02:39:36.90#ibcon#about to read 4, iclass 19, count 2 2006.257.02:39:36.90#ibcon#read 4, iclass 19, count 2 2006.257.02:39:36.90#ibcon#about to read 5, iclass 19, count 2 2006.257.02:39:36.90#ibcon#read 5, iclass 19, count 2 2006.257.02:39:36.90#ibcon#about to read 6, iclass 19, count 2 2006.257.02:39:36.90#ibcon#read 6, iclass 19, count 2 2006.257.02:39:36.90#ibcon#end of sib2, iclass 19, count 2 2006.257.02:39:36.90#ibcon#*mode == 0, iclass 19, count 2 2006.257.02:39:36.90#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.02:39:36.90#ibcon#[25=AT01-08\r\n] 2006.257.02:39:36.90#ibcon#*before write, iclass 19, count 2 2006.257.02:39:36.90#ibcon#enter sib2, iclass 19, count 2 2006.257.02:39:36.90#ibcon#flushed, iclass 19, count 2 2006.257.02:39:36.90#ibcon#about to write, iclass 19, count 2 2006.257.02:39:36.90#ibcon#wrote, iclass 19, count 2 2006.257.02:39:36.90#ibcon#about to read 3, iclass 19, count 2 2006.257.02:39:36.92#ibcon#read 3, iclass 19, count 2 2006.257.02:39:36.92#ibcon#about to read 4, iclass 19, count 2 2006.257.02:39:36.92#ibcon#read 4, iclass 19, count 2 2006.257.02:39:36.92#ibcon#about to read 5, iclass 19, count 2 2006.257.02:39:36.92#ibcon#read 5, iclass 19, count 2 2006.257.02:39:36.92#ibcon#about to read 6, iclass 19, count 2 2006.257.02:39:36.92#ibcon#read 6, iclass 19, count 2 2006.257.02:39:36.92#ibcon#end of sib2, iclass 19, count 2 2006.257.02:39:36.92#ibcon#*after write, iclass 19, count 2 2006.257.02:39:36.92#ibcon#*before return 0, iclass 19, count 2 2006.257.02:39:36.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:36.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:36.92#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.02:39:36.92#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:36.92#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:37.04#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:37.04#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:37.04#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:39:37.04#ibcon#first serial, iclass 19, count 0 2006.257.02:39:37.04#ibcon#enter sib2, iclass 19, count 0 2006.257.02:39:37.04#ibcon#flushed, iclass 19, count 0 2006.257.02:39:37.04#ibcon#about to write, iclass 19, count 0 2006.257.02:39:37.04#ibcon#wrote, iclass 19, count 0 2006.257.02:39:37.04#ibcon#about to read 3, iclass 19, count 0 2006.257.02:39:37.06#ibcon#read 3, iclass 19, count 0 2006.257.02:39:37.06#ibcon#about to read 4, iclass 19, count 0 2006.257.02:39:37.06#ibcon#read 4, iclass 19, count 0 2006.257.02:39:37.06#ibcon#about to read 5, iclass 19, count 0 2006.257.02:39:37.06#ibcon#read 5, iclass 19, count 0 2006.257.02:39:37.06#ibcon#about to read 6, iclass 19, count 0 2006.257.02:39:37.06#ibcon#read 6, iclass 19, count 0 2006.257.02:39:37.06#ibcon#end of sib2, iclass 19, count 0 2006.257.02:39:37.06#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:39:37.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:39:37.06#ibcon#[25=USB\r\n] 2006.257.02:39:37.06#ibcon#*before write, iclass 19, count 0 2006.257.02:39:37.06#ibcon#enter sib2, iclass 19, count 0 2006.257.02:39:37.06#ibcon#flushed, iclass 19, count 0 2006.257.02:39:37.06#ibcon#about to write, iclass 19, count 0 2006.257.02:39:37.06#ibcon#wrote, iclass 19, count 0 2006.257.02:39:37.06#ibcon#about to read 3, iclass 19, count 0 2006.257.02:39:37.09#ibcon#read 3, iclass 19, count 0 2006.257.02:39:37.09#ibcon#about to read 4, iclass 19, count 0 2006.257.02:39:37.09#ibcon#read 4, iclass 19, count 0 2006.257.02:39:37.09#ibcon#about to read 5, iclass 19, count 0 2006.257.02:39:37.09#ibcon#read 5, iclass 19, count 0 2006.257.02:39:37.09#ibcon#about to read 6, iclass 19, count 0 2006.257.02:39:37.09#ibcon#read 6, iclass 19, count 0 2006.257.02:39:37.09#ibcon#end of sib2, iclass 19, count 0 2006.257.02:39:37.09#ibcon#*after write, iclass 19, count 0 2006.257.02:39:37.09#ibcon#*before return 0, iclass 19, count 0 2006.257.02:39:37.09#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:37.09#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:37.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:39:37.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:39:37.09$vck44/valo=2,534.99 2006.257.02:39:37.09#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.02:39:37.09#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.02:39:37.09#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:37.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:37.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:37.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:37.09#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:39:37.09#ibcon#first serial, iclass 21, count 0 2006.257.02:39:37.09#ibcon#enter sib2, iclass 21, count 0 2006.257.02:39:37.09#ibcon#flushed, iclass 21, count 0 2006.257.02:39:37.09#ibcon#about to write, iclass 21, count 0 2006.257.02:39:37.09#ibcon#wrote, iclass 21, count 0 2006.257.02:39:37.09#ibcon#about to read 3, iclass 21, count 0 2006.257.02:39:37.11#ibcon#read 3, iclass 21, count 0 2006.257.02:39:37.11#ibcon#about to read 4, iclass 21, count 0 2006.257.02:39:37.11#ibcon#read 4, iclass 21, count 0 2006.257.02:39:37.11#ibcon#about to read 5, iclass 21, count 0 2006.257.02:39:37.11#ibcon#read 5, iclass 21, count 0 2006.257.02:39:37.11#ibcon#about to read 6, iclass 21, count 0 2006.257.02:39:37.11#ibcon#read 6, iclass 21, count 0 2006.257.02:39:37.11#ibcon#end of sib2, iclass 21, count 0 2006.257.02:39:37.11#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:39:37.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:39:37.11#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:39:37.11#ibcon#*before write, iclass 21, count 0 2006.257.02:39:37.11#ibcon#enter sib2, iclass 21, count 0 2006.257.02:39:37.11#ibcon#flushed, iclass 21, count 0 2006.257.02:39:37.11#ibcon#about to write, iclass 21, count 0 2006.257.02:39:37.11#ibcon#wrote, iclass 21, count 0 2006.257.02:39:37.11#ibcon#about to read 3, iclass 21, count 0 2006.257.02:39:37.15#ibcon#read 3, iclass 21, count 0 2006.257.02:39:37.15#ibcon#about to read 4, iclass 21, count 0 2006.257.02:39:37.15#ibcon#read 4, iclass 21, count 0 2006.257.02:39:37.15#ibcon#about to read 5, iclass 21, count 0 2006.257.02:39:37.15#ibcon#read 5, iclass 21, count 0 2006.257.02:39:37.15#ibcon#about to read 6, iclass 21, count 0 2006.257.02:39:37.15#ibcon#read 6, iclass 21, count 0 2006.257.02:39:37.15#ibcon#end of sib2, iclass 21, count 0 2006.257.02:39:37.15#ibcon#*after write, iclass 21, count 0 2006.257.02:39:37.15#ibcon#*before return 0, iclass 21, count 0 2006.257.02:39:37.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:37.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:37.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:39:37.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:39:37.15$vck44/va=2,7 2006.257.02:39:37.15#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.02:39:37.15#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.02:39:37.15#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:37.15#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:37.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:37.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:37.21#ibcon#enter wrdev, iclass 23, count 2 2006.257.02:39:37.21#ibcon#first serial, iclass 23, count 2 2006.257.02:39:37.21#ibcon#enter sib2, iclass 23, count 2 2006.257.02:39:37.21#ibcon#flushed, iclass 23, count 2 2006.257.02:39:37.21#ibcon#about to write, iclass 23, count 2 2006.257.02:39:37.21#ibcon#wrote, iclass 23, count 2 2006.257.02:39:37.21#ibcon#about to read 3, iclass 23, count 2 2006.257.02:39:37.23#ibcon#read 3, iclass 23, count 2 2006.257.02:39:37.23#ibcon#about to read 4, iclass 23, count 2 2006.257.02:39:37.23#ibcon#read 4, iclass 23, count 2 2006.257.02:39:37.23#ibcon#about to read 5, iclass 23, count 2 2006.257.02:39:37.23#ibcon#read 5, iclass 23, count 2 2006.257.02:39:37.23#ibcon#about to read 6, iclass 23, count 2 2006.257.02:39:37.23#ibcon#read 6, iclass 23, count 2 2006.257.02:39:37.23#ibcon#end of sib2, iclass 23, count 2 2006.257.02:39:37.23#ibcon#*mode == 0, iclass 23, count 2 2006.257.02:39:37.23#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.02:39:37.23#ibcon#[25=AT02-07\r\n] 2006.257.02:39:37.23#ibcon#*before write, iclass 23, count 2 2006.257.02:39:37.23#ibcon#enter sib2, iclass 23, count 2 2006.257.02:39:37.23#ibcon#flushed, iclass 23, count 2 2006.257.02:39:37.23#ibcon#about to write, iclass 23, count 2 2006.257.02:39:37.23#ibcon#wrote, iclass 23, count 2 2006.257.02:39:37.23#ibcon#about to read 3, iclass 23, count 2 2006.257.02:39:37.26#ibcon#read 3, iclass 23, count 2 2006.257.02:39:37.26#ibcon#about to read 4, iclass 23, count 2 2006.257.02:39:37.26#ibcon#read 4, iclass 23, count 2 2006.257.02:39:37.26#ibcon#about to read 5, iclass 23, count 2 2006.257.02:39:37.26#ibcon#read 5, iclass 23, count 2 2006.257.02:39:37.26#ibcon#about to read 6, iclass 23, count 2 2006.257.02:39:37.26#ibcon#read 6, iclass 23, count 2 2006.257.02:39:37.26#ibcon#end of sib2, iclass 23, count 2 2006.257.02:39:37.26#ibcon#*after write, iclass 23, count 2 2006.257.02:39:37.26#ibcon#*before return 0, iclass 23, count 2 2006.257.02:39:37.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:37.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:37.26#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.02:39:37.26#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:37.26#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:37.38#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:37.38#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:37.38#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:39:37.38#ibcon#first serial, iclass 23, count 0 2006.257.02:39:37.38#ibcon#enter sib2, iclass 23, count 0 2006.257.02:39:37.38#ibcon#flushed, iclass 23, count 0 2006.257.02:39:37.38#ibcon#about to write, iclass 23, count 0 2006.257.02:39:37.38#ibcon#wrote, iclass 23, count 0 2006.257.02:39:37.38#ibcon#about to read 3, iclass 23, count 0 2006.257.02:39:37.40#ibcon#read 3, iclass 23, count 0 2006.257.02:39:37.40#ibcon#about to read 4, iclass 23, count 0 2006.257.02:39:37.40#ibcon#read 4, iclass 23, count 0 2006.257.02:39:37.40#ibcon#about to read 5, iclass 23, count 0 2006.257.02:39:37.40#ibcon#read 5, iclass 23, count 0 2006.257.02:39:37.40#ibcon#about to read 6, iclass 23, count 0 2006.257.02:39:37.40#ibcon#read 6, iclass 23, count 0 2006.257.02:39:37.40#ibcon#end of sib2, iclass 23, count 0 2006.257.02:39:37.40#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:39:37.40#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:39:37.40#ibcon#[25=USB\r\n] 2006.257.02:39:37.40#ibcon#*before write, iclass 23, count 0 2006.257.02:39:37.40#ibcon#enter sib2, iclass 23, count 0 2006.257.02:39:37.40#ibcon#flushed, iclass 23, count 0 2006.257.02:39:37.40#ibcon#about to write, iclass 23, count 0 2006.257.02:39:37.40#ibcon#wrote, iclass 23, count 0 2006.257.02:39:37.40#ibcon#about to read 3, iclass 23, count 0 2006.257.02:39:37.43#ibcon#read 3, iclass 23, count 0 2006.257.02:39:37.43#ibcon#about to read 4, iclass 23, count 0 2006.257.02:39:37.43#ibcon#read 4, iclass 23, count 0 2006.257.02:39:37.43#ibcon#about to read 5, iclass 23, count 0 2006.257.02:39:37.43#ibcon#read 5, iclass 23, count 0 2006.257.02:39:37.43#ibcon#about to read 6, iclass 23, count 0 2006.257.02:39:37.43#ibcon#read 6, iclass 23, count 0 2006.257.02:39:37.43#ibcon#end of sib2, iclass 23, count 0 2006.257.02:39:37.43#ibcon#*after write, iclass 23, count 0 2006.257.02:39:37.43#ibcon#*before return 0, iclass 23, count 0 2006.257.02:39:37.43#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:37.43#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:37.43#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:39:37.43#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:39:37.43$vck44/valo=3,564.99 2006.257.02:39:37.43#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.02:39:37.43#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.02:39:37.43#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:37.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:37.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:37.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:37.43#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:39:37.43#ibcon#first serial, iclass 25, count 0 2006.257.02:39:37.43#ibcon#enter sib2, iclass 25, count 0 2006.257.02:39:37.43#ibcon#flushed, iclass 25, count 0 2006.257.02:39:37.43#ibcon#about to write, iclass 25, count 0 2006.257.02:39:37.43#ibcon#wrote, iclass 25, count 0 2006.257.02:39:37.43#ibcon#about to read 3, iclass 25, count 0 2006.257.02:39:37.46#ibcon#read 3, iclass 25, count 0 2006.257.02:39:37.46#ibcon#about to read 4, iclass 25, count 0 2006.257.02:39:37.46#ibcon#read 4, iclass 25, count 0 2006.257.02:39:37.46#ibcon#about to read 5, iclass 25, count 0 2006.257.02:39:37.46#ibcon#read 5, iclass 25, count 0 2006.257.02:39:37.46#ibcon#about to read 6, iclass 25, count 0 2006.257.02:39:37.46#ibcon#read 6, iclass 25, count 0 2006.257.02:39:37.46#ibcon#end of sib2, iclass 25, count 0 2006.257.02:39:37.46#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:39:37.46#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:39:37.46#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:39:37.46#ibcon#*before write, iclass 25, count 0 2006.257.02:39:37.46#ibcon#enter sib2, iclass 25, count 0 2006.257.02:39:37.46#ibcon#flushed, iclass 25, count 0 2006.257.02:39:37.46#ibcon#about to write, iclass 25, count 0 2006.257.02:39:37.46#ibcon#wrote, iclass 25, count 0 2006.257.02:39:37.46#ibcon#about to read 3, iclass 25, count 0 2006.257.02:39:37.50#ibcon#read 3, iclass 25, count 0 2006.257.02:39:37.50#ibcon#about to read 4, iclass 25, count 0 2006.257.02:39:37.50#ibcon#read 4, iclass 25, count 0 2006.257.02:39:37.50#ibcon#about to read 5, iclass 25, count 0 2006.257.02:39:37.50#ibcon#read 5, iclass 25, count 0 2006.257.02:39:37.50#ibcon#about to read 6, iclass 25, count 0 2006.257.02:39:37.50#ibcon#read 6, iclass 25, count 0 2006.257.02:39:37.50#ibcon#end of sib2, iclass 25, count 0 2006.257.02:39:37.50#ibcon#*after write, iclass 25, count 0 2006.257.02:39:37.50#ibcon#*before return 0, iclass 25, count 0 2006.257.02:39:37.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:37.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:37.50#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:39:37.50#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:39:37.50$vck44/va=3,8 2006.257.02:39:37.50#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.02:39:37.50#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.02:39:37.50#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:37.50#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:37.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:37.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:37.55#ibcon#enter wrdev, iclass 27, count 2 2006.257.02:39:37.55#ibcon#first serial, iclass 27, count 2 2006.257.02:39:37.55#ibcon#enter sib2, iclass 27, count 2 2006.257.02:39:37.55#ibcon#flushed, iclass 27, count 2 2006.257.02:39:37.55#ibcon#about to write, iclass 27, count 2 2006.257.02:39:37.55#ibcon#wrote, iclass 27, count 2 2006.257.02:39:37.55#ibcon#about to read 3, iclass 27, count 2 2006.257.02:39:37.57#ibcon#read 3, iclass 27, count 2 2006.257.02:39:37.57#ibcon#about to read 4, iclass 27, count 2 2006.257.02:39:37.57#ibcon#read 4, iclass 27, count 2 2006.257.02:39:37.57#ibcon#about to read 5, iclass 27, count 2 2006.257.02:39:37.57#ibcon#read 5, iclass 27, count 2 2006.257.02:39:37.57#ibcon#about to read 6, iclass 27, count 2 2006.257.02:39:37.57#ibcon#read 6, iclass 27, count 2 2006.257.02:39:37.57#ibcon#end of sib2, iclass 27, count 2 2006.257.02:39:37.57#ibcon#*mode == 0, iclass 27, count 2 2006.257.02:39:37.57#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.02:39:37.57#ibcon#[25=AT03-08\r\n] 2006.257.02:39:37.57#ibcon#*before write, iclass 27, count 2 2006.257.02:39:37.57#ibcon#enter sib2, iclass 27, count 2 2006.257.02:39:37.57#ibcon#flushed, iclass 27, count 2 2006.257.02:39:37.57#ibcon#about to write, iclass 27, count 2 2006.257.02:39:37.57#ibcon#wrote, iclass 27, count 2 2006.257.02:39:37.57#ibcon#about to read 3, iclass 27, count 2 2006.257.02:39:37.60#ibcon#read 3, iclass 27, count 2 2006.257.02:39:37.60#ibcon#about to read 4, iclass 27, count 2 2006.257.02:39:37.60#ibcon#read 4, iclass 27, count 2 2006.257.02:39:37.60#ibcon#about to read 5, iclass 27, count 2 2006.257.02:39:37.60#ibcon#read 5, iclass 27, count 2 2006.257.02:39:37.60#ibcon#about to read 6, iclass 27, count 2 2006.257.02:39:37.60#ibcon#read 6, iclass 27, count 2 2006.257.02:39:37.60#ibcon#end of sib2, iclass 27, count 2 2006.257.02:39:37.60#ibcon#*after write, iclass 27, count 2 2006.257.02:39:37.60#ibcon#*before return 0, iclass 27, count 2 2006.257.02:39:37.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:37.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:37.60#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.02:39:37.60#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:37.60#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:37.73#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:37.73#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:37.73#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:39:37.73#ibcon#first serial, iclass 27, count 0 2006.257.02:39:37.73#ibcon#enter sib2, iclass 27, count 0 2006.257.02:39:37.73#ibcon#flushed, iclass 27, count 0 2006.257.02:39:37.73#ibcon#about to write, iclass 27, count 0 2006.257.02:39:37.73#ibcon#wrote, iclass 27, count 0 2006.257.02:39:37.73#ibcon#about to read 3, iclass 27, count 0 2006.257.02:39:37.74#ibcon#read 3, iclass 27, count 0 2006.257.02:39:37.74#ibcon#about to read 4, iclass 27, count 0 2006.257.02:39:37.74#ibcon#read 4, iclass 27, count 0 2006.257.02:39:37.74#ibcon#about to read 5, iclass 27, count 0 2006.257.02:39:37.74#ibcon#read 5, iclass 27, count 0 2006.257.02:39:37.74#ibcon#about to read 6, iclass 27, count 0 2006.257.02:39:37.74#ibcon#read 6, iclass 27, count 0 2006.257.02:39:37.74#ibcon#end of sib2, iclass 27, count 0 2006.257.02:39:37.74#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:39:37.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:39:37.74#ibcon#[25=USB\r\n] 2006.257.02:39:37.74#ibcon#*before write, iclass 27, count 0 2006.257.02:39:37.74#ibcon#enter sib2, iclass 27, count 0 2006.257.02:39:37.74#ibcon#flushed, iclass 27, count 0 2006.257.02:39:37.74#ibcon#about to write, iclass 27, count 0 2006.257.02:39:37.74#ibcon#wrote, iclass 27, count 0 2006.257.02:39:37.74#ibcon#about to read 3, iclass 27, count 0 2006.257.02:39:37.77#ibcon#read 3, iclass 27, count 0 2006.257.02:39:37.77#ibcon#about to read 4, iclass 27, count 0 2006.257.02:39:37.77#ibcon#read 4, iclass 27, count 0 2006.257.02:39:37.77#ibcon#about to read 5, iclass 27, count 0 2006.257.02:39:37.77#ibcon#read 5, iclass 27, count 0 2006.257.02:39:37.77#ibcon#about to read 6, iclass 27, count 0 2006.257.02:39:37.77#ibcon#read 6, iclass 27, count 0 2006.257.02:39:37.77#ibcon#end of sib2, iclass 27, count 0 2006.257.02:39:37.77#ibcon#*after write, iclass 27, count 0 2006.257.02:39:37.77#ibcon#*before return 0, iclass 27, count 0 2006.257.02:39:37.77#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:37.77#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:37.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:39:37.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:39:37.77$vck44/valo=4,624.99 2006.257.02:39:37.77#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.02:39:37.77#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.02:39:37.77#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:37.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:37.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:37.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:37.77#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:39:37.77#ibcon#first serial, iclass 29, count 0 2006.257.02:39:37.77#ibcon#enter sib2, iclass 29, count 0 2006.257.02:39:37.77#ibcon#flushed, iclass 29, count 0 2006.257.02:39:37.77#ibcon#about to write, iclass 29, count 0 2006.257.02:39:37.77#ibcon#wrote, iclass 29, count 0 2006.257.02:39:37.77#ibcon#about to read 3, iclass 29, count 0 2006.257.02:39:37.80#ibcon#read 3, iclass 29, count 0 2006.257.02:39:37.80#ibcon#about to read 4, iclass 29, count 0 2006.257.02:39:37.80#ibcon#read 4, iclass 29, count 0 2006.257.02:39:37.80#ibcon#about to read 5, iclass 29, count 0 2006.257.02:39:37.80#ibcon#read 5, iclass 29, count 0 2006.257.02:39:37.80#ibcon#about to read 6, iclass 29, count 0 2006.257.02:39:37.80#ibcon#read 6, iclass 29, count 0 2006.257.02:39:37.80#ibcon#end of sib2, iclass 29, count 0 2006.257.02:39:37.80#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:39:37.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:39:37.80#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:39:37.80#ibcon#*before write, iclass 29, count 0 2006.257.02:39:37.80#ibcon#enter sib2, iclass 29, count 0 2006.257.02:39:37.80#ibcon#flushed, iclass 29, count 0 2006.257.02:39:37.80#ibcon#about to write, iclass 29, count 0 2006.257.02:39:37.80#ibcon#wrote, iclass 29, count 0 2006.257.02:39:37.80#ibcon#about to read 3, iclass 29, count 0 2006.257.02:39:37.84#ibcon#read 3, iclass 29, count 0 2006.257.02:39:37.84#ibcon#about to read 4, iclass 29, count 0 2006.257.02:39:37.84#ibcon#read 4, iclass 29, count 0 2006.257.02:39:37.84#ibcon#about to read 5, iclass 29, count 0 2006.257.02:39:37.84#ibcon#read 5, iclass 29, count 0 2006.257.02:39:37.84#ibcon#about to read 6, iclass 29, count 0 2006.257.02:39:37.84#ibcon#read 6, iclass 29, count 0 2006.257.02:39:37.84#ibcon#end of sib2, iclass 29, count 0 2006.257.02:39:37.84#ibcon#*after write, iclass 29, count 0 2006.257.02:39:37.84#ibcon#*before return 0, iclass 29, count 0 2006.257.02:39:37.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:37.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:37.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:39:37.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:39:37.84$vck44/va=4,7 2006.257.02:39:37.84#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.02:39:37.84#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.02:39:37.84#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:37.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:37.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:37.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:37.89#ibcon#enter wrdev, iclass 31, count 2 2006.257.02:39:37.89#ibcon#first serial, iclass 31, count 2 2006.257.02:39:37.89#ibcon#enter sib2, iclass 31, count 2 2006.257.02:39:37.89#ibcon#flushed, iclass 31, count 2 2006.257.02:39:37.89#ibcon#about to write, iclass 31, count 2 2006.257.02:39:37.89#ibcon#wrote, iclass 31, count 2 2006.257.02:39:37.89#ibcon#about to read 3, iclass 31, count 2 2006.257.02:39:37.91#ibcon#read 3, iclass 31, count 2 2006.257.02:39:37.91#ibcon#about to read 4, iclass 31, count 2 2006.257.02:39:37.91#ibcon#read 4, iclass 31, count 2 2006.257.02:39:37.91#ibcon#about to read 5, iclass 31, count 2 2006.257.02:39:37.91#ibcon#read 5, iclass 31, count 2 2006.257.02:39:37.91#ibcon#about to read 6, iclass 31, count 2 2006.257.02:39:37.91#ibcon#read 6, iclass 31, count 2 2006.257.02:39:37.91#ibcon#end of sib2, iclass 31, count 2 2006.257.02:39:37.91#ibcon#*mode == 0, iclass 31, count 2 2006.257.02:39:37.91#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.02:39:37.91#ibcon#[25=AT04-07\r\n] 2006.257.02:39:37.91#ibcon#*before write, iclass 31, count 2 2006.257.02:39:37.91#ibcon#enter sib2, iclass 31, count 2 2006.257.02:39:37.91#ibcon#flushed, iclass 31, count 2 2006.257.02:39:37.91#ibcon#about to write, iclass 31, count 2 2006.257.02:39:37.91#ibcon#wrote, iclass 31, count 2 2006.257.02:39:37.91#ibcon#about to read 3, iclass 31, count 2 2006.257.02:39:37.94#ibcon#read 3, iclass 31, count 2 2006.257.02:39:37.94#ibcon#about to read 4, iclass 31, count 2 2006.257.02:39:37.94#ibcon#read 4, iclass 31, count 2 2006.257.02:39:37.94#ibcon#about to read 5, iclass 31, count 2 2006.257.02:39:37.94#ibcon#read 5, iclass 31, count 2 2006.257.02:39:37.94#ibcon#about to read 6, iclass 31, count 2 2006.257.02:39:37.94#ibcon#read 6, iclass 31, count 2 2006.257.02:39:37.94#ibcon#end of sib2, iclass 31, count 2 2006.257.02:39:37.94#ibcon#*after write, iclass 31, count 2 2006.257.02:39:37.94#ibcon#*before return 0, iclass 31, count 2 2006.257.02:39:37.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:37.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:37.94#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.02:39:37.94#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:37.94#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:38.06#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:38.06#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:38.06#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:39:38.06#ibcon#first serial, iclass 31, count 0 2006.257.02:39:38.06#ibcon#enter sib2, iclass 31, count 0 2006.257.02:39:38.06#ibcon#flushed, iclass 31, count 0 2006.257.02:39:38.06#ibcon#about to write, iclass 31, count 0 2006.257.02:39:38.06#ibcon#wrote, iclass 31, count 0 2006.257.02:39:38.06#ibcon#about to read 3, iclass 31, count 0 2006.257.02:39:38.08#ibcon#read 3, iclass 31, count 0 2006.257.02:39:38.08#ibcon#about to read 4, iclass 31, count 0 2006.257.02:39:38.08#ibcon#read 4, iclass 31, count 0 2006.257.02:39:38.08#ibcon#about to read 5, iclass 31, count 0 2006.257.02:39:38.08#ibcon#read 5, iclass 31, count 0 2006.257.02:39:38.08#ibcon#about to read 6, iclass 31, count 0 2006.257.02:39:38.08#ibcon#read 6, iclass 31, count 0 2006.257.02:39:38.08#ibcon#end of sib2, iclass 31, count 0 2006.257.02:39:38.08#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:39:38.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:39:38.08#ibcon#[25=USB\r\n] 2006.257.02:39:38.08#ibcon#*before write, iclass 31, count 0 2006.257.02:39:38.08#ibcon#enter sib2, iclass 31, count 0 2006.257.02:39:38.08#ibcon#flushed, iclass 31, count 0 2006.257.02:39:38.08#ibcon#about to write, iclass 31, count 0 2006.257.02:39:38.08#ibcon#wrote, iclass 31, count 0 2006.257.02:39:38.08#ibcon#about to read 3, iclass 31, count 0 2006.257.02:39:38.11#ibcon#read 3, iclass 31, count 0 2006.257.02:39:38.11#ibcon#about to read 4, iclass 31, count 0 2006.257.02:39:38.11#ibcon#read 4, iclass 31, count 0 2006.257.02:39:38.11#ibcon#about to read 5, iclass 31, count 0 2006.257.02:39:38.11#ibcon#read 5, iclass 31, count 0 2006.257.02:39:38.11#ibcon#about to read 6, iclass 31, count 0 2006.257.02:39:38.11#ibcon#read 6, iclass 31, count 0 2006.257.02:39:38.11#ibcon#end of sib2, iclass 31, count 0 2006.257.02:39:38.11#ibcon#*after write, iclass 31, count 0 2006.257.02:39:38.11#ibcon#*before return 0, iclass 31, count 0 2006.257.02:39:38.11#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:38.11#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:38.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:39:38.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:39:38.11$vck44/valo=5,734.99 2006.257.02:39:38.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.02:39:38.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.02:39:38.11#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:38.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:38.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:38.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:38.11#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:39:38.11#ibcon#first serial, iclass 33, count 0 2006.257.02:39:38.11#ibcon#enter sib2, iclass 33, count 0 2006.257.02:39:38.11#ibcon#flushed, iclass 33, count 0 2006.257.02:39:38.11#ibcon#about to write, iclass 33, count 0 2006.257.02:39:38.11#ibcon#wrote, iclass 33, count 0 2006.257.02:39:38.11#ibcon#about to read 3, iclass 33, count 0 2006.257.02:39:38.13#ibcon#read 3, iclass 33, count 0 2006.257.02:39:38.13#ibcon#about to read 4, iclass 33, count 0 2006.257.02:39:38.13#ibcon#read 4, iclass 33, count 0 2006.257.02:39:38.13#ibcon#about to read 5, iclass 33, count 0 2006.257.02:39:38.13#ibcon#read 5, iclass 33, count 0 2006.257.02:39:38.13#ibcon#about to read 6, iclass 33, count 0 2006.257.02:39:38.13#ibcon#read 6, iclass 33, count 0 2006.257.02:39:38.13#ibcon#end of sib2, iclass 33, count 0 2006.257.02:39:38.13#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:39:38.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:39:38.13#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:39:38.13#ibcon#*before write, iclass 33, count 0 2006.257.02:39:38.13#ibcon#enter sib2, iclass 33, count 0 2006.257.02:39:38.13#ibcon#flushed, iclass 33, count 0 2006.257.02:39:38.13#ibcon#about to write, iclass 33, count 0 2006.257.02:39:38.13#ibcon#wrote, iclass 33, count 0 2006.257.02:39:38.13#ibcon#about to read 3, iclass 33, count 0 2006.257.02:39:38.17#ibcon#read 3, iclass 33, count 0 2006.257.02:39:38.17#ibcon#about to read 4, iclass 33, count 0 2006.257.02:39:38.17#ibcon#read 4, iclass 33, count 0 2006.257.02:39:38.17#ibcon#about to read 5, iclass 33, count 0 2006.257.02:39:38.17#ibcon#read 5, iclass 33, count 0 2006.257.02:39:38.17#ibcon#about to read 6, iclass 33, count 0 2006.257.02:39:38.17#ibcon#read 6, iclass 33, count 0 2006.257.02:39:38.17#ibcon#end of sib2, iclass 33, count 0 2006.257.02:39:38.17#ibcon#*after write, iclass 33, count 0 2006.257.02:39:38.17#ibcon#*before return 0, iclass 33, count 0 2006.257.02:39:38.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:38.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:38.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:39:38.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:39:38.17$vck44/va=5,4 2006.257.02:39:38.17#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.02:39:38.17#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.02:39:38.17#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:38.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:38.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:38.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:38.23#ibcon#enter wrdev, iclass 35, count 2 2006.257.02:39:38.23#ibcon#first serial, iclass 35, count 2 2006.257.02:39:38.23#ibcon#enter sib2, iclass 35, count 2 2006.257.02:39:38.23#ibcon#flushed, iclass 35, count 2 2006.257.02:39:38.23#ibcon#about to write, iclass 35, count 2 2006.257.02:39:38.23#ibcon#wrote, iclass 35, count 2 2006.257.02:39:38.23#ibcon#about to read 3, iclass 35, count 2 2006.257.02:39:38.25#ibcon#read 3, iclass 35, count 2 2006.257.02:39:38.25#ibcon#about to read 4, iclass 35, count 2 2006.257.02:39:38.25#ibcon#read 4, iclass 35, count 2 2006.257.02:39:38.25#ibcon#about to read 5, iclass 35, count 2 2006.257.02:39:38.25#ibcon#read 5, iclass 35, count 2 2006.257.02:39:38.25#ibcon#about to read 6, iclass 35, count 2 2006.257.02:39:38.25#ibcon#read 6, iclass 35, count 2 2006.257.02:39:38.25#ibcon#end of sib2, iclass 35, count 2 2006.257.02:39:38.25#ibcon#*mode == 0, iclass 35, count 2 2006.257.02:39:38.25#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.02:39:38.25#ibcon#[25=AT05-04\r\n] 2006.257.02:39:38.25#ibcon#*before write, iclass 35, count 2 2006.257.02:39:38.25#ibcon#enter sib2, iclass 35, count 2 2006.257.02:39:38.25#ibcon#flushed, iclass 35, count 2 2006.257.02:39:38.25#ibcon#about to write, iclass 35, count 2 2006.257.02:39:38.25#ibcon#wrote, iclass 35, count 2 2006.257.02:39:38.25#ibcon#about to read 3, iclass 35, count 2 2006.257.02:39:38.28#ibcon#read 3, iclass 35, count 2 2006.257.02:39:38.28#ibcon#about to read 4, iclass 35, count 2 2006.257.02:39:38.28#ibcon#read 4, iclass 35, count 2 2006.257.02:39:38.28#ibcon#about to read 5, iclass 35, count 2 2006.257.02:39:38.28#ibcon#read 5, iclass 35, count 2 2006.257.02:39:38.28#ibcon#about to read 6, iclass 35, count 2 2006.257.02:39:38.28#ibcon#read 6, iclass 35, count 2 2006.257.02:39:38.28#ibcon#end of sib2, iclass 35, count 2 2006.257.02:39:38.28#ibcon#*after write, iclass 35, count 2 2006.257.02:39:38.28#ibcon#*before return 0, iclass 35, count 2 2006.257.02:39:38.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:38.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:38.28#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.02:39:38.28#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:38.28#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:38.40#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:38.40#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:38.40#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:39:38.40#ibcon#first serial, iclass 35, count 0 2006.257.02:39:38.40#ibcon#enter sib2, iclass 35, count 0 2006.257.02:39:38.40#ibcon#flushed, iclass 35, count 0 2006.257.02:39:38.40#ibcon#about to write, iclass 35, count 0 2006.257.02:39:38.40#ibcon#wrote, iclass 35, count 0 2006.257.02:39:38.40#ibcon#about to read 3, iclass 35, count 0 2006.257.02:39:38.42#ibcon#read 3, iclass 35, count 0 2006.257.02:39:38.42#ibcon#about to read 4, iclass 35, count 0 2006.257.02:39:38.42#ibcon#read 4, iclass 35, count 0 2006.257.02:39:38.42#ibcon#about to read 5, iclass 35, count 0 2006.257.02:39:38.42#ibcon#read 5, iclass 35, count 0 2006.257.02:39:38.42#ibcon#about to read 6, iclass 35, count 0 2006.257.02:39:38.42#ibcon#read 6, iclass 35, count 0 2006.257.02:39:38.42#ibcon#end of sib2, iclass 35, count 0 2006.257.02:39:38.42#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:39:38.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:39:38.42#ibcon#[25=USB\r\n] 2006.257.02:39:38.42#ibcon#*before write, iclass 35, count 0 2006.257.02:39:38.42#ibcon#enter sib2, iclass 35, count 0 2006.257.02:39:38.42#ibcon#flushed, iclass 35, count 0 2006.257.02:39:38.42#ibcon#about to write, iclass 35, count 0 2006.257.02:39:38.42#ibcon#wrote, iclass 35, count 0 2006.257.02:39:38.42#ibcon#about to read 3, iclass 35, count 0 2006.257.02:39:38.45#ibcon#read 3, iclass 35, count 0 2006.257.02:39:38.45#ibcon#about to read 4, iclass 35, count 0 2006.257.02:39:38.45#ibcon#read 4, iclass 35, count 0 2006.257.02:39:38.45#ibcon#about to read 5, iclass 35, count 0 2006.257.02:39:38.45#ibcon#read 5, iclass 35, count 0 2006.257.02:39:38.45#ibcon#about to read 6, iclass 35, count 0 2006.257.02:39:38.45#ibcon#read 6, iclass 35, count 0 2006.257.02:39:38.45#ibcon#end of sib2, iclass 35, count 0 2006.257.02:39:38.45#ibcon#*after write, iclass 35, count 0 2006.257.02:39:38.45#ibcon#*before return 0, iclass 35, count 0 2006.257.02:39:38.45#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:38.45#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:38.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:39:38.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:39:38.45$vck44/valo=6,814.99 2006.257.02:39:38.45#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.02:39:38.45#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.02:39:38.45#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:38.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:38.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:38.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:38.45#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:39:38.45#ibcon#first serial, iclass 37, count 0 2006.257.02:39:38.45#ibcon#enter sib2, iclass 37, count 0 2006.257.02:39:38.45#ibcon#flushed, iclass 37, count 0 2006.257.02:39:38.45#ibcon#about to write, iclass 37, count 0 2006.257.02:39:38.45#ibcon#wrote, iclass 37, count 0 2006.257.02:39:38.45#ibcon#about to read 3, iclass 37, count 0 2006.257.02:39:38.47#ibcon#read 3, iclass 37, count 0 2006.257.02:39:38.47#ibcon#about to read 4, iclass 37, count 0 2006.257.02:39:38.47#ibcon#read 4, iclass 37, count 0 2006.257.02:39:38.47#ibcon#about to read 5, iclass 37, count 0 2006.257.02:39:38.47#ibcon#read 5, iclass 37, count 0 2006.257.02:39:38.47#ibcon#about to read 6, iclass 37, count 0 2006.257.02:39:38.47#ibcon#read 6, iclass 37, count 0 2006.257.02:39:38.47#ibcon#end of sib2, iclass 37, count 0 2006.257.02:39:38.47#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:39:38.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:39:38.47#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:39:38.47#ibcon#*before write, iclass 37, count 0 2006.257.02:39:38.47#ibcon#enter sib2, iclass 37, count 0 2006.257.02:39:38.47#ibcon#flushed, iclass 37, count 0 2006.257.02:39:38.47#ibcon#about to write, iclass 37, count 0 2006.257.02:39:38.47#ibcon#wrote, iclass 37, count 0 2006.257.02:39:38.47#ibcon#about to read 3, iclass 37, count 0 2006.257.02:39:38.51#ibcon#read 3, iclass 37, count 0 2006.257.02:39:38.51#ibcon#about to read 4, iclass 37, count 0 2006.257.02:39:38.51#ibcon#read 4, iclass 37, count 0 2006.257.02:39:38.51#ibcon#about to read 5, iclass 37, count 0 2006.257.02:39:38.51#ibcon#read 5, iclass 37, count 0 2006.257.02:39:38.51#ibcon#about to read 6, iclass 37, count 0 2006.257.02:39:38.51#ibcon#read 6, iclass 37, count 0 2006.257.02:39:38.51#ibcon#end of sib2, iclass 37, count 0 2006.257.02:39:38.51#ibcon#*after write, iclass 37, count 0 2006.257.02:39:38.51#ibcon#*before return 0, iclass 37, count 0 2006.257.02:39:38.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:38.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:38.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:39:38.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:39:38.51$vck44/va=6,4 2006.257.02:39:38.51#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.02:39:38.51#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.02:39:38.51#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:38.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:38.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:38.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:38.57#ibcon#enter wrdev, iclass 39, count 2 2006.257.02:39:38.57#ibcon#first serial, iclass 39, count 2 2006.257.02:39:38.57#ibcon#enter sib2, iclass 39, count 2 2006.257.02:39:38.57#ibcon#flushed, iclass 39, count 2 2006.257.02:39:38.57#ibcon#about to write, iclass 39, count 2 2006.257.02:39:38.57#ibcon#wrote, iclass 39, count 2 2006.257.02:39:38.57#ibcon#about to read 3, iclass 39, count 2 2006.257.02:39:38.59#ibcon#read 3, iclass 39, count 2 2006.257.02:39:38.59#ibcon#about to read 4, iclass 39, count 2 2006.257.02:39:38.59#ibcon#read 4, iclass 39, count 2 2006.257.02:39:38.59#ibcon#about to read 5, iclass 39, count 2 2006.257.02:39:38.59#ibcon#read 5, iclass 39, count 2 2006.257.02:39:38.59#ibcon#about to read 6, iclass 39, count 2 2006.257.02:39:38.59#ibcon#read 6, iclass 39, count 2 2006.257.02:39:38.59#ibcon#end of sib2, iclass 39, count 2 2006.257.02:39:38.59#ibcon#*mode == 0, iclass 39, count 2 2006.257.02:39:38.59#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.02:39:38.59#ibcon#[25=AT06-04\r\n] 2006.257.02:39:38.59#ibcon#*before write, iclass 39, count 2 2006.257.02:39:38.59#ibcon#enter sib2, iclass 39, count 2 2006.257.02:39:38.59#ibcon#flushed, iclass 39, count 2 2006.257.02:39:38.59#ibcon#about to write, iclass 39, count 2 2006.257.02:39:38.59#ibcon#wrote, iclass 39, count 2 2006.257.02:39:38.59#ibcon#about to read 3, iclass 39, count 2 2006.257.02:39:38.62#ibcon#read 3, iclass 39, count 2 2006.257.02:39:38.62#ibcon#about to read 4, iclass 39, count 2 2006.257.02:39:38.62#ibcon#read 4, iclass 39, count 2 2006.257.02:39:38.62#ibcon#about to read 5, iclass 39, count 2 2006.257.02:39:38.62#ibcon#read 5, iclass 39, count 2 2006.257.02:39:38.62#ibcon#about to read 6, iclass 39, count 2 2006.257.02:39:38.62#ibcon#read 6, iclass 39, count 2 2006.257.02:39:38.62#ibcon#end of sib2, iclass 39, count 2 2006.257.02:39:38.62#ibcon#*after write, iclass 39, count 2 2006.257.02:39:38.62#ibcon#*before return 0, iclass 39, count 2 2006.257.02:39:38.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:38.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:38.62#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.02:39:38.62#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:38.62#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:38.74#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:38.74#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:38.74#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:39:38.74#ibcon#first serial, iclass 39, count 0 2006.257.02:39:38.74#ibcon#enter sib2, iclass 39, count 0 2006.257.02:39:38.74#ibcon#flushed, iclass 39, count 0 2006.257.02:39:38.74#ibcon#about to write, iclass 39, count 0 2006.257.02:39:38.74#ibcon#wrote, iclass 39, count 0 2006.257.02:39:38.74#ibcon#about to read 3, iclass 39, count 0 2006.257.02:39:38.76#ibcon#read 3, iclass 39, count 0 2006.257.02:39:38.76#ibcon#about to read 4, iclass 39, count 0 2006.257.02:39:38.76#ibcon#read 4, iclass 39, count 0 2006.257.02:39:38.76#ibcon#about to read 5, iclass 39, count 0 2006.257.02:39:38.76#ibcon#read 5, iclass 39, count 0 2006.257.02:39:38.76#ibcon#about to read 6, iclass 39, count 0 2006.257.02:39:38.76#ibcon#read 6, iclass 39, count 0 2006.257.02:39:38.76#ibcon#end of sib2, iclass 39, count 0 2006.257.02:39:38.76#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:39:38.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:39:38.76#ibcon#[25=USB\r\n] 2006.257.02:39:38.76#ibcon#*before write, iclass 39, count 0 2006.257.02:39:38.76#ibcon#enter sib2, iclass 39, count 0 2006.257.02:39:38.76#ibcon#flushed, iclass 39, count 0 2006.257.02:39:38.76#ibcon#about to write, iclass 39, count 0 2006.257.02:39:38.76#ibcon#wrote, iclass 39, count 0 2006.257.02:39:38.76#ibcon#about to read 3, iclass 39, count 0 2006.257.02:39:38.79#ibcon#read 3, iclass 39, count 0 2006.257.02:39:38.79#ibcon#about to read 4, iclass 39, count 0 2006.257.02:39:38.79#ibcon#read 4, iclass 39, count 0 2006.257.02:39:38.79#ibcon#about to read 5, iclass 39, count 0 2006.257.02:39:38.79#ibcon#read 5, iclass 39, count 0 2006.257.02:39:38.79#ibcon#about to read 6, iclass 39, count 0 2006.257.02:39:38.79#ibcon#read 6, iclass 39, count 0 2006.257.02:39:38.79#ibcon#end of sib2, iclass 39, count 0 2006.257.02:39:38.79#ibcon#*after write, iclass 39, count 0 2006.257.02:39:38.79#ibcon#*before return 0, iclass 39, count 0 2006.257.02:39:38.79#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:38.79#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:38.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:39:38.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:39:38.79$vck44/valo=7,864.99 2006.257.02:39:38.79#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.02:39:38.79#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.02:39:38.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:38.79#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:38.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:38.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:38.79#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:39:38.79#ibcon#first serial, iclass 3, count 0 2006.257.02:39:38.79#ibcon#enter sib2, iclass 3, count 0 2006.257.02:39:38.79#ibcon#flushed, iclass 3, count 0 2006.257.02:39:38.79#ibcon#about to write, iclass 3, count 0 2006.257.02:39:38.79#ibcon#wrote, iclass 3, count 0 2006.257.02:39:38.79#ibcon#about to read 3, iclass 3, count 0 2006.257.02:39:38.81#ibcon#read 3, iclass 3, count 0 2006.257.02:39:38.81#ibcon#about to read 4, iclass 3, count 0 2006.257.02:39:38.81#ibcon#read 4, iclass 3, count 0 2006.257.02:39:38.81#ibcon#about to read 5, iclass 3, count 0 2006.257.02:39:38.81#ibcon#read 5, iclass 3, count 0 2006.257.02:39:38.81#ibcon#about to read 6, iclass 3, count 0 2006.257.02:39:38.81#ibcon#read 6, iclass 3, count 0 2006.257.02:39:38.81#ibcon#end of sib2, iclass 3, count 0 2006.257.02:39:38.81#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:39:38.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:39:38.81#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:39:38.81#ibcon#*before write, iclass 3, count 0 2006.257.02:39:38.81#ibcon#enter sib2, iclass 3, count 0 2006.257.02:39:38.81#ibcon#flushed, iclass 3, count 0 2006.257.02:39:38.81#ibcon#about to write, iclass 3, count 0 2006.257.02:39:38.81#ibcon#wrote, iclass 3, count 0 2006.257.02:39:38.81#ibcon#about to read 3, iclass 3, count 0 2006.257.02:39:38.85#ibcon#read 3, iclass 3, count 0 2006.257.02:39:38.85#ibcon#about to read 4, iclass 3, count 0 2006.257.02:39:38.85#ibcon#read 4, iclass 3, count 0 2006.257.02:39:38.85#ibcon#about to read 5, iclass 3, count 0 2006.257.02:39:38.85#ibcon#read 5, iclass 3, count 0 2006.257.02:39:38.85#ibcon#about to read 6, iclass 3, count 0 2006.257.02:39:38.85#ibcon#read 6, iclass 3, count 0 2006.257.02:39:38.85#ibcon#end of sib2, iclass 3, count 0 2006.257.02:39:38.85#ibcon#*after write, iclass 3, count 0 2006.257.02:39:38.85#ibcon#*before return 0, iclass 3, count 0 2006.257.02:39:38.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:38.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:38.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:39:38.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:39:38.85$vck44/va=7,4 2006.257.02:39:38.85#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.02:39:38.85#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.02:39:38.85#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:38.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:38.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:38.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:38.91#ibcon#enter wrdev, iclass 5, count 2 2006.257.02:39:38.91#ibcon#first serial, iclass 5, count 2 2006.257.02:39:38.91#ibcon#enter sib2, iclass 5, count 2 2006.257.02:39:38.91#ibcon#flushed, iclass 5, count 2 2006.257.02:39:38.91#ibcon#about to write, iclass 5, count 2 2006.257.02:39:38.91#ibcon#wrote, iclass 5, count 2 2006.257.02:39:38.91#ibcon#about to read 3, iclass 5, count 2 2006.257.02:39:38.93#ibcon#read 3, iclass 5, count 2 2006.257.02:39:38.93#ibcon#about to read 4, iclass 5, count 2 2006.257.02:39:38.93#ibcon#read 4, iclass 5, count 2 2006.257.02:39:38.93#ibcon#about to read 5, iclass 5, count 2 2006.257.02:39:38.93#ibcon#read 5, iclass 5, count 2 2006.257.02:39:38.93#ibcon#about to read 6, iclass 5, count 2 2006.257.02:39:38.93#ibcon#read 6, iclass 5, count 2 2006.257.02:39:38.93#ibcon#end of sib2, iclass 5, count 2 2006.257.02:39:38.93#ibcon#*mode == 0, iclass 5, count 2 2006.257.02:39:38.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.02:39:38.93#ibcon#[25=AT07-04\r\n] 2006.257.02:39:38.93#ibcon#*before write, iclass 5, count 2 2006.257.02:39:38.93#ibcon#enter sib2, iclass 5, count 2 2006.257.02:39:38.93#ibcon#flushed, iclass 5, count 2 2006.257.02:39:38.93#ibcon#about to write, iclass 5, count 2 2006.257.02:39:38.93#ibcon#wrote, iclass 5, count 2 2006.257.02:39:38.93#ibcon#about to read 3, iclass 5, count 2 2006.257.02:39:38.96#ibcon#read 3, iclass 5, count 2 2006.257.02:39:38.96#ibcon#about to read 4, iclass 5, count 2 2006.257.02:39:38.96#ibcon#read 4, iclass 5, count 2 2006.257.02:39:38.96#ibcon#about to read 5, iclass 5, count 2 2006.257.02:39:38.96#ibcon#read 5, iclass 5, count 2 2006.257.02:39:38.96#ibcon#about to read 6, iclass 5, count 2 2006.257.02:39:38.96#ibcon#read 6, iclass 5, count 2 2006.257.02:39:38.96#ibcon#end of sib2, iclass 5, count 2 2006.257.02:39:38.96#ibcon#*after write, iclass 5, count 2 2006.257.02:39:38.96#ibcon#*before return 0, iclass 5, count 2 2006.257.02:39:38.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:38.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:38.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.02:39:38.96#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:38.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:39.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:39.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:39.08#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:39:39.08#ibcon#first serial, iclass 5, count 0 2006.257.02:39:39.08#ibcon#enter sib2, iclass 5, count 0 2006.257.02:39:39.08#ibcon#flushed, iclass 5, count 0 2006.257.02:39:39.08#ibcon#about to write, iclass 5, count 0 2006.257.02:39:39.08#ibcon#wrote, iclass 5, count 0 2006.257.02:39:39.08#ibcon#about to read 3, iclass 5, count 0 2006.257.02:39:39.10#ibcon#read 3, iclass 5, count 0 2006.257.02:39:39.10#ibcon#about to read 4, iclass 5, count 0 2006.257.02:39:39.10#ibcon#read 4, iclass 5, count 0 2006.257.02:39:39.10#ibcon#about to read 5, iclass 5, count 0 2006.257.02:39:39.10#ibcon#read 5, iclass 5, count 0 2006.257.02:39:39.10#ibcon#about to read 6, iclass 5, count 0 2006.257.02:39:39.10#ibcon#read 6, iclass 5, count 0 2006.257.02:39:39.10#ibcon#end of sib2, iclass 5, count 0 2006.257.02:39:39.10#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:39:39.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:39:39.10#ibcon#[25=USB\r\n] 2006.257.02:39:39.10#ibcon#*before write, iclass 5, count 0 2006.257.02:39:39.10#ibcon#enter sib2, iclass 5, count 0 2006.257.02:39:39.10#ibcon#flushed, iclass 5, count 0 2006.257.02:39:39.10#ibcon#about to write, iclass 5, count 0 2006.257.02:39:39.10#ibcon#wrote, iclass 5, count 0 2006.257.02:39:39.10#ibcon#about to read 3, iclass 5, count 0 2006.257.02:39:39.13#ibcon#read 3, iclass 5, count 0 2006.257.02:39:39.13#ibcon#about to read 4, iclass 5, count 0 2006.257.02:39:39.13#ibcon#read 4, iclass 5, count 0 2006.257.02:39:39.13#ibcon#about to read 5, iclass 5, count 0 2006.257.02:39:39.13#ibcon#read 5, iclass 5, count 0 2006.257.02:39:39.13#ibcon#about to read 6, iclass 5, count 0 2006.257.02:39:39.13#ibcon#read 6, iclass 5, count 0 2006.257.02:39:39.13#ibcon#end of sib2, iclass 5, count 0 2006.257.02:39:39.13#ibcon#*after write, iclass 5, count 0 2006.257.02:39:39.13#ibcon#*before return 0, iclass 5, count 0 2006.257.02:39:39.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:39.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:39.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:39:39.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:39:39.13$vck44/valo=8,884.99 2006.257.02:39:39.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.02:39:39.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.02:39:39.13#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:39.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:39.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:39.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:39.13#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:39:39.13#ibcon#first serial, iclass 7, count 0 2006.257.02:39:39.13#ibcon#enter sib2, iclass 7, count 0 2006.257.02:39:39.13#ibcon#flushed, iclass 7, count 0 2006.257.02:39:39.13#ibcon#about to write, iclass 7, count 0 2006.257.02:39:39.13#ibcon#wrote, iclass 7, count 0 2006.257.02:39:39.13#ibcon#about to read 3, iclass 7, count 0 2006.257.02:39:39.15#ibcon#read 3, iclass 7, count 0 2006.257.02:39:39.15#ibcon#about to read 4, iclass 7, count 0 2006.257.02:39:39.15#ibcon#read 4, iclass 7, count 0 2006.257.02:39:39.15#ibcon#about to read 5, iclass 7, count 0 2006.257.02:39:39.15#ibcon#read 5, iclass 7, count 0 2006.257.02:39:39.15#ibcon#about to read 6, iclass 7, count 0 2006.257.02:39:39.15#ibcon#read 6, iclass 7, count 0 2006.257.02:39:39.15#ibcon#end of sib2, iclass 7, count 0 2006.257.02:39:39.15#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:39:39.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:39:39.15#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:39:39.15#ibcon#*before write, iclass 7, count 0 2006.257.02:39:39.15#ibcon#enter sib2, iclass 7, count 0 2006.257.02:39:39.15#ibcon#flushed, iclass 7, count 0 2006.257.02:39:39.15#ibcon#about to write, iclass 7, count 0 2006.257.02:39:39.15#ibcon#wrote, iclass 7, count 0 2006.257.02:39:39.15#ibcon#about to read 3, iclass 7, count 0 2006.257.02:39:39.19#ibcon#read 3, iclass 7, count 0 2006.257.02:39:39.19#ibcon#about to read 4, iclass 7, count 0 2006.257.02:39:39.19#ibcon#read 4, iclass 7, count 0 2006.257.02:39:39.19#ibcon#about to read 5, iclass 7, count 0 2006.257.02:39:39.19#ibcon#read 5, iclass 7, count 0 2006.257.02:39:39.19#ibcon#about to read 6, iclass 7, count 0 2006.257.02:39:39.19#ibcon#read 6, iclass 7, count 0 2006.257.02:39:39.19#ibcon#end of sib2, iclass 7, count 0 2006.257.02:39:39.19#ibcon#*after write, iclass 7, count 0 2006.257.02:39:39.19#ibcon#*before return 0, iclass 7, count 0 2006.257.02:39:39.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:39.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:39.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:39:39.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:39:39.19$vck44/va=8,4 2006.257.02:39:39.19#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.02:39:39.19#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.02:39:39.19#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:39.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:39:39.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:39:39.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:39:39.25#ibcon#enter wrdev, iclass 11, count 2 2006.257.02:39:39.25#ibcon#first serial, iclass 11, count 2 2006.257.02:39:39.25#ibcon#enter sib2, iclass 11, count 2 2006.257.02:39:39.25#ibcon#flushed, iclass 11, count 2 2006.257.02:39:39.25#ibcon#about to write, iclass 11, count 2 2006.257.02:39:39.25#ibcon#wrote, iclass 11, count 2 2006.257.02:39:39.25#ibcon#about to read 3, iclass 11, count 2 2006.257.02:39:39.27#ibcon#read 3, iclass 11, count 2 2006.257.02:39:39.27#ibcon#about to read 4, iclass 11, count 2 2006.257.02:39:39.27#ibcon#read 4, iclass 11, count 2 2006.257.02:39:39.27#ibcon#about to read 5, iclass 11, count 2 2006.257.02:39:39.27#ibcon#read 5, iclass 11, count 2 2006.257.02:39:39.27#ibcon#about to read 6, iclass 11, count 2 2006.257.02:39:39.27#ibcon#read 6, iclass 11, count 2 2006.257.02:39:39.27#ibcon#end of sib2, iclass 11, count 2 2006.257.02:39:39.27#ibcon#*mode == 0, iclass 11, count 2 2006.257.02:39:39.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.02:39:39.27#ibcon#[25=AT08-04\r\n] 2006.257.02:39:39.27#ibcon#*before write, iclass 11, count 2 2006.257.02:39:39.27#ibcon#enter sib2, iclass 11, count 2 2006.257.02:39:39.27#ibcon#flushed, iclass 11, count 2 2006.257.02:39:39.27#ibcon#about to write, iclass 11, count 2 2006.257.02:39:39.27#ibcon#wrote, iclass 11, count 2 2006.257.02:39:39.27#ibcon#about to read 3, iclass 11, count 2 2006.257.02:39:39.30#ibcon#read 3, iclass 11, count 2 2006.257.02:39:39.30#ibcon#about to read 4, iclass 11, count 2 2006.257.02:39:39.30#ibcon#read 4, iclass 11, count 2 2006.257.02:39:39.30#ibcon#about to read 5, iclass 11, count 2 2006.257.02:39:39.30#ibcon#read 5, iclass 11, count 2 2006.257.02:39:39.30#ibcon#about to read 6, iclass 11, count 2 2006.257.02:39:39.30#ibcon#read 6, iclass 11, count 2 2006.257.02:39:39.30#ibcon#end of sib2, iclass 11, count 2 2006.257.02:39:39.30#ibcon#*after write, iclass 11, count 2 2006.257.02:39:39.30#ibcon#*before return 0, iclass 11, count 2 2006.257.02:39:39.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:39:39.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:39:39.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.02:39:39.30#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:39.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:39:39.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:39:39.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:39:39.42#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:39:39.42#ibcon#first serial, iclass 11, count 0 2006.257.02:39:39.42#ibcon#enter sib2, iclass 11, count 0 2006.257.02:39:39.42#ibcon#flushed, iclass 11, count 0 2006.257.02:39:39.42#ibcon#about to write, iclass 11, count 0 2006.257.02:39:39.42#ibcon#wrote, iclass 11, count 0 2006.257.02:39:39.42#ibcon#about to read 3, iclass 11, count 0 2006.257.02:39:39.44#ibcon#read 3, iclass 11, count 0 2006.257.02:39:39.44#ibcon#about to read 4, iclass 11, count 0 2006.257.02:39:39.44#ibcon#read 4, iclass 11, count 0 2006.257.02:39:39.44#ibcon#about to read 5, iclass 11, count 0 2006.257.02:39:39.44#ibcon#read 5, iclass 11, count 0 2006.257.02:39:39.44#ibcon#about to read 6, iclass 11, count 0 2006.257.02:39:39.44#ibcon#read 6, iclass 11, count 0 2006.257.02:39:39.44#ibcon#end of sib2, iclass 11, count 0 2006.257.02:39:39.44#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:39:39.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:39:39.44#ibcon#[25=USB\r\n] 2006.257.02:39:39.44#ibcon#*before write, iclass 11, count 0 2006.257.02:39:39.44#ibcon#enter sib2, iclass 11, count 0 2006.257.02:39:39.44#ibcon#flushed, iclass 11, count 0 2006.257.02:39:39.44#ibcon#about to write, iclass 11, count 0 2006.257.02:39:39.44#ibcon#wrote, iclass 11, count 0 2006.257.02:39:39.44#ibcon#about to read 3, iclass 11, count 0 2006.257.02:39:39.47#ibcon#read 3, iclass 11, count 0 2006.257.02:39:39.47#ibcon#about to read 4, iclass 11, count 0 2006.257.02:39:39.47#ibcon#read 4, iclass 11, count 0 2006.257.02:39:39.47#ibcon#about to read 5, iclass 11, count 0 2006.257.02:39:39.47#ibcon#read 5, iclass 11, count 0 2006.257.02:39:39.47#ibcon#about to read 6, iclass 11, count 0 2006.257.02:39:39.47#ibcon#read 6, iclass 11, count 0 2006.257.02:39:39.47#ibcon#end of sib2, iclass 11, count 0 2006.257.02:39:39.47#ibcon#*after write, iclass 11, count 0 2006.257.02:39:39.47#ibcon#*before return 0, iclass 11, count 0 2006.257.02:39:39.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:39:39.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:39:39.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:39:39.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:39:39.47$vck44/vblo=1,629.99 2006.257.02:39:39.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.02:39:39.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.02:39:39.47#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:39.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:39:39.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:39:39.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:39:39.47#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:39:39.47#ibcon#first serial, iclass 13, count 0 2006.257.02:39:39.47#ibcon#enter sib2, iclass 13, count 0 2006.257.02:39:39.47#ibcon#flushed, iclass 13, count 0 2006.257.02:39:39.47#ibcon#about to write, iclass 13, count 0 2006.257.02:39:39.47#ibcon#wrote, iclass 13, count 0 2006.257.02:39:39.47#ibcon#about to read 3, iclass 13, count 0 2006.257.02:39:39.49#ibcon#read 3, iclass 13, count 0 2006.257.02:39:39.49#ibcon#about to read 4, iclass 13, count 0 2006.257.02:39:39.49#ibcon#read 4, iclass 13, count 0 2006.257.02:39:39.49#ibcon#about to read 5, iclass 13, count 0 2006.257.02:39:39.49#ibcon#read 5, iclass 13, count 0 2006.257.02:39:39.49#ibcon#about to read 6, iclass 13, count 0 2006.257.02:39:39.49#ibcon#read 6, iclass 13, count 0 2006.257.02:39:39.49#ibcon#end of sib2, iclass 13, count 0 2006.257.02:39:39.49#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:39:39.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:39:39.49#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:39:39.49#ibcon#*before write, iclass 13, count 0 2006.257.02:39:39.49#ibcon#enter sib2, iclass 13, count 0 2006.257.02:39:39.49#ibcon#flushed, iclass 13, count 0 2006.257.02:39:39.49#ibcon#about to write, iclass 13, count 0 2006.257.02:39:39.49#ibcon#wrote, iclass 13, count 0 2006.257.02:39:39.49#ibcon#about to read 3, iclass 13, count 0 2006.257.02:39:39.53#ibcon#read 3, iclass 13, count 0 2006.257.02:39:39.53#ibcon#about to read 4, iclass 13, count 0 2006.257.02:39:39.53#ibcon#read 4, iclass 13, count 0 2006.257.02:39:39.53#ibcon#about to read 5, iclass 13, count 0 2006.257.02:39:39.53#ibcon#read 5, iclass 13, count 0 2006.257.02:39:39.53#ibcon#about to read 6, iclass 13, count 0 2006.257.02:39:39.53#ibcon#read 6, iclass 13, count 0 2006.257.02:39:39.53#ibcon#end of sib2, iclass 13, count 0 2006.257.02:39:39.53#ibcon#*after write, iclass 13, count 0 2006.257.02:39:39.53#ibcon#*before return 0, iclass 13, count 0 2006.257.02:39:39.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:39:39.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:39:39.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:39:39.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:39:39.53$vck44/vb=1,4 2006.257.02:39:39.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.02:39:39.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.02:39:39.53#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:39.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:39:39.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:39:39.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:39:39.53#ibcon#enter wrdev, iclass 15, count 2 2006.257.02:39:39.53#ibcon#first serial, iclass 15, count 2 2006.257.02:39:39.53#ibcon#enter sib2, iclass 15, count 2 2006.257.02:39:39.53#ibcon#flushed, iclass 15, count 2 2006.257.02:39:39.53#ibcon#about to write, iclass 15, count 2 2006.257.02:39:39.53#ibcon#wrote, iclass 15, count 2 2006.257.02:39:39.53#ibcon#about to read 3, iclass 15, count 2 2006.257.02:39:39.55#ibcon#read 3, iclass 15, count 2 2006.257.02:39:39.55#ibcon#about to read 4, iclass 15, count 2 2006.257.02:39:39.55#ibcon#read 4, iclass 15, count 2 2006.257.02:39:39.55#ibcon#about to read 5, iclass 15, count 2 2006.257.02:39:39.55#ibcon#read 5, iclass 15, count 2 2006.257.02:39:39.55#ibcon#about to read 6, iclass 15, count 2 2006.257.02:39:39.55#ibcon#read 6, iclass 15, count 2 2006.257.02:39:39.55#ibcon#end of sib2, iclass 15, count 2 2006.257.02:39:39.55#ibcon#*mode == 0, iclass 15, count 2 2006.257.02:39:39.55#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.02:39:39.55#ibcon#[27=AT01-04\r\n] 2006.257.02:39:39.55#ibcon#*before write, iclass 15, count 2 2006.257.02:39:39.55#ibcon#enter sib2, iclass 15, count 2 2006.257.02:39:39.55#ibcon#flushed, iclass 15, count 2 2006.257.02:39:39.55#ibcon#about to write, iclass 15, count 2 2006.257.02:39:39.55#ibcon#wrote, iclass 15, count 2 2006.257.02:39:39.55#ibcon#about to read 3, iclass 15, count 2 2006.257.02:39:39.58#ibcon#read 3, iclass 15, count 2 2006.257.02:39:39.58#ibcon#about to read 4, iclass 15, count 2 2006.257.02:39:39.58#ibcon#read 4, iclass 15, count 2 2006.257.02:39:39.58#ibcon#about to read 5, iclass 15, count 2 2006.257.02:39:39.58#ibcon#read 5, iclass 15, count 2 2006.257.02:39:39.58#ibcon#about to read 6, iclass 15, count 2 2006.257.02:39:39.58#ibcon#read 6, iclass 15, count 2 2006.257.02:39:39.58#ibcon#end of sib2, iclass 15, count 2 2006.257.02:39:39.58#ibcon#*after write, iclass 15, count 2 2006.257.02:39:39.58#ibcon#*before return 0, iclass 15, count 2 2006.257.02:39:39.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:39:39.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:39:39.58#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.02:39:39.58#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:39.58#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:39:39.70#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:39:39.70#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:39:39.70#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:39:39.70#ibcon#first serial, iclass 15, count 0 2006.257.02:39:39.70#ibcon#enter sib2, iclass 15, count 0 2006.257.02:39:39.70#ibcon#flushed, iclass 15, count 0 2006.257.02:39:39.70#ibcon#about to write, iclass 15, count 0 2006.257.02:39:39.70#ibcon#wrote, iclass 15, count 0 2006.257.02:39:39.70#ibcon#about to read 3, iclass 15, count 0 2006.257.02:39:39.72#ibcon#read 3, iclass 15, count 0 2006.257.02:39:39.72#ibcon#about to read 4, iclass 15, count 0 2006.257.02:39:39.72#ibcon#read 4, iclass 15, count 0 2006.257.02:39:39.72#ibcon#about to read 5, iclass 15, count 0 2006.257.02:39:39.72#ibcon#read 5, iclass 15, count 0 2006.257.02:39:39.72#ibcon#about to read 6, iclass 15, count 0 2006.257.02:39:39.72#ibcon#read 6, iclass 15, count 0 2006.257.02:39:39.72#ibcon#end of sib2, iclass 15, count 0 2006.257.02:39:39.72#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:39:39.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:39:39.72#ibcon#[27=USB\r\n] 2006.257.02:39:39.72#ibcon#*before write, iclass 15, count 0 2006.257.02:39:39.72#ibcon#enter sib2, iclass 15, count 0 2006.257.02:39:39.72#ibcon#flushed, iclass 15, count 0 2006.257.02:39:39.72#ibcon#about to write, iclass 15, count 0 2006.257.02:39:39.72#ibcon#wrote, iclass 15, count 0 2006.257.02:39:39.72#ibcon#about to read 3, iclass 15, count 0 2006.257.02:39:39.75#ibcon#read 3, iclass 15, count 0 2006.257.02:39:39.75#ibcon#about to read 4, iclass 15, count 0 2006.257.02:39:39.75#ibcon#read 4, iclass 15, count 0 2006.257.02:39:39.75#ibcon#about to read 5, iclass 15, count 0 2006.257.02:39:39.75#ibcon#read 5, iclass 15, count 0 2006.257.02:39:39.75#ibcon#about to read 6, iclass 15, count 0 2006.257.02:39:39.75#ibcon#read 6, iclass 15, count 0 2006.257.02:39:39.75#ibcon#end of sib2, iclass 15, count 0 2006.257.02:39:39.75#ibcon#*after write, iclass 15, count 0 2006.257.02:39:39.75#ibcon#*before return 0, iclass 15, count 0 2006.257.02:39:39.75#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:39:39.75#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:39:39.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:39:39.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:39:39.75$vck44/vblo=2,634.99 2006.257.02:39:39.75#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.02:39:39.75#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.02:39:39.75#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:39.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:39.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:39.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:39.75#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:39:39.75#ibcon#first serial, iclass 17, count 0 2006.257.02:39:39.75#ibcon#enter sib2, iclass 17, count 0 2006.257.02:39:39.75#ibcon#flushed, iclass 17, count 0 2006.257.02:39:39.75#ibcon#about to write, iclass 17, count 0 2006.257.02:39:39.75#ibcon#wrote, iclass 17, count 0 2006.257.02:39:39.75#ibcon#about to read 3, iclass 17, count 0 2006.257.02:39:39.77#ibcon#read 3, iclass 17, count 0 2006.257.02:39:39.77#ibcon#about to read 4, iclass 17, count 0 2006.257.02:39:39.77#ibcon#read 4, iclass 17, count 0 2006.257.02:39:39.77#ibcon#about to read 5, iclass 17, count 0 2006.257.02:39:39.77#ibcon#read 5, iclass 17, count 0 2006.257.02:39:39.77#ibcon#about to read 6, iclass 17, count 0 2006.257.02:39:39.77#ibcon#read 6, iclass 17, count 0 2006.257.02:39:39.77#ibcon#end of sib2, iclass 17, count 0 2006.257.02:39:39.77#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:39:39.77#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:39:39.77#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:39:39.77#ibcon#*before write, iclass 17, count 0 2006.257.02:39:39.77#ibcon#enter sib2, iclass 17, count 0 2006.257.02:39:39.77#ibcon#flushed, iclass 17, count 0 2006.257.02:39:39.77#ibcon#about to write, iclass 17, count 0 2006.257.02:39:39.77#ibcon#wrote, iclass 17, count 0 2006.257.02:39:39.77#ibcon#about to read 3, iclass 17, count 0 2006.257.02:39:39.81#ibcon#read 3, iclass 17, count 0 2006.257.02:39:39.81#ibcon#about to read 4, iclass 17, count 0 2006.257.02:39:39.81#ibcon#read 4, iclass 17, count 0 2006.257.02:39:39.81#ibcon#about to read 5, iclass 17, count 0 2006.257.02:39:39.81#ibcon#read 5, iclass 17, count 0 2006.257.02:39:39.81#ibcon#about to read 6, iclass 17, count 0 2006.257.02:39:39.81#ibcon#read 6, iclass 17, count 0 2006.257.02:39:39.81#ibcon#end of sib2, iclass 17, count 0 2006.257.02:39:39.81#ibcon#*after write, iclass 17, count 0 2006.257.02:39:39.81#ibcon#*before return 0, iclass 17, count 0 2006.257.02:39:39.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:39.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:39:39.81#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:39:39.81#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:39:39.81$vck44/vb=2,5 2006.257.02:39:39.81#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.02:39:39.81#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.02:39:39.81#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:39.81#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:39.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:39.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:39.87#ibcon#enter wrdev, iclass 19, count 2 2006.257.02:39:39.87#ibcon#first serial, iclass 19, count 2 2006.257.02:39:39.87#ibcon#enter sib2, iclass 19, count 2 2006.257.02:39:39.87#ibcon#flushed, iclass 19, count 2 2006.257.02:39:39.87#ibcon#about to write, iclass 19, count 2 2006.257.02:39:39.87#ibcon#wrote, iclass 19, count 2 2006.257.02:39:39.87#ibcon#about to read 3, iclass 19, count 2 2006.257.02:39:39.89#ibcon#read 3, iclass 19, count 2 2006.257.02:39:39.89#ibcon#about to read 4, iclass 19, count 2 2006.257.02:39:39.89#ibcon#read 4, iclass 19, count 2 2006.257.02:39:39.89#ibcon#about to read 5, iclass 19, count 2 2006.257.02:39:39.89#ibcon#read 5, iclass 19, count 2 2006.257.02:39:39.89#ibcon#about to read 6, iclass 19, count 2 2006.257.02:39:39.89#ibcon#read 6, iclass 19, count 2 2006.257.02:39:39.89#ibcon#end of sib2, iclass 19, count 2 2006.257.02:39:39.89#ibcon#*mode == 0, iclass 19, count 2 2006.257.02:39:39.89#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.02:39:39.89#ibcon#[27=AT02-05\r\n] 2006.257.02:39:39.89#ibcon#*before write, iclass 19, count 2 2006.257.02:39:39.89#ibcon#enter sib2, iclass 19, count 2 2006.257.02:39:39.89#ibcon#flushed, iclass 19, count 2 2006.257.02:39:39.89#ibcon#about to write, iclass 19, count 2 2006.257.02:39:39.89#ibcon#wrote, iclass 19, count 2 2006.257.02:39:39.89#ibcon#about to read 3, iclass 19, count 2 2006.257.02:39:39.92#ibcon#read 3, iclass 19, count 2 2006.257.02:39:39.92#ibcon#about to read 4, iclass 19, count 2 2006.257.02:39:39.92#ibcon#read 4, iclass 19, count 2 2006.257.02:39:39.92#ibcon#about to read 5, iclass 19, count 2 2006.257.02:39:39.92#ibcon#read 5, iclass 19, count 2 2006.257.02:39:39.92#ibcon#about to read 6, iclass 19, count 2 2006.257.02:39:39.92#ibcon#read 6, iclass 19, count 2 2006.257.02:39:39.92#ibcon#end of sib2, iclass 19, count 2 2006.257.02:39:39.92#ibcon#*after write, iclass 19, count 2 2006.257.02:39:39.92#ibcon#*before return 0, iclass 19, count 2 2006.257.02:39:39.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:39.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:39:39.92#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.02:39:39.92#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:39.92#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:40.04#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:40.04#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:40.04#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:39:40.04#ibcon#first serial, iclass 19, count 0 2006.257.02:39:40.04#ibcon#enter sib2, iclass 19, count 0 2006.257.02:39:40.04#ibcon#flushed, iclass 19, count 0 2006.257.02:39:40.04#ibcon#about to write, iclass 19, count 0 2006.257.02:39:40.04#ibcon#wrote, iclass 19, count 0 2006.257.02:39:40.04#ibcon#about to read 3, iclass 19, count 0 2006.257.02:39:40.06#ibcon#read 3, iclass 19, count 0 2006.257.02:39:40.06#ibcon#about to read 4, iclass 19, count 0 2006.257.02:39:40.06#ibcon#read 4, iclass 19, count 0 2006.257.02:39:40.06#ibcon#about to read 5, iclass 19, count 0 2006.257.02:39:40.06#ibcon#read 5, iclass 19, count 0 2006.257.02:39:40.06#ibcon#about to read 6, iclass 19, count 0 2006.257.02:39:40.06#ibcon#read 6, iclass 19, count 0 2006.257.02:39:40.06#ibcon#end of sib2, iclass 19, count 0 2006.257.02:39:40.06#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:39:40.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:39:40.06#ibcon#[27=USB\r\n] 2006.257.02:39:40.06#ibcon#*before write, iclass 19, count 0 2006.257.02:39:40.06#ibcon#enter sib2, iclass 19, count 0 2006.257.02:39:40.06#ibcon#flushed, iclass 19, count 0 2006.257.02:39:40.06#ibcon#about to write, iclass 19, count 0 2006.257.02:39:40.06#ibcon#wrote, iclass 19, count 0 2006.257.02:39:40.06#ibcon#about to read 3, iclass 19, count 0 2006.257.02:39:40.09#ibcon#read 3, iclass 19, count 0 2006.257.02:39:40.09#ibcon#about to read 4, iclass 19, count 0 2006.257.02:39:40.09#ibcon#read 4, iclass 19, count 0 2006.257.02:39:40.09#ibcon#about to read 5, iclass 19, count 0 2006.257.02:39:40.09#ibcon#read 5, iclass 19, count 0 2006.257.02:39:40.09#ibcon#about to read 6, iclass 19, count 0 2006.257.02:39:40.09#ibcon#read 6, iclass 19, count 0 2006.257.02:39:40.09#ibcon#end of sib2, iclass 19, count 0 2006.257.02:39:40.09#ibcon#*after write, iclass 19, count 0 2006.257.02:39:40.09#ibcon#*before return 0, iclass 19, count 0 2006.257.02:39:40.09#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:40.09#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:39:40.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:39:40.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:39:40.09$vck44/vblo=3,649.99 2006.257.02:39:40.09#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.02:39:40.09#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.02:39:40.09#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:40.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:40.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:40.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:40.09#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:39:40.09#ibcon#first serial, iclass 21, count 0 2006.257.02:39:40.09#ibcon#enter sib2, iclass 21, count 0 2006.257.02:39:40.09#ibcon#flushed, iclass 21, count 0 2006.257.02:39:40.09#ibcon#about to write, iclass 21, count 0 2006.257.02:39:40.09#ibcon#wrote, iclass 21, count 0 2006.257.02:39:40.09#ibcon#about to read 3, iclass 21, count 0 2006.257.02:39:40.11#ibcon#read 3, iclass 21, count 0 2006.257.02:39:40.11#ibcon#about to read 4, iclass 21, count 0 2006.257.02:39:40.11#ibcon#read 4, iclass 21, count 0 2006.257.02:39:40.11#ibcon#about to read 5, iclass 21, count 0 2006.257.02:39:40.11#ibcon#read 5, iclass 21, count 0 2006.257.02:39:40.11#ibcon#about to read 6, iclass 21, count 0 2006.257.02:39:40.11#ibcon#read 6, iclass 21, count 0 2006.257.02:39:40.11#ibcon#end of sib2, iclass 21, count 0 2006.257.02:39:40.11#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:39:40.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:39:40.11#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:39:40.11#ibcon#*before write, iclass 21, count 0 2006.257.02:39:40.11#ibcon#enter sib2, iclass 21, count 0 2006.257.02:39:40.11#ibcon#flushed, iclass 21, count 0 2006.257.02:39:40.11#ibcon#about to write, iclass 21, count 0 2006.257.02:39:40.11#ibcon#wrote, iclass 21, count 0 2006.257.02:39:40.11#ibcon#about to read 3, iclass 21, count 0 2006.257.02:39:40.15#ibcon#read 3, iclass 21, count 0 2006.257.02:39:40.15#ibcon#about to read 4, iclass 21, count 0 2006.257.02:39:40.15#ibcon#read 4, iclass 21, count 0 2006.257.02:39:40.15#ibcon#about to read 5, iclass 21, count 0 2006.257.02:39:40.15#ibcon#read 5, iclass 21, count 0 2006.257.02:39:40.15#ibcon#about to read 6, iclass 21, count 0 2006.257.02:39:40.15#ibcon#read 6, iclass 21, count 0 2006.257.02:39:40.15#ibcon#end of sib2, iclass 21, count 0 2006.257.02:39:40.15#ibcon#*after write, iclass 21, count 0 2006.257.02:39:40.15#ibcon#*before return 0, iclass 21, count 0 2006.257.02:39:40.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:40.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:39:40.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:39:40.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:39:40.15$vck44/vb=3,4 2006.257.02:39:40.15#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.02:39:40.15#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.02:39:40.15#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:40.15#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:40.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:40.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:40.21#ibcon#enter wrdev, iclass 23, count 2 2006.257.02:39:40.21#ibcon#first serial, iclass 23, count 2 2006.257.02:39:40.21#ibcon#enter sib2, iclass 23, count 2 2006.257.02:39:40.21#ibcon#flushed, iclass 23, count 2 2006.257.02:39:40.21#ibcon#about to write, iclass 23, count 2 2006.257.02:39:40.21#ibcon#wrote, iclass 23, count 2 2006.257.02:39:40.21#ibcon#about to read 3, iclass 23, count 2 2006.257.02:39:40.23#ibcon#read 3, iclass 23, count 2 2006.257.02:39:40.23#ibcon#about to read 4, iclass 23, count 2 2006.257.02:39:40.23#ibcon#read 4, iclass 23, count 2 2006.257.02:39:40.23#ibcon#about to read 5, iclass 23, count 2 2006.257.02:39:40.23#ibcon#read 5, iclass 23, count 2 2006.257.02:39:40.23#ibcon#about to read 6, iclass 23, count 2 2006.257.02:39:40.23#ibcon#read 6, iclass 23, count 2 2006.257.02:39:40.23#ibcon#end of sib2, iclass 23, count 2 2006.257.02:39:40.23#ibcon#*mode == 0, iclass 23, count 2 2006.257.02:39:40.23#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.02:39:40.23#ibcon#[27=AT03-04\r\n] 2006.257.02:39:40.23#ibcon#*before write, iclass 23, count 2 2006.257.02:39:40.23#ibcon#enter sib2, iclass 23, count 2 2006.257.02:39:40.23#ibcon#flushed, iclass 23, count 2 2006.257.02:39:40.23#ibcon#about to write, iclass 23, count 2 2006.257.02:39:40.23#ibcon#wrote, iclass 23, count 2 2006.257.02:39:40.23#ibcon#about to read 3, iclass 23, count 2 2006.257.02:39:40.26#ibcon#read 3, iclass 23, count 2 2006.257.02:39:40.26#ibcon#about to read 4, iclass 23, count 2 2006.257.02:39:40.26#ibcon#read 4, iclass 23, count 2 2006.257.02:39:40.26#ibcon#about to read 5, iclass 23, count 2 2006.257.02:39:40.26#ibcon#read 5, iclass 23, count 2 2006.257.02:39:40.26#ibcon#about to read 6, iclass 23, count 2 2006.257.02:39:40.26#ibcon#read 6, iclass 23, count 2 2006.257.02:39:40.26#ibcon#end of sib2, iclass 23, count 2 2006.257.02:39:40.26#ibcon#*after write, iclass 23, count 2 2006.257.02:39:40.26#ibcon#*before return 0, iclass 23, count 2 2006.257.02:39:40.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:40.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:39:40.26#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.02:39:40.26#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:40.26#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:40.38#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:40.38#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:40.38#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:39:40.38#ibcon#first serial, iclass 23, count 0 2006.257.02:39:40.38#ibcon#enter sib2, iclass 23, count 0 2006.257.02:39:40.38#ibcon#flushed, iclass 23, count 0 2006.257.02:39:40.38#ibcon#about to write, iclass 23, count 0 2006.257.02:39:40.38#ibcon#wrote, iclass 23, count 0 2006.257.02:39:40.38#ibcon#about to read 3, iclass 23, count 0 2006.257.02:39:40.40#ibcon#read 3, iclass 23, count 0 2006.257.02:39:40.40#ibcon#about to read 4, iclass 23, count 0 2006.257.02:39:40.40#ibcon#read 4, iclass 23, count 0 2006.257.02:39:40.40#ibcon#about to read 5, iclass 23, count 0 2006.257.02:39:40.40#ibcon#read 5, iclass 23, count 0 2006.257.02:39:40.40#ibcon#about to read 6, iclass 23, count 0 2006.257.02:39:40.40#ibcon#read 6, iclass 23, count 0 2006.257.02:39:40.40#ibcon#end of sib2, iclass 23, count 0 2006.257.02:39:40.40#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:39:40.40#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:39:40.40#ibcon#[27=USB\r\n] 2006.257.02:39:40.40#ibcon#*before write, iclass 23, count 0 2006.257.02:39:40.40#ibcon#enter sib2, iclass 23, count 0 2006.257.02:39:40.40#ibcon#flushed, iclass 23, count 0 2006.257.02:39:40.40#ibcon#about to write, iclass 23, count 0 2006.257.02:39:40.40#ibcon#wrote, iclass 23, count 0 2006.257.02:39:40.40#ibcon#about to read 3, iclass 23, count 0 2006.257.02:39:40.43#ibcon#read 3, iclass 23, count 0 2006.257.02:39:40.43#ibcon#about to read 4, iclass 23, count 0 2006.257.02:39:40.43#ibcon#read 4, iclass 23, count 0 2006.257.02:39:40.43#ibcon#about to read 5, iclass 23, count 0 2006.257.02:39:40.43#ibcon#read 5, iclass 23, count 0 2006.257.02:39:40.43#ibcon#about to read 6, iclass 23, count 0 2006.257.02:39:40.43#ibcon#read 6, iclass 23, count 0 2006.257.02:39:40.43#ibcon#end of sib2, iclass 23, count 0 2006.257.02:39:40.43#ibcon#*after write, iclass 23, count 0 2006.257.02:39:40.43#ibcon#*before return 0, iclass 23, count 0 2006.257.02:39:40.43#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:40.43#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:39:40.43#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:39:40.43#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:39:40.43$vck44/vblo=4,679.99 2006.257.02:39:40.43#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.02:39:40.43#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.02:39:40.43#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:40.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:40.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:40.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:40.43#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:39:40.43#ibcon#first serial, iclass 25, count 0 2006.257.02:39:40.43#ibcon#enter sib2, iclass 25, count 0 2006.257.02:39:40.43#ibcon#flushed, iclass 25, count 0 2006.257.02:39:40.43#ibcon#about to write, iclass 25, count 0 2006.257.02:39:40.43#ibcon#wrote, iclass 25, count 0 2006.257.02:39:40.43#ibcon#about to read 3, iclass 25, count 0 2006.257.02:39:40.45#ibcon#read 3, iclass 25, count 0 2006.257.02:39:40.45#ibcon#about to read 4, iclass 25, count 0 2006.257.02:39:40.45#ibcon#read 4, iclass 25, count 0 2006.257.02:39:40.45#ibcon#about to read 5, iclass 25, count 0 2006.257.02:39:40.45#ibcon#read 5, iclass 25, count 0 2006.257.02:39:40.45#ibcon#about to read 6, iclass 25, count 0 2006.257.02:39:40.45#ibcon#read 6, iclass 25, count 0 2006.257.02:39:40.45#ibcon#end of sib2, iclass 25, count 0 2006.257.02:39:40.45#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:39:40.45#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:39:40.45#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:39:40.45#ibcon#*before write, iclass 25, count 0 2006.257.02:39:40.45#ibcon#enter sib2, iclass 25, count 0 2006.257.02:39:40.45#ibcon#flushed, iclass 25, count 0 2006.257.02:39:40.45#ibcon#about to write, iclass 25, count 0 2006.257.02:39:40.45#ibcon#wrote, iclass 25, count 0 2006.257.02:39:40.45#ibcon#about to read 3, iclass 25, count 0 2006.257.02:39:40.49#ibcon#read 3, iclass 25, count 0 2006.257.02:39:40.49#ibcon#about to read 4, iclass 25, count 0 2006.257.02:39:40.49#ibcon#read 4, iclass 25, count 0 2006.257.02:39:40.49#ibcon#about to read 5, iclass 25, count 0 2006.257.02:39:40.49#ibcon#read 5, iclass 25, count 0 2006.257.02:39:40.49#ibcon#about to read 6, iclass 25, count 0 2006.257.02:39:40.49#ibcon#read 6, iclass 25, count 0 2006.257.02:39:40.49#ibcon#end of sib2, iclass 25, count 0 2006.257.02:39:40.49#ibcon#*after write, iclass 25, count 0 2006.257.02:39:40.49#ibcon#*before return 0, iclass 25, count 0 2006.257.02:39:40.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:40.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:39:40.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:39:40.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:39:40.49$vck44/vb=4,5 2006.257.02:39:40.49#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.02:39:40.49#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.02:39:40.49#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:40.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:40.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:40.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:40.55#ibcon#enter wrdev, iclass 27, count 2 2006.257.02:39:40.55#ibcon#first serial, iclass 27, count 2 2006.257.02:39:40.55#ibcon#enter sib2, iclass 27, count 2 2006.257.02:39:40.55#ibcon#flushed, iclass 27, count 2 2006.257.02:39:40.55#ibcon#about to write, iclass 27, count 2 2006.257.02:39:40.55#ibcon#wrote, iclass 27, count 2 2006.257.02:39:40.55#ibcon#about to read 3, iclass 27, count 2 2006.257.02:39:40.57#ibcon#read 3, iclass 27, count 2 2006.257.02:39:40.57#ibcon#about to read 4, iclass 27, count 2 2006.257.02:39:40.57#ibcon#read 4, iclass 27, count 2 2006.257.02:39:40.57#ibcon#about to read 5, iclass 27, count 2 2006.257.02:39:40.57#ibcon#read 5, iclass 27, count 2 2006.257.02:39:40.57#ibcon#about to read 6, iclass 27, count 2 2006.257.02:39:40.57#ibcon#read 6, iclass 27, count 2 2006.257.02:39:40.57#ibcon#end of sib2, iclass 27, count 2 2006.257.02:39:40.57#ibcon#*mode == 0, iclass 27, count 2 2006.257.02:39:40.57#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.02:39:40.57#ibcon#[27=AT04-05\r\n] 2006.257.02:39:40.57#ibcon#*before write, iclass 27, count 2 2006.257.02:39:40.57#ibcon#enter sib2, iclass 27, count 2 2006.257.02:39:40.57#ibcon#flushed, iclass 27, count 2 2006.257.02:39:40.57#ibcon#about to write, iclass 27, count 2 2006.257.02:39:40.57#ibcon#wrote, iclass 27, count 2 2006.257.02:39:40.57#ibcon#about to read 3, iclass 27, count 2 2006.257.02:39:40.60#ibcon#read 3, iclass 27, count 2 2006.257.02:39:40.60#ibcon#about to read 4, iclass 27, count 2 2006.257.02:39:40.60#ibcon#read 4, iclass 27, count 2 2006.257.02:39:40.60#ibcon#about to read 5, iclass 27, count 2 2006.257.02:39:40.60#ibcon#read 5, iclass 27, count 2 2006.257.02:39:40.60#ibcon#about to read 6, iclass 27, count 2 2006.257.02:39:40.60#ibcon#read 6, iclass 27, count 2 2006.257.02:39:40.60#ibcon#end of sib2, iclass 27, count 2 2006.257.02:39:40.60#ibcon#*after write, iclass 27, count 2 2006.257.02:39:40.60#ibcon#*before return 0, iclass 27, count 2 2006.257.02:39:40.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:40.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:39:40.60#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.02:39:40.60#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:40.60#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:40.72#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:40.72#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:40.72#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:39:40.72#ibcon#first serial, iclass 27, count 0 2006.257.02:39:40.72#ibcon#enter sib2, iclass 27, count 0 2006.257.02:39:40.72#ibcon#flushed, iclass 27, count 0 2006.257.02:39:40.72#ibcon#about to write, iclass 27, count 0 2006.257.02:39:40.72#ibcon#wrote, iclass 27, count 0 2006.257.02:39:40.72#ibcon#about to read 3, iclass 27, count 0 2006.257.02:39:40.74#ibcon#read 3, iclass 27, count 0 2006.257.02:39:40.74#ibcon#about to read 4, iclass 27, count 0 2006.257.02:39:40.74#ibcon#read 4, iclass 27, count 0 2006.257.02:39:40.74#ibcon#about to read 5, iclass 27, count 0 2006.257.02:39:40.74#ibcon#read 5, iclass 27, count 0 2006.257.02:39:40.74#ibcon#about to read 6, iclass 27, count 0 2006.257.02:39:40.74#ibcon#read 6, iclass 27, count 0 2006.257.02:39:40.74#ibcon#end of sib2, iclass 27, count 0 2006.257.02:39:40.74#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:39:40.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:39:40.74#ibcon#[27=USB\r\n] 2006.257.02:39:40.74#ibcon#*before write, iclass 27, count 0 2006.257.02:39:40.74#ibcon#enter sib2, iclass 27, count 0 2006.257.02:39:40.74#ibcon#flushed, iclass 27, count 0 2006.257.02:39:40.74#ibcon#about to write, iclass 27, count 0 2006.257.02:39:40.74#ibcon#wrote, iclass 27, count 0 2006.257.02:39:40.74#ibcon#about to read 3, iclass 27, count 0 2006.257.02:39:40.77#ibcon#read 3, iclass 27, count 0 2006.257.02:39:40.77#ibcon#about to read 4, iclass 27, count 0 2006.257.02:39:40.77#ibcon#read 4, iclass 27, count 0 2006.257.02:39:40.77#ibcon#about to read 5, iclass 27, count 0 2006.257.02:39:40.77#ibcon#read 5, iclass 27, count 0 2006.257.02:39:40.77#ibcon#about to read 6, iclass 27, count 0 2006.257.02:39:40.77#ibcon#read 6, iclass 27, count 0 2006.257.02:39:40.77#ibcon#end of sib2, iclass 27, count 0 2006.257.02:39:40.77#ibcon#*after write, iclass 27, count 0 2006.257.02:39:40.77#ibcon#*before return 0, iclass 27, count 0 2006.257.02:39:40.77#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:40.77#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:39:40.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:39:40.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:39:40.77$vck44/vblo=5,709.99 2006.257.02:39:40.77#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.02:39:40.77#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.02:39:40.77#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:40.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:40.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:40.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:40.77#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:39:40.77#ibcon#first serial, iclass 29, count 0 2006.257.02:39:40.77#ibcon#enter sib2, iclass 29, count 0 2006.257.02:39:40.77#ibcon#flushed, iclass 29, count 0 2006.257.02:39:40.77#ibcon#about to write, iclass 29, count 0 2006.257.02:39:40.77#ibcon#wrote, iclass 29, count 0 2006.257.02:39:40.77#ibcon#about to read 3, iclass 29, count 0 2006.257.02:39:40.79#ibcon#read 3, iclass 29, count 0 2006.257.02:39:40.79#ibcon#about to read 4, iclass 29, count 0 2006.257.02:39:40.79#ibcon#read 4, iclass 29, count 0 2006.257.02:39:40.79#ibcon#about to read 5, iclass 29, count 0 2006.257.02:39:40.79#ibcon#read 5, iclass 29, count 0 2006.257.02:39:40.79#ibcon#about to read 6, iclass 29, count 0 2006.257.02:39:40.79#ibcon#read 6, iclass 29, count 0 2006.257.02:39:40.79#ibcon#end of sib2, iclass 29, count 0 2006.257.02:39:40.79#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:39:40.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:39:40.79#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:39:40.79#ibcon#*before write, iclass 29, count 0 2006.257.02:39:40.79#ibcon#enter sib2, iclass 29, count 0 2006.257.02:39:40.79#ibcon#flushed, iclass 29, count 0 2006.257.02:39:40.79#ibcon#about to write, iclass 29, count 0 2006.257.02:39:40.79#ibcon#wrote, iclass 29, count 0 2006.257.02:39:40.79#ibcon#about to read 3, iclass 29, count 0 2006.257.02:39:40.83#ibcon#read 3, iclass 29, count 0 2006.257.02:39:40.83#ibcon#about to read 4, iclass 29, count 0 2006.257.02:39:40.83#ibcon#read 4, iclass 29, count 0 2006.257.02:39:40.83#ibcon#about to read 5, iclass 29, count 0 2006.257.02:39:40.83#ibcon#read 5, iclass 29, count 0 2006.257.02:39:40.83#ibcon#about to read 6, iclass 29, count 0 2006.257.02:39:40.83#ibcon#read 6, iclass 29, count 0 2006.257.02:39:40.83#ibcon#end of sib2, iclass 29, count 0 2006.257.02:39:40.83#ibcon#*after write, iclass 29, count 0 2006.257.02:39:40.83#ibcon#*before return 0, iclass 29, count 0 2006.257.02:39:40.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:40.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:39:40.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:39:40.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:39:40.83$vck44/vb=5,4 2006.257.02:39:40.83#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.02:39:40.83#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.02:39:40.83#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:40.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:40.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:40.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:40.89#ibcon#enter wrdev, iclass 31, count 2 2006.257.02:39:40.89#ibcon#first serial, iclass 31, count 2 2006.257.02:39:40.89#ibcon#enter sib2, iclass 31, count 2 2006.257.02:39:40.89#ibcon#flushed, iclass 31, count 2 2006.257.02:39:40.89#ibcon#about to write, iclass 31, count 2 2006.257.02:39:40.89#ibcon#wrote, iclass 31, count 2 2006.257.02:39:40.89#ibcon#about to read 3, iclass 31, count 2 2006.257.02:39:40.91#ibcon#read 3, iclass 31, count 2 2006.257.02:39:40.91#ibcon#about to read 4, iclass 31, count 2 2006.257.02:39:40.91#ibcon#read 4, iclass 31, count 2 2006.257.02:39:40.91#ibcon#about to read 5, iclass 31, count 2 2006.257.02:39:40.91#ibcon#read 5, iclass 31, count 2 2006.257.02:39:40.91#ibcon#about to read 6, iclass 31, count 2 2006.257.02:39:40.91#ibcon#read 6, iclass 31, count 2 2006.257.02:39:40.91#ibcon#end of sib2, iclass 31, count 2 2006.257.02:39:40.91#ibcon#*mode == 0, iclass 31, count 2 2006.257.02:39:40.91#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.02:39:40.91#ibcon#[27=AT05-04\r\n] 2006.257.02:39:40.91#ibcon#*before write, iclass 31, count 2 2006.257.02:39:40.91#ibcon#enter sib2, iclass 31, count 2 2006.257.02:39:40.91#ibcon#flushed, iclass 31, count 2 2006.257.02:39:40.91#ibcon#about to write, iclass 31, count 2 2006.257.02:39:40.91#ibcon#wrote, iclass 31, count 2 2006.257.02:39:40.91#ibcon#about to read 3, iclass 31, count 2 2006.257.02:39:40.94#ibcon#read 3, iclass 31, count 2 2006.257.02:39:40.94#ibcon#about to read 4, iclass 31, count 2 2006.257.02:39:40.94#ibcon#read 4, iclass 31, count 2 2006.257.02:39:40.94#ibcon#about to read 5, iclass 31, count 2 2006.257.02:39:40.94#ibcon#read 5, iclass 31, count 2 2006.257.02:39:40.94#ibcon#about to read 6, iclass 31, count 2 2006.257.02:39:40.94#ibcon#read 6, iclass 31, count 2 2006.257.02:39:40.94#ibcon#end of sib2, iclass 31, count 2 2006.257.02:39:40.94#ibcon#*after write, iclass 31, count 2 2006.257.02:39:40.94#ibcon#*before return 0, iclass 31, count 2 2006.257.02:39:40.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:40.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:39:40.94#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.02:39:40.94#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:40.94#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:41.06#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:41.06#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:41.06#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:39:41.06#ibcon#first serial, iclass 31, count 0 2006.257.02:39:41.06#ibcon#enter sib2, iclass 31, count 0 2006.257.02:39:41.06#ibcon#flushed, iclass 31, count 0 2006.257.02:39:41.06#ibcon#about to write, iclass 31, count 0 2006.257.02:39:41.06#ibcon#wrote, iclass 31, count 0 2006.257.02:39:41.06#ibcon#about to read 3, iclass 31, count 0 2006.257.02:39:41.08#ibcon#read 3, iclass 31, count 0 2006.257.02:39:41.08#ibcon#about to read 4, iclass 31, count 0 2006.257.02:39:41.08#ibcon#read 4, iclass 31, count 0 2006.257.02:39:41.08#ibcon#about to read 5, iclass 31, count 0 2006.257.02:39:41.08#ibcon#read 5, iclass 31, count 0 2006.257.02:39:41.08#ibcon#about to read 6, iclass 31, count 0 2006.257.02:39:41.08#ibcon#read 6, iclass 31, count 0 2006.257.02:39:41.08#ibcon#end of sib2, iclass 31, count 0 2006.257.02:39:41.08#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:39:41.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:39:41.08#ibcon#[27=USB\r\n] 2006.257.02:39:41.08#ibcon#*before write, iclass 31, count 0 2006.257.02:39:41.08#ibcon#enter sib2, iclass 31, count 0 2006.257.02:39:41.08#ibcon#flushed, iclass 31, count 0 2006.257.02:39:41.08#ibcon#about to write, iclass 31, count 0 2006.257.02:39:41.08#ibcon#wrote, iclass 31, count 0 2006.257.02:39:41.08#ibcon#about to read 3, iclass 31, count 0 2006.257.02:39:41.11#ibcon#read 3, iclass 31, count 0 2006.257.02:39:41.11#ibcon#about to read 4, iclass 31, count 0 2006.257.02:39:41.11#ibcon#read 4, iclass 31, count 0 2006.257.02:39:41.11#ibcon#about to read 5, iclass 31, count 0 2006.257.02:39:41.11#ibcon#read 5, iclass 31, count 0 2006.257.02:39:41.11#ibcon#about to read 6, iclass 31, count 0 2006.257.02:39:41.11#ibcon#read 6, iclass 31, count 0 2006.257.02:39:41.11#ibcon#end of sib2, iclass 31, count 0 2006.257.02:39:41.11#ibcon#*after write, iclass 31, count 0 2006.257.02:39:41.11#ibcon#*before return 0, iclass 31, count 0 2006.257.02:39:41.11#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:41.11#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:39:41.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:39:41.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:39:41.11$vck44/vblo=6,719.99 2006.257.02:39:41.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.02:39:41.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.02:39:41.11#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:41.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:41.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:41.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:41.11#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:39:41.11#ibcon#first serial, iclass 33, count 0 2006.257.02:39:41.11#ibcon#enter sib2, iclass 33, count 0 2006.257.02:39:41.11#ibcon#flushed, iclass 33, count 0 2006.257.02:39:41.11#ibcon#about to write, iclass 33, count 0 2006.257.02:39:41.11#ibcon#wrote, iclass 33, count 0 2006.257.02:39:41.11#ibcon#about to read 3, iclass 33, count 0 2006.257.02:39:41.13#ibcon#read 3, iclass 33, count 0 2006.257.02:39:41.13#ibcon#about to read 4, iclass 33, count 0 2006.257.02:39:41.13#ibcon#read 4, iclass 33, count 0 2006.257.02:39:41.13#ibcon#about to read 5, iclass 33, count 0 2006.257.02:39:41.13#ibcon#read 5, iclass 33, count 0 2006.257.02:39:41.13#ibcon#about to read 6, iclass 33, count 0 2006.257.02:39:41.13#ibcon#read 6, iclass 33, count 0 2006.257.02:39:41.13#ibcon#end of sib2, iclass 33, count 0 2006.257.02:39:41.13#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:39:41.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:39:41.13#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:39:41.13#ibcon#*before write, iclass 33, count 0 2006.257.02:39:41.13#ibcon#enter sib2, iclass 33, count 0 2006.257.02:39:41.13#ibcon#flushed, iclass 33, count 0 2006.257.02:39:41.13#ibcon#about to write, iclass 33, count 0 2006.257.02:39:41.13#ibcon#wrote, iclass 33, count 0 2006.257.02:39:41.13#ibcon#about to read 3, iclass 33, count 0 2006.257.02:39:41.17#ibcon#read 3, iclass 33, count 0 2006.257.02:39:41.17#ibcon#about to read 4, iclass 33, count 0 2006.257.02:39:41.17#ibcon#read 4, iclass 33, count 0 2006.257.02:39:41.17#ibcon#about to read 5, iclass 33, count 0 2006.257.02:39:41.17#ibcon#read 5, iclass 33, count 0 2006.257.02:39:41.17#ibcon#about to read 6, iclass 33, count 0 2006.257.02:39:41.17#ibcon#read 6, iclass 33, count 0 2006.257.02:39:41.17#ibcon#end of sib2, iclass 33, count 0 2006.257.02:39:41.17#ibcon#*after write, iclass 33, count 0 2006.257.02:39:41.17#ibcon#*before return 0, iclass 33, count 0 2006.257.02:39:41.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:41.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:39:41.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:39:41.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:39:41.17$vck44/vb=6,4 2006.257.02:39:41.17#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.02:39:41.17#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.02:39:41.17#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:41.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:41.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:41.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:41.23#ibcon#enter wrdev, iclass 35, count 2 2006.257.02:39:41.23#ibcon#first serial, iclass 35, count 2 2006.257.02:39:41.23#ibcon#enter sib2, iclass 35, count 2 2006.257.02:39:41.23#ibcon#flushed, iclass 35, count 2 2006.257.02:39:41.23#ibcon#about to write, iclass 35, count 2 2006.257.02:39:41.23#ibcon#wrote, iclass 35, count 2 2006.257.02:39:41.23#ibcon#about to read 3, iclass 35, count 2 2006.257.02:39:41.25#ibcon#read 3, iclass 35, count 2 2006.257.02:39:41.25#ibcon#about to read 4, iclass 35, count 2 2006.257.02:39:41.25#ibcon#read 4, iclass 35, count 2 2006.257.02:39:41.25#ibcon#about to read 5, iclass 35, count 2 2006.257.02:39:41.25#ibcon#read 5, iclass 35, count 2 2006.257.02:39:41.25#ibcon#about to read 6, iclass 35, count 2 2006.257.02:39:41.25#ibcon#read 6, iclass 35, count 2 2006.257.02:39:41.25#ibcon#end of sib2, iclass 35, count 2 2006.257.02:39:41.25#ibcon#*mode == 0, iclass 35, count 2 2006.257.02:39:41.25#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.02:39:41.25#ibcon#[27=AT06-04\r\n] 2006.257.02:39:41.25#ibcon#*before write, iclass 35, count 2 2006.257.02:39:41.25#ibcon#enter sib2, iclass 35, count 2 2006.257.02:39:41.25#ibcon#flushed, iclass 35, count 2 2006.257.02:39:41.25#ibcon#about to write, iclass 35, count 2 2006.257.02:39:41.25#ibcon#wrote, iclass 35, count 2 2006.257.02:39:41.25#ibcon#about to read 3, iclass 35, count 2 2006.257.02:39:41.28#ibcon#read 3, iclass 35, count 2 2006.257.02:39:41.28#ibcon#about to read 4, iclass 35, count 2 2006.257.02:39:41.28#ibcon#read 4, iclass 35, count 2 2006.257.02:39:41.28#ibcon#about to read 5, iclass 35, count 2 2006.257.02:39:41.28#ibcon#read 5, iclass 35, count 2 2006.257.02:39:41.28#ibcon#about to read 6, iclass 35, count 2 2006.257.02:39:41.28#ibcon#read 6, iclass 35, count 2 2006.257.02:39:41.28#ibcon#end of sib2, iclass 35, count 2 2006.257.02:39:41.28#ibcon#*after write, iclass 35, count 2 2006.257.02:39:41.28#ibcon#*before return 0, iclass 35, count 2 2006.257.02:39:41.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:41.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:39:41.28#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.02:39:41.28#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:41.28#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:41.41#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:41.41#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:41.41#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:39:41.41#ibcon#first serial, iclass 35, count 0 2006.257.02:39:41.41#ibcon#enter sib2, iclass 35, count 0 2006.257.02:39:41.41#ibcon#flushed, iclass 35, count 0 2006.257.02:39:41.41#ibcon#about to write, iclass 35, count 0 2006.257.02:39:41.41#ibcon#wrote, iclass 35, count 0 2006.257.02:39:41.41#ibcon#about to read 3, iclass 35, count 0 2006.257.02:39:41.42#ibcon#read 3, iclass 35, count 0 2006.257.02:39:41.42#ibcon#about to read 4, iclass 35, count 0 2006.257.02:39:41.42#ibcon#read 4, iclass 35, count 0 2006.257.02:39:41.42#ibcon#about to read 5, iclass 35, count 0 2006.257.02:39:41.42#ibcon#read 5, iclass 35, count 0 2006.257.02:39:41.42#ibcon#about to read 6, iclass 35, count 0 2006.257.02:39:41.42#ibcon#read 6, iclass 35, count 0 2006.257.02:39:41.42#ibcon#end of sib2, iclass 35, count 0 2006.257.02:39:41.42#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:39:41.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:39:41.42#ibcon#[27=USB\r\n] 2006.257.02:39:41.42#ibcon#*before write, iclass 35, count 0 2006.257.02:39:41.42#ibcon#enter sib2, iclass 35, count 0 2006.257.02:39:41.42#ibcon#flushed, iclass 35, count 0 2006.257.02:39:41.42#ibcon#about to write, iclass 35, count 0 2006.257.02:39:41.42#ibcon#wrote, iclass 35, count 0 2006.257.02:39:41.42#ibcon#about to read 3, iclass 35, count 0 2006.257.02:39:41.45#ibcon#read 3, iclass 35, count 0 2006.257.02:39:41.45#ibcon#about to read 4, iclass 35, count 0 2006.257.02:39:41.45#ibcon#read 4, iclass 35, count 0 2006.257.02:39:41.45#ibcon#about to read 5, iclass 35, count 0 2006.257.02:39:41.45#ibcon#read 5, iclass 35, count 0 2006.257.02:39:41.45#ibcon#about to read 6, iclass 35, count 0 2006.257.02:39:41.45#ibcon#read 6, iclass 35, count 0 2006.257.02:39:41.45#ibcon#end of sib2, iclass 35, count 0 2006.257.02:39:41.45#ibcon#*after write, iclass 35, count 0 2006.257.02:39:41.45#ibcon#*before return 0, iclass 35, count 0 2006.257.02:39:41.45#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:41.45#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:39:41.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:39:41.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:39:41.45$vck44/vblo=7,734.99 2006.257.02:39:41.45#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.02:39:41.45#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.02:39:41.45#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:41.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:41.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:41.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:41.45#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:39:41.45#ibcon#first serial, iclass 37, count 0 2006.257.02:39:41.45#ibcon#enter sib2, iclass 37, count 0 2006.257.02:39:41.45#ibcon#flushed, iclass 37, count 0 2006.257.02:39:41.45#ibcon#about to write, iclass 37, count 0 2006.257.02:39:41.45#ibcon#wrote, iclass 37, count 0 2006.257.02:39:41.45#ibcon#about to read 3, iclass 37, count 0 2006.257.02:39:41.47#ibcon#read 3, iclass 37, count 0 2006.257.02:39:41.47#ibcon#about to read 4, iclass 37, count 0 2006.257.02:39:41.47#ibcon#read 4, iclass 37, count 0 2006.257.02:39:41.47#ibcon#about to read 5, iclass 37, count 0 2006.257.02:39:41.47#ibcon#read 5, iclass 37, count 0 2006.257.02:39:41.47#ibcon#about to read 6, iclass 37, count 0 2006.257.02:39:41.47#ibcon#read 6, iclass 37, count 0 2006.257.02:39:41.47#ibcon#end of sib2, iclass 37, count 0 2006.257.02:39:41.47#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:39:41.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:39:41.47#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:39:41.47#ibcon#*before write, iclass 37, count 0 2006.257.02:39:41.47#ibcon#enter sib2, iclass 37, count 0 2006.257.02:39:41.47#ibcon#flushed, iclass 37, count 0 2006.257.02:39:41.47#ibcon#about to write, iclass 37, count 0 2006.257.02:39:41.47#ibcon#wrote, iclass 37, count 0 2006.257.02:39:41.47#ibcon#about to read 3, iclass 37, count 0 2006.257.02:39:41.51#ibcon#read 3, iclass 37, count 0 2006.257.02:39:41.51#ibcon#about to read 4, iclass 37, count 0 2006.257.02:39:41.51#ibcon#read 4, iclass 37, count 0 2006.257.02:39:41.51#ibcon#about to read 5, iclass 37, count 0 2006.257.02:39:41.51#ibcon#read 5, iclass 37, count 0 2006.257.02:39:41.51#ibcon#about to read 6, iclass 37, count 0 2006.257.02:39:41.51#ibcon#read 6, iclass 37, count 0 2006.257.02:39:41.51#ibcon#end of sib2, iclass 37, count 0 2006.257.02:39:41.51#ibcon#*after write, iclass 37, count 0 2006.257.02:39:41.51#ibcon#*before return 0, iclass 37, count 0 2006.257.02:39:41.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:41.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:39:41.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:39:41.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:39:41.51$vck44/vb=7,4 2006.257.02:39:41.51#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.02:39:41.51#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.02:39:41.51#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:41.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:41.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:41.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:41.57#ibcon#enter wrdev, iclass 39, count 2 2006.257.02:39:41.57#ibcon#first serial, iclass 39, count 2 2006.257.02:39:41.57#ibcon#enter sib2, iclass 39, count 2 2006.257.02:39:41.57#ibcon#flushed, iclass 39, count 2 2006.257.02:39:41.57#ibcon#about to write, iclass 39, count 2 2006.257.02:39:41.57#ibcon#wrote, iclass 39, count 2 2006.257.02:39:41.57#ibcon#about to read 3, iclass 39, count 2 2006.257.02:39:41.59#ibcon#read 3, iclass 39, count 2 2006.257.02:39:41.59#ibcon#about to read 4, iclass 39, count 2 2006.257.02:39:41.59#ibcon#read 4, iclass 39, count 2 2006.257.02:39:41.59#ibcon#about to read 5, iclass 39, count 2 2006.257.02:39:41.59#ibcon#read 5, iclass 39, count 2 2006.257.02:39:41.59#ibcon#about to read 6, iclass 39, count 2 2006.257.02:39:41.59#ibcon#read 6, iclass 39, count 2 2006.257.02:39:41.59#ibcon#end of sib2, iclass 39, count 2 2006.257.02:39:41.59#ibcon#*mode == 0, iclass 39, count 2 2006.257.02:39:41.59#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.02:39:41.59#ibcon#[27=AT07-04\r\n] 2006.257.02:39:41.59#ibcon#*before write, iclass 39, count 2 2006.257.02:39:41.59#ibcon#enter sib2, iclass 39, count 2 2006.257.02:39:41.59#ibcon#flushed, iclass 39, count 2 2006.257.02:39:41.59#ibcon#about to write, iclass 39, count 2 2006.257.02:39:41.59#ibcon#wrote, iclass 39, count 2 2006.257.02:39:41.59#ibcon#about to read 3, iclass 39, count 2 2006.257.02:39:41.62#ibcon#read 3, iclass 39, count 2 2006.257.02:39:41.62#ibcon#about to read 4, iclass 39, count 2 2006.257.02:39:41.62#ibcon#read 4, iclass 39, count 2 2006.257.02:39:41.62#ibcon#about to read 5, iclass 39, count 2 2006.257.02:39:41.62#ibcon#read 5, iclass 39, count 2 2006.257.02:39:41.62#ibcon#about to read 6, iclass 39, count 2 2006.257.02:39:41.62#ibcon#read 6, iclass 39, count 2 2006.257.02:39:41.62#ibcon#end of sib2, iclass 39, count 2 2006.257.02:39:41.62#ibcon#*after write, iclass 39, count 2 2006.257.02:39:41.62#ibcon#*before return 0, iclass 39, count 2 2006.257.02:39:41.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:41.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:39:41.62#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.02:39:41.62#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:41.62#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:41.74#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:41.74#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:41.74#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:39:41.74#ibcon#first serial, iclass 39, count 0 2006.257.02:39:41.74#ibcon#enter sib2, iclass 39, count 0 2006.257.02:39:41.74#ibcon#flushed, iclass 39, count 0 2006.257.02:39:41.74#ibcon#about to write, iclass 39, count 0 2006.257.02:39:41.74#ibcon#wrote, iclass 39, count 0 2006.257.02:39:41.74#ibcon#about to read 3, iclass 39, count 0 2006.257.02:39:41.76#ibcon#read 3, iclass 39, count 0 2006.257.02:39:41.76#ibcon#about to read 4, iclass 39, count 0 2006.257.02:39:41.76#ibcon#read 4, iclass 39, count 0 2006.257.02:39:41.76#ibcon#about to read 5, iclass 39, count 0 2006.257.02:39:41.76#ibcon#read 5, iclass 39, count 0 2006.257.02:39:41.76#ibcon#about to read 6, iclass 39, count 0 2006.257.02:39:41.76#ibcon#read 6, iclass 39, count 0 2006.257.02:39:41.76#ibcon#end of sib2, iclass 39, count 0 2006.257.02:39:41.76#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:39:41.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:39:41.76#ibcon#[27=USB\r\n] 2006.257.02:39:41.76#ibcon#*before write, iclass 39, count 0 2006.257.02:39:41.76#ibcon#enter sib2, iclass 39, count 0 2006.257.02:39:41.76#ibcon#flushed, iclass 39, count 0 2006.257.02:39:41.76#ibcon#about to write, iclass 39, count 0 2006.257.02:39:41.76#ibcon#wrote, iclass 39, count 0 2006.257.02:39:41.76#ibcon#about to read 3, iclass 39, count 0 2006.257.02:39:41.79#ibcon#read 3, iclass 39, count 0 2006.257.02:39:41.79#ibcon#about to read 4, iclass 39, count 0 2006.257.02:39:41.79#ibcon#read 4, iclass 39, count 0 2006.257.02:39:41.79#ibcon#about to read 5, iclass 39, count 0 2006.257.02:39:41.79#ibcon#read 5, iclass 39, count 0 2006.257.02:39:41.79#ibcon#about to read 6, iclass 39, count 0 2006.257.02:39:41.79#ibcon#read 6, iclass 39, count 0 2006.257.02:39:41.79#ibcon#end of sib2, iclass 39, count 0 2006.257.02:39:41.79#ibcon#*after write, iclass 39, count 0 2006.257.02:39:41.79#ibcon#*before return 0, iclass 39, count 0 2006.257.02:39:41.79#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:41.79#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:39:41.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:39:41.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:39:41.79$vck44/vblo=8,744.99 2006.257.02:39:41.79#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.02:39:41.79#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.02:39:41.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:39:41.79#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:41.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:41.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:41.79#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:39:41.79#ibcon#first serial, iclass 3, count 0 2006.257.02:39:41.79#ibcon#enter sib2, iclass 3, count 0 2006.257.02:39:41.79#ibcon#flushed, iclass 3, count 0 2006.257.02:39:41.79#ibcon#about to write, iclass 3, count 0 2006.257.02:39:41.79#ibcon#wrote, iclass 3, count 0 2006.257.02:39:41.79#ibcon#about to read 3, iclass 3, count 0 2006.257.02:39:41.81#ibcon#read 3, iclass 3, count 0 2006.257.02:39:41.81#ibcon#about to read 4, iclass 3, count 0 2006.257.02:39:41.81#ibcon#read 4, iclass 3, count 0 2006.257.02:39:41.81#ibcon#about to read 5, iclass 3, count 0 2006.257.02:39:41.81#ibcon#read 5, iclass 3, count 0 2006.257.02:39:41.81#ibcon#about to read 6, iclass 3, count 0 2006.257.02:39:41.81#ibcon#read 6, iclass 3, count 0 2006.257.02:39:41.81#ibcon#end of sib2, iclass 3, count 0 2006.257.02:39:41.81#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:39:41.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:39:41.81#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:39:41.81#ibcon#*before write, iclass 3, count 0 2006.257.02:39:41.81#ibcon#enter sib2, iclass 3, count 0 2006.257.02:39:41.81#ibcon#flushed, iclass 3, count 0 2006.257.02:39:41.81#ibcon#about to write, iclass 3, count 0 2006.257.02:39:41.81#ibcon#wrote, iclass 3, count 0 2006.257.02:39:41.81#ibcon#about to read 3, iclass 3, count 0 2006.257.02:39:41.85#ibcon#read 3, iclass 3, count 0 2006.257.02:39:41.85#ibcon#about to read 4, iclass 3, count 0 2006.257.02:39:41.85#ibcon#read 4, iclass 3, count 0 2006.257.02:39:41.85#ibcon#about to read 5, iclass 3, count 0 2006.257.02:39:41.85#ibcon#read 5, iclass 3, count 0 2006.257.02:39:41.85#ibcon#about to read 6, iclass 3, count 0 2006.257.02:39:41.85#ibcon#read 6, iclass 3, count 0 2006.257.02:39:41.85#ibcon#end of sib2, iclass 3, count 0 2006.257.02:39:41.85#ibcon#*after write, iclass 3, count 0 2006.257.02:39:41.85#ibcon#*before return 0, iclass 3, count 0 2006.257.02:39:41.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:41.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:39:41.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:39:41.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:39:41.85$vck44/vb=8,4 2006.257.02:39:41.85#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.02:39:41.85#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.02:39:41.85#ibcon#ireg 11 cls_cnt 2 2006.257.02:39:41.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:41.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:41.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:41.91#ibcon#enter wrdev, iclass 5, count 2 2006.257.02:39:41.91#ibcon#first serial, iclass 5, count 2 2006.257.02:39:41.91#ibcon#enter sib2, iclass 5, count 2 2006.257.02:39:41.91#ibcon#flushed, iclass 5, count 2 2006.257.02:39:41.91#ibcon#about to write, iclass 5, count 2 2006.257.02:39:41.91#ibcon#wrote, iclass 5, count 2 2006.257.02:39:41.91#ibcon#about to read 3, iclass 5, count 2 2006.257.02:39:41.93#ibcon#read 3, iclass 5, count 2 2006.257.02:39:41.93#ibcon#about to read 4, iclass 5, count 2 2006.257.02:39:41.93#ibcon#read 4, iclass 5, count 2 2006.257.02:39:41.93#ibcon#about to read 5, iclass 5, count 2 2006.257.02:39:41.93#ibcon#read 5, iclass 5, count 2 2006.257.02:39:41.93#ibcon#about to read 6, iclass 5, count 2 2006.257.02:39:41.93#ibcon#read 6, iclass 5, count 2 2006.257.02:39:41.93#ibcon#end of sib2, iclass 5, count 2 2006.257.02:39:41.93#ibcon#*mode == 0, iclass 5, count 2 2006.257.02:39:41.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.02:39:41.93#ibcon#[27=AT08-04\r\n] 2006.257.02:39:41.93#ibcon#*before write, iclass 5, count 2 2006.257.02:39:41.93#ibcon#enter sib2, iclass 5, count 2 2006.257.02:39:41.93#ibcon#flushed, iclass 5, count 2 2006.257.02:39:41.93#ibcon#about to write, iclass 5, count 2 2006.257.02:39:41.93#ibcon#wrote, iclass 5, count 2 2006.257.02:39:41.93#ibcon#about to read 3, iclass 5, count 2 2006.257.02:39:41.96#ibcon#read 3, iclass 5, count 2 2006.257.02:39:41.96#ibcon#about to read 4, iclass 5, count 2 2006.257.02:39:41.96#ibcon#read 4, iclass 5, count 2 2006.257.02:39:41.96#ibcon#about to read 5, iclass 5, count 2 2006.257.02:39:41.96#ibcon#read 5, iclass 5, count 2 2006.257.02:39:41.96#ibcon#about to read 6, iclass 5, count 2 2006.257.02:39:41.96#ibcon#read 6, iclass 5, count 2 2006.257.02:39:41.96#ibcon#end of sib2, iclass 5, count 2 2006.257.02:39:41.96#ibcon#*after write, iclass 5, count 2 2006.257.02:39:41.96#ibcon#*before return 0, iclass 5, count 2 2006.257.02:39:41.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:41.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:39:41.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.02:39:41.96#ibcon#ireg 7 cls_cnt 0 2006.257.02:39:41.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:42.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:42.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:42.08#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:39:42.08#ibcon#first serial, iclass 5, count 0 2006.257.02:39:42.08#ibcon#enter sib2, iclass 5, count 0 2006.257.02:39:42.08#ibcon#flushed, iclass 5, count 0 2006.257.02:39:42.08#ibcon#about to write, iclass 5, count 0 2006.257.02:39:42.08#ibcon#wrote, iclass 5, count 0 2006.257.02:39:42.08#ibcon#about to read 3, iclass 5, count 0 2006.257.02:39:42.10#ibcon#read 3, iclass 5, count 0 2006.257.02:39:42.10#ibcon#about to read 4, iclass 5, count 0 2006.257.02:39:42.10#ibcon#read 4, iclass 5, count 0 2006.257.02:39:42.10#ibcon#about to read 5, iclass 5, count 0 2006.257.02:39:42.10#ibcon#read 5, iclass 5, count 0 2006.257.02:39:42.10#ibcon#about to read 6, iclass 5, count 0 2006.257.02:39:42.10#ibcon#read 6, iclass 5, count 0 2006.257.02:39:42.10#ibcon#end of sib2, iclass 5, count 0 2006.257.02:39:42.10#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:39:42.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:39:42.10#ibcon#[27=USB\r\n] 2006.257.02:39:42.10#ibcon#*before write, iclass 5, count 0 2006.257.02:39:42.10#ibcon#enter sib2, iclass 5, count 0 2006.257.02:39:42.10#ibcon#flushed, iclass 5, count 0 2006.257.02:39:42.10#ibcon#about to write, iclass 5, count 0 2006.257.02:39:42.10#ibcon#wrote, iclass 5, count 0 2006.257.02:39:42.10#ibcon#about to read 3, iclass 5, count 0 2006.257.02:39:42.13#ibcon#read 3, iclass 5, count 0 2006.257.02:39:42.13#ibcon#about to read 4, iclass 5, count 0 2006.257.02:39:42.13#ibcon#read 4, iclass 5, count 0 2006.257.02:39:42.13#ibcon#about to read 5, iclass 5, count 0 2006.257.02:39:42.13#ibcon#read 5, iclass 5, count 0 2006.257.02:39:42.13#ibcon#about to read 6, iclass 5, count 0 2006.257.02:39:42.13#ibcon#read 6, iclass 5, count 0 2006.257.02:39:42.13#ibcon#end of sib2, iclass 5, count 0 2006.257.02:39:42.13#ibcon#*after write, iclass 5, count 0 2006.257.02:39:42.13#ibcon#*before return 0, iclass 5, count 0 2006.257.02:39:42.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:42.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:39:42.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:39:42.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:39:42.13$vck44/vabw=wide 2006.257.02:39:42.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.02:39:42.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.02:39:42.13#ibcon#ireg 8 cls_cnt 0 2006.257.02:39:42.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:42.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:42.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:42.13#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:39:42.13#ibcon#first serial, iclass 7, count 0 2006.257.02:39:42.13#ibcon#enter sib2, iclass 7, count 0 2006.257.02:39:42.13#ibcon#flushed, iclass 7, count 0 2006.257.02:39:42.13#ibcon#about to write, iclass 7, count 0 2006.257.02:39:42.13#ibcon#wrote, iclass 7, count 0 2006.257.02:39:42.13#ibcon#about to read 3, iclass 7, count 0 2006.257.02:39:42.15#ibcon#read 3, iclass 7, count 0 2006.257.02:39:42.15#ibcon#about to read 4, iclass 7, count 0 2006.257.02:39:42.15#ibcon#read 4, iclass 7, count 0 2006.257.02:39:42.15#ibcon#about to read 5, iclass 7, count 0 2006.257.02:39:42.15#ibcon#read 5, iclass 7, count 0 2006.257.02:39:42.15#ibcon#about to read 6, iclass 7, count 0 2006.257.02:39:42.15#ibcon#read 6, iclass 7, count 0 2006.257.02:39:42.15#ibcon#end of sib2, iclass 7, count 0 2006.257.02:39:42.15#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:39:42.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:39:42.15#ibcon#[25=BW32\r\n] 2006.257.02:39:42.15#ibcon#*before write, iclass 7, count 0 2006.257.02:39:42.15#ibcon#enter sib2, iclass 7, count 0 2006.257.02:39:42.15#ibcon#flushed, iclass 7, count 0 2006.257.02:39:42.15#ibcon#about to write, iclass 7, count 0 2006.257.02:39:42.15#ibcon#wrote, iclass 7, count 0 2006.257.02:39:42.15#ibcon#about to read 3, iclass 7, count 0 2006.257.02:39:42.18#ibcon#read 3, iclass 7, count 0 2006.257.02:39:42.18#ibcon#about to read 4, iclass 7, count 0 2006.257.02:39:42.18#ibcon#read 4, iclass 7, count 0 2006.257.02:39:42.18#ibcon#about to read 5, iclass 7, count 0 2006.257.02:39:42.18#ibcon#read 5, iclass 7, count 0 2006.257.02:39:42.18#ibcon#about to read 6, iclass 7, count 0 2006.257.02:39:42.18#ibcon#read 6, iclass 7, count 0 2006.257.02:39:42.18#ibcon#end of sib2, iclass 7, count 0 2006.257.02:39:42.18#ibcon#*after write, iclass 7, count 0 2006.257.02:39:42.18#ibcon#*before return 0, iclass 7, count 0 2006.257.02:39:42.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:42.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:39:42.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:39:42.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:39:42.18$vck44/vbbw=wide 2006.257.02:39:42.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.02:39:42.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.02:39:42.18#ibcon#ireg 8 cls_cnt 0 2006.257.02:39:42.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:39:42.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:39:42.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:39:42.25#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:39:42.25#ibcon#first serial, iclass 11, count 0 2006.257.02:39:42.25#ibcon#enter sib2, iclass 11, count 0 2006.257.02:39:42.25#ibcon#flushed, iclass 11, count 0 2006.257.02:39:42.25#ibcon#about to write, iclass 11, count 0 2006.257.02:39:42.25#ibcon#wrote, iclass 11, count 0 2006.257.02:39:42.25#ibcon#about to read 3, iclass 11, count 0 2006.257.02:39:42.27#ibcon#read 3, iclass 11, count 0 2006.257.02:39:42.27#ibcon#about to read 4, iclass 11, count 0 2006.257.02:39:42.27#ibcon#read 4, iclass 11, count 0 2006.257.02:39:42.27#ibcon#about to read 5, iclass 11, count 0 2006.257.02:39:42.27#ibcon#read 5, iclass 11, count 0 2006.257.02:39:42.27#ibcon#about to read 6, iclass 11, count 0 2006.257.02:39:42.27#ibcon#read 6, iclass 11, count 0 2006.257.02:39:42.27#ibcon#end of sib2, iclass 11, count 0 2006.257.02:39:42.27#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:39:42.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:39:42.27#ibcon#[27=BW32\r\n] 2006.257.02:39:42.27#ibcon#*before write, iclass 11, count 0 2006.257.02:39:42.27#ibcon#enter sib2, iclass 11, count 0 2006.257.02:39:42.27#ibcon#flushed, iclass 11, count 0 2006.257.02:39:42.27#ibcon#about to write, iclass 11, count 0 2006.257.02:39:42.27#ibcon#wrote, iclass 11, count 0 2006.257.02:39:42.27#ibcon#about to read 3, iclass 11, count 0 2006.257.02:39:42.30#ibcon#read 3, iclass 11, count 0 2006.257.02:39:42.30#ibcon#about to read 4, iclass 11, count 0 2006.257.02:39:42.30#ibcon#read 4, iclass 11, count 0 2006.257.02:39:42.30#ibcon#about to read 5, iclass 11, count 0 2006.257.02:39:42.30#ibcon#read 5, iclass 11, count 0 2006.257.02:39:42.30#ibcon#about to read 6, iclass 11, count 0 2006.257.02:39:42.30#ibcon#read 6, iclass 11, count 0 2006.257.02:39:42.30#ibcon#end of sib2, iclass 11, count 0 2006.257.02:39:42.30#ibcon#*after write, iclass 11, count 0 2006.257.02:39:42.30#ibcon#*before return 0, iclass 11, count 0 2006.257.02:39:42.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:39:42.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:39:42.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:39:42.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:39:42.30$setupk4/ifdk4 2006.257.02:39:42.30$ifdk4/lo= 2006.257.02:39:42.30$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:39:42.30$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:39:42.30$ifdk4/patch= 2006.257.02:39:42.30$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:39:42.30$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:39:42.30$setupk4/!*+20s 2006.257.02:39:46.33#abcon#<5=/01 1.3 4.8 18.48 971012.4\r\n> 2006.257.02:39:46.35#abcon#{5=INTERFACE CLEAR} 2006.257.02:39:46.41#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:39:56.50#abcon#<5=/01 1.2 4.8 18.49 971012.4\r\n> 2006.257.02:39:56.52#abcon#{5=INTERFACE CLEAR} 2006.257.02:39:56.58#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:39:56.80$setupk4/"tpicd 2006.257.02:39:56.80$setupk4/echo=off 2006.257.02:39:56.80$setupk4/xlog=off 2006.257.02:39:56.80:!2006.257.02:42:39 2006.257.02:40:02.14#trakl#Source acquired 2006.257.02:40:02.14#flagr#flagr/antenna,acquired 2006.257.02:42:39.00:preob 2006.257.02:42:39.14/onsource/TRACKING 2006.257.02:42:39.14:!2006.257.02:42:49 2006.257.02:42:49.00:"tape 2006.257.02:42:49.00:"st=record 2006.257.02:42:49.00:data_valid=on 2006.257.02:42:49.00:midob 2006.257.02:42:50.14/onsource/TRACKING 2006.257.02:42:50.14/wx/18.65,1012.5,96 2006.257.02:42:50.36/cable/+6.4860E-03 2006.257.02:42:51.45/va/01,08,usb,yes,40,43 2006.257.02:42:51.45/va/02,07,usb,yes,43,44 2006.257.02:42:51.45/va/03,08,usb,yes,39,41 2006.257.02:42:51.45/va/04,07,usb,yes,45,47 2006.257.02:42:51.45/va/05,04,usb,yes,40,41 2006.257.02:42:51.45/va/06,04,usb,yes,44,44 2006.257.02:42:51.45/va/07,04,usb,yes,45,46 2006.257.02:42:51.45/va/08,04,usb,yes,38,46 2006.257.02:42:51.68/valo/01,524.99,yes,locked 2006.257.02:42:51.68/valo/02,534.99,yes,locked 2006.257.02:42:51.68/valo/03,564.99,yes,locked 2006.257.02:42:51.68/valo/04,624.99,yes,locked 2006.257.02:42:51.68/valo/05,734.99,yes,locked 2006.257.02:42:51.68/valo/06,814.99,yes,locked 2006.257.02:42:51.68/valo/07,864.99,yes,locked 2006.257.02:42:51.68/valo/08,884.99,yes,locked 2006.257.02:42:52.77/vb/01,04,usb,yes,34,32 2006.257.02:42:52.77/vb/02,05,usb,yes,33,32 2006.257.02:42:52.77/vb/03,04,usb,yes,34,37 2006.257.02:42:52.77/vb/04,05,usb,yes,34,33 2006.257.02:42:52.77/vb/05,04,usb,yes,30,33 2006.257.02:42:52.77/vb/06,04,usb,yes,35,31 2006.257.02:42:52.77/vb/07,04,usb,yes,35,35 2006.257.02:42:52.77/vb/08,04,usb,yes,32,36 2006.257.02:42:53.01/vblo/01,629.99,yes,locked 2006.257.02:42:53.01/vblo/02,634.99,yes,locked 2006.257.02:42:53.01/vblo/03,649.99,yes,locked 2006.257.02:42:53.01/vblo/04,679.99,yes,locked 2006.257.02:42:53.01/vblo/05,709.99,yes,locked 2006.257.02:42:53.01/vblo/06,719.99,yes,locked 2006.257.02:42:53.01/vblo/07,734.99,yes,locked 2006.257.02:42:53.01/vblo/08,744.99,yes,locked 2006.257.02:42:53.16/vabw/8 2006.257.02:42:53.31/vbbw/8 2006.257.02:42:53.40/xfe/off,on,15.5 2006.257.02:42:53.79/ifatt/23,28,28,28 2006.257.02:42:54.07/fmout-gps/S +4.59E-07 2006.257.02:42:54.11:!2006.257.02:43:29 2006.257.02:43:29.00:data_valid=off 2006.257.02:43:29.00:"et 2006.257.02:43:29.01:!+3s 2006.257.02:43:32.03:"tape 2006.257.02:43:32.03:postob 2006.257.02:43:32.20/cable/+6.4858E-03 2006.257.02:43:32.20/wx/18.67,1012.5,95 2006.257.02:43:32.26/fmout-gps/S +4.59E-07 2006.257.02:43:32.26:scan_name=257-0244,jd0609,410 2006.257.02:43:32.27:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.257.02:43:34.14#flagr#flagr/antenna,new-source 2006.257.02:43:34.14:checkk5 2006.257.02:43:34.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:43:34.99/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:43:35.42/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:43:35.88/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:43:36.24/chk_obsdata//k5ts1/T2570242??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.02:43:36.61/chk_obsdata//k5ts2/T2570242??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.02:43:37.01/chk_obsdata//k5ts3/T2570242??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.02:43:37.65/chk_obsdata//k5ts4/T2570242??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.02:43:38.47/k5log//k5ts1_log_newline 2006.257.02:43:39.49/k5log//k5ts2_log_newline 2006.257.02:43:40.31/k5log//k5ts3_log_newline 2006.257.02:43:41.07/k5log//k5ts4_log_newline 2006.257.02:43:41.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:43:41.09:setupk4=1 2006.257.02:43:41.09$setupk4/echo=on 2006.257.02:43:41.09$setupk4/pcalon 2006.257.02:43:41.09$pcalon/"no phase cal control is implemented here 2006.257.02:43:41.09$setupk4/"tpicd=stop 2006.257.02:43:41.09$setupk4/"rec=synch_on 2006.257.02:43:41.09$setupk4/"rec_mode=128 2006.257.02:43:41.09$setupk4/!* 2006.257.02:43:41.09$setupk4/recpk4 2006.257.02:43:41.09$recpk4/recpatch= 2006.257.02:43:41.09$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:43:41.09$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:43:41.09$setupk4/vck44 2006.257.02:43:41.09$vck44/valo=1,524.99 2006.257.02:43:41.09#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.02:43:41.09#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.02:43:41.09#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:41.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:41.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:41.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:41.09#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:43:41.09#ibcon#first serial, iclass 31, count 0 2006.257.02:43:41.09#ibcon#enter sib2, iclass 31, count 0 2006.257.02:43:41.09#ibcon#flushed, iclass 31, count 0 2006.257.02:43:41.09#ibcon#about to write, iclass 31, count 0 2006.257.02:43:41.09#ibcon#wrote, iclass 31, count 0 2006.257.02:43:41.09#ibcon#about to read 3, iclass 31, count 0 2006.257.02:43:41.13#ibcon#read 3, iclass 31, count 0 2006.257.02:43:41.13#ibcon#about to read 4, iclass 31, count 0 2006.257.02:43:41.13#ibcon#read 4, iclass 31, count 0 2006.257.02:43:41.13#ibcon#about to read 5, iclass 31, count 0 2006.257.02:43:41.13#ibcon#read 5, iclass 31, count 0 2006.257.02:43:41.13#ibcon#about to read 6, iclass 31, count 0 2006.257.02:43:41.13#ibcon#read 6, iclass 31, count 0 2006.257.02:43:41.13#ibcon#end of sib2, iclass 31, count 0 2006.257.02:43:41.13#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:43:41.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:43:41.13#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:43:41.13#ibcon#*before write, iclass 31, count 0 2006.257.02:43:41.13#ibcon#enter sib2, iclass 31, count 0 2006.257.02:43:41.13#ibcon#flushed, iclass 31, count 0 2006.257.02:43:41.13#ibcon#about to write, iclass 31, count 0 2006.257.02:43:41.13#ibcon#wrote, iclass 31, count 0 2006.257.02:43:41.13#ibcon#about to read 3, iclass 31, count 0 2006.257.02:43:41.18#ibcon#read 3, iclass 31, count 0 2006.257.02:43:41.18#ibcon#about to read 4, iclass 31, count 0 2006.257.02:43:41.18#ibcon#read 4, iclass 31, count 0 2006.257.02:43:41.18#ibcon#about to read 5, iclass 31, count 0 2006.257.02:43:41.18#ibcon#read 5, iclass 31, count 0 2006.257.02:43:41.18#ibcon#about to read 6, iclass 31, count 0 2006.257.02:43:41.18#ibcon#read 6, iclass 31, count 0 2006.257.02:43:41.18#ibcon#end of sib2, iclass 31, count 0 2006.257.02:43:41.18#ibcon#*after write, iclass 31, count 0 2006.257.02:43:41.18#ibcon#*before return 0, iclass 31, count 0 2006.257.02:43:41.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:41.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:41.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:43:41.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:43:41.18$vck44/va=1,8 2006.257.02:43:41.18#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.02:43:41.18#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.02:43:41.18#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:41.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:41.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:41.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:41.18#ibcon#enter wrdev, iclass 33, count 2 2006.257.02:43:41.18#ibcon#first serial, iclass 33, count 2 2006.257.02:43:41.18#ibcon#enter sib2, iclass 33, count 2 2006.257.02:43:41.18#ibcon#flushed, iclass 33, count 2 2006.257.02:43:41.18#ibcon#about to write, iclass 33, count 2 2006.257.02:43:41.18#ibcon#wrote, iclass 33, count 2 2006.257.02:43:41.18#ibcon#about to read 3, iclass 33, count 2 2006.257.02:43:41.21#ibcon#read 3, iclass 33, count 2 2006.257.02:43:41.21#ibcon#about to read 4, iclass 33, count 2 2006.257.02:43:41.21#ibcon#read 4, iclass 33, count 2 2006.257.02:43:41.21#ibcon#about to read 5, iclass 33, count 2 2006.257.02:43:41.21#ibcon#read 5, iclass 33, count 2 2006.257.02:43:41.21#ibcon#about to read 6, iclass 33, count 2 2006.257.02:43:41.21#ibcon#read 6, iclass 33, count 2 2006.257.02:43:41.21#ibcon#end of sib2, iclass 33, count 2 2006.257.02:43:41.21#ibcon#*mode == 0, iclass 33, count 2 2006.257.02:43:41.21#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.02:43:41.21#ibcon#[25=AT01-08\r\n] 2006.257.02:43:41.21#ibcon#*before write, iclass 33, count 2 2006.257.02:43:41.21#ibcon#enter sib2, iclass 33, count 2 2006.257.02:43:41.21#ibcon#flushed, iclass 33, count 2 2006.257.02:43:41.21#ibcon#about to write, iclass 33, count 2 2006.257.02:43:41.21#ibcon#wrote, iclass 33, count 2 2006.257.02:43:41.21#ibcon#about to read 3, iclass 33, count 2 2006.257.02:43:41.24#ibcon#read 3, iclass 33, count 2 2006.257.02:43:41.24#ibcon#about to read 4, iclass 33, count 2 2006.257.02:43:41.24#ibcon#read 4, iclass 33, count 2 2006.257.02:43:41.24#ibcon#about to read 5, iclass 33, count 2 2006.257.02:43:41.24#ibcon#read 5, iclass 33, count 2 2006.257.02:43:41.24#ibcon#about to read 6, iclass 33, count 2 2006.257.02:43:41.24#ibcon#read 6, iclass 33, count 2 2006.257.02:43:41.24#ibcon#end of sib2, iclass 33, count 2 2006.257.02:43:41.24#ibcon#*after write, iclass 33, count 2 2006.257.02:43:41.24#ibcon#*before return 0, iclass 33, count 2 2006.257.02:43:41.24#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:41.24#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:41.24#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.02:43:41.24#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:41.24#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:41.36#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:41.36#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:41.36#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:43:41.36#ibcon#first serial, iclass 33, count 0 2006.257.02:43:41.36#ibcon#enter sib2, iclass 33, count 0 2006.257.02:43:41.36#ibcon#flushed, iclass 33, count 0 2006.257.02:43:41.36#ibcon#about to write, iclass 33, count 0 2006.257.02:43:41.36#ibcon#wrote, iclass 33, count 0 2006.257.02:43:41.36#ibcon#about to read 3, iclass 33, count 0 2006.257.02:43:41.38#ibcon#read 3, iclass 33, count 0 2006.257.02:43:41.38#ibcon#about to read 4, iclass 33, count 0 2006.257.02:43:41.38#ibcon#read 4, iclass 33, count 0 2006.257.02:43:41.38#ibcon#about to read 5, iclass 33, count 0 2006.257.02:43:41.38#ibcon#read 5, iclass 33, count 0 2006.257.02:43:41.38#ibcon#about to read 6, iclass 33, count 0 2006.257.02:43:41.38#ibcon#read 6, iclass 33, count 0 2006.257.02:43:41.38#ibcon#end of sib2, iclass 33, count 0 2006.257.02:43:41.38#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:43:41.38#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:43:41.38#ibcon#[25=USB\r\n] 2006.257.02:43:41.38#ibcon#*before write, iclass 33, count 0 2006.257.02:43:41.38#ibcon#enter sib2, iclass 33, count 0 2006.257.02:43:41.38#ibcon#flushed, iclass 33, count 0 2006.257.02:43:41.38#ibcon#about to write, iclass 33, count 0 2006.257.02:43:41.38#ibcon#wrote, iclass 33, count 0 2006.257.02:43:41.38#ibcon#about to read 3, iclass 33, count 0 2006.257.02:43:41.41#ibcon#read 3, iclass 33, count 0 2006.257.02:43:41.41#ibcon#about to read 4, iclass 33, count 0 2006.257.02:43:41.41#ibcon#read 4, iclass 33, count 0 2006.257.02:43:41.41#ibcon#about to read 5, iclass 33, count 0 2006.257.02:43:41.41#ibcon#read 5, iclass 33, count 0 2006.257.02:43:41.41#ibcon#about to read 6, iclass 33, count 0 2006.257.02:43:41.41#ibcon#read 6, iclass 33, count 0 2006.257.02:43:41.41#ibcon#end of sib2, iclass 33, count 0 2006.257.02:43:41.41#ibcon#*after write, iclass 33, count 0 2006.257.02:43:41.41#ibcon#*before return 0, iclass 33, count 0 2006.257.02:43:41.41#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:41.41#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:41.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:43:41.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:43:41.41$vck44/valo=2,534.99 2006.257.02:43:41.41#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.02:43:41.41#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.02:43:41.41#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:41.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:41.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:41.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:41.41#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:43:41.41#ibcon#first serial, iclass 35, count 0 2006.257.02:43:41.41#ibcon#enter sib2, iclass 35, count 0 2006.257.02:43:41.41#ibcon#flushed, iclass 35, count 0 2006.257.02:43:41.41#ibcon#about to write, iclass 35, count 0 2006.257.02:43:41.41#ibcon#wrote, iclass 35, count 0 2006.257.02:43:41.41#ibcon#about to read 3, iclass 35, count 0 2006.257.02:43:41.44#ibcon#read 3, iclass 35, count 0 2006.257.02:43:41.44#ibcon#about to read 4, iclass 35, count 0 2006.257.02:43:41.44#ibcon#read 4, iclass 35, count 0 2006.257.02:43:41.44#ibcon#about to read 5, iclass 35, count 0 2006.257.02:43:41.44#ibcon#read 5, iclass 35, count 0 2006.257.02:43:41.44#ibcon#about to read 6, iclass 35, count 0 2006.257.02:43:41.44#ibcon#read 6, iclass 35, count 0 2006.257.02:43:41.44#ibcon#end of sib2, iclass 35, count 0 2006.257.02:43:41.44#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:43:41.44#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:43:41.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:43:41.44#ibcon#*before write, iclass 35, count 0 2006.257.02:43:41.44#ibcon#enter sib2, iclass 35, count 0 2006.257.02:43:41.44#ibcon#flushed, iclass 35, count 0 2006.257.02:43:41.44#ibcon#about to write, iclass 35, count 0 2006.257.02:43:41.44#ibcon#wrote, iclass 35, count 0 2006.257.02:43:41.44#ibcon#about to read 3, iclass 35, count 0 2006.257.02:43:41.48#ibcon#read 3, iclass 35, count 0 2006.257.02:43:41.48#ibcon#about to read 4, iclass 35, count 0 2006.257.02:43:41.48#ibcon#read 4, iclass 35, count 0 2006.257.02:43:41.48#ibcon#about to read 5, iclass 35, count 0 2006.257.02:43:41.48#ibcon#read 5, iclass 35, count 0 2006.257.02:43:41.48#ibcon#about to read 6, iclass 35, count 0 2006.257.02:43:41.48#ibcon#read 6, iclass 35, count 0 2006.257.02:43:41.48#ibcon#end of sib2, iclass 35, count 0 2006.257.02:43:41.48#ibcon#*after write, iclass 35, count 0 2006.257.02:43:41.48#ibcon#*before return 0, iclass 35, count 0 2006.257.02:43:41.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:41.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:41.48#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:43:41.48#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:43:41.48$vck44/va=2,7 2006.257.02:43:41.48#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.02:43:41.48#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.02:43:41.48#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:41.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:41.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:41.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:41.53#ibcon#enter wrdev, iclass 37, count 2 2006.257.02:43:41.53#ibcon#first serial, iclass 37, count 2 2006.257.02:43:41.53#ibcon#enter sib2, iclass 37, count 2 2006.257.02:43:41.53#ibcon#flushed, iclass 37, count 2 2006.257.02:43:41.53#ibcon#about to write, iclass 37, count 2 2006.257.02:43:41.53#ibcon#wrote, iclass 37, count 2 2006.257.02:43:41.53#ibcon#about to read 3, iclass 37, count 2 2006.257.02:43:41.55#ibcon#read 3, iclass 37, count 2 2006.257.02:43:41.55#ibcon#about to read 4, iclass 37, count 2 2006.257.02:43:41.55#ibcon#read 4, iclass 37, count 2 2006.257.02:43:41.55#ibcon#about to read 5, iclass 37, count 2 2006.257.02:43:41.55#ibcon#read 5, iclass 37, count 2 2006.257.02:43:41.55#ibcon#about to read 6, iclass 37, count 2 2006.257.02:43:41.55#ibcon#read 6, iclass 37, count 2 2006.257.02:43:41.55#ibcon#end of sib2, iclass 37, count 2 2006.257.02:43:41.55#ibcon#*mode == 0, iclass 37, count 2 2006.257.02:43:41.55#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.02:43:41.55#ibcon#[25=AT02-07\r\n] 2006.257.02:43:41.55#ibcon#*before write, iclass 37, count 2 2006.257.02:43:41.55#ibcon#enter sib2, iclass 37, count 2 2006.257.02:43:41.55#ibcon#flushed, iclass 37, count 2 2006.257.02:43:41.55#ibcon#about to write, iclass 37, count 2 2006.257.02:43:41.55#ibcon#wrote, iclass 37, count 2 2006.257.02:43:41.55#ibcon#about to read 3, iclass 37, count 2 2006.257.02:43:41.58#ibcon#read 3, iclass 37, count 2 2006.257.02:43:41.58#ibcon#about to read 4, iclass 37, count 2 2006.257.02:43:41.58#ibcon#read 4, iclass 37, count 2 2006.257.02:43:41.58#ibcon#about to read 5, iclass 37, count 2 2006.257.02:43:41.58#ibcon#read 5, iclass 37, count 2 2006.257.02:43:41.58#ibcon#about to read 6, iclass 37, count 2 2006.257.02:43:41.58#ibcon#read 6, iclass 37, count 2 2006.257.02:43:41.58#ibcon#end of sib2, iclass 37, count 2 2006.257.02:43:41.58#ibcon#*after write, iclass 37, count 2 2006.257.02:43:41.58#ibcon#*before return 0, iclass 37, count 2 2006.257.02:43:41.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:41.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:41.58#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.02:43:41.58#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:41.58#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:41.70#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:41.70#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:41.70#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:43:41.70#ibcon#first serial, iclass 37, count 0 2006.257.02:43:41.70#ibcon#enter sib2, iclass 37, count 0 2006.257.02:43:41.70#ibcon#flushed, iclass 37, count 0 2006.257.02:43:41.70#ibcon#about to write, iclass 37, count 0 2006.257.02:43:41.70#ibcon#wrote, iclass 37, count 0 2006.257.02:43:41.70#ibcon#about to read 3, iclass 37, count 0 2006.257.02:43:41.72#ibcon#read 3, iclass 37, count 0 2006.257.02:43:41.72#ibcon#about to read 4, iclass 37, count 0 2006.257.02:43:41.72#ibcon#read 4, iclass 37, count 0 2006.257.02:43:41.72#ibcon#about to read 5, iclass 37, count 0 2006.257.02:43:41.72#ibcon#read 5, iclass 37, count 0 2006.257.02:43:41.72#ibcon#about to read 6, iclass 37, count 0 2006.257.02:43:41.72#ibcon#read 6, iclass 37, count 0 2006.257.02:43:41.72#ibcon#end of sib2, iclass 37, count 0 2006.257.02:43:41.72#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:43:41.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:43:41.72#ibcon#[25=USB\r\n] 2006.257.02:43:41.72#ibcon#*before write, iclass 37, count 0 2006.257.02:43:41.72#ibcon#enter sib2, iclass 37, count 0 2006.257.02:43:41.72#ibcon#flushed, iclass 37, count 0 2006.257.02:43:41.72#ibcon#about to write, iclass 37, count 0 2006.257.02:43:41.72#ibcon#wrote, iclass 37, count 0 2006.257.02:43:41.72#ibcon#about to read 3, iclass 37, count 0 2006.257.02:43:41.75#ibcon#read 3, iclass 37, count 0 2006.257.02:43:41.75#ibcon#about to read 4, iclass 37, count 0 2006.257.02:43:41.75#ibcon#read 4, iclass 37, count 0 2006.257.02:43:41.75#ibcon#about to read 5, iclass 37, count 0 2006.257.02:43:41.75#ibcon#read 5, iclass 37, count 0 2006.257.02:43:41.75#ibcon#about to read 6, iclass 37, count 0 2006.257.02:43:41.75#ibcon#read 6, iclass 37, count 0 2006.257.02:43:41.75#ibcon#end of sib2, iclass 37, count 0 2006.257.02:43:41.75#ibcon#*after write, iclass 37, count 0 2006.257.02:43:41.75#ibcon#*before return 0, iclass 37, count 0 2006.257.02:43:41.75#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:41.75#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:41.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:43:41.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:43:41.75$vck44/valo=3,564.99 2006.257.02:43:41.75#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.02:43:41.75#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.02:43:41.75#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:41.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:41.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:41.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:41.75#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:43:41.75#ibcon#first serial, iclass 39, count 0 2006.257.02:43:41.75#ibcon#enter sib2, iclass 39, count 0 2006.257.02:43:41.75#ibcon#flushed, iclass 39, count 0 2006.257.02:43:41.75#ibcon#about to write, iclass 39, count 0 2006.257.02:43:41.75#ibcon#wrote, iclass 39, count 0 2006.257.02:43:41.75#ibcon#about to read 3, iclass 39, count 0 2006.257.02:43:41.78#ibcon#read 3, iclass 39, count 0 2006.257.02:43:41.78#ibcon#about to read 4, iclass 39, count 0 2006.257.02:43:41.78#ibcon#read 4, iclass 39, count 0 2006.257.02:43:41.78#ibcon#about to read 5, iclass 39, count 0 2006.257.02:43:41.78#ibcon#read 5, iclass 39, count 0 2006.257.02:43:41.78#ibcon#about to read 6, iclass 39, count 0 2006.257.02:43:41.78#ibcon#read 6, iclass 39, count 0 2006.257.02:43:41.78#ibcon#end of sib2, iclass 39, count 0 2006.257.02:43:41.78#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:43:41.78#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:43:41.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:43:41.78#ibcon#*before write, iclass 39, count 0 2006.257.02:43:41.78#ibcon#enter sib2, iclass 39, count 0 2006.257.02:43:41.78#ibcon#flushed, iclass 39, count 0 2006.257.02:43:41.78#ibcon#about to write, iclass 39, count 0 2006.257.02:43:41.78#ibcon#wrote, iclass 39, count 0 2006.257.02:43:41.78#ibcon#about to read 3, iclass 39, count 0 2006.257.02:43:41.82#ibcon#read 3, iclass 39, count 0 2006.257.02:43:41.82#ibcon#about to read 4, iclass 39, count 0 2006.257.02:43:41.82#ibcon#read 4, iclass 39, count 0 2006.257.02:43:41.82#ibcon#about to read 5, iclass 39, count 0 2006.257.02:43:41.82#ibcon#read 5, iclass 39, count 0 2006.257.02:43:41.82#ibcon#about to read 6, iclass 39, count 0 2006.257.02:43:41.82#ibcon#read 6, iclass 39, count 0 2006.257.02:43:41.82#ibcon#end of sib2, iclass 39, count 0 2006.257.02:43:41.82#ibcon#*after write, iclass 39, count 0 2006.257.02:43:41.82#ibcon#*before return 0, iclass 39, count 0 2006.257.02:43:41.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:41.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:41.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:43:41.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:43:41.82$vck44/va=3,8 2006.257.02:43:41.82#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.02:43:41.82#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.02:43:41.82#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:41.82#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:41.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:41.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:41.87#ibcon#enter wrdev, iclass 3, count 2 2006.257.02:43:41.87#ibcon#first serial, iclass 3, count 2 2006.257.02:43:41.87#ibcon#enter sib2, iclass 3, count 2 2006.257.02:43:41.87#ibcon#flushed, iclass 3, count 2 2006.257.02:43:41.87#ibcon#about to write, iclass 3, count 2 2006.257.02:43:41.87#ibcon#wrote, iclass 3, count 2 2006.257.02:43:41.87#ibcon#about to read 3, iclass 3, count 2 2006.257.02:43:41.89#ibcon#read 3, iclass 3, count 2 2006.257.02:43:41.89#ibcon#about to read 4, iclass 3, count 2 2006.257.02:43:41.89#ibcon#read 4, iclass 3, count 2 2006.257.02:43:41.89#ibcon#about to read 5, iclass 3, count 2 2006.257.02:43:41.89#ibcon#read 5, iclass 3, count 2 2006.257.02:43:41.89#ibcon#about to read 6, iclass 3, count 2 2006.257.02:43:41.89#ibcon#read 6, iclass 3, count 2 2006.257.02:43:41.89#ibcon#end of sib2, iclass 3, count 2 2006.257.02:43:41.89#ibcon#*mode == 0, iclass 3, count 2 2006.257.02:43:41.89#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.02:43:41.89#ibcon#[25=AT03-08\r\n] 2006.257.02:43:41.89#ibcon#*before write, iclass 3, count 2 2006.257.02:43:41.89#ibcon#enter sib2, iclass 3, count 2 2006.257.02:43:41.89#ibcon#flushed, iclass 3, count 2 2006.257.02:43:41.89#ibcon#about to write, iclass 3, count 2 2006.257.02:43:41.89#ibcon#wrote, iclass 3, count 2 2006.257.02:43:41.89#ibcon#about to read 3, iclass 3, count 2 2006.257.02:43:41.92#ibcon#read 3, iclass 3, count 2 2006.257.02:43:41.92#ibcon#about to read 4, iclass 3, count 2 2006.257.02:43:41.92#ibcon#read 4, iclass 3, count 2 2006.257.02:43:41.92#ibcon#about to read 5, iclass 3, count 2 2006.257.02:43:41.92#ibcon#read 5, iclass 3, count 2 2006.257.02:43:41.92#ibcon#about to read 6, iclass 3, count 2 2006.257.02:43:41.92#ibcon#read 6, iclass 3, count 2 2006.257.02:43:41.92#ibcon#end of sib2, iclass 3, count 2 2006.257.02:43:41.92#ibcon#*after write, iclass 3, count 2 2006.257.02:43:41.92#ibcon#*before return 0, iclass 3, count 2 2006.257.02:43:41.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:41.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:41.92#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.02:43:41.92#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:41.92#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:42.04#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:42.04#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:42.04#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:43:42.04#ibcon#first serial, iclass 3, count 0 2006.257.02:43:42.04#ibcon#enter sib2, iclass 3, count 0 2006.257.02:43:42.04#ibcon#flushed, iclass 3, count 0 2006.257.02:43:42.04#ibcon#about to write, iclass 3, count 0 2006.257.02:43:42.04#ibcon#wrote, iclass 3, count 0 2006.257.02:43:42.04#ibcon#about to read 3, iclass 3, count 0 2006.257.02:43:42.06#ibcon#read 3, iclass 3, count 0 2006.257.02:43:42.06#ibcon#about to read 4, iclass 3, count 0 2006.257.02:43:42.06#ibcon#read 4, iclass 3, count 0 2006.257.02:43:42.06#ibcon#about to read 5, iclass 3, count 0 2006.257.02:43:42.06#ibcon#read 5, iclass 3, count 0 2006.257.02:43:42.06#ibcon#about to read 6, iclass 3, count 0 2006.257.02:43:42.06#ibcon#read 6, iclass 3, count 0 2006.257.02:43:42.06#ibcon#end of sib2, iclass 3, count 0 2006.257.02:43:42.06#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:43:42.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:43:42.06#ibcon#[25=USB\r\n] 2006.257.02:43:42.06#ibcon#*before write, iclass 3, count 0 2006.257.02:43:42.06#ibcon#enter sib2, iclass 3, count 0 2006.257.02:43:42.06#ibcon#flushed, iclass 3, count 0 2006.257.02:43:42.06#ibcon#about to write, iclass 3, count 0 2006.257.02:43:42.06#ibcon#wrote, iclass 3, count 0 2006.257.02:43:42.06#ibcon#about to read 3, iclass 3, count 0 2006.257.02:43:42.09#ibcon#read 3, iclass 3, count 0 2006.257.02:43:42.09#ibcon#about to read 4, iclass 3, count 0 2006.257.02:43:42.09#ibcon#read 4, iclass 3, count 0 2006.257.02:43:42.09#ibcon#about to read 5, iclass 3, count 0 2006.257.02:43:42.09#ibcon#read 5, iclass 3, count 0 2006.257.02:43:42.09#ibcon#about to read 6, iclass 3, count 0 2006.257.02:43:42.09#ibcon#read 6, iclass 3, count 0 2006.257.02:43:42.09#ibcon#end of sib2, iclass 3, count 0 2006.257.02:43:42.09#ibcon#*after write, iclass 3, count 0 2006.257.02:43:42.09#ibcon#*before return 0, iclass 3, count 0 2006.257.02:43:42.09#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:42.09#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:42.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:43:42.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:43:42.09$vck44/valo=4,624.99 2006.257.02:43:42.09#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.02:43:42.09#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.02:43:42.09#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:42.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:42.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:42.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:42.09#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:43:42.09#ibcon#first serial, iclass 5, count 0 2006.257.02:43:42.09#ibcon#enter sib2, iclass 5, count 0 2006.257.02:43:42.09#ibcon#flushed, iclass 5, count 0 2006.257.02:43:42.09#ibcon#about to write, iclass 5, count 0 2006.257.02:43:42.09#ibcon#wrote, iclass 5, count 0 2006.257.02:43:42.09#ibcon#about to read 3, iclass 5, count 0 2006.257.02:43:42.11#ibcon#read 3, iclass 5, count 0 2006.257.02:43:42.11#ibcon#about to read 4, iclass 5, count 0 2006.257.02:43:42.11#ibcon#read 4, iclass 5, count 0 2006.257.02:43:42.11#ibcon#about to read 5, iclass 5, count 0 2006.257.02:43:42.11#ibcon#read 5, iclass 5, count 0 2006.257.02:43:42.11#ibcon#about to read 6, iclass 5, count 0 2006.257.02:43:42.11#ibcon#read 6, iclass 5, count 0 2006.257.02:43:42.11#ibcon#end of sib2, iclass 5, count 0 2006.257.02:43:42.11#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:43:42.11#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:43:42.11#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:43:42.11#ibcon#*before write, iclass 5, count 0 2006.257.02:43:42.11#ibcon#enter sib2, iclass 5, count 0 2006.257.02:43:42.11#ibcon#flushed, iclass 5, count 0 2006.257.02:43:42.11#ibcon#about to write, iclass 5, count 0 2006.257.02:43:42.11#ibcon#wrote, iclass 5, count 0 2006.257.02:43:42.11#ibcon#about to read 3, iclass 5, count 0 2006.257.02:43:42.15#ibcon#read 3, iclass 5, count 0 2006.257.02:43:42.15#ibcon#about to read 4, iclass 5, count 0 2006.257.02:43:42.15#ibcon#read 4, iclass 5, count 0 2006.257.02:43:42.15#ibcon#about to read 5, iclass 5, count 0 2006.257.02:43:42.15#ibcon#read 5, iclass 5, count 0 2006.257.02:43:42.15#ibcon#about to read 6, iclass 5, count 0 2006.257.02:43:42.15#ibcon#read 6, iclass 5, count 0 2006.257.02:43:42.15#ibcon#end of sib2, iclass 5, count 0 2006.257.02:43:42.15#ibcon#*after write, iclass 5, count 0 2006.257.02:43:42.15#ibcon#*before return 0, iclass 5, count 0 2006.257.02:43:42.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:42.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:42.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:43:42.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:43:42.15$vck44/va=4,7 2006.257.02:43:42.15#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.02:43:42.15#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.02:43:42.15#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:42.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:42.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:42.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:42.21#ibcon#enter wrdev, iclass 7, count 2 2006.257.02:43:42.21#ibcon#first serial, iclass 7, count 2 2006.257.02:43:42.21#ibcon#enter sib2, iclass 7, count 2 2006.257.02:43:42.21#ibcon#flushed, iclass 7, count 2 2006.257.02:43:42.21#ibcon#about to write, iclass 7, count 2 2006.257.02:43:42.21#ibcon#wrote, iclass 7, count 2 2006.257.02:43:42.21#ibcon#about to read 3, iclass 7, count 2 2006.257.02:43:42.23#ibcon#read 3, iclass 7, count 2 2006.257.02:43:42.23#ibcon#about to read 4, iclass 7, count 2 2006.257.02:43:42.23#ibcon#read 4, iclass 7, count 2 2006.257.02:43:42.23#ibcon#about to read 5, iclass 7, count 2 2006.257.02:43:42.23#ibcon#read 5, iclass 7, count 2 2006.257.02:43:42.23#ibcon#about to read 6, iclass 7, count 2 2006.257.02:43:42.23#ibcon#read 6, iclass 7, count 2 2006.257.02:43:42.23#ibcon#end of sib2, iclass 7, count 2 2006.257.02:43:42.23#ibcon#*mode == 0, iclass 7, count 2 2006.257.02:43:42.23#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.02:43:42.23#ibcon#[25=AT04-07\r\n] 2006.257.02:43:42.23#ibcon#*before write, iclass 7, count 2 2006.257.02:43:42.23#ibcon#enter sib2, iclass 7, count 2 2006.257.02:43:42.23#ibcon#flushed, iclass 7, count 2 2006.257.02:43:42.23#ibcon#about to write, iclass 7, count 2 2006.257.02:43:42.23#ibcon#wrote, iclass 7, count 2 2006.257.02:43:42.23#ibcon#about to read 3, iclass 7, count 2 2006.257.02:43:42.26#ibcon#read 3, iclass 7, count 2 2006.257.02:43:42.26#ibcon#about to read 4, iclass 7, count 2 2006.257.02:43:42.26#ibcon#read 4, iclass 7, count 2 2006.257.02:43:42.26#ibcon#about to read 5, iclass 7, count 2 2006.257.02:43:42.26#ibcon#read 5, iclass 7, count 2 2006.257.02:43:42.26#ibcon#about to read 6, iclass 7, count 2 2006.257.02:43:42.26#ibcon#read 6, iclass 7, count 2 2006.257.02:43:42.26#ibcon#end of sib2, iclass 7, count 2 2006.257.02:43:42.26#ibcon#*after write, iclass 7, count 2 2006.257.02:43:42.26#ibcon#*before return 0, iclass 7, count 2 2006.257.02:43:42.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:42.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:42.26#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.02:43:42.26#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:42.26#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:42.38#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:42.38#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:42.38#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:43:42.38#ibcon#first serial, iclass 7, count 0 2006.257.02:43:42.38#ibcon#enter sib2, iclass 7, count 0 2006.257.02:43:42.38#ibcon#flushed, iclass 7, count 0 2006.257.02:43:42.38#ibcon#about to write, iclass 7, count 0 2006.257.02:43:42.38#ibcon#wrote, iclass 7, count 0 2006.257.02:43:42.38#ibcon#about to read 3, iclass 7, count 0 2006.257.02:43:42.40#ibcon#read 3, iclass 7, count 0 2006.257.02:43:42.40#ibcon#about to read 4, iclass 7, count 0 2006.257.02:43:42.40#ibcon#read 4, iclass 7, count 0 2006.257.02:43:42.40#ibcon#about to read 5, iclass 7, count 0 2006.257.02:43:42.40#ibcon#read 5, iclass 7, count 0 2006.257.02:43:42.40#ibcon#about to read 6, iclass 7, count 0 2006.257.02:43:42.40#ibcon#read 6, iclass 7, count 0 2006.257.02:43:42.40#ibcon#end of sib2, iclass 7, count 0 2006.257.02:43:42.40#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:43:42.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:43:42.40#ibcon#[25=USB\r\n] 2006.257.02:43:42.40#ibcon#*before write, iclass 7, count 0 2006.257.02:43:42.40#ibcon#enter sib2, iclass 7, count 0 2006.257.02:43:42.40#ibcon#flushed, iclass 7, count 0 2006.257.02:43:42.40#ibcon#about to write, iclass 7, count 0 2006.257.02:43:42.40#ibcon#wrote, iclass 7, count 0 2006.257.02:43:42.40#ibcon#about to read 3, iclass 7, count 0 2006.257.02:43:42.43#ibcon#read 3, iclass 7, count 0 2006.257.02:43:42.43#ibcon#about to read 4, iclass 7, count 0 2006.257.02:43:42.43#ibcon#read 4, iclass 7, count 0 2006.257.02:43:42.43#ibcon#about to read 5, iclass 7, count 0 2006.257.02:43:42.43#ibcon#read 5, iclass 7, count 0 2006.257.02:43:42.43#ibcon#about to read 6, iclass 7, count 0 2006.257.02:43:42.43#ibcon#read 6, iclass 7, count 0 2006.257.02:43:42.43#ibcon#end of sib2, iclass 7, count 0 2006.257.02:43:42.43#ibcon#*after write, iclass 7, count 0 2006.257.02:43:42.43#ibcon#*before return 0, iclass 7, count 0 2006.257.02:43:42.43#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:42.43#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:42.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:43:42.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:43:42.43$vck44/valo=5,734.99 2006.257.02:43:42.43#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.02:43:42.43#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.02:43:42.43#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:42.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:42.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:42.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:42.43#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:43:42.43#ibcon#first serial, iclass 11, count 0 2006.257.02:43:42.43#ibcon#enter sib2, iclass 11, count 0 2006.257.02:43:42.43#ibcon#flushed, iclass 11, count 0 2006.257.02:43:42.43#ibcon#about to write, iclass 11, count 0 2006.257.02:43:42.43#ibcon#wrote, iclass 11, count 0 2006.257.02:43:42.43#ibcon#about to read 3, iclass 11, count 0 2006.257.02:43:42.45#ibcon#read 3, iclass 11, count 0 2006.257.02:43:42.45#ibcon#about to read 4, iclass 11, count 0 2006.257.02:43:42.45#ibcon#read 4, iclass 11, count 0 2006.257.02:43:42.45#ibcon#about to read 5, iclass 11, count 0 2006.257.02:43:42.45#ibcon#read 5, iclass 11, count 0 2006.257.02:43:42.45#ibcon#about to read 6, iclass 11, count 0 2006.257.02:43:42.45#ibcon#read 6, iclass 11, count 0 2006.257.02:43:42.45#ibcon#end of sib2, iclass 11, count 0 2006.257.02:43:42.45#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:43:42.45#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:43:42.45#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:43:42.45#ibcon#*before write, iclass 11, count 0 2006.257.02:43:42.45#ibcon#enter sib2, iclass 11, count 0 2006.257.02:43:42.45#ibcon#flushed, iclass 11, count 0 2006.257.02:43:42.45#ibcon#about to write, iclass 11, count 0 2006.257.02:43:42.45#ibcon#wrote, iclass 11, count 0 2006.257.02:43:42.45#ibcon#about to read 3, iclass 11, count 0 2006.257.02:43:42.49#ibcon#read 3, iclass 11, count 0 2006.257.02:43:42.49#ibcon#about to read 4, iclass 11, count 0 2006.257.02:43:42.49#ibcon#read 4, iclass 11, count 0 2006.257.02:43:42.49#ibcon#about to read 5, iclass 11, count 0 2006.257.02:43:42.49#ibcon#read 5, iclass 11, count 0 2006.257.02:43:42.49#ibcon#about to read 6, iclass 11, count 0 2006.257.02:43:42.49#ibcon#read 6, iclass 11, count 0 2006.257.02:43:42.49#ibcon#end of sib2, iclass 11, count 0 2006.257.02:43:42.49#ibcon#*after write, iclass 11, count 0 2006.257.02:43:42.49#ibcon#*before return 0, iclass 11, count 0 2006.257.02:43:42.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:42.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:42.49#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:43:42.49#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:43:42.49$vck44/va=5,4 2006.257.02:43:42.49#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.02:43:42.49#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.02:43:42.49#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:42.49#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:42.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:42.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:42.55#ibcon#enter wrdev, iclass 13, count 2 2006.257.02:43:42.55#ibcon#first serial, iclass 13, count 2 2006.257.02:43:42.55#ibcon#enter sib2, iclass 13, count 2 2006.257.02:43:42.55#ibcon#flushed, iclass 13, count 2 2006.257.02:43:42.55#ibcon#about to write, iclass 13, count 2 2006.257.02:43:42.55#ibcon#wrote, iclass 13, count 2 2006.257.02:43:42.55#ibcon#about to read 3, iclass 13, count 2 2006.257.02:43:42.57#ibcon#read 3, iclass 13, count 2 2006.257.02:43:42.57#ibcon#about to read 4, iclass 13, count 2 2006.257.02:43:42.57#ibcon#read 4, iclass 13, count 2 2006.257.02:43:42.57#ibcon#about to read 5, iclass 13, count 2 2006.257.02:43:42.57#ibcon#read 5, iclass 13, count 2 2006.257.02:43:42.57#ibcon#about to read 6, iclass 13, count 2 2006.257.02:43:42.57#ibcon#read 6, iclass 13, count 2 2006.257.02:43:42.57#ibcon#end of sib2, iclass 13, count 2 2006.257.02:43:42.57#ibcon#*mode == 0, iclass 13, count 2 2006.257.02:43:42.57#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.02:43:42.57#ibcon#[25=AT05-04\r\n] 2006.257.02:43:42.57#ibcon#*before write, iclass 13, count 2 2006.257.02:43:42.57#ibcon#enter sib2, iclass 13, count 2 2006.257.02:43:42.57#ibcon#flushed, iclass 13, count 2 2006.257.02:43:42.57#ibcon#about to write, iclass 13, count 2 2006.257.02:43:42.57#ibcon#wrote, iclass 13, count 2 2006.257.02:43:42.57#ibcon#about to read 3, iclass 13, count 2 2006.257.02:43:42.60#ibcon#read 3, iclass 13, count 2 2006.257.02:43:42.60#ibcon#about to read 4, iclass 13, count 2 2006.257.02:43:42.60#ibcon#read 4, iclass 13, count 2 2006.257.02:43:42.60#ibcon#about to read 5, iclass 13, count 2 2006.257.02:43:42.60#ibcon#read 5, iclass 13, count 2 2006.257.02:43:42.60#ibcon#about to read 6, iclass 13, count 2 2006.257.02:43:42.60#ibcon#read 6, iclass 13, count 2 2006.257.02:43:42.60#ibcon#end of sib2, iclass 13, count 2 2006.257.02:43:42.60#ibcon#*after write, iclass 13, count 2 2006.257.02:43:42.60#ibcon#*before return 0, iclass 13, count 2 2006.257.02:43:42.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:42.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:42.60#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.02:43:42.60#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:42.60#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:42.72#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:42.72#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:42.72#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:43:42.72#ibcon#first serial, iclass 13, count 0 2006.257.02:43:42.72#ibcon#enter sib2, iclass 13, count 0 2006.257.02:43:42.72#ibcon#flushed, iclass 13, count 0 2006.257.02:43:42.72#ibcon#about to write, iclass 13, count 0 2006.257.02:43:42.72#ibcon#wrote, iclass 13, count 0 2006.257.02:43:42.72#ibcon#about to read 3, iclass 13, count 0 2006.257.02:43:42.74#ibcon#read 3, iclass 13, count 0 2006.257.02:43:42.74#ibcon#about to read 4, iclass 13, count 0 2006.257.02:43:42.74#ibcon#read 4, iclass 13, count 0 2006.257.02:43:42.74#ibcon#about to read 5, iclass 13, count 0 2006.257.02:43:42.74#ibcon#read 5, iclass 13, count 0 2006.257.02:43:42.74#ibcon#about to read 6, iclass 13, count 0 2006.257.02:43:42.74#ibcon#read 6, iclass 13, count 0 2006.257.02:43:42.74#ibcon#end of sib2, iclass 13, count 0 2006.257.02:43:42.74#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:43:42.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:43:42.74#ibcon#[25=USB\r\n] 2006.257.02:43:42.74#ibcon#*before write, iclass 13, count 0 2006.257.02:43:42.74#ibcon#enter sib2, iclass 13, count 0 2006.257.02:43:42.74#ibcon#flushed, iclass 13, count 0 2006.257.02:43:42.74#ibcon#about to write, iclass 13, count 0 2006.257.02:43:42.74#ibcon#wrote, iclass 13, count 0 2006.257.02:43:42.74#ibcon#about to read 3, iclass 13, count 0 2006.257.02:43:42.77#ibcon#read 3, iclass 13, count 0 2006.257.02:43:42.77#ibcon#about to read 4, iclass 13, count 0 2006.257.02:43:42.77#ibcon#read 4, iclass 13, count 0 2006.257.02:43:42.77#ibcon#about to read 5, iclass 13, count 0 2006.257.02:43:42.77#ibcon#read 5, iclass 13, count 0 2006.257.02:43:42.77#ibcon#about to read 6, iclass 13, count 0 2006.257.02:43:42.77#ibcon#read 6, iclass 13, count 0 2006.257.02:43:42.77#ibcon#end of sib2, iclass 13, count 0 2006.257.02:43:42.77#ibcon#*after write, iclass 13, count 0 2006.257.02:43:42.77#ibcon#*before return 0, iclass 13, count 0 2006.257.02:43:42.77#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:42.77#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:42.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:43:42.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:43:42.77$vck44/valo=6,814.99 2006.257.02:43:42.77#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.02:43:42.77#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.02:43:42.77#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:42.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:42.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:42.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:42.77#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:43:42.77#ibcon#first serial, iclass 15, count 0 2006.257.02:43:42.77#ibcon#enter sib2, iclass 15, count 0 2006.257.02:43:42.77#ibcon#flushed, iclass 15, count 0 2006.257.02:43:42.77#ibcon#about to write, iclass 15, count 0 2006.257.02:43:42.77#ibcon#wrote, iclass 15, count 0 2006.257.02:43:42.77#ibcon#about to read 3, iclass 15, count 0 2006.257.02:43:42.79#ibcon#read 3, iclass 15, count 0 2006.257.02:43:42.79#ibcon#about to read 4, iclass 15, count 0 2006.257.02:43:42.79#ibcon#read 4, iclass 15, count 0 2006.257.02:43:42.79#ibcon#about to read 5, iclass 15, count 0 2006.257.02:43:42.79#ibcon#read 5, iclass 15, count 0 2006.257.02:43:42.79#ibcon#about to read 6, iclass 15, count 0 2006.257.02:43:42.79#ibcon#read 6, iclass 15, count 0 2006.257.02:43:42.79#ibcon#end of sib2, iclass 15, count 0 2006.257.02:43:42.79#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:43:42.79#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:43:42.79#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:43:42.79#ibcon#*before write, iclass 15, count 0 2006.257.02:43:42.79#ibcon#enter sib2, iclass 15, count 0 2006.257.02:43:42.79#ibcon#flushed, iclass 15, count 0 2006.257.02:43:42.79#ibcon#about to write, iclass 15, count 0 2006.257.02:43:42.79#ibcon#wrote, iclass 15, count 0 2006.257.02:43:42.79#ibcon#about to read 3, iclass 15, count 0 2006.257.02:43:42.83#ibcon#read 3, iclass 15, count 0 2006.257.02:43:42.83#ibcon#about to read 4, iclass 15, count 0 2006.257.02:43:42.83#ibcon#read 4, iclass 15, count 0 2006.257.02:43:42.83#ibcon#about to read 5, iclass 15, count 0 2006.257.02:43:42.83#ibcon#read 5, iclass 15, count 0 2006.257.02:43:42.83#ibcon#about to read 6, iclass 15, count 0 2006.257.02:43:42.83#ibcon#read 6, iclass 15, count 0 2006.257.02:43:42.83#ibcon#end of sib2, iclass 15, count 0 2006.257.02:43:42.83#ibcon#*after write, iclass 15, count 0 2006.257.02:43:42.83#ibcon#*before return 0, iclass 15, count 0 2006.257.02:43:42.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:42.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:42.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:43:42.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:43:42.83$vck44/va=6,4 2006.257.02:43:42.83#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.02:43:42.83#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.02:43:42.83#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:42.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:42.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:42.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:42.89#ibcon#enter wrdev, iclass 17, count 2 2006.257.02:43:42.89#ibcon#first serial, iclass 17, count 2 2006.257.02:43:42.89#ibcon#enter sib2, iclass 17, count 2 2006.257.02:43:42.89#ibcon#flushed, iclass 17, count 2 2006.257.02:43:42.89#ibcon#about to write, iclass 17, count 2 2006.257.02:43:42.89#ibcon#wrote, iclass 17, count 2 2006.257.02:43:42.89#ibcon#about to read 3, iclass 17, count 2 2006.257.02:43:42.91#ibcon#read 3, iclass 17, count 2 2006.257.02:43:42.91#ibcon#about to read 4, iclass 17, count 2 2006.257.02:43:42.91#ibcon#read 4, iclass 17, count 2 2006.257.02:43:42.91#ibcon#about to read 5, iclass 17, count 2 2006.257.02:43:42.91#ibcon#read 5, iclass 17, count 2 2006.257.02:43:42.91#ibcon#about to read 6, iclass 17, count 2 2006.257.02:43:42.91#ibcon#read 6, iclass 17, count 2 2006.257.02:43:42.91#ibcon#end of sib2, iclass 17, count 2 2006.257.02:43:42.91#ibcon#*mode == 0, iclass 17, count 2 2006.257.02:43:42.91#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.02:43:42.91#ibcon#[25=AT06-04\r\n] 2006.257.02:43:42.91#ibcon#*before write, iclass 17, count 2 2006.257.02:43:42.91#ibcon#enter sib2, iclass 17, count 2 2006.257.02:43:42.91#ibcon#flushed, iclass 17, count 2 2006.257.02:43:42.91#ibcon#about to write, iclass 17, count 2 2006.257.02:43:42.91#ibcon#wrote, iclass 17, count 2 2006.257.02:43:42.91#ibcon#about to read 3, iclass 17, count 2 2006.257.02:43:42.94#ibcon#read 3, iclass 17, count 2 2006.257.02:43:42.94#ibcon#about to read 4, iclass 17, count 2 2006.257.02:43:42.94#ibcon#read 4, iclass 17, count 2 2006.257.02:43:42.94#ibcon#about to read 5, iclass 17, count 2 2006.257.02:43:42.94#ibcon#read 5, iclass 17, count 2 2006.257.02:43:42.94#ibcon#about to read 6, iclass 17, count 2 2006.257.02:43:42.94#ibcon#read 6, iclass 17, count 2 2006.257.02:43:42.94#ibcon#end of sib2, iclass 17, count 2 2006.257.02:43:42.94#ibcon#*after write, iclass 17, count 2 2006.257.02:43:42.94#ibcon#*before return 0, iclass 17, count 2 2006.257.02:43:42.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:42.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:42.94#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.02:43:42.94#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:42.94#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:43.06#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:43.06#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:43.06#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:43:43.06#ibcon#first serial, iclass 17, count 0 2006.257.02:43:43.06#ibcon#enter sib2, iclass 17, count 0 2006.257.02:43:43.06#ibcon#flushed, iclass 17, count 0 2006.257.02:43:43.06#ibcon#about to write, iclass 17, count 0 2006.257.02:43:43.06#ibcon#wrote, iclass 17, count 0 2006.257.02:43:43.06#ibcon#about to read 3, iclass 17, count 0 2006.257.02:43:43.08#ibcon#read 3, iclass 17, count 0 2006.257.02:43:43.08#ibcon#about to read 4, iclass 17, count 0 2006.257.02:43:43.08#ibcon#read 4, iclass 17, count 0 2006.257.02:43:43.08#ibcon#about to read 5, iclass 17, count 0 2006.257.02:43:43.08#ibcon#read 5, iclass 17, count 0 2006.257.02:43:43.08#ibcon#about to read 6, iclass 17, count 0 2006.257.02:43:43.08#ibcon#read 6, iclass 17, count 0 2006.257.02:43:43.08#ibcon#end of sib2, iclass 17, count 0 2006.257.02:43:43.08#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:43:43.08#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:43:43.08#ibcon#[25=USB\r\n] 2006.257.02:43:43.08#ibcon#*before write, iclass 17, count 0 2006.257.02:43:43.08#ibcon#enter sib2, iclass 17, count 0 2006.257.02:43:43.08#ibcon#flushed, iclass 17, count 0 2006.257.02:43:43.08#ibcon#about to write, iclass 17, count 0 2006.257.02:43:43.08#ibcon#wrote, iclass 17, count 0 2006.257.02:43:43.08#ibcon#about to read 3, iclass 17, count 0 2006.257.02:43:43.08#abcon#<5=/01 1.1 3.1 18.68 961012.5\r\n> 2006.257.02:43:43.10#abcon#{5=INTERFACE CLEAR} 2006.257.02:43:43.11#ibcon#read 3, iclass 17, count 0 2006.257.02:43:43.11#ibcon#about to read 4, iclass 17, count 0 2006.257.02:43:43.11#ibcon#read 4, iclass 17, count 0 2006.257.02:43:43.11#ibcon#about to read 5, iclass 17, count 0 2006.257.02:43:43.11#ibcon#read 5, iclass 17, count 0 2006.257.02:43:43.11#ibcon#about to read 6, iclass 17, count 0 2006.257.02:43:43.11#ibcon#read 6, iclass 17, count 0 2006.257.02:43:43.11#ibcon#end of sib2, iclass 17, count 0 2006.257.02:43:43.11#ibcon#*after write, iclass 17, count 0 2006.257.02:43:43.11#ibcon#*before return 0, iclass 17, count 0 2006.257.02:43:43.11#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:43.11#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:43.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:43:43.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:43:43.11$vck44/valo=7,864.99 2006.257.02:43:43.11#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.02:43:43.11#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.02:43:43.11#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:43.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:43:43.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:43:43.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:43:43.11#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:43:43.11#ibcon#first serial, iclass 22, count 0 2006.257.02:43:43.11#ibcon#enter sib2, iclass 22, count 0 2006.257.02:43:43.11#ibcon#flushed, iclass 22, count 0 2006.257.02:43:43.11#ibcon#about to write, iclass 22, count 0 2006.257.02:43:43.11#ibcon#wrote, iclass 22, count 0 2006.257.02:43:43.11#ibcon#about to read 3, iclass 22, count 0 2006.257.02:43:43.13#ibcon#read 3, iclass 22, count 0 2006.257.02:43:43.13#ibcon#about to read 4, iclass 22, count 0 2006.257.02:43:43.13#ibcon#read 4, iclass 22, count 0 2006.257.02:43:43.13#ibcon#about to read 5, iclass 22, count 0 2006.257.02:43:43.13#ibcon#read 5, iclass 22, count 0 2006.257.02:43:43.13#ibcon#about to read 6, iclass 22, count 0 2006.257.02:43:43.13#ibcon#read 6, iclass 22, count 0 2006.257.02:43:43.13#ibcon#end of sib2, iclass 22, count 0 2006.257.02:43:43.13#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:43:43.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:43:43.13#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:43:43.13#ibcon#*before write, iclass 22, count 0 2006.257.02:43:43.13#ibcon#enter sib2, iclass 22, count 0 2006.257.02:43:43.13#ibcon#flushed, iclass 22, count 0 2006.257.02:43:43.13#ibcon#about to write, iclass 22, count 0 2006.257.02:43:43.13#ibcon#wrote, iclass 22, count 0 2006.257.02:43:43.13#ibcon#about to read 3, iclass 22, count 0 2006.257.02:43:43.16#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:43:43.17#ibcon#read 3, iclass 22, count 0 2006.257.02:43:43.17#ibcon#about to read 4, iclass 22, count 0 2006.257.02:43:43.17#ibcon#read 4, iclass 22, count 0 2006.257.02:43:43.17#ibcon#about to read 5, iclass 22, count 0 2006.257.02:43:43.17#ibcon#read 5, iclass 22, count 0 2006.257.02:43:43.17#ibcon#about to read 6, iclass 22, count 0 2006.257.02:43:43.17#ibcon#read 6, iclass 22, count 0 2006.257.02:43:43.17#ibcon#end of sib2, iclass 22, count 0 2006.257.02:43:43.17#ibcon#*after write, iclass 22, count 0 2006.257.02:43:43.17#ibcon#*before return 0, iclass 22, count 0 2006.257.02:43:43.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:43:43.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.02:43:43.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:43:43.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:43:43.17$vck44/va=7,4 2006.257.02:43:43.17#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.02:43:43.17#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.02:43:43.17#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:43.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:43.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:43.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:43.23#ibcon#enter wrdev, iclass 25, count 2 2006.257.02:43:43.23#ibcon#first serial, iclass 25, count 2 2006.257.02:43:43.23#ibcon#enter sib2, iclass 25, count 2 2006.257.02:43:43.23#ibcon#flushed, iclass 25, count 2 2006.257.02:43:43.23#ibcon#about to write, iclass 25, count 2 2006.257.02:43:43.23#ibcon#wrote, iclass 25, count 2 2006.257.02:43:43.23#ibcon#about to read 3, iclass 25, count 2 2006.257.02:43:43.25#ibcon#read 3, iclass 25, count 2 2006.257.02:43:43.25#ibcon#about to read 4, iclass 25, count 2 2006.257.02:43:43.25#ibcon#read 4, iclass 25, count 2 2006.257.02:43:43.25#ibcon#about to read 5, iclass 25, count 2 2006.257.02:43:43.25#ibcon#read 5, iclass 25, count 2 2006.257.02:43:43.25#ibcon#about to read 6, iclass 25, count 2 2006.257.02:43:43.25#ibcon#read 6, iclass 25, count 2 2006.257.02:43:43.25#ibcon#end of sib2, iclass 25, count 2 2006.257.02:43:43.25#ibcon#*mode == 0, iclass 25, count 2 2006.257.02:43:43.25#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.02:43:43.25#ibcon#[25=AT07-04\r\n] 2006.257.02:43:43.25#ibcon#*before write, iclass 25, count 2 2006.257.02:43:43.25#ibcon#enter sib2, iclass 25, count 2 2006.257.02:43:43.25#ibcon#flushed, iclass 25, count 2 2006.257.02:43:43.25#ibcon#about to write, iclass 25, count 2 2006.257.02:43:43.25#ibcon#wrote, iclass 25, count 2 2006.257.02:43:43.25#ibcon#about to read 3, iclass 25, count 2 2006.257.02:43:43.28#ibcon#read 3, iclass 25, count 2 2006.257.02:43:43.28#ibcon#about to read 4, iclass 25, count 2 2006.257.02:43:43.28#ibcon#read 4, iclass 25, count 2 2006.257.02:43:43.28#ibcon#about to read 5, iclass 25, count 2 2006.257.02:43:43.28#ibcon#read 5, iclass 25, count 2 2006.257.02:43:43.28#ibcon#about to read 6, iclass 25, count 2 2006.257.02:43:43.28#ibcon#read 6, iclass 25, count 2 2006.257.02:43:43.28#ibcon#end of sib2, iclass 25, count 2 2006.257.02:43:43.28#ibcon#*after write, iclass 25, count 2 2006.257.02:43:43.28#ibcon#*before return 0, iclass 25, count 2 2006.257.02:43:43.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:43.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:43.28#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.02:43:43.28#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:43.28#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:43.40#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:43.40#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:43.40#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:43:43.40#ibcon#first serial, iclass 25, count 0 2006.257.02:43:43.40#ibcon#enter sib2, iclass 25, count 0 2006.257.02:43:43.40#ibcon#flushed, iclass 25, count 0 2006.257.02:43:43.40#ibcon#about to write, iclass 25, count 0 2006.257.02:43:43.40#ibcon#wrote, iclass 25, count 0 2006.257.02:43:43.40#ibcon#about to read 3, iclass 25, count 0 2006.257.02:43:43.42#ibcon#read 3, iclass 25, count 0 2006.257.02:43:43.42#ibcon#about to read 4, iclass 25, count 0 2006.257.02:43:43.42#ibcon#read 4, iclass 25, count 0 2006.257.02:43:43.42#ibcon#about to read 5, iclass 25, count 0 2006.257.02:43:43.42#ibcon#read 5, iclass 25, count 0 2006.257.02:43:43.42#ibcon#about to read 6, iclass 25, count 0 2006.257.02:43:43.42#ibcon#read 6, iclass 25, count 0 2006.257.02:43:43.42#ibcon#end of sib2, iclass 25, count 0 2006.257.02:43:43.42#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:43:43.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:43:43.42#ibcon#[25=USB\r\n] 2006.257.02:43:43.42#ibcon#*before write, iclass 25, count 0 2006.257.02:43:43.42#ibcon#enter sib2, iclass 25, count 0 2006.257.02:43:43.42#ibcon#flushed, iclass 25, count 0 2006.257.02:43:43.42#ibcon#about to write, iclass 25, count 0 2006.257.02:43:43.42#ibcon#wrote, iclass 25, count 0 2006.257.02:43:43.42#ibcon#about to read 3, iclass 25, count 0 2006.257.02:43:43.45#ibcon#read 3, iclass 25, count 0 2006.257.02:43:43.45#ibcon#about to read 4, iclass 25, count 0 2006.257.02:43:43.45#ibcon#read 4, iclass 25, count 0 2006.257.02:43:43.45#ibcon#about to read 5, iclass 25, count 0 2006.257.02:43:43.45#ibcon#read 5, iclass 25, count 0 2006.257.02:43:43.45#ibcon#about to read 6, iclass 25, count 0 2006.257.02:43:43.45#ibcon#read 6, iclass 25, count 0 2006.257.02:43:43.45#ibcon#end of sib2, iclass 25, count 0 2006.257.02:43:43.45#ibcon#*after write, iclass 25, count 0 2006.257.02:43:43.45#ibcon#*before return 0, iclass 25, count 0 2006.257.02:43:43.45#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:43.45#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:43.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:43:43.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:43:43.45$vck44/valo=8,884.99 2006.257.02:43:43.45#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.02:43:43.45#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.02:43:43.45#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:43.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:43.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:43.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:43.45#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:43:43.45#ibcon#first serial, iclass 27, count 0 2006.257.02:43:43.45#ibcon#enter sib2, iclass 27, count 0 2006.257.02:43:43.45#ibcon#flushed, iclass 27, count 0 2006.257.02:43:43.45#ibcon#about to write, iclass 27, count 0 2006.257.02:43:43.45#ibcon#wrote, iclass 27, count 0 2006.257.02:43:43.45#ibcon#about to read 3, iclass 27, count 0 2006.257.02:43:43.47#ibcon#read 3, iclass 27, count 0 2006.257.02:43:43.47#ibcon#about to read 4, iclass 27, count 0 2006.257.02:43:43.47#ibcon#read 4, iclass 27, count 0 2006.257.02:43:43.47#ibcon#about to read 5, iclass 27, count 0 2006.257.02:43:43.47#ibcon#read 5, iclass 27, count 0 2006.257.02:43:43.47#ibcon#about to read 6, iclass 27, count 0 2006.257.02:43:43.47#ibcon#read 6, iclass 27, count 0 2006.257.02:43:43.47#ibcon#end of sib2, iclass 27, count 0 2006.257.02:43:43.47#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:43:43.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:43:43.47#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:43:43.47#ibcon#*before write, iclass 27, count 0 2006.257.02:43:43.47#ibcon#enter sib2, iclass 27, count 0 2006.257.02:43:43.47#ibcon#flushed, iclass 27, count 0 2006.257.02:43:43.47#ibcon#about to write, iclass 27, count 0 2006.257.02:43:43.47#ibcon#wrote, iclass 27, count 0 2006.257.02:43:43.47#ibcon#about to read 3, iclass 27, count 0 2006.257.02:43:43.51#ibcon#read 3, iclass 27, count 0 2006.257.02:43:43.51#ibcon#about to read 4, iclass 27, count 0 2006.257.02:43:43.51#ibcon#read 4, iclass 27, count 0 2006.257.02:43:43.51#ibcon#about to read 5, iclass 27, count 0 2006.257.02:43:43.51#ibcon#read 5, iclass 27, count 0 2006.257.02:43:43.51#ibcon#about to read 6, iclass 27, count 0 2006.257.02:43:43.51#ibcon#read 6, iclass 27, count 0 2006.257.02:43:43.51#ibcon#end of sib2, iclass 27, count 0 2006.257.02:43:43.51#ibcon#*after write, iclass 27, count 0 2006.257.02:43:43.51#ibcon#*before return 0, iclass 27, count 0 2006.257.02:43:43.51#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:43.51#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:43.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:43:43.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:43:43.51$vck44/va=8,4 2006.257.02:43:43.51#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.02:43:43.51#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.02:43:43.51#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:43.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:43:43.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:43:43.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:43:43.57#ibcon#enter wrdev, iclass 29, count 2 2006.257.02:43:43.57#ibcon#first serial, iclass 29, count 2 2006.257.02:43:43.57#ibcon#enter sib2, iclass 29, count 2 2006.257.02:43:43.57#ibcon#flushed, iclass 29, count 2 2006.257.02:43:43.57#ibcon#about to write, iclass 29, count 2 2006.257.02:43:43.57#ibcon#wrote, iclass 29, count 2 2006.257.02:43:43.57#ibcon#about to read 3, iclass 29, count 2 2006.257.02:43:43.59#ibcon#read 3, iclass 29, count 2 2006.257.02:43:43.59#ibcon#about to read 4, iclass 29, count 2 2006.257.02:43:43.59#ibcon#read 4, iclass 29, count 2 2006.257.02:43:43.59#ibcon#about to read 5, iclass 29, count 2 2006.257.02:43:43.59#ibcon#read 5, iclass 29, count 2 2006.257.02:43:43.59#ibcon#about to read 6, iclass 29, count 2 2006.257.02:43:43.59#ibcon#read 6, iclass 29, count 2 2006.257.02:43:43.59#ibcon#end of sib2, iclass 29, count 2 2006.257.02:43:43.59#ibcon#*mode == 0, iclass 29, count 2 2006.257.02:43:43.59#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.02:43:43.59#ibcon#[25=AT08-04\r\n] 2006.257.02:43:43.59#ibcon#*before write, iclass 29, count 2 2006.257.02:43:43.59#ibcon#enter sib2, iclass 29, count 2 2006.257.02:43:43.59#ibcon#flushed, iclass 29, count 2 2006.257.02:43:43.59#ibcon#about to write, iclass 29, count 2 2006.257.02:43:43.59#ibcon#wrote, iclass 29, count 2 2006.257.02:43:43.59#ibcon#about to read 3, iclass 29, count 2 2006.257.02:43:43.62#ibcon#read 3, iclass 29, count 2 2006.257.02:43:43.62#ibcon#about to read 4, iclass 29, count 2 2006.257.02:43:43.62#ibcon#read 4, iclass 29, count 2 2006.257.02:43:43.62#ibcon#about to read 5, iclass 29, count 2 2006.257.02:43:43.62#ibcon#read 5, iclass 29, count 2 2006.257.02:43:43.62#ibcon#about to read 6, iclass 29, count 2 2006.257.02:43:43.62#ibcon#read 6, iclass 29, count 2 2006.257.02:43:43.62#ibcon#end of sib2, iclass 29, count 2 2006.257.02:43:43.62#ibcon#*after write, iclass 29, count 2 2006.257.02:43:43.62#ibcon#*before return 0, iclass 29, count 2 2006.257.02:43:43.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:43:43.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:43:43.62#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.02:43:43.62#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:43.62#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:43:43.74#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:43:43.74#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:43:43.74#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:43:43.74#ibcon#first serial, iclass 29, count 0 2006.257.02:43:43.74#ibcon#enter sib2, iclass 29, count 0 2006.257.02:43:43.74#ibcon#flushed, iclass 29, count 0 2006.257.02:43:43.74#ibcon#about to write, iclass 29, count 0 2006.257.02:43:43.74#ibcon#wrote, iclass 29, count 0 2006.257.02:43:43.74#ibcon#about to read 3, iclass 29, count 0 2006.257.02:43:43.76#ibcon#read 3, iclass 29, count 0 2006.257.02:43:43.76#ibcon#about to read 4, iclass 29, count 0 2006.257.02:43:43.76#ibcon#read 4, iclass 29, count 0 2006.257.02:43:43.76#ibcon#about to read 5, iclass 29, count 0 2006.257.02:43:43.76#ibcon#read 5, iclass 29, count 0 2006.257.02:43:43.76#ibcon#about to read 6, iclass 29, count 0 2006.257.02:43:43.76#ibcon#read 6, iclass 29, count 0 2006.257.02:43:43.76#ibcon#end of sib2, iclass 29, count 0 2006.257.02:43:43.76#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:43:43.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:43:43.76#ibcon#[25=USB\r\n] 2006.257.02:43:43.76#ibcon#*before write, iclass 29, count 0 2006.257.02:43:43.76#ibcon#enter sib2, iclass 29, count 0 2006.257.02:43:43.76#ibcon#flushed, iclass 29, count 0 2006.257.02:43:43.76#ibcon#about to write, iclass 29, count 0 2006.257.02:43:43.76#ibcon#wrote, iclass 29, count 0 2006.257.02:43:43.76#ibcon#about to read 3, iclass 29, count 0 2006.257.02:43:43.79#ibcon#read 3, iclass 29, count 0 2006.257.02:43:43.79#ibcon#about to read 4, iclass 29, count 0 2006.257.02:43:43.79#ibcon#read 4, iclass 29, count 0 2006.257.02:43:43.79#ibcon#about to read 5, iclass 29, count 0 2006.257.02:43:43.79#ibcon#read 5, iclass 29, count 0 2006.257.02:43:43.79#ibcon#about to read 6, iclass 29, count 0 2006.257.02:43:43.79#ibcon#read 6, iclass 29, count 0 2006.257.02:43:43.79#ibcon#end of sib2, iclass 29, count 0 2006.257.02:43:43.79#ibcon#*after write, iclass 29, count 0 2006.257.02:43:43.79#ibcon#*before return 0, iclass 29, count 0 2006.257.02:43:43.79#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:43:43.79#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:43:43.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:43:43.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:43:43.79$vck44/vblo=1,629.99 2006.257.02:43:43.79#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.02:43:43.79#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.02:43:43.79#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:43.79#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:43.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:43.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:43.79#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:43:43.79#ibcon#first serial, iclass 31, count 0 2006.257.02:43:43.79#ibcon#enter sib2, iclass 31, count 0 2006.257.02:43:43.79#ibcon#flushed, iclass 31, count 0 2006.257.02:43:43.79#ibcon#about to write, iclass 31, count 0 2006.257.02:43:43.79#ibcon#wrote, iclass 31, count 0 2006.257.02:43:43.79#ibcon#about to read 3, iclass 31, count 0 2006.257.02:43:43.81#ibcon#read 3, iclass 31, count 0 2006.257.02:43:43.81#ibcon#about to read 4, iclass 31, count 0 2006.257.02:43:43.81#ibcon#read 4, iclass 31, count 0 2006.257.02:43:43.81#ibcon#about to read 5, iclass 31, count 0 2006.257.02:43:43.81#ibcon#read 5, iclass 31, count 0 2006.257.02:43:43.81#ibcon#about to read 6, iclass 31, count 0 2006.257.02:43:43.81#ibcon#read 6, iclass 31, count 0 2006.257.02:43:43.81#ibcon#end of sib2, iclass 31, count 0 2006.257.02:43:43.81#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:43:43.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:43:43.81#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:43:43.81#ibcon#*before write, iclass 31, count 0 2006.257.02:43:43.81#ibcon#enter sib2, iclass 31, count 0 2006.257.02:43:43.81#ibcon#flushed, iclass 31, count 0 2006.257.02:43:43.81#ibcon#about to write, iclass 31, count 0 2006.257.02:43:43.81#ibcon#wrote, iclass 31, count 0 2006.257.02:43:43.81#ibcon#about to read 3, iclass 31, count 0 2006.257.02:43:43.85#ibcon#read 3, iclass 31, count 0 2006.257.02:43:43.85#ibcon#about to read 4, iclass 31, count 0 2006.257.02:43:43.85#ibcon#read 4, iclass 31, count 0 2006.257.02:43:43.85#ibcon#about to read 5, iclass 31, count 0 2006.257.02:43:43.85#ibcon#read 5, iclass 31, count 0 2006.257.02:43:43.85#ibcon#about to read 6, iclass 31, count 0 2006.257.02:43:43.85#ibcon#read 6, iclass 31, count 0 2006.257.02:43:43.85#ibcon#end of sib2, iclass 31, count 0 2006.257.02:43:43.85#ibcon#*after write, iclass 31, count 0 2006.257.02:43:43.85#ibcon#*before return 0, iclass 31, count 0 2006.257.02:43:43.85#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:43.85#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:43:43.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:43:43.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:43:43.85$vck44/vb=1,4 2006.257.02:43:43.85#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.02:43:43.85#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.02:43:43.85#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:43.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:43.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:43.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:43.85#ibcon#enter wrdev, iclass 33, count 2 2006.257.02:43:43.85#ibcon#first serial, iclass 33, count 2 2006.257.02:43:43.85#ibcon#enter sib2, iclass 33, count 2 2006.257.02:43:43.85#ibcon#flushed, iclass 33, count 2 2006.257.02:43:43.85#ibcon#about to write, iclass 33, count 2 2006.257.02:43:43.85#ibcon#wrote, iclass 33, count 2 2006.257.02:43:43.85#ibcon#about to read 3, iclass 33, count 2 2006.257.02:43:43.87#ibcon#read 3, iclass 33, count 2 2006.257.02:43:43.87#ibcon#about to read 4, iclass 33, count 2 2006.257.02:43:43.87#ibcon#read 4, iclass 33, count 2 2006.257.02:43:43.87#ibcon#about to read 5, iclass 33, count 2 2006.257.02:43:43.87#ibcon#read 5, iclass 33, count 2 2006.257.02:43:43.87#ibcon#about to read 6, iclass 33, count 2 2006.257.02:43:43.87#ibcon#read 6, iclass 33, count 2 2006.257.02:43:43.87#ibcon#end of sib2, iclass 33, count 2 2006.257.02:43:43.87#ibcon#*mode == 0, iclass 33, count 2 2006.257.02:43:43.87#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.02:43:43.87#ibcon#[27=AT01-04\r\n] 2006.257.02:43:43.87#ibcon#*before write, iclass 33, count 2 2006.257.02:43:43.87#ibcon#enter sib2, iclass 33, count 2 2006.257.02:43:43.87#ibcon#flushed, iclass 33, count 2 2006.257.02:43:43.87#ibcon#about to write, iclass 33, count 2 2006.257.02:43:43.87#ibcon#wrote, iclass 33, count 2 2006.257.02:43:43.87#ibcon#about to read 3, iclass 33, count 2 2006.257.02:43:43.90#ibcon#read 3, iclass 33, count 2 2006.257.02:43:43.90#ibcon#about to read 4, iclass 33, count 2 2006.257.02:43:43.90#ibcon#read 4, iclass 33, count 2 2006.257.02:43:43.90#ibcon#about to read 5, iclass 33, count 2 2006.257.02:43:43.90#ibcon#read 5, iclass 33, count 2 2006.257.02:43:43.90#ibcon#about to read 6, iclass 33, count 2 2006.257.02:43:43.90#ibcon#read 6, iclass 33, count 2 2006.257.02:43:43.90#ibcon#end of sib2, iclass 33, count 2 2006.257.02:43:43.90#ibcon#*after write, iclass 33, count 2 2006.257.02:43:43.90#ibcon#*before return 0, iclass 33, count 2 2006.257.02:43:43.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:43.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:43:43.90#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.02:43:43.90#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:43.90#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:44.02#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:44.02#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:44.02#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:43:44.02#ibcon#first serial, iclass 33, count 0 2006.257.02:43:44.02#ibcon#enter sib2, iclass 33, count 0 2006.257.02:43:44.02#ibcon#flushed, iclass 33, count 0 2006.257.02:43:44.02#ibcon#about to write, iclass 33, count 0 2006.257.02:43:44.02#ibcon#wrote, iclass 33, count 0 2006.257.02:43:44.02#ibcon#about to read 3, iclass 33, count 0 2006.257.02:43:44.04#ibcon#read 3, iclass 33, count 0 2006.257.02:43:44.04#ibcon#about to read 4, iclass 33, count 0 2006.257.02:43:44.04#ibcon#read 4, iclass 33, count 0 2006.257.02:43:44.04#ibcon#about to read 5, iclass 33, count 0 2006.257.02:43:44.04#ibcon#read 5, iclass 33, count 0 2006.257.02:43:44.04#ibcon#about to read 6, iclass 33, count 0 2006.257.02:43:44.04#ibcon#read 6, iclass 33, count 0 2006.257.02:43:44.04#ibcon#end of sib2, iclass 33, count 0 2006.257.02:43:44.04#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:43:44.04#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:43:44.04#ibcon#[27=USB\r\n] 2006.257.02:43:44.04#ibcon#*before write, iclass 33, count 0 2006.257.02:43:44.04#ibcon#enter sib2, iclass 33, count 0 2006.257.02:43:44.04#ibcon#flushed, iclass 33, count 0 2006.257.02:43:44.04#ibcon#about to write, iclass 33, count 0 2006.257.02:43:44.04#ibcon#wrote, iclass 33, count 0 2006.257.02:43:44.04#ibcon#about to read 3, iclass 33, count 0 2006.257.02:43:44.07#ibcon#read 3, iclass 33, count 0 2006.257.02:43:44.07#ibcon#about to read 4, iclass 33, count 0 2006.257.02:43:44.07#ibcon#read 4, iclass 33, count 0 2006.257.02:43:44.07#ibcon#about to read 5, iclass 33, count 0 2006.257.02:43:44.07#ibcon#read 5, iclass 33, count 0 2006.257.02:43:44.07#ibcon#about to read 6, iclass 33, count 0 2006.257.02:43:44.07#ibcon#read 6, iclass 33, count 0 2006.257.02:43:44.07#ibcon#end of sib2, iclass 33, count 0 2006.257.02:43:44.07#ibcon#*after write, iclass 33, count 0 2006.257.02:43:44.07#ibcon#*before return 0, iclass 33, count 0 2006.257.02:43:44.07#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:44.07#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:43:44.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:43:44.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:43:44.07$vck44/vblo=2,634.99 2006.257.02:43:44.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.02:43:44.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.02:43:44.07#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:44.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:44.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:44.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:44.07#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:43:44.07#ibcon#first serial, iclass 35, count 0 2006.257.02:43:44.07#ibcon#enter sib2, iclass 35, count 0 2006.257.02:43:44.07#ibcon#flushed, iclass 35, count 0 2006.257.02:43:44.07#ibcon#about to write, iclass 35, count 0 2006.257.02:43:44.07#ibcon#wrote, iclass 35, count 0 2006.257.02:43:44.07#ibcon#about to read 3, iclass 35, count 0 2006.257.02:43:44.09#ibcon#read 3, iclass 35, count 0 2006.257.02:43:44.09#ibcon#about to read 4, iclass 35, count 0 2006.257.02:43:44.09#ibcon#read 4, iclass 35, count 0 2006.257.02:43:44.09#ibcon#about to read 5, iclass 35, count 0 2006.257.02:43:44.09#ibcon#read 5, iclass 35, count 0 2006.257.02:43:44.09#ibcon#about to read 6, iclass 35, count 0 2006.257.02:43:44.09#ibcon#read 6, iclass 35, count 0 2006.257.02:43:44.09#ibcon#end of sib2, iclass 35, count 0 2006.257.02:43:44.09#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:43:44.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:43:44.09#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:43:44.09#ibcon#*before write, iclass 35, count 0 2006.257.02:43:44.09#ibcon#enter sib2, iclass 35, count 0 2006.257.02:43:44.09#ibcon#flushed, iclass 35, count 0 2006.257.02:43:44.09#ibcon#about to write, iclass 35, count 0 2006.257.02:43:44.09#ibcon#wrote, iclass 35, count 0 2006.257.02:43:44.09#ibcon#about to read 3, iclass 35, count 0 2006.257.02:43:44.13#ibcon#read 3, iclass 35, count 0 2006.257.02:43:44.13#ibcon#about to read 4, iclass 35, count 0 2006.257.02:43:44.13#ibcon#read 4, iclass 35, count 0 2006.257.02:43:44.13#ibcon#about to read 5, iclass 35, count 0 2006.257.02:43:44.13#ibcon#read 5, iclass 35, count 0 2006.257.02:43:44.13#ibcon#about to read 6, iclass 35, count 0 2006.257.02:43:44.13#ibcon#read 6, iclass 35, count 0 2006.257.02:43:44.13#ibcon#end of sib2, iclass 35, count 0 2006.257.02:43:44.13#ibcon#*after write, iclass 35, count 0 2006.257.02:43:44.13#ibcon#*before return 0, iclass 35, count 0 2006.257.02:43:44.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:44.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:43:44.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:43:44.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:43:44.13$vck44/vb=2,5 2006.257.02:43:44.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.02:43:44.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.02:43:44.13#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:44.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:44.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:44.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:44.19#ibcon#enter wrdev, iclass 37, count 2 2006.257.02:43:44.19#ibcon#first serial, iclass 37, count 2 2006.257.02:43:44.19#ibcon#enter sib2, iclass 37, count 2 2006.257.02:43:44.19#ibcon#flushed, iclass 37, count 2 2006.257.02:43:44.19#ibcon#about to write, iclass 37, count 2 2006.257.02:43:44.19#ibcon#wrote, iclass 37, count 2 2006.257.02:43:44.19#ibcon#about to read 3, iclass 37, count 2 2006.257.02:43:44.21#ibcon#read 3, iclass 37, count 2 2006.257.02:43:44.21#ibcon#about to read 4, iclass 37, count 2 2006.257.02:43:44.21#ibcon#read 4, iclass 37, count 2 2006.257.02:43:44.21#ibcon#about to read 5, iclass 37, count 2 2006.257.02:43:44.21#ibcon#read 5, iclass 37, count 2 2006.257.02:43:44.21#ibcon#about to read 6, iclass 37, count 2 2006.257.02:43:44.21#ibcon#read 6, iclass 37, count 2 2006.257.02:43:44.21#ibcon#end of sib2, iclass 37, count 2 2006.257.02:43:44.21#ibcon#*mode == 0, iclass 37, count 2 2006.257.02:43:44.21#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.02:43:44.21#ibcon#[27=AT02-05\r\n] 2006.257.02:43:44.21#ibcon#*before write, iclass 37, count 2 2006.257.02:43:44.21#ibcon#enter sib2, iclass 37, count 2 2006.257.02:43:44.21#ibcon#flushed, iclass 37, count 2 2006.257.02:43:44.21#ibcon#about to write, iclass 37, count 2 2006.257.02:43:44.21#ibcon#wrote, iclass 37, count 2 2006.257.02:43:44.21#ibcon#about to read 3, iclass 37, count 2 2006.257.02:43:44.24#ibcon#read 3, iclass 37, count 2 2006.257.02:43:44.24#ibcon#about to read 4, iclass 37, count 2 2006.257.02:43:44.24#ibcon#read 4, iclass 37, count 2 2006.257.02:43:44.24#ibcon#about to read 5, iclass 37, count 2 2006.257.02:43:44.24#ibcon#read 5, iclass 37, count 2 2006.257.02:43:44.24#ibcon#about to read 6, iclass 37, count 2 2006.257.02:43:44.24#ibcon#read 6, iclass 37, count 2 2006.257.02:43:44.24#ibcon#end of sib2, iclass 37, count 2 2006.257.02:43:44.24#ibcon#*after write, iclass 37, count 2 2006.257.02:43:44.24#ibcon#*before return 0, iclass 37, count 2 2006.257.02:43:44.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:44.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:43:44.24#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.02:43:44.24#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:44.24#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:44.36#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:44.36#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:44.36#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:43:44.36#ibcon#first serial, iclass 37, count 0 2006.257.02:43:44.36#ibcon#enter sib2, iclass 37, count 0 2006.257.02:43:44.36#ibcon#flushed, iclass 37, count 0 2006.257.02:43:44.36#ibcon#about to write, iclass 37, count 0 2006.257.02:43:44.36#ibcon#wrote, iclass 37, count 0 2006.257.02:43:44.36#ibcon#about to read 3, iclass 37, count 0 2006.257.02:43:44.38#ibcon#read 3, iclass 37, count 0 2006.257.02:43:44.38#ibcon#about to read 4, iclass 37, count 0 2006.257.02:43:44.38#ibcon#read 4, iclass 37, count 0 2006.257.02:43:44.38#ibcon#about to read 5, iclass 37, count 0 2006.257.02:43:44.38#ibcon#read 5, iclass 37, count 0 2006.257.02:43:44.38#ibcon#about to read 6, iclass 37, count 0 2006.257.02:43:44.38#ibcon#read 6, iclass 37, count 0 2006.257.02:43:44.38#ibcon#end of sib2, iclass 37, count 0 2006.257.02:43:44.38#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:43:44.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:43:44.38#ibcon#[27=USB\r\n] 2006.257.02:43:44.38#ibcon#*before write, iclass 37, count 0 2006.257.02:43:44.38#ibcon#enter sib2, iclass 37, count 0 2006.257.02:43:44.38#ibcon#flushed, iclass 37, count 0 2006.257.02:43:44.38#ibcon#about to write, iclass 37, count 0 2006.257.02:43:44.38#ibcon#wrote, iclass 37, count 0 2006.257.02:43:44.38#ibcon#about to read 3, iclass 37, count 0 2006.257.02:43:44.41#ibcon#read 3, iclass 37, count 0 2006.257.02:43:44.41#ibcon#about to read 4, iclass 37, count 0 2006.257.02:43:44.41#ibcon#read 4, iclass 37, count 0 2006.257.02:43:44.41#ibcon#about to read 5, iclass 37, count 0 2006.257.02:43:44.41#ibcon#read 5, iclass 37, count 0 2006.257.02:43:44.41#ibcon#about to read 6, iclass 37, count 0 2006.257.02:43:44.41#ibcon#read 6, iclass 37, count 0 2006.257.02:43:44.41#ibcon#end of sib2, iclass 37, count 0 2006.257.02:43:44.41#ibcon#*after write, iclass 37, count 0 2006.257.02:43:44.41#ibcon#*before return 0, iclass 37, count 0 2006.257.02:43:44.41#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:44.41#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:43:44.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:43:44.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:43:44.41$vck44/vblo=3,649.99 2006.257.02:43:44.41#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.02:43:44.41#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.02:43:44.41#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:44.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:44.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:44.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:44.41#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:43:44.41#ibcon#first serial, iclass 39, count 0 2006.257.02:43:44.41#ibcon#enter sib2, iclass 39, count 0 2006.257.02:43:44.41#ibcon#flushed, iclass 39, count 0 2006.257.02:43:44.41#ibcon#about to write, iclass 39, count 0 2006.257.02:43:44.41#ibcon#wrote, iclass 39, count 0 2006.257.02:43:44.41#ibcon#about to read 3, iclass 39, count 0 2006.257.02:43:44.43#ibcon#read 3, iclass 39, count 0 2006.257.02:43:44.43#ibcon#about to read 4, iclass 39, count 0 2006.257.02:43:44.43#ibcon#read 4, iclass 39, count 0 2006.257.02:43:44.43#ibcon#about to read 5, iclass 39, count 0 2006.257.02:43:44.43#ibcon#read 5, iclass 39, count 0 2006.257.02:43:44.43#ibcon#about to read 6, iclass 39, count 0 2006.257.02:43:44.43#ibcon#read 6, iclass 39, count 0 2006.257.02:43:44.43#ibcon#end of sib2, iclass 39, count 0 2006.257.02:43:44.43#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:43:44.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:43:44.43#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:43:44.43#ibcon#*before write, iclass 39, count 0 2006.257.02:43:44.43#ibcon#enter sib2, iclass 39, count 0 2006.257.02:43:44.43#ibcon#flushed, iclass 39, count 0 2006.257.02:43:44.43#ibcon#about to write, iclass 39, count 0 2006.257.02:43:44.43#ibcon#wrote, iclass 39, count 0 2006.257.02:43:44.43#ibcon#about to read 3, iclass 39, count 0 2006.257.02:43:44.47#ibcon#read 3, iclass 39, count 0 2006.257.02:43:44.47#ibcon#about to read 4, iclass 39, count 0 2006.257.02:43:44.47#ibcon#read 4, iclass 39, count 0 2006.257.02:43:44.47#ibcon#about to read 5, iclass 39, count 0 2006.257.02:43:44.47#ibcon#read 5, iclass 39, count 0 2006.257.02:43:44.47#ibcon#about to read 6, iclass 39, count 0 2006.257.02:43:44.47#ibcon#read 6, iclass 39, count 0 2006.257.02:43:44.47#ibcon#end of sib2, iclass 39, count 0 2006.257.02:43:44.47#ibcon#*after write, iclass 39, count 0 2006.257.02:43:44.47#ibcon#*before return 0, iclass 39, count 0 2006.257.02:43:44.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:44.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:43:44.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:43:44.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:43:44.47$vck44/vb=3,4 2006.257.02:43:44.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.02:43:44.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.02:43:44.47#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:44.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:44.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:44.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:44.53#ibcon#enter wrdev, iclass 3, count 2 2006.257.02:43:44.53#ibcon#first serial, iclass 3, count 2 2006.257.02:43:44.53#ibcon#enter sib2, iclass 3, count 2 2006.257.02:43:44.53#ibcon#flushed, iclass 3, count 2 2006.257.02:43:44.53#ibcon#about to write, iclass 3, count 2 2006.257.02:43:44.53#ibcon#wrote, iclass 3, count 2 2006.257.02:43:44.53#ibcon#about to read 3, iclass 3, count 2 2006.257.02:43:44.55#ibcon#read 3, iclass 3, count 2 2006.257.02:43:44.55#ibcon#about to read 4, iclass 3, count 2 2006.257.02:43:44.55#ibcon#read 4, iclass 3, count 2 2006.257.02:43:44.55#ibcon#about to read 5, iclass 3, count 2 2006.257.02:43:44.55#ibcon#read 5, iclass 3, count 2 2006.257.02:43:44.55#ibcon#about to read 6, iclass 3, count 2 2006.257.02:43:44.55#ibcon#read 6, iclass 3, count 2 2006.257.02:43:44.55#ibcon#end of sib2, iclass 3, count 2 2006.257.02:43:44.55#ibcon#*mode == 0, iclass 3, count 2 2006.257.02:43:44.55#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.02:43:44.55#ibcon#[27=AT03-04\r\n] 2006.257.02:43:44.55#ibcon#*before write, iclass 3, count 2 2006.257.02:43:44.55#ibcon#enter sib2, iclass 3, count 2 2006.257.02:43:44.55#ibcon#flushed, iclass 3, count 2 2006.257.02:43:44.55#ibcon#about to write, iclass 3, count 2 2006.257.02:43:44.55#ibcon#wrote, iclass 3, count 2 2006.257.02:43:44.55#ibcon#about to read 3, iclass 3, count 2 2006.257.02:43:44.58#ibcon#read 3, iclass 3, count 2 2006.257.02:43:44.58#ibcon#about to read 4, iclass 3, count 2 2006.257.02:43:44.58#ibcon#read 4, iclass 3, count 2 2006.257.02:43:44.58#ibcon#about to read 5, iclass 3, count 2 2006.257.02:43:44.58#ibcon#read 5, iclass 3, count 2 2006.257.02:43:44.58#ibcon#about to read 6, iclass 3, count 2 2006.257.02:43:44.58#ibcon#read 6, iclass 3, count 2 2006.257.02:43:44.58#ibcon#end of sib2, iclass 3, count 2 2006.257.02:43:44.58#ibcon#*after write, iclass 3, count 2 2006.257.02:43:44.58#ibcon#*before return 0, iclass 3, count 2 2006.257.02:43:44.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:44.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:43:44.58#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.02:43:44.58#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:44.58#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:44.70#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:44.70#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:44.70#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:43:44.70#ibcon#first serial, iclass 3, count 0 2006.257.02:43:44.70#ibcon#enter sib2, iclass 3, count 0 2006.257.02:43:44.70#ibcon#flushed, iclass 3, count 0 2006.257.02:43:44.70#ibcon#about to write, iclass 3, count 0 2006.257.02:43:44.70#ibcon#wrote, iclass 3, count 0 2006.257.02:43:44.70#ibcon#about to read 3, iclass 3, count 0 2006.257.02:43:44.72#ibcon#read 3, iclass 3, count 0 2006.257.02:43:44.72#ibcon#about to read 4, iclass 3, count 0 2006.257.02:43:44.72#ibcon#read 4, iclass 3, count 0 2006.257.02:43:44.72#ibcon#about to read 5, iclass 3, count 0 2006.257.02:43:44.72#ibcon#read 5, iclass 3, count 0 2006.257.02:43:44.72#ibcon#about to read 6, iclass 3, count 0 2006.257.02:43:44.72#ibcon#read 6, iclass 3, count 0 2006.257.02:43:44.72#ibcon#end of sib2, iclass 3, count 0 2006.257.02:43:44.72#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:43:44.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:43:44.72#ibcon#[27=USB\r\n] 2006.257.02:43:44.72#ibcon#*before write, iclass 3, count 0 2006.257.02:43:44.72#ibcon#enter sib2, iclass 3, count 0 2006.257.02:43:44.72#ibcon#flushed, iclass 3, count 0 2006.257.02:43:44.72#ibcon#about to write, iclass 3, count 0 2006.257.02:43:44.72#ibcon#wrote, iclass 3, count 0 2006.257.02:43:44.72#ibcon#about to read 3, iclass 3, count 0 2006.257.02:43:44.75#ibcon#read 3, iclass 3, count 0 2006.257.02:43:44.75#ibcon#about to read 4, iclass 3, count 0 2006.257.02:43:44.75#ibcon#read 4, iclass 3, count 0 2006.257.02:43:44.75#ibcon#about to read 5, iclass 3, count 0 2006.257.02:43:44.75#ibcon#read 5, iclass 3, count 0 2006.257.02:43:44.75#ibcon#about to read 6, iclass 3, count 0 2006.257.02:43:44.75#ibcon#read 6, iclass 3, count 0 2006.257.02:43:44.75#ibcon#end of sib2, iclass 3, count 0 2006.257.02:43:44.75#ibcon#*after write, iclass 3, count 0 2006.257.02:43:44.75#ibcon#*before return 0, iclass 3, count 0 2006.257.02:43:44.75#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:44.75#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:43:44.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:43:44.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:43:44.75$vck44/vblo=4,679.99 2006.257.02:43:44.75#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.02:43:44.75#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.02:43:44.75#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:44.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:44.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:44.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:44.75#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:43:44.75#ibcon#first serial, iclass 5, count 0 2006.257.02:43:44.75#ibcon#enter sib2, iclass 5, count 0 2006.257.02:43:44.75#ibcon#flushed, iclass 5, count 0 2006.257.02:43:44.75#ibcon#about to write, iclass 5, count 0 2006.257.02:43:44.75#ibcon#wrote, iclass 5, count 0 2006.257.02:43:44.75#ibcon#about to read 3, iclass 5, count 0 2006.257.02:43:44.77#ibcon#read 3, iclass 5, count 0 2006.257.02:43:44.77#ibcon#about to read 4, iclass 5, count 0 2006.257.02:43:44.77#ibcon#read 4, iclass 5, count 0 2006.257.02:43:44.77#ibcon#about to read 5, iclass 5, count 0 2006.257.02:43:44.77#ibcon#read 5, iclass 5, count 0 2006.257.02:43:44.77#ibcon#about to read 6, iclass 5, count 0 2006.257.02:43:44.77#ibcon#read 6, iclass 5, count 0 2006.257.02:43:44.77#ibcon#end of sib2, iclass 5, count 0 2006.257.02:43:44.77#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:43:44.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:43:44.77#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:43:44.77#ibcon#*before write, iclass 5, count 0 2006.257.02:43:44.77#ibcon#enter sib2, iclass 5, count 0 2006.257.02:43:44.77#ibcon#flushed, iclass 5, count 0 2006.257.02:43:44.77#ibcon#about to write, iclass 5, count 0 2006.257.02:43:44.77#ibcon#wrote, iclass 5, count 0 2006.257.02:43:44.77#ibcon#about to read 3, iclass 5, count 0 2006.257.02:43:44.81#ibcon#read 3, iclass 5, count 0 2006.257.02:43:44.81#ibcon#about to read 4, iclass 5, count 0 2006.257.02:43:44.81#ibcon#read 4, iclass 5, count 0 2006.257.02:43:44.81#ibcon#about to read 5, iclass 5, count 0 2006.257.02:43:44.81#ibcon#read 5, iclass 5, count 0 2006.257.02:43:44.81#ibcon#about to read 6, iclass 5, count 0 2006.257.02:43:44.81#ibcon#read 6, iclass 5, count 0 2006.257.02:43:44.81#ibcon#end of sib2, iclass 5, count 0 2006.257.02:43:44.81#ibcon#*after write, iclass 5, count 0 2006.257.02:43:44.81#ibcon#*before return 0, iclass 5, count 0 2006.257.02:43:44.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:44.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:43:44.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:43:44.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:43:44.81$vck44/vb=4,5 2006.257.02:43:44.81#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.02:43:44.81#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.02:43:44.81#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:44.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:44.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:44.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:44.87#ibcon#enter wrdev, iclass 7, count 2 2006.257.02:43:44.87#ibcon#first serial, iclass 7, count 2 2006.257.02:43:44.87#ibcon#enter sib2, iclass 7, count 2 2006.257.02:43:44.87#ibcon#flushed, iclass 7, count 2 2006.257.02:43:44.87#ibcon#about to write, iclass 7, count 2 2006.257.02:43:44.87#ibcon#wrote, iclass 7, count 2 2006.257.02:43:44.87#ibcon#about to read 3, iclass 7, count 2 2006.257.02:43:44.89#ibcon#read 3, iclass 7, count 2 2006.257.02:43:44.89#ibcon#about to read 4, iclass 7, count 2 2006.257.02:43:44.89#ibcon#read 4, iclass 7, count 2 2006.257.02:43:44.89#ibcon#about to read 5, iclass 7, count 2 2006.257.02:43:44.89#ibcon#read 5, iclass 7, count 2 2006.257.02:43:44.89#ibcon#about to read 6, iclass 7, count 2 2006.257.02:43:44.89#ibcon#read 6, iclass 7, count 2 2006.257.02:43:44.89#ibcon#end of sib2, iclass 7, count 2 2006.257.02:43:44.89#ibcon#*mode == 0, iclass 7, count 2 2006.257.02:43:44.89#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.02:43:44.89#ibcon#[27=AT04-05\r\n] 2006.257.02:43:44.89#ibcon#*before write, iclass 7, count 2 2006.257.02:43:44.89#ibcon#enter sib2, iclass 7, count 2 2006.257.02:43:44.89#ibcon#flushed, iclass 7, count 2 2006.257.02:43:44.89#ibcon#about to write, iclass 7, count 2 2006.257.02:43:44.89#ibcon#wrote, iclass 7, count 2 2006.257.02:43:44.89#ibcon#about to read 3, iclass 7, count 2 2006.257.02:43:44.92#ibcon#read 3, iclass 7, count 2 2006.257.02:43:44.92#ibcon#about to read 4, iclass 7, count 2 2006.257.02:43:44.92#ibcon#read 4, iclass 7, count 2 2006.257.02:43:44.92#ibcon#about to read 5, iclass 7, count 2 2006.257.02:43:44.92#ibcon#read 5, iclass 7, count 2 2006.257.02:43:44.92#ibcon#about to read 6, iclass 7, count 2 2006.257.02:43:44.92#ibcon#read 6, iclass 7, count 2 2006.257.02:43:44.92#ibcon#end of sib2, iclass 7, count 2 2006.257.02:43:44.92#ibcon#*after write, iclass 7, count 2 2006.257.02:43:44.92#ibcon#*before return 0, iclass 7, count 2 2006.257.02:43:44.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:44.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:43:44.92#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.02:43:44.92#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:44.92#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:45.04#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:45.04#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:45.04#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:43:45.04#ibcon#first serial, iclass 7, count 0 2006.257.02:43:45.04#ibcon#enter sib2, iclass 7, count 0 2006.257.02:43:45.04#ibcon#flushed, iclass 7, count 0 2006.257.02:43:45.04#ibcon#about to write, iclass 7, count 0 2006.257.02:43:45.04#ibcon#wrote, iclass 7, count 0 2006.257.02:43:45.04#ibcon#about to read 3, iclass 7, count 0 2006.257.02:43:45.06#ibcon#read 3, iclass 7, count 0 2006.257.02:43:45.06#ibcon#about to read 4, iclass 7, count 0 2006.257.02:43:45.06#ibcon#read 4, iclass 7, count 0 2006.257.02:43:45.06#ibcon#about to read 5, iclass 7, count 0 2006.257.02:43:45.06#ibcon#read 5, iclass 7, count 0 2006.257.02:43:45.06#ibcon#about to read 6, iclass 7, count 0 2006.257.02:43:45.06#ibcon#read 6, iclass 7, count 0 2006.257.02:43:45.06#ibcon#end of sib2, iclass 7, count 0 2006.257.02:43:45.06#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:43:45.06#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:43:45.06#ibcon#[27=USB\r\n] 2006.257.02:43:45.06#ibcon#*before write, iclass 7, count 0 2006.257.02:43:45.06#ibcon#enter sib2, iclass 7, count 0 2006.257.02:43:45.06#ibcon#flushed, iclass 7, count 0 2006.257.02:43:45.06#ibcon#about to write, iclass 7, count 0 2006.257.02:43:45.06#ibcon#wrote, iclass 7, count 0 2006.257.02:43:45.06#ibcon#about to read 3, iclass 7, count 0 2006.257.02:43:45.09#ibcon#read 3, iclass 7, count 0 2006.257.02:43:45.09#ibcon#about to read 4, iclass 7, count 0 2006.257.02:43:45.09#ibcon#read 4, iclass 7, count 0 2006.257.02:43:45.09#ibcon#about to read 5, iclass 7, count 0 2006.257.02:43:45.09#ibcon#read 5, iclass 7, count 0 2006.257.02:43:45.09#ibcon#about to read 6, iclass 7, count 0 2006.257.02:43:45.09#ibcon#read 6, iclass 7, count 0 2006.257.02:43:45.09#ibcon#end of sib2, iclass 7, count 0 2006.257.02:43:45.09#ibcon#*after write, iclass 7, count 0 2006.257.02:43:45.09#ibcon#*before return 0, iclass 7, count 0 2006.257.02:43:45.09#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:45.09#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:43:45.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:43:45.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:43:45.09$vck44/vblo=5,709.99 2006.257.02:43:45.09#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.02:43:45.09#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.02:43:45.09#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:45.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:45.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:45.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:45.09#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:43:45.09#ibcon#first serial, iclass 11, count 0 2006.257.02:43:45.09#ibcon#enter sib2, iclass 11, count 0 2006.257.02:43:45.09#ibcon#flushed, iclass 11, count 0 2006.257.02:43:45.09#ibcon#about to write, iclass 11, count 0 2006.257.02:43:45.09#ibcon#wrote, iclass 11, count 0 2006.257.02:43:45.09#ibcon#about to read 3, iclass 11, count 0 2006.257.02:43:45.11#ibcon#read 3, iclass 11, count 0 2006.257.02:43:45.11#ibcon#about to read 4, iclass 11, count 0 2006.257.02:43:45.11#ibcon#read 4, iclass 11, count 0 2006.257.02:43:45.11#ibcon#about to read 5, iclass 11, count 0 2006.257.02:43:45.11#ibcon#read 5, iclass 11, count 0 2006.257.02:43:45.11#ibcon#about to read 6, iclass 11, count 0 2006.257.02:43:45.11#ibcon#read 6, iclass 11, count 0 2006.257.02:43:45.11#ibcon#end of sib2, iclass 11, count 0 2006.257.02:43:45.11#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:43:45.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:43:45.11#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:43:45.11#ibcon#*before write, iclass 11, count 0 2006.257.02:43:45.11#ibcon#enter sib2, iclass 11, count 0 2006.257.02:43:45.11#ibcon#flushed, iclass 11, count 0 2006.257.02:43:45.11#ibcon#about to write, iclass 11, count 0 2006.257.02:43:45.11#ibcon#wrote, iclass 11, count 0 2006.257.02:43:45.11#ibcon#about to read 3, iclass 11, count 0 2006.257.02:43:45.15#ibcon#read 3, iclass 11, count 0 2006.257.02:43:45.15#ibcon#about to read 4, iclass 11, count 0 2006.257.02:43:45.15#ibcon#read 4, iclass 11, count 0 2006.257.02:43:45.15#ibcon#about to read 5, iclass 11, count 0 2006.257.02:43:45.15#ibcon#read 5, iclass 11, count 0 2006.257.02:43:45.15#ibcon#about to read 6, iclass 11, count 0 2006.257.02:43:45.15#ibcon#read 6, iclass 11, count 0 2006.257.02:43:45.15#ibcon#end of sib2, iclass 11, count 0 2006.257.02:43:45.15#ibcon#*after write, iclass 11, count 0 2006.257.02:43:45.15#ibcon#*before return 0, iclass 11, count 0 2006.257.02:43:45.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:45.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:43:45.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:43:45.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:43:45.15$vck44/vb=5,4 2006.257.02:43:45.15#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.02:43:45.15#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.02:43:45.15#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:45.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:45.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:45.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:45.21#ibcon#enter wrdev, iclass 13, count 2 2006.257.02:43:45.21#ibcon#first serial, iclass 13, count 2 2006.257.02:43:45.21#ibcon#enter sib2, iclass 13, count 2 2006.257.02:43:45.21#ibcon#flushed, iclass 13, count 2 2006.257.02:43:45.21#ibcon#about to write, iclass 13, count 2 2006.257.02:43:45.21#ibcon#wrote, iclass 13, count 2 2006.257.02:43:45.21#ibcon#about to read 3, iclass 13, count 2 2006.257.02:43:45.23#ibcon#read 3, iclass 13, count 2 2006.257.02:43:45.23#ibcon#about to read 4, iclass 13, count 2 2006.257.02:43:45.23#ibcon#read 4, iclass 13, count 2 2006.257.02:43:45.23#ibcon#about to read 5, iclass 13, count 2 2006.257.02:43:45.23#ibcon#read 5, iclass 13, count 2 2006.257.02:43:45.23#ibcon#about to read 6, iclass 13, count 2 2006.257.02:43:45.23#ibcon#read 6, iclass 13, count 2 2006.257.02:43:45.23#ibcon#end of sib2, iclass 13, count 2 2006.257.02:43:45.23#ibcon#*mode == 0, iclass 13, count 2 2006.257.02:43:45.23#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.02:43:45.23#ibcon#[27=AT05-04\r\n] 2006.257.02:43:45.23#ibcon#*before write, iclass 13, count 2 2006.257.02:43:45.23#ibcon#enter sib2, iclass 13, count 2 2006.257.02:43:45.23#ibcon#flushed, iclass 13, count 2 2006.257.02:43:45.23#ibcon#about to write, iclass 13, count 2 2006.257.02:43:45.23#ibcon#wrote, iclass 13, count 2 2006.257.02:43:45.23#ibcon#about to read 3, iclass 13, count 2 2006.257.02:43:45.26#ibcon#read 3, iclass 13, count 2 2006.257.02:43:45.26#ibcon#about to read 4, iclass 13, count 2 2006.257.02:43:45.26#ibcon#read 4, iclass 13, count 2 2006.257.02:43:45.26#ibcon#about to read 5, iclass 13, count 2 2006.257.02:43:45.26#ibcon#read 5, iclass 13, count 2 2006.257.02:43:45.26#ibcon#about to read 6, iclass 13, count 2 2006.257.02:43:45.26#ibcon#read 6, iclass 13, count 2 2006.257.02:43:45.26#ibcon#end of sib2, iclass 13, count 2 2006.257.02:43:45.26#ibcon#*after write, iclass 13, count 2 2006.257.02:43:45.26#ibcon#*before return 0, iclass 13, count 2 2006.257.02:43:45.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:45.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:43:45.26#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.02:43:45.26#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:45.26#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:45.38#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:45.38#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:45.38#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:43:45.38#ibcon#first serial, iclass 13, count 0 2006.257.02:43:45.38#ibcon#enter sib2, iclass 13, count 0 2006.257.02:43:45.38#ibcon#flushed, iclass 13, count 0 2006.257.02:43:45.38#ibcon#about to write, iclass 13, count 0 2006.257.02:43:45.38#ibcon#wrote, iclass 13, count 0 2006.257.02:43:45.38#ibcon#about to read 3, iclass 13, count 0 2006.257.02:43:45.40#ibcon#read 3, iclass 13, count 0 2006.257.02:43:45.40#ibcon#about to read 4, iclass 13, count 0 2006.257.02:43:45.40#ibcon#read 4, iclass 13, count 0 2006.257.02:43:45.40#ibcon#about to read 5, iclass 13, count 0 2006.257.02:43:45.40#ibcon#read 5, iclass 13, count 0 2006.257.02:43:45.40#ibcon#about to read 6, iclass 13, count 0 2006.257.02:43:45.40#ibcon#read 6, iclass 13, count 0 2006.257.02:43:45.40#ibcon#end of sib2, iclass 13, count 0 2006.257.02:43:45.40#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:43:45.40#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:43:45.40#ibcon#[27=USB\r\n] 2006.257.02:43:45.40#ibcon#*before write, iclass 13, count 0 2006.257.02:43:45.40#ibcon#enter sib2, iclass 13, count 0 2006.257.02:43:45.40#ibcon#flushed, iclass 13, count 0 2006.257.02:43:45.40#ibcon#about to write, iclass 13, count 0 2006.257.02:43:45.40#ibcon#wrote, iclass 13, count 0 2006.257.02:43:45.40#ibcon#about to read 3, iclass 13, count 0 2006.257.02:43:45.43#ibcon#read 3, iclass 13, count 0 2006.257.02:43:45.43#ibcon#about to read 4, iclass 13, count 0 2006.257.02:43:45.43#ibcon#read 4, iclass 13, count 0 2006.257.02:43:45.43#ibcon#about to read 5, iclass 13, count 0 2006.257.02:43:45.43#ibcon#read 5, iclass 13, count 0 2006.257.02:43:45.43#ibcon#about to read 6, iclass 13, count 0 2006.257.02:43:45.43#ibcon#read 6, iclass 13, count 0 2006.257.02:43:45.43#ibcon#end of sib2, iclass 13, count 0 2006.257.02:43:45.43#ibcon#*after write, iclass 13, count 0 2006.257.02:43:45.43#ibcon#*before return 0, iclass 13, count 0 2006.257.02:43:45.43#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:45.43#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:43:45.43#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:43:45.43#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:43:45.43$vck44/vblo=6,719.99 2006.257.02:43:45.43#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.02:43:45.43#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.02:43:45.43#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:45.43#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:45.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:45.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:45.43#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:43:45.43#ibcon#first serial, iclass 15, count 0 2006.257.02:43:45.43#ibcon#enter sib2, iclass 15, count 0 2006.257.02:43:45.43#ibcon#flushed, iclass 15, count 0 2006.257.02:43:45.43#ibcon#about to write, iclass 15, count 0 2006.257.02:43:45.43#ibcon#wrote, iclass 15, count 0 2006.257.02:43:45.43#ibcon#about to read 3, iclass 15, count 0 2006.257.02:43:45.45#ibcon#read 3, iclass 15, count 0 2006.257.02:43:45.45#ibcon#about to read 4, iclass 15, count 0 2006.257.02:43:45.45#ibcon#read 4, iclass 15, count 0 2006.257.02:43:45.45#ibcon#about to read 5, iclass 15, count 0 2006.257.02:43:45.45#ibcon#read 5, iclass 15, count 0 2006.257.02:43:45.45#ibcon#about to read 6, iclass 15, count 0 2006.257.02:43:45.45#ibcon#read 6, iclass 15, count 0 2006.257.02:43:45.45#ibcon#end of sib2, iclass 15, count 0 2006.257.02:43:45.45#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:43:45.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:43:45.45#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:43:45.45#ibcon#*before write, iclass 15, count 0 2006.257.02:43:45.45#ibcon#enter sib2, iclass 15, count 0 2006.257.02:43:45.45#ibcon#flushed, iclass 15, count 0 2006.257.02:43:45.45#ibcon#about to write, iclass 15, count 0 2006.257.02:43:45.45#ibcon#wrote, iclass 15, count 0 2006.257.02:43:45.45#ibcon#about to read 3, iclass 15, count 0 2006.257.02:43:45.49#ibcon#read 3, iclass 15, count 0 2006.257.02:43:45.49#ibcon#about to read 4, iclass 15, count 0 2006.257.02:43:45.49#ibcon#read 4, iclass 15, count 0 2006.257.02:43:45.49#ibcon#about to read 5, iclass 15, count 0 2006.257.02:43:45.49#ibcon#read 5, iclass 15, count 0 2006.257.02:43:45.49#ibcon#about to read 6, iclass 15, count 0 2006.257.02:43:45.49#ibcon#read 6, iclass 15, count 0 2006.257.02:43:45.49#ibcon#end of sib2, iclass 15, count 0 2006.257.02:43:45.49#ibcon#*after write, iclass 15, count 0 2006.257.02:43:45.49#ibcon#*before return 0, iclass 15, count 0 2006.257.02:43:45.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:45.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:43:45.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:43:45.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:43:45.49$vck44/vb=6,4 2006.257.02:43:45.49#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.02:43:45.49#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.02:43:45.49#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:45.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:45.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:45.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:45.55#ibcon#enter wrdev, iclass 17, count 2 2006.257.02:43:45.55#ibcon#first serial, iclass 17, count 2 2006.257.02:43:45.55#ibcon#enter sib2, iclass 17, count 2 2006.257.02:43:45.55#ibcon#flushed, iclass 17, count 2 2006.257.02:43:45.55#ibcon#about to write, iclass 17, count 2 2006.257.02:43:45.55#ibcon#wrote, iclass 17, count 2 2006.257.02:43:45.55#ibcon#about to read 3, iclass 17, count 2 2006.257.02:43:45.57#ibcon#read 3, iclass 17, count 2 2006.257.02:43:45.57#ibcon#about to read 4, iclass 17, count 2 2006.257.02:43:45.57#ibcon#read 4, iclass 17, count 2 2006.257.02:43:45.57#ibcon#about to read 5, iclass 17, count 2 2006.257.02:43:45.57#ibcon#read 5, iclass 17, count 2 2006.257.02:43:45.57#ibcon#about to read 6, iclass 17, count 2 2006.257.02:43:45.57#ibcon#read 6, iclass 17, count 2 2006.257.02:43:45.57#ibcon#end of sib2, iclass 17, count 2 2006.257.02:43:45.57#ibcon#*mode == 0, iclass 17, count 2 2006.257.02:43:45.57#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.02:43:45.57#ibcon#[27=AT06-04\r\n] 2006.257.02:43:45.57#ibcon#*before write, iclass 17, count 2 2006.257.02:43:45.57#ibcon#enter sib2, iclass 17, count 2 2006.257.02:43:45.57#ibcon#flushed, iclass 17, count 2 2006.257.02:43:45.57#ibcon#about to write, iclass 17, count 2 2006.257.02:43:45.57#ibcon#wrote, iclass 17, count 2 2006.257.02:43:45.57#ibcon#about to read 3, iclass 17, count 2 2006.257.02:43:45.60#ibcon#read 3, iclass 17, count 2 2006.257.02:43:45.60#ibcon#about to read 4, iclass 17, count 2 2006.257.02:43:45.60#ibcon#read 4, iclass 17, count 2 2006.257.02:43:45.60#ibcon#about to read 5, iclass 17, count 2 2006.257.02:43:45.60#ibcon#read 5, iclass 17, count 2 2006.257.02:43:45.60#ibcon#about to read 6, iclass 17, count 2 2006.257.02:43:45.60#ibcon#read 6, iclass 17, count 2 2006.257.02:43:45.60#ibcon#end of sib2, iclass 17, count 2 2006.257.02:43:45.60#ibcon#*after write, iclass 17, count 2 2006.257.02:43:45.60#ibcon#*before return 0, iclass 17, count 2 2006.257.02:43:45.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:45.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:43:45.60#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.02:43:45.60#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:45.60#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:45.72#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:45.72#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:45.72#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:43:45.72#ibcon#first serial, iclass 17, count 0 2006.257.02:43:45.72#ibcon#enter sib2, iclass 17, count 0 2006.257.02:43:45.72#ibcon#flushed, iclass 17, count 0 2006.257.02:43:45.72#ibcon#about to write, iclass 17, count 0 2006.257.02:43:45.72#ibcon#wrote, iclass 17, count 0 2006.257.02:43:45.72#ibcon#about to read 3, iclass 17, count 0 2006.257.02:43:45.74#ibcon#read 3, iclass 17, count 0 2006.257.02:43:45.74#ibcon#about to read 4, iclass 17, count 0 2006.257.02:43:45.74#ibcon#read 4, iclass 17, count 0 2006.257.02:43:45.74#ibcon#about to read 5, iclass 17, count 0 2006.257.02:43:45.74#ibcon#read 5, iclass 17, count 0 2006.257.02:43:45.74#ibcon#about to read 6, iclass 17, count 0 2006.257.02:43:45.74#ibcon#read 6, iclass 17, count 0 2006.257.02:43:45.74#ibcon#end of sib2, iclass 17, count 0 2006.257.02:43:45.74#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:43:45.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:43:45.74#ibcon#[27=USB\r\n] 2006.257.02:43:45.74#ibcon#*before write, iclass 17, count 0 2006.257.02:43:45.74#ibcon#enter sib2, iclass 17, count 0 2006.257.02:43:45.74#ibcon#flushed, iclass 17, count 0 2006.257.02:43:45.74#ibcon#about to write, iclass 17, count 0 2006.257.02:43:45.74#ibcon#wrote, iclass 17, count 0 2006.257.02:43:45.74#ibcon#about to read 3, iclass 17, count 0 2006.257.02:43:45.77#ibcon#read 3, iclass 17, count 0 2006.257.02:43:45.77#ibcon#about to read 4, iclass 17, count 0 2006.257.02:43:45.77#ibcon#read 4, iclass 17, count 0 2006.257.02:43:45.77#ibcon#about to read 5, iclass 17, count 0 2006.257.02:43:45.77#ibcon#read 5, iclass 17, count 0 2006.257.02:43:45.77#ibcon#about to read 6, iclass 17, count 0 2006.257.02:43:45.77#ibcon#read 6, iclass 17, count 0 2006.257.02:43:45.77#ibcon#end of sib2, iclass 17, count 0 2006.257.02:43:45.77#ibcon#*after write, iclass 17, count 0 2006.257.02:43:45.77#ibcon#*before return 0, iclass 17, count 0 2006.257.02:43:45.77#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:45.77#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:43:45.77#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:43:45.77#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:43:45.77$vck44/vblo=7,734.99 2006.257.02:43:45.77#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.02:43:45.77#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.02:43:45.77#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:45.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:43:45.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:43:45.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:43:45.77#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:43:45.77#ibcon#first serial, iclass 19, count 0 2006.257.02:43:45.77#ibcon#enter sib2, iclass 19, count 0 2006.257.02:43:45.77#ibcon#flushed, iclass 19, count 0 2006.257.02:43:45.77#ibcon#about to write, iclass 19, count 0 2006.257.02:43:45.77#ibcon#wrote, iclass 19, count 0 2006.257.02:43:45.77#ibcon#about to read 3, iclass 19, count 0 2006.257.02:43:45.79#ibcon#read 3, iclass 19, count 0 2006.257.02:43:45.79#ibcon#about to read 4, iclass 19, count 0 2006.257.02:43:45.79#ibcon#read 4, iclass 19, count 0 2006.257.02:43:45.79#ibcon#about to read 5, iclass 19, count 0 2006.257.02:43:45.79#ibcon#read 5, iclass 19, count 0 2006.257.02:43:45.79#ibcon#about to read 6, iclass 19, count 0 2006.257.02:43:45.79#ibcon#read 6, iclass 19, count 0 2006.257.02:43:45.79#ibcon#end of sib2, iclass 19, count 0 2006.257.02:43:45.79#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:43:45.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:43:45.79#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:43:45.79#ibcon#*before write, iclass 19, count 0 2006.257.02:43:45.79#ibcon#enter sib2, iclass 19, count 0 2006.257.02:43:45.79#ibcon#flushed, iclass 19, count 0 2006.257.02:43:45.79#ibcon#about to write, iclass 19, count 0 2006.257.02:43:45.79#ibcon#wrote, iclass 19, count 0 2006.257.02:43:45.79#ibcon#about to read 3, iclass 19, count 0 2006.257.02:43:45.83#ibcon#read 3, iclass 19, count 0 2006.257.02:43:45.83#ibcon#about to read 4, iclass 19, count 0 2006.257.02:43:45.83#ibcon#read 4, iclass 19, count 0 2006.257.02:43:45.83#ibcon#about to read 5, iclass 19, count 0 2006.257.02:43:45.83#ibcon#read 5, iclass 19, count 0 2006.257.02:43:45.83#ibcon#about to read 6, iclass 19, count 0 2006.257.02:43:45.83#ibcon#read 6, iclass 19, count 0 2006.257.02:43:45.83#ibcon#end of sib2, iclass 19, count 0 2006.257.02:43:45.83#ibcon#*after write, iclass 19, count 0 2006.257.02:43:45.83#ibcon#*before return 0, iclass 19, count 0 2006.257.02:43:45.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:43:45.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:43:45.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:43:45.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:43:45.83$vck44/vb=7,4 2006.257.02:43:45.83#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.02:43:45.83#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.02:43:45.83#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:45.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:43:45.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:43:45.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:43:45.89#ibcon#enter wrdev, iclass 21, count 2 2006.257.02:43:45.89#ibcon#first serial, iclass 21, count 2 2006.257.02:43:45.89#ibcon#enter sib2, iclass 21, count 2 2006.257.02:43:45.89#ibcon#flushed, iclass 21, count 2 2006.257.02:43:45.89#ibcon#about to write, iclass 21, count 2 2006.257.02:43:45.89#ibcon#wrote, iclass 21, count 2 2006.257.02:43:45.89#ibcon#about to read 3, iclass 21, count 2 2006.257.02:43:45.91#ibcon#read 3, iclass 21, count 2 2006.257.02:43:45.91#ibcon#about to read 4, iclass 21, count 2 2006.257.02:43:45.91#ibcon#read 4, iclass 21, count 2 2006.257.02:43:45.91#ibcon#about to read 5, iclass 21, count 2 2006.257.02:43:45.91#ibcon#read 5, iclass 21, count 2 2006.257.02:43:45.91#ibcon#about to read 6, iclass 21, count 2 2006.257.02:43:45.91#ibcon#read 6, iclass 21, count 2 2006.257.02:43:45.91#ibcon#end of sib2, iclass 21, count 2 2006.257.02:43:45.91#ibcon#*mode == 0, iclass 21, count 2 2006.257.02:43:45.91#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.02:43:45.91#ibcon#[27=AT07-04\r\n] 2006.257.02:43:45.91#ibcon#*before write, iclass 21, count 2 2006.257.02:43:45.91#ibcon#enter sib2, iclass 21, count 2 2006.257.02:43:45.91#ibcon#flushed, iclass 21, count 2 2006.257.02:43:45.91#ibcon#about to write, iclass 21, count 2 2006.257.02:43:45.91#ibcon#wrote, iclass 21, count 2 2006.257.02:43:45.91#ibcon#about to read 3, iclass 21, count 2 2006.257.02:43:45.94#ibcon#read 3, iclass 21, count 2 2006.257.02:43:45.94#ibcon#about to read 4, iclass 21, count 2 2006.257.02:43:45.94#ibcon#read 4, iclass 21, count 2 2006.257.02:43:45.94#ibcon#about to read 5, iclass 21, count 2 2006.257.02:43:45.94#ibcon#read 5, iclass 21, count 2 2006.257.02:43:45.94#ibcon#about to read 6, iclass 21, count 2 2006.257.02:43:45.94#ibcon#read 6, iclass 21, count 2 2006.257.02:43:45.94#ibcon#end of sib2, iclass 21, count 2 2006.257.02:43:45.94#ibcon#*after write, iclass 21, count 2 2006.257.02:43:45.94#ibcon#*before return 0, iclass 21, count 2 2006.257.02:43:45.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:43:45.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:43:45.94#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.02:43:45.94#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:45.94#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:43:46.06#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:43:46.06#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:43:46.06#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:43:46.06#ibcon#first serial, iclass 21, count 0 2006.257.02:43:46.06#ibcon#enter sib2, iclass 21, count 0 2006.257.02:43:46.06#ibcon#flushed, iclass 21, count 0 2006.257.02:43:46.06#ibcon#about to write, iclass 21, count 0 2006.257.02:43:46.06#ibcon#wrote, iclass 21, count 0 2006.257.02:43:46.06#ibcon#about to read 3, iclass 21, count 0 2006.257.02:43:46.08#ibcon#read 3, iclass 21, count 0 2006.257.02:43:46.08#ibcon#about to read 4, iclass 21, count 0 2006.257.02:43:46.08#ibcon#read 4, iclass 21, count 0 2006.257.02:43:46.08#ibcon#about to read 5, iclass 21, count 0 2006.257.02:43:46.08#ibcon#read 5, iclass 21, count 0 2006.257.02:43:46.08#ibcon#about to read 6, iclass 21, count 0 2006.257.02:43:46.08#ibcon#read 6, iclass 21, count 0 2006.257.02:43:46.08#ibcon#end of sib2, iclass 21, count 0 2006.257.02:43:46.08#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:43:46.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:43:46.08#ibcon#[27=USB\r\n] 2006.257.02:43:46.08#ibcon#*before write, iclass 21, count 0 2006.257.02:43:46.08#ibcon#enter sib2, iclass 21, count 0 2006.257.02:43:46.08#ibcon#flushed, iclass 21, count 0 2006.257.02:43:46.08#ibcon#about to write, iclass 21, count 0 2006.257.02:43:46.08#ibcon#wrote, iclass 21, count 0 2006.257.02:43:46.08#ibcon#about to read 3, iclass 21, count 0 2006.257.02:43:46.11#ibcon#read 3, iclass 21, count 0 2006.257.02:43:46.11#ibcon#about to read 4, iclass 21, count 0 2006.257.02:43:46.11#ibcon#read 4, iclass 21, count 0 2006.257.02:43:46.11#ibcon#about to read 5, iclass 21, count 0 2006.257.02:43:46.11#ibcon#read 5, iclass 21, count 0 2006.257.02:43:46.11#ibcon#about to read 6, iclass 21, count 0 2006.257.02:43:46.11#ibcon#read 6, iclass 21, count 0 2006.257.02:43:46.11#ibcon#end of sib2, iclass 21, count 0 2006.257.02:43:46.11#ibcon#*after write, iclass 21, count 0 2006.257.02:43:46.11#ibcon#*before return 0, iclass 21, count 0 2006.257.02:43:46.11#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:43:46.11#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:43:46.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:43:46.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:43:46.11$vck44/vblo=8,744.99 2006.257.02:43:46.11#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.02:43:46.11#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.02:43:46.11#ibcon#ireg 17 cls_cnt 0 2006.257.02:43:46.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:43:46.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:43:46.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:43:46.11#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:43:46.11#ibcon#first serial, iclass 23, count 0 2006.257.02:43:46.11#ibcon#enter sib2, iclass 23, count 0 2006.257.02:43:46.11#ibcon#flushed, iclass 23, count 0 2006.257.02:43:46.11#ibcon#about to write, iclass 23, count 0 2006.257.02:43:46.11#ibcon#wrote, iclass 23, count 0 2006.257.02:43:46.11#ibcon#about to read 3, iclass 23, count 0 2006.257.02:43:46.13#ibcon#read 3, iclass 23, count 0 2006.257.02:43:46.13#ibcon#about to read 4, iclass 23, count 0 2006.257.02:43:46.13#ibcon#read 4, iclass 23, count 0 2006.257.02:43:46.13#ibcon#about to read 5, iclass 23, count 0 2006.257.02:43:46.13#ibcon#read 5, iclass 23, count 0 2006.257.02:43:46.13#ibcon#about to read 6, iclass 23, count 0 2006.257.02:43:46.13#ibcon#read 6, iclass 23, count 0 2006.257.02:43:46.13#ibcon#end of sib2, iclass 23, count 0 2006.257.02:43:46.13#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:43:46.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:43:46.13#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:43:46.13#ibcon#*before write, iclass 23, count 0 2006.257.02:43:46.13#ibcon#enter sib2, iclass 23, count 0 2006.257.02:43:46.13#ibcon#flushed, iclass 23, count 0 2006.257.02:43:46.13#ibcon#about to write, iclass 23, count 0 2006.257.02:43:46.13#ibcon#wrote, iclass 23, count 0 2006.257.02:43:46.13#ibcon#about to read 3, iclass 23, count 0 2006.257.02:43:46.17#ibcon#read 3, iclass 23, count 0 2006.257.02:43:46.17#ibcon#about to read 4, iclass 23, count 0 2006.257.02:43:46.17#ibcon#read 4, iclass 23, count 0 2006.257.02:43:46.17#ibcon#about to read 5, iclass 23, count 0 2006.257.02:43:46.17#ibcon#read 5, iclass 23, count 0 2006.257.02:43:46.17#ibcon#about to read 6, iclass 23, count 0 2006.257.02:43:46.17#ibcon#read 6, iclass 23, count 0 2006.257.02:43:46.17#ibcon#end of sib2, iclass 23, count 0 2006.257.02:43:46.17#ibcon#*after write, iclass 23, count 0 2006.257.02:43:46.17#ibcon#*before return 0, iclass 23, count 0 2006.257.02:43:46.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:43:46.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:43:46.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:43:46.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:43:46.17$vck44/vb=8,4 2006.257.02:43:46.17#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.02:43:46.17#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.02:43:46.17#ibcon#ireg 11 cls_cnt 2 2006.257.02:43:46.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:46.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:46.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:46.23#ibcon#enter wrdev, iclass 25, count 2 2006.257.02:43:46.23#ibcon#first serial, iclass 25, count 2 2006.257.02:43:46.23#ibcon#enter sib2, iclass 25, count 2 2006.257.02:43:46.23#ibcon#flushed, iclass 25, count 2 2006.257.02:43:46.23#ibcon#about to write, iclass 25, count 2 2006.257.02:43:46.23#ibcon#wrote, iclass 25, count 2 2006.257.02:43:46.23#ibcon#about to read 3, iclass 25, count 2 2006.257.02:43:46.25#ibcon#read 3, iclass 25, count 2 2006.257.02:43:46.25#ibcon#about to read 4, iclass 25, count 2 2006.257.02:43:46.25#ibcon#read 4, iclass 25, count 2 2006.257.02:43:46.25#ibcon#about to read 5, iclass 25, count 2 2006.257.02:43:46.25#ibcon#read 5, iclass 25, count 2 2006.257.02:43:46.25#ibcon#about to read 6, iclass 25, count 2 2006.257.02:43:46.25#ibcon#read 6, iclass 25, count 2 2006.257.02:43:46.25#ibcon#end of sib2, iclass 25, count 2 2006.257.02:43:46.25#ibcon#*mode == 0, iclass 25, count 2 2006.257.02:43:46.25#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.02:43:46.25#ibcon#[27=AT08-04\r\n] 2006.257.02:43:46.25#ibcon#*before write, iclass 25, count 2 2006.257.02:43:46.25#ibcon#enter sib2, iclass 25, count 2 2006.257.02:43:46.25#ibcon#flushed, iclass 25, count 2 2006.257.02:43:46.25#ibcon#about to write, iclass 25, count 2 2006.257.02:43:46.25#ibcon#wrote, iclass 25, count 2 2006.257.02:43:46.25#ibcon#about to read 3, iclass 25, count 2 2006.257.02:43:46.28#ibcon#read 3, iclass 25, count 2 2006.257.02:43:46.28#ibcon#about to read 4, iclass 25, count 2 2006.257.02:43:46.28#ibcon#read 4, iclass 25, count 2 2006.257.02:43:46.28#ibcon#about to read 5, iclass 25, count 2 2006.257.02:43:46.28#ibcon#read 5, iclass 25, count 2 2006.257.02:43:46.28#ibcon#about to read 6, iclass 25, count 2 2006.257.02:43:46.28#ibcon#read 6, iclass 25, count 2 2006.257.02:43:46.28#ibcon#end of sib2, iclass 25, count 2 2006.257.02:43:46.28#ibcon#*after write, iclass 25, count 2 2006.257.02:43:46.28#ibcon#*before return 0, iclass 25, count 2 2006.257.02:43:46.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:46.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:43:46.28#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.02:43:46.28#ibcon#ireg 7 cls_cnt 0 2006.257.02:43:46.28#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:46.40#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:46.40#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:46.40#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:43:46.40#ibcon#first serial, iclass 25, count 0 2006.257.02:43:46.40#ibcon#enter sib2, iclass 25, count 0 2006.257.02:43:46.40#ibcon#flushed, iclass 25, count 0 2006.257.02:43:46.40#ibcon#about to write, iclass 25, count 0 2006.257.02:43:46.40#ibcon#wrote, iclass 25, count 0 2006.257.02:43:46.40#ibcon#about to read 3, iclass 25, count 0 2006.257.02:43:46.42#ibcon#read 3, iclass 25, count 0 2006.257.02:43:46.42#ibcon#about to read 4, iclass 25, count 0 2006.257.02:43:46.42#ibcon#read 4, iclass 25, count 0 2006.257.02:43:46.42#ibcon#about to read 5, iclass 25, count 0 2006.257.02:43:46.42#ibcon#read 5, iclass 25, count 0 2006.257.02:43:46.42#ibcon#about to read 6, iclass 25, count 0 2006.257.02:43:46.42#ibcon#read 6, iclass 25, count 0 2006.257.02:43:46.42#ibcon#end of sib2, iclass 25, count 0 2006.257.02:43:46.42#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:43:46.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:43:46.42#ibcon#[27=USB\r\n] 2006.257.02:43:46.42#ibcon#*before write, iclass 25, count 0 2006.257.02:43:46.42#ibcon#enter sib2, iclass 25, count 0 2006.257.02:43:46.42#ibcon#flushed, iclass 25, count 0 2006.257.02:43:46.42#ibcon#about to write, iclass 25, count 0 2006.257.02:43:46.42#ibcon#wrote, iclass 25, count 0 2006.257.02:43:46.42#ibcon#about to read 3, iclass 25, count 0 2006.257.02:43:46.45#ibcon#read 3, iclass 25, count 0 2006.257.02:43:46.45#ibcon#about to read 4, iclass 25, count 0 2006.257.02:43:46.45#ibcon#read 4, iclass 25, count 0 2006.257.02:43:46.45#ibcon#about to read 5, iclass 25, count 0 2006.257.02:43:46.45#ibcon#read 5, iclass 25, count 0 2006.257.02:43:46.45#ibcon#about to read 6, iclass 25, count 0 2006.257.02:43:46.45#ibcon#read 6, iclass 25, count 0 2006.257.02:43:46.45#ibcon#end of sib2, iclass 25, count 0 2006.257.02:43:46.45#ibcon#*after write, iclass 25, count 0 2006.257.02:43:46.45#ibcon#*before return 0, iclass 25, count 0 2006.257.02:43:46.45#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:46.45#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:43:46.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:43:46.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:43:46.45$vck44/vabw=wide 2006.257.02:43:46.45#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.02:43:46.45#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.02:43:46.45#ibcon#ireg 8 cls_cnt 0 2006.257.02:43:46.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:46.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:46.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:46.45#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:43:46.45#ibcon#first serial, iclass 27, count 0 2006.257.02:43:46.45#ibcon#enter sib2, iclass 27, count 0 2006.257.02:43:46.45#ibcon#flushed, iclass 27, count 0 2006.257.02:43:46.45#ibcon#about to write, iclass 27, count 0 2006.257.02:43:46.45#ibcon#wrote, iclass 27, count 0 2006.257.02:43:46.45#ibcon#about to read 3, iclass 27, count 0 2006.257.02:43:46.47#ibcon#read 3, iclass 27, count 0 2006.257.02:43:46.47#ibcon#about to read 4, iclass 27, count 0 2006.257.02:43:46.47#ibcon#read 4, iclass 27, count 0 2006.257.02:43:46.47#ibcon#about to read 5, iclass 27, count 0 2006.257.02:43:46.47#ibcon#read 5, iclass 27, count 0 2006.257.02:43:46.47#ibcon#about to read 6, iclass 27, count 0 2006.257.02:43:46.47#ibcon#read 6, iclass 27, count 0 2006.257.02:43:46.47#ibcon#end of sib2, iclass 27, count 0 2006.257.02:43:46.47#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:43:46.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:43:46.47#ibcon#[25=BW32\r\n] 2006.257.02:43:46.47#ibcon#*before write, iclass 27, count 0 2006.257.02:43:46.47#ibcon#enter sib2, iclass 27, count 0 2006.257.02:43:46.47#ibcon#flushed, iclass 27, count 0 2006.257.02:43:46.47#ibcon#about to write, iclass 27, count 0 2006.257.02:43:46.47#ibcon#wrote, iclass 27, count 0 2006.257.02:43:46.47#ibcon#about to read 3, iclass 27, count 0 2006.257.02:43:46.50#ibcon#read 3, iclass 27, count 0 2006.257.02:43:46.50#ibcon#about to read 4, iclass 27, count 0 2006.257.02:43:46.50#ibcon#read 4, iclass 27, count 0 2006.257.02:43:46.50#ibcon#about to read 5, iclass 27, count 0 2006.257.02:43:46.50#ibcon#read 5, iclass 27, count 0 2006.257.02:43:46.50#ibcon#about to read 6, iclass 27, count 0 2006.257.02:43:46.50#ibcon#read 6, iclass 27, count 0 2006.257.02:43:46.50#ibcon#end of sib2, iclass 27, count 0 2006.257.02:43:46.50#ibcon#*after write, iclass 27, count 0 2006.257.02:43:46.50#ibcon#*before return 0, iclass 27, count 0 2006.257.02:43:46.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:46.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:43:46.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:43:46.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:43:46.50$vck44/vbbw=wide 2006.257.02:43:46.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.02:43:46.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.02:43:46.50#ibcon#ireg 8 cls_cnt 0 2006.257.02:43:46.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:43:46.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:43:46.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:43:46.57#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:43:46.57#ibcon#first serial, iclass 29, count 0 2006.257.02:43:46.57#ibcon#enter sib2, iclass 29, count 0 2006.257.02:43:46.57#ibcon#flushed, iclass 29, count 0 2006.257.02:43:46.57#ibcon#about to write, iclass 29, count 0 2006.257.02:43:46.57#ibcon#wrote, iclass 29, count 0 2006.257.02:43:46.57#ibcon#about to read 3, iclass 29, count 0 2006.257.02:43:46.59#ibcon#read 3, iclass 29, count 0 2006.257.02:43:46.59#ibcon#about to read 4, iclass 29, count 0 2006.257.02:43:46.59#ibcon#read 4, iclass 29, count 0 2006.257.02:43:46.59#ibcon#about to read 5, iclass 29, count 0 2006.257.02:43:46.59#ibcon#read 5, iclass 29, count 0 2006.257.02:43:46.59#ibcon#about to read 6, iclass 29, count 0 2006.257.02:43:46.59#ibcon#read 6, iclass 29, count 0 2006.257.02:43:46.59#ibcon#end of sib2, iclass 29, count 0 2006.257.02:43:46.59#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:43:46.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:43:46.59#ibcon#[27=BW32\r\n] 2006.257.02:43:46.59#ibcon#*before write, iclass 29, count 0 2006.257.02:43:46.59#ibcon#enter sib2, iclass 29, count 0 2006.257.02:43:46.59#ibcon#flushed, iclass 29, count 0 2006.257.02:43:46.59#ibcon#about to write, iclass 29, count 0 2006.257.02:43:46.59#ibcon#wrote, iclass 29, count 0 2006.257.02:43:46.59#ibcon#about to read 3, iclass 29, count 0 2006.257.02:43:46.62#ibcon#read 3, iclass 29, count 0 2006.257.02:43:46.62#ibcon#about to read 4, iclass 29, count 0 2006.257.02:43:46.62#ibcon#read 4, iclass 29, count 0 2006.257.02:43:46.62#ibcon#about to read 5, iclass 29, count 0 2006.257.02:43:46.62#ibcon#read 5, iclass 29, count 0 2006.257.02:43:46.62#ibcon#about to read 6, iclass 29, count 0 2006.257.02:43:46.62#ibcon#read 6, iclass 29, count 0 2006.257.02:43:46.62#ibcon#end of sib2, iclass 29, count 0 2006.257.02:43:46.62#ibcon#*after write, iclass 29, count 0 2006.257.02:43:46.62#ibcon#*before return 0, iclass 29, count 0 2006.257.02:43:46.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:43:46.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:43:46.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:43:46.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:43:46.62$setupk4/ifdk4 2006.257.02:43:46.62$ifdk4/lo= 2006.257.02:43:46.62$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:43:46.62$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:43:46.62$ifdk4/patch= 2006.257.02:43:46.62$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:43:46.62$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:43:46.62$setupk4/!*+20s 2006.257.02:43:53.25#abcon#<5=/01 1.1 3.1 18.69 961012.5\r\n> 2006.257.02:43:53.27#abcon#{5=INTERFACE CLEAR} 2006.257.02:43:53.33#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:43:57.14#trakl#Source acquired 2006.257.02:43:59.14#flagr#flagr/antenna,acquired 2006.257.02:44:01.10$setupk4/"tpicd 2006.257.02:44:01.10$setupk4/echo=off 2006.257.02:44:01.10$setupk4/xlog=off 2006.257.02:44:01.10:!2006.257.02:44:13 2006.257.02:44:13.00:preob 2006.257.02:44:13.13/onsource/TRACKING 2006.257.02:44:13.13:!2006.257.02:44:23 2006.257.02:44:23.00:"tape 2006.257.02:44:23.00:"st=record 2006.257.02:44:23.00:data_valid=on 2006.257.02:44:23.00:midob 2006.257.02:44:23.13/onsource/TRACKING 2006.257.02:44:23.13/wx/18.70,1012.5,96 2006.257.02:44:23.21/cable/+6.4888E-03 2006.257.02:44:24.30/va/01,08,usb,yes,35,38 2006.257.02:44:24.30/va/02,07,usb,yes,38,38 2006.257.02:44:24.30/va/03,08,usb,yes,34,36 2006.257.02:44:24.30/va/04,07,usb,yes,39,41 2006.257.02:44:24.30/va/05,04,usb,yes,35,35 2006.257.02:44:24.30/va/06,04,usb,yes,39,38 2006.257.02:44:24.30/va/07,04,usb,yes,40,40 2006.257.02:44:24.30/va/08,04,usb,yes,33,40 2006.257.02:44:24.53/valo/01,524.99,yes,locked 2006.257.02:44:24.53/valo/02,534.99,yes,locked 2006.257.02:44:24.53/valo/03,564.99,yes,locked 2006.257.02:44:24.53/valo/04,624.99,yes,locked 2006.257.02:44:24.53/valo/05,734.99,yes,locked 2006.257.02:44:24.53/valo/06,814.99,yes,locked 2006.257.02:44:24.53/valo/07,864.99,yes,locked 2006.257.02:44:24.53/valo/08,884.99,yes,locked 2006.257.02:44:25.62/vb/01,04,usb,yes,32,32 2006.257.02:44:25.62/vb/02,05,usb,yes,31,31 2006.257.02:44:25.62/vb/03,04,usb,yes,32,35 2006.257.02:44:25.62/vb/04,05,usb,yes,32,31 2006.257.02:44:25.62/vb/05,04,usb,yes,29,31 2006.257.02:44:25.62/vb/06,04,usb,yes,34,30 2006.257.02:44:25.62/vb/07,04,usb,yes,33,33 2006.257.02:44:25.62/vb/08,04,usb,yes,30,34 2006.257.02:44:25.86/vblo/01,629.99,yes,locked 2006.257.02:44:25.86/vblo/02,634.99,yes,locked 2006.257.02:44:25.86/vblo/03,649.99,yes,locked 2006.257.02:44:25.86/vblo/04,679.99,yes,locked 2006.257.02:44:25.86/vblo/05,709.99,yes,locked 2006.257.02:44:25.86/vblo/06,719.99,yes,locked 2006.257.02:44:25.86/vblo/07,734.99,yes,locked 2006.257.02:44:25.86/vblo/08,744.99,yes,locked 2006.257.02:44:26.01/vabw/8 2006.257.02:44:26.16/vbbw/8 2006.257.02:44:26.25/xfe/off,on,15.5 2006.257.02:44:26.62/ifatt/23,28,28,28 2006.257.02:44:27.08/fmout-gps/S +4.60E-07 2006.257.02:44:27.12:!2006.257.02:51:13 2006.257.02:51:13.00:data_valid=off 2006.257.02:51:13.00:"et 2006.257.02:51:13.00:!+3s 2006.257.02:51:16.03:"tape 2006.257.02:51:16.03:postob 2006.257.02:51:16.23/cable/+6.4865E-03 2006.257.02:51:16.23/wx/18.95,1012.5,92 2006.257.02:51:16.30/fmout-gps/S +4.57E-07 2006.257.02:51:16.30:scan_name=257-0253,jd0609,50 2006.257.02:51:16.30:source=1611+343,161341.06,341247.9,2000.0,cw 2006.257.02:51:17.14#flagr#flagr/antenna,new-source 2006.257.02:51:17.14:checkk5 2006.257.02:51:17.66/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:51:18.07/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:51:18.71/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:51:19.15/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:51:19.53/chk_obsdata//k5ts1/T2570244??a.dat file size is correct (nominal:1640MB, actual:1640MB). 2006.257.02:51:19.92/chk_obsdata//k5ts2/T2570244??b.dat file size is correct (nominal:1640MB, actual:1640MB). 2006.257.02:51:20.38/chk_obsdata//k5ts3/T2570244??c.dat file size is correct (nominal:1640MB, actual:1640MB). 2006.257.02:51:20.76/chk_obsdata//k5ts4/T2570244??d.dat file size is correct (nominal:1640MB, actual:1640MB). 2006.257.02:51:21.52/k5log//k5ts1_log_newline 2006.257.02:51:22.28/k5log//k5ts2_log_newline 2006.257.02:51:23.41/k5log//k5ts3_log_newline 2006.257.02:51:24.24/k5log//k5ts4_log_newline 2006.257.02:51:24.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:51:24.27:setupk4=1 2006.257.02:51:24.27$setupk4/echo=on 2006.257.02:51:24.27$setupk4/pcalon 2006.257.02:51:24.27$pcalon/"no phase cal control is implemented here 2006.257.02:51:24.27$setupk4/"tpicd=stop 2006.257.02:51:24.27$setupk4/"rec=synch_on 2006.257.02:51:24.27$setupk4/"rec_mode=128 2006.257.02:51:24.27$setupk4/!* 2006.257.02:51:24.27$setupk4/recpk4 2006.257.02:51:24.27$recpk4/recpatch= 2006.257.02:51:24.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:51:24.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:51:24.27$setupk4/vck44 2006.257.02:51:24.27$vck44/valo=1,524.99 2006.257.02:51:24.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.02:51:24.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.02:51:24.27#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:24.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:24.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:24.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:24.27#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:51:24.27#ibcon#first serial, iclass 29, count 0 2006.257.02:51:24.27#ibcon#enter sib2, iclass 29, count 0 2006.257.02:51:24.27#ibcon#flushed, iclass 29, count 0 2006.257.02:51:24.27#ibcon#about to write, iclass 29, count 0 2006.257.02:51:24.27#ibcon#wrote, iclass 29, count 0 2006.257.02:51:24.27#ibcon#about to read 3, iclass 29, count 0 2006.257.02:51:24.30#ibcon#read 3, iclass 29, count 0 2006.257.02:51:24.30#ibcon#about to read 4, iclass 29, count 0 2006.257.02:51:24.30#ibcon#read 4, iclass 29, count 0 2006.257.02:51:24.30#ibcon#about to read 5, iclass 29, count 0 2006.257.02:51:24.30#ibcon#read 5, iclass 29, count 0 2006.257.02:51:24.30#ibcon#about to read 6, iclass 29, count 0 2006.257.02:51:24.30#ibcon#read 6, iclass 29, count 0 2006.257.02:51:24.30#ibcon#end of sib2, iclass 29, count 0 2006.257.02:51:24.30#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:51:24.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:51:24.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:51:24.30#ibcon#*before write, iclass 29, count 0 2006.257.02:51:24.30#ibcon#enter sib2, iclass 29, count 0 2006.257.02:51:24.30#ibcon#flushed, iclass 29, count 0 2006.257.02:51:24.30#ibcon#about to write, iclass 29, count 0 2006.257.02:51:24.30#ibcon#wrote, iclass 29, count 0 2006.257.02:51:24.30#ibcon#about to read 3, iclass 29, count 0 2006.257.02:51:24.35#ibcon#read 3, iclass 29, count 0 2006.257.02:51:24.35#ibcon#about to read 4, iclass 29, count 0 2006.257.02:51:24.35#ibcon#read 4, iclass 29, count 0 2006.257.02:51:24.35#ibcon#about to read 5, iclass 29, count 0 2006.257.02:51:24.35#ibcon#read 5, iclass 29, count 0 2006.257.02:51:24.35#ibcon#about to read 6, iclass 29, count 0 2006.257.02:51:24.35#ibcon#read 6, iclass 29, count 0 2006.257.02:51:24.35#ibcon#end of sib2, iclass 29, count 0 2006.257.02:51:24.35#ibcon#*after write, iclass 29, count 0 2006.257.02:51:24.35#ibcon#*before return 0, iclass 29, count 0 2006.257.02:51:24.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:24.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:24.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:51:24.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:51:24.35$vck44/va=1,8 2006.257.02:51:24.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.02:51:24.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.02:51:24.35#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:24.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:24.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:24.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:24.35#ibcon#enter wrdev, iclass 31, count 2 2006.257.02:51:24.35#ibcon#first serial, iclass 31, count 2 2006.257.02:51:24.35#ibcon#enter sib2, iclass 31, count 2 2006.257.02:51:24.35#ibcon#flushed, iclass 31, count 2 2006.257.02:51:24.35#ibcon#about to write, iclass 31, count 2 2006.257.02:51:24.35#ibcon#wrote, iclass 31, count 2 2006.257.02:51:24.35#ibcon#about to read 3, iclass 31, count 2 2006.257.02:51:24.37#ibcon#read 3, iclass 31, count 2 2006.257.02:51:24.37#ibcon#about to read 4, iclass 31, count 2 2006.257.02:51:24.37#ibcon#read 4, iclass 31, count 2 2006.257.02:51:24.37#ibcon#about to read 5, iclass 31, count 2 2006.257.02:51:24.37#ibcon#read 5, iclass 31, count 2 2006.257.02:51:24.37#ibcon#about to read 6, iclass 31, count 2 2006.257.02:51:24.37#ibcon#read 6, iclass 31, count 2 2006.257.02:51:24.37#ibcon#end of sib2, iclass 31, count 2 2006.257.02:51:24.37#ibcon#*mode == 0, iclass 31, count 2 2006.257.02:51:24.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.02:51:24.37#ibcon#[25=AT01-08\r\n] 2006.257.02:51:24.37#ibcon#*before write, iclass 31, count 2 2006.257.02:51:24.37#ibcon#enter sib2, iclass 31, count 2 2006.257.02:51:24.37#ibcon#flushed, iclass 31, count 2 2006.257.02:51:24.37#ibcon#about to write, iclass 31, count 2 2006.257.02:51:24.37#ibcon#wrote, iclass 31, count 2 2006.257.02:51:24.37#ibcon#about to read 3, iclass 31, count 2 2006.257.02:51:24.40#ibcon#read 3, iclass 31, count 2 2006.257.02:51:24.40#ibcon#about to read 4, iclass 31, count 2 2006.257.02:51:24.40#ibcon#read 4, iclass 31, count 2 2006.257.02:51:24.40#ibcon#about to read 5, iclass 31, count 2 2006.257.02:51:24.40#ibcon#read 5, iclass 31, count 2 2006.257.02:51:24.40#ibcon#about to read 6, iclass 31, count 2 2006.257.02:51:24.40#ibcon#read 6, iclass 31, count 2 2006.257.02:51:24.40#ibcon#end of sib2, iclass 31, count 2 2006.257.02:51:24.40#ibcon#*after write, iclass 31, count 2 2006.257.02:51:24.40#ibcon#*before return 0, iclass 31, count 2 2006.257.02:51:24.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:24.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:24.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.02:51:24.40#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:24.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:24.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:24.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:24.52#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:51:24.52#ibcon#first serial, iclass 31, count 0 2006.257.02:51:24.52#ibcon#enter sib2, iclass 31, count 0 2006.257.02:51:24.52#ibcon#flushed, iclass 31, count 0 2006.257.02:51:24.52#ibcon#about to write, iclass 31, count 0 2006.257.02:51:24.52#ibcon#wrote, iclass 31, count 0 2006.257.02:51:24.52#ibcon#about to read 3, iclass 31, count 0 2006.257.02:51:24.54#ibcon#read 3, iclass 31, count 0 2006.257.02:51:24.54#ibcon#about to read 4, iclass 31, count 0 2006.257.02:51:24.54#ibcon#read 4, iclass 31, count 0 2006.257.02:51:24.54#ibcon#about to read 5, iclass 31, count 0 2006.257.02:51:24.54#ibcon#read 5, iclass 31, count 0 2006.257.02:51:24.54#ibcon#about to read 6, iclass 31, count 0 2006.257.02:51:24.54#ibcon#read 6, iclass 31, count 0 2006.257.02:51:24.54#ibcon#end of sib2, iclass 31, count 0 2006.257.02:51:24.54#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:51:24.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:51:24.54#ibcon#[25=USB\r\n] 2006.257.02:51:24.54#ibcon#*before write, iclass 31, count 0 2006.257.02:51:24.54#ibcon#enter sib2, iclass 31, count 0 2006.257.02:51:24.54#ibcon#flushed, iclass 31, count 0 2006.257.02:51:24.54#ibcon#about to write, iclass 31, count 0 2006.257.02:51:24.54#ibcon#wrote, iclass 31, count 0 2006.257.02:51:24.54#ibcon#about to read 3, iclass 31, count 0 2006.257.02:51:24.57#ibcon#read 3, iclass 31, count 0 2006.257.02:51:24.57#ibcon#about to read 4, iclass 31, count 0 2006.257.02:51:24.57#ibcon#read 4, iclass 31, count 0 2006.257.02:51:24.57#ibcon#about to read 5, iclass 31, count 0 2006.257.02:51:24.57#ibcon#read 5, iclass 31, count 0 2006.257.02:51:24.57#ibcon#about to read 6, iclass 31, count 0 2006.257.02:51:24.57#ibcon#read 6, iclass 31, count 0 2006.257.02:51:24.57#ibcon#end of sib2, iclass 31, count 0 2006.257.02:51:24.57#ibcon#*after write, iclass 31, count 0 2006.257.02:51:24.57#ibcon#*before return 0, iclass 31, count 0 2006.257.02:51:24.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:24.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:24.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:51:24.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:51:24.57$vck44/valo=2,534.99 2006.257.02:51:24.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.02:51:24.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.02:51:24.57#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:24.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:24.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:24.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:24.57#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:51:24.57#ibcon#first serial, iclass 33, count 0 2006.257.02:51:24.57#ibcon#enter sib2, iclass 33, count 0 2006.257.02:51:24.57#ibcon#flushed, iclass 33, count 0 2006.257.02:51:24.57#ibcon#about to write, iclass 33, count 0 2006.257.02:51:24.57#ibcon#wrote, iclass 33, count 0 2006.257.02:51:24.57#ibcon#about to read 3, iclass 33, count 0 2006.257.02:51:24.59#ibcon#read 3, iclass 33, count 0 2006.257.02:51:24.59#ibcon#about to read 4, iclass 33, count 0 2006.257.02:51:24.59#ibcon#read 4, iclass 33, count 0 2006.257.02:51:24.59#ibcon#about to read 5, iclass 33, count 0 2006.257.02:51:24.59#ibcon#read 5, iclass 33, count 0 2006.257.02:51:24.59#ibcon#about to read 6, iclass 33, count 0 2006.257.02:51:24.59#ibcon#read 6, iclass 33, count 0 2006.257.02:51:24.59#ibcon#end of sib2, iclass 33, count 0 2006.257.02:51:24.59#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:51:24.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:51:24.59#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:51:24.59#ibcon#*before write, iclass 33, count 0 2006.257.02:51:24.59#ibcon#enter sib2, iclass 33, count 0 2006.257.02:51:24.59#ibcon#flushed, iclass 33, count 0 2006.257.02:51:24.59#ibcon#about to write, iclass 33, count 0 2006.257.02:51:24.59#ibcon#wrote, iclass 33, count 0 2006.257.02:51:24.59#ibcon#about to read 3, iclass 33, count 0 2006.257.02:51:24.63#ibcon#read 3, iclass 33, count 0 2006.257.02:51:24.63#ibcon#about to read 4, iclass 33, count 0 2006.257.02:51:24.63#ibcon#read 4, iclass 33, count 0 2006.257.02:51:24.63#ibcon#about to read 5, iclass 33, count 0 2006.257.02:51:24.63#ibcon#read 5, iclass 33, count 0 2006.257.02:51:24.63#ibcon#about to read 6, iclass 33, count 0 2006.257.02:51:24.63#ibcon#read 6, iclass 33, count 0 2006.257.02:51:24.63#ibcon#end of sib2, iclass 33, count 0 2006.257.02:51:24.63#ibcon#*after write, iclass 33, count 0 2006.257.02:51:24.63#ibcon#*before return 0, iclass 33, count 0 2006.257.02:51:24.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:24.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:24.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:51:24.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:51:24.63$vck44/va=2,7 2006.257.02:51:24.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.02:51:24.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.02:51:24.63#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:24.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:24.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:24.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:24.69#ibcon#enter wrdev, iclass 35, count 2 2006.257.02:51:24.69#ibcon#first serial, iclass 35, count 2 2006.257.02:51:24.69#ibcon#enter sib2, iclass 35, count 2 2006.257.02:51:24.69#ibcon#flushed, iclass 35, count 2 2006.257.02:51:24.69#ibcon#about to write, iclass 35, count 2 2006.257.02:51:24.69#ibcon#wrote, iclass 35, count 2 2006.257.02:51:24.69#ibcon#about to read 3, iclass 35, count 2 2006.257.02:51:24.71#ibcon#read 3, iclass 35, count 2 2006.257.02:51:24.71#ibcon#about to read 4, iclass 35, count 2 2006.257.02:51:24.71#ibcon#read 4, iclass 35, count 2 2006.257.02:51:24.71#ibcon#about to read 5, iclass 35, count 2 2006.257.02:51:24.71#ibcon#read 5, iclass 35, count 2 2006.257.02:51:24.71#ibcon#about to read 6, iclass 35, count 2 2006.257.02:51:24.71#ibcon#read 6, iclass 35, count 2 2006.257.02:51:24.71#ibcon#end of sib2, iclass 35, count 2 2006.257.02:51:24.71#ibcon#*mode == 0, iclass 35, count 2 2006.257.02:51:24.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.02:51:24.71#ibcon#[25=AT02-07\r\n] 2006.257.02:51:24.71#ibcon#*before write, iclass 35, count 2 2006.257.02:51:24.71#ibcon#enter sib2, iclass 35, count 2 2006.257.02:51:24.71#ibcon#flushed, iclass 35, count 2 2006.257.02:51:24.71#ibcon#about to write, iclass 35, count 2 2006.257.02:51:24.71#ibcon#wrote, iclass 35, count 2 2006.257.02:51:24.71#ibcon#about to read 3, iclass 35, count 2 2006.257.02:51:24.74#ibcon#read 3, iclass 35, count 2 2006.257.02:51:24.74#ibcon#about to read 4, iclass 35, count 2 2006.257.02:51:24.74#ibcon#read 4, iclass 35, count 2 2006.257.02:51:24.74#ibcon#about to read 5, iclass 35, count 2 2006.257.02:51:24.74#ibcon#read 5, iclass 35, count 2 2006.257.02:51:24.74#ibcon#about to read 6, iclass 35, count 2 2006.257.02:51:24.74#ibcon#read 6, iclass 35, count 2 2006.257.02:51:24.74#ibcon#end of sib2, iclass 35, count 2 2006.257.02:51:24.74#ibcon#*after write, iclass 35, count 2 2006.257.02:51:24.74#ibcon#*before return 0, iclass 35, count 2 2006.257.02:51:24.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:24.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:24.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.02:51:24.74#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:24.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:24.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:24.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:24.86#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:51:24.86#ibcon#first serial, iclass 35, count 0 2006.257.02:51:24.86#ibcon#enter sib2, iclass 35, count 0 2006.257.02:51:24.86#ibcon#flushed, iclass 35, count 0 2006.257.02:51:24.86#ibcon#about to write, iclass 35, count 0 2006.257.02:51:24.86#ibcon#wrote, iclass 35, count 0 2006.257.02:51:24.86#ibcon#about to read 3, iclass 35, count 0 2006.257.02:51:24.88#ibcon#read 3, iclass 35, count 0 2006.257.02:51:24.88#ibcon#about to read 4, iclass 35, count 0 2006.257.02:51:24.88#ibcon#read 4, iclass 35, count 0 2006.257.02:51:24.88#ibcon#about to read 5, iclass 35, count 0 2006.257.02:51:24.88#ibcon#read 5, iclass 35, count 0 2006.257.02:51:24.88#ibcon#about to read 6, iclass 35, count 0 2006.257.02:51:24.88#ibcon#read 6, iclass 35, count 0 2006.257.02:51:24.88#ibcon#end of sib2, iclass 35, count 0 2006.257.02:51:24.88#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:51:24.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:51:24.88#ibcon#[25=USB\r\n] 2006.257.02:51:24.88#ibcon#*before write, iclass 35, count 0 2006.257.02:51:24.88#ibcon#enter sib2, iclass 35, count 0 2006.257.02:51:24.88#ibcon#flushed, iclass 35, count 0 2006.257.02:51:24.88#ibcon#about to write, iclass 35, count 0 2006.257.02:51:24.88#ibcon#wrote, iclass 35, count 0 2006.257.02:51:24.88#ibcon#about to read 3, iclass 35, count 0 2006.257.02:51:24.91#ibcon#read 3, iclass 35, count 0 2006.257.02:51:24.91#ibcon#about to read 4, iclass 35, count 0 2006.257.02:51:24.91#ibcon#read 4, iclass 35, count 0 2006.257.02:51:24.91#ibcon#about to read 5, iclass 35, count 0 2006.257.02:51:24.91#ibcon#read 5, iclass 35, count 0 2006.257.02:51:24.91#ibcon#about to read 6, iclass 35, count 0 2006.257.02:51:24.91#ibcon#read 6, iclass 35, count 0 2006.257.02:51:24.91#ibcon#end of sib2, iclass 35, count 0 2006.257.02:51:24.91#ibcon#*after write, iclass 35, count 0 2006.257.02:51:24.91#ibcon#*before return 0, iclass 35, count 0 2006.257.02:51:24.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:24.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:24.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:51:24.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:51:24.91$vck44/valo=3,564.99 2006.257.02:51:24.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.02:51:24.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.02:51:24.91#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:24.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:24.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:24.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:24.91#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:51:24.91#ibcon#first serial, iclass 37, count 0 2006.257.02:51:24.91#ibcon#enter sib2, iclass 37, count 0 2006.257.02:51:24.91#ibcon#flushed, iclass 37, count 0 2006.257.02:51:24.91#ibcon#about to write, iclass 37, count 0 2006.257.02:51:24.91#ibcon#wrote, iclass 37, count 0 2006.257.02:51:24.91#ibcon#about to read 3, iclass 37, count 0 2006.257.02:51:24.93#ibcon#read 3, iclass 37, count 0 2006.257.02:51:24.93#ibcon#about to read 4, iclass 37, count 0 2006.257.02:51:24.93#ibcon#read 4, iclass 37, count 0 2006.257.02:51:24.93#ibcon#about to read 5, iclass 37, count 0 2006.257.02:51:24.93#ibcon#read 5, iclass 37, count 0 2006.257.02:51:24.93#ibcon#about to read 6, iclass 37, count 0 2006.257.02:51:24.93#ibcon#read 6, iclass 37, count 0 2006.257.02:51:24.93#ibcon#end of sib2, iclass 37, count 0 2006.257.02:51:24.93#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:51:24.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:51:24.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:51:24.93#ibcon#*before write, iclass 37, count 0 2006.257.02:51:24.93#ibcon#enter sib2, iclass 37, count 0 2006.257.02:51:24.93#ibcon#flushed, iclass 37, count 0 2006.257.02:51:24.93#ibcon#about to write, iclass 37, count 0 2006.257.02:51:24.93#ibcon#wrote, iclass 37, count 0 2006.257.02:51:24.93#ibcon#about to read 3, iclass 37, count 0 2006.257.02:51:24.97#ibcon#read 3, iclass 37, count 0 2006.257.02:51:24.97#ibcon#about to read 4, iclass 37, count 0 2006.257.02:51:24.97#ibcon#read 4, iclass 37, count 0 2006.257.02:51:24.97#ibcon#about to read 5, iclass 37, count 0 2006.257.02:51:24.97#ibcon#read 5, iclass 37, count 0 2006.257.02:51:24.97#ibcon#about to read 6, iclass 37, count 0 2006.257.02:51:24.97#ibcon#read 6, iclass 37, count 0 2006.257.02:51:24.97#ibcon#end of sib2, iclass 37, count 0 2006.257.02:51:24.97#ibcon#*after write, iclass 37, count 0 2006.257.02:51:24.97#ibcon#*before return 0, iclass 37, count 0 2006.257.02:51:24.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:24.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:24.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:51:24.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:51:24.97$vck44/va=3,8 2006.257.02:51:24.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.02:51:24.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.02:51:24.97#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:24.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:25.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:25.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:25.03#ibcon#enter wrdev, iclass 39, count 2 2006.257.02:51:25.03#ibcon#first serial, iclass 39, count 2 2006.257.02:51:25.03#ibcon#enter sib2, iclass 39, count 2 2006.257.02:51:25.03#ibcon#flushed, iclass 39, count 2 2006.257.02:51:25.03#ibcon#about to write, iclass 39, count 2 2006.257.02:51:25.03#ibcon#wrote, iclass 39, count 2 2006.257.02:51:25.03#ibcon#about to read 3, iclass 39, count 2 2006.257.02:51:25.05#ibcon#read 3, iclass 39, count 2 2006.257.02:51:25.05#ibcon#about to read 4, iclass 39, count 2 2006.257.02:51:25.05#ibcon#read 4, iclass 39, count 2 2006.257.02:51:25.05#ibcon#about to read 5, iclass 39, count 2 2006.257.02:51:25.05#ibcon#read 5, iclass 39, count 2 2006.257.02:51:25.05#ibcon#about to read 6, iclass 39, count 2 2006.257.02:51:25.05#ibcon#read 6, iclass 39, count 2 2006.257.02:51:25.05#ibcon#end of sib2, iclass 39, count 2 2006.257.02:51:25.05#ibcon#*mode == 0, iclass 39, count 2 2006.257.02:51:25.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.02:51:25.05#ibcon#[25=AT03-08\r\n] 2006.257.02:51:25.05#ibcon#*before write, iclass 39, count 2 2006.257.02:51:25.05#ibcon#enter sib2, iclass 39, count 2 2006.257.02:51:25.05#ibcon#flushed, iclass 39, count 2 2006.257.02:51:25.05#ibcon#about to write, iclass 39, count 2 2006.257.02:51:25.05#ibcon#wrote, iclass 39, count 2 2006.257.02:51:25.05#ibcon#about to read 3, iclass 39, count 2 2006.257.02:51:25.08#ibcon#read 3, iclass 39, count 2 2006.257.02:51:25.08#ibcon#about to read 4, iclass 39, count 2 2006.257.02:51:25.09#ibcon#read 4, iclass 39, count 2 2006.257.02:51:25.09#ibcon#about to read 5, iclass 39, count 2 2006.257.02:51:25.09#ibcon#read 5, iclass 39, count 2 2006.257.02:51:25.09#ibcon#about to read 6, iclass 39, count 2 2006.257.02:51:25.09#ibcon#read 6, iclass 39, count 2 2006.257.02:51:25.09#ibcon#end of sib2, iclass 39, count 2 2006.257.02:51:25.09#ibcon#*after write, iclass 39, count 2 2006.257.02:51:25.09#ibcon#*before return 0, iclass 39, count 2 2006.257.02:51:25.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:25.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:25.09#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.02:51:25.09#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:25.09#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:25.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:25.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:25.20#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:51:25.20#ibcon#first serial, iclass 39, count 0 2006.257.02:51:25.20#ibcon#enter sib2, iclass 39, count 0 2006.257.02:51:25.20#ibcon#flushed, iclass 39, count 0 2006.257.02:51:25.20#ibcon#about to write, iclass 39, count 0 2006.257.02:51:25.20#ibcon#wrote, iclass 39, count 0 2006.257.02:51:25.20#ibcon#about to read 3, iclass 39, count 0 2006.257.02:51:25.22#ibcon#read 3, iclass 39, count 0 2006.257.02:51:25.22#ibcon#about to read 4, iclass 39, count 0 2006.257.02:51:25.22#ibcon#read 4, iclass 39, count 0 2006.257.02:51:25.22#ibcon#about to read 5, iclass 39, count 0 2006.257.02:51:25.22#ibcon#read 5, iclass 39, count 0 2006.257.02:51:25.22#ibcon#about to read 6, iclass 39, count 0 2006.257.02:51:25.22#ibcon#read 6, iclass 39, count 0 2006.257.02:51:25.22#ibcon#end of sib2, iclass 39, count 0 2006.257.02:51:25.22#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:51:25.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:51:25.22#ibcon#[25=USB\r\n] 2006.257.02:51:25.22#ibcon#*before write, iclass 39, count 0 2006.257.02:51:25.22#ibcon#enter sib2, iclass 39, count 0 2006.257.02:51:25.22#ibcon#flushed, iclass 39, count 0 2006.257.02:51:25.22#ibcon#about to write, iclass 39, count 0 2006.257.02:51:25.22#ibcon#wrote, iclass 39, count 0 2006.257.02:51:25.22#ibcon#about to read 3, iclass 39, count 0 2006.257.02:51:25.25#ibcon#read 3, iclass 39, count 0 2006.257.02:51:25.25#ibcon#about to read 4, iclass 39, count 0 2006.257.02:51:25.25#ibcon#read 4, iclass 39, count 0 2006.257.02:51:25.25#ibcon#about to read 5, iclass 39, count 0 2006.257.02:51:25.25#ibcon#read 5, iclass 39, count 0 2006.257.02:51:25.25#ibcon#about to read 6, iclass 39, count 0 2006.257.02:51:25.25#ibcon#read 6, iclass 39, count 0 2006.257.02:51:25.25#ibcon#end of sib2, iclass 39, count 0 2006.257.02:51:25.25#ibcon#*after write, iclass 39, count 0 2006.257.02:51:25.25#ibcon#*before return 0, iclass 39, count 0 2006.257.02:51:25.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:25.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:25.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:51:25.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:51:25.25$vck44/valo=4,624.99 2006.257.02:51:25.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.02:51:25.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.02:51:25.25#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:25.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:25.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:25.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:25.25#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:51:25.25#ibcon#first serial, iclass 3, count 0 2006.257.02:51:25.25#ibcon#enter sib2, iclass 3, count 0 2006.257.02:51:25.25#ibcon#flushed, iclass 3, count 0 2006.257.02:51:25.25#ibcon#about to write, iclass 3, count 0 2006.257.02:51:25.25#ibcon#wrote, iclass 3, count 0 2006.257.02:51:25.25#ibcon#about to read 3, iclass 3, count 0 2006.257.02:51:25.27#ibcon#read 3, iclass 3, count 0 2006.257.02:51:25.27#ibcon#about to read 4, iclass 3, count 0 2006.257.02:51:25.27#ibcon#read 4, iclass 3, count 0 2006.257.02:51:25.27#ibcon#about to read 5, iclass 3, count 0 2006.257.02:51:25.27#ibcon#read 5, iclass 3, count 0 2006.257.02:51:25.27#ibcon#about to read 6, iclass 3, count 0 2006.257.02:51:25.27#ibcon#read 6, iclass 3, count 0 2006.257.02:51:25.27#ibcon#end of sib2, iclass 3, count 0 2006.257.02:51:25.27#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:51:25.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:51:25.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:51:25.27#ibcon#*before write, iclass 3, count 0 2006.257.02:51:25.27#ibcon#enter sib2, iclass 3, count 0 2006.257.02:51:25.27#ibcon#flushed, iclass 3, count 0 2006.257.02:51:25.27#ibcon#about to write, iclass 3, count 0 2006.257.02:51:25.27#ibcon#wrote, iclass 3, count 0 2006.257.02:51:25.27#ibcon#about to read 3, iclass 3, count 0 2006.257.02:51:25.31#ibcon#read 3, iclass 3, count 0 2006.257.02:51:25.31#ibcon#about to read 4, iclass 3, count 0 2006.257.02:51:25.31#ibcon#read 4, iclass 3, count 0 2006.257.02:51:25.31#ibcon#about to read 5, iclass 3, count 0 2006.257.02:51:25.31#ibcon#read 5, iclass 3, count 0 2006.257.02:51:25.31#ibcon#about to read 6, iclass 3, count 0 2006.257.02:51:25.31#ibcon#read 6, iclass 3, count 0 2006.257.02:51:25.31#ibcon#end of sib2, iclass 3, count 0 2006.257.02:51:25.31#ibcon#*after write, iclass 3, count 0 2006.257.02:51:25.31#ibcon#*before return 0, iclass 3, count 0 2006.257.02:51:25.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:25.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:25.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:51:25.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:51:25.31$vck44/va=4,7 2006.257.02:51:25.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.02:51:25.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.02:51:25.31#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:25.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:25.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:25.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:25.37#ibcon#enter wrdev, iclass 5, count 2 2006.257.02:51:25.37#ibcon#first serial, iclass 5, count 2 2006.257.02:51:25.37#ibcon#enter sib2, iclass 5, count 2 2006.257.02:51:25.37#ibcon#flushed, iclass 5, count 2 2006.257.02:51:25.37#ibcon#about to write, iclass 5, count 2 2006.257.02:51:25.37#ibcon#wrote, iclass 5, count 2 2006.257.02:51:25.37#ibcon#about to read 3, iclass 5, count 2 2006.257.02:51:25.39#ibcon#read 3, iclass 5, count 2 2006.257.02:51:25.39#ibcon#about to read 4, iclass 5, count 2 2006.257.02:51:25.39#ibcon#read 4, iclass 5, count 2 2006.257.02:51:25.39#ibcon#about to read 5, iclass 5, count 2 2006.257.02:51:25.39#ibcon#read 5, iclass 5, count 2 2006.257.02:51:25.39#ibcon#about to read 6, iclass 5, count 2 2006.257.02:51:25.39#ibcon#read 6, iclass 5, count 2 2006.257.02:51:25.39#ibcon#end of sib2, iclass 5, count 2 2006.257.02:51:25.39#ibcon#*mode == 0, iclass 5, count 2 2006.257.02:51:25.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.02:51:25.39#ibcon#[25=AT04-07\r\n] 2006.257.02:51:25.39#ibcon#*before write, iclass 5, count 2 2006.257.02:51:25.39#ibcon#enter sib2, iclass 5, count 2 2006.257.02:51:25.39#ibcon#flushed, iclass 5, count 2 2006.257.02:51:25.39#ibcon#about to write, iclass 5, count 2 2006.257.02:51:25.39#ibcon#wrote, iclass 5, count 2 2006.257.02:51:25.39#ibcon#about to read 3, iclass 5, count 2 2006.257.02:51:25.42#ibcon#read 3, iclass 5, count 2 2006.257.02:51:25.42#ibcon#about to read 4, iclass 5, count 2 2006.257.02:51:25.42#ibcon#read 4, iclass 5, count 2 2006.257.02:51:25.42#ibcon#about to read 5, iclass 5, count 2 2006.257.02:51:25.42#ibcon#read 5, iclass 5, count 2 2006.257.02:51:25.42#ibcon#about to read 6, iclass 5, count 2 2006.257.02:51:25.42#ibcon#read 6, iclass 5, count 2 2006.257.02:51:25.42#ibcon#end of sib2, iclass 5, count 2 2006.257.02:51:25.42#ibcon#*after write, iclass 5, count 2 2006.257.02:51:25.42#ibcon#*before return 0, iclass 5, count 2 2006.257.02:51:25.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:25.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:25.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.02:51:25.42#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:25.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:25.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:25.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:25.54#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:51:25.54#ibcon#first serial, iclass 5, count 0 2006.257.02:51:25.54#ibcon#enter sib2, iclass 5, count 0 2006.257.02:51:25.54#ibcon#flushed, iclass 5, count 0 2006.257.02:51:25.54#ibcon#about to write, iclass 5, count 0 2006.257.02:51:25.54#ibcon#wrote, iclass 5, count 0 2006.257.02:51:25.54#ibcon#about to read 3, iclass 5, count 0 2006.257.02:51:25.56#ibcon#read 3, iclass 5, count 0 2006.257.02:51:25.56#ibcon#about to read 4, iclass 5, count 0 2006.257.02:51:25.56#ibcon#read 4, iclass 5, count 0 2006.257.02:51:25.56#ibcon#about to read 5, iclass 5, count 0 2006.257.02:51:25.56#ibcon#read 5, iclass 5, count 0 2006.257.02:51:25.56#ibcon#about to read 6, iclass 5, count 0 2006.257.02:51:25.56#ibcon#read 6, iclass 5, count 0 2006.257.02:51:25.56#ibcon#end of sib2, iclass 5, count 0 2006.257.02:51:25.56#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:51:25.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:51:25.56#ibcon#[25=USB\r\n] 2006.257.02:51:25.56#ibcon#*before write, iclass 5, count 0 2006.257.02:51:25.56#ibcon#enter sib2, iclass 5, count 0 2006.257.02:51:25.56#ibcon#flushed, iclass 5, count 0 2006.257.02:51:25.56#ibcon#about to write, iclass 5, count 0 2006.257.02:51:25.56#ibcon#wrote, iclass 5, count 0 2006.257.02:51:25.56#ibcon#about to read 3, iclass 5, count 0 2006.257.02:51:25.59#ibcon#read 3, iclass 5, count 0 2006.257.02:51:25.59#ibcon#about to read 4, iclass 5, count 0 2006.257.02:51:25.59#ibcon#read 4, iclass 5, count 0 2006.257.02:51:25.59#ibcon#about to read 5, iclass 5, count 0 2006.257.02:51:25.59#ibcon#read 5, iclass 5, count 0 2006.257.02:51:25.59#ibcon#about to read 6, iclass 5, count 0 2006.257.02:51:25.59#ibcon#read 6, iclass 5, count 0 2006.257.02:51:25.59#ibcon#end of sib2, iclass 5, count 0 2006.257.02:51:25.59#ibcon#*after write, iclass 5, count 0 2006.257.02:51:25.59#ibcon#*before return 0, iclass 5, count 0 2006.257.02:51:25.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:25.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:25.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:51:25.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:51:25.59$vck44/valo=5,734.99 2006.257.02:51:25.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.02:51:25.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.02:51:25.59#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:25.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:25.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:25.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:25.59#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:51:25.59#ibcon#first serial, iclass 7, count 0 2006.257.02:51:25.59#ibcon#enter sib2, iclass 7, count 0 2006.257.02:51:25.59#ibcon#flushed, iclass 7, count 0 2006.257.02:51:25.59#ibcon#about to write, iclass 7, count 0 2006.257.02:51:25.59#ibcon#wrote, iclass 7, count 0 2006.257.02:51:25.59#ibcon#about to read 3, iclass 7, count 0 2006.257.02:51:25.61#ibcon#read 3, iclass 7, count 0 2006.257.02:51:25.61#ibcon#about to read 4, iclass 7, count 0 2006.257.02:51:25.61#ibcon#read 4, iclass 7, count 0 2006.257.02:51:25.61#ibcon#about to read 5, iclass 7, count 0 2006.257.02:51:25.61#ibcon#read 5, iclass 7, count 0 2006.257.02:51:25.61#ibcon#about to read 6, iclass 7, count 0 2006.257.02:51:25.61#ibcon#read 6, iclass 7, count 0 2006.257.02:51:25.61#ibcon#end of sib2, iclass 7, count 0 2006.257.02:51:25.61#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:51:25.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:51:25.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:51:25.61#ibcon#*before write, iclass 7, count 0 2006.257.02:51:25.61#ibcon#enter sib2, iclass 7, count 0 2006.257.02:51:25.61#ibcon#flushed, iclass 7, count 0 2006.257.02:51:25.61#ibcon#about to write, iclass 7, count 0 2006.257.02:51:25.61#ibcon#wrote, iclass 7, count 0 2006.257.02:51:25.61#ibcon#about to read 3, iclass 7, count 0 2006.257.02:51:25.65#ibcon#read 3, iclass 7, count 0 2006.257.02:51:25.65#ibcon#about to read 4, iclass 7, count 0 2006.257.02:51:25.65#ibcon#read 4, iclass 7, count 0 2006.257.02:51:25.65#ibcon#about to read 5, iclass 7, count 0 2006.257.02:51:25.65#ibcon#read 5, iclass 7, count 0 2006.257.02:51:25.65#ibcon#about to read 6, iclass 7, count 0 2006.257.02:51:25.65#ibcon#read 6, iclass 7, count 0 2006.257.02:51:25.65#ibcon#end of sib2, iclass 7, count 0 2006.257.02:51:25.65#ibcon#*after write, iclass 7, count 0 2006.257.02:51:25.65#ibcon#*before return 0, iclass 7, count 0 2006.257.02:51:25.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:25.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:25.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:51:25.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:51:25.65$vck44/va=5,4 2006.257.02:51:25.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.02:51:25.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.02:51:25.65#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:25.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:25.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:25.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:25.71#ibcon#enter wrdev, iclass 11, count 2 2006.257.02:51:25.71#ibcon#first serial, iclass 11, count 2 2006.257.02:51:25.71#ibcon#enter sib2, iclass 11, count 2 2006.257.02:51:25.71#ibcon#flushed, iclass 11, count 2 2006.257.02:51:25.71#ibcon#about to write, iclass 11, count 2 2006.257.02:51:25.71#ibcon#wrote, iclass 11, count 2 2006.257.02:51:25.71#ibcon#about to read 3, iclass 11, count 2 2006.257.02:51:25.73#ibcon#read 3, iclass 11, count 2 2006.257.02:51:25.73#ibcon#about to read 4, iclass 11, count 2 2006.257.02:51:25.73#ibcon#read 4, iclass 11, count 2 2006.257.02:51:25.73#ibcon#about to read 5, iclass 11, count 2 2006.257.02:51:25.73#ibcon#read 5, iclass 11, count 2 2006.257.02:51:25.73#ibcon#about to read 6, iclass 11, count 2 2006.257.02:51:25.73#ibcon#read 6, iclass 11, count 2 2006.257.02:51:25.73#ibcon#end of sib2, iclass 11, count 2 2006.257.02:51:25.73#ibcon#*mode == 0, iclass 11, count 2 2006.257.02:51:25.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.02:51:25.73#ibcon#[25=AT05-04\r\n] 2006.257.02:51:25.73#ibcon#*before write, iclass 11, count 2 2006.257.02:51:25.73#ibcon#enter sib2, iclass 11, count 2 2006.257.02:51:25.73#ibcon#flushed, iclass 11, count 2 2006.257.02:51:25.73#ibcon#about to write, iclass 11, count 2 2006.257.02:51:25.73#ibcon#wrote, iclass 11, count 2 2006.257.02:51:25.73#ibcon#about to read 3, iclass 11, count 2 2006.257.02:51:25.76#ibcon#read 3, iclass 11, count 2 2006.257.02:51:25.76#ibcon#about to read 4, iclass 11, count 2 2006.257.02:51:25.76#ibcon#read 4, iclass 11, count 2 2006.257.02:51:25.76#ibcon#about to read 5, iclass 11, count 2 2006.257.02:51:25.76#ibcon#read 5, iclass 11, count 2 2006.257.02:51:25.76#ibcon#about to read 6, iclass 11, count 2 2006.257.02:51:25.76#ibcon#read 6, iclass 11, count 2 2006.257.02:51:25.76#ibcon#end of sib2, iclass 11, count 2 2006.257.02:51:25.76#ibcon#*after write, iclass 11, count 2 2006.257.02:51:25.76#ibcon#*before return 0, iclass 11, count 2 2006.257.02:51:25.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:25.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:25.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.02:51:25.76#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:25.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:25.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:25.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:25.88#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:51:25.88#ibcon#first serial, iclass 11, count 0 2006.257.02:51:25.88#ibcon#enter sib2, iclass 11, count 0 2006.257.02:51:25.88#ibcon#flushed, iclass 11, count 0 2006.257.02:51:25.88#ibcon#about to write, iclass 11, count 0 2006.257.02:51:25.88#ibcon#wrote, iclass 11, count 0 2006.257.02:51:25.88#ibcon#about to read 3, iclass 11, count 0 2006.257.02:51:25.90#ibcon#read 3, iclass 11, count 0 2006.257.02:51:25.90#ibcon#about to read 4, iclass 11, count 0 2006.257.02:51:25.90#ibcon#read 4, iclass 11, count 0 2006.257.02:51:25.90#ibcon#about to read 5, iclass 11, count 0 2006.257.02:51:25.90#ibcon#read 5, iclass 11, count 0 2006.257.02:51:25.90#ibcon#about to read 6, iclass 11, count 0 2006.257.02:51:25.90#ibcon#read 6, iclass 11, count 0 2006.257.02:51:25.90#ibcon#end of sib2, iclass 11, count 0 2006.257.02:51:25.90#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:51:25.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:51:25.90#ibcon#[25=USB\r\n] 2006.257.02:51:25.90#ibcon#*before write, iclass 11, count 0 2006.257.02:51:25.90#ibcon#enter sib2, iclass 11, count 0 2006.257.02:51:25.90#ibcon#flushed, iclass 11, count 0 2006.257.02:51:25.90#ibcon#about to write, iclass 11, count 0 2006.257.02:51:25.90#ibcon#wrote, iclass 11, count 0 2006.257.02:51:25.90#ibcon#about to read 3, iclass 11, count 0 2006.257.02:51:25.93#ibcon#read 3, iclass 11, count 0 2006.257.02:51:25.93#ibcon#about to read 4, iclass 11, count 0 2006.257.02:51:25.93#ibcon#read 4, iclass 11, count 0 2006.257.02:51:25.93#ibcon#about to read 5, iclass 11, count 0 2006.257.02:51:25.93#ibcon#read 5, iclass 11, count 0 2006.257.02:51:25.93#ibcon#about to read 6, iclass 11, count 0 2006.257.02:51:25.93#ibcon#read 6, iclass 11, count 0 2006.257.02:51:25.93#ibcon#end of sib2, iclass 11, count 0 2006.257.02:51:25.93#ibcon#*after write, iclass 11, count 0 2006.257.02:51:25.93#ibcon#*before return 0, iclass 11, count 0 2006.257.02:51:25.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:25.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:25.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:51:25.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:51:25.93$vck44/valo=6,814.99 2006.257.02:51:25.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.02:51:25.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.02:51:25.93#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:25.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:25.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:25.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:25.93#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:51:25.93#ibcon#first serial, iclass 13, count 0 2006.257.02:51:25.93#ibcon#enter sib2, iclass 13, count 0 2006.257.02:51:25.93#ibcon#flushed, iclass 13, count 0 2006.257.02:51:25.93#ibcon#about to write, iclass 13, count 0 2006.257.02:51:25.93#ibcon#wrote, iclass 13, count 0 2006.257.02:51:25.93#ibcon#about to read 3, iclass 13, count 0 2006.257.02:51:25.95#ibcon#read 3, iclass 13, count 0 2006.257.02:51:25.95#ibcon#about to read 4, iclass 13, count 0 2006.257.02:51:25.95#ibcon#read 4, iclass 13, count 0 2006.257.02:51:25.95#ibcon#about to read 5, iclass 13, count 0 2006.257.02:51:25.95#ibcon#read 5, iclass 13, count 0 2006.257.02:51:25.95#ibcon#about to read 6, iclass 13, count 0 2006.257.02:51:25.95#ibcon#read 6, iclass 13, count 0 2006.257.02:51:25.95#ibcon#end of sib2, iclass 13, count 0 2006.257.02:51:25.95#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:51:25.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:51:25.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:51:25.95#ibcon#*before write, iclass 13, count 0 2006.257.02:51:25.95#ibcon#enter sib2, iclass 13, count 0 2006.257.02:51:25.95#ibcon#flushed, iclass 13, count 0 2006.257.02:51:25.95#ibcon#about to write, iclass 13, count 0 2006.257.02:51:25.95#ibcon#wrote, iclass 13, count 0 2006.257.02:51:25.95#ibcon#about to read 3, iclass 13, count 0 2006.257.02:51:25.99#ibcon#read 3, iclass 13, count 0 2006.257.02:51:25.99#ibcon#about to read 4, iclass 13, count 0 2006.257.02:51:25.99#ibcon#read 4, iclass 13, count 0 2006.257.02:51:25.99#ibcon#about to read 5, iclass 13, count 0 2006.257.02:51:25.99#ibcon#read 5, iclass 13, count 0 2006.257.02:51:25.99#ibcon#about to read 6, iclass 13, count 0 2006.257.02:51:25.99#ibcon#read 6, iclass 13, count 0 2006.257.02:51:25.99#ibcon#end of sib2, iclass 13, count 0 2006.257.02:51:25.99#ibcon#*after write, iclass 13, count 0 2006.257.02:51:25.99#ibcon#*before return 0, iclass 13, count 0 2006.257.02:51:25.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:25.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:25.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:51:25.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:51:25.99$vck44/va=6,4 2006.257.02:51:25.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.02:51:25.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.02:51:25.99#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:25.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:26.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:26.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:26.05#ibcon#enter wrdev, iclass 15, count 2 2006.257.02:51:26.05#ibcon#first serial, iclass 15, count 2 2006.257.02:51:26.05#ibcon#enter sib2, iclass 15, count 2 2006.257.02:51:26.05#ibcon#flushed, iclass 15, count 2 2006.257.02:51:26.05#ibcon#about to write, iclass 15, count 2 2006.257.02:51:26.05#ibcon#wrote, iclass 15, count 2 2006.257.02:51:26.05#ibcon#about to read 3, iclass 15, count 2 2006.257.02:51:26.07#ibcon#read 3, iclass 15, count 2 2006.257.02:51:26.07#ibcon#about to read 4, iclass 15, count 2 2006.257.02:51:26.07#ibcon#read 4, iclass 15, count 2 2006.257.02:51:26.07#ibcon#about to read 5, iclass 15, count 2 2006.257.02:51:26.07#ibcon#read 5, iclass 15, count 2 2006.257.02:51:26.07#ibcon#about to read 6, iclass 15, count 2 2006.257.02:51:26.07#ibcon#read 6, iclass 15, count 2 2006.257.02:51:26.07#ibcon#end of sib2, iclass 15, count 2 2006.257.02:51:26.07#ibcon#*mode == 0, iclass 15, count 2 2006.257.02:51:26.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.02:51:26.07#ibcon#[25=AT06-04\r\n] 2006.257.02:51:26.07#ibcon#*before write, iclass 15, count 2 2006.257.02:51:26.07#ibcon#enter sib2, iclass 15, count 2 2006.257.02:51:26.07#ibcon#flushed, iclass 15, count 2 2006.257.02:51:26.07#ibcon#about to write, iclass 15, count 2 2006.257.02:51:26.07#ibcon#wrote, iclass 15, count 2 2006.257.02:51:26.07#ibcon#about to read 3, iclass 15, count 2 2006.257.02:51:26.10#ibcon#read 3, iclass 15, count 2 2006.257.02:51:26.10#ibcon#about to read 4, iclass 15, count 2 2006.257.02:51:26.10#ibcon#read 4, iclass 15, count 2 2006.257.02:51:26.10#ibcon#about to read 5, iclass 15, count 2 2006.257.02:51:26.10#ibcon#read 5, iclass 15, count 2 2006.257.02:51:26.10#ibcon#about to read 6, iclass 15, count 2 2006.257.02:51:26.10#ibcon#read 6, iclass 15, count 2 2006.257.02:51:26.10#ibcon#end of sib2, iclass 15, count 2 2006.257.02:51:26.10#ibcon#*after write, iclass 15, count 2 2006.257.02:51:26.10#ibcon#*before return 0, iclass 15, count 2 2006.257.02:51:26.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:26.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:26.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.02:51:26.10#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:26.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:26.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:26.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:26.22#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:51:26.22#ibcon#first serial, iclass 15, count 0 2006.257.02:51:26.22#ibcon#enter sib2, iclass 15, count 0 2006.257.02:51:26.22#ibcon#flushed, iclass 15, count 0 2006.257.02:51:26.22#ibcon#about to write, iclass 15, count 0 2006.257.02:51:26.22#ibcon#wrote, iclass 15, count 0 2006.257.02:51:26.22#ibcon#about to read 3, iclass 15, count 0 2006.257.02:51:26.24#ibcon#read 3, iclass 15, count 0 2006.257.02:51:26.24#ibcon#about to read 4, iclass 15, count 0 2006.257.02:51:26.24#ibcon#read 4, iclass 15, count 0 2006.257.02:51:26.24#ibcon#about to read 5, iclass 15, count 0 2006.257.02:51:26.24#ibcon#read 5, iclass 15, count 0 2006.257.02:51:26.24#ibcon#about to read 6, iclass 15, count 0 2006.257.02:51:26.24#ibcon#read 6, iclass 15, count 0 2006.257.02:51:26.24#ibcon#end of sib2, iclass 15, count 0 2006.257.02:51:26.24#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:51:26.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:51:26.24#ibcon#[25=USB\r\n] 2006.257.02:51:26.24#ibcon#*before write, iclass 15, count 0 2006.257.02:51:26.24#ibcon#enter sib2, iclass 15, count 0 2006.257.02:51:26.24#ibcon#flushed, iclass 15, count 0 2006.257.02:51:26.24#ibcon#about to write, iclass 15, count 0 2006.257.02:51:26.24#ibcon#wrote, iclass 15, count 0 2006.257.02:51:26.24#ibcon#about to read 3, iclass 15, count 0 2006.257.02:51:26.27#ibcon#read 3, iclass 15, count 0 2006.257.02:51:26.27#ibcon#about to read 4, iclass 15, count 0 2006.257.02:51:26.27#ibcon#read 4, iclass 15, count 0 2006.257.02:51:26.27#ibcon#about to read 5, iclass 15, count 0 2006.257.02:51:26.27#ibcon#read 5, iclass 15, count 0 2006.257.02:51:26.27#ibcon#about to read 6, iclass 15, count 0 2006.257.02:51:26.27#ibcon#read 6, iclass 15, count 0 2006.257.02:51:26.27#ibcon#end of sib2, iclass 15, count 0 2006.257.02:51:26.27#ibcon#*after write, iclass 15, count 0 2006.257.02:51:26.27#ibcon#*before return 0, iclass 15, count 0 2006.257.02:51:26.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:26.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:26.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:51:26.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:51:26.27$vck44/valo=7,864.99 2006.257.02:51:26.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.02:51:26.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.02:51:26.27#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:26.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:26.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:26.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:26.27#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:51:26.27#ibcon#first serial, iclass 17, count 0 2006.257.02:51:26.27#ibcon#enter sib2, iclass 17, count 0 2006.257.02:51:26.27#ibcon#flushed, iclass 17, count 0 2006.257.02:51:26.27#ibcon#about to write, iclass 17, count 0 2006.257.02:51:26.27#ibcon#wrote, iclass 17, count 0 2006.257.02:51:26.27#ibcon#about to read 3, iclass 17, count 0 2006.257.02:51:26.29#ibcon#read 3, iclass 17, count 0 2006.257.02:51:26.29#ibcon#about to read 4, iclass 17, count 0 2006.257.02:51:26.29#ibcon#read 4, iclass 17, count 0 2006.257.02:51:26.29#ibcon#about to read 5, iclass 17, count 0 2006.257.02:51:26.29#ibcon#read 5, iclass 17, count 0 2006.257.02:51:26.29#ibcon#about to read 6, iclass 17, count 0 2006.257.02:51:26.29#ibcon#read 6, iclass 17, count 0 2006.257.02:51:26.29#ibcon#end of sib2, iclass 17, count 0 2006.257.02:51:26.29#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:51:26.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:51:26.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:51:26.29#ibcon#*before write, iclass 17, count 0 2006.257.02:51:26.29#ibcon#enter sib2, iclass 17, count 0 2006.257.02:51:26.29#ibcon#flushed, iclass 17, count 0 2006.257.02:51:26.29#ibcon#about to write, iclass 17, count 0 2006.257.02:51:26.29#ibcon#wrote, iclass 17, count 0 2006.257.02:51:26.29#ibcon#about to read 3, iclass 17, count 0 2006.257.02:51:26.33#ibcon#read 3, iclass 17, count 0 2006.257.02:51:26.33#ibcon#about to read 4, iclass 17, count 0 2006.257.02:51:26.33#ibcon#read 4, iclass 17, count 0 2006.257.02:51:26.33#ibcon#about to read 5, iclass 17, count 0 2006.257.02:51:26.33#ibcon#read 5, iclass 17, count 0 2006.257.02:51:26.33#ibcon#about to read 6, iclass 17, count 0 2006.257.02:51:26.33#ibcon#read 6, iclass 17, count 0 2006.257.02:51:26.33#ibcon#end of sib2, iclass 17, count 0 2006.257.02:51:26.33#ibcon#*after write, iclass 17, count 0 2006.257.02:51:26.33#ibcon#*before return 0, iclass 17, count 0 2006.257.02:51:26.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:26.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:26.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:51:26.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:51:26.33$vck44/va=7,4 2006.257.02:51:26.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.02:51:26.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.02:51:26.33#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:26.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:26.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:26.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:26.39#ibcon#enter wrdev, iclass 19, count 2 2006.257.02:51:26.39#ibcon#first serial, iclass 19, count 2 2006.257.02:51:26.39#ibcon#enter sib2, iclass 19, count 2 2006.257.02:51:26.39#ibcon#flushed, iclass 19, count 2 2006.257.02:51:26.39#ibcon#about to write, iclass 19, count 2 2006.257.02:51:26.39#ibcon#wrote, iclass 19, count 2 2006.257.02:51:26.39#ibcon#about to read 3, iclass 19, count 2 2006.257.02:51:26.41#ibcon#read 3, iclass 19, count 2 2006.257.02:51:26.41#ibcon#about to read 4, iclass 19, count 2 2006.257.02:51:26.41#ibcon#read 4, iclass 19, count 2 2006.257.02:51:26.41#ibcon#about to read 5, iclass 19, count 2 2006.257.02:51:26.41#ibcon#read 5, iclass 19, count 2 2006.257.02:51:26.41#ibcon#about to read 6, iclass 19, count 2 2006.257.02:51:26.41#ibcon#read 6, iclass 19, count 2 2006.257.02:51:26.41#ibcon#end of sib2, iclass 19, count 2 2006.257.02:51:26.41#ibcon#*mode == 0, iclass 19, count 2 2006.257.02:51:26.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.02:51:26.41#ibcon#[25=AT07-04\r\n] 2006.257.02:51:26.41#ibcon#*before write, iclass 19, count 2 2006.257.02:51:26.41#ibcon#enter sib2, iclass 19, count 2 2006.257.02:51:26.41#ibcon#flushed, iclass 19, count 2 2006.257.02:51:26.41#ibcon#about to write, iclass 19, count 2 2006.257.02:51:26.41#ibcon#wrote, iclass 19, count 2 2006.257.02:51:26.41#ibcon#about to read 3, iclass 19, count 2 2006.257.02:51:26.44#ibcon#read 3, iclass 19, count 2 2006.257.02:51:26.44#ibcon#about to read 4, iclass 19, count 2 2006.257.02:51:26.44#ibcon#read 4, iclass 19, count 2 2006.257.02:51:26.44#ibcon#about to read 5, iclass 19, count 2 2006.257.02:51:26.44#ibcon#read 5, iclass 19, count 2 2006.257.02:51:26.44#ibcon#about to read 6, iclass 19, count 2 2006.257.02:51:26.44#ibcon#read 6, iclass 19, count 2 2006.257.02:51:26.44#ibcon#end of sib2, iclass 19, count 2 2006.257.02:51:26.44#ibcon#*after write, iclass 19, count 2 2006.257.02:51:26.44#ibcon#*before return 0, iclass 19, count 2 2006.257.02:51:26.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:26.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:26.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.02:51:26.44#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:26.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:26.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:26.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:26.56#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:51:26.56#ibcon#first serial, iclass 19, count 0 2006.257.02:51:26.56#ibcon#enter sib2, iclass 19, count 0 2006.257.02:51:26.56#ibcon#flushed, iclass 19, count 0 2006.257.02:51:26.56#ibcon#about to write, iclass 19, count 0 2006.257.02:51:26.56#ibcon#wrote, iclass 19, count 0 2006.257.02:51:26.56#ibcon#about to read 3, iclass 19, count 0 2006.257.02:51:26.58#ibcon#read 3, iclass 19, count 0 2006.257.02:51:26.58#ibcon#about to read 4, iclass 19, count 0 2006.257.02:51:26.58#ibcon#read 4, iclass 19, count 0 2006.257.02:51:26.58#ibcon#about to read 5, iclass 19, count 0 2006.257.02:51:26.58#ibcon#read 5, iclass 19, count 0 2006.257.02:51:26.58#ibcon#about to read 6, iclass 19, count 0 2006.257.02:51:26.58#ibcon#read 6, iclass 19, count 0 2006.257.02:51:26.58#ibcon#end of sib2, iclass 19, count 0 2006.257.02:51:26.58#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:51:26.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:51:26.58#ibcon#[25=USB\r\n] 2006.257.02:51:26.58#ibcon#*before write, iclass 19, count 0 2006.257.02:51:26.58#ibcon#enter sib2, iclass 19, count 0 2006.257.02:51:26.58#ibcon#flushed, iclass 19, count 0 2006.257.02:51:26.58#ibcon#about to write, iclass 19, count 0 2006.257.02:51:26.58#ibcon#wrote, iclass 19, count 0 2006.257.02:51:26.58#ibcon#about to read 3, iclass 19, count 0 2006.257.02:51:26.61#ibcon#read 3, iclass 19, count 0 2006.257.02:51:26.61#ibcon#about to read 4, iclass 19, count 0 2006.257.02:51:26.61#ibcon#read 4, iclass 19, count 0 2006.257.02:51:26.61#ibcon#about to read 5, iclass 19, count 0 2006.257.02:51:26.61#ibcon#read 5, iclass 19, count 0 2006.257.02:51:26.61#ibcon#about to read 6, iclass 19, count 0 2006.257.02:51:26.61#ibcon#read 6, iclass 19, count 0 2006.257.02:51:26.61#ibcon#end of sib2, iclass 19, count 0 2006.257.02:51:26.61#ibcon#*after write, iclass 19, count 0 2006.257.02:51:26.61#ibcon#*before return 0, iclass 19, count 0 2006.257.02:51:26.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:26.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:26.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:51:26.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:51:26.61$vck44/valo=8,884.99 2006.257.02:51:26.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.02:51:26.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.02:51:26.61#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:26.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:26.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:26.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:26.61#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:51:26.61#ibcon#first serial, iclass 21, count 0 2006.257.02:51:26.61#ibcon#enter sib2, iclass 21, count 0 2006.257.02:51:26.61#ibcon#flushed, iclass 21, count 0 2006.257.02:51:26.61#ibcon#about to write, iclass 21, count 0 2006.257.02:51:26.61#ibcon#wrote, iclass 21, count 0 2006.257.02:51:26.61#ibcon#about to read 3, iclass 21, count 0 2006.257.02:51:26.63#ibcon#read 3, iclass 21, count 0 2006.257.02:51:26.63#ibcon#about to read 4, iclass 21, count 0 2006.257.02:51:26.63#ibcon#read 4, iclass 21, count 0 2006.257.02:51:26.63#ibcon#about to read 5, iclass 21, count 0 2006.257.02:51:26.63#ibcon#read 5, iclass 21, count 0 2006.257.02:51:26.63#ibcon#about to read 6, iclass 21, count 0 2006.257.02:51:26.63#ibcon#read 6, iclass 21, count 0 2006.257.02:51:26.63#ibcon#end of sib2, iclass 21, count 0 2006.257.02:51:26.63#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:51:26.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:51:26.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:51:26.63#ibcon#*before write, iclass 21, count 0 2006.257.02:51:26.63#ibcon#enter sib2, iclass 21, count 0 2006.257.02:51:26.63#ibcon#flushed, iclass 21, count 0 2006.257.02:51:26.63#ibcon#about to write, iclass 21, count 0 2006.257.02:51:26.63#ibcon#wrote, iclass 21, count 0 2006.257.02:51:26.63#ibcon#about to read 3, iclass 21, count 0 2006.257.02:51:26.67#ibcon#read 3, iclass 21, count 0 2006.257.02:51:26.67#ibcon#about to read 4, iclass 21, count 0 2006.257.02:51:26.67#ibcon#read 4, iclass 21, count 0 2006.257.02:51:26.67#ibcon#about to read 5, iclass 21, count 0 2006.257.02:51:26.67#ibcon#read 5, iclass 21, count 0 2006.257.02:51:26.67#ibcon#about to read 6, iclass 21, count 0 2006.257.02:51:26.67#ibcon#read 6, iclass 21, count 0 2006.257.02:51:26.67#ibcon#end of sib2, iclass 21, count 0 2006.257.02:51:26.67#ibcon#*after write, iclass 21, count 0 2006.257.02:51:26.67#ibcon#*before return 0, iclass 21, count 0 2006.257.02:51:26.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:26.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:26.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:51:26.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:51:26.67$vck44/va=8,4 2006.257.02:51:26.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.02:51:26.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.02:51:26.67#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:26.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:51:26.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:51:26.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:51:26.73#ibcon#enter wrdev, iclass 23, count 2 2006.257.02:51:26.73#ibcon#first serial, iclass 23, count 2 2006.257.02:51:26.73#ibcon#enter sib2, iclass 23, count 2 2006.257.02:51:26.73#ibcon#flushed, iclass 23, count 2 2006.257.02:51:26.73#ibcon#about to write, iclass 23, count 2 2006.257.02:51:26.73#ibcon#wrote, iclass 23, count 2 2006.257.02:51:26.73#ibcon#about to read 3, iclass 23, count 2 2006.257.02:51:26.75#ibcon#read 3, iclass 23, count 2 2006.257.02:51:26.75#ibcon#about to read 4, iclass 23, count 2 2006.257.02:51:26.75#ibcon#read 4, iclass 23, count 2 2006.257.02:51:26.75#ibcon#about to read 5, iclass 23, count 2 2006.257.02:51:26.75#ibcon#read 5, iclass 23, count 2 2006.257.02:51:26.75#ibcon#about to read 6, iclass 23, count 2 2006.257.02:51:26.75#ibcon#read 6, iclass 23, count 2 2006.257.02:51:26.75#ibcon#end of sib2, iclass 23, count 2 2006.257.02:51:26.75#ibcon#*mode == 0, iclass 23, count 2 2006.257.02:51:26.75#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.02:51:26.75#ibcon#[25=AT08-04\r\n] 2006.257.02:51:26.75#ibcon#*before write, iclass 23, count 2 2006.257.02:51:26.75#ibcon#enter sib2, iclass 23, count 2 2006.257.02:51:26.75#ibcon#flushed, iclass 23, count 2 2006.257.02:51:26.75#ibcon#about to write, iclass 23, count 2 2006.257.02:51:26.75#ibcon#wrote, iclass 23, count 2 2006.257.02:51:26.75#ibcon#about to read 3, iclass 23, count 2 2006.257.02:51:26.78#ibcon#read 3, iclass 23, count 2 2006.257.02:51:26.78#ibcon#about to read 4, iclass 23, count 2 2006.257.02:51:26.78#ibcon#read 4, iclass 23, count 2 2006.257.02:51:26.78#ibcon#about to read 5, iclass 23, count 2 2006.257.02:51:26.78#ibcon#read 5, iclass 23, count 2 2006.257.02:51:26.78#ibcon#about to read 6, iclass 23, count 2 2006.257.02:51:26.78#ibcon#read 6, iclass 23, count 2 2006.257.02:51:26.78#ibcon#end of sib2, iclass 23, count 2 2006.257.02:51:26.78#ibcon#*after write, iclass 23, count 2 2006.257.02:51:26.78#ibcon#*before return 0, iclass 23, count 2 2006.257.02:51:26.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:51:26.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.02:51:26.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.02:51:26.78#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:26.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:51:26.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:51:26.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:51:26.90#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:51:26.90#ibcon#first serial, iclass 23, count 0 2006.257.02:51:26.90#ibcon#enter sib2, iclass 23, count 0 2006.257.02:51:26.90#ibcon#flushed, iclass 23, count 0 2006.257.02:51:26.90#ibcon#about to write, iclass 23, count 0 2006.257.02:51:26.90#ibcon#wrote, iclass 23, count 0 2006.257.02:51:26.90#ibcon#about to read 3, iclass 23, count 0 2006.257.02:51:26.92#ibcon#read 3, iclass 23, count 0 2006.257.02:51:26.92#ibcon#about to read 4, iclass 23, count 0 2006.257.02:51:26.92#ibcon#read 4, iclass 23, count 0 2006.257.02:51:26.92#ibcon#about to read 5, iclass 23, count 0 2006.257.02:51:26.92#ibcon#read 5, iclass 23, count 0 2006.257.02:51:26.92#ibcon#about to read 6, iclass 23, count 0 2006.257.02:51:26.92#ibcon#read 6, iclass 23, count 0 2006.257.02:51:26.92#ibcon#end of sib2, iclass 23, count 0 2006.257.02:51:26.92#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:51:26.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:51:26.92#ibcon#[25=USB\r\n] 2006.257.02:51:26.92#ibcon#*before write, iclass 23, count 0 2006.257.02:51:26.92#ibcon#enter sib2, iclass 23, count 0 2006.257.02:51:26.92#ibcon#flushed, iclass 23, count 0 2006.257.02:51:26.92#ibcon#about to write, iclass 23, count 0 2006.257.02:51:26.92#ibcon#wrote, iclass 23, count 0 2006.257.02:51:26.92#ibcon#about to read 3, iclass 23, count 0 2006.257.02:51:26.95#ibcon#read 3, iclass 23, count 0 2006.257.02:51:26.95#ibcon#about to read 4, iclass 23, count 0 2006.257.02:51:26.95#ibcon#read 4, iclass 23, count 0 2006.257.02:51:26.95#ibcon#about to read 5, iclass 23, count 0 2006.257.02:51:26.95#ibcon#read 5, iclass 23, count 0 2006.257.02:51:26.95#ibcon#about to read 6, iclass 23, count 0 2006.257.02:51:26.95#ibcon#read 6, iclass 23, count 0 2006.257.02:51:26.95#ibcon#end of sib2, iclass 23, count 0 2006.257.02:51:26.95#ibcon#*after write, iclass 23, count 0 2006.257.02:51:26.95#ibcon#*before return 0, iclass 23, count 0 2006.257.02:51:26.95#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:51:26.95#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.02:51:26.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:51:26.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:51:26.95$vck44/vblo=1,629.99 2006.257.02:51:26.95#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.02:51:26.95#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.02:51:26.95#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:26.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:51:26.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:51:26.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:51:26.95#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:51:26.95#ibcon#first serial, iclass 25, count 0 2006.257.02:51:26.95#ibcon#enter sib2, iclass 25, count 0 2006.257.02:51:26.95#ibcon#flushed, iclass 25, count 0 2006.257.02:51:26.95#ibcon#about to write, iclass 25, count 0 2006.257.02:51:26.95#ibcon#wrote, iclass 25, count 0 2006.257.02:51:26.95#ibcon#about to read 3, iclass 25, count 0 2006.257.02:51:26.97#ibcon#read 3, iclass 25, count 0 2006.257.02:51:26.97#ibcon#about to read 4, iclass 25, count 0 2006.257.02:51:26.97#ibcon#read 4, iclass 25, count 0 2006.257.02:51:26.97#ibcon#about to read 5, iclass 25, count 0 2006.257.02:51:26.97#ibcon#read 5, iclass 25, count 0 2006.257.02:51:26.97#ibcon#about to read 6, iclass 25, count 0 2006.257.02:51:26.97#ibcon#read 6, iclass 25, count 0 2006.257.02:51:26.97#ibcon#end of sib2, iclass 25, count 0 2006.257.02:51:26.97#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:51:26.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:51:26.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:51:26.97#ibcon#*before write, iclass 25, count 0 2006.257.02:51:26.97#ibcon#enter sib2, iclass 25, count 0 2006.257.02:51:26.97#ibcon#flushed, iclass 25, count 0 2006.257.02:51:26.97#ibcon#about to write, iclass 25, count 0 2006.257.02:51:26.97#ibcon#wrote, iclass 25, count 0 2006.257.02:51:26.97#ibcon#about to read 3, iclass 25, count 0 2006.257.02:51:27.01#ibcon#read 3, iclass 25, count 0 2006.257.02:51:27.01#ibcon#about to read 4, iclass 25, count 0 2006.257.02:51:27.01#ibcon#read 4, iclass 25, count 0 2006.257.02:51:27.01#ibcon#about to read 5, iclass 25, count 0 2006.257.02:51:27.01#ibcon#read 5, iclass 25, count 0 2006.257.02:51:27.01#ibcon#about to read 6, iclass 25, count 0 2006.257.02:51:27.01#ibcon#read 6, iclass 25, count 0 2006.257.02:51:27.01#ibcon#end of sib2, iclass 25, count 0 2006.257.02:51:27.01#ibcon#*after write, iclass 25, count 0 2006.257.02:51:27.01#ibcon#*before return 0, iclass 25, count 0 2006.257.02:51:27.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:51:27.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.02:51:27.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:51:27.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:51:27.01$vck44/vb=1,4 2006.257.02:51:27.01#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.02:51:27.01#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.02:51:27.01#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:27.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:51:27.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:51:27.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:51:27.01#ibcon#enter wrdev, iclass 27, count 2 2006.257.02:51:27.01#ibcon#first serial, iclass 27, count 2 2006.257.02:51:27.01#ibcon#enter sib2, iclass 27, count 2 2006.257.02:51:27.01#ibcon#flushed, iclass 27, count 2 2006.257.02:51:27.01#ibcon#about to write, iclass 27, count 2 2006.257.02:51:27.01#ibcon#wrote, iclass 27, count 2 2006.257.02:51:27.01#ibcon#about to read 3, iclass 27, count 2 2006.257.02:51:27.03#ibcon#read 3, iclass 27, count 2 2006.257.02:51:27.03#ibcon#about to read 4, iclass 27, count 2 2006.257.02:51:27.03#ibcon#read 4, iclass 27, count 2 2006.257.02:51:27.03#ibcon#about to read 5, iclass 27, count 2 2006.257.02:51:27.03#ibcon#read 5, iclass 27, count 2 2006.257.02:51:27.03#ibcon#about to read 6, iclass 27, count 2 2006.257.02:51:27.03#ibcon#read 6, iclass 27, count 2 2006.257.02:51:27.03#ibcon#end of sib2, iclass 27, count 2 2006.257.02:51:27.03#ibcon#*mode == 0, iclass 27, count 2 2006.257.02:51:27.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.02:51:27.03#ibcon#[27=AT01-04\r\n] 2006.257.02:51:27.03#ibcon#*before write, iclass 27, count 2 2006.257.02:51:27.03#ibcon#enter sib2, iclass 27, count 2 2006.257.02:51:27.03#ibcon#flushed, iclass 27, count 2 2006.257.02:51:27.03#ibcon#about to write, iclass 27, count 2 2006.257.02:51:27.03#ibcon#wrote, iclass 27, count 2 2006.257.02:51:27.03#ibcon#about to read 3, iclass 27, count 2 2006.257.02:51:27.06#ibcon#read 3, iclass 27, count 2 2006.257.02:51:27.06#ibcon#about to read 4, iclass 27, count 2 2006.257.02:51:27.06#ibcon#read 4, iclass 27, count 2 2006.257.02:51:27.06#ibcon#about to read 5, iclass 27, count 2 2006.257.02:51:27.06#ibcon#read 5, iclass 27, count 2 2006.257.02:51:27.06#ibcon#about to read 6, iclass 27, count 2 2006.257.02:51:27.06#ibcon#read 6, iclass 27, count 2 2006.257.02:51:27.06#ibcon#end of sib2, iclass 27, count 2 2006.257.02:51:27.06#ibcon#*after write, iclass 27, count 2 2006.257.02:51:27.06#ibcon#*before return 0, iclass 27, count 2 2006.257.02:51:27.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:51:27.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.02:51:27.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.02:51:27.06#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:27.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:51:27.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:51:27.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:51:27.18#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:51:27.18#ibcon#first serial, iclass 27, count 0 2006.257.02:51:27.18#ibcon#enter sib2, iclass 27, count 0 2006.257.02:51:27.18#ibcon#flushed, iclass 27, count 0 2006.257.02:51:27.18#ibcon#about to write, iclass 27, count 0 2006.257.02:51:27.18#ibcon#wrote, iclass 27, count 0 2006.257.02:51:27.18#ibcon#about to read 3, iclass 27, count 0 2006.257.02:51:27.20#ibcon#read 3, iclass 27, count 0 2006.257.02:51:27.20#ibcon#about to read 4, iclass 27, count 0 2006.257.02:51:27.20#ibcon#read 4, iclass 27, count 0 2006.257.02:51:27.20#ibcon#about to read 5, iclass 27, count 0 2006.257.02:51:27.20#ibcon#read 5, iclass 27, count 0 2006.257.02:51:27.20#ibcon#about to read 6, iclass 27, count 0 2006.257.02:51:27.20#ibcon#read 6, iclass 27, count 0 2006.257.02:51:27.20#ibcon#end of sib2, iclass 27, count 0 2006.257.02:51:27.20#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:51:27.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:51:27.20#ibcon#[27=USB\r\n] 2006.257.02:51:27.20#ibcon#*before write, iclass 27, count 0 2006.257.02:51:27.20#ibcon#enter sib2, iclass 27, count 0 2006.257.02:51:27.20#ibcon#flushed, iclass 27, count 0 2006.257.02:51:27.20#ibcon#about to write, iclass 27, count 0 2006.257.02:51:27.20#ibcon#wrote, iclass 27, count 0 2006.257.02:51:27.20#ibcon#about to read 3, iclass 27, count 0 2006.257.02:51:27.23#ibcon#read 3, iclass 27, count 0 2006.257.02:51:27.23#ibcon#about to read 4, iclass 27, count 0 2006.257.02:51:27.23#ibcon#read 4, iclass 27, count 0 2006.257.02:51:27.23#ibcon#about to read 5, iclass 27, count 0 2006.257.02:51:27.23#ibcon#read 5, iclass 27, count 0 2006.257.02:51:27.23#ibcon#about to read 6, iclass 27, count 0 2006.257.02:51:27.23#ibcon#read 6, iclass 27, count 0 2006.257.02:51:27.23#ibcon#end of sib2, iclass 27, count 0 2006.257.02:51:27.23#ibcon#*after write, iclass 27, count 0 2006.257.02:51:27.23#ibcon#*before return 0, iclass 27, count 0 2006.257.02:51:27.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:51:27.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.02:51:27.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:51:27.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:51:27.23$vck44/vblo=2,634.99 2006.257.02:51:27.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.02:51:27.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.02:51:27.23#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:27.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:27.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:27.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:27.23#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:51:27.23#ibcon#first serial, iclass 29, count 0 2006.257.02:51:27.23#ibcon#enter sib2, iclass 29, count 0 2006.257.02:51:27.23#ibcon#flushed, iclass 29, count 0 2006.257.02:51:27.23#ibcon#about to write, iclass 29, count 0 2006.257.02:51:27.23#ibcon#wrote, iclass 29, count 0 2006.257.02:51:27.23#ibcon#about to read 3, iclass 29, count 0 2006.257.02:51:27.25#ibcon#read 3, iclass 29, count 0 2006.257.02:51:27.25#ibcon#about to read 4, iclass 29, count 0 2006.257.02:51:27.25#ibcon#read 4, iclass 29, count 0 2006.257.02:51:27.25#ibcon#about to read 5, iclass 29, count 0 2006.257.02:51:27.25#ibcon#read 5, iclass 29, count 0 2006.257.02:51:27.25#ibcon#about to read 6, iclass 29, count 0 2006.257.02:51:27.25#ibcon#read 6, iclass 29, count 0 2006.257.02:51:27.25#ibcon#end of sib2, iclass 29, count 0 2006.257.02:51:27.25#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:51:27.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:51:27.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:51:27.25#ibcon#*before write, iclass 29, count 0 2006.257.02:51:27.25#ibcon#enter sib2, iclass 29, count 0 2006.257.02:51:27.25#ibcon#flushed, iclass 29, count 0 2006.257.02:51:27.25#ibcon#about to write, iclass 29, count 0 2006.257.02:51:27.25#ibcon#wrote, iclass 29, count 0 2006.257.02:51:27.25#ibcon#about to read 3, iclass 29, count 0 2006.257.02:51:27.29#ibcon#read 3, iclass 29, count 0 2006.257.02:51:27.29#ibcon#about to read 4, iclass 29, count 0 2006.257.02:51:27.29#ibcon#read 4, iclass 29, count 0 2006.257.02:51:27.29#ibcon#about to read 5, iclass 29, count 0 2006.257.02:51:27.29#ibcon#read 5, iclass 29, count 0 2006.257.02:51:27.29#ibcon#about to read 6, iclass 29, count 0 2006.257.02:51:27.29#ibcon#read 6, iclass 29, count 0 2006.257.02:51:27.29#ibcon#end of sib2, iclass 29, count 0 2006.257.02:51:27.29#ibcon#*after write, iclass 29, count 0 2006.257.02:51:27.29#ibcon#*before return 0, iclass 29, count 0 2006.257.02:51:27.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:27.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.02:51:27.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:51:27.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:51:27.29$vck44/vb=2,5 2006.257.02:51:27.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.02:51:27.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.02:51:27.29#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:27.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:27.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:27.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:27.35#ibcon#enter wrdev, iclass 31, count 2 2006.257.02:51:27.35#ibcon#first serial, iclass 31, count 2 2006.257.02:51:27.35#ibcon#enter sib2, iclass 31, count 2 2006.257.02:51:27.35#ibcon#flushed, iclass 31, count 2 2006.257.02:51:27.35#ibcon#about to write, iclass 31, count 2 2006.257.02:51:27.35#ibcon#wrote, iclass 31, count 2 2006.257.02:51:27.35#ibcon#about to read 3, iclass 31, count 2 2006.257.02:51:27.37#ibcon#read 3, iclass 31, count 2 2006.257.02:51:27.37#ibcon#about to read 4, iclass 31, count 2 2006.257.02:51:27.37#ibcon#read 4, iclass 31, count 2 2006.257.02:51:27.37#ibcon#about to read 5, iclass 31, count 2 2006.257.02:51:27.37#ibcon#read 5, iclass 31, count 2 2006.257.02:51:27.37#ibcon#about to read 6, iclass 31, count 2 2006.257.02:51:27.37#ibcon#read 6, iclass 31, count 2 2006.257.02:51:27.37#ibcon#end of sib2, iclass 31, count 2 2006.257.02:51:27.37#ibcon#*mode == 0, iclass 31, count 2 2006.257.02:51:27.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.02:51:27.37#ibcon#[27=AT02-05\r\n] 2006.257.02:51:27.37#ibcon#*before write, iclass 31, count 2 2006.257.02:51:27.37#ibcon#enter sib2, iclass 31, count 2 2006.257.02:51:27.37#ibcon#flushed, iclass 31, count 2 2006.257.02:51:27.37#ibcon#about to write, iclass 31, count 2 2006.257.02:51:27.37#ibcon#wrote, iclass 31, count 2 2006.257.02:51:27.37#ibcon#about to read 3, iclass 31, count 2 2006.257.02:51:27.40#ibcon#read 3, iclass 31, count 2 2006.257.02:51:27.40#ibcon#about to read 4, iclass 31, count 2 2006.257.02:51:27.40#ibcon#read 4, iclass 31, count 2 2006.257.02:51:27.40#ibcon#about to read 5, iclass 31, count 2 2006.257.02:51:27.40#ibcon#read 5, iclass 31, count 2 2006.257.02:51:27.40#ibcon#about to read 6, iclass 31, count 2 2006.257.02:51:27.40#ibcon#read 6, iclass 31, count 2 2006.257.02:51:27.40#ibcon#end of sib2, iclass 31, count 2 2006.257.02:51:27.40#ibcon#*after write, iclass 31, count 2 2006.257.02:51:27.40#ibcon#*before return 0, iclass 31, count 2 2006.257.02:51:27.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:27.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.02:51:27.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.02:51:27.40#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:27.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:27.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:27.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:27.52#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:51:27.52#ibcon#first serial, iclass 31, count 0 2006.257.02:51:27.52#ibcon#enter sib2, iclass 31, count 0 2006.257.02:51:27.52#ibcon#flushed, iclass 31, count 0 2006.257.02:51:27.52#ibcon#about to write, iclass 31, count 0 2006.257.02:51:27.52#ibcon#wrote, iclass 31, count 0 2006.257.02:51:27.52#ibcon#about to read 3, iclass 31, count 0 2006.257.02:51:27.54#ibcon#read 3, iclass 31, count 0 2006.257.02:51:27.54#ibcon#about to read 4, iclass 31, count 0 2006.257.02:51:27.54#ibcon#read 4, iclass 31, count 0 2006.257.02:51:27.54#ibcon#about to read 5, iclass 31, count 0 2006.257.02:51:27.54#ibcon#read 5, iclass 31, count 0 2006.257.02:51:27.54#ibcon#about to read 6, iclass 31, count 0 2006.257.02:51:27.54#ibcon#read 6, iclass 31, count 0 2006.257.02:51:27.54#ibcon#end of sib2, iclass 31, count 0 2006.257.02:51:27.54#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:51:27.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:51:27.54#ibcon#[27=USB\r\n] 2006.257.02:51:27.54#ibcon#*before write, iclass 31, count 0 2006.257.02:51:27.54#ibcon#enter sib2, iclass 31, count 0 2006.257.02:51:27.54#ibcon#flushed, iclass 31, count 0 2006.257.02:51:27.54#ibcon#about to write, iclass 31, count 0 2006.257.02:51:27.54#ibcon#wrote, iclass 31, count 0 2006.257.02:51:27.54#ibcon#about to read 3, iclass 31, count 0 2006.257.02:51:27.57#ibcon#read 3, iclass 31, count 0 2006.257.02:51:27.57#ibcon#about to read 4, iclass 31, count 0 2006.257.02:51:27.57#ibcon#read 4, iclass 31, count 0 2006.257.02:51:27.57#ibcon#about to read 5, iclass 31, count 0 2006.257.02:51:27.57#ibcon#read 5, iclass 31, count 0 2006.257.02:51:27.57#ibcon#about to read 6, iclass 31, count 0 2006.257.02:51:27.57#ibcon#read 6, iclass 31, count 0 2006.257.02:51:27.57#ibcon#end of sib2, iclass 31, count 0 2006.257.02:51:27.57#ibcon#*after write, iclass 31, count 0 2006.257.02:51:27.57#ibcon#*before return 0, iclass 31, count 0 2006.257.02:51:27.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:27.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.02:51:27.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:51:27.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:51:27.57$vck44/vblo=3,649.99 2006.257.02:51:27.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.02:51:27.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.02:51:27.57#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:27.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:27.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:27.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:27.57#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:51:27.57#ibcon#first serial, iclass 33, count 0 2006.257.02:51:27.57#ibcon#enter sib2, iclass 33, count 0 2006.257.02:51:27.57#ibcon#flushed, iclass 33, count 0 2006.257.02:51:27.57#ibcon#about to write, iclass 33, count 0 2006.257.02:51:27.57#ibcon#wrote, iclass 33, count 0 2006.257.02:51:27.57#ibcon#about to read 3, iclass 33, count 0 2006.257.02:51:27.59#ibcon#read 3, iclass 33, count 0 2006.257.02:51:27.59#ibcon#about to read 4, iclass 33, count 0 2006.257.02:51:27.59#ibcon#read 4, iclass 33, count 0 2006.257.02:51:27.59#ibcon#about to read 5, iclass 33, count 0 2006.257.02:51:27.59#ibcon#read 5, iclass 33, count 0 2006.257.02:51:27.59#ibcon#about to read 6, iclass 33, count 0 2006.257.02:51:27.59#ibcon#read 6, iclass 33, count 0 2006.257.02:51:27.59#ibcon#end of sib2, iclass 33, count 0 2006.257.02:51:27.59#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:51:27.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:51:27.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:51:27.59#ibcon#*before write, iclass 33, count 0 2006.257.02:51:27.59#ibcon#enter sib2, iclass 33, count 0 2006.257.02:51:27.59#ibcon#flushed, iclass 33, count 0 2006.257.02:51:27.59#ibcon#about to write, iclass 33, count 0 2006.257.02:51:27.59#ibcon#wrote, iclass 33, count 0 2006.257.02:51:27.59#ibcon#about to read 3, iclass 33, count 0 2006.257.02:51:27.63#ibcon#read 3, iclass 33, count 0 2006.257.02:51:27.63#ibcon#about to read 4, iclass 33, count 0 2006.257.02:51:27.63#ibcon#read 4, iclass 33, count 0 2006.257.02:51:27.63#ibcon#about to read 5, iclass 33, count 0 2006.257.02:51:27.63#ibcon#read 5, iclass 33, count 0 2006.257.02:51:27.63#ibcon#about to read 6, iclass 33, count 0 2006.257.02:51:27.63#ibcon#read 6, iclass 33, count 0 2006.257.02:51:27.63#ibcon#end of sib2, iclass 33, count 0 2006.257.02:51:27.63#ibcon#*after write, iclass 33, count 0 2006.257.02:51:27.63#ibcon#*before return 0, iclass 33, count 0 2006.257.02:51:27.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:27.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.02:51:27.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:51:27.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:51:27.63$vck44/vb=3,4 2006.257.02:51:27.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.02:51:27.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.02:51:27.63#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:27.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:27.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:27.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:27.69#ibcon#enter wrdev, iclass 35, count 2 2006.257.02:51:27.69#ibcon#first serial, iclass 35, count 2 2006.257.02:51:27.69#ibcon#enter sib2, iclass 35, count 2 2006.257.02:51:27.69#ibcon#flushed, iclass 35, count 2 2006.257.02:51:27.69#ibcon#about to write, iclass 35, count 2 2006.257.02:51:27.69#ibcon#wrote, iclass 35, count 2 2006.257.02:51:27.69#ibcon#about to read 3, iclass 35, count 2 2006.257.02:51:27.71#ibcon#read 3, iclass 35, count 2 2006.257.02:51:27.71#ibcon#about to read 4, iclass 35, count 2 2006.257.02:51:27.71#ibcon#read 4, iclass 35, count 2 2006.257.02:51:27.71#ibcon#about to read 5, iclass 35, count 2 2006.257.02:51:27.71#ibcon#read 5, iclass 35, count 2 2006.257.02:51:27.71#ibcon#about to read 6, iclass 35, count 2 2006.257.02:51:27.71#ibcon#read 6, iclass 35, count 2 2006.257.02:51:27.71#ibcon#end of sib2, iclass 35, count 2 2006.257.02:51:27.71#ibcon#*mode == 0, iclass 35, count 2 2006.257.02:51:27.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.02:51:27.71#ibcon#[27=AT03-04\r\n] 2006.257.02:51:27.71#ibcon#*before write, iclass 35, count 2 2006.257.02:51:27.71#ibcon#enter sib2, iclass 35, count 2 2006.257.02:51:27.71#ibcon#flushed, iclass 35, count 2 2006.257.02:51:27.71#ibcon#about to write, iclass 35, count 2 2006.257.02:51:27.71#ibcon#wrote, iclass 35, count 2 2006.257.02:51:27.71#ibcon#about to read 3, iclass 35, count 2 2006.257.02:51:27.74#ibcon#read 3, iclass 35, count 2 2006.257.02:51:27.74#ibcon#about to read 4, iclass 35, count 2 2006.257.02:51:27.74#ibcon#read 4, iclass 35, count 2 2006.257.02:51:27.74#ibcon#about to read 5, iclass 35, count 2 2006.257.02:51:27.74#ibcon#read 5, iclass 35, count 2 2006.257.02:51:27.74#ibcon#about to read 6, iclass 35, count 2 2006.257.02:51:27.74#ibcon#read 6, iclass 35, count 2 2006.257.02:51:27.74#ibcon#end of sib2, iclass 35, count 2 2006.257.02:51:27.74#ibcon#*after write, iclass 35, count 2 2006.257.02:51:27.74#ibcon#*before return 0, iclass 35, count 2 2006.257.02:51:27.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:27.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.02:51:27.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.02:51:27.74#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:27.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:27.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:27.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:27.86#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:51:27.86#ibcon#first serial, iclass 35, count 0 2006.257.02:51:27.86#ibcon#enter sib2, iclass 35, count 0 2006.257.02:51:27.86#ibcon#flushed, iclass 35, count 0 2006.257.02:51:27.86#ibcon#about to write, iclass 35, count 0 2006.257.02:51:27.86#ibcon#wrote, iclass 35, count 0 2006.257.02:51:27.86#ibcon#about to read 3, iclass 35, count 0 2006.257.02:51:27.88#ibcon#read 3, iclass 35, count 0 2006.257.02:51:27.88#ibcon#about to read 4, iclass 35, count 0 2006.257.02:51:27.88#ibcon#read 4, iclass 35, count 0 2006.257.02:51:27.88#ibcon#about to read 5, iclass 35, count 0 2006.257.02:51:27.88#ibcon#read 5, iclass 35, count 0 2006.257.02:51:27.88#ibcon#about to read 6, iclass 35, count 0 2006.257.02:51:27.88#ibcon#read 6, iclass 35, count 0 2006.257.02:51:27.88#ibcon#end of sib2, iclass 35, count 0 2006.257.02:51:27.88#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:51:27.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:51:27.88#ibcon#[27=USB\r\n] 2006.257.02:51:27.88#ibcon#*before write, iclass 35, count 0 2006.257.02:51:27.88#ibcon#enter sib2, iclass 35, count 0 2006.257.02:51:27.88#ibcon#flushed, iclass 35, count 0 2006.257.02:51:27.88#ibcon#about to write, iclass 35, count 0 2006.257.02:51:27.88#ibcon#wrote, iclass 35, count 0 2006.257.02:51:27.88#ibcon#about to read 3, iclass 35, count 0 2006.257.02:51:27.91#ibcon#read 3, iclass 35, count 0 2006.257.02:51:27.91#ibcon#about to read 4, iclass 35, count 0 2006.257.02:51:27.91#ibcon#read 4, iclass 35, count 0 2006.257.02:51:27.91#ibcon#about to read 5, iclass 35, count 0 2006.257.02:51:27.91#ibcon#read 5, iclass 35, count 0 2006.257.02:51:27.91#ibcon#about to read 6, iclass 35, count 0 2006.257.02:51:27.91#ibcon#read 6, iclass 35, count 0 2006.257.02:51:27.91#ibcon#end of sib2, iclass 35, count 0 2006.257.02:51:27.91#ibcon#*after write, iclass 35, count 0 2006.257.02:51:27.91#ibcon#*before return 0, iclass 35, count 0 2006.257.02:51:27.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:27.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.02:51:27.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:51:27.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:51:27.91$vck44/vblo=4,679.99 2006.257.02:51:27.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.02:51:27.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.02:51:27.91#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:27.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:27.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:27.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:27.91#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:51:27.91#ibcon#first serial, iclass 37, count 0 2006.257.02:51:27.91#ibcon#enter sib2, iclass 37, count 0 2006.257.02:51:27.91#ibcon#flushed, iclass 37, count 0 2006.257.02:51:27.91#ibcon#about to write, iclass 37, count 0 2006.257.02:51:27.91#ibcon#wrote, iclass 37, count 0 2006.257.02:51:27.91#ibcon#about to read 3, iclass 37, count 0 2006.257.02:51:27.93#ibcon#read 3, iclass 37, count 0 2006.257.02:51:27.93#ibcon#about to read 4, iclass 37, count 0 2006.257.02:51:27.93#ibcon#read 4, iclass 37, count 0 2006.257.02:51:27.93#ibcon#about to read 5, iclass 37, count 0 2006.257.02:51:27.93#ibcon#read 5, iclass 37, count 0 2006.257.02:51:27.93#ibcon#about to read 6, iclass 37, count 0 2006.257.02:51:27.93#ibcon#read 6, iclass 37, count 0 2006.257.02:51:27.93#ibcon#end of sib2, iclass 37, count 0 2006.257.02:51:27.93#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:51:27.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:51:27.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:51:27.93#ibcon#*before write, iclass 37, count 0 2006.257.02:51:27.93#ibcon#enter sib2, iclass 37, count 0 2006.257.02:51:27.93#ibcon#flushed, iclass 37, count 0 2006.257.02:51:27.93#ibcon#about to write, iclass 37, count 0 2006.257.02:51:27.93#ibcon#wrote, iclass 37, count 0 2006.257.02:51:27.93#ibcon#about to read 3, iclass 37, count 0 2006.257.02:51:27.97#ibcon#read 3, iclass 37, count 0 2006.257.02:51:27.97#ibcon#about to read 4, iclass 37, count 0 2006.257.02:51:27.97#ibcon#read 4, iclass 37, count 0 2006.257.02:51:27.97#ibcon#about to read 5, iclass 37, count 0 2006.257.02:51:27.97#ibcon#read 5, iclass 37, count 0 2006.257.02:51:27.97#ibcon#about to read 6, iclass 37, count 0 2006.257.02:51:27.97#ibcon#read 6, iclass 37, count 0 2006.257.02:51:27.97#ibcon#end of sib2, iclass 37, count 0 2006.257.02:51:27.97#ibcon#*after write, iclass 37, count 0 2006.257.02:51:27.97#ibcon#*before return 0, iclass 37, count 0 2006.257.02:51:27.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:27.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.02:51:27.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:51:27.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:51:27.97$vck44/vb=4,5 2006.257.02:51:27.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.02:51:27.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.02:51:27.97#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:27.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:28.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:28.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:28.03#ibcon#enter wrdev, iclass 39, count 2 2006.257.02:51:28.03#ibcon#first serial, iclass 39, count 2 2006.257.02:51:28.03#ibcon#enter sib2, iclass 39, count 2 2006.257.02:51:28.03#ibcon#flushed, iclass 39, count 2 2006.257.02:51:28.03#ibcon#about to write, iclass 39, count 2 2006.257.02:51:28.03#ibcon#wrote, iclass 39, count 2 2006.257.02:51:28.03#ibcon#about to read 3, iclass 39, count 2 2006.257.02:51:28.05#ibcon#read 3, iclass 39, count 2 2006.257.02:51:28.05#ibcon#about to read 4, iclass 39, count 2 2006.257.02:51:28.05#ibcon#read 4, iclass 39, count 2 2006.257.02:51:28.05#ibcon#about to read 5, iclass 39, count 2 2006.257.02:51:28.05#ibcon#read 5, iclass 39, count 2 2006.257.02:51:28.05#ibcon#about to read 6, iclass 39, count 2 2006.257.02:51:28.05#ibcon#read 6, iclass 39, count 2 2006.257.02:51:28.05#ibcon#end of sib2, iclass 39, count 2 2006.257.02:51:28.05#ibcon#*mode == 0, iclass 39, count 2 2006.257.02:51:28.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.02:51:28.05#ibcon#[27=AT04-05\r\n] 2006.257.02:51:28.05#ibcon#*before write, iclass 39, count 2 2006.257.02:51:28.05#ibcon#enter sib2, iclass 39, count 2 2006.257.02:51:28.05#ibcon#flushed, iclass 39, count 2 2006.257.02:51:28.05#ibcon#about to write, iclass 39, count 2 2006.257.02:51:28.05#ibcon#wrote, iclass 39, count 2 2006.257.02:51:28.05#ibcon#about to read 3, iclass 39, count 2 2006.257.02:51:28.08#ibcon#read 3, iclass 39, count 2 2006.257.02:51:28.08#ibcon#about to read 4, iclass 39, count 2 2006.257.02:51:28.08#ibcon#read 4, iclass 39, count 2 2006.257.02:51:28.08#ibcon#about to read 5, iclass 39, count 2 2006.257.02:51:28.08#ibcon#read 5, iclass 39, count 2 2006.257.02:51:28.08#ibcon#about to read 6, iclass 39, count 2 2006.257.02:51:28.08#ibcon#read 6, iclass 39, count 2 2006.257.02:51:28.08#ibcon#end of sib2, iclass 39, count 2 2006.257.02:51:28.08#ibcon#*after write, iclass 39, count 2 2006.257.02:51:28.08#ibcon#*before return 0, iclass 39, count 2 2006.257.02:51:28.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:28.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.02:51:28.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.02:51:28.08#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:28.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:28.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:28.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:28.20#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:51:28.20#ibcon#first serial, iclass 39, count 0 2006.257.02:51:28.20#ibcon#enter sib2, iclass 39, count 0 2006.257.02:51:28.20#ibcon#flushed, iclass 39, count 0 2006.257.02:51:28.20#ibcon#about to write, iclass 39, count 0 2006.257.02:51:28.20#ibcon#wrote, iclass 39, count 0 2006.257.02:51:28.20#ibcon#about to read 3, iclass 39, count 0 2006.257.02:51:28.22#ibcon#read 3, iclass 39, count 0 2006.257.02:51:28.22#ibcon#about to read 4, iclass 39, count 0 2006.257.02:51:28.22#ibcon#read 4, iclass 39, count 0 2006.257.02:51:28.22#ibcon#about to read 5, iclass 39, count 0 2006.257.02:51:28.22#ibcon#read 5, iclass 39, count 0 2006.257.02:51:28.22#ibcon#about to read 6, iclass 39, count 0 2006.257.02:51:28.22#ibcon#read 6, iclass 39, count 0 2006.257.02:51:28.22#ibcon#end of sib2, iclass 39, count 0 2006.257.02:51:28.22#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:51:28.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:51:28.22#ibcon#[27=USB\r\n] 2006.257.02:51:28.22#ibcon#*before write, iclass 39, count 0 2006.257.02:51:28.22#ibcon#enter sib2, iclass 39, count 0 2006.257.02:51:28.22#ibcon#flushed, iclass 39, count 0 2006.257.02:51:28.22#ibcon#about to write, iclass 39, count 0 2006.257.02:51:28.22#ibcon#wrote, iclass 39, count 0 2006.257.02:51:28.22#ibcon#about to read 3, iclass 39, count 0 2006.257.02:51:28.25#ibcon#read 3, iclass 39, count 0 2006.257.02:51:28.25#ibcon#about to read 4, iclass 39, count 0 2006.257.02:51:28.25#ibcon#read 4, iclass 39, count 0 2006.257.02:51:28.25#ibcon#about to read 5, iclass 39, count 0 2006.257.02:51:28.25#ibcon#read 5, iclass 39, count 0 2006.257.02:51:28.25#ibcon#about to read 6, iclass 39, count 0 2006.257.02:51:28.25#ibcon#read 6, iclass 39, count 0 2006.257.02:51:28.25#ibcon#end of sib2, iclass 39, count 0 2006.257.02:51:28.25#ibcon#*after write, iclass 39, count 0 2006.257.02:51:28.25#ibcon#*before return 0, iclass 39, count 0 2006.257.02:51:28.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:28.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.02:51:28.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:51:28.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:51:28.25$vck44/vblo=5,709.99 2006.257.02:51:28.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.02:51:28.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.02:51:28.25#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:28.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:28.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:28.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:28.25#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:51:28.25#ibcon#first serial, iclass 3, count 0 2006.257.02:51:28.25#ibcon#enter sib2, iclass 3, count 0 2006.257.02:51:28.25#ibcon#flushed, iclass 3, count 0 2006.257.02:51:28.25#ibcon#about to write, iclass 3, count 0 2006.257.02:51:28.25#ibcon#wrote, iclass 3, count 0 2006.257.02:51:28.25#ibcon#about to read 3, iclass 3, count 0 2006.257.02:51:28.27#ibcon#read 3, iclass 3, count 0 2006.257.02:51:28.27#ibcon#about to read 4, iclass 3, count 0 2006.257.02:51:28.27#ibcon#read 4, iclass 3, count 0 2006.257.02:51:28.27#ibcon#about to read 5, iclass 3, count 0 2006.257.02:51:28.27#ibcon#read 5, iclass 3, count 0 2006.257.02:51:28.27#ibcon#about to read 6, iclass 3, count 0 2006.257.02:51:28.27#ibcon#read 6, iclass 3, count 0 2006.257.02:51:28.27#ibcon#end of sib2, iclass 3, count 0 2006.257.02:51:28.27#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:51:28.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:51:28.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:51:28.27#ibcon#*before write, iclass 3, count 0 2006.257.02:51:28.27#ibcon#enter sib2, iclass 3, count 0 2006.257.02:51:28.27#ibcon#flushed, iclass 3, count 0 2006.257.02:51:28.27#ibcon#about to write, iclass 3, count 0 2006.257.02:51:28.27#ibcon#wrote, iclass 3, count 0 2006.257.02:51:28.27#ibcon#about to read 3, iclass 3, count 0 2006.257.02:51:28.31#ibcon#read 3, iclass 3, count 0 2006.257.02:51:28.31#ibcon#about to read 4, iclass 3, count 0 2006.257.02:51:28.31#ibcon#read 4, iclass 3, count 0 2006.257.02:51:28.31#ibcon#about to read 5, iclass 3, count 0 2006.257.02:51:28.31#ibcon#read 5, iclass 3, count 0 2006.257.02:51:28.31#ibcon#about to read 6, iclass 3, count 0 2006.257.02:51:28.31#ibcon#read 6, iclass 3, count 0 2006.257.02:51:28.31#ibcon#end of sib2, iclass 3, count 0 2006.257.02:51:28.31#ibcon#*after write, iclass 3, count 0 2006.257.02:51:28.31#ibcon#*before return 0, iclass 3, count 0 2006.257.02:51:28.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:28.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:51:28.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:51:28.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:51:28.31$vck44/vb=5,4 2006.257.02:51:28.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.02:51:28.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.02:51:28.31#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:28.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:28.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:28.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:28.37#ibcon#enter wrdev, iclass 5, count 2 2006.257.02:51:28.37#ibcon#first serial, iclass 5, count 2 2006.257.02:51:28.37#ibcon#enter sib2, iclass 5, count 2 2006.257.02:51:28.37#ibcon#flushed, iclass 5, count 2 2006.257.02:51:28.37#ibcon#about to write, iclass 5, count 2 2006.257.02:51:28.37#ibcon#wrote, iclass 5, count 2 2006.257.02:51:28.37#ibcon#about to read 3, iclass 5, count 2 2006.257.02:51:28.39#ibcon#read 3, iclass 5, count 2 2006.257.02:51:28.39#ibcon#about to read 4, iclass 5, count 2 2006.257.02:51:28.39#ibcon#read 4, iclass 5, count 2 2006.257.02:51:28.39#ibcon#about to read 5, iclass 5, count 2 2006.257.02:51:28.39#ibcon#read 5, iclass 5, count 2 2006.257.02:51:28.39#ibcon#about to read 6, iclass 5, count 2 2006.257.02:51:28.39#ibcon#read 6, iclass 5, count 2 2006.257.02:51:28.39#ibcon#end of sib2, iclass 5, count 2 2006.257.02:51:28.39#ibcon#*mode == 0, iclass 5, count 2 2006.257.02:51:28.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.02:51:28.39#ibcon#[27=AT05-04\r\n] 2006.257.02:51:28.39#ibcon#*before write, iclass 5, count 2 2006.257.02:51:28.39#ibcon#enter sib2, iclass 5, count 2 2006.257.02:51:28.39#ibcon#flushed, iclass 5, count 2 2006.257.02:51:28.39#ibcon#about to write, iclass 5, count 2 2006.257.02:51:28.39#ibcon#wrote, iclass 5, count 2 2006.257.02:51:28.39#ibcon#about to read 3, iclass 5, count 2 2006.257.02:51:28.42#ibcon#read 3, iclass 5, count 2 2006.257.02:51:28.42#ibcon#about to read 4, iclass 5, count 2 2006.257.02:51:28.42#ibcon#read 4, iclass 5, count 2 2006.257.02:51:28.42#ibcon#about to read 5, iclass 5, count 2 2006.257.02:51:28.42#ibcon#read 5, iclass 5, count 2 2006.257.02:51:28.42#ibcon#about to read 6, iclass 5, count 2 2006.257.02:51:28.42#ibcon#read 6, iclass 5, count 2 2006.257.02:51:28.42#ibcon#end of sib2, iclass 5, count 2 2006.257.02:51:28.42#ibcon#*after write, iclass 5, count 2 2006.257.02:51:28.42#ibcon#*before return 0, iclass 5, count 2 2006.257.02:51:28.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:28.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.02:51:28.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.02:51:28.42#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:28.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:28.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:28.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:28.54#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:51:28.54#ibcon#first serial, iclass 5, count 0 2006.257.02:51:28.54#ibcon#enter sib2, iclass 5, count 0 2006.257.02:51:28.54#ibcon#flushed, iclass 5, count 0 2006.257.02:51:28.54#ibcon#about to write, iclass 5, count 0 2006.257.02:51:28.54#ibcon#wrote, iclass 5, count 0 2006.257.02:51:28.54#ibcon#about to read 3, iclass 5, count 0 2006.257.02:51:28.56#ibcon#read 3, iclass 5, count 0 2006.257.02:51:28.56#ibcon#about to read 4, iclass 5, count 0 2006.257.02:51:28.56#ibcon#read 4, iclass 5, count 0 2006.257.02:51:28.56#ibcon#about to read 5, iclass 5, count 0 2006.257.02:51:28.56#ibcon#read 5, iclass 5, count 0 2006.257.02:51:28.56#ibcon#about to read 6, iclass 5, count 0 2006.257.02:51:28.56#ibcon#read 6, iclass 5, count 0 2006.257.02:51:28.56#ibcon#end of sib2, iclass 5, count 0 2006.257.02:51:28.56#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:51:28.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:51:28.56#ibcon#[27=USB\r\n] 2006.257.02:51:28.56#ibcon#*before write, iclass 5, count 0 2006.257.02:51:28.56#ibcon#enter sib2, iclass 5, count 0 2006.257.02:51:28.56#ibcon#flushed, iclass 5, count 0 2006.257.02:51:28.56#ibcon#about to write, iclass 5, count 0 2006.257.02:51:28.56#ibcon#wrote, iclass 5, count 0 2006.257.02:51:28.56#ibcon#about to read 3, iclass 5, count 0 2006.257.02:51:28.59#ibcon#read 3, iclass 5, count 0 2006.257.02:51:28.59#ibcon#about to read 4, iclass 5, count 0 2006.257.02:51:28.59#ibcon#read 4, iclass 5, count 0 2006.257.02:51:28.59#ibcon#about to read 5, iclass 5, count 0 2006.257.02:51:28.59#ibcon#read 5, iclass 5, count 0 2006.257.02:51:28.59#ibcon#about to read 6, iclass 5, count 0 2006.257.02:51:28.59#ibcon#read 6, iclass 5, count 0 2006.257.02:51:28.59#ibcon#end of sib2, iclass 5, count 0 2006.257.02:51:28.59#ibcon#*after write, iclass 5, count 0 2006.257.02:51:28.59#ibcon#*before return 0, iclass 5, count 0 2006.257.02:51:28.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:28.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.02:51:28.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:51:28.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:51:28.59$vck44/vblo=6,719.99 2006.257.02:51:28.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.02:51:28.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.02:51:28.59#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:28.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:28.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:28.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:28.59#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:51:28.59#ibcon#first serial, iclass 7, count 0 2006.257.02:51:28.59#ibcon#enter sib2, iclass 7, count 0 2006.257.02:51:28.59#ibcon#flushed, iclass 7, count 0 2006.257.02:51:28.59#ibcon#about to write, iclass 7, count 0 2006.257.02:51:28.59#ibcon#wrote, iclass 7, count 0 2006.257.02:51:28.59#ibcon#about to read 3, iclass 7, count 0 2006.257.02:51:28.61#ibcon#read 3, iclass 7, count 0 2006.257.02:51:28.61#ibcon#about to read 4, iclass 7, count 0 2006.257.02:51:28.61#ibcon#read 4, iclass 7, count 0 2006.257.02:51:28.61#ibcon#about to read 5, iclass 7, count 0 2006.257.02:51:28.61#ibcon#read 5, iclass 7, count 0 2006.257.02:51:28.61#ibcon#about to read 6, iclass 7, count 0 2006.257.02:51:28.61#ibcon#read 6, iclass 7, count 0 2006.257.02:51:28.61#ibcon#end of sib2, iclass 7, count 0 2006.257.02:51:28.61#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:51:28.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:51:28.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:51:28.61#ibcon#*before write, iclass 7, count 0 2006.257.02:51:28.61#ibcon#enter sib2, iclass 7, count 0 2006.257.02:51:28.61#ibcon#flushed, iclass 7, count 0 2006.257.02:51:28.61#ibcon#about to write, iclass 7, count 0 2006.257.02:51:28.61#ibcon#wrote, iclass 7, count 0 2006.257.02:51:28.61#ibcon#about to read 3, iclass 7, count 0 2006.257.02:51:28.65#ibcon#read 3, iclass 7, count 0 2006.257.02:51:28.65#ibcon#about to read 4, iclass 7, count 0 2006.257.02:51:28.65#ibcon#read 4, iclass 7, count 0 2006.257.02:51:28.65#ibcon#about to read 5, iclass 7, count 0 2006.257.02:51:28.65#ibcon#read 5, iclass 7, count 0 2006.257.02:51:28.65#ibcon#about to read 6, iclass 7, count 0 2006.257.02:51:28.65#ibcon#read 6, iclass 7, count 0 2006.257.02:51:28.65#ibcon#end of sib2, iclass 7, count 0 2006.257.02:51:28.65#ibcon#*after write, iclass 7, count 0 2006.257.02:51:28.65#ibcon#*before return 0, iclass 7, count 0 2006.257.02:51:28.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:28.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.02:51:28.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:51:28.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:51:28.65$vck44/vb=6,4 2006.257.02:51:28.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.02:51:28.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.02:51:28.65#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:28.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:28.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:28.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:28.71#ibcon#enter wrdev, iclass 11, count 2 2006.257.02:51:28.71#ibcon#first serial, iclass 11, count 2 2006.257.02:51:28.71#ibcon#enter sib2, iclass 11, count 2 2006.257.02:51:28.71#ibcon#flushed, iclass 11, count 2 2006.257.02:51:28.71#ibcon#about to write, iclass 11, count 2 2006.257.02:51:28.71#ibcon#wrote, iclass 11, count 2 2006.257.02:51:28.71#ibcon#about to read 3, iclass 11, count 2 2006.257.02:51:28.73#ibcon#read 3, iclass 11, count 2 2006.257.02:51:28.73#ibcon#about to read 4, iclass 11, count 2 2006.257.02:51:28.73#ibcon#read 4, iclass 11, count 2 2006.257.02:51:28.73#ibcon#about to read 5, iclass 11, count 2 2006.257.02:51:28.73#ibcon#read 5, iclass 11, count 2 2006.257.02:51:28.73#ibcon#about to read 6, iclass 11, count 2 2006.257.02:51:28.73#ibcon#read 6, iclass 11, count 2 2006.257.02:51:28.73#ibcon#end of sib2, iclass 11, count 2 2006.257.02:51:28.73#ibcon#*mode == 0, iclass 11, count 2 2006.257.02:51:28.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.02:51:28.73#ibcon#[27=AT06-04\r\n] 2006.257.02:51:28.73#ibcon#*before write, iclass 11, count 2 2006.257.02:51:28.73#ibcon#enter sib2, iclass 11, count 2 2006.257.02:51:28.73#ibcon#flushed, iclass 11, count 2 2006.257.02:51:28.73#ibcon#about to write, iclass 11, count 2 2006.257.02:51:28.73#ibcon#wrote, iclass 11, count 2 2006.257.02:51:28.73#ibcon#about to read 3, iclass 11, count 2 2006.257.02:51:28.76#ibcon#read 3, iclass 11, count 2 2006.257.02:51:28.76#ibcon#about to read 4, iclass 11, count 2 2006.257.02:51:28.76#ibcon#read 4, iclass 11, count 2 2006.257.02:51:28.76#ibcon#about to read 5, iclass 11, count 2 2006.257.02:51:28.76#ibcon#read 5, iclass 11, count 2 2006.257.02:51:28.76#ibcon#about to read 6, iclass 11, count 2 2006.257.02:51:28.76#ibcon#read 6, iclass 11, count 2 2006.257.02:51:28.76#ibcon#end of sib2, iclass 11, count 2 2006.257.02:51:28.76#ibcon#*after write, iclass 11, count 2 2006.257.02:51:28.76#ibcon#*before return 0, iclass 11, count 2 2006.257.02:51:28.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:28.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.02:51:28.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.02:51:28.76#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:28.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:28.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:28.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:28.88#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:51:28.88#ibcon#first serial, iclass 11, count 0 2006.257.02:51:28.88#ibcon#enter sib2, iclass 11, count 0 2006.257.02:51:28.88#ibcon#flushed, iclass 11, count 0 2006.257.02:51:28.88#ibcon#about to write, iclass 11, count 0 2006.257.02:51:28.88#ibcon#wrote, iclass 11, count 0 2006.257.02:51:28.88#ibcon#about to read 3, iclass 11, count 0 2006.257.02:51:28.90#ibcon#read 3, iclass 11, count 0 2006.257.02:51:28.90#ibcon#about to read 4, iclass 11, count 0 2006.257.02:51:28.90#ibcon#read 4, iclass 11, count 0 2006.257.02:51:28.90#ibcon#about to read 5, iclass 11, count 0 2006.257.02:51:28.90#ibcon#read 5, iclass 11, count 0 2006.257.02:51:28.90#ibcon#about to read 6, iclass 11, count 0 2006.257.02:51:28.90#ibcon#read 6, iclass 11, count 0 2006.257.02:51:28.90#ibcon#end of sib2, iclass 11, count 0 2006.257.02:51:28.90#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:51:28.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:51:28.90#ibcon#[27=USB\r\n] 2006.257.02:51:28.90#ibcon#*before write, iclass 11, count 0 2006.257.02:51:28.90#ibcon#enter sib2, iclass 11, count 0 2006.257.02:51:28.90#ibcon#flushed, iclass 11, count 0 2006.257.02:51:28.90#ibcon#about to write, iclass 11, count 0 2006.257.02:51:28.90#ibcon#wrote, iclass 11, count 0 2006.257.02:51:28.90#ibcon#about to read 3, iclass 11, count 0 2006.257.02:51:28.93#ibcon#read 3, iclass 11, count 0 2006.257.02:51:28.93#ibcon#about to read 4, iclass 11, count 0 2006.257.02:51:28.93#ibcon#read 4, iclass 11, count 0 2006.257.02:51:28.93#ibcon#about to read 5, iclass 11, count 0 2006.257.02:51:28.93#ibcon#read 5, iclass 11, count 0 2006.257.02:51:28.93#ibcon#about to read 6, iclass 11, count 0 2006.257.02:51:28.93#ibcon#read 6, iclass 11, count 0 2006.257.02:51:28.93#ibcon#end of sib2, iclass 11, count 0 2006.257.02:51:28.93#ibcon#*after write, iclass 11, count 0 2006.257.02:51:28.93#ibcon#*before return 0, iclass 11, count 0 2006.257.02:51:28.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:28.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.02:51:28.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:51:28.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:51:28.93$vck44/vblo=7,734.99 2006.257.02:51:28.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.02:51:28.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.02:51:28.93#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:28.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:28.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:28.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:28.93#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:51:28.93#ibcon#first serial, iclass 13, count 0 2006.257.02:51:28.93#ibcon#enter sib2, iclass 13, count 0 2006.257.02:51:28.93#ibcon#flushed, iclass 13, count 0 2006.257.02:51:28.93#ibcon#about to write, iclass 13, count 0 2006.257.02:51:28.93#ibcon#wrote, iclass 13, count 0 2006.257.02:51:28.93#ibcon#about to read 3, iclass 13, count 0 2006.257.02:51:28.95#ibcon#read 3, iclass 13, count 0 2006.257.02:51:28.95#ibcon#about to read 4, iclass 13, count 0 2006.257.02:51:28.95#ibcon#read 4, iclass 13, count 0 2006.257.02:51:28.95#ibcon#about to read 5, iclass 13, count 0 2006.257.02:51:28.95#ibcon#read 5, iclass 13, count 0 2006.257.02:51:28.95#ibcon#about to read 6, iclass 13, count 0 2006.257.02:51:28.95#ibcon#read 6, iclass 13, count 0 2006.257.02:51:28.95#ibcon#end of sib2, iclass 13, count 0 2006.257.02:51:28.95#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:51:28.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:51:28.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:51:28.95#ibcon#*before write, iclass 13, count 0 2006.257.02:51:28.95#ibcon#enter sib2, iclass 13, count 0 2006.257.02:51:28.95#ibcon#flushed, iclass 13, count 0 2006.257.02:51:28.95#ibcon#about to write, iclass 13, count 0 2006.257.02:51:28.95#ibcon#wrote, iclass 13, count 0 2006.257.02:51:28.95#ibcon#about to read 3, iclass 13, count 0 2006.257.02:51:28.99#ibcon#read 3, iclass 13, count 0 2006.257.02:51:28.99#ibcon#about to read 4, iclass 13, count 0 2006.257.02:51:28.99#ibcon#read 4, iclass 13, count 0 2006.257.02:51:28.99#ibcon#about to read 5, iclass 13, count 0 2006.257.02:51:28.99#ibcon#read 5, iclass 13, count 0 2006.257.02:51:28.99#ibcon#about to read 6, iclass 13, count 0 2006.257.02:51:28.99#ibcon#read 6, iclass 13, count 0 2006.257.02:51:28.99#ibcon#end of sib2, iclass 13, count 0 2006.257.02:51:28.99#ibcon#*after write, iclass 13, count 0 2006.257.02:51:28.99#ibcon#*before return 0, iclass 13, count 0 2006.257.02:51:28.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:28.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.02:51:28.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:51:28.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:51:28.99$vck44/vb=7,4 2006.257.02:51:28.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.02:51:28.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.02:51:28.99#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:28.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:29.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:29.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:29.05#ibcon#enter wrdev, iclass 15, count 2 2006.257.02:51:29.05#ibcon#first serial, iclass 15, count 2 2006.257.02:51:29.05#ibcon#enter sib2, iclass 15, count 2 2006.257.02:51:29.05#ibcon#flushed, iclass 15, count 2 2006.257.02:51:29.05#ibcon#about to write, iclass 15, count 2 2006.257.02:51:29.05#ibcon#wrote, iclass 15, count 2 2006.257.02:51:29.05#ibcon#about to read 3, iclass 15, count 2 2006.257.02:51:29.07#ibcon#read 3, iclass 15, count 2 2006.257.02:51:29.07#ibcon#about to read 4, iclass 15, count 2 2006.257.02:51:29.07#ibcon#read 4, iclass 15, count 2 2006.257.02:51:29.07#ibcon#about to read 5, iclass 15, count 2 2006.257.02:51:29.07#ibcon#read 5, iclass 15, count 2 2006.257.02:51:29.07#ibcon#about to read 6, iclass 15, count 2 2006.257.02:51:29.07#ibcon#read 6, iclass 15, count 2 2006.257.02:51:29.07#ibcon#end of sib2, iclass 15, count 2 2006.257.02:51:29.07#ibcon#*mode == 0, iclass 15, count 2 2006.257.02:51:29.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.02:51:29.07#ibcon#[27=AT07-04\r\n] 2006.257.02:51:29.07#ibcon#*before write, iclass 15, count 2 2006.257.02:51:29.07#ibcon#enter sib2, iclass 15, count 2 2006.257.02:51:29.07#ibcon#flushed, iclass 15, count 2 2006.257.02:51:29.07#ibcon#about to write, iclass 15, count 2 2006.257.02:51:29.07#ibcon#wrote, iclass 15, count 2 2006.257.02:51:29.07#ibcon#about to read 3, iclass 15, count 2 2006.257.02:51:29.10#ibcon#read 3, iclass 15, count 2 2006.257.02:51:29.10#ibcon#about to read 4, iclass 15, count 2 2006.257.02:51:29.10#ibcon#read 4, iclass 15, count 2 2006.257.02:51:29.10#ibcon#about to read 5, iclass 15, count 2 2006.257.02:51:29.10#ibcon#read 5, iclass 15, count 2 2006.257.02:51:29.10#ibcon#about to read 6, iclass 15, count 2 2006.257.02:51:29.10#ibcon#read 6, iclass 15, count 2 2006.257.02:51:29.10#ibcon#end of sib2, iclass 15, count 2 2006.257.02:51:29.10#ibcon#*after write, iclass 15, count 2 2006.257.02:51:29.10#ibcon#*before return 0, iclass 15, count 2 2006.257.02:51:29.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:29.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.02:51:29.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.02:51:29.10#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:29.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:29.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:29.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:29.22#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:51:29.22#ibcon#first serial, iclass 15, count 0 2006.257.02:51:29.22#ibcon#enter sib2, iclass 15, count 0 2006.257.02:51:29.22#ibcon#flushed, iclass 15, count 0 2006.257.02:51:29.22#ibcon#about to write, iclass 15, count 0 2006.257.02:51:29.22#ibcon#wrote, iclass 15, count 0 2006.257.02:51:29.22#ibcon#about to read 3, iclass 15, count 0 2006.257.02:51:29.24#ibcon#read 3, iclass 15, count 0 2006.257.02:51:29.24#ibcon#about to read 4, iclass 15, count 0 2006.257.02:51:29.24#ibcon#read 4, iclass 15, count 0 2006.257.02:51:29.24#ibcon#about to read 5, iclass 15, count 0 2006.257.02:51:29.24#ibcon#read 5, iclass 15, count 0 2006.257.02:51:29.24#ibcon#about to read 6, iclass 15, count 0 2006.257.02:51:29.24#ibcon#read 6, iclass 15, count 0 2006.257.02:51:29.24#ibcon#end of sib2, iclass 15, count 0 2006.257.02:51:29.24#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:51:29.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:51:29.24#ibcon#[27=USB\r\n] 2006.257.02:51:29.24#ibcon#*before write, iclass 15, count 0 2006.257.02:51:29.24#ibcon#enter sib2, iclass 15, count 0 2006.257.02:51:29.24#ibcon#flushed, iclass 15, count 0 2006.257.02:51:29.24#ibcon#about to write, iclass 15, count 0 2006.257.02:51:29.24#ibcon#wrote, iclass 15, count 0 2006.257.02:51:29.24#ibcon#about to read 3, iclass 15, count 0 2006.257.02:51:29.27#ibcon#read 3, iclass 15, count 0 2006.257.02:51:29.27#ibcon#about to read 4, iclass 15, count 0 2006.257.02:51:29.27#ibcon#read 4, iclass 15, count 0 2006.257.02:51:29.27#ibcon#about to read 5, iclass 15, count 0 2006.257.02:51:29.27#ibcon#read 5, iclass 15, count 0 2006.257.02:51:29.27#ibcon#about to read 6, iclass 15, count 0 2006.257.02:51:29.27#ibcon#read 6, iclass 15, count 0 2006.257.02:51:29.27#ibcon#end of sib2, iclass 15, count 0 2006.257.02:51:29.27#ibcon#*after write, iclass 15, count 0 2006.257.02:51:29.27#ibcon#*before return 0, iclass 15, count 0 2006.257.02:51:29.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:29.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.02:51:29.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:51:29.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:51:29.27$vck44/vblo=8,744.99 2006.257.02:51:29.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.02:51:29.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.02:51:29.27#ibcon#ireg 17 cls_cnt 0 2006.257.02:51:29.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:29.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:29.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:29.27#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:51:29.27#ibcon#first serial, iclass 17, count 0 2006.257.02:51:29.27#ibcon#enter sib2, iclass 17, count 0 2006.257.02:51:29.27#ibcon#flushed, iclass 17, count 0 2006.257.02:51:29.27#ibcon#about to write, iclass 17, count 0 2006.257.02:51:29.27#ibcon#wrote, iclass 17, count 0 2006.257.02:51:29.27#ibcon#about to read 3, iclass 17, count 0 2006.257.02:51:29.29#ibcon#read 3, iclass 17, count 0 2006.257.02:51:29.29#ibcon#about to read 4, iclass 17, count 0 2006.257.02:51:29.29#ibcon#read 4, iclass 17, count 0 2006.257.02:51:29.29#ibcon#about to read 5, iclass 17, count 0 2006.257.02:51:29.29#ibcon#read 5, iclass 17, count 0 2006.257.02:51:29.29#ibcon#about to read 6, iclass 17, count 0 2006.257.02:51:29.29#ibcon#read 6, iclass 17, count 0 2006.257.02:51:29.29#ibcon#end of sib2, iclass 17, count 0 2006.257.02:51:29.29#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:51:29.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:51:29.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:51:29.29#ibcon#*before write, iclass 17, count 0 2006.257.02:51:29.29#ibcon#enter sib2, iclass 17, count 0 2006.257.02:51:29.29#ibcon#flushed, iclass 17, count 0 2006.257.02:51:29.29#ibcon#about to write, iclass 17, count 0 2006.257.02:51:29.29#ibcon#wrote, iclass 17, count 0 2006.257.02:51:29.29#ibcon#about to read 3, iclass 17, count 0 2006.257.02:51:29.33#ibcon#read 3, iclass 17, count 0 2006.257.02:51:29.33#ibcon#about to read 4, iclass 17, count 0 2006.257.02:51:29.33#ibcon#read 4, iclass 17, count 0 2006.257.02:51:29.33#ibcon#about to read 5, iclass 17, count 0 2006.257.02:51:29.33#ibcon#read 5, iclass 17, count 0 2006.257.02:51:29.33#ibcon#about to read 6, iclass 17, count 0 2006.257.02:51:29.33#ibcon#read 6, iclass 17, count 0 2006.257.02:51:29.33#ibcon#end of sib2, iclass 17, count 0 2006.257.02:51:29.33#ibcon#*after write, iclass 17, count 0 2006.257.02:51:29.33#ibcon#*before return 0, iclass 17, count 0 2006.257.02:51:29.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:29.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.02:51:29.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:51:29.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:51:29.33$vck44/vb=8,4 2006.257.02:51:29.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.02:51:29.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.02:51:29.33#ibcon#ireg 11 cls_cnt 2 2006.257.02:51:29.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:29.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:29.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:29.39#ibcon#enter wrdev, iclass 19, count 2 2006.257.02:51:29.39#ibcon#first serial, iclass 19, count 2 2006.257.02:51:29.39#ibcon#enter sib2, iclass 19, count 2 2006.257.02:51:29.39#ibcon#flushed, iclass 19, count 2 2006.257.02:51:29.39#ibcon#about to write, iclass 19, count 2 2006.257.02:51:29.39#ibcon#wrote, iclass 19, count 2 2006.257.02:51:29.39#ibcon#about to read 3, iclass 19, count 2 2006.257.02:51:29.41#ibcon#read 3, iclass 19, count 2 2006.257.02:51:29.41#ibcon#about to read 4, iclass 19, count 2 2006.257.02:51:29.41#ibcon#read 4, iclass 19, count 2 2006.257.02:51:29.41#ibcon#about to read 5, iclass 19, count 2 2006.257.02:51:29.41#ibcon#read 5, iclass 19, count 2 2006.257.02:51:29.41#ibcon#about to read 6, iclass 19, count 2 2006.257.02:51:29.41#ibcon#read 6, iclass 19, count 2 2006.257.02:51:29.41#ibcon#end of sib2, iclass 19, count 2 2006.257.02:51:29.41#ibcon#*mode == 0, iclass 19, count 2 2006.257.02:51:29.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.02:51:29.41#ibcon#[27=AT08-04\r\n] 2006.257.02:51:29.41#ibcon#*before write, iclass 19, count 2 2006.257.02:51:29.41#ibcon#enter sib2, iclass 19, count 2 2006.257.02:51:29.41#ibcon#flushed, iclass 19, count 2 2006.257.02:51:29.41#ibcon#about to write, iclass 19, count 2 2006.257.02:51:29.41#ibcon#wrote, iclass 19, count 2 2006.257.02:51:29.41#ibcon#about to read 3, iclass 19, count 2 2006.257.02:51:29.44#ibcon#read 3, iclass 19, count 2 2006.257.02:51:29.44#ibcon#about to read 4, iclass 19, count 2 2006.257.02:51:29.44#ibcon#read 4, iclass 19, count 2 2006.257.02:51:29.44#ibcon#about to read 5, iclass 19, count 2 2006.257.02:51:29.44#ibcon#read 5, iclass 19, count 2 2006.257.02:51:29.44#ibcon#about to read 6, iclass 19, count 2 2006.257.02:51:29.44#ibcon#read 6, iclass 19, count 2 2006.257.02:51:29.44#ibcon#end of sib2, iclass 19, count 2 2006.257.02:51:29.44#ibcon#*after write, iclass 19, count 2 2006.257.02:51:29.44#ibcon#*before return 0, iclass 19, count 2 2006.257.02:51:29.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:29.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.02:51:29.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.02:51:29.44#ibcon#ireg 7 cls_cnt 0 2006.257.02:51:29.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:29.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:29.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:29.56#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:51:29.56#ibcon#first serial, iclass 19, count 0 2006.257.02:51:29.56#ibcon#enter sib2, iclass 19, count 0 2006.257.02:51:29.56#ibcon#flushed, iclass 19, count 0 2006.257.02:51:29.56#ibcon#about to write, iclass 19, count 0 2006.257.02:51:29.56#ibcon#wrote, iclass 19, count 0 2006.257.02:51:29.56#ibcon#about to read 3, iclass 19, count 0 2006.257.02:51:29.58#ibcon#read 3, iclass 19, count 0 2006.257.02:51:29.58#ibcon#about to read 4, iclass 19, count 0 2006.257.02:51:29.58#ibcon#read 4, iclass 19, count 0 2006.257.02:51:29.58#ibcon#about to read 5, iclass 19, count 0 2006.257.02:51:29.58#ibcon#read 5, iclass 19, count 0 2006.257.02:51:29.58#ibcon#about to read 6, iclass 19, count 0 2006.257.02:51:29.58#ibcon#read 6, iclass 19, count 0 2006.257.02:51:29.58#ibcon#end of sib2, iclass 19, count 0 2006.257.02:51:29.58#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:51:29.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:51:29.58#ibcon#[27=USB\r\n] 2006.257.02:51:29.58#ibcon#*before write, iclass 19, count 0 2006.257.02:51:29.58#ibcon#enter sib2, iclass 19, count 0 2006.257.02:51:29.58#ibcon#flushed, iclass 19, count 0 2006.257.02:51:29.58#ibcon#about to write, iclass 19, count 0 2006.257.02:51:29.58#ibcon#wrote, iclass 19, count 0 2006.257.02:51:29.58#ibcon#about to read 3, iclass 19, count 0 2006.257.02:51:29.61#ibcon#read 3, iclass 19, count 0 2006.257.02:51:29.61#ibcon#about to read 4, iclass 19, count 0 2006.257.02:51:29.61#ibcon#read 4, iclass 19, count 0 2006.257.02:51:29.61#ibcon#about to read 5, iclass 19, count 0 2006.257.02:51:29.61#ibcon#read 5, iclass 19, count 0 2006.257.02:51:29.61#ibcon#about to read 6, iclass 19, count 0 2006.257.02:51:29.61#ibcon#read 6, iclass 19, count 0 2006.257.02:51:29.61#ibcon#end of sib2, iclass 19, count 0 2006.257.02:51:29.61#ibcon#*after write, iclass 19, count 0 2006.257.02:51:29.61#ibcon#*before return 0, iclass 19, count 0 2006.257.02:51:29.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:29.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.02:51:29.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:51:29.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:51:29.61$vck44/vabw=wide 2006.257.02:51:29.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.02:51:29.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.02:51:29.61#ibcon#ireg 8 cls_cnt 0 2006.257.02:51:29.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:29.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:29.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:29.61#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:51:29.61#ibcon#first serial, iclass 21, count 0 2006.257.02:51:29.61#ibcon#enter sib2, iclass 21, count 0 2006.257.02:51:29.61#ibcon#flushed, iclass 21, count 0 2006.257.02:51:29.61#ibcon#about to write, iclass 21, count 0 2006.257.02:51:29.61#ibcon#wrote, iclass 21, count 0 2006.257.02:51:29.61#ibcon#about to read 3, iclass 21, count 0 2006.257.02:51:29.63#ibcon#read 3, iclass 21, count 0 2006.257.02:51:29.63#ibcon#about to read 4, iclass 21, count 0 2006.257.02:51:29.63#ibcon#read 4, iclass 21, count 0 2006.257.02:51:29.63#ibcon#about to read 5, iclass 21, count 0 2006.257.02:51:29.63#ibcon#read 5, iclass 21, count 0 2006.257.02:51:29.63#ibcon#about to read 6, iclass 21, count 0 2006.257.02:51:29.63#ibcon#read 6, iclass 21, count 0 2006.257.02:51:29.63#ibcon#end of sib2, iclass 21, count 0 2006.257.02:51:29.63#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:51:29.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:51:29.63#ibcon#[25=BW32\r\n] 2006.257.02:51:29.63#ibcon#*before write, iclass 21, count 0 2006.257.02:51:29.63#ibcon#enter sib2, iclass 21, count 0 2006.257.02:51:29.63#ibcon#flushed, iclass 21, count 0 2006.257.02:51:29.63#ibcon#about to write, iclass 21, count 0 2006.257.02:51:29.63#ibcon#wrote, iclass 21, count 0 2006.257.02:51:29.63#ibcon#about to read 3, iclass 21, count 0 2006.257.02:51:29.66#ibcon#read 3, iclass 21, count 0 2006.257.02:51:29.66#ibcon#about to read 4, iclass 21, count 0 2006.257.02:51:29.66#ibcon#read 4, iclass 21, count 0 2006.257.02:51:29.66#ibcon#about to read 5, iclass 21, count 0 2006.257.02:51:29.66#ibcon#read 5, iclass 21, count 0 2006.257.02:51:29.66#ibcon#about to read 6, iclass 21, count 0 2006.257.02:51:29.66#ibcon#read 6, iclass 21, count 0 2006.257.02:51:29.66#ibcon#end of sib2, iclass 21, count 0 2006.257.02:51:29.66#ibcon#*after write, iclass 21, count 0 2006.257.02:51:29.66#ibcon#*before return 0, iclass 21, count 0 2006.257.02:51:29.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:29.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.02:51:29.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:51:29.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:51:29.66$vck44/vbbw=wide 2006.257.02:51:29.66#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.02:51:29.66#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.02:51:29.66#ibcon#ireg 8 cls_cnt 0 2006.257.02:51:29.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:51:29.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:51:29.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:51:29.73#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:51:29.73#ibcon#first serial, iclass 23, count 0 2006.257.02:51:29.73#ibcon#enter sib2, iclass 23, count 0 2006.257.02:51:29.73#ibcon#flushed, iclass 23, count 0 2006.257.02:51:29.73#ibcon#about to write, iclass 23, count 0 2006.257.02:51:29.73#ibcon#wrote, iclass 23, count 0 2006.257.02:51:29.73#ibcon#about to read 3, iclass 23, count 0 2006.257.02:51:29.75#ibcon#read 3, iclass 23, count 0 2006.257.02:51:29.75#ibcon#about to read 4, iclass 23, count 0 2006.257.02:51:29.75#ibcon#read 4, iclass 23, count 0 2006.257.02:51:29.75#ibcon#about to read 5, iclass 23, count 0 2006.257.02:51:29.75#ibcon#read 5, iclass 23, count 0 2006.257.02:51:29.75#ibcon#about to read 6, iclass 23, count 0 2006.257.02:51:29.75#ibcon#read 6, iclass 23, count 0 2006.257.02:51:29.75#ibcon#end of sib2, iclass 23, count 0 2006.257.02:51:29.75#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:51:29.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:51:29.75#ibcon#[27=BW32\r\n] 2006.257.02:51:29.75#ibcon#*before write, iclass 23, count 0 2006.257.02:51:29.75#ibcon#enter sib2, iclass 23, count 0 2006.257.02:51:29.75#ibcon#flushed, iclass 23, count 0 2006.257.02:51:29.75#ibcon#about to write, iclass 23, count 0 2006.257.02:51:29.75#ibcon#wrote, iclass 23, count 0 2006.257.02:51:29.75#ibcon#about to read 3, iclass 23, count 0 2006.257.02:51:29.78#ibcon#read 3, iclass 23, count 0 2006.257.02:51:29.78#ibcon#about to read 4, iclass 23, count 0 2006.257.02:51:29.78#ibcon#read 4, iclass 23, count 0 2006.257.02:51:29.78#ibcon#about to read 5, iclass 23, count 0 2006.257.02:51:29.78#ibcon#read 5, iclass 23, count 0 2006.257.02:51:29.78#ibcon#about to read 6, iclass 23, count 0 2006.257.02:51:29.78#ibcon#read 6, iclass 23, count 0 2006.257.02:51:29.78#ibcon#end of sib2, iclass 23, count 0 2006.257.02:51:29.78#ibcon#*after write, iclass 23, count 0 2006.257.02:51:29.78#ibcon#*before return 0, iclass 23, count 0 2006.257.02:51:29.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:51:29.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:51:29.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:51:29.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:51:29.78$setupk4/ifdk4 2006.257.02:51:29.78$ifdk4/lo= 2006.257.02:51:29.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:51:29.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:51:29.78$ifdk4/patch= 2006.257.02:51:29.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:51:29.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:51:29.78$setupk4/!*+20s 2006.257.02:51:33.73#abcon#<5=/16 1.6 5.7 18.95 911012.5\r\n> 2006.257.02:51:33.75#abcon#{5=INTERFACE CLEAR} 2006.257.02:51:33.81#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:51:43.90#abcon#<5=/16 1.7 5.7 18.94 911012.5\r\n> 2006.257.02:51:43.92#abcon#{5=INTERFACE CLEAR} 2006.257.02:51:43.98#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:51:44.28$setupk4/"tpicd 2006.257.02:51:44.28$setupk4/echo=off 2006.257.02:51:44.28$setupk4/xlog=off 2006.257.02:51:44.28:!2006.257.02:53:23 2006.257.02:51:59.14#trakl#Source acquired 2006.257.02:52:00.14#flagr#flagr/antenna,acquired 2006.257.02:53:23.00:preob 2006.257.02:53:23.13/onsource/TRACKING 2006.257.02:53:23.13:!2006.257.02:53:33 2006.257.02:53:33.00:"tape 2006.257.02:53:33.00:"st=record 2006.257.02:53:33.00:data_valid=on 2006.257.02:53:33.00:midob 2006.257.02:53:33.13/onsource/TRACKING 2006.257.02:53:33.13/wx/18.90,1012.5,91 2006.257.02:53:33.32/cable/+6.4840E-03 2006.257.02:53:34.41/va/01,08,usb,yes,32,34 2006.257.02:53:34.41/va/02,07,usb,yes,35,35 2006.257.02:53:34.41/va/03,08,usb,yes,31,33 2006.257.02:53:34.41/va/04,07,usb,yes,36,37 2006.257.02:53:34.41/va/05,04,usb,yes,32,32 2006.257.02:53:34.41/va/06,04,usb,yes,35,35 2006.257.02:53:34.41/va/07,04,usb,yes,36,37 2006.257.02:53:34.41/va/08,04,usb,yes,30,37 2006.257.02:53:34.64/valo/01,524.99,yes,locked 2006.257.02:53:34.64/valo/02,534.99,yes,locked 2006.257.02:53:34.64/valo/03,564.99,yes,locked 2006.257.02:53:34.64/valo/04,624.99,yes,locked 2006.257.02:53:34.64/valo/05,734.99,yes,locked 2006.257.02:53:34.64/valo/06,814.99,yes,locked 2006.257.02:53:34.64/valo/07,864.99,yes,locked 2006.257.02:53:34.64/valo/08,884.99,yes,locked 2006.257.02:53:35.73/vb/01,04,usb,yes,31,29 2006.257.02:53:35.73/vb/02,05,usb,yes,30,29 2006.257.02:53:35.73/vb/03,04,usb,yes,30,33 2006.257.02:53:35.73/vb/04,05,usb,yes,31,30 2006.257.02:53:35.73/vb/05,04,usb,yes,27,30 2006.257.02:53:35.73/vb/06,04,usb,yes,32,28 2006.257.02:53:35.73/vb/07,04,usb,yes,31,31 2006.257.02:53:35.73/vb/08,04,usb,yes,29,32 2006.257.02:53:35.97/vblo/01,629.99,yes,locked 2006.257.02:53:35.97/vblo/02,634.99,yes,locked 2006.257.02:53:35.97/vblo/03,649.99,yes,locked 2006.257.02:53:35.97/vblo/04,679.99,yes,locked 2006.257.02:53:35.97/vblo/05,709.99,yes,locked 2006.257.02:53:35.97/vblo/06,719.99,yes,locked 2006.257.02:53:35.97/vblo/07,734.99,yes,locked 2006.257.02:53:35.97/vblo/08,744.99,yes,locked 2006.257.02:53:36.12/vabw/8 2006.257.02:53:36.27/vbbw/8 2006.257.02:53:36.49/xfe/off,on,15.5 2006.257.02:53:36.86/ifatt/23,28,28,28 2006.257.02:53:37.08/fmout-gps/S +4.58E-07 2006.257.02:53:37.12:!2006.257.02:54:23 2006.257.02:54:23.00:data_valid=off 2006.257.02:54:23.00:"et 2006.257.02:54:23.00:!+3s 2006.257.02:54:26.03:"tape 2006.257.02:54:26.03:postob 2006.257.02:54:26.12/cable/+6.4840E-03 2006.257.02:54:26.12/wx/18.88,1012.5,89 2006.257.02:54:26.19/fmout-gps/S +4.59E-07 2006.257.02:54:26.20:scan_name=257-0256,jd0609,200 2006.257.02:54:26.20:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.257.02:54:27.13#flagr#flagr/antenna,new-source 2006.257.02:54:27.13:checkk5 2006.257.02:54:27.58/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:54:28.06/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:54:28.47/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:54:29.06/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:54:29.45/chk_obsdata//k5ts1/T2570253??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:54:29.84/chk_obsdata//k5ts2/T2570253??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:54:30.21/chk_obsdata//k5ts3/T2570253??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:54:30.64/chk_obsdata//k5ts4/T2570253??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.02:54:31.40/k5log//k5ts1_log_newline 2006.257.02:54:32.17/k5log//k5ts2_log_newline 2006.257.02:54:33.07/k5log//k5ts3_log_newline 2006.257.02:54:33.88/k5log//k5ts4_log_newline 2006.257.02:54:33.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:54:33.90:setupk4=1 2006.257.02:54:33.90$setupk4/echo=on 2006.257.02:54:33.90$setupk4/pcalon 2006.257.02:54:33.90$pcalon/"no phase cal control is implemented here 2006.257.02:54:33.90$setupk4/"tpicd=stop 2006.257.02:54:33.90$setupk4/"rec=synch_on 2006.257.02:54:33.90$setupk4/"rec_mode=128 2006.257.02:54:33.90$setupk4/!* 2006.257.02:54:33.90$setupk4/recpk4 2006.257.02:54:33.90$recpk4/recpatch= 2006.257.02:54:33.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:54:33.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:54:33.91$setupk4/vck44 2006.257.02:54:33.91$vck44/valo=1,524.99 2006.257.02:54:33.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.02:54:33.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.02:54:33.91#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:33.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:54:33.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:54:33.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:54:33.91#ibcon#enter wrdev, iclass 28, count 0 2006.257.02:54:33.91#ibcon#first serial, iclass 28, count 0 2006.257.02:54:33.91#ibcon#enter sib2, iclass 28, count 0 2006.257.02:54:33.91#ibcon#flushed, iclass 28, count 0 2006.257.02:54:33.91#ibcon#about to write, iclass 28, count 0 2006.257.02:54:33.91#ibcon#wrote, iclass 28, count 0 2006.257.02:54:33.91#ibcon#about to read 3, iclass 28, count 0 2006.257.02:54:33.94#ibcon#read 3, iclass 28, count 0 2006.257.02:54:33.94#ibcon#about to read 4, iclass 28, count 0 2006.257.02:54:33.94#ibcon#read 4, iclass 28, count 0 2006.257.02:54:33.94#ibcon#about to read 5, iclass 28, count 0 2006.257.02:54:33.94#ibcon#read 5, iclass 28, count 0 2006.257.02:54:33.94#ibcon#about to read 6, iclass 28, count 0 2006.257.02:54:33.94#ibcon#read 6, iclass 28, count 0 2006.257.02:54:33.94#ibcon#end of sib2, iclass 28, count 0 2006.257.02:54:33.94#ibcon#*mode == 0, iclass 28, count 0 2006.257.02:54:33.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.02:54:33.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:54:33.94#ibcon#*before write, iclass 28, count 0 2006.257.02:54:33.94#ibcon#enter sib2, iclass 28, count 0 2006.257.02:54:33.94#ibcon#flushed, iclass 28, count 0 2006.257.02:54:33.94#ibcon#about to write, iclass 28, count 0 2006.257.02:54:33.94#ibcon#wrote, iclass 28, count 0 2006.257.02:54:33.94#ibcon#about to read 3, iclass 28, count 0 2006.257.02:54:33.99#ibcon#read 3, iclass 28, count 0 2006.257.02:54:33.99#ibcon#about to read 4, iclass 28, count 0 2006.257.02:54:33.99#ibcon#read 4, iclass 28, count 0 2006.257.02:54:33.99#ibcon#about to read 5, iclass 28, count 0 2006.257.02:54:33.99#ibcon#read 5, iclass 28, count 0 2006.257.02:54:33.99#ibcon#about to read 6, iclass 28, count 0 2006.257.02:54:33.99#ibcon#read 6, iclass 28, count 0 2006.257.02:54:33.99#ibcon#end of sib2, iclass 28, count 0 2006.257.02:54:33.99#ibcon#*after write, iclass 28, count 0 2006.257.02:54:33.99#ibcon#*before return 0, iclass 28, count 0 2006.257.02:54:33.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:54:33.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.02:54:33.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.02:54:33.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.02:54:33.99$vck44/va=1,8 2006.257.02:54:33.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.02:54:33.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.02:54:33.99#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:33.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:54:33.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:54:33.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:54:33.99#ibcon#enter wrdev, iclass 30, count 2 2006.257.02:54:33.99#ibcon#first serial, iclass 30, count 2 2006.257.02:54:33.99#ibcon#enter sib2, iclass 30, count 2 2006.257.02:54:33.99#ibcon#flushed, iclass 30, count 2 2006.257.02:54:33.99#ibcon#about to write, iclass 30, count 2 2006.257.02:54:33.99#ibcon#wrote, iclass 30, count 2 2006.257.02:54:33.99#ibcon#about to read 3, iclass 30, count 2 2006.257.02:54:34.01#ibcon#read 3, iclass 30, count 2 2006.257.02:54:34.01#ibcon#about to read 4, iclass 30, count 2 2006.257.02:54:34.01#ibcon#read 4, iclass 30, count 2 2006.257.02:54:34.01#ibcon#about to read 5, iclass 30, count 2 2006.257.02:54:34.01#ibcon#read 5, iclass 30, count 2 2006.257.02:54:34.01#ibcon#about to read 6, iclass 30, count 2 2006.257.02:54:34.01#ibcon#read 6, iclass 30, count 2 2006.257.02:54:34.01#ibcon#end of sib2, iclass 30, count 2 2006.257.02:54:34.01#ibcon#*mode == 0, iclass 30, count 2 2006.257.02:54:34.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.02:54:34.01#ibcon#[25=AT01-08\r\n] 2006.257.02:54:34.01#ibcon#*before write, iclass 30, count 2 2006.257.02:54:34.01#ibcon#enter sib2, iclass 30, count 2 2006.257.02:54:34.01#ibcon#flushed, iclass 30, count 2 2006.257.02:54:34.01#ibcon#about to write, iclass 30, count 2 2006.257.02:54:34.01#ibcon#wrote, iclass 30, count 2 2006.257.02:54:34.01#ibcon#about to read 3, iclass 30, count 2 2006.257.02:54:34.04#ibcon#read 3, iclass 30, count 2 2006.257.02:54:34.04#ibcon#about to read 4, iclass 30, count 2 2006.257.02:54:34.04#ibcon#read 4, iclass 30, count 2 2006.257.02:54:34.04#ibcon#about to read 5, iclass 30, count 2 2006.257.02:54:34.04#ibcon#read 5, iclass 30, count 2 2006.257.02:54:34.04#ibcon#about to read 6, iclass 30, count 2 2006.257.02:54:34.04#ibcon#read 6, iclass 30, count 2 2006.257.02:54:34.04#ibcon#end of sib2, iclass 30, count 2 2006.257.02:54:34.04#ibcon#*after write, iclass 30, count 2 2006.257.02:54:34.04#ibcon#*before return 0, iclass 30, count 2 2006.257.02:54:34.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:54:34.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.02:54:34.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.02:54:34.04#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:34.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:54:34.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:54:34.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:54:34.16#ibcon#enter wrdev, iclass 30, count 0 2006.257.02:54:34.16#ibcon#first serial, iclass 30, count 0 2006.257.02:54:34.16#ibcon#enter sib2, iclass 30, count 0 2006.257.02:54:34.16#ibcon#flushed, iclass 30, count 0 2006.257.02:54:34.16#ibcon#about to write, iclass 30, count 0 2006.257.02:54:34.16#ibcon#wrote, iclass 30, count 0 2006.257.02:54:34.16#ibcon#about to read 3, iclass 30, count 0 2006.257.02:54:34.18#ibcon#read 3, iclass 30, count 0 2006.257.02:54:34.18#ibcon#about to read 4, iclass 30, count 0 2006.257.02:54:34.18#ibcon#read 4, iclass 30, count 0 2006.257.02:54:34.18#ibcon#about to read 5, iclass 30, count 0 2006.257.02:54:34.18#ibcon#read 5, iclass 30, count 0 2006.257.02:54:34.18#ibcon#about to read 6, iclass 30, count 0 2006.257.02:54:34.18#ibcon#read 6, iclass 30, count 0 2006.257.02:54:34.18#ibcon#end of sib2, iclass 30, count 0 2006.257.02:54:34.18#ibcon#*mode == 0, iclass 30, count 0 2006.257.02:54:34.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.02:54:34.18#ibcon#[25=USB\r\n] 2006.257.02:54:34.18#ibcon#*before write, iclass 30, count 0 2006.257.02:54:34.18#ibcon#enter sib2, iclass 30, count 0 2006.257.02:54:34.18#ibcon#flushed, iclass 30, count 0 2006.257.02:54:34.18#ibcon#about to write, iclass 30, count 0 2006.257.02:54:34.18#ibcon#wrote, iclass 30, count 0 2006.257.02:54:34.18#ibcon#about to read 3, iclass 30, count 0 2006.257.02:54:34.21#ibcon#read 3, iclass 30, count 0 2006.257.02:54:34.21#ibcon#about to read 4, iclass 30, count 0 2006.257.02:54:34.21#ibcon#read 4, iclass 30, count 0 2006.257.02:54:34.21#ibcon#about to read 5, iclass 30, count 0 2006.257.02:54:34.21#ibcon#read 5, iclass 30, count 0 2006.257.02:54:34.21#ibcon#about to read 6, iclass 30, count 0 2006.257.02:54:34.21#ibcon#read 6, iclass 30, count 0 2006.257.02:54:34.21#ibcon#end of sib2, iclass 30, count 0 2006.257.02:54:34.21#ibcon#*after write, iclass 30, count 0 2006.257.02:54:34.21#ibcon#*before return 0, iclass 30, count 0 2006.257.02:54:34.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:54:34.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.02:54:34.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.02:54:34.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.02:54:34.21$vck44/valo=2,534.99 2006.257.02:54:34.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.02:54:34.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.02:54:34.21#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:34.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:34.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:34.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:34.21#ibcon#enter wrdev, iclass 32, count 0 2006.257.02:54:34.21#ibcon#first serial, iclass 32, count 0 2006.257.02:54:34.21#ibcon#enter sib2, iclass 32, count 0 2006.257.02:54:34.21#ibcon#flushed, iclass 32, count 0 2006.257.02:54:34.21#ibcon#about to write, iclass 32, count 0 2006.257.02:54:34.21#ibcon#wrote, iclass 32, count 0 2006.257.02:54:34.21#ibcon#about to read 3, iclass 32, count 0 2006.257.02:54:34.23#ibcon#read 3, iclass 32, count 0 2006.257.02:54:34.23#ibcon#about to read 4, iclass 32, count 0 2006.257.02:54:34.23#ibcon#read 4, iclass 32, count 0 2006.257.02:54:34.23#ibcon#about to read 5, iclass 32, count 0 2006.257.02:54:34.23#ibcon#read 5, iclass 32, count 0 2006.257.02:54:34.23#ibcon#about to read 6, iclass 32, count 0 2006.257.02:54:34.23#ibcon#read 6, iclass 32, count 0 2006.257.02:54:34.23#ibcon#end of sib2, iclass 32, count 0 2006.257.02:54:34.23#ibcon#*mode == 0, iclass 32, count 0 2006.257.02:54:34.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.02:54:34.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:54:34.23#ibcon#*before write, iclass 32, count 0 2006.257.02:54:34.23#ibcon#enter sib2, iclass 32, count 0 2006.257.02:54:34.23#ibcon#flushed, iclass 32, count 0 2006.257.02:54:34.23#ibcon#about to write, iclass 32, count 0 2006.257.02:54:34.23#ibcon#wrote, iclass 32, count 0 2006.257.02:54:34.23#ibcon#about to read 3, iclass 32, count 0 2006.257.02:54:34.27#ibcon#read 3, iclass 32, count 0 2006.257.02:54:34.27#ibcon#about to read 4, iclass 32, count 0 2006.257.02:54:34.27#ibcon#read 4, iclass 32, count 0 2006.257.02:54:34.27#ibcon#about to read 5, iclass 32, count 0 2006.257.02:54:34.27#ibcon#read 5, iclass 32, count 0 2006.257.02:54:34.27#ibcon#about to read 6, iclass 32, count 0 2006.257.02:54:34.27#ibcon#read 6, iclass 32, count 0 2006.257.02:54:34.27#ibcon#end of sib2, iclass 32, count 0 2006.257.02:54:34.27#ibcon#*after write, iclass 32, count 0 2006.257.02:54:34.27#ibcon#*before return 0, iclass 32, count 0 2006.257.02:54:34.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:34.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:34.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.02:54:34.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.02:54:34.27$vck44/va=2,7 2006.257.02:54:34.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.02:54:34.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.02:54:34.27#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:34.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:34.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:34.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:34.33#ibcon#enter wrdev, iclass 34, count 2 2006.257.02:54:34.33#ibcon#first serial, iclass 34, count 2 2006.257.02:54:34.33#ibcon#enter sib2, iclass 34, count 2 2006.257.02:54:34.33#ibcon#flushed, iclass 34, count 2 2006.257.02:54:34.33#ibcon#about to write, iclass 34, count 2 2006.257.02:54:34.33#ibcon#wrote, iclass 34, count 2 2006.257.02:54:34.33#ibcon#about to read 3, iclass 34, count 2 2006.257.02:54:34.35#ibcon#read 3, iclass 34, count 2 2006.257.02:54:34.35#ibcon#about to read 4, iclass 34, count 2 2006.257.02:54:34.35#ibcon#read 4, iclass 34, count 2 2006.257.02:54:34.35#ibcon#about to read 5, iclass 34, count 2 2006.257.02:54:34.35#ibcon#read 5, iclass 34, count 2 2006.257.02:54:34.35#ibcon#about to read 6, iclass 34, count 2 2006.257.02:54:34.35#ibcon#read 6, iclass 34, count 2 2006.257.02:54:34.35#ibcon#end of sib2, iclass 34, count 2 2006.257.02:54:34.35#ibcon#*mode == 0, iclass 34, count 2 2006.257.02:54:34.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.02:54:34.35#ibcon#[25=AT02-07\r\n] 2006.257.02:54:34.35#ibcon#*before write, iclass 34, count 2 2006.257.02:54:34.35#ibcon#enter sib2, iclass 34, count 2 2006.257.02:54:34.35#ibcon#flushed, iclass 34, count 2 2006.257.02:54:34.35#ibcon#about to write, iclass 34, count 2 2006.257.02:54:34.35#ibcon#wrote, iclass 34, count 2 2006.257.02:54:34.35#ibcon#about to read 3, iclass 34, count 2 2006.257.02:54:34.38#ibcon#read 3, iclass 34, count 2 2006.257.02:54:34.38#ibcon#about to read 4, iclass 34, count 2 2006.257.02:54:34.38#ibcon#read 4, iclass 34, count 2 2006.257.02:54:34.38#ibcon#about to read 5, iclass 34, count 2 2006.257.02:54:34.38#ibcon#read 5, iclass 34, count 2 2006.257.02:54:34.38#ibcon#about to read 6, iclass 34, count 2 2006.257.02:54:34.38#ibcon#read 6, iclass 34, count 2 2006.257.02:54:34.38#ibcon#end of sib2, iclass 34, count 2 2006.257.02:54:34.38#ibcon#*after write, iclass 34, count 2 2006.257.02:54:34.38#ibcon#*before return 0, iclass 34, count 2 2006.257.02:54:34.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:34.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:34.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.02:54:34.38#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:34.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:34.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:34.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:34.50#ibcon#enter wrdev, iclass 34, count 0 2006.257.02:54:34.50#ibcon#first serial, iclass 34, count 0 2006.257.02:54:34.50#ibcon#enter sib2, iclass 34, count 0 2006.257.02:54:34.50#ibcon#flushed, iclass 34, count 0 2006.257.02:54:34.50#ibcon#about to write, iclass 34, count 0 2006.257.02:54:34.50#ibcon#wrote, iclass 34, count 0 2006.257.02:54:34.50#ibcon#about to read 3, iclass 34, count 0 2006.257.02:54:34.52#ibcon#read 3, iclass 34, count 0 2006.257.02:54:34.52#ibcon#about to read 4, iclass 34, count 0 2006.257.02:54:34.52#ibcon#read 4, iclass 34, count 0 2006.257.02:54:34.52#ibcon#about to read 5, iclass 34, count 0 2006.257.02:54:34.52#ibcon#read 5, iclass 34, count 0 2006.257.02:54:34.52#ibcon#about to read 6, iclass 34, count 0 2006.257.02:54:34.52#ibcon#read 6, iclass 34, count 0 2006.257.02:54:34.52#ibcon#end of sib2, iclass 34, count 0 2006.257.02:54:34.52#ibcon#*mode == 0, iclass 34, count 0 2006.257.02:54:34.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.02:54:34.52#ibcon#[25=USB\r\n] 2006.257.02:54:34.52#ibcon#*before write, iclass 34, count 0 2006.257.02:54:34.52#ibcon#enter sib2, iclass 34, count 0 2006.257.02:54:34.52#ibcon#flushed, iclass 34, count 0 2006.257.02:54:34.52#ibcon#about to write, iclass 34, count 0 2006.257.02:54:34.52#ibcon#wrote, iclass 34, count 0 2006.257.02:54:34.52#ibcon#about to read 3, iclass 34, count 0 2006.257.02:54:34.55#ibcon#read 3, iclass 34, count 0 2006.257.02:54:34.55#ibcon#about to read 4, iclass 34, count 0 2006.257.02:54:34.55#ibcon#read 4, iclass 34, count 0 2006.257.02:54:34.55#ibcon#about to read 5, iclass 34, count 0 2006.257.02:54:34.55#ibcon#read 5, iclass 34, count 0 2006.257.02:54:34.55#ibcon#about to read 6, iclass 34, count 0 2006.257.02:54:34.55#ibcon#read 6, iclass 34, count 0 2006.257.02:54:34.55#ibcon#end of sib2, iclass 34, count 0 2006.257.02:54:34.55#ibcon#*after write, iclass 34, count 0 2006.257.02:54:34.55#ibcon#*before return 0, iclass 34, count 0 2006.257.02:54:34.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:34.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:34.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.02:54:34.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.02:54:34.55$vck44/valo=3,564.99 2006.257.02:54:34.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.02:54:34.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.02:54:34.55#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:34.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:34.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:34.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:34.55#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:54:34.55#ibcon#first serial, iclass 36, count 0 2006.257.02:54:34.55#ibcon#enter sib2, iclass 36, count 0 2006.257.02:54:34.55#ibcon#flushed, iclass 36, count 0 2006.257.02:54:34.55#ibcon#about to write, iclass 36, count 0 2006.257.02:54:34.55#ibcon#wrote, iclass 36, count 0 2006.257.02:54:34.55#ibcon#about to read 3, iclass 36, count 0 2006.257.02:54:34.57#ibcon#read 3, iclass 36, count 0 2006.257.02:54:34.57#ibcon#about to read 4, iclass 36, count 0 2006.257.02:54:34.57#ibcon#read 4, iclass 36, count 0 2006.257.02:54:34.57#ibcon#about to read 5, iclass 36, count 0 2006.257.02:54:34.57#ibcon#read 5, iclass 36, count 0 2006.257.02:54:34.57#ibcon#about to read 6, iclass 36, count 0 2006.257.02:54:34.57#ibcon#read 6, iclass 36, count 0 2006.257.02:54:34.57#ibcon#end of sib2, iclass 36, count 0 2006.257.02:54:34.57#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:54:34.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:54:34.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:54:34.57#ibcon#*before write, iclass 36, count 0 2006.257.02:54:34.57#ibcon#enter sib2, iclass 36, count 0 2006.257.02:54:34.57#ibcon#flushed, iclass 36, count 0 2006.257.02:54:34.57#ibcon#about to write, iclass 36, count 0 2006.257.02:54:34.57#ibcon#wrote, iclass 36, count 0 2006.257.02:54:34.57#ibcon#about to read 3, iclass 36, count 0 2006.257.02:54:34.61#ibcon#read 3, iclass 36, count 0 2006.257.02:54:34.61#ibcon#about to read 4, iclass 36, count 0 2006.257.02:54:34.61#ibcon#read 4, iclass 36, count 0 2006.257.02:54:34.61#ibcon#about to read 5, iclass 36, count 0 2006.257.02:54:34.61#ibcon#read 5, iclass 36, count 0 2006.257.02:54:34.61#ibcon#about to read 6, iclass 36, count 0 2006.257.02:54:34.61#ibcon#read 6, iclass 36, count 0 2006.257.02:54:34.61#ibcon#end of sib2, iclass 36, count 0 2006.257.02:54:34.61#ibcon#*after write, iclass 36, count 0 2006.257.02:54:34.61#ibcon#*before return 0, iclass 36, count 0 2006.257.02:54:34.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:34.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:34.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:54:34.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:54:34.61$vck44/va=3,8 2006.257.02:54:34.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.02:54:34.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.02:54:34.61#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:34.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:34.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:34.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:34.67#ibcon#enter wrdev, iclass 38, count 2 2006.257.02:54:34.67#ibcon#first serial, iclass 38, count 2 2006.257.02:54:34.67#ibcon#enter sib2, iclass 38, count 2 2006.257.02:54:34.67#ibcon#flushed, iclass 38, count 2 2006.257.02:54:34.67#ibcon#about to write, iclass 38, count 2 2006.257.02:54:34.67#ibcon#wrote, iclass 38, count 2 2006.257.02:54:34.67#ibcon#about to read 3, iclass 38, count 2 2006.257.02:54:34.69#ibcon#read 3, iclass 38, count 2 2006.257.02:54:34.69#ibcon#about to read 4, iclass 38, count 2 2006.257.02:54:34.69#ibcon#read 4, iclass 38, count 2 2006.257.02:54:34.69#ibcon#about to read 5, iclass 38, count 2 2006.257.02:54:34.69#ibcon#read 5, iclass 38, count 2 2006.257.02:54:34.69#ibcon#about to read 6, iclass 38, count 2 2006.257.02:54:34.69#ibcon#read 6, iclass 38, count 2 2006.257.02:54:34.69#ibcon#end of sib2, iclass 38, count 2 2006.257.02:54:34.69#ibcon#*mode == 0, iclass 38, count 2 2006.257.02:54:34.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.02:54:34.69#ibcon#[25=AT03-08\r\n] 2006.257.02:54:34.69#ibcon#*before write, iclass 38, count 2 2006.257.02:54:34.69#ibcon#enter sib2, iclass 38, count 2 2006.257.02:54:34.69#ibcon#flushed, iclass 38, count 2 2006.257.02:54:34.69#ibcon#about to write, iclass 38, count 2 2006.257.02:54:34.69#ibcon#wrote, iclass 38, count 2 2006.257.02:54:34.69#ibcon#about to read 3, iclass 38, count 2 2006.257.02:54:34.72#ibcon#read 3, iclass 38, count 2 2006.257.02:54:34.72#ibcon#about to read 4, iclass 38, count 2 2006.257.02:54:34.72#ibcon#read 4, iclass 38, count 2 2006.257.02:54:34.72#ibcon#about to read 5, iclass 38, count 2 2006.257.02:54:34.72#ibcon#read 5, iclass 38, count 2 2006.257.02:54:34.72#ibcon#about to read 6, iclass 38, count 2 2006.257.02:54:34.72#ibcon#read 6, iclass 38, count 2 2006.257.02:54:34.72#ibcon#end of sib2, iclass 38, count 2 2006.257.02:54:34.72#ibcon#*after write, iclass 38, count 2 2006.257.02:54:34.72#ibcon#*before return 0, iclass 38, count 2 2006.257.02:54:34.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:34.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:34.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.02:54:34.72#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:34.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:34.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:34.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:34.84#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:54:34.84#ibcon#first serial, iclass 38, count 0 2006.257.02:54:34.84#ibcon#enter sib2, iclass 38, count 0 2006.257.02:54:34.84#ibcon#flushed, iclass 38, count 0 2006.257.02:54:34.84#ibcon#about to write, iclass 38, count 0 2006.257.02:54:34.84#ibcon#wrote, iclass 38, count 0 2006.257.02:54:34.84#ibcon#about to read 3, iclass 38, count 0 2006.257.02:54:34.86#ibcon#read 3, iclass 38, count 0 2006.257.02:54:34.86#ibcon#about to read 4, iclass 38, count 0 2006.257.02:54:34.86#ibcon#read 4, iclass 38, count 0 2006.257.02:54:34.86#ibcon#about to read 5, iclass 38, count 0 2006.257.02:54:34.86#ibcon#read 5, iclass 38, count 0 2006.257.02:54:34.86#ibcon#about to read 6, iclass 38, count 0 2006.257.02:54:34.86#ibcon#read 6, iclass 38, count 0 2006.257.02:54:34.86#ibcon#end of sib2, iclass 38, count 0 2006.257.02:54:34.86#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:54:34.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:54:34.86#ibcon#[25=USB\r\n] 2006.257.02:54:34.86#ibcon#*before write, iclass 38, count 0 2006.257.02:54:34.86#ibcon#enter sib2, iclass 38, count 0 2006.257.02:54:34.86#ibcon#flushed, iclass 38, count 0 2006.257.02:54:34.86#ibcon#about to write, iclass 38, count 0 2006.257.02:54:34.86#ibcon#wrote, iclass 38, count 0 2006.257.02:54:34.86#ibcon#about to read 3, iclass 38, count 0 2006.257.02:54:34.89#ibcon#read 3, iclass 38, count 0 2006.257.02:54:34.89#ibcon#about to read 4, iclass 38, count 0 2006.257.02:54:34.89#ibcon#read 4, iclass 38, count 0 2006.257.02:54:34.89#ibcon#about to read 5, iclass 38, count 0 2006.257.02:54:34.89#ibcon#read 5, iclass 38, count 0 2006.257.02:54:34.89#ibcon#about to read 6, iclass 38, count 0 2006.257.02:54:34.89#ibcon#read 6, iclass 38, count 0 2006.257.02:54:34.89#ibcon#end of sib2, iclass 38, count 0 2006.257.02:54:34.89#ibcon#*after write, iclass 38, count 0 2006.257.02:54:34.89#ibcon#*before return 0, iclass 38, count 0 2006.257.02:54:34.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:34.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:34.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:54:34.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:54:34.89$vck44/valo=4,624.99 2006.257.02:54:34.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.02:54:34.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.02:54:34.89#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:34.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:34.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:34.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:34.89#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:54:34.89#ibcon#first serial, iclass 40, count 0 2006.257.02:54:34.89#ibcon#enter sib2, iclass 40, count 0 2006.257.02:54:34.89#ibcon#flushed, iclass 40, count 0 2006.257.02:54:34.89#ibcon#about to write, iclass 40, count 0 2006.257.02:54:34.89#ibcon#wrote, iclass 40, count 0 2006.257.02:54:34.89#ibcon#about to read 3, iclass 40, count 0 2006.257.02:54:34.91#ibcon#read 3, iclass 40, count 0 2006.257.02:54:34.91#ibcon#about to read 4, iclass 40, count 0 2006.257.02:54:34.91#ibcon#read 4, iclass 40, count 0 2006.257.02:54:34.91#ibcon#about to read 5, iclass 40, count 0 2006.257.02:54:34.91#ibcon#read 5, iclass 40, count 0 2006.257.02:54:34.91#ibcon#about to read 6, iclass 40, count 0 2006.257.02:54:34.91#ibcon#read 6, iclass 40, count 0 2006.257.02:54:34.91#ibcon#end of sib2, iclass 40, count 0 2006.257.02:54:34.91#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:54:34.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:54:34.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:54:34.91#ibcon#*before write, iclass 40, count 0 2006.257.02:54:34.91#ibcon#enter sib2, iclass 40, count 0 2006.257.02:54:34.91#ibcon#flushed, iclass 40, count 0 2006.257.02:54:34.91#ibcon#about to write, iclass 40, count 0 2006.257.02:54:34.91#ibcon#wrote, iclass 40, count 0 2006.257.02:54:34.91#ibcon#about to read 3, iclass 40, count 0 2006.257.02:54:34.95#ibcon#read 3, iclass 40, count 0 2006.257.02:54:34.95#ibcon#about to read 4, iclass 40, count 0 2006.257.02:54:34.95#ibcon#read 4, iclass 40, count 0 2006.257.02:54:34.95#ibcon#about to read 5, iclass 40, count 0 2006.257.02:54:34.95#ibcon#read 5, iclass 40, count 0 2006.257.02:54:34.95#ibcon#about to read 6, iclass 40, count 0 2006.257.02:54:34.95#ibcon#read 6, iclass 40, count 0 2006.257.02:54:34.95#ibcon#end of sib2, iclass 40, count 0 2006.257.02:54:34.95#ibcon#*after write, iclass 40, count 0 2006.257.02:54:34.95#ibcon#*before return 0, iclass 40, count 0 2006.257.02:54:34.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:34.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:34.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:54:34.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:54:34.95$vck44/va=4,7 2006.257.02:54:34.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.02:54:34.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.02:54:34.95#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:34.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:35.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:35.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:35.01#ibcon#enter wrdev, iclass 4, count 2 2006.257.02:54:35.01#ibcon#first serial, iclass 4, count 2 2006.257.02:54:35.01#ibcon#enter sib2, iclass 4, count 2 2006.257.02:54:35.01#ibcon#flushed, iclass 4, count 2 2006.257.02:54:35.01#ibcon#about to write, iclass 4, count 2 2006.257.02:54:35.01#ibcon#wrote, iclass 4, count 2 2006.257.02:54:35.01#ibcon#about to read 3, iclass 4, count 2 2006.257.02:54:35.03#ibcon#read 3, iclass 4, count 2 2006.257.02:54:35.03#ibcon#about to read 4, iclass 4, count 2 2006.257.02:54:35.03#ibcon#read 4, iclass 4, count 2 2006.257.02:54:35.03#ibcon#about to read 5, iclass 4, count 2 2006.257.02:54:35.03#ibcon#read 5, iclass 4, count 2 2006.257.02:54:35.03#ibcon#about to read 6, iclass 4, count 2 2006.257.02:54:35.03#ibcon#read 6, iclass 4, count 2 2006.257.02:54:35.03#ibcon#end of sib2, iclass 4, count 2 2006.257.02:54:35.03#ibcon#*mode == 0, iclass 4, count 2 2006.257.02:54:35.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.02:54:35.03#ibcon#[25=AT04-07\r\n] 2006.257.02:54:35.03#ibcon#*before write, iclass 4, count 2 2006.257.02:54:35.03#ibcon#enter sib2, iclass 4, count 2 2006.257.02:54:35.03#ibcon#flushed, iclass 4, count 2 2006.257.02:54:35.03#ibcon#about to write, iclass 4, count 2 2006.257.02:54:35.03#ibcon#wrote, iclass 4, count 2 2006.257.02:54:35.03#ibcon#about to read 3, iclass 4, count 2 2006.257.02:54:35.06#ibcon#read 3, iclass 4, count 2 2006.257.02:54:35.06#ibcon#about to read 4, iclass 4, count 2 2006.257.02:54:35.06#ibcon#read 4, iclass 4, count 2 2006.257.02:54:35.06#ibcon#about to read 5, iclass 4, count 2 2006.257.02:54:35.06#ibcon#read 5, iclass 4, count 2 2006.257.02:54:35.06#ibcon#about to read 6, iclass 4, count 2 2006.257.02:54:35.06#ibcon#read 6, iclass 4, count 2 2006.257.02:54:35.06#ibcon#end of sib2, iclass 4, count 2 2006.257.02:54:35.06#ibcon#*after write, iclass 4, count 2 2006.257.02:54:35.06#ibcon#*before return 0, iclass 4, count 2 2006.257.02:54:35.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:35.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:35.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.02:54:35.06#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:35.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:35.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:35.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:35.18#ibcon#enter wrdev, iclass 4, count 0 2006.257.02:54:35.18#ibcon#first serial, iclass 4, count 0 2006.257.02:54:35.18#ibcon#enter sib2, iclass 4, count 0 2006.257.02:54:35.18#ibcon#flushed, iclass 4, count 0 2006.257.02:54:35.18#ibcon#about to write, iclass 4, count 0 2006.257.02:54:35.18#ibcon#wrote, iclass 4, count 0 2006.257.02:54:35.18#ibcon#about to read 3, iclass 4, count 0 2006.257.02:54:35.20#ibcon#read 3, iclass 4, count 0 2006.257.02:54:35.20#ibcon#about to read 4, iclass 4, count 0 2006.257.02:54:35.20#ibcon#read 4, iclass 4, count 0 2006.257.02:54:35.20#ibcon#about to read 5, iclass 4, count 0 2006.257.02:54:35.20#ibcon#read 5, iclass 4, count 0 2006.257.02:54:35.20#ibcon#about to read 6, iclass 4, count 0 2006.257.02:54:35.20#ibcon#read 6, iclass 4, count 0 2006.257.02:54:35.20#ibcon#end of sib2, iclass 4, count 0 2006.257.02:54:35.20#ibcon#*mode == 0, iclass 4, count 0 2006.257.02:54:35.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.02:54:35.20#ibcon#[25=USB\r\n] 2006.257.02:54:35.20#ibcon#*before write, iclass 4, count 0 2006.257.02:54:35.20#ibcon#enter sib2, iclass 4, count 0 2006.257.02:54:35.20#ibcon#flushed, iclass 4, count 0 2006.257.02:54:35.20#ibcon#about to write, iclass 4, count 0 2006.257.02:54:35.20#ibcon#wrote, iclass 4, count 0 2006.257.02:54:35.20#ibcon#about to read 3, iclass 4, count 0 2006.257.02:54:35.23#ibcon#read 3, iclass 4, count 0 2006.257.02:54:35.23#ibcon#about to read 4, iclass 4, count 0 2006.257.02:54:35.23#ibcon#read 4, iclass 4, count 0 2006.257.02:54:35.23#ibcon#about to read 5, iclass 4, count 0 2006.257.02:54:35.23#ibcon#read 5, iclass 4, count 0 2006.257.02:54:35.23#ibcon#about to read 6, iclass 4, count 0 2006.257.02:54:35.23#ibcon#read 6, iclass 4, count 0 2006.257.02:54:35.23#ibcon#end of sib2, iclass 4, count 0 2006.257.02:54:35.23#ibcon#*after write, iclass 4, count 0 2006.257.02:54:35.23#ibcon#*before return 0, iclass 4, count 0 2006.257.02:54:35.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:35.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:35.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.02:54:35.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.02:54:35.23$vck44/valo=5,734.99 2006.257.02:54:35.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.02:54:35.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.02:54:35.23#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:35.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:35.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:35.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:35.23#ibcon#enter wrdev, iclass 6, count 0 2006.257.02:54:35.23#ibcon#first serial, iclass 6, count 0 2006.257.02:54:35.23#ibcon#enter sib2, iclass 6, count 0 2006.257.02:54:35.23#ibcon#flushed, iclass 6, count 0 2006.257.02:54:35.23#ibcon#about to write, iclass 6, count 0 2006.257.02:54:35.23#ibcon#wrote, iclass 6, count 0 2006.257.02:54:35.23#ibcon#about to read 3, iclass 6, count 0 2006.257.02:54:35.25#ibcon#read 3, iclass 6, count 0 2006.257.02:54:35.25#ibcon#about to read 4, iclass 6, count 0 2006.257.02:54:35.25#ibcon#read 4, iclass 6, count 0 2006.257.02:54:35.25#ibcon#about to read 5, iclass 6, count 0 2006.257.02:54:35.25#ibcon#read 5, iclass 6, count 0 2006.257.02:54:35.25#ibcon#about to read 6, iclass 6, count 0 2006.257.02:54:35.25#ibcon#read 6, iclass 6, count 0 2006.257.02:54:35.25#ibcon#end of sib2, iclass 6, count 0 2006.257.02:54:35.25#ibcon#*mode == 0, iclass 6, count 0 2006.257.02:54:35.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.02:54:35.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:54:35.25#ibcon#*before write, iclass 6, count 0 2006.257.02:54:35.25#ibcon#enter sib2, iclass 6, count 0 2006.257.02:54:35.25#ibcon#flushed, iclass 6, count 0 2006.257.02:54:35.25#ibcon#about to write, iclass 6, count 0 2006.257.02:54:35.25#ibcon#wrote, iclass 6, count 0 2006.257.02:54:35.25#ibcon#about to read 3, iclass 6, count 0 2006.257.02:54:35.29#ibcon#read 3, iclass 6, count 0 2006.257.02:54:35.29#ibcon#about to read 4, iclass 6, count 0 2006.257.02:54:35.29#ibcon#read 4, iclass 6, count 0 2006.257.02:54:35.29#ibcon#about to read 5, iclass 6, count 0 2006.257.02:54:35.29#ibcon#read 5, iclass 6, count 0 2006.257.02:54:35.29#ibcon#about to read 6, iclass 6, count 0 2006.257.02:54:35.29#ibcon#read 6, iclass 6, count 0 2006.257.02:54:35.29#ibcon#end of sib2, iclass 6, count 0 2006.257.02:54:35.29#ibcon#*after write, iclass 6, count 0 2006.257.02:54:35.29#ibcon#*before return 0, iclass 6, count 0 2006.257.02:54:35.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:35.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:35.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.02:54:35.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.02:54:35.29$vck44/va=5,4 2006.257.02:54:35.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.02:54:35.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.02:54:35.29#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:35.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:35.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:35.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:35.35#ibcon#enter wrdev, iclass 10, count 2 2006.257.02:54:35.35#ibcon#first serial, iclass 10, count 2 2006.257.02:54:35.35#ibcon#enter sib2, iclass 10, count 2 2006.257.02:54:35.35#ibcon#flushed, iclass 10, count 2 2006.257.02:54:35.35#ibcon#about to write, iclass 10, count 2 2006.257.02:54:35.35#ibcon#wrote, iclass 10, count 2 2006.257.02:54:35.35#ibcon#about to read 3, iclass 10, count 2 2006.257.02:54:35.37#ibcon#read 3, iclass 10, count 2 2006.257.02:54:35.37#ibcon#about to read 4, iclass 10, count 2 2006.257.02:54:35.37#ibcon#read 4, iclass 10, count 2 2006.257.02:54:35.37#ibcon#about to read 5, iclass 10, count 2 2006.257.02:54:35.37#ibcon#read 5, iclass 10, count 2 2006.257.02:54:35.37#ibcon#about to read 6, iclass 10, count 2 2006.257.02:54:35.37#ibcon#read 6, iclass 10, count 2 2006.257.02:54:35.37#ibcon#end of sib2, iclass 10, count 2 2006.257.02:54:35.37#ibcon#*mode == 0, iclass 10, count 2 2006.257.02:54:35.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.02:54:35.37#ibcon#[25=AT05-04\r\n] 2006.257.02:54:35.37#ibcon#*before write, iclass 10, count 2 2006.257.02:54:35.37#ibcon#enter sib2, iclass 10, count 2 2006.257.02:54:35.37#ibcon#flushed, iclass 10, count 2 2006.257.02:54:35.37#ibcon#about to write, iclass 10, count 2 2006.257.02:54:35.37#ibcon#wrote, iclass 10, count 2 2006.257.02:54:35.37#ibcon#about to read 3, iclass 10, count 2 2006.257.02:54:35.40#ibcon#read 3, iclass 10, count 2 2006.257.02:54:35.40#ibcon#about to read 4, iclass 10, count 2 2006.257.02:54:35.40#ibcon#read 4, iclass 10, count 2 2006.257.02:54:35.40#ibcon#about to read 5, iclass 10, count 2 2006.257.02:54:35.40#ibcon#read 5, iclass 10, count 2 2006.257.02:54:35.40#ibcon#about to read 6, iclass 10, count 2 2006.257.02:54:35.40#ibcon#read 6, iclass 10, count 2 2006.257.02:54:35.40#ibcon#end of sib2, iclass 10, count 2 2006.257.02:54:35.40#ibcon#*after write, iclass 10, count 2 2006.257.02:54:35.40#ibcon#*before return 0, iclass 10, count 2 2006.257.02:54:35.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:35.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:35.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.02:54:35.40#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:35.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:35.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:35.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:35.52#ibcon#enter wrdev, iclass 10, count 0 2006.257.02:54:35.52#ibcon#first serial, iclass 10, count 0 2006.257.02:54:35.52#ibcon#enter sib2, iclass 10, count 0 2006.257.02:54:35.52#ibcon#flushed, iclass 10, count 0 2006.257.02:54:35.52#ibcon#about to write, iclass 10, count 0 2006.257.02:54:35.52#ibcon#wrote, iclass 10, count 0 2006.257.02:54:35.52#ibcon#about to read 3, iclass 10, count 0 2006.257.02:54:35.54#ibcon#read 3, iclass 10, count 0 2006.257.02:54:35.54#ibcon#about to read 4, iclass 10, count 0 2006.257.02:54:35.54#ibcon#read 4, iclass 10, count 0 2006.257.02:54:35.54#ibcon#about to read 5, iclass 10, count 0 2006.257.02:54:35.54#ibcon#read 5, iclass 10, count 0 2006.257.02:54:35.54#ibcon#about to read 6, iclass 10, count 0 2006.257.02:54:35.54#ibcon#read 6, iclass 10, count 0 2006.257.02:54:35.54#ibcon#end of sib2, iclass 10, count 0 2006.257.02:54:35.54#ibcon#*mode == 0, iclass 10, count 0 2006.257.02:54:35.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.02:54:35.54#ibcon#[25=USB\r\n] 2006.257.02:54:35.54#ibcon#*before write, iclass 10, count 0 2006.257.02:54:35.54#ibcon#enter sib2, iclass 10, count 0 2006.257.02:54:35.54#ibcon#flushed, iclass 10, count 0 2006.257.02:54:35.54#ibcon#about to write, iclass 10, count 0 2006.257.02:54:35.54#ibcon#wrote, iclass 10, count 0 2006.257.02:54:35.54#ibcon#about to read 3, iclass 10, count 0 2006.257.02:54:35.57#ibcon#read 3, iclass 10, count 0 2006.257.02:54:35.57#ibcon#about to read 4, iclass 10, count 0 2006.257.02:54:35.57#ibcon#read 4, iclass 10, count 0 2006.257.02:54:35.57#ibcon#about to read 5, iclass 10, count 0 2006.257.02:54:35.57#ibcon#read 5, iclass 10, count 0 2006.257.02:54:35.57#ibcon#about to read 6, iclass 10, count 0 2006.257.02:54:35.57#ibcon#read 6, iclass 10, count 0 2006.257.02:54:35.57#ibcon#end of sib2, iclass 10, count 0 2006.257.02:54:35.57#ibcon#*after write, iclass 10, count 0 2006.257.02:54:35.57#ibcon#*before return 0, iclass 10, count 0 2006.257.02:54:35.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:35.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:35.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.02:54:35.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.02:54:35.57$vck44/valo=6,814.99 2006.257.02:54:35.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.02:54:35.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.02:54:35.57#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:35.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:35.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:35.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:35.57#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:54:35.57#ibcon#first serial, iclass 12, count 0 2006.257.02:54:35.57#ibcon#enter sib2, iclass 12, count 0 2006.257.02:54:35.57#ibcon#flushed, iclass 12, count 0 2006.257.02:54:35.57#ibcon#about to write, iclass 12, count 0 2006.257.02:54:35.57#ibcon#wrote, iclass 12, count 0 2006.257.02:54:35.57#ibcon#about to read 3, iclass 12, count 0 2006.257.02:54:35.59#ibcon#read 3, iclass 12, count 0 2006.257.02:54:35.59#ibcon#about to read 4, iclass 12, count 0 2006.257.02:54:35.59#ibcon#read 4, iclass 12, count 0 2006.257.02:54:35.59#ibcon#about to read 5, iclass 12, count 0 2006.257.02:54:35.59#ibcon#read 5, iclass 12, count 0 2006.257.02:54:35.59#ibcon#about to read 6, iclass 12, count 0 2006.257.02:54:35.59#ibcon#read 6, iclass 12, count 0 2006.257.02:54:35.59#ibcon#end of sib2, iclass 12, count 0 2006.257.02:54:35.59#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:54:35.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:54:35.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:54:35.59#ibcon#*before write, iclass 12, count 0 2006.257.02:54:35.59#ibcon#enter sib2, iclass 12, count 0 2006.257.02:54:35.59#ibcon#flushed, iclass 12, count 0 2006.257.02:54:35.59#ibcon#about to write, iclass 12, count 0 2006.257.02:54:35.59#ibcon#wrote, iclass 12, count 0 2006.257.02:54:35.59#ibcon#about to read 3, iclass 12, count 0 2006.257.02:54:35.63#ibcon#read 3, iclass 12, count 0 2006.257.02:54:35.63#ibcon#about to read 4, iclass 12, count 0 2006.257.02:54:35.63#ibcon#read 4, iclass 12, count 0 2006.257.02:54:35.63#ibcon#about to read 5, iclass 12, count 0 2006.257.02:54:35.63#ibcon#read 5, iclass 12, count 0 2006.257.02:54:35.63#ibcon#about to read 6, iclass 12, count 0 2006.257.02:54:35.63#ibcon#read 6, iclass 12, count 0 2006.257.02:54:35.63#ibcon#end of sib2, iclass 12, count 0 2006.257.02:54:35.63#ibcon#*after write, iclass 12, count 0 2006.257.02:54:35.63#ibcon#*before return 0, iclass 12, count 0 2006.257.02:54:35.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:35.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:35.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:54:35.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:54:35.63$vck44/va=6,4 2006.257.02:54:35.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.02:54:35.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.02:54:35.63#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:35.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:35.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:35.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:35.69#ibcon#enter wrdev, iclass 14, count 2 2006.257.02:54:35.69#ibcon#first serial, iclass 14, count 2 2006.257.02:54:35.69#ibcon#enter sib2, iclass 14, count 2 2006.257.02:54:35.69#ibcon#flushed, iclass 14, count 2 2006.257.02:54:35.69#ibcon#about to write, iclass 14, count 2 2006.257.02:54:35.69#ibcon#wrote, iclass 14, count 2 2006.257.02:54:35.69#ibcon#about to read 3, iclass 14, count 2 2006.257.02:54:35.71#ibcon#read 3, iclass 14, count 2 2006.257.02:54:35.71#ibcon#about to read 4, iclass 14, count 2 2006.257.02:54:35.71#ibcon#read 4, iclass 14, count 2 2006.257.02:54:35.71#ibcon#about to read 5, iclass 14, count 2 2006.257.02:54:35.71#ibcon#read 5, iclass 14, count 2 2006.257.02:54:35.71#ibcon#about to read 6, iclass 14, count 2 2006.257.02:54:35.71#ibcon#read 6, iclass 14, count 2 2006.257.02:54:35.71#ibcon#end of sib2, iclass 14, count 2 2006.257.02:54:35.71#ibcon#*mode == 0, iclass 14, count 2 2006.257.02:54:35.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.02:54:35.71#ibcon#[25=AT06-04\r\n] 2006.257.02:54:35.71#ibcon#*before write, iclass 14, count 2 2006.257.02:54:35.71#ibcon#enter sib2, iclass 14, count 2 2006.257.02:54:35.71#ibcon#flushed, iclass 14, count 2 2006.257.02:54:35.71#ibcon#about to write, iclass 14, count 2 2006.257.02:54:35.71#ibcon#wrote, iclass 14, count 2 2006.257.02:54:35.71#ibcon#about to read 3, iclass 14, count 2 2006.257.02:54:35.74#ibcon#read 3, iclass 14, count 2 2006.257.02:54:35.74#ibcon#about to read 4, iclass 14, count 2 2006.257.02:54:35.74#ibcon#read 4, iclass 14, count 2 2006.257.02:54:35.74#ibcon#about to read 5, iclass 14, count 2 2006.257.02:54:35.74#ibcon#read 5, iclass 14, count 2 2006.257.02:54:35.74#ibcon#about to read 6, iclass 14, count 2 2006.257.02:54:35.74#ibcon#read 6, iclass 14, count 2 2006.257.02:54:35.74#ibcon#end of sib2, iclass 14, count 2 2006.257.02:54:35.74#ibcon#*after write, iclass 14, count 2 2006.257.02:54:35.74#ibcon#*before return 0, iclass 14, count 2 2006.257.02:54:35.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:35.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:35.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.02:54:35.74#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:35.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:35.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:35.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:35.86#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:54:35.86#ibcon#first serial, iclass 14, count 0 2006.257.02:54:35.86#ibcon#enter sib2, iclass 14, count 0 2006.257.02:54:35.86#ibcon#flushed, iclass 14, count 0 2006.257.02:54:35.86#ibcon#about to write, iclass 14, count 0 2006.257.02:54:35.86#ibcon#wrote, iclass 14, count 0 2006.257.02:54:35.86#ibcon#about to read 3, iclass 14, count 0 2006.257.02:54:35.88#ibcon#read 3, iclass 14, count 0 2006.257.02:54:35.88#ibcon#about to read 4, iclass 14, count 0 2006.257.02:54:35.88#ibcon#read 4, iclass 14, count 0 2006.257.02:54:35.88#ibcon#about to read 5, iclass 14, count 0 2006.257.02:54:35.88#ibcon#read 5, iclass 14, count 0 2006.257.02:54:35.88#ibcon#about to read 6, iclass 14, count 0 2006.257.02:54:35.88#ibcon#read 6, iclass 14, count 0 2006.257.02:54:35.88#ibcon#end of sib2, iclass 14, count 0 2006.257.02:54:35.88#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:54:35.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:54:35.88#ibcon#[25=USB\r\n] 2006.257.02:54:35.88#ibcon#*before write, iclass 14, count 0 2006.257.02:54:35.88#ibcon#enter sib2, iclass 14, count 0 2006.257.02:54:35.88#ibcon#flushed, iclass 14, count 0 2006.257.02:54:35.88#ibcon#about to write, iclass 14, count 0 2006.257.02:54:35.88#ibcon#wrote, iclass 14, count 0 2006.257.02:54:35.88#ibcon#about to read 3, iclass 14, count 0 2006.257.02:54:35.91#ibcon#read 3, iclass 14, count 0 2006.257.02:54:35.91#ibcon#about to read 4, iclass 14, count 0 2006.257.02:54:35.91#ibcon#read 4, iclass 14, count 0 2006.257.02:54:35.91#ibcon#about to read 5, iclass 14, count 0 2006.257.02:54:35.91#ibcon#read 5, iclass 14, count 0 2006.257.02:54:35.91#ibcon#about to read 6, iclass 14, count 0 2006.257.02:54:35.91#ibcon#read 6, iclass 14, count 0 2006.257.02:54:35.91#ibcon#end of sib2, iclass 14, count 0 2006.257.02:54:35.91#ibcon#*after write, iclass 14, count 0 2006.257.02:54:35.91#ibcon#*before return 0, iclass 14, count 0 2006.257.02:54:35.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:35.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:35.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:54:35.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:54:35.91$vck44/valo=7,864.99 2006.257.02:54:35.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.02:54:35.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.02:54:35.91#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:35.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:35.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:35.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:35.91#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:54:35.91#ibcon#first serial, iclass 16, count 0 2006.257.02:54:35.91#ibcon#enter sib2, iclass 16, count 0 2006.257.02:54:35.91#ibcon#flushed, iclass 16, count 0 2006.257.02:54:35.91#ibcon#about to write, iclass 16, count 0 2006.257.02:54:35.91#ibcon#wrote, iclass 16, count 0 2006.257.02:54:35.91#ibcon#about to read 3, iclass 16, count 0 2006.257.02:54:35.93#ibcon#read 3, iclass 16, count 0 2006.257.02:54:35.93#ibcon#about to read 4, iclass 16, count 0 2006.257.02:54:35.93#ibcon#read 4, iclass 16, count 0 2006.257.02:54:35.93#ibcon#about to read 5, iclass 16, count 0 2006.257.02:54:35.93#ibcon#read 5, iclass 16, count 0 2006.257.02:54:35.93#ibcon#about to read 6, iclass 16, count 0 2006.257.02:54:35.93#ibcon#read 6, iclass 16, count 0 2006.257.02:54:35.93#ibcon#end of sib2, iclass 16, count 0 2006.257.02:54:35.93#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:54:35.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:54:35.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:54:35.93#ibcon#*before write, iclass 16, count 0 2006.257.02:54:35.93#ibcon#enter sib2, iclass 16, count 0 2006.257.02:54:35.93#ibcon#flushed, iclass 16, count 0 2006.257.02:54:35.93#ibcon#about to write, iclass 16, count 0 2006.257.02:54:35.93#ibcon#wrote, iclass 16, count 0 2006.257.02:54:35.93#ibcon#about to read 3, iclass 16, count 0 2006.257.02:54:35.97#ibcon#read 3, iclass 16, count 0 2006.257.02:54:35.97#ibcon#about to read 4, iclass 16, count 0 2006.257.02:54:35.97#ibcon#read 4, iclass 16, count 0 2006.257.02:54:35.97#ibcon#about to read 5, iclass 16, count 0 2006.257.02:54:35.97#ibcon#read 5, iclass 16, count 0 2006.257.02:54:35.97#ibcon#about to read 6, iclass 16, count 0 2006.257.02:54:35.97#ibcon#read 6, iclass 16, count 0 2006.257.02:54:35.97#ibcon#end of sib2, iclass 16, count 0 2006.257.02:54:35.97#ibcon#*after write, iclass 16, count 0 2006.257.02:54:35.97#ibcon#*before return 0, iclass 16, count 0 2006.257.02:54:35.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:35.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:35.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:54:35.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:54:35.97$vck44/va=7,4 2006.257.02:54:35.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.02:54:35.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.02:54:35.97#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:35.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:36.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:36.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:36.03#ibcon#enter wrdev, iclass 18, count 2 2006.257.02:54:36.03#ibcon#first serial, iclass 18, count 2 2006.257.02:54:36.03#ibcon#enter sib2, iclass 18, count 2 2006.257.02:54:36.03#ibcon#flushed, iclass 18, count 2 2006.257.02:54:36.03#ibcon#about to write, iclass 18, count 2 2006.257.02:54:36.03#ibcon#wrote, iclass 18, count 2 2006.257.02:54:36.03#ibcon#about to read 3, iclass 18, count 2 2006.257.02:54:36.05#ibcon#read 3, iclass 18, count 2 2006.257.02:54:36.05#ibcon#about to read 4, iclass 18, count 2 2006.257.02:54:36.05#ibcon#read 4, iclass 18, count 2 2006.257.02:54:36.05#ibcon#about to read 5, iclass 18, count 2 2006.257.02:54:36.05#ibcon#read 5, iclass 18, count 2 2006.257.02:54:36.05#ibcon#about to read 6, iclass 18, count 2 2006.257.02:54:36.05#ibcon#read 6, iclass 18, count 2 2006.257.02:54:36.05#ibcon#end of sib2, iclass 18, count 2 2006.257.02:54:36.05#ibcon#*mode == 0, iclass 18, count 2 2006.257.02:54:36.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.02:54:36.05#ibcon#[25=AT07-04\r\n] 2006.257.02:54:36.05#ibcon#*before write, iclass 18, count 2 2006.257.02:54:36.05#ibcon#enter sib2, iclass 18, count 2 2006.257.02:54:36.05#ibcon#flushed, iclass 18, count 2 2006.257.02:54:36.05#ibcon#about to write, iclass 18, count 2 2006.257.02:54:36.05#ibcon#wrote, iclass 18, count 2 2006.257.02:54:36.05#ibcon#about to read 3, iclass 18, count 2 2006.257.02:54:36.08#ibcon#read 3, iclass 18, count 2 2006.257.02:54:36.08#ibcon#about to read 4, iclass 18, count 2 2006.257.02:54:36.08#ibcon#read 4, iclass 18, count 2 2006.257.02:54:36.08#ibcon#about to read 5, iclass 18, count 2 2006.257.02:54:36.08#ibcon#read 5, iclass 18, count 2 2006.257.02:54:36.08#ibcon#about to read 6, iclass 18, count 2 2006.257.02:54:36.08#ibcon#read 6, iclass 18, count 2 2006.257.02:54:36.08#ibcon#end of sib2, iclass 18, count 2 2006.257.02:54:36.08#ibcon#*after write, iclass 18, count 2 2006.257.02:54:36.08#ibcon#*before return 0, iclass 18, count 2 2006.257.02:54:36.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:36.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:36.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.02:54:36.08#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:36.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:36.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:36.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:36.20#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:54:36.20#ibcon#first serial, iclass 18, count 0 2006.257.02:54:36.20#ibcon#enter sib2, iclass 18, count 0 2006.257.02:54:36.20#ibcon#flushed, iclass 18, count 0 2006.257.02:54:36.20#ibcon#about to write, iclass 18, count 0 2006.257.02:54:36.20#ibcon#wrote, iclass 18, count 0 2006.257.02:54:36.20#ibcon#about to read 3, iclass 18, count 0 2006.257.02:54:36.22#ibcon#read 3, iclass 18, count 0 2006.257.02:54:36.22#ibcon#about to read 4, iclass 18, count 0 2006.257.02:54:36.22#ibcon#read 4, iclass 18, count 0 2006.257.02:54:36.22#ibcon#about to read 5, iclass 18, count 0 2006.257.02:54:36.22#ibcon#read 5, iclass 18, count 0 2006.257.02:54:36.22#ibcon#about to read 6, iclass 18, count 0 2006.257.02:54:36.22#ibcon#read 6, iclass 18, count 0 2006.257.02:54:36.22#ibcon#end of sib2, iclass 18, count 0 2006.257.02:54:36.22#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:54:36.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:54:36.22#ibcon#[25=USB\r\n] 2006.257.02:54:36.22#ibcon#*before write, iclass 18, count 0 2006.257.02:54:36.22#ibcon#enter sib2, iclass 18, count 0 2006.257.02:54:36.22#ibcon#flushed, iclass 18, count 0 2006.257.02:54:36.22#ibcon#about to write, iclass 18, count 0 2006.257.02:54:36.22#ibcon#wrote, iclass 18, count 0 2006.257.02:54:36.22#ibcon#about to read 3, iclass 18, count 0 2006.257.02:54:36.25#ibcon#read 3, iclass 18, count 0 2006.257.02:54:36.25#ibcon#about to read 4, iclass 18, count 0 2006.257.02:54:36.25#ibcon#read 4, iclass 18, count 0 2006.257.02:54:36.25#ibcon#about to read 5, iclass 18, count 0 2006.257.02:54:36.25#ibcon#read 5, iclass 18, count 0 2006.257.02:54:36.25#ibcon#about to read 6, iclass 18, count 0 2006.257.02:54:36.25#ibcon#read 6, iclass 18, count 0 2006.257.02:54:36.25#ibcon#end of sib2, iclass 18, count 0 2006.257.02:54:36.25#ibcon#*after write, iclass 18, count 0 2006.257.02:54:36.25#ibcon#*before return 0, iclass 18, count 0 2006.257.02:54:36.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:36.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:36.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:54:36.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:54:36.25$vck44/valo=8,884.99 2006.257.02:54:36.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.02:54:36.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.02:54:36.25#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:36.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:36.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:36.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:36.25#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:54:36.25#ibcon#first serial, iclass 20, count 0 2006.257.02:54:36.25#ibcon#enter sib2, iclass 20, count 0 2006.257.02:54:36.25#ibcon#flushed, iclass 20, count 0 2006.257.02:54:36.25#ibcon#about to write, iclass 20, count 0 2006.257.02:54:36.25#ibcon#wrote, iclass 20, count 0 2006.257.02:54:36.25#ibcon#about to read 3, iclass 20, count 0 2006.257.02:54:36.27#ibcon#read 3, iclass 20, count 0 2006.257.02:54:36.27#ibcon#about to read 4, iclass 20, count 0 2006.257.02:54:36.27#ibcon#read 4, iclass 20, count 0 2006.257.02:54:36.27#ibcon#about to read 5, iclass 20, count 0 2006.257.02:54:36.27#ibcon#read 5, iclass 20, count 0 2006.257.02:54:36.27#ibcon#about to read 6, iclass 20, count 0 2006.257.02:54:36.27#ibcon#read 6, iclass 20, count 0 2006.257.02:54:36.27#ibcon#end of sib2, iclass 20, count 0 2006.257.02:54:36.27#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:54:36.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:54:36.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:54:36.27#ibcon#*before write, iclass 20, count 0 2006.257.02:54:36.27#ibcon#enter sib2, iclass 20, count 0 2006.257.02:54:36.27#ibcon#flushed, iclass 20, count 0 2006.257.02:54:36.27#ibcon#about to write, iclass 20, count 0 2006.257.02:54:36.27#ibcon#wrote, iclass 20, count 0 2006.257.02:54:36.27#ibcon#about to read 3, iclass 20, count 0 2006.257.02:54:36.31#ibcon#read 3, iclass 20, count 0 2006.257.02:54:36.31#ibcon#about to read 4, iclass 20, count 0 2006.257.02:54:36.31#ibcon#read 4, iclass 20, count 0 2006.257.02:54:36.31#ibcon#about to read 5, iclass 20, count 0 2006.257.02:54:36.31#ibcon#read 5, iclass 20, count 0 2006.257.02:54:36.31#ibcon#about to read 6, iclass 20, count 0 2006.257.02:54:36.31#ibcon#read 6, iclass 20, count 0 2006.257.02:54:36.31#ibcon#end of sib2, iclass 20, count 0 2006.257.02:54:36.31#ibcon#*after write, iclass 20, count 0 2006.257.02:54:36.31#ibcon#*before return 0, iclass 20, count 0 2006.257.02:54:36.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:36.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:36.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:54:36.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:54:36.31$vck44/va=8,4 2006.257.02:54:36.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.02:54:36.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.02:54:36.31#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:36.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:36.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:36.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:36.37#ibcon#enter wrdev, iclass 22, count 2 2006.257.02:54:36.37#ibcon#first serial, iclass 22, count 2 2006.257.02:54:36.37#ibcon#enter sib2, iclass 22, count 2 2006.257.02:54:36.37#ibcon#flushed, iclass 22, count 2 2006.257.02:54:36.37#ibcon#about to write, iclass 22, count 2 2006.257.02:54:36.37#ibcon#wrote, iclass 22, count 2 2006.257.02:54:36.37#ibcon#about to read 3, iclass 22, count 2 2006.257.02:54:36.39#ibcon#read 3, iclass 22, count 2 2006.257.02:54:36.39#ibcon#about to read 4, iclass 22, count 2 2006.257.02:54:36.39#ibcon#read 4, iclass 22, count 2 2006.257.02:54:36.39#ibcon#about to read 5, iclass 22, count 2 2006.257.02:54:36.39#ibcon#read 5, iclass 22, count 2 2006.257.02:54:36.39#ibcon#about to read 6, iclass 22, count 2 2006.257.02:54:36.39#ibcon#read 6, iclass 22, count 2 2006.257.02:54:36.39#ibcon#end of sib2, iclass 22, count 2 2006.257.02:54:36.39#ibcon#*mode == 0, iclass 22, count 2 2006.257.02:54:36.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.02:54:36.39#ibcon#[25=AT08-04\r\n] 2006.257.02:54:36.39#ibcon#*before write, iclass 22, count 2 2006.257.02:54:36.39#ibcon#enter sib2, iclass 22, count 2 2006.257.02:54:36.39#ibcon#flushed, iclass 22, count 2 2006.257.02:54:36.39#ibcon#about to write, iclass 22, count 2 2006.257.02:54:36.39#ibcon#wrote, iclass 22, count 2 2006.257.02:54:36.39#ibcon#about to read 3, iclass 22, count 2 2006.257.02:54:36.42#ibcon#read 3, iclass 22, count 2 2006.257.02:54:36.42#ibcon#about to read 4, iclass 22, count 2 2006.257.02:54:36.42#ibcon#read 4, iclass 22, count 2 2006.257.02:54:36.42#ibcon#about to read 5, iclass 22, count 2 2006.257.02:54:36.42#ibcon#read 5, iclass 22, count 2 2006.257.02:54:36.42#ibcon#about to read 6, iclass 22, count 2 2006.257.02:54:36.42#ibcon#read 6, iclass 22, count 2 2006.257.02:54:36.42#ibcon#end of sib2, iclass 22, count 2 2006.257.02:54:36.42#ibcon#*after write, iclass 22, count 2 2006.257.02:54:36.42#ibcon#*before return 0, iclass 22, count 2 2006.257.02:54:36.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:36.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:36.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.02:54:36.42#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:36.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:36.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:36.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:36.54#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:54:36.54#ibcon#first serial, iclass 22, count 0 2006.257.02:54:36.54#ibcon#enter sib2, iclass 22, count 0 2006.257.02:54:36.54#ibcon#flushed, iclass 22, count 0 2006.257.02:54:36.54#ibcon#about to write, iclass 22, count 0 2006.257.02:54:36.54#ibcon#wrote, iclass 22, count 0 2006.257.02:54:36.54#ibcon#about to read 3, iclass 22, count 0 2006.257.02:54:36.56#ibcon#read 3, iclass 22, count 0 2006.257.02:54:36.56#ibcon#about to read 4, iclass 22, count 0 2006.257.02:54:36.56#ibcon#read 4, iclass 22, count 0 2006.257.02:54:36.56#ibcon#about to read 5, iclass 22, count 0 2006.257.02:54:36.56#ibcon#read 5, iclass 22, count 0 2006.257.02:54:36.56#ibcon#about to read 6, iclass 22, count 0 2006.257.02:54:36.56#ibcon#read 6, iclass 22, count 0 2006.257.02:54:36.56#ibcon#end of sib2, iclass 22, count 0 2006.257.02:54:36.56#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:54:36.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:54:36.56#ibcon#[25=USB\r\n] 2006.257.02:54:36.56#ibcon#*before write, iclass 22, count 0 2006.257.02:54:36.56#ibcon#enter sib2, iclass 22, count 0 2006.257.02:54:36.56#ibcon#flushed, iclass 22, count 0 2006.257.02:54:36.56#ibcon#about to write, iclass 22, count 0 2006.257.02:54:36.56#ibcon#wrote, iclass 22, count 0 2006.257.02:54:36.56#ibcon#about to read 3, iclass 22, count 0 2006.257.02:54:36.59#ibcon#read 3, iclass 22, count 0 2006.257.02:54:36.59#ibcon#about to read 4, iclass 22, count 0 2006.257.02:54:36.59#ibcon#read 4, iclass 22, count 0 2006.257.02:54:36.59#ibcon#about to read 5, iclass 22, count 0 2006.257.02:54:36.59#ibcon#read 5, iclass 22, count 0 2006.257.02:54:36.59#ibcon#about to read 6, iclass 22, count 0 2006.257.02:54:36.59#ibcon#read 6, iclass 22, count 0 2006.257.02:54:36.59#ibcon#end of sib2, iclass 22, count 0 2006.257.02:54:36.59#ibcon#*after write, iclass 22, count 0 2006.257.02:54:36.59#ibcon#*before return 0, iclass 22, count 0 2006.257.02:54:36.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:36.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:36.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:54:36.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:54:36.59$vck44/vblo=1,629.99 2006.257.02:54:36.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.02:54:36.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.02:54:36.59#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:36.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:36.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:36.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:36.59#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:54:36.59#ibcon#first serial, iclass 24, count 0 2006.257.02:54:36.59#ibcon#enter sib2, iclass 24, count 0 2006.257.02:54:36.59#ibcon#flushed, iclass 24, count 0 2006.257.02:54:36.59#ibcon#about to write, iclass 24, count 0 2006.257.02:54:36.59#ibcon#wrote, iclass 24, count 0 2006.257.02:54:36.59#ibcon#about to read 3, iclass 24, count 0 2006.257.02:54:36.61#ibcon#read 3, iclass 24, count 0 2006.257.02:54:36.61#ibcon#about to read 4, iclass 24, count 0 2006.257.02:54:36.61#ibcon#read 4, iclass 24, count 0 2006.257.02:54:36.61#ibcon#about to read 5, iclass 24, count 0 2006.257.02:54:36.61#ibcon#read 5, iclass 24, count 0 2006.257.02:54:36.61#ibcon#about to read 6, iclass 24, count 0 2006.257.02:54:36.61#ibcon#read 6, iclass 24, count 0 2006.257.02:54:36.61#ibcon#end of sib2, iclass 24, count 0 2006.257.02:54:36.61#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:54:36.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:54:36.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:54:36.61#ibcon#*before write, iclass 24, count 0 2006.257.02:54:36.61#ibcon#enter sib2, iclass 24, count 0 2006.257.02:54:36.61#ibcon#flushed, iclass 24, count 0 2006.257.02:54:36.61#ibcon#about to write, iclass 24, count 0 2006.257.02:54:36.61#ibcon#wrote, iclass 24, count 0 2006.257.02:54:36.61#ibcon#about to read 3, iclass 24, count 0 2006.257.02:54:36.65#ibcon#read 3, iclass 24, count 0 2006.257.02:54:36.65#ibcon#about to read 4, iclass 24, count 0 2006.257.02:54:36.65#ibcon#read 4, iclass 24, count 0 2006.257.02:54:36.65#ibcon#about to read 5, iclass 24, count 0 2006.257.02:54:36.65#ibcon#read 5, iclass 24, count 0 2006.257.02:54:36.65#ibcon#about to read 6, iclass 24, count 0 2006.257.02:54:36.65#ibcon#read 6, iclass 24, count 0 2006.257.02:54:36.65#ibcon#end of sib2, iclass 24, count 0 2006.257.02:54:36.65#ibcon#*after write, iclass 24, count 0 2006.257.02:54:36.65#ibcon#*before return 0, iclass 24, count 0 2006.257.02:54:36.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:36.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:36.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:54:36.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:54:36.65$vck44/vb=1,4 2006.257.02:54:36.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.02:54:36.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.02:54:36.65#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:36.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:54:36.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:54:36.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:54:36.65#ibcon#enter wrdev, iclass 26, count 2 2006.257.02:54:36.65#ibcon#first serial, iclass 26, count 2 2006.257.02:54:36.65#ibcon#enter sib2, iclass 26, count 2 2006.257.02:54:36.65#ibcon#flushed, iclass 26, count 2 2006.257.02:54:36.65#ibcon#about to write, iclass 26, count 2 2006.257.02:54:36.65#ibcon#wrote, iclass 26, count 2 2006.257.02:54:36.65#ibcon#about to read 3, iclass 26, count 2 2006.257.02:54:36.67#ibcon#read 3, iclass 26, count 2 2006.257.02:54:36.67#ibcon#about to read 4, iclass 26, count 2 2006.257.02:54:36.67#ibcon#read 4, iclass 26, count 2 2006.257.02:54:36.67#ibcon#about to read 5, iclass 26, count 2 2006.257.02:54:36.67#ibcon#read 5, iclass 26, count 2 2006.257.02:54:36.67#ibcon#about to read 6, iclass 26, count 2 2006.257.02:54:36.67#ibcon#read 6, iclass 26, count 2 2006.257.02:54:36.67#ibcon#end of sib2, iclass 26, count 2 2006.257.02:54:36.67#ibcon#*mode == 0, iclass 26, count 2 2006.257.02:54:36.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.02:54:36.67#ibcon#[27=AT01-04\r\n] 2006.257.02:54:36.67#ibcon#*before write, iclass 26, count 2 2006.257.02:54:36.67#ibcon#enter sib2, iclass 26, count 2 2006.257.02:54:36.67#ibcon#flushed, iclass 26, count 2 2006.257.02:54:36.67#ibcon#about to write, iclass 26, count 2 2006.257.02:54:36.67#ibcon#wrote, iclass 26, count 2 2006.257.02:54:36.67#ibcon#about to read 3, iclass 26, count 2 2006.257.02:54:36.70#ibcon#read 3, iclass 26, count 2 2006.257.02:54:36.70#ibcon#about to read 4, iclass 26, count 2 2006.257.02:54:36.70#ibcon#read 4, iclass 26, count 2 2006.257.02:54:36.70#ibcon#about to read 5, iclass 26, count 2 2006.257.02:54:36.70#ibcon#read 5, iclass 26, count 2 2006.257.02:54:36.70#ibcon#about to read 6, iclass 26, count 2 2006.257.02:54:36.70#ibcon#read 6, iclass 26, count 2 2006.257.02:54:36.70#ibcon#end of sib2, iclass 26, count 2 2006.257.02:54:36.70#ibcon#*after write, iclass 26, count 2 2006.257.02:54:36.70#ibcon#*before return 0, iclass 26, count 2 2006.257.02:54:36.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:54:36.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.02:54:36.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.02:54:36.70#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:36.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:54:36.79#abcon#<5=/16 2.1 5.6 18.88 901012.5\r\n> 2006.257.02:54:36.81#abcon#{5=INTERFACE CLEAR} 2006.257.02:54:36.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:54:36.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:54:36.82#ibcon#enter wrdev, iclass 26, count 0 2006.257.02:54:36.82#ibcon#first serial, iclass 26, count 0 2006.257.02:54:36.82#ibcon#enter sib2, iclass 26, count 0 2006.257.02:54:36.82#ibcon#flushed, iclass 26, count 0 2006.257.02:54:36.82#ibcon#about to write, iclass 26, count 0 2006.257.02:54:36.82#ibcon#wrote, iclass 26, count 0 2006.257.02:54:36.82#ibcon#about to read 3, iclass 26, count 0 2006.257.02:54:36.84#ibcon#read 3, iclass 26, count 0 2006.257.02:54:36.84#ibcon#about to read 4, iclass 26, count 0 2006.257.02:54:36.84#ibcon#read 4, iclass 26, count 0 2006.257.02:54:36.84#ibcon#about to read 5, iclass 26, count 0 2006.257.02:54:36.84#ibcon#read 5, iclass 26, count 0 2006.257.02:54:36.84#ibcon#about to read 6, iclass 26, count 0 2006.257.02:54:36.84#ibcon#read 6, iclass 26, count 0 2006.257.02:54:36.84#ibcon#end of sib2, iclass 26, count 0 2006.257.02:54:36.84#ibcon#*mode == 0, iclass 26, count 0 2006.257.02:54:36.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.02:54:36.84#ibcon#[27=USB\r\n] 2006.257.02:54:36.84#ibcon#*before write, iclass 26, count 0 2006.257.02:54:36.84#ibcon#enter sib2, iclass 26, count 0 2006.257.02:54:36.84#ibcon#flushed, iclass 26, count 0 2006.257.02:54:36.84#ibcon#about to write, iclass 26, count 0 2006.257.02:54:36.84#ibcon#wrote, iclass 26, count 0 2006.257.02:54:36.84#ibcon#about to read 3, iclass 26, count 0 2006.257.02:54:36.87#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:54:36.87#ibcon#read 3, iclass 26, count 0 2006.257.02:54:36.87#ibcon#about to read 4, iclass 26, count 0 2006.257.02:54:36.87#ibcon#read 4, iclass 26, count 0 2006.257.02:54:36.87#ibcon#about to read 5, iclass 26, count 0 2006.257.02:54:36.87#ibcon#read 5, iclass 26, count 0 2006.257.02:54:36.87#ibcon#about to read 6, iclass 26, count 0 2006.257.02:54:36.87#ibcon#read 6, iclass 26, count 0 2006.257.02:54:36.87#ibcon#end of sib2, iclass 26, count 0 2006.257.02:54:36.87#ibcon#*after write, iclass 26, count 0 2006.257.02:54:36.87#ibcon#*before return 0, iclass 26, count 0 2006.257.02:54:36.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:54:36.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.02:54:36.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.02:54:36.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.02:54:36.87$vck44/vblo=2,634.99 2006.257.02:54:36.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.02:54:36.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.02:54:36.87#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:36.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:36.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:36.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:36.87#ibcon#enter wrdev, iclass 32, count 0 2006.257.02:54:36.87#ibcon#first serial, iclass 32, count 0 2006.257.02:54:36.87#ibcon#enter sib2, iclass 32, count 0 2006.257.02:54:36.87#ibcon#flushed, iclass 32, count 0 2006.257.02:54:36.87#ibcon#about to write, iclass 32, count 0 2006.257.02:54:36.87#ibcon#wrote, iclass 32, count 0 2006.257.02:54:36.87#ibcon#about to read 3, iclass 32, count 0 2006.257.02:54:36.89#ibcon#read 3, iclass 32, count 0 2006.257.02:54:36.89#ibcon#about to read 4, iclass 32, count 0 2006.257.02:54:36.89#ibcon#read 4, iclass 32, count 0 2006.257.02:54:36.89#ibcon#about to read 5, iclass 32, count 0 2006.257.02:54:36.89#ibcon#read 5, iclass 32, count 0 2006.257.02:54:36.89#ibcon#about to read 6, iclass 32, count 0 2006.257.02:54:36.89#ibcon#read 6, iclass 32, count 0 2006.257.02:54:36.89#ibcon#end of sib2, iclass 32, count 0 2006.257.02:54:36.89#ibcon#*mode == 0, iclass 32, count 0 2006.257.02:54:36.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.02:54:36.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:54:36.89#ibcon#*before write, iclass 32, count 0 2006.257.02:54:36.89#ibcon#enter sib2, iclass 32, count 0 2006.257.02:54:36.89#ibcon#flushed, iclass 32, count 0 2006.257.02:54:36.89#ibcon#about to write, iclass 32, count 0 2006.257.02:54:36.89#ibcon#wrote, iclass 32, count 0 2006.257.02:54:36.89#ibcon#about to read 3, iclass 32, count 0 2006.257.02:54:36.93#ibcon#read 3, iclass 32, count 0 2006.257.02:54:36.93#ibcon#about to read 4, iclass 32, count 0 2006.257.02:54:36.93#ibcon#read 4, iclass 32, count 0 2006.257.02:54:36.93#ibcon#about to read 5, iclass 32, count 0 2006.257.02:54:36.93#ibcon#read 5, iclass 32, count 0 2006.257.02:54:36.93#ibcon#about to read 6, iclass 32, count 0 2006.257.02:54:36.93#ibcon#read 6, iclass 32, count 0 2006.257.02:54:36.93#ibcon#end of sib2, iclass 32, count 0 2006.257.02:54:36.93#ibcon#*after write, iclass 32, count 0 2006.257.02:54:36.93#ibcon#*before return 0, iclass 32, count 0 2006.257.02:54:36.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:36.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.02:54:36.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.02:54:36.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.02:54:36.93$vck44/vb=2,5 2006.257.02:54:36.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.02:54:36.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.02:54:36.93#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:36.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:36.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:36.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:36.99#ibcon#enter wrdev, iclass 34, count 2 2006.257.02:54:36.99#ibcon#first serial, iclass 34, count 2 2006.257.02:54:36.99#ibcon#enter sib2, iclass 34, count 2 2006.257.02:54:36.99#ibcon#flushed, iclass 34, count 2 2006.257.02:54:36.99#ibcon#about to write, iclass 34, count 2 2006.257.02:54:36.99#ibcon#wrote, iclass 34, count 2 2006.257.02:54:36.99#ibcon#about to read 3, iclass 34, count 2 2006.257.02:54:37.01#ibcon#read 3, iclass 34, count 2 2006.257.02:54:37.01#ibcon#about to read 4, iclass 34, count 2 2006.257.02:54:37.01#ibcon#read 4, iclass 34, count 2 2006.257.02:54:37.01#ibcon#about to read 5, iclass 34, count 2 2006.257.02:54:37.01#ibcon#read 5, iclass 34, count 2 2006.257.02:54:37.01#ibcon#about to read 6, iclass 34, count 2 2006.257.02:54:37.01#ibcon#read 6, iclass 34, count 2 2006.257.02:54:37.01#ibcon#end of sib2, iclass 34, count 2 2006.257.02:54:37.01#ibcon#*mode == 0, iclass 34, count 2 2006.257.02:54:37.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.02:54:37.01#ibcon#[27=AT02-05\r\n] 2006.257.02:54:37.01#ibcon#*before write, iclass 34, count 2 2006.257.02:54:37.01#ibcon#enter sib2, iclass 34, count 2 2006.257.02:54:37.01#ibcon#flushed, iclass 34, count 2 2006.257.02:54:37.01#ibcon#about to write, iclass 34, count 2 2006.257.02:54:37.01#ibcon#wrote, iclass 34, count 2 2006.257.02:54:37.01#ibcon#about to read 3, iclass 34, count 2 2006.257.02:54:37.04#ibcon#read 3, iclass 34, count 2 2006.257.02:54:37.04#ibcon#about to read 4, iclass 34, count 2 2006.257.02:54:37.04#ibcon#read 4, iclass 34, count 2 2006.257.02:54:37.04#ibcon#about to read 5, iclass 34, count 2 2006.257.02:54:37.04#ibcon#read 5, iclass 34, count 2 2006.257.02:54:37.04#ibcon#about to read 6, iclass 34, count 2 2006.257.02:54:37.04#ibcon#read 6, iclass 34, count 2 2006.257.02:54:37.04#ibcon#end of sib2, iclass 34, count 2 2006.257.02:54:37.04#ibcon#*after write, iclass 34, count 2 2006.257.02:54:37.04#ibcon#*before return 0, iclass 34, count 2 2006.257.02:54:37.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:37.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.02:54:37.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.02:54:37.04#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:37.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:37.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:37.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:37.16#ibcon#enter wrdev, iclass 34, count 0 2006.257.02:54:37.16#ibcon#first serial, iclass 34, count 0 2006.257.02:54:37.16#ibcon#enter sib2, iclass 34, count 0 2006.257.02:54:37.16#ibcon#flushed, iclass 34, count 0 2006.257.02:54:37.16#ibcon#about to write, iclass 34, count 0 2006.257.02:54:37.16#ibcon#wrote, iclass 34, count 0 2006.257.02:54:37.16#ibcon#about to read 3, iclass 34, count 0 2006.257.02:54:37.18#ibcon#read 3, iclass 34, count 0 2006.257.02:54:37.18#ibcon#about to read 4, iclass 34, count 0 2006.257.02:54:37.18#ibcon#read 4, iclass 34, count 0 2006.257.02:54:37.18#ibcon#about to read 5, iclass 34, count 0 2006.257.02:54:37.18#ibcon#read 5, iclass 34, count 0 2006.257.02:54:37.18#ibcon#about to read 6, iclass 34, count 0 2006.257.02:54:37.18#ibcon#read 6, iclass 34, count 0 2006.257.02:54:37.18#ibcon#end of sib2, iclass 34, count 0 2006.257.02:54:37.18#ibcon#*mode == 0, iclass 34, count 0 2006.257.02:54:37.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.02:54:37.18#ibcon#[27=USB\r\n] 2006.257.02:54:37.18#ibcon#*before write, iclass 34, count 0 2006.257.02:54:37.18#ibcon#enter sib2, iclass 34, count 0 2006.257.02:54:37.18#ibcon#flushed, iclass 34, count 0 2006.257.02:54:37.18#ibcon#about to write, iclass 34, count 0 2006.257.02:54:37.18#ibcon#wrote, iclass 34, count 0 2006.257.02:54:37.18#ibcon#about to read 3, iclass 34, count 0 2006.257.02:54:37.21#ibcon#read 3, iclass 34, count 0 2006.257.02:54:37.21#ibcon#about to read 4, iclass 34, count 0 2006.257.02:54:37.21#ibcon#read 4, iclass 34, count 0 2006.257.02:54:37.21#ibcon#about to read 5, iclass 34, count 0 2006.257.02:54:37.21#ibcon#read 5, iclass 34, count 0 2006.257.02:54:37.21#ibcon#about to read 6, iclass 34, count 0 2006.257.02:54:37.21#ibcon#read 6, iclass 34, count 0 2006.257.02:54:37.21#ibcon#end of sib2, iclass 34, count 0 2006.257.02:54:37.21#ibcon#*after write, iclass 34, count 0 2006.257.02:54:37.21#ibcon#*before return 0, iclass 34, count 0 2006.257.02:54:37.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:37.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.02:54:37.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.02:54:37.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.02:54:37.21$vck44/vblo=3,649.99 2006.257.02:54:37.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.02:54:37.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.02:54:37.21#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:37.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:37.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:37.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:37.21#ibcon#enter wrdev, iclass 36, count 0 2006.257.02:54:37.21#ibcon#first serial, iclass 36, count 0 2006.257.02:54:37.21#ibcon#enter sib2, iclass 36, count 0 2006.257.02:54:37.21#ibcon#flushed, iclass 36, count 0 2006.257.02:54:37.21#ibcon#about to write, iclass 36, count 0 2006.257.02:54:37.21#ibcon#wrote, iclass 36, count 0 2006.257.02:54:37.21#ibcon#about to read 3, iclass 36, count 0 2006.257.02:54:37.23#ibcon#read 3, iclass 36, count 0 2006.257.02:54:37.23#ibcon#about to read 4, iclass 36, count 0 2006.257.02:54:37.23#ibcon#read 4, iclass 36, count 0 2006.257.02:54:37.23#ibcon#about to read 5, iclass 36, count 0 2006.257.02:54:37.23#ibcon#read 5, iclass 36, count 0 2006.257.02:54:37.23#ibcon#about to read 6, iclass 36, count 0 2006.257.02:54:37.23#ibcon#read 6, iclass 36, count 0 2006.257.02:54:37.23#ibcon#end of sib2, iclass 36, count 0 2006.257.02:54:37.23#ibcon#*mode == 0, iclass 36, count 0 2006.257.02:54:37.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.02:54:37.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:54:37.23#ibcon#*before write, iclass 36, count 0 2006.257.02:54:37.23#ibcon#enter sib2, iclass 36, count 0 2006.257.02:54:37.23#ibcon#flushed, iclass 36, count 0 2006.257.02:54:37.23#ibcon#about to write, iclass 36, count 0 2006.257.02:54:37.23#ibcon#wrote, iclass 36, count 0 2006.257.02:54:37.23#ibcon#about to read 3, iclass 36, count 0 2006.257.02:54:37.27#ibcon#read 3, iclass 36, count 0 2006.257.02:54:37.27#ibcon#about to read 4, iclass 36, count 0 2006.257.02:54:37.27#ibcon#read 4, iclass 36, count 0 2006.257.02:54:37.27#ibcon#about to read 5, iclass 36, count 0 2006.257.02:54:37.27#ibcon#read 5, iclass 36, count 0 2006.257.02:54:37.27#ibcon#about to read 6, iclass 36, count 0 2006.257.02:54:37.27#ibcon#read 6, iclass 36, count 0 2006.257.02:54:37.27#ibcon#end of sib2, iclass 36, count 0 2006.257.02:54:37.27#ibcon#*after write, iclass 36, count 0 2006.257.02:54:37.27#ibcon#*before return 0, iclass 36, count 0 2006.257.02:54:37.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:37.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.02:54:37.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.02:54:37.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.02:54:37.27$vck44/vb=3,4 2006.257.02:54:37.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.02:54:37.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.02:54:37.27#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:37.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:37.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:37.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:37.33#ibcon#enter wrdev, iclass 38, count 2 2006.257.02:54:37.33#ibcon#first serial, iclass 38, count 2 2006.257.02:54:37.33#ibcon#enter sib2, iclass 38, count 2 2006.257.02:54:37.33#ibcon#flushed, iclass 38, count 2 2006.257.02:54:37.33#ibcon#about to write, iclass 38, count 2 2006.257.02:54:37.33#ibcon#wrote, iclass 38, count 2 2006.257.02:54:37.33#ibcon#about to read 3, iclass 38, count 2 2006.257.02:54:37.35#ibcon#read 3, iclass 38, count 2 2006.257.02:54:37.35#ibcon#about to read 4, iclass 38, count 2 2006.257.02:54:37.35#ibcon#read 4, iclass 38, count 2 2006.257.02:54:37.35#ibcon#about to read 5, iclass 38, count 2 2006.257.02:54:37.35#ibcon#read 5, iclass 38, count 2 2006.257.02:54:37.35#ibcon#about to read 6, iclass 38, count 2 2006.257.02:54:37.35#ibcon#read 6, iclass 38, count 2 2006.257.02:54:37.35#ibcon#end of sib2, iclass 38, count 2 2006.257.02:54:37.35#ibcon#*mode == 0, iclass 38, count 2 2006.257.02:54:37.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.02:54:37.35#ibcon#[27=AT03-04\r\n] 2006.257.02:54:37.35#ibcon#*before write, iclass 38, count 2 2006.257.02:54:37.35#ibcon#enter sib2, iclass 38, count 2 2006.257.02:54:37.35#ibcon#flushed, iclass 38, count 2 2006.257.02:54:37.35#ibcon#about to write, iclass 38, count 2 2006.257.02:54:37.35#ibcon#wrote, iclass 38, count 2 2006.257.02:54:37.35#ibcon#about to read 3, iclass 38, count 2 2006.257.02:54:37.38#ibcon#read 3, iclass 38, count 2 2006.257.02:54:37.38#ibcon#about to read 4, iclass 38, count 2 2006.257.02:54:37.38#ibcon#read 4, iclass 38, count 2 2006.257.02:54:37.38#ibcon#about to read 5, iclass 38, count 2 2006.257.02:54:37.38#ibcon#read 5, iclass 38, count 2 2006.257.02:54:37.38#ibcon#about to read 6, iclass 38, count 2 2006.257.02:54:37.38#ibcon#read 6, iclass 38, count 2 2006.257.02:54:37.38#ibcon#end of sib2, iclass 38, count 2 2006.257.02:54:37.38#ibcon#*after write, iclass 38, count 2 2006.257.02:54:37.38#ibcon#*before return 0, iclass 38, count 2 2006.257.02:54:37.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:37.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.02:54:37.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.02:54:37.38#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:37.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:37.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:37.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:37.50#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:54:37.50#ibcon#first serial, iclass 38, count 0 2006.257.02:54:37.50#ibcon#enter sib2, iclass 38, count 0 2006.257.02:54:37.50#ibcon#flushed, iclass 38, count 0 2006.257.02:54:37.50#ibcon#about to write, iclass 38, count 0 2006.257.02:54:37.50#ibcon#wrote, iclass 38, count 0 2006.257.02:54:37.50#ibcon#about to read 3, iclass 38, count 0 2006.257.02:54:37.52#ibcon#read 3, iclass 38, count 0 2006.257.02:54:37.52#ibcon#about to read 4, iclass 38, count 0 2006.257.02:54:37.52#ibcon#read 4, iclass 38, count 0 2006.257.02:54:37.52#ibcon#about to read 5, iclass 38, count 0 2006.257.02:54:37.52#ibcon#read 5, iclass 38, count 0 2006.257.02:54:37.52#ibcon#about to read 6, iclass 38, count 0 2006.257.02:54:37.52#ibcon#read 6, iclass 38, count 0 2006.257.02:54:37.52#ibcon#end of sib2, iclass 38, count 0 2006.257.02:54:37.52#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:54:37.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:54:37.52#ibcon#[27=USB\r\n] 2006.257.02:54:37.52#ibcon#*before write, iclass 38, count 0 2006.257.02:54:37.52#ibcon#enter sib2, iclass 38, count 0 2006.257.02:54:37.52#ibcon#flushed, iclass 38, count 0 2006.257.02:54:37.52#ibcon#about to write, iclass 38, count 0 2006.257.02:54:37.52#ibcon#wrote, iclass 38, count 0 2006.257.02:54:37.52#ibcon#about to read 3, iclass 38, count 0 2006.257.02:54:37.55#ibcon#read 3, iclass 38, count 0 2006.257.02:54:37.55#ibcon#about to read 4, iclass 38, count 0 2006.257.02:54:37.55#ibcon#read 4, iclass 38, count 0 2006.257.02:54:37.55#ibcon#about to read 5, iclass 38, count 0 2006.257.02:54:37.55#ibcon#read 5, iclass 38, count 0 2006.257.02:54:37.55#ibcon#about to read 6, iclass 38, count 0 2006.257.02:54:37.55#ibcon#read 6, iclass 38, count 0 2006.257.02:54:37.55#ibcon#end of sib2, iclass 38, count 0 2006.257.02:54:37.55#ibcon#*after write, iclass 38, count 0 2006.257.02:54:37.55#ibcon#*before return 0, iclass 38, count 0 2006.257.02:54:37.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:37.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.02:54:37.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:54:37.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:54:37.55$vck44/vblo=4,679.99 2006.257.02:54:37.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.02:54:37.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.02:54:37.55#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:37.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:37.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:37.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:37.55#ibcon#enter wrdev, iclass 40, count 0 2006.257.02:54:37.55#ibcon#first serial, iclass 40, count 0 2006.257.02:54:37.55#ibcon#enter sib2, iclass 40, count 0 2006.257.02:54:37.55#ibcon#flushed, iclass 40, count 0 2006.257.02:54:37.55#ibcon#about to write, iclass 40, count 0 2006.257.02:54:37.55#ibcon#wrote, iclass 40, count 0 2006.257.02:54:37.55#ibcon#about to read 3, iclass 40, count 0 2006.257.02:54:37.57#ibcon#read 3, iclass 40, count 0 2006.257.02:54:37.57#ibcon#about to read 4, iclass 40, count 0 2006.257.02:54:37.57#ibcon#read 4, iclass 40, count 0 2006.257.02:54:37.57#ibcon#about to read 5, iclass 40, count 0 2006.257.02:54:37.57#ibcon#read 5, iclass 40, count 0 2006.257.02:54:37.57#ibcon#about to read 6, iclass 40, count 0 2006.257.02:54:37.57#ibcon#read 6, iclass 40, count 0 2006.257.02:54:37.57#ibcon#end of sib2, iclass 40, count 0 2006.257.02:54:37.57#ibcon#*mode == 0, iclass 40, count 0 2006.257.02:54:37.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.02:54:37.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:54:37.57#ibcon#*before write, iclass 40, count 0 2006.257.02:54:37.57#ibcon#enter sib2, iclass 40, count 0 2006.257.02:54:37.57#ibcon#flushed, iclass 40, count 0 2006.257.02:54:37.57#ibcon#about to write, iclass 40, count 0 2006.257.02:54:37.57#ibcon#wrote, iclass 40, count 0 2006.257.02:54:37.57#ibcon#about to read 3, iclass 40, count 0 2006.257.02:54:37.61#ibcon#read 3, iclass 40, count 0 2006.257.02:54:37.61#ibcon#about to read 4, iclass 40, count 0 2006.257.02:54:37.61#ibcon#read 4, iclass 40, count 0 2006.257.02:54:37.61#ibcon#about to read 5, iclass 40, count 0 2006.257.02:54:37.61#ibcon#read 5, iclass 40, count 0 2006.257.02:54:37.61#ibcon#about to read 6, iclass 40, count 0 2006.257.02:54:37.61#ibcon#read 6, iclass 40, count 0 2006.257.02:54:37.61#ibcon#end of sib2, iclass 40, count 0 2006.257.02:54:37.61#ibcon#*after write, iclass 40, count 0 2006.257.02:54:37.61#ibcon#*before return 0, iclass 40, count 0 2006.257.02:54:37.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:37.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.02:54:37.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.02:54:37.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.02:54:37.61$vck44/vb=4,5 2006.257.02:54:37.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.02:54:37.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.02:54:37.61#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:37.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:37.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:37.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:37.67#ibcon#enter wrdev, iclass 4, count 2 2006.257.02:54:37.67#ibcon#first serial, iclass 4, count 2 2006.257.02:54:37.67#ibcon#enter sib2, iclass 4, count 2 2006.257.02:54:37.67#ibcon#flushed, iclass 4, count 2 2006.257.02:54:37.67#ibcon#about to write, iclass 4, count 2 2006.257.02:54:37.67#ibcon#wrote, iclass 4, count 2 2006.257.02:54:37.67#ibcon#about to read 3, iclass 4, count 2 2006.257.02:54:37.69#ibcon#read 3, iclass 4, count 2 2006.257.02:54:37.69#ibcon#about to read 4, iclass 4, count 2 2006.257.02:54:37.69#ibcon#read 4, iclass 4, count 2 2006.257.02:54:37.69#ibcon#about to read 5, iclass 4, count 2 2006.257.02:54:37.69#ibcon#read 5, iclass 4, count 2 2006.257.02:54:37.69#ibcon#about to read 6, iclass 4, count 2 2006.257.02:54:37.69#ibcon#read 6, iclass 4, count 2 2006.257.02:54:37.69#ibcon#end of sib2, iclass 4, count 2 2006.257.02:54:37.69#ibcon#*mode == 0, iclass 4, count 2 2006.257.02:54:37.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.02:54:37.69#ibcon#[27=AT04-05\r\n] 2006.257.02:54:37.69#ibcon#*before write, iclass 4, count 2 2006.257.02:54:37.69#ibcon#enter sib2, iclass 4, count 2 2006.257.02:54:37.69#ibcon#flushed, iclass 4, count 2 2006.257.02:54:37.69#ibcon#about to write, iclass 4, count 2 2006.257.02:54:37.69#ibcon#wrote, iclass 4, count 2 2006.257.02:54:37.69#ibcon#about to read 3, iclass 4, count 2 2006.257.02:54:37.72#ibcon#read 3, iclass 4, count 2 2006.257.02:54:37.72#ibcon#about to read 4, iclass 4, count 2 2006.257.02:54:37.72#ibcon#read 4, iclass 4, count 2 2006.257.02:54:37.72#ibcon#about to read 5, iclass 4, count 2 2006.257.02:54:37.72#ibcon#read 5, iclass 4, count 2 2006.257.02:54:37.72#ibcon#about to read 6, iclass 4, count 2 2006.257.02:54:37.72#ibcon#read 6, iclass 4, count 2 2006.257.02:54:37.72#ibcon#end of sib2, iclass 4, count 2 2006.257.02:54:37.72#ibcon#*after write, iclass 4, count 2 2006.257.02:54:37.72#ibcon#*before return 0, iclass 4, count 2 2006.257.02:54:37.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:37.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.02:54:37.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.02:54:37.72#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:37.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:37.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:37.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:37.84#ibcon#enter wrdev, iclass 4, count 0 2006.257.02:54:37.84#ibcon#first serial, iclass 4, count 0 2006.257.02:54:37.84#ibcon#enter sib2, iclass 4, count 0 2006.257.02:54:37.84#ibcon#flushed, iclass 4, count 0 2006.257.02:54:37.84#ibcon#about to write, iclass 4, count 0 2006.257.02:54:37.84#ibcon#wrote, iclass 4, count 0 2006.257.02:54:37.84#ibcon#about to read 3, iclass 4, count 0 2006.257.02:54:37.86#ibcon#read 3, iclass 4, count 0 2006.257.02:54:37.86#ibcon#about to read 4, iclass 4, count 0 2006.257.02:54:37.86#ibcon#read 4, iclass 4, count 0 2006.257.02:54:37.86#ibcon#about to read 5, iclass 4, count 0 2006.257.02:54:37.86#ibcon#read 5, iclass 4, count 0 2006.257.02:54:37.86#ibcon#about to read 6, iclass 4, count 0 2006.257.02:54:37.86#ibcon#read 6, iclass 4, count 0 2006.257.02:54:37.86#ibcon#end of sib2, iclass 4, count 0 2006.257.02:54:37.86#ibcon#*mode == 0, iclass 4, count 0 2006.257.02:54:37.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.02:54:37.86#ibcon#[27=USB\r\n] 2006.257.02:54:37.86#ibcon#*before write, iclass 4, count 0 2006.257.02:54:37.86#ibcon#enter sib2, iclass 4, count 0 2006.257.02:54:37.86#ibcon#flushed, iclass 4, count 0 2006.257.02:54:37.86#ibcon#about to write, iclass 4, count 0 2006.257.02:54:37.86#ibcon#wrote, iclass 4, count 0 2006.257.02:54:37.86#ibcon#about to read 3, iclass 4, count 0 2006.257.02:54:37.89#ibcon#read 3, iclass 4, count 0 2006.257.02:54:37.89#ibcon#about to read 4, iclass 4, count 0 2006.257.02:54:37.89#ibcon#read 4, iclass 4, count 0 2006.257.02:54:37.89#ibcon#about to read 5, iclass 4, count 0 2006.257.02:54:37.89#ibcon#read 5, iclass 4, count 0 2006.257.02:54:37.89#ibcon#about to read 6, iclass 4, count 0 2006.257.02:54:37.89#ibcon#read 6, iclass 4, count 0 2006.257.02:54:37.89#ibcon#end of sib2, iclass 4, count 0 2006.257.02:54:37.89#ibcon#*after write, iclass 4, count 0 2006.257.02:54:37.89#ibcon#*before return 0, iclass 4, count 0 2006.257.02:54:37.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:37.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.02:54:37.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.02:54:37.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.02:54:37.89$vck44/vblo=5,709.99 2006.257.02:54:37.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.02:54:37.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.02:54:37.89#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:37.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:37.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:37.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:37.89#ibcon#enter wrdev, iclass 6, count 0 2006.257.02:54:37.89#ibcon#first serial, iclass 6, count 0 2006.257.02:54:37.89#ibcon#enter sib2, iclass 6, count 0 2006.257.02:54:37.89#ibcon#flushed, iclass 6, count 0 2006.257.02:54:37.89#ibcon#about to write, iclass 6, count 0 2006.257.02:54:37.89#ibcon#wrote, iclass 6, count 0 2006.257.02:54:37.89#ibcon#about to read 3, iclass 6, count 0 2006.257.02:54:37.91#ibcon#read 3, iclass 6, count 0 2006.257.02:54:37.91#ibcon#about to read 4, iclass 6, count 0 2006.257.02:54:37.91#ibcon#read 4, iclass 6, count 0 2006.257.02:54:37.91#ibcon#about to read 5, iclass 6, count 0 2006.257.02:54:37.91#ibcon#read 5, iclass 6, count 0 2006.257.02:54:37.91#ibcon#about to read 6, iclass 6, count 0 2006.257.02:54:37.91#ibcon#read 6, iclass 6, count 0 2006.257.02:54:37.91#ibcon#end of sib2, iclass 6, count 0 2006.257.02:54:37.91#ibcon#*mode == 0, iclass 6, count 0 2006.257.02:54:37.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.02:54:37.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:54:37.91#ibcon#*before write, iclass 6, count 0 2006.257.02:54:37.91#ibcon#enter sib2, iclass 6, count 0 2006.257.02:54:37.91#ibcon#flushed, iclass 6, count 0 2006.257.02:54:37.91#ibcon#about to write, iclass 6, count 0 2006.257.02:54:37.91#ibcon#wrote, iclass 6, count 0 2006.257.02:54:37.91#ibcon#about to read 3, iclass 6, count 0 2006.257.02:54:37.95#ibcon#read 3, iclass 6, count 0 2006.257.02:54:37.95#ibcon#about to read 4, iclass 6, count 0 2006.257.02:54:37.95#ibcon#read 4, iclass 6, count 0 2006.257.02:54:37.95#ibcon#about to read 5, iclass 6, count 0 2006.257.02:54:37.95#ibcon#read 5, iclass 6, count 0 2006.257.02:54:37.95#ibcon#about to read 6, iclass 6, count 0 2006.257.02:54:37.95#ibcon#read 6, iclass 6, count 0 2006.257.02:54:37.95#ibcon#end of sib2, iclass 6, count 0 2006.257.02:54:37.95#ibcon#*after write, iclass 6, count 0 2006.257.02:54:37.95#ibcon#*before return 0, iclass 6, count 0 2006.257.02:54:37.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:37.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.02:54:37.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.02:54:37.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.02:54:37.95$vck44/vb=5,4 2006.257.02:54:37.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.02:54:37.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.02:54:37.95#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:37.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:38.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:38.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:38.01#ibcon#enter wrdev, iclass 10, count 2 2006.257.02:54:38.01#ibcon#first serial, iclass 10, count 2 2006.257.02:54:38.01#ibcon#enter sib2, iclass 10, count 2 2006.257.02:54:38.01#ibcon#flushed, iclass 10, count 2 2006.257.02:54:38.01#ibcon#about to write, iclass 10, count 2 2006.257.02:54:38.01#ibcon#wrote, iclass 10, count 2 2006.257.02:54:38.01#ibcon#about to read 3, iclass 10, count 2 2006.257.02:54:38.03#ibcon#read 3, iclass 10, count 2 2006.257.02:54:38.03#ibcon#about to read 4, iclass 10, count 2 2006.257.02:54:38.03#ibcon#read 4, iclass 10, count 2 2006.257.02:54:38.03#ibcon#about to read 5, iclass 10, count 2 2006.257.02:54:38.03#ibcon#read 5, iclass 10, count 2 2006.257.02:54:38.03#ibcon#about to read 6, iclass 10, count 2 2006.257.02:54:38.03#ibcon#read 6, iclass 10, count 2 2006.257.02:54:38.03#ibcon#end of sib2, iclass 10, count 2 2006.257.02:54:38.03#ibcon#*mode == 0, iclass 10, count 2 2006.257.02:54:38.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.02:54:38.03#ibcon#[27=AT05-04\r\n] 2006.257.02:54:38.03#ibcon#*before write, iclass 10, count 2 2006.257.02:54:38.03#ibcon#enter sib2, iclass 10, count 2 2006.257.02:54:38.03#ibcon#flushed, iclass 10, count 2 2006.257.02:54:38.03#ibcon#about to write, iclass 10, count 2 2006.257.02:54:38.03#ibcon#wrote, iclass 10, count 2 2006.257.02:54:38.03#ibcon#about to read 3, iclass 10, count 2 2006.257.02:54:38.06#ibcon#read 3, iclass 10, count 2 2006.257.02:54:38.06#ibcon#about to read 4, iclass 10, count 2 2006.257.02:54:38.06#ibcon#read 4, iclass 10, count 2 2006.257.02:54:38.06#ibcon#about to read 5, iclass 10, count 2 2006.257.02:54:38.06#ibcon#read 5, iclass 10, count 2 2006.257.02:54:38.06#ibcon#about to read 6, iclass 10, count 2 2006.257.02:54:38.06#ibcon#read 6, iclass 10, count 2 2006.257.02:54:38.06#ibcon#end of sib2, iclass 10, count 2 2006.257.02:54:38.06#ibcon#*after write, iclass 10, count 2 2006.257.02:54:38.06#ibcon#*before return 0, iclass 10, count 2 2006.257.02:54:38.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:38.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.02:54:38.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.02:54:38.06#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:38.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:38.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:38.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:38.18#ibcon#enter wrdev, iclass 10, count 0 2006.257.02:54:38.18#ibcon#first serial, iclass 10, count 0 2006.257.02:54:38.18#ibcon#enter sib2, iclass 10, count 0 2006.257.02:54:38.18#ibcon#flushed, iclass 10, count 0 2006.257.02:54:38.18#ibcon#about to write, iclass 10, count 0 2006.257.02:54:38.18#ibcon#wrote, iclass 10, count 0 2006.257.02:54:38.18#ibcon#about to read 3, iclass 10, count 0 2006.257.02:54:38.20#ibcon#read 3, iclass 10, count 0 2006.257.02:54:38.20#ibcon#about to read 4, iclass 10, count 0 2006.257.02:54:38.20#ibcon#read 4, iclass 10, count 0 2006.257.02:54:38.20#ibcon#about to read 5, iclass 10, count 0 2006.257.02:54:38.20#ibcon#read 5, iclass 10, count 0 2006.257.02:54:38.20#ibcon#about to read 6, iclass 10, count 0 2006.257.02:54:38.20#ibcon#read 6, iclass 10, count 0 2006.257.02:54:38.20#ibcon#end of sib2, iclass 10, count 0 2006.257.02:54:38.20#ibcon#*mode == 0, iclass 10, count 0 2006.257.02:54:38.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.02:54:38.20#ibcon#[27=USB\r\n] 2006.257.02:54:38.20#ibcon#*before write, iclass 10, count 0 2006.257.02:54:38.20#ibcon#enter sib2, iclass 10, count 0 2006.257.02:54:38.20#ibcon#flushed, iclass 10, count 0 2006.257.02:54:38.20#ibcon#about to write, iclass 10, count 0 2006.257.02:54:38.20#ibcon#wrote, iclass 10, count 0 2006.257.02:54:38.20#ibcon#about to read 3, iclass 10, count 0 2006.257.02:54:38.23#ibcon#read 3, iclass 10, count 0 2006.257.02:54:38.23#ibcon#about to read 4, iclass 10, count 0 2006.257.02:54:38.23#ibcon#read 4, iclass 10, count 0 2006.257.02:54:38.23#ibcon#about to read 5, iclass 10, count 0 2006.257.02:54:38.23#ibcon#read 5, iclass 10, count 0 2006.257.02:54:38.23#ibcon#about to read 6, iclass 10, count 0 2006.257.02:54:38.23#ibcon#read 6, iclass 10, count 0 2006.257.02:54:38.23#ibcon#end of sib2, iclass 10, count 0 2006.257.02:54:38.23#ibcon#*after write, iclass 10, count 0 2006.257.02:54:38.23#ibcon#*before return 0, iclass 10, count 0 2006.257.02:54:38.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:38.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.02:54:38.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.02:54:38.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.02:54:38.23$vck44/vblo=6,719.99 2006.257.02:54:38.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.02:54:38.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.02:54:38.23#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:38.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:38.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:38.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:38.23#ibcon#enter wrdev, iclass 12, count 0 2006.257.02:54:38.23#ibcon#first serial, iclass 12, count 0 2006.257.02:54:38.23#ibcon#enter sib2, iclass 12, count 0 2006.257.02:54:38.23#ibcon#flushed, iclass 12, count 0 2006.257.02:54:38.23#ibcon#about to write, iclass 12, count 0 2006.257.02:54:38.23#ibcon#wrote, iclass 12, count 0 2006.257.02:54:38.23#ibcon#about to read 3, iclass 12, count 0 2006.257.02:54:38.25#ibcon#read 3, iclass 12, count 0 2006.257.02:54:38.25#ibcon#about to read 4, iclass 12, count 0 2006.257.02:54:38.25#ibcon#read 4, iclass 12, count 0 2006.257.02:54:38.25#ibcon#about to read 5, iclass 12, count 0 2006.257.02:54:38.25#ibcon#read 5, iclass 12, count 0 2006.257.02:54:38.25#ibcon#about to read 6, iclass 12, count 0 2006.257.02:54:38.25#ibcon#read 6, iclass 12, count 0 2006.257.02:54:38.25#ibcon#end of sib2, iclass 12, count 0 2006.257.02:54:38.25#ibcon#*mode == 0, iclass 12, count 0 2006.257.02:54:38.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.02:54:38.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:54:38.25#ibcon#*before write, iclass 12, count 0 2006.257.02:54:38.25#ibcon#enter sib2, iclass 12, count 0 2006.257.02:54:38.25#ibcon#flushed, iclass 12, count 0 2006.257.02:54:38.25#ibcon#about to write, iclass 12, count 0 2006.257.02:54:38.25#ibcon#wrote, iclass 12, count 0 2006.257.02:54:38.25#ibcon#about to read 3, iclass 12, count 0 2006.257.02:54:38.29#ibcon#read 3, iclass 12, count 0 2006.257.02:54:38.29#ibcon#about to read 4, iclass 12, count 0 2006.257.02:54:38.29#ibcon#read 4, iclass 12, count 0 2006.257.02:54:38.29#ibcon#about to read 5, iclass 12, count 0 2006.257.02:54:38.29#ibcon#read 5, iclass 12, count 0 2006.257.02:54:38.29#ibcon#about to read 6, iclass 12, count 0 2006.257.02:54:38.29#ibcon#read 6, iclass 12, count 0 2006.257.02:54:38.29#ibcon#end of sib2, iclass 12, count 0 2006.257.02:54:38.29#ibcon#*after write, iclass 12, count 0 2006.257.02:54:38.29#ibcon#*before return 0, iclass 12, count 0 2006.257.02:54:38.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:38.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.02:54:38.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.02:54:38.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.02:54:38.29$vck44/vb=6,4 2006.257.02:54:38.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.02:54:38.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.02:54:38.29#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:38.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:38.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:38.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:38.35#ibcon#enter wrdev, iclass 14, count 2 2006.257.02:54:38.35#ibcon#first serial, iclass 14, count 2 2006.257.02:54:38.35#ibcon#enter sib2, iclass 14, count 2 2006.257.02:54:38.35#ibcon#flushed, iclass 14, count 2 2006.257.02:54:38.35#ibcon#about to write, iclass 14, count 2 2006.257.02:54:38.35#ibcon#wrote, iclass 14, count 2 2006.257.02:54:38.35#ibcon#about to read 3, iclass 14, count 2 2006.257.02:54:38.37#ibcon#read 3, iclass 14, count 2 2006.257.02:54:38.37#ibcon#about to read 4, iclass 14, count 2 2006.257.02:54:38.37#ibcon#read 4, iclass 14, count 2 2006.257.02:54:38.37#ibcon#about to read 5, iclass 14, count 2 2006.257.02:54:38.37#ibcon#read 5, iclass 14, count 2 2006.257.02:54:38.37#ibcon#about to read 6, iclass 14, count 2 2006.257.02:54:38.37#ibcon#read 6, iclass 14, count 2 2006.257.02:54:38.37#ibcon#end of sib2, iclass 14, count 2 2006.257.02:54:38.37#ibcon#*mode == 0, iclass 14, count 2 2006.257.02:54:38.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.02:54:38.37#ibcon#[27=AT06-04\r\n] 2006.257.02:54:38.37#ibcon#*before write, iclass 14, count 2 2006.257.02:54:38.37#ibcon#enter sib2, iclass 14, count 2 2006.257.02:54:38.37#ibcon#flushed, iclass 14, count 2 2006.257.02:54:38.37#ibcon#about to write, iclass 14, count 2 2006.257.02:54:38.37#ibcon#wrote, iclass 14, count 2 2006.257.02:54:38.37#ibcon#about to read 3, iclass 14, count 2 2006.257.02:54:38.40#ibcon#read 3, iclass 14, count 2 2006.257.02:54:38.40#ibcon#about to read 4, iclass 14, count 2 2006.257.02:54:38.40#ibcon#read 4, iclass 14, count 2 2006.257.02:54:38.40#ibcon#about to read 5, iclass 14, count 2 2006.257.02:54:38.40#ibcon#read 5, iclass 14, count 2 2006.257.02:54:38.40#ibcon#about to read 6, iclass 14, count 2 2006.257.02:54:38.40#ibcon#read 6, iclass 14, count 2 2006.257.02:54:38.40#ibcon#end of sib2, iclass 14, count 2 2006.257.02:54:38.40#ibcon#*after write, iclass 14, count 2 2006.257.02:54:38.40#ibcon#*before return 0, iclass 14, count 2 2006.257.02:54:38.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:38.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.02:54:38.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.02:54:38.40#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:38.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:38.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:38.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:38.52#ibcon#enter wrdev, iclass 14, count 0 2006.257.02:54:38.52#ibcon#first serial, iclass 14, count 0 2006.257.02:54:38.52#ibcon#enter sib2, iclass 14, count 0 2006.257.02:54:38.52#ibcon#flushed, iclass 14, count 0 2006.257.02:54:38.52#ibcon#about to write, iclass 14, count 0 2006.257.02:54:38.52#ibcon#wrote, iclass 14, count 0 2006.257.02:54:38.52#ibcon#about to read 3, iclass 14, count 0 2006.257.02:54:38.54#ibcon#read 3, iclass 14, count 0 2006.257.02:54:38.54#ibcon#about to read 4, iclass 14, count 0 2006.257.02:54:38.54#ibcon#read 4, iclass 14, count 0 2006.257.02:54:38.54#ibcon#about to read 5, iclass 14, count 0 2006.257.02:54:38.54#ibcon#read 5, iclass 14, count 0 2006.257.02:54:38.54#ibcon#about to read 6, iclass 14, count 0 2006.257.02:54:38.54#ibcon#read 6, iclass 14, count 0 2006.257.02:54:38.54#ibcon#end of sib2, iclass 14, count 0 2006.257.02:54:38.54#ibcon#*mode == 0, iclass 14, count 0 2006.257.02:54:38.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.02:54:38.54#ibcon#[27=USB\r\n] 2006.257.02:54:38.54#ibcon#*before write, iclass 14, count 0 2006.257.02:54:38.54#ibcon#enter sib2, iclass 14, count 0 2006.257.02:54:38.54#ibcon#flushed, iclass 14, count 0 2006.257.02:54:38.54#ibcon#about to write, iclass 14, count 0 2006.257.02:54:38.54#ibcon#wrote, iclass 14, count 0 2006.257.02:54:38.54#ibcon#about to read 3, iclass 14, count 0 2006.257.02:54:38.57#ibcon#read 3, iclass 14, count 0 2006.257.02:54:38.57#ibcon#about to read 4, iclass 14, count 0 2006.257.02:54:38.57#ibcon#read 4, iclass 14, count 0 2006.257.02:54:38.57#ibcon#about to read 5, iclass 14, count 0 2006.257.02:54:38.57#ibcon#read 5, iclass 14, count 0 2006.257.02:54:38.57#ibcon#about to read 6, iclass 14, count 0 2006.257.02:54:38.57#ibcon#read 6, iclass 14, count 0 2006.257.02:54:38.57#ibcon#end of sib2, iclass 14, count 0 2006.257.02:54:38.57#ibcon#*after write, iclass 14, count 0 2006.257.02:54:38.57#ibcon#*before return 0, iclass 14, count 0 2006.257.02:54:38.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:38.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.02:54:38.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.02:54:38.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.02:54:38.57$vck44/vblo=7,734.99 2006.257.02:54:38.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.02:54:38.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.02:54:38.57#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:38.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:38.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:38.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:38.57#ibcon#enter wrdev, iclass 16, count 0 2006.257.02:54:38.57#ibcon#first serial, iclass 16, count 0 2006.257.02:54:38.57#ibcon#enter sib2, iclass 16, count 0 2006.257.02:54:38.57#ibcon#flushed, iclass 16, count 0 2006.257.02:54:38.57#ibcon#about to write, iclass 16, count 0 2006.257.02:54:38.57#ibcon#wrote, iclass 16, count 0 2006.257.02:54:38.57#ibcon#about to read 3, iclass 16, count 0 2006.257.02:54:38.59#ibcon#read 3, iclass 16, count 0 2006.257.02:54:38.59#ibcon#about to read 4, iclass 16, count 0 2006.257.02:54:38.59#ibcon#read 4, iclass 16, count 0 2006.257.02:54:38.59#ibcon#about to read 5, iclass 16, count 0 2006.257.02:54:38.59#ibcon#read 5, iclass 16, count 0 2006.257.02:54:38.59#ibcon#about to read 6, iclass 16, count 0 2006.257.02:54:38.59#ibcon#read 6, iclass 16, count 0 2006.257.02:54:38.59#ibcon#end of sib2, iclass 16, count 0 2006.257.02:54:38.59#ibcon#*mode == 0, iclass 16, count 0 2006.257.02:54:38.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.02:54:38.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:54:38.59#ibcon#*before write, iclass 16, count 0 2006.257.02:54:38.59#ibcon#enter sib2, iclass 16, count 0 2006.257.02:54:38.59#ibcon#flushed, iclass 16, count 0 2006.257.02:54:38.59#ibcon#about to write, iclass 16, count 0 2006.257.02:54:38.59#ibcon#wrote, iclass 16, count 0 2006.257.02:54:38.59#ibcon#about to read 3, iclass 16, count 0 2006.257.02:54:38.63#ibcon#read 3, iclass 16, count 0 2006.257.02:54:38.63#ibcon#about to read 4, iclass 16, count 0 2006.257.02:54:38.63#ibcon#read 4, iclass 16, count 0 2006.257.02:54:38.63#ibcon#about to read 5, iclass 16, count 0 2006.257.02:54:38.63#ibcon#read 5, iclass 16, count 0 2006.257.02:54:38.63#ibcon#about to read 6, iclass 16, count 0 2006.257.02:54:38.63#ibcon#read 6, iclass 16, count 0 2006.257.02:54:38.63#ibcon#end of sib2, iclass 16, count 0 2006.257.02:54:38.63#ibcon#*after write, iclass 16, count 0 2006.257.02:54:38.63#ibcon#*before return 0, iclass 16, count 0 2006.257.02:54:38.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:38.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.02:54:38.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.02:54:38.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.02:54:38.63$vck44/vb=7,4 2006.257.02:54:38.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.02:54:38.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.02:54:38.63#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:38.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:38.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:38.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:38.69#ibcon#enter wrdev, iclass 18, count 2 2006.257.02:54:38.69#ibcon#first serial, iclass 18, count 2 2006.257.02:54:38.69#ibcon#enter sib2, iclass 18, count 2 2006.257.02:54:38.69#ibcon#flushed, iclass 18, count 2 2006.257.02:54:38.69#ibcon#about to write, iclass 18, count 2 2006.257.02:54:38.69#ibcon#wrote, iclass 18, count 2 2006.257.02:54:38.69#ibcon#about to read 3, iclass 18, count 2 2006.257.02:54:38.71#ibcon#read 3, iclass 18, count 2 2006.257.02:54:38.71#ibcon#about to read 4, iclass 18, count 2 2006.257.02:54:38.71#ibcon#read 4, iclass 18, count 2 2006.257.02:54:38.71#ibcon#about to read 5, iclass 18, count 2 2006.257.02:54:38.71#ibcon#read 5, iclass 18, count 2 2006.257.02:54:38.71#ibcon#about to read 6, iclass 18, count 2 2006.257.02:54:38.71#ibcon#read 6, iclass 18, count 2 2006.257.02:54:38.71#ibcon#end of sib2, iclass 18, count 2 2006.257.02:54:38.71#ibcon#*mode == 0, iclass 18, count 2 2006.257.02:54:38.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.02:54:38.71#ibcon#[27=AT07-04\r\n] 2006.257.02:54:38.71#ibcon#*before write, iclass 18, count 2 2006.257.02:54:38.71#ibcon#enter sib2, iclass 18, count 2 2006.257.02:54:38.71#ibcon#flushed, iclass 18, count 2 2006.257.02:54:38.71#ibcon#about to write, iclass 18, count 2 2006.257.02:54:38.71#ibcon#wrote, iclass 18, count 2 2006.257.02:54:38.71#ibcon#about to read 3, iclass 18, count 2 2006.257.02:54:38.74#ibcon#read 3, iclass 18, count 2 2006.257.02:54:38.74#ibcon#about to read 4, iclass 18, count 2 2006.257.02:54:38.74#ibcon#read 4, iclass 18, count 2 2006.257.02:54:38.74#ibcon#about to read 5, iclass 18, count 2 2006.257.02:54:38.74#ibcon#read 5, iclass 18, count 2 2006.257.02:54:38.74#ibcon#about to read 6, iclass 18, count 2 2006.257.02:54:38.74#ibcon#read 6, iclass 18, count 2 2006.257.02:54:38.74#ibcon#end of sib2, iclass 18, count 2 2006.257.02:54:38.74#ibcon#*after write, iclass 18, count 2 2006.257.02:54:38.74#ibcon#*before return 0, iclass 18, count 2 2006.257.02:54:38.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:38.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.02:54:38.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.02:54:38.74#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:38.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:38.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:38.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:38.86#ibcon#enter wrdev, iclass 18, count 0 2006.257.02:54:38.86#ibcon#first serial, iclass 18, count 0 2006.257.02:54:38.86#ibcon#enter sib2, iclass 18, count 0 2006.257.02:54:38.86#ibcon#flushed, iclass 18, count 0 2006.257.02:54:38.86#ibcon#about to write, iclass 18, count 0 2006.257.02:54:38.86#ibcon#wrote, iclass 18, count 0 2006.257.02:54:38.86#ibcon#about to read 3, iclass 18, count 0 2006.257.02:54:38.88#ibcon#read 3, iclass 18, count 0 2006.257.02:54:38.88#ibcon#about to read 4, iclass 18, count 0 2006.257.02:54:38.88#ibcon#read 4, iclass 18, count 0 2006.257.02:54:38.88#ibcon#about to read 5, iclass 18, count 0 2006.257.02:54:38.88#ibcon#read 5, iclass 18, count 0 2006.257.02:54:38.88#ibcon#about to read 6, iclass 18, count 0 2006.257.02:54:38.88#ibcon#read 6, iclass 18, count 0 2006.257.02:54:38.88#ibcon#end of sib2, iclass 18, count 0 2006.257.02:54:38.88#ibcon#*mode == 0, iclass 18, count 0 2006.257.02:54:38.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.02:54:38.88#ibcon#[27=USB\r\n] 2006.257.02:54:38.88#ibcon#*before write, iclass 18, count 0 2006.257.02:54:38.88#ibcon#enter sib2, iclass 18, count 0 2006.257.02:54:38.88#ibcon#flushed, iclass 18, count 0 2006.257.02:54:38.88#ibcon#about to write, iclass 18, count 0 2006.257.02:54:38.88#ibcon#wrote, iclass 18, count 0 2006.257.02:54:38.88#ibcon#about to read 3, iclass 18, count 0 2006.257.02:54:38.91#ibcon#read 3, iclass 18, count 0 2006.257.02:54:38.91#ibcon#about to read 4, iclass 18, count 0 2006.257.02:54:38.91#ibcon#read 4, iclass 18, count 0 2006.257.02:54:38.91#ibcon#about to read 5, iclass 18, count 0 2006.257.02:54:38.91#ibcon#read 5, iclass 18, count 0 2006.257.02:54:38.91#ibcon#about to read 6, iclass 18, count 0 2006.257.02:54:38.91#ibcon#read 6, iclass 18, count 0 2006.257.02:54:38.91#ibcon#end of sib2, iclass 18, count 0 2006.257.02:54:38.91#ibcon#*after write, iclass 18, count 0 2006.257.02:54:38.91#ibcon#*before return 0, iclass 18, count 0 2006.257.02:54:38.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:38.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.02:54:38.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.02:54:38.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.02:54:38.91$vck44/vblo=8,744.99 2006.257.02:54:38.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.02:54:38.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.02:54:38.91#ibcon#ireg 17 cls_cnt 0 2006.257.02:54:38.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:38.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:38.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:38.91#ibcon#enter wrdev, iclass 20, count 0 2006.257.02:54:38.91#ibcon#first serial, iclass 20, count 0 2006.257.02:54:38.91#ibcon#enter sib2, iclass 20, count 0 2006.257.02:54:38.91#ibcon#flushed, iclass 20, count 0 2006.257.02:54:38.91#ibcon#about to write, iclass 20, count 0 2006.257.02:54:38.91#ibcon#wrote, iclass 20, count 0 2006.257.02:54:38.91#ibcon#about to read 3, iclass 20, count 0 2006.257.02:54:38.93#ibcon#read 3, iclass 20, count 0 2006.257.02:54:38.93#ibcon#about to read 4, iclass 20, count 0 2006.257.02:54:38.93#ibcon#read 4, iclass 20, count 0 2006.257.02:54:38.93#ibcon#about to read 5, iclass 20, count 0 2006.257.02:54:38.93#ibcon#read 5, iclass 20, count 0 2006.257.02:54:38.93#ibcon#about to read 6, iclass 20, count 0 2006.257.02:54:38.93#ibcon#read 6, iclass 20, count 0 2006.257.02:54:38.93#ibcon#end of sib2, iclass 20, count 0 2006.257.02:54:38.93#ibcon#*mode == 0, iclass 20, count 0 2006.257.02:54:38.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.02:54:38.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:54:38.93#ibcon#*before write, iclass 20, count 0 2006.257.02:54:38.93#ibcon#enter sib2, iclass 20, count 0 2006.257.02:54:38.93#ibcon#flushed, iclass 20, count 0 2006.257.02:54:38.93#ibcon#about to write, iclass 20, count 0 2006.257.02:54:38.93#ibcon#wrote, iclass 20, count 0 2006.257.02:54:38.93#ibcon#about to read 3, iclass 20, count 0 2006.257.02:54:38.97#ibcon#read 3, iclass 20, count 0 2006.257.02:54:38.97#ibcon#about to read 4, iclass 20, count 0 2006.257.02:54:38.97#ibcon#read 4, iclass 20, count 0 2006.257.02:54:38.97#ibcon#about to read 5, iclass 20, count 0 2006.257.02:54:38.97#ibcon#read 5, iclass 20, count 0 2006.257.02:54:38.97#ibcon#about to read 6, iclass 20, count 0 2006.257.02:54:38.97#ibcon#read 6, iclass 20, count 0 2006.257.02:54:38.97#ibcon#end of sib2, iclass 20, count 0 2006.257.02:54:38.97#ibcon#*after write, iclass 20, count 0 2006.257.02:54:38.97#ibcon#*before return 0, iclass 20, count 0 2006.257.02:54:38.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:38.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.02:54:38.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.02:54:38.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.02:54:38.97$vck44/vb=8,4 2006.257.02:54:38.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.02:54:38.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.02:54:38.97#ibcon#ireg 11 cls_cnt 2 2006.257.02:54:38.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:39.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:39.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:39.03#ibcon#enter wrdev, iclass 22, count 2 2006.257.02:54:39.03#ibcon#first serial, iclass 22, count 2 2006.257.02:54:39.03#ibcon#enter sib2, iclass 22, count 2 2006.257.02:54:39.03#ibcon#flushed, iclass 22, count 2 2006.257.02:54:39.03#ibcon#about to write, iclass 22, count 2 2006.257.02:54:39.03#ibcon#wrote, iclass 22, count 2 2006.257.02:54:39.03#ibcon#about to read 3, iclass 22, count 2 2006.257.02:54:39.05#ibcon#read 3, iclass 22, count 2 2006.257.02:54:39.05#ibcon#about to read 4, iclass 22, count 2 2006.257.02:54:39.05#ibcon#read 4, iclass 22, count 2 2006.257.02:54:39.05#ibcon#about to read 5, iclass 22, count 2 2006.257.02:54:39.05#ibcon#read 5, iclass 22, count 2 2006.257.02:54:39.05#ibcon#about to read 6, iclass 22, count 2 2006.257.02:54:39.05#ibcon#read 6, iclass 22, count 2 2006.257.02:54:39.05#ibcon#end of sib2, iclass 22, count 2 2006.257.02:54:39.05#ibcon#*mode == 0, iclass 22, count 2 2006.257.02:54:39.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.02:54:39.05#ibcon#[27=AT08-04\r\n] 2006.257.02:54:39.05#ibcon#*before write, iclass 22, count 2 2006.257.02:54:39.05#ibcon#enter sib2, iclass 22, count 2 2006.257.02:54:39.05#ibcon#flushed, iclass 22, count 2 2006.257.02:54:39.05#ibcon#about to write, iclass 22, count 2 2006.257.02:54:39.05#ibcon#wrote, iclass 22, count 2 2006.257.02:54:39.05#ibcon#about to read 3, iclass 22, count 2 2006.257.02:54:39.08#ibcon#read 3, iclass 22, count 2 2006.257.02:54:39.08#ibcon#about to read 4, iclass 22, count 2 2006.257.02:54:39.08#ibcon#read 4, iclass 22, count 2 2006.257.02:54:39.08#ibcon#about to read 5, iclass 22, count 2 2006.257.02:54:39.08#ibcon#read 5, iclass 22, count 2 2006.257.02:54:39.08#ibcon#about to read 6, iclass 22, count 2 2006.257.02:54:39.08#ibcon#read 6, iclass 22, count 2 2006.257.02:54:39.08#ibcon#end of sib2, iclass 22, count 2 2006.257.02:54:39.08#ibcon#*after write, iclass 22, count 2 2006.257.02:54:39.08#ibcon#*before return 0, iclass 22, count 2 2006.257.02:54:39.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:39.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.02:54:39.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.02:54:39.08#ibcon#ireg 7 cls_cnt 0 2006.257.02:54:39.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:39.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:39.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:39.20#ibcon#enter wrdev, iclass 22, count 0 2006.257.02:54:39.20#ibcon#first serial, iclass 22, count 0 2006.257.02:54:39.20#ibcon#enter sib2, iclass 22, count 0 2006.257.02:54:39.20#ibcon#flushed, iclass 22, count 0 2006.257.02:54:39.20#ibcon#about to write, iclass 22, count 0 2006.257.02:54:39.20#ibcon#wrote, iclass 22, count 0 2006.257.02:54:39.20#ibcon#about to read 3, iclass 22, count 0 2006.257.02:54:39.22#ibcon#read 3, iclass 22, count 0 2006.257.02:54:39.22#ibcon#about to read 4, iclass 22, count 0 2006.257.02:54:39.22#ibcon#read 4, iclass 22, count 0 2006.257.02:54:39.22#ibcon#about to read 5, iclass 22, count 0 2006.257.02:54:39.22#ibcon#read 5, iclass 22, count 0 2006.257.02:54:39.22#ibcon#about to read 6, iclass 22, count 0 2006.257.02:54:39.22#ibcon#read 6, iclass 22, count 0 2006.257.02:54:39.22#ibcon#end of sib2, iclass 22, count 0 2006.257.02:54:39.22#ibcon#*mode == 0, iclass 22, count 0 2006.257.02:54:39.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.02:54:39.22#ibcon#[27=USB\r\n] 2006.257.02:54:39.22#ibcon#*before write, iclass 22, count 0 2006.257.02:54:39.22#ibcon#enter sib2, iclass 22, count 0 2006.257.02:54:39.22#ibcon#flushed, iclass 22, count 0 2006.257.02:54:39.22#ibcon#about to write, iclass 22, count 0 2006.257.02:54:39.22#ibcon#wrote, iclass 22, count 0 2006.257.02:54:39.22#ibcon#about to read 3, iclass 22, count 0 2006.257.02:54:39.25#ibcon#read 3, iclass 22, count 0 2006.257.02:54:39.25#ibcon#about to read 4, iclass 22, count 0 2006.257.02:54:39.25#ibcon#read 4, iclass 22, count 0 2006.257.02:54:39.25#ibcon#about to read 5, iclass 22, count 0 2006.257.02:54:39.25#ibcon#read 5, iclass 22, count 0 2006.257.02:54:39.25#ibcon#about to read 6, iclass 22, count 0 2006.257.02:54:39.25#ibcon#read 6, iclass 22, count 0 2006.257.02:54:39.25#ibcon#end of sib2, iclass 22, count 0 2006.257.02:54:39.25#ibcon#*after write, iclass 22, count 0 2006.257.02:54:39.25#ibcon#*before return 0, iclass 22, count 0 2006.257.02:54:39.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:39.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.02:54:39.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.02:54:39.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.02:54:39.25$vck44/vabw=wide 2006.257.02:54:39.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.02:54:39.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.02:54:39.25#ibcon#ireg 8 cls_cnt 0 2006.257.02:54:39.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:39.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:39.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:39.25#ibcon#enter wrdev, iclass 24, count 0 2006.257.02:54:39.25#ibcon#first serial, iclass 24, count 0 2006.257.02:54:39.25#ibcon#enter sib2, iclass 24, count 0 2006.257.02:54:39.25#ibcon#flushed, iclass 24, count 0 2006.257.02:54:39.25#ibcon#about to write, iclass 24, count 0 2006.257.02:54:39.25#ibcon#wrote, iclass 24, count 0 2006.257.02:54:39.25#ibcon#about to read 3, iclass 24, count 0 2006.257.02:54:39.27#ibcon#read 3, iclass 24, count 0 2006.257.02:54:39.27#ibcon#about to read 4, iclass 24, count 0 2006.257.02:54:39.27#ibcon#read 4, iclass 24, count 0 2006.257.02:54:39.27#ibcon#about to read 5, iclass 24, count 0 2006.257.02:54:39.27#ibcon#read 5, iclass 24, count 0 2006.257.02:54:39.27#ibcon#about to read 6, iclass 24, count 0 2006.257.02:54:39.27#ibcon#read 6, iclass 24, count 0 2006.257.02:54:39.27#ibcon#end of sib2, iclass 24, count 0 2006.257.02:54:39.27#ibcon#*mode == 0, iclass 24, count 0 2006.257.02:54:39.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.02:54:39.27#ibcon#[25=BW32\r\n] 2006.257.02:54:39.27#ibcon#*before write, iclass 24, count 0 2006.257.02:54:39.27#ibcon#enter sib2, iclass 24, count 0 2006.257.02:54:39.27#ibcon#flushed, iclass 24, count 0 2006.257.02:54:39.27#ibcon#about to write, iclass 24, count 0 2006.257.02:54:39.27#ibcon#wrote, iclass 24, count 0 2006.257.02:54:39.27#ibcon#about to read 3, iclass 24, count 0 2006.257.02:54:39.30#ibcon#read 3, iclass 24, count 0 2006.257.02:54:39.30#ibcon#about to read 4, iclass 24, count 0 2006.257.02:54:39.30#ibcon#read 4, iclass 24, count 0 2006.257.02:54:39.30#ibcon#about to read 5, iclass 24, count 0 2006.257.02:54:39.30#ibcon#read 5, iclass 24, count 0 2006.257.02:54:39.30#ibcon#about to read 6, iclass 24, count 0 2006.257.02:54:39.30#ibcon#read 6, iclass 24, count 0 2006.257.02:54:39.30#ibcon#end of sib2, iclass 24, count 0 2006.257.02:54:39.30#ibcon#*after write, iclass 24, count 0 2006.257.02:54:39.30#ibcon#*before return 0, iclass 24, count 0 2006.257.02:54:39.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:39.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.02:54:39.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.02:54:39.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.02:54:39.30$vck44/vbbw=wide 2006.257.02:54:39.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.02:54:39.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.02:54:39.30#ibcon#ireg 8 cls_cnt 0 2006.257.02:54:39.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:54:39.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:54:39.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:54:39.37#ibcon#enter wrdev, iclass 26, count 0 2006.257.02:54:39.37#ibcon#first serial, iclass 26, count 0 2006.257.02:54:39.37#ibcon#enter sib2, iclass 26, count 0 2006.257.02:54:39.37#ibcon#flushed, iclass 26, count 0 2006.257.02:54:39.37#ibcon#about to write, iclass 26, count 0 2006.257.02:54:39.37#ibcon#wrote, iclass 26, count 0 2006.257.02:54:39.37#ibcon#about to read 3, iclass 26, count 0 2006.257.02:54:39.39#ibcon#read 3, iclass 26, count 0 2006.257.02:54:39.39#ibcon#about to read 4, iclass 26, count 0 2006.257.02:54:39.39#ibcon#read 4, iclass 26, count 0 2006.257.02:54:39.39#ibcon#about to read 5, iclass 26, count 0 2006.257.02:54:39.39#ibcon#read 5, iclass 26, count 0 2006.257.02:54:39.39#ibcon#about to read 6, iclass 26, count 0 2006.257.02:54:39.39#ibcon#read 6, iclass 26, count 0 2006.257.02:54:39.39#ibcon#end of sib2, iclass 26, count 0 2006.257.02:54:39.39#ibcon#*mode == 0, iclass 26, count 0 2006.257.02:54:39.39#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.02:54:39.39#ibcon#[27=BW32\r\n] 2006.257.02:54:39.39#ibcon#*before write, iclass 26, count 0 2006.257.02:54:39.39#ibcon#enter sib2, iclass 26, count 0 2006.257.02:54:39.39#ibcon#flushed, iclass 26, count 0 2006.257.02:54:39.39#ibcon#about to write, iclass 26, count 0 2006.257.02:54:39.39#ibcon#wrote, iclass 26, count 0 2006.257.02:54:39.39#ibcon#about to read 3, iclass 26, count 0 2006.257.02:54:39.42#ibcon#read 3, iclass 26, count 0 2006.257.02:54:39.42#ibcon#about to read 4, iclass 26, count 0 2006.257.02:54:39.42#ibcon#read 4, iclass 26, count 0 2006.257.02:54:39.42#ibcon#about to read 5, iclass 26, count 0 2006.257.02:54:39.42#ibcon#read 5, iclass 26, count 0 2006.257.02:54:39.42#ibcon#about to read 6, iclass 26, count 0 2006.257.02:54:39.42#ibcon#read 6, iclass 26, count 0 2006.257.02:54:39.42#ibcon#end of sib2, iclass 26, count 0 2006.257.02:54:39.42#ibcon#*after write, iclass 26, count 0 2006.257.02:54:39.42#ibcon#*before return 0, iclass 26, count 0 2006.257.02:54:39.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:54:39.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.02:54:39.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.02:54:39.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.02:54:39.42$setupk4/ifdk4 2006.257.02:54:39.42$ifdk4/lo= 2006.257.02:54:39.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:54:39.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:54:39.42$ifdk4/patch= 2006.257.02:54:39.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:54:39.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:54:39.42$setupk4/!*+20s 2006.257.02:54:46.96#abcon#<5=/16 2.1 5.6 18.88 901012.5\r\n> 2006.257.02:54:46.98#abcon#{5=INTERFACE CLEAR} 2006.257.02:54:47.04#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:54:53.91$setupk4/"tpicd 2006.257.02:54:53.91$setupk4/echo=off 2006.257.02:54:53.91$setupk4/xlog=off 2006.257.02:54:53.91:!2006.257.02:56:06 2006.257.02:55:02.14#trakl#Source acquired 2006.257.02:55:04.14#flagr#flagr/antenna,acquired 2006.257.02:56:06.00:preob 2006.257.02:56:06.14/onsource/TRACKING 2006.257.02:56:06.14:!2006.257.02:56:16 2006.257.02:56:16.00:"tape 2006.257.02:56:16.00:"st=record 2006.257.02:56:16.00:data_valid=on 2006.257.02:56:16.00:midob 2006.257.02:56:16.14/onsource/TRACKING 2006.257.02:56:16.14/wx/18.87,1012.5,90 2006.257.02:56:16.19/cable/+6.4881E-03 2006.257.02:56:17.28/va/01,08,usb,yes,44,47 2006.257.02:56:17.28/va/02,07,usb,yes,48,48 2006.257.02:56:17.28/va/03,08,usb,yes,43,45 2006.257.02:56:17.28/va/04,07,usb,yes,49,51 2006.257.02:56:17.28/va/05,04,usb,yes,44,45 2006.257.02:56:17.28/va/06,04,usb,yes,48,48 2006.257.02:56:17.28/va/07,04,usb,yes,50,50 2006.257.02:56:17.28/va/08,04,usb,yes,42,51 2006.257.02:56:17.51/valo/01,524.99,yes,locked 2006.257.02:56:17.51/valo/02,534.99,yes,locked 2006.257.02:56:17.51/valo/03,564.99,yes,locked 2006.257.02:56:17.51/valo/04,624.99,yes,locked 2006.257.02:56:17.51/valo/05,734.99,yes,locked 2006.257.02:56:17.51/valo/06,814.99,yes,locked 2006.257.02:56:17.51/valo/07,864.99,yes,locked 2006.257.02:56:17.51/valo/08,884.99,yes,locked 2006.257.02:56:18.60/vb/01,04,usb,yes,36,34 2006.257.02:56:18.60/vb/02,05,usb,yes,35,34 2006.257.02:56:18.60/vb/03,04,usb,yes,36,39 2006.257.02:56:18.60/vb/04,05,usb,yes,36,35 2006.257.02:56:18.60/vb/05,04,usb,yes,32,35 2006.257.02:56:18.60/vb/06,04,usb,yes,38,33 2006.257.02:56:18.60/vb/07,04,usb,yes,37,37 2006.257.02:56:18.60/vb/08,04,usb,yes,34,38 2006.257.02:56:18.83/vblo/01,629.99,yes,locked 2006.257.02:56:18.83/vblo/02,634.99,yes,locked 2006.257.02:56:18.83/vblo/03,649.99,yes,locked 2006.257.02:56:18.83/vblo/04,679.99,yes,locked 2006.257.02:56:18.83/vblo/05,709.99,yes,locked 2006.257.02:56:18.83/vblo/06,719.99,yes,locked 2006.257.02:56:18.83/vblo/07,734.99,yes,locked 2006.257.02:56:18.83/vblo/08,744.99,yes,locked 2006.257.02:56:18.98/vabw/8 2006.257.02:56:19.13/vbbw/8 2006.257.02:56:19.22/xfe/off,on,15.5 2006.257.02:56:19.60/ifatt/23,28,28,28 2006.257.02:56:20.08/fmout-gps/S +4.57E-07 2006.257.02:56:20.12:!2006.257.02:59:36 2006.257.02:59:36.00:data_valid=off 2006.257.02:59:36.00:"et 2006.257.02:59:36.00:!+3s 2006.257.02:59:39.01:"tape 2006.257.02:59:39.01:postob 2006.257.02:59:39.17/cable/+6.4871E-03 2006.257.02:59:39.17/wx/18.91,1012.5,90 2006.257.02:59:40.08/fmout-gps/S +4.56E-07 2006.257.02:59:40.08:scan_name=257-0301,jd0609,300 2006.257.02:59:40.08:source=oj287,085448.87,200630.6,2000.0,ccw 2006.257.02:59:41.14#flagr#flagr/antenna,new-source 2006.257.02:59:41.14:checkk5 2006.257.02:59:41.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.02:59:41.87/chk_autoobs//k5ts2/ autoobs is running! 2006.257.02:59:42.25/chk_autoobs//k5ts3/ autoobs is running! 2006.257.02:59:42.62/chk_autoobs//k5ts4/ autoobs is running! 2006.257.02:59:42.98/chk_obsdata//k5ts1/T2570256??a.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.02:59:43.33/chk_obsdata//k5ts2/T2570256??b.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.02:59:43.70/chk_obsdata//k5ts3/T2570256??c.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.02:59:44.07/chk_obsdata//k5ts4/T2570256??d.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.02:59:44.75/k5log//k5ts1_log_newline 2006.257.02:59:45.45/k5log//k5ts2_log_newline 2006.257.02:59:46.17/k5log//k5ts3_log_newline 2006.257.02:59:46.84/k5log//k5ts4_log_newline 2006.257.02:59:46.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.02:59:46.86:setupk4=1 2006.257.02:59:46.86$setupk4/echo=on 2006.257.02:59:46.87$setupk4/pcalon 2006.257.02:59:46.87$pcalon/"no phase cal control is implemented here 2006.257.02:59:46.87$setupk4/"tpicd=stop 2006.257.02:59:46.87$setupk4/"rec=synch_on 2006.257.02:59:46.87$setupk4/"rec_mode=128 2006.257.02:59:46.87$setupk4/!* 2006.257.02:59:46.87$setupk4/recpk4 2006.257.02:59:46.87$recpk4/recpatch= 2006.257.02:59:46.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.02:59:46.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.02:59:46.87$setupk4/vck44 2006.257.02:59:46.87$vck44/valo=1,524.99 2006.257.02:59:46.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.02:59:46.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.02:59:46.87#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:46.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:46.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:46.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:46.87#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:59:46.87#ibcon#first serial, iclass 5, count 0 2006.257.02:59:46.87#ibcon#enter sib2, iclass 5, count 0 2006.257.02:59:46.87#ibcon#flushed, iclass 5, count 0 2006.257.02:59:46.87#ibcon#about to write, iclass 5, count 0 2006.257.02:59:46.87#ibcon#wrote, iclass 5, count 0 2006.257.02:59:46.87#ibcon#about to read 3, iclass 5, count 0 2006.257.02:59:46.90#ibcon#read 3, iclass 5, count 0 2006.257.02:59:46.90#ibcon#about to read 4, iclass 5, count 0 2006.257.02:59:46.90#ibcon#read 4, iclass 5, count 0 2006.257.02:59:46.90#ibcon#about to read 5, iclass 5, count 0 2006.257.02:59:46.90#ibcon#read 5, iclass 5, count 0 2006.257.02:59:46.90#ibcon#about to read 6, iclass 5, count 0 2006.257.02:59:46.90#ibcon#read 6, iclass 5, count 0 2006.257.02:59:46.90#ibcon#end of sib2, iclass 5, count 0 2006.257.02:59:46.90#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:59:46.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:59:46.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.02:59:46.90#ibcon#*before write, iclass 5, count 0 2006.257.02:59:46.90#ibcon#enter sib2, iclass 5, count 0 2006.257.02:59:46.90#ibcon#flushed, iclass 5, count 0 2006.257.02:59:46.90#ibcon#about to write, iclass 5, count 0 2006.257.02:59:46.90#ibcon#wrote, iclass 5, count 0 2006.257.02:59:46.90#ibcon#about to read 3, iclass 5, count 0 2006.257.02:59:46.95#ibcon#read 3, iclass 5, count 0 2006.257.02:59:46.95#ibcon#about to read 4, iclass 5, count 0 2006.257.02:59:46.95#ibcon#read 4, iclass 5, count 0 2006.257.02:59:46.95#ibcon#about to read 5, iclass 5, count 0 2006.257.02:59:46.95#ibcon#read 5, iclass 5, count 0 2006.257.02:59:46.95#ibcon#about to read 6, iclass 5, count 0 2006.257.02:59:46.95#ibcon#read 6, iclass 5, count 0 2006.257.02:59:46.95#ibcon#end of sib2, iclass 5, count 0 2006.257.02:59:46.95#ibcon#*after write, iclass 5, count 0 2006.257.02:59:46.95#ibcon#*before return 0, iclass 5, count 0 2006.257.02:59:46.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:46.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:46.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:59:46.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:59:46.95$vck44/va=1,8 2006.257.02:59:46.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.02:59:46.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.02:59:46.95#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:46.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:46.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:46.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:46.95#ibcon#enter wrdev, iclass 7, count 2 2006.257.02:59:46.95#ibcon#first serial, iclass 7, count 2 2006.257.02:59:46.95#ibcon#enter sib2, iclass 7, count 2 2006.257.02:59:46.95#ibcon#flushed, iclass 7, count 2 2006.257.02:59:46.95#ibcon#about to write, iclass 7, count 2 2006.257.02:59:46.95#ibcon#wrote, iclass 7, count 2 2006.257.02:59:46.95#ibcon#about to read 3, iclass 7, count 2 2006.257.02:59:46.97#ibcon#read 3, iclass 7, count 2 2006.257.02:59:46.97#ibcon#about to read 4, iclass 7, count 2 2006.257.02:59:46.97#ibcon#read 4, iclass 7, count 2 2006.257.02:59:46.97#ibcon#about to read 5, iclass 7, count 2 2006.257.02:59:46.97#ibcon#read 5, iclass 7, count 2 2006.257.02:59:46.97#ibcon#about to read 6, iclass 7, count 2 2006.257.02:59:46.97#ibcon#read 6, iclass 7, count 2 2006.257.02:59:46.97#ibcon#end of sib2, iclass 7, count 2 2006.257.02:59:46.97#ibcon#*mode == 0, iclass 7, count 2 2006.257.02:59:46.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.02:59:46.97#ibcon#[25=AT01-08\r\n] 2006.257.02:59:46.97#ibcon#*before write, iclass 7, count 2 2006.257.02:59:46.97#ibcon#enter sib2, iclass 7, count 2 2006.257.02:59:46.97#ibcon#flushed, iclass 7, count 2 2006.257.02:59:46.97#ibcon#about to write, iclass 7, count 2 2006.257.02:59:46.97#ibcon#wrote, iclass 7, count 2 2006.257.02:59:46.97#ibcon#about to read 3, iclass 7, count 2 2006.257.02:59:47.00#ibcon#read 3, iclass 7, count 2 2006.257.02:59:47.00#ibcon#about to read 4, iclass 7, count 2 2006.257.02:59:47.00#ibcon#read 4, iclass 7, count 2 2006.257.02:59:47.00#ibcon#about to read 5, iclass 7, count 2 2006.257.02:59:47.00#ibcon#read 5, iclass 7, count 2 2006.257.02:59:47.00#ibcon#about to read 6, iclass 7, count 2 2006.257.02:59:47.00#ibcon#read 6, iclass 7, count 2 2006.257.02:59:47.00#ibcon#end of sib2, iclass 7, count 2 2006.257.02:59:47.00#ibcon#*after write, iclass 7, count 2 2006.257.02:59:47.00#ibcon#*before return 0, iclass 7, count 2 2006.257.02:59:47.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:47.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:47.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.02:59:47.00#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:47.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:47.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:47.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:47.12#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:59:47.12#ibcon#first serial, iclass 7, count 0 2006.257.02:59:47.12#ibcon#enter sib2, iclass 7, count 0 2006.257.02:59:47.12#ibcon#flushed, iclass 7, count 0 2006.257.02:59:47.12#ibcon#about to write, iclass 7, count 0 2006.257.02:59:47.12#ibcon#wrote, iclass 7, count 0 2006.257.02:59:47.12#ibcon#about to read 3, iclass 7, count 0 2006.257.02:59:47.14#ibcon#read 3, iclass 7, count 0 2006.257.02:59:47.14#ibcon#about to read 4, iclass 7, count 0 2006.257.02:59:47.14#ibcon#read 4, iclass 7, count 0 2006.257.02:59:47.14#ibcon#about to read 5, iclass 7, count 0 2006.257.02:59:47.14#ibcon#read 5, iclass 7, count 0 2006.257.02:59:47.14#ibcon#about to read 6, iclass 7, count 0 2006.257.02:59:47.14#ibcon#read 6, iclass 7, count 0 2006.257.02:59:47.14#ibcon#end of sib2, iclass 7, count 0 2006.257.02:59:47.14#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:59:47.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:59:47.14#ibcon#[25=USB\r\n] 2006.257.02:59:47.14#ibcon#*before write, iclass 7, count 0 2006.257.02:59:47.14#ibcon#enter sib2, iclass 7, count 0 2006.257.02:59:47.14#ibcon#flushed, iclass 7, count 0 2006.257.02:59:47.14#ibcon#about to write, iclass 7, count 0 2006.257.02:59:47.14#ibcon#wrote, iclass 7, count 0 2006.257.02:59:47.14#ibcon#about to read 3, iclass 7, count 0 2006.257.02:59:47.17#ibcon#read 3, iclass 7, count 0 2006.257.02:59:47.17#ibcon#about to read 4, iclass 7, count 0 2006.257.02:59:47.17#ibcon#read 4, iclass 7, count 0 2006.257.02:59:47.17#ibcon#about to read 5, iclass 7, count 0 2006.257.02:59:47.17#ibcon#read 5, iclass 7, count 0 2006.257.02:59:47.17#ibcon#about to read 6, iclass 7, count 0 2006.257.02:59:47.17#ibcon#read 6, iclass 7, count 0 2006.257.02:59:47.17#ibcon#end of sib2, iclass 7, count 0 2006.257.02:59:47.17#ibcon#*after write, iclass 7, count 0 2006.257.02:59:47.17#ibcon#*before return 0, iclass 7, count 0 2006.257.02:59:47.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:47.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:47.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:59:47.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:59:47.17$vck44/valo=2,534.99 2006.257.02:59:47.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.02:59:47.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.02:59:47.17#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:47.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:47.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:47.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:47.17#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:59:47.17#ibcon#first serial, iclass 11, count 0 2006.257.02:59:47.17#ibcon#enter sib2, iclass 11, count 0 2006.257.02:59:47.17#ibcon#flushed, iclass 11, count 0 2006.257.02:59:47.17#ibcon#about to write, iclass 11, count 0 2006.257.02:59:47.17#ibcon#wrote, iclass 11, count 0 2006.257.02:59:47.17#ibcon#about to read 3, iclass 11, count 0 2006.257.02:59:47.19#ibcon#read 3, iclass 11, count 0 2006.257.02:59:47.19#ibcon#about to read 4, iclass 11, count 0 2006.257.02:59:47.19#ibcon#read 4, iclass 11, count 0 2006.257.02:59:47.19#ibcon#about to read 5, iclass 11, count 0 2006.257.02:59:47.19#ibcon#read 5, iclass 11, count 0 2006.257.02:59:47.19#ibcon#about to read 6, iclass 11, count 0 2006.257.02:59:47.19#ibcon#read 6, iclass 11, count 0 2006.257.02:59:47.19#ibcon#end of sib2, iclass 11, count 0 2006.257.02:59:47.19#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:59:47.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:59:47.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.02:59:47.19#ibcon#*before write, iclass 11, count 0 2006.257.02:59:47.19#ibcon#enter sib2, iclass 11, count 0 2006.257.02:59:47.19#ibcon#flushed, iclass 11, count 0 2006.257.02:59:47.19#ibcon#about to write, iclass 11, count 0 2006.257.02:59:47.19#ibcon#wrote, iclass 11, count 0 2006.257.02:59:47.19#ibcon#about to read 3, iclass 11, count 0 2006.257.02:59:47.23#ibcon#read 3, iclass 11, count 0 2006.257.02:59:47.23#ibcon#about to read 4, iclass 11, count 0 2006.257.02:59:47.23#ibcon#read 4, iclass 11, count 0 2006.257.02:59:47.23#ibcon#about to read 5, iclass 11, count 0 2006.257.02:59:47.23#ibcon#read 5, iclass 11, count 0 2006.257.02:59:47.23#ibcon#about to read 6, iclass 11, count 0 2006.257.02:59:47.23#ibcon#read 6, iclass 11, count 0 2006.257.02:59:47.23#ibcon#end of sib2, iclass 11, count 0 2006.257.02:59:47.23#ibcon#*after write, iclass 11, count 0 2006.257.02:59:47.23#ibcon#*before return 0, iclass 11, count 0 2006.257.02:59:47.23#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:47.23#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:47.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:59:47.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:59:47.23$vck44/va=2,7 2006.257.02:59:47.23#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.02:59:47.23#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.02:59:47.23#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:47.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:47.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:47.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:47.29#ibcon#enter wrdev, iclass 13, count 2 2006.257.02:59:47.29#ibcon#first serial, iclass 13, count 2 2006.257.02:59:47.29#ibcon#enter sib2, iclass 13, count 2 2006.257.02:59:47.29#ibcon#flushed, iclass 13, count 2 2006.257.02:59:47.29#ibcon#about to write, iclass 13, count 2 2006.257.02:59:47.29#ibcon#wrote, iclass 13, count 2 2006.257.02:59:47.29#ibcon#about to read 3, iclass 13, count 2 2006.257.02:59:47.31#ibcon#read 3, iclass 13, count 2 2006.257.02:59:47.31#ibcon#about to read 4, iclass 13, count 2 2006.257.02:59:47.31#ibcon#read 4, iclass 13, count 2 2006.257.02:59:47.31#ibcon#about to read 5, iclass 13, count 2 2006.257.02:59:47.31#ibcon#read 5, iclass 13, count 2 2006.257.02:59:47.31#ibcon#about to read 6, iclass 13, count 2 2006.257.02:59:47.31#ibcon#read 6, iclass 13, count 2 2006.257.02:59:47.31#ibcon#end of sib2, iclass 13, count 2 2006.257.02:59:47.31#ibcon#*mode == 0, iclass 13, count 2 2006.257.02:59:47.31#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.02:59:47.31#ibcon#[25=AT02-07\r\n] 2006.257.02:59:47.31#ibcon#*before write, iclass 13, count 2 2006.257.02:59:47.31#ibcon#enter sib2, iclass 13, count 2 2006.257.02:59:47.31#ibcon#flushed, iclass 13, count 2 2006.257.02:59:47.31#ibcon#about to write, iclass 13, count 2 2006.257.02:59:47.31#ibcon#wrote, iclass 13, count 2 2006.257.02:59:47.31#ibcon#about to read 3, iclass 13, count 2 2006.257.02:59:47.34#ibcon#read 3, iclass 13, count 2 2006.257.02:59:47.34#ibcon#about to read 4, iclass 13, count 2 2006.257.02:59:47.34#ibcon#read 4, iclass 13, count 2 2006.257.02:59:47.34#ibcon#about to read 5, iclass 13, count 2 2006.257.02:59:47.34#ibcon#read 5, iclass 13, count 2 2006.257.02:59:47.34#ibcon#about to read 6, iclass 13, count 2 2006.257.02:59:47.34#ibcon#read 6, iclass 13, count 2 2006.257.02:59:47.34#ibcon#end of sib2, iclass 13, count 2 2006.257.02:59:47.34#ibcon#*after write, iclass 13, count 2 2006.257.02:59:47.34#ibcon#*before return 0, iclass 13, count 2 2006.257.02:59:47.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:47.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:47.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.02:59:47.34#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:47.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:47.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:47.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:47.46#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:59:47.46#ibcon#first serial, iclass 13, count 0 2006.257.02:59:47.46#ibcon#enter sib2, iclass 13, count 0 2006.257.02:59:47.46#ibcon#flushed, iclass 13, count 0 2006.257.02:59:47.46#ibcon#about to write, iclass 13, count 0 2006.257.02:59:47.46#ibcon#wrote, iclass 13, count 0 2006.257.02:59:47.46#ibcon#about to read 3, iclass 13, count 0 2006.257.02:59:47.48#ibcon#read 3, iclass 13, count 0 2006.257.02:59:47.48#ibcon#about to read 4, iclass 13, count 0 2006.257.02:59:47.48#ibcon#read 4, iclass 13, count 0 2006.257.02:59:47.48#ibcon#about to read 5, iclass 13, count 0 2006.257.02:59:47.48#ibcon#read 5, iclass 13, count 0 2006.257.02:59:47.48#ibcon#about to read 6, iclass 13, count 0 2006.257.02:59:47.48#ibcon#read 6, iclass 13, count 0 2006.257.02:59:47.48#ibcon#end of sib2, iclass 13, count 0 2006.257.02:59:47.48#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:59:47.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:59:47.48#ibcon#[25=USB\r\n] 2006.257.02:59:47.48#ibcon#*before write, iclass 13, count 0 2006.257.02:59:47.48#ibcon#enter sib2, iclass 13, count 0 2006.257.02:59:47.48#ibcon#flushed, iclass 13, count 0 2006.257.02:59:47.48#ibcon#about to write, iclass 13, count 0 2006.257.02:59:47.48#ibcon#wrote, iclass 13, count 0 2006.257.02:59:47.48#ibcon#about to read 3, iclass 13, count 0 2006.257.02:59:47.51#ibcon#read 3, iclass 13, count 0 2006.257.02:59:47.51#ibcon#about to read 4, iclass 13, count 0 2006.257.02:59:47.51#ibcon#read 4, iclass 13, count 0 2006.257.02:59:47.51#ibcon#about to read 5, iclass 13, count 0 2006.257.02:59:47.51#ibcon#read 5, iclass 13, count 0 2006.257.02:59:47.51#ibcon#about to read 6, iclass 13, count 0 2006.257.02:59:47.51#ibcon#read 6, iclass 13, count 0 2006.257.02:59:47.51#ibcon#end of sib2, iclass 13, count 0 2006.257.02:59:47.51#ibcon#*after write, iclass 13, count 0 2006.257.02:59:47.51#ibcon#*before return 0, iclass 13, count 0 2006.257.02:59:47.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:47.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:47.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:59:47.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:59:47.51$vck44/valo=3,564.99 2006.257.02:59:47.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.02:59:47.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.02:59:47.51#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:47.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:47.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:47.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:47.51#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:59:47.51#ibcon#first serial, iclass 15, count 0 2006.257.02:59:47.51#ibcon#enter sib2, iclass 15, count 0 2006.257.02:59:47.51#ibcon#flushed, iclass 15, count 0 2006.257.02:59:47.51#ibcon#about to write, iclass 15, count 0 2006.257.02:59:47.51#ibcon#wrote, iclass 15, count 0 2006.257.02:59:47.51#ibcon#about to read 3, iclass 15, count 0 2006.257.02:59:47.53#ibcon#read 3, iclass 15, count 0 2006.257.02:59:47.53#ibcon#about to read 4, iclass 15, count 0 2006.257.02:59:47.53#ibcon#read 4, iclass 15, count 0 2006.257.02:59:47.53#ibcon#about to read 5, iclass 15, count 0 2006.257.02:59:47.53#ibcon#read 5, iclass 15, count 0 2006.257.02:59:47.53#ibcon#about to read 6, iclass 15, count 0 2006.257.02:59:47.53#ibcon#read 6, iclass 15, count 0 2006.257.02:59:47.53#ibcon#end of sib2, iclass 15, count 0 2006.257.02:59:47.53#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:59:47.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:59:47.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.02:59:47.53#ibcon#*before write, iclass 15, count 0 2006.257.02:59:47.53#ibcon#enter sib2, iclass 15, count 0 2006.257.02:59:47.53#ibcon#flushed, iclass 15, count 0 2006.257.02:59:47.53#ibcon#about to write, iclass 15, count 0 2006.257.02:59:47.53#ibcon#wrote, iclass 15, count 0 2006.257.02:59:47.53#ibcon#about to read 3, iclass 15, count 0 2006.257.02:59:47.57#ibcon#read 3, iclass 15, count 0 2006.257.02:59:47.57#ibcon#about to read 4, iclass 15, count 0 2006.257.02:59:47.57#ibcon#read 4, iclass 15, count 0 2006.257.02:59:47.57#ibcon#about to read 5, iclass 15, count 0 2006.257.02:59:47.57#ibcon#read 5, iclass 15, count 0 2006.257.02:59:47.57#ibcon#about to read 6, iclass 15, count 0 2006.257.02:59:47.57#ibcon#read 6, iclass 15, count 0 2006.257.02:59:47.57#ibcon#end of sib2, iclass 15, count 0 2006.257.02:59:47.57#ibcon#*after write, iclass 15, count 0 2006.257.02:59:47.57#ibcon#*before return 0, iclass 15, count 0 2006.257.02:59:47.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:47.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:47.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:59:47.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:59:47.57$vck44/va=3,8 2006.257.02:59:47.57#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.02:59:47.57#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.02:59:47.57#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:47.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:47.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:47.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:47.63#ibcon#enter wrdev, iclass 17, count 2 2006.257.02:59:47.63#ibcon#first serial, iclass 17, count 2 2006.257.02:59:47.63#ibcon#enter sib2, iclass 17, count 2 2006.257.02:59:47.63#ibcon#flushed, iclass 17, count 2 2006.257.02:59:47.63#ibcon#about to write, iclass 17, count 2 2006.257.02:59:47.63#ibcon#wrote, iclass 17, count 2 2006.257.02:59:47.63#ibcon#about to read 3, iclass 17, count 2 2006.257.02:59:47.65#ibcon#read 3, iclass 17, count 2 2006.257.02:59:47.65#ibcon#about to read 4, iclass 17, count 2 2006.257.02:59:47.65#ibcon#read 4, iclass 17, count 2 2006.257.02:59:47.65#ibcon#about to read 5, iclass 17, count 2 2006.257.02:59:47.65#ibcon#read 5, iclass 17, count 2 2006.257.02:59:47.65#ibcon#about to read 6, iclass 17, count 2 2006.257.02:59:47.65#ibcon#read 6, iclass 17, count 2 2006.257.02:59:47.65#ibcon#end of sib2, iclass 17, count 2 2006.257.02:59:47.65#ibcon#*mode == 0, iclass 17, count 2 2006.257.02:59:47.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.02:59:47.65#ibcon#[25=AT03-08\r\n] 2006.257.02:59:47.65#ibcon#*before write, iclass 17, count 2 2006.257.02:59:47.65#ibcon#enter sib2, iclass 17, count 2 2006.257.02:59:47.65#ibcon#flushed, iclass 17, count 2 2006.257.02:59:47.65#ibcon#about to write, iclass 17, count 2 2006.257.02:59:47.65#ibcon#wrote, iclass 17, count 2 2006.257.02:59:47.65#ibcon#about to read 3, iclass 17, count 2 2006.257.02:59:47.68#ibcon#read 3, iclass 17, count 2 2006.257.02:59:47.68#ibcon#about to read 4, iclass 17, count 2 2006.257.02:59:47.68#ibcon#read 4, iclass 17, count 2 2006.257.02:59:47.68#ibcon#about to read 5, iclass 17, count 2 2006.257.02:59:47.68#ibcon#read 5, iclass 17, count 2 2006.257.02:59:47.68#ibcon#about to read 6, iclass 17, count 2 2006.257.02:59:47.68#ibcon#read 6, iclass 17, count 2 2006.257.02:59:47.68#ibcon#end of sib2, iclass 17, count 2 2006.257.02:59:47.68#ibcon#*after write, iclass 17, count 2 2006.257.02:59:47.68#ibcon#*before return 0, iclass 17, count 2 2006.257.02:59:47.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:47.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:47.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.02:59:47.68#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:47.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:47.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:47.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:47.80#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:59:47.80#ibcon#first serial, iclass 17, count 0 2006.257.02:59:47.80#ibcon#enter sib2, iclass 17, count 0 2006.257.02:59:47.80#ibcon#flushed, iclass 17, count 0 2006.257.02:59:47.80#ibcon#about to write, iclass 17, count 0 2006.257.02:59:47.80#ibcon#wrote, iclass 17, count 0 2006.257.02:59:47.80#ibcon#about to read 3, iclass 17, count 0 2006.257.02:59:47.82#ibcon#read 3, iclass 17, count 0 2006.257.02:59:47.82#ibcon#about to read 4, iclass 17, count 0 2006.257.02:59:47.82#ibcon#read 4, iclass 17, count 0 2006.257.02:59:47.82#ibcon#about to read 5, iclass 17, count 0 2006.257.02:59:47.82#ibcon#read 5, iclass 17, count 0 2006.257.02:59:47.82#ibcon#about to read 6, iclass 17, count 0 2006.257.02:59:47.82#ibcon#read 6, iclass 17, count 0 2006.257.02:59:47.82#ibcon#end of sib2, iclass 17, count 0 2006.257.02:59:47.82#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:59:47.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:59:47.82#ibcon#[25=USB\r\n] 2006.257.02:59:47.82#ibcon#*before write, iclass 17, count 0 2006.257.02:59:47.82#ibcon#enter sib2, iclass 17, count 0 2006.257.02:59:47.82#ibcon#flushed, iclass 17, count 0 2006.257.02:59:47.82#ibcon#about to write, iclass 17, count 0 2006.257.02:59:47.82#ibcon#wrote, iclass 17, count 0 2006.257.02:59:47.82#ibcon#about to read 3, iclass 17, count 0 2006.257.02:59:47.85#ibcon#read 3, iclass 17, count 0 2006.257.02:59:47.85#ibcon#about to read 4, iclass 17, count 0 2006.257.02:59:47.85#ibcon#read 4, iclass 17, count 0 2006.257.02:59:47.85#ibcon#about to read 5, iclass 17, count 0 2006.257.02:59:47.85#ibcon#read 5, iclass 17, count 0 2006.257.02:59:47.85#ibcon#about to read 6, iclass 17, count 0 2006.257.02:59:47.85#ibcon#read 6, iclass 17, count 0 2006.257.02:59:47.85#ibcon#end of sib2, iclass 17, count 0 2006.257.02:59:47.85#ibcon#*after write, iclass 17, count 0 2006.257.02:59:47.85#ibcon#*before return 0, iclass 17, count 0 2006.257.02:59:47.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:47.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:47.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:59:47.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:59:47.85$vck44/valo=4,624.99 2006.257.02:59:47.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.02:59:47.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.02:59:47.85#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:47.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:47.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:47.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:47.85#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:59:47.85#ibcon#first serial, iclass 19, count 0 2006.257.02:59:47.85#ibcon#enter sib2, iclass 19, count 0 2006.257.02:59:47.85#ibcon#flushed, iclass 19, count 0 2006.257.02:59:47.85#ibcon#about to write, iclass 19, count 0 2006.257.02:59:47.85#ibcon#wrote, iclass 19, count 0 2006.257.02:59:47.85#ibcon#about to read 3, iclass 19, count 0 2006.257.02:59:47.87#ibcon#read 3, iclass 19, count 0 2006.257.02:59:47.87#ibcon#about to read 4, iclass 19, count 0 2006.257.02:59:47.87#ibcon#read 4, iclass 19, count 0 2006.257.02:59:47.87#ibcon#about to read 5, iclass 19, count 0 2006.257.02:59:47.87#ibcon#read 5, iclass 19, count 0 2006.257.02:59:47.87#ibcon#about to read 6, iclass 19, count 0 2006.257.02:59:47.87#ibcon#read 6, iclass 19, count 0 2006.257.02:59:47.87#ibcon#end of sib2, iclass 19, count 0 2006.257.02:59:47.87#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:59:47.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:59:47.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.02:59:47.87#ibcon#*before write, iclass 19, count 0 2006.257.02:59:47.87#ibcon#enter sib2, iclass 19, count 0 2006.257.02:59:47.87#ibcon#flushed, iclass 19, count 0 2006.257.02:59:47.87#ibcon#about to write, iclass 19, count 0 2006.257.02:59:47.87#ibcon#wrote, iclass 19, count 0 2006.257.02:59:47.87#ibcon#about to read 3, iclass 19, count 0 2006.257.02:59:47.91#ibcon#read 3, iclass 19, count 0 2006.257.02:59:47.91#ibcon#about to read 4, iclass 19, count 0 2006.257.02:59:47.91#ibcon#read 4, iclass 19, count 0 2006.257.02:59:47.91#ibcon#about to read 5, iclass 19, count 0 2006.257.02:59:47.91#ibcon#read 5, iclass 19, count 0 2006.257.02:59:47.91#ibcon#about to read 6, iclass 19, count 0 2006.257.02:59:47.91#ibcon#read 6, iclass 19, count 0 2006.257.02:59:47.91#ibcon#end of sib2, iclass 19, count 0 2006.257.02:59:47.91#ibcon#*after write, iclass 19, count 0 2006.257.02:59:47.91#ibcon#*before return 0, iclass 19, count 0 2006.257.02:59:47.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:47.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:47.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:59:47.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:59:47.91$vck44/va=4,7 2006.257.02:59:47.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.02:59:47.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.02:59:47.91#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:47.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:47.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:47.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:47.97#ibcon#enter wrdev, iclass 21, count 2 2006.257.02:59:47.97#ibcon#first serial, iclass 21, count 2 2006.257.02:59:47.97#ibcon#enter sib2, iclass 21, count 2 2006.257.02:59:47.97#ibcon#flushed, iclass 21, count 2 2006.257.02:59:47.97#ibcon#about to write, iclass 21, count 2 2006.257.02:59:47.97#ibcon#wrote, iclass 21, count 2 2006.257.02:59:47.97#ibcon#about to read 3, iclass 21, count 2 2006.257.02:59:47.99#ibcon#read 3, iclass 21, count 2 2006.257.02:59:47.99#ibcon#about to read 4, iclass 21, count 2 2006.257.02:59:47.99#ibcon#read 4, iclass 21, count 2 2006.257.02:59:47.99#ibcon#about to read 5, iclass 21, count 2 2006.257.02:59:47.99#ibcon#read 5, iclass 21, count 2 2006.257.02:59:47.99#ibcon#about to read 6, iclass 21, count 2 2006.257.02:59:47.99#ibcon#read 6, iclass 21, count 2 2006.257.02:59:47.99#ibcon#end of sib2, iclass 21, count 2 2006.257.02:59:47.99#ibcon#*mode == 0, iclass 21, count 2 2006.257.02:59:47.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.02:59:47.99#ibcon#[25=AT04-07\r\n] 2006.257.02:59:47.99#ibcon#*before write, iclass 21, count 2 2006.257.02:59:47.99#ibcon#enter sib2, iclass 21, count 2 2006.257.02:59:47.99#ibcon#flushed, iclass 21, count 2 2006.257.02:59:47.99#ibcon#about to write, iclass 21, count 2 2006.257.02:59:47.99#ibcon#wrote, iclass 21, count 2 2006.257.02:59:47.99#ibcon#about to read 3, iclass 21, count 2 2006.257.02:59:48.02#ibcon#read 3, iclass 21, count 2 2006.257.02:59:48.02#ibcon#about to read 4, iclass 21, count 2 2006.257.02:59:48.02#ibcon#read 4, iclass 21, count 2 2006.257.02:59:48.02#ibcon#about to read 5, iclass 21, count 2 2006.257.02:59:48.02#ibcon#read 5, iclass 21, count 2 2006.257.02:59:48.02#ibcon#about to read 6, iclass 21, count 2 2006.257.02:59:48.02#ibcon#read 6, iclass 21, count 2 2006.257.02:59:48.02#ibcon#end of sib2, iclass 21, count 2 2006.257.02:59:48.02#ibcon#*after write, iclass 21, count 2 2006.257.02:59:48.02#ibcon#*before return 0, iclass 21, count 2 2006.257.02:59:48.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:48.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:48.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.02:59:48.02#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:48.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:48.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:48.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:48.14#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:59:48.14#ibcon#first serial, iclass 21, count 0 2006.257.02:59:48.14#ibcon#enter sib2, iclass 21, count 0 2006.257.02:59:48.14#ibcon#flushed, iclass 21, count 0 2006.257.02:59:48.14#ibcon#about to write, iclass 21, count 0 2006.257.02:59:48.14#ibcon#wrote, iclass 21, count 0 2006.257.02:59:48.14#ibcon#about to read 3, iclass 21, count 0 2006.257.02:59:48.16#ibcon#read 3, iclass 21, count 0 2006.257.02:59:48.16#ibcon#about to read 4, iclass 21, count 0 2006.257.02:59:48.16#ibcon#read 4, iclass 21, count 0 2006.257.02:59:48.16#ibcon#about to read 5, iclass 21, count 0 2006.257.02:59:48.16#ibcon#read 5, iclass 21, count 0 2006.257.02:59:48.16#ibcon#about to read 6, iclass 21, count 0 2006.257.02:59:48.16#ibcon#read 6, iclass 21, count 0 2006.257.02:59:48.16#ibcon#end of sib2, iclass 21, count 0 2006.257.02:59:48.16#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:59:48.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:59:48.16#ibcon#[25=USB\r\n] 2006.257.02:59:48.16#ibcon#*before write, iclass 21, count 0 2006.257.02:59:48.16#ibcon#enter sib2, iclass 21, count 0 2006.257.02:59:48.16#ibcon#flushed, iclass 21, count 0 2006.257.02:59:48.16#ibcon#about to write, iclass 21, count 0 2006.257.02:59:48.16#ibcon#wrote, iclass 21, count 0 2006.257.02:59:48.16#ibcon#about to read 3, iclass 21, count 0 2006.257.02:59:48.19#ibcon#read 3, iclass 21, count 0 2006.257.02:59:48.19#ibcon#about to read 4, iclass 21, count 0 2006.257.02:59:48.19#ibcon#read 4, iclass 21, count 0 2006.257.02:59:48.19#ibcon#about to read 5, iclass 21, count 0 2006.257.02:59:48.19#ibcon#read 5, iclass 21, count 0 2006.257.02:59:48.19#ibcon#about to read 6, iclass 21, count 0 2006.257.02:59:48.19#ibcon#read 6, iclass 21, count 0 2006.257.02:59:48.19#ibcon#end of sib2, iclass 21, count 0 2006.257.02:59:48.19#ibcon#*after write, iclass 21, count 0 2006.257.02:59:48.19#ibcon#*before return 0, iclass 21, count 0 2006.257.02:59:48.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:48.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:48.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:59:48.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:59:48.19$vck44/valo=5,734.99 2006.257.02:59:48.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.02:59:48.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.02:59:48.19#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:48.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:48.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:48.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:48.19#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:59:48.19#ibcon#first serial, iclass 23, count 0 2006.257.02:59:48.19#ibcon#enter sib2, iclass 23, count 0 2006.257.02:59:48.19#ibcon#flushed, iclass 23, count 0 2006.257.02:59:48.19#ibcon#about to write, iclass 23, count 0 2006.257.02:59:48.19#ibcon#wrote, iclass 23, count 0 2006.257.02:59:48.19#ibcon#about to read 3, iclass 23, count 0 2006.257.02:59:48.21#ibcon#read 3, iclass 23, count 0 2006.257.02:59:48.21#ibcon#about to read 4, iclass 23, count 0 2006.257.02:59:48.21#ibcon#read 4, iclass 23, count 0 2006.257.02:59:48.21#ibcon#about to read 5, iclass 23, count 0 2006.257.02:59:48.21#ibcon#read 5, iclass 23, count 0 2006.257.02:59:48.21#ibcon#about to read 6, iclass 23, count 0 2006.257.02:59:48.21#ibcon#read 6, iclass 23, count 0 2006.257.02:59:48.21#ibcon#end of sib2, iclass 23, count 0 2006.257.02:59:48.21#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:59:48.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:59:48.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.02:59:48.21#ibcon#*before write, iclass 23, count 0 2006.257.02:59:48.21#ibcon#enter sib2, iclass 23, count 0 2006.257.02:59:48.21#ibcon#flushed, iclass 23, count 0 2006.257.02:59:48.21#ibcon#about to write, iclass 23, count 0 2006.257.02:59:48.21#ibcon#wrote, iclass 23, count 0 2006.257.02:59:48.21#ibcon#about to read 3, iclass 23, count 0 2006.257.02:59:48.25#ibcon#read 3, iclass 23, count 0 2006.257.02:59:48.25#ibcon#about to read 4, iclass 23, count 0 2006.257.02:59:48.25#ibcon#read 4, iclass 23, count 0 2006.257.02:59:48.25#ibcon#about to read 5, iclass 23, count 0 2006.257.02:59:48.25#ibcon#read 5, iclass 23, count 0 2006.257.02:59:48.25#ibcon#about to read 6, iclass 23, count 0 2006.257.02:59:48.25#ibcon#read 6, iclass 23, count 0 2006.257.02:59:48.25#ibcon#end of sib2, iclass 23, count 0 2006.257.02:59:48.25#ibcon#*after write, iclass 23, count 0 2006.257.02:59:48.25#ibcon#*before return 0, iclass 23, count 0 2006.257.02:59:48.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:48.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:48.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:59:48.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:59:48.25$vck44/va=5,4 2006.257.02:59:48.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.02:59:48.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.02:59:48.25#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:48.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:48.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:48.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:48.31#ibcon#enter wrdev, iclass 25, count 2 2006.257.02:59:48.31#ibcon#first serial, iclass 25, count 2 2006.257.02:59:48.31#ibcon#enter sib2, iclass 25, count 2 2006.257.02:59:48.31#ibcon#flushed, iclass 25, count 2 2006.257.02:59:48.31#ibcon#about to write, iclass 25, count 2 2006.257.02:59:48.31#ibcon#wrote, iclass 25, count 2 2006.257.02:59:48.31#ibcon#about to read 3, iclass 25, count 2 2006.257.02:59:48.33#ibcon#read 3, iclass 25, count 2 2006.257.02:59:48.33#ibcon#about to read 4, iclass 25, count 2 2006.257.02:59:48.33#ibcon#read 4, iclass 25, count 2 2006.257.02:59:48.33#ibcon#about to read 5, iclass 25, count 2 2006.257.02:59:48.33#ibcon#read 5, iclass 25, count 2 2006.257.02:59:48.33#ibcon#about to read 6, iclass 25, count 2 2006.257.02:59:48.33#ibcon#read 6, iclass 25, count 2 2006.257.02:59:48.33#ibcon#end of sib2, iclass 25, count 2 2006.257.02:59:48.33#ibcon#*mode == 0, iclass 25, count 2 2006.257.02:59:48.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.02:59:48.33#ibcon#[25=AT05-04\r\n] 2006.257.02:59:48.33#ibcon#*before write, iclass 25, count 2 2006.257.02:59:48.33#ibcon#enter sib2, iclass 25, count 2 2006.257.02:59:48.33#ibcon#flushed, iclass 25, count 2 2006.257.02:59:48.33#ibcon#about to write, iclass 25, count 2 2006.257.02:59:48.33#ibcon#wrote, iclass 25, count 2 2006.257.02:59:48.33#ibcon#about to read 3, iclass 25, count 2 2006.257.02:59:48.36#ibcon#read 3, iclass 25, count 2 2006.257.02:59:48.36#ibcon#about to read 4, iclass 25, count 2 2006.257.02:59:48.36#ibcon#read 4, iclass 25, count 2 2006.257.02:59:48.36#ibcon#about to read 5, iclass 25, count 2 2006.257.02:59:48.36#ibcon#read 5, iclass 25, count 2 2006.257.02:59:48.36#ibcon#about to read 6, iclass 25, count 2 2006.257.02:59:48.36#ibcon#read 6, iclass 25, count 2 2006.257.02:59:48.36#ibcon#end of sib2, iclass 25, count 2 2006.257.02:59:48.36#ibcon#*after write, iclass 25, count 2 2006.257.02:59:48.36#ibcon#*before return 0, iclass 25, count 2 2006.257.02:59:48.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:48.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:48.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.02:59:48.36#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:48.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:48.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:48.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:48.48#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:59:48.48#ibcon#first serial, iclass 25, count 0 2006.257.02:59:48.48#ibcon#enter sib2, iclass 25, count 0 2006.257.02:59:48.48#ibcon#flushed, iclass 25, count 0 2006.257.02:59:48.48#ibcon#about to write, iclass 25, count 0 2006.257.02:59:48.48#ibcon#wrote, iclass 25, count 0 2006.257.02:59:48.48#ibcon#about to read 3, iclass 25, count 0 2006.257.02:59:48.50#ibcon#read 3, iclass 25, count 0 2006.257.02:59:48.50#ibcon#about to read 4, iclass 25, count 0 2006.257.02:59:48.50#ibcon#read 4, iclass 25, count 0 2006.257.02:59:48.50#ibcon#about to read 5, iclass 25, count 0 2006.257.02:59:48.50#ibcon#read 5, iclass 25, count 0 2006.257.02:59:48.50#ibcon#about to read 6, iclass 25, count 0 2006.257.02:59:48.50#ibcon#read 6, iclass 25, count 0 2006.257.02:59:48.50#ibcon#end of sib2, iclass 25, count 0 2006.257.02:59:48.50#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:59:48.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:59:48.50#ibcon#[25=USB\r\n] 2006.257.02:59:48.50#ibcon#*before write, iclass 25, count 0 2006.257.02:59:48.50#ibcon#enter sib2, iclass 25, count 0 2006.257.02:59:48.50#ibcon#flushed, iclass 25, count 0 2006.257.02:59:48.50#ibcon#about to write, iclass 25, count 0 2006.257.02:59:48.50#ibcon#wrote, iclass 25, count 0 2006.257.02:59:48.50#ibcon#about to read 3, iclass 25, count 0 2006.257.02:59:48.53#ibcon#read 3, iclass 25, count 0 2006.257.02:59:48.53#ibcon#about to read 4, iclass 25, count 0 2006.257.02:59:48.53#ibcon#read 4, iclass 25, count 0 2006.257.02:59:48.53#ibcon#about to read 5, iclass 25, count 0 2006.257.02:59:48.53#ibcon#read 5, iclass 25, count 0 2006.257.02:59:48.53#ibcon#about to read 6, iclass 25, count 0 2006.257.02:59:48.53#ibcon#read 6, iclass 25, count 0 2006.257.02:59:48.53#ibcon#end of sib2, iclass 25, count 0 2006.257.02:59:48.53#ibcon#*after write, iclass 25, count 0 2006.257.02:59:48.53#ibcon#*before return 0, iclass 25, count 0 2006.257.02:59:48.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:48.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:48.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:59:48.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:59:48.53$vck44/valo=6,814.99 2006.257.02:59:48.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.02:59:48.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.02:59:48.53#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:48.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:48.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:48.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:48.53#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:59:48.53#ibcon#first serial, iclass 27, count 0 2006.257.02:59:48.53#ibcon#enter sib2, iclass 27, count 0 2006.257.02:59:48.53#ibcon#flushed, iclass 27, count 0 2006.257.02:59:48.53#ibcon#about to write, iclass 27, count 0 2006.257.02:59:48.53#ibcon#wrote, iclass 27, count 0 2006.257.02:59:48.53#ibcon#about to read 3, iclass 27, count 0 2006.257.02:59:48.55#ibcon#read 3, iclass 27, count 0 2006.257.02:59:48.55#ibcon#about to read 4, iclass 27, count 0 2006.257.02:59:48.55#ibcon#read 4, iclass 27, count 0 2006.257.02:59:48.55#ibcon#about to read 5, iclass 27, count 0 2006.257.02:59:48.55#ibcon#read 5, iclass 27, count 0 2006.257.02:59:48.55#ibcon#about to read 6, iclass 27, count 0 2006.257.02:59:48.55#ibcon#read 6, iclass 27, count 0 2006.257.02:59:48.55#ibcon#end of sib2, iclass 27, count 0 2006.257.02:59:48.55#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:59:48.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:59:48.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.02:59:48.55#ibcon#*before write, iclass 27, count 0 2006.257.02:59:48.55#ibcon#enter sib2, iclass 27, count 0 2006.257.02:59:48.55#ibcon#flushed, iclass 27, count 0 2006.257.02:59:48.55#ibcon#about to write, iclass 27, count 0 2006.257.02:59:48.55#ibcon#wrote, iclass 27, count 0 2006.257.02:59:48.55#ibcon#about to read 3, iclass 27, count 0 2006.257.02:59:48.59#ibcon#read 3, iclass 27, count 0 2006.257.02:59:48.59#ibcon#about to read 4, iclass 27, count 0 2006.257.02:59:48.59#ibcon#read 4, iclass 27, count 0 2006.257.02:59:48.59#ibcon#about to read 5, iclass 27, count 0 2006.257.02:59:48.59#ibcon#read 5, iclass 27, count 0 2006.257.02:59:48.59#ibcon#about to read 6, iclass 27, count 0 2006.257.02:59:48.59#ibcon#read 6, iclass 27, count 0 2006.257.02:59:48.59#ibcon#end of sib2, iclass 27, count 0 2006.257.02:59:48.59#ibcon#*after write, iclass 27, count 0 2006.257.02:59:48.59#ibcon#*before return 0, iclass 27, count 0 2006.257.02:59:48.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:48.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:48.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:59:48.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:59:48.59$vck44/va=6,4 2006.257.02:59:48.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.02:59:48.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.02:59:48.59#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:48.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:48.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:48.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:48.65#ibcon#enter wrdev, iclass 29, count 2 2006.257.02:59:48.65#ibcon#first serial, iclass 29, count 2 2006.257.02:59:48.65#ibcon#enter sib2, iclass 29, count 2 2006.257.02:59:48.65#ibcon#flushed, iclass 29, count 2 2006.257.02:59:48.65#ibcon#about to write, iclass 29, count 2 2006.257.02:59:48.65#ibcon#wrote, iclass 29, count 2 2006.257.02:59:48.65#ibcon#about to read 3, iclass 29, count 2 2006.257.02:59:48.67#ibcon#read 3, iclass 29, count 2 2006.257.02:59:48.67#ibcon#about to read 4, iclass 29, count 2 2006.257.02:59:48.67#ibcon#read 4, iclass 29, count 2 2006.257.02:59:48.67#ibcon#about to read 5, iclass 29, count 2 2006.257.02:59:48.67#ibcon#read 5, iclass 29, count 2 2006.257.02:59:48.67#ibcon#about to read 6, iclass 29, count 2 2006.257.02:59:48.67#ibcon#read 6, iclass 29, count 2 2006.257.02:59:48.67#ibcon#end of sib2, iclass 29, count 2 2006.257.02:59:48.67#ibcon#*mode == 0, iclass 29, count 2 2006.257.02:59:48.67#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.02:59:48.67#ibcon#[25=AT06-04\r\n] 2006.257.02:59:48.67#ibcon#*before write, iclass 29, count 2 2006.257.02:59:48.67#ibcon#enter sib2, iclass 29, count 2 2006.257.02:59:48.67#ibcon#flushed, iclass 29, count 2 2006.257.02:59:48.67#ibcon#about to write, iclass 29, count 2 2006.257.02:59:48.67#ibcon#wrote, iclass 29, count 2 2006.257.02:59:48.67#ibcon#about to read 3, iclass 29, count 2 2006.257.02:59:48.70#ibcon#read 3, iclass 29, count 2 2006.257.02:59:48.70#ibcon#about to read 4, iclass 29, count 2 2006.257.02:59:48.70#ibcon#read 4, iclass 29, count 2 2006.257.02:59:48.70#ibcon#about to read 5, iclass 29, count 2 2006.257.02:59:48.70#ibcon#read 5, iclass 29, count 2 2006.257.02:59:48.70#ibcon#about to read 6, iclass 29, count 2 2006.257.02:59:48.70#ibcon#read 6, iclass 29, count 2 2006.257.02:59:48.70#ibcon#end of sib2, iclass 29, count 2 2006.257.02:59:48.70#ibcon#*after write, iclass 29, count 2 2006.257.02:59:48.70#ibcon#*before return 0, iclass 29, count 2 2006.257.02:59:48.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:48.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:48.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.02:59:48.70#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:48.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:48.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:48.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:48.82#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:59:48.82#ibcon#first serial, iclass 29, count 0 2006.257.02:59:48.82#ibcon#enter sib2, iclass 29, count 0 2006.257.02:59:48.82#ibcon#flushed, iclass 29, count 0 2006.257.02:59:48.82#ibcon#about to write, iclass 29, count 0 2006.257.02:59:48.82#ibcon#wrote, iclass 29, count 0 2006.257.02:59:48.82#ibcon#about to read 3, iclass 29, count 0 2006.257.02:59:48.84#ibcon#read 3, iclass 29, count 0 2006.257.02:59:48.84#ibcon#about to read 4, iclass 29, count 0 2006.257.02:59:48.84#ibcon#read 4, iclass 29, count 0 2006.257.02:59:48.84#ibcon#about to read 5, iclass 29, count 0 2006.257.02:59:48.84#ibcon#read 5, iclass 29, count 0 2006.257.02:59:48.84#ibcon#about to read 6, iclass 29, count 0 2006.257.02:59:48.84#ibcon#read 6, iclass 29, count 0 2006.257.02:59:48.84#ibcon#end of sib2, iclass 29, count 0 2006.257.02:59:48.84#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:59:48.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:59:48.84#ibcon#[25=USB\r\n] 2006.257.02:59:48.84#ibcon#*before write, iclass 29, count 0 2006.257.02:59:48.84#ibcon#enter sib2, iclass 29, count 0 2006.257.02:59:48.84#ibcon#flushed, iclass 29, count 0 2006.257.02:59:48.84#ibcon#about to write, iclass 29, count 0 2006.257.02:59:48.84#ibcon#wrote, iclass 29, count 0 2006.257.02:59:48.84#ibcon#about to read 3, iclass 29, count 0 2006.257.02:59:48.87#ibcon#read 3, iclass 29, count 0 2006.257.02:59:48.87#ibcon#about to read 4, iclass 29, count 0 2006.257.02:59:48.87#ibcon#read 4, iclass 29, count 0 2006.257.02:59:48.87#ibcon#about to read 5, iclass 29, count 0 2006.257.02:59:48.87#ibcon#read 5, iclass 29, count 0 2006.257.02:59:48.87#ibcon#about to read 6, iclass 29, count 0 2006.257.02:59:48.87#ibcon#read 6, iclass 29, count 0 2006.257.02:59:48.87#ibcon#end of sib2, iclass 29, count 0 2006.257.02:59:48.87#ibcon#*after write, iclass 29, count 0 2006.257.02:59:48.87#ibcon#*before return 0, iclass 29, count 0 2006.257.02:59:48.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:48.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:48.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:59:48.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:59:48.87$vck44/valo=7,864.99 2006.257.02:59:48.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.02:59:48.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.02:59:48.87#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:48.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:48.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:48.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:48.87#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:59:48.87#ibcon#first serial, iclass 31, count 0 2006.257.02:59:48.87#ibcon#enter sib2, iclass 31, count 0 2006.257.02:59:48.87#ibcon#flushed, iclass 31, count 0 2006.257.02:59:48.87#ibcon#about to write, iclass 31, count 0 2006.257.02:59:48.87#ibcon#wrote, iclass 31, count 0 2006.257.02:59:48.87#ibcon#about to read 3, iclass 31, count 0 2006.257.02:59:48.89#ibcon#read 3, iclass 31, count 0 2006.257.02:59:48.89#ibcon#about to read 4, iclass 31, count 0 2006.257.02:59:48.89#ibcon#read 4, iclass 31, count 0 2006.257.02:59:48.89#ibcon#about to read 5, iclass 31, count 0 2006.257.02:59:48.89#ibcon#read 5, iclass 31, count 0 2006.257.02:59:48.89#ibcon#about to read 6, iclass 31, count 0 2006.257.02:59:48.89#ibcon#read 6, iclass 31, count 0 2006.257.02:59:48.89#ibcon#end of sib2, iclass 31, count 0 2006.257.02:59:48.89#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:59:48.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:59:48.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.02:59:48.89#ibcon#*before write, iclass 31, count 0 2006.257.02:59:48.89#ibcon#enter sib2, iclass 31, count 0 2006.257.02:59:48.89#ibcon#flushed, iclass 31, count 0 2006.257.02:59:48.89#ibcon#about to write, iclass 31, count 0 2006.257.02:59:48.89#ibcon#wrote, iclass 31, count 0 2006.257.02:59:48.89#ibcon#about to read 3, iclass 31, count 0 2006.257.02:59:48.93#ibcon#read 3, iclass 31, count 0 2006.257.02:59:48.93#ibcon#about to read 4, iclass 31, count 0 2006.257.02:59:48.93#ibcon#read 4, iclass 31, count 0 2006.257.02:59:48.93#ibcon#about to read 5, iclass 31, count 0 2006.257.02:59:48.93#ibcon#read 5, iclass 31, count 0 2006.257.02:59:48.93#ibcon#about to read 6, iclass 31, count 0 2006.257.02:59:48.93#ibcon#read 6, iclass 31, count 0 2006.257.02:59:48.93#ibcon#end of sib2, iclass 31, count 0 2006.257.02:59:48.93#ibcon#*after write, iclass 31, count 0 2006.257.02:59:48.93#ibcon#*before return 0, iclass 31, count 0 2006.257.02:59:48.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:48.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:48.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:59:48.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:59:48.93$vck44/va=7,4 2006.257.02:59:48.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.02:59:48.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.02:59:48.93#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:48.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:48.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:48.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:48.99#ibcon#enter wrdev, iclass 33, count 2 2006.257.02:59:48.99#ibcon#first serial, iclass 33, count 2 2006.257.02:59:48.99#ibcon#enter sib2, iclass 33, count 2 2006.257.02:59:48.99#ibcon#flushed, iclass 33, count 2 2006.257.02:59:48.99#ibcon#about to write, iclass 33, count 2 2006.257.02:59:48.99#ibcon#wrote, iclass 33, count 2 2006.257.02:59:48.99#ibcon#about to read 3, iclass 33, count 2 2006.257.02:59:49.01#ibcon#read 3, iclass 33, count 2 2006.257.02:59:49.01#ibcon#about to read 4, iclass 33, count 2 2006.257.02:59:49.01#ibcon#read 4, iclass 33, count 2 2006.257.02:59:49.01#ibcon#about to read 5, iclass 33, count 2 2006.257.02:59:49.01#ibcon#read 5, iclass 33, count 2 2006.257.02:59:49.01#ibcon#about to read 6, iclass 33, count 2 2006.257.02:59:49.01#ibcon#read 6, iclass 33, count 2 2006.257.02:59:49.01#ibcon#end of sib2, iclass 33, count 2 2006.257.02:59:49.01#ibcon#*mode == 0, iclass 33, count 2 2006.257.02:59:49.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.02:59:49.01#ibcon#[25=AT07-04\r\n] 2006.257.02:59:49.01#ibcon#*before write, iclass 33, count 2 2006.257.02:59:49.01#ibcon#enter sib2, iclass 33, count 2 2006.257.02:59:49.01#ibcon#flushed, iclass 33, count 2 2006.257.02:59:49.01#ibcon#about to write, iclass 33, count 2 2006.257.02:59:49.01#ibcon#wrote, iclass 33, count 2 2006.257.02:59:49.01#ibcon#about to read 3, iclass 33, count 2 2006.257.02:59:49.04#ibcon#read 3, iclass 33, count 2 2006.257.02:59:49.04#ibcon#about to read 4, iclass 33, count 2 2006.257.02:59:49.04#ibcon#read 4, iclass 33, count 2 2006.257.02:59:49.04#ibcon#about to read 5, iclass 33, count 2 2006.257.02:59:49.04#ibcon#read 5, iclass 33, count 2 2006.257.02:59:49.04#ibcon#about to read 6, iclass 33, count 2 2006.257.02:59:49.04#ibcon#read 6, iclass 33, count 2 2006.257.02:59:49.04#ibcon#end of sib2, iclass 33, count 2 2006.257.02:59:49.04#ibcon#*after write, iclass 33, count 2 2006.257.02:59:49.04#ibcon#*before return 0, iclass 33, count 2 2006.257.02:59:49.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:49.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:49.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.02:59:49.04#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:49.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:49.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:49.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:49.16#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:59:49.16#ibcon#first serial, iclass 33, count 0 2006.257.02:59:49.16#ibcon#enter sib2, iclass 33, count 0 2006.257.02:59:49.16#ibcon#flushed, iclass 33, count 0 2006.257.02:59:49.16#ibcon#about to write, iclass 33, count 0 2006.257.02:59:49.16#ibcon#wrote, iclass 33, count 0 2006.257.02:59:49.16#ibcon#about to read 3, iclass 33, count 0 2006.257.02:59:49.18#ibcon#read 3, iclass 33, count 0 2006.257.02:59:49.18#ibcon#about to read 4, iclass 33, count 0 2006.257.02:59:49.18#ibcon#read 4, iclass 33, count 0 2006.257.02:59:49.18#ibcon#about to read 5, iclass 33, count 0 2006.257.02:59:49.18#ibcon#read 5, iclass 33, count 0 2006.257.02:59:49.18#ibcon#about to read 6, iclass 33, count 0 2006.257.02:59:49.18#ibcon#read 6, iclass 33, count 0 2006.257.02:59:49.18#ibcon#end of sib2, iclass 33, count 0 2006.257.02:59:49.18#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:59:49.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:59:49.18#ibcon#[25=USB\r\n] 2006.257.02:59:49.18#ibcon#*before write, iclass 33, count 0 2006.257.02:59:49.18#ibcon#enter sib2, iclass 33, count 0 2006.257.02:59:49.18#ibcon#flushed, iclass 33, count 0 2006.257.02:59:49.18#ibcon#about to write, iclass 33, count 0 2006.257.02:59:49.18#ibcon#wrote, iclass 33, count 0 2006.257.02:59:49.18#ibcon#about to read 3, iclass 33, count 0 2006.257.02:59:49.21#ibcon#read 3, iclass 33, count 0 2006.257.02:59:49.21#ibcon#about to read 4, iclass 33, count 0 2006.257.02:59:49.21#ibcon#read 4, iclass 33, count 0 2006.257.02:59:49.21#ibcon#about to read 5, iclass 33, count 0 2006.257.02:59:49.21#ibcon#read 5, iclass 33, count 0 2006.257.02:59:49.21#ibcon#about to read 6, iclass 33, count 0 2006.257.02:59:49.21#ibcon#read 6, iclass 33, count 0 2006.257.02:59:49.21#ibcon#end of sib2, iclass 33, count 0 2006.257.02:59:49.21#ibcon#*after write, iclass 33, count 0 2006.257.02:59:49.21#ibcon#*before return 0, iclass 33, count 0 2006.257.02:59:49.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:49.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:49.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:59:49.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:59:49.21$vck44/valo=8,884.99 2006.257.02:59:49.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.02:59:49.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.02:59:49.21#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:49.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:59:49.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:59:49.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:59:49.21#ibcon#enter wrdev, iclass 35, count 0 2006.257.02:59:49.21#ibcon#first serial, iclass 35, count 0 2006.257.02:59:49.21#ibcon#enter sib2, iclass 35, count 0 2006.257.02:59:49.21#ibcon#flushed, iclass 35, count 0 2006.257.02:59:49.21#ibcon#about to write, iclass 35, count 0 2006.257.02:59:49.21#ibcon#wrote, iclass 35, count 0 2006.257.02:59:49.21#ibcon#about to read 3, iclass 35, count 0 2006.257.02:59:49.23#ibcon#read 3, iclass 35, count 0 2006.257.02:59:49.23#ibcon#about to read 4, iclass 35, count 0 2006.257.02:59:49.23#ibcon#read 4, iclass 35, count 0 2006.257.02:59:49.23#ibcon#about to read 5, iclass 35, count 0 2006.257.02:59:49.23#ibcon#read 5, iclass 35, count 0 2006.257.02:59:49.23#ibcon#about to read 6, iclass 35, count 0 2006.257.02:59:49.23#ibcon#read 6, iclass 35, count 0 2006.257.02:59:49.23#ibcon#end of sib2, iclass 35, count 0 2006.257.02:59:49.23#ibcon#*mode == 0, iclass 35, count 0 2006.257.02:59:49.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.02:59:49.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.02:59:49.23#ibcon#*before write, iclass 35, count 0 2006.257.02:59:49.23#ibcon#enter sib2, iclass 35, count 0 2006.257.02:59:49.23#ibcon#flushed, iclass 35, count 0 2006.257.02:59:49.23#ibcon#about to write, iclass 35, count 0 2006.257.02:59:49.23#ibcon#wrote, iclass 35, count 0 2006.257.02:59:49.23#ibcon#about to read 3, iclass 35, count 0 2006.257.02:59:49.27#ibcon#read 3, iclass 35, count 0 2006.257.02:59:49.27#ibcon#about to read 4, iclass 35, count 0 2006.257.02:59:49.27#ibcon#read 4, iclass 35, count 0 2006.257.02:59:49.27#ibcon#about to read 5, iclass 35, count 0 2006.257.02:59:49.27#ibcon#read 5, iclass 35, count 0 2006.257.02:59:49.27#ibcon#about to read 6, iclass 35, count 0 2006.257.02:59:49.27#ibcon#read 6, iclass 35, count 0 2006.257.02:59:49.27#ibcon#end of sib2, iclass 35, count 0 2006.257.02:59:49.27#ibcon#*after write, iclass 35, count 0 2006.257.02:59:49.27#ibcon#*before return 0, iclass 35, count 0 2006.257.02:59:49.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:59:49.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.02:59:49.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.02:59:49.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.02:59:49.27$vck44/va=8,4 2006.257.02:59:49.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.02:59:49.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.02:59:49.27#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:49.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:59:49.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:59:49.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:59:49.33#ibcon#enter wrdev, iclass 37, count 2 2006.257.02:59:49.33#ibcon#first serial, iclass 37, count 2 2006.257.02:59:49.33#ibcon#enter sib2, iclass 37, count 2 2006.257.02:59:49.33#ibcon#flushed, iclass 37, count 2 2006.257.02:59:49.33#ibcon#about to write, iclass 37, count 2 2006.257.02:59:49.33#ibcon#wrote, iclass 37, count 2 2006.257.02:59:49.33#ibcon#about to read 3, iclass 37, count 2 2006.257.02:59:49.35#ibcon#read 3, iclass 37, count 2 2006.257.02:59:49.35#ibcon#about to read 4, iclass 37, count 2 2006.257.02:59:49.35#ibcon#read 4, iclass 37, count 2 2006.257.02:59:49.35#ibcon#about to read 5, iclass 37, count 2 2006.257.02:59:49.35#ibcon#read 5, iclass 37, count 2 2006.257.02:59:49.35#ibcon#about to read 6, iclass 37, count 2 2006.257.02:59:49.35#ibcon#read 6, iclass 37, count 2 2006.257.02:59:49.35#ibcon#end of sib2, iclass 37, count 2 2006.257.02:59:49.35#ibcon#*mode == 0, iclass 37, count 2 2006.257.02:59:49.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.02:59:49.35#ibcon#[25=AT08-04\r\n] 2006.257.02:59:49.35#ibcon#*before write, iclass 37, count 2 2006.257.02:59:49.35#ibcon#enter sib2, iclass 37, count 2 2006.257.02:59:49.35#ibcon#flushed, iclass 37, count 2 2006.257.02:59:49.35#ibcon#about to write, iclass 37, count 2 2006.257.02:59:49.35#ibcon#wrote, iclass 37, count 2 2006.257.02:59:49.35#ibcon#about to read 3, iclass 37, count 2 2006.257.02:59:49.38#ibcon#read 3, iclass 37, count 2 2006.257.02:59:49.38#ibcon#about to read 4, iclass 37, count 2 2006.257.02:59:49.38#ibcon#read 4, iclass 37, count 2 2006.257.02:59:49.38#ibcon#about to read 5, iclass 37, count 2 2006.257.02:59:49.38#ibcon#read 5, iclass 37, count 2 2006.257.02:59:49.38#ibcon#about to read 6, iclass 37, count 2 2006.257.02:59:49.38#ibcon#read 6, iclass 37, count 2 2006.257.02:59:49.38#ibcon#end of sib2, iclass 37, count 2 2006.257.02:59:49.38#ibcon#*after write, iclass 37, count 2 2006.257.02:59:49.38#ibcon#*before return 0, iclass 37, count 2 2006.257.02:59:49.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:59:49.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.02:59:49.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.02:59:49.38#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:49.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:59:49.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:59:49.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:59:49.50#ibcon#enter wrdev, iclass 37, count 0 2006.257.02:59:49.50#ibcon#first serial, iclass 37, count 0 2006.257.02:59:49.50#ibcon#enter sib2, iclass 37, count 0 2006.257.02:59:49.50#ibcon#flushed, iclass 37, count 0 2006.257.02:59:49.50#ibcon#about to write, iclass 37, count 0 2006.257.02:59:49.50#ibcon#wrote, iclass 37, count 0 2006.257.02:59:49.50#ibcon#about to read 3, iclass 37, count 0 2006.257.02:59:49.52#ibcon#read 3, iclass 37, count 0 2006.257.02:59:49.52#ibcon#about to read 4, iclass 37, count 0 2006.257.02:59:49.52#ibcon#read 4, iclass 37, count 0 2006.257.02:59:49.52#ibcon#about to read 5, iclass 37, count 0 2006.257.02:59:49.52#ibcon#read 5, iclass 37, count 0 2006.257.02:59:49.52#ibcon#about to read 6, iclass 37, count 0 2006.257.02:59:49.52#ibcon#read 6, iclass 37, count 0 2006.257.02:59:49.52#ibcon#end of sib2, iclass 37, count 0 2006.257.02:59:49.52#ibcon#*mode == 0, iclass 37, count 0 2006.257.02:59:49.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.02:59:49.52#ibcon#[25=USB\r\n] 2006.257.02:59:49.52#ibcon#*before write, iclass 37, count 0 2006.257.02:59:49.52#ibcon#enter sib2, iclass 37, count 0 2006.257.02:59:49.52#ibcon#flushed, iclass 37, count 0 2006.257.02:59:49.52#ibcon#about to write, iclass 37, count 0 2006.257.02:59:49.52#ibcon#wrote, iclass 37, count 0 2006.257.02:59:49.52#ibcon#about to read 3, iclass 37, count 0 2006.257.02:59:49.55#ibcon#read 3, iclass 37, count 0 2006.257.02:59:49.55#ibcon#about to read 4, iclass 37, count 0 2006.257.02:59:49.55#ibcon#read 4, iclass 37, count 0 2006.257.02:59:49.55#ibcon#about to read 5, iclass 37, count 0 2006.257.02:59:49.55#ibcon#read 5, iclass 37, count 0 2006.257.02:59:49.55#ibcon#about to read 6, iclass 37, count 0 2006.257.02:59:49.55#ibcon#read 6, iclass 37, count 0 2006.257.02:59:49.55#ibcon#end of sib2, iclass 37, count 0 2006.257.02:59:49.55#ibcon#*after write, iclass 37, count 0 2006.257.02:59:49.55#ibcon#*before return 0, iclass 37, count 0 2006.257.02:59:49.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:59:49.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.02:59:49.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.02:59:49.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.02:59:49.55$vck44/vblo=1,629.99 2006.257.02:59:49.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.02:59:49.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.02:59:49.55#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:49.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:59:49.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:59:49.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:59:49.55#ibcon#enter wrdev, iclass 39, count 0 2006.257.02:59:49.55#ibcon#first serial, iclass 39, count 0 2006.257.02:59:49.55#ibcon#enter sib2, iclass 39, count 0 2006.257.02:59:49.55#ibcon#flushed, iclass 39, count 0 2006.257.02:59:49.55#ibcon#about to write, iclass 39, count 0 2006.257.02:59:49.55#ibcon#wrote, iclass 39, count 0 2006.257.02:59:49.55#ibcon#about to read 3, iclass 39, count 0 2006.257.02:59:49.57#ibcon#read 3, iclass 39, count 0 2006.257.02:59:49.57#ibcon#about to read 4, iclass 39, count 0 2006.257.02:59:49.57#ibcon#read 4, iclass 39, count 0 2006.257.02:59:49.57#ibcon#about to read 5, iclass 39, count 0 2006.257.02:59:49.57#ibcon#read 5, iclass 39, count 0 2006.257.02:59:49.57#ibcon#about to read 6, iclass 39, count 0 2006.257.02:59:49.57#ibcon#read 6, iclass 39, count 0 2006.257.02:59:49.57#ibcon#end of sib2, iclass 39, count 0 2006.257.02:59:49.57#ibcon#*mode == 0, iclass 39, count 0 2006.257.02:59:49.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.02:59:49.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.02:59:49.57#ibcon#*before write, iclass 39, count 0 2006.257.02:59:49.57#ibcon#enter sib2, iclass 39, count 0 2006.257.02:59:49.57#ibcon#flushed, iclass 39, count 0 2006.257.02:59:49.57#ibcon#about to write, iclass 39, count 0 2006.257.02:59:49.57#ibcon#wrote, iclass 39, count 0 2006.257.02:59:49.57#ibcon#about to read 3, iclass 39, count 0 2006.257.02:59:49.61#ibcon#read 3, iclass 39, count 0 2006.257.02:59:49.61#ibcon#about to read 4, iclass 39, count 0 2006.257.02:59:49.61#ibcon#read 4, iclass 39, count 0 2006.257.02:59:49.61#ibcon#about to read 5, iclass 39, count 0 2006.257.02:59:49.61#ibcon#read 5, iclass 39, count 0 2006.257.02:59:49.61#ibcon#about to read 6, iclass 39, count 0 2006.257.02:59:49.61#ibcon#read 6, iclass 39, count 0 2006.257.02:59:49.61#ibcon#end of sib2, iclass 39, count 0 2006.257.02:59:49.61#ibcon#*after write, iclass 39, count 0 2006.257.02:59:49.61#ibcon#*before return 0, iclass 39, count 0 2006.257.02:59:49.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:59:49.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.02:59:49.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.02:59:49.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.02:59:49.61$vck44/vb=1,4 2006.257.02:59:49.61#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.02:59:49.61#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.02:59:49.61#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:49.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:59:49.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:59:49.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:59:49.61#ibcon#enter wrdev, iclass 3, count 2 2006.257.02:59:49.61#ibcon#first serial, iclass 3, count 2 2006.257.02:59:49.61#ibcon#enter sib2, iclass 3, count 2 2006.257.02:59:49.61#ibcon#flushed, iclass 3, count 2 2006.257.02:59:49.61#ibcon#about to write, iclass 3, count 2 2006.257.02:59:49.61#ibcon#wrote, iclass 3, count 2 2006.257.02:59:49.61#ibcon#about to read 3, iclass 3, count 2 2006.257.02:59:49.63#ibcon#read 3, iclass 3, count 2 2006.257.02:59:49.63#ibcon#about to read 4, iclass 3, count 2 2006.257.02:59:49.63#ibcon#read 4, iclass 3, count 2 2006.257.02:59:49.63#ibcon#about to read 5, iclass 3, count 2 2006.257.02:59:49.63#ibcon#read 5, iclass 3, count 2 2006.257.02:59:49.63#ibcon#about to read 6, iclass 3, count 2 2006.257.02:59:49.63#ibcon#read 6, iclass 3, count 2 2006.257.02:59:49.63#ibcon#end of sib2, iclass 3, count 2 2006.257.02:59:49.63#ibcon#*mode == 0, iclass 3, count 2 2006.257.02:59:49.63#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.02:59:49.63#ibcon#[27=AT01-04\r\n] 2006.257.02:59:49.63#ibcon#*before write, iclass 3, count 2 2006.257.02:59:49.63#ibcon#enter sib2, iclass 3, count 2 2006.257.02:59:49.63#ibcon#flushed, iclass 3, count 2 2006.257.02:59:49.63#ibcon#about to write, iclass 3, count 2 2006.257.02:59:49.63#ibcon#wrote, iclass 3, count 2 2006.257.02:59:49.63#ibcon#about to read 3, iclass 3, count 2 2006.257.02:59:49.66#ibcon#read 3, iclass 3, count 2 2006.257.02:59:49.66#ibcon#about to read 4, iclass 3, count 2 2006.257.02:59:49.66#ibcon#read 4, iclass 3, count 2 2006.257.02:59:49.66#ibcon#about to read 5, iclass 3, count 2 2006.257.02:59:49.66#ibcon#read 5, iclass 3, count 2 2006.257.02:59:49.66#ibcon#about to read 6, iclass 3, count 2 2006.257.02:59:49.66#ibcon#read 6, iclass 3, count 2 2006.257.02:59:49.66#ibcon#end of sib2, iclass 3, count 2 2006.257.02:59:49.66#ibcon#*after write, iclass 3, count 2 2006.257.02:59:49.66#ibcon#*before return 0, iclass 3, count 2 2006.257.02:59:49.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:59:49.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.02:59:49.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.02:59:49.66#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:49.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:59:49.78#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:59:49.78#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:59:49.78#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:59:49.78#ibcon#first serial, iclass 3, count 0 2006.257.02:59:49.78#ibcon#enter sib2, iclass 3, count 0 2006.257.02:59:49.78#ibcon#flushed, iclass 3, count 0 2006.257.02:59:49.78#ibcon#about to write, iclass 3, count 0 2006.257.02:59:49.78#ibcon#wrote, iclass 3, count 0 2006.257.02:59:49.78#ibcon#about to read 3, iclass 3, count 0 2006.257.02:59:49.80#ibcon#read 3, iclass 3, count 0 2006.257.02:59:49.80#ibcon#about to read 4, iclass 3, count 0 2006.257.02:59:49.80#ibcon#read 4, iclass 3, count 0 2006.257.02:59:49.80#ibcon#about to read 5, iclass 3, count 0 2006.257.02:59:49.80#ibcon#read 5, iclass 3, count 0 2006.257.02:59:49.80#ibcon#about to read 6, iclass 3, count 0 2006.257.02:59:49.80#ibcon#read 6, iclass 3, count 0 2006.257.02:59:49.80#ibcon#end of sib2, iclass 3, count 0 2006.257.02:59:49.80#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:59:49.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:59:49.80#ibcon#[27=USB\r\n] 2006.257.02:59:49.80#ibcon#*before write, iclass 3, count 0 2006.257.02:59:49.80#ibcon#enter sib2, iclass 3, count 0 2006.257.02:59:49.80#ibcon#flushed, iclass 3, count 0 2006.257.02:59:49.80#ibcon#about to write, iclass 3, count 0 2006.257.02:59:49.80#ibcon#wrote, iclass 3, count 0 2006.257.02:59:49.80#ibcon#about to read 3, iclass 3, count 0 2006.257.02:59:49.83#ibcon#read 3, iclass 3, count 0 2006.257.02:59:49.83#ibcon#about to read 4, iclass 3, count 0 2006.257.02:59:49.83#ibcon#read 4, iclass 3, count 0 2006.257.02:59:49.83#ibcon#about to read 5, iclass 3, count 0 2006.257.02:59:49.83#ibcon#read 5, iclass 3, count 0 2006.257.02:59:49.83#ibcon#about to read 6, iclass 3, count 0 2006.257.02:59:49.83#ibcon#read 6, iclass 3, count 0 2006.257.02:59:49.83#ibcon#end of sib2, iclass 3, count 0 2006.257.02:59:49.83#ibcon#*after write, iclass 3, count 0 2006.257.02:59:49.83#ibcon#*before return 0, iclass 3, count 0 2006.257.02:59:49.83#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:59:49.83#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.02:59:49.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:59:49.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:59:49.83$vck44/vblo=2,634.99 2006.257.02:59:49.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.02:59:49.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.02:59:49.83#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:49.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:49.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:49.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:49.83#ibcon#enter wrdev, iclass 5, count 0 2006.257.02:59:49.83#ibcon#first serial, iclass 5, count 0 2006.257.02:59:49.83#ibcon#enter sib2, iclass 5, count 0 2006.257.02:59:49.83#ibcon#flushed, iclass 5, count 0 2006.257.02:59:49.83#ibcon#about to write, iclass 5, count 0 2006.257.02:59:49.83#ibcon#wrote, iclass 5, count 0 2006.257.02:59:49.83#ibcon#about to read 3, iclass 5, count 0 2006.257.02:59:49.85#ibcon#read 3, iclass 5, count 0 2006.257.02:59:49.85#ibcon#about to read 4, iclass 5, count 0 2006.257.02:59:49.85#ibcon#read 4, iclass 5, count 0 2006.257.02:59:49.85#ibcon#about to read 5, iclass 5, count 0 2006.257.02:59:49.85#ibcon#read 5, iclass 5, count 0 2006.257.02:59:49.85#ibcon#about to read 6, iclass 5, count 0 2006.257.02:59:49.85#ibcon#read 6, iclass 5, count 0 2006.257.02:59:49.85#ibcon#end of sib2, iclass 5, count 0 2006.257.02:59:49.85#ibcon#*mode == 0, iclass 5, count 0 2006.257.02:59:49.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.02:59:49.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.02:59:49.85#ibcon#*before write, iclass 5, count 0 2006.257.02:59:49.85#ibcon#enter sib2, iclass 5, count 0 2006.257.02:59:49.85#ibcon#flushed, iclass 5, count 0 2006.257.02:59:49.85#ibcon#about to write, iclass 5, count 0 2006.257.02:59:49.85#ibcon#wrote, iclass 5, count 0 2006.257.02:59:49.85#ibcon#about to read 3, iclass 5, count 0 2006.257.02:59:49.89#ibcon#read 3, iclass 5, count 0 2006.257.02:59:49.89#ibcon#about to read 4, iclass 5, count 0 2006.257.02:59:49.89#ibcon#read 4, iclass 5, count 0 2006.257.02:59:49.89#ibcon#about to read 5, iclass 5, count 0 2006.257.02:59:49.89#ibcon#read 5, iclass 5, count 0 2006.257.02:59:49.89#ibcon#about to read 6, iclass 5, count 0 2006.257.02:59:49.89#ibcon#read 6, iclass 5, count 0 2006.257.02:59:49.89#ibcon#end of sib2, iclass 5, count 0 2006.257.02:59:49.89#ibcon#*after write, iclass 5, count 0 2006.257.02:59:49.89#ibcon#*before return 0, iclass 5, count 0 2006.257.02:59:49.89#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:49.89#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.02:59:49.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.02:59:49.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.02:59:49.89$vck44/vb=2,5 2006.257.02:59:49.89#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.02:59:49.89#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.02:59:49.89#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:49.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:49.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:49.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:49.95#ibcon#enter wrdev, iclass 7, count 2 2006.257.02:59:49.95#ibcon#first serial, iclass 7, count 2 2006.257.02:59:49.95#ibcon#enter sib2, iclass 7, count 2 2006.257.02:59:49.95#ibcon#flushed, iclass 7, count 2 2006.257.02:59:49.95#ibcon#about to write, iclass 7, count 2 2006.257.02:59:49.95#ibcon#wrote, iclass 7, count 2 2006.257.02:59:49.95#ibcon#about to read 3, iclass 7, count 2 2006.257.02:59:49.97#ibcon#read 3, iclass 7, count 2 2006.257.02:59:49.97#ibcon#about to read 4, iclass 7, count 2 2006.257.02:59:49.97#ibcon#read 4, iclass 7, count 2 2006.257.02:59:49.97#ibcon#about to read 5, iclass 7, count 2 2006.257.02:59:49.97#ibcon#read 5, iclass 7, count 2 2006.257.02:59:49.97#ibcon#about to read 6, iclass 7, count 2 2006.257.02:59:49.97#ibcon#read 6, iclass 7, count 2 2006.257.02:59:49.97#ibcon#end of sib2, iclass 7, count 2 2006.257.02:59:49.97#ibcon#*mode == 0, iclass 7, count 2 2006.257.02:59:49.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.02:59:49.97#ibcon#[27=AT02-05\r\n] 2006.257.02:59:49.97#ibcon#*before write, iclass 7, count 2 2006.257.02:59:49.97#ibcon#enter sib2, iclass 7, count 2 2006.257.02:59:49.97#ibcon#flushed, iclass 7, count 2 2006.257.02:59:49.97#ibcon#about to write, iclass 7, count 2 2006.257.02:59:49.97#ibcon#wrote, iclass 7, count 2 2006.257.02:59:49.97#ibcon#about to read 3, iclass 7, count 2 2006.257.02:59:50.00#ibcon#read 3, iclass 7, count 2 2006.257.02:59:50.00#ibcon#about to read 4, iclass 7, count 2 2006.257.02:59:50.00#ibcon#read 4, iclass 7, count 2 2006.257.02:59:50.00#ibcon#about to read 5, iclass 7, count 2 2006.257.02:59:50.00#ibcon#read 5, iclass 7, count 2 2006.257.02:59:50.00#ibcon#about to read 6, iclass 7, count 2 2006.257.02:59:50.00#ibcon#read 6, iclass 7, count 2 2006.257.02:59:50.00#ibcon#end of sib2, iclass 7, count 2 2006.257.02:59:50.00#ibcon#*after write, iclass 7, count 2 2006.257.02:59:50.00#ibcon#*before return 0, iclass 7, count 2 2006.257.02:59:50.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:50.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.02:59:50.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.02:59:50.00#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:50.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:50.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:50.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:50.12#ibcon#enter wrdev, iclass 7, count 0 2006.257.02:59:50.12#ibcon#first serial, iclass 7, count 0 2006.257.02:59:50.12#ibcon#enter sib2, iclass 7, count 0 2006.257.02:59:50.12#ibcon#flushed, iclass 7, count 0 2006.257.02:59:50.12#ibcon#about to write, iclass 7, count 0 2006.257.02:59:50.12#ibcon#wrote, iclass 7, count 0 2006.257.02:59:50.12#ibcon#about to read 3, iclass 7, count 0 2006.257.02:59:50.14#ibcon#read 3, iclass 7, count 0 2006.257.02:59:50.14#ibcon#about to read 4, iclass 7, count 0 2006.257.02:59:50.14#ibcon#read 4, iclass 7, count 0 2006.257.02:59:50.14#ibcon#about to read 5, iclass 7, count 0 2006.257.02:59:50.14#ibcon#read 5, iclass 7, count 0 2006.257.02:59:50.14#ibcon#about to read 6, iclass 7, count 0 2006.257.02:59:50.14#ibcon#read 6, iclass 7, count 0 2006.257.02:59:50.14#ibcon#end of sib2, iclass 7, count 0 2006.257.02:59:50.14#ibcon#*mode == 0, iclass 7, count 0 2006.257.02:59:50.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.02:59:50.14#ibcon#[27=USB\r\n] 2006.257.02:59:50.14#ibcon#*before write, iclass 7, count 0 2006.257.02:59:50.14#ibcon#enter sib2, iclass 7, count 0 2006.257.02:59:50.14#ibcon#flushed, iclass 7, count 0 2006.257.02:59:50.14#ibcon#about to write, iclass 7, count 0 2006.257.02:59:50.14#ibcon#wrote, iclass 7, count 0 2006.257.02:59:50.14#ibcon#about to read 3, iclass 7, count 0 2006.257.02:59:50.17#ibcon#read 3, iclass 7, count 0 2006.257.02:59:50.17#ibcon#about to read 4, iclass 7, count 0 2006.257.02:59:50.17#ibcon#read 4, iclass 7, count 0 2006.257.02:59:50.17#ibcon#about to read 5, iclass 7, count 0 2006.257.02:59:50.17#ibcon#read 5, iclass 7, count 0 2006.257.02:59:50.17#ibcon#about to read 6, iclass 7, count 0 2006.257.02:59:50.17#ibcon#read 6, iclass 7, count 0 2006.257.02:59:50.17#ibcon#end of sib2, iclass 7, count 0 2006.257.02:59:50.17#ibcon#*after write, iclass 7, count 0 2006.257.02:59:50.17#ibcon#*before return 0, iclass 7, count 0 2006.257.02:59:50.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:50.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.02:59:50.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.02:59:50.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.02:59:50.17$vck44/vblo=3,649.99 2006.257.02:59:50.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.02:59:50.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.02:59:50.17#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:50.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:50.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:50.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:50.17#ibcon#enter wrdev, iclass 11, count 0 2006.257.02:59:50.17#ibcon#first serial, iclass 11, count 0 2006.257.02:59:50.17#ibcon#enter sib2, iclass 11, count 0 2006.257.02:59:50.17#ibcon#flushed, iclass 11, count 0 2006.257.02:59:50.17#ibcon#about to write, iclass 11, count 0 2006.257.02:59:50.17#ibcon#wrote, iclass 11, count 0 2006.257.02:59:50.17#ibcon#about to read 3, iclass 11, count 0 2006.257.02:59:50.19#ibcon#read 3, iclass 11, count 0 2006.257.02:59:50.19#ibcon#about to read 4, iclass 11, count 0 2006.257.02:59:50.19#ibcon#read 4, iclass 11, count 0 2006.257.02:59:50.19#ibcon#about to read 5, iclass 11, count 0 2006.257.02:59:50.19#ibcon#read 5, iclass 11, count 0 2006.257.02:59:50.19#ibcon#about to read 6, iclass 11, count 0 2006.257.02:59:50.19#ibcon#read 6, iclass 11, count 0 2006.257.02:59:50.19#ibcon#end of sib2, iclass 11, count 0 2006.257.02:59:50.19#ibcon#*mode == 0, iclass 11, count 0 2006.257.02:59:50.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.02:59:50.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.02:59:50.19#ibcon#*before write, iclass 11, count 0 2006.257.02:59:50.19#ibcon#enter sib2, iclass 11, count 0 2006.257.02:59:50.19#ibcon#flushed, iclass 11, count 0 2006.257.02:59:50.19#ibcon#about to write, iclass 11, count 0 2006.257.02:59:50.19#ibcon#wrote, iclass 11, count 0 2006.257.02:59:50.19#ibcon#about to read 3, iclass 11, count 0 2006.257.02:59:50.23#ibcon#read 3, iclass 11, count 0 2006.257.02:59:50.23#ibcon#about to read 4, iclass 11, count 0 2006.257.02:59:50.23#ibcon#read 4, iclass 11, count 0 2006.257.02:59:50.23#ibcon#about to read 5, iclass 11, count 0 2006.257.02:59:50.23#ibcon#read 5, iclass 11, count 0 2006.257.02:59:50.23#ibcon#about to read 6, iclass 11, count 0 2006.257.02:59:50.23#ibcon#read 6, iclass 11, count 0 2006.257.02:59:50.23#ibcon#end of sib2, iclass 11, count 0 2006.257.02:59:50.23#ibcon#*after write, iclass 11, count 0 2006.257.02:59:50.23#ibcon#*before return 0, iclass 11, count 0 2006.257.02:59:50.23#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:50.23#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.02:59:50.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.02:59:50.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.02:59:50.23$vck44/vb=3,4 2006.257.02:59:50.23#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.02:59:50.23#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.02:59:50.23#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:50.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:50.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:50.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:50.29#ibcon#enter wrdev, iclass 13, count 2 2006.257.02:59:50.29#ibcon#first serial, iclass 13, count 2 2006.257.02:59:50.29#ibcon#enter sib2, iclass 13, count 2 2006.257.02:59:50.29#ibcon#flushed, iclass 13, count 2 2006.257.02:59:50.29#ibcon#about to write, iclass 13, count 2 2006.257.02:59:50.29#ibcon#wrote, iclass 13, count 2 2006.257.02:59:50.29#ibcon#about to read 3, iclass 13, count 2 2006.257.02:59:50.31#ibcon#read 3, iclass 13, count 2 2006.257.02:59:50.31#ibcon#about to read 4, iclass 13, count 2 2006.257.02:59:50.31#ibcon#read 4, iclass 13, count 2 2006.257.02:59:50.31#ibcon#about to read 5, iclass 13, count 2 2006.257.02:59:50.31#ibcon#read 5, iclass 13, count 2 2006.257.02:59:50.31#ibcon#about to read 6, iclass 13, count 2 2006.257.02:59:50.31#ibcon#read 6, iclass 13, count 2 2006.257.02:59:50.31#ibcon#end of sib2, iclass 13, count 2 2006.257.02:59:50.31#ibcon#*mode == 0, iclass 13, count 2 2006.257.02:59:50.31#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.02:59:50.31#ibcon#[27=AT03-04\r\n] 2006.257.02:59:50.31#ibcon#*before write, iclass 13, count 2 2006.257.02:59:50.31#ibcon#enter sib2, iclass 13, count 2 2006.257.02:59:50.31#ibcon#flushed, iclass 13, count 2 2006.257.02:59:50.31#ibcon#about to write, iclass 13, count 2 2006.257.02:59:50.31#ibcon#wrote, iclass 13, count 2 2006.257.02:59:50.31#ibcon#about to read 3, iclass 13, count 2 2006.257.02:59:50.34#ibcon#read 3, iclass 13, count 2 2006.257.02:59:50.34#ibcon#about to read 4, iclass 13, count 2 2006.257.02:59:50.34#ibcon#read 4, iclass 13, count 2 2006.257.02:59:50.34#ibcon#about to read 5, iclass 13, count 2 2006.257.02:59:50.34#ibcon#read 5, iclass 13, count 2 2006.257.02:59:50.34#ibcon#about to read 6, iclass 13, count 2 2006.257.02:59:50.34#ibcon#read 6, iclass 13, count 2 2006.257.02:59:50.34#ibcon#end of sib2, iclass 13, count 2 2006.257.02:59:50.34#ibcon#*after write, iclass 13, count 2 2006.257.02:59:50.34#ibcon#*before return 0, iclass 13, count 2 2006.257.02:59:50.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:50.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.02:59:50.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.02:59:50.34#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:50.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:50.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:50.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:50.46#ibcon#enter wrdev, iclass 13, count 0 2006.257.02:59:50.46#ibcon#first serial, iclass 13, count 0 2006.257.02:59:50.46#ibcon#enter sib2, iclass 13, count 0 2006.257.02:59:50.46#ibcon#flushed, iclass 13, count 0 2006.257.02:59:50.46#ibcon#about to write, iclass 13, count 0 2006.257.02:59:50.46#ibcon#wrote, iclass 13, count 0 2006.257.02:59:50.46#ibcon#about to read 3, iclass 13, count 0 2006.257.02:59:50.48#ibcon#read 3, iclass 13, count 0 2006.257.02:59:50.48#ibcon#about to read 4, iclass 13, count 0 2006.257.02:59:50.48#ibcon#read 4, iclass 13, count 0 2006.257.02:59:50.48#ibcon#about to read 5, iclass 13, count 0 2006.257.02:59:50.48#ibcon#read 5, iclass 13, count 0 2006.257.02:59:50.48#ibcon#about to read 6, iclass 13, count 0 2006.257.02:59:50.48#ibcon#read 6, iclass 13, count 0 2006.257.02:59:50.48#ibcon#end of sib2, iclass 13, count 0 2006.257.02:59:50.48#ibcon#*mode == 0, iclass 13, count 0 2006.257.02:59:50.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.02:59:50.48#ibcon#[27=USB\r\n] 2006.257.02:59:50.48#ibcon#*before write, iclass 13, count 0 2006.257.02:59:50.48#ibcon#enter sib2, iclass 13, count 0 2006.257.02:59:50.48#ibcon#flushed, iclass 13, count 0 2006.257.02:59:50.48#ibcon#about to write, iclass 13, count 0 2006.257.02:59:50.48#ibcon#wrote, iclass 13, count 0 2006.257.02:59:50.48#ibcon#about to read 3, iclass 13, count 0 2006.257.02:59:50.51#ibcon#read 3, iclass 13, count 0 2006.257.02:59:50.51#ibcon#about to read 4, iclass 13, count 0 2006.257.02:59:50.51#ibcon#read 4, iclass 13, count 0 2006.257.02:59:50.51#ibcon#about to read 5, iclass 13, count 0 2006.257.02:59:50.51#ibcon#read 5, iclass 13, count 0 2006.257.02:59:50.51#ibcon#about to read 6, iclass 13, count 0 2006.257.02:59:50.51#ibcon#read 6, iclass 13, count 0 2006.257.02:59:50.51#ibcon#end of sib2, iclass 13, count 0 2006.257.02:59:50.51#ibcon#*after write, iclass 13, count 0 2006.257.02:59:50.51#ibcon#*before return 0, iclass 13, count 0 2006.257.02:59:50.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:50.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.02:59:50.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.02:59:50.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.02:59:50.51$vck44/vblo=4,679.99 2006.257.02:59:50.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.02:59:50.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.02:59:50.51#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:50.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:50.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:50.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:50.51#ibcon#enter wrdev, iclass 15, count 0 2006.257.02:59:50.51#ibcon#first serial, iclass 15, count 0 2006.257.02:59:50.51#ibcon#enter sib2, iclass 15, count 0 2006.257.02:59:50.51#ibcon#flushed, iclass 15, count 0 2006.257.02:59:50.51#ibcon#about to write, iclass 15, count 0 2006.257.02:59:50.51#ibcon#wrote, iclass 15, count 0 2006.257.02:59:50.51#ibcon#about to read 3, iclass 15, count 0 2006.257.02:59:50.53#ibcon#read 3, iclass 15, count 0 2006.257.02:59:50.53#ibcon#about to read 4, iclass 15, count 0 2006.257.02:59:50.53#ibcon#read 4, iclass 15, count 0 2006.257.02:59:50.53#ibcon#about to read 5, iclass 15, count 0 2006.257.02:59:50.53#ibcon#read 5, iclass 15, count 0 2006.257.02:59:50.53#ibcon#about to read 6, iclass 15, count 0 2006.257.02:59:50.53#ibcon#read 6, iclass 15, count 0 2006.257.02:59:50.53#ibcon#end of sib2, iclass 15, count 0 2006.257.02:59:50.53#ibcon#*mode == 0, iclass 15, count 0 2006.257.02:59:50.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.02:59:50.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.02:59:50.53#ibcon#*before write, iclass 15, count 0 2006.257.02:59:50.53#ibcon#enter sib2, iclass 15, count 0 2006.257.02:59:50.53#ibcon#flushed, iclass 15, count 0 2006.257.02:59:50.53#ibcon#about to write, iclass 15, count 0 2006.257.02:59:50.53#ibcon#wrote, iclass 15, count 0 2006.257.02:59:50.53#ibcon#about to read 3, iclass 15, count 0 2006.257.02:59:50.57#ibcon#read 3, iclass 15, count 0 2006.257.02:59:50.57#ibcon#about to read 4, iclass 15, count 0 2006.257.02:59:50.57#ibcon#read 4, iclass 15, count 0 2006.257.02:59:50.57#ibcon#about to read 5, iclass 15, count 0 2006.257.02:59:50.57#ibcon#read 5, iclass 15, count 0 2006.257.02:59:50.57#ibcon#about to read 6, iclass 15, count 0 2006.257.02:59:50.57#ibcon#read 6, iclass 15, count 0 2006.257.02:59:50.57#ibcon#end of sib2, iclass 15, count 0 2006.257.02:59:50.57#ibcon#*after write, iclass 15, count 0 2006.257.02:59:50.57#ibcon#*before return 0, iclass 15, count 0 2006.257.02:59:50.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:50.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.02:59:50.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.02:59:50.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.02:59:50.57$vck44/vb=4,5 2006.257.02:59:50.57#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.02:59:50.57#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.02:59:50.57#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:50.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:50.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:50.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:50.63#ibcon#enter wrdev, iclass 17, count 2 2006.257.02:59:50.63#ibcon#first serial, iclass 17, count 2 2006.257.02:59:50.63#ibcon#enter sib2, iclass 17, count 2 2006.257.02:59:50.63#ibcon#flushed, iclass 17, count 2 2006.257.02:59:50.63#ibcon#about to write, iclass 17, count 2 2006.257.02:59:50.63#ibcon#wrote, iclass 17, count 2 2006.257.02:59:50.63#ibcon#about to read 3, iclass 17, count 2 2006.257.02:59:50.65#ibcon#read 3, iclass 17, count 2 2006.257.02:59:50.65#ibcon#about to read 4, iclass 17, count 2 2006.257.02:59:50.65#ibcon#read 4, iclass 17, count 2 2006.257.02:59:50.65#ibcon#about to read 5, iclass 17, count 2 2006.257.02:59:50.65#ibcon#read 5, iclass 17, count 2 2006.257.02:59:50.65#ibcon#about to read 6, iclass 17, count 2 2006.257.02:59:50.65#ibcon#read 6, iclass 17, count 2 2006.257.02:59:50.65#ibcon#end of sib2, iclass 17, count 2 2006.257.02:59:50.65#ibcon#*mode == 0, iclass 17, count 2 2006.257.02:59:50.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.02:59:50.65#ibcon#[27=AT04-05\r\n] 2006.257.02:59:50.65#ibcon#*before write, iclass 17, count 2 2006.257.02:59:50.65#ibcon#enter sib2, iclass 17, count 2 2006.257.02:59:50.65#ibcon#flushed, iclass 17, count 2 2006.257.02:59:50.65#ibcon#about to write, iclass 17, count 2 2006.257.02:59:50.65#ibcon#wrote, iclass 17, count 2 2006.257.02:59:50.65#ibcon#about to read 3, iclass 17, count 2 2006.257.02:59:50.68#ibcon#read 3, iclass 17, count 2 2006.257.02:59:50.68#ibcon#about to read 4, iclass 17, count 2 2006.257.02:59:50.68#ibcon#read 4, iclass 17, count 2 2006.257.02:59:50.68#ibcon#about to read 5, iclass 17, count 2 2006.257.02:59:50.68#ibcon#read 5, iclass 17, count 2 2006.257.02:59:50.68#ibcon#about to read 6, iclass 17, count 2 2006.257.02:59:50.68#ibcon#read 6, iclass 17, count 2 2006.257.02:59:50.68#ibcon#end of sib2, iclass 17, count 2 2006.257.02:59:50.68#ibcon#*after write, iclass 17, count 2 2006.257.02:59:50.68#ibcon#*before return 0, iclass 17, count 2 2006.257.02:59:50.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:50.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.02:59:50.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.02:59:50.68#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:50.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:50.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:50.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:50.80#ibcon#enter wrdev, iclass 17, count 0 2006.257.02:59:50.80#ibcon#first serial, iclass 17, count 0 2006.257.02:59:50.80#ibcon#enter sib2, iclass 17, count 0 2006.257.02:59:50.80#ibcon#flushed, iclass 17, count 0 2006.257.02:59:50.80#ibcon#about to write, iclass 17, count 0 2006.257.02:59:50.80#ibcon#wrote, iclass 17, count 0 2006.257.02:59:50.80#ibcon#about to read 3, iclass 17, count 0 2006.257.02:59:50.82#ibcon#read 3, iclass 17, count 0 2006.257.02:59:50.82#ibcon#about to read 4, iclass 17, count 0 2006.257.02:59:50.82#ibcon#read 4, iclass 17, count 0 2006.257.02:59:50.82#ibcon#about to read 5, iclass 17, count 0 2006.257.02:59:50.82#ibcon#read 5, iclass 17, count 0 2006.257.02:59:50.82#ibcon#about to read 6, iclass 17, count 0 2006.257.02:59:50.82#ibcon#read 6, iclass 17, count 0 2006.257.02:59:50.82#ibcon#end of sib2, iclass 17, count 0 2006.257.02:59:50.82#ibcon#*mode == 0, iclass 17, count 0 2006.257.02:59:50.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.02:59:50.82#ibcon#[27=USB\r\n] 2006.257.02:59:50.82#ibcon#*before write, iclass 17, count 0 2006.257.02:59:50.82#ibcon#enter sib2, iclass 17, count 0 2006.257.02:59:50.82#ibcon#flushed, iclass 17, count 0 2006.257.02:59:50.82#ibcon#about to write, iclass 17, count 0 2006.257.02:59:50.82#ibcon#wrote, iclass 17, count 0 2006.257.02:59:50.82#ibcon#about to read 3, iclass 17, count 0 2006.257.02:59:50.85#ibcon#read 3, iclass 17, count 0 2006.257.02:59:50.85#ibcon#about to read 4, iclass 17, count 0 2006.257.02:59:50.85#ibcon#read 4, iclass 17, count 0 2006.257.02:59:50.85#ibcon#about to read 5, iclass 17, count 0 2006.257.02:59:50.85#ibcon#read 5, iclass 17, count 0 2006.257.02:59:50.85#ibcon#about to read 6, iclass 17, count 0 2006.257.02:59:50.85#ibcon#read 6, iclass 17, count 0 2006.257.02:59:50.85#ibcon#end of sib2, iclass 17, count 0 2006.257.02:59:50.85#ibcon#*after write, iclass 17, count 0 2006.257.02:59:50.85#ibcon#*before return 0, iclass 17, count 0 2006.257.02:59:50.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:50.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.02:59:50.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.02:59:50.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.02:59:50.85$vck44/vblo=5,709.99 2006.257.02:59:50.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.02:59:50.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.02:59:50.85#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:50.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:50.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:50.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:50.85#ibcon#enter wrdev, iclass 19, count 0 2006.257.02:59:50.85#ibcon#first serial, iclass 19, count 0 2006.257.02:59:50.85#ibcon#enter sib2, iclass 19, count 0 2006.257.02:59:50.85#ibcon#flushed, iclass 19, count 0 2006.257.02:59:50.85#ibcon#about to write, iclass 19, count 0 2006.257.02:59:50.85#ibcon#wrote, iclass 19, count 0 2006.257.02:59:50.85#ibcon#about to read 3, iclass 19, count 0 2006.257.02:59:50.87#ibcon#read 3, iclass 19, count 0 2006.257.02:59:50.87#ibcon#about to read 4, iclass 19, count 0 2006.257.02:59:50.87#ibcon#read 4, iclass 19, count 0 2006.257.02:59:50.87#ibcon#about to read 5, iclass 19, count 0 2006.257.02:59:50.87#ibcon#read 5, iclass 19, count 0 2006.257.02:59:50.87#ibcon#about to read 6, iclass 19, count 0 2006.257.02:59:50.87#ibcon#read 6, iclass 19, count 0 2006.257.02:59:50.87#ibcon#end of sib2, iclass 19, count 0 2006.257.02:59:50.87#ibcon#*mode == 0, iclass 19, count 0 2006.257.02:59:50.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.02:59:50.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.02:59:50.87#ibcon#*before write, iclass 19, count 0 2006.257.02:59:50.87#ibcon#enter sib2, iclass 19, count 0 2006.257.02:59:50.87#ibcon#flushed, iclass 19, count 0 2006.257.02:59:50.87#ibcon#about to write, iclass 19, count 0 2006.257.02:59:50.87#ibcon#wrote, iclass 19, count 0 2006.257.02:59:50.87#ibcon#about to read 3, iclass 19, count 0 2006.257.02:59:50.91#ibcon#read 3, iclass 19, count 0 2006.257.02:59:50.91#ibcon#about to read 4, iclass 19, count 0 2006.257.02:59:50.91#ibcon#read 4, iclass 19, count 0 2006.257.02:59:50.91#ibcon#about to read 5, iclass 19, count 0 2006.257.02:59:50.91#ibcon#read 5, iclass 19, count 0 2006.257.02:59:50.91#ibcon#about to read 6, iclass 19, count 0 2006.257.02:59:50.91#ibcon#read 6, iclass 19, count 0 2006.257.02:59:50.91#ibcon#end of sib2, iclass 19, count 0 2006.257.02:59:50.91#ibcon#*after write, iclass 19, count 0 2006.257.02:59:50.91#ibcon#*before return 0, iclass 19, count 0 2006.257.02:59:50.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:50.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.02:59:50.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.02:59:50.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.02:59:50.91$vck44/vb=5,4 2006.257.02:59:50.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.02:59:50.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.02:59:50.91#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:50.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:50.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:50.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:50.97#ibcon#enter wrdev, iclass 21, count 2 2006.257.02:59:50.97#ibcon#first serial, iclass 21, count 2 2006.257.02:59:50.97#ibcon#enter sib2, iclass 21, count 2 2006.257.02:59:50.97#ibcon#flushed, iclass 21, count 2 2006.257.02:59:50.97#ibcon#about to write, iclass 21, count 2 2006.257.02:59:50.97#ibcon#wrote, iclass 21, count 2 2006.257.02:59:50.97#ibcon#about to read 3, iclass 21, count 2 2006.257.02:59:50.99#ibcon#read 3, iclass 21, count 2 2006.257.02:59:50.99#ibcon#about to read 4, iclass 21, count 2 2006.257.02:59:50.99#ibcon#read 4, iclass 21, count 2 2006.257.02:59:50.99#ibcon#about to read 5, iclass 21, count 2 2006.257.02:59:50.99#ibcon#read 5, iclass 21, count 2 2006.257.02:59:50.99#ibcon#about to read 6, iclass 21, count 2 2006.257.02:59:50.99#ibcon#read 6, iclass 21, count 2 2006.257.02:59:50.99#ibcon#end of sib2, iclass 21, count 2 2006.257.02:59:50.99#ibcon#*mode == 0, iclass 21, count 2 2006.257.02:59:50.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.02:59:50.99#ibcon#[27=AT05-04\r\n] 2006.257.02:59:50.99#ibcon#*before write, iclass 21, count 2 2006.257.02:59:50.99#ibcon#enter sib2, iclass 21, count 2 2006.257.02:59:50.99#ibcon#flushed, iclass 21, count 2 2006.257.02:59:50.99#ibcon#about to write, iclass 21, count 2 2006.257.02:59:50.99#ibcon#wrote, iclass 21, count 2 2006.257.02:59:50.99#ibcon#about to read 3, iclass 21, count 2 2006.257.02:59:51.02#ibcon#read 3, iclass 21, count 2 2006.257.02:59:51.02#ibcon#about to read 4, iclass 21, count 2 2006.257.02:59:51.02#ibcon#read 4, iclass 21, count 2 2006.257.02:59:51.02#ibcon#about to read 5, iclass 21, count 2 2006.257.02:59:51.02#ibcon#read 5, iclass 21, count 2 2006.257.02:59:51.02#ibcon#about to read 6, iclass 21, count 2 2006.257.02:59:51.02#ibcon#read 6, iclass 21, count 2 2006.257.02:59:51.02#ibcon#end of sib2, iclass 21, count 2 2006.257.02:59:51.02#ibcon#*after write, iclass 21, count 2 2006.257.02:59:51.02#ibcon#*before return 0, iclass 21, count 2 2006.257.02:59:51.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:51.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.02:59:51.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.02:59:51.02#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:51.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:51.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:51.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:51.14#ibcon#enter wrdev, iclass 21, count 0 2006.257.02:59:51.14#ibcon#first serial, iclass 21, count 0 2006.257.02:59:51.14#ibcon#enter sib2, iclass 21, count 0 2006.257.02:59:51.14#ibcon#flushed, iclass 21, count 0 2006.257.02:59:51.14#ibcon#about to write, iclass 21, count 0 2006.257.02:59:51.14#ibcon#wrote, iclass 21, count 0 2006.257.02:59:51.14#ibcon#about to read 3, iclass 21, count 0 2006.257.02:59:51.16#ibcon#read 3, iclass 21, count 0 2006.257.02:59:51.16#ibcon#about to read 4, iclass 21, count 0 2006.257.02:59:51.16#ibcon#read 4, iclass 21, count 0 2006.257.02:59:51.16#ibcon#about to read 5, iclass 21, count 0 2006.257.02:59:51.16#ibcon#read 5, iclass 21, count 0 2006.257.02:59:51.16#ibcon#about to read 6, iclass 21, count 0 2006.257.02:59:51.16#ibcon#read 6, iclass 21, count 0 2006.257.02:59:51.16#ibcon#end of sib2, iclass 21, count 0 2006.257.02:59:51.16#ibcon#*mode == 0, iclass 21, count 0 2006.257.02:59:51.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.02:59:51.16#ibcon#[27=USB\r\n] 2006.257.02:59:51.16#ibcon#*before write, iclass 21, count 0 2006.257.02:59:51.16#ibcon#enter sib2, iclass 21, count 0 2006.257.02:59:51.16#ibcon#flushed, iclass 21, count 0 2006.257.02:59:51.16#ibcon#about to write, iclass 21, count 0 2006.257.02:59:51.16#ibcon#wrote, iclass 21, count 0 2006.257.02:59:51.16#ibcon#about to read 3, iclass 21, count 0 2006.257.02:59:51.19#ibcon#read 3, iclass 21, count 0 2006.257.02:59:51.19#ibcon#about to read 4, iclass 21, count 0 2006.257.02:59:51.19#ibcon#read 4, iclass 21, count 0 2006.257.02:59:51.19#ibcon#about to read 5, iclass 21, count 0 2006.257.02:59:51.19#ibcon#read 5, iclass 21, count 0 2006.257.02:59:51.19#ibcon#about to read 6, iclass 21, count 0 2006.257.02:59:51.19#ibcon#read 6, iclass 21, count 0 2006.257.02:59:51.19#ibcon#end of sib2, iclass 21, count 0 2006.257.02:59:51.19#ibcon#*after write, iclass 21, count 0 2006.257.02:59:51.19#ibcon#*before return 0, iclass 21, count 0 2006.257.02:59:51.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:51.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.02:59:51.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.02:59:51.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.02:59:51.19$vck44/vblo=6,719.99 2006.257.02:59:51.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.02:59:51.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.02:59:51.19#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:51.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:51.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:51.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:51.19#ibcon#enter wrdev, iclass 23, count 0 2006.257.02:59:51.19#ibcon#first serial, iclass 23, count 0 2006.257.02:59:51.19#ibcon#enter sib2, iclass 23, count 0 2006.257.02:59:51.19#ibcon#flushed, iclass 23, count 0 2006.257.02:59:51.19#ibcon#about to write, iclass 23, count 0 2006.257.02:59:51.19#ibcon#wrote, iclass 23, count 0 2006.257.02:59:51.19#ibcon#about to read 3, iclass 23, count 0 2006.257.02:59:51.21#ibcon#read 3, iclass 23, count 0 2006.257.02:59:51.21#ibcon#about to read 4, iclass 23, count 0 2006.257.02:59:51.21#ibcon#read 4, iclass 23, count 0 2006.257.02:59:51.21#ibcon#about to read 5, iclass 23, count 0 2006.257.02:59:51.21#ibcon#read 5, iclass 23, count 0 2006.257.02:59:51.21#ibcon#about to read 6, iclass 23, count 0 2006.257.02:59:51.21#ibcon#read 6, iclass 23, count 0 2006.257.02:59:51.21#ibcon#end of sib2, iclass 23, count 0 2006.257.02:59:51.21#ibcon#*mode == 0, iclass 23, count 0 2006.257.02:59:51.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.02:59:51.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.02:59:51.21#ibcon#*before write, iclass 23, count 0 2006.257.02:59:51.21#ibcon#enter sib2, iclass 23, count 0 2006.257.02:59:51.21#ibcon#flushed, iclass 23, count 0 2006.257.02:59:51.21#ibcon#about to write, iclass 23, count 0 2006.257.02:59:51.21#ibcon#wrote, iclass 23, count 0 2006.257.02:59:51.21#ibcon#about to read 3, iclass 23, count 0 2006.257.02:59:51.25#ibcon#read 3, iclass 23, count 0 2006.257.02:59:51.25#ibcon#about to read 4, iclass 23, count 0 2006.257.02:59:51.25#ibcon#read 4, iclass 23, count 0 2006.257.02:59:51.25#ibcon#about to read 5, iclass 23, count 0 2006.257.02:59:51.25#ibcon#read 5, iclass 23, count 0 2006.257.02:59:51.25#ibcon#about to read 6, iclass 23, count 0 2006.257.02:59:51.25#ibcon#read 6, iclass 23, count 0 2006.257.02:59:51.25#ibcon#end of sib2, iclass 23, count 0 2006.257.02:59:51.25#ibcon#*after write, iclass 23, count 0 2006.257.02:59:51.25#ibcon#*before return 0, iclass 23, count 0 2006.257.02:59:51.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:51.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.02:59:51.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.02:59:51.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.02:59:51.25$vck44/vb=6,4 2006.257.02:59:51.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.02:59:51.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.02:59:51.25#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:51.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:51.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:51.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:51.31#ibcon#enter wrdev, iclass 25, count 2 2006.257.02:59:51.31#ibcon#first serial, iclass 25, count 2 2006.257.02:59:51.31#ibcon#enter sib2, iclass 25, count 2 2006.257.02:59:51.31#ibcon#flushed, iclass 25, count 2 2006.257.02:59:51.31#ibcon#about to write, iclass 25, count 2 2006.257.02:59:51.31#ibcon#wrote, iclass 25, count 2 2006.257.02:59:51.31#ibcon#about to read 3, iclass 25, count 2 2006.257.02:59:51.33#ibcon#read 3, iclass 25, count 2 2006.257.02:59:51.33#ibcon#about to read 4, iclass 25, count 2 2006.257.02:59:51.33#ibcon#read 4, iclass 25, count 2 2006.257.02:59:51.33#ibcon#about to read 5, iclass 25, count 2 2006.257.02:59:51.33#ibcon#read 5, iclass 25, count 2 2006.257.02:59:51.33#ibcon#about to read 6, iclass 25, count 2 2006.257.02:59:51.33#ibcon#read 6, iclass 25, count 2 2006.257.02:59:51.33#ibcon#end of sib2, iclass 25, count 2 2006.257.02:59:51.33#ibcon#*mode == 0, iclass 25, count 2 2006.257.02:59:51.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.02:59:51.33#ibcon#[27=AT06-04\r\n] 2006.257.02:59:51.33#ibcon#*before write, iclass 25, count 2 2006.257.02:59:51.33#ibcon#enter sib2, iclass 25, count 2 2006.257.02:59:51.33#ibcon#flushed, iclass 25, count 2 2006.257.02:59:51.33#ibcon#about to write, iclass 25, count 2 2006.257.02:59:51.33#ibcon#wrote, iclass 25, count 2 2006.257.02:59:51.33#ibcon#about to read 3, iclass 25, count 2 2006.257.02:59:51.36#ibcon#read 3, iclass 25, count 2 2006.257.02:59:51.36#ibcon#about to read 4, iclass 25, count 2 2006.257.02:59:51.36#ibcon#read 4, iclass 25, count 2 2006.257.02:59:51.36#ibcon#about to read 5, iclass 25, count 2 2006.257.02:59:51.36#ibcon#read 5, iclass 25, count 2 2006.257.02:59:51.36#ibcon#about to read 6, iclass 25, count 2 2006.257.02:59:51.36#ibcon#read 6, iclass 25, count 2 2006.257.02:59:51.36#ibcon#end of sib2, iclass 25, count 2 2006.257.02:59:51.36#ibcon#*after write, iclass 25, count 2 2006.257.02:59:51.36#ibcon#*before return 0, iclass 25, count 2 2006.257.02:59:51.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:51.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.02:59:51.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.02:59:51.36#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:51.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:51.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:51.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:51.48#ibcon#enter wrdev, iclass 25, count 0 2006.257.02:59:51.48#ibcon#first serial, iclass 25, count 0 2006.257.02:59:51.48#ibcon#enter sib2, iclass 25, count 0 2006.257.02:59:51.48#ibcon#flushed, iclass 25, count 0 2006.257.02:59:51.48#ibcon#about to write, iclass 25, count 0 2006.257.02:59:51.48#ibcon#wrote, iclass 25, count 0 2006.257.02:59:51.48#ibcon#about to read 3, iclass 25, count 0 2006.257.02:59:51.50#ibcon#read 3, iclass 25, count 0 2006.257.02:59:51.50#ibcon#about to read 4, iclass 25, count 0 2006.257.02:59:51.50#ibcon#read 4, iclass 25, count 0 2006.257.02:59:51.50#ibcon#about to read 5, iclass 25, count 0 2006.257.02:59:51.50#ibcon#read 5, iclass 25, count 0 2006.257.02:59:51.50#ibcon#about to read 6, iclass 25, count 0 2006.257.02:59:51.50#ibcon#read 6, iclass 25, count 0 2006.257.02:59:51.50#ibcon#end of sib2, iclass 25, count 0 2006.257.02:59:51.50#ibcon#*mode == 0, iclass 25, count 0 2006.257.02:59:51.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.02:59:51.50#ibcon#[27=USB\r\n] 2006.257.02:59:51.50#ibcon#*before write, iclass 25, count 0 2006.257.02:59:51.50#ibcon#enter sib2, iclass 25, count 0 2006.257.02:59:51.50#ibcon#flushed, iclass 25, count 0 2006.257.02:59:51.50#ibcon#about to write, iclass 25, count 0 2006.257.02:59:51.50#ibcon#wrote, iclass 25, count 0 2006.257.02:59:51.50#ibcon#about to read 3, iclass 25, count 0 2006.257.02:59:51.53#ibcon#read 3, iclass 25, count 0 2006.257.02:59:51.53#ibcon#about to read 4, iclass 25, count 0 2006.257.02:59:51.53#ibcon#read 4, iclass 25, count 0 2006.257.02:59:51.53#ibcon#about to read 5, iclass 25, count 0 2006.257.02:59:51.53#ibcon#read 5, iclass 25, count 0 2006.257.02:59:51.53#ibcon#about to read 6, iclass 25, count 0 2006.257.02:59:51.53#ibcon#read 6, iclass 25, count 0 2006.257.02:59:51.53#ibcon#end of sib2, iclass 25, count 0 2006.257.02:59:51.53#ibcon#*after write, iclass 25, count 0 2006.257.02:59:51.53#ibcon#*before return 0, iclass 25, count 0 2006.257.02:59:51.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:51.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.02:59:51.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.02:59:51.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.02:59:51.53$vck44/vblo=7,734.99 2006.257.02:59:51.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.02:59:51.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.02:59:51.53#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:51.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:51.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:51.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:51.53#ibcon#enter wrdev, iclass 27, count 0 2006.257.02:59:51.53#ibcon#first serial, iclass 27, count 0 2006.257.02:59:51.53#ibcon#enter sib2, iclass 27, count 0 2006.257.02:59:51.53#ibcon#flushed, iclass 27, count 0 2006.257.02:59:51.53#ibcon#about to write, iclass 27, count 0 2006.257.02:59:51.53#ibcon#wrote, iclass 27, count 0 2006.257.02:59:51.53#ibcon#about to read 3, iclass 27, count 0 2006.257.02:59:51.55#ibcon#read 3, iclass 27, count 0 2006.257.02:59:51.55#ibcon#about to read 4, iclass 27, count 0 2006.257.02:59:51.55#ibcon#read 4, iclass 27, count 0 2006.257.02:59:51.55#ibcon#about to read 5, iclass 27, count 0 2006.257.02:59:51.55#ibcon#read 5, iclass 27, count 0 2006.257.02:59:51.55#ibcon#about to read 6, iclass 27, count 0 2006.257.02:59:51.55#ibcon#read 6, iclass 27, count 0 2006.257.02:59:51.55#ibcon#end of sib2, iclass 27, count 0 2006.257.02:59:51.55#ibcon#*mode == 0, iclass 27, count 0 2006.257.02:59:51.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.02:59:51.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.02:59:51.55#ibcon#*before write, iclass 27, count 0 2006.257.02:59:51.55#ibcon#enter sib2, iclass 27, count 0 2006.257.02:59:51.55#ibcon#flushed, iclass 27, count 0 2006.257.02:59:51.55#ibcon#about to write, iclass 27, count 0 2006.257.02:59:51.55#ibcon#wrote, iclass 27, count 0 2006.257.02:59:51.55#ibcon#about to read 3, iclass 27, count 0 2006.257.02:59:51.59#ibcon#read 3, iclass 27, count 0 2006.257.02:59:51.59#ibcon#about to read 4, iclass 27, count 0 2006.257.02:59:51.59#ibcon#read 4, iclass 27, count 0 2006.257.02:59:51.59#ibcon#about to read 5, iclass 27, count 0 2006.257.02:59:51.59#ibcon#read 5, iclass 27, count 0 2006.257.02:59:51.59#ibcon#about to read 6, iclass 27, count 0 2006.257.02:59:51.59#ibcon#read 6, iclass 27, count 0 2006.257.02:59:51.59#ibcon#end of sib2, iclass 27, count 0 2006.257.02:59:51.59#ibcon#*after write, iclass 27, count 0 2006.257.02:59:51.59#ibcon#*before return 0, iclass 27, count 0 2006.257.02:59:51.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:51.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.02:59:51.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.02:59:51.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.02:59:51.59$vck44/vb=7,4 2006.257.02:59:51.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.02:59:51.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.02:59:51.59#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:51.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:51.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:51.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:51.65#ibcon#enter wrdev, iclass 29, count 2 2006.257.02:59:51.65#ibcon#first serial, iclass 29, count 2 2006.257.02:59:51.65#ibcon#enter sib2, iclass 29, count 2 2006.257.02:59:51.65#ibcon#flushed, iclass 29, count 2 2006.257.02:59:51.65#ibcon#about to write, iclass 29, count 2 2006.257.02:59:51.65#ibcon#wrote, iclass 29, count 2 2006.257.02:59:51.65#ibcon#about to read 3, iclass 29, count 2 2006.257.02:59:51.67#ibcon#read 3, iclass 29, count 2 2006.257.02:59:51.67#ibcon#about to read 4, iclass 29, count 2 2006.257.02:59:51.67#ibcon#read 4, iclass 29, count 2 2006.257.02:59:51.67#ibcon#about to read 5, iclass 29, count 2 2006.257.02:59:51.67#ibcon#read 5, iclass 29, count 2 2006.257.02:59:51.67#ibcon#about to read 6, iclass 29, count 2 2006.257.02:59:51.67#ibcon#read 6, iclass 29, count 2 2006.257.02:59:51.67#ibcon#end of sib2, iclass 29, count 2 2006.257.02:59:51.67#ibcon#*mode == 0, iclass 29, count 2 2006.257.02:59:51.67#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.02:59:51.67#ibcon#[27=AT07-04\r\n] 2006.257.02:59:51.67#ibcon#*before write, iclass 29, count 2 2006.257.02:59:51.67#ibcon#enter sib2, iclass 29, count 2 2006.257.02:59:51.67#ibcon#flushed, iclass 29, count 2 2006.257.02:59:51.67#ibcon#about to write, iclass 29, count 2 2006.257.02:59:51.67#ibcon#wrote, iclass 29, count 2 2006.257.02:59:51.67#ibcon#about to read 3, iclass 29, count 2 2006.257.02:59:51.70#ibcon#read 3, iclass 29, count 2 2006.257.02:59:51.70#ibcon#about to read 4, iclass 29, count 2 2006.257.02:59:51.70#ibcon#read 4, iclass 29, count 2 2006.257.02:59:51.70#ibcon#about to read 5, iclass 29, count 2 2006.257.02:59:51.70#ibcon#read 5, iclass 29, count 2 2006.257.02:59:51.70#ibcon#about to read 6, iclass 29, count 2 2006.257.02:59:51.70#ibcon#read 6, iclass 29, count 2 2006.257.02:59:51.70#ibcon#end of sib2, iclass 29, count 2 2006.257.02:59:51.70#ibcon#*after write, iclass 29, count 2 2006.257.02:59:51.70#ibcon#*before return 0, iclass 29, count 2 2006.257.02:59:51.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:51.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.02:59:51.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.02:59:51.70#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:51.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:51.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:51.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:51.82#ibcon#enter wrdev, iclass 29, count 0 2006.257.02:59:51.82#ibcon#first serial, iclass 29, count 0 2006.257.02:59:51.82#ibcon#enter sib2, iclass 29, count 0 2006.257.02:59:51.82#ibcon#flushed, iclass 29, count 0 2006.257.02:59:51.82#ibcon#about to write, iclass 29, count 0 2006.257.02:59:51.82#ibcon#wrote, iclass 29, count 0 2006.257.02:59:51.82#ibcon#about to read 3, iclass 29, count 0 2006.257.02:59:51.84#ibcon#read 3, iclass 29, count 0 2006.257.02:59:51.84#ibcon#about to read 4, iclass 29, count 0 2006.257.02:59:51.84#ibcon#read 4, iclass 29, count 0 2006.257.02:59:51.84#ibcon#about to read 5, iclass 29, count 0 2006.257.02:59:51.84#ibcon#read 5, iclass 29, count 0 2006.257.02:59:51.84#ibcon#about to read 6, iclass 29, count 0 2006.257.02:59:51.84#ibcon#read 6, iclass 29, count 0 2006.257.02:59:51.84#ibcon#end of sib2, iclass 29, count 0 2006.257.02:59:51.84#ibcon#*mode == 0, iclass 29, count 0 2006.257.02:59:51.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.02:59:51.84#ibcon#[27=USB\r\n] 2006.257.02:59:51.84#ibcon#*before write, iclass 29, count 0 2006.257.02:59:51.84#ibcon#enter sib2, iclass 29, count 0 2006.257.02:59:51.84#ibcon#flushed, iclass 29, count 0 2006.257.02:59:51.84#ibcon#about to write, iclass 29, count 0 2006.257.02:59:51.84#ibcon#wrote, iclass 29, count 0 2006.257.02:59:51.84#ibcon#about to read 3, iclass 29, count 0 2006.257.02:59:51.87#ibcon#read 3, iclass 29, count 0 2006.257.02:59:51.87#ibcon#about to read 4, iclass 29, count 0 2006.257.02:59:51.87#ibcon#read 4, iclass 29, count 0 2006.257.02:59:51.87#ibcon#about to read 5, iclass 29, count 0 2006.257.02:59:51.87#ibcon#read 5, iclass 29, count 0 2006.257.02:59:51.87#ibcon#about to read 6, iclass 29, count 0 2006.257.02:59:51.87#ibcon#read 6, iclass 29, count 0 2006.257.02:59:51.87#ibcon#end of sib2, iclass 29, count 0 2006.257.02:59:51.87#ibcon#*after write, iclass 29, count 0 2006.257.02:59:51.87#ibcon#*before return 0, iclass 29, count 0 2006.257.02:59:51.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:51.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.02:59:51.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.02:59:51.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.02:59:51.87$vck44/vblo=8,744.99 2006.257.02:59:51.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.02:59:51.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.02:59:51.87#ibcon#ireg 17 cls_cnt 0 2006.257.02:59:51.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:51.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:51.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:51.87#ibcon#enter wrdev, iclass 31, count 0 2006.257.02:59:51.87#ibcon#first serial, iclass 31, count 0 2006.257.02:59:51.87#ibcon#enter sib2, iclass 31, count 0 2006.257.02:59:51.87#ibcon#flushed, iclass 31, count 0 2006.257.02:59:51.87#ibcon#about to write, iclass 31, count 0 2006.257.02:59:51.87#ibcon#wrote, iclass 31, count 0 2006.257.02:59:51.87#ibcon#about to read 3, iclass 31, count 0 2006.257.02:59:51.89#ibcon#read 3, iclass 31, count 0 2006.257.02:59:51.89#ibcon#about to read 4, iclass 31, count 0 2006.257.02:59:51.89#ibcon#read 4, iclass 31, count 0 2006.257.02:59:51.89#ibcon#about to read 5, iclass 31, count 0 2006.257.02:59:51.89#ibcon#read 5, iclass 31, count 0 2006.257.02:59:51.89#ibcon#about to read 6, iclass 31, count 0 2006.257.02:59:51.89#ibcon#read 6, iclass 31, count 0 2006.257.02:59:51.89#ibcon#end of sib2, iclass 31, count 0 2006.257.02:59:51.89#ibcon#*mode == 0, iclass 31, count 0 2006.257.02:59:51.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.02:59:51.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.02:59:51.89#ibcon#*before write, iclass 31, count 0 2006.257.02:59:51.89#ibcon#enter sib2, iclass 31, count 0 2006.257.02:59:51.89#ibcon#flushed, iclass 31, count 0 2006.257.02:59:51.89#ibcon#about to write, iclass 31, count 0 2006.257.02:59:51.89#ibcon#wrote, iclass 31, count 0 2006.257.02:59:51.89#ibcon#about to read 3, iclass 31, count 0 2006.257.02:59:51.93#ibcon#read 3, iclass 31, count 0 2006.257.02:59:51.93#ibcon#about to read 4, iclass 31, count 0 2006.257.02:59:51.93#ibcon#read 4, iclass 31, count 0 2006.257.02:59:51.93#ibcon#about to read 5, iclass 31, count 0 2006.257.02:59:51.93#ibcon#read 5, iclass 31, count 0 2006.257.02:59:51.93#ibcon#about to read 6, iclass 31, count 0 2006.257.02:59:51.93#ibcon#read 6, iclass 31, count 0 2006.257.02:59:51.93#ibcon#end of sib2, iclass 31, count 0 2006.257.02:59:51.93#ibcon#*after write, iclass 31, count 0 2006.257.02:59:51.93#ibcon#*before return 0, iclass 31, count 0 2006.257.02:59:51.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:51.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.02:59:51.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.02:59:51.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.02:59:51.93$vck44/vb=8,4 2006.257.02:59:51.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.02:59:51.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.02:59:51.93#ibcon#ireg 11 cls_cnt 2 2006.257.02:59:51.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:51.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:51.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:51.99#ibcon#enter wrdev, iclass 33, count 2 2006.257.02:59:51.99#ibcon#first serial, iclass 33, count 2 2006.257.02:59:51.99#ibcon#enter sib2, iclass 33, count 2 2006.257.02:59:51.99#ibcon#flushed, iclass 33, count 2 2006.257.02:59:51.99#ibcon#about to write, iclass 33, count 2 2006.257.02:59:51.99#ibcon#wrote, iclass 33, count 2 2006.257.02:59:51.99#ibcon#about to read 3, iclass 33, count 2 2006.257.02:59:52.01#ibcon#read 3, iclass 33, count 2 2006.257.02:59:52.01#ibcon#about to read 4, iclass 33, count 2 2006.257.02:59:52.01#ibcon#read 4, iclass 33, count 2 2006.257.02:59:52.01#ibcon#about to read 5, iclass 33, count 2 2006.257.02:59:52.01#ibcon#read 5, iclass 33, count 2 2006.257.02:59:52.01#ibcon#about to read 6, iclass 33, count 2 2006.257.02:59:52.01#ibcon#read 6, iclass 33, count 2 2006.257.02:59:52.01#ibcon#end of sib2, iclass 33, count 2 2006.257.02:59:52.01#ibcon#*mode == 0, iclass 33, count 2 2006.257.02:59:52.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.02:59:52.01#ibcon#[27=AT08-04\r\n] 2006.257.02:59:52.01#ibcon#*before write, iclass 33, count 2 2006.257.02:59:52.01#ibcon#enter sib2, iclass 33, count 2 2006.257.02:59:52.01#ibcon#flushed, iclass 33, count 2 2006.257.02:59:52.01#ibcon#about to write, iclass 33, count 2 2006.257.02:59:52.01#ibcon#wrote, iclass 33, count 2 2006.257.02:59:52.01#ibcon#about to read 3, iclass 33, count 2 2006.257.02:59:52.04#ibcon#read 3, iclass 33, count 2 2006.257.02:59:52.04#ibcon#about to read 4, iclass 33, count 2 2006.257.02:59:52.04#ibcon#read 4, iclass 33, count 2 2006.257.02:59:52.04#ibcon#about to read 5, iclass 33, count 2 2006.257.02:59:52.04#ibcon#read 5, iclass 33, count 2 2006.257.02:59:52.04#ibcon#about to read 6, iclass 33, count 2 2006.257.02:59:52.04#ibcon#read 6, iclass 33, count 2 2006.257.02:59:52.04#ibcon#end of sib2, iclass 33, count 2 2006.257.02:59:52.04#ibcon#*after write, iclass 33, count 2 2006.257.02:59:52.04#ibcon#*before return 0, iclass 33, count 2 2006.257.02:59:52.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:52.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.02:59:52.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.02:59:52.04#ibcon#ireg 7 cls_cnt 0 2006.257.02:59:52.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:52.16#abcon#<5=/15 2.5 5.6 18.92 901012.5\r\n> 2006.257.02:59:52.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:52.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:52.16#ibcon#enter wrdev, iclass 33, count 0 2006.257.02:59:52.16#ibcon#first serial, iclass 33, count 0 2006.257.02:59:52.16#ibcon#enter sib2, iclass 33, count 0 2006.257.02:59:52.16#ibcon#flushed, iclass 33, count 0 2006.257.02:59:52.16#ibcon#about to write, iclass 33, count 0 2006.257.02:59:52.16#ibcon#wrote, iclass 33, count 0 2006.257.02:59:52.16#ibcon#about to read 3, iclass 33, count 0 2006.257.02:59:52.18#ibcon#read 3, iclass 33, count 0 2006.257.02:59:52.18#ibcon#about to read 4, iclass 33, count 0 2006.257.02:59:52.18#ibcon#read 4, iclass 33, count 0 2006.257.02:59:52.18#ibcon#about to read 5, iclass 33, count 0 2006.257.02:59:52.18#ibcon#read 5, iclass 33, count 0 2006.257.02:59:52.18#ibcon#about to read 6, iclass 33, count 0 2006.257.02:59:52.18#ibcon#read 6, iclass 33, count 0 2006.257.02:59:52.18#ibcon#end of sib2, iclass 33, count 0 2006.257.02:59:52.18#ibcon#*mode == 0, iclass 33, count 0 2006.257.02:59:52.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.02:59:52.18#ibcon#[27=USB\r\n] 2006.257.02:59:52.18#ibcon#*before write, iclass 33, count 0 2006.257.02:59:52.18#ibcon#enter sib2, iclass 33, count 0 2006.257.02:59:52.18#ibcon#flushed, iclass 33, count 0 2006.257.02:59:52.18#ibcon#about to write, iclass 33, count 0 2006.257.02:59:52.18#ibcon#wrote, iclass 33, count 0 2006.257.02:59:52.18#ibcon#about to read 3, iclass 33, count 0 2006.257.02:59:52.18#abcon#{5=INTERFACE CLEAR} 2006.257.02:59:52.21#ibcon#read 3, iclass 33, count 0 2006.257.02:59:52.21#ibcon#about to read 4, iclass 33, count 0 2006.257.02:59:52.21#ibcon#read 4, iclass 33, count 0 2006.257.02:59:52.21#ibcon#about to read 5, iclass 33, count 0 2006.257.02:59:52.21#ibcon#read 5, iclass 33, count 0 2006.257.02:59:52.21#ibcon#about to read 6, iclass 33, count 0 2006.257.02:59:52.21#ibcon#read 6, iclass 33, count 0 2006.257.02:59:52.21#ibcon#end of sib2, iclass 33, count 0 2006.257.02:59:52.21#ibcon#*after write, iclass 33, count 0 2006.257.02:59:52.21#ibcon#*before return 0, iclass 33, count 0 2006.257.02:59:52.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:52.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.02:59:52.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.02:59:52.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.02:59:52.21$vck44/vabw=wide 2006.257.02:59:52.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.02:59:52.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.02:59:52.21#ibcon#ireg 8 cls_cnt 0 2006.257.02:59:52.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:59:52.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:59:52.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:59:52.21#ibcon#enter wrdev, iclass 38, count 0 2006.257.02:59:52.21#ibcon#first serial, iclass 38, count 0 2006.257.02:59:52.21#ibcon#enter sib2, iclass 38, count 0 2006.257.02:59:52.21#ibcon#flushed, iclass 38, count 0 2006.257.02:59:52.21#ibcon#about to write, iclass 38, count 0 2006.257.02:59:52.21#ibcon#wrote, iclass 38, count 0 2006.257.02:59:52.21#ibcon#about to read 3, iclass 38, count 0 2006.257.02:59:52.23#ibcon#read 3, iclass 38, count 0 2006.257.02:59:52.23#ibcon#about to read 4, iclass 38, count 0 2006.257.02:59:52.23#ibcon#read 4, iclass 38, count 0 2006.257.02:59:52.23#ibcon#about to read 5, iclass 38, count 0 2006.257.02:59:52.23#ibcon#read 5, iclass 38, count 0 2006.257.02:59:52.23#ibcon#about to read 6, iclass 38, count 0 2006.257.02:59:52.23#ibcon#read 6, iclass 38, count 0 2006.257.02:59:52.23#ibcon#end of sib2, iclass 38, count 0 2006.257.02:59:52.23#ibcon#*mode == 0, iclass 38, count 0 2006.257.02:59:52.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.02:59:52.23#ibcon#[25=BW32\r\n] 2006.257.02:59:52.23#ibcon#*before write, iclass 38, count 0 2006.257.02:59:52.23#ibcon#enter sib2, iclass 38, count 0 2006.257.02:59:52.23#ibcon#flushed, iclass 38, count 0 2006.257.02:59:52.23#ibcon#about to write, iclass 38, count 0 2006.257.02:59:52.23#ibcon#wrote, iclass 38, count 0 2006.257.02:59:52.23#ibcon#about to read 3, iclass 38, count 0 2006.257.02:59:52.24#abcon#[5=S1D000X0/0*\r\n] 2006.257.02:59:52.26#ibcon#read 3, iclass 38, count 0 2006.257.02:59:52.26#ibcon#about to read 4, iclass 38, count 0 2006.257.02:59:52.26#ibcon#read 4, iclass 38, count 0 2006.257.02:59:52.26#ibcon#about to read 5, iclass 38, count 0 2006.257.02:59:52.26#ibcon#read 5, iclass 38, count 0 2006.257.02:59:52.26#ibcon#about to read 6, iclass 38, count 0 2006.257.02:59:52.26#ibcon#read 6, iclass 38, count 0 2006.257.02:59:52.26#ibcon#end of sib2, iclass 38, count 0 2006.257.02:59:52.26#ibcon#*after write, iclass 38, count 0 2006.257.02:59:52.26#ibcon#*before return 0, iclass 38, count 0 2006.257.02:59:52.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:59:52.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.02:59:52.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.02:59:52.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.02:59:52.26$vck44/vbbw=wide 2006.257.02:59:52.26#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.02:59:52.26#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.02:59:52.26#ibcon#ireg 8 cls_cnt 0 2006.257.02:59:52.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:59:52.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:59:52.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:59:52.33#ibcon#enter wrdev, iclass 3, count 0 2006.257.02:59:52.33#ibcon#first serial, iclass 3, count 0 2006.257.02:59:52.33#ibcon#enter sib2, iclass 3, count 0 2006.257.02:59:52.33#ibcon#flushed, iclass 3, count 0 2006.257.02:59:52.33#ibcon#about to write, iclass 3, count 0 2006.257.02:59:52.33#ibcon#wrote, iclass 3, count 0 2006.257.02:59:52.33#ibcon#about to read 3, iclass 3, count 0 2006.257.02:59:52.35#ibcon#read 3, iclass 3, count 0 2006.257.02:59:52.35#ibcon#about to read 4, iclass 3, count 0 2006.257.02:59:52.35#ibcon#read 4, iclass 3, count 0 2006.257.02:59:52.35#ibcon#about to read 5, iclass 3, count 0 2006.257.02:59:52.35#ibcon#read 5, iclass 3, count 0 2006.257.02:59:52.35#ibcon#about to read 6, iclass 3, count 0 2006.257.02:59:52.35#ibcon#read 6, iclass 3, count 0 2006.257.02:59:52.35#ibcon#end of sib2, iclass 3, count 0 2006.257.02:59:52.35#ibcon#*mode == 0, iclass 3, count 0 2006.257.02:59:52.35#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.02:59:52.35#ibcon#[27=BW32\r\n] 2006.257.02:59:52.35#ibcon#*before write, iclass 3, count 0 2006.257.02:59:52.35#ibcon#enter sib2, iclass 3, count 0 2006.257.02:59:52.35#ibcon#flushed, iclass 3, count 0 2006.257.02:59:52.35#ibcon#about to write, iclass 3, count 0 2006.257.02:59:52.35#ibcon#wrote, iclass 3, count 0 2006.257.02:59:52.35#ibcon#about to read 3, iclass 3, count 0 2006.257.02:59:52.38#ibcon#read 3, iclass 3, count 0 2006.257.02:59:52.38#ibcon#about to read 4, iclass 3, count 0 2006.257.02:59:52.38#ibcon#read 4, iclass 3, count 0 2006.257.02:59:52.38#ibcon#about to read 5, iclass 3, count 0 2006.257.02:59:52.38#ibcon#read 5, iclass 3, count 0 2006.257.02:59:52.38#ibcon#about to read 6, iclass 3, count 0 2006.257.02:59:52.38#ibcon#read 6, iclass 3, count 0 2006.257.02:59:52.38#ibcon#end of sib2, iclass 3, count 0 2006.257.02:59:52.38#ibcon#*after write, iclass 3, count 0 2006.257.02:59:52.38#ibcon#*before return 0, iclass 3, count 0 2006.257.02:59:52.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:59:52.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.02:59:52.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.02:59:52.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.02:59:52.38$setupk4/ifdk4 2006.257.02:59:52.38$ifdk4/lo= 2006.257.02:59:52.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.02:59:52.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.02:59:52.38$ifdk4/patch= 2006.257.02:59:52.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.02:59:52.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.02:59:52.38$setupk4/!*+20s 2006.257.03:00:02.33#abcon#<5=/15 2.4 5.6 18.93 901012.5\r\n> 2006.257.03:00:02.35#abcon#{5=INTERFACE CLEAR} 2006.257.03:00:02.41#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:00:06.88$setupk4/"tpicd 2006.257.03:00:06.88$setupk4/echo=off 2006.257.03:00:06.88$setupk4/xlog=off 2006.257.03:00:06.88:!2006.257.03:01:30 2006.257.03:00:19.14#trakl#Source acquired 2006.257.03:00:19.14#flagr#flagr/antenna,acquired 2006.257.03:01:30.00:preob 2006.257.03:01:30.13/onsource/TRACKING 2006.257.03:01:30.13:!2006.257.03:01:40 2006.257.03:01:40.00:"tape 2006.257.03:01:40.00:"st=record 2006.257.03:01:40.00:data_valid=on 2006.257.03:01:40.00:midob 2006.257.03:01:40.13/onsource/TRACKING 2006.257.03:01:40.13/wx/18.98,1012.5,92 2006.257.03:01:40.20/cable/+6.4866E-03 2006.257.03:01:41.29/va/01,08,usb,yes,31,34 2006.257.03:01:41.29/va/02,07,usb,yes,34,35 2006.257.03:01:41.29/va/03,08,usb,yes,30,32 2006.257.03:01:41.29/va/04,07,usb,yes,35,37 2006.257.03:01:41.29/va/05,04,usb,yes,31,32 2006.257.03:01:41.29/va/06,04,usb,yes,35,35 2006.257.03:01:41.29/va/07,04,usb,yes,36,36 2006.257.03:01:41.29/va/08,04,usb,yes,30,37 2006.257.03:01:41.52/valo/01,524.99,yes,locked 2006.257.03:01:41.52/valo/02,534.99,yes,locked 2006.257.03:01:41.52/valo/03,564.99,yes,locked 2006.257.03:01:41.52/valo/04,624.99,yes,locked 2006.257.03:01:41.52/valo/05,734.99,yes,locked 2006.257.03:01:41.52/valo/06,814.99,yes,locked 2006.257.03:01:41.52/valo/07,864.99,yes,locked 2006.257.03:01:41.52/valo/08,884.99,yes,locked 2006.257.03:01:42.61/vb/01,04,usb,yes,30,28 2006.257.03:01:42.61/vb/02,05,usb,yes,29,29 2006.257.03:01:42.61/vb/03,04,usb,yes,30,33 2006.257.03:01:42.61/vb/04,05,usb,yes,30,29 2006.257.03:01:42.61/vb/05,04,usb,yes,26,29 2006.257.03:01:42.61/vb/06,04,usb,yes,31,27 2006.257.03:01:42.61/vb/07,04,usb,yes,31,31 2006.257.03:01:42.61/vb/08,04,usb,yes,28,32 2006.257.03:01:42.84/vblo/01,629.99,yes,locked 2006.257.03:01:42.84/vblo/02,634.99,yes,locked 2006.257.03:01:42.84/vblo/03,649.99,yes,locked 2006.257.03:01:42.84/vblo/04,679.99,yes,locked 2006.257.03:01:42.84/vblo/05,709.99,yes,locked 2006.257.03:01:42.84/vblo/06,719.99,yes,locked 2006.257.03:01:42.84/vblo/07,734.99,yes,locked 2006.257.03:01:42.84/vblo/08,744.99,yes,locked 2006.257.03:01:42.99/vabw/8 2006.257.03:01:43.14/vbbw/8 2006.257.03:01:43.23/xfe/off,on,15.5 2006.257.03:01:43.60/ifatt/23,28,28,28 2006.257.03:01:44.08/fmout-gps/S +4.55E-07 2006.257.03:01:44.12:!2006.257.03:06:40 2006.257.03:04:10.14#trakl#Off source 2006.257.03:04:10.14?ERROR st -7 Antenna off-source! 2006.257.03:04:10.14#trakl#az 260.466 el 47.390 azerr*cos(el) -0.0013 elerr -0.0182 2006.257.03:04:12.15#flagr#flagr/antenna,off-source 2006.257.03:04:17.14#trakl#Source re-acquired 2006.257.03:04:18.15#flagr#flagr/antenna,re-acquired 2006.257.03:06:40.01:data_valid=off 2006.257.03:06:40.02:"et 2006.257.03:06:40.02:!+3s 2006.257.03:06:43.04:"tape 2006.257.03:06:43.05:postob 2006.257.03:06:43.12/cable/+6.4872E-03 2006.257.03:06:43.13/wx/19.16,1012.3,91 2006.257.03:06:43.20/fmout-gps/S +4.54E-07 2006.257.03:06:43.20:scan_name=257-0310,jd0609,40 2006.257.03:06:43.21:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.257.03:06:44.14#flagr#flagr/antenna,new-source 2006.257.03:06:44.15:checkk5 2006.257.03:06:44.52/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:06:44.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:06:45.28/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:06:45.65/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:06:46.01/chk_obsdata//k5ts1/T2570301??a.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.257.03:06:46.37/chk_obsdata//k5ts2/T2570301??b.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.257.03:06:46.75/chk_obsdata//k5ts3/T2570301??c.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.257.03:06:47.11/chk_obsdata//k5ts4/T2570301??d.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.257.03:06:47.80/k5log//k5ts1_log_newline 2006.257.03:06:48.47/k5log//k5ts2_log_newline 2006.257.03:06:49.19/k5log//k5ts3_log_newline 2006.257.03:06:49.87/k5log//k5ts4_log_newline 2006.257.03:06:49.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:06:49.90:setupk4=1 2006.257.03:06:49.90$setupk4/echo=on 2006.257.03:06:49.90$setupk4/pcalon 2006.257.03:06:49.90$pcalon/"no phase cal control is implemented here 2006.257.03:06:49.90$setupk4/"tpicd=stop 2006.257.03:06:49.90$setupk4/"rec=synch_on 2006.257.03:06:49.90$setupk4/"rec_mode=128 2006.257.03:06:49.90$setupk4/!* 2006.257.03:06:49.90$setupk4/recpk4 2006.257.03:06:49.90$recpk4/recpatch= 2006.257.03:06:49.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:06:49.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:06:49.90$setupk4/vck44 2006.257.03:06:49.90$vck44/valo=1,524.99 2006.257.03:06:49.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.03:06:49.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.03:06:49.90#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:49.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:49.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:49.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:49.90#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:06:49.90#ibcon#first serial, iclass 32, count 0 2006.257.03:06:49.90#ibcon#enter sib2, iclass 32, count 0 2006.257.03:06:49.90#ibcon#flushed, iclass 32, count 0 2006.257.03:06:49.90#ibcon#about to write, iclass 32, count 0 2006.257.03:06:49.90#ibcon#wrote, iclass 32, count 0 2006.257.03:06:49.90#ibcon#about to read 3, iclass 32, count 0 2006.257.03:06:49.93#ibcon#read 3, iclass 32, count 0 2006.257.03:06:49.93#ibcon#about to read 4, iclass 32, count 0 2006.257.03:06:49.93#ibcon#read 4, iclass 32, count 0 2006.257.03:06:49.93#ibcon#about to read 5, iclass 32, count 0 2006.257.03:06:49.93#ibcon#read 5, iclass 32, count 0 2006.257.03:06:49.93#ibcon#about to read 6, iclass 32, count 0 2006.257.03:06:49.93#ibcon#read 6, iclass 32, count 0 2006.257.03:06:49.93#ibcon#end of sib2, iclass 32, count 0 2006.257.03:06:49.93#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:06:49.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:06:49.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:06:49.93#ibcon#*before write, iclass 32, count 0 2006.257.03:06:49.93#ibcon#enter sib2, iclass 32, count 0 2006.257.03:06:49.93#ibcon#flushed, iclass 32, count 0 2006.257.03:06:49.93#ibcon#about to write, iclass 32, count 0 2006.257.03:06:49.93#ibcon#wrote, iclass 32, count 0 2006.257.03:06:49.93#ibcon#about to read 3, iclass 32, count 0 2006.257.03:06:49.98#ibcon#read 3, iclass 32, count 0 2006.257.03:06:49.98#ibcon#about to read 4, iclass 32, count 0 2006.257.03:06:49.98#ibcon#read 4, iclass 32, count 0 2006.257.03:06:49.98#ibcon#about to read 5, iclass 32, count 0 2006.257.03:06:49.98#ibcon#read 5, iclass 32, count 0 2006.257.03:06:49.98#ibcon#about to read 6, iclass 32, count 0 2006.257.03:06:49.98#ibcon#read 6, iclass 32, count 0 2006.257.03:06:49.98#ibcon#end of sib2, iclass 32, count 0 2006.257.03:06:49.98#ibcon#*after write, iclass 32, count 0 2006.257.03:06:49.98#ibcon#*before return 0, iclass 32, count 0 2006.257.03:06:49.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:49.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:49.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:06:49.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:06:49.98$vck44/va=1,8 2006.257.03:06:49.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.03:06:49.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.03:06:49.98#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:49.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:49.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:49.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:49.98#ibcon#enter wrdev, iclass 34, count 2 2006.257.03:06:49.98#ibcon#first serial, iclass 34, count 2 2006.257.03:06:49.98#ibcon#enter sib2, iclass 34, count 2 2006.257.03:06:49.98#ibcon#flushed, iclass 34, count 2 2006.257.03:06:49.98#ibcon#about to write, iclass 34, count 2 2006.257.03:06:49.98#ibcon#wrote, iclass 34, count 2 2006.257.03:06:49.98#ibcon#about to read 3, iclass 34, count 2 2006.257.03:06:50.00#ibcon#read 3, iclass 34, count 2 2006.257.03:06:50.00#ibcon#about to read 4, iclass 34, count 2 2006.257.03:06:50.00#ibcon#read 4, iclass 34, count 2 2006.257.03:06:50.00#ibcon#about to read 5, iclass 34, count 2 2006.257.03:06:50.00#ibcon#read 5, iclass 34, count 2 2006.257.03:06:50.00#ibcon#about to read 6, iclass 34, count 2 2006.257.03:06:50.00#ibcon#read 6, iclass 34, count 2 2006.257.03:06:50.00#ibcon#end of sib2, iclass 34, count 2 2006.257.03:06:50.00#ibcon#*mode == 0, iclass 34, count 2 2006.257.03:06:50.00#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.03:06:50.00#ibcon#[25=AT01-08\r\n] 2006.257.03:06:50.00#ibcon#*before write, iclass 34, count 2 2006.257.03:06:50.00#ibcon#enter sib2, iclass 34, count 2 2006.257.03:06:50.00#ibcon#flushed, iclass 34, count 2 2006.257.03:06:50.00#ibcon#about to write, iclass 34, count 2 2006.257.03:06:50.00#ibcon#wrote, iclass 34, count 2 2006.257.03:06:50.01#ibcon#about to read 3, iclass 34, count 2 2006.257.03:06:50.03#ibcon#read 3, iclass 34, count 2 2006.257.03:06:50.03#ibcon#about to read 4, iclass 34, count 2 2006.257.03:06:50.03#ibcon#read 4, iclass 34, count 2 2006.257.03:06:50.03#ibcon#about to read 5, iclass 34, count 2 2006.257.03:06:50.03#ibcon#read 5, iclass 34, count 2 2006.257.03:06:50.03#ibcon#about to read 6, iclass 34, count 2 2006.257.03:06:50.03#ibcon#read 6, iclass 34, count 2 2006.257.03:06:50.03#ibcon#end of sib2, iclass 34, count 2 2006.257.03:06:50.03#ibcon#*after write, iclass 34, count 2 2006.257.03:06:50.03#ibcon#*before return 0, iclass 34, count 2 2006.257.03:06:50.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:50.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:50.03#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.03:06:50.03#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:50.03#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:50.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:50.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:50.15#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:06:50.15#ibcon#first serial, iclass 34, count 0 2006.257.03:06:50.15#ibcon#enter sib2, iclass 34, count 0 2006.257.03:06:50.15#ibcon#flushed, iclass 34, count 0 2006.257.03:06:50.15#ibcon#about to write, iclass 34, count 0 2006.257.03:06:50.15#ibcon#wrote, iclass 34, count 0 2006.257.03:06:50.15#ibcon#about to read 3, iclass 34, count 0 2006.257.03:06:50.17#ibcon#read 3, iclass 34, count 0 2006.257.03:06:50.17#ibcon#about to read 4, iclass 34, count 0 2006.257.03:06:50.17#ibcon#read 4, iclass 34, count 0 2006.257.03:06:50.17#ibcon#about to read 5, iclass 34, count 0 2006.257.03:06:50.17#ibcon#read 5, iclass 34, count 0 2006.257.03:06:50.17#ibcon#about to read 6, iclass 34, count 0 2006.257.03:06:50.17#ibcon#read 6, iclass 34, count 0 2006.257.03:06:50.17#ibcon#end of sib2, iclass 34, count 0 2006.257.03:06:50.17#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:06:50.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:06:50.17#ibcon#[25=USB\r\n] 2006.257.03:06:50.17#ibcon#*before write, iclass 34, count 0 2006.257.03:06:50.17#ibcon#enter sib2, iclass 34, count 0 2006.257.03:06:50.17#ibcon#flushed, iclass 34, count 0 2006.257.03:06:50.17#ibcon#about to write, iclass 34, count 0 2006.257.03:06:50.17#ibcon#wrote, iclass 34, count 0 2006.257.03:06:50.17#ibcon#about to read 3, iclass 34, count 0 2006.257.03:06:50.20#ibcon#read 3, iclass 34, count 0 2006.257.03:06:50.20#ibcon#about to read 4, iclass 34, count 0 2006.257.03:06:50.20#ibcon#read 4, iclass 34, count 0 2006.257.03:06:50.20#ibcon#about to read 5, iclass 34, count 0 2006.257.03:06:50.20#ibcon#read 5, iclass 34, count 0 2006.257.03:06:50.20#ibcon#about to read 6, iclass 34, count 0 2006.257.03:06:50.20#ibcon#read 6, iclass 34, count 0 2006.257.03:06:50.20#ibcon#end of sib2, iclass 34, count 0 2006.257.03:06:50.20#ibcon#*after write, iclass 34, count 0 2006.257.03:06:50.20#ibcon#*before return 0, iclass 34, count 0 2006.257.03:06:50.20#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:50.20#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:50.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:06:50.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:06:50.20$vck44/valo=2,534.99 2006.257.03:06:50.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.03:06:50.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.03:06:50.20#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:50.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:50.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:50.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:50.20#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:06:50.20#ibcon#first serial, iclass 36, count 0 2006.257.03:06:50.20#ibcon#enter sib2, iclass 36, count 0 2006.257.03:06:50.20#ibcon#flushed, iclass 36, count 0 2006.257.03:06:50.20#ibcon#about to write, iclass 36, count 0 2006.257.03:06:50.20#ibcon#wrote, iclass 36, count 0 2006.257.03:06:50.20#ibcon#about to read 3, iclass 36, count 0 2006.257.03:06:50.22#ibcon#read 3, iclass 36, count 0 2006.257.03:06:50.22#ibcon#about to read 4, iclass 36, count 0 2006.257.03:06:50.22#ibcon#read 4, iclass 36, count 0 2006.257.03:06:50.22#ibcon#about to read 5, iclass 36, count 0 2006.257.03:06:50.22#ibcon#read 5, iclass 36, count 0 2006.257.03:06:50.22#ibcon#about to read 6, iclass 36, count 0 2006.257.03:06:50.22#ibcon#read 6, iclass 36, count 0 2006.257.03:06:50.22#ibcon#end of sib2, iclass 36, count 0 2006.257.03:06:50.22#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:06:50.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:06:50.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:06:50.22#ibcon#*before write, iclass 36, count 0 2006.257.03:06:50.22#ibcon#enter sib2, iclass 36, count 0 2006.257.03:06:50.22#ibcon#flushed, iclass 36, count 0 2006.257.03:06:50.22#ibcon#about to write, iclass 36, count 0 2006.257.03:06:50.22#ibcon#wrote, iclass 36, count 0 2006.257.03:06:50.22#ibcon#about to read 3, iclass 36, count 0 2006.257.03:06:50.26#ibcon#read 3, iclass 36, count 0 2006.257.03:06:50.26#ibcon#about to read 4, iclass 36, count 0 2006.257.03:06:50.26#ibcon#read 4, iclass 36, count 0 2006.257.03:06:50.26#ibcon#about to read 5, iclass 36, count 0 2006.257.03:06:50.26#ibcon#read 5, iclass 36, count 0 2006.257.03:06:50.26#ibcon#about to read 6, iclass 36, count 0 2006.257.03:06:50.26#ibcon#read 6, iclass 36, count 0 2006.257.03:06:50.26#ibcon#end of sib2, iclass 36, count 0 2006.257.03:06:50.26#ibcon#*after write, iclass 36, count 0 2006.257.03:06:50.26#ibcon#*before return 0, iclass 36, count 0 2006.257.03:06:50.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:50.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:50.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:06:50.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:06:50.26$vck44/va=2,7 2006.257.03:06:50.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.03:06:50.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.03:06:50.26#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:50.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:50.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:50.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:50.32#ibcon#enter wrdev, iclass 38, count 2 2006.257.03:06:50.32#ibcon#first serial, iclass 38, count 2 2006.257.03:06:50.32#ibcon#enter sib2, iclass 38, count 2 2006.257.03:06:50.32#ibcon#flushed, iclass 38, count 2 2006.257.03:06:50.32#ibcon#about to write, iclass 38, count 2 2006.257.03:06:50.32#ibcon#wrote, iclass 38, count 2 2006.257.03:06:50.32#ibcon#about to read 3, iclass 38, count 2 2006.257.03:06:50.34#ibcon#read 3, iclass 38, count 2 2006.257.03:06:50.34#ibcon#about to read 4, iclass 38, count 2 2006.257.03:06:50.34#ibcon#read 4, iclass 38, count 2 2006.257.03:06:50.34#ibcon#about to read 5, iclass 38, count 2 2006.257.03:06:50.34#ibcon#read 5, iclass 38, count 2 2006.257.03:06:50.34#ibcon#about to read 6, iclass 38, count 2 2006.257.03:06:50.34#ibcon#read 6, iclass 38, count 2 2006.257.03:06:50.34#ibcon#end of sib2, iclass 38, count 2 2006.257.03:06:50.34#ibcon#*mode == 0, iclass 38, count 2 2006.257.03:06:50.34#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.03:06:50.34#ibcon#[25=AT02-07\r\n] 2006.257.03:06:50.34#ibcon#*before write, iclass 38, count 2 2006.257.03:06:50.34#ibcon#enter sib2, iclass 38, count 2 2006.257.03:06:50.34#ibcon#flushed, iclass 38, count 2 2006.257.03:06:50.34#ibcon#about to write, iclass 38, count 2 2006.257.03:06:50.34#ibcon#wrote, iclass 38, count 2 2006.257.03:06:50.34#ibcon#about to read 3, iclass 38, count 2 2006.257.03:06:50.37#ibcon#read 3, iclass 38, count 2 2006.257.03:06:50.37#ibcon#about to read 4, iclass 38, count 2 2006.257.03:06:50.37#ibcon#read 4, iclass 38, count 2 2006.257.03:06:50.37#ibcon#about to read 5, iclass 38, count 2 2006.257.03:06:50.37#ibcon#read 5, iclass 38, count 2 2006.257.03:06:50.37#ibcon#about to read 6, iclass 38, count 2 2006.257.03:06:50.37#ibcon#read 6, iclass 38, count 2 2006.257.03:06:50.37#ibcon#end of sib2, iclass 38, count 2 2006.257.03:06:50.37#ibcon#*after write, iclass 38, count 2 2006.257.03:06:50.37#ibcon#*before return 0, iclass 38, count 2 2006.257.03:06:50.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:50.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:50.37#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.03:06:50.37#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:50.37#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:50.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:50.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:50.50#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:06:50.50#ibcon#first serial, iclass 38, count 0 2006.257.03:06:50.50#ibcon#enter sib2, iclass 38, count 0 2006.257.03:06:50.50#ibcon#flushed, iclass 38, count 0 2006.257.03:06:50.50#ibcon#about to write, iclass 38, count 0 2006.257.03:06:50.50#ibcon#wrote, iclass 38, count 0 2006.257.03:06:50.50#ibcon#about to read 3, iclass 38, count 0 2006.257.03:06:50.51#ibcon#read 3, iclass 38, count 0 2006.257.03:06:50.51#ibcon#about to read 4, iclass 38, count 0 2006.257.03:06:50.51#ibcon#read 4, iclass 38, count 0 2006.257.03:06:50.51#ibcon#about to read 5, iclass 38, count 0 2006.257.03:06:50.51#ibcon#read 5, iclass 38, count 0 2006.257.03:06:50.51#ibcon#about to read 6, iclass 38, count 0 2006.257.03:06:50.51#ibcon#read 6, iclass 38, count 0 2006.257.03:06:50.51#ibcon#end of sib2, iclass 38, count 0 2006.257.03:06:50.51#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:06:50.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:06:50.51#ibcon#[25=USB\r\n] 2006.257.03:06:50.51#ibcon#*before write, iclass 38, count 0 2006.257.03:06:50.51#ibcon#enter sib2, iclass 38, count 0 2006.257.03:06:50.51#ibcon#flushed, iclass 38, count 0 2006.257.03:06:50.51#ibcon#about to write, iclass 38, count 0 2006.257.03:06:50.51#ibcon#wrote, iclass 38, count 0 2006.257.03:06:50.51#ibcon#about to read 3, iclass 38, count 0 2006.257.03:06:50.54#ibcon#read 3, iclass 38, count 0 2006.257.03:06:50.54#ibcon#about to read 4, iclass 38, count 0 2006.257.03:06:50.54#ibcon#read 4, iclass 38, count 0 2006.257.03:06:50.54#ibcon#about to read 5, iclass 38, count 0 2006.257.03:06:50.54#ibcon#read 5, iclass 38, count 0 2006.257.03:06:50.54#ibcon#about to read 6, iclass 38, count 0 2006.257.03:06:50.54#ibcon#read 6, iclass 38, count 0 2006.257.03:06:50.54#ibcon#end of sib2, iclass 38, count 0 2006.257.03:06:50.54#ibcon#*after write, iclass 38, count 0 2006.257.03:06:50.54#ibcon#*before return 0, iclass 38, count 0 2006.257.03:06:50.54#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:50.54#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:50.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:06:50.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:06:50.54$vck44/valo=3,564.99 2006.257.03:06:50.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.03:06:50.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.03:06:50.54#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:50.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:50.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:50.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:50.54#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:06:50.54#ibcon#first serial, iclass 40, count 0 2006.257.03:06:50.54#ibcon#enter sib2, iclass 40, count 0 2006.257.03:06:50.54#ibcon#flushed, iclass 40, count 0 2006.257.03:06:50.54#ibcon#about to write, iclass 40, count 0 2006.257.03:06:50.54#ibcon#wrote, iclass 40, count 0 2006.257.03:06:50.54#ibcon#about to read 3, iclass 40, count 0 2006.257.03:06:50.56#ibcon#read 3, iclass 40, count 0 2006.257.03:06:50.56#ibcon#about to read 4, iclass 40, count 0 2006.257.03:06:50.56#ibcon#read 4, iclass 40, count 0 2006.257.03:06:50.56#ibcon#about to read 5, iclass 40, count 0 2006.257.03:06:50.56#ibcon#read 5, iclass 40, count 0 2006.257.03:06:50.56#ibcon#about to read 6, iclass 40, count 0 2006.257.03:06:50.56#ibcon#read 6, iclass 40, count 0 2006.257.03:06:50.56#ibcon#end of sib2, iclass 40, count 0 2006.257.03:06:50.56#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:06:50.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:06:50.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:06:50.56#ibcon#*before write, iclass 40, count 0 2006.257.03:06:50.56#ibcon#enter sib2, iclass 40, count 0 2006.257.03:06:50.56#ibcon#flushed, iclass 40, count 0 2006.257.03:06:50.56#ibcon#about to write, iclass 40, count 0 2006.257.03:06:50.56#ibcon#wrote, iclass 40, count 0 2006.257.03:06:50.56#ibcon#about to read 3, iclass 40, count 0 2006.257.03:06:50.60#ibcon#read 3, iclass 40, count 0 2006.257.03:06:50.60#ibcon#about to read 4, iclass 40, count 0 2006.257.03:06:50.60#ibcon#read 4, iclass 40, count 0 2006.257.03:06:50.60#ibcon#about to read 5, iclass 40, count 0 2006.257.03:06:50.60#ibcon#read 5, iclass 40, count 0 2006.257.03:06:50.60#ibcon#about to read 6, iclass 40, count 0 2006.257.03:06:50.60#ibcon#read 6, iclass 40, count 0 2006.257.03:06:50.60#ibcon#end of sib2, iclass 40, count 0 2006.257.03:06:50.60#ibcon#*after write, iclass 40, count 0 2006.257.03:06:50.60#ibcon#*before return 0, iclass 40, count 0 2006.257.03:06:50.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:50.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:50.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:06:50.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:06:50.60$vck44/va=3,8 2006.257.03:06:50.60#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.03:06:50.60#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.03:06:50.60#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:50.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:50.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:50.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:50.66#ibcon#enter wrdev, iclass 4, count 2 2006.257.03:06:50.66#ibcon#first serial, iclass 4, count 2 2006.257.03:06:50.66#ibcon#enter sib2, iclass 4, count 2 2006.257.03:06:50.66#ibcon#flushed, iclass 4, count 2 2006.257.03:06:50.66#ibcon#about to write, iclass 4, count 2 2006.257.03:06:50.66#ibcon#wrote, iclass 4, count 2 2006.257.03:06:50.66#ibcon#about to read 3, iclass 4, count 2 2006.257.03:06:50.68#ibcon#read 3, iclass 4, count 2 2006.257.03:06:50.68#ibcon#about to read 4, iclass 4, count 2 2006.257.03:06:50.68#ibcon#read 4, iclass 4, count 2 2006.257.03:06:50.68#ibcon#about to read 5, iclass 4, count 2 2006.257.03:06:50.68#ibcon#read 5, iclass 4, count 2 2006.257.03:06:50.68#ibcon#about to read 6, iclass 4, count 2 2006.257.03:06:50.68#ibcon#read 6, iclass 4, count 2 2006.257.03:06:50.68#ibcon#end of sib2, iclass 4, count 2 2006.257.03:06:50.68#ibcon#*mode == 0, iclass 4, count 2 2006.257.03:06:50.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.03:06:50.68#ibcon#[25=AT03-08\r\n] 2006.257.03:06:50.68#ibcon#*before write, iclass 4, count 2 2006.257.03:06:50.68#ibcon#enter sib2, iclass 4, count 2 2006.257.03:06:50.68#ibcon#flushed, iclass 4, count 2 2006.257.03:06:50.68#ibcon#about to write, iclass 4, count 2 2006.257.03:06:50.68#ibcon#wrote, iclass 4, count 2 2006.257.03:06:50.68#ibcon#about to read 3, iclass 4, count 2 2006.257.03:06:50.71#ibcon#read 3, iclass 4, count 2 2006.257.03:06:50.71#ibcon#about to read 4, iclass 4, count 2 2006.257.03:06:50.71#ibcon#read 4, iclass 4, count 2 2006.257.03:06:50.71#ibcon#about to read 5, iclass 4, count 2 2006.257.03:06:50.71#ibcon#read 5, iclass 4, count 2 2006.257.03:06:50.71#ibcon#about to read 6, iclass 4, count 2 2006.257.03:06:50.71#ibcon#read 6, iclass 4, count 2 2006.257.03:06:50.71#ibcon#end of sib2, iclass 4, count 2 2006.257.03:06:50.71#ibcon#*after write, iclass 4, count 2 2006.257.03:06:50.71#ibcon#*before return 0, iclass 4, count 2 2006.257.03:06:50.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:50.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:50.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.03:06:50.71#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:50.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:50.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:50.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:50.84#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:06:50.84#ibcon#first serial, iclass 4, count 0 2006.257.03:06:50.84#ibcon#enter sib2, iclass 4, count 0 2006.257.03:06:50.84#ibcon#flushed, iclass 4, count 0 2006.257.03:06:50.84#ibcon#about to write, iclass 4, count 0 2006.257.03:06:50.84#ibcon#wrote, iclass 4, count 0 2006.257.03:06:50.84#ibcon#about to read 3, iclass 4, count 0 2006.257.03:06:50.85#ibcon#read 3, iclass 4, count 0 2006.257.03:06:50.85#ibcon#about to read 4, iclass 4, count 0 2006.257.03:06:50.85#ibcon#read 4, iclass 4, count 0 2006.257.03:06:50.85#ibcon#about to read 5, iclass 4, count 0 2006.257.03:06:50.85#ibcon#read 5, iclass 4, count 0 2006.257.03:06:50.85#ibcon#about to read 6, iclass 4, count 0 2006.257.03:06:50.85#ibcon#read 6, iclass 4, count 0 2006.257.03:06:50.85#ibcon#end of sib2, iclass 4, count 0 2006.257.03:06:50.85#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:06:50.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:06:50.85#ibcon#[25=USB\r\n] 2006.257.03:06:50.85#ibcon#*before write, iclass 4, count 0 2006.257.03:06:50.85#ibcon#enter sib2, iclass 4, count 0 2006.257.03:06:50.85#ibcon#flushed, iclass 4, count 0 2006.257.03:06:50.85#ibcon#about to write, iclass 4, count 0 2006.257.03:06:50.85#ibcon#wrote, iclass 4, count 0 2006.257.03:06:50.85#ibcon#about to read 3, iclass 4, count 0 2006.257.03:06:50.88#ibcon#read 3, iclass 4, count 0 2006.257.03:06:50.88#ibcon#about to read 4, iclass 4, count 0 2006.257.03:06:50.88#ibcon#read 4, iclass 4, count 0 2006.257.03:06:50.88#ibcon#about to read 5, iclass 4, count 0 2006.257.03:06:50.88#ibcon#read 5, iclass 4, count 0 2006.257.03:06:50.88#ibcon#about to read 6, iclass 4, count 0 2006.257.03:06:50.88#ibcon#read 6, iclass 4, count 0 2006.257.03:06:50.88#ibcon#end of sib2, iclass 4, count 0 2006.257.03:06:50.88#ibcon#*after write, iclass 4, count 0 2006.257.03:06:50.88#ibcon#*before return 0, iclass 4, count 0 2006.257.03:06:50.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:50.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:50.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:06:50.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:06:50.88$vck44/valo=4,624.99 2006.257.03:06:50.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.03:06:50.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.03:06:50.88#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:50.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:50.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:50.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:50.88#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:06:50.88#ibcon#first serial, iclass 6, count 0 2006.257.03:06:50.88#ibcon#enter sib2, iclass 6, count 0 2006.257.03:06:50.88#ibcon#flushed, iclass 6, count 0 2006.257.03:06:50.88#ibcon#about to write, iclass 6, count 0 2006.257.03:06:50.88#ibcon#wrote, iclass 6, count 0 2006.257.03:06:50.88#ibcon#about to read 3, iclass 6, count 0 2006.257.03:06:50.90#ibcon#read 3, iclass 6, count 0 2006.257.03:06:50.90#ibcon#about to read 4, iclass 6, count 0 2006.257.03:06:50.90#ibcon#read 4, iclass 6, count 0 2006.257.03:06:50.90#ibcon#about to read 5, iclass 6, count 0 2006.257.03:06:50.90#ibcon#read 5, iclass 6, count 0 2006.257.03:06:50.90#ibcon#about to read 6, iclass 6, count 0 2006.257.03:06:50.90#ibcon#read 6, iclass 6, count 0 2006.257.03:06:50.90#ibcon#end of sib2, iclass 6, count 0 2006.257.03:06:50.90#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:06:50.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:06:50.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:06:50.90#ibcon#*before write, iclass 6, count 0 2006.257.03:06:50.90#ibcon#enter sib2, iclass 6, count 0 2006.257.03:06:50.90#ibcon#flushed, iclass 6, count 0 2006.257.03:06:50.90#ibcon#about to write, iclass 6, count 0 2006.257.03:06:50.90#ibcon#wrote, iclass 6, count 0 2006.257.03:06:50.90#ibcon#about to read 3, iclass 6, count 0 2006.257.03:06:50.94#ibcon#read 3, iclass 6, count 0 2006.257.03:06:50.94#ibcon#about to read 4, iclass 6, count 0 2006.257.03:06:50.94#ibcon#read 4, iclass 6, count 0 2006.257.03:06:50.94#ibcon#about to read 5, iclass 6, count 0 2006.257.03:06:50.94#ibcon#read 5, iclass 6, count 0 2006.257.03:06:50.94#ibcon#about to read 6, iclass 6, count 0 2006.257.03:06:50.94#ibcon#read 6, iclass 6, count 0 2006.257.03:06:50.94#ibcon#end of sib2, iclass 6, count 0 2006.257.03:06:50.94#ibcon#*after write, iclass 6, count 0 2006.257.03:06:50.94#ibcon#*before return 0, iclass 6, count 0 2006.257.03:06:50.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:50.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:50.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:06:50.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:06:50.94$vck44/va=4,7 2006.257.03:06:50.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.03:06:50.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.03:06:50.94#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:50.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:51.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:51.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:51.00#ibcon#enter wrdev, iclass 10, count 2 2006.257.03:06:51.01#ibcon#first serial, iclass 10, count 2 2006.257.03:06:51.01#ibcon#enter sib2, iclass 10, count 2 2006.257.03:06:51.01#ibcon#flushed, iclass 10, count 2 2006.257.03:06:51.01#ibcon#about to write, iclass 10, count 2 2006.257.03:06:51.01#ibcon#wrote, iclass 10, count 2 2006.257.03:06:51.01#ibcon#about to read 3, iclass 10, count 2 2006.257.03:06:51.02#ibcon#read 3, iclass 10, count 2 2006.257.03:06:51.02#ibcon#about to read 4, iclass 10, count 2 2006.257.03:06:51.02#ibcon#read 4, iclass 10, count 2 2006.257.03:06:51.02#ibcon#about to read 5, iclass 10, count 2 2006.257.03:06:51.02#ibcon#read 5, iclass 10, count 2 2006.257.03:06:51.02#ibcon#about to read 6, iclass 10, count 2 2006.257.03:06:51.02#ibcon#read 6, iclass 10, count 2 2006.257.03:06:51.02#ibcon#end of sib2, iclass 10, count 2 2006.257.03:06:51.02#ibcon#*mode == 0, iclass 10, count 2 2006.257.03:06:51.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.03:06:51.02#ibcon#[25=AT04-07\r\n] 2006.257.03:06:51.02#ibcon#*before write, iclass 10, count 2 2006.257.03:06:51.02#ibcon#enter sib2, iclass 10, count 2 2006.257.03:06:51.02#ibcon#flushed, iclass 10, count 2 2006.257.03:06:51.02#ibcon#about to write, iclass 10, count 2 2006.257.03:06:51.02#ibcon#wrote, iclass 10, count 2 2006.257.03:06:51.02#ibcon#about to read 3, iclass 10, count 2 2006.257.03:06:51.05#ibcon#read 3, iclass 10, count 2 2006.257.03:06:51.05#ibcon#about to read 4, iclass 10, count 2 2006.257.03:06:51.05#ibcon#read 4, iclass 10, count 2 2006.257.03:06:51.05#ibcon#about to read 5, iclass 10, count 2 2006.257.03:06:51.05#ibcon#read 5, iclass 10, count 2 2006.257.03:06:51.05#ibcon#about to read 6, iclass 10, count 2 2006.257.03:06:51.05#ibcon#read 6, iclass 10, count 2 2006.257.03:06:51.05#ibcon#end of sib2, iclass 10, count 2 2006.257.03:06:51.05#ibcon#*after write, iclass 10, count 2 2006.257.03:06:51.05#ibcon#*before return 0, iclass 10, count 2 2006.257.03:06:51.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:51.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:51.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.03:06:51.05#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:51.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:51.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:51.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:51.17#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:06:51.17#ibcon#first serial, iclass 10, count 0 2006.257.03:06:51.17#ibcon#enter sib2, iclass 10, count 0 2006.257.03:06:51.17#ibcon#flushed, iclass 10, count 0 2006.257.03:06:51.17#ibcon#about to write, iclass 10, count 0 2006.257.03:06:51.17#ibcon#wrote, iclass 10, count 0 2006.257.03:06:51.17#ibcon#about to read 3, iclass 10, count 0 2006.257.03:06:51.19#ibcon#read 3, iclass 10, count 0 2006.257.03:06:51.19#ibcon#about to read 4, iclass 10, count 0 2006.257.03:06:51.19#ibcon#read 4, iclass 10, count 0 2006.257.03:06:51.19#ibcon#about to read 5, iclass 10, count 0 2006.257.03:06:51.19#ibcon#read 5, iclass 10, count 0 2006.257.03:06:51.19#ibcon#about to read 6, iclass 10, count 0 2006.257.03:06:51.19#ibcon#read 6, iclass 10, count 0 2006.257.03:06:51.19#ibcon#end of sib2, iclass 10, count 0 2006.257.03:06:51.19#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:06:51.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:06:51.19#ibcon#[25=USB\r\n] 2006.257.03:06:51.19#ibcon#*before write, iclass 10, count 0 2006.257.03:06:51.19#ibcon#enter sib2, iclass 10, count 0 2006.257.03:06:51.19#ibcon#flushed, iclass 10, count 0 2006.257.03:06:51.19#ibcon#about to write, iclass 10, count 0 2006.257.03:06:51.19#ibcon#wrote, iclass 10, count 0 2006.257.03:06:51.19#ibcon#about to read 3, iclass 10, count 0 2006.257.03:06:51.22#ibcon#read 3, iclass 10, count 0 2006.257.03:06:51.22#ibcon#about to read 4, iclass 10, count 0 2006.257.03:06:51.22#ibcon#read 4, iclass 10, count 0 2006.257.03:06:51.22#ibcon#about to read 5, iclass 10, count 0 2006.257.03:06:51.22#ibcon#read 5, iclass 10, count 0 2006.257.03:06:51.22#ibcon#about to read 6, iclass 10, count 0 2006.257.03:06:51.22#ibcon#read 6, iclass 10, count 0 2006.257.03:06:51.22#ibcon#end of sib2, iclass 10, count 0 2006.257.03:06:51.22#ibcon#*after write, iclass 10, count 0 2006.257.03:06:51.22#ibcon#*before return 0, iclass 10, count 0 2006.257.03:06:51.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:51.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:51.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:06:51.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:06:51.22$vck44/valo=5,734.99 2006.257.03:06:51.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.03:06:51.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.03:06:51.22#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:51.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:51.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:51.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:51.22#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:06:51.22#ibcon#first serial, iclass 12, count 0 2006.257.03:06:51.22#ibcon#enter sib2, iclass 12, count 0 2006.257.03:06:51.22#ibcon#flushed, iclass 12, count 0 2006.257.03:06:51.22#ibcon#about to write, iclass 12, count 0 2006.257.03:06:51.22#ibcon#wrote, iclass 12, count 0 2006.257.03:06:51.22#ibcon#about to read 3, iclass 12, count 0 2006.257.03:06:51.24#ibcon#read 3, iclass 12, count 0 2006.257.03:06:51.24#ibcon#about to read 4, iclass 12, count 0 2006.257.03:06:51.24#ibcon#read 4, iclass 12, count 0 2006.257.03:06:51.24#ibcon#about to read 5, iclass 12, count 0 2006.257.03:06:51.24#ibcon#read 5, iclass 12, count 0 2006.257.03:06:51.24#ibcon#about to read 6, iclass 12, count 0 2006.257.03:06:51.24#ibcon#read 6, iclass 12, count 0 2006.257.03:06:51.24#ibcon#end of sib2, iclass 12, count 0 2006.257.03:06:51.24#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:06:51.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:06:51.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:06:51.24#ibcon#*before write, iclass 12, count 0 2006.257.03:06:51.24#ibcon#enter sib2, iclass 12, count 0 2006.257.03:06:51.24#ibcon#flushed, iclass 12, count 0 2006.257.03:06:51.24#ibcon#about to write, iclass 12, count 0 2006.257.03:06:51.24#ibcon#wrote, iclass 12, count 0 2006.257.03:06:51.24#ibcon#about to read 3, iclass 12, count 0 2006.257.03:06:51.28#ibcon#read 3, iclass 12, count 0 2006.257.03:06:51.28#ibcon#about to read 4, iclass 12, count 0 2006.257.03:06:51.28#ibcon#read 4, iclass 12, count 0 2006.257.03:06:51.28#ibcon#about to read 5, iclass 12, count 0 2006.257.03:06:51.28#ibcon#read 5, iclass 12, count 0 2006.257.03:06:51.28#ibcon#about to read 6, iclass 12, count 0 2006.257.03:06:51.28#ibcon#read 6, iclass 12, count 0 2006.257.03:06:51.28#ibcon#end of sib2, iclass 12, count 0 2006.257.03:06:51.28#ibcon#*after write, iclass 12, count 0 2006.257.03:06:51.28#ibcon#*before return 0, iclass 12, count 0 2006.257.03:06:51.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:51.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:51.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:06:51.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:06:51.28$vck44/va=5,4 2006.257.03:06:51.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.03:06:51.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.03:06:51.28#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:51.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:51.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:51.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:51.34#ibcon#enter wrdev, iclass 14, count 2 2006.257.03:06:51.34#ibcon#first serial, iclass 14, count 2 2006.257.03:06:51.34#ibcon#enter sib2, iclass 14, count 2 2006.257.03:06:51.34#ibcon#flushed, iclass 14, count 2 2006.257.03:06:51.34#ibcon#about to write, iclass 14, count 2 2006.257.03:06:51.34#ibcon#wrote, iclass 14, count 2 2006.257.03:06:51.34#ibcon#about to read 3, iclass 14, count 2 2006.257.03:06:51.36#ibcon#read 3, iclass 14, count 2 2006.257.03:06:51.36#ibcon#about to read 4, iclass 14, count 2 2006.257.03:06:51.36#ibcon#read 4, iclass 14, count 2 2006.257.03:06:51.36#ibcon#about to read 5, iclass 14, count 2 2006.257.03:06:51.36#ibcon#read 5, iclass 14, count 2 2006.257.03:06:51.36#ibcon#about to read 6, iclass 14, count 2 2006.257.03:06:51.36#ibcon#read 6, iclass 14, count 2 2006.257.03:06:51.36#ibcon#end of sib2, iclass 14, count 2 2006.257.03:06:51.36#ibcon#*mode == 0, iclass 14, count 2 2006.257.03:06:51.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.03:06:51.36#ibcon#[25=AT05-04\r\n] 2006.257.03:06:51.36#ibcon#*before write, iclass 14, count 2 2006.257.03:06:51.36#ibcon#enter sib2, iclass 14, count 2 2006.257.03:06:51.36#ibcon#flushed, iclass 14, count 2 2006.257.03:06:51.36#ibcon#about to write, iclass 14, count 2 2006.257.03:06:51.36#ibcon#wrote, iclass 14, count 2 2006.257.03:06:51.36#ibcon#about to read 3, iclass 14, count 2 2006.257.03:06:51.39#ibcon#read 3, iclass 14, count 2 2006.257.03:06:51.39#ibcon#about to read 4, iclass 14, count 2 2006.257.03:06:51.39#ibcon#read 4, iclass 14, count 2 2006.257.03:06:51.39#ibcon#about to read 5, iclass 14, count 2 2006.257.03:06:51.39#ibcon#read 5, iclass 14, count 2 2006.257.03:06:51.39#ibcon#about to read 6, iclass 14, count 2 2006.257.03:06:51.39#ibcon#read 6, iclass 14, count 2 2006.257.03:06:51.39#ibcon#end of sib2, iclass 14, count 2 2006.257.03:06:51.39#ibcon#*after write, iclass 14, count 2 2006.257.03:06:51.39#ibcon#*before return 0, iclass 14, count 2 2006.257.03:06:51.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:51.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:51.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.03:06:51.39#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:51.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:51.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:51.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:51.51#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:06:51.51#ibcon#first serial, iclass 14, count 0 2006.257.03:06:51.51#ibcon#enter sib2, iclass 14, count 0 2006.257.03:06:51.51#ibcon#flushed, iclass 14, count 0 2006.257.03:06:51.51#ibcon#about to write, iclass 14, count 0 2006.257.03:06:51.51#ibcon#wrote, iclass 14, count 0 2006.257.03:06:51.51#ibcon#about to read 3, iclass 14, count 0 2006.257.03:06:51.53#ibcon#read 3, iclass 14, count 0 2006.257.03:06:51.53#ibcon#about to read 4, iclass 14, count 0 2006.257.03:06:51.53#ibcon#read 4, iclass 14, count 0 2006.257.03:06:51.53#ibcon#about to read 5, iclass 14, count 0 2006.257.03:06:51.53#ibcon#read 5, iclass 14, count 0 2006.257.03:06:51.53#ibcon#about to read 6, iclass 14, count 0 2006.257.03:06:51.53#ibcon#read 6, iclass 14, count 0 2006.257.03:06:51.53#ibcon#end of sib2, iclass 14, count 0 2006.257.03:06:51.53#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:06:51.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:06:51.53#ibcon#[25=USB\r\n] 2006.257.03:06:51.53#ibcon#*before write, iclass 14, count 0 2006.257.03:06:51.53#ibcon#enter sib2, iclass 14, count 0 2006.257.03:06:51.53#ibcon#flushed, iclass 14, count 0 2006.257.03:06:51.53#ibcon#about to write, iclass 14, count 0 2006.257.03:06:51.53#ibcon#wrote, iclass 14, count 0 2006.257.03:06:51.53#ibcon#about to read 3, iclass 14, count 0 2006.257.03:06:51.56#ibcon#read 3, iclass 14, count 0 2006.257.03:06:51.56#ibcon#about to read 4, iclass 14, count 0 2006.257.03:06:51.56#ibcon#read 4, iclass 14, count 0 2006.257.03:06:51.56#ibcon#about to read 5, iclass 14, count 0 2006.257.03:06:51.56#ibcon#read 5, iclass 14, count 0 2006.257.03:06:51.56#ibcon#about to read 6, iclass 14, count 0 2006.257.03:06:51.56#ibcon#read 6, iclass 14, count 0 2006.257.03:06:51.56#ibcon#end of sib2, iclass 14, count 0 2006.257.03:06:51.56#ibcon#*after write, iclass 14, count 0 2006.257.03:06:51.56#ibcon#*before return 0, iclass 14, count 0 2006.257.03:06:51.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:51.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:51.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:06:51.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:06:51.56$vck44/valo=6,814.99 2006.257.03:06:51.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.03:06:51.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.03:06:51.56#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:51.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:51.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:51.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:51.56#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:06:51.56#ibcon#first serial, iclass 16, count 0 2006.257.03:06:51.56#ibcon#enter sib2, iclass 16, count 0 2006.257.03:06:51.56#ibcon#flushed, iclass 16, count 0 2006.257.03:06:51.56#ibcon#about to write, iclass 16, count 0 2006.257.03:06:51.56#ibcon#wrote, iclass 16, count 0 2006.257.03:06:51.56#ibcon#about to read 3, iclass 16, count 0 2006.257.03:06:51.58#ibcon#read 3, iclass 16, count 0 2006.257.03:06:51.58#ibcon#about to read 4, iclass 16, count 0 2006.257.03:06:51.58#ibcon#read 4, iclass 16, count 0 2006.257.03:06:51.58#ibcon#about to read 5, iclass 16, count 0 2006.257.03:06:51.58#ibcon#read 5, iclass 16, count 0 2006.257.03:06:51.58#ibcon#about to read 6, iclass 16, count 0 2006.257.03:06:51.58#ibcon#read 6, iclass 16, count 0 2006.257.03:06:51.58#ibcon#end of sib2, iclass 16, count 0 2006.257.03:06:51.58#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:06:51.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:06:51.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:06:51.58#ibcon#*before write, iclass 16, count 0 2006.257.03:06:51.58#ibcon#enter sib2, iclass 16, count 0 2006.257.03:06:51.58#ibcon#flushed, iclass 16, count 0 2006.257.03:06:51.58#ibcon#about to write, iclass 16, count 0 2006.257.03:06:51.58#ibcon#wrote, iclass 16, count 0 2006.257.03:06:51.58#ibcon#about to read 3, iclass 16, count 0 2006.257.03:06:51.62#ibcon#read 3, iclass 16, count 0 2006.257.03:06:51.62#ibcon#about to read 4, iclass 16, count 0 2006.257.03:06:51.62#ibcon#read 4, iclass 16, count 0 2006.257.03:06:51.62#ibcon#about to read 5, iclass 16, count 0 2006.257.03:06:51.62#ibcon#read 5, iclass 16, count 0 2006.257.03:06:51.62#ibcon#about to read 6, iclass 16, count 0 2006.257.03:06:51.62#ibcon#read 6, iclass 16, count 0 2006.257.03:06:51.62#ibcon#end of sib2, iclass 16, count 0 2006.257.03:06:51.62#ibcon#*after write, iclass 16, count 0 2006.257.03:06:51.62#ibcon#*before return 0, iclass 16, count 0 2006.257.03:06:51.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:51.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:51.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:06:51.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:06:51.62$vck44/va=6,4 2006.257.03:06:51.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.03:06:51.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.03:06:51.62#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:51.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:51.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:51.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:51.68#ibcon#enter wrdev, iclass 18, count 2 2006.257.03:06:51.68#ibcon#first serial, iclass 18, count 2 2006.257.03:06:51.68#ibcon#enter sib2, iclass 18, count 2 2006.257.03:06:51.68#ibcon#flushed, iclass 18, count 2 2006.257.03:06:51.68#ibcon#about to write, iclass 18, count 2 2006.257.03:06:51.68#ibcon#wrote, iclass 18, count 2 2006.257.03:06:51.68#ibcon#about to read 3, iclass 18, count 2 2006.257.03:06:51.70#ibcon#read 3, iclass 18, count 2 2006.257.03:06:51.70#ibcon#about to read 4, iclass 18, count 2 2006.257.03:06:51.70#ibcon#read 4, iclass 18, count 2 2006.257.03:06:51.70#ibcon#about to read 5, iclass 18, count 2 2006.257.03:06:51.70#ibcon#read 5, iclass 18, count 2 2006.257.03:06:51.70#ibcon#about to read 6, iclass 18, count 2 2006.257.03:06:51.70#ibcon#read 6, iclass 18, count 2 2006.257.03:06:51.70#ibcon#end of sib2, iclass 18, count 2 2006.257.03:06:51.70#ibcon#*mode == 0, iclass 18, count 2 2006.257.03:06:51.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.03:06:51.70#ibcon#[25=AT06-04\r\n] 2006.257.03:06:51.70#ibcon#*before write, iclass 18, count 2 2006.257.03:06:51.70#ibcon#enter sib2, iclass 18, count 2 2006.257.03:06:51.70#ibcon#flushed, iclass 18, count 2 2006.257.03:06:51.70#ibcon#about to write, iclass 18, count 2 2006.257.03:06:51.70#ibcon#wrote, iclass 18, count 2 2006.257.03:06:51.70#ibcon#about to read 3, iclass 18, count 2 2006.257.03:06:51.73#ibcon#read 3, iclass 18, count 2 2006.257.03:06:51.73#ibcon#about to read 4, iclass 18, count 2 2006.257.03:06:51.73#ibcon#read 4, iclass 18, count 2 2006.257.03:06:51.73#ibcon#about to read 5, iclass 18, count 2 2006.257.03:06:51.73#ibcon#read 5, iclass 18, count 2 2006.257.03:06:51.73#ibcon#about to read 6, iclass 18, count 2 2006.257.03:06:51.73#ibcon#read 6, iclass 18, count 2 2006.257.03:06:51.73#ibcon#end of sib2, iclass 18, count 2 2006.257.03:06:51.73#ibcon#*after write, iclass 18, count 2 2006.257.03:06:51.73#ibcon#*before return 0, iclass 18, count 2 2006.257.03:06:51.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:51.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:51.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.03:06:51.73#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:51.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:51.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:51.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:51.86#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:06:51.86#ibcon#first serial, iclass 18, count 0 2006.257.03:06:51.86#ibcon#enter sib2, iclass 18, count 0 2006.257.03:06:51.86#ibcon#flushed, iclass 18, count 0 2006.257.03:06:51.86#ibcon#about to write, iclass 18, count 0 2006.257.03:06:51.86#ibcon#wrote, iclass 18, count 0 2006.257.03:06:51.86#ibcon#about to read 3, iclass 18, count 0 2006.257.03:06:51.87#ibcon#read 3, iclass 18, count 0 2006.257.03:06:51.87#ibcon#about to read 4, iclass 18, count 0 2006.257.03:06:51.87#ibcon#read 4, iclass 18, count 0 2006.257.03:06:51.87#ibcon#about to read 5, iclass 18, count 0 2006.257.03:06:51.87#ibcon#read 5, iclass 18, count 0 2006.257.03:06:51.87#ibcon#about to read 6, iclass 18, count 0 2006.257.03:06:51.87#ibcon#read 6, iclass 18, count 0 2006.257.03:06:51.87#ibcon#end of sib2, iclass 18, count 0 2006.257.03:06:51.87#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:06:51.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:06:51.87#ibcon#[25=USB\r\n] 2006.257.03:06:51.87#ibcon#*before write, iclass 18, count 0 2006.257.03:06:51.87#ibcon#enter sib2, iclass 18, count 0 2006.257.03:06:51.87#ibcon#flushed, iclass 18, count 0 2006.257.03:06:51.87#ibcon#about to write, iclass 18, count 0 2006.257.03:06:51.87#ibcon#wrote, iclass 18, count 0 2006.257.03:06:51.87#ibcon#about to read 3, iclass 18, count 0 2006.257.03:06:51.90#ibcon#read 3, iclass 18, count 0 2006.257.03:06:51.90#ibcon#about to read 4, iclass 18, count 0 2006.257.03:06:51.90#ibcon#read 4, iclass 18, count 0 2006.257.03:06:51.90#ibcon#about to read 5, iclass 18, count 0 2006.257.03:06:51.90#ibcon#read 5, iclass 18, count 0 2006.257.03:06:51.90#ibcon#about to read 6, iclass 18, count 0 2006.257.03:06:51.90#ibcon#read 6, iclass 18, count 0 2006.257.03:06:51.90#ibcon#end of sib2, iclass 18, count 0 2006.257.03:06:51.90#ibcon#*after write, iclass 18, count 0 2006.257.03:06:51.90#ibcon#*before return 0, iclass 18, count 0 2006.257.03:06:51.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:51.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:51.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:06:51.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:06:51.90$vck44/valo=7,864.99 2006.257.03:06:51.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.03:06:51.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.03:06:51.90#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:51.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:51.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:51.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:51.90#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:06:51.90#ibcon#first serial, iclass 20, count 0 2006.257.03:06:51.90#ibcon#enter sib2, iclass 20, count 0 2006.257.03:06:51.90#ibcon#flushed, iclass 20, count 0 2006.257.03:06:51.90#ibcon#about to write, iclass 20, count 0 2006.257.03:06:51.90#ibcon#wrote, iclass 20, count 0 2006.257.03:06:51.90#ibcon#about to read 3, iclass 20, count 0 2006.257.03:06:51.92#ibcon#read 3, iclass 20, count 0 2006.257.03:06:51.92#ibcon#about to read 4, iclass 20, count 0 2006.257.03:06:51.92#ibcon#read 4, iclass 20, count 0 2006.257.03:06:51.92#ibcon#about to read 5, iclass 20, count 0 2006.257.03:06:51.92#ibcon#read 5, iclass 20, count 0 2006.257.03:06:51.92#ibcon#about to read 6, iclass 20, count 0 2006.257.03:06:51.92#ibcon#read 6, iclass 20, count 0 2006.257.03:06:51.92#ibcon#end of sib2, iclass 20, count 0 2006.257.03:06:51.92#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:06:51.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:06:51.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:06:51.92#ibcon#*before write, iclass 20, count 0 2006.257.03:06:51.92#ibcon#enter sib2, iclass 20, count 0 2006.257.03:06:51.92#ibcon#flushed, iclass 20, count 0 2006.257.03:06:51.92#ibcon#about to write, iclass 20, count 0 2006.257.03:06:51.92#ibcon#wrote, iclass 20, count 0 2006.257.03:06:51.92#ibcon#about to read 3, iclass 20, count 0 2006.257.03:06:51.96#ibcon#read 3, iclass 20, count 0 2006.257.03:06:51.96#ibcon#about to read 4, iclass 20, count 0 2006.257.03:06:51.96#ibcon#read 4, iclass 20, count 0 2006.257.03:06:51.96#ibcon#about to read 5, iclass 20, count 0 2006.257.03:06:51.96#ibcon#read 5, iclass 20, count 0 2006.257.03:06:51.96#ibcon#about to read 6, iclass 20, count 0 2006.257.03:06:51.96#ibcon#read 6, iclass 20, count 0 2006.257.03:06:51.96#ibcon#end of sib2, iclass 20, count 0 2006.257.03:06:51.96#ibcon#*after write, iclass 20, count 0 2006.257.03:06:51.96#ibcon#*before return 0, iclass 20, count 0 2006.257.03:06:51.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:51.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:51.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:06:51.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:06:51.96$vck44/va=7,4 2006.257.03:06:51.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.03:06:51.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.03:06:51.96#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:51.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:52.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:52.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:52.02#ibcon#enter wrdev, iclass 22, count 2 2006.257.03:06:52.02#ibcon#first serial, iclass 22, count 2 2006.257.03:06:52.02#ibcon#enter sib2, iclass 22, count 2 2006.257.03:06:52.02#ibcon#flushed, iclass 22, count 2 2006.257.03:06:52.02#ibcon#about to write, iclass 22, count 2 2006.257.03:06:52.02#ibcon#wrote, iclass 22, count 2 2006.257.03:06:52.02#ibcon#about to read 3, iclass 22, count 2 2006.257.03:06:52.04#ibcon#read 3, iclass 22, count 2 2006.257.03:06:52.04#ibcon#about to read 4, iclass 22, count 2 2006.257.03:06:52.04#ibcon#read 4, iclass 22, count 2 2006.257.03:06:52.04#ibcon#about to read 5, iclass 22, count 2 2006.257.03:06:52.04#ibcon#read 5, iclass 22, count 2 2006.257.03:06:52.04#ibcon#about to read 6, iclass 22, count 2 2006.257.03:06:52.04#ibcon#read 6, iclass 22, count 2 2006.257.03:06:52.04#ibcon#end of sib2, iclass 22, count 2 2006.257.03:06:52.04#ibcon#*mode == 0, iclass 22, count 2 2006.257.03:06:52.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.03:06:52.04#ibcon#[25=AT07-04\r\n] 2006.257.03:06:52.04#ibcon#*before write, iclass 22, count 2 2006.257.03:06:52.04#ibcon#enter sib2, iclass 22, count 2 2006.257.03:06:52.04#ibcon#flushed, iclass 22, count 2 2006.257.03:06:52.04#ibcon#about to write, iclass 22, count 2 2006.257.03:06:52.04#ibcon#wrote, iclass 22, count 2 2006.257.03:06:52.04#ibcon#about to read 3, iclass 22, count 2 2006.257.03:06:52.07#ibcon#read 3, iclass 22, count 2 2006.257.03:06:52.07#ibcon#about to read 4, iclass 22, count 2 2006.257.03:06:52.07#ibcon#read 4, iclass 22, count 2 2006.257.03:06:52.07#ibcon#about to read 5, iclass 22, count 2 2006.257.03:06:52.07#ibcon#read 5, iclass 22, count 2 2006.257.03:06:52.07#ibcon#about to read 6, iclass 22, count 2 2006.257.03:06:52.07#ibcon#read 6, iclass 22, count 2 2006.257.03:06:52.07#ibcon#end of sib2, iclass 22, count 2 2006.257.03:06:52.07#ibcon#*after write, iclass 22, count 2 2006.257.03:06:52.07#ibcon#*before return 0, iclass 22, count 2 2006.257.03:06:52.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:52.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:52.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.03:06:52.07#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:52.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:52.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:52.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:52.19#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:06:52.19#ibcon#first serial, iclass 22, count 0 2006.257.03:06:52.19#ibcon#enter sib2, iclass 22, count 0 2006.257.03:06:52.19#ibcon#flushed, iclass 22, count 0 2006.257.03:06:52.19#ibcon#about to write, iclass 22, count 0 2006.257.03:06:52.19#ibcon#wrote, iclass 22, count 0 2006.257.03:06:52.19#ibcon#about to read 3, iclass 22, count 0 2006.257.03:06:52.21#ibcon#read 3, iclass 22, count 0 2006.257.03:06:52.21#ibcon#about to read 4, iclass 22, count 0 2006.257.03:06:52.21#ibcon#read 4, iclass 22, count 0 2006.257.03:06:52.21#ibcon#about to read 5, iclass 22, count 0 2006.257.03:06:52.21#ibcon#read 5, iclass 22, count 0 2006.257.03:06:52.21#ibcon#about to read 6, iclass 22, count 0 2006.257.03:06:52.21#ibcon#read 6, iclass 22, count 0 2006.257.03:06:52.21#ibcon#end of sib2, iclass 22, count 0 2006.257.03:06:52.21#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:06:52.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:06:52.21#ibcon#[25=USB\r\n] 2006.257.03:06:52.21#ibcon#*before write, iclass 22, count 0 2006.257.03:06:52.21#ibcon#enter sib2, iclass 22, count 0 2006.257.03:06:52.21#ibcon#flushed, iclass 22, count 0 2006.257.03:06:52.21#ibcon#about to write, iclass 22, count 0 2006.257.03:06:52.21#ibcon#wrote, iclass 22, count 0 2006.257.03:06:52.21#ibcon#about to read 3, iclass 22, count 0 2006.257.03:06:52.24#ibcon#read 3, iclass 22, count 0 2006.257.03:06:52.24#ibcon#about to read 4, iclass 22, count 0 2006.257.03:06:52.24#ibcon#read 4, iclass 22, count 0 2006.257.03:06:52.24#ibcon#about to read 5, iclass 22, count 0 2006.257.03:06:52.24#ibcon#read 5, iclass 22, count 0 2006.257.03:06:52.24#ibcon#about to read 6, iclass 22, count 0 2006.257.03:06:52.24#ibcon#read 6, iclass 22, count 0 2006.257.03:06:52.24#ibcon#end of sib2, iclass 22, count 0 2006.257.03:06:52.24#ibcon#*after write, iclass 22, count 0 2006.257.03:06:52.24#ibcon#*before return 0, iclass 22, count 0 2006.257.03:06:52.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:52.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:52.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:06:52.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:06:52.24$vck44/valo=8,884.99 2006.257.03:06:52.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.03:06:52.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.03:06:52.24#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:52.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:52.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:52.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:52.24#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:06:52.24#ibcon#first serial, iclass 24, count 0 2006.257.03:06:52.24#ibcon#enter sib2, iclass 24, count 0 2006.257.03:06:52.24#ibcon#flushed, iclass 24, count 0 2006.257.03:06:52.24#ibcon#about to write, iclass 24, count 0 2006.257.03:06:52.24#ibcon#wrote, iclass 24, count 0 2006.257.03:06:52.24#ibcon#about to read 3, iclass 24, count 0 2006.257.03:06:52.26#ibcon#read 3, iclass 24, count 0 2006.257.03:06:52.26#ibcon#about to read 4, iclass 24, count 0 2006.257.03:06:52.26#ibcon#read 4, iclass 24, count 0 2006.257.03:06:52.26#ibcon#about to read 5, iclass 24, count 0 2006.257.03:06:52.26#ibcon#read 5, iclass 24, count 0 2006.257.03:06:52.26#ibcon#about to read 6, iclass 24, count 0 2006.257.03:06:52.26#ibcon#read 6, iclass 24, count 0 2006.257.03:06:52.26#ibcon#end of sib2, iclass 24, count 0 2006.257.03:06:52.26#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:06:52.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:06:52.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:06:52.26#ibcon#*before write, iclass 24, count 0 2006.257.03:06:52.26#ibcon#enter sib2, iclass 24, count 0 2006.257.03:06:52.26#ibcon#flushed, iclass 24, count 0 2006.257.03:06:52.26#ibcon#about to write, iclass 24, count 0 2006.257.03:06:52.26#ibcon#wrote, iclass 24, count 0 2006.257.03:06:52.26#ibcon#about to read 3, iclass 24, count 0 2006.257.03:06:52.30#ibcon#read 3, iclass 24, count 0 2006.257.03:06:52.30#ibcon#about to read 4, iclass 24, count 0 2006.257.03:06:52.30#ibcon#read 4, iclass 24, count 0 2006.257.03:06:52.30#ibcon#about to read 5, iclass 24, count 0 2006.257.03:06:52.30#ibcon#read 5, iclass 24, count 0 2006.257.03:06:52.30#ibcon#about to read 6, iclass 24, count 0 2006.257.03:06:52.30#ibcon#read 6, iclass 24, count 0 2006.257.03:06:52.30#ibcon#end of sib2, iclass 24, count 0 2006.257.03:06:52.30#ibcon#*after write, iclass 24, count 0 2006.257.03:06:52.30#ibcon#*before return 0, iclass 24, count 0 2006.257.03:06:52.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:52.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:52.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:06:52.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:06:52.30$vck44/va=8,4 2006.257.03:06:52.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.03:06:52.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.03:06:52.30#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:52.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:06:52.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:06:52.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:06:52.36#ibcon#enter wrdev, iclass 26, count 2 2006.257.03:06:52.36#ibcon#first serial, iclass 26, count 2 2006.257.03:06:52.36#ibcon#enter sib2, iclass 26, count 2 2006.257.03:06:52.36#ibcon#flushed, iclass 26, count 2 2006.257.03:06:52.36#ibcon#about to write, iclass 26, count 2 2006.257.03:06:52.36#ibcon#wrote, iclass 26, count 2 2006.257.03:06:52.36#ibcon#about to read 3, iclass 26, count 2 2006.257.03:06:52.38#ibcon#read 3, iclass 26, count 2 2006.257.03:06:52.38#ibcon#about to read 4, iclass 26, count 2 2006.257.03:06:52.38#ibcon#read 4, iclass 26, count 2 2006.257.03:06:52.38#ibcon#about to read 5, iclass 26, count 2 2006.257.03:06:52.38#ibcon#read 5, iclass 26, count 2 2006.257.03:06:52.38#ibcon#about to read 6, iclass 26, count 2 2006.257.03:06:52.38#ibcon#read 6, iclass 26, count 2 2006.257.03:06:52.38#ibcon#end of sib2, iclass 26, count 2 2006.257.03:06:52.38#ibcon#*mode == 0, iclass 26, count 2 2006.257.03:06:52.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.03:06:52.38#ibcon#[25=AT08-04\r\n] 2006.257.03:06:52.38#ibcon#*before write, iclass 26, count 2 2006.257.03:06:52.38#ibcon#enter sib2, iclass 26, count 2 2006.257.03:06:52.38#ibcon#flushed, iclass 26, count 2 2006.257.03:06:52.38#ibcon#about to write, iclass 26, count 2 2006.257.03:06:52.38#ibcon#wrote, iclass 26, count 2 2006.257.03:06:52.38#ibcon#about to read 3, iclass 26, count 2 2006.257.03:06:52.41#ibcon#read 3, iclass 26, count 2 2006.257.03:06:52.41#ibcon#about to read 4, iclass 26, count 2 2006.257.03:06:52.41#ibcon#read 4, iclass 26, count 2 2006.257.03:06:52.41#ibcon#about to read 5, iclass 26, count 2 2006.257.03:06:52.41#ibcon#read 5, iclass 26, count 2 2006.257.03:06:52.41#ibcon#about to read 6, iclass 26, count 2 2006.257.03:06:52.41#ibcon#read 6, iclass 26, count 2 2006.257.03:06:52.41#ibcon#end of sib2, iclass 26, count 2 2006.257.03:06:52.41#ibcon#*after write, iclass 26, count 2 2006.257.03:06:52.41#ibcon#*before return 0, iclass 26, count 2 2006.257.03:06:52.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:06:52.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:06:52.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.03:06:52.41#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:52.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:06:52.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:06:52.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:06:52.53#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:06:52.53#ibcon#first serial, iclass 26, count 0 2006.257.03:06:52.53#ibcon#enter sib2, iclass 26, count 0 2006.257.03:06:52.53#ibcon#flushed, iclass 26, count 0 2006.257.03:06:52.53#ibcon#about to write, iclass 26, count 0 2006.257.03:06:52.53#ibcon#wrote, iclass 26, count 0 2006.257.03:06:52.53#ibcon#about to read 3, iclass 26, count 0 2006.257.03:06:52.55#ibcon#read 3, iclass 26, count 0 2006.257.03:06:52.55#ibcon#about to read 4, iclass 26, count 0 2006.257.03:06:52.55#ibcon#read 4, iclass 26, count 0 2006.257.03:06:52.55#ibcon#about to read 5, iclass 26, count 0 2006.257.03:06:52.55#ibcon#read 5, iclass 26, count 0 2006.257.03:06:52.55#ibcon#about to read 6, iclass 26, count 0 2006.257.03:06:52.55#ibcon#read 6, iclass 26, count 0 2006.257.03:06:52.55#ibcon#end of sib2, iclass 26, count 0 2006.257.03:06:52.55#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:06:52.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:06:52.55#ibcon#[25=USB\r\n] 2006.257.03:06:52.55#ibcon#*before write, iclass 26, count 0 2006.257.03:06:52.55#ibcon#enter sib2, iclass 26, count 0 2006.257.03:06:52.55#ibcon#flushed, iclass 26, count 0 2006.257.03:06:52.55#ibcon#about to write, iclass 26, count 0 2006.257.03:06:52.55#ibcon#wrote, iclass 26, count 0 2006.257.03:06:52.55#ibcon#about to read 3, iclass 26, count 0 2006.257.03:06:52.58#ibcon#read 3, iclass 26, count 0 2006.257.03:06:52.58#ibcon#about to read 4, iclass 26, count 0 2006.257.03:06:52.58#ibcon#read 4, iclass 26, count 0 2006.257.03:06:52.58#ibcon#about to read 5, iclass 26, count 0 2006.257.03:06:52.58#ibcon#read 5, iclass 26, count 0 2006.257.03:06:52.58#ibcon#about to read 6, iclass 26, count 0 2006.257.03:06:52.58#ibcon#read 6, iclass 26, count 0 2006.257.03:06:52.58#ibcon#end of sib2, iclass 26, count 0 2006.257.03:06:52.58#ibcon#*after write, iclass 26, count 0 2006.257.03:06:52.58#ibcon#*before return 0, iclass 26, count 0 2006.257.03:06:52.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:06:52.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:06:52.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:06:52.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:06:52.58$vck44/vblo=1,629.99 2006.257.03:06:52.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.03:06:52.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.03:06:52.58#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:52.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:06:52.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:06:52.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:06:52.58#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:06:52.58#ibcon#first serial, iclass 28, count 0 2006.257.03:06:52.58#ibcon#enter sib2, iclass 28, count 0 2006.257.03:06:52.58#ibcon#flushed, iclass 28, count 0 2006.257.03:06:52.58#ibcon#about to write, iclass 28, count 0 2006.257.03:06:52.58#ibcon#wrote, iclass 28, count 0 2006.257.03:06:52.58#ibcon#about to read 3, iclass 28, count 0 2006.257.03:06:52.60#ibcon#read 3, iclass 28, count 0 2006.257.03:06:52.60#ibcon#about to read 4, iclass 28, count 0 2006.257.03:06:52.60#ibcon#read 4, iclass 28, count 0 2006.257.03:06:52.60#ibcon#about to read 5, iclass 28, count 0 2006.257.03:06:52.60#ibcon#read 5, iclass 28, count 0 2006.257.03:06:52.60#ibcon#about to read 6, iclass 28, count 0 2006.257.03:06:52.60#ibcon#read 6, iclass 28, count 0 2006.257.03:06:52.60#ibcon#end of sib2, iclass 28, count 0 2006.257.03:06:52.60#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:06:52.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:06:52.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:06:52.60#ibcon#*before write, iclass 28, count 0 2006.257.03:06:52.60#ibcon#enter sib2, iclass 28, count 0 2006.257.03:06:52.60#ibcon#flushed, iclass 28, count 0 2006.257.03:06:52.60#ibcon#about to write, iclass 28, count 0 2006.257.03:06:52.60#ibcon#wrote, iclass 28, count 0 2006.257.03:06:52.60#ibcon#about to read 3, iclass 28, count 0 2006.257.03:06:52.64#ibcon#read 3, iclass 28, count 0 2006.257.03:06:52.64#ibcon#about to read 4, iclass 28, count 0 2006.257.03:06:52.64#ibcon#read 4, iclass 28, count 0 2006.257.03:06:52.64#ibcon#about to read 5, iclass 28, count 0 2006.257.03:06:52.64#ibcon#read 5, iclass 28, count 0 2006.257.03:06:52.64#ibcon#about to read 6, iclass 28, count 0 2006.257.03:06:52.64#ibcon#read 6, iclass 28, count 0 2006.257.03:06:52.64#ibcon#end of sib2, iclass 28, count 0 2006.257.03:06:52.64#ibcon#*after write, iclass 28, count 0 2006.257.03:06:52.64#ibcon#*before return 0, iclass 28, count 0 2006.257.03:06:52.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:06:52.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:06:52.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:06:52.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:06:52.64$vck44/vb=1,4 2006.257.03:06:52.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.03:06:52.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.03:06:52.64#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:52.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:06:52.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:06:52.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:06:52.64#ibcon#enter wrdev, iclass 30, count 2 2006.257.03:06:52.64#ibcon#first serial, iclass 30, count 2 2006.257.03:06:52.64#ibcon#enter sib2, iclass 30, count 2 2006.257.03:06:52.64#ibcon#flushed, iclass 30, count 2 2006.257.03:06:52.64#ibcon#about to write, iclass 30, count 2 2006.257.03:06:52.64#ibcon#wrote, iclass 30, count 2 2006.257.03:06:52.64#ibcon#about to read 3, iclass 30, count 2 2006.257.03:06:52.66#ibcon#read 3, iclass 30, count 2 2006.257.03:06:52.66#ibcon#about to read 4, iclass 30, count 2 2006.257.03:06:52.66#ibcon#read 4, iclass 30, count 2 2006.257.03:06:52.66#ibcon#about to read 5, iclass 30, count 2 2006.257.03:06:52.66#ibcon#read 5, iclass 30, count 2 2006.257.03:06:52.66#ibcon#about to read 6, iclass 30, count 2 2006.257.03:06:52.66#ibcon#read 6, iclass 30, count 2 2006.257.03:06:52.66#ibcon#end of sib2, iclass 30, count 2 2006.257.03:06:52.66#ibcon#*mode == 0, iclass 30, count 2 2006.257.03:06:52.66#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.03:06:52.66#ibcon#[27=AT01-04\r\n] 2006.257.03:06:52.66#ibcon#*before write, iclass 30, count 2 2006.257.03:06:52.66#ibcon#enter sib2, iclass 30, count 2 2006.257.03:06:52.66#ibcon#flushed, iclass 30, count 2 2006.257.03:06:52.66#ibcon#about to write, iclass 30, count 2 2006.257.03:06:52.66#ibcon#wrote, iclass 30, count 2 2006.257.03:06:52.66#ibcon#about to read 3, iclass 30, count 2 2006.257.03:06:52.70#ibcon#read 3, iclass 30, count 2 2006.257.03:06:52.70#ibcon#about to read 4, iclass 30, count 2 2006.257.03:06:52.70#ibcon#read 4, iclass 30, count 2 2006.257.03:06:52.70#ibcon#about to read 5, iclass 30, count 2 2006.257.03:06:52.70#ibcon#read 5, iclass 30, count 2 2006.257.03:06:52.70#ibcon#about to read 6, iclass 30, count 2 2006.257.03:06:52.70#ibcon#read 6, iclass 30, count 2 2006.257.03:06:52.70#ibcon#end of sib2, iclass 30, count 2 2006.257.03:06:52.70#ibcon#*after write, iclass 30, count 2 2006.257.03:06:52.70#ibcon#*before return 0, iclass 30, count 2 2006.257.03:06:52.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:06:52.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:06:52.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.03:06:52.70#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:52.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:06:52.81#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:06:52.81#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:06:52.81#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:06:52.81#ibcon#first serial, iclass 30, count 0 2006.257.03:06:52.81#ibcon#enter sib2, iclass 30, count 0 2006.257.03:06:52.81#ibcon#flushed, iclass 30, count 0 2006.257.03:06:52.81#ibcon#about to write, iclass 30, count 0 2006.257.03:06:52.81#ibcon#wrote, iclass 30, count 0 2006.257.03:06:52.81#ibcon#about to read 3, iclass 30, count 0 2006.257.03:06:52.83#ibcon#read 3, iclass 30, count 0 2006.257.03:06:52.83#ibcon#about to read 4, iclass 30, count 0 2006.257.03:06:52.83#ibcon#read 4, iclass 30, count 0 2006.257.03:06:52.83#ibcon#about to read 5, iclass 30, count 0 2006.257.03:06:52.83#ibcon#read 5, iclass 30, count 0 2006.257.03:06:52.83#ibcon#about to read 6, iclass 30, count 0 2006.257.03:06:52.83#ibcon#read 6, iclass 30, count 0 2006.257.03:06:52.83#ibcon#end of sib2, iclass 30, count 0 2006.257.03:06:52.83#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:06:52.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:06:52.83#ibcon#[27=USB\r\n] 2006.257.03:06:52.83#ibcon#*before write, iclass 30, count 0 2006.257.03:06:52.83#ibcon#enter sib2, iclass 30, count 0 2006.257.03:06:52.83#ibcon#flushed, iclass 30, count 0 2006.257.03:06:52.83#ibcon#about to write, iclass 30, count 0 2006.257.03:06:52.83#ibcon#wrote, iclass 30, count 0 2006.257.03:06:52.83#ibcon#about to read 3, iclass 30, count 0 2006.257.03:06:52.86#ibcon#read 3, iclass 30, count 0 2006.257.03:06:52.86#ibcon#about to read 4, iclass 30, count 0 2006.257.03:06:52.86#ibcon#read 4, iclass 30, count 0 2006.257.03:06:52.86#ibcon#about to read 5, iclass 30, count 0 2006.257.03:06:52.86#ibcon#read 5, iclass 30, count 0 2006.257.03:06:52.86#ibcon#about to read 6, iclass 30, count 0 2006.257.03:06:52.86#ibcon#read 6, iclass 30, count 0 2006.257.03:06:52.86#ibcon#end of sib2, iclass 30, count 0 2006.257.03:06:52.86#ibcon#*after write, iclass 30, count 0 2006.257.03:06:52.86#ibcon#*before return 0, iclass 30, count 0 2006.257.03:06:52.86#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:06:52.86#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:06:52.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:06:52.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:06:52.86$vck44/vblo=2,634.99 2006.257.03:06:52.86#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.03:06:52.86#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.03:06:52.86#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:52.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:52.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:52.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:52.86#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:06:52.86#ibcon#first serial, iclass 32, count 0 2006.257.03:06:52.86#ibcon#enter sib2, iclass 32, count 0 2006.257.03:06:52.86#ibcon#flushed, iclass 32, count 0 2006.257.03:06:52.86#ibcon#about to write, iclass 32, count 0 2006.257.03:06:52.86#ibcon#wrote, iclass 32, count 0 2006.257.03:06:52.86#ibcon#about to read 3, iclass 32, count 0 2006.257.03:06:52.88#ibcon#read 3, iclass 32, count 0 2006.257.03:06:52.88#ibcon#about to read 4, iclass 32, count 0 2006.257.03:06:52.88#ibcon#read 4, iclass 32, count 0 2006.257.03:06:52.88#ibcon#about to read 5, iclass 32, count 0 2006.257.03:06:52.88#ibcon#read 5, iclass 32, count 0 2006.257.03:06:52.88#ibcon#about to read 6, iclass 32, count 0 2006.257.03:06:52.88#ibcon#read 6, iclass 32, count 0 2006.257.03:06:52.88#ibcon#end of sib2, iclass 32, count 0 2006.257.03:06:52.88#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:06:52.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:06:52.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:06:52.88#ibcon#*before write, iclass 32, count 0 2006.257.03:06:52.88#ibcon#enter sib2, iclass 32, count 0 2006.257.03:06:52.88#ibcon#flushed, iclass 32, count 0 2006.257.03:06:52.88#ibcon#about to write, iclass 32, count 0 2006.257.03:06:52.88#ibcon#wrote, iclass 32, count 0 2006.257.03:06:52.88#ibcon#about to read 3, iclass 32, count 0 2006.257.03:06:52.92#ibcon#read 3, iclass 32, count 0 2006.257.03:06:52.92#ibcon#about to read 4, iclass 32, count 0 2006.257.03:06:52.92#ibcon#read 4, iclass 32, count 0 2006.257.03:06:52.92#ibcon#about to read 5, iclass 32, count 0 2006.257.03:06:52.92#ibcon#read 5, iclass 32, count 0 2006.257.03:06:52.92#ibcon#about to read 6, iclass 32, count 0 2006.257.03:06:52.92#ibcon#read 6, iclass 32, count 0 2006.257.03:06:52.92#ibcon#end of sib2, iclass 32, count 0 2006.257.03:06:52.92#ibcon#*after write, iclass 32, count 0 2006.257.03:06:52.92#ibcon#*before return 0, iclass 32, count 0 2006.257.03:06:52.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:52.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:06:52.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:06:52.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:06:52.92$vck44/vb=2,5 2006.257.03:06:52.92#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.03:06:52.92#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.03:06:52.92#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:52.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:52.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:52.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:52.98#ibcon#enter wrdev, iclass 34, count 2 2006.257.03:06:52.98#ibcon#first serial, iclass 34, count 2 2006.257.03:06:52.98#ibcon#enter sib2, iclass 34, count 2 2006.257.03:06:52.98#ibcon#flushed, iclass 34, count 2 2006.257.03:06:52.98#ibcon#about to write, iclass 34, count 2 2006.257.03:06:52.98#ibcon#wrote, iclass 34, count 2 2006.257.03:06:52.98#ibcon#about to read 3, iclass 34, count 2 2006.257.03:06:53.00#ibcon#read 3, iclass 34, count 2 2006.257.03:06:53.00#ibcon#about to read 4, iclass 34, count 2 2006.257.03:06:53.00#ibcon#read 4, iclass 34, count 2 2006.257.03:06:53.00#ibcon#about to read 5, iclass 34, count 2 2006.257.03:06:53.00#ibcon#read 5, iclass 34, count 2 2006.257.03:06:53.00#ibcon#about to read 6, iclass 34, count 2 2006.257.03:06:53.00#ibcon#read 6, iclass 34, count 2 2006.257.03:06:53.00#ibcon#end of sib2, iclass 34, count 2 2006.257.03:06:53.00#ibcon#*mode == 0, iclass 34, count 2 2006.257.03:06:53.00#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.03:06:53.00#ibcon#[27=AT02-05\r\n] 2006.257.03:06:53.00#ibcon#*before write, iclass 34, count 2 2006.257.03:06:53.00#ibcon#enter sib2, iclass 34, count 2 2006.257.03:06:53.00#ibcon#flushed, iclass 34, count 2 2006.257.03:06:53.00#ibcon#about to write, iclass 34, count 2 2006.257.03:06:53.00#ibcon#wrote, iclass 34, count 2 2006.257.03:06:53.00#ibcon#about to read 3, iclass 34, count 2 2006.257.03:06:53.03#ibcon#read 3, iclass 34, count 2 2006.257.03:06:53.03#ibcon#about to read 4, iclass 34, count 2 2006.257.03:06:53.03#ibcon#read 4, iclass 34, count 2 2006.257.03:06:53.03#ibcon#about to read 5, iclass 34, count 2 2006.257.03:06:53.03#ibcon#read 5, iclass 34, count 2 2006.257.03:06:53.03#ibcon#about to read 6, iclass 34, count 2 2006.257.03:06:53.03#ibcon#read 6, iclass 34, count 2 2006.257.03:06:53.03#ibcon#end of sib2, iclass 34, count 2 2006.257.03:06:53.03#ibcon#*after write, iclass 34, count 2 2006.257.03:06:53.03#ibcon#*before return 0, iclass 34, count 2 2006.257.03:06:53.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:53.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:06:53.03#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.03:06:53.03#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:53.03#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:53.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:53.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:53.15#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:06:53.15#ibcon#first serial, iclass 34, count 0 2006.257.03:06:53.15#ibcon#enter sib2, iclass 34, count 0 2006.257.03:06:53.15#ibcon#flushed, iclass 34, count 0 2006.257.03:06:53.15#ibcon#about to write, iclass 34, count 0 2006.257.03:06:53.15#ibcon#wrote, iclass 34, count 0 2006.257.03:06:53.15#ibcon#about to read 3, iclass 34, count 0 2006.257.03:06:53.17#ibcon#read 3, iclass 34, count 0 2006.257.03:06:53.17#ibcon#about to read 4, iclass 34, count 0 2006.257.03:06:53.17#ibcon#read 4, iclass 34, count 0 2006.257.03:06:53.17#ibcon#about to read 5, iclass 34, count 0 2006.257.03:06:53.17#ibcon#read 5, iclass 34, count 0 2006.257.03:06:53.17#ibcon#about to read 6, iclass 34, count 0 2006.257.03:06:53.17#ibcon#read 6, iclass 34, count 0 2006.257.03:06:53.17#ibcon#end of sib2, iclass 34, count 0 2006.257.03:06:53.17#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:06:53.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:06:53.17#ibcon#[27=USB\r\n] 2006.257.03:06:53.17#ibcon#*before write, iclass 34, count 0 2006.257.03:06:53.17#ibcon#enter sib2, iclass 34, count 0 2006.257.03:06:53.17#ibcon#flushed, iclass 34, count 0 2006.257.03:06:53.17#ibcon#about to write, iclass 34, count 0 2006.257.03:06:53.17#ibcon#wrote, iclass 34, count 0 2006.257.03:06:53.17#ibcon#about to read 3, iclass 34, count 0 2006.257.03:06:53.20#ibcon#read 3, iclass 34, count 0 2006.257.03:06:53.20#ibcon#about to read 4, iclass 34, count 0 2006.257.03:06:53.20#ibcon#read 4, iclass 34, count 0 2006.257.03:06:53.20#ibcon#about to read 5, iclass 34, count 0 2006.257.03:06:53.20#ibcon#read 5, iclass 34, count 0 2006.257.03:06:53.20#ibcon#about to read 6, iclass 34, count 0 2006.257.03:06:53.20#ibcon#read 6, iclass 34, count 0 2006.257.03:06:53.20#ibcon#end of sib2, iclass 34, count 0 2006.257.03:06:53.20#ibcon#*after write, iclass 34, count 0 2006.257.03:06:53.20#ibcon#*before return 0, iclass 34, count 0 2006.257.03:06:53.20#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:53.20#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:06:53.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:06:53.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:06:53.20$vck44/vblo=3,649.99 2006.257.03:06:53.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.03:06:53.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.03:06:53.20#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:53.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:53.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:53.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:53.20#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:06:53.20#ibcon#first serial, iclass 36, count 0 2006.257.03:06:53.20#ibcon#enter sib2, iclass 36, count 0 2006.257.03:06:53.20#ibcon#flushed, iclass 36, count 0 2006.257.03:06:53.20#ibcon#about to write, iclass 36, count 0 2006.257.03:06:53.20#ibcon#wrote, iclass 36, count 0 2006.257.03:06:53.20#ibcon#about to read 3, iclass 36, count 0 2006.257.03:06:53.22#ibcon#read 3, iclass 36, count 0 2006.257.03:06:53.22#ibcon#about to read 4, iclass 36, count 0 2006.257.03:06:53.22#ibcon#read 4, iclass 36, count 0 2006.257.03:06:53.22#ibcon#about to read 5, iclass 36, count 0 2006.257.03:06:53.22#ibcon#read 5, iclass 36, count 0 2006.257.03:06:53.22#ibcon#about to read 6, iclass 36, count 0 2006.257.03:06:53.22#ibcon#read 6, iclass 36, count 0 2006.257.03:06:53.22#ibcon#end of sib2, iclass 36, count 0 2006.257.03:06:53.22#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:06:53.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:06:53.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:06:53.22#ibcon#*before write, iclass 36, count 0 2006.257.03:06:53.22#ibcon#enter sib2, iclass 36, count 0 2006.257.03:06:53.22#ibcon#flushed, iclass 36, count 0 2006.257.03:06:53.22#ibcon#about to write, iclass 36, count 0 2006.257.03:06:53.22#ibcon#wrote, iclass 36, count 0 2006.257.03:06:53.22#ibcon#about to read 3, iclass 36, count 0 2006.257.03:06:53.26#ibcon#read 3, iclass 36, count 0 2006.257.03:06:53.26#ibcon#about to read 4, iclass 36, count 0 2006.257.03:06:53.26#ibcon#read 4, iclass 36, count 0 2006.257.03:06:53.26#ibcon#about to read 5, iclass 36, count 0 2006.257.03:06:53.26#ibcon#read 5, iclass 36, count 0 2006.257.03:06:53.26#ibcon#about to read 6, iclass 36, count 0 2006.257.03:06:53.26#ibcon#read 6, iclass 36, count 0 2006.257.03:06:53.26#ibcon#end of sib2, iclass 36, count 0 2006.257.03:06:53.26#ibcon#*after write, iclass 36, count 0 2006.257.03:06:53.26#ibcon#*before return 0, iclass 36, count 0 2006.257.03:06:53.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:53.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:06:53.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:06:53.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:06:53.26$vck44/vb=3,4 2006.257.03:06:53.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.03:06:53.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.03:06:53.26#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:53.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:53.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:53.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:53.32#ibcon#enter wrdev, iclass 38, count 2 2006.257.03:06:53.32#ibcon#first serial, iclass 38, count 2 2006.257.03:06:53.32#ibcon#enter sib2, iclass 38, count 2 2006.257.03:06:53.32#ibcon#flushed, iclass 38, count 2 2006.257.03:06:53.32#ibcon#about to write, iclass 38, count 2 2006.257.03:06:53.32#ibcon#wrote, iclass 38, count 2 2006.257.03:06:53.32#ibcon#about to read 3, iclass 38, count 2 2006.257.03:06:53.34#ibcon#read 3, iclass 38, count 2 2006.257.03:06:53.34#ibcon#about to read 4, iclass 38, count 2 2006.257.03:06:53.34#ibcon#read 4, iclass 38, count 2 2006.257.03:06:53.34#ibcon#about to read 5, iclass 38, count 2 2006.257.03:06:53.34#ibcon#read 5, iclass 38, count 2 2006.257.03:06:53.34#ibcon#about to read 6, iclass 38, count 2 2006.257.03:06:53.34#ibcon#read 6, iclass 38, count 2 2006.257.03:06:53.34#ibcon#end of sib2, iclass 38, count 2 2006.257.03:06:53.34#ibcon#*mode == 0, iclass 38, count 2 2006.257.03:06:53.34#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.03:06:53.34#ibcon#[27=AT03-04\r\n] 2006.257.03:06:53.34#ibcon#*before write, iclass 38, count 2 2006.257.03:06:53.34#ibcon#enter sib2, iclass 38, count 2 2006.257.03:06:53.34#ibcon#flushed, iclass 38, count 2 2006.257.03:06:53.34#ibcon#about to write, iclass 38, count 2 2006.257.03:06:53.34#ibcon#wrote, iclass 38, count 2 2006.257.03:06:53.34#ibcon#about to read 3, iclass 38, count 2 2006.257.03:06:53.37#ibcon#read 3, iclass 38, count 2 2006.257.03:06:53.37#ibcon#about to read 4, iclass 38, count 2 2006.257.03:06:53.37#ibcon#read 4, iclass 38, count 2 2006.257.03:06:53.37#ibcon#about to read 5, iclass 38, count 2 2006.257.03:06:53.37#ibcon#read 5, iclass 38, count 2 2006.257.03:06:53.37#ibcon#about to read 6, iclass 38, count 2 2006.257.03:06:53.37#ibcon#read 6, iclass 38, count 2 2006.257.03:06:53.37#ibcon#end of sib2, iclass 38, count 2 2006.257.03:06:53.37#ibcon#*after write, iclass 38, count 2 2006.257.03:06:53.37#ibcon#*before return 0, iclass 38, count 2 2006.257.03:06:53.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:53.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:06:53.37#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.03:06:53.37#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:53.37#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:53.49#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:53.49#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:53.49#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:06:53.49#ibcon#first serial, iclass 38, count 0 2006.257.03:06:53.49#ibcon#enter sib2, iclass 38, count 0 2006.257.03:06:53.49#ibcon#flushed, iclass 38, count 0 2006.257.03:06:53.49#ibcon#about to write, iclass 38, count 0 2006.257.03:06:53.49#ibcon#wrote, iclass 38, count 0 2006.257.03:06:53.49#ibcon#about to read 3, iclass 38, count 0 2006.257.03:06:53.51#ibcon#read 3, iclass 38, count 0 2006.257.03:06:53.51#ibcon#about to read 4, iclass 38, count 0 2006.257.03:06:53.51#ibcon#read 4, iclass 38, count 0 2006.257.03:06:53.51#ibcon#about to read 5, iclass 38, count 0 2006.257.03:06:53.51#ibcon#read 5, iclass 38, count 0 2006.257.03:06:53.51#ibcon#about to read 6, iclass 38, count 0 2006.257.03:06:53.51#ibcon#read 6, iclass 38, count 0 2006.257.03:06:53.51#ibcon#end of sib2, iclass 38, count 0 2006.257.03:06:53.51#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:06:53.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:06:53.51#ibcon#[27=USB\r\n] 2006.257.03:06:53.51#ibcon#*before write, iclass 38, count 0 2006.257.03:06:53.51#ibcon#enter sib2, iclass 38, count 0 2006.257.03:06:53.51#ibcon#flushed, iclass 38, count 0 2006.257.03:06:53.51#ibcon#about to write, iclass 38, count 0 2006.257.03:06:53.51#ibcon#wrote, iclass 38, count 0 2006.257.03:06:53.51#ibcon#about to read 3, iclass 38, count 0 2006.257.03:06:53.54#ibcon#read 3, iclass 38, count 0 2006.257.03:06:53.54#ibcon#about to read 4, iclass 38, count 0 2006.257.03:06:53.54#ibcon#read 4, iclass 38, count 0 2006.257.03:06:53.54#ibcon#about to read 5, iclass 38, count 0 2006.257.03:06:53.54#ibcon#read 5, iclass 38, count 0 2006.257.03:06:53.54#ibcon#about to read 6, iclass 38, count 0 2006.257.03:06:53.54#ibcon#read 6, iclass 38, count 0 2006.257.03:06:53.54#ibcon#end of sib2, iclass 38, count 0 2006.257.03:06:53.54#ibcon#*after write, iclass 38, count 0 2006.257.03:06:53.54#ibcon#*before return 0, iclass 38, count 0 2006.257.03:06:53.54#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:53.54#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:06:53.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:06:53.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:06:53.54$vck44/vblo=4,679.99 2006.257.03:06:53.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.03:06:53.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.03:06:53.54#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:53.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:53.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:53.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:53.54#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:06:53.54#ibcon#first serial, iclass 40, count 0 2006.257.03:06:53.54#ibcon#enter sib2, iclass 40, count 0 2006.257.03:06:53.54#ibcon#flushed, iclass 40, count 0 2006.257.03:06:53.54#ibcon#about to write, iclass 40, count 0 2006.257.03:06:53.54#ibcon#wrote, iclass 40, count 0 2006.257.03:06:53.54#ibcon#about to read 3, iclass 40, count 0 2006.257.03:06:53.56#ibcon#read 3, iclass 40, count 0 2006.257.03:06:53.56#ibcon#about to read 4, iclass 40, count 0 2006.257.03:06:53.56#ibcon#read 4, iclass 40, count 0 2006.257.03:06:53.56#ibcon#about to read 5, iclass 40, count 0 2006.257.03:06:53.56#ibcon#read 5, iclass 40, count 0 2006.257.03:06:53.56#ibcon#about to read 6, iclass 40, count 0 2006.257.03:06:53.56#ibcon#read 6, iclass 40, count 0 2006.257.03:06:53.56#ibcon#end of sib2, iclass 40, count 0 2006.257.03:06:53.56#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:06:53.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:06:53.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:06:53.56#ibcon#*before write, iclass 40, count 0 2006.257.03:06:53.56#ibcon#enter sib2, iclass 40, count 0 2006.257.03:06:53.56#ibcon#flushed, iclass 40, count 0 2006.257.03:06:53.56#ibcon#about to write, iclass 40, count 0 2006.257.03:06:53.56#ibcon#wrote, iclass 40, count 0 2006.257.03:06:53.56#ibcon#about to read 3, iclass 40, count 0 2006.257.03:06:53.60#ibcon#read 3, iclass 40, count 0 2006.257.03:06:53.60#ibcon#about to read 4, iclass 40, count 0 2006.257.03:06:53.60#ibcon#read 4, iclass 40, count 0 2006.257.03:06:53.60#ibcon#about to read 5, iclass 40, count 0 2006.257.03:06:53.60#ibcon#read 5, iclass 40, count 0 2006.257.03:06:53.60#ibcon#about to read 6, iclass 40, count 0 2006.257.03:06:53.60#ibcon#read 6, iclass 40, count 0 2006.257.03:06:53.60#ibcon#end of sib2, iclass 40, count 0 2006.257.03:06:53.60#ibcon#*after write, iclass 40, count 0 2006.257.03:06:53.60#ibcon#*before return 0, iclass 40, count 0 2006.257.03:06:53.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:53.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:06:53.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:06:53.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:06:53.60$vck44/vb=4,5 2006.257.03:06:53.60#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.03:06:53.60#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.03:06:53.60#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:53.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:53.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:53.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:53.66#ibcon#enter wrdev, iclass 4, count 2 2006.257.03:06:53.66#ibcon#first serial, iclass 4, count 2 2006.257.03:06:53.66#ibcon#enter sib2, iclass 4, count 2 2006.257.03:06:53.66#ibcon#flushed, iclass 4, count 2 2006.257.03:06:53.66#ibcon#about to write, iclass 4, count 2 2006.257.03:06:53.66#ibcon#wrote, iclass 4, count 2 2006.257.03:06:53.66#ibcon#about to read 3, iclass 4, count 2 2006.257.03:06:53.68#ibcon#read 3, iclass 4, count 2 2006.257.03:06:53.68#ibcon#about to read 4, iclass 4, count 2 2006.257.03:06:53.68#ibcon#read 4, iclass 4, count 2 2006.257.03:06:53.68#ibcon#about to read 5, iclass 4, count 2 2006.257.03:06:53.68#ibcon#read 5, iclass 4, count 2 2006.257.03:06:53.68#ibcon#about to read 6, iclass 4, count 2 2006.257.03:06:53.68#ibcon#read 6, iclass 4, count 2 2006.257.03:06:53.68#ibcon#end of sib2, iclass 4, count 2 2006.257.03:06:53.68#ibcon#*mode == 0, iclass 4, count 2 2006.257.03:06:53.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.03:06:53.68#ibcon#[27=AT04-05\r\n] 2006.257.03:06:53.68#ibcon#*before write, iclass 4, count 2 2006.257.03:06:53.68#ibcon#enter sib2, iclass 4, count 2 2006.257.03:06:53.68#ibcon#flushed, iclass 4, count 2 2006.257.03:06:53.68#ibcon#about to write, iclass 4, count 2 2006.257.03:06:53.68#ibcon#wrote, iclass 4, count 2 2006.257.03:06:53.68#ibcon#about to read 3, iclass 4, count 2 2006.257.03:06:53.71#ibcon#read 3, iclass 4, count 2 2006.257.03:06:53.71#ibcon#about to read 4, iclass 4, count 2 2006.257.03:06:53.71#ibcon#read 4, iclass 4, count 2 2006.257.03:06:53.71#ibcon#about to read 5, iclass 4, count 2 2006.257.03:06:53.71#ibcon#read 5, iclass 4, count 2 2006.257.03:06:53.71#ibcon#about to read 6, iclass 4, count 2 2006.257.03:06:53.71#ibcon#read 6, iclass 4, count 2 2006.257.03:06:53.71#ibcon#end of sib2, iclass 4, count 2 2006.257.03:06:53.71#ibcon#*after write, iclass 4, count 2 2006.257.03:06:53.71#ibcon#*before return 0, iclass 4, count 2 2006.257.03:06:53.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:53.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:06:53.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.03:06:53.71#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:53.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:53.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:53.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:53.83#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:06:53.83#ibcon#first serial, iclass 4, count 0 2006.257.03:06:53.83#ibcon#enter sib2, iclass 4, count 0 2006.257.03:06:53.83#ibcon#flushed, iclass 4, count 0 2006.257.03:06:53.83#ibcon#about to write, iclass 4, count 0 2006.257.03:06:53.83#ibcon#wrote, iclass 4, count 0 2006.257.03:06:53.83#ibcon#about to read 3, iclass 4, count 0 2006.257.03:06:53.85#ibcon#read 3, iclass 4, count 0 2006.257.03:06:53.85#ibcon#about to read 4, iclass 4, count 0 2006.257.03:06:53.85#ibcon#read 4, iclass 4, count 0 2006.257.03:06:53.85#ibcon#about to read 5, iclass 4, count 0 2006.257.03:06:53.85#ibcon#read 5, iclass 4, count 0 2006.257.03:06:53.85#ibcon#about to read 6, iclass 4, count 0 2006.257.03:06:53.85#ibcon#read 6, iclass 4, count 0 2006.257.03:06:53.85#ibcon#end of sib2, iclass 4, count 0 2006.257.03:06:53.85#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:06:53.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:06:53.85#ibcon#[27=USB\r\n] 2006.257.03:06:53.85#ibcon#*before write, iclass 4, count 0 2006.257.03:06:53.85#ibcon#enter sib2, iclass 4, count 0 2006.257.03:06:53.85#ibcon#flushed, iclass 4, count 0 2006.257.03:06:53.85#ibcon#about to write, iclass 4, count 0 2006.257.03:06:53.85#ibcon#wrote, iclass 4, count 0 2006.257.03:06:53.85#ibcon#about to read 3, iclass 4, count 0 2006.257.03:06:53.88#ibcon#read 3, iclass 4, count 0 2006.257.03:06:53.88#ibcon#about to read 4, iclass 4, count 0 2006.257.03:06:53.88#ibcon#read 4, iclass 4, count 0 2006.257.03:06:53.88#ibcon#about to read 5, iclass 4, count 0 2006.257.03:06:53.88#ibcon#read 5, iclass 4, count 0 2006.257.03:06:53.88#ibcon#about to read 6, iclass 4, count 0 2006.257.03:06:53.88#ibcon#read 6, iclass 4, count 0 2006.257.03:06:53.88#ibcon#end of sib2, iclass 4, count 0 2006.257.03:06:53.88#ibcon#*after write, iclass 4, count 0 2006.257.03:06:53.88#ibcon#*before return 0, iclass 4, count 0 2006.257.03:06:53.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:53.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:06:53.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:06:53.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:06:53.88$vck44/vblo=5,709.99 2006.257.03:06:53.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.03:06:53.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.03:06:53.88#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:53.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:53.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:53.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:53.88#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:06:53.88#ibcon#first serial, iclass 6, count 0 2006.257.03:06:53.88#ibcon#enter sib2, iclass 6, count 0 2006.257.03:06:53.88#ibcon#flushed, iclass 6, count 0 2006.257.03:06:53.88#ibcon#about to write, iclass 6, count 0 2006.257.03:06:53.88#ibcon#wrote, iclass 6, count 0 2006.257.03:06:53.88#ibcon#about to read 3, iclass 6, count 0 2006.257.03:06:53.90#ibcon#read 3, iclass 6, count 0 2006.257.03:06:53.90#ibcon#about to read 4, iclass 6, count 0 2006.257.03:06:53.90#ibcon#read 4, iclass 6, count 0 2006.257.03:06:53.90#ibcon#about to read 5, iclass 6, count 0 2006.257.03:06:53.90#ibcon#read 5, iclass 6, count 0 2006.257.03:06:53.90#ibcon#about to read 6, iclass 6, count 0 2006.257.03:06:53.90#ibcon#read 6, iclass 6, count 0 2006.257.03:06:53.90#ibcon#end of sib2, iclass 6, count 0 2006.257.03:06:53.90#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:06:53.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:06:53.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:06:53.90#ibcon#*before write, iclass 6, count 0 2006.257.03:06:53.90#ibcon#enter sib2, iclass 6, count 0 2006.257.03:06:53.90#ibcon#flushed, iclass 6, count 0 2006.257.03:06:53.90#ibcon#about to write, iclass 6, count 0 2006.257.03:06:53.90#ibcon#wrote, iclass 6, count 0 2006.257.03:06:53.90#ibcon#about to read 3, iclass 6, count 0 2006.257.03:06:53.94#ibcon#read 3, iclass 6, count 0 2006.257.03:06:53.94#ibcon#about to read 4, iclass 6, count 0 2006.257.03:06:53.94#ibcon#read 4, iclass 6, count 0 2006.257.03:06:53.94#ibcon#about to read 5, iclass 6, count 0 2006.257.03:06:53.94#ibcon#read 5, iclass 6, count 0 2006.257.03:06:53.94#ibcon#about to read 6, iclass 6, count 0 2006.257.03:06:53.94#ibcon#read 6, iclass 6, count 0 2006.257.03:06:53.94#ibcon#end of sib2, iclass 6, count 0 2006.257.03:06:53.94#ibcon#*after write, iclass 6, count 0 2006.257.03:06:53.94#ibcon#*before return 0, iclass 6, count 0 2006.257.03:06:53.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:53.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:06:53.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:06:53.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:06:53.94$vck44/vb=5,4 2006.257.03:06:53.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.03:06:53.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.03:06:53.94#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:53.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:54.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:54.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:54.00#ibcon#enter wrdev, iclass 10, count 2 2006.257.03:06:54.00#ibcon#first serial, iclass 10, count 2 2006.257.03:06:54.00#ibcon#enter sib2, iclass 10, count 2 2006.257.03:06:54.00#ibcon#flushed, iclass 10, count 2 2006.257.03:06:54.00#ibcon#about to write, iclass 10, count 2 2006.257.03:06:54.00#ibcon#wrote, iclass 10, count 2 2006.257.03:06:54.00#ibcon#about to read 3, iclass 10, count 2 2006.257.03:06:54.02#ibcon#read 3, iclass 10, count 2 2006.257.03:06:54.02#ibcon#about to read 4, iclass 10, count 2 2006.257.03:06:54.02#ibcon#read 4, iclass 10, count 2 2006.257.03:06:54.02#ibcon#about to read 5, iclass 10, count 2 2006.257.03:06:54.02#ibcon#read 5, iclass 10, count 2 2006.257.03:06:54.02#ibcon#about to read 6, iclass 10, count 2 2006.257.03:06:54.02#ibcon#read 6, iclass 10, count 2 2006.257.03:06:54.02#ibcon#end of sib2, iclass 10, count 2 2006.257.03:06:54.02#ibcon#*mode == 0, iclass 10, count 2 2006.257.03:06:54.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.03:06:54.02#ibcon#[27=AT05-04\r\n] 2006.257.03:06:54.02#ibcon#*before write, iclass 10, count 2 2006.257.03:06:54.02#ibcon#enter sib2, iclass 10, count 2 2006.257.03:06:54.02#ibcon#flushed, iclass 10, count 2 2006.257.03:06:54.02#ibcon#about to write, iclass 10, count 2 2006.257.03:06:54.02#ibcon#wrote, iclass 10, count 2 2006.257.03:06:54.02#ibcon#about to read 3, iclass 10, count 2 2006.257.03:06:54.05#ibcon#read 3, iclass 10, count 2 2006.257.03:06:54.05#ibcon#about to read 4, iclass 10, count 2 2006.257.03:06:54.05#ibcon#read 4, iclass 10, count 2 2006.257.03:06:54.05#ibcon#about to read 5, iclass 10, count 2 2006.257.03:06:54.05#ibcon#read 5, iclass 10, count 2 2006.257.03:06:54.05#ibcon#about to read 6, iclass 10, count 2 2006.257.03:06:54.05#ibcon#read 6, iclass 10, count 2 2006.257.03:06:54.05#ibcon#end of sib2, iclass 10, count 2 2006.257.03:06:54.05#ibcon#*after write, iclass 10, count 2 2006.257.03:06:54.05#ibcon#*before return 0, iclass 10, count 2 2006.257.03:06:54.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:54.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:06:54.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.03:06:54.05#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:54.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:54.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:54.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:54.17#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:06:54.17#ibcon#first serial, iclass 10, count 0 2006.257.03:06:54.17#ibcon#enter sib2, iclass 10, count 0 2006.257.03:06:54.17#ibcon#flushed, iclass 10, count 0 2006.257.03:06:54.17#ibcon#about to write, iclass 10, count 0 2006.257.03:06:54.17#ibcon#wrote, iclass 10, count 0 2006.257.03:06:54.17#ibcon#about to read 3, iclass 10, count 0 2006.257.03:06:54.19#ibcon#read 3, iclass 10, count 0 2006.257.03:06:54.19#ibcon#about to read 4, iclass 10, count 0 2006.257.03:06:54.19#ibcon#read 4, iclass 10, count 0 2006.257.03:06:54.19#ibcon#about to read 5, iclass 10, count 0 2006.257.03:06:54.19#ibcon#read 5, iclass 10, count 0 2006.257.03:06:54.19#ibcon#about to read 6, iclass 10, count 0 2006.257.03:06:54.19#ibcon#read 6, iclass 10, count 0 2006.257.03:06:54.19#ibcon#end of sib2, iclass 10, count 0 2006.257.03:06:54.19#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:06:54.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:06:54.19#ibcon#[27=USB\r\n] 2006.257.03:06:54.19#ibcon#*before write, iclass 10, count 0 2006.257.03:06:54.19#ibcon#enter sib2, iclass 10, count 0 2006.257.03:06:54.19#ibcon#flushed, iclass 10, count 0 2006.257.03:06:54.19#ibcon#about to write, iclass 10, count 0 2006.257.03:06:54.19#ibcon#wrote, iclass 10, count 0 2006.257.03:06:54.19#ibcon#about to read 3, iclass 10, count 0 2006.257.03:06:54.22#ibcon#read 3, iclass 10, count 0 2006.257.03:06:54.22#ibcon#about to read 4, iclass 10, count 0 2006.257.03:06:54.22#ibcon#read 4, iclass 10, count 0 2006.257.03:06:54.22#ibcon#about to read 5, iclass 10, count 0 2006.257.03:06:54.22#ibcon#read 5, iclass 10, count 0 2006.257.03:06:54.22#ibcon#about to read 6, iclass 10, count 0 2006.257.03:06:54.22#ibcon#read 6, iclass 10, count 0 2006.257.03:06:54.22#ibcon#end of sib2, iclass 10, count 0 2006.257.03:06:54.22#ibcon#*after write, iclass 10, count 0 2006.257.03:06:54.22#ibcon#*before return 0, iclass 10, count 0 2006.257.03:06:54.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:54.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:06:54.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:06:54.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:06:54.22$vck44/vblo=6,719.99 2006.257.03:06:54.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.03:06:54.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.03:06:54.22#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:54.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:54.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:54.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:54.22#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:06:54.22#ibcon#first serial, iclass 12, count 0 2006.257.03:06:54.22#ibcon#enter sib2, iclass 12, count 0 2006.257.03:06:54.22#ibcon#flushed, iclass 12, count 0 2006.257.03:06:54.22#ibcon#about to write, iclass 12, count 0 2006.257.03:06:54.22#ibcon#wrote, iclass 12, count 0 2006.257.03:06:54.22#ibcon#about to read 3, iclass 12, count 0 2006.257.03:06:54.24#ibcon#read 3, iclass 12, count 0 2006.257.03:06:54.24#ibcon#about to read 4, iclass 12, count 0 2006.257.03:06:54.24#ibcon#read 4, iclass 12, count 0 2006.257.03:06:54.24#ibcon#about to read 5, iclass 12, count 0 2006.257.03:06:54.24#ibcon#read 5, iclass 12, count 0 2006.257.03:06:54.24#ibcon#about to read 6, iclass 12, count 0 2006.257.03:06:54.24#ibcon#read 6, iclass 12, count 0 2006.257.03:06:54.24#ibcon#end of sib2, iclass 12, count 0 2006.257.03:06:54.24#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:06:54.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:06:54.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:06:54.24#ibcon#*before write, iclass 12, count 0 2006.257.03:06:54.24#ibcon#enter sib2, iclass 12, count 0 2006.257.03:06:54.24#ibcon#flushed, iclass 12, count 0 2006.257.03:06:54.24#ibcon#about to write, iclass 12, count 0 2006.257.03:06:54.24#ibcon#wrote, iclass 12, count 0 2006.257.03:06:54.24#ibcon#about to read 3, iclass 12, count 0 2006.257.03:06:54.28#ibcon#read 3, iclass 12, count 0 2006.257.03:06:54.28#ibcon#about to read 4, iclass 12, count 0 2006.257.03:06:54.28#ibcon#read 4, iclass 12, count 0 2006.257.03:06:54.28#ibcon#about to read 5, iclass 12, count 0 2006.257.03:06:54.28#ibcon#read 5, iclass 12, count 0 2006.257.03:06:54.28#ibcon#about to read 6, iclass 12, count 0 2006.257.03:06:54.28#ibcon#read 6, iclass 12, count 0 2006.257.03:06:54.28#ibcon#end of sib2, iclass 12, count 0 2006.257.03:06:54.28#ibcon#*after write, iclass 12, count 0 2006.257.03:06:54.28#ibcon#*before return 0, iclass 12, count 0 2006.257.03:06:54.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:54.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:06:54.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:06:54.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:06:54.28$vck44/vb=6,4 2006.257.03:06:54.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.03:06:54.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.03:06:54.28#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:54.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:54.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:54.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:54.34#ibcon#enter wrdev, iclass 14, count 2 2006.257.03:06:54.34#ibcon#first serial, iclass 14, count 2 2006.257.03:06:54.34#ibcon#enter sib2, iclass 14, count 2 2006.257.03:06:54.34#ibcon#flushed, iclass 14, count 2 2006.257.03:06:54.34#ibcon#about to write, iclass 14, count 2 2006.257.03:06:54.34#ibcon#wrote, iclass 14, count 2 2006.257.03:06:54.34#ibcon#about to read 3, iclass 14, count 2 2006.257.03:06:54.36#ibcon#read 3, iclass 14, count 2 2006.257.03:06:54.36#ibcon#about to read 4, iclass 14, count 2 2006.257.03:06:54.36#ibcon#read 4, iclass 14, count 2 2006.257.03:06:54.36#ibcon#about to read 5, iclass 14, count 2 2006.257.03:06:54.36#ibcon#read 5, iclass 14, count 2 2006.257.03:06:54.36#ibcon#about to read 6, iclass 14, count 2 2006.257.03:06:54.36#ibcon#read 6, iclass 14, count 2 2006.257.03:06:54.36#ibcon#end of sib2, iclass 14, count 2 2006.257.03:06:54.36#ibcon#*mode == 0, iclass 14, count 2 2006.257.03:06:54.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.03:06:54.36#ibcon#[27=AT06-04\r\n] 2006.257.03:06:54.36#ibcon#*before write, iclass 14, count 2 2006.257.03:06:54.36#ibcon#enter sib2, iclass 14, count 2 2006.257.03:06:54.36#ibcon#flushed, iclass 14, count 2 2006.257.03:06:54.36#ibcon#about to write, iclass 14, count 2 2006.257.03:06:54.36#ibcon#wrote, iclass 14, count 2 2006.257.03:06:54.36#ibcon#about to read 3, iclass 14, count 2 2006.257.03:06:54.39#ibcon#read 3, iclass 14, count 2 2006.257.03:06:54.39#ibcon#about to read 4, iclass 14, count 2 2006.257.03:06:54.39#ibcon#read 4, iclass 14, count 2 2006.257.03:06:54.39#ibcon#about to read 5, iclass 14, count 2 2006.257.03:06:54.39#ibcon#read 5, iclass 14, count 2 2006.257.03:06:54.39#ibcon#about to read 6, iclass 14, count 2 2006.257.03:06:54.39#ibcon#read 6, iclass 14, count 2 2006.257.03:06:54.39#ibcon#end of sib2, iclass 14, count 2 2006.257.03:06:54.39#ibcon#*after write, iclass 14, count 2 2006.257.03:06:54.39#ibcon#*before return 0, iclass 14, count 2 2006.257.03:06:54.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:54.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:06:54.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.03:06:54.39#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:54.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:54.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:54.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:54.51#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:06:54.51#ibcon#first serial, iclass 14, count 0 2006.257.03:06:54.51#ibcon#enter sib2, iclass 14, count 0 2006.257.03:06:54.51#ibcon#flushed, iclass 14, count 0 2006.257.03:06:54.51#ibcon#about to write, iclass 14, count 0 2006.257.03:06:54.51#ibcon#wrote, iclass 14, count 0 2006.257.03:06:54.51#ibcon#about to read 3, iclass 14, count 0 2006.257.03:06:54.53#ibcon#read 3, iclass 14, count 0 2006.257.03:06:54.53#ibcon#about to read 4, iclass 14, count 0 2006.257.03:06:54.53#ibcon#read 4, iclass 14, count 0 2006.257.03:06:54.53#ibcon#about to read 5, iclass 14, count 0 2006.257.03:06:54.53#ibcon#read 5, iclass 14, count 0 2006.257.03:06:54.53#ibcon#about to read 6, iclass 14, count 0 2006.257.03:06:54.53#ibcon#read 6, iclass 14, count 0 2006.257.03:06:54.53#ibcon#end of sib2, iclass 14, count 0 2006.257.03:06:54.53#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:06:54.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:06:54.53#ibcon#[27=USB\r\n] 2006.257.03:06:54.53#ibcon#*before write, iclass 14, count 0 2006.257.03:06:54.53#ibcon#enter sib2, iclass 14, count 0 2006.257.03:06:54.53#ibcon#flushed, iclass 14, count 0 2006.257.03:06:54.53#ibcon#about to write, iclass 14, count 0 2006.257.03:06:54.53#ibcon#wrote, iclass 14, count 0 2006.257.03:06:54.53#ibcon#about to read 3, iclass 14, count 0 2006.257.03:06:54.56#ibcon#read 3, iclass 14, count 0 2006.257.03:06:54.56#ibcon#about to read 4, iclass 14, count 0 2006.257.03:06:54.56#ibcon#read 4, iclass 14, count 0 2006.257.03:06:54.56#ibcon#about to read 5, iclass 14, count 0 2006.257.03:06:54.56#ibcon#read 5, iclass 14, count 0 2006.257.03:06:54.56#ibcon#about to read 6, iclass 14, count 0 2006.257.03:06:54.56#ibcon#read 6, iclass 14, count 0 2006.257.03:06:54.56#ibcon#end of sib2, iclass 14, count 0 2006.257.03:06:54.56#ibcon#*after write, iclass 14, count 0 2006.257.03:06:54.56#ibcon#*before return 0, iclass 14, count 0 2006.257.03:06:54.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:54.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:06:54.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:06:54.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:06:54.56$vck44/vblo=7,734.99 2006.257.03:06:54.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.03:06:54.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.03:06:54.56#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:54.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:54.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:54.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:54.56#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:06:54.56#ibcon#first serial, iclass 16, count 0 2006.257.03:06:54.56#ibcon#enter sib2, iclass 16, count 0 2006.257.03:06:54.56#ibcon#flushed, iclass 16, count 0 2006.257.03:06:54.56#ibcon#about to write, iclass 16, count 0 2006.257.03:06:54.56#ibcon#wrote, iclass 16, count 0 2006.257.03:06:54.56#ibcon#about to read 3, iclass 16, count 0 2006.257.03:06:54.58#ibcon#read 3, iclass 16, count 0 2006.257.03:06:54.58#ibcon#about to read 4, iclass 16, count 0 2006.257.03:06:54.58#ibcon#read 4, iclass 16, count 0 2006.257.03:06:54.58#ibcon#about to read 5, iclass 16, count 0 2006.257.03:06:54.58#ibcon#read 5, iclass 16, count 0 2006.257.03:06:54.58#ibcon#about to read 6, iclass 16, count 0 2006.257.03:06:54.58#ibcon#read 6, iclass 16, count 0 2006.257.03:06:54.58#ibcon#end of sib2, iclass 16, count 0 2006.257.03:06:54.58#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:06:54.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:06:54.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:06:54.58#ibcon#*before write, iclass 16, count 0 2006.257.03:06:54.58#ibcon#enter sib2, iclass 16, count 0 2006.257.03:06:54.58#ibcon#flushed, iclass 16, count 0 2006.257.03:06:54.58#ibcon#about to write, iclass 16, count 0 2006.257.03:06:54.58#ibcon#wrote, iclass 16, count 0 2006.257.03:06:54.58#ibcon#about to read 3, iclass 16, count 0 2006.257.03:06:54.62#ibcon#read 3, iclass 16, count 0 2006.257.03:06:54.62#ibcon#about to read 4, iclass 16, count 0 2006.257.03:06:54.62#ibcon#read 4, iclass 16, count 0 2006.257.03:06:54.62#ibcon#about to read 5, iclass 16, count 0 2006.257.03:06:54.62#ibcon#read 5, iclass 16, count 0 2006.257.03:06:54.62#ibcon#about to read 6, iclass 16, count 0 2006.257.03:06:54.62#ibcon#read 6, iclass 16, count 0 2006.257.03:06:54.62#ibcon#end of sib2, iclass 16, count 0 2006.257.03:06:54.62#ibcon#*after write, iclass 16, count 0 2006.257.03:06:54.62#ibcon#*before return 0, iclass 16, count 0 2006.257.03:06:54.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:54.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:06:54.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:06:54.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:06:54.62$vck44/vb=7,4 2006.257.03:06:54.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.03:06:54.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.03:06:54.62#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:54.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:54.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:54.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:54.68#ibcon#enter wrdev, iclass 18, count 2 2006.257.03:06:54.68#ibcon#first serial, iclass 18, count 2 2006.257.03:06:54.68#ibcon#enter sib2, iclass 18, count 2 2006.257.03:06:54.68#ibcon#flushed, iclass 18, count 2 2006.257.03:06:54.68#ibcon#about to write, iclass 18, count 2 2006.257.03:06:54.68#ibcon#wrote, iclass 18, count 2 2006.257.03:06:54.68#ibcon#about to read 3, iclass 18, count 2 2006.257.03:06:54.70#ibcon#read 3, iclass 18, count 2 2006.257.03:06:54.70#ibcon#about to read 4, iclass 18, count 2 2006.257.03:06:54.70#ibcon#read 4, iclass 18, count 2 2006.257.03:06:54.70#ibcon#about to read 5, iclass 18, count 2 2006.257.03:06:54.70#ibcon#read 5, iclass 18, count 2 2006.257.03:06:54.70#ibcon#about to read 6, iclass 18, count 2 2006.257.03:06:54.70#ibcon#read 6, iclass 18, count 2 2006.257.03:06:54.70#ibcon#end of sib2, iclass 18, count 2 2006.257.03:06:54.70#ibcon#*mode == 0, iclass 18, count 2 2006.257.03:06:54.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.03:06:54.70#ibcon#[27=AT07-04\r\n] 2006.257.03:06:54.70#ibcon#*before write, iclass 18, count 2 2006.257.03:06:54.70#ibcon#enter sib2, iclass 18, count 2 2006.257.03:06:54.70#ibcon#flushed, iclass 18, count 2 2006.257.03:06:54.70#ibcon#about to write, iclass 18, count 2 2006.257.03:06:54.70#ibcon#wrote, iclass 18, count 2 2006.257.03:06:54.70#ibcon#about to read 3, iclass 18, count 2 2006.257.03:06:54.73#ibcon#read 3, iclass 18, count 2 2006.257.03:06:54.73#ibcon#about to read 4, iclass 18, count 2 2006.257.03:06:54.73#ibcon#read 4, iclass 18, count 2 2006.257.03:06:54.73#ibcon#about to read 5, iclass 18, count 2 2006.257.03:06:54.73#ibcon#read 5, iclass 18, count 2 2006.257.03:06:54.73#ibcon#about to read 6, iclass 18, count 2 2006.257.03:06:54.73#ibcon#read 6, iclass 18, count 2 2006.257.03:06:54.73#ibcon#end of sib2, iclass 18, count 2 2006.257.03:06:54.73#ibcon#*after write, iclass 18, count 2 2006.257.03:06:54.73#ibcon#*before return 0, iclass 18, count 2 2006.257.03:06:54.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:54.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:06:54.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.03:06:54.73#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:54.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:54.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:54.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:54.85#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:06:54.85#ibcon#first serial, iclass 18, count 0 2006.257.03:06:54.85#ibcon#enter sib2, iclass 18, count 0 2006.257.03:06:54.85#ibcon#flushed, iclass 18, count 0 2006.257.03:06:54.85#ibcon#about to write, iclass 18, count 0 2006.257.03:06:54.85#ibcon#wrote, iclass 18, count 0 2006.257.03:06:54.85#ibcon#about to read 3, iclass 18, count 0 2006.257.03:06:54.87#ibcon#read 3, iclass 18, count 0 2006.257.03:06:54.87#ibcon#about to read 4, iclass 18, count 0 2006.257.03:06:54.87#ibcon#read 4, iclass 18, count 0 2006.257.03:06:54.87#ibcon#about to read 5, iclass 18, count 0 2006.257.03:06:54.87#ibcon#read 5, iclass 18, count 0 2006.257.03:06:54.87#ibcon#about to read 6, iclass 18, count 0 2006.257.03:06:54.87#ibcon#read 6, iclass 18, count 0 2006.257.03:06:54.87#ibcon#end of sib2, iclass 18, count 0 2006.257.03:06:54.87#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:06:54.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:06:54.87#ibcon#[27=USB\r\n] 2006.257.03:06:54.87#ibcon#*before write, iclass 18, count 0 2006.257.03:06:54.87#ibcon#enter sib2, iclass 18, count 0 2006.257.03:06:54.87#ibcon#flushed, iclass 18, count 0 2006.257.03:06:54.87#ibcon#about to write, iclass 18, count 0 2006.257.03:06:54.87#ibcon#wrote, iclass 18, count 0 2006.257.03:06:54.87#ibcon#about to read 3, iclass 18, count 0 2006.257.03:06:54.90#ibcon#read 3, iclass 18, count 0 2006.257.03:06:54.90#ibcon#about to read 4, iclass 18, count 0 2006.257.03:06:54.90#ibcon#read 4, iclass 18, count 0 2006.257.03:06:54.90#ibcon#about to read 5, iclass 18, count 0 2006.257.03:06:54.90#ibcon#read 5, iclass 18, count 0 2006.257.03:06:54.90#ibcon#about to read 6, iclass 18, count 0 2006.257.03:06:54.90#ibcon#read 6, iclass 18, count 0 2006.257.03:06:54.90#ibcon#end of sib2, iclass 18, count 0 2006.257.03:06:54.90#ibcon#*after write, iclass 18, count 0 2006.257.03:06:54.90#ibcon#*before return 0, iclass 18, count 0 2006.257.03:06:54.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:54.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:06:54.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:06:54.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:06:54.90$vck44/vblo=8,744.99 2006.257.03:06:54.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.03:06:54.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.03:06:54.90#ibcon#ireg 17 cls_cnt 0 2006.257.03:06:54.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:54.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:54.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:54.90#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:06:54.90#ibcon#first serial, iclass 20, count 0 2006.257.03:06:54.90#ibcon#enter sib2, iclass 20, count 0 2006.257.03:06:54.90#ibcon#flushed, iclass 20, count 0 2006.257.03:06:54.90#ibcon#about to write, iclass 20, count 0 2006.257.03:06:54.90#ibcon#wrote, iclass 20, count 0 2006.257.03:06:54.90#ibcon#about to read 3, iclass 20, count 0 2006.257.03:06:54.92#ibcon#read 3, iclass 20, count 0 2006.257.03:06:54.92#ibcon#about to read 4, iclass 20, count 0 2006.257.03:06:54.92#ibcon#read 4, iclass 20, count 0 2006.257.03:06:54.92#ibcon#about to read 5, iclass 20, count 0 2006.257.03:06:54.92#ibcon#read 5, iclass 20, count 0 2006.257.03:06:54.92#ibcon#about to read 6, iclass 20, count 0 2006.257.03:06:54.92#ibcon#read 6, iclass 20, count 0 2006.257.03:06:54.92#ibcon#end of sib2, iclass 20, count 0 2006.257.03:06:54.92#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:06:54.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:06:54.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:06:54.92#ibcon#*before write, iclass 20, count 0 2006.257.03:06:54.92#ibcon#enter sib2, iclass 20, count 0 2006.257.03:06:54.92#ibcon#flushed, iclass 20, count 0 2006.257.03:06:54.92#ibcon#about to write, iclass 20, count 0 2006.257.03:06:54.92#ibcon#wrote, iclass 20, count 0 2006.257.03:06:54.92#ibcon#about to read 3, iclass 20, count 0 2006.257.03:06:54.96#ibcon#read 3, iclass 20, count 0 2006.257.03:06:54.96#ibcon#about to read 4, iclass 20, count 0 2006.257.03:06:54.96#ibcon#read 4, iclass 20, count 0 2006.257.03:06:54.96#ibcon#about to read 5, iclass 20, count 0 2006.257.03:06:54.96#ibcon#read 5, iclass 20, count 0 2006.257.03:06:54.96#ibcon#about to read 6, iclass 20, count 0 2006.257.03:06:54.96#ibcon#read 6, iclass 20, count 0 2006.257.03:06:54.96#ibcon#end of sib2, iclass 20, count 0 2006.257.03:06:54.96#ibcon#*after write, iclass 20, count 0 2006.257.03:06:54.96#ibcon#*before return 0, iclass 20, count 0 2006.257.03:06:54.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:54.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:06:54.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:06:54.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:06:54.96$vck44/vb=8,4 2006.257.03:06:54.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.03:06:54.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.03:06:54.96#ibcon#ireg 11 cls_cnt 2 2006.257.03:06:54.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:55.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:55.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:55.02#ibcon#enter wrdev, iclass 22, count 2 2006.257.03:06:55.02#ibcon#first serial, iclass 22, count 2 2006.257.03:06:55.02#ibcon#enter sib2, iclass 22, count 2 2006.257.03:06:55.02#ibcon#flushed, iclass 22, count 2 2006.257.03:06:55.02#ibcon#about to write, iclass 22, count 2 2006.257.03:06:55.02#ibcon#wrote, iclass 22, count 2 2006.257.03:06:55.02#ibcon#about to read 3, iclass 22, count 2 2006.257.03:06:55.04#ibcon#read 3, iclass 22, count 2 2006.257.03:06:55.04#ibcon#about to read 4, iclass 22, count 2 2006.257.03:06:55.04#ibcon#read 4, iclass 22, count 2 2006.257.03:06:55.04#ibcon#about to read 5, iclass 22, count 2 2006.257.03:06:55.04#ibcon#read 5, iclass 22, count 2 2006.257.03:06:55.04#ibcon#about to read 6, iclass 22, count 2 2006.257.03:06:55.04#ibcon#read 6, iclass 22, count 2 2006.257.03:06:55.04#ibcon#end of sib2, iclass 22, count 2 2006.257.03:06:55.04#ibcon#*mode == 0, iclass 22, count 2 2006.257.03:06:55.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.03:06:55.04#ibcon#[27=AT08-04\r\n] 2006.257.03:06:55.04#ibcon#*before write, iclass 22, count 2 2006.257.03:06:55.04#ibcon#enter sib2, iclass 22, count 2 2006.257.03:06:55.04#ibcon#flushed, iclass 22, count 2 2006.257.03:06:55.04#ibcon#about to write, iclass 22, count 2 2006.257.03:06:55.04#ibcon#wrote, iclass 22, count 2 2006.257.03:06:55.04#ibcon#about to read 3, iclass 22, count 2 2006.257.03:06:55.07#ibcon#read 3, iclass 22, count 2 2006.257.03:06:55.07#ibcon#about to read 4, iclass 22, count 2 2006.257.03:06:55.07#ibcon#read 4, iclass 22, count 2 2006.257.03:06:55.07#ibcon#about to read 5, iclass 22, count 2 2006.257.03:06:55.07#ibcon#read 5, iclass 22, count 2 2006.257.03:06:55.07#ibcon#about to read 6, iclass 22, count 2 2006.257.03:06:55.07#ibcon#read 6, iclass 22, count 2 2006.257.03:06:55.07#ibcon#end of sib2, iclass 22, count 2 2006.257.03:06:55.07#ibcon#*after write, iclass 22, count 2 2006.257.03:06:55.07#ibcon#*before return 0, iclass 22, count 2 2006.257.03:06:55.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:55.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:06:55.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.03:06:55.07#ibcon#ireg 7 cls_cnt 0 2006.257.03:06:55.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:55.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:55.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:55.19#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:06:55.19#ibcon#first serial, iclass 22, count 0 2006.257.03:06:55.19#ibcon#enter sib2, iclass 22, count 0 2006.257.03:06:55.19#ibcon#flushed, iclass 22, count 0 2006.257.03:06:55.19#ibcon#about to write, iclass 22, count 0 2006.257.03:06:55.19#ibcon#wrote, iclass 22, count 0 2006.257.03:06:55.19#ibcon#about to read 3, iclass 22, count 0 2006.257.03:06:55.21#ibcon#read 3, iclass 22, count 0 2006.257.03:06:55.21#ibcon#about to read 4, iclass 22, count 0 2006.257.03:06:55.21#ibcon#read 4, iclass 22, count 0 2006.257.03:06:55.21#ibcon#about to read 5, iclass 22, count 0 2006.257.03:06:55.21#ibcon#read 5, iclass 22, count 0 2006.257.03:06:55.21#ibcon#about to read 6, iclass 22, count 0 2006.257.03:06:55.21#ibcon#read 6, iclass 22, count 0 2006.257.03:06:55.21#ibcon#end of sib2, iclass 22, count 0 2006.257.03:06:55.21#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:06:55.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:06:55.21#ibcon#[27=USB\r\n] 2006.257.03:06:55.21#ibcon#*before write, iclass 22, count 0 2006.257.03:06:55.21#ibcon#enter sib2, iclass 22, count 0 2006.257.03:06:55.21#ibcon#flushed, iclass 22, count 0 2006.257.03:06:55.21#ibcon#about to write, iclass 22, count 0 2006.257.03:06:55.21#ibcon#wrote, iclass 22, count 0 2006.257.03:06:55.21#ibcon#about to read 3, iclass 22, count 0 2006.257.03:06:55.24#ibcon#read 3, iclass 22, count 0 2006.257.03:06:55.24#ibcon#about to read 4, iclass 22, count 0 2006.257.03:06:55.24#ibcon#read 4, iclass 22, count 0 2006.257.03:06:55.24#ibcon#about to read 5, iclass 22, count 0 2006.257.03:06:55.24#ibcon#read 5, iclass 22, count 0 2006.257.03:06:55.24#ibcon#about to read 6, iclass 22, count 0 2006.257.03:06:55.24#ibcon#read 6, iclass 22, count 0 2006.257.03:06:55.24#ibcon#end of sib2, iclass 22, count 0 2006.257.03:06:55.24#ibcon#*after write, iclass 22, count 0 2006.257.03:06:55.24#ibcon#*before return 0, iclass 22, count 0 2006.257.03:06:55.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:55.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:06:55.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:06:55.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:06:55.24$vck44/vabw=wide 2006.257.03:06:55.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.03:06:55.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.03:06:55.24#ibcon#ireg 8 cls_cnt 0 2006.257.03:06:55.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:55.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:55.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:55.24#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:06:55.24#ibcon#first serial, iclass 24, count 0 2006.257.03:06:55.24#ibcon#enter sib2, iclass 24, count 0 2006.257.03:06:55.24#ibcon#flushed, iclass 24, count 0 2006.257.03:06:55.24#ibcon#about to write, iclass 24, count 0 2006.257.03:06:55.24#ibcon#wrote, iclass 24, count 0 2006.257.03:06:55.24#ibcon#about to read 3, iclass 24, count 0 2006.257.03:06:55.26#ibcon#read 3, iclass 24, count 0 2006.257.03:06:55.26#ibcon#about to read 4, iclass 24, count 0 2006.257.03:06:55.26#ibcon#read 4, iclass 24, count 0 2006.257.03:06:55.26#ibcon#about to read 5, iclass 24, count 0 2006.257.03:06:55.26#ibcon#read 5, iclass 24, count 0 2006.257.03:06:55.26#ibcon#about to read 6, iclass 24, count 0 2006.257.03:06:55.26#ibcon#read 6, iclass 24, count 0 2006.257.03:06:55.26#ibcon#end of sib2, iclass 24, count 0 2006.257.03:06:55.26#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:06:55.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:06:55.26#ibcon#[25=BW32\r\n] 2006.257.03:06:55.26#ibcon#*before write, iclass 24, count 0 2006.257.03:06:55.26#ibcon#enter sib2, iclass 24, count 0 2006.257.03:06:55.26#ibcon#flushed, iclass 24, count 0 2006.257.03:06:55.26#ibcon#about to write, iclass 24, count 0 2006.257.03:06:55.26#ibcon#wrote, iclass 24, count 0 2006.257.03:06:55.26#ibcon#about to read 3, iclass 24, count 0 2006.257.03:06:55.29#ibcon#read 3, iclass 24, count 0 2006.257.03:06:55.29#ibcon#about to read 4, iclass 24, count 0 2006.257.03:06:55.29#ibcon#read 4, iclass 24, count 0 2006.257.03:06:55.29#ibcon#about to read 5, iclass 24, count 0 2006.257.03:06:55.29#ibcon#read 5, iclass 24, count 0 2006.257.03:06:55.29#ibcon#about to read 6, iclass 24, count 0 2006.257.03:06:55.29#ibcon#read 6, iclass 24, count 0 2006.257.03:06:55.29#ibcon#end of sib2, iclass 24, count 0 2006.257.03:06:55.29#ibcon#*after write, iclass 24, count 0 2006.257.03:06:55.29#ibcon#*before return 0, iclass 24, count 0 2006.257.03:06:55.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:55.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:06:55.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:06:55.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:06:55.29$vck44/vbbw=wide 2006.257.03:06:55.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.03:06:55.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.03:06:55.29#ibcon#ireg 8 cls_cnt 0 2006.257.03:06:55.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:06:55.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:06:55.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:06:55.36#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:06:55.36#ibcon#first serial, iclass 26, count 0 2006.257.03:06:55.36#ibcon#enter sib2, iclass 26, count 0 2006.257.03:06:55.36#ibcon#flushed, iclass 26, count 0 2006.257.03:06:55.36#ibcon#about to write, iclass 26, count 0 2006.257.03:06:55.36#ibcon#wrote, iclass 26, count 0 2006.257.03:06:55.36#ibcon#about to read 3, iclass 26, count 0 2006.257.03:06:55.38#ibcon#read 3, iclass 26, count 0 2006.257.03:06:55.38#ibcon#about to read 4, iclass 26, count 0 2006.257.03:06:55.38#ibcon#read 4, iclass 26, count 0 2006.257.03:06:55.38#ibcon#about to read 5, iclass 26, count 0 2006.257.03:06:55.38#ibcon#read 5, iclass 26, count 0 2006.257.03:06:55.38#ibcon#about to read 6, iclass 26, count 0 2006.257.03:06:55.38#ibcon#read 6, iclass 26, count 0 2006.257.03:06:55.38#ibcon#end of sib2, iclass 26, count 0 2006.257.03:06:55.38#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:06:55.38#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:06:55.38#ibcon#[27=BW32\r\n] 2006.257.03:06:55.38#ibcon#*before write, iclass 26, count 0 2006.257.03:06:55.38#ibcon#enter sib2, iclass 26, count 0 2006.257.03:06:55.38#ibcon#flushed, iclass 26, count 0 2006.257.03:06:55.38#ibcon#about to write, iclass 26, count 0 2006.257.03:06:55.38#ibcon#wrote, iclass 26, count 0 2006.257.03:06:55.38#ibcon#about to read 3, iclass 26, count 0 2006.257.03:06:55.41#ibcon#read 3, iclass 26, count 0 2006.257.03:06:55.41#ibcon#about to read 4, iclass 26, count 0 2006.257.03:06:55.41#ibcon#read 4, iclass 26, count 0 2006.257.03:06:55.41#ibcon#about to read 5, iclass 26, count 0 2006.257.03:06:55.41#ibcon#read 5, iclass 26, count 0 2006.257.03:06:55.41#ibcon#about to read 6, iclass 26, count 0 2006.257.03:06:55.41#ibcon#read 6, iclass 26, count 0 2006.257.03:06:55.41#ibcon#end of sib2, iclass 26, count 0 2006.257.03:06:55.41#ibcon#*after write, iclass 26, count 0 2006.257.03:06:55.41#ibcon#*before return 0, iclass 26, count 0 2006.257.03:06:55.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:06:55.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:06:55.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:06:55.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:06:55.41$setupk4/ifdk4 2006.257.03:06:55.41$ifdk4/lo= 2006.257.03:06:55.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:06:55.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:06:55.41$ifdk4/patch= 2006.257.03:06:55.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:06:55.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:06:55.42$setupk4/!*+20s 2006.257.03:06:59.45#abcon#<5=/14 1.9 5.9 19.15 921012.3\r\n> 2006.257.03:06:59.47#abcon#{5=INTERFACE CLEAR} 2006.257.03:06:59.54#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:07:08.14#trakl#Source acquired 2006.257.03:07:09.63#abcon#<5=/14 1.9 5.9 19.15 921012.3\r\n> 2006.257.03:07:09.65#abcon#{5=INTERFACE CLEAR} 2006.257.03:07:09.71#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:07:09.92$setupk4/"tpicd 2006.257.03:07:09.92$setupk4/echo=off 2006.257.03:07:09.92$setupk4/xlog=off 2006.257.03:07:09.92:!2006.257.03:10:47 2006.257.03:07:10.14#flagr#flagr/antenna,acquired 2006.257.03:10:47.00:preob 2006.257.03:10:47.13/onsource/TRACKING 2006.257.03:10:47.13:!2006.257.03:10:57 2006.257.03:10:57.00:"tape 2006.257.03:10:57.00:"st=record 2006.257.03:10:57.00:data_valid=on 2006.257.03:10:57.00:midob 2006.257.03:10:58.13/onsource/TRACKING 2006.257.03:10:58.13/wx/19.07,1012.2,93 2006.257.03:10:58.32/cable/+6.4871E-03 2006.257.03:10:59.41/va/01,08,usb,yes,36,39 2006.257.03:10:59.41/va/02,07,usb,yes,40,40 2006.257.03:10:59.41/va/03,08,usb,yes,36,38 2006.257.03:10:59.41/va/04,07,usb,yes,41,43 2006.257.03:10:59.41/va/05,04,usb,yes,37,37 2006.257.03:10:59.41/va/06,04,usb,yes,41,40 2006.257.03:10:59.41/va/07,04,usb,yes,42,42 2006.257.03:10:59.41/va/08,04,usb,yes,35,43 2006.257.03:10:59.64/valo/01,524.99,yes,locked 2006.257.03:10:59.64/valo/02,534.99,yes,locked 2006.257.03:10:59.64/valo/03,564.99,yes,locked 2006.257.03:10:59.64/valo/04,624.99,yes,locked 2006.257.03:10:59.64/valo/05,734.99,yes,locked 2006.257.03:10:59.64/valo/06,814.99,yes,locked 2006.257.03:10:59.64/valo/07,864.99,yes,locked 2006.257.03:10:59.64/valo/08,884.99,yes,locked 2006.257.03:11:00.73/vb/01,04,usb,yes,33,31 2006.257.03:11:00.73/vb/02,05,usb,yes,32,31 2006.257.03:11:00.73/vb/03,04,usb,yes,33,36 2006.257.03:11:00.73/vb/04,05,usb,yes,33,32 2006.257.03:11:00.73/vb/05,04,usb,yes,29,32 2006.257.03:11:00.73/vb/06,04,usb,yes,34,30 2006.257.03:11:00.73/vb/07,04,usb,yes,34,34 2006.257.03:11:00.73/vb/08,04,usb,yes,31,35 2006.257.03:11:00.96/vblo/01,629.99,yes,locked 2006.257.03:11:00.96/vblo/02,634.99,yes,locked 2006.257.03:11:00.96/vblo/03,649.99,yes,locked 2006.257.03:11:00.96/vblo/04,679.99,yes,locked 2006.257.03:11:00.96/vblo/05,709.99,yes,locked 2006.257.03:11:00.96/vblo/06,719.99,yes,locked 2006.257.03:11:00.96/vblo/07,734.99,yes,locked 2006.257.03:11:00.96/vblo/08,744.99,yes,locked 2006.257.03:11:01.11/vabw/8 2006.257.03:11:01.26/vbbw/8 2006.257.03:11:01.35/xfe/off,on,16.0 2006.257.03:11:01.73/ifatt/23,28,28,28 2006.257.03:11:02.07/fmout-gps/S +4.54E-07 2006.257.03:11:02.11:!2006.257.03:11:37 2006.257.03:11:37.00:data_valid=off 2006.257.03:11:37.01:"et 2006.257.03:11:37.01:!+3s 2006.257.03:11:40.03:"tape 2006.257.03:11:40.04:postob 2006.257.03:11:40.11/cable/+6.4852E-03 2006.257.03:11:40.12/wx/19.05,1012.2,94 2006.257.03:11:40.18/fmout-gps/S +4.54E-07 2006.257.03:11:40.18:scan_name=257-0315,jd0609,80 2006.257.03:11:40.19:source=3c274,123049.42,122328.0,2000.0,ccw 2006.257.03:11:42.14#flagr#flagr/antenna,new-source 2006.257.03:11:42.15:checkk5 2006.257.03:11:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:11:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:11:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:11:43.63/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:11:43.99/chk_obsdata//k5ts1/T2570310??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:11:44.35/chk_obsdata//k5ts2/T2570310??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:11:44.72/chk_obsdata//k5ts3/T2570310??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:11:45.09/chk_obsdata//k5ts4/T2570310??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:11:45.76/k5log//k5ts1_log_newline 2006.257.03:11:46.45/k5log//k5ts2_log_newline 2006.257.03:11:47.16/k5log//k5ts3_log_newline 2006.257.03:11:47.84/k5log//k5ts4_log_newline 2006.257.03:11:47.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:11:47.87:setupk4=1 2006.257.03:11:47.87$setupk4/echo=on 2006.257.03:11:47.87$setupk4/pcalon 2006.257.03:11:47.87$pcalon/"no phase cal control is implemented here 2006.257.03:11:47.87$setupk4/"tpicd=stop 2006.257.03:11:47.87$setupk4/"rec=synch_on 2006.257.03:11:47.87$setupk4/"rec_mode=128 2006.257.03:11:47.87$setupk4/!* 2006.257.03:11:47.87$setupk4/recpk4 2006.257.03:11:47.87$recpk4/recpatch= 2006.257.03:11:47.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:11:47.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:11:47.87$setupk4/vck44 2006.257.03:11:47.87$vck44/valo=1,524.99 2006.257.03:11:47.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.03:11:47.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.03:11:47.88#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:47.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:47.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:47.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:47.88#ibcon#enter wrdev, iclass 39, count 0 2006.257.03:11:47.88#ibcon#first serial, iclass 39, count 0 2006.257.03:11:47.88#ibcon#enter sib2, iclass 39, count 0 2006.257.03:11:47.88#ibcon#flushed, iclass 39, count 0 2006.257.03:11:47.88#ibcon#about to write, iclass 39, count 0 2006.257.03:11:47.88#ibcon#wrote, iclass 39, count 0 2006.257.03:11:47.88#ibcon#about to read 3, iclass 39, count 0 2006.257.03:11:47.91#ibcon#read 3, iclass 39, count 0 2006.257.03:11:47.91#ibcon#about to read 4, iclass 39, count 0 2006.257.03:11:47.91#ibcon#read 4, iclass 39, count 0 2006.257.03:11:47.91#ibcon#about to read 5, iclass 39, count 0 2006.257.03:11:47.91#ibcon#read 5, iclass 39, count 0 2006.257.03:11:47.91#ibcon#about to read 6, iclass 39, count 0 2006.257.03:11:47.91#ibcon#read 6, iclass 39, count 0 2006.257.03:11:47.91#ibcon#end of sib2, iclass 39, count 0 2006.257.03:11:47.91#ibcon#*mode == 0, iclass 39, count 0 2006.257.03:11:47.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.03:11:47.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:11:47.91#ibcon#*before write, iclass 39, count 0 2006.257.03:11:47.91#ibcon#enter sib2, iclass 39, count 0 2006.257.03:11:47.91#ibcon#flushed, iclass 39, count 0 2006.257.03:11:47.91#ibcon#about to write, iclass 39, count 0 2006.257.03:11:47.91#ibcon#wrote, iclass 39, count 0 2006.257.03:11:47.91#ibcon#about to read 3, iclass 39, count 0 2006.257.03:11:47.95#ibcon#read 3, iclass 39, count 0 2006.257.03:11:47.95#ibcon#about to read 4, iclass 39, count 0 2006.257.03:11:47.95#ibcon#read 4, iclass 39, count 0 2006.257.03:11:47.95#ibcon#about to read 5, iclass 39, count 0 2006.257.03:11:47.95#ibcon#read 5, iclass 39, count 0 2006.257.03:11:47.95#ibcon#about to read 6, iclass 39, count 0 2006.257.03:11:47.95#ibcon#read 6, iclass 39, count 0 2006.257.03:11:47.95#ibcon#end of sib2, iclass 39, count 0 2006.257.03:11:47.95#ibcon#*after write, iclass 39, count 0 2006.257.03:11:47.95#ibcon#*before return 0, iclass 39, count 0 2006.257.03:11:47.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:47.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:47.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.03:11:47.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.03:11:47.95$vck44/va=1,8 2006.257.03:11:47.95#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.03:11:47.95#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.03:11:47.95#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:47.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:47.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:47.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:47.95#ibcon#enter wrdev, iclass 3, count 2 2006.257.03:11:47.95#ibcon#first serial, iclass 3, count 2 2006.257.03:11:47.95#ibcon#enter sib2, iclass 3, count 2 2006.257.03:11:47.95#ibcon#flushed, iclass 3, count 2 2006.257.03:11:47.95#ibcon#about to write, iclass 3, count 2 2006.257.03:11:47.95#ibcon#wrote, iclass 3, count 2 2006.257.03:11:47.95#ibcon#about to read 3, iclass 3, count 2 2006.257.03:11:47.97#ibcon#read 3, iclass 3, count 2 2006.257.03:11:47.97#ibcon#about to read 4, iclass 3, count 2 2006.257.03:11:47.97#ibcon#read 4, iclass 3, count 2 2006.257.03:11:47.97#ibcon#about to read 5, iclass 3, count 2 2006.257.03:11:47.97#ibcon#read 5, iclass 3, count 2 2006.257.03:11:47.97#ibcon#about to read 6, iclass 3, count 2 2006.257.03:11:47.97#ibcon#read 6, iclass 3, count 2 2006.257.03:11:47.97#ibcon#end of sib2, iclass 3, count 2 2006.257.03:11:47.97#ibcon#*mode == 0, iclass 3, count 2 2006.257.03:11:47.97#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.03:11:47.97#ibcon#[25=AT01-08\r\n] 2006.257.03:11:47.97#ibcon#*before write, iclass 3, count 2 2006.257.03:11:47.97#ibcon#enter sib2, iclass 3, count 2 2006.257.03:11:47.97#ibcon#flushed, iclass 3, count 2 2006.257.03:11:47.97#ibcon#about to write, iclass 3, count 2 2006.257.03:11:47.97#ibcon#wrote, iclass 3, count 2 2006.257.03:11:47.97#ibcon#about to read 3, iclass 3, count 2 2006.257.03:11:48.00#ibcon#read 3, iclass 3, count 2 2006.257.03:11:48.00#ibcon#about to read 4, iclass 3, count 2 2006.257.03:11:48.00#ibcon#read 4, iclass 3, count 2 2006.257.03:11:48.00#ibcon#about to read 5, iclass 3, count 2 2006.257.03:11:48.00#ibcon#read 5, iclass 3, count 2 2006.257.03:11:48.00#ibcon#about to read 6, iclass 3, count 2 2006.257.03:11:48.00#ibcon#read 6, iclass 3, count 2 2006.257.03:11:48.00#ibcon#end of sib2, iclass 3, count 2 2006.257.03:11:48.00#ibcon#*after write, iclass 3, count 2 2006.257.03:11:48.00#ibcon#*before return 0, iclass 3, count 2 2006.257.03:11:48.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:48.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:48.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.03:11:48.00#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:48.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:48.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:48.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:48.12#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:11:48.12#ibcon#first serial, iclass 3, count 0 2006.257.03:11:48.12#ibcon#enter sib2, iclass 3, count 0 2006.257.03:11:48.12#ibcon#flushed, iclass 3, count 0 2006.257.03:11:48.12#ibcon#about to write, iclass 3, count 0 2006.257.03:11:48.12#ibcon#wrote, iclass 3, count 0 2006.257.03:11:48.12#ibcon#about to read 3, iclass 3, count 0 2006.257.03:11:48.14#ibcon#read 3, iclass 3, count 0 2006.257.03:11:48.14#ibcon#about to read 4, iclass 3, count 0 2006.257.03:11:48.14#ibcon#read 4, iclass 3, count 0 2006.257.03:11:48.14#ibcon#about to read 5, iclass 3, count 0 2006.257.03:11:48.14#ibcon#read 5, iclass 3, count 0 2006.257.03:11:48.14#ibcon#about to read 6, iclass 3, count 0 2006.257.03:11:48.14#ibcon#read 6, iclass 3, count 0 2006.257.03:11:48.14#ibcon#end of sib2, iclass 3, count 0 2006.257.03:11:48.14#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:11:48.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:11:48.14#ibcon#[25=USB\r\n] 2006.257.03:11:48.14#ibcon#*before write, iclass 3, count 0 2006.257.03:11:48.14#ibcon#enter sib2, iclass 3, count 0 2006.257.03:11:48.14#ibcon#flushed, iclass 3, count 0 2006.257.03:11:48.14#ibcon#about to write, iclass 3, count 0 2006.257.03:11:48.14#ibcon#wrote, iclass 3, count 0 2006.257.03:11:48.14#ibcon#about to read 3, iclass 3, count 0 2006.257.03:11:48.17#ibcon#read 3, iclass 3, count 0 2006.257.03:11:48.17#ibcon#about to read 4, iclass 3, count 0 2006.257.03:11:48.17#ibcon#read 4, iclass 3, count 0 2006.257.03:11:48.17#ibcon#about to read 5, iclass 3, count 0 2006.257.03:11:48.17#ibcon#read 5, iclass 3, count 0 2006.257.03:11:48.17#ibcon#about to read 6, iclass 3, count 0 2006.257.03:11:48.17#ibcon#read 6, iclass 3, count 0 2006.257.03:11:48.17#ibcon#end of sib2, iclass 3, count 0 2006.257.03:11:48.17#ibcon#*after write, iclass 3, count 0 2006.257.03:11:48.17#ibcon#*before return 0, iclass 3, count 0 2006.257.03:11:48.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:48.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:48.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:11:48.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:11:48.17$vck44/valo=2,534.99 2006.257.03:11:48.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.03:11:48.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.03:11:48.17#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:48.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:48.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:48.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:48.17#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:11:48.17#ibcon#first serial, iclass 5, count 0 2006.257.03:11:48.17#ibcon#enter sib2, iclass 5, count 0 2006.257.03:11:48.17#ibcon#flushed, iclass 5, count 0 2006.257.03:11:48.17#ibcon#about to write, iclass 5, count 0 2006.257.03:11:48.17#ibcon#wrote, iclass 5, count 0 2006.257.03:11:48.17#ibcon#about to read 3, iclass 5, count 0 2006.257.03:11:48.19#ibcon#read 3, iclass 5, count 0 2006.257.03:11:48.19#ibcon#about to read 4, iclass 5, count 0 2006.257.03:11:48.19#ibcon#read 4, iclass 5, count 0 2006.257.03:11:48.19#ibcon#about to read 5, iclass 5, count 0 2006.257.03:11:48.19#ibcon#read 5, iclass 5, count 0 2006.257.03:11:48.19#ibcon#about to read 6, iclass 5, count 0 2006.257.03:11:48.19#ibcon#read 6, iclass 5, count 0 2006.257.03:11:48.19#ibcon#end of sib2, iclass 5, count 0 2006.257.03:11:48.19#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:11:48.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:11:48.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:11:48.19#ibcon#*before write, iclass 5, count 0 2006.257.03:11:48.19#ibcon#enter sib2, iclass 5, count 0 2006.257.03:11:48.19#ibcon#flushed, iclass 5, count 0 2006.257.03:11:48.19#ibcon#about to write, iclass 5, count 0 2006.257.03:11:48.19#ibcon#wrote, iclass 5, count 0 2006.257.03:11:48.19#ibcon#about to read 3, iclass 5, count 0 2006.257.03:11:48.23#ibcon#read 3, iclass 5, count 0 2006.257.03:11:48.23#ibcon#about to read 4, iclass 5, count 0 2006.257.03:11:48.23#ibcon#read 4, iclass 5, count 0 2006.257.03:11:48.23#ibcon#about to read 5, iclass 5, count 0 2006.257.03:11:48.23#ibcon#read 5, iclass 5, count 0 2006.257.03:11:48.23#ibcon#about to read 6, iclass 5, count 0 2006.257.03:11:48.23#ibcon#read 6, iclass 5, count 0 2006.257.03:11:48.23#ibcon#end of sib2, iclass 5, count 0 2006.257.03:11:48.23#ibcon#*after write, iclass 5, count 0 2006.257.03:11:48.23#ibcon#*before return 0, iclass 5, count 0 2006.257.03:11:48.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:48.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:48.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:11:48.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:11:48.23$vck44/va=2,7 2006.257.03:11:48.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.03:11:48.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.03:11:48.23#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:48.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:48.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:48.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:48.29#ibcon#enter wrdev, iclass 7, count 2 2006.257.03:11:48.29#ibcon#first serial, iclass 7, count 2 2006.257.03:11:48.29#ibcon#enter sib2, iclass 7, count 2 2006.257.03:11:48.29#ibcon#flushed, iclass 7, count 2 2006.257.03:11:48.29#ibcon#about to write, iclass 7, count 2 2006.257.03:11:48.29#ibcon#wrote, iclass 7, count 2 2006.257.03:11:48.29#ibcon#about to read 3, iclass 7, count 2 2006.257.03:11:48.31#ibcon#read 3, iclass 7, count 2 2006.257.03:11:48.31#ibcon#about to read 4, iclass 7, count 2 2006.257.03:11:48.31#ibcon#read 4, iclass 7, count 2 2006.257.03:11:48.31#ibcon#about to read 5, iclass 7, count 2 2006.257.03:11:48.31#ibcon#read 5, iclass 7, count 2 2006.257.03:11:48.31#ibcon#about to read 6, iclass 7, count 2 2006.257.03:11:48.31#ibcon#read 6, iclass 7, count 2 2006.257.03:11:48.31#ibcon#end of sib2, iclass 7, count 2 2006.257.03:11:48.31#ibcon#*mode == 0, iclass 7, count 2 2006.257.03:11:48.31#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.03:11:48.31#ibcon#[25=AT02-07\r\n] 2006.257.03:11:48.31#ibcon#*before write, iclass 7, count 2 2006.257.03:11:48.31#ibcon#enter sib2, iclass 7, count 2 2006.257.03:11:48.31#ibcon#flushed, iclass 7, count 2 2006.257.03:11:48.31#ibcon#about to write, iclass 7, count 2 2006.257.03:11:48.31#ibcon#wrote, iclass 7, count 2 2006.257.03:11:48.31#ibcon#about to read 3, iclass 7, count 2 2006.257.03:11:48.34#ibcon#read 3, iclass 7, count 2 2006.257.03:11:48.34#ibcon#about to read 4, iclass 7, count 2 2006.257.03:11:48.34#ibcon#read 4, iclass 7, count 2 2006.257.03:11:48.34#ibcon#about to read 5, iclass 7, count 2 2006.257.03:11:48.34#ibcon#read 5, iclass 7, count 2 2006.257.03:11:48.34#ibcon#about to read 6, iclass 7, count 2 2006.257.03:11:48.34#ibcon#read 6, iclass 7, count 2 2006.257.03:11:48.34#ibcon#end of sib2, iclass 7, count 2 2006.257.03:11:48.34#ibcon#*after write, iclass 7, count 2 2006.257.03:11:48.34#ibcon#*before return 0, iclass 7, count 2 2006.257.03:11:48.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:48.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:48.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.03:11:48.34#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:48.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:48.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:48.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:48.46#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:11:48.46#ibcon#first serial, iclass 7, count 0 2006.257.03:11:48.46#ibcon#enter sib2, iclass 7, count 0 2006.257.03:11:48.46#ibcon#flushed, iclass 7, count 0 2006.257.03:11:48.46#ibcon#about to write, iclass 7, count 0 2006.257.03:11:48.46#ibcon#wrote, iclass 7, count 0 2006.257.03:11:48.46#ibcon#about to read 3, iclass 7, count 0 2006.257.03:11:48.48#ibcon#read 3, iclass 7, count 0 2006.257.03:11:48.48#ibcon#about to read 4, iclass 7, count 0 2006.257.03:11:48.48#ibcon#read 4, iclass 7, count 0 2006.257.03:11:48.48#ibcon#about to read 5, iclass 7, count 0 2006.257.03:11:48.48#ibcon#read 5, iclass 7, count 0 2006.257.03:11:48.48#ibcon#about to read 6, iclass 7, count 0 2006.257.03:11:48.48#ibcon#read 6, iclass 7, count 0 2006.257.03:11:48.48#ibcon#end of sib2, iclass 7, count 0 2006.257.03:11:48.48#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:11:48.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:11:48.48#ibcon#[25=USB\r\n] 2006.257.03:11:48.48#ibcon#*before write, iclass 7, count 0 2006.257.03:11:48.48#ibcon#enter sib2, iclass 7, count 0 2006.257.03:11:48.48#ibcon#flushed, iclass 7, count 0 2006.257.03:11:48.48#ibcon#about to write, iclass 7, count 0 2006.257.03:11:48.48#ibcon#wrote, iclass 7, count 0 2006.257.03:11:48.48#ibcon#about to read 3, iclass 7, count 0 2006.257.03:11:48.51#ibcon#read 3, iclass 7, count 0 2006.257.03:11:48.51#ibcon#about to read 4, iclass 7, count 0 2006.257.03:11:48.51#ibcon#read 4, iclass 7, count 0 2006.257.03:11:48.51#ibcon#about to read 5, iclass 7, count 0 2006.257.03:11:48.51#ibcon#read 5, iclass 7, count 0 2006.257.03:11:48.51#ibcon#about to read 6, iclass 7, count 0 2006.257.03:11:48.51#ibcon#read 6, iclass 7, count 0 2006.257.03:11:48.51#ibcon#end of sib2, iclass 7, count 0 2006.257.03:11:48.51#ibcon#*after write, iclass 7, count 0 2006.257.03:11:48.51#ibcon#*before return 0, iclass 7, count 0 2006.257.03:11:48.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:48.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:48.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:11:48.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:11:48.51$vck44/valo=3,564.99 2006.257.03:11:48.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.03:11:48.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.03:11:48.51#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:48.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:48.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:48.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:48.51#ibcon#enter wrdev, iclass 11, count 0 2006.257.03:11:48.51#ibcon#first serial, iclass 11, count 0 2006.257.03:11:48.51#ibcon#enter sib2, iclass 11, count 0 2006.257.03:11:48.51#ibcon#flushed, iclass 11, count 0 2006.257.03:11:48.51#ibcon#about to write, iclass 11, count 0 2006.257.03:11:48.51#ibcon#wrote, iclass 11, count 0 2006.257.03:11:48.51#ibcon#about to read 3, iclass 11, count 0 2006.257.03:11:48.53#ibcon#read 3, iclass 11, count 0 2006.257.03:11:48.53#ibcon#about to read 4, iclass 11, count 0 2006.257.03:11:48.53#ibcon#read 4, iclass 11, count 0 2006.257.03:11:48.53#ibcon#about to read 5, iclass 11, count 0 2006.257.03:11:48.53#ibcon#read 5, iclass 11, count 0 2006.257.03:11:48.53#ibcon#about to read 6, iclass 11, count 0 2006.257.03:11:48.53#ibcon#read 6, iclass 11, count 0 2006.257.03:11:48.53#ibcon#end of sib2, iclass 11, count 0 2006.257.03:11:48.53#ibcon#*mode == 0, iclass 11, count 0 2006.257.03:11:48.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.03:11:48.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:11:48.53#ibcon#*before write, iclass 11, count 0 2006.257.03:11:48.53#ibcon#enter sib2, iclass 11, count 0 2006.257.03:11:48.53#ibcon#flushed, iclass 11, count 0 2006.257.03:11:48.53#ibcon#about to write, iclass 11, count 0 2006.257.03:11:48.53#ibcon#wrote, iclass 11, count 0 2006.257.03:11:48.53#ibcon#about to read 3, iclass 11, count 0 2006.257.03:11:48.57#ibcon#read 3, iclass 11, count 0 2006.257.03:11:48.57#ibcon#about to read 4, iclass 11, count 0 2006.257.03:11:48.57#ibcon#read 4, iclass 11, count 0 2006.257.03:11:48.57#ibcon#about to read 5, iclass 11, count 0 2006.257.03:11:48.57#ibcon#read 5, iclass 11, count 0 2006.257.03:11:48.57#ibcon#about to read 6, iclass 11, count 0 2006.257.03:11:48.57#ibcon#read 6, iclass 11, count 0 2006.257.03:11:48.57#ibcon#end of sib2, iclass 11, count 0 2006.257.03:11:48.57#ibcon#*after write, iclass 11, count 0 2006.257.03:11:48.57#ibcon#*before return 0, iclass 11, count 0 2006.257.03:11:48.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:48.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:48.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.03:11:48.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.03:11:48.57$vck44/va=3,8 2006.257.03:11:48.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.03:11:48.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.03:11:48.57#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:48.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:48.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:48.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:48.63#ibcon#enter wrdev, iclass 13, count 2 2006.257.03:11:48.63#ibcon#first serial, iclass 13, count 2 2006.257.03:11:48.63#ibcon#enter sib2, iclass 13, count 2 2006.257.03:11:48.63#ibcon#flushed, iclass 13, count 2 2006.257.03:11:48.63#ibcon#about to write, iclass 13, count 2 2006.257.03:11:48.63#ibcon#wrote, iclass 13, count 2 2006.257.03:11:48.63#ibcon#about to read 3, iclass 13, count 2 2006.257.03:11:48.65#ibcon#read 3, iclass 13, count 2 2006.257.03:11:48.65#ibcon#about to read 4, iclass 13, count 2 2006.257.03:11:48.65#ibcon#read 4, iclass 13, count 2 2006.257.03:11:48.65#ibcon#about to read 5, iclass 13, count 2 2006.257.03:11:48.65#ibcon#read 5, iclass 13, count 2 2006.257.03:11:48.65#ibcon#about to read 6, iclass 13, count 2 2006.257.03:11:48.65#ibcon#read 6, iclass 13, count 2 2006.257.03:11:48.65#ibcon#end of sib2, iclass 13, count 2 2006.257.03:11:48.65#ibcon#*mode == 0, iclass 13, count 2 2006.257.03:11:48.65#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.03:11:48.65#ibcon#[25=AT03-08\r\n] 2006.257.03:11:48.65#ibcon#*before write, iclass 13, count 2 2006.257.03:11:48.65#ibcon#enter sib2, iclass 13, count 2 2006.257.03:11:48.65#ibcon#flushed, iclass 13, count 2 2006.257.03:11:48.65#ibcon#about to write, iclass 13, count 2 2006.257.03:11:48.65#ibcon#wrote, iclass 13, count 2 2006.257.03:11:48.65#ibcon#about to read 3, iclass 13, count 2 2006.257.03:11:48.68#ibcon#read 3, iclass 13, count 2 2006.257.03:11:48.68#ibcon#about to read 4, iclass 13, count 2 2006.257.03:11:48.68#ibcon#read 4, iclass 13, count 2 2006.257.03:11:48.68#ibcon#about to read 5, iclass 13, count 2 2006.257.03:11:48.68#ibcon#read 5, iclass 13, count 2 2006.257.03:11:48.68#ibcon#about to read 6, iclass 13, count 2 2006.257.03:11:48.68#ibcon#read 6, iclass 13, count 2 2006.257.03:11:48.68#ibcon#end of sib2, iclass 13, count 2 2006.257.03:11:48.68#ibcon#*after write, iclass 13, count 2 2006.257.03:11:48.68#ibcon#*before return 0, iclass 13, count 2 2006.257.03:11:48.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:48.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:48.68#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.03:11:48.68#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:48.68#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:48.80#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:48.80#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:48.80#ibcon#enter wrdev, iclass 13, count 0 2006.257.03:11:48.80#ibcon#first serial, iclass 13, count 0 2006.257.03:11:48.80#ibcon#enter sib2, iclass 13, count 0 2006.257.03:11:48.80#ibcon#flushed, iclass 13, count 0 2006.257.03:11:48.80#ibcon#about to write, iclass 13, count 0 2006.257.03:11:48.80#ibcon#wrote, iclass 13, count 0 2006.257.03:11:48.80#ibcon#about to read 3, iclass 13, count 0 2006.257.03:11:48.82#ibcon#read 3, iclass 13, count 0 2006.257.03:11:48.82#ibcon#about to read 4, iclass 13, count 0 2006.257.03:11:48.82#ibcon#read 4, iclass 13, count 0 2006.257.03:11:48.82#ibcon#about to read 5, iclass 13, count 0 2006.257.03:11:48.82#ibcon#read 5, iclass 13, count 0 2006.257.03:11:48.82#ibcon#about to read 6, iclass 13, count 0 2006.257.03:11:48.82#ibcon#read 6, iclass 13, count 0 2006.257.03:11:48.82#ibcon#end of sib2, iclass 13, count 0 2006.257.03:11:48.82#ibcon#*mode == 0, iclass 13, count 0 2006.257.03:11:48.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.03:11:48.82#ibcon#[25=USB\r\n] 2006.257.03:11:48.82#ibcon#*before write, iclass 13, count 0 2006.257.03:11:48.82#ibcon#enter sib2, iclass 13, count 0 2006.257.03:11:48.82#ibcon#flushed, iclass 13, count 0 2006.257.03:11:48.82#ibcon#about to write, iclass 13, count 0 2006.257.03:11:48.82#ibcon#wrote, iclass 13, count 0 2006.257.03:11:48.82#ibcon#about to read 3, iclass 13, count 0 2006.257.03:11:48.85#ibcon#read 3, iclass 13, count 0 2006.257.03:11:48.85#ibcon#about to read 4, iclass 13, count 0 2006.257.03:11:48.85#ibcon#read 4, iclass 13, count 0 2006.257.03:11:48.85#ibcon#about to read 5, iclass 13, count 0 2006.257.03:11:48.85#ibcon#read 5, iclass 13, count 0 2006.257.03:11:48.85#ibcon#about to read 6, iclass 13, count 0 2006.257.03:11:48.85#ibcon#read 6, iclass 13, count 0 2006.257.03:11:48.85#ibcon#end of sib2, iclass 13, count 0 2006.257.03:11:48.85#ibcon#*after write, iclass 13, count 0 2006.257.03:11:48.85#ibcon#*before return 0, iclass 13, count 0 2006.257.03:11:48.85#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:48.85#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:48.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.03:11:48.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.03:11:48.85$vck44/valo=4,624.99 2006.257.03:11:48.85#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.03:11:48.85#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.03:11:48.85#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:48.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:48.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:48.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:48.85#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:11:48.85#ibcon#first serial, iclass 15, count 0 2006.257.03:11:48.85#ibcon#enter sib2, iclass 15, count 0 2006.257.03:11:48.85#ibcon#flushed, iclass 15, count 0 2006.257.03:11:48.85#ibcon#about to write, iclass 15, count 0 2006.257.03:11:48.85#ibcon#wrote, iclass 15, count 0 2006.257.03:11:48.85#ibcon#about to read 3, iclass 15, count 0 2006.257.03:11:48.87#ibcon#read 3, iclass 15, count 0 2006.257.03:11:48.87#ibcon#about to read 4, iclass 15, count 0 2006.257.03:11:48.87#ibcon#read 4, iclass 15, count 0 2006.257.03:11:48.87#ibcon#about to read 5, iclass 15, count 0 2006.257.03:11:48.87#ibcon#read 5, iclass 15, count 0 2006.257.03:11:48.87#ibcon#about to read 6, iclass 15, count 0 2006.257.03:11:48.87#ibcon#read 6, iclass 15, count 0 2006.257.03:11:48.87#ibcon#end of sib2, iclass 15, count 0 2006.257.03:11:48.87#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:11:48.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:11:48.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:11:48.87#ibcon#*before write, iclass 15, count 0 2006.257.03:11:48.87#ibcon#enter sib2, iclass 15, count 0 2006.257.03:11:48.87#ibcon#flushed, iclass 15, count 0 2006.257.03:11:48.87#ibcon#about to write, iclass 15, count 0 2006.257.03:11:48.87#ibcon#wrote, iclass 15, count 0 2006.257.03:11:48.87#ibcon#about to read 3, iclass 15, count 0 2006.257.03:11:48.91#ibcon#read 3, iclass 15, count 0 2006.257.03:11:48.91#ibcon#about to read 4, iclass 15, count 0 2006.257.03:11:48.91#ibcon#read 4, iclass 15, count 0 2006.257.03:11:48.91#ibcon#about to read 5, iclass 15, count 0 2006.257.03:11:48.91#ibcon#read 5, iclass 15, count 0 2006.257.03:11:48.91#ibcon#about to read 6, iclass 15, count 0 2006.257.03:11:48.91#ibcon#read 6, iclass 15, count 0 2006.257.03:11:48.91#ibcon#end of sib2, iclass 15, count 0 2006.257.03:11:48.91#ibcon#*after write, iclass 15, count 0 2006.257.03:11:48.91#ibcon#*before return 0, iclass 15, count 0 2006.257.03:11:48.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:48.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:48.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:11:48.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:11:48.91$vck44/va=4,7 2006.257.03:11:48.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.03:11:48.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.03:11:48.91#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:48.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:48.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:48.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:48.97#ibcon#enter wrdev, iclass 17, count 2 2006.257.03:11:48.97#ibcon#first serial, iclass 17, count 2 2006.257.03:11:48.97#ibcon#enter sib2, iclass 17, count 2 2006.257.03:11:48.97#ibcon#flushed, iclass 17, count 2 2006.257.03:11:48.97#ibcon#about to write, iclass 17, count 2 2006.257.03:11:48.97#ibcon#wrote, iclass 17, count 2 2006.257.03:11:48.97#ibcon#about to read 3, iclass 17, count 2 2006.257.03:11:48.99#ibcon#read 3, iclass 17, count 2 2006.257.03:11:48.99#ibcon#about to read 4, iclass 17, count 2 2006.257.03:11:48.99#ibcon#read 4, iclass 17, count 2 2006.257.03:11:48.99#ibcon#about to read 5, iclass 17, count 2 2006.257.03:11:48.99#ibcon#read 5, iclass 17, count 2 2006.257.03:11:48.99#ibcon#about to read 6, iclass 17, count 2 2006.257.03:11:48.99#ibcon#read 6, iclass 17, count 2 2006.257.03:11:48.99#ibcon#end of sib2, iclass 17, count 2 2006.257.03:11:48.99#ibcon#*mode == 0, iclass 17, count 2 2006.257.03:11:48.99#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.03:11:48.99#ibcon#[25=AT04-07\r\n] 2006.257.03:11:48.99#ibcon#*before write, iclass 17, count 2 2006.257.03:11:48.99#ibcon#enter sib2, iclass 17, count 2 2006.257.03:11:48.99#ibcon#flushed, iclass 17, count 2 2006.257.03:11:48.99#ibcon#about to write, iclass 17, count 2 2006.257.03:11:48.99#ibcon#wrote, iclass 17, count 2 2006.257.03:11:48.99#ibcon#about to read 3, iclass 17, count 2 2006.257.03:11:49.02#ibcon#read 3, iclass 17, count 2 2006.257.03:11:49.02#ibcon#about to read 4, iclass 17, count 2 2006.257.03:11:49.02#ibcon#read 4, iclass 17, count 2 2006.257.03:11:49.02#ibcon#about to read 5, iclass 17, count 2 2006.257.03:11:49.02#ibcon#read 5, iclass 17, count 2 2006.257.03:11:49.02#ibcon#about to read 6, iclass 17, count 2 2006.257.03:11:49.02#ibcon#read 6, iclass 17, count 2 2006.257.03:11:49.02#ibcon#end of sib2, iclass 17, count 2 2006.257.03:11:49.02#ibcon#*after write, iclass 17, count 2 2006.257.03:11:49.02#ibcon#*before return 0, iclass 17, count 2 2006.257.03:11:49.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:49.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:49.02#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.03:11:49.02#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:49.02#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:49.14#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:49.14#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:49.14#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:11:49.14#ibcon#first serial, iclass 17, count 0 2006.257.03:11:49.14#ibcon#enter sib2, iclass 17, count 0 2006.257.03:11:49.14#ibcon#flushed, iclass 17, count 0 2006.257.03:11:49.14#ibcon#about to write, iclass 17, count 0 2006.257.03:11:49.14#ibcon#wrote, iclass 17, count 0 2006.257.03:11:49.14#ibcon#about to read 3, iclass 17, count 0 2006.257.03:11:49.16#ibcon#read 3, iclass 17, count 0 2006.257.03:11:49.16#ibcon#about to read 4, iclass 17, count 0 2006.257.03:11:49.16#ibcon#read 4, iclass 17, count 0 2006.257.03:11:49.16#ibcon#about to read 5, iclass 17, count 0 2006.257.03:11:49.16#ibcon#read 5, iclass 17, count 0 2006.257.03:11:49.16#ibcon#about to read 6, iclass 17, count 0 2006.257.03:11:49.16#ibcon#read 6, iclass 17, count 0 2006.257.03:11:49.16#ibcon#end of sib2, iclass 17, count 0 2006.257.03:11:49.16#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:11:49.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:11:49.16#ibcon#[25=USB\r\n] 2006.257.03:11:49.16#ibcon#*before write, iclass 17, count 0 2006.257.03:11:49.16#ibcon#enter sib2, iclass 17, count 0 2006.257.03:11:49.16#ibcon#flushed, iclass 17, count 0 2006.257.03:11:49.16#ibcon#about to write, iclass 17, count 0 2006.257.03:11:49.16#ibcon#wrote, iclass 17, count 0 2006.257.03:11:49.16#ibcon#about to read 3, iclass 17, count 0 2006.257.03:11:49.19#ibcon#read 3, iclass 17, count 0 2006.257.03:11:49.19#ibcon#about to read 4, iclass 17, count 0 2006.257.03:11:49.19#ibcon#read 4, iclass 17, count 0 2006.257.03:11:49.19#ibcon#about to read 5, iclass 17, count 0 2006.257.03:11:49.19#ibcon#read 5, iclass 17, count 0 2006.257.03:11:49.19#ibcon#about to read 6, iclass 17, count 0 2006.257.03:11:49.19#ibcon#read 6, iclass 17, count 0 2006.257.03:11:49.19#ibcon#end of sib2, iclass 17, count 0 2006.257.03:11:49.19#ibcon#*after write, iclass 17, count 0 2006.257.03:11:49.19#ibcon#*before return 0, iclass 17, count 0 2006.257.03:11:49.19#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:49.19#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:49.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:11:49.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:11:49.19$vck44/valo=5,734.99 2006.257.03:11:49.19#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.03:11:49.19#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.03:11:49.19#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:49.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:49.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:49.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:49.19#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:11:49.19#ibcon#first serial, iclass 19, count 0 2006.257.03:11:49.19#ibcon#enter sib2, iclass 19, count 0 2006.257.03:11:49.19#ibcon#flushed, iclass 19, count 0 2006.257.03:11:49.19#ibcon#about to write, iclass 19, count 0 2006.257.03:11:49.19#ibcon#wrote, iclass 19, count 0 2006.257.03:11:49.19#ibcon#about to read 3, iclass 19, count 0 2006.257.03:11:49.21#ibcon#read 3, iclass 19, count 0 2006.257.03:11:49.21#ibcon#about to read 4, iclass 19, count 0 2006.257.03:11:49.21#ibcon#read 4, iclass 19, count 0 2006.257.03:11:49.21#ibcon#about to read 5, iclass 19, count 0 2006.257.03:11:49.21#ibcon#read 5, iclass 19, count 0 2006.257.03:11:49.21#ibcon#about to read 6, iclass 19, count 0 2006.257.03:11:49.21#ibcon#read 6, iclass 19, count 0 2006.257.03:11:49.21#ibcon#end of sib2, iclass 19, count 0 2006.257.03:11:49.21#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:11:49.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:11:49.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:11:49.21#ibcon#*before write, iclass 19, count 0 2006.257.03:11:49.21#ibcon#enter sib2, iclass 19, count 0 2006.257.03:11:49.21#ibcon#flushed, iclass 19, count 0 2006.257.03:11:49.21#ibcon#about to write, iclass 19, count 0 2006.257.03:11:49.21#ibcon#wrote, iclass 19, count 0 2006.257.03:11:49.21#ibcon#about to read 3, iclass 19, count 0 2006.257.03:11:49.25#ibcon#read 3, iclass 19, count 0 2006.257.03:11:49.25#ibcon#about to read 4, iclass 19, count 0 2006.257.03:11:49.25#ibcon#read 4, iclass 19, count 0 2006.257.03:11:49.25#ibcon#about to read 5, iclass 19, count 0 2006.257.03:11:49.25#ibcon#read 5, iclass 19, count 0 2006.257.03:11:49.25#ibcon#about to read 6, iclass 19, count 0 2006.257.03:11:49.25#ibcon#read 6, iclass 19, count 0 2006.257.03:11:49.25#ibcon#end of sib2, iclass 19, count 0 2006.257.03:11:49.25#ibcon#*after write, iclass 19, count 0 2006.257.03:11:49.25#ibcon#*before return 0, iclass 19, count 0 2006.257.03:11:49.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:49.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:49.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:11:49.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:11:49.25$vck44/va=5,4 2006.257.03:11:49.25#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.03:11:49.25#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.03:11:49.25#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:49.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:49.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:49.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:49.31#ibcon#enter wrdev, iclass 21, count 2 2006.257.03:11:49.31#ibcon#first serial, iclass 21, count 2 2006.257.03:11:49.31#ibcon#enter sib2, iclass 21, count 2 2006.257.03:11:49.31#ibcon#flushed, iclass 21, count 2 2006.257.03:11:49.31#ibcon#about to write, iclass 21, count 2 2006.257.03:11:49.31#ibcon#wrote, iclass 21, count 2 2006.257.03:11:49.31#ibcon#about to read 3, iclass 21, count 2 2006.257.03:11:49.33#ibcon#read 3, iclass 21, count 2 2006.257.03:11:49.33#ibcon#about to read 4, iclass 21, count 2 2006.257.03:11:49.33#ibcon#read 4, iclass 21, count 2 2006.257.03:11:49.33#ibcon#about to read 5, iclass 21, count 2 2006.257.03:11:49.33#ibcon#read 5, iclass 21, count 2 2006.257.03:11:49.33#ibcon#about to read 6, iclass 21, count 2 2006.257.03:11:49.33#ibcon#read 6, iclass 21, count 2 2006.257.03:11:49.33#ibcon#end of sib2, iclass 21, count 2 2006.257.03:11:49.33#ibcon#*mode == 0, iclass 21, count 2 2006.257.03:11:49.33#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.03:11:49.33#ibcon#[25=AT05-04\r\n] 2006.257.03:11:49.33#ibcon#*before write, iclass 21, count 2 2006.257.03:11:49.33#ibcon#enter sib2, iclass 21, count 2 2006.257.03:11:49.33#ibcon#flushed, iclass 21, count 2 2006.257.03:11:49.33#ibcon#about to write, iclass 21, count 2 2006.257.03:11:49.33#ibcon#wrote, iclass 21, count 2 2006.257.03:11:49.33#ibcon#about to read 3, iclass 21, count 2 2006.257.03:11:49.36#ibcon#read 3, iclass 21, count 2 2006.257.03:11:49.36#ibcon#about to read 4, iclass 21, count 2 2006.257.03:11:49.36#ibcon#read 4, iclass 21, count 2 2006.257.03:11:49.36#ibcon#about to read 5, iclass 21, count 2 2006.257.03:11:49.36#ibcon#read 5, iclass 21, count 2 2006.257.03:11:49.36#ibcon#about to read 6, iclass 21, count 2 2006.257.03:11:49.36#ibcon#read 6, iclass 21, count 2 2006.257.03:11:49.36#ibcon#end of sib2, iclass 21, count 2 2006.257.03:11:49.36#ibcon#*after write, iclass 21, count 2 2006.257.03:11:49.36#ibcon#*before return 0, iclass 21, count 2 2006.257.03:11:49.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:49.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:49.36#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.03:11:49.36#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:49.36#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:49.48#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:49.48#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:49.48#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:11:49.48#ibcon#first serial, iclass 21, count 0 2006.257.03:11:49.48#ibcon#enter sib2, iclass 21, count 0 2006.257.03:11:49.48#ibcon#flushed, iclass 21, count 0 2006.257.03:11:49.48#ibcon#about to write, iclass 21, count 0 2006.257.03:11:49.48#ibcon#wrote, iclass 21, count 0 2006.257.03:11:49.48#ibcon#about to read 3, iclass 21, count 0 2006.257.03:11:49.50#ibcon#read 3, iclass 21, count 0 2006.257.03:11:49.50#ibcon#about to read 4, iclass 21, count 0 2006.257.03:11:49.50#ibcon#read 4, iclass 21, count 0 2006.257.03:11:49.50#ibcon#about to read 5, iclass 21, count 0 2006.257.03:11:49.50#ibcon#read 5, iclass 21, count 0 2006.257.03:11:49.50#ibcon#about to read 6, iclass 21, count 0 2006.257.03:11:49.50#ibcon#read 6, iclass 21, count 0 2006.257.03:11:49.50#ibcon#end of sib2, iclass 21, count 0 2006.257.03:11:49.50#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:11:49.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:11:49.50#ibcon#[25=USB\r\n] 2006.257.03:11:49.50#ibcon#*before write, iclass 21, count 0 2006.257.03:11:49.50#ibcon#enter sib2, iclass 21, count 0 2006.257.03:11:49.50#ibcon#flushed, iclass 21, count 0 2006.257.03:11:49.50#ibcon#about to write, iclass 21, count 0 2006.257.03:11:49.50#ibcon#wrote, iclass 21, count 0 2006.257.03:11:49.50#ibcon#about to read 3, iclass 21, count 0 2006.257.03:11:49.53#ibcon#read 3, iclass 21, count 0 2006.257.03:11:49.53#ibcon#about to read 4, iclass 21, count 0 2006.257.03:11:49.53#ibcon#read 4, iclass 21, count 0 2006.257.03:11:49.53#ibcon#about to read 5, iclass 21, count 0 2006.257.03:11:49.53#ibcon#read 5, iclass 21, count 0 2006.257.03:11:49.53#ibcon#about to read 6, iclass 21, count 0 2006.257.03:11:49.53#ibcon#read 6, iclass 21, count 0 2006.257.03:11:49.53#ibcon#end of sib2, iclass 21, count 0 2006.257.03:11:49.53#ibcon#*after write, iclass 21, count 0 2006.257.03:11:49.53#ibcon#*before return 0, iclass 21, count 0 2006.257.03:11:49.53#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:49.53#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:49.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:11:49.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:11:49.53$vck44/valo=6,814.99 2006.257.03:11:49.53#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.03:11:49.53#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.03:11:49.53#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:49.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:49.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:49.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:49.53#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:11:49.53#ibcon#first serial, iclass 23, count 0 2006.257.03:11:49.53#ibcon#enter sib2, iclass 23, count 0 2006.257.03:11:49.53#ibcon#flushed, iclass 23, count 0 2006.257.03:11:49.53#ibcon#about to write, iclass 23, count 0 2006.257.03:11:49.53#ibcon#wrote, iclass 23, count 0 2006.257.03:11:49.53#ibcon#about to read 3, iclass 23, count 0 2006.257.03:11:49.55#ibcon#read 3, iclass 23, count 0 2006.257.03:11:49.55#ibcon#about to read 4, iclass 23, count 0 2006.257.03:11:49.55#ibcon#read 4, iclass 23, count 0 2006.257.03:11:49.55#ibcon#about to read 5, iclass 23, count 0 2006.257.03:11:49.55#ibcon#read 5, iclass 23, count 0 2006.257.03:11:49.55#ibcon#about to read 6, iclass 23, count 0 2006.257.03:11:49.55#ibcon#read 6, iclass 23, count 0 2006.257.03:11:49.55#ibcon#end of sib2, iclass 23, count 0 2006.257.03:11:49.55#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:11:49.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:11:49.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:11:49.55#ibcon#*before write, iclass 23, count 0 2006.257.03:11:49.55#ibcon#enter sib2, iclass 23, count 0 2006.257.03:11:49.55#ibcon#flushed, iclass 23, count 0 2006.257.03:11:49.55#ibcon#about to write, iclass 23, count 0 2006.257.03:11:49.55#ibcon#wrote, iclass 23, count 0 2006.257.03:11:49.55#ibcon#about to read 3, iclass 23, count 0 2006.257.03:11:49.59#ibcon#read 3, iclass 23, count 0 2006.257.03:11:49.59#ibcon#about to read 4, iclass 23, count 0 2006.257.03:11:49.59#ibcon#read 4, iclass 23, count 0 2006.257.03:11:49.59#ibcon#about to read 5, iclass 23, count 0 2006.257.03:11:49.59#ibcon#read 5, iclass 23, count 0 2006.257.03:11:49.59#ibcon#about to read 6, iclass 23, count 0 2006.257.03:11:49.59#ibcon#read 6, iclass 23, count 0 2006.257.03:11:49.59#ibcon#end of sib2, iclass 23, count 0 2006.257.03:11:49.59#ibcon#*after write, iclass 23, count 0 2006.257.03:11:49.59#ibcon#*before return 0, iclass 23, count 0 2006.257.03:11:49.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:49.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:49.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:11:49.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:11:49.59$vck44/va=6,4 2006.257.03:11:49.59#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.03:11:49.59#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.03:11:49.59#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:49.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:49.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:49.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:49.65#ibcon#enter wrdev, iclass 25, count 2 2006.257.03:11:49.65#ibcon#first serial, iclass 25, count 2 2006.257.03:11:49.65#ibcon#enter sib2, iclass 25, count 2 2006.257.03:11:49.65#ibcon#flushed, iclass 25, count 2 2006.257.03:11:49.65#ibcon#about to write, iclass 25, count 2 2006.257.03:11:49.65#ibcon#wrote, iclass 25, count 2 2006.257.03:11:49.65#ibcon#about to read 3, iclass 25, count 2 2006.257.03:11:49.67#ibcon#read 3, iclass 25, count 2 2006.257.03:11:49.67#ibcon#about to read 4, iclass 25, count 2 2006.257.03:11:49.67#ibcon#read 4, iclass 25, count 2 2006.257.03:11:49.67#ibcon#about to read 5, iclass 25, count 2 2006.257.03:11:49.67#ibcon#read 5, iclass 25, count 2 2006.257.03:11:49.67#ibcon#about to read 6, iclass 25, count 2 2006.257.03:11:49.67#ibcon#read 6, iclass 25, count 2 2006.257.03:11:49.67#ibcon#end of sib2, iclass 25, count 2 2006.257.03:11:49.67#ibcon#*mode == 0, iclass 25, count 2 2006.257.03:11:49.67#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.03:11:49.67#ibcon#[25=AT06-04\r\n] 2006.257.03:11:49.67#ibcon#*before write, iclass 25, count 2 2006.257.03:11:49.67#ibcon#enter sib2, iclass 25, count 2 2006.257.03:11:49.67#ibcon#flushed, iclass 25, count 2 2006.257.03:11:49.67#ibcon#about to write, iclass 25, count 2 2006.257.03:11:49.67#ibcon#wrote, iclass 25, count 2 2006.257.03:11:49.67#ibcon#about to read 3, iclass 25, count 2 2006.257.03:11:49.70#ibcon#read 3, iclass 25, count 2 2006.257.03:11:49.70#ibcon#about to read 4, iclass 25, count 2 2006.257.03:11:49.70#ibcon#read 4, iclass 25, count 2 2006.257.03:11:49.70#ibcon#about to read 5, iclass 25, count 2 2006.257.03:11:49.70#ibcon#read 5, iclass 25, count 2 2006.257.03:11:49.70#ibcon#about to read 6, iclass 25, count 2 2006.257.03:11:49.70#ibcon#read 6, iclass 25, count 2 2006.257.03:11:49.70#ibcon#end of sib2, iclass 25, count 2 2006.257.03:11:49.70#ibcon#*after write, iclass 25, count 2 2006.257.03:11:49.70#ibcon#*before return 0, iclass 25, count 2 2006.257.03:11:49.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:49.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:49.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.03:11:49.70#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:49.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:49.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:49.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:49.82#ibcon#enter wrdev, iclass 25, count 0 2006.257.03:11:49.82#ibcon#first serial, iclass 25, count 0 2006.257.03:11:49.82#ibcon#enter sib2, iclass 25, count 0 2006.257.03:11:49.82#ibcon#flushed, iclass 25, count 0 2006.257.03:11:49.82#ibcon#about to write, iclass 25, count 0 2006.257.03:11:49.82#ibcon#wrote, iclass 25, count 0 2006.257.03:11:49.82#ibcon#about to read 3, iclass 25, count 0 2006.257.03:11:49.84#ibcon#read 3, iclass 25, count 0 2006.257.03:11:49.84#ibcon#about to read 4, iclass 25, count 0 2006.257.03:11:49.84#ibcon#read 4, iclass 25, count 0 2006.257.03:11:49.84#ibcon#about to read 5, iclass 25, count 0 2006.257.03:11:49.84#ibcon#read 5, iclass 25, count 0 2006.257.03:11:49.84#ibcon#about to read 6, iclass 25, count 0 2006.257.03:11:49.84#ibcon#read 6, iclass 25, count 0 2006.257.03:11:49.84#ibcon#end of sib2, iclass 25, count 0 2006.257.03:11:49.84#ibcon#*mode == 0, iclass 25, count 0 2006.257.03:11:49.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.03:11:49.84#ibcon#[25=USB\r\n] 2006.257.03:11:49.84#ibcon#*before write, iclass 25, count 0 2006.257.03:11:49.84#ibcon#enter sib2, iclass 25, count 0 2006.257.03:11:49.84#ibcon#flushed, iclass 25, count 0 2006.257.03:11:49.84#ibcon#about to write, iclass 25, count 0 2006.257.03:11:49.84#ibcon#wrote, iclass 25, count 0 2006.257.03:11:49.84#ibcon#about to read 3, iclass 25, count 0 2006.257.03:11:49.87#ibcon#read 3, iclass 25, count 0 2006.257.03:11:49.87#ibcon#about to read 4, iclass 25, count 0 2006.257.03:11:49.87#ibcon#read 4, iclass 25, count 0 2006.257.03:11:49.87#ibcon#about to read 5, iclass 25, count 0 2006.257.03:11:49.87#ibcon#read 5, iclass 25, count 0 2006.257.03:11:49.87#ibcon#about to read 6, iclass 25, count 0 2006.257.03:11:49.87#ibcon#read 6, iclass 25, count 0 2006.257.03:11:49.87#ibcon#end of sib2, iclass 25, count 0 2006.257.03:11:49.87#ibcon#*after write, iclass 25, count 0 2006.257.03:11:49.87#ibcon#*before return 0, iclass 25, count 0 2006.257.03:11:49.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:49.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:49.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.03:11:49.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.03:11:49.87$vck44/valo=7,864.99 2006.257.03:11:49.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.03:11:49.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.03:11:49.87#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:49.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:49.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:49.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:49.87#ibcon#enter wrdev, iclass 27, count 0 2006.257.03:11:49.87#ibcon#first serial, iclass 27, count 0 2006.257.03:11:49.87#ibcon#enter sib2, iclass 27, count 0 2006.257.03:11:49.87#ibcon#flushed, iclass 27, count 0 2006.257.03:11:49.87#ibcon#about to write, iclass 27, count 0 2006.257.03:11:49.87#ibcon#wrote, iclass 27, count 0 2006.257.03:11:49.87#ibcon#about to read 3, iclass 27, count 0 2006.257.03:11:49.89#ibcon#read 3, iclass 27, count 0 2006.257.03:11:49.89#ibcon#about to read 4, iclass 27, count 0 2006.257.03:11:49.89#ibcon#read 4, iclass 27, count 0 2006.257.03:11:49.89#ibcon#about to read 5, iclass 27, count 0 2006.257.03:11:49.89#ibcon#read 5, iclass 27, count 0 2006.257.03:11:49.89#ibcon#about to read 6, iclass 27, count 0 2006.257.03:11:49.89#ibcon#read 6, iclass 27, count 0 2006.257.03:11:49.89#ibcon#end of sib2, iclass 27, count 0 2006.257.03:11:49.89#ibcon#*mode == 0, iclass 27, count 0 2006.257.03:11:49.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.03:11:49.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:11:49.89#ibcon#*before write, iclass 27, count 0 2006.257.03:11:49.89#ibcon#enter sib2, iclass 27, count 0 2006.257.03:11:49.89#ibcon#flushed, iclass 27, count 0 2006.257.03:11:49.89#ibcon#about to write, iclass 27, count 0 2006.257.03:11:49.89#ibcon#wrote, iclass 27, count 0 2006.257.03:11:49.89#ibcon#about to read 3, iclass 27, count 0 2006.257.03:11:49.93#ibcon#read 3, iclass 27, count 0 2006.257.03:11:49.93#ibcon#about to read 4, iclass 27, count 0 2006.257.03:11:49.93#ibcon#read 4, iclass 27, count 0 2006.257.03:11:49.93#ibcon#about to read 5, iclass 27, count 0 2006.257.03:11:49.93#ibcon#read 5, iclass 27, count 0 2006.257.03:11:49.93#ibcon#about to read 6, iclass 27, count 0 2006.257.03:11:49.93#ibcon#read 6, iclass 27, count 0 2006.257.03:11:49.93#ibcon#end of sib2, iclass 27, count 0 2006.257.03:11:49.93#ibcon#*after write, iclass 27, count 0 2006.257.03:11:49.93#ibcon#*before return 0, iclass 27, count 0 2006.257.03:11:49.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:49.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:49.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.03:11:49.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.03:11:49.93$vck44/va=7,4 2006.257.03:11:49.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.03:11:49.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.03:11:49.93#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:49.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:49.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:49.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:49.99#ibcon#enter wrdev, iclass 29, count 2 2006.257.03:11:49.99#ibcon#first serial, iclass 29, count 2 2006.257.03:11:49.99#ibcon#enter sib2, iclass 29, count 2 2006.257.03:11:49.99#ibcon#flushed, iclass 29, count 2 2006.257.03:11:49.99#ibcon#about to write, iclass 29, count 2 2006.257.03:11:49.99#ibcon#wrote, iclass 29, count 2 2006.257.03:11:49.99#ibcon#about to read 3, iclass 29, count 2 2006.257.03:11:50.01#ibcon#read 3, iclass 29, count 2 2006.257.03:11:50.01#ibcon#about to read 4, iclass 29, count 2 2006.257.03:11:50.01#ibcon#read 4, iclass 29, count 2 2006.257.03:11:50.01#ibcon#about to read 5, iclass 29, count 2 2006.257.03:11:50.01#ibcon#read 5, iclass 29, count 2 2006.257.03:11:50.01#ibcon#about to read 6, iclass 29, count 2 2006.257.03:11:50.01#ibcon#read 6, iclass 29, count 2 2006.257.03:11:50.01#ibcon#end of sib2, iclass 29, count 2 2006.257.03:11:50.01#ibcon#*mode == 0, iclass 29, count 2 2006.257.03:11:50.01#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.03:11:50.01#ibcon#[25=AT07-04\r\n] 2006.257.03:11:50.01#ibcon#*before write, iclass 29, count 2 2006.257.03:11:50.01#ibcon#enter sib2, iclass 29, count 2 2006.257.03:11:50.01#ibcon#flushed, iclass 29, count 2 2006.257.03:11:50.01#ibcon#about to write, iclass 29, count 2 2006.257.03:11:50.01#ibcon#wrote, iclass 29, count 2 2006.257.03:11:50.01#ibcon#about to read 3, iclass 29, count 2 2006.257.03:11:50.04#ibcon#read 3, iclass 29, count 2 2006.257.03:11:50.04#ibcon#about to read 4, iclass 29, count 2 2006.257.03:11:50.04#ibcon#read 4, iclass 29, count 2 2006.257.03:11:50.04#ibcon#about to read 5, iclass 29, count 2 2006.257.03:11:50.04#ibcon#read 5, iclass 29, count 2 2006.257.03:11:50.04#ibcon#about to read 6, iclass 29, count 2 2006.257.03:11:50.04#ibcon#read 6, iclass 29, count 2 2006.257.03:11:50.04#ibcon#end of sib2, iclass 29, count 2 2006.257.03:11:50.04#ibcon#*after write, iclass 29, count 2 2006.257.03:11:50.04#ibcon#*before return 0, iclass 29, count 2 2006.257.03:11:50.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:50.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:50.04#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.03:11:50.04#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:50.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:50.16#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:50.16#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:50.16#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:11:50.16#ibcon#first serial, iclass 29, count 0 2006.257.03:11:50.16#ibcon#enter sib2, iclass 29, count 0 2006.257.03:11:50.16#ibcon#flushed, iclass 29, count 0 2006.257.03:11:50.16#ibcon#about to write, iclass 29, count 0 2006.257.03:11:50.16#ibcon#wrote, iclass 29, count 0 2006.257.03:11:50.16#ibcon#about to read 3, iclass 29, count 0 2006.257.03:11:50.18#ibcon#read 3, iclass 29, count 0 2006.257.03:11:50.18#ibcon#about to read 4, iclass 29, count 0 2006.257.03:11:50.18#ibcon#read 4, iclass 29, count 0 2006.257.03:11:50.18#ibcon#about to read 5, iclass 29, count 0 2006.257.03:11:50.18#ibcon#read 5, iclass 29, count 0 2006.257.03:11:50.18#ibcon#about to read 6, iclass 29, count 0 2006.257.03:11:50.18#ibcon#read 6, iclass 29, count 0 2006.257.03:11:50.18#ibcon#end of sib2, iclass 29, count 0 2006.257.03:11:50.18#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:11:50.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:11:50.18#ibcon#[25=USB\r\n] 2006.257.03:11:50.18#ibcon#*before write, iclass 29, count 0 2006.257.03:11:50.18#ibcon#enter sib2, iclass 29, count 0 2006.257.03:11:50.18#ibcon#flushed, iclass 29, count 0 2006.257.03:11:50.18#ibcon#about to write, iclass 29, count 0 2006.257.03:11:50.18#ibcon#wrote, iclass 29, count 0 2006.257.03:11:50.18#ibcon#about to read 3, iclass 29, count 0 2006.257.03:11:50.21#ibcon#read 3, iclass 29, count 0 2006.257.03:11:50.21#ibcon#about to read 4, iclass 29, count 0 2006.257.03:11:50.21#ibcon#read 4, iclass 29, count 0 2006.257.03:11:50.21#ibcon#about to read 5, iclass 29, count 0 2006.257.03:11:50.21#ibcon#read 5, iclass 29, count 0 2006.257.03:11:50.21#ibcon#about to read 6, iclass 29, count 0 2006.257.03:11:50.21#ibcon#read 6, iclass 29, count 0 2006.257.03:11:50.21#ibcon#end of sib2, iclass 29, count 0 2006.257.03:11:50.21#ibcon#*after write, iclass 29, count 0 2006.257.03:11:50.21#ibcon#*before return 0, iclass 29, count 0 2006.257.03:11:50.21#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:50.21#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:50.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:11:50.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:11:50.21$vck44/valo=8,884.99 2006.257.03:11:50.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.03:11:50.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.03:11:50.21#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:50.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:50.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:50.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:50.21#ibcon#enter wrdev, iclass 31, count 0 2006.257.03:11:50.21#ibcon#first serial, iclass 31, count 0 2006.257.03:11:50.21#ibcon#enter sib2, iclass 31, count 0 2006.257.03:11:50.21#ibcon#flushed, iclass 31, count 0 2006.257.03:11:50.21#ibcon#about to write, iclass 31, count 0 2006.257.03:11:50.21#ibcon#wrote, iclass 31, count 0 2006.257.03:11:50.21#ibcon#about to read 3, iclass 31, count 0 2006.257.03:11:50.23#ibcon#read 3, iclass 31, count 0 2006.257.03:11:50.23#ibcon#about to read 4, iclass 31, count 0 2006.257.03:11:50.23#ibcon#read 4, iclass 31, count 0 2006.257.03:11:50.23#ibcon#about to read 5, iclass 31, count 0 2006.257.03:11:50.23#ibcon#read 5, iclass 31, count 0 2006.257.03:11:50.23#ibcon#about to read 6, iclass 31, count 0 2006.257.03:11:50.23#ibcon#read 6, iclass 31, count 0 2006.257.03:11:50.23#ibcon#end of sib2, iclass 31, count 0 2006.257.03:11:50.23#ibcon#*mode == 0, iclass 31, count 0 2006.257.03:11:50.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.03:11:50.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:11:50.23#ibcon#*before write, iclass 31, count 0 2006.257.03:11:50.23#ibcon#enter sib2, iclass 31, count 0 2006.257.03:11:50.23#ibcon#flushed, iclass 31, count 0 2006.257.03:11:50.23#ibcon#about to write, iclass 31, count 0 2006.257.03:11:50.23#ibcon#wrote, iclass 31, count 0 2006.257.03:11:50.23#ibcon#about to read 3, iclass 31, count 0 2006.257.03:11:50.27#ibcon#read 3, iclass 31, count 0 2006.257.03:11:50.27#ibcon#about to read 4, iclass 31, count 0 2006.257.03:11:50.27#ibcon#read 4, iclass 31, count 0 2006.257.03:11:50.27#ibcon#about to read 5, iclass 31, count 0 2006.257.03:11:50.27#ibcon#read 5, iclass 31, count 0 2006.257.03:11:50.27#ibcon#about to read 6, iclass 31, count 0 2006.257.03:11:50.27#ibcon#read 6, iclass 31, count 0 2006.257.03:11:50.27#ibcon#end of sib2, iclass 31, count 0 2006.257.03:11:50.27#ibcon#*after write, iclass 31, count 0 2006.257.03:11:50.27#ibcon#*before return 0, iclass 31, count 0 2006.257.03:11:50.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:50.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:50.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.03:11:50.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.03:11:50.27$vck44/va=8,4 2006.257.03:11:50.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.03:11:50.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.03:11:50.27#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:50.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:11:50.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:11:50.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:11:50.33#ibcon#enter wrdev, iclass 33, count 2 2006.257.03:11:50.33#ibcon#first serial, iclass 33, count 2 2006.257.03:11:50.33#ibcon#enter sib2, iclass 33, count 2 2006.257.03:11:50.33#ibcon#flushed, iclass 33, count 2 2006.257.03:11:50.33#ibcon#about to write, iclass 33, count 2 2006.257.03:11:50.33#ibcon#wrote, iclass 33, count 2 2006.257.03:11:50.33#ibcon#about to read 3, iclass 33, count 2 2006.257.03:11:50.35#ibcon#read 3, iclass 33, count 2 2006.257.03:11:50.35#ibcon#about to read 4, iclass 33, count 2 2006.257.03:11:50.35#ibcon#read 4, iclass 33, count 2 2006.257.03:11:50.35#ibcon#about to read 5, iclass 33, count 2 2006.257.03:11:50.35#ibcon#read 5, iclass 33, count 2 2006.257.03:11:50.35#ibcon#about to read 6, iclass 33, count 2 2006.257.03:11:50.35#ibcon#read 6, iclass 33, count 2 2006.257.03:11:50.35#ibcon#end of sib2, iclass 33, count 2 2006.257.03:11:50.35#ibcon#*mode == 0, iclass 33, count 2 2006.257.03:11:50.35#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.03:11:50.35#ibcon#[25=AT08-04\r\n] 2006.257.03:11:50.35#ibcon#*before write, iclass 33, count 2 2006.257.03:11:50.35#ibcon#enter sib2, iclass 33, count 2 2006.257.03:11:50.35#ibcon#flushed, iclass 33, count 2 2006.257.03:11:50.35#ibcon#about to write, iclass 33, count 2 2006.257.03:11:50.35#ibcon#wrote, iclass 33, count 2 2006.257.03:11:50.35#ibcon#about to read 3, iclass 33, count 2 2006.257.03:11:50.38#ibcon#read 3, iclass 33, count 2 2006.257.03:11:50.38#ibcon#about to read 4, iclass 33, count 2 2006.257.03:11:50.38#ibcon#read 4, iclass 33, count 2 2006.257.03:11:50.38#ibcon#about to read 5, iclass 33, count 2 2006.257.03:11:50.38#ibcon#read 5, iclass 33, count 2 2006.257.03:11:50.38#ibcon#about to read 6, iclass 33, count 2 2006.257.03:11:50.38#ibcon#read 6, iclass 33, count 2 2006.257.03:11:50.38#ibcon#end of sib2, iclass 33, count 2 2006.257.03:11:50.38#ibcon#*after write, iclass 33, count 2 2006.257.03:11:50.38#ibcon#*before return 0, iclass 33, count 2 2006.257.03:11:50.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:11:50.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:11:50.38#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.03:11:50.38#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:50.38#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:11:50.50#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:11:50.50#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:11:50.50#ibcon#enter wrdev, iclass 33, count 0 2006.257.03:11:50.50#ibcon#first serial, iclass 33, count 0 2006.257.03:11:50.50#ibcon#enter sib2, iclass 33, count 0 2006.257.03:11:50.50#ibcon#flushed, iclass 33, count 0 2006.257.03:11:50.50#ibcon#about to write, iclass 33, count 0 2006.257.03:11:50.50#ibcon#wrote, iclass 33, count 0 2006.257.03:11:50.50#ibcon#about to read 3, iclass 33, count 0 2006.257.03:11:50.52#ibcon#read 3, iclass 33, count 0 2006.257.03:11:50.52#ibcon#about to read 4, iclass 33, count 0 2006.257.03:11:50.52#ibcon#read 4, iclass 33, count 0 2006.257.03:11:50.52#ibcon#about to read 5, iclass 33, count 0 2006.257.03:11:50.52#ibcon#read 5, iclass 33, count 0 2006.257.03:11:50.52#ibcon#about to read 6, iclass 33, count 0 2006.257.03:11:50.52#ibcon#read 6, iclass 33, count 0 2006.257.03:11:50.52#ibcon#end of sib2, iclass 33, count 0 2006.257.03:11:50.52#ibcon#*mode == 0, iclass 33, count 0 2006.257.03:11:50.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.03:11:50.52#ibcon#[25=USB\r\n] 2006.257.03:11:50.52#ibcon#*before write, iclass 33, count 0 2006.257.03:11:50.52#ibcon#enter sib2, iclass 33, count 0 2006.257.03:11:50.52#ibcon#flushed, iclass 33, count 0 2006.257.03:11:50.52#ibcon#about to write, iclass 33, count 0 2006.257.03:11:50.52#ibcon#wrote, iclass 33, count 0 2006.257.03:11:50.52#ibcon#about to read 3, iclass 33, count 0 2006.257.03:11:50.55#ibcon#read 3, iclass 33, count 0 2006.257.03:11:50.55#ibcon#about to read 4, iclass 33, count 0 2006.257.03:11:50.55#ibcon#read 4, iclass 33, count 0 2006.257.03:11:50.55#ibcon#about to read 5, iclass 33, count 0 2006.257.03:11:50.55#ibcon#read 5, iclass 33, count 0 2006.257.03:11:50.55#ibcon#about to read 6, iclass 33, count 0 2006.257.03:11:50.55#ibcon#read 6, iclass 33, count 0 2006.257.03:11:50.55#ibcon#end of sib2, iclass 33, count 0 2006.257.03:11:50.55#ibcon#*after write, iclass 33, count 0 2006.257.03:11:50.55#ibcon#*before return 0, iclass 33, count 0 2006.257.03:11:50.55#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:11:50.55#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:11:50.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.03:11:50.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.03:11:50.55$vck44/vblo=1,629.99 2006.257.03:11:50.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.03:11:50.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.03:11:50.55#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:50.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:11:50.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:11:50.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:11:50.55#ibcon#enter wrdev, iclass 35, count 0 2006.257.03:11:50.55#ibcon#first serial, iclass 35, count 0 2006.257.03:11:50.55#ibcon#enter sib2, iclass 35, count 0 2006.257.03:11:50.55#ibcon#flushed, iclass 35, count 0 2006.257.03:11:50.55#ibcon#about to write, iclass 35, count 0 2006.257.03:11:50.55#ibcon#wrote, iclass 35, count 0 2006.257.03:11:50.55#ibcon#about to read 3, iclass 35, count 0 2006.257.03:11:50.57#ibcon#read 3, iclass 35, count 0 2006.257.03:11:50.57#ibcon#about to read 4, iclass 35, count 0 2006.257.03:11:50.57#ibcon#read 4, iclass 35, count 0 2006.257.03:11:50.57#ibcon#about to read 5, iclass 35, count 0 2006.257.03:11:50.57#ibcon#read 5, iclass 35, count 0 2006.257.03:11:50.57#ibcon#about to read 6, iclass 35, count 0 2006.257.03:11:50.57#ibcon#read 6, iclass 35, count 0 2006.257.03:11:50.57#ibcon#end of sib2, iclass 35, count 0 2006.257.03:11:50.57#ibcon#*mode == 0, iclass 35, count 0 2006.257.03:11:50.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.03:11:50.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:11:50.57#ibcon#*before write, iclass 35, count 0 2006.257.03:11:50.57#ibcon#enter sib2, iclass 35, count 0 2006.257.03:11:50.57#ibcon#flushed, iclass 35, count 0 2006.257.03:11:50.57#ibcon#about to write, iclass 35, count 0 2006.257.03:11:50.57#ibcon#wrote, iclass 35, count 0 2006.257.03:11:50.57#ibcon#about to read 3, iclass 35, count 0 2006.257.03:11:50.61#ibcon#read 3, iclass 35, count 0 2006.257.03:11:50.61#ibcon#about to read 4, iclass 35, count 0 2006.257.03:11:50.61#ibcon#read 4, iclass 35, count 0 2006.257.03:11:50.61#ibcon#about to read 5, iclass 35, count 0 2006.257.03:11:50.61#ibcon#read 5, iclass 35, count 0 2006.257.03:11:50.61#ibcon#about to read 6, iclass 35, count 0 2006.257.03:11:50.61#ibcon#read 6, iclass 35, count 0 2006.257.03:11:50.61#ibcon#end of sib2, iclass 35, count 0 2006.257.03:11:50.61#ibcon#*after write, iclass 35, count 0 2006.257.03:11:50.61#ibcon#*before return 0, iclass 35, count 0 2006.257.03:11:50.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:11:50.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:11:50.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.03:11:50.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.03:11:50.61$vck44/vb=1,4 2006.257.03:11:50.61#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.03:11:50.61#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.03:11:50.61#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:50.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:11:50.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:11:50.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:11:50.61#ibcon#enter wrdev, iclass 37, count 2 2006.257.03:11:50.61#ibcon#first serial, iclass 37, count 2 2006.257.03:11:50.61#ibcon#enter sib2, iclass 37, count 2 2006.257.03:11:50.61#ibcon#flushed, iclass 37, count 2 2006.257.03:11:50.61#ibcon#about to write, iclass 37, count 2 2006.257.03:11:50.61#ibcon#wrote, iclass 37, count 2 2006.257.03:11:50.61#ibcon#about to read 3, iclass 37, count 2 2006.257.03:11:50.63#ibcon#read 3, iclass 37, count 2 2006.257.03:11:50.63#ibcon#about to read 4, iclass 37, count 2 2006.257.03:11:50.63#ibcon#read 4, iclass 37, count 2 2006.257.03:11:50.63#ibcon#about to read 5, iclass 37, count 2 2006.257.03:11:50.63#ibcon#read 5, iclass 37, count 2 2006.257.03:11:50.63#ibcon#about to read 6, iclass 37, count 2 2006.257.03:11:50.63#ibcon#read 6, iclass 37, count 2 2006.257.03:11:50.63#ibcon#end of sib2, iclass 37, count 2 2006.257.03:11:50.63#ibcon#*mode == 0, iclass 37, count 2 2006.257.03:11:50.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.03:11:50.63#ibcon#[27=AT01-04\r\n] 2006.257.03:11:50.63#ibcon#*before write, iclass 37, count 2 2006.257.03:11:50.63#ibcon#enter sib2, iclass 37, count 2 2006.257.03:11:50.63#ibcon#flushed, iclass 37, count 2 2006.257.03:11:50.63#ibcon#about to write, iclass 37, count 2 2006.257.03:11:50.63#ibcon#wrote, iclass 37, count 2 2006.257.03:11:50.63#ibcon#about to read 3, iclass 37, count 2 2006.257.03:11:50.66#ibcon#read 3, iclass 37, count 2 2006.257.03:11:50.66#ibcon#about to read 4, iclass 37, count 2 2006.257.03:11:50.66#ibcon#read 4, iclass 37, count 2 2006.257.03:11:50.66#ibcon#about to read 5, iclass 37, count 2 2006.257.03:11:50.66#ibcon#read 5, iclass 37, count 2 2006.257.03:11:50.66#ibcon#about to read 6, iclass 37, count 2 2006.257.03:11:50.66#ibcon#read 6, iclass 37, count 2 2006.257.03:11:50.66#ibcon#end of sib2, iclass 37, count 2 2006.257.03:11:50.66#ibcon#*after write, iclass 37, count 2 2006.257.03:11:50.66#ibcon#*before return 0, iclass 37, count 2 2006.257.03:11:50.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:11:50.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:11:50.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.03:11:50.66#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:50.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:11:50.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:11:50.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:11:50.78#ibcon#enter wrdev, iclass 37, count 0 2006.257.03:11:50.78#ibcon#first serial, iclass 37, count 0 2006.257.03:11:50.78#ibcon#enter sib2, iclass 37, count 0 2006.257.03:11:50.78#ibcon#flushed, iclass 37, count 0 2006.257.03:11:50.78#ibcon#about to write, iclass 37, count 0 2006.257.03:11:50.78#ibcon#wrote, iclass 37, count 0 2006.257.03:11:50.78#ibcon#about to read 3, iclass 37, count 0 2006.257.03:11:50.80#ibcon#read 3, iclass 37, count 0 2006.257.03:11:50.80#ibcon#about to read 4, iclass 37, count 0 2006.257.03:11:50.80#ibcon#read 4, iclass 37, count 0 2006.257.03:11:50.80#ibcon#about to read 5, iclass 37, count 0 2006.257.03:11:50.80#ibcon#read 5, iclass 37, count 0 2006.257.03:11:50.80#ibcon#about to read 6, iclass 37, count 0 2006.257.03:11:50.80#ibcon#read 6, iclass 37, count 0 2006.257.03:11:50.80#ibcon#end of sib2, iclass 37, count 0 2006.257.03:11:50.80#ibcon#*mode == 0, iclass 37, count 0 2006.257.03:11:50.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.03:11:50.80#ibcon#[27=USB\r\n] 2006.257.03:11:50.80#ibcon#*before write, iclass 37, count 0 2006.257.03:11:50.80#ibcon#enter sib2, iclass 37, count 0 2006.257.03:11:50.80#ibcon#flushed, iclass 37, count 0 2006.257.03:11:50.80#ibcon#about to write, iclass 37, count 0 2006.257.03:11:50.80#ibcon#wrote, iclass 37, count 0 2006.257.03:11:50.80#ibcon#about to read 3, iclass 37, count 0 2006.257.03:11:50.83#ibcon#read 3, iclass 37, count 0 2006.257.03:11:50.83#ibcon#about to read 4, iclass 37, count 0 2006.257.03:11:50.83#ibcon#read 4, iclass 37, count 0 2006.257.03:11:50.83#ibcon#about to read 5, iclass 37, count 0 2006.257.03:11:50.83#ibcon#read 5, iclass 37, count 0 2006.257.03:11:50.83#ibcon#about to read 6, iclass 37, count 0 2006.257.03:11:50.83#ibcon#read 6, iclass 37, count 0 2006.257.03:11:50.83#ibcon#end of sib2, iclass 37, count 0 2006.257.03:11:50.83#ibcon#*after write, iclass 37, count 0 2006.257.03:11:50.83#ibcon#*before return 0, iclass 37, count 0 2006.257.03:11:50.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:11:50.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:11:50.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.03:11:50.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.03:11:50.83$vck44/vblo=2,634.99 2006.257.03:11:50.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.03:11:50.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.03:11:50.83#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:50.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:50.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:50.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:50.83#ibcon#enter wrdev, iclass 39, count 0 2006.257.03:11:50.83#ibcon#first serial, iclass 39, count 0 2006.257.03:11:50.83#ibcon#enter sib2, iclass 39, count 0 2006.257.03:11:50.83#ibcon#flushed, iclass 39, count 0 2006.257.03:11:50.83#ibcon#about to write, iclass 39, count 0 2006.257.03:11:50.83#ibcon#wrote, iclass 39, count 0 2006.257.03:11:50.83#ibcon#about to read 3, iclass 39, count 0 2006.257.03:11:50.85#ibcon#read 3, iclass 39, count 0 2006.257.03:11:50.85#ibcon#about to read 4, iclass 39, count 0 2006.257.03:11:50.85#ibcon#read 4, iclass 39, count 0 2006.257.03:11:50.85#ibcon#about to read 5, iclass 39, count 0 2006.257.03:11:50.85#ibcon#read 5, iclass 39, count 0 2006.257.03:11:50.85#ibcon#about to read 6, iclass 39, count 0 2006.257.03:11:50.85#ibcon#read 6, iclass 39, count 0 2006.257.03:11:50.85#ibcon#end of sib2, iclass 39, count 0 2006.257.03:11:50.85#ibcon#*mode == 0, iclass 39, count 0 2006.257.03:11:50.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.03:11:50.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:11:50.85#ibcon#*before write, iclass 39, count 0 2006.257.03:11:50.85#ibcon#enter sib2, iclass 39, count 0 2006.257.03:11:50.85#ibcon#flushed, iclass 39, count 0 2006.257.03:11:50.85#ibcon#about to write, iclass 39, count 0 2006.257.03:11:50.85#ibcon#wrote, iclass 39, count 0 2006.257.03:11:50.85#ibcon#about to read 3, iclass 39, count 0 2006.257.03:11:50.89#ibcon#read 3, iclass 39, count 0 2006.257.03:11:50.89#ibcon#about to read 4, iclass 39, count 0 2006.257.03:11:50.89#ibcon#read 4, iclass 39, count 0 2006.257.03:11:50.89#ibcon#about to read 5, iclass 39, count 0 2006.257.03:11:50.89#ibcon#read 5, iclass 39, count 0 2006.257.03:11:50.89#ibcon#about to read 6, iclass 39, count 0 2006.257.03:11:50.89#ibcon#read 6, iclass 39, count 0 2006.257.03:11:50.89#ibcon#end of sib2, iclass 39, count 0 2006.257.03:11:50.89#ibcon#*after write, iclass 39, count 0 2006.257.03:11:50.89#ibcon#*before return 0, iclass 39, count 0 2006.257.03:11:50.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:50.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:11:50.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.03:11:50.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.03:11:50.89$vck44/vb=2,5 2006.257.03:11:50.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.03:11:50.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.03:11:50.89#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:50.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:50.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:50.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:50.95#ibcon#enter wrdev, iclass 3, count 2 2006.257.03:11:50.95#ibcon#first serial, iclass 3, count 2 2006.257.03:11:50.95#ibcon#enter sib2, iclass 3, count 2 2006.257.03:11:50.95#ibcon#flushed, iclass 3, count 2 2006.257.03:11:50.95#ibcon#about to write, iclass 3, count 2 2006.257.03:11:50.95#ibcon#wrote, iclass 3, count 2 2006.257.03:11:50.95#ibcon#about to read 3, iclass 3, count 2 2006.257.03:11:50.97#ibcon#read 3, iclass 3, count 2 2006.257.03:11:50.97#ibcon#about to read 4, iclass 3, count 2 2006.257.03:11:50.97#ibcon#read 4, iclass 3, count 2 2006.257.03:11:50.97#ibcon#about to read 5, iclass 3, count 2 2006.257.03:11:50.97#ibcon#read 5, iclass 3, count 2 2006.257.03:11:50.97#ibcon#about to read 6, iclass 3, count 2 2006.257.03:11:50.97#ibcon#read 6, iclass 3, count 2 2006.257.03:11:50.97#ibcon#end of sib2, iclass 3, count 2 2006.257.03:11:50.97#ibcon#*mode == 0, iclass 3, count 2 2006.257.03:11:50.97#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.03:11:50.97#ibcon#[27=AT02-05\r\n] 2006.257.03:11:50.97#ibcon#*before write, iclass 3, count 2 2006.257.03:11:50.97#ibcon#enter sib2, iclass 3, count 2 2006.257.03:11:50.97#ibcon#flushed, iclass 3, count 2 2006.257.03:11:50.97#ibcon#about to write, iclass 3, count 2 2006.257.03:11:50.97#ibcon#wrote, iclass 3, count 2 2006.257.03:11:50.97#ibcon#about to read 3, iclass 3, count 2 2006.257.03:11:51.00#ibcon#read 3, iclass 3, count 2 2006.257.03:11:51.00#ibcon#about to read 4, iclass 3, count 2 2006.257.03:11:51.00#ibcon#read 4, iclass 3, count 2 2006.257.03:11:51.00#ibcon#about to read 5, iclass 3, count 2 2006.257.03:11:51.00#ibcon#read 5, iclass 3, count 2 2006.257.03:11:51.00#ibcon#about to read 6, iclass 3, count 2 2006.257.03:11:51.00#ibcon#read 6, iclass 3, count 2 2006.257.03:11:51.00#ibcon#end of sib2, iclass 3, count 2 2006.257.03:11:51.00#ibcon#*after write, iclass 3, count 2 2006.257.03:11:51.00#ibcon#*before return 0, iclass 3, count 2 2006.257.03:11:51.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:51.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:11:51.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.03:11:51.00#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:51.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:51.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:51.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:51.12#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:11:51.12#ibcon#first serial, iclass 3, count 0 2006.257.03:11:51.12#ibcon#enter sib2, iclass 3, count 0 2006.257.03:11:51.12#ibcon#flushed, iclass 3, count 0 2006.257.03:11:51.12#ibcon#about to write, iclass 3, count 0 2006.257.03:11:51.12#ibcon#wrote, iclass 3, count 0 2006.257.03:11:51.12#ibcon#about to read 3, iclass 3, count 0 2006.257.03:11:51.14#ibcon#read 3, iclass 3, count 0 2006.257.03:11:51.14#ibcon#about to read 4, iclass 3, count 0 2006.257.03:11:51.14#ibcon#read 4, iclass 3, count 0 2006.257.03:11:51.14#ibcon#about to read 5, iclass 3, count 0 2006.257.03:11:51.14#ibcon#read 5, iclass 3, count 0 2006.257.03:11:51.14#ibcon#about to read 6, iclass 3, count 0 2006.257.03:11:51.14#ibcon#read 6, iclass 3, count 0 2006.257.03:11:51.14#ibcon#end of sib2, iclass 3, count 0 2006.257.03:11:51.14#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:11:51.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:11:51.14#ibcon#[27=USB\r\n] 2006.257.03:11:51.14#ibcon#*before write, iclass 3, count 0 2006.257.03:11:51.14#ibcon#enter sib2, iclass 3, count 0 2006.257.03:11:51.14#ibcon#flushed, iclass 3, count 0 2006.257.03:11:51.14#ibcon#about to write, iclass 3, count 0 2006.257.03:11:51.14#ibcon#wrote, iclass 3, count 0 2006.257.03:11:51.14#ibcon#about to read 3, iclass 3, count 0 2006.257.03:11:51.17#ibcon#read 3, iclass 3, count 0 2006.257.03:11:51.17#ibcon#about to read 4, iclass 3, count 0 2006.257.03:11:51.17#ibcon#read 4, iclass 3, count 0 2006.257.03:11:51.17#ibcon#about to read 5, iclass 3, count 0 2006.257.03:11:51.17#ibcon#read 5, iclass 3, count 0 2006.257.03:11:51.17#ibcon#about to read 6, iclass 3, count 0 2006.257.03:11:51.17#ibcon#read 6, iclass 3, count 0 2006.257.03:11:51.17#ibcon#end of sib2, iclass 3, count 0 2006.257.03:11:51.17#ibcon#*after write, iclass 3, count 0 2006.257.03:11:51.17#ibcon#*before return 0, iclass 3, count 0 2006.257.03:11:51.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:51.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:11:51.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:11:51.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:11:51.17$vck44/vblo=3,649.99 2006.257.03:11:51.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.03:11:51.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.03:11:51.17#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:51.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:51.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:51.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:51.17#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:11:51.17#ibcon#first serial, iclass 5, count 0 2006.257.03:11:51.17#ibcon#enter sib2, iclass 5, count 0 2006.257.03:11:51.17#ibcon#flushed, iclass 5, count 0 2006.257.03:11:51.17#ibcon#about to write, iclass 5, count 0 2006.257.03:11:51.17#ibcon#wrote, iclass 5, count 0 2006.257.03:11:51.17#ibcon#about to read 3, iclass 5, count 0 2006.257.03:11:51.19#ibcon#read 3, iclass 5, count 0 2006.257.03:11:51.19#ibcon#about to read 4, iclass 5, count 0 2006.257.03:11:51.19#ibcon#read 4, iclass 5, count 0 2006.257.03:11:51.19#ibcon#about to read 5, iclass 5, count 0 2006.257.03:11:51.19#ibcon#read 5, iclass 5, count 0 2006.257.03:11:51.19#ibcon#about to read 6, iclass 5, count 0 2006.257.03:11:51.19#ibcon#read 6, iclass 5, count 0 2006.257.03:11:51.19#ibcon#end of sib2, iclass 5, count 0 2006.257.03:11:51.19#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:11:51.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:11:51.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:11:51.19#ibcon#*before write, iclass 5, count 0 2006.257.03:11:51.19#ibcon#enter sib2, iclass 5, count 0 2006.257.03:11:51.19#ibcon#flushed, iclass 5, count 0 2006.257.03:11:51.19#ibcon#about to write, iclass 5, count 0 2006.257.03:11:51.19#ibcon#wrote, iclass 5, count 0 2006.257.03:11:51.19#ibcon#about to read 3, iclass 5, count 0 2006.257.03:11:51.23#ibcon#read 3, iclass 5, count 0 2006.257.03:11:51.23#ibcon#about to read 4, iclass 5, count 0 2006.257.03:11:51.23#ibcon#read 4, iclass 5, count 0 2006.257.03:11:51.23#ibcon#about to read 5, iclass 5, count 0 2006.257.03:11:51.23#ibcon#read 5, iclass 5, count 0 2006.257.03:11:51.23#ibcon#about to read 6, iclass 5, count 0 2006.257.03:11:51.23#ibcon#read 6, iclass 5, count 0 2006.257.03:11:51.23#ibcon#end of sib2, iclass 5, count 0 2006.257.03:11:51.23#ibcon#*after write, iclass 5, count 0 2006.257.03:11:51.23#ibcon#*before return 0, iclass 5, count 0 2006.257.03:11:51.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:51.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:11:51.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:11:51.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:11:51.23$vck44/vb=3,4 2006.257.03:11:51.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.03:11:51.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.03:11:51.23#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:51.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:51.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:51.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:51.29#ibcon#enter wrdev, iclass 7, count 2 2006.257.03:11:51.29#ibcon#first serial, iclass 7, count 2 2006.257.03:11:51.29#ibcon#enter sib2, iclass 7, count 2 2006.257.03:11:51.29#ibcon#flushed, iclass 7, count 2 2006.257.03:11:51.29#ibcon#about to write, iclass 7, count 2 2006.257.03:11:51.29#ibcon#wrote, iclass 7, count 2 2006.257.03:11:51.29#ibcon#about to read 3, iclass 7, count 2 2006.257.03:11:51.31#ibcon#read 3, iclass 7, count 2 2006.257.03:11:51.31#ibcon#about to read 4, iclass 7, count 2 2006.257.03:11:51.31#ibcon#read 4, iclass 7, count 2 2006.257.03:11:51.31#ibcon#about to read 5, iclass 7, count 2 2006.257.03:11:51.31#ibcon#read 5, iclass 7, count 2 2006.257.03:11:51.31#ibcon#about to read 6, iclass 7, count 2 2006.257.03:11:51.31#ibcon#read 6, iclass 7, count 2 2006.257.03:11:51.31#ibcon#end of sib2, iclass 7, count 2 2006.257.03:11:51.31#ibcon#*mode == 0, iclass 7, count 2 2006.257.03:11:51.31#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.03:11:51.31#ibcon#[27=AT03-04\r\n] 2006.257.03:11:51.31#ibcon#*before write, iclass 7, count 2 2006.257.03:11:51.31#ibcon#enter sib2, iclass 7, count 2 2006.257.03:11:51.31#ibcon#flushed, iclass 7, count 2 2006.257.03:11:51.31#ibcon#about to write, iclass 7, count 2 2006.257.03:11:51.31#ibcon#wrote, iclass 7, count 2 2006.257.03:11:51.31#ibcon#about to read 3, iclass 7, count 2 2006.257.03:11:51.34#ibcon#read 3, iclass 7, count 2 2006.257.03:11:51.34#ibcon#about to read 4, iclass 7, count 2 2006.257.03:11:51.34#ibcon#read 4, iclass 7, count 2 2006.257.03:11:51.34#ibcon#about to read 5, iclass 7, count 2 2006.257.03:11:51.34#ibcon#read 5, iclass 7, count 2 2006.257.03:11:51.34#ibcon#about to read 6, iclass 7, count 2 2006.257.03:11:51.34#ibcon#read 6, iclass 7, count 2 2006.257.03:11:51.34#ibcon#end of sib2, iclass 7, count 2 2006.257.03:11:51.34#ibcon#*after write, iclass 7, count 2 2006.257.03:11:51.34#ibcon#*before return 0, iclass 7, count 2 2006.257.03:11:51.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:51.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:11:51.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.03:11:51.34#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:51.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:51.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:51.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:51.46#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:11:51.46#ibcon#first serial, iclass 7, count 0 2006.257.03:11:51.46#ibcon#enter sib2, iclass 7, count 0 2006.257.03:11:51.46#ibcon#flushed, iclass 7, count 0 2006.257.03:11:51.46#ibcon#about to write, iclass 7, count 0 2006.257.03:11:51.46#ibcon#wrote, iclass 7, count 0 2006.257.03:11:51.46#ibcon#about to read 3, iclass 7, count 0 2006.257.03:11:51.48#ibcon#read 3, iclass 7, count 0 2006.257.03:11:51.48#ibcon#about to read 4, iclass 7, count 0 2006.257.03:11:51.48#ibcon#read 4, iclass 7, count 0 2006.257.03:11:51.48#ibcon#about to read 5, iclass 7, count 0 2006.257.03:11:51.48#ibcon#read 5, iclass 7, count 0 2006.257.03:11:51.48#ibcon#about to read 6, iclass 7, count 0 2006.257.03:11:51.48#ibcon#read 6, iclass 7, count 0 2006.257.03:11:51.48#ibcon#end of sib2, iclass 7, count 0 2006.257.03:11:51.48#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:11:51.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:11:51.48#ibcon#[27=USB\r\n] 2006.257.03:11:51.48#ibcon#*before write, iclass 7, count 0 2006.257.03:11:51.48#ibcon#enter sib2, iclass 7, count 0 2006.257.03:11:51.48#ibcon#flushed, iclass 7, count 0 2006.257.03:11:51.48#ibcon#about to write, iclass 7, count 0 2006.257.03:11:51.48#ibcon#wrote, iclass 7, count 0 2006.257.03:11:51.48#ibcon#about to read 3, iclass 7, count 0 2006.257.03:11:51.51#ibcon#read 3, iclass 7, count 0 2006.257.03:11:51.51#ibcon#about to read 4, iclass 7, count 0 2006.257.03:11:51.51#ibcon#read 4, iclass 7, count 0 2006.257.03:11:51.51#ibcon#about to read 5, iclass 7, count 0 2006.257.03:11:51.51#ibcon#read 5, iclass 7, count 0 2006.257.03:11:51.51#ibcon#about to read 6, iclass 7, count 0 2006.257.03:11:51.51#ibcon#read 6, iclass 7, count 0 2006.257.03:11:51.51#ibcon#end of sib2, iclass 7, count 0 2006.257.03:11:51.51#ibcon#*after write, iclass 7, count 0 2006.257.03:11:51.51#ibcon#*before return 0, iclass 7, count 0 2006.257.03:11:51.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:51.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:11:51.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:11:51.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:11:51.51$vck44/vblo=4,679.99 2006.257.03:11:51.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.03:11:51.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.03:11:51.51#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:51.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:51.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:51.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:51.51#ibcon#enter wrdev, iclass 11, count 0 2006.257.03:11:51.51#ibcon#first serial, iclass 11, count 0 2006.257.03:11:51.51#ibcon#enter sib2, iclass 11, count 0 2006.257.03:11:51.51#ibcon#flushed, iclass 11, count 0 2006.257.03:11:51.51#ibcon#about to write, iclass 11, count 0 2006.257.03:11:51.51#ibcon#wrote, iclass 11, count 0 2006.257.03:11:51.51#ibcon#about to read 3, iclass 11, count 0 2006.257.03:11:51.53#ibcon#read 3, iclass 11, count 0 2006.257.03:11:51.53#ibcon#about to read 4, iclass 11, count 0 2006.257.03:11:51.53#ibcon#read 4, iclass 11, count 0 2006.257.03:11:51.53#ibcon#about to read 5, iclass 11, count 0 2006.257.03:11:51.53#ibcon#read 5, iclass 11, count 0 2006.257.03:11:51.53#ibcon#about to read 6, iclass 11, count 0 2006.257.03:11:51.53#ibcon#read 6, iclass 11, count 0 2006.257.03:11:51.53#ibcon#end of sib2, iclass 11, count 0 2006.257.03:11:51.53#ibcon#*mode == 0, iclass 11, count 0 2006.257.03:11:51.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.03:11:51.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:11:51.53#ibcon#*before write, iclass 11, count 0 2006.257.03:11:51.53#ibcon#enter sib2, iclass 11, count 0 2006.257.03:11:51.53#ibcon#flushed, iclass 11, count 0 2006.257.03:11:51.53#ibcon#about to write, iclass 11, count 0 2006.257.03:11:51.53#ibcon#wrote, iclass 11, count 0 2006.257.03:11:51.53#ibcon#about to read 3, iclass 11, count 0 2006.257.03:11:51.57#ibcon#read 3, iclass 11, count 0 2006.257.03:11:51.57#ibcon#about to read 4, iclass 11, count 0 2006.257.03:11:51.57#ibcon#read 4, iclass 11, count 0 2006.257.03:11:51.57#ibcon#about to read 5, iclass 11, count 0 2006.257.03:11:51.57#ibcon#read 5, iclass 11, count 0 2006.257.03:11:51.57#ibcon#about to read 6, iclass 11, count 0 2006.257.03:11:51.57#ibcon#read 6, iclass 11, count 0 2006.257.03:11:51.57#ibcon#end of sib2, iclass 11, count 0 2006.257.03:11:51.57#ibcon#*after write, iclass 11, count 0 2006.257.03:11:51.57#ibcon#*before return 0, iclass 11, count 0 2006.257.03:11:51.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:51.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:11:51.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.03:11:51.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.03:11:51.57$vck44/vb=4,5 2006.257.03:11:51.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.03:11:51.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.03:11:51.57#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:51.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:51.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:51.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:51.63#ibcon#enter wrdev, iclass 13, count 2 2006.257.03:11:51.63#ibcon#first serial, iclass 13, count 2 2006.257.03:11:51.63#ibcon#enter sib2, iclass 13, count 2 2006.257.03:11:51.63#ibcon#flushed, iclass 13, count 2 2006.257.03:11:51.63#ibcon#about to write, iclass 13, count 2 2006.257.03:11:51.63#ibcon#wrote, iclass 13, count 2 2006.257.03:11:51.63#ibcon#about to read 3, iclass 13, count 2 2006.257.03:11:51.65#ibcon#read 3, iclass 13, count 2 2006.257.03:11:51.65#ibcon#about to read 4, iclass 13, count 2 2006.257.03:11:51.65#ibcon#read 4, iclass 13, count 2 2006.257.03:11:51.65#ibcon#about to read 5, iclass 13, count 2 2006.257.03:11:51.65#ibcon#read 5, iclass 13, count 2 2006.257.03:11:51.65#ibcon#about to read 6, iclass 13, count 2 2006.257.03:11:51.65#ibcon#read 6, iclass 13, count 2 2006.257.03:11:51.65#ibcon#end of sib2, iclass 13, count 2 2006.257.03:11:51.65#ibcon#*mode == 0, iclass 13, count 2 2006.257.03:11:51.65#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.03:11:51.65#ibcon#[27=AT04-05\r\n] 2006.257.03:11:51.65#ibcon#*before write, iclass 13, count 2 2006.257.03:11:51.65#ibcon#enter sib2, iclass 13, count 2 2006.257.03:11:51.65#ibcon#flushed, iclass 13, count 2 2006.257.03:11:51.65#ibcon#about to write, iclass 13, count 2 2006.257.03:11:51.65#ibcon#wrote, iclass 13, count 2 2006.257.03:11:51.65#ibcon#about to read 3, iclass 13, count 2 2006.257.03:11:51.69#ibcon#read 3, iclass 13, count 2 2006.257.03:11:51.69#ibcon#about to read 4, iclass 13, count 2 2006.257.03:11:51.69#ibcon#read 4, iclass 13, count 2 2006.257.03:11:51.69#ibcon#about to read 5, iclass 13, count 2 2006.257.03:11:51.69#ibcon#read 5, iclass 13, count 2 2006.257.03:11:51.69#ibcon#about to read 6, iclass 13, count 2 2006.257.03:11:51.69#ibcon#read 6, iclass 13, count 2 2006.257.03:11:51.69#ibcon#end of sib2, iclass 13, count 2 2006.257.03:11:51.69#ibcon#*after write, iclass 13, count 2 2006.257.03:11:51.69#ibcon#*before return 0, iclass 13, count 2 2006.257.03:11:51.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:51.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:11:51.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.03:11:51.69#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:51.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:51.80#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:51.80#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:51.80#ibcon#enter wrdev, iclass 13, count 0 2006.257.03:11:51.80#ibcon#first serial, iclass 13, count 0 2006.257.03:11:51.80#ibcon#enter sib2, iclass 13, count 0 2006.257.03:11:51.80#ibcon#flushed, iclass 13, count 0 2006.257.03:11:51.80#ibcon#about to write, iclass 13, count 0 2006.257.03:11:51.80#ibcon#wrote, iclass 13, count 0 2006.257.03:11:51.80#ibcon#about to read 3, iclass 13, count 0 2006.257.03:11:51.82#ibcon#read 3, iclass 13, count 0 2006.257.03:11:51.82#ibcon#about to read 4, iclass 13, count 0 2006.257.03:11:51.82#ibcon#read 4, iclass 13, count 0 2006.257.03:11:51.82#ibcon#about to read 5, iclass 13, count 0 2006.257.03:11:51.82#ibcon#read 5, iclass 13, count 0 2006.257.03:11:51.82#ibcon#about to read 6, iclass 13, count 0 2006.257.03:11:51.82#ibcon#read 6, iclass 13, count 0 2006.257.03:11:51.82#ibcon#end of sib2, iclass 13, count 0 2006.257.03:11:51.82#ibcon#*mode == 0, iclass 13, count 0 2006.257.03:11:51.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.03:11:51.82#ibcon#[27=USB\r\n] 2006.257.03:11:51.82#ibcon#*before write, iclass 13, count 0 2006.257.03:11:51.82#ibcon#enter sib2, iclass 13, count 0 2006.257.03:11:51.82#ibcon#flushed, iclass 13, count 0 2006.257.03:11:51.82#ibcon#about to write, iclass 13, count 0 2006.257.03:11:51.82#ibcon#wrote, iclass 13, count 0 2006.257.03:11:51.82#ibcon#about to read 3, iclass 13, count 0 2006.257.03:11:51.85#ibcon#read 3, iclass 13, count 0 2006.257.03:11:51.85#ibcon#about to read 4, iclass 13, count 0 2006.257.03:11:51.85#ibcon#read 4, iclass 13, count 0 2006.257.03:11:51.85#ibcon#about to read 5, iclass 13, count 0 2006.257.03:11:51.85#ibcon#read 5, iclass 13, count 0 2006.257.03:11:51.85#ibcon#about to read 6, iclass 13, count 0 2006.257.03:11:51.85#ibcon#read 6, iclass 13, count 0 2006.257.03:11:51.85#ibcon#end of sib2, iclass 13, count 0 2006.257.03:11:51.85#ibcon#*after write, iclass 13, count 0 2006.257.03:11:51.85#ibcon#*before return 0, iclass 13, count 0 2006.257.03:11:51.85#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:51.85#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:11:51.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.03:11:51.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.03:11:51.85$vck44/vblo=5,709.99 2006.257.03:11:51.85#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.03:11:51.85#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.03:11:51.85#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:51.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:51.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:51.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:51.85#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:11:51.85#ibcon#first serial, iclass 15, count 0 2006.257.03:11:51.85#ibcon#enter sib2, iclass 15, count 0 2006.257.03:11:51.85#ibcon#flushed, iclass 15, count 0 2006.257.03:11:51.85#ibcon#about to write, iclass 15, count 0 2006.257.03:11:51.85#ibcon#wrote, iclass 15, count 0 2006.257.03:11:51.85#ibcon#about to read 3, iclass 15, count 0 2006.257.03:11:51.87#ibcon#read 3, iclass 15, count 0 2006.257.03:11:51.87#ibcon#about to read 4, iclass 15, count 0 2006.257.03:11:51.87#ibcon#read 4, iclass 15, count 0 2006.257.03:11:51.87#ibcon#about to read 5, iclass 15, count 0 2006.257.03:11:51.87#ibcon#read 5, iclass 15, count 0 2006.257.03:11:51.87#ibcon#about to read 6, iclass 15, count 0 2006.257.03:11:51.87#ibcon#read 6, iclass 15, count 0 2006.257.03:11:51.87#ibcon#end of sib2, iclass 15, count 0 2006.257.03:11:51.87#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:11:51.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:11:51.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:11:51.87#ibcon#*before write, iclass 15, count 0 2006.257.03:11:51.87#ibcon#enter sib2, iclass 15, count 0 2006.257.03:11:51.87#ibcon#flushed, iclass 15, count 0 2006.257.03:11:51.87#ibcon#about to write, iclass 15, count 0 2006.257.03:11:51.87#ibcon#wrote, iclass 15, count 0 2006.257.03:11:51.87#ibcon#about to read 3, iclass 15, count 0 2006.257.03:11:51.91#ibcon#read 3, iclass 15, count 0 2006.257.03:11:51.91#ibcon#about to read 4, iclass 15, count 0 2006.257.03:11:51.91#ibcon#read 4, iclass 15, count 0 2006.257.03:11:51.91#ibcon#about to read 5, iclass 15, count 0 2006.257.03:11:51.91#ibcon#read 5, iclass 15, count 0 2006.257.03:11:51.91#ibcon#about to read 6, iclass 15, count 0 2006.257.03:11:51.91#ibcon#read 6, iclass 15, count 0 2006.257.03:11:51.91#ibcon#end of sib2, iclass 15, count 0 2006.257.03:11:51.91#ibcon#*after write, iclass 15, count 0 2006.257.03:11:51.91#ibcon#*before return 0, iclass 15, count 0 2006.257.03:11:51.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:51.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:11:51.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:11:51.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:11:51.91$vck44/vb=5,4 2006.257.03:11:51.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.03:11:51.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.03:11:51.91#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:51.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:51.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:51.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:51.97#ibcon#enter wrdev, iclass 17, count 2 2006.257.03:11:51.97#ibcon#first serial, iclass 17, count 2 2006.257.03:11:51.97#ibcon#enter sib2, iclass 17, count 2 2006.257.03:11:51.97#ibcon#flushed, iclass 17, count 2 2006.257.03:11:51.97#ibcon#about to write, iclass 17, count 2 2006.257.03:11:51.97#ibcon#wrote, iclass 17, count 2 2006.257.03:11:51.97#ibcon#about to read 3, iclass 17, count 2 2006.257.03:11:51.99#ibcon#read 3, iclass 17, count 2 2006.257.03:11:51.99#ibcon#about to read 4, iclass 17, count 2 2006.257.03:11:51.99#ibcon#read 4, iclass 17, count 2 2006.257.03:11:51.99#ibcon#about to read 5, iclass 17, count 2 2006.257.03:11:51.99#ibcon#read 5, iclass 17, count 2 2006.257.03:11:51.99#ibcon#about to read 6, iclass 17, count 2 2006.257.03:11:51.99#ibcon#read 6, iclass 17, count 2 2006.257.03:11:51.99#ibcon#end of sib2, iclass 17, count 2 2006.257.03:11:51.99#ibcon#*mode == 0, iclass 17, count 2 2006.257.03:11:51.99#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.03:11:51.99#ibcon#[27=AT05-04\r\n] 2006.257.03:11:51.99#ibcon#*before write, iclass 17, count 2 2006.257.03:11:51.99#ibcon#enter sib2, iclass 17, count 2 2006.257.03:11:51.99#ibcon#flushed, iclass 17, count 2 2006.257.03:11:51.99#ibcon#about to write, iclass 17, count 2 2006.257.03:11:51.99#ibcon#wrote, iclass 17, count 2 2006.257.03:11:51.99#ibcon#about to read 3, iclass 17, count 2 2006.257.03:11:52.02#ibcon#read 3, iclass 17, count 2 2006.257.03:11:52.02#ibcon#about to read 4, iclass 17, count 2 2006.257.03:11:52.02#ibcon#read 4, iclass 17, count 2 2006.257.03:11:52.02#ibcon#about to read 5, iclass 17, count 2 2006.257.03:11:52.02#ibcon#read 5, iclass 17, count 2 2006.257.03:11:52.02#ibcon#about to read 6, iclass 17, count 2 2006.257.03:11:52.02#ibcon#read 6, iclass 17, count 2 2006.257.03:11:52.02#ibcon#end of sib2, iclass 17, count 2 2006.257.03:11:52.02#ibcon#*after write, iclass 17, count 2 2006.257.03:11:52.02#ibcon#*before return 0, iclass 17, count 2 2006.257.03:11:52.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:52.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:11:52.02#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.03:11:52.02#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:52.02#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:52.14#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:52.14#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:52.14#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:11:52.14#ibcon#first serial, iclass 17, count 0 2006.257.03:11:52.14#ibcon#enter sib2, iclass 17, count 0 2006.257.03:11:52.14#ibcon#flushed, iclass 17, count 0 2006.257.03:11:52.14#ibcon#about to write, iclass 17, count 0 2006.257.03:11:52.14#ibcon#wrote, iclass 17, count 0 2006.257.03:11:52.14#ibcon#about to read 3, iclass 17, count 0 2006.257.03:11:52.16#ibcon#read 3, iclass 17, count 0 2006.257.03:11:52.16#ibcon#about to read 4, iclass 17, count 0 2006.257.03:11:52.16#ibcon#read 4, iclass 17, count 0 2006.257.03:11:52.16#ibcon#about to read 5, iclass 17, count 0 2006.257.03:11:52.16#ibcon#read 5, iclass 17, count 0 2006.257.03:11:52.16#ibcon#about to read 6, iclass 17, count 0 2006.257.03:11:52.16#ibcon#read 6, iclass 17, count 0 2006.257.03:11:52.16#ibcon#end of sib2, iclass 17, count 0 2006.257.03:11:52.16#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:11:52.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:11:52.16#ibcon#[27=USB\r\n] 2006.257.03:11:52.16#ibcon#*before write, iclass 17, count 0 2006.257.03:11:52.16#ibcon#enter sib2, iclass 17, count 0 2006.257.03:11:52.16#ibcon#flushed, iclass 17, count 0 2006.257.03:11:52.16#ibcon#about to write, iclass 17, count 0 2006.257.03:11:52.16#ibcon#wrote, iclass 17, count 0 2006.257.03:11:52.16#ibcon#about to read 3, iclass 17, count 0 2006.257.03:11:52.19#ibcon#read 3, iclass 17, count 0 2006.257.03:11:52.19#ibcon#about to read 4, iclass 17, count 0 2006.257.03:11:52.19#ibcon#read 4, iclass 17, count 0 2006.257.03:11:52.19#ibcon#about to read 5, iclass 17, count 0 2006.257.03:11:52.19#ibcon#read 5, iclass 17, count 0 2006.257.03:11:52.19#ibcon#about to read 6, iclass 17, count 0 2006.257.03:11:52.19#ibcon#read 6, iclass 17, count 0 2006.257.03:11:52.19#ibcon#end of sib2, iclass 17, count 0 2006.257.03:11:52.19#ibcon#*after write, iclass 17, count 0 2006.257.03:11:52.19#ibcon#*before return 0, iclass 17, count 0 2006.257.03:11:52.19#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:52.19#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:11:52.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:11:52.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:11:52.19$vck44/vblo=6,719.99 2006.257.03:11:52.19#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.03:11:52.19#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.03:11:52.19#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:52.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:52.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:52.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:52.19#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:11:52.19#ibcon#first serial, iclass 19, count 0 2006.257.03:11:52.19#ibcon#enter sib2, iclass 19, count 0 2006.257.03:11:52.19#ibcon#flushed, iclass 19, count 0 2006.257.03:11:52.19#ibcon#about to write, iclass 19, count 0 2006.257.03:11:52.19#ibcon#wrote, iclass 19, count 0 2006.257.03:11:52.19#ibcon#about to read 3, iclass 19, count 0 2006.257.03:11:52.21#ibcon#read 3, iclass 19, count 0 2006.257.03:11:52.21#ibcon#about to read 4, iclass 19, count 0 2006.257.03:11:52.21#ibcon#read 4, iclass 19, count 0 2006.257.03:11:52.21#ibcon#about to read 5, iclass 19, count 0 2006.257.03:11:52.21#ibcon#read 5, iclass 19, count 0 2006.257.03:11:52.21#ibcon#about to read 6, iclass 19, count 0 2006.257.03:11:52.21#ibcon#read 6, iclass 19, count 0 2006.257.03:11:52.21#ibcon#end of sib2, iclass 19, count 0 2006.257.03:11:52.21#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:11:52.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:11:52.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:11:52.21#ibcon#*before write, iclass 19, count 0 2006.257.03:11:52.21#ibcon#enter sib2, iclass 19, count 0 2006.257.03:11:52.21#ibcon#flushed, iclass 19, count 0 2006.257.03:11:52.21#ibcon#about to write, iclass 19, count 0 2006.257.03:11:52.21#ibcon#wrote, iclass 19, count 0 2006.257.03:11:52.21#ibcon#about to read 3, iclass 19, count 0 2006.257.03:11:52.25#ibcon#read 3, iclass 19, count 0 2006.257.03:11:52.25#ibcon#about to read 4, iclass 19, count 0 2006.257.03:11:52.25#ibcon#read 4, iclass 19, count 0 2006.257.03:11:52.25#ibcon#about to read 5, iclass 19, count 0 2006.257.03:11:52.25#ibcon#read 5, iclass 19, count 0 2006.257.03:11:52.25#ibcon#about to read 6, iclass 19, count 0 2006.257.03:11:52.25#ibcon#read 6, iclass 19, count 0 2006.257.03:11:52.25#ibcon#end of sib2, iclass 19, count 0 2006.257.03:11:52.25#ibcon#*after write, iclass 19, count 0 2006.257.03:11:52.25#ibcon#*before return 0, iclass 19, count 0 2006.257.03:11:52.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:52.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:11:52.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:11:52.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:11:52.25$vck44/vb=6,4 2006.257.03:11:52.25#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.03:11:52.25#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.03:11:52.25#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:52.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:52.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:52.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:52.31#ibcon#enter wrdev, iclass 21, count 2 2006.257.03:11:52.31#ibcon#first serial, iclass 21, count 2 2006.257.03:11:52.31#ibcon#enter sib2, iclass 21, count 2 2006.257.03:11:52.31#ibcon#flushed, iclass 21, count 2 2006.257.03:11:52.31#ibcon#about to write, iclass 21, count 2 2006.257.03:11:52.31#ibcon#wrote, iclass 21, count 2 2006.257.03:11:52.31#ibcon#about to read 3, iclass 21, count 2 2006.257.03:11:52.33#ibcon#read 3, iclass 21, count 2 2006.257.03:11:52.33#ibcon#about to read 4, iclass 21, count 2 2006.257.03:11:52.33#ibcon#read 4, iclass 21, count 2 2006.257.03:11:52.33#ibcon#about to read 5, iclass 21, count 2 2006.257.03:11:52.33#ibcon#read 5, iclass 21, count 2 2006.257.03:11:52.33#ibcon#about to read 6, iclass 21, count 2 2006.257.03:11:52.33#ibcon#read 6, iclass 21, count 2 2006.257.03:11:52.33#ibcon#end of sib2, iclass 21, count 2 2006.257.03:11:52.33#ibcon#*mode == 0, iclass 21, count 2 2006.257.03:11:52.33#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.03:11:52.33#ibcon#[27=AT06-04\r\n] 2006.257.03:11:52.33#ibcon#*before write, iclass 21, count 2 2006.257.03:11:52.33#ibcon#enter sib2, iclass 21, count 2 2006.257.03:11:52.33#ibcon#flushed, iclass 21, count 2 2006.257.03:11:52.33#ibcon#about to write, iclass 21, count 2 2006.257.03:11:52.33#ibcon#wrote, iclass 21, count 2 2006.257.03:11:52.33#ibcon#about to read 3, iclass 21, count 2 2006.257.03:11:52.36#ibcon#read 3, iclass 21, count 2 2006.257.03:11:52.36#ibcon#about to read 4, iclass 21, count 2 2006.257.03:11:52.36#ibcon#read 4, iclass 21, count 2 2006.257.03:11:52.36#ibcon#about to read 5, iclass 21, count 2 2006.257.03:11:52.36#ibcon#read 5, iclass 21, count 2 2006.257.03:11:52.36#ibcon#about to read 6, iclass 21, count 2 2006.257.03:11:52.36#ibcon#read 6, iclass 21, count 2 2006.257.03:11:52.36#ibcon#end of sib2, iclass 21, count 2 2006.257.03:11:52.36#ibcon#*after write, iclass 21, count 2 2006.257.03:11:52.36#ibcon#*before return 0, iclass 21, count 2 2006.257.03:11:52.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:52.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:11:52.36#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.03:11:52.36#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:52.36#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:52.48#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:52.48#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:52.48#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:11:52.48#ibcon#first serial, iclass 21, count 0 2006.257.03:11:52.48#ibcon#enter sib2, iclass 21, count 0 2006.257.03:11:52.48#ibcon#flushed, iclass 21, count 0 2006.257.03:11:52.48#ibcon#about to write, iclass 21, count 0 2006.257.03:11:52.48#ibcon#wrote, iclass 21, count 0 2006.257.03:11:52.48#ibcon#about to read 3, iclass 21, count 0 2006.257.03:11:52.50#ibcon#read 3, iclass 21, count 0 2006.257.03:11:52.50#ibcon#about to read 4, iclass 21, count 0 2006.257.03:11:52.50#ibcon#read 4, iclass 21, count 0 2006.257.03:11:52.50#ibcon#about to read 5, iclass 21, count 0 2006.257.03:11:52.50#ibcon#read 5, iclass 21, count 0 2006.257.03:11:52.50#ibcon#about to read 6, iclass 21, count 0 2006.257.03:11:52.50#ibcon#read 6, iclass 21, count 0 2006.257.03:11:52.50#ibcon#end of sib2, iclass 21, count 0 2006.257.03:11:52.50#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:11:52.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:11:52.50#ibcon#[27=USB\r\n] 2006.257.03:11:52.50#ibcon#*before write, iclass 21, count 0 2006.257.03:11:52.50#ibcon#enter sib2, iclass 21, count 0 2006.257.03:11:52.50#ibcon#flushed, iclass 21, count 0 2006.257.03:11:52.50#ibcon#about to write, iclass 21, count 0 2006.257.03:11:52.50#ibcon#wrote, iclass 21, count 0 2006.257.03:11:52.50#ibcon#about to read 3, iclass 21, count 0 2006.257.03:11:52.53#ibcon#read 3, iclass 21, count 0 2006.257.03:11:52.53#ibcon#about to read 4, iclass 21, count 0 2006.257.03:11:52.53#ibcon#read 4, iclass 21, count 0 2006.257.03:11:52.53#ibcon#about to read 5, iclass 21, count 0 2006.257.03:11:52.53#ibcon#read 5, iclass 21, count 0 2006.257.03:11:52.53#ibcon#about to read 6, iclass 21, count 0 2006.257.03:11:52.53#ibcon#read 6, iclass 21, count 0 2006.257.03:11:52.53#ibcon#end of sib2, iclass 21, count 0 2006.257.03:11:52.53#ibcon#*after write, iclass 21, count 0 2006.257.03:11:52.53#ibcon#*before return 0, iclass 21, count 0 2006.257.03:11:52.53#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:52.53#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:11:52.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:11:52.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:11:52.53$vck44/vblo=7,734.99 2006.257.03:11:52.53#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.03:11:52.53#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.03:11:52.53#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:52.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:52.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:52.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:52.53#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:11:52.53#ibcon#first serial, iclass 23, count 0 2006.257.03:11:52.53#ibcon#enter sib2, iclass 23, count 0 2006.257.03:11:52.53#ibcon#flushed, iclass 23, count 0 2006.257.03:11:52.53#ibcon#about to write, iclass 23, count 0 2006.257.03:11:52.53#ibcon#wrote, iclass 23, count 0 2006.257.03:11:52.53#ibcon#about to read 3, iclass 23, count 0 2006.257.03:11:52.55#ibcon#read 3, iclass 23, count 0 2006.257.03:11:52.55#ibcon#about to read 4, iclass 23, count 0 2006.257.03:11:52.55#ibcon#read 4, iclass 23, count 0 2006.257.03:11:52.55#ibcon#about to read 5, iclass 23, count 0 2006.257.03:11:52.55#ibcon#read 5, iclass 23, count 0 2006.257.03:11:52.55#ibcon#about to read 6, iclass 23, count 0 2006.257.03:11:52.55#ibcon#read 6, iclass 23, count 0 2006.257.03:11:52.55#ibcon#end of sib2, iclass 23, count 0 2006.257.03:11:52.55#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:11:52.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:11:52.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:11:52.55#ibcon#*before write, iclass 23, count 0 2006.257.03:11:52.55#ibcon#enter sib2, iclass 23, count 0 2006.257.03:11:52.55#ibcon#flushed, iclass 23, count 0 2006.257.03:11:52.55#ibcon#about to write, iclass 23, count 0 2006.257.03:11:52.55#ibcon#wrote, iclass 23, count 0 2006.257.03:11:52.55#ibcon#about to read 3, iclass 23, count 0 2006.257.03:11:52.59#ibcon#read 3, iclass 23, count 0 2006.257.03:11:52.59#ibcon#about to read 4, iclass 23, count 0 2006.257.03:11:52.59#ibcon#read 4, iclass 23, count 0 2006.257.03:11:52.59#ibcon#about to read 5, iclass 23, count 0 2006.257.03:11:52.59#ibcon#read 5, iclass 23, count 0 2006.257.03:11:52.59#ibcon#about to read 6, iclass 23, count 0 2006.257.03:11:52.59#ibcon#read 6, iclass 23, count 0 2006.257.03:11:52.59#ibcon#end of sib2, iclass 23, count 0 2006.257.03:11:52.59#ibcon#*after write, iclass 23, count 0 2006.257.03:11:52.59#ibcon#*before return 0, iclass 23, count 0 2006.257.03:11:52.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:52.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:11:52.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:11:52.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:11:52.59$vck44/vb=7,4 2006.257.03:11:52.59#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.03:11:52.59#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.03:11:52.59#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:52.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:52.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:52.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:52.65#ibcon#enter wrdev, iclass 25, count 2 2006.257.03:11:52.65#ibcon#first serial, iclass 25, count 2 2006.257.03:11:52.65#ibcon#enter sib2, iclass 25, count 2 2006.257.03:11:52.65#ibcon#flushed, iclass 25, count 2 2006.257.03:11:52.65#ibcon#about to write, iclass 25, count 2 2006.257.03:11:52.65#ibcon#wrote, iclass 25, count 2 2006.257.03:11:52.65#ibcon#about to read 3, iclass 25, count 2 2006.257.03:11:52.67#ibcon#read 3, iclass 25, count 2 2006.257.03:11:52.67#ibcon#about to read 4, iclass 25, count 2 2006.257.03:11:52.67#ibcon#read 4, iclass 25, count 2 2006.257.03:11:52.67#ibcon#about to read 5, iclass 25, count 2 2006.257.03:11:52.67#ibcon#read 5, iclass 25, count 2 2006.257.03:11:52.67#ibcon#about to read 6, iclass 25, count 2 2006.257.03:11:52.67#ibcon#read 6, iclass 25, count 2 2006.257.03:11:52.67#ibcon#end of sib2, iclass 25, count 2 2006.257.03:11:52.67#ibcon#*mode == 0, iclass 25, count 2 2006.257.03:11:52.67#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.03:11:52.67#ibcon#[27=AT07-04\r\n] 2006.257.03:11:52.67#ibcon#*before write, iclass 25, count 2 2006.257.03:11:52.67#ibcon#enter sib2, iclass 25, count 2 2006.257.03:11:52.67#ibcon#flushed, iclass 25, count 2 2006.257.03:11:52.67#ibcon#about to write, iclass 25, count 2 2006.257.03:11:52.67#ibcon#wrote, iclass 25, count 2 2006.257.03:11:52.67#ibcon#about to read 3, iclass 25, count 2 2006.257.03:11:52.70#ibcon#read 3, iclass 25, count 2 2006.257.03:11:52.70#ibcon#about to read 4, iclass 25, count 2 2006.257.03:11:52.70#ibcon#read 4, iclass 25, count 2 2006.257.03:11:52.70#ibcon#about to read 5, iclass 25, count 2 2006.257.03:11:52.70#ibcon#read 5, iclass 25, count 2 2006.257.03:11:52.70#ibcon#about to read 6, iclass 25, count 2 2006.257.03:11:52.70#ibcon#read 6, iclass 25, count 2 2006.257.03:11:52.70#ibcon#end of sib2, iclass 25, count 2 2006.257.03:11:52.70#ibcon#*after write, iclass 25, count 2 2006.257.03:11:52.70#ibcon#*before return 0, iclass 25, count 2 2006.257.03:11:52.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:52.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:11:52.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.03:11:52.70#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:52.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:52.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:52.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:52.82#ibcon#enter wrdev, iclass 25, count 0 2006.257.03:11:52.82#ibcon#first serial, iclass 25, count 0 2006.257.03:11:52.82#ibcon#enter sib2, iclass 25, count 0 2006.257.03:11:52.82#ibcon#flushed, iclass 25, count 0 2006.257.03:11:52.82#ibcon#about to write, iclass 25, count 0 2006.257.03:11:52.82#ibcon#wrote, iclass 25, count 0 2006.257.03:11:52.82#ibcon#about to read 3, iclass 25, count 0 2006.257.03:11:52.84#ibcon#read 3, iclass 25, count 0 2006.257.03:11:52.84#ibcon#about to read 4, iclass 25, count 0 2006.257.03:11:52.84#ibcon#read 4, iclass 25, count 0 2006.257.03:11:52.84#ibcon#about to read 5, iclass 25, count 0 2006.257.03:11:52.84#ibcon#read 5, iclass 25, count 0 2006.257.03:11:52.84#ibcon#about to read 6, iclass 25, count 0 2006.257.03:11:52.84#ibcon#read 6, iclass 25, count 0 2006.257.03:11:52.84#ibcon#end of sib2, iclass 25, count 0 2006.257.03:11:52.84#ibcon#*mode == 0, iclass 25, count 0 2006.257.03:11:52.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.03:11:52.84#ibcon#[27=USB\r\n] 2006.257.03:11:52.84#ibcon#*before write, iclass 25, count 0 2006.257.03:11:52.84#ibcon#enter sib2, iclass 25, count 0 2006.257.03:11:52.84#ibcon#flushed, iclass 25, count 0 2006.257.03:11:52.84#ibcon#about to write, iclass 25, count 0 2006.257.03:11:52.84#ibcon#wrote, iclass 25, count 0 2006.257.03:11:52.84#ibcon#about to read 3, iclass 25, count 0 2006.257.03:11:52.87#ibcon#read 3, iclass 25, count 0 2006.257.03:11:52.87#ibcon#about to read 4, iclass 25, count 0 2006.257.03:11:52.87#ibcon#read 4, iclass 25, count 0 2006.257.03:11:52.87#ibcon#about to read 5, iclass 25, count 0 2006.257.03:11:52.87#ibcon#read 5, iclass 25, count 0 2006.257.03:11:52.87#ibcon#about to read 6, iclass 25, count 0 2006.257.03:11:52.87#ibcon#read 6, iclass 25, count 0 2006.257.03:11:52.87#ibcon#end of sib2, iclass 25, count 0 2006.257.03:11:52.87#ibcon#*after write, iclass 25, count 0 2006.257.03:11:52.87#ibcon#*before return 0, iclass 25, count 0 2006.257.03:11:52.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:52.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:11:52.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.03:11:52.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.03:11:52.87$vck44/vblo=8,744.99 2006.257.03:11:52.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.03:11:52.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.03:11:52.87#ibcon#ireg 17 cls_cnt 0 2006.257.03:11:52.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:52.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:52.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:52.87#ibcon#enter wrdev, iclass 27, count 0 2006.257.03:11:52.87#ibcon#first serial, iclass 27, count 0 2006.257.03:11:52.87#ibcon#enter sib2, iclass 27, count 0 2006.257.03:11:52.87#ibcon#flushed, iclass 27, count 0 2006.257.03:11:52.87#ibcon#about to write, iclass 27, count 0 2006.257.03:11:52.87#ibcon#wrote, iclass 27, count 0 2006.257.03:11:52.87#ibcon#about to read 3, iclass 27, count 0 2006.257.03:11:52.89#ibcon#read 3, iclass 27, count 0 2006.257.03:11:52.89#ibcon#about to read 4, iclass 27, count 0 2006.257.03:11:52.89#ibcon#read 4, iclass 27, count 0 2006.257.03:11:52.89#ibcon#about to read 5, iclass 27, count 0 2006.257.03:11:52.89#ibcon#read 5, iclass 27, count 0 2006.257.03:11:52.89#ibcon#about to read 6, iclass 27, count 0 2006.257.03:11:52.89#ibcon#read 6, iclass 27, count 0 2006.257.03:11:52.89#ibcon#end of sib2, iclass 27, count 0 2006.257.03:11:52.89#ibcon#*mode == 0, iclass 27, count 0 2006.257.03:11:52.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.03:11:52.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:11:52.89#ibcon#*before write, iclass 27, count 0 2006.257.03:11:52.89#ibcon#enter sib2, iclass 27, count 0 2006.257.03:11:52.89#ibcon#flushed, iclass 27, count 0 2006.257.03:11:52.89#ibcon#about to write, iclass 27, count 0 2006.257.03:11:52.89#ibcon#wrote, iclass 27, count 0 2006.257.03:11:52.89#ibcon#about to read 3, iclass 27, count 0 2006.257.03:11:52.93#ibcon#read 3, iclass 27, count 0 2006.257.03:11:52.93#ibcon#about to read 4, iclass 27, count 0 2006.257.03:11:52.93#ibcon#read 4, iclass 27, count 0 2006.257.03:11:52.93#ibcon#about to read 5, iclass 27, count 0 2006.257.03:11:52.93#ibcon#read 5, iclass 27, count 0 2006.257.03:11:52.93#ibcon#about to read 6, iclass 27, count 0 2006.257.03:11:52.93#ibcon#read 6, iclass 27, count 0 2006.257.03:11:52.93#ibcon#end of sib2, iclass 27, count 0 2006.257.03:11:52.93#ibcon#*after write, iclass 27, count 0 2006.257.03:11:52.93#ibcon#*before return 0, iclass 27, count 0 2006.257.03:11:52.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:52.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:11:52.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.03:11:52.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.03:11:52.93$vck44/vb=8,4 2006.257.03:11:52.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.03:11:52.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.03:11:52.93#ibcon#ireg 11 cls_cnt 2 2006.257.03:11:52.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:52.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:52.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:52.99#ibcon#enter wrdev, iclass 29, count 2 2006.257.03:11:52.99#ibcon#first serial, iclass 29, count 2 2006.257.03:11:52.99#ibcon#enter sib2, iclass 29, count 2 2006.257.03:11:52.99#ibcon#flushed, iclass 29, count 2 2006.257.03:11:52.99#ibcon#about to write, iclass 29, count 2 2006.257.03:11:52.99#ibcon#wrote, iclass 29, count 2 2006.257.03:11:52.99#ibcon#about to read 3, iclass 29, count 2 2006.257.03:11:53.01#ibcon#read 3, iclass 29, count 2 2006.257.03:11:53.01#ibcon#about to read 4, iclass 29, count 2 2006.257.03:11:53.01#ibcon#read 4, iclass 29, count 2 2006.257.03:11:53.01#ibcon#about to read 5, iclass 29, count 2 2006.257.03:11:53.01#ibcon#read 5, iclass 29, count 2 2006.257.03:11:53.01#ibcon#about to read 6, iclass 29, count 2 2006.257.03:11:53.01#ibcon#read 6, iclass 29, count 2 2006.257.03:11:53.01#ibcon#end of sib2, iclass 29, count 2 2006.257.03:11:53.01#ibcon#*mode == 0, iclass 29, count 2 2006.257.03:11:53.01#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.03:11:53.01#ibcon#[27=AT08-04\r\n] 2006.257.03:11:53.01#ibcon#*before write, iclass 29, count 2 2006.257.03:11:53.01#ibcon#enter sib2, iclass 29, count 2 2006.257.03:11:53.01#ibcon#flushed, iclass 29, count 2 2006.257.03:11:53.01#ibcon#about to write, iclass 29, count 2 2006.257.03:11:53.01#ibcon#wrote, iclass 29, count 2 2006.257.03:11:53.01#ibcon#about to read 3, iclass 29, count 2 2006.257.03:11:53.04#ibcon#read 3, iclass 29, count 2 2006.257.03:11:53.04#ibcon#about to read 4, iclass 29, count 2 2006.257.03:11:53.04#ibcon#read 4, iclass 29, count 2 2006.257.03:11:53.04#ibcon#about to read 5, iclass 29, count 2 2006.257.03:11:53.04#ibcon#read 5, iclass 29, count 2 2006.257.03:11:53.04#ibcon#about to read 6, iclass 29, count 2 2006.257.03:11:53.04#ibcon#read 6, iclass 29, count 2 2006.257.03:11:53.04#ibcon#end of sib2, iclass 29, count 2 2006.257.03:11:53.04#ibcon#*after write, iclass 29, count 2 2006.257.03:11:53.04#ibcon#*before return 0, iclass 29, count 2 2006.257.03:11:53.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:53.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:11:53.04#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.03:11:53.04#ibcon#ireg 7 cls_cnt 0 2006.257.03:11:53.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:53.16#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:53.16#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:53.16#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:11:53.16#ibcon#first serial, iclass 29, count 0 2006.257.03:11:53.16#ibcon#enter sib2, iclass 29, count 0 2006.257.03:11:53.16#ibcon#flushed, iclass 29, count 0 2006.257.03:11:53.16#ibcon#about to write, iclass 29, count 0 2006.257.03:11:53.16#ibcon#wrote, iclass 29, count 0 2006.257.03:11:53.16#ibcon#about to read 3, iclass 29, count 0 2006.257.03:11:53.18#ibcon#read 3, iclass 29, count 0 2006.257.03:11:53.18#ibcon#about to read 4, iclass 29, count 0 2006.257.03:11:53.18#ibcon#read 4, iclass 29, count 0 2006.257.03:11:53.18#ibcon#about to read 5, iclass 29, count 0 2006.257.03:11:53.18#ibcon#read 5, iclass 29, count 0 2006.257.03:11:53.18#ibcon#about to read 6, iclass 29, count 0 2006.257.03:11:53.18#ibcon#read 6, iclass 29, count 0 2006.257.03:11:53.18#ibcon#end of sib2, iclass 29, count 0 2006.257.03:11:53.18#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:11:53.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:11:53.18#ibcon#[27=USB\r\n] 2006.257.03:11:53.18#ibcon#*before write, iclass 29, count 0 2006.257.03:11:53.18#ibcon#enter sib2, iclass 29, count 0 2006.257.03:11:53.18#ibcon#flushed, iclass 29, count 0 2006.257.03:11:53.18#ibcon#about to write, iclass 29, count 0 2006.257.03:11:53.18#ibcon#wrote, iclass 29, count 0 2006.257.03:11:53.18#ibcon#about to read 3, iclass 29, count 0 2006.257.03:11:53.21#ibcon#read 3, iclass 29, count 0 2006.257.03:11:53.21#ibcon#about to read 4, iclass 29, count 0 2006.257.03:11:53.21#ibcon#read 4, iclass 29, count 0 2006.257.03:11:53.21#ibcon#about to read 5, iclass 29, count 0 2006.257.03:11:53.21#ibcon#read 5, iclass 29, count 0 2006.257.03:11:53.21#ibcon#about to read 6, iclass 29, count 0 2006.257.03:11:53.21#ibcon#read 6, iclass 29, count 0 2006.257.03:11:53.21#ibcon#end of sib2, iclass 29, count 0 2006.257.03:11:53.21#ibcon#*after write, iclass 29, count 0 2006.257.03:11:53.21#ibcon#*before return 0, iclass 29, count 0 2006.257.03:11:53.21#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:53.21#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:11:53.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:11:53.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:11:53.21$vck44/vabw=wide 2006.257.03:11:53.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.03:11:53.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.03:11:53.21#ibcon#ireg 8 cls_cnt 0 2006.257.03:11:53.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:53.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:53.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:53.21#ibcon#enter wrdev, iclass 31, count 0 2006.257.03:11:53.21#ibcon#first serial, iclass 31, count 0 2006.257.03:11:53.21#ibcon#enter sib2, iclass 31, count 0 2006.257.03:11:53.21#ibcon#flushed, iclass 31, count 0 2006.257.03:11:53.21#ibcon#about to write, iclass 31, count 0 2006.257.03:11:53.21#ibcon#wrote, iclass 31, count 0 2006.257.03:11:53.21#ibcon#about to read 3, iclass 31, count 0 2006.257.03:11:53.23#ibcon#read 3, iclass 31, count 0 2006.257.03:11:53.23#ibcon#about to read 4, iclass 31, count 0 2006.257.03:11:53.23#ibcon#read 4, iclass 31, count 0 2006.257.03:11:53.23#ibcon#about to read 5, iclass 31, count 0 2006.257.03:11:53.23#ibcon#read 5, iclass 31, count 0 2006.257.03:11:53.23#ibcon#about to read 6, iclass 31, count 0 2006.257.03:11:53.23#ibcon#read 6, iclass 31, count 0 2006.257.03:11:53.23#ibcon#end of sib2, iclass 31, count 0 2006.257.03:11:53.23#ibcon#*mode == 0, iclass 31, count 0 2006.257.03:11:53.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.03:11:53.23#ibcon#[25=BW32\r\n] 2006.257.03:11:53.23#ibcon#*before write, iclass 31, count 0 2006.257.03:11:53.23#ibcon#enter sib2, iclass 31, count 0 2006.257.03:11:53.23#ibcon#flushed, iclass 31, count 0 2006.257.03:11:53.23#ibcon#about to write, iclass 31, count 0 2006.257.03:11:53.23#ibcon#wrote, iclass 31, count 0 2006.257.03:11:53.23#ibcon#about to read 3, iclass 31, count 0 2006.257.03:11:53.26#ibcon#read 3, iclass 31, count 0 2006.257.03:11:53.26#ibcon#about to read 4, iclass 31, count 0 2006.257.03:11:53.26#ibcon#read 4, iclass 31, count 0 2006.257.03:11:53.26#ibcon#about to read 5, iclass 31, count 0 2006.257.03:11:53.26#ibcon#read 5, iclass 31, count 0 2006.257.03:11:53.26#ibcon#about to read 6, iclass 31, count 0 2006.257.03:11:53.26#ibcon#read 6, iclass 31, count 0 2006.257.03:11:53.26#ibcon#end of sib2, iclass 31, count 0 2006.257.03:11:53.26#ibcon#*after write, iclass 31, count 0 2006.257.03:11:53.26#ibcon#*before return 0, iclass 31, count 0 2006.257.03:11:53.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:53.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:11:53.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.03:11:53.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.03:11:53.26$vck44/vbbw=wide 2006.257.03:11:53.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.03:11:53.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.03:11:53.26#ibcon#ireg 8 cls_cnt 0 2006.257.03:11:53.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:11:53.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:11:53.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:11:53.33#ibcon#enter wrdev, iclass 33, count 0 2006.257.03:11:53.33#ibcon#first serial, iclass 33, count 0 2006.257.03:11:53.33#ibcon#enter sib2, iclass 33, count 0 2006.257.03:11:53.33#ibcon#flushed, iclass 33, count 0 2006.257.03:11:53.33#ibcon#about to write, iclass 33, count 0 2006.257.03:11:53.33#ibcon#wrote, iclass 33, count 0 2006.257.03:11:53.33#ibcon#about to read 3, iclass 33, count 0 2006.257.03:11:53.35#ibcon#read 3, iclass 33, count 0 2006.257.03:11:53.35#ibcon#about to read 4, iclass 33, count 0 2006.257.03:11:53.35#ibcon#read 4, iclass 33, count 0 2006.257.03:11:53.35#ibcon#about to read 5, iclass 33, count 0 2006.257.03:11:53.35#ibcon#read 5, iclass 33, count 0 2006.257.03:11:53.35#ibcon#about to read 6, iclass 33, count 0 2006.257.03:11:53.35#ibcon#read 6, iclass 33, count 0 2006.257.03:11:53.35#ibcon#end of sib2, iclass 33, count 0 2006.257.03:11:53.35#ibcon#*mode == 0, iclass 33, count 0 2006.257.03:11:53.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.03:11:53.35#ibcon#[27=BW32\r\n] 2006.257.03:11:53.35#ibcon#*before write, iclass 33, count 0 2006.257.03:11:53.35#ibcon#enter sib2, iclass 33, count 0 2006.257.03:11:53.35#ibcon#flushed, iclass 33, count 0 2006.257.03:11:53.35#ibcon#about to write, iclass 33, count 0 2006.257.03:11:53.35#ibcon#wrote, iclass 33, count 0 2006.257.03:11:53.35#ibcon#about to read 3, iclass 33, count 0 2006.257.03:11:53.38#ibcon#read 3, iclass 33, count 0 2006.257.03:11:53.38#ibcon#about to read 4, iclass 33, count 0 2006.257.03:11:53.38#ibcon#read 4, iclass 33, count 0 2006.257.03:11:53.38#ibcon#about to read 5, iclass 33, count 0 2006.257.03:11:53.38#ibcon#read 5, iclass 33, count 0 2006.257.03:11:53.38#ibcon#about to read 6, iclass 33, count 0 2006.257.03:11:53.38#ibcon#read 6, iclass 33, count 0 2006.257.03:11:53.38#ibcon#end of sib2, iclass 33, count 0 2006.257.03:11:53.38#ibcon#*after write, iclass 33, count 0 2006.257.03:11:53.38#ibcon#*before return 0, iclass 33, count 0 2006.257.03:11:53.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:11:53.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:11:53.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.03:11:53.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.03:11:53.38$setupk4/ifdk4 2006.257.03:11:53.38$ifdk4/lo= 2006.257.03:11:53.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:11:53.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:11:53.38$ifdk4/patch= 2006.257.03:11:53.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:11:53.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:11:53.38$setupk4/!*+20s 2006.257.03:11:54.39#abcon#<5=/14 2.0 6.0 19.05 941012.2\r\n> 2006.257.03:11:54.41#abcon#{5=INTERFACE CLEAR} 2006.257.03:11:54.47#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:12:04.56#abcon#<5=/14 2.0 6.0 19.04 941012.2\r\n> 2006.257.03:12:04.58#abcon#{5=INTERFACE CLEAR} 2006.257.03:12:04.64#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:12:07.88$setupk4/"tpicd 2006.257.03:12:07.88$setupk4/echo=off 2006.257.03:12:07.88$setupk4/xlog=off 2006.257.03:12:07.88:!2006.257.03:15:38 2006.257.03:12:17.14#trakl#Source acquired 2006.257.03:12:19.14#flagr#flagr/antenna,acquired 2006.257.03:15:38.00:preob 2006.257.03:15:38.14/onsource/TRACKING 2006.257.03:15:38.14:!2006.257.03:15:48 2006.257.03:15:48.00:"tape 2006.257.03:15:48.00:"st=record 2006.257.03:15:48.00:data_valid=on 2006.257.03:15:48.00:midob 2006.257.03:15:49.14/onsource/TRACKING 2006.257.03:15:49.14/wx/19.01,1012.2,96 2006.257.03:15:49.20/cable/+6.4849E-03 2006.257.03:15:50.29/va/01,08,usb,yes,33,35 2006.257.03:15:50.29/va/02,07,usb,yes,36,36 2006.257.03:15:50.29/va/03,08,usb,yes,32,34 2006.257.03:15:50.29/va/04,07,usb,yes,37,39 2006.257.03:15:50.29/va/05,04,usb,yes,33,33 2006.257.03:15:50.29/va/06,04,usb,yes,37,36 2006.257.03:15:50.29/va/07,04,usb,yes,37,38 2006.257.03:15:50.29/va/08,04,usb,yes,31,38 2006.257.03:15:50.52/valo/01,524.99,yes,locked 2006.257.03:15:50.52/valo/02,534.99,yes,locked 2006.257.03:15:50.52/valo/03,564.99,yes,locked 2006.257.03:15:50.52/valo/04,624.99,yes,locked 2006.257.03:15:50.52/valo/05,734.99,yes,locked 2006.257.03:15:50.52/valo/06,814.99,yes,locked 2006.257.03:15:50.52/valo/07,864.99,yes,locked 2006.257.03:15:50.52/valo/08,884.99,yes,locked 2006.257.03:15:51.61/vb/01,04,usb,yes,39,35 2006.257.03:15:51.61/vb/02,05,usb,yes,36,36 2006.257.03:15:51.61/vb/03,04,usb,yes,37,41 2006.257.03:15:51.61/vb/04,05,usb,yes,37,36 2006.257.03:15:51.61/vb/05,04,usb,yes,33,36 2006.257.03:15:51.61/vb/06,04,usb,yes,39,34 2006.257.03:15:51.61/vb/07,04,usb,yes,38,38 2006.257.03:15:51.61/vb/08,04,usb,yes,35,39 2006.257.03:15:51.85/vblo/01,629.99,yes,locked 2006.257.03:15:51.85/vblo/02,634.99,yes,locked 2006.257.03:15:51.85/vblo/03,649.99,yes,locked 2006.257.03:15:51.85/vblo/04,679.99,yes,locked 2006.257.03:15:51.85/vblo/05,709.99,yes,locked 2006.257.03:15:51.85/vblo/06,719.99,yes,locked 2006.257.03:15:51.85/vblo/07,734.99,yes,locked 2006.257.03:15:51.85/vblo/08,744.99,yes,locked 2006.257.03:15:52.00/vabw/8 2006.257.03:15:52.15/vbbw/8 2006.257.03:15:52.27/xfe/off,on,16.0 2006.257.03:15:52.65/ifatt/23,28,28,28 2006.257.03:15:53.07/fmout-gps/S +4.54E-07 2006.257.03:15:53.11:!2006.257.03:17:08 2006.257.03:17:08.00:data_valid=off 2006.257.03:17:08.00:"et 2006.257.03:17:08.01:!+3s 2006.257.03:17:11.03:"tape 2006.257.03:17:11.03:postob 2006.257.03:17:11.24/cable/+6.4855E-03 2006.257.03:17:11.24/wx/19.03,1012.2,95 2006.257.03:17:11.32/fmout-gps/S +4.55E-07 2006.257.03:17:11.32:scan_name=257-0320,jd0609,220 2006.257.03:17:11.32:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.257.03:17:12.14#flagr#flagr/antenna,new-source 2006.257.03:17:12.14:checkk5 2006.257.03:17:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:17:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:17:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:17:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:17:13.99/chk_obsdata//k5ts1/T2570315??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.03:17:14.35/chk_obsdata//k5ts2/T2570315??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.03:17:14.72/chk_obsdata//k5ts3/T2570315??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.03:17:15.08/chk_obsdata//k5ts4/T2570315??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.03:17:15.77/k5log//k5ts1_log_newline 2006.257.03:17:16.46/k5log//k5ts2_log_newline 2006.257.03:17:17.17/k5log//k5ts3_log_newline 2006.257.03:17:17.85/k5log//k5ts4_log_newline 2006.257.03:17:17.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:17:17.87:setupk4=1 2006.257.03:17:17.87$setupk4/echo=on 2006.257.03:17:17.87$setupk4/pcalon 2006.257.03:17:17.87$pcalon/"no phase cal control is implemented here 2006.257.03:17:17.87$setupk4/"tpicd=stop 2006.257.03:17:17.87$setupk4/"rec=synch_on 2006.257.03:17:17.87$setupk4/"rec_mode=128 2006.257.03:17:17.87$setupk4/!* 2006.257.03:17:17.87$setupk4/recpk4 2006.257.03:17:17.87$recpk4/recpatch= 2006.257.03:17:17.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:17:17.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:17:17.87$setupk4/vck44 2006.257.03:17:17.87$vck44/valo=1,524.99 2006.257.03:17:17.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.03:17:17.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.03:17:17.87#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:17.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:17.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:17.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:17.87#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:17:17.87#ibcon#first serial, iclass 22, count 0 2006.257.03:17:17.87#ibcon#enter sib2, iclass 22, count 0 2006.257.03:17:17.87#ibcon#flushed, iclass 22, count 0 2006.257.03:17:17.87#ibcon#about to write, iclass 22, count 0 2006.257.03:17:17.87#ibcon#wrote, iclass 22, count 0 2006.257.03:17:17.87#ibcon#about to read 3, iclass 22, count 0 2006.257.03:17:17.91#ibcon#read 3, iclass 22, count 0 2006.257.03:17:17.91#ibcon#about to read 4, iclass 22, count 0 2006.257.03:17:17.91#ibcon#read 4, iclass 22, count 0 2006.257.03:17:17.91#ibcon#about to read 5, iclass 22, count 0 2006.257.03:17:17.91#ibcon#read 5, iclass 22, count 0 2006.257.03:17:17.91#ibcon#about to read 6, iclass 22, count 0 2006.257.03:17:17.91#ibcon#read 6, iclass 22, count 0 2006.257.03:17:17.91#ibcon#end of sib2, iclass 22, count 0 2006.257.03:17:17.91#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:17:17.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:17:17.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:17:17.91#ibcon#*before write, iclass 22, count 0 2006.257.03:17:17.91#ibcon#enter sib2, iclass 22, count 0 2006.257.03:17:17.91#ibcon#flushed, iclass 22, count 0 2006.257.03:17:17.91#ibcon#about to write, iclass 22, count 0 2006.257.03:17:17.91#ibcon#wrote, iclass 22, count 0 2006.257.03:17:17.91#ibcon#about to read 3, iclass 22, count 0 2006.257.03:17:17.95#ibcon#read 3, iclass 22, count 0 2006.257.03:17:17.95#ibcon#about to read 4, iclass 22, count 0 2006.257.03:17:17.95#ibcon#read 4, iclass 22, count 0 2006.257.03:17:17.95#ibcon#about to read 5, iclass 22, count 0 2006.257.03:17:17.95#ibcon#read 5, iclass 22, count 0 2006.257.03:17:17.95#ibcon#about to read 6, iclass 22, count 0 2006.257.03:17:17.95#ibcon#read 6, iclass 22, count 0 2006.257.03:17:17.95#ibcon#end of sib2, iclass 22, count 0 2006.257.03:17:17.95#ibcon#*after write, iclass 22, count 0 2006.257.03:17:17.95#ibcon#*before return 0, iclass 22, count 0 2006.257.03:17:17.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:17.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:17.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:17:17.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:17:17.95$vck44/va=1,8 2006.257.03:17:17.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.03:17:17.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.03:17:17.95#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:17.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:17.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:17.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:17.95#ibcon#enter wrdev, iclass 24, count 2 2006.257.03:17:17.95#ibcon#first serial, iclass 24, count 2 2006.257.03:17:17.95#ibcon#enter sib2, iclass 24, count 2 2006.257.03:17:17.95#ibcon#flushed, iclass 24, count 2 2006.257.03:17:17.95#ibcon#about to write, iclass 24, count 2 2006.257.03:17:17.95#ibcon#wrote, iclass 24, count 2 2006.257.03:17:17.95#ibcon#about to read 3, iclass 24, count 2 2006.257.03:17:17.97#ibcon#read 3, iclass 24, count 2 2006.257.03:17:17.97#ibcon#about to read 4, iclass 24, count 2 2006.257.03:17:17.97#ibcon#read 4, iclass 24, count 2 2006.257.03:17:17.97#ibcon#about to read 5, iclass 24, count 2 2006.257.03:17:17.97#ibcon#read 5, iclass 24, count 2 2006.257.03:17:17.97#ibcon#about to read 6, iclass 24, count 2 2006.257.03:17:17.97#ibcon#read 6, iclass 24, count 2 2006.257.03:17:17.97#ibcon#end of sib2, iclass 24, count 2 2006.257.03:17:17.97#ibcon#*mode == 0, iclass 24, count 2 2006.257.03:17:17.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.03:17:17.97#ibcon#[25=AT01-08\r\n] 2006.257.03:17:17.97#ibcon#*before write, iclass 24, count 2 2006.257.03:17:17.97#ibcon#enter sib2, iclass 24, count 2 2006.257.03:17:17.97#ibcon#flushed, iclass 24, count 2 2006.257.03:17:17.97#ibcon#about to write, iclass 24, count 2 2006.257.03:17:17.97#ibcon#wrote, iclass 24, count 2 2006.257.03:17:17.97#ibcon#about to read 3, iclass 24, count 2 2006.257.03:17:18.00#ibcon#read 3, iclass 24, count 2 2006.257.03:17:18.00#ibcon#about to read 4, iclass 24, count 2 2006.257.03:17:18.00#ibcon#read 4, iclass 24, count 2 2006.257.03:17:18.00#ibcon#about to read 5, iclass 24, count 2 2006.257.03:17:18.00#ibcon#read 5, iclass 24, count 2 2006.257.03:17:18.00#ibcon#about to read 6, iclass 24, count 2 2006.257.03:17:18.00#ibcon#read 6, iclass 24, count 2 2006.257.03:17:18.00#ibcon#end of sib2, iclass 24, count 2 2006.257.03:17:18.00#ibcon#*after write, iclass 24, count 2 2006.257.03:17:18.00#ibcon#*before return 0, iclass 24, count 2 2006.257.03:17:18.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:18.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:18.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.03:17:18.00#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:18.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:18.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:18.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:18.12#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:17:18.12#ibcon#first serial, iclass 24, count 0 2006.257.03:17:18.12#ibcon#enter sib2, iclass 24, count 0 2006.257.03:17:18.12#ibcon#flushed, iclass 24, count 0 2006.257.03:17:18.12#ibcon#about to write, iclass 24, count 0 2006.257.03:17:18.12#ibcon#wrote, iclass 24, count 0 2006.257.03:17:18.12#ibcon#about to read 3, iclass 24, count 0 2006.257.03:17:18.14#ibcon#read 3, iclass 24, count 0 2006.257.03:17:18.14#ibcon#about to read 4, iclass 24, count 0 2006.257.03:17:18.14#ibcon#read 4, iclass 24, count 0 2006.257.03:17:18.14#ibcon#about to read 5, iclass 24, count 0 2006.257.03:17:18.14#ibcon#read 5, iclass 24, count 0 2006.257.03:17:18.14#ibcon#about to read 6, iclass 24, count 0 2006.257.03:17:18.14#ibcon#read 6, iclass 24, count 0 2006.257.03:17:18.14#ibcon#end of sib2, iclass 24, count 0 2006.257.03:17:18.14#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:17:18.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:17:18.14#ibcon#[25=USB\r\n] 2006.257.03:17:18.14#ibcon#*before write, iclass 24, count 0 2006.257.03:17:18.14#ibcon#enter sib2, iclass 24, count 0 2006.257.03:17:18.14#ibcon#flushed, iclass 24, count 0 2006.257.03:17:18.14#ibcon#about to write, iclass 24, count 0 2006.257.03:17:18.14#ibcon#wrote, iclass 24, count 0 2006.257.03:17:18.14#ibcon#about to read 3, iclass 24, count 0 2006.257.03:17:18.17#ibcon#read 3, iclass 24, count 0 2006.257.03:17:18.17#ibcon#about to read 4, iclass 24, count 0 2006.257.03:17:18.17#ibcon#read 4, iclass 24, count 0 2006.257.03:17:18.17#ibcon#about to read 5, iclass 24, count 0 2006.257.03:17:18.17#ibcon#read 5, iclass 24, count 0 2006.257.03:17:18.17#ibcon#about to read 6, iclass 24, count 0 2006.257.03:17:18.17#ibcon#read 6, iclass 24, count 0 2006.257.03:17:18.17#ibcon#end of sib2, iclass 24, count 0 2006.257.03:17:18.17#ibcon#*after write, iclass 24, count 0 2006.257.03:17:18.17#ibcon#*before return 0, iclass 24, count 0 2006.257.03:17:18.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:18.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:18.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:17:18.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:17:18.17$vck44/valo=2,534.99 2006.257.03:17:18.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.03:17:18.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.03:17:18.17#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:18.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:18.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:18.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:18.17#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:17:18.17#ibcon#first serial, iclass 26, count 0 2006.257.03:17:18.17#ibcon#enter sib2, iclass 26, count 0 2006.257.03:17:18.17#ibcon#flushed, iclass 26, count 0 2006.257.03:17:18.17#ibcon#about to write, iclass 26, count 0 2006.257.03:17:18.17#ibcon#wrote, iclass 26, count 0 2006.257.03:17:18.17#ibcon#about to read 3, iclass 26, count 0 2006.257.03:17:18.19#ibcon#read 3, iclass 26, count 0 2006.257.03:17:18.19#ibcon#about to read 4, iclass 26, count 0 2006.257.03:17:18.19#ibcon#read 4, iclass 26, count 0 2006.257.03:17:18.19#ibcon#about to read 5, iclass 26, count 0 2006.257.03:17:18.19#ibcon#read 5, iclass 26, count 0 2006.257.03:17:18.19#ibcon#about to read 6, iclass 26, count 0 2006.257.03:17:18.19#ibcon#read 6, iclass 26, count 0 2006.257.03:17:18.19#ibcon#end of sib2, iclass 26, count 0 2006.257.03:17:18.19#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:17:18.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:17:18.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:17:18.19#ibcon#*before write, iclass 26, count 0 2006.257.03:17:18.19#ibcon#enter sib2, iclass 26, count 0 2006.257.03:17:18.19#ibcon#flushed, iclass 26, count 0 2006.257.03:17:18.19#ibcon#about to write, iclass 26, count 0 2006.257.03:17:18.19#ibcon#wrote, iclass 26, count 0 2006.257.03:17:18.19#ibcon#about to read 3, iclass 26, count 0 2006.257.03:17:18.23#ibcon#read 3, iclass 26, count 0 2006.257.03:17:18.23#ibcon#about to read 4, iclass 26, count 0 2006.257.03:17:18.23#ibcon#read 4, iclass 26, count 0 2006.257.03:17:18.23#ibcon#about to read 5, iclass 26, count 0 2006.257.03:17:18.23#ibcon#read 5, iclass 26, count 0 2006.257.03:17:18.23#ibcon#about to read 6, iclass 26, count 0 2006.257.03:17:18.23#ibcon#read 6, iclass 26, count 0 2006.257.03:17:18.23#ibcon#end of sib2, iclass 26, count 0 2006.257.03:17:18.23#ibcon#*after write, iclass 26, count 0 2006.257.03:17:18.23#ibcon#*before return 0, iclass 26, count 0 2006.257.03:17:18.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:18.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:18.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:17:18.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:17:18.23$vck44/va=2,7 2006.257.03:17:18.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.03:17:18.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.03:17:18.23#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:18.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:18.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:18.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:18.29#ibcon#enter wrdev, iclass 28, count 2 2006.257.03:17:18.29#ibcon#first serial, iclass 28, count 2 2006.257.03:17:18.29#ibcon#enter sib2, iclass 28, count 2 2006.257.03:17:18.29#ibcon#flushed, iclass 28, count 2 2006.257.03:17:18.29#ibcon#about to write, iclass 28, count 2 2006.257.03:17:18.29#ibcon#wrote, iclass 28, count 2 2006.257.03:17:18.29#ibcon#about to read 3, iclass 28, count 2 2006.257.03:17:18.31#ibcon#read 3, iclass 28, count 2 2006.257.03:17:18.31#ibcon#about to read 4, iclass 28, count 2 2006.257.03:17:18.31#ibcon#read 4, iclass 28, count 2 2006.257.03:17:18.31#ibcon#about to read 5, iclass 28, count 2 2006.257.03:17:18.31#ibcon#read 5, iclass 28, count 2 2006.257.03:17:18.31#ibcon#about to read 6, iclass 28, count 2 2006.257.03:17:18.31#ibcon#read 6, iclass 28, count 2 2006.257.03:17:18.31#ibcon#end of sib2, iclass 28, count 2 2006.257.03:17:18.31#ibcon#*mode == 0, iclass 28, count 2 2006.257.03:17:18.31#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.03:17:18.31#ibcon#[25=AT02-07\r\n] 2006.257.03:17:18.31#ibcon#*before write, iclass 28, count 2 2006.257.03:17:18.31#ibcon#enter sib2, iclass 28, count 2 2006.257.03:17:18.31#ibcon#flushed, iclass 28, count 2 2006.257.03:17:18.31#ibcon#about to write, iclass 28, count 2 2006.257.03:17:18.31#ibcon#wrote, iclass 28, count 2 2006.257.03:17:18.31#ibcon#about to read 3, iclass 28, count 2 2006.257.03:17:18.34#ibcon#read 3, iclass 28, count 2 2006.257.03:17:18.34#ibcon#about to read 4, iclass 28, count 2 2006.257.03:17:18.34#ibcon#read 4, iclass 28, count 2 2006.257.03:17:18.34#ibcon#about to read 5, iclass 28, count 2 2006.257.03:17:18.34#ibcon#read 5, iclass 28, count 2 2006.257.03:17:18.34#ibcon#about to read 6, iclass 28, count 2 2006.257.03:17:18.34#ibcon#read 6, iclass 28, count 2 2006.257.03:17:18.34#ibcon#end of sib2, iclass 28, count 2 2006.257.03:17:18.34#ibcon#*after write, iclass 28, count 2 2006.257.03:17:18.34#ibcon#*before return 0, iclass 28, count 2 2006.257.03:17:18.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:18.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:18.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.03:17:18.34#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:18.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:18.46#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:18.46#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:18.46#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:17:18.46#ibcon#first serial, iclass 28, count 0 2006.257.03:17:18.46#ibcon#enter sib2, iclass 28, count 0 2006.257.03:17:18.46#ibcon#flushed, iclass 28, count 0 2006.257.03:17:18.46#ibcon#about to write, iclass 28, count 0 2006.257.03:17:18.46#ibcon#wrote, iclass 28, count 0 2006.257.03:17:18.46#ibcon#about to read 3, iclass 28, count 0 2006.257.03:17:18.48#ibcon#read 3, iclass 28, count 0 2006.257.03:17:18.48#ibcon#about to read 4, iclass 28, count 0 2006.257.03:17:18.48#ibcon#read 4, iclass 28, count 0 2006.257.03:17:18.48#ibcon#about to read 5, iclass 28, count 0 2006.257.03:17:18.48#ibcon#read 5, iclass 28, count 0 2006.257.03:17:18.48#ibcon#about to read 6, iclass 28, count 0 2006.257.03:17:18.48#ibcon#read 6, iclass 28, count 0 2006.257.03:17:18.48#ibcon#end of sib2, iclass 28, count 0 2006.257.03:17:18.48#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:17:18.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:17:18.48#ibcon#[25=USB\r\n] 2006.257.03:17:18.48#ibcon#*before write, iclass 28, count 0 2006.257.03:17:18.48#ibcon#enter sib2, iclass 28, count 0 2006.257.03:17:18.48#ibcon#flushed, iclass 28, count 0 2006.257.03:17:18.48#ibcon#about to write, iclass 28, count 0 2006.257.03:17:18.48#ibcon#wrote, iclass 28, count 0 2006.257.03:17:18.48#ibcon#about to read 3, iclass 28, count 0 2006.257.03:17:18.51#ibcon#read 3, iclass 28, count 0 2006.257.03:17:18.51#ibcon#about to read 4, iclass 28, count 0 2006.257.03:17:18.51#ibcon#read 4, iclass 28, count 0 2006.257.03:17:18.51#ibcon#about to read 5, iclass 28, count 0 2006.257.03:17:18.51#ibcon#read 5, iclass 28, count 0 2006.257.03:17:18.51#ibcon#about to read 6, iclass 28, count 0 2006.257.03:17:18.51#ibcon#read 6, iclass 28, count 0 2006.257.03:17:18.51#ibcon#end of sib2, iclass 28, count 0 2006.257.03:17:18.51#ibcon#*after write, iclass 28, count 0 2006.257.03:17:18.51#ibcon#*before return 0, iclass 28, count 0 2006.257.03:17:18.51#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:18.51#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:18.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:17:18.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:17:18.51$vck44/valo=3,564.99 2006.257.03:17:18.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.03:17:18.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.03:17:18.51#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:18.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:18.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:18.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:18.51#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:17:18.51#ibcon#first serial, iclass 30, count 0 2006.257.03:17:18.51#ibcon#enter sib2, iclass 30, count 0 2006.257.03:17:18.51#ibcon#flushed, iclass 30, count 0 2006.257.03:17:18.51#ibcon#about to write, iclass 30, count 0 2006.257.03:17:18.51#ibcon#wrote, iclass 30, count 0 2006.257.03:17:18.51#ibcon#about to read 3, iclass 30, count 0 2006.257.03:17:18.53#ibcon#read 3, iclass 30, count 0 2006.257.03:17:18.53#ibcon#about to read 4, iclass 30, count 0 2006.257.03:17:18.53#ibcon#read 4, iclass 30, count 0 2006.257.03:17:18.53#ibcon#about to read 5, iclass 30, count 0 2006.257.03:17:18.53#ibcon#read 5, iclass 30, count 0 2006.257.03:17:18.53#ibcon#about to read 6, iclass 30, count 0 2006.257.03:17:18.53#ibcon#read 6, iclass 30, count 0 2006.257.03:17:18.53#ibcon#end of sib2, iclass 30, count 0 2006.257.03:17:18.53#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:17:18.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:17:18.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:17:18.53#ibcon#*before write, iclass 30, count 0 2006.257.03:17:18.53#ibcon#enter sib2, iclass 30, count 0 2006.257.03:17:18.53#ibcon#flushed, iclass 30, count 0 2006.257.03:17:18.53#ibcon#about to write, iclass 30, count 0 2006.257.03:17:18.53#ibcon#wrote, iclass 30, count 0 2006.257.03:17:18.53#ibcon#about to read 3, iclass 30, count 0 2006.257.03:17:18.57#ibcon#read 3, iclass 30, count 0 2006.257.03:17:18.57#ibcon#about to read 4, iclass 30, count 0 2006.257.03:17:18.57#ibcon#read 4, iclass 30, count 0 2006.257.03:17:18.57#ibcon#about to read 5, iclass 30, count 0 2006.257.03:17:18.57#ibcon#read 5, iclass 30, count 0 2006.257.03:17:18.57#ibcon#about to read 6, iclass 30, count 0 2006.257.03:17:18.57#ibcon#read 6, iclass 30, count 0 2006.257.03:17:18.57#ibcon#end of sib2, iclass 30, count 0 2006.257.03:17:18.57#ibcon#*after write, iclass 30, count 0 2006.257.03:17:18.57#ibcon#*before return 0, iclass 30, count 0 2006.257.03:17:18.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:18.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:18.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:17:18.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:17:18.57$vck44/va=3,8 2006.257.03:17:18.57#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.03:17:18.57#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.03:17:18.57#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:18.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:18.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:18.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:18.63#ibcon#enter wrdev, iclass 32, count 2 2006.257.03:17:18.63#ibcon#first serial, iclass 32, count 2 2006.257.03:17:18.63#ibcon#enter sib2, iclass 32, count 2 2006.257.03:17:18.63#ibcon#flushed, iclass 32, count 2 2006.257.03:17:18.63#ibcon#about to write, iclass 32, count 2 2006.257.03:17:18.63#ibcon#wrote, iclass 32, count 2 2006.257.03:17:18.63#ibcon#about to read 3, iclass 32, count 2 2006.257.03:17:18.65#ibcon#read 3, iclass 32, count 2 2006.257.03:17:18.65#ibcon#about to read 4, iclass 32, count 2 2006.257.03:17:18.65#ibcon#read 4, iclass 32, count 2 2006.257.03:17:18.65#ibcon#about to read 5, iclass 32, count 2 2006.257.03:17:18.65#ibcon#read 5, iclass 32, count 2 2006.257.03:17:18.65#ibcon#about to read 6, iclass 32, count 2 2006.257.03:17:18.65#ibcon#read 6, iclass 32, count 2 2006.257.03:17:18.65#ibcon#end of sib2, iclass 32, count 2 2006.257.03:17:18.65#ibcon#*mode == 0, iclass 32, count 2 2006.257.03:17:18.65#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.03:17:18.65#ibcon#[25=AT03-08\r\n] 2006.257.03:17:18.65#ibcon#*before write, iclass 32, count 2 2006.257.03:17:18.65#ibcon#enter sib2, iclass 32, count 2 2006.257.03:17:18.65#ibcon#flushed, iclass 32, count 2 2006.257.03:17:18.65#ibcon#about to write, iclass 32, count 2 2006.257.03:17:18.65#ibcon#wrote, iclass 32, count 2 2006.257.03:17:18.65#ibcon#about to read 3, iclass 32, count 2 2006.257.03:17:18.68#ibcon#read 3, iclass 32, count 2 2006.257.03:17:18.68#ibcon#about to read 4, iclass 32, count 2 2006.257.03:17:18.68#ibcon#read 4, iclass 32, count 2 2006.257.03:17:18.68#ibcon#about to read 5, iclass 32, count 2 2006.257.03:17:18.68#ibcon#read 5, iclass 32, count 2 2006.257.03:17:18.68#ibcon#about to read 6, iclass 32, count 2 2006.257.03:17:18.68#ibcon#read 6, iclass 32, count 2 2006.257.03:17:18.68#ibcon#end of sib2, iclass 32, count 2 2006.257.03:17:18.68#ibcon#*after write, iclass 32, count 2 2006.257.03:17:18.68#ibcon#*before return 0, iclass 32, count 2 2006.257.03:17:18.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:18.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:18.68#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.03:17:18.68#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:18.68#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:18.80#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:18.80#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:18.80#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:17:18.80#ibcon#first serial, iclass 32, count 0 2006.257.03:17:18.80#ibcon#enter sib2, iclass 32, count 0 2006.257.03:17:18.80#ibcon#flushed, iclass 32, count 0 2006.257.03:17:18.80#ibcon#about to write, iclass 32, count 0 2006.257.03:17:18.80#ibcon#wrote, iclass 32, count 0 2006.257.03:17:18.80#ibcon#about to read 3, iclass 32, count 0 2006.257.03:17:18.82#ibcon#read 3, iclass 32, count 0 2006.257.03:17:18.82#ibcon#about to read 4, iclass 32, count 0 2006.257.03:17:18.82#ibcon#read 4, iclass 32, count 0 2006.257.03:17:18.82#ibcon#about to read 5, iclass 32, count 0 2006.257.03:17:18.82#ibcon#read 5, iclass 32, count 0 2006.257.03:17:18.82#ibcon#about to read 6, iclass 32, count 0 2006.257.03:17:18.82#ibcon#read 6, iclass 32, count 0 2006.257.03:17:18.82#ibcon#end of sib2, iclass 32, count 0 2006.257.03:17:18.82#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:17:18.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:17:18.82#ibcon#[25=USB\r\n] 2006.257.03:17:18.82#ibcon#*before write, iclass 32, count 0 2006.257.03:17:18.82#ibcon#enter sib2, iclass 32, count 0 2006.257.03:17:18.82#ibcon#flushed, iclass 32, count 0 2006.257.03:17:18.82#ibcon#about to write, iclass 32, count 0 2006.257.03:17:18.82#ibcon#wrote, iclass 32, count 0 2006.257.03:17:18.82#ibcon#about to read 3, iclass 32, count 0 2006.257.03:17:18.85#ibcon#read 3, iclass 32, count 0 2006.257.03:17:18.85#ibcon#about to read 4, iclass 32, count 0 2006.257.03:17:18.85#ibcon#read 4, iclass 32, count 0 2006.257.03:17:18.85#ibcon#about to read 5, iclass 32, count 0 2006.257.03:17:18.85#ibcon#read 5, iclass 32, count 0 2006.257.03:17:18.85#ibcon#about to read 6, iclass 32, count 0 2006.257.03:17:18.85#ibcon#read 6, iclass 32, count 0 2006.257.03:17:18.85#ibcon#end of sib2, iclass 32, count 0 2006.257.03:17:18.85#ibcon#*after write, iclass 32, count 0 2006.257.03:17:18.85#ibcon#*before return 0, iclass 32, count 0 2006.257.03:17:18.85#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:18.85#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:18.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:17:18.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:17:18.85$vck44/valo=4,624.99 2006.257.03:17:18.85#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.03:17:18.85#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.03:17:18.85#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:18.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:18.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:18.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:18.85#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:17:18.85#ibcon#first serial, iclass 34, count 0 2006.257.03:17:18.85#ibcon#enter sib2, iclass 34, count 0 2006.257.03:17:18.85#ibcon#flushed, iclass 34, count 0 2006.257.03:17:18.85#ibcon#about to write, iclass 34, count 0 2006.257.03:17:18.85#ibcon#wrote, iclass 34, count 0 2006.257.03:17:18.85#ibcon#about to read 3, iclass 34, count 0 2006.257.03:17:18.87#ibcon#read 3, iclass 34, count 0 2006.257.03:17:18.87#ibcon#about to read 4, iclass 34, count 0 2006.257.03:17:18.87#ibcon#read 4, iclass 34, count 0 2006.257.03:17:18.87#ibcon#about to read 5, iclass 34, count 0 2006.257.03:17:18.87#ibcon#read 5, iclass 34, count 0 2006.257.03:17:18.87#ibcon#about to read 6, iclass 34, count 0 2006.257.03:17:18.87#ibcon#read 6, iclass 34, count 0 2006.257.03:17:18.87#ibcon#end of sib2, iclass 34, count 0 2006.257.03:17:18.87#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:17:18.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:17:18.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:17:18.87#ibcon#*before write, iclass 34, count 0 2006.257.03:17:18.87#ibcon#enter sib2, iclass 34, count 0 2006.257.03:17:18.87#ibcon#flushed, iclass 34, count 0 2006.257.03:17:18.87#ibcon#about to write, iclass 34, count 0 2006.257.03:17:18.87#ibcon#wrote, iclass 34, count 0 2006.257.03:17:18.87#ibcon#about to read 3, iclass 34, count 0 2006.257.03:17:18.91#ibcon#read 3, iclass 34, count 0 2006.257.03:17:18.91#ibcon#about to read 4, iclass 34, count 0 2006.257.03:17:18.91#ibcon#read 4, iclass 34, count 0 2006.257.03:17:18.91#ibcon#about to read 5, iclass 34, count 0 2006.257.03:17:18.91#ibcon#read 5, iclass 34, count 0 2006.257.03:17:18.91#ibcon#about to read 6, iclass 34, count 0 2006.257.03:17:18.91#ibcon#read 6, iclass 34, count 0 2006.257.03:17:18.91#ibcon#end of sib2, iclass 34, count 0 2006.257.03:17:18.91#ibcon#*after write, iclass 34, count 0 2006.257.03:17:18.91#ibcon#*before return 0, iclass 34, count 0 2006.257.03:17:18.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:18.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:18.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:17:18.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:17:18.91$vck44/va=4,7 2006.257.03:17:18.91#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.03:17:18.91#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.03:17:18.91#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:18.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:18.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:18.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:18.97#ibcon#enter wrdev, iclass 36, count 2 2006.257.03:17:18.97#ibcon#first serial, iclass 36, count 2 2006.257.03:17:18.97#ibcon#enter sib2, iclass 36, count 2 2006.257.03:17:18.97#ibcon#flushed, iclass 36, count 2 2006.257.03:17:18.97#ibcon#about to write, iclass 36, count 2 2006.257.03:17:18.97#ibcon#wrote, iclass 36, count 2 2006.257.03:17:18.97#ibcon#about to read 3, iclass 36, count 2 2006.257.03:17:18.99#ibcon#read 3, iclass 36, count 2 2006.257.03:17:18.99#ibcon#about to read 4, iclass 36, count 2 2006.257.03:17:18.99#ibcon#read 4, iclass 36, count 2 2006.257.03:17:18.99#ibcon#about to read 5, iclass 36, count 2 2006.257.03:17:18.99#ibcon#read 5, iclass 36, count 2 2006.257.03:17:18.99#ibcon#about to read 6, iclass 36, count 2 2006.257.03:17:18.99#ibcon#read 6, iclass 36, count 2 2006.257.03:17:18.99#ibcon#end of sib2, iclass 36, count 2 2006.257.03:17:18.99#ibcon#*mode == 0, iclass 36, count 2 2006.257.03:17:18.99#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.03:17:18.99#ibcon#[25=AT04-07\r\n] 2006.257.03:17:18.99#ibcon#*before write, iclass 36, count 2 2006.257.03:17:18.99#ibcon#enter sib2, iclass 36, count 2 2006.257.03:17:18.99#ibcon#flushed, iclass 36, count 2 2006.257.03:17:18.99#ibcon#about to write, iclass 36, count 2 2006.257.03:17:18.99#ibcon#wrote, iclass 36, count 2 2006.257.03:17:18.99#ibcon#about to read 3, iclass 36, count 2 2006.257.03:17:19.02#ibcon#read 3, iclass 36, count 2 2006.257.03:17:19.02#ibcon#about to read 4, iclass 36, count 2 2006.257.03:17:19.02#ibcon#read 4, iclass 36, count 2 2006.257.03:17:19.02#ibcon#about to read 5, iclass 36, count 2 2006.257.03:17:19.02#ibcon#read 5, iclass 36, count 2 2006.257.03:17:19.02#ibcon#about to read 6, iclass 36, count 2 2006.257.03:17:19.02#ibcon#read 6, iclass 36, count 2 2006.257.03:17:19.02#ibcon#end of sib2, iclass 36, count 2 2006.257.03:17:19.02#ibcon#*after write, iclass 36, count 2 2006.257.03:17:19.02#ibcon#*before return 0, iclass 36, count 2 2006.257.03:17:19.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:19.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:19.02#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.03:17:19.02#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:19.02#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:19.14#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:19.14#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:19.14#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:17:19.14#ibcon#first serial, iclass 36, count 0 2006.257.03:17:19.14#ibcon#enter sib2, iclass 36, count 0 2006.257.03:17:19.14#ibcon#flushed, iclass 36, count 0 2006.257.03:17:19.14#ibcon#about to write, iclass 36, count 0 2006.257.03:17:19.14#ibcon#wrote, iclass 36, count 0 2006.257.03:17:19.14#ibcon#about to read 3, iclass 36, count 0 2006.257.03:17:19.16#ibcon#read 3, iclass 36, count 0 2006.257.03:17:19.16#ibcon#about to read 4, iclass 36, count 0 2006.257.03:17:19.16#ibcon#read 4, iclass 36, count 0 2006.257.03:17:19.16#ibcon#about to read 5, iclass 36, count 0 2006.257.03:17:19.16#ibcon#read 5, iclass 36, count 0 2006.257.03:17:19.16#ibcon#about to read 6, iclass 36, count 0 2006.257.03:17:19.16#ibcon#read 6, iclass 36, count 0 2006.257.03:17:19.16#ibcon#end of sib2, iclass 36, count 0 2006.257.03:17:19.16#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:17:19.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:17:19.16#ibcon#[25=USB\r\n] 2006.257.03:17:19.16#ibcon#*before write, iclass 36, count 0 2006.257.03:17:19.16#ibcon#enter sib2, iclass 36, count 0 2006.257.03:17:19.16#ibcon#flushed, iclass 36, count 0 2006.257.03:17:19.16#ibcon#about to write, iclass 36, count 0 2006.257.03:17:19.16#ibcon#wrote, iclass 36, count 0 2006.257.03:17:19.16#ibcon#about to read 3, iclass 36, count 0 2006.257.03:17:19.19#ibcon#read 3, iclass 36, count 0 2006.257.03:17:19.19#ibcon#about to read 4, iclass 36, count 0 2006.257.03:17:19.19#ibcon#read 4, iclass 36, count 0 2006.257.03:17:19.19#ibcon#about to read 5, iclass 36, count 0 2006.257.03:17:19.19#ibcon#read 5, iclass 36, count 0 2006.257.03:17:19.19#ibcon#about to read 6, iclass 36, count 0 2006.257.03:17:19.19#ibcon#read 6, iclass 36, count 0 2006.257.03:17:19.19#ibcon#end of sib2, iclass 36, count 0 2006.257.03:17:19.19#ibcon#*after write, iclass 36, count 0 2006.257.03:17:19.19#ibcon#*before return 0, iclass 36, count 0 2006.257.03:17:19.19#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:19.19#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:19.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:17:19.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:17:19.19$vck44/valo=5,734.99 2006.257.03:17:19.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.03:17:19.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.03:17:19.19#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:19.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:19.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:19.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:19.19#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:17:19.19#ibcon#first serial, iclass 38, count 0 2006.257.03:17:19.19#ibcon#enter sib2, iclass 38, count 0 2006.257.03:17:19.19#ibcon#flushed, iclass 38, count 0 2006.257.03:17:19.19#ibcon#about to write, iclass 38, count 0 2006.257.03:17:19.19#ibcon#wrote, iclass 38, count 0 2006.257.03:17:19.19#ibcon#about to read 3, iclass 38, count 0 2006.257.03:17:19.21#ibcon#read 3, iclass 38, count 0 2006.257.03:17:19.21#ibcon#about to read 4, iclass 38, count 0 2006.257.03:17:19.21#ibcon#read 4, iclass 38, count 0 2006.257.03:17:19.21#ibcon#about to read 5, iclass 38, count 0 2006.257.03:17:19.21#ibcon#read 5, iclass 38, count 0 2006.257.03:17:19.21#ibcon#about to read 6, iclass 38, count 0 2006.257.03:17:19.21#ibcon#read 6, iclass 38, count 0 2006.257.03:17:19.21#ibcon#end of sib2, iclass 38, count 0 2006.257.03:17:19.21#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:17:19.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:17:19.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:17:19.21#ibcon#*before write, iclass 38, count 0 2006.257.03:17:19.21#ibcon#enter sib2, iclass 38, count 0 2006.257.03:17:19.21#ibcon#flushed, iclass 38, count 0 2006.257.03:17:19.21#ibcon#about to write, iclass 38, count 0 2006.257.03:17:19.21#ibcon#wrote, iclass 38, count 0 2006.257.03:17:19.21#ibcon#about to read 3, iclass 38, count 0 2006.257.03:17:19.25#ibcon#read 3, iclass 38, count 0 2006.257.03:17:19.25#ibcon#about to read 4, iclass 38, count 0 2006.257.03:17:19.25#ibcon#read 4, iclass 38, count 0 2006.257.03:17:19.25#ibcon#about to read 5, iclass 38, count 0 2006.257.03:17:19.25#ibcon#read 5, iclass 38, count 0 2006.257.03:17:19.25#ibcon#about to read 6, iclass 38, count 0 2006.257.03:17:19.25#ibcon#read 6, iclass 38, count 0 2006.257.03:17:19.25#ibcon#end of sib2, iclass 38, count 0 2006.257.03:17:19.25#ibcon#*after write, iclass 38, count 0 2006.257.03:17:19.25#ibcon#*before return 0, iclass 38, count 0 2006.257.03:17:19.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:19.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:19.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:17:19.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:17:19.25$vck44/va=5,4 2006.257.03:17:19.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.03:17:19.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.03:17:19.25#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:19.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:19.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:19.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:19.31#ibcon#enter wrdev, iclass 40, count 2 2006.257.03:17:19.31#ibcon#first serial, iclass 40, count 2 2006.257.03:17:19.31#ibcon#enter sib2, iclass 40, count 2 2006.257.03:17:19.31#ibcon#flushed, iclass 40, count 2 2006.257.03:17:19.31#ibcon#about to write, iclass 40, count 2 2006.257.03:17:19.31#ibcon#wrote, iclass 40, count 2 2006.257.03:17:19.31#ibcon#about to read 3, iclass 40, count 2 2006.257.03:17:19.33#ibcon#read 3, iclass 40, count 2 2006.257.03:17:19.33#ibcon#about to read 4, iclass 40, count 2 2006.257.03:17:19.33#ibcon#read 4, iclass 40, count 2 2006.257.03:17:19.33#ibcon#about to read 5, iclass 40, count 2 2006.257.03:17:19.33#ibcon#read 5, iclass 40, count 2 2006.257.03:17:19.33#ibcon#about to read 6, iclass 40, count 2 2006.257.03:17:19.33#ibcon#read 6, iclass 40, count 2 2006.257.03:17:19.33#ibcon#end of sib2, iclass 40, count 2 2006.257.03:17:19.33#ibcon#*mode == 0, iclass 40, count 2 2006.257.03:17:19.33#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.03:17:19.33#ibcon#[25=AT05-04\r\n] 2006.257.03:17:19.33#ibcon#*before write, iclass 40, count 2 2006.257.03:17:19.33#ibcon#enter sib2, iclass 40, count 2 2006.257.03:17:19.33#ibcon#flushed, iclass 40, count 2 2006.257.03:17:19.33#ibcon#about to write, iclass 40, count 2 2006.257.03:17:19.33#ibcon#wrote, iclass 40, count 2 2006.257.03:17:19.33#ibcon#about to read 3, iclass 40, count 2 2006.257.03:17:19.36#ibcon#read 3, iclass 40, count 2 2006.257.03:17:19.36#ibcon#about to read 4, iclass 40, count 2 2006.257.03:17:19.36#ibcon#read 4, iclass 40, count 2 2006.257.03:17:19.36#ibcon#about to read 5, iclass 40, count 2 2006.257.03:17:19.36#ibcon#read 5, iclass 40, count 2 2006.257.03:17:19.36#ibcon#about to read 6, iclass 40, count 2 2006.257.03:17:19.36#ibcon#read 6, iclass 40, count 2 2006.257.03:17:19.36#ibcon#end of sib2, iclass 40, count 2 2006.257.03:17:19.36#ibcon#*after write, iclass 40, count 2 2006.257.03:17:19.36#ibcon#*before return 0, iclass 40, count 2 2006.257.03:17:19.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:19.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:19.36#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.03:17:19.36#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:19.36#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:19.48#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:19.48#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:19.48#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:17:19.48#ibcon#first serial, iclass 40, count 0 2006.257.03:17:19.48#ibcon#enter sib2, iclass 40, count 0 2006.257.03:17:19.48#ibcon#flushed, iclass 40, count 0 2006.257.03:17:19.48#ibcon#about to write, iclass 40, count 0 2006.257.03:17:19.48#ibcon#wrote, iclass 40, count 0 2006.257.03:17:19.48#ibcon#about to read 3, iclass 40, count 0 2006.257.03:17:19.50#ibcon#read 3, iclass 40, count 0 2006.257.03:17:19.50#ibcon#about to read 4, iclass 40, count 0 2006.257.03:17:19.50#ibcon#read 4, iclass 40, count 0 2006.257.03:17:19.50#ibcon#about to read 5, iclass 40, count 0 2006.257.03:17:19.50#ibcon#read 5, iclass 40, count 0 2006.257.03:17:19.50#ibcon#about to read 6, iclass 40, count 0 2006.257.03:17:19.50#ibcon#read 6, iclass 40, count 0 2006.257.03:17:19.50#ibcon#end of sib2, iclass 40, count 0 2006.257.03:17:19.50#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:17:19.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:17:19.50#ibcon#[25=USB\r\n] 2006.257.03:17:19.50#ibcon#*before write, iclass 40, count 0 2006.257.03:17:19.50#ibcon#enter sib2, iclass 40, count 0 2006.257.03:17:19.50#ibcon#flushed, iclass 40, count 0 2006.257.03:17:19.50#ibcon#about to write, iclass 40, count 0 2006.257.03:17:19.50#ibcon#wrote, iclass 40, count 0 2006.257.03:17:19.50#ibcon#about to read 3, iclass 40, count 0 2006.257.03:17:19.53#ibcon#read 3, iclass 40, count 0 2006.257.03:17:19.53#ibcon#about to read 4, iclass 40, count 0 2006.257.03:17:19.53#ibcon#read 4, iclass 40, count 0 2006.257.03:17:19.53#ibcon#about to read 5, iclass 40, count 0 2006.257.03:17:19.53#ibcon#read 5, iclass 40, count 0 2006.257.03:17:19.53#ibcon#about to read 6, iclass 40, count 0 2006.257.03:17:19.53#ibcon#read 6, iclass 40, count 0 2006.257.03:17:19.53#ibcon#end of sib2, iclass 40, count 0 2006.257.03:17:19.53#ibcon#*after write, iclass 40, count 0 2006.257.03:17:19.53#ibcon#*before return 0, iclass 40, count 0 2006.257.03:17:19.53#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:19.53#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:19.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:17:19.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:17:19.53$vck44/valo=6,814.99 2006.257.03:17:19.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.03:17:19.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.03:17:19.53#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:19.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:19.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:19.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:19.53#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:17:19.53#ibcon#first serial, iclass 4, count 0 2006.257.03:17:19.53#ibcon#enter sib2, iclass 4, count 0 2006.257.03:17:19.53#ibcon#flushed, iclass 4, count 0 2006.257.03:17:19.53#ibcon#about to write, iclass 4, count 0 2006.257.03:17:19.53#ibcon#wrote, iclass 4, count 0 2006.257.03:17:19.53#ibcon#about to read 3, iclass 4, count 0 2006.257.03:17:19.55#ibcon#read 3, iclass 4, count 0 2006.257.03:17:19.55#ibcon#about to read 4, iclass 4, count 0 2006.257.03:17:19.55#ibcon#read 4, iclass 4, count 0 2006.257.03:17:19.55#ibcon#about to read 5, iclass 4, count 0 2006.257.03:17:19.55#ibcon#read 5, iclass 4, count 0 2006.257.03:17:19.55#ibcon#about to read 6, iclass 4, count 0 2006.257.03:17:19.55#ibcon#read 6, iclass 4, count 0 2006.257.03:17:19.55#ibcon#end of sib2, iclass 4, count 0 2006.257.03:17:19.55#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:17:19.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:17:19.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:17:19.55#ibcon#*before write, iclass 4, count 0 2006.257.03:17:19.55#ibcon#enter sib2, iclass 4, count 0 2006.257.03:17:19.55#ibcon#flushed, iclass 4, count 0 2006.257.03:17:19.55#ibcon#about to write, iclass 4, count 0 2006.257.03:17:19.55#ibcon#wrote, iclass 4, count 0 2006.257.03:17:19.55#ibcon#about to read 3, iclass 4, count 0 2006.257.03:17:19.59#ibcon#read 3, iclass 4, count 0 2006.257.03:17:19.59#ibcon#about to read 4, iclass 4, count 0 2006.257.03:17:19.59#ibcon#read 4, iclass 4, count 0 2006.257.03:17:19.59#ibcon#about to read 5, iclass 4, count 0 2006.257.03:17:19.59#ibcon#read 5, iclass 4, count 0 2006.257.03:17:19.59#ibcon#about to read 6, iclass 4, count 0 2006.257.03:17:19.59#ibcon#read 6, iclass 4, count 0 2006.257.03:17:19.59#ibcon#end of sib2, iclass 4, count 0 2006.257.03:17:19.59#ibcon#*after write, iclass 4, count 0 2006.257.03:17:19.59#ibcon#*before return 0, iclass 4, count 0 2006.257.03:17:19.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:19.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:19.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:17:19.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:17:19.59$vck44/va=6,4 2006.257.03:17:19.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.03:17:19.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.03:17:19.59#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:19.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:19.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:19.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:19.65#ibcon#enter wrdev, iclass 6, count 2 2006.257.03:17:19.65#ibcon#first serial, iclass 6, count 2 2006.257.03:17:19.65#ibcon#enter sib2, iclass 6, count 2 2006.257.03:17:19.65#ibcon#flushed, iclass 6, count 2 2006.257.03:17:19.65#ibcon#about to write, iclass 6, count 2 2006.257.03:17:19.65#ibcon#wrote, iclass 6, count 2 2006.257.03:17:19.65#ibcon#about to read 3, iclass 6, count 2 2006.257.03:17:19.67#ibcon#read 3, iclass 6, count 2 2006.257.03:17:19.67#ibcon#about to read 4, iclass 6, count 2 2006.257.03:17:19.67#ibcon#read 4, iclass 6, count 2 2006.257.03:17:19.67#ibcon#about to read 5, iclass 6, count 2 2006.257.03:17:19.67#ibcon#read 5, iclass 6, count 2 2006.257.03:17:19.67#ibcon#about to read 6, iclass 6, count 2 2006.257.03:17:19.67#ibcon#read 6, iclass 6, count 2 2006.257.03:17:19.67#ibcon#end of sib2, iclass 6, count 2 2006.257.03:17:19.67#ibcon#*mode == 0, iclass 6, count 2 2006.257.03:17:19.67#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.03:17:19.67#ibcon#[25=AT06-04\r\n] 2006.257.03:17:19.67#ibcon#*before write, iclass 6, count 2 2006.257.03:17:19.67#ibcon#enter sib2, iclass 6, count 2 2006.257.03:17:19.67#ibcon#flushed, iclass 6, count 2 2006.257.03:17:19.67#ibcon#about to write, iclass 6, count 2 2006.257.03:17:19.67#ibcon#wrote, iclass 6, count 2 2006.257.03:17:19.67#ibcon#about to read 3, iclass 6, count 2 2006.257.03:17:19.70#ibcon#read 3, iclass 6, count 2 2006.257.03:17:19.70#ibcon#about to read 4, iclass 6, count 2 2006.257.03:17:19.70#ibcon#read 4, iclass 6, count 2 2006.257.03:17:19.70#ibcon#about to read 5, iclass 6, count 2 2006.257.03:17:19.70#ibcon#read 5, iclass 6, count 2 2006.257.03:17:19.70#ibcon#about to read 6, iclass 6, count 2 2006.257.03:17:19.70#ibcon#read 6, iclass 6, count 2 2006.257.03:17:19.70#ibcon#end of sib2, iclass 6, count 2 2006.257.03:17:19.70#ibcon#*after write, iclass 6, count 2 2006.257.03:17:19.70#ibcon#*before return 0, iclass 6, count 2 2006.257.03:17:19.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:19.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:19.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.03:17:19.70#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:19.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:19.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:19.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:19.82#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:17:19.82#ibcon#first serial, iclass 6, count 0 2006.257.03:17:19.82#ibcon#enter sib2, iclass 6, count 0 2006.257.03:17:19.82#ibcon#flushed, iclass 6, count 0 2006.257.03:17:19.82#ibcon#about to write, iclass 6, count 0 2006.257.03:17:19.82#ibcon#wrote, iclass 6, count 0 2006.257.03:17:19.82#ibcon#about to read 3, iclass 6, count 0 2006.257.03:17:19.84#ibcon#read 3, iclass 6, count 0 2006.257.03:17:19.84#ibcon#about to read 4, iclass 6, count 0 2006.257.03:17:19.84#ibcon#read 4, iclass 6, count 0 2006.257.03:17:19.84#ibcon#about to read 5, iclass 6, count 0 2006.257.03:17:19.84#ibcon#read 5, iclass 6, count 0 2006.257.03:17:19.84#ibcon#about to read 6, iclass 6, count 0 2006.257.03:17:19.84#ibcon#read 6, iclass 6, count 0 2006.257.03:17:19.84#ibcon#end of sib2, iclass 6, count 0 2006.257.03:17:19.84#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:17:19.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:17:19.84#ibcon#[25=USB\r\n] 2006.257.03:17:19.84#ibcon#*before write, iclass 6, count 0 2006.257.03:17:19.84#ibcon#enter sib2, iclass 6, count 0 2006.257.03:17:19.84#ibcon#flushed, iclass 6, count 0 2006.257.03:17:19.84#ibcon#about to write, iclass 6, count 0 2006.257.03:17:19.84#ibcon#wrote, iclass 6, count 0 2006.257.03:17:19.84#ibcon#about to read 3, iclass 6, count 0 2006.257.03:17:19.87#ibcon#read 3, iclass 6, count 0 2006.257.03:17:19.87#ibcon#about to read 4, iclass 6, count 0 2006.257.03:17:19.87#ibcon#read 4, iclass 6, count 0 2006.257.03:17:19.87#ibcon#about to read 5, iclass 6, count 0 2006.257.03:17:19.87#ibcon#read 5, iclass 6, count 0 2006.257.03:17:19.87#ibcon#about to read 6, iclass 6, count 0 2006.257.03:17:19.87#ibcon#read 6, iclass 6, count 0 2006.257.03:17:19.87#ibcon#end of sib2, iclass 6, count 0 2006.257.03:17:19.87#ibcon#*after write, iclass 6, count 0 2006.257.03:17:19.87#ibcon#*before return 0, iclass 6, count 0 2006.257.03:17:19.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:19.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:19.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:17:19.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:17:19.87$vck44/valo=7,864.99 2006.257.03:17:19.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.03:17:19.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.03:17:19.87#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:19.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:19.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:19.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:19.87#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:17:19.87#ibcon#first serial, iclass 10, count 0 2006.257.03:17:19.87#ibcon#enter sib2, iclass 10, count 0 2006.257.03:17:19.87#ibcon#flushed, iclass 10, count 0 2006.257.03:17:19.87#ibcon#about to write, iclass 10, count 0 2006.257.03:17:19.87#ibcon#wrote, iclass 10, count 0 2006.257.03:17:19.87#ibcon#about to read 3, iclass 10, count 0 2006.257.03:17:19.89#ibcon#read 3, iclass 10, count 0 2006.257.03:17:19.89#ibcon#about to read 4, iclass 10, count 0 2006.257.03:17:19.89#ibcon#read 4, iclass 10, count 0 2006.257.03:17:19.89#ibcon#about to read 5, iclass 10, count 0 2006.257.03:17:19.89#ibcon#read 5, iclass 10, count 0 2006.257.03:17:19.89#ibcon#about to read 6, iclass 10, count 0 2006.257.03:17:19.89#ibcon#read 6, iclass 10, count 0 2006.257.03:17:19.89#ibcon#end of sib2, iclass 10, count 0 2006.257.03:17:19.89#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:17:19.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:17:19.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:17:19.89#ibcon#*before write, iclass 10, count 0 2006.257.03:17:19.89#ibcon#enter sib2, iclass 10, count 0 2006.257.03:17:19.89#ibcon#flushed, iclass 10, count 0 2006.257.03:17:19.89#ibcon#about to write, iclass 10, count 0 2006.257.03:17:19.89#ibcon#wrote, iclass 10, count 0 2006.257.03:17:19.89#ibcon#about to read 3, iclass 10, count 0 2006.257.03:17:19.93#ibcon#read 3, iclass 10, count 0 2006.257.03:17:19.93#ibcon#about to read 4, iclass 10, count 0 2006.257.03:17:19.93#ibcon#read 4, iclass 10, count 0 2006.257.03:17:19.93#ibcon#about to read 5, iclass 10, count 0 2006.257.03:17:19.93#ibcon#read 5, iclass 10, count 0 2006.257.03:17:19.93#ibcon#about to read 6, iclass 10, count 0 2006.257.03:17:19.93#ibcon#read 6, iclass 10, count 0 2006.257.03:17:19.93#ibcon#end of sib2, iclass 10, count 0 2006.257.03:17:19.93#ibcon#*after write, iclass 10, count 0 2006.257.03:17:19.93#ibcon#*before return 0, iclass 10, count 0 2006.257.03:17:19.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:19.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:19.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:17:19.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:17:19.93$vck44/va=7,4 2006.257.03:17:19.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.03:17:19.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.03:17:19.93#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:19.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:19.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:19.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:19.99#ibcon#enter wrdev, iclass 12, count 2 2006.257.03:17:19.99#ibcon#first serial, iclass 12, count 2 2006.257.03:17:19.99#ibcon#enter sib2, iclass 12, count 2 2006.257.03:17:19.99#ibcon#flushed, iclass 12, count 2 2006.257.03:17:19.99#ibcon#about to write, iclass 12, count 2 2006.257.03:17:19.99#ibcon#wrote, iclass 12, count 2 2006.257.03:17:19.99#ibcon#about to read 3, iclass 12, count 2 2006.257.03:17:20.01#ibcon#read 3, iclass 12, count 2 2006.257.03:17:20.01#ibcon#about to read 4, iclass 12, count 2 2006.257.03:17:20.01#ibcon#read 4, iclass 12, count 2 2006.257.03:17:20.01#ibcon#about to read 5, iclass 12, count 2 2006.257.03:17:20.01#ibcon#read 5, iclass 12, count 2 2006.257.03:17:20.01#ibcon#about to read 6, iclass 12, count 2 2006.257.03:17:20.01#ibcon#read 6, iclass 12, count 2 2006.257.03:17:20.01#ibcon#end of sib2, iclass 12, count 2 2006.257.03:17:20.01#ibcon#*mode == 0, iclass 12, count 2 2006.257.03:17:20.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.03:17:20.01#ibcon#[25=AT07-04\r\n] 2006.257.03:17:20.01#ibcon#*before write, iclass 12, count 2 2006.257.03:17:20.01#ibcon#enter sib2, iclass 12, count 2 2006.257.03:17:20.01#ibcon#flushed, iclass 12, count 2 2006.257.03:17:20.01#ibcon#about to write, iclass 12, count 2 2006.257.03:17:20.01#ibcon#wrote, iclass 12, count 2 2006.257.03:17:20.01#ibcon#about to read 3, iclass 12, count 2 2006.257.03:17:20.04#ibcon#read 3, iclass 12, count 2 2006.257.03:17:20.04#ibcon#about to read 4, iclass 12, count 2 2006.257.03:17:20.04#ibcon#read 4, iclass 12, count 2 2006.257.03:17:20.04#ibcon#about to read 5, iclass 12, count 2 2006.257.03:17:20.04#ibcon#read 5, iclass 12, count 2 2006.257.03:17:20.04#ibcon#about to read 6, iclass 12, count 2 2006.257.03:17:20.04#ibcon#read 6, iclass 12, count 2 2006.257.03:17:20.04#ibcon#end of sib2, iclass 12, count 2 2006.257.03:17:20.04#ibcon#*after write, iclass 12, count 2 2006.257.03:17:20.04#ibcon#*before return 0, iclass 12, count 2 2006.257.03:17:20.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:20.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:20.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.03:17:20.04#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:20.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:20.11#abcon#<5=/14 1.9 6.0 19.03 951012.2\r\n> 2006.257.03:17:20.13#abcon#{5=INTERFACE CLEAR} 2006.257.03:17:20.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:20.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:20.16#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:17:20.16#ibcon#first serial, iclass 12, count 0 2006.257.03:17:20.16#ibcon#enter sib2, iclass 12, count 0 2006.257.03:17:20.16#ibcon#flushed, iclass 12, count 0 2006.257.03:17:20.16#ibcon#about to write, iclass 12, count 0 2006.257.03:17:20.16#ibcon#wrote, iclass 12, count 0 2006.257.03:17:20.16#ibcon#about to read 3, iclass 12, count 0 2006.257.03:17:20.18#ibcon#read 3, iclass 12, count 0 2006.257.03:17:20.18#ibcon#about to read 4, iclass 12, count 0 2006.257.03:17:20.18#ibcon#read 4, iclass 12, count 0 2006.257.03:17:20.18#ibcon#about to read 5, iclass 12, count 0 2006.257.03:17:20.18#ibcon#read 5, iclass 12, count 0 2006.257.03:17:20.18#ibcon#about to read 6, iclass 12, count 0 2006.257.03:17:20.18#ibcon#read 6, iclass 12, count 0 2006.257.03:17:20.18#ibcon#end of sib2, iclass 12, count 0 2006.257.03:17:20.18#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:17:20.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:17:20.18#ibcon#[25=USB\r\n] 2006.257.03:17:20.18#ibcon#*before write, iclass 12, count 0 2006.257.03:17:20.18#ibcon#enter sib2, iclass 12, count 0 2006.257.03:17:20.18#ibcon#flushed, iclass 12, count 0 2006.257.03:17:20.18#ibcon#about to write, iclass 12, count 0 2006.257.03:17:20.18#ibcon#wrote, iclass 12, count 0 2006.257.03:17:20.18#ibcon#about to read 3, iclass 12, count 0 2006.257.03:17:20.19#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:17:20.21#ibcon#read 3, iclass 12, count 0 2006.257.03:17:20.21#ibcon#about to read 4, iclass 12, count 0 2006.257.03:17:20.21#ibcon#read 4, iclass 12, count 0 2006.257.03:17:20.21#ibcon#about to read 5, iclass 12, count 0 2006.257.03:17:20.21#ibcon#read 5, iclass 12, count 0 2006.257.03:17:20.21#ibcon#about to read 6, iclass 12, count 0 2006.257.03:17:20.21#ibcon#read 6, iclass 12, count 0 2006.257.03:17:20.21#ibcon#end of sib2, iclass 12, count 0 2006.257.03:17:20.21#ibcon#*after write, iclass 12, count 0 2006.257.03:17:20.21#ibcon#*before return 0, iclass 12, count 0 2006.257.03:17:20.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:20.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:20.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:17:20.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:17:20.21$vck44/valo=8,884.99 2006.257.03:17:20.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.03:17:20.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.03:17:20.21#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:20.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:20.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:20.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:20.21#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:17:20.21#ibcon#first serial, iclass 18, count 0 2006.257.03:17:20.21#ibcon#enter sib2, iclass 18, count 0 2006.257.03:17:20.21#ibcon#flushed, iclass 18, count 0 2006.257.03:17:20.21#ibcon#about to write, iclass 18, count 0 2006.257.03:17:20.21#ibcon#wrote, iclass 18, count 0 2006.257.03:17:20.21#ibcon#about to read 3, iclass 18, count 0 2006.257.03:17:20.23#ibcon#read 3, iclass 18, count 0 2006.257.03:17:20.23#ibcon#about to read 4, iclass 18, count 0 2006.257.03:17:20.23#ibcon#read 4, iclass 18, count 0 2006.257.03:17:20.23#ibcon#about to read 5, iclass 18, count 0 2006.257.03:17:20.23#ibcon#read 5, iclass 18, count 0 2006.257.03:17:20.23#ibcon#about to read 6, iclass 18, count 0 2006.257.03:17:20.23#ibcon#read 6, iclass 18, count 0 2006.257.03:17:20.23#ibcon#end of sib2, iclass 18, count 0 2006.257.03:17:20.23#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:17:20.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:17:20.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:17:20.23#ibcon#*before write, iclass 18, count 0 2006.257.03:17:20.23#ibcon#enter sib2, iclass 18, count 0 2006.257.03:17:20.23#ibcon#flushed, iclass 18, count 0 2006.257.03:17:20.23#ibcon#about to write, iclass 18, count 0 2006.257.03:17:20.23#ibcon#wrote, iclass 18, count 0 2006.257.03:17:20.23#ibcon#about to read 3, iclass 18, count 0 2006.257.03:17:20.27#ibcon#read 3, iclass 18, count 0 2006.257.03:17:20.27#ibcon#about to read 4, iclass 18, count 0 2006.257.03:17:20.27#ibcon#read 4, iclass 18, count 0 2006.257.03:17:20.27#ibcon#about to read 5, iclass 18, count 0 2006.257.03:17:20.27#ibcon#read 5, iclass 18, count 0 2006.257.03:17:20.27#ibcon#about to read 6, iclass 18, count 0 2006.257.03:17:20.27#ibcon#read 6, iclass 18, count 0 2006.257.03:17:20.27#ibcon#end of sib2, iclass 18, count 0 2006.257.03:17:20.27#ibcon#*after write, iclass 18, count 0 2006.257.03:17:20.27#ibcon#*before return 0, iclass 18, count 0 2006.257.03:17:20.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:20.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:20.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:17:20.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:17:20.27$vck44/va=8,4 2006.257.03:17:20.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.03:17:20.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.03:17:20.27#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:20.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:17:20.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:17:20.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:17:20.33#ibcon#enter wrdev, iclass 20, count 2 2006.257.03:17:20.33#ibcon#first serial, iclass 20, count 2 2006.257.03:17:20.33#ibcon#enter sib2, iclass 20, count 2 2006.257.03:17:20.33#ibcon#flushed, iclass 20, count 2 2006.257.03:17:20.33#ibcon#about to write, iclass 20, count 2 2006.257.03:17:20.33#ibcon#wrote, iclass 20, count 2 2006.257.03:17:20.33#ibcon#about to read 3, iclass 20, count 2 2006.257.03:17:20.35#ibcon#read 3, iclass 20, count 2 2006.257.03:17:20.35#ibcon#about to read 4, iclass 20, count 2 2006.257.03:17:20.35#ibcon#read 4, iclass 20, count 2 2006.257.03:17:20.35#ibcon#about to read 5, iclass 20, count 2 2006.257.03:17:20.35#ibcon#read 5, iclass 20, count 2 2006.257.03:17:20.35#ibcon#about to read 6, iclass 20, count 2 2006.257.03:17:20.35#ibcon#read 6, iclass 20, count 2 2006.257.03:17:20.35#ibcon#end of sib2, iclass 20, count 2 2006.257.03:17:20.35#ibcon#*mode == 0, iclass 20, count 2 2006.257.03:17:20.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.03:17:20.35#ibcon#[25=AT08-04\r\n] 2006.257.03:17:20.35#ibcon#*before write, iclass 20, count 2 2006.257.03:17:20.35#ibcon#enter sib2, iclass 20, count 2 2006.257.03:17:20.35#ibcon#flushed, iclass 20, count 2 2006.257.03:17:20.35#ibcon#about to write, iclass 20, count 2 2006.257.03:17:20.35#ibcon#wrote, iclass 20, count 2 2006.257.03:17:20.35#ibcon#about to read 3, iclass 20, count 2 2006.257.03:17:20.38#ibcon#read 3, iclass 20, count 2 2006.257.03:17:20.38#ibcon#about to read 4, iclass 20, count 2 2006.257.03:17:20.38#ibcon#read 4, iclass 20, count 2 2006.257.03:17:20.38#ibcon#about to read 5, iclass 20, count 2 2006.257.03:17:20.38#ibcon#read 5, iclass 20, count 2 2006.257.03:17:20.38#ibcon#about to read 6, iclass 20, count 2 2006.257.03:17:20.38#ibcon#read 6, iclass 20, count 2 2006.257.03:17:20.38#ibcon#end of sib2, iclass 20, count 2 2006.257.03:17:20.38#ibcon#*after write, iclass 20, count 2 2006.257.03:17:20.38#ibcon#*before return 0, iclass 20, count 2 2006.257.03:17:20.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:17:20.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:17:20.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.03:17:20.38#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:20.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:17:20.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:17:20.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:17:20.50#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:17:20.50#ibcon#first serial, iclass 20, count 0 2006.257.03:17:20.50#ibcon#enter sib2, iclass 20, count 0 2006.257.03:17:20.50#ibcon#flushed, iclass 20, count 0 2006.257.03:17:20.50#ibcon#about to write, iclass 20, count 0 2006.257.03:17:20.50#ibcon#wrote, iclass 20, count 0 2006.257.03:17:20.50#ibcon#about to read 3, iclass 20, count 0 2006.257.03:17:20.52#ibcon#read 3, iclass 20, count 0 2006.257.03:17:20.52#ibcon#about to read 4, iclass 20, count 0 2006.257.03:17:20.52#ibcon#read 4, iclass 20, count 0 2006.257.03:17:20.52#ibcon#about to read 5, iclass 20, count 0 2006.257.03:17:20.52#ibcon#read 5, iclass 20, count 0 2006.257.03:17:20.52#ibcon#about to read 6, iclass 20, count 0 2006.257.03:17:20.52#ibcon#read 6, iclass 20, count 0 2006.257.03:17:20.52#ibcon#end of sib2, iclass 20, count 0 2006.257.03:17:20.52#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:17:20.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:17:20.52#ibcon#[25=USB\r\n] 2006.257.03:17:20.52#ibcon#*before write, iclass 20, count 0 2006.257.03:17:20.52#ibcon#enter sib2, iclass 20, count 0 2006.257.03:17:20.52#ibcon#flushed, iclass 20, count 0 2006.257.03:17:20.52#ibcon#about to write, iclass 20, count 0 2006.257.03:17:20.52#ibcon#wrote, iclass 20, count 0 2006.257.03:17:20.52#ibcon#about to read 3, iclass 20, count 0 2006.257.03:17:20.55#ibcon#read 3, iclass 20, count 0 2006.257.03:17:20.55#ibcon#about to read 4, iclass 20, count 0 2006.257.03:17:20.55#ibcon#read 4, iclass 20, count 0 2006.257.03:17:20.55#ibcon#about to read 5, iclass 20, count 0 2006.257.03:17:20.55#ibcon#read 5, iclass 20, count 0 2006.257.03:17:20.55#ibcon#about to read 6, iclass 20, count 0 2006.257.03:17:20.55#ibcon#read 6, iclass 20, count 0 2006.257.03:17:20.55#ibcon#end of sib2, iclass 20, count 0 2006.257.03:17:20.55#ibcon#*after write, iclass 20, count 0 2006.257.03:17:20.55#ibcon#*before return 0, iclass 20, count 0 2006.257.03:17:20.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:17:20.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:17:20.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:17:20.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:17:20.55$vck44/vblo=1,629.99 2006.257.03:17:20.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.03:17:20.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.03:17:20.55#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:20.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:20.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:20.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:20.55#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:17:20.55#ibcon#first serial, iclass 22, count 0 2006.257.03:17:20.55#ibcon#enter sib2, iclass 22, count 0 2006.257.03:17:20.55#ibcon#flushed, iclass 22, count 0 2006.257.03:17:20.55#ibcon#about to write, iclass 22, count 0 2006.257.03:17:20.55#ibcon#wrote, iclass 22, count 0 2006.257.03:17:20.55#ibcon#about to read 3, iclass 22, count 0 2006.257.03:17:20.57#ibcon#read 3, iclass 22, count 0 2006.257.03:17:20.57#ibcon#about to read 4, iclass 22, count 0 2006.257.03:17:20.57#ibcon#read 4, iclass 22, count 0 2006.257.03:17:20.57#ibcon#about to read 5, iclass 22, count 0 2006.257.03:17:20.57#ibcon#read 5, iclass 22, count 0 2006.257.03:17:20.57#ibcon#about to read 6, iclass 22, count 0 2006.257.03:17:20.57#ibcon#read 6, iclass 22, count 0 2006.257.03:17:20.57#ibcon#end of sib2, iclass 22, count 0 2006.257.03:17:20.57#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:17:20.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:17:20.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:17:20.57#ibcon#*before write, iclass 22, count 0 2006.257.03:17:20.57#ibcon#enter sib2, iclass 22, count 0 2006.257.03:17:20.57#ibcon#flushed, iclass 22, count 0 2006.257.03:17:20.57#ibcon#about to write, iclass 22, count 0 2006.257.03:17:20.57#ibcon#wrote, iclass 22, count 0 2006.257.03:17:20.57#ibcon#about to read 3, iclass 22, count 0 2006.257.03:17:20.61#ibcon#read 3, iclass 22, count 0 2006.257.03:17:20.61#ibcon#about to read 4, iclass 22, count 0 2006.257.03:17:20.61#ibcon#read 4, iclass 22, count 0 2006.257.03:17:20.61#ibcon#about to read 5, iclass 22, count 0 2006.257.03:17:20.61#ibcon#read 5, iclass 22, count 0 2006.257.03:17:20.61#ibcon#about to read 6, iclass 22, count 0 2006.257.03:17:20.61#ibcon#read 6, iclass 22, count 0 2006.257.03:17:20.61#ibcon#end of sib2, iclass 22, count 0 2006.257.03:17:20.61#ibcon#*after write, iclass 22, count 0 2006.257.03:17:20.61#ibcon#*before return 0, iclass 22, count 0 2006.257.03:17:20.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:20.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:17:20.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:17:20.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:17:20.61$vck44/vb=1,4 2006.257.03:17:20.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.03:17:20.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.03:17:20.61#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:20.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:20.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:20.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:20.61#ibcon#enter wrdev, iclass 24, count 2 2006.257.03:17:20.61#ibcon#first serial, iclass 24, count 2 2006.257.03:17:20.61#ibcon#enter sib2, iclass 24, count 2 2006.257.03:17:20.61#ibcon#flushed, iclass 24, count 2 2006.257.03:17:20.61#ibcon#about to write, iclass 24, count 2 2006.257.03:17:20.61#ibcon#wrote, iclass 24, count 2 2006.257.03:17:20.61#ibcon#about to read 3, iclass 24, count 2 2006.257.03:17:20.63#ibcon#read 3, iclass 24, count 2 2006.257.03:17:20.63#ibcon#about to read 4, iclass 24, count 2 2006.257.03:17:20.63#ibcon#read 4, iclass 24, count 2 2006.257.03:17:20.63#ibcon#about to read 5, iclass 24, count 2 2006.257.03:17:20.63#ibcon#read 5, iclass 24, count 2 2006.257.03:17:20.63#ibcon#about to read 6, iclass 24, count 2 2006.257.03:17:20.63#ibcon#read 6, iclass 24, count 2 2006.257.03:17:20.63#ibcon#end of sib2, iclass 24, count 2 2006.257.03:17:20.63#ibcon#*mode == 0, iclass 24, count 2 2006.257.03:17:20.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.03:17:20.63#ibcon#[27=AT01-04\r\n] 2006.257.03:17:20.63#ibcon#*before write, iclass 24, count 2 2006.257.03:17:20.63#ibcon#enter sib2, iclass 24, count 2 2006.257.03:17:20.63#ibcon#flushed, iclass 24, count 2 2006.257.03:17:20.63#ibcon#about to write, iclass 24, count 2 2006.257.03:17:20.63#ibcon#wrote, iclass 24, count 2 2006.257.03:17:20.63#ibcon#about to read 3, iclass 24, count 2 2006.257.03:17:20.66#ibcon#read 3, iclass 24, count 2 2006.257.03:17:20.66#ibcon#about to read 4, iclass 24, count 2 2006.257.03:17:20.66#ibcon#read 4, iclass 24, count 2 2006.257.03:17:20.66#ibcon#about to read 5, iclass 24, count 2 2006.257.03:17:20.66#ibcon#read 5, iclass 24, count 2 2006.257.03:17:20.66#ibcon#about to read 6, iclass 24, count 2 2006.257.03:17:20.66#ibcon#read 6, iclass 24, count 2 2006.257.03:17:20.66#ibcon#end of sib2, iclass 24, count 2 2006.257.03:17:20.66#ibcon#*after write, iclass 24, count 2 2006.257.03:17:20.66#ibcon#*before return 0, iclass 24, count 2 2006.257.03:17:20.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:20.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:17:20.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.03:17:20.66#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:20.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:20.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:20.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:20.78#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:17:20.78#ibcon#first serial, iclass 24, count 0 2006.257.03:17:20.78#ibcon#enter sib2, iclass 24, count 0 2006.257.03:17:20.78#ibcon#flushed, iclass 24, count 0 2006.257.03:17:20.78#ibcon#about to write, iclass 24, count 0 2006.257.03:17:20.78#ibcon#wrote, iclass 24, count 0 2006.257.03:17:20.78#ibcon#about to read 3, iclass 24, count 0 2006.257.03:17:20.80#ibcon#read 3, iclass 24, count 0 2006.257.03:17:20.80#ibcon#about to read 4, iclass 24, count 0 2006.257.03:17:20.80#ibcon#read 4, iclass 24, count 0 2006.257.03:17:20.80#ibcon#about to read 5, iclass 24, count 0 2006.257.03:17:20.80#ibcon#read 5, iclass 24, count 0 2006.257.03:17:20.80#ibcon#about to read 6, iclass 24, count 0 2006.257.03:17:20.80#ibcon#read 6, iclass 24, count 0 2006.257.03:17:20.80#ibcon#end of sib2, iclass 24, count 0 2006.257.03:17:20.80#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:17:20.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:17:20.80#ibcon#[27=USB\r\n] 2006.257.03:17:20.80#ibcon#*before write, iclass 24, count 0 2006.257.03:17:20.80#ibcon#enter sib2, iclass 24, count 0 2006.257.03:17:20.80#ibcon#flushed, iclass 24, count 0 2006.257.03:17:20.80#ibcon#about to write, iclass 24, count 0 2006.257.03:17:20.80#ibcon#wrote, iclass 24, count 0 2006.257.03:17:20.80#ibcon#about to read 3, iclass 24, count 0 2006.257.03:17:20.83#ibcon#read 3, iclass 24, count 0 2006.257.03:17:20.83#ibcon#about to read 4, iclass 24, count 0 2006.257.03:17:20.83#ibcon#read 4, iclass 24, count 0 2006.257.03:17:20.83#ibcon#about to read 5, iclass 24, count 0 2006.257.03:17:20.83#ibcon#read 5, iclass 24, count 0 2006.257.03:17:20.83#ibcon#about to read 6, iclass 24, count 0 2006.257.03:17:20.83#ibcon#read 6, iclass 24, count 0 2006.257.03:17:20.83#ibcon#end of sib2, iclass 24, count 0 2006.257.03:17:20.83#ibcon#*after write, iclass 24, count 0 2006.257.03:17:20.83#ibcon#*before return 0, iclass 24, count 0 2006.257.03:17:20.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:20.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:17:20.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:17:20.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:17:20.83$vck44/vblo=2,634.99 2006.257.03:17:20.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.03:17:20.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.03:17:20.83#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:20.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:20.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:20.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:20.83#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:17:20.83#ibcon#first serial, iclass 26, count 0 2006.257.03:17:20.83#ibcon#enter sib2, iclass 26, count 0 2006.257.03:17:20.83#ibcon#flushed, iclass 26, count 0 2006.257.03:17:20.83#ibcon#about to write, iclass 26, count 0 2006.257.03:17:20.83#ibcon#wrote, iclass 26, count 0 2006.257.03:17:20.83#ibcon#about to read 3, iclass 26, count 0 2006.257.03:17:20.85#ibcon#read 3, iclass 26, count 0 2006.257.03:17:20.85#ibcon#about to read 4, iclass 26, count 0 2006.257.03:17:20.85#ibcon#read 4, iclass 26, count 0 2006.257.03:17:20.85#ibcon#about to read 5, iclass 26, count 0 2006.257.03:17:20.85#ibcon#read 5, iclass 26, count 0 2006.257.03:17:20.85#ibcon#about to read 6, iclass 26, count 0 2006.257.03:17:20.85#ibcon#read 6, iclass 26, count 0 2006.257.03:17:20.85#ibcon#end of sib2, iclass 26, count 0 2006.257.03:17:20.85#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:17:20.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:17:20.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:17:20.85#ibcon#*before write, iclass 26, count 0 2006.257.03:17:20.85#ibcon#enter sib2, iclass 26, count 0 2006.257.03:17:20.85#ibcon#flushed, iclass 26, count 0 2006.257.03:17:20.85#ibcon#about to write, iclass 26, count 0 2006.257.03:17:20.85#ibcon#wrote, iclass 26, count 0 2006.257.03:17:20.85#ibcon#about to read 3, iclass 26, count 0 2006.257.03:17:20.89#ibcon#read 3, iclass 26, count 0 2006.257.03:17:20.89#ibcon#about to read 4, iclass 26, count 0 2006.257.03:17:20.89#ibcon#read 4, iclass 26, count 0 2006.257.03:17:20.89#ibcon#about to read 5, iclass 26, count 0 2006.257.03:17:20.89#ibcon#read 5, iclass 26, count 0 2006.257.03:17:20.89#ibcon#about to read 6, iclass 26, count 0 2006.257.03:17:20.89#ibcon#read 6, iclass 26, count 0 2006.257.03:17:20.89#ibcon#end of sib2, iclass 26, count 0 2006.257.03:17:20.89#ibcon#*after write, iclass 26, count 0 2006.257.03:17:20.89#ibcon#*before return 0, iclass 26, count 0 2006.257.03:17:20.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:20.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:17:20.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:17:20.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:17:20.89$vck44/vb=2,5 2006.257.03:17:20.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.03:17:20.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.03:17:20.89#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:20.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:20.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:20.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:20.95#ibcon#enter wrdev, iclass 28, count 2 2006.257.03:17:20.95#ibcon#first serial, iclass 28, count 2 2006.257.03:17:20.95#ibcon#enter sib2, iclass 28, count 2 2006.257.03:17:20.95#ibcon#flushed, iclass 28, count 2 2006.257.03:17:20.95#ibcon#about to write, iclass 28, count 2 2006.257.03:17:20.95#ibcon#wrote, iclass 28, count 2 2006.257.03:17:20.95#ibcon#about to read 3, iclass 28, count 2 2006.257.03:17:20.97#ibcon#read 3, iclass 28, count 2 2006.257.03:17:20.97#ibcon#about to read 4, iclass 28, count 2 2006.257.03:17:20.97#ibcon#read 4, iclass 28, count 2 2006.257.03:17:20.97#ibcon#about to read 5, iclass 28, count 2 2006.257.03:17:20.97#ibcon#read 5, iclass 28, count 2 2006.257.03:17:20.97#ibcon#about to read 6, iclass 28, count 2 2006.257.03:17:20.97#ibcon#read 6, iclass 28, count 2 2006.257.03:17:20.97#ibcon#end of sib2, iclass 28, count 2 2006.257.03:17:20.97#ibcon#*mode == 0, iclass 28, count 2 2006.257.03:17:20.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.03:17:20.97#ibcon#[27=AT02-05\r\n] 2006.257.03:17:20.97#ibcon#*before write, iclass 28, count 2 2006.257.03:17:20.97#ibcon#enter sib2, iclass 28, count 2 2006.257.03:17:20.97#ibcon#flushed, iclass 28, count 2 2006.257.03:17:20.97#ibcon#about to write, iclass 28, count 2 2006.257.03:17:20.97#ibcon#wrote, iclass 28, count 2 2006.257.03:17:20.97#ibcon#about to read 3, iclass 28, count 2 2006.257.03:17:21.00#ibcon#read 3, iclass 28, count 2 2006.257.03:17:21.00#ibcon#about to read 4, iclass 28, count 2 2006.257.03:17:21.00#ibcon#read 4, iclass 28, count 2 2006.257.03:17:21.00#ibcon#about to read 5, iclass 28, count 2 2006.257.03:17:21.00#ibcon#read 5, iclass 28, count 2 2006.257.03:17:21.00#ibcon#about to read 6, iclass 28, count 2 2006.257.03:17:21.00#ibcon#read 6, iclass 28, count 2 2006.257.03:17:21.00#ibcon#end of sib2, iclass 28, count 2 2006.257.03:17:21.00#ibcon#*after write, iclass 28, count 2 2006.257.03:17:21.00#ibcon#*before return 0, iclass 28, count 2 2006.257.03:17:21.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:21.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:17:21.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.03:17:21.00#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:21.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:21.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:21.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:21.12#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:17:21.12#ibcon#first serial, iclass 28, count 0 2006.257.03:17:21.12#ibcon#enter sib2, iclass 28, count 0 2006.257.03:17:21.12#ibcon#flushed, iclass 28, count 0 2006.257.03:17:21.12#ibcon#about to write, iclass 28, count 0 2006.257.03:17:21.12#ibcon#wrote, iclass 28, count 0 2006.257.03:17:21.12#ibcon#about to read 3, iclass 28, count 0 2006.257.03:17:21.14#ibcon#read 3, iclass 28, count 0 2006.257.03:17:21.14#ibcon#about to read 4, iclass 28, count 0 2006.257.03:17:21.14#ibcon#read 4, iclass 28, count 0 2006.257.03:17:21.14#ibcon#about to read 5, iclass 28, count 0 2006.257.03:17:21.14#ibcon#read 5, iclass 28, count 0 2006.257.03:17:21.14#ibcon#about to read 6, iclass 28, count 0 2006.257.03:17:21.14#ibcon#read 6, iclass 28, count 0 2006.257.03:17:21.14#ibcon#end of sib2, iclass 28, count 0 2006.257.03:17:21.14#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:17:21.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:17:21.14#ibcon#[27=USB\r\n] 2006.257.03:17:21.14#ibcon#*before write, iclass 28, count 0 2006.257.03:17:21.14#ibcon#enter sib2, iclass 28, count 0 2006.257.03:17:21.14#ibcon#flushed, iclass 28, count 0 2006.257.03:17:21.14#ibcon#about to write, iclass 28, count 0 2006.257.03:17:21.14#ibcon#wrote, iclass 28, count 0 2006.257.03:17:21.14#ibcon#about to read 3, iclass 28, count 0 2006.257.03:17:21.17#ibcon#read 3, iclass 28, count 0 2006.257.03:17:21.17#ibcon#about to read 4, iclass 28, count 0 2006.257.03:17:21.17#ibcon#read 4, iclass 28, count 0 2006.257.03:17:21.17#ibcon#about to read 5, iclass 28, count 0 2006.257.03:17:21.17#ibcon#read 5, iclass 28, count 0 2006.257.03:17:21.17#ibcon#about to read 6, iclass 28, count 0 2006.257.03:17:21.17#ibcon#read 6, iclass 28, count 0 2006.257.03:17:21.17#ibcon#end of sib2, iclass 28, count 0 2006.257.03:17:21.17#ibcon#*after write, iclass 28, count 0 2006.257.03:17:21.17#ibcon#*before return 0, iclass 28, count 0 2006.257.03:17:21.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:21.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:17:21.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:17:21.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:17:21.17$vck44/vblo=3,649.99 2006.257.03:17:21.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.03:17:21.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.03:17:21.17#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:21.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:21.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:21.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:21.17#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:17:21.17#ibcon#first serial, iclass 30, count 0 2006.257.03:17:21.17#ibcon#enter sib2, iclass 30, count 0 2006.257.03:17:21.17#ibcon#flushed, iclass 30, count 0 2006.257.03:17:21.17#ibcon#about to write, iclass 30, count 0 2006.257.03:17:21.17#ibcon#wrote, iclass 30, count 0 2006.257.03:17:21.17#ibcon#about to read 3, iclass 30, count 0 2006.257.03:17:21.19#ibcon#read 3, iclass 30, count 0 2006.257.03:17:21.19#ibcon#about to read 4, iclass 30, count 0 2006.257.03:17:21.19#ibcon#read 4, iclass 30, count 0 2006.257.03:17:21.19#ibcon#about to read 5, iclass 30, count 0 2006.257.03:17:21.19#ibcon#read 5, iclass 30, count 0 2006.257.03:17:21.19#ibcon#about to read 6, iclass 30, count 0 2006.257.03:17:21.19#ibcon#read 6, iclass 30, count 0 2006.257.03:17:21.19#ibcon#end of sib2, iclass 30, count 0 2006.257.03:17:21.19#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:17:21.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:17:21.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:17:21.19#ibcon#*before write, iclass 30, count 0 2006.257.03:17:21.19#ibcon#enter sib2, iclass 30, count 0 2006.257.03:17:21.19#ibcon#flushed, iclass 30, count 0 2006.257.03:17:21.19#ibcon#about to write, iclass 30, count 0 2006.257.03:17:21.19#ibcon#wrote, iclass 30, count 0 2006.257.03:17:21.19#ibcon#about to read 3, iclass 30, count 0 2006.257.03:17:21.23#ibcon#read 3, iclass 30, count 0 2006.257.03:17:21.23#ibcon#about to read 4, iclass 30, count 0 2006.257.03:17:21.23#ibcon#read 4, iclass 30, count 0 2006.257.03:17:21.23#ibcon#about to read 5, iclass 30, count 0 2006.257.03:17:21.23#ibcon#read 5, iclass 30, count 0 2006.257.03:17:21.23#ibcon#about to read 6, iclass 30, count 0 2006.257.03:17:21.23#ibcon#read 6, iclass 30, count 0 2006.257.03:17:21.23#ibcon#end of sib2, iclass 30, count 0 2006.257.03:17:21.23#ibcon#*after write, iclass 30, count 0 2006.257.03:17:21.23#ibcon#*before return 0, iclass 30, count 0 2006.257.03:17:21.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:21.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:17:21.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:17:21.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:17:21.23$vck44/vb=3,4 2006.257.03:17:21.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.03:17:21.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.03:17:21.23#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:21.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:21.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:21.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:21.29#ibcon#enter wrdev, iclass 32, count 2 2006.257.03:17:21.29#ibcon#first serial, iclass 32, count 2 2006.257.03:17:21.29#ibcon#enter sib2, iclass 32, count 2 2006.257.03:17:21.29#ibcon#flushed, iclass 32, count 2 2006.257.03:17:21.29#ibcon#about to write, iclass 32, count 2 2006.257.03:17:21.29#ibcon#wrote, iclass 32, count 2 2006.257.03:17:21.29#ibcon#about to read 3, iclass 32, count 2 2006.257.03:17:21.31#ibcon#read 3, iclass 32, count 2 2006.257.03:17:21.31#ibcon#about to read 4, iclass 32, count 2 2006.257.03:17:21.31#ibcon#read 4, iclass 32, count 2 2006.257.03:17:21.31#ibcon#about to read 5, iclass 32, count 2 2006.257.03:17:21.31#ibcon#read 5, iclass 32, count 2 2006.257.03:17:21.31#ibcon#about to read 6, iclass 32, count 2 2006.257.03:17:21.31#ibcon#read 6, iclass 32, count 2 2006.257.03:17:21.31#ibcon#end of sib2, iclass 32, count 2 2006.257.03:17:21.31#ibcon#*mode == 0, iclass 32, count 2 2006.257.03:17:21.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.03:17:21.31#ibcon#[27=AT03-04\r\n] 2006.257.03:17:21.31#ibcon#*before write, iclass 32, count 2 2006.257.03:17:21.31#ibcon#enter sib2, iclass 32, count 2 2006.257.03:17:21.31#ibcon#flushed, iclass 32, count 2 2006.257.03:17:21.31#ibcon#about to write, iclass 32, count 2 2006.257.03:17:21.31#ibcon#wrote, iclass 32, count 2 2006.257.03:17:21.31#ibcon#about to read 3, iclass 32, count 2 2006.257.03:17:21.34#ibcon#read 3, iclass 32, count 2 2006.257.03:17:21.34#ibcon#about to read 4, iclass 32, count 2 2006.257.03:17:21.34#ibcon#read 4, iclass 32, count 2 2006.257.03:17:21.34#ibcon#about to read 5, iclass 32, count 2 2006.257.03:17:21.34#ibcon#read 5, iclass 32, count 2 2006.257.03:17:21.34#ibcon#about to read 6, iclass 32, count 2 2006.257.03:17:21.34#ibcon#read 6, iclass 32, count 2 2006.257.03:17:21.34#ibcon#end of sib2, iclass 32, count 2 2006.257.03:17:21.34#ibcon#*after write, iclass 32, count 2 2006.257.03:17:21.34#ibcon#*before return 0, iclass 32, count 2 2006.257.03:17:21.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:21.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:17:21.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.03:17:21.34#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:21.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:21.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:21.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:21.46#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:17:21.46#ibcon#first serial, iclass 32, count 0 2006.257.03:17:21.46#ibcon#enter sib2, iclass 32, count 0 2006.257.03:17:21.46#ibcon#flushed, iclass 32, count 0 2006.257.03:17:21.46#ibcon#about to write, iclass 32, count 0 2006.257.03:17:21.46#ibcon#wrote, iclass 32, count 0 2006.257.03:17:21.46#ibcon#about to read 3, iclass 32, count 0 2006.257.03:17:21.48#ibcon#read 3, iclass 32, count 0 2006.257.03:17:21.48#ibcon#about to read 4, iclass 32, count 0 2006.257.03:17:21.48#ibcon#read 4, iclass 32, count 0 2006.257.03:17:21.48#ibcon#about to read 5, iclass 32, count 0 2006.257.03:17:21.48#ibcon#read 5, iclass 32, count 0 2006.257.03:17:21.48#ibcon#about to read 6, iclass 32, count 0 2006.257.03:17:21.48#ibcon#read 6, iclass 32, count 0 2006.257.03:17:21.48#ibcon#end of sib2, iclass 32, count 0 2006.257.03:17:21.48#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:17:21.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:17:21.48#ibcon#[27=USB\r\n] 2006.257.03:17:21.48#ibcon#*before write, iclass 32, count 0 2006.257.03:17:21.48#ibcon#enter sib2, iclass 32, count 0 2006.257.03:17:21.48#ibcon#flushed, iclass 32, count 0 2006.257.03:17:21.48#ibcon#about to write, iclass 32, count 0 2006.257.03:17:21.48#ibcon#wrote, iclass 32, count 0 2006.257.03:17:21.48#ibcon#about to read 3, iclass 32, count 0 2006.257.03:17:21.51#ibcon#read 3, iclass 32, count 0 2006.257.03:17:21.51#ibcon#about to read 4, iclass 32, count 0 2006.257.03:17:21.51#ibcon#read 4, iclass 32, count 0 2006.257.03:17:21.51#ibcon#about to read 5, iclass 32, count 0 2006.257.03:17:21.51#ibcon#read 5, iclass 32, count 0 2006.257.03:17:21.51#ibcon#about to read 6, iclass 32, count 0 2006.257.03:17:21.51#ibcon#read 6, iclass 32, count 0 2006.257.03:17:21.51#ibcon#end of sib2, iclass 32, count 0 2006.257.03:17:21.51#ibcon#*after write, iclass 32, count 0 2006.257.03:17:21.51#ibcon#*before return 0, iclass 32, count 0 2006.257.03:17:21.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:21.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:17:21.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:17:21.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:17:21.51$vck44/vblo=4,679.99 2006.257.03:17:21.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.03:17:21.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.03:17:21.51#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:21.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:21.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:21.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:21.51#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:17:21.51#ibcon#first serial, iclass 34, count 0 2006.257.03:17:21.51#ibcon#enter sib2, iclass 34, count 0 2006.257.03:17:21.51#ibcon#flushed, iclass 34, count 0 2006.257.03:17:21.51#ibcon#about to write, iclass 34, count 0 2006.257.03:17:21.51#ibcon#wrote, iclass 34, count 0 2006.257.03:17:21.51#ibcon#about to read 3, iclass 34, count 0 2006.257.03:17:21.53#ibcon#read 3, iclass 34, count 0 2006.257.03:17:21.53#ibcon#about to read 4, iclass 34, count 0 2006.257.03:17:21.53#ibcon#read 4, iclass 34, count 0 2006.257.03:17:21.53#ibcon#about to read 5, iclass 34, count 0 2006.257.03:17:21.53#ibcon#read 5, iclass 34, count 0 2006.257.03:17:21.53#ibcon#about to read 6, iclass 34, count 0 2006.257.03:17:21.53#ibcon#read 6, iclass 34, count 0 2006.257.03:17:21.53#ibcon#end of sib2, iclass 34, count 0 2006.257.03:17:21.53#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:17:21.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:17:21.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:17:21.53#ibcon#*before write, iclass 34, count 0 2006.257.03:17:21.53#ibcon#enter sib2, iclass 34, count 0 2006.257.03:17:21.53#ibcon#flushed, iclass 34, count 0 2006.257.03:17:21.53#ibcon#about to write, iclass 34, count 0 2006.257.03:17:21.53#ibcon#wrote, iclass 34, count 0 2006.257.03:17:21.53#ibcon#about to read 3, iclass 34, count 0 2006.257.03:17:21.57#ibcon#read 3, iclass 34, count 0 2006.257.03:17:21.57#ibcon#about to read 4, iclass 34, count 0 2006.257.03:17:21.57#ibcon#read 4, iclass 34, count 0 2006.257.03:17:21.57#ibcon#about to read 5, iclass 34, count 0 2006.257.03:17:21.57#ibcon#read 5, iclass 34, count 0 2006.257.03:17:21.57#ibcon#about to read 6, iclass 34, count 0 2006.257.03:17:21.57#ibcon#read 6, iclass 34, count 0 2006.257.03:17:21.57#ibcon#end of sib2, iclass 34, count 0 2006.257.03:17:21.57#ibcon#*after write, iclass 34, count 0 2006.257.03:17:21.57#ibcon#*before return 0, iclass 34, count 0 2006.257.03:17:21.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:21.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:17:21.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:17:21.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:17:21.57$vck44/vb=4,5 2006.257.03:17:21.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.03:17:21.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.03:17:21.57#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:21.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:21.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:21.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:21.63#ibcon#enter wrdev, iclass 36, count 2 2006.257.03:17:21.63#ibcon#first serial, iclass 36, count 2 2006.257.03:17:21.63#ibcon#enter sib2, iclass 36, count 2 2006.257.03:17:21.63#ibcon#flushed, iclass 36, count 2 2006.257.03:17:21.63#ibcon#about to write, iclass 36, count 2 2006.257.03:17:21.63#ibcon#wrote, iclass 36, count 2 2006.257.03:17:21.63#ibcon#about to read 3, iclass 36, count 2 2006.257.03:17:21.65#ibcon#read 3, iclass 36, count 2 2006.257.03:17:21.65#ibcon#about to read 4, iclass 36, count 2 2006.257.03:17:21.65#ibcon#read 4, iclass 36, count 2 2006.257.03:17:21.65#ibcon#about to read 5, iclass 36, count 2 2006.257.03:17:21.65#ibcon#read 5, iclass 36, count 2 2006.257.03:17:21.65#ibcon#about to read 6, iclass 36, count 2 2006.257.03:17:21.65#ibcon#read 6, iclass 36, count 2 2006.257.03:17:21.65#ibcon#end of sib2, iclass 36, count 2 2006.257.03:17:21.65#ibcon#*mode == 0, iclass 36, count 2 2006.257.03:17:21.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.03:17:21.65#ibcon#[27=AT04-05\r\n] 2006.257.03:17:21.65#ibcon#*before write, iclass 36, count 2 2006.257.03:17:21.65#ibcon#enter sib2, iclass 36, count 2 2006.257.03:17:21.65#ibcon#flushed, iclass 36, count 2 2006.257.03:17:21.65#ibcon#about to write, iclass 36, count 2 2006.257.03:17:21.65#ibcon#wrote, iclass 36, count 2 2006.257.03:17:21.65#ibcon#about to read 3, iclass 36, count 2 2006.257.03:17:21.68#ibcon#read 3, iclass 36, count 2 2006.257.03:17:21.68#ibcon#about to read 4, iclass 36, count 2 2006.257.03:17:21.68#ibcon#read 4, iclass 36, count 2 2006.257.03:17:21.68#ibcon#about to read 5, iclass 36, count 2 2006.257.03:17:21.68#ibcon#read 5, iclass 36, count 2 2006.257.03:17:21.68#ibcon#about to read 6, iclass 36, count 2 2006.257.03:17:21.68#ibcon#read 6, iclass 36, count 2 2006.257.03:17:21.68#ibcon#end of sib2, iclass 36, count 2 2006.257.03:17:21.68#ibcon#*after write, iclass 36, count 2 2006.257.03:17:21.68#ibcon#*before return 0, iclass 36, count 2 2006.257.03:17:21.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:21.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:17:21.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.03:17:21.68#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:21.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:21.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:21.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:21.80#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:17:21.80#ibcon#first serial, iclass 36, count 0 2006.257.03:17:21.80#ibcon#enter sib2, iclass 36, count 0 2006.257.03:17:21.80#ibcon#flushed, iclass 36, count 0 2006.257.03:17:21.80#ibcon#about to write, iclass 36, count 0 2006.257.03:17:21.80#ibcon#wrote, iclass 36, count 0 2006.257.03:17:21.80#ibcon#about to read 3, iclass 36, count 0 2006.257.03:17:21.82#ibcon#read 3, iclass 36, count 0 2006.257.03:17:21.82#ibcon#about to read 4, iclass 36, count 0 2006.257.03:17:21.82#ibcon#read 4, iclass 36, count 0 2006.257.03:17:21.82#ibcon#about to read 5, iclass 36, count 0 2006.257.03:17:21.82#ibcon#read 5, iclass 36, count 0 2006.257.03:17:21.82#ibcon#about to read 6, iclass 36, count 0 2006.257.03:17:21.82#ibcon#read 6, iclass 36, count 0 2006.257.03:17:21.82#ibcon#end of sib2, iclass 36, count 0 2006.257.03:17:21.82#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:17:21.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:17:21.82#ibcon#[27=USB\r\n] 2006.257.03:17:21.82#ibcon#*before write, iclass 36, count 0 2006.257.03:17:21.82#ibcon#enter sib2, iclass 36, count 0 2006.257.03:17:21.82#ibcon#flushed, iclass 36, count 0 2006.257.03:17:21.82#ibcon#about to write, iclass 36, count 0 2006.257.03:17:21.82#ibcon#wrote, iclass 36, count 0 2006.257.03:17:21.82#ibcon#about to read 3, iclass 36, count 0 2006.257.03:17:21.85#ibcon#read 3, iclass 36, count 0 2006.257.03:17:21.85#ibcon#about to read 4, iclass 36, count 0 2006.257.03:17:21.85#ibcon#read 4, iclass 36, count 0 2006.257.03:17:21.85#ibcon#about to read 5, iclass 36, count 0 2006.257.03:17:21.85#ibcon#read 5, iclass 36, count 0 2006.257.03:17:21.85#ibcon#about to read 6, iclass 36, count 0 2006.257.03:17:21.85#ibcon#read 6, iclass 36, count 0 2006.257.03:17:21.85#ibcon#end of sib2, iclass 36, count 0 2006.257.03:17:21.85#ibcon#*after write, iclass 36, count 0 2006.257.03:17:21.85#ibcon#*before return 0, iclass 36, count 0 2006.257.03:17:21.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:21.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:17:21.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:17:21.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:17:21.85$vck44/vblo=5,709.99 2006.257.03:17:21.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.03:17:21.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.03:17:21.85#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:21.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:21.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:21.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:21.85#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:17:21.85#ibcon#first serial, iclass 38, count 0 2006.257.03:17:21.85#ibcon#enter sib2, iclass 38, count 0 2006.257.03:17:21.85#ibcon#flushed, iclass 38, count 0 2006.257.03:17:21.85#ibcon#about to write, iclass 38, count 0 2006.257.03:17:21.85#ibcon#wrote, iclass 38, count 0 2006.257.03:17:21.85#ibcon#about to read 3, iclass 38, count 0 2006.257.03:17:21.87#ibcon#read 3, iclass 38, count 0 2006.257.03:17:21.87#ibcon#about to read 4, iclass 38, count 0 2006.257.03:17:21.87#ibcon#read 4, iclass 38, count 0 2006.257.03:17:21.87#ibcon#about to read 5, iclass 38, count 0 2006.257.03:17:21.87#ibcon#read 5, iclass 38, count 0 2006.257.03:17:21.87#ibcon#about to read 6, iclass 38, count 0 2006.257.03:17:21.87#ibcon#read 6, iclass 38, count 0 2006.257.03:17:21.87#ibcon#end of sib2, iclass 38, count 0 2006.257.03:17:21.87#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:17:21.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:17:21.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:17:21.87#ibcon#*before write, iclass 38, count 0 2006.257.03:17:21.87#ibcon#enter sib2, iclass 38, count 0 2006.257.03:17:21.87#ibcon#flushed, iclass 38, count 0 2006.257.03:17:21.87#ibcon#about to write, iclass 38, count 0 2006.257.03:17:21.87#ibcon#wrote, iclass 38, count 0 2006.257.03:17:21.87#ibcon#about to read 3, iclass 38, count 0 2006.257.03:17:21.91#ibcon#read 3, iclass 38, count 0 2006.257.03:17:21.91#ibcon#about to read 4, iclass 38, count 0 2006.257.03:17:21.91#ibcon#read 4, iclass 38, count 0 2006.257.03:17:21.91#ibcon#about to read 5, iclass 38, count 0 2006.257.03:17:21.91#ibcon#read 5, iclass 38, count 0 2006.257.03:17:21.91#ibcon#about to read 6, iclass 38, count 0 2006.257.03:17:21.91#ibcon#read 6, iclass 38, count 0 2006.257.03:17:21.91#ibcon#end of sib2, iclass 38, count 0 2006.257.03:17:21.91#ibcon#*after write, iclass 38, count 0 2006.257.03:17:21.91#ibcon#*before return 0, iclass 38, count 0 2006.257.03:17:21.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:21.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:17:21.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:17:21.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:17:21.91$vck44/vb=5,4 2006.257.03:17:21.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.03:17:21.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.03:17:21.91#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:21.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:21.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:21.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:21.97#ibcon#enter wrdev, iclass 40, count 2 2006.257.03:17:21.97#ibcon#first serial, iclass 40, count 2 2006.257.03:17:21.97#ibcon#enter sib2, iclass 40, count 2 2006.257.03:17:21.97#ibcon#flushed, iclass 40, count 2 2006.257.03:17:21.97#ibcon#about to write, iclass 40, count 2 2006.257.03:17:21.97#ibcon#wrote, iclass 40, count 2 2006.257.03:17:21.97#ibcon#about to read 3, iclass 40, count 2 2006.257.03:17:21.99#ibcon#read 3, iclass 40, count 2 2006.257.03:17:21.99#ibcon#about to read 4, iclass 40, count 2 2006.257.03:17:21.99#ibcon#read 4, iclass 40, count 2 2006.257.03:17:21.99#ibcon#about to read 5, iclass 40, count 2 2006.257.03:17:21.99#ibcon#read 5, iclass 40, count 2 2006.257.03:17:21.99#ibcon#about to read 6, iclass 40, count 2 2006.257.03:17:21.99#ibcon#read 6, iclass 40, count 2 2006.257.03:17:21.99#ibcon#end of sib2, iclass 40, count 2 2006.257.03:17:21.99#ibcon#*mode == 0, iclass 40, count 2 2006.257.03:17:21.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.03:17:21.99#ibcon#[27=AT05-04\r\n] 2006.257.03:17:21.99#ibcon#*before write, iclass 40, count 2 2006.257.03:17:21.99#ibcon#enter sib2, iclass 40, count 2 2006.257.03:17:21.99#ibcon#flushed, iclass 40, count 2 2006.257.03:17:21.99#ibcon#about to write, iclass 40, count 2 2006.257.03:17:21.99#ibcon#wrote, iclass 40, count 2 2006.257.03:17:21.99#ibcon#about to read 3, iclass 40, count 2 2006.257.03:17:22.02#ibcon#read 3, iclass 40, count 2 2006.257.03:17:22.02#ibcon#about to read 4, iclass 40, count 2 2006.257.03:17:22.02#ibcon#read 4, iclass 40, count 2 2006.257.03:17:22.02#ibcon#about to read 5, iclass 40, count 2 2006.257.03:17:22.02#ibcon#read 5, iclass 40, count 2 2006.257.03:17:22.02#ibcon#about to read 6, iclass 40, count 2 2006.257.03:17:22.02#ibcon#read 6, iclass 40, count 2 2006.257.03:17:22.02#ibcon#end of sib2, iclass 40, count 2 2006.257.03:17:22.02#ibcon#*after write, iclass 40, count 2 2006.257.03:17:22.02#ibcon#*before return 0, iclass 40, count 2 2006.257.03:17:22.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:22.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:17:22.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.03:17:22.02#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:22.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:22.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:22.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:22.14#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:17:22.14#ibcon#first serial, iclass 40, count 0 2006.257.03:17:22.14#ibcon#enter sib2, iclass 40, count 0 2006.257.03:17:22.14#ibcon#flushed, iclass 40, count 0 2006.257.03:17:22.14#ibcon#about to write, iclass 40, count 0 2006.257.03:17:22.14#ibcon#wrote, iclass 40, count 0 2006.257.03:17:22.14#ibcon#about to read 3, iclass 40, count 0 2006.257.03:17:22.16#ibcon#read 3, iclass 40, count 0 2006.257.03:17:22.16#ibcon#about to read 4, iclass 40, count 0 2006.257.03:17:22.16#ibcon#read 4, iclass 40, count 0 2006.257.03:17:22.16#ibcon#about to read 5, iclass 40, count 0 2006.257.03:17:22.16#ibcon#read 5, iclass 40, count 0 2006.257.03:17:22.16#ibcon#about to read 6, iclass 40, count 0 2006.257.03:17:22.16#ibcon#read 6, iclass 40, count 0 2006.257.03:17:22.16#ibcon#end of sib2, iclass 40, count 0 2006.257.03:17:22.16#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:17:22.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:17:22.16#ibcon#[27=USB\r\n] 2006.257.03:17:22.16#ibcon#*before write, iclass 40, count 0 2006.257.03:17:22.16#ibcon#enter sib2, iclass 40, count 0 2006.257.03:17:22.16#ibcon#flushed, iclass 40, count 0 2006.257.03:17:22.16#ibcon#about to write, iclass 40, count 0 2006.257.03:17:22.16#ibcon#wrote, iclass 40, count 0 2006.257.03:17:22.16#ibcon#about to read 3, iclass 40, count 0 2006.257.03:17:22.19#ibcon#read 3, iclass 40, count 0 2006.257.03:17:22.19#ibcon#about to read 4, iclass 40, count 0 2006.257.03:17:22.19#ibcon#read 4, iclass 40, count 0 2006.257.03:17:22.19#ibcon#about to read 5, iclass 40, count 0 2006.257.03:17:22.19#ibcon#read 5, iclass 40, count 0 2006.257.03:17:22.19#ibcon#about to read 6, iclass 40, count 0 2006.257.03:17:22.19#ibcon#read 6, iclass 40, count 0 2006.257.03:17:22.19#ibcon#end of sib2, iclass 40, count 0 2006.257.03:17:22.19#ibcon#*after write, iclass 40, count 0 2006.257.03:17:22.19#ibcon#*before return 0, iclass 40, count 0 2006.257.03:17:22.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:22.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:17:22.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:17:22.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:17:22.19$vck44/vblo=6,719.99 2006.257.03:17:22.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.03:17:22.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.03:17:22.19#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:22.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:22.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:22.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:22.19#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:17:22.19#ibcon#first serial, iclass 4, count 0 2006.257.03:17:22.19#ibcon#enter sib2, iclass 4, count 0 2006.257.03:17:22.19#ibcon#flushed, iclass 4, count 0 2006.257.03:17:22.19#ibcon#about to write, iclass 4, count 0 2006.257.03:17:22.19#ibcon#wrote, iclass 4, count 0 2006.257.03:17:22.19#ibcon#about to read 3, iclass 4, count 0 2006.257.03:17:22.21#ibcon#read 3, iclass 4, count 0 2006.257.03:17:22.21#ibcon#about to read 4, iclass 4, count 0 2006.257.03:17:22.21#ibcon#read 4, iclass 4, count 0 2006.257.03:17:22.21#ibcon#about to read 5, iclass 4, count 0 2006.257.03:17:22.21#ibcon#read 5, iclass 4, count 0 2006.257.03:17:22.21#ibcon#about to read 6, iclass 4, count 0 2006.257.03:17:22.21#ibcon#read 6, iclass 4, count 0 2006.257.03:17:22.21#ibcon#end of sib2, iclass 4, count 0 2006.257.03:17:22.21#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:17:22.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:17:22.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:17:22.21#ibcon#*before write, iclass 4, count 0 2006.257.03:17:22.21#ibcon#enter sib2, iclass 4, count 0 2006.257.03:17:22.21#ibcon#flushed, iclass 4, count 0 2006.257.03:17:22.21#ibcon#about to write, iclass 4, count 0 2006.257.03:17:22.21#ibcon#wrote, iclass 4, count 0 2006.257.03:17:22.21#ibcon#about to read 3, iclass 4, count 0 2006.257.03:17:22.25#ibcon#read 3, iclass 4, count 0 2006.257.03:17:22.25#ibcon#about to read 4, iclass 4, count 0 2006.257.03:17:22.25#ibcon#read 4, iclass 4, count 0 2006.257.03:17:22.25#ibcon#about to read 5, iclass 4, count 0 2006.257.03:17:22.25#ibcon#read 5, iclass 4, count 0 2006.257.03:17:22.25#ibcon#about to read 6, iclass 4, count 0 2006.257.03:17:22.25#ibcon#read 6, iclass 4, count 0 2006.257.03:17:22.25#ibcon#end of sib2, iclass 4, count 0 2006.257.03:17:22.25#ibcon#*after write, iclass 4, count 0 2006.257.03:17:22.25#ibcon#*before return 0, iclass 4, count 0 2006.257.03:17:22.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:22.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:17:22.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:17:22.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:17:22.25$vck44/vb=6,4 2006.257.03:17:22.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.03:17:22.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.03:17:22.25#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:22.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:22.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:22.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:22.31#ibcon#enter wrdev, iclass 6, count 2 2006.257.03:17:22.31#ibcon#first serial, iclass 6, count 2 2006.257.03:17:22.31#ibcon#enter sib2, iclass 6, count 2 2006.257.03:17:22.31#ibcon#flushed, iclass 6, count 2 2006.257.03:17:22.31#ibcon#about to write, iclass 6, count 2 2006.257.03:17:22.31#ibcon#wrote, iclass 6, count 2 2006.257.03:17:22.31#ibcon#about to read 3, iclass 6, count 2 2006.257.03:17:22.33#ibcon#read 3, iclass 6, count 2 2006.257.03:17:22.33#ibcon#about to read 4, iclass 6, count 2 2006.257.03:17:22.33#ibcon#read 4, iclass 6, count 2 2006.257.03:17:22.33#ibcon#about to read 5, iclass 6, count 2 2006.257.03:17:22.33#ibcon#read 5, iclass 6, count 2 2006.257.03:17:22.33#ibcon#about to read 6, iclass 6, count 2 2006.257.03:17:22.33#ibcon#read 6, iclass 6, count 2 2006.257.03:17:22.33#ibcon#end of sib2, iclass 6, count 2 2006.257.03:17:22.33#ibcon#*mode == 0, iclass 6, count 2 2006.257.03:17:22.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.03:17:22.33#ibcon#[27=AT06-04\r\n] 2006.257.03:17:22.33#ibcon#*before write, iclass 6, count 2 2006.257.03:17:22.33#ibcon#enter sib2, iclass 6, count 2 2006.257.03:17:22.33#ibcon#flushed, iclass 6, count 2 2006.257.03:17:22.33#ibcon#about to write, iclass 6, count 2 2006.257.03:17:22.33#ibcon#wrote, iclass 6, count 2 2006.257.03:17:22.33#ibcon#about to read 3, iclass 6, count 2 2006.257.03:17:22.36#ibcon#read 3, iclass 6, count 2 2006.257.03:17:22.36#ibcon#about to read 4, iclass 6, count 2 2006.257.03:17:22.36#ibcon#read 4, iclass 6, count 2 2006.257.03:17:22.36#ibcon#about to read 5, iclass 6, count 2 2006.257.03:17:22.36#ibcon#read 5, iclass 6, count 2 2006.257.03:17:22.36#ibcon#about to read 6, iclass 6, count 2 2006.257.03:17:22.36#ibcon#read 6, iclass 6, count 2 2006.257.03:17:22.36#ibcon#end of sib2, iclass 6, count 2 2006.257.03:17:22.36#ibcon#*after write, iclass 6, count 2 2006.257.03:17:22.36#ibcon#*before return 0, iclass 6, count 2 2006.257.03:17:22.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:22.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:17:22.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.03:17:22.36#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:22.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:22.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:22.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:22.48#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:17:22.48#ibcon#first serial, iclass 6, count 0 2006.257.03:17:22.48#ibcon#enter sib2, iclass 6, count 0 2006.257.03:17:22.48#ibcon#flushed, iclass 6, count 0 2006.257.03:17:22.48#ibcon#about to write, iclass 6, count 0 2006.257.03:17:22.48#ibcon#wrote, iclass 6, count 0 2006.257.03:17:22.48#ibcon#about to read 3, iclass 6, count 0 2006.257.03:17:22.50#ibcon#read 3, iclass 6, count 0 2006.257.03:17:22.50#ibcon#about to read 4, iclass 6, count 0 2006.257.03:17:22.50#ibcon#read 4, iclass 6, count 0 2006.257.03:17:22.50#ibcon#about to read 5, iclass 6, count 0 2006.257.03:17:22.50#ibcon#read 5, iclass 6, count 0 2006.257.03:17:22.50#ibcon#about to read 6, iclass 6, count 0 2006.257.03:17:22.50#ibcon#read 6, iclass 6, count 0 2006.257.03:17:22.50#ibcon#end of sib2, iclass 6, count 0 2006.257.03:17:22.50#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:17:22.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:17:22.50#ibcon#[27=USB\r\n] 2006.257.03:17:22.50#ibcon#*before write, iclass 6, count 0 2006.257.03:17:22.50#ibcon#enter sib2, iclass 6, count 0 2006.257.03:17:22.50#ibcon#flushed, iclass 6, count 0 2006.257.03:17:22.50#ibcon#about to write, iclass 6, count 0 2006.257.03:17:22.50#ibcon#wrote, iclass 6, count 0 2006.257.03:17:22.50#ibcon#about to read 3, iclass 6, count 0 2006.257.03:17:22.53#ibcon#read 3, iclass 6, count 0 2006.257.03:17:22.53#ibcon#about to read 4, iclass 6, count 0 2006.257.03:17:22.53#ibcon#read 4, iclass 6, count 0 2006.257.03:17:22.53#ibcon#about to read 5, iclass 6, count 0 2006.257.03:17:22.53#ibcon#read 5, iclass 6, count 0 2006.257.03:17:22.53#ibcon#about to read 6, iclass 6, count 0 2006.257.03:17:22.53#ibcon#read 6, iclass 6, count 0 2006.257.03:17:22.53#ibcon#end of sib2, iclass 6, count 0 2006.257.03:17:22.53#ibcon#*after write, iclass 6, count 0 2006.257.03:17:22.53#ibcon#*before return 0, iclass 6, count 0 2006.257.03:17:22.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:22.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:17:22.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:17:22.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:17:22.53$vck44/vblo=7,734.99 2006.257.03:17:22.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.03:17:22.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.03:17:22.53#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:22.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:22.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:22.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:22.53#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:17:22.53#ibcon#first serial, iclass 10, count 0 2006.257.03:17:22.53#ibcon#enter sib2, iclass 10, count 0 2006.257.03:17:22.53#ibcon#flushed, iclass 10, count 0 2006.257.03:17:22.53#ibcon#about to write, iclass 10, count 0 2006.257.03:17:22.53#ibcon#wrote, iclass 10, count 0 2006.257.03:17:22.53#ibcon#about to read 3, iclass 10, count 0 2006.257.03:17:22.55#ibcon#read 3, iclass 10, count 0 2006.257.03:17:22.55#ibcon#about to read 4, iclass 10, count 0 2006.257.03:17:22.55#ibcon#read 4, iclass 10, count 0 2006.257.03:17:22.55#ibcon#about to read 5, iclass 10, count 0 2006.257.03:17:22.55#ibcon#read 5, iclass 10, count 0 2006.257.03:17:22.55#ibcon#about to read 6, iclass 10, count 0 2006.257.03:17:22.55#ibcon#read 6, iclass 10, count 0 2006.257.03:17:22.55#ibcon#end of sib2, iclass 10, count 0 2006.257.03:17:22.55#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:17:22.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:17:22.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:17:22.55#ibcon#*before write, iclass 10, count 0 2006.257.03:17:22.55#ibcon#enter sib2, iclass 10, count 0 2006.257.03:17:22.55#ibcon#flushed, iclass 10, count 0 2006.257.03:17:22.55#ibcon#about to write, iclass 10, count 0 2006.257.03:17:22.55#ibcon#wrote, iclass 10, count 0 2006.257.03:17:22.55#ibcon#about to read 3, iclass 10, count 0 2006.257.03:17:22.59#ibcon#read 3, iclass 10, count 0 2006.257.03:17:22.59#ibcon#about to read 4, iclass 10, count 0 2006.257.03:17:22.59#ibcon#read 4, iclass 10, count 0 2006.257.03:17:22.59#ibcon#about to read 5, iclass 10, count 0 2006.257.03:17:22.59#ibcon#read 5, iclass 10, count 0 2006.257.03:17:22.59#ibcon#about to read 6, iclass 10, count 0 2006.257.03:17:22.59#ibcon#read 6, iclass 10, count 0 2006.257.03:17:22.59#ibcon#end of sib2, iclass 10, count 0 2006.257.03:17:22.59#ibcon#*after write, iclass 10, count 0 2006.257.03:17:22.59#ibcon#*before return 0, iclass 10, count 0 2006.257.03:17:22.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:22.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:17:22.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:17:22.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:17:22.59$vck44/vb=7,4 2006.257.03:17:22.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.03:17:22.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.03:17:22.59#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:22.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:22.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:22.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:22.65#ibcon#enter wrdev, iclass 12, count 2 2006.257.03:17:22.65#ibcon#first serial, iclass 12, count 2 2006.257.03:17:22.65#ibcon#enter sib2, iclass 12, count 2 2006.257.03:17:22.65#ibcon#flushed, iclass 12, count 2 2006.257.03:17:22.65#ibcon#about to write, iclass 12, count 2 2006.257.03:17:22.65#ibcon#wrote, iclass 12, count 2 2006.257.03:17:22.65#ibcon#about to read 3, iclass 12, count 2 2006.257.03:17:22.67#ibcon#read 3, iclass 12, count 2 2006.257.03:17:22.67#ibcon#about to read 4, iclass 12, count 2 2006.257.03:17:22.67#ibcon#read 4, iclass 12, count 2 2006.257.03:17:22.67#ibcon#about to read 5, iclass 12, count 2 2006.257.03:17:22.67#ibcon#read 5, iclass 12, count 2 2006.257.03:17:22.67#ibcon#about to read 6, iclass 12, count 2 2006.257.03:17:22.67#ibcon#read 6, iclass 12, count 2 2006.257.03:17:22.67#ibcon#end of sib2, iclass 12, count 2 2006.257.03:17:22.67#ibcon#*mode == 0, iclass 12, count 2 2006.257.03:17:22.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.03:17:22.67#ibcon#[27=AT07-04\r\n] 2006.257.03:17:22.67#ibcon#*before write, iclass 12, count 2 2006.257.03:17:22.67#ibcon#enter sib2, iclass 12, count 2 2006.257.03:17:22.67#ibcon#flushed, iclass 12, count 2 2006.257.03:17:22.67#ibcon#about to write, iclass 12, count 2 2006.257.03:17:22.67#ibcon#wrote, iclass 12, count 2 2006.257.03:17:22.67#ibcon#about to read 3, iclass 12, count 2 2006.257.03:17:22.70#ibcon#read 3, iclass 12, count 2 2006.257.03:17:22.70#ibcon#about to read 4, iclass 12, count 2 2006.257.03:17:22.70#ibcon#read 4, iclass 12, count 2 2006.257.03:17:22.70#ibcon#about to read 5, iclass 12, count 2 2006.257.03:17:22.70#ibcon#read 5, iclass 12, count 2 2006.257.03:17:22.70#ibcon#about to read 6, iclass 12, count 2 2006.257.03:17:22.70#ibcon#read 6, iclass 12, count 2 2006.257.03:17:22.70#ibcon#end of sib2, iclass 12, count 2 2006.257.03:17:22.70#ibcon#*after write, iclass 12, count 2 2006.257.03:17:22.70#ibcon#*before return 0, iclass 12, count 2 2006.257.03:17:22.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:22.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:17:22.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.03:17:22.70#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:22.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:22.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:22.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:22.82#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:17:22.82#ibcon#first serial, iclass 12, count 0 2006.257.03:17:22.82#ibcon#enter sib2, iclass 12, count 0 2006.257.03:17:22.82#ibcon#flushed, iclass 12, count 0 2006.257.03:17:22.82#ibcon#about to write, iclass 12, count 0 2006.257.03:17:22.82#ibcon#wrote, iclass 12, count 0 2006.257.03:17:22.82#ibcon#about to read 3, iclass 12, count 0 2006.257.03:17:22.84#ibcon#read 3, iclass 12, count 0 2006.257.03:17:22.84#ibcon#about to read 4, iclass 12, count 0 2006.257.03:17:22.84#ibcon#read 4, iclass 12, count 0 2006.257.03:17:22.84#ibcon#about to read 5, iclass 12, count 0 2006.257.03:17:22.84#ibcon#read 5, iclass 12, count 0 2006.257.03:17:22.84#ibcon#about to read 6, iclass 12, count 0 2006.257.03:17:22.84#ibcon#read 6, iclass 12, count 0 2006.257.03:17:22.84#ibcon#end of sib2, iclass 12, count 0 2006.257.03:17:22.84#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:17:22.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:17:22.84#ibcon#[27=USB\r\n] 2006.257.03:17:22.84#ibcon#*before write, iclass 12, count 0 2006.257.03:17:22.84#ibcon#enter sib2, iclass 12, count 0 2006.257.03:17:22.84#ibcon#flushed, iclass 12, count 0 2006.257.03:17:22.84#ibcon#about to write, iclass 12, count 0 2006.257.03:17:22.84#ibcon#wrote, iclass 12, count 0 2006.257.03:17:22.84#ibcon#about to read 3, iclass 12, count 0 2006.257.03:17:22.87#ibcon#read 3, iclass 12, count 0 2006.257.03:17:22.87#ibcon#about to read 4, iclass 12, count 0 2006.257.03:17:22.87#ibcon#read 4, iclass 12, count 0 2006.257.03:17:22.87#ibcon#about to read 5, iclass 12, count 0 2006.257.03:17:22.87#ibcon#read 5, iclass 12, count 0 2006.257.03:17:22.87#ibcon#about to read 6, iclass 12, count 0 2006.257.03:17:22.87#ibcon#read 6, iclass 12, count 0 2006.257.03:17:22.87#ibcon#end of sib2, iclass 12, count 0 2006.257.03:17:22.87#ibcon#*after write, iclass 12, count 0 2006.257.03:17:22.87#ibcon#*before return 0, iclass 12, count 0 2006.257.03:17:22.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:22.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:17:22.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:17:22.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:17:22.87$vck44/vblo=8,744.99 2006.257.03:17:22.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.03:17:22.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.03:17:22.87#ibcon#ireg 17 cls_cnt 0 2006.257.03:17:22.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:17:22.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:17:22.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:17:22.87#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:17:22.87#ibcon#first serial, iclass 14, count 0 2006.257.03:17:22.87#ibcon#enter sib2, iclass 14, count 0 2006.257.03:17:22.87#ibcon#flushed, iclass 14, count 0 2006.257.03:17:22.87#ibcon#about to write, iclass 14, count 0 2006.257.03:17:22.87#ibcon#wrote, iclass 14, count 0 2006.257.03:17:22.87#ibcon#about to read 3, iclass 14, count 0 2006.257.03:17:22.89#ibcon#read 3, iclass 14, count 0 2006.257.03:17:22.89#ibcon#about to read 4, iclass 14, count 0 2006.257.03:17:22.89#ibcon#read 4, iclass 14, count 0 2006.257.03:17:22.89#ibcon#about to read 5, iclass 14, count 0 2006.257.03:17:22.89#ibcon#read 5, iclass 14, count 0 2006.257.03:17:22.89#ibcon#about to read 6, iclass 14, count 0 2006.257.03:17:22.89#ibcon#read 6, iclass 14, count 0 2006.257.03:17:22.89#ibcon#end of sib2, iclass 14, count 0 2006.257.03:17:22.89#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:17:22.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:17:22.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:17:22.89#ibcon#*before write, iclass 14, count 0 2006.257.03:17:22.89#ibcon#enter sib2, iclass 14, count 0 2006.257.03:17:22.89#ibcon#flushed, iclass 14, count 0 2006.257.03:17:22.89#ibcon#about to write, iclass 14, count 0 2006.257.03:17:22.89#ibcon#wrote, iclass 14, count 0 2006.257.03:17:22.89#ibcon#about to read 3, iclass 14, count 0 2006.257.03:17:22.93#ibcon#read 3, iclass 14, count 0 2006.257.03:17:22.93#ibcon#about to read 4, iclass 14, count 0 2006.257.03:17:22.93#ibcon#read 4, iclass 14, count 0 2006.257.03:17:22.93#ibcon#about to read 5, iclass 14, count 0 2006.257.03:17:22.93#ibcon#read 5, iclass 14, count 0 2006.257.03:17:22.93#ibcon#about to read 6, iclass 14, count 0 2006.257.03:17:22.93#ibcon#read 6, iclass 14, count 0 2006.257.03:17:22.93#ibcon#end of sib2, iclass 14, count 0 2006.257.03:17:22.93#ibcon#*after write, iclass 14, count 0 2006.257.03:17:22.93#ibcon#*before return 0, iclass 14, count 0 2006.257.03:17:22.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:17:22.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:17:22.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:17:22.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:17:22.93$vck44/vb=8,4 2006.257.03:17:22.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.03:17:22.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.03:17:22.93#ibcon#ireg 11 cls_cnt 2 2006.257.03:17:22.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:17:22.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:17:22.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:17:22.99#ibcon#enter wrdev, iclass 16, count 2 2006.257.03:17:22.99#ibcon#first serial, iclass 16, count 2 2006.257.03:17:22.99#ibcon#enter sib2, iclass 16, count 2 2006.257.03:17:22.99#ibcon#flushed, iclass 16, count 2 2006.257.03:17:22.99#ibcon#about to write, iclass 16, count 2 2006.257.03:17:22.99#ibcon#wrote, iclass 16, count 2 2006.257.03:17:22.99#ibcon#about to read 3, iclass 16, count 2 2006.257.03:17:23.01#ibcon#read 3, iclass 16, count 2 2006.257.03:17:23.01#ibcon#about to read 4, iclass 16, count 2 2006.257.03:17:23.01#ibcon#read 4, iclass 16, count 2 2006.257.03:17:23.01#ibcon#about to read 5, iclass 16, count 2 2006.257.03:17:23.01#ibcon#read 5, iclass 16, count 2 2006.257.03:17:23.01#ibcon#about to read 6, iclass 16, count 2 2006.257.03:17:23.01#ibcon#read 6, iclass 16, count 2 2006.257.03:17:23.01#ibcon#end of sib2, iclass 16, count 2 2006.257.03:17:23.01#ibcon#*mode == 0, iclass 16, count 2 2006.257.03:17:23.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.03:17:23.01#ibcon#[27=AT08-04\r\n] 2006.257.03:17:23.01#ibcon#*before write, iclass 16, count 2 2006.257.03:17:23.01#ibcon#enter sib2, iclass 16, count 2 2006.257.03:17:23.01#ibcon#flushed, iclass 16, count 2 2006.257.03:17:23.01#ibcon#about to write, iclass 16, count 2 2006.257.03:17:23.01#ibcon#wrote, iclass 16, count 2 2006.257.03:17:23.01#ibcon#about to read 3, iclass 16, count 2 2006.257.03:17:23.04#ibcon#read 3, iclass 16, count 2 2006.257.03:17:23.04#ibcon#about to read 4, iclass 16, count 2 2006.257.03:17:23.04#ibcon#read 4, iclass 16, count 2 2006.257.03:17:23.04#ibcon#about to read 5, iclass 16, count 2 2006.257.03:17:23.04#ibcon#read 5, iclass 16, count 2 2006.257.03:17:23.04#ibcon#about to read 6, iclass 16, count 2 2006.257.03:17:23.04#ibcon#read 6, iclass 16, count 2 2006.257.03:17:23.04#ibcon#end of sib2, iclass 16, count 2 2006.257.03:17:23.04#ibcon#*after write, iclass 16, count 2 2006.257.03:17:23.04#ibcon#*before return 0, iclass 16, count 2 2006.257.03:17:23.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:17:23.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:17:23.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.03:17:23.04#ibcon#ireg 7 cls_cnt 0 2006.257.03:17:23.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:17:23.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:17:23.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:17:23.16#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:17:23.16#ibcon#first serial, iclass 16, count 0 2006.257.03:17:23.16#ibcon#enter sib2, iclass 16, count 0 2006.257.03:17:23.16#ibcon#flushed, iclass 16, count 0 2006.257.03:17:23.16#ibcon#about to write, iclass 16, count 0 2006.257.03:17:23.16#ibcon#wrote, iclass 16, count 0 2006.257.03:17:23.16#ibcon#about to read 3, iclass 16, count 0 2006.257.03:17:23.18#ibcon#read 3, iclass 16, count 0 2006.257.03:17:23.18#ibcon#about to read 4, iclass 16, count 0 2006.257.03:17:23.18#ibcon#read 4, iclass 16, count 0 2006.257.03:17:23.18#ibcon#about to read 5, iclass 16, count 0 2006.257.03:17:23.18#ibcon#read 5, iclass 16, count 0 2006.257.03:17:23.18#ibcon#about to read 6, iclass 16, count 0 2006.257.03:17:23.18#ibcon#read 6, iclass 16, count 0 2006.257.03:17:23.18#ibcon#end of sib2, iclass 16, count 0 2006.257.03:17:23.18#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:17:23.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:17:23.18#ibcon#[27=USB\r\n] 2006.257.03:17:23.18#ibcon#*before write, iclass 16, count 0 2006.257.03:17:23.18#ibcon#enter sib2, iclass 16, count 0 2006.257.03:17:23.18#ibcon#flushed, iclass 16, count 0 2006.257.03:17:23.18#ibcon#about to write, iclass 16, count 0 2006.257.03:17:23.18#ibcon#wrote, iclass 16, count 0 2006.257.03:17:23.18#ibcon#about to read 3, iclass 16, count 0 2006.257.03:17:23.21#ibcon#read 3, iclass 16, count 0 2006.257.03:17:23.21#ibcon#about to read 4, iclass 16, count 0 2006.257.03:17:23.21#ibcon#read 4, iclass 16, count 0 2006.257.03:17:23.21#ibcon#about to read 5, iclass 16, count 0 2006.257.03:17:23.21#ibcon#read 5, iclass 16, count 0 2006.257.03:17:23.21#ibcon#about to read 6, iclass 16, count 0 2006.257.03:17:23.21#ibcon#read 6, iclass 16, count 0 2006.257.03:17:23.21#ibcon#end of sib2, iclass 16, count 0 2006.257.03:17:23.21#ibcon#*after write, iclass 16, count 0 2006.257.03:17:23.21#ibcon#*before return 0, iclass 16, count 0 2006.257.03:17:23.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:17:23.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:17:23.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:17:23.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:17:23.21$vck44/vabw=wide 2006.257.03:17:23.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.03:17:23.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.03:17:23.21#ibcon#ireg 8 cls_cnt 0 2006.257.03:17:23.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:23.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:23.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:23.21#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:17:23.21#ibcon#first serial, iclass 18, count 0 2006.257.03:17:23.21#ibcon#enter sib2, iclass 18, count 0 2006.257.03:17:23.21#ibcon#flushed, iclass 18, count 0 2006.257.03:17:23.21#ibcon#about to write, iclass 18, count 0 2006.257.03:17:23.21#ibcon#wrote, iclass 18, count 0 2006.257.03:17:23.21#ibcon#about to read 3, iclass 18, count 0 2006.257.03:17:23.23#ibcon#read 3, iclass 18, count 0 2006.257.03:17:23.23#ibcon#about to read 4, iclass 18, count 0 2006.257.03:17:23.23#ibcon#read 4, iclass 18, count 0 2006.257.03:17:23.23#ibcon#about to read 5, iclass 18, count 0 2006.257.03:17:23.23#ibcon#read 5, iclass 18, count 0 2006.257.03:17:23.23#ibcon#about to read 6, iclass 18, count 0 2006.257.03:17:23.23#ibcon#read 6, iclass 18, count 0 2006.257.03:17:23.23#ibcon#end of sib2, iclass 18, count 0 2006.257.03:17:23.23#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:17:23.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:17:23.23#ibcon#[25=BW32\r\n] 2006.257.03:17:23.23#ibcon#*before write, iclass 18, count 0 2006.257.03:17:23.23#ibcon#enter sib2, iclass 18, count 0 2006.257.03:17:23.23#ibcon#flushed, iclass 18, count 0 2006.257.03:17:23.23#ibcon#about to write, iclass 18, count 0 2006.257.03:17:23.23#ibcon#wrote, iclass 18, count 0 2006.257.03:17:23.23#ibcon#about to read 3, iclass 18, count 0 2006.257.03:17:23.26#ibcon#read 3, iclass 18, count 0 2006.257.03:17:23.26#ibcon#about to read 4, iclass 18, count 0 2006.257.03:17:23.26#ibcon#read 4, iclass 18, count 0 2006.257.03:17:23.26#ibcon#about to read 5, iclass 18, count 0 2006.257.03:17:23.26#ibcon#read 5, iclass 18, count 0 2006.257.03:17:23.26#ibcon#about to read 6, iclass 18, count 0 2006.257.03:17:23.26#ibcon#read 6, iclass 18, count 0 2006.257.03:17:23.26#ibcon#end of sib2, iclass 18, count 0 2006.257.03:17:23.26#ibcon#*after write, iclass 18, count 0 2006.257.03:17:23.26#ibcon#*before return 0, iclass 18, count 0 2006.257.03:17:23.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:23.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:17:23.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:17:23.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:17:23.26$vck44/vbbw=wide 2006.257.03:17:23.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.03:17:23.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.03:17:23.26#ibcon#ireg 8 cls_cnt 0 2006.257.03:17:23.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:17:23.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:17:23.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:17:23.33#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:17:23.33#ibcon#first serial, iclass 20, count 0 2006.257.03:17:23.33#ibcon#enter sib2, iclass 20, count 0 2006.257.03:17:23.33#ibcon#flushed, iclass 20, count 0 2006.257.03:17:23.33#ibcon#about to write, iclass 20, count 0 2006.257.03:17:23.33#ibcon#wrote, iclass 20, count 0 2006.257.03:17:23.33#ibcon#about to read 3, iclass 20, count 0 2006.257.03:17:23.35#ibcon#read 3, iclass 20, count 0 2006.257.03:17:23.35#ibcon#about to read 4, iclass 20, count 0 2006.257.03:17:23.35#ibcon#read 4, iclass 20, count 0 2006.257.03:17:23.35#ibcon#about to read 5, iclass 20, count 0 2006.257.03:17:23.35#ibcon#read 5, iclass 20, count 0 2006.257.03:17:23.35#ibcon#about to read 6, iclass 20, count 0 2006.257.03:17:23.35#ibcon#read 6, iclass 20, count 0 2006.257.03:17:23.35#ibcon#end of sib2, iclass 20, count 0 2006.257.03:17:23.35#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:17:23.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:17:23.35#ibcon#[27=BW32\r\n] 2006.257.03:17:23.35#ibcon#*before write, iclass 20, count 0 2006.257.03:17:23.35#ibcon#enter sib2, iclass 20, count 0 2006.257.03:17:23.35#ibcon#flushed, iclass 20, count 0 2006.257.03:17:23.35#ibcon#about to write, iclass 20, count 0 2006.257.03:17:23.35#ibcon#wrote, iclass 20, count 0 2006.257.03:17:23.35#ibcon#about to read 3, iclass 20, count 0 2006.257.03:17:23.38#ibcon#read 3, iclass 20, count 0 2006.257.03:17:23.38#ibcon#about to read 4, iclass 20, count 0 2006.257.03:17:23.38#ibcon#read 4, iclass 20, count 0 2006.257.03:17:23.38#ibcon#about to read 5, iclass 20, count 0 2006.257.03:17:23.38#ibcon#read 5, iclass 20, count 0 2006.257.03:17:23.38#ibcon#about to read 6, iclass 20, count 0 2006.257.03:17:23.38#ibcon#read 6, iclass 20, count 0 2006.257.03:17:23.38#ibcon#end of sib2, iclass 20, count 0 2006.257.03:17:23.38#ibcon#*after write, iclass 20, count 0 2006.257.03:17:23.38#ibcon#*before return 0, iclass 20, count 0 2006.257.03:17:23.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:17:23.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:17:23.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:17:23.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:17:23.38$setupk4/ifdk4 2006.257.03:17:23.38$ifdk4/lo= 2006.257.03:17:23.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:17:23.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:17:23.38$ifdk4/patch= 2006.257.03:17:23.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:17:23.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:17:23.38$setupk4/!*+20s 2006.257.03:17:30.28#abcon#<5=/14 1.9 6.0 19.03 961012.2\r\n> 2006.257.03:17:30.30#abcon#{5=INTERFACE CLEAR} 2006.257.03:17:30.36#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:17:34.14#trakl#Source acquired 2006.257.03:17:34.14#flagr#flagr/antenna,acquired 2006.257.03:17:37.88$setupk4/"tpicd 2006.257.03:17:37.88$setupk4/echo=off 2006.257.03:17:37.88$setupk4/xlog=off 2006.257.03:17:37.88:!2006.257.03:20:35 2006.257.03:20:35.00:preob 2006.257.03:20:35.14/onsource/TRACKING 2006.257.03:20:35.14:!2006.257.03:20:45 2006.257.03:20:45.00:"tape 2006.257.03:20:45.00:"st=record 2006.257.03:20:45.00:data_valid=on 2006.257.03:20:45.00:midob 2006.257.03:20:46.14/onsource/TRACKING 2006.257.03:20:46.14/wx/19.06,1012.1,96 2006.257.03:20:46.32/cable/+6.4850E-03 2006.257.03:20:47.41/va/01,08,usb,yes,31,34 2006.257.03:20:47.41/va/02,07,usb,yes,34,34 2006.257.03:20:47.41/va/03,08,usb,yes,30,32 2006.257.03:20:47.41/va/04,07,usb,yes,35,37 2006.257.03:20:47.41/va/05,04,usb,yes,31,32 2006.257.03:20:47.41/va/06,04,usb,yes,35,34 2006.257.03:20:47.41/va/07,04,usb,yes,36,36 2006.257.03:20:47.41/va/08,04,usb,yes,30,37 2006.257.03:20:47.64/valo/01,524.99,yes,locked 2006.257.03:20:47.64/valo/02,534.99,yes,locked 2006.257.03:20:47.64/valo/03,564.99,yes,locked 2006.257.03:20:47.64/valo/04,624.99,yes,locked 2006.257.03:20:47.64/valo/05,734.99,yes,locked 2006.257.03:20:47.64/valo/06,814.99,yes,locked 2006.257.03:20:47.64/valo/07,864.99,yes,locked 2006.257.03:20:47.64/valo/08,884.99,yes,locked 2006.257.03:20:48.73/vb/01,04,usb,yes,30,28 2006.257.03:20:48.73/vb/02,05,usb,yes,29,29 2006.257.03:20:48.73/vb/03,04,usb,yes,30,33 2006.257.03:20:48.73/vb/04,05,usb,yes,30,29 2006.257.03:20:48.73/vb/05,04,usb,yes,27,29 2006.257.03:20:48.73/vb/06,04,usb,yes,31,27 2006.257.03:20:48.73/vb/07,04,usb,yes,31,31 2006.257.03:20:48.73/vb/08,04,usb,yes,28,31 2006.257.03:20:48.96/vblo/01,629.99,yes,locked 2006.257.03:20:48.96/vblo/02,634.99,yes,locked 2006.257.03:20:48.96/vblo/03,649.99,yes,locked 2006.257.03:20:48.96/vblo/04,679.99,yes,locked 2006.257.03:20:48.96/vblo/05,709.99,yes,locked 2006.257.03:20:48.96/vblo/06,719.99,yes,locked 2006.257.03:20:48.96/vblo/07,734.99,yes,locked 2006.257.03:20:48.96/vblo/08,744.99,yes,locked 2006.257.03:20:49.11/vabw/8 2006.257.03:20:49.26/vbbw/8 2006.257.03:20:49.40/xfe/off,on,16.0 2006.257.03:20:49.78/ifatt/23,28,28,28 2006.257.03:20:50.07/fmout-gps/S +4.55E-07 2006.257.03:20:50.11:!2006.257.03:24:25 2006.257.03:24:25.00:data_valid=off 2006.257.03:24:25.00:"et 2006.257.03:24:25.00:!+3s 2006.257.03:24:28.01:"tape 2006.257.03:24:28.01:postob 2006.257.03:24:28.08/cable/+6.4835E-03 2006.257.03:24:28.08/wx/19.11,1012.0,96 2006.257.03:24:29.07/fmout-gps/S +4.57E-07 2006.257.03:24:29.07:scan_name=257-0327,jd0609,60 2006.257.03:24:29.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.03:24:30.14:checkk5 2006.257.03:24:30.14#flagr#flagr/antenna,new-source 2006.257.03:24:30.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:24:30.85/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:24:31.21/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:24:31.55/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:24:31.90/chk_obsdata//k5ts1/T2570320??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.03:24:32.25/chk_obsdata//k5ts2/T2570320??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.03:24:32.62/chk_obsdata//k5ts3/T2570320??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.03:24:32.97/chk_obsdata//k5ts4/T2570320??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.03:24:33.64/k5log//k5ts1_log_newline 2006.257.03:24:34.32/k5log//k5ts2_log_newline 2006.257.03:24:35.02/k5log//k5ts3_log_newline 2006.257.03:24:35.68/k5log//k5ts4_log_newline 2006.257.03:24:35.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:24:35.70:setupk4=1 2006.257.03:24:35.70$setupk4/echo=on 2006.257.03:24:35.70$setupk4/pcalon 2006.257.03:24:35.70$pcalon/"no phase cal control is implemented here 2006.257.03:24:35.70$setupk4/"tpicd=stop 2006.257.03:24:35.70$setupk4/"rec=synch_on 2006.257.03:24:35.70$setupk4/"rec_mode=128 2006.257.03:24:35.70$setupk4/!* 2006.257.03:24:35.70$setupk4/recpk4 2006.257.03:24:35.70$recpk4/recpatch= 2006.257.03:24:35.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:24:35.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:24:35.70$setupk4/vck44 2006.257.03:24:35.70$vck44/valo=1,524.99 2006.257.03:24:35.70#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.03:24:35.70#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.03:24:35.70#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:35.70#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:35.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:35.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:35.70#ibcon#enter wrdev, iclass 13, count 0 2006.257.03:24:35.70#ibcon#first serial, iclass 13, count 0 2006.257.03:24:35.70#ibcon#enter sib2, iclass 13, count 0 2006.257.03:24:35.71#ibcon#flushed, iclass 13, count 0 2006.257.03:24:35.71#ibcon#about to write, iclass 13, count 0 2006.257.03:24:35.71#ibcon#wrote, iclass 13, count 0 2006.257.03:24:35.71#ibcon#about to read 3, iclass 13, count 0 2006.257.03:24:35.72#ibcon#read 3, iclass 13, count 0 2006.257.03:24:35.72#ibcon#about to read 4, iclass 13, count 0 2006.257.03:24:35.72#ibcon#read 4, iclass 13, count 0 2006.257.03:24:35.72#ibcon#about to read 5, iclass 13, count 0 2006.257.03:24:35.72#ibcon#read 5, iclass 13, count 0 2006.257.03:24:35.72#ibcon#about to read 6, iclass 13, count 0 2006.257.03:24:35.72#ibcon#read 6, iclass 13, count 0 2006.257.03:24:35.72#ibcon#end of sib2, iclass 13, count 0 2006.257.03:24:35.72#ibcon#*mode == 0, iclass 13, count 0 2006.257.03:24:35.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.03:24:35.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:24:35.72#ibcon#*before write, iclass 13, count 0 2006.257.03:24:35.72#ibcon#enter sib2, iclass 13, count 0 2006.257.03:24:35.72#ibcon#flushed, iclass 13, count 0 2006.257.03:24:35.72#ibcon#about to write, iclass 13, count 0 2006.257.03:24:35.72#ibcon#wrote, iclass 13, count 0 2006.257.03:24:35.72#ibcon#about to read 3, iclass 13, count 0 2006.257.03:24:35.77#ibcon#read 3, iclass 13, count 0 2006.257.03:24:35.77#ibcon#about to read 4, iclass 13, count 0 2006.257.03:24:35.77#ibcon#read 4, iclass 13, count 0 2006.257.03:24:35.77#ibcon#about to read 5, iclass 13, count 0 2006.257.03:24:35.77#ibcon#read 5, iclass 13, count 0 2006.257.03:24:35.77#ibcon#about to read 6, iclass 13, count 0 2006.257.03:24:35.77#ibcon#read 6, iclass 13, count 0 2006.257.03:24:35.77#ibcon#end of sib2, iclass 13, count 0 2006.257.03:24:35.77#ibcon#*after write, iclass 13, count 0 2006.257.03:24:35.77#ibcon#*before return 0, iclass 13, count 0 2006.257.03:24:35.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:35.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:35.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.03:24:35.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.03:24:35.77$vck44/va=1,8 2006.257.03:24:35.77#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.03:24:35.77#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.03:24:35.77#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:35.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:35.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:35.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:35.77#ibcon#enter wrdev, iclass 15, count 2 2006.257.03:24:35.77#ibcon#first serial, iclass 15, count 2 2006.257.03:24:35.77#ibcon#enter sib2, iclass 15, count 2 2006.257.03:24:35.77#ibcon#flushed, iclass 15, count 2 2006.257.03:24:35.77#ibcon#about to write, iclass 15, count 2 2006.257.03:24:35.77#ibcon#wrote, iclass 15, count 2 2006.257.03:24:35.77#ibcon#about to read 3, iclass 15, count 2 2006.257.03:24:35.79#ibcon#read 3, iclass 15, count 2 2006.257.03:24:35.79#ibcon#about to read 4, iclass 15, count 2 2006.257.03:24:35.79#ibcon#read 4, iclass 15, count 2 2006.257.03:24:35.79#ibcon#about to read 5, iclass 15, count 2 2006.257.03:24:35.79#ibcon#read 5, iclass 15, count 2 2006.257.03:24:35.79#ibcon#about to read 6, iclass 15, count 2 2006.257.03:24:35.79#ibcon#read 6, iclass 15, count 2 2006.257.03:24:35.79#ibcon#end of sib2, iclass 15, count 2 2006.257.03:24:35.79#ibcon#*mode == 0, iclass 15, count 2 2006.257.03:24:35.79#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.03:24:35.79#ibcon#[25=AT01-08\r\n] 2006.257.03:24:35.79#ibcon#*before write, iclass 15, count 2 2006.257.03:24:35.79#ibcon#enter sib2, iclass 15, count 2 2006.257.03:24:35.79#ibcon#flushed, iclass 15, count 2 2006.257.03:24:35.79#ibcon#about to write, iclass 15, count 2 2006.257.03:24:35.79#ibcon#wrote, iclass 15, count 2 2006.257.03:24:35.79#ibcon#about to read 3, iclass 15, count 2 2006.257.03:24:35.82#ibcon#read 3, iclass 15, count 2 2006.257.03:24:35.82#ibcon#about to read 4, iclass 15, count 2 2006.257.03:24:35.82#ibcon#read 4, iclass 15, count 2 2006.257.03:24:35.82#ibcon#about to read 5, iclass 15, count 2 2006.257.03:24:35.82#ibcon#read 5, iclass 15, count 2 2006.257.03:24:35.82#ibcon#about to read 6, iclass 15, count 2 2006.257.03:24:35.82#ibcon#read 6, iclass 15, count 2 2006.257.03:24:35.82#ibcon#end of sib2, iclass 15, count 2 2006.257.03:24:35.82#ibcon#*after write, iclass 15, count 2 2006.257.03:24:35.82#ibcon#*before return 0, iclass 15, count 2 2006.257.03:24:35.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:35.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:35.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.03:24:35.82#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:35.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:35.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:35.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:35.94#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:24:35.94#ibcon#first serial, iclass 15, count 0 2006.257.03:24:35.94#ibcon#enter sib2, iclass 15, count 0 2006.257.03:24:35.94#ibcon#flushed, iclass 15, count 0 2006.257.03:24:35.94#ibcon#about to write, iclass 15, count 0 2006.257.03:24:35.94#ibcon#wrote, iclass 15, count 0 2006.257.03:24:35.94#ibcon#about to read 3, iclass 15, count 0 2006.257.03:24:35.96#ibcon#read 3, iclass 15, count 0 2006.257.03:24:35.96#ibcon#about to read 4, iclass 15, count 0 2006.257.03:24:35.96#ibcon#read 4, iclass 15, count 0 2006.257.03:24:35.96#ibcon#about to read 5, iclass 15, count 0 2006.257.03:24:35.96#ibcon#read 5, iclass 15, count 0 2006.257.03:24:35.96#ibcon#about to read 6, iclass 15, count 0 2006.257.03:24:35.96#ibcon#read 6, iclass 15, count 0 2006.257.03:24:35.96#ibcon#end of sib2, iclass 15, count 0 2006.257.03:24:35.96#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:24:35.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:24:35.96#ibcon#[25=USB\r\n] 2006.257.03:24:35.96#ibcon#*before write, iclass 15, count 0 2006.257.03:24:35.96#ibcon#enter sib2, iclass 15, count 0 2006.257.03:24:35.96#ibcon#flushed, iclass 15, count 0 2006.257.03:24:35.96#ibcon#about to write, iclass 15, count 0 2006.257.03:24:35.96#ibcon#wrote, iclass 15, count 0 2006.257.03:24:35.96#ibcon#about to read 3, iclass 15, count 0 2006.257.03:24:35.99#ibcon#read 3, iclass 15, count 0 2006.257.03:24:35.99#ibcon#about to read 4, iclass 15, count 0 2006.257.03:24:35.99#ibcon#read 4, iclass 15, count 0 2006.257.03:24:35.99#ibcon#about to read 5, iclass 15, count 0 2006.257.03:24:35.99#ibcon#read 5, iclass 15, count 0 2006.257.03:24:35.99#ibcon#about to read 6, iclass 15, count 0 2006.257.03:24:35.99#ibcon#read 6, iclass 15, count 0 2006.257.03:24:35.99#ibcon#end of sib2, iclass 15, count 0 2006.257.03:24:35.99#ibcon#*after write, iclass 15, count 0 2006.257.03:24:35.99#ibcon#*before return 0, iclass 15, count 0 2006.257.03:24:35.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:35.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:35.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:24:35.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:24:35.99$vck44/valo=2,534.99 2006.257.03:24:35.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.03:24:35.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.03:24:35.99#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:35.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:35.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:35.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:35.99#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:24:35.99#ibcon#first serial, iclass 17, count 0 2006.257.03:24:35.99#ibcon#enter sib2, iclass 17, count 0 2006.257.03:24:35.99#ibcon#flushed, iclass 17, count 0 2006.257.03:24:35.99#ibcon#about to write, iclass 17, count 0 2006.257.03:24:35.99#ibcon#wrote, iclass 17, count 0 2006.257.03:24:35.99#ibcon#about to read 3, iclass 17, count 0 2006.257.03:24:36.01#ibcon#read 3, iclass 17, count 0 2006.257.03:24:36.01#ibcon#about to read 4, iclass 17, count 0 2006.257.03:24:36.01#ibcon#read 4, iclass 17, count 0 2006.257.03:24:36.01#ibcon#about to read 5, iclass 17, count 0 2006.257.03:24:36.01#ibcon#read 5, iclass 17, count 0 2006.257.03:24:36.01#ibcon#about to read 6, iclass 17, count 0 2006.257.03:24:36.01#ibcon#read 6, iclass 17, count 0 2006.257.03:24:36.01#ibcon#end of sib2, iclass 17, count 0 2006.257.03:24:36.01#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:24:36.01#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:24:36.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:24:36.01#ibcon#*before write, iclass 17, count 0 2006.257.03:24:36.01#ibcon#enter sib2, iclass 17, count 0 2006.257.03:24:36.01#ibcon#flushed, iclass 17, count 0 2006.257.03:24:36.01#ibcon#about to write, iclass 17, count 0 2006.257.03:24:36.01#ibcon#wrote, iclass 17, count 0 2006.257.03:24:36.01#ibcon#about to read 3, iclass 17, count 0 2006.257.03:24:36.05#ibcon#read 3, iclass 17, count 0 2006.257.03:24:36.05#ibcon#about to read 4, iclass 17, count 0 2006.257.03:24:36.05#ibcon#read 4, iclass 17, count 0 2006.257.03:24:36.05#ibcon#about to read 5, iclass 17, count 0 2006.257.03:24:36.05#ibcon#read 5, iclass 17, count 0 2006.257.03:24:36.05#ibcon#about to read 6, iclass 17, count 0 2006.257.03:24:36.05#ibcon#read 6, iclass 17, count 0 2006.257.03:24:36.05#ibcon#end of sib2, iclass 17, count 0 2006.257.03:24:36.05#ibcon#*after write, iclass 17, count 0 2006.257.03:24:36.05#ibcon#*before return 0, iclass 17, count 0 2006.257.03:24:36.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:36.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:36.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:24:36.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:24:36.05$vck44/va=2,7 2006.257.03:24:36.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.03:24:36.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.03:24:36.05#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:36.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:36.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:36.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:36.11#ibcon#enter wrdev, iclass 19, count 2 2006.257.03:24:36.11#ibcon#first serial, iclass 19, count 2 2006.257.03:24:36.11#ibcon#enter sib2, iclass 19, count 2 2006.257.03:24:36.11#ibcon#flushed, iclass 19, count 2 2006.257.03:24:36.11#ibcon#about to write, iclass 19, count 2 2006.257.03:24:36.11#ibcon#wrote, iclass 19, count 2 2006.257.03:24:36.11#ibcon#about to read 3, iclass 19, count 2 2006.257.03:24:36.13#ibcon#read 3, iclass 19, count 2 2006.257.03:24:36.13#ibcon#about to read 4, iclass 19, count 2 2006.257.03:24:36.13#ibcon#read 4, iclass 19, count 2 2006.257.03:24:36.13#ibcon#about to read 5, iclass 19, count 2 2006.257.03:24:36.13#ibcon#read 5, iclass 19, count 2 2006.257.03:24:36.13#ibcon#about to read 6, iclass 19, count 2 2006.257.03:24:36.13#ibcon#read 6, iclass 19, count 2 2006.257.03:24:36.13#ibcon#end of sib2, iclass 19, count 2 2006.257.03:24:36.13#ibcon#*mode == 0, iclass 19, count 2 2006.257.03:24:36.13#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.03:24:36.13#ibcon#[25=AT02-07\r\n] 2006.257.03:24:36.13#ibcon#*before write, iclass 19, count 2 2006.257.03:24:36.13#ibcon#enter sib2, iclass 19, count 2 2006.257.03:24:36.13#ibcon#flushed, iclass 19, count 2 2006.257.03:24:36.13#ibcon#about to write, iclass 19, count 2 2006.257.03:24:36.13#ibcon#wrote, iclass 19, count 2 2006.257.03:24:36.13#ibcon#about to read 3, iclass 19, count 2 2006.257.03:24:36.16#ibcon#read 3, iclass 19, count 2 2006.257.03:24:36.16#ibcon#about to read 4, iclass 19, count 2 2006.257.03:24:36.16#ibcon#read 4, iclass 19, count 2 2006.257.03:24:36.16#ibcon#about to read 5, iclass 19, count 2 2006.257.03:24:36.16#ibcon#read 5, iclass 19, count 2 2006.257.03:24:36.16#ibcon#about to read 6, iclass 19, count 2 2006.257.03:24:36.16#ibcon#read 6, iclass 19, count 2 2006.257.03:24:36.16#ibcon#end of sib2, iclass 19, count 2 2006.257.03:24:36.16#ibcon#*after write, iclass 19, count 2 2006.257.03:24:36.16#ibcon#*before return 0, iclass 19, count 2 2006.257.03:24:36.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:36.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:36.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.03:24:36.16#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:36.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:36.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:36.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:36.28#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:24:36.28#ibcon#first serial, iclass 19, count 0 2006.257.03:24:36.28#ibcon#enter sib2, iclass 19, count 0 2006.257.03:24:36.28#ibcon#flushed, iclass 19, count 0 2006.257.03:24:36.28#ibcon#about to write, iclass 19, count 0 2006.257.03:24:36.28#ibcon#wrote, iclass 19, count 0 2006.257.03:24:36.28#ibcon#about to read 3, iclass 19, count 0 2006.257.03:24:36.30#ibcon#read 3, iclass 19, count 0 2006.257.03:24:36.30#ibcon#about to read 4, iclass 19, count 0 2006.257.03:24:36.30#ibcon#read 4, iclass 19, count 0 2006.257.03:24:36.30#ibcon#about to read 5, iclass 19, count 0 2006.257.03:24:36.30#ibcon#read 5, iclass 19, count 0 2006.257.03:24:36.30#ibcon#about to read 6, iclass 19, count 0 2006.257.03:24:36.30#ibcon#read 6, iclass 19, count 0 2006.257.03:24:36.30#ibcon#end of sib2, iclass 19, count 0 2006.257.03:24:36.30#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:24:36.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:24:36.30#ibcon#[25=USB\r\n] 2006.257.03:24:36.30#ibcon#*before write, iclass 19, count 0 2006.257.03:24:36.30#ibcon#enter sib2, iclass 19, count 0 2006.257.03:24:36.30#ibcon#flushed, iclass 19, count 0 2006.257.03:24:36.30#ibcon#about to write, iclass 19, count 0 2006.257.03:24:36.30#ibcon#wrote, iclass 19, count 0 2006.257.03:24:36.30#ibcon#about to read 3, iclass 19, count 0 2006.257.03:24:36.33#ibcon#read 3, iclass 19, count 0 2006.257.03:24:36.33#ibcon#about to read 4, iclass 19, count 0 2006.257.03:24:36.33#ibcon#read 4, iclass 19, count 0 2006.257.03:24:36.33#ibcon#about to read 5, iclass 19, count 0 2006.257.03:24:36.33#ibcon#read 5, iclass 19, count 0 2006.257.03:24:36.33#ibcon#about to read 6, iclass 19, count 0 2006.257.03:24:36.33#ibcon#read 6, iclass 19, count 0 2006.257.03:24:36.33#ibcon#end of sib2, iclass 19, count 0 2006.257.03:24:36.33#ibcon#*after write, iclass 19, count 0 2006.257.03:24:36.33#ibcon#*before return 0, iclass 19, count 0 2006.257.03:24:36.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:36.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:36.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:24:36.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:24:36.33$vck44/valo=3,564.99 2006.257.03:24:36.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.03:24:36.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.03:24:36.33#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:36.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:36.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:36.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:36.33#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:24:36.33#ibcon#first serial, iclass 21, count 0 2006.257.03:24:36.33#ibcon#enter sib2, iclass 21, count 0 2006.257.03:24:36.33#ibcon#flushed, iclass 21, count 0 2006.257.03:24:36.33#ibcon#about to write, iclass 21, count 0 2006.257.03:24:36.33#ibcon#wrote, iclass 21, count 0 2006.257.03:24:36.33#ibcon#about to read 3, iclass 21, count 0 2006.257.03:24:36.35#ibcon#read 3, iclass 21, count 0 2006.257.03:24:36.35#ibcon#about to read 4, iclass 21, count 0 2006.257.03:24:36.35#ibcon#read 4, iclass 21, count 0 2006.257.03:24:36.35#ibcon#about to read 5, iclass 21, count 0 2006.257.03:24:36.35#ibcon#read 5, iclass 21, count 0 2006.257.03:24:36.35#ibcon#about to read 6, iclass 21, count 0 2006.257.03:24:36.35#ibcon#read 6, iclass 21, count 0 2006.257.03:24:36.35#ibcon#end of sib2, iclass 21, count 0 2006.257.03:24:36.35#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:24:36.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:24:36.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:24:36.35#ibcon#*before write, iclass 21, count 0 2006.257.03:24:36.35#ibcon#enter sib2, iclass 21, count 0 2006.257.03:24:36.35#ibcon#flushed, iclass 21, count 0 2006.257.03:24:36.35#ibcon#about to write, iclass 21, count 0 2006.257.03:24:36.35#ibcon#wrote, iclass 21, count 0 2006.257.03:24:36.35#ibcon#about to read 3, iclass 21, count 0 2006.257.03:24:36.39#ibcon#read 3, iclass 21, count 0 2006.257.03:24:36.39#ibcon#about to read 4, iclass 21, count 0 2006.257.03:24:36.39#ibcon#read 4, iclass 21, count 0 2006.257.03:24:36.39#ibcon#about to read 5, iclass 21, count 0 2006.257.03:24:36.39#ibcon#read 5, iclass 21, count 0 2006.257.03:24:36.39#ibcon#about to read 6, iclass 21, count 0 2006.257.03:24:36.39#ibcon#read 6, iclass 21, count 0 2006.257.03:24:36.39#ibcon#end of sib2, iclass 21, count 0 2006.257.03:24:36.39#ibcon#*after write, iclass 21, count 0 2006.257.03:24:36.39#ibcon#*before return 0, iclass 21, count 0 2006.257.03:24:36.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:36.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:36.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:24:36.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:24:36.39$vck44/va=3,8 2006.257.03:24:36.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.03:24:36.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.03:24:36.39#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:36.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:36.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:36.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:36.45#ibcon#enter wrdev, iclass 23, count 2 2006.257.03:24:36.45#ibcon#first serial, iclass 23, count 2 2006.257.03:24:36.45#ibcon#enter sib2, iclass 23, count 2 2006.257.03:24:36.45#ibcon#flushed, iclass 23, count 2 2006.257.03:24:36.45#ibcon#about to write, iclass 23, count 2 2006.257.03:24:36.45#ibcon#wrote, iclass 23, count 2 2006.257.03:24:36.45#ibcon#about to read 3, iclass 23, count 2 2006.257.03:24:36.47#ibcon#read 3, iclass 23, count 2 2006.257.03:24:36.47#ibcon#about to read 4, iclass 23, count 2 2006.257.03:24:36.47#ibcon#read 4, iclass 23, count 2 2006.257.03:24:36.47#ibcon#about to read 5, iclass 23, count 2 2006.257.03:24:36.47#ibcon#read 5, iclass 23, count 2 2006.257.03:24:36.47#ibcon#about to read 6, iclass 23, count 2 2006.257.03:24:36.47#ibcon#read 6, iclass 23, count 2 2006.257.03:24:36.47#ibcon#end of sib2, iclass 23, count 2 2006.257.03:24:36.47#ibcon#*mode == 0, iclass 23, count 2 2006.257.03:24:36.47#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.03:24:36.47#ibcon#[25=AT03-08\r\n] 2006.257.03:24:36.47#ibcon#*before write, iclass 23, count 2 2006.257.03:24:36.47#ibcon#enter sib2, iclass 23, count 2 2006.257.03:24:36.47#ibcon#flushed, iclass 23, count 2 2006.257.03:24:36.47#ibcon#about to write, iclass 23, count 2 2006.257.03:24:36.47#ibcon#wrote, iclass 23, count 2 2006.257.03:24:36.47#ibcon#about to read 3, iclass 23, count 2 2006.257.03:24:36.50#ibcon#read 3, iclass 23, count 2 2006.257.03:24:36.50#ibcon#about to read 4, iclass 23, count 2 2006.257.03:24:36.50#ibcon#read 4, iclass 23, count 2 2006.257.03:24:36.50#ibcon#about to read 5, iclass 23, count 2 2006.257.03:24:36.50#ibcon#read 5, iclass 23, count 2 2006.257.03:24:36.50#ibcon#about to read 6, iclass 23, count 2 2006.257.03:24:36.50#ibcon#read 6, iclass 23, count 2 2006.257.03:24:36.50#ibcon#end of sib2, iclass 23, count 2 2006.257.03:24:36.50#ibcon#*after write, iclass 23, count 2 2006.257.03:24:36.50#ibcon#*before return 0, iclass 23, count 2 2006.257.03:24:36.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:36.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:36.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.03:24:36.50#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:36.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:36.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:36.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:36.62#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:24:36.62#ibcon#first serial, iclass 23, count 0 2006.257.03:24:36.62#ibcon#enter sib2, iclass 23, count 0 2006.257.03:24:36.62#ibcon#flushed, iclass 23, count 0 2006.257.03:24:36.62#ibcon#about to write, iclass 23, count 0 2006.257.03:24:36.62#ibcon#wrote, iclass 23, count 0 2006.257.03:24:36.62#ibcon#about to read 3, iclass 23, count 0 2006.257.03:24:36.64#ibcon#read 3, iclass 23, count 0 2006.257.03:24:36.64#ibcon#about to read 4, iclass 23, count 0 2006.257.03:24:36.64#ibcon#read 4, iclass 23, count 0 2006.257.03:24:36.64#ibcon#about to read 5, iclass 23, count 0 2006.257.03:24:36.64#ibcon#read 5, iclass 23, count 0 2006.257.03:24:36.64#ibcon#about to read 6, iclass 23, count 0 2006.257.03:24:36.64#ibcon#read 6, iclass 23, count 0 2006.257.03:24:36.64#ibcon#end of sib2, iclass 23, count 0 2006.257.03:24:36.64#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:24:36.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:24:36.64#ibcon#[25=USB\r\n] 2006.257.03:24:36.64#ibcon#*before write, iclass 23, count 0 2006.257.03:24:36.64#ibcon#enter sib2, iclass 23, count 0 2006.257.03:24:36.64#ibcon#flushed, iclass 23, count 0 2006.257.03:24:36.64#ibcon#about to write, iclass 23, count 0 2006.257.03:24:36.64#ibcon#wrote, iclass 23, count 0 2006.257.03:24:36.64#ibcon#about to read 3, iclass 23, count 0 2006.257.03:24:36.67#ibcon#read 3, iclass 23, count 0 2006.257.03:24:36.67#ibcon#about to read 4, iclass 23, count 0 2006.257.03:24:36.67#ibcon#read 4, iclass 23, count 0 2006.257.03:24:36.67#ibcon#about to read 5, iclass 23, count 0 2006.257.03:24:36.67#ibcon#read 5, iclass 23, count 0 2006.257.03:24:36.67#ibcon#about to read 6, iclass 23, count 0 2006.257.03:24:36.67#ibcon#read 6, iclass 23, count 0 2006.257.03:24:36.67#ibcon#end of sib2, iclass 23, count 0 2006.257.03:24:36.67#ibcon#*after write, iclass 23, count 0 2006.257.03:24:36.67#ibcon#*before return 0, iclass 23, count 0 2006.257.03:24:36.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:36.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:36.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:24:36.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:24:36.67$vck44/valo=4,624.99 2006.257.03:24:36.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.03:24:36.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.03:24:36.67#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:36.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:36.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:36.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:36.67#ibcon#enter wrdev, iclass 25, count 0 2006.257.03:24:36.67#ibcon#first serial, iclass 25, count 0 2006.257.03:24:36.67#ibcon#enter sib2, iclass 25, count 0 2006.257.03:24:36.67#ibcon#flushed, iclass 25, count 0 2006.257.03:24:36.67#ibcon#about to write, iclass 25, count 0 2006.257.03:24:36.67#ibcon#wrote, iclass 25, count 0 2006.257.03:24:36.67#ibcon#about to read 3, iclass 25, count 0 2006.257.03:24:36.69#ibcon#read 3, iclass 25, count 0 2006.257.03:24:36.69#ibcon#about to read 4, iclass 25, count 0 2006.257.03:24:36.69#ibcon#read 4, iclass 25, count 0 2006.257.03:24:36.69#ibcon#about to read 5, iclass 25, count 0 2006.257.03:24:36.69#ibcon#read 5, iclass 25, count 0 2006.257.03:24:36.69#ibcon#about to read 6, iclass 25, count 0 2006.257.03:24:36.69#ibcon#read 6, iclass 25, count 0 2006.257.03:24:36.69#ibcon#end of sib2, iclass 25, count 0 2006.257.03:24:36.69#ibcon#*mode == 0, iclass 25, count 0 2006.257.03:24:36.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.03:24:36.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:24:36.69#ibcon#*before write, iclass 25, count 0 2006.257.03:24:36.69#ibcon#enter sib2, iclass 25, count 0 2006.257.03:24:36.69#ibcon#flushed, iclass 25, count 0 2006.257.03:24:36.69#ibcon#about to write, iclass 25, count 0 2006.257.03:24:36.69#ibcon#wrote, iclass 25, count 0 2006.257.03:24:36.69#ibcon#about to read 3, iclass 25, count 0 2006.257.03:24:36.73#ibcon#read 3, iclass 25, count 0 2006.257.03:24:36.73#ibcon#about to read 4, iclass 25, count 0 2006.257.03:24:36.73#ibcon#read 4, iclass 25, count 0 2006.257.03:24:36.73#ibcon#about to read 5, iclass 25, count 0 2006.257.03:24:36.73#ibcon#read 5, iclass 25, count 0 2006.257.03:24:36.73#ibcon#about to read 6, iclass 25, count 0 2006.257.03:24:36.73#ibcon#read 6, iclass 25, count 0 2006.257.03:24:36.73#ibcon#end of sib2, iclass 25, count 0 2006.257.03:24:36.73#ibcon#*after write, iclass 25, count 0 2006.257.03:24:36.73#ibcon#*before return 0, iclass 25, count 0 2006.257.03:24:36.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:36.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:36.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.03:24:36.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.03:24:36.73$vck44/va=4,7 2006.257.03:24:36.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.03:24:36.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.03:24:36.73#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:36.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:36.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:36.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:36.79#ibcon#enter wrdev, iclass 27, count 2 2006.257.03:24:36.79#ibcon#first serial, iclass 27, count 2 2006.257.03:24:36.79#ibcon#enter sib2, iclass 27, count 2 2006.257.03:24:36.79#ibcon#flushed, iclass 27, count 2 2006.257.03:24:36.79#ibcon#about to write, iclass 27, count 2 2006.257.03:24:36.79#ibcon#wrote, iclass 27, count 2 2006.257.03:24:36.79#ibcon#about to read 3, iclass 27, count 2 2006.257.03:24:36.81#ibcon#read 3, iclass 27, count 2 2006.257.03:24:36.81#ibcon#about to read 4, iclass 27, count 2 2006.257.03:24:36.81#ibcon#read 4, iclass 27, count 2 2006.257.03:24:36.81#ibcon#about to read 5, iclass 27, count 2 2006.257.03:24:36.81#ibcon#read 5, iclass 27, count 2 2006.257.03:24:36.81#ibcon#about to read 6, iclass 27, count 2 2006.257.03:24:36.81#ibcon#read 6, iclass 27, count 2 2006.257.03:24:36.81#ibcon#end of sib2, iclass 27, count 2 2006.257.03:24:36.81#ibcon#*mode == 0, iclass 27, count 2 2006.257.03:24:36.81#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.03:24:36.81#ibcon#[25=AT04-07\r\n] 2006.257.03:24:36.81#ibcon#*before write, iclass 27, count 2 2006.257.03:24:36.81#ibcon#enter sib2, iclass 27, count 2 2006.257.03:24:36.81#ibcon#flushed, iclass 27, count 2 2006.257.03:24:36.81#ibcon#about to write, iclass 27, count 2 2006.257.03:24:36.81#ibcon#wrote, iclass 27, count 2 2006.257.03:24:36.81#ibcon#about to read 3, iclass 27, count 2 2006.257.03:24:36.84#ibcon#read 3, iclass 27, count 2 2006.257.03:24:36.84#ibcon#about to read 4, iclass 27, count 2 2006.257.03:24:36.84#ibcon#read 4, iclass 27, count 2 2006.257.03:24:36.84#ibcon#about to read 5, iclass 27, count 2 2006.257.03:24:36.84#ibcon#read 5, iclass 27, count 2 2006.257.03:24:36.84#ibcon#about to read 6, iclass 27, count 2 2006.257.03:24:36.84#ibcon#read 6, iclass 27, count 2 2006.257.03:24:36.84#ibcon#end of sib2, iclass 27, count 2 2006.257.03:24:36.84#ibcon#*after write, iclass 27, count 2 2006.257.03:24:36.84#ibcon#*before return 0, iclass 27, count 2 2006.257.03:24:36.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:36.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:36.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.03:24:36.84#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:36.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:36.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:36.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:36.96#ibcon#enter wrdev, iclass 27, count 0 2006.257.03:24:36.96#ibcon#first serial, iclass 27, count 0 2006.257.03:24:36.96#ibcon#enter sib2, iclass 27, count 0 2006.257.03:24:36.96#ibcon#flushed, iclass 27, count 0 2006.257.03:24:36.96#ibcon#about to write, iclass 27, count 0 2006.257.03:24:36.96#ibcon#wrote, iclass 27, count 0 2006.257.03:24:36.96#ibcon#about to read 3, iclass 27, count 0 2006.257.03:24:36.98#ibcon#read 3, iclass 27, count 0 2006.257.03:24:36.98#ibcon#about to read 4, iclass 27, count 0 2006.257.03:24:36.98#ibcon#read 4, iclass 27, count 0 2006.257.03:24:36.98#ibcon#about to read 5, iclass 27, count 0 2006.257.03:24:36.98#ibcon#read 5, iclass 27, count 0 2006.257.03:24:36.98#ibcon#about to read 6, iclass 27, count 0 2006.257.03:24:36.98#ibcon#read 6, iclass 27, count 0 2006.257.03:24:36.98#ibcon#end of sib2, iclass 27, count 0 2006.257.03:24:36.98#ibcon#*mode == 0, iclass 27, count 0 2006.257.03:24:36.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.03:24:36.98#ibcon#[25=USB\r\n] 2006.257.03:24:36.98#ibcon#*before write, iclass 27, count 0 2006.257.03:24:36.98#ibcon#enter sib2, iclass 27, count 0 2006.257.03:24:36.98#ibcon#flushed, iclass 27, count 0 2006.257.03:24:36.98#ibcon#about to write, iclass 27, count 0 2006.257.03:24:36.98#ibcon#wrote, iclass 27, count 0 2006.257.03:24:36.98#ibcon#about to read 3, iclass 27, count 0 2006.257.03:24:37.01#ibcon#read 3, iclass 27, count 0 2006.257.03:24:37.01#ibcon#about to read 4, iclass 27, count 0 2006.257.03:24:37.01#ibcon#read 4, iclass 27, count 0 2006.257.03:24:37.01#ibcon#about to read 5, iclass 27, count 0 2006.257.03:24:37.01#ibcon#read 5, iclass 27, count 0 2006.257.03:24:37.01#ibcon#about to read 6, iclass 27, count 0 2006.257.03:24:37.01#ibcon#read 6, iclass 27, count 0 2006.257.03:24:37.01#ibcon#end of sib2, iclass 27, count 0 2006.257.03:24:37.01#ibcon#*after write, iclass 27, count 0 2006.257.03:24:37.01#ibcon#*before return 0, iclass 27, count 0 2006.257.03:24:37.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:37.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:37.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.03:24:37.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.03:24:37.01$vck44/valo=5,734.99 2006.257.03:24:37.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.03:24:37.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.03:24:37.01#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:37.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:37.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:37.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:37.01#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:24:37.01#ibcon#first serial, iclass 29, count 0 2006.257.03:24:37.01#ibcon#enter sib2, iclass 29, count 0 2006.257.03:24:37.01#ibcon#flushed, iclass 29, count 0 2006.257.03:24:37.01#ibcon#about to write, iclass 29, count 0 2006.257.03:24:37.01#ibcon#wrote, iclass 29, count 0 2006.257.03:24:37.01#ibcon#about to read 3, iclass 29, count 0 2006.257.03:24:37.03#ibcon#read 3, iclass 29, count 0 2006.257.03:24:37.03#ibcon#about to read 4, iclass 29, count 0 2006.257.03:24:37.03#ibcon#read 4, iclass 29, count 0 2006.257.03:24:37.03#ibcon#about to read 5, iclass 29, count 0 2006.257.03:24:37.03#ibcon#read 5, iclass 29, count 0 2006.257.03:24:37.03#ibcon#about to read 6, iclass 29, count 0 2006.257.03:24:37.03#ibcon#read 6, iclass 29, count 0 2006.257.03:24:37.03#ibcon#end of sib2, iclass 29, count 0 2006.257.03:24:37.03#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:24:37.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:24:37.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:24:37.03#ibcon#*before write, iclass 29, count 0 2006.257.03:24:37.03#ibcon#enter sib2, iclass 29, count 0 2006.257.03:24:37.03#ibcon#flushed, iclass 29, count 0 2006.257.03:24:37.03#ibcon#about to write, iclass 29, count 0 2006.257.03:24:37.03#ibcon#wrote, iclass 29, count 0 2006.257.03:24:37.03#ibcon#about to read 3, iclass 29, count 0 2006.257.03:24:37.07#ibcon#read 3, iclass 29, count 0 2006.257.03:24:37.07#ibcon#about to read 4, iclass 29, count 0 2006.257.03:24:37.07#ibcon#read 4, iclass 29, count 0 2006.257.03:24:37.07#ibcon#about to read 5, iclass 29, count 0 2006.257.03:24:37.07#ibcon#read 5, iclass 29, count 0 2006.257.03:24:37.07#ibcon#about to read 6, iclass 29, count 0 2006.257.03:24:37.07#ibcon#read 6, iclass 29, count 0 2006.257.03:24:37.07#ibcon#end of sib2, iclass 29, count 0 2006.257.03:24:37.07#ibcon#*after write, iclass 29, count 0 2006.257.03:24:37.07#ibcon#*before return 0, iclass 29, count 0 2006.257.03:24:37.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:37.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:37.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:24:37.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:24:37.07$vck44/va=5,4 2006.257.03:24:37.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.03:24:37.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.03:24:37.07#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:37.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:37.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:37.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:37.13#ibcon#enter wrdev, iclass 31, count 2 2006.257.03:24:37.13#ibcon#first serial, iclass 31, count 2 2006.257.03:24:37.13#ibcon#enter sib2, iclass 31, count 2 2006.257.03:24:37.13#ibcon#flushed, iclass 31, count 2 2006.257.03:24:37.13#ibcon#about to write, iclass 31, count 2 2006.257.03:24:37.13#ibcon#wrote, iclass 31, count 2 2006.257.03:24:37.13#ibcon#about to read 3, iclass 31, count 2 2006.257.03:24:37.15#ibcon#read 3, iclass 31, count 2 2006.257.03:24:37.15#ibcon#about to read 4, iclass 31, count 2 2006.257.03:24:37.15#ibcon#read 4, iclass 31, count 2 2006.257.03:24:37.15#ibcon#about to read 5, iclass 31, count 2 2006.257.03:24:37.15#ibcon#read 5, iclass 31, count 2 2006.257.03:24:37.15#ibcon#about to read 6, iclass 31, count 2 2006.257.03:24:37.15#ibcon#read 6, iclass 31, count 2 2006.257.03:24:37.15#ibcon#end of sib2, iclass 31, count 2 2006.257.03:24:37.15#ibcon#*mode == 0, iclass 31, count 2 2006.257.03:24:37.15#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.03:24:37.15#ibcon#[25=AT05-04\r\n] 2006.257.03:24:37.15#ibcon#*before write, iclass 31, count 2 2006.257.03:24:37.15#ibcon#enter sib2, iclass 31, count 2 2006.257.03:24:37.15#ibcon#flushed, iclass 31, count 2 2006.257.03:24:37.15#ibcon#about to write, iclass 31, count 2 2006.257.03:24:37.15#ibcon#wrote, iclass 31, count 2 2006.257.03:24:37.15#ibcon#about to read 3, iclass 31, count 2 2006.257.03:24:37.18#ibcon#read 3, iclass 31, count 2 2006.257.03:24:37.18#ibcon#about to read 4, iclass 31, count 2 2006.257.03:24:37.18#ibcon#read 4, iclass 31, count 2 2006.257.03:24:37.18#ibcon#about to read 5, iclass 31, count 2 2006.257.03:24:37.18#ibcon#read 5, iclass 31, count 2 2006.257.03:24:37.18#ibcon#about to read 6, iclass 31, count 2 2006.257.03:24:37.18#ibcon#read 6, iclass 31, count 2 2006.257.03:24:37.18#ibcon#end of sib2, iclass 31, count 2 2006.257.03:24:37.18#ibcon#*after write, iclass 31, count 2 2006.257.03:24:37.18#ibcon#*before return 0, iclass 31, count 2 2006.257.03:24:37.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:37.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:37.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.03:24:37.18#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:37.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:37.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:37.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:37.30#ibcon#enter wrdev, iclass 31, count 0 2006.257.03:24:37.30#ibcon#first serial, iclass 31, count 0 2006.257.03:24:37.30#ibcon#enter sib2, iclass 31, count 0 2006.257.03:24:37.30#ibcon#flushed, iclass 31, count 0 2006.257.03:24:37.30#ibcon#about to write, iclass 31, count 0 2006.257.03:24:37.30#ibcon#wrote, iclass 31, count 0 2006.257.03:24:37.30#ibcon#about to read 3, iclass 31, count 0 2006.257.03:24:37.32#ibcon#read 3, iclass 31, count 0 2006.257.03:24:37.32#ibcon#about to read 4, iclass 31, count 0 2006.257.03:24:37.32#ibcon#read 4, iclass 31, count 0 2006.257.03:24:37.32#ibcon#about to read 5, iclass 31, count 0 2006.257.03:24:37.32#ibcon#read 5, iclass 31, count 0 2006.257.03:24:37.32#ibcon#about to read 6, iclass 31, count 0 2006.257.03:24:37.32#ibcon#read 6, iclass 31, count 0 2006.257.03:24:37.32#ibcon#end of sib2, iclass 31, count 0 2006.257.03:24:37.32#ibcon#*mode == 0, iclass 31, count 0 2006.257.03:24:37.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.03:24:37.32#ibcon#[25=USB\r\n] 2006.257.03:24:37.32#ibcon#*before write, iclass 31, count 0 2006.257.03:24:37.32#ibcon#enter sib2, iclass 31, count 0 2006.257.03:24:37.32#ibcon#flushed, iclass 31, count 0 2006.257.03:24:37.32#ibcon#about to write, iclass 31, count 0 2006.257.03:24:37.32#ibcon#wrote, iclass 31, count 0 2006.257.03:24:37.32#ibcon#about to read 3, iclass 31, count 0 2006.257.03:24:37.35#ibcon#read 3, iclass 31, count 0 2006.257.03:24:37.35#ibcon#about to read 4, iclass 31, count 0 2006.257.03:24:37.35#ibcon#read 4, iclass 31, count 0 2006.257.03:24:37.35#ibcon#about to read 5, iclass 31, count 0 2006.257.03:24:37.35#ibcon#read 5, iclass 31, count 0 2006.257.03:24:37.35#ibcon#about to read 6, iclass 31, count 0 2006.257.03:24:37.35#ibcon#read 6, iclass 31, count 0 2006.257.03:24:37.35#ibcon#end of sib2, iclass 31, count 0 2006.257.03:24:37.35#ibcon#*after write, iclass 31, count 0 2006.257.03:24:37.35#ibcon#*before return 0, iclass 31, count 0 2006.257.03:24:37.35#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:37.35#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:37.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.03:24:37.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.03:24:37.35$vck44/valo=6,814.99 2006.257.03:24:37.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.03:24:37.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.03:24:37.35#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:37.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:37.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:37.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:37.35#ibcon#enter wrdev, iclass 33, count 0 2006.257.03:24:37.35#ibcon#first serial, iclass 33, count 0 2006.257.03:24:37.35#ibcon#enter sib2, iclass 33, count 0 2006.257.03:24:37.35#ibcon#flushed, iclass 33, count 0 2006.257.03:24:37.35#ibcon#about to write, iclass 33, count 0 2006.257.03:24:37.35#ibcon#wrote, iclass 33, count 0 2006.257.03:24:37.35#ibcon#about to read 3, iclass 33, count 0 2006.257.03:24:37.37#ibcon#read 3, iclass 33, count 0 2006.257.03:24:37.37#ibcon#about to read 4, iclass 33, count 0 2006.257.03:24:37.37#ibcon#read 4, iclass 33, count 0 2006.257.03:24:37.37#ibcon#about to read 5, iclass 33, count 0 2006.257.03:24:37.37#ibcon#read 5, iclass 33, count 0 2006.257.03:24:37.37#ibcon#about to read 6, iclass 33, count 0 2006.257.03:24:37.37#ibcon#read 6, iclass 33, count 0 2006.257.03:24:37.37#ibcon#end of sib2, iclass 33, count 0 2006.257.03:24:37.37#ibcon#*mode == 0, iclass 33, count 0 2006.257.03:24:37.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.03:24:37.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:24:37.37#ibcon#*before write, iclass 33, count 0 2006.257.03:24:37.37#ibcon#enter sib2, iclass 33, count 0 2006.257.03:24:37.37#ibcon#flushed, iclass 33, count 0 2006.257.03:24:37.37#ibcon#about to write, iclass 33, count 0 2006.257.03:24:37.37#ibcon#wrote, iclass 33, count 0 2006.257.03:24:37.37#ibcon#about to read 3, iclass 33, count 0 2006.257.03:24:37.41#ibcon#read 3, iclass 33, count 0 2006.257.03:24:37.41#ibcon#about to read 4, iclass 33, count 0 2006.257.03:24:37.41#ibcon#read 4, iclass 33, count 0 2006.257.03:24:37.41#ibcon#about to read 5, iclass 33, count 0 2006.257.03:24:37.41#ibcon#read 5, iclass 33, count 0 2006.257.03:24:37.41#ibcon#about to read 6, iclass 33, count 0 2006.257.03:24:37.41#ibcon#read 6, iclass 33, count 0 2006.257.03:24:37.41#ibcon#end of sib2, iclass 33, count 0 2006.257.03:24:37.41#ibcon#*after write, iclass 33, count 0 2006.257.03:24:37.41#ibcon#*before return 0, iclass 33, count 0 2006.257.03:24:37.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:37.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:37.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.03:24:37.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.03:24:37.41$vck44/va=6,4 2006.257.03:24:37.41#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.03:24:37.41#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.03:24:37.41#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:37.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:24:37.42#abcon#<5=/14 1.7 4.7 19.11 961012.0\r\n> 2006.257.03:24:37.44#abcon#{5=INTERFACE CLEAR} 2006.257.03:24:37.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:24:37.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:24:37.47#ibcon#enter wrdev, iclass 36, count 2 2006.257.03:24:37.47#ibcon#first serial, iclass 36, count 2 2006.257.03:24:37.47#ibcon#enter sib2, iclass 36, count 2 2006.257.03:24:37.47#ibcon#flushed, iclass 36, count 2 2006.257.03:24:37.47#ibcon#about to write, iclass 36, count 2 2006.257.03:24:37.47#ibcon#wrote, iclass 36, count 2 2006.257.03:24:37.47#ibcon#about to read 3, iclass 36, count 2 2006.257.03:24:37.49#ibcon#read 3, iclass 36, count 2 2006.257.03:24:37.49#ibcon#about to read 4, iclass 36, count 2 2006.257.03:24:37.49#ibcon#read 4, iclass 36, count 2 2006.257.03:24:37.49#ibcon#about to read 5, iclass 36, count 2 2006.257.03:24:37.49#ibcon#read 5, iclass 36, count 2 2006.257.03:24:37.49#ibcon#about to read 6, iclass 36, count 2 2006.257.03:24:37.49#ibcon#read 6, iclass 36, count 2 2006.257.03:24:37.49#ibcon#end of sib2, iclass 36, count 2 2006.257.03:24:37.49#ibcon#*mode == 0, iclass 36, count 2 2006.257.03:24:37.49#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.03:24:37.49#ibcon#[25=AT06-04\r\n] 2006.257.03:24:37.49#ibcon#*before write, iclass 36, count 2 2006.257.03:24:37.49#ibcon#enter sib2, iclass 36, count 2 2006.257.03:24:37.49#ibcon#flushed, iclass 36, count 2 2006.257.03:24:37.49#ibcon#about to write, iclass 36, count 2 2006.257.03:24:37.49#ibcon#wrote, iclass 36, count 2 2006.257.03:24:37.49#ibcon#about to read 3, iclass 36, count 2 2006.257.03:24:37.50#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:24:37.52#ibcon#read 3, iclass 36, count 2 2006.257.03:24:37.52#ibcon#about to read 4, iclass 36, count 2 2006.257.03:24:37.52#ibcon#read 4, iclass 36, count 2 2006.257.03:24:37.52#ibcon#about to read 5, iclass 36, count 2 2006.257.03:24:37.52#ibcon#read 5, iclass 36, count 2 2006.257.03:24:37.52#ibcon#about to read 6, iclass 36, count 2 2006.257.03:24:37.52#ibcon#read 6, iclass 36, count 2 2006.257.03:24:37.52#ibcon#end of sib2, iclass 36, count 2 2006.257.03:24:37.52#ibcon#*after write, iclass 36, count 2 2006.257.03:24:37.52#ibcon#*before return 0, iclass 36, count 2 2006.257.03:24:37.52#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:24:37.52#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:24:37.52#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.03:24:37.52#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:37.52#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:24:37.64#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:24:37.64#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:24:37.64#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:24:37.64#ibcon#first serial, iclass 36, count 0 2006.257.03:24:37.64#ibcon#enter sib2, iclass 36, count 0 2006.257.03:24:37.64#ibcon#flushed, iclass 36, count 0 2006.257.03:24:37.64#ibcon#about to write, iclass 36, count 0 2006.257.03:24:37.64#ibcon#wrote, iclass 36, count 0 2006.257.03:24:37.64#ibcon#about to read 3, iclass 36, count 0 2006.257.03:24:37.66#ibcon#read 3, iclass 36, count 0 2006.257.03:24:37.66#ibcon#about to read 4, iclass 36, count 0 2006.257.03:24:37.66#ibcon#read 4, iclass 36, count 0 2006.257.03:24:37.66#ibcon#about to read 5, iclass 36, count 0 2006.257.03:24:37.66#ibcon#read 5, iclass 36, count 0 2006.257.03:24:37.66#ibcon#about to read 6, iclass 36, count 0 2006.257.03:24:37.66#ibcon#read 6, iclass 36, count 0 2006.257.03:24:37.66#ibcon#end of sib2, iclass 36, count 0 2006.257.03:24:37.66#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:24:37.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:24:37.66#ibcon#[25=USB\r\n] 2006.257.03:24:37.66#ibcon#*before write, iclass 36, count 0 2006.257.03:24:37.66#ibcon#enter sib2, iclass 36, count 0 2006.257.03:24:37.66#ibcon#flushed, iclass 36, count 0 2006.257.03:24:37.66#ibcon#about to write, iclass 36, count 0 2006.257.03:24:37.66#ibcon#wrote, iclass 36, count 0 2006.257.03:24:37.66#ibcon#about to read 3, iclass 36, count 0 2006.257.03:24:37.69#ibcon#read 3, iclass 36, count 0 2006.257.03:24:37.69#ibcon#about to read 4, iclass 36, count 0 2006.257.03:24:37.69#ibcon#read 4, iclass 36, count 0 2006.257.03:24:37.69#ibcon#about to read 5, iclass 36, count 0 2006.257.03:24:37.69#ibcon#read 5, iclass 36, count 0 2006.257.03:24:37.69#ibcon#about to read 6, iclass 36, count 0 2006.257.03:24:37.69#ibcon#read 6, iclass 36, count 0 2006.257.03:24:37.69#ibcon#end of sib2, iclass 36, count 0 2006.257.03:24:37.69#ibcon#*after write, iclass 36, count 0 2006.257.03:24:37.69#ibcon#*before return 0, iclass 36, count 0 2006.257.03:24:37.69#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:24:37.69#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:24:37.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:24:37.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:24:37.69$vck44/valo=7,864.99 2006.257.03:24:37.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.03:24:37.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.03:24:37.69#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:37.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:37.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:37.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:37.69#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:24:37.69#ibcon#first serial, iclass 3, count 0 2006.257.03:24:37.69#ibcon#enter sib2, iclass 3, count 0 2006.257.03:24:37.69#ibcon#flushed, iclass 3, count 0 2006.257.03:24:37.69#ibcon#about to write, iclass 3, count 0 2006.257.03:24:37.69#ibcon#wrote, iclass 3, count 0 2006.257.03:24:37.69#ibcon#about to read 3, iclass 3, count 0 2006.257.03:24:37.71#ibcon#read 3, iclass 3, count 0 2006.257.03:24:37.71#ibcon#about to read 4, iclass 3, count 0 2006.257.03:24:37.71#ibcon#read 4, iclass 3, count 0 2006.257.03:24:37.71#ibcon#about to read 5, iclass 3, count 0 2006.257.03:24:37.71#ibcon#read 5, iclass 3, count 0 2006.257.03:24:37.71#ibcon#about to read 6, iclass 3, count 0 2006.257.03:24:37.71#ibcon#read 6, iclass 3, count 0 2006.257.03:24:37.71#ibcon#end of sib2, iclass 3, count 0 2006.257.03:24:37.71#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:24:37.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:24:37.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:24:37.71#ibcon#*before write, iclass 3, count 0 2006.257.03:24:37.71#ibcon#enter sib2, iclass 3, count 0 2006.257.03:24:37.71#ibcon#flushed, iclass 3, count 0 2006.257.03:24:37.71#ibcon#about to write, iclass 3, count 0 2006.257.03:24:37.71#ibcon#wrote, iclass 3, count 0 2006.257.03:24:37.71#ibcon#about to read 3, iclass 3, count 0 2006.257.03:24:37.75#ibcon#read 3, iclass 3, count 0 2006.257.03:24:37.75#ibcon#about to read 4, iclass 3, count 0 2006.257.03:24:37.75#ibcon#read 4, iclass 3, count 0 2006.257.03:24:37.75#ibcon#about to read 5, iclass 3, count 0 2006.257.03:24:37.75#ibcon#read 5, iclass 3, count 0 2006.257.03:24:37.75#ibcon#about to read 6, iclass 3, count 0 2006.257.03:24:37.75#ibcon#read 6, iclass 3, count 0 2006.257.03:24:37.75#ibcon#end of sib2, iclass 3, count 0 2006.257.03:24:37.75#ibcon#*after write, iclass 3, count 0 2006.257.03:24:37.75#ibcon#*before return 0, iclass 3, count 0 2006.257.03:24:37.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:37.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:37.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:24:37.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:24:37.75$vck44/va=7,4 2006.257.03:24:37.75#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.03:24:37.75#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.03:24:37.75#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:37.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:37.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:37.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:37.81#ibcon#enter wrdev, iclass 5, count 2 2006.257.03:24:37.81#ibcon#first serial, iclass 5, count 2 2006.257.03:24:37.81#ibcon#enter sib2, iclass 5, count 2 2006.257.03:24:37.81#ibcon#flushed, iclass 5, count 2 2006.257.03:24:37.81#ibcon#about to write, iclass 5, count 2 2006.257.03:24:37.81#ibcon#wrote, iclass 5, count 2 2006.257.03:24:37.81#ibcon#about to read 3, iclass 5, count 2 2006.257.03:24:37.83#ibcon#read 3, iclass 5, count 2 2006.257.03:24:37.83#ibcon#about to read 4, iclass 5, count 2 2006.257.03:24:37.83#ibcon#read 4, iclass 5, count 2 2006.257.03:24:37.83#ibcon#about to read 5, iclass 5, count 2 2006.257.03:24:37.83#ibcon#read 5, iclass 5, count 2 2006.257.03:24:37.83#ibcon#about to read 6, iclass 5, count 2 2006.257.03:24:37.83#ibcon#read 6, iclass 5, count 2 2006.257.03:24:37.83#ibcon#end of sib2, iclass 5, count 2 2006.257.03:24:37.83#ibcon#*mode == 0, iclass 5, count 2 2006.257.03:24:37.83#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.03:24:37.83#ibcon#[25=AT07-04\r\n] 2006.257.03:24:37.83#ibcon#*before write, iclass 5, count 2 2006.257.03:24:37.83#ibcon#enter sib2, iclass 5, count 2 2006.257.03:24:37.83#ibcon#flushed, iclass 5, count 2 2006.257.03:24:37.83#ibcon#about to write, iclass 5, count 2 2006.257.03:24:37.83#ibcon#wrote, iclass 5, count 2 2006.257.03:24:37.83#ibcon#about to read 3, iclass 5, count 2 2006.257.03:24:37.86#ibcon#read 3, iclass 5, count 2 2006.257.03:24:37.86#ibcon#about to read 4, iclass 5, count 2 2006.257.03:24:37.86#ibcon#read 4, iclass 5, count 2 2006.257.03:24:37.86#ibcon#about to read 5, iclass 5, count 2 2006.257.03:24:37.86#ibcon#read 5, iclass 5, count 2 2006.257.03:24:37.86#ibcon#about to read 6, iclass 5, count 2 2006.257.03:24:37.86#ibcon#read 6, iclass 5, count 2 2006.257.03:24:37.86#ibcon#end of sib2, iclass 5, count 2 2006.257.03:24:37.86#ibcon#*after write, iclass 5, count 2 2006.257.03:24:37.86#ibcon#*before return 0, iclass 5, count 2 2006.257.03:24:37.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:37.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:37.86#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.03:24:37.86#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:37.86#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:37.98#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:37.98#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:37.98#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:24:37.98#ibcon#first serial, iclass 5, count 0 2006.257.03:24:37.98#ibcon#enter sib2, iclass 5, count 0 2006.257.03:24:37.98#ibcon#flushed, iclass 5, count 0 2006.257.03:24:37.98#ibcon#about to write, iclass 5, count 0 2006.257.03:24:37.98#ibcon#wrote, iclass 5, count 0 2006.257.03:24:37.98#ibcon#about to read 3, iclass 5, count 0 2006.257.03:24:38.00#ibcon#read 3, iclass 5, count 0 2006.257.03:24:38.00#ibcon#about to read 4, iclass 5, count 0 2006.257.03:24:38.00#ibcon#read 4, iclass 5, count 0 2006.257.03:24:38.00#ibcon#about to read 5, iclass 5, count 0 2006.257.03:24:38.00#ibcon#read 5, iclass 5, count 0 2006.257.03:24:38.00#ibcon#about to read 6, iclass 5, count 0 2006.257.03:24:38.00#ibcon#read 6, iclass 5, count 0 2006.257.03:24:38.00#ibcon#end of sib2, iclass 5, count 0 2006.257.03:24:38.00#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:24:38.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:24:38.00#ibcon#[25=USB\r\n] 2006.257.03:24:38.00#ibcon#*before write, iclass 5, count 0 2006.257.03:24:38.00#ibcon#enter sib2, iclass 5, count 0 2006.257.03:24:38.00#ibcon#flushed, iclass 5, count 0 2006.257.03:24:38.00#ibcon#about to write, iclass 5, count 0 2006.257.03:24:38.00#ibcon#wrote, iclass 5, count 0 2006.257.03:24:38.00#ibcon#about to read 3, iclass 5, count 0 2006.257.03:24:38.03#ibcon#read 3, iclass 5, count 0 2006.257.03:24:38.03#ibcon#about to read 4, iclass 5, count 0 2006.257.03:24:38.03#ibcon#read 4, iclass 5, count 0 2006.257.03:24:38.03#ibcon#about to read 5, iclass 5, count 0 2006.257.03:24:38.03#ibcon#read 5, iclass 5, count 0 2006.257.03:24:38.03#ibcon#about to read 6, iclass 5, count 0 2006.257.03:24:38.03#ibcon#read 6, iclass 5, count 0 2006.257.03:24:38.03#ibcon#end of sib2, iclass 5, count 0 2006.257.03:24:38.03#ibcon#*after write, iclass 5, count 0 2006.257.03:24:38.03#ibcon#*before return 0, iclass 5, count 0 2006.257.03:24:38.03#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:38.03#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:38.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:24:38.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:24:38.03$vck44/valo=8,884.99 2006.257.03:24:38.03#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.03:24:38.03#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.03:24:38.03#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:38.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:38.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:38.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:38.03#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:24:38.03#ibcon#first serial, iclass 7, count 0 2006.257.03:24:38.03#ibcon#enter sib2, iclass 7, count 0 2006.257.03:24:38.03#ibcon#flushed, iclass 7, count 0 2006.257.03:24:38.03#ibcon#about to write, iclass 7, count 0 2006.257.03:24:38.03#ibcon#wrote, iclass 7, count 0 2006.257.03:24:38.03#ibcon#about to read 3, iclass 7, count 0 2006.257.03:24:38.05#ibcon#read 3, iclass 7, count 0 2006.257.03:24:38.05#ibcon#about to read 4, iclass 7, count 0 2006.257.03:24:38.05#ibcon#read 4, iclass 7, count 0 2006.257.03:24:38.05#ibcon#about to read 5, iclass 7, count 0 2006.257.03:24:38.05#ibcon#read 5, iclass 7, count 0 2006.257.03:24:38.05#ibcon#about to read 6, iclass 7, count 0 2006.257.03:24:38.05#ibcon#read 6, iclass 7, count 0 2006.257.03:24:38.05#ibcon#end of sib2, iclass 7, count 0 2006.257.03:24:38.05#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:24:38.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:24:38.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:24:38.05#ibcon#*before write, iclass 7, count 0 2006.257.03:24:38.05#ibcon#enter sib2, iclass 7, count 0 2006.257.03:24:38.05#ibcon#flushed, iclass 7, count 0 2006.257.03:24:38.05#ibcon#about to write, iclass 7, count 0 2006.257.03:24:38.05#ibcon#wrote, iclass 7, count 0 2006.257.03:24:38.05#ibcon#about to read 3, iclass 7, count 0 2006.257.03:24:38.09#ibcon#read 3, iclass 7, count 0 2006.257.03:24:38.09#ibcon#about to read 4, iclass 7, count 0 2006.257.03:24:38.09#ibcon#read 4, iclass 7, count 0 2006.257.03:24:38.09#ibcon#about to read 5, iclass 7, count 0 2006.257.03:24:38.09#ibcon#read 5, iclass 7, count 0 2006.257.03:24:38.09#ibcon#about to read 6, iclass 7, count 0 2006.257.03:24:38.09#ibcon#read 6, iclass 7, count 0 2006.257.03:24:38.09#ibcon#end of sib2, iclass 7, count 0 2006.257.03:24:38.09#ibcon#*after write, iclass 7, count 0 2006.257.03:24:38.09#ibcon#*before return 0, iclass 7, count 0 2006.257.03:24:38.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:38.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:38.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:24:38.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:24:38.09$vck44/va=8,4 2006.257.03:24:38.09#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.03:24:38.09#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.03:24:38.09#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:38.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:24:38.15#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:24:38.15#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:24:38.15#ibcon#enter wrdev, iclass 11, count 2 2006.257.03:24:38.15#ibcon#first serial, iclass 11, count 2 2006.257.03:24:38.15#ibcon#enter sib2, iclass 11, count 2 2006.257.03:24:38.15#ibcon#flushed, iclass 11, count 2 2006.257.03:24:38.15#ibcon#about to write, iclass 11, count 2 2006.257.03:24:38.15#ibcon#wrote, iclass 11, count 2 2006.257.03:24:38.15#ibcon#about to read 3, iclass 11, count 2 2006.257.03:24:38.17#ibcon#read 3, iclass 11, count 2 2006.257.03:24:38.17#ibcon#about to read 4, iclass 11, count 2 2006.257.03:24:38.17#ibcon#read 4, iclass 11, count 2 2006.257.03:24:38.17#ibcon#about to read 5, iclass 11, count 2 2006.257.03:24:38.17#ibcon#read 5, iclass 11, count 2 2006.257.03:24:38.17#ibcon#about to read 6, iclass 11, count 2 2006.257.03:24:38.17#ibcon#read 6, iclass 11, count 2 2006.257.03:24:38.17#ibcon#end of sib2, iclass 11, count 2 2006.257.03:24:38.17#ibcon#*mode == 0, iclass 11, count 2 2006.257.03:24:38.17#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.03:24:38.17#ibcon#[25=AT08-04\r\n] 2006.257.03:24:38.17#ibcon#*before write, iclass 11, count 2 2006.257.03:24:38.17#ibcon#enter sib2, iclass 11, count 2 2006.257.03:24:38.17#ibcon#flushed, iclass 11, count 2 2006.257.03:24:38.17#ibcon#about to write, iclass 11, count 2 2006.257.03:24:38.17#ibcon#wrote, iclass 11, count 2 2006.257.03:24:38.17#ibcon#about to read 3, iclass 11, count 2 2006.257.03:24:38.20#ibcon#read 3, iclass 11, count 2 2006.257.03:24:38.20#ibcon#about to read 4, iclass 11, count 2 2006.257.03:24:38.20#ibcon#read 4, iclass 11, count 2 2006.257.03:24:38.20#ibcon#about to read 5, iclass 11, count 2 2006.257.03:24:38.20#ibcon#read 5, iclass 11, count 2 2006.257.03:24:38.20#ibcon#about to read 6, iclass 11, count 2 2006.257.03:24:38.20#ibcon#read 6, iclass 11, count 2 2006.257.03:24:38.20#ibcon#end of sib2, iclass 11, count 2 2006.257.03:24:38.20#ibcon#*after write, iclass 11, count 2 2006.257.03:24:38.20#ibcon#*before return 0, iclass 11, count 2 2006.257.03:24:38.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:24:38.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:24:38.20#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.03:24:38.20#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:38.20#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:24:38.32#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:24:38.32#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:24:38.32#ibcon#enter wrdev, iclass 11, count 0 2006.257.03:24:38.32#ibcon#first serial, iclass 11, count 0 2006.257.03:24:38.32#ibcon#enter sib2, iclass 11, count 0 2006.257.03:24:38.32#ibcon#flushed, iclass 11, count 0 2006.257.03:24:38.32#ibcon#about to write, iclass 11, count 0 2006.257.03:24:38.32#ibcon#wrote, iclass 11, count 0 2006.257.03:24:38.32#ibcon#about to read 3, iclass 11, count 0 2006.257.03:24:38.34#ibcon#read 3, iclass 11, count 0 2006.257.03:24:38.34#ibcon#about to read 4, iclass 11, count 0 2006.257.03:24:38.34#ibcon#read 4, iclass 11, count 0 2006.257.03:24:38.34#ibcon#about to read 5, iclass 11, count 0 2006.257.03:24:38.34#ibcon#read 5, iclass 11, count 0 2006.257.03:24:38.34#ibcon#about to read 6, iclass 11, count 0 2006.257.03:24:38.34#ibcon#read 6, iclass 11, count 0 2006.257.03:24:38.34#ibcon#end of sib2, iclass 11, count 0 2006.257.03:24:38.34#ibcon#*mode == 0, iclass 11, count 0 2006.257.03:24:38.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.03:24:38.34#ibcon#[25=USB\r\n] 2006.257.03:24:38.34#ibcon#*before write, iclass 11, count 0 2006.257.03:24:38.34#ibcon#enter sib2, iclass 11, count 0 2006.257.03:24:38.34#ibcon#flushed, iclass 11, count 0 2006.257.03:24:38.34#ibcon#about to write, iclass 11, count 0 2006.257.03:24:38.34#ibcon#wrote, iclass 11, count 0 2006.257.03:24:38.34#ibcon#about to read 3, iclass 11, count 0 2006.257.03:24:38.37#ibcon#read 3, iclass 11, count 0 2006.257.03:24:38.37#ibcon#about to read 4, iclass 11, count 0 2006.257.03:24:38.37#ibcon#read 4, iclass 11, count 0 2006.257.03:24:38.37#ibcon#about to read 5, iclass 11, count 0 2006.257.03:24:38.37#ibcon#read 5, iclass 11, count 0 2006.257.03:24:38.37#ibcon#about to read 6, iclass 11, count 0 2006.257.03:24:38.37#ibcon#read 6, iclass 11, count 0 2006.257.03:24:38.37#ibcon#end of sib2, iclass 11, count 0 2006.257.03:24:38.37#ibcon#*after write, iclass 11, count 0 2006.257.03:24:38.37#ibcon#*before return 0, iclass 11, count 0 2006.257.03:24:38.37#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:24:38.37#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:24:38.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.03:24:38.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.03:24:38.37$vck44/vblo=1,629.99 2006.257.03:24:38.37#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.03:24:38.37#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.03:24:38.37#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:38.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:38.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:38.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:38.37#ibcon#enter wrdev, iclass 13, count 0 2006.257.03:24:38.37#ibcon#first serial, iclass 13, count 0 2006.257.03:24:38.37#ibcon#enter sib2, iclass 13, count 0 2006.257.03:24:38.37#ibcon#flushed, iclass 13, count 0 2006.257.03:24:38.37#ibcon#about to write, iclass 13, count 0 2006.257.03:24:38.37#ibcon#wrote, iclass 13, count 0 2006.257.03:24:38.37#ibcon#about to read 3, iclass 13, count 0 2006.257.03:24:38.39#ibcon#read 3, iclass 13, count 0 2006.257.03:24:38.39#ibcon#about to read 4, iclass 13, count 0 2006.257.03:24:38.39#ibcon#read 4, iclass 13, count 0 2006.257.03:24:38.39#ibcon#about to read 5, iclass 13, count 0 2006.257.03:24:38.39#ibcon#read 5, iclass 13, count 0 2006.257.03:24:38.39#ibcon#about to read 6, iclass 13, count 0 2006.257.03:24:38.39#ibcon#read 6, iclass 13, count 0 2006.257.03:24:38.39#ibcon#end of sib2, iclass 13, count 0 2006.257.03:24:38.39#ibcon#*mode == 0, iclass 13, count 0 2006.257.03:24:38.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.03:24:38.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:24:38.39#ibcon#*before write, iclass 13, count 0 2006.257.03:24:38.39#ibcon#enter sib2, iclass 13, count 0 2006.257.03:24:38.39#ibcon#flushed, iclass 13, count 0 2006.257.03:24:38.39#ibcon#about to write, iclass 13, count 0 2006.257.03:24:38.39#ibcon#wrote, iclass 13, count 0 2006.257.03:24:38.39#ibcon#about to read 3, iclass 13, count 0 2006.257.03:24:38.43#ibcon#read 3, iclass 13, count 0 2006.257.03:24:38.43#ibcon#about to read 4, iclass 13, count 0 2006.257.03:24:38.43#ibcon#read 4, iclass 13, count 0 2006.257.03:24:38.43#ibcon#about to read 5, iclass 13, count 0 2006.257.03:24:38.43#ibcon#read 5, iclass 13, count 0 2006.257.03:24:38.43#ibcon#about to read 6, iclass 13, count 0 2006.257.03:24:38.43#ibcon#read 6, iclass 13, count 0 2006.257.03:24:38.43#ibcon#end of sib2, iclass 13, count 0 2006.257.03:24:38.43#ibcon#*after write, iclass 13, count 0 2006.257.03:24:38.43#ibcon#*before return 0, iclass 13, count 0 2006.257.03:24:38.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:38.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:24:38.43#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.03:24:38.43#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.03:24:38.43$vck44/vb=1,4 2006.257.03:24:38.43#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.03:24:38.43#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.03:24:38.43#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:38.43#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:38.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:38.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:38.43#ibcon#enter wrdev, iclass 15, count 2 2006.257.03:24:38.43#ibcon#first serial, iclass 15, count 2 2006.257.03:24:38.43#ibcon#enter sib2, iclass 15, count 2 2006.257.03:24:38.43#ibcon#flushed, iclass 15, count 2 2006.257.03:24:38.43#ibcon#about to write, iclass 15, count 2 2006.257.03:24:38.43#ibcon#wrote, iclass 15, count 2 2006.257.03:24:38.43#ibcon#about to read 3, iclass 15, count 2 2006.257.03:24:38.45#ibcon#read 3, iclass 15, count 2 2006.257.03:24:38.45#ibcon#about to read 4, iclass 15, count 2 2006.257.03:24:38.45#ibcon#read 4, iclass 15, count 2 2006.257.03:24:38.45#ibcon#about to read 5, iclass 15, count 2 2006.257.03:24:38.45#ibcon#read 5, iclass 15, count 2 2006.257.03:24:38.45#ibcon#about to read 6, iclass 15, count 2 2006.257.03:24:38.45#ibcon#read 6, iclass 15, count 2 2006.257.03:24:38.45#ibcon#end of sib2, iclass 15, count 2 2006.257.03:24:38.45#ibcon#*mode == 0, iclass 15, count 2 2006.257.03:24:38.45#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.03:24:38.45#ibcon#[27=AT01-04\r\n] 2006.257.03:24:38.45#ibcon#*before write, iclass 15, count 2 2006.257.03:24:38.45#ibcon#enter sib2, iclass 15, count 2 2006.257.03:24:38.45#ibcon#flushed, iclass 15, count 2 2006.257.03:24:38.45#ibcon#about to write, iclass 15, count 2 2006.257.03:24:38.45#ibcon#wrote, iclass 15, count 2 2006.257.03:24:38.45#ibcon#about to read 3, iclass 15, count 2 2006.257.03:24:38.48#ibcon#read 3, iclass 15, count 2 2006.257.03:24:38.48#ibcon#about to read 4, iclass 15, count 2 2006.257.03:24:38.48#ibcon#read 4, iclass 15, count 2 2006.257.03:24:38.48#ibcon#about to read 5, iclass 15, count 2 2006.257.03:24:38.48#ibcon#read 5, iclass 15, count 2 2006.257.03:24:38.48#ibcon#about to read 6, iclass 15, count 2 2006.257.03:24:38.48#ibcon#read 6, iclass 15, count 2 2006.257.03:24:38.48#ibcon#end of sib2, iclass 15, count 2 2006.257.03:24:38.48#ibcon#*after write, iclass 15, count 2 2006.257.03:24:38.48#ibcon#*before return 0, iclass 15, count 2 2006.257.03:24:38.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:38.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:24:38.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.03:24:38.48#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:38.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:38.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:38.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:38.60#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:24:38.60#ibcon#first serial, iclass 15, count 0 2006.257.03:24:38.60#ibcon#enter sib2, iclass 15, count 0 2006.257.03:24:38.60#ibcon#flushed, iclass 15, count 0 2006.257.03:24:38.60#ibcon#about to write, iclass 15, count 0 2006.257.03:24:38.60#ibcon#wrote, iclass 15, count 0 2006.257.03:24:38.60#ibcon#about to read 3, iclass 15, count 0 2006.257.03:24:38.62#ibcon#read 3, iclass 15, count 0 2006.257.03:24:38.62#ibcon#about to read 4, iclass 15, count 0 2006.257.03:24:38.62#ibcon#read 4, iclass 15, count 0 2006.257.03:24:38.62#ibcon#about to read 5, iclass 15, count 0 2006.257.03:24:38.62#ibcon#read 5, iclass 15, count 0 2006.257.03:24:38.62#ibcon#about to read 6, iclass 15, count 0 2006.257.03:24:38.62#ibcon#read 6, iclass 15, count 0 2006.257.03:24:38.62#ibcon#end of sib2, iclass 15, count 0 2006.257.03:24:38.62#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:24:38.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:24:38.62#ibcon#[27=USB\r\n] 2006.257.03:24:38.62#ibcon#*before write, iclass 15, count 0 2006.257.03:24:38.62#ibcon#enter sib2, iclass 15, count 0 2006.257.03:24:38.62#ibcon#flushed, iclass 15, count 0 2006.257.03:24:38.62#ibcon#about to write, iclass 15, count 0 2006.257.03:24:38.62#ibcon#wrote, iclass 15, count 0 2006.257.03:24:38.62#ibcon#about to read 3, iclass 15, count 0 2006.257.03:24:38.65#ibcon#read 3, iclass 15, count 0 2006.257.03:24:38.65#ibcon#about to read 4, iclass 15, count 0 2006.257.03:24:38.65#ibcon#read 4, iclass 15, count 0 2006.257.03:24:38.65#ibcon#about to read 5, iclass 15, count 0 2006.257.03:24:38.65#ibcon#read 5, iclass 15, count 0 2006.257.03:24:38.65#ibcon#about to read 6, iclass 15, count 0 2006.257.03:24:38.65#ibcon#read 6, iclass 15, count 0 2006.257.03:24:38.65#ibcon#end of sib2, iclass 15, count 0 2006.257.03:24:38.65#ibcon#*after write, iclass 15, count 0 2006.257.03:24:38.65#ibcon#*before return 0, iclass 15, count 0 2006.257.03:24:38.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:38.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:24:38.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:24:38.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:24:38.65$vck44/vblo=2,634.99 2006.257.03:24:38.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.03:24:38.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.03:24:38.65#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:38.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:38.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:38.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:38.65#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:24:38.65#ibcon#first serial, iclass 17, count 0 2006.257.03:24:38.65#ibcon#enter sib2, iclass 17, count 0 2006.257.03:24:38.65#ibcon#flushed, iclass 17, count 0 2006.257.03:24:38.65#ibcon#about to write, iclass 17, count 0 2006.257.03:24:38.65#ibcon#wrote, iclass 17, count 0 2006.257.03:24:38.65#ibcon#about to read 3, iclass 17, count 0 2006.257.03:24:38.67#ibcon#read 3, iclass 17, count 0 2006.257.03:24:38.67#ibcon#about to read 4, iclass 17, count 0 2006.257.03:24:38.67#ibcon#read 4, iclass 17, count 0 2006.257.03:24:38.67#ibcon#about to read 5, iclass 17, count 0 2006.257.03:24:38.67#ibcon#read 5, iclass 17, count 0 2006.257.03:24:38.67#ibcon#about to read 6, iclass 17, count 0 2006.257.03:24:38.67#ibcon#read 6, iclass 17, count 0 2006.257.03:24:38.67#ibcon#end of sib2, iclass 17, count 0 2006.257.03:24:38.67#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:24:38.67#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:24:38.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:24:38.67#ibcon#*before write, iclass 17, count 0 2006.257.03:24:38.67#ibcon#enter sib2, iclass 17, count 0 2006.257.03:24:38.67#ibcon#flushed, iclass 17, count 0 2006.257.03:24:38.67#ibcon#about to write, iclass 17, count 0 2006.257.03:24:38.67#ibcon#wrote, iclass 17, count 0 2006.257.03:24:38.67#ibcon#about to read 3, iclass 17, count 0 2006.257.03:24:38.71#ibcon#read 3, iclass 17, count 0 2006.257.03:24:38.71#ibcon#about to read 4, iclass 17, count 0 2006.257.03:24:38.71#ibcon#read 4, iclass 17, count 0 2006.257.03:24:38.71#ibcon#about to read 5, iclass 17, count 0 2006.257.03:24:38.71#ibcon#read 5, iclass 17, count 0 2006.257.03:24:38.71#ibcon#about to read 6, iclass 17, count 0 2006.257.03:24:38.71#ibcon#read 6, iclass 17, count 0 2006.257.03:24:38.71#ibcon#end of sib2, iclass 17, count 0 2006.257.03:24:38.71#ibcon#*after write, iclass 17, count 0 2006.257.03:24:38.71#ibcon#*before return 0, iclass 17, count 0 2006.257.03:24:38.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:38.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:24:38.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:24:38.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:24:38.71$vck44/vb=2,5 2006.257.03:24:38.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.03:24:38.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.03:24:38.71#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:38.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:38.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:38.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:38.77#ibcon#enter wrdev, iclass 19, count 2 2006.257.03:24:38.77#ibcon#first serial, iclass 19, count 2 2006.257.03:24:38.77#ibcon#enter sib2, iclass 19, count 2 2006.257.03:24:38.77#ibcon#flushed, iclass 19, count 2 2006.257.03:24:38.77#ibcon#about to write, iclass 19, count 2 2006.257.03:24:38.77#ibcon#wrote, iclass 19, count 2 2006.257.03:24:38.77#ibcon#about to read 3, iclass 19, count 2 2006.257.03:24:38.79#ibcon#read 3, iclass 19, count 2 2006.257.03:24:38.79#ibcon#about to read 4, iclass 19, count 2 2006.257.03:24:38.79#ibcon#read 4, iclass 19, count 2 2006.257.03:24:38.79#ibcon#about to read 5, iclass 19, count 2 2006.257.03:24:38.79#ibcon#read 5, iclass 19, count 2 2006.257.03:24:38.79#ibcon#about to read 6, iclass 19, count 2 2006.257.03:24:38.79#ibcon#read 6, iclass 19, count 2 2006.257.03:24:38.79#ibcon#end of sib2, iclass 19, count 2 2006.257.03:24:38.79#ibcon#*mode == 0, iclass 19, count 2 2006.257.03:24:38.79#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.03:24:38.79#ibcon#[27=AT02-05\r\n] 2006.257.03:24:38.79#ibcon#*before write, iclass 19, count 2 2006.257.03:24:38.79#ibcon#enter sib2, iclass 19, count 2 2006.257.03:24:38.79#ibcon#flushed, iclass 19, count 2 2006.257.03:24:38.79#ibcon#about to write, iclass 19, count 2 2006.257.03:24:38.79#ibcon#wrote, iclass 19, count 2 2006.257.03:24:38.79#ibcon#about to read 3, iclass 19, count 2 2006.257.03:24:38.82#ibcon#read 3, iclass 19, count 2 2006.257.03:24:38.82#ibcon#about to read 4, iclass 19, count 2 2006.257.03:24:38.82#ibcon#read 4, iclass 19, count 2 2006.257.03:24:38.82#ibcon#about to read 5, iclass 19, count 2 2006.257.03:24:38.82#ibcon#read 5, iclass 19, count 2 2006.257.03:24:38.82#ibcon#about to read 6, iclass 19, count 2 2006.257.03:24:38.82#ibcon#read 6, iclass 19, count 2 2006.257.03:24:38.82#ibcon#end of sib2, iclass 19, count 2 2006.257.03:24:38.82#ibcon#*after write, iclass 19, count 2 2006.257.03:24:38.82#ibcon#*before return 0, iclass 19, count 2 2006.257.03:24:38.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:38.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:24:38.82#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.03:24:38.82#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:38.82#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:38.94#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:38.94#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:38.94#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:24:38.94#ibcon#first serial, iclass 19, count 0 2006.257.03:24:38.94#ibcon#enter sib2, iclass 19, count 0 2006.257.03:24:38.94#ibcon#flushed, iclass 19, count 0 2006.257.03:24:38.94#ibcon#about to write, iclass 19, count 0 2006.257.03:24:38.94#ibcon#wrote, iclass 19, count 0 2006.257.03:24:38.94#ibcon#about to read 3, iclass 19, count 0 2006.257.03:24:38.96#ibcon#read 3, iclass 19, count 0 2006.257.03:24:38.96#ibcon#about to read 4, iclass 19, count 0 2006.257.03:24:38.96#ibcon#read 4, iclass 19, count 0 2006.257.03:24:38.96#ibcon#about to read 5, iclass 19, count 0 2006.257.03:24:38.96#ibcon#read 5, iclass 19, count 0 2006.257.03:24:38.96#ibcon#about to read 6, iclass 19, count 0 2006.257.03:24:38.96#ibcon#read 6, iclass 19, count 0 2006.257.03:24:38.96#ibcon#end of sib2, iclass 19, count 0 2006.257.03:24:38.96#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:24:38.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:24:38.96#ibcon#[27=USB\r\n] 2006.257.03:24:38.96#ibcon#*before write, iclass 19, count 0 2006.257.03:24:38.96#ibcon#enter sib2, iclass 19, count 0 2006.257.03:24:38.96#ibcon#flushed, iclass 19, count 0 2006.257.03:24:38.96#ibcon#about to write, iclass 19, count 0 2006.257.03:24:38.96#ibcon#wrote, iclass 19, count 0 2006.257.03:24:38.96#ibcon#about to read 3, iclass 19, count 0 2006.257.03:24:38.99#ibcon#read 3, iclass 19, count 0 2006.257.03:24:38.99#ibcon#about to read 4, iclass 19, count 0 2006.257.03:24:38.99#ibcon#read 4, iclass 19, count 0 2006.257.03:24:38.99#ibcon#about to read 5, iclass 19, count 0 2006.257.03:24:38.99#ibcon#read 5, iclass 19, count 0 2006.257.03:24:38.99#ibcon#about to read 6, iclass 19, count 0 2006.257.03:24:38.99#ibcon#read 6, iclass 19, count 0 2006.257.03:24:38.99#ibcon#end of sib2, iclass 19, count 0 2006.257.03:24:38.99#ibcon#*after write, iclass 19, count 0 2006.257.03:24:38.99#ibcon#*before return 0, iclass 19, count 0 2006.257.03:24:38.99#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:38.99#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:24:38.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:24:38.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:24:38.99$vck44/vblo=3,649.99 2006.257.03:24:38.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.03:24:38.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.03:24:38.99#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:38.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:38.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:38.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:38.99#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:24:38.99#ibcon#first serial, iclass 21, count 0 2006.257.03:24:38.99#ibcon#enter sib2, iclass 21, count 0 2006.257.03:24:38.99#ibcon#flushed, iclass 21, count 0 2006.257.03:24:38.99#ibcon#about to write, iclass 21, count 0 2006.257.03:24:38.99#ibcon#wrote, iclass 21, count 0 2006.257.03:24:38.99#ibcon#about to read 3, iclass 21, count 0 2006.257.03:24:39.01#ibcon#read 3, iclass 21, count 0 2006.257.03:24:39.01#ibcon#about to read 4, iclass 21, count 0 2006.257.03:24:39.01#ibcon#read 4, iclass 21, count 0 2006.257.03:24:39.01#ibcon#about to read 5, iclass 21, count 0 2006.257.03:24:39.01#ibcon#read 5, iclass 21, count 0 2006.257.03:24:39.01#ibcon#about to read 6, iclass 21, count 0 2006.257.03:24:39.01#ibcon#read 6, iclass 21, count 0 2006.257.03:24:39.01#ibcon#end of sib2, iclass 21, count 0 2006.257.03:24:39.01#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:24:39.01#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:24:39.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:24:39.01#ibcon#*before write, iclass 21, count 0 2006.257.03:24:39.01#ibcon#enter sib2, iclass 21, count 0 2006.257.03:24:39.01#ibcon#flushed, iclass 21, count 0 2006.257.03:24:39.01#ibcon#about to write, iclass 21, count 0 2006.257.03:24:39.01#ibcon#wrote, iclass 21, count 0 2006.257.03:24:39.01#ibcon#about to read 3, iclass 21, count 0 2006.257.03:24:39.05#ibcon#read 3, iclass 21, count 0 2006.257.03:24:39.05#ibcon#about to read 4, iclass 21, count 0 2006.257.03:24:39.05#ibcon#read 4, iclass 21, count 0 2006.257.03:24:39.05#ibcon#about to read 5, iclass 21, count 0 2006.257.03:24:39.05#ibcon#read 5, iclass 21, count 0 2006.257.03:24:39.05#ibcon#about to read 6, iclass 21, count 0 2006.257.03:24:39.05#ibcon#read 6, iclass 21, count 0 2006.257.03:24:39.05#ibcon#end of sib2, iclass 21, count 0 2006.257.03:24:39.05#ibcon#*after write, iclass 21, count 0 2006.257.03:24:39.05#ibcon#*before return 0, iclass 21, count 0 2006.257.03:24:39.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:39.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:24:39.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:24:39.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:24:39.05$vck44/vb=3,4 2006.257.03:24:39.05#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.03:24:39.05#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.03:24:39.05#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:39.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:39.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:39.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:39.11#ibcon#enter wrdev, iclass 23, count 2 2006.257.03:24:39.11#ibcon#first serial, iclass 23, count 2 2006.257.03:24:39.11#ibcon#enter sib2, iclass 23, count 2 2006.257.03:24:39.11#ibcon#flushed, iclass 23, count 2 2006.257.03:24:39.11#ibcon#about to write, iclass 23, count 2 2006.257.03:24:39.11#ibcon#wrote, iclass 23, count 2 2006.257.03:24:39.11#ibcon#about to read 3, iclass 23, count 2 2006.257.03:24:39.13#ibcon#read 3, iclass 23, count 2 2006.257.03:24:39.13#ibcon#about to read 4, iclass 23, count 2 2006.257.03:24:39.13#ibcon#read 4, iclass 23, count 2 2006.257.03:24:39.13#ibcon#about to read 5, iclass 23, count 2 2006.257.03:24:39.13#ibcon#read 5, iclass 23, count 2 2006.257.03:24:39.13#ibcon#about to read 6, iclass 23, count 2 2006.257.03:24:39.13#ibcon#read 6, iclass 23, count 2 2006.257.03:24:39.13#ibcon#end of sib2, iclass 23, count 2 2006.257.03:24:39.13#ibcon#*mode == 0, iclass 23, count 2 2006.257.03:24:39.13#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.03:24:39.13#ibcon#[27=AT03-04\r\n] 2006.257.03:24:39.13#ibcon#*before write, iclass 23, count 2 2006.257.03:24:39.13#ibcon#enter sib2, iclass 23, count 2 2006.257.03:24:39.13#ibcon#flushed, iclass 23, count 2 2006.257.03:24:39.13#ibcon#about to write, iclass 23, count 2 2006.257.03:24:39.13#ibcon#wrote, iclass 23, count 2 2006.257.03:24:39.13#ibcon#about to read 3, iclass 23, count 2 2006.257.03:24:39.16#ibcon#read 3, iclass 23, count 2 2006.257.03:24:39.16#ibcon#about to read 4, iclass 23, count 2 2006.257.03:24:39.16#ibcon#read 4, iclass 23, count 2 2006.257.03:24:39.16#ibcon#about to read 5, iclass 23, count 2 2006.257.03:24:39.16#ibcon#read 5, iclass 23, count 2 2006.257.03:24:39.16#ibcon#about to read 6, iclass 23, count 2 2006.257.03:24:39.16#ibcon#read 6, iclass 23, count 2 2006.257.03:24:39.16#ibcon#end of sib2, iclass 23, count 2 2006.257.03:24:39.16#ibcon#*after write, iclass 23, count 2 2006.257.03:24:39.16#ibcon#*before return 0, iclass 23, count 2 2006.257.03:24:39.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:39.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:24:39.16#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.03:24:39.16#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:39.16#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:39.28#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:39.28#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:39.28#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:24:39.28#ibcon#first serial, iclass 23, count 0 2006.257.03:24:39.28#ibcon#enter sib2, iclass 23, count 0 2006.257.03:24:39.28#ibcon#flushed, iclass 23, count 0 2006.257.03:24:39.28#ibcon#about to write, iclass 23, count 0 2006.257.03:24:39.28#ibcon#wrote, iclass 23, count 0 2006.257.03:24:39.28#ibcon#about to read 3, iclass 23, count 0 2006.257.03:24:39.30#ibcon#read 3, iclass 23, count 0 2006.257.03:24:39.30#ibcon#about to read 4, iclass 23, count 0 2006.257.03:24:39.30#ibcon#read 4, iclass 23, count 0 2006.257.03:24:39.30#ibcon#about to read 5, iclass 23, count 0 2006.257.03:24:39.30#ibcon#read 5, iclass 23, count 0 2006.257.03:24:39.30#ibcon#about to read 6, iclass 23, count 0 2006.257.03:24:39.30#ibcon#read 6, iclass 23, count 0 2006.257.03:24:39.30#ibcon#end of sib2, iclass 23, count 0 2006.257.03:24:39.30#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:24:39.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:24:39.30#ibcon#[27=USB\r\n] 2006.257.03:24:39.30#ibcon#*before write, iclass 23, count 0 2006.257.03:24:39.30#ibcon#enter sib2, iclass 23, count 0 2006.257.03:24:39.30#ibcon#flushed, iclass 23, count 0 2006.257.03:24:39.30#ibcon#about to write, iclass 23, count 0 2006.257.03:24:39.30#ibcon#wrote, iclass 23, count 0 2006.257.03:24:39.30#ibcon#about to read 3, iclass 23, count 0 2006.257.03:24:39.33#ibcon#read 3, iclass 23, count 0 2006.257.03:24:39.33#ibcon#about to read 4, iclass 23, count 0 2006.257.03:24:39.33#ibcon#read 4, iclass 23, count 0 2006.257.03:24:39.33#ibcon#about to read 5, iclass 23, count 0 2006.257.03:24:39.33#ibcon#read 5, iclass 23, count 0 2006.257.03:24:39.33#ibcon#about to read 6, iclass 23, count 0 2006.257.03:24:39.33#ibcon#read 6, iclass 23, count 0 2006.257.03:24:39.33#ibcon#end of sib2, iclass 23, count 0 2006.257.03:24:39.33#ibcon#*after write, iclass 23, count 0 2006.257.03:24:39.33#ibcon#*before return 0, iclass 23, count 0 2006.257.03:24:39.33#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:39.33#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:24:39.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:24:39.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:24:39.33$vck44/vblo=4,679.99 2006.257.03:24:39.33#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.03:24:39.33#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.03:24:39.33#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:39.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:39.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:39.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:39.33#ibcon#enter wrdev, iclass 25, count 0 2006.257.03:24:39.33#ibcon#first serial, iclass 25, count 0 2006.257.03:24:39.33#ibcon#enter sib2, iclass 25, count 0 2006.257.03:24:39.33#ibcon#flushed, iclass 25, count 0 2006.257.03:24:39.33#ibcon#about to write, iclass 25, count 0 2006.257.03:24:39.33#ibcon#wrote, iclass 25, count 0 2006.257.03:24:39.33#ibcon#about to read 3, iclass 25, count 0 2006.257.03:24:39.35#ibcon#read 3, iclass 25, count 0 2006.257.03:24:39.35#ibcon#about to read 4, iclass 25, count 0 2006.257.03:24:39.35#ibcon#read 4, iclass 25, count 0 2006.257.03:24:39.35#ibcon#about to read 5, iclass 25, count 0 2006.257.03:24:39.35#ibcon#read 5, iclass 25, count 0 2006.257.03:24:39.35#ibcon#about to read 6, iclass 25, count 0 2006.257.03:24:39.35#ibcon#read 6, iclass 25, count 0 2006.257.03:24:39.35#ibcon#end of sib2, iclass 25, count 0 2006.257.03:24:39.35#ibcon#*mode == 0, iclass 25, count 0 2006.257.03:24:39.35#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.03:24:39.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:24:39.35#ibcon#*before write, iclass 25, count 0 2006.257.03:24:39.35#ibcon#enter sib2, iclass 25, count 0 2006.257.03:24:39.35#ibcon#flushed, iclass 25, count 0 2006.257.03:24:39.35#ibcon#about to write, iclass 25, count 0 2006.257.03:24:39.35#ibcon#wrote, iclass 25, count 0 2006.257.03:24:39.35#ibcon#about to read 3, iclass 25, count 0 2006.257.03:24:39.39#ibcon#read 3, iclass 25, count 0 2006.257.03:24:39.39#ibcon#about to read 4, iclass 25, count 0 2006.257.03:24:39.39#ibcon#read 4, iclass 25, count 0 2006.257.03:24:39.39#ibcon#about to read 5, iclass 25, count 0 2006.257.03:24:39.39#ibcon#read 5, iclass 25, count 0 2006.257.03:24:39.39#ibcon#about to read 6, iclass 25, count 0 2006.257.03:24:39.39#ibcon#read 6, iclass 25, count 0 2006.257.03:24:39.39#ibcon#end of sib2, iclass 25, count 0 2006.257.03:24:39.39#ibcon#*after write, iclass 25, count 0 2006.257.03:24:39.39#ibcon#*before return 0, iclass 25, count 0 2006.257.03:24:39.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:39.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:24:39.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.03:24:39.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.03:24:39.39$vck44/vb=4,5 2006.257.03:24:39.39#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.03:24:39.39#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.03:24:39.39#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:39.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:39.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:39.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:39.45#ibcon#enter wrdev, iclass 27, count 2 2006.257.03:24:39.45#ibcon#first serial, iclass 27, count 2 2006.257.03:24:39.45#ibcon#enter sib2, iclass 27, count 2 2006.257.03:24:39.45#ibcon#flushed, iclass 27, count 2 2006.257.03:24:39.45#ibcon#about to write, iclass 27, count 2 2006.257.03:24:39.45#ibcon#wrote, iclass 27, count 2 2006.257.03:24:39.45#ibcon#about to read 3, iclass 27, count 2 2006.257.03:24:39.47#ibcon#read 3, iclass 27, count 2 2006.257.03:24:39.47#ibcon#about to read 4, iclass 27, count 2 2006.257.03:24:39.47#ibcon#read 4, iclass 27, count 2 2006.257.03:24:39.47#ibcon#about to read 5, iclass 27, count 2 2006.257.03:24:39.47#ibcon#read 5, iclass 27, count 2 2006.257.03:24:39.47#ibcon#about to read 6, iclass 27, count 2 2006.257.03:24:39.47#ibcon#read 6, iclass 27, count 2 2006.257.03:24:39.47#ibcon#end of sib2, iclass 27, count 2 2006.257.03:24:39.47#ibcon#*mode == 0, iclass 27, count 2 2006.257.03:24:39.47#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.03:24:39.47#ibcon#[27=AT04-05\r\n] 2006.257.03:24:39.47#ibcon#*before write, iclass 27, count 2 2006.257.03:24:39.47#ibcon#enter sib2, iclass 27, count 2 2006.257.03:24:39.47#ibcon#flushed, iclass 27, count 2 2006.257.03:24:39.47#ibcon#about to write, iclass 27, count 2 2006.257.03:24:39.47#ibcon#wrote, iclass 27, count 2 2006.257.03:24:39.47#ibcon#about to read 3, iclass 27, count 2 2006.257.03:24:39.50#ibcon#read 3, iclass 27, count 2 2006.257.03:24:39.50#ibcon#about to read 4, iclass 27, count 2 2006.257.03:24:39.50#ibcon#read 4, iclass 27, count 2 2006.257.03:24:39.50#ibcon#about to read 5, iclass 27, count 2 2006.257.03:24:39.50#ibcon#read 5, iclass 27, count 2 2006.257.03:24:39.50#ibcon#about to read 6, iclass 27, count 2 2006.257.03:24:39.50#ibcon#read 6, iclass 27, count 2 2006.257.03:24:39.50#ibcon#end of sib2, iclass 27, count 2 2006.257.03:24:39.50#ibcon#*after write, iclass 27, count 2 2006.257.03:24:39.50#ibcon#*before return 0, iclass 27, count 2 2006.257.03:24:39.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:39.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:24:39.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.03:24:39.50#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:39.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:39.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:39.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:39.62#ibcon#enter wrdev, iclass 27, count 0 2006.257.03:24:39.62#ibcon#first serial, iclass 27, count 0 2006.257.03:24:39.62#ibcon#enter sib2, iclass 27, count 0 2006.257.03:24:39.62#ibcon#flushed, iclass 27, count 0 2006.257.03:24:39.62#ibcon#about to write, iclass 27, count 0 2006.257.03:24:39.62#ibcon#wrote, iclass 27, count 0 2006.257.03:24:39.62#ibcon#about to read 3, iclass 27, count 0 2006.257.03:24:39.64#ibcon#read 3, iclass 27, count 0 2006.257.03:24:39.64#ibcon#about to read 4, iclass 27, count 0 2006.257.03:24:39.64#ibcon#read 4, iclass 27, count 0 2006.257.03:24:39.64#ibcon#about to read 5, iclass 27, count 0 2006.257.03:24:39.64#ibcon#read 5, iclass 27, count 0 2006.257.03:24:39.64#ibcon#about to read 6, iclass 27, count 0 2006.257.03:24:39.64#ibcon#read 6, iclass 27, count 0 2006.257.03:24:39.64#ibcon#end of sib2, iclass 27, count 0 2006.257.03:24:39.64#ibcon#*mode == 0, iclass 27, count 0 2006.257.03:24:39.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.03:24:39.64#ibcon#[27=USB\r\n] 2006.257.03:24:39.64#ibcon#*before write, iclass 27, count 0 2006.257.03:24:39.64#ibcon#enter sib2, iclass 27, count 0 2006.257.03:24:39.64#ibcon#flushed, iclass 27, count 0 2006.257.03:24:39.64#ibcon#about to write, iclass 27, count 0 2006.257.03:24:39.64#ibcon#wrote, iclass 27, count 0 2006.257.03:24:39.64#ibcon#about to read 3, iclass 27, count 0 2006.257.03:24:39.67#ibcon#read 3, iclass 27, count 0 2006.257.03:24:39.67#ibcon#about to read 4, iclass 27, count 0 2006.257.03:24:39.67#ibcon#read 4, iclass 27, count 0 2006.257.03:24:39.67#ibcon#about to read 5, iclass 27, count 0 2006.257.03:24:39.67#ibcon#read 5, iclass 27, count 0 2006.257.03:24:39.67#ibcon#about to read 6, iclass 27, count 0 2006.257.03:24:39.67#ibcon#read 6, iclass 27, count 0 2006.257.03:24:39.67#ibcon#end of sib2, iclass 27, count 0 2006.257.03:24:39.67#ibcon#*after write, iclass 27, count 0 2006.257.03:24:39.67#ibcon#*before return 0, iclass 27, count 0 2006.257.03:24:39.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:39.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:24:39.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.03:24:39.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.03:24:39.67$vck44/vblo=5,709.99 2006.257.03:24:39.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.03:24:39.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.03:24:39.67#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:39.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:39.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:39.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:39.67#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:24:39.67#ibcon#first serial, iclass 29, count 0 2006.257.03:24:39.67#ibcon#enter sib2, iclass 29, count 0 2006.257.03:24:39.67#ibcon#flushed, iclass 29, count 0 2006.257.03:24:39.67#ibcon#about to write, iclass 29, count 0 2006.257.03:24:39.67#ibcon#wrote, iclass 29, count 0 2006.257.03:24:39.67#ibcon#about to read 3, iclass 29, count 0 2006.257.03:24:39.69#ibcon#read 3, iclass 29, count 0 2006.257.03:24:39.69#ibcon#about to read 4, iclass 29, count 0 2006.257.03:24:39.69#ibcon#read 4, iclass 29, count 0 2006.257.03:24:39.69#ibcon#about to read 5, iclass 29, count 0 2006.257.03:24:39.69#ibcon#read 5, iclass 29, count 0 2006.257.03:24:39.69#ibcon#about to read 6, iclass 29, count 0 2006.257.03:24:39.69#ibcon#read 6, iclass 29, count 0 2006.257.03:24:39.69#ibcon#end of sib2, iclass 29, count 0 2006.257.03:24:39.69#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:24:39.69#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:24:39.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:24:39.69#ibcon#*before write, iclass 29, count 0 2006.257.03:24:39.69#ibcon#enter sib2, iclass 29, count 0 2006.257.03:24:39.69#ibcon#flushed, iclass 29, count 0 2006.257.03:24:39.69#ibcon#about to write, iclass 29, count 0 2006.257.03:24:39.69#ibcon#wrote, iclass 29, count 0 2006.257.03:24:39.69#ibcon#about to read 3, iclass 29, count 0 2006.257.03:24:39.73#ibcon#read 3, iclass 29, count 0 2006.257.03:24:39.73#ibcon#about to read 4, iclass 29, count 0 2006.257.03:24:39.73#ibcon#read 4, iclass 29, count 0 2006.257.03:24:39.73#ibcon#about to read 5, iclass 29, count 0 2006.257.03:24:39.73#ibcon#read 5, iclass 29, count 0 2006.257.03:24:39.73#ibcon#about to read 6, iclass 29, count 0 2006.257.03:24:39.73#ibcon#read 6, iclass 29, count 0 2006.257.03:24:39.73#ibcon#end of sib2, iclass 29, count 0 2006.257.03:24:39.73#ibcon#*after write, iclass 29, count 0 2006.257.03:24:39.73#ibcon#*before return 0, iclass 29, count 0 2006.257.03:24:39.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:39.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:24:39.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:24:39.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:24:39.73$vck44/vb=5,4 2006.257.03:24:39.73#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.03:24:39.73#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.03:24:39.73#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:39.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:39.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:39.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:39.79#ibcon#enter wrdev, iclass 31, count 2 2006.257.03:24:39.79#ibcon#first serial, iclass 31, count 2 2006.257.03:24:39.79#ibcon#enter sib2, iclass 31, count 2 2006.257.03:24:39.79#ibcon#flushed, iclass 31, count 2 2006.257.03:24:39.79#ibcon#about to write, iclass 31, count 2 2006.257.03:24:39.79#ibcon#wrote, iclass 31, count 2 2006.257.03:24:39.79#ibcon#about to read 3, iclass 31, count 2 2006.257.03:24:39.81#ibcon#read 3, iclass 31, count 2 2006.257.03:24:39.81#ibcon#about to read 4, iclass 31, count 2 2006.257.03:24:39.81#ibcon#read 4, iclass 31, count 2 2006.257.03:24:39.81#ibcon#about to read 5, iclass 31, count 2 2006.257.03:24:39.81#ibcon#read 5, iclass 31, count 2 2006.257.03:24:39.81#ibcon#about to read 6, iclass 31, count 2 2006.257.03:24:39.81#ibcon#read 6, iclass 31, count 2 2006.257.03:24:39.81#ibcon#end of sib2, iclass 31, count 2 2006.257.03:24:39.81#ibcon#*mode == 0, iclass 31, count 2 2006.257.03:24:39.81#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.03:24:39.81#ibcon#[27=AT05-04\r\n] 2006.257.03:24:39.81#ibcon#*before write, iclass 31, count 2 2006.257.03:24:39.81#ibcon#enter sib2, iclass 31, count 2 2006.257.03:24:39.81#ibcon#flushed, iclass 31, count 2 2006.257.03:24:39.81#ibcon#about to write, iclass 31, count 2 2006.257.03:24:39.81#ibcon#wrote, iclass 31, count 2 2006.257.03:24:39.81#ibcon#about to read 3, iclass 31, count 2 2006.257.03:24:39.84#ibcon#read 3, iclass 31, count 2 2006.257.03:24:39.84#ibcon#about to read 4, iclass 31, count 2 2006.257.03:24:39.84#ibcon#read 4, iclass 31, count 2 2006.257.03:24:39.84#ibcon#about to read 5, iclass 31, count 2 2006.257.03:24:39.84#ibcon#read 5, iclass 31, count 2 2006.257.03:24:39.84#ibcon#about to read 6, iclass 31, count 2 2006.257.03:24:39.84#ibcon#read 6, iclass 31, count 2 2006.257.03:24:39.84#ibcon#end of sib2, iclass 31, count 2 2006.257.03:24:39.84#ibcon#*after write, iclass 31, count 2 2006.257.03:24:39.84#ibcon#*before return 0, iclass 31, count 2 2006.257.03:24:39.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:39.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:24:39.84#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.03:24:39.84#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:39.84#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:39.96#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:39.96#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:39.96#ibcon#enter wrdev, iclass 31, count 0 2006.257.03:24:39.96#ibcon#first serial, iclass 31, count 0 2006.257.03:24:39.96#ibcon#enter sib2, iclass 31, count 0 2006.257.03:24:39.96#ibcon#flushed, iclass 31, count 0 2006.257.03:24:39.96#ibcon#about to write, iclass 31, count 0 2006.257.03:24:39.96#ibcon#wrote, iclass 31, count 0 2006.257.03:24:39.96#ibcon#about to read 3, iclass 31, count 0 2006.257.03:24:39.98#ibcon#read 3, iclass 31, count 0 2006.257.03:24:39.98#ibcon#about to read 4, iclass 31, count 0 2006.257.03:24:39.98#ibcon#read 4, iclass 31, count 0 2006.257.03:24:39.98#ibcon#about to read 5, iclass 31, count 0 2006.257.03:24:39.98#ibcon#read 5, iclass 31, count 0 2006.257.03:24:39.98#ibcon#about to read 6, iclass 31, count 0 2006.257.03:24:39.98#ibcon#read 6, iclass 31, count 0 2006.257.03:24:39.98#ibcon#end of sib2, iclass 31, count 0 2006.257.03:24:39.98#ibcon#*mode == 0, iclass 31, count 0 2006.257.03:24:39.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.03:24:39.98#ibcon#[27=USB\r\n] 2006.257.03:24:39.98#ibcon#*before write, iclass 31, count 0 2006.257.03:24:39.98#ibcon#enter sib2, iclass 31, count 0 2006.257.03:24:39.98#ibcon#flushed, iclass 31, count 0 2006.257.03:24:39.98#ibcon#about to write, iclass 31, count 0 2006.257.03:24:39.98#ibcon#wrote, iclass 31, count 0 2006.257.03:24:39.98#ibcon#about to read 3, iclass 31, count 0 2006.257.03:24:40.01#ibcon#read 3, iclass 31, count 0 2006.257.03:24:40.01#ibcon#about to read 4, iclass 31, count 0 2006.257.03:24:40.01#ibcon#read 4, iclass 31, count 0 2006.257.03:24:40.01#ibcon#about to read 5, iclass 31, count 0 2006.257.03:24:40.01#ibcon#read 5, iclass 31, count 0 2006.257.03:24:40.01#ibcon#about to read 6, iclass 31, count 0 2006.257.03:24:40.01#ibcon#read 6, iclass 31, count 0 2006.257.03:24:40.01#ibcon#end of sib2, iclass 31, count 0 2006.257.03:24:40.01#ibcon#*after write, iclass 31, count 0 2006.257.03:24:40.01#ibcon#*before return 0, iclass 31, count 0 2006.257.03:24:40.01#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:40.01#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:24:40.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.03:24:40.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.03:24:40.01$vck44/vblo=6,719.99 2006.257.03:24:40.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.03:24:40.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.03:24:40.01#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:40.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:40.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:40.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:40.01#ibcon#enter wrdev, iclass 33, count 0 2006.257.03:24:40.01#ibcon#first serial, iclass 33, count 0 2006.257.03:24:40.01#ibcon#enter sib2, iclass 33, count 0 2006.257.03:24:40.01#ibcon#flushed, iclass 33, count 0 2006.257.03:24:40.01#ibcon#about to write, iclass 33, count 0 2006.257.03:24:40.01#ibcon#wrote, iclass 33, count 0 2006.257.03:24:40.01#ibcon#about to read 3, iclass 33, count 0 2006.257.03:24:40.03#ibcon#read 3, iclass 33, count 0 2006.257.03:24:40.03#ibcon#about to read 4, iclass 33, count 0 2006.257.03:24:40.03#ibcon#read 4, iclass 33, count 0 2006.257.03:24:40.03#ibcon#about to read 5, iclass 33, count 0 2006.257.03:24:40.03#ibcon#read 5, iclass 33, count 0 2006.257.03:24:40.03#ibcon#about to read 6, iclass 33, count 0 2006.257.03:24:40.03#ibcon#read 6, iclass 33, count 0 2006.257.03:24:40.03#ibcon#end of sib2, iclass 33, count 0 2006.257.03:24:40.03#ibcon#*mode == 0, iclass 33, count 0 2006.257.03:24:40.03#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.03:24:40.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:24:40.03#ibcon#*before write, iclass 33, count 0 2006.257.03:24:40.03#ibcon#enter sib2, iclass 33, count 0 2006.257.03:24:40.03#ibcon#flushed, iclass 33, count 0 2006.257.03:24:40.03#ibcon#about to write, iclass 33, count 0 2006.257.03:24:40.03#ibcon#wrote, iclass 33, count 0 2006.257.03:24:40.03#ibcon#about to read 3, iclass 33, count 0 2006.257.03:24:40.07#ibcon#read 3, iclass 33, count 0 2006.257.03:24:40.07#ibcon#about to read 4, iclass 33, count 0 2006.257.03:24:40.07#ibcon#read 4, iclass 33, count 0 2006.257.03:24:40.07#ibcon#about to read 5, iclass 33, count 0 2006.257.03:24:40.07#ibcon#read 5, iclass 33, count 0 2006.257.03:24:40.07#ibcon#about to read 6, iclass 33, count 0 2006.257.03:24:40.07#ibcon#read 6, iclass 33, count 0 2006.257.03:24:40.07#ibcon#end of sib2, iclass 33, count 0 2006.257.03:24:40.07#ibcon#*after write, iclass 33, count 0 2006.257.03:24:40.07#ibcon#*before return 0, iclass 33, count 0 2006.257.03:24:40.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:40.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:24:40.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.03:24:40.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.03:24:40.07$vck44/vb=6,4 2006.257.03:24:40.07#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.03:24:40.07#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.03:24:40.07#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:40.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:24:40.13#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:24:40.13#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:24:40.13#ibcon#enter wrdev, iclass 35, count 2 2006.257.03:24:40.13#ibcon#first serial, iclass 35, count 2 2006.257.03:24:40.13#ibcon#enter sib2, iclass 35, count 2 2006.257.03:24:40.13#ibcon#flushed, iclass 35, count 2 2006.257.03:24:40.13#ibcon#about to write, iclass 35, count 2 2006.257.03:24:40.13#ibcon#wrote, iclass 35, count 2 2006.257.03:24:40.13#ibcon#about to read 3, iclass 35, count 2 2006.257.03:24:40.15#ibcon#read 3, iclass 35, count 2 2006.257.03:24:40.15#ibcon#about to read 4, iclass 35, count 2 2006.257.03:24:40.15#ibcon#read 4, iclass 35, count 2 2006.257.03:24:40.15#ibcon#about to read 5, iclass 35, count 2 2006.257.03:24:40.15#ibcon#read 5, iclass 35, count 2 2006.257.03:24:40.15#ibcon#about to read 6, iclass 35, count 2 2006.257.03:24:40.15#ibcon#read 6, iclass 35, count 2 2006.257.03:24:40.15#ibcon#end of sib2, iclass 35, count 2 2006.257.03:24:40.15#ibcon#*mode == 0, iclass 35, count 2 2006.257.03:24:40.15#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.03:24:40.15#ibcon#[27=AT06-04\r\n] 2006.257.03:24:40.15#ibcon#*before write, iclass 35, count 2 2006.257.03:24:40.15#ibcon#enter sib2, iclass 35, count 2 2006.257.03:24:40.15#ibcon#flushed, iclass 35, count 2 2006.257.03:24:40.15#ibcon#about to write, iclass 35, count 2 2006.257.03:24:40.15#ibcon#wrote, iclass 35, count 2 2006.257.03:24:40.15#ibcon#about to read 3, iclass 35, count 2 2006.257.03:24:40.18#ibcon#read 3, iclass 35, count 2 2006.257.03:24:40.18#ibcon#about to read 4, iclass 35, count 2 2006.257.03:24:40.18#ibcon#read 4, iclass 35, count 2 2006.257.03:24:40.18#ibcon#about to read 5, iclass 35, count 2 2006.257.03:24:40.18#ibcon#read 5, iclass 35, count 2 2006.257.03:24:40.18#ibcon#about to read 6, iclass 35, count 2 2006.257.03:24:40.18#ibcon#read 6, iclass 35, count 2 2006.257.03:24:40.18#ibcon#end of sib2, iclass 35, count 2 2006.257.03:24:40.18#ibcon#*after write, iclass 35, count 2 2006.257.03:24:40.18#ibcon#*before return 0, iclass 35, count 2 2006.257.03:24:40.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:24:40.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:24:40.18#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.03:24:40.18#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:40.18#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:24:40.30#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:24:40.30#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:24:40.30#ibcon#enter wrdev, iclass 35, count 0 2006.257.03:24:40.30#ibcon#first serial, iclass 35, count 0 2006.257.03:24:40.30#ibcon#enter sib2, iclass 35, count 0 2006.257.03:24:40.30#ibcon#flushed, iclass 35, count 0 2006.257.03:24:40.30#ibcon#about to write, iclass 35, count 0 2006.257.03:24:40.30#ibcon#wrote, iclass 35, count 0 2006.257.03:24:40.30#ibcon#about to read 3, iclass 35, count 0 2006.257.03:24:40.32#ibcon#read 3, iclass 35, count 0 2006.257.03:24:40.32#ibcon#about to read 4, iclass 35, count 0 2006.257.03:24:40.32#ibcon#read 4, iclass 35, count 0 2006.257.03:24:40.32#ibcon#about to read 5, iclass 35, count 0 2006.257.03:24:40.32#ibcon#read 5, iclass 35, count 0 2006.257.03:24:40.32#ibcon#about to read 6, iclass 35, count 0 2006.257.03:24:40.32#ibcon#read 6, iclass 35, count 0 2006.257.03:24:40.32#ibcon#end of sib2, iclass 35, count 0 2006.257.03:24:40.32#ibcon#*mode == 0, iclass 35, count 0 2006.257.03:24:40.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.03:24:40.32#ibcon#[27=USB\r\n] 2006.257.03:24:40.32#ibcon#*before write, iclass 35, count 0 2006.257.03:24:40.32#ibcon#enter sib2, iclass 35, count 0 2006.257.03:24:40.32#ibcon#flushed, iclass 35, count 0 2006.257.03:24:40.32#ibcon#about to write, iclass 35, count 0 2006.257.03:24:40.32#ibcon#wrote, iclass 35, count 0 2006.257.03:24:40.32#ibcon#about to read 3, iclass 35, count 0 2006.257.03:24:40.35#ibcon#read 3, iclass 35, count 0 2006.257.03:24:40.35#ibcon#about to read 4, iclass 35, count 0 2006.257.03:24:40.35#ibcon#read 4, iclass 35, count 0 2006.257.03:24:40.35#ibcon#about to read 5, iclass 35, count 0 2006.257.03:24:40.35#ibcon#read 5, iclass 35, count 0 2006.257.03:24:40.35#ibcon#about to read 6, iclass 35, count 0 2006.257.03:24:40.35#ibcon#read 6, iclass 35, count 0 2006.257.03:24:40.35#ibcon#end of sib2, iclass 35, count 0 2006.257.03:24:40.35#ibcon#*after write, iclass 35, count 0 2006.257.03:24:40.35#ibcon#*before return 0, iclass 35, count 0 2006.257.03:24:40.35#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:24:40.35#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:24:40.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.03:24:40.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.03:24:40.35$vck44/vblo=7,734.99 2006.257.03:24:40.35#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.03:24:40.35#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.03:24:40.35#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:40.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:24:40.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:24:40.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:24:40.35#ibcon#enter wrdev, iclass 37, count 0 2006.257.03:24:40.35#ibcon#first serial, iclass 37, count 0 2006.257.03:24:40.35#ibcon#enter sib2, iclass 37, count 0 2006.257.03:24:40.35#ibcon#flushed, iclass 37, count 0 2006.257.03:24:40.35#ibcon#about to write, iclass 37, count 0 2006.257.03:24:40.35#ibcon#wrote, iclass 37, count 0 2006.257.03:24:40.35#ibcon#about to read 3, iclass 37, count 0 2006.257.03:24:40.37#ibcon#read 3, iclass 37, count 0 2006.257.03:24:40.37#ibcon#about to read 4, iclass 37, count 0 2006.257.03:24:40.37#ibcon#read 4, iclass 37, count 0 2006.257.03:24:40.37#ibcon#about to read 5, iclass 37, count 0 2006.257.03:24:40.37#ibcon#read 5, iclass 37, count 0 2006.257.03:24:40.37#ibcon#about to read 6, iclass 37, count 0 2006.257.03:24:40.37#ibcon#read 6, iclass 37, count 0 2006.257.03:24:40.37#ibcon#end of sib2, iclass 37, count 0 2006.257.03:24:40.37#ibcon#*mode == 0, iclass 37, count 0 2006.257.03:24:40.37#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.03:24:40.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:24:40.37#ibcon#*before write, iclass 37, count 0 2006.257.03:24:40.37#ibcon#enter sib2, iclass 37, count 0 2006.257.03:24:40.37#ibcon#flushed, iclass 37, count 0 2006.257.03:24:40.37#ibcon#about to write, iclass 37, count 0 2006.257.03:24:40.37#ibcon#wrote, iclass 37, count 0 2006.257.03:24:40.37#ibcon#about to read 3, iclass 37, count 0 2006.257.03:24:40.41#ibcon#read 3, iclass 37, count 0 2006.257.03:24:40.41#ibcon#about to read 4, iclass 37, count 0 2006.257.03:24:40.41#ibcon#read 4, iclass 37, count 0 2006.257.03:24:40.41#ibcon#about to read 5, iclass 37, count 0 2006.257.03:24:40.41#ibcon#read 5, iclass 37, count 0 2006.257.03:24:40.41#ibcon#about to read 6, iclass 37, count 0 2006.257.03:24:40.41#ibcon#read 6, iclass 37, count 0 2006.257.03:24:40.41#ibcon#end of sib2, iclass 37, count 0 2006.257.03:24:40.41#ibcon#*after write, iclass 37, count 0 2006.257.03:24:40.41#ibcon#*before return 0, iclass 37, count 0 2006.257.03:24:40.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:24:40.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:24:40.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.03:24:40.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.03:24:40.41$vck44/vb=7,4 2006.257.03:24:40.41#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.03:24:40.41#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.03:24:40.41#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:40.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:24:40.47#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:24:40.47#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:24:40.47#ibcon#enter wrdev, iclass 39, count 2 2006.257.03:24:40.47#ibcon#first serial, iclass 39, count 2 2006.257.03:24:40.47#ibcon#enter sib2, iclass 39, count 2 2006.257.03:24:40.47#ibcon#flushed, iclass 39, count 2 2006.257.03:24:40.47#ibcon#about to write, iclass 39, count 2 2006.257.03:24:40.47#ibcon#wrote, iclass 39, count 2 2006.257.03:24:40.47#ibcon#about to read 3, iclass 39, count 2 2006.257.03:24:40.49#ibcon#read 3, iclass 39, count 2 2006.257.03:24:40.49#ibcon#about to read 4, iclass 39, count 2 2006.257.03:24:40.49#ibcon#read 4, iclass 39, count 2 2006.257.03:24:40.49#ibcon#about to read 5, iclass 39, count 2 2006.257.03:24:40.49#ibcon#read 5, iclass 39, count 2 2006.257.03:24:40.49#ibcon#about to read 6, iclass 39, count 2 2006.257.03:24:40.49#ibcon#read 6, iclass 39, count 2 2006.257.03:24:40.49#ibcon#end of sib2, iclass 39, count 2 2006.257.03:24:40.49#ibcon#*mode == 0, iclass 39, count 2 2006.257.03:24:40.49#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.03:24:40.49#ibcon#[27=AT07-04\r\n] 2006.257.03:24:40.49#ibcon#*before write, iclass 39, count 2 2006.257.03:24:40.49#ibcon#enter sib2, iclass 39, count 2 2006.257.03:24:40.49#ibcon#flushed, iclass 39, count 2 2006.257.03:24:40.49#ibcon#about to write, iclass 39, count 2 2006.257.03:24:40.49#ibcon#wrote, iclass 39, count 2 2006.257.03:24:40.49#ibcon#about to read 3, iclass 39, count 2 2006.257.03:24:40.52#ibcon#read 3, iclass 39, count 2 2006.257.03:24:40.52#ibcon#about to read 4, iclass 39, count 2 2006.257.03:24:40.52#ibcon#read 4, iclass 39, count 2 2006.257.03:24:40.52#ibcon#about to read 5, iclass 39, count 2 2006.257.03:24:40.52#ibcon#read 5, iclass 39, count 2 2006.257.03:24:40.52#ibcon#about to read 6, iclass 39, count 2 2006.257.03:24:40.52#ibcon#read 6, iclass 39, count 2 2006.257.03:24:40.52#ibcon#end of sib2, iclass 39, count 2 2006.257.03:24:40.52#ibcon#*after write, iclass 39, count 2 2006.257.03:24:40.52#ibcon#*before return 0, iclass 39, count 2 2006.257.03:24:40.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:24:40.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:24:40.52#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.03:24:40.52#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:40.52#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:24:40.64#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:24:40.64#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:24:40.64#ibcon#enter wrdev, iclass 39, count 0 2006.257.03:24:40.64#ibcon#first serial, iclass 39, count 0 2006.257.03:24:40.64#ibcon#enter sib2, iclass 39, count 0 2006.257.03:24:40.64#ibcon#flushed, iclass 39, count 0 2006.257.03:24:40.64#ibcon#about to write, iclass 39, count 0 2006.257.03:24:40.64#ibcon#wrote, iclass 39, count 0 2006.257.03:24:40.64#ibcon#about to read 3, iclass 39, count 0 2006.257.03:24:40.66#ibcon#read 3, iclass 39, count 0 2006.257.03:24:40.66#ibcon#about to read 4, iclass 39, count 0 2006.257.03:24:40.66#ibcon#read 4, iclass 39, count 0 2006.257.03:24:40.66#ibcon#about to read 5, iclass 39, count 0 2006.257.03:24:40.66#ibcon#read 5, iclass 39, count 0 2006.257.03:24:40.66#ibcon#about to read 6, iclass 39, count 0 2006.257.03:24:40.66#ibcon#read 6, iclass 39, count 0 2006.257.03:24:40.66#ibcon#end of sib2, iclass 39, count 0 2006.257.03:24:40.66#ibcon#*mode == 0, iclass 39, count 0 2006.257.03:24:40.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.03:24:40.66#ibcon#[27=USB\r\n] 2006.257.03:24:40.66#ibcon#*before write, iclass 39, count 0 2006.257.03:24:40.66#ibcon#enter sib2, iclass 39, count 0 2006.257.03:24:40.66#ibcon#flushed, iclass 39, count 0 2006.257.03:24:40.66#ibcon#about to write, iclass 39, count 0 2006.257.03:24:40.66#ibcon#wrote, iclass 39, count 0 2006.257.03:24:40.66#ibcon#about to read 3, iclass 39, count 0 2006.257.03:24:40.69#ibcon#read 3, iclass 39, count 0 2006.257.03:24:40.69#ibcon#about to read 4, iclass 39, count 0 2006.257.03:24:40.69#ibcon#read 4, iclass 39, count 0 2006.257.03:24:40.69#ibcon#about to read 5, iclass 39, count 0 2006.257.03:24:40.69#ibcon#read 5, iclass 39, count 0 2006.257.03:24:40.69#ibcon#about to read 6, iclass 39, count 0 2006.257.03:24:40.69#ibcon#read 6, iclass 39, count 0 2006.257.03:24:40.69#ibcon#end of sib2, iclass 39, count 0 2006.257.03:24:40.69#ibcon#*after write, iclass 39, count 0 2006.257.03:24:40.69#ibcon#*before return 0, iclass 39, count 0 2006.257.03:24:40.69#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:24:40.69#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:24:40.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.03:24:40.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.03:24:40.69$vck44/vblo=8,744.99 2006.257.03:24:40.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.03:24:40.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.03:24:40.69#ibcon#ireg 17 cls_cnt 0 2006.257.03:24:40.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:40.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:40.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:40.69#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:24:40.69#ibcon#first serial, iclass 3, count 0 2006.257.03:24:40.69#ibcon#enter sib2, iclass 3, count 0 2006.257.03:24:40.69#ibcon#flushed, iclass 3, count 0 2006.257.03:24:40.69#ibcon#about to write, iclass 3, count 0 2006.257.03:24:40.69#ibcon#wrote, iclass 3, count 0 2006.257.03:24:40.69#ibcon#about to read 3, iclass 3, count 0 2006.257.03:24:40.71#ibcon#read 3, iclass 3, count 0 2006.257.03:24:40.71#ibcon#about to read 4, iclass 3, count 0 2006.257.03:24:40.71#ibcon#read 4, iclass 3, count 0 2006.257.03:24:40.71#ibcon#about to read 5, iclass 3, count 0 2006.257.03:24:40.71#ibcon#read 5, iclass 3, count 0 2006.257.03:24:40.71#ibcon#about to read 6, iclass 3, count 0 2006.257.03:24:40.71#ibcon#read 6, iclass 3, count 0 2006.257.03:24:40.71#ibcon#end of sib2, iclass 3, count 0 2006.257.03:24:40.71#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:24:40.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:24:40.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:24:40.71#ibcon#*before write, iclass 3, count 0 2006.257.03:24:40.71#ibcon#enter sib2, iclass 3, count 0 2006.257.03:24:40.71#ibcon#flushed, iclass 3, count 0 2006.257.03:24:40.71#ibcon#about to write, iclass 3, count 0 2006.257.03:24:40.71#ibcon#wrote, iclass 3, count 0 2006.257.03:24:40.71#ibcon#about to read 3, iclass 3, count 0 2006.257.03:24:40.75#ibcon#read 3, iclass 3, count 0 2006.257.03:24:40.75#ibcon#about to read 4, iclass 3, count 0 2006.257.03:24:40.75#ibcon#read 4, iclass 3, count 0 2006.257.03:24:40.75#ibcon#about to read 5, iclass 3, count 0 2006.257.03:24:40.75#ibcon#read 5, iclass 3, count 0 2006.257.03:24:40.75#ibcon#about to read 6, iclass 3, count 0 2006.257.03:24:40.75#ibcon#read 6, iclass 3, count 0 2006.257.03:24:40.75#ibcon#end of sib2, iclass 3, count 0 2006.257.03:24:40.75#ibcon#*after write, iclass 3, count 0 2006.257.03:24:40.75#ibcon#*before return 0, iclass 3, count 0 2006.257.03:24:40.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:40.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:24:40.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:24:40.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:24:40.75$vck44/vb=8,4 2006.257.03:24:40.75#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.03:24:40.75#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.03:24:40.75#ibcon#ireg 11 cls_cnt 2 2006.257.03:24:40.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:40.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:40.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:40.81#ibcon#enter wrdev, iclass 5, count 2 2006.257.03:24:40.81#ibcon#first serial, iclass 5, count 2 2006.257.03:24:40.81#ibcon#enter sib2, iclass 5, count 2 2006.257.03:24:40.81#ibcon#flushed, iclass 5, count 2 2006.257.03:24:40.81#ibcon#about to write, iclass 5, count 2 2006.257.03:24:40.81#ibcon#wrote, iclass 5, count 2 2006.257.03:24:40.81#ibcon#about to read 3, iclass 5, count 2 2006.257.03:24:40.83#ibcon#read 3, iclass 5, count 2 2006.257.03:24:40.83#ibcon#about to read 4, iclass 5, count 2 2006.257.03:24:40.83#ibcon#read 4, iclass 5, count 2 2006.257.03:24:40.83#ibcon#about to read 5, iclass 5, count 2 2006.257.03:24:40.83#ibcon#read 5, iclass 5, count 2 2006.257.03:24:40.83#ibcon#about to read 6, iclass 5, count 2 2006.257.03:24:40.83#ibcon#read 6, iclass 5, count 2 2006.257.03:24:40.83#ibcon#end of sib2, iclass 5, count 2 2006.257.03:24:40.83#ibcon#*mode == 0, iclass 5, count 2 2006.257.03:24:40.83#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.03:24:40.83#ibcon#[27=AT08-04\r\n] 2006.257.03:24:40.83#ibcon#*before write, iclass 5, count 2 2006.257.03:24:40.83#ibcon#enter sib2, iclass 5, count 2 2006.257.03:24:40.83#ibcon#flushed, iclass 5, count 2 2006.257.03:24:40.83#ibcon#about to write, iclass 5, count 2 2006.257.03:24:40.83#ibcon#wrote, iclass 5, count 2 2006.257.03:24:40.83#ibcon#about to read 3, iclass 5, count 2 2006.257.03:24:40.86#ibcon#read 3, iclass 5, count 2 2006.257.03:24:40.86#ibcon#about to read 4, iclass 5, count 2 2006.257.03:24:40.86#ibcon#read 4, iclass 5, count 2 2006.257.03:24:40.86#ibcon#about to read 5, iclass 5, count 2 2006.257.03:24:40.86#ibcon#read 5, iclass 5, count 2 2006.257.03:24:40.86#ibcon#about to read 6, iclass 5, count 2 2006.257.03:24:40.86#ibcon#read 6, iclass 5, count 2 2006.257.03:24:40.86#ibcon#end of sib2, iclass 5, count 2 2006.257.03:24:40.86#ibcon#*after write, iclass 5, count 2 2006.257.03:24:40.86#ibcon#*before return 0, iclass 5, count 2 2006.257.03:24:40.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:40.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:24:40.86#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.03:24:40.86#ibcon#ireg 7 cls_cnt 0 2006.257.03:24:40.86#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:40.98#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:40.98#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:40.98#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:24:40.98#ibcon#first serial, iclass 5, count 0 2006.257.03:24:40.98#ibcon#enter sib2, iclass 5, count 0 2006.257.03:24:40.98#ibcon#flushed, iclass 5, count 0 2006.257.03:24:40.98#ibcon#about to write, iclass 5, count 0 2006.257.03:24:40.98#ibcon#wrote, iclass 5, count 0 2006.257.03:24:40.98#ibcon#about to read 3, iclass 5, count 0 2006.257.03:24:41.00#ibcon#read 3, iclass 5, count 0 2006.257.03:24:41.00#ibcon#about to read 4, iclass 5, count 0 2006.257.03:24:41.00#ibcon#read 4, iclass 5, count 0 2006.257.03:24:41.00#ibcon#about to read 5, iclass 5, count 0 2006.257.03:24:41.00#ibcon#read 5, iclass 5, count 0 2006.257.03:24:41.00#ibcon#about to read 6, iclass 5, count 0 2006.257.03:24:41.00#ibcon#read 6, iclass 5, count 0 2006.257.03:24:41.00#ibcon#end of sib2, iclass 5, count 0 2006.257.03:24:41.00#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:24:41.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:24:41.00#ibcon#[27=USB\r\n] 2006.257.03:24:41.00#ibcon#*before write, iclass 5, count 0 2006.257.03:24:41.00#ibcon#enter sib2, iclass 5, count 0 2006.257.03:24:41.00#ibcon#flushed, iclass 5, count 0 2006.257.03:24:41.00#ibcon#about to write, iclass 5, count 0 2006.257.03:24:41.00#ibcon#wrote, iclass 5, count 0 2006.257.03:24:41.00#ibcon#about to read 3, iclass 5, count 0 2006.257.03:24:41.03#ibcon#read 3, iclass 5, count 0 2006.257.03:24:41.03#ibcon#about to read 4, iclass 5, count 0 2006.257.03:24:41.03#ibcon#read 4, iclass 5, count 0 2006.257.03:24:41.03#ibcon#about to read 5, iclass 5, count 0 2006.257.03:24:41.03#ibcon#read 5, iclass 5, count 0 2006.257.03:24:41.03#ibcon#about to read 6, iclass 5, count 0 2006.257.03:24:41.03#ibcon#read 6, iclass 5, count 0 2006.257.03:24:41.03#ibcon#end of sib2, iclass 5, count 0 2006.257.03:24:41.03#ibcon#*after write, iclass 5, count 0 2006.257.03:24:41.03#ibcon#*before return 0, iclass 5, count 0 2006.257.03:24:41.03#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:41.03#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:24:41.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:24:41.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:24:41.03$vck44/vabw=wide 2006.257.03:24:41.03#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.03:24:41.03#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.03:24:41.03#ibcon#ireg 8 cls_cnt 0 2006.257.03:24:41.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:41.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:41.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:41.03#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:24:41.03#ibcon#first serial, iclass 7, count 0 2006.257.03:24:41.03#ibcon#enter sib2, iclass 7, count 0 2006.257.03:24:41.03#ibcon#flushed, iclass 7, count 0 2006.257.03:24:41.03#ibcon#about to write, iclass 7, count 0 2006.257.03:24:41.03#ibcon#wrote, iclass 7, count 0 2006.257.03:24:41.03#ibcon#about to read 3, iclass 7, count 0 2006.257.03:24:41.05#ibcon#read 3, iclass 7, count 0 2006.257.03:24:41.05#ibcon#about to read 4, iclass 7, count 0 2006.257.03:24:41.05#ibcon#read 4, iclass 7, count 0 2006.257.03:24:41.05#ibcon#about to read 5, iclass 7, count 0 2006.257.03:24:41.05#ibcon#read 5, iclass 7, count 0 2006.257.03:24:41.05#ibcon#about to read 6, iclass 7, count 0 2006.257.03:24:41.05#ibcon#read 6, iclass 7, count 0 2006.257.03:24:41.05#ibcon#end of sib2, iclass 7, count 0 2006.257.03:24:41.05#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:24:41.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:24:41.05#ibcon#[25=BW32\r\n] 2006.257.03:24:41.05#ibcon#*before write, iclass 7, count 0 2006.257.03:24:41.05#ibcon#enter sib2, iclass 7, count 0 2006.257.03:24:41.05#ibcon#flushed, iclass 7, count 0 2006.257.03:24:41.05#ibcon#about to write, iclass 7, count 0 2006.257.03:24:41.05#ibcon#wrote, iclass 7, count 0 2006.257.03:24:41.05#ibcon#about to read 3, iclass 7, count 0 2006.257.03:24:41.08#ibcon#read 3, iclass 7, count 0 2006.257.03:24:41.08#ibcon#about to read 4, iclass 7, count 0 2006.257.03:24:41.08#ibcon#read 4, iclass 7, count 0 2006.257.03:24:41.08#ibcon#about to read 5, iclass 7, count 0 2006.257.03:24:41.08#ibcon#read 5, iclass 7, count 0 2006.257.03:24:41.08#ibcon#about to read 6, iclass 7, count 0 2006.257.03:24:41.08#ibcon#read 6, iclass 7, count 0 2006.257.03:24:41.08#ibcon#end of sib2, iclass 7, count 0 2006.257.03:24:41.08#ibcon#*after write, iclass 7, count 0 2006.257.03:24:41.08#ibcon#*before return 0, iclass 7, count 0 2006.257.03:24:41.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:41.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:24:41.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:24:41.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:24:41.08$vck44/vbbw=wide 2006.257.03:24:41.08#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.03:24:41.08#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.03:24:41.08#ibcon#ireg 8 cls_cnt 0 2006.257.03:24:41.08#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:24:41.15#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:24:41.15#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:24:41.15#ibcon#enter wrdev, iclass 11, count 0 2006.257.03:24:41.15#ibcon#first serial, iclass 11, count 0 2006.257.03:24:41.15#ibcon#enter sib2, iclass 11, count 0 2006.257.03:24:41.15#ibcon#flushed, iclass 11, count 0 2006.257.03:24:41.15#ibcon#about to write, iclass 11, count 0 2006.257.03:24:41.15#ibcon#wrote, iclass 11, count 0 2006.257.03:24:41.15#ibcon#about to read 3, iclass 11, count 0 2006.257.03:24:41.17#ibcon#read 3, iclass 11, count 0 2006.257.03:24:41.17#ibcon#about to read 4, iclass 11, count 0 2006.257.03:24:41.17#ibcon#read 4, iclass 11, count 0 2006.257.03:24:41.17#ibcon#about to read 5, iclass 11, count 0 2006.257.03:24:41.17#ibcon#read 5, iclass 11, count 0 2006.257.03:24:41.17#ibcon#about to read 6, iclass 11, count 0 2006.257.03:24:41.17#ibcon#read 6, iclass 11, count 0 2006.257.03:24:41.17#ibcon#end of sib2, iclass 11, count 0 2006.257.03:24:41.17#ibcon#*mode == 0, iclass 11, count 0 2006.257.03:24:41.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.03:24:41.17#ibcon#[27=BW32\r\n] 2006.257.03:24:41.17#ibcon#*before write, iclass 11, count 0 2006.257.03:24:41.17#ibcon#enter sib2, iclass 11, count 0 2006.257.03:24:41.17#ibcon#flushed, iclass 11, count 0 2006.257.03:24:41.17#ibcon#about to write, iclass 11, count 0 2006.257.03:24:41.17#ibcon#wrote, iclass 11, count 0 2006.257.03:24:41.17#ibcon#about to read 3, iclass 11, count 0 2006.257.03:24:41.20#ibcon#read 3, iclass 11, count 0 2006.257.03:24:41.20#ibcon#about to read 4, iclass 11, count 0 2006.257.03:24:41.20#ibcon#read 4, iclass 11, count 0 2006.257.03:24:41.20#ibcon#about to read 5, iclass 11, count 0 2006.257.03:24:41.20#ibcon#read 5, iclass 11, count 0 2006.257.03:24:41.20#ibcon#about to read 6, iclass 11, count 0 2006.257.03:24:41.20#ibcon#read 6, iclass 11, count 0 2006.257.03:24:41.20#ibcon#end of sib2, iclass 11, count 0 2006.257.03:24:41.20#ibcon#*after write, iclass 11, count 0 2006.257.03:24:41.20#ibcon#*before return 0, iclass 11, count 0 2006.257.03:24:41.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:24:41.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:24:41.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.03:24:41.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.03:24:41.20$setupk4/ifdk4 2006.257.03:24:41.20$ifdk4/lo= 2006.257.03:24:41.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:24:41.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:24:41.20$ifdk4/patch= 2006.257.03:24:41.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:24:41.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:24:41.20$setupk4/!*+20s 2006.257.03:24:47.59#abcon#<5=/14 1.7 4.8 19.11 961012.0\r\n> 2006.257.03:24:47.61#abcon#{5=INTERFACE CLEAR} 2006.257.03:24:47.67#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:24:55.71$setupk4/"tpicd 2006.257.03:24:55.71$setupk4/echo=off 2006.257.03:24:55.71$setupk4/xlog=off 2006.257.03:24:55.71:!2006.257.03:27:45 2006.257.03:25:26.14#trakl#Source acquired 2006.257.03:25:28.14#flagr#flagr/antenna,acquired 2006.257.03:27:45.00:preob 2006.257.03:27:45.13/onsource/TRACKING 2006.257.03:27:45.13:!2006.257.03:27:55 2006.257.03:27:55.00:"tape 2006.257.03:27:55.00:"st=record 2006.257.03:27:55.00:data_valid=on 2006.257.03:27:55.00:midob 2006.257.03:27:55.13/onsource/TRACKING 2006.257.03:27:55.13/wx/19.16,1012.1,95 2006.257.03:27:55.35/cable/+6.4844E-03 2006.257.03:27:56.44/va/01,08,usb,yes,34,37 2006.257.03:27:56.44/va/02,07,usb,yes,37,37 2006.257.03:27:56.44/va/03,08,usb,yes,33,35 2006.257.03:27:56.44/va/04,07,usb,yes,38,40 2006.257.03:27:56.44/va/05,04,usb,yes,34,35 2006.257.03:27:56.44/va/06,04,usb,yes,38,37 2006.257.03:27:56.44/va/07,04,usb,yes,39,39 2006.257.03:27:56.44/va/08,04,usb,yes,32,40 2006.257.03:27:56.67/valo/01,524.99,yes,locked 2006.257.03:27:56.67/valo/02,534.99,yes,locked 2006.257.03:27:56.67/valo/03,564.99,yes,locked 2006.257.03:27:56.67/valo/04,624.99,yes,locked 2006.257.03:27:56.67/valo/05,734.99,yes,locked 2006.257.03:27:56.67/valo/06,814.99,yes,locked 2006.257.03:27:56.67/valo/07,864.99,yes,locked 2006.257.03:27:56.67/valo/08,884.99,yes,locked 2006.257.03:27:57.76/vb/01,04,usb,yes,32,30 2006.257.03:27:57.76/vb/02,05,usb,yes,31,30 2006.257.03:27:57.76/vb/03,04,usb,yes,32,35 2006.257.03:27:57.76/vb/04,05,usb,yes,32,31 2006.257.03:27:57.76/vb/05,04,usb,yes,28,31 2006.257.03:27:57.76/vb/06,04,usb,yes,33,29 2006.257.03:27:57.76/vb/07,04,usb,yes,33,33 2006.257.03:27:57.76/vb/08,04,usb,yes,30,34 2006.257.03:27:58.00/vblo/01,629.99,yes,locked 2006.257.03:27:58.00/vblo/02,634.99,yes,locked 2006.257.03:27:58.00/vblo/03,649.99,yes,locked 2006.257.03:27:58.00/vblo/04,679.99,yes,locked 2006.257.03:27:58.00/vblo/05,709.99,yes,locked 2006.257.03:27:58.00/vblo/06,719.99,yes,locked 2006.257.03:27:58.00/vblo/07,734.99,yes,locked 2006.257.03:27:58.00/vblo/08,744.99,yes,locked 2006.257.03:27:58.15/vabw/8 2006.257.03:27:58.30/vbbw/8 2006.257.03:27:58.39/xfe/off,on,16.0 2006.257.03:27:58.76/ifatt/23,28,28,28 2006.257.03:27:59.08/fmout-gps/S +4.55E-07 2006.257.03:27:59.12:!2006.257.03:28:55 2006.257.03:28:55.00:data_valid=off 2006.257.03:28:55.00:"et 2006.257.03:28:55.00:!+3s 2006.257.03:28:58.01:"tape 2006.257.03:28:58.01:postob 2006.257.03:28:58.12/cable/+6.4846E-03 2006.257.03:28:58.12/wx/19.17,1012.1,95 2006.257.03:28:59.07/fmout-gps/S +4.54E-07 2006.257.03:28:59.07:scan_name=257-0333,jd0609,220 2006.257.03:28:59.07:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.257.03:28:59.14#flagr#flagr/antenna,new-source 2006.257.03:29:00.14:checkk5 2006.257.03:29:00.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:29:00.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:29:01.19/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:29:01.54/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:29:01.89/chk_obsdata//k5ts1/T2570327??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.03:29:02.23/chk_obsdata//k5ts2/T2570327??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.03:29:02.59/chk_obsdata//k5ts3/T2570327??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.03:29:02.94/chk_obsdata//k5ts4/T2570327??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.03:29:03.61/k5log//k5ts1_log_newline 2006.257.03:29:04.27/k5log//k5ts2_log_newline 2006.257.03:29:04.94/k5log//k5ts3_log_newline 2006.257.03:29:05.61/k5log//k5ts4_log_newline 2006.257.03:29:05.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:29:05.63:setupk4=1 2006.257.03:29:05.63$setupk4/echo=on 2006.257.03:29:05.63$setupk4/pcalon 2006.257.03:29:05.63$pcalon/"no phase cal control is implemented here 2006.257.03:29:05.63$setupk4/"tpicd=stop 2006.257.03:29:05.63$setupk4/"rec=synch_on 2006.257.03:29:05.63$setupk4/"rec_mode=128 2006.257.03:29:05.63$setupk4/!* 2006.257.03:29:05.63$setupk4/recpk4 2006.257.03:29:05.63$recpk4/recpatch= 2006.257.03:29:05.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:29:05.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:29:05.63$setupk4/vck44 2006.257.03:29:05.63$vck44/valo=1,524.99 2006.257.03:29:05.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.03:29:05.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.03:29:05.63#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:05.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:05.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:05.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:05.63#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:29:05.63#ibcon#first serial, iclass 12, count 0 2006.257.03:29:05.63#ibcon#enter sib2, iclass 12, count 0 2006.257.03:29:05.63#ibcon#flushed, iclass 12, count 0 2006.257.03:29:05.63#ibcon#about to write, iclass 12, count 0 2006.257.03:29:05.63#ibcon#wrote, iclass 12, count 0 2006.257.03:29:05.63#ibcon#about to read 3, iclass 12, count 0 2006.257.03:29:05.65#ibcon#read 3, iclass 12, count 0 2006.257.03:29:05.65#ibcon#about to read 4, iclass 12, count 0 2006.257.03:29:05.65#ibcon#read 4, iclass 12, count 0 2006.257.03:29:05.65#ibcon#about to read 5, iclass 12, count 0 2006.257.03:29:05.65#ibcon#read 5, iclass 12, count 0 2006.257.03:29:05.65#ibcon#about to read 6, iclass 12, count 0 2006.257.03:29:05.65#ibcon#read 6, iclass 12, count 0 2006.257.03:29:05.65#ibcon#end of sib2, iclass 12, count 0 2006.257.03:29:05.65#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:29:05.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:29:05.65#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:29:05.65#ibcon#*before write, iclass 12, count 0 2006.257.03:29:05.65#ibcon#enter sib2, iclass 12, count 0 2006.257.03:29:05.65#ibcon#flushed, iclass 12, count 0 2006.257.03:29:05.65#ibcon#about to write, iclass 12, count 0 2006.257.03:29:05.65#ibcon#wrote, iclass 12, count 0 2006.257.03:29:05.65#ibcon#about to read 3, iclass 12, count 0 2006.257.03:29:05.70#ibcon#read 3, iclass 12, count 0 2006.257.03:29:05.70#ibcon#about to read 4, iclass 12, count 0 2006.257.03:29:05.70#ibcon#read 4, iclass 12, count 0 2006.257.03:29:05.70#ibcon#about to read 5, iclass 12, count 0 2006.257.03:29:05.70#ibcon#read 5, iclass 12, count 0 2006.257.03:29:05.70#ibcon#about to read 6, iclass 12, count 0 2006.257.03:29:05.70#ibcon#read 6, iclass 12, count 0 2006.257.03:29:05.70#ibcon#end of sib2, iclass 12, count 0 2006.257.03:29:05.70#ibcon#*after write, iclass 12, count 0 2006.257.03:29:05.70#ibcon#*before return 0, iclass 12, count 0 2006.257.03:29:05.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:05.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:05.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:29:05.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:29:05.70$vck44/va=1,8 2006.257.03:29:05.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.03:29:05.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.03:29:05.70#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:05.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:05.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:05.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:05.70#ibcon#enter wrdev, iclass 14, count 2 2006.257.03:29:05.70#ibcon#first serial, iclass 14, count 2 2006.257.03:29:05.70#ibcon#enter sib2, iclass 14, count 2 2006.257.03:29:05.70#ibcon#flushed, iclass 14, count 2 2006.257.03:29:05.70#ibcon#about to write, iclass 14, count 2 2006.257.03:29:05.70#ibcon#wrote, iclass 14, count 2 2006.257.03:29:05.70#ibcon#about to read 3, iclass 14, count 2 2006.257.03:29:05.72#ibcon#read 3, iclass 14, count 2 2006.257.03:29:05.72#ibcon#about to read 4, iclass 14, count 2 2006.257.03:29:05.72#ibcon#read 4, iclass 14, count 2 2006.257.03:29:05.72#ibcon#about to read 5, iclass 14, count 2 2006.257.03:29:05.72#ibcon#read 5, iclass 14, count 2 2006.257.03:29:05.72#ibcon#about to read 6, iclass 14, count 2 2006.257.03:29:05.72#ibcon#read 6, iclass 14, count 2 2006.257.03:29:05.72#ibcon#end of sib2, iclass 14, count 2 2006.257.03:29:05.72#ibcon#*mode == 0, iclass 14, count 2 2006.257.03:29:05.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.03:29:05.72#ibcon#[25=AT01-08\r\n] 2006.257.03:29:05.72#ibcon#*before write, iclass 14, count 2 2006.257.03:29:05.72#ibcon#enter sib2, iclass 14, count 2 2006.257.03:29:05.72#ibcon#flushed, iclass 14, count 2 2006.257.03:29:05.72#ibcon#about to write, iclass 14, count 2 2006.257.03:29:05.72#ibcon#wrote, iclass 14, count 2 2006.257.03:29:05.72#ibcon#about to read 3, iclass 14, count 2 2006.257.03:29:05.75#ibcon#read 3, iclass 14, count 2 2006.257.03:29:05.75#ibcon#about to read 4, iclass 14, count 2 2006.257.03:29:05.75#ibcon#read 4, iclass 14, count 2 2006.257.03:29:05.75#ibcon#about to read 5, iclass 14, count 2 2006.257.03:29:05.75#ibcon#read 5, iclass 14, count 2 2006.257.03:29:05.75#ibcon#about to read 6, iclass 14, count 2 2006.257.03:29:05.75#ibcon#read 6, iclass 14, count 2 2006.257.03:29:05.75#ibcon#end of sib2, iclass 14, count 2 2006.257.03:29:05.75#ibcon#*after write, iclass 14, count 2 2006.257.03:29:05.75#ibcon#*before return 0, iclass 14, count 2 2006.257.03:29:05.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:05.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:05.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.03:29:05.75#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:05.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:05.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:05.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:05.87#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:29:05.87#ibcon#first serial, iclass 14, count 0 2006.257.03:29:05.87#ibcon#enter sib2, iclass 14, count 0 2006.257.03:29:05.87#ibcon#flushed, iclass 14, count 0 2006.257.03:29:05.87#ibcon#about to write, iclass 14, count 0 2006.257.03:29:05.87#ibcon#wrote, iclass 14, count 0 2006.257.03:29:05.87#ibcon#about to read 3, iclass 14, count 0 2006.257.03:29:05.89#ibcon#read 3, iclass 14, count 0 2006.257.03:29:05.89#ibcon#about to read 4, iclass 14, count 0 2006.257.03:29:05.89#ibcon#read 4, iclass 14, count 0 2006.257.03:29:05.89#ibcon#about to read 5, iclass 14, count 0 2006.257.03:29:05.89#ibcon#read 5, iclass 14, count 0 2006.257.03:29:05.89#ibcon#about to read 6, iclass 14, count 0 2006.257.03:29:05.89#ibcon#read 6, iclass 14, count 0 2006.257.03:29:05.89#ibcon#end of sib2, iclass 14, count 0 2006.257.03:29:05.89#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:29:05.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:29:05.89#ibcon#[25=USB\r\n] 2006.257.03:29:05.89#ibcon#*before write, iclass 14, count 0 2006.257.03:29:05.89#ibcon#enter sib2, iclass 14, count 0 2006.257.03:29:05.89#ibcon#flushed, iclass 14, count 0 2006.257.03:29:05.89#ibcon#about to write, iclass 14, count 0 2006.257.03:29:05.89#ibcon#wrote, iclass 14, count 0 2006.257.03:29:05.89#ibcon#about to read 3, iclass 14, count 0 2006.257.03:29:05.92#ibcon#read 3, iclass 14, count 0 2006.257.03:29:05.92#ibcon#about to read 4, iclass 14, count 0 2006.257.03:29:05.92#ibcon#read 4, iclass 14, count 0 2006.257.03:29:05.92#ibcon#about to read 5, iclass 14, count 0 2006.257.03:29:05.92#ibcon#read 5, iclass 14, count 0 2006.257.03:29:05.92#ibcon#about to read 6, iclass 14, count 0 2006.257.03:29:05.92#ibcon#read 6, iclass 14, count 0 2006.257.03:29:05.92#ibcon#end of sib2, iclass 14, count 0 2006.257.03:29:05.92#ibcon#*after write, iclass 14, count 0 2006.257.03:29:05.92#ibcon#*before return 0, iclass 14, count 0 2006.257.03:29:05.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:05.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:05.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:29:05.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:29:05.92$vck44/valo=2,534.99 2006.257.03:29:05.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.03:29:05.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.03:29:05.92#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:05.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:05.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:05.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:05.92#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:29:05.92#ibcon#first serial, iclass 16, count 0 2006.257.03:29:05.92#ibcon#enter sib2, iclass 16, count 0 2006.257.03:29:05.92#ibcon#flushed, iclass 16, count 0 2006.257.03:29:05.92#ibcon#about to write, iclass 16, count 0 2006.257.03:29:05.92#ibcon#wrote, iclass 16, count 0 2006.257.03:29:05.92#ibcon#about to read 3, iclass 16, count 0 2006.257.03:29:05.94#ibcon#read 3, iclass 16, count 0 2006.257.03:29:05.94#ibcon#about to read 4, iclass 16, count 0 2006.257.03:29:05.94#ibcon#read 4, iclass 16, count 0 2006.257.03:29:05.94#ibcon#about to read 5, iclass 16, count 0 2006.257.03:29:05.94#ibcon#read 5, iclass 16, count 0 2006.257.03:29:05.94#ibcon#about to read 6, iclass 16, count 0 2006.257.03:29:05.94#ibcon#read 6, iclass 16, count 0 2006.257.03:29:05.94#ibcon#end of sib2, iclass 16, count 0 2006.257.03:29:05.94#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:29:05.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:29:05.94#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:29:05.94#ibcon#*before write, iclass 16, count 0 2006.257.03:29:05.94#ibcon#enter sib2, iclass 16, count 0 2006.257.03:29:05.94#ibcon#flushed, iclass 16, count 0 2006.257.03:29:05.94#ibcon#about to write, iclass 16, count 0 2006.257.03:29:05.94#ibcon#wrote, iclass 16, count 0 2006.257.03:29:05.94#ibcon#about to read 3, iclass 16, count 0 2006.257.03:29:05.98#ibcon#read 3, iclass 16, count 0 2006.257.03:29:05.98#ibcon#about to read 4, iclass 16, count 0 2006.257.03:29:05.98#ibcon#read 4, iclass 16, count 0 2006.257.03:29:05.98#ibcon#about to read 5, iclass 16, count 0 2006.257.03:29:05.98#ibcon#read 5, iclass 16, count 0 2006.257.03:29:05.98#ibcon#about to read 6, iclass 16, count 0 2006.257.03:29:05.98#ibcon#read 6, iclass 16, count 0 2006.257.03:29:05.98#ibcon#end of sib2, iclass 16, count 0 2006.257.03:29:05.98#ibcon#*after write, iclass 16, count 0 2006.257.03:29:05.98#ibcon#*before return 0, iclass 16, count 0 2006.257.03:29:05.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:05.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:05.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:29:05.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:29:05.98$vck44/va=2,7 2006.257.03:29:05.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.03:29:05.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.03:29:05.98#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:05.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:06.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:06.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:06.04#ibcon#enter wrdev, iclass 18, count 2 2006.257.03:29:06.04#ibcon#first serial, iclass 18, count 2 2006.257.03:29:06.04#ibcon#enter sib2, iclass 18, count 2 2006.257.03:29:06.04#ibcon#flushed, iclass 18, count 2 2006.257.03:29:06.04#ibcon#about to write, iclass 18, count 2 2006.257.03:29:06.04#ibcon#wrote, iclass 18, count 2 2006.257.03:29:06.04#ibcon#about to read 3, iclass 18, count 2 2006.257.03:29:06.06#ibcon#read 3, iclass 18, count 2 2006.257.03:29:06.06#ibcon#about to read 4, iclass 18, count 2 2006.257.03:29:06.06#ibcon#read 4, iclass 18, count 2 2006.257.03:29:06.06#ibcon#about to read 5, iclass 18, count 2 2006.257.03:29:06.06#ibcon#read 5, iclass 18, count 2 2006.257.03:29:06.06#ibcon#about to read 6, iclass 18, count 2 2006.257.03:29:06.06#ibcon#read 6, iclass 18, count 2 2006.257.03:29:06.06#ibcon#end of sib2, iclass 18, count 2 2006.257.03:29:06.06#ibcon#*mode == 0, iclass 18, count 2 2006.257.03:29:06.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.03:29:06.06#ibcon#[25=AT02-07\r\n] 2006.257.03:29:06.06#ibcon#*before write, iclass 18, count 2 2006.257.03:29:06.06#ibcon#enter sib2, iclass 18, count 2 2006.257.03:29:06.06#ibcon#flushed, iclass 18, count 2 2006.257.03:29:06.06#ibcon#about to write, iclass 18, count 2 2006.257.03:29:06.06#ibcon#wrote, iclass 18, count 2 2006.257.03:29:06.06#ibcon#about to read 3, iclass 18, count 2 2006.257.03:29:06.09#ibcon#read 3, iclass 18, count 2 2006.257.03:29:06.09#ibcon#about to read 4, iclass 18, count 2 2006.257.03:29:06.09#ibcon#read 4, iclass 18, count 2 2006.257.03:29:06.09#ibcon#about to read 5, iclass 18, count 2 2006.257.03:29:06.09#ibcon#read 5, iclass 18, count 2 2006.257.03:29:06.09#ibcon#about to read 6, iclass 18, count 2 2006.257.03:29:06.09#ibcon#read 6, iclass 18, count 2 2006.257.03:29:06.09#ibcon#end of sib2, iclass 18, count 2 2006.257.03:29:06.09#ibcon#*after write, iclass 18, count 2 2006.257.03:29:06.09#ibcon#*before return 0, iclass 18, count 2 2006.257.03:29:06.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:06.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:06.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.03:29:06.09#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:06.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:06.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:06.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:06.21#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:29:06.21#ibcon#first serial, iclass 18, count 0 2006.257.03:29:06.21#ibcon#enter sib2, iclass 18, count 0 2006.257.03:29:06.21#ibcon#flushed, iclass 18, count 0 2006.257.03:29:06.21#ibcon#about to write, iclass 18, count 0 2006.257.03:29:06.21#ibcon#wrote, iclass 18, count 0 2006.257.03:29:06.21#ibcon#about to read 3, iclass 18, count 0 2006.257.03:29:06.23#ibcon#read 3, iclass 18, count 0 2006.257.03:29:06.23#ibcon#about to read 4, iclass 18, count 0 2006.257.03:29:06.23#ibcon#read 4, iclass 18, count 0 2006.257.03:29:06.23#ibcon#about to read 5, iclass 18, count 0 2006.257.03:29:06.23#ibcon#read 5, iclass 18, count 0 2006.257.03:29:06.23#ibcon#about to read 6, iclass 18, count 0 2006.257.03:29:06.23#ibcon#read 6, iclass 18, count 0 2006.257.03:29:06.23#ibcon#end of sib2, iclass 18, count 0 2006.257.03:29:06.23#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:29:06.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:29:06.23#ibcon#[25=USB\r\n] 2006.257.03:29:06.23#ibcon#*before write, iclass 18, count 0 2006.257.03:29:06.23#ibcon#enter sib2, iclass 18, count 0 2006.257.03:29:06.23#ibcon#flushed, iclass 18, count 0 2006.257.03:29:06.23#ibcon#about to write, iclass 18, count 0 2006.257.03:29:06.23#ibcon#wrote, iclass 18, count 0 2006.257.03:29:06.23#ibcon#about to read 3, iclass 18, count 0 2006.257.03:29:06.26#ibcon#read 3, iclass 18, count 0 2006.257.03:29:06.26#ibcon#about to read 4, iclass 18, count 0 2006.257.03:29:06.26#ibcon#read 4, iclass 18, count 0 2006.257.03:29:06.26#ibcon#about to read 5, iclass 18, count 0 2006.257.03:29:06.26#ibcon#read 5, iclass 18, count 0 2006.257.03:29:06.26#ibcon#about to read 6, iclass 18, count 0 2006.257.03:29:06.26#ibcon#read 6, iclass 18, count 0 2006.257.03:29:06.26#ibcon#end of sib2, iclass 18, count 0 2006.257.03:29:06.26#ibcon#*after write, iclass 18, count 0 2006.257.03:29:06.26#ibcon#*before return 0, iclass 18, count 0 2006.257.03:29:06.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:06.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:06.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:29:06.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:29:06.26$vck44/valo=3,564.99 2006.257.03:29:06.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.03:29:06.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.03:29:06.26#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:06.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:06.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:06.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:06.26#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:29:06.26#ibcon#first serial, iclass 20, count 0 2006.257.03:29:06.26#ibcon#enter sib2, iclass 20, count 0 2006.257.03:29:06.26#ibcon#flushed, iclass 20, count 0 2006.257.03:29:06.26#ibcon#about to write, iclass 20, count 0 2006.257.03:29:06.26#ibcon#wrote, iclass 20, count 0 2006.257.03:29:06.26#ibcon#about to read 3, iclass 20, count 0 2006.257.03:29:06.28#ibcon#read 3, iclass 20, count 0 2006.257.03:29:06.28#ibcon#about to read 4, iclass 20, count 0 2006.257.03:29:06.28#ibcon#read 4, iclass 20, count 0 2006.257.03:29:06.28#ibcon#about to read 5, iclass 20, count 0 2006.257.03:29:06.28#ibcon#read 5, iclass 20, count 0 2006.257.03:29:06.28#ibcon#about to read 6, iclass 20, count 0 2006.257.03:29:06.28#ibcon#read 6, iclass 20, count 0 2006.257.03:29:06.28#ibcon#end of sib2, iclass 20, count 0 2006.257.03:29:06.28#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:29:06.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:29:06.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:29:06.28#ibcon#*before write, iclass 20, count 0 2006.257.03:29:06.28#ibcon#enter sib2, iclass 20, count 0 2006.257.03:29:06.28#ibcon#flushed, iclass 20, count 0 2006.257.03:29:06.28#ibcon#about to write, iclass 20, count 0 2006.257.03:29:06.28#ibcon#wrote, iclass 20, count 0 2006.257.03:29:06.28#ibcon#about to read 3, iclass 20, count 0 2006.257.03:29:06.32#ibcon#read 3, iclass 20, count 0 2006.257.03:29:06.32#ibcon#about to read 4, iclass 20, count 0 2006.257.03:29:06.32#ibcon#read 4, iclass 20, count 0 2006.257.03:29:06.32#ibcon#about to read 5, iclass 20, count 0 2006.257.03:29:06.32#ibcon#read 5, iclass 20, count 0 2006.257.03:29:06.32#ibcon#about to read 6, iclass 20, count 0 2006.257.03:29:06.32#ibcon#read 6, iclass 20, count 0 2006.257.03:29:06.32#ibcon#end of sib2, iclass 20, count 0 2006.257.03:29:06.32#ibcon#*after write, iclass 20, count 0 2006.257.03:29:06.32#ibcon#*before return 0, iclass 20, count 0 2006.257.03:29:06.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:06.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:06.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:29:06.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:29:06.32$vck44/va=3,8 2006.257.03:29:06.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.03:29:06.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.03:29:06.32#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:06.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:06.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:06.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:06.38#ibcon#enter wrdev, iclass 22, count 2 2006.257.03:29:06.38#ibcon#first serial, iclass 22, count 2 2006.257.03:29:06.38#ibcon#enter sib2, iclass 22, count 2 2006.257.03:29:06.38#ibcon#flushed, iclass 22, count 2 2006.257.03:29:06.38#ibcon#about to write, iclass 22, count 2 2006.257.03:29:06.38#ibcon#wrote, iclass 22, count 2 2006.257.03:29:06.38#ibcon#about to read 3, iclass 22, count 2 2006.257.03:29:06.40#ibcon#read 3, iclass 22, count 2 2006.257.03:29:06.40#ibcon#about to read 4, iclass 22, count 2 2006.257.03:29:06.40#ibcon#read 4, iclass 22, count 2 2006.257.03:29:06.40#ibcon#about to read 5, iclass 22, count 2 2006.257.03:29:06.40#ibcon#read 5, iclass 22, count 2 2006.257.03:29:06.40#ibcon#about to read 6, iclass 22, count 2 2006.257.03:29:06.40#ibcon#read 6, iclass 22, count 2 2006.257.03:29:06.40#ibcon#end of sib2, iclass 22, count 2 2006.257.03:29:06.40#ibcon#*mode == 0, iclass 22, count 2 2006.257.03:29:06.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.03:29:06.40#ibcon#[25=AT03-08\r\n] 2006.257.03:29:06.40#ibcon#*before write, iclass 22, count 2 2006.257.03:29:06.40#ibcon#enter sib2, iclass 22, count 2 2006.257.03:29:06.40#ibcon#flushed, iclass 22, count 2 2006.257.03:29:06.40#ibcon#about to write, iclass 22, count 2 2006.257.03:29:06.40#ibcon#wrote, iclass 22, count 2 2006.257.03:29:06.40#ibcon#about to read 3, iclass 22, count 2 2006.257.03:29:06.43#ibcon#read 3, iclass 22, count 2 2006.257.03:29:06.43#ibcon#about to read 4, iclass 22, count 2 2006.257.03:29:06.43#ibcon#read 4, iclass 22, count 2 2006.257.03:29:06.43#ibcon#about to read 5, iclass 22, count 2 2006.257.03:29:06.43#ibcon#read 5, iclass 22, count 2 2006.257.03:29:06.43#ibcon#about to read 6, iclass 22, count 2 2006.257.03:29:06.43#ibcon#read 6, iclass 22, count 2 2006.257.03:29:06.43#ibcon#end of sib2, iclass 22, count 2 2006.257.03:29:06.43#ibcon#*after write, iclass 22, count 2 2006.257.03:29:06.43#ibcon#*before return 0, iclass 22, count 2 2006.257.03:29:06.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:06.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:06.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.03:29:06.43#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:06.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:06.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:06.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:06.55#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:29:06.55#ibcon#first serial, iclass 22, count 0 2006.257.03:29:06.55#ibcon#enter sib2, iclass 22, count 0 2006.257.03:29:06.55#ibcon#flushed, iclass 22, count 0 2006.257.03:29:06.55#ibcon#about to write, iclass 22, count 0 2006.257.03:29:06.55#ibcon#wrote, iclass 22, count 0 2006.257.03:29:06.55#ibcon#about to read 3, iclass 22, count 0 2006.257.03:29:06.57#ibcon#read 3, iclass 22, count 0 2006.257.03:29:06.57#ibcon#about to read 4, iclass 22, count 0 2006.257.03:29:06.57#ibcon#read 4, iclass 22, count 0 2006.257.03:29:06.57#ibcon#about to read 5, iclass 22, count 0 2006.257.03:29:06.57#ibcon#read 5, iclass 22, count 0 2006.257.03:29:06.57#ibcon#about to read 6, iclass 22, count 0 2006.257.03:29:06.57#ibcon#read 6, iclass 22, count 0 2006.257.03:29:06.57#ibcon#end of sib2, iclass 22, count 0 2006.257.03:29:06.57#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:29:06.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:29:06.57#ibcon#[25=USB\r\n] 2006.257.03:29:06.57#ibcon#*before write, iclass 22, count 0 2006.257.03:29:06.57#ibcon#enter sib2, iclass 22, count 0 2006.257.03:29:06.57#ibcon#flushed, iclass 22, count 0 2006.257.03:29:06.57#ibcon#about to write, iclass 22, count 0 2006.257.03:29:06.57#ibcon#wrote, iclass 22, count 0 2006.257.03:29:06.57#ibcon#about to read 3, iclass 22, count 0 2006.257.03:29:06.60#ibcon#read 3, iclass 22, count 0 2006.257.03:29:06.60#ibcon#about to read 4, iclass 22, count 0 2006.257.03:29:06.60#ibcon#read 4, iclass 22, count 0 2006.257.03:29:06.60#ibcon#about to read 5, iclass 22, count 0 2006.257.03:29:06.60#ibcon#read 5, iclass 22, count 0 2006.257.03:29:06.60#ibcon#about to read 6, iclass 22, count 0 2006.257.03:29:06.60#ibcon#read 6, iclass 22, count 0 2006.257.03:29:06.60#ibcon#end of sib2, iclass 22, count 0 2006.257.03:29:06.60#ibcon#*after write, iclass 22, count 0 2006.257.03:29:06.60#ibcon#*before return 0, iclass 22, count 0 2006.257.03:29:06.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:06.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:06.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:29:06.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:29:06.60$vck44/valo=4,624.99 2006.257.03:29:06.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.03:29:06.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.03:29:06.60#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:06.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:06.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:06.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:06.60#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:29:06.60#ibcon#first serial, iclass 24, count 0 2006.257.03:29:06.60#ibcon#enter sib2, iclass 24, count 0 2006.257.03:29:06.60#ibcon#flushed, iclass 24, count 0 2006.257.03:29:06.60#ibcon#about to write, iclass 24, count 0 2006.257.03:29:06.60#ibcon#wrote, iclass 24, count 0 2006.257.03:29:06.60#ibcon#about to read 3, iclass 24, count 0 2006.257.03:29:06.62#ibcon#read 3, iclass 24, count 0 2006.257.03:29:06.62#ibcon#about to read 4, iclass 24, count 0 2006.257.03:29:06.62#ibcon#read 4, iclass 24, count 0 2006.257.03:29:06.62#ibcon#about to read 5, iclass 24, count 0 2006.257.03:29:06.62#ibcon#read 5, iclass 24, count 0 2006.257.03:29:06.62#ibcon#about to read 6, iclass 24, count 0 2006.257.03:29:06.62#ibcon#read 6, iclass 24, count 0 2006.257.03:29:06.62#ibcon#end of sib2, iclass 24, count 0 2006.257.03:29:06.62#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:29:06.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:29:06.62#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:29:06.62#ibcon#*before write, iclass 24, count 0 2006.257.03:29:06.62#ibcon#enter sib2, iclass 24, count 0 2006.257.03:29:06.62#ibcon#flushed, iclass 24, count 0 2006.257.03:29:06.62#ibcon#about to write, iclass 24, count 0 2006.257.03:29:06.62#ibcon#wrote, iclass 24, count 0 2006.257.03:29:06.62#ibcon#about to read 3, iclass 24, count 0 2006.257.03:29:06.66#ibcon#read 3, iclass 24, count 0 2006.257.03:29:06.66#ibcon#about to read 4, iclass 24, count 0 2006.257.03:29:06.66#ibcon#read 4, iclass 24, count 0 2006.257.03:29:06.66#ibcon#about to read 5, iclass 24, count 0 2006.257.03:29:06.66#ibcon#read 5, iclass 24, count 0 2006.257.03:29:06.66#ibcon#about to read 6, iclass 24, count 0 2006.257.03:29:06.66#ibcon#read 6, iclass 24, count 0 2006.257.03:29:06.66#ibcon#end of sib2, iclass 24, count 0 2006.257.03:29:06.66#ibcon#*after write, iclass 24, count 0 2006.257.03:29:06.66#ibcon#*before return 0, iclass 24, count 0 2006.257.03:29:06.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:06.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:06.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:29:06.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:29:06.66$vck44/va=4,7 2006.257.03:29:06.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.03:29:06.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.03:29:06.66#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:06.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:06.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:06.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:06.72#ibcon#enter wrdev, iclass 26, count 2 2006.257.03:29:06.72#ibcon#first serial, iclass 26, count 2 2006.257.03:29:06.72#ibcon#enter sib2, iclass 26, count 2 2006.257.03:29:06.72#ibcon#flushed, iclass 26, count 2 2006.257.03:29:06.72#ibcon#about to write, iclass 26, count 2 2006.257.03:29:06.72#ibcon#wrote, iclass 26, count 2 2006.257.03:29:06.72#ibcon#about to read 3, iclass 26, count 2 2006.257.03:29:06.74#ibcon#read 3, iclass 26, count 2 2006.257.03:29:06.74#ibcon#about to read 4, iclass 26, count 2 2006.257.03:29:06.74#ibcon#read 4, iclass 26, count 2 2006.257.03:29:06.74#ibcon#about to read 5, iclass 26, count 2 2006.257.03:29:06.74#ibcon#read 5, iclass 26, count 2 2006.257.03:29:06.74#ibcon#about to read 6, iclass 26, count 2 2006.257.03:29:06.74#ibcon#read 6, iclass 26, count 2 2006.257.03:29:06.74#ibcon#end of sib2, iclass 26, count 2 2006.257.03:29:06.74#ibcon#*mode == 0, iclass 26, count 2 2006.257.03:29:06.74#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.03:29:06.74#ibcon#[25=AT04-07\r\n] 2006.257.03:29:06.74#ibcon#*before write, iclass 26, count 2 2006.257.03:29:06.74#ibcon#enter sib2, iclass 26, count 2 2006.257.03:29:06.74#ibcon#flushed, iclass 26, count 2 2006.257.03:29:06.74#ibcon#about to write, iclass 26, count 2 2006.257.03:29:06.74#ibcon#wrote, iclass 26, count 2 2006.257.03:29:06.74#ibcon#about to read 3, iclass 26, count 2 2006.257.03:29:06.77#ibcon#read 3, iclass 26, count 2 2006.257.03:29:06.77#ibcon#about to read 4, iclass 26, count 2 2006.257.03:29:06.77#ibcon#read 4, iclass 26, count 2 2006.257.03:29:06.77#ibcon#about to read 5, iclass 26, count 2 2006.257.03:29:06.77#ibcon#read 5, iclass 26, count 2 2006.257.03:29:06.77#ibcon#about to read 6, iclass 26, count 2 2006.257.03:29:06.77#ibcon#read 6, iclass 26, count 2 2006.257.03:29:06.77#ibcon#end of sib2, iclass 26, count 2 2006.257.03:29:06.77#ibcon#*after write, iclass 26, count 2 2006.257.03:29:06.77#ibcon#*before return 0, iclass 26, count 2 2006.257.03:29:06.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:06.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:06.77#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.03:29:06.77#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:06.77#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:06.89#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:06.89#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:06.89#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:29:06.89#ibcon#first serial, iclass 26, count 0 2006.257.03:29:06.89#ibcon#enter sib2, iclass 26, count 0 2006.257.03:29:06.89#ibcon#flushed, iclass 26, count 0 2006.257.03:29:06.89#ibcon#about to write, iclass 26, count 0 2006.257.03:29:06.89#ibcon#wrote, iclass 26, count 0 2006.257.03:29:06.89#ibcon#about to read 3, iclass 26, count 0 2006.257.03:29:06.91#ibcon#read 3, iclass 26, count 0 2006.257.03:29:06.91#ibcon#about to read 4, iclass 26, count 0 2006.257.03:29:06.91#ibcon#read 4, iclass 26, count 0 2006.257.03:29:06.91#ibcon#about to read 5, iclass 26, count 0 2006.257.03:29:06.91#ibcon#read 5, iclass 26, count 0 2006.257.03:29:06.91#ibcon#about to read 6, iclass 26, count 0 2006.257.03:29:06.91#ibcon#read 6, iclass 26, count 0 2006.257.03:29:06.91#ibcon#end of sib2, iclass 26, count 0 2006.257.03:29:06.91#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:29:06.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:29:06.91#ibcon#[25=USB\r\n] 2006.257.03:29:06.91#ibcon#*before write, iclass 26, count 0 2006.257.03:29:06.91#ibcon#enter sib2, iclass 26, count 0 2006.257.03:29:06.91#ibcon#flushed, iclass 26, count 0 2006.257.03:29:06.91#ibcon#about to write, iclass 26, count 0 2006.257.03:29:06.91#ibcon#wrote, iclass 26, count 0 2006.257.03:29:06.91#ibcon#about to read 3, iclass 26, count 0 2006.257.03:29:06.94#ibcon#read 3, iclass 26, count 0 2006.257.03:29:06.94#ibcon#about to read 4, iclass 26, count 0 2006.257.03:29:06.94#ibcon#read 4, iclass 26, count 0 2006.257.03:29:06.94#ibcon#about to read 5, iclass 26, count 0 2006.257.03:29:06.94#ibcon#read 5, iclass 26, count 0 2006.257.03:29:06.94#ibcon#about to read 6, iclass 26, count 0 2006.257.03:29:06.94#ibcon#read 6, iclass 26, count 0 2006.257.03:29:06.94#ibcon#end of sib2, iclass 26, count 0 2006.257.03:29:06.94#ibcon#*after write, iclass 26, count 0 2006.257.03:29:06.94#ibcon#*before return 0, iclass 26, count 0 2006.257.03:29:06.94#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:06.94#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:06.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:29:06.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:29:06.94$vck44/valo=5,734.99 2006.257.03:29:06.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.03:29:06.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.03:29:06.94#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:06.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:06.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:06.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:06.94#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:29:06.94#ibcon#first serial, iclass 28, count 0 2006.257.03:29:06.94#ibcon#enter sib2, iclass 28, count 0 2006.257.03:29:06.94#ibcon#flushed, iclass 28, count 0 2006.257.03:29:06.94#ibcon#about to write, iclass 28, count 0 2006.257.03:29:06.94#ibcon#wrote, iclass 28, count 0 2006.257.03:29:06.94#ibcon#about to read 3, iclass 28, count 0 2006.257.03:29:06.96#ibcon#read 3, iclass 28, count 0 2006.257.03:29:06.96#ibcon#about to read 4, iclass 28, count 0 2006.257.03:29:06.96#ibcon#read 4, iclass 28, count 0 2006.257.03:29:06.96#ibcon#about to read 5, iclass 28, count 0 2006.257.03:29:06.96#ibcon#read 5, iclass 28, count 0 2006.257.03:29:06.96#ibcon#about to read 6, iclass 28, count 0 2006.257.03:29:06.96#ibcon#read 6, iclass 28, count 0 2006.257.03:29:06.96#ibcon#end of sib2, iclass 28, count 0 2006.257.03:29:06.96#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:29:06.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:29:06.96#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:29:06.96#ibcon#*before write, iclass 28, count 0 2006.257.03:29:06.96#ibcon#enter sib2, iclass 28, count 0 2006.257.03:29:06.96#ibcon#flushed, iclass 28, count 0 2006.257.03:29:06.96#ibcon#about to write, iclass 28, count 0 2006.257.03:29:06.96#ibcon#wrote, iclass 28, count 0 2006.257.03:29:06.96#ibcon#about to read 3, iclass 28, count 0 2006.257.03:29:07.00#ibcon#read 3, iclass 28, count 0 2006.257.03:29:07.00#ibcon#about to read 4, iclass 28, count 0 2006.257.03:29:07.00#ibcon#read 4, iclass 28, count 0 2006.257.03:29:07.00#ibcon#about to read 5, iclass 28, count 0 2006.257.03:29:07.00#ibcon#read 5, iclass 28, count 0 2006.257.03:29:07.00#ibcon#about to read 6, iclass 28, count 0 2006.257.03:29:07.00#ibcon#read 6, iclass 28, count 0 2006.257.03:29:07.00#ibcon#end of sib2, iclass 28, count 0 2006.257.03:29:07.00#ibcon#*after write, iclass 28, count 0 2006.257.03:29:07.00#ibcon#*before return 0, iclass 28, count 0 2006.257.03:29:07.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:07.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:07.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:29:07.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:29:07.00$vck44/va=5,4 2006.257.03:29:07.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.03:29:07.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.03:29:07.00#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:07.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:07.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:07.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:07.06#ibcon#enter wrdev, iclass 30, count 2 2006.257.03:29:07.06#ibcon#first serial, iclass 30, count 2 2006.257.03:29:07.06#ibcon#enter sib2, iclass 30, count 2 2006.257.03:29:07.06#ibcon#flushed, iclass 30, count 2 2006.257.03:29:07.06#ibcon#about to write, iclass 30, count 2 2006.257.03:29:07.06#ibcon#wrote, iclass 30, count 2 2006.257.03:29:07.06#ibcon#about to read 3, iclass 30, count 2 2006.257.03:29:07.08#ibcon#read 3, iclass 30, count 2 2006.257.03:29:07.08#ibcon#about to read 4, iclass 30, count 2 2006.257.03:29:07.08#ibcon#read 4, iclass 30, count 2 2006.257.03:29:07.08#ibcon#about to read 5, iclass 30, count 2 2006.257.03:29:07.08#ibcon#read 5, iclass 30, count 2 2006.257.03:29:07.08#ibcon#about to read 6, iclass 30, count 2 2006.257.03:29:07.08#ibcon#read 6, iclass 30, count 2 2006.257.03:29:07.08#ibcon#end of sib2, iclass 30, count 2 2006.257.03:29:07.08#ibcon#*mode == 0, iclass 30, count 2 2006.257.03:29:07.08#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.03:29:07.08#ibcon#[25=AT05-04\r\n] 2006.257.03:29:07.08#ibcon#*before write, iclass 30, count 2 2006.257.03:29:07.08#ibcon#enter sib2, iclass 30, count 2 2006.257.03:29:07.08#ibcon#flushed, iclass 30, count 2 2006.257.03:29:07.08#ibcon#about to write, iclass 30, count 2 2006.257.03:29:07.08#ibcon#wrote, iclass 30, count 2 2006.257.03:29:07.08#ibcon#about to read 3, iclass 30, count 2 2006.257.03:29:07.11#ibcon#read 3, iclass 30, count 2 2006.257.03:29:07.11#ibcon#about to read 4, iclass 30, count 2 2006.257.03:29:07.11#ibcon#read 4, iclass 30, count 2 2006.257.03:29:07.11#ibcon#about to read 5, iclass 30, count 2 2006.257.03:29:07.11#ibcon#read 5, iclass 30, count 2 2006.257.03:29:07.11#ibcon#about to read 6, iclass 30, count 2 2006.257.03:29:07.11#ibcon#read 6, iclass 30, count 2 2006.257.03:29:07.11#ibcon#end of sib2, iclass 30, count 2 2006.257.03:29:07.11#ibcon#*after write, iclass 30, count 2 2006.257.03:29:07.11#ibcon#*before return 0, iclass 30, count 2 2006.257.03:29:07.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:07.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:07.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.03:29:07.11#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:07.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:07.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:07.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:07.23#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:29:07.23#ibcon#first serial, iclass 30, count 0 2006.257.03:29:07.23#ibcon#enter sib2, iclass 30, count 0 2006.257.03:29:07.23#ibcon#flushed, iclass 30, count 0 2006.257.03:29:07.23#ibcon#about to write, iclass 30, count 0 2006.257.03:29:07.23#ibcon#wrote, iclass 30, count 0 2006.257.03:29:07.23#ibcon#about to read 3, iclass 30, count 0 2006.257.03:29:07.25#ibcon#read 3, iclass 30, count 0 2006.257.03:29:07.25#ibcon#about to read 4, iclass 30, count 0 2006.257.03:29:07.25#ibcon#read 4, iclass 30, count 0 2006.257.03:29:07.25#ibcon#about to read 5, iclass 30, count 0 2006.257.03:29:07.25#ibcon#read 5, iclass 30, count 0 2006.257.03:29:07.25#ibcon#about to read 6, iclass 30, count 0 2006.257.03:29:07.25#ibcon#read 6, iclass 30, count 0 2006.257.03:29:07.25#ibcon#end of sib2, iclass 30, count 0 2006.257.03:29:07.25#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:29:07.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:29:07.25#ibcon#[25=USB\r\n] 2006.257.03:29:07.25#ibcon#*before write, iclass 30, count 0 2006.257.03:29:07.25#ibcon#enter sib2, iclass 30, count 0 2006.257.03:29:07.25#ibcon#flushed, iclass 30, count 0 2006.257.03:29:07.25#ibcon#about to write, iclass 30, count 0 2006.257.03:29:07.25#ibcon#wrote, iclass 30, count 0 2006.257.03:29:07.25#ibcon#about to read 3, iclass 30, count 0 2006.257.03:29:07.28#ibcon#read 3, iclass 30, count 0 2006.257.03:29:07.28#ibcon#about to read 4, iclass 30, count 0 2006.257.03:29:07.28#ibcon#read 4, iclass 30, count 0 2006.257.03:29:07.28#ibcon#about to read 5, iclass 30, count 0 2006.257.03:29:07.28#ibcon#read 5, iclass 30, count 0 2006.257.03:29:07.28#ibcon#about to read 6, iclass 30, count 0 2006.257.03:29:07.28#ibcon#read 6, iclass 30, count 0 2006.257.03:29:07.28#ibcon#end of sib2, iclass 30, count 0 2006.257.03:29:07.28#ibcon#*after write, iclass 30, count 0 2006.257.03:29:07.28#ibcon#*before return 0, iclass 30, count 0 2006.257.03:29:07.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:07.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:07.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:29:07.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:29:07.28$vck44/valo=6,814.99 2006.257.03:29:07.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.03:29:07.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.03:29:07.28#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:07.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:07.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:07.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:07.28#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:29:07.28#ibcon#first serial, iclass 32, count 0 2006.257.03:29:07.28#ibcon#enter sib2, iclass 32, count 0 2006.257.03:29:07.28#ibcon#flushed, iclass 32, count 0 2006.257.03:29:07.28#ibcon#about to write, iclass 32, count 0 2006.257.03:29:07.28#ibcon#wrote, iclass 32, count 0 2006.257.03:29:07.28#ibcon#about to read 3, iclass 32, count 0 2006.257.03:29:07.30#ibcon#read 3, iclass 32, count 0 2006.257.03:29:07.30#ibcon#about to read 4, iclass 32, count 0 2006.257.03:29:07.30#ibcon#read 4, iclass 32, count 0 2006.257.03:29:07.30#ibcon#about to read 5, iclass 32, count 0 2006.257.03:29:07.30#ibcon#read 5, iclass 32, count 0 2006.257.03:29:07.30#ibcon#about to read 6, iclass 32, count 0 2006.257.03:29:07.30#ibcon#read 6, iclass 32, count 0 2006.257.03:29:07.30#ibcon#end of sib2, iclass 32, count 0 2006.257.03:29:07.30#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:29:07.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:29:07.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:29:07.30#ibcon#*before write, iclass 32, count 0 2006.257.03:29:07.30#ibcon#enter sib2, iclass 32, count 0 2006.257.03:29:07.30#ibcon#flushed, iclass 32, count 0 2006.257.03:29:07.30#ibcon#about to write, iclass 32, count 0 2006.257.03:29:07.30#ibcon#wrote, iclass 32, count 0 2006.257.03:29:07.30#ibcon#about to read 3, iclass 32, count 0 2006.257.03:29:07.34#ibcon#read 3, iclass 32, count 0 2006.257.03:29:07.34#ibcon#about to read 4, iclass 32, count 0 2006.257.03:29:07.34#ibcon#read 4, iclass 32, count 0 2006.257.03:29:07.34#ibcon#about to read 5, iclass 32, count 0 2006.257.03:29:07.34#ibcon#read 5, iclass 32, count 0 2006.257.03:29:07.34#ibcon#about to read 6, iclass 32, count 0 2006.257.03:29:07.34#ibcon#read 6, iclass 32, count 0 2006.257.03:29:07.34#ibcon#end of sib2, iclass 32, count 0 2006.257.03:29:07.34#ibcon#*after write, iclass 32, count 0 2006.257.03:29:07.34#ibcon#*before return 0, iclass 32, count 0 2006.257.03:29:07.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:07.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:07.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:29:07.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:29:07.34$vck44/va=6,4 2006.257.03:29:07.34#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.03:29:07.34#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.03:29:07.34#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:07.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:07.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:07.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:07.40#ibcon#enter wrdev, iclass 34, count 2 2006.257.03:29:07.40#ibcon#first serial, iclass 34, count 2 2006.257.03:29:07.40#ibcon#enter sib2, iclass 34, count 2 2006.257.03:29:07.40#ibcon#flushed, iclass 34, count 2 2006.257.03:29:07.40#ibcon#about to write, iclass 34, count 2 2006.257.03:29:07.40#ibcon#wrote, iclass 34, count 2 2006.257.03:29:07.40#ibcon#about to read 3, iclass 34, count 2 2006.257.03:29:07.42#ibcon#read 3, iclass 34, count 2 2006.257.03:29:07.42#ibcon#about to read 4, iclass 34, count 2 2006.257.03:29:07.42#ibcon#read 4, iclass 34, count 2 2006.257.03:29:07.42#ibcon#about to read 5, iclass 34, count 2 2006.257.03:29:07.42#ibcon#read 5, iclass 34, count 2 2006.257.03:29:07.42#ibcon#about to read 6, iclass 34, count 2 2006.257.03:29:07.42#ibcon#read 6, iclass 34, count 2 2006.257.03:29:07.42#ibcon#end of sib2, iclass 34, count 2 2006.257.03:29:07.42#ibcon#*mode == 0, iclass 34, count 2 2006.257.03:29:07.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.03:29:07.42#ibcon#[25=AT06-04\r\n] 2006.257.03:29:07.42#ibcon#*before write, iclass 34, count 2 2006.257.03:29:07.42#ibcon#enter sib2, iclass 34, count 2 2006.257.03:29:07.42#ibcon#flushed, iclass 34, count 2 2006.257.03:29:07.42#ibcon#about to write, iclass 34, count 2 2006.257.03:29:07.42#ibcon#wrote, iclass 34, count 2 2006.257.03:29:07.42#ibcon#about to read 3, iclass 34, count 2 2006.257.03:29:07.45#ibcon#read 3, iclass 34, count 2 2006.257.03:29:07.45#ibcon#about to read 4, iclass 34, count 2 2006.257.03:29:07.45#ibcon#read 4, iclass 34, count 2 2006.257.03:29:07.45#ibcon#about to read 5, iclass 34, count 2 2006.257.03:29:07.45#ibcon#read 5, iclass 34, count 2 2006.257.03:29:07.45#ibcon#about to read 6, iclass 34, count 2 2006.257.03:29:07.45#ibcon#read 6, iclass 34, count 2 2006.257.03:29:07.45#ibcon#end of sib2, iclass 34, count 2 2006.257.03:29:07.45#ibcon#*after write, iclass 34, count 2 2006.257.03:29:07.45#ibcon#*before return 0, iclass 34, count 2 2006.257.03:29:07.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:07.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:07.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.03:29:07.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:07.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:07.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:07.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:07.57#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:29:07.57#ibcon#first serial, iclass 34, count 0 2006.257.03:29:07.57#ibcon#enter sib2, iclass 34, count 0 2006.257.03:29:07.57#ibcon#flushed, iclass 34, count 0 2006.257.03:29:07.57#ibcon#about to write, iclass 34, count 0 2006.257.03:29:07.57#ibcon#wrote, iclass 34, count 0 2006.257.03:29:07.57#ibcon#about to read 3, iclass 34, count 0 2006.257.03:29:07.59#ibcon#read 3, iclass 34, count 0 2006.257.03:29:07.59#ibcon#about to read 4, iclass 34, count 0 2006.257.03:29:07.59#ibcon#read 4, iclass 34, count 0 2006.257.03:29:07.59#ibcon#about to read 5, iclass 34, count 0 2006.257.03:29:07.59#ibcon#read 5, iclass 34, count 0 2006.257.03:29:07.59#ibcon#about to read 6, iclass 34, count 0 2006.257.03:29:07.59#ibcon#read 6, iclass 34, count 0 2006.257.03:29:07.59#ibcon#end of sib2, iclass 34, count 0 2006.257.03:29:07.59#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:29:07.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:29:07.59#ibcon#[25=USB\r\n] 2006.257.03:29:07.59#ibcon#*before write, iclass 34, count 0 2006.257.03:29:07.59#ibcon#enter sib2, iclass 34, count 0 2006.257.03:29:07.59#ibcon#flushed, iclass 34, count 0 2006.257.03:29:07.59#ibcon#about to write, iclass 34, count 0 2006.257.03:29:07.59#ibcon#wrote, iclass 34, count 0 2006.257.03:29:07.59#ibcon#about to read 3, iclass 34, count 0 2006.257.03:29:07.62#ibcon#read 3, iclass 34, count 0 2006.257.03:29:07.62#ibcon#about to read 4, iclass 34, count 0 2006.257.03:29:07.62#ibcon#read 4, iclass 34, count 0 2006.257.03:29:07.62#ibcon#about to read 5, iclass 34, count 0 2006.257.03:29:07.62#ibcon#read 5, iclass 34, count 0 2006.257.03:29:07.62#ibcon#about to read 6, iclass 34, count 0 2006.257.03:29:07.62#ibcon#read 6, iclass 34, count 0 2006.257.03:29:07.62#ibcon#end of sib2, iclass 34, count 0 2006.257.03:29:07.62#ibcon#*after write, iclass 34, count 0 2006.257.03:29:07.62#ibcon#*before return 0, iclass 34, count 0 2006.257.03:29:07.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:07.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:07.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:29:07.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:29:07.62$vck44/valo=7,864.99 2006.257.03:29:07.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.03:29:07.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.03:29:07.62#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:07.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:07.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:07.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:07.62#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:29:07.62#ibcon#first serial, iclass 36, count 0 2006.257.03:29:07.62#ibcon#enter sib2, iclass 36, count 0 2006.257.03:29:07.62#ibcon#flushed, iclass 36, count 0 2006.257.03:29:07.62#ibcon#about to write, iclass 36, count 0 2006.257.03:29:07.62#ibcon#wrote, iclass 36, count 0 2006.257.03:29:07.62#ibcon#about to read 3, iclass 36, count 0 2006.257.03:29:07.64#ibcon#read 3, iclass 36, count 0 2006.257.03:29:07.64#ibcon#about to read 4, iclass 36, count 0 2006.257.03:29:07.64#ibcon#read 4, iclass 36, count 0 2006.257.03:29:07.64#ibcon#about to read 5, iclass 36, count 0 2006.257.03:29:07.64#ibcon#read 5, iclass 36, count 0 2006.257.03:29:07.64#ibcon#about to read 6, iclass 36, count 0 2006.257.03:29:07.64#ibcon#read 6, iclass 36, count 0 2006.257.03:29:07.64#ibcon#end of sib2, iclass 36, count 0 2006.257.03:29:07.64#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:29:07.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:29:07.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:29:07.64#ibcon#*before write, iclass 36, count 0 2006.257.03:29:07.64#ibcon#enter sib2, iclass 36, count 0 2006.257.03:29:07.64#ibcon#flushed, iclass 36, count 0 2006.257.03:29:07.64#ibcon#about to write, iclass 36, count 0 2006.257.03:29:07.64#ibcon#wrote, iclass 36, count 0 2006.257.03:29:07.64#ibcon#about to read 3, iclass 36, count 0 2006.257.03:29:07.68#ibcon#read 3, iclass 36, count 0 2006.257.03:29:07.68#ibcon#about to read 4, iclass 36, count 0 2006.257.03:29:07.68#ibcon#read 4, iclass 36, count 0 2006.257.03:29:07.68#ibcon#about to read 5, iclass 36, count 0 2006.257.03:29:07.68#ibcon#read 5, iclass 36, count 0 2006.257.03:29:07.68#ibcon#about to read 6, iclass 36, count 0 2006.257.03:29:07.68#ibcon#read 6, iclass 36, count 0 2006.257.03:29:07.68#ibcon#end of sib2, iclass 36, count 0 2006.257.03:29:07.68#ibcon#*after write, iclass 36, count 0 2006.257.03:29:07.68#ibcon#*before return 0, iclass 36, count 0 2006.257.03:29:07.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:07.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:07.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:29:07.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:29:07.68$vck44/va=7,4 2006.257.03:29:07.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.03:29:07.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.03:29:07.68#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:07.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:07.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:07.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:07.74#ibcon#enter wrdev, iclass 38, count 2 2006.257.03:29:07.74#ibcon#first serial, iclass 38, count 2 2006.257.03:29:07.74#ibcon#enter sib2, iclass 38, count 2 2006.257.03:29:07.74#ibcon#flushed, iclass 38, count 2 2006.257.03:29:07.74#ibcon#about to write, iclass 38, count 2 2006.257.03:29:07.74#ibcon#wrote, iclass 38, count 2 2006.257.03:29:07.74#ibcon#about to read 3, iclass 38, count 2 2006.257.03:29:07.76#ibcon#read 3, iclass 38, count 2 2006.257.03:29:07.76#ibcon#about to read 4, iclass 38, count 2 2006.257.03:29:07.76#ibcon#read 4, iclass 38, count 2 2006.257.03:29:07.76#ibcon#about to read 5, iclass 38, count 2 2006.257.03:29:07.76#ibcon#read 5, iclass 38, count 2 2006.257.03:29:07.76#ibcon#about to read 6, iclass 38, count 2 2006.257.03:29:07.76#ibcon#read 6, iclass 38, count 2 2006.257.03:29:07.76#ibcon#end of sib2, iclass 38, count 2 2006.257.03:29:07.76#ibcon#*mode == 0, iclass 38, count 2 2006.257.03:29:07.76#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.03:29:07.76#ibcon#[25=AT07-04\r\n] 2006.257.03:29:07.76#ibcon#*before write, iclass 38, count 2 2006.257.03:29:07.76#ibcon#enter sib2, iclass 38, count 2 2006.257.03:29:07.76#ibcon#flushed, iclass 38, count 2 2006.257.03:29:07.76#ibcon#about to write, iclass 38, count 2 2006.257.03:29:07.76#ibcon#wrote, iclass 38, count 2 2006.257.03:29:07.76#ibcon#about to read 3, iclass 38, count 2 2006.257.03:29:07.79#ibcon#read 3, iclass 38, count 2 2006.257.03:29:07.79#ibcon#about to read 4, iclass 38, count 2 2006.257.03:29:07.79#ibcon#read 4, iclass 38, count 2 2006.257.03:29:07.79#ibcon#about to read 5, iclass 38, count 2 2006.257.03:29:07.79#ibcon#read 5, iclass 38, count 2 2006.257.03:29:07.79#ibcon#about to read 6, iclass 38, count 2 2006.257.03:29:07.79#ibcon#read 6, iclass 38, count 2 2006.257.03:29:07.79#ibcon#end of sib2, iclass 38, count 2 2006.257.03:29:07.79#ibcon#*after write, iclass 38, count 2 2006.257.03:29:07.79#ibcon#*before return 0, iclass 38, count 2 2006.257.03:29:07.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:07.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:07.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.03:29:07.79#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:07.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:07.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:07.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:07.91#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:29:07.91#ibcon#first serial, iclass 38, count 0 2006.257.03:29:07.91#ibcon#enter sib2, iclass 38, count 0 2006.257.03:29:07.91#ibcon#flushed, iclass 38, count 0 2006.257.03:29:07.91#ibcon#about to write, iclass 38, count 0 2006.257.03:29:07.91#ibcon#wrote, iclass 38, count 0 2006.257.03:29:07.91#ibcon#about to read 3, iclass 38, count 0 2006.257.03:29:07.93#ibcon#read 3, iclass 38, count 0 2006.257.03:29:07.93#ibcon#about to read 4, iclass 38, count 0 2006.257.03:29:07.93#ibcon#read 4, iclass 38, count 0 2006.257.03:29:07.93#ibcon#about to read 5, iclass 38, count 0 2006.257.03:29:07.93#ibcon#read 5, iclass 38, count 0 2006.257.03:29:07.93#ibcon#about to read 6, iclass 38, count 0 2006.257.03:29:07.93#ibcon#read 6, iclass 38, count 0 2006.257.03:29:07.93#ibcon#end of sib2, iclass 38, count 0 2006.257.03:29:07.93#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:29:07.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:29:07.93#ibcon#[25=USB\r\n] 2006.257.03:29:07.93#ibcon#*before write, iclass 38, count 0 2006.257.03:29:07.93#ibcon#enter sib2, iclass 38, count 0 2006.257.03:29:07.93#ibcon#flushed, iclass 38, count 0 2006.257.03:29:07.93#ibcon#about to write, iclass 38, count 0 2006.257.03:29:07.93#ibcon#wrote, iclass 38, count 0 2006.257.03:29:07.93#ibcon#about to read 3, iclass 38, count 0 2006.257.03:29:07.96#ibcon#read 3, iclass 38, count 0 2006.257.03:29:07.96#ibcon#about to read 4, iclass 38, count 0 2006.257.03:29:07.96#ibcon#read 4, iclass 38, count 0 2006.257.03:29:07.96#ibcon#about to read 5, iclass 38, count 0 2006.257.03:29:07.96#ibcon#read 5, iclass 38, count 0 2006.257.03:29:07.96#ibcon#about to read 6, iclass 38, count 0 2006.257.03:29:07.96#ibcon#read 6, iclass 38, count 0 2006.257.03:29:07.96#ibcon#end of sib2, iclass 38, count 0 2006.257.03:29:07.96#ibcon#*after write, iclass 38, count 0 2006.257.03:29:07.96#ibcon#*before return 0, iclass 38, count 0 2006.257.03:29:07.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:07.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:07.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:29:07.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:29:07.96$vck44/valo=8,884.99 2006.257.03:29:07.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.03:29:07.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.03:29:07.96#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:07.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:07.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:07.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:07.96#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:29:07.96#ibcon#first serial, iclass 40, count 0 2006.257.03:29:07.96#ibcon#enter sib2, iclass 40, count 0 2006.257.03:29:07.96#ibcon#flushed, iclass 40, count 0 2006.257.03:29:07.96#ibcon#about to write, iclass 40, count 0 2006.257.03:29:07.96#ibcon#wrote, iclass 40, count 0 2006.257.03:29:07.96#ibcon#about to read 3, iclass 40, count 0 2006.257.03:29:07.98#ibcon#read 3, iclass 40, count 0 2006.257.03:29:07.98#ibcon#about to read 4, iclass 40, count 0 2006.257.03:29:07.98#ibcon#read 4, iclass 40, count 0 2006.257.03:29:07.98#ibcon#about to read 5, iclass 40, count 0 2006.257.03:29:07.98#ibcon#read 5, iclass 40, count 0 2006.257.03:29:07.98#ibcon#about to read 6, iclass 40, count 0 2006.257.03:29:07.98#ibcon#read 6, iclass 40, count 0 2006.257.03:29:07.98#ibcon#end of sib2, iclass 40, count 0 2006.257.03:29:07.98#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:29:07.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:29:07.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:29:07.98#ibcon#*before write, iclass 40, count 0 2006.257.03:29:07.98#ibcon#enter sib2, iclass 40, count 0 2006.257.03:29:07.98#ibcon#flushed, iclass 40, count 0 2006.257.03:29:07.98#ibcon#about to write, iclass 40, count 0 2006.257.03:29:07.98#ibcon#wrote, iclass 40, count 0 2006.257.03:29:07.98#ibcon#about to read 3, iclass 40, count 0 2006.257.03:29:08.02#ibcon#read 3, iclass 40, count 0 2006.257.03:29:08.02#ibcon#about to read 4, iclass 40, count 0 2006.257.03:29:08.02#ibcon#read 4, iclass 40, count 0 2006.257.03:29:08.02#ibcon#about to read 5, iclass 40, count 0 2006.257.03:29:08.02#ibcon#read 5, iclass 40, count 0 2006.257.03:29:08.02#ibcon#about to read 6, iclass 40, count 0 2006.257.03:29:08.02#ibcon#read 6, iclass 40, count 0 2006.257.03:29:08.02#ibcon#end of sib2, iclass 40, count 0 2006.257.03:29:08.02#ibcon#*after write, iclass 40, count 0 2006.257.03:29:08.02#ibcon#*before return 0, iclass 40, count 0 2006.257.03:29:08.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:08.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:08.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:29:08.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:29:08.02$vck44/va=8,4 2006.257.03:29:08.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.03:29:08.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.03:29:08.02#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:08.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:29:08.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:29:08.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:29:08.08#ibcon#enter wrdev, iclass 4, count 2 2006.257.03:29:08.08#ibcon#first serial, iclass 4, count 2 2006.257.03:29:08.08#ibcon#enter sib2, iclass 4, count 2 2006.257.03:29:08.08#ibcon#flushed, iclass 4, count 2 2006.257.03:29:08.08#ibcon#about to write, iclass 4, count 2 2006.257.03:29:08.08#ibcon#wrote, iclass 4, count 2 2006.257.03:29:08.08#ibcon#about to read 3, iclass 4, count 2 2006.257.03:29:08.10#ibcon#read 3, iclass 4, count 2 2006.257.03:29:08.10#ibcon#about to read 4, iclass 4, count 2 2006.257.03:29:08.10#ibcon#read 4, iclass 4, count 2 2006.257.03:29:08.10#ibcon#about to read 5, iclass 4, count 2 2006.257.03:29:08.10#ibcon#read 5, iclass 4, count 2 2006.257.03:29:08.10#ibcon#about to read 6, iclass 4, count 2 2006.257.03:29:08.10#ibcon#read 6, iclass 4, count 2 2006.257.03:29:08.10#ibcon#end of sib2, iclass 4, count 2 2006.257.03:29:08.10#ibcon#*mode == 0, iclass 4, count 2 2006.257.03:29:08.10#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.03:29:08.10#ibcon#[25=AT08-04\r\n] 2006.257.03:29:08.10#ibcon#*before write, iclass 4, count 2 2006.257.03:29:08.10#ibcon#enter sib2, iclass 4, count 2 2006.257.03:29:08.10#ibcon#flushed, iclass 4, count 2 2006.257.03:29:08.10#ibcon#about to write, iclass 4, count 2 2006.257.03:29:08.10#ibcon#wrote, iclass 4, count 2 2006.257.03:29:08.10#ibcon#about to read 3, iclass 4, count 2 2006.257.03:29:08.13#ibcon#read 3, iclass 4, count 2 2006.257.03:29:08.13#ibcon#about to read 4, iclass 4, count 2 2006.257.03:29:08.13#ibcon#read 4, iclass 4, count 2 2006.257.03:29:08.13#ibcon#about to read 5, iclass 4, count 2 2006.257.03:29:08.13#ibcon#read 5, iclass 4, count 2 2006.257.03:29:08.13#ibcon#about to read 6, iclass 4, count 2 2006.257.03:29:08.13#ibcon#read 6, iclass 4, count 2 2006.257.03:29:08.13#ibcon#end of sib2, iclass 4, count 2 2006.257.03:29:08.13#ibcon#*after write, iclass 4, count 2 2006.257.03:29:08.13#ibcon#*before return 0, iclass 4, count 2 2006.257.03:29:08.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:29:08.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:29:08.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.03:29:08.13#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:08.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:29:08.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:29:08.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:29:08.25#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:29:08.25#ibcon#first serial, iclass 4, count 0 2006.257.03:29:08.25#ibcon#enter sib2, iclass 4, count 0 2006.257.03:29:08.25#ibcon#flushed, iclass 4, count 0 2006.257.03:29:08.25#ibcon#about to write, iclass 4, count 0 2006.257.03:29:08.25#ibcon#wrote, iclass 4, count 0 2006.257.03:29:08.25#ibcon#about to read 3, iclass 4, count 0 2006.257.03:29:08.27#ibcon#read 3, iclass 4, count 0 2006.257.03:29:08.27#ibcon#about to read 4, iclass 4, count 0 2006.257.03:29:08.27#ibcon#read 4, iclass 4, count 0 2006.257.03:29:08.27#ibcon#about to read 5, iclass 4, count 0 2006.257.03:29:08.27#ibcon#read 5, iclass 4, count 0 2006.257.03:29:08.27#ibcon#about to read 6, iclass 4, count 0 2006.257.03:29:08.27#ibcon#read 6, iclass 4, count 0 2006.257.03:29:08.27#ibcon#end of sib2, iclass 4, count 0 2006.257.03:29:08.27#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:29:08.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:29:08.27#ibcon#[25=USB\r\n] 2006.257.03:29:08.27#ibcon#*before write, iclass 4, count 0 2006.257.03:29:08.27#ibcon#enter sib2, iclass 4, count 0 2006.257.03:29:08.27#ibcon#flushed, iclass 4, count 0 2006.257.03:29:08.27#ibcon#about to write, iclass 4, count 0 2006.257.03:29:08.27#ibcon#wrote, iclass 4, count 0 2006.257.03:29:08.27#ibcon#about to read 3, iclass 4, count 0 2006.257.03:29:08.30#ibcon#read 3, iclass 4, count 0 2006.257.03:29:08.30#ibcon#about to read 4, iclass 4, count 0 2006.257.03:29:08.30#ibcon#read 4, iclass 4, count 0 2006.257.03:29:08.30#ibcon#about to read 5, iclass 4, count 0 2006.257.03:29:08.30#ibcon#read 5, iclass 4, count 0 2006.257.03:29:08.30#ibcon#about to read 6, iclass 4, count 0 2006.257.03:29:08.30#ibcon#read 6, iclass 4, count 0 2006.257.03:29:08.30#ibcon#end of sib2, iclass 4, count 0 2006.257.03:29:08.30#ibcon#*after write, iclass 4, count 0 2006.257.03:29:08.30#ibcon#*before return 0, iclass 4, count 0 2006.257.03:29:08.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:29:08.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:29:08.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:29:08.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:29:08.30$vck44/vblo=1,629.99 2006.257.03:29:08.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.03:29:08.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.03:29:08.30#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:08.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:29:08.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:29:08.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:29:08.30#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:29:08.30#ibcon#first serial, iclass 6, count 0 2006.257.03:29:08.30#ibcon#enter sib2, iclass 6, count 0 2006.257.03:29:08.30#ibcon#flushed, iclass 6, count 0 2006.257.03:29:08.30#ibcon#about to write, iclass 6, count 0 2006.257.03:29:08.30#ibcon#wrote, iclass 6, count 0 2006.257.03:29:08.30#ibcon#about to read 3, iclass 6, count 0 2006.257.03:29:08.32#ibcon#read 3, iclass 6, count 0 2006.257.03:29:08.32#ibcon#about to read 4, iclass 6, count 0 2006.257.03:29:08.32#ibcon#read 4, iclass 6, count 0 2006.257.03:29:08.32#ibcon#about to read 5, iclass 6, count 0 2006.257.03:29:08.32#ibcon#read 5, iclass 6, count 0 2006.257.03:29:08.32#ibcon#about to read 6, iclass 6, count 0 2006.257.03:29:08.32#ibcon#read 6, iclass 6, count 0 2006.257.03:29:08.32#ibcon#end of sib2, iclass 6, count 0 2006.257.03:29:08.32#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:29:08.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:29:08.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:29:08.32#ibcon#*before write, iclass 6, count 0 2006.257.03:29:08.32#ibcon#enter sib2, iclass 6, count 0 2006.257.03:29:08.32#ibcon#flushed, iclass 6, count 0 2006.257.03:29:08.32#ibcon#about to write, iclass 6, count 0 2006.257.03:29:08.32#ibcon#wrote, iclass 6, count 0 2006.257.03:29:08.32#ibcon#about to read 3, iclass 6, count 0 2006.257.03:29:08.36#ibcon#read 3, iclass 6, count 0 2006.257.03:29:08.36#ibcon#about to read 4, iclass 6, count 0 2006.257.03:29:08.36#ibcon#read 4, iclass 6, count 0 2006.257.03:29:08.36#ibcon#about to read 5, iclass 6, count 0 2006.257.03:29:08.36#ibcon#read 5, iclass 6, count 0 2006.257.03:29:08.36#ibcon#about to read 6, iclass 6, count 0 2006.257.03:29:08.36#ibcon#read 6, iclass 6, count 0 2006.257.03:29:08.36#ibcon#end of sib2, iclass 6, count 0 2006.257.03:29:08.36#ibcon#*after write, iclass 6, count 0 2006.257.03:29:08.36#ibcon#*before return 0, iclass 6, count 0 2006.257.03:29:08.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:29:08.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:29:08.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:29:08.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:29:08.36$vck44/vb=1,4 2006.257.03:29:08.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.03:29:08.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.03:29:08.36#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:08.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:29:08.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:29:08.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:29:08.36#ibcon#enter wrdev, iclass 10, count 2 2006.257.03:29:08.36#ibcon#first serial, iclass 10, count 2 2006.257.03:29:08.36#ibcon#enter sib2, iclass 10, count 2 2006.257.03:29:08.36#ibcon#flushed, iclass 10, count 2 2006.257.03:29:08.36#ibcon#about to write, iclass 10, count 2 2006.257.03:29:08.36#ibcon#wrote, iclass 10, count 2 2006.257.03:29:08.36#ibcon#about to read 3, iclass 10, count 2 2006.257.03:29:08.38#ibcon#read 3, iclass 10, count 2 2006.257.03:29:08.38#ibcon#about to read 4, iclass 10, count 2 2006.257.03:29:08.38#ibcon#read 4, iclass 10, count 2 2006.257.03:29:08.38#ibcon#about to read 5, iclass 10, count 2 2006.257.03:29:08.38#ibcon#read 5, iclass 10, count 2 2006.257.03:29:08.38#ibcon#about to read 6, iclass 10, count 2 2006.257.03:29:08.38#ibcon#read 6, iclass 10, count 2 2006.257.03:29:08.38#ibcon#end of sib2, iclass 10, count 2 2006.257.03:29:08.38#ibcon#*mode == 0, iclass 10, count 2 2006.257.03:29:08.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.03:29:08.38#ibcon#[27=AT01-04\r\n] 2006.257.03:29:08.38#ibcon#*before write, iclass 10, count 2 2006.257.03:29:08.38#ibcon#enter sib2, iclass 10, count 2 2006.257.03:29:08.38#ibcon#flushed, iclass 10, count 2 2006.257.03:29:08.38#ibcon#about to write, iclass 10, count 2 2006.257.03:29:08.38#ibcon#wrote, iclass 10, count 2 2006.257.03:29:08.38#ibcon#about to read 3, iclass 10, count 2 2006.257.03:29:08.41#ibcon#read 3, iclass 10, count 2 2006.257.03:29:08.41#ibcon#about to read 4, iclass 10, count 2 2006.257.03:29:08.41#ibcon#read 4, iclass 10, count 2 2006.257.03:29:08.41#ibcon#about to read 5, iclass 10, count 2 2006.257.03:29:08.41#ibcon#read 5, iclass 10, count 2 2006.257.03:29:08.41#ibcon#about to read 6, iclass 10, count 2 2006.257.03:29:08.41#ibcon#read 6, iclass 10, count 2 2006.257.03:29:08.41#ibcon#end of sib2, iclass 10, count 2 2006.257.03:29:08.41#ibcon#*after write, iclass 10, count 2 2006.257.03:29:08.41#ibcon#*before return 0, iclass 10, count 2 2006.257.03:29:08.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:29:08.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:29:08.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.03:29:08.41#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:08.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:29:08.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:29:08.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:29:08.53#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:29:08.53#ibcon#first serial, iclass 10, count 0 2006.257.03:29:08.53#ibcon#enter sib2, iclass 10, count 0 2006.257.03:29:08.53#ibcon#flushed, iclass 10, count 0 2006.257.03:29:08.53#ibcon#about to write, iclass 10, count 0 2006.257.03:29:08.53#ibcon#wrote, iclass 10, count 0 2006.257.03:29:08.53#ibcon#about to read 3, iclass 10, count 0 2006.257.03:29:08.55#ibcon#read 3, iclass 10, count 0 2006.257.03:29:08.55#ibcon#about to read 4, iclass 10, count 0 2006.257.03:29:08.55#ibcon#read 4, iclass 10, count 0 2006.257.03:29:08.55#ibcon#about to read 5, iclass 10, count 0 2006.257.03:29:08.55#ibcon#read 5, iclass 10, count 0 2006.257.03:29:08.55#ibcon#about to read 6, iclass 10, count 0 2006.257.03:29:08.55#ibcon#read 6, iclass 10, count 0 2006.257.03:29:08.55#ibcon#end of sib2, iclass 10, count 0 2006.257.03:29:08.55#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:29:08.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:29:08.55#ibcon#[27=USB\r\n] 2006.257.03:29:08.55#ibcon#*before write, iclass 10, count 0 2006.257.03:29:08.55#ibcon#enter sib2, iclass 10, count 0 2006.257.03:29:08.55#ibcon#flushed, iclass 10, count 0 2006.257.03:29:08.55#ibcon#about to write, iclass 10, count 0 2006.257.03:29:08.55#ibcon#wrote, iclass 10, count 0 2006.257.03:29:08.55#ibcon#about to read 3, iclass 10, count 0 2006.257.03:29:08.58#ibcon#read 3, iclass 10, count 0 2006.257.03:29:08.58#ibcon#about to read 4, iclass 10, count 0 2006.257.03:29:08.58#ibcon#read 4, iclass 10, count 0 2006.257.03:29:08.58#ibcon#about to read 5, iclass 10, count 0 2006.257.03:29:08.58#ibcon#read 5, iclass 10, count 0 2006.257.03:29:08.58#ibcon#about to read 6, iclass 10, count 0 2006.257.03:29:08.58#ibcon#read 6, iclass 10, count 0 2006.257.03:29:08.58#ibcon#end of sib2, iclass 10, count 0 2006.257.03:29:08.58#ibcon#*after write, iclass 10, count 0 2006.257.03:29:08.58#ibcon#*before return 0, iclass 10, count 0 2006.257.03:29:08.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:29:08.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:29:08.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:29:08.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:29:08.58$vck44/vblo=2,634.99 2006.257.03:29:08.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.03:29:08.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.03:29:08.58#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:08.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:08.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:08.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:08.58#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:29:08.58#ibcon#first serial, iclass 12, count 0 2006.257.03:29:08.58#ibcon#enter sib2, iclass 12, count 0 2006.257.03:29:08.58#ibcon#flushed, iclass 12, count 0 2006.257.03:29:08.58#ibcon#about to write, iclass 12, count 0 2006.257.03:29:08.58#ibcon#wrote, iclass 12, count 0 2006.257.03:29:08.58#ibcon#about to read 3, iclass 12, count 0 2006.257.03:29:08.60#ibcon#read 3, iclass 12, count 0 2006.257.03:29:08.60#ibcon#about to read 4, iclass 12, count 0 2006.257.03:29:08.60#ibcon#read 4, iclass 12, count 0 2006.257.03:29:08.60#ibcon#about to read 5, iclass 12, count 0 2006.257.03:29:08.60#ibcon#read 5, iclass 12, count 0 2006.257.03:29:08.60#ibcon#about to read 6, iclass 12, count 0 2006.257.03:29:08.60#ibcon#read 6, iclass 12, count 0 2006.257.03:29:08.60#ibcon#end of sib2, iclass 12, count 0 2006.257.03:29:08.60#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:29:08.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:29:08.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:29:08.60#ibcon#*before write, iclass 12, count 0 2006.257.03:29:08.60#ibcon#enter sib2, iclass 12, count 0 2006.257.03:29:08.60#ibcon#flushed, iclass 12, count 0 2006.257.03:29:08.60#ibcon#about to write, iclass 12, count 0 2006.257.03:29:08.60#ibcon#wrote, iclass 12, count 0 2006.257.03:29:08.60#ibcon#about to read 3, iclass 12, count 0 2006.257.03:29:08.64#ibcon#read 3, iclass 12, count 0 2006.257.03:29:08.64#ibcon#about to read 4, iclass 12, count 0 2006.257.03:29:08.64#ibcon#read 4, iclass 12, count 0 2006.257.03:29:08.64#ibcon#about to read 5, iclass 12, count 0 2006.257.03:29:08.64#ibcon#read 5, iclass 12, count 0 2006.257.03:29:08.64#ibcon#about to read 6, iclass 12, count 0 2006.257.03:29:08.64#ibcon#read 6, iclass 12, count 0 2006.257.03:29:08.64#ibcon#end of sib2, iclass 12, count 0 2006.257.03:29:08.64#ibcon#*after write, iclass 12, count 0 2006.257.03:29:08.64#ibcon#*before return 0, iclass 12, count 0 2006.257.03:29:08.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:08.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:29:08.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:29:08.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:29:08.64$vck44/vb=2,5 2006.257.03:29:08.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.03:29:08.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.03:29:08.64#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:08.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:08.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:08.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:08.70#ibcon#enter wrdev, iclass 14, count 2 2006.257.03:29:08.70#ibcon#first serial, iclass 14, count 2 2006.257.03:29:08.70#ibcon#enter sib2, iclass 14, count 2 2006.257.03:29:08.70#ibcon#flushed, iclass 14, count 2 2006.257.03:29:08.70#ibcon#about to write, iclass 14, count 2 2006.257.03:29:08.70#ibcon#wrote, iclass 14, count 2 2006.257.03:29:08.70#ibcon#about to read 3, iclass 14, count 2 2006.257.03:29:08.72#ibcon#read 3, iclass 14, count 2 2006.257.03:29:08.72#ibcon#about to read 4, iclass 14, count 2 2006.257.03:29:08.72#ibcon#read 4, iclass 14, count 2 2006.257.03:29:08.72#ibcon#about to read 5, iclass 14, count 2 2006.257.03:29:08.72#ibcon#read 5, iclass 14, count 2 2006.257.03:29:08.72#ibcon#about to read 6, iclass 14, count 2 2006.257.03:29:08.72#ibcon#read 6, iclass 14, count 2 2006.257.03:29:08.72#ibcon#end of sib2, iclass 14, count 2 2006.257.03:29:08.72#ibcon#*mode == 0, iclass 14, count 2 2006.257.03:29:08.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.03:29:08.72#ibcon#[27=AT02-05\r\n] 2006.257.03:29:08.72#ibcon#*before write, iclass 14, count 2 2006.257.03:29:08.72#ibcon#enter sib2, iclass 14, count 2 2006.257.03:29:08.72#ibcon#flushed, iclass 14, count 2 2006.257.03:29:08.72#ibcon#about to write, iclass 14, count 2 2006.257.03:29:08.72#ibcon#wrote, iclass 14, count 2 2006.257.03:29:08.72#ibcon#about to read 3, iclass 14, count 2 2006.257.03:29:08.75#ibcon#read 3, iclass 14, count 2 2006.257.03:29:08.75#ibcon#about to read 4, iclass 14, count 2 2006.257.03:29:08.75#ibcon#read 4, iclass 14, count 2 2006.257.03:29:08.75#ibcon#about to read 5, iclass 14, count 2 2006.257.03:29:08.75#ibcon#read 5, iclass 14, count 2 2006.257.03:29:08.75#ibcon#about to read 6, iclass 14, count 2 2006.257.03:29:08.75#ibcon#read 6, iclass 14, count 2 2006.257.03:29:08.75#ibcon#end of sib2, iclass 14, count 2 2006.257.03:29:08.75#ibcon#*after write, iclass 14, count 2 2006.257.03:29:08.75#ibcon#*before return 0, iclass 14, count 2 2006.257.03:29:08.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:08.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:29:08.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.03:29:08.75#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:08.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:08.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:08.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:08.87#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:29:08.87#ibcon#first serial, iclass 14, count 0 2006.257.03:29:08.87#ibcon#enter sib2, iclass 14, count 0 2006.257.03:29:08.87#ibcon#flushed, iclass 14, count 0 2006.257.03:29:08.87#ibcon#about to write, iclass 14, count 0 2006.257.03:29:08.87#ibcon#wrote, iclass 14, count 0 2006.257.03:29:08.87#ibcon#about to read 3, iclass 14, count 0 2006.257.03:29:08.89#ibcon#read 3, iclass 14, count 0 2006.257.03:29:08.89#ibcon#about to read 4, iclass 14, count 0 2006.257.03:29:08.89#ibcon#read 4, iclass 14, count 0 2006.257.03:29:08.89#ibcon#about to read 5, iclass 14, count 0 2006.257.03:29:08.89#ibcon#read 5, iclass 14, count 0 2006.257.03:29:08.89#ibcon#about to read 6, iclass 14, count 0 2006.257.03:29:08.89#ibcon#read 6, iclass 14, count 0 2006.257.03:29:08.89#ibcon#end of sib2, iclass 14, count 0 2006.257.03:29:08.89#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:29:08.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:29:08.89#ibcon#[27=USB\r\n] 2006.257.03:29:08.89#ibcon#*before write, iclass 14, count 0 2006.257.03:29:08.89#ibcon#enter sib2, iclass 14, count 0 2006.257.03:29:08.89#ibcon#flushed, iclass 14, count 0 2006.257.03:29:08.89#ibcon#about to write, iclass 14, count 0 2006.257.03:29:08.89#ibcon#wrote, iclass 14, count 0 2006.257.03:29:08.89#ibcon#about to read 3, iclass 14, count 0 2006.257.03:29:08.92#ibcon#read 3, iclass 14, count 0 2006.257.03:29:08.92#ibcon#about to read 4, iclass 14, count 0 2006.257.03:29:08.92#ibcon#read 4, iclass 14, count 0 2006.257.03:29:08.92#ibcon#about to read 5, iclass 14, count 0 2006.257.03:29:08.92#ibcon#read 5, iclass 14, count 0 2006.257.03:29:08.92#ibcon#about to read 6, iclass 14, count 0 2006.257.03:29:08.92#ibcon#read 6, iclass 14, count 0 2006.257.03:29:08.92#ibcon#end of sib2, iclass 14, count 0 2006.257.03:29:08.92#ibcon#*after write, iclass 14, count 0 2006.257.03:29:08.92#ibcon#*before return 0, iclass 14, count 0 2006.257.03:29:08.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:08.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:29:08.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:29:08.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:29:08.92$vck44/vblo=3,649.99 2006.257.03:29:08.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.03:29:08.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.03:29:08.92#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:08.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:08.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:08.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:08.92#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:29:08.92#ibcon#first serial, iclass 16, count 0 2006.257.03:29:08.92#ibcon#enter sib2, iclass 16, count 0 2006.257.03:29:08.92#ibcon#flushed, iclass 16, count 0 2006.257.03:29:08.92#ibcon#about to write, iclass 16, count 0 2006.257.03:29:08.92#ibcon#wrote, iclass 16, count 0 2006.257.03:29:08.92#ibcon#about to read 3, iclass 16, count 0 2006.257.03:29:08.94#ibcon#read 3, iclass 16, count 0 2006.257.03:29:08.94#ibcon#about to read 4, iclass 16, count 0 2006.257.03:29:08.94#ibcon#read 4, iclass 16, count 0 2006.257.03:29:08.94#ibcon#about to read 5, iclass 16, count 0 2006.257.03:29:08.94#ibcon#read 5, iclass 16, count 0 2006.257.03:29:08.94#ibcon#about to read 6, iclass 16, count 0 2006.257.03:29:08.94#ibcon#read 6, iclass 16, count 0 2006.257.03:29:08.94#ibcon#end of sib2, iclass 16, count 0 2006.257.03:29:08.94#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:29:08.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:29:08.94#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:29:08.94#ibcon#*before write, iclass 16, count 0 2006.257.03:29:08.94#ibcon#enter sib2, iclass 16, count 0 2006.257.03:29:08.94#ibcon#flushed, iclass 16, count 0 2006.257.03:29:08.94#ibcon#about to write, iclass 16, count 0 2006.257.03:29:08.94#ibcon#wrote, iclass 16, count 0 2006.257.03:29:08.94#ibcon#about to read 3, iclass 16, count 0 2006.257.03:29:08.98#ibcon#read 3, iclass 16, count 0 2006.257.03:29:08.98#ibcon#about to read 4, iclass 16, count 0 2006.257.03:29:08.98#ibcon#read 4, iclass 16, count 0 2006.257.03:29:08.98#ibcon#about to read 5, iclass 16, count 0 2006.257.03:29:08.98#ibcon#read 5, iclass 16, count 0 2006.257.03:29:08.98#ibcon#about to read 6, iclass 16, count 0 2006.257.03:29:08.98#ibcon#read 6, iclass 16, count 0 2006.257.03:29:08.98#ibcon#end of sib2, iclass 16, count 0 2006.257.03:29:08.98#ibcon#*after write, iclass 16, count 0 2006.257.03:29:08.98#ibcon#*before return 0, iclass 16, count 0 2006.257.03:29:08.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:08.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:29:08.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:29:08.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:29:08.98$vck44/vb=3,4 2006.257.03:29:08.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.03:29:08.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.03:29:08.98#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:08.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:09.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:09.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:09.04#ibcon#enter wrdev, iclass 18, count 2 2006.257.03:29:09.04#ibcon#first serial, iclass 18, count 2 2006.257.03:29:09.04#ibcon#enter sib2, iclass 18, count 2 2006.257.03:29:09.04#ibcon#flushed, iclass 18, count 2 2006.257.03:29:09.04#ibcon#about to write, iclass 18, count 2 2006.257.03:29:09.04#ibcon#wrote, iclass 18, count 2 2006.257.03:29:09.04#ibcon#about to read 3, iclass 18, count 2 2006.257.03:29:09.06#ibcon#read 3, iclass 18, count 2 2006.257.03:29:09.06#ibcon#about to read 4, iclass 18, count 2 2006.257.03:29:09.06#ibcon#read 4, iclass 18, count 2 2006.257.03:29:09.06#ibcon#about to read 5, iclass 18, count 2 2006.257.03:29:09.06#ibcon#read 5, iclass 18, count 2 2006.257.03:29:09.06#ibcon#about to read 6, iclass 18, count 2 2006.257.03:29:09.06#ibcon#read 6, iclass 18, count 2 2006.257.03:29:09.06#ibcon#end of sib2, iclass 18, count 2 2006.257.03:29:09.06#ibcon#*mode == 0, iclass 18, count 2 2006.257.03:29:09.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.03:29:09.06#ibcon#[27=AT03-04\r\n] 2006.257.03:29:09.06#ibcon#*before write, iclass 18, count 2 2006.257.03:29:09.06#ibcon#enter sib2, iclass 18, count 2 2006.257.03:29:09.06#ibcon#flushed, iclass 18, count 2 2006.257.03:29:09.06#ibcon#about to write, iclass 18, count 2 2006.257.03:29:09.06#ibcon#wrote, iclass 18, count 2 2006.257.03:29:09.06#ibcon#about to read 3, iclass 18, count 2 2006.257.03:29:09.09#ibcon#read 3, iclass 18, count 2 2006.257.03:29:09.09#ibcon#about to read 4, iclass 18, count 2 2006.257.03:29:09.09#ibcon#read 4, iclass 18, count 2 2006.257.03:29:09.09#ibcon#about to read 5, iclass 18, count 2 2006.257.03:29:09.09#ibcon#read 5, iclass 18, count 2 2006.257.03:29:09.09#ibcon#about to read 6, iclass 18, count 2 2006.257.03:29:09.09#ibcon#read 6, iclass 18, count 2 2006.257.03:29:09.09#ibcon#end of sib2, iclass 18, count 2 2006.257.03:29:09.09#ibcon#*after write, iclass 18, count 2 2006.257.03:29:09.09#ibcon#*before return 0, iclass 18, count 2 2006.257.03:29:09.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:09.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:29:09.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.03:29:09.09#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:09.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:09.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:09.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:09.21#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:29:09.21#ibcon#first serial, iclass 18, count 0 2006.257.03:29:09.21#ibcon#enter sib2, iclass 18, count 0 2006.257.03:29:09.21#ibcon#flushed, iclass 18, count 0 2006.257.03:29:09.21#ibcon#about to write, iclass 18, count 0 2006.257.03:29:09.21#ibcon#wrote, iclass 18, count 0 2006.257.03:29:09.21#ibcon#about to read 3, iclass 18, count 0 2006.257.03:29:09.23#ibcon#read 3, iclass 18, count 0 2006.257.03:29:09.23#ibcon#about to read 4, iclass 18, count 0 2006.257.03:29:09.23#ibcon#read 4, iclass 18, count 0 2006.257.03:29:09.23#ibcon#about to read 5, iclass 18, count 0 2006.257.03:29:09.23#ibcon#read 5, iclass 18, count 0 2006.257.03:29:09.23#ibcon#about to read 6, iclass 18, count 0 2006.257.03:29:09.23#ibcon#read 6, iclass 18, count 0 2006.257.03:29:09.23#ibcon#end of sib2, iclass 18, count 0 2006.257.03:29:09.23#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:29:09.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:29:09.23#ibcon#[27=USB\r\n] 2006.257.03:29:09.23#ibcon#*before write, iclass 18, count 0 2006.257.03:29:09.23#ibcon#enter sib2, iclass 18, count 0 2006.257.03:29:09.23#ibcon#flushed, iclass 18, count 0 2006.257.03:29:09.23#ibcon#about to write, iclass 18, count 0 2006.257.03:29:09.23#ibcon#wrote, iclass 18, count 0 2006.257.03:29:09.23#ibcon#about to read 3, iclass 18, count 0 2006.257.03:29:09.26#ibcon#read 3, iclass 18, count 0 2006.257.03:29:09.26#ibcon#about to read 4, iclass 18, count 0 2006.257.03:29:09.26#ibcon#read 4, iclass 18, count 0 2006.257.03:29:09.26#ibcon#about to read 5, iclass 18, count 0 2006.257.03:29:09.26#ibcon#read 5, iclass 18, count 0 2006.257.03:29:09.26#ibcon#about to read 6, iclass 18, count 0 2006.257.03:29:09.26#ibcon#read 6, iclass 18, count 0 2006.257.03:29:09.26#ibcon#end of sib2, iclass 18, count 0 2006.257.03:29:09.26#ibcon#*after write, iclass 18, count 0 2006.257.03:29:09.26#ibcon#*before return 0, iclass 18, count 0 2006.257.03:29:09.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:09.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:29:09.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:29:09.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:29:09.26$vck44/vblo=4,679.99 2006.257.03:29:09.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.03:29:09.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.03:29:09.26#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:09.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:09.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:09.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:09.26#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:29:09.26#ibcon#first serial, iclass 20, count 0 2006.257.03:29:09.26#ibcon#enter sib2, iclass 20, count 0 2006.257.03:29:09.26#ibcon#flushed, iclass 20, count 0 2006.257.03:29:09.26#ibcon#about to write, iclass 20, count 0 2006.257.03:29:09.26#ibcon#wrote, iclass 20, count 0 2006.257.03:29:09.26#ibcon#about to read 3, iclass 20, count 0 2006.257.03:29:09.28#ibcon#read 3, iclass 20, count 0 2006.257.03:29:09.28#ibcon#about to read 4, iclass 20, count 0 2006.257.03:29:09.28#ibcon#read 4, iclass 20, count 0 2006.257.03:29:09.28#ibcon#about to read 5, iclass 20, count 0 2006.257.03:29:09.28#ibcon#read 5, iclass 20, count 0 2006.257.03:29:09.28#ibcon#about to read 6, iclass 20, count 0 2006.257.03:29:09.28#ibcon#read 6, iclass 20, count 0 2006.257.03:29:09.28#ibcon#end of sib2, iclass 20, count 0 2006.257.03:29:09.28#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:29:09.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:29:09.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:29:09.28#ibcon#*before write, iclass 20, count 0 2006.257.03:29:09.28#ibcon#enter sib2, iclass 20, count 0 2006.257.03:29:09.28#ibcon#flushed, iclass 20, count 0 2006.257.03:29:09.28#ibcon#about to write, iclass 20, count 0 2006.257.03:29:09.28#ibcon#wrote, iclass 20, count 0 2006.257.03:29:09.28#ibcon#about to read 3, iclass 20, count 0 2006.257.03:29:09.32#ibcon#read 3, iclass 20, count 0 2006.257.03:29:09.32#ibcon#about to read 4, iclass 20, count 0 2006.257.03:29:09.32#ibcon#read 4, iclass 20, count 0 2006.257.03:29:09.32#ibcon#about to read 5, iclass 20, count 0 2006.257.03:29:09.32#ibcon#read 5, iclass 20, count 0 2006.257.03:29:09.32#ibcon#about to read 6, iclass 20, count 0 2006.257.03:29:09.32#ibcon#read 6, iclass 20, count 0 2006.257.03:29:09.32#ibcon#end of sib2, iclass 20, count 0 2006.257.03:29:09.32#ibcon#*after write, iclass 20, count 0 2006.257.03:29:09.32#ibcon#*before return 0, iclass 20, count 0 2006.257.03:29:09.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:09.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:29:09.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:29:09.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:29:09.32$vck44/vb=4,5 2006.257.03:29:09.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.03:29:09.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.03:29:09.32#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:09.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:09.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:09.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:09.38#ibcon#enter wrdev, iclass 22, count 2 2006.257.03:29:09.38#ibcon#first serial, iclass 22, count 2 2006.257.03:29:09.38#ibcon#enter sib2, iclass 22, count 2 2006.257.03:29:09.38#ibcon#flushed, iclass 22, count 2 2006.257.03:29:09.38#ibcon#about to write, iclass 22, count 2 2006.257.03:29:09.38#ibcon#wrote, iclass 22, count 2 2006.257.03:29:09.38#ibcon#about to read 3, iclass 22, count 2 2006.257.03:29:09.40#ibcon#read 3, iclass 22, count 2 2006.257.03:29:09.40#ibcon#about to read 4, iclass 22, count 2 2006.257.03:29:09.40#ibcon#read 4, iclass 22, count 2 2006.257.03:29:09.40#ibcon#about to read 5, iclass 22, count 2 2006.257.03:29:09.40#ibcon#read 5, iclass 22, count 2 2006.257.03:29:09.40#ibcon#about to read 6, iclass 22, count 2 2006.257.03:29:09.40#ibcon#read 6, iclass 22, count 2 2006.257.03:29:09.40#ibcon#end of sib2, iclass 22, count 2 2006.257.03:29:09.40#ibcon#*mode == 0, iclass 22, count 2 2006.257.03:29:09.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.03:29:09.40#ibcon#[27=AT04-05\r\n] 2006.257.03:29:09.40#ibcon#*before write, iclass 22, count 2 2006.257.03:29:09.40#ibcon#enter sib2, iclass 22, count 2 2006.257.03:29:09.40#ibcon#flushed, iclass 22, count 2 2006.257.03:29:09.40#ibcon#about to write, iclass 22, count 2 2006.257.03:29:09.40#ibcon#wrote, iclass 22, count 2 2006.257.03:29:09.40#ibcon#about to read 3, iclass 22, count 2 2006.257.03:29:09.43#ibcon#read 3, iclass 22, count 2 2006.257.03:29:09.43#ibcon#about to read 4, iclass 22, count 2 2006.257.03:29:09.43#ibcon#read 4, iclass 22, count 2 2006.257.03:29:09.43#ibcon#about to read 5, iclass 22, count 2 2006.257.03:29:09.43#ibcon#read 5, iclass 22, count 2 2006.257.03:29:09.43#ibcon#about to read 6, iclass 22, count 2 2006.257.03:29:09.43#ibcon#read 6, iclass 22, count 2 2006.257.03:29:09.43#ibcon#end of sib2, iclass 22, count 2 2006.257.03:29:09.43#ibcon#*after write, iclass 22, count 2 2006.257.03:29:09.43#ibcon#*before return 0, iclass 22, count 2 2006.257.03:29:09.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:09.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:29:09.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.03:29:09.43#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:09.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:09.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:09.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:09.55#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:29:09.55#ibcon#first serial, iclass 22, count 0 2006.257.03:29:09.55#ibcon#enter sib2, iclass 22, count 0 2006.257.03:29:09.55#ibcon#flushed, iclass 22, count 0 2006.257.03:29:09.55#ibcon#about to write, iclass 22, count 0 2006.257.03:29:09.55#ibcon#wrote, iclass 22, count 0 2006.257.03:29:09.55#ibcon#about to read 3, iclass 22, count 0 2006.257.03:29:09.57#ibcon#read 3, iclass 22, count 0 2006.257.03:29:09.57#ibcon#about to read 4, iclass 22, count 0 2006.257.03:29:09.57#ibcon#read 4, iclass 22, count 0 2006.257.03:29:09.57#ibcon#about to read 5, iclass 22, count 0 2006.257.03:29:09.57#ibcon#read 5, iclass 22, count 0 2006.257.03:29:09.57#ibcon#about to read 6, iclass 22, count 0 2006.257.03:29:09.57#ibcon#read 6, iclass 22, count 0 2006.257.03:29:09.57#ibcon#end of sib2, iclass 22, count 0 2006.257.03:29:09.57#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:29:09.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:29:09.57#ibcon#[27=USB\r\n] 2006.257.03:29:09.57#ibcon#*before write, iclass 22, count 0 2006.257.03:29:09.57#ibcon#enter sib2, iclass 22, count 0 2006.257.03:29:09.57#ibcon#flushed, iclass 22, count 0 2006.257.03:29:09.57#ibcon#about to write, iclass 22, count 0 2006.257.03:29:09.57#ibcon#wrote, iclass 22, count 0 2006.257.03:29:09.57#ibcon#about to read 3, iclass 22, count 0 2006.257.03:29:09.60#ibcon#read 3, iclass 22, count 0 2006.257.03:29:09.60#ibcon#about to read 4, iclass 22, count 0 2006.257.03:29:09.60#ibcon#read 4, iclass 22, count 0 2006.257.03:29:09.60#ibcon#about to read 5, iclass 22, count 0 2006.257.03:29:09.60#ibcon#read 5, iclass 22, count 0 2006.257.03:29:09.60#ibcon#about to read 6, iclass 22, count 0 2006.257.03:29:09.60#ibcon#read 6, iclass 22, count 0 2006.257.03:29:09.60#ibcon#end of sib2, iclass 22, count 0 2006.257.03:29:09.60#ibcon#*after write, iclass 22, count 0 2006.257.03:29:09.60#ibcon#*before return 0, iclass 22, count 0 2006.257.03:29:09.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:09.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:29:09.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:29:09.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:29:09.60$vck44/vblo=5,709.99 2006.257.03:29:09.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.03:29:09.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.03:29:09.60#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:09.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:09.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:09.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:09.60#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:29:09.60#ibcon#first serial, iclass 24, count 0 2006.257.03:29:09.60#ibcon#enter sib2, iclass 24, count 0 2006.257.03:29:09.60#ibcon#flushed, iclass 24, count 0 2006.257.03:29:09.60#ibcon#about to write, iclass 24, count 0 2006.257.03:29:09.60#ibcon#wrote, iclass 24, count 0 2006.257.03:29:09.60#ibcon#about to read 3, iclass 24, count 0 2006.257.03:29:09.62#ibcon#read 3, iclass 24, count 0 2006.257.03:29:09.62#ibcon#about to read 4, iclass 24, count 0 2006.257.03:29:09.62#ibcon#read 4, iclass 24, count 0 2006.257.03:29:09.62#ibcon#about to read 5, iclass 24, count 0 2006.257.03:29:09.62#ibcon#read 5, iclass 24, count 0 2006.257.03:29:09.62#ibcon#about to read 6, iclass 24, count 0 2006.257.03:29:09.62#ibcon#read 6, iclass 24, count 0 2006.257.03:29:09.62#ibcon#end of sib2, iclass 24, count 0 2006.257.03:29:09.62#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:29:09.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:29:09.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:29:09.62#ibcon#*before write, iclass 24, count 0 2006.257.03:29:09.62#ibcon#enter sib2, iclass 24, count 0 2006.257.03:29:09.62#ibcon#flushed, iclass 24, count 0 2006.257.03:29:09.62#ibcon#about to write, iclass 24, count 0 2006.257.03:29:09.62#ibcon#wrote, iclass 24, count 0 2006.257.03:29:09.62#ibcon#about to read 3, iclass 24, count 0 2006.257.03:29:09.66#ibcon#read 3, iclass 24, count 0 2006.257.03:29:09.66#ibcon#about to read 4, iclass 24, count 0 2006.257.03:29:09.66#ibcon#read 4, iclass 24, count 0 2006.257.03:29:09.66#ibcon#about to read 5, iclass 24, count 0 2006.257.03:29:09.66#ibcon#read 5, iclass 24, count 0 2006.257.03:29:09.66#ibcon#about to read 6, iclass 24, count 0 2006.257.03:29:09.66#ibcon#read 6, iclass 24, count 0 2006.257.03:29:09.66#ibcon#end of sib2, iclass 24, count 0 2006.257.03:29:09.66#ibcon#*after write, iclass 24, count 0 2006.257.03:29:09.66#ibcon#*before return 0, iclass 24, count 0 2006.257.03:29:09.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:09.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:29:09.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:29:09.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:29:09.66$vck44/vb=5,4 2006.257.03:29:09.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.03:29:09.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.03:29:09.66#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:09.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:09.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:09.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:09.72#ibcon#enter wrdev, iclass 26, count 2 2006.257.03:29:09.72#ibcon#first serial, iclass 26, count 2 2006.257.03:29:09.72#ibcon#enter sib2, iclass 26, count 2 2006.257.03:29:09.72#ibcon#flushed, iclass 26, count 2 2006.257.03:29:09.72#ibcon#about to write, iclass 26, count 2 2006.257.03:29:09.72#ibcon#wrote, iclass 26, count 2 2006.257.03:29:09.72#ibcon#about to read 3, iclass 26, count 2 2006.257.03:29:09.74#ibcon#read 3, iclass 26, count 2 2006.257.03:29:09.74#ibcon#about to read 4, iclass 26, count 2 2006.257.03:29:09.74#ibcon#read 4, iclass 26, count 2 2006.257.03:29:09.74#ibcon#about to read 5, iclass 26, count 2 2006.257.03:29:09.74#ibcon#read 5, iclass 26, count 2 2006.257.03:29:09.74#ibcon#about to read 6, iclass 26, count 2 2006.257.03:29:09.74#ibcon#read 6, iclass 26, count 2 2006.257.03:29:09.74#ibcon#end of sib2, iclass 26, count 2 2006.257.03:29:09.74#ibcon#*mode == 0, iclass 26, count 2 2006.257.03:29:09.74#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.03:29:09.74#ibcon#[27=AT05-04\r\n] 2006.257.03:29:09.74#ibcon#*before write, iclass 26, count 2 2006.257.03:29:09.74#ibcon#enter sib2, iclass 26, count 2 2006.257.03:29:09.74#ibcon#flushed, iclass 26, count 2 2006.257.03:29:09.74#ibcon#about to write, iclass 26, count 2 2006.257.03:29:09.74#ibcon#wrote, iclass 26, count 2 2006.257.03:29:09.74#ibcon#about to read 3, iclass 26, count 2 2006.257.03:29:09.77#ibcon#read 3, iclass 26, count 2 2006.257.03:29:09.77#ibcon#about to read 4, iclass 26, count 2 2006.257.03:29:09.77#ibcon#read 4, iclass 26, count 2 2006.257.03:29:09.77#ibcon#about to read 5, iclass 26, count 2 2006.257.03:29:09.77#ibcon#read 5, iclass 26, count 2 2006.257.03:29:09.77#ibcon#about to read 6, iclass 26, count 2 2006.257.03:29:09.77#ibcon#read 6, iclass 26, count 2 2006.257.03:29:09.77#ibcon#end of sib2, iclass 26, count 2 2006.257.03:29:09.77#ibcon#*after write, iclass 26, count 2 2006.257.03:29:09.77#ibcon#*before return 0, iclass 26, count 2 2006.257.03:29:09.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:09.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:29:09.77#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.03:29:09.77#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:09.77#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:09.89#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:09.89#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:09.89#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:29:09.89#ibcon#first serial, iclass 26, count 0 2006.257.03:29:09.89#ibcon#enter sib2, iclass 26, count 0 2006.257.03:29:09.89#ibcon#flushed, iclass 26, count 0 2006.257.03:29:09.89#ibcon#about to write, iclass 26, count 0 2006.257.03:29:09.89#ibcon#wrote, iclass 26, count 0 2006.257.03:29:09.89#ibcon#about to read 3, iclass 26, count 0 2006.257.03:29:09.91#ibcon#read 3, iclass 26, count 0 2006.257.03:29:09.91#ibcon#about to read 4, iclass 26, count 0 2006.257.03:29:09.91#ibcon#read 4, iclass 26, count 0 2006.257.03:29:09.91#ibcon#about to read 5, iclass 26, count 0 2006.257.03:29:09.91#ibcon#read 5, iclass 26, count 0 2006.257.03:29:09.91#ibcon#about to read 6, iclass 26, count 0 2006.257.03:29:09.91#ibcon#read 6, iclass 26, count 0 2006.257.03:29:09.91#ibcon#end of sib2, iclass 26, count 0 2006.257.03:29:09.91#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:29:09.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:29:09.91#ibcon#[27=USB\r\n] 2006.257.03:29:09.91#ibcon#*before write, iclass 26, count 0 2006.257.03:29:09.91#ibcon#enter sib2, iclass 26, count 0 2006.257.03:29:09.91#ibcon#flushed, iclass 26, count 0 2006.257.03:29:09.91#ibcon#about to write, iclass 26, count 0 2006.257.03:29:09.91#ibcon#wrote, iclass 26, count 0 2006.257.03:29:09.91#ibcon#about to read 3, iclass 26, count 0 2006.257.03:29:09.94#ibcon#read 3, iclass 26, count 0 2006.257.03:29:09.94#ibcon#about to read 4, iclass 26, count 0 2006.257.03:29:09.94#ibcon#read 4, iclass 26, count 0 2006.257.03:29:09.94#ibcon#about to read 5, iclass 26, count 0 2006.257.03:29:09.94#ibcon#read 5, iclass 26, count 0 2006.257.03:29:09.94#ibcon#about to read 6, iclass 26, count 0 2006.257.03:29:09.94#ibcon#read 6, iclass 26, count 0 2006.257.03:29:09.94#ibcon#end of sib2, iclass 26, count 0 2006.257.03:29:09.94#ibcon#*after write, iclass 26, count 0 2006.257.03:29:09.94#ibcon#*before return 0, iclass 26, count 0 2006.257.03:29:09.94#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:09.94#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:29:09.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:29:09.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:29:09.94$vck44/vblo=6,719.99 2006.257.03:29:09.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.03:29:09.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.03:29:09.94#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:09.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:09.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:09.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:09.94#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:29:09.94#ibcon#first serial, iclass 28, count 0 2006.257.03:29:09.94#ibcon#enter sib2, iclass 28, count 0 2006.257.03:29:09.94#ibcon#flushed, iclass 28, count 0 2006.257.03:29:09.94#ibcon#about to write, iclass 28, count 0 2006.257.03:29:09.94#ibcon#wrote, iclass 28, count 0 2006.257.03:29:09.94#ibcon#about to read 3, iclass 28, count 0 2006.257.03:29:09.96#ibcon#read 3, iclass 28, count 0 2006.257.03:29:09.96#ibcon#about to read 4, iclass 28, count 0 2006.257.03:29:09.96#ibcon#read 4, iclass 28, count 0 2006.257.03:29:09.96#ibcon#about to read 5, iclass 28, count 0 2006.257.03:29:09.96#ibcon#read 5, iclass 28, count 0 2006.257.03:29:09.96#ibcon#about to read 6, iclass 28, count 0 2006.257.03:29:09.96#ibcon#read 6, iclass 28, count 0 2006.257.03:29:09.96#ibcon#end of sib2, iclass 28, count 0 2006.257.03:29:09.96#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:29:09.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:29:09.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:29:09.96#ibcon#*before write, iclass 28, count 0 2006.257.03:29:09.96#ibcon#enter sib2, iclass 28, count 0 2006.257.03:29:09.96#ibcon#flushed, iclass 28, count 0 2006.257.03:29:09.96#ibcon#about to write, iclass 28, count 0 2006.257.03:29:09.96#ibcon#wrote, iclass 28, count 0 2006.257.03:29:09.96#ibcon#about to read 3, iclass 28, count 0 2006.257.03:29:10.00#ibcon#read 3, iclass 28, count 0 2006.257.03:29:10.00#ibcon#about to read 4, iclass 28, count 0 2006.257.03:29:10.00#ibcon#read 4, iclass 28, count 0 2006.257.03:29:10.00#ibcon#about to read 5, iclass 28, count 0 2006.257.03:29:10.00#ibcon#read 5, iclass 28, count 0 2006.257.03:29:10.00#ibcon#about to read 6, iclass 28, count 0 2006.257.03:29:10.00#ibcon#read 6, iclass 28, count 0 2006.257.03:29:10.00#ibcon#end of sib2, iclass 28, count 0 2006.257.03:29:10.00#ibcon#*after write, iclass 28, count 0 2006.257.03:29:10.00#ibcon#*before return 0, iclass 28, count 0 2006.257.03:29:10.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:10.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:29:10.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:29:10.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:29:10.00$vck44/vb=6,4 2006.257.03:29:10.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.03:29:10.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.03:29:10.00#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:10.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:10.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:10.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:10.06#ibcon#enter wrdev, iclass 30, count 2 2006.257.03:29:10.06#ibcon#first serial, iclass 30, count 2 2006.257.03:29:10.06#ibcon#enter sib2, iclass 30, count 2 2006.257.03:29:10.06#ibcon#flushed, iclass 30, count 2 2006.257.03:29:10.06#ibcon#about to write, iclass 30, count 2 2006.257.03:29:10.06#ibcon#wrote, iclass 30, count 2 2006.257.03:29:10.06#ibcon#about to read 3, iclass 30, count 2 2006.257.03:29:10.08#ibcon#read 3, iclass 30, count 2 2006.257.03:29:10.08#ibcon#about to read 4, iclass 30, count 2 2006.257.03:29:10.08#ibcon#read 4, iclass 30, count 2 2006.257.03:29:10.08#ibcon#about to read 5, iclass 30, count 2 2006.257.03:29:10.08#ibcon#read 5, iclass 30, count 2 2006.257.03:29:10.08#ibcon#about to read 6, iclass 30, count 2 2006.257.03:29:10.08#ibcon#read 6, iclass 30, count 2 2006.257.03:29:10.08#ibcon#end of sib2, iclass 30, count 2 2006.257.03:29:10.08#ibcon#*mode == 0, iclass 30, count 2 2006.257.03:29:10.08#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.03:29:10.08#ibcon#[27=AT06-04\r\n] 2006.257.03:29:10.08#ibcon#*before write, iclass 30, count 2 2006.257.03:29:10.08#ibcon#enter sib2, iclass 30, count 2 2006.257.03:29:10.08#ibcon#flushed, iclass 30, count 2 2006.257.03:29:10.08#ibcon#about to write, iclass 30, count 2 2006.257.03:29:10.08#ibcon#wrote, iclass 30, count 2 2006.257.03:29:10.08#ibcon#about to read 3, iclass 30, count 2 2006.257.03:29:10.11#ibcon#read 3, iclass 30, count 2 2006.257.03:29:10.11#ibcon#about to read 4, iclass 30, count 2 2006.257.03:29:10.11#ibcon#read 4, iclass 30, count 2 2006.257.03:29:10.11#ibcon#about to read 5, iclass 30, count 2 2006.257.03:29:10.11#ibcon#read 5, iclass 30, count 2 2006.257.03:29:10.11#ibcon#about to read 6, iclass 30, count 2 2006.257.03:29:10.11#ibcon#read 6, iclass 30, count 2 2006.257.03:29:10.11#ibcon#end of sib2, iclass 30, count 2 2006.257.03:29:10.11#ibcon#*after write, iclass 30, count 2 2006.257.03:29:10.11#ibcon#*before return 0, iclass 30, count 2 2006.257.03:29:10.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:10.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:29:10.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.03:29:10.11#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:10.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:10.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:10.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:10.23#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:29:10.23#ibcon#first serial, iclass 30, count 0 2006.257.03:29:10.23#ibcon#enter sib2, iclass 30, count 0 2006.257.03:29:10.23#ibcon#flushed, iclass 30, count 0 2006.257.03:29:10.23#ibcon#about to write, iclass 30, count 0 2006.257.03:29:10.23#ibcon#wrote, iclass 30, count 0 2006.257.03:29:10.23#ibcon#about to read 3, iclass 30, count 0 2006.257.03:29:10.25#ibcon#read 3, iclass 30, count 0 2006.257.03:29:10.25#ibcon#about to read 4, iclass 30, count 0 2006.257.03:29:10.25#ibcon#read 4, iclass 30, count 0 2006.257.03:29:10.25#ibcon#about to read 5, iclass 30, count 0 2006.257.03:29:10.25#ibcon#read 5, iclass 30, count 0 2006.257.03:29:10.25#ibcon#about to read 6, iclass 30, count 0 2006.257.03:29:10.25#ibcon#read 6, iclass 30, count 0 2006.257.03:29:10.25#ibcon#end of sib2, iclass 30, count 0 2006.257.03:29:10.25#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:29:10.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:29:10.25#ibcon#[27=USB\r\n] 2006.257.03:29:10.25#ibcon#*before write, iclass 30, count 0 2006.257.03:29:10.25#ibcon#enter sib2, iclass 30, count 0 2006.257.03:29:10.25#ibcon#flushed, iclass 30, count 0 2006.257.03:29:10.25#ibcon#about to write, iclass 30, count 0 2006.257.03:29:10.25#ibcon#wrote, iclass 30, count 0 2006.257.03:29:10.25#ibcon#about to read 3, iclass 30, count 0 2006.257.03:29:10.28#ibcon#read 3, iclass 30, count 0 2006.257.03:29:10.28#ibcon#about to read 4, iclass 30, count 0 2006.257.03:29:10.28#ibcon#read 4, iclass 30, count 0 2006.257.03:29:10.28#ibcon#about to read 5, iclass 30, count 0 2006.257.03:29:10.28#ibcon#read 5, iclass 30, count 0 2006.257.03:29:10.28#ibcon#about to read 6, iclass 30, count 0 2006.257.03:29:10.28#ibcon#read 6, iclass 30, count 0 2006.257.03:29:10.28#ibcon#end of sib2, iclass 30, count 0 2006.257.03:29:10.28#ibcon#*after write, iclass 30, count 0 2006.257.03:29:10.28#ibcon#*before return 0, iclass 30, count 0 2006.257.03:29:10.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:10.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:29:10.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:29:10.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:29:10.28$vck44/vblo=7,734.99 2006.257.03:29:10.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.03:29:10.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.03:29:10.28#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:10.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:10.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:10.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:10.28#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:29:10.28#ibcon#first serial, iclass 32, count 0 2006.257.03:29:10.28#ibcon#enter sib2, iclass 32, count 0 2006.257.03:29:10.28#ibcon#flushed, iclass 32, count 0 2006.257.03:29:10.28#ibcon#about to write, iclass 32, count 0 2006.257.03:29:10.28#ibcon#wrote, iclass 32, count 0 2006.257.03:29:10.28#ibcon#about to read 3, iclass 32, count 0 2006.257.03:29:10.30#ibcon#read 3, iclass 32, count 0 2006.257.03:29:10.30#ibcon#about to read 4, iclass 32, count 0 2006.257.03:29:10.30#ibcon#read 4, iclass 32, count 0 2006.257.03:29:10.30#ibcon#about to read 5, iclass 32, count 0 2006.257.03:29:10.30#ibcon#read 5, iclass 32, count 0 2006.257.03:29:10.30#ibcon#about to read 6, iclass 32, count 0 2006.257.03:29:10.30#ibcon#read 6, iclass 32, count 0 2006.257.03:29:10.30#ibcon#end of sib2, iclass 32, count 0 2006.257.03:29:10.30#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:29:10.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:29:10.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:29:10.30#ibcon#*before write, iclass 32, count 0 2006.257.03:29:10.30#ibcon#enter sib2, iclass 32, count 0 2006.257.03:29:10.30#ibcon#flushed, iclass 32, count 0 2006.257.03:29:10.30#ibcon#about to write, iclass 32, count 0 2006.257.03:29:10.30#ibcon#wrote, iclass 32, count 0 2006.257.03:29:10.30#ibcon#about to read 3, iclass 32, count 0 2006.257.03:29:10.34#ibcon#read 3, iclass 32, count 0 2006.257.03:29:10.34#ibcon#about to read 4, iclass 32, count 0 2006.257.03:29:10.34#ibcon#read 4, iclass 32, count 0 2006.257.03:29:10.34#ibcon#about to read 5, iclass 32, count 0 2006.257.03:29:10.34#ibcon#read 5, iclass 32, count 0 2006.257.03:29:10.34#ibcon#about to read 6, iclass 32, count 0 2006.257.03:29:10.34#ibcon#read 6, iclass 32, count 0 2006.257.03:29:10.34#ibcon#end of sib2, iclass 32, count 0 2006.257.03:29:10.34#ibcon#*after write, iclass 32, count 0 2006.257.03:29:10.34#ibcon#*before return 0, iclass 32, count 0 2006.257.03:29:10.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:10.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:29:10.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:29:10.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:29:10.34$vck44/vb=7,4 2006.257.03:29:10.34#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.03:29:10.34#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.03:29:10.34#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:10.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:10.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:10.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:10.40#ibcon#enter wrdev, iclass 34, count 2 2006.257.03:29:10.40#ibcon#first serial, iclass 34, count 2 2006.257.03:29:10.40#ibcon#enter sib2, iclass 34, count 2 2006.257.03:29:10.40#ibcon#flushed, iclass 34, count 2 2006.257.03:29:10.40#ibcon#about to write, iclass 34, count 2 2006.257.03:29:10.40#ibcon#wrote, iclass 34, count 2 2006.257.03:29:10.40#ibcon#about to read 3, iclass 34, count 2 2006.257.03:29:10.42#ibcon#read 3, iclass 34, count 2 2006.257.03:29:10.42#ibcon#about to read 4, iclass 34, count 2 2006.257.03:29:10.42#ibcon#read 4, iclass 34, count 2 2006.257.03:29:10.42#ibcon#about to read 5, iclass 34, count 2 2006.257.03:29:10.42#ibcon#read 5, iclass 34, count 2 2006.257.03:29:10.42#ibcon#about to read 6, iclass 34, count 2 2006.257.03:29:10.42#ibcon#read 6, iclass 34, count 2 2006.257.03:29:10.42#ibcon#end of sib2, iclass 34, count 2 2006.257.03:29:10.42#ibcon#*mode == 0, iclass 34, count 2 2006.257.03:29:10.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.03:29:10.42#ibcon#[27=AT07-04\r\n] 2006.257.03:29:10.42#ibcon#*before write, iclass 34, count 2 2006.257.03:29:10.42#ibcon#enter sib2, iclass 34, count 2 2006.257.03:29:10.42#ibcon#flushed, iclass 34, count 2 2006.257.03:29:10.42#ibcon#about to write, iclass 34, count 2 2006.257.03:29:10.42#ibcon#wrote, iclass 34, count 2 2006.257.03:29:10.42#ibcon#about to read 3, iclass 34, count 2 2006.257.03:29:10.45#ibcon#read 3, iclass 34, count 2 2006.257.03:29:10.45#ibcon#about to read 4, iclass 34, count 2 2006.257.03:29:10.45#ibcon#read 4, iclass 34, count 2 2006.257.03:29:10.45#ibcon#about to read 5, iclass 34, count 2 2006.257.03:29:10.45#ibcon#read 5, iclass 34, count 2 2006.257.03:29:10.45#ibcon#about to read 6, iclass 34, count 2 2006.257.03:29:10.45#ibcon#read 6, iclass 34, count 2 2006.257.03:29:10.45#ibcon#end of sib2, iclass 34, count 2 2006.257.03:29:10.45#ibcon#*after write, iclass 34, count 2 2006.257.03:29:10.45#ibcon#*before return 0, iclass 34, count 2 2006.257.03:29:10.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:10.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:29:10.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.03:29:10.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:10.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:10.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:10.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:10.57#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:29:10.57#ibcon#first serial, iclass 34, count 0 2006.257.03:29:10.57#ibcon#enter sib2, iclass 34, count 0 2006.257.03:29:10.57#ibcon#flushed, iclass 34, count 0 2006.257.03:29:10.57#ibcon#about to write, iclass 34, count 0 2006.257.03:29:10.57#ibcon#wrote, iclass 34, count 0 2006.257.03:29:10.57#ibcon#about to read 3, iclass 34, count 0 2006.257.03:29:10.59#ibcon#read 3, iclass 34, count 0 2006.257.03:29:10.59#ibcon#about to read 4, iclass 34, count 0 2006.257.03:29:10.59#ibcon#read 4, iclass 34, count 0 2006.257.03:29:10.59#ibcon#about to read 5, iclass 34, count 0 2006.257.03:29:10.59#ibcon#read 5, iclass 34, count 0 2006.257.03:29:10.59#ibcon#about to read 6, iclass 34, count 0 2006.257.03:29:10.59#ibcon#read 6, iclass 34, count 0 2006.257.03:29:10.59#ibcon#end of sib2, iclass 34, count 0 2006.257.03:29:10.59#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:29:10.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:29:10.59#ibcon#[27=USB\r\n] 2006.257.03:29:10.59#ibcon#*before write, iclass 34, count 0 2006.257.03:29:10.59#ibcon#enter sib2, iclass 34, count 0 2006.257.03:29:10.59#ibcon#flushed, iclass 34, count 0 2006.257.03:29:10.59#ibcon#about to write, iclass 34, count 0 2006.257.03:29:10.59#ibcon#wrote, iclass 34, count 0 2006.257.03:29:10.59#ibcon#about to read 3, iclass 34, count 0 2006.257.03:29:10.62#ibcon#read 3, iclass 34, count 0 2006.257.03:29:10.62#ibcon#about to read 4, iclass 34, count 0 2006.257.03:29:10.62#ibcon#read 4, iclass 34, count 0 2006.257.03:29:10.62#ibcon#about to read 5, iclass 34, count 0 2006.257.03:29:10.62#ibcon#read 5, iclass 34, count 0 2006.257.03:29:10.62#ibcon#about to read 6, iclass 34, count 0 2006.257.03:29:10.62#ibcon#read 6, iclass 34, count 0 2006.257.03:29:10.62#ibcon#end of sib2, iclass 34, count 0 2006.257.03:29:10.62#ibcon#*after write, iclass 34, count 0 2006.257.03:29:10.62#ibcon#*before return 0, iclass 34, count 0 2006.257.03:29:10.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:10.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:29:10.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:29:10.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:29:10.62$vck44/vblo=8,744.99 2006.257.03:29:10.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.03:29:10.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.03:29:10.62#ibcon#ireg 17 cls_cnt 0 2006.257.03:29:10.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:10.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:10.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:10.62#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:29:10.62#ibcon#first serial, iclass 36, count 0 2006.257.03:29:10.62#ibcon#enter sib2, iclass 36, count 0 2006.257.03:29:10.62#ibcon#flushed, iclass 36, count 0 2006.257.03:29:10.62#ibcon#about to write, iclass 36, count 0 2006.257.03:29:10.62#ibcon#wrote, iclass 36, count 0 2006.257.03:29:10.62#ibcon#about to read 3, iclass 36, count 0 2006.257.03:29:10.64#ibcon#read 3, iclass 36, count 0 2006.257.03:29:10.64#ibcon#about to read 4, iclass 36, count 0 2006.257.03:29:10.64#ibcon#read 4, iclass 36, count 0 2006.257.03:29:10.64#ibcon#about to read 5, iclass 36, count 0 2006.257.03:29:10.64#ibcon#read 5, iclass 36, count 0 2006.257.03:29:10.64#ibcon#about to read 6, iclass 36, count 0 2006.257.03:29:10.64#ibcon#read 6, iclass 36, count 0 2006.257.03:29:10.64#ibcon#end of sib2, iclass 36, count 0 2006.257.03:29:10.64#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:29:10.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:29:10.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:29:10.64#ibcon#*before write, iclass 36, count 0 2006.257.03:29:10.64#ibcon#enter sib2, iclass 36, count 0 2006.257.03:29:10.64#ibcon#flushed, iclass 36, count 0 2006.257.03:29:10.64#ibcon#about to write, iclass 36, count 0 2006.257.03:29:10.64#ibcon#wrote, iclass 36, count 0 2006.257.03:29:10.64#ibcon#about to read 3, iclass 36, count 0 2006.257.03:29:10.68#ibcon#read 3, iclass 36, count 0 2006.257.03:29:10.68#ibcon#about to read 4, iclass 36, count 0 2006.257.03:29:10.68#ibcon#read 4, iclass 36, count 0 2006.257.03:29:10.68#ibcon#about to read 5, iclass 36, count 0 2006.257.03:29:10.68#ibcon#read 5, iclass 36, count 0 2006.257.03:29:10.68#ibcon#about to read 6, iclass 36, count 0 2006.257.03:29:10.68#ibcon#read 6, iclass 36, count 0 2006.257.03:29:10.68#ibcon#end of sib2, iclass 36, count 0 2006.257.03:29:10.68#ibcon#*after write, iclass 36, count 0 2006.257.03:29:10.68#ibcon#*before return 0, iclass 36, count 0 2006.257.03:29:10.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:10.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:29:10.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:29:10.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:29:10.68$vck44/vb=8,4 2006.257.03:29:10.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.03:29:10.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.03:29:10.68#ibcon#ireg 11 cls_cnt 2 2006.257.03:29:10.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:10.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:10.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:10.74#ibcon#enter wrdev, iclass 38, count 2 2006.257.03:29:10.74#ibcon#first serial, iclass 38, count 2 2006.257.03:29:10.74#ibcon#enter sib2, iclass 38, count 2 2006.257.03:29:10.74#ibcon#flushed, iclass 38, count 2 2006.257.03:29:10.74#ibcon#about to write, iclass 38, count 2 2006.257.03:29:10.74#ibcon#wrote, iclass 38, count 2 2006.257.03:29:10.74#ibcon#about to read 3, iclass 38, count 2 2006.257.03:29:10.76#ibcon#read 3, iclass 38, count 2 2006.257.03:29:10.76#ibcon#about to read 4, iclass 38, count 2 2006.257.03:29:10.76#ibcon#read 4, iclass 38, count 2 2006.257.03:29:10.76#ibcon#about to read 5, iclass 38, count 2 2006.257.03:29:10.76#ibcon#read 5, iclass 38, count 2 2006.257.03:29:10.76#ibcon#about to read 6, iclass 38, count 2 2006.257.03:29:10.76#ibcon#read 6, iclass 38, count 2 2006.257.03:29:10.76#ibcon#end of sib2, iclass 38, count 2 2006.257.03:29:10.76#ibcon#*mode == 0, iclass 38, count 2 2006.257.03:29:10.76#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.03:29:10.76#ibcon#[27=AT08-04\r\n] 2006.257.03:29:10.76#ibcon#*before write, iclass 38, count 2 2006.257.03:29:10.76#ibcon#enter sib2, iclass 38, count 2 2006.257.03:29:10.76#ibcon#flushed, iclass 38, count 2 2006.257.03:29:10.76#ibcon#about to write, iclass 38, count 2 2006.257.03:29:10.76#ibcon#wrote, iclass 38, count 2 2006.257.03:29:10.76#ibcon#about to read 3, iclass 38, count 2 2006.257.03:29:10.79#ibcon#read 3, iclass 38, count 2 2006.257.03:29:10.79#ibcon#about to read 4, iclass 38, count 2 2006.257.03:29:10.79#ibcon#read 4, iclass 38, count 2 2006.257.03:29:10.79#ibcon#about to read 5, iclass 38, count 2 2006.257.03:29:10.79#ibcon#read 5, iclass 38, count 2 2006.257.03:29:10.79#ibcon#about to read 6, iclass 38, count 2 2006.257.03:29:10.79#ibcon#read 6, iclass 38, count 2 2006.257.03:29:10.79#ibcon#end of sib2, iclass 38, count 2 2006.257.03:29:10.79#ibcon#*after write, iclass 38, count 2 2006.257.03:29:10.79#ibcon#*before return 0, iclass 38, count 2 2006.257.03:29:10.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:10.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:29:10.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.03:29:10.79#ibcon#ireg 7 cls_cnt 0 2006.257.03:29:10.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:10.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:10.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:10.91#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:29:10.91#ibcon#first serial, iclass 38, count 0 2006.257.03:29:10.91#ibcon#enter sib2, iclass 38, count 0 2006.257.03:29:10.91#ibcon#flushed, iclass 38, count 0 2006.257.03:29:10.91#ibcon#about to write, iclass 38, count 0 2006.257.03:29:10.91#ibcon#wrote, iclass 38, count 0 2006.257.03:29:10.91#ibcon#about to read 3, iclass 38, count 0 2006.257.03:29:10.93#ibcon#read 3, iclass 38, count 0 2006.257.03:29:10.93#ibcon#about to read 4, iclass 38, count 0 2006.257.03:29:10.93#ibcon#read 4, iclass 38, count 0 2006.257.03:29:10.93#ibcon#about to read 5, iclass 38, count 0 2006.257.03:29:10.93#ibcon#read 5, iclass 38, count 0 2006.257.03:29:10.93#ibcon#about to read 6, iclass 38, count 0 2006.257.03:29:10.93#ibcon#read 6, iclass 38, count 0 2006.257.03:29:10.93#ibcon#end of sib2, iclass 38, count 0 2006.257.03:29:10.93#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:29:10.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:29:10.93#ibcon#[27=USB\r\n] 2006.257.03:29:10.93#ibcon#*before write, iclass 38, count 0 2006.257.03:29:10.93#ibcon#enter sib2, iclass 38, count 0 2006.257.03:29:10.93#ibcon#flushed, iclass 38, count 0 2006.257.03:29:10.93#ibcon#about to write, iclass 38, count 0 2006.257.03:29:10.93#ibcon#wrote, iclass 38, count 0 2006.257.03:29:10.93#ibcon#about to read 3, iclass 38, count 0 2006.257.03:29:10.96#ibcon#read 3, iclass 38, count 0 2006.257.03:29:10.96#ibcon#about to read 4, iclass 38, count 0 2006.257.03:29:10.96#ibcon#read 4, iclass 38, count 0 2006.257.03:29:10.96#ibcon#about to read 5, iclass 38, count 0 2006.257.03:29:10.96#ibcon#read 5, iclass 38, count 0 2006.257.03:29:10.96#ibcon#about to read 6, iclass 38, count 0 2006.257.03:29:10.96#ibcon#read 6, iclass 38, count 0 2006.257.03:29:10.96#ibcon#end of sib2, iclass 38, count 0 2006.257.03:29:10.96#ibcon#*after write, iclass 38, count 0 2006.257.03:29:10.96#ibcon#*before return 0, iclass 38, count 0 2006.257.03:29:10.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:10.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:29:10.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:29:10.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:29:10.96$vck44/vabw=wide 2006.257.03:29:10.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.03:29:10.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.03:29:10.96#ibcon#ireg 8 cls_cnt 0 2006.257.03:29:10.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:10.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:10.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:10.96#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:29:10.96#ibcon#first serial, iclass 40, count 0 2006.257.03:29:10.96#ibcon#enter sib2, iclass 40, count 0 2006.257.03:29:10.96#ibcon#flushed, iclass 40, count 0 2006.257.03:29:10.96#ibcon#about to write, iclass 40, count 0 2006.257.03:29:10.96#ibcon#wrote, iclass 40, count 0 2006.257.03:29:10.96#ibcon#about to read 3, iclass 40, count 0 2006.257.03:29:10.98#ibcon#read 3, iclass 40, count 0 2006.257.03:29:10.98#ibcon#about to read 4, iclass 40, count 0 2006.257.03:29:10.98#ibcon#read 4, iclass 40, count 0 2006.257.03:29:10.98#ibcon#about to read 5, iclass 40, count 0 2006.257.03:29:10.98#ibcon#read 5, iclass 40, count 0 2006.257.03:29:10.98#ibcon#about to read 6, iclass 40, count 0 2006.257.03:29:10.98#ibcon#read 6, iclass 40, count 0 2006.257.03:29:10.98#ibcon#end of sib2, iclass 40, count 0 2006.257.03:29:10.98#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:29:10.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:29:10.98#ibcon#[25=BW32\r\n] 2006.257.03:29:10.98#ibcon#*before write, iclass 40, count 0 2006.257.03:29:10.98#ibcon#enter sib2, iclass 40, count 0 2006.257.03:29:10.98#ibcon#flushed, iclass 40, count 0 2006.257.03:29:10.98#ibcon#about to write, iclass 40, count 0 2006.257.03:29:10.98#ibcon#wrote, iclass 40, count 0 2006.257.03:29:10.98#ibcon#about to read 3, iclass 40, count 0 2006.257.03:29:11.01#ibcon#read 3, iclass 40, count 0 2006.257.03:29:11.01#ibcon#about to read 4, iclass 40, count 0 2006.257.03:29:11.01#ibcon#read 4, iclass 40, count 0 2006.257.03:29:11.01#ibcon#about to read 5, iclass 40, count 0 2006.257.03:29:11.01#ibcon#read 5, iclass 40, count 0 2006.257.03:29:11.01#ibcon#about to read 6, iclass 40, count 0 2006.257.03:29:11.01#ibcon#read 6, iclass 40, count 0 2006.257.03:29:11.01#ibcon#end of sib2, iclass 40, count 0 2006.257.03:29:11.01#ibcon#*after write, iclass 40, count 0 2006.257.03:29:11.01#ibcon#*before return 0, iclass 40, count 0 2006.257.03:29:11.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:11.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:29:11.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:29:11.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:29:11.01$vck44/vbbw=wide 2006.257.03:29:11.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.03:29:11.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.03:29:11.01#ibcon#ireg 8 cls_cnt 0 2006.257.03:29:11.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:29:11.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:29:11.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:29:11.08#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:29:11.08#ibcon#first serial, iclass 4, count 0 2006.257.03:29:11.08#ibcon#enter sib2, iclass 4, count 0 2006.257.03:29:11.08#ibcon#flushed, iclass 4, count 0 2006.257.03:29:11.08#ibcon#about to write, iclass 4, count 0 2006.257.03:29:11.08#ibcon#wrote, iclass 4, count 0 2006.257.03:29:11.08#ibcon#about to read 3, iclass 4, count 0 2006.257.03:29:11.10#ibcon#read 3, iclass 4, count 0 2006.257.03:29:11.10#ibcon#about to read 4, iclass 4, count 0 2006.257.03:29:11.10#ibcon#read 4, iclass 4, count 0 2006.257.03:29:11.10#ibcon#about to read 5, iclass 4, count 0 2006.257.03:29:11.10#ibcon#read 5, iclass 4, count 0 2006.257.03:29:11.10#ibcon#about to read 6, iclass 4, count 0 2006.257.03:29:11.10#ibcon#read 6, iclass 4, count 0 2006.257.03:29:11.10#ibcon#end of sib2, iclass 4, count 0 2006.257.03:29:11.10#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:29:11.10#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:29:11.10#ibcon#[27=BW32\r\n] 2006.257.03:29:11.10#ibcon#*before write, iclass 4, count 0 2006.257.03:29:11.10#ibcon#enter sib2, iclass 4, count 0 2006.257.03:29:11.10#ibcon#flushed, iclass 4, count 0 2006.257.03:29:11.10#ibcon#about to write, iclass 4, count 0 2006.257.03:29:11.10#ibcon#wrote, iclass 4, count 0 2006.257.03:29:11.10#ibcon#about to read 3, iclass 4, count 0 2006.257.03:29:11.13#ibcon#read 3, iclass 4, count 0 2006.257.03:29:11.13#ibcon#about to read 4, iclass 4, count 0 2006.257.03:29:11.13#ibcon#read 4, iclass 4, count 0 2006.257.03:29:11.13#ibcon#about to read 5, iclass 4, count 0 2006.257.03:29:11.13#ibcon#read 5, iclass 4, count 0 2006.257.03:29:11.13#ibcon#about to read 6, iclass 4, count 0 2006.257.03:29:11.13#ibcon#read 6, iclass 4, count 0 2006.257.03:29:11.13#ibcon#end of sib2, iclass 4, count 0 2006.257.03:29:11.13#ibcon#*after write, iclass 4, count 0 2006.257.03:29:11.13#ibcon#*before return 0, iclass 4, count 0 2006.257.03:29:11.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:29:11.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:29:11.13#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:29:11.13#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:29:11.13$setupk4/ifdk4 2006.257.03:29:11.13$ifdk4/lo= 2006.257.03:29:11.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:29:11.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:29:11.13$ifdk4/patch= 2006.257.03:29:11.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:29:11.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:29:11.13$setupk4/!*+20s 2006.257.03:29:12.16#abcon#<5=/14 1.6 4.8 19.17 951012.1\r\n> 2006.257.03:29:12.18#abcon#{5=INTERFACE CLEAR} 2006.257.03:29:12.24#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:29:22.33#abcon#<5=/14 1.6 4.7 19.17 961012.1\r\n> 2006.257.03:29:22.35#abcon#{5=INTERFACE CLEAR} 2006.257.03:29:22.41#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:29:25.64$setupk4/"tpicd 2006.257.03:29:25.64$setupk4/echo=off 2006.257.03:29:25.64$setupk4/xlog=off 2006.257.03:29:25.64:!2006.257.03:32:52 2006.257.03:29:27.14#trakl#Source acquired 2006.257.03:29:29.14#flagr#flagr/antenna,acquired 2006.257.03:32:52.00:preob 2006.257.03:32:52.14/onsource/TRACKING 2006.257.03:32:52.14:!2006.257.03:33:02 2006.257.03:33:02.00:"tape 2006.257.03:33:02.00:"st=record 2006.257.03:33:02.00:data_valid=on 2006.257.03:33:02.00:midob 2006.257.03:33:02.14/onsource/TRACKING 2006.257.03:33:02.14/wx/19.25,1012.1,95 2006.257.03:33:02.19/cable/+6.4854E-03 2006.257.03:33:03.28/va/01,08,usb,yes,32,34 2006.257.03:33:03.28/va/02,07,usb,yes,35,35 2006.257.03:33:03.28/va/03,08,usb,yes,31,33 2006.257.03:33:03.28/va/04,07,usb,yes,36,37 2006.257.03:33:03.28/va/05,04,usb,yes,32,32 2006.257.03:33:03.28/va/06,04,usb,yes,36,35 2006.257.03:33:03.28/va/07,04,usb,yes,36,37 2006.257.03:33:03.28/va/08,04,usb,yes,30,37 2006.257.03:33:03.51/valo/01,524.99,yes,locked 2006.257.03:33:03.51/valo/02,534.99,yes,locked 2006.257.03:33:03.51/valo/03,564.99,yes,locked 2006.257.03:33:03.51/valo/04,624.99,yes,locked 2006.257.03:33:03.51/valo/05,734.99,yes,locked 2006.257.03:33:03.51/valo/06,814.99,yes,locked 2006.257.03:33:03.51/valo/07,864.99,yes,locked 2006.257.03:33:03.51/valo/08,884.99,yes,locked 2006.257.03:33:04.60/vb/01,04,usb,yes,30,29 2006.257.03:33:04.60/vb/02,05,usb,yes,29,30 2006.257.03:33:04.60/vb/03,04,usb,yes,30,33 2006.257.03:33:04.60/vb/04,05,usb,yes,30,29 2006.257.03:33:04.60/vb/05,04,usb,yes,27,29 2006.257.03:33:04.60/vb/06,04,usb,yes,32,28 2006.257.03:33:04.60/vb/07,04,usb,yes,31,31 2006.257.03:33:04.60/vb/08,04,usb,yes,29,32 2006.257.03:33:04.83/vblo/01,629.99,yes,locked 2006.257.03:33:04.83/vblo/02,634.99,yes,locked 2006.257.03:33:04.83/vblo/03,649.99,yes,locked 2006.257.03:33:04.83/vblo/04,679.99,yes,locked 2006.257.03:33:04.83/vblo/05,709.99,yes,locked 2006.257.03:33:04.83/vblo/06,719.99,yes,locked 2006.257.03:33:04.83/vblo/07,734.99,yes,locked 2006.257.03:33:04.83/vblo/08,744.99,yes,locked 2006.257.03:33:04.98/vabw/8 2006.257.03:33:05.13/vbbw/8 2006.257.03:33:05.22/xfe/off,on,16.5 2006.257.03:33:05.59/ifatt/23,28,28,28 2006.257.03:33:06.08/fmout-gps/S +4.53E-07 2006.257.03:33:06.12:!2006.257.03:36:42 2006.257.03:36:42.02:data_valid=off 2006.257.03:36:42.02:"et 2006.257.03:36:42.02:!+3s 2006.257.03:36:45.03:"tape 2006.257.03:36:45.03:postob 2006.257.03:36:45.16/cable/+6.4847E-03 2006.257.03:36:45.16/wx/19.40,1012.0,95 2006.257.03:36:45.22/fmout-gps/S +4.54E-07 2006.257.03:36:45.22:scan_name=257-0346,jd0609,40 2006.257.03:36:45.22:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.257.03:36:47.13#flagr#flagr/antenna,new-source 2006.257.03:36:47.13:checkk5 2006.257.03:36:47.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:36:47.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:36:48.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:36:48.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:36:48.87/chk_obsdata//k5ts1/T2570333??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.03:36:49.22/chk_obsdata//k5ts2/T2570333??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.03:36:49.58/chk_obsdata//k5ts3/T2570333??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.03:36:49.93/chk_obsdata//k5ts4/T2570333??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.03:36:50.59/k5log//k5ts1_log_newline 2006.257.03:36:51.26/k5log//k5ts2_log_newline 2006.257.03:36:51.96/k5log//k5ts3_log_newline 2006.257.03:36:52.62/k5log//k5ts4_log_newline 2006.257.03:36:52.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:36:52.64:setupk4=1 2006.257.03:36:52.64$setupk4/echo=on 2006.257.03:36:52.64$setupk4/pcalon 2006.257.03:36:52.64$pcalon/"no phase cal control is implemented here 2006.257.03:36:52.64$setupk4/"tpicd=stop 2006.257.03:36:52.64$setupk4/"rec=synch_on 2006.257.03:36:52.64$setupk4/"rec_mode=128 2006.257.03:36:52.64$setupk4/!* 2006.257.03:36:52.64$setupk4/recpk4 2006.257.03:36:52.64$recpk4/recpatch= 2006.257.03:36:52.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:36:52.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:36:52.65$setupk4/vck44 2006.257.03:36:52.65$vck44/valo=1,524.99 2006.257.03:36:52.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.03:36:52.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.03:36:52.65#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:52.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:52.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:52.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:52.65#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:36:52.65#ibcon#first serial, iclass 15, count 0 2006.257.03:36:52.65#ibcon#enter sib2, iclass 15, count 0 2006.257.03:36:52.65#ibcon#flushed, iclass 15, count 0 2006.257.03:36:52.65#ibcon#about to write, iclass 15, count 0 2006.257.03:36:52.65#ibcon#wrote, iclass 15, count 0 2006.257.03:36:52.65#ibcon#about to read 3, iclass 15, count 0 2006.257.03:36:52.66#ibcon#read 3, iclass 15, count 0 2006.257.03:36:52.66#ibcon#about to read 4, iclass 15, count 0 2006.257.03:36:52.66#ibcon#read 4, iclass 15, count 0 2006.257.03:36:52.66#ibcon#about to read 5, iclass 15, count 0 2006.257.03:36:52.67#ibcon#read 5, iclass 15, count 0 2006.257.03:36:52.67#ibcon#about to read 6, iclass 15, count 0 2006.257.03:36:52.67#ibcon#read 6, iclass 15, count 0 2006.257.03:36:52.67#ibcon#end of sib2, iclass 15, count 0 2006.257.03:36:52.67#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:36:52.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:36:52.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:36:52.67#ibcon#*before write, iclass 15, count 0 2006.257.03:36:52.67#ibcon#enter sib2, iclass 15, count 0 2006.257.03:36:52.67#ibcon#flushed, iclass 15, count 0 2006.257.03:36:52.67#ibcon#about to write, iclass 15, count 0 2006.257.03:36:52.67#ibcon#wrote, iclass 15, count 0 2006.257.03:36:52.67#ibcon#about to read 3, iclass 15, count 0 2006.257.03:36:52.71#ibcon#read 3, iclass 15, count 0 2006.257.03:36:52.71#ibcon#about to read 4, iclass 15, count 0 2006.257.03:36:52.71#ibcon#read 4, iclass 15, count 0 2006.257.03:36:52.71#ibcon#about to read 5, iclass 15, count 0 2006.257.03:36:52.71#ibcon#read 5, iclass 15, count 0 2006.257.03:36:52.72#ibcon#about to read 6, iclass 15, count 0 2006.257.03:36:52.72#ibcon#read 6, iclass 15, count 0 2006.257.03:36:52.72#ibcon#end of sib2, iclass 15, count 0 2006.257.03:36:52.72#ibcon#*after write, iclass 15, count 0 2006.257.03:36:52.72#ibcon#*before return 0, iclass 15, count 0 2006.257.03:36:52.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:52.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:52.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:36:52.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:36:52.72$vck44/va=1,8 2006.257.03:36:52.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.03:36:52.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.03:36:52.72#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:52.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:52.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:52.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:52.72#ibcon#enter wrdev, iclass 17, count 2 2006.257.03:36:52.72#ibcon#first serial, iclass 17, count 2 2006.257.03:36:52.72#ibcon#enter sib2, iclass 17, count 2 2006.257.03:36:52.72#ibcon#flushed, iclass 17, count 2 2006.257.03:36:52.72#ibcon#about to write, iclass 17, count 2 2006.257.03:36:52.72#ibcon#wrote, iclass 17, count 2 2006.257.03:36:52.72#ibcon#about to read 3, iclass 17, count 2 2006.257.03:36:52.73#ibcon#read 3, iclass 17, count 2 2006.257.03:36:52.73#ibcon#about to read 4, iclass 17, count 2 2006.257.03:36:52.73#ibcon#read 4, iclass 17, count 2 2006.257.03:36:52.73#ibcon#about to read 5, iclass 17, count 2 2006.257.03:36:52.74#ibcon#read 5, iclass 17, count 2 2006.257.03:36:52.74#ibcon#about to read 6, iclass 17, count 2 2006.257.03:36:52.74#ibcon#read 6, iclass 17, count 2 2006.257.03:36:52.74#ibcon#end of sib2, iclass 17, count 2 2006.257.03:36:52.74#ibcon#*mode == 0, iclass 17, count 2 2006.257.03:36:52.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.03:36:52.74#ibcon#[25=AT01-08\r\n] 2006.257.03:36:52.74#ibcon#*before write, iclass 17, count 2 2006.257.03:36:52.74#ibcon#enter sib2, iclass 17, count 2 2006.257.03:36:52.74#ibcon#flushed, iclass 17, count 2 2006.257.03:36:52.74#ibcon#about to write, iclass 17, count 2 2006.257.03:36:52.74#ibcon#wrote, iclass 17, count 2 2006.257.03:36:52.74#ibcon#about to read 3, iclass 17, count 2 2006.257.03:36:52.76#ibcon#read 3, iclass 17, count 2 2006.257.03:36:52.76#ibcon#about to read 4, iclass 17, count 2 2006.257.03:36:52.76#ibcon#read 4, iclass 17, count 2 2006.257.03:36:52.76#ibcon#about to read 5, iclass 17, count 2 2006.257.03:36:52.76#ibcon#read 5, iclass 17, count 2 2006.257.03:36:52.77#ibcon#about to read 6, iclass 17, count 2 2006.257.03:36:52.77#ibcon#read 6, iclass 17, count 2 2006.257.03:36:52.77#ibcon#end of sib2, iclass 17, count 2 2006.257.03:36:52.77#ibcon#*after write, iclass 17, count 2 2006.257.03:36:52.77#ibcon#*before return 0, iclass 17, count 2 2006.257.03:36:52.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:52.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:52.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.03:36:52.77#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:52.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:52.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:52.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:52.88#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:36:52.88#ibcon#first serial, iclass 17, count 0 2006.257.03:36:52.88#ibcon#enter sib2, iclass 17, count 0 2006.257.03:36:52.88#ibcon#flushed, iclass 17, count 0 2006.257.03:36:52.89#ibcon#about to write, iclass 17, count 0 2006.257.03:36:52.89#ibcon#wrote, iclass 17, count 0 2006.257.03:36:52.89#ibcon#about to read 3, iclass 17, count 0 2006.257.03:36:52.90#ibcon#read 3, iclass 17, count 0 2006.257.03:36:52.90#ibcon#about to read 4, iclass 17, count 0 2006.257.03:36:52.90#ibcon#read 4, iclass 17, count 0 2006.257.03:36:52.90#ibcon#about to read 5, iclass 17, count 0 2006.257.03:36:52.90#ibcon#read 5, iclass 17, count 0 2006.257.03:36:52.91#ibcon#about to read 6, iclass 17, count 0 2006.257.03:36:52.91#ibcon#read 6, iclass 17, count 0 2006.257.03:36:52.91#ibcon#end of sib2, iclass 17, count 0 2006.257.03:36:52.91#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:36:52.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:36:52.91#ibcon#[25=USB\r\n] 2006.257.03:36:52.91#ibcon#*before write, iclass 17, count 0 2006.257.03:36:52.91#ibcon#enter sib2, iclass 17, count 0 2006.257.03:36:52.91#ibcon#flushed, iclass 17, count 0 2006.257.03:36:52.91#ibcon#about to write, iclass 17, count 0 2006.257.03:36:52.91#ibcon#wrote, iclass 17, count 0 2006.257.03:36:52.91#ibcon#about to read 3, iclass 17, count 0 2006.257.03:36:52.93#ibcon#read 3, iclass 17, count 0 2006.257.03:36:52.93#ibcon#about to read 4, iclass 17, count 0 2006.257.03:36:52.93#ibcon#read 4, iclass 17, count 0 2006.257.03:36:52.93#ibcon#about to read 5, iclass 17, count 0 2006.257.03:36:52.93#ibcon#read 5, iclass 17, count 0 2006.257.03:36:52.94#ibcon#about to read 6, iclass 17, count 0 2006.257.03:36:52.94#ibcon#read 6, iclass 17, count 0 2006.257.03:36:52.94#ibcon#end of sib2, iclass 17, count 0 2006.257.03:36:52.94#ibcon#*after write, iclass 17, count 0 2006.257.03:36:52.94#ibcon#*before return 0, iclass 17, count 0 2006.257.03:36:52.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:52.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:52.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:36:52.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:36:52.94$vck44/valo=2,534.99 2006.257.03:36:52.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.03:36:52.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.03:36:52.94#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:52.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:52.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:52.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:52.94#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:36:52.94#ibcon#first serial, iclass 19, count 0 2006.257.03:36:52.94#ibcon#enter sib2, iclass 19, count 0 2006.257.03:36:52.94#ibcon#flushed, iclass 19, count 0 2006.257.03:36:52.94#ibcon#about to write, iclass 19, count 0 2006.257.03:36:52.94#ibcon#wrote, iclass 19, count 0 2006.257.03:36:52.94#ibcon#about to read 3, iclass 19, count 0 2006.257.03:36:52.95#ibcon#read 3, iclass 19, count 0 2006.257.03:36:52.95#ibcon#about to read 4, iclass 19, count 0 2006.257.03:36:52.95#ibcon#read 4, iclass 19, count 0 2006.257.03:36:52.95#ibcon#about to read 5, iclass 19, count 0 2006.257.03:36:52.95#ibcon#read 5, iclass 19, count 0 2006.257.03:36:52.96#ibcon#about to read 6, iclass 19, count 0 2006.257.03:36:52.96#ibcon#read 6, iclass 19, count 0 2006.257.03:36:52.96#ibcon#end of sib2, iclass 19, count 0 2006.257.03:36:52.96#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:36:52.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:36:52.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:36:52.96#ibcon#*before write, iclass 19, count 0 2006.257.03:36:52.96#ibcon#enter sib2, iclass 19, count 0 2006.257.03:36:52.96#ibcon#flushed, iclass 19, count 0 2006.257.03:36:52.96#ibcon#about to write, iclass 19, count 0 2006.257.03:36:52.96#ibcon#wrote, iclass 19, count 0 2006.257.03:36:52.96#ibcon#about to read 3, iclass 19, count 0 2006.257.03:36:52.99#ibcon#read 3, iclass 19, count 0 2006.257.03:36:52.99#ibcon#about to read 4, iclass 19, count 0 2006.257.03:36:52.99#ibcon#read 4, iclass 19, count 0 2006.257.03:36:52.99#ibcon#about to read 5, iclass 19, count 0 2006.257.03:36:52.99#ibcon#read 5, iclass 19, count 0 2006.257.03:36:53.00#ibcon#about to read 6, iclass 19, count 0 2006.257.03:36:53.00#ibcon#read 6, iclass 19, count 0 2006.257.03:36:53.00#ibcon#end of sib2, iclass 19, count 0 2006.257.03:36:53.00#ibcon#*after write, iclass 19, count 0 2006.257.03:36:53.00#ibcon#*before return 0, iclass 19, count 0 2006.257.03:36:53.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:53.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:53.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:36:53.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:36:53.00$vck44/va=2,7 2006.257.03:36:53.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.03:36:53.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.03:36:53.00#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:53.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:53.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:53.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:53.05#ibcon#enter wrdev, iclass 21, count 2 2006.257.03:36:53.05#ibcon#first serial, iclass 21, count 2 2006.257.03:36:53.05#ibcon#enter sib2, iclass 21, count 2 2006.257.03:36:53.05#ibcon#flushed, iclass 21, count 2 2006.257.03:36:53.05#ibcon#about to write, iclass 21, count 2 2006.257.03:36:53.06#ibcon#wrote, iclass 21, count 2 2006.257.03:36:53.06#ibcon#about to read 3, iclass 21, count 2 2006.257.03:36:53.07#ibcon#read 3, iclass 21, count 2 2006.257.03:36:53.07#ibcon#about to read 4, iclass 21, count 2 2006.257.03:36:53.07#ibcon#read 4, iclass 21, count 2 2006.257.03:36:53.07#ibcon#about to read 5, iclass 21, count 2 2006.257.03:36:53.07#ibcon#read 5, iclass 21, count 2 2006.257.03:36:53.08#ibcon#about to read 6, iclass 21, count 2 2006.257.03:36:53.08#ibcon#read 6, iclass 21, count 2 2006.257.03:36:53.08#ibcon#end of sib2, iclass 21, count 2 2006.257.03:36:53.08#ibcon#*mode == 0, iclass 21, count 2 2006.257.03:36:53.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.03:36:53.08#ibcon#[25=AT02-07\r\n] 2006.257.03:36:53.08#ibcon#*before write, iclass 21, count 2 2006.257.03:36:53.08#ibcon#enter sib2, iclass 21, count 2 2006.257.03:36:53.08#ibcon#flushed, iclass 21, count 2 2006.257.03:36:53.08#ibcon#about to write, iclass 21, count 2 2006.257.03:36:53.08#ibcon#wrote, iclass 21, count 2 2006.257.03:36:53.08#ibcon#about to read 3, iclass 21, count 2 2006.257.03:36:53.10#ibcon#read 3, iclass 21, count 2 2006.257.03:36:53.10#ibcon#about to read 4, iclass 21, count 2 2006.257.03:36:53.10#ibcon#read 4, iclass 21, count 2 2006.257.03:36:53.10#ibcon#about to read 5, iclass 21, count 2 2006.257.03:36:53.10#ibcon#read 5, iclass 21, count 2 2006.257.03:36:53.11#ibcon#about to read 6, iclass 21, count 2 2006.257.03:36:53.11#ibcon#read 6, iclass 21, count 2 2006.257.03:36:53.11#ibcon#end of sib2, iclass 21, count 2 2006.257.03:36:53.11#ibcon#*after write, iclass 21, count 2 2006.257.03:36:53.11#ibcon#*before return 0, iclass 21, count 2 2006.257.03:36:53.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:53.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:53.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.03:36:53.11#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:53.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:53.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:53.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:53.23#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:36:53.23#ibcon#first serial, iclass 21, count 0 2006.257.03:36:53.23#ibcon#enter sib2, iclass 21, count 0 2006.257.03:36:53.23#ibcon#flushed, iclass 21, count 0 2006.257.03:36:53.23#ibcon#about to write, iclass 21, count 0 2006.257.03:36:53.23#ibcon#wrote, iclass 21, count 0 2006.257.03:36:53.23#ibcon#about to read 3, iclass 21, count 0 2006.257.03:36:53.24#ibcon#read 3, iclass 21, count 0 2006.257.03:36:53.24#ibcon#about to read 4, iclass 21, count 0 2006.257.03:36:53.24#ibcon#read 4, iclass 21, count 0 2006.257.03:36:53.24#ibcon#about to read 5, iclass 21, count 0 2006.257.03:36:53.24#ibcon#read 5, iclass 21, count 0 2006.257.03:36:53.25#ibcon#about to read 6, iclass 21, count 0 2006.257.03:36:53.25#ibcon#read 6, iclass 21, count 0 2006.257.03:36:53.25#ibcon#end of sib2, iclass 21, count 0 2006.257.03:36:53.25#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:36:53.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:36:53.25#ibcon#[25=USB\r\n] 2006.257.03:36:53.25#ibcon#*before write, iclass 21, count 0 2006.257.03:36:53.25#ibcon#enter sib2, iclass 21, count 0 2006.257.03:36:53.25#ibcon#flushed, iclass 21, count 0 2006.257.03:36:53.25#ibcon#about to write, iclass 21, count 0 2006.257.03:36:53.25#ibcon#wrote, iclass 21, count 0 2006.257.03:36:53.25#ibcon#about to read 3, iclass 21, count 0 2006.257.03:36:53.27#ibcon#read 3, iclass 21, count 0 2006.257.03:36:53.27#ibcon#about to read 4, iclass 21, count 0 2006.257.03:36:53.27#ibcon#read 4, iclass 21, count 0 2006.257.03:36:53.27#ibcon#about to read 5, iclass 21, count 0 2006.257.03:36:53.27#ibcon#read 5, iclass 21, count 0 2006.257.03:36:53.28#ibcon#about to read 6, iclass 21, count 0 2006.257.03:36:53.28#ibcon#read 6, iclass 21, count 0 2006.257.03:36:53.28#ibcon#end of sib2, iclass 21, count 0 2006.257.03:36:53.28#ibcon#*after write, iclass 21, count 0 2006.257.03:36:53.28#ibcon#*before return 0, iclass 21, count 0 2006.257.03:36:53.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:53.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:53.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:36:53.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:36:53.28$vck44/valo=3,564.99 2006.257.03:36:53.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.03:36:53.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.03:36:53.28#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:53.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:53.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:53.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:53.28#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:36:53.28#ibcon#first serial, iclass 23, count 0 2006.257.03:36:53.28#ibcon#enter sib2, iclass 23, count 0 2006.257.03:36:53.28#ibcon#flushed, iclass 23, count 0 2006.257.03:36:53.28#ibcon#about to write, iclass 23, count 0 2006.257.03:36:53.28#ibcon#wrote, iclass 23, count 0 2006.257.03:36:53.28#ibcon#about to read 3, iclass 23, count 0 2006.257.03:36:53.29#ibcon#read 3, iclass 23, count 0 2006.257.03:36:53.29#ibcon#about to read 4, iclass 23, count 0 2006.257.03:36:53.29#ibcon#read 4, iclass 23, count 0 2006.257.03:36:53.29#ibcon#about to read 5, iclass 23, count 0 2006.257.03:36:53.29#ibcon#read 5, iclass 23, count 0 2006.257.03:36:53.30#ibcon#about to read 6, iclass 23, count 0 2006.257.03:36:53.30#ibcon#read 6, iclass 23, count 0 2006.257.03:36:53.30#ibcon#end of sib2, iclass 23, count 0 2006.257.03:36:53.30#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:36:53.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:36:53.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:36:53.30#ibcon#*before write, iclass 23, count 0 2006.257.03:36:53.30#ibcon#enter sib2, iclass 23, count 0 2006.257.03:36:53.30#ibcon#flushed, iclass 23, count 0 2006.257.03:36:53.30#ibcon#about to write, iclass 23, count 0 2006.257.03:36:53.30#ibcon#wrote, iclass 23, count 0 2006.257.03:36:53.30#ibcon#about to read 3, iclass 23, count 0 2006.257.03:36:53.33#ibcon#read 3, iclass 23, count 0 2006.257.03:36:53.33#ibcon#about to read 4, iclass 23, count 0 2006.257.03:36:53.33#ibcon#read 4, iclass 23, count 0 2006.257.03:36:53.33#ibcon#about to read 5, iclass 23, count 0 2006.257.03:36:53.33#ibcon#read 5, iclass 23, count 0 2006.257.03:36:53.34#ibcon#about to read 6, iclass 23, count 0 2006.257.03:36:53.34#ibcon#read 6, iclass 23, count 0 2006.257.03:36:53.34#ibcon#end of sib2, iclass 23, count 0 2006.257.03:36:53.34#ibcon#*after write, iclass 23, count 0 2006.257.03:36:53.34#ibcon#*before return 0, iclass 23, count 0 2006.257.03:36:53.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:53.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:53.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:36:53.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:36:53.34$vck44/va=3,8 2006.257.03:36:53.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.03:36:53.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.03:36:53.34#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:53.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:53.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:53.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:53.39#ibcon#enter wrdev, iclass 25, count 2 2006.257.03:36:53.39#ibcon#first serial, iclass 25, count 2 2006.257.03:36:53.39#ibcon#enter sib2, iclass 25, count 2 2006.257.03:36:53.39#ibcon#flushed, iclass 25, count 2 2006.257.03:36:53.39#ibcon#about to write, iclass 25, count 2 2006.257.03:36:53.40#ibcon#wrote, iclass 25, count 2 2006.257.03:36:53.40#ibcon#about to read 3, iclass 25, count 2 2006.257.03:36:53.41#ibcon#read 3, iclass 25, count 2 2006.257.03:36:53.41#ibcon#about to read 4, iclass 25, count 2 2006.257.03:36:53.41#ibcon#read 4, iclass 25, count 2 2006.257.03:36:53.41#ibcon#about to read 5, iclass 25, count 2 2006.257.03:36:53.42#ibcon#read 5, iclass 25, count 2 2006.257.03:36:53.42#ibcon#about to read 6, iclass 25, count 2 2006.257.03:36:53.42#ibcon#read 6, iclass 25, count 2 2006.257.03:36:53.42#ibcon#end of sib2, iclass 25, count 2 2006.257.03:36:53.42#ibcon#*mode == 0, iclass 25, count 2 2006.257.03:36:53.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.03:36:53.42#ibcon#[25=AT03-08\r\n] 2006.257.03:36:53.42#ibcon#*before write, iclass 25, count 2 2006.257.03:36:53.42#ibcon#enter sib2, iclass 25, count 2 2006.257.03:36:53.42#ibcon#flushed, iclass 25, count 2 2006.257.03:36:53.42#ibcon#about to write, iclass 25, count 2 2006.257.03:36:53.42#ibcon#wrote, iclass 25, count 2 2006.257.03:36:53.42#ibcon#about to read 3, iclass 25, count 2 2006.257.03:36:53.44#ibcon#read 3, iclass 25, count 2 2006.257.03:36:53.44#ibcon#about to read 4, iclass 25, count 2 2006.257.03:36:53.44#ibcon#read 4, iclass 25, count 2 2006.257.03:36:53.44#ibcon#about to read 5, iclass 25, count 2 2006.257.03:36:53.44#ibcon#read 5, iclass 25, count 2 2006.257.03:36:53.45#ibcon#about to read 6, iclass 25, count 2 2006.257.03:36:53.45#ibcon#read 6, iclass 25, count 2 2006.257.03:36:53.45#ibcon#end of sib2, iclass 25, count 2 2006.257.03:36:53.45#ibcon#*after write, iclass 25, count 2 2006.257.03:36:53.45#ibcon#*before return 0, iclass 25, count 2 2006.257.03:36:53.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:53.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:53.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.03:36:53.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:53.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:53.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:53.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:53.56#ibcon#enter wrdev, iclass 25, count 0 2006.257.03:36:53.56#ibcon#first serial, iclass 25, count 0 2006.257.03:36:53.56#ibcon#enter sib2, iclass 25, count 0 2006.257.03:36:53.56#ibcon#flushed, iclass 25, count 0 2006.257.03:36:53.56#ibcon#about to write, iclass 25, count 0 2006.257.03:36:53.57#ibcon#wrote, iclass 25, count 0 2006.257.03:36:53.57#ibcon#about to read 3, iclass 25, count 0 2006.257.03:36:53.58#ibcon#read 3, iclass 25, count 0 2006.257.03:36:53.58#ibcon#about to read 4, iclass 25, count 0 2006.257.03:36:53.58#ibcon#read 4, iclass 25, count 0 2006.257.03:36:53.58#ibcon#about to read 5, iclass 25, count 0 2006.257.03:36:53.58#ibcon#read 5, iclass 25, count 0 2006.257.03:36:53.59#ibcon#about to read 6, iclass 25, count 0 2006.257.03:36:53.59#ibcon#read 6, iclass 25, count 0 2006.257.03:36:53.59#ibcon#end of sib2, iclass 25, count 0 2006.257.03:36:53.59#ibcon#*mode == 0, iclass 25, count 0 2006.257.03:36:53.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.03:36:53.59#ibcon#[25=USB\r\n] 2006.257.03:36:53.59#ibcon#*before write, iclass 25, count 0 2006.257.03:36:53.59#ibcon#enter sib2, iclass 25, count 0 2006.257.03:36:53.59#ibcon#flushed, iclass 25, count 0 2006.257.03:36:53.59#ibcon#about to write, iclass 25, count 0 2006.257.03:36:53.59#ibcon#wrote, iclass 25, count 0 2006.257.03:36:53.59#ibcon#about to read 3, iclass 25, count 0 2006.257.03:36:53.61#ibcon#read 3, iclass 25, count 0 2006.257.03:36:53.61#ibcon#about to read 4, iclass 25, count 0 2006.257.03:36:53.61#ibcon#read 4, iclass 25, count 0 2006.257.03:36:53.61#ibcon#about to read 5, iclass 25, count 0 2006.257.03:36:53.62#ibcon#read 5, iclass 25, count 0 2006.257.03:36:53.62#ibcon#about to read 6, iclass 25, count 0 2006.257.03:36:53.62#ibcon#read 6, iclass 25, count 0 2006.257.03:36:53.62#ibcon#end of sib2, iclass 25, count 0 2006.257.03:36:53.62#ibcon#*after write, iclass 25, count 0 2006.257.03:36:53.62#ibcon#*before return 0, iclass 25, count 0 2006.257.03:36:53.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:53.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:53.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.03:36:53.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.03:36:53.62$vck44/valo=4,624.99 2006.257.03:36:53.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.03:36:53.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.03:36:53.62#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:53.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:53.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:53.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:53.62#ibcon#enter wrdev, iclass 27, count 0 2006.257.03:36:53.62#ibcon#first serial, iclass 27, count 0 2006.257.03:36:53.62#ibcon#enter sib2, iclass 27, count 0 2006.257.03:36:53.62#ibcon#flushed, iclass 27, count 0 2006.257.03:36:53.62#ibcon#about to write, iclass 27, count 0 2006.257.03:36:53.62#ibcon#wrote, iclass 27, count 0 2006.257.03:36:53.62#ibcon#about to read 3, iclass 27, count 0 2006.257.03:36:53.63#ibcon#read 3, iclass 27, count 0 2006.257.03:36:53.63#ibcon#about to read 4, iclass 27, count 0 2006.257.03:36:53.63#ibcon#read 4, iclass 27, count 0 2006.257.03:36:53.63#ibcon#about to read 5, iclass 27, count 0 2006.257.03:36:53.63#ibcon#read 5, iclass 27, count 0 2006.257.03:36:53.64#ibcon#about to read 6, iclass 27, count 0 2006.257.03:36:53.64#ibcon#read 6, iclass 27, count 0 2006.257.03:36:53.64#ibcon#end of sib2, iclass 27, count 0 2006.257.03:36:53.64#ibcon#*mode == 0, iclass 27, count 0 2006.257.03:36:53.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.03:36:53.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:36:53.64#ibcon#*before write, iclass 27, count 0 2006.257.03:36:53.64#ibcon#enter sib2, iclass 27, count 0 2006.257.03:36:53.64#ibcon#flushed, iclass 27, count 0 2006.257.03:36:53.64#ibcon#about to write, iclass 27, count 0 2006.257.03:36:53.64#ibcon#wrote, iclass 27, count 0 2006.257.03:36:53.64#ibcon#about to read 3, iclass 27, count 0 2006.257.03:36:53.67#ibcon#read 3, iclass 27, count 0 2006.257.03:36:53.67#ibcon#about to read 4, iclass 27, count 0 2006.257.03:36:53.67#ibcon#read 4, iclass 27, count 0 2006.257.03:36:53.67#ibcon#about to read 5, iclass 27, count 0 2006.257.03:36:53.67#ibcon#read 5, iclass 27, count 0 2006.257.03:36:53.68#ibcon#about to read 6, iclass 27, count 0 2006.257.03:36:53.68#ibcon#read 6, iclass 27, count 0 2006.257.03:36:53.68#ibcon#end of sib2, iclass 27, count 0 2006.257.03:36:53.68#ibcon#*after write, iclass 27, count 0 2006.257.03:36:53.68#ibcon#*before return 0, iclass 27, count 0 2006.257.03:36:53.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:53.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:53.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.03:36:53.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.03:36:53.68$vck44/va=4,7 2006.257.03:36:53.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.03:36:53.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.03:36:53.68#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:53.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:53.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:53.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:53.73#ibcon#enter wrdev, iclass 29, count 2 2006.257.03:36:53.73#ibcon#first serial, iclass 29, count 2 2006.257.03:36:53.73#ibcon#enter sib2, iclass 29, count 2 2006.257.03:36:53.73#ibcon#flushed, iclass 29, count 2 2006.257.03:36:53.73#ibcon#about to write, iclass 29, count 2 2006.257.03:36:53.74#ibcon#wrote, iclass 29, count 2 2006.257.03:36:53.74#ibcon#about to read 3, iclass 29, count 2 2006.257.03:36:53.75#ibcon#read 3, iclass 29, count 2 2006.257.03:36:53.75#ibcon#about to read 4, iclass 29, count 2 2006.257.03:36:53.75#ibcon#read 4, iclass 29, count 2 2006.257.03:36:53.75#ibcon#about to read 5, iclass 29, count 2 2006.257.03:36:53.76#ibcon#read 5, iclass 29, count 2 2006.257.03:36:53.76#ibcon#about to read 6, iclass 29, count 2 2006.257.03:36:53.76#ibcon#read 6, iclass 29, count 2 2006.257.03:36:53.76#ibcon#end of sib2, iclass 29, count 2 2006.257.03:36:53.76#ibcon#*mode == 0, iclass 29, count 2 2006.257.03:36:53.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.03:36:53.76#ibcon#[25=AT04-07\r\n] 2006.257.03:36:53.76#ibcon#*before write, iclass 29, count 2 2006.257.03:36:53.76#ibcon#enter sib2, iclass 29, count 2 2006.257.03:36:53.76#ibcon#flushed, iclass 29, count 2 2006.257.03:36:53.76#ibcon#about to write, iclass 29, count 2 2006.257.03:36:53.76#ibcon#wrote, iclass 29, count 2 2006.257.03:36:53.76#ibcon#about to read 3, iclass 29, count 2 2006.257.03:36:53.78#ibcon#read 3, iclass 29, count 2 2006.257.03:36:53.78#ibcon#about to read 4, iclass 29, count 2 2006.257.03:36:53.78#ibcon#read 4, iclass 29, count 2 2006.257.03:36:53.78#ibcon#about to read 5, iclass 29, count 2 2006.257.03:36:53.78#ibcon#read 5, iclass 29, count 2 2006.257.03:36:53.79#ibcon#about to read 6, iclass 29, count 2 2006.257.03:36:53.79#ibcon#read 6, iclass 29, count 2 2006.257.03:36:53.79#ibcon#end of sib2, iclass 29, count 2 2006.257.03:36:53.79#ibcon#*after write, iclass 29, count 2 2006.257.03:36:53.79#ibcon#*before return 0, iclass 29, count 2 2006.257.03:36:53.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:53.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:53.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.03:36:53.79#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:53.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:53.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:53.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:53.90#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:36:53.90#ibcon#first serial, iclass 29, count 0 2006.257.03:36:53.90#ibcon#enter sib2, iclass 29, count 0 2006.257.03:36:53.90#ibcon#flushed, iclass 29, count 0 2006.257.03:36:53.90#ibcon#about to write, iclass 29, count 0 2006.257.03:36:53.91#ibcon#wrote, iclass 29, count 0 2006.257.03:36:53.91#ibcon#about to read 3, iclass 29, count 0 2006.257.03:36:53.92#ibcon#read 3, iclass 29, count 0 2006.257.03:36:53.92#ibcon#about to read 4, iclass 29, count 0 2006.257.03:36:53.92#ibcon#read 4, iclass 29, count 0 2006.257.03:36:53.92#ibcon#about to read 5, iclass 29, count 0 2006.257.03:36:53.92#ibcon#read 5, iclass 29, count 0 2006.257.03:36:53.93#ibcon#about to read 6, iclass 29, count 0 2006.257.03:36:53.93#ibcon#read 6, iclass 29, count 0 2006.257.03:36:53.93#ibcon#end of sib2, iclass 29, count 0 2006.257.03:36:53.93#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:36:53.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:36:53.93#ibcon#[25=USB\r\n] 2006.257.03:36:53.93#ibcon#*before write, iclass 29, count 0 2006.257.03:36:53.93#ibcon#enter sib2, iclass 29, count 0 2006.257.03:36:53.93#ibcon#flushed, iclass 29, count 0 2006.257.03:36:53.93#ibcon#about to write, iclass 29, count 0 2006.257.03:36:53.93#ibcon#wrote, iclass 29, count 0 2006.257.03:36:53.93#ibcon#about to read 3, iclass 29, count 0 2006.257.03:36:53.95#ibcon#read 3, iclass 29, count 0 2006.257.03:36:53.96#ibcon#about to read 4, iclass 29, count 0 2006.257.03:36:53.96#ibcon#read 4, iclass 29, count 0 2006.257.03:36:53.96#ibcon#about to read 5, iclass 29, count 0 2006.257.03:36:53.96#ibcon#read 5, iclass 29, count 0 2006.257.03:36:53.96#ibcon#about to read 6, iclass 29, count 0 2006.257.03:36:53.96#ibcon#read 6, iclass 29, count 0 2006.257.03:36:53.96#ibcon#end of sib2, iclass 29, count 0 2006.257.03:36:53.96#ibcon#*after write, iclass 29, count 0 2006.257.03:36:53.96#ibcon#*before return 0, iclass 29, count 0 2006.257.03:36:53.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:53.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:53.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:36:53.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:36:53.96$vck44/valo=5,734.99 2006.257.03:36:53.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.03:36:53.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.03:36:53.96#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:53.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:53.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:53.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:53.96#ibcon#enter wrdev, iclass 31, count 0 2006.257.03:36:53.96#ibcon#first serial, iclass 31, count 0 2006.257.03:36:53.96#ibcon#enter sib2, iclass 31, count 0 2006.257.03:36:53.96#ibcon#flushed, iclass 31, count 0 2006.257.03:36:53.96#ibcon#about to write, iclass 31, count 0 2006.257.03:36:53.96#ibcon#wrote, iclass 31, count 0 2006.257.03:36:53.96#ibcon#about to read 3, iclass 31, count 0 2006.257.03:36:53.97#ibcon#read 3, iclass 31, count 0 2006.257.03:36:53.97#ibcon#about to read 4, iclass 31, count 0 2006.257.03:36:53.97#ibcon#read 4, iclass 31, count 0 2006.257.03:36:53.97#ibcon#about to read 5, iclass 31, count 0 2006.257.03:36:53.98#ibcon#read 5, iclass 31, count 0 2006.257.03:36:53.98#ibcon#about to read 6, iclass 31, count 0 2006.257.03:36:53.98#ibcon#read 6, iclass 31, count 0 2006.257.03:36:53.98#ibcon#end of sib2, iclass 31, count 0 2006.257.03:36:53.98#ibcon#*mode == 0, iclass 31, count 0 2006.257.03:36:53.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.03:36:53.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:36:53.98#ibcon#*before write, iclass 31, count 0 2006.257.03:36:53.98#ibcon#enter sib2, iclass 31, count 0 2006.257.03:36:53.98#ibcon#flushed, iclass 31, count 0 2006.257.03:36:53.98#ibcon#about to write, iclass 31, count 0 2006.257.03:36:53.98#ibcon#wrote, iclass 31, count 0 2006.257.03:36:53.98#ibcon#about to read 3, iclass 31, count 0 2006.257.03:36:54.01#ibcon#read 3, iclass 31, count 0 2006.257.03:36:54.01#ibcon#about to read 4, iclass 31, count 0 2006.257.03:36:54.01#ibcon#read 4, iclass 31, count 0 2006.257.03:36:54.01#ibcon#about to read 5, iclass 31, count 0 2006.257.03:36:54.01#ibcon#read 5, iclass 31, count 0 2006.257.03:36:54.01#ibcon#about to read 6, iclass 31, count 0 2006.257.03:36:54.02#ibcon#read 6, iclass 31, count 0 2006.257.03:36:54.02#ibcon#end of sib2, iclass 31, count 0 2006.257.03:36:54.02#ibcon#*after write, iclass 31, count 0 2006.257.03:36:54.02#ibcon#*before return 0, iclass 31, count 0 2006.257.03:36:54.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:54.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:54.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.03:36:54.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.03:36:54.02$vck44/va=5,4 2006.257.03:36:54.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.03:36:54.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.03:36:54.02#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:54.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:54.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:54.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:54.07#ibcon#enter wrdev, iclass 33, count 2 2006.257.03:36:54.07#ibcon#first serial, iclass 33, count 2 2006.257.03:36:54.07#ibcon#enter sib2, iclass 33, count 2 2006.257.03:36:54.07#ibcon#flushed, iclass 33, count 2 2006.257.03:36:54.08#ibcon#about to write, iclass 33, count 2 2006.257.03:36:54.08#ibcon#wrote, iclass 33, count 2 2006.257.03:36:54.08#ibcon#about to read 3, iclass 33, count 2 2006.257.03:36:54.09#ibcon#read 3, iclass 33, count 2 2006.257.03:36:54.09#ibcon#about to read 4, iclass 33, count 2 2006.257.03:36:54.09#ibcon#read 4, iclass 33, count 2 2006.257.03:36:54.09#ibcon#about to read 5, iclass 33, count 2 2006.257.03:36:54.10#ibcon#read 5, iclass 33, count 2 2006.257.03:36:54.10#ibcon#about to read 6, iclass 33, count 2 2006.257.03:36:54.10#ibcon#read 6, iclass 33, count 2 2006.257.03:36:54.10#ibcon#end of sib2, iclass 33, count 2 2006.257.03:36:54.10#ibcon#*mode == 0, iclass 33, count 2 2006.257.03:36:54.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.03:36:54.10#ibcon#[25=AT05-04\r\n] 2006.257.03:36:54.10#ibcon#*before write, iclass 33, count 2 2006.257.03:36:54.10#ibcon#enter sib2, iclass 33, count 2 2006.257.03:36:54.10#ibcon#flushed, iclass 33, count 2 2006.257.03:36:54.10#ibcon#about to write, iclass 33, count 2 2006.257.03:36:54.10#ibcon#wrote, iclass 33, count 2 2006.257.03:36:54.10#ibcon#about to read 3, iclass 33, count 2 2006.257.03:36:54.12#ibcon#read 3, iclass 33, count 2 2006.257.03:36:54.12#ibcon#about to read 4, iclass 33, count 2 2006.257.03:36:54.12#ibcon#read 4, iclass 33, count 2 2006.257.03:36:54.12#ibcon#about to read 5, iclass 33, count 2 2006.257.03:36:54.12#ibcon#read 5, iclass 33, count 2 2006.257.03:36:54.13#ibcon#about to read 6, iclass 33, count 2 2006.257.03:36:54.13#ibcon#read 6, iclass 33, count 2 2006.257.03:36:54.13#ibcon#end of sib2, iclass 33, count 2 2006.257.03:36:54.13#ibcon#*after write, iclass 33, count 2 2006.257.03:36:54.13#ibcon#*before return 0, iclass 33, count 2 2006.257.03:36:54.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:54.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:54.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.03:36:54.13#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:54.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:54.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:54.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:54.24#ibcon#enter wrdev, iclass 33, count 0 2006.257.03:36:54.24#ibcon#first serial, iclass 33, count 0 2006.257.03:36:54.24#ibcon#enter sib2, iclass 33, count 0 2006.257.03:36:54.24#ibcon#flushed, iclass 33, count 0 2006.257.03:36:54.24#ibcon#about to write, iclass 33, count 0 2006.257.03:36:54.25#ibcon#wrote, iclass 33, count 0 2006.257.03:36:54.25#ibcon#about to read 3, iclass 33, count 0 2006.257.03:36:54.26#ibcon#read 3, iclass 33, count 0 2006.257.03:36:54.26#ibcon#about to read 4, iclass 33, count 0 2006.257.03:36:54.26#ibcon#read 4, iclass 33, count 0 2006.257.03:36:54.26#ibcon#about to read 5, iclass 33, count 0 2006.257.03:36:54.26#ibcon#read 5, iclass 33, count 0 2006.257.03:36:54.26#ibcon#about to read 6, iclass 33, count 0 2006.257.03:36:54.27#ibcon#read 6, iclass 33, count 0 2006.257.03:36:54.27#ibcon#end of sib2, iclass 33, count 0 2006.257.03:36:54.27#ibcon#*mode == 0, iclass 33, count 0 2006.257.03:36:54.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.03:36:54.27#ibcon#[25=USB\r\n] 2006.257.03:36:54.27#ibcon#*before write, iclass 33, count 0 2006.257.03:36:54.27#ibcon#enter sib2, iclass 33, count 0 2006.257.03:36:54.27#ibcon#flushed, iclass 33, count 0 2006.257.03:36:54.27#ibcon#about to write, iclass 33, count 0 2006.257.03:36:54.27#ibcon#wrote, iclass 33, count 0 2006.257.03:36:54.27#ibcon#about to read 3, iclass 33, count 0 2006.257.03:36:54.29#ibcon#read 3, iclass 33, count 0 2006.257.03:36:54.29#ibcon#about to read 4, iclass 33, count 0 2006.257.03:36:54.29#ibcon#read 4, iclass 33, count 0 2006.257.03:36:54.29#ibcon#about to read 5, iclass 33, count 0 2006.257.03:36:54.29#ibcon#read 5, iclass 33, count 0 2006.257.03:36:54.29#ibcon#about to read 6, iclass 33, count 0 2006.257.03:36:54.30#ibcon#read 6, iclass 33, count 0 2006.257.03:36:54.30#ibcon#end of sib2, iclass 33, count 0 2006.257.03:36:54.30#ibcon#*after write, iclass 33, count 0 2006.257.03:36:54.30#ibcon#*before return 0, iclass 33, count 0 2006.257.03:36:54.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:54.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:54.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.03:36:54.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.03:36:54.30$vck44/valo=6,814.99 2006.257.03:36:54.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.03:36:54.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.03:36:54.30#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:54.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:54.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:54.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:54.30#ibcon#enter wrdev, iclass 35, count 0 2006.257.03:36:54.30#ibcon#first serial, iclass 35, count 0 2006.257.03:36:54.30#ibcon#enter sib2, iclass 35, count 0 2006.257.03:36:54.30#ibcon#flushed, iclass 35, count 0 2006.257.03:36:54.30#ibcon#about to write, iclass 35, count 0 2006.257.03:36:54.30#ibcon#wrote, iclass 35, count 0 2006.257.03:36:54.30#ibcon#about to read 3, iclass 35, count 0 2006.257.03:36:54.31#ibcon#read 3, iclass 35, count 0 2006.257.03:36:54.31#ibcon#about to read 4, iclass 35, count 0 2006.257.03:36:54.31#ibcon#read 4, iclass 35, count 0 2006.257.03:36:54.31#ibcon#about to read 5, iclass 35, count 0 2006.257.03:36:54.32#ibcon#read 5, iclass 35, count 0 2006.257.03:36:54.32#ibcon#about to read 6, iclass 35, count 0 2006.257.03:36:54.32#ibcon#read 6, iclass 35, count 0 2006.257.03:36:54.32#ibcon#end of sib2, iclass 35, count 0 2006.257.03:36:54.32#ibcon#*mode == 0, iclass 35, count 0 2006.257.03:36:54.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.03:36:54.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:36:54.32#ibcon#*before write, iclass 35, count 0 2006.257.03:36:54.32#ibcon#enter sib2, iclass 35, count 0 2006.257.03:36:54.32#ibcon#flushed, iclass 35, count 0 2006.257.03:36:54.32#ibcon#about to write, iclass 35, count 0 2006.257.03:36:54.32#ibcon#wrote, iclass 35, count 0 2006.257.03:36:54.32#ibcon#about to read 3, iclass 35, count 0 2006.257.03:36:54.35#ibcon#read 3, iclass 35, count 0 2006.257.03:36:54.35#ibcon#about to read 4, iclass 35, count 0 2006.257.03:36:54.35#ibcon#read 4, iclass 35, count 0 2006.257.03:36:54.35#ibcon#about to read 5, iclass 35, count 0 2006.257.03:36:54.35#ibcon#read 5, iclass 35, count 0 2006.257.03:36:54.36#ibcon#about to read 6, iclass 35, count 0 2006.257.03:36:54.36#ibcon#read 6, iclass 35, count 0 2006.257.03:36:54.36#ibcon#end of sib2, iclass 35, count 0 2006.257.03:36:54.36#ibcon#*after write, iclass 35, count 0 2006.257.03:36:54.36#ibcon#*before return 0, iclass 35, count 0 2006.257.03:36:54.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:54.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:54.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.03:36:54.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.03:36:54.36$vck44/va=6,4 2006.257.03:36:54.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.03:36:54.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.03:36:54.36#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:54.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:54.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:54.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:54.42#ibcon#enter wrdev, iclass 37, count 2 2006.257.03:36:54.42#ibcon#first serial, iclass 37, count 2 2006.257.03:36:54.42#ibcon#enter sib2, iclass 37, count 2 2006.257.03:36:54.42#ibcon#flushed, iclass 37, count 2 2006.257.03:36:54.42#ibcon#about to write, iclass 37, count 2 2006.257.03:36:54.42#ibcon#wrote, iclass 37, count 2 2006.257.03:36:54.42#ibcon#about to read 3, iclass 37, count 2 2006.257.03:36:54.43#ibcon#read 3, iclass 37, count 2 2006.257.03:36:54.43#ibcon#about to read 4, iclass 37, count 2 2006.257.03:36:54.43#ibcon#read 4, iclass 37, count 2 2006.257.03:36:54.43#ibcon#about to read 5, iclass 37, count 2 2006.257.03:36:54.44#ibcon#read 5, iclass 37, count 2 2006.257.03:36:54.44#ibcon#about to read 6, iclass 37, count 2 2006.257.03:36:54.44#ibcon#read 6, iclass 37, count 2 2006.257.03:36:54.44#ibcon#end of sib2, iclass 37, count 2 2006.257.03:36:54.44#ibcon#*mode == 0, iclass 37, count 2 2006.257.03:36:54.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.03:36:54.44#ibcon#[25=AT06-04\r\n] 2006.257.03:36:54.44#ibcon#*before write, iclass 37, count 2 2006.257.03:36:54.44#ibcon#enter sib2, iclass 37, count 2 2006.257.03:36:54.44#ibcon#flushed, iclass 37, count 2 2006.257.03:36:54.44#ibcon#about to write, iclass 37, count 2 2006.257.03:36:54.44#ibcon#wrote, iclass 37, count 2 2006.257.03:36:54.44#ibcon#about to read 3, iclass 37, count 2 2006.257.03:36:54.46#ibcon#read 3, iclass 37, count 2 2006.257.03:36:54.46#ibcon#about to read 4, iclass 37, count 2 2006.257.03:36:54.46#ibcon#read 4, iclass 37, count 2 2006.257.03:36:54.46#ibcon#about to read 5, iclass 37, count 2 2006.257.03:36:54.47#ibcon#read 5, iclass 37, count 2 2006.257.03:36:54.47#ibcon#about to read 6, iclass 37, count 2 2006.257.03:36:54.47#ibcon#read 6, iclass 37, count 2 2006.257.03:36:54.47#ibcon#end of sib2, iclass 37, count 2 2006.257.03:36:54.47#ibcon#*after write, iclass 37, count 2 2006.257.03:36:54.47#ibcon#*before return 0, iclass 37, count 2 2006.257.03:36:54.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:54.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:54.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.03:36:54.47#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:54.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:54.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:54.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:54.58#ibcon#enter wrdev, iclass 37, count 0 2006.257.03:36:54.58#ibcon#first serial, iclass 37, count 0 2006.257.03:36:54.58#ibcon#enter sib2, iclass 37, count 0 2006.257.03:36:54.58#ibcon#flushed, iclass 37, count 0 2006.257.03:36:54.58#ibcon#about to write, iclass 37, count 0 2006.257.03:36:54.59#ibcon#wrote, iclass 37, count 0 2006.257.03:36:54.59#ibcon#about to read 3, iclass 37, count 0 2006.257.03:36:54.60#ibcon#read 3, iclass 37, count 0 2006.257.03:36:54.60#ibcon#about to read 4, iclass 37, count 0 2006.257.03:36:54.60#ibcon#read 4, iclass 37, count 0 2006.257.03:36:54.60#ibcon#about to read 5, iclass 37, count 0 2006.257.03:36:54.60#ibcon#read 5, iclass 37, count 0 2006.257.03:36:54.61#ibcon#about to read 6, iclass 37, count 0 2006.257.03:36:54.61#ibcon#read 6, iclass 37, count 0 2006.257.03:36:54.61#ibcon#end of sib2, iclass 37, count 0 2006.257.03:36:54.61#ibcon#*mode == 0, iclass 37, count 0 2006.257.03:36:54.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.03:36:54.61#ibcon#[25=USB\r\n] 2006.257.03:36:54.61#ibcon#*before write, iclass 37, count 0 2006.257.03:36:54.61#ibcon#enter sib2, iclass 37, count 0 2006.257.03:36:54.61#ibcon#flushed, iclass 37, count 0 2006.257.03:36:54.61#ibcon#about to write, iclass 37, count 0 2006.257.03:36:54.61#ibcon#wrote, iclass 37, count 0 2006.257.03:36:54.61#ibcon#about to read 3, iclass 37, count 0 2006.257.03:36:54.63#ibcon#read 3, iclass 37, count 0 2006.257.03:36:54.63#ibcon#about to read 4, iclass 37, count 0 2006.257.03:36:54.63#ibcon#read 4, iclass 37, count 0 2006.257.03:36:54.63#ibcon#about to read 5, iclass 37, count 0 2006.257.03:36:54.63#ibcon#read 5, iclass 37, count 0 2006.257.03:36:54.64#ibcon#about to read 6, iclass 37, count 0 2006.257.03:36:54.64#ibcon#read 6, iclass 37, count 0 2006.257.03:36:54.64#ibcon#end of sib2, iclass 37, count 0 2006.257.03:36:54.64#ibcon#*after write, iclass 37, count 0 2006.257.03:36:54.64#ibcon#*before return 0, iclass 37, count 0 2006.257.03:36:54.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:54.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:54.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.03:36:54.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.03:36:54.64$vck44/valo=7,864.99 2006.257.03:36:54.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.03:36:54.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.03:36:54.64#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:54.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:54.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:54.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:54.64#ibcon#enter wrdev, iclass 39, count 0 2006.257.03:36:54.64#ibcon#first serial, iclass 39, count 0 2006.257.03:36:54.64#ibcon#enter sib2, iclass 39, count 0 2006.257.03:36:54.64#ibcon#flushed, iclass 39, count 0 2006.257.03:36:54.64#ibcon#about to write, iclass 39, count 0 2006.257.03:36:54.64#ibcon#wrote, iclass 39, count 0 2006.257.03:36:54.64#ibcon#about to read 3, iclass 39, count 0 2006.257.03:36:54.65#ibcon#read 3, iclass 39, count 0 2006.257.03:36:54.65#ibcon#about to read 4, iclass 39, count 0 2006.257.03:36:54.65#ibcon#read 4, iclass 39, count 0 2006.257.03:36:54.65#ibcon#about to read 5, iclass 39, count 0 2006.257.03:36:54.65#ibcon#read 5, iclass 39, count 0 2006.257.03:36:54.66#ibcon#about to read 6, iclass 39, count 0 2006.257.03:36:54.66#ibcon#read 6, iclass 39, count 0 2006.257.03:36:54.66#ibcon#end of sib2, iclass 39, count 0 2006.257.03:36:54.66#ibcon#*mode == 0, iclass 39, count 0 2006.257.03:36:54.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.03:36:54.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:36:54.66#ibcon#*before write, iclass 39, count 0 2006.257.03:36:54.66#ibcon#enter sib2, iclass 39, count 0 2006.257.03:36:54.66#ibcon#flushed, iclass 39, count 0 2006.257.03:36:54.66#ibcon#about to write, iclass 39, count 0 2006.257.03:36:54.66#ibcon#wrote, iclass 39, count 0 2006.257.03:36:54.66#ibcon#about to read 3, iclass 39, count 0 2006.257.03:36:54.69#ibcon#read 3, iclass 39, count 0 2006.257.03:36:54.69#ibcon#about to read 4, iclass 39, count 0 2006.257.03:36:54.69#ibcon#read 4, iclass 39, count 0 2006.257.03:36:54.69#ibcon#about to read 5, iclass 39, count 0 2006.257.03:36:54.69#ibcon#read 5, iclass 39, count 0 2006.257.03:36:54.69#ibcon#about to read 6, iclass 39, count 0 2006.257.03:36:54.70#ibcon#read 6, iclass 39, count 0 2006.257.03:36:54.70#ibcon#end of sib2, iclass 39, count 0 2006.257.03:36:54.70#ibcon#*after write, iclass 39, count 0 2006.257.03:36:54.70#ibcon#*before return 0, iclass 39, count 0 2006.257.03:36:54.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:54.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:54.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.03:36:54.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.03:36:54.70$vck44/va=7,4 2006.257.03:36:54.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.03:36:54.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.03:36:54.70#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:54.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:54.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:54.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:54.75#ibcon#enter wrdev, iclass 3, count 2 2006.257.03:36:54.75#ibcon#first serial, iclass 3, count 2 2006.257.03:36:54.75#ibcon#enter sib2, iclass 3, count 2 2006.257.03:36:54.75#ibcon#flushed, iclass 3, count 2 2006.257.03:36:54.75#ibcon#about to write, iclass 3, count 2 2006.257.03:36:54.76#ibcon#wrote, iclass 3, count 2 2006.257.03:36:54.76#ibcon#about to read 3, iclass 3, count 2 2006.257.03:36:54.77#ibcon#read 3, iclass 3, count 2 2006.257.03:36:54.77#ibcon#about to read 4, iclass 3, count 2 2006.257.03:36:54.77#ibcon#read 4, iclass 3, count 2 2006.257.03:36:54.77#ibcon#about to read 5, iclass 3, count 2 2006.257.03:36:54.77#ibcon#read 5, iclass 3, count 2 2006.257.03:36:54.78#ibcon#about to read 6, iclass 3, count 2 2006.257.03:36:54.78#ibcon#read 6, iclass 3, count 2 2006.257.03:36:54.78#ibcon#end of sib2, iclass 3, count 2 2006.257.03:36:54.78#ibcon#*mode == 0, iclass 3, count 2 2006.257.03:36:54.78#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.03:36:54.78#ibcon#[25=AT07-04\r\n] 2006.257.03:36:54.78#ibcon#*before write, iclass 3, count 2 2006.257.03:36:54.78#ibcon#enter sib2, iclass 3, count 2 2006.257.03:36:54.78#ibcon#flushed, iclass 3, count 2 2006.257.03:36:54.78#ibcon#about to write, iclass 3, count 2 2006.257.03:36:54.78#ibcon#wrote, iclass 3, count 2 2006.257.03:36:54.78#ibcon#about to read 3, iclass 3, count 2 2006.257.03:36:54.80#ibcon#read 3, iclass 3, count 2 2006.257.03:36:54.80#ibcon#about to read 4, iclass 3, count 2 2006.257.03:36:54.80#ibcon#read 4, iclass 3, count 2 2006.257.03:36:54.80#ibcon#about to read 5, iclass 3, count 2 2006.257.03:36:54.80#ibcon#read 5, iclass 3, count 2 2006.257.03:36:54.80#ibcon#about to read 6, iclass 3, count 2 2006.257.03:36:54.81#ibcon#read 6, iclass 3, count 2 2006.257.03:36:54.81#ibcon#end of sib2, iclass 3, count 2 2006.257.03:36:54.81#ibcon#*after write, iclass 3, count 2 2006.257.03:36:54.81#ibcon#*before return 0, iclass 3, count 2 2006.257.03:36:54.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:54.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:54.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.03:36:54.81#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:54.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:54.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:54.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:54.92#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:36:54.92#ibcon#first serial, iclass 3, count 0 2006.257.03:36:54.92#ibcon#enter sib2, iclass 3, count 0 2006.257.03:36:54.92#ibcon#flushed, iclass 3, count 0 2006.257.03:36:54.92#ibcon#about to write, iclass 3, count 0 2006.257.03:36:54.93#ibcon#wrote, iclass 3, count 0 2006.257.03:36:54.93#ibcon#about to read 3, iclass 3, count 0 2006.257.03:36:54.94#ibcon#read 3, iclass 3, count 0 2006.257.03:36:54.94#ibcon#about to read 4, iclass 3, count 0 2006.257.03:36:54.94#ibcon#read 4, iclass 3, count 0 2006.257.03:36:54.94#ibcon#about to read 5, iclass 3, count 0 2006.257.03:36:54.94#ibcon#read 5, iclass 3, count 0 2006.257.03:36:54.94#ibcon#about to read 6, iclass 3, count 0 2006.257.03:36:54.95#ibcon#read 6, iclass 3, count 0 2006.257.03:36:54.95#ibcon#end of sib2, iclass 3, count 0 2006.257.03:36:54.95#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:36:54.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:36:54.95#ibcon#[25=USB\r\n] 2006.257.03:36:54.95#ibcon#*before write, iclass 3, count 0 2006.257.03:36:54.95#ibcon#enter sib2, iclass 3, count 0 2006.257.03:36:54.95#ibcon#flushed, iclass 3, count 0 2006.257.03:36:54.95#ibcon#about to write, iclass 3, count 0 2006.257.03:36:54.95#ibcon#wrote, iclass 3, count 0 2006.257.03:36:54.95#ibcon#about to read 3, iclass 3, count 0 2006.257.03:36:54.97#ibcon#read 3, iclass 3, count 0 2006.257.03:36:54.97#ibcon#about to read 4, iclass 3, count 0 2006.257.03:36:54.97#ibcon#read 4, iclass 3, count 0 2006.257.03:36:54.97#ibcon#about to read 5, iclass 3, count 0 2006.257.03:36:54.97#ibcon#read 5, iclass 3, count 0 2006.257.03:36:54.97#ibcon#about to read 6, iclass 3, count 0 2006.257.03:36:54.98#ibcon#read 6, iclass 3, count 0 2006.257.03:36:54.98#ibcon#end of sib2, iclass 3, count 0 2006.257.03:36:54.98#ibcon#*after write, iclass 3, count 0 2006.257.03:36:54.98#ibcon#*before return 0, iclass 3, count 0 2006.257.03:36:54.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:54.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:54.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:36:54.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:36:54.98$vck44/valo=8,884.99 2006.257.03:36:54.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.03:36:54.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.03:36:54.98#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:54.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:54.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:54.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:54.98#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:36:54.98#ibcon#first serial, iclass 5, count 0 2006.257.03:36:54.98#ibcon#enter sib2, iclass 5, count 0 2006.257.03:36:54.98#ibcon#flushed, iclass 5, count 0 2006.257.03:36:54.98#ibcon#about to write, iclass 5, count 0 2006.257.03:36:54.98#ibcon#wrote, iclass 5, count 0 2006.257.03:36:54.98#ibcon#about to read 3, iclass 5, count 0 2006.257.03:36:54.99#ibcon#read 3, iclass 5, count 0 2006.257.03:36:54.99#ibcon#about to read 4, iclass 5, count 0 2006.257.03:36:54.99#ibcon#read 4, iclass 5, count 0 2006.257.03:36:54.99#ibcon#about to read 5, iclass 5, count 0 2006.257.03:36:55.00#ibcon#read 5, iclass 5, count 0 2006.257.03:36:55.00#ibcon#about to read 6, iclass 5, count 0 2006.257.03:36:55.00#ibcon#read 6, iclass 5, count 0 2006.257.03:36:55.00#ibcon#end of sib2, iclass 5, count 0 2006.257.03:36:55.00#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:36:55.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:36:55.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:36:55.00#ibcon#*before write, iclass 5, count 0 2006.257.03:36:55.00#ibcon#enter sib2, iclass 5, count 0 2006.257.03:36:55.00#ibcon#flushed, iclass 5, count 0 2006.257.03:36:55.00#ibcon#about to write, iclass 5, count 0 2006.257.03:36:55.00#ibcon#wrote, iclass 5, count 0 2006.257.03:36:55.00#ibcon#about to read 3, iclass 5, count 0 2006.257.03:36:55.03#ibcon#read 3, iclass 5, count 0 2006.257.03:36:55.03#ibcon#about to read 4, iclass 5, count 0 2006.257.03:36:55.03#ibcon#read 4, iclass 5, count 0 2006.257.03:36:55.03#ibcon#about to read 5, iclass 5, count 0 2006.257.03:36:55.03#ibcon#read 5, iclass 5, count 0 2006.257.03:36:55.03#ibcon#about to read 6, iclass 5, count 0 2006.257.03:36:55.04#ibcon#read 6, iclass 5, count 0 2006.257.03:36:55.04#ibcon#end of sib2, iclass 5, count 0 2006.257.03:36:55.04#ibcon#*after write, iclass 5, count 0 2006.257.03:36:55.04#ibcon#*before return 0, iclass 5, count 0 2006.257.03:36:55.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:55.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:55.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:36:55.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:36:55.04$vck44/va=8,4 2006.257.03:36:55.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.03:36:55.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.03:36:55.04#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:55.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:36:55.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:36:55.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:36:55.09#ibcon#enter wrdev, iclass 7, count 2 2006.257.03:36:55.09#ibcon#first serial, iclass 7, count 2 2006.257.03:36:55.09#ibcon#enter sib2, iclass 7, count 2 2006.257.03:36:55.09#ibcon#flushed, iclass 7, count 2 2006.257.03:36:55.09#ibcon#about to write, iclass 7, count 2 2006.257.03:36:55.10#ibcon#wrote, iclass 7, count 2 2006.257.03:36:55.10#ibcon#about to read 3, iclass 7, count 2 2006.257.03:36:55.11#ibcon#read 3, iclass 7, count 2 2006.257.03:36:55.11#ibcon#about to read 4, iclass 7, count 2 2006.257.03:36:55.11#ibcon#read 4, iclass 7, count 2 2006.257.03:36:55.11#ibcon#about to read 5, iclass 7, count 2 2006.257.03:36:55.11#ibcon#read 5, iclass 7, count 2 2006.257.03:36:55.11#ibcon#about to read 6, iclass 7, count 2 2006.257.03:36:55.12#ibcon#read 6, iclass 7, count 2 2006.257.03:36:55.12#ibcon#end of sib2, iclass 7, count 2 2006.257.03:36:55.12#ibcon#*mode == 0, iclass 7, count 2 2006.257.03:36:55.12#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.03:36:55.12#ibcon#[25=AT08-04\r\n] 2006.257.03:36:55.12#ibcon#*before write, iclass 7, count 2 2006.257.03:36:55.12#ibcon#enter sib2, iclass 7, count 2 2006.257.03:36:55.12#ibcon#flushed, iclass 7, count 2 2006.257.03:36:55.12#ibcon#about to write, iclass 7, count 2 2006.257.03:36:55.12#ibcon#wrote, iclass 7, count 2 2006.257.03:36:55.12#ibcon#about to read 3, iclass 7, count 2 2006.257.03:36:55.14#ibcon#read 3, iclass 7, count 2 2006.257.03:36:55.14#ibcon#about to read 4, iclass 7, count 2 2006.257.03:36:55.14#ibcon#read 4, iclass 7, count 2 2006.257.03:36:55.14#ibcon#about to read 5, iclass 7, count 2 2006.257.03:36:55.14#ibcon#read 5, iclass 7, count 2 2006.257.03:36:55.14#ibcon#about to read 6, iclass 7, count 2 2006.257.03:36:55.15#ibcon#read 6, iclass 7, count 2 2006.257.03:36:55.15#ibcon#end of sib2, iclass 7, count 2 2006.257.03:36:55.15#ibcon#*after write, iclass 7, count 2 2006.257.03:36:55.15#ibcon#*before return 0, iclass 7, count 2 2006.257.03:36:55.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:36:55.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:36:55.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.03:36:55.15#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:55.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:36:55.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:36:55.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:36:55.26#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:36:55.26#ibcon#first serial, iclass 7, count 0 2006.257.03:36:55.26#ibcon#enter sib2, iclass 7, count 0 2006.257.03:36:55.26#ibcon#flushed, iclass 7, count 0 2006.257.03:36:55.26#ibcon#about to write, iclass 7, count 0 2006.257.03:36:55.27#ibcon#wrote, iclass 7, count 0 2006.257.03:36:55.27#ibcon#about to read 3, iclass 7, count 0 2006.257.03:36:55.28#ibcon#read 3, iclass 7, count 0 2006.257.03:36:55.28#ibcon#about to read 4, iclass 7, count 0 2006.257.03:36:55.28#ibcon#read 4, iclass 7, count 0 2006.257.03:36:55.28#ibcon#about to read 5, iclass 7, count 0 2006.257.03:36:55.28#ibcon#read 5, iclass 7, count 0 2006.257.03:36:55.28#ibcon#about to read 6, iclass 7, count 0 2006.257.03:36:55.29#ibcon#read 6, iclass 7, count 0 2006.257.03:36:55.29#ibcon#end of sib2, iclass 7, count 0 2006.257.03:36:55.29#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:36:55.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:36:55.29#ibcon#[25=USB\r\n] 2006.257.03:36:55.29#ibcon#*before write, iclass 7, count 0 2006.257.03:36:55.29#ibcon#enter sib2, iclass 7, count 0 2006.257.03:36:55.29#ibcon#flushed, iclass 7, count 0 2006.257.03:36:55.29#ibcon#about to write, iclass 7, count 0 2006.257.03:36:55.29#ibcon#wrote, iclass 7, count 0 2006.257.03:36:55.29#ibcon#about to read 3, iclass 7, count 0 2006.257.03:36:55.31#ibcon#read 3, iclass 7, count 0 2006.257.03:36:55.31#ibcon#about to read 4, iclass 7, count 0 2006.257.03:36:55.31#ibcon#read 4, iclass 7, count 0 2006.257.03:36:55.31#ibcon#about to read 5, iclass 7, count 0 2006.257.03:36:55.32#ibcon#read 5, iclass 7, count 0 2006.257.03:36:55.32#ibcon#about to read 6, iclass 7, count 0 2006.257.03:36:55.32#ibcon#read 6, iclass 7, count 0 2006.257.03:36:55.32#ibcon#end of sib2, iclass 7, count 0 2006.257.03:36:55.32#ibcon#*after write, iclass 7, count 0 2006.257.03:36:55.32#ibcon#*before return 0, iclass 7, count 0 2006.257.03:36:55.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:36:55.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:36:55.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:36:55.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:36:55.32$vck44/vblo=1,629.99 2006.257.03:36:55.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.03:36:55.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.03:36:55.32#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:55.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:36:55.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:36:55.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:36:55.32#ibcon#enter wrdev, iclass 11, count 0 2006.257.03:36:55.32#ibcon#first serial, iclass 11, count 0 2006.257.03:36:55.32#ibcon#enter sib2, iclass 11, count 0 2006.257.03:36:55.32#ibcon#flushed, iclass 11, count 0 2006.257.03:36:55.32#ibcon#about to write, iclass 11, count 0 2006.257.03:36:55.32#ibcon#wrote, iclass 11, count 0 2006.257.03:36:55.32#ibcon#about to read 3, iclass 11, count 0 2006.257.03:36:55.33#ibcon#read 3, iclass 11, count 0 2006.257.03:36:55.33#ibcon#about to read 4, iclass 11, count 0 2006.257.03:36:55.33#ibcon#read 4, iclass 11, count 0 2006.257.03:36:55.33#ibcon#about to read 5, iclass 11, count 0 2006.257.03:36:55.33#ibcon#read 5, iclass 11, count 0 2006.257.03:36:55.34#ibcon#about to read 6, iclass 11, count 0 2006.257.03:36:55.34#ibcon#read 6, iclass 11, count 0 2006.257.03:36:55.34#ibcon#end of sib2, iclass 11, count 0 2006.257.03:36:55.34#ibcon#*mode == 0, iclass 11, count 0 2006.257.03:36:55.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.03:36:55.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:36:55.34#ibcon#*before write, iclass 11, count 0 2006.257.03:36:55.34#ibcon#enter sib2, iclass 11, count 0 2006.257.03:36:55.34#ibcon#flushed, iclass 11, count 0 2006.257.03:36:55.34#ibcon#about to write, iclass 11, count 0 2006.257.03:36:55.34#ibcon#wrote, iclass 11, count 0 2006.257.03:36:55.34#ibcon#about to read 3, iclass 11, count 0 2006.257.03:36:55.37#ibcon#read 3, iclass 11, count 0 2006.257.03:36:55.37#ibcon#about to read 4, iclass 11, count 0 2006.257.03:36:55.37#ibcon#read 4, iclass 11, count 0 2006.257.03:36:55.37#ibcon#about to read 5, iclass 11, count 0 2006.257.03:36:55.37#ibcon#read 5, iclass 11, count 0 2006.257.03:36:55.37#ibcon#about to read 6, iclass 11, count 0 2006.257.03:36:55.38#ibcon#read 6, iclass 11, count 0 2006.257.03:36:55.38#ibcon#end of sib2, iclass 11, count 0 2006.257.03:36:55.38#ibcon#*after write, iclass 11, count 0 2006.257.03:36:55.38#ibcon#*before return 0, iclass 11, count 0 2006.257.03:36:55.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:36:55.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:36:55.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.03:36:55.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.03:36:55.38$vck44/vb=1,4 2006.257.03:36:55.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.03:36:55.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.03:36:55.38#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:55.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:36:55.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:36:55.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:36:55.38#ibcon#enter wrdev, iclass 13, count 2 2006.257.03:36:55.38#ibcon#first serial, iclass 13, count 2 2006.257.03:36:55.38#ibcon#enter sib2, iclass 13, count 2 2006.257.03:36:55.38#ibcon#flushed, iclass 13, count 2 2006.257.03:36:55.38#ibcon#about to write, iclass 13, count 2 2006.257.03:36:55.38#ibcon#wrote, iclass 13, count 2 2006.257.03:36:55.38#ibcon#about to read 3, iclass 13, count 2 2006.257.03:36:55.39#ibcon#read 3, iclass 13, count 2 2006.257.03:36:55.39#ibcon#about to read 4, iclass 13, count 2 2006.257.03:36:55.39#ibcon#read 4, iclass 13, count 2 2006.257.03:36:55.39#ibcon#about to read 5, iclass 13, count 2 2006.257.03:36:55.39#ibcon#read 5, iclass 13, count 2 2006.257.03:36:55.40#ibcon#about to read 6, iclass 13, count 2 2006.257.03:36:55.40#ibcon#read 6, iclass 13, count 2 2006.257.03:36:55.40#ibcon#end of sib2, iclass 13, count 2 2006.257.03:36:55.40#ibcon#*mode == 0, iclass 13, count 2 2006.257.03:36:55.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.03:36:55.40#ibcon#[27=AT01-04\r\n] 2006.257.03:36:55.40#ibcon#*before write, iclass 13, count 2 2006.257.03:36:55.40#ibcon#enter sib2, iclass 13, count 2 2006.257.03:36:55.40#ibcon#flushed, iclass 13, count 2 2006.257.03:36:55.40#ibcon#about to write, iclass 13, count 2 2006.257.03:36:55.40#ibcon#wrote, iclass 13, count 2 2006.257.03:36:55.40#ibcon#about to read 3, iclass 13, count 2 2006.257.03:36:55.42#ibcon#read 3, iclass 13, count 2 2006.257.03:36:55.42#ibcon#about to read 4, iclass 13, count 2 2006.257.03:36:55.42#ibcon#read 4, iclass 13, count 2 2006.257.03:36:55.42#ibcon#about to read 5, iclass 13, count 2 2006.257.03:36:55.42#ibcon#read 5, iclass 13, count 2 2006.257.03:36:55.42#ibcon#about to read 6, iclass 13, count 2 2006.257.03:36:55.43#ibcon#read 6, iclass 13, count 2 2006.257.03:36:55.43#ibcon#end of sib2, iclass 13, count 2 2006.257.03:36:55.43#ibcon#*after write, iclass 13, count 2 2006.257.03:36:55.43#ibcon#*before return 0, iclass 13, count 2 2006.257.03:36:55.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:36:55.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:36:55.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.03:36:55.43#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:55.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:36:55.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:36:55.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:36:55.54#ibcon#enter wrdev, iclass 13, count 0 2006.257.03:36:55.54#ibcon#first serial, iclass 13, count 0 2006.257.03:36:55.54#ibcon#enter sib2, iclass 13, count 0 2006.257.03:36:55.54#ibcon#flushed, iclass 13, count 0 2006.257.03:36:55.54#ibcon#about to write, iclass 13, count 0 2006.257.03:36:55.55#ibcon#wrote, iclass 13, count 0 2006.257.03:36:55.55#ibcon#about to read 3, iclass 13, count 0 2006.257.03:36:55.56#ibcon#read 3, iclass 13, count 0 2006.257.03:36:55.56#ibcon#about to read 4, iclass 13, count 0 2006.257.03:36:55.56#ibcon#read 4, iclass 13, count 0 2006.257.03:36:55.56#ibcon#about to read 5, iclass 13, count 0 2006.257.03:36:55.56#ibcon#read 5, iclass 13, count 0 2006.257.03:36:55.57#ibcon#about to read 6, iclass 13, count 0 2006.257.03:36:55.57#ibcon#read 6, iclass 13, count 0 2006.257.03:36:55.57#ibcon#end of sib2, iclass 13, count 0 2006.257.03:36:55.57#ibcon#*mode == 0, iclass 13, count 0 2006.257.03:36:55.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.03:36:55.57#ibcon#[27=USB\r\n] 2006.257.03:36:55.57#ibcon#*before write, iclass 13, count 0 2006.257.03:36:55.57#ibcon#enter sib2, iclass 13, count 0 2006.257.03:36:55.57#ibcon#flushed, iclass 13, count 0 2006.257.03:36:55.57#ibcon#about to write, iclass 13, count 0 2006.257.03:36:55.57#ibcon#wrote, iclass 13, count 0 2006.257.03:36:55.57#ibcon#about to read 3, iclass 13, count 0 2006.257.03:36:55.59#ibcon#read 3, iclass 13, count 0 2006.257.03:36:55.59#ibcon#about to read 4, iclass 13, count 0 2006.257.03:36:55.59#ibcon#read 4, iclass 13, count 0 2006.257.03:36:55.59#ibcon#about to read 5, iclass 13, count 0 2006.257.03:36:55.59#ibcon#read 5, iclass 13, count 0 2006.257.03:36:55.59#ibcon#about to read 6, iclass 13, count 0 2006.257.03:36:55.60#ibcon#read 6, iclass 13, count 0 2006.257.03:36:55.60#ibcon#end of sib2, iclass 13, count 0 2006.257.03:36:55.60#ibcon#*after write, iclass 13, count 0 2006.257.03:36:55.60#ibcon#*before return 0, iclass 13, count 0 2006.257.03:36:55.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:36:55.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:36:55.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.03:36:55.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.03:36:55.60$vck44/vblo=2,634.99 2006.257.03:36:55.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.03:36:55.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.03:36:55.60#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:55.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:55.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:55.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:55.60#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:36:55.60#ibcon#first serial, iclass 15, count 0 2006.257.03:36:55.60#ibcon#enter sib2, iclass 15, count 0 2006.257.03:36:55.60#ibcon#flushed, iclass 15, count 0 2006.257.03:36:55.60#ibcon#about to write, iclass 15, count 0 2006.257.03:36:55.60#ibcon#wrote, iclass 15, count 0 2006.257.03:36:55.60#ibcon#about to read 3, iclass 15, count 0 2006.257.03:36:55.61#ibcon#read 3, iclass 15, count 0 2006.257.03:36:55.61#ibcon#about to read 4, iclass 15, count 0 2006.257.03:36:55.61#ibcon#read 4, iclass 15, count 0 2006.257.03:36:55.61#ibcon#about to read 5, iclass 15, count 0 2006.257.03:36:55.61#ibcon#read 5, iclass 15, count 0 2006.257.03:36:55.62#ibcon#about to read 6, iclass 15, count 0 2006.257.03:36:55.62#ibcon#read 6, iclass 15, count 0 2006.257.03:36:55.62#ibcon#end of sib2, iclass 15, count 0 2006.257.03:36:55.62#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:36:55.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:36:55.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:36:55.62#ibcon#*before write, iclass 15, count 0 2006.257.03:36:55.62#ibcon#enter sib2, iclass 15, count 0 2006.257.03:36:55.62#ibcon#flushed, iclass 15, count 0 2006.257.03:36:55.62#ibcon#about to write, iclass 15, count 0 2006.257.03:36:55.62#ibcon#wrote, iclass 15, count 0 2006.257.03:36:55.62#ibcon#about to read 3, iclass 15, count 0 2006.257.03:36:55.65#ibcon#read 3, iclass 15, count 0 2006.257.03:36:55.65#ibcon#about to read 4, iclass 15, count 0 2006.257.03:36:55.65#ibcon#read 4, iclass 15, count 0 2006.257.03:36:55.65#ibcon#about to read 5, iclass 15, count 0 2006.257.03:36:55.65#ibcon#read 5, iclass 15, count 0 2006.257.03:36:55.65#ibcon#about to read 6, iclass 15, count 0 2006.257.03:36:55.66#ibcon#read 6, iclass 15, count 0 2006.257.03:36:55.66#ibcon#end of sib2, iclass 15, count 0 2006.257.03:36:55.66#ibcon#*after write, iclass 15, count 0 2006.257.03:36:55.66#ibcon#*before return 0, iclass 15, count 0 2006.257.03:36:55.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:55.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:36:55.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:36:55.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:36:55.66$vck44/vb=2,5 2006.257.03:36:55.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.03:36:55.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.03:36:55.66#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:55.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:55.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:55.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:55.71#ibcon#enter wrdev, iclass 17, count 2 2006.257.03:36:55.71#ibcon#first serial, iclass 17, count 2 2006.257.03:36:55.71#ibcon#enter sib2, iclass 17, count 2 2006.257.03:36:55.71#ibcon#flushed, iclass 17, count 2 2006.257.03:36:55.71#ibcon#about to write, iclass 17, count 2 2006.257.03:36:55.72#ibcon#wrote, iclass 17, count 2 2006.257.03:36:55.72#ibcon#about to read 3, iclass 17, count 2 2006.257.03:36:55.73#ibcon#read 3, iclass 17, count 2 2006.257.03:36:55.73#ibcon#about to read 4, iclass 17, count 2 2006.257.03:36:55.73#ibcon#read 4, iclass 17, count 2 2006.257.03:36:55.73#ibcon#about to read 5, iclass 17, count 2 2006.257.03:36:55.73#ibcon#read 5, iclass 17, count 2 2006.257.03:36:55.73#ibcon#about to read 6, iclass 17, count 2 2006.257.03:36:55.74#ibcon#read 6, iclass 17, count 2 2006.257.03:36:55.74#ibcon#end of sib2, iclass 17, count 2 2006.257.03:36:55.74#ibcon#*mode == 0, iclass 17, count 2 2006.257.03:36:55.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.03:36:55.74#ibcon#[27=AT02-05\r\n] 2006.257.03:36:55.74#ibcon#*before write, iclass 17, count 2 2006.257.03:36:55.74#ibcon#enter sib2, iclass 17, count 2 2006.257.03:36:55.74#ibcon#flushed, iclass 17, count 2 2006.257.03:36:55.74#ibcon#about to write, iclass 17, count 2 2006.257.03:36:55.74#ibcon#wrote, iclass 17, count 2 2006.257.03:36:55.74#ibcon#about to read 3, iclass 17, count 2 2006.257.03:36:55.76#ibcon#read 3, iclass 17, count 2 2006.257.03:36:55.76#ibcon#about to read 4, iclass 17, count 2 2006.257.03:36:55.76#ibcon#read 4, iclass 17, count 2 2006.257.03:36:55.76#ibcon#about to read 5, iclass 17, count 2 2006.257.03:36:55.76#ibcon#read 5, iclass 17, count 2 2006.257.03:36:55.76#ibcon#about to read 6, iclass 17, count 2 2006.257.03:36:55.77#ibcon#read 6, iclass 17, count 2 2006.257.03:36:55.77#ibcon#end of sib2, iclass 17, count 2 2006.257.03:36:55.77#ibcon#*after write, iclass 17, count 2 2006.257.03:36:55.77#ibcon#*before return 0, iclass 17, count 2 2006.257.03:36:55.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:55.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:36:55.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.03:36:55.77#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:55.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:55.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:55.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:55.88#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:36:55.88#ibcon#first serial, iclass 17, count 0 2006.257.03:36:55.88#ibcon#enter sib2, iclass 17, count 0 2006.257.03:36:55.88#ibcon#flushed, iclass 17, count 0 2006.257.03:36:55.88#ibcon#about to write, iclass 17, count 0 2006.257.03:36:55.89#ibcon#wrote, iclass 17, count 0 2006.257.03:36:55.89#ibcon#about to read 3, iclass 17, count 0 2006.257.03:36:55.90#ibcon#read 3, iclass 17, count 0 2006.257.03:36:55.90#ibcon#about to read 4, iclass 17, count 0 2006.257.03:36:55.90#ibcon#read 4, iclass 17, count 0 2006.257.03:36:55.90#ibcon#about to read 5, iclass 17, count 0 2006.257.03:36:55.91#ibcon#read 5, iclass 17, count 0 2006.257.03:36:55.91#ibcon#about to read 6, iclass 17, count 0 2006.257.03:36:55.91#ibcon#read 6, iclass 17, count 0 2006.257.03:36:55.91#ibcon#end of sib2, iclass 17, count 0 2006.257.03:36:55.91#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:36:55.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:36:55.91#ibcon#[27=USB\r\n] 2006.257.03:36:55.91#ibcon#*before write, iclass 17, count 0 2006.257.03:36:55.91#ibcon#enter sib2, iclass 17, count 0 2006.257.03:36:55.91#ibcon#flushed, iclass 17, count 0 2006.257.03:36:55.91#ibcon#about to write, iclass 17, count 0 2006.257.03:36:55.91#ibcon#wrote, iclass 17, count 0 2006.257.03:36:55.91#ibcon#about to read 3, iclass 17, count 0 2006.257.03:36:55.93#ibcon#read 3, iclass 17, count 0 2006.257.03:36:55.93#ibcon#about to read 4, iclass 17, count 0 2006.257.03:36:55.93#ibcon#read 4, iclass 17, count 0 2006.257.03:36:55.93#ibcon#about to read 5, iclass 17, count 0 2006.257.03:36:55.93#ibcon#read 5, iclass 17, count 0 2006.257.03:36:55.93#ibcon#about to read 6, iclass 17, count 0 2006.257.03:36:55.94#ibcon#read 6, iclass 17, count 0 2006.257.03:36:55.94#ibcon#end of sib2, iclass 17, count 0 2006.257.03:36:55.94#ibcon#*after write, iclass 17, count 0 2006.257.03:36:55.94#ibcon#*before return 0, iclass 17, count 0 2006.257.03:36:55.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:55.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:36:55.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:36:55.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:36:55.94$vck44/vblo=3,649.99 2006.257.03:36:55.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.03:36:55.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.03:36:55.94#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:55.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:55.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:55.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:55.94#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:36:55.94#ibcon#first serial, iclass 19, count 0 2006.257.03:36:55.94#ibcon#enter sib2, iclass 19, count 0 2006.257.03:36:55.94#ibcon#flushed, iclass 19, count 0 2006.257.03:36:55.94#ibcon#about to write, iclass 19, count 0 2006.257.03:36:55.94#ibcon#wrote, iclass 19, count 0 2006.257.03:36:55.94#ibcon#about to read 3, iclass 19, count 0 2006.257.03:36:55.95#ibcon#read 3, iclass 19, count 0 2006.257.03:36:55.95#ibcon#about to read 4, iclass 19, count 0 2006.257.03:36:55.95#ibcon#read 4, iclass 19, count 0 2006.257.03:36:55.95#ibcon#about to read 5, iclass 19, count 0 2006.257.03:36:55.95#ibcon#read 5, iclass 19, count 0 2006.257.03:36:55.96#ibcon#about to read 6, iclass 19, count 0 2006.257.03:36:55.96#ibcon#read 6, iclass 19, count 0 2006.257.03:36:55.96#ibcon#end of sib2, iclass 19, count 0 2006.257.03:36:55.96#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:36:55.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:36:55.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:36:55.96#ibcon#*before write, iclass 19, count 0 2006.257.03:36:55.96#ibcon#enter sib2, iclass 19, count 0 2006.257.03:36:55.96#ibcon#flushed, iclass 19, count 0 2006.257.03:36:55.96#ibcon#about to write, iclass 19, count 0 2006.257.03:36:55.96#ibcon#wrote, iclass 19, count 0 2006.257.03:36:55.96#ibcon#about to read 3, iclass 19, count 0 2006.257.03:36:55.99#ibcon#read 3, iclass 19, count 0 2006.257.03:36:55.99#ibcon#about to read 4, iclass 19, count 0 2006.257.03:36:55.99#ibcon#read 4, iclass 19, count 0 2006.257.03:36:55.99#ibcon#about to read 5, iclass 19, count 0 2006.257.03:36:55.99#ibcon#read 5, iclass 19, count 0 2006.257.03:36:55.99#ibcon#about to read 6, iclass 19, count 0 2006.257.03:36:56.00#ibcon#read 6, iclass 19, count 0 2006.257.03:36:56.00#ibcon#end of sib2, iclass 19, count 0 2006.257.03:36:56.00#ibcon#*after write, iclass 19, count 0 2006.257.03:36:56.00#ibcon#*before return 0, iclass 19, count 0 2006.257.03:36:56.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:56.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:36:56.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:36:56.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:36:56.00$vck44/vb=3,4 2006.257.03:36:56.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.03:36:56.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.03:36:56.00#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:56.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:56.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:56.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:56.05#ibcon#enter wrdev, iclass 21, count 2 2006.257.03:36:56.05#ibcon#first serial, iclass 21, count 2 2006.257.03:36:56.05#ibcon#enter sib2, iclass 21, count 2 2006.257.03:36:56.05#ibcon#flushed, iclass 21, count 2 2006.257.03:36:56.05#ibcon#about to write, iclass 21, count 2 2006.257.03:36:56.06#ibcon#wrote, iclass 21, count 2 2006.257.03:36:56.06#ibcon#about to read 3, iclass 21, count 2 2006.257.03:36:56.07#ibcon#read 3, iclass 21, count 2 2006.257.03:36:56.07#ibcon#about to read 4, iclass 21, count 2 2006.257.03:36:56.07#ibcon#read 4, iclass 21, count 2 2006.257.03:36:56.07#ibcon#about to read 5, iclass 21, count 2 2006.257.03:36:56.07#ibcon#read 5, iclass 21, count 2 2006.257.03:36:56.07#ibcon#about to read 6, iclass 21, count 2 2006.257.03:36:56.08#ibcon#read 6, iclass 21, count 2 2006.257.03:36:56.08#ibcon#end of sib2, iclass 21, count 2 2006.257.03:36:56.08#ibcon#*mode == 0, iclass 21, count 2 2006.257.03:36:56.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.03:36:56.08#ibcon#[27=AT03-04\r\n] 2006.257.03:36:56.08#ibcon#*before write, iclass 21, count 2 2006.257.03:36:56.08#ibcon#enter sib2, iclass 21, count 2 2006.257.03:36:56.08#ibcon#flushed, iclass 21, count 2 2006.257.03:36:56.08#ibcon#about to write, iclass 21, count 2 2006.257.03:36:56.08#ibcon#wrote, iclass 21, count 2 2006.257.03:36:56.08#ibcon#about to read 3, iclass 21, count 2 2006.257.03:36:56.10#ibcon#read 3, iclass 21, count 2 2006.257.03:36:56.10#ibcon#about to read 4, iclass 21, count 2 2006.257.03:36:56.10#ibcon#read 4, iclass 21, count 2 2006.257.03:36:56.10#ibcon#about to read 5, iclass 21, count 2 2006.257.03:36:56.10#ibcon#read 5, iclass 21, count 2 2006.257.03:36:56.10#ibcon#about to read 6, iclass 21, count 2 2006.257.03:36:56.11#ibcon#read 6, iclass 21, count 2 2006.257.03:36:56.11#ibcon#end of sib2, iclass 21, count 2 2006.257.03:36:56.11#ibcon#*after write, iclass 21, count 2 2006.257.03:36:56.11#ibcon#*before return 0, iclass 21, count 2 2006.257.03:36:56.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:56.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:36:56.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.03:36:56.11#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:56.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:56.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:56.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:56.22#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:36:56.22#ibcon#first serial, iclass 21, count 0 2006.257.03:36:56.22#ibcon#enter sib2, iclass 21, count 0 2006.257.03:36:56.22#ibcon#flushed, iclass 21, count 0 2006.257.03:36:56.22#ibcon#about to write, iclass 21, count 0 2006.257.03:36:56.23#ibcon#wrote, iclass 21, count 0 2006.257.03:36:56.23#ibcon#about to read 3, iclass 21, count 0 2006.257.03:36:56.24#ibcon#read 3, iclass 21, count 0 2006.257.03:36:56.24#ibcon#about to read 4, iclass 21, count 0 2006.257.03:36:56.24#ibcon#read 4, iclass 21, count 0 2006.257.03:36:56.24#ibcon#about to read 5, iclass 21, count 0 2006.257.03:36:56.25#ibcon#read 5, iclass 21, count 0 2006.257.03:36:56.25#ibcon#about to read 6, iclass 21, count 0 2006.257.03:36:56.25#ibcon#read 6, iclass 21, count 0 2006.257.03:36:56.25#ibcon#end of sib2, iclass 21, count 0 2006.257.03:36:56.25#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:36:56.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:36:56.25#ibcon#[27=USB\r\n] 2006.257.03:36:56.25#ibcon#*before write, iclass 21, count 0 2006.257.03:36:56.25#ibcon#enter sib2, iclass 21, count 0 2006.257.03:36:56.25#ibcon#flushed, iclass 21, count 0 2006.257.03:36:56.25#ibcon#about to write, iclass 21, count 0 2006.257.03:36:56.25#ibcon#wrote, iclass 21, count 0 2006.257.03:36:56.25#ibcon#about to read 3, iclass 21, count 0 2006.257.03:36:56.27#ibcon#read 3, iclass 21, count 0 2006.257.03:36:56.27#ibcon#about to read 4, iclass 21, count 0 2006.257.03:36:56.27#ibcon#read 4, iclass 21, count 0 2006.257.03:36:56.27#ibcon#about to read 5, iclass 21, count 0 2006.257.03:36:56.27#ibcon#read 5, iclass 21, count 0 2006.257.03:36:56.27#ibcon#about to read 6, iclass 21, count 0 2006.257.03:36:56.28#ibcon#read 6, iclass 21, count 0 2006.257.03:36:56.28#ibcon#end of sib2, iclass 21, count 0 2006.257.03:36:56.28#ibcon#*after write, iclass 21, count 0 2006.257.03:36:56.28#ibcon#*before return 0, iclass 21, count 0 2006.257.03:36:56.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:56.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:36:56.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:36:56.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:36:56.28$vck44/vblo=4,679.99 2006.257.03:36:56.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.03:36:56.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.03:36:56.28#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:56.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:56.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:56.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:56.28#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:36:56.28#ibcon#first serial, iclass 23, count 0 2006.257.03:36:56.28#ibcon#enter sib2, iclass 23, count 0 2006.257.03:36:56.28#ibcon#flushed, iclass 23, count 0 2006.257.03:36:56.28#ibcon#about to write, iclass 23, count 0 2006.257.03:36:56.28#ibcon#wrote, iclass 23, count 0 2006.257.03:36:56.28#ibcon#about to read 3, iclass 23, count 0 2006.257.03:36:56.29#ibcon#read 3, iclass 23, count 0 2006.257.03:36:56.29#ibcon#about to read 4, iclass 23, count 0 2006.257.03:36:56.29#ibcon#read 4, iclass 23, count 0 2006.257.03:36:56.30#ibcon#about to read 5, iclass 23, count 0 2006.257.03:36:56.30#ibcon#read 5, iclass 23, count 0 2006.257.03:36:56.30#ibcon#about to read 6, iclass 23, count 0 2006.257.03:36:56.30#ibcon#read 6, iclass 23, count 0 2006.257.03:36:56.30#ibcon#end of sib2, iclass 23, count 0 2006.257.03:36:56.30#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:36:56.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:36:56.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:36:56.30#ibcon#*before write, iclass 23, count 0 2006.257.03:36:56.30#ibcon#enter sib2, iclass 23, count 0 2006.257.03:36:56.30#ibcon#flushed, iclass 23, count 0 2006.257.03:36:56.30#ibcon#about to write, iclass 23, count 0 2006.257.03:36:56.30#ibcon#wrote, iclass 23, count 0 2006.257.03:36:56.30#ibcon#about to read 3, iclass 23, count 0 2006.257.03:36:56.33#ibcon#read 3, iclass 23, count 0 2006.257.03:36:56.33#ibcon#about to read 4, iclass 23, count 0 2006.257.03:36:56.33#ibcon#read 4, iclass 23, count 0 2006.257.03:36:56.33#ibcon#about to read 5, iclass 23, count 0 2006.257.03:36:56.33#ibcon#read 5, iclass 23, count 0 2006.257.03:36:56.33#ibcon#about to read 6, iclass 23, count 0 2006.257.03:36:56.34#ibcon#read 6, iclass 23, count 0 2006.257.03:36:56.34#ibcon#end of sib2, iclass 23, count 0 2006.257.03:36:56.34#ibcon#*after write, iclass 23, count 0 2006.257.03:36:56.34#ibcon#*before return 0, iclass 23, count 0 2006.257.03:36:56.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:56.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:36:56.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:36:56.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:36:56.34$vck44/vb=4,5 2006.257.03:36:56.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.03:36:56.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.03:36:56.34#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:56.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:56.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:56.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:56.39#ibcon#enter wrdev, iclass 25, count 2 2006.257.03:36:56.39#ibcon#first serial, iclass 25, count 2 2006.257.03:36:56.39#ibcon#enter sib2, iclass 25, count 2 2006.257.03:36:56.39#ibcon#flushed, iclass 25, count 2 2006.257.03:36:56.39#ibcon#about to write, iclass 25, count 2 2006.257.03:36:56.40#ibcon#wrote, iclass 25, count 2 2006.257.03:36:56.40#ibcon#about to read 3, iclass 25, count 2 2006.257.03:36:56.41#ibcon#read 3, iclass 25, count 2 2006.257.03:36:56.41#ibcon#about to read 4, iclass 25, count 2 2006.257.03:36:56.41#ibcon#read 4, iclass 25, count 2 2006.257.03:36:56.41#ibcon#about to read 5, iclass 25, count 2 2006.257.03:36:56.41#ibcon#read 5, iclass 25, count 2 2006.257.03:36:56.42#ibcon#about to read 6, iclass 25, count 2 2006.257.03:36:56.42#ibcon#read 6, iclass 25, count 2 2006.257.03:36:56.42#ibcon#end of sib2, iclass 25, count 2 2006.257.03:36:56.42#ibcon#*mode == 0, iclass 25, count 2 2006.257.03:36:56.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.03:36:56.42#ibcon#[27=AT04-05\r\n] 2006.257.03:36:56.42#ibcon#*before write, iclass 25, count 2 2006.257.03:36:56.42#ibcon#enter sib2, iclass 25, count 2 2006.257.03:36:56.42#ibcon#flushed, iclass 25, count 2 2006.257.03:36:56.42#ibcon#about to write, iclass 25, count 2 2006.257.03:36:56.42#ibcon#wrote, iclass 25, count 2 2006.257.03:36:56.42#ibcon#about to read 3, iclass 25, count 2 2006.257.03:36:56.44#ibcon#read 3, iclass 25, count 2 2006.257.03:36:56.44#ibcon#about to read 4, iclass 25, count 2 2006.257.03:36:56.44#ibcon#read 4, iclass 25, count 2 2006.257.03:36:56.44#ibcon#about to read 5, iclass 25, count 2 2006.257.03:36:56.44#ibcon#read 5, iclass 25, count 2 2006.257.03:36:56.44#ibcon#about to read 6, iclass 25, count 2 2006.257.03:36:56.45#ibcon#read 6, iclass 25, count 2 2006.257.03:36:56.45#ibcon#end of sib2, iclass 25, count 2 2006.257.03:36:56.45#ibcon#*after write, iclass 25, count 2 2006.257.03:36:56.45#ibcon#*before return 0, iclass 25, count 2 2006.257.03:36:56.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:56.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:36:56.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.03:36:56.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:56.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:56.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:56.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:56.56#ibcon#enter wrdev, iclass 25, count 0 2006.257.03:36:56.56#ibcon#first serial, iclass 25, count 0 2006.257.03:36:56.56#ibcon#enter sib2, iclass 25, count 0 2006.257.03:36:56.56#ibcon#flushed, iclass 25, count 0 2006.257.03:36:56.56#ibcon#about to write, iclass 25, count 0 2006.257.03:36:56.57#ibcon#wrote, iclass 25, count 0 2006.257.03:36:56.57#ibcon#about to read 3, iclass 25, count 0 2006.257.03:36:56.58#ibcon#read 3, iclass 25, count 0 2006.257.03:36:56.58#ibcon#about to read 4, iclass 25, count 0 2006.257.03:36:56.58#ibcon#read 4, iclass 25, count 0 2006.257.03:36:56.58#ibcon#about to read 5, iclass 25, count 0 2006.257.03:36:56.58#ibcon#read 5, iclass 25, count 0 2006.257.03:36:56.58#ibcon#about to read 6, iclass 25, count 0 2006.257.03:36:56.59#ibcon#read 6, iclass 25, count 0 2006.257.03:36:56.59#ibcon#end of sib2, iclass 25, count 0 2006.257.03:36:56.59#ibcon#*mode == 0, iclass 25, count 0 2006.257.03:36:56.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.03:36:56.59#ibcon#[27=USB\r\n] 2006.257.03:36:56.59#ibcon#*before write, iclass 25, count 0 2006.257.03:36:56.59#ibcon#enter sib2, iclass 25, count 0 2006.257.03:36:56.59#ibcon#flushed, iclass 25, count 0 2006.257.03:36:56.59#ibcon#about to write, iclass 25, count 0 2006.257.03:36:56.59#ibcon#wrote, iclass 25, count 0 2006.257.03:36:56.59#ibcon#about to read 3, iclass 25, count 0 2006.257.03:36:56.61#ibcon#read 3, iclass 25, count 0 2006.257.03:36:56.61#ibcon#about to read 4, iclass 25, count 0 2006.257.03:36:56.61#ibcon#read 4, iclass 25, count 0 2006.257.03:36:56.61#ibcon#about to read 5, iclass 25, count 0 2006.257.03:36:56.61#ibcon#read 5, iclass 25, count 0 2006.257.03:36:56.61#ibcon#about to read 6, iclass 25, count 0 2006.257.03:36:56.62#ibcon#read 6, iclass 25, count 0 2006.257.03:36:56.62#ibcon#end of sib2, iclass 25, count 0 2006.257.03:36:56.62#ibcon#*after write, iclass 25, count 0 2006.257.03:36:56.62#ibcon#*before return 0, iclass 25, count 0 2006.257.03:36:56.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:56.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:36:56.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.03:36:56.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.03:36:56.62$vck44/vblo=5,709.99 2006.257.03:36:56.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.03:36:56.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.03:36:56.62#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:56.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:56.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:56.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:56.62#ibcon#enter wrdev, iclass 27, count 0 2006.257.03:36:56.62#ibcon#first serial, iclass 27, count 0 2006.257.03:36:56.62#ibcon#enter sib2, iclass 27, count 0 2006.257.03:36:56.62#ibcon#flushed, iclass 27, count 0 2006.257.03:36:56.62#ibcon#about to write, iclass 27, count 0 2006.257.03:36:56.62#ibcon#wrote, iclass 27, count 0 2006.257.03:36:56.62#ibcon#about to read 3, iclass 27, count 0 2006.257.03:36:56.63#ibcon#read 3, iclass 27, count 0 2006.257.03:36:56.63#ibcon#about to read 4, iclass 27, count 0 2006.257.03:36:56.63#ibcon#read 4, iclass 27, count 0 2006.257.03:36:56.63#ibcon#about to read 5, iclass 27, count 0 2006.257.03:36:56.64#ibcon#read 5, iclass 27, count 0 2006.257.03:36:56.64#ibcon#about to read 6, iclass 27, count 0 2006.257.03:36:56.64#ibcon#read 6, iclass 27, count 0 2006.257.03:36:56.64#ibcon#end of sib2, iclass 27, count 0 2006.257.03:36:56.64#ibcon#*mode == 0, iclass 27, count 0 2006.257.03:36:56.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.03:36:56.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:36:56.64#ibcon#*before write, iclass 27, count 0 2006.257.03:36:56.64#ibcon#enter sib2, iclass 27, count 0 2006.257.03:36:56.64#ibcon#flushed, iclass 27, count 0 2006.257.03:36:56.64#ibcon#about to write, iclass 27, count 0 2006.257.03:36:56.64#ibcon#wrote, iclass 27, count 0 2006.257.03:36:56.64#ibcon#about to read 3, iclass 27, count 0 2006.257.03:36:56.67#ibcon#read 3, iclass 27, count 0 2006.257.03:36:56.67#ibcon#about to read 4, iclass 27, count 0 2006.257.03:36:56.67#ibcon#read 4, iclass 27, count 0 2006.257.03:36:56.67#ibcon#about to read 5, iclass 27, count 0 2006.257.03:36:56.68#ibcon#read 5, iclass 27, count 0 2006.257.03:36:56.68#ibcon#about to read 6, iclass 27, count 0 2006.257.03:36:56.68#ibcon#read 6, iclass 27, count 0 2006.257.03:36:56.68#ibcon#end of sib2, iclass 27, count 0 2006.257.03:36:56.68#ibcon#*after write, iclass 27, count 0 2006.257.03:36:56.68#ibcon#*before return 0, iclass 27, count 0 2006.257.03:36:56.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:56.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:36:56.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.03:36:56.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.03:36:56.68$vck44/vb=5,4 2006.257.03:36:56.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.03:36:56.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.03:36:56.68#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:56.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:56.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:56.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:56.73#ibcon#enter wrdev, iclass 29, count 2 2006.257.03:36:56.73#ibcon#first serial, iclass 29, count 2 2006.257.03:36:56.73#ibcon#enter sib2, iclass 29, count 2 2006.257.03:36:56.73#ibcon#flushed, iclass 29, count 2 2006.257.03:36:56.73#ibcon#about to write, iclass 29, count 2 2006.257.03:36:56.74#ibcon#wrote, iclass 29, count 2 2006.257.03:36:56.74#ibcon#about to read 3, iclass 29, count 2 2006.257.03:36:56.75#ibcon#read 3, iclass 29, count 2 2006.257.03:36:56.75#ibcon#about to read 4, iclass 29, count 2 2006.257.03:36:56.75#ibcon#read 4, iclass 29, count 2 2006.257.03:36:56.75#ibcon#about to read 5, iclass 29, count 2 2006.257.03:36:56.75#ibcon#read 5, iclass 29, count 2 2006.257.03:36:56.75#ibcon#about to read 6, iclass 29, count 2 2006.257.03:36:56.76#ibcon#read 6, iclass 29, count 2 2006.257.03:36:56.76#ibcon#end of sib2, iclass 29, count 2 2006.257.03:36:56.76#ibcon#*mode == 0, iclass 29, count 2 2006.257.03:36:56.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.03:36:56.76#ibcon#[27=AT05-04\r\n] 2006.257.03:36:56.76#ibcon#*before write, iclass 29, count 2 2006.257.03:36:56.76#ibcon#enter sib2, iclass 29, count 2 2006.257.03:36:56.76#ibcon#flushed, iclass 29, count 2 2006.257.03:36:56.76#ibcon#about to write, iclass 29, count 2 2006.257.03:36:56.76#ibcon#wrote, iclass 29, count 2 2006.257.03:36:56.76#ibcon#about to read 3, iclass 29, count 2 2006.257.03:36:56.78#ibcon#read 3, iclass 29, count 2 2006.257.03:36:56.78#ibcon#about to read 4, iclass 29, count 2 2006.257.03:36:56.78#ibcon#read 4, iclass 29, count 2 2006.257.03:36:56.78#ibcon#about to read 5, iclass 29, count 2 2006.257.03:36:56.78#ibcon#read 5, iclass 29, count 2 2006.257.03:36:56.78#ibcon#about to read 6, iclass 29, count 2 2006.257.03:36:56.79#ibcon#read 6, iclass 29, count 2 2006.257.03:36:56.79#ibcon#end of sib2, iclass 29, count 2 2006.257.03:36:56.79#ibcon#*after write, iclass 29, count 2 2006.257.03:36:56.79#ibcon#*before return 0, iclass 29, count 2 2006.257.03:36:56.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:56.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:36:56.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.03:36:56.79#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:56.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:56.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:56.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:56.90#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:36:56.90#ibcon#first serial, iclass 29, count 0 2006.257.03:36:56.90#ibcon#enter sib2, iclass 29, count 0 2006.257.03:36:56.90#ibcon#flushed, iclass 29, count 0 2006.257.03:36:56.90#ibcon#about to write, iclass 29, count 0 2006.257.03:36:56.91#ibcon#wrote, iclass 29, count 0 2006.257.03:36:56.91#ibcon#about to read 3, iclass 29, count 0 2006.257.03:36:56.92#ibcon#read 3, iclass 29, count 0 2006.257.03:36:56.92#ibcon#about to read 4, iclass 29, count 0 2006.257.03:36:56.92#ibcon#read 4, iclass 29, count 0 2006.257.03:36:56.92#ibcon#about to read 5, iclass 29, count 0 2006.257.03:36:56.92#ibcon#read 5, iclass 29, count 0 2006.257.03:36:56.92#ibcon#about to read 6, iclass 29, count 0 2006.257.03:36:56.93#ibcon#read 6, iclass 29, count 0 2006.257.03:36:56.93#ibcon#end of sib2, iclass 29, count 0 2006.257.03:36:56.93#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:36:56.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:36:56.93#ibcon#[27=USB\r\n] 2006.257.03:36:56.93#ibcon#*before write, iclass 29, count 0 2006.257.03:36:56.93#ibcon#enter sib2, iclass 29, count 0 2006.257.03:36:56.93#ibcon#flushed, iclass 29, count 0 2006.257.03:36:56.93#ibcon#about to write, iclass 29, count 0 2006.257.03:36:56.93#ibcon#wrote, iclass 29, count 0 2006.257.03:36:56.93#ibcon#about to read 3, iclass 29, count 0 2006.257.03:36:56.95#ibcon#read 3, iclass 29, count 0 2006.257.03:36:56.95#ibcon#about to read 4, iclass 29, count 0 2006.257.03:36:56.95#ibcon#read 4, iclass 29, count 0 2006.257.03:36:56.95#ibcon#about to read 5, iclass 29, count 0 2006.257.03:36:56.95#ibcon#read 5, iclass 29, count 0 2006.257.03:36:56.95#ibcon#about to read 6, iclass 29, count 0 2006.257.03:36:56.96#ibcon#read 6, iclass 29, count 0 2006.257.03:36:56.96#ibcon#end of sib2, iclass 29, count 0 2006.257.03:36:56.96#ibcon#*after write, iclass 29, count 0 2006.257.03:36:56.96#ibcon#*before return 0, iclass 29, count 0 2006.257.03:36:56.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:56.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:36:56.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:36:56.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:36:56.96$vck44/vblo=6,719.99 2006.257.03:36:56.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.03:36:56.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.03:36:56.96#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:56.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:56.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:56.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:56.96#ibcon#enter wrdev, iclass 31, count 0 2006.257.03:36:56.96#ibcon#first serial, iclass 31, count 0 2006.257.03:36:56.96#ibcon#enter sib2, iclass 31, count 0 2006.257.03:36:56.96#ibcon#flushed, iclass 31, count 0 2006.257.03:36:56.96#ibcon#about to write, iclass 31, count 0 2006.257.03:36:56.96#ibcon#wrote, iclass 31, count 0 2006.257.03:36:56.96#ibcon#about to read 3, iclass 31, count 0 2006.257.03:36:56.97#ibcon#read 3, iclass 31, count 0 2006.257.03:36:56.97#ibcon#about to read 4, iclass 31, count 0 2006.257.03:36:56.97#ibcon#read 4, iclass 31, count 0 2006.257.03:36:56.97#ibcon#about to read 5, iclass 31, count 0 2006.257.03:36:56.97#ibcon#read 5, iclass 31, count 0 2006.257.03:36:56.97#ibcon#about to read 6, iclass 31, count 0 2006.257.03:36:56.98#ibcon#read 6, iclass 31, count 0 2006.257.03:36:56.98#ibcon#end of sib2, iclass 31, count 0 2006.257.03:36:56.98#ibcon#*mode == 0, iclass 31, count 0 2006.257.03:36:56.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.03:36:56.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:36:56.98#ibcon#*before write, iclass 31, count 0 2006.257.03:36:56.98#ibcon#enter sib2, iclass 31, count 0 2006.257.03:36:56.98#ibcon#flushed, iclass 31, count 0 2006.257.03:36:56.98#ibcon#about to write, iclass 31, count 0 2006.257.03:36:56.98#ibcon#wrote, iclass 31, count 0 2006.257.03:36:56.98#ibcon#about to read 3, iclass 31, count 0 2006.257.03:36:57.01#ibcon#read 3, iclass 31, count 0 2006.257.03:36:57.01#ibcon#about to read 4, iclass 31, count 0 2006.257.03:36:57.01#ibcon#read 4, iclass 31, count 0 2006.257.03:36:57.01#ibcon#about to read 5, iclass 31, count 0 2006.257.03:36:57.01#ibcon#read 5, iclass 31, count 0 2006.257.03:36:57.01#ibcon#about to read 6, iclass 31, count 0 2006.257.03:36:57.01#ibcon#read 6, iclass 31, count 0 2006.257.03:36:57.02#ibcon#end of sib2, iclass 31, count 0 2006.257.03:36:57.02#ibcon#*after write, iclass 31, count 0 2006.257.03:36:57.02#ibcon#*before return 0, iclass 31, count 0 2006.257.03:36:57.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:57.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:36:57.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.03:36:57.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.03:36:57.02$vck44/vb=6,4 2006.257.03:36:57.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.03:36:57.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.03:36:57.02#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:57.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:57.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:57.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:57.07#ibcon#enter wrdev, iclass 33, count 2 2006.257.03:36:57.07#ibcon#first serial, iclass 33, count 2 2006.257.03:36:57.07#ibcon#enter sib2, iclass 33, count 2 2006.257.03:36:57.07#ibcon#flushed, iclass 33, count 2 2006.257.03:36:57.07#ibcon#about to write, iclass 33, count 2 2006.257.03:36:57.08#ibcon#wrote, iclass 33, count 2 2006.257.03:36:57.08#ibcon#about to read 3, iclass 33, count 2 2006.257.03:36:57.09#ibcon#read 3, iclass 33, count 2 2006.257.03:36:57.09#ibcon#about to read 4, iclass 33, count 2 2006.257.03:36:57.09#ibcon#read 4, iclass 33, count 2 2006.257.03:36:57.09#ibcon#about to read 5, iclass 33, count 2 2006.257.03:36:57.09#ibcon#read 5, iclass 33, count 2 2006.257.03:36:57.10#ibcon#about to read 6, iclass 33, count 2 2006.257.03:36:57.10#ibcon#read 6, iclass 33, count 2 2006.257.03:36:57.10#ibcon#end of sib2, iclass 33, count 2 2006.257.03:36:57.10#ibcon#*mode == 0, iclass 33, count 2 2006.257.03:36:57.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.03:36:57.10#ibcon#[27=AT06-04\r\n] 2006.257.03:36:57.10#ibcon#*before write, iclass 33, count 2 2006.257.03:36:57.10#ibcon#enter sib2, iclass 33, count 2 2006.257.03:36:57.10#ibcon#flushed, iclass 33, count 2 2006.257.03:36:57.10#ibcon#about to write, iclass 33, count 2 2006.257.03:36:57.10#ibcon#wrote, iclass 33, count 2 2006.257.03:36:57.10#ibcon#about to read 3, iclass 33, count 2 2006.257.03:36:57.12#ibcon#read 3, iclass 33, count 2 2006.257.03:36:57.12#ibcon#about to read 4, iclass 33, count 2 2006.257.03:36:57.12#ibcon#read 4, iclass 33, count 2 2006.257.03:36:57.12#ibcon#about to read 5, iclass 33, count 2 2006.257.03:36:57.12#ibcon#read 5, iclass 33, count 2 2006.257.03:36:57.12#ibcon#about to read 6, iclass 33, count 2 2006.257.03:36:57.13#ibcon#read 6, iclass 33, count 2 2006.257.03:36:57.13#ibcon#end of sib2, iclass 33, count 2 2006.257.03:36:57.13#ibcon#*after write, iclass 33, count 2 2006.257.03:36:57.13#ibcon#*before return 0, iclass 33, count 2 2006.257.03:36:57.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:57.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:36:57.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.03:36:57.13#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:57.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:57.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:57.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:57.24#ibcon#enter wrdev, iclass 33, count 0 2006.257.03:36:57.24#ibcon#first serial, iclass 33, count 0 2006.257.03:36:57.24#ibcon#enter sib2, iclass 33, count 0 2006.257.03:36:57.24#ibcon#flushed, iclass 33, count 0 2006.257.03:36:57.24#ibcon#about to write, iclass 33, count 0 2006.257.03:36:57.25#ibcon#wrote, iclass 33, count 0 2006.257.03:36:57.25#ibcon#about to read 3, iclass 33, count 0 2006.257.03:36:57.26#ibcon#read 3, iclass 33, count 0 2006.257.03:36:57.26#ibcon#about to read 4, iclass 33, count 0 2006.257.03:36:57.26#ibcon#read 4, iclass 33, count 0 2006.257.03:36:57.27#ibcon#about to read 5, iclass 33, count 0 2006.257.03:36:57.27#ibcon#read 5, iclass 33, count 0 2006.257.03:36:57.27#ibcon#about to read 6, iclass 33, count 0 2006.257.03:36:57.27#ibcon#read 6, iclass 33, count 0 2006.257.03:36:57.27#ibcon#end of sib2, iclass 33, count 0 2006.257.03:36:57.27#ibcon#*mode == 0, iclass 33, count 0 2006.257.03:36:57.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.03:36:57.27#ibcon#[27=USB\r\n] 2006.257.03:36:57.27#ibcon#*before write, iclass 33, count 0 2006.257.03:36:57.27#ibcon#enter sib2, iclass 33, count 0 2006.257.03:36:57.27#ibcon#flushed, iclass 33, count 0 2006.257.03:36:57.27#ibcon#about to write, iclass 33, count 0 2006.257.03:36:57.27#ibcon#wrote, iclass 33, count 0 2006.257.03:36:57.27#ibcon#about to read 3, iclass 33, count 0 2006.257.03:36:57.29#ibcon#read 3, iclass 33, count 0 2006.257.03:36:57.29#ibcon#about to read 4, iclass 33, count 0 2006.257.03:36:57.29#ibcon#read 4, iclass 33, count 0 2006.257.03:36:57.29#ibcon#about to read 5, iclass 33, count 0 2006.257.03:36:57.29#ibcon#read 5, iclass 33, count 0 2006.257.03:36:57.29#ibcon#about to read 6, iclass 33, count 0 2006.257.03:36:57.30#ibcon#read 6, iclass 33, count 0 2006.257.03:36:57.30#ibcon#end of sib2, iclass 33, count 0 2006.257.03:36:57.30#ibcon#*after write, iclass 33, count 0 2006.257.03:36:57.30#ibcon#*before return 0, iclass 33, count 0 2006.257.03:36:57.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:57.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:36:57.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.03:36:57.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.03:36:57.30$vck44/vblo=7,734.99 2006.257.03:36:57.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.03:36:57.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.03:36:57.30#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:57.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:57.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:57.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:57.30#ibcon#enter wrdev, iclass 35, count 0 2006.257.03:36:57.30#ibcon#first serial, iclass 35, count 0 2006.257.03:36:57.30#ibcon#enter sib2, iclass 35, count 0 2006.257.03:36:57.30#ibcon#flushed, iclass 35, count 0 2006.257.03:36:57.30#ibcon#about to write, iclass 35, count 0 2006.257.03:36:57.30#ibcon#wrote, iclass 35, count 0 2006.257.03:36:57.30#ibcon#about to read 3, iclass 35, count 0 2006.257.03:36:57.31#ibcon#read 3, iclass 35, count 0 2006.257.03:36:57.31#ibcon#about to read 4, iclass 35, count 0 2006.257.03:36:57.31#ibcon#read 4, iclass 35, count 0 2006.257.03:36:57.31#ibcon#about to read 5, iclass 35, count 0 2006.257.03:36:57.31#ibcon#read 5, iclass 35, count 0 2006.257.03:36:57.31#ibcon#about to read 6, iclass 35, count 0 2006.257.03:36:57.32#ibcon#read 6, iclass 35, count 0 2006.257.03:36:57.32#ibcon#end of sib2, iclass 35, count 0 2006.257.03:36:57.32#ibcon#*mode == 0, iclass 35, count 0 2006.257.03:36:57.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.03:36:57.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:36:57.32#ibcon#*before write, iclass 35, count 0 2006.257.03:36:57.32#ibcon#enter sib2, iclass 35, count 0 2006.257.03:36:57.32#ibcon#flushed, iclass 35, count 0 2006.257.03:36:57.32#ibcon#about to write, iclass 35, count 0 2006.257.03:36:57.32#ibcon#wrote, iclass 35, count 0 2006.257.03:36:57.32#ibcon#about to read 3, iclass 35, count 0 2006.257.03:36:57.35#ibcon#read 3, iclass 35, count 0 2006.257.03:36:57.35#ibcon#about to read 4, iclass 35, count 0 2006.257.03:36:57.35#ibcon#read 4, iclass 35, count 0 2006.257.03:36:57.35#ibcon#about to read 5, iclass 35, count 0 2006.257.03:36:57.35#ibcon#read 5, iclass 35, count 0 2006.257.03:36:57.35#ibcon#about to read 6, iclass 35, count 0 2006.257.03:36:57.36#ibcon#read 6, iclass 35, count 0 2006.257.03:36:57.36#ibcon#end of sib2, iclass 35, count 0 2006.257.03:36:57.36#ibcon#*after write, iclass 35, count 0 2006.257.03:36:57.36#ibcon#*before return 0, iclass 35, count 0 2006.257.03:36:57.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:57.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:36:57.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.03:36:57.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.03:36:57.36$vck44/vb=7,4 2006.257.03:36:57.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.03:36:57.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.03:36:57.36#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:57.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:57.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:57.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:57.42#ibcon#enter wrdev, iclass 37, count 2 2006.257.03:36:57.42#ibcon#first serial, iclass 37, count 2 2006.257.03:36:57.42#ibcon#enter sib2, iclass 37, count 2 2006.257.03:36:57.42#ibcon#flushed, iclass 37, count 2 2006.257.03:36:57.42#ibcon#about to write, iclass 37, count 2 2006.257.03:36:57.42#ibcon#wrote, iclass 37, count 2 2006.257.03:36:57.42#ibcon#about to read 3, iclass 37, count 2 2006.257.03:36:57.43#ibcon#read 3, iclass 37, count 2 2006.257.03:36:57.43#ibcon#about to read 4, iclass 37, count 2 2006.257.03:36:57.43#ibcon#read 4, iclass 37, count 2 2006.257.03:36:57.43#ibcon#about to read 5, iclass 37, count 2 2006.257.03:36:57.43#ibcon#read 5, iclass 37, count 2 2006.257.03:36:57.44#ibcon#about to read 6, iclass 37, count 2 2006.257.03:36:57.44#ibcon#read 6, iclass 37, count 2 2006.257.03:36:57.44#ibcon#end of sib2, iclass 37, count 2 2006.257.03:36:57.44#ibcon#*mode == 0, iclass 37, count 2 2006.257.03:36:57.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.03:36:57.44#ibcon#[27=AT07-04\r\n] 2006.257.03:36:57.44#ibcon#*before write, iclass 37, count 2 2006.257.03:36:57.44#ibcon#enter sib2, iclass 37, count 2 2006.257.03:36:57.44#ibcon#flushed, iclass 37, count 2 2006.257.03:36:57.44#ibcon#about to write, iclass 37, count 2 2006.257.03:36:57.44#ibcon#wrote, iclass 37, count 2 2006.257.03:36:57.44#ibcon#about to read 3, iclass 37, count 2 2006.257.03:36:57.46#ibcon#read 3, iclass 37, count 2 2006.257.03:36:57.46#ibcon#about to read 4, iclass 37, count 2 2006.257.03:36:57.46#ibcon#read 4, iclass 37, count 2 2006.257.03:36:57.46#ibcon#about to read 5, iclass 37, count 2 2006.257.03:36:57.46#ibcon#read 5, iclass 37, count 2 2006.257.03:36:57.46#ibcon#about to read 6, iclass 37, count 2 2006.257.03:36:57.47#ibcon#read 6, iclass 37, count 2 2006.257.03:36:57.47#ibcon#end of sib2, iclass 37, count 2 2006.257.03:36:57.47#ibcon#*after write, iclass 37, count 2 2006.257.03:36:57.47#ibcon#*before return 0, iclass 37, count 2 2006.257.03:36:57.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:57.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:36:57.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.03:36:57.47#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:57.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:57.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:57.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:57.58#ibcon#enter wrdev, iclass 37, count 0 2006.257.03:36:57.58#ibcon#first serial, iclass 37, count 0 2006.257.03:36:57.58#ibcon#enter sib2, iclass 37, count 0 2006.257.03:36:57.58#ibcon#flushed, iclass 37, count 0 2006.257.03:36:57.58#ibcon#about to write, iclass 37, count 0 2006.257.03:36:57.59#ibcon#wrote, iclass 37, count 0 2006.257.03:36:57.59#ibcon#about to read 3, iclass 37, count 0 2006.257.03:36:57.60#ibcon#read 3, iclass 37, count 0 2006.257.03:36:57.60#ibcon#about to read 4, iclass 37, count 0 2006.257.03:36:57.60#ibcon#read 4, iclass 37, count 0 2006.257.03:36:57.60#ibcon#about to read 5, iclass 37, count 0 2006.257.03:36:57.60#ibcon#read 5, iclass 37, count 0 2006.257.03:36:57.61#ibcon#about to read 6, iclass 37, count 0 2006.257.03:36:57.61#ibcon#read 6, iclass 37, count 0 2006.257.03:36:57.61#ibcon#end of sib2, iclass 37, count 0 2006.257.03:36:57.61#ibcon#*mode == 0, iclass 37, count 0 2006.257.03:36:57.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.03:36:57.61#ibcon#[27=USB\r\n] 2006.257.03:36:57.61#ibcon#*before write, iclass 37, count 0 2006.257.03:36:57.61#ibcon#enter sib2, iclass 37, count 0 2006.257.03:36:57.61#ibcon#flushed, iclass 37, count 0 2006.257.03:36:57.61#ibcon#about to write, iclass 37, count 0 2006.257.03:36:57.61#ibcon#wrote, iclass 37, count 0 2006.257.03:36:57.61#ibcon#about to read 3, iclass 37, count 0 2006.257.03:36:57.63#ibcon#read 3, iclass 37, count 0 2006.257.03:36:57.63#ibcon#about to read 4, iclass 37, count 0 2006.257.03:36:57.63#ibcon#read 4, iclass 37, count 0 2006.257.03:36:57.63#ibcon#about to read 5, iclass 37, count 0 2006.257.03:36:57.63#ibcon#read 5, iclass 37, count 0 2006.257.03:36:57.63#ibcon#about to read 6, iclass 37, count 0 2006.257.03:36:57.64#ibcon#read 6, iclass 37, count 0 2006.257.03:36:57.64#ibcon#end of sib2, iclass 37, count 0 2006.257.03:36:57.64#ibcon#*after write, iclass 37, count 0 2006.257.03:36:57.64#ibcon#*before return 0, iclass 37, count 0 2006.257.03:36:57.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:57.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:36:57.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.03:36:57.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.03:36:57.64$vck44/vblo=8,744.99 2006.257.03:36:57.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.03:36:57.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.03:36:57.64#ibcon#ireg 17 cls_cnt 0 2006.257.03:36:57.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:57.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:57.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:57.64#ibcon#enter wrdev, iclass 39, count 0 2006.257.03:36:57.64#ibcon#first serial, iclass 39, count 0 2006.257.03:36:57.64#ibcon#enter sib2, iclass 39, count 0 2006.257.03:36:57.64#ibcon#flushed, iclass 39, count 0 2006.257.03:36:57.64#ibcon#about to write, iclass 39, count 0 2006.257.03:36:57.64#ibcon#wrote, iclass 39, count 0 2006.257.03:36:57.64#ibcon#about to read 3, iclass 39, count 0 2006.257.03:36:57.65#ibcon#read 3, iclass 39, count 0 2006.257.03:36:57.65#ibcon#about to read 4, iclass 39, count 0 2006.257.03:36:57.65#ibcon#read 4, iclass 39, count 0 2006.257.03:36:57.65#ibcon#about to read 5, iclass 39, count 0 2006.257.03:36:57.65#ibcon#read 5, iclass 39, count 0 2006.257.03:36:57.66#ibcon#about to read 6, iclass 39, count 0 2006.257.03:36:57.66#ibcon#read 6, iclass 39, count 0 2006.257.03:36:57.66#ibcon#end of sib2, iclass 39, count 0 2006.257.03:36:57.66#ibcon#*mode == 0, iclass 39, count 0 2006.257.03:36:57.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.03:36:57.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:36:57.66#ibcon#*before write, iclass 39, count 0 2006.257.03:36:57.66#ibcon#enter sib2, iclass 39, count 0 2006.257.03:36:57.66#ibcon#flushed, iclass 39, count 0 2006.257.03:36:57.66#ibcon#about to write, iclass 39, count 0 2006.257.03:36:57.66#ibcon#wrote, iclass 39, count 0 2006.257.03:36:57.66#ibcon#about to read 3, iclass 39, count 0 2006.257.03:36:57.69#ibcon#read 3, iclass 39, count 0 2006.257.03:36:57.69#ibcon#about to read 4, iclass 39, count 0 2006.257.03:36:57.69#ibcon#read 4, iclass 39, count 0 2006.257.03:36:57.69#ibcon#about to read 5, iclass 39, count 0 2006.257.03:36:57.69#ibcon#read 5, iclass 39, count 0 2006.257.03:36:57.69#ibcon#about to read 6, iclass 39, count 0 2006.257.03:36:57.70#ibcon#read 6, iclass 39, count 0 2006.257.03:36:57.70#ibcon#end of sib2, iclass 39, count 0 2006.257.03:36:57.70#ibcon#*after write, iclass 39, count 0 2006.257.03:36:57.70#ibcon#*before return 0, iclass 39, count 0 2006.257.03:36:57.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:57.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:36:57.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.03:36:57.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.03:36:57.70$vck44/vb=8,4 2006.257.03:36:57.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.03:36:57.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.03:36:57.70#ibcon#ireg 11 cls_cnt 2 2006.257.03:36:57.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:57.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:57.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:57.75#ibcon#enter wrdev, iclass 3, count 2 2006.257.03:36:57.75#ibcon#first serial, iclass 3, count 2 2006.257.03:36:57.75#ibcon#enter sib2, iclass 3, count 2 2006.257.03:36:57.75#ibcon#flushed, iclass 3, count 2 2006.257.03:36:57.75#ibcon#about to write, iclass 3, count 2 2006.257.03:36:57.76#ibcon#wrote, iclass 3, count 2 2006.257.03:36:57.76#ibcon#about to read 3, iclass 3, count 2 2006.257.03:36:57.77#ibcon#read 3, iclass 3, count 2 2006.257.03:36:57.77#ibcon#about to read 4, iclass 3, count 2 2006.257.03:36:57.77#ibcon#read 4, iclass 3, count 2 2006.257.03:36:57.77#ibcon#about to read 5, iclass 3, count 2 2006.257.03:36:57.77#ibcon#read 5, iclass 3, count 2 2006.257.03:36:57.77#ibcon#about to read 6, iclass 3, count 2 2006.257.03:36:57.78#ibcon#read 6, iclass 3, count 2 2006.257.03:36:57.78#ibcon#end of sib2, iclass 3, count 2 2006.257.03:36:57.78#ibcon#*mode == 0, iclass 3, count 2 2006.257.03:36:57.78#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.03:36:57.78#ibcon#[27=AT08-04\r\n] 2006.257.03:36:57.78#ibcon#*before write, iclass 3, count 2 2006.257.03:36:57.78#ibcon#enter sib2, iclass 3, count 2 2006.257.03:36:57.78#ibcon#flushed, iclass 3, count 2 2006.257.03:36:57.78#ibcon#about to write, iclass 3, count 2 2006.257.03:36:57.78#ibcon#wrote, iclass 3, count 2 2006.257.03:36:57.78#ibcon#about to read 3, iclass 3, count 2 2006.257.03:36:57.80#ibcon#read 3, iclass 3, count 2 2006.257.03:36:57.80#ibcon#about to read 4, iclass 3, count 2 2006.257.03:36:57.80#ibcon#read 4, iclass 3, count 2 2006.257.03:36:57.80#ibcon#about to read 5, iclass 3, count 2 2006.257.03:36:57.80#ibcon#read 5, iclass 3, count 2 2006.257.03:36:57.80#ibcon#about to read 6, iclass 3, count 2 2006.257.03:36:57.81#ibcon#read 6, iclass 3, count 2 2006.257.03:36:57.81#ibcon#end of sib2, iclass 3, count 2 2006.257.03:36:57.81#ibcon#*after write, iclass 3, count 2 2006.257.03:36:57.81#ibcon#*before return 0, iclass 3, count 2 2006.257.03:36:57.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:57.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:36:57.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.03:36:57.81#ibcon#ireg 7 cls_cnt 0 2006.257.03:36:57.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:57.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:57.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:57.92#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:36:57.92#ibcon#first serial, iclass 3, count 0 2006.257.03:36:57.92#ibcon#enter sib2, iclass 3, count 0 2006.257.03:36:57.92#ibcon#flushed, iclass 3, count 0 2006.257.03:36:57.92#ibcon#about to write, iclass 3, count 0 2006.257.03:36:57.93#ibcon#wrote, iclass 3, count 0 2006.257.03:36:57.93#ibcon#about to read 3, iclass 3, count 0 2006.257.03:36:57.94#ibcon#read 3, iclass 3, count 0 2006.257.03:36:57.94#ibcon#about to read 4, iclass 3, count 0 2006.257.03:36:57.94#ibcon#read 4, iclass 3, count 0 2006.257.03:36:57.94#ibcon#about to read 5, iclass 3, count 0 2006.257.03:36:57.94#ibcon#read 5, iclass 3, count 0 2006.257.03:36:57.94#ibcon#about to read 6, iclass 3, count 0 2006.257.03:36:57.94#ibcon#read 6, iclass 3, count 0 2006.257.03:36:57.95#ibcon#end of sib2, iclass 3, count 0 2006.257.03:36:57.95#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:36:57.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:36:57.95#ibcon#[27=USB\r\n] 2006.257.03:36:57.95#ibcon#*before write, iclass 3, count 0 2006.257.03:36:57.95#ibcon#enter sib2, iclass 3, count 0 2006.257.03:36:57.95#ibcon#flushed, iclass 3, count 0 2006.257.03:36:57.95#ibcon#about to write, iclass 3, count 0 2006.257.03:36:57.95#ibcon#wrote, iclass 3, count 0 2006.257.03:36:57.95#ibcon#about to read 3, iclass 3, count 0 2006.257.03:36:57.97#ibcon#read 3, iclass 3, count 0 2006.257.03:36:57.97#ibcon#about to read 4, iclass 3, count 0 2006.257.03:36:57.97#ibcon#read 4, iclass 3, count 0 2006.257.03:36:57.97#ibcon#about to read 5, iclass 3, count 0 2006.257.03:36:57.97#ibcon#read 5, iclass 3, count 0 2006.257.03:36:57.97#ibcon#about to read 6, iclass 3, count 0 2006.257.03:36:57.98#ibcon#read 6, iclass 3, count 0 2006.257.03:36:57.98#ibcon#end of sib2, iclass 3, count 0 2006.257.03:36:57.98#ibcon#*after write, iclass 3, count 0 2006.257.03:36:57.98#ibcon#*before return 0, iclass 3, count 0 2006.257.03:36:57.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:57.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:36:57.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:36:57.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:36:57.98$vck44/vabw=wide 2006.257.03:36:57.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.03:36:57.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.03:36:57.98#ibcon#ireg 8 cls_cnt 0 2006.257.03:36:57.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:57.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:57.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:57.98#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:36:57.98#ibcon#first serial, iclass 5, count 0 2006.257.03:36:57.98#ibcon#enter sib2, iclass 5, count 0 2006.257.03:36:57.98#ibcon#flushed, iclass 5, count 0 2006.257.03:36:57.98#ibcon#about to write, iclass 5, count 0 2006.257.03:36:57.98#ibcon#wrote, iclass 5, count 0 2006.257.03:36:57.98#ibcon#about to read 3, iclass 5, count 0 2006.257.03:36:57.99#ibcon#read 3, iclass 5, count 0 2006.257.03:36:57.99#ibcon#about to read 4, iclass 5, count 0 2006.257.03:36:57.99#ibcon#read 4, iclass 5, count 0 2006.257.03:36:57.99#ibcon#about to read 5, iclass 5, count 0 2006.257.03:36:57.99#ibcon#read 5, iclass 5, count 0 2006.257.03:36:57.99#ibcon#about to read 6, iclass 5, count 0 2006.257.03:36:58.00#ibcon#read 6, iclass 5, count 0 2006.257.03:36:58.00#ibcon#end of sib2, iclass 5, count 0 2006.257.03:36:58.00#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:36:58.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:36:58.00#ibcon#[25=BW32\r\n] 2006.257.03:36:58.00#ibcon#*before write, iclass 5, count 0 2006.257.03:36:58.00#ibcon#enter sib2, iclass 5, count 0 2006.257.03:36:58.00#ibcon#flushed, iclass 5, count 0 2006.257.03:36:58.00#ibcon#about to write, iclass 5, count 0 2006.257.03:36:58.00#ibcon#wrote, iclass 5, count 0 2006.257.03:36:58.00#ibcon#about to read 3, iclass 5, count 0 2006.257.03:36:58.02#ibcon#read 3, iclass 5, count 0 2006.257.03:36:58.02#ibcon#about to read 4, iclass 5, count 0 2006.257.03:36:58.02#ibcon#read 4, iclass 5, count 0 2006.257.03:36:58.02#ibcon#about to read 5, iclass 5, count 0 2006.257.03:36:58.02#ibcon#read 5, iclass 5, count 0 2006.257.03:36:58.02#ibcon#about to read 6, iclass 5, count 0 2006.257.03:36:58.02#ibcon#read 6, iclass 5, count 0 2006.257.03:36:58.03#ibcon#end of sib2, iclass 5, count 0 2006.257.03:36:58.03#ibcon#*after write, iclass 5, count 0 2006.257.03:36:58.03#ibcon#*before return 0, iclass 5, count 0 2006.257.03:36:58.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:58.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:36:58.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:36:58.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:36:58.03$vck44/vbbw=wide 2006.257.03:36:58.03#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.03:36:58.03#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.03:36:58.03#ibcon#ireg 8 cls_cnt 0 2006.257.03:36:58.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:36:58.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:36:58.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:36:58.09#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:36:58.09#ibcon#first serial, iclass 7, count 0 2006.257.03:36:58.09#ibcon#enter sib2, iclass 7, count 0 2006.257.03:36:58.09#ibcon#flushed, iclass 7, count 0 2006.257.03:36:58.09#ibcon#about to write, iclass 7, count 0 2006.257.03:36:58.10#ibcon#wrote, iclass 7, count 0 2006.257.03:36:58.10#ibcon#about to read 3, iclass 7, count 0 2006.257.03:36:58.11#ibcon#read 3, iclass 7, count 0 2006.257.03:36:58.11#ibcon#about to read 4, iclass 7, count 0 2006.257.03:36:58.11#ibcon#read 4, iclass 7, count 0 2006.257.03:36:58.11#ibcon#about to read 5, iclass 7, count 0 2006.257.03:36:58.11#ibcon#read 5, iclass 7, count 0 2006.257.03:36:58.12#ibcon#about to read 6, iclass 7, count 0 2006.257.03:36:58.12#ibcon#read 6, iclass 7, count 0 2006.257.03:36:58.12#ibcon#end of sib2, iclass 7, count 0 2006.257.03:36:58.12#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:36:58.12#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:36:58.12#ibcon#[27=BW32\r\n] 2006.257.03:36:58.12#ibcon#*before write, iclass 7, count 0 2006.257.03:36:58.12#ibcon#enter sib2, iclass 7, count 0 2006.257.03:36:58.12#ibcon#flushed, iclass 7, count 0 2006.257.03:36:58.12#ibcon#about to write, iclass 7, count 0 2006.257.03:36:58.12#ibcon#wrote, iclass 7, count 0 2006.257.03:36:58.12#ibcon#about to read 3, iclass 7, count 0 2006.257.03:36:58.14#ibcon#read 3, iclass 7, count 0 2006.257.03:36:58.14#ibcon#about to read 4, iclass 7, count 0 2006.257.03:36:58.14#ibcon#read 4, iclass 7, count 0 2006.257.03:36:58.14#ibcon#about to read 5, iclass 7, count 0 2006.257.03:36:58.14#ibcon#read 5, iclass 7, count 0 2006.257.03:36:58.14#ibcon#about to read 6, iclass 7, count 0 2006.257.03:36:58.14#ibcon#read 6, iclass 7, count 0 2006.257.03:36:58.15#ibcon#end of sib2, iclass 7, count 0 2006.257.03:36:58.15#ibcon#*after write, iclass 7, count 0 2006.257.03:36:58.15#ibcon#*before return 0, iclass 7, count 0 2006.257.03:36:58.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:36:58.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:36:58.15#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:36:58.15#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:36:58.15$setupk4/ifdk4 2006.257.03:36:58.15$ifdk4/lo= 2006.257.03:36:58.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:36:58.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:36:58.15$ifdk4/patch= 2006.257.03:36:58.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:36:58.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:36:58.15$setupk4/!*+20s 2006.257.03:37:00.11#abcon#<5=/14 1.9 4.7 19.41 941012.0\r\n> 2006.257.03:37:00.13#abcon#{5=INTERFACE CLEAR} 2006.257.03:37:00.19#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:37:10.28#abcon#<5=/14 1.9 4.7 19.42 941012.0\r\n> 2006.257.03:37:10.30#abcon#{5=INTERFACE CLEAR} 2006.257.03:37:10.36#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:37:12.66$setupk4/"tpicd 2006.257.03:37:12.67$setupk4/echo=off 2006.257.03:37:12.67$setupk4/xlog=off 2006.257.03:37:12.67:!2006.257.03:46:44 2006.257.03:37:19.14#trakl#Source acquired 2006.257.03:37:21.15#flagr#flagr/antenna,acquired 2006.257.03:46:44.00:preob 2006.257.03:46:44.14/onsource/TRACKING 2006.257.03:46:44.14:!2006.257.03:46:54 2006.257.03:46:54.00:"tape 2006.257.03:46:54.00:"st=record 2006.257.03:46:54.00:data_valid=on 2006.257.03:46:54.00:midob 2006.257.03:46:54.14/onsource/TRACKING 2006.257.03:46:54.14/wx/19.40,1012.3,94 2006.257.03:46:54.26/cable/+6.4852E-03 2006.257.03:46:55.35/va/01,08,usb,yes,32,34 2006.257.03:46:55.35/va/02,07,usb,yes,35,35 2006.257.03:46:55.35/va/03,08,usb,yes,31,33 2006.257.03:46:55.35/va/04,07,usb,yes,36,37 2006.257.03:46:55.35/va/05,04,usb,yes,32,32 2006.257.03:46:55.35/va/06,04,usb,yes,36,35 2006.257.03:46:55.35/va/07,04,usb,yes,36,37 2006.257.03:46:55.35/va/08,04,usb,yes,30,37 2006.257.03:46:55.58/valo/01,524.99,yes,locked 2006.257.03:46:55.58/valo/02,534.99,yes,locked 2006.257.03:46:55.58/valo/03,564.99,yes,locked 2006.257.03:46:55.58/valo/04,624.99,yes,locked 2006.257.03:46:55.58/valo/05,734.99,yes,locked 2006.257.03:46:55.58/valo/06,814.99,yes,locked 2006.257.03:46:55.58/valo/07,864.99,yes,locked 2006.257.03:46:55.58/valo/08,884.99,yes,locked 2006.257.03:46:56.67/vb/01,04,usb,yes,31,28 2006.257.03:46:56.67/vb/02,05,usb,yes,29,29 2006.257.03:46:56.67/vb/03,04,usb,yes,30,33 2006.257.03:46:56.67/vb/04,05,usb,yes,30,29 2006.257.03:46:56.67/vb/05,04,usb,yes,27,29 2006.257.03:46:56.67/vb/06,04,usb,yes,31,27 2006.257.03:46:56.67/vb/07,04,usb,yes,31,31 2006.257.03:46:56.67/vb/08,04,usb,yes,28,32 2006.257.03:46:56.90/vblo/01,629.99,yes,locked 2006.257.03:46:56.90/vblo/02,634.99,yes,locked 2006.257.03:46:56.90/vblo/03,649.99,yes,locked 2006.257.03:46:56.90/vblo/04,679.99,yes,locked 2006.257.03:46:56.90/vblo/05,709.99,yes,locked 2006.257.03:46:56.90/vblo/06,719.99,yes,locked 2006.257.03:46:56.90/vblo/07,734.99,yes,locked 2006.257.03:46:56.90/vblo/08,744.99,yes,locked 2006.257.03:46:57.05/vabw/8 2006.257.03:46:57.20/vbbw/8 2006.257.03:46:57.37/xfe/off,on,16.5 2006.257.03:46:57.75/ifatt/23,28,28,28 2006.257.03:46:58.07/fmout-gps/S +4.51E-07 2006.257.03:46:58.11:!2006.257.03:47:34 2006.257.03:47:34.01:data_valid=off 2006.257.03:47:34.02:"et 2006.257.03:47:34.02:!+3s 2006.257.03:47:37.04:"tape 2006.257.03:47:37.04:postob 2006.257.03:47:37.24/cable/+6.4859E-03 2006.257.03:47:37.24/wx/19.39,1012.3,94 2006.257.03:47:37.30/fmout-gps/S +4.51E-07 2006.257.03:47:37.30:scan_name=257-0349,jd0609,40 2006.257.03:47:37.31:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.257.03:47:39.14#flagr#flagr/antenna,new-source 2006.257.03:47:39.15:checkk5 2006.257.03:47:39.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:47:39.87/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:47:40.23/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:47:40.59/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:47:40.93/chk_obsdata//k5ts1/T2570346??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.03:47:41.28/chk_obsdata//k5ts2/T2570346??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.03:47:41.64/chk_obsdata//k5ts3/T2570346??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.03:47:41.99/chk_obsdata//k5ts4/T2570346??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.03:47:42.67/k5log//k5ts1_log_newline 2006.257.03:47:43.34/k5log//k5ts2_log_newline 2006.257.03:47:44.02/k5log//k5ts3_log_newline 2006.257.03:47:44.68/k5log//k5ts4_log_newline 2006.257.03:47:44.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:47:44.70:setupk4=1 2006.257.03:47:44.70$setupk4/echo=on 2006.257.03:47:44.70$setupk4/pcalon 2006.257.03:47:44.70$pcalon/"no phase cal control is implemented here 2006.257.03:47:44.70$setupk4/"tpicd=stop 2006.257.03:47:44.70$setupk4/"rec=synch_on 2006.257.03:47:44.70$setupk4/"rec_mode=128 2006.257.03:47:44.70$setupk4/!* 2006.257.03:47:44.70$setupk4/recpk4 2006.257.03:47:44.70$recpk4/recpatch= 2006.257.03:47:44.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:47:44.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:47:44.71$setupk4/vck44 2006.257.03:47:44.71$vck44/valo=1,524.99 2006.257.03:47:44.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.03:47:44.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.03:47:44.71#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:44.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:44.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:44.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:44.71#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:47:44.71#ibcon#first serial, iclass 18, count 0 2006.257.03:47:44.71#ibcon#enter sib2, iclass 18, count 0 2006.257.03:47:44.71#ibcon#flushed, iclass 18, count 0 2006.257.03:47:44.71#ibcon#about to write, iclass 18, count 0 2006.257.03:47:44.71#ibcon#wrote, iclass 18, count 0 2006.257.03:47:44.71#ibcon#about to read 3, iclass 18, count 0 2006.257.03:47:44.72#ibcon#read 3, iclass 18, count 0 2006.257.03:47:44.72#ibcon#about to read 4, iclass 18, count 0 2006.257.03:47:44.72#ibcon#read 4, iclass 18, count 0 2006.257.03:47:44.72#ibcon#about to read 5, iclass 18, count 0 2006.257.03:47:44.72#ibcon#read 5, iclass 18, count 0 2006.257.03:47:44.72#ibcon#about to read 6, iclass 18, count 0 2006.257.03:47:44.72#ibcon#read 6, iclass 18, count 0 2006.257.03:47:44.72#ibcon#end of sib2, iclass 18, count 0 2006.257.03:47:44.72#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:47:44.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:47:44.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:47:44.72#ibcon#*before write, iclass 18, count 0 2006.257.03:47:44.72#ibcon#enter sib2, iclass 18, count 0 2006.257.03:47:44.72#ibcon#flushed, iclass 18, count 0 2006.257.03:47:44.72#ibcon#about to write, iclass 18, count 0 2006.257.03:47:44.72#ibcon#wrote, iclass 18, count 0 2006.257.03:47:44.72#ibcon#about to read 3, iclass 18, count 0 2006.257.03:47:44.77#ibcon#read 3, iclass 18, count 0 2006.257.03:47:44.77#ibcon#about to read 4, iclass 18, count 0 2006.257.03:47:44.77#ibcon#read 4, iclass 18, count 0 2006.257.03:47:44.77#ibcon#about to read 5, iclass 18, count 0 2006.257.03:47:44.77#ibcon#read 5, iclass 18, count 0 2006.257.03:47:44.77#ibcon#about to read 6, iclass 18, count 0 2006.257.03:47:44.77#ibcon#read 6, iclass 18, count 0 2006.257.03:47:44.77#ibcon#end of sib2, iclass 18, count 0 2006.257.03:47:44.77#ibcon#*after write, iclass 18, count 0 2006.257.03:47:44.77#ibcon#*before return 0, iclass 18, count 0 2006.257.03:47:44.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:44.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:44.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:47:44.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:47:44.77$vck44/va=1,8 2006.257.03:47:44.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.03:47:44.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.03:47:44.77#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:44.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:44.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:44.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:44.77#ibcon#enter wrdev, iclass 20, count 2 2006.257.03:47:44.77#ibcon#first serial, iclass 20, count 2 2006.257.03:47:44.77#ibcon#enter sib2, iclass 20, count 2 2006.257.03:47:44.77#ibcon#flushed, iclass 20, count 2 2006.257.03:47:44.77#ibcon#about to write, iclass 20, count 2 2006.257.03:47:44.77#ibcon#wrote, iclass 20, count 2 2006.257.03:47:44.77#ibcon#about to read 3, iclass 20, count 2 2006.257.03:47:44.79#ibcon#read 3, iclass 20, count 2 2006.257.03:47:44.79#ibcon#about to read 4, iclass 20, count 2 2006.257.03:47:44.79#ibcon#read 4, iclass 20, count 2 2006.257.03:47:44.79#ibcon#about to read 5, iclass 20, count 2 2006.257.03:47:44.79#ibcon#read 5, iclass 20, count 2 2006.257.03:47:44.79#ibcon#about to read 6, iclass 20, count 2 2006.257.03:47:44.79#ibcon#read 6, iclass 20, count 2 2006.257.03:47:44.79#ibcon#end of sib2, iclass 20, count 2 2006.257.03:47:44.79#ibcon#*mode == 0, iclass 20, count 2 2006.257.03:47:44.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.03:47:44.79#ibcon#[25=AT01-08\r\n] 2006.257.03:47:44.79#ibcon#*before write, iclass 20, count 2 2006.257.03:47:44.79#ibcon#enter sib2, iclass 20, count 2 2006.257.03:47:44.79#ibcon#flushed, iclass 20, count 2 2006.257.03:47:44.79#ibcon#about to write, iclass 20, count 2 2006.257.03:47:44.79#ibcon#wrote, iclass 20, count 2 2006.257.03:47:44.79#ibcon#about to read 3, iclass 20, count 2 2006.257.03:47:44.82#ibcon#read 3, iclass 20, count 2 2006.257.03:47:44.82#ibcon#about to read 4, iclass 20, count 2 2006.257.03:47:44.82#ibcon#read 4, iclass 20, count 2 2006.257.03:47:44.82#ibcon#about to read 5, iclass 20, count 2 2006.257.03:47:44.82#ibcon#read 5, iclass 20, count 2 2006.257.03:47:44.82#ibcon#about to read 6, iclass 20, count 2 2006.257.03:47:44.82#ibcon#read 6, iclass 20, count 2 2006.257.03:47:44.82#ibcon#end of sib2, iclass 20, count 2 2006.257.03:47:44.82#ibcon#*after write, iclass 20, count 2 2006.257.03:47:44.82#ibcon#*before return 0, iclass 20, count 2 2006.257.03:47:44.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:44.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:44.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.03:47:44.82#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:44.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:44.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:44.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:44.94#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:47:44.94#ibcon#first serial, iclass 20, count 0 2006.257.03:47:44.94#ibcon#enter sib2, iclass 20, count 0 2006.257.03:47:44.94#ibcon#flushed, iclass 20, count 0 2006.257.03:47:44.94#ibcon#about to write, iclass 20, count 0 2006.257.03:47:44.94#ibcon#wrote, iclass 20, count 0 2006.257.03:47:44.94#ibcon#about to read 3, iclass 20, count 0 2006.257.03:47:44.96#ibcon#read 3, iclass 20, count 0 2006.257.03:47:44.96#ibcon#about to read 4, iclass 20, count 0 2006.257.03:47:44.96#ibcon#read 4, iclass 20, count 0 2006.257.03:47:44.96#ibcon#about to read 5, iclass 20, count 0 2006.257.03:47:44.96#ibcon#read 5, iclass 20, count 0 2006.257.03:47:44.96#ibcon#about to read 6, iclass 20, count 0 2006.257.03:47:44.96#ibcon#read 6, iclass 20, count 0 2006.257.03:47:44.96#ibcon#end of sib2, iclass 20, count 0 2006.257.03:47:44.96#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:47:44.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:47:44.96#ibcon#[25=USB\r\n] 2006.257.03:47:44.96#ibcon#*before write, iclass 20, count 0 2006.257.03:47:44.96#ibcon#enter sib2, iclass 20, count 0 2006.257.03:47:44.96#ibcon#flushed, iclass 20, count 0 2006.257.03:47:44.96#ibcon#about to write, iclass 20, count 0 2006.257.03:47:44.96#ibcon#wrote, iclass 20, count 0 2006.257.03:47:44.96#ibcon#about to read 3, iclass 20, count 0 2006.257.03:47:44.99#ibcon#read 3, iclass 20, count 0 2006.257.03:47:44.99#ibcon#about to read 4, iclass 20, count 0 2006.257.03:47:44.99#ibcon#read 4, iclass 20, count 0 2006.257.03:47:44.99#ibcon#about to read 5, iclass 20, count 0 2006.257.03:47:44.99#ibcon#read 5, iclass 20, count 0 2006.257.03:47:44.99#ibcon#about to read 6, iclass 20, count 0 2006.257.03:47:44.99#ibcon#read 6, iclass 20, count 0 2006.257.03:47:44.99#ibcon#end of sib2, iclass 20, count 0 2006.257.03:47:44.99#ibcon#*after write, iclass 20, count 0 2006.257.03:47:44.99#ibcon#*before return 0, iclass 20, count 0 2006.257.03:47:44.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:44.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:44.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:47:44.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:47:44.99$vck44/valo=2,534.99 2006.257.03:47:44.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.03:47:44.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.03:47:44.99#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:44.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:44.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:44.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:44.99#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:47:44.99#ibcon#first serial, iclass 22, count 0 2006.257.03:47:44.99#ibcon#enter sib2, iclass 22, count 0 2006.257.03:47:44.99#ibcon#flushed, iclass 22, count 0 2006.257.03:47:44.99#ibcon#about to write, iclass 22, count 0 2006.257.03:47:44.99#ibcon#wrote, iclass 22, count 0 2006.257.03:47:44.99#ibcon#about to read 3, iclass 22, count 0 2006.257.03:47:45.01#ibcon#read 3, iclass 22, count 0 2006.257.03:47:45.01#ibcon#about to read 4, iclass 22, count 0 2006.257.03:47:45.01#ibcon#read 4, iclass 22, count 0 2006.257.03:47:45.01#ibcon#about to read 5, iclass 22, count 0 2006.257.03:47:45.01#ibcon#read 5, iclass 22, count 0 2006.257.03:47:45.01#ibcon#about to read 6, iclass 22, count 0 2006.257.03:47:45.01#ibcon#read 6, iclass 22, count 0 2006.257.03:47:45.01#ibcon#end of sib2, iclass 22, count 0 2006.257.03:47:45.01#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:47:45.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:47:45.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:47:45.01#ibcon#*before write, iclass 22, count 0 2006.257.03:47:45.01#ibcon#enter sib2, iclass 22, count 0 2006.257.03:47:45.01#ibcon#flushed, iclass 22, count 0 2006.257.03:47:45.01#ibcon#about to write, iclass 22, count 0 2006.257.03:47:45.01#ibcon#wrote, iclass 22, count 0 2006.257.03:47:45.01#ibcon#about to read 3, iclass 22, count 0 2006.257.03:47:45.05#ibcon#read 3, iclass 22, count 0 2006.257.03:47:45.05#ibcon#about to read 4, iclass 22, count 0 2006.257.03:47:45.05#ibcon#read 4, iclass 22, count 0 2006.257.03:47:45.05#ibcon#about to read 5, iclass 22, count 0 2006.257.03:47:45.05#ibcon#read 5, iclass 22, count 0 2006.257.03:47:45.05#ibcon#about to read 6, iclass 22, count 0 2006.257.03:47:45.05#ibcon#read 6, iclass 22, count 0 2006.257.03:47:45.05#ibcon#end of sib2, iclass 22, count 0 2006.257.03:47:45.05#ibcon#*after write, iclass 22, count 0 2006.257.03:47:45.05#ibcon#*before return 0, iclass 22, count 0 2006.257.03:47:45.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:45.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:45.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:47:45.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:47:45.05$vck44/va=2,7 2006.257.03:47:45.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.03:47:45.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.03:47:45.05#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:45.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:45.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:45.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:45.11#ibcon#enter wrdev, iclass 24, count 2 2006.257.03:47:45.11#ibcon#first serial, iclass 24, count 2 2006.257.03:47:45.11#ibcon#enter sib2, iclass 24, count 2 2006.257.03:47:45.11#ibcon#flushed, iclass 24, count 2 2006.257.03:47:45.11#ibcon#about to write, iclass 24, count 2 2006.257.03:47:45.11#ibcon#wrote, iclass 24, count 2 2006.257.03:47:45.11#ibcon#about to read 3, iclass 24, count 2 2006.257.03:47:45.13#ibcon#read 3, iclass 24, count 2 2006.257.03:47:45.13#ibcon#about to read 4, iclass 24, count 2 2006.257.03:47:45.13#ibcon#read 4, iclass 24, count 2 2006.257.03:47:45.13#ibcon#about to read 5, iclass 24, count 2 2006.257.03:47:45.13#ibcon#read 5, iclass 24, count 2 2006.257.03:47:45.13#ibcon#about to read 6, iclass 24, count 2 2006.257.03:47:45.13#ibcon#read 6, iclass 24, count 2 2006.257.03:47:45.13#ibcon#end of sib2, iclass 24, count 2 2006.257.03:47:45.13#ibcon#*mode == 0, iclass 24, count 2 2006.257.03:47:45.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.03:47:45.13#ibcon#[25=AT02-07\r\n] 2006.257.03:47:45.13#ibcon#*before write, iclass 24, count 2 2006.257.03:47:45.13#ibcon#enter sib2, iclass 24, count 2 2006.257.03:47:45.13#ibcon#flushed, iclass 24, count 2 2006.257.03:47:45.13#ibcon#about to write, iclass 24, count 2 2006.257.03:47:45.13#ibcon#wrote, iclass 24, count 2 2006.257.03:47:45.13#ibcon#about to read 3, iclass 24, count 2 2006.257.03:47:45.16#ibcon#read 3, iclass 24, count 2 2006.257.03:47:45.16#ibcon#about to read 4, iclass 24, count 2 2006.257.03:47:45.16#ibcon#read 4, iclass 24, count 2 2006.257.03:47:45.16#ibcon#about to read 5, iclass 24, count 2 2006.257.03:47:45.16#ibcon#read 5, iclass 24, count 2 2006.257.03:47:45.16#ibcon#about to read 6, iclass 24, count 2 2006.257.03:47:45.16#ibcon#read 6, iclass 24, count 2 2006.257.03:47:45.16#ibcon#end of sib2, iclass 24, count 2 2006.257.03:47:45.16#ibcon#*after write, iclass 24, count 2 2006.257.03:47:45.16#ibcon#*before return 0, iclass 24, count 2 2006.257.03:47:45.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:45.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:45.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.03:47:45.16#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:45.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:45.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:45.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:45.28#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:47:45.28#ibcon#first serial, iclass 24, count 0 2006.257.03:47:45.28#ibcon#enter sib2, iclass 24, count 0 2006.257.03:47:45.28#ibcon#flushed, iclass 24, count 0 2006.257.03:47:45.28#ibcon#about to write, iclass 24, count 0 2006.257.03:47:45.28#ibcon#wrote, iclass 24, count 0 2006.257.03:47:45.28#ibcon#about to read 3, iclass 24, count 0 2006.257.03:47:45.30#ibcon#read 3, iclass 24, count 0 2006.257.03:47:45.30#ibcon#about to read 4, iclass 24, count 0 2006.257.03:47:45.30#ibcon#read 4, iclass 24, count 0 2006.257.03:47:45.30#ibcon#about to read 5, iclass 24, count 0 2006.257.03:47:45.30#ibcon#read 5, iclass 24, count 0 2006.257.03:47:45.30#ibcon#about to read 6, iclass 24, count 0 2006.257.03:47:45.30#ibcon#read 6, iclass 24, count 0 2006.257.03:47:45.30#ibcon#end of sib2, iclass 24, count 0 2006.257.03:47:45.30#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:47:45.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:47:45.30#ibcon#[25=USB\r\n] 2006.257.03:47:45.30#ibcon#*before write, iclass 24, count 0 2006.257.03:47:45.30#ibcon#enter sib2, iclass 24, count 0 2006.257.03:47:45.30#ibcon#flushed, iclass 24, count 0 2006.257.03:47:45.30#ibcon#about to write, iclass 24, count 0 2006.257.03:47:45.30#ibcon#wrote, iclass 24, count 0 2006.257.03:47:45.30#ibcon#about to read 3, iclass 24, count 0 2006.257.03:47:45.33#ibcon#read 3, iclass 24, count 0 2006.257.03:47:45.33#ibcon#about to read 4, iclass 24, count 0 2006.257.03:47:45.33#ibcon#read 4, iclass 24, count 0 2006.257.03:47:45.33#ibcon#about to read 5, iclass 24, count 0 2006.257.03:47:45.33#ibcon#read 5, iclass 24, count 0 2006.257.03:47:45.33#ibcon#about to read 6, iclass 24, count 0 2006.257.03:47:45.33#ibcon#read 6, iclass 24, count 0 2006.257.03:47:45.33#ibcon#end of sib2, iclass 24, count 0 2006.257.03:47:45.33#ibcon#*after write, iclass 24, count 0 2006.257.03:47:45.33#ibcon#*before return 0, iclass 24, count 0 2006.257.03:47:45.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:45.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:45.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:47:45.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:47:45.33$vck44/valo=3,564.99 2006.257.03:47:45.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.03:47:45.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.03:47:45.33#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:45.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:45.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:45.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:45.33#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:47:45.33#ibcon#first serial, iclass 26, count 0 2006.257.03:47:45.33#ibcon#enter sib2, iclass 26, count 0 2006.257.03:47:45.33#ibcon#flushed, iclass 26, count 0 2006.257.03:47:45.33#ibcon#about to write, iclass 26, count 0 2006.257.03:47:45.33#ibcon#wrote, iclass 26, count 0 2006.257.03:47:45.33#ibcon#about to read 3, iclass 26, count 0 2006.257.03:47:45.35#ibcon#read 3, iclass 26, count 0 2006.257.03:47:45.35#ibcon#about to read 4, iclass 26, count 0 2006.257.03:47:45.35#ibcon#read 4, iclass 26, count 0 2006.257.03:47:45.35#ibcon#about to read 5, iclass 26, count 0 2006.257.03:47:45.35#ibcon#read 5, iclass 26, count 0 2006.257.03:47:45.35#ibcon#about to read 6, iclass 26, count 0 2006.257.03:47:45.35#ibcon#read 6, iclass 26, count 0 2006.257.03:47:45.35#ibcon#end of sib2, iclass 26, count 0 2006.257.03:47:45.35#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:47:45.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:47:45.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:47:45.35#ibcon#*before write, iclass 26, count 0 2006.257.03:47:45.35#ibcon#enter sib2, iclass 26, count 0 2006.257.03:47:45.35#ibcon#flushed, iclass 26, count 0 2006.257.03:47:45.35#ibcon#about to write, iclass 26, count 0 2006.257.03:47:45.35#ibcon#wrote, iclass 26, count 0 2006.257.03:47:45.35#ibcon#about to read 3, iclass 26, count 0 2006.257.03:47:45.39#ibcon#read 3, iclass 26, count 0 2006.257.03:47:45.39#ibcon#about to read 4, iclass 26, count 0 2006.257.03:47:45.39#ibcon#read 4, iclass 26, count 0 2006.257.03:47:45.39#ibcon#about to read 5, iclass 26, count 0 2006.257.03:47:45.39#ibcon#read 5, iclass 26, count 0 2006.257.03:47:45.39#ibcon#about to read 6, iclass 26, count 0 2006.257.03:47:45.39#ibcon#read 6, iclass 26, count 0 2006.257.03:47:45.39#ibcon#end of sib2, iclass 26, count 0 2006.257.03:47:45.39#ibcon#*after write, iclass 26, count 0 2006.257.03:47:45.39#ibcon#*before return 0, iclass 26, count 0 2006.257.03:47:45.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:45.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:45.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:47:45.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:47:45.39$vck44/va=3,8 2006.257.03:47:45.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.03:47:45.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.03:47:45.39#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:45.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:45.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:45.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:45.45#ibcon#enter wrdev, iclass 28, count 2 2006.257.03:47:45.45#ibcon#first serial, iclass 28, count 2 2006.257.03:47:45.45#ibcon#enter sib2, iclass 28, count 2 2006.257.03:47:45.45#ibcon#flushed, iclass 28, count 2 2006.257.03:47:45.45#ibcon#about to write, iclass 28, count 2 2006.257.03:47:45.45#ibcon#wrote, iclass 28, count 2 2006.257.03:47:45.45#ibcon#about to read 3, iclass 28, count 2 2006.257.03:47:45.47#ibcon#read 3, iclass 28, count 2 2006.257.03:47:45.47#ibcon#about to read 4, iclass 28, count 2 2006.257.03:47:45.47#ibcon#read 4, iclass 28, count 2 2006.257.03:47:45.47#ibcon#about to read 5, iclass 28, count 2 2006.257.03:47:45.47#ibcon#read 5, iclass 28, count 2 2006.257.03:47:45.47#ibcon#about to read 6, iclass 28, count 2 2006.257.03:47:45.47#ibcon#read 6, iclass 28, count 2 2006.257.03:47:45.47#ibcon#end of sib2, iclass 28, count 2 2006.257.03:47:45.47#ibcon#*mode == 0, iclass 28, count 2 2006.257.03:47:45.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.03:47:45.47#ibcon#[25=AT03-08\r\n] 2006.257.03:47:45.47#ibcon#*before write, iclass 28, count 2 2006.257.03:47:45.47#ibcon#enter sib2, iclass 28, count 2 2006.257.03:47:45.47#ibcon#flushed, iclass 28, count 2 2006.257.03:47:45.47#ibcon#about to write, iclass 28, count 2 2006.257.03:47:45.47#ibcon#wrote, iclass 28, count 2 2006.257.03:47:45.47#ibcon#about to read 3, iclass 28, count 2 2006.257.03:47:45.50#ibcon#read 3, iclass 28, count 2 2006.257.03:47:45.50#ibcon#about to read 4, iclass 28, count 2 2006.257.03:47:45.50#ibcon#read 4, iclass 28, count 2 2006.257.03:47:45.50#ibcon#about to read 5, iclass 28, count 2 2006.257.03:47:45.50#ibcon#read 5, iclass 28, count 2 2006.257.03:47:45.50#ibcon#about to read 6, iclass 28, count 2 2006.257.03:47:45.50#ibcon#read 6, iclass 28, count 2 2006.257.03:47:45.50#ibcon#end of sib2, iclass 28, count 2 2006.257.03:47:45.50#ibcon#*after write, iclass 28, count 2 2006.257.03:47:45.50#ibcon#*before return 0, iclass 28, count 2 2006.257.03:47:45.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:45.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:45.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.03:47:45.50#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:45.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:45.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:45.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:45.62#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:47:45.62#ibcon#first serial, iclass 28, count 0 2006.257.03:47:45.62#ibcon#enter sib2, iclass 28, count 0 2006.257.03:47:45.62#ibcon#flushed, iclass 28, count 0 2006.257.03:47:45.62#ibcon#about to write, iclass 28, count 0 2006.257.03:47:45.62#ibcon#wrote, iclass 28, count 0 2006.257.03:47:45.62#ibcon#about to read 3, iclass 28, count 0 2006.257.03:47:45.64#ibcon#read 3, iclass 28, count 0 2006.257.03:47:45.64#ibcon#about to read 4, iclass 28, count 0 2006.257.03:47:45.64#ibcon#read 4, iclass 28, count 0 2006.257.03:47:45.64#ibcon#about to read 5, iclass 28, count 0 2006.257.03:47:45.64#ibcon#read 5, iclass 28, count 0 2006.257.03:47:45.64#ibcon#about to read 6, iclass 28, count 0 2006.257.03:47:45.64#ibcon#read 6, iclass 28, count 0 2006.257.03:47:45.64#ibcon#end of sib2, iclass 28, count 0 2006.257.03:47:45.64#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:47:45.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:47:45.64#ibcon#[25=USB\r\n] 2006.257.03:47:45.64#ibcon#*before write, iclass 28, count 0 2006.257.03:47:45.64#ibcon#enter sib2, iclass 28, count 0 2006.257.03:47:45.64#ibcon#flushed, iclass 28, count 0 2006.257.03:47:45.64#ibcon#about to write, iclass 28, count 0 2006.257.03:47:45.64#ibcon#wrote, iclass 28, count 0 2006.257.03:47:45.64#ibcon#about to read 3, iclass 28, count 0 2006.257.03:47:45.67#ibcon#read 3, iclass 28, count 0 2006.257.03:47:45.67#ibcon#about to read 4, iclass 28, count 0 2006.257.03:47:45.67#ibcon#read 4, iclass 28, count 0 2006.257.03:47:45.67#ibcon#about to read 5, iclass 28, count 0 2006.257.03:47:45.67#ibcon#read 5, iclass 28, count 0 2006.257.03:47:45.67#ibcon#about to read 6, iclass 28, count 0 2006.257.03:47:45.67#ibcon#read 6, iclass 28, count 0 2006.257.03:47:45.67#ibcon#end of sib2, iclass 28, count 0 2006.257.03:47:45.67#ibcon#*after write, iclass 28, count 0 2006.257.03:47:45.67#ibcon#*before return 0, iclass 28, count 0 2006.257.03:47:45.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:45.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:45.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:47:45.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:47:45.67$vck44/valo=4,624.99 2006.257.03:47:45.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.03:47:45.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.03:47:45.67#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:45.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:45.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:45.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:45.67#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:47:45.67#ibcon#first serial, iclass 30, count 0 2006.257.03:47:45.67#ibcon#enter sib2, iclass 30, count 0 2006.257.03:47:45.67#ibcon#flushed, iclass 30, count 0 2006.257.03:47:45.67#ibcon#about to write, iclass 30, count 0 2006.257.03:47:45.67#ibcon#wrote, iclass 30, count 0 2006.257.03:47:45.67#ibcon#about to read 3, iclass 30, count 0 2006.257.03:47:45.69#ibcon#read 3, iclass 30, count 0 2006.257.03:47:45.69#ibcon#about to read 4, iclass 30, count 0 2006.257.03:47:45.69#ibcon#read 4, iclass 30, count 0 2006.257.03:47:45.69#ibcon#about to read 5, iclass 30, count 0 2006.257.03:47:45.69#ibcon#read 5, iclass 30, count 0 2006.257.03:47:45.69#ibcon#about to read 6, iclass 30, count 0 2006.257.03:47:45.69#ibcon#read 6, iclass 30, count 0 2006.257.03:47:45.69#ibcon#end of sib2, iclass 30, count 0 2006.257.03:47:45.69#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:47:45.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:47:45.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:47:45.69#ibcon#*before write, iclass 30, count 0 2006.257.03:47:45.69#ibcon#enter sib2, iclass 30, count 0 2006.257.03:47:45.69#ibcon#flushed, iclass 30, count 0 2006.257.03:47:45.69#ibcon#about to write, iclass 30, count 0 2006.257.03:47:45.69#ibcon#wrote, iclass 30, count 0 2006.257.03:47:45.69#ibcon#about to read 3, iclass 30, count 0 2006.257.03:47:45.73#ibcon#read 3, iclass 30, count 0 2006.257.03:47:45.73#ibcon#about to read 4, iclass 30, count 0 2006.257.03:47:45.73#ibcon#read 4, iclass 30, count 0 2006.257.03:47:45.73#ibcon#about to read 5, iclass 30, count 0 2006.257.03:47:45.73#ibcon#read 5, iclass 30, count 0 2006.257.03:47:45.73#ibcon#about to read 6, iclass 30, count 0 2006.257.03:47:45.73#ibcon#read 6, iclass 30, count 0 2006.257.03:47:45.73#ibcon#end of sib2, iclass 30, count 0 2006.257.03:47:45.73#ibcon#*after write, iclass 30, count 0 2006.257.03:47:45.73#ibcon#*before return 0, iclass 30, count 0 2006.257.03:47:45.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:45.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:45.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:47:45.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:47:45.73$vck44/va=4,7 2006.257.03:47:45.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.03:47:45.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.03:47:45.73#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:45.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:45.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:45.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:45.79#ibcon#enter wrdev, iclass 32, count 2 2006.257.03:47:45.79#ibcon#first serial, iclass 32, count 2 2006.257.03:47:45.79#ibcon#enter sib2, iclass 32, count 2 2006.257.03:47:45.79#ibcon#flushed, iclass 32, count 2 2006.257.03:47:45.79#ibcon#about to write, iclass 32, count 2 2006.257.03:47:45.79#ibcon#wrote, iclass 32, count 2 2006.257.03:47:45.79#ibcon#about to read 3, iclass 32, count 2 2006.257.03:47:45.81#ibcon#read 3, iclass 32, count 2 2006.257.03:47:45.81#ibcon#about to read 4, iclass 32, count 2 2006.257.03:47:45.81#ibcon#read 4, iclass 32, count 2 2006.257.03:47:45.81#ibcon#about to read 5, iclass 32, count 2 2006.257.03:47:45.81#ibcon#read 5, iclass 32, count 2 2006.257.03:47:45.81#ibcon#about to read 6, iclass 32, count 2 2006.257.03:47:45.81#ibcon#read 6, iclass 32, count 2 2006.257.03:47:45.81#ibcon#end of sib2, iclass 32, count 2 2006.257.03:47:45.81#ibcon#*mode == 0, iclass 32, count 2 2006.257.03:47:45.81#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.03:47:45.81#ibcon#[25=AT04-07\r\n] 2006.257.03:47:45.81#ibcon#*before write, iclass 32, count 2 2006.257.03:47:45.81#ibcon#enter sib2, iclass 32, count 2 2006.257.03:47:45.81#ibcon#flushed, iclass 32, count 2 2006.257.03:47:45.81#ibcon#about to write, iclass 32, count 2 2006.257.03:47:45.81#ibcon#wrote, iclass 32, count 2 2006.257.03:47:45.81#ibcon#about to read 3, iclass 32, count 2 2006.257.03:47:45.84#ibcon#read 3, iclass 32, count 2 2006.257.03:47:45.84#ibcon#about to read 4, iclass 32, count 2 2006.257.03:47:45.84#ibcon#read 4, iclass 32, count 2 2006.257.03:47:45.84#ibcon#about to read 5, iclass 32, count 2 2006.257.03:47:45.84#ibcon#read 5, iclass 32, count 2 2006.257.03:47:45.84#ibcon#about to read 6, iclass 32, count 2 2006.257.03:47:45.84#ibcon#read 6, iclass 32, count 2 2006.257.03:47:45.84#ibcon#end of sib2, iclass 32, count 2 2006.257.03:47:45.84#ibcon#*after write, iclass 32, count 2 2006.257.03:47:45.84#ibcon#*before return 0, iclass 32, count 2 2006.257.03:47:45.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:45.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:45.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.03:47:45.84#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:45.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:45.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:45.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:45.96#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:47:45.96#ibcon#first serial, iclass 32, count 0 2006.257.03:47:45.96#ibcon#enter sib2, iclass 32, count 0 2006.257.03:47:45.96#ibcon#flushed, iclass 32, count 0 2006.257.03:47:45.96#ibcon#about to write, iclass 32, count 0 2006.257.03:47:45.96#ibcon#wrote, iclass 32, count 0 2006.257.03:47:45.96#ibcon#about to read 3, iclass 32, count 0 2006.257.03:47:45.98#ibcon#read 3, iclass 32, count 0 2006.257.03:47:45.98#ibcon#about to read 4, iclass 32, count 0 2006.257.03:47:45.98#ibcon#read 4, iclass 32, count 0 2006.257.03:47:45.98#ibcon#about to read 5, iclass 32, count 0 2006.257.03:47:45.98#ibcon#read 5, iclass 32, count 0 2006.257.03:47:45.98#ibcon#about to read 6, iclass 32, count 0 2006.257.03:47:45.98#ibcon#read 6, iclass 32, count 0 2006.257.03:47:45.98#ibcon#end of sib2, iclass 32, count 0 2006.257.03:47:45.98#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:47:45.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:47:45.98#ibcon#[25=USB\r\n] 2006.257.03:47:45.98#ibcon#*before write, iclass 32, count 0 2006.257.03:47:45.98#ibcon#enter sib2, iclass 32, count 0 2006.257.03:47:45.98#ibcon#flushed, iclass 32, count 0 2006.257.03:47:45.98#ibcon#about to write, iclass 32, count 0 2006.257.03:47:45.98#ibcon#wrote, iclass 32, count 0 2006.257.03:47:45.98#ibcon#about to read 3, iclass 32, count 0 2006.257.03:47:46.01#ibcon#read 3, iclass 32, count 0 2006.257.03:47:46.01#ibcon#about to read 4, iclass 32, count 0 2006.257.03:47:46.01#ibcon#read 4, iclass 32, count 0 2006.257.03:47:46.01#ibcon#about to read 5, iclass 32, count 0 2006.257.03:47:46.01#ibcon#read 5, iclass 32, count 0 2006.257.03:47:46.01#ibcon#about to read 6, iclass 32, count 0 2006.257.03:47:46.01#ibcon#read 6, iclass 32, count 0 2006.257.03:47:46.01#ibcon#end of sib2, iclass 32, count 0 2006.257.03:47:46.01#ibcon#*after write, iclass 32, count 0 2006.257.03:47:46.01#ibcon#*before return 0, iclass 32, count 0 2006.257.03:47:46.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:46.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:46.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:47:46.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:47:46.01$vck44/valo=5,734.99 2006.257.03:47:46.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.03:47:46.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.03:47:46.01#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:46.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:46.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:46.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:46.01#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:47:46.01#ibcon#first serial, iclass 34, count 0 2006.257.03:47:46.01#ibcon#enter sib2, iclass 34, count 0 2006.257.03:47:46.01#ibcon#flushed, iclass 34, count 0 2006.257.03:47:46.01#ibcon#about to write, iclass 34, count 0 2006.257.03:47:46.01#ibcon#wrote, iclass 34, count 0 2006.257.03:47:46.01#ibcon#about to read 3, iclass 34, count 0 2006.257.03:47:46.03#ibcon#read 3, iclass 34, count 0 2006.257.03:47:46.03#ibcon#about to read 4, iclass 34, count 0 2006.257.03:47:46.03#ibcon#read 4, iclass 34, count 0 2006.257.03:47:46.03#ibcon#about to read 5, iclass 34, count 0 2006.257.03:47:46.03#ibcon#read 5, iclass 34, count 0 2006.257.03:47:46.03#ibcon#about to read 6, iclass 34, count 0 2006.257.03:47:46.03#ibcon#read 6, iclass 34, count 0 2006.257.03:47:46.03#ibcon#end of sib2, iclass 34, count 0 2006.257.03:47:46.03#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:47:46.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:47:46.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:47:46.03#ibcon#*before write, iclass 34, count 0 2006.257.03:47:46.03#ibcon#enter sib2, iclass 34, count 0 2006.257.03:47:46.03#ibcon#flushed, iclass 34, count 0 2006.257.03:47:46.03#ibcon#about to write, iclass 34, count 0 2006.257.03:47:46.03#ibcon#wrote, iclass 34, count 0 2006.257.03:47:46.03#ibcon#about to read 3, iclass 34, count 0 2006.257.03:47:46.07#ibcon#read 3, iclass 34, count 0 2006.257.03:47:46.07#ibcon#about to read 4, iclass 34, count 0 2006.257.03:47:46.07#ibcon#read 4, iclass 34, count 0 2006.257.03:47:46.07#ibcon#about to read 5, iclass 34, count 0 2006.257.03:47:46.07#ibcon#read 5, iclass 34, count 0 2006.257.03:47:46.07#ibcon#about to read 6, iclass 34, count 0 2006.257.03:47:46.07#ibcon#read 6, iclass 34, count 0 2006.257.03:47:46.07#ibcon#end of sib2, iclass 34, count 0 2006.257.03:47:46.07#ibcon#*after write, iclass 34, count 0 2006.257.03:47:46.07#ibcon#*before return 0, iclass 34, count 0 2006.257.03:47:46.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:46.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:46.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:47:46.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:47:46.07$vck44/va=5,4 2006.257.03:47:46.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.03:47:46.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.03:47:46.07#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:46.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:46.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:46.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:46.13#ibcon#enter wrdev, iclass 36, count 2 2006.257.03:47:46.13#ibcon#first serial, iclass 36, count 2 2006.257.03:47:46.13#ibcon#enter sib2, iclass 36, count 2 2006.257.03:47:46.13#ibcon#flushed, iclass 36, count 2 2006.257.03:47:46.13#ibcon#about to write, iclass 36, count 2 2006.257.03:47:46.13#ibcon#wrote, iclass 36, count 2 2006.257.03:47:46.13#ibcon#about to read 3, iclass 36, count 2 2006.257.03:47:46.15#ibcon#read 3, iclass 36, count 2 2006.257.03:47:46.15#ibcon#about to read 4, iclass 36, count 2 2006.257.03:47:46.15#ibcon#read 4, iclass 36, count 2 2006.257.03:47:46.15#ibcon#about to read 5, iclass 36, count 2 2006.257.03:47:46.15#ibcon#read 5, iclass 36, count 2 2006.257.03:47:46.15#ibcon#about to read 6, iclass 36, count 2 2006.257.03:47:46.15#ibcon#read 6, iclass 36, count 2 2006.257.03:47:46.15#ibcon#end of sib2, iclass 36, count 2 2006.257.03:47:46.15#ibcon#*mode == 0, iclass 36, count 2 2006.257.03:47:46.15#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.03:47:46.15#ibcon#[25=AT05-04\r\n] 2006.257.03:47:46.15#ibcon#*before write, iclass 36, count 2 2006.257.03:47:46.15#ibcon#enter sib2, iclass 36, count 2 2006.257.03:47:46.15#ibcon#flushed, iclass 36, count 2 2006.257.03:47:46.15#ibcon#about to write, iclass 36, count 2 2006.257.03:47:46.15#ibcon#wrote, iclass 36, count 2 2006.257.03:47:46.15#ibcon#about to read 3, iclass 36, count 2 2006.257.03:47:46.18#ibcon#read 3, iclass 36, count 2 2006.257.03:47:46.18#ibcon#about to read 4, iclass 36, count 2 2006.257.03:47:46.18#ibcon#read 4, iclass 36, count 2 2006.257.03:47:46.18#ibcon#about to read 5, iclass 36, count 2 2006.257.03:47:46.18#ibcon#read 5, iclass 36, count 2 2006.257.03:47:46.18#ibcon#about to read 6, iclass 36, count 2 2006.257.03:47:46.18#ibcon#read 6, iclass 36, count 2 2006.257.03:47:46.18#ibcon#end of sib2, iclass 36, count 2 2006.257.03:47:46.18#ibcon#*after write, iclass 36, count 2 2006.257.03:47:46.18#ibcon#*before return 0, iclass 36, count 2 2006.257.03:47:46.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:46.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:46.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.03:47:46.18#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:46.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:46.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:46.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:46.30#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:47:46.30#ibcon#first serial, iclass 36, count 0 2006.257.03:47:46.30#ibcon#enter sib2, iclass 36, count 0 2006.257.03:47:46.30#ibcon#flushed, iclass 36, count 0 2006.257.03:47:46.30#ibcon#about to write, iclass 36, count 0 2006.257.03:47:46.30#ibcon#wrote, iclass 36, count 0 2006.257.03:47:46.30#ibcon#about to read 3, iclass 36, count 0 2006.257.03:47:46.32#ibcon#read 3, iclass 36, count 0 2006.257.03:47:46.32#ibcon#about to read 4, iclass 36, count 0 2006.257.03:47:46.32#ibcon#read 4, iclass 36, count 0 2006.257.03:47:46.32#ibcon#about to read 5, iclass 36, count 0 2006.257.03:47:46.32#ibcon#read 5, iclass 36, count 0 2006.257.03:47:46.32#ibcon#about to read 6, iclass 36, count 0 2006.257.03:47:46.32#ibcon#read 6, iclass 36, count 0 2006.257.03:47:46.32#ibcon#end of sib2, iclass 36, count 0 2006.257.03:47:46.32#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:47:46.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:47:46.32#ibcon#[25=USB\r\n] 2006.257.03:47:46.32#ibcon#*before write, iclass 36, count 0 2006.257.03:47:46.32#ibcon#enter sib2, iclass 36, count 0 2006.257.03:47:46.32#ibcon#flushed, iclass 36, count 0 2006.257.03:47:46.32#ibcon#about to write, iclass 36, count 0 2006.257.03:47:46.32#ibcon#wrote, iclass 36, count 0 2006.257.03:47:46.32#ibcon#about to read 3, iclass 36, count 0 2006.257.03:47:46.35#ibcon#read 3, iclass 36, count 0 2006.257.03:47:46.35#ibcon#about to read 4, iclass 36, count 0 2006.257.03:47:46.35#ibcon#read 4, iclass 36, count 0 2006.257.03:47:46.35#ibcon#about to read 5, iclass 36, count 0 2006.257.03:47:46.35#ibcon#read 5, iclass 36, count 0 2006.257.03:47:46.35#ibcon#about to read 6, iclass 36, count 0 2006.257.03:47:46.35#ibcon#read 6, iclass 36, count 0 2006.257.03:47:46.35#ibcon#end of sib2, iclass 36, count 0 2006.257.03:47:46.35#ibcon#*after write, iclass 36, count 0 2006.257.03:47:46.35#ibcon#*before return 0, iclass 36, count 0 2006.257.03:47:46.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:46.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:46.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:47:46.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:47:46.35$vck44/valo=6,814.99 2006.257.03:47:46.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.03:47:46.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.03:47:46.35#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:46.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:46.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:46.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:46.35#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:47:46.35#ibcon#first serial, iclass 38, count 0 2006.257.03:47:46.35#ibcon#enter sib2, iclass 38, count 0 2006.257.03:47:46.35#ibcon#flushed, iclass 38, count 0 2006.257.03:47:46.35#ibcon#about to write, iclass 38, count 0 2006.257.03:47:46.35#ibcon#wrote, iclass 38, count 0 2006.257.03:47:46.35#ibcon#about to read 3, iclass 38, count 0 2006.257.03:47:46.37#ibcon#read 3, iclass 38, count 0 2006.257.03:47:46.37#ibcon#about to read 4, iclass 38, count 0 2006.257.03:47:46.37#ibcon#read 4, iclass 38, count 0 2006.257.03:47:46.37#ibcon#about to read 5, iclass 38, count 0 2006.257.03:47:46.37#ibcon#read 5, iclass 38, count 0 2006.257.03:47:46.37#ibcon#about to read 6, iclass 38, count 0 2006.257.03:47:46.37#ibcon#read 6, iclass 38, count 0 2006.257.03:47:46.37#ibcon#end of sib2, iclass 38, count 0 2006.257.03:47:46.37#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:47:46.37#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:47:46.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:47:46.37#ibcon#*before write, iclass 38, count 0 2006.257.03:47:46.37#ibcon#enter sib2, iclass 38, count 0 2006.257.03:47:46.37#ibcon#flushed, iclass 38, count 0 2006.257.03:47:46.37#ibcon#about to write, iclass 38, count 0 2006.257.03:47:46.37#ibcon#wrote, iclass 38, count 0 2006.257.03:47:46.37#ibcon#about to read 3, iclass 38, count 0 2006.257.03:47:46.41#ibcon#read 3, iclass 38, count 0 2006.257.03:47:46.41#ibcon#about to read 4, iclass 38, count 0 2006.257.03:47:46.41#ibcon#read 4, iclass 38, count 0 2006.257.03:47:46.41#ibcon#about to read 5, iclass 38, count 0 2006.257.03:47:46.41#ibcon#read 5, iclass 38, count 0 2006.257.03:47:46.41#ibcon#about to read 6, iclass 38, count 0 2006.257.03:47:46.41#ibcon#read 6, iclass 38, count 0 2006.257.03:47:46.41#ibcon#end of sib2, iclass 38, count 0 2006.257.03:47:46.41#ibcon#*after write, iclass 38, count 0 2006.257.03:47:46.41#ibcon#*before return 0, iclass 38, count 0 2006.257.03:47:46.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:46.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:46.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:47:46.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:47:46.41$vck44/va=6,4 2006.257.03:47:46.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.03:47:46.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.03:47:46.41#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:46.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:46.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:46.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:46.47#ibcon#enter wrdev, iclass 40, count 2 2006.257.03:47:46.47#ibcon#first serial, iclass 40, count 2 2006.257.03:47:46.47#ibcon#enter sib2, iclass 40, count 2 2006.257.03:47:46.47#ibcon#flushed, iclass 40, count 2 2006.257.03:47:46.47#ibcon#about to write, iclass 40, count 2 2006.257.03:47:46.47#ibcon#wrote, iclass 40, count 2 2006.257.03:47:46.47#ibcon#about to read 3, iclass 40, count 2 2006.257.03:47:46.49#ibcon#read 3, iclass 40, count 2 2006.257.03:47:46.49#ibcon#about to read 4, iclass 40, count 2 2006.257.03:47:46.49#ibcon#read 4, iclass 40, count 2 2006.257.03:47:46.49#ibcon#about to read 5, iclass 40, count 2 2006.257.03:47:46.49#ibcon#read 5, iclass 40, count 2 2006.257.03:47:46.49#ibcon#about to read 6, iclass 40, count 2 2006.257.03:47:46.49#ibcon#read 6, iclass 40, count 2 2006.257.03:47:46.49#ibcon#end of sib2, iclass 40, count 2 2006.257.03:47:46.49#ibcon#*mode == 0, iclass 40, count 2 2006.257.03:47:46.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.03:47:46.49#ibcon#[25=AT06-04\r\n] 2006.257.03:47:46.49#ibcon#*before write, iclass 40, count 2 2006.257.03:47:46.49#ibcon#enter sib2, iclass 40, count 2 2006.257.03:47:46.49#ibcon#flushed, iclass 40, count 2 2006.257.03:47:46.49#ibcon#about to write, iclass 40, count 2 2006.257.03:47:46.49#ibcon#wrote, iclass 40, count 2 2006.257.03:47:46.49#ibcon#about to read 3, iclass 40, count 2 2006.257.03:47:46.52#ibcon#read 3, iclass 40, count 2 2006.257.03:47:46.52#ibcon#about to read 4, iclass 40, count 2 2006.257.03:47:46.52#ibcon#read 4, iclass 40, count 2 2006.257.03:47:46.52#ibcon#about to read 5, iclass 40, count 2 2006.257.03:47:46.52#ibcon#read 5, iclass 40, count 2 2006.257.03:47:46.52#ibcon#about to read 6, iclass 40, count 2 2006.257.03:47:46.52#ibcon#read 6, iclass 40, count 2 2006.257.03:47:46.52#ibcon#end of sib2, iclass 40, count 2 2006.257.03:47:46.52#ibcon#*after write, iclass 40, count 2 2006.257.03:47:46.52#ibcon#*before return 0, iclass 40, count 2 2006.257.03:47:46.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:46.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:46.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.03:47:46.52#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:46.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:46.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:46.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:46.64#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:47:46.64#ibcon#first serial, iclass 40, count 0 2006.257.03:47:46.64#ibcon#enter sib2, iclass 40, count 0 2006.257.03:47:46.64#ibcon#flushed, iclass 40, count 0 2006.257.03:47:46.64#ibcon#about to write, iclass 40, count 0 2006.257.03:47:46.64#ibcon#wrote, iclass 40, count 0 2006.257.03:47:46.64#ibcon#about to read 3, iclass 40, count 0 2006.257.03:47:46.66#ibcon#read 3, iclass 40, count 0 2006.257.03:47:46.66#ibcon#about to read 4, iclass 40, count 0 2006.257.03:47:46.66#ibcon#read 4, iclass 40, count 0 2006.257.03:47:46.66#ibcon#about to read 5, iclass 40, count 0 2006.257.03:47:46.66#ibcon#read 5, iclass 40, count 0 2006.257.03:47:46.66#ibcon#about to read 6, iclass 40, count 0 2006.257.03:47:46.66#ibcon#read 6, iclass 40, count 0 2006.257.03:47:46.66#ibcon#end of sib2, iclass 40, count 0 2006.257.03:47:46.66#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:47:46.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:47:46.66#ibcon#[25=USB\r\n] 2006.257.03:47:46.66#ibcon#*before write, iclass 40, count 0 2006.257.03:47:46.66#ibcon#enter sib2, iclass 40, count 0 2006.257.03:47:46.66#ibcon#flushed, iclass 40, count 0 2006.257.03:47:46.66#ibcon#about to write, iclass 40, count 0 2006.257.03:47:46.66#ibcon#wrote, iclass 40, count 0 2006.257.03:47:46.66#ibcon#about to read 3, iclass 40, count 0 2006.257.03:47:46.69#ibcon#read 3, iclass 40, count 0 2006.257.03:47:46.69#ibcon#about to read 4, iclass 40, count 0 2006.257.03:47:46.69#ibcon#read 4, iclass 40, count 0 2006.257.03:47:46.69#ibcon#about to read 5, iclass 40, count 0 2006.257.03:47:46.69#ibcon#read 5, iclass 40, count 0 2006.257.03:47:46.69#ibcon#about to read 6, iclass 40, count 0 2006.257.03:47:46.69#ibcon#read 6, iclass 40, count 0 2006.257.03:47:46.69#ibcon#end of sib2, iclass 40, count 0 2006.257.03:47:46.69#ibcon#*after write, iclass 40, count 0 2006.257.03:47:46.69#ibcon#*before return 0, iclass 40, count 0 2006.257.03:47:46.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:46.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:46.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:47:46.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:47:46.69$vck44/valo=7,864.99 2006.257.03:47:46.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.03:47:46.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.03:47:46.69#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:46.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:46.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:46.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:46.69#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:47:46.69#ibcon#first serial, iclass 4, count 0 2006.257.03:47:46.69#ibcon#enter sib2, iclass 4, count 0 2006.257.03:47:46.69#ibcon#flushed, iclass 4, count 0 2006.257.03:47:46.69#ibcon#about to write, iclass 4, count 0 2006.257.03:47:46.69#ibcon#wrote, iclass 4, count 0 2006.257.03:47:46.69#ibcon#about to read 3, iclass 4, count 0 2006.257.03:47:46.71#ibcon#read 3, iclass 4, count 0 2006.257.03:47:46.71#ibcon#about to read 4, iclass 4, count 0 2006.257.03:47:46.71#ibcon#read 4, iclass 4, count 0 2006.257.03:47:46.71#ibcon#about to read 5, iclass 4, count 0 2006.257.03:47:46.71#ibcon#read 5, iclass 4, count 0 2006.257.03:47:46.71#ibcon#about to read 6, iclass 4, count 0 2006.257.03:47:46.71#ibcon#read 6, iclass 4, count 0 2006.257.03:47:46.71#ibcon#end of sib2, iclass 4, count 0 2006.257.03:47:46.71#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:47:46.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:47:46.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:47:46.71#ibcon#*before write, iclass 4, count 0 2006.257.03:47:46.71#ibcon#enter sib2, iclass 4, count 0 2006.257.03:47:46.71#ibcon#flushed, iclass 4, count 0 2006.257.03:47:46.71#ibcon#about to write, iclass 4, count 0 2006.257.03:47:46.71#ibcon#wrote, iclass 4, count 0 2006.257.03:47:46.71#ibcon#about to read 3, iclass 4, count 0 2006.257.03:47:46.75#ibcon#read 3, iclass 4, count 0 2006.257.03:47:46.75#ibcon#about to read 4, iclass 4, count 0 2006.257.03:47:46.75#ibcon#read 4, iclass 4, count 0 2006.257.03:47:46.75#ibcon#about to read 5, iclass 4, count 0 2006.257.03:47:46.75#ibcon#read 5, iclass 4, count 0 2006.257.03:47:46.75#ibcon#about to read 6, iclass 4, count 0 2006.257.03:47:46.75#ibcon#read 6, iclass 4, count 0 2006.257.03:47:46.75#ibcon#end of sib2, iclass 4, count 0 2006.257.03:47:46.75#ibcon#*after write, iclass 4, count 0 2006.257.03:47:46.75#ibcon#*before return 0, iclass 4, count 0 2006.257.03:47:46.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:46.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:46.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:47:46.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:47:46.75$vck44/va=7,4 2006.257.03:47:46.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.03:47:46.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.03:47:46.75#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:46.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:46.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:46.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:46.81#ibcon#enter wrdev, iclass 6, count 2 2006.257.03:47:46.81#ibcon#first serial, iclass 6, count 2 2006.257.03:47:46.81#ibcon#enter sib2, iclass 6, count 2 2006.257.03:47:46.81#ibcon#flushed, iclass 6, count 2 2006.257.03:47:46.81#ibcon#about to write, iclass 6, count 2 2006.257.03:47:46.81#ibcon#wrote, iclass 6, count 2 2006.257.03:47:46.81#ibcon#about to read 3, iclass 6, count 2 2006.257.03:47:46.83#ibcon#read 3, iclass 6, count 2 2006.257.03:47:46.83#ibcon#about to read 4, iclass 6, count 2 2006.257.03:47:46.83#ibcon#read 4, iclass 6, count 2 2006.257.03:47:46.83#ibcon#about to read 5, iclass 6, count 2 2006.257.03:47:46.83#ibcon#read 5, iclass 6, count 2 2006.257.03:47:46.83#ibcon#about to read 6, iclass 6, count 2 2006.257.03:47:46.83#ibcon#read 6, iclass 6, count 2 2006.257.03:47:46.83#ibcon#end of sib2, iclass 6, count 2 2006.257.03:47:46.83#ibcon#*mode == 0, iclass 6, count 2 2006.257.03:47:46.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.03:47:46.83#ibcon#[25=AT07-04\r\n] 2006.257.03:47:46.83#ibcon#*before write, iclass 6, count 2 2006.257.03:47:46.83#ibcon#enter sib2, iclass 6, count 2 2006.257.03:47:46.83#ibcon#flushed, iclass 6, count 2 2006.257.03:47:46.83#ibcon#about to write, iclass 6, count 2 2006.257.03:47:46.83#ibcon#wrote, iclass 6, count 2 2006.257.03:47:46.83#ibcon#about to read 3, iclass 6, count 2 2006.257.03:47:46.86#ibcon#read 3, iclass 6, count 2 2006.257.03:47:46.86#ibcon#about to read 4, iclass 6, count 2 2006.257.03:47:46.86#ibcon#read 4, iclass 6, count 2 2006.257.03:47:46.86#ibcon#about to read 5, iclass 6, count 2 2006.257.03:47:46.86#ibcon#read 5, iclass 6, count 2 2006.257.03:47:46.86#ibcon#about to read 6, iclass 6, count 2 2006.257.03:47:46.86#ibcon#read 6, iclass 6, count 2 2006.257.03:47:46.86#ibcon#end of sib2, iclass 6, count 2 2006.257.03:47:46.86#ibcon#*after write, iclass 6, count 2 2006.257.03:47:46.86#ibcon#*before return 0, iclass 6, count 2 2006.257.03:47:46.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:46.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:46.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.03:47:46.86#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:46.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:46.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:46.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:46.98#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:47:46.98#ibcon#first serial, iclass 6, count 0 2006.257.03:47:46.98#ibcon#enter sib2, iclass 6, count 0 2006.257.03:47:46.98#ibcon#flushed, iclass 6, count 0 2006.257.03:47:46.98#ibcon#about to write, iclass 6, count 0 2006.257.03:47:46.98#ibcon#wrote, iclass 6, count 0 2006.257.03:47:46.98#ibcon#about to read 3, iclass 6, count 0 2006.257.03:47:47.00#ibcon#read 3, iclass 6, count 0 2006.257.03:47:47.00#ibcon#about to read 4, iclass 6, count 0 2006.257.03:47:47.00#ibcon#read 4, iclass 6, count 0 2006.257.03:47:47.00#ibcon#about to read 5, iclass 6, count 0 2006.257.03:47:47.00#ibcon#read 5, iclass 6, count 0 2006.257.03:47:47.00#ibcon#about to read 6, iclass 6, count 0 2006.257.03:47:47.00#ibcon#read 6, iclass 6, count 0 2006.257.03:47:47.00#ibcon#end of sib2, iclass 6, count 0 2006.257.03:47:47.00#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:47:47.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:47:47.00#ibcon#[25=USB\r\n] 2006.257.03:47:47.00#ibcon#*before write, iclass 6, count 0 2006.257.03:47:47.00#ibcon#enter sib2, iclass 6, count 0 2006.257.03:47:47.00#ibcon#flushed, iclass 6, count 0 2006.257.03:47:47.00#ibcon#about to write, iclass 6, count 0 2006.257.03:47:47.00#ibcon#wrote, iclass 6, count 0 2006.257.03:47:47.00#ibcon#about to read 3, iclass 6, count 0 2006.257.03:47:47.03#ibcon#read 3, iclass 6, count 0 2006.257.03:47:47.03#ibcon#about to read 4, iclass 6, count 0 2006.257.03:47:47.03#ibcon#read 4, iclass 6, count 0 2006.257.03:47:47.03#ibcon#about to read 5, iclass 6, count 0 2006.257.03:47:47.03#ibcon#read 5, iclass 6, count 0 2006.257.03:47:47.03#ibcon#about to read 6, iclass 6, count 0 2006.257.03:47:47.03#ibcon#read 6, iclass 6, count 0 2006.257.03:47:47.03#ibcon#end of sib2, iclass 6, count 0 2006.257.03:47:47.03#ibcon#*after write, iclass 6, count 0 2006.257.03:47:47.03#ibcon#*before return 0, iclass 6, count 0 2006.257.03:47:47.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:47.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:47.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:47:47.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:47:47.03$vck44/valo=8,884.99 2006.257.03:47:47.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.03:47:47.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.03:47:47.03#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:47.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:47.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:47.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:47.03#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:47:47.03#ibcon#first serial, iclass 10, count 0 2006.257.03:47:47.03#ibcon#enter sib2, iclass 10, count 0 2006.257.03:47:47.03#ibcon#flushed, iclass 10, count 0 2006.257.03:47:47.03#ibcon#about to write, iclass 10, count 0 2006.257.03:47:47.03#ibcon#wrote, iclass 10, count 0 2006.257.03:47:47.03#ibcon#about to read 3, iclass 10, count 0 2006.257.03:47:47.05#ibcon#read 3, iclass 10, count 0 2006.257.03:47:47.05#ibcon#about to read 4, iclass 10, count 0 2006.257.03:47:47.05#ibcon#read 4, iclass 10, count 0 2006.257.03:47:47.05#ibcon#about to read 5, iclass 10, count 0 2006.257.03:47:47.05#ibcon#read 5, iclass 10, count 0 2006.257.03:47:47.05#ibcon#about to read 6, iclass 10, count 0 2006.257.03:47:47.05#ibcon#read 6, iclass 10, count 0 2006.257.03:47:47.05#ibcon#end of sib2, iclass 10, count 0 2006.257.03:47:47.05#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:47:47.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:47:47.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:47:47.05#ibcon#*before write, iclass 10, count 0 2006.257.03:47:47.05#ibcon#enter sib2, iclass 10, count 0 2006.257.03:47:47.05#ibcon#flushed, iclass 10, count 0 2006.257.03:47:47.05#ibcon#about to write, iclass 10, count 0 2006.257.03:47:47.05#ibcon#wrote, iclass 10, count 0 2006.257.03:47:47.05#ibcon#about to read 3, iclass 10, count 0 2006.257.03:47:47.09#ibcon#read 3, iclass 10, count 0 2006.257.03:47:47.09#ibcon#about to read 4, iclass 10, count 0 2006.257.03:47:47.09#ibcon#read 4, iclass 10, count 0 2006.257.03:47:47.09#ibcon#about to read 5, iclass 10, count 0 2006.257.03:47:47.09#ibcon#read 5, iclass 10, count 0 2006.257.03:47:47.09#ibcon#about to read 6, iclass 10, count 0 2006.257.03:47:47.09#ibcon#read 6, iclass 10, count 0 2006.257.03:47:47.09#ibcon#end of sib2, iclass 10, count 0 2006.257.03:47:47.09#ibcon#*after write, iclass 10, count 0 2006.257.03:47:47.09#ibcon#*before return 0, iclass 10, count 0 2006.257.03:47:47.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:47.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:47.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:47:47.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:47:47.09$vck44/va=8,4 2006.257.03:47:47.09#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.03:47:47.09#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.03:47:47.09#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:47.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:47:47.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:47:47.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:47:47.15#ibcon#enter wrdev, iclass 12, count 2 2006.257.03:47:47.15#ibcon#first serial, iclass 12, count 2 2006.257.03:47:47.15#ibcon#enter sib2, iclass 12, count 2 2006.257.03:47:47.15#ibcon#flushed, iclass 12, count 2 2006.257.03:47:47.15#ibcon#about to write, iclass 12, count 2 2006.257.03:47:47.15#ibcon#wrote, iclass 12, count 2 2006.257.03:47:47.15#ibcon#about to read 3, iclass 12, count 2 2006.257.03:47:47.17#ibcon#read 3, iclass 12, count 2 2006.257.03:47:47.17#ibcon#about to read 4, iclass 12, count 2 2006.257.03:47:47.17#ibcon#read 4, iclass 12, count 2 2006.257.03:47:47.17#ibcon#about to read 5, iclass 12, count 2 2006.257.03:47:47.17#ibcon#read 5, iclass 12, count 2 2006.257.03:47:47.17#ibcon#about to read 6, iclass 12, count 2 2006.257.03:47:47.17#ibcon#read 6, iclass 12, count 2 2006.257.03:47:47.17#ibcon#end of sib2, iclass 12, count 2 2006.257.03:47:47.17#ibcon#*mode == 0, iclass 12, count 2 2006.257.03:47:47.17#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.03:47:47.17#ibcon#[25=AT08-04\r\n] 2006.257.03:47:47.17#ibcon#*before write, iclass 12, count 2 2006.257.03:47:47.17#ibcon#enter sib2, iclass 12, count 2 2006.257.03:47:47.17#ibcon#flushed, iclass 12, count 2 2006.257.03:47:47.17#ibcon#about to write, iclass 12, count 2 2006.257.03:47:47.17#ibcon#wrote, iclass 12, count 2 2006.257.03:47:47.17#ibcon#about to read 3, iclass 12, count 2 2006.257.03:47:47.20#ibcon#read 3, iclass 12, count 2 2006.257.03:47:47.20#ibcon#about to read 4, iclass 12, count 2 2006.257.03:47:47.20#ibcon#read 4, iclass 12, count 2 2006.257.03:47:47.20#ibcon#about to read 5, iclass 12, count 2 2006.257.03:47:47.20#ibcon#read 5, iclass 12, count 2 2006.257.03:47:47.20#ibcon#about to read 6, iclass 12, count 2 2006.257.03:47:47.20#ibcon#read 6, iclass 12, count 2 2006.257.03:47:47.20#ibcon#end of sib2, iclass 12, count 2 2006.257.03:47:47.20#ibcon#*after write, iclass 12, count 2 2006.257.03:47:47.20#ibcon#*before return 0, iclass 12, count 2 2006.257.03:47:47.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:47:47.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:47:47.20#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.03:47:47.20#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:47.20#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:47:47.32#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:47:47.32#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:47:47.32#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:47:47.32#ibcon#first serial, iclass 12, count 0 2006.257.03:47:47.32#ibcon#enter sib2, iclass 12, count 0 2006.257.03:47:47.32#ibcon#flushed, iclass 12, count 0 2006.257.03:47:47.32#ibcon#about to write, iclass 12, count 0 2006.257.03:47:47.32#ibcon#wrote, iclass 12, count 0 2006.257.03:47:47.32#ibcon#about to read 3, iclass 12, count 0 2006.257.03:47:47.34#ibcon#read 3, iclass 12, count 0 2006.257.03:47:47.34#ibcon#about to read 4, iclass 12, count 0 2006.257.03:47:47.34#ibcon#read 4, iclass 12, count 0 2006.257.03:47:47.34#ibcon#about to read 5, iclass 12, count 0 2006.257.03:47:47.34#ibcon#read 5, iclass 12, count 0 2006.257.03:47:47.34#ibcon#about to read 6, iclass 12, count 0 2006.257.03:47:47.34#ibcon#read 6, iclass 12, count 0 2006.257.03:47:47.34#ibcon#end of sib2, iclass 12, count 0 2006.257.03:47:47.34#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:47:47.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:47:47.34#ibcon#[25=USB\r\n] 2006.257.03:47:47.34#ibcon#*before write, iclass 12, count 0 2006.257.03:47:47.34#ibcon#enter sib2, iclass 12, count 0 2006.257.03:47:47.34#ibcon#flushed, iclass 12, count 0 2006.257.03:47:47.34#ibcon#about to write, iclass 12, count 0 2006.257.03:47:47.34#ibcon#wrote, iclass 12, count 0 2006.257.03:47:47.34#ibcon#about to read 3, iclass 12, count 0 2006.257.03:47:47.37#ibcon#read 3, iclass 12, count 0 2006.257.03:47:47.37#ibcon#about to read 4, iclass 12, count 0 2006.257.03:47:47.37#ibcon#read 4, iclass 12, count 0 2006.257.03:47:47.37#ibcon#about to read 5, iclass 12, count 0 2006.257.03:47:47.37#ibcon#read 5, iclass 12, count 0 2006.257.03:47:47.37#ibcon#about to read 6, iclass 12, count 0 2006.257.03:47:47.37#ibcon#read 6, iclass 12, count 0 2006.257.03:47:47.37#ibcon#end of sib2, iclass 12, count 0 2006.257.03:47:47.37#ibcon#*after write, iclass 12, count 0 2006.257.03:47:47.37#ibcon#*before return 0, iclass 12, count 0 2006.257.03:47:47.37#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:47:47.37#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:47:47.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:47:47.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:47:47.37$vck44/vblo=1,629.99 2006.257.03:47:47.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.03:47:47.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.03:47:47.37#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:47.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:47:47.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:47:47.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:47:47.37#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:47:47.37#ibcon#first serial, iclass 14, count 0 2006.257.03:47:47.37#ibcon#enter sib2, iclass 14, count 0 2006.257.03:47:47.37#ibcon#flushed, iclass 14, count 0 2006.257.03:47:47.37#ibcon#about to write, iclass 14, count 0 2006.257.03:47:47.37#ibcon#wrote, iclass 14, count 0 2006.257.03:47:47.37#ibcon#about to read 3, iclass 14, count 0 2006.257.03:47:47.39#ibcon#read 3, iclass 14, count 0 2006.257.03:47:47.39#ibcon#about to read 4, iclass 14, count 0 2006.257.03:47:47.39#ibcon#read 4, iclass 14, count 0 2006.257.03:47:47.39#ibcon#about to read 5, iclass 14, count 0 2006.257.03:47:47.39#ibcon#read 5, iclass 14, count 0 2006.257.03:47:47.39#ibcon#about to read 6, iclass 14, count 0 2006.257.03:47:47.39#ibcon#read 6, iclass 14, count 0 2006.257.03:47:47.39#ibcon#end of sib2, iclass 14, count 0 2006.257.03:47:47.39#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:47:47.39#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:47:47.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:47:47.39#ibcon#*before write, iclass 14, count 0 2006.257.03:47:47.39#ibcon#enter sib2, iclass 14, count 0 2006.257.03:47:47.39#ibcon#flushed, iclass 14, count 0 2006.257.03:47:47.39#ibcon#about to write, iclass 14, count 0 2006.257.03:47:47.39#ibcon#wrote, iclass 14, count 0 2006.257.03:47:47.39#ibcon#about to read 3, iclass 14, count 0 2006.257.03:47:47.43#ibcon#read 3, iclass 14, count 0 2006.257.03:47:47.43#ibcon#about to read 4, iclass 14, count 0 2006.257.03:47:47.43#ibcon#read 4, iclass 14, count 0 2006.257.03:47:47.43#ibcon#about to read 5, iclass 14, count 0 2006.257.03:47:47.43#ibcon#read 5, iclass 14, count 0 2006.257.03:47:47.43#ibcon#about to read 6, iclass 14, count 0 2006.257.03:47:47.43#ibcon#read 6, iclass 14, count 0 2006.257.03:47:47.43#ibcon#end of sib2, iclass 14, count 0 2006.257.03:47:47.43#ibcon#*after write, iclass 14, count 0 2006.257.03:47:47.43#ibcon#*before return 0, iclass 14, count 0 2006.257.03:47:47.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:47:47.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:47:47.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:47:47.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:47:47.43$vck44/vb=1,4 2006.257.03:47:47.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.03:47:47.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.03:47:47.43#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:47.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:47:47.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:47:47.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:47:47.43#ibcon#enter wrdev, iclass 16, count 2 2006.257.03:47:47.43#ibcon#first serial, iclass 16, count 2 2006.257.03:47:47.43#ibcon#enter sib2, iclass 16, count 2 2006.257.03:47:47.43#ibcon#flushed, iclass 16, count 2 2006.257.03:47:47.43#ibcon#about to write, iclass 16, count 2 2006.257.03:47:47.43#ibcon#wrote, iclass 16, count 2 2006.257.03:47:47.43#ibcon#about to read 3, iclass 16, count 2 2006.257.03:47:47.45#ibcon#read 3, iclass 16, count 2 2006.257.03:47:47.45#ibcon#about to read 4, iclass 16, count 2 2006.257.03:47:47.45#ibcon#read 4, iclass 16, count 2 2006.257.03:47:47.45#ibcon#about to read 5, iclass 16, count 2 2006.257.03:47:47.45#ibcon#read 5, iclass 16, count 2 2006.257.03:47:47.45#ibcon#about to read 6, iclass 16, count 2 2006.257.03:47:47.45#ibcon#read 6, iclass 16, count 2 2006.257.03:47:47.45#ibcon#end of sib2, iclass 16, count 2 2006.257.03:47:47.45#ibcon#*mode == 0, iclass 16, count 2 2006.257.03:47:47.45#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.03:47:47.45#ibcon#[27=AT01-04\r\n] 2006.257.03:47:47.45#ibcon#*before write, iclass 16, count 2 2006.257.03:47:47.45#ibcon#enter sib2, iclass 16, count 2 2006.257.03:47:47.45#ibcon#flushed, iclass 16, count 2 2006.257.03:47:47.45#ibcon#about to write, iclass 16, count 2 2006.257.03:47:47.45#ibcon#wrote, iclass 16, count 2 2006.257.03:47:47.45#ibcon#about to read 3, iclass 16, count 2 2006.257.03:47:47.48#ibcon#read 3, iclass 16, count 2 2006.257.03:47:47.48#ibcon#about to read 4, iclass 16, count 2 2006.257.03:47:47.48#ibcon#read 4, iclass 16, count 2 2006.257.03:47:47.48#ibcon#about to read 5, iclass 16, count 2 2006.257.03:47:47.48#ibcon#read 5, iclass 16, count 2 2006.257.03:47:47.48#ibcon#about to read 6, iclass 16, count 2 2006.257.03:47:47.48#ibcon#read 6, iclass 16, count 2 2006.257.03:47:47.48#ibcon#end of sib2, iclass 16, count 2 2006.257.03:47:47.48#ibcon#*after write, iclass 16, count 2 2006.257.03:47:47.48#ibcon#*before return 0, iclass 16, count 2 2006.257.03:47:47.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:47:47.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:47:47.48#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.03:47:47.48#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:47.48#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:47:47.60#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:47:47.60#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:47:47.60#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:47:47.60#ibcon#first serial, iclass 16, count 0 2006.257.03:47:47.60#ibcon#enter sib2, iclass 16, count 0 2006.257.03:47:47.60#ibcon#flushed, iclass 16, count 0 2006.257.03:47:47.60#ibcon#about to write, iclass 16, count 0 2006.257.03:47:47.60#ibcon#wrote, iclass 16, count 0 2006.257.03:47:47.60#ibcon#about to read 3, iclass 16, count 0 2006.257.03:47:47.62#ibcon#read 3, iclass 16, count 0 2006.257.03:47:47.62#ibcon#about to read 4, iclass 16, count 0 2006.257.03:47:47.62#ibcon#read 4, iclass 16, count 0 2006.257.03:47:47.62#ibcon#about to read 5, iclass 16, count 0 2006.257.03:47:47.62#ibcon#read 5, iclass 16, count 0 2006.257.03:47:47.62#ibcon#about to read 6, iclass 16, count 0 2006.257.03:47:47.62#ibcon#read 6, iclass 16, count 0 2006.257.03:47:47.62#ibcon#end of sib2, iclass 16, count 0 2006.257.03:47:47.62#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:47:47.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:47:47.62#ibcon#[27=USB\r\n] 2006.257.03:47:47.62#ibcon#*before write, iclass 16, count 0 2006.257.03:47:47.62#ibcon#enter sib2, iclass 16, count 0 2006.257.03:47:47.62#ibcon#flushed, iclass 16, count 0 2006.257.03:47:47.62#ibcon#about to write, iclass 16, count 0 2006.257.03:47:47.62#ibcon#wrote, iclass 16, count 0 2006.257.03:47:47.62#ibcon#about to read 3, iclass 16, count 0 2006.257.03:47:47.65#ibcon#read 3, iclass 16, count 0 2006.257.03:47:47.65#ibcon#about to read 4, iclass 16, count 0 2006.257.03:47:47.65#ibcon#read 4, iclass 16, count 0 2006.257.03:47:47.65#ibcon#about to read 5, iclass 16, count 0 2006.257.03:47:47.65#ibcon#read 5, iclass 16, count 0 2006.257.03:47:47.65#ibcon#about to read 6, iclass 16, count 0 2006.257.03:47:47.65#ibcon#read 6, iclass 16, count 0 2006.257.03:47:47.65#ibcon#end of sib2, iclass 16, count 0 2006.257.03:47:47.65#ibcon#*after write, iclass 16, count 0 2006.257.03:47:47.65#ibcon#*before return 0, iclass 16, count 0 2006.257.03:47:47.65#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:47:47.65#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:47:47.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:47:47.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:47:47.65$vck44/vblo=2,634.99 2006.257.03:47:47.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.03:47:47.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.03:47:47.65#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:47.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:47.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:47.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:47.65#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:47:47.65#ibcon#first serial, iclass 18, count 0 2006.257.03:47:47.65#ibcon#enter sib2, iclass 18, count 0 2006.257.03:47:47.65#ibcon#flushed, iclass 18, count 0 2006.257.03:47:47.65#ibcon#about to write, iclass 18, count 0 2006.257.03:47:47.65#ibcon#wrote, iclass 18, count 0 2006.257.03:47:47.65#ibcon#about to read 3, iclass 18, count 0 2006.257.03:47:47.67#ibcon#read 3, iclass 18, count 0 2006.257.03:47:47.67#ibcon#about to read 4, iclass 18, count 0 2006.257.03:47:47.67#ibcon#read 4, iclass 18, count 0 2006.257.03:47:47.67#ibcon#about to read 5, iclass 18, count 0 2006.257.03:47:47.67#ibcon#read 5, iclass 18, count 0 2006.257.03:47:47.67#ibcon#about to read 6, iclass 18, count 0 2006.257.03:47:47.67#ibcon#read 6, iclass 18, count 0 2006.257.03:47:47.67#ibcon#end of sib2, iclass 18, count 0 2006.257.03:47:47.67#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:47:47.67#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:47:47.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:47:47.67#ibcon#*before write, iclass 18, count 0 2006.257.03:47:47.67#ibcon#enter sib2, iclass 18, count 0 2006.257.03:47:47.67#ibcon#flushed, iclass 18, count 0 2006.257.03:47:47.67#ibcon#about to write, iclass 18, count 0 2006.257.03:47:47.67#ibcon#wrote, iclass 18, count 0 2006.257.03:47:47.67#ibcon#about to read 3, iclass 18, count 0 2006.257.03:47:47.71#ibcon#read 3, iclass 18, count 0 2006.257.03:47:47.71#ibcon#about to read 4, iclass 18, count 0 2006.257.03:47:47.71#ibcon#read 4, iclass 18, count 0 2006.257.03:47:47.71#ibcon#about to read 5, iclass 18, count 0 2006.257.03:47:47.71#ibcon#read 5, iclass 18, count 0 2006.257.03:47:47.71#ibcon#about to read 6, iclass 18, count 0 2006.257.03:47:47.71#ibcon#read 6, iclass 18, count 0 2006.257.03:47:47.71#ibcon#end of sib2, iclass 18, count 0 2006.257.03:47:47.71#ibcon#*after write, iclass 18, count 0 2006.257.03:47:47.71#ibcon#*before return 0, iclass 18, count 0 2006.257.03:47:47.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:47.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:47:47.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:47:47.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:47:47.71$vck44/vb=2,5 2006.257.03:47:47.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.03:47:47.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.03:47:47.71#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:47.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:47.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:47.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:47.77#ibcon#enter wrdev, iclass 20, count 2 2006.257.03:47:47.77#ibcon#first serial, iclass 20, count 2 2006.257.03:47:47.77#ibcon#enter sib2, iclass 20, count 2 2006.257.03:47:47.77#ibcon#flushed, iclass 20, count 2 2006.257.03:47:47.77#ibcon#about to write, iclass 20, count 2 2006.257.03:47:47.77#ibcon#wrote, iclass 20, count 2 2006.257.03:47:47.77#ibcon#about to read 3, iclass 20, count 2 2006.257.03:47:47.79#ibcon#read 3, iclass 20, count 2 2006.257.03:47:47.79#ibcon#about to read 4, iclass 20, count 2 2006.257.03:47:47.79#ibcon#read 4, iclass 20, count 2 2006.257.03:47:47.79#ibcon#about to read 5, iclass 20, count 2 2006.257.03:47:47.79#ibcon#read 5, iclass 20, count 2 2006.257.03:47:47.79#ibcon#about to read 6, iclass 20, count 2 2006.257.03:47:47.79#ibcon#read 6, iclass 20, count 2 2006.257.03:47:47.79#ibcon#end of sib2, iclass 20, count 2 2006.257.03:47:47.79#ibcon#*mode == 0, iclass 20, count 2 2006.257.03:47:47.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.03:47:47.79#ibcon#[27=AT02-05\r\n] 2006.257.03:47:47.79#ibcon#*before write, iclass 20, count 2 2006.257.03:47:47.79#ibcon#enter sib2, iclass 20, count 2 2006.257.03:47:47.79#ibcon#flushed, iclass 20, count 2 2006.257.03:47:47.79#ibcon#about to write, iclass 20, count 2 2006.257.03:47:47.79#ibcon#wrote, iclass 20, count 2 2006.257.03:47:47.79#ibcon#about to read 3, iclass 20, count 2 2006.257.03:47:47.82#ibcon#read 3, iclass 20, count 2 2006.257.03:47:47.82#ibcon#about to read 4, iclass 20, count 2 2006.257.03:47:47.82#ibcon#read 4, iclass 20, count 2 2006.257.03:47:47.82#ibcon#about to read 5, iclass 20, count 2 2006.257.03:47:47.82#ibcon#read 5, iclass 20, count 2 2006.257.03:47:47.82#ibcon#about to read 6, iclass 20, count 2 2006.257.03:47:47.82#ibcon#read 6, iclass 20, count 2 2006.257.03:47:47.82#ibcon#end of sib2, iclass 20, count 2 2006.257.03:47:47.82#ibcon#*after write, iclass 20, count 2 2006.257.03:47:47.82#ibcon#*before return 0, iclass 20, count 2 2006.257.03:47:47.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:47.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:47:47.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.03:47:47.82#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:47.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:47.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:47.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:47.94#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:47:47.94#ibcon#first serial, iclass 20, count 0 2006.257.03:47:47.94#ibcon#enter sib2, iclass 20, count 0 2006.257.03:47:47.94#ibcon#flushed, iclass 20, count 0 2006.257.03:47:47.94#ibcon#about to write, iclass 20, count 0 2006.257.03:47:47.94#ibcon#wrote, iclass 20, count 0 2006.257.03:47:47.94#ibcon#about to read 3, iclass 20, count 0 2006.257.03:47:47.96#ibcon#read 3, iclass 20, count 0 2006.257.03:47:47.96#ibcon#about to read 4, iclass 20, count 0 2006.257.03:47:47.96#ibcon#read 4, iclass 20, count 0 2006.257.03:47:47.96#ibcon#about to read 5, iclass 20, count 0 2006.257.03:47:47.96#ibcon#read 5, iclass 20, count 0 2006.257.03:47:47.96#ibcon#about to read 6, iclass 20, count 0 2006.257.03:47:47.96#ibcon#read 6, iclass 20, count 0 2006.257.03:47:47.96#ibcon#end of sib2, iclass 20, count 0 2006.257.03:47:47.96#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:47:47.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:47:47.96#ibcon#[27=USB\r\n] 2006.257.03:47:47.96#ibcon#*before write, iclass 20, count 0 2006.257.03:47:47.96#ibcon#enter sib2, iclass 20, count 0 2006.257.03:47:47.96#ibcon#flushed, iclass 20, count 0 2006.257.03:47:47.96#ibcon#about to write, iclass 20, count 0 2006.257.03:47:47.96#ibcon#wrote, iclass 20, count 0 2006.257.03:47:47.96#ibcon#about to read 3, iclass 20, count 0 2006.257.03:47:47.99#ibcon#read 3, iclass 20, count 0 2006.257.03:47:47.99#ibcon#about to read 4, iclass 20, count 0 2006.257.03:47:47.99#ibcon#read 4, iclass 20, count 0 2006.257.03:47:47.99#ibcon#about to read 5, iclass 20, count 0 2006.257.03:47:47.99#ibcon#read 5, iclass 20, count 0 2006.257.03:47:47.99#ibcon#about to read 6, iclass 20, count 0 2006.257.03:47:47.99#ibcon#read 6, iclass 20, count 0 2006.257.03:47:47.99#ibcon#end of sib2, iclass 20, count 0 2006.257.03:47:47.99#ibcon#*after write, iclass 20, count 0 2006.257.03:47:47.99#ibcon#*before return 0, iclass 20, count 0 2006.257.03:47:47.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:47.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:47:47.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:47:47.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:47:47.99$vck44/vblo=3,649.99 2006.257.03:47:47.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.03:47:47.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.03:47:47.99#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:47.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:47.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:47.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:47.99#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:47:47.99#ibcon#first serial, iclass 22, count 0 2006.257.03:47:47.99#ibcon#enter sib2, iclass 22, count 0 2006.257.03:47:47.99#ibcon#flushed, iclass 22, count 0 2006.257.03:47:47.99#ibcon#about to write, iclass 22, count 0 2006.257.03:47:47.99#ibcon#wrote, iclass 22, count 0 2006.257.03:47:47.99#ibcon#about to read 3, iclass 22, count 0 2006.257.03:47:48.01#ibcon#read 3, iclass 22, count 0 2006.257.03:47:48.01#ibcon#about to read 4, iclass 22, count 0 2006.257.03:47:48.01#ibcon#read 4, iclass 22, count 0 2006.257.03:47:48.01#ibcon#about to read 5, iclass 22, count 0 2006.257.03:47:48.01#ibcon#read 5, iclass 22, count 0 2006.257.03:47:48.01#ibcon#about to read 6, iclass 22, count 0 2006.257.03:47:48.01#ibcon#read 6, iclass 22, count 0 2006.257.03:47:48.01#ibcon#end of sib2, iclass 22, count 0 2006.257.03:47:48.01#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:47:48.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:47:48.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:47:48.01#ibcon#*before write, iclass 22, count 0 2006.257.03:47:48.01#ibcon#enter sib2, iclass 22, count 0 2006.257.03:47:48.01#ibcon#flushed, iclass 22, count 0 2006.257.03:47:48.01#ibcon#about to write, iclass 22, count 0 2006.257.03:47:48.01#ibcon#wrote, iclass 22, count 0 2006.257.03:47:48.01#ibcon#about to read 3, iclass 22, count 0 2006.257.03:47:48.05#ibcon#read 3, iclass 22, count 0 2006.257.03:47:48.05#ibcon#about to read 4, iclass 22, count 0 2006.257.03:47:48.05#ibcon#read 4, iclass 22, count 0 2006.257.03:47:48.05#ibcon#about to read 5, iclass 22, count 0 2006.257.03:47:48.05#ibcon#read 5, iclass 22, count 0 2006.257.03:47:48.05#ibcon#about to read 6, iclass 22, count 0 2006.257.03:47:48.05#ibcon#read 6, iclass 22, count 0 2006.257.03:47:48.05#ibcon#end of sib2, iclass 22, count 0 2006.257.03:47:48.05#ibcon#*after write, iclass 22, count 0 2006.257.03:47:48.05#ibcon#*before return 0, iclass 22, count 0 2006.257.03:47:48.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:48.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:47:48.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:47:48.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:47:48.05$vck44/vb=3,4 2006.257.03:47:48.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.03:47:48.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.03:47:48.05#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:48.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:48.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:48.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:48.11#ibcon#enter wrdev, iclass 24, count 2 2006.257.03:47:48.11#ibcon#first serial, iclass 24, count 2 2006.257.03:47:48.11#ibcon#enter sib2, iclass 24, count 2 2006.257.03:47:48.11#ibcon#flushed, iclass 24, count 2 2006.257.03:47:48.11#ibcon#about to write, iclass 24, count 2 2006.257.03:47:48.11#ibcon#wrote, iclass 24, count 2 2006.257.03:47:48.11#ibcon#about to read 3, iclass 24, count 2 2006.257.03:47:48.13#ibcon#read 3, iclass 24, count 2 2006.257.03:47:48.13#ibcon#about to read 4, iclass 24, count 2 2006.257.03:47:48.13#ibcon#read 4, iclass 24, count 2 2006.257.03:47:48.13#ibcon#about to read 5, iclass 24, count 2 2006.257.03:47:48.13#ibcon#read 5, iclass 24, count 2 2006.257.03:47:48.13#ibcon#about to read 6, iclass 24, count 2 2006.257.03:47:48.13#ibcon#read 6, iclass 24, count 2 2006.257.03:47:48.13#ibcon#end of sib2, iclass 24, count 2 2006.257.03:47:48.13#ibcon#*mode == 0, iclass 24, count 2 2006.257.03:47:48.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.03:47:48.13#ibcon#[27=AT03-04\r\n] 2006.257.03:47:48.13#ibcon#*before write, iclass 24, count 2 2006.257.03:47:48.13#ibcon#enter sib2, iclass 24, count 2 2006.257.03:47:48.13#ibcon#flushed, iclass 24, count 2 2006.257.03:47:48.13#ibcon#about to write, iclass 24, count 2 2006.257.03:47:48.13#ibcon#wrote, iclass 24, count 2 2006.257.03:47:48.13#ibcon#about to read 3, iclass 24, count 2 2006.257.03:47:48.16#ibcon#read 3, iclass 24, count 2 2006.257.03:47:48.16#ibcon#about to read 4, iclass 24, count 2 2006.257.03:47:48.16#ibcon#read 4, iclass 24, count 2 2006.257.03:47:48.16#ibcon#about to read 5, iclass 24, count 2 2006.257.03:47:48.16#ibcon#read 5, iclass 24, count 2 2006.257.03:47:48.16#ibcon#about to read 6, iclass 24, count 2 2006.257.03:47:48.16#ibcon#read 6, iclass 24, count 2 2006.257.03:47:48.16#ibcon#end of sib2, iclass 24, count 2 2006.257.03:47:48.16#ibcon#*after write, iclass 24, count 2 2006.257.03:47:48.16#ibcon#*before return 0, iclass 24, count 2 2006.257.03:47:48.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:48.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:47:48.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.03:47:48.16#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:48.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:48.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:48.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:48.28#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:47:48.28#ibcon#first serial, iclass 24, count 0 2006.257.03:47:48.28#ibcon#enter sib2, iclass 24, count 0 2006.257.03:47:48.28#ibcon#flushed, iclass 24, count 0 2006.257.03:47:48.28#ibcon#about to write, iclass 24, count 0 2006.257.03:47:48.28#ibcon#wrote, iclass 24, count 0 2006.257.03:47:48.28#ibcon#about to read 3, iclass 24, count 0 2006.257.03:47:48.30#ibcon#read 3, iclass 24, count 0 2006.257.03:47:48.30#ibcon#about to read 4, iclass 24, count 0 2006.257.03:47:48.30#ibcon#read 4, iclass 24, count 0 2006.257.03:47:48.30#ibcon#about to read 5, iclass 24, count 0 2006.257.03:47:48.30#ibcon#read 5, iclass 24, count 0 2006.257.03:47:48.30#ibcon#about to read 6, iclass 24, count 0 2006.257.03:47:48.30#ibcon#read 6, iclass 24, count 0 2006.257.03:47:48.30#ibcon#end of sib2, iclass 24, count 0 2006.257.03:47:48.30#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:47:48.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:47:48.30#ibcon#[27=USB\r\n] 2006.257.03:47:48.30#ibcon#*before write, iclass 24, count 0 2006.257.03:47:48.30#ibcon#enter sib2, iclass 24, count 0 2006.257.03:47:48.30#ibcon#flushed, iclass 24, count 0 2006.257.03:47:48.30#ibcon#about to write, iclass 24, count 0 2006.257.03:47:48.30#ibcon#wrote, iclass 24, count 0 2006.257.03:47:48.30#ibcon#about to read 3, iclass 24, count 0 2006.257.03:47:48.33#ibcon#read 3, iclass 24, count 0 2006.257.03:47:48.33#ibcon#about to read 4, iclass 24, count 0 2006.257.03:47:48.33#ibcon#read 4, iclass 24, count 0 2006.257.03:47:48.33#ibcon#about to read 5, iclass 24, count 0 2006.257.03:47:48.33#ibcon#read 5, iclass 24, count 0 2006.257.03:47:48.33#ibcon#about to read 6, iclass 24, count 0 2006.257.03:47:48.33#ibcon#read 6, iclass 24, count 0 2006.257.03:47:48.33#ibcon#end of sib2, iclass 24, count 0 2006.257.03:47:48.33#ibcon#*after write, iclass 24, count 0 2006.257.03:47:48.33#ibcon#*before return 0, iclass 24, count 0 2006.257.03:47:48.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:48.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:47:48.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:47:48.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:47:48.33$vck44/vblo=4,679.99 2006.257.03:47:48.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.03:47:48.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.03:47:48.33#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:48.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:48.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:48.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:48.33#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:47:48.33#ibcon#first serial, iclass 26, count 0 2006.257.03:47:48.33#ibcon#enter sib2, iclass 26, count 0 2006.257.03:47:48.33#ibcon#flushed, iclass 26, count 0 2006.257.03:47:48.33#ibcon#about to write, iclass 26, count 0 2006.257.03:47:48.33#ibcon#wrote, iclass 26, count 0 2006.257.03:47:48.33#ibcon#about to read 3, iclass 26, count 0 2006.257.03:47:48.35#ibcon#read 3, iclass 26, count 0 2006.257.03:47:48.35#ibcon#about to read 4, iclass 26, count 0 2006.257.03:47:48.35#ibcon#read 4, iclass 26, count 0 2006.257.03:47:48.35#ibcon#about to read 5, iclass 26, count 0 2006.257.03:47:48.35#ibcon#read 5, iclass 26, count 0 2006.257.03:47:48.35#ibcon#about to read 6, iclass 26, count 0 2006.257.03:47:48.35#ibcon#read 6, iclass 26, count 0 2006.257.03:47:48.35#ibcon#end of sib2, iclass 26, count 0 2006.257.03:47:48.35#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:47:48.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:47:48.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:47:48.35#ibcon#*before write, iclass 26, count 0 2006.257.03:47:48.35#ibcon#enter sib2, iclass 26, count 0 2006.257.03:47:48.35#ibcon#flushed, iclass 26, count 0 2006.257.03:47:48.35#ibcon#about to write, iclass 26, count 0 2006.257.03:47:48.35#ibcon#wrote, iclass 26, count 0 2006.257.03:47:48.35#ibcon#about to read 3, iclass 26, count 0 2006.257.03:47:48.39#ibcon#read 3, iclass 26, count 0 2006.257.03:47:48.39#ibcon#about to read 4, iclass 26, count 0 2006.257.03:47:48.39#ibcon#read 4, iclass 26, count 0 2006.257.03:47:48.39#ibcon#about to read 5, iclass 26, count 0 2006.257.03:47:48.39#ibcon#read 5, iclass 26, count 0 2006.257.03:47:48.39#ibcon#about to read 6, iclass 26, count 0 2006.257.03:47:48.39#ibcon#read 6, iclass 26, count 0 2006.257.03:47:48.39#ibcon#end of sib2, iclass 26, count 0 2006.257.03:47:48.39#ibcon#*after write, iclass 26, count 0 2006.257.03:47:48.39#ibcon#*before return 0, iclass 26, count 0 2006.257.03:47:48.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:48.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:47:48.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:47:48.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:47:48.39$vck44/vb=4,5 2006.257.03:47:48.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.03:47:48.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.03:47:48.39#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:48.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:48.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:48.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:48.45#ibcon#enter wrdev, iclass 28, count 2 2006.257.03:47:48.45#ibcon#first serial, iclass 28, count 2 2006.257.03:47:48.45#ibcon#enter sib2, iclass 28, count 2 2006.257.03:47:48.45#ibcon#flushed, iclass 28, count 2 2006.257.03:47:48.45#ibcon#about to write, iclass 28, count 2 2006.257.03:47:48.45#ibcon#wrote, iclass 28, count 2 2006.257.03:47:48.45#ibcon#about to read 3, iclass 28, count 2 2006.257.03:47:48.47#ibcon#read 3, iclass 28, count 2 2006.257.03:47:48.47#ibcon#about to read 4, iclass 28, count 2 2006.257.03:47:48.47#ibcon#read 4, iclass 28, count 2 2006.257.03:47:48.47#ibcon#about to read 5, iclass 28, count 2 2006.257.03:47:48.47#ibcon#read 5, iclass 28, count 2 2006.257.03:47:48.47#ibcon#about to read 6, iclass 28, count 2 2006.257.03:47:48.47#ibcon#read 6, iclass 28, count 2 2006.257.03:47:48.47#ibcon#end of sib2, iclass 28, count 2 2006.257.03:47:48.47#ibcon#*mode == 0, iclass 28, count 2 2006.257.03:47:48.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.03:47:48.47#ibcon#[27=AT04-05\r\n] 2006.257.03:47:48.47#ibcon#*before write, iclass 28, count 2 2006.257.03:47:48.47#ibcon#enter sib2, iclass 28, count 2 2006.257.03:47:48.47#ibcon#flushed, iclass 28, count 2 2006.257.03:47:48.47#ibcon#about to write, iclass 28, count 2 2006.257.03:47:48.47#ibcon#wrote, iclass 28, count 2 2006.257.03:47:48.47#ibcon#about to read 3, iclass 28, count 2 2006.257.03:47:48.50#ibcon#read 3, iclass 28, count 2 2006.257.03:47:48.50#ibcon#about to read 4, iclass 28, count 2 2006.257.03:47:48.50#ibcon#read 4, iclass 28, count 2 2006.257.03:47:48.50#ibcon#about to read 5, iclass 28, count 2 2006.257.03:47:48.50#ibcon#read 5, iclass 28, count 2 2006.257.03:47:48.50#ibcon#about to read 6, iclass 28, count 2 2006.257.03:47:48.50#ibcon#read 6, iclass 28, count 2 2006.257.03:47:48.50#ibcon#end of sib2, iclass 28, count 2 2006.257.03:47:48.50#ibcon#*after write, iclass 28, count 2 2006.257.03:47:48.50#ibcon#*before return 0, iclass 28, count 2 2006.257.03:47:48.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:48.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:47:48.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.03:47:48.50#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:48.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:48.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:48.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:48.62#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:47:48.62#ibcon#first serial, iclass 28, count 0 2006.257.03:47:48.62#ibcon#enter sib2, iclass 28, count 0 2006.257.03:47:48.62#ibcon#flushed, iclass 28, count 0 2006.257.03:47:48.62#ibcon#about to write, iclass 28, count 0 2006.257.03:47:48.62#ibcon#wrote, iclass 28, count 0 2006.257.03:47:48.62#ibcon#about to read 3, iclass 28, count 0 2006.257.03:47:48.64#ibcon#read 3, iclass 28, count 0 2006.257.03:47:48.64#ibcon#about to read 4, iclass 28, count 0 2006.257.03:47:48.64#ibcon#read 4, iclass 28, count 0 2006.257.03:47:48.64#ibcon#about to read 5, iclass 28, count 0 2006.257.03:47:48.64#ibcon#read 5, iclass 28, count 0 2006.257.03:47:48.64#ibcon#about to read 6, iclass 28, count 0 2006.257.03:47:48.64#ibcon#read 6, iclass 28, count 0 2006.257.03:47:48.64#ibcon#end of sib2, iclass 28, count 0 2006.257.03:47:48.64#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:47:48.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:47:48.64#ibcon#[27=USB\r\n] 2006.257.03:47:48.64#ibcon#*before write, iclass 28, count 0 2006.257.03:47:48.64#ibcon#enter sib2, iclass 28, count 0 2006.257.03:47:48.64#ibcon#flushed, iclass 28, count 0 2006.257.03:47:48.64#ibcon#about to write, iclass 28, count 0 2006.257.03:47:48.64#ibcon#wrote, iclass 28, count 0 2006.257.03:47:48.64#ibcon#about to read 3, iclass 28, count 0 2006.257.03:47:48.67#ibcon#read 3, iclass 28, count 0 2006.257.03:47:48.67#ibcon#about to read 4, iclass 28, count 0 2006.257.03:47:48.67#ibcon#read 4, iclass 28, count 0 2006.257.03:47:48.67#ibcon#about to read 5, iclass 28, count 0 2006.257.03:47:48.67#ibcon#read 5, iclass 28, count 0 2006.257.03:47:48.67#ibcon#about to read 6, iclass 28, count 0 2006.257.03:47:48.67#ibcon#read 6, iclass 28, count 0 2006.257.03:47:48.67#ibcon#end of sib2, iclass 28, count 0 2006.257.03:47:48.67#ibcon#*after write, iclass 28, count 0 2006.257.03:47:48.67#ibcon#*before return 0, iclass 28, count 0 2006.257.03:47:48.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:48.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:47:48.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:47:48.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:47:48.67$vck44/vblo=5,709.99 2006.257.03:47:48.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.03:47:48.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.03:47:48.67#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:48.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:48.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:48.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:48.67#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:47:48.67#ibcon#first serial, iclass 30, count 0 2006.257.03:47:48.67#ibcon#enter sib2, iclass 30, count 0 2006.257.03:47:48.67#ibcon#flushed, iclass 30, count 0 2006.257.03:47:48.67#ibcon#about to write, iclass 30, count 0 2006.257.03:47:48.67#ibcon#wrote, iclass 30, count 0 2006.257.03:47:48.67#ibcon#about to read 3, iclass 30, count 0 2006.257.03:47:48.69#ibcon#read 3, iclass 30, count 0 2006.257.03:47:48.69#ibcon#about to read 4, iclass 30, count 0 2006.257.03:47:48.69#ibcon#read 4, iclass 30, count 0 2006.257.03:47:48.69#ibcon#about to read 5, iclass 30, count 0 2006.257.03:47:48.69#ibcon#read 5, iclass 30, count 0 2006.257.03:47:48.69#ibcon#about to read 6, iclass 30, count 0 2006.257.03:47:48.69#ibcon#read 6, iclass 30, count 0 2006.257.03:47:48.69#ibcon#end of sib2, iclass 30, count 0 2006.257.03:47:48.69#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:47:48.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:47:48.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:47:48.69#ibcon#*before write, iclass 30, count 0 2006.257.03:47:48.69#ibcon#enter sib2, iclass 30, count 0 2006.257.03:47:48.69#ibcon#flushed, iclass 30, count 0 2006.257.03:47:48.69#ibcon#about to write, iclass 30, count 0 2006.257.03:47:48.69#ibcon#wrote, iclass 30, count 0 2006.257.03:47:48.69#ibcon#about to read 3, iclass 30, count 0 2006.257.03:47:48.73#ibcon#read 3, iclass 30, count 0 2006.257.03:47:48.73#ibcon#about to read 4, iclass 30, count 0 2006.257.03:47:48.73#ibcon#read 4, iclass 30, count 0 2006.257.03:47:48.73#ibcon#about to read 5, iclass 30, count 0 2006.257.03:47:48.73#ibcon#read 5, iclass 30, count 0 2006.257.03:47:48.73#ibcon#about to read 6, iclass 30, count 0 2006.257.03:47:48.73#ibcon#read 6, iclass 30, count 0 2006.257.03:47:48.73#ibcon#end of sib2, iclass 30, count 0 2006.257.03:47:48.73#ibcon#*after write, iclass 30, count 0 2006.257.03:47:48.73#ibcon#*before return 0, iclass 30, count 0 2006.257.03:47:48.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:48.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:47:48.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:47:48.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:47:48.73$vck44/vb=5,4 2006.257.03:47:48.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.03:47:48.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.03:47:48.73#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:48.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:48.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:48.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:48.79#ibcon#enter wrdev, iclass 32, count 2 2006.257.03:47:48.79#ibcon#first serial, iclass 32, count 2 2006.257.03:47:48.79#ibcon#enter sib2, iclass 32, count 2 2006.257.03:47:48.79#ibcon#flushed, iclass 32, count 2 2006.257.03:47:48.79#ibcon#about to write, iclass 32, count 2 2006.257.03:47:48.79#ibcon#wrote, iclass 32, count 2 2006.257.03:47:48.79#ibcon#about to read 3, iclass 32, count 2 2006.257.03:47:48.81#ibcon#read 3, iclass 32, count 2 2006.257.03:47:48.81#ibcon#about to read 4, iclass 32, count 2 2006.257.03:47:48.81#ibcon#read 4, iclass 32, count 2 2006.257.03:47:48.81#ibcon#about to read 5, iclass 32, count 2 2006.257.03:47:48.81#ibcon#read 5, iclass 32, count 2 2006.257.03:47:48.81#ibcon#about to read 6, iclass 32, count 2 2006.257.03:47:48.81#ibcon#read 6, iclass 32, count 2 2006.257.03:47:48.81#ibcon#end of sib2, iclass 32, count 2 2006.257.03:47:48.81#ibcon#*mode == 0, iclass 32, count 2 2006.257.03:47:48.81#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.03:47:48.81#ibcon#[27=AT05-04\r\n] 2006.257.03:47:48.81#ibcon#*before write, iclass 32, count 2 2006.257.03:47:48.81#ibcon#enter sib2, iclass 32, count 2 2006.257.03:47:48.81#ibcon#flushed, iclass 32, count 2 2006.257.03:47:48.81#ibcon#about to write, iclass 32, count 2 2006.257.03:47:48.81#ibcon#wrote, iclass 32, count 2 2006.257.03:47:48.81#ibcon#about to read 3, iclass 32, count 2 2006.257.03:47:48.84#ibcon#read 3, iclass 32, count 2 2006.257.03:47:48.84#ibcon#about to read 4, iclass 32, count 2 2006.257.03:47:48.84#ibcon#read 4, iclass 32, count 2 2006.257.03:47:48.84#ibcon#about to read 5, iclass 32, count 2 2006.257.03:47:48.84#ibcon#read 5, iclass 32, count 2 2006.257.03:47:48.84#ibcon#about to read 6, iclass 32, count 2 2006.257.03:47:48.84#ibcon#read 6, iclass 32, count 2 2006.257.03:47:48.84#ibcon#end of sib2, iclass 32, count 2 2006.257.03:47:48.84#ibcon#*after write, iclass 32, count 2 2006.257.03:47:48.84#ibcon#*before return 0, iclass 32, count 2 2006.257.03:47:48.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:48.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:47:48.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.03:47:48.84#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:48.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:48.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:48.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:48.96#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:47:48.96#ibcon#first serial, iclass 32, count 0 2006.257.03:47:48.96#ibcon#enter sib2, iclass 32, count 0 2006.257.03:47:48.96#ibcon#flushed, iclass 32, count 0 2006.257.03:47:48.96#ibcon#about to write, iclass 32, count 0 2006.257.03:47:48.96#ibcon#wrote, iclass 32, count 0 2006.257.03:47:48.96#ibcon#about to read 3, iclass 32, count 0 2006.257.03:47:48.98#ibcon#read 3, iclass 32, count 0 2006.257.03:47:48.98#ibcon#about to read 4, iclass 32, count 0 2006.257.03:47:48.98#ibcon#read 4, iclass 32, count 0 2006.257.03:47:48.98#ibcon#about to read 5, iclass 32, count 0 2006.257.03:47:48.98#ibcon#read 5, iclass 32, count 0 2006.257.03:47:48.98#ibcon#about to read 6, iclass 32, count 0 2006.257.03:47:48.98#ibcon#read 6, iclass 32, count 0 2006.257.03:47:48.98#ibcon#end of sib2, iclass 32, count 0 2006.257.03:47:48.98#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:47:48.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:47:48.98#ibcon#[27=USB\r\n] 2006.257.03:47:48.98#ibcon#*before write, iclass 32, count 0 2006.257.03:47:48.98#ibcon#enter sib2, iclass 32, count 0 2006.257.03:47:48.98#ibcon#flushed, iclass 32, count 0 2006.257.03:47:48.98#ibcon#about to write, iclass 32, count 0 2006.257.03:47:48.98#ibcon#wrote, iclass 32, count 0 2006.257.03:47:48.98#ibcon#about to read 3, iclass 32, count 0 2006.257.03:47:49.01#ibcon#read 3, iclass 32, count 0 2006.257.03:47:49.01#ibcon#about to read 4, iclass 32, count 0 2006.257.03:47:49.01#ibcon#read 4, iclass 32, count 0 2006.257.03:47:49.01#ibcon#about to read 5, iclass 32, count 0 2006.257.03:47:49.01#ibcon#read 5, iclass 32, count 0 2006.257.03:47:49.01#ibcon#about to read 6, iclass 32, count 0 2006.257.03:47:49.01#ibcon#read 6, iclass 32, count 0 2006.257.03:47:49.01#ibcon#end of sib2, iclass 32, count 0 2006.257.03:47:49.01#ibcon#*after write, iclass 32, count 0 2006.257.03:47:49.01#ibcon#*before return 0, iclass 32, count 0 2006.257.03:47:49.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:49.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:47:49.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:47:49.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:47:49.01$vck44/vblo=6,719.99 2006.257.03:47:49.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.03:47:49.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.03:47:49.01#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:49.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:49.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:49.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:49.01#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:47:49.01#ibcon#first serial, iclass 34, count 0 2006.257.03:47:49.01#ibcon#enter sib2, iclass 34, count 0 2006.257.03:47:49.01#ibcon#flushed, iclass 34, count 0 2006.257.03:47:49.01#ibcon#about to write, iclass 34, count 0 2006.257.03:47:49.01#ibcon#wrote, iclass 34, count 0 2006.257.03:47:49.01#ibcon#about to read 3, iclass 34, count 0 2006.257.03:47:49.03#ibcon#read 3, iclass 34, count 0 2006.257.03:47:49.03#ibcon#about to read 4, iclass 34, count 0 2006.257.03:47:49.03#ibcon#read 4, iclass 34, count 0 2006.257.03:47:49.03#ibcon#about to read 5, iclass 34, count 0 2006.257.03:47:49.03#ibcon#read 5, iclass 34, count 0 2006.257.03:47:49.03#ibcon#about to read 6, iclass 34, count 0 2006.257.03:47:49.03#ibcon#read 6, iclass 34, count 0 2006.257.03:47:49.03#ibcon#end of sib2, iclass 34, count 0 2006.257.03:47:49.03#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:47:49.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:47:49.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:47:49.03#ibcon#*before write, iclass 34, count 0 2006.257.03:47:49.03#ibcon#enter sib2, iclass 34, count 0 2006.257.03:47:49.03#ibcon#flushed, iclass 34, count 0 2006.257.03:47:49.03#ibcon#about to write, iclass 34, count 0 2006.257.03:47:49.03#ibcon#wrote, iclass 34, count 0 2006.257.03:47:49.03#ibcon#about to read 3, iclass 34, count 0 2006.257.03:47:49.07#ibcon#read 3, iclass 34, count 0 2006.257.03:47:49.07#ibcon#about to read 4, iclass 34, count 0 2006.257.03:47:49.07#ibcon#read 4, iclass 34, count 0 2006.257.03:47:49.07#ibcon#about to read 5, iclass 34, count 0 2006.257.03:47:49.07#ibcon#read 5, iclass 34, count 0 2006.257.03:47:49.07#ibcon#about to read 6, iclass 34, count 0 2006.257.03:47:49.07#ibcon#read 6, iclass 34, count 0 2006.257.03:47:49.07#ibcon#end of sib2, iclass 34, count 0 2006.257.03:47:49.07#ibcon#*after write, iclass 34, count 0 2006.257.03:47:49.07#ibcon#*before return 0, iclass 34, count 0 2006.257.03:47:49.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:49.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:47:49.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:47:49.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:47:49.07$vck44/vb=6,4 2006.257.03:47:49.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.03:47:49.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.03:47:49.07#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:49.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:49.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:49.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:49.13#ibcon#enter wrdev, iclass 36, count 2 2006.257.03:47:49.13#ibcon#first serial, iclass 36, count 2 2006.257.03:47:49.13#ibcon#enter sib2, iclass 36, count 2 2006.257.03:47:49.13#ibcon#flushed, iclass 36, count 2 2006.257.03:47:49.13#ibcon#about to write, iclass 36, count 2 2006.257.03:47:49.13#ibcon#wrote, iclass 36, count 2 2006.257.03:47:49.13#ibcon#about to read 3, iclass 36, count 2 2006.257.03:47:49.15#ibcon#read 3, iclass 36, count 2 2006.257.03:47:49.15#ibcon#about to read 4, iclass 36, count 2 2006.257.03:47:49.15#ibcon#read 4, iclass 36, count 2 2006.257.03:47:49.15#ibcon#about to read 5, iclass 36, count 2 2006.257.03:47:49.15#ibcon#read 5, iclass 36, count 2 2006.257.03:47:49.15#ibcon#about to read 6, iclass 36, count 2 2006.257.03:47:49.15#ibcon#read 6, iclass 36, count 2 2006.257.03:47:49.15#ibcon#end of sib2, iclass 36, count 2 2006.257.03:47:49.15#ibcon#*mode == 0, iclass 36, count 2 2006.257.03:47:49.15#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.03:47:49.15#ibcon#[27=AT06-04\r\n] 2006.257.03:47:49.15#ibcon#*before write, iclass 36, count 2 2006.257.03:47:49.15#ibcon#enter sib2, iclass 36, count 2 2006.257.03:47:49.15#ibcon#flushed, iclass 36, count 2 2006.257.03:47:49.15#ibcon#about to write, iclass 36, count 2 2006.257.03:47:49.15#ibcon#wrote, iclass 36, count 2 2006.257.03:47:49.15#ibcon#about to read 3, iclass 36, count 2 2006.257.03:47:49.18#ibcon#read 3, iclass 36, count 2 2006.257.03:47:49.18#ibcon#about to read 4, iclass 36, count 2 2006.257.03:47:49.18#ibcon#read 4, iclass 36, count 2 2006.257.03:47:49.18#ibcon#about to read 5, iclass 36, count 2 2006.257.03:47:49.18#ibcon#read 5, iclass 36, count 2 2006.257.03:47:49.18#ibcon#about to read 6, iclass 36, count 2 2006.257.03:47:49.18#ibcon#read 6, iclass 36, count 2 2006.257.03:47:49.18#ibcon#end of sib2, iclass 36, count 2 2006.257.03:47:49.18#ibcon#*after write, iclass 36, count 2 2006.257.03:47:49.18#ibcon#*before return 0, iclass 36, count 2 2006.257.03:47:49.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:49.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:47:49.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.03:47:49.18#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:49.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:49.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:49.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:49.30#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:47:49.30#ibcon#first serial, iclass 36, count 0 2006.257.03:47:49.30#ibcon#enter sib2, iclass 36, count 0 2006.257.03:47:49.30#ibcon#flushed, iclass 36, count 0 2006.257.03:47:49.30#ibcon#about to write, iclass 36, count 0 2006.257.03:47:49.30#ibcon#wrote, iclass 36, count 0 2006.257.03:47:49.30#ibcon#about to read 3, iclass 36, count 0 2006.257.03:47:49.32#ibcon#read 3, iclass 36, count 0 2006.257.03:47:49.32#ibcon#about to read 4, iclass 36, count 0 2006.257.03:47:49.32#ibcon#read 4, iclass 36, count 0 2006.257.03:47:49.32#ibcon#about to read 5, iclass 36, count 0 2006.257.03:47:49.32#ibcon#read 5, iclass 36, count 0 2006.257.03:47:49.32#ibcon#about to read 6, iclass 36, count 0 2006.257.03:47:49.32#ibcon#read 6, iclass 36, count 0 2006.257.03:47:49.32#ibcon#end of sib2, iclass 36, count 0 2006.257.03:47:49.32#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:47:49.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:47:49.32#ibcon#[27=USB\r\n] 2006.257.03:47:49.32#ibcon#*before write, iclass 36, count 0 2006.257.03:47:49.32#ibcon#enter sib2, iclass 36, count 0 2006.257.03:47:49.32#ibcon#flushed, iclass 36, count 0 2006.257.03:47:49.32#ibcon#about to write, iclass 36, count 0 2006.257.03:47:49.32#ibcon#wrote, iclass 36, count 0 2006.257.03:47:49.32#ibcon#about to read 3, iclass 36, count 0 2006.257.03:47:49.35#ibcon#read 3, iclass 36, count 0 2006.257.03:47:49.35#ibcon#about to read 4, iclass 36, count 0 2006.257.03:47:49.35#ibcon#read 4, iclass 36, count 0 2006.257.03:47:49.35#ibcon#about to read 5, iclass 36, count 0 2006.257.03:47:49.35#ibcon#read 5, iclass 36, count 0 2006.257.03:47:49.35#ibcon#about to read 6, iclass 36, count 0 2006.257.03:47:49.35#ibcon#read 6, iclass 36, count 0 2006.257.03:47:49.35#ibcon#end of sib2, iclass 36, count 0 2006.257.03:47:49.35#ibcon#*after write, iclass 36, count 0 2006.257.03:47:49.35#ibcon#*before return 0, iclass 36, count 0 2006.257.03:47:49.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:49.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:47:49.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:47:49.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:47:49.35$vck44/vblo=7,734.99 2006.257.03:47:49.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.03:47:49.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.03:47:49.35#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:49.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:49.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:49.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:49.35#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:47:49.35#ibcon#first serial, iclass 38, count 0 2006.257.03:47:49.35#ibcon#enter sib2, iclass 38, count 0 2006.257.03:47:49.35#ibcon#flushed, iclass 38, count 0 2006.257.03:47:49.35#ibcon#about to write, iclass 38, count 0 2006.257.03:47:49.35#ibcon#wrote, iclass 38, count 0 2006.257.03:47:49.35#ibcon#about to read 3, iclass 38, count 0 2006.257.03:47:49.37#ibcon#read 3, iclass 38, count 0 2006.257.03:47:49.37#ibcon#about to read 4, iclass 38, count 0 2006.257.03:47:49.37#ibcon#read 4, iclass 38, count 0 2006.257.03:47:49.37#ibcon#about to read 5, iclass 38, count 0 2006.257.03:47:49.37#ibcon#read 5, iclass 38, count 0 2006.257.03:47:49.37#ibcon#about to read 6, iclass 38, count 0 2006.257.03:47:49.37#ibcon#read 6, iclass 38, count 0 2006.257.03:47:49.37#ibcon#end of sib2, iclass 38, count 0 2006.257.03:47:49.37#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:47:49.37#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:47:49.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:47:49.37#ibcon#*before write, iclass 38, count 0 2006.257.03:47:49.37#ibcon#enter sib2, iclass 38, count 0 2006.257.03:47:49.37#ibcon#flushed, iclass 38, count 0 2006.257.03:47:49.37#ibcon#about to write, iclass 38, count 0 2006.257.03:47:49.37#ibcon#wrote, iclass 38, count 0 2006.257.03:47:49.37#ibcon#about to read 3, iclass 38, count 0 2006.257.03:47:49.41#ibcon#read 3, iclass 38, count 0 2006.257.03:47:49.41#ibcon#about to read 4, iclass 38, count 0 2006.257.03:47:49.41#ibcon#read 4, iclass 38, count 0 2006.257.03:47:49.41#ibcon#about to read 5, iclass 38, count 0 2006.257.03:47:49.41#ibcon#read 5, iclass 38, count 0 2006.257.03:47:49.41#ibcon#about to read 6, iclass 38, count 0 2006.257.03:47:49.41#ibcon#read 6, iclass 38, count 0 2006.257.03:47:49.41#ibcon#end of sib2, iclass 38, count 0 2006.257.03:47:49.41#ibcon#*after write, iclass 38, count 0 2006.257.03:47:49.41#ibcon#*before return 0, iclass 38, count 0 2006.257.03:47:49.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:49.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:47:49.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:47:49.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:47:49.41$vck44/vb=7,4 2006.257.03:47:49.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.03:47:49.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.03:47:49.41#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:49.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:49.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:49.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:49.47#ibcon#enter wrdev, iclass 40, count 2 2006.257.03:47:49.47#ibcon#first serial, iclass 40, count 2 2006.257.03:47:49.47#ibcon#enter sib2, iclass 40, count 2 2006.257.03:47:49.47#ibcon#flushed, iclass 40, count 2 2006.257.03:47:49.47#ibcon#about to write, iclass 40, count 2 2006.257.03:47:49.47#ibcon#wrote, iclass 40, count 2 2006.257.03:47:49.47#ibcon#about to read 3, iclass 40, count 2 2006.257.03:47:49.49#ibcon#read 3, iclass 40, count 2 2006.257.03:47:49.49#ibcon#about to read 4, iclass 40, count 2 2006.257.03:47:49.49#ibcon#read 4, iclass 40, count 2 2006.257.03:47:49.49#ibcon#about to read 5, iclass 40, count 2 2006.257.03:47:49.49#ibcon#read 5, iclass 40, count 2 2006.257.03:47:49.49#ibcon#about to read 6, iclass 40, count 2 2006.257.03:47:49.49#ibcon#read 6, iclass 40, count 2 2006.257.03:47:49.49#ibcon#end of sib2, iclass 40, count 2 2006.257.03:47:49.49#ibcon#*mode == 0, iclass 40, count 2 2006.257.03:47:49.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.03:47:49.49#ibcon#[27=AT07-04\r\n] 2006.257.03:47:49.49#ibcon#*before write, iclass 40, count 2 2006.257.03:47:49.49#ibcon#enter sib2, iclass 40, count 2 2006.257.03:47:49.49#ibcon#flushed, iclass 40, count 2 2006.257.03:47:49.49#ibcon#about to write, iclass 40, count 2 2006.257.03:47:49.49#ibcon#wrote, iclass 40, count 2 2006.257.03:47:49.49#ibcon#about to read 3, iclass 40, count 2 2006.257.03:47:49.52#ibcon#read 3, iclass 40, count 2 2006.257.03:47:49.52#ibcon#about to read 4, iclass 40, count 2 2006.257.03:47:49.52#ibcon#read 4, iclass 40, count 2 2006.257.03:47:49.52#ibcon#about to read 5, iclass 40, count 2 2006.257.03:47:49.52#ibcon#read 5, iclass 40, count 2 2006.257.03:47:49.52#ibcon#about to read 6, iclass 40, count 2 2006.257.03:47:49.52#ibcon#read 6, iclass 40, count 2 2006.257.03:47:49.52#ibcon#end of sib2, iclass 40, count 2 2006.257.03:47:49.52#ibcon#*after write, iclass 40, count 2 2006.257.03:47:49.52#ibcon#*before return 0, iclass 40, count 2 2006.257.03:47:49.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:49.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:47:49.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.03:47:49.52#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:49.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:49.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:49.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:49.64#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:47:49.64#ibcon#first serial, iclass 40, count 0 2006.257.03:47:49.64#ibcon#enter sib2, iclass 40, count 0 2006.257.03:47:49.64#ibcon#flushed, iclass 40, count 0 2006.257.03:47:49.64#ibcon#about to write, iclass 40, count 0 2006.257.03:47:49.64#ibcon#wrote, iclass 40, count 0 2006.257.03:47:49.64#ibcon#about to read 3, iclass 40, count 0 2006.257.03:47:49.66#ibcon#read 3, iclass 40, count 0 2006.257.03:47:49.66#ibcon#about to read 4, iclass 40, count 0 2006.257.03:47:49.66#ibcon#read 4, iclass 40, count 0 2006.257.03:47:49.66#ibcon#about to read 5, iclass 40, count 0 2006.257.03:47:49.66#ibcon#read 5, iclass 40, count 0 2006.257.03:47:49.66#ibcon#about to read 6, iclass 40, count 0 2006.257.03:47:49.66#ibcon#read 6, iclass 40, count 0 2006.257.03:47:49.66#ibcon#end of sib2, iclass 40, count 0 2006.257.03:47:49.66#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:47:49.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:47:49.66#ibcon#[27=USB\r\n] 2006.257.03:47:49.66#ibcon#*before write, iclass 40, count 0 2006.257.03:47:49.66#ibcon#enter sib2, iclass 40, count 0 2006.257.03:47:49.66#ibcon#flushed, iclass 40, count 0 2006.257.03:47:49.66#ibcon#about to write, iclass 40, count 0 2006.257.03:47:49.66#ibcon#wrote, iclass 40, count 0 2006.257.03:47:49.66#ibcon#about to read 3, iclass 40, count 0 2006.257.03:47:49.69#ibcon#read 3, iclass 40, count 0 2006.257.03:47:49.69#ibcon#about to read 4, iclass 40, count 0 2006.257.03:47:49.69#ibcon#read 4, iclass 40, count 0 2006.257.03:47:49.69#ibcon#about to read 5, iclass 40, count 0 2006.257.03:47:49.69#ibcon#read 5, iclass 40, count 0 2006.257.03:47:49.69#ibcon#about to read 6, iclass 40, count 0 2006.257.03:47:49.69#ibcon#read 6, iclass 40, count 0 2006.257.03:47:49.69#ibcon#end of sib2, iclass 40, count 0 2006.257.03:47:49.69#ibcon#*after write, iclass 40, count 0 2006.257.03:47:49.69#ibcon#*before return 0, iclass 40, count 0 2006.257.03:47:49.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:49.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:47:49.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:47:49.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:47:49.69$vck44/vblo=8,744.99 2006.257.03:47:49.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.03:47:49.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.03:47:49.69#ibcon#ireg 17 cls_cnt 0 2006.257.03:47:49.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:49.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:49.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:49.69#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:47:49.69#ibcon#first serial, iclass 4, count 0 2006.257.03:47:49.69#ibcon#enter sib2, iclass 4, count 0 2006.257.03:47:49.69#ibcon#flushed, iclass 4, count 0 2006.257.03:47:49.69#ibcon#about to write, iclass 4, count 0 2006.257.03:47:49.69#ibcon#wrote, iclass 4, count 0 2006.257.03:47:49.69#ibcon#about to read 3, iclass 4, count 0 2006.257.03:47:49.71#ibcon#read 3, iclass 4, count 0 2006.257.03:47:49.71#ibcon#about to read 4, iclass 4, count 0 2006.257.03:47:49.71#ibcon#read 4, iclass 4, count 0 2006.257.03:47:49.71#ibcon#about to read 5, iclass 4, count 0 2006.257.03:47:49.71#ibcon#read 5, iclass 4, count 0 2006.257.03:47:49.71#ibcon#about to read 6, iclass 4, count 0 2006.257.03:47:49.71#ibcon#read 6, iclass 4, count 0 2006.257.03:47:49.71#ibcon#end of sib2, iclass 4, count 0 2006.257.03:47:49.71#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:47:49.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:47:49.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:47:49.71#ibcon#*before write, iclass 4, count 0 2006.257.03:47:49.71#ibcon#enter sib2, iclass 4, count 0 2006.257.03:47:49.71#ibcon#flushed, iclass 4, count 0 2006.257.03:47:49.71#ibcon#about to write, iclass 4, count 0 2006.257.03:47:49.71#ibcon#wrote, iclass 4, count 0 2006.257.03:47:49.71#ibcon#about to read 3, iclass 4, count 0 2006.257.03:47:49.75#ibcon#read 3, iclass 4, count 0 2006.257.03:47:49.75#ibcon#about to read 4, iclass 4, count 0 2006.257.03:47:49.75#ibcon#read 4, iclass 4, count 0 2006.257.03:47:49.75#ibcon#about to read 5, iclass 4, count 0 2006.257.03:47:49.75#ibcon#read 5, iclass 4, count 0 2006.257.03:47:49.75#ibcon#about to read 6, iclass 4, count 0 2006.257.03:47:49.75#ibcon#read 6, iclass 4, count 0 2006.257.03:47:49.75#ibcon#end of sib2, iclass 4, count 0 2006.257.03:47:49.75#ibcon#*after write, iclass 4, count 0 2006.257.03:47:49.75#ibcon#*before return 0, iclass 4, count 0 2006.257.03:47:49.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:49.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:47:49.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:47:49.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:47:49.75$vck44/vb=8,4 2006.257.03:47:49.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.03:47:49.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.03:47:49.75#ibcon#ireg 11 cls_cnt 2 2006.257.03:47:49.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:49.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:49.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:49.81#ibcon#enter wrdev, iclass 6, count 2 2006.257.03:47:49.81#ibcon#first serial, iclass 6, count 2 2006.257.03:47:49.81#ibcon#enter sib2, iclass 6, count 2 2006.257.03:47:49.81#ibcon#flushed, iclass 6, count 2 2006.257.03:47:49.81#ibcon#about to write, iclass 6, count 2 2006.257.03:47:49.81#ibcon#wrote, iclass 6, count 2 2006.257.03:47:49.81#ibcon#about to read 3, iclass 6, count 2 2006.257.03:47:49.83#ibcon#read 3, iclass 6, count 2 2006.257.03:47:49.83#ibcon#about to read 4, iclass 6, count 2 2006.257.03:47:49.83#ibcon#read 4, iclass 6, count 2 2006.257.03:47:49.83#ibcon#about to read 5, iclass 6, count 2 2006.257.03:47:49.83#ibcon#read 5, iclass 6, count 2 2006.257.03:47:49.83#ibcon#about to read 6, iclass 6, count 2 2006.257.03:47:49.83#ibcon#read 6, iclass 6, count 2 2006.257.03:47:49.83#ibcon#end of sib2, iclass 6, count 2 2006.257.03:47:49.83#ibcon#*mode == 0, iclass 6, count 2 2006.257.03:47:49.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.03:47:49.83#ibcon#[27=AT08-04\r\n] 2006.257.03:47:49.83#ibcon#*before write, iclass 6, count 2 2006.257.03:47:49.83#ibcon#enter sib2, iclass 6, count 2 2006.257.03:47:49.83#ibcon#flushed, iclass 6, count 2 2006.257.03:47:49.83#ibcon#about to write, iclass 6, count 2 2006.257.03:47:49.83#ibcon#wrote, iclass 6, count 2 2006.257.03:47:49.83#ibcon#about to read 3, iclass 6, count 2 2006.257.03:47:49.86#ibcon#read 3, iclass 6, count 2 2006.257.03:47:49.86#ibcon#about to read 4, iclass 6, count 2 2006.257.03:47:49.86#ibcon#read 4, iclass 6, count 2 2006.257.03:47:49.86#ibcon#about to read 5, iclass 6, count 2 2006.257.03:47:49.86#ibcon#read 5, iclass 6, count 2 2006.257.03:47:49.86#ibcon#about to read 6, iclass 6, count 2 2006.257.03:47:49.86#ibcon#read 6, iclass 6, count 2 2006.257.03:47:49.86#ibcon#end of sib2, iclass 6, count 2 2006.257.03:47:49.86#ibcon#*after write, iclass 6, count 2 2006.257.03:47:49.86#ibcon#*before return 0, iclass 6, count 2 2006.257.03:47:49.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:49.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:47:49.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.03:47:49.86#ibcon#ireg 7 cls_cnt 0 2006.257.03:47:49.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:49.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:49.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:49.98#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:47:49.98#ibcon#first serial, iclass 6, count 0 2006.257.03:47:49.98#ibcon#enter sib2, iclass 6, count 0 2006.257.03:47:49.98#ibcon#flushed, iclass 6, count 0 2006.257.03:47:49.98#ibcon#about to write, iclass 6, count 0 2006.257.03:47:49.98#ibcon#wrote, iclass 6, count 0 2006.257.03:47:49.98#ibcon#about to read 3, iclass 6, count 0 2006.257.03:47:50.00#ibcon#read 3, iclass 6, count 0 2006.257.03:47:50.00#ibcon#about to read 4, iclass 6, count 0 2006.257.03:47:50.00#ibcon#read 4, iclass 6, count 0 2006.257.03:47:50.00#ibcon#about to read 5, iclass 6, count 0 2006.257.03:47:50.00#ibcon#read 5, iclass 6, count 0 2006.257.03:47:50.00#ibcon#about to read 6, iclass 6, count 0 2006.257.03:47:50.00#ibcon#read 6, iclass 6, count 0 2006.257.03:47:50.00#ibcon#end of sib2, iclass 6, count 0 2006.257.03:47:50.00#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:47:50.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:47:50.00#ibcon#[27=USB\r\n] 2006.257.03:47:50.00#ibcon#*before write, iclass 6, count 0 2006.257.03:47:50.00#ibcon#enter sib2, iclass 6, count 0 2006.257.03:47:50.00#ibcon#flushed, iclass 6, count 0 2006.257.03:47:50.00#ibcon#about to write, iclass 6, count 0 2006.257.03:47:50.00#ibcon#wrote, iclass 6, count 0 2006.257.03:47:50.00#ibcon#about to read 3, iclass 6, count 0 2006.257.03:47:50.03#ibcon#read 3, iclass 6, count 0 2006.257.03:47:50.03#ibcon#about to read 4, iclass 6, count 0 2006.257.03:47:50.03#ibcon#read 4, iclass 6, count 0 2006.257.03:47:50.03#ibcon#about to read 5, iclass 6, count 0 2006.257.03:47:50.03#ibcon#read 5, iclass 6, count 0 2006.257.03:47:50.03#ibcon#about to read 6, iclass 6, count 0 2006.257.03:47:50.03#ibcon#read 6, iclass 6, count 0 2006.257.03:47:50.03#ibcon#end of sib2, iclass 6, count 0 2006.257.03:47:50.03#ibcon#*after write, iclass 6, count 0 2006.257.03:47:50.03#ibcon#*before return 0, iclass 6, count 0 2006.257.03:47:50.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:50.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:47:50.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:47:50.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:47:50.03$vck44/vabw=wide 2006.257.03:47:50.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.03:47:50.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.03:47:50.03#ibcon#ireg 8 cls_cnt 0 2006.257.03:47:50.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:50.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:50.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:50.03#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:47:50.03#ibcon#first serial, iclass 10, count 0 2006.257.03:47:50.03#ibcon#enter sib2, iclass 10, count 0 2006.257.03:47:50.03#ibcon#flushed, iclass 10, count 0 2006.257.03:47:50.03#ibcon#about to write, iclass 10, count 0 2006.257.03:47:50.03#ibcon#wrote, iclass 10, count 0 2006.257.03:47:50.03#ibcon#about to read 3, iclass 10, count 0 2006.257.03:47:50.05#ibcon#read 3, iclass 10, count 0 2006.257.03:47:50.05#ibcon#about to read 4, iclass 10, count 0 2006.257.03:47:50.05#ibcon#read 4, iclass 10, count 0 2006.257.03:47:50.05#ibcon#about to read 5, iclass 10, count 0 2006.257.03:47:50.05#ibcon#read 5, iclass 10, count 0 2006.257.03:47:50.05#ibcon#about to read 6, iclass 10, count 0 2006.257.03:47:50.05#ibcon#read 6, iclass 10, count 0 2006.257.03:47:50.05#ibcon#end of sib2, iclass 10, count 0 2006.257.03:47:50.05#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:47:50.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:47:50.05#ibcon#[25=BW32\r\n] 2006.257.03:47:50.05#ibcon#*before write, iclass 10, count 0 2006.257.03:47:50.05#ibcon#enter sib2, iclass 10, count 0 2006.257.03:47:50.05#ibcon#flushed, iclass 10, count 0 2006.257.03:47:50.05#ibcon#about to write, iclass 10, count 0 2006.257.03:47:50.05#ibcon#wrote, iclass 10, count 0 2006.257.03:47:50.05#ibcon#about to read 3, iclass 10, count 0 2006.257.03:47:50.08#ibcon#read 3, iclass 10, count 0 2006.257.03:47:50.08#ibcon#about to read 4, iclass 10, count 0 2006.257.03:47:50.08#ibcon#read 4, iclass 10, count 0 2006.257.03:47:50.08#ibcon#about to read 5, iclass 10, count 0 2006.257.03:47:50.08#ibcon#read 5, iclass 10, count 0 2006.257.03:47:50.08#ibcon#about to read 6, iclass 10, count 0 2006.257.03:47:50.08#ibcon#read 6, iclass 10, count 0 2006.257.03:47:50.08#ibcon#end of sib2, iclass 10, count 0 2006.257.03:47:50.08#ibcon#*after write, iclass 10, count 0 2006.257.03:47:50.08#ibcon#*before return 0, iclass 10, count 0 2006.257.03:47:50.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:50.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:47:50.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:47:50.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:47:50.08$vck44/vbbw=wide 2006.257.03:47:50.08#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.03:47:50.08#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.03:47:50.08#ibcon#ireg 8 cls_cnt 0 2006.257.03:47:50.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:47:50.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:47:50.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:47:50.15#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:47:50.15#ibcon#first serial, iclass 12, count 0 2006.257.03:47:50.15#ibcon#enter sib2, iclass 12, count 0 2006.257.03:47:50.15#ibcon#flushed, iclass 12, count 0 2006.257.03:47:50.15#ibcon#about to write, iclass 12, count 0 2006.257.03:47:50.15#ibcon#wrote, iclass 12, count 0 2006.257.03:47:50.15#ibcon#about to read 3, iclass 12, count 0 2006.257.03:47:50.17#ibcon#read 3, iclass 12, count 0 2006.257.03:47:50.17#ibcon#about to read 4, iclass 12, count 0 2006.257.03:47:50.17#ibcon#read 4, iclass 12, count 0 2006.257.03:47:50.17#ibcon#about to read 5, iclass 12, count 0 2006.257.03:47:50.17#ibcon#read 5, iclass 12, count 0 2006.257.03:47:50.17#ibcon#about to read 6, iclass 12, count 0 2006.257.03:47:50.17#ibcon#read 6, iclass 12, count 0 2006.257.03:47:50.17#ibcon#end of sib2, iclass 12, count 0 2006.257.03:47:50.17#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:47:50.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:47:50.17#ibcon#[27=BW32\r\n] 2006.257.03:47:50.17#ibcon#*before write, iclass 12, count 0 2006.257.03:47:50.17#ibcon#enter sib2, iclass 12, count 0 2006.257.03:47:50.17#ibcon#flushed, iclass 12, count 0 2006.257.03:47:50.17#ibcon#about to write, iclass 12, count 0 2006.257.03:47:50.17#ibcon#wrote, iclass 12, count 0 2006.257.03:47:50.17#ibcon#about to read 3, iclass 12, count 0 2006.257.03:47:50.20#ibcon#read 3, iclass 12, count 0 2006.257.03:47:50.20#ibcon#about to read 4, iclass 12, count 0 2006.257.03:47:50.20#ibcon#read 4, iclass 12, count 0 2006.257.03:47:50.20#ibcon#about to read 5, iclass 12, count 0 2006.257.03:47:50.20#ibcon#read 5, iclass 12, count 0 2006.257.03:47:50.20#ibcon#about to read 6, iclass 12, count 0 2006.257.03:47:50.20#ibcon#read 6, iclass 12, count 0 2006.257.03:47:50.20#ibcon#end of sib2, iclass 12, count 0 2006.257.03:47:50.20#ibcon#*after write, iclass 12, count 0 2006.257.03:47:50.20#ibcon#*before return 0, iclass 12, count 0 2006.257.03:47:50.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:47:50.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:47:50.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:47:50.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:47:50.20$setupk4/ifdk4 2006.257.03:47:50.20$ifdk4/lo= 2006.257.03:47:50.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:47:50.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:47:50.20$ifdk4/patch= 2006.257.03:47:50.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:47:50.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:47:50.20$setupk4/!*+20s 2006.257.03:47:51.14#abcon#<5=/13 1.6 4.3 19.39 951012.3\r\n> 2006.257.03:47:51.16#abcon#{5=INTERFACE CLEAR} 2006.257.03:47:51.22#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:48:01.31#abcon#<5=/13 1.5 4.3 19.39 951012.3\r\n> 2006.257.03:48:01.33#abcon#{5=INTERFACE CLEAR} 2006.257.03:48:01.39#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:48:04.71$setupk4/"tpicd 2006.257.03:48:04.71$setupk4/echo=off 2006.257.03:48:04.71$setupk4/xlog=off 2006.257.03:48:04.71:!2006.257.03:48:57 2006.257.03:48:38.14#trakl#Source acquired 2006.257.03:48:40.14#flagr#flagr/antenna,acquired 2006.257.03:48:57.00:preob 2006.257.03:48:57.14/onsource/TRACKING 2006.257.03:48:57.14:!2006.257.03:49:07 2006.257.03:49:07.00:"tape 2006.257.03:49:07.00:"st=record 2006.257.03:49:07.00:data_valid=on 2006.257.03:49:07.00:midob 2006.257.03:49:07.14/onsource/TRACKING 2006.257.03:49:07.14/wx/19.38,1012.3,95 2006.257.03:49:07.19/cable/+6.4839E-03 2006.257.03:49:08.28/va/01,08,usb,yes,37,39 2006.257.03:49:08.28/va/02,07,usb,yes,40,40 2006.257.03:49:08.28/va/03,08,usb,yes,36,38 2006.257.03:49:08.28/va/04,07,usb,yes,41,43 2006.257.03:49:08.28/va/05,04,usb,yes,37,37 2006.257.03:49:08.28/va/06,04,usb,yes,41,40 2006.257.03:49:08.28/va/07,04,usb,yes,42,42 2006.257.03:49:08.28/va/08,04,usb,yes,35,43 2006.257.03:49:08.51/valo/01,524.99,yes,locked 2006.257.03:49:08.51/valo/02,534.99,yes,locked 2006.257.03:49:08.51/valo/03,564.99,yes,locked 2006.257.03:49:08.51/valo/04,624.99,yes,locked 2006.257.03:49:08.51/valo/05,734.99,yes,locked 2006.257.03:49:08.51/valo/06,814.99,yes,locked 2006.257.03:49:08.51/valo/07,864.99,yes,locked 2006.257.03:49:08.51/valo/08,884.99,yes,locked 2006.257.03:49:09.60/vb/01,04,usb,yes,30,36 2006.257.03:49:09.60/vb/02,05,usb,yes,28,37 2006.257.03:49:09.60/vb/03,04,usb,yes,29,33 2006.257.03:49:09.60/vb/04,05,usb,yes,29,28 2006.257.03:49:09.60/vb/05,04,usb,yes,26,28 2006.257.03:49:09.60/vb/06,04,usb,yes,31,27 2006.257.03:49:09.60/vb/07,04,usb,yes,30,30 2006.257.03:49:09.60/vb/08,04,usb,yes,28,31 2006.257.03:49:09.84/vblo/01,629.99,yes,locked 2006.257.03:49:09.84/vblo/02,634.99,yes,locked 2006.257.03:49:09.84/vblo/03,649.99,yes,locked 2006.257.03:49:09.84/vblo/04,679.99,yes,locked 2006.257.03:49:09.84/vblo/05,709.99,yes,locked 2006.257.03:49:09.84/vblo/06,719.99,yes,locked 2006.257.03:49:09.84/vblo/07,734.99,yes,locked 2006.257.03:49:09.84/vblo/08,744.99,yes,locked 2006.257.03:49:09.99/vabw/8 2006.257.03:49:10.14/vbbw/8 2006.257.03:49:10.23/xfe/off,on,16.5 2006.257.03:49:10.61/ifatt/23,28,28,28 2006.257.03:49:11.07/fmout-gps/S +4.52E-07 2006.257.03:49:11.11:!2006.257.03:49:47 2006.257.03:49:47.01:data_valid=off 2006.257.03:49:47.01:"et 2006.257.03:49:47.02:!+3s 2006.257.03:49:50.04:"tape 2006.257.03:49:50.04:postob 2006.257.03:49:50.12/cable/+6.4844E-03 2006.257.03:49:50.12/wx/19.38,1012.3,95 2006.257.03:49:50.18/fmout-gps/S +4.51E-07 2006.257.03:49:50.18:scan_name=257-0350,jd0609,40 2006.257.03:49:50.18:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.03:49:52.14#flagr#flagr/antenna,new-source 2006.257.03:49:52.14:checkk5 2006.257.03:49:52.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:49:52.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:49:53.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:49:53.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:49:54.17/chk_obsdata//k5ts1/T2570349??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:49:54.57/chk_obsdata//k5ts2/T2570349??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:49:54.98/chk_obsdata//k5ts3/T2570349??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:49:55.38/chk_obsdata//k5ts4/T2570349??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:49:56.10/k5log//k5ts1_log_newline 2006.257.03:49:56.83/k5log//k5ts2_log_newline 2006.257.03:49:57.56/k5log//k5ts3_log_newline 2006.257.03:49:58.29/k5log//k5ts4_log_newline 2006.257.03:49:58.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:49:58.31:setupk4=1 2006.257.03:49:58.31$setupk4/echo=on 2006.257.03:49:58.31$setupk4/pcalon 2006.257.03:49:58.31$pcalon/"no phase cal control is implemented here 2006.257.03:49:58.31$setupk4/"tpicd=stop 2006.257.03:49:58.31$setupk4/"rec=synch_on 2006.257.03:49:58.31$setupk4/"rec_mode=128 2006.257.03:49:58.31$setupk4/!* 2006.257.03:49:58.31$setupk4/recpk4 2006.257.03:49:58.31$recpk4/recpatch= 2006.257.03:49:58.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:49:58.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:49:58.31$setupk4/vck44 2006.257.03:49:58.31$vck44/valo=1,524.99 2006.257.03:49:58.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.03:49:58.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.03:49:58.32#ibcon#ireg 17 cls_cnt 0 2006.257.03:49:58.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:49:58.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:49:58.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:49:58.32#ibcon#enter wrdev, iclass 33, count 0 2006.257.03:49:58.32#ibcon#first serial, iclass 33, count 0 2006.257.03:49:58.32#ibcon#enter sib2, iclass 33, count 0 2006.257.03:49:58.32#ibcon#flushed, iclass 33, count 0 2006.257.03:49:58.32#ibcon#about to write, iclass 33, count 0 2006.257.03:49:58.32#ibcon#wrote, iclass 33, count 0 2006.257.03:49:58.32#ibcon#about to read 3, iclass 33, count 0 2006.257.03:49:58.33#ibcon#read 3, iclass 33, count 0 2006.257.03:49:58.33#ibcon#about to read 4, iclass 33, count 0 2006.257.03:49:58.33#ibcon#read 4, iclass 33, count 0 2006.257.03:49:58.33#ibcon#about to read 5, iclass 33, count 0 2006.257.03:49:58.33#ibcon#read 5, iclass 33, count 0 2006.257.03:49:58.33#ibcon#about to read 6, iclass 33, count 0 2006.257.03:49:58.33#ibcon#read 6, iclass 33, count 0 2006.257.03:49:58.33#ibcon#end of sib2, iclass 33, count 0 2006.257.03:49:58.33#ibcon#*mode == 0, iclass 33, count 0 2006.257.03:49:58.33#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.03:49:58.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:49:58.33#ibcon#*before write, iclass 33, count 0 2006.257.03:49:58.33#ibcon#enter sib2, iclass 33, count 0 2006.257.03:49:58.33#ibcon#flushed, iclass 33, count 0 2006.257.03:49:58.33#ibcon#about to write, iclass 33, count 0 2006.257.03:49:58.33#ibcon#wrote, iclass 33, count 0 2006.257.03:49:58.33#ibcon#about to read 3, iclass 33, count 0 2006.257.03:49:58.38#ibcon#read 3, iclass 33, count 0 2006.257.03:49:58.38#ibcon#about to read 4, iclass 33, count 0 2006.257.03:49:58.38#ibcon#read 4, iclass 33, count 0 2006.257.03:49:58.38#ibcon#about to read 5, iclass 33, count 0 2006.257.03:49:58.38#ibcon#read 5, iclass 33, count 0 2006.257.03:49:58.38#ibcon#about to read 6, iclass 33, count 0 2006.257.03:49:58.38#ibcon#read 6, iclass 33, count 0 2006.257.03:49:58.38#ibcon#end of sib2, iclass 33, count 0 2006.257.03:49:58.38#ibcon#*after write, iclass 33, count 0 2006.257.03:49:58.38#ibcon#*before return 0, iclass 33, count 0 2006.257.03:49:58.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:49:58.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:49:58.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.03:49:58.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.03:49:58.38$vck44/va=1,8 2006.257.03:49:58.38#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.03:49:58.38#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.03:49:58.38#ibcon#ireg 11 cls_cnt 2 2006.257.03:49:58.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:49:58.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:49:58.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:49:58.38#ibcon#enter wrdev, iclass 35, count 2 2006.257.03:49:58.38#ibcon#first serial, iclass 35, count 2 2006.257.03:49:58.38#ibcon#enter sib2, iclass 35, count 2 2006.257.03:49:58.38#ibcon#flushed, iclass 35, count 2 2006.257.03:49:58.38#ibcon#about to write, iclass 35, count 2 2006.257.03:49:58.38#ibcon#wrote, iclass 35, count 2 2006.257.03:49:58.38#ibcon#about to read 3, iclass 35, count 2 2006.257.03:49:58.40#ibcon#read 3, iclass 35, count 2 2006.257.03:49:58.40#ibcon#about to read 4, iclass 35, count 2 2006.257.03:49:58.40#ibcon#read 4, iclass 35, count 2 2006.257.03:49:58.40#ibcon#about to read 5, iclass 35, count 2 2006.257.03:49:58.40#ibcon#read 5, iclass 35, count 2 2006.257.03:49:58.40#ibcon#about to read 6, iclass 35, count 2 2006.257.03:49:58.40#ibcon#read 6, iclass 35, count 2 2006.257.03:49:58.40#ibcon#end of sib2, iclass 35, count 2 2006.257.03:49:58.40#ibcon#*mode == 0, iclass 35, count 2 2006.257.03:49:58.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.03:49:58.40#ibcon#[25=AT01-08\r\n] 2006.257.03:49:58.40#ibcon#*before write, iclass 35, count 2 2006.257.03:49:58.40#ibcon#enter sib2, iclass 35, count 2 2006.257.03:49:58.40#ibcon#flushed, iclass 35, count 2 2006.257.03:49:58.40#ibcon#about to write, iclass 35, count 2 2006.257.03:49:58.40#ibcon#wrote, iclass 35, count 2 2006.257.03:49:58.40#ibcon#about to read 3, iclass 35, count 2 2006.257.03:49:58.43#ibcon#read 3, iclass 35, count 2 2006.257.03:49:58.43#ibcon#about to read 4, iclass 35, count 2 2006.257.03:49:58.43#ibcon#read 4, iclass 35, count 2 2006.257.03:49:58.43#ibcon#about to read 5, iclass 35, count 2 2006.257.03:49:58.43#ibcon#read 5, iclass 35, count 2 2006.257.03:49:58.43#ibcon#about to read 6, iclass 35, count 2 2006.257.03:49:58.43#ibcon#read 6, iclass 35, count 2 2006.257.03:49:58.43#ibcon#end of sib2, iclass 35, count 2 2006.257.03:49:58.43#ibcon#*after write, iclass 35, count 2 2006.257.03:49:58.43#ibcon#*before return 0, iclass 35, count 2 2006.257.03:49:58.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:49:58.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:49:58.43#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.03:49:58.43#ibcon#ireg 7 cls_cnt 0 2006.257.03:49:58.43#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:49:58.55#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:49:58.55#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:49:58.55#ibcon#enter wrdev, iclass 35, count 0 2006.257.03:49:58.55#ibcon#first serial, iclass 35, count 0 2006.257.03:49:58.55#ibcon#enter sib2, iclass 35, count 0 2006.257.03:49:58.55#ibcon#flushed, iclass 35, count 0 2006.257.03:49:58.55#ibcon#about to write, iclass 35, count 0 2006.257.03:49:58.55#ibcon#wrote, iclass 35, count 0 2006.257.03:49:58.55#ibcon#about to read 3, iclass 35, count 0 2006.257.03:49:58.57#ibcon#read 3, iclass 35, count 0 2006.257.03:49:58.57#ibcon#about to read 4, iclass 35, count 0 2006.257.03:49:58.57#ibcon#read 4, iclass 35, count 0 2006.257.03:49:58.57#ibcon#about to read 5, iclass 35, count 0 2006.257.03:49:58.57#ibcon#read 5, iclass 35, count 0 2006.257.03:49:58.57#ibcon#about to read 6, iclass 35, count 0 2006.257.03:49:58.57#ibcon#read 6, iclass 35, count 0 2006.257.03:49:58.57#ibcon#end of sib2, iclass 35, count 0 2006.257.03:49:58.57#ibcon#*mode == 0, iclass 35, count 0 2006.257.03:49:58.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.03:49:58.57#ibcon#[25=USB\r\n] 2006.257.03:49:58.57#ibcon#*before write, iclass 35, count 0 2006.257.03:49:58.57#ibcon#enter sib2, iclass 35, count 0 2006.257.03:49:58.57#ibcon#flushed, iclass 35, count 0 2006.257.03:49:58.57#ibcon#about to write, iclass 35, count 0 2006.257.03:49:58.57#ibcon#wrote, iclass 35, count 0 2006.257.03:49:58.57#ibcon#about to read 3, iclass 35, count 0 2006.257.03:49:58.60#ibcon#read 3, iclass 35, count 0 2006.257.03:49:58.60#ibcon#about to read 4, iclass 35, count 0 2006.257.03:49:58.60#ibcon#read 4, iclass 35, count 0 2006.257.03:49:58.60#ibcon#about to read 5, iclass 35, count 0 2006.257.03:49:58.60#ibcon#read 5, iclass 35, count 0 2006.257.03:49:58.60#ibcon#about to read 6, iclass 35, count 0 2006.257.03:49:58.60#ibcon#read 6, iclass 35, count 0 2006.257.03:49:58.60#ibcon#end of sib2, iclass 35, count 0 2006.257.03:49:58.60#ibcon#*after write, iclass 35, count 0 2006.257.03:49:58.60#ibcon#*before return 0, iclass 35, count 0 2006.257.03:49:58.60#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:49:58.60#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:49:58.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.03:49:58.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.03:49:58.60$vck44/valo=2,534.99 2006.257.03:49:58.60#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.03:49:58.60#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.03:49:58.60#ibcon#ireg 17 cls_cnt 0 2006.257.03:49:58.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:49:58.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:49:58.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:49:58.60#ibcon#enter wrdev, iclass 37, count 0 2006.257.03:49:58.60#ibcon#first serial, iclass 37, count 0 2006.257.03:49:58.60#ibcon#enter sib2, iclass 37, count 0 2006.257.03:49:58.60#ibcon#flushed, iclass 37, count 0 2006.257.03:49:58.60#ibcon#about to write, iclass 37, count 0 2006.257.03:49:58.60#ibcon#wrote, iclass 37, count 0 2006.257.03:49:58.60#ibcon#about to read 3, iclass 37, count 0 2006.257.03:49:58.62#ibcon#read 3, iclass 37, count 0 2006.257.03:49:58.62#ibcon#about to read 4, iclass 37, count 0 2006.257.03:49:58.62#ibcon#read 4, iclass 37, count 0 2006.257.03:49:58.62#ibcon#about to read 5, iclass 37, count 0 2006.257.03:49:58.62#ibcon#read 5, iclass 37, count 0 2006.257.03:49:58.62#ibcon#about to read 6, iclass 37, count 0 2006.257.03:49:58.62#ibcon#read 6, iclass 37, count 0 2006.257.03:49:58.62#ibcon#end of sib2, iclass 37, count 0 2006.257.03:49:58.62#ibcon#*mode == 0, iclass 37, count 0 2006.257.03:49:58.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.03:49:58.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:49:58.62#ibcon#*before write, iclass 37, count 0 2006.257.03:49:58.62#ibcon#enter sib2, iclass 37, count 0 2006.257.03:49:58.62#ibcon#flushed, iclass 37, count 0 2006.257.03:49:58.62#ibcon#about to write, iclass 37, count 0 2006.257.03:49:58.62#ibcon#wrote, iclass 37, count 0 2006.257.03:49:58.62#ibcon#about to read 3, iclass 37, count 0 2006.257.03:49:58.66#ibcon#read 3, iclass 37, count 0 2006.257.03:49:58.66#ibcon#about to read 4, iclass 37, count 0 2006.257.03:49:58.66#ibcon#read 4, iclass 37, count 0 2006.257.03:49:58.66#ibcon#about to read 5, iclass 37, count 0 2006.257.03:49:58.66#ibcon#read 5, iclass 37, count 0 2006.257.03:49:58.66#ibcon#about to read 6, iclass 37, count 0 2006.257.03:49:58.66#ibcon#read 6, iclass 37, count 0 2006.257.03:49:58.66#ibcon#end of sib2, iclass 37, count 0 2006.257.03:49:58.66#ibcon#*after write, iclass 37, count 0 2006.257.03:49:58.66#ibcon#*before return 0, iclass 37, count 0 2006.257.03:49:58.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:49:58.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:49:58.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.03:49:58.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.03:49:58.66$vck44/va=2,7 2006.257.03:49:58.66#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.03:49:58.66#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.03:49:58.66#ibcon#ireg 11 cls_cnt 2 2006.257.03:49:58.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:49:58.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:49:58.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:49:58.72#ibcon#enter wrdev, iclass 39, count 2 2006.257.03:49:58.72#ibcon#first serial, iclass 39, count 2 2006.257.03:49:58.72#ibcon#enter sib2, iclass 39, count 2 2006.257.03:49:58.72#ibcon#flushed, iclass 39, count 2 2006.257.03:49:58.72#ibcon#about to write, iclass 39, count 2 2006.257.03:49:58.72#ibcon#wrote, iclass 39, count 2 2006.257.03:49:58.72#ibcon#about to read 3, iclass 39, count 2 2006.257.03:49:58.74#ibcon#read 3, iclass 39, count 2 2006.257.03:49:58.74#ibcon#about to read 4, iclass 39, count 2 2006.257.03:49:58.74#ibcon#read 4, iclass 39, count 2 2006.257.03:49:58.74#ibcon#about to read 5, iclass 39, count 2 2006.257.03:49:58.74#ibcon#read 5, iclass 39, count 2 2006.257.03:49:58.74#ibcon#about to read 6, iclass 39, count 2 2006.257.03:49:58.74#ibcon#read 6, iclass 39, count 2 2006.257.03:49:58.74#ibcon#end of sib2, iclass 39, count 2 2006.257.03:49:58.74#ibcon#*mode == 0, iclass 39, count 2 2006.257.03:49:58.74#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.03:49:58.74#ibcon#[25=AT02-07\r\n] 2006.257.03:49:58.74#ibcon#*before write, iclass 39, count 2 2006.257.03:49:58.74#ibcon#enter sib2, iclass 39, count 2 2006.257.03:49:58.74#ibcon#flushed, iclass 39, count 2 2006.257.03:49:58.74#ibcon#about to write, iclass 39, count 2 2006.257.03:49:58.74#ibcon#wrote, iclass 39, count 2 2006.257.03:49:58.74#ibcon#about to read 3, iclass 39, count 2 2006.257.03:49:58.77#ibcon#read 3, iclass 39, count 2 2006.257.03:49:58.77#ibcon#about to read 4, iclass 39, count 2 2006.257.03:49:58.77#ibcon#read 4, iclass 39, count 2 2006.257.03:49:58.77#ibcon#about to read 5, iclass 39, count 2 2006.257.03:49:58.77#ibcon#read 5, iclass 39, count 2 2006.257.03:49:58.77#ibcon#about to read 6, iclass 39, count 2 2006.257.03:49:58.77#ibcon#read 6, iclass 39, count 2 2006.257.03:49:58.77#ibcon#end of sib2, iclass 39, count 2 2006.257.03:49:58.77#ibcon#*after write, iclass 39, count 2 2006.257.03:49:58.77#ibcon#*before return 0, iclass 39, count 2 2006.257.03:49:58.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:49:58.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:49:58.77#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.03:49:58.77#ibcon#ireg 7 cls_cnt 0 2006.257.03:49:58.77#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:49:58.89#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:49:58.89#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:49:58.89#ibcon#enter wrdev, iclass 39, count 0 2006.257.03:49:58.89#ibcon#first serial, iclass 39, count 0 2006.257.03:49:58.89#ibcon#enter sib2, iclass 39, count 0 2006.257.03:49:58.89#ibcon#flushed, iclass 39, count 0 2006.257.03:49:58.89#ibcon#about to write, iclass 39, count 0 2006.257.03:49:58.89#ibcon#wrote, iclass 39, count 0 2006.257.03:49:58.89#ibcon#about to read 3, iclass 39, count 0 2006.257.03:49:58.91#ibcon#read 3, iclass 39, count 0 2006.257.03:49:58.91#ibcon#about to read 4, iclass 39, count 0 2006.257.03:49:58.91#ibcon#read 4, iclass 39, count 0 2006.257.03:49:58.91#ibcon#about to read 5, iclass 39, count 0 2006.257.03:49:58.91#ibcon#read 5, iclass 39, count 0 2006.257.03:49:58.91#ibcon#about to read 6, iclass 39, count 0 2006.257.03:49:58.91#ibcon#read 6, iclass 39, count 0 2006.257.03:49:58.91#ibcon#end of sib2, iclass 39, count 0 2006.257.03:49:58.91#ibcon#*mode == 0, iclass 39, count 0 2006.257.03:49:58.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.03:49:58.91#ibcon#[25=USB\r\n] 2006.257.03:49:58.91#ibcon#*before write, iclass 39, count 0 2006.257.03:49:58.91#ibcon#enter sib2, iclass 39, count 0 2006.257.03:49:58.91#ibcon#flushed, iclass 39, count 0 2006.257.03:49:58.91#ibcon#about to write, iclass 39, count 0 2006.257.03:49:58.91#ibcon#wrote, iclass 39, count 0 2006.257.03:49:58.91#ibcon#about to read 3, iclass 39, count 0 2006.257.03:49:58.94#ibcon#read 3, iclass 39, count 0 2006.257.03:49:58.94#ibcon#about to read 4, iclass 39, count 0 2006.257.03:49:58.94#ibcon#read 4, iclass 39, count 0 2006.257.03:49:58.94#ibcon#about to read 5, iclass 39, count 0 2006.257.03:49:58.94#ibcon#read 5, iclass 39, count 0 2006.257.03:49:58.94#ibcon#about to read 6, iclass 39, count 0 2006.257.03:49:58.94#ibcon#read 6, iclass 39, count 0 2006.257.03:49:58.94#ibcon#end of sib2, iclass 39, count 0 2006.257.03:49:58.94#ibcon#*after write, iclass 39, count 0 2006.257.03:49:58.94#ibcon#*before return 0, iclass 39, count 0 2006.257.03:49:58.94#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:49:58.94#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:49:58.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.03:49:58.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.03:49:58.94$vck44/valo=3,564.99 2006.257.03:49:58.94#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.03:49:58.94#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.03:49:58.94#ibcon#ireg 17 cls_cnt 0 2006.257.03:49:58.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:49:58.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:49:58.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:49:58.94#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:49:58.94#ibcon#first serial, iclass 3, count 0 2006.257.03:49:58.94#ibcon#enter sib2, iclass 3, count 0 2006.257.03:49:58.94#ibcon#flushed, iclass 3, count 0 2006.257.03:49:58.94#ibcon#about to write, iclass 3, count 0 2006.257.03:49:58.94#ibcon#wrote, iclass 3, count 0 2006.257.03:49:58.94#ibcon#about to read 3, iclass 3, count 0 2006.257.03:49:58.96#ibcon#read 3, iclass 3, count 0 2006.257.03:49:58.96#ibcon#about to read 4, iclass 3, count 0 2006.257.03:49:58.96#ibcon#read 4, iclass 3, count 0 2006.257.03:49:58.96#ibcon#about to read 5, iclass 3, count 0 2006.257.03:49:58.96#ibcon#read 5, iclass 3, count 0 2006.257.03:49:58.96#ibcon#about to read 6, iclass 3, count 0 2006.257.03:49:58.96#ibcon#read 6, iclass 3, count 0 2006.257.03:49:58.96#ibcon#end of sib2, iclass 3, count 0 2006.257.03:49:58.96#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:49:58.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:49:58.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:49:58.96#ibcon#*before write, iclass 3, count 0 2006.257.03:49:58.96#ibcon#enter sib2, iclass 3, count 0 2006.257.03:49:58.96#ibcon#flushed, iclass 3, count 0 2006.257.03:49:58.96#ibcon#about to write, iclass 3, count 0 2006.257.03:49:58.96#ibcon#wrote, iclass 3, count 0 2006.257.03:49:58.96#ibcon#about to read 3, iclass 3, count 0 2006.257.03:49:59.00#ibcon#read 3, iclass 3, count 0 2006.257.03:49:59.00#ibcon#about to read 4, iclass 3, count 0 2006.257.03:49:59.00#ibcon#read 4, iclass 3, count 0 2006.257.03:49:59.00#ibcon#about to read 5, iclass 3, count 0 2006.257.03:49:59.00#ibcon#read 5, iclass 3, count 0 2006.257.03:49:59.00#ibcon#about to read 6, iclass 3, count 0 2006.257.03:49:59.00#ibcon#read 6, iclass 3, count 0 2006.257.03:49:59.00#ibcon#end of sib2, iclass 3, count 0 2006.257.03:49:59.00#ibcon#*after write, iclass 3, count 0 2006.257.03:49:59.00#ibcon#*before return 0, iclass 3, count 0 2006.257.03:49:59.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:49:59.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:49:59.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:49:59.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:49:59.00$vck44/va=3,8 2006.257.03:49:59.00#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.03:49:59.00#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.03:49:59.00#ibcon#ireg 11 cls_cnt 2 2006.257.03:49:59.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:49:59.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:49:59.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:49:59.06#ibcon#enter wrdev, iclass 5, count 2 2006.257.03:49:59.06#ibcon#first serial, iclass 5, count 2 2006.257.03:49:59.06#ibcon#enter sib2, iclass 5, count 2 2006.257.03:49:59.06#ibcon#flushed, iclass 5, count 2 2006.257.03:49:59.06#ibcon#about to write, iclass 5, count 2 2006.257.03:49:59.06#ibcon#wrote, iclass 5, count 2 2006.257.03:49:59.06#ibcon#about to read 3, iclass 5, count 2 2006.257.03:49:59.08#ibcon#read 3, iclass 5, count 2 2006.257.03:49:59.08#ibcon#about to read 4, iclass 5, count 2 2006.257.03:49:59.08#ibcon#read 4, iclass 5, count 2 2006.257.03:49:59.08#ibcon#about to read 5, iclass 5, count 2 2006.257.03:49:59.08#ibcon#read 5, iclass 5, count 2 2006.257.03:49:59.08#ibcon#about to read 6, iclass 5, count 2 2006.257.03:49:59.08#ibcon#read 6, iclass 5, count 2 2006.257.03:49:59.08#ibcon#end of sib2, iclass 5, count 2 2006.257.03:49:59.08#ibcon#*mode == 0, iclass 5, count 2 2006.257.03:49:59.08#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.03:49:59.08#ibcon#[25=AT03-08\r\n] 2006.257.03:49:59.08#ibcon#*before write, iclass 5, count 2 2006.257.03:49:59.08#ibcon#enter sib2, iclass 5, count 2 2006.257.03:49:59.08#ibcon#flushed, iclass 5, count 2 2006.257.03:49:59.08#ibcon#about to write, iclass 5, count 2 2006.257.03:49:59.08#ibcon#wrote, iclass 5, count 2 2006.257.03:49:59.08#ibcon#about to read 3, iclass 5, count 2 2006.257.03:49:59.11#ibcon#read 3, iclass 5, count 2 2006.257.03:49:59.11#ibcon#about to read 4, iclass 5, count 2 2006.257.03:49:59.11#ibcon#read 4, iclass 5, count 2 2006.257.03:49:59.11#ibcon#about to read 5, iclass 5, count 2 2006.257.03:49:59.11#ibcon#read 5, iclass 5, count 2 2006.257.03:49:59.11#ibcon#about to read 6, iclass 5, count 2 2006.257.03:49:59.11#ibcon#read 6, iclass 5, count 2 2006.257.03:49:59.11#ibcon#end of sib2, iclass 5, count 2 2006.257.03:49:59.11#ibcon#*after write, iclass 5, count 2 2006.257.03:49:59.11#ibcon#*before return 0, iclass 5, count 2 2006.257.03:49:59.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:49:59.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:49:59.11#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.03:49:59.11#ibcon#ireg 7 cls_cnt 0 2006.257.03:49:59.11#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:49:59.23#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:49:59.23#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:49:59.23#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:49:59.23#ibcon#first serial, iclass 5, count 0 2006.257.03:49:59.23#ibcon#enter sib2, iclass 5, count 0 2006.257.03:49:59.23#ibcon#flushed, iclass 5, count 0 2006.257.03:49:59.23#ibcon#about to write, iclass 5, count 0 2006.257.03:49:59.23#ibcon#wrote, iclass 5, count 0 2006.257.03:49:59.23#ibcon#about to read 3, iclass 5, count 0 2006.257.03:49:59.25#ibcon#read 3, iclass 5, count 0 2006.257.03:49:59.25#ibcon#about to read 4, iclass 5, count 0 2006.257.03:49:59.25#ibcon#read 4, iclass 5, count 0 2006.257.03:49:59.25#ibcon#about to read 5, iclass 5, count 0 2006.257.03:49:59.25#ibcon#read 5, iclass 5, count 0 2006.257.03:49:59.25#ibcon#about to read 6, iclass 5, count 0 2006.257.03:49:59.25#ibcon#read 6, iclass 5, count 0 2006.257.03:49:59.25#ibcon#end of sib2, iclass 5, count 0 2006.257.03:49:59.25#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:49:59.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:49:59.25#ibcon#[25=USB\r\n] 2006.257.03:49:59.25#ibcon#*before write, iclass 5, count 0 2006.257.03:49:59.25#ibcon#enter sib2, iclass 5, count 0 2006.257.03:49:59.25#ibcon#flushed, iclass 5, count 0 2006.257.03:49:59.25#ibcon#about to write, iclass 5, count 0 2006.257.03:49:59.25#ibcon#wrote, iclass 5, count 0 2006.257.03:49:59.25#ibcon#about to read 3, iclass 5, count 0 2006.257.03:49:59.28#ibcon#read 3, iclass 5, count 0 2006.257.03:49:59.28#ibcon#about to read 4, iclass 5, count 0 2006.257.03:49:59.28#ibcon#read 4, iclass 5, count 0 2006.257.03:49:59.28#ibcon#about to read 5, iclass 5, count 0 2006.257.03:49:59.28#ibcon#read 5, iclass 5, count 0 2006.257.03:49:59.28#ibcon#about to read 6, iclass 5, count 0 2006.257.03:49:59.28#ibcon#read 6, iclass 5, count 0 2006.257.03:49:59.28#ibcon#end of sib2, iclass 5, count 0 2006.257.03:49:59.28#ibcon#*after write, iclass 5, count 0 2006.257.03:49:59.28#ibcon#*before return 0, iclass 5, count 0 2006.257.03:49:59.28#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:49:59.28#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:49:59.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:49:59.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:49:59.28$vck44/valo=4,624.99 2006.257.03:49:59.28#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.03:49:59.28#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.03:49:59.28#ibcon#ireg 17 cls_cnt 0 2006.257.03:49:59.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:49:59.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:49:59.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:49:59.28#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:49:59.28#ibcon#first serial, iclass 7, count 0 2006.257.03:49:59.28#ibcon#enter sib2, iclass 7, count 0 2006.257.03:49:59.28#ibcon#flushed, iclass 7, count 0 2006.257.03:49:59.28#ibcon#about to write, iclass 7, count 0 2006.257.03:49:59.28#ibcon#wrote, iclass 7, count 0 2006.257.03:49:59.28#ibcon#about to read 3, iclass 7, count 0 2006.257.03:49:59.30#ibcon#read 3, iclass 7, count 0 2006.257.03:49:59.30#ibcon#about to read 4, iclass 7, count 0 2006.257.03:49:59.30#ibcon#read 4, iclass 7, count 0 2006.257.03:49:59.30#ibcon#about to read 5, iclass 7, count 0 2006.257.03:49:59.30#ibcon#read 5, iclass 7, count 0 2006.257.03:49:59.30#ibcon#about to read 6, iclass 7, count 0 2006.257.03:49:59.30#ibcon#read 6, iclass 7, count 0 2006.257.03:49:59.30#ibcon#end of sib2, iclass 7, count 0 2006.257.03:49:59.30#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:49:59.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:49:59.30#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:49:59.30#ibcon#*before write, iclass 7, count 0 2006.257.03:49:59.30#ibcon#enter sib2, iclass 7, count 0 2006.257.03:49:59.30#ibcon#flushed, iclass 7, count 0 2006.257.03:49:59.30#ibcon#about to write, iclass 7, count 0 2006.257.03:49:59.30#ibcon#wrote, iclass 7, count 0 2006.257.03:49:59.30#ibcon#about to read 3, iclass 7, count 0 2006.257.03:49:59.34#ibcon#read 3, iclass 7, count 0 2006.257.03:49:59.34#ibcon#about to read 4, iclass 7, count 0 2006.257.03:49:59.34#ibcon#read 4, iclass 7, count 0 2006.257.03:49:59.34#ibcon#about to read 5, iclass 7, count 0 2006.257.03:49:59.34#ibcon#read 5, iclass 7, count 0 2006.257.03:49:59.34#ibcon#about to read 6, iclass 7, count 0 2006.257.03:49:59.34#ibcon#read 6, iclass 7, count 0 2006.257.03:49:59.34#ibcon#end of sib2, iclass 7, count 0 2006.257.03:49:59.34#ibcon#*after write, iclass 7, count 0 2006.257.03:49:59.34#ibcon#*before return 0, iclass 7, count 0 2006.257.03:49:59.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:49:59.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:49:59.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:49:59.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:49:59.34$vck44/va=4,7 2006.257.03:49:59.34#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.03:49:59.34#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.03:49:59.34#ibcon#ireg 11 cls_cnt 2 2006.257.03:49:59.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:49:59.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:49:59.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:49:59.40#ibcon#enter wrdev, iclass 11, count 2 2006.257.03:49:59.40#ibcon#first serial, iclass 11, count 2 2006.257.03:49:59.40#ibcon#enter sib2, iclass 11, count 2 2006.257.03:49:59.40#ibcon#flushed, iclass 11, count 2 2006.257.03:49:59.40#ibcon#about to write, iclass 11, count 2 2006.257.03:49:59.40#ibcon#wrote, iclass 11, count 2 2006.257.03:49:59.40#ibcon#about to read 3, iclass 11, count 2 2006.257.03:49:59.42#ibcon#read 3, iclass 11, count 2 2006.257.03:49:59.42#ibcon#about to read 4, iclass 11, count 2 2006.257.03:49:59.42#ibcon#read 4, iclass 11, count 2 2006.257.03:49:59.42#ibcon#about to read 5, iclass 11, count 2 2006.257.03:49:59.42#ibcon#read 5, iclass 11, count 2 2006.257.03:49:59.42#ibcon#about to read 6, iclass 11, count 2 2006.257.03:49:59.42#ibcon#read 6, iclass 11, count 2 2006.257.03:49:59.42#ibcon#end of sib2, iclass 11, count 2 2006.257.03:49:59.42#ibcon#*mode == 0, iclass 11, count 2 2006.257.03:49:59.42#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.03:49:59.42#ibcon#[25=AT04-07\r\n] 2006.257.03:49:59.42#ibcon#*before write, iclass 11, count 2 2006.257.03:49:59.42#ibcon#enter sib2, iclass 11, count 2 2006.257.03:49:59.42#ibcon#flushed, iclass 11, count 2 2006.257.03:49:59.42#ibcon#about to write, iclass 11, count 2 2006.257.03:49:59.42#ibcon#wrote, iclass 11, count 2 2006.257.03:49:59.42#ibcon#about to read 3, iclass 11, count 2 2006.257.03:49:59.45#ibcon#read 3, iclass 11, count 2 2006.257.03:49:59.45#ibcon#about to read 4, iclass 11, count 2 2006.257.03:49:59.45#ibcon#read 4, iclass 11, count 2 2006.257.03:49:59.45#ibcon#about to read 5, iclass 11, count 2 2006.257.03:49:59.45#ibcon#read 5, iclass 11, count 2 2006.257.03:49:59.45#ibcon#about to read 6, iclass 11, count 2 2006.257.03:49:59.45#ibcon#read 6, iclass 11, count 2 2006.257.03:49:59.45#ibcon#end of sib2, iclass 11, count 2 2006.257.03:49:59.45#ibcon#*after write, iclass 11, count 2 2006.257.03:49:59.45#ibcon#*before return 0, iclass 11, count 2 2006.257.03:49:59.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:49:59.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:49:59.45#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.03:49:59.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:49:59.45#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:49:59.57#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:49:59.57#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:49:59.57#ibcon#enter wrdev, iclass 11, count 0 2006.257.03:49:59.57#ibcon#first serial, iclass 11, count 0 2006.257.03:49:59.57#ibcon#enter sib2, iclass 11, count 0 2006.257.03:49:59.57#ibcon#flushed, iclass 11, count 0 2006.257.03:49:59.57#ibcon#about to write, iclass 11, count 0 2006.257.03:49:59.57#ibcon#wrote, iclass 11, count 0 2006.257.03:49:59.57#ibcon#about to read 3, iclass 11, count 0 2006.257.03:49:59.59#ibcon#read 3, iclass 11, count 0 2006.257.03:49:59.59#ibcon#about to read 4, iclass 11, count 0 2006.257.03:49:59.59#ibcon#read 4, iclass 11, count 0 2006.257.03:49:59.59#ibcon#about to read 5, iclass 11, count 0 2006.257.03:49:59.59#ibcon#read 5, iclass 11, count 0 2006.257.03:49:59.59#ibcon#about to read 6, iclass 11, count 0 2006.257.03:49:59.59#ibcon#read 6, iclass 11, count 0 2006.257.03:49:59.59#ibcon#end of sib2, iclass 11, count 0 2006.257.03:49:59.59#ibcon#*mode == 0, iclass 11, count 0 2006.257.03:49:59.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.03:49:59.59#ibcon#[25=USB\r\n] 2006.257.03:49:59.59#ibcon#*before write, iclass 11, count 0 2006.257.03:49:59.59#ibcon#enter sib2, iclass 11, count 0 2006.257.03:49:59.59#ibcon#flushed, iclass 11, count 0 2006.257.03:49:59.59#ibcon#about to write, iclass 11, count 0 2006.257.03:49:59.59#ibcon#wrote, iclass 11, count 0 2006.257.03:49:59.59#ibcon#about to read 3, iclass 11, count 0 2006.257.03:49:59.62#ibcon#read 3, iclass 11, count 0 2006.257.03:49:59.62#ibcon#about to read 4, iclass 11, count 0 2006.257.03:49:59.62#ibcon#read 4, iclass 11, count 0 2006.257.03:49:59.62#ibcon#about to read 5, iclass 11, count 0 2006.257.03:49:59.62#ibcon#read 5, iclass 11, count 0 2006.257.03:49:59.62#ibcon#about to read 6, iclass 11, count 0 2006.257.03:49:59.62#ibcon#read 6, iclass 11, count 0 2006.257.03:49:59.62#ibcon#end of sib2, iclass 11, count 0 2006.257.03:49:59.62#ibcon#*after write, iclass 11, count 0 2006.257.03:49:59.62#ibcon#*before return 0, iclass 11, count 0 2006.257.03:49:59.62#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:49:59.62#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:49:59.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.03:49:59.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.03:49:59.62$vck44/valo=5,734.99 2006.257.03:49:59.62#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.03:49:59.62#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.03:49:59.62#ibcon#ireg 17 cls_cnt 0 2006.257.03:49:59.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:49:59.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:49:59.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:49:59.62#ibcon#enter wrdev, iclass 13, count 0 2006.257.03:49:59.62#ibcon#first serial, iclass 13, count 0 2006.257.03:49:59.62#ibcon#enter sib2, iclass 13, count 0 2006.257.03:49:59.62#ibcon#flushed, iclass 13, count 0 2006.257.03:49:59.62#ibcon#about to write, iclass 13, count 0 2006.257.03:49:59.62#ibcon#wrote, iclass 13, count 0 2006.257.03:49:59.62#ibcon#about to read 3, iclass 13, count 0 2006.257.03:49:59.64#ibcon#read 3, iclass 13, count 0 2006.257.03:49:59.64#ibcon#about to read 4, iclass 13, count 0 2006.257.03:49:59.64#ibcon#read 4, iclass 13, count 0 2006.257.03:49:59.64#ibcon#about to read 5, iclass 13, count 0 2006.257.03:49:59.64#ibcon#read 5, iclass 13, count 0 2006.257.03:49:59.64#ibcon#about to read 6, iclass 13, count 0 2006.257.03:49:59.64#ibcon#read 6, iclass 13, count 0 2006.257.03:49:59.64#ibcon#end of sib2, iclass 13, count 0 2006.257.03:49:59.64#ibcon#*mode == 0, iclass 13, count 0 2006.257.03:49:59.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.03:49:59.64#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:49:59.64#ibcon#*before write, iclass 13, count 0 2006.257.03:49:59.64#ibcon#enter sib2, iclass 13, count 0 2006.257.03:49:59.64#ibcon#flushed, iclass 13, count 0 2006.257.03:49:59.64#ibcon#about to write, iclass 13, count 0 2006.257.03:49:59.64#ibcon#wrote, iclass 13, count 0 2006.257.03:49:59.64#ibcon#about to read 3, iclass 13, count 0 2006.257.03:49:59.68#ibcon#read 3, iclass 13, count 0 2006.257.03:49:59.68#ibcon#about to read 4, iclass 13, count 0 2006.257.03:49:59.68#ibcon#read 4, iclass 13, count 0 2006.257.03:49:59.68#ibcon#about to read 5, iclass 13, count 0 2006.257.03:49:59.68#ibcon#read 5, iclass 13, count 0 2006.257.03:49:59.68#ibcon#about to read 6, iclass 13, count 0 2006.257.03:49:59.68#ibcon#read 6, iclass 13, count 0 2006.257.03:49:59.68#ibcon#end of sib2, iclass 13, count 0 2006.257.03:49:59.68#ibcon#*after write, iclass 13, count 0 2006.257.03:49:59.68#ibcon#*before return 0, iclass 13, count 0 2006.257.03:49:59.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:49:59.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:49:59.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.03:49:59.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.03:49:59.68$vck44/va=5,4 2006.257.03:49:59.68#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.03:49:59.68#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.03:49:59.68#ibcon#ireg 11 cls_cnt 2 2006.257.03:49:59.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:49:59.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:49:59.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:49:59.74#ibcon#enter wrdev, iclass 15, count 2 2006.257.03:49:59.74#ibcon#first serial, iclass 15, count 2 2006.257.03:49:59.74#ibcon#enter sib2, iclass 15, count 2 2006.257.03:49:59.74#ibcon#flushed, iclass 15, count 2 2006.257.03:49:59.74#ibcon#about to write, iclass 15, count 2 2006.257.03:49:59.74#ibcon#wrote, iclass 15, count 2 2006.257.03:49:59.74#ibcon#about to read 3, iclass 15, count 2 2006.257.03:49:59.76#ibcon#read 3, iclass 15, count 2 2006.257.03:49:59.76#ibcon#about to read 4, iclass 15, count 2 2006.257.03:49:59.76#ibcon#read 4, iclass 15, count 2 2006.257.03:49:59.76#ibcon#about to read 5, iclass 15, count 2 2006.257.03:49:59.76#ibcon#read 5, iclass 15, count 2 2006.257.03:49:59.76#ibcon#about to read 6, iclass 15, count 2 2006.257.03:49:59.76#ibcon#read 6, iclass 15, count 2 2006.257.03:49:59.76#ibcon#end of sib2, iclass 15, count 2 2006.257.03:49:59.76#ibcon#*mode == 0, iclass 15, count 2 2006.257.03:49:59.76#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.03:49:59.76#ibcon#[25=AT05-04\r\n] 2006.257.03:49:59.76#ibcon#*before write, iclass 15, count 2 2006.257.03:49:59.76#ibcon#enter sib2, iclass 15, count 2 2006.257.03:49:59.76#ibcon#flushed, iclass 15, count 2 2006.257.03:49:59.76#ibcon#about to write, iclass 15, count 2 2006.257.03:49:59.76#ibcon#wrote, iclass 15, count 2 2006.257.03:49:59.76#ibcon#about to read 3, iclass 15, count 2 2006.257.03:49:59.79#ibcon#read 3, iclass 15, count 2 2006.257.03:49:59.79#ibcon#about to read 4, iclass 15, count 2 2006.257.03:49:59.79#ibcon#read 4, iclass 15, count 2 2006.257.03:49:59.79#ibcon#about to read 5, iclass 15, count 2 2006.257.03:49:59.79#ibcon#read 5, iclass 15, count 2 2006.257.03:49:59.79#ibcon#about to read 6, iclass 15, count 2 2006.257.03:49:59.79#ibcon#read 6, iclass 15, count 2 2006.257.03:49:59.79#ibcon#end of sib2, iclass 15, count 2 2006.257.03:49:59.79#ibcon#*after write, iclass 15, count 2 2006.257.03:49:59.79#ibcon#*before return 0, iclass 15, count 2 2006.257.03:49:59.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:49:59.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:49:59.79#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.03:49:59.79#ibcon#ireg 7 cls_cnt 0 2006.257.03:49:59.79#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:49:59.91#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:49:59.91#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:49:59.91#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:49:59.91#ibcon#first serial, iclass 15, count 0 2006.257.03:49:59.91#ibcon#enter sib2, iclass 15, count 0 2006.257.03:49:59.91#ibcon#flushed, iclass 15, count 0 2006.257.03:49:59.91#ibcon#about to write, iclass 15, count 0 2006.257.03:49:59.91#ibcon#wrote, iclass 15, count 0 2006.257.03:49:59.91#ibcon#about to read 3, iclass 15, count 0 2006.257.03:49:59.93#ibcon#read 3, iclass 15, count 0 2006.257.03:49:59.93#ibcon#about to read 4, iclass 15, count 0 2006.257.03:49:59.93#ibcon#read 4, iclass 15, count 0 2006.257.03:49:59.93#ibcon#about to read 5, iclass 15, count 0 2006.257.03:49:59.93#ibcon#read 5, iclass 15, count 0 2006.257.03:49:59.93#ibcon#about to read 6, iclass 15, count 0 2006.257.03:49:59.93#ibcon#read 6, iclass 15, count 0 2006.257.03:49:59.93#ibcon#end of sib2, iclass 15, count 0 2006.257.03:49:59.93#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:49:59.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:49:59.93#ibcon#[25=USB\r\n] 2006.257.03:49:59.93#ibcon#*before write, iclass 15, count 0 2006.257.03:49:59.93#ibcon#enter sib2, iclass 15, count 0 2006.257.03:49:59.93#ibcon#flushed, iclass 15, count 0 2006.257.03:49:59.93#ibcon#about to write, iclass 15, count 0 2006.257.03:49:59.93#ibcon#wrote, iclass 15, count 0 2006.257.03:49:59.93#ibcon#about to read 3, iclass 15, count 0 2006.257.03:49:59.96#ibcon#read 3, iclass 15, count 0 2006.257.03:49:59.96#ibcon#about to read 4, iclass 15, count 0 2006.257.03:49:59.96#ibcon#read 4, iclass 15, count 0 2006.257.03:49:59.96#ibcon#about to read 5, iclass 15, count 0 2006.257.03:49:59.96#ibcon#read 5, iclass 15, count 0 2006.257.03:49:59.96#ibcon#about to read 6, iclass 15, count 0 2006.257.03:49:59.96#ibcon#read 6, iclass 15, count 0 2006.257.03:49:59.96#ibcon#end of sib2, iclass 15, count 0 2006.257.03:49:59.96#ibcon#*after write, iclass 15, count 0 2006.257.03:49:59.96#ibcon#*before return 0, iclass 15, count 0 2006.257.03:49:59.96#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:49:59.96#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:49:59.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:49:59.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:49:59.96$vck44/valo=6,814.99 2006.257.03:49:59.96#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.03:49:59.96#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.03:49:59.96#ibcon#ireg 17 cls_cnt 0 2006.257.03:49:59.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:49:59.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:49:59.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:49:59.96#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:49:59.96#ibcon#first serial, iclass 17, count 0 2006.257.03:49:59.96#ibcon#enter sib2, iclass 17, count 0 2006.257.03:49:59.96#ibcon#flushed, iclass 17, count 0 2006.257.03:49:59.96#ibcon#about to write, iclass 17, count 0 2006.257.03:49:59.96#ibcon#wrote, iclass 17, count 0 2006.257.03:49:59.96#ibcon#about to read 3, iclass 17, count 0 2006.257.03:49:59.98#ibcon#read 3, iclass 17, count 0 2006.257.03:49:59.98#ibcon#about to read 4, iclass 17, count 0 2006.257.03:49:59.98#ibcon#read 4, iclass 17, count 0 2006.257.03:49:59.98#ibcon#about to read 5, iclass 17, count 0 2006.257.03:49:59.98#ibcon#read 5, iclass 17, count 0 2006.257.03:49:59.98#ibcon#about to read 6, iclass 17, count 0 2006.257.03:49:59.98#ibcon#read 6, iclass 17, count 0 2006.257.03:49:59.98#ibcon#end of sib2, iclass 17, count 0 2006.257.03:49:59.98#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:49:59.98#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:49:59.98#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:49:59.98#ibcon#*before write, iclass 17, count 0 2006.257.03:49:59.98#ibcon#enter sib2, iclass 17, count 0 2006.257.03:49:59.98#ibcon#flushed, iclass 17, count 0 2006.257.03:49:59.98#ibcon#about to write, iclass 17, count 0 2006.257.03:49:59.98#ibcon#wrote, iclass 17, count 0 2006.257.03:49:59.98#ibcon#about to read 3, iclass 17, count 0 2006.257.03:50:00.02#ibcon#read 3, iclass 17, count 0 2006.257.03:50:00.02#ibcon#about to read 4, iclass 17, count 0 2006.257.03:50:00.02#ibcon#read 4, iclass 17, count 0 2006.257.03:50:00.02#ibcon#about to read 5, iclass 17, count 0 2006.257.03:50:00.02#ibcon#read 5, iclass 17, count 0 2006.257.03:50:00.02#ibcon#about to read 6, iclass 17, count 0 2006.257.03:50:00.02#ibcon#read 6, iclass 17, count 0 2006.257.03:50:00.02#ibcon#end of sib2, iclass 17, count 0 2006.257.03:50:00.02#ibcon#*after write, iclass 17, count 0 2006.257.03:50:00.02#ibcon#*before return 0, iclass 17, count 0 2006.257.03:50:00.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:50:00.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:50:00.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:50:00.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:50:00.02$vck44/va=6,4 2006.257.03:50:00.02#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.03:50:00.02#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.03:50:00.02#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:00.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:00.08#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:00.08#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:00.08#ibcon#enter wrdev, iclass 19, count 2 2006.257.03:50:00.08#ibcon#first serial, iclass 19, count 2 2006.257.03:50:00.08#ibcon#enter sib2, iclass 19, count 2 2006.257.03:50:00.08#ibcon#flushed, iclass 19, count 2 2006.257.03:50:00.08#ibcon#about to write, iclass 19, count 2 2006.257.03:50:00.08#ibcon#wrote, iclass 19, count 2 2006.257.03:50:00.08#ibcon#about to read 3, iclass 19, count 2 2006.257.03:50:00.10#ibcon#read 3, iclass 19, count 2 2006.257.03:50:00.10#ibcon#about to read 4, iclass 19, count 2 2006.257.03:50:00.10#ibcon#read 4, iclass 19, count 2 2006.257.03:50:00.10#ibcon#about to read 5, iclass 19, count 2 2006.257.03:50:00.10#ibcon#read 5, iclass 19, count 2 2006.257.03:50:00.10#ibcon#about to read 6, iclass 19, count 2 2006.257.03:50:00.10#ibcon#read 6, iclass 19, count 2 2006.257.03:50:00.10#ibcon#end of sib2, iclass 19, count 2 2006.257.03:50:00.10#ibcon#*mode == 0, iclass 19, count 2 2006.257.03:50:00.10#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.03:50:00.10#ibcon#[25=AT06-04\r\n] 2006.257.03:50:00.10#ibcon#*before write, iclass 19, count 2 2006.257.03:50:00.10#ibcon#enter sib2, iclass 19, count 2 2006.257.03:50:00.10#ibcon#flushed, iclass 19, count 2 2006.257.03:50:00.10#ibcon#about to write, iclass 19, count 2 2006.257.03:50:00.10#ibcon#wrote, iclass 19, count 2 2006.257.03:50:00.10#ibcon#about to read 3, iclass 19, count 2 2006.257.03:50:00.13#ibcon#read 3, iclass 19, count 2 2006.257.03:50:00.13#ibcon#about to read 4, iclass 19, count 2 2006.257.03:50:00.13#ibcon#read 4, iclass 19, count 2 2006.257.03:50:00.13#ibcon#about to read 5, iclass 19, count 2 2006.257.03:50:00.13#ibcon#read 5, iclass 19, count 2 2006.257.03:50:00.13#ibcon#about to read 6, iclass 19, count 2 2006.257.03:50:00.13#ibcon#read 6, iclass 19, count 2 2006.257.03:50:00.13#ibcon#end of sib2, iclass 19, count 2 2006.257.03:50:00.13#ibcon#*after write, iclass 19, count 2 2006.257.03:50:00.13#ibcon#*before return 0, iclass 19, count 2 2006.257.03:50:00.13#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:00.13#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:00.13#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.03:50:00.13#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:00.13#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:00.25#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:00.25#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:00.25#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:50:00.25#ibcon#first serial, iclass 19, count 0 2006.257.03:50:00.25#ibcon#enter sib2, iclass 19, count 0 2006.257.03:50:00.25#ibcon#flushed, iclass 19, count 0 2006.257.03:50:00.25#ibcon#about to write, iclass 19, count 0 2006.257.03:50:00.25#ibcon#wrote, iclass 19, count 0 2006.257.03:50:00.25#ibcon#about to read 3, iclass 19, count 0 2006.257.03:50:00.27#ibcon#read 3, iclass 19, count 0 2006.257.03:50:00.27#ibcon#about to read 4, iclass 19, count 0 2006.257.03:50:00.27#ibcon#read 4, iclass 19, count 0 2006.257.03:50:00.27#ibcon#about to read 5, iclass 19, count 0 2006.257.03:50:00.27#ibcon#read 5, iclass 19, count 0 2006.257.03:50:00.27#ibcon#about to read 6, iclass 19, count 0 2006.257.03:50:00.27#ibcon#read 6, iclass 19, count 0 2006.257.03:50:00.27#ibcon#end of sib2, iclass 19, count 0 2006.257.03:50:00.27#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:50:00.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:50:00.27#ibcon#[25=USB\r\n] 2006.257.03:50:00.27#ibcon#*before write, iclass 19, count 0 2006.257.03:50:00.27#ibcon#enter sib2, iclass 19, count 0 2006.257.03:50:00.27#ibcon#flushed, iclass 19, count 0 2006.257.03:50:00.27#ibcon#about to write, iclass 19, count 0 2006.257.03:50:00.27#ibcon#wrote, iclass 19, count 0 2006.257.03:50:00.27#ibcon#about to read 3, iclass 19, count 0 2006.257.03:50:00.30#ibcon#read 3, iclass 19, count 0 2006.257.03:50:00.30#ibcon#about to read 4, iclass 19, count 0 2006.257.03:50:00.30#ibcon#read 4, iclass 19, count 0 2006.257.03:50:00.30#ibcon#about to read 5, iclass 19, count 0 2006.257.03:50:00.30#ibcon#read 5, iclass 19, count 0 2006.257.03:50:00.30#ibcon#about to read 6, iclass 19, count 0 2006.257.03:50:00.30#ibcon#read 6, iclass 19, count 0 2006.257.03:50:00.30#ibcon#end of sib2, iclass 19, count 0 2006.257.03:50:00.30#ibcon#*after write, iclass 19, count 0 2006.257.03:50:00.30#ibcon#*before return 0, iclass 19, count 0 2006.257.03:50:00.30#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:00.30#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:00.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:50:00.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:50:00.30$vck44/valo=7,864.99 2006.257.03:50:00.30#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.03:50:00.30#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.03:50:00.30#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:00.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:00.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:00.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:00.30#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:50:00.30#ibcon#first serial, iclass 21, count 0 2006.257.03:50:00.30#ibcon#enter sib2, iclass 21, count 0 2006.257.03:50:00.30#ibcon#flushed, iclass 21, count 0 2006.257.03:50:00.30#ibcon#about to write, iclass 21, count 0 2006.257.03:50:00.30#ibcon#wrote, iclass 21, count 0 2006.257.03:50:00.30#ibcon#about to read 3, iclass 21, count 0 2006.257.03:50:00.32#ibcon#read 3, iclass 21, count 0 2006.257.03:50:00.32#ibcon#about to read 4, iclass 21, count 0 2006.257.03:50:00.32#ibcon#read 4, iclass 21, count 0 2006.257.03:50:00.32#ibcon#about to read 5, iclass 21, count 0 2006.257.03:50:00.32#ibcon#read 5, iclass 21, count 0 2006.257.03:50:00.32#ibcon#about to read 6, iclass 21, count 0 2006.257.03:50:00.32#ibcon#read 6, iclass 21, count 0 2006.257.03:50:00.32#ibcon#end of sib2, iclass 21, count 0 2006.257.03:50:00.32#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:50:00.32#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:50:00.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:50:00.32#ibcon#*before write, iclass 21, count 0 2006.257.03:50:00.32#ibcon#enter sib2, iclass 21, count 0 2006.257.03:50:00.32#ibcon#flushed, iclass 21, count 0 2006.257.03:50:00.32#ibcon#about to write, iclass 21, count 0 2006.257.03:50:00.32#ibcon#wrote, iclass 21, count 0 2006.257.03:50:00.32#ibcon#about to read 3, iclass 21, count 0 2006.257.03:50:00.36#ibcon#read 3, iclass 21, count 0 2006.257.03:50:00.36#ibcon#about to read 4, iclass 21, count 0 2006.257.03:50:00.36#ibcon#read 4, iclass 21, count 0 2006.257.03:50:00.36#ibcon#about to read 5, iclass 21, count 0 2006.257.03:50:00.36#ibcon#read 5, iclass 21, count 0 2006.257.03:50:00.36#ibcon#about to read 6, iclass 21, count 0 2006.257.03:50:00.36#ibcon#read 6, iclass 21, count 0 2006.257.03:50:00.36#ibcon#end of sib2, iclass 21, count 0 2006.257.03:50:00.36#ibcon#*after write, iclass 21, count 0 2006.257.03:50:00.36#ibcon#*before return 0, iclass 21, count 0 2006.257.03:50:00.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:00.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:00.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:50:00.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:50:00.36$vck44/va=7,4 2006.257.03:50:00.36#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.03:50:00.36#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.03:50:00.36#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:00.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:00.42#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:00.42#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:00.42#ibcon#enter wrdev, iclass 23, count 2 2006.257.03:50:00.42#ibcon#first serial, iclass 23, count 2 2006.257.03:50:00.42#ibcon#enter sib2, iclass 23, count 2 2006.257.03:50:00.42#ibcon#flushed, iclass 23, count 2 2006.257.03:50:00.42#ibcon#about to write, iclass 23, count 2 2006.257.03:50:00.42#ibcon#wrote, iclass 23, count 2 2006.257.03:50:00.42#ibcon#about to read 3, iclass 23, count 2 2006.257.03:50:00.44#ibcon#read 3, iclass 23, count 2 2006.257.03:50:00.44#ibcon#about to read 4, iclass 23, count 2 2006.257.03:50:00.44#ibcon#read 4, iclass 23, count 2 2006.257.03:50:00.44#ibcon#about to read 5, iclass 23, count 2 2006.257.03:50:00.44#ibcon#read 5, iclass 23, count 2 2006.257.03:50:00.44#ibcon#about to read 6, iclass 23, count 2 2006.257.03:50:00.44#ibcon#read 6, iclass 23, count 2 2006.257.03:50:00.44#ibcon#end of sib2, iclass 23, count 2 2006.257.03:50:00.44#ibcon#*mode == 0, iclass 23, count 2 2006.257.03:50:00.44#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.03:50:00.44#ibcon#[25=AT07-04\r\n] 2006.257.03:50:00.44#ibcon#*before write, iclass 23, count 2 2006.257.03:50:00.44#ibcon#enter sib2, iclass 23, count 2 2006.257.03:50:00.44#ibcon#flushed, iclass 23, count 2 2006.257.03:50:00.44#ibcon#about to write, iclass 23, count 2 2006.257.03:50:00.44#ibcon#wrote, iclass 23, count 2 2006.257.03:50:00.44#ibcon#about to read 3, iclass 23, count 2 2006.257.03:50:00.47#ibcon#read 3, iclass 23, count 2 2006.257.03:50:00.47#ibcon#about to read 4, iclass 23, count 2 2006.257.03:50:00.47#ibcon#read 4, iclass 23, count 2 2006.257.03:50:00.47#ibcon#about to read 5, iclass 23, count 2 2006.257.03:50:00.47#ibcon#read 5, iclass 23, count 2 2006.257.03:50:00.47#ibcon#about to read 6, iclass 23, count 2 2006.257.03:50:00.47#ibcon#read 6, iclass 23, count 2 2006.257.03:50:00.47#ibcon#end of sib2, iclass 23, count 2 2006.257.03:50:00.47#ibcon#*after write, iclass 23, count 2 2006.257.03:50:00.47#ibcon#*before return 0, iclass 23, count 2 2006.257.03:50:00.47#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:00.47#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:00.47#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.03:50:00.47#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:00.47#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:00.59#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:00.59#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:00.59#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:50:00.59#ibcon#first serial, iclass 23, count 0 2006.257.03:50:00.59#ibcon#enter sib2, iclass 23, count 0 2006.257.03:50:00.59#ibcon#flushed, iclass 23, count 0 2006.257.03:50:00.59#ibcon#about to write, iclass 23, count 0 2006.257.03:50:00.59#ibcon#wrote, iclass 23, count 0 2006.257.03:50:00.59#ibcon#about to read 3, iclass 23, count 0 2006.257.03:50:00.61#ibcon#read 3, iclass 23, count 0 2006.257.03:50:00.61#ibcon#about to read 4, iclass 23, count 0 2006.257.03:50:00.61#ibcon#read 4, iclass 23, count 0 2006.257.03:50:00.61#ibcon#about to read 5, iclass 23, count 0 2006.257.03:50:00.61#ibcon#read 5, iclass 23, count 0 2006.257.03:50:00.61#ibcon#about to read 6, iclass 23, count 0 2006.257.03:50:00.61#ibcon#read 6, iclass 23, count 0 2006.257.03:50:00.61#ibcon#end of sib2, iclass 23, count 0 2006.257.03:50:00.61#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:50:00.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:50:00.61#ibcon#[25=USB\r\n] 2006.257.03:50:00.61#ibcon#*before write, iclass 23, count 0 2006.257.03:50:00.61#ibcon#enter sib2, iclass 23, count 0 2006.257.03:50:00.61#ibcon#flushed, iclass 23, count 0 2006.257.03:50:00.61#ibcon#about to write, iclass 23, count 0 2006.257.03:50:00.61#ibcon#wrote, iclass 23, count 0 2006.257.03:50:00.61#ibcon#about to read 3, iclass 23, count 0 2006.257.03:50:00.64#ibcon#read 3, iclass 23, count 0 2006.257.03:50:00.64#ibcon#about to read 4, iclass 23, count 0 2006.257.03:50:00.64#ibcon#read 4, iclass 23, count 0 2006.257.03:50:00.64#ibcon#about to read 5, iclass 23, count 0 2006.257.03:50:00.64#ibcon#read 5, iclass 23, count 0 2006.257.03:50:00.64#ibcon#about to read 6, iclass 23, count 0 2006.257.03:50:00.64#ibcon#read 6, iclass 23, count 0 2006.257.03:50:00.64#ibcon#end of sib2, iclass 23, count 0 2006.257.03:50:00.64#ibcon#*after write, iclass 23, count 0 2006.257.03:50:00.64#ibcon#*before return 0, iclass 23, count 0 2006.257.03:50:00.64#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:00.64#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:00.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:50:00.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:50:00.64$vck44/valo=8,884.99 2006.257.03:50:00.64#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.03:50:00.64#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.03:50:00.64#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:00.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:50:00.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:50:00.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:50:00.64#ibcon#enter wrdev, iclass 25, count 0 2006.257.03:50:00.64#ibcon#first serial, iclass 25, count 0 2006.257.03:50:00.64#ibcon#enter sib2, iclass 25, count 0 2006.257.03:50:00.64#ibcon#flushed, iclass 25, count 0 2006.257.03:50:00.64#ibcon#about to write, iclass 25, count 0 2006.257.03:50:00.64#ibcon#wrote, iclass 25, count 0 2006.257.03:50:00.64#ibcon#about to read 3, iclass 25, count 0 2006.257.03:50:00.66#ibcon#read 3, iclass 25, count 0 2006.257.03:50:00.66#ibcon#about to read 4, iclass 25, count 0 2006.257.03:50:00.66#ibcon#read 4, iclass 25, count 0 2006.257.03:50:00.66#ibcon#about to read 5, iclass 25, count 0 2006.257.03:50:00.66#ibcon#read 5, iclass 25, count 0 2006.257.03:50:00.66#ibcon#about to read 6, iclass 25, count 0 2006.257.03:50:00.66#ibcon#read 6, iclass 25, count 0 2006.257.03:50:00.66#ibcon#end of sib2, iclass 25, count 0 2006.257.03:50:00.66#ibcon#*mode == 0, iclass 25, count 0 2006.257.03:50:00.66#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.03:50:00.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:50:00.66#ibcon#*before write, iclass 25, count 0 2006.257.03:50:00.66#ibcon#enter sib2, iclass 25, count 0 2006.257.03:50:00.66#ibcon#flushed, iclass 25, count 0 2006.257.03:50:00.66#ibcon#about to write, iclass 25, count 0 2006.257.03:50:00.66#ibcon#wrote, iclass 25, count 0 2006.257.03:50:00.66#ibcon#about to read 3, iclass 25, count 0 2006.257.03:50:00.70#ibcon#read 3, iclass 25, count 0 2006.257.03:50:00.70#ibcon#about to read 4, iclass 25, count 0 2006.257.03:50:00.70#ibcon#read 4, iclass 25, count 0 2006.257.03:50:00.70#ibcon#about to read 5, iclass 25, count 0 2006.257.03:50:00.70#ibcon#read 5, iclass 25, count 0 2006.257.03:50:00.70#ibcon#about to read 6, iclass 25, count 0 2006.257.03:50:00.70#ibcon#read 6, iclass 25, count 0 2006.257.03:50:00.70#ibcon#end of sib2, iclass 25, count 0 2006.257.03:50:00.70#ibcon#*after write, iclass 25, count 0 2006.257.03:50:00.70#ibcon#*before return 0, iclass 25, count 0 2006.257.03:50:00.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:50:00.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.03:50:00.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.03:50:00.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.03:50:00.70$vck44/va=8,4 2006.257.03:50:00.70#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.03:50:00.70#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.03:50:00.70#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:00.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:50:00.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:50:00.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:50:00.76#ibcon#enter wrdev, iclass 27, count 2 2006.257.03:50:00.76#ibcon#first serial, iclass 27, count 2 2006.257.03:50:00.76#ibcon#enter sib2, iclass 27, count 2 2006.257.03:50:00.76#ibcon#flushed, iclass 27, count 2 2006.257.03:50:00.76#ibcon#about to write, iclass 27, count 2 2006.257.03:50:00.76#ibcon#wrote, iclass 27, count 2 2006.257.03:50:00.76#ibcon#about to read 3, iclass 27, count 2 2006.257.03:50:00.78#ibcon#read 3, iclass 27, count 2 2006.257.03:50:00.78#ibcon#about to read 4, iclass 27, count 2 2006.257.03:50:00.78#ibcon#read 4, iclass 27, count 2 2006.257.03:50:00.78#ibcon#about to read 5, iclass 27, count 2 2006.257.03:50:00.78#ibcon#read 5, iclass 27, count 2 2006.257.03:50:00.78#ibcon#about to read 6, iclass 27, count 2 2006.257.03:50:00.78#ibcon#read 6, iclass 27, count 2 2006.257.03:50:00.78#ibcon#end of sib2, iclass 27, count 2 2006.257.03:50:00.78#ibcon#*mode == 0, iclass 27, count 2 2006.257.03:50:00.78#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.03:50:00.78#ibcon#[25=AT08-04\r\n] 2006.257.03:50:00.78#ibcon#*before write, iclass 27, count 2 2006.257.03:50:00.78#ibcon#enter sib2, iclass 27, count 2 2006.257.03:50:00.78#ibcon#flushed, iclass 27, count 2 2006.257.03:50:00.78#ibcon#about to write, iclass 27, count 2 2006.257.03:50:00.78#ibcon#wrote, iclass 27, count 2 2006.257.03:50:00.78#ibcon#about to read 3, iclass 27, count 2 2006.257.03:50:00.81#ibcon#read 3, iclass 27, count 2 2006.257.03:50:00.81#ibcon#about to read 4, iclass 27, count 2 2006.257.03:50:00.81#ibcon#read 4, iclass 27, count 2 2006.257.03:50:00.81#ibcon#about to read 5, iclass 27, count 2 2006.257.03:50:00.81#ibcon#read 5, iclass 27, count 2 2006.257.03:50:00.81#ibcon#about to read 6, iclass 27, count 2 2006.257.03:50:00.81#ibcon#read 6, iclass 27, count 2 2006.257.03:50:00.81#ibcon#end of sib2, iclass 27, count 2 2006.257.03:50:00.81#ibcon#*after write, iclass 27, count 2 2006.257.03:50:00.81#ibcon#*before return 0, iclass 27, count 2 2006.257.03:50:00.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:50:00.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.03:50:00.81#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.03:50:00.81#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:00.81#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:50:00.93#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:50:00.93#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:50:00.93#ibcon#enter wrdev, iclass 27, count 0 2006.257.03:50:00.93#ibcon#first serial, iclass 27, count 0 2006.257.03:50:00.93#ibcon#enter sib2, iclass 27, count 0 2006.257.03:50:00.93#ibcon#flushed, iclass 27, count 0 2006.257.03:50:00.93#ibcon#about to write, iclass 27, count 0 2006.257.03:50:00.93#ibcon#wrote, iclass 27, count 0 2006.257.03:50:00.93#ibcon#about to read 3, iclass 27, count 0 2006.257.03:50:00.95#ibcon#read 3, iclass 27, count 0 2006.257.03:50:00.95#ibcon#about to read 4, iclass 27, count 0 2006.257.03:50:00.95#ibcon#read 4, iclass 27, count 0 2006.257.03:50:00.95#ibcon#about to read 5, iclass 27, count 0 2006.257.03:50:00.95#ibcon#read 5, iclass 27, count 0 2006.257.03:50:00.95#ibcon#about to read 6, iclass 27, count 0 2006.257.03:50:00.95#ibcon#read 6, iclass 27, count 0 2006.257.03:50:00.95#ibcon#end of sib2, iclass 27, count 0 2006.257.03:50:00.95#ibcon#*mode == 0, iclass 27, count 0 2006.257.03:50:00.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.03:50:00.95#ibcon#[25=USB\r\n] 2006.257.03:50:00.95#ibcon#*before write, iclass 27, count 0 2006.257.03:50:00.95#ibcon#enter sib2, iclass 27, count 0 2006.257.03:50:00.95#ibcon#flushed, iclass 27, count 0 2006.257.03:50:00.95#ibcon#about to write, iclass 27, count 0 2006.257.03:50:00.95#ibcon#wrote, iclass 27, count 0 2006.257.03:50:00.95#ibcon#about to read 3, iclass 27, count 0 2006.257.03:50:00.98#ibcon#read 3, iclass 27, count 0 2006.257.03:50:00.98#ibcon#about to read 4, iclass 27, count 0 2006.257.03:50:00.98#ibcon#read 4, iclass 27, count 0 2006.257.03:50:00.98#ibcon#about to read 5, iclass 27, count 0 2006.257.03:50:00.98#ibcon#read 5, iclass 27, count 0 2006.257.03:50:00.98#ibcon#about to read 6, iclass 27, count 0 2006.257.03:50:00.98#ibcon#read 6, iclass 27, count 0 2006.257.03:50:00.98#ibcon#end of sib2, iclass 27, count 0 2006.257.03:50:00.98#ibcon#*after write, iclass 27, count 0 2006.257.03:50:00.98#ibcon#*before return 0, iclass 27, count 0 2006.257.03:50:00.98#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:50:00.98#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.03:50:00.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.03:50:00.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.03:50:00.98$vck44/vblo=1,629.99 2006.257.03:50:00.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.03:50:00.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.03:50:00.98#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:00.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:00.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:00.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:00.98#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:50:00.98#ibcon#first serial, iclass 29, count 0 2006.257.03:50:00.98#ibcon#enter sib2, iclass 29, count 0 2006.257.03:50:00.98#ibcon#flushed, iclass 29, count 0 2006.257.03:50:00.98#ibcon#about to write, iclass 29, count 0 2006.257.03:50:00.98#ibcon#wrote, iclass 29, count 0 2006.257.03:50:00.98#ibcon#about to read 3, iclass 29, count 0 2006.257.03:50:01.00#ibcon#read 3, iclass 29, count 0 2006.257.03:50:01.00#ibcon#about to read 4, iclass 29, count 0 2006.257.03:50:01.00#ibcon#read 4, iclass 29, count 0 2006.257.03:50:01.00#ibcon#about to read 5, iclass 29, count 0 2006.257.03:50:01.00#ibcon#read 5, iclass 29, count 0 2006.257.03:50:01.00#ibcon#about to read 6, iclass 29, count 0 2006.257.03:50:01.00#ibcon#read 6, iclass 29, count 0 2006.257.03:50:01.00#ibcon#end of sib2, iclass 29, count 0 2006.257.03:50:01.00#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:50:01.00#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:50:01.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:50:01.00#ibcon#*before write, iclass 29, count 0 2006.257.03:50:01.00#ibcon#enter sib2, iclass 29, count 0 2006.257.03:50:01.00#ibcon#flushed, iclass 29, count 0 2006.257.03:50:01.00#ibcon#about to write, iclass 29, count 0 2006.257.03:50:01.00#ibcon#wrote, iclass 29, count 0 2006.257.03:50:01.00#ibcon#about to read 3, iclass 29, count 0 2006.257.03:50:01.04#ibcon#read 3, iclass 29, count 0 2006.257.03:50:01.04#ibcon#about to read 4, iclass 29, count 0 2006.257.03:50:01.04#ibcon#read 4, iclass 29, count 0 2006.257.03:50:01.04#ibcon#about to read 5, iclass 29, count 0 2006.257.03:50:01.04#ibcon#read 5, iclass 29, count 0 2006.257.03:50:01.04#ibcon#about to read 6, iclass 29, count 0 2006.257.03:50:01.04#ibcon#read 6, iclass 29, count 0 2006.257.03:50:01.04#ibcon#end of sib2, iclass 29, count 0 2006.257.03:50:01.04#ibcon#*after write, iclass 29, count 0 2006.257.03:50:01.04#ibcon#*before return 0, iclass 29, count 0 2006.257.03:50:01.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:01.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:01.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:50:01.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:50:01.04$vck44/vb=1,4 2006.257.03:50:01.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.03:50:01.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.03:50:01.04#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:01.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:50:01.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:50:01.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:50:01.04#ibcon#enter wrdev, iclass 31, count 2 2006.257.03:50:01.04#ibcon#first serial, iclass 31, count 2 2006.257.03:50:01.04#ibcon#enter sib2, iclass 31, count 2 2006.257.03:50:01.04#ibcon#flushed, iclass 31, count 2 2006.257.03:50:01.04#ibcon#about to write, iclass 31, count 2 2006.257.03:50:01.04#ibcon#wrote, iclass 31, count 2 2006.257.03:50:01.04#ibcon#about to read 3, iclass 31, count 2 2006.257.03:50:01.06#ibcon#read 3, iclass 31, count 2 2006.257.03:50:01.06#ibcon#about to read 4, iclass 31, count 2 2006.257.03:50:01.06#ibcon#read 4, iclass 31, count 2 2006.257.03:50:01.06#ibcon#about to read 5, iclass 31, count 2 2006.257.03:50:01.06#ibcon#read 5, iclass 31, count 2 2006.257.03:50:01.06#ibcon#about to read 6, iclass 31, count 2 2006.257.03:50:01.06#ibcon#read 6, iclass 31, count 2 2006.257.03:50:01.06#ibcon#end of sib2, iclass 31, count 2 2006.257.03:50:01.06#ibcon#*mode == 0, iclass 31, count 2 2006.257.03:50:01.06#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.03:50:01.06#ibcon#[27=AT01-04\r\n] 2006.257.03:50:01.06#ibcon#*before write, iclass 31, count 2 2006.257.03:50:01.06#ibcon#enter sib2, iclass 31, count 2 2006.257.03:50:01.06#ibcon#flushed, iclass 31, count 2 2006.257.03:50:01.06#ibcon#about to write, iclass 31, count 2 2006.257.03:50:01.06#ibcon#wrote, iclass 31, count 2 2006.257.03:50:01.06#ibcon#about to read 3, iclass 31, count 2 2006.257.03:50:01.09#ibcon#read 3, iclass 31, count 2 2006.257.03:50:01.09#ibcon#about to read 4, iclass 31, count 2 2006.257.03:50:01.09#ibcon#read 4, iclass 31, count 2 2006.257.03:50:01.09#ibcon#about to read 5, iclass 31, count 2 2006.257.03:50:01.09#ibcon#read 5, iclass 31, count 2 2006.257.03:50:01.09#ibcon#about to read 6, iclass 31, count 2 2006.257.03:50:01.09#ibcon#read 6, iclass 31, count 2 2006.257.03:50:01.09#ibcon#end of sib2, iclass 31, count 2 2006.257.03:50:01.09#ibcon#*after write, iclass 31, count 2 2006.257.03:50:01.09#ibcon#*before return 0, iclass 31, count 2 2006.257.03:50:01.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:50:01.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.03:50:01.09#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.03:50:01.09#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:01.09#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:50:01.21#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:50:01.21#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:50:01.21#ibcon#enter wrdev, iclass 31, count 0 2006.257.03:50:01.21#ibcon#first serial, iclass 31, count 0 2006.257.03:50:01.21#ibcon#enter sib2, iclass 31, count 0 2006.257.03:50:01.21#ibcon#flushed, iclass 31, count 0 2006.257.03:50:01.21#ibcon#about to write, iclass 31, count 0 2006.257.03:50:01.21#ibcon#wrote, iclass 31, count 0 2006.257.03:50:01.21#ibcon#about to read 3, iclass 31, count 0 2006.257.03:50:01.23#ibcon#read 3, iclass 31, count 0 2006.257.03:50:01.23#ibcon#about to read 4, iclass 31, count 0 2006.257.03:50:01.23#ibcon#read 4, iclass 31, count 0 2006.257.03:50:01.23#ibcon#about to read 5, iclass 31, count 0 2006.257.03:50:01.23#ibcon#read 5, iclass 31, count 0 2006.257.03:50:01.23#ibcon#about to read 6, iclass 31, count 0 2006.257.03:50:01.23#ibcon#read 6, iclass 31, count 0 2006.257.03:50:01.23#ibcon#end of sib2, iclass 31, count 0 2006.257.03:50:01.23#ibcon#*mode == 0, iclass 31, count 0 2006.257.03:50:01.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.03:50:01.23#ibcon#[27=USB\r\n] 2006.257.03:50:01.23#ibcon#*before write, iclass 31, count 0 2006.257.03:50:01.23#ibcon#enter sib2, iclass 31, count 0 2006.257.03:50:01.23#ibcon#flushed, iclass 31, count 0 2006.257.03:50:01.23#ibcon#about to write, iclass 31, count 0 2006.257.03:50:01.23#ibcon#wrote, iclass 31, count 0 2006.257.03:50:01.23#ibcon#about to read 3, iclass 31, count 0 2006.257.03:50:01.26#ibcon#read 3, iclass 31, count 0 2006.257.03:50:01.26#ibcon#about to read 4, iclass 31, count 0 2006.257.03:50:01.26#ibcon#read 4, iclass 31, count 0 2006.257.03:50:01.26#ibcon#about to read 5, iclass 31, count 0 2006.257.03:50:01.26#ibcon#read 5, iclass 31, count 0 2006.257.03:50:01.26#ibcon#about to read 6, iclass 31, count 0 2006.257.03:50:01.26#ibcon#read 6, iclass 31, count 0 2006.257.03:50:01.26#ibcon#end of sib2, iclass 31, count 0 2006.257.03:50:01.26#ibcon#*after write, iclass 31, count 0 2006.257.03:50:01.26#ibcon#*before return 0, iclass 31, count 0 2006.257.03:50:01.26#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:50:01.26#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.03:50:01.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.03:50:01.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.03:50:01.26$vck44/vblo=2,634.99 2006.257.03:50:01.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.03:50:01.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.03:50:01.26#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:01.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:50:01.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:50:01.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:50:01.26#ibcon#enter wrdev, iclass 33, count 0 2006.257.03:50:01.26#ibcon#first serial, iclass 33, count 0 2006.257.03:50:01.26#ibcon#enter sib2, iclass 33, count 0 2006.257.03:50:01.26#ibcon#flushed, iclass 33, count 0 2006.257.03:50:01.26#ibcon#about to write, iclass 33, count 0 2006.257.03:50:01.26#ibcon#wrote, iclass 33, count 0 2006.257.03:50:01.26#ibcon#about to read 3, iclass 33, count 0 2006.257.03:50:01.28#ibcon#read 3, iclass 33, count 0 2006.257.03:50:01.28#ibcon#about to read 4, iclass 33, count 0 2006.257.03:50:01.28#ibcon#read 4, iclass 33, count 0 2006.257.03:50:01.28#ibcon#about to read 5, iclass 33, count 0 2006.257.03:50:01.28#ibcon#read 5, iclass 33, count 0 2006.257.03:50:01.28#ibcon#about to read 6, iclass 33, count 0 2006.257.03:50:01.28#ibcon#read 6, iclass 33, count 0 2006.257.03:50:01.28#ibcon#end of sib2, iclass 33, count 0 2006.257.03:50:01.28#ibcon#*mode == 0, iclass 33, count 0 2006.257.03:50:01.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.03:50:01.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:50:01.28#ibcon#*before write, iclass 33, count 0 2006.257.03:50:01.28#ibcon#enter sib2, iclass 33, count 0 2006.257.03:50:01.28#ibcon#flushed, iclass 33, count 0 2006.257.03:50:01.28#ibcon#about to write, iclass 33, count 0 2006.257.03:50:01.28#ibcon#wrote, iclass 33, count 0 2006.257.03:50:01.28#ibcon#about to read 3, iclass 33, count 0 2006.257.03:50:01.32#ibcon#read 3, iclass 33, count 0 2006.257.03:50:01.32#ibcon#about to read 4, iclass 33, count 0 2006.257.03:50:01.32#ibcon#read 4, iclass 33, count 0 2006.257.03:50:01.32#ibcon#about to read 5, iclass 33, count 0 2006.257.03:50:01.32#ibcon#read 5, iclass 33, count 0 2006.257.03:50:01.32#ibcon#about to read 6, iclass 33, count 0 2006.257.03:50:01.32#ibcon#read 6, iclass 33, count 0 2006.257.03:50:01.32#ibcon#end of sib2, iclass 33, count 0 2006.257.03:50:01.32#ibcon#*after write, iclass 33, count 0 2006.257.03:50:01.32#ibcon#*before return 0, iclass 33, count 0 2006.257.03:50:01.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:50:01.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.03:50:01.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.03:50:01.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.03:50:01.32$vck44/vb=2,5 2006.257.03:50:01.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.03:50:01.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.03:50:01.32#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:01.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:50:01.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:50:01.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:50:01.38#ibcon#enter wrdev, iclass 35, count 2 2006.257.03:50:01.38#ibcon#first serial, iclass 35, count 2 2006.257.03:50:01.38#ibcon#enter sib2, iclass 35, count 2 2006.257.03:50:01.38#ibcon#flushed, iclass 35, count 2 2006.257.03:50:01.38#ibcon#about to write, iclass 35, count 2 2006.257.03:50:01.38#ibcon#wrote, iclass 35, count 2 2006.257.03:50:01.38#ibcon#about to read 3, iclass 35, count 2 2006.257.03:50:01.40#ibcon#read 3, iclass 35, count 2 2006.257.03:50:01.40#ibcon#about to read 4, iclass 35, count 2 2006.257.03:50:01.40#ibcon#read 4, iclass 35, count 2 2006.257.03:50:01.40#ibcon#about to read 5, iclass 35, count 2 2006.257.03:50:01.40#ibcon#read 5, iclass 35, count 2 2006.257.03:50:01.40#ibcon#about to read 6, iclass 35, count 2 2006.257.03:50:01.40#ibcon#read 6, iclass 35, count 2 2006.257.03:50:01.40#ibcon#end of sib2, iclass 35, count 2 2006.257.03:50:01.40#ibcon#*mode == 0, iclass 35, count 2 2006.257.03:50:01.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.03:50:01.40#ibcon#[27=AT02-05\r\n] 2006.257.03:50:01.40#ibcon#*before write, iclass 35, count 2 2006.257.03:50:01.40#ibcon#enter sib2, iclass 35, count 2 2006.257.03:50:01.40#ibcon#flushed, iclass 35, count 2 2006.257.03:50:01.40#ibcon#about to write, iclass 35, count 2 2006.257.03:50:01.40#ibcon#wrote, iclass 35, count 2 2006.257.03:50:01.40#ibcon#about to read 3, iclass 35, count 2 2006.257.03:50:01.43#ibcon#read 3, iclass 35, count 2 2006.257.03:50:01.43#ibcon#about to read 4, iclass 35, count 2 2006.257.03:50:01.43#ibcon#read 4, iclass 35, count 2 2006.257.03:50:01.43#ibcon#about to read 5, iclass 35, count 2 2006.257.03:50:01.43#ibcon#read 5, iclass 35, count 2 2006.257.03:50:01.43#ibcon#about to read 6, iclass 35, count 2 2006.257.03:50:01.43#ibcon#read 6, iclass 35, count 2 2006.257.03:50:01.43#ibcon#end of sib2, iclass 35, count 2 2006.257.03:50:01.43#ibcon#*after write, iclass 35, count 2 2006.257.03:50:01.43#ibcon#*before return 0, iclass 35, count 2 2006.257.03:50:01.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:50:01.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.03:50:01.43#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.03:50:01.43#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:01.43#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:50:01.55#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:50:01.55#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:50:01.55#ibcon#enter wrdev, iclass 35, count 0 2006.257.03:50:01.55#ibcon#first serial, iclass 35, count 0 2006.257.03:50:01.55#ibcon#enter sib2, iclass 35, count 0 2006.257.03:50:01.55#ibcon#flushed, iclass 35, count 0 2006.257.03:50:01.55#ibcon#about to write, iclass 35, count 0 2006.257.03:50:01.55#ibcon#wrote, iclass 35, count 0 2006.257.03:50:01.55#ibcon#about to read 3, iclass 35, count 0 2006.257.03:50:01.57#ibcon#read 3, iclass 35, count 0 2006.257.03:50:01.57#ibcon#about to read 4, iclass 35, count 0 2006.257.03:50:01.57#ibcon#read 4, iclass 35, count 0 2006.257.03:50:01.57#ibcon#about to read 5, iclass 35, count 0 2006.257.03:50:01.57#ibcon#read 5, iclass 35, count 0 2006.257.03:50:01.57#ibcon#about to read 6, iclass 35, count 0 2006.257.03:50:01.57#ibcon#read 6, iclass 35, count 0 2006.257.03:50:01.57#ibcon#end of sib2, iclass 35, count 0 2006.257.03:50:01.57#ibcon#*mode == 0, iclass 35, count 0 2006.257.03:50:01.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.03:50:01.57#ibcon#[27=USB\r\n] 2006.257.03:50:01.57#ibcon#*before write, iclass 35, count 0 2006.257.03:50:01.57#ibcon#enter sib2, iclass 35, count 0 2006.257.03:50:01.57#ibcon#flushed, iclass 35, count 0 2006.257.03:50:01.57#ibcon#about to write, iclass 35, count 0 2006.257.03:50:01.57#ibcon#wrote, iclass 35, count 0 2006.257.03:50:01.57#ibcon#about to read 3, iclass 35, count 0 2006.257.03:50:01.60#ibcon#read 3, iclass 35, count 0 2006.257.03:50:01.60#ibcon#about to read 4, iclass 35, count 0 2006.257.03:50:01.60#ibcon#read 4, iclass 35, count 0 2006.257.03:50:01.60#ibcon#about to read 5, iclass 35, count 0 2006.257.03:50:01.60#ibcon#read 5, iclass 35, count 0 2006.257.03:50:01.60#ibcon#about to read 6, iclass 35, count 0 2006.257.03:50:01.60#ibcon#read 6, iclass 35, count 0 2006.257.03:50:01.60#ibcon#end of sib2, iclass 35, count 0 2006.257.03:50:01.60#ibcon#*after write, iclass 35, count 0 2006.257.03:50:01.60#ibcon#*before return 0, iclass 35, count 0 2006.257.03:50:01.60#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:50:01.60#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.03:50:01.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.03:50:01.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.03:50:01.60$vck44/vblo=3,649.99 2006.257.03:50:01.60#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.03:50:01.60#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.03:50:01.60#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:01.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:50:01.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:50:01.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:50:01.60#ibcon#enter wrdev, iclass 37, count 0 2006.257.03:50:01.60#ibcon#first serial, iclass 37, count 0 2006.257.03:50:01.60#ibcon#enter sib2, iclass 37, count 0 2006.257.03:50:01.60#ibcon#flushed, iclass 37, count 0 2006.257.03:50:01.60#ibcon#about to write, iclass 37, count 0 2006.257.03:50:01.60#ibcon#wrote, iclass 37, count 0 2006.257.03:50:01.60#ibcon#about to read 3, iclass 37, count 0 2006.257.03:50:01.62#ibcon#read 3, iclass 37, count 0 2006.257.03:50:01.62#ibcon#about to read 4, iclass 37, count 0 2006.257.03:50:01.62#ibcon#read 4, iclass 37, count 0 2006.257.03:50:01.62#ibcon#about to read 5, iclass 37, count 0 2006.257.03:50:01.62#ibcon#read 5, iclass 37, count 0 2006.257.03:50:01.62#ibcon#about to read 6, iclass 37, count 0 2006.257.03:50:01.62#ibcon#read 6, iclass 37, count 0 2006.257.03:50:01.62#ibcon#end of sib2, iclass 37, count 0 2006.257.03:50:01.62#ibcon#*mode == 0, iclass 37, count 0 2006.257.03:50:01.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.03:50:01.62#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:50:01.62#ibcon#*before write, iclass 37, count 0 2006.257.03:50:01.62#ibcon#enter sib2, iclass 37, count 0 2006.257.03:50:01.62#ibcon#flushed, iclass 37, count 0 2006.257.03:50:01.62#ibcon#about to write, iclass 37, count 0 2006.257.03:50:01.62#ibcon#wrote, iclass 37, count 0 2006.257.03:50:01.62#ibcon#about to read 3, iclass 37, count 0 2006.257.03:50:01.66#ibcon#read 3, iclass 37, count 0 2006.257.03:50:01.66#ibcon#about to read 4, iclass 37, count 0 2006.257.03:50:01.66#ibcon#read 4, iclass 37, count 0 2006.257.03:50:01.66#ibcon#about to read 5, iclass 37, count 0 2006.257.03:50:01.66#ibcon#read 5, iclass 37, count 0 2006.257.03:50:01.66#ibcon#about to read 6, iclass 37, count 0 2006.257.03:50:01.66#ibcon#read 6, iclass 37, count 0 2006.257.03:50:01.66#ibcon#end of sib2, iclass 37, count 0 2006.257.03:50:01.66#ibcon#*after write, iclass 37, count 0 2006.257.03:50:01.66#ibcon#*before return 0, iclass 37, count 0 2006.257.03:50:01.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:50:01.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.03:50:01.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.03:50:01.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.03:50:01.66$vck44/vb=3,4 2006.257.03:50:01.66#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.03:50:01.66#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.03:50:01.66#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:01.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:50:01.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:50:01.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:50:01.72#ibcon#enter wrdev, iclass 39, count 2 2006.257.03:50:01.72#ibcon#first serial, iclass 39, count 2 2006.257.03:50:01.72#ibcon#enter sib2, iclass 39, count 2 2006.257.03:50:01.72#ibcon#flushed, iclass 39, count 2 2006.257.03:50:01.72#ibcon#about to write, iclass 39, count 2 2006.257.03:50:01.72#ibcon#wrote, iclass 39, count 2 2006.257.03:50:01.72#ibcon#about to read 3, iclass 39, count 2 2006.257.03:50:01.74#ibcon#read 3, iclass 39, count 2 2006.257.03:50:01.74#ibcon#about to read 4, iclass 39, count 2 2006.257.03:50:01.74#ibcon#read 4, iclass 39, count 2 2006.257.03:50:01.74#ibcon#about to read 5, iclass 39, count 2 2006.257.03:50:01.74#ibcon#read 5, iclass 39, count 2 2006.257.03:50:01.74#ibcon#about to read 6, iclass 39, count 2 2006.257.03:50:01.74#ibcon#read 6, iclass 39, count 2 2006.257.03:50:01.74#ibcon#end of sib2, iclass 39, count 2 2006.257.03:50:01.74#ibcon#*mode == 0, iclass 39, count 2 2006.257.03:50:01.74#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.03:50:01.74#ibcon#[27=AT03-04\r\n] 2006.257.03:50:01.74#ibcon#*before write, iclass 39, count 2 2006.257.03:50:01.74#ibcon#enter sib2, iclass 39, count 2 2006.257.03:50:01.74#ibcon#flushed, iclass 39, count 2 2006.257.03:50:01.74#ibcon#about to write, iclass 39, count 2 2006.257.03:50:01.74#ibcon#wrote, iclass 39, count 2 2006.257.03:50:01.74#ibcon#about to read 3, iclass 39, count 2 2006.257.03:50:01.77#ibcon#read 3, iclass 39, count 2 2006.257.03:50:01.77#ibcon#about to read 4, iclass 39, count 2 2006.257.03:50:01.77#ibcon#read 4, iclass 39, count 2 2006.257.03:50:01.77#ibcon#about to read 5, iclass 39, count 2 2006.257.03:50:01.77#ibcon#read 5, iclass 39, count 2 2006.257.03:50:01.77#ibcon#about to read 6, iclass 39, count 2 2006.257.03:50:01.77#ibcon#read 6, iclass 39, count 2 2006.257.03:50:01.77#ibcon#end of sib2, iclass 39, count 2 2006.257.03:50:01.77#ibcon#*after write, iclass 39, count 2 2006.257.03:50:01.77#ibcon#*before return 0, iclass 39, count 2 2006.257.03:50:01.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:50:01.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.03:50:01.77#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.03:50:01.77#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:01.77#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:50:01.89#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:50:01.89#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:50:01.89#ibcon#enter wrdev, iclass 39, count 0 2006.257.03:50:01.89#ibcon#first serial, iclass 39, count 0 2006.257.03:50:01.89#ibcon#enter sib2, iclass 39, count 0 2006.257.03:50:01.89#ibcon#flushed, iclass 39, count 0 2006.257.03:50:01.89#ibcon#about to write, iclass 39, count 0 2006.257.03:50:01.89#ibcon#wrote, iclass 39, count 0 2006.257.03:50:01.89#ibcon#about to read 3, iclass 39, count 0 2006.257.03:50:01.91#ibcon#read 3, iclass 39, count 0 2006.257.03:50:01.91#ibcon#about to read 4, iclass 39, count 0 2006.257.03:50:01.91#ibcon#read 4, iclass 39, count 0 2006.257.03:50:01.91#ibcon#about to read 5, iclass 39, count 0 2006.257.03:50:01.91#ibcon#read 5, iclass 39, count 0 2006.257.03:50:01.91#ibcon#about to read 6, iclass 39, count 0 2006.257.03:50:01.91#ibcon#read 6, iclass 39, count 0 2006.257.03:50:01.91#ibcon#end of sib2, iclass 39, count 0 2006.257.03:50:01.91#ibcon#*mode == 0, iclass 39, count 0 2006.257.03:50:01.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.03:50:01.91#ibcon#[27=USB\r\n] 2006.257.03:50:01.91#ibcon#*before write, iclass 39, count 0 2006.257.03:50:01.91#ibcon#enter sib2, iclass 39, count 0 2006.257.03:50:01.91#ibcon#flushed, iclass 39, count 0 2006.257.03:50:01.91#ibcon#about to write, iclass 39, count 0 2006.257.03:50:01.91#ibcon#wrote, iclass 39, count 0 2006.257.03:50:01.91#ibcon#about to read 3, iclass 39, count 0 2006.257.03:50:01.94#ibcon#read 3, iclass 39, count 0 2006.257.03:50:01.94#ibcon#about to read 4, iclass 39, count 0 2006.257.03:50:01.94#ibcon#read 4, iclass 39, count 0 2006.257.03:50:01.94#ibcon#about to read 5, iclass 39, count 0 2006.257.03:50:01.94#ibcon#read 5, iclass 39, count 0 2006.257.03:50:01.94#ibcon#about to read 6, iclass 39, count 0 2006.257.03:50:01.94#ibcon#read 6, iclass 39, count 0 2006.257.03:50:01.94#ibcon#end of sib2, iclass 39, count 0 2006.257.03:50:01.94#ibcon#*after write, iclass 39, count 0 2006.257.03:50:01.94#ibcon#*before return 0, iclass 39, count 0 2006.257.03:50:01.94#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:50:01.94#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.03:50:01.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.03:50:01.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.03:50:01.94$vck44/vblo=4,679.99 2006.257.03:50:01.94#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.03:50:01.94#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.03:50:01.94#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:01.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:50:01.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:50:01.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:50:01.94#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:50:01.94#ibcon#first serial, iclass 3, count 0 2006.257.03:50:01.94#ibcon#enter sib2, iclass 3, count 0 2006.257.03:50:01.94#ibcon#flushed, iclass 3, count 0 2006.257.03:50:01.94#ibcon#about to write, iclass 3, count 0 2006.257.03:50:01.94#ibcon#wrote, iclass 3, count 0 2006.257.03:50:01.94#ibcon#about to read 3, iclass 3, count 0 2006.257.03:50:01.96#ibcon#read 3, iclass 3, count 0 2006.257.03:50:01.96#ibcon#about to read 4, iclass 3, count 0 2006.257.03:50:01.96#ibcon#read 4, iclass 3, count 0 2006.257.03:50:01.96#ibcon#about to read 5, iclass 3, count 0 2006.257.03:50:01.96#ibcon#read 5, iclass 3, count 0 2006.257.03:50:01.96#ibcon#about to read 6, iclass 3, count 0 2006.257.03:50:01.96#ibcon#read 6, iclass 3, count 0 2006.257.03:50:01.96#ibcon#end of sib2, iclass 3, count 0 2006.257.03:50:01.96#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:50:01.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:50:01.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:50:01.96#ibcon#*before write, iclass 3, count 0 2006.257.03:50:01.96#ibcon#enter sib2, iclass 3, count 0 2006.257.03:50:01.96#ibcon#flushed, iclass 3, count 0 2006.257.03:50:01.96#ibcon#about to write, iclass 3, count 0 2006.257.03:50:01.96#ibcon#wrote, iclass 3, count 0 2006.257.03:50:01.96#ibcon#about to read 3, iclass 3, count 0 2006.257.03:50:02.00#ibcon#read 3, iclass 3, count 0 2006.257.03:50:02.00#ibcon#about to read 4, iclass 3, count 0 2006.257.03:50:02.00#ibcon#read 4, iclass 3, count 0 2006.257.03:50:02.00#ibcon#about to read 5, iclass 3, count 0 2006.257.03:50:02.00#ibcon#read 5, iclass 3, count 0 2006.257.03:50:02.00#ibcon#about to read 6, iclass 3, count 0 2006.257.03:50:02.00#ibcon#read 6, iclass 3, count 0 2006.257.03:50:02.00#ibcon#end of sib2, iclass 3, count 0 2006.257.03:50:02.00#ibcon#*after write, iclass 3, count 0 2006.257.03:50:02.00#ibcon#*before return 0, iclass 3, count 0 2006.257.03:50:02.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:50:02.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:50:02.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:50:02.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:50:02.00$vck44/vb=4,5 2006.257.03:50:02.00#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.03:50:02.00#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.03:50:02.00#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:02.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:50:02.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:50:02.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:50:02.06#ibcon#enter wrdev, iclass 5, count 2 2006.257.03:50:02.06#ibcon#first serial, iclass 5, count 2 2006.257.03:50:02.06#ibcon#enter sib2, iclass 5, count 2 2006.257.03:50:02.06#ibcon#flushed, iclass 5, count 2 2006.257.03:50:02.06#ibcon#about to write, iclass 5, count 2 2006.257.03:50:02.06#ibcon#wrote, iclass 5, count 2 2006.257.03:50:02.06#ibcon#about to read 3, iclass 5, count 2 2006.257.03:50:02.08#ibcon#read 3, iclass 5, count 2 2006.257.03:50:02.08#ibcon#about to read 4, iclass 5, count 2 2006.257.03:50:02.08#ibcon#read 4, iclass 5, count 2 2006.257.03:50:02.08#ibcon#about to read 5, iclass 5, count 2 2006.257.03:50:02.08#ibcon#read 5, iclass 5, count 2 2006.257.03:50:02.08#ibcon#about to read 6, iclass 5, count 2 2006.257.03:50:02.08#ibcon#read 6, iclass 5, count 2 2006.257.03:50:02.08#ibcon#end of sib2, iclass 5, count 2 2006.257.03:50:02.08#ibcon#*mode == 0, iclass 5, count 2 2006.257.03:50:02.08#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.03:50:02.08#ibcon#[27=AT04-05\r\n] 2006.257.03:50:02.08#ibcon#*before write, iclass 5, count 2 2006.257.03:50:02.08#ibcon#enter sib2, iclass 5, count 2 2006.257.03:50:02.08#ibcon#flushed, iclass 5, count 2 2006.257.03:50:02.08#ibcon#about to write, iclass 5, count 2 2006.257.03:50:02.08#ibcon#wrote, iclass 5, count 2 2006.257.03:50:02.08#ibcon#about to read 3, iclass 5, count 2 2006.257.03:50:02.11#ibcon#read 3, iclass 5, count 2 2006.257.03:50:02.11#ibcon#about to read 4, iclass 5, count 2 2006.257.03:50:02.11#ibcon#read 4, iclass 5, count 2 2006.257.03:50:02.11#ibcon#about to read 5, iclass 5, count 2 2006.257.03:50:02.11#ibcon#read 5, iclass 5, count 2 2006.257.03:50:02.11#ibcon#about to read 6, iclass 5, count 2 2006.257.03:50:02.11#ibcon#read 6, iclass 5, count 2 2006.257.03:50:02.11#ibcon#end of sib2, iclass 5, count 2 2006.257.03:50:02.11#ibcon#*after write, iclass 5, count 2 2006.257.03:50:02.11#ibcon#*before return 0, iclass 5, count 2 2006.257.03:50:02.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:50:02.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.03:50:02.11#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.03:50:02.11#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:02.11#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:50:02.23#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:50:02.23#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:50:02.23#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:50:02.23#ibcon#first serial, iclass 5, count 0 2006.257.03:50:02.23#ibcon#enter sib2, iclass 5, count 0 2006.257.03:50:02.23#ibcon#flushed, iclass 5, count 0 2006.257.03:50:02.23#ibcon#about to write, iclass 5, count 0 2006.257.03:50:02.23#ibcon#wrote, iclass 5, count 0 2006.257.03:50:02.23#ibcon#about to read 3, iclass 5, count 0 2006.257.03:50:02.25#ibcon#read 3, iclass 5, count 0 2006.257.03:50:02.25#ibcon#about to read 4, iclass 5, count 0 2006.257.03:50:02.25#ibcon#read 4, iclass 5, count 0 2006.257.03:50:02.25#ibcon#about to read 5, iclass 5, count 0 2006.257.03:50:02.25#ibcon#read 5, iclass 5, count 0 2006.257.03:50:02.25#ibcon#about to read 6, iclass 5, count 0 2006.257.03:50:02.25#ibcon#read 6, iclass 5, count 0 2006.257.03:50:02.25#ibcon#end of sib2, iclass 5, count 0 2006.257.03:50:02.25#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:50:02.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:50:02.25#ibcon#[27=USB\r\n] 2006.257.03:50:02.25#ibcon#*before write, iclass 5, count 0 2006.257.03:50:02.25#ibcon#enter sib2, iclass 5, count 0 2006.257.03:50:02.25#ibcon#flushed, iclass 5, count 0 2006.257.03:50:02.25#ibcon#about to write, iclass 5, count 0 2006.257.03:50:02.25#ibcon#wrote, iclass 5, count 0 2006.257.03:50:02.25#ibcon#about to read 3, iclass 5, count 0 2006.257.03:50:02.28#ibcon#read 3, iclass 5, count 0 2006.257.03:50:02.28#ibcon#about to read 4, iclass 5, count 0 2006.257.03:50:02.28#ibcon#read 4, iclass 5, count 0 2006.257.03:50:02.28#ibcon#about to read 5, iclass 5, count 0 2006.257.03:50:02.28#ibcon#read 5, iclass 5, count 0 2006.257.03:50:02.28#ibcon#about to read 6, iclass 5, count 0 2006.257.03:50:02.28#ibcon#read 6, iclass 5, count 0 2006.257.03:50:02.28#ibcon#end of sib2, iclass 5, count 0 2006.257.03:50:02.28#ibcon#*after write, iclass 5, count 0 2006.257.03:50:02.28#ibcon#*before return 0, iclass 5, count 0 2006.257.03:50:02.28#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:50:02.28#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.03:50:02.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:50:02.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:50:02.28$vck44/vblo=5,709.99 2006.257.03:50:02.28#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.03:50:02.28#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.03:50:02.28#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:02.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:50:02.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:50:02.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:50:02.28#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:50:02.28#ibcon#first serial, iclass 7, count 0 2006.257.03:50:02.28#ibcon#enter sib2, iclass 7, count 0 2006.257.03:50:02.28#ibcon#flushed, iclass 7, count 0 2006.257.03:50:02.28#ibcon#about to write, iclass 7, count 0 2006.257.03:50:02.28#ibcon#wrote, iclass 7, count 0 2006.257.03:50:02.28#ibcon#about to read 3, iclass 7, count 0 2006.257.03:50:02.30#ibcon#read 3, iclass 7, count 0 2006.257.03:50:02.30#ibcon#about to read 4, iclass 7, count 0 2006.257.03:50:02.30#ibcon#read 4, iclass 7, count 0 2006.257.03:50:02.30#ibcon#about to read 5, iclass 7, count 0 2006.257.03:50:02.30#ibcon#read 5, iclass 7, count 0 2006.257.03:50:02.30#ibcon#about to read 6, iclass 7, count 0 2006.257.03:50:02.30#ibcon#read 6, iclass 7, count 0 2006.257.03:50:02.30#ibcon#end of sib2, iclass 7, count 0 2006.257.03:50:02.30#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:50:02.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:50:02.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:50:02.30#ibcon#*before write, iclass 7, count 0 2006.257.03:50:02.30#ibcon#enter sib2, iclass 7, count 0 2006.257.03:50:02.30#ibcon#flushed, iclass 7, count 0 2006.257.03:50:02.30#ibcon#about to write, iclass 7, count 0 2006.257.03:50:02.30#ibcon#wrote, iclass 7, count 0 2006.257.03:50:02.30#ibcon#about to read 3, iclass 7, count 0 2006.257.03:50:02.34#ibcon#read 3, iclass 7, count 0 2006.257.03:50:02.34#ibcon#about to read 4, iclass 7, count 0 2006.257.03:50:02.34#ibcon#read 4, iclass 7, count 0 2006.257.03:50:02.34#ibcon#about to read 5, iclass 7, count 0 2006.257.03:50:02.34#ibcon#read 5, iclass 7, count 0 2006.257.03:50:02.34#ibcon#about to read 6, iclass 7, count 0 2006.257.03:50:02.34#ibcon#read 6, iclass 7, count 0 2006.257.03:50:02.34#ibcon#end of sib2, iclass 7, count 0 2006.257.03:50:02.34#ibcon#*after write, iclass 7, count 0 2006.257.03:50:02.34#ibcon#*before return 0, iclass 7, count 0 2006.257.03:50:02.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:50:02.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.03:50:02.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:50:02.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:50:02.34$vck44/vb=5,4 2006.257.03:50:02.34#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.03:50:02.34#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.03:50:02.34#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:02.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:50:02.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:50:02.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:50:02.40#ibcon#enter wrdev, iclass 11, count 2 2006.257.03:50:02.40#ibcon#first serial, iclass 11, count 2 2006.257.03:50:02.40#ibcon#enter sib2, iclass 11, count 2 2006.257.03:50:02.40#ibcon#flushed, iclass 11, count 2 2006.257.03:50:02.40#ibcon#about to write, iclass 11, count 2 2006.257.03:50:02.40#ibcon#wrote, iclass 11, count 2 2006.257.03:50:02.40#ibcon#about to read 3, iclass 11, count 2 2006.257.03:50:02.42#ibcon#read 3, iclass 11, count 2 2006.257.03:50:02.42#ibcon#about to read 4, iclass 11, count 2 2006.257.03:50:02.42#ibcon#read 4, iclass 11, count 2 2006.257.03:50:02.42#ibcon#about to read 5, iclass 11, count 2 2006.257.03:50:02.42#ibcon#read 5, iclass 11, count 2 2006.257.03:50:02.42#ibcon#about to read 6, iclass 11, count 2 2006.257.03:50:02.42#ibcon#read 6, iclass 11, count 2 2006.257.03:50:02.42#ibcon#end of sib2, iclass 11, count 2 2006.257.03:50:02.42#ibcon#*mode == 0, iclass 11, count 2 2006.257.03:50:02.42#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.03:50:02.42#ibcon#[27=AT05-04\r\n] 2006.257.03:50:02.42#ibcon#*before write, iclass 11, count 2 2006.257.03:50:02.42#ibcon#enter sib2, iclass 11, count 2 2006.257.03:50:02.42#ibcon#flushed, iclass 11, count 2 2006.257.03:50:02.42#ibcon#about to write, iclass 11, count 2 2006.257.03:50:02.42#ibcon#wrote, iclass 11, count 2 2006.257.03:50:02.42#ibcon#about to read 3, iclass 11, count 2 2006.257.03:50:02.45#ibcon#read 3, iclass 11, count 2 2006.257.03:50:02.45#ibcon#about to read 4, iclass 11, count 2 2006.257.03:50:02.45#ibcon#read 4, iclass 11, count 2 2006.257.03:50:02.45#ibcon#about to read 5, iclass 11, count 2 2006.257.03:50:02.45#ibcon#read 5, iclass 11, count 2 2006.257.03:50:02.45#ibcon#about to read 6, iclass 11, count 2 2006.257.03:50:02.45#ibcon#read 6, iclass 11, count 2 2006.257.03:50:02.45#ibcon#end of sib2, iclass 11, count 2 2006.257.03:50:02.45#ibcon#*after write, iclass 11, count 2 2006.257.03:50:02.45#ibcon#*before return 0, iclass 11, count 2 2006.257.03:50:02.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:50:02.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.03:50:02.45#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.03:50:02.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:02.45#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:50:02.57#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:50:02.57#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:50:02.57#ibcon#enter wrdev, iclass 11, count 0 2006.257.03:50:02.57#ibcon#first serial, iclass 11, count 0 2006.257.03:50:02.57#ibcon#enter sib2, iclass 11, count 0 2006.257.03:50:02.57#ibcon#flushed, iclass 11, count 0 2006.257.03:50:02.57#ibcon#about to write, iclass 11, count 0 2006.257.03:50:02.57#ibcon#wrote, iclass 11, count 0 2006.257.03:50:02.57#ibcon#about to read 3, iclass 11, count 0 2006.257.03:50:02.59#ibcon#read 3, iclass 11, count 0 2006.257.03:50:02.59#ibcon#about to read 4, iclass 11, count 0 2006.257.03:50:02.59#ibcon#read 4, iclass 11, count 0 2006.257.03:50:02.59#ibcon#about to read 5, iclass 11, count 0 2006.257.03:50:02.59#ibcon#read 5, iclass 11, count 0 2006.257.03:50:02.59#ibcon#about to read 6, iclass 11, count 0 2006.257.03:50:02.59#ibcon#read 6, iclass 11, count 0 2006.257.03:50:02.59#ibcon#end of sib2, iclass 11, count 0 2006.257.03:50:02.59#ibcon#*mode == 0, iclass 11, count 0 2006.257.03:50:02.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.03:50:02.59#ibcon#[27=USB\r\n] 2006.257.03:50:02.59#ibcon#*before write, iclass 11, count 0 2006.257.03:50:02.59#ibcon#enter sib2, iclass 11, count 0 2006.257.03:50:02.59#ibcon#flushed, iclass 11, count 0 2006.257.03:50:02.59#ibcon#about to write, iclass 11, count 0 2006.257.03:50:02.59#ibcon#wrote, iclass 11, count 0 2006.257.03:50:02.59#ibcon#about to read 3, iclass 11, count 0 2006.257.03:50:02.62#ibcon#read 3, iclass 11, count 0 2006.257.03:50:02.62#ibcon#about to read 4, iclass 11, count 0 2006.257.03:50:02.62#ibcon#read 4, iclass 11, count 0 2006.257.03:50:02.62#ibcon#about to read 5, iclass 11, count 0 2006.257.03:50:02.62#ibcon#read 5, iclass 11, count 0 2006.257.03:50:02.62#ibcon#about to read 6, iclass 11, count 0 2006.257.03:50:02.62#ibcon#read 6, iclass 11, count 0 2006.257.03:50:02.62#ibcon#end of sib2, iclass 11, count 0 2006.257.03:50:02.62#ibcon#*after write, iclass 11, count 0 2006.257.03:50:02.62#ibcon#*before return 0, iclass 11, count 0 2006.257.03:50:02.62#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:50:02.62#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.03:50:02.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.03:50:02.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.03:50:02.62$vck44/vblo=6,719.99 2006.257.03:50:02.62#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.03:50:02.62#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.03:50:02.62#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:02.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:50:02.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:50:02.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:50:02.62#ibcon#enter wrdev, iclass 13, count 0 2006.257.03:50:02.62#ibcon#first serial, iclass 13, count 0 2006.257.03:50:02.62#ibcon#enter sib2, iclass 13, count 0 2006.257.03:50:02.62#ibcon#flushed, iclass 13, count 0 2006.257.03:50:02.62#ibcon#about to write, iclass 13, count 0 2006.257.03:50:02.62#ibcon#wrote, iclass 13, count 0 2006.257.03:50:02.62#ibcon#about to read 3, iclass 13, count 0 2006.257.03:50:02.64#ibcon#read 3, iclass 13, count 0 2006.257.03:50:02.64#ibcon#about to read 4, iclass 13, count 0 2006.257.03:50:02.64#ibcon#read 4, iclass 13, count 0 2006.257.03:50:02.64#ibcon#about to read 5, iclass 13, count 0 2006.257.03:50:02.64#ibcon#read 5, iclass 13, count 0 2006.257.03:50:02.64#ibcon#about to read 6, iclass 13, count 0 2006.257.03:50:02.64#ibcon#read 6, iclass 13, count 0 2006.257.03:50:02.64#ibcon#end of sib2, iclass 13, count 0 2006.257.03:50:02.64#ibcon#*mode == 0, iclass 13, count 0 2006.257.03:50:02.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.03:50:02.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:50:02.64#ibcon#*before write, iclass 13, count 0 2006.257.03:50:02.64#ibcon#enter sib2, iclass 13, count 0 2006.257.03:50:02.64#ibcon#flushed, iclass 13, count 0 2006.257.03:50:02.64#ibcon#about to write, iclass 13, count 0 2006.257.03:50:02.64#ibcon#wrote, iclass 13, count 0 2006.257.03:50:02.64#ibcon#about to read 3, iclass 13, count 0 2006.257.03:50:02.68#ibcon#read 3, iclass 13, count 0 2006.257.03:50:02.68#ibcon#about to read 4, iclass 13, count 0 2006.257.03:50:02.68#ibcon#read 4, iclass 13, count 0 2006.257.03:50:02.68#ibcon#about to read 5, iclass 13, count 0 2006.257.03:50:02.68#ibcon#read 5, iclass 13, count 0 2006.257.03:50:02.68#ibcon#about to read 6, iclass 13, count 0 2006.257.03:50:02.68#ibcon#read 6, iclass 13, count 0 2006.257.03:50:02.68#ibcon#end of sib2, iclass 13, count 0 2006.257.03:50:02.68#ibcon#*after write, iclass 13, count 0 2006.257.03:50:02.68#ibcon#*before return 0, iclass 13, count 0 2006.257.03:50:02.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:50:02.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.03:50:02.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.03:50:02.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.03:50:02.68$vck44/vb=6,4 2006.257.03:50:02.68#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.03:50:02.68#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.03:50:02.68#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:02.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:50:02.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:50:02.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:50:02.74#ibcon#enter wrdev, iclass 15, count 2 2006.257.03:50:02.74#ibcon#first serial, iclass 15, count 2 2006.257.03:50:02.74#ibcon#enter sib2, iclass 15, count 2 2006.257.03:50:02.74#ibcon#flushed, iclass 15, count 2 2006.257.03:50:02.74#ibcon#about to write, iclass 15, count 2 2006.257.03:50:02.74#ibcon#wrote, iclass 15, count 2 2006.257.03:50:02.74#ibcon#about to read 3, iclass 15, count 2 2006.257.03:50:02.76#ibcon#read 3, iclass 15, count 2 2006.257.03:50:02.76#ibcon#about to read 4, iclass 15, count 2 2006.257.03:50:02.76#ibcon#read 4, iclass 15, count 2 2006.257.03:50:02.76#ibcon#about to read 5, iclass 15, count 2 2006.257.03:50:02.76#ibcon#read 5, iclass 15, count 2 2006.257.03:50:02.76#ibcon#about to read 6, iclass 15, count 2 2006.257.03:50:02.76#ibcon#read 6, iclass 15, count 2 2006.257.03:50:02.76#ibcon#end of sib2, iclass 15, count 2 2006.257.03:50:02.76#ibcon#*mode == 0, iclass 15, count 2 2006.257.03:50:02.76#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.03:50:02.76#ibcon#[27=AT06-04\r\n] 2006.257.03:50:02.76#ibcon#*before write, iclass 15, count 2 2006.257.03:50:02.76#ibcon#enter sib2, iclass 15, count 2 2006.257.03:50:02.76#ibcon#flushed, iclass 15, count 2 2006.257.03:50:02.76#ibcon#about to write, iclass 15, count 2 2006.257.03:50:02.76#ibcon#wrote, iclass 15, count 2 2006.257.03:50:02.76#ibcon#about to read 3, iclass 15, count 2 2006.257.03:50:02.79#ibcon#read 3, iclass 15, count 2 2006.257.03:50:02.79#ibcon#about to read 4, iclass 15, count 2 2006.257.03:50:02.79#ibcon#read 4, iclass 15, count 2 2006.257.03:50:02.79#ibcon#about to read 5, iclass 15, count 2 2006.257.03:50:02.79#ibcon#read 5, iclass 15, count 2 2006.257.03:50:02.79#ibcon#about to read 6, iclass 15, count 2 2006.257.03:50:02.79#ibcon#read 6, iclass 15, count 2 2006.257.03:50:02.79#ibcon#end of sib2, iclass 15, count 2 2006.257.03:50:02.79#ibcon#*after write, iclass 15, count 2 2006.257.03:50:02.79#ibcon#*before return 0, iclass 15, count 2 2006.257.03:50:02.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:50:02.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.03:50:02.79#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.03:50:02.79#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:02.79#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:50:02.91#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:50:02.91#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:50:02.91#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:50:02.91#ibcon#first serial, iclass 15, count 0 2006.257.03:50:02.91#ibcon#enter sib2, iclass 15, count 0 2006.257.03:50:02.91#ibcon#flushed, iclass 15, count 0 2006.257.03:50:02.91#ibcon#about to write, iclass 15, count 0 2006.257.03:50:02.91#ibcon#wrote, iclass 15, count 0 2006.257.03:50:02.91#ibcon#about to read 3, iclass 15, count 0 2006.257.03:50:02.93#ibcon#read 3, iclass 15, count 0 2006.257.03:50:02.93#ibcon#about to read 4, iclass 15, count 0 2006.257.03:50:02.93#ibcon#read 4, iclass 15, count 0 2006.257.03:50:02.93#ibcon#about to read 5, iclass 15, count 0 2006.257.03:50:02.93#ibcon#read 5, iclass 15, count 0 2006.257.03:50:02.93#ibcon#about to read 6, iclass 15, count 0 2006.257.03:50:02.93#ibcon#read 6, iclass 15, count 0 2006.257.03:50:02.93#ibcon#end of sib2, iclass 15, count 0 2006.257.03:50:02.93#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:50:02.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:50:02.93#ibcon#[27=USB\r\n] 2006.257.03:50:02.93#ibcon#*before write, iclass 15, count 0 2006.257.03:50:02.93#ibcon#enter sib2, iclass 15, count 0 2006.257.03:50:02.93#ibcon#flushed, iclass 15, count 0 2006.257.03:50:02.93#ibcon#about to write, iclass 15, count 0 2006.257.03:50:02.93#ibcon#wrote, iclass 15, count 0 2006.257.03:50:02.93#ibcon#about to read 3, iclass 15, count 0 2006.257.03:50:02.96#ibcon#read 3, iclass 15, count 0 2006.257.03:50:02.96#ibcon#about to read 4, iclass 15, count 0 2006.257.03:50:02.96#ibcon#read 4, iclass 15, count 0 2006.257.03:50:02.96#ibcon#about to read 5, iclass 15, count 0 2006.257.03:50:02.96#ibcon#read 5, iclass 15, count 0 2006.257.03:50:02.96#ibcon#about to read 6, iclass 15, count 0 2006.257.03:50:02.96#ibcon#read 6, iclass 15, count 0 2006.257.03:50:02.96#ibcon#end of sib2, iclass 15, count 0 2006.257.03:50:02.96#ibcon#*after write, iclass 15, count 0 2006.257.03:50:02.96#ibcon#*before return 0, iclass 15, count 0 2006.257.03:50:02.96#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:50:02.96#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.03:50:02.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:50:02.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:50:02.96$vck44/vblo=7,734.99 2006.257.03:50:02.96#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.03:50:02.96#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.03:50:02.96#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:02.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:50:02.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:50:02.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:50:02.96#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:50:02.96#ibcon#first serial, iclass 17, count 0 2006.257.03:50:02.96#ibcon#enter sib2, iclass 17, count 0 2006.257.03:50:02.96#ibcon#flushed, iclass 17, count 0 2006.257.03:50:02.96#ibcon#about to write, iclass 17, count 0 2006.257.03:50:02.96#ibcon#wrote, iclass 17, count 0 2006.257.03:50:02.96#ibcon#about to read 3, iclass 17, count 0 2006.257.03:50:02.98#ibcon#read 3, iclass 17, count 0 2006.257.03:50:02.98#ibcon#about to read 4, iclass 17, count 0 2006.257.03:50:02.98#ibcon#read 4, iclass 17, count 0 2006.257.03:50:02.98#ibcon#about to read 5, iclass 17, count 0 2006.257.03:50:02.98#ibcon#read 5, iclass 17, count 0 2006.257.03:50:02.98#ibcon#about to read 6, iclass 17, count 0 2006.257.03:50:02.98#ibcon#read 6, iclass 17, count 0 2006.257.03:50:02.98#ibcon#end of sib2, iclass 17, count 0 2006.257.03:50:02.98#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:50:02.98#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:50:02.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:50:02.98#ibcon#*before write, iclass 17, count 0 2006.257.03:50:02.98#ibcon#enter sib2, iclass 17, count 0 2006.257.03:50:02.98#ibcon#flushed, iclass 17, count 0 2006.257.03:50:02.98#ibcon#about to write, iclass 17, count 0 2006.257.03:50:02.98#ibcon#wrote, iclass 17, count 0 2006.257.03:50:02.98#ibcon#about to read 3, iclass 17, count 0 2006.257.03:50:03.02#ibcon#read 3, iclass 17, count 0 2006.257.03:50:03.02#ibcon#about to read 4, iclass 17, count 0 2006.257.03:50:03.02#ibcon#read 4, iclass 17, count 0 2006.257.03:50:03.02#ibcon#about to read 5, iclass 17, count 0 2006.257.03:50:03.02#ibcon#read 5, iclass 17, count 0 2006.257.03:50:03.02#ibcon#about to read 6, iclass 17, count 0 2006.257.03:50:03.02#ibcon#read 6, iclass 17, count 0 2006.257.03:50:03.02#ibcon#end of sib2, iclass 17, count 0 2006.257.03:50:03.02#ibcon#*after write, iclass 17, count 0 2006.257.03:50:03.02#ibcon#*before return 0, iclass 17, count 0 2006.257.03:50:03.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:50:03.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.03:50:03.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:50:03.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:50:03.02$vck44/vb=7,4 2006.257.03:50:03.02#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.03:50:03.02#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.03:50:03.02#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:03.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:03.08#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:03.08#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:03.08#ibcon#enter wrdev, iclass 19, count 2 2006.257.03:50:03.08#ibcon#first serial, iclass 19, count 2 2006.257.03:50:03.08#ibcon#enter sib2, iclass 19, count 2 2006.257.03:50:03.08#ibcon#flushed, iclass 19, count 2 2006.257.03:50:03.08#ibcon#about to write, iclass 19, count 2 2006.257.03:50:03.08#ibcon#wrote, iclass 19, count 2 2006.257.03:50:03.08#ibcon#about to read 3, iclass 19, count 2 2006.257.03:50:03.10#ibcon#read 3, iclass 19, count 2 2006.257.03:50:03.10#ibcon#about to read 4, iclass 19, count 2 2006.257.03:50:03.10#ibcon#read 4, iclass 19, count 2 2006.257.03:50:03.10#ibcon#about to read 5, iclass 19, count 2 2006.257.03:50:03.10#ibcon#read 5, iclass 19, count 2 2006.257.03:50:03.10#ibcon#about to read 6, iclass 19, count 2 2006.257.03:50:03.10#ibcon#read 6, iclass 19, count 2 2006.257.03:50:03.10#ibcon#end of sib2, iclass 19, count 2 2006.257.03:50:03.10#ibcon#*mode == 0, iclass 19, count 2 2006.257.03:50:03.10#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.03:50:03.10#ibcon#[27=AT07-04\r\n] 2006.257.03:50:03.10#ibcon#*before write, iclass 19, count 2 2006.257.03:50:03.10#ibcon#enter sib2, iclass 19, count 2 2006.257.03:50:03.10#ibcon#flushed, iclass 19, count 2 2006.257.03:50:03.10#ibcon#about to write, iclass 19, count 2 2006.257.03:50:03.10#ibcon#wrote, iclass 19, count 2 2006.257.03:50:03.10#ibcon#about to read 3, iclass 19, count 2 2006.257.03:50:03.13#ibcon#read 3, iclass 19, count 2 2006.257.03:50:03.13#ibcon#about to read 4, iclass 19, count 2 2006.257.03:50:03.13#ibcon#read 4, iclass 19, count 2 2006.257.03:50:03.13#ibcon#about to read 5, iclass 19, count 2 2006.257.03:50:03.13#ibcon#read 5, iclass 19, count 2 2006.257.03:50:03.13#ibcon#about to read 6, iclass 19, count 2 2006.257.03:50:03.13#ibcon#read 6, iclass 19, count 2 2006.257.03:50:03.13#ibcon#end of sib2, iclass 19, count 2 2006.257.03:50:03.13#ibcon#*after write, iclass 19, count 2 2006.257.03:50:03.13#ibcon#*before return 0, iclass 19, count 2 2006.257.03:50:03.13#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:03.13#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.03:50:03.13#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.03:50:03.13#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:03.13#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:03.25#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:03.25#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:03.25#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:50:03.25#ibcon#first serial, iclass 19, count 0 2006.257.03:50:03.25#ibcon#enter sib2, iclass 19, count 0 2006.257.03:50:03.25#ibcon#flushed, iclass 19, count 0 2006.257.03:50:03.25#ibcon#about to write, iclass 19, count 0 2006.257.03:50:03.25#ibcon#wrote, iclass 19, count 0 2006.257.03:50:03.25#ibcon#about to read 3, iclass 19, count 0 2006.257.03:50:03.27#ibcon#read 3, iclass 19, count 0 2006.257.03:50:03.27#ibcon#about to read 4, iclass 19, count 0 2006.257.03:50:03.27#ibcon#read 4, iclass 19, count 0 2006.257.03:50:03.27#ibcon#about to read 5, iclass 19, count 0 2006.257.03:50:03.27#ibcon#read 5, iclass 19, count 0 2006.257.03:50:03.27#ibcon#about to read 6, iclass 19, count 0 2006.257.03:50:03.27#ibcon#read 6, iclass 19, count 0 2006.257.03:50:03.27#ibcon#end of sib2, iclass 19, count 0 2006.257.03:50:03.27#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:50:03.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:50:03.27#ibcon#[27=USB\r\n] 2006.257.03:50:03.27#ibcon#*before write, iclass 19, count 0 2006.257.03:50:03.27#ibcon#enter sib2, iclass 19, count 0 2006.257.03:50:03.27#ibcon#flushed, iclass 19, count 0 2006.257.03:50:03.27#ibcon#about to write, iclass 19, count 0 2006.257.03:50:03.27#ibcon#wrote, iclass 19, count 0 2006.257.03:50:03.27#ibcon#about to read 3, iclass 19, count 0 2006.257.03:50:03.30#ibcon#read 3, iclass 19, count 0 2006.257.03:50:03.30#ibcon#about to read 4, iclass 19, count 0 2006.257.03:50:03.30#ibcon#read 4, iclass 19, count 0 2006.257.03:50:03.30#ibcon#about to read 5, iclass 19, count 0 2006.257.03:50:03.30#ibcon#read 5, iclass 19, count 0 2006.257.03:50:03.30#ibcon#about to read 6, iclass 19, count 0 2006.257.03:50:03.30#ibcon#read 6, iclass 19, count 0 2006.257.03:50:03.30#ibcon#end of sib2, iclass 19, count 0 2006.257.03:50:03.30#ibcon#*after write, iclass 19, count 0 2006.257.03:50:03.30#ibcon#*before return 0, iclass 19, count 0 2006.257.03:50:03.30#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:03.30#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.03:50:03.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:50:03.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:50:03.30$vck44/vblo=8,744.99 2006.257.03:50:03.30#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.03:50:03.30#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.03:50:03.30#ibcon#ireg 17 cls_cnt 0 2006.257.03:50:03.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:03.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:03.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:03.30#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:50:03.30#ibcon#first serial, iclass 21, count 0 2006.257.03:50:03.30#ibcon#enter sib2, iclass 21, count 0 2006.257.03:50:03.30#ibcon#flushed, iclass 21, count 0 2006.257.03:50:03.30#ibcon#about to write, iclass 21, count 0 2006.257.03:50:03.30#ibcon#wrote, iclass 21, count 0 2006.257.03:50:03.30#ibcon#about to read 3, iclass 21, count 0 2006.257.03:50:03.32#ibcon#read 3, iclass 21, count 0 2006.257.03:50:03.32#ibcon#about to read 4, iclass 21, count 0 2006.257.03:50:03.32#ibcon#read 4, iclass 21, count 0 2006.257.03:50:03.32#ibcon#about to read 5, iclass 21, count 0 2006.257.03:50:03.32#ibcon#read 5, iclass 21, count 0 2006.257.03:50:03.32#ibcon#about to read 6, iclass 21, count 0 2006.257.03:50:03.32#ibcon#read 6, iclass 21, count 0 2006.257.03:50:03.32#ibcon#end of sib2, iclass 21, count 0 2006.257.03:50:03.32#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:50:03.32#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:50:03.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:50:03.32#ibcon#*before write, iclass 21, count 0 2006.257.03:50:03.32#ibcon#enter sib2, iclass 21, count 0 2006.257.03:50:03.32#ibcon#flushed, iclass 21, count 0 2006.257.03:50:03.32#ibcon#about to write, iclass 21, count 0 2006.257.03:50:03.32#ibcon#wrote, iclass 21, count 0 2006.257.03:50:03.32#ibcon#about to read 3, iclass 21, count 0 2006.257.03:50:03.36#ibcon#read 3, iclass 21, count 0 2006.257.03:50:03.36#ibcon#about to read 4, iclass 21, count 0 2006.257.03:50:03.36#ibcon#read 4, iclass 21, count 0 2006.257.03:50:03.36#ibcon#about to read 5, iclass 21, count 0 2006.257.03:50:03.36#ibcon#read 5, iclass 21, count 0 2006.257.03:50:03.36#ibcon#about to read 6, iclass 21, count 0 2006.257.03:50:03.36#ibcon#read 6, iclass 21, count 0 2006.257.03:50:03.36#ibcon#end of sib2, iclass 21, count 0 2006.257.03:50:03.36#ibcon#*after write, iclass 21, count 0 2006.257.03:50:03.36#ibcon#*before return 0, iclass 21, count 0 2006.257.03:50:03.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:03.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.03:50:03.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:50:03.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:50:03.36$vck44/vb=8,4 2006.257.03:50:03.36#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.03:50:03.36#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.03:50:03.36#ibcon#ireg 11 cls_cnt 2 2006.257.03:50:03.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:03.42#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:03.42#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:03.42#ibcon#enter wrdev, iclass 23, count 2 2006.257.03:50:03.42#ibcon#first serial, iclass 23, count 2 2006.257.03:50:03.42#ibcon#enter sib2, iclass 23, count 2 2006.257.03:50:03.42#ibcon#flushed, iclass 23, count 2 2006.257.03:50:03.42#ibcon#about to write, iclass 23, count 2 2006.257.03:50:03.42#ibcon#wrote, iclass 23, count 2 2006.257.03:50:03.42#ibcon#about to read 3, iclass 23, count 2 2006.257.03:50:03.44#ibcon#read 3, iclass 23, count 2 2006.257.03:50:03.44#ibcon#about to read 4, iclass 23, count 2 2006.257.03:50:03.44#ibcon#read 4, iclass 23, count 2 2006.257.03:50:03.44#ibcon#about to read 5, iclass 23, count 2 2006.257.03:50:03.44#ibcon#read 5, iclass 23, count 2 2006.257.03:50:03.44#ibcon#about to read 6, iclass 23, count 2 2006.257.03:50:03.44#ibcon#read 6, iclass 23, count 2 2006.257.03:50:03.44#ibcon#end of sib2, iclass 23, count 2 2006.257.03:50:03.44#ibcon#*mode == 0, iclass 23, count 2 2006.257.03:50:03.44#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.03:50:03.44#ibcon#[27=AT08-04\r\n] 2006.257.03:50:03.44#ibcon#*before write, iclass 23, count 2 2006.257.03:50:03.44#ibcon#enter sib2, iclass 23, count 2 2006.257.03:50:03.44#ibcon#flushed, iclass 23, count 2 2006.257.03:50:03.44#ibcon#about to write, iclass 23, count 2 2006.257.03:50:03.44#ibcon#wrote, iclass 23, count 2 2006.257.03:50:03.44#ibcon#about to read 3, iclass 23, count 2 2006.257.03:50:03.46#abcon#<5=/13 1.6 6.8 19.38 951012.3\r\n> 2006.257.03:50:03.47#ibcon#read 3, iclass 23, count 2 2006.257.03:50:03.47#ibcon#about to read 4, iclass 23, count 2 2006.257.03:50:03.47#ibcon#read 4, iclass 23, count 2 2006.257.03:50:03.47#ibcon#about to read 5, iclass 23, count 2 2006.257.03:50:03.47#ibcon#read 5, iclass 23, count 2 2006.257.03:50:03.47#ibcon#about to read 6, iclass 23, count 2 2006.257.03:50:03.47#ibcon#read 6, iclass 23, count 2 2006.257.03:50:03.47#ibcon#end of sib2, iclass 23, count 2 2006.257.03:50:03.47#ibcon#*after write, iclass 23, count 2 2006.257.03:50:03.47#ibcon#*before return 0, iclass 23, count 2 2006.257.03:50:03.47#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:03.47#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.03:50:03.47#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.03:50:03.47#ibcon#ireg 7 cls_cnt 0 2006.257.03:50:03.47#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:03.48#abcon#{5=INTERFACE CLEAR} 2006.257.03:50:03.54#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:50:03.59#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:03.59#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:03.59#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:50:03.59#ibcon#first serial, iclass 23, count 0 2006.257.03:50:03.59#ibcon#enter sib2, iclass 23, count 0 2006.257.03:50:03.59#ibcon#flushed, iclass 23, count 0 2006.257.03:50:03.59#ibcon#about to write, iclass 23, count 0 2006.257.03:50:03.59#ibcon#wrote, iclass 23, count 0 2006.257.03:50:03.59#ibcon#about to read 3, iclass 23, count 0 2006.257.03:50:03.61#ibcon#read 3, iclass 23, count 0 2006.257.03:50:03.61#ibcon#about to read 4, iclass 23, count 0 2006.257.03:50:03.61#ibcon#read 4, iclass 23, count 0 2006.257.03:50:03.61#ibcon#about to read 5, iclass 23, count 0 2006.257.03:50:03.61#ibcon#read 5, iclass 23, count 0 2006.257.03:50:03.61#ibcon#about to read 6, iclass 23, count 0 2006.257.03:50:03.61#ibcon#read 6, iclass 23, count 0 2006.257.03:50:03.61#ibcon#end of sib2, iclass 23, count 0 2006.257.03:50:03.61#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:50:03.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:50:03.61#ibcon#[27=USB\r\n] 2006.257.03:50:03.61#ibcon#*before write, iclass 23, count 0 2006.257.03:50:03.61#ibcon#enter sib2, iclass 23, count 0 2006.257.03:50:03.61#ibcon#flushed, iclass 23, count 0 2006.257.03:50:03.61#ibcon#about to write, iclass 23, count 0 2006.257.03:50:03.61#ibcon#wrote, iclass 23, count 0 2006.257.03:50:03.61#ibcon#about to read 3, iclass 23, count 0 2006.257.03:50:03.64#ibcon#read 3, iclass 23, count 0 2006.257.03:50:03.64#ibcon#about to read 4, iclass 23, count 0 2006.257.03:50:03.64#ibcon#read 4, iclass 23, count 0 2006.257.03:50:03.64#ibcon#about to read 5, iclass 23, count 0 2006.257.03:50:03.64#ibcon#read 5, iclass 23, count 0 2006.257.03:50:03.64#ibcon#about to read 6, iclass 23, count 0 2006.257.03:50:03.64#ibcon#read 6, iclass 23, count 0 2006.257.03:50:03.64#ibcon#end of sib2, iclass 23, count 0 2006.257.03:50:03.64#ibcon#*after write, iclass 23, count 0 2006.257.03:50:03.64#ibcon#*before return 0, iclass 23, count 0 2006.257.03:50:03.64#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:03.64#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.03:50:03.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:50:03.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:50:03.64$vck44/vabw=wide 2006.257.03:50:03.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.03:50:03.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.03:50:03.64#ibcon#ireg 8 cls_cnt 0 2006.257.03:50:03.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:03.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:03.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:03.64#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:50:03.64#ibcon#first serial, iclass 29, count 0 2006.257.03:50:03.64#ibcon#enter sib2, iclass 29, count 0 2006.257.03:50:03.64#ibcon#flushed, iclass 29, count 0 2006.257.03:50:03.64#ibcon#about to write, iclass 29, count 0 2006.257.03:50:03.64#ibcon#wrote, iclass 29, count 0 2006.257.03:50:03.64#ibcon#about to read 3, iclass 29, count 0 2006.257.03:50:03.66#ibcon#read 3, iclass 29, count 0 2006.257.03:50:03.66#ibcon#about to read 4, iclass 29, count 0 2006.257.03:50:03.66#ibcon#read 4, iclass 29, count 0 2006.257.03:50:03.66#ibcon#about to read 5, iclass 29, count 0 2006.257.03:50:03.66#ibcon#read 5, iclass 29, count 0 2006.257.03:50:03.66#ibcon#about to read 6, iclass 29, count 0 2006.257.03:50:03.66#ibcon#read 6, iclass 29, count 0 2006.257.03:50:03.66#ibcon#end of sib2, iclass 29, count 0 2006.257.03:50:03.66#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:50:03.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:50:03.66#ibcon#[25=BW32\r\n] 2006.257.03:50:03.66#ibcon#*before write, iclass 29, count 0 2006.257.03:50:03.66#ibcon#enter sib2, iclass 29, count 0 2006.257.03:50:03.66#ibcon#flushed, iclass 29, count 0 2006.257.03:50:03.66#ibcon#about to write, iclass 29, count 0 2006.257.03:50:03.66#ibcon#wrote, iclass 29, count 0 2006.257.03:50:03.66#ibcon#about to read 3, iclass 29, count 0 2006.257.03:50:03.69#ibcon#read 3, iclass 29, count 0 2006.257.03:50:03.69#ibcon#about to read 4, iclass 29, count 0 2006.257.03:50:03.69#ibcon#read 4, iclass 29, count 0 2006.257.03:50:03.69#ibcon#about to read 5, iclass 29, count 0 2006.257.03:50:03.69#ibcon#read 5, iclass 29, count 0 2006.257.03:50:03.69#ibcon#about to read 6, iclass 29, count 0 2006.257.03:50:03.69#ibcon#read 6, iclass 29, count 0 2006.257.03:50:03.69#ibcon#end of sib2, iclass 29, count 0 2006.257.03:50:03.69#ibcon#*after write, iclass 29, count 0 2006.257.03:50:03.69#ibcon#*before return 0, iclass 29, count 0 2006.257.03:50:03.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:03.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:50:03.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:50:03.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:50:03.69$vck44/vbbw=wide 2006.257.03:50:03.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.03:50:03.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.03:50:03.69#ibcon#ireg 8 cls_cnt 0 2006.257.03:50:03.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:50:03.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:50:03.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:50:03.76#ibcon#enter wrdev, iclass 31, count 0 2006.257.03:50:03.76#ibcon#first serial, iclass 31, count 0 2006.257.03:50:03.76#ibcon#enter sib2, iclass 31, count 0 2006.257.03:50:03.76#ibcon#flushed, iclass 31, count 0 2006.257.03:50:03.76#ibcon#about to write, iclass 31, count 0 2006.257.03:50:03.76#ibcon#wrote, iclass 31, count 0 2006.257.03:50:03.76#ibcon#about to read 3, iclass 31, count 0 2006.257.03:50:03.78#ibcon#read 3, iclass 31, count 0 2006.257.03:50:03.78#ibcon#about to read 4, iclass 31, count 0 2006.257.03:50:03.78#ibcon#read 4, iclass 31, count 0 2006.257.03:50:03.78#ibcon#about to read 5, iclass 31, count 0 2006.257.03:50:03.78#ibcon#read 5, iclass 31, count 0 2006.257.03:50:03.78#ibcon#about to read 6, iclass 31, count 0 2006.257.03:50:03.78#ibcon#read 6, iclass 31, count 0 2006.257.03:50:03.78#ibcon#end of sib2, iclass 31, count 0 2006.257.03:50:03.78#ibcon#*mode == 0, iclass 31, count 0 2006.257.03:50:03.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.03:50:03.78#ibcon#[27=BW32\r\n] 2006.257.03:50:03.78#ibcon#*before write, iclass 31, count 0 2006.257.03:50:03.78#ibcon#enter sib2, iclass 31, count 0 2006.257.03:50:03.78#ibcon#flushed, iclass 31, count 0 2006.257.03:50:03.78#ibcon#about to write, iclass 31, count 0 2006.257.03:50:03.78#ibcon#wrote, iclass 31, count 0 2006.257.03:50:03.78#ibcon#about to read 3, iclass 31, count 0 2006.257.03:50:03.81#ibcon#read 3, iclass 31, count 0 2006.257.03:50:03.81#ibcon#about to read 4, iclass 31, count 0 2006.257.03:50:03.81#ibcon#read 4, iclass 31, count 0 2006.257.03:50:03.81#ibcon#about to read 5, iclass 31, count 0 2006.257.03:50:03.81#ibcon#read 5, iclass 31, count 0 2006.257.03:50:03.81#ibcon#about to read 6, iclass 31, count 0 2006.257.03:50:03.81#ibcon#read 6, iclass 31, count 0 2006.257.03:50:03.81#ibcon#end of sib2, iclass 31, count 0 2006.257.03:50:03.81#ibcon#*after write, iclass 31, count 0 2006.257.03:50:03.81#ibcon#*before return 0, iclass 31, count 0 2006.257.03:50:03.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:50:03.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:50:03.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.03:50:03.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.03:50:03.81$setupk4/ifdk4 2006.257.03:50:03.81$ifdk4/lo= 2006.257.03:50:03.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:50:03.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:50:03.81$ifdk4/patch= 2006.257.03:50:03.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:50:03.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:50:03.81$setupk4/!*+20s 2006.257.03:50:11.14#trakl#Source acquired 2006.257.03:50:11.14#flagr#flagr/antenna,acquired 2006.257.03:50:13.63#abcon#<5=/13 1.5 6.8 19.38 951012.3\r\n> 2006.257.03:50:13.65#abcon#{5=INTERFACE CLEAR} 2006.257.03:50:13.71#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:50:18.32$setupk4/"tpicd 2006.257.03:50:18.32$setupk4/echo=off 2006.257.03:50:18.32$setupk4/xlog=off 2006.257.03:50:18.32:!2006.257.03:50:27 2006.257.03:50:27.00:preob 2006.257.03:50:27.14/onsource/TRACKING 2006.257.03:50:27.14:!2006.257.03:50:37 2006.257.03:50:37.00:"tape 2006.257.03:50:37.00:"st=record 2006.257.03:50:37.00:data_valid=on 2006.257.03:50:37.00:midob 2006.257.03:50:38.14/onsource/TRACKING 2006.257.03:50:38.14/wx/19.37,1012.3,95 2006.257.03:50:38.31/cable/+6.4833E-03 2006.257.03:50:39.40/va/01,08,usb,yes,36,39 2006.257.03:50:39.40/va/02,07,usb,yes,39,39 2006.257.03:50:39.40/va/03,08,usb,yes,35,37 2006.257.03:50:39.40/va/04,07,usb,yes,40,42 2006.257.03:50:39.40/va/05,04,usb,yes,36,37 2006.257.03:50:39.40/va/06,04,usb,yes,40,40 2006.257.03:50:39.40/va/07,04,usb,yes,41,42 2006.257.03:50:39.40/va/08,04,usb,yes,34,42 2006.257.03:50:39.63/valo/01,524.99,yes,locked 2006.257.03:50:39.63/valo/02,534.99,yes,locked 2006.257.03:50:39.63/valo/03,564.99,yes,locked 2006.257.03:50:39.63/valo/04,624.99,yes,locked 2006.257.03:50:39.63/valo/05,734.99,yes,locked 2006.257.03:50:39.63/valo/06,814.99,yes,locked 2006.257.03:50:39.63/valo/07,864.99,yes,locked 2006.257.03:50:39.63/valo/08,884.99,yes,locked 2006.257.03:50:40.72/vb/01,04,usb,yes,34,31 2006.257.03:50:40.72/vb/02,05,usb,yes,32,32 2006.257.03:50:40.72/vb/03,04,usb,yes,33,37 2006.257.03:50:40.72/vb/04,05,usb,yes,33,32 2006.257.03:50:40.72/vb/05,04,usb,yes,30,32 2006.257.03:50:40.72/vb/06,04,usb,yes,35,31 2006.257.03:50:40.72/vb/07,04,usb,yes,35,34 2006.257.03:50:40.72/vb/08,04,usb,yes,32,35 2006.257.03:50:40.96/vblo/01,629.99,yes,locked 2006.257.03:50:40.96/vblo/02,634.99,yes,locked 2006.257.03:50:40.96/vblo/03,649.99,yes,locked 2006.257.03:50:40.96/vblo/04,679.99,yes,locked 2006.257.03:50:40.96/vblo/05,709.99,yes,locked 2006.257.03:50:40.96/vblo/06,719.99,yes,locked 2006.257.03:50:40.96/vblo/07,734.99,yes,locked 2006.257.03:50:40.96/vblo/08,744.99,yes,locked 2006.257.03:50:41.11/vabw/8 2006.257.03:50:41.26/vbbw/8 2006.257.03:50:41.35/xfe/off,on,16.5 2006.257.03:50:41.74/ifatt/23,28,28,28 2006.257.03:50:42.07/fmout-gps/S +4.50E-07 2006.257.03:50:42.11:!2006.257.03:51:17 2006.257.03:51:17.01:data_valid=off 2006.257.03:51:17.01:"et 2006.257.03:51:17.02:!+3s 2006.257.03:51:20.04:"tape 2006.257.03:51:20.04:postob 2006.257.03:51:20.23/cable/+6.4842E-03 2006.257.03:51:20.23/wx/19.35,1012.2,94 2006.257.03:51:20.29/fmout-gps/S +4.51E-07 2006.257.03:51:20.29:scan_name=257-0352,jd0609,50 2006.257.03:51:20.30:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.03:51:22.14#flagr#flagr/antenna,new-source 2006.257.03:51:22.14:checkk5 2006.257.03:51:22.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:51:22.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:51:23.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:51:23.78/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:51:24.16/chk_obsdata//k5ts1/T2570350??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:51:24.56/chk_obsdata//k5ts2/T2570350??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:51:24.99/chk_obsdata//k5ts3/T2570350??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:51:25.38/chk_obsdata//k5ts4/T2570350??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:51:26.12/k5log//k5ts1_log_newline 2006.257.03:51:26.83/k5log//k5ts2_log_newline 2006.257.03:51:27.57/k5log//k5ts3_log_newline 2006.257.03:51:28.31/k5log//k5ts4_log_newline 2006.257.03:51:28.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:51:28.33:setupk4=1 2006.257.03:51:28.33$setupk4/echo=on 2006.257.03:51:28.33$setupk4/pcalon 2006.257.03:51:28.33$pcalon/"no phase cal control is implemented here 2006.257.03:51:28.33$setupk4/"tpicd=stop 2006.257.03:51:28.33$setupk4/"rec=synch_on 2006.257.03:51:28.33$setupk4/"rec_mode=128 2006.257.03:51:28.33$setupk4/!* 2006.257.03:51:28.33$setupk4/recpk4 2006.257.03:51:28.33$recpk4/recpatch= 2006.257.03:51:28.33$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:51:28.33$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:51:28.33$setupk4/vck44 2006.257.03:51:28.33$vck44/valo=1,524.99 2006.257.03:51:28.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.03:51:28.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.03:51:28.33#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:28.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:28.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:28.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:28.33#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:51:28.33#ibcon#first serial, iclass 32, count 0 2006.257.03:51:28.33#ibcon#enter sib2, iclass 32, count 0 2006.257.03:51:28.33#ibcon#flushed, iclass 32, count 0 2006.257.03:51:28.33#ibcon#about to write, iclass 32, count 0 2006.257.03:51:28.33#ibcon#wrote, iclass 32, count 0 2006.257.03:51:28.33#ibcon#about to read 3, iclass 32, count 0 2006.257.03:51:28.35#ibcon#read 3, iclass 32, count 0 2006.257.03:51:28.35#ibcon#about to read 4, iclass 32, count 0 2006.257.03:51:28.35#ibcon#read 4, iclass 32, count 0 2006.257.03:51:28.35#ibcon#about to read 5, iclass 32, count 0 2006.257.03:51:28.35#ibcon#read 5, iclass 32, count 0 2006.257.03:51:28.35#ibcon#about to read 6, iclass 32, count 0 2006.257.03:51:28.35#ibcon#read 6, iclass 32, count 0 2006.257.03:51:28.35#ibcon#end of sib2, iclass 32, count 0 2006.257.03:51:28.35#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:51:28.35#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:51:28.35#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:51:28.35#ibcon#*before write, iclass 32, count 0 2006.257.03:51:28.35#ibcon#enter sib2, iclass 32, count 0 2006.257.03:51:28.35#ibcon#flushed, iclass 32, count 0 2006.257.03:51:28.35#ibcon#about to write, iclass 32, count 0 2006.257.03:51:28.35#ibcon#wrote, iclass 32, count 0 2006.257.03:51:28.35#ibcon#about to read 3, iclass 32, count 0 2006.257.03:51:28.40#ibcon#read 3, iclass 32, count 0 2006.257.03:51:28.40#ibcon#about to read 4, iclass 32, count 0 2006.257.03:51:28.40#ibcon#read 4, iclass 32, count 0 2006.257.03:51:28.40#ibcon#about to read 5, iclass 32, count 0 2006.257.03:51:28.40#ibcon#read 5, iclass 32, count 0 2006.257.03:51:28.40#ibcon#about to read 6, iclass 32, count 0 2006.257.03:51:28.40#ibcon#read 6, iclass 32, count 0 2006.257.03:51:28.40#ibcon#end of sib2, iclass 32, count 0 2006.257.03:51:28.40#ibcon#*after write, iclass 32, count 0 2006.257.03:51:28.40#ibcon#*before return 0, iclass 32, count 0 2006.257.03:51:28.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:28.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:28.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:51:28.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:51:28.40$vck44/va=1,8 2006.257.03:51:28.40#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.03:51:28.40#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.03:51:28.40#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:28.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:28.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:28.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:28.40#ibcon#enter wrdev, iclass 34, count 2 2006.257.03:51:28.40#ibcon#first serial, iclass 34, count 2 2006.257.03:51:28.40#ibcon#enter sib2, iclass 34, count 2 2006.257.03:51:28.40#ibcon#flushed, iclass 34, count 2 2006.257.03:51:28.40#ibcon#about to write, iclass 34, count 2 2006.257.03:51:28.40#ibcon#wrote, iclass 34, count 2 2006.257.03:51:28.40#ibcon#about to read 3, iclass 34, count 2 2006.257.03:51:28.42#ibcon#read 3, iclass 34, count 2 2006.257.03:51:28.42#ibcon#about to read 4, iclass 34, count 2 2006.257.03:51:28.42#ibcon#read 4, iclass 34, count 2 2006.257.03:51:28.42#ibcon#about to read 5, iclass 34, count 2 2006.257.03:51:28.42#ibcon#read 5, iclass 34, count 2 2006.257.03:51:28.42#ibcon#about to read 6, iclass 34, count 2 2006.257.03:51:28.42#ibcon#read 6, iclass 34, count 2 2006.257.03:51:28.42#ibcon#end of sib2, iclass 34, count 2 2006.257.03:51:28.42#ibcon#*mode == 0, iclass 34, count 2 2006.257.03:51:28.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.03:51:28.42#ibcon#[25=AT01-08\r\n] 2006.257.03:51:28.42#ibcon#*before write, iclass 34, count 2 2006.257.03:51:28.42#ibcon#enter sib2, iclass 34, count 2 2006.257.03:51:28.42#ibcon#flushed, iclass 34, count 2 2006.257.03:51:28.42#ibcon#about to write, iclass 34, count 2 2006.257.03:51:28.42#ibcon#wrote, iclass 34, count 2 2006.257.03:51:28.42#ibcon#about to read 3, iclass 34, count 2 2006.257.03:51:28.45#ibcon#read 3, iclass 34, count 2 2006.257.03:51:28.45#ibcon#about to read 4, iclass 34, count 2 2006.257.03:51:28.45#ibcon#read 4, iclass 34, count 2 2006.257.03:51:28.45#ibcon#about to read 5, iclass 34, count 2 2006.257.03:51:28.45#ibcon#read 5, iclass 34, count 2 2006.257.03:51:28.45#ibcon#about to read 6, iclass 34, count 2 2006.257.03:51:28.45#ibcon#read 6, iclass 34, count 2 2006.257.03:51:28.45#ibcon#end of sib2, iclass 34, count 2 2006.257.03:51:28.45#ibcon#*after write, iclass 34, count 2 2006.257.03:51:28.45#ibcon#*before return 0, iclass 34, count 2 2006.257.03:51:28.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:28.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:28.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.03:51:28.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:28.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:28.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:28.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:28.57#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:51:28.57#ibcon#first serial, iclass 34, count 0 2006.257.03:51:28.57#ibcon#enter sib2, iclass 34, count 0 2006.257.03:51:28.57#ibcon#flushed, iclass 34, count 0 2006.257.03:51:28.57#ibcon#about to write, iclass 34, count 0 2006.257.03:51:28.57#ibcon#wrote, iclass 34, count 0 2006.257.03:51:28.57#ibcon#about to read 3, iclass 34, count 0 2006.257.03:51:28.59#ibcon#read 3, iclass 34, count 0 2006.257.03:51:28.59#ibcon#about to read 4, iclass 34, count 0 2006.257.03:51:28.59#ibcon#read 4, iclass 34, count 0 2006.257.03:51:28.59#ibcon#about to read 5, iclass 34, count 0 2006.257.03:51:28.59#ibcon#read 5, iclass 34, count 0 2006.257.03:51:28.59#ibcon#about to read 6, iclass 34, count 0 2006.257.03:51:28.59#ibcon#read 6, iclass 34, count 0 2006.257.03:51:28.59#ibcon#end of sib2, iclass 34, count 0 2006.257.03:51:28.59#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:51:28.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:51:28.59#ibcon#[25=USB\r\n] 2006.257.03:51:28.59#ibcon#*before write, iclass 34, count 0 2006.257.03:51:28.59#ibcon#enter sib2, iclass 34, count 0 2006.257.03:51:28.59#ibcon#flushed, iclass 34, count 0 2006.257.03:51:28.59#ibcon#about to write, iclass 34, count 0 2006.257.03:51:28.59#ibcon#wrote, iclass 34, count 0 2006.257.03:51:28.59#ibcon#about to read 3, iclass 34, count 0 2006.257.03:51:28.62#ibcon#read 3, iclass 34, count 0 2006.257.03:51:28.62#ibcon#about to read 4, iclass 34, count 0 2006.257.03:51:28.62#ibcon#read 4, iclass 34, count 0 2006.257.03:51:28.62#ibcon#about to read 5, iclass 34, count 0 2006.257.03:51:28.62#ibcon#read 5, iclass 34, count 0 2006.257.03:51:28.62#ibcon#about to read 6, iclass 34, count 0 2006.257.03:51:28.62#ibcon#read 6, iclass 34, count 0 2006.257.03:51:28.62#ibcon#end of sib2, iclass 34, count 0 2006.257.03:51:28.62#ibcon#*after write, iclass 34, count 0 2006.257.03:51:28.62#ibcon#*before return 0, iclass 34, count 0 2006.257.03:51:28.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:28.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:28.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:51:28.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:51:28.62$vck44/valo=2,534.99 2006.257.03:51:28.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.03:51:28.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.03:51:28.62#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:28.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:28.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:28.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:28.62#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:51:28.62#ibcon#first serial, iclass 36, count 0 2006.257.03:51:28.62#ibcon#enter sib2, iclass 36, count 0 2006.257.03:51:28.62#ibcon#flushed, iclass 36, count 0 2006.257.03:51:28.62#ibcon#about to write, iclass 36, count 0 2006.257.03:51:28.62#ibcon#wrote, iclass 36, count 0 2006.257.03:51:28.62#ibcon#about to read 3, iclass 36, count 0 2006.257.03:51:28.64#ibcon#read 3, iclass 36, count 0 2006.257.03:51:28.64#ibcon#about to read 4, iclass 36, count 0 2006.257.03:51:28.64#ibcon#read 4, iclass 36, count 0 2006.257.03:51:28.64#ibcon#about to read 5, iclass 36, count 0 2006.257.03:51:28.64#ibcon#read 5, iclass 36, count 0 2006.257.03:51:28.64#ibcon#about to read 6, iclass 36, count 0 2006.257.03:51:28.64#ibcon#read 6, iclass 36, count 0 2006.257.03:51:28.64#ibcon#end of sib2, iclass 36, count 0 2006.257.03:51:28.64#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:51:28.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:51:28.64#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:51:28.64#ibcon#*before write, iclass 36, count 0 2006.257.03:51:28.64#ibcon#enter sib2, iclass 36, count 0 2006.257.03:51:28.64#ibcon#flushed, iclass 36, count 0 2006.257.03:51:28.64#ibcon#about to write, iclass 36, count 0 2006.257.03:51:28.64#ibcon#wrote, iclass 36, count 0 2006.257.03:51:28.64#ibcon#about to read 3, iclass 36, count 0 2006.257.03:51:28.68#ibcon#read 3, iclass 36, count 0 2006.257.03:51:28.68#ibcon#about to read 4, iclass 36, count 0 2006.257.03:51:28.68#ibcon#read 4, iclass 36, count 0 2006.257.03:51:28.68#ibcon#about to read 5, iclass 36, count 0 2006.257.03:51:28.68#ibcon#read 5, iclass 36, count 0 2006.257.03:51:28.68#ibcon#about to read 6, iclass 36, count 0 2006.257.03:51:28.68#ibcon#read 6, iclass 36, count 0 2006.257.03:51:28.68#ibcon#end of sib2, iclass 36, count 0 2006.257.03:51:28.68#ibcon#*after write, iclass 36, count 0 2006.257.03:51:28.68#ibcon#*before return 0, iclass 36, count 0 2006.257.03:51:28.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:28.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:28.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:51:28.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:51:28.68$vck44/va=2,7 2006.257.03:51:28.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.03:51:28.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.03:51:28.68#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:28.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:28.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:28.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:28.74#ibcon#enter wrdev, iclass 38, count 2 2006.257.03:51:28.74#ibcon#first serial, iclass 38, count 2 2006.257.03:51:28.74#ibcon#enter sib2, iclass 38, count 2 2006.257.03:51:28.74#ibcon#flushed, iclass 38, count 2 2006.257.03:51:28.74#ibcon#about to write, iclass 38, count 2 2006.257.03:51:28.74#ibcon#wrote, iclass 38, count 2 2006.257.03:51:28.74#ibcon#about to read 3, iclass 38, count 2 2006.257.03:51:28.76#ibcon#read 3, iclass 38, count 2 2006.257.03:51:28.76#ibcon#about to read 4, iclass 38, count 2 2006.257.03:51:28.76#ibcon#read 4, iclass 38, count 2 2006.257.03:51:28.76#ibcon#about to read 5, iclass 38, count 2 2006.257.03:51:28.76#ibcon#read 5, iclass 38, count 2 2006.257.03:51:28.76#ibcon#about to read 6, iclass 38, count 2 2006.257.03:51:28.76#ibcon#read 6, iclass 38, count 2 2006.257.03:51:28.76#ibcon#end of sib2, iclass 38, count 2 2006.257.03:51:28.76#ibcon#*mode == 0, iclass 38, count 2 2006.257.03:51:28.76#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.03:51:28.76#ibcon#[25=AT02-07\r\n] 2006.257.03:51:28.76#ibcon#*before write, iclass 38, count 2 2006.257.03:51:28.76#ibcon#enter sib2, iclass 38, count 2 2006.257.03:51:28.76#ibcon#flushed, iclass 38, count 2 2006.257.03:51:28.76#ibcon#about to write, iclass 38, count 2 2006.257.03:51:28.76#ibcon#wrote, iclass 38, count 2 2006.257.03:51:28.76#ibcon#about to read 3, iclass 38, count 2 2006.257.03:51:28.79#ibcon#read 3, iclass 38, count 2 2006.257.03:51:28.79#ibcon#about to read 4, iclass 38, count 2 2006.257.03:51:28.79#ibcon#read 4, iclass 38, count 2 2006.257.03:51:28.79#ibcon#about to read 5, iclass 38, count 2 2006.257.03:51:28.79#ibcon#read 5, iclass 38, count 2 2006.257.03:51:28.79#ibcon#about to read 6, iclass 38, count 2 2006.257.03:51:28.79#ibcon#read 6, iclass 38, count 2 2006.257.03:51:28.79#ibcon#end of sib2, iclass 38, count 2 2006.257.03:51:28.79#ibcon#*after write, iclass 38, count 2 2006.257.03:51:28.79#ibcon#*before return 0, iclass 38, count 2 2006.257.03:51:28.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:28.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:28.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.03:51:28.79#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:28.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:28.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:28.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:28.91#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:51:28.91#ibcon#first serial, iclass 38, count 0 2006.257.03:51:28.91#ibcon#enter sib2, iclass 38, count 0 2006.257.03:51:28.91#ibcon#flushed, iclass 38, count 0 2006.257.03:51:28.91#ibcon#about to write, iclass 38, count 0 2006.257.03:51:28.91#ibcon#wrote, iclass 38, count 0 2006.257.03:51:28.91#ibcon#about to read 3, iclass 38, count 0 2006.257.03:51:28.93#ibcon#read 3, iclass 38, count 0 2006.257.03:51:28.93#ibcon#about to read 4, iclass 38, count 0 2006.257.03:51:28.93#ibcon#read 4, iclass 38, count 0 2006.257.03:51:28.93#ibcon#about to read 5, iclass 38, count 0 2006.257.03:51:28.93#ibcon#read 5, iclass 38, count 0 2006.257.03:51:28.93#ibcon#about to read 6, iclass 38, count 0 2006.257.03:51:28.93#ibcon#read 6, iclass 38, count 0 2006.257.03:51:28.93#ibcon#end of sib2, iclass 38, count 0 2006.257.03:51:28.93#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:51:28.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:51:28.93#ibcon#[25=USB\r\n] 2006.257.03:51:28.93#ibcon#*before write, iclass 38, count 0 2006.257.03:51:28.93#ibcon#enter sib2, iclass 38, count 0 2006.257.03:51:28.93#ibcon#flushed, iclass 38, count 0 2006.257.03:51:28.93#ibcon#about to write, iclass 38, count 0 2006.257.03:51:28.93#ibcon#wrote, iclass 38, count 0 2006.257.03:51:28.93#ibcon#about to read 3, iclass 38, count 0 2006.257.03:51:28.96#ibcon#read 3, iclass 38, count 0 2006.257.03:51:28.96#ibcon#about to read 4, iclass 38, count 0 2006.257.03:51:28.96#ibcon#read 4, iclass 38, count 0 2006.257.03:51:28.96#ibcon#about to read 5, iclass 38, count 0 2006.257.03:51:28.96#ibcon#read 5, iclass 38, count 0 2006.257.03:51:28.96#ibcon#about to read 6, iclass 38, count 0 2006.257.03:51:28.96#ibcon#read 6, iclass 38, count 0 2006.257.03:51:28.96#ibcon#end of sib2, iclass 38, count 0 2006.257.03:51:28.96#ibcon#*after write, iclass 38, count 0 2006.257.03:51:28.96#ibcon#*before return 0, iclass 38, count 0 2006.257.03:51:28.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:28.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:28.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:51:28.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:51:28.96$vck44/valo=3,564.99 2006.257.03:51:28.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.03:51:28.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.03:51:28.96#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:28.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:28.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:28.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:28.96#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:51:28.96#ibcon#first serial, iclass 40, count 0 2006.257.03:51:28.96#ibcon#enter sib2, iclass 40, count 0 2006.257.03:51:28.96#ibcon#flushed, iclass 40, count 0 2006.257.03:51:28.96#ibcon#about to write, iclass 40, count 0 2006.257.03:51:28.96#ibcon#wrote, iclass 40, count 0 2006.257.03:51:28.96#ibcon#about to read 3, iclass 40, count 0 2006.257.03:51:28.98#ibcon#read 3, iclass 40, count 0 2006.257.03:51:28.98#ibcon#about to read 4, iclass 40, count 0 2006.257.03:51:28.98#ibcon#read 4, iclass 40, count 0 2006.257.03:51:28.98#ibcon#about to read 5, iclass 40, count 0 2006.257.03:51:28.98#ibcon#read 5, iclass 40, count 0 2006.257.03:51:28.98#ibcon#about to read 6, iclass 40, count 0 2006.257.03:51:28.98#ibcon#read 6, iclass 40, count 0 2006.257.03:51:28.98#ibcon#end of sib2, iclass 40, count 0 2006.257.03:51:28.98#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:51:28.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:51:28.98#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:51:28.98#ibcon#*before write, iclass 40, count 0 2006.257.03:51:28.98#ibcon#enter sib2, iclass 40, count 0 2006.257.03:51:28.98#ibcon#flushed, iclass 40, count 0 2006.257.03:51:28.98#ibcon#about to write, iclass 40, count 0 2006.257.03:51:28.98#ibcon#wrote, iclass 40, count 0 2006.257.03:51:28.98#ibcon#about to read 3, iclass 40, count 0 2006.257.03:51:29.02#ibcon#read 3, iclass 40, count 0 2006.257.03:51:29.02#ibcon#about to read 4, iclass 40, count 0 2006.257.03:51:29.02#ibcon#read 4, iclass 40, count 0 2006.257.03:51:29.02#ibcon#about to read 5, iclass 40, count 0 2006.257.03:51:29.02#ibcon#read 5, iclass 40, count 0 2006.257.03:51:29.02#ibcon#about to read 6, iclass 40, count 0 2006.257.03:51:29.02#ibcon#read 6, iclass 40, count 0 2006.257.03:51:29.02#ibcon#end of sib2, iclass 40, count 0 2006.257.03:51:29.02#ibcon#*after write, iclass 40, count 0 2006.257.03:51:29.02#ibcon#*before return 0, iclass 40, count 0 2006.257.03:51:29.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:29.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:29.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:51:29.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:51:29.02$vck44/va=3,8 2006.257.03:51:29.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.03:51:29.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.03:51:29.02#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:29.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:29.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:29.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:29.08#ibcon#enter wrdev, iclass 4, count 2 2006.257.03:51:29.08#ibcon#first serial, iclass 4, count 2 2006.257.03:51:29.08#ibcon#enter sib2, iclass 4, count 2 2006.257.03:51:29.08#ibcon#flushed, iclass 4, count 2 2006.257.03:51:29.08#ibcon#about to write, iclass 4, count 2 2006.257.03:51:29.08#ibcon#wrote, iclass 4, count 2 2006.257.03:51:29.08#ibcon#about to read 3, iclass 4, count 2 2006.257.03:51:29.10#ibcon#read 3, iclass 4, count 2 2006.257.03:51:29.10#ibcon#about to read 4, iclass 4, count 2 2006.257.03:51:29.10#ibcon#read 4, iclass 4, count 2 2006.257.03:51:29.10#ibcon#about to read 5, iclass 4, count 2 2006.257.03:51:29.10#ibcon#read 5, iclass 4, count 2 2006.257.03:51:29.10#ibcon#about to read 6, iclass 4, count 2 2006.257.03:51:29.10#ibcon#read 6, iclass 4, count 2 2006.257.03:51:29.10#ibcon#end of sib2, iclass 4, count 2 2006.257.03:51:29.10#ibcon#*mode == 0, iclass 4, count 2 2006.257.03:51:29.10#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.03:51:29.10#ibcon#[25=AT03-08\r\n] 2006.257.03:51:29.10#ibcon#*before write, iclass 4, count 2 2006.257.03:51:29.10#ibcon#enter sib2, iclass 4, count 2 2006.257.03:51:29.10#ibcon#flushed, iclass 4, count 2 2006.257.03:51:29.10#ibcon#about to write, iclass 4, count 2 2006.257.03:51:29.10#ibcon#wrote, iclass 4, count 2 2006.257.03:51:29.10#ibcon#about to read 3, iclass 4, count 2 2006.257.03:51:29.13#ibcon#read 3, iclass 4, count 2 2006.257.03:51:29.13#ibcon#about to read 4, iclass 4, count 2 2006.257.03:51:29.13#ibcon#read 4, iclass 4, count 2 2006.257.03:51:29.13#ibcon#about to read 5, iclass 4, count 2 2006.257.03:51:29.13#ibcon#read 5, iclass 4, count 2 2006.257.03:51:29.13#ibcon#about to read 6, iclass 4, count 2 2006.257.03:51:29.13#ibcon#read 6, iclass 4, count 2 2006.257.03:51:29.13#ibcon#end of sib2, iclass 4, count 2 2006.257.03:51:29.13#ibcon#*after write, iclass 4, count 2 2006.257.03:51:29.13#ibcon#*before return 0, iclass 4, count 2 2006.257.03:51:29.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:29.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:29.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.03:51:29.13#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:29.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:29.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:29.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:29.25#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:51:29.25#ibcon#first serial, iclass 4, count 0 2006.257.03:51:29.25#ibcon#enter sib2, iclass 4, count 0 2006.257.03:51:29.25#ibcon#flushed, iclass 4, count 0 2006.257.03:51:29.25#ibcon#about to write, iclass 4, count 0 2006.257.03:51:29.25#ibcon#wrote, iclass 4, count 0 2006.257.03:51:29.25#ibcon#about to read 3, iclass 4, count 0 2006.257.03:51:29.27#ibcon#read 3, iclass 4, count 0 2006.257.03:51:29.27#ibcon#about to read 4, iclass 4, count 0 2006.257.03:51:29.27#ibcon#read 4, iclass 4, count 0 2006.257.03:51:29.27#ibcon#about to read 5, iclass 4, count 0 2006.257.03:51:29.27#ibcon#read 5, iclass 4, count 0 2006.257.03:51:29.27#ibcon#about to read 6, iclass 4, count 0 2006.257.03:51:29.27#ibcon#read 6, iclass 4, count 0 2006.257.03:51:29.27#ibcon#end of sib2, iclass 4, count 0 2006.257.03:51:29.27#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:51:29.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:51:29.27#ibcon#[25=USB\r\n] 2006.257.03:51:29.27#ibcon#*before write, iclass 4, count 0 2006.257.03:51:29.27#ibcon#enter sib2, iclass 4, count 0 2006.257.03:51:29.27#ibcon#flushed, iclass 4, count 0 2006.257.03:51:29.27#ibcon#about to write, iclass 4, count 0 2006.257.03:51:29.27#ibcon#wrote, iclass 4, count 0 2006.257.03:51:29.27#ibcon#about to read 3, iclass 4, count 0 2006.257.03:51:29.30#ibcon#read 3, iclass 4, count 0 2006.257.03:51:29.30#ibcon#about to read 4, iclass 4, count 0 2006.257.03:51:29.30#ibcon#read 4, iclass 4, count 0 2006.257.03:51:29.30#ibcon#about to read 5, iclass 4, count 0 2006.257.03:51:29.30#ibcon#read 5, iclass 4, count 0 2006.257.03:51:29.30#ibcon#about to read 6, iclass 4, count 0 2006.257.03:51:29.30#ibcon#read 6, iclass 4, count 0 2006.257.03:51:29.30#ibcon#end of sib2, iclass 4, count 0 2006.257.03:51:29.30#ibcon#*after write, iclass 4, count 0 2006.257.03:51:29.30#ibcon#*before return 0, iclass 4, count 0 2006.257.03:51:29.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:29.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:29.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:51:29.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:51:29.30$vck44/valo=4,624.99 2006.257.03:51:29.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.03:51:29.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.03:51:29.30#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:29.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:29.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:29.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:29.30#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:51:29.30#ibcon#first serial, iclass 6, count 0 2006.257.03:51:29.30#ibcon#enter sib2, iclass 6, count 0 2006.257.03:51:29.30#ibcon#flushed, iclass 6, count 0 2006.257.03:51:29.30#ibcon#about to write, iclass 6, count 0 2006.257.03:51:29.30#ibcon#wrote, iclass 6, count 0 2006.257.03:51:29.30#ibcon#about to read 3, iclass 6, count 0 2006.257.03:51:29.32#ibcon#read 3, iclass 6, count 0 2006.257.03:51:29.32#ibcon#about to read 4, iclass 6, count 0 2006.257.03:51:29.32#ibcon#read 4, iclass 6, count 0 2006.257.03:51:29.32#ibcon#about to read 5, iclass 6, count 0 2006.257.03:51:29.32#ibcon#read 5, iclass 6, count 0 2006.257.03:51:29.32#ibcon#about to read 6, iclass 6, count 0 2006.257.03:51:29.32#ibcon#read 6, iclass 6, count 0 2006.257.03:51:29.32#ibcon#end of sib2, iclass 6, count 0 2006.257.03:51:29.32#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:51:29.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:51:29.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:51:29.32#ibcon#*before write, iclass 6, count 0 2006.257.03:51:29.32#ibcon#enter sib2, iclass 6, count 0 2006.257.03:51:29.32#ibcon#flushed, iclass 6, count 0 2006.257.03:51:29.32#ibcon#about to write, iclass 6, count 0 2006.257.03:51:29.32#ibcon#wrote, iclass 6, count 0 2006.257.03:51:29.32#ibcon#about to read 3, iclass 6, count 0 2006.257.03:51:29.36#ibcon#read 3, iclass 6, count 0 2006.257.03:51:29.36#ibcon#about to read 4, iclass 6, count 0 2006.257.03:51:29.36#ibcon#read 4, iclass 6, count 0 2006.257.03:51:29.36#ibcon#about to read 5, iclass 6, count 0 2006.257.03:51:29.36#ibcon#read 5, iclass 6, count 0 2006.257.03:51:29.36#ibcon#about to read 6, iclass 6, count 0 2006.257.03:51:29.36#ibcon#read 6, iclass 6, count 0 2006.257.03:51:29.36#ibcon#end of sib2, iclass 6, count 0 2006.257.03:51:29.36#ibcon#*after write, iclass 6, count 0 2006.257.03:51:29.36#ibcon#*before return 0, iclass 6, count 0 2006.257.03:51:29.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:29.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:29.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:51:29.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:51:29.36$vck44/va=4,7 2006.257.03:51:29.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.03:51:29.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.03:51:29.36#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:29.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:29.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:29.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:29.42#ibcon#enter wrdev, iclass 10, count 2 2006.257.03:51:29.42#ibcon#first serial, iclass 10, count 2 2006.257.03:51:29.42#ibcon#enter sib2, iclass 10, count 2 2006.257.03:51:29.42#ibcon#flushed, iclass 10, count 2 2006.257.03:51:29.42#ibcon#about to write, iclass 10, count 2 2006.257.03:51:29.42#ibcon#wrote, iclass 10, count 2 2006.257.03:51:29.42#ibcon#about to read 3, iclass 10, count 2 2006.257.03:51:29.44#ibcon#read 3, iclass 10, count 2 2006.257.03:51:29.44#ibcon#about to read 4, iclass 10, count 2 2006.257.03:51:29.44#ibcon#read 4, iclass 10, count 2 2006.257.03:51:29.44#ibcon#about to read 5, iclass 10, count 2 2006.257.03:51:29.44#ibcon#read 5, iclass 10, count 2 2006.257.03:51:29.44#ibcon#about to read 6, iclass 10, count 2 2006.257.03:51:29.44#ibcon#read 6, iclass 10, count 2 2006.257.03:51:29.44#ibcon#end of sib2, iclass 10, count 2 2006.257.03:51:29.44#ibcon#*mode == 0, iclass 10, count 2 2006.257.03:51:29.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.03:51:29.44#ibcon#[25=AT04-07\r\n] 2006.257.03:51:29.44#ibcon#*before write, iclass 10, count 2 2006.257.03:51:29.44#ibcon#enter sib2, iclass 10, count 2 2006.257.03:51:29.44#ibcon#flushed, iclass 10, count 2 2006.257.03:51:29.44#ibcon#about to write, iclass 10, count 2 2006.257.03:51:29.44#ibcon#wrote, iclass 10, count 2 2006.257.03:51:29.44#ibcon#about to read 3, iclass 10, count 2 2006.257.03:51:29.47#ibcon#read 3, iclass 10, count 2 2006.257.03:51:29.47#ibcon#about to read 4, iclass 10, count 2 2006.257.03:51:29.47#ibcon#read 4, iclass 10, count 2 2006.257.03:51:29.47#ibcon#about to read 5, iclass 10, count 2 2006.257.03:51:29.47#ibcon#read 5, iclass 10, count 2 2006.257.03:51:29.47#ibcon#about to read 6, iclass 10, count 2 2006.257.03:51:29.47#ibcon#read 6, iclass 10, count 2 2006.257.03:51:29.47#ibcon#end of sib2, iclass 10, count 2 2006.257.03:51:29.47#ibcon#*after write, iclass 10, count 2 2006.257.03:51:29.47#ibcon#*before return 0, iclass 10, count 2 2006.257.03:51:29.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:29.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:29.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.03:51:29.47#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:29.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:29.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:29.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:29.59#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:51:29.59#ibcon#first serial, iclass 10, count 0 2006.257.03:51:29.59#ibcon#enter sib2, iclass 10, count 0 2006.257.03:51:29.59#ibcon#flushed, iclass 10, count 0 2006.257.03:51:29.59#ibcon#about to write, iclass 10, count 0 2006.257.03:51:29.59#ibcon#wrote, iclass 10, count 0 2006.257.03:51:29.59#ibcon#about to read 3, iclass 10, count 0 2006.257.03:51:29.61#ibcon#read 3, iclass 10, count 0 2006.257.03:51:29.61#ibcon#about to read 4, iclass 10, count 0 2006.257.03:51:29.61#ibcon#read 4, iclass 10, count 0 2006.257.03:51:29.61#ibcon#about to read 5, iclass 10, count 0 2006.257.03:51:29.61#ibcon#read 5, iclass 10, count 0 2006.257.03:51:29.61#ibcon#about to read 6, iclass 10, count 0 2006.257.03:51:29.61#ibcon#read 6, iclass 10, count 0 2006.257.03:51:29.61#ibcon#end of sib2, iclass 10, count 0 2006.257.03:51:29.61#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:51:29.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:51:29.61#ibcon#[25=USB\r\n] 2006.257.03:51:29.61#ibcon#*before write, iclass 10, count 0 2006.257.03:51:29.61#ibcon#enter sib2, iclass 10, count 0 2006.257.03:51:29.61#ibcon#flushed, iclass 10, count 0 2006.257.03:51:29.61#ibcon#about to write, iclass 10, count 0 2006.257.03:51:29.61#ibcon#wrote, iclass 10, count 0 2006.257.03:51:29.61#ibcon#about to read 3, iclass 10, count 0 2006.257.03:51:29.64#ibcon#read 3, iclass 10, count 0 2006.257.03:51:29.64#ibcon#about to read 4, iclass 10, count 0 2006.257.03:51:29.64#ibcon#read 4, iclass 10, count 0 2006.257.03:51:29.64#ibcon#about to read 5, iclass 10, count 0 2006.257.03:51:29.64#ibcon#read 5, iclass 10, count 0 2006.257.03:51:29.64#ibcon#about to read 6, iclass 10, count 0 2006.257.03:51:29.64#ibcon#read 6, iclass 10, count 0 2006.257.03:51:29.64#ibcon#end of sib2, iclass 10, count 0 2006.257.03:51:29.64#ibcon#*after write, iclass 10, count 0 2006.257.03:51:29.64#ibcon#*before return 0, iclass 10, count 0 2006.257.03:51:29.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:29.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:29.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:51:29.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:51:29.64$vck44/valo=5,734.99 2006.257.03:51:29.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.03:51:29.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.03:51:29.64#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:29.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:29.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:29.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:29.64#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:51:29.64#ibcon#first serial, iclass 12, count 0 2006.257.03:51:29.64#ibcon#enter sib2, iclass 12, count 0 2006.257.03:51:29.64#ibcon#flushed, iclass 12, count 0 2006.257.03:51:29.64#ibcon#about to write, iclass 12, count 0 2006.257.03:51:29.64#ibcon#wrote, iclass 12, count 0 2006.257.03:51:29.64#ibcon#about to read 3, iclass 12, count 0 2006.257.03:51:29.66#ibcon#read 3, iclass 12, count 0 2006.257.03:51:29.66#ibcon#about to read 4, iclass 12, count 0 2006.257.03:51:29.66#ibcon#read 4, iclass 12, count 0 2006.257.03:51:29.66#ibcon#about to read 5, iclass 12, count 0 2006.257.03:51:29.66#ibcon#read 5, iclass 12, count 0 2006.257.03:51:29.66#ibcon#about to read 6, iclass 12, count 0 2006.257.03:51:29.66#ibcon#read 6, iclass 12, count 0 2006.257.03:51:29.66#ibcon#end of sib2, iclass 12, count 0 2006.257.03:51:29.66#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:51:29.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:51:29.66#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:51:29.66#ibcon#*before write, iclass 12, count 0 2006.257.03:51:29.66#ibcon#enter sib2, iclass 12, count 0 2006.257.03:51:29.66#ibcon#flushed, iclass 12, count 0 2006.257.03:51:29.66#ibcon#about to write, iclass 12, count 0 2006.257.03:51:29.66#ibcon#wrote, iclass 12, count 0 2006.257.03:51:29.66#ibcon#about to read 3, iclass 12, count 0 2006.257.03:51:29.70#ibcon#read 3, iclass 12, count 0 2006.257.03:51:29.70#ibcon#about to read 4, iclass 12, count 0 2006.257.03:51:29.70#ibcon#read 4, iclass 12, count 0 2006.257.03:51:29.70#ibcon#about to read 5, iclass 12, count 0 2006.257.03:51:29.70#ibcon#read 5, iclass 12, count 0 2006.257.03:51:29.70#ibcon#about to read 6, iclass 12, count 0 2006.257.03:51:29.70#ibcon#read 6, iclass 12, count 0 2006.257.03:51:29.70#ibcon#end of sib2, iclass 12, count 0 2006.257.03:51:29.70#ibcon#*after write, iclass 12, count 0 2006.257.03:51:29.70#ibcon#*before return 0, iclass 12, count 0 2006.257.03:51:29.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:29.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:29.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:51:29.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:51:29.70$vck44/va=5,4 2006.257.03:51:29.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.03:51:29.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.03:51:29.70#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:29.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:29.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:29.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:29.76#ibcon#enter wrdev, iclass 14, count 2 2006.257.03:51:29.76#ibcon#first serial, iclass 14, count 2 2006.257.03:51:29.76#ibcon#enter sib2, iclass 14, count 2 2006.257.03:51:29.76#ibcon#flushed, iclass 14, count 2 2006.257.03:51:29.76#ibcon#about to write, iclass 14, count 2 2006.257.03:51:29.76#ibcon#wrote, iclass 14, count 2 2006.257.03:51:29.76#ibcon#about to read 3, iclass 14, count 2 2006.257.03:51:29.78#ibcon#read 3, iclass 14, count 2 2006.257.03:51:29.78#ibcon#about to read 4, iclass 14, count 2 2006.257.03:51:29.78#ibcon#read 4, iclass 14, count 2 2006.257.03:51:29.78#ibcon#about to read 5, iclass 14, count 2 2006.257.03:51:29.78#ibcon#read 5, iclass 14, count 2 2006.257.03:51:29.78#ibcon#about to read 6, iclass 14, count 2 2006.257.03:51:29.78#ibcon#read 6, iclass 14, count 2 2006.257.03:51:29.78#ibcon#end of sib2, iclass 14, count 2 2006.257.03:51:29.78#ibcon#*mode == 0, iclass 14, count 2 2006.257.03:51:29.78#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.03:51:29.78#ibcon#[25=AT05-04\r\n] 2006.257.03:51:29.78#ibcon#*before write, iclass 14, count 2 2006.257.03:51:29.78#ibcon#enter sib2, iclass 14, count 2 2006.257.03:51:29.78#ibcon#flushed, iclass 14, count 2 2006.257.03:51:29.78#ibcon#about to write, iclass 14, count 2 2006.257.03:51:29.78#ibcon#wrote, iclass 14, count 2 2006.257.03:51:29.78#ibcon#about to read 3, iclass 14, count 2 2006.257.03:51:29.81#ibcon#read 3, iclass 14, count 2 2006.257.03:51:29.81#ibcon#about to read 4, iclass 14, count 2 2006.257.03:51:29.81#ibcon#read 4, iclass 14, count 2 2006.257.03:51:29.81#ibcon#about to read 5, iclass 14, count 2 2006.257.03:51:29.81#ibcon#read 5, iclass 14, count 2 2006.257.03:51:29.81#ibcon#about to read 6, iclass 14, count 2 2006.257.03:51:29.81#ibcon#read 6, iclass 14, count 2 2006.257.03:51:29.81#ibcon#end of sib2, iclass 14, count 2 2006.257.03:51:29.81#ibcon#*after write, iclass 14, count 2 2006.257.03:51:29.81#ibcon#*before return 0, iclass 14, count 2 2006.257.03:51:29.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:29.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:29.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.03:51:29.81#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:29.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:29.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:29.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:29.93#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:51:29.93#ibcon#first serial, iclass 14, count 0 2006.257.03:51:29.93#ibcon#enter sib2, iclass 14, count 0 2006.257.03:51:29.93#ibcon#flushed, iclass 14, count 0 2006.257.03:51:29.93#ibcon#about to write, iclass 14, count 0 2006.257.03:51:29.93#ibcon#wrote, iclass 14, count 0 2006.257.03:51:29.93#ibcon#about to read 3, iclass 14, count 0 2006.257.03:51:29.95#ibcon#read 3, iclass 14, count 0 2006.257.03:51:29.95#ibcon#about to read 4, iclass 14, count 0 2006.257.03:51:29.95#ibcon#read 4, iclass 14, count 0 2006.257.03:51:29.95#ibcon#about to read 5, iclass 14, count 0 2006.257.03:51:29.95#ibcon#read 5, iclass 14, count 0 2006.257.03:51:29.95#ibcon#about to read 6, iclass 14, count 0 2006.257.03:51:29.95#ibcon#read 6, iclass 14, count 0 2006.257.03:51:29.95#ibcon#end of sib2, iclass 14, count 0 2006.257.03:51:29.95#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:51:29.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:51:29.95#ibcon#[25=USB\r\n] 2006.257.03:51:29.95#ibcon#*before write, iclass 14, count 0 2006.257.03:51:29.95#ibcon#enter sib2, iclass 14, count 0 2006.257.03:51:29.95#ibcon#flushed, iclass 14, count 0 2006.257.03:51:29.95#ibcon#about to write, iclass 14, count 0 2006.257.03:51:29.95#ibcon#wrote, iclass 14, count 0 2006.257.03:51:29.95#ibcon#about to read 3, iclass 14, count 0 2006.257.03:51:29.98#ibcon#read 3, iclass 14, count 0 2006.257.03:51:29.98#ibcon#about to read 4, iclass 14, count 0 2006.257.03:51:29.98#ibcon#read 4, iclass 14, count 0 2006.257.03:51:29.98#ibcon#about to read 5, iclass 14, count 0 2006.257.03:51:29.98#ibcon#read 5, iclass 14, count 0 2006.257.03:51:29.98#ibcon#about to read 6, iclass 14, count 0 2006.257.03:51:29.98#ibcon#read 6, iclass 14, count 0 2006.257.03:51:29.98#ibcon#end of sib2, iclass 14, count 0 2006.257.03:51:29.98#ibcon#*after write, iclass 14, count 0 2006.257.03:51:29.98#ibcon#*before return 0, iclass 14, count 0 2006.257.03:51:29.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:29.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:29.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:51:29.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:51:29.98$vck44/valo=6,814.99 2006.257.03:51:29.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.03:51:29.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.03:51:29.98#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:29.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:29.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:29.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:29.98#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:51:29.98#ibcon#first serial, iclass 16, count 0 2006.257.03:51:29.98#ibcon#enter sib2, iclass 16, count 0 2006.257.03:51:29.98#ibcon#flushed, iclass 16, count 0 2006.257.03:51:29.98#ibcon#about to write, iclass 16, count 0 2006.257.03:51:29.98#ibcon#wrote, iclass 16, count 0 2006.257.03:51:29.98#ibcon#about to read 3, iclass 16, count 0 2006.257.03:51:30.00#ibcon#read 3, iclass 16, count 0 2006.257.03:51:30.00#ibcon#about to read 4, iclass 16, count 0 2006.257.03:51:30.00#ibcon#read 4, iclass 16, count 0 2006.257.03:51:30.00#ibcon#about to read 5, iclass 16, count 0 2006.257.03:51:30.00#ibcon#read 5, iclass 16, count 0 2006.257.03:51:30.00#ibcon#about to read 6, iclass 16, count 0 2006.257.03:51:30.00#ibcon#read 6, iclass 16, count 0 2006.257.03:51:30.00#ibcon#end of sib2, iclass 16, count 0 2006.257.03:51:30.00#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:51:30.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:51:30.00#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:51:30.00#ibcon#*before write, iclass 16, count 0 2006.257.03:51:30.00#ibcon#enter sib2, iclass 16, count 0 2006.257.03:51:30.00#ibcon#flushed, iclass 16, count 0 2006.257.03:51:30.00#ibcon#about to write, iclass 16, count 0 2006.257.03:51:30.00#ibcon#wrote, iclass 16, count 0 2006.257.03:51:30.00#ibcon#about to read 3, iclass 16, count 0 2006.257.03:51:30.04#ibcon#read 3, iclass 16, count 0 2006.257.03:51:30.04#ibcon#about to read 4, iclass 16, count 0 2006.257.03:51:30.04#ibcon#read 4, iclass 16, count 0 2006.257.03:51:30.04#ibcon#about to read 5, iclass 16, count 0 2006.257.03:51:30.04#ibcon#read 5, iclass 16, count 0 2006.257.03:51:30.04#ibcon#about to read 6, iclass 16, count 0 2006.257.03:51:30.04#ibcon#read 6, iclass 16, count 0 2006.257.03:51:30.04#ibcon#end of sib2, iclass 16, count 0 2006.257.03:51:30.04#ibcon#*after write, iclass 16, count 0 2006.257.03:51:30.04#ibcon#*before return 0, iclass 16, count 0 2006.257.03:51:30.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:30.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:30.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:51:30.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:51:30.04$vck44/va=6,4 2006.257.03:51:30.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.03:51:30.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.03:51:30.04#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:30.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:30.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:30.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:30.10#ibcon#enter wrdev, iclass 18, count 2 2006.257.03:51:30.10#ibcon#first serial, iclass 18, count 2 2006.257.03:51:30.10#ibcon#enter sib2, iclass 18, count 2 2006.257.03:51:30.10#ibcon#flushed, iclass 18, count 2 2006.257.03:51:30.10#ibcon#about to write, iclass 18, count 2 2006.257.03:51:30.10#ibcon#wrote, iclass 18, count 2 2006.257.03:51:30.10#ibcon#about to read 3, iclass 18, count 2 2006.257.03:51:30.12#ibcon#read 3, iclass 18, count 2 2006.257.03:51:30.12#ibcon#about to read 4, iclass 18, count 2 2006.257.03:51:30.12#ibcon#read 4, iclass 18, count 2 2006.257.03:51:30.12#ibcon#about to read 5, iclass 18, count 2 2006.257.03:51:30.12#ibcon#read 5, iclass 18, count 2 2006.257.03:51:30.12#ibcon#about to read 6, iclass 18, count 2 2006.257.03:51:30.12#ibcon#read 6, iclass 18, count 2 2006.257.03:51:30.12#ibcon#end of sib2, iclass 18, count 2 2006.257.03:51:30.12#ibcon#*mode == 0, iclass 18, count 2 2006.257.03:51:30.12#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.03:51:30.12#ibcon#[25=AT06-04\r\n] 2006.257.03:51:30.12#ibcon#*before write, iclass 18, count 2 2006.257.03:51:30.12#ibcon#enter sib2, iclass 18, count 2 2006.257.03:51:30.12#ibcon#flushed, iclass 18, count 2 2006.257.03:51:30.12#ibcon#about to write, iclass 18, count 2 2006.257.03:51:30.12#ibcon#wrote, iclass 18, count 2 2006.257.03:51:30.12#ibcon#about to read 3, iclass 18, count 2 2006.257.03:51:30.15#ibcon#read 3, iclass 18, count 2 2006.257.03:51:30.15#ibcon#about to read 4, iclass 18, count 2 2006.257.03:51:30.15#ibcon#read 4, iclass 18, count 2 2006.257.03:51:30.15#ibcon#about to read 5, iclass 18, count 2 2006.257.03:51:30.15#ibcon#read 5, iclass 18, count 2 2006.257.03:51:30.15#ibcon#about to read 6, iclass 18, count 2 2006.257.03:51:30.15#ibcon#read 6, iclass 18, count 2 2006.257.03:51:30.15#ibcon#end of sib2, iclass 18, count 2 2006.257.03:51:30.15#ibcon#*after write, iclass 18, count 2 2006.257.03:51:30.15#ibcon#*before return 0, iclass 18, count 2 2006.257.03:51:30.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:30.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:30.15#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.03:51:30.15#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:30.15#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:30.27#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:30.27#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:30.27#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:51:30.27#ibcon#first serial, iclass 18, count 0 2006.257.03:51:30.27#ibcon#enter sib2, iclass 18, count 0 2006.257.03:51:30.27#ibcon#flushed, iclass 18, count 0 2006.257.03:51:30.27#ibcon#about to write, iclass 18, count 0 2006.257.03:51:30.27#ibcon#wrote, iclass 18, count 0 2006.257.03:51:30.27#ibcon#about to read 3, iclass 18, count 0 2006.257.03:51:30.29#ibcon#read 3, iclass 18, count 0 2006.257.03:51:30.29#ibcon#about to read 4, iclass 18, count 0 2006.257.03:51:30.29#ibcon#read 4, iclass 18, count 0 2006.257.03:51:30.29#ibcon#about to read 5, iclass 18, count 0 2006.257.03:51:30.29#ibcon#read 5, iclass 18, count 0 2006.257.03:51:30.29#ibcon#about to read 6, iclass 18, count 0 2006.257.03:51:30.29#ibcon#read 6, iclass 18, count 0 2006.257.03:51:30.29#ibcon#end of sib2, iclass 18, count 0 2006.257.03:51:30.29#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:51:30.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:51:30.29#ibcon#[25=USB\r\n] 2006.257.03:51:30.29#ibcon#*before write, iclass 18, count 0 2006.257.03:51:30.29#ibcon#enter sib2, iclass 18, count 0 2006.257.03:51:30.29#ibcon#flushed, iclass 18, count 0 2006.257.03:51:30.29#ibcon#about to write, iclass 18, count 0 2006.257.03:51:30.29#ibcon#wrote, iclass 18, count 0 2006.257.03:51:30.29#ibcon#about to read 3, iclass 18, count 0 2006.257.03:51:30.32#ibcon#read 3, iclass 18, count 0 2006.257.03:51:30.32#ibcon#about to read 4, iclass 18, count 0 2006.257.03:51:30.32#ibcon#read 4, iclass 18, count 0 2006.257.03:51:30.32#ibcon#about to read 5, iclass 18, count 0 2006.257.03:51:30.32#ibcon#read 5, iclass 18, count 0 2006.257.03:51:30.32#ibcon#about to read 6, iclass 18, count 0 2006.257.03:51:30.32#ibcon#read 6, iclass 18, count 0 2006.257.03:51:30.32#ibcon#end of sib2, iclass 18, count 0 2006.257.03:51:30.32#ibcon#*after write, iclass 18, count 0 2006.257.03:51:30.32#ibcon#*before return 0, iclass 18, count 0 2006.257.03:51:30.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:30.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:30.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:51:30.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:51:30.32$vck44/valo=7,864.99 2006.257.03:51:30.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.03:51:30.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.03:51:30.32#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:30.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:30.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:30.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:30.32#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:51:30.32#ibcon#first serial, iclass 20, count 0 2006.257.03:51:30.32#ibcon#enter sib2, iclass 20, count 0 2006.257.03:51:30.32#ibcon#flushed, iclass 20, count 0 2006.257.03:51:30.32#ibcon#about to write, iclass 20, count 0 2006.257.03:51:30.32#ibcon#wrote, iclass 20, count 0 2006.257.03:51:30.32#ibcon#about to read 3, iclass 20, count 0 2006.257.03:51:30.34#ibcon#read 3, iclass 20, count 0 2006.257.03:51:30.34#ibcon#about to read 4, iclass 20, count 0 2006.257.03:51:30.34#ibcon#read 4, iclass 20, count 0 2006.257.03:51:30.34#ibcon#about to read 5, iclass 20, count 0 2006.257.03:51:30.34#ibcon#read 5, iclass 20, count 0 2006.257.03:51:30.34#ibcon#about to read 6, iclass 20, count 0 2006.257.03:51:30.34#ibcon#read 6, iclass 20, count 0 2006.257.03:51:30.34#ibcon#end of sib2, iclass 20, count 0 2006.257.03:51:30.34#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:51:30.34#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:51:30.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:51:30.34#ibcon#*before write, iclass 20, count 0 2006.257.03:51:30.34#ibcon#enter sib2, iclass 20, count 0 2006.257.03:51:30.34#ibcon#flushed, iclass 20, count 0 2006.257.03:51:30.34#ibcon#about to write, iclass 20, count 0 2006.257.03:51:30.34#ibcon#wrote, iclass 20, count 0 2006.257.03:51:30.34#ibcon#about to read 3, iclass 20, count 0 2006.257.03:51:30.38#ibcon#read 3, iclass 20, count 0 2006.257.03:51:30.38#ibcon#about to read 4, iclass 20, count 0 2006.257.03:51:30.38#ibcon#read 4, iclass 20, count 0 2006.257.03:51:30.38#ibcon#about to read 5, iclass 20, count 0 2006.257.03:51:30.38#ibcon#read 5, iclass 20, count 0 2006.257.03:51:30.38#ibcon#about to read 6, iclass 20, count 0 2006.257.03:51:30.38#ibcon#read 6, iclass 20, count 0 2006.257.03:51:30.38#ibcon#end of sib2, iclass 20, count 0 2006.257.03:51:30.38#ibcon#*after write, iclass 20, count 0 2006.257.03:51:30.38#ibcon#*before return 0, iclass 20, count 0 2006.257.03:51:30.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:30.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:30.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:51:30.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:51:30.38$vck44/va=7,4 2006.257.03:51:30.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.03:51:30.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.03:51:30.38#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:30.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:30.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:30.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:30.44#ibcon#enter wrdev, iclass 22, count 2 2006.257.03:51:30.44#ibcon#first serial, iclass 22, count 2 2006.257.03:51:30.44#ibcon#enter sib2, iclass 22, count 2 2006.257.03:51:30.44#ibcon#flushed, iclass 22, count 2 2006.257.03:51:30.44#ibcon#about to write, iclass 22, count 2 2006.257.03:51:30.44#ibcon#wrote, iclass 22, count 2 2006.257.03:51:30.44#ibcon#about to read 3, iclass 22, count 2 2006.257.03:51:30.46#ibcon#read 3, iclass 22, count 2 2006.257.03:51:30.46#ibcon#about to read 4, iclass 22, count 2 2006.257.03:51:30.46#ibcon#read 4, iclass 22, count 2 2006.257.03:51:30.46#ibcon#about to read 5, iclass 22, count 2 2006.257.03:51:30.46#ibcon#read 5, iclass 22, count 2 2006.257.03:51:30.46#ibcon#about to read 6, iclass 22, count 2 2006.257.03:51:30.46#ibcon#read 6, iclass 22, count 2 2006.257.03:51:30.46#ibcon#end of sib2, iclass 22, count 2 2006.257.03:51:30.46#ibcon#*mode == 0, iclass 22, count 2 2006.257.03:51:30.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.03:51:30.46#ibcon#[25=AT07-04\r\n] 2006.257.03:51:30.46#ibcon#*before write, iclass 22, count 2 2006.257.03:51:30.46#ibcon#enter sib2, iclass 22, count 2 2006.257.03:51:30.46#ibcon#flushed, iclass 22, count 2 2006.257.03:51:30.46#ibcon#about to write, iclass 22, count 2 2006.257.03:51:30.46#ibcon#wrote, iclass 22, count 2 2006.257.03:51:30.46#ibcon#about to read 3, iclass 22, count 2 2006.257.03:51:30.49#ibcon#read 3, iclass 22, count 2 2006.257.03:51:30.49#ibcon#about to read 4, iclass 22, count 2 2006.257.03:51:30.49#ibcon#read 4, iclass 22, count 2 2006.257.03:51:30.49#ibcon#about to read 5, iclass 22, count 2 2006.257.03:51:30.49#ibcon#read 5, iclass 22, count 2 2006.257.03:51:30.49#ibcon#about to read 6, iclass 22, count 2 2006.257.03:51:30.49#ibcon#read 6, iclass 22, count 2 2006.257.03:51:30.49#ibcon#end of sib2, iclass 22, count 2 2006.257.03:51:30.49#ibcon#*after write, iclass 22, count 2 2006.257.03:51:30.49#ibcon#*before return 0, iclass 22, count 2 2006.257.03:51:30.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:30.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:30.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.03:51:30.49#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:30.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:30.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:30.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:30.61#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:51:30.61#ibcon#first serial, iclass 22, count 0 2006.257.03:51:30.61#ibcon#enter sib2, iclass 22, count 0 2006.257.03:51:30.61#ibcon#flushed, iclass 22, count 0 2006.257.03:51:30.61#ibcon#about to write, iclass 22, count 0 2006.257.03:51:30.61#ibcon#wrote, iclass 22, count 0 2006.257.03:51:30.61#ibcon#about to read 3, iclass 22, count 0 2006.257.03:51:30.63#ibcon#read 3, iclass 22, count 0 2006.257.03:51:30.63#ibcon#about to read 4, iclass 22, count 0 2006.257.03:51:30.63#ibcon#read 4, iclass 22, count 0 2006.257.03:51:30.63#ibcon#about to read 5, iclass 22, count 0 2006.257.03:51:30.63#ibcon#read 5, iclass 22, count 0 2006.257.03:51:30.63#ibcon#about to read 6, iclass 22, count 0 2006.257.03:51:30.63#ibcon#read 6, iclass 22, count 0 2006.257.03:51:30.63#ibcon#end of sib2, iclass 22, count 0 2006.257.03:51:30.63#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:51:30.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:51:30.63#ibcon#[25=USB\r\n] 2006.257.03:51:30.63#ibcon#*before write, iclass 22, count 0 2006.257.03:51:30.63#ibcon#enter sib2, iclass 22, count 0 2006.257.03:51:30.63#ibcon#flushed, iclass 22, count 0 2006.257.03:51:30.63#ibcon#about to write, iclass 22, count 0 2006.257.03:51:30.63#ibcon#wrote, iclass 22, count 0 2006.257.03:51:30.63#ibcon#about to read 3, iclass 22, count 0 2006.257.03:51:30.66#ibcon#read 3, iclass 22, count 0 2006.257.03:51:30.66#ibcon#about to read 4, iclass 22, count 0 2006.257.03:51:30.66#ibcon#read 4, iclass 22, count 0 2006.257.03:51:30.66#ibcon#about to read 5, iclass 22, count 0 2006.257.03:51:30.66#ibcon#read 5, iclass 22, count 0 2006.257.03:51:30.66#ibcon#about to read 6, iclass 22, count 0 2006.257.03:51:30.66#ibcon#read 6, iclass 22, count 0 2006.257.03:51:30.66#ibcon#end of sib2, iclass 22, count 0 2006.257.03:51:30.66#ibcon#*after write, iclass 22, count 0 2006.257.03:51:30.66#ibcon#*before return 0, iclass 22, count 0 2006.257.03:51:30.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:30.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:30.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:51:30.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:51:30.66$vck44/valo=8,884.99 2006.257.03:51:30.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.03:51:30.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.03:51:30.66#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:30.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:30.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:30.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:30.66#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:51:30.66#ibcon#first serial, iclass 24, count 0 2006.257.03:51:30.66#ibcon#enter sib2, iclass 24, count 0 2006.257.03:51:30.66#ibcon#flushed, iclass 24, count 0 2006.257.03:51:30.66#ibcon#about to write, iclass 24, count 0 2006.257.03:51:30.66#ibcon#wrote, iclass 24, count 0 2006.257.03:51:30.66#ibcon#about to read 3, iclass 24, count 0 2006.257.03:51:30.68#ibcon#read 3, iclass 24, count 0 2006.257.03:51:30.68#ibcon#about to read 4, iclass 24, count 0 2006.257.03:51:30.68#ibcon#read 4, iclass 24, count 0 2006.257.03:51:30.68#ibcon#about to read 5, iclass 24, count 0 2006.257.03:51:30.68#ibcon#read 5, iclass 24, count 0 2006.257.03:51:30.68#ibcon#about to read 6, iclass 24, count 0 2006.257.03:51:30.68#ibcon#read 6, iclass 24, count 0 2006.257.03:51:30.68#ibcon#end of sib2, iclass 24, count 0 2006.257.03:51:30.68#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:51:30.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:51:30.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:51:30.68#ibcon#*before write, iclass 24, count 0 2006.257.03:51:30.68#ibcon#enter sib2, iclass 24, count 0 2006.257.03:51:30.68#ibcon#flushed, iclass 24, count 0 2006.257.03:51:30.68#ibcon#about to write, iclass 24, count 0 2006.257.03:51:30.68#ibcon#wrote, iclass 24, count 0 2006.257.03:51:30.68#ibcon#about to read 3, iclass 24, count 0 2006.257.03:51:30.72#ibcon#read 3, iclass 24, count 0 2006.257.03:51:30.72#ibcon#about to read 4, iclass 24, count 0 2006.257.03:51:30.72#ibcon#read 4, iclass 24, count 0 2006.257.03:51:30.72#ibcon#about to read 5, iclass 24, count 0 2006.257.03:51:30.72#ibcon#read 5, iclass 24, count 0 2006.257.03:51:30.72#ibcon#about to read 6, iclass 24, count 0 2006.257.03:51:30.72#ibcon#read 6, iclass 24, count 0 2006.257.03:51:30.72#ibcon#end of sib2, iclass 24, count 0 2006.257.03:51:30.72#ibcon#*after write, iclass 24, count 0 2006.257.03:51:30.72#ibcon#*before return 0, iclass 24, count 0 2006.257.03:51:30.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:30.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:30.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:51:30.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:51:30.72$vck44/va=8,4 2006.257.03:51:30.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.03:51:30.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.03:51:30.72#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:30.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:51:30.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:51:30.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:51:30.78#ibcon#enter wrdev, iclass 26, count 2 2006.257.03:51:30.78#ibcon#first serial, iclass 26, count 2 2006.257.03:51:30.78#ibcon#enter sib2, iclass 26, count 2 2006.257.03:51:30.78#ibcon#flushed, iclass 26, count 2 2006.257.03:51:30.78#ibcon#about to write, iclass 26, count 2 2006.257.03:51:30.78#ibcon#wrote, iclass 26, count 2 2006.257.03:51:30.78#ibcon#about to read 3, iclass 26, count 2 2006.257.03:51:30.80#ibcon#read 3, iclass 26, count 2 2006.257.03:51:30.80#ibcon#about to read 4, iclass 26, count 2 2006.257.03:51:30.80#ibcon#read 4, iclass 26, count 2 2006.257.03:51:30.80#ibcon#about to read 5, iclass 26, count 2 2006.257.03:51:30.80#ibcon#read 5, iclass 26, count 2 2006.257.03:51:30.80#ibcon#about to read 6, iclass 26, count 2 2006.257.03:51:30.80#ibcon#read 6, iclass 26, count 2 2006.257.03:51:30.80#ibcon#end of sib2, iclass 26, count 2 2006.257.03:51:30.80#ibcon#*mode == 0, iclass 26, count 2 2006.257.03:51:30.80#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.03:51:30.80#ibcon#[25=AT08-04\r\n] 2006.257.03:51:30.80#ibcon#*before write, iclass 26, count 2 2006.257.03:51:30.80#ibcon#enter sib2, iclass 26, count 2 2006.257.03:51:30.80#ibcon#flushed, iclass 26, count 2 2006.257.03:51:30.80#ibcon#about to write, iclass 26, count 2 2006.257.03:51:30.80#ibcon#wrote, iclass 26, count 2 2006.257.03:51:30.80#ibcon#about to read 3, iclass 26, count 2 2006.257.03:51:30.83#ibcon#read 3, iclass 26, count 2 2006.257.03:51:30.83#ibcon#about to read 4, iclass 26, count 2 2006.257.03:51:30.83#ibcon#read 4, iclass 26, count 2 2006.257.03:51:30.83#ibcon#about to read 5, iclass 26, count 2 2006.257.03:51:30.83#ibcon#read 5, iclass 26, count 2 2006.257.03:51:30.83#ibcon#about to read 6, iclass 26, count 2 2006.257.03:51:30.83#ibcon#read 6, iclass 26, count 2 2006.257.03:51:30.83#ibcon#end of sib2, iclass 26, count 2 2006.257.03:51:30.83#ibcon#*after write, iclass 26, count 2 2006.257.03:51:30.83#ibcon#*before return 0, iclass 26, count 2 2006.257.03:51:30.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:51:30.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.03:51:30.83#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.03:51:30.83#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:30.83#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:51:30.95#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:51:30.95#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:51:30.95#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:51:30.95#ibcon#first serial, iclass 26, count 0 2006.257.03:51:30.95#ibcon#enter sib2, iclass 26, count 0 2006.257.03:51:30.95#ibcon#flushed, iclass 26, count 0 2006.257.03:51:30.95#ibcon#about to write, iclass 26, count 0 2006.257.03:51:30.95#ibcon#wrote, iclass 26, count 0 2006.257.03:51:30.95#ibcon#about to read 3, iclass 26, count 0 2006.257.03:51:30.97#ibcon#read 3, iclass 26, count 0 2006.257.03:51:30.97#ibcon#about to read 4, iclass 26, count 0 2006.257.03:51:30.97#ibcon#read 4, iclass 26, count 0 2006.257.03:51:30.97#ibcon#about to read 5, iclass 26, count 0 2006.257.03:51:30.97#ibcon#read 5, iclass 26, count 0 2006.257.03:51:30.97#ibcon#about to read 6, iclass 26, count 0 2006.257.03:51:30.97#ibcon#read 6, iclass 26, count 0 2006.257.03:51:30.97#ibcon#end of sib2, iclass 26, count 0 2006.257.03:51:30.97#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:51:30.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:51:30.97#ibcon#[25=USB\r\n] 2006.257.03:51:30.97#ibcon#*before write, iclass 26, count 0 2006.257.03:51:30.97#ibcon#enter sib2, iclass 26, count 0 2006.257.03:51:30.97#ibcon#flushed, iclass 26, count 0 2006.257.03:51:30.97#ibcon#about to write, iclass 26, count 0 2006.257.03:51:30.97#ibcon#wrote, iclass 26, count 0 2006.257.03:51:30.97#ibcon#about to read 3, iclass 26, count 0 2006.257.03:51:31.00#ibcon#read 3, iclass 26, count 0 2006.257.03:51:31.00#ibcon#about to read 4, iclass 26, count 0 2006.257.03:51:31.00#ibcon#read 4, iclass 26, count 0 2006.257.03:51:31.00#ibcon#about to read 5, iclass 26, count 0 2006.257.03:51:31.00#ibcon#read 5, iclass 26, count 0 2006.257.03:51:31.00#ibcon#about to read 6, iclass 26, count 0 2006.257.03:51:31.00#ibcon#read 6, iclass 26, count 0 2006.257.03:51:31.00#ibcon#end of sib2, iclass 26, count 0 2006.257.03:51:31.00#ibcon#*after write, iclass 26, count 0 2006.257.03:51:31.00#ibcon#*before return 0, iclass 26, count 0 2006.257.03:51:31.00#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:51:31.00#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.03:51:31.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:51:31.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:51:31.00$vck44/vblo=1,629.99 2006.257.03:51:31.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.03:51:31.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.03:51:31.00#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:31.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:51:31.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:51:31.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:51:31.00#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:51:31.00#ibcon#first serial, iclass 28, count 0 2006.257.03:51:31.00#ibcon#enter sib2, iclass 28, count 0 2006.257.03:51:31.00#ibcon#flushed, iclass 28, count 0 2006.257.03:51:31.00#ibcon#about to write, iclass 28, count 0 2006.257.03:51:31.00#ibcon#wrote, iclass 28, count 0 2006.257.03:51:31.00#ibcon#about to read 3, iclass 28, count 0 2006.257.03:51:31.02#ibcon#read 3, iclass 28, count 0 2006.257.03:51:31.02#ibcon#about to read 4, iclass 28, count 0 2006.257.03:51:31.02#ibcon#read 4, iclass 28, count 0 2006.257.03:51:31.02#ibcon#about to read 5, iclass 28, count 0 2006.257.03:51:31.02#ibcon#read 5, iclass 28, count 0 2006.257.03:51:31.02#ibcon#about to read 6, iclass 28, count 0 2006.257.03:51:31.02#ibcon#read 6, iclass 28, count 0 2006.257.03:51:31.02#ibcon#end of sib2, iclass 28, count 0 2006.257.03:51:31.02#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:51:31.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:51:31.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:51:31.02#ibcon#*before write, iclass 28, count 0 2006.257.03:51:31.02#ibcon#enter sib2, iclass 28, count 0 2006.257.03:51:31.02#ibcon#flushed, iclass 28, count 0 2006.257.03:51:31.02#ibcon#about to write, iclass 28, count 0 2006.257.03:51:31.02#ibcon#wrote, iclass 28, count 0 2006.257.03:51:31.02#ibcon#about to read 3, iclass 28, count 0 2006.257.03:51:31.06#ibcon#read 3, iclass 28, count 0 2006.257.03:51:31.06#ibcon#about to read 4, iclass 28, count 0 2006.257.03:51:31.06#ibcon#read 4, iclass 28, count 0 2006.257.03:51:31.06#ibcon#about to read 5, iclass 28, count 0 2006.257.03:51:31.06#ibcon#read 5, iclass 28, count 0 2006.257.03:51:31.06#ibcon#about to read 6, iclass 28, count 0 2006.257.03:51:31.06#ibcon#read 6, iclass 28, count 0 2006.257.03:51:31.06#ibcon#end of sib2, iclass 28, count 0 2006.257.03:51:31.06#ibcon#*after write, iclass 28, count 0 2006.257.03:51:31.06#ibcon#*before return 0, iclass 28, count 0 2006.257.03:51:31.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:51:31.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:51:31.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:51:31.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:51:31.06$vck44/vb=1,4 2006.257.03:51:31.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.03:51:31.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.03:51:31.06#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:31.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:51:31.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:51:31.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:51:31.06#ibcon#enter wrdev, iclass 30, count 2 2006.257.03:51:31.06#ibcon#first serial, iclass 30, count 2 2006.257.03:51:31.06#ibcon#enter sib2, iclass 30, count 2 2006.257.03:51:31.06#ibcon#flushed, iclass 30, count 2 2006.257.03:51:31.06#ibcon#about to write, iclass 30, count 2 2006.257.03:51:31.06#ibcon#wrote, iclass 30, count 2 2006.257.03:51:31.06#ibcon#about to read 3, iclass 30, count 2 2006.257.03:51:31.08#ibcon#read 3, iclass 30, count 2 2006.257.03:51:31.08#ibcon#about to read 4, iclass 30, count 2 2006.257.03:51:31.08#ibcon#read 4, iclass 30, count 2 2006.257.03:51:31.08#ibcon#about to read 5, iclass 30, count 2 2006.257.03:51:31.08#ibcon#read 5, iclass 30, count 2 2006.257.03:51:31.08#ibcon#about to read 6, iclass 30, count 2 2006.257.03:51:31.08#ibcon#read 6, iclass 30, count 2 2006.257.03:51:31.08#ibcon#end of sib2, iclass 30, count 2 2006.257.03:51:31.08#ibcon#*mode == 0, iclass 30, count 2 2006.257.03:51:31.08#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.03:51:31.08#ibcon#[27=AT01-04\r\n] 2006.257.03:51:31.08#ibcon#*before write, iclass 30, count 2 2006.257.03:51:31.08#ibcon#enter sib2, iclass 30, count 2 2006.257.03:51:31.08#ibcon#flushed, iclass 30, count 2 2006.257.03:51:31.08#ibcon#about to write, iclass 30, count 2 2006.257.03:51:31.08#ibcon#wrote, iclass 30, count 2 2006.257.03:51:31.08#ibcon#about to read 3, iclass 30, count 2 2006.257.03:51:31.11#ibcon#read 3, iclass 30, count 2 2006.257.03:51:31.11#ibcon#about to read 4, iclass 30, count 2 2006.257.03:51:31.11#ibcon#read 4, iclass 30, count 2 2006.257.03:51:31.11#ibcon#about to read 5, iclass 30, count 2 2006.257.03:51:31.11#ibcon#read 5, iclass 30, count 2 2006.257.03:51:31.11#ibcon#about to read 6, iclass 30, count 2 2006.257.03:51:31.11#ibcon#read 6, iclass 30, count 2 2006.257.03:51:31.11#ibcon#end of sib2, iclass 30, count 2 2006.257.03:51:31.11#ibcon#*after write, iclass 30, count 2 2006.257.03:51:31.11#ibcon#*before return 0, iclass 30, count 2 2006.257.03:51:31.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:51:31.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.03:51:31.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.03:51:31.11#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:31.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:51:31.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:51:31.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:51:31.23#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:51:31.23#ibcon#first serial, iclass 30, count 0 2006.257.03:51:31.23#ibcon#enter sib2, iclass 30, count 0 2006.257.03:51:31.23#ibcon#flushed, iclass 30, count 0 2006.257.03:51:31.23#ibcon#about to write, iclass 30, count 0 2006.257.03:51:31.23#ibcon#wrote, iclass 30, count 0 2006.257.03:51:31.23#ibcon#about to read 3, iclass 30, count 0 2006.257.03:51:31.25#ibcon#read 3, iclass 30, count 0 2006.257.03:51:31.25#ibcon#about to read 4, iclass 30, count 0 2006.257.03:51:31.25#ibcon#read 4, iclass 30, count 0 2006.257.03:51:31.25#ibcon#about to read 5, iclass 30, count 0 2006.257.03:51:31.25#ibcon#read 5, iclass 30, count 0 2006.257.03:51:31.25#ibcon#about to read 6, iclass 30, count 0 2006.257.03:51:31.25#ibcon#read 6, iclass 30, count 0 2006.257.03:51:31.25#ibcon#end of sib2, iclass 30, count 0 2006.257.03:51:31.25#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:51:31.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:51:31.25#ibcon#[27=USB\r\n] 2006.257.03:51:31.25#ibcon#*before write, iclass 30, count 0 2006.257.03:51:31.25#ibcon#enter sib2, iclass 30, count 0 2006.257.03:51:31.25#ibcon#flushed, iclass 30, count 0 2006.257.03:51:31.25#ibcon#about to write, iclass 30, count 0 2006.257.03:51:31.25#ibcon#wrote, iclass 30, count 0 2006.257.03:51:31.25#ibcon#about to read 3, iclass 30, count 0 2006.257.03:51:31.28#ibcon#read 3, iclass 30, count 0 2006.257.03:51:31.28#ibcon#about to read 4, iclass 30, count 0 2006.257.03:51:31.28#ibcon#read 4, iclass 30, count 0 2006.257.03:51:31.28#ibcon#about to read 5, iclass 30, count 0 2006.257.03:51:31.28#ibcon#read 5, iclass 30, count 0 2006.257.03:51:31.28#ibcon#about to read 6, iclass 30, count 0 2006.257.03:51:31.28#ibcon#read 6, iclass 30, count 0 2006.257.03:51:31.28#ibcon#end of sib2, iclass 30, count 0 2006.257.03:51:31.28#ibcon#*after write, iclass 30, count 0 2006.257.03:51:31.28#ibcon#*before return 0, iclass 30, count 0 2006.257.03:51:31.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:51:31.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.03:51:31.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:51:31.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:51:31.28$vck44/vblo=2,634.99 2006.257.03:51:31.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.03:51:31.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.03:51:31.28#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:31.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:31.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:31.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:31.28#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:51:31.28#ibcon#first serial, iclass 32, count 0 2006.257.03:51:31.28#ibcon#enter sib2, iclass 32, count 0 2006.257.03:51:31.28#ibcon#flushed, iclass 32, count 0 2006.257.03:51:31.28#ibcon#about to write, iclass 32, count 0 2006.257.03:51:31.28#ibcon#wrote, iclass 32, count 0 2006.257.03:51:31.28#ibcon#about to read 3, iclass 32, count 0 2006.257.03:51:31.30#ibcon#read 3, iclass 32, count 0 2006.257.03:51:31.30#ibcon#about to read 4, iclass 32, count 0 2006.257.03:51:31.30#ibcon#read 4, iclass 32, count 0 2006.257.03:51:31.30#ibcon#about to read 5, iclass 32, count 0 2006.257.03:51:31.30#ibcon#read 5, iclass 32, count 0 2006.257.03:51:31.30#ibcon#about to read 6, iclass 32, count 0 2006.257.03:51:31.30#ibcon#read 6, iclass 32, count 0 2006.257.03:51:31.30#ibcon#end of sib2, iclass 32, count 0 2006.257.03:51:31.30#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:51:31.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:51:31.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:51:31.30#ibcon#*before write, iclass 32, count 0 2006.257.03:51:31.30#ibcon#enter sib2, iclass 32, count 0 2006.257.03:51:31.30#ibcon#flushed, iclass 32, count 0 2006.257.03:51:31.30#ibcon#about to write, iclass 32, count 0 2006.257.03:51:31.30#ibcon#wrote, iclass 32, count 0 2006.257.03:51:31.30#ibcon#about to read 3, iclass 32, count 0 2006.257.03:51:31.34#ibcon#read 3, iclass 32, count 0 2006.257.03:51:31.34#ibcon#about to read 4, iclass 32, count 0 2006.257.03:51:31.34#ibcon#read 4, iclass 32, count 0 2006.257.03:51:31.34#ibcon#about to read 5, iclass 32, count 0 2006.257.03:51:31.34#ibcon#read 5, iclass 32, count 0 2006.257.03:51:31.34#ibcon#about to read 6, iclass 32, count 0 2006.257.03:51:31.34#ibcon#read 6, iclass 32, count 0 2006.257.03:51:31.34#ibcon#end of sib2, iclass 32, count 0 2006.257.03:51:31.34#ibcon#*after write, iclass 32, count 0 2006.257.03:51:31.34#ibcon#*before return 0, iclass 32, count 0 2006.257.03:51:31.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:31.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.03:51:31.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:51:31.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:51:31.34$vck44/vb=2,5 2006.257.03:51:31.34#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.03:51:31.34#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.03:51:31.34#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:31.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:31.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:31.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:31.40#ibcon#enter wrdev, iclass 34, count 2 2006.257.03:51:31.40#ibcon#first serial, iclass 34, count 2 2006.257.03:51:31.40#ibcon#enter sib2, iclass 34, count 2 2006.257.03:51:31.40#ibcon#flushed, iclass 34, count 2 2006.257.03:51:31.40#ibcon#about to write, iclass 34, count 2 2006.257.03:51:31.40#ibcon#wrote, iclass 34, count 2 2006.257.03:51:31.40#ibcon#about to read 3, iclass 34, count 2 2006.257.03:51:31.42#ibcon#read 3, iclass 34, count 2 2006.257.03:51:31.42#ibcon#about to read 4, iclass 34, count 2 2006.257.03:51:31.42#ibcon#read 4, iclass 34, count 2 2006.257.03:51:31.42#ibcon#about to read 5, iclass 34, count 2 2006.257.03:51:31.42#ibcon#read 5, iclass 34, count 2 2006.257.03:51:31.42#ibcon#about to read 6, iclass 34, count 2 2006.257.03:51:31.42#ibcon#read 6, iclass 34, count 2 2006.257.03:51:31.42#ibcon#end of sib2, iclass 34, count 2 2006.257.03:51:31.42#ibcon#*mode == 0, iclass 34, count 2 2006.257.03:51:31.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.03:51:31.42#ibcon#[27=AT02-05\r\n] 2006.257.03:51:31.42#ibcon#*before write, iclass 34, count 2 2006.257.03:51:31.42#ibcon#enter sib2, iclass 34, count 2 2006.257.03:51:31.42#ibcon#flushed, iclass 34, count 2 2006.257.03:51:31.42#ibcon#about to write, iclass 34, count 2 2006.257.03:51:31.42#ibcon#wrote, iclass 34, count 2 2006.257.03:51:31.42#ibcon#about to read 3, iclass 34, count 2 2006.257.03:51:31.45#ibcon#read 3, iclass 34, count 2 2006.257.03:51:31.45#ibcon#about to read 4, iclass 34, count 2 2006.257.03:51:31.45#ibcon#read 4, iclass 34, count 2 2006.257.03:51:31.45#ibcon#about to read 5, iclass 34, count 2 2006.257.03:51:31.45#ibcon#read 5, iclass 34, count 2 2006.257.03:51:31.45#ibcon#about to read 6, iclass 34, count 2 2006.257.03:51:31.45#ibcon#read 6, iclass 34, count 2 2006.257.03:51:31.45#ibcon#end of sib2, iclass 34, count 2 2006.257.03:51:31.45#ibcon#*after write, iclass 34, count 2 2006.257.03:51:31.45#ibcon#*before return 0, iclass 34, count 2 2006.257.03:51:31.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:31.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.03:51:31.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.03:51:31.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:31.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:31.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:31.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:31.57#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:51:31.57#ibcon#first serial, iclass 34, count 0 2006.257.03:51:31.57#ibcon#enter sib2, iclass 34, count 0 2006.257.03:51:31.57#ibcon#flushed, iclass 34, count 0 2006.257.03:51:31.57#ibcon#about to write, iclass 34, count 0 2006.257.03:51:31.57#ibcon#wrote, iclass 34, count 0 2006.257.03:51:31.57#ibcon#about to read 3, iclass 34, count 0 2006.257.03:51:31.59#ibcon#read 3, iclass 34, count 0 2006.257.03:51:31.59#ibcon#about to read 4, iclass 34, count 0 2006.257.03:51:31.59#ibcon#read 4, iclass 34, count 0 2006.257.03:51:31.59#ibcon#about to read 5, iclass 34, count 0 2006.257.03:51:31.59#ibcon#read 5, iclass 34, count 0 2006.257.03:51:31.59#ibcon#about to read 6, iclass 34, count 0 2006.257.03:51:31.59#ibcon#read 6, iclass 34, count 0 2006.257.03:51:31.59#ibcon#end of sib2, iclass 34, count 0 2006.257.03:51:31.59#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:51:31.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:51:31.59#ibcon#[27=USB\r\n] 2006.257.03:51:31.59#ibcon#*before write, iclass 34, count 0 2006.257.03:51:31.59#ibcon#enter sib2, iclass 34, count 0 2006.257.03:51:31.59#ibcon#flushed, iclass 34, count 0 2006.257.03:51:31.59#ibcon#about to write, iclass 34, count 0 2006.257.03:51:31.59#ibcon#wrote, iclass 34, count 0 2006.257.03:51:31.59#ibcon#about to read 3, iclass 34, count 0 2006.257.03:51:31.62#ibcon#read 3, iclass 34, count 0 2006.257.03:51:31.62#ibcon#about to read 4, iclass 34, count 0 2006.257.03:51:31.62#ibcon#read 4, iclass 34, count 0 2006.257.03:51:31.62#ibcon#about to read 5, iclass 34, count 0 2006.257.03:51:31.62#ibcon#read 5, iclass 34, count 0 2006.257.03:51:31.62#ibcon#about to read 6, iclass 34, count 0 2006.257.03:51:31.62#ibcon#read 6, iclass 34, count 0 2006.257.03:51:31.62#ibcon#end of sib2, iclass 34, count 0 2006.257.03:51:31.62#ibcon#*after write, iclass 34, count 0 2006.257.03:51:31.62#ibcon#*before return 0, iclass 34, count 0 2006.257.03:51:31.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:31.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.03:51:31.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:51:31.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:51:31.62$vck44/vblo=3,649.99 2006.257.03:51:31.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.03:51:31.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.03:51:31.62#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:31.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:31.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:31.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:31.62#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:51:31.62#ibcon#first serial, iclass 36, count 0 2006.257.03:51:31.62#ibcon#enter sib2, iclass 36, count 0 2006.257.03:51:31.62#ibcon#flushed, iclass 36, count 0 2006.257.03:51:31.62#ibcon#about to write, iclass 36, count 0 2006.257.03:51:31.62#ibcon#wrote, iclass 36, count 0 2006.257.03:51:31.62#ibcon#about to read 3, iclass 36, count 0 2006.257.03:51:31.64#ibcon#read 3, iclass 36, count 0 2006.257.03:51:31.64#ibcon#about to read 4, iclass 36, count 0 2006.257.03:51:31.64#ibcon#read 4, iclass 36, count 0 2006.257.03:51:31.64#ibcon#about to read 5, iclass 36, count 0 2006.257.03:51:31.64#ibcon#read 5, iclass 36, count 0 2006.257.03:51:31.64#ibcon#about to read 6, iclass 36, count 0 2006.257.03:51:31.64#ibcon#read 6, iclass 36, count 0 2006.257.03:51:31.64#ibcon#end of sib2, iclass 36, count 0 2006.257.03:51:31.64#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:51:31.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:51:31.64#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:51:31.64#ibcon#*before write, iclass 36, count 0 2006.257.03:51:31.64#ibcon#enter sib2, iclass 36, count 0 2006.257.03:51:31.64#ibcon#flushed, iclass 36, count 0 2006.257.03:51:31.64#ibcon#about to write, iclass 36, count 0 2006.257.03:51:31.64#ibcon#wrote, iclass 36, count 0 2006.257.03:51:31.64#ibcon#about to read 3, iclass 36, count 0 2006.257.03:51:31.68#ibcon#read 3, iclass 36, count 0 2006.257.03:51:31.68#ibcon#about to read 4, iclass 36, count 0 2006.257.03:51:31.68#ibcon#read 4, iclass 36, count 0 2006.257.03:51:31.68#ibcon#about to read 5, iclass 36, count 0 2006.257.03:51:31.68#ibcon#read 5, iclass 36, count 0 2006.257.03:51:31.68#ibcon#about to read 6, iclass 36, count 0 2006.257.03:51:31.68#ibcon#read 6, iclass 36, count 0 2006.257.03:51:31.68#ibcon#end of sib2, iclass 36, count 0 2006.257.03:51:31.68#ibcon#*after write, iclass 36, count 0 2006.257.03:51:31.68#ibcon#*before return 0, iclass 36, count 0 2006.257.03:51:31.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:31.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.03:51:31.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:51:31.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:51:31.68$vck44/vb=3,4 2006.257.03:51:31.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.03:51:31.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.03:51:31.68#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:31.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:31.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:31.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:31.74#ibcon#enter wrdev, iclass 38, count 2 2006.257.03:51:31.74#ibcon#first serial, iclass 38, count 2 2006.257.03:51:31.74#ibcon#enter sib2, iclass 38, count 2 2006.257.03:51:31.74#ibcon#flushed, iclass 38, count 2 2006.257.03:51:31.74#ibcon#about to write, iclass 38, count 2 2006.257.03:51:31.74#ibcon#wrote, iclass 38, count 2 2006.257.03:51:31.74#ibcon#about to read 3, iclass 38, count 2 2006.257.03:51:31.76#ibcon#read 3, iclass 38, count 2 2006.257.03:51:31.76#ibcon#about to read 4, iclass 38, count 2 2006.257.03:51:31.76#ibcon#read 4, iclass 38, count 2 2006.257.03:51:31.76#ibcon#about to read 5, iclass 38, count 2 2006.257.03:51:31.76#ibcon#read 5, iclass 38, count 2 2006.257.03:51:31.76#ibcon#about to read 6, iclass 38, count 2 2006.257.03:51:31.76#ibcon#read 6, iclass 38, count 2 2006.257.03:51:31.76#ibcon#end of sib2, iclass 38, count 2 2006.257.03:51:31.76#ibcon#*mode == 0, iclass 38, count 2 2006.257.03:51:31.76#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.03:51:31.76#ibcon#[27=AT03-04\r\n] 2006.257.03:51:31.76#ibcon#*before write, iclass 38, count 2 2006.257.03:51:31.76#ibcon#enter sib2, iclass 38, count 2 2006.257.03:51:31.76#ibcon#flushed, iclass 38, count 2 2006.257.03:51:31.76#ibcon#about to write, iclass 38, count 2 2006.257.03:51:31.76#ibcon#wrote, iclass 38, count 2 2006.257.03:51:31.76#ibcon#about to read 3, iclass 38, count 2 2006.257.03:51:31.79#ibcon#read 3, iclass 38, count 2 2006.257.03:51:31.79#ibcon#about to read 4, iclass 38, count 2 2006.257.03:51:31.79#ibcon#read 4, iclass 38, count 2 2006.257.03:51:31.79#ibcon#about to read 5, iclass 38, count 2 2006.257.03:51:31.79#ibcon#read 5, iclass 38, count 2 2006.257.03:51:31.79#ibcon#about to read 6, iclass 38, count 2 2006.257.03:51:31.79#ibcon#read 6, iclass 38, count 2 2006.257.03:51:31.79#ibcon#end of sib2, iclass 38, count 2 2006.257.03:51:31.79#ibcon#*after write, iclass 38, count 2 2006.257.03:51:31.79#ibcon#*before return 0, iclass 38, count 2 2006.257.03:51:31.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:31.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.03:51:31.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.03:51:31.79#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:31.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:31.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:31.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:31.91#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:51:31.91#ibcon#first serial, iclass 38, count 0 2006.257.03:51:31.91#ibcon#enter sib2, iclass 38, count 0 2006.257.03:51:31.91#ibcon#flushed, iclass 38, count 0 2006.257.03:51:31.91#ibcon#about to write, iclass 38, count 0 2006.257.03:51:31.91#ibcon#wrote, iclass 38, count 0 2006.257.03:51:31.91#ibcon#about to read 3, iclass 38, count 0 2006.257.03:51:31.93#ibcon#read 3, iclass 38, count 0 2006.257.03:51:31.93#ibcon#about to read 4, iclass 38, count 0 2006.257.03:51:31.93#ibcon#read 4, iclass 38, count 0 2006.257.03:51:31.93#ibcon#about to read 5, iclass 38, count 0 2006.257.03:51:31.93#ibcon#read 5, iclass 38, count 0 2006.257.03:51:31.93#ibcon#about to read 6, iclass 38, count 0 2006.257.03:51:31.93#ibcon#read 6, iclass 38, count 0 2006.257.03:51:31.93#ibcon#end of sib2, iclass 38, count 0 2006.257.03:51:31.93#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:51:31.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:51:31.93#ibcon#[27=USB\r\n] 2006.257.03:51:31.93#ibcon#*before write, iclass 38, count 0 2006.257.03:51:31.93#ibcon#enter sib2, iclass 38, count 0 2006.257.03:51:31.93#ibcon#flushed, iclass 38, count 0 2006.257.03:51:31.93#ibcon#about to write, iclass 38, count 0 2006.257.03:51:31.93#ibcon#wrote, iclass 38, count 0 2006.257.03:51:31.93#ibcon#about to read 3, iclass 38, count 0 2006.257.03:51:31.96#ibcon#read 3, iclass 38, count 0 2006.257.03:51:31.96#ibcon#about to read 4, iclass 38, count 0 2006.257.03:51:31.96#ibcon#read 4, iclass 38, count 0 2006.257.03:51:31.96#ibcon#about to read 5, iclass 38, count 0 2006.257.03:51:31.96#ibcon#read 5, iclass 38, count 0 2006.257.03:51:31.96#ibcon#about to read 6, iclass 38, count 0 2006.257.03:51:31.96#ibcon#read 6, iclass 38, count 0 2006.257.03:51:31.96#ibcon#end of sib2, iclass 38, count 0 2006.257.03:51:31.96#ibcon#*after write, iclass 38, count 0 2006.257.03:51:31.96#ibcon#*before return 0, iclass 38, count 0 2006.257.03:51:31.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:31.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.03:51:31.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:51:31.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:51:31.96$vck44/vblo=4,679.99 2006.257.03:51:31.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.03:51:31.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.03:51:31.96#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:31.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:31.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:31.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:31.96#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:51:31.96#ibcon#first serial, iclass 40, count 0 2006.257.03:51:31.96#ibcon#enter sib2, iclass 40, count 0 2006.257.03:51:31.96#ibcon#flushed, iclass 40, count 0 2006.257.03:51:31.96#ibcon#about to write, iclass 40, count 0 2006.257.03:51:31.96#ibcon#wrote, iclass 40, count 0 2006.257.03:51:31.96#ibcon#about to read 3, iclass 40, count 0 2006.257.03:51:31.98#ibcon#read 3, iclass 40, count 0 2006.257.03:51:31.98#ibcon#about to read 4, iclass 40, count 0 2006.257.03:51:31.98#ibcon#read 4, iclass 40, count 0 2006.257.03:51:31.98#ibcon#about to read 5, iclass 40, count 0 2006.257.03:51:31.98#ibcon#read 5, iclass 40, count 0 2006.257.03:51:31.98#ibcon#about to read 6, iclass 40, count 0 2006.257.03:51:31.98#ibcon#read 6, iclass 40, count 0 2006.257.03:51:31.98#ibcon#end of sib2, iclass 40, count 0 2006.257.03:51:31.98#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:51:31.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:51:31.98#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:51:31.98#ibcon#*before write, iclass 40, count 0 2006.257.03:51:31.98#ibcon#enter sib2, iclass 40, count 0 2006.257.03:51:31.98#ibcon#flushed, iclass 40, count 0 2006.257.03:51:31.98#ibcon#about to write, iclass 40, count 0 2006.257.03:51:31.98#ibcon#wrote, iclass 40, count 0 2006.257.03:51:31.98#ibcon#about to read 3, iclass 40, count 0 2006.257.03:51:32.02#ibcon#read 3, iclass 40, count 0 2006.257.03:51:32.02#ibcon#about to read 4, iclass 40, count 0 2006.257.03:51:32.02#ibcon#read 4, iclass 40, count 0 2006.257.03:51:32.02#ibcon#about to read 5, iclass 40, count 0 2006.257.03:51:32.02#ibcon#read 5, iclass 40, count 0 2006.257.03:51:32.02#ibcon#about to read 6, iclass 40, count 0 2006.257.03:51:32.02#ibcon#read 6, iclass 40, count 0 2006.257.03:51:32.02#ibcon#end of sib2, iclass 40, count 0 2006.257.03:51:32.02#ibcon#*after write, iclass 40, count 0 2006.257.03:51:32.02#ibcon#*before return 0, iclass 40, count 0 2006.257.03:51:32.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:32.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.03:51:32.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:51:32.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:51:32.02$vck44/vb=4,5 2006.257.03:51:32.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.03:51:32.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.03:51:32.02#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:32.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:32.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:32.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:32.08#ibcon#enter wrdev, iclass 4, count 2 2006.257.03:51:32.08#ibcon#first serial, iclass 4, count 2 2006.257.03:51:32.08#ibcon#enter sib2, iclass 4, count 2 2006.257.03:51:32.08#ibcon#flushed, iclass 4, count 2 2006.257.03:51:32.08#ibcon#about to write, iclass 4, count 2 2006.257.03:51:32.08#ibcon#wrote, iclass 4, count 2 2006.257.03:51:32.08#ibcon#about to read 3, iclass 4, count 2 2006.257.03:51:32.10#ibcon#read 3, iclass 4, count 2 2006.257.03:51:32.10#ibcon#about to read 4, iclass 4, count 2 2006.257.03:51:32.10#ibcon#read 4, iclass 4, count 2 2006.257.03:51:32.10#ibcon#about to read 5, iclass 4, count 2 2006.257.03:51:32.10#ibcon#read 5, iclass 4, count 2 2006.257.03:51:32.10#ibcon#about to read 6, iclass 4, count 2 2006.257.03:51:32.10#ibcon#read 6, iclass 4, count 2 2006.257.03:51:32.10#ibcon#end of sib2, iclass 4, count 2 2006.257.03:51:32.10#ibcon#*mode == 0, iclass 4, count 2 2006.257.03:51:32.10#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.03:51:32.10#ibcon#[27=AT04-05\r\n] 2006.257.03:51:32.10#ibcon#*before write, iclass 4, count 2 2006.257.03:51:32.10#ibcon#enter sib2, iclass 4, count 2 2006.257.03:51:32.10#ibcon#flushed, iclass 4, count 2 2006.257.03:51:32.10#ibcon#about to write, iclass 4, count 2 2006.257.03:51:32.10#ibcon#wrote, iclass 4, count 2 2006.257.03:51:32.10#ibcon#about to read 3, iclass 4, count 2 2006.257.03:51:32.13#ibcon#read 3, iclass 4, count 2 2006.257.03:51:32.13#ibcon#about to read 4, iclass 4, count 2 2006.257.03:51:32.13#ibcon#read 4, iclass 4, count 2 2006.257.03:51:32.13#ibcon#about to read 5, iclass 4, count 2 2006.257.03:51:32.13#ibcon#read 5, iclass 4, count 2 2006.257.03:51:32.13#ibcon#about to read 6, iclass 4, count 2 2006.257.03:51:32.13#ibcon#read 6, iclass 4, count 2 2006.257.03:51:32.13#ibcon#end of sib2, iclass 4, count 2 2006.257.03:51:32.13#ibcon#*after write, iclass 4, count 2 2006.257.03:51:32.13#ibcon#*before return 0, iclass 4, count 2 2006.257.03:51:32.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:32.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.03:51:32.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.03:51:32.13#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:32.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:32.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:32.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:32.25#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:51:32.25#ibcon#first serial, iclass 4, count 0 2006.257.03:51:32.25#ibcon#enter sib2, iclass 4, count 0 2006.257.03:51:32.25#ibcon#flushed, iclass 4, count 0 2006.257.03:51:32.25#ibcon#about to write, iclass 4, count 0 2006.257.03:51:32.25#ibcon#wrote, iclass 4, count 0 2006.257.03:51:32.25#ibcon#about to read 3, iclass 4, count 0 2006.257.03:51:32.27#ibcon#read 3, iclass 4, count 0 2006.257.03:51:32.27#ibcon#about to read 4, iclass 4, count 0 2006.257.03:51:32.27#ibcon#read 4, iclass 4, count 0 2006.257.03:51:32.27#ibcon#about to read 5, iclass 4, count 0 2006.257.03:51:32.27#ibcon#read 5, iclass 4, count 0 2006.257.03:51:32.27#ibcon#about to read 6, iclass 4, count 0 2006.257.03:51:32.27#ibcon#read 6, iclass 4, count 0 2006.257.03:51:32.27#ibcon#end of sib2, iclass 4, count 0 2006.257.03:51:32.27#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:51:32.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:51:32.27#ibcon#[27=USB\r\n] 2006.257.03:51:32.27#ibcon#*before write, iclass 4, count 0 2006.257.03:51:32.27#ibcon#enter sib2, iclass 4, count 0 2006.257.03:51:32.27#ibcon#flushed, iclass 4, count 0 2006.257.03:51:32.27#ibcon#about to write, iclass 4, count 0 2006.257.03:51:32.27#ibcon#wrote, iclass 4, count 0 2006.257.03:51:32.27#ibcon#about to read 3, iclass 4, count 0 2006.257.03:51:32.30#ibcon#read 3, iclass 4, count 0 2006.257.03:51:32.30#ibcon#about to read 4, iclass 4, count 0 2006.257.03:51:32.30#ibcon#read 4, iclass 4, count 0 2006.257.03:51:32.30#ibcon#about to read 5, iclass 4, count 0 2006.257.03:51:32.30#ibcon#read 5, iclass 4, count 0 2006.257.03:51:32.30#ibcon#about to read 6, iclass 4, count 0 2006.257.03:51:32.30#ibcon#read 6, iclass 4, count 0 2006.257.03:51:32.30#ibcon#end of sib2, iclass 4, count 0 2006.257.03:51:32.30#ibcon#*after write, iclass 4, count 0 2006.257.03:51:32.30#ibcon#*before return 0, iclass 4, count 0 2006.257.03:51:32.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:32.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.03:51:32.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:51:32.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:51:32.30$vck44/vblo=5,709.99 2006.257.03:51:32.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.03:51:32.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.03:51:32.30#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:32.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:32.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:32.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:32.30#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:51:32.30#ibcon#first serial, iclass 6, count 0 2006.257.03:51:32.30#ibcon#enter sib2, iclass 6, count 0 2006.257.03:51:32.30#ibcon#flushed, iclass 6, count 0 2006.257.03:51:32.30#ibcon#about to write, iclass 6, count 0 2006.257.03:51:32.30#ibcon#wrote, iclass 6, count 0 2006.257.03:51:32.30#ibcon#about to read 3, iclass 6, count 0 2006.257.03:51:32.32#ibcon#read 3, iclass 6, count 0 2006.257.03:51:32.32#ibcon#about to read 4, iclass 6, count 0 2006.257.03:51:32.32#ibcon#read 4, iclass 6, count 0 2006.257.03:51:32.32#ibcon#about to read 5, iclass 6, count 0 2006.257.03:51:32.32#ibcon#read 5, iclass 6, count 0 2006.257.03:51:32.32#ibcon#about to read 6, iclass 6, count 0 2006.257.03:51:32.32#ibcon#read 6, iclass 6, count 0 2006.257.03:51:32.32#ibcon#end of sib2, iclass 6, count 0 2006.257.03:51:32.32#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:51:32.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:51:32.32#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:51:32.32#ibcon#*before write, iclass 6, count 0 2006.257.03:51:32.32#ibcon#enter sib2, iclass 6, count 0 2006.257.03:51:32.32#ibcon#flushed, iclass 6, count 0 2006.257.03:51:32.32#ibcon#about to write, iclass 6, count 0 2006.257.03:51:32.32#ibcon#wrote, iclass 6, count 0 2006.257.03:51:32.32#ibcon#about to read 3, iclass 6, count 0 2006.257.03:51:32.36#ibcon#read 3, iclass 6, count 0 2006.257.03:51:32.36#ibcon#about to read 4, iclass 6, count 0 2006.257.03:51:32.36#ibcon#read 4, iclass 6, count 0 2006.257.03:51:32.36#ibcon#about to read 5, iclass 6, count 0 2006.257.03:51:32.36#ibcon#read 5, iclass 6, count 0 2006.257.03:51:32.36#ibcon#about to read 6, iclass 6, count 0 2006.257.03:51:32.36#ibcon#read 6, iclass 6, count 0 2006.257.03:51:32.36#ibcon#end of sib2, iclass 6, count 0 2006.257.03:51:32.36#ibcon#*after write, iclass 6, count 0 2006.257.03:51:32.36#ibcon#*before return 0, iclass 6, count 0 2006.257.03:51:32.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:32.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.03:51:32.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:51:32.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:51:32.36$vck44/vb=5,4 2006.257.03:51:32.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.03:51:32.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.03:51:32.36#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:32.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:32.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:32.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:32.42#ibcon#enter wrdev, iclass 10, count 2 2006.257.03:51:32.42#ibcon#first serial, iclass 10, count 2 2006.257.03:51:32.42#ibcon#enter sib2, iclass 10, count 2 2006.257.03:51:32.42#ibcon#flushed, iclass 10, count 2 2006.257.03:51:32.42#ibcon#about to write, iclass 10, count 2 2006.257.03:51:32.42#ibcon#wrote, iclass 10, count 2 2006.257.03:51:32.42#ibcon#about to read 3, iclass 10, count 2 2006.257.03:51:32.44#ibcon#read 3, iclass 10, count 2 2006.257.03:51:32.44#ibcon#about to read 4, iclass 10, count 2 2006.257.03:51:32.44#ibcon#read 4, iclass 10, count 2 2006.257.03:51:32.44#ibcon#about to read 5, iclass 10, count 2 2006.257.03:51:32.44#ibcon#read 5, iclass 10, count 2 2006.257.03:51:32.44#ibcon#about to read 6, iclass 10, count 2 2006.257.03:51:32.44#ibcon#read 6, iclass 10, count 2 2006.257.03:51:32.44#ibcon#end of sib2, iclass 10, count 2 2006.257.03:51:32.44#ibcon#*mode == 0, iclass 10, count 2 2006.257.03:51:32.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.03:51:32.44#ibcon#[27=AT05-04\r\n] 2006.257.03:51:32.44#ibcon#*before write, iclass 10, count 2 2006.257.03:51:32.44#ibcon#enter sib2, iclass 10, count 2 2006.257.03:51:32.44#ibcon#flushed, iclass 10, count 2 2006.257.03:51:32.44#ibcon#about to write, iclass 10, count 2 2006.257.03:51:32.44#ibcon#wrote, iclass 10, count 2 2006.257.03:51:32.44#ibcon#about to read 3, iclass 10, count 2 2006.257.03:51:32.47#ibcon#read 3, iclass 10, count 2 2006.257.03:51:32.47#ibcon#about to read 4, iclass 10, count 2 2006.257.03:51:32.47#ibcon#read 4, iclass 10, count 2 2006.257.03:51:32.47#ibcon#about to read 5, iclass 10, count 2 2006.257.03:51:32.47#ibcon#read 5, iclass 10, count 2 2006.257.03:51:32.47#ibcon#about to read 6, iclass 10, count 2 2006.257.03:51:32.47#ibcon#read 6, iclass 10, count 2 2006.257.03:51:32.47#ibcon#end of sib2, iclass 10, count 2 2006.257.03:51:32.47#ibcon#*after write, iclass 10, count 2 2006.257.03:51:32.47#ibcon#*before return 0, iclass 10, count 2 2006.257.03:51:32.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:32.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.03:51:32.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.03:51:32.47#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:32.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:32.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:32.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:32.59#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:51:32.59#ibcon#first serial, iclass 10, count 0 2006.257.03:51:32.59#ibcon#enter sib2, iclass 10, count 0 2006.257.03:51:32.59#ibcon#flushed, iclass 10, count 0 2006.257.03:51:32.59#ibcon#about to write, iclass 10, count 0 2006.257.03:51:32.59#ibcon#wrote, iclass 10, count 0 2006.257.03:51:32.59#ibcon#about to read 3, iclass 10, count 0 2006.257.03:51:32.61#ibcon#read 3, iclass 10, count 0 2006.257.03:51:32.61#ibcon#about to read 4, iclass 10, count 0 2006.257.03:51:32.61#ibcon#read 4, iclass 10, count 0 2006.257.03:51:32.61#ibcon#about to read 5, iclass 10, count 0 2006.257.03:51:32.61#ibcon#read 5, iclass 10, count 0 2006.257.03:51:32.61#ibcon#about to read 6, iclass 10, count 0 2006.257.03:51:32.61#ibcon#read 6, iclass 10, count 0 2006.257.03:51:32.61#ibcon#end of sib2, iclass 10, count 0 2006.257.03:51:32.61#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:51:32.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:51:32.61#ibcon#[27=USB\r\n] 2006.257.03:51:32.61#ibcon#*before write, iclass 10, count 0 2006.257.03:51:32.61#ibcon#enter sib2, iclass 10, count 0 2006.257.03:51:32.61#ibcon#flushed, iclass 10, count 0 2006.257.03:51:32.61#ibcon#about to write, iclass 10, count 0 2006.257.03:51:32.61#ibcon#wrote, iclass 10, count 0 2006.257.03:51:32.61#ibcon#about to read 3, iclass 10, count 0 2006.257.03:51:32.64#ibcon#read 3, iclass 10, count 0 2006.257.03:51:32.64#ibcon#about to read 4, iclass 10, count 0 2006.257.03:51:32.64#ibcon#read 4, iclass 10, count 0 2006.257.03:51:32.64#ibcon#about to read 5, iclass 10, count 0 2006.257.03:51:32.64#ibcon#read 5, iclass 10, count 0 2006.257.03:51:32.64#ibcon#about to read 6, iclass 10, count 0 2006.257.03:51:32.64#ibcon#read 6, iclass 10, count 0 2006.257.03:51:32.64#ibcon#end of sib2, iclass 10, count 0 2006.257.03:51:32.64#ibcon#*after write, iclass 10, count 0 2006.257.03:51:32.64#ibcon#*before return 0, iclass 10, count 0 2006.257.03:51:32.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:32.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.03:51:32.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:51:32.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:51:32.64$vck44/vblo=6,719.99 2006.257.03:51:32.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.03:51:32.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.03:51:32.64#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:32.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:32.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:32.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:32.64#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:51:32.64#ibcon#first serial, iclass 12, count 0 2006.257.03:51:32.64#ibcon#enter sib2, iclass 12, count 0 2006.257.03:51:32.64#ibcon#flushed, iclass 12, count 0 2006.257.03:51:32.64#ibcon#about to write, iclass 12, count 0 2006.257.03:51:32.64#ibcon#wrote, iclass 12, count 0 2006.257.03:51:32.64#ibcon#about to read 3, iclass 12, count 0 2006.257.03:51:32.66#ibcon#read 3, iclass 12, count 0 2006.257.03:51:32.66#ibcon#about to read 4, iclass 12, count 0 2006.257.03:51:32.66#ibcon#read 4, iclass 12, count 0 2006.257.03:51:32.66#ibcon#about to read 5, iclass 12, count 0 2006.257.03:51:32.66#ibcon#read 5, iclass 12, count 0 2006.257.03:51:32.66#ibcon#about to read 6, iclass 12, count 0 2006.257.03:51:32.66#ibcon#read 6, iclass 12, count 0 2006.257.03:51:32.66#ibcon#end of sib2, iclass 12, count 0 2006.257.03:51:32.66#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:51:32.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:51:32.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:51:32.66#ibcon#*before write, iclass 12, count 0 2006.257.03:51:32.66#ibcon#enter sib2, iclass 12, count 0 2006.257.03:51:32.66#ibcon#flushed, iclass 12, count 0 2006.257.03:51:32.66#ibcon#about to write, iclass 12, count 0 2006.257.03:51:32.66#ibcon#wrote, iclass 12, count 0 2006.257.03:51:32.66#ibcon#about to read 3, iclass 12, count 0 2006.257.03:51:32.70#ibcon#read 3, iclass 12, count 0 2006.257.03:51:32.70#ibcon#about to read 4, iclass 12, count 0 2006.257.03:51:32.70#ibcon#read 4, iclass 12, count 0 2006.257.03:51:32.70#ibcon#about to read 5, iclass 12, count 0 2006.257.03:51:32.70#ibcon#read 5, iclass 12, count 0 2006.257.03:51:32.70#ibcon#about to read 6, iclass 12, count 0 2006.257.03:51:32.70#ibcon#read 6, iclass 12, count 0 2006.257.03:51:32.70#ibcon#end of sib2, iclass 12, count 0 2006.257.03:51:32.70#ibcon#*after write, iclass 12, count 0 2006.257.03:51:32.70#ibcon#*before return 0, iclass 12, count 0 2006.257.03:51:32.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:32.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.03:51:32.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:51:32.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:51:32.70$vck44/vb=6,4 2006.257.03:51:32.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.03:51:32.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.03:51:32.70#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:32.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:32.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:32.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:32.76#ibcon#enter wrdev, iclass 14, count 2 2006.257.03:51:32.76#ibcon#first serial, iclass 14, count 2 2006.257.03:51:32.76#ibcon#enter sib2, iclass 14, count 2 2006.257.03:51:32.76#ibcon#flushed, iclass 14, count 2 2006.257.03:51:32.76#ibcon#about to write, iclass 14, count 2 2006.257.03:51:32.76#ibcon#wrote, iclass 14, count 2 2006.257.03:51:32.76#ibcon#about to read 3, iclass 14, count 2 2006.257.03:51:32.78#ibcon#read 3, iclass 14, count 2 2006.257.03:51:32.78#ibcon#about to read 4, iclass 14, count 2 2006.257.03:51:32.78#ibcon#read 4, iclass 14, count 2 2006.257.03:51:32.78#ibcon#about to read 5, iclass 14, count 2 2006.257.03:51:32.78#ibcon#read 5, iclass 14, count 2 2006.257.03:51:32.78#ibcon#about to read 6, iclass 14, count 2 2006.257.03:51:32.78#ibcon#read 6, iclass 14, count 2 2006.257.03:51:32.78#ibcon#end of sib2, iclass 14, count 2 2006.257.03:51:32.78#ibcon#*mode == 0, iclass 14, count 2 2006.257.03:51:32.78#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.03:51:32.78#ibcon#[27=AT06-04\r\n] 2006.257.03:51:32.78#ibcon#*before write, iclass 14, count 2 2006.257.03:51:32.78#ibcon#enter sib2, iclass 14, count 2 2006.257.03:51:32.78#ibcon#flushed, iclass 14, count 2 2006.257.03:51:32.78#ibcon#about to write, iclass 14, count 2 2006.257.03:51:32.78#ibcon#wrote, iclass 14, count 2 2006.257.03:51:32.78#ibcon#about to read 3, iclass 14, count 2 2006.257.03:51:32.81#ibcon#read 3, iclass 14, count 2 2006.257.03:51:32.81#ibcon#about to read 4, iclass 14, count 2 2006.257.03:51:32.81#ibcon#read 4, iclass 14, count 2 2006.257.03:51:32.81#ibcon#about to read 5, iclass 14, count 2 2006.257.03:51:32.81#ibcon#read 5, iclass 14, count 2 2006.257.03:51:32.81#ibcon#about to read 6, iclass 14, count 2 2006.257.03:51:32.81#ibcon#read 6, iclass 14, count 2 2006.257.03:51:32.81#ibcon#end of sib2, iclass 14, count 2 2006.257.03:51:32.81#ibcon#*after write, iclass 14, count 2 2006.257.03:51:32.81#ibcon#*before return 0, iclass 14, count 2 2006.257.03:51:32.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:32.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.03:51:32.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.03:51:32.81#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:32.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:32.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:32.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:32.93#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:51:32.93#ibcon#first serial, iclass 14, count 0 2006.257.03:51:32.93#ibcon#enter sib2, iclass 14, count 0 2006.257.03:51:32.93#ibcon#flushed, iclass 14, count 0 2006.257.03:51:32.93#ibcon#about to write, iclass 14, count 0 2006.257.03:51:32.93#ibcon#wrote, iclass 14, count 0 2006.257.03:51:32.93#ibcon#about to read 3, iclass 14, count 0 2006.257.03:51:32.95#ibcon#read 3, iclass 14, count 0 2006.257.03:51:32.95#ibcon#about to read 4, iclass 14, count 0 2006.257.03:51:32.95#ibcon#read 4, iclass 14, count 0 2006.257.03:51:32.95#ibcon#about to read 5, iclass 14, count 0 2006.257.03:51:32.95#ibcon#read 5, iclass 14, count 0 2006.257.03:51:32.95#ibcon#about to read 6, iclass 14, count 0 2006.257.03:51:32.95#ibcon#read 6, iclass 14, count 0 2006.257.03:51:32.95#ibcon#end of sib2, iclass 14, count 0 2006.257.03:51:32.95#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:51:32.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:51:32.95#ibcon#[27=USB\r\n] 2006.257.03:51:32.95#ibcon#*before write, iclass 14, count 0 2006.257.03:51:32.95#ibcon#enter sib2, iclass 14, count 0 2006.257.03:51:32.95#ibcon#flushed, iclass 14, count 0 2006.257.03:51:32.95#ibcon#about to write, iclass 14, count 0 2006.257.03:51:32.95#ibcon#wrote, iclass 14, count 0 2006.257.03:51:32.95#ibcon#about to read 3, iclass 14, count 0 2006.257.03:51:32.98#ibcon#read 3, iclass 14, count 0 2006.257.03:51:32.98#ibcon#about to read 4, iclass 14, count 0 2006.257.03:51:32.98#ibcon#read 4, iclass 14, count 0 2006.257.03:51:32.98#ibcon#about to read 5, iclass 14, count 0 2006.257.03:51:32.98#ibcon#read 5, iclass 14, count 0 2006.257.03:51:32.98#ibcon#about to read 6, iclass 14, count 0 2006.257.03:51:32.98#ibcon#read 6, iclass 14, count 0 2006.257.03:51:32.98#ibcon#end of sib2, iclass 14, count 0 2006.257.03:51:32.98#ibcon#*after write, iclass 14, count 0 2006.257.03:51:32.98#ibcon#*before return 0, iclass 14, count 0 2006.257.03:51:32.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:32.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.03:51:32.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:51:32.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:51:32.98$vck44/vblo=7,734.99 2006.257.03:51:32.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.03:51:32.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.03:51:32.98#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:32.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:32.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:32.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:32.98#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:51:32.98#ibcon#first serial, iclass 16, count 0 2006.257.03:51:32.98#ibcon#enter sib2, iclass 16, count 0 2006.257.03:51:32.98#ibcon#flushed, iclass 16, count 0 2006.257.03:51:32.98#ibcon#about to write, iclass 16, count 0 2006.257.03:51:32.98#ibcon#wrote, iclass 16, count 0 2006.257.03:51:32.98#ibcon#about to read 3, iclass 16, count 0 2006.257.03:51:33.00#ibcon#read 3, iclass 16, count 0 2006.257.03:51:33.00#ibcon#about to read 4, iclass 16, count 0 2006.257.03:51:33.00#ibcon#read 4, iclass 16, count 0 2006.257.03:51:33.00#ibcon#about to read 5, iclass 16, count 0 2006.257.03:51:33.00#ibcon#read 5, iclass 16, count 0 2006.257.03:51:33.00#ibcon#about to read 6, iclass 16, count 0 2006.257.03:51:33.00#ibcon#read 6, iclass 16, count 0 2006.257.03:51:33.00#ibcon#end of sib2, iclass 16, count 0 2006.257.03:51:33.00#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:51:33.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:51:33.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:51:33.00#ibcon#*before write, iclass 16, count 0 2006.257.03:51:33.00#ibcon#enter sib2, iclass 16, count 0 2006.257.03:51:33.00#ibcon#flushed, iclass 16, count 0 2006.257.03:51:33.00#ibcon#about to write, iclass 16, count 0 2006.257.03:51:33.00#ibcon#wrote, iclass 16, count 0 2006.257.03:51:33.00#ibcon#about to read 3, iclass 16, count 0 2006.257.03:51:33.04#ibcon#read 3, iclass 16, count 0 2006.257.03:51:33.04#ibcon#about to read 4, iclass 16, count 0 2006.257.03:51:33.04#ibcon#read 4, iclass 16, count 0 2006.257.03:51:33.04#ibcon#about to read 5, iclass 16, count 0 2006.257.03:51:33.04#ibcon#read 5, iclass 16, count 0 2006.257.03:51:33.04#ibcon#about to read 6, iclass 16, count 0 2006.257.03:51:33.04#ibcon#read 6, iclass 16, count 0 2006.257.03:51:33.04#ibcon#end of sib2, iclass 16, count 0 2006.257.03:51:33.04#ibcon#*after write, iclass 16, count 0 2006.257.03:51:33.04#ibcon#*before return 0, iclass 16, count 0 2006.257.03:51:33.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:33.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.03:51:33.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:51:33.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:51:33.04$vck44/vb=7,4 2006.257.03:51:33.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.03:51:33.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.03:51:33.04#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:33.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:33.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:33.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:33.10#ibcon#enter wrdev, iclass 18, count 2 2006.257.03:51:33.10#ibcon#first serial, iclass 18, count 2 2006.257.03:51:33.10#ibcon#enter sib2, iclass 18, count 2 2006.257.03:51:33.10#ibcon#flushed, iclass 18, count 2 2006.257.03:51:33.10#ibcon#about to write, iclass 18, count 2 2006.257.03:51:33.10#ibcon#wrote, iclass 18, count 2 2006.257.03:51:33.10#ibcon#about to read 3, iclass 18, count 2 2006.257.03:51:33.12#ibcon#read 3, iclass 18, count 2 2006.257.03:51:33.12#ibcon#about to read 4, iclass 18, count 2 2006.257.03:51:33.12#ibcon#read 4, iclass 18, count 2 2006.257.03:51:33.12#ibcon#about to read 5, iclass 18, count 2 2006.257.03:51:33.12#ibcon#read 5, iclass 18, count 2 2006.257.03:51:33.12#ibcon#about to read 6, iclass 18, count 2 2006.257.03:51:33.12#ibcon#read 6, iclass 18, count 2 2006.257.03:51:33.12#ibcon#end of sib2, iclass 18, count 2 2006.257.03:51:33.12#ibcon#*mode == 0, iclass 18, count 2 2006.257.03:51:33.12#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.03:51:33.12#ibcon#[27=AT07-04\r\n] 2006.257.03:51:33.12#ibcon#*before write, iclass 18, count 2 2006.257.03:51:33.12#ibcon#enter sib2, iclass 18, count 2 2006.257.03:51:33.12#ibcon#flushed, iclass 18, count 2 2006.257.03:51:33.12#ibcon#about to write, iclass 18, count 2 2006.257.03:51:33.12#ibcon#wrote, iclass 18, count 2 2006.257.03:51:33.12#ibcon#about to read 3, iclass 18, count 2 2006.257.03:51:33.15#ibcon#read 3, iclass 18, count 2 2006.257.03:51:33.15#ibcon#about to read 4, iclass 18, count 2 2006.257.03:51:33.15#ibcon#read 4, iclass 18, count 2 2006.257.03:51:33.15#ibcon#about to read 5, iclass 18, count 2 2006.257.03:51:33.15#ibcon#read 5, iclass 18, count 2 2006.257.03:51:33.15#ibcon#about to read 6, iclass 18, count 2 2006.257.03:51:33.15#ibcon#read 6, iclass 18, count 2 2006.257.03:51:33.15#ibcon#end of sib2, iclass 18, count 2 2006.257.03:51:33.15#ibcon#*after write, iclass 18, count 2 2006.257.03:51:33.15#ibcon#*before return 0, iclass 18, count 2 2006.257.03:51:33.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:33.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.03:51:33.15#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.03:51:33.15#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:33.15#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:33.27#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:33.27#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:33.27#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:51:33.27#ibcon#first serial, iclass 18, count 0 2006.257.03:51:33.27#ibcon#enter sib2, iclass 18, count 0 2006.257.03:51:33.27#ibcon#flushed, iclass 18, count 0 2006.257.03:51:33.27#ibcon#about to write, iclass 18, count 0 2006.257.03:51:33.27#ibcon#wrote, iclass 18, count 0 2006.257.03:51:33.27#ibcon#about to read 3, iclass 18, count 0 2006.257.03:51:33.29#ibcon#read 3, iclass 18, count 0 2006.257.03:51:33.29#ibcon#about to read 4, iclass 18, count 0 2006.257.03:51:33.29#ibcon#read 4, iclass 18, count 0 2006.257.03:51:33.29#ibcon#about to read 5, iclass 18, count 0 2006.257.03:51:33.29#ibcon#read 5, iclass 18, count 0 2006.257.03:51:33.29#ibcon#about to read 6, iclass 18, count 0 2006.257.03:51:33.29#ibcon#read 6, iclass 18, count 0 2006.257.03:51:33.29#ibcon#end of sib2, iclass 18, count 0 2006.257.03:51:33.29#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:51:33.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:51:33.29#ibcon#[27=USB\r\n] 2006.257.03:51:33.29#ibcon#*before write, iclass 18, count 0 2006.257.03:51:33.29#ibcon#enter sib2, iclass 18, count 0 2006.257.03:51:33.29#ibcon#flushed, iclass 18, count 0 2006.257.03:51:33.29#ibcon#about to write, iclass 18, count 0 2006.257.03:51:33.29#ibcon#wrote, iclass 18, count 0 2006.257.03:51:33.29#ibcon#about to read 3, iclass 18, count 0 2006.257.03:51:33.32#ibcon#read 3, iclass 18, count 0 2006.257.03:51:33.32#ibcon#about to read 4, iclass 18, count 0 2006.257.03:51:33.32#ibcon#read 4, iclass 18, count 0 2006.257.03:51:33.32#ibcon#about to read 5, iclass 18, count 0 2006.257.03:51:33.32#ibcon#read 5, iclass 18, count 0 2006.257.03:51:33.32#ibcon#about to read 6, iclass 18, count 0 2006.257.03:51:33.32#ibcon#read 6, iclass 18, count 0 2006.257.03:51:33.32#ibcon#end of sib2, iclass 18, count 0 2006.257.03:51:33.32#ibcon#*after write, iclass 18, count 0 2006.257.03:51:33.32#ibcon#*before return 0, iclass 18, count 0 2006.257.03:51:33.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:33.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.03:51:33.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:51:33.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:51:33.32$vck44/vblo=8,744.99 2006.257.03:51:33.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.03:51:33.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.03:51:33.32#ibcon#ireg 17 cls_cnt 0 2006.257.03:51:33.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:33.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:33.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:33.32#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:51:33.32#ibcon#first serial, iclass 20, count 0 2006.257.03:51:33.32#ibcon#enter sib2, iclass 20, count 0 2006.257.03:51:33.32#ibcon#flushed, iclass 20, count 0 2006.257.03:51:33.32#ibcon#about to write, iclass 20, count 0 2006.257.03:51:33.32#ibcon#wrote, iclass 20, count 0 2006.257.03:51:33.32#ibcon#about to read 3, iclass 20, count 0 2006.257.03:51:33.34#ibcon#read 3, iclass 20, count 0 2006.257.03:51:33.34#ibcon#about to read 4, iclass 20, count 0 2006.257.03:51:33.34#ibcon#read 4, iclass 20, count 0 2006.257.03:51:33.34#ibcon#about to read 5, iclass 20, count 0 2006.257.03:51:33.34#ibcon#read 5, iclass 20, count 0 2006.257.03:51:33.34#ibcon#about to read 6, iclass 20, count 0 2006.257.03:51:33.34#ibcon#read 6, iclass 20, count 0 2006.257.03:51:33.34#ibcon#end of sib2, iclass 20, count 0 2006.257.03:51:33.34#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:51:33.34#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:51:33.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:51:33.34#ibcon#*before write, iclass 20, count 0 2006.257.03:51:33.34#ibcon#enter sib2, iclass 20, count 0 2006.257.03:51:33.34#ibcon#flushed, iclass 20, count 0 2006.257.03:51:33.34#ibcon#about to write, iclass 20, count 0 2006.257.03:51:33.34#ibcon#wrote, iclass 20, count 0 2006.257.03:51:33.34#ibcon#about to read 3, iclass 20, count 0 2006.257.03:51:33.38#ibcon#read 3, iclass 20, count 0 2006.257.03:51:33.38#ibcon#about to read 4, iclass 20, count 0 2006.257.03:51:33.38#ibcon#read 4, iclass 20, count 0 2006.257.03:51:33.38#ibcon#about to read 5, iclass 20, count 0 2006.257.03:51:33.38#ibcon#read 5, iclass 20, count 0 2006.257.03:51:33.38#ibcon#about to read 6, iclass 20, count 0 2006.257.03:51:33.38#ibcon#read 6, iclass 20, count 0 2006.257.03:51:33.38#ibcon#end of sib2, iclass 20, count 0 2006.257.03:51:33.38#ibcon#*after write, iclass 20, count 0 2006.257.03:51:33.38#ibcon#*before return 0, iclass 20, count 0 2006.257.03:51:33.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:33.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.03:51:33.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:51:33.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:51:33.38$vck44/vb=8,4 2006.257.03:51:33.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.03:51:33.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.03:51:33.38#ibcon#ireg 11 cls_cnt 2 2006.257.03:51:33.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:33.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:33.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:33.44#ibcon#enter wrdev, iclass 22, count 2 2006.257.03:51:33.44#ibcon#first serial, iclass 22, count 2 2006.257.03:51:33.44#ibcon#enter sib2, iclass 22, count 2 2006.257.03:51:33.44#ibcon#flushed, iclass 22, count 2 2006.257.03:51:33.44#ibcon#about to write, iclass 22, count 2 2006.257.03:51:33.44#ibcon#wrote, iclass 22, count 2 2006.257.03:51:33.44#ibcon#about to read 3, iclass 22, count 2 2006.257.03:51:33.46#ibcon#read 3, iclass 22, count 2 2006.257.03:51:33.46#ibcon#about to read 4, iclass 22, count 2 2006.257.03:51:33.46#ibcon#read 4, iclass 22, count 2 2006.257.03:51:33.46#ibcon#about to read 5, iclass 22, count 2 2006.257.03:51:33.46#ibcon#read 5, iclass 22, count 2 2006.257.03:51:33.46#ibcon#about to read 6, iclass 22, count 2 2006.257.03:51:33.46#ibcon#read 6, iclass 22, count 2 2006.257.03:51:33.46#ibcon#end of sib2, iclass 22, count 2 2006.257.03:51:33.46#ibcon#*mode == 0, iclass 22, count 2 2006.257.03:51:33.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.03:51:33.46#ibcon#[27=AT08-04\r\n] 2006.257.03:51:33.46#ibcon#*before write, iclass 22, count 2 2006.257.03:51:33.46#ibcon#enter sib2, iclass 22, count 2 2006.257.03:51:33.46#ibcon#flushed, iclass 22, count 2 2006.257.03:51:33.46#ibcon#about to write, iclass 22, count 2 2006.257.03:51:33.46#ibcon#wrote, iclass 22, count 2 2006.257.03:51:33.46#ibcon#about to read 3, iclass 22, count 2 2006.257.03:51:33.49#ibcon#read 3, iclass 22, count 2 2006.257.03:51:33.49#ibcon#about to read 4, iclass 22, count 2 2006.257.03:51:33.49#ibcon#read 4, iclass 22, count 2 2006.257.03:51:33.49#ibcon#about to read 5, iclass 22, count 2 2006.257.03:51:33.49#ibcon#read 5, iclass 22, count 2 2006.257.03:51:33.49#ibcon#about to read 6, iclass 22, count 2 2006.257.03:51:33.49#ibcon#read 6, iclass 22, count 2 2006.257.03:51:33.49#ibcon#end of sib2, iclass 22, count 2 2006.257.03:51:33.49#ibcon#*after write, iclass 22, count 2 2006.257.03:51:33.49#ibcon#*before return 0, iclass 22, count 2 2006.257.03:51:33.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:33.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.03:51:33.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.03:51:33.49#ibcon#ireg 7 cls_cnt 0 2006.257.03:51:33.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:33.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:33.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:33.61#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:51:33.61#ibcon#first serial, iclass 22, count 0 2006.257.03:51:33.61#ibcon#enter sib2, iclass 22, count 0 2006.257.03:51:33.61#ibcon#flushed, iclass 22, count 0 2006.257.03:51:33.61#ibcon#about to write, iclass 22, count 0 2006.257.03:51:33.61#ibcon#wrote, iclass 22, count 0 2006.257.03:51:33.61#ibcon#about to read 3, iclass 22, count 0 2006.257.03:51:33.63#ibcon#read 3, iclass 22, count 0 2006.257.03:51:33.63#ibcon#about to read 4, iclass 22, count 0 2006.257.03:51:33.63#ibcon#read 4, iclass 22, count 0 2006.257.03:51:33.63#ibcon#about to read 5, iclass 22, count 0 2006.257.03:51:33.63#ibcon#read 5, iclass 22, count 0 2006.257.03:51:33.63#ibcon#about to read 6, iclass 22, count 0 2006.257.03:51:33.63#ibcon#read 6, iclass 22, count 0 2006.257.03:51:33.63#ibcon#end of sib2, iclass 22, count 0 2006.257.03:51:33.63#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:51:33.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:51:33.63#ibcon#[27=USB\r\n] 2006.257.03:51:33.63#ibcon#*before write, iclass 22, count 0 2006.257.03:51:33.63#ibcon#enter sib2, iclass 22, count 0 2006.257.03:51:33.63#ibcon#flushed, iclass 22, count 0 2006.257.03:51:33.63#ibcon#about to write, iclass 22, count 0 2006.257.03:51:33.63#ibcon#wrote, iclass 22, count 0 2006.257.03:51:33.63#ibcon#about to read 3, iclass 22, count 0 2006.257.03:51:33.66#ibcon#read 3, iclass 22, count 0 2006.257.03:51:33.66#ibcon#about to read 4, iclass 22, count 0 2006.257.03:51:33.66#ibcon#read 4, iclass 22, count 0 2006.257.03:51:33.66#ibcon#about to read 5, iclass 22, count 0 2006.257.03:51:33.66#ibcon#read 5, iclass 22, count 0 2006.257.03:51:33.66#ibcon#about to read 6, iclass 22, count 0 2006.257.03:51:33.66#ibcon#read 6, iclass 22, count 0 2006.257.03:51:33.66#ibcon#end of sib2, iclass 22, count 0 2006.257.03:51:33.66#ibcon#*after write, iclass 22, count 0 2006.257.03:51:33.66#ibcon#*before return 0, iclass 22, count 0 2006.257.03:51:33.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:33.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.03:51:33.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:51:33.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:51:33.66$vck44/vabw=wide 2006.257.03:51:33.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.03:51:33.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.03:51:33.66#ibcon#ireg 8 cls_cnt 0 2006.257.03:51:33.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:33.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:33.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:33.66#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:51:33.66#ibcon#first serial, iclass 24, count 0 2006.257.03:51:33.66#ibcon#enter sib2, iclass 24, count 0 2006.257.03:51:33.66#ibcon#flushed, iclass 24, count 0 2006.257.03:51:33.66#ibcon#about to write, iclass 24, count 0 2006.257.03:51:33.66#ibcon#wrote, iclass 24, count 0 2006.257.03:51:33.66#ibcon#about to read 3, iclass 24, count 0 2006.257.03:51:33.68#ibcon#read 3, iclass 24, count 0 2006.257.03:51:33.68#ibcon#about to read 4, iclass 24, count 0 2006.257.03:51:33.68#ibcon#read 4, iclass 24, count 0 2006.257.03:51:33.68#ibcon#about to read 5, iclass 24, count 0 2006.257.03:51:33.68#ibcon#read 5, iclass 24, count 0 2006.257.03:51:33.68#ibcon#about to read 6, iclass 24, count 0 2006.257.03:51:33.68#ibcon#read 6, iclass 24, count 0 2006.257.03:51:33.68#ibcon#end of sib2, iclass 24, count 0 2006.257.03:51:33.68#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:51:33.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:51:33.68#ibcon#[25=BW32\r\n] 2006.257.03:51:33.68#ibcon#*before write, iclass 24, count 0 2006.257.03:51:33.68#ibcon#enter sib2, iclass 24, count 0 2006.257.03:51:33.68#ibcon#flushed, iclass 24, count 0 2006.257.03:51:33.68#ibcon#about to write, iclass 24, count 0 2006.257.03:51:33.68#ibcon#wrote, iclass 24, count 0 2006.257.03:51:33.68#ibcon#about to read 3, iclass 24, count 0 2006.257.03:51:33.71#ibcon#read 3, iclass 24, count 0 2006.257.03:51:33.71#ibcon#about to read 4, iclass 24, count 0 2006.257.03:51:33.71#ibcon#read 4, iclass 24, count 0 2006.257.03:51:33.71#ibcon#about to read 5, iclass 24, count 0 2006.257.03:51:33.71#ibcon#read 5, iclass 24, count 0 2006.257.03:51:33.71#ibcon#about to read 6, iclass 24, count 0 2006.257.03:51:33.71#ibcon#read 6, iclass 24, count 0 2006.257.03:51:33.71#ibcon#end of sib2, iclass 24, count 0 2006.257.03:51:33.71#ibcon#*after write, iclass 24, count 0 2006.257.03:51:33.71#ibcon#*before return 0, iclass 24, count 0 2006.257.03:51:33.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:33.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.03:51:33.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:51:33.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:51:33.71$vck44/vbbw=wide 2006.257.03:51:33.71#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.03:51:33.71#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.03:51:33.71#ibcon#ireg 8 cls_cnt 0 2006.257.03:51:33.71#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:51:33.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:51:33.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:51:33.78#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:51:33.78#ibcon#first serial, iclass 26, count 0 2006.257.03:51:33.78#ibcon#enter sib2, iclass 26, count 0 2006.257.03:51:33.78#ibcon#flushed, iclass 26, count 0 2006.257.03:51:33.78#ibcon#about to write, iclass 26, count 0 2006.257.03:51:33.78#ibcon#wrote, iclass 26, count 0 2006.257.03:51:33.78#ibcon#about to read 3, iclass 26, count 0 2006.257.03:51:33.80#ibcon#read 3, iclass 26, count 0 2006.257.03:51:33.80#ibcon#about to read 4, iclass 26, count 0 2006.257.03:51:33.80#ibcon#read 4, iclass 26, count 0 2006.257.03:51:33.80#ibcon#about to read 5, iclass 26, count 0 2006.257.03:51:33.80#ibcon#read 5, iclass 26, count 0 2006.257.03:51:33.80#ibcon#about to read 6, iclass 26, count 0 2006.257.03:51:33.80#ibcon#read 6, iclass 26, count 0 2006.257.03:51:33.80#ibcon#end of sib2, iclass 26, count 0 2006.257.03:51:33.80#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:51:33.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:51:33.80#ibcon#[27=BW32\r\n] 2006.257.03:51:33.80#ibcon#*before write, iclass 26, count 0 2006.257.03:51:33.80#ibcon#enter sib2, iclass 26, count 0 2006.257.03:51:33.80#ibcon#flushed, iclass 26, count 0 2006.257.03:51:33.80#ibcon#about to write, iclass 26, count 0 2006.257.03:51:33.80#ibcon#wrote, iclass 26, count 0 2006.257.03:51:33.80#ibcon#about to read 3, iclass 26, count 0 2006.257.03:51:33.83#ibcon#read 3, iclass 26, count 0 2006.257.03:51:33.83#ibcon#about to read 4, iclass 26, count 0 2006.257.03:51:33.83#ibcon#read 4, iclass 26, count 0 2006.257.03:51:33.83#ibcon#about to read 5, iclass 26, count 0 2006.257.03:51:33.83#ibcon#read 5, iclass 26, count 0 2006.257.03:51:33.83#ibcon#about to read 6, iclass 26, count 0 2006.257.03:51:33.83#ibcon#read 6, iclass 26, count 0 2006.257.03:51:33.83#ibcon#end of sib2, iclass 26, count 0 2006.257.03:51:33.83#ibcon#*after write, iclass 26, count 0 2006.257.03:51:33.83#ibcon#*before return 0, iclass 26, count 0 2006.257.03:51:33.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:51:33.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:51:33.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:51:33.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:51:33.83$setupk4/ifdk4 2006.257.03:51:33.83$ifdk4/lo= 2006.257.03:51:33.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:51:33.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:51:33.83$ifdk4/patch= 2006.257.03:51:33.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:51:33.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:51:33.83$setupk4/!*+20s 2006.257.03:51:34.99#abcon#<5=/13 1.5 6.8 19.34 951012.2\r\n> 2006.257.03:51:35.01#abcon#{5=INTERFACE CLEAR} 2006.257.03:51:35.07#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:51:45.14#trakl#Source acquired 2006.257.03:51:45.16#abcon#<5=/13 1.5 6.8 19.34 951012.2\r\n> 2006.257.03:51:45.18#abcon#{5=INTERFACE CLEAR} 2006.257.03:51:45.24#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:51:47.14#flagr#flagr/antenna,acquired 2006.257.03:51:48.34$setupk4/"tpicd 2006.257.03:51:48.34$setupk4/echo=off 2006.257.03:51:48.34$setupk4/xlog=off 2006.257.03:51:48.34:!2006.257.03:52:00 2006.257.03:52:00.00:preob 2006.257.03:52:00.13/onsource/TRACKING 2006.257.03:52:00.13:!2006.257.03:52:10 2006.257.03:52:10.00:"tape 2006.257.03:52:10.00:"st=record 2006.257.03:52:10.00:data_valid=on 2006.257.03:52:10.00:midob 2006.257.03:52:11.13/onsource/TRACKING 2006.257.03:52:11.13/wx/19.33,1012.2,95 2006.257.03:52:11.31/cable/+6.4847E-03 2006.257.03:52:12.40/va/01,08,usb,yes,31,34 2006.257.03:52:12.40/va/02,07,usb,yes,34,34 2006.257.03:52:12.40/va/03,08,usb,yes,30,32 2006.257.03:52:12.40/va/04,07,usb,yes,35,37 2006.257.03:52:12.40/va/05,04,usb,yes,31,32 2006.257.03:52:12.40/va/06,04,usb,yes,35,35 2006.257.03:52:12.40/va/07,04,usb,yes,36,36 2006.257.03:52:12.40/va/08,04,usb,yes,30,37 2006.257.03:52:12.63/valo/01,524.99,yes,locked 2006.257.03:52:12.63/valo/02,534.99,yes,locked 2006.257.03:52:12.63/valo/03,564.99,yes,locked 2006.257.03:52:12.63/valo/04,624.99,yes,locked 2006.257.03:52:12.63/valo/05,734.99,yes,locked 2006.257.03:52:12.63/valo/06,814.99,yes,locked 2006.257.03:52:12.63/valo/07,864.99,yes,locked 2006.257.03:52:12.63/valo/08,884.99,yes,locked 2006.257.03:52:13.72/vb/01,04,usb,yes,30,28 2006.257.03:52:13.72/vb/02,05,usb,yes,29,29 2006.257.03:52:13.72/vb/03,04,usb,yes,30,33 2006.257.03:52:13.72/vb/04,05,usb,yes,30,29 2006.257.03:52:13.72/vb/05,04,usb,yes,26,29 2006.257.03:52:13.72/vb/06,04,usb,yes,31,27 2006.257.03:52:13.72/vb/07,04,usb,yes,31,31 2006.257.03:52:13.72/vb/08,04,usb,yes,28,31 2006.257.03:52:13.96/vblo/01,629.99,yes,locked 2006.257.03:52:13.96/vblo/02,634.99,yes,locked 2006.257.03:52:13.96/vblo/03,649.99,yes,locked 2006.257.03:52:13.96/vblo/04,679.99,yes,locked 2006.257.03:52:13.96/vblo/05,709.99,yes,locked 2006.257.03:52:13.96/vblo/06,719.99,yes,locked 2006.257.03:52:13.96/vblo/07,734.99,yes,locked 2006.257.03:52:13.96/vblo/08,744.99,yes,locked 2006.257.03:52:14.11/vabw/8 2006.257.03:52:14.26/vbbw/8 2006.257.03:52:14.35/xfe/off,on,16.5 2006.257.03:52:14.72/ifatt/23,28,28,28 2006.257.03:52:15.07/fmout-gps/S +4.52E-07 2006.257.03:52:15.11:!2006.257.03:53:00 2006.257.03:53:00.00:data_valid=off 2006.257.03:53:00.00:"et 2006.257.03:53:00.01:!+3s 2006.257.03:53:03.03:"tape 2006.257.03:53:03.03:postob 2006.257.03:53:03.19/cable/+6.4830E-03 2006.257.03:53:03.19/wx/19.30,1012.2,95 2006.257.03:53:03.25/fmout-gps/S +4.52E-07 2006.257.03:53:03.25:scan_name=257-0358,jd0609,40 2006.257.03:53:03.26:source=1424-418,142756.30,-420619.4,2000.0,ccw 2006.257.03:53:04.13#flagr#flagr/antenna,new-source 2006.257.03:53:04.13:checkk5 2006.257.03:53:04.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:53:04.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:53:05.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:53:05.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:53:06.13/chk_obsdata//k5ts1/T2570352??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.03:53:06.53/chk_obsdata//k5ts2/T2570352??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.03:53:06.93/chk_obsdata//k5ts3/T2570352??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.03:53:07.32/chk_obsdata//k5ts4/T2570352??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.03:53:08.06/k5log//k5ts1_log_newline 2006.257.03:53:08.78/k5log//k5ts2_log_newline 2006.257.03:53:09.55/k5log//k5ts3_log_newline 2006.257.03:53:10.27/k5log//k5ts4_log_newline 2006.257.03:53:10.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:53:10.29:setupk4=1 2006.257.03:53:10.29$setupk4/echo=on 2006.257.03:53:10.29$setupk4/pcalon 2006.257.03:53:10.29$pcalon/"no phase cal control is implemented here 2006.257.03:53:10.29$setupk4/"tpicd=stop 2006.257.03:53:10.29$setupk4/"rec=synch_on 2006.257.03:53:10.29$setupk4/"rec_mode=128 2006.257.03:53:10.29$setupk4/!* 2006.257.03:53:10.29$setupk4/recpk4 2006.257.03:53:10.29$recpk4/recpatch= 2006.257.03:53:10.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:53:10.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:53:10.29$setupk4/vck44 2006.257.03:53:10.29$vck44/valo=1,524.99 2006.257.03:53:10.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.03:53:10.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.03:53:10.29#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:10.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:10.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:10.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:10.29#ibcon#enter wrdev, iclass 35, count 0 2006.257.03:53:10.29#ibcon#first serial, iclass 35, count 0 2006.257.03:53:10.29#ibcon#enter sib2, iclass 35, count 0 2006.257.03:53:10.29#ibcon#flushed, iclass 35, count 0 2006.257.03:53:10.29#ibcon#about to write, iclass 35, count 0 2006.257.03:53:10.30#ibcon#wrote, iclass 35, count 0 2006.257.03:53:10.30#ibcon#about to read 3, iclass 35, count 0 2006.257.03:53:10.31#ibcon#read 3, iclass 35, count 0 2006.257.03:53:10.31#ibcon#about to read 4, iclass 35, count 0 2006.257.03:53:10.31#ibcon#read 4, iclass 35, count 0 2006.257.03:53:10.31#ibcon#about to read 5, iclass 35, count 0 2006.257.03:53:10.31#ibcon#read 5, iclass 35, count 0 2006.257.03:53:10.31#ibcon#about to read 6, iclass 35, count 0 2006.257.03:53:10.31#ibcon#read 6, iclass 35, count 0 2006.257.03:53:10.31#ibcon#end of sib2, iclass 35, count 0 2006.257.03:53:10.31#ibcon#*mode == 0, iclass 35, count 0 2006.257.03:53:10.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.03:53:10.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:53:10.31#ibcon#*before write, iclass 35, count 0 2006.257.03:53:10.31#ibcon#enter sib2, iclass 35, count 0 2006.257.03:53:10.31#ibcon#flushed, iclass 35, count 0 2006.257.03:53:10.31#ibcon#about to write, iclass 35, count 0 2006.257.03:53:10.31#ibcon#wrote, iclass 35, count 0 2006.257.03:53:10.31#ibcon#about to read 3, iclass 35, count 0 2006.257.03:53:10.36#ibcon#read 3, iclass 35, count 0 2006.257.03:53:10.36#ibcon#about to read 4, iclass 35, count 0 2006.257.03:53:10.36#ibcon#read 4, iclass 35, count 0 2006.257.03:53:10.36#ibcon#about to read 5, iclass 35, count 0 2006.257.03:53:10.36#ibcon#read 5, iclass 35, count 0 2006.257.03:53:10.36#ibcon#about to read 6, iclass 35, count 0 2006.257.03:53:10.36#ibcon#read 6, iclass 35, count 0 2006.257.03:53:10.36#ibcon#end of sib2, iclass 35, count 0 2006.257.03:53:10.36#ibcon#*after write, iclass 35, count 0 2006.257.03:53:10.36#ibcon#*before return 0, iclass 35, count 0 2006.257.03:53:10.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:10.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:10.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.03:53:10.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.03:53:10.36$vck44/va=1,8 2006.257.03:53:10.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.03:53:10.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.03:53:10.36#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:10.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:10.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:10.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:10.36#ibcon#enter wrdev, iclass 37, count 2 2006.257.03:53:10.36#ibcon#first serial, iclass 37, count 2 2006.257.03:53:10.36#ibcon#enter sib2, iclass 37, count 2 2006.257.03:53:10.36#ibcon#flushed, iclass 37, count 2 2006.257.03:53:10.36#ibcon#about to write, iclass 37, count 2 2006.257.03:53:10.36#ibcon#wrote, iclass 37, count 2 2006.257.03:53:10.36#ibcon#about to read 3, iclass 37, count 2 2006.257.03:53:10.38#ibcon#read 3, iclass 37, count 2 2006.257.03:53:10.38#ibcon#about to read 4, iclass 37, count 2 2006.257.03:53:10.38#ibcon#read 4, iclass 37, count 2 2006.257.03:53:10.38#ibcon#about to read 5, iclass 37, count 2 2006.257.03:53:10.38#ibcon#read 5, iclass 37, count 2 2006.257.03:53:10.38#ibcon#about to read 6, iclass 37, count 2 2006.257.03:53:10.38#ibcon#read 6, iclass 37, count 2 2006.257.03:53:10.38#ibcon#end of sib2, iclass 37, count 2 2006.257.03:53:10.38#ibcon#*mode == 0, iclass 37, count 2 2006.257.03:53:10.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.03:53:10.38#ibcon#[25=AT01-08\r\n] 2006.257.03:53:10.38#ibcon#*before write, iclass 37, count 2 2006.257.03:53:10.38#ibcon#enter sib2, iclass 37, count 2 2006.257.03:53:10.38#ibcon#flushed, iclass 37, count 2 2006.257.03:53:10.38#ibcon#about to write, iclass 37, count 2 2006.257.03:53:10.38#ibcon#wrote, iclass 37, count 2 2006.257.03:53:10.38#ibcon#about to read 3, iclass 37, count 2 2006.257.03:53:10.41#ibcon#read 3, iclass 37, count 2 2006.257.03:53:10.41#ibcon#about to read 4, iclass 37, count 2 2006.257.03:53:10.41#ibcon#read 4, iclass 37, count 2 2006.257.03:53:10.41#ibcon#about to read 5, iclass 37, count 2 2006.257.03:53:10.41#ibcon#read 5, iclass 37, count 2 2006.257.03:53:10.41#ibcon#about to read 6, iclass 37, count 2 2006.257.03:53:10.41#ibcon#read 6, iclass 37, count 2 2006.257.03:53:10.41#ibcon#end of sib2, iclass 37, count 2 2006.257.03:53:10.41#ibcon#*after write, iclass 37, count 2 2006.257.03:53:10.41#ibcon#*before return 0, iclass 37, count 2 2006.257.03:53:10.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:10.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:10.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.03:53:10.41#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:10.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:10.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:10.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:10.53#ibcon#enter wrdev, iclass 37, count 0 2006.257.03:53:10.53#ibcon#first serial, iclass 37, count 0 2006.257.03:53:10.53#ibcon#enter sib2, iclass 37, count 0 2006.257.03:53:10.53#ibcon#flushed, iclass 37, count 0 2006.257.03:53:10.53#ibcon#about to write, iclass 37, count 0 2006.257.03:53:10.53#ibcon#wrote, iclass 37, count 0 2006.257.03:53:10.53#ibcon#about to read 3, iclass 37, count 0 2006.257.03:53:10.55#ibcon#read 3, iclass 37, count 0 2006.257.03:53:10.55#ibcon#about to read 4, iclass 37, count 0 2006.257.03:53:10.55#ibcon#read 4, iclass 37, count 0 2006.257.03:53:10.55#ibcon#about to read 5, iclass 37, count 0 2006.257.03:53:10.55#ibcon#read 5, iclass 37, count 0 2006.257.03:53:10.55#ibcon#about to read 6, iclass 37, count 0 2006.257.03:53:10.55#ibcon#read 6, iclass 37, count 0 2006.257.03:53:10.55#ibcon#end of sib2, iclass 37, count 0 2006.257.03:53:10.55#ibcon#*mode == 0, iclass 37, count 0 2006.257.03:53:10.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.03:53:10.55#ibcon#[25=USB\r\n] 2006.257.03:53:10.55#ibcon#*before write, iclass 37, count 0 2006.257.03:53:10.55#ibcon#enter sib2, iclass 37, count 0 2006.257.03:53:10.55#ibcon#flushed, iclass 37, count 0 2006.257.03:53:10.55#ibcon#about to write, iclass 37, count 0 2006.257.03:53:10.55#ibcon#wrote, iclass 37, count 0 2006.257.03:53:10.55#ibcon#about to read 3, iclass 37, count 0 2006.257.03:53:10.58#ibcon#read 3, iclass 37, count 0 2006.257.03:53:10.58#ibcon#about to read 4, iclass 37, count 0 2006.257.03:53:10.58#ibcon#read 4, iclass 37, count 0 2006.257.03:53:10.58#ibcon#about to read 5, iclass 37, count 0 2006.257.03:53:10.58#ibcon#read 5, iclass 37, count 0 2006.257.03:53:10.58#ibcon#about to read 6, iclass 37, count 0 2006.257.03:53:10.58#ibcon#read 6, iclass 37, count 0 2006.257.03:53:10.58#ibcon#end of sib2, iclass 37, count 0 2006.257.03:53:10.58#ibcon#*after write, iclass 37, count 0 2006.257.03:53:10.58#ibcon#*before return 0, iclass 37, count 0 2006.257.03:53:10.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:10.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:10.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.03:53:10.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.03:53:10.58$vck44/valo=2,534.99 2006.257.03:53:10.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.03:53:10.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.03:53:10.58#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:10.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:10.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:10.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:10.58#ibcon#enter wrdev, iclass 39, count 0 2006.257.03:53:10.58#ibcon#first serial, iclass 39, count 0 2006.257.03:53:10.58#ibcon#enter sib2, iclass 39, count 0 2006.257.03:53:10.58#ibcon#flushed, iclass 39, count 0 2006.257.03:53:10.58#ibcon#about to write, iclass 39, count 0 2006.257.03:53:10.58#ibcon#wrote, iclass 39, count 0 2006.257.03:53:10.58#ibcon#about to read 3, iclass 39, count 0 2006.257.03:53:10.60#ibcon#read 3, iclass 39, count 0 2006.257.03:53:10.60#ibcon#about to read 4, iclass 39, count 0 2006.257.03:53:10.60#ibcon#read 4, iclass 39, count 0 2006.257.03:53:10.60#ibcon#about to read 5, iclass 39, count 0 2006.257.03:53:10.60#ibcon#read 5, iclass 39, count 0 2006.257.03:53:10.60#ibcon#about to read 6, iclass 39, count 0 2006.257.03:53:10.60#ibcon#read 6, iclass 39, count 0 2006.257.03:53:10.60#ibcon#end of sib2, iclass 39, count 0 2006.257.03:53:10.60#ibcon#*mode == 0, iclass 39, count 0 2006.257.03:53:10.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.03:53:10.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:53:10.60#ibcon#*before write, iclass 39, count 0 2006.257.03:53:10.60#ibcon#enter sib2, iclass 39, count 0 2006.257.03:53:10.60#ibcon#flushed, iclass 39, count 0 2006.257.03:53:10.60#ibcon#about to write, iclass 39, count 0 2006.257.03:53:10.60#ibcon#wrote, iclass 39, count 0 2006.257.03:53:10.60#ibcon#about to read 3, iclass 39, count 0 2006.257.03:53:10.64#ibcon#read 3, iclass 39, count 0 2006.257.03:53:10.64#ibcon#about to read 4, iclass 39, count 0 2006.257.03:53:10.64#ibcon#read 4, iclass 39, count 0 2006.257.03:53:10.64#ibcon#about to read 5, iclass 39, count 0 2006.257.03:53:10.64#ibcon#read 5, iclass 39, count 0 2006.257.03:53:10.64#ibcon#about to read 6, iclass 39, count 0 2006.257.03:53:10.64#ibcon#read 6, iclass 39, count 0 2006.257.03:53:10.64#ibcon#end of sib2, iclass 39, count 0 2006.257.03:53:10.64#ibcon#*after write, iclass 39, count 0 2006.257.03:53:10.64#ibcon#*before return 0, iclass 39, count 0 2006.257.03:53:10.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:10.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:10.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.03:53:10.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.03:53:10.64$vck44/va=2,7 2006.257.03:53:10.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.03:53:10.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.03:53:10.64#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:10.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:10.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:10.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:10.70#ibcon#enter wrdev, iclass 3, count 2 2006.257.03:53:10.70#ibcon#first serial, iclass 3, count 2 2006.257.03:53:10.70#ibcon#enter sib2, iclass 3, count 2 2006.257.03:53:10.70#ibcon#flushed, iclass 3, count 2 2006.257.03:53:10.70#ibcon#about to write, iclass 3, count 2 2006.257.03:53:10.70#ibcon#wrote, iclass 3, count 2 2006.257.03:53:10.70#ibcon#about to read 3, iclass 3, count 2 2006.257.03:53:10.72#ibcon#read 3, iclass 3, count 2 2006.257.03:53:10.72#ibcon#about to read 4, iclass 3, count 2 2006.257.03:53:10.72#ibcon#read 4, iclass 3, count 2 2006.257.03:53:10.72#ibcon#about to read 5, iclass 3, count 2 2006.257.03:53:10.72#ibcon#read 5, iclass 3, count 2 2006.257.03:53:10.72#ibcon#about to read 6, iclass 3, count 2 2006.257.03:53:10.72#ibcon#read 6, iclass 3, count 2 2006.257.03:53:10.72#ibcon#end of sib2, iclass 3, count 2 2006.257.03:53:10.72#ibcon#*mode == 0, iclass 3, count 2 2006.257.03:53:10.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.03:53:10.72#ibcon#[25=AT02-07\r\n] 2006.257.03:53:10.72#ibcon#*before write, iclass 3, count 2 2006.257.03:53:10.72#ibcon#enter sib2, iclass 3, count 2 2006.257.03:53:10.72#ibcon#flushed, iclass 3, count 2 2006.257.03:53:10.72#ibcon#about to write, iclass 3, count 2 2006.257.03:53:10.72#ibcon#wrote, iclass 3, count 2 2006.257.03:53:10.72#ibcon#about to read 3, iclass 3, count 2 2006.257.03:53:10.75#ibcon#read 3, iclass 3, count 2 2006.257.03:53:10.75#ibcon#about to read 4, iclass 3, count 2 2006.257.03:53:10.75#ibcon#read 4, iclass 3, count 2 2006.257.03:53:10.75#ibcon#about to read 5, iclass 3, count 2 2006.257.03:53:10.75#ibcon#read 5, iclass 3, count 2 2006.257.03:53:10.75#ibcon#about to read 6, iclass 3, count 2 2006.257.03:53:10.75#ibcon#read 6, iclass 3, count 2 2006.257.03:53:10.75#ibcon#end of sib2, iclass 3, count 2 2006.257.03:53:10.75#ibcon#*after write, iclass 3, count 2 2006.257.03:53:10.75#ibcon#*before return 0, iclass 3, count 2 2006.257.03:53:10.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:10.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:10.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.03:53:10.75#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:10.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:10.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:10.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:10.87#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:53:10.87#ibcon#first serial, iclass 3, count 0 2006.257.03:53:10.87#ibcon#enter sib2, iclass 3, count 0 2006.257.03:53:10.87#ibcon#flushed, iclass 3, count 0 2006.257.03:53:10.87#ibcon#about to write, iclass 3, count 0 2006.257.03:53:10.87#ibcon#wrote, iclass 3, count 0 2006.257.03:53:10.87#ibcon#about to read 3, iclass 3, count 0 2006.257.03:53:10.89#ibcon#read 3, iclass 3, count 0 2006.257.03:53:10.89#ibcon#about to read 4, iclass 3, count 0 2006.257.03:53:10.89#ibcon#read 4, iclass 3, count 0 2006.257.03:53:10.89#ibcon#about to read 5, iclass 3, count 0 2006.257.03:53:10.89#ibcon#read 5, iclass 3, count 0 2006.257.03:53:10.89#ibcon#about to read 6, iclass 3, count 0 2006.257.03:53:10.89#ibcon#read 6, iclass 3, count 0 2006.257.03:53:10.89#ibcon#end of sib2, iclass 3, count 0 2006.257.03:53:10.89#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:53:10.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:53:10.89#ibcon#[25=USB\r\n] 2006.257.03:53:10.89#ibcon#*before write, iclass 3, count 0 2006.257.03:53:10.89#ibcon#enter sib2, iclass 3, count 0 2006.257.03:53:10.89#ibcon#flushed, iclass 3, count 0 2006.257.03:53:10.89#ibcon#about to write, iclass 3, count 0 2006.257.03:53:10.89#ibcon#wrote, iclass 3, count 0 2006.257.03:53:10.89#ibcon#about to read 3, iclass 3, count 0 2006.257.03:53:10.92#ibcon#read 3, iclass 3, count 0 2006.257.03:53:10.92#ibcon#about to read 4, iclass 3, count 0 2006.257.03:53:10.92#ibcon#read 4, iclass 3, count 0 2006.257.03:53:10.92#ibcon#about to read 5, iclass 3, count 0 2006.257.03:53:10.92#ibcon#read 5, iclass 3, count 0 2006.257.03:53:10.92#ibcon#about to read 6, iclass 3, count 0 2006.257.03:53:10.92#ibcon#read 6, iclass 3, count 0 2006.257.03:53:10.92#ibcon#end of sib2, iclass 3, count 0 2006.257.03:53:10.92#ibcon#*after write, iclass 3, count 0 2006.257.03:53:10.92#ibcon#*before return 0, iclass 3, count 0 2006.257.03:53:10.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:10.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:10.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:53:10.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:53:10.92$vck44/valo=3,564.99 2006.257.03:53:10.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.03:53:10.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.03:53:10.92#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:10.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:10.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:10.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:10.92#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:53:10.92#ibcon#first serial, iclass 5, count 0 2006.257.03:53:10.92#ibcon#enter sib2, iclass 5, count 0 2006.257.03:53:10.92#ibcon#flushed, iclass 5, count 0 2006.257.03:53:10.92#ibcon#about to write, iclass 5, count 0 2006.257.03:53:10.92#ibcon#wrote, iclass 5, count 0 2006.257.03:53:10.92#ibcon#about to read 3, iclass 5, count 0 2006.257.03:53:10.94#ibcon#read 3, iclass 5, count 0 2006.257.03:53:10.94#ibcon#about to read 4, iclass 5, count 0 2006.257.03:53:10.94#ibcon#read 4, iclass 5, count 0 2006.257.03:53:10.94#ibcon#about to read 5, iclass 5, count 0 2006.257.03:53:10.94#ibcon#read 5, iclass 5, count 0 2006.257.03:53:10.94#ibcon#about to read 6, iclass 5, count 0 2006.257.03:53:10.94#ibcon#read 6, iclass 5, count 0 2006.257.03:53:10.94#ibcon#end of sib2, iclass 5, count 0 2006.257.03:53:10.94#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:53:10.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:53:10.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:53:10.94#ibcon#*before write, iclass 5, count 0 2006.257.03:53:10.94#ibcon#enter sib2, iclass 5, count 0 2006.257.03:53:10.94#ibcon#flushed, iclass 5, count 0 2006.257.03:53:10.94#ibcon#about to write, iclass 5, count 0 2006.257.03:53:10.94#ibcon#wrote, iclass 5, count 0 2006.257.03:53:10.94#ibcon#about to read 3, iclass 5, count 0 2006.257.03:53:10.98#ibcon#read 3, iclass 5, count 0 2006.257.03:53:10.98#ibcon#about to read 4, iclass 5, count 0 2006.257.03:53:10.98#ibcon#read 4, iclass 5, count 0 2006.257.03:53:10.98#ibcon#about to read 5, iclass 5, count 0 2006.257.03:53:10.98#ibcon#read 5, iclass 5, count 0 2006.257.03:53:10.98#ibcon#about to read 6, iclass 5, count 0 2006.257.03:53:10.98#ibcon#read 6, iclass 5, count 0 2006.257.03:53:10.98#ibcon#end of sib2, iclass 5, count 0 2006.257.03:53:10.98#ibcon#*after write, iclass 5, count 0 2006.257.03:53:10.98#ibcon#*before return 0, iclass 5, count 0 2006.257.03:53:10.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:10.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:10.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:53:10.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:53:10.98$vck44/va=3,8 2006.257.03:53:10.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.03:53:10.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.03:53:10.98#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:10.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:11.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:11.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:11.04#ibcon#enter wrdev, iclass 7, count 2 2006.257.03:53:11.04#ibcon#first serial, iclass 7, count 2 2006.257.03:53:11.04#ibcon#enter sib2, iclass 7, count 2 2006.257.03:53:11.04#ibcon#flushed, iclass 7, count 2 2006.257.03:53:11.04#ibcon#about to write, iclass 7, count 2 2006.257.03:53:11.04#ibcon#wrote, iclass 7, count 2 2006.257.03:53:11.04#ibcon#about to read 3, iclass 7, count 2 2006.257.03:53:11.06#ibcon#read 3, iclass 7, count 2 2006.257.03:53:11.06#ibcon#about to read 4, iclass 7, count 2 2006.257.03:53:11.06#ibcon#read 4, iclass 7, count 2 2006.257.03:53:11.06#ibcon#about to read 5, iclass 7, count 2 2006.257.03:53:11.06#ibcon#read 5, iclass 7, count 2 2006.257.03:53:11.06#ibcon#about to read 6, iclass 7, count 2 2006.257.03:53:11.06#ibcon#read 6, iclass 7, count 2 2006.257.03:53:11.06#ibcon#end of sib2, iclass 7, count 2 2006.257.03:53:11.06#ibcon#*mode == 0, iclass 7, count 2 2006.257.03:53:11.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.03:53:11.06#ibcon#[25=AT03-08\r\n] 2006.257.03:53:11.06#ibcon#*before write, iclass 7, count 2 2006.257.03:53:11.06#ibcon#enter sib2, iclass 7, count 2 2006.257.03:53:11.06#ibcon#flushed, iclass 7, count 2 2006.257.03:53:11.06#ibcon#about to write, iclass 7, count 2 2006.257.03:53:11.06#ibcon#wrote, iclass 7, count 2 2006.257.03:53:11.06#ibcon#about to read 3, iclass 7, count 2 2006.257.03:53:11.09#ibcon#read 3, iclass 7, count 2 2006.257.03:53:11.09#ibcon#about to read 4, iclass 7, count 2 2006.257.03:53:11.09#ibcon#read 4, iclass 7, count 2 2006.257.03:53:11.09#ibcon#about to read 5, iclass 7, count 2 2006.257.03:53:11.09#ibcon#read 5, iclass 7, count 2 2006.257.03:53:11.09#ibcon#about to read 6, iclass 7, count 2 2006.257.03:53:11.09#ibcon#read 6, iclass 7, count 2 2006.257.03:53:11.09#ibcon#end of sib2, iclass 7, count 2 2006.257.03:53:11.09#ibcon#*after write, iclass 7, count 2 2006.257.03:53:11.09#ibcon#*before return 0, iclass 7, count 2 2006.257.03:53:11.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:11.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:11.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.03:53:11.09#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:11.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:11.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:11.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:11.21#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:53:11.21#ibcon#first serial, iclass 7, count 0 2006.257.03:53:11.21#ibcon#enter sib2, iclass 7, count 0 2006.257.03:53:11.21#ibcon#flushed, iclass 7, count 0 2006.257.03:53:11.21#ibcon#about to write, iclass 7, count 0 2006.257.03:53:11.21#ibcon#wrote, iclass 7, count 0 2006.257.03:53:11.21#ibcon#about to read 3, iclass 7, count 0 2006.257.03:53:11.23#ibcon#read 3, iclass 7, count 0 2006.257.03:53:11.23#ibcon#about to read 4, iclass 7, count 0 2006.257.03:53:11.23#ibcon#read 4, iclass 7, count 0 2006.257.03:53:11.23#ibcon#about to read 5, iclass 7, count 0 2006.257.03:53:11.23#ibcon#read 5, iclass 7, count 0 2006.257.03:53:11.23#ibcon#about to read 6, iclass 7, count 0 2006.257.03:53:11.23#ibcon#read 6, iclass 7, count 0 2006.257.03:53:11.23#ibcon#end of sib2, iclass 7, count 0 2006.257.03:53:11.23#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:53:11.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:53:11.23#ibcon#[25=USB\r\n] 2006.257.03:53:11.23#ibcon#*before write, iclass 7, count 0 2006.257.03:53:11.23#ibcon#enter sib2, iclass 7, count 0 2006.257.03:53:11.23#ibcon#flushed, iclass 7, count 0 2006.257.03:53:11.23#ibcon#about to write, iclass 7, count 0 2006.257.03:53:11.23#ibcon#wrote, iclass 7, count 0 2006.257.03:53:11.23#ibcon#about to read 3, iclass 7, count 0 2006.257.03:53:11.26#ibcon#read 3, iclass 7, count 0 2006.257.03:53:11.26#ibcon#about to read 4, iclass 7, count 0 2006.257.03:53:11.26#ibcon#read 4, iclass 7, count 0 2006.257.03:53:11.26#ibcon#about to read 5, iclass 7, count 0 2006.257.03:53:11.26#ibcon#read 5, iclass 7, count 0 2006.257.03:53:11.26#ibcon#about to read 6, iclass 7, count 0 2006.257.03:53:11.26#ibcon#read 6, iclass 7, count 0 2006.257.03:53:11.26#ibcon#end of sib2, iclass 7, count 0 2006.257.03:53:11.26#ibcon#*after write, iclass 7, count 0 2006.257.03:53:11.26#ibcon#*before return 0, iclass 7, count 0 2006.257.03:53:11.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:11.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:11.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:53:11.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:53:11.26$vck44/valo=4,624.99 2006.257.03:53:11.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.03:53:11.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.03:53:11.26#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:11.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:11.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:11.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:11.26#ibcon#enter wrdev, iclass 11, count 0 2006.257.03:53:11.26#ibcon#first serial, iclass 11, count 0 2006.257.03:53:11.26#ibcon#enter sib2, iclass 11, count 0 2006.257.03:53:11.26#ibcon#flushed, iclass 11, count 0 2006.257.03:53:11.26#ibcon#about to write, iclass 11, count 0 2006.257.03:53:11.26#ibcon#wrote, iclass 11, count 0 2006.257.03:53:11.26#ibcon#about to read 3, iclass 11, count 0 2006.257.03:53:11.28#ibcon#read 3, iclass 11, count 0 2006.257.03:53:11.28#ibcon#about to read 4, iclass 11, count 0 2006.257.03:53:11.28#ibcon#read 4, iclass 11, count 0 2006.257.03:53:11.28#ibcon#about to read 5, iclass 11, count 0 2006.257.03:53:11.28#ibcon#read 5, iclass 11, count 0 2006.257.03:53:11.28#ibcon#about to read 6, iclass 11, count 0 2006.257.03:53:11.28#ibcon#read 6, iclass 11, count 0 2006.257.03:53:11.28#ibcon#end of sib2, iclass 11, count 0 2006.257.03:53:11.28#ibcon#*mode == 0, iclass 11, count 0 2006.257.03:53:11.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.03:53:11.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:53:11.28#ibcon#*before write, iclass 11, count 0 2006.257.03:53:11.28#ibcon#enter sib2, iclass 11, count 0 2006.257.03:53:11.28#ibcon#flushed, iclass 11, count 0 2006.257.03:53:11.28#ibcon#about to write, iclass 11, count 0 2006.257.03:53:11.28#ibcon#wrote, iclass 11, count 0 2006.257.03:53:11.28#ibcon#about to read 3, iclass 11, count 0 2006.257.03:53:11.32#ibcon#read 3, iclass 11, count 0 2006.257.03:53:11.32#ibcon#about to read 4, iclass 11, count 0 2006.257.03:53:11.32#ibcon#read 4, iclass 11, count 0 2006.257.03:53:11.32#ibcon#about to read 5, iclass 11, count 0 2006.257.03:53:11.32#ibcon#read 5, iclass 11, count 0 2006.257.03:53:11.32#ibcon#about to read 6, iclass 11, count 0 2006.257.03:53:11.32#ibcon#read 6, iclass 11, count 0 2006.257.03:53:11.32#ibcon#end of sib2, iclass 11, count 0 2006.257.03:53:11.32#ibcon#*after write, iclass 11, count 0 2006.257.03:53:11.32#ibcon#*before return 0, iclass 11, count 0 2006.257.03:53:11.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:11.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:11.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.03:53:11.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.03:53:11.32$vck44/va=4,7 2006.257.03:53:11.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.03:53:11.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.03:53:11.32#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:11.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:11.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:11.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:11.38#ibcon#enter wrdev, iclass 13, count 2 2006.257.03:53:11.38#ibcon#first serial, iclass 13, count 2 2006.257.03:53:11.38#ibcon#enter sib2, iclass 13, count 2 2006.257.03:53:11.38#ibcon#flushed, iclass 13, count 2 2006.257.03:53:11.38#ibcon#about to write, iclass 13, count 2 2006.257.03:53:11.38#ibcon#wrote, iclass 13, count 2 2006.257.03:53:11.38#ibcon#about to read 3, iclass 13, count 2 2006.257.03:53:11.40#ibcon#read 3, iclass 13, count 2 2006.257.03:53:11.40#ibcon#about to read 4, iclass 13, count 2 2006.257.03:53:11.40#ibcon#read 4, iclass 13, count 2 2006.257.03:53:11.40#ibcon#about to read 5, iclass 13, count 2 2006.257.03:53:11.40#ibcon#read 5, iclass 13, count 2 2006.257.03:53:11.40#ibcon#about to read 6, iclass 13, count 2 2006.257.03:53:11.40#ibcon#read 6, iclass 13, count 2 2006.257.03:53:11.40#ibcon#end of sib2, iclass 13, count 2 2006.257.03:53:11.40#ibcon#*mode == 0, iclass 13, count 2 2006.257.03:53:11.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.03:53:11.40#ibcon#[25=AT04-07\r\n] 2006.257.03:53:11.40#ibcon#*before write, iclass 13, count 2 2006.257.03:53:11.40#ibcon#enter sib2, iclass 13, count 2 2006.257.03:53:11.40#ibcon#flushed, iclass 13, count 2 2006.257.03:53:11.40#ibcon#about to write, iclass 13, count 2 2006.257.03:53:11.40#ibcon#wrote, iclass 13, count 2 2006.257.03:53:11.40#ibcon#about to read 3, iclass 13, count 2 2006.257.03:53:11.43#ibcon#read 3, iclass 13, count 2 2006.257.03:53:11.43#ibcon#about to read 4, iclass 13, count 2 2006.257.03:53:11.43#ibcon#read 4, iclass 13, count 2 2006.257.03:53:11.43#ibcon#about to read 5, iclass 13, count 2 2006.257.03:53:11.43#ibcon#read 5, iclass 13, count 2 2006.257.03:53:11.43#ibcon#about to read 6, iclass 13, count 2 2006.257.03:53:11.43#ibcon#read 6, iclass 13, count 2 2006.257.03:53:11.43#ibcon#end of sib2, iclass 13, count 2 2006.257.03:53:11.43#ibcon#*after write, iclass 13, count 2 2006.257.03:53:11.43#ibcon#*before return 0, iclass 13, count 2 2006.257.03:53:11.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:11.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:11.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.03:53:11.43#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:11.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:11.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:11.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:11.55#ibcon#enter wrdev, iclass 13, count 0 2006.257.03:53:11.55#ibcon#first serial, iclass 13, count 0 2006.257.03:53:11.55#ibcon#enter sib2, iclass 13, count 0 2006.257.03:53:11.55#ibcon#flushed, iclass 13, count 0 2006.257.03:53:11.55#ibcon#about to write, iclass 13, count 0 2006.257.03:53:11.55#ibcon#wrote, iclass 13, count 0 2006.257.03:53:11.55#ibcon#about to read 3, iclass 13, count 0 2006.257.03:53:11.57#ibcon#read 3, iclass 13, count 0 2006.257.03:53:11.57#ibcon#about to read 4, iclass 13, count 0 2006.257.03:53:11.57#ibcon#read 4, iclass 13, count 0 2006.257.03:53:11.57#ibcon#about to read 5, iclass 13, count 0 2006.257.03:53:11.57#ibcon#read 5, iclass 13, count 0 2006.257.03:53:11.57#ibcon#about to read 6, iclass 13, count 0 2006.257.03:53:11.57#ibcon#read 6, iclass 13, count 0 2006.257.03:53:11.57#ibcon#end of sib2, iclass 13, count 0 2006.257.03:53:11.57#ibcon#*mode == 0, iclass 13, count 0 2006.257.03:53:11.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.03:53:11.57#ibcon#[25=USB\r\n] 2006.257.03:53:11.57#ibcon#*before write, iclass 13, count 0 2006.257.03:53:11.57#ibcon#enter sib2, iclass 13, count 0 2006.257.03:53:11.57#ibcon#flushed, iclass 13, count 0 2006.257.03:53:11.57#ibcon#about to write, iclass 13, count 0 2006.257.03:53:11.57#ibcon#wrote, iclass 13, count 0 2006.257.03:53:11.57#ibcon#about to read 3, iclass 13, count 0 2006.257.03:53:11.60#ibcon#read 3, iclass 13, count 0 2006.257.03:53:11.60#ibcon#about to read 4, iclass 13, count 0 2006.257.03:53:11.60#ibcon#read 4, iclass 13, count 0 2006.257.03:53:11.60#ibcon#about to read 5, iclass 13, count 0 2006.257.03:53:11.60#ibcon#read 5, iclass 13, count 0 2006.257.03:53:11.60#ibcon#about to read 6, iclass 13, count 0 2006.257.03:53:11.60#ibcon#read 6, iclass 13, count 0 2006.257.03:53:11.60#ibcon#end of sib2, iclass 13, count 0 2006.257.03:53:11.60#ibcon#*after write, iclass 13, count 0 2006.257.03:53:11.60#ibcon#*before return 0, iclass 13, count 0 2006.257.03:53:11.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:11.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:11.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.03:53:11.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.03:53:11.60$vck44/valo=5,734.99 2006.257.03:53:11.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.03:53:11.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.03:53:11.60#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:11.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:11.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:11.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:11.60#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:53:11.60#ibcon#first serial, iclass 15, count 0 2006.257.03:53:11.60#ibcon#enter sib2, iclass 15, count 0 2006.257.03:53:11.60#ibcon#flushed, iclass 15, count 0 2006.257.03:53:11.60#ibcon#about to write, iclass 15, count 0 2006.257.03:53:11.60#ibcon#wrote, iclass 15, count 0 2006.257.03:53:11.60#ibcon#about to read 3, iclass 15, count 0 2006.257.03:53:11.62#ibcon#read 3, iclass 15, count 0 2006.257.03:53:11.62#ibcon#about to read 4, iclass 15, count 0 2006.257.03:53:11.62#ibcon#read 4, iclass 15, count 0 2006.257.03:53:11.62#ibcon#about to read 5, iclass 15, count 0 2006.257.03:53:11.62#ibcon#read 5, iclass 15, count 0 2006.257.03:53:11.62#ibcon#about to read 6, iclass 15, count 0 2006.257.03:53:11.62#ibcon#read 6, iclass 15, count 0 2006.257.03:53:11.62#ibcon#end of sib2, iclass 15, count 0 2006.257.03:53:11.62#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:53:11.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:53:11.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:53:11.62#ibcon#*before write, iclass 15, count 0 2006.257.03:53:11.62#ibcon#enter sib2, iclass 15, count 0 2006.257.03:53:11.62#ibcon#flushed, iclass 15, count 0 2006.257.03:53:11.62#ibcon#about to write, iclass 15, count 0 2006.257.03:53:11.62#ibcon#wrote, iclass 15, count 0 2006.257.03:53:11.62#ibcon#about to read 3, iclass 15, count 0 2006.257.03:53:11.66#ibcon#read 3, iclass 15, count 0 2006.257.03:53:11.66#ibcon#about to read 4, iclass 15, count 0 2006.257.03:53:11.66#ibcon#read 4, iclass 15, count 0 2006.257.03:53:11.66#ibcon#about to read 5, iclass 15, count 0 2006.257.03:53:11.66#ibcon#read 5, iclass 15, count 0 2006.257.03:53:11.66#ibcon#about to read 6, iclass 15, count 0 2006.257.03:53:11.66#ibcon#read 6, iclass 15, count 0 2006.257.03:53:11.66#ibcon#end of sib2, iclass 15, count 0 2006.257.03:53:11.66#ibcon#*after write, iclass 15, count 0 2006.257.03:53:11.66#ibcon#*before return 0, iclass 15, count 0 2006.257.03:53:11.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:11.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:11.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:53:11.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:53:11.66$vck44/va=5,4 2006.257.03:53:11.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.03:53:11.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.03:53:11.66#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:11.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:11.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:11.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:11.72#ibcon#enter wrdev, iclass 17, count 2 2006.257.03:53:11.72#ibcon#first serial, iclass 17, count 2 2006.257.03:53:11.72#ibcon#enter sib2, iclass 17, count 2 2006.257.03:53:11.72#ibcon#flushed, iclass 17, count 2 2006.257.03:53:11.72#ibcon#about to write, iclass 17, count 2 2006.257.03:53:11.72#ibcon#wrote, iclass 17, count 2 2006.257.03:53:11.72#ibcon#about to read 3, iclass 17, count 2 2006.257.03:53:11.74#ibcon#read 3, iclass 17, count 2 2006.257.03:53:11.74#ibcon#about to read 4, iclass 17, count 2 2006.257.03:53:11.74#ibcon#read 4, iclass 17, count 2 2006.257.03:53:11.74#ibcon#about to read 5, iclass 17, count 2 2006.257.03:53:11.74#ibcon#read 5, iclass 17, count 2 2006.257.03:53:11.74#ibcon#about to read 6, iclass 17, count 2 2006.257.03:53:11.74#ibcon#read 6, iclass 17, count 2 2006.257.03:53:11.74#ibcon#end of sib2, iclass 17, count 2 2006.257.03:53:11.74#ibcon#*mode == 0, iclass 17, count 2 2006.257.03:53:11.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.03:53:11.74#ibcon#[25=AT05-04\r\n] 2006.257.03:53:11.74#ibcon#*before write, iclass 17, count 2 2006.257.03:53:11.74#ibcon#enter sib2, iclass 17, count 2 2006.257.03:53:11.74#ibcon#flushed, iclass 17, count 2 2006.257.03:53:11.74#ibcon#about to write, iclass 17, count 2 2006.257.03:53:11.74#ibcon#wrote, iclass 17, count 2 2006.257.03:53:11.74#ibcon#about to read 3, iclass 17, count 2 2006.257.03:53:11.77#ibcon#read 3, iclass 17, count 2 2006.257.03:53:11.77#ibcon#about to read 4, iclass 17, count 2 2006.257.03:53:11.77#ibcon#read 4, iclass 17, count 2 2006.257.03:53:11.77#ibcon#about to read 5, iclass 17, count 2 2006.257.03:53:11.77#ibcon#read 5, iclass 17, count 2 2006.257.03:53:11.77#ibcon#about to read 6, iclass 17, count 2 2006.257.03:53:11.77#ibcon#read 6, iclass 17, count 2 2006.257.03:53:11.77#ibcon#end of sib2, iclass 17, count 2 2006.257.03:53:11.77#ibcon#*after write, iclass 17, count 2 2006.257.03:53:11.77#ibcon#*before return 0, iclass 17, count 2 2006.257.03:53:11.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:11.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:11.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.03:53:11.77#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:11.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:11.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:11.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:11.89#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:53:11.89#ibcon#first serial, iclass 17, count 0 2006.257.03:53:11.89#ibcon#enter sib2, iclass 17, count 0 2006.257.03:53:11.89#ibcon#flushed, iclass 17, count 0 2006.257.03:53:11.89#ibcon#about to write, iclass 17, count 0 2006.257.03:53:11.89#ibcon#wrote, iclass 17, count 0 2006.257.03:53:11.89#ibcon#about to read 3, iclass 17, count 0 2006.257.03:53:11.91#ibcon#read 3, iclass 17, count 0 2006.257.03:53:11.91#ibcon#about to read 4, iclass 17, count 0 2006.257.03:53:11.91#ibcon#read 4, iclass 17, count 0 2006.257.03:53:11.91#ibcon#about to read 5, iclass 17, count 0 2006.257.03:53:11.91#ibcon#read 5, iclass 17, count 0 2006.257.03:53:11.91#ibcon#about to read 6, iclass 17, count 0 2006.257.03:53:11.91#ibcon#read 6, iclass 17, count 0 2006.257.03:53:11.91#ibcon#end of sib2, iclass 17, count 0 2006.257.03:53:11.91#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:53:11.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:53:11.91#ibcon#[25=USB\r\n] 2006.257.03:53:11.91#ibcon#*before write, iclass 17, count 0 2006.257.03:53:11.91#ibcon#enter sib2, iclass 17, count 0 2006.257.03:53:11.91#ibcon#flushed, iclass 17, count 0 2006.257.03:53:11.91#ibcon#about to write, iclass 17, count 0 2006.257.03:53:11.91#ibcon#wrote, iclass 17, count 0 2006.257.03:53:11.91#ibcon#about to read 3, iclass 17, count 0 2006.257.03:53:11.94#ibcon#read 3, iclass 17, count 0 2006.257.03:53:11.94#ibcon#about to read 4, iclass 17, count 0 2006.257.03:53:11.94#ibcon#read 4, iclass 17, count 0 2006.257.03:53:11.94#ibcon#about to read 5, iclass 17, count 0 2006.257.03:53:11.94#ibcon#read 5, iclass 17, count 0 2006.257.03:53:11.94#ibcon#about to read 6, iclass 17, count 0 2006.257.03:53:11.94#ibcon#read 6, iclass 17, count 0 2006.257.03:53:11.94#ibcon#end of sib2, iclass 17, count 0 2006.257.03:53:11.94#ibcon#*after write, iclass 17, count 0 2006.257.03:53:11.94#ibcon#*before return 0, iclass 17, count 0 2006.257.03:53:11.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:11.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:11.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:53:11.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:53:11.94$vck44/valo=6,814.99 2006.257.03:53:11.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.03:53:11.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.03:53:11.94#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:11.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:11.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:11.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:11.94#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:53:11.94#ibcon#first serial, iclass 19, count 0 2006.257.03:53:11.94#ibcon#enter sib2, iclass 19, count 0 2006.257.03:53:11.94#ibcon#flushed, iclass 19, count 0 2006.257.03:53:11.94#ibcon#about to write, iclass 19, count 0 2006.257.03:53:11.94#ibcon#wrote, iclass 19, count 0 2006.257.03:53:11.94#ibcon#about to read 3, iclass 19, count 0 2006.257.03:53:11.96#ibcon#read 3, iclass 19, count 0 2006.257.03:53:11.96#ibcon#about to read 4, iclass 19, count 0 2006.257.03:53:11.96#ibcon#read 4, iclass 19, count 0 2006.257.03:53:11.96#ibcon#about to read 5, iclass 19, count 0 2006.257.03:53:11.96#ibcon#read 5, iclass 19, count 0 2006.257.03:53:11.96#ibcon#about to read 6, iclass 19, count 0 2006.257.03:53:11.96#ibcon#read 6, iclass 19, count 0 2006.257.03:53:11.96#ibcon#end of sib2, iclass 19, count 0 2006.257.03:53:11.96#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:53:11.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:53:11.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:53:11.96#ibcon#*before write, iclass 19, count 0 2006.257.03:53:11.96#ibcon#enter sib2, iclass 19, count 0 2006.257.03:53:11.96#ibcon#flushed, iclass 19, count 0 2006.257.03:53:11.96#ibcon#about to write, iclass 19, count 0 2006.257.03:53:11.96#ibcon#wrote, iclass 19, count 0 2006.257.03:53:11.96#ibcon#about to read 3, iclass 19, count 0 2006.257.03:53:12.00#ibcon#read 3, iclass 19, count 0 2006.257.03:53:12.00#ibcon#about to read 4, iclass 19, count 0 2006.257.03:53:12.00#ibcon#read 4, iclass 19, count 0 2006.257.03:53:12.00#ibcon#about to read 5, iclass 19, count 0 2006.257.03:53:12.00#ibcon#read 5, iclass 19, count 0 2006.257.03:53:12.00#ibcon#about to read 6, iclass 19, count 0 2006.257.03:53:12.00#ibcon#read 6, iclass 19, count 0 2006.257.03:53:12.00#ibcon#end of sib2, iclass 19, count 0 2006.257.03:53:12.00#ibcon#*after write, iclass 19, count 0 2006.257.03:53:12.00#ibcon#*before return 0, iclass 19, count 0 2006.257.03:53:12.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:12.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:12.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:53:12.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:53:12.00$vck44/va=6,4 2006.257.03:53:12.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.03:53:12.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.03:53:12.00#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:12.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:12.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:12.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:12.06#ibcon#enter wrdev, iclass 21, count 2 2006.257.03:53:12.06#ibcon#first serial, iclass 21, count 2 2006.257.03:53:12.06#ibcon#enter sib2, iclass 21, count 2 2006.257.03:53:12.06#ibcon#flushed, iclass 21, count 2 2006.257.03:53:12.06#ibcon#about to write, iclass 21, count 2 2006.257.03:53:12.06#ibcon#wrote, iclass 21, count 2 2006.257.03:53:12.06#ibcon#about to read 3, iclass 21, count 2 2006.257.03:53:12.08#ibcon#read 3, iclass 21, count 2 2006.257.03:53:12.08#ibcon#about to read 4, iclass 21, count 2 2006.257.03:53:12.08#ibcon#read 4, iclass 21, count 2 2006.257.03:53:12.08#ibcon#about to read 5, iclass 21, count 2 2006.257.03:53:12.08#ibcon#read 5, iclass 21, count 2 2006.257.03:53:12.08#ibcon#about to read 6, iclass 21, count 2 2006.257.03:53:12.08#ibcon#read 6, iclass 21, count 2 2006.257.03:53:12.08#ibcon#end of sib2, iclass 21, count 2 2006.257.03:53:12.08#ibcon#*mode == 0, iclass 21, count 2 2006.257.03:53:12.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.03:53:12.08#ibcon#[25=AT06-04\r\n] 2006.257.03:53:12.08#ibcon#*before write, iclass 21, count 2 2006.257.03:53:12.08#ibcon#enter sib2, iclass 21, count 2 2006.257.03:53:12.08#ibcon#flushed, iclass 21, count 2 2006.257.03:53:12.08#ibcon#about to write, iclass 21, count 2 2006.257.03:53:12.08#ibcon#wrote, iclass 21, count 2 2006.257.03:53:12.08#ibcon#about to read 3, iclass 21, count 2 2006.257.03:53:12.11#ibcon#read 3, iclass 21, count 2 2006.257.03:53:12.11#ibcon#about to read 4, iclass 21, count 2 2006.257.03:53:12.11#ibcon#read 4, iclass 21, count 2 2006.257.03:53:12.11#ibcon#about to read 5, iclass 21, count 2 2006.257.03:53:12.11#ibcon#read 5, iclass 21, count 2 2006.257.03:53:12.11#ibcon#about to read 6, iclass 21, count 2 2006.257.03:53:12.11#ibcon#read 6, iclass 21, count 2 2006.257.03:53:12.11#ibcon#end of sib2, iclass 21, count 2 2006.257.03:53:12.11#ibcon#*after write, iclass 21, count 2 2006.257.03:53:12.11#ibcon#*before return 0, iclass 21, count 2 2006.257.03:53:12.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:12.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:12.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.03:53:12.11#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:12.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:12.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:12.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:12.23#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:53:12.23#ibcon#first serial, iclass 21, count 0 2006.257.03:53:12.23#ibcon#enter sib2, iclass 21, count 0 2006.257.03:53:12.23#ibcon#flushed, iclass 21, count 0 2006.257.03:53:12.23#ibcon#about to write, iclass 21, count 0 2006.257.03:53:12.23#ibcon#wrote, iclass 21, count 0 2006.257.03:53:12.23#ibcon#about to read 3, iclass 21, count 0 2006.257.03:53:12.25#ibcon#read 3, iclass 21, count 0 2006.257.03:53:12.25#ibcon#about to read 4, iclass 21, count 0 2006.257.03:53:12.25#ibcon#read 4, iclass 21, count 0 2006.257.03:53:12.25#ibcon#about to read 5, iclass 21, count 0 2006.257.03:53:12.25#ibcon#read 5, iclass 21, count 0 2006.257.03:53:12.25#ibcon#about to read 6, iclass 21, count 0 2006.257.03:53:12.25#ibcon#read 6, iclass 21, count 0 2006.257.03:53:12.25#ibcon#end of sib2, iclass 21, count 0 2006.257.03:53:12.25#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:53:12.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:53:12.25#ibcon#[25=USB\r\n] 2006.257.03:53:12.25#ibcon#*before write, iclass 21, count 0 2006.257.03:53:12.25#ibcon#enter sib2, iclass 21, count 0 2006.257.03:53:12.25#ibcon#flushed, iclass 21, count 0 2006.257.03:53:12.25#ibcon#about to write, iclass 21, count 0 2006.257.03:53:12.25#ibcon#wrote, iclass 21, count 0 2006.257.03:53:12.25#ibcon#about to read 3, iclass 21, count 0 2006.257.03:53:12.28#ibcon#read 3, iclass 21, count 0 2006.257.03:53:12.28#ibcon#about to read 4, iclass 21, count 0 2006.257.03:53:12.28#ibcon#read 4, iclass 21, count 0 2006.257.03:53:12.28#ibcon#about to read 5, iclass 21, count 0 2006.257.03:53:12.28#ibcon#read 5, iclass 21, count 0 2006.257.03:53:12.28#ibcon#about to read 6, iclass 21, count 0 2006.257.03:53:12.28#ibcon#read 6, iclass 21, count 0 2006.257.03:53:12.28#ibcon#end of sib2, iclass 21, count 0 2006.257.03:53:12.28#ibcon#*after write, iclass 21, count 0 2006.257.03:53:12.28#ibcon#*before return 0, iclass 21, count 0 2006.257.03:53:12.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:12.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:12.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:53:12.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:53:12.28$vck44/valo=7,864.99 2006.257.03:53:12.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.03:53:12.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.03:53:12.28#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:12.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:12.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:12.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:12.28#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:53:12.28#ibcon#first serial, iclass 23, count 0 2006.257.03:53:12.28#ibcon#enter sib2, iclass 23, count 0 2006.257.03:53:12.28#ibcon#flushed, iclass 23, count 0 2006.257.03:53:12.28#ibcon#about to write, iclass 23, count 0 2006.257.03:53:12.28#ibcon#wrote, iclass 23, count 0 2006.257.03:53:12.28#ibcon#about to read 3, iclass 23, count 0 2006.257.03:53:12.30#ibcon#read 3, iclass 23, count 0 2006.257.03:53:12.30#ibcon#about to read 4, iclass 23, count 0 2006.257.03:53:12.30#ibcon#read 4, iclass 23, count 0 2006.257.03:53:12.30#ibcon#about to read 5, iclass 23, count 0 2006.257.03:53:12.30#ibcon#read 5, iclass 23, count 0 2006.257.03:53:12.30#ibcon#about to read 6, iclass 23, count 0 2006.257.03:53:12.30#ibcon#read 6, iclass 23, count 0 2006.257.03:53:12.30#ibcon#end of sib2, iclass 23, count 0 2006.257.03:53:12.30#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:53:12.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:53:12.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:53:12.30#ibcon#*before write, iclass 23, count 0 2006.257.03:53:12.30#ibcon#enter sib2, iclass 23, count 0 2006.257.03:53:12.30#ibcon#flushed, iclass 23, count 0 2006.257.03:53:12.30#ibcon#about to write, iclass 23, count 0 2006.257.03:53:12.30#ibcon#wrote, iclass 23, count 0 2006.257.03:53:12.30#ibcon#about to read 3, iclass 23, count 0 2006.257.03:53:12.34#ibcon#read 3, iclass 23, count 0 2006.257.03:53:12.34#ibcon#about to read 4, iclass 23, count 0 2006.257.03:53:12.34#ibcon#read 4, iclass 23, count 0 2006.257.03:53:12.34#ibcon#about to read 5, iclass 23, count 0 2006.257.03:53:12.34#ibcon#read 5, iclass 23, count 0 2006.257.03:53:12.34#ibcon#about to read 6, iclass 23, count 0 2006.257.03:53:12.34#ibcon#read 6, iclass 23, count 0 2006.257.03:53:12.34#ibcon#end of sib2, iclass 23, count 0 2006.257.03:53:12.34#ibcon#*after write, iclass 23, count 0 2006.257.03:53:12.34#ibcon#*before return 0, iclass 23, count 0 2006.257.03:53:12.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:12.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:12.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:53:12.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:53:12.34$vck44/va=7,4 2006.257.03:53:12.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.03:53:12.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.03:53:12.34#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:12.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:12.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:12.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:12.40#ibcon#enter wrdev, iclass 25, count 2 2006.257.03:53:12.40#ibcon#first serial, iclass 25, count 2 2006.257.03:53:12.40#ibcon#enter sib2, iclass 25, count 2 2006.257.03:53:12.40#ibcon#flushed, iclass 25, count 2 2006.257.03:53:12.40#ibcon#about to write, iclass 25, count 2 2006.257.03:53:12.40#ibcon#wrote, iclass 25, count 2 2006.257.03:53:12.40#ibcon#about to read 3, iclass 25, count 2 2006.257.03:53:12.42#ibcon#read 3, iclass 25, count 2 2006.257.03:53:12.42#ibcon#about to read 4, iclass 25, count 2 2006.257.03:53:12.42#ibcon#read 4, iclass 25, count 2 2006.257.03:53:12.42#ibcon#about to read 5, iclass 25, count 2 2006.257.03:53:12.42#ibcon#read 5, iclass 25, count 2 2006.257.03:53:12.42#ibcon#about to read 6, iclass 25, count 2 2006.257.03:53:12.42#ibcon#read 6, iclass 25, count 2 2006.257.03:53:12.42#ibcon#end of sib2, iclass 25, count 2 2006.257.03:53:12.42#ibcon#*mode == 0, iclass 25, count 2 2006.257.03:53:12.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.03:53:12.42#ibcon#[25=AT07-04\r\n] 2006.257.03:53:12.42#ibcon#*before write, iclass 25, count 2 2006.257.03:53:12.42#ibcon#enter sib2, iclass 25, count 2 2006.257.03:53:12.42#ibcon#flushed, iclass 25, count 2 2006.257.03:53:12.42#ibcon#about to write, iclass 25, count 2 2006.257.03:53:12.42#ibcon#wrote, iclass 25, count 2 2006.257.03:53:12.42#ibcon#about to read 3, iclass 25, count 2 2006.257.03:53:12.45#ibcon#read 3, iclass 25, count 2 2006.257.03:53:12.45#ibcon#about to read 4, iclass 25, count 2 2006.257.03:53:12.45#ibcon#read 4, iclass 25, count 2 2006.257.03:53:12.45#ibcon#about to read 5, iclass 25, count 2 2006.257.03:53:12.45#ibcon#read 5, iclass 25, count 2 2006.257.03:53:12.45#ibcon#about to read 6, iclass 25, count 2 2006.257.03:53:12.45#ibcon#read 6, iclass 25, count 2 2006.257.03:53:12.45#ibcon#end of sib2, iclass 25, count 2 2006.257.03:53:12.45#ibcon#*after write, iclass 25, count 2 2006.257.03:53:12.45#ibcon#*before return 0, iclass 25, count 2 2006.257.03:53:12.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:12.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:12.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.03:53:12.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:12.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:12.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:12.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:12.57#ibcon#enter wrdev, iclass 25, count 0 2006.257.03:53:12.57#ibcon#first serial, iclass 25, count 0 2006.257.03:53:12.57#ibcon#enter sib2, iclass 25, count 0 2006.257.03:53:12.57#ibcon#flushed, iclass 25, count 0 2006.257.03:53:12.57#ibcon#about to write, iclass 25, count 0 2006.257.03:53:12.57#ibcon#wrote, iclass 25, count 0 2006.257.03:53:12.57#ibcon#about to read 3, iclass 25, count 0 2006.257.03:53:12.59#ibcon#read 3, iclass 25, count 0 2006.257.03:53:12.59#ibcon#about to read 4, iclass 25, count 0 2006.257.03:53:12.59#ibcon#read 4, iclass 25, count 0 2006.257.03:53:12.59#ibcon#about to read 5, iclass 25, count 0 2006.257.03:53:12.59#ibcon#read 5, iclass 25, count 0 2006.257.03:53:12.59#ibcon#about to read 6, iclass 25, count 0 2006.257.03:53:12.59#ibcon#read 6, iclass 25, count 0 2006.257.03:53:12.59#ibcon#end of sib2, iclass 25, count 0 2006.257.03:53:12.59#ibcon#*mode == 0, iclass 25, count 0 2006.257.03:53:12.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.03:53:12.59#ibcon#[25=USB\r\n] 2006.257.03:53:12.59#ibcon#*before write, iclass 25, count 0 2006.257.03:53:12.59#ibcon#enter sib2, iclass 25, count 0 2006.257.03:53:12.59#ibcon#flushed, iclass 25, count 0 2006.257.03:53:12.59#ibcon#about to write, iclass 25, count 0 2006.257.03:53:12.59#ibcon#wrote, iclass 25, count 0 2006.257.03:53:12.59#ibcon#about to read 3, iclass 25, count 0 2006.257.03:53:12.62#ibcon#read 3, iclass 25, count 0 2006.257.03:53:12.62#ibcon#about to read 4, iclass 25, count 0 2006.257.03:53:12.62#ibcon#read 4, iclass 25, count 0 2006.257.03:53:12.62#ibcon#about to read 5, iclass 25, count 0 2006.257.03:53:12.62#ibcon#read 5, iclass 25, count 0 2006.257.03:53:12.62#ibcon#about to read 6, iclass 25, count 0 2006.257.03:53:12.62#ibcon#read 6, iclass 25, count 0 2006.257.03:53:12.62#ibcon#end of sib2, iclass 25, count 0 2006.257.03:53:12.62#ibcon#*after write, iclass 25, count 0 2006.257.03:53:12.62#ibcon#*before return 0, iclass 25, count 0 2006.257.03:53:12.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:12.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:12.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.03:53:12.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.03:53:12.62$vck44/valo=8,884.99 2006.257.03:53:12.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.03:53:12.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.03:53:12.62#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:12.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:12.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:12.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:12.62#ibcon#enter wrdev, iclass 27, count 0 2006.257.03:53:12.62#ibcon#first serial, iclass 27, count 0 2006.257.03:53:12.62#ibcon#enter sib2, iclass 27, count 0 2006.257.03:53:12.62#ibcon#flushed, iclass 27, count 0 2006.257.03:53:12.62#ibcon#about to write, iclass 27, count 0 2006.257.03:53:12.62#ibcon#wrote, iclass 27, count 0 2006.257.03:53:12.62#ibcon#about to read 3, iclass 27, count 0 2006.257.03:53:12.64#ibcon#read 3, iclass 27, count 0 2006.257.03:53:12.64#ibcon#about to read 4, iclass 27, count 0 2006.257.03:53:12.64#ibcon#read 4, iclass 27, count 0 2006.257.03:53:12.64#ibcon#about to read 5, iclass 27, count 0 2006.257.03:53:12.64#ibcon#read 5, iclass 27, count 0 2006.257.03:53:12.64#ibcon#about to read 6, iclass 27, count 0 2006.257.03:53:12.64#ibcon#read 6, iclass 27, count 0 2006.257.03:53:12.64#ibcon#end of sib2, iclass 27, count 0 2006.257.03:53:12.64#ibcon#*mode == 0, iclass 27, count 0 2006.257.03:53:12.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.03:53:12.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:53:12.64#ibcon#*before write, iclass 27, count 0 2006.257.03:53:12.64#ibcon#enter sib2, iclass 27, count 0 2006.257.03:53:12.64#ibcon#flushed, iclass 27, count 0 2006.257.03:53:12.64#ibcon#about to write, iclass 27, count 0 2006.257.03:53:12.64#ibcon#wrote, iclass 27, count 0 2006.257.03:53:12.64#ibcon#about to read 3, iclass 27, count 0 2006.257.03:53:12.68#ibcon#read 3, iclass 27, count 0 2006.257.03:53:12.68#ibcon#about to read 4, iclass 27, count 0 2006.257.03:53:12.68#ibcon#read 4, iclass 27, count 0 2006.257.03:53:12.68#ibcon#about to read 5, iclass 27, count 0 2006.257.03:53:12.68#ibcon#read 5, iclass 27, count 0 2006.257.03:53:12.68#ibcon#about to read 6, iclass 27, count 0 2006.257.03:53:12.68#ibcon#read 6, iclass 27, count 0 2006.257.03:53:12.68#ibcon#end of sib2, iclass 27, count 0 2006.257.03:53:12.68#ibcon#*after write, iclass 27, count 0 2006.257.03:53:12.68#ibcon#*before return 0, iclass 27, count 0 2006.257.03:53:12.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:12.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:12.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.03:53:12.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.03:53:12.68$vck44/va=8,4 2006.257.03:53:12.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.03:53:12.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.03:53:12.68#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:12.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:53:12.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:53:12.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:53:12.74#ibcon#enter wrdev, iclass 29, count 2 2006.257.03:53:12.74#ibcon#first serial, iclass 29, count 2 2006.257.03:53:12.74#ibcon#enter sib2, iclass 29, count 2 2006.257.03:53:12.74#ibcon#flushed, iclass 29, count 2 2006.257.03:53:12.74#ibcon#about to write, iclass 29, count 2 2006.257.03:53:12.74#ibcon#wrote, iclass 29, count 2 2006.257.03:53:12.74#ibcon#about to read 3, iclass 29, count 2 2006.257.03:53:12.76#ibcon#read 3, iclass 29, count 2 2006.257.03:53:12.76#ibcon#about to read 4, iclass 29, count 2 2006.257.03:53:12.76#ibcon#read 4, iclass 29, count 2 2006.257.03:53:12.76#ibcon#about to read 5, iclass 29, count 2 2006.257.03:53:12.76#ibcon#read 5, iclass 29, count 2 2006.257.03:53:12.76#ibcon#about to read 6, iclass 29, count 2 2006.257.03:53:12.76#ibcon#read 6, iclass 29, count 2 2006.257.03:53:12.76#ibcon#end of sib2, iclass 29, count 2 2006.257.03:53:12.76#ibcon#*mode == 0, iclass 29, count 2 2006.257.03:53:12.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.03:53:12.76#ibcon#[25=AT08-04\r\n] 2006.257.03:53:12.76#ibcon#*before write, iclass 29, count 2 2006.257.03:53:12.76#ibcon#enter sib2, iclass 29, count 2 2006.257.03:53:12.76#ibcon#flushed, iclass 29, count 2 2006.257.03:53:12.76#ibcon#about to write, iclass 29, count 2 2006.257.03:53:12.76#ibcon#wrote, iclass 29, count 2 2006.257.03:53:12.76#ibcon#about to read 3, iclass 29, count 2 2006.257.03:53:12.79#ibcon#read 3, iclass 29, count 2 2006.257.03:53:12.79#ibcon#about to read 4, iclass 29, count 2 2006.257.03:53:12.79#ibcon#read 4, iclass 29, count 2 2006.257.03:53:12.79#ibcon#about to read 5, iclass 29, count 2 2006.257.03:53:12.79#ibcon#read 5, iclass 29, count 2 2006.257.03:53:12.79#ibcon#about to read 6, iclass 29, count 2 2006.257.03:53:12.79#ibcon#read 6, iclass 29, count 2 2006.257.03:53:12.79#ibcon#end of sib2, iclass 29, count 2 2006.257.03:53:12.79#ibcon#*after write, iclass 29, count 2 2006.257.03:53:12.79#ibcon#*before return 0, iclass 29, count 2 2006.257.03:53:12.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:53:12.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.03:53:12.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.03:53:12.79#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:12.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:53:12.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:53:12.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:53:12.91#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:53:12.91#ibcon#first serial, iclass 29, count 0 2006.257.03:53:12.91#ibcon#enter sib2, iclass 29, count 0 2006.257.03:53:12.91#ibcon#flushed, iclass 29, count 0 2006.257.03:53:12.91#ibcon#about to write, iclass 29, count 0 2006.257.03:53:12.91#ibcon#wrote, iclass 29, count 0 2006.257.03:53:12.91#ibcon#about to read 3, iclass 29, count 0 2006.257.03:53:12.93#ibcon#read 3, iclass 29, count 0 2006.257.03:53:12.93#ibcon#about to read 4, iclass 29, count 0 2006.257.03:53:12.93#ibcon#read 4, iclass 29, count 0 2006.257.03:53:12.93#ibcon#about to read 5, iclass 29, count 0 2006.257.03:53:12.93#ibcon#read 5, iclass 29, count 0 2006.257.03:53:12.93#ibcon#about to read 6, iclass 29, count 0 2006.257.03:53:12.93#ibcon#read 6, iclass 29, count 0 2006.257.03:53:12.93#ibcon#end of sib2, iclass 29, count 0 2006.257.03:53:12.93#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:53:12.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:53:12.93#ibcon#[25=USB\r\n] 2006.257.03:53:12.93#ibcon#*before write, iclass 29, count 0 2006.257.03:53:12.93#ibcon#enter sib2, iclass 29, count 0 2006.257.03:53:12.93#ibcon#flushed, iclass 29, count 0 2006.257.03:53:12.93#ibcon#about to write, iclass 29, count 0 2006.257.03:53:12.93#ibcon#wrote, iclass 29, count 0 2006.257.03:53:12.93#ibcon#about to read 3, iclass 29, count 0 2006.257.03:53:12.96#ibcon#read 3, iclass 29, count 0 2006.257.03:53:12.96#ibcon#about to read 4, iclass 29, count 0 2006.257.03:53:12.96#ibcon#read 4, iclass 29, count 0 2006.257.03:53:12.96#ibcon#about to read 5, iclass 29, count 0 2006.257.03:53:12.96#ibcon#read 5, iclass 29, count 0 2006.257.03:53:12.96#ibcon#about to read 6, iclass 29, count 0 2006.257.03:53:12.96#ibcon#read 6, iclass 29, count 0 2006.257.03:53:12.96#ibcon#end of sib2, iclass 29, count 0 2006.257.03:53:12.96#ibcon#*after write, iclass 29, count 0 2006.257.03:53:12.96#ibcon#*before return 0, iclass 29, count 0 2006.257.03:53:12.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:53:12.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.03:53:12.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:53:12.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:53:12.96$vck44/vblo=1,629.99 2006.257.03:53:12.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.03:53:12.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.03:53:12.96#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:12.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:53:12.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:53:12.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:53:12.96#ibcon#enter wrdev, iclass 31, count 0 2006.257.03:53:12.96#ibcon#first serial, iclass 31, count 0 2006.257.03:53:12.96#ibcon#enter sib2, iclass 31, count 0 2006.257.03:53:12.96#ibcon#flushed, iclass 31, count 0 2006.257.03:53:12.96#ibcon#about to write, iclass 31, count 0 2006.257.03:53:12.96#ibcon#wrote, iclass 31, count 0 2006.257.03:53:12.96#ibcon#about to read 3, iclass 31, count 0 2006.257.03:53:12.98#ibcon#read 3, iclass 31, count 0 2006.257.03:53:12.98#ibcon#about to read 4, iclass 31, count 0 2006.257.03:53:12.98#ibcon#read 4, iclass 31, count 0 2006.257.03:53:12.98#ibcon#about to read 5, iclass 31, count 0 2006.257.03:53:12.98#ibcon#read 5, iclass 31, count 0 2006.257.03:53:12.98#ibcon#about to read 6, iclass 31, count 0 2006.257.03:53:12.98#ibcon#read 6, iclass 31, count 0 2006.257.03:53:12.98#ibcon#end of sib2, iclass 31, count 0 2006.257.03:53:12.98#ibcon#*mode == 0, iclass 31, count 0 2006.257.03:53:12.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.03:53:12.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:53:12.98#ibcon#*before write, iclass 31, count 0 2006.257.03:53:12.98#ibcon#enter sib2, iclass 31, count 0 2006.257.03:53:12.98#ibcon#flushed, iclass 31, count 0 2006.257.03:53:12.98#ibcon#about to write, iclass 31, count 0 2006.257.03:53:12.98#ibcon#wrote, iclass 31, count 0 2006.257.03:53:12.98#ibcon#about to read 3, iclass 31, count 0 2006.257.03:53:13.02#ibcon#read 3, iclass 31, count 0 2006.257.03:53:13.02#ibcon#about to read 4, iclass 31, count 0 2006.257.03:53:13.02#ibcon#read 4, iclass 31, count 0 2006.257.03:53:13.02#ibcon#about to read 5, iclass 31, count 0 2006.257.03:53:13.02#ibcon#read 5, iclass 31, count 0 2006.257.03:53:13.02#ibcon#about to read 6, iclass 31, count 0 2006.257.03:53:13.02#ibcon#read 6, iclass 31, count 0 2006.257.03:53:13.02#ibcon#end of sib2, iclass 31, count 0 2006.257.03:53:13.02#ibcon#*after write, iclass 31, count 0 2006.257.03:53:13.02#ibcon#*before return 0, iclass 31, count 0 2006.257.03:53:13.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:53:13.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.03:53:13.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.03:53:13.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.03:53:13.02$vck44/vb=1,4 2006.257.03:53:13.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.03:53:13.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.03:53:13.02#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:13.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:53:13.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:53:13.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:53:13.02#ibcon#enter wrdev, iclass 33, count 2 2006.257.03:53:13.02#ibcon#first serial, iclass 33, count 2 2006.257.03:53:13.02#ibcon#enter sib2, iclass 33, count 2 2006.257.03:53:13.02#ibcon#flushed, iclass 33, count 2 2006.257.03:53:13.02#ibcon#about to write, iclass 33, count 2 2006.257.03:53:13.02#ibcon#wrote, iclass 33, count 2 2006.257.03:53:13.02#ibcon#about to read 3, iclass 33, count 2 2006.257.03:53:13.04#ibcon#read 3, iclass 33, count 2 2006.257.03:53:13.04#ibcon#about to read 4, iclass 33, count 2 2006.257.03:53:13.04#ibcon#read 4, iclass 33, count 2 2006.257.03:53:13.04#ibcon#about to read 5, iclass 33, count 2 2006.257.03:53:13.04#ibcon#read 5, iclass 33, count 2 2006.257.03:53:13.04#ibcon#about to read 6, iclass 33, count 2 2006.257.03:53:13.04#ibcon#read 6, iclass 33, count 2 2006.257.03:53:13.04#ibcon#end of sib2, iclass 33, count 2 2006.257.03:53:13.04#ibcon#*mode == 0, iclass 33, count 2 2006.257.03:53:13.04#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.03:53:13.04#ibcon#[27=AT01-04\r\n] 2006.257.03:53:13.04#ibcon#*before write, iclass 33, count 2 2006.257.03:53:13.04#ibcon#enter sib2, iclass 33, count 2 2006.257.03:53:13.04#ibcon#flushed, iclass 33, count 2 2006.257.03:53:13.04#ibcon#about to write, iclass 33, count 2 2006.257.03:53:13.04#ibcon#wrote, iclass 33, count 2 2006.257.03:53:13.04#ibcon#about to read 3, iclass 33, count 2 2006.257.03:53:13.07#ibcon#read 3, iclass 33, count 2 2006.257.03:53:13.07#ibcon#about to read 4, iclass 33, count 2 2006.257.03:53:13.07#ibcon#read 4, iclass 33, count 2 2006.257.03:53:13.07#ibcon#about to read 5, iclass 33, count 2 2006.257.03:53:13.07#ibcon#read 5, iclass 33, count 2 2006.257.03:53:13.07#ibcon#about to read 6, iclass 33, count 2 2006.257.03:53:13.07#ibcon#read 6, iclass 33, count 2 2006.257.03:53:13.07#ibcon#end of sib2, iclass 33, count 2 2006.257.03:53:13.07#ibcon#*after write, iclass 33, count 2 2006.257.03:53:13.07#ibcon#*before return 0, iclass 33, count 2 2006.257.03:53:13.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:53:13.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.03:53:13.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.03:53:13.07#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:13.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:53:13.19#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:53:13.19#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:53:13.19#ibcon#enter wrdev, iclass 33, count 0 2006.257.03:53:13.19#ibcon#first serial, iclass 33, count 0 2006.257.03:53:13.19#ibcon#enter sib2, iclass 33, count 0 2006.257.03:53:13.19#ibcon#flushed, iclass 33, count 0 2006.257.03:53:13.19#ibcon#about to write, iclass 33, count 0 2006.257.03:53:13.19#ibcon#wrote, iclass 33, count 0 2006.257.03:53:13.19#ibcon#about to read 3, iclass 33, count 0 2006.257.03:53:13.21#ibcon#read 3, iclass 33, count 0 2006.257.03:53:13.21#ibcon#about to read 4, iclass 33, count 0 2006.257.03:53:13.21#ibcon#read 4, iclass 33, count 0 2006.257.03:53:13.21#ibcon#about to read 5, iclass 33, count 0 2006.257.03:53:13.21#ibcon#read 5, iclass 33, count 0 2006.257.03:53:13.21#ibcon#about to read 6, iclass 33, count 0 2006.257.03:53:13.21#ibcon#read 6, iclass 33, count 0 2006.257.03:53:13.21#ibcon#end of sib2, iclass 33, count 0 2006.257.03:53:13.21#ibcon#*mode == 0, iclass 33, count 0 2006.257.03:53:13.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.03:53:13.21#ibcon#[27=USB\r\n] 2006.257.03:53:13.21#ibcon#*before write, iclass 33, count 0 2006.257.03:53:13.21#ibcon#enter sib2, iclass 33, count 0 2006.257.03:53:13.21#ibcon#flushed, iclass 33, count 0 2006.257.03:53:13.21#ibcon#about to write, iclass 33, count 0 2006.257.03:53:13.21#ibcon#wrote, iclass 33, count 0 2006.257.03:53:13.21#ibcon#about to read 3, iclass 33, count 0 2006.257.03:53:13.24#ibcon#read 3, iclass 33, count 0 2006.257.03:53:13.24#ibcon#about to read 4, iclass 33, count 0 2006.257.03:53:13.24#ibcon#read 4, iclass 33, count 0 2006.257.03:53:13.24#ibcon#about to read 5, iclass 33, count 0 2006.257.03:53:13.24#ibcon#read 5, iclass 33, count 0 2006.257.03:53:13.24#ibcon#about to read 6, iclass 33, count 0 2006.257.03:53:13.24#ibcon#read 6, iclass 33, count 0 2006.257.03:53:13.24#ibcon#end of sib2, iclass 33, count 0 2006.257.03:53:13.24#ibcon#*after write, iclass 33, count 0 2006.257.03:53:13.24#ibcon#*before return 0, iclass 33, count 0 2006.257.03:53:13.24#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:53:13.24#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.03:53:13.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.03:53:13.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.03:53:13.24$vck44/vblo=2,634.99 2006.257.03:53:13.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.03:53:13.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.03:53:13.24#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:13.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:13.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:13.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:13.24#ibcon#enter wrdev, iclass 35, count 0 2006.257.03:53:13.24#ibcon#first serial, iclass 35, count 0 2006.257.03:53:13.24#ibcon#enter sib2, iclass 35, count 0 2006.257.03:53:13.24#ibcon#flushed, iclass 35, count 0 2006.257.03:53:13.24#ibcon#about to write, iclass 35, count 0 2006.257.03:53:13.24#ibcon#wrote, iclass 35, count 0 2006.257.03:53:13.24#ibcon#about to read 3, iclass 35, count 0 2006.257.03:53:13.26#ibcon#read 3, iclass 35, count 0 2006.257.03:53:13.26#ibcon#about to read 4, iclass 35, count 0 2006.257.03:53:13.26#ibcon#read 4, iclass 35, count 0 2006.257.03:53:13.26#ibcon#about to read 5, iclass 35, count 0 2006.257.03:53:13.26#ibcon#read 5, iclass 35, count 0 2006.257.03:53:13.26#ibcon#about to read 6, iclass 35, count 0 2006.257.03:53:13.26#ibcon#read 6, iclass 35, count 0 2006.257.03:53:13.26#ibcon#end of sib2, iclass 35, count 0 2006.257.03:53:13.26#ibcon#*mode == 0, iclass 35, count 0 2006.257.03:53:13.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.03:53:13.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:53:13.26#ibcon#*before write, iclass 35, count 0 2006.257.03:53:13.26#ibcon#enter sib2, iclass 35, count 0 2006.257.03:53:13.26#ibcon#flushed, iclass 35, count 0 2006.257.03:53:13.26#ibcon#about to write, iclass 35, count 0 2006.257.03:53:13.26#ibcon#wrote, iclass 35, count 0 2006.257.03:53:13.26#ibcon#about to read 3, iclass 35, count 0 2006.257.03:53:13.30#ibcon#read 3, iclass 35, count 0 2006.257.03:53:13.30#ibcon#about to read 4, iclass 35, count 0 2006.257.03:53:13.30#ibcon#read 4, iclass 35, count 0 2006.257.03:53:13.30#ibcon#about to read 5, iclass 35, count 0 2006.257.03:53:13.30#ibcon#read 5, iclass 35, count 0 2006.257.03:53:13.30#ibcon#about to read 6, iclass 35, count 0 2006.257.03:53:13.30#ibcon#read 6, iclass 35, count 0 2006.257.03:53:13.30#ibcon#end of sib2, iclass 35, count 0 2006.257.03:53:13.30#ibcon#*after write, iclass 35, count 0 2006.257.03:53:13.30#ibcon#*before return 0, iclass 35, count 0 2006.257.03:53:13.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:13.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.03:53:13.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.03:53:13.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.03:53:13.30$vck44/vb=2,5 2006.257.03:53:13.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.03:53:13.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.03:53:13.30#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:13.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:13.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:13.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:13.36#ibcon#enter wrdev, iclass 37, count 2 2006.257.03:53:13.36#ibcon#first serial, iclass 37, count 2 2006.257.03:53:13.36#ibcon#enter sib2, iclass 37, count 2 2006.257.03:53:13.36#ibcon#flushed, iclass 37, count 2 2006.257.03:53:13.36#ibcon#about to write, iclass 37, count 2 2006.257.03:53:13.36#ibcon#wrote, iclass 37, count 2 2006.257.03:53:13.36#ibcon#about to read 3, iclass 37, count 2 2006.257.03:53:13.38#ibcon#read 3, iclass 37, count 2 2006.257.03:53:13.38#ibcon#about to read 4, iclass 37, count 2 2006.257.03:53:13.38#ibcon#read 4, iclass 37, count 2 2006.257.03:53:13.38#ibcon#about to read 5, iclass 37, count 2 2006.257.03:53:13.38#ibcon#read 5, iclass 37, count 2 2006.257.03:53:13.38#ibcon#about to read 6, iclass 37, count 2 2006.257.03:53:13.38#ibcon#read 6, iclass 37, count 2 2006.257.03:53:13.38#ibcon#end of sib2, iclass 37, count 2 2006.257.03:53:13.38#ibcon#*mode == 0, iclass 37, count 2 2006.257.03:53:13.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.03:53:13.38#ibcon#[27=AT02-05\r\n] 2006.257.03:53:13.38#ibcon#*before write, iclass 37, count 2 2006.257.03:53:13.38#ibcon#enter sib2, iclass 37, count 2 2006.257.03:53:13.38#ibcon#flushed, iclass 37, count 2 2006.257.03:53:13.38#ibcon#about to write, iclass 37, count 2 2006.257.03:53:13.38#ibcon#wrote, iclass 37, count 2 2006.257.03:53:13.38#ibcon#about to read 3, iclass 37, count 2 2006.257.03:53:13.41#ibcon#read 3, iclass 37, count 2 2006.257.03:53:13.41#ibcon#about to read 4, iclass 37, count 2 2006.257.03:53:13.41#ibcon#read 4, iclass 37, count 2 2006.257.03:53:13.41#ibcon#about to read 5, iclass 37, count 2 2006.257.03:53:13.41#ibcon#read 5, iclass 37, count 2 2006.257.03:53:13.41#ibcon#about to read 6, iclass 37, count 2 2006.257.03:53:13.41#ibcon#read 6, iclass 37, count 2 2006.257.03:53:13.41#ibcon#end of sib2, iclass 37, count 2 2006.257.03:53:13.41#ibcon#*after write, iclass 37, count 2 2006.257.03:53:13.41#ibcon#*before return 0, iclass 37, count 2 2006.257.03:53:13.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:13.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.03:53:13.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.03:53:13.41#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:13.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:13.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:13.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:13.53#ibcon#enter wrdev, iclass 37, count 0 2006.257.03:53:13.53#ibcon#first serial, iclass 37, count 0 2006.257.03:53:13.53#ibcon#enter sib2, iclass 37, count 0 2006.257.03:53:13.53#ibcon#flushed, iclass 37, count 0 2006.257.03:53:13.53#ibcon#about to write, iclass 37, count 0 2006.257.03:53:13.53#ibcon#wrote, iclass 37, count 0 2006.257.03:53:13.53#ibcon#about to read 3, iclass 37, count 0 2006.257.03:53:13.55#ibcon#read 3, iclass 37, count 0 2006.257.03:53:13.55#ibcon#about to read 4, iclass 37, count 0 2006.257.03:53:13.55#ibcon#read 4, iclass 37, count 0 2006.257.03:53:13.55#ibcon#about to read 5, iclass 37, count 0 2006.257.03:53:13.55#ibcon#read 5, iclass 37, count 0 2006.257.03:53:13.55#ibcon#about to read 6, iclass 37, count 0 2006.257.03:53:13.55#ibcon#read 6, iclass 37, count 0 2006.257.03:53:13.55#ibcon#end of sib2, iclass 37, count 0 2006.257.03:53:13.55#ibcon#*mode == 0, iclass 37, count 0 2006.257.03:53:13.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.03:53:13.55#ibcon#[27=USB\r\n] 2006.257.03:53:13.55#ibcon#*before write, iclass 37, count 0 2006.257.03:53:13.55#ibcon#enter sib2, iclass 37, count 0 2006.257.03:53:13.55#ibcon#flushed, iclass 37, count 0 2006.257.03:53:13.55#ibcon#about to write, iclass 37, count 0 2006.257.03:53:13.55#ibcon#wrote, iclass 37, count 0 2006.257.03:53:13.55#ibcon#about to read 3, iclass 37, count 0 2006.257.03:53:13.58#ibcon#read 3, iclass 37, count 0 2006.257.03:53:13.58#ibcon#about to read 4, iclass 37, count 0 2006.257.03:53:13.58#ibcon#read 4, iclass 37, count 0 2006.257.03:53:13.58#ibcon#about to read 5, iclass 37, count 0 2006.257.03:53:13.58#ibcon#read 5, iclass 37, count 0 2006.257.03:53:13.58#ibcon#about to read 6, iclass 37, count 0 2006.257.03:53:13.58#ibcon#read 6, iclass 37, count 0 2006.257.03:53:13.58#ibcon#end of sib2, iclass 37, count 0 2006.257.03:53:13.58#ibcon#*after write, iclass 37, count 0 2006.257.03:53:13.58#ibcon#*before return 0, iclass 37, count 0 2006.257.03:53:13.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:13.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.03:53:13.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.03:53:13.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.03:53:13.58$vck44/vblo=3,649.99 2006.257.03:53:13.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.03:53:13.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.03:53:13.58#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:13.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:13.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:13.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:13.58#ibcon#enter wrdev, iclass 39, count 0 2006.257.03:53:13.58#ibcon#first serial, iclass 39, count 0 2006.257.03:53:13.58#ibcon#enter sib2, iclass 39, count 0 2006.257.03:53:13.58#ibcon#flushed, iclass 39, count 0 2006.257.03:53:13.58#ibcon#about to write, iclass 39, count 0 2006.257.03:53:13.58#ibcon#wrote, iclass 39, count 0 2006.257.03:53:13.58#ibcon#about to read 3, iclass 39, count 0 2006.257.03:53:13.60#ibcon#read 3, iclass 39, count 0 2006.257.03:53:13.60#ibcon#about to read 4, iclass 39, count 0 2006.257.03:53:13.60#ibcon#read 4, iclass 39, count 0 2006.257.03:53:13.60#ibcon#about to read 5, iclass 39, count 0 2006.257.03:53:13.60#ibcon#read 5, iclass 39, count 0 2006.257.03:53:13.60#ibcon#about to read 6, iclass 39, count 0 2006.257.03:53:13.60#ibcon#read 6, iclass 39, count 0 2006.257.03:53:13.60#ibcon#end of sib2, iclass 39, count 0 2006.257.03:53:13.60#ibcon#*mode == 0, iclass 39, count 0 2006.257.03:53:13.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.03:53:13.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:53:13.60#ibcon#*before write, iclass 39, count 0 2006.257.03:53:13.60#ibcon#enter sib2, iclass 39, count 0 2006.257.03:53:13.60#ibcon#flushed, iclass 39, count 0 2006.257.03:53:13.60#ibcon#about to write, iclass 39, count 0 2006.257.03:53:13.60#ibcon#wrote, iclass 39, count 0 2006.257.03:53:13.60#ibcon#about to read 3, iclass 39, count 0 2006.257.03:53:13.64#ibcon#read 3, iclass 39, count 0 2006.257.03:53:13.64#ibcon#about to read 4, iclass 39, count 0 2006.257.03:53:13.64#ibcon#read 4, iclass 39, count 0 2006.257.03:53:13.64#ibcon#about to read 5, iclass 39, count 0 2006.257.03:53:13.64#ibcon#read 5, iclass 39, count 0 2006.257.03:53:13.64#ibcon#about to read 6, iclass 39, count 0 2006.257.03:53:13.64#ibcon#read 6, iclass 39, count 0 2006.257.03:53:13.64#ibcon#end of sib2, iclass 39, count 0 2006.257.03:53:13.64#ibcon#*after write, iclass 39, count 0 2006.257.03:53:13.64#ibcon#*before return 0, iclass 39, count 0 2006.257.03:53:13.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:13.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.03:53:13.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.03:53:13.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.03:53:13.64$vck44/vb=3,4 2006.257.03:53:13.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.03:53:13.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.03:53:13.64#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:13.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:13.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:13.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:13.70#ibcon#enter wrdev, iclass 3, count 2 2006.257.03:53:13.70#ibcon#first serial, iclass 3, count 2 2006.257.03:53:13.70#ibcon#enter sib2, iclass 3, count 2 2006.257.03:53:13.70#ibcon#flushed, iclass 3, count 2 2006.257.03:53:13.70#ibcon#about to write, iclass 3, count 2 2006.257.03:53:13.70#ibcon#wrote, iclass 3, count 2 2006.257.03:53:13.70#ibcon#about to read 3, iclass 3, count 2 2006.257.03:53:13.72#ibcon#read 3, iclass 3, count 2 2006.257.03:53:13.72#ibcon#about to read 4, iclass 3, count 2 2006.257.03:53:13.72#ibcon#read 4, iclass 3, count 2 2006.257.03:53:13.72#ibcon#about to read 5, iclass 3, count 2 2006.257.03:53:13.72#ibcon#read 5, iclass 3, count 2 2006.257.03:53:13.72#ibcon#about to read 6, iclass 3, count 2 2006.257.03:53:13.72#ibcon#read 6, iclass 3, count 2 2006.257.03:53:13.72#ibcon#end of sib2, iclass 3, count 2 2006.257.03:53:13.72#ibcon#*mode == 0, iclass 3, count 2 2006.257.03:53:13.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.03:53:13.72#ibcon#[27=AT03-04\r\n] 2006.257.03:53:13.72#ibcon#*before write, iclass 3, count 2 2006.257.03:53:13.72#ibcon#enter sib2, iclass 3, count 2 2006.257.03:53:13.72#ibcon#flushed, iclass 3, count 2 2006.257.03:53:13.72#ibcon#about to write, iclass 3, count 2 2006.257.03:53:13.72#ibcon#wrote, iclass 3, count 2 2006.257.03:53:13.72#ibcon#about to read 3, iclass 3, count 2 2006.257.03:53:13.75#ibcon#read 3, iclass 3, count 2 2006.257.03:53:13.75#ibcon#about to read 4, iclass 3, count 2 2006.257.03:53:13.75#ibcon#read 4, iclass 3, count 2 2006.257.03:53:13.75#ibcon#about to read 5, iclass 3, count 2 2006.257.03:53:13.75#ibcon#read 5, iclass 3, count 2 2006.257.03:53:13.75#ibcon#about to read 6, iclass 3, count 2 2006.257.03:53:13.75#ibcon#read 6, iclass 3, count 2 2006.257.03:53:13.75#ibcon#end of sib2, iclass 3, count 2 2006.257.03:53:13.75#ibcon#*after write, iclass 3, count 2 2006.257.03:53:13.75#ibcon#*before return 0, iclass 3, count 2 2006.257.03:53:13.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:13.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.03:53:13.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.03:53:13.75#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:13.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:13.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:13.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:13.87#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:53:13.87#ibcon#first serial, iclass 3, count 0 2006.257.03:53:13.87#ibcon#enter sib2, iclass 3, count 0 2006.257.03:53:13.87#ibcon#flushed, iclass 3, count 0 2006.257.03:53:13.87#ibcon#about to write, iclass 3, count 0 2006.257.03:53:13.87#ibcon#wrote, iclass 3, count 0 2006.257.03:53:13.87#ibcon#about to read 3, iclass 3, count 0 2006.257.03:53:13.89#ibcon#read 3, iclass 3, count 0 2006.257.03:53:13.89#ibcon#about to read 4, iclass 3, count 0 2006.257.03:53:13.89#ibcon#read 4, iclass 3, count 0 2006.257.03:53:13.89#ibcon#about to read 5, iclass 3, count 0 2006.257.03:53:13.89#ibcon#read 5, iclass 3, count 0 2006.257.03:53:13.89#ibcon#about to read 6, iclass 3, count 0 2006.257.03:53:13.89#ibcon#read 6, iclass 3, count 0 2006.257.03:53:13.89#ibcon#end of sib2, iclass 3, count 0 2006.257.03:53:13.89#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:53:13.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:53:13.89#ibcon#[27=USB\r\n] 2006.257.03:53:13.89#ibcon#*before write, iclass 3, count 0 2006.257.03:53:13.89#ibcon#enter sib2, iclass 3, count 0 2006.257.03:53:13.89#ibcon#flushed, iclass 3, count 0 2006.257.03:53:13.89#ibcon#about to write, iclass 3, count 0 2006.257.03:53:13.89#ibcon#wrote, iclass 3, count 0 2006.257.03:53:13.89#ibcon#about to read 3, iclass 3, count 0 2006.257.03:53:13.92#ibcon#read 3, iclass 3, count 0 2006.257.03:53:13.92#ibcon#about to read 4, iclass 3, count 0 2006.257.03:53:13.92#ibcon#read 4, iclass 3, count 0 2006.257.03:53:13.92#ibcon#about to read 5, iclass 3, count 0 2006.257.03:53:13.92#ibcon#read 5, iclass 3, count 0 2006.257.03:53:13.92#ibcon#about to read 6, iclass 3, count 0 2006.257.03:53:13.92#ibcon#read 6, iclass 3, count 0 2006.257.03:53:13.92#ibcon#end of sib2, iclass 3, count 0 2006.257.03:53:13.92#ibcon#*after write, iclass 3, count 0 2006.257.03:53:13.92#ibcon#*before return 0, iclass 3, count 0 2006.257.03:53:13.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:13.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.03:53:13.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:53:13.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:53:13.92$vck44/vblo=4,679.99 2006.257.03:53:13.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.03:53:13.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.03:53:13.92#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:13.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:13.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:13.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:13.92#ibcon#enter wrdev, iclass 5, count 0 2006.257.03:53:13.92#ibcon#first serial, iclass 5, count 0 2006.257.03:53:13.92#ibcon#enter sib2, iclass 5, count 0 2006.257.03:53:13.92#ibcon#flushed, iclass 5, count 0 2006.257.03:53:13.92#ibcon#about to write, iclass 5, count 0 2006.257.03:53:13.92#ibcon#wrote, iclass 5, count 0 2006.257.03:53:13.92#ibcon#about to read 3, iclass 5, count 0 2006.257.03:53:13.94#ibcon#read 3, iclass 5, count 0 2006.257.03:53:13.94#ibcon#about to read 4, iclass 5, count 0 2006.257.03:53:13.94#ibcon#read 4, iclass 5, count 0 2006.257.03:53:13.94#ibcon#about to read 5, iclass 5, count 0 2006.257.03:53:13.94#ibcon#read 5, iclass 5, count 0 2006.257.03:53:13.94#ibcon#about to read 6, iclass 5, count 0 2006.257.03:53:13.94#ibcon#read 6, iclass 5, count 0 2006.257.03:53:13.94#ibcon#end of sib2, iclass 5, count 0 2006.257.03:53:13.94#ibcon#*mode == 0, iclass 5, count 0 2006.257.03:53:13.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.03:53:13.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:53:13.94#ibcon#*before write, iclass 5, count 0 2006.257.03:53:13.94#ibcon#enter sib2, iclass 5, count 0 2006.257.03:53:13.94#ibcon#flushed, iclass 5, count 0 2006.257.03:53:13.94#ibcon#about to write, iclass 5, count 0 2006.257.03:53:13.94#ibcon#wrote, iclass 5, count 0 2006.257.03:53:13.94#ibcon#about to read 3, iclass 5, count 0 2006.257.03:53:13.98#ibcon#read 3, iclass 5, count 0 2006.257.03:53:13.98#ibcon#about to read 4, iclass 5, count 0 2006.257.03:53:13.98#ibcon#read 4, iclass 5, count 0 2006.257.03:53:13.98#ibcon#about to read 5, iclass 5, count 0 2006.257.03:53:13.98#ibcon#read 5, iclass 5, count 0 2006.257.03:53:13.98#ibcon#about to read 6, iclass 5, count 0 2006.257.03:53:13.98#ibcon#read 6, iclass 5, count 0 2006.257.03:53:13.98#ibcon#end of sib2, iclass 5, count 0 2006.257.03:53:13.98#ibcon#*after write, iclass 5, count 0 2006.257.03:53:13.98#ibcon#*before return 0, iclass 5, count 0 2006.257.03:53:13.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:13.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.03:53:13.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.03:53:13.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.03:53:13.98$vck44/vb=4,5 2006.257.03:53:13.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.03:53:13.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.03:53:13.98#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:13.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:14.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:14.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:14.04#ibcon#enter wrdev, iclass 7, count 2 2006.257.03:53:14.04#ibcon#first serial, iclass 7, count 2 2006.257.03:53:14.04#ibcon#enter sib2, iclass 7, count 2 2006.257.03:53:14.04#ibcon#flushed, iclass 7, count 2 2006.257.03:53:14.04#ibcon#about to write, iclass 7, count 2 2006.257.03:53:14.04#ibcon#wrote, iclass 7, count 2 2006.257.03:53:14.04#ibcon#about to read 3, iclass 7, count 2 2006.257.03:53:14.06#ibcon#read 3, iclass 7, count 2 2006.257.03:53:14.06#ibcon#about to read 4, iclass 7, count 2 2006.257.03:53:14.06#ibcon#read 4, iclass 7, count 2 2006.257.03:53:14.06#ibcon#about to read 5, iclass 7, count 2 2006.257.03:53:14.06#ibcon#read 5, iclass 7, count 2 2006.257.03:53:14.06#ibcon#about to read 6, iclass 7, count 2 2006.257.03:53:14.06#ibcon#read 6, iclass 7, count 2 2006.257.03:53:14.06#ibcon#end of sib2, iclass 7, count 2 2006.257.03:53:14.06#ibcon#*mode == 0, iclass 7, count 2 2006.257.03:53:14.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.03:53:14.06#ibcon#[27=AT04-05\r\n] 2006.257.03:53:14.06#ibcon#*before write, iclass 7, count 2 2006.257.03:53:14.06#ibcon#enter sib2, iclass 7, count 2 2006.257.03:53:14.06#ibcon#flushed, iclass 7, count 2 2006.257.03:53:14.06#ibcon#about to write, iclass 7, count 2 2006.257.03:53:14.06#ibcon#wrote, iclass 7, count 2 2006.257.03:53:14.06#ibcon#about to read 3, iclass 7, count 2 2006.257.03:53:14.09#ibcon#read 3, iclass 7, count 2 2006.257.03:53:14.09#ibcon#about to read 4, iclass 7, count 2 2006.257.03:53:14.09#ibcon#read 4, iclass 7, count 2 2006.257.03:53:14.09#ibcon#about to read 5, iclass 7, count 2 2006.257.03:53:14.09#ibcon#read 5, iclass 7, count 2 2006.257.03:53:14.09#ibcon#about to read 6, iclass 7, count 2 2006.257.03:53:14.09#ibcon#read 6, iclass 7, count 2 2006.257.03:53:14.09#ibcon#end of sib2, iclass 7, count 2 2006.257.03:53:14.09#ibcon#*after write, iclass 7, count 2 2006.257.03:53:14.09#ibcon#*before return 0, iclass 7, count 2 2006.257.03:53:14.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:14.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.03:53:14.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.03:53:14.09#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:14.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:14.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:14.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:14.21#ibcon#enter wrdev, iclass 7, count 0 2006.257.03:53:14.21#ibcon#first serial, iclass 7, count 0 2006.257.03:53:14.21#ibcon#enter sib2, iclass 7, count 0 2006.257.03:53:14.21#ibcon#flushed, iclass 7, count 0 2006.257.03:53:14.21#ibcon#about to write, iclass 7, count 0 2006.257.03:53:14.21#ibcon#wrote, iclass 7, count 0 2006.257.03:53:14.21#ibcon#about to read 3, iclass 7, count 0 2006.257.03:53:14.23#ibcon#read 3, iclass 7, count 0 2006.257.03:53:14.23#ibcon#about to read 4, iclass 7, count 0 2006.257.03:53:14.23#ibcon#read 4, iclass 7, count 0 2006.257.03:53:14.23#ibcon#about to read 5, iclass 7, count 0 2006.257.03:53:14.23#ibcon#read 5, iclass 7, count 0 2006.257.03:53:14.23#ibcon#about to read 6, iclass 7, count 0 2006.257.03:53:14.23#ibcon#read 6, iclass 7, count 0 2006.257.03:53:14.23#ibcon#end of sib2, iclass 7, count 0 2006.257.03:53:14.23#ibcon#*mode == 0, iclass 7, count 0 2006.257.03:53:14.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.03:53:14.23#ibcon#[27=USB\r\n] 2006.257.03:53:14.23#ibcon#*before write, iclass 7, count 0 2006.257.03:53:14.23#ibcon#enter sib2, iclass 7, count 0 2006.257.03:53:14.23#ibcon#flushed, iclass 7, count 0 2006.257.03:53:14.23#ibcon#about to write, iclass 7, count 0 2006.257.03:53:14.23#ibcon#wrote, iclass 7, count 0 2006.257.03:53:14.23#ibcon#about to read 3, iclass 7, count 0 2006.257.03:53:14.26#ibcon#read 3, iclass 7, count 0 2006.257.03:53:14.26#ibcon#about to read 4, iclass 7, count 0 2006.257.03:53:14.26#ibcon#read 4, iclass 7, count 0 2006.257.03:53:14.26#ibcon#about to read 5, iclass 7, count 0 2006.257.03:53:14.26#ibcon#read 5, iclass 7, count 0 2006.257.03:53:14.26#ibcon#about to read 6, iclass 7, count 0 2006.257.03:53:14.26#ibcon#read 6, iclass 7, count 0 2006.257.03:53:14.26#ibcon#end of sib2, iclass 7, count 0 2006.257.03:53:14.26#ibcon#*after write, iclass 7, count 0 2006.257.03:53:14.26#ibcon#*before return 0, iclass 7, count 0 2006.257.03:53:14.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:14.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.03:53:14.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.03:53:14.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.03:53:14.26$vck44/vblo=5,709.99 2006.257.03:53:14.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.03:53:14.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.03:53:14.26#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:14.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:14.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:14.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:14.26#ibcon#enter wrdev, iclass 11, count 0 2006.257.03:53:14.26#ibcon#first serial, iclass 11, count 0 2006.257.03:53:14.26#ibcon#enter sib2, iclass 11, count 0 2006.257.03:53:14.26#ibcon#flushed, iclass 11, count 0 2006.257.03:53:14.26#ibcon#about to write, iclass 11, count 0 2006.257.03:53:14.26#ibcon#wrote, iclass 11, count 0 2006.257.03:53:14.26#ibcon#about to read 3, iclass 11, count 0 2006.257.03:53:14.28#ibcon#read 3, iclass 11, count 0 2006.257.03:53:14.28#ibcon#about to read 4, iclass 11, count 0 2006.257.03:53:14.28#ibcon#read 4, iclass 11, count 0 2006.257.03:53:14.28#ibcon#about to read 5, iclass 11, count 0 2006.257.03:53:14.28#ibcon#read 5, iclass 11, count 0 2006.257.03:53:14.28#ibcon#about to read 6, iclass 11, count 0 2006.257.03:53:14.28#ibcon#read 6, iclass 11, count 0 2006.257.03:53:14.28#ibcon#end of sib2, iclass 11, count 0 2006.257.03:53:14.28#ibcon#*mode == 0, iclass 11, count 0 2006.257.03:53:14.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.03:53:14.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:53:14.28#ibcon#*before write, iclass 11, count 0 2006.257.03:53:14.28#ibcon#enter sib2, iclass 11, count 0 2006.257.03:53:14.28#ibcon#flushed, iclass 11, count 0 2006.257.03:53:14.28#ibcon#about to write, iclass 11, count 0 2006.257.03:53:14.28#ibcon#wrote, iclass 11, count 0 2006.257.03:53:14.28#ibcon#about to read 3, iclass 11, count 0 2006.257.03:53:14.32#ibcon#read 3, iclass 11, count 0 2006.257.03:53:14.32#ibcon#about to read 4, iclass 11, count 0 2006.257.03:53:14.32#ibcon#read 4, iclass 11, count 0 2006.257.03:53:14.32#ibcon#about to read 5, iclass 11, count 0 2006.257.03:53:14.32#ibcon#read 5, iclass 11, count 0 2006.257.03:53:14.32#ibcon#about to read 6, iclass 11, count 0 2006.257.03:53:14.32#ibcon#read 6, iclass 11, count 0 2006.257.03:53:14.32#ibcon#end of sib2, iclass 11, count 0 2006.257.03:53:14.32#ibcon#*after write, iclass 11, count 0 2006.257.03:53:14.32#ibcon#*before return 0, iclass 11, count 0 2006.257.03:53:14.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:14.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.03:53:14.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.03:53:14.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.03:53:14.32$vck44/vb=5,4 2006.257.03:53:14.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.03:53:14.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.03:53:14.32#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:14.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:14.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:14.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:14.38#ibcon#enter wrdev, iclass 13, count 2 2006.257.03:53:14.38#ibcon#first serial, iclass 13, count 2 2006.257.03:53:14.38#ibcon#enter sib2, iclass 13, count 2 2006.257.03:53:14.38#ibcon#flushed, iclass 13, count 2 2006.257.03:53:14.38#ibcon#about to write, iclass 13, count 2 2006.257.03:53:14.38#ibcon#wrote, iclass 13, count 2 2006.257.03:53:14.38#ibcon#about to read 3, iclass 13, count 2 2006.257.03:53:14.40#ibcon#read 3, iclass 13, count 2 2006.257.03:53:14.40#ibcon#about to read 4, iclass 13, count 2 2006.257.03:53:14.40#ibcon#read 4, iclass 13, count 2 2006.257.03:53:14.40#ibcon#about to read 5, iclass 13, count 2 2006.257.03:53:14.40#ibcon#read 5, iclass 13, count 2 2006.257.03:53:14.40#ibcon#about to read 6, iclass 13, count 2 2006.257.03:53:14.40#ibcon#read 6, iclass 13, count 2 2006.257.03:53:14.40#ibcon#end of sib2, iclass 13, count 2 2006.257.03:53:14.40#ibcon#*mode == 0, iclass 13, count 2 2006.257.03:53:14.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.03:53:14.40#ibcon#[27=AT05-04\r\n] 2006.257.03:53:14.40#ibcon#*before write, iclass 13, count 2 2006.257.03:53:14.40#ibcon#enter sib2, iclass 13, count 2 2006.257.03:53:14.40#ibcon#flushed, iclass 13, count 2 2006.257.03:53:14.40#ibcon#about to write, iclass 13, count 2 2006.257.03:53:14.40#ibcon#wrote, iclass 13, count 2 2006.257.03:53:14.40#ibcon#about to read 3, iclass 13, count 2 2006.257.03:53:14.43#ibcon#read 3, iclass 13, count 2 2006.257.03:53:14.43#ibcon#about to read 4, iclass 13, count 2 2006.257.03:53:14.43#ibcon#read 4, iclass 13, count 2 2006.257.03:53:14.43#ibcon#about to read 5, iclass 13, count 2 2006.257.03:53:14.43#ibcon#read 5, iclass 13, count 2 2006.257.03:53:14.43#ibcon#about to read 6, iclass 13, count 2 2006.257.03:53:14.43#ibcon#read 6, iclass 13, count 2 2006.257.03:53:14.43#ibcon#end of sib2, iclass 13, count 2 2006.257.03:53:14.43#ibcon#*after write, iclass 13, count 2 2006.257.03:53:14.43#ibcon#*before return 0, iclass 13, count 2 2006.257.03:53:14.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:14.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.03:53:14.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.03:53:14.43#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:14.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:14.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:14.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:14.55#ibcon#enter wrdev, iclass 13, count 0 2006.257.03:53:14.55#ibcon#first serial, iclass 13, count 0 2006.257.03:53:14.55#ibcon#enter sib2, iclass 13, count 0 2006.257.03:53:14.55#ibcon#flushed, iclass 13, count 0 2006.257.03:53:14.55#ibcon#about to write, iclass 13, count 0 2006.257.03:53:14.55#ibcon#wrote, iclass 13, count 0 2006.257.03:53:14.55#ibcon#about to read 3, iclass 13, count 0 2006.257.03:53:14.57#ibcon#read 3, iclass 13, count 0 2006.257.03:53:14.57#ibcon#about to read 4, iclass 13, count 0 2006.257.03:53:14.57#ibcon#read 4, iclass 13, count 0 2006.257.03:53:14.57#ibcon#about to read 5, iclass 13, count 0 2006.257.03:53:14.57#ibcon#read 5, iclass 13, count 0 2006.257.03:53:14.57#ibcon#about to read 6, iclass 13, count 0 2006.257.03:53:14.57#ibcon#read 6, iclass 13, count 0 2006.257.03:53:14.57#ibcon#end of sib2, iclass 13, count 0 2006.257.03:53:14.57#ibcon#*mode == 0, iclass 13, count 0 2006.257.03:53:14.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.03:53:14.57#ibcon#[27=USB\r\n] 2006.257.03:53:14.57#ibcon#*before write, iclass 13, count 0 2006.257.03:53:14.57#ibcon#enter sib2, iclass 13, count 0 2006.257.03:53:14.57#ibcon#flushed, iclass 13, count 0 2006.257.03:53:14.57#ibcon#about to write, iclass 13, count 0 2006.257.03:53:14.57#ibcon#wrote, iclass 13, count 0 2006.257.03:53:14.57#ibcon#about to read 3, iclass 13, count 0 2006.257.03:53:14.60#ibcon#read 3, iclass 13, count 0 2006.257.03:53:14.60#ibcon#about to read 4, iclass 13, count 0 2006.257.03:53:14.60#ibcon#read 4, iclass 13, count 0 2006.257.03:53:14.60#ibcon#about to read 5, iclass 13, count 0 2006.257.03:53:14.60#ibcon#read 5, iclass 13, count 0 2006.257.03:53:14.60#ibcon#about to read 6, iclass 13, count 0 2006.257.03:53:14.60#ibcon#read 6, iclass 13, count 0 2006.257.03:53:14.60#ibcon#end of sib2, iclass 13, count 0 2006.257.03:53:14.60#ibcon#*after write, iclass 13, count 0 2006.257.03:53:14.60#ibcon#*before return 0, iclass 13, count 0 2006.257.03:53:14.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:14.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.03:53:14.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.03:53:14.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.03:53:14.60$vck44/vblo=6,719.99 2006.257.03:53:14.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.03:53:14.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.03:53:14.60#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:14.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:14.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:14.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:14.60#ibcon#enter wrdev, iclass 15, count 0 2006.257.03:53:14.60#ibcon#first serial, iclass 15, count 0 2006.257.03:53:14.60#ibcon#enter sib2, iclass 15, count 0 2006.257.03:53:14.60#ibcon#flushed, iclass 15, count 0 2006.257.03:53:14.60#ibcon#about to write, iclass 15, count 0 2006.257.03:53:14.60#ibcon#wrote, iclass 15, count 0 2006.257.03:53:14.60#ibcon#about to read 3, iclass 15, count 0 2006.257.03:53:14.62#ibcon#read 3, iclass 15, count 0 2006.257.03:53:14.62#ibcon#about to read 4, iclass 15, count 0 2006.257.03:53:14.62#ibcon#read 4, iclass 15, count 0 2006.257.03:53:14.62#ibcon#about to read 5, iclass 15, count 0 2006.257.03:53:14.62#ibcon#read 5, iclass 15, count 0 2006.257.03:53:14.62#ibcon#about to read 6, iclass 15, count 0 2006.257.03:53:14.62#ibcon#read 6, iclass 15, count 0 2006.257.03:53:14.62#ibcon#end of sib2, iclass 15, count 0 2006.257.03:53:14.62#ibcon#*mode == 0, iclass 15, count 0 2006.257.03:53:14.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.03:53:14.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:53:14.62#ibcon#*before write, iclass 15, count 0 2006.257.03:53:14.62#ibcon#enter sib2, iclass 15, count 0 2006.257.03:53:14.62#ibcon#flushed, iclass 15, count 0 2006.257.03:53:14.62#ibcon#about to write, iclass 15, count 0 2006.257.03:53:14.62#ibcon#wrote, iclass 15, count 0 2006.257.03:53:14.62#ibcon#about to read 3, iclass 15, count 0 2006.257.03:53:14.66#ibcon#read 3, iclass 15, count 0 2006.257.03:53:14.66#ibcon#about to read 4, iclass 15, count 0 2006.257.03:53:14.66#ibcon#read 4, iclass 15, count 0 2006.257.03:53:14.66#ibcon#about to read 5, iclass 15, count 0 2006.257.03:53:14.66#ibcon#read 5, iclass 15, count 0 2006.257.03:53:14.66#ibcon#about to read 6, iclass 15, count 0 2006.257.03:53:14.66#ibcon#read 6, iclass 15, count 0 2006.257.03:53:14.66#ibcon#end of sib2, iclass 15, count 0 2006.257.03:53:14.66#ibcon#*after write, iclass 15, count 0 2006.257.03:53:14.66#ibcon#*before return 0, iclass 15, count 0 2006.257.03:53:14.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:14.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.03:53:14.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.03:53:14.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.03:53:14.66$vck44/vb=6,4 2006.257.03:53:14.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.03:53:14.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.03:53:14.66#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:14.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:14.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:14.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:14.72#ibcon#enter wrdev, iclass 17, count 2 2006.257.03:53:14.72#ibcon#first serial, iclass 17, count 2 2006.257.03:53:14.72#ibcon#enter sib2, iclass 17, count 2 2006.257.03:53:14.72#ibcon#flushed, iclass 17, count 2 2006.257.03:53:14.72#ibcon#about to write, iclass 17, count 2 2006.257.03:53:14.72#ibcon#wrote, iclass 17, count 2 2006.257.03:53:14.72#ibcon#about to read 3, iclass 17, count 2 2006.257.03:53:14.74#ibcon#read 3, iclass 17, count 2 2006.257.03:53:14.74#ibcon#about to read 4, iclass 17, count 2 2006.257.03:53:14.74#ibcon#read 4, iclass 17, count 2 2006.257.03:53:14.74#ibcon#about to read 5, iclass 17, count 2 2006.257.03:53:14.74#ibcon#read 5, iclass 17, count 2 2006.257.03:53:14.74#ibcon#about to read 6, iclass 17, count 2 2006.257.03:53:14.74#ibcon#read 6, iclass 17, count 2 2006.257.03:53:14.74#ibcon#end of sib2, iclass 17, count 2 2006.257.03:53:14.74#ibcon#*mode == 0, iclass 17, count 2 2006.257.03:53:14.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.03:53:14.74#ibcon#[27=AT06-04\r\n] 2006.257.03:53:14.74#ibcon#*before write, iclass 17, count 2 2006.257.03:53:14.74#ibcon#enter sib2, iclass 17, count 2 2006.257.03:53:14.74#ibcon#flushed, iclass 17, count 2 2006.257.03:53:14.74#ibcon#about to write, iclass 17, count 2 2006.257.03:53:14.74#ibcon#wrote, iclass 17, count 2 2006.257.03:53:14.74#ibcon#about to read 3, iclass 17, count 2 2006.257.03:53:14.77#ibcon#read 3, iclass 17, count 2 2006.257.03:53:14.77#ibcon#about to read 4, iclass 17, count 2 2006.257.03:53:14.77#ibcon#read 4, iclass 17, count 2 2006.257.03:53:14.77#ibcon#about to read 5, iclass 17, count 2 2006.257.03:53:14.77#ibcon#read 5, iclass 17, count 2 2006.257.03:53:14.77#ibcon#about to read 6, iclass 17, count 2 2006.257.03:53:14.77#ibcon#read 6, iclass 17, count 2 2006.257.03:53:14.77#ibcon#end of sib2, iclass 17, count 2 2006.257.03:53:14.77#ibcon#*after write, iclass 17, count 2 2006.257.03:53:14.77#ibcon#*before return 0, iclass 17, count 2 2006.257.03:53:14.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:14.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.03:53:14.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.03:53:14.77#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:14.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:14.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:14.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:14.89#ibcon#enter wrdev, iclass 17, count 0 2006.257.03:53:14.89#ibcon#first serial, iclass 17, count 0 2006.257.03:53:14.89#ibcon#enter sib2, iclass 17, count 0 2006.257.03:53:14.89#ibcon#flushed, iclass 17, count 0 2006.257.03:53:14.89#ibcon#about to write, iclass 17, count 0 2006.257.03:53:14.89#ibcon#wrote, iclass 17, count 0 2006.257.03:53:14.89#ibcon#about to read 3, iclass 17, count 0 2006.257.03:53:14.91#ibcon#read 3, iclass 17, count 0 2006.257.03:53:14.91#ibcon#about to read 4, iclass 17, count 0 2006.257.03:53:14.91#ibcon#read 4, iclass 17, count 0 2006.257.03:53:14.91#ibcon#about to read 5, iclass 17, count 0 2006.257.03:53:14.91#ibcon#read 5, iclass 17, count 0 2006.257.03:53:14.91#ibcon#about to read 6, iclass 17, count 0 2006.257.03:53:14.91#ibcon#read 6, iclass 17, count 0 2006.257.03:53:14.91#ibcon#end of sib2, iclass 17, count 0 2006.257.03:53:14.91#ibcon#*mode == 0, iclass 17, count 0 2006.257.03:53:14.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.03:53:14.91#ibcon#[27=USB\r\n] 2006.257.03:53:14.91#ibcon#*before write, iclass 17, count 0 2006.257.03:53:14.91#ibcon#enter sib2, iclass 17, count 0 2006.257.03:53:14.91#ibcon#flushed, iclass 17, count 0 2006.257.03:53:14.91#ibcon#about to write, iclass 17, count 0 2006.257.03:53:14.91#ibcon#wrote, iclass 17, count 0 2006.257.03:53:14.91#ibcon#about to read 3, iclass 17, count 0 2006.257.03:53:14.94#ibcon#read 3, iclass 17, count 0 2006.257.03:53:14.94#ibcon#about to read 4, iclass 17, count 0 2006.257.03:53:14.94#ibcon#read 4, iclass 17, count 0 2006.257.03:53:14.94#ibcon#about to read 5, iclass 17, count 0 2006.257.03:53:14.94#ibcon#read 5, iclass 17, count 0 2006.257.03:53:14.94#ibcon#about to read 6, iclass 17, count 0 2006.257.03:53:14.94#ibcon#read 6, iclass 17, count 0 2006.257.03:53:14.94#ibcon#end of sib2, iclass 17, count 0 2006.257.03:53:14.94#ibcon#*after write, iclass 17, count 0 2006.257.03:53:14.94#ibcon#*before return 0, iclass 17, count 0 2006.257.03:53:14.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:14.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.03:53:14.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.03:53:14.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.03:53:14.94$vck44/vblo=7,734.99 2006.257.03:53:14.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.03:53:14.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.03:53:14.94#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:14.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:14.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:14.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:14.94#ibcon#enter wrdev, iclass 19, count 0 2006.257.03:53:14.94#ibcon#first serial, iclass 19, count 0 2006.257.03:53:14.94#ibcon#enter sib2, iclass 19, count 0 2006.257.03:53:14.94#ibcon#flushed, iclass 19, count 0 2006.257.03:53:14.94#ibcon#about to write, iclass 19, count 0 2006.257.03:53:14.94#ibcon#wrote, iclass 19, count 0 2006.257.03:53:14.94#ibcon#about to read 3, iclass 19, count 0 2006.257.03:53:14.96#ibcon#read 3, iclass 19, count 0 2006.257.03:53:14.96#ibcon#about to read 4, iclass 19, count 0 2006.257.03:53:14.96#ibcon#read 4, iclass 19, count 0 2006.257.03:53:14.96#ibcon#about to read 5, iclass 19, count 0 2006.257.03:53:14.96#ibcon#read 5, iclass 19, count 0 2006.257.03:53:14.96#ibcon#about to read 6, iclass 19, count 0 2006.257.03:53:14.96#ibcon#read 6, iclass 19, count 0 2006.257.03:53:14.96#ibcon#end of sib2, iclass 19, count 0 2006.257.03:53:14.96#ibcon#*mode == 0, iclass 19, count 0 2006.257.03:53:14.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.03:53:14.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:53:14.96#ibcon#*before write, iclass 19, count 0 2006.257.03:53:14.96#ibcon#enter sib2, iclass 19, count 0 2006.257.03:53:14.96#ibcon#flushed, iclass 19, count 0 2006.257.03:53:14.96#ibcon#about to write, iclass 19, count 0 2006.257.03:53:14.96#ibcon#wrote, iclass 19, count 0 2006.257.03:53:14.96#ibcon#about to read 3, iclass 19, count 0 2006.257.03:53:15.00#ibcon#read 3, iclass 19, count 0 2006.257.03:53:15.00#ibcon#about to read 4, iclass 19, count 0 2006.257.03:53:15.00#ibcon#read 4, iclass 19, count 0 2006.257.03:53:15.00#ibcon#about to read 5, iclass 19, count 0 2006.257.03:53:15.00#ibcon#read 5, iclass 19, count 0 2006.257.03:53:15.00#ibcon#about to read 6, iclass 19, count 0 2006.257.03:53:15.00#ibcon#read 6, iclass 19, count 0 2006.257.03:53:15.00#ibcon#end of sib2, iclass 19, count 0 2006.257.03:53:15.00#ibcon#*after write, iclass 19, count 0 2006.257.03:53:15.00#ibcon#*before return 0, iclass 19, count 0 2006.257.03:53:15.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:15.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.03:53:15.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.03:53:15.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.03:53:15.00$vck44/vb=7,4 2006.257.03:53:15.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.03:53:15.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.03:53:15.00#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:15.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:15.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:15.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:15.06#ibcon#enter wrdev, iclass 21, count 2 2006.257.03:53:15.06#ibcon#first serial, iclass 21, count 2 2006.257.03:53:15.06#ibcon#enter sib2, iclass 21, count 2 2006.257.03:53:15.06#ibcon#flushed, iclass 21, count 2 2006.257.03:53:15.06#ibcon#about to write, iclass 21, count 2 2006.257.03:53:15.06#ibcon#wrote, iclass 21, count 2 2006.257.03:53:15.06#ibcon#about to read 3, iclass 21, count 2 2006.257.03:53:15.08#ibcon#read 3, iclass 21, count 2 2006.257.03:53:15.08#ibcon#about to read 4, iclass 21, count 2 2006.257.03:53:15.08#ibcon#read 4, iclass 21, count 2 2006.257.03:53:15.08#ibcon#about to read 5, iclass 21, count 2 2006.257.03:53:15.08#ibcon#read 5, iclass 21, count 2 2006.257.03:53:15.08#ibcon#about to read 6, iclass 21, count 2 2006.257.03:53:15.08#ibcon#read 6, iclass 21, count 2 2006.257.03:53:15.08#ibcon#end of sib2, iclass 21, count 2 2006.257.03:53:15.08#ibcon#*mode == 0, iclass 21, count 2 2006.257.03:53:15.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.03:53:15.08#ibcon#[27=AT07-04\r\n] 2006.257.03:53:15.08#ibcon#*before write, iclass 21, count 2 2006.257.03:53:15.08#ibcon#enter sib2, iclass 21, count 2 2006.257.03:53:15.08#ibcon#flushed, iclass 21, count 2 2006.257.03:53:15.08#ibcon#about to write, iclass 21, count 2 2006.257.03:53:15.08#ibcon#wrote, iclass 21, count 2 2006.257.03:53:15.08#ibcon#about to read 3, iclass 21, count 2 2006.257.03:53:15.11#ibcon#read 3, iclass 21, count 2 2006.257.03:53:15.11#ibcon#about to read 4, iclass 21, count 2 2006.257.03:53:15.11#ibcon#read 4, iclass 21, count 2 2006.257.03:53:15.11#ibcon#about to read 5, iclass 21, count 2 2006.257.03:53:15.11#ibcon#read 5, iclass 21, count 2 2006.257.03:53:15.11#ibcon#about to read 6, iclass 21, count 2 2006.257.03:53:15.11#ibcon#read 6, iclass 21, count 2 2006.257.03:53:15.11#ibcon#end of sib2, iclass 21, count 2 2006.257.03:53:15.11#ibcon#*after write, iclass 21, count 2 2006.257.03:53:15.11#ibcon#*before return 0, iclass 21, count 2 2006.257.03:53:15.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:15.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.03:53:15.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.03:53:15.11#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:15.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:15.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:15.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:15.23#ibcon#enter wrdev, iclass 21, count 0 2006.257.03:53:15.23#ibcon#first serial, iclass 21, count 0 2006.257.03:53:15.23#ibcon#enter sib2, iclass 21, count 0 2006.257.03:53:15.23#ibcon#flushed, iclass 21, count 0 2006.257.03:53:15.23#ibcon#about to write, iclass 21, count 0 2006.257.03:53:15.23#ibcon#wrote, iclass 21, count 0 2006.257.03:53:15.23#ibcon#about to read 3, iclass 21, count 0 2006.257.03:53:15.25#ibcon#read 3, iclass 21, count 0 2006.257.03:53:15.25#ibcon#about to read 4, iclass 21, count 0 2006.257.03:53:15.25#ibcon#read 4, iclass 21, count 0 2006.257.03:53:15.25#ibcon#about to read 5, iclass 21, count 0 2006.257.03:53:15.25#ibcon#read 5, iclass 21, count 0 2006.257.03:53:15.25#ibcon#about to read 6, iclass 21, count 0 2006.257.03:53:15.25#ibcon#read 6, iclass 21, count 0 2006.257.03:53:15.25#ibcon#end of sib2, iclass 21, count 0 2006.257.03:53:15.25#ibcon#*mode == 0, iclass 21, count 0 2006.257.03:53:15.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.03:53:15.25#ibcon#[27=USB\r\n] 2006.257.03:53:15.25#ibcon#*before write, iclass 21, count 0 2006.257.03:53:15.25#ibcon#enter sib2, iclass 21, count 0 2006.257.03:53:15.25#ibcon#flushed, iclass 21, count 0 2006.257.03:53:15.25#ibcon#about to write, iclass 21, count 0 2006.257.03:53:15.25#ibcon#wrote, iclass 21, count 0 2006.257.03:53:15.25#ibcon#about to read 3, iclass 21, count 0 2006.257.03:53:15.28#ibcon#read 3, iclass 21, count 0 2006.257.03:53:15.28#ibcon#about to read 4, iclass 21, count 0 2006.257.03:53:15.28#ibcon#read 4, iclass 21, count 0 2006.257.03:53:15.28#ibcon#about to read 5, iclass 21, count 0 2006.257.03:53:15.28#ibcon#read 5, iclass 21, count 0 2006.257.03:53:15.28#ibcon#about to read 6, iclass 21, count 0 2006.257.03:53:15.28#ibcon#read 6, iclass 21, count 0 2006.257.03:53:15.28#ibcon#end of sib2, iclass 21, count 0 2006.257.03:53:15.28#ibcon#*after write, iclass 21, count 0 2006.257.03:53:15.28#ibcon#*before return 0, iclass 21, count 0 2006.257.03:53:15.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:15.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.03:53:15.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.03:53:15.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.03:53:15.28$vck44/vblo=8,744.99 2006.257.03:53:15.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.03:53:15.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.03:53:15.28#ibcon#ireg 17 cls_cnt 0 2006.257.03:53:15.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:15.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:15.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:15.28#ibcon#enter wrdev, iclass 23, count 0 2006.257.03:53:15.28#ibcon#first serial, iclass 23, count 0 2006.257.03:53:15.28#ibcon#enter sib2, iclass 23, count 0 2006.257.03:53:15.28#ibcon#flushed, iclass 23, count 0 2006.257.03:53:15.28#ibcon#about to write, iclass 23, count 0 2006.257.03:53:15.28#ibcon#wrote, iclass 23, count 0 2006.257.03:53:15.28#ibcon#about to read 3, iclass 23, count 0 2006.257.03:53:15.30#ibcon#read 3, iclass 23, count 0 2006.257.03:53:15.30#ibcon#about to read 4, iclass 23, count 0 2006.257.03:53:15.30#ibcon#read 4, iclass 23, count 0 2006.257.03:53:15.30#ibcon#about to read 5, iclass 23, count 0 2006.257.03:53:15.30#ibcon#read 5, iclass 23, count 0 2006.257.03:53:15.30#ibcon#about to read 6, iclass 23, count 0 2006.257.03:53:15.30#ibcon#read 6, iclass 23, count 0 2006.257.03:53:15.30#ibcon#end of sib2, iclass 23, count 0 2006.257.03:53:15.30#ibcon#*mode == 0, iclass 23, count 0 2006.257.03:53:15.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.03:53:15.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:53:15.30#ibcon#*before write, iclass 23, count 0 2006.257.03:53:15.30#ibcon#enter sib2, iclass 23, count 0 2006.257.03:53:15.30#ibcon#flushed, iclass 23, count 0 2006.257.03:53:15.30#ibcon#about to write, iclass 23, count 0 2006.257.03:53:15.30#ibcon#wrote, iclass 23, count 0 2006.257.03:53:15.30#ibcon#about to read 3, iclass 23, count 0 2006.257.03:53:15.34#ibcon#read 3, iclass 23, count 0 2006.257.03:53:15.34#ibcon#about to read 4, iclass 23, count 0 2006.257.03:53:15.34#ibcon#read 4, iclass 23, count 0 2006.257.03:53:15.34#ibcon#about to read 5, iclass 23, count 0 2006.257.03:53:15.34#ibcon#read 5, iclass 23, count 0 2006.257.03:53:15.34#ibcon#about to read 6, iclass 23, count 0 2006.257.03:53:15.34#ibcon#read 6, iclass 23, count 0 2006.257.03:53:15.34#ibcon#end of sib2, iclass 23, count 0 2006.257.03:53:15.34#ibcon#*after write, iclass 23, count 0 2006.257.03:53:15.34#ibcon#*before return 0, iclass 23, count 0 2006.257.03:53:15.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:15.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.03:53:15.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.03:53:15.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.03:53:15.34$vck44/vb=8,4 2006.257.03:53:15.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.03:53:15.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.03:53:15.34#ibcon#ireg 11 cls_cnt 2 2006.257.03:53:15.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:15.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:15.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:15.40#ibcon#enter wrdev, iclass 25, count 2 2006.257.03:53:15.40#ibcon#first serial, iclass 25, count 2 2006.257.03:53:15.40#ibcon#enter sib2, iclass 25, count 2 2006.257.03:53:15.40#ibcon#flushed, iclass 25, count 2 2006.257.03:53:15.40#ibcon#about to write, iclass 25, count 2 2006.257.03:53:15.40#ibcon#wrote, iclass 25, count 2 2006.257.03:53:15.40#ibcon#about to read 3, iclass 25, count 2 2006.257.03:53:15.42#ibcon#read 3, iclass 25, count 2 2006.257.03:53:15.42#ibcon#about to read 4, iclass 25, count 2 2006.257.03:53:15.42#ibcon#read 4, iclass 25, count 2 2006.257.03:53:15.42#ibcon#about to read 5, iclass 25, count 2 2006.257.03:53:15.42#ibcon#read 5, iclass 25, count 2 2006.257.03:53:15.42#ibcon#about to read 6, iclass 25, count 2 2006.257.03:53:15.42#ibcon#read 6, iclass 25, count 2 2006.257.03:53:15.42#ibcon#end of sib2, iclass 25, count 2 2006.257.03:53:15.42#ibcon#*mode == 0, iclass 25, count 2 2006.257.03:53:15.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.03:53:15.42#ibcon#[27=AT08-04\r\n] 2006.257.03:53:15.42#ibcon#*before write, iclass 25, count 2 2006.257.03:53:15.42#ibcon#enter sib2, iclass 25, count 2 2006.257.03:53:15.42#ibcon#flushed, iclass 25, count 2 2006.257.03:53:15.42#ibcon#about to write, iclass 25, count 2 2006.257.03:53:15.42#ibcon#wrote, iclass 25, count 2 2006.257.03:53:15.42#ibcon#about to read 3, iclass 25, count 2 2006.257.03:53:15.45#ibcon#read 3, iclass 25, count 2 2006.257.03:53:15.45#ibcon#about to read 4, iclass 25, count 2 2006.257.03:53:15.45#ibcon#read 4, iclass 25, count 2 2006.257.03:53:15.45#ibcon#about to read 5, iclass 25, count 2 2006.257.03:53:15.45#ibcon#read 5, iclass 25, count 2 2006.257.03:53:15.45#ibcon#about to read 6, iclass 25, count 2 2006.257.03:53:15.45#ibcon#read 6, iclass 25, count 2 2006.257.03:53:15.45#ibcon#end of sib2, iclass 25, count 2 2006.257.03:53:15.45#ibcon#*after write, iclass 25, count 2 2006.257.03:53:15.45#ibcon#*before return 0, iclass 25, count 2 2006.257.03:53:15.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:15.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.03:53:15.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.03:53:15.45#ibcon#ireg 7 cls_cnt 0 2006.257.03:53:15.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:15.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:15.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:15.57#ibcon#enter wrdev, iclass 25, count 0 2006.257.03:53:15.57#ibcon#first serial, iclass 25, count 0 2006.257.03:53:15.57#ibcon#enter sib2, iclass 25, count 0 2006.257.03:53:15.57#ibcon#flushed, iclass 25, count 0 2006.257.03:53:15.57#ibcon#about to write, iclass 25, count 0 2006.257.03:53:15.57#ibcon#wrote, iclass 25, count 0 2006.257.03:53:15.57#ibcon#about to read 3, iclass 25, count 0 2006.257.03:53:15.59#ibcon#read 3, iclass 25, count 0 2006.257.03:53:15.59#ibcon#about to read 4, iclass 25, count 0 2006.257.03:53:15.59#ibcon#read 4, iclass 25, count 0 2006.257.03:53:15.59#ibcon#about to read 5, iclass 25, count 0 2006.257.03:53:15.59#ibcon#read 5, iclass 25, count 0 2006.257.03:53:15.59#ibcon#about to read 6, iclass 25, count 0 2006.257.03:53:15.59#ibcon#read 6, iclass 25, count 0 2006.257.03:53:15.59#ibcon#end of sib2, iclass 25, count 0 2006.257.03:53:15.59#ibcon#*mode == 0, iclass 25, count 0 2006.257.03:53:15.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.03:53:15.59#ibcon#[27=USB\r\n] 2006.257.03:53:15.59#ibcon#*before write, iclass 25, count 0 2006.257.03:53:15.59#ibcon#enter sib2, iclass 25, count 0 2006.257.03:53:15.59#ibcon#flushed, iclass 25, count 0 2006.257.03:53:15.59#ibcon#about to write, iclass 25, count 0 2006.257.03:53:15.59#ibcon#wrote, iclass 25, count 0 2006.257.03:53:15.59#ibcon#about to read 3, iclass 25, count 0 2006.257.03:53:15.62#ibcon#read 3, iclass 25, count 0 2006.257.03:53:15.62#ibcon#about to read 4, iclass 25, count 0 2006.257.03:53:15.62#ibcon#read 4, iclass 25, count 0 2006.257.03:53:15.62#ibcon#about to read 5, iclass 25, count 0 2006.257.03:53:15.62#ibcon#read 5, iclass 25, count 0 2006.257.03:53:15.62#ibcon#about to read 6, iclass 25, count 0 2006.257.03:53:15.62#ibcon#read 6, iclass 25, count 0 2006.257.03:53:15.62#ibcon#end of sib2, iclass 25, count 0 2006.257.03:53:15.62#ibcon#*after write, iclass 25, count 0 2006.257.03:53:15.62#ibcon#*before return 0, iclass 25, count 0 2006.257.03:53:15.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:15.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.03:53:15.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.03:53:15.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.03:53:15.62$vck44/vabw=wide 2006.257.03:53:15.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.03:53:15.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.03:53:15.62#ibcon#ireg 8 cls_cnt 0 2006.257.03:53:15.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:15.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:15.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:15.62#ibcon#enter wrdev, iclass 27, count 0 2006.257.03:53:15.62#ibcon#first serial, iclass 27, count 0 2006.257.03:53:15.62#ibcon#enter sib2, iclass 27, count 0 2006.257.03:53:15.62#ibcon#flushed, iclass 27, count 0 2006.257.03:53:15.62#ibcon#about to write, iclass 27, count 0 2006.257.03:53:15.62#ibcon#wrote, iclass 27, count 0 2006.257.03:53:15.62#ibcon#about to read 3, iclass 27, count 0 2006.257.03:53:15.64#ibcon#read 3, iclass 27, count 0 2006.257.03:53:15.64#ibcon#about to read 4, iclass 27, count 0 2006.257.03:53:15.64#ibcon#read 4, iclass 27, count 0 2006.257.03:53:15.64#ibcon#about to read 5, iclass 27, count 0 2006.257.03:53:15.64#ibcon#read 5, iclass 27, count 0 2006.257.03:53:15.64#ibcon#about to read 6, iclass 27, count 0 2006.257.03:53:15.64#ibcon#read 6, iclass 27, count 0 2006.257.03:53:15.64#ibcon#end of sib2, iclass 27, count 0 2006.257.03:53:15.64#ibcon#*mode == 0, iclass 27, count 0 2006.257.03:53:15.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.03:53:15.64#ibcon#[25=BW32\r\n] 2006.257.03:53:15.64#ibcon#*before write, iclass 27, count 0 2006.257.03:53:15.64#ibcon#enter sib2, iclass 27, count 0 2006.257.03:53:15.64#ibcon#flushed, iclass 27, count 0 2006.257.03:53:15.64#ibcon#about to write, iclass 27, count 0 2006.257.03:53:15.64#ibcon#wrote, iclass 27, count 0 2006.257.03:53:15.64#ibcon#about to read 3, iclass 27, count 0 2006.257.03:53:15.67#ibcon#read 3, iclass 27, count 0 2006.257.03:53:15.67#ibcon#about to read 4, iclass 27, count 0 2006.257.03:53:15.67#ibcon#read 4, iclass 27, count 0 2006.257.03:53:15.67#ibcon#about to read 5, iclass 27, count 0 2006.257.03:53:15.67#ibcon#read 5, iclass 27, count 0 2006.257.03:53:15.67#ibcon#about to read 6, iclass 27, count 0 2006.257.03:53:15.67#ibcon#read 6, iclass 27, count 0 2006.257.03:53:15.67#ibcon#end of sib2, iclass 27, count 0 2006.257.03:53:15.67#ibcon#*after write, iclass 27, count 0 2006.257.03:53:15.67#ibcon#*before return 0, iclass 27, count 0 2006.257.03:53:15.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:15.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.03:53:15.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.03:53:15.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.03:53:15.67$vck44/vbbw=wide 2006.257.03:53:15.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.03:53:15.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.03:53:15.67#ibcon#ireg 8 cls_cnt 0 2006.257.03:53:15.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:53:15.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:53:15.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:53:15.74#ibcon#enter wrdev, iclass 29, count 0 2006.257.03:53:15.74#ibcon#first serial, iclass 29, count 0 2006.257.03:53:15.74#ibcon#enter sib2, iclass 29, count 0 2006.257.03:53:15.74#ibcon#flushed, iclass 29, count 0 2006.257.03:53:15.74#ibcon#about to write, iclass 29, count 0 2006.257.03:53:15.74#ibcon#wrote, iclass 29, count 0 2006.257.03:53:15.74#ibcon#about to read 3, iclass 29, count 0 2006.257.03:53:15.76#ibcon#read 3, iclass 29, count 0 2006.257.03:53:15.76#ibcon#about to read 4, iclass 29, count 0 2006.257.03:53:15.76#ibcon#read 4, iclass 29, count 0 2006.257.03:53:15.76#ibcon#about to read 5, iclass 29, count 0 2006.257.03:53:15.76#ibcon#read 5, iclass 29, count 0 2006.257.03:53:15.76#ibcon#about to read 6, iclass 29, count 0 2006.257.03:53:15.76#ibcon#read 6, iclass 29, count 0 2006.257.03:53:15.76#ibcon#end of sib2, iclass 29, count 0 2006.257.03:53:15.76#ibcon#*mode == 0, iclass 29, count 0 2006.257.03:53:15.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.03:53:15.76#ibcon#[27=BW32\r\n] 2006.257.03:53:15.76#ibcon#*before write, iclass 29, count 0 2006.257.03:53:15.76#ibcon#enter sib2, iclass 29, count 0 2006.257.03:53:15.76#ibcon#flushed, iclass 29, count 0 2006.257.03:53:15.76#ibcon#about to write, iclass 29, count 0 2006.257.03:53:15.76#ibcon#wrote, iclass 29, count 0 2006.257.03:53:15.76#ibcon#about to read 3, iclass 29, count 0 2006.257.03:53:15.79#ibcon#read 3, iclass 29, count 0 2006.257.03:53:15.79#ibcon#about to read 4, iclass 29, count 0 2006.257.03:53:15.79#ibcon#read 4, iclass 29, count 0 2006.257.03:53:15.79#ibcon#about to read 5, iclass 29, count 0 2006.257.03:53:15.79#ibcon#read 5, iclass 29, count 0 2006.257.03:53:15.79#ibcon#about to read 6, iclass 29, count 0 2006.257.03:53:15.79#ibcon#read 6, iclass 29, count 0 2006.257.03:53:15.79#ibcon#end of sib2, iclass 29, count 0 2006.257.03:53:15.79#ibcon#*after write, iclass 29, count 0 2006.257.03:53:15.79#ibcon#*before return 0, iclass 29, count 0 2006.257.03:53:15.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:53:15.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.03:53:15.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.03:53:15.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.03:53:15.79$setupk4/ifdk4 2006.257.03:53:15.79$ifdk4/lo= 2006.257.03:53:15.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:53:15.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:53:15.79$ifdk4/patch= 2006.257.03:53:15.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:53:15.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:53:15.79$setupk4/!*+20s 2006.257.03:53:16.70#abcon#<5=/13 1.6 6.8 19.29 951012.2\r\n> 2006.257.03:53:16.72#abcon#{5=INTERFACE CLEAR} 2006.257.03:53:16.78#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:53:26.87#abcon#<5=/13 1.7 6.8 19.29 951012.2\r\n> 2006.257.03:53:26.89#abcon#{5=INTERFACE CLEAR} 2006.257.03:53:26.95#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:53:30.30$setupk4/"tpicd 2006.257.03:53:30.30$setupk4/echo=off 2006.257.03:53:30.30$setupk4/xlog=off 2006.257.03:53:30.30:!2006.257.03:58:08 2006.257.03:53:40.13#trakl#Source acquired 2006.257.03:53:41.13#flagr#flagr/antenna,acquired 2006.257.03:58:08.00:preob 2006.257.03:58:09.14/onsource/TRACKING 2006.257.03:58:09.14:!2006.257.03:58:18 2006.257.03:58:18.00:"tape 2006.257.03:58:18.00:"st=record 2006.257.03:58:18.00:data_valid=on 2006.257.03:58:18.00:midob 2006.257.03:58:18.14/onsource/TRACKING 2006.257.03:58:18.14/wx/19.16,1012.1,95 2006.257.03:58:18.27/cable/+6.4863E-03 2006.257.03:58:19.36/va/01,08,usb,yes,37,40 2006.257.03:58:19.36/va/02,07,usb,yes,40,40 2006.257.03:58:19.36/va/03,08,usb,yes,36,38 2006.257.03:58:19.36/va/04,07,usb,yes,41,43 2006.257.03:58:19.36/va/05,04,usb,yes,37,37 2006.257.03:58:19.36/va/06,04,usb,yes,41,40 2006.257.03:58:19.36/va/07,04,usb,yes,42,42 2006.257.03:58:19.36/va/08,04,usb,yes,35,43 2006.257.03:58:19.59/valo/01,524.99,yes,locked 2006.257.03:58:19.59/valo/02,534.99,yes,locked 2006.257.03:58:19.59/valo/03,564.99,yes,locked 2006.257.03:58:19.59/valo/04,624.99,yes,locked 2006.257.03:58:19.59/valo/05,734.99,yes,locked 2006.257.03:58:19.59/valo/06,814.99,yes,locked 2006.257.03:58:19.59/valo/07,864.99,yes,locked 2006.257.03:58:19.59/valo/08,884.99,yes,locked 2006.257.03:58:20.68/vb/01,04,usb,yes,33,32 2006.257.03:58:20.68/vb/02,05,usb,yes,31,32 2006.257.03:58:20.68/vb/03,04,usb,yes,32,35 2006.257.03:58:20.68/vb/04,05,usb,yes,32,31 2006.257.03:58:20.68/vb/05,04,usb,yes,28,31 2006.257.03:58:20.68/vb/06,04,usb,yes,34,29 2006.257.03:58:20.68/vb/07,04,usb,yes,33,33 2006.257.03:58:20.68/vb/08,04,usb,yes,30,34 2006.257.03:58:20.92/vblo/01,629.99,yes,locked 2006.257.03:58:20.92/vblo/02,634.99,yes,locked 2006.257.03:58:20.92/vblo/03,649.99,yes,locked 2006.257.03:58:20.92/vblo/04,679.99,yes,locked 2006.257.03:58:20.92/vblo/05,709.99,yes,locked 2006.257.03:58:20.92/vblo/06,719.99,yes,locked 2006.257.03:58:20.92/vblo/07,734.99,yes,locked 2006.257.03:58:20.92/vblo/08,744.99,yes,locked 2006.257.03:58:21.07/vabw/8 2006.257.03:58:21.22/vbbw/8 2006.257.03:58:21.37/xfe/off,on,16.7 2006.257.03:58:21.74/ifatt/23,28,28,28 2006.257.03:58:22.08/fmout-gps/S +4.53E-07 2006.257.03:58:22.12:!2006.257.03:58:58 2006.257.03:58:58.01:data_valid=off 2006.257.03:58:58.01:"et 2006.257.03:58:58.01:!+3s 2006.257.03:59:01.02:"tape 2006.257.03:59:01.02:postob 2006.257.03:59:01.15/cable/+6.4842E-03 2006.257.03:59:01.15/wx/19.15,1012.0,95 2006.257.03:59:01.21/fmout-gps/S +4.52E-07 2006.257.03:59:01.21:scan_name=257-0404,jd0609,80 2006.257.03:59:01.21:source=3c274,123049.42,122328.0,2000.0,ccw 2006.257.03:59:03.14#flagr#flagr/antenna,new-source 2006.257.03:59:03.14:checkk5 2006.257.03:59:03.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.03:59:03.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.03:59:04.39/chk_autoobs//k5ts3/ autoobs is running! 2006.257.03:59:04.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.03:59:05.15/chk_obsdata//k5ts1/T2570358??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:59:05.54/chk_obsdata//k5ts2/T2570358??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:59:05.96/chk_obsdata//k5ts3/T2570358??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:59:06.35/chk_obsdata//k5ts4/T2570358??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.03:59:07.08/k5log//k5ts1_log_newline 2006.257.03:59:07.77/k5log//k5ts2_log_newline 2006.257.03:59:08.52/k5log//k5ts3_log_newline 2006.257.03:59:09.24/k5log//k5ts4_log_newline 2006.257.03:59:09.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.03:59:09.26:setupk4=1 2006.257.03:59:09.26$setupk4/echo=on 2006.257.03:59:09.26$setupk4/pcalon 2006.257.03:59:09.26$pcalon/"no phase cal control is implemented here 2006.257.03:59:09.26$setupk4/"tpicd=stop 2006.257.03:59:09.26$setupk4/"rec=synch_on 2006.257.03:59:09.26$setupk4/"rec_mode=128 2006.257.03:59:09.26$setupk4/!* 2006.257.03:59:09.26$setupk4/recpk4 2006.257.03:59:09.26$recpk4/recpatch= 2006.257.03:59:09.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.03:59:09.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.03:59:09.26$setupk4/vck44 2006.257.03:59:09.26$vck44/valo=1,524.99 2006.257.03:59:09.26#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.03:59:09.26#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.03:59:09.26#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:09.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:09.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:09.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:09.26#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:59:09.26#ibcon#first serial, iclass 30, count 0 2006.257.03:59:09.26#ibcon#enter sib2, iclass 30, count 0 2006.257.03:59:09.26#ibcon#flushed, iclass 30, count 0 2006.257.03:59:09.26#ibcon#about to write, iclass 30, count 0 2006.257.03:59:09.26#ibcon#wrote, iclass 30, count 0 2006.257.03:59:09.26#ibcon#about to read 3, iclass 30, count 0 2006.257.03:59:09.28#ibcon#read 3, iclass 30, count 0 2006.257.03:59:09.28#ibcon#about to read 4, iclass 30, count 0 2006.257.03:59:09.28#ibcon#read 4, iclass 30, count 0 2006.257.03:59:09.28#ibcon#about to read 5, iclass 30, count 0 2006.257.03:59:09.28#ibcon#read 5, iclass 30, count 0 2006.257.03:59:09.28#ibcon#about to read 6, iclass 30, count 0 2006.257.03:59:09.28#ibcon#read 6, iclass 30, count 0 2006.257.03:59:09.28#ibcon#end of sib2, iclass 30, count 0 2006.257.03:59:09.28#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:59:09.28#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:59:09.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.03:59:09.28#ibcon#*before write, iclass 30, count 0 2006.257.03:59:09.28#ibcon#enter sib2, iclass 30, count 0 2006.257.03:59:09.28#ibcon#flushed, iclass 30, count 0 2006.257.03:59:09.28#ibcon#about to write, iclass 30, count 0 2006.257.03:59:09.28#ibcon#wrote, iclass 30, count 0 2006.257.03:59:09.28#ibcon#about to read 3, iclass 30, count 0 2006.257.03:59:09.33#ibcon#read 3, iclass 30, count 0 2006.257.03:59:09.33#ibcon#about to read 4, iclass 30, count 0 2006.257.03:59:09.33#ibcon#read 4, iclass 30, count 0 2006.257.03:59:09.33#ibcon#about to read 5, iclass 30, count 0 2006.257.03:59:09.33#ibcon#read 5, iclass 30, count 0 2006.257.03:59:09.33#ibcon#about to read 6, iclass 30, count 0 2006.257.03:59:09.33#ibcon#read 6, iclass 30, count 0 2006.257.03:59:09.33#ibcon#end of sib2, iclass 30, count 0 2006.257.03:59:09.33#ibcon#*after write, iclass 30, count 0 2006.257.03:59:09.33#ibcon#*before return 0, iclass 30, count 0 2006.257.03:59:09.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:09.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:09.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:59:09.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:59:09.33$vck44/va=1,8 2006.257.03:59:09.33#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.03:59:09.33#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.03:59:09.33#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:09.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:09.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:09.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:09.33#ibcon#enter wrdev, iclass 32, count 2 2006.257.03:59:09.33#ibcon#first serial, iclass 32, count 2 2006.257.03:59:09.33#ibcon#enter sib2, iclass 32, count 2 2006.257.03:59:09.33#ibcon#flushed, iclass 32, count 2 2006.257.03:59:09.33#ibcon#about to write, iclass 32, count 2 2006.257.03:59:09.33#ibcon#wrote, iclass 32, count 2 2006.257.03:59:09.33#ibcon#about to read 3, iclass 32, count 2 2006.257.03:59:09.35#ibcon#read 3, iclass 32, count 2 2006.257.03:59:09.35#ibcon#about to read 4, iclass 32, count 2 2006.257.03:59:09.35#ibcon#read 4, iclass 32, count 2 2006.257.03:59:09.35#ibcon#about to read 5, iclass 32, count 2 2006.257.03:59:09.35#ibcon#read 5, iclass 32, count 2 2006.257.03:59:09.35#ibcon#about to read 6, iclass 32, count 2 2006.257.03:59:09.35#ibcon#read 6, iclass 32, count 2 2006.257.03:59:09.35#ibcon#end of sib2, iclass 32, count 2 2006.257.03:59:09.35#ibcon#*mode == 0, iclass 32, count 2 2006.257.03:59:09.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.03:59:09.35#ibcon#[25=AT01-08\r\n] 2006.257.03:59:09.35#ibcon#*before write, iclass 32, count 2 2006.257.03:59:09.35#ibcon#enter sib2, iclass 32, count 2 2006.257.03:59:09.35#ibcon#flushed, iclass 32, count 2 2006.257.03:59:09.35#ibcon#about to write, iclass 32, count 2 2006.257.03:59:09.35#ibcon#wrote, iclass 32, count 2 2006.257.03:59:09.35#ibcon#about to read 3, iclass 32, count 2 2006.257.03:59:09.38#ibcon#read 3, iclass 32, count 2 2006.257.03:59:09.38#ibcon#about to read 4, iclass 32, count 2 2006.257.03:59:09.38#ibcon#read 4, iclass 32, count 2 2006.257.03:59:09.38#ibcon#about to read 5, iclass 32, count 2 2006.257.03:59:09.38#ibcon#read 5, iclass 32, count 2 2006.257.03:59:09.38#ibcon#about to read 6, iclass 32, count 2 2006.257.03:59:09.38#ibcon#read 6, iclass 32, count 2 2006.257.03:59:09.38#ibcon#end of sib2, iclass 32, count 2 2006.257.03:59:09.38#ibcon#*after write, iclass 32, count 2 2006.257.03:59:09.38#ibcon#*before return 0, iclass 32, count 2 2006.257.03:59:09.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:09.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:09.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.03:59:09.38#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:09.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:09.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:09.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:09.50#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:59:09.50#ibcon#first serial, iclass 32, count 0 2006.257.03:59:09.50#ibcon#enter sib2, iclass 32, count 0 2006.257.03:59:09.50#ibcon#flushed, iclass 32, count 0 2006.257.03:59:09.50#ibcon#about to write, iclass 32, count 0 2006.257.03:59:09.50#ibcon#wrote, iclass 32, count 0 2006.257.03:59:09.50#ibcon#about to read 3, iclass 32, count 0 2006.257.03:59:09.52#ibcon#read 3, iclass 32, count 0 2006.257.03:59:09.52#ibcon#about to read 4, iclass 32, count 0 2006.257.03:59:09.52#ibcon#read 4, iclass 32, count 0 2006.257.03:59:09.52#ibcon#about to read 5, iclass 32, count 0 2006.257.03:59:09.52#ibcon#read 5, iclass 32, count 0 2006.257.03:59:09.52#ibcon#about to read 6, iclass 32, count 0 2006.257.03:59:09.52#ibcon#read 6, iclass 32, count 0 2006.257.03:59:09.52#ibcon#end of sib2, iclass 32, count 0 2006.257.03:59:09.52#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:59:09.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:59:09.52#ibcon#[25=USB\r\n] 2006.257.03:59:09.52#ibcon#*before write, iclass 32, count 0 2006.257.03:59:09.52#ibcon#enter sib2, iclass 32, count 0 2006.257.03:59:09.52#ibcon#flushed, iclass 32, count 0 2006.257.03:59:09.52#ibcon#about to write, iclass 32, count 0 2006.257.03:59:09.52#ibcon#wrote, iclass 32, count 0 2006.257.03:59:09.52#ibcon#about to read 3, iclass 32, count 0 2006.257.03:59:09.55#ibcon#read 3, iclass 32, count 0 2006.257.03:59:09.55#ibcon#about to read 4, iclass 32, count 0 2006.257.03:59:09.55#ibcon#read 4, iclass 32, count 0 2006.257.03:59:09.55#ibcon#about to read 5, iclass 32, count 0 2006.257.03:59:09.55#ibcon#read 5, iclass 32, count 0 2006.257.03:59:09.55#ibcon#about to read 6, iclass 32, count 0 2006.257.03:59:09.55#ibcon#read 6, iclass 32, count 0 2006.257.03:59:09.55#ibcon#end of sib2, iclass 32, count 0 2006.257.03:59:09.55#ibcon#*after write, iclass 32, count 0 2006.257.03:59:09.55#ibcon#*before return 0, iclass 32, count 0 2006.257.03:59:09.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:09.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:09.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:59:09.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:59:09.55$vck44/valo=2,534.99 2006.257.03:59:09.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.03:59:09.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.03:59:09.55#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:09.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:09.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:09.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:09.55#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:59:09.55#ibcon#first serial, iclass 34, count 0 2006.257.03:59:09.55#ibcon#enter sib2, iclass 34, count 0 2006.257.03:59:09.55#ibcon#flushed, iclass 34, count 0 2006.257.03:59:09.55#ibcon#about to write, iclass 34, count 0 2006.257.03:59:09.55#ibcon#wrote, iclass 34, count 0 2006.257.03:59:09.55#ibcon#about to read 3, iclass 34, count 0 2006.257.03:59:09.57#ibcon#read 3, iclass 34, count 0 2006.257.03:59:09.57#ibcon#about to read 4, iclass 34, count 0 2006.257.03:59:09.57#ibcon#read 4, iclass 34, count 0 2006.257.03:59:09.57#ibcon#about to read 5, iclass 34, count 0 2006.257.03:59:09.57#ibcon#read 5, iclass 34, count 0 2006.257.03:59:09.57#ibcon#about to read 6, iclass 34, count 0 2006.257.03:59:09.57#ibcon#read 6, iclass 34, count 0 2006.257.03:59:09.57#ibcon#end of sib2, iclass 34, count 0 2006.257.03:59:09.57#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:59:09.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:59:09.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.03:59:09.57#ibcon#*before write, iclass 34, count 0 2006.257.03:59:09.57#ibcon#enter sib2, iclass 34, count 0 2006.257.03:59:09.57#ibcon#flushed, iclass 34, count 0 2006.257.03:59:09.57#ibcon#about to write, iclass 34, count 0 2006.257.03:59:09.57#ibcon#wrote, iclass 34, count 0 2006.257.03:59:09.57#ibcon#about to read 3, iclass 34, count 0 2006.257.03:59:09.61#ibcon#read 3, iclass 34, count 0 2006.257.03:59:09.61#ibcon#about to read 4, iclass 34, count 0 2006.257.03:59:09.61#ibcon#read 4, iclass 34, count 0 2006.257.03:59:09.61#ibcon#about to read 5, iclass 34, count 0 2006.257.03:59:09.61#ibcon#read 5, iclass 34, count 0 2006.257.03:59:09.61#ibcon#about to read 6, iclass 34, count 0 2006.257.03:59:09.61#ibcon#read 6, iclass 34, count 0 2006.257.03:59:09.61#ibcon#end of sib2, iclass 34, count 0 2006.257.03:59:09.61#ibcon#*after write, iclass 34, count 0 2006.257.03:59:09.61#ibcon#*before return 0, iclass 34, count 0 2006.257.03:59:09.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:09.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:09.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:59:09.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:59:09.61$vck44/va=2,7 2006.257.03:59:09.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.03:59:09.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.03:59:09.61#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:09.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:09.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:09.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:09.67#ibcon#enter wrdev, iclass 36, count 2 2006.257.03:59:09.67#ibcon#first serial, iclass 36, count 2 2006.257.03:59:09.67#ibcon#enter sib2, iclass 36, count 2 2006.257.03:59:09.67#ibcon#flushed, iclass 36, count 2 2006.257.03:59:09.67#ibcon#about to write, iclass 36, count 2 2006.257.03:59:09.67#ibcon#wrote, iclass 36, count 2 2006.257.03:59:09.67#ibcon#about to read 3, iclass 36, count 2 2006.257.03:59:09.69#ibcon#read 3, iclass 36, count 2 2006.257.03:59:09.69#ibcon#about to read 4, iclass 36, count 2 2006.257.03:59:09.69#ibcon#read 4, iclass 36, count 2 2006.257.03:59:09.69#ibcon#about to read 5, iclass 36, count 2 2006.257.03:59:09.69#ibcon#read 5, iclass 36, count 2 2006.257.03:59:09.69#ibcon#about to read 6, iclass 36, count 2 2006.257.03:59:09.69#ibcon#read 6, iclass 36, count 2 2006.257.03:59:09.69#ibcon#end of sib2, iclass 36, count 2 2006.257.03:59:09.69#ibcon#*mode == 0, iclass 36, count 2 2006.257.03:59:09.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.03:59:09.69#ibcon#[25=AT02-07\r\n] 2006.257.03:59:09.69#ibcon#*before write, iclass 36, count 2 2006.257.03:59:09.69#ibcon#enter sib2, iclass 36, count 2 2006.257.03:59:09.69#ibcon#flushed, iclass 36, count 2 2006.257.03:59:09.69#ibcon#about to write, iclass 36, count 2 2006.257.03:59:09.69#ibcon#wrote, iclass 36, count 2 2006.257.03:59:09.69#ibcon#about to read 3, iclass 36, count 2 2006.257.03:59:09.72#ibcon#read 3, iclass 36, count 2 2006.257.03:59:09.72#ibcon#about to read 4, iclass 36, count 2 2006.257.03:59:09.72#ibcon#read 4, iclass 36, count 2 2006.257.03:59:09.72#ibcon#about to read 5, iclass 36, count 2 2006.257.03:59:09.72#ibcon#read 5, iclass 36, count 2 2006.257.03:59:09.72#ibcon#about to read 6, iclass 36, count 2 2006.257.03:59:09.72#ibcon#read 6, iclass 36, count 2 2006.257.03:59:09.72#ibcon#end of sib2, iclass 36, count 2 2006.257.03:59:09.72#ibcon#*after write, iclass 36, count 2 2006.257.03:59:09.72#ibcon#*before return 0, iclass 36, count 2 2006.257.03:59:09.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:09.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:09.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.03:59:09.72#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:09.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:09.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:09.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:09.84#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:59:09.84#ibcon#first serial, iclass 36, count 0 2006.257.03:59:09.84#ibcon#enter sib2, iclass 36, count 0 2006.257.03:59:09.84#ibcon#flushed, iclass 36, count 0 2006.257.03:59:09.84#ibcon#about to write, iclass 36, count 0 2006.257.03:59:09.84#ibcon#wrote, iclass 36, count 0 2006.257.03:59:09.84#ibcon#about to read 3, iclass 36, count 0 2006.257.03:59:09.86#ibcon#read 3, iclass 36, count 0 2006.257.03:59:09.86#ibcon#about to read 4, iclass 36, count 0 2006.257.03:59:09.86#ibcon#read 4, iclass 36, count 0 2006.257.03:59:09.86#ibcon#about to read 5, iclass 36, count 0 2006.257.03:59:09.86#ibcon#read 5, iclass 36, count 0 2006.257.03:59:09.86#ibcon#about to read 6, iclass 36, count 0 2006.257.03:59:09.86#ibcon#read 6, iclass 36, count 0 2006.257.03:59:09.86#ibcon#end of sib2, iclass 36, count 0 2006.257.03:59:09.86#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:59:09.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:59:09.86#ibcon#[25=USB\r\n] 2006.257.03:59:09.86#ibcon#*before write, iclass 36, count 0 2006.257.03:59:09.86#ibcon#enter sib2, iclass 36, count 0 2006.257.03:59:09.86#ibcon#flushed, iclass 36, count 0 2006.257.03:59:09.86#ibcon#about to write, iclass 36, count 0 2006.257.03:59:09.86#ibcon#wrote, iclass 36, count 0 2006.257.03:59:09.86#ibcon#about to read 3, iclass 36, count 0 2006.257.03:59:09.89#ibcon#read 3, iclass 36, count 0 2006.257.03:59:09.89#ibcon#about to read 4, iclass 36, count 0 2006.257.03:59:09.89#ibcon#read 4, iclass 36, count 0 2006.257.03:59:09.89#ibcon#about to read 5, iclass 36, count 0 2006.257.03:59:09.89#ibcon#read 5, iclass 36, count 0 2006.257.03:59:09.89#ibcon#about to read 6, iclass 36, count 0 2006.257.03:59:09.89#ibcon#read 6, iclass 36, count 0 2006.257.03:59:09.89#ibcon#end of sib2, iclass 36, count 0 2006.257.03:59:09.89#ibcon#*after write, iclass 36, count 0 2006.257.03:59:09.89#ibcon#*before return 0, iclass 36, count 0 2006.257.03:59:09.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:09.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:09.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:59:09.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:59:09.89$vck44/valo=3,564.99 2006.257.03:59:09.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.03:59:09.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.03:59:09.89#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:09.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:59:09.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:59:09.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:59:09.89#ibcon#enter wrdev, iclass 38, count 0 2006.257.03:59:09.89#ibcon#first serial, iclass 38, count 0 2006.257.03:59:09.89#ibcon#enter sib2, iclass 38, count 0 2006.257.03:59:09.89#ibcon#flushed, iclass 38, count 0 2006.257.03:59:09.89#ibcon#about to write, iclass 38, count 0 2006.257.03:59:09.89#ibcon#wrote, iclass 38, count 0 2006.257.03:59:09.89#ibcon#about to read 3, iclass 38, count 0 2006.257.03:59:09.91#ibcon#read 3, iclass 38, count 0 2006.257.03:59:09.91#ibcon#about to read 4, iclass 38, count 0 2006.257.03:59:09.91#ibcon#read 4, iclass 38, count 0 2006.257.03:59:09.91#ibcon#about to read 5, iclass 38, count 0 2006.257.03:59:09.91#ibcon#read 5, iclass 38, count 0 2006.257.03:59:09.91#ibcon#about to read 6, iclass 38, count 0 2006.257.03:59:09.91#ibcon#read 6, iclass 38, count 0 2006.257.03:59:09.91#ibcon#end of sib2, iclass 38, count 0 2006.257.03:59:09.91#ibcon#*mode == 0, iclass 38, count 0 2006.257.03:59:09.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.03:59:09.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.03:59:09.91#ibcon#*before write, iclass 38, count 0 2006.257.03:59:09.91#ibcon#enter sib2, iclass 38, count 0 2006.257.03:59:09.91#ibcon#flushed, iclass 38, count 0 2006.257.03:59:09.91#ibcon#about to write, iclass 38, count 0 2006.257.03:59:09.91#ibcon#wrote, iclass 38, count 0 2006.257.03:59:09.91#ibcon#about to read 3, iclass 38, count 0 2006.257.03:59:09.95#ibcon#read 3, iclass 38, count 0 2006.257.03:59:09.95#ibcon#about to read 4, iclass 38, count 0 2006.257.03:59:09.95#ibcon#read 4, iclass 38, count 0 2006.257.03:59:09.95#ibcon#about to read 5, iclass 38, count 0 2006.257.03:59:09.95#ibcon#read 5, iclass 38, count 0 2006.257.03:59:09.95#ibcon#about to read 6, iclass 38, count 0 2006.257.03:59:09.95#ibcon#read 6, iclass 38, count 0 2006.257.03:59:09.95#ibcon#end of sib2, iclass 38, count 0 2006.257.03:59:09.95#ibcon#*after write, iclass 38, count 0 2006.257.03:59:09.95#ibcon#*before return 0, iclass 38, count 0 2006.257.03:59:09.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:59:09.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.03:59:09.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.03:59:09.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.03:59:09.95$vck44/va=3,8 2006.257.03:59:09.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.03:59:09.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.03:59:09.95#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:09.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:59:10.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:59:10.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:59:10.01#ibcon#enter wrdev, iclass 40, count 2 2006.257.03:59:10.01#ibcon#first serial, iclass 40, count 2 2006.257.03:59:10.01#ibcon#enter sib2, iclass 40, count 2 2006.257.03:59:10.01#ibcon#flushed, iclass 40, count 2 2006.257.03:59:10.01#ibcon#about to write, iclass 40, count 2 2006.257.03:59:10.01#ibcon#wrote, iclass 40, count 2 2006.257.03:59:10.01#ibcon#about to read 3, iclass 40, count 2 2006.257.03:59:10.03#ibcon#read 3, iclass 40, count 2 2006.257.03:59:10.03#ibcon#about to read 4, iclass 40, count 2 2006.257.03:59:10.03#ibcon#read 4, iclass 40, count 2 2006.257.03:59:10.03#ibcon#about to read 5, iclass 40, count 2 2006.257.03:59:10.03#ibcon#read 5, iclass 40, count 2 2006.257.03:59:10.03#ibcon#about to read 6, iclass 40, count 2 2006.257.03:59:10.03#ibcon#read 6, iclass 40, count 2 2006.257.03:59:10.03#ibcon#end of sib2, iclass 40, count 2 2006.257.03:59:10.03#ibcon#*mode == 0, iclass 40, count 2 2006.257.03:59:10.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.03:59:10.03#ibcon#[25=AT03-08\r\n] 2006.257.03:59:10.03#ibcon#*before write, iclass 40, count 2 2006.257.03:59:10.03#ibcon#enter sib2, iclass 40, count 2 2006.257.03:59:10.03#ibcon#flushed, iclass 40, count 2 2006.257.03:59:10.03#ibcon#about to write, iclass 40, count 2 2006.257.03:59:10.03#ibcon#wrote, iclass 40, count 2 2006.257.03:59:10.03#ibcon#about to read 3, iclass 40, count 2 2006.257.03:59:10.06#ibcon#read 3, iclass 40, count 2 2006.257.03:59:10.06#ibcon#about to read 4, iclass 40, count 2 2006.257.03:59:10.06#ibcon#read 4, iclass 40, count 2 2006.257.03:59:10.06#ibcon#about to read 5, iclass 40, count 2 2006.257.03:59:10.06#ibcon#read 5, iclass 40, count 2 2006.257.03:59:10.06#ibcon#about to read 6, iclass 40, count 2 2006.257.03:59:10.06#ibcon#read 6, iclass 40, count 2 2006.257.03:59:10.06#ibcon#end of sib2, iclass 40, count 2 2006.257.03:59:10.06#ibcon#*after write, iclass 40, count 2 2006.257.03:59:10.06#ibcon#*before return 0, iclass 40, count 2 2006.257.03:59:10.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:59:10.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.03:59:10.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.03:59:10.06#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:10.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:59:10.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:59:10.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:59:10.18#ibcon#enter wrdev, iclass 40, count 0 2006.257.03:59:10.18#ibcon#first serial, iclass 40, count 0 2006.257.03:59:10.18#ibcon#enter sib2, iclass 40, count 0 2006.257.03:59:10.18#ibcon#flushed, iclass 40, count 0 2006.257.03:59:10.18#ibcon#about to write, iclass 40, count 0 2006.257.03:59:10.18#ibcon#wrote, iclass 40, count 0 2006.257.03:59:10.18#ibcon#about to read 3, iclass 40, count 0 2006.257.03:59:10.20#ibcon#read 3, iclass 40, count 0 2006.257.03:59:10.20#ibcon#about to read 4, iclass 40, count 0 2006.257.03:59:10.20#ibcon#read 4, iclass 40, count 0 2006.257.03:59:10.20#ibcon#about to read 5, iclass 40, count 0 2006.257.03:59:10.20#ibcon#read 5, iclass 40, count 0 2006.257.03:59:10.20#ibcon#about to read 6, iclass 40, count 0 2006.257.03:59:10.20#ibcon#read 6, iclass 40, count 0 2006.257.03:59:10.20#ibcon#end of sib2, iclass 40, count 0 2006.257.03:59:10.20#ibcon#*mode == 0, iclass 40, count 0 2006.257.03:59:10.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.03:59:10.20#ibcon#[25=USB\r\n] 2006.257.03:59:10.20#ibcon#*before write, iclass 40, count 0 2006.257.03:59:10.20#ibcon#enter sib2, iclass 40, count 0 2006.257.03:59:10.20#ibcon#flushed, iclass 40, count 0 2006.257.03:59:10.20#ibcon#about to write, iclass 40, count 0 2006.257.03:59:10.20#ibcon#wrote, iclass 40, count 0 2006.257.03:59:10.20#ibcon#about to read 3, iclass 40, count 0 2006.257.03:59:10.23#ibcon#read 3, iclass 40, count 0 2006.257.03:59:10.23#ibcon#about to read 4, iclass 40, count 0 2006.257.03:59:10.23#ibcon#read 4, iclass 40, count 0 2006.257.03:59:10.23#ibcon#about to read 5, iclass 40, count 0 2006.257.03:59:10.23#ibcon#read 5, iclass 40, count 0 2006.257.03:59:10.23#ibcon#about to read 6, iclass 40, count 0 2006.257.03:59:10.23#ibcon#read 6, iclass 40, count 0 2006.257.03:59:10.23#ibcon#end of sib2, iclass 40, count 0 2006.257.03:59:10.23#ibcon#*after write, iclass 40, count 0 2006.257.03:59:10.23#ibcon#*before return 0, iclass 40, count 0 2006.257.03:59:10.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:59:10.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.03:59:10.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.03:59:10.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.03:59:10.23$vck44/valo=4,624.99 2006.257.03:59:10.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.03:59:10.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.03:59:10.23#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:10.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:59:10.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:59:10.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:59:10.23#ibcon#enter wrdev, iclass 4, count 0 2006.257.03:59:10.23#ibcon#first serial, iclass 4, count 0 2006.257.03:59:10.23#ibcon#enter sib2, iclass 4, count 0 2006.257.03:59:10.23#ibcon#flushed, iclass 4, count 0 2006.257.03:59:10.23#ibcon#about to write, iclass 4, count 0 2006.257.03:59:10.23#ibcon#wrote, iclass 4, count 0 2006.257.03:59:10.23#ibcon#about to read 3, iclass 4, count 0 2006.257.03:59:10.25#ibcon#read 3, iclass 4, count 0 2006.257.03:59:10.25#ibcon#about to read 4, iclass 4, count 0 2006.257.03:59:10.25#ibcon#read 4, iclass 4, count 0 2006.257.03:59:10.25#ibcon#about to read 5, iclass 4, count 0 2006.257.03:59:10.25#ibcon#read 5, iclass 4, count 0 2006.257.03:59:10.25#ibcon#about to read 6, iclass 4, count 0 2006.257.03:59:10.25#ibcon#read 6, iclass 4, count 0 2006.257.03:59:10.25#ibcon#end of sib2, iclass 4, count 0 2006.257.03:59:10.25#ibcon#*mode == 0, iclass 4, count 0 2006.257.03:59:10.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.03:59:10.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.03:59:10.25#ibcon#*before write, iclass 4, count 0 2006.257.03:59:10.25#ibcon#enter sib2, iclass 4, count 0 2006.257.03:59:10.25#ibcon#flushed, iclass 4, count 0 2006.257.03:59:10.25#ibcon#about to write, iclass 4, count 0 2006.257.03:59:10.25#ibcon#wrote, iclass 4, count 0 2006.257.03:59:10.25#ibcon#about to read 3, iclass 4, count 0 2006.257.03:59:10.29#ibcon#read 3, iclass 4, count 0 2006.257.03:59:10.29#ibcon#about to read 4, iclass 4, count 0 2006.257.03:59:10.29#ibcon#read 4, iclass 4, count 0 2006.257.03:59:10.29#ibcon#about to read 5, iclass 4, count 0 2006.257.03:59:10.29#ibcon#read 5, iclass 4, count 0 2006.257.03:59:10.29#ibcon#about to read 6, iclass 4, count 0 2006.257.03:59:10.29#ibcon#read 6, iclass 4, count 0 2006.257.03:59:10.29#ibcon#end of sib2, iclass 4, count 0 2006.257.03:59:10.29#ibcon#*after write, iclass 4, count 0 2006.257.03:59:10.29#ibcon#*before return 0, iclass 4, count 0 2006.257.03:59:10.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:59:10.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.03:59:10.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.03:59:10.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.03:59:10.29$vck44/va=4,7 2006.257.03:59:10.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.03:59:10.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.03:59:10.29#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:10.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:10.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:10.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:10.35#ibcon#enter wrdev, iclass 6, count 2 2006.257.03:59:10.35#ibcon#first serial, iclass 6, count 2 2006.257.03:59:10.35#ibcon#enter sib2, iclass 6, count 2 2006.257.03:59:10.35#ibcon#flushed, iclass 6, count 2 2006.257.03:59:10.35#ibcon#about to write, iclass 6, count 2 2006.257.03:59:10.35#ibcon#wrote, iclass 6, count 2 2006.257.03:59:10.35#ibcon#about to read 3, iclass 6, count 2 2006.257.03:59:10.37#ibcon#read 3, iclass 6, count 2 2006.257.03:59:10.37#ibcon#about to read 4, iclass 6, count 2 2006.257.03:59:10.37#ibcon#read 4, iclass 6, count 2 2006.257.03:59:10.37#ibcon#about to read 5, iclass 6, count 2 2006.257.03:59:10.37#ibcon#read 5, iclass 6, count 2 2006.257.03:59:10.37#ibcon#about to read 6, iclass 6, count 2 2006.257.03:59:10.37#ibcon#read 6, iclass 6, count 2 2006.257.03:59:10.37#ibcon#end of sib2, iclass 6, count 2 2006.257.03:59:10.37#ibcon#*mode == 0, iclass 6, count 2 2006.257.03:59:10.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.03:59:10.37#ibcon#[25=AT04-07\r\n] 2006.257.03:59:10.37#ibcon#*before write, iclass 6, count 2 2006.257.03:59:10.37#ibcon#enter sib2, iclass 6, count 2 2006.257.03:59:10.37#ibcon#flushed, iclass 6, count 2 2006.257.03:59:10.37#ibcon#about to write, iclass 6, count 2 2006.257.03:59:10.37#ibcon#wrote, iclass 6, count 2 2006.257.03:59:10.37#ibcon#about to read 3, iclass 6, count 2 2006.257.03:59:10.40#ibcon#read 3, iclass 6, count 2 2006.257.03:59:10.40#ibcon#about to read 4, iclass 6, count 2 2006.257.03:59:10.40#ibcon#read 4, iclass 6, count 2 2006.257.03:59:10.40#ibcon#about to read 5, iclass 6, count 2 2006.257.03:59:10.40#ibcon#read 5, iclass 6, count 2 2006.257.03:59:10.40#ibcon#about to read 6, iclass 6, count 2 2006.257.03:59:10.40#ibcon#read 6, iclass 6, count 2 2006.257.03:59:10.40#ibcon#end of sib2, iclass 6, count 2 2006.257.03:59:10.40#ibcon#*after write, iclass 6, count 2 2006.257.03:59:10.40#ibcon#*before return 0, iclass 6, count 2 2006.257.03:59:10.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:10.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:10.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.03:59:10.40#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:10.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:10.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:10.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:10.52#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:59:10.52#ibcon#first serial, iclass 6, count 0 2006.257.03:59:10.52#ibcon#enter sib2, iclass 6, count 0 2006.257.03:59:10.52#ibcon#flushed, iclass 6, count 0 2006.257.03:59:10.52#ibcon#about to write, iclass 6, count 0 2006.257.03:59:10.52#ibcon#wrote, iclass 6, count 0 2006.257.03:59:10.52#ibcon#about to read 3, iclass 6, count 0 2006.257.03:59:10.54#ibcon#read 3, iclass 6, count 0 2006.257.03:59:10.54#ibcon#about to read 4, iclass 6, count 0 2006.257.03:59:10.54#ibcon#read 4, iclass 6, count 0 2006.257.03:59:10.54#ibcon#about to read 5, iclass 6, count 0 2006.257.03:59:10.54#ibcon#read 5, iclass 6, count 0 2006.257.03:59:10.54#ibcon#about to read 6, iclass 6, count 0 2006.257.03:59:10.54#ibcon#read 6, iclass 6, count 0 2006.257.03:59:10.54#ibcon#end of sib2, iclass 6, count 0 2006.257.03:59:10.54#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:59:10.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:59:10.54#ibcon#[25=USB\r\n] 2006.257.03:59:10.54#ibcon#*before write, iclass 6, count 0 2006.257.03:59:10.54#ibcon#enter sib2, iclass 6, count 0 2006.257.03:59:10.54#ibcon#flushed, iclass 6, count 0 2006.257.03:59:10.54#ibcon#about to write, iclass 6, count 0 2006.257.03:59:10.54#ibcon#wrote, iclass 6, count 0 2006.257.03:59:10.54#ibcon#about to read 3, iclass 6, count 0 2006.257.03:59:10.57#ibcon#read 3, iclass 6, count 0 2006.257.03:59:10.57#ibcon#about to read 4, iclass 6, count 0 2006.257.03:59:10.57#ibcon#read 4, iclass 6, count 0 2006.257.03:59:10.57#ibcon#about to read 5, iclass 6, count 0 2006.257.03:59:10.57#ibcon#read 5, iclass 6, count 0 2006.257.03:59:10.57#ibcon#about to read 6, iclass 6, count 0 2006.257.03:59:10.57#ibcon#read 6, iclass 6, count 0 2006.257.03:59:10.57#ibcon#end of sib2, iclass 6, count 0 2006.257.03:59:10.57#ibcon#*after write, iclass 6, count 0 2006.257.03:59:10.57#ibcon#*before return 0, iclass 6, count 0 2006.257.03:59:10.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:10.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:10.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:59:10.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:59:10.57$vck44/valo=5,734.99 2006.257.03:59:10.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.03:59:10.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.03:59:10.57#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:10.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:10.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:10.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:10.57#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:59:10.57#ibcon#first serial, iclass 10, count 0 2006.257.03:59:10.57#ibcon#enter sib2, iclass 10, count 0 2006.257.03:59:10.57#ibcon#flushed, iclass 10, count 0 2006.257.03:59:10.57#ibcon#about to write, iclass 10, count 0 2006.257.03:59:10.57#ibcon#wrote, iclass 10, count 0 2006.257.03:59:10.57#ibcon#about to read 3, iclass 10, count 0 2006.257.03:59:10.59#ibcon#read 3, iclass 10, count 0 2006.257.03:59:10.59#ibcon#about to read 4, iclass 10, count 0 2006.257.03:59:10.59#ibcon#read 4, iclass 10, count 0 2006.257.03:59:10.59#ibcon#about to read 5, iclass 10, count 0 2006.257.03:59:10.59#ibcon#read 5, iclass 10, count 0 2006.257.03:59:10.59#ibcon#about to read 6, iclass 10, count 0 2006.257.03:59:10.59#ibcon#read 6, iclass 10, count 0 2006.257.03:59:10.59#ibcon#end of sib2, iclass 10, count 0 2006.257.03:59:10.59#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:59:10.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:59:10.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.03:59:10.59#ibcon#*before write, iclass 10, count 0 2006.257.03:59:10.59#ibcon#enter sib2, iclass 10, count 0 2006.257.03:59:10.59#ibcon#flushed, iclass 10, count 0 2006.257.03:59:10.59#ibcon#about to write, iclass 10, count 0 2006.257.03:59:10.59#ibcon#wrote, iclass 10, count 0 2006.257.03:59:10.59#ibcon#about to read 3, iclass 10, count 0 2006.257.03:59:10.63#ibcon#read 3, iclass 10, count 0 2006.257.03:59:10.63#ibcon#about to read 4, iclass 10, count 0 2006.257.03:59:10.63#ibcon#read 4, iclass 10, count 0 2006.257.03:59:10.63#ibcon#about to read 5, iclass 10, count 0 2006.257.03:59:10.63#ibcon#read 5, iclass 10, count 0 2006.257.03:59:10.63#ibcon#about to read 6, iclass 10, count 0 2006.257.03:59:10.63#ibcon#read 6, iclass 10, count 0 2006.257.03:59:10.63#ibcon#end of sib2, iclass 10, count 0 2006.257.03:59:10.63#ibcon#*after write, iclass 10, count 0 2006.257.03:59:10.63#ibcon#*before return 0, iclass 10, count 0 2006.257.03:59:10.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:10.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:10.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:59:10.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:59:10.63$vck44/va=5,4 2006.257.03:59:10.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.03:59:10.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.03:59:10.63#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:10.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:10.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:10.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:10.69#ibcon#enter wrdev, iclass 12, count 2 2006.257.03:59:10.69#ibcon#first serial, iclass 12, count 2 2006.257.03:59:10.69#ibcon#enter sib2, iclass 12, count 2 2006.257.03:59:10.69#ibcon#flushed, iclass 12, count 2 2006.257.03:59:10.69#ibcon#about to write, iclass 12, count 2 2006.257.03:59:10.69#ibcon#wrote, iclass 12, count 2 2006.257.03:59:10.69#ibcon#about to read 3, iclass 12, count 2 2006.257.03:59:10.71#ibcon#read 3, iclass 12, count 2 2006.257.03:59:10.71#ibcon#about to read 4, iclass 12, count 2 2006.257.03:59:10.71#ibcon#read 4, iclass 12, count 2 2006.257.03:59:10.71#ibcon#about to read 5, iclass 12, count 2 2006.257.03:59:10.71#ibcon#read 5, iclass 12, count 2 2006.257.03:59:10.71#ibcon#about to read 6, iclass 12, count 2 2006.257.03:59:10.71#ibcon#read 6, iclass 12, count 2 2006.257.03:59:10.71#ibcon#end of sib2, iclass 12, count 2 2006.257.03:59:10.71#ibcon#*mode == 0, iclass 12, count 2 2006.257.03:59:10.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.03:59:10.71#ibcon#[25=AT05-04\r\n] 2006.257.03:59:10.71#ibcon#*before write, iclass 12, count 2 2006.257.03:59:10.71#ibcon#enter sib2, iclass 12, count 2 2006.257.03:59:10.71#ibcon#flushed, iclass 12, count 2 2006.257.03:59:10.71#ibcon#about to write, iclass 12, count 2 2006.257.03:59:10.71#ibcon#wrote, iclass 12, count 2 2006.257.03:59:10.71#ibcon#about to read 3, iclass 12, count 2 2006.257.03:59:10.74#ibcon#read 3, iclass 12, count 2 2006.257.03:59:10.74#ibcon#about to read 4, iclass 12, count 2 2006.257.03:59:10.74#ibcon#read 4, iclass 12, count 2 2006.257.03:59:10.74#ibcon#about to read 5, iclass 12, count 2 2006.257.03:59:10.74#ibcon#read 5, iclass 12, count 2 2006.257.03:59:10.74#ibcon#about to read 6, iclass 12, count 2 2006.257.03:59:10.74#ibcon#read 6, iclass 12, count 2 2006.257.03:59:10.74#ibcon#end of sib2, iclass 12, count 2 2006.257.03:59:10.74#ibcon#*after write, iclass 12, count 2 2006.257.03:59:10.74#ibcon#*before return 0, iclass 12, count 2 2006.257.03:59:10.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:10.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:10.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.03:59:10.74#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:10.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:10.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:10.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:10.86#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:59:10.86#ibcon#first serial, iclass 12, count 0 2006.257.03:59:10.86#ibcon#enter sib2, iclass 12, count 0 2006.257.03:59:10.86#ibcon#flushed, iclass 12, count 0 2006.257.03:59:10.86#ibcon#about to write, iclass 12, count 0 2006.257.03:59:10.86#ibcon#wrote, iclass 12, count 0 2006.257.03:59:10.86#ibcon#about to read 3, iclass 12, count 0 2006.257.03:59:10.88#ibcon#read 3, iclass 12, count 0 2006.257.03:59:10.88#ibcon#about to read 4, iclass 12, count 0 2006.257.03:59:10.88#ibcon#read 4, iclass 12, count 0 2006.257.03:59:10.88#ibcon#about to read 5, iclass 12, count 0 2006.257.03:59:10.88#ibcon#read 5, iclass 12, count 0 2006.257.03:59:10.88#ibcon#about to read 6, iclass 12, count 0 2006.257.03:59:10.88#ibcon#read 6, iclass 12, count 0 2006.257.03:59:10.88#ibcon#end of sib2, iclass 12, count 0 2006.257.03:59:10.88#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:59:10.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:59:10.88#ibcon#[25=USB\r\n] 2006.257.03:59:10.88#ibcon#*before write, iclass 12, count 0 2006.257.03:59:10.88#ibcon#enter sib2, iclass 12, count 0 2006.257.03:59:10.88#ibcon#flushed, iclass 12, count 0 2006.257.03:59:10.88#ibcon#about to write, iclass 12, count 0 2006.257.03:59:10.88#ibcon#wrote, iclass 12, count 0 2006.257.03:59:10.88#ibcon#about to read 3, iclass 12, count 0 2006.257.03:59:10.91#ibcon#read 3, iclass 12, count 0 2006.257.03:59:10.91#ibcon#about to read 4, iclass 12, count 0 2006.257.03:59:10.91#ibcon#read 4, iclass 12, count 0 2006.257.03:59:10.91#ibcon#about to read 5, iclass 12, count 0 2006.257.03:59:10.91#ibcon#read 5, iclass 12, count 0 2006.257.03:59:10.91#ibcon#about to read 6, iclass 12, count 0 2006.257.03:59:10.91#ibcon#read 6, iclass 12, count 0 2006.257.03:59:10.91#ibcon#end of sib2, iclass 12, count 0 2006.257.03:59:10.91#ibcon#*after write, iclass 12, count 0 2006.257.03:59:10.91#ibcon#*before return 0, iclass 12, count 0 2006.257.03:59:10.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:10.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:10.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:59:10.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:59:10.91$vck44/valo=6,814.99 2006.257.03:59:10.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.03:59:10.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.03:59:10.91#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:10.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:10.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:10.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:10.91#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:59:10.91#ibcon#first serial, iclass 14, count 0 2006.257.03:59:10.91#ibcon#enter sib2, iclass 14, count 0 2006.257.03:59:10.91#ibcon#flushed, iclass 14, count 0 2006.257.03:59:10.91#ibcon#about to write, iclass 14, count 0 2006.257.03:59:10.91#ibcon#wrote, iclass 14, count 0 2006.257.03:59:10.91#ibcon#about to read 3, iclass 14, count 0 2006.257.03:59:10.93#ibcon#read 3, iclass 14, count 0 2006.257.03:59:10.93#ibcon#about to read 4, iclass 14, count 0 2006.257.03:59:10.93#ibcon#read 4, iclass 14, count 0 2006.257.03:59:10.93#ibcon#about to read 5, iclass 14, count 0 2006.257.03:59:10.93#ibcon#read 5, iclass 14, count 0 2006.257.03:59:10.93#ibcon#about to read 6, iclass 14, count 0 2006.257.03:59:10.93#ibcon#read 6, iclass 14, count 0 2006.257.03:59:10.93#ibcon#end of sib2, iclass 14, count 0 2006.257.03:59:10.93#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:59:10.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:59:10.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.03:59:10.93#ibcon#*before write, iclass 14, count 0 2006.257.03:59:10.93#ibcon#enter sib2, iclass 14, count 0 2006.257.03:59:10.93#ibcon#flushed, iclass 14, count 0 2006.257.03:59:10.93#ibcon#about to write, iclass 14, count 0 2006.257.03:59:10.93#ibcon#wrote, iclass 14, count 0 2006.257.03:59:10.93#ibcon#about to read 3, iclass 14, count 0 2006.257.03:59:10.97#ibcon#read 3, iclass 14, count 0 2006.257.03:59:10.97#ibcon#about to read 4, iclass 14, count 0 2006.257.03:59:10.97#ibcon#read 4, iclass 14, count 0 2006.257.03:59:10.97#ibcon#about to read 5, iclass 14, count 0 2006.257.03:59:10.97#ibcon#read 5, iclass 14, count 0 2006.257.03:59:10.97#ibcon#about to read 6, iclass 14, count 0 2006.257.03:59:10.97#ibcon#read 6, iclass 14, count 0 2006.257.03:59:10.97#ibcon#end of sib2, iclass 14, count 0 2006.257.03:59:10.97#ibcon#*after write, iclass 14, count 0 2006.257.03:59:10.97#ibcon#*before return 0, iclass 14, count 0 2006.257.03:59:10.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:10.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:10.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:59:10.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:59:10.97$vck44/va=6,4 2006.257.03:59:10.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.03:59:10.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.03:59:10.97#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:10.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:11.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:11.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:11.03#ibcon#enter wrdev, iclass 16, count 2 2006.257.03:59:11.03#ibcon#first serial, iclass 16, count 2 2006.257.03:59:11.03#ibcon#enter sib2, iclass 16, count 2 2006.257.03:59:11.03#ibcon#flushed, iclass 16, count 2 2006.257.03:59:11.03#ibcon#about to write, iclass 16, count 2 2006.257.03:59:11.03#ibcon#wrote, iclass 16, count 2 2006.257.03:59:11.03#ibcon#about to read 3, iclass 16, count 2 2006.257.03:59:11.05#ibcon#read 3, iclass 16, count 2 2006.257.03:59:11.05#ibcon#about to read 4, iclass 16, count 2 2006.257.03:59:11.05#ibcon#read 4, iclass 16, count 2 2006.257.03:59:11.05#ibcon#about to read 5, iclass 16, count 2 2006.257.03:59:11.05#ibcon#read 5, iclass 16, count 2 2006.257.03:59:11.05#ibcon#about to read 6, iclass 16, count 2 2006.257.03:59:11.05#ibcon#read 6, iclass 16, count 2 2006.257.03:59:11.05#ibcon#end of sib2, iclass 16, count 2 2006.257.03:59:11.05#ibcon#*mode == 0, iclass 16, count 2 2006.257.03:59:11.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.03:59:11.05#ibcon#[25=AT06-04\r\n] 2006.257.03:59:11.05#ibcon#*before write, iclass 16, count 2 2006.257.03:59:11.05#ibcon#enter sib2, iclass 16, count 2 2006.257.03:59:11.05#ibcon#flushed, iclass 16, count 2 2006.257.03:59:11.05#ibcon#about to write, iclass 16, count 2 2006.257.03:59:11.05#ibcon#wrote, iclass 16, count 2 2006.257.03:59:11.05#ibcon#about to read 3, iclass 16, count 2 2006.257.03:59:11.08#ibcon#read 3, iclass 16, count 2 2006.257.03:59:11.08#ibcon#about to read 4, iclass 16, count 2 2006.257.03:59:11.08#ibcon#read 4, iclass 16, count 2 2006.257.03:59:11.08#ibcon#about to read 5, iclass 16, count 2 2006.257.03:59:11.08#ibcon#read 5, iclass 16, count 2 2006.257.03:59:11.08#ibcon#about to read 6, iclass 16, count 2 2006.257.03:59:11.08#ibcon#read 6, iclass 16, count 2 2006.257.03:59:11.08#ibcon#end of sib2, iclass 16, count 2 2006.257.03:59:11.08#ibcon#*after write, iclass 16, count 2 2006.257.03:59:11.08#ibcon#*before return 0, iclass 16, count 2 2006.257.03:59:11.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:11.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:11.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.03:59:11.08#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:11.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:11.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:11.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:11.20#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:59:11.20#ibcon#first serial, iclass 16, count 0 2006.257.03:59:11.20#ibcon#enter sib2, iclass 16, count 0 2006.257.03:59:11.20#ibcon#flushed, iclass 16, count 0 2006.257.03:59:11.20#ibcon#about to write, iclass 16, count 0 2006.257.03:59:11.20#ibcon#wrote, iclass 16, count 0 2006.257.03:59:11.20#ibcon#about to read 3, iclass 16, count 0 2006.257.03:59:11.22#ibcon#read 3, iclass 16, count 0 2006.257.03:59:11.22#ibcon#about to read 4, iclass 16, count 0 2006.257.03:59:11.22#ibcon#read 4, iclass 16, count 0 2006.257.03:59:11.22#ibcon#about to read 5, iclass 16, count 0 2006.257.03:59:11.22#ibcon#read 5, iclass 16, count 0 2006.257.03:59:11.22#ibcon#about to read 6, iclass 16, count 0 2006.257.03:59:11.22#ibcon#read 6, iclass 16, count 0 2006.257.03:59:11.22#ibcon#end of sib2, iclass 16, count 0 2006.257.03:59:11.22#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:59:11.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:59:11.22#ibcon#[25=USB\r\n] 2006.257.03:59:11.22#ibcon#*before write, iclass 16, count 0 2006.257.03:59:11.22#ibcon#enter sib2, iclass 16, count 0 2006.257.03:59:11.22#ibcon#flushed, iclass 16, count 0 2006.257.03:59:11.22#ibcon#about to write, iclass 16, count 0 2006.257.03:59:11.22#ibcon#wrote, iclass 16, count 0 2006.257.03:59:11.22#ibcon#about to read 3, iclass 16, count 0 2006.257.03:59:11.25#ibcon#read 3, iclass 16, count 0 2006.257.03:59:11.25#ibcon#about to read 4, iclass 16, count 0 2006.257.03:59:11.25#ibcon#read 4, iclass 16, count 0 2006.257.03:59:11.25#ibcon#about to read 5, iclass 16, count 0 2006.257.03:59:11.25#ibcon#read 5, iclass 16, count 0 2006.257.03:59:11.25#ibcon#about to read 6, iclass 16, count 0 2006.257.03:59:11.25#ibcon#read 6, iclass 16, count 0 2006.257.03:59:11.25#ibcon#end of sib2, iclass 16, count 0 2006.257.03:59:11.25#ibcon#*after write, iclass 16, count 0 2006.257.03:59:11.25#ibcon#*before return 0, iclass 16, count 0 2006.257.03:59:11.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:11.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:11.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:59:11.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:59:11.25$vck44/valo=7,864.99 2006.257.03:59:11.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.03:59:11.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.03:59:11.25#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:11.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:11.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:11.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:11.25#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:59:11.25#ibcon#first serial, iclass 18, count 0 2006.257.03:59:11.25#ibcon#enter sib2, iclass 18, count 0 2006.257.03:59:11.25#ibcon#flushed, iclass 18, count 0 2006.257.03:59:11.25#ibcon#about to write, iclass 18, count 0 2006.257.03:59:11.25#ibcon#wrote, iclass 18, count 0 2006.257.03:59:11.25#ibcon#about to read 3, iclass 18, count 0 2006.257.03:59:11.27#ibcon#read 3, iclass 18, count 0 2006.257.03:59:11.27#ibcon#about to read 4, iclass 18, count 0 2006.257.03:59:11.27#ibcon#read 4, iclass 18, count 0 2006.257.03:59:11.27#ibcon#about to read 5, iclass 18, count 0 2006.257.03:59:11.27#ibcon#read 5, iclass 18, count 0 2006.257.03:59:11.27#ibcon#about to read 6, iclass 18, count 0 2006.257.03:59:11.27#ibcon#read 6, iclass 18, count 0 2006.257.03:59:11.27#ibcon#end of sib2, iclass 18, count 0 2006.257.03:59:11.27#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:59:11.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:59:11.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.03:59:11.27#ibcon#*before write, iclass 18, count 0 2006.257.03:59:11.27#ibcon#enter sib2, iclass 18, count 0 2006.257.03:59:11.27#ibcon#flushed, iclass 18, count 0 2006.257.03:59:11.27#ibcon#about to write, iclass 18, count 0 2006.257.03:59:11.27#ibcon#wrote, iclass 18, count 0 2006.257.03:59:11.27#ibcon#about to read 3, iclass 18, count 0 2006.257.03:59:11.31#ibcon#read 3, iclass 18, count 0 2006.257.03:59:11.31#ibcon#about to read 4, iclass 18, count 0 2006.257.03:59:11.31#ibcon#read 4, iclass 18, count 0 2006.257.03:59:11.31#ibcon#about to read 5, iclass 18, count 0 2006.257.03:59:11.31#ibcon#read 5, iclass 18, count 0 2006.257.03:59:11.31#ibcon#about to read 6, iclass 18, count 0 2006.257.03:59:11.31#ibcon#read 6, iclass 18, count 0 2006.257.03:59:11.31#ibcon#end of sib2, iclass 18, count 0 2006.257.03:59:11.31#ibcon#*after write, iclass 18, count 0 2006.257.03:59:11.31#ibcon#*before return 0, iclass 18, count 0 2006.257.03:59:11.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:11.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:11.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:59:11.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:59:11.31$vck44/va=7,4 2006.257.03:59:11.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.03:59:11.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.03:59:11.31#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:11.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:11.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:11.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:11.37#ibcon#enter wrdev, iclass 20, count 2 2006.257.03:59:11.37#ibcon#first serial, iclass 20, count 2 2006.257.03:59:11.37#ibcon#enter sib2, iclass 20, count 2 2006.257.03:59:11.37#ibcon#flushed, iclass 20, count 2 2006.257.03:59:11.37#ibcon#about to write, iclass 20, count 2 2006.257.03:59:11.37#ibcon#wrote, iclass 20, count 2 2006.257.03:59:11.37#ibcon#about to read 3, iclass 20, count 2 2006.257.03:59:11.39#ibcon#read 3, iclass 20, count 2 2006.257.03:59:11.39#ibcon#about to read 4, iclass 20, count 2 2006.257.03:59:11.39#ibcon#read 4, iclass 20, count 2 2006.257.03:59:11.39#ibcon#about to read 5, iclass 20, count 2 2006.257.03:59:11.39#ibcon#read 5, iclass 20, count 2 2006.257.03:59:11.39#ibcon#about to read 6, iclass 20, count 2 2006.257.03:59:11.39#ibcon#read 6, iclass 20, count 2 2006.257.03:59:11.39#ibcon#end of sib2, iclass 20, count 2 2006.257.03:59:11.39#ibcon#*mode == 0, iclass 20, count 2 2006.257.03:59:11.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.03:59:11.39#ibcon#[25=AT07-04\r\n] 2006.257.03:59:11.39#ibcon#*before write, iclass 20, count 2 2006.257.03:59:11.39#ibcon#enter sib2, iclass 20, count 2 2006.257.03:59:11.39#ibcon#flushed, iclass 20, count 2 2006.257.03:59:11.39#ibcon#about to write, iclass 20, count 2 2006.257.03:59:11.39#ibcon#wrote, iclass 20, count 2 2006.257.03:59:11.39#ibcon#about to read 3, iclass 20, count 2 2006.257.03:59:11.42#ibcon#read 3, iclass 20, count 2 2006.257.03:59:11.42#ibcon#about to read 4, iclass 20, count 2 2006.257.03:59:11.42#ibcon#read 4, iclass 20, count 2 2006.257.03:59:11.42#ibcon#about to read 5, iclass 20, count 2 2006.257.03:59:11.42#ibcon#read 5, iclass 20, count 2 2006.257.03:59:11.42#ibcon#about to read 6, iclass 20, count 2 2006.257.03:59:11.42#ibcon#read 6, iclass 20, count 2 2006.257.03:59:11.42#ibcon#end of sib2, iclass 20, count 2 2006.257.03:59:11.42#ibcon#*after write, iclass 20, count 2 2006.257.03:59:11.42#ibcon#*before return 0, iclass 20, count 2 2006.257.03:59:11.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:11.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:11.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.03:59:11.42#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:11.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:11.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:11.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:11.54#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:59:11.54#ibcon#first serial, iclass 20, count 0 2006.257.03:59:11.54#ibcon#enter sib2, iclass 20, count 0 2006.257.03:59:11.54#ibcon#flushed, iclass 20, count 0 2006.257.03:59:11.54#ibcon#about to write, iclass 20, count 0 2006.257.03:59:11.54#ibcon#wrote, iclass 20, count 0 2006.257.03:59:11.54#ibcon#about to read 3, iclass 20, count 0 2006.257.03:59:11.56#ibcon#read 3, iclass 20, count 0 2006.257.03:59:11.56#ibcon#about to read 4, iclass 20, count 0 2006.257.03:59:11.56#ibcon#read 4, iclass 20, count 0 2006.257.03:59:11.56#ibcon#about to read 5, iclass 20, count 0 2006.257.03:59:11.56#ibcon#read 5, iclass 20, count 0 2006.257.03:59:11.56#ibcon#about to read 6, iclass 20, count 0 2006.257.03:59:11.56#ibcon#read 6, iclass 20, count 0 2006.257.03:59:11.56#ibcon#end of sib2, iclass 20, count 0 2006.257.03:59:11.56#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:59:11.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:59:11.56#ibcon#[25=USB\r\n] 2006.257.03:59:11.56#ibcon#*before write, iclass 20, count 0 2006.257.03:59:11.56#ibcon#enter sib2, iclass 20, count 0 2006.257.03:59:11.56#ibcon#flushed, iclass 20, count 0 2006.257.03:59:11.56#ibcon#about to write, iclass 20, count 0 2006.257.03:59:11.56#ibcon#wrote, iclass 20, count 0 2006.257.03:59:11.56#ibcon#about to read 3, iclass 20, count 0 2006.257.03:59:11.59#ibcon#read 3, iclass 20, count 0 2006.257.03:59:11.59#ibcon#about to read 4, iclass 20, count 0 2006.257.03:59:11.59#ibcon#read 4, iclass 20, count 0 2006.257.03:59:11.59#ibcon#about to read 5, iclass 20, count 0 2006.257.03:59:11.59#ibcon#read 5, iclass 20, count 0 2006.257.03:59:11.59#ibcon#about to read 6, iclass 20, count 0 2006.257.03:59:11.59#ibcon#read 6, iclass 20, count 0 2006.257.03:59:11.59#ibcon#end of sib2, iclass 20, count 0 2006.257.03:59:11.59#ibcon#*after write, iclass 20, count 0 2006.257.03:59:11.59#ibcon#*before return 0, iclass 20, count 0 2006.257.03:59:11.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:11.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:11.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:59:11.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:59:11.59$vck44/valo=8,884.99 2006.257.03:59:11.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.03:59:11.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.03:59:11.59#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:11.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:11.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:11.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:11.59#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:59:11.59#ibcon#first serial, iclass 22, count 0 2006.257.03:59:11.59#ibcon#enter sib2, iclass 22, count 0 2006.257.03:59:11.59#ibcon#flushed, iclass 22, count 0 2006.257.03:59:11.59#ibcon#about to write, iclass 22, count 0 2006.257.03:59:11.59#ibcon#wrote, iclass 22, count 0 2006.257.03:59:11.59#ibcon#about to read 3, iclass 22, count 0 2006.257.03:59:11.61#ibcon#read 3, iclass 22, count 0 2006.257.03:59:11.61#ibcon#about to read 4, iclass 22, count 0 2006.257.03:59:11.61#ibcon#read 4, iclass 22, count 0 2006.257.03:59:11.61#ibcon#about to read 5, iclass 22, count 0 2006.257.03:59:11.61#ibcon#read 5, iclass 22, count 0 2006.257.03:59:11.61#ibcon#about to read 6, iclass 22, count 0 2006.257.03:59:11.61#ibcon#read 6, iclass 22, count 0 2006.257.03:59:11.61#ibcon#end of sib2, iclass 22, count 0 2006.257.03:59:11.61#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:59:11.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:59:11.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.03:59:11.61#ibcon#*before write, iclass 22, count 0 2006.257.03:59:11.61#ibcon#enter sib2, iclass 22, count 0 2006.257.03:59:11.61#ibcon#flushed, iclass 22, count 0 2006.257.03:59:11.61#ibcon#about to write, iclass 22, count 0 2006.257.03:59:11.61#ibcon#wrote, iclass 22, count 0 2006.257.03:59:11.61#ibcon#about to read 3, iclass 22, count 0 2006.257.03:59:11.65#ibcon#read 3, iclass 22, count 0 2006.257.03:59:11.65#ibcon#about to read 4, iclass 22, count 0 2006.257.03:59:11.65#ibcon#read 4, iclass 22, count 0 2006.257.03:59:11.65#ibcon#about to read 5, iclass 22, count 0 2006.257.03:59:11.65#ibcon#read 5, iclass 22, count 0 2006.257.03:59:11.65#ibcon#about to read 6, iclass 22, count 0 2006.257.03:59:11.65#ibcon#read 6, iclass 22, count 0 2006.257.03:59:11.65#ibcon#end of sib2, iclass 22, count 0 2006.257.03:59:11.65#ibcon#*after write, iclass 22, count 0 2006.257.03:59:11.65#ibcon#*before return 0, iclass 22, count 0 2006.257.03:59:11.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:11.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:11.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:59:11.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:59:11.65$vck44/va=8,4 2006.257.03:59:11.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.03:59:11.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.03:59:11.65#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:11.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:11.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:11.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:11.71#ibcon#enter wrdev, iclass 24, count 2 2006.257.03:59:11.71#ibcon#first serial, iclass 24, count 2 2006.257.03:59:11.71#ibcon#enter sib2, iclass 24, count 2 2006.257.03:59:11.71#ibcon#flushed, iclass 24, count 2 2006.257.03:59:11.71#ibcon#about to write, iclass 24, count 2 2006.257.03:59:11.71#ibcon#wrote, iclass 24, count 2 2006.257.03:59:11.71#ibcon#about to read 3, iclass 24, count 2 2006.257.03:59:11.73#ibcon#read 3, iclass 24, count 2 2006.257.03:59:11.73#ibcon#about to read 4, iclass 24, count 2 2006.257.03:59:11.73#ibcon#read 4, iclass 24, count 2 2006.257.03:59:11.73#ibcon#about to read 5, iclass 24, count 2 2006.257.03:59:11.73#ibcon#read 5, iclass 24, count 2 2006.257.03:59:11.73#ibcon#about to read 6, iclass 24, count 2 2006.257.03:59:11.73#ibcon#read 6, iclass 24, count 2 2006.257.03:59:11.73#ibcon#end of sib2, iclass 24, count 2 2006.257.03:59:11.73#ibcon#*mode == 0, iclass 24, count 2 2006.257.03:59:11.73#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.03:59:11.73#ibcon#[25=AT08-04\r\n] 2006.257.03:59:11.73#ibcon#*before write, iclass 24, count 2 2006.257.03:59:11.73#ibcon#enter sib2, iclass 24, count 2 2006.257.03:59:11.73#ibcon#flushed, iclass 24, count 2 2006.257.03:59:11.73#ibcon#about to write, iclass 24, count 2 2006.257.03:59:11.73#ibcon#wrote, iclass 24, count 2 2006.257.03:59:11.73#ibcon#about to read 3, iclass 24, count 2 2006.257.03:59:11.76#ibcon#read 3, iclass 24, count 2 2006.257.03:59:11.76#ibcon#about to read 4, iclass 24, count 2 2006.257.03:59:11.76#ibcon#read 4, iclass 24, count 2 2006.257.03:59:11.76#ibcon#about to read 5, iclass 24, count 2 2006.257.03:59:11.76#ibcon#read 5, iclass 24, count 2 2006.257.03:59:11.76#ibcon#about to read 6, iclass 24, count 2 2006.257.03:59:11.76#ibcon#read 6, iclass 24, count 2 2006.257.03:59:11.76#ibcon#end of sib2, iclass 24, count 2 2006.257.03:59:11.76#ibcon#*after write, iclass 24, count 2 2006.257.03:59:11.76#ibcon#*before return 0, iclass 24, count 2 2006.257.03:59:11.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:11.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:11.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.03:59:11.76#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:11.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:11.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:11.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:11.88#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:59:11.88#ibcon#first serial, iclass 24, count 0 2006.257.03:59:11.88#ibcon#enter sib2, iclass 24, count 0 2006.257.03:59:11.88#ibcon#flushed, iclass 24, count 0 2006.257.03:59:11.88#ibcon#about to write, iclass 24, count 0 2006.257.03:59:11.88#ibcon#wrote, iclass 24, count 0 2006.257.03:59:11.88#ibcon#about to read 3, iclass 24, count 0 2006.257.03:59:11.90#ibcon#read 3, iclass 24, count 0 2006.257.03:59:11.90#ibcon#about to read 4, iclass 24, count 0 2006.257.03:59:11.90#ibcon#read 4, iclass 24, count 0 2006.257.03:59:11.90#ibcon#about to read 5, iclass 24, count 0 2006.257.03:59:11.90#ibcon#read 5, iclass 24, count 0 2006.257.03:59:11.90#ibcon#about to read 6, iclass 24, count 0 2006.257.03:59:11.90#ibcon#read 6, iclass 24, count 0 2006.257.03:59:11.90#ibcon#end of sib2, iclass 24, count 0 2006.257.03:59:11.90#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:59:11.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:59:11.90#ibcon#[25=USB\r\n] 2006.257.03:59:11.90#ibcon#*before write, iclass 24, count 0 2006.257.03:59:11.90#ibcon#enter sib2, iclass 24, count 0 2006.257.03:59:11.90#ibcon#flushed, iclass 24, count 0 2006.257.03:59:11.90#ibcon#about to write, iclass 24, count 0 2006.257.03:59:11.90#ibcon#wrote, iclass 24, count 0 2006.257.03:59:11.90#ibcon#about to read 3, iclass 24, count 0 2006.257.03:59:11.93#ibcon#read 3, iclass 24, count 0 2006.257.03:59:11.93#ibcon#about to read 4, iclass 24, count 0 2006.257.03:59:11.93#ibcon#read 4, iclass 24, count 0 2006.257.03:59:11.93#ibcon#about to read 5, iclass 24, count 0 2006.257.03:59:11.93#ibcon#read 5, iclass 24, count 0 2006.257.03:59:11.93#ibcon#about to read 6, iclass 24, count 0 2006.257.03:59:11.93#ibcon#read 6, iclass 24, count 0 2006.257.03:59:11.93#ibcon#end of sib2, iclass 24, count 0 2006.257.03:59:11.93#ibcon#*after write, iclass 24, count 0 2006.257.03:59:11.93#ibcon#*before return 0, iclass 24, count 0 2006.257.03:59:11.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:11.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:11.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:59:11.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:59:11.93$vck44/vblo=1,629.99 2006.257.03:59:11.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.03:59:11.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.03:59:11.93#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:11.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:11.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:11.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:11.93#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:59:11.93#ibcon#first serial, iclass 26, count 0 2006.257.03:59:11.93#ibcon#enter sib2, iclass 26, count 0 2006.257.03:59:11.93#ibcon#flushed, iclass 26, count 0 2006.257.03:59:11.93#ibcon#about to write, iclass 26, count 0 2006.257.03:59:11.93#ibcon#wrote, iclass 26, count 0 2006.257.03:59:11.93#ibcon#about to read 3, iclass 26, count 0 2006.257.03:59:11.95#ibcon#read 3, iclass 26, count 0 2006.257.03:59:11.95#ibcon#about to read 4, iclass 26, count 0 2006.257.03:59:11.95#ibcon#read 4, iclass 26, count 0 2006.257.03:59:11.95#ibcon#about to read 5, iclass 26, count 0 2006.257.03:59:11.95#ibcon#read 5, iclass 26, count 0 2006.257.03:59:11.95#ibcon#about to read 6, iclass 26, count 0 2006.257.03:59:11.95#ibcon#read 6, iclass 26, count 0 2006.257.03:59:11.95#ibcon#end of sib2, iclass 26, count 0 2006.257.03:59:11.95#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:59:11.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:59:11.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.03:59:11.95#ibcon#*before write, iclass 26, count 0 2006.257.03:59:11.95#ibcon#enter sib2, iclass 26, count 0 2006.257.03:59:11.95#ibcon#flushed, iclass 26, count 0 2006.257.03:59:11.95#ibcon#about to write, iclass 26, count 0 2006.257.03:59:11.95#ibcon#wrote, iclass 26, count 0 2006.257.03:59:11.95#ibcon#about to read 3, iclass 26, count 0 2006.257.03:59:11.99#ibcon#read 3, iclass 26, count 0 2006.257.03:59:11.99#ibcon#about to read 4, iclass 26, count 0 2006.257.03:59:11.99#ibcon#read 4, iclass 26, count 0 2006.257.03:59:11.99#ibcon#about to read 5, iclass 26, count 0 2006.257.03:59:11.99#ibcon#read 5, iclass 26, count 0 2006.257.03:59:11.99#ibcon#about to read 6, iclass 26, count 0 2006.257.03:59:11.99#ibcon#read 6, iclass 26, count 0 2006.257.03:59:11.99#ibcon#end of sib2, iclass 26, count 0 2006.257.03:59:11.99#ibcon#*after write, iclass 26, count 0 2006.257.03:59:11.99#ibcon#*before return 0, iclass 26, count 0 2006.257.03:59:11.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:11.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:11.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:59:11.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:59:11.99$vck44/vb=1,4 2006.257.03:59:11.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.03:59:11.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.03:59:11.99#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:11.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:59:11.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:59:11.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:59:11.99#ibcon#enter wrdev, iclass 28, count 2 2006.257.03:59:11.99#ibcon#first serial, iclass 28, count 2 2006.257.03:59:11.99#ibcon#enter sib2, iclass 28, count 2 2006.257.03:59:11.99#ibcon#flushed, iclass 28, count 2 2006.257.03:59:11.99#ibcon#about to write, iclass 28, count 2 2006.257.03:59:11.99#ibcon#wrote, iclass 28, count 2 2006.257.03:59:11.99#ibcon#about to read 3, iclass 28, count 2 2006.257.03:59:12.01#ibcon#read 3, iclass 28, count 2 2006.257.03:59:12.01#ibcon#about to read 4, iclass 28, count 2 2006.257.03:59:12.01#ibcon#read 4, iclass 28, count 2 2006.257.03:59:12.01#ibcon#about to read 5, iclass 28, count 2 2006.257.03:59:12.01#ibcon#read 5, iclass 28, count 2 2006.257.03:59:12.01#ibcon#about to read 6, iclass 28, count 2 2006.257.03:59:12.01#ibcon#read 6, iclass 28, count 2 2006.257.03:59:12.01#ibcon#end of sib2, iclass 28, count 2 2006.257.03:59:12.01#ibcon#*mode == 0, iclass 28, count 2 2006.257.03:59:12.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.03:59:12.01#ibcon#[27=AT01-04\r\n] 2006.257.03:59:12.01#ibcon#*before write, iclass 28, count 2 2006.257.03:59:12.01#ibcon#enter sib2, iclass 28, count 2 2006.257.03:59:12.01#ibcon#flushed, iclass 28, count 2 2006.257.03:59:12.01#ibcon#about to write, iclass 28, count 2 2006.257.03:59:12.01#ibcon#wrote, iclass 28, count 2 2006.257.03:59:12.01#ibcon#about to read 3, iclass 28, count 2 2006.257.03:59:12.04#ibcon#read 3, iclass 28, count 2 2006.257.03:59:12.04#ibcon#about to read 4, iclass 28, count 2 2006.257.03:59:12.04#ibcon#read 4, iclass 28, count 2 2006.257.03:59:12.04#ibcon#about to read 5, iclass 28, count 2 2006.257.03:59:12.04#ibcon#read 5, iclass 28, count 2 2006.257.03:59:12.04#ibcon#about to read 6, iclass 28, count 2 2006.257.03:59:12.04#ibcon#read 6, iclass 28, count 2 2006.257.03:59:12.04#ibcon#end of sib2, iclass 28, count 2 2006.257.03:59:12.04#ibcon#*after write, iclass 28, count 2 2006.257.03:59:12.04#ibcon#*before return 0, iclass 28, count 2 2006.257.03:59:12.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:59:12.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.03:59:12.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.03:59:12.04#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:12.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:59:12.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:59:12.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:59:12.16#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:59:12.16#ibcon#first serial, iclass 28, count 0 2006.257.03:59:12.16#ibcon#enter sib2, iclass 28, count 0 2006.257.03:59:12.16#ibcon#flushed, iclass 28, count 0 2006.257.03:59:12.16#ibcon#about to write, iclass 28, count 0 2006.257.03:59:12.16#ibcon#wrote, iclass 28, count 0 2006.257.03:59:12.16#ibcon#about to read 3, iclass 28, count 0 2006.257.03:59:12.18#ibcon#read 3, iclass 28, count 0 2006.257.03:59:12.18#ibcon#about to read 4, iclass 28, count 0 2006.257.03:59:12.18#ibcon#read 4, iclass 28, count 0 2006.257.03:59:12.18#ibcon#about to read 5, iclass 28, count 0 2006.257.03:59:12.18#ibcon#read 5, iclass 28, count 0 2006.257.03:59:12.18#ibcon#about to read 6, iclass 28, count 0 2006.257.03:59:12.18#ibcon#read 6, iclass 28, count 0 2006.257.03:59:12.18#ibcon#end of sib2, iclass 28, count 0 2006.257.03:59:12.18#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:59:12.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:59:12.18#ibcon#[27=USB\r\n] 2006.257.03:59:12.18#ibcon#*before write, iclass 28, count 0 2006.257.03:59:12.18#ibcon#enter sib2, iclass 28, count 0 2006.257.03:59:12.18#ibcon#flushed, iclass 28, count 0 2006.257.03:59:12.18#ibcon#about to write, iclass 28, count 0 2006.257.03:59:12.18#ibcon#wrote, iclass 28, count 0 2006.257.03:59:12.18#ibcon#about to read 3, iclass 28, count 0 2006.257.03:59:12.21#ibcon#read 3, iclass 28, count 0 2006.257.03:59:12.21#ibcon#about to read 4, iclass 28, count 0 2006.257.03:59:12.21#ibcon#read 4, iclass 28, count 0 2006.257.03:59:12.21#ibcon#about to read 5, iclass 28, count 0 2006.257.03:59:12.21#ibcon#read 5, iclass 28, count 0 2006.257.03:59:12.21#ibcon#about to read 6, iclass 28, count 0 2006.257.03:59:12.21#ibcon#read 6, iclass 28, count 0 2006.257.03:59:12.21#ibcon#end of sib2, iclass 28, count 0 2006.257.03:59:12.21#ibcon#*after write, iclass 28, count 0 2006.257.03:59:12.21#ibcon#*before return 0, iclass 28, count 0 2006.257.03:59:12.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:59:12.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.03:59:12.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:59:12.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:59:12.21$vck44/vblo=2,634.99 2006.257.03:59:12.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.03:59:12.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.03:59:12.21#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:12.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:12.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:12.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:12.21#ibcon#enter wrdev, iclass 30, count 0 2006.257.03:59:12.21#ibcon#first serial, iclass 30, count 0 2006.257.03:59:12.21#ibcon#enter sib2, iclass 30, count 0 2006.257.03:59:12.21#ibcon#flushed, iclass 30, count 0 2006.257.03:59:12.21#ibcon#about to write, iclass 30, count 0 2006.257.03:59:12.21#ibcon#wrote, iclass 30, count 0 2006.257.03:59:12.21#ibcon#about to read 3, iclass 30, count 0 2006.257.03:59:12.23#ibcon#read 3, iclass 30, count 0 2006.257.03:59:12.23#ibcon#about to read 4, iclass 30, count 0 2006.257.03:59:12.23#ibcon#read 4, iclass 30, count 0 2006.257.03:59:12.23#ibcon#about to read 5, iclass 30, count 0 2006.257.03:59:12.23#ibcon#read 5, iclass 30, count 0 2006.257.03:59:12.23#ibcon#about to read 6, iclass 30, count 0 2006.257.03:59:12.23#ibcon#read 6, iclass 30, count 0 2006.257.03:59:12.23#ibcon#end of sib2, iclass 30, count 0 2006.257.03:59:12.23#ibcon#*mode == 0, iclass 30, count 0 2006.257.03:59:12.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.03:59:12.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.03:59:12.23#ibcon#*before write, iclass 30, count 0 2006.257.03:59:12.23#ibcon#enter sib2, iclass 30, count 0 2006.257.03:59:12.23#ibcon#flushed, iclass 30, count 0 2006.257.03:59:12.23#ibcon#about to write, iclass 30, count 0 2006.257.03:59:12.23#ibcon#wrote, iclass 30, count 0 2006.257.03:59:12.23#ibcon#about to read 3, iclass 30, count 0 2006.257.03:59:12.27#ibcon#read 3, iclass 30, count 0 2006.257.03:59:12.27#ibcon#about to read 4, iclass 30, count 0 2006.257.03:59:12.27#ibcon#read 4, iclass 30, count 0 2006.257.03:59:12.27#ibcon#about to read 5, iclass 30, count 0 2006.257.03:59:12.27#ibcon#read 5, iclass 30, count 0 2006.257.03:59:12.27#ibcon#about to read 6, iclass 30, count 0 2006.257.03:59:12.27#ibcon#read 6, iclass 30, count 0 2006.257.03:59:12.27#ibcon#end of sib2, iclass 30, count 0 2006.257.03:59:12.27#ibcon#*after write, iclass 30, count 0 2006.257.03:59:12.27#ibcon#*before return 0, iclass 30, count 0 2006.257.03:59:12.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:12.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.03:59:12.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.03:59:12.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.03:59:12.27$vck44/vb=2,5 2006.257.03:59:12.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.03:59:12.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.03:59:12.27#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:12.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:12.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:12.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:12.33#ibcon#enter wrdev, iclass 32, count 2 2006.257.03:59:12.33#ibcon#first serial, iclass 32, count 2 2006.257.03:59:12.33#ibcon#enter sib2, iclass 32, count 2 2006.257.03:59:12.33#ibcon#flushed, iclass 32, count 2 2006.257.03:59:12.33#ibcon#about to write, iclass 32, count 2 2006.257.03:59:12.33#ibcon#wrote, iclass 32, count 2 2006.257.03:59:12.33#ibcon#about to read 3, iclass 32, count 2 2006.257.03:59:12.35#ibcon#read 3, iclass 32, count 2 2006.257.03:59:12.35#ibcon#about to read 4, iclass 32, count 2 2006.257.03:59:12.35#ibcon#read 4, iclass 32, count 2 2006.257.03:59:12.35#ibcon#about to read 5, iclass 32, count 2 2006.257.03:59:12.35#ibcon#read 5, iclass 32, count 2 2006.257.03:59:12.35#ibcon#about to read 6, iclass 32, count 2 2006.257.03:59:12.35#ibcon#read 6, iclass 32, count 2 2006.257.03:59:12.35#ibcon#end of sib2, iclass 32, count 2 2006.257.03:59:12.35#ibcon#*mode == 0, iclass 32, count 2 2006.257.03:59:12.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.03:59:12.35#ibcon#[27=AT02-05\r\n] 2006.257.03:59:12.35#ibcon#*before write, iclass 32, count 2 2006.257.03:59:12.35#ibcon#enter sib2, iclass 32, count 2 2006.257.03:59:12.35#ibcon#flushed, iclass 32, count 2 2006.257.03:59:12.35#ibcon#about to write, iclass 32, count 2 2006.257.03:59:12.35#ibcon#wrote, iclass 32, count 2 2006.257.03:59:12.35#ibcon#about to read 3, iclass 32, count 2 2006.257.03:59:12.38#ibcon#read 3, iclass 32, count 2 2006.257.03:59:12.38#ibcon#about to read 4, iclass 32, count 2 2006.257.03:59:12.38#ibcon#read 4, iclass 32, count 2 2006.257.03:59:12.38#ibcon#about to read 5, iclass 32, count 2 2006.257.03:59:12.38#ibcon#read 5, iclass 32, count 2 2006.257.03:59:12.38#ibcon#about to read 6, iclass 32, count 2 2006.257.03:59:12.38#ibcon#read 6, iclass 32, count 2 2006.257.03:59:12.38#ibcon#end of sib2, iclass 32, count 2 2006.257.03:59:12.38#ibcon#*after write, iclass 32, count 2 2006.257.03:59:12.38#ibcon#*before return 0, iclass 32, count 2 2006.257.03:59:12.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:12.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.03:59:12.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.03:59:12.38#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:12.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:12.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:12.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:12.50#ibcon#enter wrdev, iclass 32, count 0 2006.257.03:59:12.50#ibcon#first serial, iclass 32, count 0 2006.257.03:59:12.50#ibcon#enter sib2, iclass 32, count 0 2006.257.03:59:12.50#ibcon#flushed, iclass 32, count 0 2006.257.03:59:12.50#ibcon#about to write, iclass 32, count 0 2006.257.03:59:12.50#ibcon#wrote, iclass 32, count 0 2006.257.03:59:12.50#ibcon#about to read 3, iclass 32, count 0 2006.257.03:59:12.52#ibcon#read 3, iclass 32, count 0 2006.257.03:59:12.52#ibcon#about to read 4, iclass 32, count 0 2006.257.03:59:12.52#ibcon#read 4, iclass 32, count 0 2006.257.03:59:12.52#ibcon#about to read 5, iclass 32, count 0 2006.257.03:59:12.52#ibcon#read 5, iclass 32, count 0 2006.257.03:59:12.52#ibcon#about to read 6, iclass 32, count 0 2006.257.03:59:12.52#ibcon#read 6, iclass 32, count 0 2006.257.03:59:12.52#ibcon#end of sib2, iclass 32, count 0 2006.257.03:59:12.52#ibcon#*mode == 0, iclass 32, count 0 2006.257.03:59:12.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.03:59:12.52#ibcon#[27=USB\r\n] 2006.257.03:59:12.52#ibcon#*before write, iclass 32, count 0 2006.257.03:59:12.52#ibcon#enter sib2, iclass 32, count 0 2006.257.03:59:12.52#ibcon#flushed, iclass 32, count 0 2006.257.03:59:12.52#ibcon#about to write, iclass 32, count 0 2006.257.03:59:12.52#ibcon#wrote, iclass 32, count 0 2006.257.03:59:12.52#ibcon#about to read 3, iclass 32, count 0 2006.257.03:59:12.55#ibcon#read 3, iclass 32, count 0 2006.257.03:59:12.55#ibcon#about to read 4, iclass 32, count 0 2006.257.03:59:12.55#ibcon#read 4, iclass 32, count 0 2006.257.03:59:12.55#ibcon#about to read 5, iclass 32, count 0 2006.257.03:59:12.55#ibcon#read 5, iclass 32, count 0 2006.257.03:59:12.55#ibcon#about to read 6, iclass 32, count 0 2006.257.03:59:12.55#ibcon#read 6, iclass 32, count 0 2006.257.03:59:12.55#ibcon#end of sib2, iclass 32, count 0 2006.257.03:59:12.55#ibcon#*after write, iclass 32, count 0 2006.257.03:59:12.55#ibcon#*before return 0, iclass 32, count 0 2006.257.03:59:12.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:12.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.03:59:12.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.03:59:12.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.03:59:12.55$vck44/vblo=3,649.99 2006.257.03:59:12.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.03:59:12.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.03:59:12.55#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:12.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:12.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:12.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:12.55#ibcon#enter wrdev, iclass 34, count 0 2006.257.03:59:12.55#ibcon#first serial, iclass 34, count 0 2006.257.03:59:12.55#ibcon#enter sib2, iclass 34, count 0 2006.257.03:59:12.55#ibcon#flushed, iclass 34, count 0 2006.257.03:59:12.55#ibcon#about to write, iclass 34, count 0 2006.257.03:59:12.55#ibcon#wrote, iclass 34, count 0 2006.257.03:59:12.55#ibcon#about to read 3, iclass 34, count 0 2006.257.03:59:12.57#ibcon#read 3, iclass 34, count 0 2006.257.03:59:12.57#ibcon#about to read 4, iclass 34, count 0 2006.257.03:59:12.57#ibcon#read 4, iclass 34, count 0 2006.257.03:59:12.57#ibcon#about to read 5, iclass 34, count 0 2006.257.03:59:12.57#ibcon#read 5, iclass 34, count 0 2006.257.03:59:12.57#ibcon#about to read 6, iclass 34, count 0 2006.257.03:59:12.57#ibcon#read 6, iclass 34, count 0 2006.257.03:59:12.57#ibcon#end of sib2, iclass 34, count 0 2006.257.03:59:12.57#ibcon#*mode == 0, iclass 34, count 0 2006.257.03:59:12.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.03:59:12.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.03:59:12.57#ibcon#*before write, iclass 34, count 0 2006.257.03:59:12.57#ibcon#enter sib2, iclass 34, count 0 2006.257.03:59:12.57#ibcon#flushed, iclass 34, count 0 2006.257.03:59:12.57#ibcon#about to write, iclass 34, count 0 2006.257.03:59:12.57#ibcon#wrote, iclass 34, count 0 2006.257.03:59:12.57#ibcon#about to read 3, iclass 34, count 0 2006.257.03:59:12.61#ibcon#read 3, iclass 34, count 0 2006.257.03:59:12.61#ibcon#about to read 4, iclass 34, count 0 2006.257.03:59:12.61#ibcon#read 4, iclass 34, count 0 2006.257.03:59:12.61#ibcon#about to read 5, iclass 34, count 0 2006.257.03:59:12.61#ibcon#read 5, iclass 34, count 0 2006.257.03:59:12.61#ibcon#about to read 6, iclass 34, count 0 2006.257.03:59:12.61#ibcon#read 6, iclass 34, count 0 2006.257.03:59:12.61#ibcon#end of sib2, iclass 34, count 0 2006.257.03:59:12.61#ibcon#*after write, iclass 34, count 0 2006.257.03:59:12.61#ibcon#*before return 0, iclass 34, count 0 2006.257.03:59:12.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:12.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.03:59:12.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.03:59:12.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.03:59:12.61$vck44/vb=3,4 2006.257.03:59:12.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.03:59:12.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.03:59:12.61#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:12.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:12.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:12.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:12.67#ibcon#enter wrdev, iclass 36, count 2 2006.257.03:59:12.67#ibcon#first serial, iclass 36, count 2 2006.257.03:59:12.67#ibcon#enter sib2, iclass 36, count 2 2006.257.03:59:12.67#ibcon#flushed, iclass 36, count 2 2006.257.03:59:12.67#ibcon#about to write, iclass 36, count 2 2006.257.03:59:12.67#ibcon#wrote, iclass 36, count 2 2006.257.03:59:12.67#ibcon#about to read 3, iclass 36, count 2 2006.257.03:59:12.69#ibcon#read 3, iclass 36, count 2 2006.257.03:59:12.69#ibcon#about to read 4, iclass 36, count 2 2006.257.03:59:12.69#ibcon#read 4, iclass 36, count 2 2006.257.03:59:12.69#ibcon#about to read 5, iclass 36, count 2 2006.257.03:59:12.69#ibcon#read 5, iclass 36, count 2 2006.257.03:59:12.69#ibcon#about to read 6, iclass 36, count 2 2006.257.03:59:12.69#ibcon#read 6, iclass 36, count 2 2006.257.03:59:12.69#ibcon#end of sib2, iclass 36, count 2 2006.257.03:59:12.69#ibcon#*mode == 0, iclass 36, count 2 2006.257.03:59:12.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.03:59:12.69#ibcon#[27=AT03-04\r\n] 2006.257.03:59:12.69#ibcon#*before write, iclass 36, count 2 2006.257.03:59:12.69#ibcon#enter sib2, iclass 36, count 2 2006.257.03:59:12.69#ibcon#flushed, iclass 36, count 2 2006.257.03:59:12.69#ibcon#about to write, iclass 36, count 2 2006.257.03:59:12.69#ibcon#wrote, iclass 36, count 2 2006.257.03:59:12.69#ibcon#about to read 3, iclass 36, count 2 2006.257.03:59:12.72#ibcon#read 3, iclass 36, count 2 2006.257.03:59:12.72#ibcon#about to read 4, iclass 36, count 2 2006.257.03:59:12.72#ibcon#read 4, iclass 36, count 2 2006.257.03:59:12.72#ibcon#about to read 5, iclass 36, count 2 2006.257.03:59:12.72#ibcon#read 5, iclass 36, count 2 2006.257.03:59:12.72#ibcon#about to read 6, iclass 36, count 2 2006.257.03:59:12.72#ibcon#read 6, iclass 36, count 2 2006.257.03:59:12.72#ibcon#end of sib2, iclass 36, count 2 2006.257.03:59:12.72#ibcon#*after write, iclass 36, count 2 2006.257.03:59:12.72#ibcon#*before return 0, iclass 36, count 2 2006.257.03:59:12.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:12.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.03:59:12.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.03:59:12.72#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:12.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:12.83#abcon#<5=/14 2.0 6.8 19.15 951012.0\r\n> 2006.257.03:59:12.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:12.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:12.84#ibcon#enter wrdev, iclass 36, count 0 2006.257.03:59:12.84#ibcon#first serial, iclass 36, count 0 2006.257.03:59:12.84#ibcon#enter sib2, iclass 36, count 0 2006.257.03:59:12.84#ibcon#flushed, iclass 36, count 0 2006.257.03:59:12.84#ibcon#about to write, iclass 36, count 0 2006.257.03:59:12.84#ibcon#wrote, iclass 36, count 0 2006.257.03:59:12.84#ibcon#about to read 3, iclass 36, count 0 2006.257.03:59:12.85#abcon#{5=INTERFACE CLEAR} 2006.257.03:59:12.86#ibcon#read 3, iclass 36, count 0 2006.257.03:59:12.86#ibcon#about to read 4, iclass 36, count 0 2006.257.03:59:12.86#ibcon#read 4, iclass 36, count 0 2006.257.03:59:12.86#ibcon#about to read 5, iclass 36, count 0 2006.257.03:59:12.86#ibcon#read 5, iclass 36, count 0 2006.257.03:59:12.86#ibcon#about to read 6, iclass 36, count 0 2006.257.03:59:12.86#ibcon#read 6, iclass 36, count 0 2006.257.03:59:12.86#ibcon#end of sib2, iclass 36, count 0 2006.257.03:59:12.86#ibcon#*mode == 0, iclass 36, count 0 2006.257.03:59:12.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.03:59:12.86#ibcon#[27=USB\r\n] 2006.257.03:59:12.86#ibcon#*before write, iclass 36, count 0 2006.257.03:59:12.86#ibcon#enter sib2, iclass 36, count 0 2006.257.03:59:12.86#ibcon#flushed, iclass 36, count 0 2006.257.03:59:12.86#ibcon#about to write, iclass 36, count 0 2006.257.03:59:12.86#ibcon#wrote, iclass 36, count 0 2006.257.03:59:12.86#ibcon#about to read 3, iclass 36, count 0 2006.257.03:59:12.89#ibcon#read 3, iclass 36, count 0 2006.257.03:59:12.89#ibcon#about to read 4, iclass 36, count 0 2006.257.03:59:12.89#ibcon#read 4, iclass 36, count 0 2006.257.03:59:12.89#ibcon#about to read 5, iclass 36, count 0 2006.257.03:59:12.89#ibcon#read 5, iclass 36, count 0 2006.257.03:59:12.89#ibcon#about to read 6, iclass 36, count 0 2006.257.03:59:12.89#ibcon#read 6, iclass 36, count 0 2006.257.03:59:12.89#ibcon#end of sib2, iclass 36, count 0 2006.257.03:59:12.89#ibcon#*after write, iclass 36, count 0 2006.257.03:59:12.89#ibcon#*before return 0, iclass 36, count 0 2006.257.03:59:12.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:12.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.03:59:12.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.03:59:12.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.03:59:12.89$vck44/vblo=4,679.99 2006.257.03:59:12.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.03:59:12.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.03:59:12.89#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:12.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:59:12.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:59:12.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:59:12.89#ibcon#enter wrdev, iclass 3, count 0 2006.257.03:59:12.89#ibcon#first serial, iclass 3, count 0 2006.257.03:59:12.89#ibcon#enter sib2, iclass 3, count 0 2006.257.03:59:12.89#ibcon#flushed, iclass 3, count 0 2006.257.03:59:12.89#ibcon#about to write, iclass 3, count 0 2006.257.03:59:12.89#ibcon#wrote, iclass 3, count 0 2006.257.03:59:12.89#ibcon#about to read 3, iclass 3, count 0 2006.257.03:59:12.91#ibcon#read 3, iclass 3, count 0 2006.257.03:59:12.91#ibcon#about to read 4, iclass 3, count 0 2006.257.03:59:12.91#ibcon#read 4, iclass 3, count 0 2006.257.03:59:12.91#ibcon#about to read 5, iclass 3, count 0 2006.257.03:59:12.91#ibcon#read 5, iclass 3, count 0 2006.257.03:59:12.91#ibcon#about to read 6, iclass 3, count 0 2006.257.03:59:12.91#ibcon#read 6, iclass 3, count 0 2006.257.03:59:12.91#ibcon#end of sib2, iclass 3, count 0 2006.257.03:59:12.91#ibcon#*mode == 0, iclass 3, count 0 2006.257.03:59:12.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.03:59:12.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.03:59:12.91#ibcon#*before write, iclass 3, count 0 2006.257.03:59:12.91#ibcon#enter sib2, iclass 3, count 0 2006.257.03:59:12.91#ibcon#flushed, iclass 3, count 0 2006.257.03:59:12.91#ibcon#about to write, iclass 3, count 0 2006.257.03:59:12.91#ibcon#wrote, iclass 3, count 0 2006.257.03:59:12.91#ibcon#about to read 3, iclass 3, count 0 2006.257.03:59:12.91#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:59:12.95#ibcon#read 3, iclass 3, count 0 2006.257.03:59:12.95#ibcon#about to read 4, iclass 3, count 0 2006.257.03:59:12.95#ibcon#read 4, iclass 3, count 0 2006.257.03:59:12.95#ibcon#about to read 5, iclass 3, count 0 2006.257.03:59:12.95#ibcon#read 5, iclass 3, count 0 2006.257.03:59:12.95#ibcon#about to read 6, iclass 3, count 0 2006.257.03:59:12.95#ibcon#read 6, iclass 3, count 0 2006.257.03:59:12.95#ibcon#end of sib2, iclass 3, count 0 2006.257.03:59:12.95#ibcon#*after write, iclass 3, count 0 2006.257.03:59:12.95#ibcon#*before return 0, iclass 3, count 0 2006.257.03:59:12.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:59:12.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.03:59:12.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.03:59:12.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.03:59:12.95$vck44/vb=4,5 2006.257.03:59:12.95#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.03:59:12.95#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.03:59:12.95#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:12.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:13.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:13.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:13.01#ibcon#enter wrdev, iclass 6, count 2 2006.257.03:59:13.01#ibcon#first serial, iclass 6, count 2 2006.257.03:59:13.01#ibcon#enter sib2, iclass 6, count 2 2006.257.03:59:13.01#ibcon#flushed, iclass 6, count 2 2006.257.03:59:13.01#ibcon#about to write, iclass 6, count 2 2006.257.03:59:13.01#ibcon#wrote, iclass 6, count 2 2006.257.03:59:13.01#ibcon#about to read 3, iclass 6, count 2 2006.257.03:59:13.03#ibcon#read 3, iclass 6, count 2 2006.257.03:59:13.03#ibcon#about to read 4, iclass 6, count 2 2006.257.03:59:13.03#ibcon#read 4, iclass 6, count 2 2006.257.03:59:13.03#ibcon#about to read 5, iclass 6, count 2 2006.257.03:59:13.03#ibcon#read 5, iclass 6, count 2 2006.257.03:59:13.03#ibcon#about to read 6, iclass 6, count 2 2006.257.03:59:13.03#ibcon#read 6, iclass 6, count 2 2006.257.03:59:13.03#ibcon#end of sib2, iclass 6, count 2 2006.257.03:59:13.03#ibcon#*mode == 0, iclass 6, count 2 2006.257.03:59:13.03#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.03:59:13.03#ibcon#[27=AT04-05\r\n] 2006.257.03:59:13.03#ibcon#*before write, iclass 6, count 2 2006.257.03:59:13.03#ibcon#enter sib2, iclass 6, count 2 2006.257.03:59:13.03#ibcon#flushed, iclass 6, count 2 2006.257.03:59:13.03#ibcon#about to write, iclass 6, count 2 2006.257.03:59:13.03#ibcon#wrote, iclass 6, count 2 2006.257.03:59:13.03#ibcon#about to read 3, iclass 6, count 2 2006.257.03:59:13.06#ibcon#read 3, iclass 6, count 2 2006.257.03:59:13.06#ibcon#about to read 4, iclass 6, count 2 2006.257.03:59:13.06#ibcon#read 4, iclass 6, count 2 2006.257.03:59:13.06#ibcon#about to read 5, iclass 6, count 2 2006.257.03:59:13.06#ibcon#read 5, iclass 6, count 2 2006.257.03:59:13.06#ibcon#about to read 6, iclass 6, count 2 2006.257.03:59:13.06#ibcon#read 6, iclass 6, count 2 2006.257.03:59:13.06#ibcon#end of sib2, iclass 6, count 2 2006.257.03:59:13.06#ibcon#*after write, iclass 6, count 2 2006.257.03:59:13.06#ibcon#*before return 0, iclass 6, count 2 2006.257.03:59:13.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:13.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.03:59:13.06#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.03:59:13.06#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:13.06#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:13.18#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:13.18#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:13.18#ibcon#enter wrdev, iclass 6, count 0 2006.257.03:59:13.18#ibcon#first serial, iclass 6, count 0 2006.257.03:59:13.18#ibcon#enter sib2, iclass 6, count 0 2006.257.03:59:13.18#ibcon#flushed, iclass 6, count 0 2006.257.03:59:13.18#ibcon#about to write, iclass 6, count 0 2006.257.03:59:13.18#ibcon#wrote, iclass 6, count 0 2006.257.03:59:13.18#ibcon#about to read 3, iclass 6, count 0 2006.257.03:59:13.20#ibcon#read 3, iclass 6, count 0 2006.257.03:59:13.20#ibcon#about to read 4, iclass 6, count 0 2006.257.03:59:13.20#ibcon#read 4, iclass 6, count 0 2006.257.03:59:13.20#ibcon#about to read 5, iclass 6, count 0 2006.257.03:59:13.20#ibcon#read 5, iclass 6, count 0 2006.257.03:59:13.20#ibcon#about to read 6, iclass 6, count 0 2006.257.03:59:13.20#ibcon#read 6, iclass 6, count 0 2006.257.03:59:13.20#ibcon#end of sib2, iclass 6, count 0 2006.257.03:59:13.20#ibcon#*mode == 0, iclass 6, count 0 2006.257.03:59:13.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.03:59:13.20#ibcon#[27=USB\r\n] 2006.257.03:59:13.20#ibcon#*before write, iclass 6, count 0 2006.257.03:59:13.20#ibcon#enter sib2, iclass 6, count 0 2006.257.03:59:13.20#ibcon#flushed, iclass 6, count 0 2006.257.03:59:13.20#ibcon#about to write, iclass 6, count 0 2006.257.03:59:13.20#ibcon#wrote, iclass 6, count 0 2006.257.03:59:13.20#ibcon#about to read 3, iclass 6, count 0 2006.257.03:59:13.23#ibcon#read 3, iclass 6, count 0 2006.257.03:59:13.23#ibcon#about to read 4, iclass 6, count 0 2006.257.03:59:13.23#ibcon#read 4, iclass 6, count 0 2006.257.03:59:13.23#ibcon#about to read 5, iclass 6, count 0 2006.257.03:59:13.23#ibcon#read 5, iclass 6, count 0 2006.257.03:59:13.23#ibcon#about to read 6, iclass 6, count 0 2006.257.03:59:13.23#ibcon#read 6, iclass 6, count 0 2006.257.03:59:13.23#ibcon#end of sib2, iclass 6, count 0 2006.257.03:59:13.23#ibcon#*after write, iclass 6, count 0 2006.257.03:59:13.23#ibcon#*before return 0, iclass 6, count 0 2006.257.03:59:13.23#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:13.23#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.03:59:13.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.03:59:13.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.03:59:13.23$vck44/vblo=5,709.99 2006.257.03:59:13.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.03:59:13.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.03:59:13.23#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:13.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:13.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:13.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:13.23#ibcon#enter wrdev, iclass 10, count 0 2006.257.03:59:13.23#ibcon#first serial, iclass 10, count 0 2006.257.03:59:13.23#ibcon#enter sib2, iclass 10, count 0 2006.257.03:59:13.23#ibcon#flushed, iclass 10, count 0 2006.257.03:59:13.23#ibcon#about to write, iclass 10, count 0 2006.257.03:59:13.23#ibcon#wrote, iclass 10, count 0 2006.257.03:59:13.23#ibcon#about to read 3, iclass 10, count 0 2006.257.03:59:13.25#ibcon#read 3, iclass 10, count 0 2006.257.03:59:13.25#ibcon#about to read 4, iclass 10, count 0 2006.257.03:59:13.25#ibcon#read 4, iclass 10, count 0 2006.257.03:59:13.25#ibcon#about to read 5, iclass 10, count 0 2006.257.03:59:13.25#ibcon#read 5, iclass 10, count 0 2006.257.03:59:13.25#ibcon#about to read 6, iclass 10, count 0 2006.257.03:59:13.25#ibcon#read 6, iclass 10, count 0 2006.257.03:59:13.25#ibcon#end of sib2, iclass 10, count 0 2006.257.03:59:13.25#ibcon#*mode == 0, iclass 10, count 0 2006.257.03:59:13.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.03:59:13.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.03:59:13.25#ibcon#*before write, iclass 10, count 0 2006.257.03:59:13.25#ibcon#enter sib2, iclass 10, count 0 2006.257.03:59:13.25#ibcon#flushed, iclass 10, count 0 2006.257.03:59:13.25#ibcon#about to write, iclass 10, count 0 2006.257.03:59:13.25#ibcon#wrote, iclass 10, count 0 2006.257.03:59:13.25#ibcon#about to read 3, iclass 10, count 0 2006.257.03:59:13.29#ibcon#read 3, iclass 10, count 0 2006.257.03:59:13.29#ibcon#about to read 4, iclass 10, count 0 2006.257.03:59:13.29#ibcon#read 4, iclass 10, count 0 2006.257.03:59:13.29#ibcon#about to read 5, iclass 10, count 0 2006.257.03:59:13.29#ibcon#read 5, iclass 10, count 0 2006.257.03:59:13.29#ibcon#about to read 6, iclass 10, count 0 2006.257.03:59:13.29#ibcon#read 6, iclass 10, count 0 2006.257.03:59:13.29#ibcon#end of sib2, iclass 10, count 0 2006.257.03:59:13.29#ibcon#*after write, iclass 10, count 0 2006.257.03:59:13.29#ibcon#*before return 0, iclass 10, count 0 2006.257.03:59:13.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:13.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.03:59:13.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.03:59:13.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.03:59:13.29$vck44/vb=5,4 2006.257.03:59:13.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.03:59:13.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.03:59:13.29#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:13.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:13.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:13.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:13.35#ibcon#enter wrdev, iclass 12, count 2 2006.257.03:59:13.35#ibcon#first serial, iclass 12, count 2 2006.257.03:59:13.35#ibcon#enter sib2, iclass 12, count 2 2006.257.03:59:13.35#ibcon#flushed, iclass 12, count 2 2006.257.03:59:13.35#ibcon#about to write, iclass 12, count 2 2006.257.03:59:13.35#ibcon#wrote, iclass 12, count 2 2006.257.03:59:13.35#ibcon#about to read 3, iclass 12, count 2 2006.257.03:59:13.37#ibcon#read 3, iclass 12, count 2 2006.257.03:59:13.37#ibcon#about to read 4, iclass 12, count 2 2006.257.03:59:13.37#ibcon#read 4, iclass 12, count 2 2006.257.03:59:13.37#ibcon#about to read 5, iclass 12, count 2 2006.257.03:59:13.37#ibcon#read 5, iclass 12, count 2 2006.257.03:59:13.37#ibcon#about to read 6, iclass 12, count 2 2006.257.03:59:13.37#ibcon#read 6, iclass 12, count 2 2006.257.03:59:13.37#ibcon#end of sib2, iclass 12, count 2 2006.257.03:59:13.37#ibcon#*mode == 0, iclass 12, count 2 2006.257.03:59:13.37#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.03:59:13.37#ibcon#[27=AT05-04\r\n] 2006.257.03:59:13.37#ibcon#*before write, iclass 12, count 2 2006.257.03:59:13.37#ibcon#enter sib2, iclass 12, count 2 2006.257.03:59:13.37#ibcon#flushed, iclass 12, count 2 2006.257.03:59:13.37#ibcon#about to write, iclass 12, count 2 2006.257.03:59:13.37#ibcon#wrote, iclass 12, count 2 2006.257.03:59:13.37#ibcon#about to read 3, iclass 12, count 2 2006.257.03:59:13.40#ibcon#read 3, iclass 12, count 2 2006.257.03:59:13.40#ibcon#about to read 4, iclass 12, count 2 2006.257.03:59:13.40#ibcon#read 4, iclass 12, count 2 2006.257.03:59:13.40#ibcon#about to read 5, iclass 12, count 2 2006.257.03:59:13.40#ibcon#read 5, iclass 12, count 2 2006.257.03:59:13.40#ibcon#about to read 6, iclass 12, count 2 2006.257.03:59:13.40#ibcon#read 6, iclass 12, count 2 2006.257.03:59:13.40#ibcon#end of sib2, iclass 12, count 2 2006.257.03:59:13.40#ibcon#*after write, iclass 12, count 2 2006.257.03:59:13.40#ibcon#*before return 0, iclass 12, count 2 2006.257.03:59:13.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:13.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.03:59:13.40#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.03:59:13.40#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:13.40#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:13.52#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:13.52#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:13.52#ibcon#enter wrdev, iclass 12, count 0 2006.257.03:59:13.52#ibcon#first serial, iclass 12, count 0 2006.257.03:59:13.52#ibcon#enter sib2, iclass 12, count 0 2006.257.03:59:13.52#ibcon#flushed, iclass 12, count 0 2006.257.03:59:13.52#ibcon#about to write, iclass 12, count 0 2006.257.03:59:13.52#ibcon#wrote, iclass 12, count 0 2006.257.03:59:13.52#ibcon#about to read 3, iclass 12, count 0 2006.257.03:59:13.54#ibcon#read 3, iclass 12, count 0 2006.257.03:59:13.54#ibcon#about to read 4, iclass 12, count 0 2006.257.03:59:13.54#ibcon#read 4, iclass 12, count 0 2006.257.03:59:13.54#ibcon#about to read 5, iclass 12, count 0 2006.257.03:59:13.54#ibcon#read 5, iclass 12, count 0 2006.257.03:59:13.54#ibcon#about to read 6, iclass 12, count 0 2006.257.03:59:13.54#ibcon#read 6, iclass 12, count 0 2006.257.03:59:13.54#ibcon#end of sib2, iclass 12, count 0 2006.257.03:59:13.54#ibcon#*mode == 0, iclass 12, count 0 2006.257.03:59:13.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.03:59:13.54#ibcon#[27=USB\r\n] 2006.257.03:59:13.54#ibcon#*before write, iclass 12, count 0 2006.257.03:59:13.54#ibcon#enter sib2, iclass 12, count 0 2006.257.03:59:13.54#ibcon#flushed, iclass 12, count 0 2006.257.03:59:13.54#ibcon#about to write, iclass 12, count 0 2006.257.03:59:13.54#ibcon#wrote, iclass 12, count 0 2006.257.03:59:13.54#ibcon#about to read 3, iclass 12, count 0 2006.257.03:59:13.57#ibcon#read 3, iclass 12, count 0 2006.257.03:59:13.57#ibcon#about to read 4, iclass 12, count 0 2006.257.03:59:13.57#ibcon#read 4, iclass 12, count 0 2006.257.03:59:13.57#ibcon#about to read 5, iclass 12, count 0 2006.257.03:59:13.57#ibcon#read 5, iclass 12, count 0 2006.257.03:59:13.57#ibcon#about to read 6, iclass 12, count 0 2006.257.03:59:13.57#ibcon#read 6, iclass 12, count 0 2006.257.03:59:13.57#ibcon#end of sib2, iclass 12, count 0 2006.257.03:59:13.57#ibcon#*after write, iclass 12, count 0 2006.257.03:59:13.57#ibcon#*before return 0, iclass 12, count 0 2006.257.03:59:13.57#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:13.57#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.03:59:13.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.03:59:13.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.03:59:13.57$vck44/vblo=6,719.99 2006.257.03:59:13.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.03:59:13.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.03:59:13.57#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:13.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:13.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:13.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:13.57#ibcon#enter wrdev, iclass 14, count 0 2006.257.03:59:13.57#ibcon#first serial, iclass 14, count 0 2006.257.03:59:13.57#ibcon#enter sib2, iclass 14, count 0 2006.257.03:59:13.57#ibcon#flushed, iclass 14, count 0 2006.257.03:59:13.57#ibcon#about to write, iclass 14, count 0 2006.257.03:59:13.57#ibcon#wrote, iclass 14, count 0 2006.257.03:59:13.57#ibcon#about to read 3, iclass 14, count 0 2006.257.03:59:13.59#ibcon#read 3, iclass 14, count 0 2006.257.03:59:13.59#ibcon#about to read 4, iclass 14, count 0 2006.257.03:59:13.59#ibcon#read 4, iclass 14, count 0 2006.257.03:59:13.59#ibcon#about to read 5, iclass 14, count 0 2006.257.03:59:13.59#ibcon#read 5, iclass 14, count 0 2006.257.03:59:13.59#ibcon#about to read 6, iclass 14, count 0 2006.257.03:59:13.59#ibcon#read 6, iclass 14, count 0 2006.257.03:59:13.59#ibcon#end of sib2, iclass 14, count 0 2006.257.03:59:13.59#ibcon#*mode == 0, iclass 14, count 0 2006.257.03:59:13.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.03:59:13.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.03:59:13.59#ibcon#*before write, iclass 14, count 0 2006.257.03:59:13.59#ibcon#enter sib2, iclass 14, count 0 2006.257.03:59:13.59#ibcon#flushed, iclass 14, count 0 2006.257.03:59:13.59#ibcon#about to write, iclass 14, count 0 2006.257.03:59:13.59#ibcon#wrote, iclass 14, count 0 2006.257.03:59:13.59#ibcon#about to read 3, iclass 14, count 0 2006.257.03:59:13.63#ibcon#read 3, iclass 14, count 0 2006.257.03:59:13.63#ibcon#about to read 4, iclass 14, count 0 2006.257.03:59:13.63#ibcon#read 4, iclass 14, count 0 2006.257.03:59:13.63#ibcon#about to read 5, iclass 14, count 0 2006.257.03:59:13.63#ibcon#read 5, iclass 14, count 0 2006.257.03:59:13.63#ibcon#about to read 6, iclass 14, count 0 2006.257.03:59:13.63#ibcon#read 6, iclass 14, count 0 2006.257.03:59:13.63#ibcon#end of sib2, iclass 14, count 0 2006.257.03:59:13.63#ibcon#*after write, iclass 14, count 0 2006.257.03:59:13.63#ibcon#*before return 0, iclass 14, count 0 2006.257.03:59:13.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:13.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.03:59:13.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.03:59:13.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.03:59:13.63$vck44/vb=6,4 2006.257.03:59:13.63#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.03:59:13.63#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.03:59:13.63#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:13.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:13.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:13.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:13.69#ibcon#enter wrdev, iclass 16, count 2 2006.257.03:59:13.69#ibcon#first serial, iclass 16, count 2 2006.257.03:59:13.69#ibcon#enter sib2, iclass 16, count 2 2006.257.03:59:13.69#ibcon#flushed, iclass 16, count 2 2006.257.03:59:13.69#ibcon#about to write, iclass 16, count 2 2006.257.03:59:13.69#ibcon#wrote, iclass 16, count 2 2006.257.03:59:13.69#ibcon#about to read 3, iclass 16, count 2 2006.257.03:59:13.71#ibcon#read 3, iclass 16, count 2 2006.257.03:59:13.71#ibcon#about to read 4, iclass 16, count 2 2006.257.03:59:13.71#ibcon#read 4, iclass 16, count 2 2006.257.03:59:13.71#ibcon#about to read 5, iclass 16, count 2 2006.257.03:59:13.71#ibcon#read 5, iclass 16, count 2 2006.257.03:59:13.71#ibcon#about to read 6, iclass 16, count 2 2006.257.03:59:13.71#ibcon#read 6, iclass 16, count 2 2006.257.03:59:13.71#ibcon#end of sib2, iclass 16, count 2 2006.257.03:59:13.71#ibcon#*mode == 0, iclass 16, count 2 2006.257.03:59:13.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.03:59:13.71#ibcon#[27=AT06-04\r\n] 2006.257.03:59:13.71#ibcon#*before write, iclass 16, count 2 2006.257.03:59:13.71#ibcon#enter sib2, iclass 16, count 2 2006.257.03:59:13.71#ibcon#flushed, iclass 16, count 2 2006.257.03:59:13.71#ibcon#about to write, iclass 16, count 2 2006.257.03:59:13.71#ibcon#wrote, iclass 16, count 2 2006.257.03:59:13.71#ibcon#about to read 3, iclass 16, count 2 2006.257.03:59:13.74#ibcon#read 3, iclass 16, count 2 2006.257.03:59:13.74#ibcon#about to read 4, iclass 16, count 2 2006.257.03:59:13.74#ibcon#read 4, iclass 16, count 2 2006.257.03:59:13.74#ibcon#about to read 5, iclass 16, count 2 2006.257.03:59:13.74#ibcon#read 5, iclass 16, count 2 2006.257.03:59:13.74#ibcon#about to read 6, iclass 16, count 2 2006.257.03:59:13.74#ibcon#read 6, iclass 16, count 2 2006.257.03:59:13.74#ibcon#end of sib2, iclass 16, count 2 2006.257.03:59:13.74#ibcon#*after write, iclass 16, count 2 2006.257.03:59:13.74#ibcon#*before return 0, iclass 16, count 2 2006.257.03:59:13.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:13.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.03:59:13.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.03:59:13.74#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:13.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:13.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:13.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:13.86#ibcon#enter wrdev, iclass 16, count 0 2006.257.03:59:13.86#ibcon#first serial, iclass 16, count 0 2006.257.03:59:13.86#ibcon#enter sib2, iclass 16, count 0 2006.257.03:59:13.86#ibcon#flushed, iclass 16, count 0 2006.257.03:59:13.86#ibcon#about to write, iclass 16, count 0 2006.257.03:59:13.86#ibcon#wrote, iclass 16, count 0 2006.257.03:59:13.86#ibcon#about to read 3, iclass 16, count 0 2006.257.03:59:13.88#ibcon#read 3, iclass 16, count 0 2006.257.03:59:13.88#ibcon#about to read 4, iclass 16, count 0 2006.257.03:59:13.88#ibcon#read 4, iclass 16, count 0 2006.257.03:59:13.88#ibcon#about to read 5, iclass 16, count 0 2006.257.03:59:13.88#ibcon#read 5, iclass 16, count 0 2006.257.03:59:13.88#ibcon#about to read 6, iclass 16, count 0 2006.257.03:59:13.88#ibcon#read 6, iclass 16, count 0 2006.257.03:59:13.88#ibcon#end of sib2, iclass 16, count 0 2006.257.03:59:13.88#ibcon#*mode == 0, iclass 16, count 0 2006.257.03:59:13.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.03:59:13.88#ibcon#[27=USB\r\n] 2006.257.03:59:13.88#ibcon#*before write, iclass 16, count 0 2006.257.03:59:13.88#ibcon#enter sib2, iclass 16, count 0 2006.257.03:59:13.88#ibcon#flushed, iclass 16, count 0 2006.257.03:59:13.88#ibcon#about to write, iclass 16, count 0 2006.257.03:59:13.88#ibcon#wrote, iclass 16, count 0 2006.257.03:59:13.88#ibcon#about to read 3, iclass 16, count 0 2006.257.03:59:13.91#ibcon#read 3, iclass 16, count 0 2006.257.03:59:13.91#ibcon#about to read 4, iclass 16, count 0 2006.257.03:59:13.91#ibcon#read 4, iclass 16, count 0 2006.257.03:59:13.91#ibcon#about to read 5, iclass 16, count 0 2006.257.03:59:13.91#ibcon#read 5, iclass 16, count 0 2006.257.03:59:13.91#ibcon#about to read 6, iclass 16, count 0 2006.257.03:59:13.91#ibcon#read 6, iclass 16, count 0 2006.257.03:59:13.91#ibcon#end of sib2, iclass 16, count 0 2006.257.03:59:13.91#ibcon#*after write, iclass 16, count 0 2006.257.03:59:13.91#ibcon#*before return 0, iclass 16, count 0 2006.257.03:59:13.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:13.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.03:59:13.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.03:59:13.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.03:59:13.91$vck44/vblo=7,734.99 2006.257.03:59:13.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.03:59:13.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.03:59:13.91#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:13.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:13.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:13.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:13.91#ibcon#enter wrdev, iclass 18, count 0 2006.257.03:59:13.91#ibcon#first serial, iclass 18, count 0 2006.257.03:59:13.91#ibcon#enter sib2, iclass 18, count 0 2006.257.03:59:13.91#ibcon#flushed, iclass 18, count 0 2006.257.03:59:13.91#ibcon#about to write, iclass 18, count 0 2006.257.03:59:13.91#ibcon#wrote, iclass 18, count 0 2006.257.03:59:13.91#ibcon#about to read 3, iclass 18, count 0 2006.257.03:59:13.93#ibcon#read 3, iclass 18, count 0 2006.257.03:59:13.93#ibcon#about to read 4, iclass 18, count 0 2006.257.03:59:13.93#ibcon#read 4, iclass 18, count 0 2006.257.03:59:13.93#ibcon#about to read 5, iclass 18, count 0 2006.257.03:59:13.93#ibcon#read 5, iclass 18, count 0 2006.257.03:59:13.93#ibcon#about to read 6, iclass 18, count 0 2006.257.03:59:13.93#ibcon#read 6, iclass 18, count 0 2006.257.03:59:13.93#ibcon#end of sib2, iclass 18, count 0 2006.257.03:59:13.93#ibcon#*mode == 0, iclass 18, count 0 2006.257.03:59:13.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.03:59:13.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.03:59:13.93#ibcon#*before write, iclass 18, count 0 2006.257.03:59:13.93#ibcon#enter sib2, iclass 18, count 0 2006.257.03:59:13.93#ibcon#flushed, iclass 18, count 0 2006.257.03:59:13.93#ibcon#about to write, iclass 18, count 0 2006.257.03:59:13.93#ibcon#wrote, iclass 18, count 0 2006.257.03:59:13.93#ibcon#about to read 3, iclass 18, count 0 2006.257.03:59:13.97#ibcon#read 3, iclass 18, count 0 2006.257.03:59:13.97#ibcon#about to read 4, iclass 18, count 0 2006.257.03:59:13.97#ibcon#read 4, iclass 18, count 0 2006.257.03:59:13.97#ibcon#about to read 5, iclass 18, count 0 2006.257.03:59:13.97#ibcon#read 5, iclass 18, count 0 2006.257.03:59:13.97#ibcon#about to read 6, iclass 18, count 0 2006.257.03:59:13.97#ibcon#read 6, iclass 18, count 0 2006.257.03:59:13.97#ibcon#end of sib2, iclass 18, count 0 2006.257.03:59:13.97#ibcon#*after write, iclass 18, count 0 2006.257.03:59:13.97#ibcon#*before return 0, iclass 18, count 0 2006.257.03:59:13.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:13.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.03:59:13.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.03:59:13.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.03:59:13.97$vck44/vb=7,4 2006.257.03:59:13.97#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.03:59:13.97#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.03:59:13.97#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:13.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:14.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:14.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:14.03#ibcon#enter wrdev, iclass 20, count 2 2006.257.03:59:14.03#ibcon#first serial, iclass 20, count 2 2006.257.03:59:14.03#ibcon#enter sib2, iclass 20, count 2 2006.257.03:59:14.03#ibcon#flushed, iclass 20, count 2 2006.257.03:59:14.03#ibcon#about to write, iclass 20, count 2 2006.257.03:59:14.03#ibcon#wrote, iclass 20, count 2 2006.257.03:59:14.03#ibcon#about to read 3, iclass 20, count 2 2006.257.03:59:14.05#ibcon#read 3, iclass 20, count 2 2006.257.03:59:14.05#ibcon#about to read 4, iclass 20, count 2 2006.257.03:59:14.05#ibcon#read 4, iclass 20, count 2 2006.257.03:59:14.05#ibcon#about to read 5, iclass 20, count 2 2006.257.03:59:14.05#ibcon#read 5, iclass 20, count 2 2006.257.03:59:14.05#ibcon#about to read 6, iclass 20, count 2 2006.257.03:59:14.05#ibcon#read 6, iclass 20, count 2 2006.257.03:59:14.05#ibcon#end of sib2, iclass 20, count 2 2006.257.03:59:14.05#ibcon#*mode == 0, iclass 20, count 2 2006.257.03:59:14.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.03:59:14.05#ibcon#[27=AT07-04\r\n] 2006.257.03:59:14.05#ibcon#*before write, iclass 20, count 2 2006.257.03:59:14.05#ibcon#enter sib2, iclass 20, count 2 2006.257.03:59:14.05#ibcon#flushed, iclass 20, count 2 2006.257.03:59:14.05#ibcon#about to write, iclass 20, count 2 2006.257.03:59:14.05#ibcon#wrote, iclass 20, count 2 2006.257.03:59:14.05#ibcon#about to read 3, iclass 20, count 2 2006.257.03:59:14.08#ibcon#read 3, iclass 20, count 2 2006.257.03:59:14.08#ibcon#about to read 4, iclass 20, count 2 2006.257.03:59:14.08#ibcon#read 4, iclass 20, count 2 2006.257.03:59:14.08#ibcon#about to read 5, iclass 20, count 2 2006.257.03:59:14.08#ibcon#read 5, iclass 20, count 2 2006.257.03:59:14.08#ibcon#about to read 6, iclass 20, count 2 2006.257.03:59:14.08#ibcon#read 6, iclass 20, count 2 2006.257.03:59:14.08#ibcon#end of sib2, iclass 20, count 2 2006.257.03:59:14.08#ibcon#*after write, iclass 20, count 2 2006.257.03:59:14.08#ibcon#*before return 0, iclass 20, count 2 2006.257.03:59:14.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:14.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.03:59:14.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.03:59:14.08#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:14.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:14.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:14.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:14.20#ibcon#enter wrdev, iclass 20, count 0 2006.257.03:59:14.20#ibcon#first serial, iclass 20, count 0 2006.257.03:59:14.20#ibcon#enter sib2, iclass 20, count 0 2006.257.03:59:14.20#ibcon#flushed, iclass 20, count 0 2006.257.03:59:14.20#ibcon#about to write, iclass 20, count 0 2006.257.03:59:14.20#ibcon#wrote, iclass 20, count 0 2006.257.03:59:14.20#ibcon#about to read 3, iclass 20, count 0 2006.257.03:59:14.22#ibcon#read 3, iclass 20, count 0 2006.257.03:59:14.22#ibcon#about to read 4, iclass 20, count 0 2006.257.03:59:14.22#ibcon#read 4, iclass 20, count 0 2006.257.03:59:14.22#ibcon#about to read 5, iclass 20, count 0 2006.257.03:59:14.22#ibcon#read 5, iclass 20, count 0 2006.257.03:59:14.22#ibcon#about to read 6, iclass 20, count 0 2006.257.03:59:14.22#ibcon#read 6, iclass 20, count 0 2006.257.03:59:14.22#ibcon#end of sib2, iclass 20, count 0 2006.257.03:59:14.22#ibcon#*mode == 0, iclass 20, count 0 2006.257.03:59:14.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.03:59:14.22#ibcon#[27=USB\r\n] 2006.257.03:59:14.22#ibcon#*before write, iclass 20, count 0 2006.257.03:59:14.22#ibcon#enter sib2, iclass 20, count 0 2006.257.03:59:14.22#ibcon#flushed, iclass 20, count 0 2006.257.03:59:14.22#ibcon#about to write, iclass 20, count 0 2006.257.03:59:14.22#ibcon#wrote, iclass 20, count 0 2006.257.03:59:14.22#ibcon#about to read 3, iclass 20, count 0 2006.257.03:59:14.25#ibcon#read 3, iclass 20, count 0 2006.257.03:59:14.25#ibcon#about to read 4, iclass 20, count 0 2006.257.03:59:14.25#ibcon#read 4, iclass 20, count 0 2006.257.03:59:14.25#ibcon#about to read 5, iclass 20, count 0 2006.257.03:59:14.25#ibcon#read 5, iclass 20, count 0 2006.257.03:59:14.25#ibcon#about to read 6, iclass 20, count 0 2006.257.03:59:14.25#ibcon#read 6, iclass 20, count 0 2006.257.03:59:14.25#ibcon#end of sib2, iclass 20, count 0 2006.257.03:59:14.25#ibcon#*after write, iclass 20, count 0 2006.257.03:59:14.25#ibcon#*before return 0, iclass 20, count 0 2006.257.03:59:14.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:14.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.03:59:14.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.03:59:14.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.03:59:14.25$vck44/vblo=8,744.99 2006.257.03:59:14.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.03:59:14.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.03:59:14.25#ibcon#ireg 17 cls_cnt 0 2006.257.03:59:14.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:14.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:14.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:14.25#ibcon#enter wrdev, iclass 22, count 0 2006.257.03:59:14.25#ibcon#first serial, iclass 22, count 0 2006.257.03:59:14.25#ibcon#enter sib2, iclass 22, count 0 2006.257.03:59:14.25#ibcon#flushed, iclass 22, count 0 2006.257.03:59:14.25#ibcon#about to write, iclass 22, count 0 2006.257.03:59:14.25#ibcon#wrote, iclass 22, count 0 2006.257.03:59:14.25#ibcon#about to read 3, iclass 22, count 0 2006.257.03:59:14.27#ibcon#read 3, iclass 22, count 0 2006.257.03:59:14.27#ibcon#about to read 4, iclass 22, count 0 2006.257.03:59:14.27#ibcon#read 4, iclass 22, count 0 2006.257.03:59:14.27#ibcon#about to read 5, iclass 22, count 0 2006.257.03:59:14.27#ibcon#read 5, iclass 22, count 0 2006.257.03:59:14.27#ibcon#about to read 6, iclass 22, count 0 2006.257.03:59:14.27#ibcon#read 6, iclass 22, count 0 2006.257.03:59:14.27#ibcon#end of sib2, iclass 22, count 0 2006.257.03:59:14.27#ibcon#*mode == 0, iclass 22, count 0 2006.257.03:59:14.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.03:59:14.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.03:59:14.27#ibcon#*before write, iclass 22, count 0 2006.257.03:59:14.27#ibcon#enter sib2, iclass 22, count 0 2006.257.03:59:14.27#ibcon#flushed, iclass 22, count 0 2006.257.03:59:14.27#ibcon#about to write, iclass 22, count 0 2006.257.03:59:14.27#ibcon#wrote, iclass 22, count 0 2006.257.03:59:14.27#ibcon#about to read 3, iclass 22, count 0 2006.257.03:59:14.31#ibcon#read 3, iclass 22, count 0 2006.257.03:59:14.31#ibcon#about to read 4, iclass 22, count 0 2006.257.03:59:14.31#ibcon#read 4, iclass 22, count 0 2006.257.03:59:14.31#ibcon#about to read 5, iclass 22, count 0 2006.257.03:59:14.31#ibcon#read 5, iclass 22, count 0 2006.257.03:59:14.31#ibcon#about to read 6, iclass 22, count 0 2006.257.03:59:14.31#ibcon#read 6, iclass 22, count 0 2006.257.03:59:14.31#ibcon#end of sib2, iclass 22, count 0 2006.257.03:59:14.31#ibcon#*after write, iclass 22, count 0 2006.257.03:59:14.31#ibcon#*before return 0, iclass 22, count 0 2006.257.03:59:14.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:14.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.03:59:14.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.03:59:14.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.03:59:14.31$vck44/vb=8,4 2006.257.03:59:14.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.03:59:14.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.03:59:14.31#ibcon#ireg 11 cls_cnt 2 2006.257.03:59:14.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:14.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:14.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:14.37#ibcon#enter wrdev, iclass 24, count 2 2006.257.03:59:14.37#ibcon#first serial, iclass 24, count 2 2006.257.03:59:14.37#ibcon#enter sib2, iclass 24, count 2 2006.257.03:59:14.37#ibcon#flushed, iclass 24, count 2 2006.257.03:59:14.37#ibcon#about to write, iclass 24, count 2 2006.257.03:59:14.37#ibcon#wrote, iclass 24, count 2 2006.257.03:59:14.37#ibcon#about to read 3, iclass 24, count 2 2006.257.03:59:14.39#ibcon#read 3, iclass 24, count 2 2006.257.03:59:14.39#ibcon#about to read 4, iclass 24, count 2 2006.257.03:59:14.39#ibcon#read 4, iclass 24, count 2 2006.257.03:59:14.39#ibcon#about to read 5, iclass 24, count 2 2006.257.03:59:14.39#ibcon#read 5, iclass 24, count 2 2006.257.03:59:14.39#ibcon#about to read 6, iclass 24, count 2 2006.257.03:59:14.39#ibcon#read 6, iclass 24, count 2 2006.257.03:59:14.39#ibcon#end of sib2, iclass 24, count 2 2006.257.03:59:14.39#ibcon#*mode == 0, iclass 24, count 2 2006.257.03:59:14.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.03:59:14.39#ibcon#[27=AT08-04\r\n] 2006.257.03:59:14.39#ibcon#*before write, iclass 24, count 2 2006.257.03:59:14.39#ibcon#enter sib2, iclass 24, count 2 2006.257.03:59:14.39#ibcon#flushed, iclass 24, count 2 2006.257.03:59:14.39#ibcon#about to write, iclass 24, count 2 2006.257.03:59:14.39#ibcon#wrote, iclass 24, count 2 2006.257.03:59:14.39#ibcon#about to read 3, iclass 24, count 2 2006.257.03:59:14.42#ibcon#read 3, iclass 24, count 2 2006.257.03:59:14.42#ibcon#about to read 4, iclass 24, count 2 2006.257.03:59:14.42#ibcon#read 4, iclass 24, count 2 2006.257.03:59:14.42#ibcon#about to read 5, iclass 24, count 2 2006.257.03:59:14.42#ibcon#read 5, iclass 24, count 2 2006.257.03:59:14.42#ibcon#about to read 6, iclass 24, count 2 2006.257.03:59:14.42#ibcon#read 6, iclass 24, count 2 2006.257.03:59:14.42#ibcon#end of sib2, iclass 24, count 2 2006.257.03:59:14.42#ibcon#*after write, iclass 24, count 2 2006.257.03:59:14.42#ibcon#*before return 0, iclass 24, count 2 2006.257.03:59:14.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:14.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.03:59:14.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.03:59:14.42#ibcon#ireg 7 cls_cnt 0 2006.257.03:59:14.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:14.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:14.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:14.54#ibcon#enter wrdev, iclass 24, count 0 2006.257.03:59:14.54#ibcon#first serial, iclass 24, count 0 2006.257.03:59:14.54#ibcon#enter sib2, iclass 24, count 0 2006.257.03:59:14.54#ibcon#flushed, iclass 24, count 0 2006.257.03:59:14.54#ibcon#about to write, iclass 24, count 0 2006.257.03:59:14.54#ibcon#wrote, iclass 24, count 0 2006.257.03:59:14.54#ibcon#about to read 3, iclass 24, count 0 2006.257.03:59:14.56#ibcon#read 3, iclass 24, count 0 2006.257.03:59:14.56#ibcon#about to read 4, iclass 24, count 0 2006.257.03:59:14.56#ibcon#read 4, iclass 24, count 0 2006.257.03:59:14.56#ibcon#about to read 5, iclass 24, count 0 2006.257.03:59:14.56#ibcon#read 5, iclass 24, count 0 2006.257.03:59:14.56#ibcon#about to read 6, iclass 24, count 0 2006.257.03:59:14.56#ibcon#read 6, iclass 24, count 0 2006.257.03:59:14.56#ibcon#end of sib2, iclass 24, count 0 2006.257.03:59:14.56#ibcon#*mode == 0, iclass 24, count 0 2006.257.03:59:14.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.03:59:14.56#ibcon#[27=USB\r\n] 2006.257.03:59:14.56#ibcon#*before write, iclass 24, count 0 2006.257.03:59:14.56#ibcon#enter sib2, iclass 24, count 0 2006.257.03:59:14.56#ibcon#flushed, iclass 24, count 0 2006.257.03:59:14.56#ibcon#about to write, iclass 24, count 0 2006.257.03:59:14.56#ibcon#wrote, iclass 24, count 0 2006.257.03:59:14.56#ibcon#about to read 3, iclass 24, count 0 2006.257.03:59:14.59#ibcon#read 3, iclass 24, count 0 2006.257.03:59:14.59#ibcon#about to read 4, iclass 24, count 0 2006.257.03:59:14.59#ibcon#read 4, iclass 24, count 0 2006.257.03:59:14.59#ibcon#about to read 5, iclass 24, count 0 2006.257.03:59:14.59#ibcon#read 5, iclass 24, count 0 2006.257.03:59:14.59#ibcon#about to read 6, iclass 24, count 0 2006.257.03:59:14.59#ibcon#read 6, iclass 24, count 0 2006.257.03:59:14.59#ibcon#end of sib2, iclass 24, count 0 2006.257.03:59:14.59#ibcon#*after write, iclass 24, count 0 2006.257.03:59:14.59#ibcon#*before return 0, iclass 24, count 0 2006.257.03:59:14.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:14.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.03:59:14.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.03:59:14.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.03:59:14.59$vck44/vabw=wide 2006.257.03:59:14.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.03:59:14.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.03:59:14.59#ibcon#ireg 8 cls_cnt 0 2006.257.03:59:14.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:14.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:14.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:14.59#ibcon#enter wrdev, iclass 26, count 0 2006.257.03:59:14.59#ibcon#first serial, iclass 26, count 0 2006.257.03:59:14.59#ibcon#enter sib2, iclass 26, count 0 2006.257.03:59:14.59#ibcon#flushed, iclass 26, count 0 2006.257.03:59:14.59#ibcon#about to write, iclass 26, count 0 2006.257.03:59:14.59#ibcon#wrote, iclass 26, count 0 2006.257.03:59:14.59#ibcon#about to read 3, iclass 26, count 0 2006.257.03:59:14.61#ibcon#read 3, iclass 26, count 0 2006.257.03:59:14.61#ibcon#about to read 4, iclass 26, count 0 2006.257.03:59:14.61#ibcon#read 4, iclass 26, count 0 2006.257.03:59:14.61#ibcon#about to read 5, iclass 26, count 0 2006.257.03:59:14.61#ibcon#read 5, iclass 26, count 0 2006.257.03:59:14.61#ibcon#about to read 6, iclass 26, count 0 2006.257.03:59:14.61#ibcon#read 6, iclass 26, count 0 2006.257.03:59:14.61#ibcon#end of sib2, iclass 26, count 0 2006.257.03:59:14.61#ibcon#*mode == 0, iclass 26, count 0 2006.257.03:59:14.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.03:59:14.61#ibcon#[25=BW32\r\n] 2006.257.03:59:14.61#ibcon#*before write, iclass 26, count 0 2006.257.03:59:14.61#ibcon#enter sib2, iclass 26, count 0 2006.257.03:59:14.61#ibcon#flushed, iclass 26, count 0 2006.257.03:59:14.61#ibcon#about to write, iclass 26, count 0 2006.257.03:59:14.61#ibcon#wrote, iclass 26, count 0 2006.257.03:59:14.61#ibcon#about to read 3, iclass 26, count 0 2006.257.03:59:14.64#ibcon#read 3, iclass 26, count 0 2006.257.03:59:14.64#ibcon#about to read 4, iclass 26, count 0 2006.257.03:59:14.64#ibcon#read 4, iclass 26, count 0 2006.257.03:59:14.64#ibcon#about to read 5, iclass 26, count 0 2006.257.03:59:14.64#ibcon#read 5, iclass 26, count 0 2006.257.03:59:14.64#ibcon#about to read 6, iclass 26, count 0 2006.257.03:59:14.64#ibcon#read 6, iclass 26, count 0 2006.257.03:59:14.64#ibcon#end of sib2, iclass 26, count 0 2006.257.03:59:14.64#ibcon#*after write, iclass 26, count 0 2006.257.03:59:14.64#ibcon#*before return 0, iclass 26, count 0 2006.257.03:59:14.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:14.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.03:59:14.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.03:59:14.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.03:59:14.64$vck44/vbbw=wide 2006.257.03:59:14.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.03:59:14.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.03:59:14.64#ibcon#ireg 8 cls_cnt 0 2006.257.03:59:14.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:59:14.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:59:14.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:59:14.71#ibcon#enter wrdev, iclass 28, count 0 2006.257.03:59:14.71#ibcon#first serial, iclass 28, count 0 2006.257.03:59:14.71#ibcon#enter sib2, iclass 28, count 0 2006.257.03:59:14.71#ibcon#flushed, iclass 28, count 0 2006.257.03:59:14.71#ibcon#about to write, iclass 28, count 0 2006.257.03:59:14.71#ibcon#wrote, iclass 28, count 0 2006.257.03:59:14.71#ibcon#about to read 3, iclass 28, count 0 2006.257.03:59:14.73#ibcon#read 3, iclass 28, count 0 2006.257.03:59:14.73#ibcon#about to read 4, iclass 28, count 0 2006.257.03:59:14.73#ibcon#read 4, iclass 28, count 0 2006.257.03:59:14.73#ibcon#about to read 5, iclass 28, count 0 2006.257.03:59:14.73#ibcon#read 5, iclass 28, count 0 2006.257.03:59:14.73#ibcon#about to read 6, iclass 28, count 0 2006.257.03:59:14.73#ibcon#read 6, iclass 28, count 0 2006.257.03:59:14.73#ibcon#end of sib2, iclass 28, count 0 2006.257.03:59:14.73#ibcon#*mode == 0, iclass 28, count 0 2006.257.03:59:14.73#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.03:59:14.73#ibcon#[27=BW32\r\n] 2006.257.03:59:14.73#ibcon#*before write, iclass 28, count 0 2006.257.03:59:14.73#ibcon#enter sib2, iclass 28, count 0 2006.257.03:59:14.73#ibcon#flushed, iclass 28, count 0 2006.257.03:59:14.73#ibcon#about to write, iclass 28, count 0 2006.257.03:59:14.73#ibcon#wrote, iclass 28, count 0 2006.257.03:59:14.73#ibcon#about to read 3, iclass 28, count 0 2006.257.03:59:14.76#ibcon#read 3, iclass 28, count 0 2006.257.03:59:14.76#ibcon#about to read 4, iclass 28, count 0 2006.257.03:59:14.76#ibcon#read 4, iclass 28, count 0 2006.257.03:59:14.76#ibcon#about to read 5, iclass 28, count 0 2006.257.03:59:14.76#ibcon#read 5, iclass 28, count 0 2006.257.03:59:14.76#ibcon#about to read 6, iclass 28, count 0 2006.257.03:59:14.76#ibcon#read 6, iclass 28, count 0 2006.257.03:59:14.76#ibcon#end of sib2, iclass 28, count 0 2006.257.03:59:14.76#ibcon#*after write, iclass 28, count 0 2006.257.03:59:14.76#ibcon#*before return 0, iclass 28, count 0 2006.257.03:59:14.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:59:14.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.03:59:14.76#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.03:59:14.76#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.03:59:14.76$setupk4/ifdk4 2006.257.03:59:14.76$ifdk4/lo= 2006.257.03:59:14.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.03:59:14.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.03:59:14.76$ifdk4/patch= 2006.257.03:59:14.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.03:59:14.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.03:59:14.76$setupk4/!*+20s 2006.257.03:59:23.00#abcon#<5=/14 2.0 6.8 19.15 951012.0\r\n> 2006.257.03:59:23.02#abcon#{5=INTERFACE CLEAR} 2006.257.03:59:23.08#abcon#[5=S1D000X0/0*\r\n] 2006.257.03:59:29.27$setupk4/"tpicd 2006.257.03:59:29.27$setupk4/echo=off 2006.257.03:59:29.27$setupk4/xlog=off 2006.257.03:59:29.27:!2006.257.04:04:05 2006.257.03:59:32.14#trakl#Source acquired 2006.257.03:59:34.14#flagr#flagr/antenna,acquired 2006.257.04:04:05.00:preob 2006.257.04:04:05.14/onsource/TRACKING 2006.257.04:04:05.14:!2006.257.04:04:15 2006.257.04:04:15.00:"tape 2006.257.04:04:15.00:"st=record 2006.257.04:04:15.00:data_valid=on 2006.257.04:04:15.00:midob 2006.257.04:04:16.14/onsource/TRACKING 2006.257.04:04:16.14/wx/19.22,1011.8,95 2006.257.04:04:16.28/cable/+6.4852E-03 2006.257.04:04:17.37/va/01,08,usb,yes,33,36 2006.257.04:04:17.37/va/02,07,usb,yes,36,36 2006.257.04:04:17.37/va/03,08,usb,yes,32,34 2006.257.04:04:17.37/va/04,07,usb,yes,37,39 2006.257.04:04:17.37/va/05,04,usb,yes,33,33 2006.257.04:04:17.37/va/06,04,usb,yes,37,36 2006.257.04:04:17.37/va/07,04,usb,yes,38,38 2006.257.04:04:17.37/va/08,04,usb,yes,31,38 2006.257.04:04:17.60/valo/01,524.99,yes,locked 2006.257.04:04:17.60/valo/02,534.99,yes,locked 2006.257.04:04:17.60/valo/03,564.99,yes,locked 2006.257.04:04:17.60/valo/04,624.99,yes,locked 2006.257.04:04:17.60/valo/05,734.99,yes,locked 2006.257.04:04:17.60/valo/06,814.99,yes,locked 2006.257.04:04:17.60/valo/07,864.99,yes,locked 2006.257.04:04:17.60/valo/08,884.99,yes,locked 2006.257.04:04:18.69/vb/01,04,usb,yes,38,35 2006.257.04:04:18.69/vb/02,05,usb,yes,36,36 2006.257.04:04:18.69/vb/03,04,usb,yes,37,41 2006.257.04:04:18.69/vb/04,05,usb,yes,37,36 2006.257.04:04:18.69/vb/05,04,usb,yes,33,36 2006.257.04:04:18.69/vb/06,04,usb,yes,38,34 2006.257.04:04:18.69/vb/07,04,usb,yes,38,38 2006.257.04:04:18.69/vb/08,04,usb,yes,35,39 2006.257.04:04:18.93/vblo/01,629.99,yes,locked 2006.257.04:04:18.93/vblo/02,634.99,yes,locked 2006.257.04:04:18.93/vblo/03,649.99,yes,locked 2006.257.04:04:18.93/vblo/04,679.99,yes,locked 2006.257.04:04:18.93/vblo/05,709.99,yes,locked 2006.257.04:04:18.93/vblo/06,719.99,yes,locked 2006.257.04:04:18.93/vblo/07,734.99,yes,locked 2006.257.04:04:18.93/vblo/08,744.99,yes,locked 2006.257.04:04:19.08/vabw/8 2006.257.04:04:19.23/vbbw/8 2006.257.04:04:19.40/xfe/off,on,16.7 2006.257.04:04:19.77/ifatt/23,28,28,28 2006.257.04:04:20.08/fmout-gps/S +4.54E-07 2006.257.04:04:20.12:!2006.257.04:05:35 2006.257.04:05:35.00:data_valid=off 2006.257.04:05:35.00:"et 2006.257.04:05:35.00:!+3s 2006.257.04:05:38.01:"tape 2006.257.04:05:38.01:postob 2006.257.04:05:38.24/cable/+6.4868E-03 2006.257.04:05:38.24/wx/19.25,1011.9,95 2006.257.04:05:39.08/fmout-gps/S +4.56E-07 2006.257.04:05:39.08:scan_name=257-0409,jd0609,210 2006.257.04:05:39.08:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.257.04:05:40.14#flagr#flagr/antenna,new-source 2006.257.04:05:40.14:checkk5 2006.257.04:05:40.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.04:05:40.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.04:05:41.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.04:05:41.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.04:05:42.20/chk_obsdata//k5ts1/T2570404??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.04:05:42.67/chk_obsdata//k5ts2/T2570404??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.04:05:43.07/chk_obsdata//k5ts3/T2570404??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.04:05:43.48/chk_obsdata//k5ts4/T2570404??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.04:05:44.20/k5log//k5ts1_log_newline 2006.257.04:05:44.91/k5log//k5ts2_log_newline 2006.257.04:05:45.66/k5log//k5ts3_log_newline 2006.257.04:05:46.38/k5log//k5ts4_log_newline 2006.257.04:05:46.41/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.04:05:46.41:setupk4=1 2006.257.04:05:46.41$setupk4/echo=on 2006.257.04:05:46.41$setupk4/pcalon 2006.257.04:05:46.41$pcalon/"no phase cal control is implemented here 2006.257.04:05:46.41$setupk4/"tpicd=stop 2006.257.04:05:46.41$setupk4/"rec=synch_on 2006.257.04:05:46.41$setupk4/"rec_mode=128 2006.257.04:05:46.41$setupk4/!* 2006.257.04:05:46.41$setupk4/recpk4 2006.257.04:05:46.41$recpk4/recpatch= 2006.257.04:05:46.41$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.04:05:46.41$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.04:05:46.41$setupk4/vck44 2006.257.04:05:46.41$vck44/valo=1,524.99 2006.257.04:05:46.41#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.04:05:46.41#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.04:05:46.41#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:46.41#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:46.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:46.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:46.41#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:05:46.41#ibcon#first serial, iclass 3, count 0 2006.257.04:05:46.41#ibcon#enter sib2, iclass 3, count 0 2006.257.04:05:46.41#ibcon#flushed, iclass 3, count 0 2006.257.04:05:46.41#ibcon#about to write, iclass 3, count 0 2006.257.04:05:46.41#ibcon#wrote, iclass 3, count 0 2006.257.04:05:46.41#ibcon#about to read 3, iclass 3, count 0 2006.257.04:05:46.43#ibcon#read 3, iclass 3, count 0 2006.257.04:05:46.43#ibcon#about to read 4, iclass 3, count 0 2006.257.04:05:46.43#ibcon#read 4, iclass 3, count 0 2006.257.04:05:46.43#ibcon#about to read 5, iclass 3, count 0 2006.257.04:05:46.43#ibcon#read 5, iclass 3, count 0 2006.257.04:05:46.43#ibcon#about to read 6, iclass 3, count 0 2006.257.04:05:46.43#ibcon#read 6, iclass 3, count 0 2006.257.04:05:46.43#ibcon#end of sib2, iclass 3, count 0 2006.257.04:05:46.43#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:05:46.43#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:05:46.43#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.04:05:46.43#ibcon#*before write, iclass 3, count 0 2006.257.04:05:46.43#ibcon#enter sib2, iclass 3, count 0 2006.257.04:05:46.43#ibcon#flushed, iclass 3, count 0 2006.257.04:05:46.43#ibcon#about to write, iclass 3, count 0 2006.257.04:05:46.43#ibcon#wrote, iclass 3, count 0 2006.257.04:05:46.43#ibcon#about to read 3, iclass 3, count 0 2006.257.04:05:46.48#ibcon#read 3, iclass 3, count 0 2006.257.04:05:46.48#ibcon#about to read 4, iclass 3, count 0 2006.257.04:05:46.48#ibcon#read 4, iclass 3, count 0 2006.257.04:05:46.48#ibcon#about to read 5, iclass 3, count 0 2006.257.04:05:46.48#ibcon#read 5, iclass 3, count 0 2006.257.04:05:46.48#ibcon#about to read 6, iclass 3, count 0 2006.257.04:05:46.48#ibcon#read 6, iclass 3, count 0 2006.257.04:05:46.48#ibcon#end of sib2, iclass 3, count 0 2006.257.04:05:46.48#ibcon#*after write, iclass 3, count 0 2006.257.04:05:46.48#ibcon#*before return 0, iclass 3, count 0 2006.257.04:05:46.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:46.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:46.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:05:46.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:05:46.48$vck44/va=1,8 2006.257.04:05:46.48#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.04:05:46.48#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.04:05:46.48#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:46.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:46.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:46.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:46.48#ibcon#enter wrdev, iclass 5, count 2 2006.257.04:05:46.48#ibcon#first serial, iclass 5, count 2 2006.257.04:05:46.48#ibcon#enter sib2, iclass 5, count 2 2006.257.04:05:46.48#ibcon#flushed, iclass 5, count 2 2006.257.04:05:46.48#ibcon#about to write, iclass 5, count 2 2006.257.04:05:46.48#ibcon#wrote, iclass 5, count 2 2006.257.04:05:46.48#ibcon#about to read 3, iclass 5, count 2 2006.257.04:05:46.50#ibcon#read 3, iclass 5, count 2 2006.257.04:05:46.50#ibcon#about to read 4, iclass 5, count 2 2006.257.04:05:46.50#ibcon#read 4, iclass 5, count 2 2006.257.04:05:46.50#ibcon#about to read 5, iclass 5, count 2 2006.257.04:05:46.50#ibcon#read 5, iclass 5, count 2 2006.257.04:05:46.50#ibcon#about to read 6, iclass 5, count 2 2006.257.04:05:46.50#ibcon#read 6, iclass 5, count 2 2006.257.04:05:46.50#ibcon#end of sib2, iclass 5, count 2 2006.257.04:05:46.50#ibcon#*mode == 0, iclass 5, count 2 2006.257.04:05:46.50#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.04:05:46.50#ibcon#[25=AT01-08\r\n] 2006.257.04:05:46.50#ibcon#*before write, iclass 5, count 2 2006.257.04:05:46.50#ibcon#enter sib2, iclass 5, count 2 2006.257.04:05:46.50#ibcon#flushed, iclass 5, count 2 2006.257.04:05:46.50#ibcon#about to write, iclass 5, count 2 2006.257.04:05:46.50#ibcon#wrote, iclass 5, count 2 2006.257.04:05:46.50#ibcon#about to read 3, iclass 5, count 2 2006.257.04:05:46.53#ibcon#read 3, iclass 5, count 2 2006.257.04:05:46.53#ibcon#about to read 4, iclass 5, count 2 2006.257.04:05:46.53#ibcon#read 4, iclass 5, count 2 2006.257.04:05:46.53#ibcon#about to read 5, iclass 5, count 2 2006.257.04:05:46.53#ibcon#read 5, iclass 5, count 2 2006.257.04:05:46.53#ibcon#about to read 6, iclass 5, count 2 2006.257.04:05:46.53#ibcon#read 6, iclass 5, count 2 2006.257.04:05:46.53#ibcon#end of sib2, iclass 5, count 2 2006.257.04:05:46.53#ibcon#*after write, iclass 5, count 2 2006.257.04:05:46.53#ibcon#*before return 0, iclass 5, count 2 2006.257.04:05:46.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:46.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:46.53#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.04:05:46.53#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:46.53#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:46.65#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:46.65#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:46.65#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:05:46.65#ibcon#first serial, iclass 5, count 0 2006.257.04:05:46.65#ibcon#enter sib2, iclass 5, count 0 2006.257.04:05:46.65#ibcon#flushed, iclass 5, count 0 2006.257.04:05:46.65#ibcon#about to write, iclass 5, count 0 2006.257.04:05:46.65#ibcon#wrote, iclass 5, count 0 2006.257.04:05:46.65#ibcon#about to read 3, iclass 5, count 0 2006.257.04:05:46.67#ibcon#read 3, iclass 5, count 0 2006.257.04:05:46.67#ibcon#about to read 4, iclass 5, count 0 2006.257.04:05:46.67#ibcon#read 4, iclass 5, count 0 2006.257.04:05:46.67#ibcon#about to read 5, iclass 5, count 0 2006.257.04:05:46.67#ibcon#read 5, iclass 5, count 0 2006.257.04:05:46.67#ibcon#about to read 6, iclass 5, count 0 2006.257.04:05:46.67#ibcon#read 6, iclass 5, count 0 2006.257.04:05:46.67#ibcon#end of sib2, iclass 5, count 0 2006.257.04:05:46.67#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:05:46.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:05:46.67#ibcon#[25=USB\r\n] 2006.257.04:05:46.67#ibcon#*before write, iclass 5, count 0 2006.257.04:05:46.67#ibcon#enter sib2, iclass 5, count 0 2006.257.04:05:46.67#ibcon#flushed, iclass 5, count 0 2006.257.04:05:46.67#ibcon#about to write, iclass 5, count 0 2006.257.04:05:46.67#ibcon#wrote, iclass 5, count 0 2006.257.04:05:46.67#ibcon#about to read 3, iclass 5, count 0 2006.257.04:05:46.70#ibcon#read 3, iclass 5, count 0 2006.257.04:05:46.70#ibcon#about to read 4, iclass 5, count 0 2006.257.04:05:46.70#ibcon#read 4, iclass 5, count 0 2006.257.04:05:46.70#ibcon#about to read 5, iclass 5, count 0 2006.257.04:05:46.70#ibcon#read 5, iclass 5, count 0 2006.257.04:05:46.70#ibcon#about to read 6, iclass 5, count 0 2006.257.04:05:46.70#ibcon#read 6, iclass 5, count 0 2006.257.04:05:46.70#ibcon#end of sib2, iclass 5, count 0 2006.257.04:05:46.70#ibcon#*after write, iclass 5, count 0 2006.257.04:05:46.70#ibcon#*before return 0, iclass 5, count 0 2006.257.04:05:46.70#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:46.70#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:46.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:05:46.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:05:46.70$vck44/valo=2,534.99 2006.257.04:05:46.70#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.04:05:46.70#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.04:05:46.70#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:46.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:05:46.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:05:46.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:05:46.70#ibcon#enter wrdev, iclass 7, count 0 2006.257.04:05:46.70#ibcon#first serial, iclass 7, count 0 2006.257.04:05:46.70#ibcon#enter sib2, iclass 7, count 0 2006.257.04:05:46.70#ibcon#flushed, iclass 7, count 0 2006.257.04:05:46.70#ibcon#about to write, iclass 7, count 0 2006.257.04:05:46.70#ibcon#wrote, iclass 7, count 0 2006.257.04:05:46.70#ibcon#about to read 3, iclass 7, count 0 2006.257.04:05:46.72#ibcon#read 3, iclass 7, count 0 2006.257.04:05:46.72#ibcon#about to read 4, iclass 7, count 0 2006.257.04:05:46.72#ibcon#read 4, iclass 7, count 0 2006.257.04:05:46.72#ibcon#about to read 5, iclass 7, count 0 2006.257.04:05:46.72#ibcon#read 5, iclass 7, count 0 2006.257.04:05:46.72#ibcon#about to read 6, iclass 7, count 0 2006.257.04:05:46.72#ibcon#read 6, iclass 7, count 0 2006.257.04:05:46.72#ibcon#end of sib2, iclass 7, count 0 2006.257.04:05:46.72#ibcon#*mode == 0, iclass 7, count 0 2006.257.04:05:46.72#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.04:05:46.72#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.04:05:46.72#ibcon#*before write, iclass 7, count 0 2006.257.04:05:46.72#ibcon#enter sib2, iclass 7, count 0 2006.257.04:05:46.72#ibcon#flushed, iclass 7, count 0 2006.257.04:05:46.72#ibcon#about to write, iclass 7, count 0 2006.257.04:05:46.72#ibcon#wrote, iclass 7, count 0 2006.257.04:05:46.72#ibcon#about to read 3, iclass 7, count 0 2006.257.04:05:46.76#ibcon#read 3, iclass 7, count 0 2006.257.04:05:46.76#ibcon#about to read 4, iclass 7, count 0 2006.257.04:05:46.76#ibcon#read 4, iclass 7, count 0 2006.257.04:05:46.76#ibcon#about to read 5, iclass 7, count 0 2006.257.04:05:46.76#ibcon#read 5, iclass 7, count 0 2006.257.04:05:46.76#ibcon#about to read 6, iclass 7, count 0 2006.257.04:05:46.76#ibcon#read 6, iclass 7, count 0 2006.257.04:05:46.76#ibcon#end of sib2, iclass 7, count 0 2006.257.04:05:46.76#ibcon#*after write, iclass 7, count 0 2006.257.04:05:46.76#ibcon#*before return 0, iclass 7, count 0 2006.257.04:05:46.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:05:46.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:05:46.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.04:05:46.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.04:05:46.76$vck44/va=2,7 2006.257.04:05:46.76#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.04:05:46.76#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.04:05:46.76#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:46.76#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:05:46.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:05:46.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:05:46.82#ibcon#enter wrdev, iclass 11, count 2 2006.257.04:05:46.82#ibcon#first serial, iclass 11, count 2 2006.257.04:05:46.82#ibcon#enter sib2, iclass 11, count 2 2006.257.04:05:46.82#ibcon#flushed, iclass 11, count 2 2006.257.04:05:46.82#ibcon#about to write, iclass 11, count 2 2006.257.04:05:46.82#ibcon#wrote, iclass 11, count 2 2006.257.04:05:46.82#ibcon#about to read 3, iclass 11, count 2 2006.257.04:05:46.84#ibcon#read 3, iclass 11, count 2 2006.257.04:05:46.84#ibcon#about to read 4, iclass 11, count 2 2006.257.04:05:46.84#ibcon#read 4, iclass 11, count 2 2006.257.04:05:46.84#ibcon#about to read 5, iclass 11, count 2 2006.257.04:05:46.84#ibcon#read 5, iclass 11, count 2 2006.257.04:05:46.84#ibcon#about to read 6, iclass 11, count 2 2006.257.04:05:46.84#ibcon#read 6, iclass 11, count 2 2006.257.04:05:46.84#ibcon#end of sib2, iclass 11, count 2 2006.257.04:05:46.84#ibcon#*mode == 0, iclass 11, count 2 2006.257.04:05:46.84#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.04:05:46.84#ibcon#[25=AT02-07\r\n] 2006.257.04:05:46.84#ibcon#*before write, iclass 11, count 2 2006.257.04:05:46.84#ibcon#enter sib2, iclass 11, count 2 2006.257.04:05:46.84#ibcon#flushed, iclass 11, count 2 2006.257.04:05:46.84#ibcon#about to write, iclass 11, count 2 2006.257.04:05:46.84#ibcon#wrote, iclass 11, count 2 2006.257.04:05:46.84#ibcon#about to read 3, iclass 11, count 2 2006.257.04:05:46.87#ibcon#read 3, iclass 11, count 2 2006.257.04:05:46.87#ibcon#about to read 4, iclass 11, count 2 2006.257.04:05:46.87#ibcon#read 4, iclass 11, count 2 2006.257.04:05:46.87#ibcon#about to read 5, iclass 11, count 2 2006.257.04:05:46.87#ibcon#read 5, iclass 11, count 2 2006.257.04:05:46.87#ibcon#about to read 6, iclass 11, count 2 2006.257.04:05:46.87#ibcon#read 6, iclass 11, count 2 2006.257.04:05:46.87#ibcon#end of sib2, iclass 11, count 2 2006.257.04:05:46.87#ibcon#*after write, iclass 11, count 2 2006.257.04:05:46.87#ibcon#*before return 0, iclass 11, count 2 2006.257.04:05:46.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:05:46.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:05:46.87#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.04:05:46.87#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:46.87#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:05:46.99#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:05:46.99#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:05:46.99#ibcon#enter wrdev, iclass 11, count 0 2006.257.04:05:46.99#ibcon#first serial, iclass 11, count 0 2006.257.04:05:46.99#ibcon#enter sib2, iclass 11, count 0 2006.257.04:05:46.99#ibcon#flushed, iclass 11, count 0 2006.257.04:05:46.99#ibcon#about to write, iclass 11, count 0 2006.257.04:05:46.99#ibcon#wrote, iclass 11, count 0 2006.257.04:05:46.99#ibcon#about to read 3, iclass 11, count 0 2006.257.04:05:47.01#ibcon#read 3, iclass 11, count 0 2006.257.04:05:47.01#ibcon#about to read 4, iclass 11, count 0 2006.257.04:05:47.01#ibcon#read 4, iclass 11, count 0 2006.257.04:05:47.01#ibcon#about to read 5, iclass 11, count 0 2006.257.04:05:47.01#ibcon#read 5, iclass 11, count 0 2006.257.04:05:47.01#ibcon#about to read 6, iclass 11, count 0 2006.257.04:05:47.01#ibcon#read 6, iclass 11, count 0 2006.257.04:05:47.01#ibcon#end of sib2, iclass 11, count 0 2006.257.04:05:47.01#ibcon#*mode == 0, iclass 11, count 0 2006.257.04:05:47.01#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.04:05:47.01#ibcon#[25=USB\r\n] 2006.257.04:05:47.01#ibcon#*before write, iclass 11, count 0 2006.257.04:05:47.01#ibcon#enter sib2, iclass 11, count 0 2006.257.04:05:47.01#ibcon#flushed, iclass 11, count 0 2006.257.04:05:47.01#ibcon#about to write, iclass 11, count 0 2006.257.04:05:47.01#ibcon#wrote, iclass 11, count 0 2006.257.04:05:47.01#ibcon#about to read 3, iclass 11, count 0 2006.257.04:05:47.04#ibcon#read 3, iclass 11, count 0 2006.257.04:05:47.04#ibcon#about to read 4, iclass 11, count 0 2006.257.04:05:47.04#ibcon#read 4, iclass 11, count 0 2006.257.04:05:47.04#ibcon#about to read 5, iclass 11, count 0 2006.257.04:05:47.04#ibcon#read 5, iclass 11, count 0 2006.257.04:05:47.04#ibcon#about to read 6, iclass 11, count 0 2006.257.04:05:47.04#ibcon#read 6, iclass 11, count 0 2006.257.04:05:47.04#ibcon#end of sib2, iclass 11, count 0 2006.257.04:05:47.04#ibcon#*after write, iclass 11, count 0 2006.257.04:05:47.04#ibcon#*before return 0, iclass 11, count 0 2006.257.04:05:47.04#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:05:47.04#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:05:47.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.04:05:47.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.04:05:47.04$vck44/valo=3,564.99 2006.257.04:05:47.04#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.04:05:47.04#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.04:05:47.04#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:47.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:47.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:47.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:47.04#ibcon#enter wrdev, iclass 13, count 0 2006.257.04:05:47.04#ibcon#first serial, iclass 13, count 0 2006.257.04:05:47.04#ibcon#enter sib2, iclass 13, count 0 2006.257.04:05:47.04#ibcon#flushed, iclass 13, count 0 2006.257.04:05:47.04#ibcon#about to write, iclass 13, count 0 2006.257.04:05:47.04#ibcon#wrote, iclass 13, count 0 2006.257.04:05:47.04#ibcon#about to read 3, iclass 13, count 0 2006.257.04:05:47.06#ibcon#read 3, iclass 13, count 0 2006.257.04:05:47.06#ibcon#about to read 4, iclass 13, count 0 2006.257.04:05:47.06#ibcon#read 4, iclass 13, count 0 2006.257.04:05:47.06#ibcon#about to read 5, iclass 13, count 0 2006.257.04:05:47.06#ibcon#read 5, iclass 13, count 0 2006.257.04:05:47.06#ibcon#about to read 6, iclass 13, count 0 2006.257.04:05:47.06#ibcon#read 6, iclass 13, count 0 2006.257.04:05:47.06#ibcon#end of sib2, iclass 13, count 0 2006.257.04:05:47.06#ibcon#*mode == 0, iclass 13, count 0 2006.257.04:05:47.06#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.04:05:47.06#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.04:05:47.06#ibcon#*before write, iclass 13, count 0 2006.257.04:05:47.06#ibcon#enter sib2, iclass 13, count 0 2006.257.04:05:47.06#ibcon#flushed, iclass 13, count 0 2006.257.04:05:47.06#ibcon#about to write, iclass 13, count 0 2006.257.04:05:47.06#ibcon#wrote, iclass 13, count 0 2006.257.04:05:47.06#ibcon#about to read 3, iclass 13, count 0 2006.257.04:05:47.10#ibcon#read 3, iclass 13, count 0 2006.257.04:05:47.10#ibcon#about to read 4, iclass 13, count 0 2006.257.04:05:47.10#ibcon#read 4, iclass 13, count 0 2006.257.04:05:47.10#ibcon#about to read 5, iclass 13, count 0 2006.257.04:05:47.10#ibcon#read 5, iclass 13, count 0 2006.257.04:05:47.10#ibcon#about to read 6, iclass 13, count 0 2006.257.04:05:47.10#ibcon#read 6, iclass 13, count 0 2006.257.04:05:47.10#ibcon#end of sib2, iclass 13, count 0 2006.257.04:05:47.10#ibcon#*after write, iclass 13, count 0 2006.257.04:05:47.10#ibcon#*before return 0, iclass 13, count 0 2006.257.04:05:47.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:47.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:47.10#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.04:05:47.10#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.04:05:47.10$vck44/va=3,8 2006.257.04:05:47.10#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.04:05:47.10#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.04:05:47.10#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:47.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:47.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:47.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:47.16#ibcon#enter wrdev, iclass 15, count 2 2006.257.04:05:47.16#ibcon#first serial, iclass 15, count 2 2006.257.04:05:47.16#ibcon#enter sib2, iclass 15, count 2 2006.257.04:05:47.16#ibcon#flushed, iclass 15, count 2 2006.257.04:05:47.16#ibcon#about to write, iclass 15, count 2 2006.257.04:05:47.16#ibcon#wrote, iclass 15, count 2 2006.257.04:05:47.16#ibcon#about to read 3, iclass 15, count 2 2006.257.04:05:47.18#ibcon#read 3, iclass 15, count 2 2006.257.04:05:47.18#ibcon#about to read 4, iclass 15, count 2 2006.257.04:05:47.18#ibcon#read 4, iclass 15, count 2 2006.257.04:05:47.18#ibcon#about to read 5, iclass 15, count 2 2006.257.04:05:47.18#ibcon#read 5, iclass 15, count 2 2006.257.04:05:47.18#ibcon#about to read 6, iclass 15, count 2 2006.257.04:05:47.18#ibcon#read 6, iclass 15, count 2 2006.257.04:05:47.18#ibcon#end of sib2, iclass 15, count 2 2006.257.04:05:47.18#ibcon#*mode == 0, iclass 15, count 2 2006.257.04:05:47.18#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.04:05:47.18#ibcon#[25=AT03-08\r\n] 2006.257.04:05:47.18#ibcon#*before write, iclass 15, count 2 2006.257.04:05:47.18#ibcon#enter sib2, iclass 15, count 2 2006.257.04:05:47.18#ibcon#flushed, iclass 15, count 2 2006.257.04:05:47.18#ibcon#about to write, iclass 15, count 2 2006.257.04:05:47.18#ibcon#wrote, iclass 15, count 2 2006.257.04:05:47.18#ibcon#about to read 3, iclass 15, count 2 2006.257.04:05:47.21#ibcon#read 3, iclass 15, count 2 2006.257.04:05:47.21#ibcon#about to read 4, iclass 15, count 2 2006.257.04:05:47.21#ibcon#read 4, iclass 15, count 2 2006.257.04:05:47.21#ibcon#about to read 5, iclass 15, count 2 2006.257.04:05:47.21#ibcon#read 5, iclass 15, count 2 2006.257.04:05:47.21#ibcon#about to read 6, iclass 15, count 2 2006.257.04:05:47.21#ibcon#read 6, iclass 15, count 2 2006.257.04:05:47.21#ibcon#end of sib2, iclass 15, count 2 2006.257.04:05:47.21#ibcon#*after write, iclass 15, count 2 2006.257.04:05:47.21#ibcon#*before return 0, iclass 15, count 2 2006.257.04:05:47.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:47.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:47.21#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.04:05:47.21#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:47.21#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:47.33#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:47.33#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:47.33#ibcon#enter wrdev, iclass 15, count 0 2006.257.04:05:47.33#ibcon#first serial, iclass 15, count 0 2006.257.04:05:47.33#ibcon#enter sib2, iclass 15, count 0 2006.257.04:05:47.33#ibcon#flushed, iclass 15, count 0 2006.257.04:05:47.33#ibcon#about to write, iclass 15, count 0 2006.257.04:05:47.33#ibcon#wrote, iclass 15, count 0 2006.257.04:05:47.33#ibcon#about to read 3, iclass 15, count 0 2006.257.04:05:47.35#ibcon#read 3, iclass 15, count 0 2006.257.04:05:47.35#ibcon#about to read 4, iclass 15, count 0 2006.257.04:05:47.35#ibcon#read 4, iclass 15, count 0 2006.257.04:05:47.35#ibcon#about to read 5, iclass 15, count 0 2006.257.04:05:47.35#ibcon#read 5, iclass 15, count 0 2006.257.04:05:47.35#ibcon#about to read 6, iclass 15, count 0 2006.257.04:05:47.35#ibcon#read 6, iclass 15, count 0 2006.257.04:05:47.35#ibcon#end of sib2, iclass 15, count 0 2006.257.04:05:47.35#ibcon#*mode == 0, iclass 15, count 0 2006.257.04:05:47.35#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.04:05:47.35#ibcon#[25=USB\r\n] 2006.257.04:05:47.35#ibcon#*before write, iclass 15, count 0 2006.257.04:05:47.35#ibcon#enter sib2, iclass 15, count 0 2006.257.04:05:47.35#ibcon#flushed, iclass 15, count 0 2006.257.04:05:47.35#ibcon#about to write, iclass 15, count 0 2006.257.04:05:47.35#ibcon#wrote, iclass 15, count 0 2006.257.04:05:47.35#ibcon#about to read 3, iclass 15, count 0 2006.257.04:05:47.38#ibcon#read 3, iclass 15, count 0 2006.257.04:05:47.38#ibcon#about to read 4, iclass 15, count 0 2006.257.04:05:47.38#ibcon#read 4, iclass 15, count 0 2006.257.04:05:47.38#ibcon#about to read 5, iclass 15, count 0 2006.257.04:05:47.38#ibcon#read 5, iclass 15, count 0 2006.257.04:05:47.38#ibcon#about to read 6, iclass 15, count 0 2006.257.04:05:47.38#ibcon#read 6, iclass 15, count 0 2006.257.04:05:47.38#ibcon#end of sib2, iclass 15, count 0 2006.257.04:05:47.38#ibcon#*after write, iclass 15, count 0 2006.257.04:05:47.38#ibcon#*before return 0, iclass 15, count 0 2006.257.04:05:47.38#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:47.38#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:47.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.04:05:47.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.04:05:47.38$vck44/valo=4,624.99 2006.257.04:05:47.38#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.04:05:47.38#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.04:05:47.38#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:47.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:47.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:47.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:47.38#ibcon#enter wrdev, iclass 17, count 0 2006.257.04:05:47.38#ibcon#first serial, iclass 17, count 0 2006.257.04:05:47.38#ibcon#enter sib2, iclass 17, count 0 2006.257.04:05:47.38#ibcon#flushed, iclass 17, count 0 2006.257.04:05:47.38#ibcon#about to write, iclass 17, count 0 2006.257.04:05:47.38#ibcon#wrote, iclass 17, count 0 2006.257.04:05:47.38#ibcon#about to read 3, iclass 17, count 0 2006.257.04:05:47.40#ibcon#read 3, iclass 17, count 0 2006.257.04:05:47.40#ibcon#about to read 4, iclass 17, count 0 2006.257.04:05:47.40#ibcon#read 4, iclass 17, count 0 2006.257.04:05:47.40#ibcon#about to read 5, iclass 17, count 0 2006.257.04:05:47.40#ibcon#read 5, iclass 17, count 0 2006.257.04:05:47.40#ibcon#about to read 6, iclass 17, count 0 2006.257.04:05:47.40#ibcon#read 6, iclass 17, count 0 2006.257.04:05:47.40#ibcon#end of sib2, iclass 17, count 0 2006.257.04:05:47.40#ibcon#*mode == 0, iclass 17, count 0 2006.257.04:05:47.40#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.04:05:47.40#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.04:05:47.40#ibcon#*before write, iclass 17, count 0 2006.257.04:05:47.40#ibcon#enter sib2, iclass 17, count 0 2006.257.04:05:47.40#ibcon#flushed, iclass 17, count 0 2006.257.04:05:47.40#ibcon#about to write, iclass 17, count 0 2006.257.04:05:47.40#ibcon#wrote, iclass 17, count 0 2006.257.04:05:47.40#ibcon#about to read 3, iclass 17, count 0 2006.257.04:05:47.44#ibcon#read 3, iclass 17, count 0 2006.257.04:05:47.44#ibcon#about to read 4, iclass 17, count 0 2006.257.04:05:47.44#ibcon#read 4, iclass 17, count 0 2006.257.04:05:47.44#ibcon#about to read 5, iclass 17, count 0 2006.257.04:05:47.44#ibcon#read 5, iclass 17, count 0 2006.257.04:05:47.44#ibcon#about to read 6, iclass 17, count 0 2006.257.04:05:47.44#ibcon#read 6, iclass 17, count 0 2006.257.04:05:47.44#ibcon#end of sib2, iclass 17, count 0 2006.257.04:05:47.44#ibcon#*after write, iclass 17, count 0 2006.257.04:05:47.44#ibcon#*before return 0, iclass 17, count 0 2006.257.04:05:47.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:47.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:47.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.04:05:47.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.04:05:47.44$vck44/va=4,7 2006.257.04:05:47.44#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.04:05:47.44#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.04:05:47.44#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:47.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:47.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:47.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:47.50#ibcon#enter wrdev, iclass 19, count 2 2006.257.04:05:47.50#ibcon#first serial, iclass 19, count 2 2006.257.04:05:47.50#ibcon#enter sib2, iclass 19, count 2 2006.257.04:05:47.50#ibcon#flushed, iclass 19, count 2 2006.257.04:05:47.50#ibcon#about to write, iclass 19, count 2 2006.257.04:05:47.50#ibcon#wrote, iclass 19, count 2 2006.257.04:05:47.50#ibcon#about to read 3, iclass 19, count 2 2006.257.04:05:47.52#ibcon#read 3, iclass 19, count 2 2006.257.04:05:47.52#ibcon#about to read 4, iclass 19, count 2 2006.257.04:05:47.52#ibcon#read 4, iclass 19, count 2 2006.257.04:05:47.52#ibcon#about to read 5, iclass 19, count 2 2006.257.04:05:47.52#ibcon#read 5, iclass 19, count 2 2006.257.04:05:47.52#ibcon#about to read 6, iclass 19, count 2 2006.257.04:05:47.52#ibcon#read 6, iclass 19, count 2 2006.257.04:05:47.52#ibcon#end of sib2, iclass 19, count 2 2006.257.04:05:47.52#ibcon#*mode == 0, iclass 19, count 2 2006.257.04:05:47.52#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.04:05:47.52#ibcon#[25=AT04-07\r\n] 2006.257.04:05:47.52#ibcon#*before write, iclass 19, count 2 2006.257.04:05:47.52#ibcon#enter sib2, iclass 19, count 2 2006.257.04:05:47.52#ibcon#flushed, iclass 19, count 2 2006.257.04:05:47.52#ibcon#about to write, iclass 19, count 2 2006.257.04:05:47.52#ibcon#wrote, iclass 19, count 2 2006.257.04:05:47.52#ibcon#about to read 3, iclass 19, count 2 2006.257.04:05:47.55#ibcon#read 3, iclass 19, count 2 2006.257.04:05:47.55#ibcon#about to read 4, iclass 19, count 2 2006.257.04:05:47.55#ibcon#read 4, iclass 19, count 2 2006.257.04:05:47.55#ibcon#about to read 5, iclass 19, count 2 2006.257.04:05:47.55#ibcon#read 5, iclass 19, count 2 2006.257.04:05:47.55#ibcon#about to read 6, iclass 19, count 2 2006.257.04:05:47.55#ibcon#read 6, iclass 19, count 2 2006.257.04:05:47.55#ibcon#end of sib2, iclass 19, count 2 2006.257.04:05:47.55#ibcon#*after write, iclass 19, count 2 2006.257.04:05:47.55#ibcon#*before return 0, iclass 19, count 2 2006.257.04:05:47.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:47.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:47.55#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.04:05:47.55#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:47.55#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:47.67#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:47.67#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:47.67#ibcon#enter wrdev, iclass 19, count 0 2006.257.04:05:47.67#ibcon#first serial, iclass 19, count 0 2006.257.04:05:47.67#ibcon#enter sib2, iclass 19, count 0 2006.257.04:05:47.67#ibcon#flushed, iclass 19, count 0 2006.257.04:05:47.67#ibcon#about to write, iclass 19, count 0 2006.257.04:05:47.67#ibcon#wrote, iclass 19, count 0 2006.257.04:05:47.67#ibcon#about to read 3, iclass 19, count 0 2006.257.04:05:47.69#ibcon#read 3, iclass 19, count 0 2006.257.04:05:47.69#ibcon#about to read 4, iclass 19, count 0 2006.257.04:05:47.69#ibcon#read 4, iclass 19, count 0 2006.257.04:05:47.69#ibcon#about to read 5, iclass 19, count 0 2006.257.04:05:47.69#ibcon#read 5, iclass 19, count 0 2006.257.04:05:47.69#ibcon#about to read 6, iclass 19, count 0 2006.257.04:05:47.69#ibcon#read 6, iclass 19, count 0 2006.257.04:05:47.69#ibcon#end of sib2, iclass 19, count 0 2006.257.04:05:47.69#ibcon#*mode == 0, iclass 19, count 0 2006.257.04:05:47.69#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.04:05:47.69#ibcon#[25=USB\r\n] 2006.257.04:05:47.69#ibcon#*before write, iclass 19, count 0 2006.257.04:05:47.69#ibcon#enter sib2, iclass 19, count 0 2006.257.04:05:47.69#ibcon#flushed, iclass 19, count 0 2006.257.04:05:47.69#ibcon#about to write, iclass 19, count 0 2006.257.04:05:47.69#ibcon#wrote, iclass 19, count 0 2006.257.04:05:47.69#ibcon#about to read 3, iclass 19, count 0 2006.257.04:05:47.72#ibcon#read 3, iclass 19, count 0 2006.257.04:05:47.72#ibcon#about to read 4, iclass 19, count 0 2006.257.04:05:47.72#ibcon#read 4, iclass 19, count 0 2006.257.04:05:47.72#ibcon#about to read 5, iclass 19, count 0 2006.257.04:05:47.72#ibcon#read 5, iclass 19, count 0 2006.257.04:05:47.72#ibcon#about to read 6, iclass 19, count 0 2006.257.04:05:47.72#ibcon#read 6, iclass 19, count 0 2006.257.04:05:47.72#ibcon#end of sib2, iclass 19, count 0 2006.257.04:05:47.72#ibcon#*after write, iclass 19, count 0 2006.257.04:05:47.72#ibcon#*before return 0, iclass 19, count 0 2006.257.04:05:47.72#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:47.72#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:47.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.04:05:47.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.04:05:47.72$vck44/valo=5,734.99 2006.257.04:05:47.72#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.04:05:47.72#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.04:05:47.72#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:47.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:47.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:47.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:47.72#ibcon#enter wrdev, iclass 21, count 0 2006.257.04:05:47.72#ibcon#first serial, iclass 21, count 0 2006.257.04:05:47.72#ibcon#enter sib2, iclass 21, count 0 2006.257.04:05:47.72#ibcon#flushed, iclass 21, count 0 2006.257.04:05:47.72#ibcon#about to write, iclass 21, count 0 2006.257.04:05:47.72#ibcon#wrote, iclass 21, count 0 2006.257.04:05:47.72#ibcon#about to read 3, iclass 21, count 0 2006.257.04:05:47.74#ibcon#read 3, iclass 21, count 0 2006.257.04:05:47.74#ibcon#about to read 4, iclass 21, count 0 2006.257.04:05:47.74#ibcon#read 4, iclass 21, count 0 2006.257.04:05:47.74#ibcon#about to read 5, iclass 21, count 0 2006.257.04:05:47.74#ibcon#read 5, iclass 21, count 0 2006.257.04:05:47.74#ibcon#about to read 6, iclass 21, count 0 2006.257.04:05:47.74#ibcon#read 6, iclass 21, count 0 2006.257.04:05:47.74#ibcon#end of sib2, iclass 21, count 0 2006.257.04:05:47.74#ibcon#*mode == 0, iclass 21, count 0 2006.257.04:05:47.74#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.04:05:47.74#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.04:05:47.74#ibcon#*before write, iclass 21, count 0 2006.257.04:05:47.74#ibcon#enter sib2, iclass 21, count 0 2006.257.04:05:47.74#ibcon#flushed, iclass 21, count 0 2006.257.04:05:47.74#ibcon#about to write, iclass 21, count 0 2006.257.04:05:47.74#ibcon#wrote, iclass 21, count 0 2006.257.04:05:47.74#ibcon#about to read 3, iclass 21, count 0 2006.257.04:05:47.78#ibcon#read 3, iclass 21, count 0 2006.257.04:05:47.78#ibcon#about to read 4, iclass 21, count 0 2006.257.04:05:47.78#ibcon#read 4, iclass 21, count 0 2006.257.04:05:47.78#ibcon#about to read 5, iclass 21, count 0 2006.257.04:05:47.78#ibcon#read 5, iclass 21, count 0 2006.257.04:05:47.78#ibcon#about to read 6, iclass 21, count 0 2006.257.04:05:47.78#ibcon#read 6, iclass 21, count 0 2006.257.04:05:47.78#ibcon#end of sib2, iclass 21, count 0 2006.257.04:05:47.78#ibcon#*after write, iclass 21, count 0 2006.257.04:05:47.78#ibcon#*before return 0, iclass 21, count 0 2006.257.04:05:47.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:47.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:47.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.04:05:47.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.04:05:47.78$vck44/va=5,4 2006.257.04:05:47.78#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.04:05:47.78#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.04:05:47.78#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:47.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:47.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:47.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:47.84#ibcon#enter wrdev, iclass 23, count 2 2006.257.04:05:47.84#ibcon#first serial, iclass 23, count 2 2006.257.04:05:47.84#ibcon#enter sib2, iclass 23, count 2 2006.257.04:05:47.84#ibcon#flushed, iclass 23, count 2 2006.257.04:05:47.84#ibcon#about to write, iclass 23, count 2 2006.257.04:05:47.84#ibcon#wrote, iclass 23, count 2 2006.257.04:05:47.84#ibcon#about to read 3, iclass 23, count 2 2006.257.04:05:47.86#ibcon#read 3, iclass 23, count 2 2006.257.04:05:47.86#ibcon#about to read 4, iclass 23, count 2 2006.257.04:05:47.86#ibcon#read 4, iclass 23, count 2 2006.257.04:05:47.86#ibcon#about to read 5, iclass 23, count 2 2006.257.04:05:47.86#ibcon#read 5, iclass 23, count 2 2006.257.04:05:47.86#ibcon#about to read 6, iclass 23, count 2 2006.257.04:05:47.86#ibcon#read 6, iclass 23, count 2 2006.257.04:05:47.86#ibcon#end of sib2, iclass 23, count 2 2006.257.04:05:47.86#ibcon#*mode == 0, iclass 23, count 2 2006.257.04:05:47.86#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.04:05:47.86#ibcon#[25=AT05-04\r\n] 2006.257.04:05:47.86#ibcon#*before write, iclass 23, count 2 2006.257.04:05:47.86#ibcon#enter sib2, iclass 23, count 2 2006.257.04:05:47.86#ibcon#flushed, iclass 23, count 2 2006.257.04:05:47.86#ibcon#about to write, iclass 23, count 2 2006.257.04:05:47.86#ibcon#wrote, iclass 23, count 2 2006.257.04:05:47.86#ibcon#about to read 3, iclass 23, count 2 2006.257.04:05:47.89#ibcon#read 3, iclass 23, count 2 2006.257.04:05:47.89#ibcon#about to read 4, iclass 23, count 2 2006.257.04:05:47.89#ibcon#read 4, iclass 23, count 2 2006.257.04:05:47.89#ibcon#about to read 5, iclass 23, count 2 2006.257.04:05:47.89#ibcon#read 5, iclass 23, count 2 2006.257.04:05:47.89#ibcon#about to read 6, iclass 23, count 2 2006.257.04:05:47.89#ibcon#read 6, iclass 23, count 2 2006.257.04:05:47.89#ibcon#end of sib2, iclass 23, count 2 2006.257.04:05:47.89#ibcon#*after write, iclass 23, count 2 2006.257.04:05:47.89#ibcon#*before return 0, iclass 23, count 2 2006.257.04:05:47.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:47.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:47.89#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.04:05:47.89#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:47.89#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:48.01#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:48.01#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:48.01#ibcon#enter wrdev, iclass 23, count 0 2006.257.04:05:48.01#ibcon#first serial, iclass 23, count 0 2006.257.04:05:48.01#ibcon#enter sib2, iclass 23, count 0 2006.257.04:05:48.01#ibcon#flushed, iclass 23, count 0 2006.257.04:05:48.01#ibcon#about to write, iclass 23, count 0 2006.257.04:05:48.01#ibcon#wrote, iclass 23, count 0 2006.257.04:05:48.01#ibcon#about to read 3, iclass 23, count 0 2006.257.04:05:48.03#ibcon#read 3, iclass 23, count 0 2006.257.04:05:48.03#ibcon#about to read 4, iclass 23, count 0 2006.257.04:05:48.03#ibcon#read 4, iclass 23, count 0 2006.257.04:05:48.03#ibcon#about to read 5, iclass 23, count 0 2006.257.04:05:48.03#ibcon#read 5, iclass 23, count 0 2006.257.04:05:48.03#ibcon#about to read 6, iclass 23, count 0 2006.257.04:05:48.03#ibcon#read 6, iclass 23, count 0 2006.257.04:05:48.03#ibcon#end of sib2, iclass 23, count 0 2006.257.04:05:48.03#ibcon#*mode == 0, iclass 23, count 0 2006.257.04:05:48.03#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.04:05:48.03#ibcon#[25=USB\r\n] 2006.257.04:05:48.03#ibcon#*before write, iclass 23, count 0 2006.257.04:05:48.03#ibcon#enter sib2, iclass 23, count 0 2006.257.04:05:48.03#ibcon#flushed, iclass 23, count 0 2006.257.04:05:48.03#ibcon#about to write, iclass 23, count 0 2006.257.04:05:48.03#ibcon#wrote, iclass 23, count 0 2006.257.04:05:48.03#ibcon#about to read 3, iclass 23, count 0 2006.257.04:05:48.06#ibcon#read 3, iclass 23, count 0 2006.257.04:05:48.06#ibcon#about to read 4, iclass 23, count 0 2006.257.04:05:48.06#ibcon#read 4, iclass 23, count 0 2006.257.04:05:48.06#ibcon#about to read 5, iclass 23, count 0 2006.257.04:05:48.06#ibcon#read 5, iclass 23, count 0 2006.257.04:05:48.06#ibcon#about to read 6, iclass 23, count 0 2006.257.04:05:48.06#ibcon#read 6, iclass 23, count 0 2006.257.04:05:48.06#ibcon#end of sib2, iclass 23, count 0 2006.257.04:05:48.06#ibcon#*after write, iclass 23, count 0 2006.257.04:05:48.06#ibcon#*before return 0, iclass 23, count 0 2006.257.04:05:48.06#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:48.06#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:48.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.04:05:48.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.04:05:48.06$vck44/valo=6,814.99 2006.257.04:05:48.06#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.04:05:48.06#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.04:05:48.06#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:48.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:48.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:48.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:48.06#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:05:48.06#ibcon#first serial, iclass 25, count 0 2006.257.04:05:48.06#ibcon#enter sib2, iclass 25, count 0 2006.257.04:05:48.06#ibcon#flushed, iclass 25, count 0 2006.257.04:05:48.06#ibcon#about to write, iclass 25, count 0 2006.257.04:05:48.06#ibcon#wrote, iclass 25, count 0 2006.257.04:05:48.06#ibcon#about to read 3, iclass 25, count 0 2006.257.04:05:48.08#ibcon#read 3, iclass 25, count 0 2006.257.04:05:48.08#ibcon#about to read 4, iclass 25, count 0 2006.257.04:05:48.08#ibcon#read 4, iclass 25, count 0 2006.257.04:05:48.08#ibcon#about to read 5, iclass 25, count 0 2006.257.04:05:48.08#ibcon#read 5, iclass 25, count 0 2006.257.04:05:48.08#ibcon#about to read 6, iclass 25, count 0 2006.257.04:05:48.08#ibcon#read 6, iclass 25, count 0 2006.257.04:05:48.08#ibcon#end of sib2, iclass 25, count 0 2006.257.04:05:48.08#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:05:48.08#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:05:48.08#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.04:05:48.08#ibcon#*before write, iclass 25, count 0 2006.257.04:05:48.08#ibcon#enter sib2, iclass 25, count 0 2006.257.04:05:48.08#ibcon#flushed, iclass 25, count 0 2006.257.04:05:48.08#ibcon#about to write, iclass 25, count 0 2006.257.04:05:48.08#ibcon#wrote, iclass 25, count 0 2006.257.04:05:48.08#ibcon#about to read 3, iclass 25, count 0 2006.257.04:05:48.12#ibcon#read 3, iclass 25, count 0 2006.257.04:05:48.12#ibcon#about to read 4, iclass 25, count 0 2006.257.04:05:48.12#ibcon#read 4, iclass 25, count 0 2006.257.04:05:48.12#ibcon#about to read 5, iclass 25, count 0 2006.257.04:05:48.12#ibcon#read 5, iclass 25, count 0 2006.257.04:05:48.12#ibcon#about to read 6, iclass 25, count 0 2006.257.04:05:48.12#ibcon#read 6, iclass 25, count 0 2006.257.04:05:48.12#ibcon#end of sib2, iclass 25, count 0 2006.257.04:05:48.12#ibcon#*after write, iclass 25, count 0 2006.257.04:05:48.12#ibcon#*before return 0, iclass 25, count 0 2006.257.04:05:48.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:48.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:48.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:05:48.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:05:48.12$vck44/va=6,4 2006.257.04:05:48.12#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.04:05:48.12#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.04:05:48.12#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:48.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:48.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:48.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:48.18#ibcon#enter wrdev, iclass 27, count 2 2006.257.04:05:48.18#ibcon#first serial, iclass 27, count 2 2006.257.04:05:48.18#ibcon#enter sib2, iclass 27, count 2 2006.257.04:05:48.18#ibcon#flushed, iclass 27, count 2 2006.257.04:05:48.18#ibcon#about to write, iclass 27, count 2 2006.257.04:05:48.18#ibcon#wrote, iclass 27, count 2 2006.257.04:05:48.18#ibcon#about to read 3, iclass 27, count 2 2006.257.04:05:48.20#ibcon#read 3, iclass 27, count 2 2006.257.04:05:48.20#ibcon#about to read 4, iclass 27, count 2 2006.257.04:05:48.20#ibcon#read 4, iclass 27, count 2 2006.257.04:05:48.20#ibcon#about to read 5, iclass 27, count 2 2006.257.04:05:48.20#ibcon#read 5, iclass 27, count 2 2006.257.04:05:48.20#ibcon#about to read 6, iclass 27, count 2 2006.257.04:05:48.20#ibcon#read 6, iclass 27, count 2 2006.257.04:05:48.20#ibcon#end of sib2, iclass 27, count 2 2006.257.04:05:48.20#ibcon#*mode == 0, iclass 27, count 2 2006.257.04:05:48.20#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.04:05:48.20#ibcon#[25=AT06-04\r\n] 2006.257.04:05:48.20#ibcon#*before write, iclass 27, count 2 2006.257.04:05:48.20#ibcon#enter sib2, iclass 27, count 2 2006.257.04:05:48.20#ibcon#flushed, iclass 27, count 2 2006.257.04:05:48.20#ibcon#about to write, iclass 27, count 2 2006.257.04:05:48.20#ibcon#wrote, iclass 27, count 2 2006.257.04:05:48.20#ibcon#about to read 3, iclass 27, count 2 2006.257.04:05:48.23#ibcon#read 3, iclass 27, count 2 2006.257.04:05:48.23#ibcon#about to read 4, iclass 27, count 2 2006.257.04:05:48.23#ibcon#read 4, iclass 27, count 2 2006.257.04:05:48.23#ibcon#about to read 5, iclass 27, count 2 2006.257.04:05:48.23#ibcon#read 5, iclass 27, count 2 2006.257.04:05:48.23#ibcon#about to read 6, iclass 27, count 2 2006.257.04:05:48.23#ibcon#read 6, iclass 27, count 2 2006.257.04:05:48.23#ibcon#end of sib2, iclass 27, count 2 2006.257.04:05:48.23#ibcon#*after write, iclass 27, count 2 2006.257.04:05:48.23#ibcon#*before return 0, iclass 27, count 2 2006.257.04:05:48.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:48.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:48.23#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.04:05:48.23#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:48.23#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:48.35#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:48.35#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:48.35#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:05:48.35#ibcon#first serial, iclass 27, count 0 2006.257.04:05:48.35#ibcon#enter sib2, iclass 27, count 0 2006.257.04:05:48.35#ibcon#flushed, iclass 27, count 0 2006.257.04:05:48.35#ibcon#about to write, iclass 27, count 0 2006.257.04:05:48.35#ibcon#wrote, iclass 27, count 0 2006.257.04:05:48.35#ibcon#about to read 3, iclass 27, count 0 2006.257.04:05:48.37#ibcon#read 3, iclass 27, count 0 2006.257.04:05:48.37#ibcon#about to read 4, iclass 27, count 0 2006.257.04:05:48.37#ibcon#read 4, iclass 27, count 0 2006.257.04:05:48.37#ibcon#about to read 5, iclass 27, count 0 2006.257.04:05:48.37#ibcon#read 5, iclass 27, count 0 2006.257.04:05:48.37#ibcon#about to read 6, iclass 27, count 0 2006.257.04:05:48.37#ibcon#read 6, iclass 27, count 0 2006.257.04:05:48.37#ibcon#end of sib2, iclass 27, count 0 2006.257.04:05:48.37#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:05:48.37#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:05:48.37#ibcon#[25=USB\r\n] 2006.257.04:05:48.37#ibcon#*before write, iclass 27, count 0 2006.257.04:05:48.37#ibcon#enter sib2, iclass 27, count 0 2006.257.04:05:48.37#ibcon#flushed, iclass 27, count 0 2006.257.04:05:48.37#ibcon#about to write, iclass 27, count 0 2006.257.04:05:48.37#ibcon#wrote, iclass 27, count 0 2006.257.04:05:48.37#ibcon#about to read 3, iclass 27, count 0 2006.257.04:05:48.40#ibcon#read 3, iclass 27, count 0 2006.257.04:05:48.40#ibcon#about to read 4, iclass 27, count 0 2006.257.04:05:48.40#ibcon#read 4, iclass 27, count 0 2006.257.04:05:48.40#ibcon#about to read 5, iclass 27, count 0 2006.257.04:05:48.40#ibcon#read 5, iclass 27, count 0 2006.257.04:05:48.40#ibcon#about to read 6, iclass 27, count 0 2006.257.04:05:48.40#ibcon#read 6, iclass 27, count 0 2006.257.04:05:48.40#ibcon#end of sib2, iclass 27, count 0 2006.257.04:05:48.40#ibcon#*after write, iclass 27, count 0 2006.257.04:05:48.40#ibcon#*before return 0, iclass 27, count 0 2006.257.04:05:48.40#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:48.40#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:48.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:05:48.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:05:48.40$vck44/valo=7,864.99 2006.257.04:05:48.40#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.04:05:48.40#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.04:05:48.40#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:48.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:48.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:48.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:48.40#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:05:48.40#ibcon#first serial, iclass 29, count 0 2006.257.04:05:48.40#ibcon#enter sib2, iclass 29, count 0 2006.257.04:05:48.40#ibcon#flushed, iclass 29, count 0 2006.257.04:05:48.40#ibcon#about to write, iclass 29, count 0 2006.257.04:05:48.40#ibcon#wrote, iclass 29, count 0 2006.257.04:05:48.40#ibcon#about to read 3, iclass 29, count 0 2006.257.04:05:48.42#ibcon#read 3, iclass 29, count 0 2006.257.04:05:48.42#ibcon#about to read 4, iclass 29, count 0 2006.257.04:05:48.42#ibcon#read 4, iclass 29, count 0 2006.257.04:05:48.42#ibcon#about to read 5, iclass 29, count 0 2006.257.04:05:48.42#ibcon#read 5, iclass 29, count 0 2006.257.04:05:48.42#ibcon#about to read 6, iclass 29, count 0 2006.257.04:05:48.42#ibcon#read 6, iclass 29, count 0 2006.257.04:05:48.42#ibcon#end of sib2, iclass 29, count 0 2006.257.04:05:48.42#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:05:48.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:05:48.42#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.04:05:48.42#ibcon#*before write, iclass 29, count 0 2006.257.04:05:48.42#ibcon#enter sib2, iclass 29, count 0 2006.257.04:05:48.42#ibcon#flushed, iclass 29, count 0 2006.257.04:05:48.42#ibcon#about to write, iclass 29, count 0 2006.257.04:05:48.42#ibcon#wrote, iclass 29, count 0 2006.257.04:05:48.42#ibcon#about to read 3, iclass 29, count 0 2006.257.04:05:48.46#ibcon#read 3, iclass 29, count 0 2006.257.04:05:48.46#ibcon#about to read 4, iclass 29, count 0 2006.257.04:05:48.46#ibcon#read 4, iclass 29, count 0 2006.257.04:05:48.46#ibcon#about to read 5, iclass 29, count 0 2006.257.04:05:48.46#ibcon#read 5, iclass 29, count 0 2006.257.04:05:48.46#ibcon#about to read 6, iclass 29, count 0 2006.257.04:05:48.46#ibcon#read 6, iclass 29, count 0 2006.257.04:05:48.46#ibcon#end of sib2, iclass 29, count 0 2006.257.04:05:48.46#ibcon#*after write, iclass 29, count 0 2006.257.04:05:48.46#ibcon#*before return 0, iclass 29, count 0 2006.257.04:05:48.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:48.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:48.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:05:48.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:05:48.46$vck44/va=7,4 2006.257.04:05:48.46#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.04:05:48.46#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.04:05:48.46#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:48.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:48.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:48.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:48.52#ibcon#enter wrdev, iclass 31, count 2 2006.257.04:05:48.52#ibcon#first serial, iclass 31, count 2 2006.257.04:05:48.52#ibcon#enter sib2, iclass 31, count 2 2006.257.04:05:48.52#ibcon#flushed, iclass 31, count 2 2006.257.04:05:48.52#ibcon#about to write, iclass 31, count 2 2006.257.04:05:48.52#ibcon#wrote, iclass 31, count 2 2006.257.04:05:48.52#ibcon#about to read 3, iclass 31, count 2 2006.257.04:05:48.54#ibcon#read 3, iclass 31, count 2 2006.257.04:05:48.54#ibcon#about to read 4, iclass 31, count 2 2006.257.04:05:48.54#ibcon#read 4, iclass 31, count 2 2006.257.04:05:48.54#ibcon#about to read 5, iclass 31, count 2 2006.257.04:05:48.54#ibcon#read 5, iclass 31, count 2 2006.257.04:05:48.54#ibcon#about to read 6, iclass 31, count 2 2006.257.04:05:48.54#ibcon#read 6, iclass 31, count 2 2006.257.04:05:48.54#ibcon#end of sib2, iclass 31, count 2 2006.257.04:05:48.54#ibcon#*mode == 0, iclass 31, count 2 2006.257.04:05:48.54#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.04:05:48.54#ibcon#[25=AT07-04\r\n] 2006.257.04:05:48.54#ibcon#*before write, iclass 31, count 2 2006.257.04:05:48.54#ibcon#enter sib2, iclass 31, count 2 2006.257.04:05:48.54#ibcon#flushed, iclass 31, count 2 2006.257.04:05:48.54#ibcon#about to write, iclass 31, count 2 2006.257.04:05:48.54#ibcon#wrote, iclass 31, count 2 2006.257.04:05:48.54#ibcon#about to read 3, iclass 31, count 2 2006.257.04:05:48.57#ibcon#read 3, iclass 31, count 2 2006.257.04:05:48.57#ibcon#about to read 4, iclass 31, count 2 2006.257.04:05:48.57#ibcon#read 4, iclass 31, count 2 2006.257.04:05:48.57#ibcon#about to read 5, iclass 31, count 2 2006.257.04:05:48.57#ibcon#read 5, iclass 31, count 2 2006.257.04:05:48.57#ibcon#about to read 6, iclass 31, count 2 2006.257.04:05:48.57#ibcon#read 6, iclass 31, count 2 2006.257.04:05:48.57#ibcon#end of sib2, iclass 31, count 2 2006.257.04:05:48.57#ibcon#*after write, iclass 31, count 2 2006.257.04:05:48.57#ibcon#*before return 0, iclass 31, count 2 2006.257.04:05:48.57#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:48.57#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:48.57#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.04:05:48.57#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:48.57#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:48.69#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:48.69#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:48.69#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:05:48.69#ibcon#first serial, iclass 31, count 0 2006.257.04:05:48.69#ibcon#enter sib2, iclass 31, count 0 2006.257.04:05:48.69#ibcon#flushed, iclass 31, count 0 2006.257.04:05:48.69#ibcon#about to write, iclass 31, count 0 2006.257.04:05:48.69#ibcon#wrote, iclass 31, count 0 2006.257.04:05:48.69#ibcon#about to read 3, iclass 31, count 0 2006.257.04:05:48.71#ibcon#read 3, iclass 31, count 0 2006.257.04:05:48.71#ibcon#about to read 4, iclass 31, count 0 2006.257.04:05:48.71#ibcon#read 4, iclass 31, count 0 2006.257.04:05:48.71#ibcon#about to read 5, iclass 31, count 0 2006.257.04:05:48.71#ibcon#read 5, iclass 31, count 0 2006.257.04:05:48.71#ibcon#about to read 6, iclass 31, count 0 2006.257.04:05:48.71#ibcon#read 6, iclass 31, count 0 2006.257.04:05:48.71#ibcon#end of sib2, iclass 31, count 0 2006.257.04:05:48.71#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:05:48.71#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:05:48.71#ibcon#[25=USB\r\n] 2006.257.04:05:48.71#ibcon#*before write, iclass 31, count 0 2006.257.04:05:48.71#ibcon#enter sib2, iclass 31, count 0 2006.257.04:05:48.71#ibcon#flushed, iclass 31, count 0 2006.257.04:05:48.71#ibcon#about to write, iclass 31, count 0 2006.257.04:05:48.71#ibcon#wrote, iclass 31, count 0 2006.257.04:05:48.71#ibcon#about to read 3, iclass 31, count 0 2006.257.04:05:48.74#ibcon#read 3, iclass 31, count 0 2006.257.04:05:48.74#ibcon#about to read 4, iclass 31, count 0 2006.257.04:05:48.74#ibcon#read 4, iclass 31, count 0 2006.257.04:05:48.74#ibcon#about to read 5, iclass 31, count 0 2006.257.04:05:48.74#ibcon#read 5, iclass 31, count 0 2006.257.04:05:48.74#ibcon#about to read 6, iclass 31, count 0 2006.257.04:05:48.74#ibcon#read 6, iclass 31, count 0 2006.257.04:05:48.74#ibcon#end of sib2, iclass 31, count 0 2006.257.04:05:48.74#ibcon#*after write, iclass 31, count 0 2006.257.04:05:48.74#ibcon#*before return 0, iclass 31, count 0 2006.257.04:05:48.74#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:48.74#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:48.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:05:48.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:05:48.74$vck44/valo=8,884.99 2006.257.04:05:48.74#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.04:05:48.74#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.04:05:48.74#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:48.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:48.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:48.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:48.74#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:05:48.74#ibcon#first serial, iclass 33, count 0 2006.257.04:05:48.74#ibcon#enter sib2, iclass 33, count 0 2006.257.04:05:48.74#ibcon#flushed, iclass 33, count 0 2006.257.04:05:48.74#ibcon#about to write, iclass 33, count 0 2006.257.04:05:48.74#ibcon#wrote, iclass 33, count 0 2006.257.04:05:48.74#ibcon#about to read 3, iclass 33, count 0 2006.257.04:05:48.76#ibcon#read 3, iclass 33, count 0 2006.257.04:05:48.76#ibcon#about to read 4, iclass 33, count 0 2006.257.04:05:48.76#ibcon#read 4, iclass 33, count 0 2006.257.04:05:48.76#ibcon#about to read 5, iclass 33, count 0 2006.257.04:05:48.76#ibcon#read 5, iclass 33, count 0 2006.257.04:05:48.76#ibcon#about to read 6, iclass 33, count 0 2006.257.04:05:48.76#ibcon#read 6, iclass 33, count 0 2006.257.04:05:48.76#ibcon#end of sib2, iclass 33, count 0 2006.257.04:05:48.76#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:05:48.76#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:05:48.76#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.04:05:48.76#ibcon#*before write, iclass 33, count 0 2006.257.04:05:48.76#ibcon#enter sib2, iclass 33, count 0 2006.257.04:05:48.76#ibcon#flushed, iclass 33, count 0 2006.257.04:05:48.76#ibcon#about to write, iclass 33, count 0 2006.257.04:05:48.76#ibcon#wrote, iclass 33, count 0 2006.257.04:05:48.76#ibcon#about to read 3, iclass 33, count 0 2006.257.04:05:48.80#ibcon#read 3, iclass 33, count 0 2006.257.04:05:48.80#ibcon#about to read 4, iclass 33, count 0 2006.257.04:05:48.80#ibcon#read 4, iclass 33, count 0 2006.257.04:05:48.80#ibcon#about to read 5, iclass 33, count 0 2006.257.04:05:48.80#ibcon#read 5, iclass 33, count 0 2006.257.04:05:48.80#ibcon#about to read 6, iclass 33, count 0 2006.257.04:05:48.80#ibcon#read 6, iclass 33, count 0 2006.257.04:05:48.80#ibcon#end of sib2, iclass 33, count 0 2006.257.04:05:48.80#ibcon#*after write, iclass 33, count 0 2006.257.04:05:48.80#ibcon#*before return 0, iclass 33, count 0 2006.257.04:05:48.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:48.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:48.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:05:48.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:05:48.80$vck44/va=8,4 2006.257.04:05:48.80#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.04:05:48.80#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.04:05:48.80#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:48.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:48.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:48.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:48.86#ibcon#enter wrdev, iclass 35, count 2 2006.257.04:05:48.86#ibcon#first serial, iclass 35, count 2 2006.257.04:05:48.86#ibcon#enter sib2, iclass 35, count 2 2006.257.04:05:48.86#ibcon#flushed, iclass 35, count 2 2006.257.04:05:48.86#ibcon#about to write, iclass 35, count 2 2006.257.04:05:48.86#ibcon#wrote, iclass 35, count 2 2006.257.04:05:48.86#ibcon#about to read 3, iclass 35, count 2 2006.257.04:05:48.88#ibcon#read 3, iclass 35, count 2 2006.257.04:05:48.88#ibcon#about to read 4, iclass 35, count 2 2006.257.04:05:48.88#ibcon#read 4, iclass 35, count 2 2006.257.04:05:48.88#ibcon#about to read 5, iclass 35, count 2 2006.257.04:05:48.88#ibcon#read 5, iclass 35, count 2 2006.257.04:05:48.88#ibcon#about to read 6, iclass 35, count 2 2006.257.04:05:48.88#ibcon#read 6, iclass 35, count 2 2006.257.04:05:48.88#ibcon#end of sib2, iclass 35, count 2 2006.257.04:05:48.88#ibcon#*mode == 0, iclass 35, count 2 2006.257.04:05:48.88#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.04:05:48.88#ibcon#[25=AT08-04\r\n] 2006.257.04:05:48.88#ibcon#*before write, iclass 35, count 2 2006.257.04:05:48.88#ibcon#enter sib2, iclass 35, count 2 2006.257.04:05:48.88#ibcon#flushed, iclass 35, count 2 2006.257.04:05:48.88#ibcon#about to write, iclass 35, count 2 2006.257.04:05:48.88#ibcon#wrote, iclass 35, count 2 2006.257.04:05:48.88#ibcon#about to read 3, iclass 35, count 2 2006.257.04:05:48.91#ibcon#read 3, iclass 35, count 2 2006.257.04:05:48.91#ibcon#about to read 4, iclass 35, count 2 2006.257.04:05:48.91#ibcon#read 4, iclass 35, count 2 2006.257.04:05:48.91#ibcon#about to read 5, iclass 35, count 2 2006.257.04:05:48.91#ibcon#read 5, iclass 35, count 2 2006.257.04:05:48.91#ibcon#about to read 6, iclass 35, count 2 2006.257.04:05:48.91#ibcon#read 6, iclass 35, count 2 2006.257.04:05:48.91#ibcon#end of sib2, iclass 35, count 2 2006.257.04:05:48.91#ibcon#*after write, iclass 35, count 2 2006.257.04:05:48.91#ibcon#*before return 0, iclass 35, count 2 2006.257.04:05:48.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:48.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:48.91#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.04:05:48.91#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:48.91#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:49.03#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:49.03#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:49.03#ibcon#enter wrdev, iclass 35, count 0 2006.257.04:05:49.03#ibcon#first serial, iclass 35, count 0 2006.257.04:05:49.03#ibcon#enter sib2, iclass 35, count 0 2006.257.04:05:49.03#ibcon#flushed, iclass 35, count 0 2006.257.04:05:49.03#ibcon#about to write, iclass 35, count 0 2006.257.04:05:49.03#ibcon#wrote, iclass 35, count 0 2006.257.04:05:49.03#ibcon#about to read 3, iclass 35, count 0 2006.257.04:05:49.05#ibcon#read 3, iclass 35, count 0 2006.257.04:05:49.05#ibcon#about to read 4, iclass 35, count 0 2006.257.04:05:49.05#ibcon#read 4, iclass 35, count 0 2006.257.04:05:49.05#ibcon#about to read 5, iclass 35, count 0 2006.257.04:05:49.05#ibcon#read 5, iclass 35, count 0 2006.257.04:05:49.05#ibcon#about to read 6, iclass 35, count 0 2006.257.04:05:49.05#ibcon#read 6, iclass 35, count 0 2006.257.04:05:49.05#ibcon#end of sib2, iclass 35, count 0 2006.257.04:05:49.05#ibcon#*mode == 0, iclass 35, count 0 2006.257.04:05:49.05#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.04:05:49.05#ibcon#[25=USB\r\n] 2006.257.04:05:49.05#ibcon#*before write, iclass 35, count 0 2006.257.04:05:49.05#ibcon#enter sib2, iclass 35, count 0 2006.257.04:05:49.05#ibcon#flushed, iclass 35, count 0 2006.257.04:05:49.05#ibcon#about to write, iclass 35, count 0 2006.257.04:05:49.05#ibcon#wrote, iclass 35, count 0 2006.257.04:05:49.05#ibcon#about to read 3, iclass 35, count 0 2006.257.04:05:49.08#ibcon#read 3, iclass 35, count 0 2006.257.04:05:49.08#ibcon#about to read 4, iclass 35, count 0 2006.257.04:05:49.08#ibcon#read 4, iclass 35, count 0 2006.257.04:05:49.08#ibcon#about to read 5, iclass 35, count 0 2006.257.04:05:49.08#ibcon#read 5, iclass 35, count 0 2006.257.04:05:49.08#ibcon#about to read 6, iclass 35, count 0 2006.257.04:05:49.08#ibcon#read 6, iclass 35, count 0 2006.257.04:05:49.08#ibcon#end of sib2, iclass 35, count 0 2006.257.04:05:49.08#ibcon#*after write, iclass 35, count 0 2006.257.04:05:49.08#ibcon#*before return 0, iclass 35, count 0 2006.257.04:05:49.08#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:49.08#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:49.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.04:05:49.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.04:05:49.08$vck44/vblo=1,629.99 2006.257.04:05:49.08#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.04:05:49.08#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.04:05:49.08#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:49.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:49.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:49.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:49.08#ibcon#enter wrdev, iclass 37, count 0 2006.257.04:05:49.08#ibcon#first serial, iclass 37, count 0 2006.257.04:05:49.08#ibcon#enter sib2, iclass 37, count 0 2006.257.04:05:49.08#ibcon#flushed, iclass 37, count 0 2006.257.04:05:49.08#ibcon#about to write, iclass 37, count 0 2006.257.04:05:49.08#ibcon#wrote, iclass 37, count 0 2006.257.04:05:49.08#ibcon#about to read 3, iclass 37, count 0 2006.257.04:05:49.10#ibcon#read 3, iclass 37, count 0 2006.257.04:05:49.10#ibcon#about to read 4, iclass 37, count 0 2006.257.04:05:49.10#ibcon#read 4, iclass 37, count 0 2006.257.04:05:49.10#ibcon#about to read 5, iclass 37, count 0 2006.257.04:05:49.10#ibcon#read 5, iclass 37, count 0 2006.257.04:05:49.10#ibcon#about to read 6, iclass 37, count 0 2006.257.04:05:49.10#ibcon#read 6, iclass 37, count 0 2006.257.04:05:49.10#ibcon#end of sib2, iclass 37, count 0 2006.257.04:05:49.10#ibcon#*mode == 0, iclass 37, count 0 2006.257.04:05:49.10#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.04:05:49.10#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.04:05:49.10#ibcon#*before write, iclass 37, count 0 2006.257.04:05:49.10#ibcon#enter sib2, iclass 37, count 0 2006.257.04:05:49.10#ibcon#flushed, iclass 37, count 0 2006.257.04:05:49.10#ibcon#about to write, iclass 37, count 0 2006.257.04:05:49.10#ibcon#wrote, iclass 37, count 0 2006.257.04:05:49.10#ibcon#about to read 3, iclass 37, count 0 2006.257.04:05:49.14#ibcon#read 3, iclass 37, count 0 2006.257.04:05:49.14#ibcon#about to read 4, iclass 37, count 0 2006.257.04:05:49.14#ibcon#read 4, iclass 37, count 0 2006.257.04:05:49.14#ibcon#about to read 5, iclass 37, count 0 2006.257.04:05:49.14#ibcon#read 5, iclass 37, count 0 2006.257.04:05:49.14#ibcon#about to read 6, iclass 37, count 0 2006.257.04:05:49.14#ibcon#read 6, iclass 37, count 0 2006.257.04:05:49.14#ibcon#end of sib2, iclass 37, count 0 2006.257.04:05:49.14#ibcon#*after write, iclass 37, count 0 2006.257.04:05:49.14#ibcon#*before return 0, iclass 37, count 0 2006.257.04:05:49.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:49.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:49.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.04:05:49.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.04:05:49.14$vck44/vb=1,4 2006.257.04:05:49.14#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.04:05:49.14#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.04:05:49.14#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:49.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:05:49.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:05:49.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:05:49.14#ibcon#enter wrdev, iclass 39, count 2 2006.257.04:05:49.14#ibcon#first serial, iclass 39, count 2 2006.257.04:05:49.14#ibcon#enter sib2, iclass 39, count 2 2006.257.04:05:49.14#ibcon#flushed, iclass 39, count 2 2006.257.04:05:49.14#ibcon#about to write, iclass 39, count 2 2006.257.04:05:49.14#ibcon#wrote, iclass 39, count 2 2006.257.04:05:49.14#ibcon#about to read 3, iclass 39, count 2 2006.257.04:05:49.16#ibcon#read 3, iclass 39, count 2 2006.257.04:05:49.16#ibcon#about to read 4, iclass 39, count 2 2006.257.04:05:49.16#ibcon#read 4, iclass 39, count 2 2006.257.04:05:49.16#ibcon#about to read 5, iclass 39, count 2 2006.257.04:05:49.16#ibcon#read 5, iclass 39, count 2 2006.257.04:05:49.16#ibcon#about to read 6, iclass 39, count 2 2006.257.04:05:49.16#ibcon#read 6, iclass 39, count 2 2006.257.04:05:49.16#ibcon#end of sib2, iclass 39, count 2 2006.257.04:05:49.16#ibcon#*mode == 0, iclass 39, count 2 2006.257.04:05:49.16#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.04:05:49.16#ibcon#[27=AT01-04\r\n] 2006.257.04:05:49.16#ibcon#*before write, iclass 39, count 2 2006.257.04:05:49.16#ibcon#enter sib2, iclass 39, count 2 2006.257.04:05:49.16#ibcon#flushed, iclass 39, count 2 2006.257.04:05:49.16#ibcon#about to write, iclass 39, count 2 2006.257.04:05:49.16#ibcon#wrote, iclass 39, count 2 2006.257.04:05:49.16#ibcon#about to read 3, iclass 39, count 2 2006.257.04:05:49.19#ibcon#read 3, iclass 39, count 2 2006.257.04:05:49.19#ibcon#about to read 4, iclass 39, count 2 2006.257.04:05:49.19#ibcon#read 4, iclass 39, count 2 2006.257.04:05:49.19#ibcon#about to read 5, iclass 39, count 2 2006.257.04:05:49.19#ibcon#read 5, iclass 39, count 2 2006.257.04:05:49.19#ibcon#about to read 6, iclass 39, count 2 2006.257.04:05:49.19#ibcon#read 6, iclass 39, count 2 2006.257.04:05:49.19#ibcon#end of sib2, iclass 39, count 2 2006.257.04:05:49.19#ibcon#*after write, iclass 39, count 2 2006.257.04:05:49.19#ibcon#*before return 0, iclass 39, count 2 2006.257.04:05:49.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:05:49.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:05:49.19#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.04:05:49.19#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:49.19#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:05:49.31#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:05:49.31#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:05:49.31#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:05:49.31#ibcon#first serial, iclass 39, count 0 2006.257.04:05:49.31#ibcon#enter sib2, iclass 39, count 0 2006.257.04:05:49.31#ibcon#flushed, iclass 39, count 0 2006.257.04:05:49.31#ibcon#about to write, iclass 39, count 0 2006.257.04:05:49.31#ibcon#wrote, iclass 39, count 0 2006.257.04:05:49.31#ibcon#about to read 3, iclass 39, count 0 2006.257.04:05:49.33#ibcon#read 3, iclass 39, count 0 2006.257.04:05:49.33#ibcon#about to read 4, iclass 39, count 0 2006.257.04:05:49.33#ibcon#read 4, iclass 39, count 0 2006.257.04:05:49.33#ibcon#about to read 5, iclass 39, count 0 2006.257.04:05:49.33#ibcon#read 5, iclass 39, count 0 2006.257.04:05:49.33#ibcon#about to read 6, iclass 39, count 0 2006.257.04:05:49.33#ibcon#read 6, iclass 39, count 0 2006.257.04:05:49.33#ibcon#end of sib2, iclass 39, count 0 2006.257.04:05:49.33#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:05:49.33#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:05:49.33#ibcon#[27=USB\r\n] 2006.257.04:05:49.33#ibcon#*before write, iclass 39, count 0 2006.257.04:05:49.33#ibcon#enter sib2, iclass 39, count 0 2006.257.04:05:49.33#ibcon#flushed, iclass 39, count 0 2006.257.04:05:49.33#ibcon#about to write, iclass 39, count 0 2006.257.04:05:49.33#ibcon#wrote, iclass 39, count 0 2006.257.04:05:49.33#ibcon#about to read 3, iclass 39, count 0 2006.257.04:05:49.36#ibcon#read 3, iclass 39, count 0 2006.257.04:05:49.36#ibcon#about to read 4, iclass 39, count 0 2006.257.04:05:49.36#ibcon#read 4, iclass 39, count 0 2006.257.04:05:49.36#ibcon#about to read 5, iclass 39, count 0 2006.257.04:05:49.36#ibcon#read 5, iclass 39, count 0 2006.257.04:05:49.36#ibcon#about to read 6, iclass 39, count 0 2006.257.04:05:49.36#ibcon#read 6, iclass 39, count 0 2006.257.04:05:49.36#ibcon#end of sib2, iclass 39, count 0 2006.257.04:05:49.36#ibcon#*after write, iclass 39, count 0 2006.257.04:05:49.36#ibcon#*before return 0, iclass 39, count 0 2006.257.04:05:49.36#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:05:49.36#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:05:49.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:05:49.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:05:49.36$vck44/vblo=2,634.99 2006.257.04:05:49.36#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.04:05:49.36#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.04:05:49.36#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:49.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:49.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:49.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:49.36#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:05:49.36#ibcon#first serial, iclass 3, count 0 2006.257.04:05:49.36#ibcon#enter sib2, iclass 3, count 0 2006.257.04:05:49.36#ibcon#flushed, iclass 3, count 0 2006.257.04:05:49.36#ibcon#about to write, iclass 3, count 0 2006.257.04:05:49.36#ibcon#wrote, iclass 3, count 0 2006.257.04:05:49.36#ibcon#about to read 3, iclass 3, count 0 2006.257.04:05:49.38#ibcon#read 3, iclass 3, count 0 2006.257.04:05:49.38#ibcon#about to read 4, iclass 3, count 0 2006.257.04:05:49.38#ibcon#read 4, iclass 3, count 0 2006.257.04:05:49.38#ibcon#about to read 5, iclass 3, count 0 2006.257.04:05:49.38#ibcon#read 5, iclass 3, count 0 2006.257.04:05:49.38#ibcon#about to read 6, iclass 3, count 0 2006.257.04:05:49.38#ibcon#read 6, iclass 3, count 0 2006.257.04:05:49.38#ibcon#end of sib2, iclass 3, count 0 2006.257.04:05:49.38#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:05:49.38#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:05:49.38#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.04:05:49.38#ibcon#*before write, iclass 3, count 0 2006.257.04:05:49.38#ibcon#enter sib2, iclass 3, count 0 2006.257.04:05:49.38#ibcon#flushed, iclass 3, count 0 2006.257.04:05:49.38#ibcon#about to write, iclass 3, count 0 2006.257.04:05:49.38#ibcon#wrote, iclass 3, count 0 2006.257.04:05:49.38#ibcon#about to read 3, iclass 3, count 0 2006.257.04:05:49.42#ibcon#read 3, iclass 3, count 0 2006.257.04:05:49.42#ibcon#about to read 4, iclass 3, count 0 2006.257.04:05:49.42#ibcon#read 4, iclass 3, count 0 2006.257.04:05:49.42#ibcon#about to read 5, iclass 3, count 0 2006.257.04:05:49.42#ibcon#read 5, iclass 3, count 0 2006.257.04:05:49.42#ibcon#about to read 6, iclass 3, count 0 2006.257.04:05:49.42#ibcon#read 6, iclass 3, count 0 2006.257.04:05:49.42#ibcon#end of sib2, iclass 3, count 0 2006.257.04:05:49.42#ibcon#*after write, iclass 3, count 0 2006.257.04:05:49.42#ibcon#*before return 0, iclass 3, count 0 2006.257.04:05:49.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:49.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:05:49.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:05:49.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:05:49.42$vck44/vb=2,5 2006.257.04:05:49.42#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.04:05:49.42#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.04:05:49.42#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:49.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:49.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:49.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:49.48#ibcon#enter wrdev, iclass 5, count 2 2006.257.04:05:49.48#ibcon#first serial, iclass 5, count 2 2006.257.04:05:49.48#ibcon#enter sib2, iclass 5, count 2 2006.257.04:05:49.48#ibcon#flushed, iclass 5, count 2 2006.257.04:05:49.48#ibcon#about to write, iclass 5, count 2 2006.257.04:05:49.48#ibcon#wrote, iclass 5, count 2 2006.257.04:05:49.48#ibcon#about to read 3, iclass 5, count 2 2006.257.04:05:49.50#ibcon#read 3, iclass 5, count 2 2006.257.04:05:49.50#ibcon#about to read 4, iclass 5, count 2 2006.257.04:05:49.50#ibcon#read 4, iclass 5, count 2 2006.257.04:05:49.50#ibcon#about to read 5, iclass 5, count 2 2006.257.04:05:49.50#ibcon#read 5, iclass 5, count 2 2006.257.04:05:49.50#ibcon#about to read 6, iclass 5, count 2 2006.257.04:05:49.50#ibcon#read 6, iclass 5, count 2 2006.257.04:05:49.50#ibcon#end of sib2, iclass 5, count 2 2006.257.04:05:49.50#ibcon#*mode == 0, iclass 5, count 2 2006.257.04:05:49.50#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.04:05:49.50#ibcon#[27=AT02-05\r\n] 2006.257.04:05:49.50#ibcon#*before write, iclass 5, count 2 2006.257.04:05:49.50#ibcon#enter sib2, iclass 5, count 2 2006.257.04:05:49.50#ibcon#flushed, iclass 5, count 2 2006.257.04:05:49.50#ibcon#about to write, iclass 5, count 2 2006.257.04:05:49.50#ibcon#wrote, iclass 5, count 2 2006.257.04:05:49.50#ibcon#about to read 3, iclass 5, count 2 2006.257.04:05:49.53#ibcon#read 3, iclass 5, count 2 2006.257.04:05:49.53#ibcon#about to read 4, iclass 5, count 2 2006.257.04:05:49.53#ibcon#read 4, iclass 5, count 2 2006.257.04:05:49.53#ibcon#about to read 5, iclass 5, count 2 2006.257.04:05:49.53#ibcon#read 5, iclass 5, count 2 2006.257.04:05:49.53#ibcon#about to read 6, iclass 5, count 2 2006.257.04:05:49.53#ibcon#read 6, iclass 5, count 2 2006.257.04:05:49.53#ibcon#end of sib2, iclass 5, count 2 2006.257.04:05:49.53#ibcon#*after write, iclass 5, count 2 2006.257.04:05:49.53#ibcon#*before return 0, iclass 5, count 2 2006.257.04:05:49.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:49.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:05:49.53#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.04:05:49.53#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:49.53#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:49.60#abcon#<5=/14 2.3 5.9 19.26 951011.9\r\n> 2006.257.04:05:49.62#abcon#{5=INTERFACE CLEAR} 2006.257.04:05:49.65#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:49.65#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:49.65#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:05:49.65#ibcon#first serial, iclass 5, count 0 2006.257.04:05:49.65#ibcon#enter sib2, iclass 5, count 0 2006.257.04:05:49.65#ibcon#flushed, iclass 5, count 0 2006.257.04:05:49.65#ibcon#about to write, iclass 5, count 0 2006.257.04:05:49.65#ibcon#wrote, iclass 5, count 0 2006.257.04:05:49.65#ibcon#about to read 3, iclass 5, count 0 2006.257.04:05:49.67#ibcon#read 3, iclass 5, count 0 2006.257.04:05:49.67#ibcon#about to read 4, iclass 5, count 0 2006.257.04:05:49.67#ibcon#read 4, iclass 5, count 0 2006.257.04:05:49.67#ibcon#about to read 5, iclass 5, count 0 2006.257.04:05:49.67#ibcon#read 5, iclass 5, count 0 2006.257.04:05:49.67#ibcon#about to read 6, iclass 5, count 0 2006.257.04:05:49.67#ibcon#read 6, iclass 5, count 0 2006.257.04:05:49.67#ibcon#end of sib2, iclass 5, count 0 2006.257.04:05:49.67#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:05:49.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:05:49.67#ibcon#[27=USB\r\n] 2006.257.04:05:49.67#ibcon#*before write, iclass 5, count 0 2006.257.04:05:49.67#ibcon#enter sib2, iclass 5, count 0 2006.257.04:05:49.67#ibcon#flushed, iclass 5, count 0 2006.257.04:05:49.67#ibcon#about to write, iclass 5, count 0 2006.257.04:05:49.67#ibcon#wrote, iclass 5, count 0 2006.257.04:05:49.67#ibcon#about to read 3, iclass 5, count 0 2006.257.04:05:49.68#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:05:49.70#ibcon#read 3, iclass 5, count 0 2006.257.04:05:49.70#ibcon#about to read 4, iclass 5, count 0 2006.257.04:05:49.70#ibcon#read 4, iclass 5, count 0 2006.257.04:05:49.70#ibcon#about to read 5, iclass 5, count 0 2006.257.04:05:49.70#ibcon#read 5, iclass 5, count 0 2006.257.04:05:49.70#ibcon#about to read 6, iclass 5, count 0 2006.257.04:05:49.70#ibcon#read 6, iclass 5, count 0 2006.257.04:05:49.70#ibcon#end of sib2, iclass 5, count 0 2006.257.04:05:49.70#ibcon#*after write, iclass 5, count 0 2006.257.04:05:49.70#ibcon#*before return 0, iclass 5, count 0 2006.257.04:05:49.70#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:49.70#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:05:49.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:05:49.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:05:49.70$vck44/vblo=3,649.99 2006.257.04:05:49.70#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.04:05:49.70#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.04:05:49.70#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:49.70#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:49.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:49.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:49.70#ibcon#enter wrdev, iclass 13, count 0 2006.257.04:05:49.70#ibcon#first serial, iclass 13, count 0 2006.257.04:05:49.70#ibcon#enter sib2, iclass 13, count 0 2006.257.04:05:49.70#ibcon#flushed, iclass 13, count 0 2006.257.04:05:49.70#ibcon#about to write, iclass 13, count 0 2006.257.04:05:49.70#ibcon#wrote, iclass 13, count 0 2006.257.04:05:49.70#ibcon#about to read 3, iclass 13, count 0 2006.257.04:05:49.72#ibcon#read 3, iclass 13, count 0 2006.257.04:05:49.72#ibcon#about to read 4, iclass 13, count 0 2006.257.04:05:49.72#ibcon#read 4, iclass 13, count 0 2006.257.04:05:49.72#ibcon#about to read 5, iclass 13, count 0 2006.257.04:05:49.72#ibcon#read 5, iclass 13, count 0 2006.257.04:05:49.72#ibcon#about to read 6, iclass 13, count 0 2006.257.04:05:49.72#ibcon#read 6, iclass 13, count 0 2006.257.04:05:49.72#ibcon#end of sib2, iclass 13, count 0 2006.257.04:05:49.72#ibcon#*mode == 0, iclass 13, count 0 2006.257.04:05:49.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.04:05:49.72#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.04:05:49.72#ibcon#*before write, iclass 13, count 0 2006.257.04:05:49.72#ibcon#enter sib2, iclass 13, count 0 2006.257.04:05:49.72#ibcon#flushed, iclass 13, count 0 2006.257.04:05:49.72#ibcon#about to write, iclass 13, count 0 2006.257.04:05:49.72#ibcon#wrote, iclass 13, count 0 2006.257.04:05:49.72#ibcon#about to read 3, iclass 13, count 0 2006.257.04:05:49.76#ibcon#read 3, iclass 13, count 0 2006.257.04:05:49.76#ibcon#about to read 4, iclass 13, count 0 2006.257.04:05:49.76#ibcon#read 4, iclass 13, count 0 2006.257.04:05:49.76#ibcon#about to read 5, iclass 13, count 0 2006.257.04:05:49.76#ibcon#read 5, iclass 13, count 0 2006.257.04:05:49.76#ibcon#about to read 6, iclass 13, count 0 2006.257.04:05:49.76#ibcon#read 6, iclass 13, count 0 2006.257.04:05:49.76#ibcon#end of sib2, iclass 13, count 0 2006.257.04:05:49.76#ibcon#*after write, iclass 13, count 0 2006.257.04:05:49.76#ibcon#*before return 0, iclass 13, count 0 2006.257.04:05:49.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:49.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:05:49.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.04:05:49.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.04:05:49.76$vck44/vb=3,4 2006.257.04:05:49.76#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.04:05:49.76#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.04:05:49.76#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:49.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:49.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:49.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:49.82#ibcon#enter wrdev, iclass 15, count 2 2006.257.04:05:49.82#ibcon#first serial, iclass 15, count 2 2006.257.04:05:49.82#ibcon#enter sib2, iclass 15, count 2 2006.257.04:05:49.82#ibcon#flushed, iclass 15, count 2 2006.257.04:05:49.82#ibcon#about to write, iclass 15, count 2 2006.257.04:05:49.82#ibcon#wrote, iclass 15, count 2 2006.257.04:05:49.82#ibcon#about to read 3, iclass 15, count 2 2006.257.04:05:49.84#ibcon#read 3, iclass 15, count 2 2006.257.04:05:49.84#ibcon#about to read 4, iclass 15, count 2 2006.257.04:05:49.84#ibcon#read 4, iclass 15, count 2 2006.257.04:05:49.84#ibcon#about to read 5, iclass 15, count 2 2006.257.04:05:49.84#ibcon#read 5, iclass 15, count 2 2006.257.04:05:49.84#ibcon#about to read 6, iclass 15, count 2 2006.257.04:05:49.84#ibcon#read 6, iclass 15, count 2 2006.257.04:05:49.84#ibcon#end of sib2, iclass 15, count 2 2006.257.04:05:49.84#ibcon#*mode == 0, iclass 15, count 2 2006.257.04:05:49.84#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.04:05:49.84#ibcon#[27=AT03-04\r\n] 2006.257.04:05:49.84#ibcon#*before write, iclass 15, count 2 2006.257.04:05:49.84#ibcon#enter sib2, iclass 15, count 2 2006.257.04:05:49.84#ibcon#flushed, iclass 15, count 2 2006.257.04:05:49.84#ibcon#about to write, iclass 15, count 2 2006.257.04:05:49.84#ibcon#wrote, iclass 15, count 2 2006.257.04:05:49.84#ibcon#about to read 3, iclass 15, count 2 2006.257.04:05:49.87#ibcon#read 3, iclass 15, count 2 2006.257.04:05:49.87#ibcon#about to read 4, iclass 15, count 2 2006.257.04:05:49.87#ibcon#read 4, iclass 15, count 2 2006.257.04:05:49.87#ibcon#about to read 5, iclass 15, count 2 2006.257.04:05:49.87#ibcon#read 5, iclass 15, count 2 2006.257.04:05:49.87#ibcon#about to read 6, iclass 15, count 2 2006.257.04:05:49.87#ibcon#read 6, iclass 15, count 2 2006.257.04:05:49.87#ibcon#end of sib2, iclass 15, count 2 2006.257.04:05:49.87#ibcon#*after write, iclass 15, count 2 2006.257.04:05:49.87#ibcon#*before return 0, iclass 15, count 2 2006.257.04:05:49.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:49.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:05:49.87#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.04:05:49.87#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:49.87#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:49.99#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:49.99#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:49.99#ibcon#enter wrdev, iclass 15, count 0 2006.257.04:05:49.99#ibcon#first serial, iclass 15, count 0 2006.257.04:05:49.99#ibcon#enter sib2, iclass 15, count 0 2006.257.04:05:49.99#ibcon#flushed, iclass 15, count 0 2006.257.04:05:49.99#ibcon#about to write, iclass 15, count 0 2006.257.04:05:49.99#ibcon#wrote, iclass 15, count 0 2006.257.04:05:49.99#ibcon#about to read 3, iclass 15, count 0 2006.257.04:05:50.01#ibcon#read 3, iclass 15, count 0 2006.257.04:05:50.01#ibcon#about to read 4, iclass 15, count 0 2006.257.04:05:50.01#ibcon#read 4, iclass 15, count 0 2006.257.04:05:50.01#ibcon#about to read 5, iclass 15, count 0 2006.257.04:05:50.01#ibcon#read 5, iclass 15, count 0 2006.257.04:05:50.01#ibcon#about to read 6, iclass 15, count 0 2006.257.04:05:50.01#ibcon#read 6, iclass 15, count 0 2006.257.04:05:50.01#ibcon#end of sib2, iclass 15, count 0 2006.257.04:05:50.01#ibcon#*mode == 0, iclass 15, count 0 2006.257.04:05:50.01#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.04:05:50.01#ibcon#[27=USB\r\n] 2006.257.04:05:50.01#ibcon#*before write, iclass 15, count 0 2006.257.04:05:50.01#ibcon#enter sib2, iclass 15, count 0 2006.257.04:05:50.01#ibcon#flushed, iclass 15, count 0 2006.257.04:05:50.01#ibcon#about to write, iclass 15, count 0 2006.257.04:05:50.01#ibcon#wrote, iclass 15, count 0 2006.257.04:05:50.01#ibcon#about to read 3, iclass 15, count 0 2006.257.04:05:50.04#ibcon#read 3, iclass 15, count 0 2006.257.04:05:50.04#ibcon#about to read 4, iclass 15, count 0 2006.257.04:05:50.04#ibcon#read 4, iclass 15, count 0 2006.257.04:05:50.04#ibcon#about to read 5, iclass 15, count 0 2006.257.04:05:50.04#ibcon#read 5, iclass 15, count 0 2006.257.04:05:50.04#ibcon#about to read 6, iclass 15, count 0 2006.257.04:05:50.04#ibcon#read 6, iclass 15, count 0 2006.257.04:05:50.04#ibcon#end of sib2, iclass 15, count 0 2006.257.04:05:50.04#ibcon#*after write, iclass 15, count 0 2006.257.04:05:50.04#ibcon#*before return 0, iclass 15, count 0 2006.257.04:05:50.04#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:50.04#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:05:50.04#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.04:05:50.04#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.04:05:50.04$vck44/vblo=4,679.99 2006.257.04:05:50.04#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.04:05:50.04#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.04:05:50.04#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:50.04#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:50.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:50.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:50.04#ibcon#enter wrdev, iclass 17, count 0 2006.257.04:05:50.04#ibcon#first serial, iclass 17, count 0 2006.257.04:05:50.04#ibcon#enter sib2, iclass 17, count 0 2006.257.04:05:50.04#ibcon#flushed, iclass 17, count 0 2006.257.04:05:50.04#ibcon#about to write, iclass 17, count 0 2006.257.04:05:50.04#ibcon#wrote, iclass 17, count 0 2006.257.04:05:50.04#ibcon#about to read 3, iclass 17, count 0 2006.257.04:05:50.06#ibcon#read 3, iclass 17, count 0 2006.257.04:05:50.06#ibcon#about to read 4, iclass 17, count 0 2006.257.04:05:50.06#ibcon#read 4, iclass 17, count 0 2006.257.04:05:50.06#ibcon#about to read 5, iclass 17, count 0 2006.257.04:05:50.06#ibcon#read 5, iclass 17, count 0 2006.257.04:05:50.06#ibcon#about to read 6, iclass 17, count 0 2006.257.04:05:50.06#ibcon#read 6, iclass 17, count 0 2006.257.04:05:50.06#ibcon#end of sib2, iclass 17, count 0 2006.257.04:05:50.06#ibcon#*mode == 0, iclass 17, count 0 2006.257.04:05:50.06#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.04:05:50.06#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.04:05:50.06#ibcon#*before write, iclass 17, count 0 2006.257.04:05:50.06#ibcon#enter sib2, iclass 17, count 0 2006.257.04:05:50.06#ibcon#flushed, iclass 17, count 0 2006.257.04:05:50.06#ibcon#about to write, iclass 17, count 0 2006.257.04:05:50.06#ibcon#wrote, iclass 17, count 0 2006.257.04:05:50.06#ibcon#about to read 3, iclass 17, count 0 2006.257.04:05:50.10#ibcon#read 3, iclass 17, count 0 2006.257.04:05:50.10#ibcon#about to read 4, iclass 17, count 0 2006.257.04:05:50.10#ibcon#read 4, iclass 17, count 0 2006.257.04:05:50.10#ibcon#about to read 5, iclass 17, count 0 2006.257.04:05:50.10#ibcon#read 5, iclass 17, count 0 2006.257.04:05:50.10#ibcon#about to read 6, iclass 17, count 0 2006.257.04:05:50.10#ibcon#read 6, iclass 17, count 0 2006.257.04:05:50.10#ibcon#end of sib2, iclass 17, count 0 2006.257.04:05:50.10#ibcon#*after write, iclass 17, count 0 2006.257.04:05:50.10#ibcon#*before return 0, iclass 17, count 0 2006.257.04:05:50.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:50.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:05:50.10#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.04:05:50.10#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.04:05:50.10$vck44/vb=4,5 2006.257.04:05:50.10#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.04:05:50.10#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.04:05:50.10#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:50.10#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:50.16#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:50.16#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:50.16#ibcon#enter wrdev, iclass 19, count 2 2006.257.04:05:50.16#ibcon#first serial, iclass 19, count 2 2006.257.04:05:50.16#ibcon#enter sib2, iclass 19, count 2 2006.257.04:05:50.16#ibcon#flushed, iclass 19, count 2 2006.257.04:05:50.16#ibcon#about to write, iclass 19, count 2 2006.257.04:05:50.16#ibcon#wrote, iclass 19, count 2 2006.257.04:05:50.16#ibcon#about to read 3, iclass 19, count 2 2006.257.04:05:50.18#ibcon#read 3, iclass 19, count 2 2006.257.04:05:50.18#ibcon#about to read 4, iclass 19, count 2 2006.257.04:05:50.18#ibcon#read 4, iclass 19, count 2 2006.257.04:05:50.18#ibcon#about to read 5, iclass 19, count 2 2006.257.04:05:50.18#ibcon#read 5, iclass 19, count 2 2006.257.04:05:50.18#ibcon#about to read 6, iclass 19, count 2 2006.257.04:05:50.18#ibcon#read 6, iclass 19, count 2 2006.257.04:05:50.18#ibcon#end of sib2, iclass 19, count 2 2006.257.04:05:50.18#ibcon#*mode == 0, iclass 19, count 2 2006.257.04:05:50.18#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.04:05:50.18#ibcon#[27=AT04-05\r\n] 2006.257.04:05:50.18#ibcon#*before write, iclass 19, count 2 2006.257.04:05:50.18#ibcon#enter sib2, iclass 19, count 2 2006.257.04:05:50.18#ibcon#flushed, iclass 19, count 2 2006.257.04:05:50.18#ibcon#about to write, iclass 19, count 2 2006.257.04:05:50.18#ibcon#wrote, iclass 19, count 2 2006.257.04:05:50.18#ibcon#about to read 3, iclass 19, count 2 2006.257.04:05:50.21#ibcon#read 3, iclass 19, count 2 2006.257.04:05:50.21#ibcon#about to read 4, iclass 19, count 2 2006.257.04:05:50.21#ibcon#read 4, iclass 19, count 2 2006.257.04:05:50.21#ibcon#about to read 5, iclass 19, count 2 2006.257.04:05:50.21#ibcon#read 5, iclass 19, count 2 2006.257.04:05:50.21#ibcon#about to read 6, iclass 19, count 2 2006.257.04:05:50.21#ibcon#read 6, iclass 19, count 2 2006.257.04:05:50.21#ibcon#end of sib2, iclass 19, count 2 2006.257.04:05:50.21#ibcon#*after write, iclass 19, count 2 2006.257.04:05:50.21#ibcon#*before return 0, iclass 19, count 2 2006.257.04:05:50.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:50.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:05:50.21#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.04:05:50.21#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:50.21#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:50.33#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:50.33#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:50.33#ibcon#enter wrdev, iclass 19, count 0 2006.257.04:05:50.33#ibcon#first serial, iclass 19, count 0 2006.257.04:05:50.33#ibcon#enter sib2, iclass 19, count 0 2006.257.04:05:50.33#ibcon#flushed, iclass 19, count 0 2006.257.04:05:50.33#ibcon#about to write, iclass 19, count 0 2006.257.04:05:50.33#ibcon#wrote, iclass 19, count 0 2006.257.04:05:50.33#ibcon#about to read 3, iclass 19, count 0 2006.257.04:05:50.35#ibcon#read 3, iclass 19, count 0 2006.257.04:05:50.35#ibcon#about to read 4, iclass 19, count 0 2006.257.04:05:50.35#ibcon#read 4, iclass 19, count 0 2006.257.04:05:50.35#ibcon#about to read 5, iclass 19, count 0 2006.257.04:05:50.35#ibcon#read 5, iclass 19, count 0 2006.257.04:05:50.35#ibcon#about to read 6, iclass 19, count 0 2006.257.04:05:50.35#ibcon#read 6, iclass 19, count 0 2006.257.04:05:50.35#ibcon#end of sib2, iclass 19, count 0 2006.257.04:05:50.35#ibcon#*mode == 0, iclass 19, count 0 2006.257.04:05:50.35#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.04:05:50.35#ibcon#[27=USB\r\n] 2006.257.04:05:50.35#ibcon#*before write, iclass 19, count 0 2006.257.04:05:50.35#ibcon#enter sib2, iclass 19, count 0 2006.257.04:05:50.35#ibcon#flushed, iclass 19, count 0 2006.257.04:05:50.35#ibcon#about to write, iclass 19, count 0 2006.257.04:05:50.35#ibcon#wrote, iclass 19, count 0 2006.257.04:05:50.35#ibcon#about to read 3, iclass 19, count 0 2006.257.04:05:50.38#ibcon#read 3, iclass 19, count 0 2006.257.04:05:50.38#ibcon#about to read 4, iclass 19, count 0 2006.257.04:05:50.38#ibcon#read 4, iclass 19, count 0 2006.257.04:05:50.38#ibcon#about to read 5, iclass 19, count 0 2006.257.04:05:50.38#ibcon#read 5, iclass 19, count 0 2006.257.04:05:50.38#ibcon#about to read 6, iclass 19, count 0 2006.257.04:05:50.38#ibcon#read 6, iclass 19, count 0 2006.257.04:05:50.38#ibcon#end of sib2, iclass 19, count 0 2006.257.04:05:50.38#ibcon#*after write, iclass 19, count 0 2006.257.04:05:50.38#ibcon#*before return 0, iclass 19, count 0 2006.257.04:05:50.38#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:50.38#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:05:50.38#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.04:05:50.38#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.04:05:50.38$vck44/vblo=5,709.99 2006.257.04:05:50.38#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.04:05:50.38#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.04:05:50.38#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:50.38#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:50.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:50.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:50.38#ibcon#enter wrdev, iclass 21, count 0 2006.257.04:05:50.38#ibcon#first serial, iclass 21, count 0 2006.257.04:05:50.38#ibcon#enter sib2, iclass 21, count 0 2006.257.04:05:50.38#ibcon#flushed, iclass 21, count 0 2006.257.04:05:50.38#ibcon#about to write, iclass 21, count 0 2006.257.04:05:50.38#ibcon#wrote, iclass 21, count 0 2006.257.04:05:50.38#ibcon#about to read 3, iclass 21, count 0 2006.257.04:05:50.40#ibcon#read 3, iclass 21, count 0 2006.257.04:05:50.40#ibcon#about to read 4, iclass 21, count 0 2006.257.04:05:50.40#ibcon#read 4, iclass 21, count 0 2006.257.04:05:50.40#ibcon#about to read 5, iclass 21, count 0 2006.257.04:05:50.40#ibcon#read 5, iclass 21, count 0 2006.257.04:05:50.40#ibcon#about to read 6, iclass 21, count 0 2006.257.04:05:50.40#ibcon#read 6, iclass 21, count 0 2006.257.04:05:50.40#ibcon#end of sib2, iclass 21, count 0 2006.257.04:05:50.40#ibcon#*mode == 0, iclass 21, count 0 2006.257.04:05:50.40#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.04:05:50.40#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.04:05:50.40#ibcon#*before write, iclass 21, count 0 2006.257.04:05:50.40#ibcon#enter sib2, iclass 21, count 0 2006.257.04:05:50.40#ibcon#flushed, iclass 21, count 0 2006.257.04:05:50.40#ibcon#about to write, iclass 21, count 0 2006.257.04:05:50.40#ibcon#wrote, iclass 21, count 0 2006.257.04:05:50.40#ibcon#about to read 3, iclass 21, count 0 2006.257.04:05:50.44#ibcon#read 3, iclass 21, count 0 2006.257.04:05:50.44#ibcon#about to read 4, iclass 21, count 0 2006.257.04:05:50.44#ibcon#read 4, iclass 21, count 0 2006.257.04:05:50.44#ibcon#about to read 5, iclass 21, count 0 2006.257.04:05:50.44#ibcon#read 5, iclass 21, count 0 2006.257.04:05:50.44#ibcon#about to read 6, iclass 21, count 0 2006.257.04:05:50.44#ibcon#read 6, iclass 21, count 0 2006.257.04:05:50.44#ibcon#end of sib2, iclass 21, count 0 2006.257.04:05:50.44#ibcon#*after write, iclass 21, count 0 2006.257.04:05:50.44#ibcon#*before return 0, iclass 21, count 0 2006.257.04:05:50.44#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:50.44#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:05:50.44#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.04:05:50.44#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.04:05:50.44$vck44/vb=5,4 2006.257.04:05:50.44#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.04:05:50.44#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.04:05:50.44#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:50.44#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:50.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:50.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:50.50#ibcon#enter wrdev, iclass 23, count 2 2006.257.04:05:50.50#ibcon#first serial, iclass 23, count 2 2006.257.04:05:50.50#ibcon#enter sib2, iclass 23, count 2 2006.257.04:05:50.50#ibcon#flushed, iclass 23, count 2 2006.257.04:05:50.50#ibcon#about to write, iclass 23, count 2 2006.257.04:05:50.50#ibcon#wrote, iclass 23, count 2 2006.257.04:05:50.50#ibcon#about to read 3, iclass 23, count 2 2006.257.04:05:50.52#ibcon#read 3, iclass 23, count 2 2006.257.04:05:50.52#ibcon#about to read 4, iclass 23, count 2 2006.257.04:05:50.52#ibcon#read 4, iclass 23, count 2 2006.257.04:05:50.52#ibcon#about to read 5, iclass 23, count 2 2006.257.04:05:50.52#ibcon#read 5, iclass 23, count 2 2006.257.04:05:50.52#ibcon#about to read 6, iclass 23, count 2 2006.257.04:05:50.52#ibcon#read 6, iclass 23, count 2 2006.257.04:05:50.52#ibcon#end of sib2, iclass 23, count 2 2006.257.04:05:50.52#ibcon#*mode == 0, iclass 23, count 2 2006.257.04:05:50.52#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.04:05:50.52#ibcon#[27=AT05-04\r\n] 2006.257.04:05:50.52#ibcon#*before write, iclass 23, count 2 2006.257.04:05:50.52#ibcon#enter sib2, iclass 23, count 2 2006.257.04:05:50.52#ibcon#flushed, iclass 23, count 2 2006.257.04:05:50.52#ibcon#about to write, iclass 23, count 2 2006.257.04:05:50.52#ibcon#wrote, iclass 23, count 2 2006.257.04:05:50.52#ibcon#about to read 3, iclass 23, count 2 2006.257.04:05:50.55#ibcon#read 3, iclass 23, count 2 2006.257.04:05:50.55#ibcon#about to read 4, iclass 23, count 2 2006.257.04:05:50.55#ibcon#read 4, iclass 23, count 2 2006.257.04:05:50.55#ibcon#about to read 5, iclass 23, count 2 2006.257.04:05:50.55#ibcon#read 5, iclass 23, count 2 2006.257.04:05:50.55#ibcon#about to read 6, iclass 23, count 2 2006.257.04:05:50.55#ibcon#read 6, iclass 23, count 2 2006.257.04:05:50.55#ibcon#end of sib2, iclass 23, count 2 2006.257.04:05:50.55#ibcon#*after write, iclass 23, count 2 2006.257.04:05:50.55#ibcon#*before return 0, iclass 23, count 2 2006.257.04:05:50.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:50.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:05:50.55#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.04:05:50.55#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:50.55#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:50.67#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:50.67#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:50.67#ibcon#enter wrdev, iclass 23, count 0 2006.257.04:05:50.67#ibcon#first serial, iclass 23, count 0 2006.257.04:05:50.67#ibcon#enter sib2, iclass 23, count 0 2006.257.04:05:50.67#ibcon#flushed, iclass 23, count 0 2006.257.04:05:50.67#ibcon#about to write, iclass 23, count 0 2006.257.04:05:50.67#ibcon#wrote, iclass 23, count 0 2006.257.04:05:50.67#ibcon#about to read 3, iclass 23, count 0 2006.257.04:05:50.69#ibcon#read 3, iclass 23, count 0 2006.257.04:05:50.69#ibcon#about to read 4, iclass 23, count 0 2006.257.04:05:50.69#ibcon#read 4, iclass 23, count 0 2006.257.04:05:50.69#ibcon#about to read 5, iclass 23, count 0 2006.257.04:05:50.69#ibcon#read 5, iclass 23, count 0 2006.257.04:05:50.69#ibcon#about to read 6, iclass 23, count 0 2006.257.04:05:50.69#ibcon#read 6, iclass 23, count 0 2006.257.04:05:50.69#ibcon#end of sib2, iclass 23, count 0 2006.257.04:05:50.69#ibcon#*mode == 0, iclass 23, count 0 2006.257.04:05:50.69#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.04:05:50.69#ibcon#[27=USB\r\n] 2006.257.04:05:50.69#ibcon#*before write, iclass 23, count 0 2006.257.04:05:50.69#ibcon#enter sib2, iclass 23, count 0 2006.257.04:05:50.69#ibcon#flushed, iclass 23, count 0 2006.257.04:05:50.69#ibcon#about to write, iclass 23, count 0 2006.257.04:05:50.69#ibcon#wrote, iclass 23, count 0 2006.257.04:05:50.69#ibcon#about to read 3, iclass 23, count 0 2006.257.04:05:50.72#ibcon#read 3, iclass 23, count 0 2006.257.04:05:50.72#ibcon#about to read 4, iclass 23, count 0 2006.257.04:05:50.72#ibcon#read 4, iclass 23, count 0 2006.257.04:05:50.72#ibcon#about to read 5, iclass 23, count 0 2006.257.04:05:50.72#ibcon#read 5, iclass 23, count 0 2006.257.04:05:50.72#ibcon#about to read 6, iclass 23, count 0 2006.257.04:05:50.72#ibcon#read 6, iclass 23, count 0 2006.257.04:05:50.72#ibcon#end of sib2, iclass 23, count 0 2006.257.04:05:50.72#ibcon#*after write, iclass 23, count 0 2006.257.04:05:50.72#ibcon#*before return 0, iclass 23, count 0 2006.257.04:05:50.72#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:50.72#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:05:50.72#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.04:05:50.72#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.04:05:50.72$vck44/vblo=6,719.99 2006.257.04:05:50.72#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.04:05:50.72#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.04:05:50.72#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:50.72#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:50.72#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:50.72#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:50.72#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:05:50.72#ibcon#first serial, iclass 25, count 0 2006.257.04:05:50.72#ibcon#enter sib2, iclass 25, count 0 2006.257.04:05:50.72#ibcon#flushed, iclass 25, count 0 2006.257.04:05:50.72#ibcon#about to write, iclass 25, count 0 2006.257.04:05:50.72#ibcon#wrote, iclass 25, count 0 2006.257.04:05:50.72#ibcon#about to read 3, iclass 25, count 0 2006.257.04:05:50.74#ibcon#read 3, iclass 25, count 0 2006.257.04:05:50.74#ibcon#about to read 4, iclass 25, count 0 2006.257.04:05:50.74#ibcon#read 4, iclass 25, count 0 2006.257.04:05:50.74#ibcon#about to read 5, iclass 25, count 0 2006.257.04:05:50.74#ibcon#read 5, iclass 25, count 0 2006.257.04:05:50.74#ibcon#about to read 6, iclass 25, count 0 2006.257.04:05:50.74#ibcon#read 6, iclass 25, count 0 2006.257.04:05:50.74#ibcon#end of sib2, iclass 25, count 0 2006.257.04:05:50.74#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:05:50.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:05:50.74#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.04:05:50.74#ibcon#*before write, iclass 25, count 0 2006.257.04:05:50.74#ibcon#enter sib2, iclass 25, count 0 2006.257.04:05:50.74#ibcon#flushed, iclass 25, count 0 2006.257.04:05:50.74#ibcon#about to write, iclass 25, count 0 2006.257.04:05:50.74#ibcon#wrote, iclass 25, count 0 2006.257.04:05:50.74#ibcon#about to read 3, iclass 25, count 0 2006.257.04:05:50.78#ibcon#read 3, iclass 25, count 0 2006.257.04:05:50.78#ibcon#about to read 4, iclass 25, count 0 2006.257.04:05:50.78#ibcon#read 4, iclass 25, count 0 2006.257.04:05:50.78#ibcon#about to read 5, iclass 25, count 0 2006.257.04:05:50.78#ibcon#read 5, iclass 25, count 0 2006.257.04:05:50.78#ibcon#about to read 6, iclass 25, count 0 2006.257.04:05:50.78#ibcon#read 6, iclass 25, count 0 2006.257.04:05:50.78#ibcon#end of sib2, iclass 25, count 0 2006.257.04:05:50.78#ibcon#*after write, iclass 25, count 0 2006.257.04:05:50.78#ibcon#*before return 0, iclass 25, count 0 2006.257.04:05:50.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:50.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:05:50.78#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:05:50.78#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:05:50.78$vck44/vb=6,4 2006.257.04:05:50.78#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.04:05:50.78#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.04:05:50.78#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:50.78#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:50.84#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:50.84#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:50.84#ibcon#enter wrdev, iclass 27, count 2 2006.257.04:05:50.84#ibcon#first serial, iclass 27, count 2 2006.257.04:05:50.84#ibcon#enter sib2, iclass 27, count 2 2006.257.04:05:50.84#ibcon#flushed, iclass 27, count 2 2006.257.04:05:50.84#ibcon#about to write, iclass 27, count 2 2006.257.04:05:50.84#ibcon#wrote, iclass 27, count 2 2006.257.04:05:50.84#ibcon#about to read 3, iclass 27, count 2 2006.257.04:05:50.86#ibcon#read 3, iclass 27, count 2 2006.257.04:05:50.86#ibcon#about to read 4, iclass 27, count 2 2006.257.04:05:50.86#ibcon#read 4, iclass 27, count 2 2006.257.04:05:50.86#ibcon#about to read 5, iclass 27, count 2 2006.257.04:05:50.86#ibcon#read 5, iclass 27, count 2 2006.257.04:05:50.86#ibcon#about to read 6, iclass 27, count 2 2006.257.04:05:50.86#ibcon#read 6, iclass 27, count 2 2006.257.04:05:50.86#ibcon#end of sib2, iclass 27, count 2 2006.257.04:05:50.86#ibcon#*mode == 0, iclass 27, count 2 2006.257.04:05:50.86#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.04:05:50.86#ibcon#[27=AT06-04\r\n] 2006.257.04:05:50.86#ibcon#*before write, iclass 27, count 2 2006.257.04:05:50.86#ibcon#enter sib2, iclass 27, count 2 2006.257.04:05:50.86#ibcon#flushed, iclass 27, count 2 2006.257.04:05:50.86#ibcon#about to write, iclass 27, count 2 2006.257.04:05:50.86#ibcon#wrote, iclass 27, count 2 2006.257.04:05:50.86#ibcon#about to read 3, iclass 27, count 2 2006.257.04:05:50.89#ibcon#read 3, iclass 27, count 2 2006.257.04:05:50.89#ibcon#about to read 4, iclass 27, count 2 2006.257.04:05:50.89#ibcon#read 4, iclass 27, count 2 2006.257.04:05:50.89#ibcon#about to read 5, iclass 27, count 2 2006.257.04:05:50.89#ibcon#read 5, iclass 27, count 2 2006.257.04:05:50.89#ibcon#about to read 6, iclass 27, count 2 2006.257.04:05:50.89#ibcon#read 6, iclass 27, count 2 2006.257.04:05:50.89#ibcon#end of sib2, iclass 27, count 2 2006.257.04:05:50.89#ibcon#*after write, iclass 27, count 2 2006.257.04:05:50.89#ibcon#*before return 0, iclass 27, count 2 2006.257.04:05:50.89#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:50.89#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:05:50.89#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.04:05:50.89#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:50.89#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:51.01#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:51.01#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:51.01#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:05:51.01#ibcon#first serial, iclass 27, count 0 2006.257.04:05:51.01#ibcon#enter sib2, iclass 27, count 0 2006.257.04:05:51.01#ibcon#flushed, iclass 27, count 0 2006.257.04:05:51.01#ibcon#about to write, iclass 27, count 0 2006.257.04:05:51.01#ibcon#wrote, iclass 27, count 0 2006.257.04:05:51.01#ibcon#about to read 3, iclass 27, count 0 2006.257.04:05:51.03#ibcon#read 3, iclass 27, count 0 2006.257.04:05:51.03#ibcon#about to read 4, iclass 27, count 0 2006.257.04:05:51.03#ibcon#read 4, iclass 27, count 0 2006.257.04:05:51.03#ibcon#about to read 5, iclass 27, count 0 2006.257.04:05:51.03#ibcon#read 5, iclass 27, count 0 2006.257.04:05:51.03#ibcon#about to read 6, iclass 27, count 0 2006.257.04:05:51.03#ibcon#read 6, iclass 27, count 0 2006.257.04:05:51.03#ibcon#end of sib2, iclass 27, count 0 2006.257.04:05:51.03#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:05:51.03#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:05:51.03#ibcon#[27=USB\r\n] 2006.257.04:05:51.03#ibcon#*before write, iclass 27, count 0 2006.257.04:05:51.03#ibcon#enter sib2, iclass 27, count 0 2006.257.04:05:51.03#ibcon#flushed, iclass 27, count 0 2006.257.04:05:51.03#ibcon#about to write, iclass 27, count 0 2006.257.04:05:51.03#ibcon#wrote, iclass 27, count 0 2006.257.04:05:51.03#ibcon#about to read 3, iclass 27, count 0 2006.257.04:05:51.06#ibcon#read 3, iclass 27, count 0 2006.257.04:05:51.06#ibcon#about to read 4, iclass 27, count 0 2006.257.04:05:51.06#ibcon#read 4, iclass 27, count 0 2006.257.04:05:51.06#ibcon#about to read 5, iclass 27, count 0 2006.257.04:05:51.06#ibcon#read 5, iclass 27, count 0 2006.257.04:05:51.06#ibcon#about to read 6, iclass 27, count 0 2006.257.04:05:51.06#ibcon#read 6, iclass 27, count 0 2006.257.04:05:51.06#ibcon#end of sib2, iclass 27, count 0 2006.257.04:05:51.06#ibcon#*after write, iclass 27, count 0 2006.257.04:05:51.06#ibcon#*before return 0, iclass 27, count 0 2006.257.04:05:51.06#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:51.06#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:05:51.06#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:05:51.06#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:05:51.06$vck44/vblo=7,734.99 2006.257.04:05:51.06#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.04:05:51.06#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.04:05:51.06#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:51.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:51.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:51.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:51.06#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:05:51.06#ibcon#first serial, iclass 29, count 0 2006.257.04:05:51.06#ibcon#enter sib2, iclass 29, count 0 2006.257.04:05:51.06#ibcon#flushed, iclass 29, count 0 2006.257.04:05:51.06#ibcon#about to write, iclass 29, count 0 2006.257.04:05:51.06#ibcon#wrote, iclass 29, count 0 2006.257.04:05:51.06#ibcon#about to read 3, iclass 29, count 0 2006.257.04:05:51.08#ibcon#read 3, iclass 29, count 0 2006.257.04:05:51.08#ibcon#about to read 4, iclass 29, count 0 2006.257.04:05:51.08#ibcon#read 4, iclass 29, count 0 2006.257.04:05:51.08#ibcon#about to read 5, iclass 29, count 0 2006.257.04:05:51.08#ibcon#read 5, iclass 29, count 0 2006.257.04:05:51.08#ibcon#about to read 6, iclass 29, count 0 2006.257.04:05:51.08#ibcon#read 6, iclass 29, count 0 2006.257.04:05:51.08#ibcon#end of sib2, iclass 29, count 0 2006.257.04:05:51.08#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:05:51.08#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:05:51.08#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.04:05:51.08#ibcon#*before write, iclass 29, count 0 2006.257.04:05:51.08#ibcon#enter sib2, iclass 29, count 0 2006.257.04:05:51.08#ibcon#flushed, iclass 29, count 0 2006.257.04:05:51.08#ibcon#about to write, iclass 29, count 0 2006.257.04:05:51.08#ibcon#wrote, iclass 29, count 0 2006.257.04:05:51.08#ibcon#about to read 3, iclass 29, count 0 2006.257.04:05:51.12#ibcon#read 3, iclass 29, count 0 2006.257.04:05:51.12#ibcon#about to read 4, iclass 29, count 0 2006.257.04:05:51.12#ibcon#read 4, iclass 29, count 0 2006.257.04:05:51.12#ibcon#about to read 5, iclass 29, count 0 2006.257.04:05:51.12#ibcon#read 5, iclass 29, count 0 2006.257.04:05:51.12#ibcon#about to read 6, iclass 29, count 0 2006.257.04:05:51.12#ibcon#read 6, iclass 29, count 0 2006.257.04:05:51.12#ibcon#end of sib2, iclass 29, count 0 2006.257.04:05:51.12#ibcon#*after write, iclass 29, count 0 2006.257.04:05:51.12#ibcon#*before return 0, iclass 29, count 0 2006.257.04:05:51.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:51.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:05:51.12#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:05:51.12#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:05:51.12$vck44/vb=7,4 2006.257.04:05:51.12#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.04:05:51.12#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.04:05:51.12#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:51.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:51.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:51.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:51.18#ibcon#enter wrdev, iclass 31, count 2 2006.257.04:05:51.18#ibcon#first serial, iclass 31, count 2 2006.257.04:05:51.18#ibcon#enter sib2, iclass 31, count 2 2006.257.04:05:51.18#ibcon#flushed, iclass 31, count 2 2006.257.04:05:51.18#ibcon#about to write, iclass 31, count 2 2006.257.04:05:51.18#ibcon#wrote, iclass 31, count 2 2006.257.04:05:51.18#ibcon#about to read 3, iclass 31, count 2 2006.257.04:05:51.20#ibcon#read 3, iclass 31, count 2 2006.257.04:05:51.20#ibcon#about to read 4, iclass 31, count 2 2006.257.04:05:51.20#ibcon#read 4, iclass 31, count 2 2006.257.04:05:51.20#ibcon#about to read 5, iclass 31, count 2 2006.257.04:05:51.20#ibcon#read 5, iclass 31, count 2 2006.257.04:05:51.20#ibcon#about to read 6, iclass 31, count 2 2006.257.04:05:51.20#ibcon#read 6, iclass 31, count 2 2006.257.04:05:51.20#ibcon#end of sib2, iclass 31, count 2 2006.257.04:05:51.20#ibcon#*mode == 0, iclass 31, count 2 2006.257.04:05:51.20#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.04:05:51.20#ibcon#[27=AT07-04\r\n] 2006.257.04:05:51.20#ibcon#*before write, iclass 31, count 2 2006.257.04:05:51.20#ibcon#enter sib2, iclass 31, count 2 2006.257.04:05:51.20#ibcon#flushed, iclass 31, count 2 2006.257.04:05:51.20#ibcon#about to write, iclass 31, count 2 2006.257.04:05:51.20#ibcon#wrote, iclass 31, count 2 2006.257.04:05:51.20#ibcon#about to read 3, iclass 31, count 2 2006.257.04:05:51.23#ibcon#read 3, iclass 31, count 2 2006.257.04:05:51.23#ibcon#about to read 4, iclass 31, count 2 2006.257.04:05:51.23#ibcon#read 4, iclass 31, count 2 2006.257.04:05:51.23#ibcon#about to read 5, iclass 31, count 2 2006.257.04:05:51.23#ibcon#read 5, iclass 31, count 2 2006.257.04:05:51.23#ibcon#about to read 6, iclass 31, count 2 2006.257.04:05:51.23#ibcon#read 6, iclass 31, count 2 2006.257.04:05:51.23#ibcon#end of sib2, iclass 31, count 2 2006.257.04:05:51.23#ibcon#*after write, iclass 31, count 2 2006.257.04:05:51.23#ibcon#*before return 0, iclass 31, count 2 2006.257.04:05:51.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:51.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:05:51.23#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.04:05:51.23#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:51.23#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:51.35#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:51.35#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:51.35#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:05:51.35#ibcon#first serial, iclass 31, count 0 2006.257.04:05:51.35#ibcon#enter sib2, iclass 31, count 0 2006.257.04:05:51.35#ibcon#flushed, iclass 31, count 0 2006.257.04:05:51.35#ibcon#about to write, iclass 31, count 0 2006.257.04:05:51.35#ibcon#wrote, iclass 31, count 0 2006.257.04:05:51.35#ibcon#about to read 3, iclass 31, count 0 2006.257.04:05:51.37#ibcon#read 3, iclass 31, count 0 2006.257.04:05:51.37#ibcon#about to read 4, iclass 31, count 0 2006.257.04:05:51.37#ibcon#read 4, iclass 31, count 0 2006.257.04:05:51.37#ibcon#about to read 5, iclass 31, count 0 2006.257.04:05:51.37#ibcon#read 5, iclass 31, count 0 2006.257.04:05:51.37#ibcon#about to read 6, iclass 31, count 0 2006.257.04:05:51.37#ibcon#read 6, iclass 31, count 0 2006.257.04:05:51.37#ibcon#end of sib2, iclass 31, count 0 2006.257.04:05:51.37#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:05:51.37#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:05:51.37#ibcon#[27=USB\r\n] 2006.257.04:05:51.37#ibcon#*before write, iclass 31, count 0 2006.257.04:05:51.37#ibcon#enter sib2, iclass 31, count 0 2006.257.04:05:51.37#ibcon#flushed, iclass 31, count 0 2006.257.04:05:51.37#ibcon#about to write, iclass 31, count 0 2006.257.04:05:51.37#ibcon#wrote, iclass 31, count 0 2006.257.04:05:51.37#ibcon#about to read 3, iclass 31, count 0 2006.257.04:05:51.40#ibcon#read 3, iclass 31, count 0 2006.257.04:05:51.40#ibcon#about to read 4, iclass 31, count 0 2006.257.04:05:51.40#ibcon#read 4, iclass 31, count 0 2006.257.04:05:51.40#ibcon#about to read 5, iclass 31, count 0 2006.257.04:05:51.40#ibcon#read 5, iclass 31, count 0 2006.257.04:05:51.40#ibcon#about to read 6, iclass 31, count 0 2006.257.04:05:51.40#ibcon#read 6, iclass 31, count 0 2006.257.04:05:51.40#ibcon#end of sib2, iclass 31, count 0 2006.257.04:05:51.40#ibcon#*after write, iclass 31, count 0 2006.257.04:05:51.40#ibcon#*before return 0, iclass 31, count 0 2006.257.04:05:51.40#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:51.40#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:05:51.40#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:05:51.40#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:05:51.40$vck44/vblo=8,744.99 2006.257.04:05:51.40#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.04:05:51.40#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.04:05:51.40#ibcon#ireg 17 cls_cnt 0 2006.257.04:05:51.40#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:51.40#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:51.40#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:51.40#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:05:51.40#ibcon#first serial, iclass 33, count 0 2006.257.04:05:51.40#ibcon#enter sib2, iclass 33, count 0 2006.257.04:05:51.40#ibcon#flushed, iclass 33, count 0 2006.257.04:05:51.40#ibcon#about to write, iclass 33, count 0 2006.257.04:05:51.40#ibcon#wrote, iclass 33, count 0 2006.257.04:05:51.40#ibcon#about to read 3, iclass 33, count 0 2006.257.04:05:51.42#ibcon#read 3, iclass 33, count 0 2006.257.04:05:51.42#ibcon#about to read 4, iclass 33, count 0 2006.257.04:05:51.42#ibcon#read 4, iclass 33, count 0 2006.257.04:05:51.42#ibcon#about to read 5, iclass 33, count 0 2006.257.04:05:51.42#ibcon#read 5, iclass 33, count 0 2006.257.04:05:51.42#ibcon#about to read 6, iclass 33, count 0 2006.257.04:05:51.42#ibcon#read 6, iclass 33, count 0 2006.257.04:05:51.42#ibcon#end of sib2, iclass 33, count 0 2006.257.04:05:51.42#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:05:51.42#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:05:51.42#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.04:05:51.42#ibcon#*before write, iclass 33, count 0 2006.257.04:05:51.42#ibcon#enter sib2, iclass 33, count 0 2006.257.04:05:51.42#ibcon#flushed, iclass 33, count 0 2006.257.04:05:51.42#ibcon#about to write, iclass 33, count 0 2006.257.04:05:51.42#ibcon#wrote, iclass 33, count 0 2006.257.04:05:51.42#ibcon#about to read 3, iclass 33, count 0 2006.257.04:05:51.46#ibcon#read 3, iclass 33, count 0 2006.257.04:05:51.46#ibcon#about to read 4, iclass 33, count 0 2006.257.04:05:51.46#ibcon#read 4, iclass 33, count 0 2006.257.04:05:51.46#ibcon#about to read 5, iclass 33, count 0 2006.257.04:05:51.46#ibcon#read 5, iclass 33, count 0 2006.257.04:05:51.46#ibcon#about to read 6, iclass 33, count 0 2006.257.04:05:51.46#ibcon#read 6, iclass 33, count 0 2006.257.04:05:51.46#ibcon#end of sib2, iclass 33, count 0 2006.257.04:05:51.46#ibcon#*after write, iclass 33, count 0 2006.257.04:05:51.46#ibcon#*before return 0, iclass 33, count 0 2006.257.04:05:51.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:51.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:05:51.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:05:51.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:05:51.46$vck44/vb=8,4 2006.257.04:05:51.46#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.04:05:51.46#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.04:05:51.46#ibcon#ireg 11 cls_cnt 2 2006.257.04:05:51.46#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:51.52#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:51.52#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:51.52#ibcon#enter wrdev, iclass 35, count 2 2006.257.04:05:51.52#ibcon#first serial, iclass 35, count 2 2006.257.04:05:51.52#ibcon#enter sib2, iclass 35, count 2 2006.257.04:05:51.52#ibcon#flushed, iclass 35, count 2 2006.257.04:05:51.52#ibcon#about to write, iclass 35, count 2 2006.257.04:05:51.52#ibcon#wrote, iclass 35, count 2 2006.257.04:05:51.52#ibcon#about to read 3, iclass 35, count 2 2006.257.04:05:51.54#ibcon#read 3, iclass 35, count 2 2006.257.04:05:51.54#ibcon#about to read 4, iclass 35, count 2 2006.257.04:05:51.54#ibcon#read 4, iclass 35, count 2 2006.257.04:05:51.54#ibcon#about to read 5, iclass 35, count 2 2006.257.04:05:51.54#ibcon#read 5, iclass 35, count 2 2006.257.04:05:51.54#ibcon#about to read 6, iclass 35, count 2 2006.257.04:05:51.54#ibcon#read 6, iclass 35, count 2 2006.257.04:05:51.54#ibcon#end of sib2, iclass 35, count 2 2006.257.04:05:51.54#ibcon#*mode == 0, iclass 35, count 2 2006.257.04:05:51.54#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.04:05:51.54#ibcon#[27=AT08-04\r\n] 2006.257.04:05:51.54#ibcon#*before write, iclass 35, count 2 2006.257.04:05:51.54#ibcon#enter sib2, iclass 35, count 2 2006.257.04:05:51.54#ibcon#flushed, iclass 35, count 2 2006.257.04:05:51.54#ibcon#about to write, iclass 35, count 2 2006.257.04:05:51.54#ibcon#wrote, iclass 35, count 2 2006.257.04:05:51.54#ibcon#about to read 3, iclass 35, count 2 2006.257.04:05:51.57#ibcon#read 3, iclass 35, count 2 2006.257.04:05:51.57#ibcon#about to read 4, iclass 35, count 2 2006.257.04:05:51.57#ibcon#read 4, iclass 35, count 2 2006.257.04:05:51.57#ibcon#about to read 5, iclass 35, count 2 2006.257.04:05:51.57#ibcon#read 5, iclass 35, count 2 2006.257.04:05:51.57#ibcon#about to read 6, iclass 35, count 2 2006.257.04:05:51.57#ibcon#read 6, iclass 35, count 2 2006.257.04:05:51.57#ibcon#end of sib2, iclass 35, count 2 2006.257.04:05:51.57#ibcon#*after write, iclass 35, count 2 2006.257.04:05:51.57#ibcon#*before return 0, iclass 35, count 2 2006.257.04:05:51.57#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:51.57#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:05:51.57#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.04:05:51.57#ibcon#ireg 7 cls_cnt 0 2006.257.04:05:51.57#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:51.69#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:51.69#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:51.69#ibcon#enter wrdev, iclass 35, count 0 2006.257.04:05:51.69#ibcon#first serial, iclass 35, count 0 2006.257.04:05:51.69#ibcon#enter sib2, iclass 35, count 0 2006.257.04:05:51.69#ibcon#flushed, iclass 35, count 0 2006.257.04:05:51.69#ibcon#about to write, iclass 35, count 0 2006.257.04:05:51.69#ibcon#wrote, iclass 35, count 0 2006.257.04:05:51.69#ibcon#about to read 3, iclass 35, count 0 2006.257.04:05:51.71#ibcon#read 3, iclass 35, count 0 2006.257.04:05:51.71#ibcon#about to read 4, iclass 35, count 0 2006.257.04:05:51.71#ibcon#read 4, iclass 35, count 0 2006.257.04:05:51.71#ibcon#about to read 5, iclass 35, count 0 2006.257.04:05:51.71#ibcon#read 5, iclass 35, count 0 2006.257.04:05:51.71#ibcon#about to read 6, iclass 35, count 0 2006.257.04:05:51.71#ibcon#read 6, iclass 35, count 0 2006.257.04:05:51.71#ibcon#end of sib2, iclass 35, count 0 2006.257.04:05:51.71#ibcon#*mode == 0, iclass 35, count 0 2006.257.04:05:51.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.04:05:51.71#ibcon#[27=USB\r\n] 2006.257.04:05:51.71#ibcon#*before write, iclass 35, count 0 2006.257.04:05:51.71#ibcon#enter sib2, iclass 35, count 0 2006.257.04:05:51.71#ibcon#flushed, iclass 35, count 0 2006.257.04:05:51.71#ibcon#about to write, iclass 35, count 0 2006.257.04:05:51.71#ibcon#wrote, iclass 35, count 0 2006.257.04:05:51.71#ibcon#about to read 3, iclass 35, count 0 2006.257.04:05:51.74#ibcon#read 3, iclass 35, count 0 2006.257.04:05:51.74#ibcon#about to read 4, iclass 35, count 0 2006.257.04:05:51.74#ibcon#read 4, iclass 35, count 0 2006.257.04:05:51.74#ibcon#about to read 5, iclass 35, count 0 2006.257.04:05:51.74#ibcon#read 5, iclass 35, count 0 2006.257.04:05:51.74#ibcon#about to read 6, iclass 35, count 0 2006.257.04:05:51.74#ibcon#read 6, iclass 35, count 0 2006.257.04:05:51.74#ibcon#end of sib2, iclass 35, count 0 2006.257.04:05:51.74#ibcon#*after write, iclass 35, count 0 2006.257.04:05:51.74#ibcon#*before return 0, iclass 35, count 0 2006.257.04:05:51.74#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:51.74#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:05:51.74#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.04:05:51.74#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.04:05:51.74$vck44/vabw=wide 2006.257.04:05:51.74#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.04:05:51.74#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.04:05:51.74#ibcon#ireg 8 cls_cnt 0 2006.257.04:05:51.74#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:51.74#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:51.74#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:51.74#ibcon#enter wrdev, iclass 37, count 0 2006.257.04:05:51.74#ibcon#first serial, iclass 37, count 0 2006.257.04:05:51.74#ibcon#enter sib2, iclass 37, count 0 2006.257.04:05:51.74#ibcon#flushed, iclass 37, count 0 2006.257.04:05:51.74#ibcon#about to write, iclass 37, count 0 2006.257.04:05:51.74#ibcon#wrote, iclass 37, count 0 2006.257.04:05:51.74#ibcon#about to read 3, iclass 37, count 0 2006.257.04:05:51.76#ibcon#read 3, iclass 37, count 0 2006.257.04:05:51.76#ibcon#about to read 4, iclass 37, count 0 2006.257.04:05:51.76#ibcon#read 4, iclass 37, count 0 2006.257.04:05:51.76#ibcon#about to read 5, iclass 37, count 0 2006.257.04:05:51.76#ibcon#read 5, iclass 37, count 0 2006.257.04:05:51.76#ibcon#about to read 6, iclass 37, count 0 2006.257.04:05:51.76#ibcon#read 6, iclass 37, count 0 2006.257.04:05:51.76#ibcon#end of sib2, iclass 37, count 0 2006.257.04:05:51.76#ibcon#*mode == 0, iclass 37, count 0 2006.257.04:05:51.76#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.04:05:51.76#ibcon#[25=BW32\r\n] 2006.257.04:05:51.76#ibcon#*before write, iclass 37, count 0 2006.257.04:05:51.76#ibcon#enter sib2, iclass 37, count 0 2006.257.04:05:51.76#ibcon#flushed, iclass 37, count 0 2006.257.04:05:51.76#ibcon#about to write, iclass 37, count 0 2006.257.04:05:51.76#ibcon#wrote, iclass 37, count 0 2006.257.04:05:51.76#ibcon#about to read 3, iclass 37, count 0 2006.257.04:05:51.79#ibcon#read 3, iclass 37, count 0 2006.257.04:05:51.79#ibcon#about to read 4, iclass 37, count 0 2006.257.04:05:51.79#ibcon#read 4, iclass 37, count 0 2006.257.04:05:51.79#ibcon#about to read 5, iclass 37, count 0 2006.257.04:05:51.79#ibcon#read 5, iclass 37, count 0 2006.257.04:05:51.79#ibcon#about to read 6, iclass 37, count 0 2006.257.04:05:51.79#ibcon#read 6, iclass 37, count 0 2006.257.04:05:51.79#ibcon#end of sib2, iclass 37, count 0 2006.257.04:05:51.79#ibcon#*after write, iclass 37, count 0 2006.257.04:05:51.79#ibcon#*before return 0, iclass 37, count 0 2006.257.04:05:51.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:51.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:05:51.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.04:05:51.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.04:05:51.79$vck44/vbbw=wide 2006.257.04:05:51.79#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.04:05:51.79#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.04:05:51.79#ibcon#ireg 8 cls_cnt 0 2006.257.04:05:51.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:05:51.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:05:51.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:05:51.86#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:05:51.86#ibcon#first serial, iclass 39, count 0 2006.257.04:05:51.86#ibcon#enter sib2, iclass 39, count 0 2006.257.04:05:51.86#ibcon#flushed, iclass 39, count 0 2006.257.04:05:51.86#ibcon#about to write, iclass 39, count 0 2006.257.04:05:51.86#ibcon#wrote, iclass 39, count 0 2006.257.04:05:51.86#ibcon#about to read 3, iclass 39, count 0 2006.257.04:05:51.88#ibcon#read 3, iclass 39, count 0 2006.257.04:05:51.88#ibcon#about to read 4, iclass 39, count 0 2006.257.04:05:51.88#ibcon#read 4, iclass 39, count 0 2006.257.04:05:51.88#ibcon#about to read 5, iclass 39, count 0 2006.257.04:05:51.88#ibcon#read 5, iclass 39, count 0 2006.257.04:05:51.88#ibcon#about to read 6, iclass 39, count 0 2006.257.04:05:51.88#ibcon#read 6, iclass 39, count 0 2006.257.04:05:51.88#ibcon#end of sib2, iclass 39, count 0 2006.257.04:05:51.88#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:05:51.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:05:51.88#ibcon#[27=BW32\r\n] 2006.257.04:05:51.88#ibcon#*before write, iclass 39, count 0 2006.257.04:05:51.88#ibcon#enter sib2, iclass 39, count 0 2006.257.04:05:51.88#ibcon#flushed, iclass 39, count 0 2006.257.04:05:51.88#ibcon#about to write, iclass 39, count 0 2006.257.04:05:51.88#ibcon#wrote, iclass 39, count 0 2006.257.04:05:51.88#ibcon#about to read 3, iclass 39, count 0 2006.257.04:05:51.91#ibcon#read 3, iclass 39, count 0 2006.257.04:05:51.91#ibcon#about to read 4, iclass 39, count 0 2006.257.04:05:51.91#ibcon#read 4, iclass 39, count 0 2006.257.04:05:51.91#ibcon#about to read 5, iclass 39, count 0 2006.257.04:05:51.91#ibcon#read 5, iclass 39, count 0 2006.257.04:05:51.91#ibcon#about to read 6, iclass 39, count 0 2006.257.04:05:51.91#ibcon#read 6, iclass 39, count 0 2006.257.04:05:51.91#ibcon#end of sib2, iclass 39, count 0 2006.257.04:05:51.91#ibcon#*after write, iclass 39, count 0 2006.257.04:05:51.91#ibcon#*before return 0, iclass 39, count 0 2006.257.04:05:51.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:05:51.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:05:51.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:05:51.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:05:51.91$setupk4/ifdk4 2006.257.04:05:51.91$ifdk4/lo= 2006.257.04:05:51.91$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.04:05:51.91$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.04:05:51.91$ifdk4/patch= 2006.257.04:05:51.91$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.04:05:51.91$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.04:05:51.91$setupk4/!*+20s 2006.257.04:05:59.77#abcon#<5=/14 2.3 5.8 19.26 951011.9\r\n> 2006.257.04:05:59.79#abcon#{5=INTERFACE CLEAR} 2006.257.04:05:59.85#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:06:01.14#trakl#Source acquired 2006.257.04:06:03.14#flagr#flagr/antenna,acquired 2006.257.04:06:06.42$setupk4/"tpicd 2006.257.04:06:06.42$setupk4/echo=off 2006.257.04:06:06.42$setupk4/xlog=off 2006.257.04:06:06.42:!2006.257.04:09:02 2006.257.04:09:02.00:preob 2006.257.04:09:02.13/onsource/TRACKING 2006.257.04:09:02.13:!2006.257.04:09:12 2006.257.04:09:12.00:"tape 2006.257.04:09:12.00:"st=record 2006.257.04:09:12.00:data_valid=on 2006.257.04:09:12.00:midob 2006.257.04:09:12.13/onsource/TRACKING 2006.257.04:09:12.13/wx/19.33,1011.9,94 2006.257.04:09:12.28/cable/+6.4830E-03 2006.257.04:09:13.37/va/01,08,usb,yes,31,34 2006.257.04:09:13.37/va/02,07,usb,yes,34,35 2006.257.04:09:13.37/va/03,08,usb,yes,31,32 2006.257.04:09:13.37/va/04,07,usb,yes,35,37 2006.257.04:09:13.37/va/05,04,usb,yes,32,32 2006.257.04:09:13.37/va/06,04,usb,yes,35,35 2006.257.04:09:13.37/va/07,04,usb,yes,36,36 2006.257.04:09:13.37/va/08,04,usb,yes,30,37 2006.257.04:09:13.60/valo/01,524.99,yes,locked 2006.257.04:09:13.60/valo/02,534.99,yes,locked 2006.257.04:09:13.60/valo/03,564.99,yes,locked 2006.257.04:09:13.60/valo/04,624.99,yes,locked 2006.257.04:09:13.60/valo/05,734.99,yes,locked 2006.257.04:09:13.60/valo/06,814.99,yes,locked 2006.257.04:09:13.60/valo/07,864.99,yes,locked 2006.257.04:09:13.60/valo/08,884.99,yes,locked 2006.257.04:09:14.69/vb/01,04,usb,yes,31,28 2006.257.04:09:14.69/vb/02,05,usb,yes,29,29 2006.257.04:09:14.69/vb/03,04,usb,yes,30,33 2006.257.04:09:14.69/vb/04,05,usb,yes,30,29 2006.257.04:09:14.69/vb/05,04,usb,yes,27,29 2006.257.04:09:14.69/vb/06,04,usb,yes,31,27 2006.257.04:09:14.69/vb/07,04,usb,yes,31,31 2006.257.04:09:14.69/vb/08,04,usb,yes,28,32 2006.257.04:09:14.92/vblo/01,629.99,yes,locked 2006.257.04:09:14.92/vblo/02,634.99,yes,locked 2006.257.04:09:14.92/vblo/03,649.99,yes,locked 2006.257.04:09:14.92/vblo/04,679.99,yes,locked 2006.257.04:09:14.92/vblo/05,709.99,yes,locked 2006.257.04:09:14.92/vblo/06,719.99,yes,locked 2006.257.04:09:14.92/vblo/07,734.99,yes,locked 2006.257.04:09:14.92/vblo/08,744.99,yes,locked 2006.257.04:09:15.07/vabw/8 2006.257.04:09:15.22/vbbw/8 2006.257.04:09:15.31/xfe/off,on,16.7 2006.257.04:09:15.68/ifatt/23,28,28,28 2006.257.04:09:16.08/fmout-gps/S +4.55E-07 2006.257.04:09:16.12:!2006.257.04:12:42 2006.257.04:12:42.00:data_valid=off 2006.257.04:12:42.00:"et 2006.257.04:12:42.00:!+3s 2006.257.04:12:45.01:"tape 2006.257.04:12:45.01:postob 2006.257.04:12:45.19/cable/+6.4835E-03 2006.257.04:12:45.19/wx/19.31,1011.9,94 2006.257.04:12:46.08/fmout-gps/S +4.57E-07 2006.257.04:12:46.08:scan_name=257-0416,jd0609,320 2006.257.04:12:46.08:source=oj287,085448.87,200630.6,2000.0,ccw 2006.257.04:12:46.14#flagr#flagr/antenna,new-source 2006.257.04:12:47.14:checkk5 2006.257.04:12:47.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.04:12:47.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.04:12:48.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.04:12:48.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.04:12:49.15/chk_obsdata//k5ts1/T2570409??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.04:12:49.59/chk_obsdata//k5ts2/T2570409??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.04:12:50.01/chk_obsdata//k5ts3/T2570409??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.04:12:50.41/chk_obsdata//k5ts4/T2570409??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.04:12:51.14/k5log//k5ts1_log_newline 2006.257.04:12:51.86/k5log//k5ts2_log_newline 2006.257.04:12:52.60/k5log//k5ts3_log_newline 2006.257.04:12:53.31/k5log//k5ts4_log_newline 2006.257.04:12:53.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.04:12:53.33:setupk4=1 2006.257.04:12:53.33$setupk4/echo=on 2006.257.04:12:53.33$setupk4/pcalon 2006.257.04:12:53.33$pcalon/"no phase cal control is implemented here 2006.257.04:12:53.33$setupk4/"tpicd=stop 2006.257.04:12:53.33$setupk4/"rec=synch_on 2006.257.04:12:53.33$setupk4/"rec_mode=128 2006.257.04:12:53.33$setupk4/!* 2006.257.04:12:53.33$setupk4/recpk4 2006.257.04:12:53.33$recpk4/recpatch= 2006.257.04:12:53.34$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.04:12:53.34$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.04:12:53.34$setupk4/vck44 2006.257.04:12:53.34$vck44/valo=1,524.99 2006.257.04:12:53.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.04:12:53.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.04:12:53.34#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:53.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:53.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:53.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:53.34#ibcon#enter wrdev, iclass 28, count 0 2006.257.04:12:53.34#ibcon#first serial, iclass 28, count 0 2006.257.04:12:53.34#ibcon#enter sib2, iclass 28, count 0 2006.257.04:12:53.34#ibcon#flushed, iclass 28, count 0 2006.257.04:12:53.34#ibcon#about to write, iclass 28, count 0 2006.257.04:12:53.34#ibcon#wrote, iclass 28, count 0 2006.257.04:12:53.34#ibcon#about to read 3, iclass 28, count 0 2006.257.04:12:53.36#ibcon#read 3, iclass 28, count 0 2006.257.04:12:53.36#ibcon#about to read 4, iclass 28, count 0 2006.257.04:12:53.36#ibcon#read 4, iclass 28, count 0 2006.257.04:12:53.36#ibcon#about to read 5, iclass 28, count 0 2006.257.04:12:53.36#ibcon#read 5, iclass 28, count 0 2006.257.04:12:53.36#ibcon#about to read 6, iclass 28, count 0 2006.257.04:12:53.36#ibcon#read 6, iclass 28, count 0 2006.257.04:12:53.36#ibcon#end of sib2, iclass 28, count 0 2006.257.04:12:53.36#ibcon#*mode == 0, iclass 28, count 0 2006.257.04:12:53.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.04:12:53.36#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.04:12:53.36#ibcon#*before write, iclass 28, count 0 2006.257.04:12:53.36#ibcon#enter sib2, iclass 28, count 0 2006.257.04:12:53.36#ibcon#flushed, iclass 28, count 0 2006.257.04:12:53.36#ibcon#about to write, iclass 28, count 0 2006.257.04:12:53.36#ibcon#wrote, iclass 28, count 0 2006.257.04:12:53.36#ibcon#about to read 3, iclass 28, count 0 2006.257.04:12:53.41#ibcon#read 3, iclass 28, count 0 2006.257.04:12:53.41#ibcon#about to read 4, iclass 28, count 0 2006.257.04:12:53.41#ibcon#read 4, iclass 28, count 0 2006.257.04:12:53.41#ibcon#about to read 5, iclass 28, count 0 2006.257.04:12:53.41#ibcon#read 5, iclass 28, count 0 2006.257.04:12:53.41#ibcon#about to read 6, iclass 28, count 0 2006.257.04:12:53.41#ibcon#read 6, iclass 28, count 0 2006.257.04:12:53.41#ibcon#end of sib2, iclass 28, count 0 2006.257.04:12:53.41#ibcon#*after write, iclass 28, count 0 2006.257.04:12:53.41#ibcon#*before return 0, iclass 28, count 0 2006.257.04:12:53.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:53.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:53.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.04:12:53.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.04:12:53.41$vck44/va=1,8 2006.257.04:12:53.41#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.04:12:53.41#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.04:12:53.41#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:53.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:53.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:53.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:53.41#ibcon#enter wrdev, iclass 30, count 2 2006.257.04:12:53.41#ibcon#first serial, iclass 30, count 2 2006.257.04:12:53.41#ibcon#enter sib2, iclass 30, count 2 2006.257.04:12:53.41#ibcon#flushed, iclass 30, count 2 2006.257.04:12:53.41#ibcon#about to write, iclass 30, count 2 2006.257.04:12:53.41#ibcon#wrote, iclass 30, count 2 2006.257.04:12:53.41#ibcon#about to read 3, iclass 30, count 2 2006.257.04:12:53.43#ibcon#read 3, iclass 30, count 2 2006.257.04:12:53.43#ibcon#about to read 4, iclass 30, count 2 2006.257.04:12:53.43#ibcon#read 4, iclass 30, count 2 2006.257.04:12:53.43#ibcon#about to read 5, iclass 30, count 2 2006.257.04:12:53.43#ibcon#read 5, iclass 30, count 2 2006.257.04:12:53.43#ibcon#about to read 6, iclass 30, count 2 2006.257.04:12:53.43#ibcon#read 6, iclass 30, count 2 2006.257.04:12:53.43#ibcon#end of sib2, iclass 30, count 2 2006.257.04:12:53.43#ibcon#*mode == 0, iclass 30, count 2 2006.257.04:12:53.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.04:12:53.43#ibcon#[25=AT01-08\r\n] 2006.257.04:12:53.43#ibcon#*before write, iclass 30, count 2 2006.257.04:12:53.43#ibcon#enter sib2, iclass 30, count 2 2006.257.04:12:53.43#ibcon#flushed, iclass 30, count 2 2006.257.04:12:53.43#ibcon#about to write, iclass 30, count 2 2006.257.04:12:53.43#ibcon#wrote, iclass 30, count 2 2006.257.04:12:53.43#ibcon#about to read 3, iclass 30, count 2 2006.257.04:12:53.46#ibcon#read 3, iclass 30, count 2 2006.257.04:12:53.46#ibcon#about to read 4, iclass 30, count 2 2006.257.04:12:53.46#ibcon#read 4, iclass 30, count 2 2006.257.04:12:53.46#ibcon#about to read 5, iclass 30, count 2 2006.257.04:12:53.46#ibcon#read 5, iclass 30, count 2 2006.257.04:12:53.46#ibcon#about to read 6, iclass 30, count 2 2006.257.04:12:53.46#ibcon#read 6, iclass 30, count 2 2006.257.04:12:53.46#ibcon#end of sib2, iclass 30, count 2 2006.257.04:12:53.46#ibcon#*after write, iclass 30, count 2 2006.257.04:12:53.46#ibcon#*before return 0, iclass 30, count 2 2006.257.04:12:53.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:53.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:53.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.04:12:53.46#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:53.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:53.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:53.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:53.58#ibcon#enter wrdev, iclass 30, count 0 2006.257.04:12:53.58#ibcon#first serial, iclass 30, count 0 2006.257.04:12:53.58#ibcon#enter sib2, iclass 30, count 0 2006.257.04:12:53.58#ibcon#flushed, iclass 30, count 0 2006.257.04:12:53.58#ibcon#about to write, iclass 30, count 0 2006.257.04:12:53.58#ibcon#wrote, iclass 30, count 0 2006.257.04:12:53.58#ibcon#about to read 3, iclass 30, count 0 2006.257.04:12:53.60#ibcon#read 3, iclass 30, count 0 2006.257.04:12:53.60#ibcon#about to read 4, iclass 30, count 0 2006.257.04:12:53.60#ibcon#read 4, iclass 30, count 0 2006.257.04:12:53.60#ibcon#about to read 5, iclass 30, count 0 2006.257.04:12:53.60#ibcon#read 5, iclass 30, count 0 2006.257.04:12:53.60#ibcon#about to read 6, iclass 30, count 0 2006.257.04:12:53.60#ibcon#read 6, iclass 30, count 0 2006.257.04:12:53.60#ibcon#end of sib2, iclass 30, count 0 2006.257.04:12:53.60#ibcon#*mode == 0, iclass 30, count 0 2006.257.04:12:53.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.04:12:53.60#ibcon#[25=USB\r\n] 2006.257.04:12:53.60#ibcon#*before write, iclass 30, count 0 2006.257.04:12:53.60#ibcon#enter sib2, iclass 30, count 0 2006.257.04:12:53.60#ibcon#flushed, iclass 30, count 0 2006.257.04:12:53.60#ibcon#about to write, iclass 30, count 0 2006.257.04:12:53.60#ibcon#wrote, iclass 30, count 0 2006.257.04:12:53.60#ibcon#about to read 3, iclass 30, count 0 2006.257.04:12:53.63#ibcon#read 3, iclass 30, count 0 2006.257.04:12:53.63#ibcon#about to read 4, iclass 30, count 0 2006.257.04:12:53.63#ibcon#read 4, iclass 30, count 0 2006.257.04:12:53.63#ibcon#about to read 5, iclass 30, count 0 2006.257.04:12:53.63#ibcon#read 5, iclass 30, count 0 2006.257.04:12:53.63#ibcon#about to read 6, iclass 30, count 0 2006.257.04:12:53.63#ibcon#read 6, iclass 30, count 0 2006.257.04:12:53.63#ibcon#end of sib2, iclass 30, count 0 2006.257.04:12:53.63#ibcon#*after write, iclass 30, count 0 2006.257.04:12:53.63#ibcon#*before return 0, iclass 30, count 0 2006.257.04:12:53.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:53.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:53.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.04:12:53.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.04:12:53.63$vck44/valo=2,534.99 2006.257.04:12:53.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.04:12:53.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.04:12:53.63#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:53.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:53.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:53.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:53.63#ibcon#enter wrdev, iclass 32, count 0 2006.257.04:12:53.63#ibcon#first serial, iclass 32, count 0 2006.257.04:12:53.63#ibcon#enter sib2, iclass 32, count 0 2006.257.04:12:53.63#ibcon#flushed, iclass 32, count 0 2006.257.04:12:53.63#ibcon#about to write, iclass 32, count 0 2006.257.04:12:53.63#ibcon#wrote, iclass 32, count 0 2006.257.04:12:53.63#ibcon#about to read 3, iclass 32, count 0 2006.257.04:12:53.65#ibcon#read 3, iclass 32, count 0 2006.257.04:12:53.65#ibcon#about to read 4, iclass 32, count 0 2006.257.04:12:53.65#ibcon#read 4, iclass 32, count 0 2006.257.04:12:53.65#ibcon#about to read 5, iclass 32, count 0 2006.257.04:12:53.65#ibcon#read 5, iclass 32, count 0 2006.257.04:12:53.65#ibcon#about to read 6, iclass 32, count 0 2006.257.04:12:53.65#ibcon#read 6, iclass 32, count 0 2006.257.04:12:53.65#ibcon#end of sib2, iclass 32, count 0 2006.257.04:12:53.65#ibcon#*mode == 0, iclass 32, count 0 2006.257.04:12:53.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.04:12:53.65#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.04:12:53.65#ibcon#*before write, iclass 32, count 0 2006.257.04:12:53.65#ibcon#enter sib2, iclass 32, count 0 2006.257.04:12:53.65#ibcon#flushed, iclass 32, count 0 2006.257.04:12:53.65#ibcon#about to write, iclass 32, count 0 2006.257.04:12:53.65#ibcon#wrote, iclass 32, count 0 2006.257.04:12:53.65#ibcon#about to read 3, iclass 32, count 0 2006.257.04:12:53.69#ibcon#read 3, iclass 32, count 0 2006.257.04:12:53.69#ibcon#about to read 4, iclass 32, count 0 2006.257.04:12:53.69#ibcon#read 4, iclass 32, count 0 2006.257.04:12:53.69#ibcon#about to read 5, iclass 32, count 0 2006.257.04:12:53.69#ibcon#read 5, iclass 32, count 0 2006.257.04:12:53.69#ibcon#about to read 6, iclass 32, count 0 2006.257.04:12:53.69#ibcon#read 6, iclass 32, count 0 2006.257.04:12:53.69#ibcon#end of sib2, iclass 32, count 0 2006.257.04:12:53.69#ibcon#*after write, iclass 32, count 0 2006.257.04:12:53.69#ibcon#*before return 0, iclass 32, count 0 2006.257.04:12:53.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:53.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:53.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.04:12:53.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.04:12:53.69$vck44/va=2,7 2006.257.04:12:53.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.04:12:53.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.04:12:53.69#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:53.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:53.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:53.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:53.75#ibcon#enter wrdev, iclass 34, count 2 2006.257.04:12:53.75#ibcon#first serial, iclass 34, count 2 2006.257.04:12:53.75#ibcon#enter sib2, iclass 34, count 2 2006.257.04:12:53.75#ibcon#flushed, iclass 34, count 2 2006.257.04:12:53.75#ibcon#about to write, iclass 34, count 2 2006.257.04:12:53.75#ibcon#wrote, iclass 34, count 2 2006.257.04:12:53.75#ibcon#about to read 3, iclass 34, count 2 2006.257.04:12:53.77#ibcon#read 3, iclass 34, count 2 2006.257.04:12:53.77#ibcon#about to read 4, iclass 34, count 2 2006.257.04:12:53.77#ibcon#read 4, iclass 34, count 2 2006.257.04:12:53.77#ibcon#about to read 5, iclass 34, count 2 2006.257.04:12:53.77#ibcon#read 5, iclass 34, count 2 2006.257.04:12:53.77#ibcon#about to read 6, iclass 34, count 2 2006.257.04:12:53.77#ibcon#read 6, iclass 34, count 2 2006.257.04:12:53.77#ibcon#end of sib2, iclass 34, count 2 2006.257.04:12:53.77#ibcon#*mode == 0, iclass 34, count 2 2006.257.04:12:53.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.04:12:53.77#ibcon#[25=AT02-07\r\n] 2006.257.04:12:53.77#ibcon#*before write, iclass 34, count 2 2006.257.04:12:53.77#ibcon#enter sib2, iclass 34, count 2 2006.257.04:12:53.77#ibcon#flushed, iclass 34, count 2 2006.257.04:12:53.77#ibcon#about to write, iclass 34, count 2 2006.257.04:12:53.77#ibcon#wrote, iclass 34, count 2 2006.257.04:12:53.77#ibcon#about to read 3, iclass 34, count 2 2006.257.04:12:53.80#ibcon#read 3, iclass 34, count 2 2006.257.04:12:53.80#ibcon#about to read 4, iclass 34, count 2 2006.257.04:12:53.80#ibcon#read 4, iclass 34, count 2 2006.257.04:12:53.80#ibcon#about to read 5, iclass 34, count 2 2006.257.04:12:53.80#ibcon#read 5, iclass 34, count 2 2006.257.04:12:53.80#ibcon#about to read 6, iclass 34, count 2 2006.257.04:12:53.80#ibcon#read 6, iclass 34, count 2 2006.257.04:12:53.80#ibcon#end of sib2, iclass 34, count 2 2006.257.04:12:53.80#ibcon#*after write, iclass 34, count 2 2006.257.04:12:53.80#ibcon#*before return 0, iclass 34, count 2 2006.257.04:12:53.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:53.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:53.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.04:12:53.80#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:53.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:53.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:53.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:53.92#ibcon#enter wrdev, iclass 34, count 0 2006.257.04:12:53.92#ibcon#first serial, iclass 34, count 0 2006.257.04:12:53.92#ibcon#enter sib2, iclass 34, count 0 2006.257.04:12:53.92#ibcon#flushed, iclass 34, count 0 2006.257.04:12:53.92#ibcon#about to write, iclass 34, count 0 2006.257.04:12:53.92#ibcon#wrote, iclass 34, count 0 2006.257.04:12:53.92#ibcon#about to read 3, iclass 34, count 0 2006.257.04:12:53.94#ibcon#read 3, iclass 34, count 0 2006.257.04:12:53.94#ibcon#about to read 4, iclass 34, count 0 2006.257.04:12:53.94#ibcon#read 4, iclass 34, count 0 2006.257.04:12:53.94#ibcon#about to read 5, iclass 34, count 0 2006.257.04:12:53.94#ibcon#read 5, iclass 34, count 0 2006.257.04:12:53.94#ibcon#about to read 6, iclass 34, count 0 2006.257.04:12:53.94#ibcon#read 6, iclass 34, count 0 2006.257.04:12:53.94#ibcon#end of sib2, iclass 34, count 0 2006.257.04:12:53.94#ibcon#*mode == 0, iclass 34, count 0 2006.257.04:12:53.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.04:12:53.94#ibcon#[25=USB\r\n] 2006.257.04:12:53.94#ibcon#*before write, iclass 34, count 0 2006.257.04:12:53.94#ibcon#enter sib2, iclass 34, count 0 2006.257.04:12:53.94#ibcon#flushed, iclass 34, count 0 2006.257.04:12:53.94#ibcon#about to write, iclass 34, count 0 2006.257.04:12:53.94#ibcon#wrote, iclass 34, count 0 2006.257.04:12:53.94#ibcon#about to read 3, iclass 34, count 0 2006.257.04:12:53.97#ibcon#read 3, iclass 34, count 0 2006.257.04:12:53.97#ibcon#about to read 4, iclass 34, count 0 2006.257.04:12:53.97#ibcon#read 4, iclass 34, count 0 2006.257.04:12:53.97#ibcon#about to read 5, iclass 34, count 0 2006.257.04:12:53.97#ibcon#read 5, iclass 34, count 0 2006.257.04:12:53.97#ibcon#about to read 6, iclass 34, count 0 2006.257.04:12:53.97#ibcon#read 6, iclass 34, count 0 2006.257.04:12:53.97#ibcon#end of sib2, iclass 34, count 0 2006.257.04:12:53.97#ibcon#*after write, iclass 34, count 0 2006.257.04:12:53.97#ibcon#*before return 0, iclass 34, count 0 2006.257.04:12:53.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:53.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:53.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.04:12:53.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.04:12:53.97$vck44/valo=3,564.99 2006.257.04:12:53.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.04:12:53.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.04:12:53.97#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:53.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:12:53.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:12:53.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:12:53.97#ibcon#enter wrdev, iclass 36, count 0 2006.257.04:12:53.97#ibcon#first serial, iclass 36, count 0 2006.257.04:12:53.97#ibcon#enter sib2, iclass 36, count 0 2006.257.04:12:53.97#ibcon#flushed, iclass 36, count 0 2006.257.04:12:53.97#ibcon#about to write, iclass 36, count 0 2006.257.04:12:53.97#ibcon#wrote, iclass 36, count 0 2006.257.04:12:53.97#ibcon#about to read 3, iclass 36, count 0 2006.257.04:12:53.99#ibcon#read 3, iclass 36, count 0 2006.257.04:12:53.99#ibcon#about to read 4, iclass 36, count 0 2006.257.04:12:53.99#ibcon#read 4, iclass 36, count 0 2006.257.04:12:53.99#ibcon#about to read 5, iclass 36, count 0 2006.257.04:12:53.99#ibcon#read 5, iclass 36, count 0 2006.257.04:12:53.99#ibcon#about to read 6, iclass 36, count 0 2006.257.04:12:53.99#ibcon#read 6, iclass 36, count 0 2006.257.04:12:53.99#ibcon#end of sib2, iclass 36, count 0 2006.257.04:12:53.99#ibcon#*mode == 0, iclass 36, count 0 2006.257.04:12:53.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.04:12:53.99#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.04:12:53.99#ibcon#*before write, iclass 36, count 0 2006.257.04:12:53.99#ibcon#enter sib2, iclass 36, count 0 2006.257.04:12:53.99#ibcon#flushed, iclass 36, count 0 2006.257.04:12:53.99#ibcon#about to write, iclass 36, count 0 2006.257.04:12:53.99#ibcon#wrote, iclass 36, count 0 2006.257.04:12:53.99#ibcon#about to read 3, iclass 36, count 0 2006.257.04:12:54.03#ibcon#read 3, iclass 36, count 0 2006.257.04:12:54.03#ibcon#about to read 4, iclass 36, count 0 2006.257.04:12:54.03#ibcon#read 4, iclass 36, count 0 2006.257.04:12:54.03#ibcon#about to read 5, iclass 36, count 0 2006.257.04:12:54.03#ibcon#read 5, iclass 36, count 0 2006.257.04:12:54.03#ibcon#about to read 6, iclass 36, count 0 2006.257.04:12:54.03#ibcon#read 6, iclass 36, count 0 2006.257.04:12:54.03#ibcon#end of sib2, iclass 36, count 0 2006.257.04:12:54.03#ibcon#*after write, iclass 36, count 0 2006.257.04:12:54.03#ibcon#*before return 0, iclass 36, count 0 2006.257.04:12:54.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:12:54.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:12:54.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.04:12:54.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.04:12:54.03$vck44/va=3,8 2006.257.04:12:54.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.04:12:54.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.04:12:54.03#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:54.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:12:54.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:12:54.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:12:54.09#ibcon#enter wrdev, iclass 38, count 2 2006.257.04:12:54.09#ibcon#first serial, iclass 38, count 2 2006.257.04:12:54.09#ibcon#enter sib2, iclass 38, count 2 2006.257.04:12:54.09#ibcon#flushed, iclass 38, count 2 2006.257.04:12:54.09#ibcon#about to write, iclass 38, count 2 2006.257.04:12:54.09#ibcon#wrote, iclass 38, count 2 2006.257.04:12:54.09#ibcon#about to read 3, iclass 38, count 2 2006.257.04:12:54.11#ibcon#read 3, iclass 38, count 2 2006.257.04:12:54.11#ibcon#about to read 4, iclass 38, count 2 2006.257.04:12:54.11#ibcon#read 4, iclass 38, count 2 2006.257.04:12:54.11#ibcon#about to read 5, iclass 38, count 2 2006.257.04:12:54.11#ibcon#read 5, iclass 38, count 2 2006.257.04:12:54.11#ibcon#about to read 6, iclass 38, count 2 2006.257.04:12:54.11#ibcon#read 6, iclass 38, count 2 2006.257.04:12:54.11#ibcon#end of sib2, iclass 38, count 2 2006.257.04:12:54.11#ibcon#*mode == 0, iclass 38, count 2 2006.257.04:12:54.11#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.04:12:54.11#ibcon#[25=AT03-08\r\n] 2006.257.04:12:54.11#ibcon#*before write, iclass 38, count 2 2006.257.04:12:54.11#ibcon#enter sib2, iclass 38, count 2 2006.257.04:12:54.11#ibcon#flushed, iclass 38, count 2 2006.257.04:12:54.11#ibcon#about to write, iclass 38, count 2 2006.257.04:12:54.11#ibcon#wrote, iclass 38, count 2 2006.257.04:12:54.11#ibcon#about to read 3, iclass 38, count 2 2006.257.04:12:54.14#ibcon#read 3, iclass 38, count 2 2006.257.04:12:54.14#ibcon#about to read 4, iclass 38, count 2 2006.257.04:12:54.14#ibcon#read 4, iclass 38, count 2 2006.257.04:12:54.14#ibcon#about to read 5, iclass 38, count 2 2006.257.04:12:54.14#ibcon#read 5, iclass 38, count 2 2006.257.04:12:54.14#ibcon#about to read 6, iclass 38, count 2 2006.257.04:12:54.14#ibcon#read 6, iclass 38, count 2 2006.257.04:12:54.14#ibcon#end of sib2, iclass 38, count 2 2006.257.04:12:54.14#ibcon#*after write, iclass 38, count 2 2006.257.04:12:54.14#ibcon#*before return 0, iclass 38, count 2 2006.257.04:12:54.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:12:54.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:12:54.14#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.04:12:54.14#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:54.14#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:12:54.26#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:12:54.26#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:12:54.26#ibcon#enter wrdev, iclass 38, count 0 2006.257.04:12:54.26#ibcon#first serial, iclass 38, count 0 2006.257.04:12:54.26#ibcon#enter sib2, iclass 38, count 0 2006.257.04:12:54.26#ibcon#flushed, iclass 38, count 0 2006.257.04:12:54.26#ibcon#about to write, iclass 38, count 0 2006.257.04:12:54.26#ibcon#wrote, iclass 38, count 0 2006.257.04:12:54.26#ibcon#about to read 3, iclass 38, count 0 2006.257.04:12:54.28#ibcon#read 3, iclass 38, count 0 2006.257.04:12:54.28#ibcon#about to read 4, iclass 38, count 0 2006.257.04:12:54.28#ibcon#read 4, iclass 38, count 0 2006.257.04:12:54.28#ibcon#about to read 5, iclass 38, count 0 2006.257.04:12:54.28#ibcon#read 5, iclass 38, count 0 2006.257.04:12:54.28#ibcon#about to read 6, iclass 38, count 0 2006.257.04:12:54.28#ibcon#read 6, iclass 38, count 0 2006.257.04:12:54.28#ibcon#end of sib2, iclass 38, count 0 2006.257.04:12:54.28#ibcon#*mode == 0, iclass 38, count 0 2006.257.04:12:54.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.04:12:54.28#ibcon#[25=USB\r\n] 2006.257.04:12:54.28#ibcon#*before write, iclass 38, count 0 2006.257.04:12:54.28#ibcon#enter sib2, iclass 38, count 0 2006.257.04:12:54.28#ibcon#flushed, iclass 38, count 0 2006.257.04:12:54.28#ibcon#about to write, iclass 38, count 0 2006.257.04:12:54.28#ibcon#wrote, iclass 38, count 0 2006.257.04:12:54.28#ibcon#about to read 3, iclass 38, count 0 2006.257.04:12:54.31#ibcon#read 3, iclass 38, count 0 2006.257.04:12:54.31#ibcon#about to read 4, iclass 38, count 0 2006.257.04:12:54.31#ibcon#read 4, iclass 38, count 0 2006.257.04:12:54.31#ibcon#about to read 5, iclass 38, count 0 2006.257.04:12:54.31#ibcon#read 5, iclass 38, count 0 2006.257.04:12:54.31#ibcon#about to read 6, iclass 38, count 0 2006.257.04:12:54.31#ibcon#read 6, iclass 38, count 0 2006.257.04:12:54.31#ibcon#end of sib2, iclass 38, count 0 2006.257.04:12:54.31#ibcon#*after write, iclass 38, count 0 2006.257.04:12:54.31#ibcon#*before return 0, iclass 38, count 0 2006.257.04:12:54.31#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:12:54.31#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:12:54.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.04:12:54.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.04:12:54.31$vck44/valo=4,624.99 2006.257.04:12:54.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.04:12:54.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.04:12:54.31#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:54.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:54.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:54.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:54.31#ibcon#enter wrdev, iclass 40, count 0 2006.257.04:12:54.31#ibcon#first serial, iclass 40, count 0 2006.257.04:12:54.31#ibcon#enter sib2, iclass 40, count 0 2006.257.04:12:54.31#ibcon#flushed, iclass 40, count 0 2006.257.04:12:54.31#ibcon#about to write, iclass 40, count 0 2006.257.04:12:54.31#ibcon#wrote, iclass 40, count 0 2006.257.04:12:54.31#ibcon#about to read 3, iclass 40, count 0 2006.257.04:12:54.33#ibcon#read 3, iclass 40, count 0 2006.257.04:12:54.33#ibcon#about to read 4, iclass 40, count 0 2006.257.04:12:54.33#ibcon#read 4, iclass 40, count 0 2006.257.04:12:54.33#ibcon#about to read 5, iclass 40, count 0 2006.257.04:12:54.33#ibcon#read 5, iclass 40, count 0 2006.257.04:12:54.33#ibcon#about to read 6, iclass 40, count 0 2006.257.04:12:54.33#ibcon#read 6, iclass 40, count 0 2006.257.04:12:54.33#ibcon#end of sib2, iclass 40, count 0 2006.257.04:12:54.33#ibcon#*mode == 0, iclass 40, count 0 2006.257.04:12:54.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.04:12:54.33#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.04:12:54.33#ibcon#*before write, iclass 40, count 0 2006.257.04:12:54.33#ibcon#enter sib2, iclass 40, count 0 2006.257.04:12:54.33#ibcon#flushed, iclass 40, count 0 2006.257.04:12:54.33#ibcon#about to write, iclass 40, count 0 2006.257.04:12:54.33#ibcon#wrote, iclass 40, count 0 2006.257.04:12:54.33#ibcon#about to read 3, iclass 40, count 0 2006.257.04:12:54.37#ibcon#read 3, iclass 40, count 0 2006.257.04:12:54.37#ibcon#about to read 4, iclass 40, count 0 2006.257.04:12:54.37#ibcon#read 4, iclass 40, count 0 2006.257.04:12:54.37#ibcon#about to read 5, iclass 40, count 0 2006.257.04:12:54.37#ibcon#read 5, iclass 40, count 0 2006.257.04:12:54.37#ibcon#about to read 6, iclass 40, count 0 2006.257.04:12:54.37#ibcon#read 6, iclass 40, count 0 2006.257.04:12:54.37#ibcon#end of sib2, iclass 40, count 0 2006.257.04:12:54.37#ibcon#*after write, iclass 40, count 0 2006.257.04:12:54.37#ibcon#*before return 0, iclass 40, count 0 2006.257.04:12:54.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:54.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:54.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.04:12:54.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.04:12:54.37$vck44/va=4,7 2006.257.04:12:54.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.04:12:54.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.04:12:54.37#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:54.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:54.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:54.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:54.43#ibcon#enter wrdev, iclass 4, count 2 2006.257.04:12:54.43#ibcon#first serial, iclass 4, count 2 2006.257.04:12:54.43#ibcon#enter sib2, iclass 4, count 2 2006.257.04:12:54.43#ibcon#flushed, iclass 4, count 2 2006.257.04:12:54.43#ibcon#about to write, iclass 4, count 2 2006.257.04:12:54.43#ibcon#wrote, iclass 4, count 2 2006.257.04:12:54.43#ibcon#about to read 3, iclass 4, count 2 2006.257.04:12:54.45#ibcon#read 3, iclass 4, count 2 2006.257.04:12:54.45#ibcon#about to read 4, iclass 4, count 2 2006.257.04:12:54.45#ibcon#read 4, iclass 4, count 2 2006.257.04:12:54.45#ibcon#about to read 5, iclass 4, count 2 2006.257.04:12:54.45#ibcon#read 5, iclass 4, count 2 2006.257.04:12:54.45#ibcon#about to read 6, iclass 4, count 2 2006.257.04:12:54.45#ibcon#read 6, iclass 4, count 2 2006.257.04:12:54.45#ibcon#end of sib2, iclass 4, count 2 2006.257.04:12:54.45#ibcon#*mode == 0, iclass 4, count 2 2006.257.04:12:54.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.04:12:54.45#ibcon#[25=AT04-07\r\n] 2006.257.04:12:54.45#ibcon#*before write, iclass 4, count 2 2006.257.04:12:54.45#ibcon#enter sib2, iclass 4, count 2 2006.257.04:12:54.45#ibcon#flushed, iclass 4, count 2 2006.257.04:12:54.45#ibcon#about to write, iclass 4, count 2 2006.257.04:12:54.45#ibcon#wrote, iclass 4, count 2 2006.257.04:12:54.45#ibcon#about to read 3, iclass 4, count 2 2006.257.04:12:54.48#ibcon#read 3, iclass 4, count 2 2006.257.04:12:54.48#ibcon#about to read 4, iclass 4, count 2 2006.257.04:12:54.48#ibcon#read 4, iclass 4, count 2 2006.257.04:12:54.48#ibcon#about to read 5, iclass 4, count 2 2006.257.04:12:54.48#ibcon#read 5, iclass 4, count 2 2006.257.04:12:54.48#ibcon#about to read 6, iclass 4, count 2 2006.257.04:12:54.48#ibcon#read 6, iclass 4, count 2 2006.257.04:12:54.48#ibcon#end of sib2, iclass 4, count 2 2006.257.04:12:54.48#ibcon#*after write, iclass 4, count 2 2006.257.04:12:54.48#ibcon#*before return 0, iclass 4, count 2 2006.257.04:12:54.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:54.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:54.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.04:12:54.48#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:54.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:54.60#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:54.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:54.60#ibcon#enter wrdev, iclass 4, count 0 2006.257.04:12:54.60#ibcon#first serial, iclass 4, count 0 2006.257.04:12:54.60#ibcon#enter sib2, iclass 4, count 0 2006.257.04:12:54.60#ibcon#flushed, iclass 4, count 0 2006.257.04:12:54.60#ibcon#about to write, iclass 4, count 0 2006.257.04:12:54.60#ibcon#wrote, iclass 4, count 0 2006.257.04:12:54.60#ibcon#about to read 3, iclass 4, count 0 2006.257.04:12:54.62#ibcon#read 3, iclass 4, count 0 2006.257.04:12:54.62#ibcon#about to read 4, iclass 4, count 0 2006.257.04:12:54.62#ibcon#read 4, iclass 4, count 0 2006.257.04:12:54.62#ibcon#about to read 5, iclass 4, count 0 2006.257.04:12:54.62#ibcon#read 5, iclass 4, count 0 2006.257.04:12:54.62#ibcon#about to read 6, iclass 4, count 0 2006.257.04:12:54.62#ibcon#read 6, iclass 4, count 0 2006.257.04:12:54.62#ibcon#end of sib2, iclass 4, count 0 2006.257.04:12:54.62#ibcon#*mode == 0, iclass 4, count 0 2006.257.04:12:54.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.04:12:54.62#ibcon#[25=USB\r\n] 2006.257.04:12:54.62#ibcon#*before write, iclass 4, count 0 2006.257.04:12:54.62#ibcon#enter sib2, iclass 4, count 0 2006.257.04:12:54.62#ibcon#flushed, iclass 4, count 0 2006.257.04:12:54.62#ibcon#about to write, iclass 4, count 0 2006.257.04:12:54.62#ibcon#wrote, iclass 4, count 0 2006.257.04:12:54.62#ibcon#about to read 3, iclass 4, count 0 2006.257.04:12:54.65#ibcon#read 3, iclass 4, count 0 2006.257.04:12:54.65#ibcon#about to read 4, iclass 4, count 0 2006.257.04:12:54.65#ibcon#read 4, iclass 4, count 0 2006.257.04:12:54.65#ibcon#about to read 5, iclass 4, count 0 2006.257.04:12:54.65#ibcon#read 5, iclass 4, count 0 2006.257.04:12:54.65#ibcon#about to read 6, iclass 4, count 0 2006.257.04:12:54.65#ibcon#read 6, iclass 4, count 0 2006.257.04:12:54.65#ibcon#end of sib2, iclass 4, count 0 2006.257.04:12:54.65#ibcon#*after write, iclass 4, count 0 2006.257.04:12:54.65#ibcon#*before return 0, iclass 4, count 0 2006.257.04:12:54.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:54.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:54.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.04:12:54.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.04:12:54.65$vck44/valo=5,734.99 2006.257.04:12:54.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.04:12:54.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.04:12:54.65#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:54.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:54.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:54.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:54.65#ibcon#enter wrdev, iclass 6, count 0 2006.257.04:12:54.65#ibcon#first serial, iclass 6, count 0 2006.257.04:12:54.65#ibcon#enter sib2, iclass 6, count 0 2006.257.04:12:54.65#ibcon#flushed, iclass 6, count 0 2006.257.04:12:54.65#ibcon#about to write, iclass 6, count 0 2006.257.04:12:54.65#ibcon#wrote, iclass 6, count 0 2006.257.04:12:54.65#ibcon#about to read 3, iclass 6, count 0 2006.257.04:12:54.67#ibcon#read 3, iclass 6, count 0 2006.257.04:12:54.67#ibcon#about to read 4, iclass 6, count 0 2006.257.04:12:54.67#ibcon#read 4, iclass 6, count 0 2006.257.04:12:54.67#ibcon#about to read 5, iclass 6, count 0 2006.257.04:12:54.67#ibcon#read 5, iclass 6, count 0 2006.257.04:12:54.67#ibcon#about to read 6, iclass 6, count 0 2006.257.04:12:54.67#ibcon#read 6, iclass 6, count 0 2006.257.04:12:54.67#ibcon#end of sib2, iclass 6, count 0 2006.257.04:12:54.67#ibcon#*mode == 0, iclass 6, count 0 2006.257.04:12:54.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.04:12:54.67#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.04:12:54.67#ibcon#*before write, iclass 6, count 0 2006.257.04:12:54.67#ibcon#enter sib2, iclass 6, count 0 2006.257.04:12:54.67#ibcon#flushed, iclass 6, count 0 2006.257.04:12:54.67#ibcon#about to write, iclass 6, count 0 2006.257.04:12:54.67#ibcon#wrote, iclass 6, count 0 2006.257.04:12:54.67#ibcon#about to read 3, iclass 6, count 0 2006.257.04:12:54.71#ibcon#read 3, iclass 6, count 0 2006.257.04:12:54.71#ibcon#about to read 4, iclass 6, count 0 2006.257.04:12:54.71#ibcon#read 4, iclass 6, count 0 2006.257.04:12:54.71#ibcon#about to read 5, iclass 6, count 0 2006.257.04:12:54.71#ibcon#read 5, iclass 6, count 0 2006.257.04:12:54.71#ibcon#about to read 6, iclass 6, count 0 2006.257.04:12:54.71#ibcon#read 6, iclass 6, count 0 2006.257.04:12:54.71#ibcon#end of sib2, iclass 6, count 0 2006.257.04:12:54.71#ibcon#*after write, iclass 6, count 0 2006.257.04:12:54.71#ibcon#*before return 0, iclass 6, count 0 2006.257.04:12:54.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:54.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:54.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.04:12:54.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.04:12:54.71$vck44/va=5,4 2006.257.04:12:54.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.04:12:54.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.04:12:54.71#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:54.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:54.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:54.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:54.77#ibcon#enter wrdev, iclass 10, count 2 2006.257.04:12:54.77#ibcon#first serial, iclass 10, count 2 2006.257.04:12:54.77#ibcon#enter sib2, iclass 10, count 2 2006.257.04:12:54.77#ibcon#flushed, iclass 10, count 2 2006.257.04:12:54.77#ibcon#about to write, iclass 10, count 2 2006.257.04:12:54.77#ibcon#wrote, iclass 10, count 2 2006.257.04:12:54.77#ibcon#about to read 3, iclass 10, count 2 2006.257.04:12:54.79#ibcon#read 3, iclass 10, count 2 2006.257.04:12:54.79#ibcon#about to read 4, iclass 10, count 2 2006.257.04:12:54.79#ibcon#read 4, iclass 10, count 2 2006.257.04:12:54.79#ibcon#about to read 5, iclass 10, count 2 2006.257.04:12:54.79#ibcon#read 5, iclass 10, count 2 2006.257.04:12:54.79#ibcon#about to read 6, iclass 10, count 2 2006.257.04:12:54.79#ibcon#read 6, iclass 10, count 2 2006.257.04:12:54.79#ibcon#end of sib2, iclass 10, count 2 2006.257.04:12:54.79#ibcon#*mode == 0, iclass 10, count 2 2006.257.04:12:54.79#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.04:12:54.79#ibcon#[25=AT05-04\r\n] 2006.257.04:12:54.79#ibcon#*before write, iclass 10, count 2 2006.257.04:12:54.79#ibcon#enter sib2, iclass 10, count 2 2006.257.04:12:54.79#ibcon#flushed, iclass 10, count 2 2006.257.04:12:54.79#ibcon#about to write, iclass 10, count 2 2006.257.04:12:54.79#ibcon#wrote, iclass 10, count 2 2006.257.04:12:54.79#ibcon#about to read 3, iclass 10, count 2 2006.257.04:12:54.82#ibcon#read 3, iclass 10, count 2 2006.257.04:12:54.82#ibcon#about to read 4, iclass 10, count 2 2006.257.04:12:54.82#ibcon#read 4, iclass 10, count 2 2006.257.04:12:54.82#ibcon#about to read 5, iclass 10, count 2 2006.257.04:12:54.82#ibcon#read 5, iclass 10, count 2 2006.257.04:12:54.82#ibcon#about to read 6, iclass 10, count 2 2006.257.04:12:54.82#ibcon#read 6, iclass 10, count 2 2006.257.04:12:54.82#ibcon#end of sib2, iclass 10, count 2 2006.257.04:12:54.82#ibcon#*after write, iclass 10, count 2 2006.257.04:12:54.82#ibcon#*before return 0, iclass 10, count 2 2006.257.04:12:54.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:54.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:54.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.04:12:54.82#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:54.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:54.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:54.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:54.94#ibcon#enter wrdev, iclass 10, count 0 2006.257.04:12:54.94#ibcon#first serial, iclass 10, count 0 2006.257.04:12:54.94#ibcon#enter sib2, iclass 10, count 0 2006.257.04:12:54.94#ibcon#flushed, iclass 10, count 0 2006.257.04:12:54.94#ibcon#about to write, iclass 10, count 0 2006.257.04:12:54.94#ibcon#wrote, iclass 10, count 0 2006.257.04:12:54.94#ibcon#about to read 3, iclass 10, count 0 2006.257.04:12:54.96#ibcon#read 3, iclass 10, count 0 2006.257.04:12:54.96#ibcon#about to read 4, iclass 10, count 0 2006.257.04:12:54.96#ibcon#read 4, iclass 10, count 0 2006.257.04:12:54.96#ibcon#about to read 5, iclass 10, count 0 2006.257.04:12:54.96#ibcon#read 5, iclass 10, count 0 2006.257.04:12:54.96#ibcon#about to read 6, iclass 10, count 0 2006.257.04:12:54.96#ibcon#read 6, iclass 10, count 0 2006.257.04:12:54.96#ibcon#end of sib2, iclass 10, count 0 2006.257.04:12:54.96#ibcon#*mode == 0, iclass 10, count 0 2006.257.04:12:54.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.04:12:54.96#ibcon#[25=USB\r\n] 2006.257.04:12:54.96#ibcon#*before write, iclass 10, count 0 2006.257.04:12:54.96#ibcon#enter sib2, iclass 10, count 0 2006.257.04:12:54.96#ibcon#flushed, iclass 10, count 0 2006.257.04:12:54.96#ibcon#about to write, iclass 10, count 0 2006.257.04:12:54.96#ibcon#wrote, iclass 10, count 0 2006.257.04:12:54.96#ibcon#about to read 3, iclass 10, count 0 2006.257.04:12:54.99#ibcon#read 3, iclass 10, count 0 2006.257.04:12:54.99#ibcon#about to read 4, iclass 10, count 0 2006.257.04:12:54.99#ibcon#read 4, iclass 10, count 0 2006.257.04:12:54.99#ibcon#about to read 5, iclass 10, count 0 2006.257.04:12:54.99#ibcon#read 5, iclass 10, count 0 2006.257.04:12:54.99#ibcon#about to read 6, iclass 10, count 0 2006.257.04:12:54.99#ibcon#read 6, iclass 10, count 0 2006.257.04:12:54.99#ibcon#end of sib2, iclass 10, count 0 2006.257.04:12:54.99#ibcon#*after write, iclass 10, count 0 2006.257.04:12:54.99#ibcon#*before return 0, iclass 10, count 0 2006.257.04:12:54.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:54.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:54.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.04:12:54.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.04:12:54.99$vck44/valo=6,814.99 2006.257.04:12:54.99#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.04:12:54.99#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.04:12:54.99#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:54.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:54.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:54.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:54.99#ibcon#enter wrdev, iclass 12, count 0 2006.257.04:12:54.99#ibcon#first serial, iclass 12, count 0 2006.257.04:12:54.99#ibcon#enter sib2, iclass 12, count 0 2006.257.04:12:54.99#ibcon#flushed, iclass 12, count 0 2006.257.04:12:54.99#ibcon#about to write, iclass 12, count 0 2006.257.04:12:54.99#ibcon#wrote, iclass 12, count 0 2006.257.04:12:54.99#ibcon#about to read 3, iclass 12, count 0 2006.257.04:12:55.01#ibcon#read 3, iclass 12, count 0 2006.257.04:12:55.01#ibcon#about to read 4, iclass 12, count 0 2006.257.04:12:55.01#ibcon#read 4, iclass 12, count 0 2006.257.04:12:55.01#ibcon#about to read 5, iclass 12, count 0 2006.257.04:12:55.01#ibcon#read 5, iclass 12, count 0 2006.257.04:12:55.01#ibcon#about to read 6, iclass 12, count 0 2006.257.04:12:55.01#ibcon#read 6, iclass 12, count 0 2006.257.04:12:55.01#ibcon#end of sib2, iclass 12, count 0 2006.257.04:12:55.01#ibcon#*mode == 0, iclass 12, count 0 2006.257.04:12:55.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.04:12:55.01#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.04:12:55.01#ibcon#*before write, iclass 12, count 0 2006.257.04:12:55.01#ibcon#enter sib2, iclass 12, count 0 2006.257.04:12:55.01#ibcon#flushed, iclass 12, count 0 2006.257.04:12:55.01#ibcon#about to write, iclass 12, count 0 2006.257.04:12:55.01#ibcon#wrote, iclass 12, count 0 2006.257.04:12:55.01#ibcon#about to read 3, iclass 12, count 0 2006.257.04:12:55.05#ibcon#read 3, iclass 12, count 0 2006.257.04:12:55.05#ibcon#about to read 4, iclass 12, count 0 2006.257.04:12:55.05#ibcon#read 4, iclass 12, count 0 2006.257.04:12:55.05#ibcon#about to read 5, iclass 12, count 0 2006.257.04:12:55.05#ibcon#read 5, iclass 12, count 0 2006.257.04:12:55.05#ibcon#about to read 6, iclass 12, count 0 2006.257.04:12:55.05#ibcon#read 6, iclass 12, count 0 2006.257.04:12:55.05#ibcon#end of sib2, iclass 12, count 0 2006.257.04:12:55.05#ibcon#*after write, iclass 12, count 0 2006.257.04:12:55.05#ibcon#*before return 0, iclass 12, count 0 2006.257.04:12:55.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:55.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:55.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.04:12:55.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.04:12:55.05$vck44/va=6,4 2006.257.04:12:55.05#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.04:12:55.05#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.04:12:55.05#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:55.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:55.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:55.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:55.11#ibcon#enter wrdev, iclass 14, count 2 2006.257.04:12:55.11#ibcon#first serial, iclass 14, count 2 2006.257.04:12:55.11#ibcon#enter sib2, iclass 14, count 2 2006.257.04:12:55.11#ibcon#flushed, iclass 14, count 2 2006.257.04:12:55.11#ibcon#about to write, iclass 14, count 2 2006.257.04:12:55.11#ibcon#wrote, iclass 14, count 2 2006.257.04:12:55.11#ibcon#about to read 3, iclass 14, count 2 2006.257.04:12:55.13#ibcon#read 3, iclass 14, count 2 2006.257.04:12:55.13#ibcon#about to read 4, iclass 14, count 2 2006.257.04:12:55.13#ibcon#read 4, iclass 14, count 2 2006.257.04:12:55.13#ibcon#about to read 5, iclass 14, count 2 2006.257.04:12:55.13#ibcon#read 5, iclass 14, count 2 2006.257.04:12:55.13#ibcon#about to read 6, iclass 14, count 2 2006.257.04:12:55.13#ibcon#read 6, iclass 14, count 2 2006.257.04:12:55.13#ibcon#end of sib2, iclass 14, count 2 2006.257.04:12:55.13#ibcon#*mode == 0, iclass 14, count 2 2006.257.04:12:55.13#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.04:12:55.13#ibcon#[25=AT06-04\r\n] 2006.257.04:12:55.13#ibcon#*before write, iclass 14, count 2 2006.257.04:12:55.13#ibcon#enter sib2, iclass 14, count 2 2006.257.04:12:55.13#ibcon#flushed, iclass 14, count 2 2006.257.04:12:55.13#ibcon#about to write, iclass 14, count 2 2006.257.04:12:55.13#ibcon#wrote, iclass 14, count 2 2006.257.04:12:55.13#ibcon#about to read 3, iclass 14, count 2 2006.257.04:12:55.16#ibcon#read 3, iclass 14, count 2 2006.257.04:12:55.16#ibcon#about to read 4, iclass 14, count 2 2006.257.04:12:55.16#ibcon#read 4, iclass 14, count 2 2006.257.04:12:55.16#ibcon#about to read 5, iclass 14, count 2 2006.257.04:12:55.16#ibcon#read 5, iclass 14, count 2 2006.257.04:12:55.16#ibcon#about to read 6, iclass 14, count 2 2006.257.04:12:55.16#ibcon#read 6, iclass 14, count 2 2006.257.04:12:55.16#ibcon#end of sib2, iclass 14, count 2 2006.257.04:12:55.16#ibcon#*after write, iclass 14, count 2 2006.257.04:12:55.16#ibcon#*before return 0, iclass 14, count 2 2006.257.04:12:55.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:55.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:55.16#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.04:12:55.16#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:55.16#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:55.28#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:55.28#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:55.28#ibcon#enter wrdev, iclass 14, count 0 2006.257.04:12:55.28#ibcon#first serial, iclass 14, count 0 2006.257.04:12:55.28#ibcon#enter sib2, iclass 14, count 0 2006.257.04:12:55.28#ibcon#flushed, iclass 14, count 0 2006.257.04:12:55.28#ibcon#about to write, iclass 14, count 0 2006.257.04:12:55.28#ibcon#wrote, iclass 14, count 0 2006.257.04:12:55.28#ibcon#about to read 3, iclass 14, count 0 2006.257.04:12:55.30#ibcon#read 3, iclass 14, count 0 2006.257.04:12:55.30#ibcon#about to read 4, iclass 14, count 0 2006.257.04:12:55.30#ibcon#read 4, iclass 14, count 0 2006.257.04:12:55.30#ibcon#about to read 5, iclass 14, count 0 2006.257.04:12:55.30#ibcon#read 5, iclass 14, count 0 2006.257.04:12:55.30#ibcon#about to read 6, iclass 14, count 0 2006.257.04:12:55.30#ibcon#read 6, iclass 14, count 0 2006.257.04:12:55.30#ibcon#end of sib2, iclass 14, count 0 2006.257.04:12:55.30#ibcon#*mode == 0, iclass 14, count 0 2006.257.04:12:55.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.04:12:55.30#ibcon#[25=USB\r\n] 2006.257.04:12:55.30#ibcon#*before write, iclass 14, count 0 2006.257.04:12:55.30#ibcon#enter sib2, iclass 14, count 0 2006.257.04:12:55.30#ibcon#flushed, iclass 14, count 0 2006.257.04:12:55.30#ibcon#about to write, iclass 14, count 0 2006.257.04:12:55.30#ibcon#wrote, iclass 14, count 0 2006.257.04:12:55.30#ibcon#about to read 3, iclass 14, count 0 2006.257.04:12:55.33#ibcon#read 3, iclass 14, count 0 2006.257.04:12:55.33#ibcon#about to read 4, iclass 14, count 0 2006.257.04:12:55.33#ibcon#read 4, iclass 14, count 0 2006.257.04:12:55.33#ibcon#about to read 5, iclass 14, count 0 2006.257.04:12:55.33#ibcon#read 5, iclass 14, count 0 2006.257.04:12:55.33#ibcon#about to read 6, iclass 14, count 0 2006.257.04:12:55.33#ibcon#read 6, iclass 14, count 0 2006.257.04:12:55.33#ibcon#end of sib2, iclass 14, count 0 2006.257.04:12:55.33#ibcon#*after write, iclass 14, count 0 2006.257.04:12:55.33#ibcon#*before return 0, iclass 14, count 0 2006.257.04:12:55.33#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:55.33#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:55.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.04:12:55.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.04:12:55.33$vck44/valo=7,864.99 2006.257.04:12:55.33#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.04:12:55.33#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.04:12:55.33#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:55.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:55.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:55.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:55.33#ibcon#enter wrdev, iclass 16, count 0 2006.257.04:12:55.33#ibcon#first serial, iclass 16, count 0 2006.257.04:12:55.33#ibcon#enter sib2, iclass 16, count 0 2006.257.04:12:55.33#ibcon#flushed, iclass 16, count 0 2006.257.04:12:55.33#ibcon#about to write, iclass 16, count 0 2006.257.04:12:55.33#ibcon#wrote, iclass 16, count 0 2006.257.04:12:55.33#ibcon#about to read 3, iclass 16, count 0 2006.257.04:12:55.35#ibcon#read 3, iclass 16, count 0 2006.257.04:12:55.35#ibcon#about to read 4, iclass 16, count 0 2006.257.04:12:55.35#ibcon#read 4, iclass 16, count 0 2006.257.04:12:55.35#ibcon#about to read 5, iclass 16, count 0 2006.257.04:12:55.35#ibcon#read 5, iclass 16, count 0 2006.257.04:12:55.35#ibcon#about to read 6, iclass 16, count 0 2006.257.04:12:55.35#ibcon#read 6, iclass 16, count 0 2006.257.04:12:55.35#ibcon#end of sib2, iclass 16, count 0 2006.257.04:12:55.35#ibcon#*mode == 0, iclass 16, count 0 2006.257.04:12:55.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.04:12:55.35#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.04:12:55.35#ibcon#*before write, iclass 16, count 0 2006.257.04:12:55.35#ibcon#enter sib2, iclass 16, count 0 2006.257.04:12:55.35#ibcon#flushed, iclass 16, count 0 2006.257.04:12:55.35#ibcon#about to write, iclass 16, count 0 2006.257.04:12:55.35#ibcon#wrote, iclass 16, count 0 2006.257.04:12:55.35#ibcon#about to read 3, iclass 16, count 0 2006.257.04:12:55.39#ibcon#read 3, iclass 16, count 0 2006.257.04:12:55.39#ibcon#about to read 4, iclass 16, count 0 2006.257.04:12:55.39#ibcon#read 4, iclass 16, count 0 2006.257.04:12:55.39#ibcon#about to read 5, iclass 16, count 0 2006.257.04:12:55.39#ibcon#read 5, iclass 16, count 0 2006.257.04:12:55.39#ibcon#about to read 6, iclass 16, count 0 2006.257.04:12:55.39#ibcon#read 6, iclass 16, count 0 2006.257.04:12:55.39#ibcon#end of sib2, iclass 16, count 0 2006.257.04:12:55.39#ibcon#*after write, iclass 16, count 0 2006.257.04:12:55.39#ibcon#*before return 0, iclass 16, count 0 2006.257.04:12:55.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:55.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:55.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.04:12:55.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.04:12:55.39$vck44/va=7,4 2006.257.04:12:55.39#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.04:12:55.39#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.04:12:55.39#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:55.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:55.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:55.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:55.45#ibcon#enter wrdev, iclass 18, count 2 2006.257.04:12:55.45#ibcon#first serial, iclass 18, count 2 2006.257.04:12:55.45#ibcon#enter sib2, iclass 18, count 2 2006.257.04:12:55.45#ibcon#flushed, iclass 18, count 2 2006.257.04:12:55.45#ibcon#about to write, iclass 18, count 2 2006.257.04:12:55.45#ibcon#wrote, iclass 18, count 2 2006.257.04:12:55.45#ibcon#about to read 3, iclass 18, count 2 2006.257.04:12:55.47#ibcon#read 3, iclass 18, count 2 2006.257.04:12:55.47#ibcon#about to read 4, iclass 18, count 2 2006.257.04:12:55.47#ibcon#read 4, iclass 18, count 2 2006.257.04:12:55.47#ibcon#about to read 5, iclass 18, count 2 2006.257.04:12:55.47#ibcon#read 5, iclass 18, count 2 2006.257.04:12:55.47#ibcon#about to read 6, iclass 18, count 2 2006.257.04:12:55.47#ibcon#read 6, iclass 18, count 2 2006.257.04:12:55.47#ibcon#end of sib2, iclass 18, count 2 2006.257.04:12:55.47#ibcon#*mode == 0, iclass 18, count 2 2006.257.04:12:55.47#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.04:12:55.47#ibcon#[25=AT07-04\r\n] 2006.257.04:12:55.47#ibcon#*before write, iclass 18, count 2 2006.257.04:12:55.47#ibcon#enter sib2, iclass 18, count 2 2006.257.04:12:55.47#ibcon#flushed, iclass 18, count 2 2006.257.04:12:55.47#ibcon#about to write, iclass 18, count 2 2006.257.04:12:55.47#ibcon#wrote, iclass 18, count 2 2006.257.04:12:55.47#ibcon#about to read 3, iclass 18, count 2 2006.257.04:12:55.50#ibcon#read 3, iclass 18, count 2 2006.257.04:12:55.50#ibcon#about to read 4, iclass 18, count 2 2006.257.04:12:55.50#ibcon#read 4, iclass 18, count 2 2006.257.04:12:55.50#ibcon#about to read 5, iclass 18, count 2 2006.257.04:12:55.50#ibcon#read 5, iclass 18, count 2 2006.257.04:12:55.50#ibcon#about to read 6, iclass 18, count 2 2006.257.04:12:55.50#ibcon#read 6, iclass 18, count 2 2006.257.04:12:55.50#ibcon#end of sib2, iclass 18, count 2 2006.257.04:12:55.50#ibcon#*after write, iclass 18, count 2 2006.257.04:12:55.50#ibcon#*before return 0, iclass 18, count 2 2006.257.04:12:55.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:55.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:55.50#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.04:12:55.50#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:55.50#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:55.62#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:55.62#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:55.62#ibcon#enter wrdev, iclass 18, count 0 2006.257.04:12:55.62#ibcon#first serial, iclass 18, count 0 2006.257.04:12:55.62#ibcon#enter sib2, iclass 18, count 0 2006.257.04:12:55.62#ibcon#flushed, iclass 18, count 0 2006.257.04:12:55.62#ibcon#about to write, iclass 18, count 0 2006.257.04:12:55.62#ibcon#wrote, iclass 18, count 0 2006.257.04:12:55.62#ibcon#about to read 3, iclass 18, count 0 2006.257.04:12:55.64#ibcon#read 3, iclass 18, count 0 2006.257.04:12:55.64#ibcon#about to read 4, iclass 18, count 0 2006.257.04:12:55.64#ibcon#read 4, iclass 18, count 0 2006.257.04:12:55.64#ibcon#about to read 5, iclass 18, count 0 2006.257.04:12:55.64#ibcon#read 5, iclass 18, count 0 2006.257.04:12:55.64#ibcon#about to read 6, iclass 18, count 0 2006.257.04:12:55.64#ibcon#read 6, iclass 18, count 0 2006.257.04:12:55.64#ibcon#end of sib2, iclass 18, count 0 2006.257.04:12:55.64#ibcon#*mode == 0, iclass 18, count 0 2006.257.04:12:55.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.04:12:55.64#ibcon#[25=USB\r\n] 2006.257.04:12:55.64#ibcon#*before write, iclass 18, count 0 2006.257.04:12:55.64#ibcon#enter sib2, iclass 18, count 0 2006.257.04:12:55.64#ibcon#flushed, iclass 18, count 0 2006.257.04:12:55.64#ibcon#about to write, iclass 18, count 0 2006.257.04:12:55.64#ibcon#wrote, iclass 18, count 0 2006.257.04:12:55.64#ibcon#about to read 3, iclass 18, count 0 2006.257.04:12:55.67#ibcon#read 3, iclass 18, count 0 2006.257.04:12:55.67#ibcon#about to read 4, iclass 18, count 0 2006.257.04:12:55.67#ibcon#read 4, iclass 18, count 0 2006.257.04:12:55.67#ibcon#about to read 5, iclass 18, count 0 2006.257.04:12:55.67#ibcon#read 5, iclass 18, count 0 2006.257.04:12:55.67#ibcon#about to read 6, iclass 18, count 0 2006.257.04:12:55.67#ibcon#read 6, iclass 18, count 0 2006.257.04:12:55.67#ibcon#end of sib2, iclass 18, count 0 2006.257.04:12:55.67#ibcon#*after write, iclass 18, count 0 2006.257.04:12:55.67#ibcon#*before return 0, iclass 18, count 0 2006.257.04:12:55.67#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:55.67#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:55.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.04:12:55.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.04:12:55.67$vck44/valo=8,884.99 2006.257.04:12:55.67#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.04:12:55.67#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.04:12:55.67#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:55.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:55.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:55.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:55.67#ibcon#enter wrdev, iclass 20, count 0 2006.257.04:12:55.67#ibcon#first serial, iclass 20, count 0 2006.257.04:12:55.67#ibcon#enter sib2, iclass 20, count 0 2006.257.04:12:55.67#ibcon#flushed, iclass 20, count 0 2006.257.04:12:55.67#ibcon#about to write, iclass 20, count 0 2006.257.04:12:55.67#ibcon#wrote, iclass 20, count 0 2006.257.04:12:55.67#ibcon#about to read 3, iclass 20, count 0 2006.257.04:12:55.69#ibcon#read 3, iclass 20, count 0 2006.257.04:12:55.69#ibcon#about to read 4, iclass 20, count 0 2006.257.04:12:55.69#ibcon#read 4, iclass 20, count 0 2006.257.04:12:55.69#ibcon#about to read 5, iclass 20, count 0 2006.257.04:12:55.69#ibcon#read 5, iclass 20, count 0 2006.257.04:12:55.69#ibcon#about to read 6, iclass 20, count 0 2006.257.04:12:55.69#ibcon#read 6, iclass 20, count 0 2006.257.04:12:55.69#ibcon#end of sib2, iclass 20, count 0 2006.257.04:12:55.69#ibcon#*mode == 0, iclass 20, count 0 2006.257.04:12:55.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.04:12:55.69#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.04:12:55.69#ibcon#*before write, iclass 20, count 0 2006.257.04:12:55.69#ibcon#enter sib2, iclass 20, count 0 2006.257.04:12:55.69#ibcon#flushed, iclass 20, count 0 2006.257.04:12:55.69#ibcon#about to write, iclass 20, count 0 2006.257.04:12:55.69#ibcon#wrote, iclass 20, count 0 2006.257.04:12:55.69#ibcon#about to read 3, iclass 20, count 0 2006.257.04:12:55.73#ibcon#read 3, iclass 20, count 0 2006.257.04:12:55.73#ibcon#about to read 4, iclass 20, count 0 2006.257.04:12:55.73#ibcon#read 4, iclass 20, count 0 2006.257.04:12:55.73#ibcon#about to read 5, iclass 20, count 0 2006.257.04:12:55.73#ibcon#read 5, iclass 20, count 0 2006.257.04:12:55.73#ibcon#about to read 6, iclass 20, count 0 2006.257.04:12:55.73#ibcon#read 6, iclass 20, count 0 2006.257.04:12:55.73#ibcon#end of sib2, iclass 20, count 0 2006.257.04:12:55.73#ibcon#*after write, iclass 20, count 0 2006.257.04:12:55.73#ibcon#*before return 0, iclass 20, count 0 2006.257.04:12:55.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:55.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:55.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.04:12:55.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.04:12:55.73$vck44/va=8,4 2006.257.04:12:55.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.04:12:55.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.04:12:55.73#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:55.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:55.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:55.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:55.79#ibcon#enter wrdev, iclass 22, count 2 2006.257.04:12:55.79#ibcon#first serial, iclass 22, count 2 2006.257.04:12:55.79#ibcon#enter sib2, iclass 22, count 2 2006.257.04:12:55.79#ibcon#flushed, iclass 22, count 2 2006.257.04:12:55.79#ibcon#about to write, iclass 22, count 2 2006.257.04:12:55.79#ibcon#wrote, iclass 22, count 2 2006.257.04:12:55.79#ibcon#about to read 3, iclass 22, count 2 2006.257.04:12:55.81#ibcon#read 3, iclass 22, count 2 2006.257.04:12:55.81#ibcon#about to read 4, iclass 22, count 2 2006.257.04:12:55.81#ibcon#read 4, iclass 22, count 2 2006.257.04:12:55.81#ibcon#about to read 5, iclass 22, count 2 2006.257.04:12:55.81#ibcon#read 5, iclass 22, count 2 2006.257.04:12:55.81#ibcon#about to read 6, iclass 22, count 2 2006.257.04:12:55.81#ibcon#read 6, iclass 22, count 2 2006.257.04:12:55.81#ibcon#end of sib2, iclass 22, count 2 2006.257.04:12:55.81#ibcon#*mode == 0, iclass 22, count 2 2006.257.04:12:55.81#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.04:12:55.81#ibcon#[25=AT08-04\r\n] 2006.257.04:12:55.81#ibcon#*before write, iclass 22, count 2 2006.257.04:12:55.81#ibcon#enter sib2, iclass 22, count 2 2006.257.04:12:55.81#ibcon#flushed, iclass 22, count 2 2006.257.04:12:55.81#ibcon#about to write, iclass 22, count 2 2006.257.04:12:55.81#ibcon#wrote, iclass 22, count 2 2006.257.04:12:55.81#ibcon#about to read 3, iclass 22, count 2 2006.257.04:12:55.84#ibcon#read 3, iclass 22, count 2 2006.257.04:12:55.84#ibcon#about to read 4, iclass 22, count 2 2006.257.04:12:55.84#ibcon#read 4, iclass 22, count 2 2006.257.04:12:55.84#ibcon#about to read 5, iclass 22, count 2 2006.257.04:12:55.84#ibcon#read 5, iclass 22, count 2 2006.257.04:12:55.84#ibcon#about to read 6, iclass 22, count 2 2006.257.04:12:55.84#ibcon#read 6, iclass 22, count 2 2006.257.04:12:55.84#ibcon#end of sib2, iclass 22, count 2 2006.257.04:12:55.84#ibcon#*after write, iclass 22, count 2 2006.257.04:12:55.84#ibcon#*before return 0, iclass 22, count 2 2006.257.04:12:55.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:55.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:55.84#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.04:12:55.84#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:55.84#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:55.96#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:55.96#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:55.96#ibcon#enter wrdev, iclass 22, count 0 2006.257.04:12:55.96#ibcon#first serial, iclass 22, count 0 2006.257.04:12:55.96#ibcon#enter sib2, iclass 22, count 0 2006.257.04:12:55.96#ibcon#flushed, iclass 22, count 0 2006.257.04:12:55.96#ibcon#about to write, iclass 22, count 0 2006.257.04:12:55.96#ibcon#wrote, iclass 22, count 0 2006.257.04:12:55.96#ibcon#about to read 3, iclass 22, count 0 2006.257.04:12:55.98#ibcon#read 3, iclass 22, count 0 2006.257.04:12:55.98#ibcon#about to read 4, iclass 22, count 0 2006.257.04:12:55.98#ibcon#read 4, iclass 22, count 0 2006.257.04:12:55.98#ibcon#about to read 5, iclass 22, count 0 2006.257.04:12:55.98#ibcon#read 5, iclass 22, count 0 2006.257.04:12:55.98#ibcon#about to read 6, iclass 22, count 0 2006.257.04:12:55.98#ibcon#read 6, iclass 22, count 0 2006.257.04:12:55.98#ibcon#end of sib2, iclass 22, count 0 2006.257.04:12:55.98#ibcon#*mode == 0, iclass 22, count 0 2006.257.04:12:55.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.04:12:55.98#ibcon#[25=USB\r\n] 2006.257.04:12:55.98#ibcon#*before write, iclass 22, count 0 2006.257.04:12:55.98#ibcon#enter sib2, iclass 22, count 0 2006.257.04:12:55.98#ibcon#flushed, iclass 22, count 0 2006.257.04:12:55.98#ibcon#about to write, iclass 22, count 0 2006.257.04:12:55.98#ibcon#wrote, iclass 22, count 0 2006.257.04:12:55.98#ibcon#about to read 3, iclass 22, count 0 2006.257.04:12:56.01#ibcon#read 3, iclass 22, count 0 2006.257.04:12:56.01#ibcon#about to read 4, iclass 22, count 0 2006.257.04:12:56.01#ibcon#read 4, iclass 22, count 0 2006.257.04:12:56.01#ibcon#about to read 5, iclass 22, count 0 2006.257.04:12:56.01#ibcon#read 5, iclass 22, count 0 2006.257.04:12:56.01#ibcon#about to read 6, iclass 22, count 0 2006.257.04:12:56.01#ibcon#read 6, iclass 22, count 0 2006.257.04:12:56.01#ibcon#end of sib2, iclass 22, count 0 2006.257.04:12:56.01#ibcon#*after write, iclass 22, count 0 2006.257.04:12:56.01#ibcon#*before return 0, iclass 22, count 0 2006.257.04:12:56.01#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:56.01#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:56.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.04:12:56.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.04:12:56.01$vck44/vblo=1,629.99 2006.257.04:12:56.01#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.04:12:56.01#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.04:12:56.01#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:56.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:56.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:56.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:56.01#ibcon#enter wrdev, iclass 24, count 0 2006.257.04:12:56.01#ibcon#first serial, iclass 24, count 0 2006.257.04:12:56.01#ibcon#enter sib2, iclass 24, count 0 2006.257.04:12:56.01#ibcon#flushed, iclass 24, count 0 2006.257.04:12:56.01#ibcon#about to write, iclass 24, count 0 2006.257.04:12:56.01#ibcon#wrote, iclass 24, count 0 2006.257.04:12:56.01#ibcon#about to read 3, iclass 24, count 0 2006.257.04:12:56.03#ibcon#read 3, iclass 24, count 0 2006.257.04:12:56.03#ibcon#about to read 4, iclass 24, count 0 2006.257.04:12:56.03#ibcon#read 4, iclass 24, count 0 2006.257.04:12:56.03#ibcon#about to read 5, iclass 24, count 0 2006.257.04:12:56.03#ibcon#read 5, iclass 24, count 0 2006.257.04:12:56.03#ibcon#about to read 6, iclass 24, count 0 2006.257.04:12:56.03#ibcon#read 6, iclass 24, count 0 2006.257.04:12:56.03#ibcon#end of sib2, iclass 24, count 0 2006.257.04:12:56.03#ibcon#*mode == 0, iclass 24, count 0 2006.257.04:12:56.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.04:12:56.03#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.04:12:56.03#ibcon#*before write, iclass 24, count 0 2006.257.04:12:56.03#ibcon#enter sib2, iclass 24, count 0 2006.257.04:12:56.03#ibcon#flushed, iclass 24, count 0 2006.257.04:12:56.03#ibcon#about to write, iclass 24, count 0 2006.257.04:12:56.03#ibcon#wrote, iclass 24, count 0 2006.257.04:12:56.03#ibcon#about to read 3, iclass 24, count 0 2006.257.04:12:56.07#ibcon#read 3, iclass 24, count 0 2006.257.04:12:56.07#ibcon#about to read 4, iclass 24, count 0 2006.257.04:12:56.07#ibcon#read 4, iclass 24, count 0 2006.257.04:12:56.07#ibcon#about to read 5, iclass 24, count 0 2006.257.04:12:56.07#ibcon#read 5, iclass 24, count 0 2006.257.04:12:56.07#ibcon#about to read 6, iclass 24, count 0 2006.257.04:12:56.07#ibcon#read 6, iclass 24, count 0 2006.257.04:12:56.07#ibcon#end of sib2, iclass 24, count 0 2006.257.04:12:56.07#ibcon#*after write, iclass 24, count 0 2006.257.04:12:56.07#ibcon#*before return 0, iclass 24, count 0 2006.257.04:12:56.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:56.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:56.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.04:12:56.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.04:12:56.07$vck44/vb=1,4 2006.257.04:12:56.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.04:12:56.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.04:12:56.07#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:56.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:12:56.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:12:56.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:12:56.07#ibcon#enter wrdev, iclass 26, count 2 2006.257.04:12:56.07#ibcon#first serial, iclass 26, count 2 2006.257.04:12:56.07#ibcon#enter sib2, iclass 26, count 2 2006.257.04:12:56.07#ibcon#flushed, iclass 26, count 2 2006.257.04:12:56.07#ibcon#about to write, iclass 26, count 2 2006.257.04:12:56.07#ibcon#wrote, iclass 26, count 2 2006.257.04:12:56.07#ibcon#about to read 3, iclass 26, count 2 2006.257.04:12:56.09#ibcon#read 3, iclass 26, count 2 2006.257.04:12:56.09#ibcon#about to read 4, iclass 26, count 2 2006.257.04:12:56.09#ibcon#read 4, iclass 26, count 2 2006.257.04:12:56.09#ibcon#about to read 5, iclass 26, count 2 2006.257.04:12:56.09#ibcon#read 5, iclass 26, count 2 2006.257.04:12:56.09#ibcon#about to read 6, iclass 26, count 2 2006.257.04:12:56.09#ibcon#read 6, iclass 26, count 2 2006.257.04:12:56.09#ibcon#end of sib2, iclass 26, count 2 2006.257.04:12:56.09#ibcon#*mode == 0, iclass 26, count 2 2006.257.04:12:56.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.04:12:56.09#ibcon#[27=AT01-04\r\n] 2006.257.04:12:56.09#ibcon#*before write, iclass 26, count 2 2006.257.04:12:56.09#ibcon#enter sib2, iclass 26, count 2 2006.257.04:12:56.09#ibcon#flushed, iclass 26, count 2 2006.257.04:12:56.09#ibcon#about to write, iclass 26, count 2 2006.257.04:12:56.09#ibcon#wrote, iclass 26, count 2 2006.257.04:12:56.09#ibcon#about to read 3, iclass 26, count 2 2006.257.04:12:56.12#ibcon#read 3, iclass 26, count 2 2006.257.04:12:56.12#ibcon#about to read 4, iclass 26, count 2 2006.257.04:12:56.12#ibcon#read 4, iclass 26, count 2 2006.257.04:12:56.12#ibcon#about to read 5, iclass 26, count 2 2006.257.04:12:56.12#ibcon#read 5, iclass 26, count 2 2006.257.04:12:56.12#ibcon#about to read 6, iclass 26, count 2 2006.257.04:12:56.12#ibcon#read 6, iclass 26, count 2 2006.257.04:12:56.12#ibcon#end of sib2, iclass 26, count 2 2006.257.04:12:56.12#ibcon#*after write, iclass 26, count 2 2006.257.04:12:56.12#ibcon#*before return 0, iclass 26, count 2 2006.257.04:12:56.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:12:56.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:12:56.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.04:12:56.12#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:56.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:12:56.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:12:56.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:12:56.24#ibcon#enter wrdev, iclass 26, count 0 2006.257.04:12:56.24#ibcon#first serial, iclass 26, count 0 2006.257.04:12:56.24#ibcon#enter sib2, iclass 26, count 0 2006.257.04:12:56.24#ibcon#flushed, iclass 26, count 0 2006.257.04:12:56.24#ibcon#about to write, iclass 26, count 0 2006.257.04:12:56.24#ibcon#wrote, iclass 26, count 0 2006.257.04:12:56.24#ibcon#about to read 3, iclass 26, count 0 2006.257.04:12:56.26#ibcon#read 3, iclass 26, count 0 2006.257.04:12:56.26#ibcon#about to read 4, iclass 26, count 0 2006.257.04:12:56.26#ibcon#read 4, iclass 26, count 0 2006.257.04:12:56.26#ibcon#about to read 5, iclass 26, count 0 2006.257.04:12:56.26#ibcon#read 5, iclass 26, count 0 2006.257.04:12:56.26#ibcon#about to read 6, iclass 26, count 0 2006.257.04:12:56.26#ibcon#read 6, iclass 26, count 0 2006.257.04:12:56.26#ibcon#end of sib2, iclass 26, count 0 2006.257.04:12:56.26#ibcon#*mode == 0, iclass 26, count 0 2006.257.04:12:56.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.04:12:56.26#ibcon#[27=USB\r\n] 2006.257.04:12:56.26#ibcon#*before write, iclass 26, count 0 2006.257.04:12:56.26#ibcon#enter sib2, iclass 26, count 0 2006.257.04:12:56.26#ibcon#flushed, iclass 26, count 0 2006.257.04:12:56.26#ibcon#about to write, iclass 26, count 0 2006.257.04:12:56.26#ibcon#wrote, iclass 26, count 0 2006.257.04:12:56.26#ibcon#about to read 3, iclass 26, count 0 2006.257.04:12:56.29#ibcon#read 3, iclass 26, count 0 2006.257.04:12:56.29#ibcon#about to read 4, iclass 26, count 0 2006.257.04:12:56.29#ibcon#read 4, iclass 26, count 0 2006.257.04:12:56.29#ibcon#about to read 5, iclass 26, count 0 2006.257.04:12:56.29#ibcon#read 5, iclass 26, count 0 2006.257.04:12:56.29#ibcon#about to read 6, iclass 26, count 0 2006.257.04:12:56.29#ibcon#read 6, iclass 26, count 0 2006.257.04:12:56.29#ibcon#end of sib2, iclass 26, count 0 2006.257.04:12:56.29#ibcon#*after write, iclass 26, count 0 2006.257.04:12:56.29#ibcon#*before return 0, iclass 26, count 0 2006.257.04:12:56.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:12:56.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:12:56.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.04:12:56.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.04:12:56.29$vck44/vblo=2,634.99 2006.257.04:12:56.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.04:12:56.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.04:12:56.29#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:56.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:56.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:56.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:56.29#ibcon#enter wrdev, iclass 28, count 0 2006.257.04:12:56.29#ibcon#first serial, iclass 28, count 0 2006.257.04:12:56.29#ibcon#enter sib2, iclass 28, count 0 2006.257.04:12:56.29#ibcon#flushed, iclass 28, count 0 2006.257.04:12:56.29#ibcon#about to write, iclass 28, count 0 2006.257.04:12:56.29#ibcon#wrote, iclass 28, count 0 2006.257.04:12:56.29#ibcon#about to read 3, iclass 28, count 0 2006.257.04:12:56.31#ibcon#read 3, iclass 28, count 0 2006.257.04:12:56.31#ibcon#about to read 4, iclass 28, count 0 2006.257.04:12:56.31#ibcon#read 4, iclass 28, count 0 2006.257.04:12:56.31#ibcon#about to read 5, iclass 28, count 0 2006.257.04:12:56.31#ibcon#read 5, iclass 28, count 0 2006.257.04:12:56.31#ibcon#about to read 6, iclass 28, count 0 2006.257.04:12:56.31#ibcon#read 6, iclass 28, count 0 2006.257.04:12:56.31#ibcon#end of sib2, iclass 28, count 0 2006.257.04:12:56.31#ibcon#*mode == 0, iclass 28, count 0 2006.257.04:12:56.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.04:12:56.31#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.04:12:56.31#ibcon#*before write, iclass 28, count 0 2006.257.04:12:56.31#ibcon#enter sib2, iclass 28, count 0 2006.257.04:12:56.31#ibcon#flushed, iclass 28, count 0 2006.257.04:12:56.31#ibcon#about to write, iclass 28, count 0 2006.257.04:12:56.31#ibcon#wrote, iclass 28, count 0 2006.257.04:12:56.31#ibcon#about to read 3, iclass 28, count 0 2006.257.04:12:56.35#ibcon#read 3, iclass 28, count 0 2006.257.04:12:56.35#ibcon#about to read 4, iclass 28, count 0 2006.257.04:12:56.35#ibcon#read 4, iclass 28, count 0 2006.257.04:12:56.35#ibcon#about to read 5, iclass 28, count 0 2006.257.04:12:56.35#ibcon#read 5, iclass 28, count 0 2006.257.04:12:56.35#ibcon#about to read 6, iclass 28, count 0 2006.257.04:12:56.35#ibcon#read 6, iclass 28, count 0 2006.257.04:12:56.35#ibcon#end of sib2, iclass 28, count 0 2006.257.04:12:56.35#ibcon#*after write, iclass 28, count 0 2006.257.04:12:56.35#ibcon#*before return 0, iclass 28, count 0 2006.257.04:12:56.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:56.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:12:56.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.04:12:56.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.04:12:56.35$vck44/vb=2,5 2006.257.04:12:56.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.04:12:56.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.04:12:56.35#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:56.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:56.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:56.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:56.41#ibcon#enter wrdev, iclass 30, count 2 2006.257.04:12:56.41#ibcon#first serial, iclass 30, count 2 2006.257.04:12:56.41#ibcon#enter sib2, iclass 30, count 2 2006.257.04:12:56.41#ibcon#flushed, iclass 30, count 2 2006.257.04:12:56.41#ibcon#about to write, iclass 30, count 2 2006.257.04:12:56.41#ibcon#wrote, iclass 30, count 2 2006.257.04:12:56.41#ibcon#about to read 3, iclass 30, count 2 2006.257.04:12:56.43#ibcon#read 3, iclass 30, count 2 2006.257.04:12:56.43#ibcon#about to read 4, iclass 30, count 2 2006.257.04:12:56.43#ibcon#read 4, iclass 30, count 2 2006.257.04:12:56.43#ibcon#about to read 5, iclass 30, count 2 2006.257.04:12:56.43#ibcon#read 5, iclass 30, count 2 2006.257.04:12:56.43#ibcon#about to read 6, iclass 30, count 2 2006.257.04:12:56.43#ibcon#read 6, iclass 30, count 2 2006.257.04:12:56.43#ibcon#end of sib2, iclass 30, count 2 2006.257.04:12:56.43#ibcon#*mode == 0, iclass 30, count 2 2006.257.04:12:56.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.04:12:56.43#ibcon#[27=AT02-05\r\n] 2006.257.04:12:56.43#ibcon#*before write, iclass 30, count 2 2006.257.04:12:56.43#ibcon#enter sib2, iclass 30, count 2 2006.257.04:12:56.43#ibcon#flushed, iclass 30, count 2 2006.257.04:12:56.43#ibcon#about to write, iclass 30, count 2 2006.257.04:12:56.43#ibcon#wrote, iclass 30, count 2 2006.257.04:12:56.43#ibcon#about to read 3, iclass 30, count 2 2006.257.04:12:56.46#ibcon#read 3, iclass 30, count 2 2006.257.04:12:56.46#ibcon#about to read 4, iclass 30, count 2 2006.257.04:12:56.46#ibcon#read 4, iclass 30, count 2 2006.257.04:12:56.46#ibcon#about to read 5, iclass 30, count 2 2006.257.04:12:56.46#ibcon#read 5, iclass 30, count 2 2006.257.04:12:56.46#ibcon#about to read 6, iclass 30, count 2 2006.257.04:12:56.46#ibcon#read 6, iclass 30, count 2 2006.257.04:12:56.46#ibcon#end of sib2, iclass 30, count 2 2006.257.04:12:56.46#ibcon#*after write, iclass 30, count 2 2006.257.04:12:56.46#ibcon#*before return 0, iclass 30, count 2 2006.257.04:12:56.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:56.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:12:56.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.04:12:56.46#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:56.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:56.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:56.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:56.58#ibcon#enter wrdev, iclass 30, count 0 2006.257.04:12:56.58#ibcon#first serial, iclass 30, count 0 2006.257.04:12:56.58#ibcon#enter sib2, iclass 30, count 0 2006.257.04:12:56.58#ibcon#flushed, iclass 30, count 0 2006.257.04:12:56.58#ibcon#about to write, iclass 30, count 0 2006.257.04:12:56.58#ibcon#wrote, iclass 30, count 0 2006.257.04:12:56.58#ibcon#about to read 3, iclass 30, count 0 2006.257.04:12:56.60#ibcon#read 3, iclass 30, count 0 2006.257.04:12:56.60#ibcon#about to read 4, iclass 30, count 0 2006.257.04:12:56.60#ibcon#read 4, iclass 30, count 0 2006.257.04:12:56.60#ibcon#about to read 5, iclass 30, count 0 2006.257.04:12:56.60#ibcon#read 5, iclass 30, count 0 2006.257.04:12:56.60#ibcon#about to read 6, iclass 30, count 0 2006.257.04:12:56.60#ibcon#read 6, iclass 30, count 0 2006.257.04:12:56.60#ibcon#end of sib2, iclass 30, count 0 2006.257.04:12:56.60#ibcon#*mode == 0, iclass 30, count 0 2006.257.04:12:56.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.04:12:56.60#ibcon#[27=USB\r\n] 2006.257.04:12:56.60#ibcon#*before write, iclass 30, count 0 2006.257.04:12:56.60#ibcon#enter sib2, iclass 30, count 0 2006.257.04:12:56.60#ibcon#flushed, iclass 30, count 0 2006.257.04:12:56.60#ibcon#about to write, iclass 30, count 0 2006.257.04:12:56.60#ibcon#wrote, iclass 30, count 0 2006.257.04:12:56.60#ibcon#about to read 3, iclass 30, count 0 2006.257.04:12:56.63#ibcon#read 3, iclass 30, count 0 2006.257.04:12:56.63#ibcon#about to read 4, iclass 30, count 0 2006.257.04:12:56.63#ibcon#read 4, iclass 30, count 0 2006.257.04:12:56.63#ibcon#about to read 5, iclass 30, count 0 2006.257.04:12:56.63#ibcon#read 5, iclass 30, count 0 2006.257.04:12:56.63#ibcon#about to read 6, iclass 30, count 0 2006.257.04:12:56.63#ibcon#read 6, iclass 30, count 0 2006.257.04:12:56.63#ibcon#end of sib2, iclass 30, count 0 2006.257.04:12:56.63#ibcon#*after write, iclass 30, count 0 2006.257.04:12:56.63#ibcon#*before return 0, iclass 30, count 0 2006.257.04:12:56.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:56.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:12:56.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.04:12:56.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.04:12:56.63$vck44/vblo=3,649.99 2006.257.04:12:56.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.04:12:56.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.04:12:56.63#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:56.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:56.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:56.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:56.63#ibcon#enter wrdev, iclass 32, count 0 2006.257.04:12:56.63#ibcon#first serial, iclass 32, count 0 2006.257.04:12:56.63#ibcon#enter sib2, iclass 32, count 0 2006.257.04:12:56.63#ibcon#flushed, iclass 32, count 0 2006.257.04:12:56.63#ibcon#about to write, iclass 32, count 0 2006.257.04:12:56.63#ibcon#wrote, iclass 32, count 0 2006.257.04:12:56.63#ibcon#about to read 3, iclass 32, count 0 2006.257.04:12:56.65#ibcon#read 3, iclass 32, count 0 2006.257.04:12:56.65#ibcon#about to read 4, iclass 32, count 0 2006.257.04:12:56.65#ibcon#read 4, iclass 32, count 0 2006.257.04:12:56.65#ibcon#about to read 5, iclass 32, count 0 2006.257.04:12:56.65#ibcon#read 5, iclass 32, count 0 2006.257.04:12:56.65#ibcon#about to read 6, iclass 32, count 0 2006.257.04:12:56.65#ibcon#read 6, iclass 32, count 0 2006.257.04:12:56.65#ibcon#end of sib2, iclass 32, count 0 2006.257.04:12:56.65#ibcon#*mode == 0, iclass 32, count 0 2006.257.04:12:56.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.04:12:56.65#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.04:12:56.65#ibcon#*before write, iclass 32, count 0 2006.257.04:12:56.65#ibcon#enter sib2, iclass 32, count 0 2006.257.04:12:56.65#ibcon#flushed, iclass 32, count 0 2006.257.04:12:56.65#ibcon#about to write, iclass 32, count 0 2006.257.04:12:56.65#ibcon#wrote, iclass 32, count 0 2006.257.04:12:56.65#ibcon#about to read 3, iclass 32, count 0 2006.257.04:12:56.69#ibcon#read 3, iclass 32, count 0 2006.257.04:12:56.69#ibcon#about to read 4, iclass 32, count 0 2006.257.04:12:56.69#ibcon#read 4, iclass 32, count 0 2006.257.04:12:56.69#ibcon#about to read 5, iclass 32, count 0 2006.257.04:12:56.69#ibcon#read 5, iclass 32, count 0 2006.257.04:12:56.69#ibcon#about to read 6, iclass 32, count 0 2006.257.04:12:56.69#ibcon#read 6, iclass 32, count 0 2006.257.04:12:56.69#ibcon#end of sib2, iclass 32, count 0 2006.257.04:12:56.69#ibcon#*after write, iclass 32, count 0 2006.257.04:12:56.69#ibcon#*before return 0, iclass 32, count 0 2006.257.04:12:56.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:56.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:12:56.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.04:12:56.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.04:12:56.69$vck44/vb=3,4 2006.257.04:12:56.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.04:12:56.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.04:12:56.69#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:56.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:56.74#abcon#<5=/14 2.1 6.2 19.31 941011.9\r\n> 2006.257.04:12:56.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:56.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:56.75#ibcon#enter wrdev, iclass 34, count 2 2006.257.04:12:56.75#ibcon#first serial, iclass 34, count 2 2006.257.04:12:56.75#ibcon#enter sib2, iclass 34, count 2 2006.257.04:12:56.75#ibcon#flushed, iclass 34, count 2 2006.257.04:12:56.75#ibcon#about to write, iclass 34, count 2 2006.257.04:12:56.75#ibcon#wrote, iclass 34, count 2 2006.257.04:12:56.75#ibcon#about to read 3, iclass 34, count 2 2006.257.04:12:56.76#abcon#{5=INTERFACE CLEAR} 2006.257.04:12:56.77#ibcon#read 3, iclass 34, count 2 2006.257.04:12:56.77#ibcon#about to read 4, iclass 34, count 2 2006.257.04:12:56.77#ibcon#read 4, iclass 34, count 2 2006.257.04:12:56.77#ibcon#about to read 5, iclass 34, count 2 2006.257.04:12:56.77#ibcon#read 5, iclass 34, count 2 2006.257.04:12:56.77#ibcon#about to read 6, iclass 34, count 2 2006.257.04:12:56.77#ibcon#read 6, iclass 34, count 2 2006.257.04:12:56.77#ibcon#end of sib2, iclass 34, count 2 2006.257.04:12:56.77#ibcon#*mode == 0, iclass 34, count 2 2006.257.04:12:56.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.04:12:56.77#ibcon#[27=AT03-04\r\n] 2006.257.04:12:56.77#ibcon#*before write, iclass 34, count 2 2006.257.04:12:56.77#ibcon#enter sib2, iclass 34, count 2 2006.257.04:12:56.77#ibcon#flushed, iclass 34, count 2 2006.257.04:12:56.77#ibcon#about to write, iclass 34, count 2 2006.257.04:12:56.77#ibcon#wrote, iclass 34, count 2 2006.257.04:12:56.77#ibcon#about to read 3, iclass 34, count 2 2006.257.04:12:56.80#ibcon#read 3, iclass 34, count 2 2006.257.04:12:56.80#ibcon#about to read 4, iclass 34, count 2 2006.257.04:12:56.80#ibcon#read 4, iclass 34, count 2 2006.257.04:12:56.80#ibcon#about to read 5, iclass 34, count 2 2006.257.04:12:56.80#ibcon#read 5, iclass 34, count 2 2006.257.04:12:56.80#ibcon#about to read 6, iclass 34, count 2 2006.257.04:12:56.80#ibcon#read 6, iclass 34, count 2 2006.257.04:12:56.80#ibcon#end of sib2, iclass 34, count 2 2006.257.04:12:56.80#ibcon#*after write, iclass 34, count 2 2006.257.04:12:56.80#ibcon#*before return 0, iclass 34, count 2 2006.257.04:12:56.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:56.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:12:56.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.04:12:56.80#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:56.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:56.82#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:12:56.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:56.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:56.92#ibcon#enter wrdev, iclass 34, count 0 2006.257.04:12:56.92#ibcon#first serial, iclass 34, count 0 2006.257.04:12:56.92#ibcon#enter sib2, iclass 34, count 0 2006.257.04:12:56.92#ibcon#flushed, iclass 34, count 0 2006.257.04:12:56.92#ibcon#about to write, iclass 34, count 0 2006.257.04:12:56.92#ibcon#wrote, iclass 34, count 0 2006.257.04:12:56.92#ibcon#about to read 3, iclass 34, count 0 2006.257.04:12:56.94#ibcon#read 3, iclass 34, count 0 2006.257.04:12:56.94#ibcon#about to read 4, iclass 34, count 0 2006.257.04:12:56.94#ibcon#read 4, iclass 34, count 0 2006.257.04:12:56.94#ibcon#about to read 5, iclass 34, count 0 2006.257.04:12:56.94#ibcon#read 5, iclass 34, count 0 2006.257.04:12:56.94#ibcon#about to read 6, iclass 34, count 0 2006.257.04:12:56.94#ibcon#read 6, iclass 34, count 0 2006.257.04:12:56.94#ibcon#end of sib2, iclass 34, count 0 2006.257.04:12:56.94#ibcon#*mode == 0, iclass 34, count 0 2006.257.04:12:56.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.04:12:56.94#ibcon#[27=USB\r\n] 2006.257.04:12:56.94#ibcon#*before write, iclass 34, count 0 2006.257.04:12:56.94#ibcon#enter sib2, iclass 34, count 0 2006.257.04:12:56.94#ibcon#flushed, iclass 34, count 0 2006.257.04:12:56.94#ibcon#about to write, iclass 34, count 0 2006.257.04:12:56.94#ibcon#wrote, iclass 34, count 0 2006.257.04:12:56.94#ibcon#about to read 3, iclass 34, count 0 2006.257.04:12:56.97#ibcon#read 3, iclass 34, count 0 2006.257.04:12:56.97#ibcon#about to read 4, iclass 34, count 0 2006.257.04:12:56.97#ibcon#read 4, iclass 34, count 0 2006.257.04:12:56.97#ibcon#about to read 5, iclass 34, count 0 2006.257.04:12:56.97#ibcon#read 5, iclass 34, count 0 2006.257.04:12:56.97#ibcon#about to read 6, iclass 34, count 0 2006.257.04:12:56.97#ibcon#read 6, iclass 34, count 0 2006.257.04:12:56.97#ibcon#end of sib2, iclass 34, count 0 2006.257.04:12:56.97#ibcon#*after write, iclass 34, count 0 2006.257.04:12:56.97#ibcon#*before return 0, iclass 34, count 0 2006.257.04:12:56.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:56.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:12:56.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.04:12:56.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.04:12:56.97$vck44/vblo=4,679.99 2006.257.04:12:56.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.04:12:56.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.04:12:56.97#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:56.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:56.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:56.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:56.97#ibcon#enter wrdev, iclass 40, count 0 2006.257.04:12:56.97#ibcon#first serial, iclass 40, count 0 2006.257.04:12:56.97#ibcon#enter sib2, iclass 40, count 0 2006.257.04:12:56.97#ibcon#flushed, iclass 40, count 0 2006.257.04:12:56.97#ibcon#about to write, iclass 40, count 0 2006.257.04:12:56.97#ibcon#wrote, iclass 40, count 0 2006.257.04:12:56.97#ibcon#about to read 3, iclass 40, count 0 2006.257.04:12:56.99#ibcon#read 3, iclass 40, count 0 2006.257.04:12:56.99#ibcon#about to read 4, iclass 40, count 0 2006.257.04:12:56.99#ibcon#read 4, iclass 40, count 0 2006.257.04:12:56.99#ibcon#about to read 5, iclass 40, count 0 2006.257.04:12:56.99#ibcon#read 5, iclass 40, count 0 2006.257.04:12:56.99#ibcon#about to read 6, iclass 40, count 0 2006.257.04:12:56.99#ibcon#read 6, iclass 40, count 0 2006.257.04:12:56.99#ibcon#end of sib2, iclass 40, count 0 2006.257.04:12:56.99#ibcon#*mode == 0, iclass 40, count 0 2006.257.04:12:56.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.04:12:56.99#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.04:12:56.99#ibcon#*before write, iclass 40, count 0 2006.257.04:12:56.99#ibcon#enter sib2, iclass 40, count 0 2006.257.04:12:56.99#ibcon#flushed, iclass 40, count 0 2006.257.04:12:56.99#ibcon#about to write, iclass 40, count 0 2006.257.04:12:56.99#ibcon#wrote, iclass 40, count 0 2006.257.04:12:56.99#ibcon#about to read 3, iclass 40, count 0 2006.257.04:12:57.03#ibcon#read 3, iclass 40, count 0 2006.257.04:12:57.03#ibcon#about to read 4, iclass 40, count 0 2006.257.04:12:57.03#ibcon#read 4, iclass 40, count 0 2006.257.04:12:57.03#ibcon#about to read 5, iclass 40, count 0 2006.257.04:12:57.03#ibcon#read 5, iclass 40, count 0 2006.257.04:12:57.03#ibcon#about to read 6, iclass 40, count 0 2006.257.04:12:57.03#ibcon#read 6, iclass 40, count 0 2006.257.04:12:57.03#ibcon#end of sib2, iclass 40, count 0 2006.257.04:12:57.03#ibcon#*after write, iclass 40, count 0 2006.257.04:12:57.03#ibcon#*before return 0, iclass 40, count 0 2006.257.04:12:57.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:57.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:12:57.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.04:12:57.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.04:12:57.03$vck44/vb=4,5 2006.257.04:12:57.03#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.04:12:57.03#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.04:12:57.03#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:57.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:57.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:57.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:57.09#ibcon#enter wrdev, iclass 4, count 2 2006.257.04:12:57.09#ibcon#first serial, iclass 4, count 2 2006.257.04:12:57.09#ibcon#enter sib2, iclass 4, count 2 2006.257.04:12:57.09#ibcon#flushed, iclass 4, count 2 2006.257.04:12:57.09#ibcon#about to write, iclass 4, count 2 2006.257.04:12:57.09#ibcon#wrote, iclass 4, count 2 2006.257.04:12:57.09#ibcon#about to read 3, iclass 4, count 2 2006.257.04:12:57.11#ibcon#read 3, iclass 4, count 2 2006.257.04:12:57.11#ibcon#about to read 4, iclass 4, count 2 2006.257.04:12:57.11#ibcon#read 4, iclass 4, count 2 2006.257.04:12:57.11#ibcon#about to read 5, iclass 4, count 2 2006.257.04:12:57.11#ibcon#read 5, iclass 4, count 2 2006.257.04:12:57.11#ibcon#about to read 6, iclass 4, count 2 2006.257.04:12:57.11#ibcon#read 6, iclass 4, count 2 2006.257.04:12:57.11#ibcon#end of sib2, iclass 4, count 2 2006.257.04:12:57.11#ibcon#*mode == 0, iclass 4, count 2 2006.257.04:12:57.11#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.04:12:57.11#ibcon#[27=AT04-05\r\n] 2006.257.04:12:57.11#ibcon#*before write, iclass 4, count 2 2006.257.04:12:57.11#ibcon#enter sib2, iclass 4, count 2 2006.257.04:12:57.11#ibcon#flushed, iclass 4, count 2 2006.257.04:12:57.11#ibcon#about to write, iclass 4, count 2 2006.257.04:12:57.11#ibcon#wrote, iclass 4, count 2 2006.257.04:12:57.11#ibcon#about to read 3, iclass 4, count 2 2006.257.04:12:57.14#ibcon#read 3, iclass 4, count 2 2006.257.04:12:57.14#ibcon#about to read 4, iclass 4, count 2 2006.257.04:12:57.14#ibcon#read 4, iclass 4, count 2 2006.257.04:12:57.14#ibcon#about to read 5, iclass 4, count 2 2006.257.04:12:57.14#ibcon#read 5, iclass 4, count 2 2006.257.04:12:57.14#ibcon#about to read 6, iclass 4, count 2 2006.257.04:12:57.14#ibcon#read 6, iclass 4, count 2 2006.257.04:12:57.14#ibcon#end of sib2, iclass 4, count 2 2006.257.04:12:57.14#ibcon#*after write, iclass 4, count 2 2006.257.04:12:57.14#ibcon#*before return 0, iclass 4, count 2 2006.257.04:12:57.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:57.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:12:57.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.04:12:57.14#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:57.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:57.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:57.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:57.26#ibcon#enter wrdev, iclass 4, count 0 2006.257.04:12:57.26#ibcon#first serial, iclass 4, count 0 2006.257.04:12:57.26#ibcon#enter sib2, iclass 4, count 0 2006.257.04:12:57.26#ibcon#flushed, iclass 4, count 0 2006.257.04:12:57.26#ibcon#about to write, iclass 4, count 0 2006.257.04:12:57.26#ibcon#wrote, iclass 4, count 0 2006.257.04:12:57.26#ibcon#about to read 3, iclass 4, count 0 2006.257.04:12:57.28#ibcon#read 3, iclass 4, count 0 2006.257.04:12:57.28#ibcon#about to read 4, iclass 4, count 0 2006.257.04:12:57.28#ibcon#read 4, iclass 4, count 0 2006.257.04:12:57.28#ibcon#about to read 5, iclass 4, count 0 2006.257.04:12:57.28#ibcon#read 5, iclass 4, count 0 2006.257.04:12:57.28#ibcon#about to read 6, iclass 4, count 0 2006.257.04:12:57.28#ibcon#read 6, iclass 4, count 0 2006.257.04:12:57.28#ibcon#end of sib2, iclass 4, count 0 2006.257.04:12:57.28#ibcon#*mode == 0, iclass 4, count 0 2006.257.04:12:57.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.04:12:57.28#ibcon#[27=USB\r\n] 2006.257.04:12:57.28#ibcon#*before write, iclass 4, count 0 2006.257.04:12:57.28#ibcon#enter sib2, iclass 4, count 0 2006.257.04:12:57.28#ibcon#flushed, iclass 4, count 0 2006.257.04:12:57.28#ibcon#about to write, iclass 4, count 0 2006.257.04:12:57.28#ibcon#wrote, iclass 4, count 0 2006.257.04:12:57.28#ibcon#about to read 3, iclass 4, count 0 2006.257.04:12:57.31#ibcon#read 3, iclass 4, count 0 2006.257.04:12:57.31#ibcon#about to read 4, iclass 4, count 0 2006.257.04:12:57.31#ibcon#read 4, iclass 4, count 0 2006.257.04:12:57.31#ibcon#about to read 5, iclass 4, count 0 2006.257.04:12:57.31#ibcon#read 5, iclass 4, count 0 2006.257.04:12:57.31#ibcon#about to read 6, iclass 4, count 0 2006.257.04:12:57.31#ibcon#read 6, iclass 4, count 0 2006.257.04:12:57.31#ibcon#end of sib2, iclass 4, count 0 2006.257.04:12:57.31#ibcon#*after write, iclass 4, count 0 2006.257.04:12:57.31#ibcon#*before return 0, iclass 4, count 0 2006.257.04:12:57.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:57.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:12:57.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.04:12:57.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.04:12:57.31$vck44/vblo=5,709.99 2006.257.04:12:57.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.04:12:57.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.04:12:57.31#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:57.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:57.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:57.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:57.31#ibcon#enter wrdev, iclass 6, count 0 2006.257.04:12:57.31#ibcon#first serial, iclass 6, count 0 2006.257.04:12:57.31#ibcon#enter sib2, iclass 6, count 0 2006.257.04:12:57.31#ibcon#flushed, iclass 6, count 0 2006.257.04:12:57.31#ibcon#about to write, iclass 6, count 0 2006.257.04:12:57.31#ibcon#wrote, iclass 6, count 0 2006.257.04:12:57.31#ibcon#about to read 3, iclass 6, count 0 2006.257.04:12:57.33#ibcon#read 3, iclass 6, count 0 2006.257.04:12:57.33#ibcon#about to read 4, iclass 6, count 0 2006.257.04:12:57.33#ibcon#read 4, iclass 6, count 0 2006.257.04:12:57.33#ibcon#about to read 5, iclass 6, count 0 2006.257.04:12:57.33#ibcon#read 5, iclass 6, count 0 2006.257.04:12:57.33#ibcon#about to read 6, iclass 6, count 0 2006.257.04:12:57.33#ibcon#read 6, iclass 6, count 0 2006.257.04:12:57.33#ibcon#end of sib2, iclass 6, count 0 2006.257.04:12:57.33#ibcon#*mode == 0, iclass 6, count 0 2006.257.04:12:57.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.04:12:57.33#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.04:12:57.33#ibcon#*before write, iclass 6, count 0 2006.257.04:12:57.33#ibcon#enter sib2, iclass 6, count 0 2006.257.04:12:57.33#ibcon#flushed, iclass 6, count 0 2006.257.04:12:57.33#ibcon#about to write, iclass 6, count 0 2006.257.04:12:57.33#ibcon#wrote, iclass 6, count 0 2006.257.04:12:57.33#ibcon#about to read 3, iclass 6, count 0 2006.257.04:12:57.37#ibcon#read 3, iclass 6, count 0 2006.257.04:12:57.37#ibcon#about to read 4, iclass 6, count 0 2006.257.04:12:57.37#ibcon#read 4, iclass 6, count 0 2006.257.04:12:57.37#ibcon#about to read 5, iclass 6, count 0 2006.257.04:12:57.37#ibcon#read 5, iclass 6, count 0 2006.257.04:12:57.37#ibcon#about to read 6, iclass 6, count 0 2006.257.04:12:57.37#ibcon#read 6, iclass 6, count 0 2006.257.04:12:57.37#ibcon#end of sib2, iclass 6, count 0 2006.257.04:12:57.37#ibcon#*after write, iclass 6, count 0 2006.257.04:12:57.37#ibcon#*before return 0, iclass 6, count 0 2006.257.04:12:57.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:57.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:12:57.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.04:12:57.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.04:12:57.37$vck44/vb=5,4 2006.257.04:12:57.37#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.04:12:57.37#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.04:12:57.37#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:57.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:57.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:57.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:57.43#ibcon#enter wrdev, iclass 10, count 2 2006.257.04:12:57.43#ibcon#first serial, iclass 10, count 2 2006.257.04:12:57.43#ibcon#enter sib2, iclass 10, count 2 2006.257.04:12:57.43#ibcon#flushed, iclass 10, count 2 2006.257.04:12:57.43#ibcon#about to write, iclass 10, count 2 2006.257.04:12:57.43#ibcon#wrote, iclass 10, count 2 2006.257.04:12:57.43#ibcon#about to read 3, iclass 10, count 2 2006.257.04:12:57.45#ibcon#read 3, iclass 10, count 2 2006.257.04:12:57.45#ibcon#about to read 4, iclass 10, count 2 2006.257.04:12:57.45#ibcon#read 4, iclass 10, count 2 2006.257.04:12:57.45#ibcon#about to read 5, iclass 10, count 2 2006.257.04:12:57.45#ibcon#read 5, iclass 10, count 2 2006.257.04:12:57.45#ibcon#about to read 6, iclass 10, count 2 2006.257.04:12:57.45#ibcon#read 6, iclass 10, count 2 2006.257.04:12:57.45#ibcon#end of sib2, iclass 10, count 2 2006.257.04:12:57.45#ibcon#*mode == 0, iclass 10, count 2 2006.257.04:12:57.45#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.04:12:57.45#ibcon#[27=AT05-04\r\n] 2006.257.04:12:57.45#ibcon#*before write, iclass 10, count 2 2006.257.04:12:57.45#ibcon#enter sib2, iclass 10, count 2 2006.257.04:12:57.45#ibcon#flushed, iclass 10, count 2 2006.257.04:12:57.45#ibcon#about to write, iclass 10, count 2 2006.257.04:12:57.45#ibcon#wrote, iclass 10, count 2 2006.257.04:12:57.45#ibcon#about to read 3, iclass 10, count 2 2006.257.04:12:57.48#ibcon#read 3, iclass 10, count 2 2006.257.04:12:57.48#ibcon#about to read 4, iclass 10, count 2 2006.257.04:12:57.48#ibcon#read 4, iclass 10, count 2 2006.257.04:12:57.48#ibcon#about to read 5, iclass 10, count 2 2006.257.04:12:57.48#ibcon#read 5, iclass 10, count 2 2006.257.04:12:57.48#ibcon#about to read 6, iclass 10, count 2 2006.257.04:12:57.48#ibcon#read 6, iclass 10, count 2 2006.257.04:12:57.48#ibcon#end of sib2, iclass 10, count 2 2006.257.04:12:57.48#ibcon#*after write, iclass 10, count 2 2006.257.04:12:57.48#ibcon#*before return 0, iclass 10, count 2 2006.257.04:12:57.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:57.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:12:57.48#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.04:12:57.48#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:57.48#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:57.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:57.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:57.60#ibcon#enter wrdev, iclass 10, count 0 2006.257.04:12:57.60#ibcon#first serial, iclass 10, count 0 2006.257.04:12:57.60#ibcon#enter sib2, iclass 10, count 0 2006.257.04:12:57.60#ibcon#flushed, iclass 10, count 0 2006.257.04:12:57.60#ibcon#about to write, iclass 10, count 0 2006.257.04:12:57.60#ibcon#wrote, iclass 10, count 0 2006.257.04:12:57.60#ibcon#about to read 3, iclass 10, count 0 2006.257.04:12:57.62#ibcon#read 3, iclass 10, count 0 2006.257.04:12:57.62#ibcon#about to read 4, iclass 10, count 0 2006.257.04:12:57.62#ibcon#read 4, iclass 10, count 0 2006.257.04:12:57.62#ibcon#about to read 5, iclass 10, count 0 2006.257.04:12:57.62#ibcon#read 5, iclass 10, count 0 2006.257.04:12:57.62#ibcon#about to read 6, iclass 10, count 0 2006.257.04:12:57.62#ibcon#read 6, iclass 10, count 0 2006.257.04:12:57.62#ibcon#end of sib2, iclass 10, count 0 2006.257.04:12:57.62#ibcon#*mode == 0, iclass 10, count 0 2006.257.04:12:57.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.04:12:57.62#ibcon#[27=USB\r\n] 2006.257.04:12:57.62#ibcon#*before write, iclass 10, count 0 2006.257.04:12:57.62#ibcon#enter sib2, iclass 10, count 0 2006.257.04:12:57.62#ibcon#flushed, iclass 10, count 0 2006.257.04:12:57.62#ibcon#about to write, iclass 10, count 0 2006.257.04:12:57.62#ibcon#wrote, iclass 10, count 0 2006.257.04:12:57.62#ibcon#about to read 3, iclass 10, count 0 2006.257.04:12:57.65#ibcon#read 3, iclass 10, count 0 2006.257.04:12:57.65#ibcon#about to read 4, iclass 10, count 0 2006.257.04:12:57.65#ibcon#read 4, iclass 10, count 0 2006.257.04:12:57.65#ibcon#about to read 5, iclass 10, count 0 2006.257.04:12:57.65#ibcon#read 5, iclass 10, count 0 2006.257.04:12:57.65#ibcon#about to read 6, iclass 10, count 0 2006.257.04:12:57.65#ibcon#read 6, iclass 10, count 0 2006.257.04:12:57.65#ibcon#end of sib2, iclass 10, count 0 2006.257.04:12:57.65#ibcon#*after write, iclass 10, count 0 2006.257.04:12:57.65#ibcon#*before return 0, iclass 10, count 0 2006.257.04:12:57.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:57.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:12:57.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.04:12:57.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.04:12:57.65$vck44/vblo=6,719.99 2006.257.04:12:57.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.04:12:57.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.04:12:57.65#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:57.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:57.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:57.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:57.65#ibcon#enter wrdev, iclass 12, count 0 2006.257.04:12:57.65#ibcon#first serial, iclass 12, count 0 2006.257.04:12:57.65#ibcon#enter sib2, iclass 12, count 0 2006.257.04:12:57.65#ibcon#flushed, iclass 12, count 0 2006.257.04:12:57.65#ibcon#about to write, iclass 12, count 0 2006.257.04:12:57.65#ibcon#wrote, iclass 12, count 0 2006.257.04:12:57.65#ibcon#about to read 3, iclass 12, count 0 2006.257.04:12:57.67#ibcon#read 3, iclass 12, count 0 2006.257.04:12:57.67#ibcon#about to read 4, iclass 12, count 0 2006.257.04:12:57.67#ibcon#read 4, iclass 12, count 0 2006.257.04:12:57.67#ibcon#about to read 5, iclass 12, count 0 2006.257.04:12:57.67#ibcon#read 5, iclass 12, count 0 2006.257.04:12:57.67#ibcon#about to read 6, iclass 12, count 0 2006.257.04:12:57.67#ibcon#read 6, iclass 12, count 0 2006.257.04:12:57.67#ibcon#end of sib2, iclass 12, count 0 2006.257.04:12:57.67#ibcon#*mode == 0, iclass 12, count 0 2006.257.04:12:57.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.04:12:57.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.04:12:57.67#ibcon#*before write, iclass 12, count 0 2006.257.04:12:57.67#ibcon#enter sib2, iclass 12, count 0 2006.257.04:12:57.67#ibcon#flushed, iclass 12, count 0 2006.257.04:12:57.67#ibcon#about to write, iclass 12, count 0 2006.257.04:12:57.67#ibcon#wrote, iclass 12, count 0 2006.257.04:12:57.67#ibcon#about to read 3, iclass 12, count 0 2006.257.04:12:57.71#ibcon#read 3, iclass 12, count 0 2006.257.04:12:57.71#ibcon#about to read 4, iclass 12, count 0 2006.257.04:12:57.71#ibcon#read 4, iclass 12, count 0 2006.257.04:12:57.71#ibcon#about to read 5, iclass 12, count 0 2006.257.04:12:57.71#ibcon#read 5, iclass 12, count 0 2006.257.04:12:57.71#ibcon#about to read 6, iclass 12, count 0 2006.257.04:12:57.71#ibcon#read 6, iclass 12, count 0 2006.257.04:12:57.71#ibcon#end of sib2, iclass 12, count 0 2006.257.04:12:57.71#ibcon#*after write, iclass 12, count 0 2006.257.04:12:57.71#ibcon#*before return 0, iclass 12, count 0 2006.257.04:12:57.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:57.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:12:57.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.04:12:57.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.04:12:57.71$vck44/vb=6,4 2006.257.04:12:57.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.04:12:57.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.04:12:57.71#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:57.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:57.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:57.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:57.77#ibcon#enter wrdev, iclass 14, count 2 2006.257.04:12:57.77#ibcon#first serial, iclass 14, count 2 2006.257.04:12:57.77#ibcon#enter sib2, iclass 14, count 2 2006.257.04:12:57.77#ibcon#flushed, iclass 14, count 2 2006.257.04:12:57.77#ibcon#about to write, iclass 14, count 2 2006.257.04:12:57.77#ibcon#wrote, iclass 14, count 2 2006.257.04:12:57.77#ibcon#about to read 3, iclass 14, count 2 2006.257.04:12:57.79#ibcon#read 3, iclass 14, count 2 2006.257.04:12:57.79#ibcon#about to read 4, iclass 14, count 2 2006.257.04:12:57.79#ibcon#read 4, iclass 14, count 2 2006.257.04:12:57.79#ibcon#about to read 5, iclass 14, count 2 2006.257.04:12:57.79#ibcon#read 5, iclass 14, count 2 2006.257.04:12:57.79#ibcon#about to read 6, iclass 14, count 2 2006.257.04:12:57.79#ibcon#read 6, iclass 14, count 2 2006.257.04:12:57.79#ibcon#end of sib2, iclass 14, count 2 2006.257.04:12:57.79#ibcon#*mode == 0, iclass 14, count 2 2006.257.04:12:57.79#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.04:12:57.79#ibcon#[27=AT06-04\r\n] 2006.257.04:12:57.79#ibcon#*before write, iclass 14, count 2 2006.257.04:12:57.79#ibcon#enter sib2, iclass 14, count 2 2006.257.04:12:57.79#ibcon#flushed, iclass 14, count 2 2006.257.04:12:57.79#ibcon#about to write, iclass 14, count 2 2006.257.04:12:57.79#ibcon#wrote, iclass 14, count 2 2006.257.04:12:57.79#ibcon#about to read 3, iclass 14, count 2 2006.257.04:12:57.82#ibcon#read 3, iclass 14, count 2 2006.257.04:12:57.82#ibcon#about to read 4, iclass 14, count 2 2006.257.04:12:57.82#ibcon#read 4, iclass 14, count 2 2006.257.04:12:57.82#ibcon#about to read 5, iclass 14, count 2 2006.257.04:12:57.82#ibcon#read 5, iclass 14, count 2 2006.257.04:12:57.82#ibcon#about to read 6, iclass 14, count 2 2006.257.04:12:57.82#ibcon#read 6, iclass 14, count 2 2006.257.04:12:57.82#ibcon#end of sib2, iclass 14, count 2 2006.257.04:12:57.82#ibcon#*after write, iclass 14, count 2 2006.257.04:12:57.82#ibcon#*before return 0, iclass 14, count 2 2006.257.04:12:57.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:57.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:12:57.82#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.04:12:57.82#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:57.82#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:57.94#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:57.94#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:57.94#ibcon#enter wrdev, iclass 14, count 0 2006.257.04:12:57.94#ibcon#first serial, iclass 14, count 0 2006.257.04:12:57.94#ibcon#enter sib2, iclass 14, count 0 2006.257.04:12:57.94#ibcon#flushed, iclass 14, count 0 2006.257.04:12:57.94#ibcon#about to write, iclass 14, count 0 2006.257.04:12:57.94#ibcon#wrote, iclass 14, count 0 2006.257.04:12:57.94#ibcon#about to read 3, iclass 14, count 0 2006.257.04:12:57.96#ibcon#read 3, iclass 14, count 0 2006.257.04:12:57.96#ibcon#about to read 4, iclass 14, count 0 2006.257.04:12:57.96#ibcon#read 4, iclass 14, count 0 2006.257.04:12:57.96#ibcon#about to read 5, iclass 14, count 0 2006.257.04:12:57.96#ibcon#read 5, iclass 14, count 0 2006.257.04:12:57.96#ibcon#about to read 6, iclass 14, count 0 2006.257.04:12:57.96#ibcon#read 6, iclass 14, count 0 2006.257.04:12:57.96#ibcon#end of sib2, iclass 14, count 0 2006.257.04:12:57.96#ibcon#*mode == 0, iclass 14, count 0 2006.257.04:12:57.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.04:12:57.96#ibcon#[27=USB\r\n] 2006.257.04:12:57.96#ibcon#*before write, iclass 14, count 0 2006.257.04:12:57.96#ibcon#enter sib2, iclass 14, count 0 2006.257.04:12:57.96#ibcon#flushed, iclass 14, count 0 2006.257.04:12:57.96#ibcon#about to write, iclass 14, count 0 2006.257.04:12:57.96#ibcon#wrote, iclass 14, count 0 2006.257.04:12:57.96#ibcon#about to read 3, iclass 14, count 0 2006.257.04:12:57.99#ibcon#read 3, iclass 14, count 0 2006.257.04:12:57.99#ibcon#about to read 4, iclass 14, count 0 2006.257.04:12:57.99#ibcon#read 4, iclass 14, count 0 2006.257.04:12:57.99#ibcon#about to read 5, iclass 14, count 0 2006.257.04:12:57.99#ibcon#read 5, iclass 14, count 0 2006.257.04:12:57.99#ibcon#about to read 6, iclass 14, count 0 2006.257.04:12:57.99#ibcon#read 6, iclass 14, count 0 2006.257.04:12:57.99#ibcon#end of sib2, iclass 14, count 0 2006.257.04:12:57.99#ibcon#*after write, iclass 14, count 0 2006.257.04:12:57.99#ibcon#*before return 0, iclass 14, count 0 2006.257.04:12:57.99#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:57.99#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:12:57.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.04:12:57.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.04:12:57.99$vck44/vblo=7,734.99 2006.257.04:12:57.99#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.04:12:57.99#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.04:12:57.99#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:57.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:57.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:57.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:57.99#ibcon#enter wrdev, iclass 16, count 0 2006.257.04:12:57.99#ibcon#first serial, iclass 16, count 0 2006.257.04:12:57.99#ibcon#enter sib2, iclass 16, count 0 2006.257.04:12:57.99#ibcon#flushed, iclass 16, count 0 2006.257.04:12:57.99#ibcon#about to write, iclass 16, count 0 2006.257.04:12:57.99#ibcon#wrote, iclass 16, count 0 2006.257.04:12:57.99#ibcon#about to read 3, iclass 16, count 0 2006.257.04:12:58.01#ibcon#read 3, iclass 16, count 0 2006.257.04:12:58.01#ibcon#about to read 4, iclass 16, count 0 2006.257.04:12:58.01#ibcon#read 4, iclass 16, count 0 2006.257.04:12:58.01#ibcon#about to read 5, iclass 16, count 0 2006.257.04:12:58.01#ibcon#read 5, iclass 16, count 0 2006.257.04:12:58.01#ibcon#about to read 6, iclass 16, count 0 2006.257.04:12:58.01#ibcon#read 6, iclass 16, count 0 2006.257.04:12:58.01#ibcon#end of sib2, iclass 16, count 0 2006.257.04:12:58.01#ibcon#*mode == 0, iclass 16, count 0 2006.257.04:12:58.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.04:12:58.01#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.04:12:58.01#ibcon#*before write, iclass 16, count 0 2006.257.04:12:58.01#ibcon#enter sib2, iclass 16, count 0 2006.257.04:12:58.01#ibcon#flushed, iclass 16, count 0 2006.257.04:12:58.01#ibcon#about to write, iclass 16, count 0 2006.257.04:12:58.01#ibcon#wrote, iclass 16, count 0 2006.257.04:12:58.01#ibcon#about to read 3, iclass 16, count 0 2006.257.04:12:58.05#ibcon#read 3, iclass 16, count 0 2006.257.04:12:58.05#ibcon#about to read 4, iclass 16, count 0 2006.257.04:12:58.05#ibcon#read 4, iclass 16, count 0 2006.257.04:12:58.05#ibcon#about to read 5, iclass 16, count 0 2006.257.04:12:58.05#ibcon#read 5, iclass 16, count 0 2006.257.04:12:58.05#ibcon#about to read 6, iclass 16, count 0 2006.257.04:12:58.05#ibcon#read 6, iclass 16, count 0 2006.257.04:12:58.05#ibcon#end of sib2, iclass 16, count 0 2006.257.04:12:58.05#ibcon#*after write, iclass 16, count 0 2006.257.04:12:58.05#ibcon#*before return 0, iclass 16, count 0 2006.257.04:12:58.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:58.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:12:58.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.04:12:58.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.04:12:58.05$vck44/vb=7,4 2006.257.04:12:58.05#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.04:12:58.05#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.04:12:58.05#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:58.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:58.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:58.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:58.11#ibcon#enter wrdev, iclass 18, count 2 2006.257.04:12:58.11#ibcon#first serial, iclass 18, count 2 2006.257.04:12:58.11#ibcon#enter sib2, iclass 18, count 2 2006.257.04:12:58.11#ibcon#flushed, iclass 18, count 2 2006.257.04:12:58.11#ibcon#about to write, iclass 18, count 2 2006.257.04:12:58.11#ibcon#wrote, iclass 18, count 2 2006.257.04:12:58.11#ibcon#about to read 3, iclass 18, count 2 2006.257.04:12:58.13#ibcon#read 3, iclass 18, count 2 2006.257.04:12:58.13#ibcon#about to read 4, iclass 18, count 2 2006.257.04:12:58.13#ibcon#read 4, iclass 18, count 2 2006.257.04:12:58.13#ibcon#about to read 5, iclass 18, count 2 2006.257.04:12:58.13#ibcon#read 5, iclass 18, count 2 2006.257.04:12:58.13#ibcon#about to read 6, iclass 18, count 2 2006.257.04:12:58.13#ibcon#read 6, iclass 18, count 2 2006.257.04:12:58.13#ibcon#end of sib2, iclass 18, count 2 2006.257.04:12:58.13#ibcon#*mode == 0, iclass 18, count 2 2006.257.04:12:58.13#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.04:12:58.13#ibcon#[27=AT07-04\r\n] 2006.257.04:12:58.13#ibcon#*before write, iclass 18, count 2 2006.257.04:12:58.13#ibcon#enter sib2, iclass 18, count 2 2006.257.04:12:58.13#ibcon#flushed, iclass 18, count 2 2006.257.04:12:58.13#ibcon#about to write, iclass 18, count 2 2006.257.04:12:58.13#ibcon#wrote, iclass 18, count 2 2006.257.04:12:58.13#ibcon#about to read 3, iclass 18, count 2 2006.257.04:12:58.16#ibcon#read 3, iclass 18, count 2 2006.257.04:12:58.16#ibcon#about to read 4, iclass 18, count 2 2006.257.04:12:58.16#ibcon#read 4, iclass 18, count 2 2006.257.04:12:58.16#ibcon#about to read 5, iclass 18, count 2 2006.257.04:12:58.16#ibcon#read 5, iclass 18, count 2 2006.257.04:12:58.16#ibcon#about to read 6, iclass 18, count 2 2006.257.04:12:58.16#ibcon#read 6, iclass 18, count 2 2006.257.04:12:58.16#ibcon#end of sib2, iclass 18, count 2 2006.257.04:12:58.16#ibcon#*after write, iclass 18, count 2 2006.257.04:12:58.16#ibcon#*before return 0, iclass 18, count 2 2006.257.04:12:58.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:58.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:12:58.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.04:12:58.16#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:58.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:58.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:58.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:58.28#ibcon#enter wrdev, iclass 18, count 0 2006.257.04:12:58.28#ibcon#first serial, iclass 18, count 0 2006.257.04:12:58.28#ibcon#enter sib2, iclass 18, count 0 2006.257.04:12:58.28#ibcon#flushed, iclass 18, count 0 2006.257.04:12:58.28#ibcon#about to write, iclass 18, count 0 2006.257.04:12:58.28#ibcon#wrote, iclass 18, count 0 2006.257.04:12:58.28#ibcon#about to read 3, iclass 18, count 0 2006.257.04:12:58.30#ibcon#read 3, iclass 18, count 0 2006.257.04:12:58.30#ibcon#about to read 4, iclass 18, count 0 2006.257.04:12:58.30#ibcon#read 4, iclass 18, count 0 2006.257.04:12:58.30#ibcon#about to read 5, iclass 18, count 0 2006.257.04:12:58.30#ibcon#read 5, iclass 18, count 0 2006.257.04:12:58.30#ibcon#about to read 6, iclass 18, count 0 2006.257.04:12:58.30#ibcon#read 6, iclass 18, count 0 2006.257.04:12:58.30#ibcon#end of sib2, iclass 18, count 0 2006.257.04:12:58.30#ibcon#*mode == 0, iclass 18, count 0 2006.257.04:12:58.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.04:12:58.30#ibcon#[27=USB\r\n] 2006.257.04:12:58.30#ibcon#*before write, iclass 18, count 0 2006.257.04:12:58.30#ibcon#enter sib2, iclass 18, count 0 2006.257.04:12:58.30#ibcon#flushed, iclass 18, count 0 2006.257.04:12:58.30#ibcon#about to write, iclass 18, count 0 2006.257.04:12:58.30#ibcon#wrote, iclass 18, count 0 2006.257.04:12:58.30#ibcon#about to read 3, iclass 18, count 0 2006.257.04:12:58.33#ibcon#read 3, iclass 18, count 0 2006.257.04:12:58.33#ibcon#about to read 4, iclass 18, count 0 2006.257.04:12:58.33#ibcon#read 4, iclass 18, count 0 2006.257.04:12:58.33#ibcon#about to read 5, iclass 18, count 0 2006.257.04:12:58.33#ibcon#read 5, iclass 18, count 0 2006.257.04:12:58.33#ibcon#about to read 6, iclass 18, count 0 2006.257.04:12:58.33#ibcon#read 6, iclass 18, count 0 2006.257.04:12:58.33#ibcon#end of sib2, iclass 18, count 0 2006.257.04:12:58.33#ibcon#*after write, iclass 18, count 0 2006.257.04:12:58.33#ibcon#*before return 0, iclass 18, count 0 2006.257.04:12:58.33#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:58.33#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:12:58.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.04:12:58.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.04:12:58.33$vck44/vblo=8,744.99 2006.257.04:12:58.33#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.04:12:58.33#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.04:12:58.33#ibcon#ireg 17 cls_cnt 0 2006.257.04:12:58.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:58.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:58.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:58.33#ibcon#enter wrdev, iclass 20, count 0 2006.257.04:12:58.33#ibcon#first serial, iclass 20, count 0 2006.257.04:12:58.33#ibcon#enter sib2, iclass 20, count 0 2006.257.04:12:58.33#ibcon#flushed, iclass 20, count 0 2006.257.04:12:58.33#ibcon#about to write, iclass 20, count 0 2006.257.04:12:58.33#ibcon#wrote, iclass 20, count 0 2006.257.04:12:58.33#ibcon#about to read 3, iclass 20, count 0 2006.257.04:12:58.35#ibcon#read 3, iclass 20, count 0 2006.257.04:12:58.35#ibcon#about to read 4, iclass 20, count 0 2006.257.04:12:58.35#ibcon#read 4, iclass 20, count 0 2006.257.04:12:58.35#ibcon#about to read 5, iclass 20, count 0 2006.257.04:12:58.35#ibcon#read 5, iclass 20, count 0 2006.257.04:12:58.35#ibcon#about to read 6, iclass 20, count 0 2006.257.04:12:58.35#ibcon#read 6, iclass 20, count 0 2006.257.04:12:58.35#ibcon#end of sib2, iclass 20, count 0 2006.257.04:12:58.35#ibcon#*mode == 0, iclass 20, count 0 2006.257.04:12:58.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.04:12:58.35#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.04:12:58.35#ibcon#*before write, iclass 20, count 0 2006.257.04:12:58.35#ibcon#enter sib2, iclass 20, count 0 2006.257.04:12:58.35#ibcon#flushed, iclass 20, count 0 2006.257.04:12:58.35#ibcon#about to write, iclass 20, count 0 2006.257.04:12:58.35#ibcon#wrote, iclass 20, count 0 2006.257.04:12:58.35#ibcon#about to read 3, iclass 20, count 0 2006.257.04:12:58.39#ibcon#read 3, iclass 20, count 0 2006.257.04:12:58.39#ibcon#about to read 4, iclass 20, count 0 2006.257.04:12:58.39#ibcon#read 4, iclass 20, count 0 2006.257.04:12:58.39#ibcon#about to read 5, iclass 20, count 0 2006.257.04:12:58.39#ibcon#read 5, iclass 20, count 0 2006.257.04:12:58.39#ibcon#about to read 6, iclass 20, count 0 2006.257.04:12:58.39#ibcon#read 6, iclass 20, count 0 2006.257.04:12:58.39#ibcon#end of sib2, iclass 20, count 0 2006.257.04:12:58.39#ibcon#*after write, iclass 20, count 0 2006.257.04:12:58.39#ibcon#*before return 0, iclass 20, count 0 2006.257.04:12:58.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:58.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:12:58.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.04:12:58.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.04:12:58.39$vck44/vb=8,4 2006.257.04:12:58.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.04:12:58.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.04:12:58.39#ibcon#ireg 11 cls_cnt 2 2006.257.04:12:58.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:58.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:58.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:58.45#ibcon#enter wrdev, iclass 22, count 2 2006.257.04:12:58.45#ibcon#first serial, iclass 22, count 2 2006.257.04:12:58.45#ibcon#enter sib2, iclass 22, count 2 2006.257.04:12:58.45#ibcon#flushed, iclass 22, count 2 2006.257.04:12:58.45#ibcon#about to write, iclass 22, count 2 2006.257.04:12:58.45#ibcon#wrote, iclass 22, count 2 2006.257.04:12:58.45#ibcon#about to read 3, iclass 22, count 2 2006.257.04:12:58.47#ibcon#read 3, iclass 22, count 2 2006.257.04:12:58.47#ibcon#about to read 4, iclass 22, count 2 2006.257.04:12:58.47#ibcon#read 4, iclass 22, count 2 2006.257.04:12:58.47#ibcon#about to read 5, iclass 22, count 2 2006.257.04:12:58.47#ibcon#read 5, iclass 22, count 2 2006.257.04:12:58.47#ibcon#about to read 6, iclass 22, count 2 2006.257.04:12:58.47#ibcon#read 6, iclass 22, count 2 2006.257.04:12:58.47#ibcon#end of sib2, iclass 22, count 2 2006.257.04:12:58.47#ibcon#*mode == 0, iclass 22, count 2 2006.257.04:12:58.47#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.04:12:58.47#ibcon#[27=AT08-04\r\n] 2006.257.04:12:58.47#ibcon#*before write, iclass 22, count 2 2006.257.04:12:58.47#ibcon#enter sib2, iclass 22, count 2 2006.257.04:12:58.47#ibcon#flushed, iclass 22, count 2 2006.257.04:12:58.47#ibcon#about to write, iclass 22, count 2 2006.257.04:12:58.47#ibcon#wrote, iclass 22, count 2 2006.257.04:12:58.47#ibcon#about to read 3, iclass 22, count 2 2006.257.04:12:58.50#ibcon#read 3, iclass 22, count 2 2006.257.04:12:58.50#ibcon#about to read 4, iclass 22, count 2 2006.257.04:12:58.50#ibcon#read 4, iclass 22, count 2 2006.257.04:12:58.50#ibcon#about to read 5, iclass 22, count 2 2006.257.04:12:58.50#ibcon#read 5, iclass 22, count 2 2006.257.04:12:58.50#ibcon#about to read 6, iclass 22, count 2 2006.257.04:12:58.50#ibcon#read 6, iclass 22, count 2 2006.257.04:12:58.50#ibcon#end of sib2, iclass 22, count 2 2006.257.04:12:58.50#ibcon#*after write, iclass 22, count 2 2006.257.04:12:58.50#ibcon#*before return 0, iclass 22, count 2 2006.257.04:12:58.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:58.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:12:58.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.04:12:58.50#ibcon#ireg 7 cls_cnt 0 2006.257.04:12:58.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:58.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:58.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:58.62#ibcon#enter wrdev, iclass 22, count 0 2006.257.04:12:58.62#ibcon#first serial, iclass 22, count 0 2006.257.04:12:58.62#ibcon#enter sib2, iclass 22, count 0 2006.257.04:12:58.62#ibcon#flushed, iclass 22, count 0 2006.257.04:12:58.62#ibcon#about to write, iclass 22, count 0 2006.257.04:12:58.62#ibcon#wrote, iclass 22, count 0 2006.257.04:12:58.62#ibcon#about to read 3, iclass 22, count 0 2006.257.04:12:58.64#ibcon#read 3, iclass 22, count 0 2006.257.04:12:58.64#ibcon#about to read 4, iclass 22, count 0 2006.257.04:12:58.64#ibcon#read 4, iclass 22, count 0 2006.257.04:12:58.64#ibcon#about to read 5, iclass 22, count 0 2006.257.04:12:58.64#ibcon#read 5, iclass 22, count 0 2006.257.04:12:58.64#ibcon#about to read 6, iclass 22, count 0 2006.257.04:12:58.64#ibcon#read 6, iclass 22, count 0 2006.257.04:12:58.64#ibcon#end of sib2, iclass 22, count 0 2006.257.04:12:58.64#ibcon#*mode == 0, iclass 22, count 0 2006.257.04:12:58.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.04:12:58.64#ibcon#[27=USB\r\n] 2006.257.04:12:58.64#ibcon#*before write, iclass 22, count 0 2006.257.04:12:58.64#ibcon#enter sib2, iclass 22, count 0 2006.257.04:12:58.64#ibcon#flushed, iclass 22, count 0 2006.257.04:12:58.64#ibcon#about to write, iclass 22, count 0 2006.257.04:12:58.64#ibcon#wrote, iclass 22, count 0 2006.257.04:12:58.64#ibcon#about to read 3, iclass 22, count 0 2006.257.04:12:58.67#ibcon#read 3, iclass 22, count 0 2006.257.04:12:58.67#ibcon#about to read 4, iclass 22, count 0 2006.257.04:12:58.67#ibcon#read 4, iclass 22, count 0 2006.257.04:12:58.67#ibcon#about to read 5, iclass 22, count 0 2006.257.04:12:58.67#ibcon#read 5, iclass 22, count 0 2006.257.04:12:58.67#ibcon#about to read 6, iclass 22, count 0 2006.257.04:12:58.67#ibcon#read 6, iclass 22, count 0 2006.257.04:12:58.67#ibcon#end of sib2, iclass 22, count 0 2006.257.04:12:58.67#ibcon#*after write, iclass 22, count 0 2006.257.04:12:58.67#ibcon#*before return 0, iclass 22, count 0 2006.257.04:12:58.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:58.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:12:58.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.04:12:58.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.04:12:58.67$vck44/vabw=wide 2006.257.04:12:58.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.04:12:58.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.04:12:58.67#ibcon#ireg 8 cls_cnt 0 2006.257.04:12:58.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:58.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:58.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:58.67#ibcon#enter wrdev, iclass 24, count 0 2006.257.04:12:58.67#ibcon#first serial, iclass 24, count 0 2006.257.04:12:58.67#ibcon#enter sib2, iclass 24, count 0 2006.257.04:12:58.67#ibcon#flushed, iclass 24, count 0 2006.257.04:12:58.67#ibcon#about to write, iclass 24, count 0 2006.257.04:12:58.67#ibcon#wrote, iclass 24, count 0 2006.257.04:12:58.67#ibcon#about to read 3, iclass 24, count 0 2006.257.04:12:58.69#ibcon#read 3, iclass 24, count 0 2006.257.04:12:58.69#ibcon#about to read 4, iclass 24, count 0 2006.257.04:12:58.69#ibcon#read 4, iclass 24, count 0 2006.257.04:12:58.69#ibcon#about to read 5, iclass 24, count 0 2006.257.04:12:58.69#ibcon#read 5, iclass 24, count 0 2006.257.04:12:58.69#ibcon#about to read 6, iclass 24, count 0 2006.257.04:12:58.69#ibcon#read 6, iclass 24, count 0 2006.257.04:12:58.69#ibcon#end of sib2, iclass 24, count 0 2006.257.04:12:58.69#ibcon#*mode == 0, iclass 24, count 0 2006.257.04:12:58.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.04:12:58.69#ibcon#[25=BW32\r\n] 2006.257.04:12:58.69#ibcon#*before write, iclass 24, count 0 2006.257.04:12:58.69#ibcon#enter sib2, iclass 24, count 0 2006.257.04:12:58.69#ibcon#flushed, iclass 24, count 0 2006.257.04:12:58.69#ibcon#about to write, iclass 24, count 0 2006.257.04:12:58.69#ibcon#wrote, iclass 24, count 0 2006.257.04:12:58.69#ibcon#about to read 3, iclass 24, count 0 2006.257.04:12:58.72#ibcon#read 3, iclass 24, count 0 2006.257.04:12:58.72#ibcon#about to read 4, iclass 24, count 0 2006.257.04:12:58.72#ibcon#read 4, iclass 24, count 0 2006.257.04:12:58.72#ibcon#about to read 5, iclass 24, count 0 2006.257.04:12:58.72#ibcon#read 5, iclass 24, count 0 2006.257.04:12:58.72#ibcon#about to read 6, iclass 24, count 0 2006.257.04:12:58.72#ibcon#read 6, iclass 24, count 0 2006.257.04:12:58.72#ibcon#end of sib2, iclass 24, count 0 2006.257.04:12:58.72#ibcon#*after write, iclass 24, count 0 2006.257.04:12:58.72#ibcon#*before return 0, iclass 24, count 0 2006.257.04:12:58.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:58.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:12:58.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.04:12:58.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.04:12:58.72$vck44/vbbw=wide 2006.257.04:12:58.72#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.04:12:58.72#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.04:12:58.72#ibcon#ireg 8 cls_cnt 0 2006.257.04:12:58.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:12:58.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:12:58.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:12:58.79#ibcon#enter wrdev, iclass 26, count 0 2006.257.04:12:58.79#ibcon#first serial, iclass 26, count 0 2006.257.04:12:58.79#ibcon#enter sib2, iclass 26, count 0 2006.257.04:12:58.79#ibcon#flushed, iclass 26, count 0 2006.257.04:12:58.79#ibcon#about to write, iclass 26, count 0 2006.257.04:12:58.79#ibcon#wrote, iclass 26, count 0 2006.257.04:12:58.79#ibcon#about to read 3, iclass 26, count 0 2006.257.04:12:58.81#ibcon#read 3, iclass 26, count 0 2006.257.04:12:58.81#ibcon#about to read 4, iclass 26, count 0 2006.257.04:12:58.81#ibcon#read 4, iclass 26, count 0 2006.257.04:12:58.81#ibcon#about to read 5, iclass 26, count 0 2006.257.04:12:58.81#ibcon#read 5, iclass 26, count 0 2006.257.04:12:58.81#ibcon#about to read 6, iclass 26, count 0 2006.257.04:12:58.81#ibcon#read 6, iclass 26, count 0 2006.257.04:12:58.81#ibcon#end of sib2, iclass 26, count 0 2006.257.04:12:58.81#ibcon#*mode == 0, iclass 26, count 0 2006.257.04:12:58.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.04:12:58.81#ibcon#[27=BW32\r\n] 2006.257.04:12:58.81#ibcon#*before write, iclass 26, count 0 2006.257.04:12:58.81#ibcon#enter sib2, iclass 26, count 0 2006.257.04:12:58.81#ibcon#flushed, iclass 26, count 0 2006.257.04:12:58.81#ibcon#about to write, iclass 26, count 0 2006.257.04:12:58.81#ibcon#wrote, iclass 26, count 0 2006.257.04:12:58.81#ibcon#about to read 3, iclass 26, count 0 2006.257.04:12:58.84#ibcon#read 3, iclass 26, count 0 2006.257.04:12:58.84#ibcon#about to read 4, iclass 26, count 0 2006.257.04:12:58.84#ibcon#read 4, iclass 26, count 0 2006.257.04:12:58.84#ibcon#about to read 5, iclass 26, count 0 2006.257.04:12:58.84#ibcon#read 5, iclass 26, count 0 2006.257.04:12:58.84#ibcon#about to read 6, iclass 26, count 0 2006.257.04:12:58.84#ibcon#read 6, iclass 26, count 0 2006.257.04:12:58.84#ibcon#end of sib2, iclass 26, count 0 2006.257.04:12:58.84#ibcon#*after write, iclass 26, count 0 2006.257.04:12:58.84#ibcon#*before return 0, iclass 26, count 0 2006.257.04:12:58.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:12:58.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:12:58.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.04:12:58.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.04:12:58.84$setupk4/ifdk4 2006.257.04:12:58.84$ifdk4/lo= 2006.257.04:12:58.84$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.04:12:58.84$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.04:12:58.84$ifdk4/patch= 2006.257.04:12:58.84$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.04:12:58.84$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.04:12:58.84$setupk4/!*+20s 2006.257.04:13:06.91#abcon#<5=/14 2.1 6.1 19.31 941011.9\r\n> 2006.257.04:13:06.93#abcon#{5=INTERFACE CLEAR} 2006.257.04:13:06.99#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:13:13.34$setupk4/"tpicd 2006.257.04:13:13.34$setupk4/echo=off 2006.257.04:13:13.34$setupk4/xlog=off 2006.257.04:13:13.34:!2006.257.04:15:56 2006.257.04:13:28.13#trakl#Source acquired 2006.257.04:13:28.14#flagr#flagr/antenna,acquired 2006.257.04:15:56.02:preob 2006.257.04:15:57.15/onsource/TRACKING 2006.257.04:15:57.15:!2006.257.04:16:06 2006.257.04:16:06.01:"tape 2006.257.04:16:06.02:"st=record 2006.257.04:16:06.02:data_valid=on 2006.257.04:16:06.02:midob 2006.257.04:16:07.14/onsource/TRACKING 2006.257.04:16:07.15/wx/19.34,1011.9,95 2006.257.04:16:07.35/cable/+6.4842E-03 2006.257.04:16:08.44/va/01,08,usb,yes,31,34 2006.257.04:16:08.44/va/02,07,usb,yes,34,35 2006.257.04:16:08.44/va/03,08,usb,yes,31,32 2006.257.04:16:08.44/va/04,07,usb,yes,35,37 2006.257.04:16:08.44/va/05,04,usb,yes,32,32 2006.257.04:16:08.44/va/06,04,usb,yes,35,35 2006.257.04:16:08.44/va/07,04,usb,yes,36,36 2006.257.04:16:08.44/va/08,04,usb,yes,30,37 2006.257.04:16:08.67/valo/01,524.99,yes,locked 2006.257.04:16:08.67/valo/02,534.99,yes,locked 2006.257.04:16:08.67/valo/03,564.99,yes,locked 2006.257.04:16:08.67/valo/04,624.99,yes,locked 2006.257.04:16:08.67/valo/05,734.99,yes,locked 2006.257.04:16:08.67/valo/06,814.99,yes,locked 2006.257.04:16:08.67/valo/07,864.99,yes,locked 2006.257.04:16:08.67/valo/08,884.99,yes,locked 2006.257.04:16:09.76/vb/01,04,usb,yes,30,28 2006.257.04:16:09.76/vb/02,05,usb,yes,29,29 2006.257.04:16:09.76/vb/03,04,usb,yes,30,33 2006.257.04:16:09.76/vb/04,05,usb,yes,30,29 2006.257.04:16:09.76/vb/05,04,usb,yes,26,29 2006.257.04:16:09.76/vb/06,04,usb,yes,31,27 2006.257.04:16:09.76/vb/07,04,usb,yes,31,31 2006.257.04:16:09.76/vb/08,04,usb,yes,28,32 2006.257.04:16:10.00/vblo/01,629.99,yes,locked 2006.257.04:16:10.00/vblo/02,634.99,yes,locked 2006.257.04:16:10.00/vblo/03,649.99,yes,locked 2006.257.04:16:10.00/vblo/04,679.99,yes,locked 2006.257.04:16:10.00/vblo/05,709.99,yes,locked 2006.257.04:16:10.00/vblo/06,719.99,yes,locked 2006.257.04:16:10.00/vblo/07,734.99,yes,locked 2006.257.04:16:10.00/vblo/08,744.99,yes,locked 2006.257.04:16:10.15/vabw/8 2006.257.04:16:10.30/vbbw/8 2006.257.04:16:10.39/xfe/off,on,16.5 2006.257.04:16:10.76/ifatt/23,28,28,28 2006.257.04:16:11.07/fmout-gps/S +4.55E-07 2006.257.04:16:11.11:!2006.257.04:21:26 2006.257.04:17:32.13#trakl#Off source 2006.257.04:17:32.13?ERROR st -7 Antenna off-source! 2006.257.04:17:32.13#trakl#az 272.170 el 32.584 azerr*cos(el) 0.0030 elerr -0.0188 2006.257.04:17:33.13#flagr#flagr/antenna,off-source 2006.257.04:17:38.13#trakl#Source re-acquired 2006.257.04:17:39.13#flagr#flagr/antenna,re-acquired 2006.257.04:21:26.00:data_valid=off 2006.257.04:21:26.01:"et 2006.257.04:21:26.01:!+3s 2006.257.04:21:29.03:"tape 2006.257.04:21:29.03:postob 2006.257.04:21:29.11/cable/+6.4835E-03 2006.257.04:21:29.12/wx/19.53,1011.9,94 2006.257.04:21:29.17/fmout-gps/S +4.54E-07 2006.257.04:21:29.17:scan_name=257-0425,jd0609,90 2006.257.04:21:29.17:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.04:21:31.14#flagr#flagr/antenna,new-source 2006.257.04:21:31.15:checkk5 2006.257.04:21:31.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.04:21:31.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.04:21:32.39/chk_autoobs//k5ts3/ autoobs is running! 2006.257.04:21:32.81/chk_autoobs//k5ts4/ autoobs is running! 2006.257.04:21:33.21/chk_obsdata//k5ts1/T2570416??a.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.257.04:21:33.61/chk_obsdata//k5ts2/T2570416??b.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.257.04:21:34.01/chk_obsdata//k5ts3/T2570416??c.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.257.04:21:34.42/chk_obsdata//k5ts4/T2570416??d.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.257.04:21:35.16/k5log//k5ts1_log_newline 2006.257.04:21:35.86/k5log//k5ts2_log_newline 2006.257.04:21:36.60/k5log//k5ts3_log_newline 2006.257.04:21:37.31/k5log//k5ts4_log_newline 2006.257.04:21:37.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.04:21:37.33:setupk4=1 2006.257.04:21:37.33$setupk4/echo=on 2006.257.04:21:37.33$setupk4/pcalon 2006.257.04:21:37.33$pcalon/"no phase cal control is implemented here 2006.257.04:21:37.33$setupk4/"tpicd=stop 2006.257.04:21:37.33$setupk4/"rec=synch_on 2006.257.04:21:37.33$setupk4/"rec_mode=128 2006.257.04:21:37.33$setupk4/!* 2006.257.04:21:37.33$setupk4/recpk4 2006.257.04:21:37.33$recpk4/recpatch= 2006.257.04:21:37.34$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.04:21:37.34$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.04:21:37.34$setupk4/vck44 2006.257.04:21:37.34$vck44/valo=1,524.99 2006.257.04:21:37.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.04:21:37.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.04:21:37.34#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:37.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:37.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:37.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:37.34#ibcon#enter wrdev, iclass 21, count 0 2006.257.04:21:37.34#ibcon#first serial, iclass 21, count 0 2006.257.04:21:37.34#ibcon#enter sib2, iclass 21, count 0 2006.257.04:21:37.34#ibcon#flushed, iclass 21, count 0 2006.257.04:21:37.34#ibcon#about to write, iclass 21, count 0 2006.257.04:21:37.34#ibcon#wrote, iclass 21, count 0 2006.257.04:21:37.34#ibcon#about to read 3, iclass 21, count 0 2006.257.04:21:37.35#ibcon#read 3, iclass 21, count 0 2006.257.04:21:37.35#ibcon#about to read 4, iclass 21, count 0 2006.257.04:21:37.35#ibcon#read 4, iclass 21, count 0 2006.257.04:21:37.35#ibcon#about to read 5, iclass 21, count 0 2006.257.04:21:37.35#ibcon#read 5, iclass 21, count 0 2006.257.04:21:37.35#ibcon#about to read 6, iclass 21, count 0 2006.257.04:21:37.35#ibcon#read 6, iclass 21, count 0 2006.257.04:21:37.35#ibcon#end of sib2, iclass 21, count 0 2006.257.04:21:37.35#ibcon#*mode == 0, iclass 21, count 0 2006.257.04:21:37.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.04:21:37.35#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.04:21:37.35#ibcon#*before write, iclass 21, count 0 2006.257.04:21:37.35#ibcon#enter sib2, iclass 21, count 0 2006.257.04:21:37.35#ibcon#flushed, iclass 21, count 0 2006.257.04:21:37.35#ibcon#about to write, iclass 21, count 0 2006.257.04:21:37.35#ibcon#wrote, iclass 21, count 0 2006.257.04:21:37.35#ibcon#about to read 3, iclass 21, count 0 2006.257.04:21:37.40#ibcon#read 3, iclass 21, count 0 2006.257.04:21:37.40#ibcon#about to read 4, iclass 21, count 0 2006.257.04:21:37.40#ibcon#read 4, iclass 21, count 0 2006.257.04:21:37.40#ibcon#about to read 5, iclass 21, count 0 2006.257.04:21:37.40#ibcon#read 5, iclass 21, count 0 2006.257.04:21:37.40#ibcon#about to read 6, iclass 21, count 0 2006.257.04:21:37.40#ibcon#read 6, iclass 21, count 0 2006.257.04:21:37.40#ibcon#end of sib2, iclass 21, count 0 2006.257.04:21:37.40#ibcon#*after write, iclass 21, count 0 2006.257.04:21:37.40#ibcon#*before return 0, iclass 21, count 0 2006.257.04:21:37.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:37.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:37.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.04:21:37.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.04:21:37.40$vck44/va=1,8 2006.257.04:21:37.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.04:21:37.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.04:21:37.40#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:37.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:37.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:37.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:37.40#ibcon#enter wrdev, iclass 23, count 2 2006.257.04:21:37.40#ibcon#first serial, iclass 23, count 2 2006.257.04:21:37.40#ibcon#enter sib2, iclass 23, count 2 2006.257.04:21:37.40#ibcon#flushed, iclass 23, count 2 2006.257.04:21:37.40#ibcon#about to write, iclass 23, count 2 2006.257.04:21:37.40#ibcon#wrote, iclass 23, count 2 2006.257.04:21:37.40#ibcon#about to read 3, iclass 23, count 2 2006.257.04:21:37.42#ibcon#read 3, iclass 23, count 2 2006.257.04:21:37.42#ibcon#about to read 4, iclass 23, count 2 2006.257.04:21:37.42#ibcon#read 4, iclass 23, count 2 2006.257.04:21:37.42#ibcon#about to read 5, iclass 23, count 2 2006.257.04:21:37.42#ibcon#read 5, iclass 23, count 2 2006.257.04:21:37.42#ibcon#about to read 6, iclass 23, count 2 2006.257.04:21:37.42#ibcon#read 6, iclass 23, count 2 2006.257.04:21:37.42#ibcon#end of sib2, iclass 23, count 2 2006.257.04:21:37.42#ibcon#*mode == 0, iclass 23, count 2 2006.257.04:21:37.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.04:21:37.42#ibcon#[25=AT01-08\r\n] 2006.257.04:21:37.42#ibcon#*before write, iclass 23, count 2 2006.257.04:21:37.42#ibcon#enter sib2, iclass 23, count 2 2006.257.04:21:37.42#ibcon#flushed, iclass 23, count 2 2006.257.04:21:37.42#ibcon#about to write, iclass 23, count 2 2006.257.04:21:37.42#ibcon#wrote, iclass 23, count 2 2006.257.04:21:37.42#ibcon#about to read 3, iclass 23, count 2 2006.257.04:21:37.45#ibcon#read 3, iclass 23, count 2 2006.257.04:21:37.45#ibcon#about to read 4, iclass 23, count 2 2006.257.04:21:37.45#ibcon#read 4, iclass 23, count 2 2006.257.04:21:37.45#ibcon#about to read 5, iclass 23, count 2 2006.257.04:21:37.45#ibcon#read 5, iclass 23, count 2 2006.257.04:21:37.45#ibcon#about to read 6, iclass 23, count 2 2006.257.04:21:37.45#ibcon#read 6, iclass 23, count 2 2006.257.04:21:37.45#ibcon#end of sib2, iclass 23, count 2 2006.257.04:21:37.45#ibcon#*after write, iclass 23, count 2 2006.257.04:21:37.45#ibcon#*before return 0, iclass 23, count 2 2006.257.04:21:37.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:37.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:37.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.04:21:37.45#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:37.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:37.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:37.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:37.57#ibcon#enter wrdev, iclass 23, count 0 2006.257.04:21:37.57#ibcon#first serial, iclass 23, count 0 2006.257.04:21:37.57#ibcon#enter sib2, iclass 23, count 0 2006.257.04:21:37.57#ibcon#flushed, iclass 23, count 0 2006.257.04:21:37.57#ibcon#about to write, iclass 23, count 0 2006.257.04:21:37.57#ibcon#wrote, iclass 23, count 0 2006.257.04:21:37.57#ibcon#about to read 3, iclass 23, count 0 2006.257.04:21:37.59#ibcon#read 3, iclass 23, count 0 2006.257.04:21:37.59#ibcon#about to read 4, iclass 23, count 0 2006.257.04:21:37.59#ibcon#read 4, iclass 23, count 0 2006.257.04:21:37.59#ibcon#about to read 5, iclass 23, count 0 2006.257.04:21:37.59#ibcon#read 5, iclass 23, count 0 2006.257.04:21:37.59#ibcon#about to read 6, iclass 23, count 0 2006.257.04:21:37.59#ibcon#read 6, iclass 23, count 0 2006.257.04:21:37.59#ibcon#end of sib2, iclass 23, count 0 2006.257.04:21:37.59#ibcon#*mode == 0, iclass 23, count 0 2006.257.04:21:37.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.04:21:37.59#ibcon#[25=USB\r\n] 2006.257.04:21:37.59#ibcon#*before write, iclass 23, count 0 2006.257.04:21:37.59#ibcon#enter sib2, iclass 23, count 0 2006.257.04:21:37.59#ibcon#flushed, iclass 23, count 0 2006.257.04:21:37.59#ibcon#about to write, iclass 23, count 0 2006.257.04:21:37.59#ibcon#wrote, iclass 23, count 0 2006.257.04:21:37.59#ibcon#about to read 3, iclass 23, count 0 2006.257.04:21:37.62#ibcon#read 3, iclass 23, count 0 2006.257.04:21:37.62#ibcon#about to read 4, iclass 23, count 0 2006.257.04:21:37.62#ibcon#read 4, iclass 23, count 0 2006.257.04:21:37.62#ibcon#about to read 5, iclass 23, count 0 2006.257.04:21:37.62#ibcon#read 5, iclass 23, count 0 2006.257.04:21:37.62#ibcon#about to read 6, iclass 23, count 0 2006.257.04:21:37.62#ibcon#read 6, iclass 23, count 0 2006.257.04:21:37.62#ibcon#end of sib2, iclass 23, count 0 2006.257.04:21:37.62#ibcon#*after write, iclass 23, count 0 2006.257.04:21:37.62#ibcon#*before return 0, iclass 23, count 0 2006.257.04:21:37.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:37.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:37.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.04:21:37.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.04:21:37.62$vck44/valo=2,534.99 2006.257.04:21:37.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.04:21:37.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.04:21:37.62#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:37.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:37.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:37.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:37.62#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:21:37.62#ibcon#first serial, iclass 25, count 0 2006.257.04:21:37.62#ibcon#enter sib2, iclass 25, count 0 2006.257.04:21:37.62#ibcon#flushed, iclass 25, count 0 2006.257.04:21:37.62#ibcon#about to write, iclass 25, count 0 2006.257.04:21:37.62#ibcon#wrote, iclass 25, count 0 2006.257.04:21:37.62#ibcon#about to read 3, iclass 25, count 0 2006.257.04:21:37.64#ibcon#read 3, iclass 25, count 0 2006.257.04:21:37.64#ibcon#about to read 4, iclass 25, count 0 2006.257.04:21:37.64#ibcon#read 4, iclass 25, count 0 2006.257.04:21:37.64#ibcon#about to read 5, iclass 25, count 0 2006.257.04:21:37.64#ibcon#read 5, iclass 25, count 0 2006.257.04:21:37.64#ibcon#about to read 6, iclass 25, count 0 2006.257.04:21:37.64#ibcon#read 6, iclass 25, count 0 2006.257.04:21:37.64#ibcon#end of sib2, iclass 25, count 0 2006.257.04:21:37.64#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:21:37.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:21:37.64#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.04:21:37.64#ibcon#*before write, iclass 25, count 0 2006.257.04:21:37.64#ibcon#enter sib2, iclass 25, count 0 2006.257.04:21:37.64#ibcon#flushed, iclass 25, count 0 2006.257.04:21:37.64#ibcon#about to write, iclass 25, count 0 2006.257.04:21:37.64#ibcon#wrote, iclass 25, count 0 2006.257.04:21:37.64#ibcon#about to read 3, iclass 25, count 0 2006.257.04:21:37.68#ibcon#read 3, iclass 25, count 0 2006.257.04:21:37.68#ibcon#about to read 4, iclass 25, count 0 2006.257.04:21:37.68#ibcon#read 4, iclass 25, count 0 2006.257.04:21:37.68#ibcon#about to read 5, iclass 25, count 0 2006.257.04:21:37.68#ibcon#read 5, iclass 25, count 0 2006.257.04:21:37.68#ibcon#about to read 6, iclass 25, count 0 2006.257.04:21:37.68#ibcon#read 6, iclass 25, count 0 2006.257.04:21:37.68#ibcon#end of sib2, iclass 25, count 0 2006.257.04:21:37.68#ibcon#*after write, iclass 25, count 0 2006.257.04:21:37.68#ibcon#*before return 0, iclass 25, count 0 2006.257.04:21:37.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:37.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:37.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:21:37.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:21:37.68$vck44/va=2,7 2006.257.04:21:37.68#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.04:21:37.68#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.04:21:37.68#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:37.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:37.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:37.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:37.74#ibcon#enter wrdev, iclass 27, count 2 2006.257.04:21:37.74#ibcon#first serial, iclass 27, count 2 2006.257.04:21:37.74#ibcon#enter sib2, iclass 27, count 2 2006.257.04:21:37.74#ibcon#flushed, iclass 27, count 2 2006.257.04:21:37.74#ibcon#about to write, iclass 27, count 2 2006.257.04:21:37.74#ibcon#wrote, iclass 27, count 2 2006.257.04:21:37.74#ibcon#about to read 3, iclass 27, count 2 2006.257.04:21:37.76#ibcon#read 3, iclass 27, count 2 2006.257.04:21:37.76#ibcon#about to read 4, iclass 27, count 2 2006.257.04:21:37.76#ibcon#read 4, iclass 27, count 2 2006.257.04:21:37.76#ibcon#about to read 5, iclass 27, count 2 2006.257.04:21:37.76#ibcon#read 5, iclass 27, count 2 2006.257.04:21:37.76#ibcon#about to read 6, iclass 27, count 2 2006.257.04:21:37.76#ibcon#read 6, iclass 27, count 2 2006.257.04:21:37.76#ibcon#end of sib2, iclass 27, count 2 2006.257.04:21:37.76#ibcon#*mode == 0, iclass 27, count 2 2006.257.04:21:37.76#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.04:21:37.76#ibcon#[25=AT02-07\r\n] 2006.257.04:21:37.76#ibcon#*before write, iclass 27, count 2 2006.257.04:21:37.76#ibcon#enter sib2, iclass 27, count 2 2006.257.04:21:37.76#ibcon#flushed, iclass 27, count 2 2006.257.04:21:37.76#ibcon#about to write, iclass 27, count 2 2006.257.04:21:37.76#ibcon#wrote, iclass 27, count 2 2006.257.04:21:37.76#ibcon#about to read 3, iclass 27, count 2 2006.257.04:21:37.79#ibcon#read 3, iclass 27, count 2 2006.257.04:21:37.79#ibcon#about to read 4, iclass 27, count 2 2006.257.04:21:37.79#ibcon#read 4, iclass 27, count 2 2006.257.04:21:37.79#ibcon#about to read 5, iclass 27, count 2 2006.257.04:21:37.79#ibcon#read 5, iclass 27, count 2 2006.257.04:21:37.79#ibcon#about to read 6, iclass 27, count 2 2006.257.04:21:37.79#ibcon#read 6, iclass 27, count 2 2006.257.04:21:37.79#ibcon#end of sib2, iclass 27, count 2 2006.257.04:21:37.79#ibcon#*after write, iclass 27, count 2 2006.257.04:21:37.79#ibcon#*before return 0, iclass 27, count 2 2006.257.04:21:37.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:37.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:37.79#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.04:21:37.79#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:37.79#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:37.91#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:37.91#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:37.91#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:21:37.91#ibcon#first serial, iclass 27, count 0 2006.257.04:21:37.91#ibcon#enter sib2, iclass 27, count 0 2006.257.04:21:37.91#ibcon#flushed, iclass 27, count 0 2006.257.04:21:37.91#ibcon#about to write, iclass 27, count 0 2006.257.04:21:37.91#ibcon#wrote, iclass 27, count 0 2006.257.04:21:37.91#ibcon#about to read 3, iclass 27, count 0 2006.257.04:21:37.93#ibcon#read 3, iclass 27, count 0 2006.257.04:21:37.93#ibcon#about to read 4, iclass 27, count 0 2006.257.04:21:37.93#ibcon#read 4, iclass 27, count 0 2006.257.04:21:37.93#ibcon#about to read 5, iclass 27, count 0 2006.257.04:21:37.93#ibcon#read 5, iclass 27, count 0 2006.257.04:21:37.93#ibcon#about to read 6, iclass 27, count 0 2006.257.04:21:37.93#ibcon#read 6, iclass 27, count 0 2006.257.04:21:37.93#ibcon#end of sib2, iclass 27, count 0 2006.257.04:21:37.93#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:21:37.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:21:37.93#ibcon#[25=USB\r\n] 2006.257.04:21:37.93#ibcon#*before write, iclass 27, count 0 2006.257.04:21:37.93#ibcon#enter sib2, iclass 27, count 0 2006.257.04:21:37.93#ibcon#flushed, iclass 27, count 0 2006.257.04:21:37.93#ibcon#about to write, iclass 27, count 0 2006.257.04:21:37.93#ibcon#wrote, iclass 27, count 0 2006.257.04:21:37.93#ibcon#about to read 3, iclass 27, count 0 2006.257.04:21:37.96#ibcon#read 3, iclass 27, count 0 2006.257.04:21:37.96#ibcon#about to read 4, iclass 27, count 0 2006.257.04:21:37.96#ibcon#read 4, iclass 27, count 0 2006.257.04:21:37.96#ibcon#about to read 5, iclass 27, count 0 2006.257.04:21:37.96#ibcon#read 5, iclass 27, count 0 2006.257.04:21:37.96#ibcon#about to read 6, iclass 27, count 0 2006.257.04:21:37.96#ibcon#read 6, iclass 27, count 0 2006.257.04:21:37.96#ibcon#end of sib2, iclass 27, count 0 2006.257.04:21:37.96#ibcon#*after write, iclass 27, count 0 2006.257.04:21:37.96#ibcon#*before return 0, iclass 27, count 0 2006.257.04:21:37.96#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:37.96#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:37.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:21:37.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:21:37.96$vck44/valo=3,564.99 2006.257.04:21:37.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.04:21:37.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.04:21:37.96#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:37.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:37.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:37.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:37.96#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:21:37.96#ibcon#first serial, iclass 29, count 0 2006.257.04:21:37.96#ibcon#enter sib2, iclass 29, count 0 2006.257.04:21:37.96#ibcon#flushed, iclass 29, count 0 2006.257.04:21:37.96#ibcon#about to write, iclass 29, count 0 2006.257.04:21:37.96#ibcon#wrote, iclass 29, count 0 2006.257.04:21:37.96#ibcon#about to read 3, iclass 29, count 0 2006.257.04:21:37.98#ibcon#read 3, iclass 29, count 0 2006.257.04:21:37.98#ibcon#about to read 4, iclass 29, count 0 2006.257.04:21:37.98#ibcon#read 4, iclass 29, count 0 2006.257.04:21:37.98#ibcon#about to read 5, iclass 29, count 0 2006.257.04:21:37.98#ibcon#read 5, iclass 29, count 0 2006.257.04:21:37.98#ibcon#about to read 6, iclass 29, count 0 2006.257.04:21:37.98#ibcon#read 6, iclass 29, count 0 2006.257.04:21:37.98#ibcon#end of sib2, iclass 29, count 0 2006.257.04:21:37.98#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:21:37.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:21:37.98#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.04:21:37.98#ibcon#*before write, iclass 29, count 0 2006.257.04:21:37.98#ibcon#enter sib2, iclass 29, count 0 2006.257.04:21:37.98#ibcon#flushed, iclass 29, count 0 2006.257.04:21:37.98#ibcon#about to write, iclass 29, count 0 2006.257.04:21:37.98#ibcon#wrote, iclass 29, count 0 2006.257.04:21:37.98#ibcon#about to read 3, iclass 29, count 0 2006.257.04:21:38.02#ibcon#read 3, iclass 29, count 0 2006.257.04:21:38.02#ibcon#about to read 4, iclass 29, count 0 2006.257.04:21:38.02#ibcon#read 4, iclass 29, count 0 2006.257.04:21:38.02#ibcon#about to read 5, iclass 29, count 0 2006.257.04:21:38.02#ibcon#read 5, iclass 29, count 0 2006.257.04:21:38.02#ibcon#about to read 6, iclass 29, count 0 2006.257.04:21:38.02#ibcon#read 6, iclass 29, count 0 2006.257.04:21:38.02#ibcon#end of sib2, iclass 29, count 0 2006.257.04:21:38.02#ibcon#*after write, iclass 29, count 0 2006.257.04:21:38.02#ibcon#*before return 0, iclass 29, count 0 2006.257.04:21:38.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:38.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:38.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:21:38.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:21:38.02$vck44/va=3,8 2006.257.04:21:38.02#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.04:21:38.02#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.04:21:38.02#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:38.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:38.08#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:38.08#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:38.08#ibcon#enter wrdev, iclass 31, count 2 2006.257.04:21:38.08#ibcon#first serial, iclass 31, count 2 2006.257.04:21:38.08#ibcon#enter sib2, iclass 31, count 2 2006.257.04:21:38.08#ibcon#flushed, iclass 31, count 2 2006.257.04:21:38.08#ibcon#about to write, iclass 31, count 2 2006.257.04:21:38.08#ibcon#wrote, iclass 31, count 2 2006.257.04:21:38.08#ibcon#about to read 3, iclass 31, count 2 2006.257.04:21:38.10#ibcon#read 3, iclass 31, count 2 2006.257.04:21:38.10#ibcon#about to read 4, iclass 31, count 2 2006.257.04:21:38.10#ibcon#read 4, iclass 31, count 2 2006.257.04:21:38.10#ibcon#about to read 5, iclass 31, count 2 2006.257.04:21:38.10#ibcon#read 5, iclass 31, count 2 2006.257.04:21:38.10#ibcon#about to read 6, iclass 31, count 2 2006.257.04:21:38.10#ibcon#read 6, iclass 31, count 2 2006.257.04:21:38.10#ibcon#end of sib2, iclass 31, count 2 2006.257.04:21:38.10#ibcon#*mode == 0, iclass 31, count 2 2006.257.04:21:38.10#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.04:21:38.10#ibcon#[25=AT03-08\r\n] 2006.257.04:21:38.10#ibcon#*before write, iclass 31, count 2 2006.257.04:21:38.10#ibcon#enter sib2, iclass 31, count 2 2006.257.04:21:38.10#ibcon#flushed, iclass 31, count 2 2006.257.04:21:38.10#ibcon#about to write, iclass 31, count 2 2006.257.04:21:38.10#ibcon#wrote, iclass 31, count 2 2006.257.04:21:38.10#ibcon#about to read 3, iclass 31, count 2 2006.257.04:21:38.13#ibcon#read 3, iclass 31, count 2 2006.257.04:21:38.13#ibcon#about to read 4, iclass 31, count 2 2006.257.04:21:38.13#ibcon#read 4, iclass 31, count 2 2006.257.04:21:38.13#ibcon#about to read 5, iclass 31, count 2 2006.257.04:21:38.13#ibcon#read 5, iclass 31, count 2 2006.257.04:21:38.13#ibcon#about to read 6, iclass 31, count 2 2006.257.04:21:38.13#ibcon#read 6, iclass 31, count 2 2006.257.04:21:38.13#ibcon#end of sib2, iclass 31, count 2 2006.257.04:21:38.13#ibcon#*after write, iclass 31, count 2 2006.257.04:21:38.13#ibcon#*before return 0, iclass 31, count 2 2006.257.04:21:38.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:38.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:38.13#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.04:21:38.13#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:38.13#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:38.25#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:38.25#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:38.25#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:21:38.25#ibcon#first serial, iclass 31, count 0 2006.257.04:21:38.25#ibcon#enter sib2, iclass 31, count 0 2006.257.04:21:38.25#ibcon#flushed, iclass 31, count 0 2006.257.04:21:38.25#ibcon#about to write, iclass 31, count 0 2006.257.04:21:38.25#ibcon#wrote, iclass 31, count 0 2006.257.04:21:38.25#ibcon#about to read 3, iclass 31, count 0 2006.257.04:21:38.27#ibcon#read 3, iclass 31, count 0 2006.257.04:21:38.27#ibcon#about to read 4, iclass 31, count 0 2006.257.04:21:38.27#ibcon#read 4, iclass 31, count 0 2006.257.04:21:38.27#ibcon#about to read 5, iclass 31, count 0 2006.257.04:21:38.27#ibcon#read 5, iclass 31, count 0 2006.257.04:21:38.27#ibcon#about to read 6, iclass 31, count 0 2006.257.04:21:38.27#ibcon#read 6, iclass 31, count 0 2006.257.04:21:38.27#ibcon#end of sib2, iclass 31, count 0 2006.257.04:21:38.27#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:21:38.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:21:38.27#ibcon#[25=USB\r\n] 2006.257.04:21:38.27#ibcon#*before write, iclass 31, count 0 2006.257.04:21:38.27#ibcon#enter sib2, iclass 31, count 0 2006.257.04:21:38.27#ibcon#flushed, iclass 31, count 0 2006.257.04:21:38.27#ibcon#about to write, iclass 31, count 0 2006.257.04:21:38.27#ibcon#wrote, iclass 31, count 0 2006.257.04:21:38.27#ibcon#about to read 3, iclass 31, count 0 2006.257.04:21:38.30#ibcon#read 3, iclass 31, count 0 2006.257.04:21:38.30#ibcon#about to read 4, iclass 31, count 0 2006.257.04:21:38.30#ibcon#read 4, iclass 31, count 0 2006.257.04:21:38.30#ibcon#about to read 5, iclass 31, count 0 2006.257.04:21:38.30#ibcon#read 5, iclass 31, count 0 2006.257.04:21:38.30#ibcon#about to read 6, iclass 31, count 0 2006.257.04:21:38.30#ibcon#read 6, iclass 31, count 0 2006.257.04:21:38.30#ibcon#end of sib2, iclass 31, count 0 2006.257.04:21:38.30#ibcon#*after write, iclass 31, count 0 2006.257.04:21:38.30#ibcon#*before return 0, iclass 31, count 0 2006.257.04:21:38.30#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:38.30#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:38.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:21:38.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:21:38.30$vck44/valo=4,624.99 2006.257.04:21:38.30#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.04:21:38.30#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.04:21:38.30#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:38.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:38.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:38.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:38.30#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:21:38.30#ibcon#first serial, iclass 33, count 0 2006.257.04:21:38.30#ibcon#enter sib2, iclass 33, count 0 2006.257.04:21:38.30#ibcon#flushed, iclass 33, count 0 2006.257.04:21:38.30#ibcon#about to write, iclass 33, count 0 2006.257.04:21:38.30#ibcon#wrote, iclass 33, count 0 2006.257.04:21:38.30#ibcon#about to read 3, iclass 33, count 0 2006.257.04:21:38.32#ibcon#read 3, iclass 33, count 0 2006.257.04:21:38.32#ibcon#about to read 4, iclass 33, count 0 2006.257.04:21:38.32#ibcon#read 4, iclass 33, count 0 2006.257.04:21:38.32#ibcon#about to read 5, iclass 33, count 0 2006.257.04:21:38.32#ibcon#read 5, iclass 33, count 0 2006.257.04:21:38.32#ibcon#about to read 6, iclass 33, count 0 2006.257.04:21:38.32#ibcon#read 6, iclass 33, count 0 2006.257.04:21:38.32#ibcon#end of sib2, iclass 33, count 0 2006.257.04:21:38.32#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:21:38.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:21:38.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.04:21:38.32#ibcon#*before write, iclass 33, count 0 2006.257.04:21:38.32#ibcon#enter sib2, iclass 33, count 0 2006.257.04:21:38.32#ibcon#flushed, iclass 33, count 0 2006.257.04:21:38.32#ibcon#about to write, iclass 33, count 0 2006.257.04:21:38.32#ibcon#wrote, iclass 33, count 0 2006.257.04:21:38.32#ibcon#about to read 3, iclass 33, count 0 2006.257.04:21:38.36#ibcon#read 3, iclass 33, count 0 2006.257.04:21:38.36#ibcon#about to read 4, iclass 33, count 0 2006.257.04:21:38.36#ibcon#read 4, iclass 33, count 0 2006.257.04:21:38.36#ibcon#about to read 5, iclass 33, count 0 2006.257.04:21:38.36#ibcon#read 5, iclass 33, count 0 2006.257.04:21:38.36#ibcon#about to read 6, iclass 33, count 0 2006.257.04:21:38.36#ibcon#read 6, iclass 33, count 0 2006.257.04:21:38.36#ibcon#end of sib2, iclass 33, count 0 2006.257.04:21:38.36#ibcon#*after write, iclass 33, count 0 2006.257.04:21:38.36#ibcon#*before return 0, iclass 33, count 0 2006.257.04:21:38.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:38.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:38.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:21:38.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:21:38.36$vck44/va=4,7 2006.257.04:21:38.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.04:21:38.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.04:21:38.36#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:38.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:38.42#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:38.42#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:38.42#ibcon#enter wrdev, iclass 35, count 2 2006.257.04:21:38.42#ibcon#first serial, iclass 35, count 2 2006.257.04:21:38.42#ibcon#enter sib2, iclass 35, count 2 2006.257.04:21:38.42#ibcon#flushed, iclass 35, count 2 2006.257.04:21:38.42#ibcon#about to write, iclass 35, count 2 2006.257.04:21:38.42#ibcon#wrote, iclass 35, count 2 2006.257.04:21:38.42#ibcon#about to read 3, iclass 35, count 2 2006.257.04:21:38.44#ibcon#read 3, iclass 35, count 2 2006.257.04:21:38.44#ibcon#about to read 4, iclass 35, count 2 2006.257.04:21:38.44#ibcon#read 4, iclass 35, count 2 2006.257.04:21:38.44#ibcon#about to read 5, iclass 35, count 2 2006.257.04:21:38.44#ibcon#read 5, iclass 35, count 2 2006.257.04:21:38.44#ibcon#about to read 6, iclass 35, count 2 2006.257.04:21:38.44#ibcon#read 6, iclass 35, count 2 2006.257.04:21:38.44#ibcon#end of sib2, iclass 35, count 2 2006.257.04:21:38.44#ibcon#*mode == 0, iclass 35, count 2 2006.257.04:21:38.44#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.04:21:38.44#ibcon#[25=AT04-07\r\n] 2006.257.04:21:38.44#ibcon#*before write, iclass 35, count 2 2006.257.04:21:38.44#ibcon#enter sib2, iclass 35, count 2 2006.257.04:21:38.44#ibcon#flushed, iclass 35, count 2 2006.257.04:21:38.44#ibcon#about to write, iclass 35, count 2 2006.257.04:21:38.44#ibcon#wrote, iclass 35, count 2 2006.257.04:21:38.44#ibcon#about to read 3, iclass 35, count 2 2006.257.04:21:38.47#ibcon#read 3, iclass 35, count 2 2006.257.04:21:38.47#ibcon#about to read 4, iclass 35, count 2 2006.257.04:21:38.47#ibcon#read 4, iclass 35, count 2 2006.257.04:21:38.47#ibcon#about to read 5, iclass 35, count 2 2006.257.04:21:38.47#ibcon#read 5, iclass 35, count 2 2006.257.04:21:38.47#ibcon#about to read 6, iclass 35, count 2 2006.257.04:21:38.47#ibcon#read 6, iclass 35, count 2 2006.257.04:21:38.47#ibcon#end of sib2, iclass 35, count 2 2006.257.04:21:38.47#ibcon#*after write, iclass 35, count 2 2006.257.04:21:38.47#ibcon#*before return 0, iclass 35, count 2 2006.257.04:21:38.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:38.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:38.47#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.04:21:38.47#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:38.47#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:38.59#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:38.59#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:38.59#ibcon#enter wrdev, iclass 35, count 0 2006.257.04:21:38.59#ibcon#first serial, iclass 35, count 0 2006.257.04:21:38.59#ibcon#enter sib2, iclass 35, count 0 2006.257.04:21:38.59#ibcon#flushed, iclass 35, count 0 2006.257.04:21:38.59#ibcon#about to write, iclass 35, count 0 2006.257.04:21:38.59#ibcon#wrote, iclass 35, count 0 2006.257.04:21:38.59#ibcon#about to read 3, iclass 35, count 0 2006.257.04:21:38.61#ibcon#read 3, iclass 35, count 0 2006.257.04:21:38.61#ibcon#about to read 4, iclass 35, count 0 2006.257.04:21:38.61#ibcon#read 4, iclass 35, count 0 2006.257.04:21:38.61#ibcon#about to read 5, iclass 35, count 0 2006.257.04:21:38.61#ibcon#read 5, iclass 35, count 0 2006.257.04:21:38.61#ibcon#about to read 6, iclass 35, count 0 2006.257.04:21:38.61#ibcon#read 6, iclass 35, count 0 2006.257.04:21:38.61#ibcon#end of sib2, iclass 35, count 0 2006.257.04:21:38.61#ibcon#*mode == 0, iclass 35, count 0 2006.257.04:21:38.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.04:21:38.61#ibcon#[25=USB\r\n] 2006.257.04:21:38.61#ibcon#*before write, iclass 35, count 0 2006.257.04:21:38.61#ibcon#enter sib2, iclass 35, count 0 2006.257.04:21:38.61#ibcon#flushed, iclass 35, count 0 2006.257.04:21:38.61#ibcon#about to write, iclass 35, count 0 2006.257.04:21:38.61#ibcon#wrote, iclass 35, count 0 2006.257.04:21:38.61#ibcon#about to read 3, iclass 35, count 0 2006.257.04:21:38.64#ibcon#read 3, iclass 35, count 0 2006.257.04:21:38.64#ibcon#about to read 4, iclass 35, count 0 2006.257.04:21:38.64#ibcon#read 4, iclass 35, count 0 2006.257.04:21:38.64#ibcon#about to read 5, iclass 35, count 0 2006.257.04:21:38.64#ibcon#read 5, iclass 35, count 0 2006.257.04:21:38.64#ibcon#about to read 6, iclass 35, count 0 2006.257.04:21:38.64#ibcon#read 6, iclass 35, count 0 2006.257.04:21:38.64#ibcon#end of sib2, iclass 35, count 0 2006.257.04:21:38.64#ibcon#*after write, iclass 35, count 0 2006.257.04:21:38.64#ibcon#*before return 0, iclass 35, count 0 2006.257.04:21:38.64#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:38.64#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:38.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.04:21:38.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.04:21:38.64$vck44/valo=5,734.99 2006.257.04:21:38.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.04:21:38.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.04:21:38.64#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:38.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:38.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:38.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:38.64#ibcon#enter wrdev, iclass 37, count 0 2006.257.04:21:38.64#ibcon#first serial, iclass 37, count 0 2006.257.04:21:38.64#ibcon#enter sib2, iclass 37, count 0 2006.257.04:21:38.64#ibcon#flushed, iclass 37, count 0 2006.257.04:21:38.64#ibcon#about to write, iclass 37, count 0 2006.257.04:21:38.64#ibcon#wrote, iclass 37, count 0 2006.257.04:21:38.64#ibcon#about to read 3, iclass 37, count 0 2006.257.04:21:38.66#ibcon#read 3, iclass 37, count 0 2006.257.04:21:38.66#ibcon#about to read 4, iclass 37, count 0 2006.257.04:21:38.66#ibcon#read 4, iclass 37, count 0 2006.257.04:21:38.66#ibcon#about to read 5, iclass 37, count 0 2006.257.04:21:38.66#ibcon#read 5, iclass 37, count 0 2006.257.04:21:38.66#ibcon#about to read 6, iclass 37, count 0 2006.257.04:21:38.66#ibcon#read 6, iclass 37, count 0 2006.257.04:21:38.66#ibcon#end of sib2, iclass 37, count 0 2006.257.04:21:38.66#ibcon#*mode == 0, iclass 37, count 0 2006.257.04:21:38.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.04:21:38.66#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.04:21:38.66#ibcon#*before write, iclass 37, count 0 2006.257.04:21:38.66#ibcon#enter sib2, iclass 37, count 0 2006.257.04:21:38.66#ibcon#flushed, iclass 37, count 0 2006.257.04:21:38.66#ibcon#about to write, iclass 37, count 0 2006.257.04:21:38.66#ibcon#wrote, iclass 37, count 0 2006.257.04:21:38.66#ibcon#about to read 3, iclass 37, count 0 2006.257.04:21:38.70#ibcon#read 3, iclass 37, count 0 2006.257.04:21:38.70#ibcon#about to read 4, iclass 37, count 0 2006.257.04:21:38.70#ibcon#read 4, iclass 37, count 0 2006.257.04:21:38.70#ibcon#about to read 5, iclass 37, count 0 2006.257.04:21:38.70#ibcon#read 5, iclass 37, count 0 2006.257.04:21:38.70#ibcon#about to read 6, iclass 37, count 0 2006.257.04:21:38.70#ibcon#read 6, iclass 37, count 0 2006.257.04:21:38.70#ibcon#end of sib2, iclass 37, count 0 2006.257.04:21:38.70#ibcon#*after write, iclass 37, count 0 2006.257.04:21:38.70#ibcon#*before return 0, iclass 37, count 0 2006.257.04:21:38.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:38.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:38.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.04:21:38.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.04:21:38.70$vck44/va=5,4 2006.257.04:21:38.70#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.04:21:38.70#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.04:21:38.70#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:38.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:38.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:38.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:38.76#ibcon#enter wrdev, iclass 39, count 2 2006.257.04:21:38.76#ibcon#first serial, iclass 39, count 2 2006.257.04:21:38.76#ibcon#enter sib2, iclass 39, count 2 2006.257.04:21:38.76#ibcon#flushed, iclass 39, count 2 2006.257.04:21:38.76#ibcon#about to write, iclass 39, count 2 2006.257.04:21:38.76#ibcon#wrote, iclass 39, count 2 2006.257.04:21:38.76#ibcon#about to read 3, iclass 39, count 2 2006.257.04:21:38.78#ibcon#read 3, iclass 39, count 2 2006.257.04:21:38.78#ibcon#about to read 4, iclass 39, count 2 2006.257.04:21:38.78#ibcon#read 4, iclass 39, count 2 2006.257.04:21:38.78#ibcon#about to read 5, iclass 39, count 2 2006.257.04:21:38.78#ibcon#read 5, iclass 39, count 2 2006.257.04:21:38.78#ibcon#about to read 6, iclass 39, count 2 2006.257.04:21:38.78#ibcon#read 6, iclass 39, count 2 2006.257.04:21:38.78#ibcon#end of sib2, iclass 39, count 2 2006.257.04:21:38.78#ibcon#*mode == 0, iclass 39, count 2 2006.257.04:21:38.78#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.04:21:38.78#ibcon#[25=AT05-04\r\n] 2006.257.04:21:38.78#ibcon#*before write, iclass 39, count 2 2006.257.04:21:38.78#ibcon#enter sib2, iclass 39, count 2 2006.257.04:21:38.78#ibcon#flushed, iclass 39, count 2 2006.257.04:21:38.78#ibcon#about to write, iclass 39, count 2 2006.257.04:21:38.78#ibcon#wrote, iclass 39, count 2 2006.257.04:21:38.78#ibcon#about to read 3, iclass 39, count 2 2006.257.04:21:38.81#ibcon#read 3, iclass 39, count 2 2006.257.04:21:38.81#ibcon#about to read 4, iclass 39, count 2 2006.257.04:21:38.81#ibcon#read 4, iclass 39, count 2 2006.257.04:21:38.81#ibcon#about to read 5, iclass 39, count 2 2006.257.04:21:38.81#ibcon#read 5, iclass 39, count 2 2006.257.04:21:38.81#ibcon#about to read 6, iclass 39, count 2 2006.257.04:21:38.81#ibcon#read 6, iclass 39, count 2 2006.257.04:21:38.81#ibcon#end of sib2, iclass 39, count 2 2006.257.04:21:38.81#ibcon#*after write, iclass 39, count 2 2006.257.04:21:38.81#ibcon#*before return 0, iclass 39, count 2 2006.257.04:21:38.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:38.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:38.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.04:21:38.81#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:38.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:38.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:38.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:38.93#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:21:38.93#ibcon#first serial, iclass 39, count 0 2006.257.04:21:38.93#ibcon#enter sib2, iclass 39, count 0 2006.257.04:21:38.93#ibcon#flushed, iclass 39, count 0 2006.257.04:21:38.93#ibcon#about to write, iclass 39, count 0 2006.257.04:21:38.93#ibcon#wrote, iclass 39, count 0 2006.257.04:21:38.93#ibcon#about to read 3, iclass 39, count 0 2006.257.04:21:38.95#ibcon#read 3, iclass 39, count 0 2006.257.04:21:38.95#ibcon#about to read 4, iclass 39, count 0 2006.257.04:21:38.95#ibcon#read 4, iclass 39, count 0 2006.257.04:21:38.95#ibcon#about to read 5, iclass 39, count 0 2006.257.04:21:38.95#ibcon#read 5, iclass 39, count 0 2006.257.04:21:38.95#ibcon#about to read 6, iclass 39, count 0 2006.257.04:21:38.95#ibcon#read 6, iclass 39, count 0 2006.257.04:21:38.95#ibcon#end of sib2, iclass 39, count 0 2006.257.04:21:38.95#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:21:38.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:21:38.95#ibcon#[25=USB\r\n] 2006.257.04:21:38.95#ibcon#*before write, iclass 39, count 0 2006.257.04:21:38.95#ibcon#enter sib2, iclass 39, count 0 2006.257.04:21:38.95#ibcon#flushed, iclass 39, count 0 2006.257.04:21:38.95#ibcon#about to write, iclass 39, count 0 2006.257.04:21:38.95#ibcon#wrote, iclass 39, count 0 2006.257.04:21:38.95#ibcon#about to read 3, iclass 39, count 0 2006.257.04:21:38.98#ibcon#read 3, iclass 39, count 0 2006.257.04:21:38.98#ibcon#about to read 4, iclass 39, count 0 2006.257.04:21:38.98#ibcon#read 4, iclass 39, count 0 2006.257.04:21:38.98#ibcon#about to read 5, iclass 39, count 0 2006.257.04:21:38.98#ibcon#read 5, iclass 39, count 0 2006.257.04:21:38.98#ibcon#about to read 6, iclass 39, count 0 2006.257.04:21:38.98#ibcon#read 6, iclass 39, count 0 2006.257.04:21:38.98#ibcon#end of sib2, iclass 39, count 0 2006.257.04:21:38.98#ibcon#*after write, iclass 39, count 0 2006.257.04:21:38.98#ibcon#*before return 0, iclass 39, count 0 2006.257.04:21:38.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:38.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:38.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:21:38.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:21:38.98$vck44/valo=6,814.99 2006.257.04:21:38.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.04:21:38.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.04:21:38.98#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:38.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:38.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:38.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:38.98#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:21:38.98#ibcon#first serial, iclass 3, count 0 2006.257.04:21:38.98#ibcon#enter sib2, iclass 3, count 0 2006.257.04:21:38.98#ibcon#flushed, iclass 3, count 0 2006.257.04:21:38.98#ibcon#about to write, iclass 3, count 0 2006.257.04:21:38.98#ibcon#wrote, iclass 3, count 0 2006.257.04:21:38.98#ibcon#about to read 3, iclass 3, count 0 2006.257.04:21:39.00#ibcon#read 3, iclass 3, count 0 2006.257.04:21:39.00#ibcon#about to read 4, iclass 3, count 0 2006.257.04:21:39.00#ibcon#read 4, iclass 3, count 0 2006.257.04:21:39.00#ibcon#about to read 5, iclass 3, count 0 2006.257.04:21:39.00#ibcon#read 5, iclass 3, count 0 2006.257.04:21:39.00#ibcon#about to read 6, iclass 3, count 0 2006.257.04:21:39.00#ibcon#read 6, iclass 3, count 0 2006.257.04:21:39.00#ibcon#end of sib2, iclass 3, count 0 2006.257.04:21:39.00#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:21:39.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:21:39.00#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.04:21:39.00#ibcon#*before write, iclass 3, count 0 2006.257.04:21:39.00#ibcon#enter sib2, iclass 3, count 0 2006.257.04:21:39.00#ibcon#flushed, iclass 3, count 0 2006.257.04:21:39.00#ibcon#about to write, iclass 3, count 0 2006.257.04:21:39.00#ibcon#wrote, iclass 3, count 0 2006.257.04:21:39.00#ibcon#about to read 3, iclass 3, count 0 2006.257.04:21:39.04#ibcon#read 3, iclass 3, count 0 2006.257.04:21:39.04#ibcon#about to read 4, iclass 3, count 0 2006.257.04:21:39.04#ibcon#read 4, iclass 3, count 0 2006.257.04:21:39.04#ibcon#about to read 5, iclass 3, count 0 2006.257.04:21:39.04#ibcon#read 5, iclass 3, count 0 2006.257.04:21:39.04#ibcon#about to read 6, iclass 3, count 0 2006.257.04:21:39.04#ibcon#read 6, iclass 3, count 0 2006.257.04:21:39.04#ibcon#end of sib2, iclass 3, count 0 2006.257.04:21:39.04#ibcon#*after write, iclass 3, count 0 2006.257.04:21:39.04#ibcon#*before return 0, iclass 3, count 0 2006.257.04:21:39.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:39.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:39.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:21:39.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:21:39.04$vck44/va=6,4 2006.257.04:21:39.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.04:21:39.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.04:21:39.04#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:39.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:39.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:39.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:39.10#ibcon#enter wrdev, iclass 5, count 2 2006.257.04:21:39.10#ibcon#first serial, iclass 5, count 2 2006.257.04:21:39.10#ibcon#enter sib2, iclass 5, count 2 2006.257.04:21:39.10#ibcon#flushed, iclass 5, count 2 2006.257.04:21:39.10#ibcon#about to write, iclass 5, count 2 2006.257.04:21:39.10#ibcon#wrote, iclass 5, count 2 2006.257.04:21:39.10#ibcon#about to read 3, iclass 5, count 2 2006.257.04:21:39.12#ibcon#read 3, iclass 5, count 2 2006.257.04:21:39.12#ibcon#about to read 4, iclass 5, count 2 2006.257.04:21:39.12#ibcon#read 4, iclass 5, count 2 2006.257.04:21:39.12#ibcon#about to read 5, iclass 5, count 2 2006.257.04:21:39.12#ibcon#read 5, iclass 5, count 2 2006.257.04:21:39.12#ibcon#about to read 6, iclass 5, count 2 2006.257.04:21:39.12#ibcon#read 6, iclass 5, count 2 2006.257.04:21:39.12#ibcon#end of sib2, iclass 5, count 2 2006.257.04:21:39.12#ibcon#*mode == 0, iclass 5, count 2 2006.257.04:21:39.12#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.04:21:39.12#ibcon#[25=AT06-04\r\n] 2006.257.04:21:39.12#ibcon#*before write, iclass 5, count 2 2006.257.04:21:39.12#ibcon#enter sib2, iclass 5, count 2 2006.257.04:21:39.12#ibcon#flushed, iclass 5, count 2 2006.257.04:21:39.12#ibcon#about to write, iclass 5, count 2 2006.257.04:21:39.12#ibcon#wrote, iclass 5, count 2 2006.257.04:21:39.12#ibcon#about to read 3, iclass 5, count 2 2006.257.04:21:39.15#ibcon#read 3, iclass 5, count 2 2006.257.04:21:39.15#ibcon#about to read 4, iclass 5, count 2 2006.257.04:21:39.15#ibcon#read 4, iclass 5, count 2 2006.257.04:21:39.15#ibcon#about to read 5, iclass 5, count 2 2006.257.04:21:39.15#ibcon#read 5, iclass 5, count 2 2006.257.04:21:39.15#ibcon#about to read 6, iclass 5, count 2 2006.257.04:21:39.15#ibcon#read 6, iclass 5, count 2 2006.257.04:21:39.15#ibcon#end of sib2, iclass 5, count 2 2006.257.04:21:39.15#ibcon#*after write, iclass 5, count 2 2006.257.04:21:39.15#ibcon#*before return 0, iclass 5, count 2 2006.257.04:21:39.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:39.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:39.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.04:21:39.15#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:39.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:39.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:39.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:39.27#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:21:39.27#ibcon#first serial, iclass 5, count 0 2006.257.04:21:39.27#ibcon#enter sib2, iclass 5, count 0 2006.257.04:21:39.27#ibcon#flushed, iclass 5, count 0 2006.257.04:21:39.27#ibcon#about to write, iclass 5, count 0 2006.257.04:21:39.27#ibcon#wrote, iclass 5, count 0 2006.257.04:21:39.27#ibcon#about to read 3, iclass 5, count 0 2006.257.04:21:39.29#ibcon#read 3, iclass 5, count 0 2006.257.04:21:39.29#ibcon#about to read 4, iclass 5, count 0 2006.257.04:21:39.29#ibcon#read 4, iclass 5, count 0 2006.257.04:21:39.29#ibcon#about to read 5, iclass 5, count 0 2006.257.04:21:39.29#ibcon#read 5, iclass 5, count 0 2006.257.04:21:39.29#ibcon#about to read 6, iclass 5, count 0 2006.257.04:21:39.29#ibcon#read 6, iclass 5, count 0 2006.257.04:21:39.29#ibcon#end of sib2, iclass 5, count 0 2006.257.04:21:39.29#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:21:39.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:21:39.29#ibcon#[25=USB\r\n] 2006.257.04:21:39.29#ibcon#*before write, iclass 5, count 0 2006.257.04:21:39.29#ibcon#enter sib2, iclass 5, count 0 2006.257.04:21:39.29#ibcon#flushed, iclass 5, count 0 2006.257.04:21:39.29#ibcon#about to write, iclass 5, count 0 2006.257.04:21:39.29#ibcon#wrote, iclass 5, count 0 2006.257.04:21:39.29#ibcon#about to read 3, iclass 5, count 0 2006.257.04:21:39.32#ibcon#read 3, iclass 5, count 0 2006.257.04:21:39.32#ibcon#about to read 4, iclass 5, count 0 2006.257.04:21:39.32#ibcon#read 4, iclass 5, count 0 2006.257.04:21:39.32#ibcon#about to read 5, iclass 5, count 0 2006.257.04:21:39.32#ibcon#read 5, iclass 5, count 0 2006.257.04:21:39.32#ibcon#about to read 6, iclass 5, count 0 2006.257.04:21:39.32#ibcon#read 6, iclass 5, count 0 2006.257.04:21:39.32#ibcon#end of sib2, iclass 5, count 0 2006.257.04:21:39.32#ibcon#*after write, iclass 5, count 0 2006.257.04:21:39.32#ibcon#*before return 0, iclass 5, count 0 2006.257.04:21:39.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:39.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:39.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:21:39.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:21:39.32$vck44/valo=7,864.99 2006.257.04:21:39.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.04:21:39.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.04:21:39.32#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:39.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:39.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:39.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:39.32#ibcon#enter wrdev, iclass 7, count 0 2006.257.04:21:39.32#ibcon#first serial, iclass 7, count 0 2006.257.04:21:39.32#ibcon#enter sib2, iclass 7, count 0 2006.257.04:21:39.32#ibcon#flushed, iclass 7, count 0 2006.257.04:21:39.32#ibcon#about to write, iclass 7, count 0 2006.257.04:21:39.32#ibcon#wrote, iclass 7, count 0 2006.257.04:21:39.32#ibcon#about to read 3, iclass 7, count 0 2006.257.04:21:39.34#ibcon#read 3, iclass 7, count 0 2006.257.04:21:39.34#ibcon#about to read 4, iclass 7, count 0 2006.257.04:21:39.34#ibcon#read 4, iclass 7, count 0 2006.257.04:21:39.34#ibcon#about to read 5, iclass 7, count 0 2006.257.04:21:39.34#ibcon#read 5, iclass 7, count 0 2006.257.04:21:39.34#ibcon#about to read 6, iclass 7, count 0 2006.257.04:21:39.34#ibcon#read 6, iclass 7, count 0 2006.257.04:21:39.34#ibcon#end of sib2, iclass 7, count 0 2006.257.04:21:39.34#ibcon#*mode == 0, iclass 7, count 0 2006.257.04:21:39.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.04:21:39.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.04:21:39.34#ibcon#*before write, iclass 7, count 0 2006.257.04:21:39.34#ibcon#enter sib2, iclass 7, count 0 2006.257.04:21:39.34#ibcon#flushed, iclass 7, count 0 2006.257.04:21:39.34#ibcon#about to write, iclass 7, count 0 2006.257.04:21:39.34#ibcon#wrote, iclass 7, count 0 2006.257.04:21:39.34#ibcon#about to read 3, iclass 7, count 0 2006.257.04:21:39.38#ibcon#read 3, iclass 7, count 0 2006.257.04:21:39.38#ibcon#about to read 4, iclass 7, count 0 2006.257.04:21:39.38#ibcon#read 4, iclass 7, count 0 2006.257.04:21:39.38#ibcon#about to read 5, iclass 7, count 0 2006.257.04:21:39.38#ibcon#read 5, iclass 7, count 0 2006.257.04:21:39.38#ibcon#about to read 6, iclass 7, count 0 2006.257.04:21:39.38#ibcon#read 6, iclass 7, count 0 2006.257.04:21:39.38#ibcon#end of sib2, iclass 7, count 0 2006.257.04:21:39.38#ibcon#*after write, iclass 7, count 0 2006.257.04:21:39.38#ibcon#*before return 0, iclass 7, count 0 2006.257.04:21:39.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:39.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:39.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.04:21:39.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.04:21:39.38$vck44/va=7,4 2006.257.04:21:39.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.04:21:39.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.04:21:39.38#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:39.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:39.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:39.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:39.44#ibcon#enter wrdev, iclass 11, count 2 2006.257.04:21:39.44#ibcon#first serial, iclass 11, count 2 2006.257.04:21:39.44#ibcon#enter sib2, iclass 11, count 2 2006.257.04:21:39.44#ibcon#flushed, iclass 11, count 2 2006.257.04:21:39.44#ibcon#about to write, iclass 11, count 2 2006.257.04:21:39.44#ibcon#wrote, iclass 11, count 2 2006.257.04:21:39.44#ibcon#about to read 3, iclass 11, count 2 2006.257.04:21:39.46#ibcon#read 3, iclass 11, count 2 2006.257.04:21:39.46#ibcon#about to read 4, iclass 11, count 2 2006.257.04:21:39.46#ibcon#read 4, iclass 11, count 2 2006.257.04:21:39.46#ibcon#about to read 5, iclass 11, count 2 2006.257.04:21:39.46#ibcon#read 5, iclass 11, count 2 2006.257.04:21:39.46#ibcon#about to read 6, iclass 11, count 2 2006.257.04:21:39.46#ibcon#read 6, iclass 11, count 2 2006.257.04:21:39.46#ibcon#end of sib2, iclass 11, count 2 2006.257.04:21:39.46#ibcon#*mode == 0, iclass 11, count 2 2006.257.04:21:39.46#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.04:21:39.46#ibcon#[25=AT07-04\r\n] 2006.257.04:21:39.46#ibcon#*before write, iclass 11, count 2 2006.257.04:21:39.46#ibcon#enter sib2, iclass 11, count 2 2006.257.04:21:39.46#ibcon#flushed, iclass 11, count 2 2006.257.04:21:39.46#ibcon#about to write, iclass 11, count 2 2006.257.04:21:39.46#ibcon#wrote, iclass 11, count 2 2006.257.04:21:39.46#ibcon#about to read 3, iclass 11, count 2 2006.257.04:21:39.49#ibcon#read 3, iclass 11, count 2 2006.257.04:21:39.49#ibcon#about to read 4, iclass 11, count 2 2006.257.04:21:39.49#ibcon#read 4, iclass 11, count 2 2006.257.04:21:39.49#ibcon#about to read 5, iclass 11, count 2 2006.257.04:21:39.49#ibcon#read 5, iclass 11, count 2 2006.257.04:21:39.49#ibcon#about to read 6, iclass 11, count 2 2006.257.04:21:39.49#ibcon#read 6, iclass 11, count 2 2006.257.04:21:39.49#ibcon#end of sib2, iclass 11, count 2 2006.257.04:21:39.49#ibcon#*after write, iclass 11, count 2 2006.257.04:21:39.49#ibcon#*before return 0, iclass 11, count 2 2006.257.04:21:39.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:39.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:39.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.04:21:39.49#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:39.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:39.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:39.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:39.61#ibcon#enter wrdev, iclass 11, count 0 2006.257.04:21:39.61#ibcon#first serial, iclass 11, count 0 2006.257.04:21:39.61#ibcon#enter sib2, iclass 11, count 0 2006.257.04:21:39.61#ibcon#flushed, iclass 11, count 0 2006.257.04:21:39.61#ibcon#about to write, iclass 11, count 0 2006.257.04:21:39.61#ibcon#wrote, iclass 11, count 0 2006.257.04:21:39.61#ibcon#about to read 3, iclass 11, count 0 2006.257.04:21:39.63#ibcon#read 3, iclass 11, count 0 2006.257.04:21:39.63#ibcon#about to read 4, iclass 11, count 0 2006.257.04:21:39.63#ibcon#read 4, iclass 11, count 0 2006.257.04:21:39.63#ibcon#about to read 5, iclass 11, count 0 2006.257.04:21:39.63#ibcon#read 5, iclass 11, count 0 2006.257.04:21:39.63#ibcon#about to read 6, iclass 11, count 0 2006.257.04:21:39.63#ibcon#read 6, iclass 11, count 0 2006.257.04:21:39.63#ibcon#end of sib2, iclass 11, count 0 2006.257.04:21:39.63#ibcon#*mode == 0, iclass 11, count 0 2006.257.04:21:39.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.04:21:39.63#ibcon#[25=USB\r\n] 2006.257.04:21:39.63#ibcon#*before write, iclass 11, count 0 2006.257.04:21:39.63#ibcon#enter sib2, iclass 11, count 0 2006.257.04:21:39.63#ibcon#flushed, iclass 11, count 0 2006.257.04:21:39.63#ibcon#about to write, iclass 11, count 0 2006.257.04:21:39.63#ibcon#wrote, iclass 11, count 0 2006.257.04:21:39.63#ibcon#about to read 3, iclass 11, count 0 2006.257.04:21:39.66#ibcon#read 3, iclass 11, count 0 2006.257.04:21:39.66#ibcon#about to read 4, iclass 11, count 0 2006.257.04:21:39.66#ibcon#read 4, iclass 11, count 0 2006.257.04:21:39.66#ibcon#about to read 5, iclass 11, count 0 2006.257.04:21:39.66#ibcon#read 5, iclass 11, count 0 2006.257.04:21:39.66#ibcon#about to read 6, iclass 11, count 0 2006.257.04:21:39.66#ibcon#read 6, iclass 11, count 0 2006.257.04:21:39.66#ibcon#end of sib2, iclass 11, count 0 2006.257.04:21:39.66#ibcon#*after write, iclass 11, count 0 2006.257.04:21:39.66#ibcon#*before return 0, iclass 11, count 0 2006.257.04:21:39.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:39.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:39.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.04:21:39.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.04:21:39.66$vck44/valo=8,884.99 2006.257.04:21:39.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.04:21:39.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.04:21:39.66#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:39.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:39.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:39.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:39.66#ibcon#enter wrdev, iclass 13, count 0 2006.257.04:21:39.66#ibcon#first serial, iclass 13, count 0 2006.257.04:21:39.66#ibcon#enter sib2, iclass 13, count 0 2006.257.04:21:39.66#ibcon#flushed, iclass 13, count 0 2006.257.04:21:39.66#ibcon#about to write, iclass 13, count 0 2006.257.04:21:39.66#ibcon#wrote, iclass 13, count 0 2006.257.04:21:39.66#ibcon#about to read 3, iclass 13, count 0 2006.257.04:21:39.68#ibcon#read 3, iclass 13, count 0 2006.257.04:21:39.68#ibcon#about to read 4, iclass 13, count 0 2006.257.04:21:39.68#ibcon#read 4, iclass 13, count 0 2006.257.04:21:39.68#ibcon#about to read 5, iclass 13, count 0 2006.257.04:21:39.68#ibcon#read 5, iclass 13, count 0 2006.257.04:21:39.68#ibcon#about to read 6, iclass 13, count 0 2006.257.04:21:39.68#ibcon#read 6, iclass 13, count 0 2006.257.04:21:39.68#ibcon#end of sib2, iclass 13, count 0 2006.257.04:21:39.68#ibcon#*mode == 0, iclass 13, count 0 2006.257.04:21:39.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.04:21:39.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.04:21:39.68#ibcon#*before write, iclass 13, count 0 2006.257.04:21:39.68#ibcon#enter sib2, iclass 13, count 0 2006.257.04:21:39.68#ibcon#flushed, iclass 13, count 0 2006.257.04:21:39.68#ibcon#about to write, iclass 13, count 0 2006.257.04:21:39.68#ibcon#wrote, iclass 13, count 0 2006.257.04:21:39.68#ibcon#about to read 3, iclass 13, count 0 2006.257.04:21:39.72#ibcon#read 3, iclass 13, count 0 2006.257.04:21:39.72#ibcon#about to read 4, iclass 13, count 0 2006.257.04:21:39.72#ibcon#read 4, iclass 13, count 0 2006.257.04:21:39.72#ibcon#about to read 5, iclass 13, count 0 2006.257.04:21:39.72#ibcon#read 5, iclass 13, count 0 2006.257.04:21:39.72#ibcon#about to read 6, iclass 13, count 0 2006.257.04:21:39.72#ibcon#read 6, iclass 13, count 0 2006.257.04:21:39.72#ibcon#end of sib2, iclass 13, count 0 2006.257.04:21:39.72#ibcon#*after write, iclass 13, count 0 2006.257.04:21:39.72#ibcon#*before return 0, iclass 13, count 0 2006.257.04:21:39.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:39.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:39.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.04:21:39.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.04:21:39.72$vck44/va=8,4 2006.257.04:21:39.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.04:21:39.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.04:21:39.72#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:39.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:21:39.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:21:39.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:21:39.78#ibcon#enter wrdev, iclass 15, count 2 2006.257.04:21:39.78#ibcon#first serial, iclass 15, count 2 2006.257.04:21:39.78#ibcon#enter sib2, iclass 15, count 2 2006.257.04:21:39.78#ibcon#flushed, iclass 15, count 2 2006.257.04:21:39.78#ibcon#about to write, iclass 15, count 2 2006.257.04:21:39.78#ibcon#wrote, iclass 15, count 2 2006.257.04:21:39.78#ibcon#about to read 3, iclass 15, count 2 2006.257.04:21:39.80#ibcon#read 3, iclass 15, count 2 2006.257.04:21:39.80#ibcon#about to read 4, iclass 15, count 2 2006.257.04:21:39.80#ibcon#read 4, iclass 15, count 2 2006.257.04:21:39.80#ibcon#about to read 5, iclass 15, count 2 2006.257.04:21:39.80#ibcon#read 5, iclass 15, count 2 2006.257.04:21:39.80#ibcon#about to read 6, iclass 15, count 2 2006.257.04:21:39.80#ibcon#read 6, iclass 15, count 2 2006.257.04:21:39.80#ibcon#end of sib2, iclass 15, count 2 2006.257.04:21:39.80#ibcon#*mode == 0, iclass 15, count 2 2006.257.04:21:39.80#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.04:21:39.80#ibcon#[25=AT08-04\r\n] 2006.257.04:21:39.80#ibcon#*before write, iclass 15, count 2 2006.257.04:21:39.80#ibcon#enter sib2, iclass 15, count 2 2006.257.04:21:39.80#ibcon#flushed, iclass 15, count 2 2006.257.04:21:39.80#ibcon#about to write, iclass 15, count 2 2006.257.04:21:39.80#ibcon#wrote, iclass 15, count 2 2006.257.04:21:39.80#ibcon#about to read 3, iclass 15, count 2 2006.257.04:21:39.83#ibcon#read 3, iclass 15, count 2 2006.257.04:21:39.83#ibcon#about to read 4, iclass 15, count 2 2006.257.04:21:39.83#ibcon#read 4, iclass 15, count 2 2006.257.04:21:39.83#ibcon#about to read 5, iclass 15, count 2 2006.257.04:21:39.83#ibcon#read 5, iclass 15, count 2 2006.257.04:21:39.83#ibcon#about to read 6, iclass 15, count 2 2006.257.04:21:39.83#ibcon#read 6, iclass 15, count 2 2006.257.04:21:39.83#ibcon#end of sib2, iclass 15, count 2 2006.257.04:21:39.83#ibcon#*after write, iclass 15, count 2 2006.257.04:21:39.83#ibcon#*before return 0, iclass 15, count 2 2006.257.04:21:39.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:21:39.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:21:39.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.04:21:39.83#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:39.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:21:39.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:21:39.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:21:39.95#ibcon#enter wrdev, iclass 15, count 0 2006.257.04:21:39.95#ibcon#first serial, iclass 15, count 0 2006.257.04:21:39.95#ibcon#enter sib2, iclass 15, count 0 2006.257.04:21:39.95#ibcon#flushed, iclass 15, count 0 2006.257.04:21:39.95#ibcon#about to write, iclass 15, count 0 2006.257.04:21:39.95#ibcon#wrote, iclass 15, count 0 2006.257.04:21:39.95#ibcon#about to read 3, iclass 15, count 0 2006.257.04:21:39.97#ibcon#read 3, iclass 15, count 0 2006.257.04:21:39.97#ibcon#about to read 4, iclass 15, count 0 2006.257.04:21:39.97#ibcon#read 4, iclass 15, count 0 2006.257.04:21:39.97#ibcon#about to read 5, iclass 15, count 0 2006.257.04:21:39.97#ibcon#read 5, iclass 15, count 0 2006.257.04:21:39.97#ibcon#about to read 6, iclass 15, count 0 2006.257.04:21:39.97#ibcon#read 6, iclass 15, count 0 2006.257.04:21:39.97#ibcon#end of sib2, iclass 15, count 0 2006.257.04:21:39.97#ibcon#*mode == 0, iclass 15, count 0 2006.257.04:21:39.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.04:21:39.97#ibcon#[25=USB\r\n] 2006.257.04:21:39.97#ibcon#*before write, iclass 15, count 0 2006.257.04:21:39.97#ibcon#enter sib2, iclass 15, count 0 2006.257.04:21:39.97#ibcon#flushed, iclass 15, count 0 2006.257.04:21:39.97#ibcon#about to write, iclass 15, count 0 2006.257.04:21:39.97#ibcon#wrote, iclass 15, count 0 2006.257.04:21:39.97#ibcon#about to read 3, iclass 15, count 0 2006.257.04:21:40.00#ibcon#read 3, iclass 15, count 0 2006.257.04:21:40.00#ibcon#about to read 4, iclass 15, count 0 2006.257.04:21:40.00#ibcon#read 4, iclass 15, count 0 2006.257.04:21:40.00#ibcon#about to read 5, iclass 15, count 0 2006.257.04:21:40.00#ibcon#read 5, iclass 15, count 0 2006.257.04:21:40.00#ibcon#about to read 6, iclass 15, count 0 2006.257.04:21:40.00#ibcon#read 6, iclass 15, count 0 2006.257.04:21:40.00#ibcon#end of sib2, iclass 15, count 0 2006.257.04:21:40.00#ibcon#*after write, iclass 15, count 0 2006.257.04:21:40.00#ibcon#*before return 0, iclass 15, count 0 2006.257.04:21:40.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:21:40.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:21:40.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.04:21:40.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.04:21:40.00$vck44/vblo=1,629.99 2006.257.04:21:40.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.04:21:40.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.04:21:40.00#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:40.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:21:40.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:21:40.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:21:40.00#ibcon#enter wrdev, iclass 17, count 0 2006.257.04:21:40.00#ibcon#first serial, iclass 17, count 0 2006.257.04:21:40.00#ibcon#enter sib2, iclass 17, count 0 2006.257.04:21:40.00#ibcon#flushed, iclass 17, count 0 2006.257.04:21:40.00#ibcon#about to write, iclass 17, count 0 2006.257.04:21:40.00#ibcon#wrote, iclass 17, count 0 2006.257.04:21:40.00#ibcon#about to read 3, iclass 17, count 0 2006.257.04:21:40.02#ibcon#read 3, iclass 17, count 0 2006.257.04:21:40.02#ibcon#about to read 4, iclass 17, count 0 2006.257.04:21:40.02#ibcon#read 4, iclass 17, count 0 2006.257.04:21:40.02#ibcon#about to read 5, iclass 17, count 0 2006.257.04:21:40.02#ibcon#read 5, iclass 17, count 0 2006.257.04:21:40.02#ibcon#about to read 6, iclass 17, count 0 2006.257.04:21:40.02#ibcon#read 6, iclass 17, count 0 2006.257.04:21:40.02#ibcon#end of sib2, iclass 17, count 0 2006.257.04:21:40.02#ibcon#*mode == 0, iclass 17, count 0 2006.257.04:21:40.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.04:21:40.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.04:21:40.02#ibcon#*before write, iclass 17, count 0 2006.257.04:21:40.02#ibcon#enter sib2, iclass 17, count 0 2006.257.04:21:40.02#ibcon#flushed, iclass 17, count 0 2006.257.04:21:40.02#ibcon#about to write, iclass 17, count 0 2006.257.04:21:40.02#ibcon#wrote, iclass 17, count 0 2006.257.04:21:40.02#ibcon#about to read 3, iclass 17, count 0 2006.257.04:21:40.06#ibcon#read 3, iclass 17, count 0 2006.257.04:21:40.06#ibcon#about to read 4, iclass 17, count 0 2006.257.04:21:40.06#ibcon#read 4, iclass 17, count 0 2006.257.04:21:40.06#ibcon#about to read 5, iclass 17, count 0 2006.257.04:21:40.06#ibcon#read 5, iclass 17, count 0 2006.257.04:21:40.06#ibcon#about to read 6, iclass 17, count 0 2006.257.04:21:40.06#ibcon#read 6, iclass 17, count 0 2006.257.04:21:40.06#ibcon#end of sib2, iclass 17, count 0 2006.257.04:21:40.06#ibcon#*after write, iclass 17, count 0 2006.257.04:21:40.06#ibcon#*before return 0, iclass 17, count 0 2006.257.04:21:40.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:21:40.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:21:40.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.04:21:40.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.04:21:40.06$vck44/vb=1,4 2006.257.04:21:40.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.04:21:40.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.04:21:40.06#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:40.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:21:40.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:21:40.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:21:40.06#ibcon#enter wrdev, iclass 19, count 2 2006.257.04:21:40.06#ibcon#first serial, iclass 19, count 2 2006.257.04:21:40.06#ibcon#enter sib2, iclass 19, count 2 2006.257.04:21:40.06#ibcon#flushed, iclass 19, count 2 2006.257.04:21:40.06#ibcon#about to write, iclass 19, count 2 2006.257.04:21:40.06#ibcon#wrote, iclass 19, count 2 2006.257.04:21:40.06#ibcon#about to read 3, iclass 19, count 2 2006.257.04:21:40.08#ibcon#read 3, iclass 19, count 2 2006.257.04:21:40.08#ibcon#about to read 4, iclass 19, count 2 2006.257.04:21:40.08#ibcon#read 4, iclass 19, count 2 2006.257.04:21:40.08#ibcon#about to read 5, iclass 19, count 2 2006.257.04:21:40.08#ibcon#read 5, iclass 19, count 2 2006.257.04:21:40.08#ibcon#about to read 6, iclass 19, count 2 2006.257.04:21:40.08#ibcon#read 6, iclass 19, count 2 2006.257.04:21:40.08#ibcon#end of sib2, iclass 19, count 2 2006.257.04:21:40.08#ibcon#*mode == 0, iclass 19, count 2 2006.257.04:21:40.08#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.04:21:40.08#ibcon#[27=AT01-04\r\n] 2006.257.04:21:40.08#ibcon#*before write, iclass 19, count 2 2006.257.04:21:40.08#ibcon#enter sib2, iclass 19, count 2 2006.257.04:21:40.08#ibcon#flushed, iclass 19, count 2 2006.257.04:21:40.08#ibcon#about to write, iclass 19, count 2 2006.257.04:21:40.08#ibcon#wrote, iclass 19, count 2 2006.257.04:21:40.08#ibcon#about to read 3, iclass 19, count 2 2006.257.04:21:40.11#ibcon#read 3, iclass 19, count 2 2006.257.04:21:40.11#ibcon#about to read 4, iclass 19, count 2 2006.257.04:21:40.11#ibcon#read 4, iclass 19, count 2 2006.257.04:21:40.11#ibcon#about to read 5, iclass 19, count 2 2006.257.04:21:40.11#ibcon#read 5, iclass 19, count 2 2006.257.04:21:40.11#ibcon#about to read 6, iclass 19, count 2 2006.257.04:21:40.11#ibcon#read 6, iclass 19, count 2 2006.257.04:21:40.11#ibcon#end of sib2, iclass 19, count 2 2006.257.04:21:40.11#ibcon#*after write, iclass 19, count 2 2006.257.04:21:40.11#ibcon#*before return 0, iclass 19, count 2 2006.257.04:21:40.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:21:40.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:21:40.11#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.04:21:40.11#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:40.11#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:21:40.23#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:21:40.23#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:21:40.23#ibcon#enter wrdev, iclass 19, count 0 2006.257.04:21:40.23#ibcon#first serial, iclass 19, count 0 2006.257.04:21:40.23#ibcon#enter sib2, iclass 19, count 0 2006.257.04:21:40.23#ibcon#flushed, iclass 19, count 0 2006.257.04:21:40.23#ibcon#about to write, iclass 19, count 0 2006.257.04:21:40.23#ibcon#wrote, iclass 19, count 0 2006.257.04:21:40.23#ibcon#about to read 3, iclass 19, count 0 2006.257.04:21:40.25#ibcon#read 3, iclass 19, count 0 2006.257.04:21:40.25#ibcon#about to read 4, iclass 19, count 0 2006.257.04:21:40.25#ibcon#read 4, iclass 19, count 0 2006.257.04:21:40.25#ibcon#about to read 5, iclass 19, count 0 2006.257.04:21:40.25#ibcon#read 5, iclass 19, count 0 2006.257.04:21:40.25#ibcon#about to read 6, iclass 19, count 0 2006.257.04:21:40.25#ibcon#read 6, iclass 19, count 0 2006.257.04:21:40.25#ibcon#end of sib2, iclass 19, count 0 2006.257.04:21:40.25#ibcon#*mode == 0, iclass 19, count 0 2006.257.04:21:40.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.04:21:40.25#ibcon#[27=USB\r\n] 2006.257.04:21:40.25#ibcon#*before write, iclass 19, count 0 2006.257.04:21:40.25#ibcon#enter sib2, iclass 19, count 0 2006.257.04:21:40.25#ibcon#flushed, iclass 19, count 0 2006.257.04:21:40.25#ibcon#about to write, iclass 19, count 0 2006.257.04:21:40.25#ibcon#wrote, iclass 19, count 0 2006.257.04:21:40.25#ibcon#about to read 3, iclass 19, count 0 2006.257.04:21:40.28#ibcon#read 3, iclass 19, count 0 2006.257.04:21:40.28#ibcon#about to read 4, iclass 19, count 0 2006.257.04:21:40.28#ibcon#read 4, iclass 19, count 0 2006.257.04:21:40.28#ibcon#about to read 5, iclass 19, count 0 2006.257.04:21:40.28#ibcon#read 5, iclass 19, count 0 2006.257.04:21:40.28#ibcon#about to read 6, iclass 19, count 0 2006.257.04:21:40.28#ibcon#read 6, iclass 19, count 0 2006.257.04:21:40.28#ibcon#end of sib2, iclass 19, count 0 2006.257.04:21:40.28#ibcon#*after write, iclass 19, count 0 2006.257.04:21:40.28#ibcon#*before return 0, iclass 19, count 0 2006.257.04:21:40.28#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:21:40.28#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:21:40.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.04:21:40.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.04:21:40.28$vck44/vblo=2,634.99 2006.257.04:21:40.28#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.04:21:40.28#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.04:21:40.28#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:40.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:40.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:40.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:40.28#ibcon#enter wrdev, iclass 21, count 0 2006.257.04:21:40.28#ibcon#first serial, iclass 21, count 0 2006.257.04:21:40.28#ibcon#enter sib2, iclass 21, count 0 2006.257.04:21:40.28#ibcon#flushed, iclass 21, count 0 2006.257.04:21:40.28#ibcon#about to write, iclass 21, count 0 2006.257.04:21:40.28#ibcon#wrote, iclass 21, count 0 2006.257.04:21:40.28#ibcon#about to read 3, iclass 21, count 0 2006.257.04:21:40.30#ibcon#read 3, iclass 21, count 0 2006.257.04:21:40.30#ibcon#about to read 4, iclass 21, count 0 2006.257.04:21:40.30#ibcon#read 4, iclass 21, count 0 2006.257.04:21:40.30#ibcon#about to read 5, iclass 21, count 0 2006.257.04:21:40.30#ibcon#read 5, iclass 21, count 0 2006.257.04:21:40.30#ibcon#about to read 6, iclass 21, count 0 2006.257.04:21:40.30#ibcon#read 6, iclass 21, count 0 2006.257.04:21:40.30#ibcon#end of sib2, iclass 21, count 0 2006.257.04:21:40.30#ibcon#*mode == 0, iclass 21, count 0 2006.257.04:21:40.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.04:21:40.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.04:21:40.30#ibcon#*before write, iclass 21, count 0 2006.257.04:21:40.30#ibcon#enter sib2, iclass 21, count 0 2006.257.04:21:40.30#ibcon#flushed, iclass 21, count 0 2006.257.04:21:40.30#ibcon#about to write, iclass 21, count 0 2006.257.04:21:40.30#ibcon#wrote, iclass 21, count 0 2006.257.04:21:40.30#ibcon#about to read 3, iclass 21, count 0 2006.257.04:21:40.34#ibcon#read 3, iclass 21, count 0 2006.257.04:21:40.34#ibcon#about to read 4, iclass 21, count 0 2006.257.04:21:40.34#ibcon#read 4, iclass 21, count 0 2006.257.04:21:40.34#ibcon#about to read 5, iclass 21, count 0 2006.257.04:21:40.34#ibcon#read 5, iclass 21, count 0 2006.257.04:21:40.34#ibcon#about to read 6, iclass 21, count 0 2006.257.04:21:40.34#ibcon#read 6, iclass 21, count 0 2006.257.04:21:40.34#ibcon#end of sib2, iclass 21, count 0 2006.257.04:21:40.34#ibcon#*after write, iclass 21, count 0 2006.257.04:21:40.34#ibcon#*before return 0, iclass 21, count 0 2006.257.04:21:40.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:40.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:21:40.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.04:21:40.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.04:21:40.34$vck44/vb=2,5 2006.257.04:21:40.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.04:21:40.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.04:21:40.34#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:40.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:40.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:40.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:40.40#ibcon#enter wrdev, iclass 23, count 2 2006.257.04:21:40.40#ibcon#first serial, iclass 23, count 2 2006.257.04:21:40.40#ibcon#enter sib2, iclass 23, count 2 2006.257.04:21:40.40#ibcon#flushed, iclass 23, count 2 2006.257.04:21:40.40#ibcon#about to write, iclass 23, count 2 2006.257.04:21:40.40#ibcon#wrote, iclass 23, count 2 2006.257.04:21:40.40#ibcon#about to read 3, iclass 23, count 2 2006.257.04:21:40.42#ibcon#read 3, iclass 23, count 2 2006.257.04:21:40.42#ibcon#about to read 4, iclass 23, count 2 2006.257.04:21:40.42#ibcon#read 4, iclass 23, count 2 2006.257.04:21:40.42#ibcon#about to read 5, iclass 23, count 2 2006.257.04:21:40.42#ibcon#read 5, iclass 23, count 2 2006.257.04:21:40.42#ibcon#about to read 6, iclass 23, count 2 2006.257.04:21:40.42#ibcon#read 6, iclass 23, count 2 2006.257.04:21:40.42#ibcon#end of sib2, iclass 23, count 2 2006.257.04:21:40.42#ibcon#*mode == 0, iclass 23, count 2 2006.257.04:21:40.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.04:21:40.42#ibcon#[27=AT02-05\r\n] 2006.257.04:21:40.42#ibcon#*before write, iclass 23, count 2 2006.257.04:21:40.42#ibcon#enter sib2, iclass 23, count 2 2006.257.04:21:40.42#ibcon#flushed, iclass 23, count 2 2006.257.04:21:40.42#ibcon#about to write, iclass 23, count 2 2006.257.04:21:40.42#ibcon#wrote, iclass 23, count 2 2006.257.04:21:40.42#ibcon#about to read 3, iclass 23, count 2 2006.257.04:21:40.45#ibcon#read 3, iclass 23, count 2 2006.257.04:21:40.45#ibcon#about to read 4, iclass 23, count 2 2006.257.04:21:40.45#ibcon#read 4, iclass 23, count 2 2006.257.04:21:40.45#ibcon#about to read 5, iclass 23, count 2 2006.257.04:21:40.45#ibcon#read 5, iclass 23, count 2 2006.257.04:21:40.45#ibcon#about to read 6, iclass 23, count 2 2006.257.04:21:40.45#ibcon#read 6, iclass 23, count 2 2006.257.04:21:40.45#ibcon#end of sib2, iclass 23, count 2 2006.257.04:21:40.45#ibcon#*after write, iclass 23, count 2 2006.257.04:21:40.45#ibcon#*before return 0, iclass 23, count 2 2006.257.04:21:40.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:40.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:21:40.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.04:21:40.45#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:40.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:40.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:40.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:40.57#ibcon#enter wrdev, iclass 23, count 0 2006.257.04:21:40.57#ibcon#first serial, iclass 23, count 0 2006.257.04:21:40.57#ibcon#enter sib2, iclass 23, count 0 2006.257.04:21:40.57#ibcon#flushed, iclass 23, count 0 2006.257.04:21:40.57#ibcon#about to write, iclass 23, count 0 2006.257.04:21:40.57#ibcon#wrote, iclass 23, count 0 2006.257.04:21:40.57#ibcon#about to read 3, iclass 23, count 0 2006.257.04:21:40.59#ibcon#read 3, iclass 23, count 0 2006.257.04:21:40.59#ibcon#about to read 4, iclass 23, count 0 2006.257.04:21:40.59#ibcon#read 4, iclass 23, count 0 2006.257.04:21:40.59#ibcon#about to read 5, iclass 23, count 0 2006.257.04:21:40.59#ibcon#read 5, iclass 23, count 0 2006.257.04:21:40.59#ibcon#about to read 6, iclass 23, count 0 2006.257.04:21:40.59#ibcon#read 6, iclass 23, count 0 2006.257.04:21:40.59#ibcon#end of sib2, iclass 23, count 0 2006.257.04:21:40.59#ibcon#*mode == 0, iclass 23, count 0 2006.257.04:21:40.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.04:21:40.59#ibcon#[27=USB\r\n] 2006.257.04:21:40.59#ibcon#*before write, iclass 23, count 0 2006.257.04:21:40.59#ibcon#enter sib2, iclass 23, count 0 2006.257.04:21:40.59#ibcon#flushed, iclass 23, count 0 2006.257.04:21:40.59#ibcon#about to write, iclass 23, count 0 2006.257.04:21:40.59#ibcon#wrote, iclass 23, count 0 2006.257.04:21:40.59#ibcon#about to read 3, iclass 23, count 0 2006.257.04:21:40.62#ibcon#read 3, iclass 23, count 0 2006.257.04:21:40.62#ibcon#about to read 4, iclass 23, count 0 2006.257.04:21:40.62#ibcon#read 4, iclass 23, count 0 2006.257.04:21:40.62#ibcon#about to read 5, iclass 23, count 0 2006.257.04:21:40.62#ibcon#read 5, iclass 23, count 0 2006.257.04:21:40.62#ibcon#about to read 6, iclass 23, count 0 2006.257.04:21:40.62#ibcon#read 6, iclass 23, count 0 2006.257.04:21:40.62#ibcon#end of sib2, iclass 23, count 0 2006.257.04:21:40.62#ibcon#*after write, iclass 23, count 0 2006.257.04:21:40.62#ibcon#*before return 0, iclass 23, count 0 2006.257.04:21:40.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:40.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:21:40.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.04:21:40.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.04:21:40.62$vck44/vblo=3,649.99 2006.257.04:21:40.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.04:21:40.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.04:21:40.62#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:40.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:40.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:40.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:40.62#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:21:40.62#ibcon#first serial, iclass 25, count 0 2006.257.04:21:40.62#ibcon#enter sib2, iclass 25, count 0 2006.257.04:21:40.62#ibcon#flushed, iclass 25, count 0 2006.257.04:21:40.62#ibcon#about to write, iclass 25, count 0 2006.257.04:21:40.62#ibcon#wrote, iclass 25, count 0 2006.257.04:21:40.62#ibcon#about to read 3, iclass 25, count 0 2006.257.04:21:40.64#ibcon#read 3, iclass 25, count 0 2006.257.04:21:40.64#ibcon#about to read 4, iclass 25, count 0 2006.257.04:21:40.64#ibcon#read 4, iclass 25, count 0 2006.257.04:21:40.64#ibcon#about to read 5, iclass 25, count 0 2006.257.04:21:40.64#ibcon#read 5, iclass 25, count 0 2006.257.04:21:40.64#ibcon#about to read 6, iclass 25, count 0 2006.257.04:21:40.64#ibcon#read 6, iclass 25, count 0 2006.257.04:21:40.64#ibcon#end of sib2, iclass 25, count 0 2006.257.04:21:40.64#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:21:40.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:21:40.64#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.04:21:40.64#ibcon#*before write, iclass 25, count 0 2006.257.04:21:40.64#ibcon#enter sib2, iclass 25, count 0 2006.257.04:21:40.64#ibcon#flushed, iclass 25, count 0 2006.257.04:21:40.64#ibcon#about to write, iclass 25, count 0 2006.257.04:21:40.64#ibcon#wrote, iclass 25, count 0 2006.257.04:21:40.64#ibcon#about to read 3, iclass 25, count 0 2006.257.04:21:40.68#ibcon#read 3, iclass 25, count 0 2006.257.04:21:40.68#ibcon#about to read 4, iclass 25, count 0 2006.257.04:21:40.68#ibcon#read 4, iclass 25, count 0 2006.257.04:21:40.68#ibcon#about to read 5, iclass 25, count 0 2006.257.04:21:40.68#ibcon#read 5, iclass 25, count 0 2006.257.04:21:40.68#ibcon#about to read 6, iclass 25, count 0 2006.257.04:21:40.68#ibcon#read 6, iclass 25, count 0 2006.257.04:21:40.68#ibcon#end of sib2, iclass 25, count 0 2006.257.04:21:40.68#ibcon#*after write, iclass 25, count 0 2006.257.04:21:40.68#ibcon#*before return 0, iclass 25, count 0 2006.257.04:21:40.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:40.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:21:40.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:21:40.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:21:40.68$vck44/vb=3,4 2006.257.04:21:40.68#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.04:21:40.68#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.04:21:40.68#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:40.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:40.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:40.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:40.74#ibcon#enter wrdev, iclass 27, count 2 2006.257.04:21:40.74#ibcon#first serial, iclass 27, count 2 2006.257.04:21:40.74#ibcon#enter sib2, iclass 27, count 2 2006.257.04:21:40.74#ibcon#flushed, iclass 27, count 2 2006.257.04:21:40.74#ibcon#about to write, iclass 27, count 2 2006.257.04:21:40.74#ibcon#wrote, iclass 27, count 2 2006.257.04:21:40.74#ibcon#about to read 3, iclass 27, count 2 2006.257.04:21:40.76#ibcon#read 3, iclass 27, count 2 2006.257.04:21:40.76#ibcon#about to read 4, iclass 27, count 2 2006.257.04:21:40.76#ibcon#read 4, iclass 27, count 2 2006.257.04:21:40.76#ibcon#about to read 5, iclass 27, count 2 2006.257.04:21:40.76#ibcon#read 5, iclass 27, count 2 2006.257.04:21:40.76#ibcon#about to read 6, iclass 27, count 2 2006.257.04:21:40.76#ibcon#read 6, iclass 27, count 2 2006.257.04:21:40.76#ibcon#end of sib2, iclass 27, count 2 2006.257.04:21:40.76#ibcon#*mode == 0, iclass 27, count 2 2006.257.04:21:40.76#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.04:21:40.76#ibcon#[27=AT03-04\r\n] 2006.257.04:21:40.76#ibcon#*before write, iclass 27, count 2 2006.257.04:21:40.76#ibcon#enter sib2, iclass 27, count 2 2006.257.04:21:40.76#ibcon#flushed, iclass 27, count 2 2006.257.04:21:40.76#ibcon#about to write, iclass 27, count 2 2006.257.04:21:40.76#ibcon#wrote, iclass 27, count 2 2006.257.04:21:40.76#ibcon#about to read 3, iclass 27, count 2 2006.257.04:21:40.79#ibcon#read 3, iclass 27, count 2 2006.257.04:21:40.79#ibcon#about to read 4, iclass 27, count 2 2006.257.04:21:40.79#ibcon#read 4, iclass 27, count 2 2006.257.04:21:40.79#ibcon#about to read 5, iclass 27, count 2 2006.257.04:21:40.79#ibcon#read 5, iclass 27, count 2 2006.257.04:21:40.79#ibcon#about to read 6, iclass 27, count 2 2006.257.04:21:40.79#ibcon#read 6, iclass 27, count 2 2006.257.04:21:40.79#ibcon#end of sib2, iclass 27, count 2 2006.257.04:21:40.79#ibcon#*after write, iclass 27, count 2 2006.257.04:21:40.79#ibcon#*before return 0, iclass 27, count 2 2006.257.04:21:40.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:40.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:21:40.79#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.04:21:40.79#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:40.79#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:40.91#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:40.91#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:40.91#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:21:40.91#ibcon#first serial, iclass 27, count 0 2006.257.04:21:40.91#ibcon#enter sib2, iclass 27, count 0 2006.257.04:21:40.91#ibcon#flushed, iclass 27, count 0 2006.257.04:21:40.91#ibcon#about to write, iclass 27, count 0 2006.257.04:21:40.91#ibcon#wrote, iclass 27, count 0 2006.257.04:21:40.91#ibcon#about to read 3, iclass 27, count 0 2006.257.04:21:40.93#ibcon#read 3, iclass 27, count 0 2006.257.04:21:40.93#ibcon#about to read 4, iclass 27, count 0 2006.257.04:21:40.93#ibcon#read 4, iclass 27, count 0 2006.257.04:21:40.93#ibcon#about to read 5, iclass 27, count 0 2006.257.04:21:40.93#ibcon#read 5, iclass 27, count 0 2006.257.04:21:40.93#ibcon#about to read 6, iclass 27, count 0 2006.257.04:21:40.93#ibcon#read 6, iclass 27, count 0 2006.257.04:21:40.93#ibcon#end of sib2, iclass 27, count 0 2006.257.04:21:40.93#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:21:40.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:21:40.93#ibcon#[27=USB\r\n] 2006.257.04:21:40.93#ibcon#*before write, iclass 27, count 0 2006.257.04:21:40.93#ibcon#enter sib2, iclass 27, count 0 2006.257.04:21:40.93#ibcon#flushed, iclass 27, count 0 2006.257.04:21:40.93#ibcon#about to write, iclass 27, count 0 2006.257.04:21:40.93#ibcon#wrote, iclass 27, count 0 2006.257.04:21:40.93#ibcon#about to read 3, iclass 27, count 0 2006.257.04:21:40.96#ibcon#read 3, iclass 27, count 0 2006.257.04:21:40.96#ibcon#about to read 4, iclass 27, count 0 2006.257.04:21:40.96#ibcon#read 4, iclass 27, count 0 2006.257.04:21:40.96#ibcon#about to read 5, iclass 27, count 0 2006.257.04:21:40.96#ibcon#read 5, iclass 27, count 0 2006.257.04:21:40.96#ibcon#about to read 6, iclass 27, count 0 2006.257.04:21:40.96#ibcon#read 6, iclass 27, count 0 2006.257.04:21:40.96#ibcon#end of sib2, iclass 27, count 0 2006.257.04:21:40.96#ibcon#*after write, iclass 27, count 0 2006.257.04:21:40.96#ibcon#*before return 0, iclass 27, count 0 2006.257.04:21:40.96#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:40.96#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:21:40.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:21:40.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:21:40.96$vck44/vblo=4,679.99 2006.257.04:21:40.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.04:21:40.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.04:21:40.96#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:40.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:40.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:40.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:40.96#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:21:40.96#ibcon#first serial, iclass 29, count 0 2006.257.04:21:40.96#ibcon#enter sib2, iclass 29, count 0 2006.257.04:21:40.96#ibcon#flushed, iclass 29, count 0 2006.257.04:21:40.96#ibcon#about to write, iclass 29, count 0 2006.257.04:21:40.96#ibcon#wrote, iclass 29, count 0 2006.257.04:21:40.96#ibcon#about to read 3, iclass 29, count 0 2006.257.04:21:40.98#ibcon#read 3, iclass 29, count 0 2006.257.04:21:40.98#ibcon#about to read 4, iclass 29, count 0 2006.257.04:21:40.98#ibcon#read 4, iclass 29, count 0 2006.257.04:21:40.98#ibcon#about to read 5, iclass 29, count 0 2006.257.04:21:40.98#ibcon#read 5, iclass 29, count 0 2006.257.04:21:40.98#ibcon#about to read 6, iclass 29, count 0 2006.257.04:21:40.98#ibcon#read 6, iclass 29, count 0 2006.257.04:21:40.98#ibcon#end of sib2, iclass 29, count 0 2006.257.04:21:40.98#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:21:40.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:21:40.98#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.04:21:40.98#ibcon#*before write, iclass 29, count 0 2006.257.04:21:40.98#ibcon#enter sib2, iclass 29, count 0 2006.257.04:21:40.98#ibcon#flushed, iclass 29, count 0 2006.257.04:21:40.98#ibcon#about to write, iclass 29, count 0 2006.257.04:21:40.98#ibcon#wrote, iclass 29, count 0 2006.257.04:21:40.98#ibcon#about to read 3, iclass 29, count 0 2006.257.04:21:41.02#ibcon#read 3, iclass 29, count 0 2006.257.04:21:41.02#ibcon#about to read 4, iclass 29, count 0 2006.257.04:21:41.02#ibcon#read 4, iclass 29, count 0 2006.257.04:21:41.02#ibcon#about to read 5, iclass 29, count 0 2006.257.04:21:41.02#ibcon#read 5, iclass 29, count 0 2006.257.04:21:41.02#ibcon#about to read 6, iclass 29, count 0 2006.257.04:21:41.02#ibcon#read 6, iclass 29, count 0 2006.257.04:21:41.02#ibcon#end of sib2, iclass 29, count 0 2006.257.04:21:41.02#ibcon#*after write, iclass 29, count 0 2006.257.04:21:41.02#ibcon#*before return 0, iclass 29, count 0 2006.257.04:21:41.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:41.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:21:41.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:21:41.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:21:41.02$vck44/vb=4,5 2006.257.04:21:41.02#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.04:21:41.02#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.04:21:41.02#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:41.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:41.08#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:41.08#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:41.08#ibcon#enter wrdev, iclass 31, count 2 2006.257.04:21:41.08#ibcon#first serial, iclass 31, count 2 2006.257.04:21:41.08#ibcon#enter sib2, iclass 31, count 2 2006.257.04:21:41.08#ibcon#flushed, iclass 31, count 2 2006.257.04:21:41.08#ibcon#about to write, iclass 31, count 2 2006.257.04:21:41.08#ibcon#wrote, iclass 31, count 2 2006.257.04:21:41.08#ibcon#about to read 3, iclass 31, count 2 2006.257.04:21:41.10#ibcon#read 3, iclass 31, count 2 2006.257.04:21:41.10#ibcon#about to read 4, iclass 31, count 2 2006.257.04:21:41.10#ibcon#read 4, iclass 31, count 2 2006.257.04:21:41.10#ibcon#about to read 5, iclass 31, count 2 2006.257.04:21:41.10#ibcon#read 5, iclass 31, count 2 2006.257.04:21:41.10#ibcon#about to read 6, iclass 31, count 2 2006.257.04:21:41.10#ibcon#read 6, iclass 31, count 2 2006.257.04:21:41.10#ibcon#end of sib2, iclass 31, count 2 2006.257.04:21:41.10#ibcon#*mode == 0, iclass 31, count 2 2006.257.04:21:41.10#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.04:21:41.10#ibcon#[27=AT04-05\r\n] 2006.257.04:21:41.10#ibcon#*before write, iclass 31, count 2 2006.257.04:21:41.10#ibcon#enter sib2, iclass 31, count 2 2006.257.04:21:41.10#ibcon#flushed, iclass 31, count 2 2006.257.04:21:41.10#ibcon#about to write, iclass 31, count 2 2006.257.04:21:41.10#ibcon#wrote, iclass 31, count 2 2006.257.04:21:41.10#ibcon#about to read 3, iclass 31, count 2 2006.257.04:21:41.13#ibcon#read 3, iclass 31, count 2 2006.257.04:21:41.13#ibcon#about to read 4, iclass 31, count 2 2006.257.04:21:41.13#ibcon#read 4, iclass 31, count 2 2006.257.04:21:41.13#ibcon#about to read 5, iclass 31, count 2 2006.257.04:21:41.13#ibcon#read 5, iclass 31, count 2 2006.257.04:21:41.13#ibcon#about to read 6, iclass 31, count 2 2006.257.04:21:41.13#ibcon#read 6, iclass 31, count 2 2006.257.04:21:41.13#ibcon#end of sib2, iclass 31, count 2 2006.257.04:21:41.13#ibcon#*after write, iclass 31, count 2 2006.257.04:21:41.13#ibcon#*before return 0, iclass 31, count 2 2006.257.04:21:41.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:41.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:21:41.13#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.04:21:41.13#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:41.13#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:41.25#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:41.25#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:41.25#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:21:41.25#ibcon#first serial, iclass 31, count 0 2006.257.04:21:41.25#ibcon#enter sib2, iclass 31, count 0 2006.257.04:21:41.25#ibcon#flushed, iclass 31, count 0 2006.257.04:21:41.25#ibcon#about to write, iclass 31, count 0 2006.257.04:21:41.25#ibcon#wrote, iclass 31, count 0 2006.257.04:21:41.25#ibcon#about to read 3, iclass 31, count 0 2006.257.04:21:41.27#ibcon#read 3, iclass 31, count 0 2006.257.04:21:41.27#ibcon#about to read 4, iclass 31, count 0 2006.257.04:21:41.27#ibcon#read 4, iclass 31, count 0 2006.257.04:21:41.27#ibcon#about to read 5, iclass 31, count 0 2006.257.04:21:41.27#ibcon#read 5, iclass 31, count 0 2006.257.04:21:41.27#ibcon#about to read 6, iclass 31, count 0 2006.257.04:21:41.27#ibcon#read 6, iclass 31, count 0 2006.257.04:21:41.27#ibcon#end of sib2, iclass 31, count 0 2006.257.04:21:41.27#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:21:41.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:21:41.27#ibcon#[27=USB\r\n] 2006.257.04:21:41.27#ibcon#*before write, iclass 31, count 0 2006.257.04:21:41.27#ibcon#enter sib2, iclass 31, count 0 2006.257.04:21:41.27#ibcon#flushed, iclass 31, count 0 2006.257.04:21:41.27#ibcon#about to write, iclass 31, count 0 2006.257.04:21:41.27#ibcon#wrote, iclass 31, count 0 2006.257.04:21:41.27#ibcon#about to read 3, iclass 31, count 0 2006.257.04:21:41.30#ibcon#read 3, iclass 31, count 0 2006.257.04:21:41.30#ibcon#about to read 4, iclass 31, count 0 2006.257.04:21:41.30#ibcon#read 4, iclass 31, count 0 2006.257.04:21:41.30#ibcon#about to read 5, iclass 31, count 0 2006.257.04:21:41.30#ibcon#read 5, iclass 31, count 0 2006.257.04:21:41.30#ibcon#about to read 6, iclass 31, count 0 2006.257.04:21:41.30#ibcon#read 6, iclass 31, count 0 2006.257.04:21:41.30#ibcon#end of sib2, iclass 31, count 0 2006.257.04:21:41.30#ibcon#*after write, iclass 31, count 0 2006.257.04:21:41.30#ibcon#*before return 0, iclass 31, count 0 2006.257.04:21:41.30#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:41.30#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:21:41.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:21:41.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:21:41.30$vck44/vblo=5,709.99 2006.257.04:21:41.30#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.04:21:41.30#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.04:21:41.30#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:41.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:41.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:41.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:41.30#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:21:41.30#ibcon#first serial, iclass 33, count 0 2006.257.04:21:41.30#ibcon#enter sib2, iclass 33, count 0 2006.257.04:21:41.30#ibcon#flushed, iclass 33, count 0 2006.257.04:21:41.30#ibcon#about to write, iclass 33, count 0 2006.257.04:21:41.30#ibcon#wrote, iclass 33, count 0 2006.257.04:21:41.30#ibcon#about to read 3, iclass 33, count 0 2006.257.04:21:41.32#ibcon#read 3, iclass 33, count 0 2006.257.04:21:41.32#ibcon#about to read 4, iclass 33, count 0 2006.257.04:21:41.32#ibcon#read 4, iclass 33, count 0 2006.257.04:21:41.32#ibcon#about to read 5, iclass 33, count 0 2006.257.04:21:41.32#ibcon#read 5, iclass 33, count 0 2006.257.04:21:41.32#ibcon#about to read 6, iclass 33, count 0 2006.257.04:21:41.32#ibcon#read 6, iclass 33, count 0 2006.257.04:21:41.32#ibcon#end of sib2, iclass 33, count 0 2006.257.04:21:41.32#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:21:41.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:21:41.32#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.04:21:41.32#ibcon#*before write, iclass 33, count 0 2006.257.04:21:41.32#ibcon#enter sib2, iclass 33, count 0 2006.257.04:21:41.32#ibcon#flushed, iclass 33, count 0 2006.257.04:21:41.32#ibcon#about to write, iclass 33, count 0 2006.257.04:21:41.32#ibcon#wrote, iclass 33, count 0 2006.257.04:21:41.32#ibcon#about to read 3, iclass 33, count 0 2006.257.04:21:41.36#ibcon#read 3, iclass 33, count 0 2006.257.04:21:41.36#ibcon#about to read 4, iclass 33, count 0 2006.257.04:21:41.36#ibcon#read 4, iclass 33, count 0 2006.257.04:21:41.36#ibcon#about to read 5, iclass 33, count 0 2006.257.04:21:41.36#ibcon#read 5, iclass 33, count 0 2006.257.04:21:41.36#ibcon#about to read 6, iclass 33, count 0 2006.257.04:21:41.36#ibcon#read 6, iclass 33, count 0 2006.257.04:21:41.36#ibcon#end of sib2, iclass 33, count 0 2006.257.04:21:41.36#ibcon#*after write, iclass 33, count 0 2006.257.04:21:41.36#ibcon#*before return 0, iclass 33, count 0 2006.257.04:21:41.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:41.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:21:41.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:21:41.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:21:41.36$vck44/vb=5,4 2006.257.04:21:41.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.04:21:41.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.04:21:41.36#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:41.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:41.42#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:41.42#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:41.42#ibcon#enter wrdev, iclass 35, count 2 2006.257.04:21:41.42#ibcon#first serial, iclass 35, count 2 2006.257.04:21:41.42#ibcon#enter sib2, iclass 35, count 2 2006.257.04:21:41.42#ibcon#flushed, iclass 35, count 2 2006.257.04:21:41.42#ibcon#about to write, iclass 35, count 2 2006.257.04:21:41.42#ibcon#wrote, iclass 35, count 2 2006.257.04:21:41.42#ibcon#about to read 3, iclass 35, count 2 2006.257.04:21:41.44#ibcon#read 3, iclass 35, count 2 2006.257.04:21:41.44#ibcon#about to read 4, iclass 35, count 2 2006.257.04:21:41.44#ibcon#read 4, iclass 35, count 2 2006.257.04:21:41.44#ibcon#about to read 5, iclass 35, count 2 2006.257.04:21:41.44#ibcon#read 5, iclass 35, count 2 2006.257.04:21:41.44#ibcon#about to read 6, iclass 35, count 2 2006.257.04:21:41.44#ibcon#read 6, iclass 35, count 2 2006.257.04:21:41.44#ibcon#end of sib2, iclass 35, count 2 2006.257.04:21:41.44#ibcon#*mode == 0, iclass 35, count 2 2006.257.04:21:41.44#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.04:21:41.44#ibcon#[27=AT05-04\r\n] 2006.257.04:21:41.44#ibcon#*before write, iclass 35, count 2 2006.257.04:21:41.44#ibcon#enter sib2, iclass 35, count 2 2006.257.04:21:41.44#ibcon#flushed, iclass 35, count 2 2006.257.04:21:41.44#ibcon#about to write, iclass 35, count 2 2006.257.04:21:41.44#ibcon#wrote, iclass 35, count 2 2006.257.04:21:41.44#ibcon#about to read 3, iclass 35, count 2 2006.257.04:21:41.47#ibcon#read 3, iclass 35, count 2 2006.257.04:21:41.47#ibcon#about to read 4, iclass 35, count 2 2006.257.04:21:41.47#ibcon#read 4, iclass 35, count 2 2006.257.04:21:41.47#ibcon#about to read 5, iclass 35, count 2 2006.257.04:21:41.47#ibcon#read 5, iclass 35, count 2 2006.257.04:21:41.47#ibcon#about to read 6, iclass 35, count 2 2006.257.04:21:41.47#ibcon#read 6, iclass 35, count 2 2006.257.04:21:41.47#ibcon#end of sib2, iclass 35, count 2 2006.257.04:21:41.47#ibcon#*after write, iclass 35, count 2 2006.257.04:21:41.47#ibcon#*before return 0, iclass 35, count 2 2006.257.04:21:41.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:41.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:21:41.47#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.04:21:41.47#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:41.47#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:41.59#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:41.59#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:41.59#ibcon#enter wrdev, iclass 35, count 0 2006.257.04:21:41.59#ibcon#first serial, iclass 35, count 0 2006.257.04:21:41.59#ibcon#enter sib2, iclass 35, count 0 2006.257.04:21:41.59#ibcon#flushed, iclass 35, count 0 2006.257.04:21:41.59#ibcon#about to write, iclass 35, count 0 2006.257.04:21:41.59#ibcon#wrote, iclass 35, count 0 2006.257.04:21:41.59#ibcon#about to read 3, iclass 35, count 0 2006.257.04:21:41.61#ibcon#read 3, iclass 35, count 0 2006.257.04:21:41.61#ibcon#about to read 4, iclass 35, count 0 2006.257.04:21:41.61#ibcon#read 4, iclass 35, count 0 2006.257.04:21:41.61#ibcon#about to read 5, iclass 35, count 0 2006.257.04:21:41.61#ibcon#read 5, iclass 35, count 0 2006.257.04:21:41.61#ibcon#about to read 6, iclass 35, count 0 2006.257.04:21:41.61#ibcon#read 6, iclass 35, count 0 2006.257.04:21:41.61#ibcon#end of sib2, iclass 35, count 0 2006.257.04:21:41.61#ibcon#*mode == 0, iclass 35, count 0 2006.257.04:21:41.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.04:21:41.61#ibcon#[27=USB\r\n] 2006.257.04:21:41.61#ibcon#*before write, iclass 35, count 0 2006.257.04:21:41.61#ibcon#enter sib2, iclass 35, count 0 2006.257.04:21:41.61#ibcon#flushed, iclass 35, count 0 2006.257.04:21:41.61#ibcon#about to write, iclass 35, count 0 2006.257.04:21:41.61#ibcon#wrote, iclass 35, count 0 2006.257.04:21:41.61#ibcon#about to read 3, iclass 35, count 0 2006.257.04:21:41.64#ibcon#read 3, iclass 35, count 0 2006.257.04:21:41.64#ibcon#about to read 4, iclass 35, count 0 2006.257.04:21:41.64#ibcon#read 4, iclass 35, count 0 2006.257.04:21:41.64#ibcon#about to read 5, iclass 35, count 0 2006.257.04:21:41.64#ibcon#read 5, iclass 35, count 0 2006.257.04:21:41.64#ibcon#about to read 6, iclass 35, count 0 2006.257.04:21:41.64#ibcon#read 6, iclass 35, count 0 2006.257.04:21:41.64#ibcon#end of sib2, iclass 35, count 0 2006.257.04:21:41.64#ibcon#*after write, iclass 35, count 0 2006.257.04:21:41.64#ibcon#*before return 0, iclass 35, count 0 2006.257.04:21:41.64#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:41.64#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:21:41.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.04:21:41.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.04:21:41.64$vck44/vblo=6,719.99 2006.257.04:21:41.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.04:21:41.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.04:21:41.64#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:41.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:41.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:41.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:41.64#ibcon#enter wrdev, iclass 37, count 0 2006.257.04:21:41.64#ibcon#first serial, iclass 37, count 0 2006.257.04:21:41.64#ibcon#enter sib2, iclass 37, count 0 2006.257.04:21:41.64#ibcon#flushed, iclass 37, count 0 2006.257.04:21:41.64#ibcon#about to write, iclass 37, count 0 2006.257.04:21:41.64#ibcon#wrote, iclass 37, count 0 2006.257.04:21:41.64#ibcon#about to read 3, iclass 37, count 0 2006.257.04:21:41.66#ibcon#read 3, iclass 37, count 0 2006.257.04:21:41.66#ibcon#about to read 4, iclass 37, count 0 2006.257.04:21:41.66#ibcon#read 4, iclass 37, count 0 2006.257.04:21:41.66#ibcon#about to read 5, iclass 37, count 0 2006.257.04:21:41.66#ibcon#read 5, iclass 37, count 0 2006.257.04:21:41.66#ibcon#about to read 6, iclass 37, count 0 2006.257.04:21:41.66#ibcon#read 6, iclass 37, count 0 2006.257.04:21:41.66#ibcon#end of sib2, iclass 37, count 0 2006.257.04:21:41.66#ibcon#*mode == 0, iclass 37, count 0 2006.257.04:21:41.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.04:21:41.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.04:21:41.66#ibcon#*before write, iclass 37, count 0 2006.257.04:21:41.66#ibcon#enter sib2, iclass 37, count 0 2006.257.04:21:41.66#ibcon#flushed, iclass 37, count 0 2006.257.04:21:41.66#ibcon#about to write, iclass 37, count 0 2006.257.04:21:41.66#ibcon#wrote, iclass 37, count 0 2006.257.04:21:41.66#ibcon#about to read 3, iclass 37, count 0 2006.257.04:21:41.70#ibcon#read 3, iclass 37, count 0 2006.257.04:21:41.70#ibcon#about to read 4, iclass 37, count 0 2006.257.04:21:41.70#ibcon#read 4, iclass 37, count 0 2006.257.04:21:41.70#ibcon#about to read 5, iclass 37, count 0 2006.257.04:21:41.70#ibcon#read 5, iclass 37, count 0 2006.257.04:21:41.70#ibcon#about to read 6, iclass 37, count 0 2006.257.04:21:41.70#ibcon#read 6, iclass 37, count 0 2006.257.04:21:41.70#ibcon#end of sib2, iclass 37, count 0 2006.257.04:21:41.70#ibcon#*after write, iclass 37, count 0 2006.257.04:21:41.70#ibcon#*before return 0, iclass 37, count 0 2006.257.04:21:41.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:41.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:21:41.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.04:21:41.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.04:21:41.70$vck44/vb=6,4 2006.257.04:21:41.70#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.04:21:41.70#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.04:21:41.70#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:41.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:41.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:41.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:41.76#ibcon#enter wrdev, iclass 39, count 2 2006.257.04:21:41.76#ibcon#first serial, iclass 39, count 2 2006.257.04:21:41.76#ibcon#enter sib2, iclass 39, count 2 2006.257.04:21:41.76#ibcon#flushed, iclass 39, count 2 2006.257.04:21:41.76#ibcon#about to write, iclass 39, count 2 2006.257.04:21:41.76#ibcon#wrote, iclass 39, count 2 2006.257.04:21:41.76#ibcon#about to read 3, iclass 39, count 2 2006.257.04:21:41.78#ibcon#read 3, iclass 39, count 2 2006.257.04:21:41.78#ibcon#about to read 4, iclass 39, count 2 2006.257.04:21:41.78#ibcon#read 4, iclass 39, count 2 2006.257.04:21:41.78#ibcon#about to read 5, iclass 39, count 2 2006.257.04:21:41.78#ibcon#read 5, iclass 39, count 2 2006.257.04:21:41.78#ibcon#about to read 6, iclass 39, count 2 2006.257.04:21:41.78#ibcon#read 6, iclass 39, count 2 2006.257.04:21:41.78#ibcon#end of sib2, iclass 39, count 2 2006.257.04:21:41.78#ibcon#*mode == 0, iclass 39, count 2 2006.257.04:21:41.78#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.04:21:41.78#ibcon#[27=AT06-04\r\n] 2006.257.04:21:41.78#ibcon#*before write, iclass 39, count 2 2006.257.04:21:41.78#ibcon#enter sib2, iclass 39, count 2 2006.257.04:21:41.78#ibcon#flushed, iclass 39, count 2 2006.257.04:21:41.78#ibcon#about to write, iclass 39, count 2 2006.257.04:21:41.78#ibcon#wrote, iclass 39, count 2 2006.257.04:21:41.78#ibcon#about to read 3, iclass 39, count 2 2006.257.04:21:41.81#ibcon#read 3, iclass 39, count 2 2006.257.04:21:41.81#ibcon#about to read 4, iclass 39, count 2 2006.257.04:21:41.81#ibcon#read 4, iclass 39, count 2 2006.257.04:21:41.81#ibcon#about to read 5, iclass 39, count 2 2006.257.04:21:41.81#ibcon#read 5, iclass 39, count 2 2006.257.04:21:41.81#ibcon#about to read 6, iclass 39, count 2 2006.257.04:21:41.81#ibcon#read 6, iclass 39, count 2 2006.257.04:21:41.81#ibcon#end of sib2, iclass 39, count 2 2006.257.04:21:41.81#ibcon#*after write, iclass 39, count 2 2006.257.04:21:41.81#ibcon#*before return 0, iclass 39, count 2 2006.257.04:21:41.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:41.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:21:41.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.04:21:41.81#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:41.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:41.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:41.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:41.93#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:21:41.93#ibcon#first serial, iclass 39, count 0 2006.257.04:21:41.93#ibcon#enter sib2, iclass 39, count 0 2006.257.04:21:41.93#ibcon#flushed, iclass 39, count 0 2006.257.04:21:41.93#ibcon#about to write, iclass 39, count 0 2006.257.04:21:41.93#ibcon#wrote, iclass 39, count 0 2006.257.04:21:41.93#ibcon#about to read 3, iclass 39, count 0 2006.257.04:21:41.95#ibcon#read 3, iclass 39, count 0 2006.257.04:21:41.95#ibcon#about to read 4, iclass 39, count 0 2006.257.04:21:41.95#ibcon#read 4, iclass 39, count 0 2006.257.04:21:41.95#ibcon#about to read 5, iclass 39, count 0 2006.257.04:21:41.95#ibcon#read 5, iclass 39, count 0 2006.257.04:21:41.95#ibcon#about to read 6, iclass 39, count 0 2006.257.04:21:41.95#ibcon#read 6, iclass 39, count 0 2006.257.04:21:41.95#ibcon#end of sib2, iclass 39, count 0 2006.257.04:21:41.95#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:21:41.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:21:41.95#ibcon#[27=USB\r\n] 2006.257.04:21:41.95#ibcon#*before write, iclass 39, count 0 2006.257.04:21:41.95#ibcon#enter sib2, iclass 39, count 0 2006.257.04:21:41.95#ibcon#flushed, iclass 39, count 0 2006.257.04:21:41.95#ibcon#about to write, iclass 39, count 0 2006.257.04:21:41.95#ibcon#wrote, iclass 39, count 0 2006.257.04:21:41.95#ibcon#about to read 3, iclass 39, count 0 2006.257.04:21:41.98#ibcon#read 3, iclass 39, count 0 2006.257.04:21:41.98#ibcon#about to read 4, iclass 39, count 0 2006.257.04:21:41.98#ibcon#read 4, iclass 39, count 0 2006.257.04:21:41.98#ibcon#about to read 5, iclass 39, count 0 2006.257.04:21:41.98#ibcon#read 5, iclass 39, count 0 2006.257.04:21:41.98#ibcon#about to read 6, iclass 39, count 0 2006.257.04:21:41.98#ibcon#read 6, iclass 39, count 0 2006.257.04:21:41.98#ibcon#end of sib2, iclass 39, count 0 2006.257.04:21:41.98#ibcon#*after write, iclass 39, count 0 2006.257.04:21:41.98#ibcon#*before return 0, iclass 39, count 0 2006.257.04:21:41.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:41.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:21:41.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:21:41.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:21:41.98$vck44/vblo=7,734.99 2006.257.04:21:41.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.04:21:41.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.04:21:41.98#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:41.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:41.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:41.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:41.98#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:21:41.98#ibcon#first serial, iclass 3, count 0 2006.257.04:21:41.98#ibcon#enter sib2, iclass 3, count 0 2006.257.04:21:41.98#ibcon#flushed, iclass 3, count 0 2006.257.04:21:41.98#ibcon#about to write, iclass 3, count 0 2006.257.04:21:41.98#ibcon#wrote, iclass 3, count 0 2006.257.04:21:41.98#ibcon#about to read 3, iclass 3, count 0 2006.257.04:21:42.00#ibcon#read 3, iclass 3, count 0 2006.257.04:21:42.00#ibcon#about to read 4, iclass 3, count 0 2006.257.04:21:42.00#ibcon#read 4, iclass 3, count 0 2006.257.04:21:42.00#ibcon#about to read 5, iclass 3, count 0 2006.257.04:21:42.00#ibcon#read 5, iclass 3, count 0 2006.257.04:21:42.00#ibcon#about to read 6, iclass 3, count 0 2006.257.04:21:42.00#ibcon#read 6, iclass 3, count 0 2006.257.04:21:42.00#ibcon#end of sib2, iclass 3, count 0 2006.257.04:21:42.00#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:21:42.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:21:42.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.04:21:42.00#ibcon#*before write, iclass 3, count 0 2006.257.04:21:42.00#ibcon#enter sib2, iclass 3, count 0 2006.257.04:21:42.00#ibcon#flushed, iclass 3, count 0 2006.257.04:21:42.00#ibcon#about to write, iclass 3, count 0 2006.257.04:21:42.00#ibcon#wrote, iclass 3, count 0 2006.257.04:21:42.00#ibcon#about to read 3, iclass 3, count 0 2006.257.04:21:42.04#ibcon#read 3, iclass 3, count 0 2006.257.04:21:42.04#ibcon#about to read 4, iclass 3, count 0 2006.257.04:21:42.04#ibcon#read 4, iclass 3, count 0 2006.257.04:21:42.04#ibcon#about to read 5, iclass 3, count 0 2006.257.04:21:42.04#ibcon#read 5, iclass 3, count 0 2006.257.04:21:42.04#ibcon#about to read 6, iclass 3, count 0 2006.257.04:21:42.04#ibcon#read 6, iclass 3, count 0 2006.257.04:21:42.04#ibcon#end of sib2, iclass 3, count 0 2006.257.04:21:42.04#ibcon#*after write, iclass 3, count 0 2006.257.04:21:42.04#ibcon#*before return 0, iclass 3, count 0 2006.257.04:21:42.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:42.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:21:42.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:21:42.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:21:42.04$vck44/vb=7,4 2006.257.04:21:42.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.04:21:42.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.04:21:42.04#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:42.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:42.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:42.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:42.10#ibcon#enter wrdev, iclass 5, count 2 2006.257.04:21:42.10#ibcon#first serial, iclass 5, count 2 2006.257.04:21:42.10#ibcon#enter sib2, iclass 5, count 2 2006.257.04:21:42.10#ibcon#flushed, iclass 5, count 2 2006.257.04:21:42.10#ibcon#about to write, iclass 5, count 2 2006.257.04:21:42.10#ibcon#wrote, iclass 5, count 2 2006.257.04:21:42.10#ibcon#about to read 3, iclass 5, count 2 2006.257.04:21:42.12#ibcon#read 3, iclass 5, count 2 2006.257.04:21:42.12#ibcon#about to read 4, iclass 5, count 2 2006.257.04:21:42.12#ibcon#read 4, iclass 5, count 2 2006.257.04:21:42.12#ibcon#about to read 5, iclass 5, count 2 2006.257.04:21:42.12#ibcon#read 5, iclass 5, count 2 2006.257.04:21:42.12#ibcon#about to read 6, iclass 5, count 2 2006.257.04:21:42.12#ibcon#read 6, iclass 5, count 2 2006.257.04:21:42.12#ibcon#end of sib2, iclass 5, count 2 2006.257.04:21:42.12#ibcon#*mode == 0, iclass 5, count 2 2006.257.04:21:42.12#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.04:21:42.12#ibcon#[27=AT07-04\r\n] 2006.257.04:21:42.12#ibcon#*before write, iclass 5, count 2 2006.257.04:21:42.12#ibcon#enter sib2, iclass 5, count 2 2006.257.04:21:42.12#ibcon#flushed, iclass 5, count 2 2006.257.04:21:42.12#ibcon#about to write, iclass 5, count 2 2006.257.04:21:42.12#ibcon#wrote, iclass 5, count 2 2006.257.04:21:42.12#ibcon#about to read 3, iclass 5, count 2 2006.257.04:21:42.15#ibcon#read 3, iclass 5, count 2 2006.257.04:21:42.15#ibcon#about to read 4, iclass 5, count 2 2006.257.04:21:42.15#ibcon#read 4, iclass 5, count 2 2006.257.04:21:42.15#ibcon#about to read 5, iclass 5, count 2 2006.257.04:21:42.15#ibcon#read 5, iclass 5, count 2 2006.257.04:21:42.15#ibcon#about to read 6, iclass 5, count 2 2006.257.04:21:42.15#ibcon#read 6, iclass 5, count 2 2006.257.04:21:42.15#ibcon#end of sib2, iclass 5, count 2 2006.257.04:21:42.15#ibcon#*after write, iclass 5, count 2 2006.257.04:21:42.15#ibcon#*before return 0, iclass 5, count 2 2006.257.04:21:42.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:42.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:21:42.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.04:21:42.15#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:42.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:42.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:42.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:42.27#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:21:42.27#ibcon#first serial, iclass 5, count 0 2006.257.04:21:42.27#ibcon#enter sib2, iclass 5, count 0 2006.257.04:21:42.27#ibcon#flushed, iclass 5, count 0 2006.257.04:21:42.27#ibcon#about to write, iclass 5, count 0 2006.257.04:21:42.27#ibcon#wrote, iclass 5, count 0 2006.257.04:21:42.27#ibcon#about to read 3, iclass 5, count 0 2006.257.04:21:42.29#ibcon#read 3, iclass 5, count 0 2006.257.04:21:42.29#ibcon#about to read 4, iclass 5, count 0 2006.257.04:21:42.29#ibcon#read 4, iclass 5, count 0 2006.257.04:21:42.29#ibcon#about to read 5, iclass 5, count 0 2006.257.04:21:42.29#ibcon#read 5, iclass 5, count 0 2006.257.04:21:42.29#ibcon#about to read 6, iclass 5, count 0 2006.257.04:21:42.29#ibcon#read 6, iclass 5, count 0 2006.257.04:21:42.29#ibcon#end of sib2, iclass 5, count 0 2006.257.04:21:42.29#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:21:42.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:21:42.29#ibcon#[27=USB\r\n] 2006.257.04:21:42.29#ibcon#*before write, iclass 5, count 0 2006.257.04:21:42.29#ibcon#enter sib2, iclass 5, count 0 2006.257.04:21:42.29#ibcon#flushed, iclass 5, count 0 2006.257.04:21:42.29#ibcon#about to write, iclass 5, count 0 2006.257.04:21:42.29#ibcon#wrote, iclass 5, count 0 2006.257.04:21:42.29#ibcon#about to read 3, iclass 5, count 0 2006.257.04:21:42.32#ibcon#read 3, iclass 5, count 0 2006.257.04:21:42.32#ibcon#about to read 4, iclass 5, count 0 2006.257.04:21:42.32#ibcon#read 4, iclass 5, count 0 2006.257.04:21:42.32#ibcon#about to read 5, iclass 5, count 0 2006.257.04:21:42.32#ibcon#read 5, iclass 5, count 0 2006.257.04:21:42.32#ibcon#about to read 6, iclass 5, count 0 2006.257.04:21:42.32#ibcon#read 6, iclass 5, count 0 2006.257.04:21:42.32#ibcon#end of sib2, iclass 5, count 0 2006.257.04:21:42.32#ibcon#*after write, iclass 5, count 0 2006.257.04:21:42.32#ibcon#*before return 0, iclass 5, count 0 2006.257.04:21:42.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:42.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:21:42.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:21:42.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:21:42.32$vck44/vblo=8,744.99 2006.257.04:21:42.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.04:21:42.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.04:21:42.32#ibcon#ireg 17 cls_cnt 0 2006.257.04:21:42.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:42.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:42.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:42.32#ibcon#enter wrdev, iclass 7, count 0 2006.257.04:21:42.32#ibcon#first serial, iclass 7, count 0 2006.257.04:21:42.32#ibcon#enter sib2, iclass 7, count 0 2006.257.04:21:42.32#ibcon#flushed, iclass 7, count 0 2006.257.04:21:42.32#ibcon#about to write, iclass 7, count 0 2006.257.04:21:42.32#ibcon#wrote, iclass 7, count 0 2006.257.04:21:42.32#ibcon#about to read 3, iclass 7, count 0 2006.257.04:21:42.34#ibcon#read 3, iclass 7, count 0 2006.257.04:21:42.34#ibcon#about to read 4, iclass 7, count 0 2006.257.04:21:42.34#ibcon#read 4, iclass 7, count 0 2006.257.04:21:42.34#ibcon#about to read 5, iclass 7, count 0 2006.257.04:21:42.34#ibcon#read 5, iclass 7, count 0 2006.257.04:21:42.34#ibcon#about to read 6, iclass 7, count 0 2006.257.04:21:42.34#ibcon#read 6, iclass 7, count 0 2006.257.04:21:42.34#ibcon#end of sib2, iclass 7, count 0 2006.257.04:21:42.34#ibcon#*mode == 0, iclass 7, count 0 2006.257.04:21:42.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.04:21:42.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.04:21:42.34#ibcon#*before write, iclass 7, count 0 2006.257.04:21:42.34#ibcon#enter sib2, iclass 7, count 0 2006.257.04:21:42.34#ibcon#flushed, iclass 7, count 0 2006.257.04:21:42.34#ibcon#about to write, iclass 7, count 0 2006.257.04:21:42.34#ibcon#wrote, iclass 7, count 0 2006.257.04:21:42.34#ibcon#about to read 3, iclass 7, count 0 2006.257.04:21:42.38#ibcon#read 3, iclass 7, count 0 2006.257.04:21:42.38#ibcon#about to read 4, iclass 7, count 0 2006.257.04:21:42.38#ibcon#read 4, iclass 7, count 0 2006.257.04:21:42.38#ibcon#about to read 5, iclass 7, count 0 2006.257.04:21:42.38#ibcon#read 5, iclass 7, count 0 2006.257.04:21:42.38#ibcon#about to read 6, iclass 7, count 0 2006.257.04:21:42.38#ibcon#read 6, iclass 7, count 0 2006.257.04:21:42.38#ibcon#end of sib2, iclass 7, count 0 2006.257.04:21:42.38#ibcon#*after write, iclass 7, count 0 2006.257.04:21:42.38#ibcon#*before return 0, iclass 7, count 0 2006.257.04:21:42.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:42.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:21:42.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.04:21:42.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.04:21:42.38$vck44/vb=8,4 2006.257.04:21:42.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.04:21:42.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.04:21:42.38#ibcon#ireg 11 cls_cnt 2 2006.257.04:21:42.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:42.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:42.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:42.44#ibcon#enter wrdev, iclass 11, count 2 2006.257.04:21:42.44#ibcon#first serial, iclass 11, count 2 2006.257.04:21:42.44#ibcon#enter sib2, iclass 11, count 2 2006.257.04:21:42.44#ibcon#flushed, iclass 11, count 2 2006.257.04:21:42.44#ibcon#about to write, iclass 11, count 2 2006.257.04:21:42.44#ibcon#wrote, iclass 11, count 2 2006.257.04:21:42.44#ibcon#about to read 3, iclass 11, count 2 2006.257.04:21:42.46#ibcon#read 3, iclass 11, count 2 2006.257.04:21:42.46#ibcon#about to read 4, iclass 11, count 2 2006.257.04:21:42.46#ibcon#read 4, iclass 11, count 2 2006.257.04:21:42.46#ibcon#about to read 5, iclass 11, count 2 2006.257.04:21:42.46#ibcon#read 5, iclass 11, count 2 2006.257.04:21:42.46#ibcon#about to read 6, iclass 11, count 2 2006.257.04:21:42.46#ibcon#read 6, iclass 11, count 2 2006.257.04:21:42.46#ibcon#end of sib2, iclass 11, count 2 2006.257.04:21:42.46#ibcon#*mode == 0, iclass 11, count 2 2006.257.04:21:42.46#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.04:21:42.46#ibcon#[27=AT08-04\r\n] 2006.257.04:21:42.46#ibcon#*before write, iclass 11, count 2 2006.257.04:21:42.46#ibcon#enter sib2, iclass 11, count 2 2006.257.04:21:42.46#ibcon#flushed, iclass 11, count 2 2006.257.04:21:42.46#ibcon#about to write, iclass 11, count 2 2006.257.04:21:42.46#ibcon#wrote, iclass 11, count 2 2006.257.04:21:42.46#ibcon#about to read 3, iclass 11, count 2 2006.257.04:21:42.49#ibcon#read 3, iclass 11, count 2 2006.257.04:21:42.49#ibcon#about to read 4, iclass 11, count 2 2006.257.04:21:42.49#ibcon#read 4, iclass 11, count 2 2006.257.04:21:42.49#ibcon#about to read 5, iclass 11, count 2 2006.257.04:21:42.49#ibcon#read 5, iclass 11, count 2 2006.257.04:21:42.49#ibcon#about to read 6, iclass 11, count 2 2006.257.04:21:42.49#ibcon#read 6, iclass 11, count 2 2006.257.04:21:42.49#ibcon#end of sib2, iclass 11, count 2 2006.257.04:21:42.49#ibcon#*after write, iclass 11, count 2 2006.257.04:21:42.49#ibcon#*before return 0, iclass 11, count 2 2006.257.04:21:42.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:42.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:21:42.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.04:21:42.49#ibcon#ireg 7 cls_cnt 0 2006.257.04:21:42.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:42.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:42.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:42.61#ibcon#enter wrdev, iclass 11, count 0 2006.257.04:21:42.61#ibcon#first serial, iclass 11, count 0 2006.257.04:21:42.61#ibcon#enter sib2, iclass 11, count 0 2006.257.04:21:42.61#ibcon#flushed, iclass 11, count 0 2006.257.04:21:42.61#ibcon#about to write, iclass 11, count 0 2006.257.04:21:42.61#ibcon#wrote, iclass 11, count 0 2006.257.04:21:42.61#ibcon#about to read 3, iclass 11, count 0 2006.257.04:21:42.63#ibcon#read 3, iclass 11, count 0 2006.257.04:21:42.63#ibcon#about to read 4, iclass 11, count 0 2006.257.04:21:42.63#ibcon#read 4, iclass 11, count 0 2006.257.04:21:42.63#ibcon#about to read 5, iclass 11, count 0 2006.257.04:21:42.63#ibcon#read 5, iclass 11, count 0 2006.257.04:21:42.63#ibcon#about to read 6, iclass 11, count 0 2006.257.04:21:42.63#ibcon#read 6, iclass 11, count 0 2006.257.04:21:42.63#ibcon#end of sib2, iclass 11, count 0 2006.257.04:21:42.63#ibcon#*mode == 0, iclass 11, count 0 2006.257.04:21:42.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.04:21:42.63#ibcon#[27=USB\r\n] 2006.257.04:21:42.63#ibcon#*before write, iclass 11, count 0 2006.257.04:21:42.63#ibcon#enter sib2, iclass 11, count 0 2006.257.04:21:42.63#ibcon#flushed, iclass 11, count 0 2006.257.04:21:42.63#ibcon#about to write, iclass 11, count 0 2006.257.04:21:42.63#ibcon#wrote, iclass 11, count 0 2006.257.04:21:42.63#ibcon#about to read 3, iclass 11, count 0 2006.257.04:21:42.66#ibcon#read 3, iclass 11, count 0 2006.257.04:21:42.66#ibcon#about to read 4, iclass 11, count 0 2006.257.04:21:42.66#ibcon#read 4, iclass 11, count 0 2006.257.04:21:42.66#ibcon#about to read 5, iclass 11, count 0 2006.257.04:21:42.66#ibcon#read 5, iclass 11, count 0 2006.257.04:21:42.66#ibcon#about to read 6, iclass 11, count 0 2006.257.04:21:42.66#ibcon#read 6, iclass 11, count 0 2006.257.04:21:42.66#ibcon#end of sib2, iclass 11, count 0 2006.257.04:21:42.66#ibcon#*after write, iclass 11, count 0 2006.257.04:21:42.66#ibcon#*before return 0, iclass 11, count 0 2006.257.04:21:42.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:42.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:21:42.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.04:21:42.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.04:21:42.66$vck44/vabw=wide 2006.257.04:21:42.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.04:21:42.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.04:21:42.66#ibcon#ireg 8 cls_cnt 0 2006.257.04:21:42.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:42.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:42.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:42.66#ibcon#enter wrdev, iclass 13, count 0 2006.257.04:21:42.66#ibcon#first serial, iclass 13, count 0 2006.257.04:21:42.66#ibcon#enter sib2, iclass 13, count 0 2006.257.04:21:42.66#ibcon#flushed, iclass 13, count 0 2006.257.04:21:42.66#ibcon#about to write, iclass 13, count 0 2006.257.04:21:42.66#ibcon#wrote, iclass 13, count 0 2006.257.04:21:42.66#ibcon#about to read 3, iclass 13, count 0 2006.257.04:21:42.68#ibcon#read 3, iclass 13, count 0 2006.257.04:21:42.68#ibcon#about to read 4, iclass 13, count 0 2006.257.04:21:42.68#ibcon#read 4, iclass 13, count 0 2006.257.04:21:42.68#ibcon#about to read 5, iclass 13, count 0 2006.257.04:21:42.68#ibcon#read 5, iclass 13, count 0 2006.257.04:21:42.68#ibcon#about to read 6, iclass 13, count 0 2006.257.04:21:42.68#ibcon#read 6, iclass 13, count 0 2006.257.04:21:42.68#ibcon#end of sib2, iclass 13, count 0 2006.257.04:21:42.68#ibcon#*mode == 0, iclass 13, count 0 2006.257.04:21:42.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.04:21:42.68#ibcon#[25=BW32\r\n] 2006.257.04:21:42.68#ibcon#*before write, iclass 13, count 0 2006.257.04:21:42.68#ibcon#enter sib2, iclass 13, count 0 2006.257.04:21:42.68#ibcon#flushed, iclass 13, count 0 2006.257.04:21:42.68#ibcon#about to write, iclass 13, count 0 2006.257.04:21:42.68#ibcon#wrote, iclass 13, count 0 2006.257.04:21:42.68#ibcon#about to read 3, iclass 13, count 0 2006.257.04:21:42.71#ibcon#read 3, iclass 13, count 0 2006.257.04:21:42.71#ibcon#about to read 4, iclass 13, count 0 2006.257.04:21:42.71#ibcon#read 4, iclass 13, count 0 2006.257.04:21:42.71#ibcon#about to read 5, iclass 13, count 0 2006.257.04:21:42.71#ibcon#read 5, iclass 13, count 0 2006.257.04:21:42.71#ibcon#about to read 6, iclass 13, count 0 2006.257.04:21:42.71#ibcon#read 6, iclass 13, count 0 2006.257.04:21:42.71#ibcon#end of sib2, iclass 13, count 0 2006.257.04:21:42.71#ibcon#*after write, iclass 13, count 0 2006.257.04:21:42.71#ibcon#*before return 0, iclass 13, count 0 2006.257.04:21:42.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:42.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:21:42.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.04:21:42.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.04:21:42.71$vck44/vbbw=wide 2006.257.04:21:42.71#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.04:21:42.71#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.04:21:42.71#ibcon#ireg 8 cls_cnt 0 2006.257.04:21:42.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:21:42.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:21:42.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:21:42.78#ibcon#enter wrdev, iclass 15, count 0 2006.257.04:21:42.78#ibcon#first serial, iclass 15, count 0 2006.257.04:21:42.78#ibcon#enter sib2, iclass 15, count 0 2006.257.04:21:42.78#ibcon#flushed, iclass 15, count 0 2006.257.04:21:42.78#ibcon#about to write, iclass 15, count 0 2006.257.04:21:42.78#ibcon#wrote, iclass 15, count 0 2006.257.04:21:42.78#ibcon#about to read 3, iclass 15, count 0 2006.257.04:21:42.80#ibcon#read 3, iclass 15, count 0 2006.257.04:21:42.80#ibcon#about to read 4, iclass 15, count 0 2006.257.04:21:42.80#ibcon#read 4, iclass 15, count 0 2006.257.04:21:42.80#ibcon#about to read 5, iclass 15, count 0 2006.257.04:21:42.80#ibcon#read 5, iclass 15, count 0 2006.257.04:21:42.80#ibcon#about to read 6, iclass 15, count 0 2006.257.04:21:42.80#ibcon#read 6, iclass 15, count 0 2006.257.04:21:42.80#ibcon#end of sib2, iclass 15, count 0 2006.257.04:21:42.80#ibcon#*mode == 0, iclass 15, count 0 2006.257.04:21:42.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.04:21:42.80#ibcon#[27=BW32\r\n] 2006.257.04:21:42.80#ibcon#*before write, iclass 15, count 0 2006.257.04:21:42.80#ibcon#enter sib2, iclass 15, count 0 2006.257.04:21:42.80#ibcon#flushed, iclass 15, count 0 2006.257.04:21:42.80#ibcon#about to write, iclass 15, count 0 2006.257.04:21:42.80#ibcon#wrote, iclass 15, count 0 2006.257.04:21:42.80#ibcon#about to read 3, iclass 15, count 0 2006.257.04:21:42.83#ibcon#read 3, iclass 15, count 0 2006.257.04:21:42.83#ibcon#about to read 4, iclass 15, count 0 2006.257.04:21:42.83#ibcon#read 4, iclass 15, count 0 2006.257.04:21:42.83#ibcon#about to read 5, iclass 15, count 0 2006.257.04:21:42.83#ibcon#read 5, iclass 15, count 0 2006.257.04:21:42.83#ibcon#about to read 6, iclass 15, count 0 2006.257.04:21:42.83#ibcon#read 6, iclass 15, count 0 2006.257.04:21:42.83#ibcon#end of sib2, iclass 15, count 0 2006.257.04:21:42.83#ibcon#*after write, iclass 15, count 0 2006.257.04:21:42.83#ibcon#*before return 0, iclass 15, count 0 2006.257.04:21:42.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:21:42.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:21:42.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.04:21:42.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.04:21:42.83$setupk4/ifdk4 2006.257.04:21:42.83$ifdk4/lo= 2006.257.04:21:42.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.04:21:42.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.04:21:42.83$ifdk4/patch= 2006.257.04:21:42.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.04:21:42.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.04:21:42.83$setupk4/!*+20s 2006.257.04:21:45.72#abcon#<5=/14 1.6 4.5 19.55 941011.8\r\n> 2006.257.04:21:45.74#abcon#{5=INTERFACE CLEAR} 2006.257.04:21:45.80#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:21:53.14#trakl#Source acquired 2006.257.04:21:53.14#flagr#flagr/antenna,acquired 2006.257.04:21:55.89#abcon#<5=/14 1.6 4.5 19.55 941011.9\r\n> 2006.257.04:21:55.91#abcon#{5=INTERFACE CLEAR} 2006.257.04:21:55.97#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:21:57.34$setupk4/"tpicd 2006.257.04:21:57.34$setupk4/echo=off 2006.257.04:21:57.34$setupk4/xlog=off 2006.257.04:21:57.34:!2006.257.04:25:33 2006.257.04:22:47.14#trakl#Off source 2006.257.04:22:47.14?ERROR st -7 Antenna off-source! 2006.257.04:22:47.14#trakl#az 312.855 el 9.671 azerr*cos(el) 0.0196 elerr 0.0024 2006.257.04:22:47.14#flagr#flagr/antenna,off-source 2006.257.04:22:53.14#trakl#Source re-acquired 2006.257.04:22:53.14#flagr#flagr/antenna,re-acquired 2006.257.04:25:33.00:preob 2006.257.04:25:33.14/onsource/TRACKING 2006.257.04:25:33.14:!2006.257.04:25:43 2006.257.04:25:43.00:"tape 2006.257.04:25:43.00:"st=record 2006.257.04:25:43.00:data_valid=on 2006.257.04:25:43.00:midob 2006.257.04:25:44.13/onsource/TRACKING 2006.257.04:25:44.13/wx/19.53,1011.9,93 2006.257.04:25:44.19/cable/+6.4842E-03 2006.257.04:25:45.28/va/01,08,usb,yes,45,48 2006.257.04:25:45.28/va/02,07,usb,yes,48,49 2006.257.04:25:45.28/va/03,08,usb,yes,44,46 2006.257.04:25:45.28/va/04,07,usb,yes,50,53 2006.257.04:25:45.28/va/05,04,usb,yes,45,46 2006.257.04:25:45.28/va/06,04,usb,yes,50,49 2006.257.04:25:45.28/va/07,04,usb,yes,51,51 2006.257.04:25:45.28/va/08,04,usb,yes,43,51 2006.257.04:25:45.51/valo/01,524.99,yes,locked 2006.257.04:25:45.51/valo/02,534.99,yes,locked 2006.257.04:25:45.51/valo/03,564.99,yes,locked 2006.257.04:25:45.51/valo/04,624.99,yes,locked 2006.257.04:25:45.51/valo/05,734.99,yes,locked 2006.257.04:25:45.51/valo/06,814.99,yes,locked 2006.257.04:25:45.51/valo/07,864.99,yes,locked 2006.257.04:25:45.51/valo/08,884.99,yes,locked 2006.257.04:25:46.60/vb/01,04,usb,yes,44,40 2006.257.04:25:46.60/vb/02,05,usb,yes,41,41 2006.257.04:25:46.60/vb/03,04,usb,yes,43,47 2006.257.04:25:46.60/vb/04,05,usb,yes,43,42 2006.257.04:25:46.60/vb/05,04,usb,yes,39,42 2006.257.04:25:46.60/vb/06,04,usb,yes,45,40 2006.257.04:25:46.60/vb/07,04,usb,yes,44,44 2006.257.04:25:46.60/vb/08,04,usb,yes,40,45 2006.257.04:25:46.83/vblo/01,629.99,yes,locked 2006.257.04:25:46.83/vblo/02,634.99,yes,locked 2006.257.04:25:46.83/vblo/03,649.99,yes,locked 2006.257.04:25:46.83/vblo/04,679.99,yes,locked 2006.257.04:25:46.83/vblo/05,709.99,yes,locked 2006.257.04:25:46.83/vblo/06,719.99,yes,locked 2006.257.04:25:46.83/vblo/07,734.99,yes,locked 2006.257.04:25:46.83/vblo/08,744.99,yes,locked 2006.257.04:25:46.98/vabw/8 2006.257.04:25:47.13/vbbw/8 2006.257.04:25:47.22/xfe/off,on,16.7 2006.257.04:25:47.59/ifatt/23,28,28,28 2006.257.04:25:48.07/fmout-gps/S +4.55E-07 2006.257.04:25:48.11:!2006.257.04:27:13 2006.257.04:27:13.01:data_valid=off 2006.257.04:27:13.01:"et 2006.257.04:27:13.02:!+3s 2006.257.04:27:16.04:"tape 2006.257.04:27:16.04:postob 2006.257.04:27:16.12/cable/+6.4841E-03 2006.257.04:27:16.12/wx/19.51,1011.9,93 2006.257.04:27:16.18/fmout-gps/S +4.54E-07 2006.257.04:27:16.18:scan_name=257-0431,jd0609,40 2006.257.04:27:16.18:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.257.04:27:17.13#flagr#flagr/antenna,new-source 2006.257.04:27:17.13:checkk5 2006.257.04:27:17.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.04:27:17.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.04:27:18.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.04:27:18.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.04:27:19.12/chk_obsdata//k5ts1/T2570425??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.04:27:19.51/chk_obsdata//k5ts2/T2570425??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.04:27:19.91/chk_obsdata//k5ts3/T2570425??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.04:27:20.30/chk_obsdata//k5ts4/T2570425??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.04:27:21.02/k5log//k5ts1_log_newline 2006.257.04:27:21.75/k5log//k5ts2_log_newline 2006.257.04:27:22.51/k5log//k5ts3_log_newline 2006.257.04:27:23.23/k5log//k5ts4_log_newline 2006.257.04:27:23.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.04:27:23.25:setupk4=1 2006.257.04:27:23.25$setupk4/echo=on 2006.257.04:27:23.25$setupk4/pcalon 2006.257.04:27:23.25$pcalon/"no phase cal control is implemented here 2006.257.04:27:23.25$setupk4/"tpicd=stop 2006.257.04:27:23.25$setupk4/"rec=synch_on 2006.257.04:27:23.25$setupk4/"rec_mode=128 2006.257.04:27:23.25$setupk4/!* 2006.257.04:27:23.25$setupk4/recpk4 2006.257.04:27:23.25$recpk4/recpatch= 2006.257.04:27:23.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.04:27:23.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.04:27:23.25$setupk4/vck44 2006.257.04:27:23.25$vck44/valo=1,524.99 2006.257.04:27:23.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.04:27:23.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.04:27:23.25#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:23.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:23.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:23.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:23.25#ibcon#enter wrdev, iclass 14, count 0 2006.257.04:27:23.25#ibcon#first serial, iclass 14, count 0 2006.257.04:27:23.25#ibcon#enter sib2, iclass 14, count 0 2006.257.04:27:23.25#ibcon#flushed, iclass 14, count 0 2006.257.04:27:23.25#ibcon#about to write, iclass 14, count 0 2006.257.04:27:23.25#ibcon#wrote, iclass 14, count 0 2006.257.04:27:23.25#ibcon#about to read 3, iclass 14, count 0 2006.257.04:27:23.27#ibcon#read 3, iclass 14, count 0 2006.257.04:27:23.27#ibcon#about to read 4, iclass 14, count 0 2006.257.04:27:23.27#ibcon#read 4, iclass 14, count 0 2006.257.04:27:23.27#ibcon#about to read 5, iclass 14, count 0 2006.257.04:27:23.27#ibcon#read 5, iclass 14, count 0 2006.257.04:27:23.27#ibcon#about to read 6, iclass 14, count 0 2006.257.04:27:23.27#ibcon#read 6, iclass 14, count 0 2006.257.04:27:23.27#ibcon#end of sib2, iclass 14, count 0 2006.257.04:27:23.27#ibcon#*mode == 0, iclass 14, count 0 2006.257.04:27:23.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.04:27:23.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.04:27:23.27#ibcon#*before write, iclass 14, count 0 2006.257.04:27:23.27#ibcon#enter sib2, iclass 14, count 0 2006.257.04:27:23.27#ibcon#flushed, iclass 14, count 0 2006.257.04:27:23.27#ibcon#about to write, iclass 14, count 0 2006.257.04:27:23.27#ibcon#wrote, iclass 14, count 0 2006.257.04:27:23.27#ibcon#about to read 3, iclass 14, count 0 2006.257.04:27:23.32#ibcon#read 3, iclass 14, count 0 2006.257.04:27:23.32#ibcon#about to read 4, iclass 14, count 0 2006.257.04:27:23.32#ibcon#read 4, iclass 14, count 0 2006.257.04:27:23.32#ibcon#about to read 5, iclass 14, count 0 2006.257.04:27:23.32#ibcon#read 5, iclass 14, count 0 2006.257.04:27:23.32#ibcon#about to read 6, iclass 14, count 0 2006.257.04:27:23.32#ibcon#read 6, iclass 14, count 0 2006.257.04:27:23.32#ibcon#end of sib2, iclass 14, count 0 2006.257.04:27:23.32#ibcon#*after write, iclass 14, count 0 2006.257.04:27:23.32#ibcon#*before return 0, iclass 14, count 0 2006.257.04:27:23.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:23.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:23.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.04:27:23.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.04:27:23.32$vck44/va=1,8 2006.257.04:27:23.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.04:27:23.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.04:27:23.32#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:23.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:23.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:23.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:23.32#ibcon#enter wrdev, iclass 16, count 2 2006.257.04:27:23.32#ibcon#first serial, iclass 16, count 2 2006.257.04:27:23.32#ibcon#enter sib2, iclass 16, count 2 2006.257.04:27:23.32#ibcon#flushed, iclass 16, count 2 2006.257.04:27:23.32#ibcon#about to write, iclass 16, count 2 2006.257.04:27:23.32#ibcon#wrote, iclass 16, count 2 2006.257.04:27:23.32#ibcon#about to read 3, iclass 16, count 2 2006.257.04:27:23.34#ibcon#read 3, iclass 16, count 2 2006.257.04:27:23.34#ibcon#about to read 4, iclass 16, count 2 2006.257.04:27:23.34#ibcon#read 4, iclass 16, count 2 2006.257.04:27:23.34#ibcon#about to read 5, iclass 16, count 2 2006.257.04:27:23.34#ibcon#read 5, iclass 16, count 2 2006.257.04:27:23.34#ibcon#about to read 6, iclass 16, count 2 2006.257.04:27:23.34#ibcon#read 6, iclass 16, count 2 2006.257.04:27:23.34#ibcon#end of sib2, iclass 16, count 2 2006.257.04:27:23.34#ibcon#*mode == 0, iclass 16, count 2 2006.257.04:27:23.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.04:27:23.34#ibcon#[25=AT01-08\r\n] 2006.257.04:27:23.34#ibcon#*before write, iclass 16, count 2 2006.257.04:27:23.34#ibcon#enter sib2, iclass 16, count 2 2006.257.04:27:23.34#ibcon#flushed, iclass 16, count 2 2006.257.04:27:23.34#ibcon#about to write, iclass 16, count 2 2006.257.04:27:23.34#ibcon#wrote, iclass 16, count 2 2006.257.04:27:23.34#ibcon#about to read 3, iclass 16, count 2 2006.257.04:27:23.37#ibcon#read 3, iclass 16, count 2 2006.257.04:27:23.37#ibcon#about to read 4, iclass 16, count 2 2006.257.04:27:23.37#ibcon#read 4, iclass 16, count 2 2006.257.04:27:23.37#ibcon#about to read 5, iclass 16, count 2 2006.257.04:27:23.37#ibcon#read 5, iclass 16, count 2 2006.257.04:27:23.37#ibcon#about to read 6, iclass 16, count 2 2006.257.04:27:23.37#ibcon#read 6, iclass 16, count 2 2006.257.04:27:23.37#ibcon#end of sib2, iclass 16, count 2 2006.257.04:27:23.37#ibcon#*after write, iclass 16, count 2 2006.257.04:27:23.37#ibcon#*before return 0, iclass 16, count 2 2006.257.04:27:23.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:23.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:23.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.04:27:23.37#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:23.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:23.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:23.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:23.49#ibcon#enter wrdev, iclass 16, count 0 2006.257.04:27:23.49#ibcon#first serial, iclass 16, count 0 2006.257.04:27:23.49#ibcon#enter sib2, iclass 16, count 0 2006.257.04:27:23.49#ibcon#flushed, iclass 16, count 0 2006.257.04:27:23.49#ibcon#about to write, iclass 16, count 0 2006.257.04:27:23.49#ibcon#wrote, iclass 16, count 0 2006.257.04:27:23.49#ibcon#about to read 3, iclass 16, count 0 2006.257.04:27:23.51#ibcon#read 3, iclass 16, count 0 2006.257.04:27:23.51#ibcon#about to read 4, iclass 16, count 0 2006.257.04:27:23.51#ibcon#read 4, iclass 16, count 0 2006.257.04:27:23.51#ibcon#about to read 5, iclass 16, count 0 2006.257.04:27:23.51#ibcon#read 5, iclass 16, count 0 2006.257.04:27:23.51#ibcon#about to read 6, iclass 16, count 0 2006.257.04:27:23.51#ibcon#read 6, iclass 16, count 0 2006.257.04:27:23.51#ibcon#end of sib2, iclass 16, count 0 2006.257.04:27:23.51#ibcon#*mode == 0, iclass 16, count 0 2006.257.04:27:23.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.04:27:23.51#ibcon#[25=USB\r\n] 2006.257.04:27:23.51#ibcon#*before write, iclass 16, count 0 2006.257.04:27:23.51#ibcon#enter sib2, iclass 16, count 0 2006.257.04:27:23.51#ibcon#flushed, iclass 16, count 0 2006.257.04:27:23.51#ibcon#about to write, iclass 16, count 0 2006.257.04:27:23.51#ibcon#wrote, iclass 16, count 0 2006.257.04:27:23.51#ibcon#about to read 3, iclass 16, count 0 2006.257.04:27:23.54#ibcon#read 3, iclass 16, count 0 2006.257.04:27:23.54#ibcon#about to read 4, iclass 16, count 0 2006.257.04:27:23.54#ibcon#read 4, iclass 16, count 0 2006.257.04:27:23.54#ibcon#about to read 5, iclass 16, count 0 2006.257.04:27:23.54#ibcon#read 5, iclass 16, count 0 2006.257.04:27:23.54#ibcon#about to read 6, iclass 16, count 0 2006.257.04:27:23.54#ibcon#read 6, iclass 16, count 0 2006.257.04:27:23.54#ibcon#end of sib2, iclass 16, count 0 2006.257.04:27:23.54#ibcon#*after write, iclass 16, count 0 2006.257.04:27:23.54#ibcon#*before return 0, iclass 16, count 0 2006.257.04:27:23.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:23.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:23.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.04:27:23.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.04:27:23.54$vck44/valo=2,534.99 2006.257.04:27:23.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.04:27:23.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.04:27:23.54#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:23.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:23.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:23.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:23.54#ibcon#enter wrdev, iclass 18, count 0 2006.257.04:27:23.54#ibcon#first serial, iclass 18, count 0 2006.257.04:27:23.54#ibcon#enter sib2, iclass 18, count 0 2006.257.04:27:23.54#ibcon#flushed, iclass 18, count 0 2006.257.04:27:23.54#ibcon#about to write, iclass 18, count 0 2006.257.04:27:23.54#ibcon#wrote, iclass 18, count 0 2006.257.04:27:23.54#ibcon#about to read 3, iclass 18, count 0 2006.257.04:27:23.56#ibcon#read 3, iclass 18, count 0 2006.257.04:27:23.56#ibcon#about to read 4, iclass 18, count 0 2006.257.04:27:23.56#ibcon#read 4, iclass 18, count 0 2006.257.04:27:23.56#ibcon#about to read 5, iclass 18, count 0 2006.257.04:27:23.56#ibcon#read 5, iclass 18, count 0 2006.257.04:27:23.56#ibcon#about to read 6, iclass 18, count 0 2006.257.04:27:23.56#ibcon#read 6, iclass 18, count 0 2006.257.04:27:23.56#ibcon#end of sib2, iclass 18, count 0 2006.257.04:27:23.56#ibcon#*mode == 0, iclass 18, count 0 2006.257.04:27:23.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.04:27:23.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.04:27:23.56#ibcon#*before write, iclass 18, count 0 2006.257.04:27:23.56#ibcon#enter sib2, iclass 18, count 0 2006.257.04:27:23.56#ibcon#flushed, iclass 18, count 0 2006.257.04:27:23.56#ibcon#about to write, iclass 18, count 0 2006.257.04:27:23.56#ibcon#wrote, iclass 18, count 0 2006.257.04:27:23.56#ibcon#about to read 3, iclass 18, count 0 2006.257.04:27:23.60#ibcon#read 3, iclass 18, count 0 2006.257.04:27:23.60#ibcon#about to read 4, iclass 18, count 0 2006.257.04:27:23.60#ibcon#read 4, iclass 18, count 0 2006.257.04:27:23.60#ibcon#about to read 5, iclass 18, count 0 2006.257.04:27:23.60#ibcon#read 5, iclass 18, count 0 2006.257.04:27:23.60#ibcon#about to read 6, iclass 18, count 0 2006.257.04:27:23.60#ibcon#read 6, iclass 18, count 0 2006.257.04:27:23.60#ibcon#end of sib2, iclass 18, count 0 2006.257.04:27:23.60#ibcon#*after write, iclass 18, count 0 2006.257.04:27:23.60#ibcon#*before return 0, iclass 18, count 0 2006.257.04:27:23.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:23.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:23.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.04:27:23.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.04:27:23.60$vck44/va=2,7 2006.257.04:27:23.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.04:27:23.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.04:27:23.60#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:23.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:23.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:23.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:23.66#ibcon#enter wrdev, iclass 20, count 2 2006.257.04:27:23.66#ibcon#first serial, iclass 20, count 2 2006.257.04:27:23.66#ibcon#enter sib2, iclass 20, count 2 2006.257.04:27:23.66#ibcon#flushed, iclass 20, count 2 2006.257.04:27:23.66#ibcon#about to write, iclass 20, count 2 2006.257.04:27:23.66#ibcon#wrote, iclass 20, count 2 2006.257.04:27:23.66#ibcon#about to read 3, iclass 20, count 2 2006.257.04:27:23.68#ibcon#read 3, iclass 20, count 2 2006.257.04:27:23.68#ibcon#about to read 4, iclass 20, count 2 2006.257.04:27:23.68#ibcon#read 4, iclass 20, count 2 2006.257.04:27:23.68#ibcon#about to read 5, iclass 20, count 2 2006.257.04:27:23.68#ibcon#read 5, iclass 20, count 2 2006.257.04:27:23.68#ibcon#about to read 6, iclass 20, count 2 2006.257.04:27:23.68#ibcon#read 6, iclass 20, count 2 2006.257.04:27:23.68#ibcon#end of sib2, iclass 20, count 2 2006.257.04:27:23.68#ibcon#*mode == 0, iclass 20, count 2 2006.257.04:27:23.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.04:27:23.68#ibcon#[25=AT02-07\r\n] 2006.257.04:27:23.68#ibcon#*before write, iclass 20, count 2 2006.257.04:27:23.68#ibcon#enter sib2, iclass 20, count 2 2006.257.04:27:23.68#ibcon#flushed, iclass 20, count 2 2006.257.04:27:23.68#ibcon#about to write, iclass 20, count 2 2006.257.04:27:23.68#ibcon#wrote, iclass 20, count 2 2006.257.04:27:23.68#ibcon#about to read 3, iclass 20, count 2 2006.257.04:27:23.71#ibcon#read 3, iclass 20, count 2 2006.257.04:27:23.71#ibcon#about to read 4, iclass 20, count 2 2006.257.04:27:23.71#ibcon#read 4, iclass 20, count 2 2006.257.04:27:23.71#ibcon#about to read 5, iclass 20, count 2 2006.257.04:27:23.71#ibcon#read 5, iclass 20, count 2 2006.257.04:27:23.71#ibcon#about to read 6, iclass 20, count 2 2006.257.04:27:23.71#ibcon#read 6, iclass 20, count 2 2006.257.04:27:23.71#ibcon#end of sib2, iclass 20, count 2 2006.257.04:27:23.71#ibcon#*after write, iclass 20, count 2 2006.257.04:27:23.71#ibcon#*before return 0, iclass 20, count 2 2006.257.04:27:23.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:23.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:23.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.04:27:23.71#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:23.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:23.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:23.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:23.83#ibcon#enter wrdev, iclass 20, count 0 2006.257.04:27:23.83#ibcon#first serial, iclass 20, count 0 2006.257.04:27:23.83#ibcon#enter sib2, iclass 20, count 0 2006.257.04:27:23.83#ibcon#flushed, iclass 20, count 0 2006.257.04:27:23.83#ibcon#about to write, iclass 20, count 0 2006.257.04:27:23.83#ibcon#wrote, iclass 20, count 0 2006.257.04:27:23.83#ibcon#about to read 3, iclass 20, count 0 2006.257.04:27:23.85#ibcon#read 3, iclass 20, count 0 2006.257.04:27:23.85#ibcon#about to read 4, iclass 20, count 0 2006.257.04:27:23.85#ibcon#read 4, iclass 20, count 0 2006.257.04:27:23.85#ibcon#about to read 5, iclass 20, count 0 2006.257.04:27:23.85#ibcon#read 5, iclass 20, count 0 2006.257.04:27:23.85#ibcon#about to read 6, iclass 20, count 0 2006.257.04:27:23.85#ibcon#read 6, iclass 20, count 0 2006.257.04:27:23.85#ibcon#end of sib2, iclass 20, count 0 2006.257.04:27:23.85#ibcon#*mode == 0, iclass 20, count 0 2006.257.04:27:23.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.04:27:23.85#ibcon#[25=USB\r\n] 2006.257.04:27:23.85#ibcon#*before write, iclass 20, count 0 2006.257.04:27:23.85#ibcon#enter sib2, iclass 20, count 0 2006.257.04:27:23.85#ibcon#flushed, iclass 20, count 0 2006.257.04:27:23.85#ibcon#about to write, iclass 20, count 0 2006.257.04:27:23.85#ibcon#wrote, iclass 20, count 0 2006.257.04:27:23.85#ibcon#about to read 3, iclass 20, count 0 2006.257.04:27:23.88#ibcon#read 3, iclass 20, count 0 2006.257.04:27:23.88#ibcon#about to read 4, iclass 20, count 0 2006.257.04:27:23.88#ibcon#read 4, iclass 20, count 0 2006.257.04:27:23.88#ibcon#about to read 5, iclass 20, count 0 2006.257.04:27:23.88#ibcon#read 5, iclass 20, count 0 2006.257.04:27:23.88#ibcon#about to read 6, iclass 20, count 0 2006.257.04:27:23.88#ibcon#read 6, iclass 20, count 0 2006.257.04:27:23.88#ibcon#end of sib2, iclass 20, count 0 2006.257.04:27:23.88#ibcon#*after write, iclass 20, count 0 2006.257.04:27:23.88#ibcon#*before return 0, iclass 20, count 0 2006.257.04:27:23.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:23.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:23.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.04:27:23.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.04:27:23.88$vck44/valo=3,564.99 2006.257.04:27:23.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.04:27:23.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.04:27:23.88#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:23.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:23.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:23.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:23.88#ibcon#enter wrdev, iclass 22, count 0 2006.257.04:27:23.88#ibcon#first serial, iclass 22, count 0 2006.257.04:27:23.88#ibcon#enter sib2, iclass 22, count 0 2006.257.04:27:23.88#ibcon#flushed, iclass 22, count 0 2006.257.04:27:23.88#ibcon#about to write, iclass 22, count 0 2006.257.04:27:23.88#ibcon#wrote, iclass 22, count 0 2006.257.04:27:23.88#ibcon#about to read 3, iclass 22, count 0 2006.257.04:27:23.90#ibcon#read 3, iclass 22, count 0 2006.257.04:27:23.90#ibcon#about to read 4, iclass 22, count 0 2006.257.04:27:23.90#ibcon#read 4, iclass 22, count 0 2006.257.04:27:23.90#ibcon#about to read 5, iclass 22, count 0 2006.257.04:27:23.90#ibcon#read 5, iclass 22, count 0 2006.257.04:27:23.90#ibcon#about to read 6, iclass 22, count 0 2006.257.04:27:23.90#ibcon#read 6, iclass 22, count 0 2006.257.04:27:23.90#ibcon#end of sib2, iclass 22, count 0 2006.257.04:27:23.90#ibcon#*mode == 0, iclass 22, count 0 2006.257.04:27:23.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.04:27:23.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.04:27:23.90#ibcon#*before write, iclass 22, count 0 2006.257.04:27:23.90#ibcon#enter sib2, iclass 22, count 0 2006.257.04:27:23.90#ibcon#flushed, iclass 22, count 0 2006.257.04:27:23.90#ibcon#about to write, iclass 22, count 0 2006.257.04:27:23.90#ibcon#wrote, iclass 22, count 0 2006.257.04:27:23.90#ibcon#about to read 3, iclass 22, count 0 2006.257.04:27:23.94#ibcon#read 3, iclass 22, count 0 2006.257.04:27:23.94#ibcon#about to read 4, iclass 22, count 0 2006.257.04:27:23.94#ibcon#read 4, iclass 22, count 0 2006.257.04:27:23.94#ibcon#about to read 5, iclass 22, count 0 2006.257.04:27:23.94#ibcon#read 5, iclass 22, count 0 2006.257.04:27:23.94#ibcon#about to read 6, iclass 22, count 0 2006.257.04:27:23.94#ibcon#read 6, iclass 22, count 0 2006.257.04:27:23.94#ibcon#end of sib2, iclass 22, count 0 2006.257.04:27:23.94#ibcon#*after write, iclass 22, count 0 2006.257.04:27:23.94#ibcon#*before return 0, iclass 22, count 0 2006.257.04:27:23.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:23.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:23.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.04:27:23.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.04:27:23.94$vck44/va=3,8 2006.257.04:27:23.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.04:27:23.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.04:27:23.94#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:23.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:24.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:24.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:24.00#ibcon#enter wrdev, iclass 24, count 2 2006.257.04:27:24.00#ibcon#first serial, iclass 24, count 2 2006.257.04:27:24.00#ibcon#enter sib2, iclass 24, count 2 2006.257.04:27:24.00#ibcon#flushed, iclass 24, count 2 2006.257.04:27:24.00#ibcon#about to write, iclass 24, count 2 2006.257.04:27:24.00#ibcon#wrote, iclass 24, count 2 2006.257.04:27:24.00#ibcon#about to read 3, iclass 24, count 2 2006.257.04:27:24.02#ibcon#read 3, iclass 24, count 2 2006.257.04:27:24.02#ibcon#about to read 4, iclass 24, count 2 2006.257.04:27:24.02#ibcon#read 4, iclass 24, count 2 2006.257.04:27:24.02#ibcon#about to read 5, iclass 24, count 2 2006.257.04:27:24.02#ibcon#read 5, iclass 24, count 2 2006.257.04:27:24.02#ibcon#about to read 6, iclass 24, count 2 2006.257.04:27:24.02#ibcon#read 6, iclass 24, count 2 2006.257.04:27:24.02#ibcon#end of sib2, iclass 24, count 2 2006.257.04:27:24.02#ibcon#*mode == 0, iclass 24, count 2 2006.257.04:27:24.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.04:27:24.02#ibcon#[25=AT03-08\r\n] 2006.257.04:27:24.02#ibcon#*before write, iclass 24, count 2 2006.257.04:27:24.02#ibcon#enter sib2, iclass 24, count 2 2006.257.04:27:24.02#ibcon#flushed, iclass 24, count 2 2006.257.04:27:24.02#ibcon#about to write, iclass 24, count 2 2006.257.04:27:24.02#ibcon#wrote, iclass 24, count 2 2006.257.04:27:24.02#ibcon#about to read 3, iclass 24, count 2 2006.257.04:27:24.05#ibcon#read 3, iclass 24, count 2 2006.257.04:27:24.05#ibcon#about to read 4, iclass 24, count 2 2006.257.04:27:24.05#ibcon#read 4, iclass 24, count 2 2006.257.04:27:24.05#ibcon#about to read 5, iclass 24, count 2 2006.257.04:27:24.05#ibcon#read 5, iclass 24, count 2 2006.257.04:27:24.05#ibcon#about to read 6, iclass 24, count 2 2006.257.04:27:24.05#ibcon#read 6, iclass 24, count 2 2006.257.04:27:24.05#ibcon#end of sib2, iclass 24, count 2 2006.257.04:27:24.05#ibcon#*after write, iclass 24, count 2 2006.257.04:27:24.05#ibcon#*before return 0, iclass 24, count 2 2006.257.04:27:24.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:24.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:24.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.04:27:24.05#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:24.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:24.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:24.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:24.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.04:27:24.17#ibcon#first serial, iclass 24, count 0 2006.257.04:27:24.17#ibcon#enter sib2, iclass 24, count 0 2006.257.04:27:24.17#ibcon#flushed, iclass 24, count 0 2006.257.04:27:24.17#ibcon#about to write, iclass 24, count 0 2006.257.04:27:24.17#ibcon#wrote, iclass 24, count 0 2006.257.04:27:24.17#ibcon#about to read 3, iclass 24, count 0 2006.257.04:27:24.19#ibcon#read 3, iclass 24, count 0 2006.257.04:27:24.19#ibcon#about to read 4, iclass 24, count 0 2006.257.04:27:24.19#ibcon#read 4, iclass 24, count 0 2006.257.04:27:24.19#ibcon#about to read 5, iclass 24, count 0 2006.257.04:27:24.19#ibcon#read 5, iclass 24, count 0 2006.257.04:27:24.19#ibcon#about to read 6, iclass 24, count 0 2006.257.04:27:24.19#ibcon#read 6, iclass 24, count 0 2006.257.04:27:24.19#ibcon#end of sib2, iclass 24, count 0 2006.257.04:27:24.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.04:27:24.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.04:27:24.19#ibcon#[25=USB\r\n] 2006.257.04:27:24.19#ibcon#*before write, iclass 24, count 0 2006.257.04:27:24.19#ibcon#enter sib2, iclass 24, count 0 2006.257.04:27:24.19#ibcon#flushed, iclass 24, count 0 2006.257.04:27:24.19#ibcon#about to write, iclass 24, count 0 2006.257.04:27:24.19#ibcon#wrote, iclass 24, count 0 2006.257.04:27:24.19#ibcon#about to read 3, iclass 24, count 0 2006.257.04:27:24.22#ibcon#read 3, iclass 24, count 0 2006.257.04:27:24.22#ibcon#about to read 4, iclass 24, count 0 2006.257.04:27:24.22#ibcon#read 4, iclass 24, count 0 2006.257.04:27:24.22#ibcon#about to read 5, iclass 24, count 0 2006.257.04:27:24.22#ibcon#read 5, iclass 24, count 0 2006.257.04:27:24.22#ibcon#about to read 6, iclass 24, count 0 2006.257.04:27:24.22#ibcon#read 6, iclass 24, count 0 2006.257.04:27:24.22#ibcon#end of sib2, iclass 24, count 0 2006.257.04:27:24.22#ibcon#*after write, iclass 24, count 0 2006.257.04:27:24.22#ibcon#*before return 0, iclass 24, count 0 2006.257.04:27:24.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:24.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:24.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.04:27:24.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.04:27:24.22$vck44/valo=4,624.99 2006.257.04:27:24.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.04:27:24.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.04:27:24.22#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:24.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:24.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:24.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:24.22#ibcon#enter wrdev, iclass 26, count 0 2006.257.04:27:24.22#ibcon#first serial, iclass 26, count 0 2006.257.04:27:24.22#ibcon#enter sib2, iclass 26, count 0 2006.257.04:27:24.22#ibcon#flushed, iclass 26, count 0 2006.257.04:27:24.22#ibcon#about to write, iclass 26, count 0 2006.257.04:27:24.22#ibcon#wrote, iclass 26, count 0 2006.257.04:27:24.22#ibcon#about to read 3, iclass 26, count 0 2006.257.04:27:24.24#ibcon#read 3, iclass 26, count 0 2006.257.04:27:24.24#ibcon#about to read 4, iclass 26, count 0 2006.257.04:27:24.24#ibcon#read 4, iclass 26, count 0 2006.257.04:27:24.24#ibcon#about to read 5, iclass 26, count 0 2006.257.04:27:24.24#ibcon#read 5, iclass 26, count 0 2006.257.04:27:24.24#ibcon#about to read 6, iclass 26, count 0 2006.257.04:27:24.24#ibcon#read 6, iclass 26, count 0 2006.257.04:27:24.24#ibcon#end of sib2, iclass 26, count 0 2006.257.04:27:24.24#ibcon#*mode == 0, iclass 26, count 0 2006.257.04:27:24.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.04:27:24.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.04:27:24.24#ibcon#*before write, iclass 26, count 0 2006.257.04:27:24.24#ibcon#enter sib2, iclass 26, count 0 2006.257.04:27:24.24#ibcon#flushed, iclass 26, count 0 2006.257.04:27:24.24#ibcon#about to write, iclass 26, count 0 2006.257.04:27:24.24#ibcon#wrote, iclass 26, count 0 2006.257.04:27:24.24#ibcon#about to read 3, iclass 26, count 0 2006.257.04:27:24.28#ibcon#read 3, iclass 26, count 0 2006.257.04:27:24.28#ibcon#about to read 4, iclass 26, count 0 2006.257.04:27:24.28#ibcon#read 4, iclass 26, count 0 2006.257.04:27:24.28#ibcon#about to read 5, iclass 26, count 0 2006.257.04:27:24.28#ibcon#read 5, iclass 26, count 0 2006.257.04:27:24.28#ibcon#about to read 6, iclass 26, count 0 2006.257.04:27:24.28#ibcon#read 6, iclass 26, count 0 2006.257.04:27:24.28#ibcon#end of sib2, iclass 26, count 0 2006.257.04:27:24.28#ibcon#*after write, iclass 26, count 0 2006.257.04:27:24.28#ibcon#*before return 0, iclass 26, count 0 2006.257.04:27:24.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:24.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:24.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.04:27:24.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.04:27:24.28$vck44/va=4,7 2006.257.04:27:24.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.04:27:24.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.04:27:24.28#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:24.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:24.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:24.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:24.34#ibcon#enter wrdev, iclass 28, count 2 2006.257.04:27:24.34#ibcon#first serial, iclass 28, count 2 2006.257.04:27:24.34#ibcon#enter sib2, iclass 28, count 2 2006.257.04:27:24.34#ibcon#flushed, iclass 28, count 2 2006.257.04:27:24.34#ibcon#about to write, iclass 28, count 2 2006.257.04:27:24.34#ibcon#wrote, iclass 28, count 2 2006.257.04:27:24.34#ibcon#about to read 3, iclass 28, count 2 2006.257.04:27:24.36#ibcon#read 3, iclass 28, count 2 2006.257.04:27:24.36#ibcon#about to read 4, iclass 28, count 2 2006.257.04:27:24.36#ibcon#read 4, iclass 28, count 2 2006.257.04:27:24.36#ibcon#about to read 5, iclass 28, count 2 2006.257.04:27:24.36#ibcon#read 5, iclass 28, count 2 2006.257.04:27:24.36#ibcon#about to read 6, iclass 28, count 2 2006.257.04:27:24.36#ibcon#read 6, iclass 28, count 2 2006.257.04:27:24.36#ibcon#end of sib2, iclass 28, count 2 2006.257.04:27:24.36#ibcon#*mode == 0, iclass 28, count 2 2006.257.04:27:24.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.04:27:24.36#ibcon#[25=AT04-07\r\n] 2006.257.04:27:24.36#ibcon#*before write, iclass 28, count 2 2006.257.04:27:24.36#ibcon#enter sib2, iclass 28, count 2 2006.257.04:27:24.36#ibcon#flushed, iclass 28, count 2 2006.257.04:27:24.36#ibcon#about to write, iclass 28, count 2 2006.257.04:27:24.36#ibcon#wrote, iclass 28, count 2 2006.257.04:27:24.36#ibcon#about to read 3, iclass 28, count 2 2006.257.04:27:24.39#ibcon#read 3, iclass 28, count 2 2006.257.04:27:24.39#ibcon#about to read 4, iclass 28, count 2 2006.257.04:27:24.39#ibcon#read 4, iclass 28, count 2 2006.257.04:27:24.39#ibcon#about to read 5, iclass 28, count 2 2006.257.04:27:24.39#ibcon#read 5, iclass 28, count 2 2006.257.04:27:24.39#ibcon#about to read 6, iclass 28, count 2 2006.257.04:27:24.39#ibcon#read 6, iclass 28, count 2 2006.257.04:27:24.39#ibcon#end of sib2, iclass 28, count 2 2006.257.04:27:24.39#ibcon#*after write, iclass 28, count 2 2006.257.04:27:24.39#ibcon#*before return 0, iclass 28, count 2 2006.257.04:27:24.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:24.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:24.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.04:27:24.39#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:24.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:24.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:24.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:24.51#ibcon#enter wrdev, iclass 28, count 0 2006.257.04:27:24.51#ibcon#first serial, iclass 28, count 0 2006.257.04:27:24.51#ibcon#enter sib2, iclass 28, count 0 2006.257.04:27:24.51#ibcon#flushed, iclass 28, count 0 2006.257.04:27:24.51#ibcon#about to write, iclass 28, count 0 2006.257.04:27:24.51#ibcon#wrote, iclass 28, count 0 2006.257.04:27:24.51#ibcon#about to read 3, iclass 28, count 0 2006.257.04:27:24.53#ibcon#read 3, iclass 28, count 0 2006.257.04:27:24.53#ibcon#about to read 4, iclass 28, count 0 2006.257.04:27:24.53#ibcon#read 4, iclass 28, count 0 2006.257.04:27:24.53#ibcon#about to read 5, iclass 28, count 0 2006.257.04:27:24.53#ibcon#read 5, iclass 28, count 0 2006.257.04:27:24.53#ibcon#about to read 6, iclass 28, count 0 2006.257.04:27:24.53#ibcon#read 6, iclass 28, count 0 2006.257.04:27:24.53#ibcon#end of sib2, iclass 28, count 0 2006.257.04:27:24.53#ibcon#*mode == 0, iclass 28, count 0 2006.257.04:27:24.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.04:27:24.53#ibcon#[25=USB\r\n] 2006.257.04:27:24.53#ibcon#*before write, iclass 28, count 0 2006.257.04:27:24.53#ibcon#enter sib2, iclass 28, count 0 2006.257.04:27:24.53#ibcon#flushed, iclass 28, count 0 2006.257.04:27:24.53#ibcon#about to write, iclass 28, count 0 2006.257.04:27:24.53#ibcon#wrote, iclass 28, count 0 2006.257.04:27:24.53#ibcon#about to read 3, iclass 28, count 0 2006.257.04:27:24.56#ibcon#read 3, iclass 28, count 0 2006.257.04:27:24.56#ibcon#about to read 4, iclass 28, count 0 2006.257.04:27:24.56#ibcon#read 4, iclass 28, count 0 2006.257.04:27:24.56#ibcon#about to read 5, iclass 28, count 0 2006.257.04:27:24.56#ibcon#read 5, iclass 28, count 0 2006.257.04:27:24.56#ibcon#about to read 6, iclass 28, count 0 2006.257.04:27:24.56#ibcon#read 6, iclass 28, count 0 2006.257.04:27:24.56#ibcon#end of sib2, iclass 28, count 0 2006.257.04:27:24.56#ibcon#*after write, iclass 28, count 0 2006.257.04:27:24.56#ibcon#*before return 0, iclass 28, count 0 2006.257.04:27:24.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:24.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:24.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.04:27:24.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.04:27:24.56$vck44/valo=5,734.99 2006.257.04:27:24.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.04:27:24.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.04:27:24.56#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:24.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:24.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:24.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:24.56#ibcon#enter wrdev, iclass 30, count 0 2006.257.04:27:24.56#ibcon#first serial, iclass 30, count 0 2006.257.04:27:24.56#ibcon#enter sib2, iclass 30, count 0 2006.257.04:27:24.56#ibcon#flushed, iclass 30, count 0 2006.257.04:27:24.56#ibcon#about to write, iclass 30, count 0 2006.257.04:27:24.56#ibcon#wrote, iclass 30, count 0 2006.257.04:27:24.56#ibcon#about to read 3, iclass 30, count 0 2006.257.04:27:24.58#ibcon#read 3, iclass 30, count 0 2006.257.04:27:24.58#ibcon#about to read 4, iclass 30, count 0 2006.257.04:27:24.58#ibcon#read 4, iclass 30, count 0 2006.257.04:27:24.58#ibcon#about to read 5, iclass 30, count 0 2006.257.04:27:24.58#ibcon#read 5, iclass 30, count 0 2006.257.04:27:24.58#ibcon#about to read 6, iclass 30, count 0 2006.257.04:27:24.58#ibcon#read 6, iclass 30, count 0 2006.257.04:27:24.58#ibcon#end of sib2, iclass 30, count 0 2006.257.04:27:24.58#ibcon#*mode == 0, iclass 30, count 0 2006.257.04:27:24.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.04:27:24.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.04:27:24.58#ibcon#*before write, iclass 30, count 0 2006.257.04:27:24.58#ibcon#enter sib2, iclass 30, count 0 2006.257.04:27:24.58#ibcon#flushed, iclass 30, count 0 2006.257.04:27:24.58#ibcon#about to write, iclass 30, count 0 2006.257.04:27:24.58#ibcon#wrote, iclass 30, count 0 2006.257.04:27:24.58#ibcon#about to read 3, iclass 30, count 0 2006.257.04:27:24.62#ibcon#read 3, iclass 30, count 0 2006.257.04:27:24.62#ibcon#about to read 4, iclass 30, count 0 2006.257.04:27:24.62#ibcon#read 4, iclass 30, count 0 2006.257.04:27:24.62#ibcon#about to read 5, iclass 30, count 0 2006.257.04:27:24.62#ibcon#read 5, iclass 30, count 0 2006.257.04:27:24.62#ibcon#about to read 6, iclass 30, count 0 2006.257.04:27:24.62#ibcon#read 6, iclass 30, count 0 2006.257.04:27:24.62#ibcon#end of sib2, iclass 30, count 0 2006.257.04:27:24.62#ibcon#*after write, iclass 30, count 0 2006.257.04:27:24.62#ibcon#*before return 0, iclass 30, count 0 2006.257.04:27:24.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:24.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:24.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.04:27:24.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.04:27:24.62$vck44/va=5,4 2006.257.04:27:24.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.04:27:24.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.04:27:24.62#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:24.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:24.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:24.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:24.68#ibcon#enter wrdev, iclass 32, count 2 2006.257.04:27:24.68#ibcon#first serial, iclass 32, count 2 2006.257.04:27:24.68#ibcon#enter sib2, iclass 32, count 2 2006.257.04:27:24.68#ibcon#flushed, iclass 32, count 2 2006.257.04:27:24.68#ibcon#about to write, iclass 32, count 2 2006.257.04:27:24.68#ibcon#wrote, iclass 32, count 2 2006.257.04:27:24.68#ibcon#about to read 3, iclass 32, count 2 2006.257.04:27:24.70#ibcon#read 3, iclass 32, count 2 2006.257.04:27:24.70#ibcon#about to read 4, iclass 32, count 2 2006.257.04:27:24.70#ibcon#read 4, iclass 32, count 2 2006.257.04:27:24.70#ibcon#about to read 5, iclass 32, count 2 2006.257.04:27:24.70#ibcon#read 5, iclass 32, count 2 2006.257.04:27:24.70#ibcon#about to read 6, iclass 32, count 2 2006.257.04:27:24.70#ibcon#read 6, iclass 32, count 2 2006.257.04:27:24.70#ibcon#end of sib2, iclass 32, count 2 2006.257.04:27:24.70#ibcon#*mode == 0, iclass 32, count 2 2006.257.04:27:24.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.04:27:24.70#ibcon#[25=AT05-04\r\n] 2006.257.04:27:24.70#ibcon#*before write, iclass 32, count 2 2006.257.04:27:24.70#ibcon#enter sib2, iclass 32, count 2 2006.257.04:27:24.70#ibcon#flushed, iclass 32, count 2 2006.257.04:27:24.70#ibcon#about to write, iclass 32, count 2 2006.257.04:27:24.70#ibcon#wrote, iclass 32, count 2 2006.257.04:27:24.70#ibcon#about to read 3, iclass 32, count 2 2006.257.04:27:24.73#ibcon#read 3, iclass 32, count 2 2006.257.04:27:24.73#ibcon#about to read 4, iclass 32, count 2 2006.257.04:27:24.73#ibcon#read 4, iclass 32, count 2 2006.257.04:27:24.73#ibcon#about to read 5, iclass 32, count 2 2006.257.04:27:24.73#ibcon#read 5, iclass 32, count 2 2006.257.04:27:24.73#ibcon#about to read 6, iclass 32, count 2 2006.257.04:27:24.73#ibcon#read 6, iclass 32, count 2 2006.257.04:27:24.73#ibcon#end of sib2, iclass 32, count 2 2006.257.04:27:24.73#ibcon#*after write, iclass 32, count 2 2006.257.04:27:24.73#ibcon#*before return 0, iclass 32, count 2 2006.257.04:27:24.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:24.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:24.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.04:27:24.73#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:24.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:24.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:24.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:24.85#ibcon#enter wrdev, iclass 32, count 0 2006.257.04:27:24.85#ibcon#first serial, iclass 32, count 0 2006.257.04:27:24.85#ibcon#enter sib2, iclass 32, count 0 2006.257.04:27:24.85#ibcon#flushed, iclass 32, count 0 2006.257.04:27:24.85#ibcon#about to write, iclass 32, count 0 2006.257.04:27:24.85#ibcon#wrote, iclass 32, count 0 2006.257.04:27:24.85#ibcon#about to read 3, iclass 32, count 0 2006.257.04:27:24.87#ibcon#read 3, iclass 32, count 0 2006.257.04:27:24.87#ibcon#about to read 4, iclass 32, count 0 2006.257.04:27:24.87#ibcon#read 4, iclass 32, count 0 2006.257.04:27:24.87#ibcon#about to read 5, iclass 32, count 0 2006.257.04:27:24.87#ibcon#read 5, iclass 32, count 0 2006.257.04:27:24.87#ibcon#about to read 6, iclass 32, count 0 2006.257.04:27:24.87#ibcon#read 6, iclass 32, count 0 2006.257.04:27:24.87#ibcon#end of sib2, iclass 32, count 0 2006.257.04:27:24.87#ibcon#*mode == 0, iclass 32, count 0 2006.257.04:27:24.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.04:27:24.87#ibcon#[25=USB\r\n] 2006.257.04:27:24.87#ibcon#*before write, iclass 32, count 0 2006.257.04:27:24.87#ibcon#enter sib2, iclass 32, count 0 2006.257.04:27:24.87#ibcon#flushed, iclass 32, count 0 2006.257.04:27:24.87#ibcon#about to write, iclass 32, count 0 2006.257.04:27:24.87#ibcon#wrote, iclass 32, count 0 2006.257.04:27:24.87#ibcon#about to read 3, iclass 32, count 0 2006.257.04:27:24.90#ibcon#read 3, iclass 32, count 0 2006.257.04:27:24.90#ibcon#about to read 4, iclass 32, count 0 2006.257.04:27:24.90#ibcon#read 4, iclass 32, count 0 2006.257.04:27:24.90#ibcon#about to read 5, iclass 32, count 0 2006.257.04:27:24.90#ibcon#read 5, iclass 32, count 0 2006.257.04:27:24.90#ibcon#about to read 6, iclass 32, count 0 2006.257.04:27:24.90#ibcon#read 6, iclass 32, count 0 2006.257.04:27:24.90#ibcon#end of sib2, iclass 32, count 0 2006.257.04:27:24.90#ibcon#*after write, iclass 32, count 0 2006.257.04:27:24.90#ibcon#*before return 0, iclass 32, count 0 2006.257.04:27:24.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:24.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:24.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.04:27:24.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.04:27:24.90$vck44/valo=6,814.99 2006.257.04:27:24.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.04:27:24.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.04:27:24.90#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:24.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:24.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:24.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:24.90#ibcon#enter wrdev, iclass 34, count 0 2006.257.04:27:24.90#ibcon#first serial, iclass 34, count 0 2006.257.04:27:24.90#ibcon#enter sib2, iclass 34, count 0 2006.257.04:27:24.90#ibcon#flushed, iclass 34, count 0 2006.257.04:27:24.90#ibcon#about to write, iclass 34, count 0 2006.257.04:27:24.90#ibcon#wrote, iclass 34, count 0 2006.257.04:27:24.90#ibcon#about to read 3, iclass 34, count 0 2006.257.04:27:24.92#ibcon#read 3, iclass 34, count 0 2006.257.04:27:24.92#ibcon#about to read 4, iclass 34, count 0 2006.257.04:27:24.92#ibcon#read 4, iclass 34, count 0 2006.257.04:27:24.92#ibcon#about to read 5, iclass 34, count 0 2006.257.04:27:24.92#ibcon#read 5, iclass 34, count 0 2006.257.04:27:24.92#ibcon#about to read 6, iclass 34, count 0 2006.257.04:27:24.92#ibcon#read 6, iclass 34, count 0 2006.257.04:27:24.92#ibcon#end of sib2, iclass 34, count 0 2006.257.04:27:24.92#ibcon#*mode == 0, iclass 34, count 0 2006.257.04:27:24.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.04:27:24.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.04:27:24.92#ibcon#*before write, iclass 34, count 0 2006.257.04:27:24.92#ibcon#enter sib2, iclass 34, count 0 2006.257.04:27:24.92#ibcon#flushed, iclass 34, count 0 2006.257.04:27:24.92#ibcon#about to write, iclass 34, count 0 2006.257.04:27:24.92#ibcon#wrote, iclass 34, count 0 2006.257.04:27:24.92#ibcon#about to read 3, iclass 34, count 0 2006.257.04:27:24.96#ibcon#read 3, iclass 34, count 0 2006.257.04:27:24.96#ibcon#about to read 4, iclass 34, count 0 2006.257.04:27:24.96#ibcon#read 4, iclass 34, count 0 2006.257.04:27:24.96#ibcon#about to read 5, iclass 34, count 0 2006.257.04:27:24.96#ibcon#read 5, iclass 34, count 0 2006.257.04:27:24.96#ibcon#about to read 6, iclass 34, count 0 2006.257.04:27:24.96#ibcon#read 6, iclass 34, count 0 2006.257.04:27:24.96#ibcon#end of sib2, iclass 34, count 0 2006.257.04:27:24.96#ibcon#*after write, iclass 34, count 0 2006.257.04:27:24.96#ibcon#*before return 0, iclass 34, count 0 2006.257.04:27:24.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:24.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:24.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.04:27:24.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.04:27:24.96$vck44/va=6,4 2006.257.04:27:24.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.04:27:24.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.04:27:24.96#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:24.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:25.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:25.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:25.02#ibcon#enter wrdev, iclass 36, count 2 2006.257.04:27:25.02#ibcon#first serial, iclass 36, count 2 2006.257.04:27:25.02#ibcon#enter sib2, iclass 36, count 2 2006.257.04:27:25.02#ibcon#flushed, iclass 36, count 2 2006.257.04:27:25.02#ibcon#about to write, iclass 36, count 2 2006.257.04:27:25.02#ibcon#wrote, iclass 36, count 2 2006.257.04:27:25.02#ibcon#about to read 3, iclass 36, count 2 2006.257.04:27:25.04#ibcon#read 3, iclass 36, count 2 2006.257.04:27:25.04#ibcon#about to read 4, iclass 36, count 2 2006.257.04:27:25.04#ibcon#read 4, iclass 36, count 2 2006.257.04:27:25.04#ibcon#about to read 5, iclass 36, count 2 2006.257.04:27:25.04#ibcon#read 5, iclass 36, count 2 2006.257.04:27:25.04#ibcon#about to read 6, iclass 36, count 2 2006.257.04:27:25.04#ibcon#read 6, iclass 36, count 2 2006.257.04:27:25.04#ibcon#end of sib2, iclass 36, count 2 2006.257.04:27:25.04#ibcon#*mode == 0, iclass 36, count 2 2006.257.04:27:25.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.04:27:25.04#ibcon#[25=AT06-04\r\n] 2006.257.04:27:25.04#ibcon#*before write, iclass 36, count 2 2006.257.04:27:25.04#ibcon#enter sib2, iclass 36, count 2 2006.257.04:27:25.04#ibcon#flushed, iclass 36, count 2 2006.257.04:27:25.04#ibcon#about to write, iclass 36, count 2 2006.257.04:27:25.04#ibcon#wrote, iclass 36, count 2 2006.257.04:27:25.04#ibcon#about to read 3, iclass 36, count 2 2006.257.04:27:25.07#ibcon#read 3, iclass 36, count 2 2006.257.04:27:25.07#ibcon#about to read 4, iclass 36, count 2 2006.257.04:27:25.07#ibcon#read 4, iclass 36, count 2 2006.257.04:27:25.07#ibcon#about to read 5, iclass 36, count 2 2006.257.04:27:25.07#ibcon#read 5, iclass 36, count 2 2006.257.04:27:25.07#ibcon#about to read 6, iclass 36, count 2 2006.257.04:27:25.07#ibcon#read 6, iclass 36, count 2 2006.257.04:27:25.07#ibcon#end of sib2, iclass 36, count 2 2006.257.04:27:25.07#ibcon#*after write, iclass 36, count 2 2006.257.04:27:25.07#ibcon#*before return 0, iclass 36, count 2 2006.257.04:27:25.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:25.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:25.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.04:27:25.07#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:25.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:25.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:25.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:25.19#ibcon#enter wrdev, iclass 36, count 0 2006.257.04:27:25.19#ibcon#first serial, iclass 36, count 0 2006.257.04:27:25.19#ibcon#enter sib2, iclass 36, count 0 2006.257.04:27:25.19#ibcon#flushed, iclass 36, count 0 2006.257.04:27:25.19#ibcon#about to write, iclass 36, count 0 2006.257.04:27:25.19#ibcon#wrote, iclass 36, count 0 2006.257.04:27:25.19#ibcon#about to read 3, iclass 36, count 0 2006.257.04:27:25.21#ibcon#read 3, iclass 36, count 0 2006.257.04:27:25.21#ibcon#about to read 4, iclass 36, count 0 2006.257.04:27:25.21#ibcon#read 4, iclass 36, count 0 2006.257.04:27:25.21#ibcon#about to read 5, iclass 36, count 0 2006.257.04:27:25.21#ibcon#read 5, iclass 36, count 0 2006.257.04:27:25.21#ibcon#about to read 6, iclass 36, count 0 2006.257.04:27:25.21#ibcon#read 6, iclass 36, count 0 2006.257.04:27:25.21#ibcon#end of sib2, iclass 36, count 0 2006.257.04:27:25.21#ibcon#*mode == 0, iclass 36, count 0 2006.257.04:27:25.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.04:27:25.21#ibcon#[25=USB\r\n] 2006.257.04:27:25.21#ibcon#*before write, iclass 36, count 0 2006.257.04:27:25.21#ibcon#enter sib2, iclass 36, count 0 2006.257.04:27:25.21#ibcon#flushed, iclass 36, count 0 2006.257.04:27:25.21#ibcon#about to write, iclass 36, count 0 2006.257.04:27:25.21#ibcon#wrote, iclass 36, count 0 2006.257.04:27:25.21#ibcon#about to read 3, iclass 36, count 0 2006.257.04:27:25.24#ibcon#read 3, iclass 36, count 0 2006.257.04:27:25.24#ibcon#about to read 4, iclass 36, count 0 2006.257.04:27:25.24#ibcon#read 4, iclass 36, count 0 2006.257.04:27:25.24#ibcon#about to read 5, iclass 36, count 0 2006.257.04:27:25.24#ibcon#read 5, iclass 36, count 0 2006.257.04:27:25.24#ibcon#about to read 6, iclass 36, count 0 2006.257.04:27:25.24#ibcon#read 6, iclass 36, count 0 2006.257.04:27:25.24#ibcon#end of sib2, iclass 36, count 0 2006.257.04:27:25.24#ibcon#*after write, iclass 36, count 0 2006.257.04:27:25.24#ibcon#*before return 0, iclass 36, count 0 2006.257.04:27:25.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:25.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:25.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.04:27:25.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.04:27:25.24$vck44/valo=7,864.99 2006.257.04:27:25.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.04:27:25.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.04:27:25.24#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:25.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:25.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:25.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:25.24#ibcon#enter wrdev, iclass 38, count 0 2006.257.04:27:25.24#ibcon#first serial, iclass 38, count 0 2006.257.04:27:25.24#ibcon#enter sib2, iclass 38, count 0 2006.257.04:27:25.24#ibcon#flushed, iclass 38, count 0 2006.257.04:27:25.24#ibcon#about to write, iclass 38, count 0 2006.257.04:27:25.24#ibcon#wrote, iclass 38, count 0 2006.257.04:27:25.24#ibcon#about to read 3, iclass 38, count 0 2006.257.04:27:25.26#ibcon#read 3, iclass 38, count 0 2006.257.04:27:25.26#ibcon#about to read 4, iclass 38, count 0 2006.257.04:27:25.26#ibcon#read 4, iclass 38, count 0 2006.257.04:27:25.26#ibcon#about to read 5, iclass 38, count 0 2006.257.04:27:25.26#ibcon#read 5, iclass 38, count 0 2006.257.04:27:25.26#ibcon#about to read 6, iclass 38, count 0 2006.257.04:27:25.26#ibcon#read 6, iclass 38, count 0 2006.257.04:27:25.26#ibcon#end of sib2, iclass 38, count 0 2006.257.04:27:25.26#ibcon#*mode == 0, iclass 38, count 0 2006.257.04:27:25.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.04:27:25.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.04:27:25.26#ibcon#*before write, iclass 38, count 0 2006.257.04:27:25.26#ibcon#enter sib2, iclass 38, count 0 2006.257.04:27:25.26#ibcon#flushed, iclass 38, count 0 2006.257.04:27:25.26#ibcon#about to write, iclass 38, count 0 2006.257.04:27:25.26#ibcon#wrote, iclass 38, count 0 2006.257.04:27:25.26#ibcon#about to read 3, iclass 38, count 0 2006.257.04:27:25.30#ibcon#read 3, iclass 38, count 0 2006.257.04:27:25.30#ibcon#about to read 4, iclass 38, count 0 2006.257.04:27:25.30#ibcon#read 4, iclass 38, count 0 2006.257.04:27:25.30#ibcon#about to read 5, iclass 38, count 0 2006.257.04:27:25.30#ibcon#read 5, iclass 38, count 0 2006.257.04:27:25.30#ibcon#about to read 6, iclass 38, count 0 2006.257.04:27:25.30#ibcon#read 6, iclass 38, count 0 2006.257.04:27:25.30#ibcon#end of sib2, iclass 38, count 0 2006.257.04:27:25.30#ibcon#*after write, iclass 38, count 0 2006.257.04:27:25.30#ibcon#*before return 0, iclass 38, count 0 2006.257.04:27:25.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:25.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:25.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.04:27:25.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.04:27:25.30$vck44/va=7,4 2006.257.04:27:25.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.04:27:25.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.04:27:25.30#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:25.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:25.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:25.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:25.36#ibcon#enter wrdev, iclass 40, count 2 2006.257.04:27:25.36#ibcon#first serial, iclass 40, count 2 2006.257.04:27:25.36#ibcon#enter sib2, iclass 40, count 2 2006.257.04:27:25.36#ibcon#flushed, iclass 40, count 2 2006.257.04:27:25.36#ibcon#about to write, iclass 40, count 2 2006.257.04:27:25.36#ibcon#wrote, iclass 40, count 2 2006.257.04:27:25.36#ibcon#about to read 3, iclass 40, count 2 2006.257.04:27:25.38#ibcon#read 3, iclass 40, count 2 2006.257.04:27:25.38#ibcon#about to read 4, iclass 40, count 2 2006.257.04:27:25.38#ibcon#read 4, iclass 40, count 2 2006.257.04:27:25.38#ibcon#about to read 5, iclass 40, count 2 2006.257.04:27:25.38#ibcon#read 5, iclass 40, count 2 2006.257.04:27:25.38#ibcon#about to read 6, iclass 40, count 2 2006.257.04:27:25.38#ibcon#read 6, iclass 40, count 2 2006.257.04:27:25.38#ibcon#end of sib2, iclass 40, count 2 2006.257.04:27:25.38#ibcon#*mode == 0, iclass 40, count 2 2006.257.04:27:25.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.04:27:25.38#ibcon#[25=AT07-04\r\n] 2006.257.04:27:25.38#ibcon#*before write, iclass 40, count 2 2006.257.04:27:25.38#ibcon#enter sib2, iclass 40, count 2 2006.257.04:27:25.38#ibcon#flushed, iclass 40, count 2 2006.257.04:27:25.38#ibcon#about to write, iclass 40, count 2 2006.257.04:27:25.38#ibcon#wrote, iclass 40, count 2 2006.257.04:27:25.38#ibcon#about to read 3, iclass 40, count 2 2006.257.04:27:25.41#ibcon#read 3, iclass 40, count 2 2006.257.04:27:25.41#ibcon#about to read 4, iclass 40, count 2 2006.257.04:27:25.41#ibcon#read 4, iclass 40, count 2 2006.257.04:27:25.41#ibcon#about to read 5, iclass 40, count 2 2006.257.04:27:25.41#ibcon#read 5, iclass 40, count 2 2006.257.04:27:25.41#ibcon#about to read 6, iclass 40, count 2 2006.257.04:27:25.41#ibcon#read 6, iclass 40, count 2 2006.257.04:27:25.41#ibcon#end of sib2, iclass 40, count 2 2006.257.04:27:25.41#ibcon#*after write, iclass 40, count 2 2006.257.04:27:25.41#ibcon#*before return 0, iclass 40, count 2 2006.257.04:27:25.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:25.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:25.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.04:27:25.41#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:25.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:25.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:25.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:25.53#ibcon#enter wrdev, iclass 40, count 0 2006.257.04:27:25.53#ibcon#first serial, iclass 40, count 0 2006.257.04:27:25.53#ibcon#enter sib2, iclass 40, count 0 2006.257.04:27:25.53#ibcon#flushed, iclass 40, count 0 2006.257.04:27:25.53#ibcon#about to write, iclass 40, count 0 2006.257.04:27:25.53#ibcon#wrote, iclass 40, count 0 2006.257.04:27:25.53#ibcon#about to read 3, iclass 40, count 0 2006.257.04:27:25.55#ibcon#read 3, iclass 40, count 0 2006.257.04:27:25.55#ibcon#about to read 4, iclass 40, count 0 2006.257.04:27:25.55#ibcon#read 4, iclass 40, count 0 2006.257.04:27:25.55#ibcon#about to read 5, iclass 40, count 0 2006.257.04:27:25.55#ibcon#read 5, iclass 40, count 0 2006.257.04:27:25.55#ibcon#about to read 6, iclass 40, count 0 2006.257.04:27:25.55#ibcon#read 6, iclass 40, count 0 2006.257.04:27:25.55#ibcon#end of sib2, iclass 40, count 0 2006.257.04:27:25.55#ibcon#*mode == 0, iclass 40, count 0 2006.257.04:27:25.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.04:27:25.55#ibcon#[25=USB\r\n] 2006.257.04:27:25.55#ibcon#*before write, iclass 40, count 0 2006.257.04:27:25.55#ibcon#enter sib2, iclass 40, count 0 2006.257.04:27:25.55#ibcon#flushed, iclass 40, count 0 2006.257.04:27:25.55#ibcon#about to write, iclass 40, count 0 2006.257.04:27:25.55#ibcon#wrote, iclass 40, count 0 2006.257.04:27:25.55#ibcon#about to read 3, iclass 40, count 0 2006.257.04:27:25.58#ibcon#read 3, iclass 40, count 0 2006.257.04:27:25.58#ibcon#about to read 4, iclass 40, count 0 2006.257.04:27:25.58#ibcon#read 4, iclass 40, count 0 2006.257.04:27:25.58#ibcon#about to read 5, iclass 40, count 0 2006.257.04:27:25.58#ibcon#read 5, iclass 40, count 0 2006.257.04:27:25.58#ibcon#about to read 6, iclass 40, count 0 2006.257.04:27:25.58#ibcon#read 6, iclass 40, count 0 2006.257.04:27:25.58#ibcon#end of sib2, iclass 40, count 0 2006.257.04:27:25.58#ibcon#*after write, iclass 40, count 0 2006.257.04:27:25.58#ibcon#*before return 0, iclass 40, count 0 2006.257.04:27:25.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:25.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:25.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.04:27:25.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.04:27:25.58$vck44/valo=8,884.99 2006.257.04:27:25.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.04:27:25.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.04:27:25.58#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:25.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:25.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:25.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:25.58#ibcon#enter wrdev, iclass 4, count 0 2006.257.04:27:25.58#ibcon#first serial, iclass 4, count 0 2006.257.04:27:25.58#ibcon#enter sib2, iclass 4, count 0 2006.257.04:27:25.58#ibcon#flushed, iclass 4, count 0 2006.257.04:27:25.58#ibcon#about to write, iclass 4, count 0 2006.257.04:27:25.58#ibcon#wrote, iclass 4, count 0 2006.257.04:27:25.58#ibcon#about to read 3, iclass 4, count 0 2006.257.04:27:25.60#ibcon#read 3, iclass 4, count 0 2006.257.04:27:25.60#ibcon#about to read 4, iclass 4, count 0 2006.257.04:27:25.60#ibcon#read 4, iclass 4, count 0 2006.257.04:27:25.60#ibcon#about to read 5, iclass 4, count 0 2006.257.04:27:25.60#ibcon#read 5, iclass 4, count 0 2006.257.04:27:25.60#ibcon#about to read 6, iclass 4, count 0 2006.257.04:27:25.60#ibcon#read 6, iclass 4, count 0 2006.257.04:27:25.60#ibcon#end of sib2, iclass 4, count 0 2006.257.04:27:25.60#ibcon#*mode == 0, iclass 4, count 0 2006.257.04:27:25.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.04:27:25.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.04:27:25.60#ibcon#*before write, iclass 4, count 0 2006.257.04:27:25.60#ibcon#enter sib2, iclass 4, count 0 2006.257.04:27:25.60#ibcon#flushed, iclass 4, count 0 2006.257.04:27:25.60#ibcon#about to write, iclass 4, count 0 2006.257.04:27:25.60#ibcon#wrote, iclass 4, count 0 2006.257.04:27:25.60#ibcon#about to read 3, iclass 4, count 0 2006.257.04:27:25.64#ibcon#read 3, iclass 4, count 0 2006.257.04:27:25.64#ibcon#about to read 4, iclass 4, count 0 2006.257.04:27:25.64#ibcon#read 4, iclass 4, count 0 2006.257.04:27:25.64#ibcon#about to read 5, iclass 4, count 0 2006.257.04:27:25.64#ibcon#read 5, iclass 4, count 0 2006.257.04:27:25.64#ibcon#about to read 6, iclass 4, count 0 2006.257.04:27:25.64#ibcon#read 6, iclass 4, count 0 2006.257.04:27:25.64#ibcon#end of sib2, iclass 4, count 0 2006.257.04:27:25.64#ibcon#*after write, iclass 4, count 0 2006.257.04:27:25.64#ibcon#*before return 0, iclass 4, count 0 2006.257.04:27:25.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:25.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:25.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.04:27:25.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.04:27:25.64$vck44/va=8,4 2006.257.04:27:25.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.04:27:25.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.04:27:25.64#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:25.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:27:25.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:27:25.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:27:25.70#ibcon#enter wrdev, iclass 6, count 2 2006.257.04:27:25.70#ibcon#first serial, iclass 6, count 2 2006.257.04:27:25.70#ibcon#enter sib2, iclass 6, count 2 2006.257.04:27:25.70#ibcon#flushed, iclass 6, count 2 2006.257.04:27:25.70#ibcon#about to write, iclass 6, count 2 2006.257.04:27:25.70#ibcon#wrote, iclass 6, count 2 2006.257.04:27:25.70#ibcon#about to read 3, iclass 6, count 2 2006.257.04:27:25.72#ibcon#read 3, iclass 6, count 2 2006.257.04:27:25.72#ibcon#about to read 4, iclass 6, count 2 2006.257.04:27:25.72#ibcon#read 4, iclass 6, count 2 2006.257.04:27:25.72#ibcon#about to read 5, iclass 6, count 2 2006.257.04:27:25.72#ibcon#read 5, iclass 6, count 2 2006.257.04:27:25.72#ibcon#about to read 6, iclass 6, count 2 2006.257.04:27:25.72#ibcon#read 6, iclass 6, count 2 2006.257.04:27:25.72#ibcon#end of sib2, iclass 6, count 2 2006.257.04:27:25.72#ibcon#*mode == 0, iclass 6, count 2 2006.257.04:27:25.72#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.04:27:25.72#ibcon#[25=AT08-04\r\n] 2006.257.04:27:25.72#ibcon#*before write, iclass 6, count 2 2006.257.04:27:25.72#ibcon#enter sib2, iclass 6, count 2 2006.257.04:27:25.72#ibcon#flushed, iclass 6, count 2 2006.257.04:27:25.72#ibcon#about to write, iclass 6, count 2 2006.257.04:27:25.72#ibcon#wrote, iclass 6, count 2 2006.257.04:27:25.72#ibcon#about to read 3, iclass 6, count 2 2006.257.04:27:25.75#ibcon#read 3, iclass 6, count 2 2006.257.04:27:25.75#ibcon#about to read 4, iclass 6, count 2 2006.257.04:27:25.75#ibcon#read 4, iclass 6, count 2 2006.257.04:27:25.75#ibcon#about to read 5, iclass 6, count 2 2006.257.04:27:25.75#ibcon#read 5, iclass 6, count 2 2006.257.04:27:25.75#ibcon#about to read 6, iclass 6, count 2 2006.257.04:27:25.75#ibcon#read 6, iclass 6, count 2 2006.257.04:27:25.75#ibcon#end of sib2, iclass 6, count 2 2006.257.04:27:25.75#ibcon#*after write, iclass 6, count 2 2006.257.04:27:25.75#ibcon#*before return 0, iclass 6, count 2 2006.257.04:27:25.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:27:25.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:27:25.75#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.04:27:25.75#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:25.75#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:27:25.87#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:27:25.87#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:27:25.87#ibcon#enter wrdev, iclass 6, count 0 2006.257.04:27:25.87#ibcon#first serial, iclass 6, count 0 2006.257.04:27:25.87#ibcon#enter sib2, iclass 6, count 0 2006.257.04:27:25.87#ibcon#flushed, iclass 6, count 0 2006.257.04:27:25.87#ibcon#about to write, iclass 6, count 0 2006.257.04:27:25.87#ibcon#wrote, iclass 6, count 0 2006.257.04:27:25.87#ibcon#about to read 3, iclass 6, count 0 2006.257.04:27:25.89#ibcon#read 3, iclass 6, count 0 2006.257.04:27:25.89#ibcon#about to read 4, iclass 6, count 0 2006.257.04:27:25.89#ibcon#read 4, iclass 6, count 0 2006.257.04:27:25.89#ibcon#about to read 5, iclass 6, count 0 2006.257.04:27:25.89#ibcon#read 5, iclass 6, count 0 2006.257.04:27:25.89#ibcon#about to read 6, iclass 6, count 0 2006.257.04:27:25.89#ibcon#read 6, iclass 6, count 0 2006.257.04:27:25.89#ibcon#end of sib2, iclass 6, count 0 2006.257.04:27:25.89#ibcon#*mode == 0, iclass 6, count 0 2006.257.04:27:25.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.04:27:25.89#ibcon#[25=USB\r\n] 2006.257.04:27:25.89#ibcon#*before write, iclass 6, count 0 2006.257.04:27:25.89#ibcon#enter sib2, iclass 6, count 0 2006.257.04:27:25.89#ibcon#flushed, iclass 6, count 0 2006.257.04:27:25.89#ibcon#about to write, iclass 6, count 0 2006.257.04:27:25.89#ibcon#wrote, iclass 6, count 0 2006.257.04:27:25.89#ibcon#about to read 3, iclass 6, count 0 2006.257.04:27:25.92#ibcon#read 3, iclass 6, count 0 2006.257.04:27:25.92#ibcon#about to read 4, iclass 6, count 0 2006.257.04:27:25.92#ibcon#read 4, iclass 6, count 0 2006.257.04:27:25.92#ibcon#about to read 5, iclass 6, count 0 2006.257.04:27:25.92#ibcon#read 5, iclass 6, count 0 2006.257.04:27:25.92#ibcon#about to read 6, iclass 6, count 0 2006.257.04:27:25.92#ibcon#read 6, iclass 6, count 0 2006.257.04:27:25.92#ibcon#end of sib2, iclass 6, count 0 2006.257.04:27:25.92#ibcon#*after write, iclass 6, count 0 2006.257.04:27:25.92#ibcon#*before return 0, iclass 6, count 0 2006.257.04:27:25.92#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:27:25.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:27:25.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.04:27:25.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.04:27:25.92$vck44/vblo=1,629.99 2006.257.04:27:25.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.04:27:25.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.04:27:25.92#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:25.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:27:25.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:27:25.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:27:25.92#ibcon#enter wrdev, iclass 10, count 0 2006.257.04:27:25.92#ibcon#first serial, iclass 10, count 0 2006.257.04:27:25.92#ibcon#enter sib2, iclass 10, count 0 2006.257.04:27:25.92#ibcon#flushed, iclass 10, count 0 2006.257.04:27:25.92#ibcon#about to write, iclass 10, count 0 2006.257.04:27:25.92#ibcon#wrote, iclass 10, count 0 2006.257.04:27:25.92#ibcon#about to read 3, iclass 10, count 0 2006.257.04:27:25.94#ibcon#read 3, iclass 10, count 0 2006.257.04:27:25.94#ibcon#about to read 4, iclass 10, count 0 2006.257.04:27:25.94#ibcon#read 4, iclass 10, count 0 2006.257.04:27:25.94#ibcon#about to read 5, iclass 10, count 0 2006.257.04:27:25.94#ibcon#read 5, iclass 10, count 0 2006.257.04:27:25.94#ibcon#about to read 6, iclass 10, count 0 2006.257.04:27:25.94#ibcon#read 6, iclass 10, count 0 2006.257.04:27:25.94#ibcon#end of sib2, iclass 10, count 0 2006.257.04:27:25.94#ibcon#*mode == 0, iclass 10, count 0 2006.257.04:27:25.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.04:27:25.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.04:27:25.94#ibcon#*before write, iclass 10, count 0 2006.257.04:27:25.94#ibcon#enter sib2, iclass 10, count 0 2006.257.04:27:25.94#ibcon#flushed, iclass 10, count 0 2006.257.04:27:25.94#ibcon#about to write, iclass 10, count 0 2006.257.04:27:25.94#ibcon#wrote, iclass 10, count 0 2006.257.04:27:25.94#ibcon#about to read 3, iclass 10, count 0 2006.257.04:27:25.98#ibcon#read 3, iclass 10, count 0 2006.257.04:27:25.98#ibcon#about to read 4, iclass 10, count 0 2006.257.04:27:25.98#ibcon#read 4, iclass 10, count 0 2006.257.04:27:25.98#ibcon#about to read 5, iclass 10, count 0 2006.257.04:27:25.98#ibcon#read 5, iclass 10, count 0 2006.257.04:27:25.98#ibcon#about to read 6, iclass 10, count 0 2006.257.04:27:25.98#ibcon#read 6, iclass 10, count 0 2006.257.04:27:25.98#ibcon#end of sib2, iclass 10, count 0 2006.257.04:27:25.98#ibcon#*after write, iclass 10, count 0 2006.257.04:27:25.98#ibcon#*before return 0, iclass 10, count 0 2006.257.04:27:25.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:27:25.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:27:25.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.04:27:25.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.04:27:25.98$vck44/vb=1,4 2006.257.04:27:25.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.04:27:25.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.04:27:25.98#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:25.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:27:25.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:27:25.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:27:25.98#ibcon#enter wrdev, iclass 12, count 2 2006.257.04:27:25.98#ibcon#first serial, iclass 12, count 2 2006.257.04:27:25.98#ibcon#enter sib2, iclass 12, count 2 2006.257.04:27:25.98#ibcon#flushed, iclass 12, count 2 2006.257.04:27:25.98#ibcon#about to write, iclass 12, count 2 2006.257.04:27:25.98#ibcon#wrote, iclass 12, count 2 2006.257.04:27:25.98#ibcon#about to read 3, iclass 12, count 2 2006.257.04:27:26.00#ibcon#read 3, iclass 12, count 2 2006.257.04:27:26.00#ibcon#about to read 4, iclass 12, count 2 2006.257.04:27:26.00#ibcon#read 4, iclass 12, count 2 2006.257.04:27:26.00#ibcon#about to read 5, iclass 12, count 2 2006.257.04:27:26.00#ibcon#read 5, iclass 12, count 2 2006.257.04:27:26.00#ibcon#about to read 6, iclass 12, count 2 2006.257.04:27:26.00#ibcon#read 6, iclass 12, count 2 2006.257.04:27:26.00#ibcon#end of sib2, iclass 12, count 2 2006.257.04:27:26.00#ibcon#*mode == 0, iclass 12, count 2 2006.257.04:27:26.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.04:27:26.00#ibcon#[27=AT01-04\r\n] 2006.257.04:27:26.00#ibcon#*before write, iclass 12, count 2 2006.257.04:27:26.00#ibcon#enter sib2, iclass 12, count 2 2006.257.04:27:26.00#ibcon#flushed, iclass 12, count 2 2006.257.04:27:26.00#ibcon#about to write, iclass 12, count 2 2006.257.04:27:26.00#ibcon#wrote, iclass 12, count 2 2006.257.04:27:26.00#ibcon#about to read 3, iclass 12, count 2 2006.257.04:27:26.03#ibcon#read 3, iclass 12, count 2 2006.257.04:27:26.03#ibcon#about to read 4, iclass 12, count 2 2006.257.04:27:26.03#ibcon#read 4, iclass 12, count 2 2006.257.04:27:26.03#ibcon#about to read 5, iclass 12, count 2 2006.257.04:27:26.03#ibcon#read 5, iclass 12, count 2 2006.257.04:27:26.03#ibcon#about to read 6, iclass 12, count 2 2006.257.04:27:26.03#ibcon#read 6, iclass 12, count 2 2006.257.04:27:26.03#ibcon#end of sib2, iclass 12, count 2 2006.257.04:27:26.03#ibcon#*after write, iclass 12, count 2 2006.257.04:27:26.03#ibcon#*before return 0, iclass 12, count 2 2006.257.04:27:26.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:27:26.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:27:26.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.04:27:26.03#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:26.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:27:26.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:27:26.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:27:26.15#ibcon#enter wrdev, iclass 12, count 0 2006.257.04:27:26.15#ibcon#first serial, iclass 12, count 0 2006.257.04:27:26.15#ibcon#enter sib2, iclass 12, count 0 2006.257.04:27:26.15#ibcon#flushed, iclass 12, count 0 2006.257.04:27:26.15#ibcon#about to write, iclass 12, count 0 2006.257.04:27:26.15#ibcon#wrote, iclass 12, count 0 2006.257.04:27:26.15#ibcon#about to read 3, iclass 12, count 0 2006.257.04:27:26.17#ibcon#read 3, iclass 12, count 0 2006.257.04:27:26.17#ibcon#about to read 4, iclass 12, count 0 2006.257.04:27:26.17#ibcon#read 4, iclass 12, count 0 2006.257.04:27:26.17#ibcon#about to read 5, iclass 12, count 0 2006.257.04:27:26.17#ibcon#read 5, iclass 12, count 0 2006.257.04:27:26.17#ibcon#about to read 6, iclass 12, count 0 2006.257.04:27:26.17#ibcon#read 6, iclass 12, count 0 2006.257.04:27:26.17#ibcon#end of sib2, iclass 12, count 0 2006.257.04:27:26.17#ibcon#*mode == 0, iclass 12, count 0 2006.257.04:27:26.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.04:27:26.17#ibcon#[27=USB\r\n] 2006.257.04:27:26.17#ibcon#*before write, iclass 12, count 0 2006.257.04:27:26.17#ibcon#enter sib2, iclass 12, count 0 2006.257.04:27:26.17#ibcon#flushed, iclass 12, count 0 2006.257.04:27:26.17#ibcon#about to write, iclass 12, count 0 2006.257.04:27:26.17#ibcon#wrote, iclass 12, count 0 2006.257.04:27:26.17#ibcon#about to read 3, iclass 12, count 0 2006.257.04:27:26.20#ibcon#read 3, iclass 12, count 0 2006.257.04:27:26.20#ibcon#about to read 4, iclass 12, count 0 2006.257.04:27:26.20#ibcon#read 4, iclass 12, count 0 2006.257.04:27:26.20#ibcon#about to read 5, iclass 12, count 0 2006.257.04:27:26.20#ibcon#read 5, iclass 12, count 0 2006.257.04:27:26.20#ibcon#about to read 6, iclass 12, count 0 2006.257.04:27:26.20#ibcon#read 6, iclass 12, count 0 2006.257.04:27:26.20#ibcon#end of sib2, iclass 12, count 0 2006.257.04:27:26.20#ibcon#*after write, iclass 12, count 0 2006.257.04:27:26.20#ibcon#*before return 0, iclass 12, count 0 2006.257.04:27:26.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:27:26.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:27:26.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.04:27:26.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.04:27:26.20$vck44/vblo=2,634.99 2006.257.04:27:26.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.04:27:26.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.04:27:26.20#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:26.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:26.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:26.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:26.20#ibcon#enter wrdev, iclass 14, count 0 2006.257.04:27:26.20#ibcon#first serial, iclass 14, count 0 2006.257.04:27:26.20#ibcon#enter sib2, iclass 14, count 0 2006.257.04:27:26.20#ibcon#flushed, iclass 14, count 0 2006.257.04:27:26.20#ibcon#about to write, iclass 14, count 0 2006.257.04:27:26.20#ibcon#wrote, iclass 14, count 0 2006.257.04:27:26.20#ibcon#about to read 3, iclass 14, count 0 2006.257.04:27:26.22#ibcon#read 3, iclass 14, count 0 2006.257.04:27:26.22#ibcon#about to read 4, iclass 14, count 0 2006.257.04:27:26.22#ibcon#read 4, iclass 14, count 0 2006.257.04:27:26.22#ibcon#about to read 5, iclass 14, count 0 2006.257.04:27:26.22#ibcon#read 5, iclass 14, count 0 2006.257.04:27:26.22#ibcon#about to read 6, iclass 14, count 0 2006.257.04:27:26.22#ibcon#read 6, iclass 14, count 0 2006.257.04:27:26.22#ibcon#end of sib2, iclass 14, count 0 2006.257.04:27:26.22#ibcon#*mode == 0, iclass 14, count 0 2006.257.04:27:26.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.04:27:26.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.04:27:26.22#ibcon#*before write, iclass 14, count 0 2006.257.04:27:26.22#ibcon#enter sib2, iclass 14, count 0 2006.257.04:27:26.22#ibcon#flushed, iclass 14, count 0 2006.257.04:27:26.22#ibcon#about to write, iclass 14, count 0 2006.257.04:27:26.22#ibcon#wrote, iclass 14, count 0 2006.257.04:27:26.22#ibcon#about to read 3, iclass 14, count 0 2006.257.04:27:26.26#ibcon#read 3, iclass 14, count 0 2006.257.04:27:26.26#ibcon#about to read 4, iclass 14, count 0 2006.257.04:27:26.26#ibcon#read 4, iclass 14, count 0 2006.257.04:27:26.26#ibcon#about to read 5, iclass 14, count 0 2006.257.04:27:26.26#ibcon#read 5, iclass 14, count 0 2006.257.04:27:26.26#ibcon#about to read 6, iclass 14, count 0 2006.257.04:27:26.26#ibcon#read 6, iclass 14, count 0 2006.257.04:27:26.26#ibcon#end of sib2, iclass 14, count 0 2006.257.04:27:26.26#ibcon#*after write, iclass 14, count 0 2006.257.04:27:26.26#ibcon#*before return 0, iclass 14, count 0 2006.257.04:27:26.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:26.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:27:26.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.04:27:26.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.04:27:26.26$vck44/vb=2,5 2006.257.04:27:26.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.04:27:26.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.04:27:26.26#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:26.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:26.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:26.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:26.32#ibcon#enter wrdev, iclass 16, count 2 2006.257.04:27:26.32#ibcon#first serial, iclass 16, count 2 2006.257.04:27:26.32#ibcon#enter sib2, iclass 16, count 2 2006.257.04:27:26.32#ibcon#flushed, iclass 16, count 2 2006.257.04:27:26.32#ibcon#about to write, iclass 16, count 2 2006.257.04:27:26.32#ibcon#wrote, iclass 16, count 2 2006.257.04:27:26.32#ibcon#about to read 3, iclass 16, count 2 2006.257.04:27:26.34#ibcon#read 3, iclass 16, count 2 2006.257.04:27:26.34#ibcon#about to read 4, iclass 16, count 2 2006.257.04:27:26.34#ibcon#read 4, iclass 16, count 2 2006.257.04:27:26.34#ibcon#about to read 5, iclass 16, count 2 2006.257.04:27:26.34#ibcon#read 5, iclass 16, count 2 2006.257.04:27:26.34#ibcon#about to read 6, iclass 16, count 2 2006.257.04:27:26.34#ibcon#read 6, iclass 16, count 2 2006.257.04:27:26.34#ibcon#end of sib2, iclass 16, count 2 2006.257.04:27:26.34#ibcon#*mode == 0, iclass 16, count 2 2006.257.04:27:26.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.04:27:26.34#ibcon#[27=AT02-05\r\n] 2006.257.04:27:26.34#ibcon#*before write, iclass 16, count 2 2006.257.04:27:26.34#ibcon#enter sib2, iclass 16, count 2 2006.257.04:27:26.34#ibcon#flushed, iclass 16, count 2 2006.257.04:27:26.34#ibcon#about to write, iclass 16, count 2 2006.257.04:27:26.34#ibcon#wrote, iclass 16, count 2 2006.257.04:27:26.34#ibcon#about to read 3, iclass 16, count 2 2006.257.04:27:26.37#ibcon#read 3, iclass 16, count 2 2006.257.04:27:26.37#ibcon#about to read 4, iclass 16, count 2 2006.257.04:27:26.37#ibcon#read 4, iclass 16, count 2 2006.257.04:27:26.37#ibcon#about to read 5, iclass 16, count 2 2006.257.04:27:26.37#ibcon#read 5, iclass 16, count 2 2006.257.04:27:26.37#ibcon#about to read 6, iclass 16, count 2 2006.257.04:27:26.37#ibcon#read 6, iclass 16, count 2 2006.257.04:27:26.37#ibcon#end of sib2, iclass 16, count 2 2006.257.04:27:26.37#ibcon#*after write, iclass 16, count 2 2006.257.04:27:26.37#ibcon#*before return 0, iclass 16, count 2 2006.257.04:27:26.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:26.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:27:26.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.04:27:26.37#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:26.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:26.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:26.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:26.49#ibcon#enter wrdev, iclass 16, count 0 2006.257.04:27:26.49#ibcon#first serial, iclass 16, count 0 2006.257.04:27:26.49#ibcon#enter sib2, iclass 16, count 0 2006.257.04:27:26.49#ibcon#flushed, iclass 16, count 0 2006.257.04:27:26.49#ibcon#about to write, iclass 16, count 0 2006.257.04:27:26.49#ibcon#wrote, iclass 16, count 0 2006.257.04:27:26.49#ibcon#about to read 3, iclass 16, count 0 2006.257.04:27:26.51#ibcon#read 3, iclass 16, count 0 2006.257.04:27:26.51#ibcon#about to read 4, iclass 16, count 0 2006.257.04:27:26.51#ibcon#read 4, iclass 16, count 0 2006.257.04:27:26.51#ibcon#about to read 5, iclass 16, count 0 2006.257.04:27:26.51#ibcon#read 5, iclass 16, count 0 2006.257.04:27:26.51#ibcon#about to read 6, iclass 16, count 0 2006.257.04:27:26.51#ibcon#read 6, iclass 16, count 0 2006.257.04:27:26.51#ibcon#end of sib2, iclass 16, count 0 2006.257.04:27:26.51#ibcon#*mode == 0, iclass 16, count 0 2006.257.04:27:26.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.04:27:26.51#ibcon#[27=USB\r\n] 2006.257.04:27:26.51#ibcon#*before write, iclass 16, count 0 2006.257.04:27:26.51#ibcon#enter sib2, iclass 16, count 0 2006.257.04:27:26.51#ibcon#flushed, iclass 16, count 0 2006.257.04:27:26.51#ibcon#about to write, iclass 16, count 0 2006.257.04:27:26.51#ibcon#wrote, iclass 16, count 0 2006.257.04:27:26.51#ibcon#about to read 3, iclass 16, count 0 2006.257.04:27:26.54#ibcon#read 3, iclass 16, count 0 2006.257.04:27:26.54#ibcon#about to read 4, iclass 16, count 0 2006.257.04:27:26.54#ibcon#read 4, iclass 16, count 0 2006.257.04:27:26.54#ibcon#about to read 5, iclass 16, count 0 2006.257.04:27:26.54#ibcon#read 5, iclass 16, count 0 2006.257.04:27:26.54#ibcon#about to read 6, iclass 16, count 0 2006.257.04:27:26.54#ibcon#read 6, iclass 16, count 0 2006.257.04:27:26.54#ibcon#end of sib2, iclass 16, count 0 2006.257.04:27:26.54#ibcon#*after write, iclass 16, count 0 2006.257.04:27:26.54#ibcon#*before return 0, iclass 16, count 0 2006.257.04:27:26.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:26.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:27:26.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.04:27:26.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.04:27:26.54$vck44/vblo=3,649.99 2006.257.04:27:26.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.04:27:26.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.04:27:26.54#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:26.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:26.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:26.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:26.54#ibcon#enter wrdev, iclass 18, count 0 2006.257.04:27:26.54#ibcon#first serial, iclass 18, count 0 2006.257.04:27:26.54#ibcon#enter sib2, iclass 18, count 0 2006.257.04:27:26.54#ibcon#flushed, iclass 18, count 0 2006.257.04:27:26.54#ibcon#about to write, iclass 18, count 0 2006.257.04:27:26.54#ibcon#wrote, iclass 18, count 0 2006.257.04:27:26.54#ibcon#about to read 3, iclass 18, count 0 2006.257.04:27:26.56#ibcon#read 3, iclass 18, count 0 2006.257.04:27:26.56#ibcon#about to read 4, iclass 18, count 0 2006.257.04:27:26.56#ibcon#read 4, iclass 18, count 0 2006.257.04:27:26.56#ibcon#about to read 5, iclass 18, count 0 2006.257.04:27:26.56#ibcon#read 5, iclass 18, count 0 2006.257.04:27:26.56#ibcon#about to read 6, iclass 18, count 0 2006.257.04:27:26.56#ibcon#read 6, iclass 18, count 0 2006.257.04:27:26.56#ibcon#end of sib2, iclass 18, count 0 2006.257.04:27:26.56#ibcon#*mode == 0, iclass 18, count 0 2006.257.04:27:26.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.04:27:26.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.04:27:26.56#ibcon#*before write, iclass 18, count 0 2006.257.04:27:26.56#ibcon#enter sib2, iclass 18, count 0 2006.257.04:27:26.56#ibcon#flushed, iclass 18, count 0 2006.257.04:27:26.56#ibcon#about to write, iclass 18, count 0 2006.257.04:27:26.56#ibcon#wrote, iclass 18, count 0 2006.257.04:27:26.56#ibcon#about to read 3, iclass 18, count 0 2006.257.04:27:26.60#ibcon#read 3, iclass 18, count 0 2006.257.04:27:26.60#ibcon#about to read 4, iclass 18, count 0 2006.257.04:27:26.60#ibcon#read 4, iclass 18, count 0 2006.257.04:27:26.60#ibcon#about to read 5, iclass 18, count 0 2006.257.04:27:26.60#ibcon#read 5, iclass 18, count 0 2006.257.04:27:26.60#ibcon#about to read 6, iclass 18, count 0 2006.257.04:27:26.60#ibcon#read 6, iclass 18, count 0 2006.257.04:27:26.60#ibcon#end of sib2, iclass 18, count 0 2006.257.04:27:26.60#ibcon#*after write, iclass 18, count 0 2006.257.04:27:26.60#ibcon#*before return 0, iclass 18, count 0 2006.257.04:27:26.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:26.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:27:26.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.04:27:26.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.04:27:26.60$vck44/vb=3,4 2006.257.04:27:26.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.04:27:26.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.04:27:26.60#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:26.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:26.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:26.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:26.66#ibcon#enter wrdev, iclass 20, count 2 2006.257.04:27:26.66#ibcon#first serial, iclass 20, count 2 2006.257.04:27:26.66#ibcon#enter sib2, iclass 20, count 2 2006.257.04:27:26.66#ibcon#flushed, iclass 20, count 2 2006.257.04:27:26.66#ibcon#about to write, iclass 20, count 2 2006.257.04:27:26.66#ibcon#wrote, iclass 20, count 2 2006.257.04:27:26.66#ibcon#about to read 3, iclass 20, count 2 2006.257.04:27:26.68#ibcon#read 3, iclass 20, count 2 2006.257.04:27:26.68#ibcon#about to read 4, iclass 20, count 2 2006.257.04:27:26.68#ibcon#read 4, iclass 20, count 2 2006.257.04:27:26.68#ibcon#about to read 5, iclass 20, count 2 2006.257.04:27:26.68#ibcon#read 5, iclass 20, count 2 2006.257.04:27:26.68#ibcon#about to read 6, iclass 20, count 2 2006.257.04:27:26.68#ibcon#read 6, iclass 20, count 2 2006.257.04:27:26.68#ibcon#end of sib2, iclass 20, count 2 2006.257.04:27:26.68#ibcon#*mode == 0, iclass 20, count 2 2006.257.04:27:26.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.04:27:26.68#ibcon#[27=AT03-04\r\n] 2006.257.04:27:26.68#ibcon#*before write, iclass 20, count 2 2006.257.04:27:26.68#ibcon#enter sib2, iclass 20, count 2 2006.257.04:27:26.68#ibcon#flushed, iclass 20, count 2 2006.257.04:27:26.68#ibcon#about to write, iclass 20, count 2 2006.257.04:27:26.68#ibcon#wrote, iclass 20, count 2 2006.257.04:27:26.68#ibcon#about to read 3, iclass 20, count 2 2006.257.04:27:26.71#ibcon#read 3, iclass 20, count 2 2006.257.04:27:26.71#ibcon#about to read 4, iclass 20, count 2 2006.257.04:27:26.71#ibcon#read 4, iclass 20, count 2 2006.257.04:27:26.71#ibcon#about to read 5, iclass 20, count 2 2006.257.04:27:26.71#ibcon#read 5, iclass 20, count 2 2006.257.04:27:26.71#ibcon#about to read 6, iclass 20, count 2 2006.257.04:27:26.71#ibcon#read 6, iclass 20, count 2 2006.257.04:27:26.71#ibcon#end of sib2, iclass 20, count 2 2006.257.04:27:26.71#ibcon#*after write, iclass 20, count 2 2006.257.04:27:26.71#ibcon#*before return 0, iclass 20, count 2 2006.257.04:27:26.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:26.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:27:26.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.04:27:26.71#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:26.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:26.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:26.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:26.83#ibcon#enter wrdev, iclass 20, count 0 2006.257.04:27:26.83#ibcon#first serial, iclass 20, count 0 2006.257.04:27:26.83#ibcon#enter sib2, iclass 20, count 0 2006.257.04:27:26.83#ibcon#flushed, iclass 20, count 0 2006.257.04:27:26.83#ibcon#about to write, iclass 20, count 0 2006.257.04:27:26.83#ibcon#wrote, iclass 20, count 0 2006.257.04:27:26.83#ibcon#about to read 3, iclass 20, count 0 2006.257.04:27:26.85#ibcon#read 3, iclass 20, count 0 2006.257.04:27:26.85#ibcon#about to read 4, iclass 20, count 0 2006.257.04:27:26.85#ibcon#read 4, iclass 20, count 0 2006.257.04:27:26.85#ibcon#about to read 5, iclass 20, count 0 2006.257.04:27:26.85#ibcon#read 5, iclass 20, count 0 2006.257.04:27:26.85#ibcon#about to read 6, iclass 20, count 0 2006.257.04:27:26.85#ibcon#read 6, iclass 20, count 0 2006.257.04:27:26.85#ibcon#end of sib2, iclass 20, count 0 2006.257.04:27:26.85#ibcon#*mode == 0, iclass 20, count 0 2006.257.04:27:26.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.04:27:26.85#ibcon#[27=USB\r\n] 2006.257.04:27:26.85#ibcon#*before write, iclass 20, count 0 2006.257.04:27:26.85#ibcon#enter sib2, iclass 20, count 0 2006.257.04:27:26.85#ibcon#flushed, iclass 20, count 0 2006.257.04:27:26.85#ibcon#about to write, iclass 20, count 0 2006.257.04:27:26.85#ibcon#wrote, iclass 20, count 0 2006.257.04:27:26.85#ibcon#about to read 3, iclass 20, count 0 2006.257.04:27:26.88#ibcon#read 3, iclass 20, count 0 2006.257.04:27:26.88#ibcon#about to read 4, iclass 20, count 0 2006.257.04:27:26.88#ibcon#read 4, iclass 20, count 0 2006.257.04:27:26.88#ibcon#about to read 5, iclass 20, count 0 2006.257.04:27:26.88#ibcon#read 5, iclass 20, count 0 2006.257.04:27:26.88#ibcon#about to read 6, iclass 20, count 0 2006.257.04:27:26.88#ibcon#read 6, iclass 20, count 0 2006.257.04:27:26.88#ibcon#end of sib2, iclass 20, count 0 2006.257.04:27:26.88#ibcon#*after write, iclass 20, count 0 2006.257.04:27:26.88#ibcon#*before return 0, iclass 20, count 0 2006.257.04:27:26.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:26.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:27:26.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.04:27:26.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.04:27:26.88$vck44/vblo=4,679.99 2006.257.04:27:26.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.04:27:26.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.04:27:26.88#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:26.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:26.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:26.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:26.88#ibcon#enter wrdev, iclass 22, count 0 2006.257.04:27:26.88#ibcon#first serial, iclass 22, count 0 2006.257.04:27:26.88#ibcon#enter sib2, iclass 22, count 0 2006.257.04:27:26.88#ibcon#flushed, iclass 22, count 0 2006.257.04:27:26.88#ibcon#about to write, iclass 22, count 0 2006.257.04:27:26.88#ibcon#wrote, iclass 22, count 0 2006.257.04:27:26.88#ibcon#about to read 3, iclass 22, count 0 2006.257.04:27:26.90#ibcon#read 3, iclass 22, count 0 2006.257.04:27:26.90#ibcon#about to read 4, iclass 22, count 0 2006.257.04:27:26.90#ibcon#read 4, iclass 22, count 0 2006.257.04:27:26.90#ibcon#about to read 5, iclass 22, count 0 2006.257.04:27:26.90#ibcon#read 5, iclass 22, count 0 2006.257.04:27:26.90#ibcon#about to read 6, iclass 22, count 0 2006.257.04:27:26.90#ibcon#read 6, iclass 22, count 0 2006.257.04:27:26.90#ibcon#end of sib2, iclass 22, count 0 2006.257.04:27:26.90#ibcon#*mode == 0, iclass 22, count 0 2006.257.04:27:26.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.04:27:26.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.04:27:26.90#ibcon#*before write, iclass 22, count 0 2006.257.04:27:26.90#ibcon#enter sib2, iclass 22, count 0 2006.257.04:27:26.90#ibcon#flushed, iclass 22, count 0 2006.257.04:27:26.90#ibcon#about to write, iclass 22, count 0 2006.257.04:27:26.90#ibcon#wrote, iclass 22, count 0 2006.257.04:27:26.90#ibcon#about to read 3, iclass 22, count 0 2006.257.04:27:26.94#ibcon#read 3, iclass 22, count 0 2006.257.04:27:26.94#ibcon#about to read 4, iclass 22, count 0 2006.257.04:27:26.94#ibcon#read 4, iclass 22, count 0 2006.257.04:27:26.94#ibcon#about to read 5, iclass 22, count 0 2006.257.04:27:26.94#ibcon#read 5, iclass 22, count 0 2006.257.04:27:26.94#ibcon#about to read 6, iclass 22, count 0 2006.257.04:27:26.94#ibcon#read 6, iclass 22, count 0 2006.257.04:27:26.94#ibcon#end of sib2, iclass 22, count 0 2006.257.04:27:26.94#ibcon#*after write, iclass 22, count 0 2006.257.04:27:26.94#ibcon#*before return 0, iclass 22, count 0 2006.257.04:27:26.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:26.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:27:26.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.04:27:26.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.04:27:26.94$vck44/vb=4,5 2006.257.04:27:26.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.04:27:26.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.04:27:26.94#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:26.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:27.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:27.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:27.00#ibcon#enter wrdev, iclass 24, count 2 2006.257.04:27:27.00#ibcon#first serial, iclass 24, count 2 2006.257.04:27:27.00#ibcon#enter sib2, iclass 24, count 2 2006.257.04:27:27.00#ibcon#flushed, iclass 24, count 2 2006.257.04:27:27.00#ibcon#about to write, iclass 24, count 2 2006.257.04:27:27.00#ibcon#wrote, iclass 24, count 2 2006.257.04:27:27.00#ibcon#about to read 3, iclass 24, count 2 2006.257.04:27:27.02#ibcon#read 3, iclass 24, count 2 2006.257.04:27:27.02#ibcon#about to read 4, iclass 24, count 2 2006.257.04:27:27.02#ibcon#read 4, iclass 24, count 2 2006.257.04:27:27.02#ibcon#about to read 5, iclass 24, count 2 2006.257.04:27:27.02#ibcon#read 5, iclass 24, count 2 2006.257.04:27:27.02#ibcon#about to read 6, iclass 24, count 2 2006.257.04:27:27.02#ibcon#read 6, iclass 24, count 2 2006.257.04:27:27.02#ibcon#end of sib2, iclass 24, count 2 2006.257.04:27:27.02#ibcon#*mode == 0, iclass 24, count 2 2006.257.04:27:27.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.04:27:27.02#ibcon#[27=AT04-05\r\n] 2006.257.04:27:27.02#ibcon#*before write, iclass 24, count 2 2006.257.04:27:27.02#ibcon#enter sib2, iclass 24, count 2 2006.257.04:27:27.02#ibcon#flushed, iclass 24, count 2 2006.257.04:27:27.02#ibcon#about to write, iclass 24, count 2 2006.257.04:27:27.02#ibcon#wrote, iclass 24, count 2 2006.257.04:27:27.02#ibcon#about to read 3, iclass 24, count 2 2006.257.04:27:27.05#ibcon#read 3, iclass 24, count 2 2006.257.04:27:27.05#ibcon#about to read 4, iclass 24, count 2 2006.257.04:27:27.05#ibcon#read 4, iclass 24, count 2 2006.257.04:27:27.05#ibcon#about to read 5, iclass 24, count 2 2006.257.04:27:27.05#ibcon#read 5, iclass 24, count 2 2006.257.04:27:27.05#ibcon#about to read 6, iclass 24, count 2 2006.257.04:27:27.05#ibcon#read 6, iclass 24, count 2 2006.257.04:27:27.05#ibcon#end of sib2, iclass 24, count 2 2006.257.04:27:27.05#ibcon#*after write, iclass 24, count 2 2006.257.04:27:27.05#ibcon#*before return 0, iclass 24, count 2 2006.257.04:27:27.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:27.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:27:27.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.04:27:27.05#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:27.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:27.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:27.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:27.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.04:27:27.17#ibcon#first serial, iclass 24, count 0 2006.257.04:27:27.17#ibcon#enter sib2, iclass 24, count 0 2006.257.04:27:27.17#ibcon#flushed, iclass 24, count 0 2006.257.04:27:27.17#ibcon#about to write, iclass 24, count 0 2006.257.04:27:27.17#ibcon#wrote, iclass 24, count 0 2006.257.04:27:27.17#ibcon#about to read 3, iclass 24, count 0 2006.257.04:27:27.19#ibcon#read 3, iclass 24, count 0 2006.257.04:27:27.19#ibcon#about to read 4, iclass 24, count 0 2006.257.04:27:27.19#ibcon#read 4, iclass 24, count 0 2006.257.04:27:27.19#ibcon#about to read 5, iclass 24, count 0 2006.257.04:27:27.19#ibcon#read 5, iclass 24, count 0 2006.257.04:27:27.19#ibcon#about to read 6, iclass 24, count 0 2006.257.04:27:27.19#ibcon#read 6, iclass 24, count 0 2006.257.04:27:27.19#ibcon#end of sib2, iclass 24, count 0 2006.257.04:27:27.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.04:27:27.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.04:27:27.19#ibcon#[27=USB\r\n] 2006.257.04:27:27.19#ibcon#*before write, iclass 24, count 0 2006.257.04:27:27.19#ibcon#enter sib2, iclass 24, count 0 2006.257.04:27:27.19#ibcon#flushed, iclass 24, count 0 2006.257.04:27:27.19#ibcon#about to write, iclass 24, count 0 2006.257.04:27:27.19#ibcon#wrote, iclass 24, count 0 2006.257.04:27:27.19#ibcon#about to read 3, iclass 24, count 0 2006.257.04:27:27.22#ibcon#read 3, iclass 24, count 0 2006.257.04:27:27.22#ibcon#about to read 4, iclass 24, count 0 2006.257.04:27:27.22#ibcon#read 4, iclass 24, count 0 2006.257.04:27:27.22#ibcon#about to read 5, iclass 24, count 0 2006.257.04:27:27.22#ibcon#read 5, iclass 24, count 0 2006.257.04:27:27.22#ibcon#about to read 6, iclass 24, count 0 2006.257.04:27:27.22#ibcon#read 6, iclass 24, count 0 2006.257.04:27:27.22#ibcon#end of sib2, iclass 24, count 0 2006.257.04:27:27.22#ibcon#*after write, iclass 24, count 0 2006.257.04:27:27.22#ibcon#*before return 0, iclass 24, count 0 2006.257.04:27:27.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:27.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:27:27.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.04:27:27.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.04:27:27.22$vck44/vblo=5,709.99 2006.257.04:27:27.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.04:27:27.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.04:27:27.22#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:27.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:27.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:27.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:27.22#ibcon#enter wrdev, iclass 26, count 0 2006.257.04:27:27.22#ibcon#first serial, iclass 26, count 0 2006.257.04:27:27.22#ibcon#enter sib2, iclass 26, count 0 2006.257.04:27:27.22#ibcon#flushed, iclass 26, count 0 2006.257.04:27:27.22#ibcon#about to write, iclass 26, count 0 2006.257.04:27:27.22#ibcon#wrote, iclass 26, count 0 2006.257.04:27:27.22#ibcon#about to read 3, iclass 26, count 0 2006.257.04:27:27.24#ibcon#read 3, iclass 26, count 0 2006.257.04:27:27.24#ibcon#about to read 4, iclass 26, count 0 2006.257.04:27:27.24#ibcon#read 4, iclass 26, count 0 2006.257.04:27:27.24#ibcon#about to read 5, iclass 26, count 0 2006.257.04:27:27.24#ibcon#read 5, iclass 26, count 0 2006.257.04:27:27.24#ibcon#about to read 6, iclass 26, count 0 2006.257.04:27:27.24#ibcon#read 6, iclass 26, count 0 2006.257.04:27:27.24#ibcon#end of sib2, iclass 26, count 0 2006.257.04:27:27.24#ibcon#*mode == 0, iclass 26, count 0 2006.257.04:27:27.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.04:27:27.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.04:27:27.24#ibcon#*before write, iclass 26, count 0 2006.257.04:27:27.24#ibcon#enter sib2, iclass 26, count 0 2006.257.04:27:27.24#ibcon#flushed, iclass 26, count 0 2006.257.04:27:27.24#ibcon#about to write, iclass 26, count 0 2006.257.04:27:27.24#ibcon#wrote, iclass 26, count 0 2006.257.04:27:27.24#ibcon#about to read 3, iclass 26, count 0 2006.257.04:27:27.28#ibcon#read 3, iclass 26, count 0 2006.257.04:27:27.28#ibcon#about to read 4, iclass 26, count 0 2006.257.04:27:27.28#ibcon#read 4, iclass 26, count 0 2006.257.04:27:27.28#ibcon#about to read 5, iclass 26, count 0 2006.257.04:27:27.28#ibcon#read 5, iclass 26, count 0 2006.257.04:27:27.28#ibcon#about to read 6, iclass 26, count 0 2006.257.04:27:27.28#ibcon#read 6, iclass 26, count 0 2006.257.04:27:27.28#ibcon#end of sib2, iclass 26, count 0 2006.257.04:27:27.28#ibcon#*after write, iclass 26, count 0 2006.257.04:27:27.28#ibcon#*before return 0, iclass 26, count 0 2006.257.04:27:27.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:27.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:27:27.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.04:27:27.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.04:27:27.28$vck44/vb=5,4 2006.257.04:27:27.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.04:27:27.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.04:27:27.28#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:27.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:27.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:27.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:27.34#ibcon#enter wrdev, iclass 28, count 2 2006.257.04:27:27.34#ibcon#first serial, iclass 28, count 2 2006.257.04:27:27.34#ibcon#enter sib2, iclass 28, count 2 2006.257.04:27:27.34#ibcon#flushed, iclass 28, count 2 2006.257.04:27:27.34#ibcon#about to write, iclass 28, count 2 2006.257.04:27:27.34#ibcon#wrote, iclass 28, count 2 2006.257.04:27:27.34#ibcon#about to read 3, iclass 28, count 2 2006.257.04:27:27.36#ibcon#read 3, iclass 28, count 2 2006.257.04:27:27.36#ibcon#about to read 4, iclass 28, count 2 2006.257.04:27:27.36#ibcon#read 4, iclass 28, count 2 2006.257.04:27:27.36#ibcon#about to read 5, iclass 28, count 2 2006.257.04:27:27.36#ibcon#read 5, iclass 28, count 2 2006.257.04:27:27.36#ibcon#about to read 6, iclass 28, count 2 2006.257.04:27:27.36#ibcon#read 6, iclass 28, count 2 2006.257.04:27:27.36#ibcon#end of sib2, iclass 28, count 2 2006.257.04:27:27.36#ibcon#*mode == 0, iclass 28, count 2 2006.257.04:27:27.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.04:27:27.36#ibcon#[27=AT05-04\r\n] 2006.257.04:27:27.36#ibcon#*before write, iclass 28, count 2 2006.257.04:27:27.36#ibcon#enter sib2, iclass 28, count 2 2006.257.04:27:27.36#ibcon#flushed, iclass 28, count 2 2006.257.04:27:27.36#ibcon#about to write, iclass 28, count 2 2006.257.04:27:27.36#ibcon#wrote, iclass 28, count 2 2006.257.04:27:27.36#ibcon#about to read 3, iclass 28, count 2 2006.257.04:27:27.39#ibcon#read 3, iclass 28, count 2 2006.257.04:27:27.39#ibcon#about to read 4, iclass 28, count 2 2006.257.04:27:27.39#ibcon#read 4, iclass 28, count 2 2006.257.04:27:27.39#ibcon#about to read 5, iclass 28, count 2 2006.257.04:27:27.39#ibcon#read 5, iclass 28, count 2 2006.257.04:27:27.39#ibcon#about to read 6, iclass 28, count 2 2006.257.04:27:27.39#ibcon#read 6, iclass 28, count 2 2006.257.04:27:27.39#ibcon#end of sib2, iclass 28, count 2 2006.257.04:27:27.39#ibcon#*after write, iclass 28, count 2 2006.257.04:27:27.39#ibcon#*before return 0, iclass 28, count 2 2006.257.04:27:27.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:27.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:27:27.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.04:27:27.39#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:27.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:27.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:27.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:27.51#ibcon#enter wrdev, iclass 28, count 0 2006.257.04:27:27.51#ibcon#first serial, iclass 28, count 0 2006.257.04:27:27.51#ibcon#enter sib2, iclass 28, count 0 2006.257.04:27:27.51#ibcon#flushed, iclass 28, count 0 2006.257.04:27:27.51#ibcon#about to write, iclass 28, count 0 2006.257.04:27:27.51#ibcon#wrote, iclass 28, count 0 2006.257.04:27:27.51#ibcon#about to read 3, iclass 28, count 0 2006.257.04:27:27.53#ibcon#read 3, iclass 28, count 0 2006.257.04:27:27.53#ibcon#about to read 4, iclass 28, count 0 2006.257.04:27:27.53#ibcon#read 4, iclass 28, count 0 2006.257.04:27:27.53#ibcon#about to read 5, iclass 28, count 0 2006.257.04:27:27.53#ibcon#read 5, iclass 28, count 0 2006.257.04:27:27.53#ibcon#about to read 6, iclass 28, count 0 2006.257.04:27:27.53#ibcon#read 6, iclass 28, count 0 2006.257.04:27:27.53#ibcon#end of sib2, iclass 28, count 0 2006.257.04:27:27.53#ibcon#*mode == 0, iclass 28, count 0 2006.257.04:27:27.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.04:27:27.53#ibcon#[27=USB\r\n] 2006.257.04:27:27.53#ibcon#*before write, iclass 28, count 0 2006.257.04:27:27.53#ibcon#enter sib2, iclass 28, count 0 2006.257.04:27:27.53#ibcon#flushed, iclass 28, count 0 2006.257.04:27:27.53#ibcon#about to write, iclass 28, count 0 2006.257.04:27:27.53#ibcon#wrote, iclass 28, count 0 2006.257.04:27:27.53#ibcon#about to read 3, iclass 28, count 0 2006.257.04:27:27.56#ibcon#read 3, iclass 28, count 0 2006.257.04:27:27.56#ibcon#about to read 4, iclass 28, count 0 2006.257.04:27:27.56#ibcon#read 4, iclass 28, count 0 2006.257.04:27:27.56#ibcon#about to read 5, iclass 28, count 0 2006.257.04:27:27.56#ibcon#read 5, iclass 28, count 0 2006.257.04:27:27.56#ibcon#about to read 6, iclass 28, count 0 2006.257.04:27:27.56#ibcon#read 6, iclass 28, count 0 2006.257.04:27:27.56#ibcon#end of sib2, iclass 28, count 0 2006.257.04:27:27.56#ibcon#*after write, iclass 28, count 0 2006.257.04:27:27.56#ibcon#*before return 0, iclass 28, count 0 2006.257.04:27:27.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:27.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:27:27.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.04:27:27.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.04:27:27.56$vck44/vblo=6,719.99 2006.257.04:27:27.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.04:27:27.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.04:27:27.56#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:27.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:27.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:27.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:27.56#ibcon#enter wrdev, iclass 30, count 0 2006.257.04:27:27.56#ibcon#first serial, iclass 30, count 0 2006.257.04:27:27.56#ibcon#enter sib2, iclass 30, count 0 2006.257.04:27:27.56#ibcon#flushed, iclass 30, count 0 2006.257.04:27:27.56#ibcon#about to write, iclass 30, count 0 2006.257.04:27:27.56#ibcon#wrote, iclass 30, count 0 2006.257.04:27:27.56#ibcon#about to read 3, iclass 30, count 0 2006.257.04:27:27.58#ibcon#read 3, iclass 30, count 0 2006.257.04:27:27.58#ibcon#about to read 4, iclass 30, count 0 2006.257.04:27:27.58#ibcon#read 4, iclass 30, count 0 2006.257.04:27:27.58#ibcon#about to read 5, iclass 30, count 0 2006.257.04:27:27.58#ibcon#read 5, iclass 30, count 0 2006.257.04:27:27.58#ibcon#about to read 6, iclass 30, count 0 2006.257.04:27:27.58#ibcon#read 6, iclass 30, count 0 2006.257.04:27:27.58#ibcon#end of sib2, iclass 30, count 0 2006.257.04:27:27.58#ibcon#*mode == 0, iclass 30, count 0 2006.257.04:27:27.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.04:27:27.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.04:27:27.58#ibcon#*before write, iclass 30, count 0 2006.257.04:27:27.58#ibcon#enter sib2, iclass 30, count 0 2006.257.04:27:27.58#ibcon#flushed, iclass 30, count 0 2006.257.04:27:27.58#ibcon#about to write, iclass 30, count 0 2006.257.04:27:27.58#ibcon#wrote, iclass 30, count 0 2006.257.04:27:27.58#ibcon#about to read 3, iclass 30, count 0 2006.257.04:27:27.62#ibcon#read 3, iclass 30, count 0 2006.257.04:27:27.62#ibcon#about to read 4, iclass 30, count 0 2006.257.04:27:27.62#ibcon#read 4, iclass 30, count 0 2006.257.04:27:27.62#ibcon#about to read 5, iclass 30, count 0 2006.257.04:27:27.62#ibcon#read 5, iclass 30, count 0 2006.257.04:27:27.62#ibcon#about to read 6, iclass 30, count 0 2006.257.04:27:27.62#ibcon#read 6, iclass 30, count 0 2006.257.04:27:27.62#ibcon#end of sib2, iclass 30, count 0 2006.257.04:27:27.62#ibcon#*after write, iclass 30, count 0 2006.257.04:27:27.62#ibcon#*before return 0, iclass 30, count 0 2006.257.04:27:27.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:27.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:27:27.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.04:27:27.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.04:27:27.62$vck44/vb=6,4 2006.257.04:27:27.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.04:27:27.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.04:27:27.62#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:27.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:27.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:27.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:27.68#ibcon#enter wrdev, iclass 32, count 2 2006.257.04:27:27.68#ibcon#first serial, iclass 32, count 2 2006.257.04:27:27.68#ibcon#enter sib2, iclass 32, count 2 2006.257.04:27:27.68#ibcon#flushed, iclass 32, count 2 2006.257.04:27:27.68#ibcon#about to write, iclass 32, count 2 2006.257.04:27:27.68#ibcon#wrote, iclass 32, count 2 2006.257.04:27:27.68#ibcon#about to read 3, iclass 32, count 2 2006.257.04:27:27.70#ibcon#read 3, iclass 32, count 2 2006.257.04:27:27.70#ibcon#about to read 4, iclass 32, count 2 2006.257.04:27:27.70#ibcon#read 4, iclass 32, count 2 2006.257.04:27:27.70#ibcon#about to read 5, iclass 32, count 2 2006.257.04:27:27.70#ibcon#read 5, iclass 32, count 2 2006.257.04:27:27.70#ibcon#about to read 6, iclass 32, count 2 2006.257.04:27:27.70#ibcon#read 6, iclass 32, count 2 2006.257.04:27:27.70#ibcon#end of sib2, iclass 32, count 2 2006.257.04:27:27.70#ibcon#*mode == 0, iclass 32, count 2 2006.257.04:27:27.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.04:27:27.70#ibcon#[27=AT06-04\r\n] 2006.257.04:27:27.70#ibcon#*before write, iclass 32, count 2 2006.257.04:27:27.70#ibcon#enter sib2, iclass 32, count 2 2006.257.04:27:27.70#ibcon#flushed, iclass 32, count 2 2006.257.04:27:27.70#ibcon#about to write, iclass 32, count 2 2006.257.04:27:27.70#ibcon#wrote, iclass 32, count 2 2006.257.04:27:27.70#ibcon#about to read 3, iclass 32, count 2 2006.257.04:27:27.73#ibcon#read 3, iclass 32, count 2 2006.257.04:27:27.73#ibcon#about to read 4, iclass 32, count 2 2006.257.04:27:27.73#ibcon#read 4, iclass 32, count 2 2006.257.04:27:27.73#ibcon#about to read 5, iclass 32, count 2 2006.257.04:27:27.73#ibcon#read 5, iclass 32, count 2 2006.257.04:27:27.73#ibcon#about to read 6, iclass 32, count 2 2006.257.04:27:27.73#ibcon#read 6, iclass 32, count 2 2006.257.04:27:27.73#ibcon#end of sib2, iclass 32, count 2 2006.257.04:27:27.73#ibcon#*after write, iclass 32, count 2 2006.257.04:27:27.73#ibcon#*before return 0, iclass 32, count 2 2006.257.04:27:27.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:27.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:27:27.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.04:27:27.73#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:27.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:27.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:27.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:27.85#ibcon#enter wrdev, iclass 32, count 0 2006.257.04:27:27.85#ibcon#first serial, iclass 32, count 0 2006.257.04:27:27.85#ibcon#enter sib2, iclass 32, count 0 2006.257.04:27:27.85#ibcon#flushed, iclass 32, count 0 2006.257.04:27:27.85#ibcon#about to write, iclass 32, count 0 2006.257.04:27:27.85#ibcon#wrote, iclass 32, count 0 2006.257.04:27:27.85#ibcon#about to read 3, iclass 32, count 0 2006.257.04:27:27.87#ibcon#read 3, iclass 32, count 0 2006.257.04:27:27.87#ibcon#about to read 4, iclass 32, count 0 2006.257.04:27:27.87#ibcon#read 4, iclass 32, count 0 2006.257.04:27:27.87#ibcon#about to read 5, iclass 32, count 0 2006.257.04:27:27.87#ibcon#read 5, iclass 32, count 0 2006.257.04:27:27.87#ibcon#about to read 6, iclass 32, count 0 2006.257.04:27:27.87#ibcon#read 6, iclass 32, count 0 2006.257.04:27:27.87#ibcon#end of sib2, iclass 32, count 0 2006.257.04:27:27.87#ibcon#*mode == 0, iclass 32, count 0 2006.257.04:27:27.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.04:27:27.87#ibcon#[27=USB\r\n] 2006.257.04:27:27.87#ibcon#*before write, iclass 32, count 0 2006.257.04:27:27.87#ibcon#enter sib2, iclass 32, count 0 2006.257.04:27:27.87#ibcon#flushed, iclass 32, count 0 2006.257.04:27:27.87#ibcon#about to write, iclass 32, count 0 2006.257.04:27:27.87#ibcon#wrote, iclass 32, count 0 2006.257.04:27:27.87#ibcon#about to read 3, iclass 32, count 0 2006.257.04:27:27.90#ibcon#read 3, iclass 32, count 0 2006.257.04:27:27.90#ibcon#about to read 4, iclass 32, count 0 2006.257.04:27:27.90#ibcon#read 4, iclass 32, count 0 2006.257.04:27:27.90#ibcon#about to read 5, iclass 32, count 0 2006.257.04:27:27.90#ibcon#read 5, iclass 32, count 0 2006.257.04:27:27.90#ibcon#about to read 6, iclass 32, count 0 2006.257.04:27:27.90#ibcon#read 6, iclass 32, count 0 2006.257.04:27:27.90#ibcon#end of sib2, iclass 32, count 0 2006.257.04:27:27.90#ibcon#*after write, iclass 32, count 0 2006.257.04:27:27.90#ibcon#*before return 0, iclass 32, count 0 2006.257.04:27:27.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:27.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:27:27.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.04:27:27.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.04:27:27.90$vck44/vblo=7,734.99 2006.257.04:27:27.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.04:27:27.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.04:27:27.90#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:27.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:27.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:27.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:27.90#ibcon#enter wrdev, iclass 34, count 0 2006.257.04:27:27.90#ibcon#first serial, iclass 34, count 0 2006.257.04:27:27.90#ibcon#enter sib2, iclass 34, count 0 2006.257.04:27:27.90#ibcon#flushed, iclass 34, count 0 2006.257.04:27:27.90#ibcon#about to write, iclass 34, count 0 2006.257.04:27:27.90#ibcon#wrote, iclass 34, count 0 2006.257.04:27:27.90#ibcon#about to read 3, iclass 34, count 0 2006.257.04:27:27.92#ibcon#read 3, iclass 34, count 0 2006.257.04:27:27.92#ibcon#about to read 4, iclass 34, count 0 2006.257.04:27:27.92#ibcon#read 4, iclass 34, count 0 2006.257.04:27:27.92#ibcon#about to read 5, iclass 34, count 0 2006.257.04:27:27.92#ibcon#read 5, iclass 34, count 0 2006.257.04:27:27.92#ibcon#about to read 6, iclass 34, count 0 2006.257.04:27:27.92#ibcon#read 6, iclass 34, count 0 2006.257.04:27:27.92#ibcon#end of sib2, iclass 34, count 0 2006.257.04:27:27.92#ibcon#*mode == 0, iclass 34, count 0 2006.257.04:27:27.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.04:27:27.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.04:27:27.92#ibcon#*before write, iclass 34, count 0 2006.257.04:27:27.92#ibcon#enter sib2, iclass 34, count 0 2006.257.04:27:27.92#ibcon#flushed, iclass 34, count 0 2006.257.04:27:27.92#ibcon#about to write, iclass 34, count 0 2006.257.04:27:27.92#ibcon#wrote, iclass 34, count 0 2006.257.04:27:27.92#ibcon#about to read 3, iclass 34, count 0 2006.257.04:27:27.96#ibcon#read 3, iclass 34, count 0 2006.257.04:27:27.96#ibcon#about to read 4, iclass 34, count 0 2006.257.04:27:27.96#ibcon#read 4, iclass 34, count 0 2006.257.04:27:27.96#ibcon#about to read 5, iclass 34, count 0 2006.257.04:27:27.96#ibcon#read 5, iclass 34, count 0 2006.257.04:27:27.96#ibcon#about to read 6, iclass 34, count 0 2006.257.04:27:27.96#ibcon#read 6, iclass 34, count 0 2006.257.04:27:27.96#ibcon#end of sib2, iclass 34, count 0 2006.257.04:27:27.96#ibcon#*after write, iclass 34, count 0 2006.257.04:27:27.96#ibcon#*before return 0, iclass 34, count 0 2006.257.04:27:27.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:27.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:27:27.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.04:27:27.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.04:27:27.96$vck44/vb=7,4 2006.257.04:27:27.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.04:27:27.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.04:27:27.96#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:27.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:28.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:28.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:28.02#ibcon#enter wrdev, iclass 36, count 2 2006.257.04:27:28.02#ibcon#first serial, iclass 36, count 2 2006.257.04:27:28.02#ibcon#enter sib2, iclass 36, count 2 2006.257.04:27:28.02#ibcon#flushed, iclass 36, count 2 2006.257.04:27:28.02#ibcon#about to write, iclass 36, count 2 2006.257.04:27:28.02#ibcon#wrote, iclass 36, count 2 2006.257.04:27:28.02#ibcon#about to read 3, iclass 36, count 2 2006.257.04:27:28.04#ibcon#read 3, iclass 36, count 2 2006.257.04:27:28.04#ibcon#about to read 4, iclass 36, count 2 2006.257.04:27:28.04#ibcon#read 4, iclass 36, count 2 2006.257.04:27:28.04#ibcon#about to read 5, iclass 36, count 2 2006.257.04:27:28.04#ibcon#read 5, iclass 36, count 2 2006.257.04:27:28.04#ibcon#about to read 6, iclass 36, count 2 2006.257.04:27:28.04#ibcon#read 6, iclass 36, count 2 2006.257.04:27:28.04#ibcon#end of sib2, iclass 36, count 2 2006.257.04:27:28.04#ibcon#*mode == 0, iclass 36, count 2 2006.257.04:27:28.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.04:27:28.04#ibcon#[27=AT07-04\r\n] 2006.257.04:27:28.04#ibcon#*before write, iclass 36, count 2 2006.257.04:27:28.04#ibcon#enter sib2, iclass 36, count 2 2006.257.04:27:28.04#ibcon#flushed, iclass 36, count 2 2006.257.04:27:28.04#ibcon#about to write, iclass 36, count 2 2006.257.04:27:28.04#ibcon#wrote, iclass 36, count 2 2006.257.04:27:28.04#ibcon#about to read 3, iclass 36, count 2 2006.257.04:27:28.07#ibcon#read 3, iclass 36, count 2 2006.257.04:27:28.07#ibcon#about to read 4, iclass 36, count 2 2006.257.04:27:28.07#ibcon#read 4, iclass 36, count 2 2006.257.04:27:28.07#ibcon#about to read 5, iclass 36, count 2 2006.257.04:27:28.07#ibcon#read 5, iclass 36, count 2 2006.257.04:27:28.07#ibcon#about to read 6, iclass 36, count 2 2006.257.04:27:28.07#ibcon#read 6, iclass 36, count 2 2006.257.04:27:28.07#ibcon#end of sib2, iclass 36, count 2 2006.257.04:27:28.07#ibcon#*after write, iclass 36, count 2 2006.257.04:27:28.07#ibcon#*before return 0, iclass 36, count 2 2006.257.04:27:28.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:28.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:27:28.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.04:27:28.07#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:28.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:28.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:28.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:28.19#ibcon#enter wrdev, iclass 36, count 0 2006.257.04:27:28.19#ibcon#first serial, iclass 36, count 0 2006.257.04:27:28.19#ibcon#enter sib2, iclass 36, count 0 2006.257.04:27:28.19#ibcon#flushed, iclass 36, count 0 2006.257.04:27:28.19#ibcon#about to write, iclass 36, count 0 2006.257.04:27:28.19#ibcon#wrote, iclass 36, count 0 2006.257.04:27:28.19#ibcon#about to read 3, iclass 36, count 0 2006.257.04:27:28.21#ibcon#read 3, iclass 36, count 0 2006.257.04:27:28.21#ibcon#about to read 4, iclass 36, count 0 2006.257.04:27:28.21#ibcon#read 4, iclass 36, count 0 2006.257.04:27:28.21#ibcon#about to read 5, iclass 36, count 0 2006.257.04:27:28.21#ibcon#read 5, iclass 36, count 0 2006.257.04:27:28.21#ibcon#about to read 6, iclass 36, count 0 2006.257.04:27:28.21#ibcon#read 6, iclass 36, count 0 2006.257.04:27:28.21#ibcon#end of sib2, iclass 36, count 0 2006.257.04:27:28.21#ibcon#*mode == 0, iclass 36, count 0 2006.257.04:27:28.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.04:27:28.21#ibcon#[27=USB\r\n] 2006.257.04:27:28.21#ibcon#*before write, iclass 36, count 0 2006.257.04:27:28.21#ibcon#enter sib2, iclass 36, count 0 2006.257.04:27:28.21#ibcon#flushed, iclass 36, count 0 2006.257.04:27:28.21#ibcon#about to write, iclass 36, count 0 2006.257.04:27:28.21#ibcon#wrote, iclass 36, count 0 2006.257.04:27:28.21#ibcon#about to read 3, iclass 36, count 0 2006.257.04:27:28.24#ibcon#read 3, iclass 36, count 0 2006.257.04:27:28.24#ibcon#about to read 4, iclass 36, count 0 2006.257.04:27:28.24#ibcon#read 4, iclass 36, count 0 2006.257.04:27:28.24#ibcon#about to read 5, iclass 36, count 0 2006.257.04:27:28.24#ibcon#read 5, iclass 36, count 0 2006.257.04:27:28.24#ibcon#about to read 6, iclass 36, count 0 2006.257.04:27:28.24#ibcon#read 6, iclass 36, count 0 2006.257.04:27:28.24#ibcon#end of sib2, iclass 36, count 0 2006.257.04:27:28.24#ibcon#*after write, iclass 36, count 0 2006.257.04:27:28.24#ibcon#*before return 0, iclass 36, count 0 2006.257.04:27:28.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:28.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:27:28.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.04:27:28.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.04:27:28.24$vck44/vblo=8,744.99 2006.257.04:27:28.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.04:27:28.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.04:27:28.24#ibcon#ireg 17 cls_cnt 0 2006.257.04:27:28.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:28.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:28.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:28.24#ibcon#enter wrdev, iclass 38, count 0 2006.257.04:27:28.24#ibcon#first serial, iclass 38, count 0 2006.257.04:27:28.24#ibcon#enter sib2, iclass 38, count 0 2006.257.04:27:28.24#ibcon#flushed, iclass 38, count 0 2006.257.04:27:28.24#ibcon#about to write, iclass 38, count 0 2006.257.04:27:28.24#ibcon#wrote, iclass 38, count 0 2006.257.04:27:28.24#ibcon#about to read 3, iclass 38, count 0 2006.257.04:27:28.26#ibcon#read 3, iclass 38, count 0 2006.257.04:27:28.26#ibcon#about to read 4, iclass 38, count 0 2006.257.04:27:28.26#ibcon#read 4, iclass 38, count 0 2006.257.04:27:28.26#ibcon#about to read 5, iclass 38, count 0 2006.257.04:27:28.26#ibcon#read 5, iclass 38, count 0 2006.257.04:27:28.26#ibcon#about to read 6, iclass 38, count 0 2006.257.04:27:28.26#ibcon#read 6, iclass 38, count 0 2006.257.04:27:28.26#ibcon#end of sib2, iclass 38, count 0 2006.257.04:27:28.26#ibcon#*mode == 0, iclass 38, count 0 2006.257.04:27:28.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.04:27:28.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.04:27:28.26#ibcon#*before write, iclass 38, count 0 2006.257.04:27:28.26#ibcon#enter sib2, iclass 38, count 0 2006.257.04:27:28.26#ibcon#flushed, iclass 38, count 0 2006.257.04:27:28.26#ibcon#about to write, iclass 38, count 0 2006.257.04:27:28.26#ibcon#wrote, iclass 38, count 0 2006.257.04:27:28.26#ibcon#about to read 3, iclass 38, count 0 2006.257.04:27:28.30#ibcon#read 3, iclass 38, count 0 2006.257.04:27:28.30#ibcon#about to read 4, iclass 38, count 0 2006.257.04:27:28.30#ibcon#read 4, iclass 38, count 0 2006.257.04:27:28.30#ibcon#about to read 5, iclass 38, count 0 2006.257.04:27:28.30#ibcon#read 5, iclass 38, count 0 2006.257.04:27:28.30#ibcon#about to read 6, iclass 38, count 0 2006.257.04:27:28.30#ibcon#read 6, iclass 38, count 0 2006.257.04:27:28.30#ibcon#end of sib2, iclass 38, count 0 2006.257.04:27:28.30#ibcon#*after write, iclass 38, count 0 2006.257.04:27:28.30#ibcon#*before return 0, iclass 38, count 0 2006.257.04:27:28.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:28.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:27:28.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.04:27:28.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.04:27:28.30$vck44/vb=8,4 2006.257.04:27:28.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.04:27:28.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.04:27:28.30#ibcon#ireg 11 cls_cnt 2 2006.257.04:27:28.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:28.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:28.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:28.36#ibcon#enter wrdev, iclass 40, count 2 2006.257.04:27:28.36#ibcon#first serial, iclass 40, count 2 2006.257.04:27:28.36#ibcon#enter sib2, iclass 40, count 2 2006.257.04:27:28.36#ibcon#flushed, iclass 40, count 2 2006.257.04:27:28.36#ibcon#about to write, iclass 40, count 2 2006.257.04:27:28.36#ibcon#wrote, iclass 40, count 2 2006.257.04:27:28.36#ibcon#about to read 3, iclass 40, count 2 2006.257.04:27:28.38#ibcon#read 3, iclass 40, count 2 2006.257.04:27:28.38#ibcon#about to read 4, iclass 40, count 2 2006.257.04:27:28.38#ibcon#read 4, iclass 40, count 2 2006.257.04:27:28.38#ibcon#about to read 5, iclass 40, count 2 2006.257.04:27:28.38#ibcon#read 5, iclass 40, count 2 2006.257.04:27:28.38#ibcon#about to read 6, iclass 40, count 2 2006.257.04:27:28.38#ibcon#read 6, iclass 40, count 2 2006.257.04:27:28.38#ibcon#end of sib2, iclass 40, count 2 2006.257.04:27:28.38#ibcon#*mode == 0, iclass 40, count 2 2006.257.04:27:28.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.04:27:28.38#ibcon#[27=AT08-04\r\n] 2006.257.04:27:28.38#ibcon#*before write, iclass 40, count 2 2006.257.04:27:28.38#ibcon#enter sib2, iclass 40, count 2 2006.257.04:27:28.38#ibcon#flushed, iclass 40, count 2 2006.257.04:27:28.38#ibcon#about to write, iclass 40, count 2 2006.257.04:27:28.38#ibcon#wrote, iclass 40, count 2 2006.257.04:27:28.38#ibcon#about to read 3, iclass 40, count 2 2006.257.04:27:28.41#ibcon#read 3, iclass 40, count 2 2006.257.04:27:28.41#ibcon#about to read 4, iclass 40, count 2 2006.257.04:27:28.41#ibcon#read 4, iclass 40, count 2 2006.257.04:27:28.41#ibcon#about to read 5, iclass 40, count 2 2006.257.04:27:28.41#ibcon#read 5, iclass 40, count 2 2006.257.04:27:28.41#ibcon#about to read 6, iclass 40, count 2 2006.257.04:27:28.41#ibcon#read 6, iclass 40, count 2 2006.257.04:27:28.41#ibcon#end of sib2, iclass 40, count 2 2006.257.04:27:28.41#ibcon#*after write, iclass 40, count 2 2006.257.04:27:28.41#ibcon#*before return 0, iclass 40, count 2 2006.257.04:27:28.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:28.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:27:28.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.04:27:28.41#ibcon#ireg 7 cls_cnt 0 2006.257.04:27:28.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:28.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:28.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:28.53#ibcon#enter wrdev, iclass 40, count 0 2006.257.04:27:28.53#ibcon#first serial, iclass 40, count 0 2006.257.04:27:28.53#ibcon#enter sib2, iclass 40, count 0 2006.257.04:27:28.53#ibcon#flushed, iclass 40, count 0 2006.257.04:27:28.53#ibcon#about to write, iclass 40, count 0 2006.257.04:27:28.53#ibcon#wrote, iclass 40, count 0 2006.257.04:27:28.53#ibcon#about to read 3, iclass 40, count 0 2006.257.04:27:28.55#ibcon#read 3, iclass 40, count 0 2006.257.04:27:28.55#ibcon#about to read 4, iclass 40, count 0 2006.257.04:27:28.55#ibcon#read 4, iclass 40, count 0 2006.257.04:27:28.55#ibcon#about to read 5, iclass 40, count 0 2006.257.04:27:28.55#ibcon#read 5, iclass 40, count 0 2006.257.04:27:28.55#ibcon#about to read 6, iclass 40, count 0 2006.257.04:27:28.55#ibcon#read 6, iclass 40, count 0 2006.257.04:27:28.55#ibcon#end of sib2, iclass 40, count 0 2006.257.04:27:28.55#ibcon#*mode == 0, iclass 40, count 0 2006.257.04:27:28.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.04:27:28.55#ibcon#[27=USB\r\n] 2006.257.04:27:28.55#ibcon#*before write, iclass 40, count 0 2006.257.04:27:28.55#ibcon#enter sib2, iclass 40, count 0 2006.257.04:27:28.55#ibcon#flushed, iclass 40, count 0 2006.257.04:27:28.55#ibcon#about to write, iclass 40, count 0 2006.257.04:27:28.55#ibcon#wrote, iclass 40, count 0 2006.257.04:27:28.55#ibcon#about to read 3, iclass 40, count 0 2006.257.04:27:28.58#ibcon#read 3, iclass 40, count 0 2006.257.04:27:28.58#ibcon#about to read 4, iclass 40, count 0 2006.257.04:27:28.58#ibcon#read 4, iclass 40, count 0 2006.257.04:27:28.58#ibcon#about to read 5, iclass 40, count 0 2006.257.04:27:28.58#ibcon#read 5, iclass 40, count 0 2006.257.04:27:28.58#ibcon#about to read 6, iclass 40, count 0 2006.257.04:27:28.58#ibcon#read 6, iclass 40, count 0 2006.257.04:27:28.58#ibcon#end of sib2, iclass 40, count 0 2006.257.04:27:28.58#ibcon#*after write, iclass 40, count 0 2006.257.04:27:28.58#ibcon#*before return 0, iclass 40, count 0 2006.257.04:27:28.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:28.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:27:28.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.04:27:28.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.04:27:28.58$vck44/vabw=wide 2006.257.04:27:28.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.04:27:28.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.04:27:28.58#ibcon#ireg 8 cls_cnt 0 2006.257.04:27:28.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:28.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:28.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:28.58#ibcon#enter wrdev, iclass 4, count 0 2006.257.04:27:28.58#ibcon#first serial, iclass 4, count 0 2006.257.04:27:28.58#ibcon#enter sib2, iclass 4, count 0 2006.257.04:27:28.58#ibcon#flushed, iclass 4, count 0 2006.257.04:27:28.58#ibcon#about to write, iclass 4, count 0 2006.257.04:27:28.58#ibcon#wrote, iclass 4, count 0 2006.257.04:27:28.58#ibcon#about to read 3, iclass 4, count 0 2006.257.04:27:28.60#ibcon#read 3, iclass 4, count 0 2006.257.04:27:28.60#ibcon#about to read 4, iclass 4, count 0 2006.257.04:27:28.60#ibcon#read 4, iclass 4, count 0 2006.257.04:27:28.60#ibcon#about to read 5, iclass 4, count 0 2006.257.04:27:28.60#ibcon#read 5, iclass 4, count 0 2006.257.04:27:28.60#ibcon#about to read 6, iclass 4, count 0 2006.257.04:27:28.60#ibcon#read 6, iclass 4, count 0 2006.257.04:27:28.60#ibcon#end of sib2, iclass 4, count 0 2006.257.04:27:28.60#ibcon#*mode == 0, iclass 4, count 0 2006.257.04:27:28.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.04:27:28.60#ibcon#[25=BW32\r\n] 2006.257.04:27:28.60#ibcon#*before write, iclass 4, count 0 2006.257.04:27:28.60#ibcon#enter sib2, iclass 4, count 0 2006.257.04:27:28.60#ibcon#flushed, iclass 4, count 0 2006.257.04:27:28.60#ibcon#about to write, iclass 4, count 0 2006.257.04:27:28.60#ibcon#wrote, iclass 4, count 0 2006.257.04:27:28.60#ibcon#about to read 3, iclass 4, count 0 2006.257.04:27:28.63#ibcon#read 3, iclass 4, count 0 2006.257.04:27:28.63#ibcon#about to read 4, iclass 4, count 0 2006.257.04:27:28.63#ibcon#read 4, iclass 4, count 0 2006.257.04:27:28.63#ibcon#about to read 5, iclass 4, count 0 2006.257.04:27:28.63#ibcon#read 5, iclass 4, count 0 2006.257.04:27:28.63#ibcon#about to read 6, iclass 4, count 0 2006.257.04:27:28.63#ibcon#read 6, iclass 4, count 0 2006.257.04:27:28.63#ibcon#end of sib2, iclass 4, count 0 2006.257.04:27:28.63#ibcon#*after write, iclass 4, count 0 2006.257.04:27:28.63#ibcon#*before return 0, iclass 4, count 0 2006.257.04:27:28.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:28.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:27:28.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.04:27:28.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.04:27:28.63$vck44/vbbw=wide 2006.257.04:27:28.63#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.04:27:28.63#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.04:27:28.63#ibcon#ireg 8 cls_cnt 0 2006.257.04:27:28.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:27:28.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:27:28.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:27:28.70#ibcon#enter wrdev, iclass 6, count 0 2006.257.04:27:28.70#ibcon#first serial, iclass 6, count 0 2006.257.04:27:28.70#ibcon#enter sib2, iclass 6, count 0 2006.257.04:27:28.70#ibcon#flushed, iclass 6, count 0 2006.257.04:27:28.70#ibcon#about to write, iclass 6, count 0 2006.257.04:27:28.70#ibcon#wrote, iclass 6, count 0 2006.257.04:27:28.70#ibcon#about to read 3, iclass 6, count 0 2006.257.04:27:28.72#ibcon#read 3, iclass 6, count 0 2006.257.04:27:28.72#ibcon#about to read 4, iclass 6, count 0 2006.257.04:27:28.72#ibcon#read 4, iclass 6, count 0 2006.257.04:27:28.72#ibcon#about to read 5, iclass 6, count 0 2006.257.04:27:28.72#ibcon#read 5, iclass 6, count 0 2006.257.04:27:28.72#ibcon#about to read 6, iclass 6, count 0 2006.257.04:27:28.72#ibcon#read 6, iclass 6, count 0 2006.257.04:27:28.72#ibcon#end of sib2, iclass 6, count 0 2006.257.04:27:28.72#ibcon#*mode == 0, iclass 6, count 0 2006.257.04:27:28.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.04:27:28.72#ibcon#[27=BW32\r\n] 2006.257.04:27:28.72#ibcon#*before write, iclass 6, count 0 2006.257.04:27:28.72#ibcon#enter sib2, iclass 6, count 0 2006.257.04:27:28.72#ibcon#flushed, iclass 6, count 0 2006.257.04:27:28.72#ibcon#about to write, iclass 6, count 0 2006.257.04:27:28.72#ibcon#wrote, iclass 6, count 0 2006.257.04:27:28.72#ibcon#about to read 3, iclass 6, count 0 2006.257.04:27:28.75#ibcon#read 3, iclass 6, count 0 2006.257.04:27:28.75#ibcon#about to read 4, iclass 6, count 0 2006.257.04:27:28.75#ibcon#read 4, iclass 6, count 0 2006.257.04:27:28.75#ibcon#about to read 5, iclass 6, count 0 2006.257.04:27:28.75#ibcon#read 5, iclass 6, count 0 2006.257.04:27:28.75#ibcon#about to read 6, iclass 6, count 0 2006.257.04:27:28.75#ibcon#read 6, iclass 6, count 0 2006.257.04:27:28.75#ibcon#end of sib2, iclass 6, count 0 2006.257.04:27:28.75#ibcon#*after write, iclass 6, count 0 2006.257.04:27:28.75#ibcon#*before return 0, iclass 6, count 0 2006.257.04:27:28.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:27:28.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:27:28.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.04:27:28.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.04:27:28.75$setupk4/ifdk4 2006.257.04:27:28.75$ifdk4/lo= 2006.257.04:27:28.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.04:27:28.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.04:27:28.75$ifdk4/patch= 2006.257.04:27:28.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.04:27:28.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.04:27:28.75$setupk4/!*+20s 2006.257.04:27:31.64#abcon#<5=/14 2.1 6.3 19.50 931011.9\r\n> 2006.257.04:27:31.66#abcon#{5=INTERFACE CLEAR} 2006.257.04:27:31.72#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:27:41.81#abcon#<5=/14 2.1 6.2 19.50 931012.0\r\n> 2006.257.04:27:41.83#abcon#{5=INTERFACE CLEAR} 2006.257.04:27:41.89#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:27:43.26$setupk4/"tpicd 2006.257.04:27:43.26$setupk4/echo=off 2006.257.04:27:43.26$setupk4/xlog=off 2006.257.04:27:43.26:!2006.257.04:30:51 2006.257.04:28:14.14#trakl#Source acquired 2006.257.04:28:16.14#flagr#flagr/antenna,acquired 2006.257.04:30:51.00:preob 2006.257.04:30:51.14/onsource/TRACKING 2006.257.04:30:51.14:!2006.257.04:31:01 2006.257.04:31:01.00:"tape 2006.257.04:31:01.00:"st=record 2006.257.04:31:01.00:data_valid=on 2006.257.04:31:01.00:midob 2006.257.04:31:01.14/onsource/TRACKING 2006.257.04:31:01.14/wx/19.51,1012.0,93 2006.257.04:31:01.23/cable/+6.4830E-03 2006.257.04:31:02.32/va/01,08,usb,yes,33,36 2006.257.04:31:02.32/va/02,07,usb,yes,36,37 2006.257.04:31:02.32/va/03,08,usb,yes,33,34 2006.257.04:31:02.32/va/04,07,usb,yes,37,39 2006.257.04:31:02.32/va/05,04,usb,yes,34,34 2006.257.04:31:02.32/va/06,04,usb,yes,37,37 2006.257.04:31:02.32/va/07,04,usb,yes,38,39 2006.257.04:31:02.32/va/08,04,usb,yes,32,39 2006.257.04:31:02.55/valo/01,524.99,yes,locked 2006.257.04:31:02.55/valo/02,534.99,yes,locked 2006.257.04:31:02.55/valo/03,564.99,yes,locked 2006.257.04:31:02.55/valo/04,624.99,yes,locked 2006.257.04:31:02.55/valo/05,734.99,yes,locked 2006.257.04:31:02.55/valo/06,814.99,yes,locked 2006.257.04:31:02.55/valo/07,864.99,yes,locked 2006.257.04:31:02.55/valo/08,884.99,yes,locked 2006.257.04:31:03.64/vb/01,04,usb,yes,32,30 2006.257.04:31:03.64/vb/02,05,usb,yes,30,30 2006.257.04:31:03.64/vb/03,04,usb,yes,31,34 2006.257.04:31:03.64/vb/04,05,usb,yes,31,30 2006.257.04:31:03.64/vb/05,04,usb,yes,28,30 2006.257.04:31:03.64/vb/06,04,usb,yes,32,28 2006.257.04:31:03.64/vb/07,04,usb,yes,32,32 2006.257.04:31:03.64/vb/08,04,usb,yes,29,33 2006.257.04:31:03.87/vblo/01,629.99,yes,locked 2006.257.04:31:03.87/vblo/02,634.99,yes,locked 2006.257.04:31:03.87/vblo/03,649.99,yes,locked 2006.257.04:31:03.87/vblo/04,679.99,yes,locked 2006.257.04:31:03.87/vblo/05,709.99,yes,locked 2006.257.04:31:03.87/vblo/06,719.99,yes,locked 2006.257.04:31:03.87/vblo/07,734.99,yes,locked 2006.257.04:31:03.87/vblo/08,744.99,yes,locked 2006.257.04:31:04.02/vabw/8 2006.257.04:31:04.17/vbbw/8 2006.257.04:31:04.26/xfe/off,on,16.7 2006.257.04:31:04.64/ifatt/23,28,28,28 2006.257.04:31:05.07/fmout-gps/S +4.55E-07 2006.257.04:31:05.11:!2006.257.04:31:41 2006.257.04:31:41.00:data_valid=off 2006.257.04:31:41.00:"et 2006.257.04:31:41.00:!+3s 2006.257.04:31:44.01:"tape 2006.257.04:31:44.01:postob 2006.257.04:31:44.15/cable/+6.4835E-03 2006.257.04:31:44.15/wx/19.51,1012.0,93 2006.257.04:31:45.07/fmout-gps/S +4.55E-07 2006.257.04:31:45.07:scan_name=257-0433,jd0609,360 2006.257.04:31:45.07:source=1622-253,162546.89,-252738.3,2000.0,cw 2006.257.04:31:46.14#flagr#flagr/antenna,new-source 2006.257.04:31:46.14:checkk5 2006.257.04:31:46.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.04:31:46.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.04:31:47.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.04:31:47.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.04:31:48.14/chk_obsdata//k5ts1/T2570431??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.04:31:48.54/chk_obsdata//k5ts2/T2570431??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.04:31:48.97/chk_obsdata//k5ts3/T2570431??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.04:31:49.36/chk_obsdata//k5ts4/T2570431??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.04:31:50.08/k5log//k5ts1_log_newline 2006.257.04:31:50.78/k5log//k5ts2_log_newline 2006.257.04:31:51.53/k5log//k5ts3_log_newline 2006.257.04:31:52.27/k5log//k5ts4_log_newline 2006.257.04:31:52.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.04:31:52.29:setupk4=1 2006.257.04:31:52.29$setupk4/echo=on 2006.257.04:31:52.29$setupk4/pcalon 2006.257.04:31:52.29$pcalon/"no phase cal control is implemented here 2006.257.04:31:52.29$setupk4/"tpicd=stop 2006.257.04:31:52.29$setupk4/"rec=synch_on 2006.257.04:31:52.29$setupk4/"rec_mode=128 2006.257.04:31:52.29$setupk4/!* 2006.257.04:31:52.29$setupk4/recpk4 2006.257.04:31:52.29$recpk4/recpatch= 2006.257.04:31:52.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.04:31:52.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.04:31:52.29$setupk4/vck44 2006.257.04:31:52.29$vck44/valo=1,524.99 2006.257.04:31:52.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.04:31:52.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.04:31:52.29#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:52.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:52.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:52.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:52.29#ibcon#enter wrdev, iclass 7, count 0 2006.257.04:31:52.29#ibcon#first serial, iclass 7, count 0 2006.257.04:31:52.29#ibcon#enter sib2, iclass 7, count 0 2006.257.04:31:52.29#ibcon#flushed, iclass 7, count 0 2006.257.04:31:52.29#ibcon#about to write, iclass 7, count 0 2006.257.04:31:52.29#ibcon#wrote, iclass 7, count 0 2006.257.04:31:52.29#ibcon#about to read 3, iclass 7, count 0 2006.257.04:31:52.31#ibcon#read 3, iclass 7, count 0 2006.257.04:31:52.31#ibcon#about to read 4, iclass 7, count 0 2006.257.04:31:52.31#ibcon#read 4, iclass 7, count 0 2006.257.04:31:52.31#ibcon#about to read 5, iclass 7, count 0 2006.257.04:31:52.31#ibcon#read 5, iclass 7, count 0 2006.257.04:31:52.31#ibcon#about to read 6, iclass 7, count 0 2006.257.04:31:52.31#ibcon#read 6, iclass 7, count 0 2006.257.04:31:52.31#ibcon#end of sib2, iclass 7, count 0 2006.257.04:31:52.31#ibcon#*mode == 0, iclass 7, count 0 2006.257.04:31:52.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.04:31:52.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.04:31:52.31#ibcon#*before write, iclass 7, count 0 2006.257.04:31:52.31#ibcon#enter sib2, iclass 7, count 0 2006.257.04:31:52.31#ibcon#flushed, iclass 7, count 0 2006.257.04:31:52.31#ibcon#about to write, iclass 7, count 0 2006.257.04:31:52.31#ibcon#wrote, iclass 7, count 0 2006.257.04:31:52.31#ibcon#about to read 3, iclass 7, count 0 2006.257.04:31:52.36#ibcon#read 3, iclass 7, count 0 2006.257.04:31:52.36#ibcon#about to read 4, iclass 7, count 0 2006.257.04:31:52.36#ibcon#read 4, iclass 7, count 0 2006.257.04:31:52.36#ibcon#about to read 5, iclass 7, count 0 2006.257.04:31:52.36#ibcon#read 5, iclass 7, count 0 2006.257.04:31:52.36#ibcon#about to read 6, iclass 7, count 0 2006.257.04:31:52.36#ibcon#read 6, iclass 7, count 0 2006.257.04:31:52.36#ibcon#end of sib2, iclass 7, count 0 2006.257.04:31:52.36#ibcon#*after write, iclass 7, count 0 2006.257.04:31:52.36#ibcon#*before return 0, iclass 7, count 0 2006.257.04:31:52.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:52.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:52.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.04:31:52.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.04:31:52.36$vck44/va=1,8 2006.257.04:31:52.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.04:31:52.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.04:31:52.36#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:52.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:52.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:52.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:52.36#ibcon#enter wrdev, iclass 11, count 2 2006.257.04:31:52.36#ibcon#first serial, iclass 11, count 2 2006.257.04:31:52.36#ibcon#enter sib2, iclass 11, count 2 2006.257.04:31:52.36#ibcon#flushed, iclass 11, count 2 2006.257.04:31:52.36#ibcon#about to write, iclass 11, count 2 2006.257.04:31:52.36#ibcon#wrote, iclass 11, count 2 2006.257.04:31:52.36#ibcon#about to read 3, iclass 11, count 2 2006.257.04:31:52.38#ibcon#read 3, iclass 11, count 2 2006.257.04:31:52.38#ibcon#about to read 4, iclass 11, count 2 2006.257.04:31:52.38#ibcon#read 4, iclass 11, count 2 2006.257.04:31:52.38#ibcon#about to read 5, iclass 11, count 2 2006.257.04:31:52.38#ibcon#read 5, iclass 11, count 2 2006.257.04:31:52.38#ibcon#about to read 6, iclass 11, count 2 2006.257.04:31:52.38#ibcon#read 6, iclass 11, count 2 2006.257.04:31:52.38#ibcon#end of sib2, iclass 11, count 2 2006.257.04:31:52.38#ibcon#*mode == 0, iclass 11, count 2 2006.257.04:31:52.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.04:31:52.38#ibcon#[25=AT01-08\r\n] 2006.257.04:31:52.38#ibcon#*before write, iclass 11, count 2 2006.257.04:31:52.38#ibcon#enter sib2, iclass 11, count 2 2006.257.04:31:52.38#ibcon#flushed, iclass 11, count 2 2006.257.04:31:52.38#ibcon#about to write, iclass 11, count 2 2006.257.04:31:52.38#ibcon#wrote, iclass 11, count 2 2006.257.04:31:52.38#ibcon#about to read 3, iclass 11, count 2 2006.257.04:31:52.41#ibcon#read 3, iclass 11, count 2 2006.257.04:31:52.41#ibcon#about to read 4, iclass 11, count 2 2006.257.04:31:52.41#ibcon#read 4, iclass 11, count 2 2006.257.04:31:52.41#ibcon#about to read 5, iclass 11, count 2 2006.257.04:31:52.41#ibcon#read 5, iclass 11, count 2 2006.257.04:31:52.41#ibcon#about to read 6, iclass 11, count 2 2006.257.04:31:52.41#ibcon#read 6, iclass 11, count 2 2006.257.04:31:52.41#ibcon#end of sib2, iclass 11, count 2 2006.257.04:31:52.41#ibcon#*after write, iclass 11, count 2 2006.257.04:31:52.41#ibcon#*before return 0, iclass 11, count 2 2006.257.04:31:52.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:52.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:52.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.04:31:52.41#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:52.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:52.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:52.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:52.53#ibcon#enter wrdev, iclass 11, count 0 2006.257.04:31:52.53#ibcon#first serial, iclass 11, count 0 2006.257.04:31:52.53#ibcon#enter sib2, iclass 11, count 0 2006.257.04:31:52.53#ibcon#flushed, iclass 11, count 0 2006.257.04:31:52.53#ibcon#about to write, iclass 11, count 0 2006.257.04:31:52.53#ibcon#wrote, iclass 11, count 0 2006.257.04:31:52.53#ibcon#about to read 3, iclass 11, count 0 2006.257.04:31:52.55#ibcon#read 3, iclass 11, count 0 2006.257.04:31:52.55#ibcon#about to read 4, iclass 11, count 0 2006.257.04:31:52.55#ibcon#read 4, iclass 11, count 0 2006.257.04:31:52.55#ibcon#about to read 5, iclass 11, count 0 2006.257.04:31:52.55#ibcon#read 5, iclass 11, count 0 2006.257.04:31:52.55#ibcon#about to read 6, iclass 11, count 0 2006.257.04:31:52.55#ibcon#read 6, iclass 11, count 0 2006.257.04:31:52.55#ibcon#end of sib2, iclass 11, count 0 2006.257.04:31:52.55#ibcon#*mode == 0, iclass 11, count 0 2006.257.04:31:52.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.04:31:52.55#ibcon#[25=USB\r\n] 2006.257.04:31:52.55#ibcon#*before write, iclass 11, count 0 2006.257.04:31:52.55#ibcon#enter sib2, iclass 11, count 0 2006.257.04:31:52.55#ibcon#flushed, iclass 11, count 0 2006.257.04:31:52.55#ibcon#about to write, iclass 11, count 0 2006.257.04:31:52.55#ibcon#wrote, iclass 11, count 0 2006.257.04:31:52.55#ibcon#about to read 3, iclass 11, count 0 2006.257.04:31:52.58#ibcon#read 3, iclass 11, count 0 2006.257.04:31:52.58#ibcon#about to read 4, iclass 11, count 0 2006.257.04:31:52.58#ibcon#read 4, iclass 11, count 0 2006.257.04:31:52.58#ibcon#about to read 5, iclass 11, count 0 2006.257.04:31:52.58#ibcon#read 5, iclass 11, count 0 2006.257.04:31:52.58#ibcon#about to read 6, iclass 11, count 0 2006.257.04:31:52.58#ibcon#read 6, iclass 11, count 0 2006.257.04:31:52.58#ibcon#end of sib2, iclass 11, count 0 2006.257.04:31:52.58#ibcon#*after write, iclass 11, count 0 2006.257.04:31:52.58#ibcon#*before return 0, iclass 11, count 0 2006.257.04:31:52.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:52.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:52.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.04:31:52.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.04:31:52.58$vck44/valo=2,534.99 2006.257.04:31:52.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.04:31:52.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.04:31:52.58#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:52.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:52.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:52.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:52.58#ibcon#enter wrdev, iclass 13, count 0 2006.257.04:31:52.58#ibcon#first serial, iclass 13, count 0 2006.257.04:31:52.58#ibcon#enter sib2, iclass 13, count 0 2006.257.04:31:52.58#ibcon#flushed, iclass 13, count 0 2006.257.04:31:52.58#ibcon#about to write, iclass 13, count 0 2006.257.04:31:52.58#ibcon#wrote, iclass 13, count 0 2006.257.04:31:52.58#ibcon#about to read 3, iclass 13, count 0 2006.257.04:31:52.60#ibcon#read 3, iclass 13, count 0 2006.257.04:31:52.60#ibcon#about to read 4, iclass 13, count 0 2006.257.04:31:52.60#ibcon#read 4, iclass 13, count 0 2006.257.04:31:52.60#ibcon#about to read 5, iclass 13, count 0 2006.257.04:31:52.60#ibcon#read 5, iclass 13, count 0 2006.257.04:31:52.60#ibcon#about to read 6, iclass 13, count 0 2006.257.04:31:52.60#ibcon#read 6, iclass 13, count 0 2006.257.04:31:52.60#ibcon#end of sib2, iclass 13, count 0 2006.257.04:31:52.60#ibcon#*mode == 0, iclass 13, count 0 2006.257.04:31:52.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.04:31:52.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.04:31:52.60#ibcon#*before write, iclass 13, count 0 2006.257.04:31:52.60#ibcon#enter sib2, iclass 13, count 0 2006.257.04:31:52.60#ibcon#flushed, iclass 13, count 0 2006.257.04:31:52.60#ibcon#about to write, iclass 13, count 0 2006.257.04:31:52.60#ibcon#wrote, iclass 13, count 0 2006.257.04:31:52.60#ibcon#about to read 3, iclass 13, count 0 2006.257.04:31:52.64#ibcon#read 3, iclass 13, count 0 2006.257.04:31:52.64#ibcon#about to read 4, iclass 13, count 0 2006.257.04:31:52.64#ibcon#read 4, iclass 13, count 0 2006.257.04:31:52.64#ibcon#about to read 5, iclass 13, count 0 2006.257.04:31:52.64#ibcon#read 5, iclass 13, count 0 2006.257.04:31:52.64#ibcon#about to read 6, iclass 13, count 0 2006.257.04:31:52.64#ibcon#read 6, iclass 13, count 0 2006.257.04:31:52.64#ibcon#end of sib2, iclass 13, count 0 2006.257.04:31:52.64#ibcon#*after write, iclass 13, count 0 2006.257.04:31:52.64#ibcon#*before return 0, iclass 13, count 0 2006.257.04:31:52.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:52.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:52.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.04:31:52.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.04:31:52.64$vck44/va=2,7 2006.257.04:31:52.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.04:31:52.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.04:31:52.64#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:52.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:52.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:52.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:52.70#ibcon#enter wrdev, iclass 15, count 2 2006.257.04:31:52.70#ibcon#first serial, iclass 15, count 2 2006.257.04:31:52.70#ibcon#enter sib2, iclass 15, count 2 2006.257.04:31:52.70#ibcon#flushed, iclass 15, count 2 2006.257.04:31:52.70#ibcon#about to write, iclass 15, count 2 2006.257.04:31:52.70#ibcon#wrote, iclass 15, count 2 2006.257.04:31:52.70#ibcon#about to read 3, iclass 15, count 2 2006.257.04:31:52.72#ibcon#read 3, iclass 15, count 2 2006.257.04:31:52.72#ibcon#about to read 4, iclass 15, count 2 2006.257.04:31:52.72#ibcon#read 4, iclass 15, count 2 2006.257.04:31:52.72#ibcon#about to read 5, iclass 15, count 2 2006.257.04:31:52.72#ibcon#read 5, iclass 15, count 2 2006.257.04:31:52.72#ibcon#about to read 6, iclass 15, count 2 2006.257.04:31:52.72#ibcon#read 6, iclass 15, count 2 2006.257.04:31:52.72#ibcon#end of sib2, iclass 15, count 2 2006.257.04:31:52.72#ibcon#*mode == 0, iclass 15, count 2 2006.257.04:31:52.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.04:31:52.72#ibcon#[25=AT02-07\r\n] 2006.257.04:31:52.72#ibcon#*before write, iclass 15, count 2 2006.257.04:31:52.72#ibcon#enter sib2, iclass 15, count 2 2006.257.04:31:52.72#ibcon#flushed, iclass 15, count 2 2006.257.04:31:52.72#ibcon#about to write, iclass 15, count 2 2006.257.04:31:52.72#ibcon#wrote, iclass 15, count 2 2006.257.04:31:52.72#ibcon#about to read 3, iclass 15, count 2 2006.257.04:31:52.75#ibcon#read 3, iclass 15, count 2 2006.257.04:31:52.75#ibcon#about to read 4, iclass 15, count 2 2006.257.04:31:52.75#ibcon#read 4, iclass 15, count 2 2006.257.04:31:52.75#ibcon#about to read 5, iclass 15, count 2 2006.257.04:31:52.75#ibcon#read 5, iclass 15, count 2 2006.257.04:31:52.75#ibcon#about to read 6, iclass 15, count 2 2006.257.04:31:52.75#ibcon#read 6, iclass 15, count 2 2006.257.04:31:52.75#ibcon#end of sib2, iclass 15, count 2 2006.257.04:31:52.75#ibcon#*after write, iclass 15, count 2 2006.257.04:31:52.75#ibcon#*before return 0, iclass 15, count 2 2006.257.04:31:52.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:52.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:52.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.04:31:52.75#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:52.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:52.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:52.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:52.87#ibcon#enter wrdev, iclass 15, count 0 2006.257.04:31:52.87#ibcon#first serial, iclass 15, count 0 2006.257.04:31:52.87#ibcon#enter sib2, iclass 15, count 0 2006.257.04:31:52.87#ibcon#flushed, iclass 15, count 0 2006.257.04:31:52.87#ibcon#about to write, iclass 15, count 0 2006.257.04:31:52.87#ibcon#wrote, iclass 15, count 0 2006.257.04:31:52.87#ibcon#about to read 3, iclass 15, count 0 2006.257.04:31:52.89#ibcon#read 3, iclass 15, count 0 2006.257.04:31:52.89#ibcon#about to read 4, iclass 15, count 0 2006.257.04:31:52.89#ibcon#read 4, iclass 15, count 0 2006.257.04:31:52.89#ibcon#about to read 5, iclass 15, count 0 2006.257.04:31:52.89#ibcon#read 5, iclass 15, count 0 2006.257.04:31:52.89#ibcon#about to read 6, iclass 15, count 0 2006.257.04:31:52.89#ibcon#read 6, iclass 15, count 0 2006.257.04:31:52.89#ibcon#end of sib2, iclass 15, count 0 2006.257.04:31:52.89#ibcon#*mode == 0, iclass 15, count 0 2006.257.04:31:52.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.04:31:52.89#ibcon#[25=USB\r\n] 2006.257.04:31:52.89#ibcon#*before write, iclass 15, count 0 2006.257.04:31:52.89#ibcon#enter sib2, iclass 15, count 0 2006.257.04:31:52.89#ibcon#flushed, iclass 15, count 0 2006.257.04:31:52.89#ibcon#about to write, iclass 15, count 0 2006.257.04:31:52.89#ibcon#wrote, iclass 15, count 0 2006.257.04:31:52.89#ibcon#about to read 3, iclass 15, count 0 2006.257.04:31:52.92#ibcon#read 3, iclass 15, count 0 2006.257.04:31:52.92#ibcon#about to read 4, iclass 15, count 0 2006.257.04:31:52.92#ibcon#read 4, iclass 15, count 0 2006.257.04:31:52.92#ibcon#about to read 5, iclass 15, count 0 2006.257.04:31:52.92#ibcon#read 5, iclass 15, count 0 2006.257.04:31:52.92#ibcon#about to read 6, iclass 15, count 0 2006.257.04:31:52.92#ibcon#read 6, iclass 15, count 0 2006.257.04:31:52.92#ibcon#end of sib2, iclass 15, count 0 2006.257.04:31:52.92#ibcon#*after write, iclass 15, count 0 2006.257.04:31:52.92#ibcon#*before return 0, iclass 15, count 0 2006.257.04:31:52.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:52.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:52.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.04:31:52.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.04:31:52.92$vck44/valo=3,564.99 2006.257.04:31:52.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.04:31:52.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.04:31:52.92#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:52.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:52.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:52.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:52.92#ibcon#enter wrdev, iclass 17, count 0 2006.257.04:31:52.92#ibcon#first serial, iclass 17, count 0 2006.257.04:31:52.92#ibcon#enter sib2, iclass 17, count 0 2006.257.04:31:52.92#ibcon#flushed, iclass 17, count 0 2006.257.04:31:52.92#ibcon#about to write, iclass 17, count 0 2006.257.04:31:52.92#ibcon#wrote, iclass 17, count 0 2006.257.04:31:52.92#ibcon#about to read 3, iclass 17, count 0 2006.257.04:31:52.94#ibcon#read 3, iclass 17, count 0 2006.257.04:31:52.94#ibcon#about to read 4, iclass 17, count 0 2006.257.04:31:52.94#ibcon#read 4, iclass 17, count 0 2006.257.04:31:52.94#ibcon#about to read 5, iclass 17, count 0 2006.257.04:31:52.94#ibcon#read 5, iclass 17, count 0 2006.257.04:31:52.94#ibcon#about to read 6, iclass 17, count 0 2006.257.04:31:52.94#ibcon#read 6, iclass 17, count 0 2006.257.04:31:52.94#ibcon#end of sib2, iclass 17, count 0 2006.257.04:31:52.94#ibcon#*mode == 0, iclass 17, count 0 2006.257.04:31:52.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.04:31:52.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.04:31:52.94#ibcon#*before write, iclass 17, count 0 2006.257.04:31:52.94#ibcon#enter sib2, iclass 17, count 0 2006.257.04:31:52.94#ibcon#flushed, iclass 17, count 0 2006.257.04:31:52.94#ibcon#about to write, iclass 17, count 0 2006.257.04:31:52.94#ibcon#wrote, iclass 17, count 0 2006.257.04:31:52.94#ibcon#about to read 3, iclass 17, count 0 2006.257.04:31:52.98#ibcon#read 3, iclass 17, count 0 2006.257.04:31:52.98#ibcon#about to read 4, iclass 17, count 0 2006.257.04:31:52.98#ibcon#read 4, iclass 17, count 0 2006.257.04:31:52.98#ibcon#about to read 5, iclass 17, count 0 2006.257.04:31:52.98#ibcon#read 5, iclass 17, count 0 2006.257.04:31:52.98#ibcon#about to read 6, iclass 17, count 0 2006.257.04:31:52.98#ibcon#read 6, iclass 17, count 0 2006.257.04:31:52.98#ibcon#end of sib2, iclass 17, count 0 2006.257.04:31:52.98#ibcon#*after write, iclass 17, count 0 2006.257.04:31:52.98#ibcon#*before return 0, iclass 17, count 0 2006.257.04:31:52.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:52.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:52.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.04:31:52.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.04:31:52.98$vck44/va=3,8 2006.257.04:31:52.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.04:31:52.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.04:31:52.98#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:52.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:53.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:53.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:53.04#ibcon#enter wrdev, iclass 19, count 2 2006.257.04:31:53.04#ibcon#first serial, iclass 19, count 2 2006.257.04:31:53.04#ibcon#enter sib2, iclass 19, count 2 2006.257.04:31:53.04#ibcon#flushed, iclass 19, count 2 2006.257.04:31:53.04#ibcon#about to write, iclass 19, count 2 2006.257.04:31:53.04#ibcon#wrote, iclass 19, count 2 2006.257.04:31:53.04#ibcon#about to read 3, iclass 19, count 2 2006.257.04:31:53.06#ibcon#read 3, iclass 19, count 2 2006.257.04:31:53.06#ibcon#about to read 4, iclass 19, count 2 2006.257.04:31:53.06#ibcon#read 4, iclass 19, count 2 2006.257.04:31:53.06#ibcon#about to read 5, iclass 19, count 2 2006.257.04:31:53.06#ibcon#read 5, iclass 19, count 2 2006.257.04:31:53.06#ibcon#about to read 6, iclass 19, count 2 2006.257.04:31:53.06#ibcon#read 6, iclass 19, count 2 2006.257.04:31:53.06#ibcon#end of sib2, iclass 19, count 2 2006.257.04:31:53.06#ibcon#*mode == 0, iclass 19, count 2 2006.257.04:31:53.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.04:31:53.06#ibcon#[25=AT03-08\r\n] 2006.257.04:31:53.06#ibcon#*before write, iclass 19, count 2 2006.257.04:31:53.06#ibcon#enter sib2, iclass 19, count 2 2006.257.04:31:53.06#ibcon#flushed, iclass 19, count 2 2006.257.04:31:53.06#ibcon#about to write, iclass 19, count 2 2006.257.04:31:53.06#ibcon#wrote, iclass 19, count 2 2006.257.04:31:53.06#ibcon#about to read 3, iclass 19, count 2 2006.257.04:31:53.09#ibcon#read 3, iclass 19, count 2 2006.257.04:31:53.09#ibcon#about to read 4, iclass 19, count 2 2006.257.04:31:53.09#ibcon#read 4, iclass 19, count 2 2006.257.04:31:53.09#ibcon#about to read 5, iclass 19, count 2 2006.257.04:31:53.09#ibcon#read 5, iclass 19, count 2 2006.257.04:31:53.09#ibcon#about to read 6, iclass 19, count 2 2006.257.04:31:53.09#ibcon#read 6, iclass 19, count 2 2006.257.04:31:53.09#ibcon#end of sib2, iclass 19, count 2 2006.257.04:31:53.09#ibcon#*after write, iclass 19, count 2 2006.257.04:31:53.09#ibcon#*before return 0, iclass 19, count 2 2006.257.04:31:53.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:53.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:53.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.04:31:53.09#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:53.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:53.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:53.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:53.21#ibcon#enter wrdev, iclass 19, count 0 2006.257.04:31:53.21#ibcon#first serial, iclass 19, count 0 2006.257.04:31:53.21#ibcon#enter sib2, iclass 19, count 0 2006.257.04:31:53.21#ibcon#flushed, iclass 19, count 0 2006.257.04:31:53.21#ibcon#about to write, iclass 19, count 0 2006.257.04:31:53.21#ibcon#wrote, iclass 19, count 0 2006.257.04:31:53.21#ibcon#about to read 3, iclass 19, count 0 2006.257.04:31:53.23#ibcon#read 3, iclass 19, count 0 2006.257.04:31:53.23#ibcon#about to read 4, iclass 19, count 0 2006.257.04:31:53.23#ibcon#read 4, iclass 19, count 0 2006.257.04:31:53.23#ibcon#about to read 5, iclass 19, count 0 2006.257.04:31:53.23#ibcon#read 5, iclass 19, count 0 2006.257.04:31:53.23#ibcon#about to read 6, iclass 19, count 0 2006.257.04:31:53.23#ibcon#read 6, iclass 19, count 0 2006.257.04:31:53.23#ibcon#end of sib2, iclass 19, count 0 2006.257.04:31:53.23#ibcon#*mode == 0, iclass 19, count 0 2006.257.04:31:53.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.04:31:53.23#ibcon#[25=USB\r\n] 2006.257.04:31:53.23#ibcon#*before write, iclass 19, count 0 2006.257.04:31:53.23#ibcon#enter sib2, iclass 19, count 0 2006.257.04:31:53.23#ibcon#flushed, iclass 19, count 0 2006.257.04:31:53.23#ibcon#about to write, iclass 19, count 0 2006.257.04:31:53.23#ibcon#wrote, iclass 19, count 0 2006.257.04:31:53.23#ibcon#about to read 3, iclass 19, count 0 2006.257.04:31:53.26#ibcon#read 3, iclass 19, count 0 2006.257.04:31:53.26#ibcon#about to read 4, iclass 19, count 0 2006.257.04:31:53.26#ibcon#read 4, iclass 19, count 0 2006.257.04:31:53.26#ibcon#about to read 5, iclass 19, count 0 2006.257.04:31:53.26#ibcon#read 5, iclass 19, count 0 2006.257.04:31:53.26#ibcon#about to read 6, iclass 19, count 0 2006.257.04:31:53.26#ibcon#read 6, iclass 19, count 0 2006.257.04:31:53.26#ibcon#end of sib2, iclass 19, count 0 2006.257.04:31:53.26#ibcon#*after write, iclass 19, count 0 2006.257.04:31:53.26#ibcon#*before return 0, iclass 19, count 0 2006.257.04:31:53.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:53.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:53.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.04:31:53.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.04:31:53.26$vck44/valo=4,624.99 2006.257.04:31:53.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.04:31:53.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.04:31:53.26#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:53.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:31:53.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:31:53.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:31:53.26#ibcon#enter wrdev, iclass 21, count 0 2006.257.04:31:53.26#ibcon#first serial, iclass 21, count 0 2006.257.04:31:53.26#ibcon#enter sib2, iclass 21, count 0 2006.257.04:31:53.26#ibcon#flushed, iclass 21, count 0 2006.257.04:31:53.26#ibcon#about to write, iclass 21, count 0 2006.257.04:31:53.26#ibcon#wrote, iclass 21, count 0 2006.257.04:31:53.26#ibcon#about to read 3, iclass 21, count 0 2006.257.04:31:53.28#ibcon#read 3, iclass 21, count 0 2006.257.04:31:53.28#ibcon#about to read 4, iclass 21, count 0 2006.257.04:31:53.28#ibcon#read 4, iclass 21, count 0 2006.257.04:31:53.28#ibcon#about to read 5, iclass 21, count 0 2006.257.04:31:53.28#ibcon#read 5, iclass 21, count 0 2006.257.04:31:53.28#ibcon#about to read 6, iclass 21, count 0 2006.257.04:31:53.28#ibcon#read 6, iclass 21, count 0 2006.257.04:31:53.28#ibcon#end of sib2, iclass 21, count 0 2006.257.04:31:53.28#ibcon#*mode == 0, iclass 21, count 0 2006.257.04:31:53.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.04:31:53.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.04:31:53.28#ibcon#*before write, iclass 21, count 0 2006.257.04:31:53.28#ibcon#enter sib2, iclass 21, count 0 2006.257.04:31:53.28#ibcon#flushed, iclass 21, count 0 2006.257.04:31:53.28#ibcon#about to write, iclass 21, count 0 2006.257.04:31:53.28#ibcon#wrote, iclass 21, count 0 2006.257.04:31:53.28#ibcon#about to read 3, iclass 21, count 0 2006.257.04:31:53.32#ibcon#read 3, iclass 21, count 0 2006.257.04:31:53.32#ibcon#about to read 4, iclass 21, count 0 2006.257.04:31:53.32#ibcon#read 4, iclass 21, count 0 2006.257.04:31:53.32#ibcon#about to read 5, iclass 21, count 0 2006.257.04:31:53.32#ibcon#read 5, iclass 21, count 0 2006.257.04:31:53.32#ibcon#about to read 6, iclass 21, count 0 2006.257.04:31:53.32#ibcon#read 6, iclass 21, count 0 2006.257.04:31:53.32#ibcon#end of sib2, iclass 21, count 0 2006.257.04:31:53.32#ibcon#*after write, iclass 21, count 0 2006.257.04:31:53.32#ibcon#*before return 0, iclass 21, count 0 2006.257.04:31:53.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:31:53.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:31:53.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.04:31:53.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.04:31:53.32$vck44/va=4,7 2006.257.04:31:53.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.04:31:53.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.04:31:53.32#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:53.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:31:53.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:31:53.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:31:53.38#ibcon#enter wrdev, iclass 23, count 2 2006.257.04:31:53.38#ibcon#first serial, iclass 23, count 2 2006.257.04:31:53.38#ibcon#enter sib2, iclass 23, count 2 2006.257.04:31:53.38#ibcon#flushed, iclass 23, count 2 2006.257.04:31:53.38#ibcon#about to write, iclass 23, count 2 2006.257.04:31:53.38#ibcon#wrote, iclass 23, count 2 2006.257.04:31:53.38#ibcon#about to read 3, iclass 23, count 2 2006.257.04:31:53.40#ibcon#read 3, iclass 23, count 2 2006.257.04:31:53.40#ibcon#about to read 4, iclass 23, count 2 2006.257.04:31:53.40#ibcon#read 4, iclass 23, count 2 2006.257.04:31:53.40#ibcon#about to read 5, iclass 23, count 2 2006.257.04:31:53.40#ibcon#read 5, iclass 23, count 2 2006.257.04:31:53.40#ibcon#about to read 6, iclass 23, count 2 2006.257.04:31:53.40#ibcon#read 6, iclass 23, count 2 2006.257.04:31:53.40#ibcon#end of sib2, iclass 23, count 2 2006.257.04:31:53.40#ibcon#*mode == 0, iclass 23, count 2 2006.257.04:31:53.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.04:31:53.40#ibcon#[25=AT04-07\r\n] 2006.257.04:31:53.40#ibcon#*before write, iclass 23, count 2 2006.257.04:31:53.40#ibcon#enter sib2, iclass 23, count 2 2006.257.04:31:53.40#ibcon#flushed, iclass 23, count 2 2006.257.04:31:53.40#ibcon#about to write, iclass 23, count 2 2006.257.04:31:53.40#ibcon#wrote, iclass 23, count 2 2006.257.04:31:53.40#ibcon#about to read 3, iclass 23, count 2 2006.257.04:31:53.43#ibcon#read 3, iclass 23, count 2 2006.257.04:31:53.43#ibcon#about to read 4, iclass 23, count 2 2006.257.04:31:53.43#ibcon#read 4, iclass 23, count 2 2006.257.04:31:53.43#ibcon#about to read 5, iclass 23, count 2 2006.257.04:31:53.43#ibcon#read 5, iclass 23, count 2 2006.257.04:31:53.43#ibcon#about to read 6, iclass 23, count 2 2006.257.04:31:53.43#ibcon#read 6, iclass 23, count 2 2006.257.04:31:53.43#ibcon#end of sib2, iclass 23, count 2 2006.257.04:31:53.43#ibcon#*after write, iclass 23, count 2 2006.257.04:31:53.43#ibcon#*before return 0, iclass 23, count 2 2006.257.04:31:53.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:31:53.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:31:53.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.04:31:53.43#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:53.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:31:53.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:31:53.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:31:53.55#ibcon#enter wrdev, iclass 23, count 0 2006.257.04:31:53.55#ibcon#first serial, iclass 23, count 0 2006.257.04:31:53.55#ibcon#enter sib2, iclass 23, count 0 2006.257.04:31:53.55#ibcon#flushed, iclass 23, count 0 2006.257.04:31:53.55#ibcon#about to write, iclass 23, count 0 2006.257.04:31:53.55#ibcon#wrote, iclass 23, count 0 2006.257.04:31:53.55#ibcon#about to read 3, iclass 23, count 0 2006.257.04:31:53.57#ibcon#read 3, iclass 23, count 0 2006.257.04:31:53.57#ibcon#about to read 4, iclass 23, count 0 2006.257.04:31:53.57#ibcon#read 4, iclass 23, count 0 2006.257.04:31:53.57#ibcon#about to read 5, iclass 23, count 0 2006.257.04:31:53.57#ibcon#read 5, iclass 23, count 0 2006.257.04:31:53.57#ibcon#about to read 6, iclass 23, count 0 2006.257.04:31:53.57#ibcon#read 6, iclass 23, count 0 2006.257.04:31:53.57#ibcon#end of sib2, iclass 23, count 0 2006.257.04:31:53.57#ibcon#*mode == 0, iclass 23, count 0 2006.257.04:31:53.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.04:31:53.57#ibcon#[25=USB\r\n] 2006.257.04:31:53.57#ibcon#*before write, iclass 23, count 0 2006.257.04:31:53.57#ibcon#enter sib2, iclass 23, count 0 2006.257.04:31:53.57#ibcon#flushed, iclass 23, count 0 2006.257.04:31:53.57#ibcon#about to write, iclass 23, count 0 2006.257.04:31:53.57#ibcon#wrote, iclass 23, count 0 2006.257.04:31:53.57#ibcon#about to read 3, iclass 23, count 0 2006.257.04:31:53.60#ibcon#read 3, iclass 23, count 0 2006.257.04:31:53.60#ibcon#about to read 4, iclass 23, count 0 2006.257.04:31:53.60#ibcon#read 4, iclass 23, count 0 2006.257.04:31:53.60#ibcon#about to read 5, iclass 23, count 0 2006.257.04:31:53.60#ibcon#read 5, iclass 23, count 0 2006.257.04:31:53.60#ibcon#about to read 6, iclass 23, count 0 2006.257.04:31:53.60#ibcon#read 6, iclass 23, count 0 2006.257.04:31:53.60#ibcon#end of sib2, iclass 23, count 0 2006.257.04:31:53.60#ibcon#*after write, iclass 23, count 0 2006.257.04:31:53.60#ibcon#*before return 0, iclass 23, count 0 2006.257.04:31:53.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:31:53.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:31:53.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.04:31:53.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.04:31:53.60$vck44/valo=5,734.99 2006.257.04:31:53.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.04:31:53.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.04:31:53.60#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:53.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:53.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:53.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:53.60#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:31:53.60#ibcon#first serial, iclass 25, count 0 2006.257.04:31:53.60#ibcon#enter sib2, iclass 25, count 0 2006.257.04:31:53.60#ibcon#flushed, iclass 25, count 0 2006.257.04:31:53.60#ibcon#about to write, iclass 25, count 0 2006.257.04:31:53.60#ibcon#wrote, iclass 25, count 0 2006.257.04:31:53.60#ibcon#about to read 3, iclass 25, count 0 2006.257.04:31:53.62#ibcon#read 3, iclass 25, count 0 2006.257.04:31:53.62#ibcon#about to read 4, iclass 25, count 0 2006.257.04:31:53.62#ibcon#read 4, iclass 25, count 0 2006.257.04:31:53.62#ibcon#about to read 5, iclass 25, count 0 2006.257.04:31:53.62#ibcon#read 5, iclass 25, count 0 2006.257.04:31:53.62#ibcon#about to read 6, iclass 25, count 0 2006.257.04:31:53.62#ibcon#read 6, iclass 25, count 0 2006.257.04:31:53.62#ibcon#end of sib2, iclass 25, count 0 2006.257.04:31:53.62#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:31:53.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:31:53.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.04:31:53.62#ibcon#*before write, iclass 25, count 0 2006.257.04:31:53.62#ibcon#enter sib2, iclass 25, count 0 2006.257.04:31:53.62#ibcon#flushed, iclass 25, count 0 2006.257.04:31:53.62#ibcon#about to write, iclass 25, count 0 2006.257.04:31:53.62#ibcon#wrote, iclass 25, count 0 2006.257.04:31:53.62#ibcon#about to read 3, iclass 25, count 0 2006.257.04:31:53.66#ibcon#read 3, iclass 25, count 0 2006.257.04:31:53.66#ibcon#about to read 4, iclass 25, count 0 2006.257.04:31:53.66#ibcon#read 4, iclass 25, count 0 2006.257.04:31:53.66#ibcon#about to read 5, iclass 25, count 0 2006.257.04:31:53.66#ibcon#read 5, iclass 25, count 0 2006.257.04:31:53.66#ibcon#about to read 6, iclass 25, count 0 2006.257.04:31:53.66#ibcon#read 6, iclass 25, count 0 2006.257.04:31:53.66#ibcon#end of sib2, iclass 25, count 0 2006.257.04:31:53.66#ibcon#*after write, iclass 25, count 0 2006.257.04:31:53.66#ibcon#*before return 0, iclass 25, count 0 2006.257.04:31:53.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:53.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:53.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:31:53.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:31:53.66$vck44/va=5,4 2006.257.04:31:53.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.04:31:53.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.04:31:53.66#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:53.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:53.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:53.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:53.72#ibcon#enter wrdev, iclass 27, count 2 2006.257.04:31:53.72#ibcon#first serial, iclass 27, count 2 2006.257.04:31:53.72#ibcon#enter sib2, iclass 27, count 2 2006.257.04:31:53.72#ibcon#flushed, iclass 27, count 2 2006.257.04:31:53.72#ibcon#about to write, iclass 27, count 2 2006.257.04:31:53.72#ibcon#wrote, iclass 27, count 2 2006.257.04:31:53.72#ibcon#about to read 3, iclass 27, count 2 2006.257.04:31:53.74#ibcon#read 3, iclass 27, count 2 2006.257.04:31:53.74#ibcon#about to read 4, iclass 27, count 2 2006.257.04:31:53.74#ibcon#read 4, iclass 27, count 2 2006.257.04:31:53.74#ibcon#about to read 5, iclass 27, count 2 2006.257.04:31:53.74#ibcon#read 5, iclass 27, count 2 2006.257.04:31:53.74#ibcon#about to read 6, iclass 27, count 2 2006.257.04:31:53.74#ibcon#read 6, iclass 27, count 2 2006.257.04:31:53.74#ibcon#end of sib2, iclass 27, count 2 2006.257.04:31:53.74#ibcon#*mode == 0, iclass 27, count 2 2006.257.04:31:53.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.04:31:53.74#ibcon#[25=AT05-04\r\n] 2006.257.04:31:53.74#ibcon#*before write, iclass 27, count 2 2006.257.04:31:53.74#ibcon#enter sib2, iclass 27, count 2 2006.257.04:31:53.74#ibcon#flushed, iclass 27, count 2 2006.257.04:31:53.74#ibcon#about to write, iclass 27, count 2 2006.257.04:31:53.74#ibcon#wrote, iclass 27, count 2 2006.257.04:31:53.74#ibcon#about to read 3, iclass 27, count 2 2006.257.04:31:53.77#ibcon#read 3, iclass 27, count 2 2006.257.04:31:53.77#ibcon#about to read 4, iclass 27, count 2 2006.257.04:31:53.77#ibcon#read 4, iclass 27, count 2 2006.257.04:31:53.77#ibcon#about to read 5, iclass 27, count 2 2006.257.04:31:53.77#ibcon#read 5, iclass 27, count 2 2006.257.04:31:53.77#ibcon#about to read 6, iclass 27, count 2 2006.257.04:31:53.77#ibcon#read 6, iclass 27, count 2 2006.257.04:31:53.77#ibcon#end of sib2, iclass 27, count 2 2006.257.04:31:53.77#ibcon#*after write, iclass 27, count 2 2006.257.04:31:53.77#ibcon#*before return 0, iclass 27, count 2 2006.257.04:31:53.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:53.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:53.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.04:31:53.77#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:53.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:53.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:53.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:53.89#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:31:53.89#ibcon#first serial, iclass 27, count 0 2006.257.04:31:53.89#ibcon#enter sib2, iclass 27, count 0 2006.257.04:31:53.89#ibcon#flushed, iclass 27, count 0 2006.257.04:31:53.89#ibcon#about to write, iclass 27, count 0 2006.257.04:31:53.89#ibcon#wrote, iclass 27, count 0 2006.257.04:31:53.89#ibcon#about to read 3, iclass 27, count 0 2006.257.04:31:53.91#ibcon#read 3, iclass 27, count 0 2006.257.04:31:53.91#ibcon#about to read 4, iclass 27, count 0 2006.257.04:31:53.91#ibcon#read 4, iclass 27, count 0 2006.257.04:31:53.91#ibcon#about to read 5, iclass 27, count 0 2006.257.04:31:53.91#ibcon#read 5, iclass 27, count 0 2006.257.04:31:53.91#ibcon#about to read 6, iclass 27, count 0 2006.257.04:31:53.91#ibcon#read 6, iclass 27, count 0 2006.257.04:31:53.91#ibcon#end of sib2, iclass 27, count 0 2006.257.04:31:53.91#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:31:53.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:31:53.91#ibcon#[25=USB\r\n] 2006.257.04:31:53.91#ibcon#*before write, iclass 27, count 0 2006.257.04:31:53.91#ibcon#enter sib2, iclass 27, count 0 2006.257.04:31:53.91#ibcon#flushed, iclass 27, count 0 2006.257.04:31:53.91#ibcon#about to write, iclass 27, count 0 2006.257.04:31:53.91#ibcon#wrote, iclass 27, count 0 2006.257.04:31:53.91#ibcon#about to read 3, iclass 27, count 0 2006.257.04:31:53.94#ibcon#read 3, iclass 27, count 0 2006.257.04:31:53.94#ibcon#about to read 4, iclass 27, count 0 2006.257.04:31:53.94#ibcon#read 4, iclass 27, count 0 2006.257.04:31:53.94#ibcon#about to read 5, iclass 27, count 0 2006.257.04:31:53.94#ibcon#read 5, iclass 27, count 0 2006.257.04:31:53.94#ibcon#about to read 6, iclass 27, count 0 2006.257.04:31:53.94#ibcon#read 6, iclass 27, count 0 2006.257.04:31:53.94#ibcon#end of sib2, iclass 27, count 0 2006.257.04:31:53.94#ibcon#*after write, iclass 27, count 0 2006.257.04:31:53.94#ibcon#*before return 0, iclass 27, count 0 2006.257.04:31:53.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:53.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:53.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:31:53.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:31:53.94$vck44/valo=6,814.99 2006.257.04:31:53.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.04:31:53.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.04:31:53.94#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:53.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:53.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:53.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:53.94#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:31:53.94#ibcon#first serial, iclass 29, count 0 2006.257.04:31:53.94#ibcon#enter sib2, iclass 29, count 0 2006.257.04:31:53.94#ibcon#flushed, iclass 29, count 0 2006.257.04:31:53.94#ibcon#about to write, iclass 29, count 0 2006.257.04:31:53.94#ibcon#wrote, iclass 29, count 0 2006.257.04:31:53.94#ibcon#about to read 3, iclass 29, count 0 2006.257.04:31:53.96#ibcon#read 3, iclass 29, count 0 2006.257.04:31:53.96#ibcon#about to read 4, iclass 29, count 0 2006.257.04:31:53.96#ibcon#read 4, iclass 29, count 0 2006.257.04:31:53.96#ibcon#about to read 5, iclass 29, count 0 2006.257.04:31:53.96#ibcon#read 5, iclass 29, count 0 2006.257.04:31:53.96#ibcon#about to read 6, iclass 29, count 0 2006.257.04:31:53.96#ibcon#read 6, iclass 29, count 0 2006.257.04:31:53.96#ibcon#end of sib2, iclass 29, count 0 2006.257.04:31:53.96#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:31:53.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:31:53.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.04:31:53.96#ibcon#*before write, iclass 29, count 0 2006.257.04:31:53.96#ibcon#enter sib2, iclass 29, count 0 2006.257.04:31:53.96#ibcon#flushed, iclass 29, count 0 2006.257.04:31:53.96#ibcon#about to write, iclass 29, count 0 2006.257.04:31:53.96#ibcon#wrote, iclass 29, count 0 2006.257.04:31:53.96#ibcon#about to read 3, iclass 29, count 0 2006.257.04:31:54.00#ibcon#read 3, iclass 29, count 0 2006.257.04:31:54.00#ibcon#about to read 4, iclass 29, count 0 2006.257.04:31:54.00#ibcon#read 4, iclass 29, count 0 2006.257.04:31:54.00#ibcon#about to read 5, iclass 29, count 0 2006.257.04:31:54.00#ibcon#read 5, iclass 29, count 0 2006.257.04:31:54.00#ibcon#about to read 6, iclass 29, count 0 2006.257.04:31:54.00#ibcon#read 6, iclass 29, count 0 2006.257.04:31:54.00#ibcon#end of sib2, iclass 29, count 0 2006.257.04:31:54.00#ibcon#*after write, iclass 29, count 0 2006.257.04:31:54.00#ibcon#*before return 0, iclass 29, count 0 2006.257.04:31:54.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:54.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:54.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:31:54.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:31:54.00$vck44/va=6,4 2006.257.04:31:54.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.04:31:54.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.04:31:54.00#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:54.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:54.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:54.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:54.06#ibcon#enter wrdev, iclass 31, count 2 2006.257.04:31:54.06#ibcon#first serial, iclass 31, count 2 2006.257.04:31:54.06#ibcon#enter sib2, iclass 31, count 2 2006.257.04:31:54.06#ibcon#flushed, iclass 31, count 2 2006.257.04:31:54.06#ibcon#about to write, iclass 31, count 2 2006.257.04:31:54.06#ibcon#wrote, iclass 31, count 2 2006.257.04:31:54.06#ibcon#about to read 3, iclass 31, count 2 2006.257.04:31:54.08#ibcon#read 3, iclass 31, count 2 2006.257.04:31:54.08#ibcon#about to read 4, iclass 31, count 2 2006.257.04:31:54.08#ibcon#read 4, iclass 31, count 2 2006.257.04:31:54.08#ibcon#about to read 5, iclass 31, count 2 2006.257.04:31:54.08#ibcon#read 5, iclass 31, count 2 2006.257.04:31:54.08#ibcon#about to read 6, iclass 31, count 2 2006.257.04:31:54.08#ibcon#read 6, iclass 31, count 2 2006.257.04:31:54.08#ibcon#end of sib2, iclass 31, count 2 2006.257.04:31:54.08#ibcon#*mode == 0, iclass 31, count 2 2006.257.04:31:54.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.04:31:54.08#ibcon#[25=AT06-04\r\n] 2006.257.04:31:54.08#ibcon#*before write, iclass 31, count 2 2006.257.04:31:54.08#ibcon#enter sib2, iclass 31, count 2 2006.257.04:31:54.08#ibcon#flushed, iclass 31, count 2 2006.257.04:31:54.08#ibcon#about to write, iclass 31, count 2 2006.257.04:31:54.08#ibcon#wrote, iclass 31, count 2 2006.257.04:31:54.08#ibcon#about to read 3, iclass 31, count 2 2006.257.04:31:54.11#ibcon#read 3, iclass 31, count 2 2006.257.04:31:54.11#ibcon#about to read 4, iclass 31, count 2 2006.257.04:31:54.11#ibcon#read 4, iclass 31, count 2 2006.257.04:31:54.11#ibcon#about to read 5, iclass 31, count 2 2006.257.04:31:54.11#ibcon#read 5, iclass 31, count 2 2006.257.04:31:54.11#ibcon#about to read 6, iclass 31, count 2 2006.257.04:31:54.11#ibcon#read 6, iclass 31, count 2 2006.257.04:31:54.11#ibcon#end of sib2, iclass 31, count 2 2006.257.04:31:54.11#ibcon#*after write, iclass 31, count 2 2006.257.04:31:54.11#ibcon#*before return 0, iclass 31, count 2 2006.257.04:31:54.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:54.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:54.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.04:31:54.11#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:54.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:54.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:54.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:54.23#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:31:54.23#ibcon#first serial, iclass 31, count 0 2006.257.04:31:54.23#ibcon#enter sib2, iclass 31, count 0 2006.257.04:31:54.23#ibcon#flushed, iclass 31, count 0 2006.257.04:31:54.23#ibcon#about to write, iclass 31, count 0 2006.257.04:31:54.23#ibcon#wrote, iclass 31, count 0 2006.257.04:31:54.23#ibcon#about to read 3, iclass 31, count 0 2006.257.04:31:54.25#ibcon#read 3, iclass 31, count 0 2006.257.04:31:54.25#ibcon#about to read 4, iclass 31, count 0 2006.257.04:31:54.25#ibcon#read 4, iclass 31, count 0 2006.257.04:31:54.25#ibcon#about to read 5, iclass 31, count 0 2006.257.04:31:54.25#ibcon#read 5, iclass 31, count 0 2006.257.04:31:54.25#ibcon#about to read 6, iclass 31, count 0 2006.257.04:31:54.25#ibcon#read 6, iclass 31, count 0 2006.257.04:31:54.25#ibcon#end of sib2, iclass 31, count 0 2006.257.04:31:54.25#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:31:54.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:31:54.25#ibcon#[25=USB\r\n] 2006.257.04:31:54.25#ibcon#*before write, iclass 31, count 0 2006.257.04:31:54.25#ibcon#enter sib2, iclass 31, count 0 2006.257.04:31:54.25#ibcon#flushed, iclass 31, count 0 2006.257.04:31:54.25#ibcon#about to write, iclass 31, count 0 2006.257.04:31:54.25#ibcon#wrote, iclass 31, count 0 2006.257.04:31:54.25#ibcon#about to read 3, iclass 31, count 0 2006.257.04:31:54.28#ibcon#read 3, iclass 31, count 0 2006.257.04:31:54.28#ibcon#about to read 4, iclass 31, count 0 2006.257.04:31:54.28#ibcon#read 4, iclass 31, count 0 2006.257.04:31:54.28#ibcon#about to read 5, iclass 31, count 0 2006.257.04:31:54.28#ibcon#read 5, iclass 31, count 0 2006.257.04:31:54.28#ibcon#about to read 6, iclass 31, count 0 2006.257.04:31:54.28#ibcon#read 6, iclass 31, count 0 2006.257.04:31:54.28#ibcon#end of sib2, iclass 31, count 0 2006.257.04:31:54.28#ibcon#*after write, iclass 31, count 0 2006.257.04:31:54.28#ibcon#*before return 0, iclass 31, count 0 2006.257.04:31:54.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:54.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:54.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:31:54.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:31:54.28$vck44/valo=7,864.99 2006.257.04:31:54.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.04:31:54.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.04:31:54.28#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:54.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:54.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:54.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:54.28#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:31:54.28#ibcon#first serial, iclass 33, count 0 2006.257.04:31:54.28#ibcon#enter sib2, iclass 33, count 0 2006.257.04:31:54.28#ibcon#flushed, iclass 33, count 0 2006.257.04:31:54.28#ibcon#about to write, iclass 33, count 0 2006.257.04:31:54.28#ibcon#wrote, iclass 33, count 0 2006.257.04:31:54.28#ibcon#about to read 3, iclass 33, count 0 2006.257.04:31:54.30#ibcon#read 3, iclass 33, count 0 2006.257.04:31:54.30#ibcon#about to read 4, iclass 33, count 0 2006.257.04:31:54.30#ibcon#read 4, iclass 33, count 0 2006.257.04:31:54.30#ibcon#about to read 5, iclass 33, count 0 2006.257.04:31:54.30#ibcon#read 5, iclass 33, count 0 2006.257.04:31:54.30#ibcon#about to read 6, iclass 33, count 0 2006.257.04:31:54.30#ibcon#read 6, iclass 33, count 0 2006.257.04:31:54.30#ibcon#end of sib2, iclass 33, count 0 2006.257.04:31:54.30#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:31:54.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:31:54.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.04:31:54.30#ibcon#*before write, iclass 33, count 0 2006.257.04:31:54.30#ibcon#enter sib2, iclass 33, count 0 2006.257.04:31:54.30#ibcon#flushed, iclass 33, count 0 2006.257.04:31:54.30#ibcon#about to write, iclass 33, count 0 2006.257.04:31:54.30#ibcon#wrote, iclass 33, count 0 2006.257.04:31:54.30#ibcon#about to read 3, iclass 33, count 0 2006.257.04:31:54.34#ibcon#read 3, iclass 33, count 0 2006.257.04:31:54.34#ibcon#about to read 4, iclass 33, count 0 2006.257.04:31:54.34#ibcon#read 4, iclass 33, count 0 2006.257.04:31:54.34#ibcon#about to read 5, iclass 33, count 0 2006.257.04:31:54.34#ibcon#read 5, iclass 33, count 0 2006.257.04:31:54.34#ibcon#about to read 6, iclass 33, count 0 2006.257.04:31:54.34#ibcon#read 6, iclass 33, count 0 2006.257.04:31:54.34#ibcon#end of sib2, iclass 33, count 0 2006.257.04:31:54.34#ibcon#*after write, iclass 33, count 0 2006.257.04:31:54.34#ibcon#*before return 0, iclass 33, count 0 2006.257.04:31:54.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:54.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:54.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:31:54.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:31:54.34$vck44/va=7,4 2006.257.04:31:54.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.04:31:54.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.04:31:54.34#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:54.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:54.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:54.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:54.40#ibcon#enter wrdev, iclass 35, count 2 2006.257.04:31:54.40#ibcon#first serial, iclass 35, count 2 2006.257.04:31:54.40#ibcon#enter sib2, iclass 35, count 2 2006.257.04:31:54.40#ibcon#flushed, iclass 35, count 2 2006.257.04:31:54.40#ibcon#about to write, iclass 35, count 2 2006.257.04:31:54.40#ibcon#wrote, iclass 35, count 2 2006.257.04:31:54.40#ibcon#about to read 3, iclass 35, count 2 2006.257.04:31:54.42#ibcon#read 3, iclass 35, count 2 2006.257.04:31:54.42#ibcon#about to read 4, iclass 35, count 2 2006.257.04:31:54.42#ibcon#read 4, iclass 35, count 2 2006.257.04:31:54.42#ibcon#about to read 5, iclass 35, count 2 2006.257.04:31:54.42#ibcon#read 5, iclass 35, count 2 2006.257.04:31:54.42#ibcon#about to read 6, iclass 35, count 2 2006.257.04:31:54.42#ibcon#read 6, iclass 35, count 2 2006.257.04:31:54.42#ibcon#end of sib2, iclass 35, count 2 2006.257.04:31:54.42#ibcon#*mode == 0, iclass 35, count 2 2006.257.04:31:54.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.04:31:54.42#ibcon#[25=AT07-04\r\n] 2006.257.04:31:54.42#ibcon#*before write, iclass 35, count 2 2006.257.04:31:54.42#ibcon#enter sib2, iclass 35, count 2 2006.257.04:31:54.42#ibcon#flushed, iclass 35, count 2 2006.257.04:31:54.42#ibcon#about to write, iclass 35, count 2 2006.257.04:31:54.42#ibcon#wrote, iclass 35, count 2 2006.257.04:31:54.42#ibcon#about to read 3, iclass 35, count 2 2006.257.04:31:54.45#ibcon#read 3, iclass 35, count 2 2006.257.04:31:54.45#ibcon#about to read 4, iclass 35, count 2 2006.257.04:31:54.45#ibcon#read 4, iclass 35, count 2 2006.257.04:31:54.45#ibcon#about to read 5, iclass 35, count 2 2006.257.04:31:54.45#ibcon#read 5, iclass 35, count 2 2006.257.04:31:54.45#ibcon#about to read 6, iclass 35, count 2 2006.257.04:31:54.45#ibcon#read 6, iclass 35, count 2 2006.257.04:31:54.45#ibcon#end of sib2, iclass 35, count 2 2006.257.04:31:54.45#ibcon#*after write, iclass 35, count 2 2006.257.04:31:54.45#ibcon#*before return 0, iclass 35, count 2 2006.257.04:31:54.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:54.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:54.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.04:31:54.45#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:54.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:54.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:54.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:54.57#ibcon#enter wrdev, iclass 35, count 0 2006.257.04:31:54.57#ibcon#first serial, iclass 35, count 0 2006.257.04:31:54.57#ibcon#enter sib2, iclass 35, count 0 2006.257.04:31:54.57#ibcon#flushed, iclass 35, count 0 2006.257.04:31:54.57#ibcon#about to write, iclass 35, count 0 2006.257.04:31:54.57#ibcon#wrote, iclass 35, count 0 2006.257.04:31:54.57#ibcon#about to read 3, iclass 35, count 0 2006.257.04:31:54.59#ibcon#read 3, iclass 35, count 0 2006.257.04:31:54.59#ibcon#about to read 4, iclass 35, count 0 2006.257.04:31:54.59#ibcon#read 4, iclass 35, count 0 2006.257.04:31:54.59#ibcon#about to read 5, iclass 35, count 0 2006.257.04:31:54.59#ibcon#read 5, iclass 35, count 0 2006.257.04:31:54.59#ibcon#about to read 6, iclass 35, count 0 2006.257.04:31:54.59#ibcon#read 6, iclass 35, count 0 2006.257.04:31:54.59#ibcon#end of sib2, iclass 35, count 0 2006.257.04:31:54.59#ibcon#*mode == 0, iclass 35, count 0 2006.257.04:31:54.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.04:31:54.59#ibcon#[25=USB\r\n] 2006.257.04:31:54.59#ibcon#*before write, iclass 35, count 0 2006.257.04:31:54.59#ibcon#enter sib2, iclass 35, count 0 2006.257.04:31:54.59#ibcon#flushed, iclass 35, count 0 2006.257.04:31:54.59#ibcon#about to write, iclass 35, count 0 2006.257.04:31:54.59#ibcon#wrote, iclass 35, count 0 2006.257.04:31:54.59#ibcon#about to read 3, iclass 35, count 0 2006.257.04:31:54.62#ibcon#read 3, iclass 35, count 0 2006.257.04:31:54.62#ibcon#about to read 4, iclass 35, count 0 2006.257.04:31:54.62#ibcon#read 4, iclass 35, count 0 2006.257.04:31:54.62#ibcon#about to read 5, iclass 35, count 0 2006.257.04:31:54.62#ibcon#read 5, iclass 35, count 0 2006.257.04:31:54.62#ibcon#about to read 6, iclass 35, count 0 2006.257.04:31:54.62#ibcon#read 6, iclass 35, count 0 2006.257.04:31:54.62#ibcon#end of sib2, iclass 35, count 0 2006.257.04:31:54.62#ibcon#*after write, iclass 35, count 0 2006.257.04:31:54.62#ibcon#*before return 0, iclass 35, count 0 2006.257.04:31:54.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:54.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:54.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.04:31:54.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.04:31:54.62$vck44/valo=8,884.99 2006.257.04:31:54.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.04:31:54.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.04:31:54.62#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:54.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:54.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:54.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:54.62#ibcon#enter wrdev, iclass 37, count 0 2006.257.04:31:54.62#ibcon#first serial, iclass 37, count 0 2006.257.04:31:54.62#ibcon#enter sib2, iclass 37, count 0 2006.257.04:31:54.62#ibcon#flushed, iclass 37, count 0 2006.257.04:31:54.62#ibcon#about to write, iclass 37, count 0 2006.257.04:31:54.62#ibcon#wrote, iclass 37, count 0 2006.257.04:31:54.62#ibcon#about to read 3, iclass 37, count 0 2006.257.04:31:54.64#ibcon#read 3, iclass 37, count 0 2006.257.04:31:54.64#ibcon#about to read 4, iclass 37, count 0 2006.257.04:31:54.64#ibcon#read 4, iclass 37, count 0 2006.257.04:31:54.64#ibcon#about to read 5, iclass 37, count 0 2006.257.04:31:54.64#ibcon#read 5, iclass 37, count 0 2006.257.04:31:54.64#ibcon#about to read 6, iclass 37, count 0 2006.257.04:31:54.64#ibcon#read 6, iclass 37, count 0 2006.257.04:31:54.64#ibcon#end of sib2, iclass 37, count 0 2006.257.04:31:54.64#ibcon#*mode == 0, iclass 37, count 0 2006.257.04:31:54.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.04:31:54.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.04:31:54.64#ibcon#*before write, iclass 37, count 0 2006.257.04:31:54.64#ibcon#enter sib2, iclass 37, count 0 2006.257.04:31:54.64#ibcon#flushed, iclass 37, count 0 2006.257.04:31:54.64#ibcon#about to write, iclass 37, count 0 2006.257.04:31:54.64#ibcon#wrote, iclass 37, count 0 2006.257.04:31:54.64#ibcon#about to read 3, iclass 37, count 0 2006.257.04:31:54.68#ibcon#read 3, iclass 37, count 0 2006.257.04:31:54.68#ibcon#about to read 4, iclass 37, count 0 2006.257.04:31:54.68#ibcon#read 4, iclass 37, count 0 2006.257.04:31:54.68#ibcon#about to read 5, iclass 37, count 0 2006.257.04:31:54.68#ibcon#read 5, iclass 37, count 0 2006.257.04:31:54.68#ibcon#about to read 6, iclass 37, count 0 2006.257.04:31:54.68#ibcon#read 6, iclass 37, count 0 2006.257.04:31:54.68#ibcon#end of sib2, iclass 37, count 0 2006.257.04:31:54.68#ibcon#*after write, iclass 37, count 0 2006.257.04:31:54.68#ibcon#*before return 0, iclass 37, count 0 2006.257.04:31:54.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:54.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:54.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.04:31:54.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.04:31:54.68$vck44/va=8,4 2006.257.04:31:54.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.04:31:54.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.04:31:54.68#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:54.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:54.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:54.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:54.74#ibcon#enter wrdev, iclass 39, count 2 2006.257.04:31:54.74#ibcon#first serial, iclass 39, count 2 2006.257.04:31:54.74#ibcon#enter sib2, iclass 39, count 2 2006.257.04:31:54.74#ibcon#flushed, iclass 39, count 2 2006.257.04:31:54.74#ibcon#about to write, iclass 39, count 2 2006.257.04:31:54.74#ibcon#wrote, iclass 39, count 2 2006.257.04:31:54.74#ibcon#about to read 3, iclass 39, count 2 2006.257.04:31:54.76#ibcon#read 3, iclass 39, count 2 2006.257.04:31:54.76#ibcon#about to read 4, iclass 39, count 2 2006.257.04:31:54.76#ibcon#read 4, iclass 39, count 2 2006.257.04:31:54.76#ibcon#about to read 5, iclass 39, count 2 2006.257.04:31:54.76#ibcon#read 5, iclass 39, count 2 2006.257.04:31:54.76#ibcon#about to read 6, iclass 39, count 2 2006.257.04:31:54.76#ibcon#read 6, iclass 39, count 2 2006.257.04:31:54.76#ibcon#end of sib2, iclass 39, count 2 2006.257.04:31:54.76#ibcon#*mode == 0, iclass 39, count 2 2006.257.04:31:54.76#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.04:31:54.76#ibcon#[25=AT08-04\r\n] 2006.257.04:31:54.76#ibcon#*before write, iclass 39, count 2 2006.257.04:31:54.76#ibcon#enter sib2, iclass 39, count 2 2006.257.04:31:54.76#ibcon#flushed, iclass 39, count 2 2006.257.04:31:54.76#ibcon#about to write, iclass 39, count 2 2006.257.04:31:54.76#ibcon#wrote, iclass 39, count 2 2006.257.04:31:54.76#ibcon#about to read 3, iclass 39, count 2 2006.257.04:31:54.79#ibcon#read 3, iclass 39, count 2 2006.257.04:31:54.79#ibcon#about to read 4, iclass 39, count 2 2006.257.04:31:54.79#ibcon#read 4, iclass 39, count 2 2006.257.04:31:54.79#ibcon#about to read 5, iclass 39, count 2 2006.257.04:31:54.79#ibcon#read 5, iclass 39, count 2 2006.257.04:31:54.79#ibcon#about to read 6, iclass 39, count 2 2006.257.04:31:54.79#ibcon#read 6, iclass 39, count 2 2006.257.04:31:54.79#ibcon#end of sib2, iclass 39, count 2 2006.257.04:31:54.79#ibcon#*after write, iclass 39, count 2 2006.257.04:31:54.79#ibcon#*before return 0, iclass 39, count 2 2006.257.04:31:54.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:54.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:54.79#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.04:31:54.79#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:54.79#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:54.91#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:54.91#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:54.91#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:31:54.91#ibcon#first serial, iclass 39, count 0 2006.257.04:31:54.91#ibcon#enter sib2, iclass 39, count 0 2006.257.04:31:54.91#ibcon#flushed, iclass 39, count 0 2006.257.04:31:54.91#ibcon#about to write, iclass 39, count 0 2006.257.04:31:54.91#ibcon#wrote, iclass 39, count 0 2006.257.04:31:54.91#ibcon#about to read 3, iclass 39, count 0 2006.257.04:31:54.93#ibcon#read 3, iclass 39, count 0 2006.257.04:31:54.93#ibcon#about to read 4, iclass 39, count 0 2006.257.04:31:54.93#ibcon#read 4, iclass 39, count 0 2006.257.04:31:54.93#ibcon#about to read 5, iclass 39, count 0 2006.257.04:31:54.93#ibcon#read 5, iclass 39, count 0 2006.257.04:31:54.93#ibcon#about to read 6, iclass 39, count 0 2006.257.04:31:54.93#ibcon#read 6, iclass 39, count 0 2006.257.04:31:54.93#ibcon#end of sib2, iclass 39, count 0 2006.257.04:31:54.93#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:31:54.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:31:54.93#ibcon#[25=USB\r\n] 2006.257.04:31:54.93#ibcon#*before write, iclass 39, count 0 2006.257.04:31:54.93#ibcon#enter sib2, iclass 39, count 0 2006.257.04:31:54.93#ibcon#flushed, iclass 39, count 0 2006.257.04:31:54.93#ibcon#about to write, iclass 39, count 0 2006.257.04:31:54.93#ibcon#wrote, iclass 39, count 0 2006.257.04:31:54.93#ibcon#about to read 3, iclass 39, count 0 2006.257.04:31:54.96#ibcon#read 3, iclass 39, count 0 2006.257.04:31:54.96#ibcon#about to read 4, iclass 39, count 0 2006.257.04:31:54.96#ibcon#read 4, iclass 39, count 0 2006.257.04:31:54.96#ibcon#about to read 5, iclass 39, count 0 2006.257.04:31:54.96#ibcon#read 5, iclass 39, count 0 2006.257.04:31:54.96#ibcon#about to read 6, iclass 39, count 0 2006.257.04:31:54.96#ibcon#read 6, iclass 39, count 0 2006.257.04:31:54.96#ibcon#end of sib2, iclass 39, count 0 2006.257.04:31:54.96#ibcon#*after write, iclass 39, count 0 2006.257.04:31:54.96#ibcon#*before return 0, iclass 39, count 0 2006.257.04:31:54.96#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:54.96#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:54.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:31:54.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:31:54.96$vck44/vblo=1,629.99 2006.257.04:31:54.96#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.04:31:54.96#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.04:31:54.96#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:54.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:54.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:54.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:54.96#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:31:54.96#ibcon#first serial, iclass 3, count 0 2006.257.04:31:54.96#ibcon#enter sib2, iclass 3, count 0 2006.257.04:31:54.96#ibcon#flushed, iclass 3, count 0 2006.257.04:31:54.96#ibcon#about to write, iclass 3, count 0 2006.257.04:31:54.96#ibcon#wrote, iclass 3, count 0 2006.257.04:31:54.96#ibcon#about to read 3, iclass 3, count 0 2006.257.04:31:54.98#ibcon#read 3, iclass 3, count 0 2006.257.04:31:54.98#ibcon#about to read 4, iclass 3, count 0 2006.257.04:31:54.98#ibcon#read 4, iclass 3, count 0 2006.257.04:31:54.98#ibcon#about to read 5, iclass 3, count 0 2006.257.04:31:54.98#ibcon#read 5, iclass 3, count 0 2006.257.04:31:54.98#ibcon#about to read 6, iclass 3, count 0 2006.257.04:31:54.98#ibcon#read 6, iclass 3, count 0 2006.257.04:31:54.98#ibcon#end of sib2, iclass 3, count 0 2006.257.04:31:54.98#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:31:54.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:31:54.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.04:31:54.98#ibcon#*before write, iclass 3, count 0 2006.257.04:31:54.98#ibcon#enter sib2, iclass 3, count 0 2006.257.04:31:54.98#ibcon#flushed, iclass 3, count 0 2006.257.04:31:54.98#ibcon#about to write, iclass 3, count 0 2006.257.04:31:54.98#ibcon#wrote, iclass 3, count 0 2006.257.04:31:54.98#ibcon#about to read 3, iclass 3, count 0 2006.257.04:31:55.02#ibcon#read 3, iclass 3, count 0 2006.257.04:31:55.02#ibcon#about to read 4, iclass 3, count 0 2006.257.04:31:55.02#ibcon#read 4, iclass 3, count 0 2006.257.04:31:55.02#ibcon#about to read 5, iclass 3, count 0 2006.257.04:31:55.02#ibcon#read 5, iclass 3, count 0 2006.257.04:31:55.02#ibcon#about to read 6, iclass 3, count 0 2006.257.04:31:55.02#ibcon#read 6, iclass 3, count 0 2006.257.04:31:55.02#ibcon#end of sib2, iclass 3, count 0 2006.257.04:31:55.02#ibcon#*after write, iclass 3, count 0 2006.257.04:31:55.02#ibcon#*before return 0, iclass 3, count 0 2006.257.04:31:55.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:55.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:55.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:31:55.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:31:55.02$vck44/vb=1,4 2006.257.04:31:55.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.04:31:55.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.04:31:55.02#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:55.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:31:55.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:31:55.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:31:55.02#ibcon#enter wrdev, iclass 5, count 2 2006.257.04:31:55.02#ibcon#first serial, iclass 5, count 2 2006.257.04:31:55.02#ibcon#enter sib2, iclass 5, count 2 2006.257.04:31:55.02#ibcon#flushed, iclass 5, count 2 2006.257.04:31:55.02#ibcon#about to write, iclass 5, count 2 2006.257.04:31:55.02#ibcon#wrote, iclass 5, count 2 2006.257.04:31:55.02#ibcon#about to read 3, iclass 5, count 2 2006.257.04:31:55.04#ibcon#read 3, iclass 5, count 2 2006.257.04:31:55.04#ibcon#about to read 4, iclass 5, count 2 2006.257.04:31:55.04#ibcon#read 4, iclass 5, count 2 2006.257.04:31:55.04#ibcon#about to read 5, iclass 5, count 2 2006.257.04:31:55.04#ibcon#read 5, iclass 5, count 2 2006.257.04:31:55.04#ibcon#about to read 6, iclass 5, count 2 2006.257.04:31:55.04#ibcon#read 6, iclass 5, count 2 2006.257.04:31:55.04#ibcon#end of sib2, iclass 5, count 2 2006.257.04:31:55.04#ibcon#*mode == 0, iclass 5, count 2 2006.257.04:31:55.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.04:31:55.04#ibcon#[27=AT01-04\r\n] 2006.257.04:31:55.04#ibcon#*before write, iclass 5, count 2 2006.257.04:31:55.04#ibcon#enter sib2, iclass 5, count 2 2006.257.04:31:55.04#ibcon#flushed, iclass 5, count 2 2006.257.04:31:55.04#ibcon#about to write, iclass 5, count 2 2006.257.04:31:55.04#ibcon#wrote, iclass 5, count 2 2006.257.04:31:55.04#ibcon#about to read 3, iclass 5, count 2 2006.257.04:31:55.07#ibcon#read 3, iclass 5, count 2 2006.257.04:31:55.07#ibcon#about to read 4, iclass 5, count 2 2006.257.04:31:55.07#ibcon#read 4, iclass 5, count 2 2006.257.04:31:55.07#ibcon#about to read 5, iclass 5, count 2 2006.257.04:31:55.07#ibcon#read 5, iclass 5, count 2 2006.257.04:31:55.07#ibcon#about to read 6, iclass 5, count 2 2006.257.04:31:55.07#ibcon#read 6, iclass 5, count 2 2006.257.04:31:55.07#ibcon#end of sib2, iclass 5, count 2 2006.257.04:31:55.07#ibcon#*after write, iclass 5, count 2 2006.257.04:31:55.07#ibcon#*before return 0, iclass 5, count 2 2006.257.04:31:55.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:31:55.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:31:55.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.04:31:55.07#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:55.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:31:55.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:31:55.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:31:55.19#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:31:55.19#ibcon#first serial, iclass 5, count 0 2006.257.04:31:55.19#ibcon#enter sib2, iclass 5, count 0 2006.257.04:31:55.19#ibcon#flushed, iclass 5, count 0 2006.257.04:31:55.19#ibcon#about to write, iclass 5, count 0 2006.257.04:31:55.19#ibcon#wrote, iclass 5, count 0 2006.257.04:31:55.19#ibcon#about to read 3, iclass 5, count 0 2006.257.04:31:55.21#ibcon#read 3, iclass 5, count 0 2006.257.04:31:55.21#ibcon#about to read 4, iclass 5, count 0 2006.257.04:31:55.21#ibcon#read 4, iclass 5, count 0 2006.257.04:31:55.21#ibcon#about to read 5, iclass 5, count 0 2006.257.04:31:55.21#ibcon#read 5, iclass 5, count 0 2006.257.04:31:55.21#ibcon#about to read 6, iclass 5, count 0 2006.257.04:31:55.21#ibcon#read 6, iclass 5, count 0 2006.257.04:31:55.21#ibcon#end of sib2, iclass 5, count 0 2006.257.04:31:55.21#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:31:55.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:31:55.21#ibcon#[27=USB\r\n] 2006.257.04:31:55.21#ibcon#*before write, iclass 5, count 0 2006.257.04:31:55.21#ibcon#enter sib2, iclass 5, count 0 2006.257.04:31:55.21#ibcon#flushed, iclass 5, count 0 2006.257.04:31:55.21#ibcon#about to write, iclass 5, count 0 2006.257.04:31:55.21#ibcon#wrote, iclass 5, count 0 2006.257.04:31:55.21#ibcon#about to read 3, iclass 5, count 0 2006.257.04:31:55.24#ibcon#read 3, iclass 5, count 0 2006.257.04:31:55.24#ibcon#about to read 4, iclass 5, count 0 2006.257.04:31:55.24#ibcon#read 4, iclass 5, count 0 2006.257.04:31:55.24#ibcon#about to read 5, iclass 5, count 0 2006.257.04:31:55.24#ibcon#read 5, iclass 5, count 0 2006.257.04:31:55.24#ibcon#about to read 6, iclass 5, count 0 2006.257.04:31:55.24#ibcon#read 6, iclass 5, count 0 2006.257.04:31:55.24#ibcon#end of sib2, iclass 5, count 0 2006.257.04:31:55.24#ibcon#*after write, iclass 5, count 0 2006.257.04:31:55.24#ibcon#*before return 0, iclass 5, count 0 2006.257.04:31:55.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:31:55.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:31:55.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:31:55.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:31:55.24$vck44/vblo=2,634.99 2006.257.04:31:55.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.04:31:55.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.04:31:55.24#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:55.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:55.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:55.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:55.24#ibcon#enter wrdev, iclass 7, count 0 2006.257.04:31:55.24#ibcon#first serial, iclass 7, count 0 2006.257.04:31:55.24#ibcon#enter sib2, iclass 7, count 0 2006.257.04:31:55.24#ibcon#flushed, iclass 7, count 0 2006.257.04:31:55.24#ibcon#about to write, iclass 7, count 0 2006.257.04:31:55.24#ibcon#wrote, iclass 7, count 0 2006.257.04:31:55.24#ibcon#about to read 3, iclass 7, count 0 2006.257.04:31:55.26#ibcon#read 3, iclass 7, count 0 2006.257.04:31:55.26#ibcon#about to read 4, iclass 7, count 0 2006.257.04:31:55.26#ibcon#read 4, iclass 7, count 0 2006.257.04:31:55.26#ibcon#about to read 5, iclass 7, count 0 2006.257.04:31:55.26#ibcon#read 5, iclass 7, count 0 2006.257.04:31:55.26#ibcon#about to read 6, iclass 7, count 0 2006.257.04:31:55.26#ibcon#read 6, iclass 7, count 0 2006.257.04:31:55.26#ibcon#end of sib2, iclass 7, count 0 2006.257.04:31:55.26#ibcon#*mode == 0, iclass 7, count 0 2006.257.04:31:55.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.04:31:55.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.04:31:55.26#ibcon#*before write, iclass 7, count 0 2006.257.04:31:55.26#ibcon#enter sib2, iclass 7, count 0 2006.257.04:31:55.26#ibcon#flushed, iclass 7, count 0 2006.257.04:31:55.26#ibcon#about to write, iclass 7, count 0 2006.257.04:31:55.26#ibcon#wrote, iclass 7, count 0 2006.257.04:31:55.26#ibcon#about to read 3, iclass 7, count 0 2006.257.04:31:55.30#ibcon#read 3, iclass 7, count 0 2006.257.04:31:55.30#ibcon#about to read 4, iclass 7, count 0 2006.257.04:31:55.30#ibcon#read 4, iclass 7, count 0 2006.257.04:31:55.30#ibcon#about to read 5, iclass 7, count 0 2006.257.04:31:55.30#ibcon#read 5, iclass 7, count 0 2006.257.04:31:55.30#ibcon#about to read 6, iclass 7, count 0 2006.257.04:31:55.30#ibcon#read 6, iclass 7, count 0 2006.257.04:31:55.30#ibcon#end of sib2, iclass 7, count 0 2006.257.04:31:55.30#ibcon#*after write, iclass 7, count 0 2006.257.04:31:55.30#ibcon#*before return 0, iclass 7, count 0 2006.257.04:31:55.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:55.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:31:55.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.04:31:55.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.04:31:55.30$vck44/vb=2,5 2006.257.04:31:55.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.04:31:55.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.04:31:55.30#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:55.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:55.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:55.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:55.36#ibcon#enter wrdev, iclass 11, count 2 2006.257.04:31:55.36#ibcon#first serial, iclass 11, count 2 2006.257.04:31:55.36#ibcon#enter sib2, iclass 11, count 2 2006.257.04:31:55.36#ibcon#flushed, iclass 11, count 2 2006.257.04:31:55.36#ibcon#about to write, iclass 11, count 2 2006.257.04:31:55.36#ibcon#wrote, iclass 11, count 2 2006.257.04:31:55.36#ibcon#about to read 3, iclass 11, count 2 2006.257.04:31:55.38#ibcon#read 3, iclass 11, count 2 2006.257.04:31:55.38#ibcon#about to read 4, iclass 11, count 2 2006.257.04:31:55.38#ibcon#read 4, iclass 11, count 2 2006.257.04:31:55.38#ibcon#about to read 5, iclass 11, count 2 2006.257.04:31:55.38#ibcon#read 5, iclass 11, count 2 2006.257.04:31:55.38#ibcon#about to read 6, iclass 11, count 2 2006.257.04:31:55.38#ibcon#read 6, iclass 11, count 2 2006.257.04:31:55.38#ibcon#end of sib2, iclass 11, count 2 2006.257.04:31:55.38#ibcon#*mode == 0, iclass 11, count 2 2006.257.04:31:55.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.04:31:55.38#ibcon#[27=AT02-05\r\n] 2006.257.04:31:55.38#ibcon#*before write, iclass 11, count 2 2006.257.04:31:55.38#ibcon#enter sib2, iclass 11, count 2 2006.257.04:31:55.38#ibcon#flushed, iclass 11, count 2 2006.257.04:31:55.38#ibcon#about to write, iclass 11, count 2 2006.257.04:31:55.38#ibcon#wrote, iclass 11, count 2 2006.257.04:31:55.38#ibcon#about to read 3, iclass 11, count 2 2006.257.04:31:55.41#ibcon#read 3, iclass 11, count 2 2006.257.04:31:55.41#ibcon#about to read 4, iclass 11, count 2 2006.257.04:31:55.41#ibcon#read 4, iclass 11, count 2 2006.257.04:31:55.41#ibcon#about to read 5, iclass 11, count 2 2006.257.04:31:55.41#ibcon#read 5, iclass 11, count 2 2006.257.04:31:55.41#ibcon#about to read 6, iclass 11, count 2 2006.257.04:31:55.41#ibcon#read 6, iclass 11, count 2 2006.257.04:31:55.41#ibcon#end of sib2, iclass 11, count 2 2006.257.04:31:55.41#ibcon#*after write, iclass 11, count 2 2006.257.04:31:55.41#ibcon#*before return 0, iclass 11, count 2 2006.257.04:31:55.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:55.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:31:55.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.04:31:55.41#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:55.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:55.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:55.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:55.53#ibcon#enter wrdev, iclass 11, count 0 2006.257.04:31:55.53#ibcon#first serial, iclass 11, count 0 2006.257.04:31:55.53#ibcon#enter sib2, iclass 11, count 0 2006.257.04:31:55.53#ibcon#flushed, iclass 11, count 0 2006.257.04:31:55.53#ibcon#about to write, iclass 11, count 0 2006.257.04:31:55.53#ibcon#wrote, iclass 11, count 0 2006.257.04:31:55.53#ibcon#about to read 3, iclass 11, count 0 2006.257.04:31:55.55#ibcon#read 3, iclass 11, count 0 2006.257.04:31:55.55#ibcon#about to read 4, iclass 11, count 0 2006.257.04:31:55.55#ibcon#read 4, iclass 11, count 0 2006.257.04:31:55.55#ibcon#about to read 5, iclass 11, count 0 2006.257.04:31:55.55#ibcon#read 5, iclass 11, count 0 2006.257.04:31:55.55#ibcon#about to read 6, iclass 11, count 0 2006.257.04:31:55.55#ibcon#read 6, iclass 11, count 0 2006.257.04:31:55.55#ibcon#end of sib2, iclass 11, count 0 2006.257.04:31:55.55#ibcon#*mode == 0, iclass 11, count 0 2006.257.04:31:55.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.04:31:55.55#ibcon#[27=USB\r\n] 2006.257.04:31:55.55#ibcon#*before write, iclass 11, count 0 2006.257.04:31:55.55#ibcon#enter sib2, iclass 11, count 0 2006.257.04:31:55.55#ibcon#flushed, iclass 11, count 0 2006.257.04:31:55.55#ibcon#about to write, iclass 11, count 0 2006.257.04:31:55.55#ibcon#wrote, iclass 11, count 0 2006.257.04:31:55.55#ibcon#about to read 3, iclass 11, count 0 2006.257.04:31:55.58#ibcon#read 3, iclass 11, count 0 2006.257.04:31:55.58#ibcon#about to read 4, iclass 11, count 0 2006.257.04:31:55.58#ibcon#read 4, iclass 11, count 0 2006.257.04:31:55.58#ibcon#about to read 5, iclass 11, count 0 2006.257.04:31:55.58#ibcon#read 5, iclass 11, count 0 2006.257.04:31:55.58#ibcon#about to read 6, iclass 11, count 0 2006.257.04:31:55.58#ibcon#read 6, iclass 11, count 0 2006.257.04:31:55.58#ibcon#end of sib2, iclass 11, count 0 2006.257.04:31:55.58#ibcon#*after write, iclass 11, count 0 2006.257.04:31:55.58#ibcon#*before return 0, iclass 11, count 0 2006.257.04:31:55.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:55.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:31:55.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.04:31:55.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.04:31:55.58$vck44/vblo=3,649.99 2006.257.04:31:55.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.04:31:55.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.04:31:55.58#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:55.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:55.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:55.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:55.58#ibcon#enter wrdev, iclass 13, count 0 2006.257.04:31:55.58#ibcon#first serial, iclass 13, count 0 2006.257.04:31:55.58#ibcon#enter sib2, iclass 13, count 0 2006.257.04:31:55.58#ibcon#flushed, iclass 13, count 0 2006.257.04:31:55.58#ibcon#about to write, iclass 13, count 0 2006.257.04:31:55.58#ibcon#wrote, iclass 13, count 0 2006.257.04:31:55.58#ibcon#about to read 3, iclass 13, count 0 2006.257.04:31:55.60#ibcon#read 3, iclass 13, count 0 2006.257.04:31:55.60#ibcon#about to read 4, iclass 13, count 0 2006.257.04:31:55.60#ibcon#read 4, iclass 13, count 0 2006.257.04:31:55.60#ibcon#about to read 5, iclass 13, count 0 2006.257.04:31:55.60#ibcon#read 5, iclass 13, count 0 2006.257.04:31:55.60#ibcon#about to read 6, iclass 13, count 0 2006.257.04:31:55.60#ibcon#read 6, iclass 13, count 0 2006.257.04:31:55.60#ibcon#end of sib2, iclass 13, count 0 2006.257.04:31:55.60#ibcon#*mode == 0, iclass 13, count 0 2006.257.04:31:55.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.04:31:55.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.04:31:55.60#ibcon#*before write, iclass 13, count 0 2006.257.04:31:55.60#ibcon#enter sib2, iclass 13, count 0 2006.257.04:31:55.60#ibcon#flushed, iclass 13, count 0 2006.257.04:31:55.60#ibcon#about to write, iclass 13, count 0 2006.257.04:31:55.60#ibcon#wrote, iclass 13, count 0 2006.257.04:31:55.60#ibcon#about to read 3, iclass 13, count 0 2006.257.04:31:55.64#ibcon#read 3, iclass 13, count 0 2006.257.04:31:55.64#ibcon#about to read 4, iclass 13, count 0 2006.257.04:31:55.64#ibcon#read 4, iclass 13, count 0 2006.257.04:31:55.64#ibcon#about to read 5, iclass 13, count 0 2006.257.04:31:55.64#ibcon#read 5, iclass 13, count 0 2006.257.04:31:55.64#ibcon#about to read 6, iclass 13, count 0 2006.257.04:31:55.64#ibcon#read 6, iclass 13, count 0 2006.257.04:31:55.64#ibcon#end of sib2, iclass 13, count 0 2006.257.04:31:55.64#ibcon#*after write, iclass 13, count 0 2006.257.04:31:55.64#ibcon#*before return 0, iclass 13, count 0 2006.257.04:31:55.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:55.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:31:55.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.04:31:55.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.04:31:55.64$vck44/vb=3,4 2006.257.04:31:55.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.04:31:55.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.04:31:55.64#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:55.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:55.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:55.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:55.70#ibcon#enter wrdev, iclass 15, count 2 2006.257.04:31:55.70#ibcon#first serial, iclass 15, count 2 2006.257.04:31:55.70#ibcon#enter sib2, iclass 15, count 2 2006.257.04:31:55.70#ibcon#flushed, iclass 15, count 2 2006.257.04:31:55.70#ibcon#about to write, iclass 15, count 2 2006.257.04:31:55.70#ibcon#wrote, iclass 15, count 2 2006.257.04:31:55.70#ibcon#about to read 3, iclass 15, count 2 2006.257.04:31:55.72#ibcon#read 3, iclass 15, count 2 2006.257.04:31:55.72#ibcon#about to read 4, iclass 15, count 2 2006.257.04:31:55.72#ibcon#read 4, iclass 15, count 2 2006.257.04:31:55.72#ibcon#about to read 5, iclass 15, count 2 2006.257.04:31:55.72#ibcon#read 5, iclass 15, count 2 2006.257.04:31:55.72#ibcon#about to read 6, iclass 15, count 2 2006.257.04:31:55.72#ibcon#read 6, iclass 15, count 2 2006.257.04:31:55.72#ibcon#end of sib2, iclass 15, count 2 2006.257.04:31:55.72#ibcon#*mode == 0, iclass 15, count 2 2006.257.04:31:55.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.04:31:55.72#ibcon#[27=AT03-04\r\n] 2006.257.04:31:55.72#ibcon#*before write, iclass 15, count 2 2006.257.04:31:55.72#ibcon#enter sib2, iclass 15, count 2 2006.257.04:31:55.72#ibcon#flushed, iclass 15, count 2 2006.257.04:31:55.72#ibcon#about to write, iclass 15, count 2 2006.257.04:31:55.72#ibcon#wrote, iclass 15, count 2 2006.257.04:31:55.72#ibcon#about to read 3, iclass 15, count 2 2006.257.04:31:55.75#ibcon#read 3, iclass 15, count 2 2006.257.04:31:55.75#ibcon#about to read 4, iclass 15, count 2 2006.257.04:31:55.75#ibcon#read 4, iclass 15, count 2 2006.257.04:31:55.75#ibcon#about to read 5, iclass 15, count 2 2006.257.04:31:55.75#ibcon#read 5, iclass 15, count 2 2006.257.04:31:55.75#ibcon#about to read 6, iclass 15, count 2 2006.257.04:31:55.75#ibcon#read 6, iclass 15, count 2 2006.257.04:31:55.75#ibcon#end of sib2, iclass 15, count 2 2006.257.04:31:55.75#ibcon#*after write, iclass 15, count 2 2006.257.04:31:55.75#ibcon#*before return 0, iclass 15, count 2 2006.257.04:31:55.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:55.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:31:55.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.04:31:55.75#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:55.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:55.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:55.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:55.87#ibcon#enter wrdev, iclass 15, count 0 2006.257.04:31:55.87#ibcon#first serial, iclass 15, count 0 2006.257.04:31:55.87#ibcon#enter sib2, iclass 15, count 0 2006.257.04:31:55.87#ibcon#flushed, iclass 15, count 0 2006.257.04:31:55.87#ibcon#about to write, iclass 15, count 0 2006.257.04:31:55.87#ibcon#wrote, iclass 15, count 0 2006.257.04:31:55.87#ibcon#about to read 3, iclass 15, count 0 2006.257.04:31:55.89#ibcon#read 3, iclass 15, count 0 2006.257.04:31:55.89#ibcon#about to read 4, iclass 15, count 0 2006.257.04:31:55.89#ibcon#read 4, iclass 15, count 0 2006.257.04:31:55.89#ibcon#about to read 5, iclass 15, count 0 2006.257.04:31:55.89#ibcon#read 5, iclass 15, count 0 2006.257.04:31:55.89#ibcon#about to read 6, iclass 15, count 0 2006.257.04:31:55.89#ibcon#read 6, iclass 15, count 0 2006.257.04:31:55.89#ibcon#end of sib2, iclass 15, count 0 2006.257.04:31:55.89#ibcon#*mode == 0, iclass 15, count 0 2006.257.04:31:55.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.04:31:55.89#ibcon#[27=USB\r\n] 2006.257.04:31:55.89#ibcon#*before write, iclass 15, count 0 2006.257.04:31:55.89#ibcon#enter sib2, iclass 15, count 0 2006.257.04:31:55.89#ibcon#flushed, iclass 15, count 0 2006.257.04:31:55.89#ibcon#about to write, iclass 15, count 0 2006.257.04:31:55.89#ibcon#wrote, iclass 15, count 0 2006.257.04:31:55.89#ibcon#about to read 3, iclass 15, count 0 2006.257.04:31:55.92#ibcon#read 3, iclass 15, count 0 2006.257.04:31:55.92#ibcon#about to read 4, iclass 15, count 0 2006.257.04:31:55.92#ibcon#read 4, iclass 15, count 0 2006.257.04:31:55.92#ibcon#about to read 5, iclass 15, count 0 2006.257.04:31:55.92#ibcon#read 5, iclass 15, count 0 2006.257.04:31:55.92#ibcon#about to read 6, iclass 15, count 0 2006.257.04:31:55.92#ibcon#read 6, iclass 15, count 0 2006.257.04:31:55.92#ibcon#end of sib2, iclass 15, count 0 2006.257.04:31:55.92#ibcon#*after write, iclass 15, count 0 2006.257.04:31:55.92#ibcon#*before return 0, iclass 15, count 0 2006.257.04:31:55.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:55.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:31:55.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.04:31:55.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.04:31:55.92$vck44/vblo=4,679.99 2006.257.04:31:55.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.04:31:55.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.04:31:55.92#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:55.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:55.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:55.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:55.92#ibcon#enter wrdev, iclass 17, count 0 2006.257.04:31:55.92#ibcon#first serial, iclass 17, count 0 2006.257.04:31:55.92#ibcon#enter sib2, iclass 17, count 0 2006.257.04:31:55.92#ibcon#flushed, iclass 17, count 0 2006.257.04:31:55.92#ibcon#about to write, iclass 17, count 0 2006.257.04:31:55.92#ibcon#wrote, iclass 17, count 0 2006.257.04:31:55.92#ibcon#about to read 3, iclass 17, count 0 2006.257.04:31:55.94#ibcon#read 3, iclass 17, count 0 2006.257.04:31:55.94#ibcon#about to read 4, iclass 17, count 0 2006.257.04:31:55.94#ibcon#read 4, iclass 17, count 0 2006.257.04:31:55.94#ibcon#about to read 5, iclass 17, count 0 2006.257.04:31:55.94#ibcon#read 5, iclass 17, count 0 2006.257.04:31:55.94#ibcon#about to read 6, iclass 17, count 0 2006.257.04:31:55.94#ibcon#read 6, iclass 17, count 0 2006.257.04:31:55.94#ibcon#end of sib2, iclass 17, count 0 2006.257.04:31:55.94#ibcon#*mode == 0, iclass 17, count 0 2006.257.04:31:55.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.04:31:55.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.04:31:55.94#ibcon#*before write, iclass 17, count 0 2006.257.04:31:55.94#ibcon#enter sib2, iclass 17, count 0 2006.257.04:31:55.94#ibcon#flushed, iclass 17, count 0 2006.257.04:31:55.94#ibcon#about to write, iclass 17, count 0 2006.257.04:31:55.94#ibcon#wrote, iclass 17, count 0 2006.257.04:31:55.94#ibcon#about to read 3, iclass 17, count 0 2006.257.04:31:55.98#ibcon#read 3, iclass 17, count 0 2006.257.04:31:55.98#ibcon#about to read 4, iclass 17, count 0 2006.257.04:31:55.98#ibcon#read 4, iclass 17, count 0 2006.257.04:31:55.98#ibcon#about to read 5, iclass 17, count 0 2006.257.04:31:55.98#ibcon#read 5, iclass 17, count 0 2006.257.04:31:55.98#ibcon#about to read 6, iclass 17, count 0 2006.257.04:31:55.98#ibcon#read 6, iclass 17, count 0 2006.257.04:31:55.98#ibcon#end of sib2, iclass 17, count 0 2006.257.04:31:55.98#ibcon#*after write, iclass 17, count 0 2006.257.04:31:55.98#ibcon#*before return 0, iclass 17, count 0 2006.257.04:31:55.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:55.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:31:55.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.04:31:55.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.04:31:55.98$vck44/vb=4,5 2006.257.04:31:55.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.04:31:55.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.04:31:55.98#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:55.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:56.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:56.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:56.04#ibcon#enter wrdev, iclass 19, count 2 2006.257.04:31:56.04#ibcon#first serial, iclass 19, count 2 2006.257.04:31:56.04#ibcon#enter sib2, iclass 19, count 2 2006.257.04:31:56.04#ibcon#flushed, iclass 19, count 2 2006.257.04:31:56.04#ibcon#about to write, iclass 19, count 2 2006.257.04:31:56.04#ibcon#wrote, iclass 19, count 2 2006.257.04:31:56.04#ibcon#about to read 3, iclass 19, count 2 2006.257.04:31:56.06#ibcon#read 3, iclass 19, count 2 2006.257.04:31:56.06#ibcon#about to read 4, iclass 19, count 2 2006.257.04:31:56.06#ibcon#read 4, iclass 19, count 2 2006.257.04:31:56.06#ibcon#about to read 5, iclass 19, count 2 2006.257.04:31:56.06#ibcon#read 5, iclass 19, count 2 2006.257.04:31:56.06#ibcon#about to read 6, iclass 19, count 2 2006.257.04:31:56.06#ibcon#read 6, iclass 19, count 2 2006.257.04:31:56.06#ibcon#end of sib2, iclass 19, count 2 2006.257.04:31:56.06#ibcon#*mode == 0, iclass 19, count 2 2006.257.04:31:56.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.04:31:56.06#ibcon#[27=AT04-05\r\n] 2006.257.04:31:56.06#ibcon#*before write, iclass 19, count 2 2006.257.04:31:56.06#ibcon#enter sib2, iclass 19, count 2 2006.257.04:31:56.06#ibcon#flushed, iclass 19, count 2 2006.257.04:31:56.06#ibcon#about to write, iclass 19, count 2 2006.257.04:31:56.06#ibcon#wrote, iclass 19, count 2 2006.257.04:31:56.06#ibcon#about to read 3, iclass 19, count 2 2006.257.04:31:56.06#abcon#<5=/14 2.2 6.2 19.51 931012.0\r\n> 2006.257.04:31:56.08#abcon#{5=INTERFACE CLEAR} 2006.257.04:31:56.09#ibcon#read 3, iclass 19, count 2 2006.257.04:31:56.09#ibcon#about to read 4, iclass 19, count 2 2006.257.04:31:56.09#ibcon#read 4, iclass 19, count 2 2006.257.04:31:56.09#ibcon#about to read 5, iclass 19, count 2 2006.257.04:31:56.09#ibcon#read 5, iclass 19, count 2 2006.257.04:31:56.09#ibcon#about to read 6, iclass 19, count 2 2006.257.04:31:56.09#ibcon#read 6, iclass 19, count 2 2006.257.04:31:56.09#ibcon#end of sib2, iclass 19, count 2 2006.257.04:31:56.09#ibcon#*after write, iclass 19, count 2 2006.257.04:31:56.09#ibcon#*before return 0, iclass 19, count 2 2006.257.04:31:56.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:56.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:31:56.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.04:31:56.09#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:56.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:56.14#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:31:56.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:56.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:56.21#ibcon#enter wrdev, iclass 19, count 0 2006.257.04:31:56.21#ibcon#first serial, iclass 19, count 0 2006.257.04:31:56.21#ibcon#enter sib2, iclass 19, count 0 2006.257.04:31:56.21#ibcon#flushed, iclass 19, count 0 2006.257.04:31:56.21#ibcon#about to write, iclass 19, count 0 2006.257.04:31:56.21#ibcon#wrote, iclass 19, count 0 2006.257.04:31:56.21#ibcon#about to read 3, iclass 19, count 0 2006.257.04:31:56.23#ibcon#read 3, iclass 19, count 0 2006.257.04:31:56.23#ibcon#about to read 4, iclass 19, count 0 2006.257.04:31:56.23#ibcon#read 4, iclass 19, count 0 2006.257.04:31:56.23#ibcon#about to read 5, iclass 19, count 0 2006.257.04:31:56.23#ibcon#read 5, iclass 19, count 0 2006.257.04:31:56.23#ibcon#about to read 6, iclass 19, count 0 2006.257.04:31:56.23#ibcon#read 6, iclass 19, count 0 2006.257.04:31:56.23#ibcon#end of sib2, iclass 19, count 0 2006.257.04:31:56.23#ibcon#*mode == 0, iclass 19, count 0 2006.257.04:31:56.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.04:31:56.23#ibcon#[27=USB\r\n] 2006.257.04:31:56.23#ibcon#*before write, iclass 19, count 0 2006.257.04:31:56.23#ibcon#enter sib2, iclass 19, count 0 2006.257.04:31:56.23#ibcon#flushed, iclass 19, count 0 2006.257.04:31:56.23#ibcon#about to write, iclass 19, count 0 2006.257.04:31:56.23#ibcon#wrote, iclass 19, count 0 2006.257.04:31:56.23#ibcon#about to read 3, iclass 19, count 0 2006.257.04:31:56.26#ibcon#read 3, iclass 19, count 0 2006.257.04:31:56.26#ibcon#about to read 4, iclass 19, count 0 2006.257.04:31:56.26#ibcon#read 4, iclass 19, count 0 2006.257.04:31:56.26#ibcon#about to read 5, iclass 19, count 0 2006.257.04:31:56.26#ibcon#read 5, iclass 19, count 0 2006.257.04:31:56.26#ibcon#about to read 6, iclass 19, count 0 2006.257.04:31:56.26#ibcon#read 6, iclass 19, count 0 2006.257.04:31:56.26#ibcon#end of sib2, iclass 19, count 0 2006.257.04:31:56.26#ibcon#*after write, iclass 19, count 0 2006.257.04:31:56.26#ibcon#*before return 0, iclass 19, count 0 2006.257.04:31:56.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:56.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:31:56.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.04:31:56.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.04:31:56.26$vck44/vblo=5,709.99 2006.257.04:31:56.26#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.04:31:56.26#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.04:31:56.26#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:56.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:56.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:56.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:56.26#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:31:56.26#ibcon#first serial, iclass 25, count 0 2006.257.04:31:56.26#ibcon#enter sib2, iclass 25, count 0 2006.257.04:31:56.26#ibcon#flushed, iclass 25, count 0 2006.257.04:31:56.26#ibcon#about to write, iclass 25, count 0 2006.257.04:31:56.26#ibcon#wrote, iclass 25, count 0 2006.257.04:31:56.26#ibcon#about to read 3, iclass 25, count 0 2006.257.04:31:56.28#ibcon#read 3, iclass 25, count 0 2006.257.04:31:56.28#ibcon#about to read 4, iclass 25, count 0 2006.257.04:31:56.28#ibcon#read 4, iclass 25, count 0 2006.257.04:31:56.28#ibcon#about to read 5, iclass 25, count 0 2006.257.04:31:56.28#ibcon#read 5, iclass 25, count 0 2006.257.04:31:56.28#ibcon#about to read 6, iclass 25, count 0 2006.257.04:31:56.28#ibcon#read 6, iclass 25, count 0 2006.257.04:31:56.28#ibcon#end of sib2, iclass 25, count 0 2006.257.04:31:56.28#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:31:56.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:31:56.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.04:31:56.28#ibcon#*before write, iclass 25, count 0 2006.257.04:31:56.28#ibcon#enter sib2, iclass 25, count 0 2006.257.04:31:56.28#ibcon#flushed, iclass 25, count 0 2006.257.04:31:56.28#ibcon#about to write, iclass 25, count 0 2006.257.04:31:56.28#ibcon#wrote, iclass 25, count 0 2006.257.04:31:56.28#ibcon#about to read 3, iclass 25, count 0 2006.257.04:31:56.32#ibcon#read 3, iclass 25, count 0 2006.257.04:31:56.32#ibcon#about to read 4, iclass 25, count 0 2006.257.04:31:56.32#ibcon#read 4, iclass 25, count 0 2006.257.04:31:56.32#ibcon#about to read 5, iclass 25, count 0 2006.257.04:31:56.32#ibcon#read 5, iclass 25, count 0 2006.257.04:31:56.32#ibcon#about to read 6, iclass 25, count 0 2006.257.04:31:56.32#ibcon#read 6, iclass 25, count 0 2006.257.04:31:56.32#ibcon#end of sib2, iclass 25, count 0 2006.257.04:31:56.32#ibcon#*after write, iclass 25, count 0 2006.257.04:31:56.32#ibcon#*before return 0, iclass 25, count 0 2006.257.04:31:56.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:56.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:31:56.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:31:56.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:31:56.32$vck44/vb=5,4 2006.257.04:31:56.32#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.04:31:56.32#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.04:31:56.32#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:56.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:56.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:56.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:56.38#ibcon#enter wrdev, iclass 27, count 2 2006.257.04:31:56.38#ibcon#first serial, iclass 27, count 2 2006.257.04:31:56.38#ibcon#enter sib2, iclass 27, count 2 2006.257.04:31:56.38#ibcon#flushed, iclass 27, count 2 2006.257.04:31:56.38#ibcon#about to write, iclass 27, count 2 2006.257.04:31:56.38#ibcon#wrote, iclass 27, count 2 2006.257.04:31:56.38#ibcon#about to read 3, iclass 27, count 2 2006.257.04:31:56.40#ibcon#read 3, iclass 27, count 2 2006.257.04:31:56.40#ibcon#about to read 4, iclass 27, count 2 2006.257.04:31:56.40#ibcon#read 4, iclass 27, count 2 2006.257.04:31:56.40#ibcon#about to read 5, iclass 27, count 2 2006.257.04:31:56.40#ibcon#read 5, iclass 27, count 2 2006.257.04:31:56.40#ibcon#about to read 6, iclass 27, count 2 2006.257.04:31:56.40#ibcon#read 6, iclass 27, count 2 2006.257.04:31:56.40#ibcon#end of sib2, iclass 27, count 2 2006.257.04:31:56.40#ibcon#*mode == 0, iclass 27, count 2 2006.257.04:31:56.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.04:31:56.40#ibcon#[27=AT05-04\r\n] 2006.257.04:31:56.40#ibcon#*before write, iclass 27, count 2 2006.257.04:31:56.40#ibcon#enter sib2, iclass 27, count 2 2006.257.04:31:56.40#ibcon#flushed, iclass 27, count 2 2006.257.04:31:56.40#ibcon#about to write, iclass 27, count 2 2006.257.04:31:56.40#ibcon#wrote, iclass 27, count 2 2006.257.04:31:56.40#ibcon#about to read 3, iclass 27, count 2 2006.257.04:31:56.43#ibcon#read 3, iclass 27, count 2 2006.257.04:31:56.43#ibcon#about to read 4, iclass 27, count 2 2006.257.04:31:56.43#ibcon#read 4, iclass 27, count 2 2006.257.04:31:56.43#ibcon#about to read 5, iclass 27, count 2 2006.257.04:31:56.43#ibcon#read 5, iclass 27, count 2 2006.257.04:31:56.43#ibcon#about to read 6, iclass 27, count 2 2006.257.04:31:56.43#ibcon#read 6, iclass 27, count 2 2006.257.04:31:56.43#ibcon#end of sib2, iclass 27, count 2 2006.257.04:31:56.43#ibcon#*after write, iclass 27, count 2 2006.257.04:31:56.43#ibcon#*before return 0, iclass 27, count 2 2006.257.04:31:56.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:56.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:31:56.43#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.04:31:56.43#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:56.43#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:56.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:56.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:56.55#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:31:56.55#ibcon#first serial, iclass 27, count 0 2006.257.04:31:56.55#ibcon#enter sib2, iclass 27, count 0 2006.257.04:31:56.55#ibcon#flushed, iclass 27, count 0 2006.257.04:31:56.55#ibcon#about to write, iclass 27, count 0 2006.257.04:31:56.55#ibcon#wrote, iclass 27, count 0 2006.257.04:31:56.55#ibcon#about to read 3, iclass 27, count 0 2006.257.04:31:56.57#ibcon#read 3, iclass 27, count 0 2006.257.04:31:56.57#ibcon#about to read 4, iclass 27, count 0 2006.257.04:31:56.57#ibcon#read 4, iclass 27, count 0 2006.257.04:31:56.57#ibcon#about to read 5, iclass 27, count 0 2006.257.04:31:56.57#ibcon#read 5, iclass 27, count 0 2006.257.04:31:56.57#ibcon#about to read 6, iclass 27, count 0 2006.257.04:31:56.57#ibcon#read 6, iclass 27, count 0 2006.257.04:31:56.57#ibcon#end of sib2, iclass 27, count 0 2006.257.04:31:56.57#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:31:56.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:31:56.57#ibcon#[27=USB\r\n] 2006.257.04:31:56.57#ibcon#*before write, iclass 27, count 0 2006.257.04:31:56.57#ibcon#enter sib2, iclass 27, count 0 2006.257.04:31:56.57#ibcon#flushed, iclass 27, count 0 2006.257.04:31:56.57#ibcon#about to write, iclass 27, count 0 2006.257.04:31:56.57#ibcon#wrote, iclass 27, count 0 2006.257.04:31:56.57#ibcon#about to read 3, iclass 27, count 0 2006.257.04:31:56.60#ibcon#read 3, iclass 27, count 0 2006.257.04:31:56.60#ibcon#about to read 4, iclass 27, count 0 2006.257.04:31:56.60#ibcon#read 4, iclass 27, count 0 2006.257.04:31:56.60#ibcon#about to read 5, iclass 27, count 0 2006.257.04:31:56.60#ibcon#read 5, iclass 27, count 0 2006.257.04:31:56.60#ibcon#about to read 6, iclass 27, count 0 2006.257.04:31:56.60#ibcon#read 6, iclass 27, count 0 2006.257.04:31:56.60#ibcon#end of sib2, iclass 27, count 0 2006.257.04:31:56.60#ibcon#*after write, iclass 27, count 0 2006.257.04:31:56.60#ibcon#*before return 0, iclass 27, count 0 2006.257.04:31:56.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:56.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:31:56.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:31:56.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:31:56.60$vck44/vblo=6,719.99 2006.257.04:31:56.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.04:31:56.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.04:31:56.60#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:56.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:56.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:56.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:56.60#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:31:56.60#ibcon#first serial, iclass 29, count 0 2006.257.04:31:56.60#ibcon#enter sib2, iclass 29, count 0 2006.257.04:31:56.60#ibcon#flushed, iclass 29, count 0 2006.257.04:31:56.60#ibcon#about to write, iclass 29, count 0 2006.257.04:31:56.60#ibcon#wrote, iclass 29, count 0 2006.257.04:31:56.60#ibcon#about to read 3, iclass 29, count 0 2006.257.04:31:56.62#ibcon#read 3, iclass 29, count 0 2006.257.04:31:56.62#ibcon#about to read 4, iclass 29, count 0 2006.257.04:31:56.62#ibcon#read 4, iclass 29, count 0 2006.257.04:31:56.62#ibcon#about to read 5, iclass 29, count 0 2006.257.04:31:56.62#ibcon#read 5, iclass 29, count 0 2006.257.04:31:56.62#ibcon#about to read 6, iclass 29, count 0 2006.257.04:31:56.62#ibcon#read 6, iclass 29, count 0 2006.257.04:31:56.62#ibcon#end of sib2, iclass 29, count 0 2006.257.04:31:56.62#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:31:56.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:31:56.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.04:31:56.62#ibcon#*before write, iclass 29, count 0 2006.257.04:31:56.62#ibcon#enter sib2, iclass 29, count 0 2006.257.04:31:56.62#ibcon#flushed, iclass 29, count 0 2006.257.04:31:56.62#ibcon#about to write, iclass 29, count 0 2006.257.04:31:56.62#ibcon#wrote, iclass 29, count 0 2006.257.04:31:56.62#ibcon#about to read 3, iclass 29, count 0 2006.257.04:31:56.66#ibcon#read 3, iclass 29, count 0 2006.257.04:31:56.66#ibcon#about to read 4, iclass 29, count 0 2006.257.04:31:56.66#ibcon#read 4, iclass 29, count 0 2006.257.04:31:56.66#ibcon#about to read 5, iclass 29, count 0 2006.257.04:31:56.66#ibcon#read 5, iclass 29, count 0 2006.257.04:31:56.66#ibcon#about to read 6, iclass 29, count 0 2006.257.04:31:56.66#ibcon#read 6, iclass 29, count 0 2006.257.04:31:56.66#ibcon#end of sib2, iclass 29, count 0 2006.257.04:31:56.66#ibcon#*after write, iclass 29, count 0 2006.257.04:31:56.66#ibcon#*before return 0, iclass 29, count 0 2006.257.04:31:56.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:56.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:31:56.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:31:56.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:31:56.66$vck44/vb=6,4 2006.257.04:31:56.66#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.04:31:56.66#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.04:31:56.66#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:56.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:56.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:56.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:56.72#ibcon#enter wrdev, iclass 31, count 2 2006.257.04:31:56.72#ibcon#first serial, iclass 31, count 2 2006.257.04:31:56.72#ibcon#enter sib2, iclass 31, count 2 2006.257.04:31:56.72#ibcon#flushed, iclass 31, count 2 2006.257.04:31:56.72#ibcon#about to write, iclass 31, count 2 2006.257.04:31:56.72#ibcon#wrote, iclass 31, count 2 2006.257.04:31:56.72#ibcon#about to read 3, iclass 31, count 2 2006.257.04:31:56.74#ibcon#read 3, iclass 31, count 2 2006.257.04:31:56.74#ibcon#about to read 4, iclass 31, count 2 2006.257.04:31:56.74#ibcon#read 4, iclass 31, count 2 2006.257.04:31:56.74#ibcon#about to read 5, iclass 31, count 2 2006.257.04:31:56.74#ibcon#read 5, iclass 31, count 2 2006.257.04:31:56.74#ibcon#about to read 6, iclass 31, count 2 2006.257.04:31:56.74#ibcon#read 6, iclass 31, count 2 2006.257.04:31:56.74#ibcon#end of sib2, iclass 31, count 2 2006.257.04:31:56.74#ibcon#*mode == 0, iclass 31, count 2 2006.257.04:31:56.74#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.04:31:56.74#ibcon#[27=AT06-04\r\n] 2006.257.04:31:56.74#ibcon#*before write, iclass 31, count 2 2006.257.04:31:56.74#ibcon#enter sib2, iclass 31, count 2 2006.257.04:31:56.74#ibcon#flushed, iclass 31, count 2 2006.257.04:31:56.74#ibcon#about to write, iclass 31, count 2 2006.257.04:31:56.74#ibcon#wrote, iclass 31, count 2 2006.257.04:31:56.74#ibcon#about to read 3, iclass 31, count 2 2006.257.04:31:56.77#ibcon#read 3, iclass 31, count 2 2006.257.04:31:56.77#ibcon#about to read 4, iclass 31, count 2 2006.257.04:31:56.77#ibcon#read 4, iclass 31, count 2 2006.257.04:31:56.77#ibcon#about to read 5, iclass 31, count 2 2006.257.04:31:56.77#ibcon#read 5, iclass 31, count 2 2006.257.04:31:56.77#ibcon#about to read 6, iclass 31, count 2 2006.257.04:31:56.77#ibcon#read 6, iclass 31, count 2 2006.257.04:31:56.77#ibcon#end of sib2, iclass 31, count 2 2006.257.04:31:56.77#ibcon#*after write, iclass 31, count 2 2006.257.04:31:56.77#ibcon#*before return 0, iclass 31, count 2 2006.257.04:31:56.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:56.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:31:56.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.04:31:56.77#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:56.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:56.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:56.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:56.89#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:31:56.89#ibcon#first serial, iclass 31, count 0 2006.257.04:31:56.89#ibcon#enter sib2, iclass 31, count 0 2006.257.04:31:56.89#ibcon#flushed, iclass 31, count 0 2006.257.04:31:56.89#ibcon#about to write, iclass 31, count 0 2006.257.04:31:56.89#ibcon#wrote, iclass 31, count 0 2006.257.04:31:56.89#ibcon#about to read 3, iclass 31, count 0 2006.257.04:31:56.91#ibcon#read 3, iclass 31, count 0 2006.257.04:31:56.91#ibcon#about to read 4, iclass 31, count 0 2006.257.04:31:56.91#ibcon#read 4, iclass 31, count 0 2006.257.04:31:56.91#ibcon#about to read 5, iclass 31, count 0 2006.257.04:31:56.91#ibcon#read 5, iclass 31, count 0 2006.257.04:31:56.91#ibcon#about to read 6, iclass 31, count 0 2006.257.04:31:56.91#ibcon#read 6, iclass 31, count 0 2006.257.04:31:56.91#ibcon#end of sib2, iclass 31, count 0 2006.257.04:31:56.91#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:31:56.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:31:56.91#ibcon#[27=USB\r\n] 2006.257.04:31:56.91#ibcon#*before write, iclass 31, count 0 2006.257.04:31:56.91#ibcon#enter sib2, iclass 31, count 0 2006.257.04:31:56.91#ibcon#flushed, iclass 31, count 0 2006.257.04:31:56.91#ibcon#about to write, iclass 31, count 0 2006.257.04:31:56.91#ibcon#wrote, iclass 31, count 0 2006.257.04:31:56.91#ibcon#about to read 3, iclass 31, count 0 2006.257.04:31:56.94#ibcon#read 3, iclass 31, count 0 2006.257.04:31:56.94#ibcon#about to read 4, iclass 31, count 0 2006.257.04:31:56.94#ibcon#read 4, iclass 31, count 0 2006.257.04:31:56.94#ibcon#about to read 5, iclass 31, count 0 2006.257.04:31:56.94#ibcon#read 5, iclass 31, count 0 2006.257.04:31:56.94#ibcon#about to read 6, iclass 31, count 0 2006.257.04:31:56.94#ibcon#read 6, iclass 31, count 0 2006.257.04:31:56.94#ibcon#end of sib2, iclass 31, count 0 2006.257.04:31:56.94#ibcon#*after write, iclass 31, count 0 2006.257.04:31:56.94#ibcon#*before return 0, iclass 31, count 0 2006.257.04:31:56.94#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:56.94#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:31:56.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:31:56.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:31:56.94$vck44/vblo=7,734.99 2006.257.04:31:56.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.04:31:56.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.04:31:56.94#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:56.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:56.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:56.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:56.94#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:31:56.94#ibcon#first serial, iclass 33, count 0 2006.257.04:31:56.94#ibcon#enter sib2, iclass 33, count 0 2006.257.04:31:56.94#ibcon#flushed, iclass 33, count 0 2006.257.04:31:56.94#ibcon#about to write, iclass 33, count 0 2006.257.04:31:56.94#ibcon#wrote, iclass 33, count 0 2006.257.04:31:56.94#ibcon#about to read 3, iclass 33, count 0 2006.257.04:31:56.96#ibcon#read 3, iclass 33, count 0 2006.257.04:31:56.96#ibcon#about to read 4, iclass 33, count 0 2006.257.04:31:56.96#ibcon#read 4, iclass 33, count 0 2006.257.04:31:56.96#ibcon#about to read 5, iclass 33, count 0 2006.257.04:31:56.96#ibcon#read 5, iclass 33, count 0 2006.257.04:31:56.96#ibcon#about to read 6, iclass 33, count 0 2006.257.04:31:56.96#ibcon#read 6, iclass 33, count 0 2006.257.04:31:56.96#ibcon#end of sib2, iclass 33, count 0 2006.257.04:31:56.96#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:31:56.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:31:56.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.04:31:56.96#ibcon#*before write, iclass 33, count 0 2006.257.04:31:56.96#ibcon#enter sib2, iclass 33, count 0 2006.257.04:31:56.96#ibcon#flushed, iclass 33, count 0 2006.257.04:31:56.96#ibcon#about to write, iclass 33, count 0 2006.257.04:31:56.96#ibcon#wrote, iclass 33, count 0 2006.257.04:31:56.96#ibcon#about to read 3, iclass 33, count 0 2006.257.04:31:57.00#ibcon#read 3, iclass 33, count 0 2006.257.04:31:57.00#ibcon#about to read 4, iclass 33, count 0 2006.257.04:31:57.00#ibcon#read 4, iclass 33, count 0 2006.257.04:31:57.00#ibcon#about to read 5, iclass 33, count 0 2006.257.04:31:57.00#ibcon#read 5, iclass 33, count 0 2006.257.04:31:57.00#ibcon#about to read 6, iclass 33, count 0 2006.257.04:31:57.00#ibcon#read 6, iclass 33, count 0 2006.257.04:31:57.00#ibcon#end of sib2, iclass 33, count 0 2006.257.04:31:57.00#ibcon#*after write, iclass 33, count 0 2006.257.04:31:57.00#ibcon#*before return 0, iclass 33, count 0 2006.257.04:31:57.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:57.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:31:57.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:31:57.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:31:57.00$vck44/vb=7,4 2006.257.04:31:57.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.04:31:57.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.04:31:57.00#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:57.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:57.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:57.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:57.06#ibcon#enter wrdev, iclass 35, count 2 2006.257.04:31:57.06#ibcon#first serial, iclass 35, count 2 2006.257.04:31:57.06#ibcon#enter sib2, iclass 35, count 2 2006.257.04:31:57.06#ibcon#flushed, iclass 35, count 2 2006.257.04:31:57.06#ibcon#about to write, iclass 35, count 2 2006.257.04:31:57.06#ibcon#wrote, iclass 35, count 2 2006.257.04:31:57.06#ibcon#about to read 3, iclass 35, count 2 2006.257.04:31:57.08#ibcon#read 3, iclass 35, count 2 2006.257.04:31:57.08#ibcon#about to read 4, iclass 35, count 2 2006.257.04:31:57.08#ibcon#read 4, iclass 35, count 2 2006.257.04:31:57.08#ibcon#about to read 5, iclass 35, count 2 2006.257.04:31:57.08#ibcon#read 5, iclass 35, count 2 2006.257.04:31:57.08#ibcon#about to read 6, iclass 35, count 2 2006.257.04:31:57.08#ibcon#read 6, iclass 35, count 2 2006.257.04:31:57.08#ibcon#end of sib2, iclass 35, count 2 2006.257.04:31:57.08#ibcon#*mode == 0, iclass 35, count 2 2006.257.04:31:57.08#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.04:31:57.08#ibcon#[27=AT07-04\r\n] 2006.257.04:31:57.08#ibcon#*before write, iclass 35, count 2 2006.257.04:31:57.08#ibcon#enter sib2, iclass 35, count 2 2006.257.04:31:57.08#ibcon#flushed, iclass 35, count 2 2006.257.04:31:57.08#ibcon#about to write, iclass 35, count 2 2006.257.04:31:57.08#ibcon#wrote, iclass 35, count 2 2006.257.04:31:57.08#ibcon#about to read 3, iclass 35, count 2 2006.257.04:31:57.11#ibcon#read 3, iclass 35, count 2 2006.257.04:31:57.11#ibcon#about to read 4, iclass 35, count 2 2006.257.04:31:57.11#ibcon#read 4, iclass 35, count 2 2006.257.04:31:57.11#ibcon#about to read 5, iclass 35, count 2 2006.257.04:31:57.11#ibcon#read 5, iclass 35, count 2 2006.257.04:31:57.11#ibcon#about to read 6, iclass 35, count 2 2006.257.04:31:57.11#ibcon#read 6, iclass 35, count 2 2006.257.04:31:57.11#ibcon#end of sib2, iclass 35, count 2 2006.257.04:31:57.11#ibcon#*after write, iclass 35, count 2 2006.257.04:31:57.11#ibcon#*before return 0, iclass 35, count 2 2006.257.04:31:57.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:57.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:31:57.11#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.04:31:57.11#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:57.11#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:57.23#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:57.23#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:57.23#ibcon#enter wrdev, iclass 35, count 0 2006.257.04:31:57.23#ibcon#first serial, iclass 35, count 0 2006.257.04:31:57.23#ibcon#enter sib2, iclass 35, count 0 2006.257.04:31:57.23#ibcon#flushed, iclass 35, count 0 2006.257.04:31:57.23#ibcon#about to write, iclass 35, count 0 2006.257.04:31:57.23#ibcon#wrote, iclass 35, count 0 2006.257.04:31:57.23#ibcon#about to read 3, iclass 35, count 0 2006.257.04:31:57.25#ibcon#read 3, iclass 35, count 0 2006.257.04:31:57.25#ibcon#about to read 4, iclass 35, count 0 2006.257.04:31:57.25#ibcon#read 4, iclass 35, count 0 2006.257.04:31:57.25#ibcon#about to read 5, iclass 35, count 0 2006.257.04:31:57.25#ibcon#read 5, iclass 35, count 0 2006.257.04:31:57.25#ibcon#about to read 6, iclass 35, count 0 2006.257.04:31:57.25#ibcon#read 6, iclass 35, count 0 2006.257.04:31:57.25#ibcon#end of sib2, iclass 35, count 0 2006.257.04:31:57.25#ibcon#*mode == 0, iclass 35, count 0 2006.257.04:31:57.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.04:31:57.25#ibcon#[27=USB\r\n] 2006.257.04:31:57.25#ibcon#*before write, iclass 35, count 0 2006.257.04:31:57.25#ibcon#enter sib2, iclass 35, count 0 2006.257.04:31:57.25#ibcon#flushed, iclass 35, count 0 2006.257.04:31:57.25#ibcon#about to write, iclass 35, count 0 2006.257.04:31:57.25#ibcon#wrote, iclass 35, count 0 2006.257.04:31:57.25#ibcon#about to read 3, iclass 35, count 0 2006.257.04:31:57.28#ibcon#read 3, iclass 35, count 0 2006.257.04:31:57.28#ibcon#about to read 4, iclass 35, count 0 2006.257.04:31:57.28#ibcon#read 4, iclass 35, count 0 2006.257.04:31:57.28#ibcon#about to read 5, iclass 35, count 0 2006.257.04:31:57.28#ibcon#read 5, iclass 35, count 0 2006.257.04:31:57.28#ibcon#about to read 6, iclass 35, count 0 2006.257.04:31:57.28#ibcon#read 6, iclass 35, count 0 2006.257.04:31:57.28#ibcon#end of sib2, iclass 35, count 0 2006.257.04:31:57.28#ibcon#*after write, iclass 35, count 0 2006.257.04:31:57.28#ibcon#*before return 0, iclass 35, count 0 2006.257.04:31:57.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:57.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:31:57.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.04:31:57.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.04:31:57.28$vck44/vblo=8,744.99 2006.257.04:31:57.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.04:31:57.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.04:31:57.28#ibcon#ireg 17 cls_cnt 0 2006.257.04:31:57.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:57.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:57.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:57.28#ibcon#enter wrdev, iclass 37, count 0 2006.257.04:31:57.28#ibcon#first serial, iclass 37, count 0 2006.257.04:31:57.28#ibcon#enter sib2, iclass 37, count 0 2006.257.04:31:57.28#ibcon#flushed, iclass 37, count 0 2006.257.04:31:57.28#ibcon#about to write, iclass 37, count 0 2006.257.04:31:57.28#ibcon#wrote, iclass 37, count 0 2006.257.04:31:57.28#ibcon#about to read 3, iclass 37, count 0 2006.257.04:31:57.30#ibcon#read 3, iclass 37, count 0 2006.257.04:31:57.30#ibcon#about to read 4, iclass 37, count 0 2006.257.04:31:57.30#ibcon#read 4, iclass 37, count 0 2006.257.04:31:57.30#ibcon#about to read 5, iclass 37, count 0 2006.257.04:31:57.30#ibcon#read 5, iclass 37, count 0 2006.257.04:31:57.30#ibcon#about to read 6, iclass 37, count 0 2006.257.04:31:57.30#ibcon#read 6, iclass 37, count 0 2006.257.04:31:57.30#ibcon#end of sib2, iclass 37, count 0 2006.257.04:31:57.30#ibcon#*mode == 0, iclass 37, count 0 2006.257.04:31:57.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.04:31:57.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.04:31:57.30#ibcon#*before write, iclass 37, count 0 2006.257.04:31:57.30#ibcon#enter sib2, iclass 37, count 0 2006.257.04:31:57.30#ibcon#flushed, iclass 37, count 0 2006.257.04:31:57.30#ibcon#about to write, iclass 37, count 0 2006.257.04:31:57.30#ibcon#wrote, iclass 37, count 0 2006.257.04:31:57.30#ibcon#about to read 3, iclass 37, count 0 2006.257.04:31:57.34#ibcon#read 3, iclass 37, count 0 2006.257.04:31:57.34#ibcon#about to read 4, iclass 37, count 0 2006.257.04:31:57.34#ibcon#read 4, iclass 37, count 0 2006.257.04:31:57.34#ibcon#about to read 5, iclass 37, count 0 2006.257.04:31:57.34#ibcon#read 5, iclass 37, count 0 2006.257.04:31:57.34#ibcon#about to read 6, iclass 37, count 0 2006.257.04:31:57.34#ibcon#read 6, iclass 37, count 0 2006.257.04:31:57.34#ibcon#end of sib2, iclass 37, count 0 2006.257.04:31:57.34#ibcon#*after write, iclass 37, count 0 2006.257.04:31:57.34#ibcon#*before return 0, iclass 37, count 0 2006.257.04:31:57.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:57.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:31:57.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.04:31:57.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.04:31:57.34$vck44/vb=8,4 2006.257.04:31:57.34#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.04:31:57.34#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.04:31:57.34#ibcon#ireg 11 cls_cnt 2 2006.257.04:31:57.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:57.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:57.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:57.40#ibcon#enter wrdev, iclass 39, count 2 2006.257.04:31:57.40#ibcon#first serial, iclass 39, count 2 2006.257.04:31:57.40#ibcon#enter sib2, iclass 39, count 2 2006.257.04:31:57.40#ibcon#flushed, iclass 39, count 2 2006.257.04:31:57.40#ibcon#about to write, iclass 39, count 2 2006.257.04:31:57.40#ibcon#wrote, iclass 39, count 2 2006.257.04:31:57.40#ibcon#about to read 3, iclass 39, count 2 2006.257.04:31:57.42#ibcon#read 3, iclass 39, count 2 2006.257.04:31:57.42#ibcon#about to read 4, iclass 39, count 2 2006.257.04:31:57.42#ibcon#read 4, iclass 39, count 2 2006.257.04:31:57.42#ibcon#about to read 5, iclass 39, count 2 2006.257.04:31:57.42#ibcon#read 5, iclass 39, count 2 2006.257.04:31:57.42#ibcon#about to read 6, iclass 39, count 2 2006.257.04:31:57.42#ibcon#read 6, iclass 39, count 2 2006.257.04:31:57.42#ibcon#end of sib2, iclass 39, count 2 2006.257.04:31:57.42#ibcon#*mode == 0, iclass 39, count 2 2006.257.04:31:57.42#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.04:31:57.42#ibcon#[27=AT08-04\r\n] 2006.257.04:31:57.42#ibcon#*before write, iclass 39, count 2 2006.257.04:31:57.42#ibcon#enter sib2, iclass 39, count 2 2006.257.04:31:57.42#ibcon#flushed, iclass 39, count 2 2006.257.04:31:57.42#ibcon#about to write, iclass 39, count 2 2006.257.04:31:57.42#ibcon#wrote, iclass 39, count 2 2006.257.04:31:57.42#ibcon#about to read 3, iclass 39, count 2 2006.257.04:31:57.45#ibcon#read 3, iclass 39, count 2 2006.257.04:31:57.45#ibcon#about to read 4, iclass 39, count 2 2006.257.04:31:57.45#ibcon#read 4, iclass 39, count 2 2006.257.04:31:57.45#ibcon#about to read 5, iclass 39, count 2 2006.257.04:31:57.45#ibcon#read 5, iclass 39, count 2 2006.257.04:31:57.45#ibcon#about to read 6, iclass 39, count 2 2006.257.04:31:57.45#ibcon#read 6, iclass 39, count 2 2006.257.04:31:57.45#ibcon#end of sib2, iclass 39, count 2 2006.257.04:31:57.45#ibcon#*after write, iclass 39, count 2 2006.257.04:31:57.45#ibcon#*before return 0, iclass 39, count 2 2006.257.04:31:57.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:57.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:31:57.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.04:31:57.45#ibcon#ireg 7 cls_cnt 0 2006.257.04:31:57.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:57.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:57.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:57.57#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:31:57.57#ibcon#first serial, iclass 39, count 0 2006.257.04:31:57.57#ibcon#enter sib2, iclass 39, count 0 2006.257.04:31:57.57#ibcon#flushed, iclass 39, count 0 2006.257.04:31:57.57#ibcon#about to write, iclass 39, count 0 2006.257.04:31:57.57#ibcon#wrote, iclass 39, count 0 2006.257.04:31:57.57#ibcon#about to read 3, iclass 39, count 0 2006.257.04:31:57.59#ibcon#read 3, iclass 39, count 0 2006.257.04:31:57.59#ibcon#about to read 4, iclass 39, count 0 2006.257.04:31:57.59#ibcon#read 4, iclass 39, count 0 2006.257.04:31:57.59#ibcon#about to read 5, iclass 39, count 0 2006.257.04:31:57.59#ibcon#read 5, iclass 39, count 0 2006.257.04:31:57.59#ibcon#about to read 6, iclass 39, count 0 2006.257.04:31:57.59#ibcon#read 6, iclass 39, count 0 2006.257.04:31:57.59#ibcon#end of sib2, iclass 39, count 0 2006.257.04:31:57.59#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:31:57.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:31:57.59#ibcon#[27=USB\r\n] 2006.257.04:31:57.59#ibcon#*before write, iclass 39, count 0 2006.257.04:31:57.59#ibcon#enter sib2, iclass 39, count 0 2006.257.04:31:57.59#ibcon#flushed, iclass 39, count 0 2006.257.04:31:57.59#ibcon#about to write, iclass 39, count 0 2006.257.04:31:57.59#ibcon#wrote, iclass 39, count 0 2006.257.04:31:57.59#ibcon#about to read 3, iclass 39, count 0 2006.257.04:31:57.62#ibcon#read 3, iclass 39, count 0 2006.257.04:31:57.62#ibcon#about to read 4, iclass 39, count 0 2006.257.04:31:57.62#ibcon#read 4, iclass 39, count 0 2006.257.04:31:57.62#ibcon#about to read 5, iclass 39, count 0 2006.257.04:31:57.62#ibcon#read 5, iclass 39, count 0 2006.257.04:31:57.62#ibcon#about to read 6, iclass 39, count 0 2006.257.04:31:57.62#ibcon#read 6, iclass 39, count 0 2006.257.04:31:57.62#ibcon#end of sib2, iclass 39, count 0 2006.257.04:31:57.62#ibcon#*after write, iclass 39, count 0 2006.257.04:31:57.62#ibcon#*before return 0, iclass 39, count 0 2006.257.04:31:57.62#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:57.62#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:31:57.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:31:57.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:31:57.62$vck44/vabw=wide 2006.257.04:31:57.62#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.04:31:57.62#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.04:31:57.62#ibcon#ireg 8 cls_cnt 0 2006.257.04:31:57.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:57.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:57.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:57.62#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:31:57.62#ibcon#first serial, iclass 3, count 0 2006.257.04:31:57.62#ibcon#enter sib2, iclass 3, count 0 2006.257.04:31:57.62#ibcon#flushed, iclass 3, count 0 2006.257.04:31:57.62#ibcon#about to write, iclass 3, count 0 2006.257.04:31:57.62#ibcon#wrote, iclass 3, count 0 2006.257.04:31:57.62#ibcon#about to read 3, iclass 3, count 0 2006.257.04:31:57.64#ibcon#read 3, iclass 3, count 0 2006.257.04:31:57.64#ibcon#about to read 4, iclass 3, count 0 2006.257.04:31:57.64#ibcon#read 4, iclass 3, count 0 2006.257.04:31:57.64#ibcon#about to read 5, iclass 3, count 0 2006.257.04:31:57.64#ibcon#read 5, iclass 3, count 0 2006.257.04:31:57.64#ibcon#about to read 6, iclass 3, count 0 2006.257.04:31:57.64#ibcon#read 6, iclass 3, count 0 2006.257.04:31:57.64#ibcon#end of sib2, iclass 3, count 0 2006.257.04:31:57.64#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:31:57.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:31:57.64#ibcon#[25=BW32\r\n] 2006.257.04:31:57.64#ibcon#*before write, iclass 3, count 0 2006.257.04:31:57.64#ibcon#enter sib2, iclass 3, count 0 2006.257.04:31:57.64#ibcon#flushed, iclass 3, count 0 2006.257.04:31:57.64#ibcon#about to write, iclass 3, count 0 2006.257.04:31:57.64#ibcon#wrote, iclass 3, count 0 2006.257.04:31:57.64#ibcon#about to read 3, iclass 3, count 0 2006.257.04:31:57.67#ibcon#read 3, iclass 3, count 0 2006.257.04:31:57.67#ibcon#about to read 4, iclass 3, count 0 2006.257.04:31:57.67#ibcon#read 4, iclass 3, count 0 2006.257.04:31:57.67#ibcon#about to read 5, iclass 3, count 0 2006.257.04:31:57.67#ibcon#read 5, iclass 3, count 0 2006.257.04:31:57.67#ibcon#about to read 6, iclass 3, count 0 2006.257.04:31:57.67#ibcon#read 6, iclass 3, count 0 2006.257.04:31:57.67#ibcon#end of sib2, iclass 3, count 0 2006.257.04:31:57.67#ibcon#*after write, iclass 3, count 0 2006.257.04:31:57.67#ibcon#*before return 0, iclass 3, count 0 2006.257.04:31:57.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:57.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:31:57.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:31:57.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:31:57.67$vck44/vbbw=wide 2006.257.04:31:57.67#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.04:31:57.67#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.04:31:57.67#ibcon#ireg 8 cls_cnt 0 2006.257.04:31:57.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:31:57.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:31:57.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:31:57.74#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:31:57.74#ibcon#first serial, iclass 5, count 0 2006.257.04:31:57.74#ibcon#enter sib2, iclass 5, count 0 2006.257.04:31:57.74#ibcon#flushed, iclass 5, count 0 2006.257.04:31:57.74#ibcon#about to write, iclass 5, count 0 2006.257.04:31:57.74#ibcon#wrote, iclass 5, count 0 2006.257.04:31:57.74#ibcon#about to read 3, iclass 5, count 0 2006.257.04:31:57.76#ibcon#read 3, iclass 5, count 0 2006.257.04:31:57.76#ibcon#about to read 4, iclass 5, count 0 2006.257.04:31:57.76#ibcon#read 4, iclass 5, count 0 2006.257.04:31:57.76#ibcon#about to read 5, iclass 5, count 0 2006.257.04:31:57.76#ibcon#read 5, iclass 5, count 0 2006.257.04:31:57.76#ibcon#about to read 6, iclass 5, count 0 2006.257.04:31:57.76#ibcon#read 6, iclass 5, count 0 2006.257.04:31:57.76#ibcon#end of sib2, iclass 5, count 0 2006.257.04:31:57.76#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:31:57.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:31:57.76#ibcon#[27=BW32\r\n] 2006.257.04:31:57.76#ibcon#*before write, iclass 5, count 0 2006.257.04:31:57.76#ibcon#enter sib2, iclass 5, count 0 2006.257.04:31:57.76#ibcon#flushed, iclass 5, count 0 2006.257.04:31:57.76#ibcon#about to write, iclass 5, count 0 2006.257.04:31:57.76#ibcon#wrote, iclass 5, count 0 2006.257.04:31:57.76#ibcon#about to read 3, iclass 5, count 0 2006.257.04:31:57.79#ibcon#read 3, iclass 5, count 0 2006.257.04:31:57.79#ibcon#about to read 4, iclass 5, count 0 2006.257.04:31:57.79#ibcon#read 4, iclass 5, count 0 2006.257.04:31:57.79#ibcon#about to read 5, iclass 5, count 0 2006.257.04:31:57.79#ibcon#read 5, iclass 5, count 0 2006.257.04:31:57.79#ibcon#about to read 6, iclass 5, count 0 2006.257.04:31:57.79#ibcon#read 6, iclass 5, count 0 2006.257.04:31:57.79#ibcon#end of sib2, iclass 5, count 0 2006.257.04:31:57.79#ibcon#*after write, iclass 5, count 0 2006.257.04:31:57.79#ibcon#*before return 0, iclass 5, count 0 2006.257.04:31:57.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:31:57.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:31:57.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:31:57.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:31:57.79$setupk4/ifdk4 2006.257.04:31:57.79$ifdk4/lo= 2006.257.04:31:57.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.04:31:57.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.04:31:57.79$ifdk4/patch= 2006.257.04:31:57.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.04:31:57.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.04:31:57.79$setupk4/!*+20s 2006.257.04:32:05.14#trakl#Source acquired 2006.257.04:32:05.14#flagr#flagr/antenna,acquired 2006.257.04:32:06.23#abcon#<5=/14 2.1 6.2 19.50 931012.0\r\n> 2006.257.04:32:06.25#abcon#{5=INTERFACE CLEAR} 2006.257.04:32:06.31#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:32:12.30$setupk4/"tpicd 2006.257.04:32:12.30$setupk4/echo=off 2006.257.04:32:12.30$setupk4/xlog=off 2006.257.04:32:12.30:!2006.257.04:33:48 2006.257.04:33:48.00:preob 2006.257.04:33:48.14/onsource/TRACKING 2006.257.04:33:48.14:!2006.257.04:33:58 2006.257.04:33:58.00:"tape 2006.257.04:33:58.00:"st=record 2006.257.04:33:58.00:data_valid=on 2006.257.04:33:58.00:midob 2006.257.04:33:59.14/onsource/TRACKING 2006.257.04:33:59.14/wx/19.51,1011.9,93 2006.257.04:33:59.35/cable/+6.4844E-03 2006.257.04:34:00.44/va/01,08,usb,yes,34,37 2006.257.04:34:00.44/va/02,07,usb,yes,37,38 2006.257.04:34:00.44/va/03,08,usb,yes,33,35 2006.257.04:34:00.44/va/04,07,usb,yes,38,40 2006.257.04:34:00.44/va/05,04,usb,yes,34,35 2006.257.04:34:00.44/va/06,04,usb,yes,38,38 2006.257.04:34:00.44/va/07,04,usb,yes,39,40 2006.257.04:34:00.44/va/08,04,usb,yes,33,40 2006.257.04:34:00.67/valo/01,524.99,yes,locked 2006.257.04:34:00.67/valo/02,534.99,yes,locked 2006.257.04:34:00.67/valo/03,564.99,yes,locked 2006.257.04:34:00.67/valo/04,624.99,yes,locked 2006.257.04:34:00.67/valo/05,734.99,yes,locked 2006.257.04:34:00.67/valo/06,814.99,yes,locked 2006.257.04:34:00.67/valo/07,864.99,yes,locked 2006.257.04:34:00.67/valo/08,884.99,yes,locked 2006.257.04:34:01.76/vb/01,04,usb,yes,30,31 2006.257.04:34:01.76/vb/02,05,usb,yes,29,31 2006.257.04:34:01.76/vb/03,04,usb,yes,30,33 2006.257.04:34:01.76/vb/04,05,usb,yes,30,29 2006.257.04:34:01.76/vb/05,04,usb,yes,27,29 2006.257.04:34:01.76/vb/06,04,usb,yes,31,27 2006.257.04:34:01.76/vb/07,04,usb,yes,31,31 2006.257.04:34:01.76/vb/08,04,usb,yes,28,32 2006.257.04:34:02.00/vblo/01,629.99,yes,locked 2006.257.04:34:02.00/vblo/02,634.99,yes,locked 2006.257.04:34:02.00/vblo/03,649.99,yes,locked 2006.257.04:34:02.00/vblo/04,679.99,yes,locked 2006.257.04:34:02.00/vblo/05,709.99,yes,locked 2006.257.04:34:02.00/vblo/06,719.99,yes,locked 2006.257.04:34:02.00/vblo/07,734.99,yes,locked 2006.257.04:34:02.00/vblo/08,744.99,yes,locked 2006.257.04:34:02.15/vabw/8 2006.257.04:34:02.30/vbbw/8 2006.257.04:34:02.39/xfe/off,on,16.7 2006.257.04:34:02.77/ifatt/23,28,28,28 2006.257.04:34:03.07/fmout-gps/S +4.54E-07 2006.257.04:34:03.11:!2006.257.04:39:58 2006.257.04:39:58.00:data_valid=off 2006.257.04:39:58.00:"et 2006.257.04:39:58.00:!+3s 2006.257.04:40:01.01:"tape 2006.257.04:40:01.01:postob 2006.257.04:40:01.15/cable/+6.4843E-03 2006.257.04:40:01.15/wx/19.61,1011.9,93 2006.257.04:40:02.08/fmout-gps/S +4.53E-07 2006.257.04:40:02.08:scan_name=257-0442,jd0609,50 2006.257.04:40:02.08:source=1611+343,161341.06,341247.9,2000.0,cw 2006.257.04:40:02.14#flagr#flagr/antenna,new-source 2006.257.04:40:03.14:checkk5 2006.257.04:40:03.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.04:40:03.91/chk_autoobs//k5ts2/ autoobs is running! 2006.257.04:40:04.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.04:40:04.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.04:40:05.15/chk_obsdata//k5ts1/T2570433??a.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.257.04:40:05.56/chk_obsdata//k5ts2/T2570433??b.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.257.04:40:05.97/chk_obsdata//k5ts3/T2570433??c.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.257.04:40:06.36/chk_obsdata//k5ts4/T2570433??d.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.257.04:40:07.07/k5log//k5ts1_log_newline 2006.257.04:40:07.78/k5log//k5ts2_log_newline 2006.257.04:40:08.54/k5log//k5ts3_log_newline 2006.257.04:40:09.26/k5log//k5ts4_log_newline 2006.257.04:40:09.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.04:40:09.28:setupk4=1 2006.257.04:40:09.28$setupk4/echo=on 2006.257.04:40:09.28$setupk4/pcalon 2006.257.04:40:09.28$pcalon/"no phase cal control is implemented here 2006.257.04:40:09.28$setupk4/"tpicd=stop 2006.257.04:40:09.28$setupk4/"rec=synch_on 2006.257.04:40:09.28$setupk4/"rec_mode=128 2006.257.04:40:09.28$setupk4/!* 2006.257.04:40:09.28$setupk4/recpk4 2006.257.04:40:09.28$recpk4/recpatch= 2006.257.04:40:09.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.04:40:09.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.04:40:09.29$setupk4/vck44 2006.257.04:40:09.29$vck44/valo=1,524.99 2006.257.04:40:09.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.04:40:09.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.04:40:09.29#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:09.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:09.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:09.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:09.29#ibcon#enter wrdev, iclass 24, count 0 2006.257.04:40:09.29#ibcon#first serial, iclass 24, count 0 2006.257.04:40:09.29#ibcon#enter sib2, iclass 24, count 0 2006.257.04:40:09.29#ibcon#flushed, iclass 24, count 0 2006.257.04:40:09.29#ibcon#about to write, iclass 24, count 0 2006.257.04:40:09.29#ibcon#wrote, iclass 24, count 0 2006.257.04:40:09.29#ibcon#about to read 3, iclass 24, count 0 2006.257.04:40:09.31#ibcon#read 3, iclass 24, count 0 2006.257.04:40:09.31#ibcon#about to read 4, iclass 24, count 0 2006.257.04:40:09.31#ibcon#read 4, iclass 24, count 0 2006.257.04:40:09.31#ibcon#about to read 5, iclass 24, count 0 2006.257.04:40:09.31#ibcon#read 5, iclass 24, count 0 2006.257.04:40:09.31#ibcon#about to read 6, iclass 24, count 0 2006.257.04:40:09.31#ibcon#read 6, iclass 24, count 0 2006.257.04:40:09.31#ibcon#end of sib2, iclass 24, count 0 2006.257.04:40:09.31#ibcon#*mode == 0, iclass 24, count 0 2006.257.04:40:09.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.04:40:09.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.04:40:09.31#ibcon#*before write, iclass 24, count 0 2006.257.04:40:09.31#ibcon#enter sib2, iclass 24, count 0 2006.257.04:40:09.31#ibcon#flushed, iclass 24, count 0 2006.257.04:40:09.31#ibcon#about to write, iclass 24, count 0 2006.257.04:40:09.31#ibcon#wrote, iclass 24, count 0 2006.257.04:40:09.31#ibcon#about to read 3, iclass 24, count 0 2006.257.04:40:09.36#ibcon#read 3, iclass 24, count 0 2006.257.04:40:09.36#ibcon#about to read 4, iclass 24, count 0 2006.257.04:40:09.36#ibcon#read 4, iclass 24, count 0 2006.257.04:40:09.36#ibcon#about to read 5, iclass 24, count 0 2006.257.04:40:09.36#ibcon#read 5, iclass 24, count 0 2006.257.04:40:09.36#ibcon#about to read 6, iclass 24, count 0 2006.257.04:40:09.36#ibcon#read 6, iclass 24, count 0 2006.257.04:40:09.36#ibcon#end of sib2, iclass 24, count 0 2006.257.04:40:09.36#ibcon#*after write, iclass 24, count 0 2006.257.04:40:09.36#ibcon#*before return 0, iclass 24, count 0 2006.257.04:40:09.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:09.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:09.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.04:40:09.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.04:40:09.36$vck44/va=1,8 2006.257.04:40:09.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.04:40:09.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.04:40:09.36#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:09.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:09.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:09.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:09.36#ibcon#enter wrdev, iclass 26, count 2 2006.257.04:40:09.36#ibcon#first serial, iclass 26, count 2 2006.257.04:40:09.36#ibcon#enter sib2, iclass 26, count 2 2006.257.04:40:09.36#ibcon#flushed, iclass 26, count 2 2006.257.04:40:09.36#ibcon#about to write, iclass 26, count 2 2006.257.04:40:09.36#ibcon#wrote, iclass 26, count 2 2006.257.04:40:09.36#ibcon#about to read 3, iclass 26, count 2 2006.257.04:40:09.38#ibcon#read 3, iclass 26, count 2 2006.257.04:40:09.38#ibcon#about to read 4, iclass 26, count 2 2006.257.04:40:09.38#ibcon#read 4, iclass 26, count 2 2006.257.04:40:09.38#ibcon#about to read 5, iclass 26, count 2 2006.257.04:40:09.38#ibcon#read 5, iclass 26, count 2 2006.257.04:40:09.38#ibcon#about to read 6, iclass 26, count 2 2006.257.04:40:09.38#ibcon#read 6, iclass 26, count 2 2006.257.04:40:09.38#ibcon#end of sib2, iclass 26, count 2 2006.257.04:40:09.38#ibcon#*mode == 0, iclass 26, count 2 2006.257.04:40:09.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.04:40:09.38#ibcon#[25=AT01-08\r\n] 2006.257.04:40:09.38#ibcon#*before write, iclass 26, count 2 2006.257.04:40:09.38#ibcon#enter sib2, iclass 26, count 2 2006.257.04:40:09.38#ibcon#flushed, iclass 26, count 2 2006.257.04:40:09.38#ibcon#about to write, iclass 26, count 2 2006.257.04:40:09.38#ibcon#wrote, iclass 26, count 2 2006.257.04:40:09.38#ibcon#about to read 3, iclass 26, count 2 2006.257.04:40:09.41#ibcon#read 3, iclass 26, count 2 2006.257.04:40:09.41#ibcon#about to read 4, iclass 26, count 2 2006.257.04:40:09.41#ibcon#read 4, iclass 26, count 2 2006.257.04:40:09.41#ibcon#about to read 5, iclass 26, count 2 2006.257.04:40:09.41#ibcon#read 5, iclass 26, count 2 2006.257.04:40:09.41#ibcon#about to read 6, iclass 26, count 2 2006.257.04:40:09.41#ibcon#read 6, iclass 26, count 2 2006.257.04:40:09.41#ibcon#end of sib2, iclass 26, count 2 2006.257.04:40:09.41#ibcon#*after write, iclass 26, count 2 2006.257.04:40:09.41#ibcon#*before return 0, iclass 26, count 2 2006.257.04:40:09.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:09.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:09.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.04:40:09.41#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:09.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:09.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:09.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:09.53#ibcon#enter wrdev, iclass 26, count 0 2006.257.04:40:09.53#ibcon#first serial, iclass 26, count 0 2006.257.04:40:09.53#ibcon#enter sib2, iclass 26, count 0 2006.257.04:40:09.53#ibcon#flushed, iclass 26, count 0 2006.257.04:40:09.53#ibcon#about to write, iclass 26, count 0 2006.257.04:40:09.53#ibcon#wrote, iclass 26, count 0 2006.257.04:40:09.53#ibcon#about to read 3, iclass 26, count 0 2006.257.04:40:09.55#ibcon#read 3, iclass 26, count 0 2006.257.04:40:09.55#ibcon#about to read 4, iclass 26, count 0 2006.257.04:40:09.55#ibcon#read 4, iclass 26, count 0 2006.257.04:40:09.55#ibcon#about to read 5, iclass 26, count 0 2006.257.04:40:09.55#ibcon#read 5, iclass 26, count 0 2006.257.04:40:09.55#ibcon#about to read 6, iclass 26, count 0 2006.257.04:40:09.55#ibcon#read 6, iclass 26, count 0 2006.257.04:40:09.55#ibcon#end of sib2, iclass 26, count 0 2006.257.04:40:09.55#ibcon#*mode == 0, iclass 26, count 0 2006.257.04:40:09.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.04:40:09.55#ibcon#[25=USB\r\n] 2006.257.04:40:09.55#ibcon#*before write, iclass 26, count 0 2006.257.04:40:09.55#ibcon#enter sib2, iclass 26, count 0 2006.257.04:40:09.55#ibcon#flushed, iclass 26, count 0 2006.257.04:40:09.55#ibcon#about to write, iclass 26, count 0 2006.257.04:40:09.55#ibcon#wrote, iclass 26, count 0 2006.257.04:40:09.55#ibcon#about to read 3, iclass 26, count 0 2006.257.04:40:09.58#ibcon#read 3, iclass 26, count 0 2006.257.04:40:09.58#ibcon#about to read 4, iclass 26, count 0 2006.257.04:40:09.58#ibcon#read 4, iclass 26, count 0 2006.257.04:40:09.58#ibcon#about to read 5, iclass 26, count 0 2006.257.04:40:09.58#ibcon#read 5, iclass 26, count 0 2006.257.04:40:09.58#ibcon#about to read 6, iclass 26, count 0 2006.257.04:40:09.58#ibcon#read 6, iclass 26, count 0 2006.257.04:40:09.58#ibcon#end of sib2, iclass 26, count 0 2006.257.04:40:09.58#ibcon#*after write, iclass 26, count 0 2006.257.04:40:09.58#ibcon#*before return 0, iclass 26, count 0 2006.257.04:40:09.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:09.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:09.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.04:40:09.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.04:40:09.58$vck44/valo=2,534.99 2006.257.04:40:09.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.04:40:09.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.04:40:09.58#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:09.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:09.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:09.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:09.58#ibcon#enter wrdev, iclass 28, count 0 2006.257.04:40:09.58#ibcon#first serial, iclass 28, count 0 2006.257.04:40:09.58#ibcon#enter sib2, iclass 28, count 0 2006.257.04:40:09.58#ibcon#flushed, iclass 28, count 0 2006.257.04:40:09.58#ibcon#about to write, iclass 28, count 0 2006.257.04:40:09.58#ibcon#wrote, iclass 28, count 0 2006.257.04:40:09.58#ibcon#about to read 3, iclass 28, count 0 2006.257.04:40:09.60#ibcon#read 3, iclass 28, count 0 2006.257.04:40:09.60#ibcon#about to read 4, iclass 28, count 0 2006.257.04:40:09.60#ibcon#read 4, iclass 28, count 0 2006.257.04:40:09.60#ibcon#about to read 5, iclass 28, count 0 2006.257.04:40:09.60#ibcon#read 5, iclass 28, count 0 2006.257.04:40:09.60#ibcon#about to read 6, iclass 28, count 0 2006.257.04:40:09.60#ibcon#read 6, iclass 28, count 0 2006.257.04:40:09.60#ibcon#end of sib2, iclass 28, count 0 2006.257.04:40:09.60#ibcon#*mode == 0, iclass 28, count 0 2006.257.04:40:09.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.04:40:09.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.04:40:09.60#ibcon#*before write, iclass 28, count 0 2006.257.04:40:09.60#ibcon#enter sib2, iclass 28, count 0 2006.257.04:40:09.60#ibcon#flushed, iclass 28, count 0 2006.257.04:40:09.60#ibcon#about to write, iclass 28, count 0 2006.257.04:40:09.60#ibcon#wrote, iclass 28, count 0 2006.257.04:40:09.60#ibcon#about to read 3, iclass 28, count 0 2006.257.04:40:09.64#ibcon#read 3, iclass 28, count 0 2006.257.04:40:09.64#ibcon#about to read 4, iclass 28, count 0 2006.257.04:40:09.64#ibcon#read 4, iclass 28, count 0 2006.257.04:40:09.64#ibcon#about to read 5, iclass 28, count 0 2006.257.04:40:09.64#ibcon#read 5, iclass 28, count 0 2006.257.04:40:09.64#ibcon#about to read 6, iclass 28, count 0 2006.257.04:40:09.64#ibcon#read 6, iclass 28, count 0 2006.257.04:40:09.64#ibcon#end of sib2, iclass 28, count 0 2006.257.04:40:09.64#ibcon#*after write, iclass 28, count 0 2006.257.04:40:09.64#ibcon#*before return 0, iclass 28, count 0 2006.257.04:40:09.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:09.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:09.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.04:40:09.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.04:40:09.64$vck44/va=2,7 2006.257.04:40:09.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.04:40:09.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.04:40:09.64#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:09.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:09.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:09.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:09.70#ibcon#enter wrdev, iclass 30, count 2 2006.257.04:40:09.70#ibcon#first serial, iclass 30, count 2 2006.257.04:40:09.70#ibcon#enter sib2, iclass 30, count 2 2006.257.04:40:09.70#ibcon#flushed, iclass 30, count 2 2006.257.04:40:09.70#ibcon#about to write, iclass 30, count 2 2006.257.04:40:09.70#ibcon#wrote, iclass 30, count 2 2006.257.04:40:09.70#ibcon#about to read 3, iclass 30, count 2 2006.257.04:40:09.72#ibcon#read 3, iclass 30, count 2 2006.257.04:40:09.72#ibcon#about to read 4, iclass 30, count 2 2006.257.04:40:09.72#ibcon#read 4, iclass 30, count 2 2006.257.04:40:09.72#ibcon#about to read 5, iclass 30, count 2 2006.257.04:40:09.72#ibcon#read 5, iclass 30, count 2 2006.257.04:40:09.72#ibcon#about to read 6, iclass 30, count 2 2006.257.04:40:09.72#ibcon#read 6, iclass 30, count 2 2006.257.04:40:09.72#ibcon#end of sib2, iclass 30, count 2 2006.257.04:40:09.72#ibcon#*mode == 0, iclass 30, count 2 2006.257.04:40:09.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.04:40:09.72#ibcon#[25=AT02-07\r\n] 2006.257.04:40:09.72#ibcon#*before write, iclass 30, count 2 2006.257.04:40:09.72#ibcon#enter sib2, iclass 30, count 2 2006.257.04:40:09.72#ibcon#flushed, iclass 30, count 2 2006.257.04:40:09.72#ibcon#about to write, iclass 30, count 2 2006.257.04:40:09.72#ibcon#wrote, iclass 30, count 2 2006.257.04:40:09.72#ibcon#about to read 3, iclass 30, count 2 2006.257.04:40:09.75#ibcon#read 3, iclass 30, count 2 2006.257.04:40:09.75#ibcon#about to read 4, iclass 30, count 2 2006.257.04:40:09.75#ibcon#read 4, iclass 30, count 2 2006.257.04:40:09.75#ibcon#about to read 5, iclass 30, count 2 2006.257.04:40:09.75#ibcon#read 5, iclass 30, count 2 2006.257.04:40:09.75#ibcon#about to read 6, iclass 30, count 2 2006.257.04:40:09.75#ibcon#read 6, iclass 30, count 2 2006.257.04:40:09.75#ibcon#end of sib2, iclass 30, count 2 2006.257.04:40:09.75#ibcon#*after write, iclass 30, count 2 2006.257.04:40:09.75#ibcon#*before return 0, iclass 30, count 2 2006.257.04:40:09.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:09.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:09.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.04:40:09.75#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:09.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:09.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:09.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:09.87#ibcon#enter wrdev, iclass 30, count 0 2006.257.04:40:09.87#ibcon#first serial, iclass 30, count 0 2006.257.04:40:09.87#ibcon#enter sib2, iclass 30, count 0 2006.257.04:40:09.87#ibcon#flushed, iclass 30, count 0 2006.257.04:40:09.87#ibcon#about to write, iclass 30, count 0 2006.257.04:40:09.87#ibcon#wrote, iclass 30, count 0 2006.257.04:40:09.87#ibcon#about to read 3, iclass 30, count 0 2006.257.04:40:09.89#ibcon#read 3, iclass 30, count 0 2006.257.04:40:09.89#ibcon#about to read 4, iclass 30, count 0 2006.257.04:40:09.89#ibcon#read 4, iclass 30, count 0 2006.257.04:40:09.89#ibcon#about to read 5, iclass 30, count 0 2006.257.04:40:09.89#ibcon#read 5, iclass 30, count 0 2006.257.04:40:09.89#ibcon#about to read 6, iclass 30, count 0 2006.257.04:40:09.89#ibcon#read 6, iclass 30, count 0 2006.257.04:40:09.89#ibcon#end of sib2, iclass 30, count 0 2006.257.04:40:09.89#ibcon#*mode == 0, iclass 30, count 0 2006.257.04:40:09.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.04:40:09.89#ibcon#[25=USB\r\n] 2006.257.04:40:09.89#ibcon#*before write, iclass 30, count 0 2006.257.04:40:09.89#ibcon#enter sib2, iclass 30, count 0 2006.257.04:40:09.89#ibcon#flushed, iclass 30, count 0 2006.257.04:40:09.89#ibcon#about to write, iclass 30, count 0 2006.257.04:40:09.89#ibcon#wrote, iclass 30, count 0 2006.257.04:40:09.89#ibcon#about to read 3, iclass 30, count 0 2006.257.04:40:09.92#ibcon#read 3, iclass 30, count 0 2006.257.04:40:09.92#ibcon#about to read 4, iclass 30, count 0 2006.257.04:40:09.92#ibcon#read 4, iclass 30, count 0 2006.257.04:40:09.92#ibcon#about to read 5, iclass 30, count 0 2006.257.04:40:09.92#ibcon#read 5, iclass 30, count 0 2006.257.04:40:09.92#ibcon#about to read 6, iclass 30, count 0 2006.257.04:40:09.92#ibcon#read 6, iclass 30, count 0 2006.257.04:40:09.92#ibcon#end of sib2, iclass 30, count 0 2006.257.04:40:09.92#ibcon#*after write, iclass 30, count 0 2006.257.04:40:09.92#ibcon#*before return 0, iclass 30, count 0 2006.257.04:40:09.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:09.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:09.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.04:40:09.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.04:40:09.92$vck44/valo=3,564.99 2006.257.04:40:09.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.04:40:09.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.04:40:09.92#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:09.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:09.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:09.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:09.92#ibcon#enter wrdev, iclass 32, count 0 2006.257.04:40:09.92#ibcon#first serial, iclass 32, count 0 2006.257.04:40:09.92#ibcon#enter sib2, iclass 32, count 0 2006.257.04:40:09.92#ibcon#flushed, iclass 32, count 0 2006.257.04:40:09.92#ibcon#about to write, iclass 32, count 0 2006.257.04:40:09.92#ibcon#wrote, iclass 32, count 0 2006.257.04:40:09.92#ibcon#about to read 3, iclass 32, count 0 2006.257.04:40:09.94#ibcon#read 3, iclass 32, count 0 2006.257.04:40:09.94#ibcon#about to read 4, iclass 32, count 0 2006.257.04:40:09.94#ibcon#read 4, iclass 32, count 0 2006.257.04:40:09.94#ibcon#about to read 5, iclass 32, count 0 2006.257.04:40:09.94#ibcon#read 5, iclass 32, count 0 2006.257.04:40:09.94#ibcon#about to read 6, iclass 32, count 0 2006.257.04:40:09.94#ibcon#read 6, iclass 32, count 0 2006.257.04:40:09.94#ibcon#end of sib2, iclass 32, count 0 2006.257.04:40:09.94#ibcon#*mode == 0, iclass 32, count 0 2006.257.04:40:09.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.04:40:09.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.04:40:09.94#ibcon#*before write, iclass 32, count 0 2006.257.04:40:09.94#ibcon#enter sib2, iclass 32, count 0 2006.257.04:40:09.94#ibcon#flushed, iclass 32, count 0 2006.257.04:40:09.94#ibcon#about to write, iclass 32, count 0 2006.257.04:40:09.94#ibcon#wrote, iclass 32, count 0 2006.257.04:40:09.94#ibcon#about to read 3, iclass 32, count 0 2006.257.04:40:09.98#ibcon#read 3, iclass 32, count 0 2006.257.04:40:09.98#ibcon#about to read 4, iclass 32, count 0 2006.257.04:40:09.98#ibcon#read 4, iclass 32, count 0 2006.257.04:40:09.98#ibcon#about to read 5, iclass 32, count 0 2006.257.04:40:09.98#ibcon#read 5, iclass 32, count 0 2006.257.04:40:09.98#ibcon#about to read 6, iclass 32, count 0 2006.257.04:40:09.98#ibcon#read 6, iclass 32, count 0 2006.257.04:40:09.98#ibcon#end of sib2, iclass 32, count 0 2006.257.04:40:09.98#ibcon#*after write, iclass 32, count 0 2006.257.04:40:09.98#ibcon#*before return 0, iclass 32, count 0 2006.257.04:40:09.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:09.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:09.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.04:40:09.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.04:40:09.98$vck44/va=3,8 2006.257.04:40:09.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.04:40:09.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.04:40:09.98#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:09.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:10.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:10.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:10.04#ibcon#enter wrdev, iclass 34, count 2 2006.257.04:40:10.04#ibcon#first serial, iclass 34, count 2 2006.257.04:40:10.04#ibcon#enter sib2, iclass 34, count 2 2006.257.04:40:10.04#ibcon#flushed, iclass 34, count 2 2006.257.04:40:10.04#ibcon#about to write, iclass 34, count 2 2006.257.04:40:10.04#ibcon#wrote, iclass 34, count 2 2006.257.04:40:10.04#ibcon#about to read 3, iclass 34, count 2 2006.257.04:40:10.06#ibcon#read 3, iclass 34, count 2 2006.257.04:40:10.06#ibcon#about to read 4, iclass 34, count 2 2006.257.04:40:10.06#ibcon#read 4, iclass 34, count 2 2006.257.04:40:10.06#ibcon#about to read 5, iclass 34, count 2 2006.257.04:40:10.06#ibcon#read 5, iclass 34, count 2 2006.257.04:40:10.06#ibcon#about to read 6, iclass 34, count 2 2006.257.04:40:10.06#ibcon#read 6, iclass 34, count 2 2006.257.04:40:10.06#ibcon#end of sib2, iclass 34, count 2 2006.257.04:40:10.06#ibcon#*mode == 0, iclass 34, count 2 2006.257.04:40:10.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.04:40:10.06#ibcon#[25=AT03-08\r\n] 2006.257.04:40:10.06#ibcon#*before write, iclass 34, count 2 2006.257.04:40:10.06#ibcon#enter sib2, iclass 34, count 2 2006.257.04:40:10.06#ibcon#flushed, iclass 34, count 2 2006.257.04:40:10.06#ibcon#about to write, iclass 34, count 2 2006.257.04:40:10.06#ibcon#wrote, iclass 34, count 2 2006.257.04:40:10.06#ibcon#about to read 3, iclass 34, count 2 2006.257.04:40:10.09#ibcon#read 3, iclass 34, count 2 2006.257.04:40:10.09#ibcon#about to read 4, iclass 34, count 2 2006.257.04:40:10.09#ibcon#read 4, iclass 34, count 2 2006.257.04:40:10.09#ibcon#about to read 5, iclass 34, count 2 2006.257.04:40:10.09#ibcon#read 5, iclass 34, count 2 2006.257.04:40:10.09#ibcon#about to read 6, iclass 34, count 2 2006.257.04:40:10.09#ibcon#read 6, iclass 34, count 2 2006.257.04:40:10.09#ibcon#end of sib2, iclass 34, count 2 2006.257.04:40:10.09#ibcon#*after write, iclass 34, count 2 2006.257.04:40:10.09#ibcon#*before return 0, iclass 34, count 2 2006.257.04:40:10.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:10.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:10.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.04:40:10.09#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:10.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:10.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:10.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:10.21#ibcon#enter wrdev, iclass 34, count 0 2006.257.04:40:10.21#ibcon#first serial, iclass 34, count 0 2006.257.04:40:10.21#ibcon#enter sib2, iclass 34, count 0 2006.257.04:40:10.21#ibcon#flushed, iclass 34, count 0 2006.257.04:40:10.21#ibcon#about to write, iclass 34, count 0 2006.257.04:40:10.21#ibcon#wrote, iclass 34, count 0 2006.257.04:40:10.21#ibcon#about to read 3, iclass 34, count 0 2006.257.04:40:10.23#ibcon#read 3, iclass 34, count 0 2006.257.04:40:10.23#ibcon#about to read 4, iclass 34, count 0 2006.257.04:40:10.23#ibcon#read 4, iclass 34, count 0 2006.257.04:40:10.23#ibcon#about to read 5, iclass 34, count 0 2006.257.04:40:10.23#ibcon#read 5, iclass 34, count 0 2006.257.04:40:10.23#ibcon#about to read 6, iclass 34, count 0 2006.257.04:40:10.23#ibcon#read 6, iclass 34, count 0 2006.257.04:40:10.23#ibcon#end of sib2, iclass 34, count 0 2006.257.04:40:10.23#ibcon#*mode == 0, iclass 34, count 0 2006.257.04:40:10.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.04:40:10.23#ibcon#[25=USB\r\n] 2006.257.04:40:10.23#ibcon#*before write, iclass 34, count 0 2006.257.04:40:10.23#ibcon#enter sib2, iclass 34, count 0 2006.257.04:40:10.23#ibcon#flushed, iclass 34, count 0 2006.257.04:40:10.23#ibcon#about to write, iclass 34, count 0 2006.257.04:40:10.23#ibcon#wrote, iclass 34, count 0 2006.257.04:40:10.23#ibcon#about to read 3, iclass 34, count 0 2006.257.04:40:10.26#ibcon#read 3, iclass 34, count 0 2006.257.04:40:10.26#ibcon#about to read 4, iclass 34, count 0 2006.257.04:40:10.26#ibcon#read 4, iclass 34, count 0 2006.257.04:40:10.26#ibcon#about to read 5, iclass 34, count 0 2006.257.04:40:10.26#ibcon#read 5, iclass 34, count 0 2006.257.04:40:10.26#ibcon#about to read 6, iclass 34, count 0 2006.257.04:40:10.26#ibcon#read 6, iclass 34, count 0 2006.257.04:40:10.26#ibcon#end of sib2, iclass 34, count 0 2006.257.04:40:10.26#ibcon#*after write, iclass 34, count 0 2006.257.04:40:10.26#ibcon#*before return 0, iclass 34, count 0 2006.257.04:40:10.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:10.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:10.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.04:40:10.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.04:40:10.26$vck44/valo=4,624.99 2006.257.04:40:10.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.04:40:10.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.04:40:10.26#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:10.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:10.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:10.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:10.26#ibcon#enter wrdev, iclass 36, count 0 2006.257.04:40:10.26#ibcon#first serial, iclass 36, count 0 2006.257.04:40:10.26#ibcon#enter sib2, iclass 36, count 0 2006.257.04:40:10.26#ibcon#flushed, iclass 36, count 0 2006.257.04:40:10.26#ibcon#about to write, iclass 36, count 0 2006.257.04:40:10.26#ibcon#wrote, iclass 36, count 0 2006.257.04:40:10.26#ibcon#about to read 3, iclass 36, count 0 2006.257.04:40:10.28#ibcon#read 3, iclass 36, count 0 2006.257.04:40:10.28#ibcon#about to read 4, iclass 36, count 0 2006.257.04:40:10.28#ibcon#read 4, iclass 36, count 0 2006.257.04:40:10.28#ibcon#about to read 5, iclass 36, count 0 2006.257.04:40:10.28#ibcon#read 5, iclass 36, count 0 2006.257.04:40:10.28#ibcon#about to read 6, iclass 36, count 0 2006.257.04:40:10.28#ibcon#read 6, iclass 36, count 0 2006.257.04:40:10.28#ibcon#end of sib2, iclass 36, count 0 2006.257.04:40:10.28#ibcon#*mode == 0, iclass 36, count 0 2006.257.04:40:10.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.04:40:10.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.04:40:10.28#ibcon#*before write, iclass 36, count 0 2006.257.04:40:10.28#ibcon#enter sib2, iclass 36, count 0 2006.257.04:40:10.28#ibcon#flushed, iclass 36, count 0 2006.257.04:40:10.28#ibcon#about to write, iclass 36, count 0 2006.257.04:40:10.28#ibcon#wrote, iclass 36, count 0 2006.257.04:40:10.28#ibcon#about to read 3, iclass 36, count 0 2006.257.04:40:10.32#ibcon#read 3, iclass 36, count 0 2006.257.04:40:10.32#ibcon#about to read 4, iclass 36, count 0 2006.257.04:40:10.32#ibcon#read 4, iclass 36, count 0 2006.257.04:40:10.32#ibcon#about to read 5, iclass 36, count 0 2006.257.04:40:10.32#ibcon#read 5, iclass 36, count 0 2006.257.04:40:10.32#ibcon#about to read 6, iclass 36, count 0 2006.257.04:40:10.32#ibcon#read 6, iclass 36, count 0 2006.257.04:40:10.32#ibcon#end of sib2, iclass 36, count 0 2006.257.04:40:10.32#ibcon#*after write, iclass 36, count 0 2006.257.04:40:10.32#ibcon#*before return 0, iclass 36, count 0 2006.257.04:40:10.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:10.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:10.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.04:40:10.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.04:40:10.32$vck44/va=4,7 2006.257.04:40:10.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.04:40:10.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.04:40:10.32#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:10.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:10.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:10.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:10.38#ibcon#enter wrdev, iclass 38, count 2 2006.257.04:40:10.38#ibcon#first serial, iclass 38, count 2 2006.257.04:40:10.38#ibcon#enter sib2, iclass 38, count 2 2006.257.04:40:10.38#ibcon#flushed, iclass 38, count 2 2006.257.04:40:10.38#ibcon#about to write, iclass 38, count 2 2006.257.04:40:10.38#ibcon#wrote, iclass 38, count 2 2006.257.04:40:10.38#ibcon#about to read 3, iclass 38, count 2 2006.257.04:40:10.40#ibcon#read 3, iclass 38, count 2 2006.257.04:40:10.40#ibcon#about to read 4, iclass 38, count 2 2006.257.04:40:10.40#ibcon#read 4, iclass 38, count 2 2006.257.04:40:10.40#ibcon#about to read 5, iclass 38, count 2 2006.257.04:40:10.40#ibcon#read 5, iclass 38, count 2 2006.257.04:40:10.40#ibcon#about to read 6, iclass 38, count 2 2006.257.04:40:10.40#ibcon#read 6, iclass 38, count 2 2006.257.04:40:10.40#ibcon#end of sib2, iclass 38, count 2 2006.257.04:40:10.40#ibcon#*mode == 0, iclass 38, count 2 2006.257.04:40:10.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.04:40:10.40#ibcon#[25=AT04-07\r\n] 2006.257.04:40:10.40#ibcon#*before write, iclass 38, count 2 2006.257.04:40:10.40#ibcon#enter sib2, iclass 38, count 2 2006.257.04:40:10.40#ibcon#flushed, iclass 38, count 2 2006.257.04:40:10.40#ibcon#about to write, iclass 38, count 2 2006.257.04:40:10.40#ibcon#wrote, iclass 38, count 2 2006.257.04:40:10.40#ibcon#about to read 3, iclass 38, count 2 2006.257.04:40:10.43#ibcon#read 3, iclass 38, count 2 2006.257.04:40:10.43#ibcon#about to read 4, iclass 38, count 2 2006.257.04:40:10.43#ibcon#read 4, iclass 38, count 2 2006.257.04:40:10.43#ibcon#about to read 5, iclass 38, count 2 2006.257.04:40:10.43#ibcon#read 5, iclass 38, count 2 2006.257.04:40:10.43#ibcon#about to read 6, iclass 38, count 2 2006.257.04:40:10.43#ibcon#read 6, iclass 38, count 2 2006.257.04:40:10.43#ibcon#end of sib2, iclass 38, count 2 2006.257.04:40:10.43#ibcon#*after write, iclass 38, count 2 2006.257.04:40:10.43#ibcon#*before return 0, iclass 38, count 2 2006.257.04:40:10.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:10.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:10.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.04:40:10.43#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:10.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:10.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:10.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:10.55#ibcon#enter wrdev, iclass 38, count 0 2006.257.04:40:10.55#ibcon#first serial, iclass 38, count 0 2006.257.04:40:10.55#ibcon#enter sib2, iclass 38, count 0 2006.257.04:40:10.55#ibcon#flushed, iclass 38, count 0 2006.257.04:40:10.55#ibcon#about to write, iclass 38, count 0 2006.257.04:40:10.55#ibcon#wrote, iclass 38, count 0 2006.257.04:40:10.55#ibcon#about to read 3, iclass 38, count 0 2006.257.04:40:10.57#ibcon#read 3, iclass 38, count 0 2006.257.04:40:10.57#ibcon#about to read 4, iclass 38, count 0 2006.257.04:40:10.57#ibcon#read 4, iclass 38, count 0 2006.257.04:40:10.57#ibcon#about to read 5, iclass 38, count 0 2006.257.04:40:10.57#ibcon#read 5, iclass 38, count 0 2006.257.04:40:10.57#ibcon#about to read 6, iclass 38, count 0 2006.257.04:40:10.57#ibcon#read 6, iclass 38, count 0 2006.257.04:40:10.57#ibcon#end of sib2, iclass 38, count 0 2006.257.04:40:10.57#ibcon#*mode == 0, iclass 38, count 0 2006.257.04:40:10.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.04:40:10.57#ibcon#[25=USB\r\n] 2006.257.04:40:10.57#ibcon#*before write, iclass 38, count 0 2006.257.04:40:10.57#ibcon#enter sib2, iclass 38, count 0 2006.257.04:40:10.57#ibcon#flushed, iclass 38, count 0 2006.257.04:40:10.57#ibcon#about to write, iclass 38, count 0 2006.257.04:40:10.57#ibcon#wrote, iclass 38, count 0 2006.257.04:40:10.57#ibcon#about to read 3, iclass 38, count 0 2006.257.04:40:10.60#ibcon#read 3, iclass 38, count 0 2006.257.04:40:10.60#ibcon#about to read 4, iclass 38, count 0 2006.257.04:40:10.60#ibcon#read 4, iclass 38, count 0 2006.257.04:40:10.60#ibcon#about to read 5, iclass 38, count 0 2006.257.04:40:10.60#ibcon#read 5, iclass 38, count 0 2006.257.04:40:10.60#ibcon#about to read 6, iclass 38, count 0 2006.257.04:40:10.60#ibcon#read 6, iclass 38, count 0 2006.257.04:40:10.60#ibcon#end of sib2, iclass 38, count 0 2006.257.04:40:10.60#ibcon#*after write, iclass 38, count 0 2006.257.04:40:10.60#ibcon#*before return 0, iclass 38, count 0 2006.257.04:40:10.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:10.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:10.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.04:40:10.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.04:40:10.60$vck44/valo=5,734.99 2006.257.04:40:10.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.04:40:10.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.04:40:10.60#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:10.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:10.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:10.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:10.60#ibcon#enter wrdev, iclass 40, count 0 2006.257.04:40:10.60#ibcon#first serial, iclass 40, count 0 2006.257.04:40:10.60#ibcon#enter sib2, iclass 40, count 0 2006.257.04:40:10.60#ibcon#flushed, iclass 40, count 0 2006.257.04:40:10.60#ibcon#about to write, iclass 40, count 0 2006.257.04:40:10.60#ibcon#wrote, iclass 40, count 0 2006.257.04:40:10.60#ibcon#about to read 3, iclass 40, count 0 2006.257.04:40:10.62#ibcon#read 3, iclass 40, count 0 2006.257.04:40:10.62#ibcon#about to read 4, iclass 40, count 0 2006.257.04:40:10.62#ibcon#read 4, iclass 40, count 0 2006.257.04:40:10.62#ibcon#about to read 5, iclass 40, count 0 2006.257.04:40:10.62#ibcon#read 5, iclass 40, count 0 2006.257.04:40:10.62#ibcon#about to read 6, iclass 40, count 0 2006.257.04:40:10.62#ibcon#read 6, iclass 40, count 0 2006.257.04:40:10.62#ibcon#end of sib2, iclass 40, count 0 2006.257.04:40:10.62#ibcon#*mode == 0, iclass 40, count 0 2006.257.04:40:10.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.04:40:10.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.04:40:10.62#ibcon#*before write, iclass 40, count 0 2006.257.04:40:10.62#ibcon#enter sib2, iclass 40, count 0 2006.257.04:40:10.62#ibcon#flushed, iclass 40, count 0 2006.257.04:40:10.62#ibcon#about to write, iclass 40, count 0 2006.257.04:40:10.62#ibcon#wrote, iclass 40, count 0 2006.257.04:40:10.62#ibcon#about to read 3, iclass 40, count 0 2006.257.04:40:10.66#ibcon#read 3, iclass 40, count 0 2006.257.04:40:10.66#ibcon#about to read 4, iclass 40, count 0 2006.257.04:40:10.66#ibcon#read 4, iclass 40, count 0 2006.257.04:40:10.66#ibcon#about to read 5, iclass 40, count 0 2006.257.04:40:10.66#ibcon#read 5, iclass 40, count 0 2006.257.04:40:10.66#ibcon#about to read 6, iclass 40, count 0 2006.257.04:40:10.66#ibcon#read 6, iclass 40, count 0 2006.257.04:40:10.66#ibcon#end of sib2, iclass 40, count 0 2006.257.04:40:10.66#ibcon#*after write, iclass 40, count 0 2006.257.04:40:10.66#ibcon#*before return 0, iclass 40, count 0 2006.257.04:40:10.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:10.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:10.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.04:40:10.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.04:40:10.66$vck44/va=5,4 2006.257.04:40:10.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.04:40:10.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.04:40:10.66#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:10.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:10.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:10.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:10.72#ibcon#enter wrdev, iclass 4, count 2 2006.257.04:40:10.72#ibcon#first serial, iclass 4, count 2 2006.257.04:40:10.72#ibcon#enter sib2, iclass 4, count 2 2006.257.04:40:10.72#ibcon#flushed, iclass 4, count 2 2006.257.04:40:10.72#ibcon#about to write, iclass 4, count 2 2006.257.04:40:10.72#ibcon#wrote, iclass 4, count 2 2006.257.04:40:10.72#ibcon#about to read 3, iclass 4, count 2 2006.257.04:40:10.74#ibcon#read 3, iclass 4, count 2 2006.257.04:40:10.74#ibcon#about to read 4, iclass 4, count 2 2006.257.04:40:10.74#ibcon#read 4, iclass 4, count 2 2006.257.04:40:10.74#ibcon#about to read 5, iclass 4, count 2 2006.257.04:40:10.74#ibcon#read 5, iclass 4, count 2 2006.257.04:40:10.74#ibcon#about to read 6, iclass 4, count 2 2006.257.04:40:10.74#ibcon#read 6, iclass 4, count 2 2006.257.04:40:10.74#ibcon#end of sib2, iclass 4, count 2 2006.257.04:40:10.74#ibcon#*mode == 0, iclass 4, count 2 2006.257.04:40:10.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.04:40:10.74#ibcon#[25=AT05-04\r\n] 2006.257.04:40:10.74#ibcon#*before write, iclass 4, count 2 2006.257.04:40:10.74#ibcon#enter sib2, iclass 4, count 2 2006.257.04:40:10.74#ibcon#flushed, iclass 4, count 2 2006.257.04:40:10.74#ibcon#about to write, iclass 4, count 2 2006.257.04:40:10.74#ibcon#wrote, iclass 4, count 2 2006.257.04:40:10.74#ibcon#about to read 3, iclass 4, count 2 2006.257.04:40:10.77#ibcon#read 3, iclass 4, count 2 2006.257.04:40:10.77#ibcon#about to read 4, iclass 4, count 2 2006.257.04:40:10.77#ibcon#read 4, iclass 4, count 2 2006.257.04:40:10.77#ibcon#about to read 5, iclass 4, count 2 2006.257.04:40:10.77#ibcon#read 5, iclass 4, count 2 2006.257.04:40:10.77#ibcon#about to read 6, iclass 4, count 2 2006.257.04:40:10.77#ibcon#read 6, iclass 4, count 2 2006.257.04:40:10.77#ibcon#end of sib2, iclass 4, count 2 2006.257.04:40:10.77#ibcon#*after write, iclass 4, count 2 2006.257.04:40:10.77#ibcon#*before return 0, iclass 4, count 2 2006.257.04:40:10.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:10.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:10.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.04:40:10.77#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:10.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:10.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:10.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:10.89#ibcon#enter wrdev, iclass 4, count 0 2006.257.04:40:10.89#ibcon#first serial, iclass 4, count 0 2006.257.04:40:10.89#ibcon#enter sib2, iclass 4, count 0 2006.257.04:40:10.89#ibcon#flushed, iclass 4, count 0 2006.257.04:40:10.89#ibcon#about to write, iclass 4, count 0 2006.257.04:40:10.89#ibcon#wrote, iclass 4, count 0 2006.257.04:40:10.89#ibcon#about to read 3, iclass 4, count 0 2006.257.04:40:10.91#ibcon#read 3, iclass 4, count 0 2006.257.04:40:10.91#ibcon#about to read 4, iclass 4, count 0 2006.257.04:40:10.91#ibcon#read 4, iclass 4, count 0 2006.257.04:40:10.91#ibcon#about to read 5, iclass 4, count 0 2006.257.04:40:10.91#ibcon#read 5, iclass 4, count 0 2006.257.04:40:10.91#ibcon#about to read 6, iclass 4, count 0 2006.257.04:40:10.91#ibcon#read 6, iclass 4, count 0 2006.257.04:40:10.91#ibcon#end of sib2, iclass 4, count 0 2006.257.04:40:10.91#ibcon#*mode == 0, iclass 4, count 0 2006.257.04:40:10.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.04:40:10.91#ibcon#[25=USB\r\n] 2006.257.04:40:10.91#ibcon#*before write, iclass 4, count 0 2006.257.04:40:10.91#ibcon#enter sib2, iclass 4, count 0 2006.257.04:40:10.91#ibcon#flushed, iclass 4, count 0 2006.257.04:40:10.91#ibcon#about to write, iclass 4, count 0 2006.257.04:40:10.91#ibcon#wrote, iclass 4, count 0 2006.257.04:40:10.91#ibcon#about to read 3, iclass 4, count 0 2006.257.04:40:10.94#ibcon#read 3, iclass 4, count 0 2006.257.04:40:10.94#ibcon#about to read 4, iclass 4, count 0 2006.257.04:40:10.94#ibcon#read 4, iclass 4, count 0 2006.257.04:40:10.94#ibcon#about to read 5, iclass 4, count 0 2006.257.04:40:10.94#ibcon#read 5, iclass 4, count 0 2006.257.04:40:10.94#ibcon#about to read 6, iclass 4, count 0 2006.257.04:40:10.94#ibcon#read 6, iclass 4, count 0 2006.257.04:40:10.94#ibcon#end of sib2, iclass 4, count 0 2006.257.04:40:10.94#ibcon#*after write, iclass 4, count 0 2006.257.04:40:10.94#ibcon#*before return 0, iclass 4, count 0 2006.257.04:40:10.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:10.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:10.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.04:40:10.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.04:40:10.94$vck44/valo=6,814.99 2006.257.04:40:10.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.04:40:10.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.04:40:10.94#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:10.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:10.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:10.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:10.94#ibcon#enter wrdev, iclass 6, count 0 2006.257.04:40:10.94#ibcon#first serial, iclass 6, count 0 2006.257.04:40:10.94#ibcon#enter sib2, iclass 6, count 0 2006.257.04:40:10.94#ibcon#flushed, iclass 6, count 0 2006.257.04:40:10.94#ibcon#about to write, iclass 6, count 0 2006.257.04:40:10.94#ibcon#wrote, iclass 6, count 0 2006.257.04:40:10.94#ibcon#about to read 3, iclass 6, count 0 2006.257.04:40:10.96#ibcon#read 3, iclass 6, count 0 2006.257.04:40:10.96#ibcon#about to read 4, iclass 6, count 0 2006.257.04:40:10.96#ibcon#read 4, iclass 6, count 0 2006.257.04:40:10.96#ibcon#about to read 5, iclass 6, count 0 2006.257.04:40:10.96#ibcon#read 5, iclass 6, count 0 2006.257.04:40:10.96#ibcon#about to read 6, iclass 6, count 0 2006.257.04:40:10.96#ibcon#read 6, iclass 6, count 0 2006.257.04:40:10.96#ibcon#end of sib2, iclass 6, count 0 2006.257.04:40:10.96#ibcon#*mode == 0, iclass 6, count 0 2006.257.04:40:10.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.04:40:10.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.04:40:10.96#ibcon#*before write, iclass 6, count 0 2006.257.04:40:10.96#ibcon#enter sib2, iclass 6, count 0 2006.257.04:40:10.96#ibcon#flushed, iclass 6, count 0 2006.257.04:40:10.96#ibcon#about to write, iclass 6, count 0 2006.257.04:40:10.96#ibcon#wrote, iclass 6, count 0 2006.257.04:40:10.96#ibcon#about to read 3, iclass 6, count 0 2006.257.04:40:11.00#ibcon#read 3, iclass 6, count 0 2006.257.04:40:11.00#ibcon#about to read 4, iclass 6, count 0 2006.257.04:40:11.00#ibcon#read 4, iclass 6, count 0 2006.257.04:40:11.00#ibcon#about to read 5, iclass 6, count 0 2006.257.04:40:11.00#ibcon#read 5, iclass 6, count 0 2006.257.04:40:11.00#ibcon#about to read 6, iclass 6, count 0 2006.257.04:40:11.00#ibcon#read 6, iclass 6, count 0 2006.257.04:40:11.00#ibcon#end of sib2, iclass 6, count 0 2006.257.04:40:11.00#ibcon#*after write, iclass 6, count 0 2006.257.04:40:11.00#ibcon#*before return 0, iclass 6, count 0 2006.257.04:40:11.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:11.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:11.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.04:40:11.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.04:40:11.00$vck44/va=6,4 2006.257.04:40:11.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.04:40:11.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.04:40:11.00#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:11.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:11.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:11.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:11.06#ibcon#enter wrdev, iclass 10, count 2 2006.257.04:40:11.06#ibcon#first serial, iclass 10, count 2 2006.257.04:40:11.06#ibcon#enter sib2, iclass 10, count 2 2006.257.04:40:11.06#ibcon#flushed, iclass 10, count 2 2006.257.04:40:11.06#ibcon#about to write, iclass 10, count 2 2006.257.04:40:11.06#ibcon#wrote, iclass 10, count 2 2006.257.04:40:11.06#ibcon#about to read 3, iclass 10, count 2 2006.257.04:40:11.08#ibcon#read 3, iclass 10, count 2 2006.257.04:40:11.08#ibcon#about to read 4, iclass 10, count 2 2006.257.04:40:11.08#ibcon#read 4, iclass 10, count 2 2006.257.04:40:11.08#ibcon#about to read 5, iclass 10, count 2 2006.257.04:40:11.08#ibcon#read 5, iclass 10, count 2 2006.257.04:40:11.08#ibcon#about to read 6, iclass 10, count 2 2006.257.04:40:11.08#ibcon#read 6, iclass 10, count 2 2006.257.04:40:11.08#ibcon#end of sib2, iclass 10, count 2 2006.257.04:40:11.08#ibcon#*mode == 0, iclass 10, count 2 2006.257.04:40:11.08#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.04:40:11.08#ibcon#[25=AT06-04\r\n] 2006.257.04:40:11.08#ibcon#*before write, iclass 10, count 2 2006.257.04:40:11.08#ibcon#enter sib2, iclass 10, count 2 2006.257.04:40:11.08#ibcon#flushed, iclass 10, count 2 2006.257.04:40:11.08#ibcon#about to write, iclass 10, count 2 2006.257.04:40:11.08#ibcon#wrote, iclass 10, count 2 2006.257.04:40:11.08#ibcon#about to read 3, iclass 10, count 2 2006.257.04:40:11.11#ibcon#read 3, iclass 10, count 2 2006.257.04:40:11.11#ibcon#about to read 4, iclass 10, count 2 2006.257.04:40:11.11#ibcon#read 4, iclass 10, count 2 2006.257.04:40:11.11#ibcon#about to read 5, iclass 10, count 2 2006.257.04:40:11.11#ibcon#read 5, iclass 10, count 2 2006.257.04:40:11.11#ibcon#about to read 6, iclass 10, count 2 2006.257.04:40:11.11#ibcon#read 6, iclass 10, count 2 2006.257.04:40:11.11#ibcon#end of sib2, iclass 10, count 2 2006.257.04:40:11.11#ibcon#*after write, iclass 10, count 2 2006.257.04:40:11.11#ibcon#*before return 0, iclass 10, count 2 2006.257.04:40:11.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:11.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:11.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.04:40:11.11#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:11.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:11.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:11.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:11.23#ibcon#enter wrdev, iclass 10, count 0 2006.257.04:40:11.23#ibcon#first serial, iclass 10, count 0 2006.257.04:40:11.23#ibcon#enter sib2, iclass 10, count 0 2006.257.04:40:11.23#ibcon#flushed, iclass 10, count 0 2006.257.04:40:11.23#ibcon#about to write, iclass 10, count 0 2006.257.04:40:11.23#ibcon#wrote, iclass 10, count 0 2006.257.04:40:11.23#ibcon#about to read 3, iclass 10, count 0 2006.257.04:40:11.25#ibcon#read 3, iclass 10, count 0 2006.257.04:40:11.25#ibcon#about to read 4, iclass 10, count 0 2006.257.04:40:11.25#ibcon#read 4, iclass 10, count 0 2006.257.04:40:11.25#ibcon#about to read 5, iclass 10, count 0 2006.257.04:40:11.25#ibcon#read 5, iclass 10, count 0 2006.257.04:40:11.25#ibcon#about to read 6, iclass 10, count 0 2006.257.04:40:11.25#ibcon#read 6, iclass 10, count 0 2006.257.04:40:11.25#ibcon#end of sib2, iclass 10, count 0 2006.257.04:40:11.25#ibcon#*mode == 0, iclass 10, count 0 2006.257.04:40:11.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.04:40:11.25#ibcon#[25=USB\r\n] 2006.257.04:40:11.25#ibcon#*before write, iclass 10, count 0 2006.257.04:40:11.25#ibcon#enter sib2, iclass 10, count 0 2006.257.04:40:11.25#ibcon#flushed, iclass 10, count 0 2006.257.04:40:11.25#ibcon#about to write, iclass 10, count 0 2006.257.04:40:11.25#ibcon#wrote, iclass 10, count 0 2006.257.04:40:11.25#ibcon#about to read 3, iclass 10, count 0 2006.257.04:40:11.28#ibcon#read 3, iclass 10, count 0 2006.257.04:40:11.28#ibcon#about to read 4, iclass 10, count 0 2006.257.04:40:11.28#ibcon#read 4, iclass 10, count 0 2006.257.04:40:11.28#ibcon#about to read 5, iclass 10, count 0 2006.257.04:40:11.28#ibcon#read 5, iclass 10, count 0 2006.257.04:40:11.28#ibcon#about to read 6, iclass 10, count 0 2006.257.04:40:11.28#ibcon#read 6, iclass 10, count 0 2006.257.04:40:11.28#ibcon#end of sib2, iclass 10, count 0 2006.257.04:40:11.28#ibcon#*after write, iclass 10, count 0 2006.257.04:40:11.28#ibcon#*before return 0, iclass 10, count 0 2006.257.04:40:11.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:11.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:11.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.04:40:11.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.04:40:11.28$vck44/valo=7,864.99 2006.257.04:40:11.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.04:40:11.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.04:40:11.28#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:11.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:11.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:11.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:11.28#ibcon#enter wrdev, iclass 12, count 0 2006.257.04:40:11.28#ibcon#first serial, iclass 12, count 0 2006.257.04:40:11.28#ibcon#enter sib2, iclass 12, count 0 2006.257.04:40:11.28#ibcon#flushed, iclass 12, count 0 2006.257.04:40:11.28#ibcon#about to write, iclass 12, count 0 2006.257.04:40:11.28#ibcon#wrote, iclass 12, count 0 2006.257.04:40:11.28#ibcon#about to read 3, iclass 12, count 0 2006.257.04:40:11.30#ibcon#read 3, iclass 12, count 0 2006.257.04:40:11.30#ibcon#about to read 4, iclass 12, count 0 2006.257.04:40:11.30#ibcon#read 4, iclass 12, count 0 2006.257.04:40:11.30#ibcon#about to read 5, iclass 12, count 0 2006.257.04:40:11.30#ibcon#read 5, iclass 12, count 0 2006.257.04:40:11.30#ibcon#about to read 6, iclass 12, count 0 2006.257.04:40:11.30#ibcon#read 6, iclass 12, count 0 2006.257.04:40:11.30#ibcon#end of sib2, iclass 12, count 0 2006.257.04:40:11.30#ibcon#*mode == 0, iclass 12, count 0 2006.257.04:40:11.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.04:40:11.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.04:40:11.30#ibcon#*before write, iclass 12, count 0 2006.257.04:40:11.30#ibcon#enter sib2, iclass 12, count 0 2006.257.04:40:11.30#ibcon#flushed, iclass 12, count 0 2006.257.04:40:11.30#ibcon#about to write, iclass 12, count 0 2006.257.04:40:11.30#ibcon#wrote, iclass 12, count 0 2006.257.04:40:11.30#ibcon#about to read 3, iclass 12, count 0 2006.257.04:40:11.34#ibcon#read 3, iclass 12, count 0 2006.257.04:40:11.34#ibcon#about to read 4, iclass 12, count 0 2006.257.04:40:11.34#ibcon#read 4, iclass 12, count 0 2006.257.04:40:11.34#ibcon#about to read 5, iclass 12, count 0 2006.257.04:40:11.34#ibcon#read 5, iclass 12, count 0 2006.257.04:40:11.34#ibcon#about to read 6, iclass 12, count 0 2006.257.04:40:11.34#ibcon#read 6, iclass 12, count 0 2006.257.04:40:11.34#ibcon#end of sib2, iclass 12, count 0 2006.257.04:40:11.34#ibcon#*after write, iclass 12, count 0 2006.257.04:40:11.34#ibcon#*before return 0, iclass 12, count 0 2006.257.04:40:11.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:11.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:11.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.04:40:11.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.04:40:11.34$vck44/va=7,4 2006.257.04:40:11.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.04:40:11.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.04:40:11.34#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:11.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:11.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:11.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:11.40#ibcon#enter wrdev, iclass 14, count 2 2006.257.04:40:11.40#ibcon#first serial, iclass 14, count 2 2006.257.04:40:11.40#ibcon#enter sib2, iclass 14, count 2 2006.257.04:40:11.40#ibcon#flushed, iclass 14, count 2 2006.257.04:40:11.40#ibcon#about to write, iclass 14, count 2 2006.257.04:40:11.40#ibcon#wrote, iclass 14, count 2 2006.257.04:40:11.40#ibcon#about to read 3, iclass 14, count 2 2006.257.04:40:11.42#ibcon#read 3, iclass 14, count 2 2006.257.04:40:11.42#ibcon#about to read 4, iclass 14, count 2 2006.257.04:40:11.42#ibcon#read 4, iclass 14, count 2 2006.257.04:40:11.42#ibcon#about to read 5, iclass 14, count 2 2006.257.04:40:11.42#ibcon#read 5, iclass 14, count 2 2006.257.04:40:11.42#ibcon#about to read 6, iclass 14, count 2 2006.257.04:40:11.42#ibcon#read 6, iclass 14, count 2 2006.257.04:40:11.42#ibcon#end of sib2, iclass 14, count 2 2006.257.04:40:11.42#ibcon#*mode == 0, iclass 14, count 2 2006.257.04:40:11.42#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.04:40:11.42#ibcon#[25=AT07-04\r\n] 2006.257.04:40:11.42#ibcon#*before write, iclass 14, count 2 2006.257.04:40:11.42#ibcon#enter sib2, iclass 14, count 2 2006.257.04:40:11.42#ibcon#flushed, iclass 14, count 2 2006.257.04:40:11.42#ibcon#about to write, iclass 14, count 2 2006.257.04:40:11.42#ibcon#wrote, iclass 14, count 2 2006.257.04:40:11.42#ibcon#about to read 3, iclass 14, count 2 2006.257.04:40:11.45#ibcon#read 3, iclass 14, count 2 2006.257.04:40:11.45#ibcon#about to read 4, iclass 14, count 2 2006.257.04:40:11.45#ibcon#read 4, iclass 14, count 2 2006.257.04:40:11.45#ibcon#about to read 5, iclass 14, count 2 2006.257.04:40:11.45#ibcon#read 5, iclass 14, count 2 2006.257.04:40:11.45#ibcon#about to read 6, iclass 14, count 2 2006.257.04:40:11.45#ibcon#read 6, iclass 14, count 2 2006.257.04:40:11.45#ibcon#end of sib2, iclass 14, count 2 2006.257.04:40:11.45#ibcon#*after write, iclass 14, count 2 2006.257.04:40:11.45#ibcon#*before return 0, iclass 14, count 2 2006.257.04:40:11.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:11.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:11.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.04:40:11.45#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:11.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:11.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:11.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:11.57#ibcon#enter wrdev, iclass 14, count 0 2006.257.04:40:11.57#ibcon#first serial, iclass 14, count 0 2006.257.04:40:11.57#ibcon#enter sib2, iclass 14, count 0 2006.257.04:40:11.57#ibcon#flushed, iclass 14, count 0 2006.257.04:40:11.57#ibcon#about to write, iclass 14, count 0 2006.257.04:40:11.57#ibcon#wrote, iclass 14, count 0 2006.257.04:40:11.57#ibcon#about to read 3, iclass 14, count 0 2006.257.04:40:11.59#ibcon#read 3, iclass 14, count 0 2006.257.04:40:11.59#ibcon#about to read 4, iclass 14, count 0 2006.257.04:40:11.59#ibcon#read 4, iclass 14, count 0 2006.257.04:40:11.59#ibcon#about to read 5, iclass 14, count 0 2006.257.04:40:11.59#ibcon#read 5, iclass 14, count 0 2006.257.04:40:11.59#ibcon#about to read 6, iclass 14, count 0 2006.257.04:40:11.59#ibcon#read 6, iclass 14, count 0 2006.257.04:40:11.59#ibcon#end of sib2, iclass 14, count 0 2006.257.04:40:11.59#ibcon#*mode == 0, iclass 14, count 0 2006.257.04:40:11.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.04:40:11.59#ibcon#[25=USB\r\n] 2006.257.04:40:11.59#ibcon#*before write, iclass 14, count 0 2006.257.04:40:11.59#ibcon#enter sib2, iclass 14, count 0 2006.257.04:40:11.59#ibcon#flushed, iclass 14, count 0 2006.257.04:40:11.59#ibcon#about to write, iclass 14, count 0 2006.257.04:40:11.59#ibcon#wrote, iclass 14, count 0 2006.257.04:40:11.59#ibcon#about to read 3, iclass 14, count 0 2006.257.04:40:11.62#ibcon#read 3, iclass 14, count 0 2006.257.04:40:11.62#ibcon#about to read 4, iclass 14, count 0 2006.257.04:40:11.62#ibcon#read 4, iclass 14, count 0 2006.257.04:40:11.62#ibcon#about to read 5, iclass 14, count 0 2006.257.04:40:11.62#ibcon#read 5, iclass 14, count 0 2006.257.04:40:11.62#ibcon#about to read 6, iclass 14, count 0 2006.257.04:40:11.62#ibcon#read 6, iclass 14, count 0 2006.257.04:40:11.62#ibcon#end of sib2, iclass 14, count 0 2006.257.04:40:11.62#ibcon#*after write, iclass 14, count 0 2006.257.04:40:11.62#ibcon#*before return 0, iclass 14, count 0 2006.257.04:40:11.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:11.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:11.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.04:40:11.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.04:40:11.62$vck44/valo=8,884.99 2006.257.04:40:11.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.04:40:11.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.04:40:11.62#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:11.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:40:11.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:40:11.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:40:11.62#ibcon#enter wrdev, iclass 16, count 0 2006.257.04:40:11.62#ibcon#first serial, iclass 16, count 0 2006.257.04:40:11.62#ibcon#enter sib2, iclass 16, count 0 2006.257.04:40:11.62#ibcon#flushed, iclass 16, count 0 2006.257.04:40:11.62#ibcon#about to write, iclass 16, count 0 2006.257.04:40:11.62#ibcon#wrote, iclass 16, count 0 2006.257.04:40:11.62#ibcon#about to read 3, iclass 16, count 0 2006.257.04:40:11.64#ibcon#read 3, iclass 16, count 0 2006.257.04:40:11.64#ibcon#about to read 4, iclass 16, count 0 2006.257.04:40:11.64#ibcon#read 4, iclass 16, count 0 2006.257.04:40:11.64#ibcon#about to read 5, iclass 16, count 0 2006.257.04:40:11.64#ibcon#read 5, iclass 16, count 0 2006.257.04:40:11.64#ibcon#about to read 6, iclass 16, count 0 2006.257.04:40:11.64#ibcon#read 6, iclass 16, count 0 2006.257.04:40:11.64#ibcon#end of sib2, iclass 16, count 0 2006.257.04:40:11.64#ibcon#*mode == 0, iclass 16, count 0 2006.257.04:40:11.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.04:40:11.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.04:40:11.64#ibcon#*before write, iclass 16, count 0 2006.257.04:40:11.64#ibcon#enter sib2, iclass 16, count 0 2006.257.04:40:11.64#ibcon#flushed, iclass 16, count 0 2006.257.04:40:11.64#ibcon#about to write, iclass 16, count 0 2006.257.04:40:11.64#ibcon#wrote, iclass 16, count 0 2006.257.04:40:11.64#ibcon#about to read 3, iclass 16, count 0 2006.257.04:40:11.68#ibcon#read 3, iclass 16, count 0 2006.257.04:40:11.68#ibcon#about to read 4, iclass 16, count 0 2006.257.04:40:11.68#ibcon#read 4, iclass 16, count 0 2006.257.04:40:11.68#ibcon#about to read 5, iclass 16, count 0 2006.257.04:40:11.68#ibcon#read 5, iclass 16, count 0 2006.257.04:40:11.68#ibcon#about to read 6, iclass 16, count 0 2006.257.04:40:11.68#ibcon#read 6, iclass 16, count 0 2006.257.04:40:11.68#ibcon#end of sib2, iclass 16, count 0 2006.257.04:40:11.68#ibcon#*after write, iclass 16, count 0 2006.257.04:40:11.68#ibcon#*before return 0, iclass 16, count 0 2006.257.04:40:11.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:40:11.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.04:40:11.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.04:40:11.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.04:40:11.68$vck44/va=8,4 2006.257.04:40:11.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.04:40:11.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.04:40:11.68#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:11.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:40:11.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:40:11.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:40:11.74#ibcon#enter wrdev, iclass 18, count 2 2006.257.04:40:11.74#ibcon#first serial, iclass 18, count 2 2006.257.04:40:11.74#ibcon#enter sib2, iclass 18, count 2 2006.257.04:40:11.74#ibcon#flushed, iclass 18, count 2 2006.257.04:40:11.74#ibcon#about to write, iclass 18, count 2 2006.257.04:40:11.74#ibcon#wrote, iclass 18, count 2 2006.257.04:40:11.74#ibcon#about to read 3, iclass 18, count 2 2006.257.04:40:11.76#ibcon#read 3, iclass 18, count 2 2006.257.04:40:11.76#ibcon#about to read 4, iclass 18, count 2 2006.257.04:40:11.76#ibcon#read 4, iclass 18, count 2 2006.257.04:40:11.76#ibcon#about to read 5, iclass 18, count 2 2006.257.04:40:11.76#ibcon#read 5, iclass 18, count 2 2006.257.04:40:11.76#ibcon#about to read 6, iclass 18, count 2 2006.257.04:40:11.76#ibcon#read 6, iclass 18, count 2 2006.257.04:40:11.76#ibcon#end of sib2, iclass 18, count 2 2006.257.04:40:11.76#ibcon#*mode == 0, iclass 18, count 2 2006.257.04:40:11.76#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.04:40:11.76#ibcon#[25=AT08-04\r\n] 2006.257.04:40:11.76#ibcon#*before write, iclass 18, count 2 2006.257.04:40:11.76#ibcon#enter sib2, iclass 18, count 2 2006.257.04:40:11.76#ibcon#flushed, iclass 18, count 2 2006.257.04:40:11.76#ibcon#about to write, iclass 18, count 2 2006.257.04:40:11.76#ibcon#wrote, iclass 18, count 2 2006.257.04:40:11.76#ibcon#about to read 3, iclass 18, count 2 2006.257.04:40:11.79#ibcon#read 3, iclass 18, count 2 2006.257.04:40:11.79#ibcon#about to read 4, iclass 18, count 2 2006.257.04:40:11.79#ibcon#read 4, iclass 18, count 2 2006.257.04:40:11.79#ibcon#about to read 5, iclass 18, count 2 2006.257.04:40:11.79#ibcon#read 5, iclass 18, count 2 2006.257.04:40:11.79#ibcon#about to read 6, iclass 18, count 2 2006.257.04:40:11.79#ibcon#read 6, iclass 18, count 2 2006.257.04:40:11.79#ibcon#end of sib2, iclass 18, count 2 2006.257.04:40:11.79#ibcon#*after write, iclass 18, count 2 2006.257.04:40:11.79#ibcon#*before return 0, iclass 18, count 2 2006.257.04:40:11.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:40:11.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.04:40:11.79#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.04:40:11.79#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:11.79#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:40:11.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:40:11.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:40:11.91#ibcon#enter wrdev, iclass 18, count 0 2006.257.04:40:11.91#ibcon#first serial, iclass 18, count 0 2006.257.04:40:11.91#ibcon#enter sib2, iclass 18, count 0 2006.257.04:40:11.91#ibcon#flushed, iclass 18, count 0 2006.257.04:40:11.91#ibcon#about to write, iclass 18, count 0 2006.257.04:40:11.91#ibcon#wrote, iclass 18, count 0 2006.257.04:40:11.91#ibcon#about to read 3, iclass 18, count 0 2006.257.04:40:11.93#ibcon#read 3, iclass 18, count 0 2006.257.04:40:11.93#ibcon#about to read 4, iclass 18, count 0 2006.257.04:40:11.93#ibcon#read 4, iclass 18, count 0 2006.257.04:40:11.93#ibcon#about to read 5, iclass 18, count 0 2006.257.04:40:11.93#ibcon#read 5, iclass 18, count 0 2006.257.04:40:11.93#ibcon#about to read 6, iclass 18, count 0 2006.257.04:40:11.93#ibcon#read 6, iclass 18, count 0 2006.257.04:40:11.93#ibcon#end of sib2, iclass 18, count 0 2006.257.04:40:11.93#ibcon#*mode == 0, iclass 18, count 0 2006.257.04:40:11.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.04:40:11.93#ibcon#[25=USB\r\n] 2006.257.04:40:11.93#ibcon#*before write, iclass 18, count 0 2006.257.04:40:11.93#ibcon#enter sib2, iclass 18, count 0 2006.257.04:40:11.93#ibcon#flushed, iclass 18, count 0 2006.257.04:40:11.93#ibcon#about to write, iclass 18, count 0 2006.257.04:40:11.93#ibcon#wrote, iclass 18, count 0 2006.257.04:40:11.93#ibcon#about to read 3, iclass 18, count 0 2006.257.04:40:11.96#ibcon#read 3, iclass 18, count 0 2006.257.04:40:11.96#ibcon#about to read 4, iclass 18, count 0 2006.257.04:40:11.96#ibcon#read 4, iclass 18, count 0 2006.257.04:40:11.96#ibcon#about to read 5, iclass 18, count 0 2006.257.04:40:11.96#ibcon#read 5, iclass 18, count 0 2006.257.04:40:11.96#ibcon#about to read 6, iclass 18, count 0 2006.257.04:40:11.96#ibcon#read 6, iclass 18, count 0 2006.257.04:40:11.96#ibcon#end of sib2, iclass 18, count 0 2006.257.04:40:11.96#ibcon#*after write, iclass 18, count 0 2006.257.04:40:11.96#ibcon#*before return 0, iclass 18, count 0 2006.257.04:40:11.96#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:40:11.96#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.04:40:11.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.04:40:11.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.04:40:11.96$vck44/vblo=1,629.99 2006.257.04:40:11.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.04:40:11.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.04:40:11.96#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:11.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:11.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:11.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:11.96#ibcon#enter wrdev, iclass 20, count 0 2006.257.04:40:11.96#ibcon#first serial, iclass 20, count 0 2006.257.04:40:11.96#ibcon#enter sib2, iclass 20, count 0 2006.257.04:40:11.96#ibcon#flushed, iclass 20, count 0 2006.257.04:40:11.96#ibcon#about to write, iclass 20, count 0 2006.257.04:40:11.96#ibcon#wrote, iclass 20, count 0 2006.257.04:40:11.96#ibcon#about to read 3, iclass 20, count 0 2006.257.04:40:11.98#ibcon#read 3, iclass 20, count 0 2006.257.04:40:11.98#ibcon#about to read 4, iclass 20, count 0 2006.257.04:40:11.98#ibcon#read 4, iclass 20, count 0 2006.257.04:40:11.98#ibcon#about to read 5, iclass 20, count 0 2006.257.04:40:11.98#ibcon#read 5, iclass 20, count 0 2006.257.04:40:11.98#ibcon#about to read 6, iclass 20, count 0 2006.257.04:40:11.98#ibcon#read 6, iclass 20, count 0 2006.257.04:40:11.98#ibcon#end of sib2, iclass 20, count 0 2006.257.04:40:11.98#ibcon#*mode == 0, iclass 20, count 0 2006.257.04:40:11.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.04:40:11.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.04:40:11.98#ibcon#*before write, iclass 20, count 0 2006.257.04:40:11.98#ibcon#enter sib2, iclass 20, count 0 2006.257.04:40:11.98#ibcon#flushed, iclass 20, count 0 2006.257.04:40:11.98#ibcon#about to write, iclass 20, count 0 2006.257.04:40:11.98#ibcon#wrote, iclass 20, count 0 2006.257.04:40:11.98#ibcon#about to read 3, iclass 20, count 0 2006.257.04:40:12.02#ibcon#read 3, iclass 20, count 0 2006.257.04:40:12.02#ibcon#about to read 4, iclass 20, count 0 2006.257.04:40:12.02#ibcon#read 4, iclass 20, count 0 2006.257.04:40:12.02#ibcon#about to read 5, iclass 20, count 0 2006.257.04:40:12.02#ibcon#read 5, iclass 20, count 0 2006.257.04:40:12.02#ibcon#about to read 6, iclass 20, count 0 2006.257.04:40:12.02#ibcon#read 6, iclass 20, count 0 2006.257.04:40:12.02#ibcon#end of sib2, iclass 20, count 0 2006.257.04:40:12.02#ibcon#*after write, iclass 20, count 0 2006.257.04:40:12.02#ibcon#*before return 0, iclass 20, count 0 2006.257.04:40:12.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:12.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:12.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.04:40:12.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.04:40:12.02$vck44/vb=1,4 2006.257.04:40:12.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.04:40:12.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.04:40:12.02#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:12.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:40:12.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:40:12.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:40:12.02#ibcon#enter wrdev, iclass 22, count 2 2006.257.04:40:12.02#ibcon#first serial, iclass 22, count 2 2006.257.04:40:12.02#ibcon#enter sib2, iclass 22, count 2 2006.257.04:40:12.02#ibcon#flushed, iclass 22, count 2 2006.257.04:40:12.02#ibcon#about to write, iclass 22, count 2 2006.257.04:40:12.02#ibcon#wrote, iclass 22, count 2 2006.257.04:40:12.02#ibcon#about to read 3, iclass 22, count 2 2006.257.04:40:12.04#ibcon#read 3, iclass 22, count 2 2006.257.04:40:12.04#ibcon#about to read 4, iclass 22, count 2 2006.257.04:40:12.04#ibcon#read 4, iclass 22, count 2 2006.257.04:40:12.04#ibcon#about to read 5, iclass 22, count 2 2006.257.04:40:12.04#ibcon#read 5, iclass 22, count 2 2006.257.04:40:12.04#ibcon#about to read 6, iclass 22, count 2 2006.257.04:40:12.04#ibcon#read 6, iclass 22, count 2 2006.257.04:40:12.04#ibcon#end of sib2, iclass 22, count 2 2006.257.04:40:12.04#ibcon#*mode == 0, iclass 22, count 2 2006.257.04:40:12.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.04:40:12.04#ibcon#[27=AT01-04\r\n] 2006.257.04:40:12.04#ibcon#*before write, iclass 22, count 2 2006.257.04:40:12.04#ibcon#enter sib2, iclass 22, count 2 2006.257.04:40:12.04#ibcon#flushed, iclass 22, count 2 2006.257.04:40:12.04#ibcon#about to write, iclass 22, count 2 2006.257.04:40:12.04#ibcon#wrote, iclass 22, count 2 2006.257.04:40:12.04#ibcon#about to read 3, iclass 22, count 2 2006.257.04:40:12.07#ibcon#read 3, iclass 22, count 2 2006.257.04:40:12.07#ibcon#about to read 4, iclass 22, count 2 2006.257.04:40:12.07#ibcon#read 4, iclass 22, count 2 2006.257.04:40:12.07#ibcon#about to read 5, iclass 22, count 2 2006.257.04:40:12.07#ibcon#read 5, iclass 22, count 2 2006.257.04:40:12.07#ibcon#about to read 6, iclass 22, count 2 2006.257.04:40:12.07#ibcon#read 6, iclass 22, count 2 2006.257.04:40:12.07#ibcon#end of sib2, iclass 22, count 2 2006.257.04:40:12.07#ibcon#*after write, iclass 22, count 2 2006.257.04:40:12.07#ibcon#*before return 0, iclass 22, count 2 2006.257.04:40:12.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:40:12.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.04:40:12.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.04:40:12.07#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:12.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:40:12.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:40:12.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:40:12.19#ibcon#enter wrdev, iclass 22, count 0 2006.257.04:40:12.19#ibcon#first serial, iclass 22, count 0 2006.257.04:40:12.19#ibcon#enter sib2, iclass 22, count 0 2006.257.04:40:12.19#ibcon#flushed, iclass 22, count 0 2006.257.04:40:12.19#ibcon#about to write, iclass 22, count 0 2006.257.04:40:12.19#ibcon#wrote, iclass 22, count 0 2006.257.04:40:12.19#ibcon#about to read 3, iclass 22, count 0 2006.257.04:40:12.21#ibcon#read 3, iclass 22, count 0 2006.257.04:40:12.21#ibcon#about to read 4, iclass 22, count 0 2006.257.04:40:12.21#ibcon#read 4, iclass 22, count 0 2006.257.04:40:12.21#ibcon#about to read 5, iclass 22, count 0 2006.257.04:40:12.21#ibcon#read 5, iclass 22, count 0 2006.257.04:40:12.21#ibcon#about to read 6, iclass 22, count 0 2006.257.04:40:12.21#ibcon#read 6, iclass 22, count 0 2006.257.04:40:12.21#ibcon#end of sib2, iclass 22, count 0 2006.257.04:40:12.21#ibcon#*mode == 0, iclass 22, count 0 2006.257.04:40:12.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.04:40:12.21#ibcon#[27=USB\r\n] 2006.257.04:40:12.21#ibcon#*before write, iclass 22, count 0 2006.257.04:40:12.21#ibcon#enter sib2, iclass 22, count 0 2006.257.04:40:12.21#ibcon#flushed, iclass 22, count 0 2006.257.04:40:12.21#ibcon#about to write, iclass 22, count 0 2006.257.04:40:12.21#ibcon#wrote, iclass 22, count 0 2006.257.04:40:12.21#ibcon#about to read 3, iclass 22, count 0 2006.257.04:40:12.24#ibcon#read 3, iclass 22, count 0 2006.257.04:40:12.24#ibcon#about to read 4, iclass 22, count 0 2006.257.04:40:12.24#ibcon#read 4, iclass 22, count 0 2006.257.04:40:12.24#ibcon#about to read 5, iclass 22, count 0 2006.257.04:40:12.24#ibcon#read 5, iclass 22, count 0 2006.257.04:40:12.24#ibcon#about to read 6, iclass 22, count 0 2006.257.04:40:12.24#ibcon#read 6, iclass 22, count 0 2006.257.04:40:12.24#ibcon#end of sib2, iclass 22, count 0 2006.257.04:40:12.24#ibcon#*after write, iclass 22, count 0 2006.257.04:40:12.24#ibcon#*before return 0, iclass 22, count 0 2006.257.04:40:12.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:40:12.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.04:40:12.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.04:40:12.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.04:40:12.24$vck44/vblo=2,634.99 2006.257.04:40:12.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.04:40:12.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.04:40:12.24#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:12.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:12.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:12.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:12.24#ibcon#enter wrdev, iclass 24, count 0 2006.257.04:40:12.24#ibcon#first serial, iclass 24, count 0 2006.257.04:40:12.24#ibcon#enter sib2, iclass 24, count 0 2006.257.04:40:12.24#ibcon#flushed, iclass 24, count 0 2006.257.04:40:12.24#ibcon#about to write, iclass 24, count 0 2006.257.04:40:12.24#ibcon#wrote, iclass 24, count 0 2006.257.04:40:12.24#ibcon#about to read 3, iclass 24, count 0 2006.257.04:40:12.26#ibcon#read 3, iclass 24, count 0 2006.257.04:40:12.26#ibcon#about to read 4, iclass 24, count 0 2006.257.04:40:12.26#ibcon#read 4, iclass 24, count 0 2006.257.04:40:12.26#ibcon#about to read 5, iclass 24, count 0 2006.257.04:40:12.26#ibcon#read 5, iclass 24, count 0 2006.257.04:40:12.26#ibcon#about to read 6, iclass 24, count 0 2006.257.04:40:12.26#ibcon#read 6, iclass 24, count 0 2006.257.04:40:12.26#ibcon#end of sib2, iclass 24, count 0 2006.257.04:40:12.26#ibcon#*mode == 0, iclass 24, count 0 2006.257.04:40:12.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.04:40:12.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.04:40:12.26#ibcon#*before write, iclass 24, count 0 2006.257.04:40:12.26#ibcon#enter sib2, iclass 24, count 0 2006.257.04:40:12.26#ibcon#flushed, iclass 24, count 0 2006.257.04:40:12.26#ibcon#about to write, iclass 24, count 0 2006.257.04:40:12.26#ibcon#wrote, iclass 24, count 0 2006.257.04:40:12.26#ibcon#about to read 3, iclass 24, count 0 2006.257.04:40:12.30#ibcon#read 3, iclass 24, count 0 2006.257.04:40:12.30#ibcon#about to read 4, iclass 24, count 0 2006.257.04:40:12.30#ibcon#read 4, iclass 24, count 0 2006.257.04:40:12.30#ibcon#about to read 5, iclass 24, count 0 2006.257.04:40:12.30#ibcon#read 5, iclass 24, count 0 2006.257.04:40:12.30#ibcon#about to read 6, iclass 24, count 0 2006.257.04:40:12.30#ibcon#read 6, iclass 24, count 0 2006.257.04:40:12.30#ibcon#end of sib2, iclass 24, count 0 2006.257.04:40:12.30#ibcon#*after write, iclass 24, count 0 2006.257.04:40:12.30#ibcon#*before return 0, iclass 24, count 0 2006.257.04:40:12.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:12.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.04:40:12.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.04:40:12.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.04:40:12.30$vck44/vb=2,5 2006.257.04:40:12.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.04:40:12.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.04:40:12.30#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:12.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:12.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:12.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:12.36#ibcon#enter wrdev, iclass 26, count 2 2006.257.04:40:12.36#ibcon#first serial, iclass 26, count 2 2006.257.04:40:12.36#ibcon#enter sib2, iclass 26, count 2 2006.257.04:40:12.36#ibcon#flushed, iclass 26, count 2 2006.257.04:40:12.36#ibcon#about to write, iclass 26, count 2 2006.257.04:40:12.36#ibcon#wrote, iclass 26, count 2 2006.257.04:40:12.36#ibcon#about to read 3, iclass 26, count 2 2006.257.04:40:12.38#ibcon#read 3, iclass 26, count 2 2006.257.04:40:12.38#ibcon#about to read 4, iclass 26, count 2 2006.257.04:40:12.38#ibcon#read 4, iclass 26, count 2 2006.257.04:40:12.38#ibcon#about to read 5, iclass 26, count 2 2006.257.04:40:12.38#ibcon#read 5, iclass 26, count 2 2006.257.04:40:12.38#ibcon#about to read 6, iclass 26, count 2 2006.257.04:40:12.38#ibcon#read 6, iclass 26, count 2 2006.257.04:40:12.38#ibcon#end of sib2, iclass 26, count 2 2006.257.04:40:12.38#ibcon#*mode == 0, iclass 26, count 2 2006.257.04:40:12.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.04:40:12.38#ibcon#[27=AT02-05\r\n] 2006.257.04:40:12.38#ibcon#*before write, iclass 26, count 2 2006.257.04:40:12.38#ibcon#enter sib2, iclass 26, count 2 2006.257.04:40:12.38#ibcon#flushed, iclass 26, count 2 2006.257.04:40:12.38#ibcon#about to write, iclass 26, count 2 2006.257.04:40:12.38#ibcon#wrote, iclass 26, count 2 2006.257.04:40:12.38#ibcon#about to read 3, iclass 26, count 2 2006.257.04:40:12.41#ibcon#read 3, iclass 26, count 2 2006.257.04:40:12.41#ibcon#about to read 4, iclass 26, count 2 2006.257.04:40:12.41#ibcon#read 4, iclass 26, count 2 2006.257.04:40:12.41#ibcon#about to read 5, iclass 26, count 2 2006.257.04:40:12.41#ibcon#read 5, iclass 26, count 2 2006.257.04:40:12.41#ibcon#about to read 6, iclass 26, count 2 2006.257.04:40:12.41#ibcon#read 6, iclass 26, count 2 2006.257.04:40:12.41#ibcon#end of sib2, iclass 26, count 2 2006.257.04:40:12.41#ibcon#*after write, iclass 26, count 2 2006.257.04:40:12.41#ibcon#*before return 0, iclass 26, count 2 2006.257.04:40:12.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:12.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.04:40:12.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.04:40:12.41#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:12.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:12.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:12.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:12.53#ibcon#enter wrdev, iclass 26, count 0 2006.257.04:40:12.53#ibcon#first serial, iclass 26, count 0 2006.257.04:40:12.53#ibcon#enter sib2, iclass 26, count 0 2006.257.04:40:12.53#ibcon#flushed, iclass 26, count 0 2006.257.04:40:12.53#ibcon#about to write, iclass 26, count 0 2006.257.04:40:12.53#ibcon#wrote, iclass 26, count 0 2006.257.04:40:12.53#ibcon#about to read 3, iclass 26, count 0 2006.257.04:40:12.55#ibcon#read 3, iclass 26, count 0 2006.257.04:40:12.55#ibcon#about to read 4, iclass 26, count 0 2006.257.04:40:12.55#ibcon#read 4, iclass 26, count 0 2006.257.04:40:12.55#ibcon#about to read 5, iclass 26, count 0 2006.257.04:40:12.55#ibcon#read 5, iclass 26, count 0 2006.257.04:40:12.55#ibcon#about to read 6, iclass 26, count 0 2006.257.04:40:12.55#ibcon#read 6, iclass 26, count 0 2006.257.04:40:12.55#ibcon#end of sib2, iclass 26, count 0 2006.257.04:40:12.55#ibcon#*mode == 0, iclass 26, count 0 2006.257.04:40:12.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.04:40:12.55#ibcon#[27=USB\r\n] 2006.257.04:40:12.55#ibcon#*before write, iclass 26, count 0 2006.257.04:40:12.55#ibcon#enter sib2, iclass 26, count 0 2006.257.04:40:12.55#ibcon#flushed, iclass 26, count 0 2006.257.04:40:12.55#ibcon#about to write, iclass 26, count 0 2006.257.04:40:12.55#ibcon#wrote, iclass 26, count 0 2006.257.04:40:12.55#ibcon#about to read 3, iclass 26, count 0 2006.257.04:40:12.58#ibcon#read 3, iclass 26, count 0 2006.257.04:40:12.58#ibcon#about to read 4, iclass 26, count 0 2006.257.04:40:12.58#ibcon#read 4, iclass 26, count 0 2006.257.04:40:12.58#ibcon#about to read 5, iclass 26, count 0 2006.257.04:40:12.58#ibcon#read 5, iclass 26, count 0 2006.257.04:40:12.58#ibcon#about to read 6, iclass 26, count 0 2006.257.04:40:12.58#ibcon#read 6, iclass 26, count 0 2006.257.04:40:12.58#ibcon#end of sib2, iclass 26, count 0 2006.257.04:40:12.58#ibcon#*after write, iclass 26, count 0 2006.257.04:40:12.58#ibcon#*before return 0, iclass 26, count 0 2006.257.04:40:12.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:12.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.04:40:12.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.04:40:12.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.04:40:12.58$vck44/vblo=3,649.99 2006.257.04:40:12.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.04:40:12.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.04:40:12.58#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:12.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:12.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:12.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:12.58#ibcon#enter wrdev, iclass 28, count 0 2006.257.04:40:12.58#ibcon#first serial, iclass 28, count 0 2006.257.04:40:12.58#ibcon#enter sib2, iclass 28, count 0 2006.257.04:40:12.58#ibcon#flushed, iclass 28, count 0 2006.257.04:40:12.58#ibcon#about to write, iclass 28, count 0 2006.257.04:40:12.58#ibcon#wrote, iclass 28, count 0 2006.257.04:40:12.58#ibcon#about to read 3, iclass 28, count 0 2006.257.04:40:12.60#ibcon#read 3, iclass 28, count 0 2006.257.04:40:12.60#ibcon#about to read 4, iclass 28, count 0 2006.257.04:40:12.60#ibcon#read 4, iclass 28, count 0 2006.257.04:40:12.60#ibcon#about to read 5, iclass 28, count 0 2006.257.04:40:12.60#ibcon#read 5, iclass 28, count 0 2006.257.04:40:12.60#ibcon#about to read 6, iclass 28, count 0 2006.257.04:40:12.60#ibcon#read 6, iclass 28, count 0 2006.257.04:40:12.60#ibcon#end of sib2, iclass 28, count 0 2006.257.04:40:12.60#ibcon#*mode == 0, iclass 28, count 0 2006.257.04:40:12.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.04:40:12.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.04:40:12.60#ibcon#*before write, iclass 28, count 0 2006.257.04:40:12.60#ibcon#enter sib2, iclass 28, count 0 2006.257.04:40:12.60#ibcon#flushed, iclass 28, count 0 2006.257.04:40:12.60#ibcon#about to write, iclass 28, count 0 2006.257.04:40:12.60#ibcon#wrote, iclass 28, count 0 2006.257.04:40:12.60#ibcon#about to read 3, iclass 28, count 0 2006.257.04:40:12.64#ibcon#read 3, iclass 28, count 0 2006.257.04:40:12.64#ibcon#about to read 4, iclass 28, count 0 2006.257.04:40:12.64#ibcon#read 4, iclass 28, count 0 2006.257.04:40:12.64#ibcon#about to read 5, iclass 28, count 0 2006.257.04:40:12.64#ibcon#read 5, iclass 28, count 0 2006.257.04:40:12.64#ibcon#about to read 6, iclass 28, count 0 2006.257.04:40:12.64#ibcon#read 6, iclass 28, count 0 2006.257.04:40:12.64#ibcon#end of sib2, iclass 28, count 0 2006.257.04:40:12.64#ibcon#*after write, iclass 28, count 0 2006.257.04:40:12.64#ibcon#*before return 0, iclass 28, count 0 2006.257.04:40:12.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:12.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.04:40:12.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.04:40:12.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.04:40:12.64$vck44/vb=3,4 2006.257.04:40:12.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.04:40:12.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.04:40:12.64#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:12.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:12.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:12.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:12.70#ibcon#enter wrdev, iclass 30, count 2 2006.257.04:40:12.70#ibcon#first serial, iclass 30, count 2 2006.257.04:40:12.70#ibcon#enter sib2, iclass 30, count 2 2006.257.04:40:12.70#ibcon#flushed, iclass 30, count 2 2006.257.04:40:12.70#ibcon#about to write, iclass 30, count 2 2006.257.04:40:12.70#ibcon#wrote, iclass 30, count 2 2006.257.04:40:12.70#ibcon#about to read 3, iclass 30, count 2 2006.257.04:40:12.72#ibcon#read 3, iclass 30, count 2 2006.257.04:40:12.72#ibcon#about to read 4, iclass 30, count 2 2006.257.04:40:12.72#ibcon#read 4, iclass 30, count 2 2006.257.04:40:12.72#ibcon#about to read 5, iclass 30, count 2 2006.257.04:40:12.72#ibcon#read 5, iclass 30, count 2 2006.257.04:40:12.72#ibcon#about to read 6, iclass 30, count 2 2006.257.04:40:12.72#ibcon#read 6, iclass 30, count 2 2006.257.04:40:12.72#ibcon#end of sib2, iclass 30, count 2 2006.257.04:40:12.72#ibcon#*mode == 0, iclass 30, count 2 2006.257.04:40:12.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.04:40:12.72#ibcon#[27=AT03-04\r\n] 2006.257.04:40:12.72#ibcon#*before write, iclass 30, count 2 2006.257.04:40:12.72#ibcon#enter sib2, iclass 30, count 2 2006.257.04:40:12.72#ibcon#flushed, iclass 30, count 2 2006.257.04:40:12.72#ibcon#about to write, iclass 30, count 2 2006.257.04:40:12.72#ibcon#wrote, iclass 30, count 2 2006.257.04:40:12.72#ibcon#about to read 3, iclass 30, count 2 2006.257.04:40:12.75#ibcon#read 3, iclass 30, count 2 2006.257.04:40:12.75#ibcon#about to read 4, iclass 30, count 2 2006.257.04:40:12.75#ibcon#read 4, iclass 30, count 2 2006.257.04:40:12.75#ibcon#about to read 5, iclass 30, count 2 2006.257.04:40:12.75#ibcon#read 5, iclass 30, count 2 2006.257.04:40:12.75#ibcon#about to read 6, iclass 30, count 2 2006.257.04:40:12.75#ibcon#read 6, iclass 30, count 2 2006.257.04:40:12.75#ibcon#end of sib2, iclass 30, count 2 2006.257.04:40:12.75#ibcon#*after write, iclass 30, count 2 2006.257.04:40:12.75#ibcon#*before return 0, iclass 30, count 2 2006.257.04:40:12.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:12.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.04:40:12.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.04:40:12.75#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:12.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:12.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:12.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:12.87#ibcon#enter wrdev, iclass 30, count 0 2006.257.04:40:12.87#ibcon#first serial, iclass 30, count 0 2006.257.04:40:12.87#ibcon#enter sib2, iclass 30, count 0 2006.257.04:40:12.87#ibcon#flushed, iclass 30, count 0 2006.257.04:40:12.87#ibcon#about to write, iclass 30, count 0 2006.257.04:40:12.87#ibcon#wrote, iclass 30, count 0 2006.257.04:40:12.87#ibcon#about to read 3, iclass 30, count 0 2006.257.04:40:12.89#ibcon#read 3, iclass 30, count 0 2006.257.04:40:12.89#ibcon#about to read 4, iclass 30, count 0 2006.257.04:40:12.89#ibcon#read 4, iclass 30, count 0 2006.257.04:40:12.89#ibcon#about to read 5, iclass 30, count 0 2006.257.04:40:12.89#ibcon#read 5, iclass 30, count 0 2006.257.04:40:12.89#ibcon#about to read 6, iclass 30, count 0 2006.257.04:40:12.89#ibcon#read 6, iclass 30, count 0 2006.257.04:40:12.89#ibcon#end of sib2, iclass 30, count 0 2006.257.04:40:12.89#ibcon#*mode == 0, iclass 30, count 0 2006.257.04:40:12.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.04:40:12.89#ibcon#[27=USB\r\n] 2006.257.04:40:12.89#ibcon#*before write, iclass 30, count 0 2006.257.04:40:12.89#ibcon#enter sib2, iclass 30, count 0 2006.257.04:40:12.89#ibcon#flushed, iclass 30, count 0 2006.257.04:40:12.89#ibcon#about to write, iclass 30, count 0 2006.257.04:40:12.89#ibcon#wrote, iclass 30, count 0 2006.257.04:40:12.89#ibcon#about to read 3, iclass 30, count 0 2006.257.04:40:12.92#ibcon#read 3, iclass 30, count 0 2006.257.04:40:12.92#ibcon#about to read 4, iclass 30, count 0 2006.257.04:40:12.92#ibcon#read 4, iclass 30, count 0 2006.257.04:40:12.92#ibcon#about to read 5, iclass 30, count 0 2006.257.04:40:12.92#ibcon#read 5, iclass 30, count 0 2006.257.04:40:12.92#ibcon#about to read 6, iclass 30, count 0 2006.257.04:40:12.92#ibcon#read 6, iclass 30, count 0 2006.257.04:40:12.92#ibcon#end of sib2, iclass 30, count 0 2006.257.04:40:12.92#ibcon#*after write, iclass 30, count 0 2006.257.04:40:12.92#ibcon#*before return 0, iclass 30, count 0 2006.257.04:40:12.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:12.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.04:40:12.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.04:40:12.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.04:40:12.92$vck44/vblo=4,679.99 2006.257.04:40:12.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.04:40:12.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.04:40:12.92#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:12.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:12.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:12.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:12.92#ibcon#enter wrdev, iclass 32, count 0 2006.257.04:40:12.92#ibcon#first serial, iclass 32, count 0 2006.257.04:40:12.92#ibcon#enter sib2, iclass 32, count 0 2006.257.04:40:12.92#ibcon#flushed, iclass 32, count 0 2006.257.04:40:12.92#ibcon#about to write, iclass 32, count 0 2006.257.04:40:12.92#ibcon#wrote, iclass 32, count 0 2006.257.04:40:12.92#ibcon#about to read 3, iclass 32, count 0 2006.257.04:40:12.94#ibcon#read 3, iclass 32, count 0 2006.257.04:40:12.94#ibcon#about to read 4, iclass 32, count 0 2006.257.04:40:12.94#ibcon#read 4, iclass 32, count 0 2006.257.04:40:12.94#ibcon#about to read 5, iclass 32, count 0 2006.257.04:40:12.94#ibcon#read 5, iclass 32, count 0 2006.257.04:40:12.94#ibcon#about to read 6, iclass 32, count 0 2006.257.04:40:12.94#ibcon#read 6, iclass 32, count 0 2006.257.04:40:12.94#ibcon#end of sib2, iclass 32, count 0 2006.257.04:40:12.94#ibcon#*mode == 0, iclass 32, count 0 2006.257.04:40:12.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.04:40:12.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.04:40:12.94#ibcon#*before write, iclass 32, count 0 2006.257.04:40:12.94#ibcon#enter sib2, iclass 32, count 0 2006.257.04:40:12.94#ibcon#flushed, iclass 32, count 0 2006.257.04:40:12.94#ibcon#about to write, iclass 32, count 0 2006.257.04:40:12.94#ibcon#wrote, iclass 32, count 0 2006.257.04:40:12.94#ibcon#about to read 3, iclass 32, count 0 2006.257.04:40:12.98#ibcon#read 3, iclass 32, count 0 2006.257.04:40:12.98#ibcon#about to read 4, iclass 32, count 0 2006.257.04:40:12.98#ibcon#read 4, iclass 32, count 0 2006.257.04:40:12.98#ibcon#about to read 5, iclass 32, count 0 2006.257.04:40:12.98#ibcon#read 5, iclass 32, count 0 2006.257.04:40:12.98#ibcon#about to read 6, iclass 32, count 0 2006.257.04:40:12.98#ibcon#read 6, iclass 32, count 0 2006.257.04:40:12.98#ibcon#end of sib2, iclass 32, count 0 2006.257.04:40:12.98#ibcon#*after write, iclass 32, count 0 2006.257.04:40:12.98#ibcon#*before return 0, iclass 32, count 0 2006.257.04:40:12.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:12.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.04:40:12.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.04:40:12.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.04:40:12.98$vck44/vb=4,5 2006.257.04:40:12.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.04:40:12.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.04:40:12.98#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:12.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:13.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:13.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:13.04#ibcon#enter wrdev, iclass 34, count 2 2006.257.04:40:13.04#ibcon#first serial, iclass 34, count 2 2006.257.04:40:13.04#ibcon#enter sib2, iclass 34, count 2 2006.257.04:40:13.04#ibcon#flushed, iclass 34, count 2 2006.257.04:40:13.04#ibcon#about to write, iclass 34, count 2 2006.257.04:40:13.04#ibcon#wrote, iclass 34, count 2 2006.257.04:40:13.04#ibcon#about to read 3, iclass 34, count 2 2006.257.04:40:13.06#ibcon#read 3, iclass 34, count 2 2006.257.04:40:13.06#ibcon#about to read 4, iclass 34, count 2 2006.257.04:40:13.06#ibcon#read 4, iclass 34, count 2 2006.257.04:40:13.06#ibcon#about to read 5, iclass 34, count 2 2006.257.04:40:13.06#ibcon#read 5, iclass 34, count 2 2006.257.04:40:13.06#ibcon#about to read 6, iclass 34, count 2 2006.257.04:40:13.06#ibcon#read 6, iclass 34, count 2 2006.257.04:40:13.06#ibcon#end of sib2, iclass 34, count 2 2006.257.04:40:13.06#ibcon#*mode == 0, iclass 34, count 2 2006.257.04:40:13.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.04:40:13.06#ibcon#[27=AT04-05\r\n] 2006.257.04:40:13.06#ibcon#*before write, iclass 34, count 2 2006.257.04:40:13.06#ibcon#enter sib2, iclass 34, count 2 2006.257.04:40:13.06#ibcon#flushed, iclass 34, count 2 2006.257.04:40:13.06#ibcon#about to write, iclass 34, count 2 2006.257.04:40:13.06#ibcon#wrote, iclass 34, count 2 2006.257.04:40:13.06#ibcon#about to read 3, iclass 34, count 2 2006.257.04:40:13.09#ibcon#read 3, iclass 34, count 2 2006.257.04:40:13.09#ibcon#about to read 4, iclass 34, count 2 2006.257.04:40:13.09#ibcon#read 4, iclass 34, count 2 2006.257.04:40:13.09#ibcon#about to read 5, iclass 34, count 2 2006.257.04:40:13.09#ibcon#read 5, iclass 34, count 2 2006.257.04:40:13.09#ibcon#about to read 6, iclass 34, count 2 2006.257.04:40:13.09#ibcon#read 6, iclass 34, count 2 2006.257.04:40:13.09#ibcon#end of sib2, iclass 34, count 2 2006.257.04:40:13.09#ibcon#*after write, iclass 34, count 2 2006.257.04:40:13.09#ibcon#*before return 0, iclass 34, count 2 2006.257.04:40:13.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:13.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.04:40:13.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.04:40:13.09#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:13.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:13.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:13.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:13.21#ibcon#enter wrdev, iclass 34, count 0 2006.257.04:40:13.21#ibcon#first serial, iclass 34, count 0 2006.257.04:40:13.21#ibcon#enter sib2, iclass 34, count 0 2006.257.04:40:13.21#ibcon#flushed, iclass 34, count 0 2006.257.04:40:13.21#ibcon#about to write, iclass 34, count 0 2006.257.04:40:13.21#ibcon#wrote, iclass 34, count 0 2006.257.04:40:13.21#ibcon#about to read 3, iclass 34, count 0 2006.257.04:40:13.23#ibcon#read 3, iclass 34, count 0 2006.257.04:40:13.23#ibcon#about to read 4, iclass 34, count 0 2006.257.04:40:13.23#ibcon#read 4, iclass 34, count 0 2006.257.04:40:13.23#ibcon#about to read 5, iclass 34, count 0 2006.257.04:40:13.23#ibcon#read 5, iclass 34, count 0 2006.257.04:40:13.23#ibcon#about to read 6, iclass 34, count 0 2006.257.04:40:13.23#ibcon#read 6, iclass 34, count 0 2006.257.04:40:13.23#ibcon#end of sib2, iclass 34, count 0 2006.257.04:40:13.23#ibcon#*mode == 0, iclass 34, count 0 2006.257.04:40:13.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.04:40:13.23#ibcon#[27=USB\r\n] 2006.257.04:40:13.23#ibcon#*before write, iclass 34, count 0 2006.257.04:40:13.23#ibcon#enter sib2, iclass 34, count 0 2006.257.04:40:13.23#ibcon#flushed, iclass 34, count 0 2006.257.04:40:13.23#ibcon#about to write, iclass 34, count 0 2006.257.04:40:13.23#ibcon#wrote, iclass 34, count 0 2006.257.04:40:13.23#ibcon#about to read 3, iclass 34, count 0 2006.257.04:40:13.26#ibcon#read 3, iclass 34, count 0 2006.257.04:40:13.26#ibcon#about to read 4, iclass 34, count 0 2006.257.04:40:13.26#ibcon#read 4, iclass 34, count 0 2006.257.04:40:13.26#ibcon#about to read 5, iclass 34, count 0 2006.257.04:40:13.26#ibcon#read 5, iclass 34, count 0 2006.257.04:40:13.26#ibcon#about to read 6, iclass 34, count 0 2006.257.04:40:13.26#ibcon#read 6, iclass 34, count 0 2006.257.04:40:13.26#ibcon#end of sib2, iclass 34, count 0 2006.257.04:40:13.26#ibcon#*after write, iclass 34, count 0 2006.257.04:40:13.26#ibcon#*before return 0, iclass 34, count 0 2006.257.04:40:13.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:13.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.04:40:13.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.04:40:13.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.04:40:13.26$vck44/vblo=5,709.99 2006.257.04:40:13.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.04:40:13.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.04:40:13.26#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:13.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:13.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:13.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:13.26#ibcon#enter wrdev, iclass 36, count 0 2006.257.04:40:13.26#ibcon#first serial, iclass 36, count 0 2006.257.04:40:13.26#ibcon#enter sib2, iclass 36, count 0 2006.257.04:40:13.26#ibcon#flushed, iclass 36, count 0 2006.257.04:40:13.26#ibcon#about to write, iclass 36, count 0 2006.257.04:40:13.26#ibcon#wrote, iclass 36, count 0 2006.257.04:40:13.26#ibcon#about to read 3, iclass 36, count 0 2006.257.04:40:13.28#ibcon#read 3, iclass 36, count 0 2006.257.04:40:13.28#ibcon#about to read 4, iclass 36, count 0 2006.257.04:40:13.28#ibcon#read 4, iclass 36, count 0 2006.257.04:40:13.28#ibcon#about to read 5, iclass 36, count 0 2006.257.04:40:13.28#ibcon#read 5, iclass 36, count 0 2006.257.04:40:13.28#ibcon#about to read 6, iclass 36, count 0 2006.257.04:40:13.28#ibcon#read 6, iclass 36, count 0 2006.257.04:40:13.28#ibcon#end of sib2, iclass 36, count 0 2006.257.04:40:13.28#ibcon#*mode == 0, iclass 36, count 0 2006.257.04:40:13.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.04:40:13.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.04:40:13.28#ibcon#*before write, iclass 36, count 0 2006.257.04:40:13.28#ibcon#enter sib2, iclass 36, count 0 2006.257.04:40:13.28#ibcon#flushed, iclass 36, count 0 2006.257.04:40:13.28#ibcon#about to write, iclass 36, count 0 2006.257.04:40:13.28#ibcon#wrote, iclass 36, count 0 2006.257.04:40:13.28#ibcon#about to read 3, iclass 36, count 0 2006.257.04:40:13.32#ibcon#read 3, iclass 36, count 0 2006.257.04:40:13.32#ibcon#about to read 4, iclass 36, count 0 2006.257.04:40:13.32#ibcon#read 4, iclass 36, count 0 2006.257.04:40:13.32#ibcon#about to read 5, iclass 36, count 0 2006.257.04:40:13.32#ibcon#read 5, iclass 36, count 0 2006.257.04:40:13.32#ibcon#about to read 6, iclass 36, count 0 2006.257.04:40:13.32#ibcon#read 6, iclass 36, count 0 2006.257.04:40:13.32#ibcon#end of sib2, iclass 36, count 0 2006.257.04:40:13.32#ibcon#*after write, iclass 36, count 0 2006.257.04:40:13.32#ibcon#*before return 0, iclass 36, count 0 2006.257.04:40:13.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:13.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.04:40:13.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.04:40:13.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.04:40:13.32$vck44/vb=5,4 2006.257.04:40:13.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.04:40:13.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.04:40:13.32#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:13.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:13.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:13.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:13.38#ibcon#enter wrdev, iclass 38, count 2 2006.257.04:40:13.38#ibcon#first serial, iclass 38, count 2 2006.257.04:40:13.38#ibcon#enter sib2, iclass 38, count 2 2006.257.04:40:13.38#ibcon#flushed, iclass 38, count 2 2006.257.04:40:13.38#ibcon#about to write, iclass 38, count 2 2006.257.04:40:13.38#ibcon#wrote, iclass 38, count 2 2006.257.04:40:13.38#ibcon#about to read 3, iclass 38, count 2 2006.257.04:40:13.40#ibcon#read 3, iclass 38, count 2 2006.257.04:40:13.40#ibcon#about to read 4, iclass 38, count 2 2006.257.04:40:13.40#ibcon#read 4, iclass 38, count 2 2006.257.04:40:13.40#ibcon#about to read 5, iclass 38, count 2 2006.257.04:40:13.40#ibcon#read 5, iclass 38, count 2 2006.257.04:40:13.40#ibcon#about to read 6, iclass 38, count 2 2006.257.04:40:13.40#ibcon#read 6, iclass 38, count 2 2006.257.04:40:13.40#ibcon#end of sib2, iclass 38, count 2 2006.257.04:40:13.40#ibcon#*mode == 0, iclass 38, count 2 2006.257.04:40:13.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.04:40:13.40#ibcon#[27=AT05-04\r\n] 2006.257.04:40:13.40#ibcon#*before write, iclass 38, count 2 2006.257.04:40:13.40#ibcon#enter sib2, iclass 38, count 2 2006.257.04:40:13.40#ibcon#flushed, iclass 38, count 2 2006.257.04:40:13.40#ibcon#about to write, iclass 38, count 2 2006.257.04:40:13.40#ibcon#wrote, iclass 38, count 2 2006.257.04:40:13.40#ibcon#about to read 3, iclass 38, count 2 2006.257.04:40:13.43#ibcon#read 3, iclass 38, count 2 2006.257.04:40:13.43#ibcon#about to read 4, iclass 38, count 2 2006.257.04:40:13.43#ibcon#read 4, iclass 38, count 2 2006.257.04:40:13.43#ibcon#about to read 5, iclass 38, count 2 2006.257.04:40:13.43#ibcon#read 5, iclass 38, count 2 2006.257.04:40:13.43#ibcon#about to read 6, iclass 38, count 2 2006.257.04:40:13.43#ibcon#read 6, iclass 38, count 2 2006.257.04:40:13.43#ibcon#end of sib2, iclass 38, count 2 2006.257.04:40:13.43#ibcon#*after write, iclass 38, count 2 2006.257.04:40:13.43#ibcon#*before return 0, iclass 38, count 2 2006.257.04:40:13.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:13.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.04:40:13.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.04:40:13.43#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:13.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:13.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:13.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:13.55#ibcon#enter wrdev, iclass 38, count 0 2006.257.04:40:13.55#ibcon#first serial, iclass 38, count 0 2006.257.04:40:13.55#ibcon#enter sib2, iclass 38, count 0 2006.257.04:40:13.55#ibcon#flushed, iclass 38, count 0 2006.257.04:40:13.55#ibcon#about to write, iclass 38, count 0 2006.257.04:40:13.55#ibcon#wrote, iclass 38, count 0 2006.257.04:40:13.55#ibcon#about to read 3, iclass 38, count 0 2006.257.04:40:13.57#ibcon#read 3, iclass 38, count 0 2006.257.04:40:13.57#ibcon#about to read 4, iclass 38, count 0 2006.257.04:40:13.57#ibcon#read 4, iclass 38, count 0 2006.257.04:40:13.57#ibcon#about to read 5, iclass 38, count 0 2006.257.04:40:13.57#ibcon#read 5, iclass 38, count 0 2006.257.04:40:13.57#ibcon#about to read 6, iclass 38, count 0 2006.257.04:40:13.57#ibcon#read 6, iclass 38, count 0 2006.257.04:40:13.57#ibcon#end of sib2, iclass 38, count 0 2006.257.04:40:13.57#ibcon#*mode == 0, iclass 38, count 0 2006.257.04:40:13.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.04:40:13.57#ibcon#[27=USB\r\n] 2006.257.04:40:13.57#ibcon#*before write, iclass 38, count 0 2006.257.04:40:13.57#ibcon#enter sib2, iclass 38, count 0 2006.257.04:40:13.57#ibcon#flushed, iclass 38, count 0 2006.257.04:40:13.57#ibcon#about to write, iclass 38, count 0 2006.257.04:40:13.57#ibcon#wrote, iclass 38, count 0 2006.257.04:40:13.57#ibcon#about to read 3, iclass 38, count 0 2006.257.04:40:13.60#ibcon#read 3, iclass 38, count 0 2006.257.04:40:13.60#ibcon#about to read 4, iclass 38, count 0 2006.257.04:40:13.60#ibcon#read 4, iclass 38, count 0 2006.257.04:40:13.60#ibcon#about to read 5, iclass 38, count 0 2006.257.04:40:13.60#ibcon#read 5, iclass 38, count 0 2006.257.04:40:13.60#ibcon#about to read 6, iclass 38, count 0 2006.257.04:40:13.60#ibcon#read 6, iclass 38, count 0 2006.257.04:40:13.60#ibcon#end of sib2, iclass 38, count 0 2006.257.04:40:13.60#ibcon#*after write, iclass 38, count 0 2006.257.04:40:13.60#ibcon#*before return 0, iclass 38, count 0 2006.257.04:40:13.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:13.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.04:40:13.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.04:40:13.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.04:40:13.60$vck44/vblo=6,719.99 2006.257.04:40:13.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.04:40:13.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.04:40:13.60#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:13.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:13.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:13.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:13.60#ibcon#enter wrdev, iclass 40, count 0 2006.257.04:40:13.60#ibcon#first serial, iclass 40, count 0 2006.257.04:40:13.60#ibcon#enter sib2, iclass 40, count 0 2006.257.04:40:13.60#ibcon#flushed, iclass 40, count 0 2006.257.04:40:13.60#ibcon#about to write, iclass 40, count 0 2006.257.04:40:13.60#ibcon#wrote, iclass 40, count 0 2006.257.04:40:13.60#ibcon#about to read 3, iclass 40, count 0 2006.257.04:40:13.62#ibcon#read 3, iclass 40, count 0 2006.257.04:40:13.62#ibcon#about to read 4, iclass 40, count 0 2006.257.04:40:13.62#ibcon#read 4, iclass 40, count 0 2006.257.04:40:13.62#ibcon#about to read 5, iclass 40, count 0 2006.257.04:40:13.62#ibcon#read 5, iclass 40, count 0 2006.257.04:40:13.62#ibcon#about to read 6, iclass 40, count 0 2006.257.04:40:13.62#ibcon#read 6, iclass 40, count 0 2006.257.04:40:13.62#ibcon#end of sib2, iclass 40, count 0 2006.257.04:40:13.62#ibcon#*mode == 0, iclass 40, count 0 2006.257.04:40:13.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.04:40:13.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.04:40:13.62#ibcon#*before write, iclass 40, count 0 2006.257.04:40:13.62#ibcon#enter sib2, iclass 40, count 0 2006.257.04:40:13.62#ibcon#flushed, iclass 40, count 0 2006.257.04:40:13.62#ibcon#about to write, iclass 40, count 0 2006.257.04:40:13.62#ibcon#wrote, iclass 40, count 0 2006.257.04:40:13.62#ibcon#about to read 3, iclass 40, count 0 2006.257.04:40:13.66#ibcon#read 3, iclass 40, count 0 2006.257.04:40:13.66#ibcon#about to read 4, iclass 40, count 0 2006.257.04:40:13.66#ibcon#read 4, iclass 40, count 0 2006.257.04:40:13.66#ibcon#about to read 5, iclass 40, count 0 2006.257.04:40:13.66#ibcon#read 5, iclass 40, count 0 2006.257.04:40:13.66#ibcon#about to read 6, iclass 40, count 0 2006.257.04:40:13.66#ibcon#read 6, iclass 40, count 0 2006.257.04:40:13.66#ibcon#end of sib2, iclass 40, count 0 2006.257.04:40:13.66#ibcon#*after write, iclass 40, count 0 2006.257.04:40:13.66#ibcon#*before return 0, iclass 40, count 0 2006.257.04:40:13.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:13.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.04:40:13.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.04:40:13.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.04:40:13.66$vck44/vb=6,4 2006.257.04:40:13.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.04:40:13.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.04:40:13.66#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:13.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:13.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:13.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:13.72#ibcon#enter wrdev, iclass 4, count 2 2006.257.04:40:13.72#ibcon#first serial, iclass 4, count 2 2006.257.04:40:13.72#ibcon#enter sib2, iclass 4, count 2 2006.257.04:40:13.72#ibcon#flushed, iclass 4, count 2 2006.257.04:40:13.72#ibcon#about to write, iclass 4, count 2 2006.257.04:40:13.72#ibcon#wrote, iclass 4, count 2 2006.257.04:40:13.72#ibcon#about to read 3, iclass 4, count 2 2006.257.04:40:13.74#ibcon#read 3, iclass 4, count 2 2006.257.04:40:13.74#ibcon#about to read 4, iclass 4, count 2 2006.257.04:40:13.74#ibcon#read 4, iclass 4, count 2 2006.257.04:40:13.74#ibcon#about to read 5, iclass 4, count 2 2006.257.04:40:13.74#ibcon#read 5, iclass 4, count 2 2006.257.04:40:13.74#ibcon#about to read 6, iclass 4, count 2 2006.257.04:40:13.74#ibcon#read 6, iclass 4, count 2 2006.257.04:40:13.74#ibcon#end of sib2, iclass 4, count 2 2006.257.04:40:13.74#ibcon#*mode == 0, iclass 4, count 2 2006.257.04:40:13.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.04:40:13.74#ibcon#[27=AT06-04\r\n] 2006.257.04:40:13.74#ibcon#*before write, iclass 4, count 2 2006.257.04:40:13.74#ibcon#enter sib2, iclass 4, count 2 2006.257.04:40:13.74#ibcon#flushed, iclass 4, count 2 2006.257.04:40:13.74#ibcon#about to write, iclass 4, count 2 2006.257.04:40:13.74#ibcon#wrote, iclass 4, count 2 2006.257.04:40:13.74#ibcon#about to read 3, iclass 4, count 2 2006.257.04:40:13.77#ibcon#read 3, iclass 4, count 2 2006.257.04:40:13.77#ibcon#about to read 4, iclass 4, count 2 2006.257.04:40:13.77#ibcon#read 4, iclass 4, count 2 2006.257.04:40:13.77#ibcon#about to read 5, iclass 4, count 2 2006.257.04:40:13.77#ibcon#read 5, iclass 4, count 2 2006.257.04:40:13.77#ibcon#about to read 6, iclass 4, count 2 2006.257.04:40:13.77#ibcon#read 6, iclass 4, count 2 2006.257.04:40:13.77#ibcon#end of sib2, iclass 4, count 2 2006.257.04:40:13.77#ibcon#*after write, iclass 4, count 2 2006.257.04:40:13.77#ibcon#*before return 0, iclass 4, count 2 2006.257.04:40:13.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:13.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.04:40:13.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.04:40:13.77#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:13.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:13.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:13.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:13.89#ibcon#enter wrdev, iclass 4, count 0 2006.257.04:40:13.89#ibcon#first serial, iclass 4, count 0 2006.257.04:40:13.89#ibcon#enter sib2, iclass 4, count 0 2006.257.04:40:13.89#ibcon#flushed, iclass 4, count 0 2006.257.04:40:13.89#ibcon#about to write, iclass 4, count 0 2006.257.04:40:13.89#ibcon#wrote, iclass 4, count 0 2006.257.04:40:13.89#ibcon#about to read 3, iclass 4, count 0 2006.257.04:40:13.91#ibcon#read 3, iclass 4, count 0 2006.257.04:40:13.91#ibcon#about to read 4, iclass 4, count 0 2006.257.04:40:13.91#ibcon#read 4, iclass 4, count 0 2006.257.04:40:13.91#ibcon#about to read 5, iclass 4, count 0 2006.257.04:40:13.91#ibcon#read 5, iclass 4, count 0 2006.257.04:40:13.91#ibcon#about to read 6, iclass 4, count 0 2006.257.04:40:13.91#ibcon#read 6, iclass 4, count 0 2006.257.04:40:13.91#ibcon#end of sib2, iclass 4, count 0 2006.257.04:40:13.91#ibcon#*mode == 0, iclass 4, count 0 2006.257.04:40:13.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.04:40:13.91#ibcon#[27=USB\r\n] 2006.257.04:40:13.91#ibcon#*before write, iclass 4, count 0 2006.257.04:40:13.91#ibcon#enter sib2, iclass 4, count 0 2006.257.04:40:13.91#ibcon#flushed, iclass 4, count 0 2006.257.04:40:13.91#ibcon#about to write, iclass 4, count 0 2006.257.04:40:13.91#ibcon#wrote, iclass 4, count 0 2006.257.04:40:13.91#ibcon#about to read 3, iclass 4, count 0 2006.257.04:40:13.94#ibcon#read 3, iclass 4, count 0 2006.257.04:40:13.94#ibcon#about to read 4, iclass 4, count 0 2006.257.04:40:13.94#ibcon#read 4, iclass 4, count 0 2006.257.04:40:13.94#ibcon#about to read 5, iclass 4, count 0 2006.257.04:40:13.94#ibcon#read 5, iclass 4, count 0 2006.257.04:40:13.94#ibcon#about to read 6, iclass 4, count 0 2006.257.04:40:13.94#ibcon#read 6, iclass 4, count 0 2006.257.04:40:13.94#ibcon#end of sib2, iclass 4, count 0 2006.257.04:40:13.94#ibcon#*after write, iclass 4, count 0 2006.257.04:40:13.94#ibcon#*before return 0, iclass 4, count 0 2006.257.04:40:13.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:13.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.04:40:13.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.04:40:13.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.04:40:13.94$vck44/vblo=7,734.99 2006.257.04:40:13.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.04:40:13.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.04:40:13.94#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:13.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:13.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:13.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:13.94#ibcon#enter wrdev, iclass 6, count 0 2006.257.04:40:13.94#ibcon#first serial, iclass 6, count 0 2006.257.04:40:13.94#ibcon#enter sib2, iclass 6, count 0 2006.257.04:40:13.94#ibcon#flushed, iclass 6, count 0 2006.257.04:40:13.94#ibcon#about to write, iclass 6, count 0 2006.257.04:40:13.94#ibcon#wrote, iclass 6, count 0 2006.257.04:40:13.94#ibcon#about to read 3, iclass 6, count 0 2006.257.04:40:13.96#ibcon#read 3, iclass 6, count 0 2006.257.04:40:13.96#ibcon#about to read 4, iclass 6, count 0 2006.257.04:40:13.96#ibcon#read 4, iclass 6, count 0 2006.257.04:40:13.96#ibcon#about to read 5, iclass 6, count 0 2006.257.04:40:13.96#ibcon#read 5, iclass 6, count 0 2006.257.04:40:13.96#ibcon#about to read 6, iclass 6, count 0 2006.257.04:40:13.96#ibcon#read 6, iclass 6, count 0 2006.257.04:40:13.96#ibcon#end of sib2, iclass 6, count 0 2006.257.04:40:13.96#ibcon#*mode == 0, iclass 6, count 0 2006.257.04:40:13.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.04:40:13.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.04:40:13.96#ibcon#*before write, iclass 6, count 0 2006.257.04:40:13.96#ibcon#enter sib2, iclass 6, count 0 2006.257.04:40:13.96#ibcon#flushed, iclass 6, count 0 2006.257.04:40:13.96#ibcon#about to write, iclass 6, count 0 2006.257.04:40:13.96#ibcon#wrote, iclass 6, count 0 2006.257.04:40:13.96#ibcon#about to read 3, iclass 6, count 0 2006.257.04:40:14.00#ibcon#read 3, iclass 6, count 0 2006.257.04:40:14.00#ibcon#about to read 4, iclass 6, count 0 2006.257.04:40:14.00#ibcon#read 4, iclass 6, count 0 2006.257.04:40:14.00#ibcon#about to read 5, iclass 6, count 0 2006.257.04:40:14.00#ibcon#read 5, iclass 6, count 0 2006.257.04:40:14.00#ibcon#about to read 6, iclass 6, count 0 2006.257.04:40:14.00#ibcon#read 6, iclass 6, count 0 2006.257.04:40:14.00#ibcon#end of sib2, iclass 6, count 0 2006.257.04:40:14.00#ibcon#*after write, iclass 6, count 0 2006.257.04:40:14.00#ibcon#*before return 0, iclass 6, count 0 2006.257.04:40:14.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:14.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.04:40:14.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.04:40:14.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.04:40:14.00$vck44/vb=7,4 2006.257.04:40:14.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.04:40:14.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.04:40:14.00#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:14.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:14.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:14.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:14.06#ibcon#enter wrdev, iclass 10, count 2 2006.257.04:40:14.06#ibcon#first serial, iclass 10, count 2 2006.257.04:40:14.06#ibcon#enter sib2, iclass 10, count 2 2006.257.04:40:14.06#ibcon#flushed, iclass 10, count 2 2006.257.04:40:14.06#ibcon#about to write, iclass 10, count 2 2006.257.04:40:14.06#ibcon#wrote, iclass 10, count 2 2006.257.04:40:14.06#ibcon#about to read 3, iclass 10, count 2 2006.257.04:40:14.08#ibcon#read 3, iclass 10, count 2 2006.257.04:40:14.08#ibcon#about to read 4, iclass 10, count 2 2006.257.04:40:14.08#ibcon#read 4, iclass 10, count 2 2006.257.04:40:14.08#ibcon#about to read 5, iclass 10, count 2 2006.257.04:40:14.08#ibcon#read 5, iclass 10, count 2 2006.257.04:40:14.08#ibcon#about to read 6, iclass 10, count 2 2006.257.04:40:14.08#ibcon#read 6, iclass 10, count 2 2006.257.04:40:14.08#ibcon#end of sib2, iclass 10, count 2 2006.257.04:40:14.08#ibcon#*mode == 0, iclass 10, count 2 2006.257.04:40:14.08#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.04:40:14.08#ibcon#[27=AT07-04\r\n] 2006.257.04:40:14.08#ibcon#*before write, iclass 10, count 2 2006.257.04:40:14.08#ibcon#enter sib2, iclass 10, count 2 2006.257.04:40:14.08#ibcon#flushed, iclass 10, count 2 2006.257.04:40:14.08#ibcon#about to write, iclass 10, count 2 2006.257.04:40:14.08#ibcon#wrote, iclass 10, count 2 2006.257.04:40:14.08#ibcon#about to read 3, iclass 10, count 2 2006.257.04:40:14.11#ibcon#read 3, iclass 10, count 2 2006.257.04:40:14.11#ibcon#about to read 4, iclass 10, count 2 2006.257.04:40:14.11#ibcon#read 4, iclass 10, count 2 2006.257.04:40:14.11#ibcon#about to read 5, iclass 10, count 2 2006.257.04:40:14.11#ibcon#read 5, iclass 10, count 2 2006.257.04:40:14.11#ibcon#about to read 6, iclass 10, count 2 2006.257.04:40:14.11#ibcon#read 6, iclass 10, count 2 2006.257.04:40:14.11#ibcon#end of sib2, iclass 10, count 2 2006.257.04:40:14.11#ibcon#*after write, iclass 10, count 2 2006.257.04:40:14.11#ibcon#*before return 0, iclass 10, count 2 2006.257.04:40:14.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:14.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.04:40:14.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.04:40:14.11#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:14.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:14.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:14.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:14.23#ibcon#enter wrdev, iclass 10, count 0 2006.257.04:40:14.23#ibcon#first serial, iclass 10, count 0 2006.257.04:40:14.23#ibcon#enter sib2, iclass 10, count 0 2006.257.04:40:14.23#ibcon#flushed, iclass 10, count 0 2006.257.04:40:14.23#ibcon#about to write, iclass 10, count 0 2006.257.04:40:14.23#ibcon#wrote, iclass 10, count 0 2006.257.04:40:14.23#ibcon#about to read 3, iclass 10, count 0 2006.257.04:40:14.25#ibcon#read 3, iclass 10, count 0 2006.257.04:40:14.25#ibcon#about to read 4, iclass 10, count 0 2006.257.04:40:14.25#ibcon#read 4, iclass 10, count 0 2006.257.04:40:14.25#ibcon#about to read 5, iclass 10, count 0 2006.257.04:40:14.25#ibcon#read 5, iclass 10, count 0 2006.257.04:40:14.25#ibcon#about to read 6, iclass 10, count 0 2006.257.04:40:14.25#ibcon#read 6, iclass 10, count 0 2006.257.04:40:14.25#ibcon#end of sib2, iclass 10, count 0 2006.257.04:40:14.25#ibcon#*mode == 0, iclass 10, count 0 2006.257.04:40:14.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.04:40:14.25#ibcon#[27=USB\r\n] 2006.257.04:40:14.25#ibcon#*before write, iclass 10, count 0 2006.257.04:40:14.25#ibcon#enter sib2, iclass 10, count 0 2006.257.04:40:14.25#ibcon#flushed, iclass 10, count 0 2006.257.04:40:14.25#ibcon#about to write, iclass 10, count 0 2006.257.04:40:14.25#ibcon#wrote, iclass 10, count 0 2006.257.04:40:14.25#ibcon#about to read 3, iclass 10, count 0 2006.257.04:40:14.28#ibcon#read 3, iclass 10, count 0 2006.257.04:40:14.28#ibcon#about to read 4, iclass 10, count 0 2006.257.04:40:14.28#ibcon#read 4, iclass 10, count 0 2006.257.04:40:14.28#ibcon#about to read 5, iclass 10, count 0 2006.257.04:40:14.28#ibcon#read 5, iclass 10, count 0 2006.257.04:40:14.28#ibcon#about to read 6, iclass 10, count 0 2006.257.04:40:14.28#ibcon#read 6, iclass 10, count 0 2006.257.04:40:14.28#ibcon#end of sib2, iclass 10, count 0 2006.257.04:40:14.28#ibcon#*after write, iclass 10, count 0 2006.257.04:40:14.28#ibcon#*before return 0, iclass 10, count 0 2006.257.04:40:14.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:14.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.04:40:14.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.04:40:14.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.04:40:14.28$vck44/vblo=8,744.99 2006.257.04:40:14.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.04:40:14.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.04:40:14.28#ibcon#ireg 17 cls_cnt 0 2006.257.04:40:14.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:14.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:14.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:14.28#ibcon#enter wrdev, iclass 12, count 0 2006.257.04:40:14.28#ibcon#first serial, iclass 12, count 0 2006.257.04:40:14.28#ibcon#enter sib2, iclass 12, count 0 2006.257.04:40:14.28#ibcon#flushed, iclass 12, count 0 2006.257.04:40:14.28#ibcon#about to write, iclass 12, count 0 2006.257.04:40:14.28#ibcon#wrote, iclass 12, count 0 2006.257.04:40:14.28#ibcon#about to read 3, iclass 12, count 0 2006.257.04:40:14.30#ibcon#read 3, iclass 12, count 0 2006.257.04:40:14.30#ibcon#about to read 4, iclass 12, count 0 2006.257.04:40:14.30#ibcon#read 4, iclass 12, count 0 2006.257.04:40:14.30#ibcon#about to read 5, iclass 12, count 0 2006.257.04:40:14.30#ibcon#read 5, iclass 12, count 0 2006.257.04:40:14.30#ibcon#about to read 6, iclass 12, count 0 2006.257.04:40:14.30#ibcon#read 6, iclass 12, count 0 2006.257.04:40:14.30#ibcon#end of sib2, iclass 12, count 0 2006.257.04:40:14.30#ibcon#*mode == 0, iclass 12, count 0 2006.257.04:40:14.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.04:40:14.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.04:40:14.30#ibcon#*before write, iclass 12, count 0 2006.257.04:40:14.30#ibcon#enter sib2, iclass 12, count 0 2006.257.04:40:14.30#ibcon#flushed, iclass 12, count 0 2006.257.04:40:14.30#ibcon#about to write, iclass 12, count 0 2006.257.04:40:14.30#ibcon#wrote, iclass 12, count 0 2006.257.04:40:14.30#ibcon#about to read 3, iclass 12, count 0 2006.257.04:40:14.34#ibcon#read 3, iclass 12, count 0 2006.257.04:40:14.34#ibcon#about to read 4, iclass 12, count 0 2006.257.04:40:14.34#ibcon#read 4, iclass 12, count 0 2006.257.04:40:14.34#ibcon#about to read 5, iclass 12, count 0 2006.257.04:40:14.34#ibcon#read 5, iclass 12, count 0 2006.257.04:40:14.34#ibcon#about to read 6, iclass 12, count 0 2006.257.04:40:14.34#ibcon#read 6, iclass 12, count 0 2006.257.04:40:14.34#ibcon#end of sib2, iclass 12, count 0 2006.257.04:40:14.34#ibcon#*after write, iclass 12, count 0 2006.257.04:40:14.34#ibcon#*before return 0, iclass 12, count 0 2006.257.04:40:14.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:14.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:40:14.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.04:40:14.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.04:40:14.34$vck44/vb=8,4 2006.257.04:40:14.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.04:40:14.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.04:40:14.34#ibcon#ireg 11 cls_cnt 2 2006.257.04:40:14.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:14.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:14.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:14.40#ibcon#enter wrdev, iclass 14, count 2 2006.257.04:40:14.40#ibcon#first serial, iclass 14, count 2 2006.257.04:40:14.40#ibcon#enter sib2, iclass 14, count 2 2006.257.04:40:14.40#ibcon#flushed, iclass 14, count 2 2006.257.04:40:14.40#ibcon#about to write, iclass 14, count 2 2006.257.04:40:14.40#ibcon#wrote, iclass 14, count 2 2006.257.04:40:14.40#ibcon#about to read 3, iclass 14, count 2 2006.257.04:40:14.42#ibcon#read 3, iclass 14, count 2 2006.257.04:40:14.42#ibcon#about to read 4, iclass 14, count 2 2006.257.04:40:14.42#ibcon#read 4, iclass 14, count 2 2006.257.04:40:14.42#ibcon#about to read 5, iclass 14, count 2 2006.257.04:40:14.42#ibcon#read 5, iclass 14, count 2 2006.257.04:40:14.42#ibcon#about to read 6, iclass 14, count 2 2006.257.04:40:14.42#ibcon#read 6, iclass 14, count 2 2006.257.04:40:14.42#ibcon#end of sib2, iclass 14, count 2 2006.257.04:40:14.42#ibcon#*mode == 0, iclass 14, count 2 2006.257.04:40:14.42#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.04:40:14.42#ibcon#[27=AT08-04\r\n] 2006.257.04:40:14.42#ibcon#*before write, iclass 14, count 2 2006.257.04:40:14.42#ibcon#enter sib2, iclass 14, count 2 2006.257.04:40:14.42#ibcon#flushed, iclass 14, count 2 2006.257.04:40:14.42#ibcon#about to write, iclass 14, count 2 2006.257.04:40:14.42#ibcon#wrote, iclass 14, count 2 2006.257.04:40:14.42#ibcon#about to read 3, iclass 14, count 2 2006.257.04:40:14.45#ibcon#read 3, iclass 14, count 2 2006.257.04:40:14.45#ibcon#about to read 4, iclass 14, count 2 2006.257.04:40:14.45#ibcon#read 4, iclass 14, count 2 2006.257.04:40:14.45#ibcon#about to read 5, iclass 14, count 2 2006.257.04:40:14.45#ibcon#read 5, iclass 14, count 2 2006.257.04:40:14.45#ibcon#about to read 6, iclass 14, count 2 2006.257.04:40:14.45#ibcon#read 6, iclass 14, count 2 2006.257.04:40:14.45#ibcon#end of sib2, iclass 14, count 2 2006.257.04:40:14.45#ibcon#*after write, iclass 14, count 2 2006.257.04:40:14.45#ibcon#*before return 0, iclass 14, count 2 2006.257.04:40:14.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:14.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.04:40:14.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.04:40:14.45#ibcon#ireg 7 cls_cnt 0 2006.257.04:40:14.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:14.53#abcon#<5=/14 1.7 4.8 19.62 931011.9\r\n> 2006.257.04:40:14.55#abcon#{5=INTERFACE CLEAR} 2006.257.04:40:14.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:14.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:14.57#ibcon#enter wrdev, iclass 14, count 0 2006.257.04:40:14.57#ibcon#first serial, iclass 14, count 0 2006.257.04:40:14.57#ibcon#enter sib2, iclass 14, count 0 2006.257.04:40:14.57#ibcon#flushed, iclass 14, count 0 2006.257.04:40:14.57#ibcon#about to write, iclass 14, count 0 2006.257.04:40:14.57#ibcon#wrote, iclass 14, count 0 2006.257.04:40:14.57#ibcon#about to read 3, iclass 14, count 0 2006.257.04:40:14.59#ibcon#read 3, iclass 14, count 0 2006.257.04:40:14.59#ibcon#about to read 4, iclass 14, count 0 2006.257.04:40:14.59#ibcon#read 4, iclass 14, count 0 2006.257.04:40:14.59#ibcon#about to read 5, iclass 14, count 0 2006.257.04:40:14.59#ibcon#read 5, iclass 14, count 0 2006.257.04:40:14.59#ibcon#about to read 6, iclass 14, count 0 2006.257.04:40:14.59#ibcon#read 6, iclass 14, count 0 2006.257.04:40:14.59#ibcon#end of sib2, iclass 14, count 0 2006.257.04:40:14.59#ibcon#*mode == 0, iclass 14, count 0 2006.257.04:40:14.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.04:40:14.59#ibcon#[27=USB\r\n] 2006.257.04:40:14.59#ibcon#*before write, iclass 14, count 0 2006.257.04:40:14.59#ibcon#enter sib2, iclass 14, count 0 2006.257.04:40:14.59#ibcon#flushed, iclass 14, count 0 2006.257.04:40:14.59#ibcon#about to write, iclass 14, count 0 2006.257.04:40:14.59#ibcon#wrote, iclass 14, count 0 2006.257.04:40:14.59#ibcon#about to read 3, iclass 14, count 0 2006.257.04:40:14.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:40:14.62#ibcon#read 3, iclass 14, count 0 2006.257.04:40:14.62#ibcon#about to read 4, iclass 14, count 0 2006.257.04:40:14.62#ibcon#read 4, iclass 14, count 0 2006.257.04:40:14.62#ibcon#about to read 5, iclass 14, count 0 2006.257.04:40:14.62#ibcon#read 5, iclass 14, count 0 2006.257.04:40:14.62#ibcon#about to read 6, iclass 14, count 0 2006.257.04:40:14.62#ibcon#read 6, iclass 14, count 0 2006.257.04:40:14.62#ibcon#end of sib2, iclass 14, count 0 2006.257.04:40:14.62#ibcon#*after write, iclass 14, count 0 2006.257.04:40:14.62#ibcon#*before return 0, iclass 14, count 0 2006.257.04:40:14.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:14.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.04:40:14.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.04:40:14.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.04:40:14.62$vck44/vabw=wide 2006.257.04:40:14.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.04:40:14.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.04:40:14.62#ibcon#ireg 8 cls_cnt 0 2006.257.04:40:14.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:14.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:14.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:14.62#ibcon#enter wrdev, iclass 20, count 0 2006.257.04:40:14.62#ibcon#first serial, iclass 20, count 0 2006.257.04:40:14.62#ibcon#enter sib2, iclass 20, count 0 2006.257.04:40:14.62#ibcon#flushed, iclass 20, count 0 2006.257.04:40:14.62#ibcon#about to write, iclass 20, count 0 2006.257.04:40:14.62#ibcon#wrote, iclass 20, count 0 2006.257.04:40:14.62#ibcon#about to read 3, iclass 20, count 0 2006.257.04:40:14.64#ibcon#read 3, iclass 20, count 0 2006.257.04:40:14.64#ibcon#about to read 4, iclass 20, count 0 2006.257.04:40:14.64#ibcon#read 4, iclass 20, count 0 2006.257.04:40:14.64#ibcon#about to read 5, iclass 20, count 0 2006.257.04:40:14.64#ibcon#read 5, iclass 20, count 0 2006.257.04:40:14.64#ibcon#about to read 6, iclass 20, count 0 2006.257.04:40:14.64#ibcon#read 6, iclass 20, count 0 2006.257.04:40:14.64#ibcon#end of sib2, iclass 20, count 0 2006.257.04:40:14.64#ibcon#*mode == 0, iclass 20, count 0 2006.257.04:40:14.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.04:40:14.64#ibcon#[25=BW32\r\n] 2006.257.04:40:14.64#ibcon#*before write, iclass 20, count 0 2006.257.04:40:14.64#ibcon#enter sib2, iclass 20, count 0 2006.257.04:40:14.64#ibcon#flushed, iclass 20, count 0 2006.257.04:40:14.64#ibcon#about to write, iclass 20, count 0 2006.257.04:40:14.64#ibcon#wrote, iclass 20, count 0 2006.257.04:40:14.64#ibcon#about to read 3, iclass 20, count 0 2006.257.04:40:14.67#ibcon#read 3, iclass 20, count 0 2006.257.04:40:14.67#ibcon#about to read 4, iclass 20, count 0 2006.257.04:40:14.67#ibcon#read 4, iclass 20, count 0 2006.257.04:40:14.67#ibcon#about to read 5, iclass 20, count 0 2006.257.04:40:14.67#ibcon#read 5, iclass 20, count 0 2006.257.04:40:14.67#ibcon#about to read 6, iclass 20, count 0 2006.257.04:40:14.67#ibcon#read 6, iclass 20, count 0 2006.257.04:40:14.67#ibcon#end of sib2, iclass 20, count 0 2006.257.04:40:14.67#ibcon#*after write, iclass 20, count 0 2006.257.04:40:14.67#ibcon#*before return 0, iclass 20, count 0 2006.257.04:40:14.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:14.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.04:40:14.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.04:40:14.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.04:40:14.67$vck44/vbbw=wide 2006.257.04:40:14.67#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.04:40:14.67#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.04:40:14.67#ibcon#ireg 8 cls_cnt 0 2006.257.04:40:14.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:40:14.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:40:14.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:40:14.74#ibcon#enter wrdev, iclass 22, count 0 2006.257.04:40:14.74#ibcon#first serial, iclass 22, count 0 2006.257.04:40:14.74#ibcon#enter sib2, iclass 22, count 0 2006.257.04:40:14.74#ibcon#flushed, iclass 22, count 0 2006.257.04:40:14.74#ibcon#about to write, iclass 22, count 0 2006.257.04:40:14.74#ibcon#wrote, iclass 22, count 0 2006.257.04:40:14.74#ibcon#about to read 3, iclass 22, count 0 2006.257.04:40:14.76#ibcon#read 3, iclass 22, count 0 2006.257.04:40:14.76#ibcon#about to read 4, iclass 22, count 0 2006.257.04:40:14.76#ibcon#read 4, iclass 22, count 0 2006.257.04:40:14.76#ibcon#about to read 5, iclass 22, count 0 2006.257.04:40:14.76#ibcon#read 5, iclass 22, count 0 2006.257.04:40:14.76#ibcon#about to read 6, iclass 22, count 0 2006.257.04:40:14.76#ibcon#read 6, iclass 22, count 0 2006.257.04:40:14.76#ibcon#end of sib2, iclass 22, count 0 2006.257.04:40:14.76#ibcon#*mode == 0, iclass 22, count 0 2006.257.04:40:14.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.04:40:14.76#ibcon#[27=BW32\r\n] 2006.257.04:40:14.76#ibcon#*before write, iclass 22, count 0 2006.257.04:40:14.76#ibcon#enter sib2, iclass 22, count 0 2006.257.04:40:14.76#ibcon#flushed, iclass 22, count 0 2006.257.04:40:14.76#ibcon#about to write, iclass 22, count 0 2006.257.04:40:14.76#ibcon#wrote, iclass 22, count 0 2006.257.04:40:14.76#ibcon#about to read 3, iclass 22, count 0 2006.257.04:40:14.79#ibcon#read 3, iclass 22, count 0 2006.257.04:40:14.79#ibcon#about to read 4, iclass 22, count 0 2006.257.04:40:14.79#ibcon#read 4, iclass 22, count 0 2006.257.04:40:14.79#ibcon#about to read 5, iclass 22, count 0 2006.257.04:40:14.79#ibcon#read 5, iclass 22, count 0 2006.257.04:40:14.79#ibcon#about to read 6, iclass 22, count 0 2006.257.04:40:14.79#ibcon#read 6, iclass 22, count 0 2006.257.04:40:14.79#ibcon#end of sib2, iclass 22, count 0 2006.257.04:40:14.79#ibcon#*after write, iclass 22, count 0 2006.257.04:40:14.79#ibcon#*before return 0, iclass 22, count 0 2006.257.04:40:14.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:40:14.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:40:14.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.04:40:14.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.04:40:14.79$setupk4/ifdk4 2006.257.04:40:14.79$ifdk4/lo= 2006.257.04:40:14.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.04:40:14.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.04:40:14.79$ifdk4/patch= 2006.257.04:40:14.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.04:40:14.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.04:40:14.79$setupk4/!*+20s 2006.257.04:40:24.70#abcon#<5=/14 1.7 4.9 19.62 931011.9\r\n> 2006.257.04:40:24.72#abcon#{5=INTERFACE CLEAR} 2006.257.04:40:24.78#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:40:29.29$setupk4/"tpicd 2006.257.04:40:29.29$setupk4/echo=off 2006.257.04:40:29.29$setupk4/xlog=off 2006.257.04:40:29.29:!2006.257.04:42:38 2006.257.04:40:31.14#trakl#Source acquired 2006.257.04:40:32.14#flagr#flagr/antenna,acquired 2006.257.04:42:38.00:preob 2006.257.04:42:39.14/onsource/TRACKING 2006.257.04:42:39.14:!2006.257.04:42:48 2006.257.04:42:48.00:"tape 2006.257.04:42:48.00:"st=record 2006.257.04:42:48.00:data_valid=on 2006.257.04:42:48.00:midob 2006.257.04:42:48.13/onsource/TRACKING 2006.257.04:42:48.13/wx/19.64,1011.9,93 2006.257.04:42:48.27/cable/+6.4825E-03 2006.257.04:42:49.36/va/01,08,usb,yes,31,33 2006.257.04:42:49.36/va/02,07,usb,yes,34,34 2006.257.04:42:49.36/va/03,08,usb,yes,30,32 2006.257.04:42:49.36/va/04,07,usb,yes,35,36 2006.257.04:42:49.36/va/05,04,usb,yes,31,32 2006.257.04:42:49.36/va/06,04,usb,yes,35,34 2006.257.04:42:49.36/va/07,04,usb,yes,36,36 2006.257.04:42:49.36/va/08,04,usb,yes,30,36 2006.257.04:42:49.59/valo/01,524.99,yes,locked 2006.257.04:42:49.59/valo/02,534.99,yes,locked 2006.257.04:42:49.59/valo/03,564.99,yes,locked 2006.257.04:42:49.59/valo/04,624.99,yes,locked 2006.257.04:42:49.59/valo/05,734.99,yes,locked 2006.257.04:42:49.59/valo/06,814.99,yes,locked 2006.257.04:42:49.59/valo/07,864.99,yes,locked 2006.257.04:42:49.59/valo/08,884.99,yes,locked 2006.257.04:42:50.68/vb/01,04,usb,yes,30,28 2006.257.04:42:50.68/vb/02,05,usb,yes,29,29 2006.257.04:42:50.68/vb/03,04,usb,yes,30,33 2006.257.04:42:50.68/vb/04,05,usb,yes,30,29 2006.257.04:42:50.68/vb/05,04,usb,yes,27,29 2006.257.04:42:50.68/vb/06,04,usb,yes,31,27 2006.257.04:42:50.68/vb/07,04,usb,yes,31,31 2006.257.04:42:50.68/vb/08,04,usb,yes,28,32 2006.257.04:42:50.91/vblo/01,629.99,yes,locked 2006.257.04:42:50.91/vblo/02,634.99,yes,locked 2006.257.04:42:50.91/vblo/03,649.99,yes,locked 2006.257.04:42:50.91/vblo/04,679.99,yes,locked 2006.257.04:42:50.91/vblo/05,709.99,yes,locked 2006.257.04:42:50.91/vblo/06,719.99,yes,locked 2006.257.04:42:50.91/vblo/07,734.99,yes,locked 2006.257.04:42:50.91/vblo/08,744.99,yes,locked 2006.257.04:42:51.06/vabw/8 2006.257.04:42:51.21/vbbw/8 2006.257.04:42:51.30/xfe/off,on,16.7 2006.257.04:42:51.69/ifatt/23,28,28,28 2006.257.04:42:52.08/fmout-gps/S +4.53E-07 2006.257.04:42:52.12:!2006.257.04:43:38 2006.257.04:43:38.00:data_valid=off 2006.257.04:43:38.00:"et 2006.257.04:43:38.00:!+3s 2006.257.04:43:41.01:"tape 2006.257.04:43:41.01:postob 2006.257.04:43:41.20/cable/+6.4820E-03 2006.257.04:43:41.20/wx/19.64,1012.0,92 2006.257.04:43:42.08/fmout-gps/S +4.53E-07 2006.257.04:43:42.08:scan_name=257-0449,jd0609,80 2006.257.04:43:42.08:source=3c274,123049.42,122328.0,2000.0,cw 2006.257.04:43:43.13#flagr#flagr/antenna,new-source 2006.257.04:43:43.13:checkk5 2006.257.04:43:43.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.04:43:43.89/chk_autoobs//k5ts2/ autoobs is running! 2006.257.04:43:44.29/chk_autoobs//k5ts3/ autoobs is running! 2006.257.04:43:44.80/chk_autoobs//k5ts4/ autoobs is running! 2006.257.04:43:45.20/chk_obsdata//k5ts1/T2570442??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.04:43:45.62/chk_obsdata//k5ts2/T2570442??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.04:43:46.03/chk_obsdata//k5ts3/T2570442??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.04:43:46.43/chk_obsdata//k5ts4/T2570442??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.04:43:47.15/k5log//k5ts1_log_newline 2006.257.04:43:47.85/k5log//k5ts2_log_newline 2006.257.04:43:48.59/k5log//k5ts3_log_newline 2006.257.04:43:49.32/k5log//k5ts4_log_newline 2006.257.04:43:49.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.04:43:49.34:setupk4=1 2006.257.04:43:49.34$setupk4/echo=on 2006.257.04:43:49.34$setupk4/pcalon 2006.257.04:43:49.34$pcalon/"no phase cal control is implemented here 2006.257.04:43:49.34$setupk4/"tpicd=stop 2006.257.04:43:49.34$setupk4/"rec=synch_on 2006.257.04:43:49.34$setupk4/"rec_mode=128 2006.257.04:43:49.34$setupk4/!* 2006.257.04:43:49.34$setupk4/recpk4 2006.257.04:43:49.34$recpk4/recpatch= 2006.257.04:43:49.35$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.04:43:49.35$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.04:43:49.35$setupk4/vck44 2006.257.04:43:49.35$vck44/valo=1,524.99 2006.257.04:43:49.35#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.04:43:49.35#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.04:43:49.35#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:49.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:49.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:49.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:49.35#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:43:49.35#ibcon#first serial, iclass 39, count 0 2006.257.04:43:49.35#ibcon#enter sib2, iclass 39, count 0 2006.257.04:43:49.35#ibcon#flushed, iclass 39, count 0 2006.257.04:43:49.35#ibcon#about to write, iclass 39, count 0 2006.257.04:43:49.35#ibcon#wrote, iclass 39, count 0 2006.257.04:43:49.35#ibcon#about to read 3, iclass 39, count 0 2006.257.04:43:49.37#ibcon#read 3, iclass 39, count 0 2006.257.04:43:49.37#ibcon#about to read 4, iclass 39, count 0 2006.257.04:43:49.37#ibcon#read 4, iclass 39, count 0 2006.257.04:43:49.37#ibcon#about to read 5, iclass 39, count 0 2006.257.04:43:49.37#ibcon#read 5, iclass 39, count 0 2006.257.04:43:49.37#ibcon#about to read 6, iclass 39, count 0 2006.257.04:43:49.37#ibcon#read 6, iclass 39, count 0 2006.257.04:43:49.37#ibcon#end of sib2, iclass 39, count 0 2006.257.04:43:49.37#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:43:49.37#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:43:49.37#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.04:43:49.37#ibcon#*before write, iclass 39, count 0 2006.257.04:43:49.37#ibcon#enter sib2, iclass 39, count 0 2006.257.04:43:49.37#ibcon#flushed, iclass 39, count 0 2006.257.04:43:49.37#ibcon#about to write, iclass 39, count 0 2006.257.04:43:49.37#ibcon#wrote, iclass 39, count 0 2006.257.04:43:49.37#ibcon#about to read 3, iclass 39, count 0 2006.257.04:43:49.42#ibcon#read 3, iclass 39, count 0 2006.257.04:43:49.42#ibcon#about to read 4, iclass 39, count 0 2006.257.04:43:49.42#ibcon#read 4, iclass 39, count 0 2006.257.04:43:49.42#ibcon#about to read 5, iclass 39, count 0 2006.257.04:43:49.42#ibcon#read 5, iclass 39, count 0 2006.257.04:43:49.42#ibcon#about to read 6, iclass 39, count 0 2006.257.04:43:49.42#ibcon#read 6, iclass 39, count 0 2006.257.04:43:49.42#ibcon#end of sib2, iclass 39, count 0 2006.257.04:43:49.42#ibcon#*after write, iclass 39, count 0 2006.257.04:43:49.42#ibcon#*before return 0, iclass 39, count 0 2006.257.04:43:49.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:49.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:49.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:43:49.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:43:49.42$vck44/va=1,8 2006.257.04:43:49.42#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.04:43:49.42#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.04:43:49.42#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:49.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:49.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:49.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:49.42#ibcon#enter wrdev, iclass 3, count 2 2006.257.04:43:49.42#ibcon#first serial, iclass 3, count 2 2006.257.04:43:49.42#ibcon#enter sib2, iclass 3, count 2 2006.257.04:43:49.42#ibcon#flushed, iclass 3, count 2 2006.257.04:43:49.42#ibcon#about to write, iclass 3, count 2 2006.257.04:43:49.42#ibcon#wrote, iclass 3, count 2 2006.257.04:43:49.42#ibcon#about to read 3, iclass 3, count 2 2006.257.04:43:49.44#ibcon#read 3, iclass 3, count 2 2006.257.04:43:49.44#ibcon#about to read 4, iclass 3, count 2 2006.257.04:43:49.44#ibcon#read 4, iclass 3, count 2 2006.257.04:43:49.44#ibcon#about to read 5, iclass 3, count 2 2006.257.04:43:49.44#ibcon#read 5, iclass 3, count 2 2006.257.04:43:49.44#ibcon#about to read 6, iclass 3, count 2 2006.257.04:43:49.44#ibcon#read 6, iclass 3, count 2 2006.257.04:43:49.44#ibcon#end of sib2, iclass 3, count 2 2006.257.04:43:49.44#ibcon#*mode == 0, iclass 3, count 2 2006.257.04:43:49.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.04:43:49.44#ibcon#[25=AT01-08\r\n] 2006.257.04:43:49.44#ibcon#*before write, iclass 3, count 2 2006.257.04:43:49.44#ibcon#enter sib2, iclass 3, count 2 2006.257.04:43:49.44#ibcon#flushed, iclass 3, count 2 2006.257.04:43:49.44#ibcon#about to write, iclass 3, count 2 2006.257.04:43:49.44#ibcon#wrote, iclass 3, count 2 2006.257.04:43:49.44#ibcon#about to read 3, iclass 3, count 2 2006.257.04:43:49.47#ibcon#read 3, iclass 3, count 2 2006.257.04:43:49.47#ibcon#about to read 4, iclass 3, count 2 2006.257.04:43:49.47#ibcon#read 4, iclass 3, count 2 2006.257.04:43:49.47#ibcon#about to read 5, iclass 3, count 2 2006.257.04:43:49.47#ibcon#read 5, iclass 3, count 2 2006.257.04:43:49.47#ibcon#about to read 6, iclass 3, count 2 2006.257.04:43:49.47#ibcon#read 6, iclass 3, count 2 2006.257.04:43:49.47#ibcon#end of sib2, iclass 3, count 2 2006.257.04:43:49.47#ibcon#*after write, iclass 3, count 2 2006.257.04:43:49.47#ibcon#*before return 0, iclass 3, count 2 2006.257.04:43:49.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:49.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:49.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.04:43:49.47#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:49.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:49.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:49.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:49.59#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:43:49.59#ibcon#first serial, iclass 3, count 0 2006.257.04:43:49.59#ibcon#enter sib2, iclass 3, count 0 2006.257.04:43:49.59#ibcon#flushed, iclass 3, count 0 2006.257.04:43:49.59#ibcon#about to write, iclass 3, count 0 2006.257.04:43:49.59#ibcon#wrote, iclass 3, count 0 2006.257.04:43:49.59#ibcon#about to read 3, iclass 3, count 0 2006.257.04:43:49.61#ibcon#read 3, iclass 3, count 0 2006.257.04:43:49.61#ibcon#about to read 4, iclass 3, count 0 2006.257.04:43:49.61#ibcon#read 4, iclass 3, count 0 2006.257.04:43:49.61#ibcon#about to read 5, iclass 3, count 0 2006.257.04:43:49.61#ibcon#read 5, iclass 3, count 0 2006.257.04:43:49.61#ibcon#about to read 6, iclass 3, count 0 2006.257.04:43:49.61#ibcon#read 6, iclass 3, count 0 2006.257.04:43:49.61#ibcon#end of sib2, iclass 3, count 0 2006.257.04:43:49.61#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:43:49.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:43:49.61#ibcon#[25=USB\r\n] 2006.257.04:43:49.61#ibcon#*before write, iclass 3, count 0 2006.257.04:43:49.61#ibcon#enter sib2, iclass 3, count 0 2006.257.04:43:49.61#ibcon#flushed, iclass 3, count 0 2006.257.04:43:49.61#ibcon#about to write, iclass 3, count 0 2006.257.04:43:49.61#ibcon#wrote, iclass 3, count 0 2006.257.04:43:49.61#ibcon#about to read 3, iclass 3, count 0 2006.257.04:43:49.64#ibcon#read 3, iclass 3, count 0 2006.257.04:43:49.64#ibcon#about to read 4, iclass 3, count 0 2006.257.04:43:49.64#ibcon#read 4, iclass 3, count 0 2006.257.04:43:49.64#ibcon#about to read 5, iclass 3, count 0 2006.257.04:43:49.64#ibcon#read 5, iclass 3, count 0 2006.257.04:43:49.64#ibcon#about to read 6, iclass 3, count 0 2006.257.04:43:49.64#ibcon#read 6, iclass 3, count 0 2006.257.04:43:49.64#ibcon#end of sib2, iclass 3, count 0 2006.257.04:43:49.64#ibcon#*after write, iclass 3, count 0 2006.257.04:43:49.64#ibcon#*before return 0, iclass 3, count 0 2006.257.04:43:49.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:49.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:49.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:43:49.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:43:49.64$vck44/valo=2,534.99 2006.257.04:43:49.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.04:43:49.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.04:43:49.64#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:49.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:49.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:49.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:49.64#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:43:49.64#ibcon#first serial, iclass 5, count 0 2006.257.04:43:49.64#ibcon#enter sib2, iclass 5, count 0 2006.257.04:43:49.64#ibcon#flushed, iclass 5, count 0 2006.257.04:43:49.64#ibcon#about to write, iclass 5, count 0 2006.257.04:43:49.64#ibcon#wrote, iclass 5, count 0 2006.257.04:43:49.64#ibcon#about to read 3, iclass 5, count 0 2006.257.04:43:49.66#ibcon#read 3, iclass 5, count 0 2006.257.04:43:49.66#ibcon#about to read 4, iclass 5, count 0 2006.257.04:43:49.66#ibcon#read 4, iclass 5, count 0 2006.257.04:43:49.66#ibcon#about to read 5, iclass 5, count 0 2006.257.04:43:49.66#ibcon#read 5, iclass 5, count 0 2006.257.04:43:49.66#ibcon#about to read 6, iclass 5, count 0 2006.257.04:43:49.66#ibcon#read 6, iclass 5, count 0 2006.257.04:43:49.66#ibcon#end of sib2, iclass 5, count 0 2006.257.04:43:49.66#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:43:49.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:43:49.66#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.04:43:49.66#ibcon#*before write, iclass 5, count 0 2006.257.04:43:49.66#ibcon#enter sib2, iclass 5, count 0 2006.257.04:43:49.66#ibcon#flushed, iclass 5, count 0 2006.257.04:43:49.66#ibcon#about to write, iclass 5, count 0 2006.257.04:43:49.66#ibcon#wrote, iclass 5, count 0 2006.257.04:43:49.66#ibcon#about to read 3, iclass 5, count 0 2006.257.04:43:49.70#ibcon#read 3, iclass 5, count 0 2006.257.04:43:49.70#ibcon#about to read 4, iclass 5, count 0 2006.257.04:43:49.70#ibcon#read 4, iclass 5, count 0 2006.257.04:43:49.70#ibcon#about to read 5, iclass 5, count 0 2006.257.04:43:49.70#ibcon#read 5, iclass 5, count 0 2006.257.04:43:49.70#ibcon#about to read 6, iclass 5, count 0 2006.257.04:43:49.70#ibcon#read 6, iclass 5, count 0 2006.257.04:43:49.70#ibcon#end of sib2, iclass 5, count 0 2006.257.04:43:49.70#ibcon#*after write, iclass 5, count 0 2006.257.04:43:49.70#ibcon#*before return 0, iclass 5, count 0 2006.257.04:43:49.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:49.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:49.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:43:49.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:43:49.70$vck44/va=2,7 2006.257.04:43:49.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.04:43:49.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.04:43:49.70#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:49.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:49.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:49.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:49.76#ibcon#enter wrdev, iclass 7, count 2 2006.257.04:43:49.76#ibcon#first serial, iclass 7, count 2 2006.257.04:43:49.76#ibcon#enter sib2, iclass 7, count 2 2006.257.04:43:49.76#ibcon#flushed, iclass 7, count 2 2006.257.04:43:49.76#ibcon#about to write, iclass 7, count 2 2006.257.04:43:49.76#ibcon#wrote, iclass 7, count 2 2006.257.04:43:49.76#ibcon#about to read 3, iclass 7, count 2 2006.257.04:43:49.78#ibcon#read 3, iclass 7, count 2 2006.257.04:43:49.78#ibcon#about to read 4, iclass 7, count 2 2006.257.04:43:49.78#ibcon#read 4, iclass 7, count 2 2006.257.04:43:49.78#ibcon#about to read 5, iclass 7, count 2 2006.257.04:43:49.78#ibcon#read 5, iclass 7, count 2 2006.257.04:43:49.78#ibcon#about to read 6, iclass 7, count 2 2006.257.04:43:49.78#ibcon#read 6, iclass 7, count 2 2006.257.04:43:49.78#ibcon#end of sib2, iclass 7, count 2 2006.257.04:43:49.78#ibcon#*mode == 0, iclass 7, count 2 2006.257.04:43:49.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.04:43:49.78#ibcon#[25=AT02-07\r\n] 2006.257.04:43:49.78#ibcon#*before write, iclass 7, count 2 2006.257.04:43:49.78#ibcon#enter sib2, iclass 7, count 2 2006.257.04:43:49.78#ibcon#flushed, iclass 7, count 2 2006.257.04:43:49.78#ibcon#about to write, iclass 7, count 2 2006.257.04:43:49.78#ibcon#wrote, iclass 7, count 2 2006.257.04:43:49.78#ibcon#about to read 3, iclass 7, count 2 2006.257.04:43:49.81#ibcon#read 3, iclass 7, count 2 2006.257.04:43:49.81#ibcon#about to read 4, iclass 7, count 2 2006.257.04:43:49.81#ibcon#read 4, iclass 7, count 2 2006.257.04:43:49.81#ibcon#about to read 5, iclass 7, count 2 2006.257.04:43:49.81#ibcon#read 5, iclass 7, count 2 2006.257.04:43:49.81#ibcon#about to read 6, iclass 7, count 2 2006.257.04:43:49.81#ibcon#read 6, iclass 7, count 2 2006.257.04:43:49.81#ibcon#end of sib2, iclass 7, count 2 2006.257.04:43:49.81#ibcon#*after write, iclass 7, count 2 2006.257.04:43:49.81#ibcon#*before return 0, iclass 7, count 2 2006.257.04:43:49.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:49.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:49.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.04:43:49.81#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:49.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:49.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:49.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:49.93#ibcon#enter wrdev, iclass 7, count 0 2006.257.04:43:49.93#ibcon#first serial, iclass 7, count 0 2006.257.04:43:49.93#ibcon#enter sib2, iclass 7, count 0 2006.257.04:43:49.93#ibcon#flushed, iclass 7, count 0 2006.257.04:43:49.93#ibcon#about to write, iclass 7, count 0 2006.257.04:43:49.93#ibcon#wrote, iclass 7, count 0 2006.257.04:43:49.93#ibcon#about to read 3, iclass 7, count 0 2006.257.04:43:49.95#ibcon#read 3, iclass 7, count 0 2006.257.04:43:49.95#ibcon#about to read 4, iclass 7, count 0 2006.257.04:43:49.95#ibcon#read 4, iclass 7, count 0 2006.257.04:43:49.95#ibcon#about to read 5, iclass 7, count 0 2006.257.04:43:49.95#ibcon#read 5, iclass 7, count 0 2006.257.04:43:49.95#ibcon#about to read 6, iclass 7, count 0 2006.257.04:43:49.95#ibcon#read 6, iclass 7, count 0 2006.257.04:43:49.95#ibcon#end of sib2, iclass 7, count 0 2006.257.04:43:49.95#ibcon#*mode == 0, iclass 7, count 0 2006.257.04:43:49.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.04:43:49.95#ibcon#[25=USB\r\n] 2006.257.04:43:49.95#ibcon#*before write, iclass 7, count 0 2006.257.04:43:49.95#ibcon#enter sib2, iclass 7, count 0 2006.257.04:43:49.95#ibcon#flushed, iclass 7, count 0 2006.257.04:43:49.95#ibcon#about to write, iclass 7, count 0 2006.257.04:43:49.95#ibcon#wrote, iclass 7, count 0 2006.257.04:43:49.95#ibcon#about to read 3, iclass 7, count 0 2006.257.04:43:49.98#ibcon#read 3, iclass 7, count 0 2006.257.04:43:49.98#ibcon#about to read 4, iclass 7, count 0 2006.257.04:43:49.98#ibcon#read 4, iclass 7, count 0 2006.257.04:43:49.98#ibcon#about to read 5, iclass 7, count 0 2006.257.04:43:49.98#ibcon#read 5, iclass 7, count 0 2006.257.04:43:49.98#ibcon#about to read 6, iclass 7, count 0 2006.257.04:43:49.98#ibcon#read 6, iclass 7, count 0 2006.257.04:43:49.98#ibcon#end of sib2, iclass 7, count 0 2006.257.04:43:49.98#ibcon#*after write, iclass 7, count 0 2006.257.04:43:49.98#ibcon#*before return 0, iclass 7, count 0 2006.257.04:43:49.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:49.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:49.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.04:43:49.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.04:43:49.98$vck44/valo=3,564.99 2006.257.04:43:49.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.04:43:49.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.04:43:49.98#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:49.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:49.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:49.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:49.98#ibcon#enter wrdev, iclass 11, count 0 2006.257.04:43:49.98#ibcon#first serial, iclass 11, count 0 2006.257.04:43:49.98#ibcon#enter sib2, iclass 11, count 0 2006.257.04:43:49.98#ibcon#flushed, iclass 11, count 0 2006.257.04:43:49.98#ibcon#about to write, iclass 11, count 0 2006.257.04:43:49.98#ibcon#wrote, iclass 11, count 0 2006.257.04:43:49.98#ibcon#about to read 3, iclass 11, count 0 2006.257.04:43:50.00#ibcon#read 3, iclass 11, count 0 2006.257.04:43:50.00#ibcon#about to read 4, iclass 11, count 0 2006.257.04:43:50.00#ibcon#read 4, iclass 11, count 0 2006.257.04:43:50.00#ibcon#about to read 5, iclass 11, count 0 2006.257.04:43:50.00#ibcon#read 5, iclass 11, count 0 2006.257.04:43:50.00#ibcon#about to read 6, iclass 11, count 0 2006.257.04:43:50.00#ibcon#read 6, iclass 11, count 0 2006.257.04:43:50.00#ibcon#end of sib2, iclass 11, count 0 2006.257.04:43:50.00#ibcon#*mode == 0, iclass 11, count 0 2006.257.04:43:50.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.04:43:50.00#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.04:43:50.00#ibcon#*before write, iclass 11, count 0 2006.257.04:43:50.00#ibcon#enter sib2, iclass 11, count 0 2006.257.04:43:50.00#ibcon#flushed, iclass 11, count 0 2006.257.04:43:50.00#ibcon#about to write, iclass 11, count 0 2006.257.04:43:50.00#ibcon#wrote, iclass 11, count 0 2006.257.04:43:50.00#ibcon#about to read 3, iclass 11, count 0 2006.257.04:43:50.04#ibcon#read 3, iclass 11, count 0 2006.257.04:43:50.04#ibcon#about to read 4, iclass 11, count 0 2006.257.04:43:50.04#ibcon#read 4, iclass 11, count 0 2006.257.04:43:50.04#ibcon#about to read 5, iclass 11, count 0 2006.257.04:43:50.04#ibcon#read 5, iclass 11, count 0 2006.257.04:43:50.04#ibcon#about to read 6, iclass 11, count 0 2006.257.04:43:50.04#ibcon#read 6, iclass 11, count 0 2006.257.04:43:50.04#ibcon#end of sib2, iclass 11, count 0 2006.257.04:43:50.04#ibcon#*after write, iclass 11, count 0 2006.257.04:43:50.04#ibcon#*before return 0, iclass 11, count 0 2006.257.04:43:50.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:50.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:50.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.04:43:50.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.04:43:50.04$vck44/va=3,8 2006.257.04:43:50.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.04:43:50.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.04:43:50.04#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:50.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:50.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:50.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:50.10#ibcon#enter wrdev, iclass 13, count 2 2006.257.04:43:50.10#ibcon#first serial, iclass 13, count 2 2006.257.04:43:50.10#ibcon#enter sib2, iclass 13, count 2 2006.257.04:43:50.10#ibcon#flushed, iclass 13, count 2 2006.257.04:43:50.10#ibcon#about to write, iclass 13, count 2 2006.257.04:43:50.10#ibcon#wrote, iclass 13, count 2 2006.257.04:43:50.10#ibcon#about to read 3, iclass 13, count 2 2006.257.04:43:50.12#ibcon#read 3, iclass 13, count 2 2006.257.04:43:50.12#ibcon#about to read 4, iclass 13, count 2 2006.257.04:43:50.12#ibcon#read 4, iclass 13, count 2 2006.257.04:43:50.12#ibcon#about to read 5, iclass 13, count 2 2006.257.04:43:50.12#ibcon#read 5, iclass 13, count 2 2006.257.04:43:50.12#ibcon#about to read 6, iclass 13, count 2 2006.257.04:43:50.12#ibcon#read 6, iclass 13, count 2 2006.257.04:43:50.12#ibcon#end of sib2, iclass 13, count 2 2006.257.04:43:50.12#ibcon#*mode == 0, iclass 13, count 2 2006.257.04:43:50.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.04:43:50.12#ibcon#[25=AT03-08\r\n] 2006.257.04:43:50.12#ibcon#*before write, iclass 13, count 2 2006.257.04:43:50.12#ibcon#enter sib2, iclass 13, count 2 2006.257.04:43:50.12#ibcon#flushed, iclass 13, count 2 2006.257.04:43:50.12#ibcon#about to write, iclass 13, count 2 2006.257.04:43:50.12#ibcon#wrote, iclass 13, count 2 2006.257.04:43:50.12#ibcon#about to read 3, iclass 13, count 2 2006.257.04:43:50.15#ibcon#read 3, iclass 13, count 2 2006.257.04:43:50.15#ibcon#about to read 4, iclass 13, count 2 2006.257.04:43:50.15#ibcon#read 4, iclass 13, count 2 2006.257.04:43:50.15#ibcon#about to read 5, iclass 13, count 2 2006.257.04:43:50.15#ibcon#read 5, iclass 13, count 2 2006.257.04:43:50.15#ibcon#about to read 6, iclass 13, count 2 2006.257.04:43:50.15#ibcon#read 6, iclass 13, count 2 2006.257.04:43:50.15#ibcon#end of sib2, iclass 13, count 2 2006.257.04:43:50.15#ibcon#*after write, iclass 13, count 2 2006.257.04:43:50.15#ibcon#*before return 0, iclass 13, count 2 2006.257.04:43:50.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:50.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:50.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.04:43:50.15#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:50.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:50.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:50.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:50.27#ibcon#enter wrdev, iclass 13, count 0 2006.257.04:43:50.27#ibcon#first serial, iclass 13, count 0 2006.257.04:43:50.27#ibcon#enter sib2, iclass 13, count 0 2006.257.04:43:50.27#ibcon#flushed, iclass 13, count 0 2006.257.04:43:50.27#ibcon#about to write, iclass 13, count 0 2006.257.04:43:50.27#ibcon#wrote, iclass 13, count 0 2006.257.04:43:50.27#ibcon#about to read 3, iclass 13, count 0 2006.257.04:43:50.29#ibcon#read 3, iclass 13, count 0 2006.257.04:43:50.29#ibcon#about to read 4, iclass 13, count 0 2006.257.04:43:50.29#ibcon#read 4, iclass 13, count 0 2006.257.04:43:50.29#ibcon#about to read 5, iclass 13, count 0 2006.257.04:43:50.29#ibcon#read 5, iclass 13, count 0 2006.257.04:43:50.29#ibcon#about to read 6, iclass 13, count 0 2006.257.04:43:50.29#ibcon#read 6, iclass 13, count 0 2006.257.04:43:50.29#ibcon#end of sib2, iclass 13, count 0 2006.257.04:43:50.29#ibcon#*mode == 0, iclass 13, count 0 2006.257.04:43:50.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.04:43:50.29#ibcon#[25=USB\r\n] 2006.257.04:43:50.29#ibcon#*before write, iclass 13, count 0 2006.257.04:43:50.29#ibcon#enter sib2, iclass 13, count 0 2006.257.04:43:50.29#ibcon#flushed, iclass 13, count 0 2006.257.04:43:50.29#ibcon#about to write, iclass 13, count 0 2006.257.04:43:50.29#ibcon#wrote, iclass 13, count 0 2006.257.04:43:50.29#ibcon#about to read 3, iclass 13, count 0 2006.257.04:43:50.32#ibcon#read 3, iclass 13, count 0 2006.257.04:43:50.32#ibcon#about to read 4, iclass 13, count 0 2006.257.04:43:50.32#ibcon#read 4, iclass 13, count 0 2006.257.04:43:50.32#ibcon#about to read 5, iclass 13, count 0 2006.257.04:43:50.32#ibcon#read 5, iclass 13, count 0 2006.257.04:43:50.32#ibcon#about to read 6, iclass 13, count 0 2006.257.04:43:50.32#ibcon#read 6, iclass 13, count 0 2006.257.04:43:50.32#ibcon#end of sib2, iclass 13, count 0 2006.257.04:43:50.32#ibcon#*after write, iclass 13, count 0 2006.257.04:43:50.32#ibcon#*before return 0, iclass 13, count 0 2006.257.04:43:50.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:50.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:50.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.04:43:50.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.04:43:50.32$vck44/valo=4,624.99 2006.257.04:43:50.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.04:43:50.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.04:43:50.32#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:50.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:50.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:50.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:50.32#ibcon#enter wrdev, iclass 15, count 0 2006.257.04:43:50.32#ibcon#first serial, iclass 15, count 0 2006.257.04:43:50.32#ibcon#enter sib2, iclass 15, count 0 2006.257.04:43:50.32#ibcon#flushed, iclass 15, count 0 2006.257.04:43:50.32#ibcon#about to write, iclass 15, count 0 2006.257.04:43:50.32#ibcon#wrote, iclass 15, count 0 2006.257.04:43:50.32#ibcon#about to read 3, iclass 15, count 0 2006.257.04:43:50.34#ibcon#read 3, iclass 15, count 0 2006.257.04:43:50.34#ibcon#about to read 4, iclass 15, count 0 2006.257.04:43:50.34#ibcon#read 4, iclass 15, count 0 2006.257.04:43:50.34#ibcon#about to read 5, iclass 15, count 0 2006.257.04:43:50.34#ibcon#read 5, iclass 15, count 0 2006.257.04:43:50.34#ibcon#about to read 6, iclass 15, count 0 2006.257.04:43:50.34#ibcon#read 6, iclass 15, count 0 2006.257.04:43:50.34#ibcon#end of sib2, iclass 15, count 0 2006.257.04:43:50.34#ibcon#*mode == 0, iclass 15, count 0 2006.257.04:43:50.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.04:43:50.34#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.04:43:50.34#ibcon#*before write, iclass 15, count 0 2006.257.04:43:50.34#ibcon#enter sib2, iclass 15, count 0 2006.257.04:43:50.34#ibcon#flushed, iclass 15, count 0 2006.257.04:43:50.34#ibcon#about to write, iclass 15, count 0 2006.257.04:43:50.34#ibcon#wrote, iclass 15, count 0 2006.257.04:43:50.34#ibcon#about to read 3, iclass 15, count 0 2006.257.04:43:50.38#ibcon#read 3, iclass 15, count 0 2006.257.04:43:50.38#ibcon#about to read 4, iclass 15, count 0 2006.257.04:43:50.38#ibcon#read 4, iclass 15, count 0 2006.257.04:43:50.38#ibcon#about to read 5, iclass 15, count 0 2006.257.04:43:50.38#ibcon#read 5, iclass 15, count 0 2006.257.04:43:50.38#ibcon#about to read 6, iclass 15, count 0 2006.257.04:43:50.38#ibcon#read 6, iclass 15, count 0 2006.257.04:43:50.38#ibcon#end of sib2, iclass 15, count 0 2006.257.04:43:50.38#ibcon#*after write, iclass 15, count 0 2006.257.04:43:50.38#ibcon#*before return 0, iclass 15, count 0 2006.257.04:43:50.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:50.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:50.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.04:43:50.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.04:43:50.38$vck44/va=4,7 2006.257.04:43:50.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.04:43:50.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.04:43:50.38#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:50.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:50.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:50.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:50.44#ibcon#enter wrdev, iclass 17, count 2 2006.257.04:43:50.44#ibcon#first serial, iclass 17, count 2 2006.257.04:43:50.44#ibcon#enter sib2, iclass 17, count 2 2006.257.04:43:50.44#ibcon#flushed, iclass 17, count 2 2006.257.04:43:50.44#ibcon#about to write, iclass 17, count 2 2006.257.04:43:50.44#ibcon#wrote, iclass 17, count 2 2006.257.04:43:50.44#ibcon#about to read 3, iclass 17, count 2 2006.257.04:43:50.46#ibcon#read 3, iclass 17, count 2 2006.257.04:43:50.46#ibcon#about to read 4, iclass 17, count 2 2006.257.04:43:50.46#ibcon#read 4, iclass 17, count 2 2006.257.04:43:50.46#ibcon#about to read 5, iclass 17, count 2 2006.257.04:43:50.46#ibcon#read 5, iclass 17, count 2 2006.257.04:43:50.46#ibcon#about to read 6, iclass 17, count 2 2006.257.04:43:50.46#ibcon#read 6, iclass 17, count 2 2006.257.04:43:50.46#ibcon#end of sib2, iclass 17, count 2 2006.257.04:43:50.46#ibcon#*mode == 0, iclass 17, count 2 2006.257.04:43:50.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.04:43:50.46#ibcon#[25=AT04-07\r\n] 2006.257.04:43:50.46#ibcon#*before write, iclass 17, count 2 2006.257.04:43:50.46#ibcon#enter sib2, iclass 17, count 2 2006.257.04:43:50.46#ibcon#flushed, iclass 17, count 2 2006.257.04:43:50.46#ibcon#about to write, iclass 17, count 2 2006.257.04:43:50.46#ibcon#wrote, iclass 17, count 2 2006.257.04:43:50.46#ibcon#about to read 3, iclass 17, count 2 2006.257.04:43:50.49#ibcon#read 3, iclass 17, count 2 2006.257.04:43:50.49#ibcon#about to read 4, iclass 17, count 2 2006.257.04:43:50.49#ibcon#read 4, iclass 17, count 2 2006.257.04:43:50.49#ibcon#about to read 5, iclass 17, count 2 2006.257.04:43:50.49#ibcon#read 5, iclass 17, count 2 2006.257.04:43:50.49#ibcon#about to read 6, iclass 17, count 2 2006.257.04:43:50.49#ibcon#read 6, iclass 17, count 2 2006.257.04:43:50.49#ibcon#end of sib2, iclass 17, count 2 2006.257.04:43:50.49#ibcon#*after write, iclass 17, count 2 2006.257.04:43:50.49#ibcon#*before return 0, iclass 17, count 2 2006.257.04:43:50.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:50.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:50.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.04:43:50.49#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:50.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:50.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:50.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:50.61#ibcon#enter wrdev, iclass 17, count 0 2006.257.04:43:50.61#ibcon#first serial, iclass 17, count 0 2006.257.04:43:50.61#ibcon#enter sib2, iclass 17, count 0 2006.257.04:43:50.61#ibcon#flushed, iclass 17, count 0 2006.257.04:43:50.61#ibcon#about to write, iclass 17, count 0 2006.257.04:43:50.61#ibcon#wrote, iclass 17, count 0 2006.257.04:43:50.61#ibcon#about to read 3, iclass 17, count 0 2006.257.04:43:50.63#ibcon#read 3, iclass 17, count 0 2006.257.04:43:50.63#ibcon#about to read 4, iclass 17, count 0 2006.257.04:43:50.63#ibcon#read 4, iclass 17, count 0 2006.257.04:43:50.63#ibcon#about to read 5, iclass 17, count 0 2006.257.04:43:50.63#ibcon#read 5, iclass 17, count 0 2006.257.04:43:50.63#ibcon#about to read 6, iclass 17, count 0 2006.257.04:43:50.63#ibcon#read 6, iclass 17, count 0 2006.257.04:43:50.63#ibcon#end of sib2, iclass 17, count 0 2006.257.04:43:50.63#ibcon#*mode == 0, iclass 17, count 0 2006.257.04:43:50.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.04:43:50.63#ibcon#[25=USB\r\n] 2006.257.04:43:50.63#ibcon#*before write, iclass 17, count 0 2006.257.04:43:50.63#ibcon#enter sib2, iclass 17, count 0 2006.257.04:43:50.63#ibcon#flushed, iclass 17, count 0 2006.257.04:43:50.63#ibcon#about to write, iclass 17, count 0 2006.257.04:43:50.63#ibcon#wrote, iclass 17, count 0 2006.257.04:43:50.63#ibcon#about to read 3, iclass 17, count 0 2006.257.04:43:50.66#ibcon#read 3, iclass 17, count 0 2006.257.04:43:50.66#ibcon#about to read 4, iclass 17, count 0 2006.257.04:43:50.66#ibcon#read 4, iclass 17, count 0 2006.257.04:43:50.66#ibcon#about to read 5, iclass 17, count 0 2006.257.04:43:50.66#ibcon#read 5, iclass 17, count 0 2006.257.04:43:50.66#ibcon#about to read 6, iclass 17, count 0 2006.257.04:43:50.66#ibcon#read 6, iclass 17, count 0 2006.257.04:43:50.66#ibcon#end of sib2, iclass 17, count 0 2006.257.04:43:50.66#ibcon#*after write, iclass 17, count 0 2006.257.04:43:50.66#ibcon#*before return 0, iclass 17, count 0 2006.257.04:43:50.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:50.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:50.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.04:43:50.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.04:43:50.66$vck44/valo=5,734.99 2006.257.04:43:50.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.04:43:50.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.04:43:50.66#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:50.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:50.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:50.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:50.66#ibcon#enter wrdev, iclass 19, count 0 2006.257.04:43:50.66#ibcon#first serial, iclass 19, count 0 2006.257.04:43:50.66#ibcon#enter sib2, iclass 19, count 0 2006.257.04:43:50.66#ibcon#flushed, iclass 19, count 0 2006.257.04:43:50.66#ibcon#about to write, iclass 19, count 0 2006.257.04:43:50.66#ibcon#wrote, iclass 19, count 0 2006.257.04:43:50.66#ibcon#about to read 3, iclass 19, count 0 2006.257.04:43:50.68#ibcon#read 3, iclass 19, count 0 2006.257.04:43:50.68#ibcon#about to read 4, iclass 19, count 0 2006.257.04:43:50.68#ibcon#read 4, iclass 19, count 0 2006.257.04:43:50.68#ibcon#about to read 5, iclass 19, count 0 2006.257.04:43:50.68#ibcon#read 5, iclass 19, count 0 2006.257.04:43:50.68#ibcon#about to read 6, iclass 19, count 0 2006.257.04:43:50.68#ibcon#read 6, iclass 19, count 0 2006.257.04:43:50.68#ibcon#end of sib2, iclass 19, count 0 2006.257.04:43:50.68#ibcon#*mode == 0, iclass 19, count 0 2006.257.04:43:50.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.04:43:50.68#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.04:43:50.68#ibcon#*before write, iclass 19, count 0 2006.257.04:43:50.68#ibcon#enter sib2, iclass 19, count 0 2006.257.04:43:50.68#ibcon#flushed, iclass 19, count 0 2006.257.04:43:50.68#ibcon#about to write, iclass 19, count 0 2006.257.04:43:50.68#ibcon#wrote, iclass 19, count 0 2006.257.04:43:50.68#ibcon#about to read 3, iclass 19, count 0 2006.257.04:43:50.72#ibcon#read 3, iclass 19, count 0 2006.257.04:43:50.72#ibcon#about to read 4, iclass 19, count 0 2006.257.04:43:50.72#ibcon#read 4, iclass 19, count 0 2006.257.04:43:50.72#ibcon#about to read 5, iclass 19, count 0 2006.257.04:43:50.72#ibcon#read 5, iclass 19, count 0 2006.257.04:43:50.72#ibcon#about to read 6, iclass 19, count 0 2006.257.04:43:50.72#ibcon#read 6, iclass 19, count 0 2006.257.04:43:50.72#ibcon#end of sib2, iclass 19, count 0 2006.257.04:43:50.72#ibcon#*after write, iclass 19, count 0 2006.257.04:43:50.72#ibcon#*before return 0, iclass 19, count 0 2006.257.04:43:50.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:50.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:50.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.04:43:50.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.04:43:50.72$vck44/va=5,4 2006.257.04:43:50.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.04:43:50.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.04:43:50.72#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:50.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:50.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:50.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:50.78#ibcon#enter wrdev, iclass 21, count 2 2006.257.04:43:50.78#ibcon#first serial, iclass 21, count 2 2006.257.04:43:50.78#ibcon#enter sib2, iclass 21, count 2 2006.257.04:43:50.78#ibcon#flushed, iclass 21, count 2 2006.257.04:43:50.78#ibcon#about to write, iclass 21, count 2 2006.257.04:43:50.78#ibcon#wrote, iclass 21, count 2 2006.257.04:43:50.78#ibcon#about to read 3, iclass 21, count 2 2006.257.04:43:50.80#ibcon#read 3, iclass 21, count 2 2006.257.04:43:50.80#ibcon#about to read 4, iclass 21, count 2 2006.257.04:43:50.80#ibcon#read 4, iclass 21, count 2 2006.257.04:43:50.80#ibcon#about to read 5, iclass 21, count 2 2006.257.04:43:50.80#ibcon#read 5, iclass 21, count 2 2006.257.04:43:50.80#ibcon#about to read 6, iclass 21, count 2 2006.257.04:43:50.80#ibcon#read 6, iclass 21, count 2 2006.257.04:43:50.80#ibcon#end of sib2, iclass 21, count 2 2006.257.04:43:50.80#ibcon#*mode == 0, iclass 21, count 2 2006.257.04:43:50.80#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.04:43:50.80#ibcon#[25=AT05-04\r\n] 2006.257.04:43:50.80#ibcon#*before write, iclass 21, count 2 2006.257.04:43:50.80#ibcon#enter sib2, iclass 21, count 2 2006.257.04:43:50.80#ibcon#flushed, iclass 21, count 2 2006.257.04:43:50.80#ibcon#about to write, iclass 21, count 2 2006.257.04:43:50.80#ibcon#wrote, iclass 21, count 2 2006.257.04:43:50.80#ibcon#about to read 3, iclass 21, count 2 2006.257.04:43:50.83#ibcon#read 3, iclass 21, count 2 2006.257.04:43:50.83#ibcon#about to read 4, iclass 21, count 2 2006.257.04:43:50.83#ibcon#read 4, iclass 21, count 2 2006.257.04:43:50.83#ibcon#about to read 5, iclass 21, count 2 2006.257.04:43:50.83#ibcon#read 5, iclass 21, count 2 2006.257.04:43:50.83#ibcon#about to read 6, iclass 21, count 2 2006.257.04:43:50.83#ibcon#read 6, iclass 21, count 2 2006.257.04:43:50.83#ibcon#end of sib2, iclass 21, count 2 2006.257.04:43:50.83#ibcon#*after write, iclass 21, count 2 2006.257.04:43:50.83#ibcon#*before return 0, iclass 21, count 2 2006.257.04:43:50.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:50.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:50.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.04:43:50.83#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:50.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:50.95#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:50.95#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:50.95#ibcon#enter wrdev, iclass 21, count 0 2006.257.04:43:50.95#ibcon#first serial, iclass 21, count 0 2006.257.04:43:50.95#ibcon#enter sib2, iclass 21, count 0 2006.257.04:43:50.95#ibcon#flushed, iclass 21, count 0 2006.257.04:43:50.95#ibcon#about to write, iclass 21, count 0 2006.257.04:43:50.95#ibcon#wrote, iclass 21, count 0 2006.257.04:43:50.95#ibcon#about to read 3, iclass 21, count 0 2006.257.04:43:50.97#ibcon#read 3, iclass 21, count 0 2006.257.04:43:50.97#ibcon#about to read 4, iclass 21, count 0 2006.257.04:43:50.97#ibcon#read 4, iclass 21, count 0 2006.257.04:43:50.97#ibcon#about to read 5, iclass 21, count 0 2006.257.04:43:50.97#ibcon#read 5, iclass 21, count 0 2006.257.04:43:50.97#ibcon#about to read 6, iclass 21, count 0 2006.257.04:43:50.97#ibcon#read 6, iclass 21, count 0 2006.257.04:43:50.97#ibcon#end of sib2, iclass 21, count 0 2006.257.04:43:50.97#ibcon#*mode == 0, iclass 21, count 0 2006.257.04:43:50.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.04:43:50.97#ibcon#[25=USB\r\n] 2006.257.04:43:50.97#ibcon#*before write, iclass 21, count 0 2006.257.04:43:50.97#ibcon#enter sib2, iclass 21, count 0 2006.257.04:43:50.97#ibcon#flushed, iclass 21, count 0 2006.257.04:43:50.97#ibcon#about to write, iclass 21, count 0 2006.257.04:43:50.97#ibcon#wrote, iclass 21, count 0 2006.257.04:43:50.97#ibcon#about to read 3, iclass 21, count 0 2006.257.04:43:51.00#ibcon#read 3, iclass 21, count 0 2006.257.04:43:51.00#ibcon#about to read 4, iclass 21, count 0 2006.257.04:43:51.00#ibcon#read 4, iclass 21, count 0 2006.257.04:43:51.00#ibcon#about to read 5, iclass 21, count 0 2006.257.04:43:51.00#ibcon#read 5, iclass 21, count 0 2006.257.04:43:51.00#ibcon#about to read 6, iclass 21, count 0 2006.257.04:43:51.00#ibcon#read 6, iclass 21, count 0 2006.257.04:43:51.00#ibcon#end of sib2, iclass 21, count 0 2006.257.04:43:51.00#ibcon#*after write, iclass 21, count 0 2006.257.04:43:51.00#ibcon#*before return 0, iclass 21, count 0 2006.257.04:43:51.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:51.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:51.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.04:43:51.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.04:43:51.00$vck44/valo=6,814.99 2006.257.04:43:51.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.04:43:51.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.04:43:51.00#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:51.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:51.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:51.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:51.00#ibcon#enter wrdev, iclass 23, count 0 2006.257.04:43:51.00#ibcon#first serial, iclass 23, count 0 2006.257.04:43:51.00#ibcon#enter sib2, iclass 23, count 0 2006.257.04:43:51.00#ibcon#flushed, iclass 23, count 0 2006.257.04:43:51.00#ibcon#about to write, iclass 23, count 0 2006.257.04:43:51.00#ibcon#wrote, iclass 23, count 0 2006.257.04:43:51.00#ibcon#about to read 3, iclass 23, count 0 2006.257.04:43:51.02#ibcon#read 3, iclass 23, count 0 2006.257.04:43:51.02#ibcon#about to read 4, iclass 23, count 0 2006.257.04:43:51.02#ibcon#read 4, iclass 23, count 0 2006.257.04:43:51.02#ibcon#about to read 5, iclass 23, count 0 2006.257.04:43:51.02#ibcon#read 5, iclass 23, count 0 2006.257.04:43:51.02#ibcon#about to read 6, iclass 23, count 0 2006.257.04:43:51.02#ibcon#read 6, iclass 23, count 0 2006.257.04:43:51.02#ibcon#end of sib2, iclass 23, count 0 2006.257.04:43:51.02#ibcon#*mode == 0, iclass 23, count 0 2006.257.04:43:51.02#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.04:43:51.02#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.04:43:51.02#ibcon#*before write, iclass 23, count 0 2006.257.04:43:51.02#ibcon#enter sib2, iclass 23, count 0 2006.257.04:43:51.02#ibcon#flushed, iclass 23, count 0 2006.257.04:43:51.02#ibcon#about to write, iclass 23, count 0 2006.257.04:43:51.02#ibcon#wrote, iclass 23, count 0 2006.257.04:43:51.02#ibcon#about to read 3, iclass 23, count 0 2006.257.04:43:51.06#ibcon#read 3, iclass 23, count 0 2006.257.04:43:51.06#ibcon#about to read 4, iclass 23, count 0 2006.257.04:43:51.06#ibcon#read 4, iclass 23, count 0 2006.257.04:43:51.06#ibcon#about to read 5, iclass 23, count 0 2006.257.04:43:51.06#ibcon#read 5, iclass 23, count 0 2006.257.04:43:51.06#ibcon#about to read 6, iclass 23, count 0 2006.257.04:43:51.06#ibcon#read 6, iclass 23, count 0 2006.257.04:43:51.06#ibcon#end of sib2, iclass 23, count 0 2006.257.04:43:51.06#ibcon#*after write, iclass 23, count 0 2006.257.04:43:51.06#ibcon#*before return 0, iclass 23, count 0 2006.257.04:43:51.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:51.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:51.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.04:43:51.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.04:43:51.06$vck44/va=6,4 2006.257.04:43:51.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.04:43:51.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.04:43:51.06#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:51.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:51.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:51.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:51.12#ibcon#enter wrdev, iclass 25, count 2 2006.257.04:43:51.12#ibcon#first serial, iclass 25, count 2 2006.257.04:43:51.12#ibcon#enter sib2, iclass 25, count 2 2006.257.04:43:51.12#ibcon#flushed, iclass 25, count 2 2006.257.04:43:51.12#ibcon#about to write, iclass 25, count 2 2006.257.04:43:51.12#ibcon#wrote, iclass 25, count 2 2006.257.04:43:51.12#ibcon#about to read 3, iclass 25, count 2 2006.257.04:43:51.14#ibcon#read 3, iclass 25, count 2 2006.257.04:43:51.14#ibcon#about to read 4, iclass 25, count 2 2006.257.04:43:51.14#ibcon#read 4, iclass 25, count 2 2006.257.04:43:51.14#ibcon#about to read 5, iclass 25, count 2 2006.257.04:43:51.14#ibcon#read 5, iclass 25, count 2 2006.257.04:43:51.14#ibcon#about to read 6, iclass 25, count 2 2006.257.04:43:51.14#ibcon#read 6, iclass 25, count 2 2006.257.04:43:51.14#ibcon#end of sib2, iclass 25, count 2 2006.257.04:43:51.14#ibcon#*mode == 0, iclass 25, count 2 2006.257.04:43:51.14#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.04:43:51.14#ibcon#[25=AT06-04\r\n] 2006.257.04:43:51.14#ibcon#*before write, iclass 25, count 2 2006.257.04:43:51.14#ibcon#enter sib2, iclass 25, count 2 2006.257.04:43:51.14#ibcon#flushed, iclass 25, count 2 2006.257.04:43:51.14#ibcon#about to write, iclass 25, count 2 2006.257.04:43:51.14#ibcon#wrote, iclass 25, count 2 2006.257.04:43:51.14#ibcon#about to read 3, iclass 25, count 2 2006.257.04:43:51.17#ibcon#read 3, iclass 25, count 2 2006.257.04:43:51.17#ibcon#about to read 4, iclass 25, count 2 2006.257.04:43:51.17#ibcon#read 4, iclass 25, count 2 2006.257.04:43:51.17#ibcon#about to read 5, iclass 25, count 2 2006.257.04:43:51.17#ibcon#read 5, iclass 25, count 2 2006.257.04:43:51.17#ibcon#about to read 6, iclass 25, count 2 2006.257.04:43:51.17#ibcon#read 6, iclass 25, count 2 2006.257.04:43:51.17#ibcon#end of sib2, iclass 25, count 2 2006.257.04:43:51.17#ibcon#*after write, iclass 25, count 2 2006.257.04:43:51.17#ibcon#*before return 0, iclass 25, count 2 2006.257.04:43:51.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:51.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:51.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.04:43:51.17#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:51.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:51.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:51.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:51.29#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:43:51.29#ibcon#first serial, iclass 25, count 0 2006.257.04:43:51.29#ibcon#enter sib2, iclass 25, count 0 2006.257.04:43:51.29#ibcon#flushed, iclass 25, count 0 2006.257.04:43:51.29#ibcon#about to write, iclass 25, count 0 2006.257.04:43:51.29#ibcon#wrote, iclass 25, count 0 2006.257.04:43:51.29#ibcon#about to read 3, iclass 25, count 0 2006.257.04:43:51.31#ibcon#read 3, iclass 25, count 0 2006.257.04:43:51.31#ibcon#about to read 4, iclass 25, count 0 2006.257.04:43:51.31#ibcon#read 4, iclass 25, count 0 2006.257.04:43:51.31#ibcon#about to read 5, iclass 25, count 0 2006.257.04:43:51.31#ibcon#read 5, iclass 25, count 0 2006.257.04:43:51.31#ibcon#about to read 6, iclass 25, count 0 2006.257.04:43:51.31#ibcon#read 6, iclass 25, count 0 2006.257.04:43:51.31#ibcon#end of sib2, iclass 25, count 0 2006.257.04:43:51.31#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:43:51.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:43:51.31#ibcon#[25=USB\r\n] 2006.257.04:43:51.31#ibcon#*before write, iclass 25, count 0 2006.257.04:43:51.31#ibcon#enter sib2, iclass 25, count 0 2006.257.04:43:51.31#ibcon#flushed, iclass 25, count 0 2006.257.04:43:51.31#ibcon#about to write, iclass 25, count 0 2006.257.04:43:51.31#ibcon#wrote, iclass 25, count 0 2006.257.04:43:51.31#ibcon#about to read 3, iclass 25, count 0 2006.257.04:43:51.34#ibcon#read 3, iclass 25, count 0 2006.257.04:43:51.34#ibcon#about to read 4, iclass 25, count 0 2006.257.04:43:51.34#ibcon#read 4, iclass 25, count 0 2006.257.04:43:51.34#ibcon#about to read 5, iclass 25, count 0 2006.257.04:43:51.34#ibcon#read 5, iclass 25, count 0 2006.257.04:43:51.34#ibcon#about to read 6, iclass 25, count 0 2006.257.04:43:51.34#ibcon#read 6, iclass 25, count 0 2006.257.04:43:51.34#ibcon#end of sib2, iclass 25, count 0 2006.257.04:43:51.34#ibcon#*after write, iclass 25, count 0 2006.257.04:43:51.34#ibcon#*before return 0, iclass 25, count 0 2006.257.04:43:51.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:51.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:51.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:43:51.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:43:51.34$vck44/valo=7,864.99 2006.257.04:43:51.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.04:43:51.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.04:43:51.34#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:51.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:51.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:51.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:51.34#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:43:51.34#ibcon#first serial, iclass 27, count 0 2006.257.04:43:51.34#ibcon#enter sib2, iclass 27, count 0 2006.257.04:43:51.34#ibcon#flushed, iclass 27, count 0 2006.257.04:43:51.34#ibcon#about to write, iclass 27, count 0 2006.257.04:43:51.34#ibcon#wrote, iclass 27, count 0 2006.257.04:43:51.34#ibcon#about to read 3, iclass 27, count 0 2006.257.04:43:51.36#ibcon#read 3, iclass 27, count 0 2006.257.04:43:51.36#ibcon#about to read 4, iclass 27, count 0 2006.257.04:43:51.36#ibcon#read 4, iclass 27, count 0 2006.257.04:43:51.36#ibcon#about to read 5, iclass 27, count 0 2006.257.04:43:51.36#ibcon#read 5, iclass 27, count 0 2006.257.04:43:51.36#ibcon#about to read 6, iclass 27, count 0 2006.257.04:43:51.36#ibcon#read 6, iclass 27, count 0 2006.257.04:43:51.36#ibcon#end of sib2, iclass 27, count 0 2006.257.04:43:51.36#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:43:51.36#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:43:51.36#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.04:43:51.36#ibcon#*before write, iclass 27, count 0 2006.257.04:43:51.36#ibcon#enter sib2, iclass 27, count 0 2006.257.04:43:51.36#ibcon#flushed, iclass 27, count 0 2006.257.04:43:51.36#ibcon#about to write, iclass 27, count 0 2006.257.04:43:51.36#ibcon#wrote, iclass 27, count 0 2006.257.04:43:51.36#ibcon#about to read 3, iclass 27, count 0 2006.257.04:43:51.40#ibcon#read 3, iclass 27, count 0 2006.257.04:43:51.40#ibcon#about to read 4, iclass 27, count 0 2006.257.04:43:51.40#ibcon#read 4, iclass 27, count 0 2006.257.04:43:51.40#ibcon#about to read 5, iclass 27, count 0 2006.257.04:43:51.40#ibcon#read 5, iclass 27, count 0 2006.257.04:43:51.40#ibcon#about to read 6, iclass 27, count 0 2006.257.04:43:51.40#ibcon#read 6, iclass 27, count 0 2006.257.04:43:51.40#ibcon#end of sib2, iclass 27, count 0 2006.257.04:43:51.40#ibcon#*after write, iclass 27, count 0 2006.257.04:43:51.40#ibcon#*before return 0, iclass 27, count 0 2006.257.04:43:51.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:51.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:51.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:43:51.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:43:51.40$vck44/va=7,4 2006.257.04:43:51.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.04:43:51.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.04:43:51.40#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:51.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:51.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:51.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:51.46#ibcon#enter wrdev, iclass 29, count 2 2006.257.04:43:51.46#ibcon#first serial, iclass 29, count 2 2006.257.04:43:51.46#ibcon#enter sib2, iclass 29, count 2 2006.257.04:43:51.46#ibcon#flushed, iclass 29, count 2 2006.257.04:43:51.46#ibcon#about to write, iclass 29, count 2 2006.257.04:43:51.46#ibcon#wrote, iclass 29, count 2 2006.257.04:43:51.46#ibcon#about to read 3, iclass 29, count 2 2006.257.04:43:51.48#ibcon#read 3, iclass 29, count 2 2006.257.04:43:51.48#ibcon#about to read 4, iclass 29, count 2 2006.257.04:43:51.48#ibcon#read 4, iclass 29, count 2 2006.257.04:43:51.48#ibcon#about to read 5, iclass 29, count 2 2006.257.04:43:51.48#ibcon#read 5, iclass 29, count 2 2006.257.04:43:51.48#ibcon#about to read 6, iclass 29, count 2 2006.257.04:43:51.48#ibcon#read 6, iclass 29, count 2 2006.257.04:43:51.48#ibcon#end of sib2, iclass 29, count 2 2006.257.04:43:51.48#ibcon#*mode == 0, iclass 29, count 2 2006.257.04:43:51.48#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.04:43:51.48#ibcon#[25=AT07-04\r\n] 2006.257.04:43:51.48#ibcon#*before write, iclass 29, count 2 2006.257.04:43:51.48#ibcon#enter sib2, iclass 29, count 2 2006.257.04:43:51.48#ibcon#flushed, iclass 29, count 2 2006.257.04:43:51.48#ibcon#about to write, iclass 29, count 2 2006.257.04:43:51.48#ibcon#wrote, iclass 29, count 2 2006.257.04:43:51.48#ibcon#about to read 3, iclass 29, count 2 2006.257.04:43:51.51#ibcon#read 3, iclass 29, count 2 2006.257.04:43:51.51#ibcon#about to read 4, iclass 29, count 2 2006.257.04:43:51.51#ibcon#read 4, iclass 29, count 2 2006.257.04:43:51.51#ibcon#about to read 5, iclass 29, count 2 2006.257.04:43:51.51#ibcon#read 5, iclass 29, count 2 2006.257.04:43:51.51#ibcon#about to read 6, iclass 29, count 2 2006.257.04:43:51.51#ibcon#read 6, iclass 29, count 2 2006.257.04:43:51.51#ibcon#end of sib2, iclass 29, count 2 2006.257.04:43:51.51#ibcon#*after write, iclass 29, count 2 2006.257.04:43:51.51#ibcon#*before return 0, iclass 29, count 2 2006.257.04:43:51.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:51.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:51.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.04:43:51.51#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:51.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:51.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:51.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:51.63#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:43:51.63#ibcon#first serial, iclass 29, count 0 2006.257.04:43:51.63#ibcon#enter sib2, iclass 29, count 0 2006.257.04:43:51.63#ibcon#flushed, iclass 29, count 0 2006.257.04:43:51.63#ibcon#about to write, iclass 29, count 0 2006.257.04:43:51.63#ibcon#wrote, iclass 29, count 0 2006.257.04:43:51.63#ibcon#about to read 3, iclass 29, count 0 2006.257.04:43:51.65#ibcon#read 3, iclass 29, count 0 2006.257.04:43:51.65#ibcon#about to read 4, iclass 29, count 0 2006.257.04:43:51.65#ibcon#read 4, iclass 29, count 0 2006.257.04:43:51.65#ibcon#about to read 5, iclass 29, count 0 2006.257.04:43:51.65#ibcon#read 5, iclass 29, count 0 2006.257.04:43:51.65#ibcon#about to read 6, iclass 29, count 0 2006.257.04:43:51.65#ibcon#read 6, iclass 29, count 0 2006.257.04:43:51.65#ibcon#end of sib2, iclass 29, count 0 2006.257.04:43:51.65#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:43:51.65#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:43:51.65#ibcon#[25=USB\r\n] 2006.257.04:43:51.65#ibcon#*before write, iclass 29, count 0 2006.257.04:43:51.65#ibcon#enter sib2, iclass 29, count 0 2006.257.04:43:51.65#ibcon#flushed, iclass 29, count 0 2006.257.04:43:51.65#ibcon#about to write, iclass 29, count 0 2006.257.04:43:51.65#ibcon#wrote, iclass 29, count 0 2006.257.04:43:51.65#ibcon#about to read 3, iclass 29, count 0 2006.257.04:43:51.68#ibcon#read 3, iclass 29, count 0 2006.257.04:43:51.68#ibcon#about to read 4, iclass 29, count 0 2006.257.04:43:51.68#ibcon#read 4, iclass 29, count 0 2006.257.04:43:51.68#ibcon#about to read 5, iclass 29, count 0 2006.257.04:43:51.68#ibcon#read 5, iclass 29, count 0 2006.257.04:43:51.68#ibcon#about to read 6, iclass 29, count 0 2006.257.04:43:51.68#ibcon#read 6, iclass 29, count 0 2006.257.04:43:51.68#ibcon#end of sib2, iclass 29, count 0 2006.257.04:43:51.68#ibcon#*after write, iclass 29, count 0 2006.257.04:43:51.68#ibcon#*before return 0, iclass 29, count 0 2006.257.04:43:51.68#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:51.68#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:51.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:43:51.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:43:51.68$vck44/valo=8,884.99 2006.257.04:43:51.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.04:43:51.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.04:43:51.68#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:51.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:51.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:51.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:51.68#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:43:51.68#ibcon#first serial, iclass 31, count 0 2006.257.04:43:51.68#ibcon#enter sib2, iclass 31, count 0 2006.257.04:43:51.68#ibcon#flushed, iclass 31, count 0 2006.257.04:43:51.68#ibcon#about to write, iclass 31, count 0 2006.257.04:43:51.68#ibcon#wrote, iclass 31, count 0 2006.257.04:43:51.68#ibcon#about to read 3, iclass 31, count 0 2006.257.04:43:51.70#ibcon#read 3, iclass 31, count 0 2006.257.04:43:51.70#ibcon#about to read 4, iclass 31, count 0 2006.257.04:43:51.70#ibcon#read 4, iclass 31, count 0 2006.257.04:43:51.70#ibcon#about to read 5, iclass 31, count 0 2006.257.04:43:51.70#ibcon#read 5, iclass 31, count 0 2006.257.04:43:51.70#ibcon#about to read 6, iclass 31, count 0 2006.257.04:43:51.70#ibcon#read 6, iclass 31, count 0 2006.257.04:43:51.70#ibcon#end of sib2, iclass 31, count 0 2006.257.04:43:51.70#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:43:51.70#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:43:51.70#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.04:43:51.70#ibcon#*before write, iclass 31, count 0 2006.257.04:43:51.70#ibcon#enter sib2, iclass 31, count 0 2006.257.04:43:51.70#ibcon#flushed, iclass 31, count 0 2006.257.04:43:51.70#ibcon#about to write, iclass 31, count 0 2006.257.04:43:51.70#ibcon#wrote, iclass 31, count 0 2006.257.04:43:51.70#ibcon#about to read 3, iclass 31, count 0 2006.257.04:43:51.74#ibcon#read 3, iclass 31, count 0 2006.257.04:43:51.74#ibcon#about to read 4, iclass 31, count 0 2006.257.04:43:51.74#ibcon#read 4, iclass 31, count 0 2006.257.04:43:51.74#ibcon#about to read 5, iclass 31, count 0 2006.257.04:43:51.74#ibcon#read 5, iclass 31, count 0 2006.257.04:43:51.74#ibcon#about to read 6, iclass 31, count 0 2006.257.04:43:51.74#ibcon#read 6, iclass 31, count 0 2006.257.04:43:51.74#ibcon#end of sib2, iclass 31, count 0 2006.257.04:43:51.74#ibcon#*after write, iclass 31, count 0 2006.257.04:43:51.74#ibcon#*before return 0, iclass 31, count 0 2006.257.04:43:51.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:51.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:51.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:43:51.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:43:51.74$vck44/va=8,4 2006.257.04:43:51.74#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.04:43:51.74#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.04:43:51.74#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:51.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.04:43:51.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.04:43:51.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.04:43:51.80#ibcon#enter wrdev, iclass 33, count 2 2006.257.04:43:51.80#ibcon#first serial, iclass 33, count 2 2006.257.04:43:51.80#ibcon#enter sib2, iclass 33, count 2 2006.257.04:43:51.80#ibcon#flushed, iclass 33, count 2 2006.257.04:43:51.80#ibcon#about to write, iclass 33, count 2 2006.257.04:43:51.80#ibcon#wrote, iclass 33, count 2 2006.257.04:43:51.80#ibcon#about to read 3, iclass 33, count 2 2006.257.04:43:51.82#ibcon#read 3, iclass 33, count 2 2006.257.04:43:51.82#ibcon#about to read 4, iclass 33, count 2 2006.257.04:43:51.82#ibcon#read 4, iclass 33, count 2 2006.257.04:43:51.82#ibcon#about to read 5, iclass 33, count 2 2006.257.04:43:51.82#ibcon#read 5, iclass 33, count 2 2006.257.04:43:51.82#ibcon#about to read 6, iclass 33, count 2 2006.257.04:43:51.82#ibcon#read 6, iclass 33, count 2 2006.257.04:43:51.82#ibcon#end of sib2, iclass 33, count 2 2006.257.04:43:51.82#ibcon#*mode == 0, iclass 33, count 2 2006.257.04:43:51.82#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.04:43:51.82#ibcon#[25=AT08-04\r\n] 2006.257.04:43:51.82#ibcon#*before write, iclass 33, count 2 2006.257.04:43:51.82#ibcon#enter sib2, iclass 33, count 2 2006.257.04:43:51.82#ibcon#flushed, iclass 33, count 2 2006.257.04:43:51.82#ibcon#about to write, iclass 33, count 2 2006.257.04:43:51.82#ibcon#wrote, iclass 33, count 2 2006.257.04:43:51.82#ibcon#about to read 3, iclass 33, count 2 2006.257.04:43:51.85#ibcon#read 3, iclass 33, count 2 2006.257.04:43:51.85#ibcon#about to read 4, iclass 33, count 2 2006.257.04:43:51.85#ibcon#read 4, iclass 33, count 2 2006.257.04:43:51.85#ibcon#about to read 5, iclass 33, count 2 2006.257.04:43:51.85#ibcon#read 5, iclass 33, count 2 2006.257.04:43:51.85#ibcon#about to read 6, iclass 33, count 2 2006.257.04:43:51.85#ibcon#read 6, iclass 33, count 2 2006.257.04:43:51.85#ibcon#end of sib2, iclass 33, count 2 2006.257.04:43:51.85#ibcon#*after write, iclass 33, count 2 2006.257.04:43:51.85#ibcon#*before return 0, iclass 33, count 2 2006.257.04:43:51.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.04:43:51.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.04:43:51.85#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.04:43:51.85#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:51.85#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.04:43:51.97#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.04:43:51.97#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.04:43:51.97#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:43:51.97#ibcon#first serial, iclass 33, count 0 2006.257.04:43:51.97#ibcon#enter sib2, iclass 33, count 0 2006.257.04:43:51.97#ibcon#flushed, iclass 33, count 0 2006.257.04:43:51.97#ibcon#about to write, iclass 33, count 0 2006.257.04:43:51.97#ibcon#wrote, iclass 33, count 0 2006.257.04:43:51.97#ibcon#about to read 3, iclass 33, count 0 2006.257.04:43:51.99#ibcon#read 3, iclass 33, count 0 2006.257.04:43:51.99#ibcon#about to read 4, iclass 33, count 0 2006.257.04:43:51.99#ibcon#read 4, iclass 33, count 0 2006.257.04:43:51.99#ibcon#about to read 5, iclass 33, count 0 2006.257.04:43:51.99#ibcon#read 5, iclass 33, count 0 2006.257.04:43:51.99#ibcon#about to read 6, iclass 33, count 0 2006.257.04:43:51.99#ibcon#read 6, iclass 33, count 0 2006.257.04:43:51.99#ibcon#end of sib2, iclass 33, count 0 2006.257.04:43:51.99#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:43:51.99#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:43:51.99#ibcon#[25=USB\r\n] 2006.257.04:43:51.99#ibcon#*before write, iclass 33, count 0 2006.257.04:43:51.99#ibcon#enter sib2, iclass 33, count 0 2006.257.04:43:51.99#ibcon#flushed, iclass 33, count 0 2006.257.04:43:51.99#ibcon#about to write, iclass 33, count 0 2006.257.04:43:51.99#ibcon#wrote, iclass 33, count 0 2006.257.04:43:51.99#ibcon#about to read 3, iclass 33, count 0 2006.257.04:43:52.02#ibcon#read 3, iclass 33, count 0 2006.257.04:43:52.02#ibcon#about to read 4, iclass 33, count 0 2006.257.04:43:52.02#ibcon#read 4, iclass 33, count 0 2006.257.04:43:52.02#ibcon#about to read 5, iclass 33, count 0 2006.257.04:43:52.02#ibcon#read 5, iclass 33, count 0 2006.257.04:43:52.02#ibcon#about to read 6, iclass 33, count 0 2006.257.04:43:52.02#ibcon#read 6, iclass 33, count 0 2006.257.04:43:52.02#ibcon#end of sib2, iclass 33, count 0 2006.257.04:43:52.02#ibcon#*after write, iclass 33, count 0 2006.257.04:43:52.02#ibcon#*before return 0, iclass 33, count 0 2006.257.04:43:52.02#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.04:43:52.02#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.04:43:52.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:43:52.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:43:52.02$vck44/vblo=1,629.99 2006.257.04:43:52.02#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.04:43:52.02#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.04:43:52.02#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:52.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:43:52.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:43:52.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:43:52.02#ibcon#enter wrdev, iclass 35, count 0 2006.257.04:43:52.02#ibcon#first serial, iclass 35, count 0 2006.257.04:43:52.02#ibcon#enter sib2, iclass 35, count 0 2006.257.04:43:52.02#ibcon#flushed, iclass 35, count 0 2006.257.04:43:52.02#ibcon#about to write, iclass 35, count 0 2006.257.04:43:52.02#ibcon#wrote, iclass 35, count 0 2006.257.04:43:52.02#ibcon#about to read 3, iclass 35, count 0 2006.257.04:43:52.04#ibcon#read 3, iclass 35, count 0 2006.257.04:43:52.04#ibcon#about to read 4, iclass 35, count 0 2006.257.04:43:52.04#ibcon#read 4, iclass 35, count 0 2006.257.04:43:52.04#ibcon#about to read 5, iclass 35, count 0 2006.257.04:43:52.04#ibcon#read 5, iclass 35, count 0 2006.257.04:43:52.04#ibcon#about to read 6, iclass 35, count 0 2006.257.04:43:52.04#ibcon#read 6, iclass 35, count 0 2006.257.04:43:52.04#ibcon#end of sib2, iclass 35, count 0 2006.257.04:43:52.04#ibcon#*mode == 0, iclass 35, count 0 2006.257.04:43:52.04#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.04:43:52.04#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.04:43:52.04#ibcon#*before write, iclass 35, count 0 2006.257.04:43:52.04#ibcon#enter sib2, iclass 35, count 0 2006.257.04:43:52.04#ibcon#flushed, iclass 35, count 0 2006.257.04:43:52.04#ibcon#about to write, iclass 35, count 0 2006.257.04:43:52.04#ibcon#wrote, iclass 35, count 0 2006.257.04:43:52.04#ibcon#about to read 3, iclass 35, count 0 2006.257.04:43:52.08#ibcon#read 3, iclass 35, count 0 2006.257.04:43:52.08#ibcon#about to read 4, iclass 35, count 0 2006.257.04:43:52.08#ibcon#read 4, iclass 35, count 0 2006.257.04:43:52.08#ibcon#about to read 5, iclass 35, count 0 2006.257.04:43:52.08#ibcon#read 5, iclass 35, count 0 2006.257.04:43:52.08#ibcon#about to read 6, iclass 35, count 0 2006.257.04:43:52.08#ibcon#read 6, iclass 35, count 0 2006.257.04:43:52.08#ibcon#end of sib2, iclass 35, count 0 2006.257.04:43:52.08#ibcon#*after write, iclass 35, count 0 2006.257.04:43:52.08#ibcon#*before return 0, iclass 35, count 0 2006.257.04:43:52.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:43:52.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:43:52.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.04:43:52.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.04:43:52.08$vck44/vb=1,4 2006.257.04:43:52.08#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.04:43:52.08#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.04:43:52.08#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:52.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.04:43:52.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.04:43:52.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.04:43:52.08#ibcon#enter wrdev, iclass 37, count 2 2006.257.04:43:52.08#ibcon#first serial, iclass 37, count 2 2006.257.04:43:52.08#ibcon#enter sib2, iclass 37, count 2 2006.257.04:43:52.08#ibcon#flushed, iclass 37, count 2 2006.257.04:43:52.08#ibcon#about to write, iclass 37, count 2 2006.257.04:43:52.08#ibcon#wrote, iclass 37, count 2 2006.257.04:43:52.08#ibcon#about to read 3, iclass 37, count 2 2006.257.04:43:52.10#ibcon#read 3, iclass 37, count 2 2006.257.04:43:52.10#ibcon#about to read 4, iclass 37, count 2 2006.257.04:43:52.10#ibcon#read 4, iclass 37, count 2 2006.257.04:43:52.10#ibcon#about to read 5, iclass 37, count 2 2006.257.04:43:52.10#ibcon#read 5, iclass 37, count 2 2006.257.04:43:52.10#ibcon#about to read 6, iclass 37, count 2 2006.257.04:43:52.10#ibcon#read 6, iclass 37, count 2 2006.257.04:43:52.10#ibcon#end of sib2, iclass 37, count 2 2006.257.04:43:52.10#ibcon#*mode == 0, iclass 37, count 2 2006.257.04:43:52.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.04:43:52.10#ibcon#[27=AT01-04\r\n] 2006.257.04:43:52.10#ibcon#*before write, iclass 37, count 2 2006.257.04:43:52.10#ibcon#enter sib2, iclass 37, count 2 2006.257.04:43:52.10#ibcon#flushed, iclass 37, count 2 2006.257.04:43:52.10#ibcon#about to write, iclass 37, count 2 2006.257.04:43:52.10#ibcon#wrote, iclass 37, count 2 2006.257.04:43:52.10#ibcon#about to read 3, iclass 37, count 2 2006.257.04:43:52.13#ibcon#read 3, iclass 37, count 2 2006.257.04:43:52.13#ibcon#about to read 4, iclass 37, count 2 2006.257.04:43:52.13#ibcon#read 4, iclass 37, count 2 2006.257.04:43:52.13#ibcon#about to read 5, iclass 37, count 2 2006.257.04:43:52.13#ibcon#read 5, iclass 37, count 2 2006.257.04:43:52.13#ibcon#about to read 6, iclass 37, count 2 2006.257.04:43:52.13#ibcon#read 6, iclass 37, count 2 2006.257.04:43:52.13#ibcon#end of sib2, iclass 37, count 2 2006.257.04:43:52.13#ibcon#*after write, iclass 37, count 2 2006.257.04:43:52.13#ibcon#*before return 0, iclass 37, count 2 2006.257.04:43:52.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.04:43:52.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.04:43:52.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.04:43:52.13#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:52.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.04:43:52.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.04:43:52.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.04:43:52.25#ibcon#enter wrdev, iclass 37, count 0 2006.257.04:43:52.25#ibcon#first serial, iclass 37, count 0 2006.257.04:43:52.25#ibcon#enter sib2, iclass 37, count 0 2006.257.04:43:52.25#ibcon#flushed, iclass 37, count 0 2006.257.04:43:52.25#ibcon#about to write, iclass 37, count 0 2006.257.04:43:52.25#ibcon#wrote, iclass 37, count 0 2006.257.04:43:52.25#ibcon#about to read 3, iclass 37, count 0 2006.257.04:43:52.27#ibcon#read 3, iclass 37, count 0 2006.257.04:43:52.27#ibcon#about to read 4, iclass 37, count 0 2006.257.04:43:52.27#ibcon#read 4, iclass 37, count 0 2006.257.04:43:52.27#ibcon#about to read 5, iclass 37, count 0 2006.257.04:43:52.27#ibcon#read 5, iclass 37, count 0 2006.257.04:43:52.27#ibcon#about to read 6, iclass 37, count 0 2006.257.04:43:52.27#ibcon#read 6, iclass 37, count 0 2006.257.04:43:52.27#ibcon#end of sib2, iclass 37, count 0 2006.257.04:43:52.27#ibcon#*mode == 0, iclass 37, count 0 2006.257.04:43:52.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.04:43:52.27#ibcon#[27=USB\r\n] 2006.257.04:43:52.27#ibcon#*before write, iclass 37, count 0 2006.257.04:43:52.27#ibcon#enter sib2, iclass 37, count 0 2006.257.04:43:52.27#ibcon#flushed, iclass 37, count 0 2006.257.04:43:52.27#ibcon#about to write, iclass 37, count 0 2006.257.04:43:52.27#ibcon#wrote, iclass 37, count 0 2006.257.04:43:52.27#ibcon#about to read 3, iclass 37, count 0 2006.257.04:43:52.30#ibcon#read 3, iclass 37, count 0 2006.257.04:43:52.30#ibcon#about to read 4, iclass 37, count 0 2006.257.04:43:52.30#ibcon#read 4, iclass 37, count 0 2006.257.04:43:52.30#ibcon#about to read 5, iclass 37, count 0 2006.257.04:43:52.30#ibcon#read 5, iclass 37, count 0 2006.257.04:43:52.30#ibcon#about to read 6, iclass 37, count 0 2006.257.04:43:52.30#ibcon#read 6, iclass 37, count 0 2006.257.04:43:52.30#ibcon#end of sib2, iclass 37, count 0 2006.257.04:43:52.30#ibcon#*after write, iclass 37, count 0 2006.257.04:43:52.30#ibcon#*before return 0, iclass 37, count 0 2006.257.04:43:52.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.04:43:52.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.04:43:52.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.04:43:52.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.04:43:52.30$vck44/vblo=2,634.99 2006.257.04:43:52.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.04:43:52.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.04:43:52.30#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:52.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:52.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:52.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:52.30#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:43:52.30#ibcon#first serial, iclass 39, count 0 2006.257.04:43:52.30#ibcon#enter sib2, iclass 39, count 0 2006.257.04:43:52.30#ibcon#flushed, iclass 39, count 0 2006.257.04:43:52.30#ibcon#about to write, iclass 39, count 0 2006.257.04:43:52.30#ibcon#wrote, iclass 39, count 0 2006.257.04:43:52.30#ibcon#about to read 3, iclass 39, count 0 2006.257.04:43:52.32#ibcon#read 3, iclass 39, count 0 2006.257.04:43:52.32#ibcon#about to read 4, iclass 39, count 0 2006.257.04:43:52.32#ibcon#read 4, iclass 39, count 0 2006.257.04:43:52.32#ibcon#about to read 5, iclass 39, count 0 2006.257.04:43:52.32#ibcon#read 5, iclass 39, count 0 2006.257.04:43:52.32#ibcon#about to read 6, iclass 39, count 0 2006.257.04:43:52.32#ibcon#read 6, iclass 39, count 0 2006.257.04:43:52.32#ibcon#end of sib2, iclass 39, count 0 2006.257.04:43:52.32#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:43:52.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:43:52.32#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.04:43:52.32#ibcon#*before write, iclass 39, count 0 2006.257.04:43:52.32#ibcon#enter sib2, iclass 39, count 0 2006.257.04:43:52.32#ibcon#flushed, iclass 39, count 0 2006.257.04:43:52.32#ibcon#about to write, iclass 39, count 0 2006.257.04:43:52.32#ibcon#wrote, iclass 39, count 0 2006.257.04:43:52.32#ibcon#about to read 3, iclass 39, count 0 2006.257.04:43:52.36#ibcon#read 3, iclass 39, count 0 2006.257.04:43:52.36#ibcon#about to read 4, iclass 39, count 0 2006.257.04:43:52.36#ibcon#read 4, iclass 39, count 0 2006.257.04:43:52.36#ibcon#about to read 5, iclass 39, count 0 2006.257.04:43:52.36#ibcon#read 5, iclass 39, count 0 2006.257.04:43:52.36#ibcon#about to read 6, iclass 39, count 0 2006.257.04:43:52.36#ibcon#read 6, iclass 39, count 0 2006.257.04:43:52.36#ibcon#end of sib2, iclass 39, count 0 2006.257.04:43:52.36#ibcon#*after write, iclass 39, count 0 2006.257.04:43:52.36#ibcon#*before return 0, iclass 39, count 0 2006.257.04:43:52.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:52.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.04:43:52.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:43:52.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:43:52.36$vck44/vb=2,5 2006.257.04:43:52.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.04:43:52.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.04:43:52.36#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:52.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:52.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:52.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:52.42#ibcon#enter wrdev, iclass 3, count 2 2006.257.04:43:52.42#ibcon#first serial, iclass 3, count 2 2006.257.04:43:52.42#ibcon#enter sib2, iclass 3, count 2 2006.257.04:43:52.42#ibcon#flushed, iclass 3, count 2 2006.257.04:43:52.42#ibcon#about to write, iclass 3, count 2 2006.257.04:43:52.42#ibcon#wrote, iclass 3, count 2 2006.257.04:43:52.42#ibcon#about to read 3, iclass 3, count 2 2006.257.04:43:52.44#ibcon#read 3, iclass 3, count 2 2006.257.04:43:52.44#ibcon#about to read 4, iclass 3, count 2 2006.257.04:43:52.44#ibcon#read 4, iclass 3, count 2 2006.257.04:43:52.44#ibcon#about to read 5, iclass 3, count 2 2006.257.04:43:52.44#ibcon#read 5, iclass 3, count 2 2006.257.04:43:52.44#ibcon#about to read 6, iclass 3, count 2 2006.257.04:43:52.44#ibcon#read 6, iclass 3, count 2 2006.257.04:43:52.44#ibcon#end of sib2, iclass 3, count 2 2006.257.04:43:52.44#ibcon#*mode == 0, iclass 3, count 2 2006.257.04:43:52.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.04:43:52.44#ibcon#[27=AT02-05\r\n] 2006.257.04:43:52.44#ibcon#*before write, iclass 3, count 2 2006.257.04:43:52.44#ibcon#enter sib2, iclass 3, count 2 2006.257.04:43:52.44#ibcon#flushed, iclass 3, count 2 2006.257.04:43:52.44#ibcon#about to write, iclass 3, count 2 2006.257.04:43:52.44#ibcon#wrote, iclass 3, count 2 2006.257.04:43:52.44#ibcon#about to read 3, iclass 3, count 2 2006.257.04:43:52.47#ibcon#read 3, iclass 3, count 2 2006.257.04:43:52.47#ibcon#about to read 4, iclass 3, count 2 2006.257.04:43:52.47#ibcon#read 4, iclass 3, count 2 2006.257.04:43:52.47#ibcon#about to read 5, iclass 3, count 2 2006.257.04:43:52.47#ibcon#read 5, iclass 3, count 2 2006.257.04:43:52.47#ibcon#about to read 6, iclass 3, count 2 2006.257.04:43:52.47#ibcon#read 6, iclass 3, count 2 2006.257.04:43:52.47#ibcon#end of sib2, iclass 3, count 2 2006.257.04:43:52.47#ibcon#*after write, iclass 3, count 2 2006.257.04:43:52.47#ibcon#*before return 0, iclass 3, count 2 2006.257.04:43:52.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:52.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:43:52.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.04:43:52.47#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:52.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:52.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:52.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:52.59#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:43:52.59#ibcon#first serial, iclass 3, count 0 2006.257.04:43:52.59#ibcon#enter sib2, iclass 3, count 0 2006.257.04:43:52.59#ibcon#flushed, iclass 3, count 0 2006.257.04:43:52.59#ibcon#about to write, iclass 3, count 0 2006.257.04:43:52.59#ibcon#wrote, iclass 3, count 0 2006.257.04:43:52.59#ibcon#about to read 3, iclass 3, count 0 2006.257.04:43:52.61#ibcon#read 3, iclass 3, count 0 2006.257.04:43:52.61#ibcon#about to read 4, iclass 3, count 0 2006.257.04:43:52.61#ibcon#read 4, iclass 3, count 0 2006.257.04:43:52.61#ibcon#about to read 5, iclass 3, count 0 2006.257.04:43:52.61#ibcon#read 5, iclass 3, count 0 2006.257.04:43:52.61#ibcon#about to read 6, iclass 3, count 0 2006.257.04:43:52.61#ibcon#read 6, iclass 3, count 0 2006.257.04:43:52.61#ibcon#end of sib2, iclass 3, count 0 2006.257.04:43:52.61#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:43:52.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:43:52.61#ibcon#[27=USB\r\n] 2006.257.04:43:52.61#ibcon#*before write, iclass 3, count 0 2006.257.04:43:52.61#ibcon#enter sib2, iclass 3, count 0 2006.257.04:43:52.61#ibcon#flushed, iclass 3, count 0 2006.257.04:43:52.61#ibcon#about to write, iclass 3, count 0 2006.257.04:43:52.61#ibcon#wrote, iclass 3, count 0 2006.257.04:43:52.61#ibcon#about to read 3, iclass 3, count 0 2006.257.04:43:52.64#ibcon#read 3, iclass 3, count 0 2006.257.04:43:52.64#ibcon#about to read 4, iclass 3, count 0 2006.257.04:43:52.64#ibcon#read 4, iclass 3, count 0 2006.257.04:43:52.64#ibcon#about to read 5, iclass 3, count 0 2006.257.04:43:52.64#ibcon#read 5, iclass 3, count 0 2006.257.04:43:52.64#ibcon#about to read 6, iclass 3, count 0 2006.257.04:43:52.64#ibcon#read 6, iclass 3, count 0 2006.257.04:43:52.64#ibcon#end of sib2, iclass 3, count 0 2006.257.04:43:52.64#ibcon#*after write, iclass 3, count 0 2006.257.04:43:52.64#ibcon#*before return 0, iclass 3, count 0 2006.257.04:43:52.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:52.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:43:52.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:43:52.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:43:52.64$vck44/vblo=3,649.99 2006.257.04:43:52.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.04:43:52.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.04:43:52.64#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:52.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:52.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:52.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:52.64#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:43:52.64#ibcon#first serial, iclass 5, count 0 2006.257.04:43:52.64#ibcon#enter sib2, iclass 5, count 0 2006.257.04:43:52.64#ibcon#flushed, iclass 5, count 0 2006.257.04:43:52.64#ibcon#about to write, iclass 5, count 0 2006.257.04:43:52.64#ibcon#wrote, iclass 5, count 0 2006.257.04:43:52.64#ibcon#about to read 3, iclass 5, count 0 2006.257.04:43:52.66#ibcon#read 3, iclass 5, count 0 2006.257.04:43:52.66#ibcon#about to read 4, iclass 5, count 0 2006.257.04:43:52.66#ibcon#read 4, iclass 5, count 0 2006.257.04:43:52.66#ibcon#about to read 5, iclass 5, count 0 2006.257.04:43:52.66#ibcon#read 5, iclass 5, count 0 2006.257.04:43:52.66#ibcon#about to read 6, iclass 5, count 0 2006.257.04:43:52.66#ibcon#read 6, iclass 5, count 0 2006.257.04:43:52.66#ibcon#end of sib2, iclass 5, count 0 2006.257.04:43:52.66#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:43:52.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:43:52.66#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.04:43:52.66#ibcon#*before write, iclass 5, count 0 2006.257.04:43:52.66#ibcon#enter sib2, iclass 5, count 0 2006.257.04:43:52.66#ibcon#flushed, iclass 5, count 0 2006.257.04:43:52.66#ibcon#about to write, iclass 5, count 0 2006.257.04:43:52.66#ibcon#wrote, iclass 5, count 0 2006.257.04:43:52.66#ibcon#about to read 3, iclass 5, count 0 2006.257.04:43:52.70#ibcon#read 3, iclass 5, count 0 2006.257.04:43:52.70#ibcon#about to read 4, iclass 5, count 0 2006.257.04:43:52.70#ibcon#read 4, iclass 5, count 0 2006.257.04:43:52.70#ibcon#about to read 5, iclass 5, count 0 2006.257.04:43:52.70#ibcon#read 5, iclass 5, count 0 2006.257.04:43:52.70#ibcon#about to read 6, iclass 5, count 0 2006.257.04:43:52.70#ibcon#read 6, iclass 5, count 0 2006.257.04:43:52.70#ibcon#end of sib2, iclass 5, count 0 2006.257.04:43:52.70#ibcon#*after write, iclass 5, count 0 2006.257.04:43:52.70#ibcon#*before return 0, iclass 5, count 0 2006.257.04:43:52.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:52.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.04:43:52.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:43:52.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:43:52.70$vck44/vb=3,4 2006.257.04:43:52.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.04:43:52.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.04:43:52.70#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:52.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:52.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:52.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:52.76#ibcon#enter wrdev, iclass 7, count 2 2006.257.04:43:52.76#ibcon#first serial, iclass 7, count 2 2006.257.04:43:52.76#ibcon#enter sib2, iclass 7, count 2 2006.257.04:43:52.76#ibcon#flushed, iclass 7, count 2 2006.257.04:43:52.76#ibcon#about to write, iclass 7, count 2 2006.257.04:43:52.76#ibcon#wrote, iclass 7, count 2 2006.257.04:43:52.76#ibcon#about to read 3, iclass 7, count 2 2006.257.04:43:52.78#ibcon#read 3, iclass 7, count 2 2006.257.04:43:52.78#ibcon#about to read 4, iclass 7, count 2 2006.257.04:43:52.78#ibcon#read 4, iclass 7, count 2 2006.257.04:43:52.78#ibcon#about to read 5, iclass 7, count 2 2006.257.04:43:52.78#ibcon#read 5, iclass 7, count 2 2006.257.04:43:52.78#ibcon#about to read 6, iclass 7, count 2 2006.257.04:43:52.78#ibcon#read 6, iclass 7, count 2 2006.257.04:43:52.78#ibcon#end of sib2, iclass 7, count 2 2006.257.04:43:52.78#ibcon#*mode == 0, iclass 7, count 2 2006.257.04:43:52.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.04:43:52.78#ibcon#[27=AT03-04\r\n] 2006.257.04:43:52.78#ibcon#*before write, iclass 7, count 2 2006.257.04:43:52.78#ibcon#enter sib2, iclass 7, count 2 2006.257.04:43:52.78#ibcon#flushed, iclass 7, count 2 2006.257.04:43:52.78#ibcon#about to write, iclass 7, count 2 2006.257.04:43:52.78#ibcon#wrote, iclass 7, count 2 2006.257.04:43:52.78#ibcon#about to read 3, iclass 7, count 2 2006.257.04:43:52.81#ibcon#read 3, iclass 7, count 2 2006.257.04:43:52.81#ibcon#about to read 4, iclass 7, count 2 2006.257.04:43:52.81#ibcon#read 4, iclass 7, count 2 2006.257.04:43:52.81#ibcon#about to read 5, iclass 7, count 2 2006.257.04:43:52.81#ibcon#read 5, iclass 7, count 2 2006.257.04:43:52.81#ibcon#about to read 6, iclass 7, count 2 2006.257.04:43:52.81#ibcon#read 6, iclass 7, count 2 2006.257.04:43:52.81#ibcon#end of sib2, iclass 7, count 2 2006.257.04:43:52.81#ibcon#*after write, iclass 7, count 2 2006.257.04:43:52.81#ibcon#*before return 0, iclass 7, count 2 2006.257.04:43:52.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:52.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.04:43:52.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.04:43:52.81#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:52.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:52.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:52.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:52.93#ibcon#enter wrdev, iclass 7, count 0 2006.257.04:43:52.93#ibcon#first serial, iclass 7, count 0 2006.257.04:43:52.93#ibcon#enter sib2, iclass 7, count 0 2006.257.04:43:52.93#ibcon#flushed, iclass 7, count 0 2006.257.04:43:52.93#ibcon#about to write, iclass 7, count 0 2006.257.04:43:52.93#ibcon#wrote, iclass 7, count 0 2006.257.04:43:52.93#ibcon#about to read 3, iclass 7, count 0 2006.257.04:43:52.95#ibcon#read 3, iclass 7, count 0 2006.257.04:43:52.95#ibcon#about to read 4, iclass 7, count 0 2006.257.04:43:52.95#ibcon#read 4, iclass 7, count 0 2006.257.04:43:52.95#ibcon#about to read 5, iclass 7, count 0 2006.257.04:43:52.95#ibcon#read 5, iclass 7, count 0 2006.257.04:43:52.95#ibcon#about to read 6, iclass 7, count 0 2006.257.04:43:52.95#ibcon#read 6, iclass 7, count 0 2006.257.04:43:52.95#ibcon#end of sib2, iclass 7, count 0 2006.257.04:43:52.95#ibcon#*mode == 0, iclass 7, count 0 2006.257.04:43:52.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.04:43:52.95#ibcon#[27=USB\r\n] 2006.257.04:43:52.95#ibcon#*before write, iclass 7, count 0 2006.257.04:43:52.95#ibcon#enter sib2, iclass 7, count 0 2006.257.04:43:52.95#ibcon#flushed, iclass 7, count 0 2006.257.04:43:52.95#ibcon#about to write, iclass 7, count 0 2006.257.04:43:52.95#ibcon#wrote, iclass 7, count 0 2006.257.04:43:52.95#ibcon#about to read 3, iclass 7, count 0 2006.257.04:43:52.98#ibcon#read 3, iclass 7, count 0 2006.257.04:43:52.98#ibcon#about to read 4, iclass 7, count 0 2006.257.04:43:52.98#ibcon#read 4, iclass 7, count 0 2006.257.04:43:52.98#ibcon#about to read 5, iclass 7, count 0 2006.257.04:43:52.98#ibcon#read 5, iclass 7, count 0 2006.257.04:43:52.98#ibcon#about to read 6, iclass 7, count 0 2006.257.04:43:52.98#ibcon#read 6, iclass 7, count 0 2006.257.04:43:52.98#ibcon#end of sib2, iclass 7, count 0 2006.257.04:43:52.98#ibcon#*after write, iclass 7, count 0 2006.257.04:43:52.98#ibcon#*before return 0, iclass 7, count 0 2006.257.04:43:52.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:52.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.04:43:52.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.04:43:52.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.04:43:52.98$vck44/vblo=4,679.99 2006.257.04:43:52.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.04:43:52.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.04:43:52.98#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:52.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:52.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:52.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:52.98#ibcon#enter wrdev, iclass 11, count 0 2006.257.04:43:52.98#ibcon#first serial, iclass 11, count 0 2006.257.04:43:52.98#ibcon#enter sib2, iclass 11, count 0 2006.257.04:43:52.98#ibcon#flushed, iclass 11, count 0 2006.257.04:43:52.98#ibcon#about to write, iclass 11, count 0 2006.257.04:43:52.98#ibcon#wrote, iclass 11, count 0 2006.257.04:43:52.98#ibcon#about to read 3, iclass 11, count 0 2006.257.04:43:53.00#ibcon#read 3, iclass 11, count 0 2006.257.04:43:53.00#ibcon#about to read 4, iclass 11, count 0 2006.257.04:43:53.00#ibcon#read 4, iclass 11, count 0 2006.257.04:43:53.00#ibcon#about to read 5, iclass 11, count 0 2006.257.04:43:53.00#ibcon#read 5, iclass 11, count 0 2006.257.04:43:53.00#ibcon#about to read 6, iclass 11, count 0 2006.257.04:43:53.00#ibcon#read 6, iclass 11, count 0 2006.257.04:43:53.00#ibcon#end of sib2, iclass 11, count 0 2006.257.04:43:53.00#ibcon#*mode == 0, iclass 11, count 0 2006.257.04:43:53.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.04:43:53.00#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.04:43:53.00#ibcon#*before write, iclass 11, count 0 2006.257.04:43:53.00#ibcon#enter sib2, iclass 11, count 0 2006.257.04:43:53.00#ibcon#flushed, iclass 11, count 0 2006.257.04:43:53.00#ibcon#about to write, iclass 11, count 0 2006.257.04:43:53.00#ibcon#wrote, iclass 11, count 0 2006.257.04:43:53.00#ibcon#about to read 3, iclass 11, count 0 2006.257.04:43:53.04#ibcon#read 3, iclass 11, count 0 2006.257.04:43:53.04#ibcon#about to read 4, iclass 11, count 0 2006.257.04:43:53.04#ibcon#read 4, iclass 11, count 0 2006.257.04:43:53.04#ibcon#about to read 5, iclass 11, count 0 2006.257.04:43:53.04#ibcon#read 5, iclass 11, count 0 2006.257.04:43:53.04#ibcon#about to read 6, iclass 11, count 0 2006.257.04:43:53.04#ibcon#read 6, iclass 11, count 0 2006.257.04:43:53.04#ibcon#end of sib2, iclass 11, count 0 2006.257.04:43:53.04#ibcon#*after write, iclass 11, count 0 2006.257.04:43:53.04#ibcon#*before return 0, iclass 11, count 0 2006.257.04:43:53.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:53.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.04:43:53.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.04:43:53.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.04:43:53.04$vck44/vb=4,5 2006.257.04:43:53.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.04:43:53.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.04:43:53.04#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:53.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:53.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:53.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:53.10#ibcon#enter wrdev, iclass 13, count 2 2006.257.04:43:53.10#ibcon#first serial, iclass 13, count 2 2006.257.04:43:53.10#ibcon#enter sib2, iclass 13, count 2 2006.257.04:43:53.10#ibcon#flushed, iclass 13, count 2 2006.257.04:43:53.10#ibcon#about to write, iclass 13, count 2 2006.257.04:43:53.10#ibcon#wrote, iclass 13, count 2 2006.257.04:43:53.10#ibcon#about to read 3, iclass 13, count 2 2006.257.04:43:53.12#ibcon#read 3, iclass 13, count 2 2006.257.04:43:53.12#ibcon#about to read 4, iclass 13, count 2 2006.257.04:43:53.12#ibcon#read 4, iclass 13, count 2 2006.257.04:43:53.12#ibcon#about to read 5, iclass 13, count 2 2006.257.04:43:53.12#ibcon#read 5, iclass 13, count 2 2006.257.04:43:53.12#ibcon#about to read 6, iclass 13, count 2 2006.257.04:43:53.12#ibcon#read 6, iclass 13, count 2 2006.257.04:43:53.12#ibcon#end of sib2, iclass 13, count 2 2006.257.04:43:53.12#ibcon#*mode == 0, iclass 13, count 2 2006.257.04:43:53.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.04:43:53.12#ibcon#[27=AT04-05\r\n] 2006.257.04:43:53.12#ibcon#*before write, iclass 13, count 2 2006.257.04:43:53.12#ibcon#enter sib2, iclass 13, count 2 2006.257.04:43:53.12#ibcon#flushed, iclass 13, count 2 2006.257.04:43:53.12#ibcon#about to write, iclass 13, count 2 2006.257.04:43:53.12#ibcon#wrote, iclass 13, count 2 2006.257.04:43:53.12#ibcon#about to read 3, iclass 13, count 2 2006.257.04:43:53.15#ibcon#read 3, iclass 13, count 2 2006.257.04:43:53.15#ibcon#about to read 4, iclass 13, count 2 2006.257.04:43:53.15#ibcon#read 4, iclass 13, count 2 2006.257.04:43:53.15#ibcon#about to read 5, iclass 13, count 2 2006.257.04:43:53.15#ibcon#read 5, iclass 13, count 2 2006.257.04:43:53.15#ibcon#about to read 6, iclass 13, count 2 2006.257.04:43:53.15#ibcon#read 6, iclass 13, count 2 2006.257.04:43:53.15#ibcon#end of sib2, iclass 13, count 2 2006.257.04:43:53.15#ibcon#*after write, iclass 13, count 2 2006.257.04:43:53.15#ibcon#*before return 0, iclass 13, count 2 2006.257.04:43:53.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:53.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.04:43:53.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.04:43:53.15#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:53.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:53.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:53.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:53.27#ibcon#enter wrdev, iclass 13, count 0 2006.257.04:43:53.27#ibcon#first serial, iclass 13, count 0 2006.257.04:43:53.27#ibcon#enter sib2, iclass 13, count 0 2006.257.04:43:53.27#ibcon#flushed, iclass 13, count 0 2006.257.04:43:53.27#ibcon#about to write, iclass 13, count 0 2006.257.04:43:53.27#ibcon#wrote, iclass 13, count 0 2006.257.04:43:53.27#ibcon#about to read 3, iclass 13, count 0 2006.257.04:43:53.29#ibcon#read 3, iclass 13, count 0 2006.257.04:43:53.29#ibcon#about to read 4, iclass 13, count 0 2006.257.04:43:53.29#ibcon#read 4, iclass 13, count 0 2006.257.04:43:53.29#ibcon#about to read 5, iclass 13, count 0 2006.257.04:43:53.29#ibcon#read 5, iclass 13, count 0 2006.257.04:43:53.29#ibcon#about to read 6, iclass 13, count 0 2006.257.04:43:53.29#ibcon#read 6, iclass 13, count 0 2006.257.04:43:53.29#ibcon#end of sib2, iclass 13, count 0 2006.257.04:43:53.29#ibcon#*mode == 0, iclass 13, count 0 2006.257.04:43:53.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.04:43:53.29#ibcon#[27=USB\r\n] 2006.257.04:43:53.29#ibcon#*before write, iclass 13, count 0 2006.257.04:43:53.29#ibcon#enter sib2, iclass 13, count 0 2006.257.04:43:53.29#ibcon#flushed, iclass 13, count 0 2006.257.04:43:53.29#ibcon#about to write, iclass 13, count 0 2006.257.04:43:53.29#ibcon#wrote, iclass 13, count 0 2006.257.04:43:53.29#ibcon#about to read 3, iclass 13, count 0 2006.257.04:43:53.32#ibcon#read 3, iclass 13, count 0 2006.257.04:43:53.32#ibcon#about to read 4, iclass 13, count 0 2006.257.04:43:53.32#ibcon#read 4, iclass 13, count 0 2006.257.04:43:53.32#ibcon#about to read 5, iclass 13, count 0 2006.257.04:43:53.32#ibcon#read 5, iclass 13, count 0 2006.257.04:43:53.32#ibcon#about to read 6, iclass 13, count 0 2006.257.04:43:53.32#ibcon#read 6, iclass 13, count 0 2006.257.04:43:53.32#ibcon#end of sib2, iclass 13, count 0 2006.257.04:43:53.32#ibcon#*after write, iclass 13, count 0 2006.257.04:43:53.32#ibcon#*before return 0, iclass 13, count 0 2006.257.04:43:53.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:53.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.04:43:53.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.04:43:53.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.04:43:53.32$vck44/vblo=5,709.99 2006.257.04:43:53.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.04:43:53.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.04:43:53.32#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:53.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:53.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:53.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:53.32#ibcon#enter wrdev, iclass 15, count 0 2006.257.04:43:53.32#ibcon#first serial, iclass 15, count 0 2006.257.04:43:53.32#ibcon#enter sib2, iclass 15, count 0 2006.257.04:43:53.32#ibcon#flushed, iclass 15, count 0 2006.257.04:43:53.32#ibcon#about to write, iclass 15, count 0 2006.257.04:43:53.32#ibcon#wrote, iclass 15, count 0 2006.257.04:43:53.32#ibcon#about to read 3, iclass 15, count 0 2006.257.04:43:53.34#ibcon#read 3, iclass 15, count 0 2006.257.04:43:53.34#ibcon#about to read 4, iclass 15, count 0 2006.257.04:43:53.34#ibcon#read 4, iclass 15, count 0 2006.257.04:43:53.34#ibcon#about to read 5, iclass 15, count 0 2006.257.04:43:53.34#ibcon#read 5, iclass 15, count 0 2006.257.04:43:53.34#ibcon#about to read 6, iclass 15, count 0 2006.257.04:43:53.34#ibcon#read 6, iclass 15, count 0 2006.257.04:43:53.34#ibcon#end of sib2, iclass 15, count 0 2006.257.04:43:53.34#ibcon#*mode == 0, iclass 15, count 0 2006.257.04:43:53.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.04:43:53.34#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.04:43:53.34#ibcon#*before write, iclass 15, count 0 2006.257.04:43:53.34#ibcon#enter sib2, iclass 15, count 0 2006.257.04:43:53.34#ibcon#flushed, iclass 15, count 0 2006.257.04:43:53.34#ibcon#about to write, iclass 15, count 0 2006.257.04:43:53.34#ibcon#wrote, iclass 15, count 0 2006.257.04:43:53.34#ibcon#about to read 3, iclass 15, count 0 2006.257.04:43:53.38#ibcon#read 3, iclass 15, count 0 2006.257.04:43:53.38#ibcon#about to read 4, iclass 15, count 0 2006.257.04:43:53.38#ibcon#read 4, iclass 15, count 0 2006.257.04:43:53.38#ibcon#about to read 5, iclass 15, count 0 2006.257.04:43:53.38#ibcon#read 5, iclass 15, count 0 2006.257.04:43:53.38#ibcon#about to read 6, iclass 15, count 0 2006.257.04:43:53.38#ibcon#read 6, iclass 15, count 0 2006.257.04:43:53.38#ibcon#end of sib2, iclass 15, count 0 2006.257.04:43:53.38#ibcon#*after write, iclass 15, count 0 2006.257.04:43:53.38#ibcon#*before return 0, iclass 15, count 0 2006.257.04:43:53.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:53.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.04:43:53.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.04:43:53.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.04:43:53.38$vck44/vb=5,4 2006.257.04:43:53.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.04:43:53.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.04:43:53.38#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:53.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:53.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:53.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:53.44#ibcon#enter wrdev, iclass 17, count 2 2006.257.04:43:53.44#ibcon#first serial, iclass 17, count 2 2006.257.04:43:53.44#ibcon#enter sib2, iclass 17, count 2 2006.257.04:43:53.44#ibcon#flushed, iclass 17, count 2 2006.257.04:43:53.44#ibcon#about to write, iclass 17, count 2 2006.257.04:43:53.44#ibcon#wrote, iclass 17, count 2 2006.257.04:43:53.44#ibcon#about to read 3, iclass 17, count 2 2006.257.04:43:53.46#ibcon#read 3, iclass 17, count 2 2006.257.04:43:53.46#ibcon#about to read 4, iclass 17, count 2 2006.257.04:43:53.46#ibcon#read 4, iclass 17, count 2 2006.257.04:43:53.46#ibcon#about to read 5, iclass 17, count 2 2006.257.04:43:53.46#ibcon#read 5, iclass 17, count 2 2006.257.04:43:53.46#ibcon#about to read 6, iclass 17, count 2 2006.257.04:43:53.46#ibcon#read 6, iclass 17, count 2 2006.257.04:43:53.46#ibcon#end of sib2, iclass 17, count 2 2006.257.04:43:53.46#ibcon#*mode == 0, iclass 17, count 2 2006.257.04:43:53.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.04:43:53.46#ibcon#[27=AT05-04\r\n] 2006.257.04:43:53.46#ibcon#*before write, iclass 17, count 2 2006.257.04:43:53.46#ibcon#enter sib2, iclass 17, count 2 2006.257.04:43:53.46#ibcon#flushed, iclass 17, count 2 2006.257.04:43:53.46#ibcon#about to write, iclass 17, count 2 2006.257.04:43:53.46#ibcon#wrote, iclass 17, count 2 2006.257.04:43:53.46#ibcon#about to read 3, iclass 17, count 2 2006.257.04:43:53.49#ibcon#read 3, iclass 17, count 2 2006.257.04:43:53.49#ibcon#about to read 4, iclass 17, count 2 2006.257.04:43:53.49#ibcon#read 4, iclass 17, count 2 2006.257.04:43:53.49#ibcon#about to read 5, iclass 17, count 2 2006.257.04:43:53.49#ibcon#read 5, iclass 17, count 2 2006.257.04:43:53.49#ibcon#about to read 6, iclass 17, count 2 2006.257.04:43:53.49#ibcon#read 6, iclass 17, count 2 2006.257.04:43:53.49#ibcon#end of sib2, iclass 17, count 2 2006.257.04:43:53.49#ibcon#*after write, iclass 17, count 2 2006.257.04:43:53.49#ibcon#*before return 0, iclass 17, count 2 2006.257.04:43:53.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:53.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.04:43:53.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.04:43:53.49#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:53.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:53.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:53.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:53.61#ibcon#enter wrdev, iclass 17, count 0 2006.257.04:43:53.61#ibcon#first serial, iclass 17, count 0 2006.257.04:43:53.61#ibcon#enter sib2, iclass 17, count 0 2006.257.04:43:53.61#ibcon#flushed, iclass 17, count 0 2006.257.04:43:53.61#ibcon#about to write, iclass 17, count 0 2006.257.04:43:53.61#ibcon#wrote, iclass 17, count 0 2006.257.04:43:53.61#ibcon#about to read 3, iclass 17, count 0 2006.257.04:43:53.63#ibcon#read 3, iclass 17, count 0 2006.257.04:43:53.63#ibcon#about to read 4, iclass 17, count 0 2006.257.04:43:53.63#ibcon#read 4, iclass 17, count 0 2006.257.04:43:53.63#ibcon#about to read 5, iclass 17, count 0 2006.257.04:43:53.63#ibcon#read 5, iclass 17, count 0 2006.257.04:43:53.63#ibcon#about to read 6, iclass 17, count 0 2006.257.04:43:53.63#ibcon#read 6, iclass 17, count 0 2006.257.04:43:53.63#ibcon#end of sib2, iclass 17, count 0 2006.257.04:43:53.63#ibcon#*mode == 0, iclass 17, count 0 2006.257.04:43:53.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.04:43:53.63#ibcon#[27=USB\r\n] 2006.257.04:43:53.63#ibcon#*before write, iclass 17, count 0 2006.257.04:43:53.63#ibcon#enter sib2, iclass 17, count 0 2006.257.04:43:53.63#ibcon#flushed, iclass 17, count 0 2006.257.04:43:53.63#ibcon#about to write, iclass 17, count 0 2006.257.04:43:53.63#ibcon#wrote, iclass 17, count 0 2006.257.04:43:53.63#ibcon#about to read 3, iclass 17, count 0 2006.257.04:43:53.66#ibcon#read 3, iclass 17, count 0 2006.257.04:43:53.66#ibcon#about to read 4, iclass 17, count 0 2006.257.04:43:53.66#ibcon#read 4, iclass 17, count 0 2006.257.04:43:53.66#ibcon#about to read 5, iclass 17, count 0 2006.257.04:43:53.66#ibcon#read 5, iclass 17, count 0 2006.257.04:43:53.66#ibcon#about to read 6, iclass 17, count 0 2006.257.04:43:53.66#ibcon#read 6, iclass 17, count 0 2006.257.04:43:53.66#ibcon#end of sib2, iclass 17, count 0 2006.257.04:43:53.66#ibcon#*after write, iclass 17, count 0 2006.257.04:43:53.66#ibcon#*before return 0, iclass 17, count 0 2006.257.04:43:53.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:53.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.04:43:53.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.04:43:53.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.04:43:53.66$vck44/vblo=6,719.99 2006.257.04:43:53.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.04:43:53.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.04:43:53.66#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:53.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:53.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:53.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:53.66#ibcon#enter wrdev, iclass 19, count 0 2006.257.04:43:53.66#ibcon#first serial, iclass 19, count 0 2006.257.04:43:53.66#ibcon#enter sib2, iclass 19, count 0 2006.257.04:43:53.66#ibcon#flushed, iclass 19, count 0 2006.257.04:43:53.66#ibcon#about to write, iclass 19, count 0 2006.257.04:43:53.66#ibcon#wrote, iclass 19, count 0 2006.257.04:43:53.66#ibcon#about to read 3, iclass 19, count 0 2006.257.04:43:53.68#ibcon#read 3, iclass 19, count 0 2006.257.04:43:53.68#ibcon#about to read 4, iclass 19, count 0 2006.257.04:43:53.68#ibcon#read 4, iclass 19, count 0 2006.257.04:43:53.68#ibcon#about to read 5, iclass 19, count 0 2006.257.04:43:53.68#ibcon#read 5, iclass 19, count 0 2006.257.04:43:53.68#ibcon#about to read 6, iclass 19, count 0 2006.257.04:43:53.68#ibcon#read 6, iclass 19, count 0 2006.257.04:43:53.68#ibcon#end of sib2, iclass 19, count 0 2006.257.04:43:53.68#ibcon#*mode == 0, iclass 19, count 0 2006.257.04:43:53.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.04:43:53.68#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.04:43:53.68#ibcon#*before write, iclass 19, count 0 2006.257.04:43:53.68#ibcon#enter sib2, iclass 19, count 0 2006.257.04:43:53.68#ibcon#flushed, iclass 19, count 0 2006.257.04:43:53.68#ibcon#about to write, iclass 19, count 0 2006.257.04:43:53.68#ibcon#wrote, iclass 19, count 0 2006.257.04:43:53.68#ibcon#about to read 3, iclass 19, count 0 2006.257.04:43:53.72#ibcon#read 3, iclass 19, count 0 2006.257.04:43:53.72#ibcon#about to read 4, iclass 19, count 0 2006.257.04:43:53.72#ibcon#read 4, iclass 19, count 0 2006.257.04:43:53.72#ibcon#about to read 5, iclass 19, count 0 2006.257.04:43:53.72#ibcon#read 5, iclass 19, count 0 2006.257.04:43:53.72#ibcon#about to read 6, iclass 19, count 0 2006.257.04:43:53.72#ibcon#read 6, iclass 19, count 0 2006.257.04:43:53.72#ibcon#end of sib2, iclass 19, count 0 2006.257.04:43:53.72#ibcon#*after write, iclass 19, count 0 2006.257.04:43:53.72#ibcon#*before return 0, iclass 19, count 0 2006.257.04:43:53.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:53.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.04:43:53.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.04:43:53.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.04:43:53.72$vck44/vb=6,4 2006.257.04:43:53.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.04:43:53.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.04:43:53.72#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:53.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:53.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:53.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:53.78#ibcon#enter wrdev, iclass 21, count 2 2006.257.04:43:53.78#ibcon#first serial, iclass 21, count 2 2006.257.04:43:53.78#ibcon#enter sib2, iclass 21, count 2 2006.257.04:43:53.78#ibcon#flushed, iclass 21, count 2 2006.257.04:43:53.78#ibcon#about to write, iclass 21, count 2 2006.257.04:43:53.78#ibcon#wrote, iclass 21, count 2 2006.257.04:43:53.78#ibcon#about to read 3, iclass 21, count 2 2006.257.04:43:53.80#ibcon#read 3, iclass 21, count 2 2006.257.04:43:53.80#ibcon#about to read 4, iclass 21, count 2 2006.257.04:43:53.80#ibcon#read 4, iclass 21, count 2 2006.257.04:43:53.80#ibcon#about to read 5, iclass 21, count 2 2006.257.04:43:53.80#ibcon#read 5, iclass 21, count 2 2006.257.04:43:53.80#ibcon#about to read 6, iclass 21, count 2 2006.257.04:43:53.80#ibcon#read 6, iclass 21, count 2 2006.257.04:43:53.80#ibcon#end of sib2, iclass 21, count 2 2006.257.04:43:53.80#ibcon#*mode == 0, iclass 21, count 2 2006.257.04:43:53.80#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.04:43:53.80#ibcon#[27=AT06-04\r\n] 2006.257.04:43:53.80#ibcon#*before write, iclass 21, count 2 2006.257.04:43:53.80#ibcon#enter sib2, iclass 21, count 2 2006.257.04:43:53.80#ibcon#flushed, iclass 21, count 2 2006.257.04:43:53.80#ibcon#about to write, iclass 21, count 2 2006.257.04:43:53.80#ibcon#wrote, iclass 21, count 2 2006.257.04:43:53.80#ibcon#about to read 3, iclass 21, count 2 2006.257.04:43:53.83#ibcon#read 3, iclass 21, count 2 2006.257.04:43:53.83#ibcon#about to read 4, iclass 21, count 2 2006.257.04:43:53.83#ibcon#read 4, iclass 21, count 2 2006.257.04:43:53.83#ibcon#about to read 5, iclass 21, count 2 2006.257.04:43:53.83#ibcon#read 5, iclass 21, count 2 2006.257.04:43:53.83#ibcon#about to read 6, iclass 21, count 2 2006.257.04:43:53.83#ibcon#read 6, iclass 21, count 2 2006.257.04:43:53.83#ibcon#end of sib2, iclass 21, count 2 2006.257.04:43:53.83#ibcon#*after write, iclass 21, count 2 2006.257.04:43:53.83#ibcon#*before return 0, iclass 21, count 2 2006.257.04:43:53.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:53.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.04:43:53.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.04:43:53.83#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:53.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:53.95#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:53.95#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:53.95#ibcon#enter wrdev, iclass 21, count 0 2006.257.04:43:53.95#ibcon#first serial, iclass 21, count 0 2006.257.04:43:53.95#ibcon#enter sib2, iclass 21, count 0 2006.257.04:43:53.95#ibcon#flushed, iclass 21, count 0 2006.257.04:43:53.95#ibcon#about to write, iclass 21, count 0 2006.257.04:43:53.95#ibcon#wrote, iclass 21, count 0 2006.257.04:43:53.95#ibcon#about to read 3, iclass 21, count 0 2006.257.04:43:53.97#ibcon#read 3, iclass 21, count 0 2006.257.04:43:53.97#ibcon#about to read 4, iclass 21, count 0 2006.257.04:43:53.97#ibcon#read 4, iclass 21, count 0 2006.257.04:43:53.97#ibcon#about to read 5, iclass 21, count 0 2006.257.04:43:53.97#ibcon#read 5, iclass 21, count 0 2006.257.04:43:53.97#ibcon#about to read 6, iclass 21, count 0 2006.257.04:43:53.97#ibcon#read 6, iclass 21, count 0 2006.257.04:43:53.97#ibcon#end of sib2, iclass 21, count 0 2006.257.04:43:53.97#ibcon#*mode == 0, iclass 21, count 0 2006.257.04:43:53.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.04:43:53.97#ibcon#[27=USB\r\n] 2006.257.04:43:53.97#ibcon#*before write, iclass 21, count 0 2006.257.04:43:53.97#ibcon#enter sib2, iclass 21, count 0 2006.257.04:43:53.97#ibcon#flushed, iclass 21, count 0 2006.257.04:43:53.97#ibcon#about to write, iclass 21, count 0 2006.257.04:43:53.97#ibcon#wrote, iclass 21, count 0 2006.257.04:43:53.97#ibcon#about to read 3, iclass 21, count 0 2006.257.04:43:54.00#ibcon#read 3, iclass 21, count 0 2006.257.04:43:54.00#ibcon#about to read 4, iclass 21, count 0 2006.257.04:43:54.00#ibcon#read 4, iclass 21, count 0 2006.257.04:43:54.00#ibcon#about to read 5, iclass 21, count 0 2006.257.04:43:54.00#ibcon#read 5, iclass 21, count 0 2006.257.04:43:54.00#ibcon#about to read 6, iclass 21, count 0 2006.257.04:43:54.00#ibcon#read 6, iclass 21, count 0 2006.257.04:43:54.00#ibcon#end of sib2, iclass 21, count 0 2006.257.04:43:54.00#ibcon#*after write, iclass 21, count 0 2006.257.04:43:54.00#ibcon#*before return 0, iclass 21, count 0 2006.257.04:43:54.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:54.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.04:43:54.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.04:43:54.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.04:43:54.00$vck44/vblo=7,734.99 2006.257.04:43:54.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.04:43:54.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.04:43:54.00#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:54.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:54.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:54.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:54.00#ibcon#enter wrdev, iclass 23, count 0 2006.257.04:43:54.00#ibcon#first serial, iclass 23, count 0 2006.257.04:43:54.00#ibcon#enter sib2, iclass 23, count 0 2006.257.04:43:54.00#ibcon#flushed, iclass 23, count 0 2006.257.04:43:54.00#ibcon#about to write, iclass 23, count 0 2006.257.04:43:54.00#ibcon#wrote, iclass 23, count 0 2006.257.04:43:54.00#ibcon#about to read 3, iclass 23, count 0 2006.257.04:43:54.02#ibcon#read 3, iclass 23, count 0 2006.257.04:43:54.02#ibcon#about to read 4, iclass 23, count 0 2006.257.04:43:54.02#ibcon#read 4, iclass 23, count 0 2006.257.04:43:54.02#ibcon#about to read 5, iclass 23, count 0 2006.257.04:43:54.02#ibcon#read 5, iclass 23, count 0 2006.257.04:43:54.02#ibcon#about to read 6, iclass 23, count 0 2006.257.04:43:54.02#ibcon#read 6, iclass 23, count 0 2006.257.04:43:54.02#ibcon#end of sib2, iclass 23, count 0 2006.257.04:43:54.02#ibcon#*mode == 0, iclass 23, count 0 2006.257.04:43:54.02#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.04:43:54.02#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.04:43:54.02#ibcon#*before write, iclass 23, count 0 2006.257.04:43:54.02#ibcon#enter sib2, iclass 23, count 0 2006.257.04:43:54.02#ibcon#flushed, iclass 23, count 0 2006.257.04:43:54.02#ibcon#about to write, iclass 23, count 0 2006.257.04:43:54.02#ibcon#wrote, iclass 23, count 0 2006.257.04:43:54.02#ibcon#about to read 3, iclass 23, count 0 2006.257.04:43:54.06#ibcon#read 3, iclass 23, count 0 2006.257.04:43:54.06#ibcon#about to read 4, iclass 23, count 0 2006.257.04:43:54.06#ibcon#read 4, iclass 23, count 0 2006.257.04:43:54.06#ibcon#about to read 5, iclass 23, count 0 2006.257.04:43:54.06#ibcon#read 5, iclass 23, count 0 2006.257.04:43:54.06#ibcon#about to read 6, iclass 23, count 0 2006.257.04:43:54.06#ibcon#read 6, iclass 23, count 0 2006.257.04:43:54.06#ibcon#end of sib2, iclass 23, count 0 2006.257.04:43:54.06#ibcon#*after write, iclass 23, count 0 2006.257.04:43:54.06#ibcon#*before return 0, iclass 23, count 0 2006.257.04:43:54.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:54.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.04:43:54.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.04:43:54.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.04:43:54.06$vck44/vb=7,4 2006.257.04:43:54.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.04:43:54.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.04:43:54.06#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:54.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:54.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:54.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:54.12#ibcon#enter wrdev, iclass 25, count 2 2006.257.04:43:54.12#ibcon#first serial, iclass 25, count 2 2006.257.04:43:54.12#ibcon#enter sib2, iclass 25, count 2 2006.257.04:43:54.12#ibcon#flushed, iclass 25, count 2 2006.257.04:43:54.12#ibcon#about to write, iclass 25, count 2 2006.257.04:43:54.12#ibcon#wrote, iclass 25, count 2 2006.257.04:43:54.12#ibcon#about to read 3, iclass 25, count 2 2006.257.04:43:54.14#ibcon#read 3, iclass 25, count 2 2006.257.04:43:54.14#ibcon#about to read 4, iclass 25, count 2 2006.257.04:43:54.14#ibcon#read 4, iclass 25, count 2 2006.257.04:43:54.14#ibcon#about to read 5, iclass 25, count 2 2006.257.04:43:54.14#ibcon#read 5, iclass 25, count 2 2006.257.04:43:54.14#ibcon#about to read 6, iclass 25, count 2 2006.257.04:43:54.14#ibcon#read 6, iclass 25, count 2 2006.257.04:43:54.14#ibcon#end of sib2, iclass 25, count 2 2006.257.04:43:54.14#ibcon#*mode == 0, iclass 25, count 2 2006.257.04:43:54.14#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.04:43:54.14#ibcon#[27=AT07-04\r\n] 2006.257.04:43:54.14#ibcon#*before write, iclass 25, count 2 2006.257.04:43:54.14#ibcon#enter sib2, iclass 25, count 2 2006.257.04:43:54.14#ibcon#flushed, iclass 25, count 2 2006.257.04:43:54.14#ibcon#about to write, iclass 25, count 2 2006.257.04:43:54.14#ibcon#wrote, iclass 25, count 2 2006.257.04:43:54.14#ibcon#about to read 3, iclass 25, count 2 2006.257.04:43:54.17#ibcon#read 3, iclass 25, count 2 2006.257.04:43:54.17#ibcon#about to read 4, iclass 25, count 2 2006.257.04:43:54.17#ibcon#read 4, iclass 25, count 2 2006.257.04:43:54.17#ibcon#about to read 5, iclass 25, count 2 2006.257.04:43:54.17#ibcon#read 5, iclass 25, count 2 2006.257.04:43:54.17#ibcon#about to read 6, iclass 25, count 2 2006.257.04:43:54.17#ibcon#read 6, iclass 25, count 2 2006.257.04:43:54.17#ibcon#end of sib2, iclass 25, count 2 2006.257.04:43:54.17#ibcon#*after write, iclass 25, count 2 2006.257.04:43:54.17#ibcon#*before return 0, iclass 25, count 2 2006.257.04:43:54.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:54.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.04:43:54.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.04:43:54.17#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:54.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:54.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:54.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:54.29#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:43:54.29#ibcon#first serial, iclass 25, count 0 2006.257.04:43:54.29#ibcon#enter sib2, iclass 25, count 0 2006.257.04:43:54.29#ibcon#flushed, iclass 25, count 0 2006.257.04:43:54.29#ibcon#about to write, iclass 25, count 0 2006.257.04:43:54.29#ibcon#wrote, iclass 25, count 0 2006.257.04:43:54.29#ibcon#about to read 3, iclass 25, count 0 2006.257.04:43:54.31#ibcon#read 3, iclass 25, count 0 2006.257.04:43:54.31#ibcon#about to read 4, iclass 25, count 0 2006.257.04:43:54.31#ibcon#read 4, iclass 25, count 0 2006.257.04:43:54.31#ibcon#about to read 5, iclass 25, count 0 2006.257.04:43:54.31#ibcon#read 5, iclass 25, count 0 2006.257.04:43:54.31#ibcon#about to read 6, iclass 25, count 0 2006.257.04:43:54.31#ibcon#read 6, iclass 25, count 0 2006.257.04:43:54.31#ibcon#end of sib2, iclass 25, count 0 2006.257.04:43:54.31#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:43:54.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:43:54.31#ibcon#[27=USB\r\n] 2006.257.04:43:54.31#ibcon#*before write, iclass 25, count 0 2006.257.04:43:54.31#ibcon#enter sib2, iclass 25, count 0 2006.257.04:43:54.31#ibcon#flushed, iclass 25, count 0 2006.257.04:43:54.31#ibcon#about to write, iclass 25, count 0 2006.257.04:43:54.31#ibcon#wrote, iclass 25, count 0 2006.257.04:43:54.31#ibcon#about to read 3, iclass 25, count 0 2006.257.04:43:54.34#ibcon#read 3, iclass 25, count 0 2006.257.04:43:54.34#ibcon#about to read 4, iclass 25, count 0 2006.257.04:43:54.34#ibcon#read 4, iclass 25, count 0 2006.257.04:43:54.34#ibcon#about to read 5, iclass 25, count 0 2006.257.04:43:54.34#ibcon#read 5, iclass 25, count 0 2006.257.04:43:54.34#ibcon#about to read 6, iclass 25, count 0 2006.257.04:43:54.34#ibcon#read 6, iclass 25, count 0 2006.257.04:43:54.34#ibcon#end of sib2, iclass 25, count 0 2006.257.04:43:54.34#ibcon#*after write, iclass 25, count 0 2006.257.04:43:54.34#ibcon#*before return 0, iclass 25, count 0 2006.257.04:43:54.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:54.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.04:43:54.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:43:54.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:43:54.34$vck44/vblo=8,744.99 2006.257.04:43:54.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.04:43:54.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.04:43:54.34#ibcon#ireg 17 cls_cnt 0 2006.257.04:43:54.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:54.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:54.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:54.34#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:43:54.34#ibcon#first serial, iclass 27, count 0 2006.257.04:43:54.34#ibcon#enter sib2, iclass 27, count 0 2006.257.04:43:54.34#ibcon#flushed, iclass 27, count 0 2006.257.04:43:54.34#ibcon#about to write, iclass 27, count 0 2006.257.04:43:54.34#ibcon#wrote, iclass 27, count 0 2006.257.04:43:54.34#ibcon#about to read 3, iclass 27, count 0 2006.257.04:43:54.36#ibcon#read 3, iclass 27, count 0 2006.257.04:43:54.36#ibcon#about to read 4, iclass 27, count 0 2006.257.04:43:54.36#ibcon#read 4, iclass 27, count 0 2006.257.04:43:54.36#ibcon#about to read 5, iclass 27, count 0 2006.257.04:43:54.36#ibcon#read 5, iclass 27, count 0 2006.257.04:43:54.36#ibcon#about to read 6, iclass 27, count 0 2006.257.04:43:54.36#ibcon#read 6, iclass 27, count 0 2006.257.04:43:54.36#ibcon#end of sib2, iclass 27, count 0 2006.257.04:43:54.36#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:43:54.36#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:43:54.36#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.04:43:54.36#ibcon#*before write, iclass 27, count 0 2006.257.04:43:54.36#ibcon#enter sib2, iclass 27, count 0 2006.257.04:43:54.36#ibcon#flushed, iclass 27, count 0 2006.257.04:43:54.36#ibcon#about to write, iclass 27, count 0 2006.257.04:43:54.36#ibcon#wrote, iclass 27, count 0 2006.257.04:43:54.36#ibcon#about to read 3, iclass 27, count 0 2006.257.04:43:54.40#ibcon#read 3, iclass 27, count 0 2006.257.04:43:54.40#ibcon#about to read 4, iclass 27, count 0 2006.257.04:43:54.40#ibcon#read 4, iclass 27, count 0 2006.257.04:43:54.40#ibcon#about to read 5, iclass 27, count 0 2006.257.04:43:54.40#ibcon#read 5, iclass 27, count 0 2006.257.04:43:54.40#ibcon#about to read 6, iclass 27, count 0 2006.257.04:43:54.40#ibcon#read 6, iclass 27, count 0 2006.257.04:43:54.40#ibcon#end of sib2, iclass 27, count 0 2006.257.04:43:54.40#ibcon#*after write, iclass 27, count 0 2006.257.04:43:54.40#ibcon#*before return 0, iclass 27, count 0 2006.257.04:43:54.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:54.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.04:43:54.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:43:54.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:43:54.40$vck44/vb=8,4 2006.257.04:43:54.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.04:43:54.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.04:43:54.40#ibcon#ireg 11 cls_cnt 2 2006.257.04:43:54.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:54.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:54.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:54.46#ibcon#enter wrdev, iclass 29, count 2 2006.257.04:43:54.46#ibcon#first serial, iclass 29, count 2 2006.257.04:43:54.46#ibcon#enter sib2, iclass 29, count 2 2006.257.04:43:54.46#ibcon#flushed, iclass 29, count 2 2006.257.04:43:54.46#ibcon#about to write, iclass 29, count 2 2006.257.04:43:54.46#ibcon#wrote, iclass 29, count 2 2006.257.04:43:54.46#ibcon#about to read 3, iclass 29, count 2 2006.257.04:43:54.48#ibcon#read 3, iclass 29, count 2 2006.257.04:43:54.48#ibcon#about to read 4, iclass 29, count 2 2006.257.04:43:54.48#ibcon#read 4, iclass 29, count 2 2006.257.04:43:54.48#ibcon#about to read 5, iclass 29, count 2 2006.257.04:43:54.48#ibcon#read 5, iclass 29, count 2 2006.257.04:43:54.48#ibcon#about to read 6, iclass 29, count 2 2006.257.04:43:54.48#ibcon#read 6, iclass 29, count 2 2006.257.04:43:54.48#ibcon#end of sib2, iclass 29, count 2 2006.257.04:43:54.48#ibcon#*mode == 0, iclass 29, count 2 2006.257.04:43:54.48#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.04:43:54.48#ibcon#[27=AT08-04\r\n] 2006.257.04:43:54.48#ibcon#*before write, iclass 29, count 2 2006.257.04:43:54.48#ibcon#enter sib2, iclass 29, count 2 2006.257.04:43:54.48#ibcon#flushed, iclass 29, count 2 2006.257.04:43:54.48#ibcon#about to write, iclass 29, count 2 2006.257.04:43:54.48#ibcon#wrote, iclass 29, count 2 2006.257.04:43:54.48#ibcon#about to read 3, iclass 29, count 2 2006.257.04:43:54.51#ibcon#read 3, iclass 29, count 2 2006.257.04:43:54.51#ibcon#about to read 4, iclass 29, count 2 2006.257.04:43:54.51#ibcon#read 4, iclass 29, count 2 2006.257.04:43:54.51#ibcon#about to read 5, iclass 29, count 2 2006.257.04:43:54.51#ibcon#read 5, iclass 29, count 2 2006.257.04:43:54.51#ibcon#about to read 6, iclass 29, count 2 2006.257.04:43:54.51#ibcon#read 6, iclass 29, count 2 2006.257.04:43:54.51#ibcon#end of sib2, iclass 29, count 2 2006.257.04:43:54.51#ibcon#*after write, iclass 29, count 2 2006.257.04:43:54.51#ibcon#*before return 0, iclass 29, count 2 2006.257.04:43:54.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:54.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.04:43:54.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.04:43:54.51#ibcon#ireg 7 cls_cnt 0 2006.257.04:43:54.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:54.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:54.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:54.63#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:43:54.63#ibcon#first serial, iclass 29, count 0 2006.257.04:43:54.63#ibcon#enter sib2, iclass 29, count 0 2006.257.04:43:54.63#ibcon#flushed, iclass 29, count 0 2006.257.04:43:54.63#ibcon#about to write, iclass 29, count 0 2006.257.04:43:54.63#ibcon#wrote, iclass 29, count 0 2006.257.04:43:54.63#ibcon#about to read 3, iclass 29, count 0 2006.257.04:43:54.65#ibcon#read 3, iclass 29, count 0 2006.257.04:43:54.65#ibcon#about to read 4, iclass 29, count 0 2006.257.04:43:54.65#ibcon#read 4, iclass 29, count 0 2006.257.04:43:54.65#ibcon#about to read 5, iclass 29, count 0 2006.257.04:43:54.65#ibcon#read 5, iclass 29, count 0 2006.257.04:43:54.65#ibcon#about to read 6, iclass 29, count 0 2006.257.04:43:54.65#ibcon#read 6, iclass 29, count 0 2006.257.04:43:54.65#ibcon#end of sib2, iclass 29, count 0 2006.257.04:43:54.65#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:43:54.65#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:43:54.65#ibcon#[27=USB\r\n] 2006.257.04:43:54.65#ibcon#*before write, iclass 29, count 0 2006.257.04:43:54.65#ibcon#enter sib2, iclass 29, count 0 2006.257.04:43:54.65#ibcon#flushed, iclass 29, count 0 2006.257.04:43:54.65#ibcon#about to write, iclass 29, count 0 2006.257.04:43:54.65#ibcon#wrote, iclass 29, count 0 2006.257.04:43:54.65#ibcon#about to read 3, iclass 29, count 0 2006.257.04:43:54.68#ibcon#read 3, iclass 29, count 0 2006.257.04:43:54.68#ibcon#about to read 4, iclass 29, count 0 2006.257.04:43:54.68#ibcon#read 4, iclass 29, count 0 2006.257.04:43:54.68#ibcon#about to read 5, iclass 29, count 0 2006.257.04:43:54.68#ibcon#read 5, iclass 29, count 0 2006.257.04:43:54.68#ibcon#about to read 6, iclass 29, count 0 2006.257.04:43:54.68#ibcon#read 6, iclass 29, count 0 2006.257.04:43:54.68#ibcon#end of sib2, iclass 29, count 0 2006.257.04:43:54.68#ibcon#*after write, iclass 29, count 0 2006.257.04:43:54.68#ibcon#*before return 0, iclass 29, count 0 2006.257.04:43:54.68#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:54.68#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.04:43:54.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:43:54.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:43:54.68$vck44/vabw=wide 2006.257.04:43:54.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.04:43:54.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.04:43:54.68#ibcon#ireg 8 cls_cnt 0 2006.257.04:43:54.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:54.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:54.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:54.68#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:43:54.68#ibcon#first serial, iclass 31, count 0 2006.257.04:43:54.68#ibcon#enter sib2, iclass 31, count 0 2006.257.04:43:54.68#ibcon#flushed, iclass 31, count 0 2006.257.04:43:54.68#ibcon#about to write, iclass 31, count 0 2006.257.04:43:54.68#ibcon#wrote, iclass 31, count 0 2006.257.04:43:54.68#ibcon#about to read 3, iclass 31, count 0 2006.257.04:43:54.70#ibcon#read 3, iclass 31, count 0 2006.257.04:43:54.70#ibcon#about to read 4, iclass 31, count 0 2006.257.04:43:54.70#ibcon#read 4, iclass 31, count 0 2006.257.04:43:54.70#ibcon#about to read 5, iclass 31, count 0 2006.257.04:43:54.70#ibcon#read 5, iclass 31, count 0 2006.257.04:43:54.70#ibcon#about to read 6, iclass 31, count 0 2006.257.04:43:54.70#ibcon#read 6, iclass 31, count 0 2006.257.04:43:54.70#ibcon#end of sib2, iclass 31, count 0 2006.257.04:43:54.70#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:43:54.70#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:43:54.70#ibcon#[25=BW32\r\n] 2006.257.04:43:54.70#ibcon#*before write, iclass 31, count 0 2006.257.04:43:54.70#ibcon#enter sib2, iclass 31, count 0 2006.257.04:43:54.70#ibcon#flushed, iclass 31, count 0 2006.257.04:43:54.70#ibcon#about to write, iclass 31, count 0 2006.257.04:43:54.70#ibcon#wrote, iclass 31, count 0 2006.257.04:43:54.70#ibcon#about to read 3, iclass 31, count 0 2006.257.04:43:54.73#ibcon#read 3, iclass 31, count 0 2006.257.04:43:54.73#ibcon#about to read 4, iclass 31, count 0 2006.257.04:43:54.73#ibcon#read 4, iclass 31, count 0 2006.257.04:43:54.73#ibcon#about to read 5, iclass 31, count 0 2006.257.04:43:54.73#ibcon#read 5, iclass 31, count 0 2006.257.04:43:54.73#ibcon#about to read 6, iclass 31, count 0 2006.257.04:43:54.73#ibcon#read 6, iclass 31, count 0 2006.257.04:43:54.73#ibcon#end of sib2, iclass 31, count 0 2006.257.04:43:54.73#ibcon#*after write, iclass 31, count 0 2006.257.04:43:54.73#ibcon#*before return 0, iclass 31, count 0 2006.257.04:43:54.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:54.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.04:43:54.73#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:43:54.73#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:43:54.73$vck44/vbbw=wide 2006.257.04:43:54.73#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.04:43:54.73#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.04:43:54.73#ibcon#ireg 8 cls_cnt 0 2006.257.04:43:54.73#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:43:54.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:43:54.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:43:54.80#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:43:54.80#ibcon#first serial, iclass 33, count 0 2006.257.04:43:54.80#ibcon#enter sib2, iclass 33, count 0 2006.257.04:43:54.80#ibcon#flushed, iclass 33, count 0 2006.257.04:43:54.80#ibcon#about to write, iclass 33, count 0 2006.257.04:43:54.80#ibcon#wrote, iclass 33, count 0 2006.257.04:43:54.80#ibcon#about to read 3, iclass 33, count 0 2006.257.04:43:54.82#ibcon#read 3, iclass 33, count 0 2006.257.04:43:54.82#ibcon#about to read 4, iclass 33, count 0 2006.257.04:43:54.82#ibcon#read 4, iclass 33, count 0 2006.257.04:43:54.82#ibcon#about to read 5, iclass 33, count 0 2006.257.04:43:54.82#ibcon#read 5, iclass 33, count 0 2006.257.04:43:54.82#ibcon#about to read 6, iclass 33, count 0 2006.257.04:43:54.82#ibcon#read 6, iclass 33, count 0 2006.257.04:43:54.82#ibcon#end of sib2, iclass 33, count 0 2006.257.04:43:54.82#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:43:54.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:43:54.82#ibcon#[27=BW32\r\n] 2006.257.04:43:54.82#ibcon#*before write, iclass 33, count 0 2006.257.04:43:54.82#ibcon#enter sib2, iclass 33, count 0 2006.257.04:43:54.82#ibcon#flushed, iclass 33, count 0 2006.257.04:43:54.82#ibcon#about to write, iclass 33, count 0 2006.257.04:43:54.82#ibcon#wrote, iclass 33, count 0 2006.257.04:43:54.82#ibcon#about to read 3, iclass 33, count 0 2006.257.04:43:54.85#ibcon#read 3, iclass 33, count 0 2006.257.04:43:54.85#ibcon#about to read 4, iclass 33, count 0 2006.257.04:43:54.85#ibcon#read 4, iclass 33, count 0 2006.257.04:43:54.85#ibcon#about to read 5, iclass 33, count 0 2006.257.04:43:54.85#ibcon#read 5, iclass 33, count 0 2006.257.04:43:54.85#ibcon#about to read 6, iclass 33, count 0 2006.257.04:43:54.85#ibcon#read 6, iclass 33, count 0 2006.257.04:43:54.85#ibcon#end of sib2, iclass 33, count 0 2006.257.04:43:54.85#ibcon#*after write, iclass 33, count 0 2006.257.04:43:54.85#ibcon#*before return 0, iclass 33, count 0 2006.257.04:43:54.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:43:54.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:43:54.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:43:54.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:43:54.85$setupk4/ifdk4 2006.257.04:43:54.85$ifdk4/lo= 2006.257.04:43:54.85$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.04:43:54.85$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.04:43:54.85$ifdk4/patch= 2006.257.04:43:54.85$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.04:43:54.85$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.04:43:54.85$setupk4/!*+20s 2006.257.04:43:58.36#abcon#<5=/14 1.8 4.9 19.65 921011.9\r\n> 2006.257.04:43:58.38#abcon#{5=INTERFACE CLEAR} 2006.257.04:43:58.44#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:44:08.53#abcon#<5=/14 1.8 4.9 19.65 921012.0\r\n> 2006.257.04:44:08.55#abcon#{5=INTERFACE CLEAR} 2006.257.04:44:08.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:44:09.35$setupk4/"tpicd 2006.257.04:44:09.35$setupk4/echo=off 2006.257.04:44:09.35$setupk4/xlog=off 2006.257.04:44:09.35:!2006.257.04:48:50 2006.257.04:44:35.13#trakl#Source acquired 2006.257.04:44:36.13#flagr#flagr/antenna,acquired 2006.257.04:48:50.00:preob 2006.257.04:48:50.14/onsource/TRACKING 2006.257.04:48:50.14:!2006.257.04:49:00 2006.257.04:49:00.00:"tape 2006.257.04:49:00.00:"st=record 2006.257.04:49:00.00:data_valid=on 2006.257.04:49:00.00:midob 2006.257.04:49:00.14/onsource/TRACKING 2006.257.04:49:00.14/wx/19.66,1012.0,94 2006.257.04:49:00.33/cable/+6.4817E-03 2006.257.04:49:01.42/va/01,08,usb,yes,33,36 2006.257.04:49:01.42/va/02,07,usb,yes,36,37 2006.257.04:49:01.42/va/03,08,usb,yes,32,34 2006.257.04:49:01.42/va/04,07,usb,yes,37,39 2006.257.04:49:01.42/va/05,04,usb,yes,33,34 2006.257.04:49:01.42/va/06,04,usb,yes,37,37 2006.257.04:49:01.42/va/07,04,usb,yes,38,38 2006.257.04:49:01.42/va/08,04,usb,yes,32,39 2006.257.04:49:01.65/valo/01,524.99,yes,locked 2006.257.04:49:01.65/valo/02,534.99,yes,locked 2006.257.04:49:01.65/valo/03,564.99,yes,locked 2006.257.04:49:01.65/valo/04,624.99,yes,locked 2006.257.04:49:01.65/valo/05,734.99,yes,locked 2006.257.04:49:01.65/valo/06,814.99,yes,locked 2006.257.04:49:01.65/valo/07,864.99,yes,locked 2006.257.04:49:01.65/valo/08,884.99,yes,locked 2006.257.04:49:02.74/vb/01,04,usb,yes,38,35 2006.257.04:49:02.74/vb/02,05,usb,yes,36,36 2006.257.04:49:02.74/vb/03,04,usb,yes,37,41 2006.257.04:49:02.74/vb/04,05,usb,yes,37,36 2006.257.04:49:02.74/vb/05,04,usb,yes,33,36 2006.257.04:49:02.74/vb/06,04,usb,yes,39,34 2006.257.04:49:02.74/vb/07,04,usb,yes,38,38 2006.257.04:49:02.74/vb/08,04,usb,yes,35,39 2006.257.04:49:02.98/vblo/01,629.99,yes,locked 2006.257.04:49:02.98/vblo/02,634.99,yes,locked 2006.257.04:49:02.98/vblo/03,649.99,yes,locked 2006.257.04:49:02.98/vblo/04,679.99,yes,locked 2006.257.04:49:02.98/vblo/05,709.99,yes,locked 2006.257.04:49:02.98/vblo/06,719.99,yes,locked 2006.257.04:49:02.98/vblo/07,734.99,yes,locked 2006.257.04:49:02.98/vblo/08,744.99,yes,locked 2006.257.04:49:03.13/vabw/8 2006.257.04:49:03.28/vbbw/8 2006.257.04:49:03.37/xfe/off,on,16.7 2006.257.04:49:03.74/ifatt/23,28,28,28 2006.257.04:49:04.08/fmout-gps/S +4.53E-07 2006.257.04:49:04.12:!2006.257.04:50:20 2006.257.04:50:20.02:data_valid=off 2006.257.04:50:20.02:"et 2006.257.04:50:20.02:!+3s 2006.257.04:50:23.04:"tape 2006.257.04:50:23.05:postob 2006.257.04:50:23.13/cable/+6.4825E-03 2006.257.04:50:23.13/wx/19.67,1012.0,93 2006.257.04:50:23.18/fmout-gps/S +4.54E-07 2006.257.04:50:23.19:scan_name=257-0453,jd0609,210 2006.257.04:50:23.19:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.257.04:50:24.15#flagr#flagr/antenna,new-source 2006.257.04:50:24.15:checkk5 2006.257.04:50:24.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.04:50:24.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.04:50:25.40/chk_autoobs//k5ts3/ autoobs is running! 2006.257.04:50:25.85/chk_autoobs//k5ts4/ autoobs is running! 2006.257.04:50:26.23/chk_obsdata//k5ts1/T2570449??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.04:50:26.62/chk_obsdata//k5ts2/T2570449??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.04:50:27.03/chk_obsdata//k5ts3/T2570449??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.04:50:27.44/chk_obsdata//k5ts4/T2570449??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.04:50:28.16/k5log//k5ts1_log_newline 2006.257.04:50:28.86/k5log//k5ts2_log_newline 2006.257.04:50:29.61/k5log//k5ts3_log_newline 2006.257.04:50:30.33/k5log//k5ts4_log_newline 2006.257.04:50:30.36/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.04:50:30.36:setupk4=1 2006.257.04:50:30.36$setupk4/echo=on 2006.257.04:50:30.36$setupk4/pcalon 2006.257.04:50:30.36$pcalon/"no phase cal control is implemented here 2006.257.04:50:30.36$setupk4/"tpicd=stop 2006.257.04:50:30.36$setupk4/"rec=synch_on 2006.257.04:50:30.36$setupk4/"rec_mode=128 2006.257.04:50:30.36$setupk4/!* 2006.257.04:50:30.36$setupk4/recpk4 2006.257.04:50:30.36$recpk4/recpatch= 2006.257.04:50:30.36$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.04:50:30.36$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.04:50:30.36$setupk4/vck44 2006.257.04:50:30.36$vck44/valo=1,524.99 2006.257.04:50:30.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.04:50:30.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.04:50:30.36#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:30.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:30.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:30.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:30.36#ibcon#enter wrdev, iclass 14, count 0 2006.257.04:50:30.36#ibcon#first serial, iclass 14, count 0 2006.257.04:50:30.36#ibcon#enter sib2, iclass 14, count 0 2006.257.04:50:30.36#ibcon#flushed, iclass 14, count 0 2006.257.04:50:30.36#ibcon#about to write, iclass 14, count 0 2006.257.04:50:30.36#ibcon#wrote, iclass 14, count 0 2006.257.04:50:30.36#ibcon#about to read 3, iclass 14, count 0 2006.257.04:50:30.37#ibcon#read 3, iclass 14, count 0 2006.257.04:50:30.37#ibcon#about to read 4, iclass 14, count 0 2006.257.04:50:30.37#ibcon#read 4, iclass 14, count 0 2006.257.04:50:30.37#ibcon#about to read 5, iclass 14, count 0 2006.257.04:50:30.37#ibcon#read 5, iclass 14, count 0 2006.257.04:50:30.37#ibcon#about to read 6, iclass 14, count 0 2006.257.04:50:30.37#ibcon#read 6, iclass 14, count 0 2006.257.04:50:30.37#ibcon#end of sib2, iclass 14, count 0 2006.257.04:50:30.37#ibcon#*mode == 0, iclass 14, count 0 2006.257.04:50:30.37#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.04:50:30.38#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.04:50:30.38#ibcon#*before write, iclass 14, count 0 2006.257.04:50:30.38#ibcon#enter sib2, iclass 14, count 0 2006.257.04:50:30.38#ibcon#flushed, iclass 14, count 0 2006.257.04:50:30.38#ibcon#about to write, iclass 14, count 0 2006.257.04:50:30.38#ibcon#wrote, iclass 14, count 0 2006.257.04:50:30.38#ibcon#about to read 3, iclass 14, count 0 2006.257.04:50:30.42#ibcon#read 3, iclass 14, count 0 2006.257.04:50:30.42#ibcon#about to read 4, iclass 14, count 0 2006.257.04:50:30.42#ibcon#read 4, iclass 14, count 0 2006.257.04:50:30.42#ibcon#about to read 5, iclass 14, count 0 2006.257.04:50:30.42#ibcon#read 5, iclass 14, count 0 2006.257.04:50:30.42#ibcon#about to read 6, iclass 14, count 0 2006.257.04:50:30.42#ibcon#read 6, iclass 14, count 0 2006.257.04:50:30.42#ibcon#end of sib2, iclass 14, count 0 2006.257.04:50:30.42#ibcon#*after write, iclass 14, count 0 2006.257.04:50:30.42#ibcon#*before return 0, iclass 14, count 0 2006.257.04:50:30.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:30.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:30.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.04:50:30.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.04:50:30.43$vck44/va=1,8 2006.257.04:50:30.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.04:50:30.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.04:50:30.43#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:30.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:30.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:30.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:30.43#ibcon#enter wrdev, iclass 16, count 2 2006.257.04:50:30.43#ibcon#first serial, iclass 16, count 2 2006.257.04:50:30.43#ibcon#enter sib2, iclass 16, count 2 2006.257.04:50:30.43#ibcon#flushed, iclass 16, count 2 2006.257.04:50:30.43#ibcon#about to write, iclass 16, count 2 2006.257.04:50:30.43#ibcon#wrote, iclass 16, count 2 2006.257.04:50:30.43#ibcon#about to read 3, iclass 16, count 2 2006.257.04:50:30.44#ibcon#read 3, iclass 16, count 2 2006.257.04:50:30.44#ibcon#about to read 4, iclass 16, count 2 2006.257.04:50:30.44#ibcon#read 4, iclass 16, count 2 2006.257.04:50:30.44#ibcon#about to read 5, iclass 16, count 2 2006.257.04:50:30.44#ibcon#read 5, iclass 16, count 2 2006.257.04:50:30.44#ibcon#about to read 6, iclass 16, count 2 2006.257.04:50:30.44#ibcon#read 6, iclass 16, count 2 2006.257.04:50:30.44#ibcon#end of sib2, iclass 16, count 2 2006.257.04:50:30.44#ibcon#*mode == 0, iclass 16, count 2 2006.257.04:50:30.44#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.04:50:30.44#ibcon#[25=AT01-08\r\n] 2006.257.04:50:30.44#ibcon#*before write, iclass 16, count 2 2006.257.04:50:30.44#ibcon#enter sib2, iclass 16, count 2 2006.257.04:50:30.44#ibcon#flushed, iclass 16, count 2 2006.257.04:50:30.44#ibcon#about to write, iclass 16, count 2 2006.257.04:50:30.44#ibcon#wrote, iclass 16, count 2 2006.257.04:50:30.45#ibcon#about to read 3, iclass 16, count 2 2006.257.04:50:30.47#ibcon#read 3, iclass 16, count 2 2006.257.04:50:30.47#ibcon#about to read 4, iclass 16, count 2 2006.257.04:50:30.47#ibcon#read 4, iclass 16, count 2 2006.257.04:50:30.47#ibcon#about to read 5, iclass 16, count 2 2006.257.04:50:30.47#ibcon#read 5, iclass 16, count 2 2006.257.04:50:30.47#ibcon#about to read 6, iclass 16, count 2 2006.257.04:50:30.47#ibcon#read 6, iclass 16, count 2 2006.257.04:50:30.47#ibcon#end of sib2, iclass 16, count 2 2006.257.04:50:30.47#ibcon#*after write, iclass 16, count 2 2006.257.04:50:30.47#ibcon#*before return 0, iclass 16, count 2 2006.257.04:50:30.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:30.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:30.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.04:50:30.47#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:30.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:30.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:30.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:30.59#ibcon#enter wrdev, iclass 16, count 0 2006.257.04:50:30.59#ibcon#first serial, iclass 16, count 0 2006.257.04:50:30.59#ibcon#enter sib2, iclass 16, count 0 2006.257.04:50:30.59#ibcon#flushed, iclass 16, count 0 2006.257.04:50:30.59#ibcon#about to write, iclass 16, count 0 2006.257.04:50:30.59#ibcon#wrote, iclass 16, count 0 2006.257.04:50:30.59#ibcon#about to read 3, iclass 16, count 0 2006.257.04:50:30.61#ibcon#read 3, iclass 16, count 0 2006.257.04:50:30.61#ibcon#about to read 4, iclass 16, count 0 2006.257.04:50:30.61#ibcon#read 4, iclass 16, count 0 2006.257.04:50:30.61#ibcon#about to read 5, iclass 16, count 0 2006.257.04:50:30.61#ibcon#read 5, iclass 16, count 0 2006.257.04:50:30.61#ibcon#about to read 6, iclass 16, count 0 2006.257.04:50:30.61#ibcon#read 6, iclass 16, count 0 2006.257.04:50:30.61#ibcon#end of sib2, iclass 16, count 0 2006.257.04:50:30.61#ibcon#*mode == 0, iclass 16, count 0 2006.257.04:50:30.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.04:50:30.61#ibcon#[25=USB\r\n] 2006.257.04:50:30.61#ibcon#*before write, iclass 16, count 0 2006.257.04:50:30.61#ibcon#enter sib2, iclass 16, count 0 2006.257.04:50:30.61#ibcon#flushed, iclass 16, count 0 2006.257.04:50:30.61#ibcon#about to write, iclass 16, count 0 2006.257.04:50:30.61#ibcon#wrote, iclass 16, count 0 2006.257.04:50:30.62#ibcon#about to read 3, iclass 16, count 0 2006.257.04:50:30.64#ibcon#read 3, iclass 16, count 0 2006.257.04:50:30.64#ibcon#about to read 4, iclass 16, count 0 2006.257.04:50:30.64#ibcon#read 4, iclass 16, count 0 2006.257.04:50:30.64#ibcon#about to read 5, iclass 16, count 0 2006.257.04:50:30.64#ibcon#read 5, iclass 16, count 0 2006.257.04:50:30.64#ibcon#about to read 6, iclass 16, count 0 2006.257.04:50:30.64#ibcon#read 6, iclass 16, count 0 2006.257.04:50:30.64#ibcon#end of sib2, iclass 16, count 0 2006.257.04:50:30.64#ibcon#*after write, iclass 16, count 0 2006.257.04:50:30.64#ibcon#*before return 0, iclass 16, count 0 2006.257.04:50:30.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:30.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:30.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.04:50:30.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.04:50:30.65$vck44/valo=2,534.99 2006.257.04:50:30.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.04:50:30.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.04:50:30.65#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:30.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:30.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:30.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:30.65#ibcon#enter wrdev, iclass 18, count 0 2006.257.04:50:30.65#ibcon#first serial, iclass 18, count 0 2006.257.04:50:30.65#ibcon#enter sib2, iclass 18, count 0 2006.257.04:50:30.65#ibcon#flushed, iclass 18, count 0 2006.257.04:50:30.65#ibcon#about to write, iclass 18, count 0 2006.257.04:50:30.65#ibcon#wrote, iclass 18, count 0 2006.257.04:50:30.65#ibcon#about to read 3, iclass 18, count 0 2006.257.04:50:30.66#ibcon#read 3, iclass 18, count 0 2006.257.04:50:30.66#ibcon#about to read 4, iclass 18, count 0 2006.257.04:50:30.66#ibcon#read 4, iclass 18, count 0 2006.257.04:50:30.66#ibcon#about to read 5, iclass 18, count 0 2006.257.04:50:30.66#ibcon#read 5, iclass 18, count 0 2006.257.04:50:30.66#ibcon#about to read 6, iclass 18, count 0 2006.257.04:50:30.66#ibcon#read 6, iclass 18, count 0 2006.257.04:50:30.66#ibcon#end of sib2, iclass 18, count 0 2006.257.04:50:30.66#ibcon#*mode == 0, iclass 18, count 0 2006.257.04:50:30.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.04:50:30.66#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.04:50:30.66#ibcon#*before write, iclass 18, count 0 2006.257.04:50:30.66#ibcon#enter sib2, iclass 18, count 0 2006.257.04:50:30.66#ibcon#flushed, iclass 18, count 0 2006.257.04:50:30.66#ibcon#about to write, iclass 18, count 0 2006.257.04:50:30.66#ibcon#wrote, iclass 18, count 0 2006.257.04:50:30.66#ibcon#about to read 3, iclass 18, count 0 2006.257.04:50:30.70#ibcon#read 3, iclass 18, count 0 2006.257.04:50:30.70#ibcon#about to read 4, iclass 18, count 0 2006.257.04:50:30.70#ibcon#read 4, iclass 18, count 0 2006.257.04:50:30.70#ibcon#about to read 5, iclass 18, count 0 2006.257.04:50:30.70#ibcon#read 5, iclass 18, count 0 2006.257.04:50:30.70#ibcon#about to read 6, iclass 18, count 0 2006.257.04:50:30.70#ibcon#read 6, iclass 18, count 0 2006.257.04:50:30.70#ibcon#end of sib2, iclass 18, count 0 2006.257.04:50:30.70#ibcon#*after write, iclass 18, count 0 2006.257.04:50:30.70#ibcon#*before return 0, iclass 18, count 0 2006.257.04:50:30.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:30.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:30.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.04:50:30.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.04:50:30.71$vck44/va=2,7 2006.257.04:50:30.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.04:50:30.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.04:50:30.71#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:30.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:30.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:30.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:30.75#ibcon#enter wrdev, iclass 20, count 2 2006.257.04:50:30.75#ibcon#first serial, iclass 20, count 2 2006.257.04:50:30.75#ibcon#enter sib2, iclass 20, count 2 2006.257.04:50:30.75#ibcon#flushed, iclass 20, count 2 2006.257.04:50:30.75#ibcon#about to write, iclass 20, count 2 2006.257.04:50:30.75#ibcon#wrote, iclass 20, count 2 2006.257.04:50:30.75#ibcon#about to read 3, iclass 20, count 2 2006.257.04:50:30.77#ibcon#read 3, iclass 20, count 2 2006.257.04:50:30.77#ibcon#about to read 4, iclass 20, count 2 2006.257.04:50:30.77#ibcon#read 4, iclass 20, count 2 2006.257.04:50:30.77#ibcon#about to read 5, iclass 20, count 2 2006.257.04:50:30.77#ibcon#read 5, iclass 20, count 2 2006.257.04:50:30.77#ibcon#about to read 6, iclass 20, count 2 2006.257.04:50:30.77#ibcon#read 6, iclass 20, count 2 2006.257.04:50:30.77#ibcon#end of sib2, iclass 20, count 2 2006.257.04:50:30.77#ibcon#*mode == 0, iclass 20, count 2 2006.257.04:50:30.77#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.04:50:30.77#ibcon#[25=AT02-07\r\n] 2006.257.04:50:30.77#ibcon#*before write, iclass 20, count 2 2006.257.04:50:30.77#ibcon#enter sib2, iclass 20, count 2 2006.257.04:50:30.77#ibcon#flushed, iclass 20, count 2 2006.257.04:50:30.77#ibcon#about to write, iclass 20, count 2 2006.257.04:50:30.77#ibcon#wrote, iclass 20, count 2 2006.257.04:50:30.77#ibcon#about to read 3, iclass 20, count 2 2006.257.04:50:30.80#ibcon#read 3, iclass 20, count 2 2006.257.04:50:30.80#ibcon#about to read 4, iclass 20, count 2 2006.257.04:50:30.80#ibcon#read 4, iclass 20, count 2 2006.257.04:50:30.80#ibcon#about to read 5, iclass 20, count 2 2006.257.04:50:30.80#ibcon#read 5, iclass 20, count 2 2006.257.04:50:30.80#ibcon#about to read 6, iclass 20, count 2 2006.257.04:50:30.80#ibcon#read 6, iclass 20, count 2 2006.257.04:50:30.80#ibcon#end of sib2, iclass 20, count 2 2006.257.04:50:30.80#ibcon#*after write, iclass 20, count 2 2006.257.04:50:30.80#ibcon#*before return 0, iclass 20, count 2 2006.257.04:50:30.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:30.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:30.80#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.04:50:30.80#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:30.80#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:30.92#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:30.92#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:30.92#ibcon#enter wrdev, iclass 20, count 0 2006.257.04:50:30.92#ibcon#first serial, iclass 20, count 0 2006.257.04:50:30.92#ibcon#enter sib2, iclass 20, count 0 2006.257.04:50:30.92#ibcon#flushed, iclass 20, count 0 2006.257.04:50:30.92#ibcon#about to write, iclass 20, count 0 2006.257.04:50:30.92#ibcon#wrote, iclass 20, count 0 2006.257.04:50:30.92#ibcon#about to read 3, iclass 20, count 0 2006.257.04:50:30.94#ibcon#read 3, iclass 20, count 0 2006.257.04:50:30.94#ibcon#about to read 4, iclass 20, count 0 2006.257.04:50:30.94#ibcon#read 4, iclass 20, count 0 2006.257.04:50:30.94#ibcon#about to read 5, iclass 20, count 0 2006.257.04:50:30.94#ibcon#read 5, iclass 20, count 0 2006.257.04:50:30.94#ibcon#about to read 6, iclass 20, count 0 2006.257.04:50:30.94#ibcon#read 6, iclass 20, count 0 2006.257.04:50:30.94#ibcon#end of sib2, iclass 20, count 0 2006.257.04:50:30.94#ibcon#*mode == 0, iclass 20, count 0 2006.257.04:50:30.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.04:50:30.94#ibcon#[25=USB\r\n] 2006.257.04:50:30.94#ibcon#*before write, iclass 20, count 0 2006.257.04:50:30.94#ibcon#enter sib2, iclass 20, count 0 2006.257.04:50:30.94#ibcon#flushed, iclass 20, count 0 2006.257.04:50:30.94#ibcon#about to write, iclass 20, count 0 2006.257.04:50:30.94#ibcon#wrote, iclass 20, count 0 2006.257.04:50:30.94#ibcon#about to read 3, iclass 20, count 0 2006.257.04:50:30.97#ibcon#read 3, iclass 20, count 0 2006.257.04:50:30.97#ibcon#about to read 4, iclass 20, count 0 2006.257.04:50:30.97#ibcon#read 4, iclass 20, count 0 2006.257.04:50:30.97#ibcon#about to read 5, iclass 20, count 0 2006.257.04:50:30.97#ibcon#read 5, iclass 20, count 0 2006.257.04:50:30.97#ibcon#about to read 6, iclass 20, count 0 2006.257.04:50:30.97#ibcon#read 6, iclass 20, count 0 2006.257.04:50:30.97#ibcon#end of sib2, iclass 20, count 0 2006.257.04:50:30.97#ibcon#*after write, iclass 20, count 0 2006.257.04:50:30.97#ibcon#*before return 0, iclass 20, count 0 2006.257.04:50:30.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:30.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:30.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.04:50:30.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.04:50:30.98$vck44/valo=3,564.99 2006.257.04:50:30.98#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.04:50:30.98#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.04:50:30.98#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:30.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:30.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:30.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:30.98#ibcon#enter wrdev, iclass 22, count 0 2006.257.04:50:30.98#ibcon#first serial, iclass 22, count 0 2006.257.04:50:30.98#ibcon#enter sib2, iclass 22, count 0 2006.257.04:50:30.98#ibcon#flushed, iclass 22, count 0 2006.257.04:50:30.98#ibcon#about to write, iclass 22, count 0 2006.257.04:50:30.98#ibcon#wrote, iclass 22, count 0 2006.257.04:50:30.98#ibcon#about to read 3, iclass 22, count 0 2006.257.04:50:30.99#ibcon#read 3, iclass 22, count 0 2006.257.04:50:30.99#ibcon#about to read 4, iclass 22, count 0 2006.257.04:50:30.99#ibcon#read 4, iclass 22, count 0 2006.257.04:50:30.99#ibcon#about to read 5, iclass 22, count 0 2006.257.04:50:30.99#ibcon#read 5, iclass 22, count 0 2006.257.04:50:30.99#ibcon#about to read 6, iclass 22, count 0 2006.257.04:50:30.99#ibcon#read 6, iclass 22, count 0 2006.257.04:50:30.99#ibcon#end of sib2, iclass 22, count 0 2006.257.04:50:30.99#ibcon#*mode == 0, iclass 22, count 0 2006.257.04:50:30.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.04:50:30.99#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.04:50:30.99#ibcon#*before write, iclass 22, count 0 2006.257.04:50:30.99#ibcon#enter sib2, iclass 22, count 0 2006.257.04:50:30.99#ibcon#flushed, iclass 22, count 0 2006.257.04:50:30.99#ibcon#about to write, iclass 22, count 0 2006.257.04:50:30.99#ibcon#wrote, iclass 22, count 0 2006.257.04:50:30.99#ibcon#about to read 3, iclass 22, count 0 2006.257.04:50:31.03#ibcon#read 3, iclass 22, count 0 2006.257.04:50:31.03#ibcon#about to read 4, iclass 22, count 0 2006.257.04:50:31.03#ibcon#read 4, iclass 22, count 0 2006.257.04:50:31.03#ibcon#about to read 5, iclass 22, count 0 2006.257.04:50:31.03#ibcon#read 5, iclass 22, count 0 2006.257.04:50:31.03#ibcon#about to read 6, iclass 22, count 0 2006.257.04:50:31.03#ibcon#read 6, iclass 22, count 0 2006.257.04:50:31.03#ibcon#end of sib2, iclass 22, count 0 2006.257.04:50:31.03#ibcon#*after write, iclass 22, count 0 2006.257.04:50:31.03#ibcon#*before return 0, iclass 22, count 0 2006.257.04:50:31.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:31.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:31.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.04:50:31.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.04:50:31.04$vck44/va=3,8 2006.257.04:50:31.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.04:50:31.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.04:50:31.04#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:31.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:31.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:31.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:31.08#ibcon#enter wrdev, iclass 24, count 2 2006.257.04:50:31.08#ibcon#first serial, iclass 24, count 2 2006.257.04:50:31.08#ibcon#enter sib2, iclass 24, count 2 2006.257.04:50:31.08#ibcon#flushed, iclass 24, count 2 2006.257.04:50:31.08#ibcon#about to write, iclass 24, count 2 2006.257.04:50:31.08#ibcon#wrote, iclass 24, count 2 2006.257.04:50:31.08#ibcon#about to read 3, iclass 24, count 2 2006.257.04:50:31.10#ibcon#read 3, iclass 24, count 2 2006.257.04:50:31.10#ibcon#about to read 4, iclass 24, count 2 2006.257.04:50:31.10#ibcon#read 4, iclass 24, count 2 2006.257.04:50:31.10#ibcon#about to read 5, iclass 24, count 2 2006.257.04:50:31.10#ibcon#read 5, iclass 24, count 2 2006.257.04:50:31.10#ibcon#about to read 6, iclass 24, count 2 2006.257.04:50:31.10#ibcon#read 6, iclass 24, count 2 2006.257.04:50:31.10#ibcon#end of sib2, iclass 24, count 2 2006.257.04:50:31.10#ibcon#*mode == 0, iclass 24, count 2 2006.257.04:50:31.10#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.04:50:31.10#ibcon#[25=AT03-08\r\n] 2006.257.04:50:31.10#ibcon#*before write, iclass 24, count 2 2006.257.04:50:31.10#ibcon#enter sib2, iclass 24, count 2 2006.257.04:50:31.10#ibcon#flushed, iclass 24, count 2 2006.257.04:50:31.10#ibcon#about to write, iclass 24, count 2 2006.257.04:50:31.10#ibcon#wrote, iclass 24, count 2 2006.257.04:50:31.10#ibcon#about to read 3, iclass 24, count 2 2006.257.04:50:31.13#ibcon#read 3, iclass 24, count 2 2006.257.04:50:31.13#ibcon#about to read 4, iclass 24, count 2 2006.257.04:50:31.13#ibcon#read 4, iclass 24, count 2 2006.257.04:50:31.13#ibcon#about to read 5, iclass 24, count 2 2006.257.04:50:31.13#ibcon#read 5, iclass 24, count 2 2006.257.04:50:31.13#ibcon#about to read 6, iclass 24, count 2 2006.257.04:50:31.13#ibcon#read 6, iclass 24, count 2 2006.257.04:50:31.13#ibcon#end of sib2, iclass 24, count 2 2006.257.04:50:31.13#ibcon#*after write, iclass 24, count 2 2006.257.04:50:31.13#ibcon#*before return 0, iclass 24, count 2 2006.257.04:50:31.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:31.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:31.13#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.04:50:31.13#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:31.13#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:31.25#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:31.25#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:31.25#ibcon#enter wrdev, iclass 24, count 0 2006.257.04:50:31.25#ibcon#first serial, iclass 24, count 0 2006.257.04:50:31.25#ibcon#enter sib2, iclass 24, count 0 2006.257.04:50:31.25#ibcon#flushed, iclass 24, count 0 2006.257.04:50:31.25#ibcon#about to write, iclass 24, count 0 2006.257.04:50:31.25#ibcon#wrote, iclass 24, count 0 2006.257.04:50:31.25#ibcon#about to read 3, iclass 24, count 0 2006.257.04:50:31.27#ibcon#read 3, iclass 24, count 0 2006.257.04:50:31.27#ibcon#about to read 4, iclass 24, count 0 2006.257.04:50:31.27#ibcon#read 4, iclass 24, count 0 2006.257.04:50:31.27#ibcon#about to read 5, iclass 24, count 0 2006.257.04:50:31.27#ibcon#read 5, iclass 24, count 0 2006.257.04:50:31.27#ibcon#about to read 6, iclass 24, count 0 2006.257.04:50:31.27#ibcon#read 6, iclass 24, count 0 2006.257.04:50:31.27#ibcon#end of sib2, iclass 24, count 0 2006.257.04:50:31.27#ibcon#*mode == 0, iclass 24, count 0 2006.257.04:50:31.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.04:50:31.27#ibcon#[25=USB\r\n] 2006.257.04:50:31.27#ibcon#*before write, iclass 24, count 0 2006.257.04:50:31.27#ibcon#enter sib2, iclass 24, count 0 2006.257.04:50:31.27#ibcon#flushed, iclass 24, count 0 2006.257.04:50:31.27#ibcon#about to write, iclass 24, count 0 2006.257.04:50:31.27#ibcon#wrote, iclass 24, count 0 2006.257.04:50:31.27#ibcon#about to read 3, iclass 24, count 0 2006.257.04:50:31.30#ibcon#read 3, iclass 24, count 0 2006.257.04:50:31.30#ibcon#about to read 4, iclass 24, count 0 2006.257.04:50:31.30#ibcon#read 4, iclass 24, count 0 2006.257.04:50:31.30#ibcon#about to read 5, iclass 24, count 0 2006.257.04:50:31.30#ibcon#read 5, iclass 24, count 0 2006.257.04:50:31.30#ibcon#about to read 6, iclass 24, count 0 2006.257.04:50:31.30#ibcon#read 6, iclass 24, count 0 2006.257.04:50:31.30#ibcon#end of sib2, iclass 24, count 0 2006.257.04:50:31.30#ibcon#*after write, iclass 24, count 0 2006.257.04:50:31.30#ibcon#*before return 0, iclass 24, count 0 2006.257.04:50:31.30#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:31.30#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:31.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.04:50:31.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.04:50:31.31$vck44/valo=4,624.99 2006.257.04:50:31.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.04:50:31.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.04:50:31.31#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:31.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:31.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:31.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:31.31#ibcon#enter wrdev, iclass 26, count 0 2006.257.04:50:31.31#ibcon#first serial, iclass 26, count 0 2006.257.04:50:31.31#ibcon#enter sib2, iclass 26, count 0 2006.257.04:50:31.31#ibcon#flushed, iclass 26, count 0 2006.257.04:50:31.31#ibcon#about to write, iclass 26, count 0 2006.257.04:50:31.31#ibcon#wrote, iclass 26, count 0 2006.257.04:50:31.31#ibcon#about to read 3, iclass 26, count 0 2006.257.04:50:31.32#ibcon#read 3, iclass 26, count 0 2006.257.04:50:31.32#ibcon#about to read 4, iclass 26, count 0 2006.257.04:50:31.32#ibcon#read 4, iclass 26, count 0 2006.257.04:50:31.32#ibcon#about to read 5, iclass 26, count 0 2006.257.04:50:31.32#ibcon#read 5, iclass 26, count 0 2006.257.04:50:31.32#ibcon#about to read 6, iclass 26, count 0 2006.257.04:50:31.32#ibcon#read 6, iclass 26, count 0 2006.257.04:50:31.32#ibcon#end of sib2, iclass 26, count 0 2006.257.04:50:31.32#ibcon#*mode == 0, iclass 26, count 0 2006.257.04:50:31.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.04:50:31.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.04:50:31.32#ibcon#*before write, iclass 26, count 0 2006.257.04:50:31.32#ibcon#enter sib2, iclass 26, count 0 2006.257.04:50:31.32#ibcon#flushed, iclass 26, count 0 2006.257.04:50:31.32#ibcon#about to write, iclass 26, count 0 2006.257.04:50:31.32#ibcon#wrote, iclass 26, count 0 2006.257.04:50:31.32#ibcon#about to read 3, iclass 26, count 0 2006.257.04:50:31.36#ibcon#read 3, iclass 26, count 0 2006.257.04:50:31.36#ibcon#about to read 4, iclass 26, count 0 2006.257.04:50:31.36#ibcon#read 4, iclass 26, count 0 2006.257.04:50:31.36#ibcon#about to read 5, iclass 26, count 0 2006.257.04:50:31.36#ibcon#read 5, iclass 26, count 0 2006.257.04:50:31.36#ibcon#about to read 6, iclass 26, count 0 2006.257.04:50:31.36#ibcon#read 6, iclass 26, count 0 2006.257.04:50:31.36#ibcon#end of sib2, iclass 26, count 0 2006.257.04:50:31.36#ibcon#*after write, iclass 26, count 0 2006.257.04:50:31.36#ibcon#*before return 0, iclass 26, count 0 2006.257.04:50:31.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:31.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:31.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.04:50:31.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.04:50:31.37$vck44/va=4,7 2006.257.04:50:31.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.04:50:31.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.04:50:31.37#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:31.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:31.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:31.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:31.41#ibcon#enter wrdev, iclass 28, count 2 2006.257.04:50:31.41#ibcon#first serial, iclass 28, count 2 2006.257.04:50:31.41#ibcon#enter sib2, iclass 28, count 2 2006.257.04:50:31.41#ibcon#flushed, iclass 28, count 2 2006.257.04:50:31.41#ibcon#about to write, iclass 28, count 2 2006.257.04:50:31.41#ibcon#wrote, iclass 28, count 2 2006.257.04:50:31.41#ibcon#about to read 3, iclass 28, count 2 2006.257.04:50:31.43#ibcon#read 3, iclass 28, count 2 2006.257.04:50:31.43#ibcon#about to read 4, iclass 28, count 2 2006.257.04:50:31.43#ibcon#read 4, iclass 28, count 2 2006.257.04:50:31.43#ibcon#about to read 5, iclass 28, count 2 2006.257.04:50:31.43#ibcon#read 5, iclass 28, count 2 2006.257.04:50:31.43#ibcon#about to read 6, iclass 28, count 2 2006.257.04:50:31.43#ibcon#read 6, iclass 28, count 2 2006.257.04:50:31.43#ibcon#end of sib2, iclass 28, count 2 2006.257.04:50:31.43#ibcon#*mode == 0, iclass 28, count 2 2006.257.04:50:31.43#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.04:50:31.43#ibcon#[25=AT04-07\r\n] 2006.257.04:50:31.43#ibcon#*before write, iclass 28, count 2 2006.257.04:50:31.43#ibcon#enter sib2, iclass 28, count 2 2006.257.04:50:31.43#ibcon#flushed, iclass 28, count 2 2006.257.04:50:31.43#ibcon#about to write, iclass 28, count 2 2006.257.04:50:31.43#ibcon#wrote, iclass 28, count 2 2006.257.04:50:31.43#ibcon#about to read 3, iclass 28, count 2 2006.257.04:50:31.46#ibcon#read 3, iclass 28, count 2 2006.257.04:50:31.46#ibcon#about to read 4, iclass 28, count 2 2006.257.04:50:31.46#ibcon#read 4, iclass 28, count 2 2006.257.04:50:31.46#ibcon#about to read 5, iclass 28, count 2 2006.257.04:50:31.46#ibcon#read 5, iclass 28, count 2 2006.257.04:50:31.46#ibcon#about to read 6, iclass 28, count 2 2006.257.04:50:31.46#ibcon#read 6, iclass 28, count 2 2006.257.04:50:31.46#ibcon#end of sib2, iclass 28, count 2 2006.257.04:50:31.46#ibcon#*after write, iclass 28, count 2 2006.257.04:50:31.46#ibcon#*before return 0, iclass 28, count 2 2006.257.04:50:31.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:31.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:31.46#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.04:50:31.46#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:31.46#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:31.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:31.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:31.58#ibcon#enter wrdev, iclass 28, count 0 2006.257.04:50:31.58#ibcon#first serial, iclass 28, count 0 2006.257.04:50:31.58#ibcon#enter sib2, iclass 28, count 0 2006.257.04:50:31.58#ibcon#flushed, iclass 28, count 0 2006.257.04:50:31.58#ibcon#about to write, iclass 28, count 0 2006.257.04:50:31.58#ibcon#wrote, iclass 28, count 0 2006.257.04:50:31.58#ibcon#about to read 3, iclass 28, count 0 2006.257.04:50:31.60#ibcon#read 3, iclass 28, count 0 2006.257.04:50:31.60#ibcon#about to read 4, iclass 28, count 0 2006.257.04:50:31.60#ibcon#read 4, iclass 28, count 0 2006.257.04:50:31.60#ibcon#about to read 5, iclass 28, count 0 2006.257.04:50:31.60#ibcon#read 5, iclass 28, count 0 2006.257.04:50:31.60#ibcon#about to read 6, iclass 28, count 0 2006.257.04:50:31.60#ibcon#read 6, iclass 28, count 0 2006.257.04:50:31.60#ibcon#end of sib2, iclass 28, count 0 2006.257.04:50:31.60#ibcon#*mode == 0, iclass 28, count 0 2006.257.04:50:31.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.04:50:31.60#ibcon#[25=USB\r\n] 2006.257.04:50:31.60#ibcon#*before write, iclass 28, count 0 2006.257.04:50:31.60#ibcon#enter sib2, iclass 28, count 0 2006.257.04:50:31.60#ibcon#flushed, iclass 28, count 0 2006.257.04:50:31.60#ibcon#about to write, iclass 28, count 0 2006.257.04:50:31.60#ibcon#wrote, iclass 28, count 0 2006.257.04:50:31.60#ibcon#about to read 3, iclass 28, count 0 2006.257.04:50:31.63#ibcon#read 3, iclass 28, count 0 2006.257.04:50:31.63#ibcon#about to read 4, iclass 28, count 0 2006.257.04:50:31.63#ibcon#read 4, iclass 28, count 0 2006.257.04:50:31.63#ibcon#about to read 5, iclass 28, count 0 2006.257.04:50:31.63#ibcon#read 5, iclass 28, count 0 2006.257.04:50:31.63#ibcon#about to read 6, iclass 28, count 0 2006.257.04:50:31.63#ibcon#read 6, iclass 28, count 0 2006.257.04:50:31.63#ibcon#end of sib2, iclass 28, count 0 2006.257.04:50:31.63#ibcon#*after write, iclass 28, count 0 2006.257.04:50:31.63#ibcon#*before return 0, iclass 28, count 0 2006.257.04:50:31.63#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:31.63#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:31.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.04:50:31.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.04:50:31.64$vck44/valo=5,734.99 2006.257.04:50:31.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.04:50:31.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.04:50:31.64#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:31.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:31.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:31.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:31.64#ibcon#enter wrdev, iclass 30, count 0 2006.257.04:50:31.64#ibcon#first serial, iclass 30, count 0 2006.257.04:50:31.64#ibcon#enter sib2, iclass 30, count 0 2006.257.04:50:31.64#ibcon#flushed, iclass 30, count 0 2006.257.04:50:31.64#ibcon#about to write, iclass 30, count 0 2006.257.04:50:31.64#ibcon#wrote, iclass 30, count 0 2006.257.04:50:31.64#ibcon#about to read 3, iclass 30, count 0 2006.257.04:50:31.65#ibcon#read 3, iclass 30, count 0 2006.257.04:50:31.65#ibcon#about to read 4, iclass 30, count 0 2006.257.04:50:31.65#ibcon#read 4, iclass 30, count 0 2006.257.04:50:31.65#ibcon#about to read 5, iclass 30, count 0 2006.257.04:50:31.65#ibcon#read 5, iclass 30, count 0 2006.257.04:50:31.65#ibcon#about to read 6, iclass 30, count 0 2006.257.04:50:31.65#ibcon#read 6, iclass 30, count 0 2006.257.04:50:31.65#ibcon#end of sib2, iclass 30, count 0 2006.257.04:50:31.65#ibcon#*mode == 0, iclass 30, count 0 2006.257.04:50:31.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.04:50:31.65#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.04:50:31.65#ibcon#*before write, iclass 30, count 0 2006.257.04:50:31.65#ibcon#enter sib2, iclass 30, count 0 2006.257.04:50:31.65#ibcon#flushed, iclass 30, count 0 2006.257.04:50:31.65#ibcon#about to write, iclass 30, count 0 2006.257.04:50:31.65#ibcon#wrote, iclass 30, count 0 2006.257.04:50:31.66#ibcon#about to read 3, iclass 30, count 0 2006.257.04:50:31.69#ibcon#read 3, iclass 30, count 0 2006.257.04:50:31.69#ibcon#about to read 4, iclass 30, count 0 2006.257.04:50:31.69#ibcon#read 4, iclass 30, count 0 2006.257.04:50:31.69#ibcon#about to read 5, iclass 30, count 0 2006.257.04:50:31.69#ibcon#read 5, iclass 30, count 0 2006.257.04:50:31.69#ibcon#about to read 6, iclass 30, count 0 2006.257.04:50:31.69#ibcon#read 6, iclass 30, count 0 2006.257.04:50:31.69#ibcon#end of sib2, iclass 30, count 0 2006.257.04:50:31.69#ibcon#*after write, iclass 30, count 0 2006.257.04:50:31.69#ibcon#*before return 0, iclass 30, count 0 2006.257.04:50:31.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:31.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:31.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.04:50:31.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.04:50:31.70$vck44/va=5,4 2006.257.04:50:31.70#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.04:50:31.70#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.04:50:31.70#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:31.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:31.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:31.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:31.74#ibcon#enter wrdev, iclass 32, count 2 2006.257.04:50:31.74#ibcon#first serial, iclass 32, count 2 2006.257.04:50:31.74#ibcon#enter sib2, iclass 32, count 2 2006.257.04:50:31.74#ibcon#flushed, iclass 32, count 2 2006.257.04:50:31.74#ibcon#about to write, iclass 32, count 2 2006.257.04:50:31.74#ibcon#wrote, iclass 32, count 2 2006.257.04:50:31.74#ibcon#about to read 3, iclass 32, count 2 2006.257.04:50:31.76#ibcon#read 3, iclass 32, count 2 2006.257.04:50:31.76#ibcon#about to read 4, iclass 32, count 2 2006.257.04:50:31.76#ibcon#read 4, iclass 32, count 2 2006.257.04:50:31.76#ibcon#about to read 5, iclass 32, count 2 2006.257.04:50:31.76#ibcon#read 5, iclass 32, count 2 2006.257.04:50:31.76#ibcon#about to read 6, iclass 32, count 2 2006.257.04:50:31.76#ibcon#read 6, iclass 32, count 2 2006.257.04:50:31.76#ibcon#end of sib2, iclass 32, count 2 2006.257.04:50:31.76#ibcon#*mode == 0, iclass 32, count 2 2006.257.04:50:31.76#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.04:50:31.76#ibcon#[25=AT05-04\r\n] 2006.257.04:50:31.76#ibcon#*before write, iclass 32, count 2 2006.257.04:50:31.76#ibcon#enter sib2, iclass 32, count 2 2006.257.04:50:31.76#ibcon#flushed, iclass 32, count 2 2006.257.04:50:31.76#ibcon#about to write, iclass 32, count 2 2006.257.04:50:31.76#ibcon#wrote, iclass 32, count 2 2006.257.04:50:31.76#ibcon#about to read 3, iclass 32, count 2 2006.257.04:50:31.79#ibcon#read 3, iclass 32, count 2 2006.257.04:50:31.79#ibcon#about to read 4, iclass 32, count 2 2006.257.04:50:31.79#ibcon#read 4, iclass 32, count 2 2006.257.04:50:31.79#ibcon#about to read 5, iclass 32, count 2 2006.257.04:50:31.79#ibcon#read 5, iclass 32, count 2 2006.257.04:50:31.79#ibcon#about to read 6, iclass 32, count 2 2006.257.04:50:31.79#ibcon#read 6, iclass 32, count 2 2006.257.04:50:31.79#ibcon#end of sib2, iclass 32, count 2 2006.257.04:50:31.79#ibcon#*after write, iclass 32, count 2 2006.257.04:50:31.79#ibcon#*before return 0, iclass 32, count 2 2006.257.04:50:31.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:31.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:31.79#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.04:50:31.79#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:31.79#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:31.91#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:31.91#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:31.91#ibcon#enter wrdev, iclass 32, count 0 2006.257.04:50:31.91#ibcon#first serial, iclass 32, count 0 2006.257.04:50:31.91#ibcon#enter sib2, iclass 32, count 0 2006.257.04:50:31.91#ibcon#flushed, iclass 32, count 0 2006.257.04:50:31.91#ibcon#about to write, iclass 32, count 0 2006.257.04:50:31.91#ibcon#wrote, iclass 32, count 0 2006.257.04:50:31.91#ibcon#about to read 3, iclass 32, count 0 2006.257.04:50:31.93#ibcon#read 3, iclass 32, count 0 2006.257.04:50:31.93#ibcon#about to read 4, iclass 32, count 0 2006.257.04:50:31.93#ibcon#read 4, iclass 32, count 0 2006.257.04:50:31.93#ibcon#about to read 5, iclass 32, count 0 2006.257.04:50:31.93#ibcon#read 5, iclass 32, count 0 2006.257.04:50:31.93#ibcon#about to read 6, iclass 32, count 0 2006.257.04:50:31.93#ibcon#read 6, iclass 32, count 0 2006.257.04:50:31.93#ibcon#end of sib2, iclass 32, count 0 2006.257.04:50:31.93#ibcon#*mode == 0, iclass 32, count 0 2006.257.04:50:31.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.04:50:31.93#ibcon#[25=USB\r\n] 2006.257.04:50:31.93#ibcon#*before write, iclass 32, count 0 2006.257.04:50:31.93#ibcon#enter sib2, iclass 32, count 0 2006.257.04:50:31.93#ibcon#flushed, iclass 32, count 0 2006.257.04:50:31.93#ibcon#about to write, iclass 32, count 0 2006.257.04:50:31.93#ibcon#wrote, iclass 32, count 0 2006.257.04:50:31.93#ibcon#about to read 3, iclass 32, count 0 2006.257.04:50:31.96#ibcon#read 3, iclass 32, count 0 2006.257.04:50:31.96#ibcon#about to read 4, iclass 32, count 0 2006.257.04:50:31.96#ibcon#read 4, iclass 32, count 0 2006.257.04:50:31.96#ibcon#about to read 5, iclass 32, count 0 2006.257.04:50:31.96#ibcon#read 5, iclass 32, count 0 2006.257.04:50:31.96#ibcon#about to read 6, iclass 32, count 0 2006.257.04:50:31.96#ibcon#read 6, iclass 32, count 0 2006.257.04:50:31.96#ibcon#end of sib2, iclass 32, count 0 2006.257.04:50:31.96#ibcon#*after write, iclass 32, count 0 2006.257.04:50:31.96#ibcon#*before return 0, iclass 32, count 0 2006.257.04:50:31.96#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:31.96#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:31.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.04:50:31.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.04:50:31.97$vck44/valo=6,814.99 2006.257.04:50:31.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.04:50:31.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.04:50:31.97#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:31.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:31.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:31.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:31.97#ibcon#enter wrdev, iclass 34, count 0 2006.257.04:50:31.97#ibcon#first serial, iclass 34, count 0 2006.257.04:50:31.97#ibcon#enter sib2, iclass 34, count 0 2006.257.04:50:31.97#ibcon#flushed, iclass 34, count 0 2006.257.04:50:31.97#ibcon#about to write, iclass 34, count 0 2006.257.04:50:31.97#ibcon#wrote, iclass 34, count 0 2006.257.04:50:31.97#ibcon#about to read 3, iclass 34, count 0 2006.257.04:50:31.98#ibcon#read 3, iclass 34, count 0 2006.257.04:50:31.98#ibcon#about to read 4, iclass 34, count 0 2006.257.04:50:31.98#ibcon#read 4, iclass 34, count 0 2006.257.04:50:31.98#ibcon#about to read 5, iclass 34, count 0 2006.257.04:50:31.98#ibcon#read 5, iclass 34, count 0 2006.257.04:50:31.98#ibcon#about to read 6, iclass 34, count 0 2006.257.04:50:31.98#ibcon#read 6, iclass 34, count 0 2006.257.04:50:31.98#ibcon#end of sib2, iclass 34, count 0 2006.257.04:50:31.98#ibcon#*mode == 0, iclass 34, count 0 2006.257.04:50:31.98#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.04:50:31.98#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.04:50:31.98#ibcon#*before write, iclass 34, count 0 2006.257.04:50:31.98#ibcon#enter sib2, iclass 34, count 0 2006.257.04:50:31.98#ibcon#flushed, iclass 34, count 0 2006.257.04:50:31.98#ibcon#about to write, iclass 34, count 0 2006.257.04:50:31.98#ibcon#wrote, iclass 34, count 0 2006.257.04:50:31.98#ibcon#about to read 3, iclass 34, count 0 2006.257.04:50:32.02#ibcon#read 3, iclass 34, count 0 2006.257.04:50:32.02#ibcon#about to read 4, iclass 34, count 0 2006.257.04:50:32.02#ibcon#read 4, iclass 34, count 0 2006.257.04:50:32.02#ibcon#about to read 5, iclass 34, count 0 2006.257.04:50:32.02#ibcon#read 5, iclass 34, count 0 2006.257.04:50:32.02#ibcon#about to read 6, iclass 34, count 0 2006.257.04:50:32.02#ibcon#read 6, iclass 34, count 0 2006.257.04:50:32.02#ibcon#end of sib2, iclass 34, count 0 2006.257.04:50:32.02#ibcon#*after write, iclass 34, count 0 2006.257.04:50:32.02#ibcon#*before return 0, iclass 34, count 0 2006.257.04:50:32.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:32.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:32.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.04:50:32.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.04:50:32.03$vck44/va=6,4 2006.257.04:50:32.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.04:50:32.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.04:50:32.03#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:32.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:32.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:32.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:32.07#ibcon#enter wrdev, iclass 36, count 2 2006.257.04:50:32.07#ibcon#first serial, iclass 36, count 2 2006.257.04:50:32.07#ibcon#enter sib2, iclass 36, count 2 2006.257.04:50:32.07#ibcon#flushed, iclass 36, count 2 2006.257.04:50:32.07#ibcon#about to write, iclass 36, count 2 2006.257.04:50:32.07#ibcon#wrote, iclass 36, count 2 2006.257.04:50:32.07#ibcon#about to read 3, iclass 36, count 2 2006.257.04:50:32.09#ibcon#read 3, iclass 36, count 2 2006.257.04:50:32.09#ibcon#about to read 4, iclass 36, count 2 2006.257.04:50:32.09#ibcon#read 4, iclass 36, count 2 2006.257.04:50:32.09#ibcon#about to read 5, iclass 36, count 2 2006.257.04:50:32.09#ibcon#read 5, iclass 36, count 2 2006.257.04:50:32.09#ibcon#about to read 6, iclass 36, count 2 2006.257.04:50:32.09#ibcon#read 6, iclass 36, count 2 2006.257.04:50:32.09#ibcon#end of sib2, iclass 36, count 2 2006.257.04:50:32.09#ibcon#*mode == 0, iclass 36, count 2 2006.257.04:50:32.09#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.04:50:32.09#ibcon#[25=AT06-04\r\n] 2006.257.04:50:32.09#ibcon#*before write, iclass 36, count 2 2006.257.04:50:32.09#ibcon#enter sib2, iclass 36, count 2 2006.257.04:50:32.09#ibcon#flushed, iclass 36, count 2 2006.257.04:50:32.09#ibcon#about to write, iclass 36, count 2 2006.257.04:50:32.09#ibcon#wrote, iclass 36, count 2 2006.257.04:50:32.09#ibcon#about to read 3, iclass 36, count 2 2006.257.04:50:32.12#ibcon#read 3, iclass 36, count 2 2006.257.04:50:32.12#ibcon#about to read 4, iclass 36, count 2 2006.257.04:50:32.12#ibcon#read 4, iclass 36, count 2 2006.257.04:50:32.12#ibcon#about to read 5, iclass 36, count 2 2006.257.04:50:32.12#ibcon#read 5, iclass 36, count 2 2006.257.04:50:32.12#ibcon#about to read 6, iclass 36, count 2 2006.257.04:50:32.12#ibcon#read 6, iclass 36, count 2 2006.257.04:50:32.12#ibcon#end of sib2, iclass 36, count 2 2006.257.04:50:32.12#ibcon#*after write, iclass 36, count 2 2006.257.04:50:32.12#ibcon#*before return 0, iclass 36, count 2 2006.257.04:50:32.12#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:32.12#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:32.12#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.04:50:32.12#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:32.12#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:32.24#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:32.24#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:32.24#ibcon#enter wrdev, iclass 36, count 0 2006.257.04:50:32.24#ibcon#first serial, iclass 36, count 0 2006.257.04:50:32.24#ibcon#enter sib2, iclass 36, count 0 2006.257.04:50:32.24#ibcon#flushed, iclass 36, count 0 2006.257.04:50:32.24#ibcon#about to write, iclass 36, count 0 2006.257.04:50:32.24#ibcon#wrote, iclass 36, count 0 2006.257.04:50:32.24#ibcon#about to read 3, iclass 36, count 0 2006.257.04:50:32.26#ibcon#read 3, iclass 36, count 0 2006.257.04:50:32.26#ibcon#about to read 4, iclass 36, count 0 2006.257.04:50:32.26#ibcon#read 4, iclass 36, count 0 2006.257.04:50:32.26#ibcon#about to read 5, iclass 36, count 0 2006.257.04:50:32.26#ibcon#read 5, iclass 36, count 0 2006.257.04:50:32.26#ibcon#about to read 6, iclass 36, count 0 2006.257.04:50:32.26#ibcon#read 6, iclass 36, count 0 2006.257.04:50:32.26#ibcon#end of sib2, iclass 36, count 0 2006.257.04:50:32.26#ibcon#*mode == 0, iclass 36, count 0 2006.257.04:50:32.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.04:50:32.26#ibcon#[25=USB\r\n] 2006.257.04:50:32.26#ibcon#*before write, iclass 36, count 0 2006.257.04:50:32.26#ibcon#enter sib2, iclass 36, count 0 2006.257.04:50:32.26#ibcon#flushed, iclass 36, count 0 2006.257.04:50:32.26#ibcon#about to write, iclass 36, count 0 2006.257.04:50:32.26#ibcon#wrote, iclass 36, count 0 2006.257.04:50:32.26#ibcon#about to read 3, iclass 36, count 0 2006.257.04:50:32.29#ibcon#read 3, iclass 36, count 0 2006.257.04:50:32.29#ibcon#about to read 4, iclass 36, count 0 2006.257.04:50:32.29#ibcon#read 4, iclass 36, count 0 2006.257.04:50:32.29#ibcon#about to read 5, iclass 36, count 0 2006.257.04:50:32.29#ibcon#read 5, iclass 36, count 0 2006.257.04:50:32.29#ibcon#about to read 6, iclass 36, count 0 2006.257.04:50:32.29#ibcon#read 6, iclass 36, count 0 2006.257.04:50:32.29#ibcon#end of sib2, iclass 36, count 0 2006.257.04:50:32.29#ibcon#*after write, iclass 36, count 0 2006.257.04:50:32.29#ibcon#*before return 0, iclass 36, count 0 2006.257.04:50:32.29#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:32.29#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:32.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.04:50:32.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.04:50:32.30$vck44/valo=7,864.99 2006.257.04:50:32.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.04:50:32.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.04:50:32.30#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:32.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:32.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:32.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:32.30#ibcon#enter wrdev, iclass 38, count 0 2006.257.04:50:32.30#ibcon#first serial, iclass 38, count 0 2006.257.04:50:32.30#ibcon#enter sib2, iclass 38, count 0 2006.257.04:50:32.30#ibcon#flushed, iclass 38, count 0 2006.257.04:50:32.30#ibcon#about to write, iclass 38, count 0 2006.257.04:50:32.30#ibcon#wrote, iclass 38, count 0 2006.257.04:50:32.30#ibcon#about to read 3, iclass 38, count 0 2006.257.04:50:32.31#ibcon#read 3, iclass 38, count 0 2006.257.04:50:32.31#ibcon#about to read 4, iclass 38, count 0 2006.257.04:50:32.31#ibcon#read 4, iclass 38, count 0 2006.257.04:50:32.31#ibcon#about to read 5, iclass 38, count 0 2006.257.04:50:32.31#ibcon#read 5, iclass 38, count 0 2006.257.04:50:32.31#ibcon#about to read 6, iclass 38, count 0 2006.257.04:50:32.31#ibcon#read 6, iclass 38, count 0 2006.257.04:50:32.31#ibcon#end of sib2, iclass 38, count 0 2006.257.04:50:32.31#ibcon#*mode == 0, iclass 38, count 0 2006.257.04:50:32.31#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.04:50:32.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.04:50:32.31#ibcon#*before write, iclass 38, count 0 2006.257.04:50:32.31#ibcon#enter sib2, iclass 38, count 0 2006.257.04:50:32.31#ibcon#flushed, iclass 38, count 0 2006.257.04:50:32.31#ibcon#about to write, iclass 38, count 0 2006.257.04:50:32.31#ibcon#wrote, iclass 38, count 0 2006.257.04:50:32.31#ibcon#about to read 3, iclass 38, count 0 2006.257.04:50:32.35#ibcon#read 3, iclass 38, count 0 2006.257.04:50:32.35#ibcon#about to read 4, iclass 38, count 0 2006.257.04:50:32.35#ibcon#read 4, iclass 38, count 0 2006.257.04:50:32.35#ibcon#about to read 5, iclass 38, count 0 2006.257.04:50:32.35#ibcon#read 5, iclass 38, count 0 2006.257.04:50:32.35#ibcon#about to read 6, iclass 38, count 0 2006.257.04:50:32.35#ibcon#read 6, iclass 38, count 0 2006.257.04:50:32.35#ibcon#end of sib2, iclass 38, count 0 2006.257.04:50:32.35#ibcon#*after write, iclass 38, count 0 2006.257.04:50:32.35#ibcon#*before return 0, iclass 38, count 0 2006.257.04:50:32.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:32.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:32.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.04:50:32.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.04:50:32.36$vck44/va=7,4 2006.257.04:50:32.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.04:50:32.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.04:50:32.36#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:32.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:50:32.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:50:32.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:50:32.40#ibcon#enter wrdev, iclass 40, count 2 2006.257.04:50:32.40#ibcon#first serial, iclass 40, count 2 2006.257.04:50:32.40#ibcon#enter sib2, iclass 40, count 2 2006.257.04:50:32.40#ibcon#flushed, iclass 40, count 2 2006.257.04:50:32.40#ibcon#about to write, iclass 40, count 2 2006.257.04:50:32.40#ibcon#wrote, iclass 40, count 2 2006.257.04:50:32.40#ibcon#about to read 3, iclass 40, count 2 2006.257.04:50:32.42#ibcon#read 3, iclass 40, count 2 2006.257.04:50:32.42#ibcon#about to read 4, iclass 40, count 2 2006.257.04:50:32.42#ibcon#read 4, iclass 40, count 2 2006.257.04:50:32.42#ibcon#about to read 5, iclass 40, count 2 2006.257.04:50:32.42#ibcon#read 5, iclass 40, count 2 2006.257.04:50:32.42#ibcon#about to read 6, iclass 40, count 2 2006.257.04:50:32.42#ibcon#read 6, iclass 40, count 2 2006.257.04:50:32.42#ibcon#end of sib2, iclass 40, count 2 2006.257.04:50:32.42#ibcon#*mode == 0, iclass 40, count 2 2006.257.04:50:32.42#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.04:50:32.42#ibcon#[25=AT07-04\r\n] 2006.257.04:50:32.42#ibcon#*before write, iclass 40, count 2 2006.257.04:50:32.42#ibcon#enter sib2, iclass 40, count 2 2006.257.04:50:32.42#ibcon#flushed, iclass 40, count 2 2006.257.04:50:32.42#ibcon#about to write, iclass 40, count 2 2006.257.04:50:32.42#ibcon#wrote, iclass 40, count 2 2006.257.04:50:32.42#ibcon#about to read 3, iclass 40, count 2 2006.257.04:50:32.45#ibcon#read 3, iclass 40, count 2 2006.257.04:50:32.45#ibcon#about to read 4, iclass 40, count 2 2006.257.04:50:32.45#ibcon#read 4, iclass 40, count 2 2006.257.04:50:32.45#ibcon#about to read 5, iclass 40, count 2 2006.257.04:50:32.45#ibcon#read 5, iclass 40, count 2 2006.257.04:50:32.45#ibcon#about to read 6, iclass 40, count 2 2006.257.04:50:32.45#ibcon#read 6, iclass 40, count 2 2006.257.04:50:32.45#ibcon#end of sib2, iclass 40, count 2 2006.257.04:50:32.45#ibcon#*after write, iclass 40, count 2 2006.257.04:50:32.45#ibcon#*before return 0, iclass 40, count 2 2006.257.04:50:32.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:50:32.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.04:50:32.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.04:50:32.45#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:32.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:50:32.57#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:50:32.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:50:32.57#ibcon#enter wrdev, iclass 40, count 0 2006.257.04:50:32.57#ibcon#first serial, iclass 40, count 0 2006.257.04:50:32.57#ibcon#enter sib2, iclass 40, count 0 2006.257.04:50:32.57#ibcon#flushed, iclass 40, count 0 2006.257.04:50:32.57#ibcon#about to write, iclass 40, count 0 2006.257.04:50:32.57#ibcon#wrote, iclass 40, count 0 2006.257.04:50:32.57#ibcon#about to read 3, iclass 40, count 0 2006.257.04:50:32.59#ibcon#read 3, iclass 40, count 0 2006.257.04:50:32.59#ibcon#about to read 4, iclass 40, count 0 2006.257.04:50:32.59#ibcon#read 4, iclass 40, count 0 2006.257.04:50:32.59#ibcon#about to read 5, iclass 40, count 0 2006.257.04:50:32.59#ibcon#read 5, iclass 40, count 0 2006.257.04:50:32.59#ibcon#about to read 6, iclass 40, count 0 2006.257.04:50:32.59#ibcon#read 6, iclass 40, count 0 2006.257.04:50:32.59#ibcon#end of sib2, iclass 40, count 0 2006.257.04:50:32.59#ibcon#*mode == 0, iclass 40, count 0 2006.257.04:50:32.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.04:50:32.59#ibcon#[25=USB\r\n] 2006.257.04:50:32.59#ibcon#*before write, iclass 40, count 0 2006.257.04:50:32.59#ibcon#enter sib2, iclass 40, count 0 2006.257.04:50:32.59#ibcon#flushed, iclass 40, count 0 2006.257.04:50:32.60#ibcon#about to write, iclass 40, count 0 2006.257.04:50:32.60#ibcon#wrote, iclass 40, count 0 2006.257.04:50:32.60#ibcon#about to read 3, iclass 40, count 0 2006.257.04:50:32.62#ibcon#read 3, iclass 40, count 0 2006.257.04:50:32.62#ibcon#about to read 4, iclass 40, count 0 2006.257.04:50:32.62#ibcon#read 4, iclass 40, count 0 2006.257.04:50:32.62#ibcon#about to read 5, iclass 40, count 0 2006.257.04:50:32.62#ibcon#read 5, iclass 40, count 0 2006.257.04:50:32.62#ibcon#about to read 6, iclass 40, count 0 2006.257.04:50:32.62#ibcon#read 6, iclass 40, count 0 2006.257.04:50:32.62#ibcon#end of sib2, iclass 40, count 0 2006.257.04:50:32.62#ibcon#*after write, iclass 40, count 0 2006.257.04:50:32.62#ibcon#*before return 0, iclass 40, count 0 2006.257.04:50:32.62#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:50:32.62#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.04:50:32.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.04:50:32.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.04:50:32.63$vck44/valo=8,884.99 2006.257.04:50:32.63#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.04:50:32.63#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.04:50:32.63#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:32.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:50:32.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:50:32.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:50:32.63#ibcon#enter wrdev, iclass 4, count 0 2006.257.04:50:32.63#ibcon#first serial, iclass 4, count 0 2006.257.04:50:32.63#ibcon#enter sib2, iclass 4, count 0 2006.257.04:50:32.63#ibcon#flushed, iclass 4, count 0 2006.257.04:50:32.63#ibcon#about to write, iclass 4, count 0 2006.257.04:50:32.63#ibcon#wrote, iclass 4, count 0 2006.257.04:50:32.63#ibcon#about to read 3, iclass 4, count 0 2006.257.04:50:32.64#ibcon#read 3, iclass 4, count 0 2006.257.04:50:32.64#ibcon#about to read 4, iclass 4, count 0 2006.257.04:50:32.64#ibcon#read 4, iclass 4, count 0 2006.257.04:50:32.64#ibcon#about to read 5, iclass 4, count 0 2006.257.04:50:32.64#ibcon#read 5, iclass 4, count 0 2006.257.04:50:32.64#ibcon#about to read 6, iclass 4, count 0 2006.257.04:50:32.64#ibcon#read 6, iclass 4, count 0 2006.257.04:50:32.64#ibcon#end of sib2, iclass 4, count 0 2006.257.04:50:32.64#ibcon#*mode == 0, iclass 4, count 0 2006.257.04:50:32.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.04:50:32.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.04:50:32.64#ibcon#*before write, iclass 4, count 0 2006.257.04:50:32.64#ibcon#enter sib2, iclass 4, count 0 2006.257.04:50:32.64#ibcon#flushed, iclass 4, count 0 2006.257.04:50:32.64#ibcon#about to write, iclass 4, count 0 2006.257.04:50:32.65#ibcon#wrote, iclass 4, count 0 2006.257.04:50:32.65#ibcon#about to read 3, iclass 4, count 0 2006.257.04:50:32.68#ibcon#read 3, iclass 4, count 0 2006.257.04:50:32.68#ibcon#about to read 4, iclass 4, count 0 2006.257.04:50:32.68#ibcon#read 4, iclass 4, count 0 2006.257.04:50:32.68#ibcon#about to read 5, iclass 4, count 0 2006.257.04:50:32.68#ibcon#read 5, iclass 4, count 0 2006.257.04:50:32.68#ibcon#about to read 6, iclass 4, count 0 2006.257.04:50:32.68#ibcon#read 6, iclass 4, count 0 2006.257.04:50:32.68#ibcon#end of sib2, iclass 4, count 0 2006.257.04:50:32.68#ibcon#*after write, iclass 4, count 0 2006.257.04:50:32.68#ibcon#*before return 0, iclass 4, count 0 2006.257.04:50:32.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:50:32.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.04:50:32.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.04:50:32.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.04:50:32.69$vck44/va=8,4 2006.257.04:50:32.69#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.04:50:32.69#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.04:50:32.69#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:32.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:50:32.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:50:32.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:50:32.73#ibcon#enter wrdev, iclass 6, count 2 2006.257.04:50:32.73#ibcon#first serial, iclass 6, count 2 2006.257.04:50:32.73#ibcon#enter sib2, iclass 6, count 2 2006.257.04:50:32.73#ibcon#flushed, iclass 6, count 2 2006.257.04:50:32.73#ibcon#about to write, iclass 6, count 2 2006.257.04:50:32.73#ibcon#wrote, iclass 6, count 2 2006.257.04:50:32.73#ibcon#about to read 3, iclass 6, count 2 2006.257.04:50:32.75#ibcon#read 3, iclass 6, count 2 2006.257.04:50:32.75#ibcon#about to read 4, iclass 6, count 2 2006.257.04:50:32.75#ibcon#read 4, iclass 6, count 2 2006.257.04:50:32.75#ibcon#about to read 5, iclass 6, count 2 2006.257.04:50:32.75#ibcon#read 5, iclass 6, count 2 2006.257.04:50:32.75#ibcon#about to read 6, iclass 6, count 2 2006.257.04:50:32.75#ibcon#read 6, iclass 6, count 2 2006.257.04:50:32.75#ibcon#end of sib2, iclass 6, count 2 2006.257.04:50:32.75#ibcon#*mode == 0, iclass 6, count 2 2006.257.04:50:32.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.04:50:32.75#ibcon#[25=AT08-04\r\n] 2006.257.04:50:32.75#ibcon#*before write, iclass 6, count 2 2006.257.04:50:32.75#ibcon#enter sib2, iclass 6, count 2 2006.257.04:50:32.75#ibcon#flushed, iclass 6, count 2 2006.257.04:50:32.75#ibcon#about to write, iclass 6, count 2 2006.257.04:50:32.75#ibcon#wrote, iclass 6, count 2 2006.257.04:50:32.76#ibcon#about to read 3, iclass 6, count 2 2006.257.04:50:32.78#ibcon#read 3, iclass 6, count 2 2006.257.04:50:32.78#ibcon#about to read 4, iclass 6, count 2 2006.257.04:50:32.78#ibcon#read 4, iclass 6, count 2 2006.257.04:50:32.78#ibcon#about to read 5, iclass 6, count 2 2006.257.04:50:32.78#ibcon#read 5, iclass 6, count 2 2006.257.04:50:32.78#ibcon#about to read 6, iclass 6, count 2 2006.257.04:50:32.78#ibcon#read 6, iclass 6, count 2 2006.257.04:50:32.78#ibcon#end of sib2, iclass 6, count 2 2006.257.04:50:32.78#ibcon#*after write, iclass 6, count 2 2006.257.04:50:32.78#ibcon#*before return 0, iclass 6, count 2 2006.257.04:50:32.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:50:32.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.04:50:32.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.04:50:32.78#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:32.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:50:32.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:50:32.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:50:32.90#ibcon#enter wrdev, iclass 6, count 0 2006.257.04:50:32.90#ibcon#first serial, iclass 6, count 0 2006.257.04:50:32.90#ibcon#enter sib2, iclass 6, count 0 2006.257.04:50:32.90#ibcon#flushed, iclass 6, count 0 2006.257.04:50:32.90#ibcon#about to write, iclass 6, count 0 2006.257.04:50:32.90#ibcon#wrote, iclass 6, count 0 2006.257.04:50:32.90#ibcon#about to read 3, iclass 6, count 0 2006.257.04:50:32.92#ibcon#read 3, iclass 6, count 0 2006.257.04:50:32.92#ibcon#about to read 4, iclass 6, count 0 2006.257.04:50:32.92#ibcon#read 4, iclass 6, count 0 2006.257.04:50:32.92#ibcon#about to read 5, iclass 6, count 0 2006.257.04:50:32.92#ibcon#read 5, iclass 6, count 0 2006.257.04:50:32.92#ibcon#about to read 6, iclass 6, count 0 2006.257.04:50:32.92#ibcon#read 6, iclass 6, count 0 2006.257.04:50:32.92#ibcon#end of sib2, iclass 6, count 0 2006.257.04:50:32.92#ibcon#*mode == 0, iclass 6, count 0 2006.257.04:50:32.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.04:50:32.92#ibcon#[25=USB\r\n] 2006.257.04:50:32.92#ibcon#*before write, iclass 6, count 0 2006.257.04:50:32.92#ibcon#enter sib2, iclass 6, count 0 2006.257.04:50:32.92#ibcon#flushed, iclass 6, count 0 2006.257.04:50:32.92#ibcon#about to write, iclass 6, count 0 2006.257.04:50:32.92#ibcon#wrote, iclass 6, count 0 2006.257.04:50:32.92#ibcon#about to read 3, iclass 6, count 0 2006.257.04:50:32.95#ibcon#read 3, iclass 6, count 0 2006.257.04:50:32.95#ibcon#about to read 4, iclass 6, count 0 2006.257.04:50:32.95#ibcon#read 4, iclass 6, count 0 2006.257.04:50:32.95#ibcon#about to read 5, iclass 6, count 0 2006.257.04:50:32.95#ibcon#read 5, iclass 6, count 0 2006.257.04:50:32.95#ibcon#about to read 6, iclass 6, count 0 2006.257.04:50:32.95#ibcon#read 6, iclass 6, count 0 2006.257.04:50:32.95#ibcon#end of sib2, iclass 6, count 0 2006.257.04:50:32.95#ibcon#*after write, iclass 6, count 0 2006.257.04:50:32.95#ibcon#*before return 0, iclass 6, count 0 2006.257.04:50:32.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:50:32.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.04:50:32.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.04:50:32.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.04:50:32.96$vck44/vblo=1,629.99 2006.257.04:50:32.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.04:50:32.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.04:50:32.96#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:32.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:32.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:32.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:32.96#ibcon#enter wrdev, iclass 10, count 0 2006.257.04:50:32.96#ibcon#first serial, iclass 10, count 0 2006.257.04:50:32.96#ibcon#enter sib2, iclass 10, count 0 2006.257.04:50:32.96#ibcon#flushed, iclass 10, count 0 2006.257.04:50:32.96#ibcon#about to write, iclass 10, count 0 2006.257.04:50:32.96#ibcon#wrote, iclass 10, count 0 2006.257.04:50:32.96#ibcon#about to read 3, iclass 10, count 0 2006.257.04:50:32.97#ibcon#read 3, iclass 10, count 0 2006.257.04:50:32.97#ibcon#about to read 4, iclass 10, count 0 2006.257.04:50:32.97#ibcon#read 4, iclass 10, count 0 2006.257.04:50:32.97#ibcon#about to read 5, iclass 10, count 0 2006.257.04:50:32.97#ibcon#read 5, iclass 10, count 0 2006.257.04:50:32.97#ibcon#about to read 6, iclass 10, count 0 2006.257.04:50:32.97#ibcon#read 6, iclass 10, count 0 2006.257.04:50:32.97#ibcon#end of sib2, iclass 10, count 0 2006.257.04:50:32.97#ibcon#*mode == 0, iclass 10, count 0 2006.257.04:50:32.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.04:50:32.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.04:50:32.97#ibcon#*before write, iclass 10, count 0 2006.257.04:50:32.97#ibcon#enter sib2, iclass 10, count 0 2006.257.04:50:32.97#ibcon#flushed, iclass 10, count 0 2006.257.04:50:32.97#ibcon#about to write, iclass 10, count 0 2006.257.04:50:32.97#ibcon#wrote, iclass 10, count 0 2006.257.04:50:32.97#ibcon#about to read 3, iclass 10, count 0 2006.257.04:50:33.01#ibcon#read 3, iclass 10, count 0 2006.257.04:50:33.01#ibcon#about to read 4, iclass 10, count 0 2006.257.04:50:33.01#ibcon#read 4, iclass 10, count 0 2006.257.04:50:33.01#ibcon#about to read 5, iclass 10, count 0 2006.257.04:50:33.01#ibcon#read 5, iclass 10, count 0 2006.257.04:50:33.01#ibcon#about to read 6, iclass 10, count 0 2006.257.04:50:33.01#ibcon#read 6, iclass 10, count 0 2006.257.04:50:33.01#ibcon#end of sib2, iclass 10, count 0 2006.257.04:50:33.01#ibcon#*after write, iclass 10, count 0 2006.257.04:50:33.01#ibcon#*before return 0, iclass 10, count 0 2006.257.04:50:33.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:33.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:33.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.04:50:33.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.04:50:33.02$vck44/vb=1,4 2006.257.04:50:33.02#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.04:50:33.02#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.04:50:33.02#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:33.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:50:33.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:50:33.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:50:33.02#ibcon#enter wrdev, iclass 12, count 2 2006.257.04:50:33.02#ibcon#first serial, iclass 12, count 2 2006.257.04:50:33.02#ibcon#enter sib2, iclass 12, count 2 2006.257.04:50:33.02#ibcon#flushed, iclass 12, count 2 2006.257.04:50:33.02#ibcon#about to write, iclass 12, count 2 2006.257.04:50:33.02#ibcon#wrote, iclass 12, count 2 2006.257.04:50:33.02#ibcon#about to read 3, iclass 12, count 2 2006.257.04:50:33.03#ibcon#read 3, iclass 12, count 2 2006.257.04:50:33.03#ibcon#about to read 4, iclass 12, count 2 2006.257.04:50:33.03#ibcon#read 4, iclass 12, count 2 2006.257.04:50:33.03#ibcon#about to read 5, iclass 12, count 2 2006.257.04:50:33.03#ibcon#read 5, iclass 12, count 2 2006.257.04:50:33.03#ibcon#about to read 6, iclass 12, count 2 2006.257.04:50:33.03#ibcon#read 6, iclass 12, count 2 2006.257.04:50:33.03#ibcon#end of sib2, iclass 12, count 2 2006.257.04:50:33.03#ibcon#*mode == 0, iclass 12, count 2 2006.257.04:50:33.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.04:50:33.03#ibcon#[27=AT01-04\r\n] 2006.257.04:50:33.03#ibcon#*before write, iclass 12, count 2 2006.257.04:50:33.03#ibcon#enter sib2, iclass 12, count 2 2006.257.04:50:33.03#ibcon#flushed, iclass 12, count 2 2006.257.04:50:33.03#ibcon#about to write, iclass 12, count 2 2006.257.04:50:33.03#ibcon#wrote, iclass 12, count 2 2006.257.04:50:33.03#ibcon#about to read 3, iclass 12, count 2 2006.257.04:50:33.06#ibcon#read 3, iclass 12, count 2 2006.257.04:50:33.06#ibcon#about to read 4, iclass 12, count 2 2006.257.04:50:33.06#ibcon#read 4, iclass 12, count 2 2006.257.04:50:33.06#ibcon#about to read 5, iclass 12, count 2 2006.257.04:50:33.06#ibcon#read 5, iclass 12, count 2 2006.257.04:50:33.06#ibcon#about to read 6, iclass 12, count 2 2006.257.04:50:33.06#ibcon#read 6, iclass 12, count 2 2006.257.04:50:33.06#ibcon#end of sib2, iclass 12, count 2 2006.257.04:50:33.06#ibcon#*after write, iclass 12, count 2 2006.257.04:50:33.06#ibcon#*before return 0, iclass 12, count 2 2006.257.04:50:33.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:50:33.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.04:50:33.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.04:50:33.06#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:33.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:50:33.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:50:33.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:50:33.18#ibcon#enter wrdev, iclass 12, count 0 2006.257.04:50:33.18#ibcon#first serial, iclass 12, count 0 2006.257.04:50:33.18#ibcon#enter sib2, iclass 12, count 0 2006.257.04:50:33.18#ibcon#flushed, iclass 12, count 0 2006.257.04:50:33.18#ibcon#about to write, iclass 12, count 0 2006.257.04:50:33.18#ibcon#wrote, iclass 12, count 0 2006.257.04:50:33.18#ibcon#about to read 3, iclass 12, count 0 2006.257.04:50:33.20#ibcon#read 3, iclass 12, count 0 2006.257.04:50:33.20#ibcon#about to read 4, iclass 12, count 0 2006.257.04:50:33.20#ibcon#read 4, iclass 12, count 0 2006.257.04:50:33.20#ibcon#about to read 5, iclass 12, count 0 2006.257.04:50:33.20#ibcon#read 5, iclass 12, count 0 2006.257.04:50:33.20#ibcon#about to read 6, iclass 12, count 0 2006.257.04:50:33.20#ibcon#read 6, iclass 12, count 0 2006.257.04:50:33.20#ibcon#end of sib2, iclass 12, count 0 2006.257.04:50:33.20#ibcon#*mode == 0, iclass 12, count 0 2006.257.04:50:33.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.04:50:33.20#ibcon#[27=USB\r\n] 2006.257.04:50:33.20#ibcon#*before write, iclass 12, count 0 2006.257.04:50:33.20#ibcon#enter sib2, iclass 12, count 0 2006.257.04:50:33.20#ibcon#flushed, iclass 12, count 0 2006.257.04:50:33.20#ibcon#about to write, iclass 12, count 0 2006.257.04:50:33.20#ibcon#wrote, iclass 12, count 0 2006.257.04:50:33.20#ibcon#about to read 3, iclass 12, count 0 2006.257.04:50:33.23#ibcon#read 3, iclass 12, count 0 2006.257.04:50:33.23#ibcon#about to read 4, iclass 12, count 0 2006.257.04:50:33.23#ibcon#read 4, iclass 12, count 0 2006.257.04:50:33.23#ibcon#about to read 5, iclass 12, count 0 2006.257.04:50:33.23#ibcon#read 5, iclass 12, count 0 2006.257.04:50:33.23#ibcon#about to read 6, iclass 12, count 0 2006.257.04:50:33.23#ibcon#read 6, iclass 12, count 0 2006.257.04:50:33.23#ibcon#end of sib2, iclass 12, count 0 2006.257.04:50:33.23#ibcon#*after write, iclass 12, count 0 2006.257.04:50:33.23#ibcon#*before return 0, iclass 12, count 0 2006.257.04:50:33.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:50:33.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.04:50:33.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.04:50:33.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.04:50:33.24$vck44/vblo=2,634.99 2006.257.04:50:33.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.04:50:33.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.04:50:33.24#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:33.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:33.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:33.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:33.24#ibcon#enter wrdev, iclass 14, count 0 2006.257.04:50:33.24#ibcon#first serial, iclass 14, count 0 2006.257.04:50:33.24#ibcon#enter sib2, iclass 14, count 0 2006.257.04:50:33.24#ibcon#flushed, iclass 14, count 0 2006.257.04:50:33.24#ibcon#about to write, iclass 14, count 0 2006.257.04:50:33.24#ibcon#wrote, iclass 14, count 0 2006.257.04:50:33.24#ibcon#about to read 3, iclass 14, count 0 2006.257.04:50:33.25#ibcon#read 3, iclass 14, count 0 2006.257.04:50:33.25#ibcon#about to read 4, iclass 14, count 0 2006.257.04:50:33.25#ibcon#read 4, iclass 14, count 0 2006.257.04:50:33.25#ibcon#about to read 5, iclass 14, count 0 2006.257.04:50:33.25#ibcon#read 5, iclass 14, count 0 2006.257.04:50:33.25#ibcon#about to read 6, iclass 14, count 0 2006.257.04:50:33.25#ibcon#read 6, iclass 14, count 0 2006.257.04:50:33.25#ibcon#end of sib2, iclass 14, count 0 2006.257.04:50:33.25#ibcon#*mode == 0, iclass 14, count 0 2006.257.04:50:33.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.04:50:33.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.04:50:33.25#ibcon#*before write, iclass 14, count 0 2006.257.04:50:33.25#ibcon#enter sib2, iclass 14, count 0 2006.257.04:50:33.25#ibcon#flushed, iclass 14, count 0 2006.257.04:50:33.25#ibcon#about to write, iclass 14, count 0 2006.257.04:50:33.25#ibcon#wrote, iclass 14, count 0 2006.257.04:50:33.26#ibcon#about to read 3, iclass 14, count 0 2006.257.04:50:33.29#ibcon#read 3, iclass 14, count 0 2006.257.04:50:33.29#ibcon#about to read 4, iclass 14, count 0 2006.257.04:50:33.29#ibcon#read 4, iclass 14, count 0 2006.257.04:50:33.29#ibcon#about to read 5, iclass 14, count 0 2006.257.04:50:33.29#ibcon#read 5, iclass 14, count 0 2006.257.04:50:33.29#ibcon#about to read 6, iclass 14, count 0 2006.257.04:50:33.29#ibcon#read 6, iclass 14, count 0 2006.257.04:50:33.29#ibcon#end of sib2, iclass 14, count 0 2006.257.04:50:33.29#ibcon#*after write, iclass 14, count 0 2006.257.04:50:33.29#ibcon#*before return 0, iclass 14, count 0 2006.257.04:50:33.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:33.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.04:50:33.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.04:50:33.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.04:50:33.30$vck44/vb=2,5 2006.257.04:50:33.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.04:50:33.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.04:50:33.30#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:33.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:33.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:33.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:33.34#ibcon#enter wrdev, iclass 16, count 2 2006.257.04:50:33.34#ibcon#first serial, iclass 16, count 2 2006.257.04:50:33.34#ibcon#enter sib2, iclass 16, count 2 2006.257.04:50:33.34#ibcon#flushed, iclass 16, count 2 2006.257.04:50:33.34#ibcon#about to write, iclass 16, count 2 2006.257.04:50:33.34#ibcon#wrote, iclass 16, count 2 2006.257.04:50:33.34#ibcon#about to read 3, iclass 16, count 2 2006.257.04:50:33.36#ibcon#read 3, iclass 16, count 2 2006.257.04:50:33.36#ibcon#about to read 4, iclass 16, count 2 2006.257.04:50:33.36#ibcon#read 4, iclass 16, count 2 2006.257.04:50:33.36#ibcon#about to read 5, iclass 16, count 2 2006.257.04:50:33.36#ibcon#read 5, iclass 16, count 2 2006.257.04:50:33.36#ibcon#about to read 6, iclass 16, count 2 2006.257.04:50:33.36#ibcon#read 6, iclass 16, count 2 2006.257.04:50:33.36#ibcon#end of sib2, iclass 16, count 2 2006.257.04:50:33.36#ibcon#*mode == 0, iclass 16, count 2 2006.257.04:50:33.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.04:50:33.36#ibcon#[27=AT02-05\r\n] 2006.257.04:50:33.36#ibcon#*before write, iclass 16, count 2 2006.257.04:50:33.36#ibcon#enter sib2, iclass 16, count 2 2006.257.04:50:33.36#ibcon#flushed, iclass 16, count 2 2006.257.04:50:33.36#ibcon#about to write, iclass 16, count 2 2006.257.04:50:33.36#ibcon#wrote, iclass 16, count 2 2006.257.04:50:33.36#ibcon#about to read 3, iclass 16, count 2 2006.257.04:50:33.39#ibcon#read 3, iclass 16, count 2 2006.257.04:50:33.39#ibcon#about to read 4, iclass 16, count 2 2006.257.04:50:33.39#ibcon#read 4, iclass 16, count 2 2006.257.04:50:33.39#ibcon#about to read 5, iclass 16, count 2 2006.257.04:50:33.39#ibcon#read 5, iclass 16, count 2 2006.257.04:50:33.39#ibcon#about to read 6, iclass 16, count 2 2006.257.04:50:33.39#ibcon#read 6, iclass 16, count 2 2006.257.04:50:33.39#ibcon#end of sib2, iclass 16, count 2 2006.257.04:50:33.39#ibcon#*after write, iclass 16, count 2 2006.257.04:50:33.39#ibcon#*before return 0, iclass 16, count 2 2006.257.04:50:33.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:33.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.04:50:33.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.04:50:33.39#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:33.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:33.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:33.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:33.51#ibcon#enter wrdev, iclass 16, count 0 2006.257.04:50:33.51#ibcon#first serial, iclass 16, count 0 2006.257.04:50:33.51#ibcon#enter sib2, iclass 16, count 0 2006.257.04:50:33.51#ibcon#flushed, iclass 16, count 0 2006.257.04:50:33.51#ibcon#about to write, iclass 16, count 0 2006.257.04:50:33.51#ibcon#wrote, iclass 16, count 0 2006.257.04:50:33.51#ibcon#about to read 3, iclass 16, count 0 2006.257.04:50:33.53#ibcon#read 3, iclass 16, count 0 2006.257.04:50:33.53#ibcon#about to read 4, iclass 16, count 0 2006.257.04:50:33.53#ibcon#read 4, iclass 16, count 0 2006.257.04:50:33.53#ibcon#about to read 5, iclass 16, count 0 2006.257.04:50:33.53#ibcon#read 5, iclass 16, count 0 2006.257.04:50:33.53#ibcon#about to read 6, iclass 16, count 0 2006.257.04:50:33.53#ibcon#read 6, iclass 16, count 0 2006.257.04:50:33.53#ibcon#end of sib2, iclass 16, count 0 2006.257.04:50:33.53#ibcon#*mode == 0, iclass 16, count 0 2006.257.04:50:33.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.04:50:33.53#ibcon#[27=USB\r\n] 2006.257.04:50:33.53#ibcon#*before write, iclass 16, count 0 2006.257.04:50:33.53#ibcon#enter sib2, iclass 16, count 0 2006.257.04:50:33.53#ibcon#flushed, iclass 16, count 0 2006.257.04:50:33.53#ibcon#about to write, iclass 16, count 0 2006.257.04:50:33.53#ibcon#wrote, iclass 16, count 0 2006.257.04:50:33.53#ibcon#about to read 3, iclass 16, count 0 2006.257.04:50:33.56#ibcon#read 3, iclass 16, count 0 2006.257.04:50:33.56#ibcon#about to read 4, iclass 16, count 0 2006.257.04:50:33.56#ibcon#read 4, iclass 16, count 0 2006.257.04:50:33.56#ibcon#about to read 5, iclass 16, count 0 2006.257.04:50:33.56#ibcon#read 5, iclass 16, count 0 2006.257.04:50:33.56#ibcon#about to read 6, iclass 16, count 0 2006.257.04:50:33.56#ibcon#read 6, iclass 16, count 0 2006.257.04:50:33.56#ibcon#end of sib2, iclass 16, count 0 2006.257.04:50:33.56#ibcon#*after write, iclass 16, count 0 2006.257.04:50:33.56#ibcon#*before return 0, iclass 16, count 0 2006.257.04:50:33.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:33.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.04:50:33.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.04:50:33.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.04:50:33.57$vck44/vblo=3,649.99 2006.257.04:50:33.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.04:50:33.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.04:50:33.57#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:33.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:33.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:33.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:33.57#ibcon#enter wrdev, iclass 18, count 0 2006.257.04:50:33.57#ibcon#first serial, iclass 18, count 0 2006.257.04:50:33.57#ibcon#enter sib2, iclass 18, count 0 2006.257.04:50:33.57#ibcon#flushed, iclass 18, count 0 2006.257.04:50:33.57#ibcon#about to write, iclass 18, count 0 2006.257.04:50:33.57#ibcon#wrote, iclass 18, count 0 2006.257.04:50:33.57#ibcon#about to read 3, iclass 18, count 0 2006.257.04:50:33.58#ibcon#read 3, iclass 18, count 0 2006.257.04:50:33.58#ibcon#about to read 4, iclass 18, count 0 2006.257.04:50:33.58#ibcon#read 4, iclass 18, count 0 2006.257.04:50:33.58#ibcon#about to read 5, iclass 18, count 0 2006.257.04:50:33.58#ibcon#read 5, iclass 18, count 0 2006.257.04:50:33.58#ibcon#about to read 6, iclass 18, count 0 2006.257.04:50:33.58#ibcon#read 6, iclass 18, count 0 2006.257.04:50:33.58#ibcon#end of sib2, iclass 18, count 0 2006.257.04:50:33.58#ibcon#*mode == 0, iclass 18, count 0 2006.257.04:50:33.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.04:50:33.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.04:50:33.58#ibcon#*before write, iclass 18, count 0 2006.257.04:50:33.58#ibcon#enter sib2, iclass 18, count 0 2006.257.04:50:33.58#ibcon#flushed, iclass 18, count 0 2006.257.04:50:33.58#ibcon#about to write, iclass 18, count 0 2006.257.04:50:33.58#ibcon#wrote, iclass 18, count 0 2006.257.04:50:33.58#ibcon#about to read 3, iclass 18, count 0 2006.257.04:50:33.62#ibcon#read 3, iclass 18, count 0 2006.257.04:50:33.62#ibcon#about to read 4, iclass 18, count 0 2006.257.04:50:33.62#ibcon#read 4, iclass 18, count 0 2006.257.04:50:33.62#ibcon#about to read 5, iclass 18, count 0 2006.257.04:50:33.62#ibcon#read 5, iclass 18, count 0 2006.257.04:50:33.62#ibcon#about to read 6, iclass 18, count 0 2006.257.04:50:33.62#ibcon#read 6, iclass 18, count 0 2006.257.04:50:33.62#ibcon#end of sib2, iclass 18, count 0 2006.257.04:50:33.62#ibcon#*after write, iclass 18, count 0 2006.257.04:50:33.62#ibcon#*before return 0, iclass 18, count 0 2006.257.04:50:33.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:33.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.04:50:33.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.04:50:33.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.04:50:33.63$vck44/vb=3,4 2006.257.04:50:33.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.04:50:33.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.04:50:33.63#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:33.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:33.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:33.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:33.67#ibcon#enter wrdev, iclass 20, count 2 2006.257.04:50:33.67#ibcon#first serial, iclass 20, count 2 2006.257.04:50:33.67#ibcon#enter sib2, iclass 20, count 2 2006.257.04:50:33.67#ibcon#flushed, iclass 20, count 2 2006.257.04:50:33.67#ibcon#about to write, iclass 20, count 2 2006.257.04:50:33.67#ibcon#wrote, iclass 20, count 2 2006.257.04:50:33.67#ibcon#about to read 3, iclass 20, count 2 2006.257.04:50:33.69#ibcon#read 3, iclass 20, count 2 2006.257.04:50:33.69#ibcon#about to read 4, iclass 20, count 2 2006.257.04:50:33.69#ibcon#read 4, iclass 20, count 2 2006.257.04:50:33.69#ibcon#about to read 5, iclass 20, count 2 2006.257.04:50:33.69#ibcon#read 5, iclass 20, count 2 2006.257.04:50:33.69#ibcon#about to read 6, iclass 20, count 2 2006.257.04:50:33.69#ibcon#read 6, iclass 20, count 2 2006.257.04:50:33.69#ibcon#end of sib2, iclass 20, count 2 2006.257.04:50:33.69#ibcon#*mode == 0, iclass 20, count 2 2006.257.04:50:33.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.04:50:33.69#ibcon#[27=AT03-04\r\n] 2006.257.04:50:33.69#ibcon#*before write, iclass 20, count 2 2006.257.04:50:33.69#ibcon#enter sib2, iclass 20, count 2 2006.257.04:50:33.69#ibcon#flushed, iclass 20, count 2 2006.257.04:50:33.69#ibcon#about to write, iclass 20, count 2 2006.257.04:50:33.69#ibcon#wrote, iclass 20, count 2 2006.257.04:50:33.69#ibcon#about to read 3, iclass 20, count 2 2006.257.04:50:33.72#ibcon#read 3, iclass 20, count 2 2006.257.04:50:33.72#ibcon#about to read 4, iclass 20, count 2 2006.257.04:50:33.72#ibcon#read 4, iclass 20, count 2 2006.257.04:50:33.72#ibcon#about to read 5, iclass 20, count 2 2006.257.04:50:33.72#ibcon#read 5, iclass 20, count 2 2006.257.04:50:33.72#ibcon#about to read 6, iclass 20, count 2 2006.257.04:50:33.72#ibcon#read 6, iclass 20, count 2 2006.257.04:50:33.72#ibcon#end of sib2, iclass 20, count 2 2006.257.04:50:33.72#ibcon#*after write, iclass 20, count 2 2006.257.04:50:33.72#ibcon#*before return 0, iclass 20, count 2 2006.257.04:50:33.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:33.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.04:50:33.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.04:50:33.72#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:33.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:33.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:33.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:33.84#ibcon#enter wrdev, iclass 20, count 0 2006.257.04:50:33.84#ibcon#first serial, iclass 20, count 0 2006.257.04:50:33.84#ibcon#enter sib2, iclass 20, count 0 2006.257.04:50:33.84#ibcon#flushed, iclass 20, count 0 2006.257.04:50:33.84#ibcon#about to write, iclass 20, count 0 2006.257.04:50:33.84#ibcon#wrote, iclass 20, count 0 2006.257.04:50:33.84#ibcon#about to read 3, iclass 20, count 0 2006.257.04:50:33.86#ibcon#read 3, iclass 20, count 0 2006.257.04:50:33.86#ibcon#about to read 4, iclass 20, count 0 2006.257.04:50:33.86#ibcon#read 4, iclass 20, count 0 2006.257.04:50:33.86#ibcon#about to read 5, iclass 20, count 0 2006.257.04:50:33.86#ibcon#read 5, iclass 20, count 0 2006.257.04:50:33.86#ibcon#about to read 6, iclass 20, count 0 2006.257.04:50:33.86#ibcon#read 6, iclass 20, count 0 2006.257.04:50:33.86#ibcon#end of sib2, iclass 20, count 0 2006.257.04:50:33.86#ibcon#*mode == 0, iclass 20, count 0 2006.257.04:50:33.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.04:50:33.86#ibcon#[27=USB\r\n] 2006.257.04:50:33.86#ibcon#*before write, iclass 20, count 0 2006.257.04:50:33.86#ibcon#enter sib2, iclass 20, count 0 2006.257.04:50:33.86#ibcon#flushed, iclass 20, count 0 2006.257.04:50:33.86#ibcon#about to write, iclass 20, count 0 2006.257.04:50:33.86#ibcon#wrote, iclass 20, count 0 2006.257.04:50:33.86#ibcon#about to read 3, iclass 20, count 0 2006.257.04:50:33.89#ibcon#read 3, iclass 20, count 0 2006.257.04:50:33.89#ibcon#about to read 4, iclass 20, count 0 2006.257.04:50:33.89#ibcon#read 4, iclass 20, count 0 2006.257.04:50:33.89#ibcon#about to read 5, iclass 20, count 0 2006.257.04:50:33.89#ibcon#read 5, iclass 20, count 0 2006.257.04:50:33.89#ibcon#about to read 6, iclass 20, count 0 2006.257.04:50:33.89#ibcon#read 6, iclass 20, count 0 2006.257.04:50:33.89#ibcon#end of sib2, iclass 20, count 0 2006.257.04:50:33.89#ibcon#*after write, iclass 20, count 0 2006.257.04:50:33.89#ibcon#*before return 0, iclass 20, count 0 2006.257.04:50:33.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:33.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.04:50:33.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.04:50:33.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.04:50:33.90$vck44/vblo=4,679.99 2006.257.04:50:33.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.04:50:33.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.04:50:33.90#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:33.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:33.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:33.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:33.90#ibcon#enter wrdev, iclass 22, count 0 2006.257.04:50:33.90#ibcon#first serial, iclass 22, count 0 2006.257.04:50:33.90#ibcon#enter sib2, iclass 22, count 0 2006.257.04:50:33.90#ibcon#flushed, iclass 22, count 0 2006.257.04:50:33.90#ibcon#about to write, iclass 22, count 0 2006.257.04:50:33.90#ibcon#wrote, iclass 22, count 0 2006.257.04:50:33.90#ibcon#about to read 3, iclass 22, count 0 2006.257.04:50:33.91#ibcon#read 3, iclass 22, count 0 2006.257.04:50:33.91#ibcon#about to read 4, iclass 22, count 0 2006.257.04:50:33.91#ibcon#read 4, iclass 22, count 0 2006.257.04:50:33.91#ibcon#about to read 5, iclass 22, count 0 2006.257.04:50:33.91#ibcon#read 5, iclass 22, count 0 2006.257.04:50:33.91#ibcon#about to read 6, iclass 22, count 0 2006.257.04:50:33.91#ibcon#read 6, iclass 22, count 0 2006.257.04:50:33.91#ibcon#end of sib2, iclass 22, count 0 2006.257.04:50:33.91#ibcon#*mode == 0, iclass 22, count 0 2006.257.04:50:33.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.04:50:33.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.04:50:33.91#ibcon#*before write, iclass 22, count 0 2006.257.04:50:33.91#ibcon#enter sib2, iclass 22, count 0 2006.257.04:50:33.91#ibcon#flushed, iclass 22, count 0 2006.257.04:50:33.91#ibcon#about to write, iclass 22, count 0 2006.257.04:50:33.92#ibcon#wrote, iclass 22, count 0 2006.257.04:50:33.92#ibcon#about to read 3, iclass 22, count 0 2006.257.04:50:33.95#ibcon#read 3, iclass 22, count 0 2006.257.04:50:33.95#ibcon#about to read 4, iclass 22, count 0 2006.257.04:50:33.95#ibcon#read 4, iclass 22, count 0 2006.257.04:50:33.95#ibcon#about to read 5, iclass 22, count 0 2006.257.04:50:33.95#ibcon#read 5, iclass 22, count 0 2006.257.04:50:33.95#ibcon#about to read 6, iclass 22, count 0 2006.257.04:50:33.95#ibcon#read 6, iclass 22, count 0 2006.257.04:50:33.95#ibcon#end of sib2, iclass 22, count 0 2006.257.04:50:33.95#ibcon#*after write, iclass 22, count 0 2006.257.04:50:33.95#ibcon#*before return 0, iclass 22, count 0 2006.257.04:50:33.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:33.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.04:50:33.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.04:50:33.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.04:50:33.96$vck44/vb=4,5 2006.257.04:50:33.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.04:50:33.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.04:50:33.96#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:33.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:34.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:34.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:34.01#ibcon#enter wrdev, iclass 24, count 2 2006.257.04:50:34.01#ibcon#first serial, iclass 24, count 2 2006.257.04:50:34.01#ibcon#enter sib2, iclass 24, count 2 2006.257.04:50:34.01#ibcon#flushed, iclass 24, count 2 2006.257.04:50:34.01#ibcon#about to write, iclass 24, count 2 2006.257.04:50:34.01#ibcon#wrote, iclass 24, count 2 2006.257.04:50:34.01#ibcon#about to read 3, iclass 24, count 2 2006.257.04:50:34.02#ibcon#read 3, iclass 24, count 2 2006.257.04:50:34.02#ibcon#about to read 4, iclass 24, count 2 2006.257.04:50:34.02#ibcon#read 4, iclass 24, count 2 2006.257.04:50:34.02#ibcon#about to read 5, iclass 24, count 2 2006.257.04:50:34.02#ibcon#read 5, iclass 24, count 2 2006.257.04:50:34.02#ibcon#about to read 6, iclass 24, count 2 2006.257.04:50:34.02#ibcon#read 6, iclass 24, count 2 2006.257.04:50:34.02#ibcon#end of sib2, iclass 24, count 2 2006.257.04:50:34.02#ibcon#*mode == 0, iclass 24, count 2 2006.257.04:50:34.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.04:50:34.02#ibcon#[27=AT04-05\r\n] 2006.257.04:50:34.02#ibcon#*before write, iclass 24, count 2 2006.257.04:50:34.02#ibcon#enter sib2, iclass 24, count 2 2006.257.04:50:34.02#ibcon#flushed, iclass 24, count 2 2006.257.04:50:34.02#ibcon#about to write, iclass 24, count 2 2006.257.04:50:34.02#ibcon#wrote, iclass 24, count 2 2006.257.04:50:34.02#ibcon#about to read 3, iclass 24, count 2 2006.257.04:50:34.05#ibcon#read 3, iclass 24, count 2 2006.257.04:50:34.05#ibcon#about to read 4, iclass 24, count 2 2006.257.04:50:34.05#ibcon#read 4, iclass 24, count 2 2006.257.04:50:34.05#ibcon#about to read 5, iclass 24, count 2 2006.257.04:50:34.05#ibcon#read 5, iclass 24, count 2 2006.257.04:50:34.05#ibcon#about to read 6, iclass 24, count 2 2006.257.04:50:34.05#ibcon#read 6, iclass 24, count 2 2006.257.04:50:34.05#ibcon#end of sib2, iclass 24, count 2 2006.257.04:50:34.05#ibcon#*after write, iclass 24, count 2 2006.257.04:50:34.05#ibcon#*before return 0, iclass 24, count 2 2006.257.04:50:34.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:34.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.04:50:34.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.04:50:34.05#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:34.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:34.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:34.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:34.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.04:50:34.17#ibcon#first serial, iclass 24, count 0 2006.257.04:50:34.17#ibcon#enter sib2, iclass 24, count 0 2006.257.04:50:34.17#ibcon#flushed, iclass 24, count 0 2006.257.04:50:34.17#ibcon#about to write, iclass 24, count 0 2006.257.04:50:34.17#ibcon#wrote, iclass 24, count 0 2006.257.04:50:34.17#ibcon#about to read 3, iclass 24, count 0 2006.257.04:50:34.19#ibcon#read 3, iclass 24, count 0 2006.257.04:50:34.19#ibcon#about to read 4, iclass 24, count 0 2006.257.04:50:34.19#ibcon#read 4, iclass 24, count 0 2006.257.04:50:34.19#ibcon#about to read 5, iclass 24, count 0 2006.257.04:50:34.19#ibcon#read 5, iclass 24, count 0 2006.257.04:50:34.19#ibcon#about to read 6, iclass 24, count 0 2006.257.04:50:34.19#ibcon#read 6, iclass 24, count 0 2006.257.04:50:34.19#ibcon#end of sib2, iclass 24, count 0 2006.257.04:50:34.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.04:50:34.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.04:50:34.19#ibcon#[27=USB\r\n] 2006.257.04:50:34.19#ibcon#*before write, iclass 24, count 0 2006.257.04:50:34.19#ibcon#enter sib2, iclass 24, count 0 2006.257.04:50:34.19#ibcon#flushed, iclass 24, count 0 2006.257.04:50:34.19#ibcon#about to write, iclass 24, count 0 2006.257.04:50:34.19#ibcon#wrote, iclass 24, count 0 2006.257.04:50:34.19#ibcon#about to read 3, iclass 24, count 0 2006.257.04:50:34.22#ibcon#read 3, iclass 24, count 0 2006.257.04:50:34.22#ibcon#about to read 4, iclass 24, count 0 2006.257.04:50:34.22#ibcon#read 4, iclass 24, count 0 2006.257.04:50:34.22#ibcon#about to read 5, iclass 24, count 0 2006.257.04:50:34.22#ibcon#read 5, iclass 24, count 0 2006.257.04:50:34.22#ibcon#about to read 6, iclass 24, count 0 2006.257.04:50:34.22#ibcon#read 6, iclass 24, count 0 2006.257.04:50:34.22#ibcon#end of sib2, iclass 24, count 0 2006.257.04:50:34.22#ibcon#*after write, iclass 24, count 0 2006.257.04:50:34.22#ibcon#*before return 0, iclass 24, count 0 2006.257.04:50:34.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:34.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.04:50:34.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.04:50:34.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.04:50:34.23$vck44/vblo=5,709.99 2006.257.04:50:34.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.04:50:34.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.04:50:34.23#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:34.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:34.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:34.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:34.23#ibcon#enter wrdev, iclass 26, count 0 2006.257.04:50:34.23#ibcon#first serial, iclass 26, count 0 2006.257.04:50:34.23#ibcon#enter sib2, iclass 26, count 0 2006.257.04:50:34.23#ibcon#flushed, iclass 26, count 0 2006.257.04:50:34.23#ibcon#about to write, iclass 26, count 0 2006.257.04:50:34.23#ibcon#wrote, iclass 26, count 0 2006.257.04:50:34.23#ibcon#about to read 3, iclass 26, count 0 2006.257.04:50:34.24#ibcon#read 3, iclass 26, count 0 2006.257.04:50:34.24#ibcon#about to read 4, iclass 26, count 0 2006.257.04:50:34.24#ibcon#read 4, iclass 26, count 0 2006.257.04:50:34.24#ibcon#about to read 5, iclass 26, count 0 2006.257.04:50:34.24#ibcon#read 5, iclass 26, count 0 2006.257.04:50:34.24#ibcon#about to read 6, iclass 26, count 0 2006.257.04:50:34.24#ibcon#read 6, iclass 26, count 0 2006.257.04:50:34.24#ibcon#end of sib2, iclass 26, count 0 2006.257.04:50:34.24#ibcon#*mode == 0, iclass 26, count 0 2006.257.04:50:34.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.04:50:34.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.04:50:34.24#ibcon#*before write, iclass 26, count 0 2006.257.04:50:34.24#ibcon#enter sib2, iclass 26, count 0 2006.257.04:50:34.24#ibcon#flushed, iclass 26, count 0 2006.257.04:50:34.24#ibcon#about to write, iclass 26, count 0 2006.257.04:50:34.24#ibcon#wrote, iclass 26, count 0 2006.257.04:50:34.24#ibcon#about to read 3, iclass 26, count 0 2006.257.04:50:34.28#ibcon#read 3, iclass 26, count 0 2006.257.04:50:34.28#ibcon#about to read 4, iclass 26, count 0 2006.257.04:50:34.28#ibcon#read 4, iclass 26, count 0 2006.257.04:50:34.28#ibcon#about to read 5, iclass 26, count 0 2006.257.04:50:34.28#ibcon#read 5, iclass 26, count 0 2006.257.04:50:34.28#ibcon#about to read 6, iclass 26, count 0 2006.257.04:50:34.28#ibcon#read 6, iclass 26, count 0 2006.257.04:50:34.28#ibcon#end of sib2, iclass 26, count 0 2006.257.04:50:34.28#ibcon#*after write, iclass 26, count 0 2006.257.04:50:34.28#ibcon#*before return 0, iclass 26, count 0 2006.257.04:50:34.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:34.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.04:50:34.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.04:50:34.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.04:50:34.29$vck44/vb=5,4 2006.257.04:50:34.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.04:50:34.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.04:50:34.29#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:34.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:34.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:34.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:34.33#ibcon#enter wrdev, iclass 28, count 2 2006.257.04:50:34.33#ibcon#first serial, iclass 28, count 2 2006.257.04:50:34.33#ibcon#enter sib2, iclass 28, count 2 2006.257.04:50:34.33#ibcon#flushed, iclass 28, count 2 2006.257.04:50:34.33#ibcon#about to write, iclass 28, count 2 2006.257.04:50:34.33#ibcon#wrote, iclass 28, count 2 2006.257.04:50:34.33#ibcon#about to read 3, iclass 28, count 2 2006.257.04:50:34.35#ibcon#read 3, iclass 28, count 2 2006.257.04:50:34.35#ibcon#about to read 4, iclass 28, count 2 2006.257.04:50:34.35#ibcon#read 4, iclass 28, count 2 2006.257.04:50:34.35#ibcon#about to read 5, iclass 28, count 2 2006.257.04:50:34.35#ibcon#read 5, iclass 28, count 2 2006.257.04:50:34.35#ibcon#about to read 6, iclass 28, count 2 2006.257.04:50:34.35#ibcon#read 6, iclass 28, count 2 2006.257.04:50:34.35#ibcon#end of sib2, iclass 28, count 2 2006.257.04:50:34.35#ibcon#*mode == 0, iclass 28, count 2 2006.257.04:50:34.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.04:50:34.35#ibcon#[27=AT05-04\r\n] 2006.257.04:50:34.35#ibcon#*before write, iclass 28, count 2 2006.257.04:50:34.35#ibcon#enter sib2, iclass 28, count 2 2006.257.04:50:34.35#ibcon#flushed, iclass 28, count 2 2006.257.04:50:34.35#ibcon#about to write, iclass 28, count 2 2006.257.04:50:34.35#ibcon#wrote, iclass 28, count 2 2006.257.04:50:34.35#ibcon#about to read 3, iclass 28, count 2 2006.257.04:50:34.38#ibcon#read 3, iclass 28, count 2 2006.257.04:50:34.38#ibcon#about to read 4, iclass 28, count 2 2006.257.04:50:34.38#ibcon#read 4, iclass 28, count 2 2006.257.04:50:34.38#ibcon#about to read 5, iclass 28, count 2 2006.257.04:50:34.38#ibcon#read 5, iclass 28, count 2 2006.257.04:50:34.38#ibcon#about to read 6, iclass 28, count 2 2006.257.04:50:34.38#ibcon#read 6, iclass 28, count 2 2006.257.04:50:34.38#ibcon#end of sib2, iclass 28, count 2 2006.257.04:50:34.38#ibcon#*after write, iclass 28, count 2 2006.257.04:50:34.38#ibcon#*before return 0, iclass 28, count 2 2006.257.04:50:34.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:34.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.04:50:34.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.04:50:34.38#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:34.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:34.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:34.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:34.50#ibcon#enter wrdev, iclass 28, count 0 2006.257.04:50:34.50#ibcon#first serial, iclass 28, count 0 2006.257.04:50:34.50#ibcon#enter sib2, iclass 28, count 0 2006.257.04:50:34.50#ibcon#flushed, iclass 28, count 0 2006.257.04:50:34.50#ibcon#about to write, iclass 28, count 0 2006.257.04:50:34.50#ibcon#wrote, iclass 28, count 0 2006.257.04:50:34.50#ibcon#about to read 3, iclass 28, count 0 2006.257.04:50:34.52#ibcon#read 3, iclass 28, count 0 2006.257.04:50:34.52#ibcon#about to read 4, iclass 28, count 0 2006.257.04:50:34.52#ibcon#read 4, iclass 28, count 0 2006.257.04:50:34.52#ibcon#about to read 5, iclass 28, count 0 2006.257.04:50:34.52#ibcon#read 5, iclass 28, count 0 2006.257.04:50:34.52#ibcon#about to read 6, iclass 28, count 0 2006.257.04:50:34.52#ibcon#read 6, iclass 28, count 0 2006.257.04:50:34.52#ibcon#end of sib2, iclass 28, count 0 2006.257.04:50:34.52#ibcon#*mode == 0, iclass 28, count 0 2006.257.04:50:34.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.04:50:34.52#ibcon#[27=USB\r\n] 2006.257.04:50:34.52#ibcon#*before write, iclass 28, count 0 2006.257.04:50:34.52#ibcon#enter sib2, iclass 28, count 0 2006.257.04:50:34.52#ibcon#flushed, iclass 28, count 0 2006.257.04:50:34.52#ibcon#about to write, iclass 28, count 0 2006.257.04:50:34.52#ibcon#wrote, iclass 28, count 0 2006.257.04:50:34.52#ibcon#about to read 3, iclass 28, count 0 2006.257.04:50:34.55#ibcon#read 3, iclass 28, count 0 2006.257.04:50:34.55#ibcon#about to read 4, iclass 28, count 0 2006.257.04:50:34.55#ibcon#read 4, iclass 28, count 0 2006.257.04:50:34.55#ibcon#about to read 5, iclass 28, count 0 2006.257.04:50:34.55#ibcon#read 5, iclass 28, count 0 2006.257.04:50:34.55#ibcon#about to read 6, iclass 28, count 0 2006.257.04:50:34.55#ibcon#read 6, iclass 28, count 0 2006.257.04:50:34.55#ibcon#end of sib2, iclass 28, count 0 2006.257.04:50:34.55#ibcon#*after write, iclass 28, count 0 2006.257.04:50:34.55#ibcon#*before return 0, iclass 28, count 0 2006.257.04:50:34.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:34.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.04:50:34.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.04:50:34.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.04:50:34.56$vck44/vblo=6,719.99 2006.257.04:50:34.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.04:50:34.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.04:50:34.56#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:34.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:34.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:34.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:34.56#ibcon#enter wrdev, iclass 30, count 0 2006.257.04:50:34.56#ibcon#first serial, iclass 30, count 0 2006.257.04:50:34.56#ibcon#enter sib2, iclass 30, count 0 2006.257.04:50:34.56#ibcon#flushed, iclass 30, count 0 2006.257.04:50:34.56#ibcon#about to write, iclass 30, count 0 2006.257.04:50:34.56#ibcon#wrote, iclass 30, count 0 2006.257.04:50:34.56#ibcon#about to read 3, iclass 30, count 0 2006.257.04:50:34.57#ibcon#read 3, iclass 30, count 0 2006.257.04:50:34.57#ibcon#about to read 4, iclass 30, count 0 2006.257.04:50:34.57#ibcon#read 4, iclass 30, count 0 2006.257.04:50:34.57#ibcon#about to read 5, iclass 30, count 0 2006.257.04:50:34.57#ibcon#read 5, iclass 30, count 0 2006.257.04:50:34.57#ibcon#about to read 6, iclass 30, count 0 2006.257.04:50:34.57#ibcon#read 6, iclass 30, count 0 2006.257.04:50:34.57#ibcon#end of sib2, iclass 30, count 0 2006.257.04:50:34.57#ibcon#*mode == 0, iclass 30, count 0 2006.257.04:50:34.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.04:50:34.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.04:50:34.57#ibcon#*before write, iclass 30, count 0 2006.257.04:50:34.57#ibcon#enter sib2, iclass 30, count 0 2006.257.04:50:34.57#ibcon#flushed, iclass 30, count 0 2006.257.04:50:34.57#ibcon#about to write, iclass 30, count 0 2006.257.04:50:34.57#ibcon#wrote, iclass 30, count 0 2006.257.04:50:34.57#ibcon#about to read 3, iclass 30, count 0 2006.257.04:50:34.61#ibcon#read 3, iclass 30, count 0 2006.257.04:50:34.61#ibcon#about to read 4, iclass 30, count 0 2006.257.04:50:34.61#ibcon#read 4, iclass 30, count 0 2006.257.04:50:34.61#ibcon#about to read 5, iclass 30, count 0 2006.257.04:50:34.61#ibcon#read 5, iclass 30, count 0 2006.257.04:50:34.61#ibcon#about to read 6, iclass 30, count 0 2006.257.04:50:34.61#ibcon#read 6, iclass 30, count 0 2006.257.04:50:34.61#ibcon#end of sib2, iclass 30, count 0 2006.257.04:50:34.61#ibcon#*after write, iclass 30, count 0 2006.257.04:50:34.61#ibcon#*before return 0, iclass 30, count 0 2006.257.04:50:34.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:34.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.04:50:34.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.04:50:34.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.04:50:34.62$vck44/vb=6,4 2006.257.04:50:34.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.04:50:34.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.04:50:34.62#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:34.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:34.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:34.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:34.66#ibcon#enter wrdev, iclass 32, count 2 2006.257.04:50:34.66#ibcon#first serial, iclass 32, count 2 2006.257.04:50:34.66#ibcon#enter sib2, iclass 32, count 2 2006.257.04:50:34.66#ibcon#flushed, iclass 32, count 2 2006.257.04:50:34.66#ibcon#about to write, iclass 32, count 2 2006.257.04:50:34.66#ibcon#wrote, iclass 32, count 2 2006.257.04:50:34.66#ibcon#about to read 3, iclass 32, count 2 2006.257.04:50:34.68#ibcon#read 3, iclass 32, count 2 2006.257.04:50:34.68#ibcon#about to read 4, iclass 32, count 2 2006.257.04:50:34.68#ibcon#read 4, iclass 32, count 2 2006.257.04:50:34.68#ibcon#about to read 5, iclass 32, count 2 2006.257.04:50:34.68#ibcon#read 5, iclass 32, count 2 2006.257.04:50:34.68#ibcon#about to read 6, iclass 32, count 2 2006.257.04:50:34.68#ibcon#read 6, iclass 32, count 2 2006.257.04:50:34.68#ibcon#end of sib2, iclass 32, count 2 2006.257.04:50:34.68#ibcon#*mode == 0, iclass 32, count 2 2006.257.04:50:34.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.04:50:34.68#ibcon#[27=AT06-04\r\n] 2006.257.04:50:34.68#ibcon#*before write, iclass 32, count 2 2006.257.04:50:34.68#ibcon#enter sib2, iclass 32, count 2 2006.257.04:50:34.68#ibcon#flushed, iclass 32, count 2 2006.257.04:50:34.68#ibcon#about to write, iclass 32, count 2 2006.257.04:50:34.68#ibcon#wrote, iclass 32, count 2 2006.257.04:50:34.68#ibcon#about to read 3, iclass 32, count 2 2006.257.04:50:34.71#ibcon#read 3, iclass 32, count 2 2006.257.04:50:34.71#ibcon#about to read 4, iclass 32, count 2 2006.257.04:50:34.71#ibcon#read 4, iclass 32, count 2 2006.257.04:50:34.71#ibcon#about to read 5, iclass 32, count 2 2006.257.04:50:34.71#ibcon#read 5, iclass 32, count 2 2006.257.04:50:34.71#ibcon#about to read 6, iclass 32, count 2 2006.257.04:50:34.71#ibcon#read 6, iclass 32, count 2 2006.257.04:50:34.71#ibcon#end of sib2, iclass 32, count 2 2006.257.04:50:34.71#ibcon#*after write, iclass 32, count 2 2006.257.04:50:34.71#ibcon#*before return 0, iclass 32, count 2 2006.257.04:50:34.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:34.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.04:50:34.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.04:50:34.71#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:34.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:34.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:34.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:34.83#ibcon#enter wrdev, iclass 32, count 0 2006.257.04:50:34.83#ibcon#first serial, iclass 32, count 0 2006.257.04:50:34.83#ibcon#enter sib2, iclass 32, count 0 2006.257.04:50:34.83#ibcon#flushed, iclass 32, count 0 2006.257.04:50:34.83#ibcon#about to write, iclass 32, count 0 2006.257.04:50:34.83#ibcon#wrote, iclass 32, count 0 2006.257.04:50:34.83#ibcon#about to read 3, iclass 32, count 0 2006.257.04:50:34.85#ibcon#read 3, iclass 32, count 0 2006.257.04:50:34.85#ibcon#about to read 4, iclass 32, count 0 2006.257.04:50:34.85#ibcon#read 4, iclass 32, count 0 2006.257.04:50:34.85#ibcon#about to read 5, iclass 32, count 0 2006.257.04:50:34.85#ibcon#read 5, iclass 32, count 0 2006.257.04:50:34.85#ibcon#about to read 6, iclass 32, count 0 2006.257.04:50:34.85#ibcon#read 6, iclass 32, count 0 2006.257.04:50:34.85#ibcon#end of sib2, iclass 32, count 0 2006.257.04:50:34.85#ibcon#*mode == 0, iclass 32, count 0 2006.257.04:50:34.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.04:50:34.85#ibcon#[27=USB\r\n] 2006.257.04:50:34.85#ibcon#*before write, iclass 32, count 0 2006.257.04:50:34.85#ibcon#enter sib2, iclass 32, count 0 2006.257.04:50:34.85#ibcon#flushed, iclass 32, count 0 2006.257.04:50:34.85#ibcon#about to write, iclass 32, count 0 2006.257.04:50:34.85#ibcon#wrote, iclass 32, count 0 2006.257.04:50:34.85#ibcon#about to read 3, iclass 32, count 0 2006.257.04:50:34.88#ibcon#read 3, iclass 32, count 0 2006.257.04:50:34.88#ibcon#about to read 4, iclass 32, count 0 2006.257.04:50:34.88#ibcon#read 4, iclass 32, count 0 2006.257.04:50:34.88#ibcon#about to read 5, iclass 32, count 0 2006.257.04:50:34.88#ibcon#read 5, iclass 32, count 0 2006.257.04:50:34.88#ibcon#about to read 6, iclass 32, count 0 2006.257.04:50:34.88#ibcon#read 6, iclass 32, count 0 2006.257.04:50:34.88#ibcon#end of sib2, iclass 32, count 0 2006.257.04:50:34.88#ibcon#*after write, iclass 32, count 0 2006.257.04:50:34.88#ibcon#*before return 0, iclass 32, count 0 2006.257.04:50:34.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:34.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.04:50:34.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.04:50:34.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.04:50:34.89$vck44/vblo=7,734.99 2006.257.04:50:34.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.04:50:34.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.04:50:34.89#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:34.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:34.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:34.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:34.89#ibcon#enter wrdev, iclass 34, count 0 2006.257.04:50:34.89#ibcon#first serial, iclass 34, count 0 2006.257.04:50:34.89#ibcon#enter sib2, iclass 34, count 0 2006.257.04:50:34.89#ibcon#flushed, iclass 34, count 0 2006.257.04:50:34.89#ibcon#about to write, iclass 34, count 0 2006.257.04:50:34.89#ibcon#wrote, iclass 34, count 0 2006.257.04:50:34.89#ibcon#about to read 3, iclass 34, count 0 2006.257.04:50:34.90#ibcon#read 3, iclass 34, count 0 2006.257.04:50:34.90#ibcon#about to read 4, iclass 34, count 0 2006.257.04:50:34.90#ibcon#read 4, iclass 34, count 0 2006.257.04:50:34.90#ibcon#about to read 5, iclass 34, count 0 2006.257.04:50:34.90#ibcon#read 5, iclass 34, count 0 2006.257.04:50:34.90#ibcon#about to read 6, iclass 34, count 0 2006.257.04:50:34.90#ibcon#read 6, iclass 34, count 0 2006.257.04:50:34.90#ibcon#end of sib2, iclass 34, count 0 2006.257.04:50:34.90#ibcon#*mode == 0, iclass 34, count 0 2006.257.04:50:34.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.04:50:34.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.04:50:34.90#ibcon#*before write, iclass 34, count 0 2006.257.04:50:34.90#ibcon#enter sib2, iclass 34, count 0 2006.257.04:50:34.90#ibcon#flushed, iclass 34, count 0 2006.257.04:50:34.90#ibcon#about to write, iclass 34, count 0 2006.257.04:50:34.90#ibcon#wrote, iclass 34, count 0 2006.257.04:50:34.90#ibcon#about to read 3, iclass 34, count 0 2006.257.04:50:34.94#ibcon#read 3, iclass 34, count 0 2006.257.04:50:34.94#ibcon#about to read 4, iclass 34, count 0 2006.257.04:50:34.94#ibcon#read 4, iclass 34, count 0 2006.257.04:50:34.94#ibcon#about to read 5, iclass 34, count 0 2006.257.04:50:34.94#ibcon#read 5, iclass 34, count 0 2006.257.04:50:34.94#ibcon#about to read 6, iclass 34, count 0 2006.257.04:50:34.94#ibcon#read 6, iclass 34, count 0 2006.257.04:50:34.94#ibcon#end of sib2, iclass 34, count 0 2006.257.04:50:34.94#ibcon#*after write, iclass 34, count 0 2006.257.04:50:34.94#ibcon#*before return 0, iclass 34, count 0 2006.257.04:50:34.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:34.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.04:50:34.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.04:50:34.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.04:50:34.95$vck44/vb=7,4 2006.257.04:50:34.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.04:50:34.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.04:50:34.95#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:34.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:34.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:34.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:34.99#ibcon#enter wrdev, iclass 36, count 2 2006.257.04:50:34.99#ibcon#first serial, iclass 36, count 2 2006.257.04:50:34.99#ibcon#enter sib2, iclass 36, count 2 2006.257.04:50:34.99#ibcon#flushed, iclass 36, count 2 2006.257.04:50:34.99#ibcon#about to write, iclass 36, count 2 2006.257.04:50:34.99#ibcon#wrote, iclass 36, count 2 2006.257.04:50:34.99#ibcon#about to read 3, iclass 36, count 2 2006.257.04:50:35.01#ibcon#read 3, iclass 36, count 2 2006.257.04:50:35.01#ibcon#about to read 4, iclass 36, count 2 2006.257.04:50:35.01#ibcon#read 4, iclass 36, count 2 2006.257.04:50:35.01#ibcon#about to read 5, iclass 36, count 2 2006.257.04:50:35.01#ibcon#read 5, iclass 36, count 2 2006.257.04:50:35.01#ibcon#about to read 6, iclass 36, count 2 2006.257.04:50:35.01#ibcon#read 6, iclass 36, count 2 2006.257.04:50:35.01#ibcon#end of sib2, iclass 36, count 2 2006.257.04:50:35.01#ibcon#*mode == 0, iclass 36, count 2 2006.257.04:50:35.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.04:50:35.01#ibcon#[27=AT07-04\r\n] 2006.257.04:50:35.01#ibcon#*before write, iclass 36, count 2 2006.257.04:50:35.01#ibcon#enter sib2, iclass 36, count 2 2006.257.04:50:35.01#ibcon#flushed, iclass 36, count 2 2006.257.04:50:35.01#ibcon#about to write, iclass 36, count 2 2006.257.04:50:35.01#ibcon#wrote, iclass 36, count 2 2006.257.04:50:35.01#ibcon#about to read 3, iclass 36, count 2 2006.257.04:50:35.04#ibcon#read 3, iclass 36, count 2 2006.257.04:50:35.04#ibcon#about to read 4, iclass 36, count 2 2006.257.04:50:35.04#ibcon#read 4, iclass 36, count 2 2006.257.04:50:35.04#ibcon#about to read 5, iclass 36, count 2 2006.257.04:50:35.04#ibcon#read 5, iclass 36, count 2 2006.257.04:50:35.04#ibcon#about to read 6, iclass 36, count 2 2006.257.04:50:35.04#ibcon#read 6, iclass 36, count 2 2006.257.04:50:35.04#ibcon#end of sib2, iclass 36, count 2 2006.257.04:50:35.04#ibcon#*after write, iclass 36, count 2 2006.257.04:50:35.04#ibcon#*before return 0, iclass 36, count 2 2006.257.04:50:35.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:35.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.04:50:35.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.04:50:35.04#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:35.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:35.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:35.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:35.16#ibcon#enter wrdev, iclass 36, count 0 2006.257.04:50:35.16#ibcon#first serial, iclass 36, count 0 2006.257.04:50:35.16#ibcon#enter sib2, iclass 36, count 0 2006.257.04:50:35.16#ibcon#flushed, iclass 36, count 0 2006.257.04:50:35.16#ibcon#about to write, iclass 36, count 0 2006.257.04:50:35.16#ibcon#wrote, iclass 36, count 0 2006.257.04:50:35.16#ibcon#about to read 3, iclass 36, count 0 2006.257.04:50:35.18#ibcon#read 3, iclass 36, count 0 2006.257.04:50:35.18#ibcon#about to read 4, iclass 36, count 0 2006.257.04:50:35.18#ibcon#read 4, iclass 36, count 0 2006.257.04:50:35.18#ibcon#about to read 5, iclass 36, count 0 2006.257.04:50:35.18#ibcon#read 5, iclass 36, count 0 2006.257.04:50:35.18#ibcon#about to read 6, iclass 36, count 0 2006.257.04:50:35.18#ibcon#read 6, iclass 36, count 0 2006.257.04:50:35.18#ibcon#end of sib2, iclass 36, count 0 2006.257.04:50:35.18#ibcon#*mode == 0, iclass 36, count 0 2006.257.04:50:35.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.04:50:35.18#ibcon#[27=USB\r\n] 2006.257.04:50:35.18#ibcon#*before write, iclass 36, count 0 2006.257.04:50:35.18#ibcon#enter sib2, iclass 36, count 0 2006.257.04:50:35.18#ibcon#flushed, iclass 36, count 0 2006.257.04:50:35.18#ibcon#about to write, iclass 36, count 0 2006.257.04:50:35.18#ibcon#wrote, iclass 36, count 0 2006.257.04:50:35.18#ibcon#about to read 3, iclass 36, count 0 2006.257.04:50:35.21#ibcon#read 3, iclass 36, count 0 2006.257.04:50:35.21#ibcon#about to read 4, iclass 36, count 0 2006.257.04:50:35.21#ibcon#read 4, iclass 36, count 0 2006.257.04:50:35.21#ibcon#about to read 5, iclass 36, count 0 2006.257.04:50:35.21#ibcon#read 5, iclass 36, count 0 2006.257.04:50:35.21#ibcon#about to read 6, iclass 36, count 0 2006.257.04:50:35.21#ibcon#read 6, iclass 36, count 0 2006.257.04:50:35.21#ibcon#end of sib2, iclass 36, count 0 2006.257.04:50:35.21#ibcon#*after write, iclass 36, count 0 2006.257.04:50:35.21#ibcon#*before return 0, iclass 36, count 0 2006.257.04:50:35.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:35.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.04:50:35.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.04:50:35.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.04:50:35.22$vck44/vblo=8,744.99 2006.257.04:50:35.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.04:50:35.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.04:50:35.22#ibcon#ireg 17 cls_cnt 0 2006.257.04:50:35.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:35.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:35.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:35.22#ibcon#enter wrdev, iclass 38, count 0 2006.257.04:50:35.22#ibcon#first serial, iclass 38, count 0 2006.257.04:50:35.22#ibcon#enter sib2, iclass 38, count 0 2006.257.04:50:35.22#ibcon#flushed, iclass 38, count 0 2006.257.04:50:35.22#ibcon#about to write, iclass 38, count 0 2006.257.04:50:35.22#ibcon#wrote, iclass 38, count 0 2006.257.04:50:35.22#ibcon#about to read 3, iclass 38, count 0 2006.257.04:50:35.23#ibcon#read 3, iclass 38, count 0 2006.257.04:50:35.23#ibcon#about to read 4, iclass 38, count 0 2006.257.04:50:35.23#ibcon#read 4, iclass 38, count 0 2006.257.04:50:35.23#ibcon#about to read 5, iclass 38, count 0 2006.257.04:50:35.23#ibcon#read 5, iclass 38, count 0 2006.257.04:50:35.23#ibcon#about to read 6, iclass 38, count 0 2006.257.04:50:35.23#ibcon#read 6, iclass 38, count 0 2006.257.04:50:35.23#ibcon#end of sib2, iclass 38, count 0 2006.257.04:50:35.23#ibcon#*mode == 0, iclass 38, count 0 2006.257.04:50:35.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.04:50:35.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.04:50:35.23#ibcon#*before write, iclass 38, count 0 2006.257.04:50:35.23#ibcon#enter sib2, iclass 38, count 0 2006.257.04:50:35.23#ibcon#flushed, iclass 38, count 0 2006.257.04:50:35.23#ibcon#about to write, iclass 38, count 0 2006.257.04:50:35.23#ibcon#wrote, iclass 38, count 0 2006.257.04:50:35.24#ibcon#about to read 3, iclass 38, count 0 2006.257.04:50:35.27#ibcon#read 3, iclass 38, count 0 2006.257.04:50:35.27#ibcon#about to read 4, iclass 38, count 0 2006.257.04:50:35.27#ibcon#read 4, iclass 38, count 0 2006.257.04:50:35.27#ibcon#about to read 5, iclass 38, count 0 2006.257.04:50:35.27#ibcon#read 5, iclass 38, count 0 2006.257.04:50:35.27#ibcon#about to read 6, iclass 38, count 0 2006.257.04:50:35.27#ibcon#read 6, iclass 38, count 0 2006.257.04:50:35.27#ibcon#end of sib2, iclass 38, count 0 2006.257.04:50:35.27#ibcon#*after write, iclass 38, count 0 2006.257.04:50:35.27#ibcon#*before return 0, iclass 38, count 0 2006.257.04:50:35.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:35.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.04:50:35.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.04:50:35.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.04:50:35.28$vck44/vb=8,4 2006.257.04:50:35.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.04:50:35.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.04:50:35.28#ibcon#ireg 11 cls_cnt 2 2006.257.04:50:35.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:50:35.31#abcon#<5=/14 1.5 4.5 19.67 931012.0\r\n> 2006.257.04:50:35.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:50:35.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:50:35.32#ibcon#enter wrdev, iclass 3, count 2 2006.257.04:50:35.32#ibcon#first serial, iclass 3, count 2 2006.257.04:50:35.32#ibcon#enter sib2, iclass 3, count 2 2006.257.04:50:35.32#ibcon#flushed, iclass 3, count 2 2006.257.04:50:35.32#ibcon#about to write, iclass 3, count 2 2006.257.04:50:35.32#ibcon#wrote, iclass 3, count 2 2006.257.04:50:35.32#ibcon#about to read 3, iclass 3, count 2 2006.257.04:50:35.33#abcon#{5=INTERFACE CLEAR} 2006.257.04:50:35.34#ibcon#read 3, iclass 3, count 2 2006.257.04:50:35.34#ibcon#about to read 4, iclass 3, count 2 2006.257.04:50:35.34#ibcon#read 4, iclass 3, count 2 2006.257.04:50:35.34#ibcon#about to read 5, iclass 3, count 2 2006.257.04:50:35.34#ibcon#read 5, iclass 3, count 2 2006.257.04:50:35.34#ibcon#about to read 6, iclass 3, count 2 2006.257.04:50:35.34#ibcon#read 6, iclass 3, count 2 2006.257.04:50:35.34#ibcon#end of sib2, iclass 3, count 2 2006.257.04:50:35.34#ibcon#*mode == 0, iclass 3, count 2 2006.257.04:50:35.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.04:50:35.34#ibcon#[27=AT08-04\r\n] 2006.257.04:50:35.34#ibcon#*before write, iclass 3, count 2 2006.257.04:50:35.34#ibcon#enter sib2, iclass 3, count 2 2006.257.04:50:35.34#ibcon#flushed, iclass 3, count 2 2006.257.04:50:35.34#ibcon#about to write, iclass 3, count 2 2006.257.04:50:35.34#ibcon#wrote, iclass 3, count 2 2006.257.04:50:35.34#ibcon#about to read 3, iclass 3, count 2 2006.257.04:50:35.37#ibcon#read 3, iclass 3, count 2 2006.257.04:50:35.37#ibcon#about to read 4, iclass 3, count 2 2006.257.04:50:35.37#ibcon#read 4, iclass 3, count 2 2006.257.04:50:35.37#ibcon#about to read 5, iclass 3, count 2 2006.257.04:50:35.37#ibcon#read 5, iclass 3, count 2 2006.257.04:50:35.37#ibcon#about to read 6, iclass 3, count 2 2006.257.04:50:35.37#ibcon#read 6, iclass 3, count 2 2006.257.04:50:35.37#ibcon#end of sib2, iclass 3, count 2 2006.257.04:50:35.37#ibcon#*after write, iclass 3, count 2 2006.257.04:50:35.37#ibcon#*before return 0, iclass 3, count 2 2006.257.04:50:35.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:50:35.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.04:50:35.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.04:50:35.37#ibcon#ireg 7 cls_cnt 0 2006.257.04:50:35.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:50:35.39#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:50:35.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:50:35.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:50:35.49#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:50:35.49#ibcon#first serial, iclass 3, count 0 2006.257.04:50:35.49#ibcon#enter sib2, iclass 3, count 0 2006.257.04:50:35.49#ibcon#flushed, iclass 3, count 0 2006.257.04:50:35.49#ibcon#about to write, iclass 3, count 0 2006.257.04:50:35.49#ibcon#wrote, iclass 3, count 0 2006.257.04:50:35.49#ibcon#about to read 3, iclass 3, count 0 2006.257.04:50:35.51#ibcon#read 3, iclass 3, count 0 2006.257.04:50:35.51#ibcon#about to read 4, iclass 3, count 0 2006.257.04:50:35.51#ibcon#read 4, iclass 3, count 0 2006.257.04:50:35.51#ibcon#about to read 5, iclass 3, count 0 2006.257.04:50:35.51#ibcon#read 5, iclass 3, count 0 2006.257.04:50:35.51#ibcon#about to read 6, iclass 3, count 0 2006.257.04:50:35.51#ibcon#read 6, iclass 3, count 0 2006.257.04:50:35.51#ibcon#end of sib2, iclass 3, count 0 2006.257.04:50:35.51#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:50:35.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:50:35.51#ibcon#[27=USB\r\n] 2006.257.04:50:35.51#ibcon#*before write, iclass 3, count 0 2006.257.04:50:35.51#ibcon#enter sib2, iclass 3, count 0 2006.257.04:50:35.51#ibcon#flushed, iclass 3, count 0 2006.257.04:50:35.51#ibcon#about to write, iclass 3, count 0 2006.257.04:50:35.51#ibcon#wrote, iclass 3, count 0 2006.257.04:50:35.51#ibcon#about to read 3, iclass 3, count 0 2006.257.04:50:35.54#ibcon#read 3, iclass 3, count 0 2006.257.04:50:35.54#ibcon#about to read 4, iclass 3, count 0 2006.257.04:50:35.54#ibcon#read 4, iclass 3, count 0 2006.257.04:50:35.54#ibcon#about to read 5, iclass 3, count 0 2006.257.04:50:35.54#ibcon#read 5, iclass 3, count 0 2006.257.04:50:35.54#ibcon#about to read 6, iclass 3, count 0 2006.257.04:50:35.54#ibcon#read 6, iclass 3, count 0 2006.257.04:50:35.54#ibcon#end of sib2, iclass 3, count 0 2006.257.04:50:35.54#ibcon#*after write, iclass 3, count 0 2006.257.04:50:35.54#ibcon#*before return 0, iclass 3, count 0 2006.257.04:50:35.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:50:35.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.04:50:35.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:50:35.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:50:35.55$vck44/vabw=wide 2006.257.04:50:35.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.04:50:35.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.04:50:35.55#ibcon#ireg 8 cls_cnt 0 2006.257.04:50:35.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:35.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:35.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:35.55#ibcon#enter wrdev, iclass 10, count 0 2006.257.04:50:35.55#ibcon#first serial, iclass 10, count 0 2006.257.04:50:35.55#ibcon#enter sib2, iclass 10, count 0 2006.257.04:50:35.55#ibcon#flushed, iclass 10, count 0 2006.257.04:50:35.55#ibcon#about to write, iclass 10, count 0 2006.257.04:50:35.55#ibcon#wrote, iclass 10, count 0 2006.257.04:50:35.55#ibcon#about to read 3, iclass 10, count 0 2006.257.04:50:35.56#ibcon#read 3, iclass 10, count 0 2006.257.04:50:35.56#ibcon#about to read 4, iclass 10, count 0 2006.257.04:50:35.56#ibcon#read 4, iclass 10, count 0 2006.257.04:50:35.56#ibcon#about to read 5, iclass 10, count 0 2006.257.04:50:35.56#ibcon#read 5, iclass 10, count 0 2006.257.04:50:35.56#ibcon#about to read 6, iclass 10, count 0 2006.257.04:50:35.56#ibcon#read 6, iclass 10, count 0 2006.257.04:50:35.56#ibcon#end of sib2, iclass 10, count 0 2006.257.04:50:35.56#ibcon#*mode == 0, iclass 10, count 0 2006.257.04:50:35.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.04:50:35.56#ibcon#[25=BW32\r\n] 2006.257.04:50:35.56#ibcon#*before write, iclass 10, count 0 2006.257.04:50:35.56#ibcon#enter sib2, iclass 10, count 0 2006.257.04:50:35.56#ibcon#flushed, iclass 10, count 0 2006.257.04:50:35.56#ibcon#about to write, iclass 10, count 0 2006.257.04:50:35.56#ibcon#wrote, iclass 10, count 0 2006.257.04:50:35.56#ibcon#about to read 3, iclass 10, count 0 2006.257.04:50:35.59#ibcon#read 3, iclass 10, count 0 2006.257.04:50:35.59#ibcon#about to read 4, iclass 10, count 0 2006.257.04:50:35.59#ibcon#read 4, iclass 10, count 0 2006.257.04:50:35.59#ibcon#about to read 5, iclass 10, count 0 2006.257.04:50:35.59#ibcon#read 5, iclass 10, count 0 2006.257.04:50:35.59#ibcon#about to read 6, iclass 10, count 0 2006.257.04:50:35.59#ibcon#read 6, iclass 10, count 0 2006.257.04:50:35.59#ibcon#end of sib2, iclass 10, count 0 2006.257.04:50:35.59#ibcon#*after write, iclass 10, count 0 2006.257.04:50:35.59#ibcon#*before return 0, iclass 10, count 0 2006.257.04:50:35.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:35.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.04:50:35.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.04:50:35.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.04:50:35.60$vck44/vbbw=wide 2006.257.04:50:35.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.04:50:35.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.04:50:35.60#ibcon#ireg 8 cls_cnt 0 2006.257.04:50:35.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:50:35.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:50:35.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:50:35.65#ibcon#enter wrdev, iclass 12, count 0 2006.257.04:50:35.65#ibcon#first serial, iclass 12, count 0 2006.257.04:50:35.65#ibcon#enter sib2, iclass 12, count 0 2006.257.04:50:35.65#ibcon#flushed, iclass 12, count 0 2006.257.04:50:35.65#ibcon#about to write, iclass 12, count 0 2006.257.04:50:35.65#ibcon#wrote, iclass 12, count 0 2006.257.04:50:35.65#ibcon#about to read 3, iclass 12, count 0 2006.257.04:50:35.67#ibcon#read 3, iclass 12, count 0 2006.257.04:50:35.67#ibcon#about to read 4, iclass 12, count 0 2006.257.04:50:35.67#ibcon#read 4, iclass 12, count 0 2006.257.04:50:35.67#ibcon#about to read 5, iclass 12, count 0 2006.257.04:50:35.67#ibcon#read 5, iclass 12, count 0 2006.257.04:50:35.67#ibcon#about to read 6, iclass 12, count 0 2006.257.04:50:35.67#ibcon#read 6, iclass 12, count 0 2006.257.04:50:35.67#ibcon#end of sib2, iclass 12, count 0 2006.257.04:50:35.67#ibcon#*mode == 0, iclass 12, count 0 2006.257.04:50:35.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.04:50:35.67#ibcon#[27=BW32\r\n] 2006.257.04:50:35.67#ibcon#*before write, iclass 12, count 0 2006.257.04:50:35.67#ibcon#enter sib2, iclass 12, count 0 2006.257.04:50:35.67#ibcon#flushed, iclass 12, count 0 2006.257.04:50:35.67#ibcon#about to write, iclass 12, count 0 2006.257.04:50:35.67#ibcon#wrote, iclass 12, count 0 2006.257.04:50:35.67#ibcon#about to read 3, iclass 12, count 0 2006.257.04:50:35.70#ibcon#read 3, iclass 12, count 0 2006.257.04:50:35.70#ibcon#about to read 4, iclass 12, count 0 2006.257.04:50:35.70#ibcon#read 4, iclass 12, count 0 2006.257.04:50:35.70#ibcon#about to read 5, iclass 12, count 0 2006.257.04:50:35.70#ibcon#read 5, iclass 12, count 0 2006.257.04:50:35.70#ibcon#about to read 6, iclass 12, count 0 2006.257.04:50:35.70#ibcon#read 6, iclass 12, count 0 2006.257.04:50:35.70#ibcon#end of sib2, iclass 12, count 0 2006.257.04:50:35.70#ibcon#*after write, iclass 12, count 0 2006.257.04:50:35.70#ibcon#*before return 0, iclass 12, count 0 2006.257.04:50:35.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:50:35.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.04:50:35.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.04:50:35.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.04:50:35.71$setupk4/ifdk4 2006.257.04:50:35.71$ifdk4/lo= 2006.257.04:50:35.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.04:50:35.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.04:50:35.71$ifdk4/patch= 2006.257.04:50:35.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.04:50:35.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.04:50:35.71$setupk4/!*+20s 2006.257.04:50:45.14#trakl#Source acquired 2006.257.04:50:45.48#abcon#<5=/14 1.5 4.5 19.68 931012.0\r\n> 2006.257.04:50:45.50#abcon#{5=INTERFACE CLEAR} 2006.257.04:50:45.56#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:50:46.15#flagr#flagr/antenna,acquired 2006.257.04:50:50.38$setupk4/"tpicd 2006.257.04:50:50.38$setupk4/echo=off 2006.257.04:50:50.38$setupk4/xlog=off 2006.257.04:50:50.39:!2006.257.04:53:47 2006.257.04:53:47.01:preob 2006.257.04:53:48.14/onsource/TRACKING 2006.257.04:53:48.14:!2006.257.04:53:57 2006.257.04:53:57.00:"tape 2006.257.04:53:57.00:"st=record 2006.257.04:53:57.00:data_valid=on 2006.257.04:53:57.00:midob 2006.257.04:53:57.14/onsource/TRACKING 2006.257.04:53:57.15/wx/19.70,1011.9,93 2006.257.04:53:57.22/cable/+6.4824E-03 2006.257.04:53:58.31/va/01,08,usb,yes,32,34 2006.257.04:53:58.31/va/02,07,usb,yes,34,35 2006.257.04:53:58.31/va/03,08,usb,yes,31,32 2006.257.04:53:58.31/va/04,07,usb,yes,35,37 2006.257.04:53:58.31/va/05,04,usb,yes,32,32 2006.257.04:53:58.31/va/06,04,usb,yes,35,35 2006.257.04:53:58.31/va/07,04,usb,yes,36,37 2006.257.04:53:58.31/va/08,04,usb,yes,30,37 2006.257.04:53:58.54/valo/01,524.99,yes,locked 2006.257.04:53:58.54/valo/02,534.99,yes,locked 2006.257.04:53:58.54/valo/03,564.99,yes,locked 2006.257.04:53:58.54/valo/04,624.99,yes,locked 2006.257.04:53:58.54/valo/05,734.99,yes,locked 2006.257.04:53:58.54/valo/06,814.99,yes,locked 2006.257.04:53:58.54/valo/07,864.99,yes,locked 2006.257.04:53:58.54/valo/08,884.99,yes,locked 2006.257.04:53:59.63/vb/01,04,usb,yes,30,28 2006.257.04:53:59.63/vb/02,05,usb,yes,29,28 2006.257.04:53:59.63/vb/03,04,usb,yes,29,32 2006.257.04:53:59.63/vb/04,05,usb,yes,30,29 2006.257.04:53:59.63/vb/05,04,usb,yes,26,28 2006.257.04:53:59.63/vb/06,04,usb,yes,31,27 2006.257.04:53:59.63/vb/07,04,usb,yes,30,30 2006.257.04:53:59.63/vb/08,04,usb,yes,28,31 2006.257.04:53:59.86/vblo/01,629.99,yes,locked 2006.257.04:53:59.86/vblo/02,634.99,yes,locked 2006.257.04:53:59.86/vblo/03,649.99,yes,locked 2006.257.04:53:59.86/vblo/04,679.99,yes,locked 2006.257.04:53:59.86/vblo/05,709.99,yes,locked 2006.257.04:53:59.86/vblo/06,719.99,yes,locked 2006.257.04:53:59.86/vblo/07,734.99,yes,locked 2006.257.04:53:59.86/vblo/08,744.99,yes,locked 2006.257.04:54:00.01/vabw/8 2006.257.04:54:00.16/vbbw/8 2006.257.04:54:00.25/xfe/off,on,16.7 2006.257.04:54:00.64/ifatt/23,28,28,28 2006.257.04:54:01.07/fmout-gps/S +4.56E-07 2006.257.04:54:01.11:!2006.257.04:57:27 2006.257.04:57:27.01:data_valid=off 2006.257.04:57:27.02:"et 2006.257.04:57:27.02:!+3s 2006.257.04:57:30.04:"tape 2006.257.04:57:30.05:postob 2006.257.04:57:30.19/cable/+6.4830E-03 2006.257.04:57:30.20/wx/19.69,1011.9,93 2006.257.04:57:30.25/fmout-gps/S +4.59E-07 2006.257.04:57:30.26:scan_name=257-0500,jd0609,40 2006.257.04:57:30.26:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.257.04:57:32.14#flagr#flagr/antenna,new-source 2006.257.04:57:32.15:checkk5 2006.257.04:57:32.59/chk_autoobs//k5ts1/ autoobs is running! 2006.257.04:57:32.98/chk_autoobs//k5ts2/ autoobs is running! 2006.257.04:57:33.39/chk_autoobs//k5ts3/ autoobs is running! 2006.257.04:57:34.18/chk_autoobs//k5ts4/ autoobs is running! 2006.257.04:57:34.57/chk_obsdata//k5ts1/T2570453??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.04:57:34.97/chk_obsdata//k5ts2/T2570453??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.04:57:35.39/chk_obsdata//k5ts3/T2570453??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.04:57:35.81/chk_obsdata//k5ts4/T2570453??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.04:57:36.55/k5log//k5ts1_log_newline 2006.257.04:57:37.26/k5log//k5ts2_log_newline 2006.257.04:57:38.01/k5log//k5ts3_log_newline 2006.257.04:57:38.73/k5log//k5ts4_log_newline 2006.257.04:57:38.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.04:57:38.75:setupk4=1 2006.257.04:57:38.75$setupk4/echo=on 2006.257.04:57:38.75$setupk4/pcalon 2006.257.04:57:38.75$pcalon/"no phase cal control is implemented here 2006.257.04:57:38.75$setupk4/"tpicd=stop 2006.257.04:57:38.75$setupk4/"rec=synch_on 2006.257.04:57:38.75$setupk4/"rec_mode=128 2006.257.04:57:38.75$setupk4/!* 2006.257.04:57:38.75$setupk4/recpk4 2006.257.04:57:38.75$recpk4/recpatch= 2006.257.04:57:38.76$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.04:57:38.76$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.04:57:38.76$setupk4/vck44 2006.257.04:57:38.76$vck44/valo=1,524.99 2006.257.04:57:38.76#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.04:57:38.76#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.04:57:38.76#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:38.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:38.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:38.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:38.76#ibcon#enter wrdev, iclass 37, count 0 2006.257.04:57:38.76#ibcon#first serial, iclass 37, count 0 2006.257.04:57:38.76#ibcon#enter sib2, iclass 37, count 0 2006.257.04:57:38.76#ibcon#flushed, iclass 37, count 0 2006.257.04:57:38.76#ibcon#about to write, iclass 37, count 0 2006.257.04:57:38.76#ibcon#wrote, iclass 37, count 0 2006.257.04:57:38.76#ibcon#about to read 3, iclass 37, count 0 2006.257.04:57:38.77#ibcon#read 3, iclass 37, count 0 2006.257.04:57:38.77#ibcon#about to read 4, iclass 37, count 0 2006.257.04:57:38.77#ibcon#read 4, iclass 37, count 0 2006.257.04:57:38.77#ibcon#about to read 5, iclass 37, count 0 2006.257.04:57:38.77#ibcon#read 5, iclass 37, count 0 2006.257.04:57:38.77#ibcon#about to read 6, iclass 37, count 0 2006.257.04:57:38.77#ibcon#read 6, iclass 37, count 0 2006.257.04:57:38.77#ibcon#end of sib2, iclass 37, count 0 2006.257.04:57:38.77#ibcon#*mode == 0, iclass 37, count 0 2006.257.04:57:38.77#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.04:57:38.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.04:57:38.77#ibcon#*before write, iclass 37, count 0 2006.257.04:57:38.77#ibcon#enter sib2, iclass 37, count 0 2006.257.04:57:38.77#ibcon#flushed, iclass 37, count 0 2006.257.04:57:38.77#ibcon#about to write, iclass 37, count 0 2006.257.04:57:38.77#ibcon#wrote, iclass 37, count 0 2006.257.04:57:38.77#ibcon#about to read 3, iclass 37, count 0 2006.257.04:57:38.82#ibcon#read 3, iclass 37, count 0 2006.257.04:57:38.82#ibcon#about to read 4, iclass 37, count 0 2006.257.04:57:38.82#ibcon#read 4, iclass 37, count 0 2006.257.04:57:38.82#ibcon#about to read 5, iclass 37, count 0 2006.257.04:57:38.82#ibcon#read 5, iclass 37, count 0 2006.257.04:57:38.82#ibcon#about to read 6, iclass 37, count 0 2006.257.04:57:38.82#ibcon#read 6, iclass 37, count 0 2006.257.04:57:38.82#ibcon#end of sib2, iclass 37, count 0 2006.257.04:57:38.82#ibcon#*after write, iclass 37, count 0 2006.257.04:57:38.82#ibcon#*before return 0, iclass 37, count 0 2006.257.04:57:38.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:38.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:38.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.04:57:38.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.04:57:38.82$vck44/va=1,8 2006.257.04:57:38.82#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.04:57:38.82#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.04:57:38.82#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:38.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:38.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:38.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:38.82#ibcon#enter wrdev, iclass 39, count 2 2006.257.04:57:38.82#ibcon#first serial, iclass 39, count 2 2006.257.04:57:38.82#ibcon#enter sib2, iclass 39, count 2 2006.257.04:57:38.82#ibcon#flushed, iclass 39, count 2 2006.257.04:57:38.82#ibcon#about to write, iclass 39, count 2 2006.257.04:57:38.82#ibcon#wrote, iclass 39, count 2 2006.257.04:57:38.82#ibcon#about to read 3, iclass 39, count 2 2006.257.04:57:38.84#ibcon#read 3, iclass 39, count 2 2006.257.04:57:38.84#ibcon#about to read 4, iclass 39, count 2 2006.257.04:57:38.84#ibcon#read 4, iclass 39, count 2 2006.257.04:57:38.84#ibcon#about to read 5, iclass 39, count 2 2006.257.04:57:38.84#ibcon#read 5, iclass 39, count 2 2006.257.04:57:38.84#ibcon#about to read 6, iclass 39, count 2 2006.257.04:57:38.84#ibcon#read 6, iclass 39, count 2 2006.257.04:57:38.84#ibcon#end of sib2, iclass 39, count 2 2006.257.04:57:38.84#ibcon#*mode == 0, iclass 39, count 2 2006.257.04:57:38.84#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.04:57:38.84#ibcon#[25=AT01-08\r\n] 2006.257.04:57:38.84#ibcon#*before write, iclass 39, count 2 2006.257.04:57:38.84#ibcon#enter sib2, iclass 39, count 2 2006.257.04:57:38.84#ibcon#flushed, iclass 39, count 2 2006.257.04:57:38.84#ibcon#about to write, iclass 39, count 2 2006.257.04:57:38.84#ibcon#wrote, iclass 39, count 2 2006.257.04:57:38.84#ibcon#about to read 3, iclass 39, count 2 2006.257.04:57:38.87#ibcon#read 3, iclass 39, count 2 2006.257.04:57:38.87#ibcon#about to read 4, iclass 39, count 2 2006.257.04:57:38.87#ibcon#read 4, iclass 39, count 2 2006.257.04:57:38.87#ibcon#about to read 5, iclass 39, count 2 2006.257.04:57:38.87#ibcon#read 5, iclass 39, count 2 2006.257.04:57:38.87#ibcon#about to read 6, iclass 39, count 2 2006.257.04:57:38.87#ibcon#read 6, iclass 39, count 2 2006.257.04:57:38.87#ibcon#end of sib2, iclass 39, count 2 2006.257.04:57:38.87#ibcon#*after write, iclass 39, count 2 2006.257.04:57:38.87#ibcon#*before return 0, iclass 39, count 2 2006.257.04:57:38.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:38.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:38.87#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.04:57:38.87#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:38.87#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:38.99#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:38.99#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:38.99#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:57:38.99#ibcon#first serial, iclass 39, count 0 2006.257.04:57:38.99#ibcon#enter sib2, iclass 39, count 0 2006.257.04:57:38.99#ibcon#flushed, iclass 39, count 0 2006.257.04:57:38.99#ibcon#about to write, iclass 39, count 0 2006.257.04:57:38.99#ibcon#wrote, iclass 39, count 0 2006.257.04:57:38.99#ibcon#about to read 3, iclass 39, count 0 2006.257.04:57:39.01#ibcon#read 3, iclass 39, count 0 2006.257.04:57:39.01#ibcon#about to read 4, iclass 39, count 0 2006.257.04:57:39.01#ibcon#read 4, iclass 39, count 0 2006.257.04:57:39.01#ibcon#about to read 5, iclass 39, count 0 2006.257.04:57:39.01#ibcon#read 5, iclass 39, count 0 2006.257.04:57:39.01#ibcon#about to read 6, iclass 39, count 0 2006.257.04:57:39.01#ibcon#read 6, iclass 39, count 0 2006.257.04:57:39.01#ibcon#end of sib2, iclass 39, count 0 2006.257.04:57:39.01#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:57:39.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:57:39.01#ibcon#[25=USB\r\n] 2006.257.04:57:39.01#ibcon#*before write, iclass 39, count 0 2006.257.04:57:39.01#ibcon#enter sib2, iclass 39, count 0 2006.257.04:57:39.01#ibcon#flushed, iclass 39, count 0 2006.257.04:57:39.01#ibcon#about to write, iclass 39, count 0 2006.257.04:57:39.01#ibcon#wrote, iclass 39, count 0 2006.257.04:57:39.01#ibcon#about to read 3, iclass 39, count 0 2006.257.04:57:39.04#ibcon#read 3, iclass 39, count 0 2006.257.04:57:39.04#ibcon#about to read 4, iclass 39, count 0 2006.257.04:57:39.04#ibcon#read 4, iclass 39, count 0 2006.257.04:57:39.04#ibcon#about to read 5, iclass 39, count 0 2006.257.04:57:39.04#ibcon#read 5, iclass 39, count 0 2006.257.04:57:39.04#ibcon#about to read 6, iclass 39, count 0 2006.257.04:57:39.04#ibcon#read 6, iclass 39, count 0 2006.257.04:57:39.04#ibcon#end of sib2, iclass 39, count 0 2006.257.04:57:39.04#ibcon#*after write, iclass 39, count 0 2006.257.04:57:39.04#ibcon#*before return 0, iclass 39, count 0 2006.257.04:57:39.04#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:39.04#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:39.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:57:39.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:57:39.04$vck44/valo=2,534.99 2006.257.04:57:39.04#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.04:57:39.04#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.04:57:39.04#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:39.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:39.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:39.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:39.04#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:57:39.04#ibcon#first serial, iclass 3, count 0 2006.257.04:57:39.04#ibcon#enter sib2, iclass 3, count 0 2006.257.04:57:39.04#ibcon#flushed, iclass 3, count 0 2006.257.04:57:39.04#ibcon#about to write, iclass 3, count 0 2006.257.04:57:39.04#ibcon#wrote, iclass 3, count 0 2006.257.04:57:39.04#ibcon#about to read 3, iclass 3, count 0 2006.257.04:57:39.06#ibcon#read 3, iclass 3, count 0 2006.257.04:57:39.06#ibcon#about to read 4, iclass 3, count 0 2006.257.04:57:39.06#ibcon#read 4, iclass 3, count 0 2006.257.04:57:39.06#ibcon#about to read 5, iclass 3, count 0 2006.257.04:57:39.06#ibcon#read 5, iclass 3, count 0 2006.257.04:57:39.06#ibcon#about to read 6, iclass 3, count 0 2006.257.04:57:39.06#ibcon#read 6, iclass 3, count 0 2006.257.04:57:39.06#ibcon#end of sib2, iclass 3, count 0 2006.257.04:57:39.06#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:57:39.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:57:39.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.04:57:39.06#ibcon#*before write, iclass 3, count 0 2006.257.04:57:39.06#ibcon#enter sib2, iclass 3, count 0 2006.257.04:57:39.06#ibcon#flushed, iclass 3, count 0 2006.257.04:57:39.06#ibcon#about to write, iclass 3, count 0 2006.257.04:57:39.06#ibcon#wrote, iclass 3, count 0 2006.257.04:57:39.06#ibcon#about to read 3, iclass 3, count 0 2006.257.04:57:39.10#ibcon#read 3, iclass 3, count 0 2006.257.04:57:39.10#ibcon#about to read 4, iclass 3, count 0 2006.257.04:57:39.10#ibcon#read 4, iclass 3, count 0 2006.257.04:57:39.10#ibcon#about to read 5, iclass 3, count 0 2006.257.04:57:39.10#ibcon#read 5, iclass 3, count 0 2006.257.04:57:39.10#ibcon#about to read 6, iclass 3, count 0 2006.257.04:57:39.10#ibcon#read 6, iclass 3, count 0 2006.257.04:57:39.10#ibcon#end of sib2, iclass 3, count 0 2006.257.04:57:39.10#ibcon#*after write, iclass 3, count 0 2006.257.04:57:39.10#ibcon#*before return 0, iclass 3, count 0 2006.257.04:57:39.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:39.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:39.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:57:39.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:57:39.10$vck44/va=2,7 2006.257.04:57:39.10#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.04:57:39.10#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.04:57:39.10#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:39.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:39.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:39.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:39.16#ibcon#enter wrdev, iclass 5, count 2 2006.257.04:57:39.16#ibcon#first serial, iclass 5, count 2 2006.257.04:57:39.16#ibcon#enter sib2, iclass 5, count 2 2006.257.04:57:39.16#ibcon#flushed, iclass 5, count 2 2006.257.04:57:39.16#ibcon#about to write, iclass 5, count 2 2006.257.04:57:39.16#ibcon#wrote, iclass 5, count 2 2006.257.04:57:39.16#ibcon#about to read 3, iclass 5, count 2 2006.257.04:57:39.18#ibcon#read 3, iclass 5, count 2 2006.257.04:57:39.18#ibcon#about to read 4, iclass 5, count 2 2006.257.04:57:39.18#ibcon#read 4, iclass 5, count 2 2006.257.04:57:39.18#ibcon#about to read 5, iclass 5, count 2 2006.257.04:57:39.18#ibcon#read 5, iclass 5, count 2 2006.257.04:57:39.18#ibcon#about to read 6, iclass 5, count 2 2006.257.04:57:39.18#ibcon#read 6, iclass 5, count 2 2006.257.04:57:39.18#ibcon#end of sib2, iclass 5, count 2 2006.257.04:57:39.18#ibcon#*mode == 0, iclass 5, count 2 2006.257.04:57:39.18#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.04:57:39.18#ibcon#[25=AT02-07\r\n] 2006.257.04:57:39.18#ibcon#*before write, iclass 5, count 2 2006.257.04:57:39.18#ibcon#enter sib2, iclass 5, count 2 2006.257.04:57:39.18#ibcon#flushed, iclass 5, count 2 2006.257.04:57:39.18#ibcon#about to write, iclass 5, count 2 2006.257.04:57:39.18#ibcon#wrote, iclass 5, count 2 2006.257.04:57:39.18#ibcon#about to read 3, iclass 5, count 2 2006.257.04:57:39.21#ibcon#read 3, iclass 5, count 2 2006.257.04:57:39.21#ibcon#about to read 4, iclass 5, count 2 2006.257.04:57:39.21#ibcon#read 4, iclass 5, count 2 2006.257.04:57:39.21#ibcon#about to read 5, iclass 5, count 2 2006.257.04:57:39.21#ibcon#read 5, iclass 5, count 2 2006.257.04:57:39.21#ibcon#about to read 6, iclass 5, count 2 2006.257.04:57:39.21#ibcon#read 6, iclass 5, count 2 2006.257.04:57:39.21#ibcon#end of sib2, iclass 5, count 2 2006.257.04:57:39.21#ibcon#*after write, iclass 5, count 2 2006.257.04:57:39.21#ibcon#*before return 0, iclass 5, count 2 2006.257.04:57:39.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:39.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:39.21#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.04:57:39.21#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:39.21#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:39.33#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:39.33#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:39.33#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:57:39.33#ibcon#first serial, iclass 5, count 0 2006.257.04:57:39.33#ibcon#enter sib2, iclass 5, count 0 2006.257.04:57:39.33#ibcon#flushed, iclass 5, count 0 2006.257.04:57:39.33#ibcon#about to write, iclass 5, count 0 2006.257.04:57:39.33#ibcon#wrote, iclass 5, count 0 2006.257.04:57:39.33#ibcon#about to read 3, iclass 5, count 0 2006.257.04:57:39.35#ibcon#read 3, iclass 5, count 0 2006.257.04:57:39.35#ibcon#about to read 4, iclass 5, count 0 2006.257.04:57:39.35#ibcon#read 4, iclass 5, count 0 2006.257.04:57:39.35#ibcon#about to read 5, iclass 5, count 0 2006.257.04:57:39.35#ibcon#read 5, iclass 5, count 0 2006.257.04:57:39.35#ibcon#about to read 6, iclass 5, count 0 2006.257.04:57:39.35#ibcon#read 6, iclass 5, count 0 2006.257.04:57:39.35#ibcon#end of sib2, iclass 5, count 0 2006.257.04:57:39.35#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:57:39.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:57:39.35#ibcon#[25=USB\r\n] 2006.257.04:57:39.35#ibcon#*before write, iclass 5, count 0 2006.257.04:57:39.35#ibcon#enter sib2, iclass 5, count 0 2006.257.04:57:39.35#ibcon#flushed, iclass 5, count 0 2006.257.04:57:39.35#ibcon#about to write, iclass 5, count 0 2006.257.04:57:39.35#ibcon#wrote, iclass 5, count 0 2006.257.04:57:39.35#ibcon#about to read 3, iclass 5, count 0 2006.257.04:57:39.38#ibcon#read 3, iclass 5, count 0 2006.257.04:57:39.38#ibcon#about to read 4, iclass 5, count 0 2006.257.04:57:39.38#ibcon#read 4, iclass 5, count 0 2006.257.04:57:39.38#ibcon#about to read 5, iclass 5, count 0 2006.257.04:57:39.38#ibcon#read 5, iclass 5, count 0 2006.257.04:57:39.38#ibcon#about to read 6, iclass 5, count 0 2006.257.04:57:39.38#ibcon#read 6, iclass 5, count 0 2006.257.04:57:39.38#ibcon#end of sib2, iclass 5, count 0 2006.257.04:57:39.38#ibcon#*after write, iclass 5, count 0 2006.257.04:57:39.38#ibcon#*before return 0, iclass 5, count 0 2006.257.04:57:39.38#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:39.38#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:39.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:57:39.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:57:39.38$vck44/valo=3,564.99 2006.257.04:57:39.38#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.04:57:39.38#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.04:57:39.38#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:39.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:39.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:39.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:39.38#ibcon#enter wrdev, iclass 7, count 0 2006.257.04:57:39.38#ibcon#first serial, iclass 7, count 0 2006.257.04:57:39.38#ibcon#enter sib2, iclass 7, count 0 2006.257.04:57:39.38#ibcon#flushed, iclass 7, count 0 2006.257.04:57:39.38#ibcon#about to write, iclass 7, count 0 2006.257.04:57:39.38#ibcon#wrote, iclass 7, count 0 2006.257.04:57:39.38#ibcon#about to read 3, iclass 7, count 0 2006.257.04:57:39.40#ibcon#read 3, iclass 7, count 0 2006.257.04:57:39.40#ibcon#about to read 4, iclass 7, count 0 2006.257.04:57:39.40#ibcon#read 4, iclass 7, count 0 2006.257.04:57:39.40#ibcon#about to read 5, iclass 7, count 0 2006.257.04:57:39.40#ibcon#read 5, iclass 7, count 0 2006.257.04:57:39.40#ibcon#about to read 6, iclass 7, count 0 2006.257.04:57:39.40#ibcon#read 6, iclass 7, count 0 2006.257.04:57:39.40#ibcon#end of sib2, iclass 7, count 0 2006.257.04:57:39.40#ibcon#*mode == 0, iclass 7, count 0 2006.257.04:57:39.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.04:57:39.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.04:57:39.40#ibcon#*before write, iclass 7, count 0 2006.257.04:57:39.40#ibcon#enter sib2, iclass 7, count 0 2006.257.04:57:39.40#ibcon#flushed, iclass 7, count 0 2006.257.04:57:39.40#ibcon#about to write, iclass 7, count 0 2006.257.04:57:39.40#ibcon#wrote, iclass 7, count 0 2006.257.04:57:39.40#ibcon#about to read 3, iclass 7, count 0 2006.257.04:57:39.44#ibcon#read 3, iclass 7, count 0 2006.257.04:57:39.44#ibcon#about to read 4, iclass 7, count 0 2006.257.04:57:39.44#ibcon#read 4, iclass 7, count 0 2006.257.04:57:39.44#ibcon#about to read 5, iclass 7, count 0 2006.257.04:57:39.44#ibcon#read 5, iclass 7, count 0 2006.257.04:57:39.44#ibcon#about to read 6, iclass 7, count 0 2006.257.04:57:39.44#ibcon#read 6, iclass 7, count 0 2006.257.04:57:39.44#ibcon#end of sib2, iclass 7, count 0 2006.257.04:57:39.44#ibcon#*after write, iclass 7, count 0 2006.257.04:57:39.44#ibcon#*before return 0, iclass 7, count 0 2006.257.04:57:39.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:39.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:39.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.04:57:39.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.04:57:39.44$vck44/va=3,8 2006.257.04:57:39.44#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.04:57:39.44#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.04:57:39.44#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:39.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:39.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:39.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:39.50#ibcon#enter wrdev, iclass 11, count 2 2006.257.04:57:39.50#ibcon#first serial, iclass 11, count 2 2006.257.04:57:39.50#ibcon#enter sib2, iclass 11, count 2 2006.257.04:57:39.50#ibcon#flushed, iclass 11, count 2 2006.257.04:57:39.50#ibcon#about to write, iclass 11, count 2 2006.257.04:57:39.50#ibcon#wrote, iclass 11, count 2 2006.257.04:57:39.50#ibcon#about to read 3, iclass 11, count 2 2006.257.04:57:39.52#ibcon#read 3, iclass 11, count 2 2006.257.04:57:39.52#ibcon#about to read 4, iclass 11, count 2 2006.257.04:57:39.52#ibcon#read 4, iclass 11, count 2 2006.257.04:57:39.52#ibcon#about to read 5, iclass 11, count 2 2006.257.04:57:39.52#ibcon#read 5, iclass 11, count 2 2006.257.04:57:39.52#ibcon#about to read 6, iclass 11, count 2 2006.257.04:57:39.52#ibcon#read 6, iclass 11, count 2 2006.257.04:57:39.52#ibcon#end of sib2, iclass 11, count 2 2006.257.04:57:39.52#ibcon#*mode == 0, iclass 11, count 2 2006.257.04:57:39.52#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.04:57:39.52#ibcon#[25=AT03-08\r\n] 2006.257.04:57:39.52#ibcon#*before write, iclass 11, count 2 2006.257.04:57:39.52#ibcon#enter sib2, iclass 11, count 2 2006.257.04:57:39.52#ibcon#flushed, iclass 11, count 2 2006.257.04:57:39.52#ibcon#about to write, iclass 11, count 2 2006.257.04:57:39.52#ibcon#wrote, iclass 11, count 2 2006.257.04:57:39.52#ibcon#about to read 3, iclass 11, count 2 2006.257.04:57:39.55#ibcon#read 3, iclass 11, count 2 2006.257.04:57:39.55#ibcon#about to read 4, iclass 11, count 2 2006.257.04:57:39.55#ibcon#read 4, iclass 11, count 2 2006.257.04:57:39.55#ibcon#about to read 5, iclass 11, count 2 2006.257.04:57:39.55#ibcon#read 5, iclass 11, count 2 2006.257.04:57:39.55#ibcon#about to read 6, iclass 11, count 2 2006.257.04:57:39.55#ibcon#read 6, iclass 11, count 2 2006.257.04:57:39.55#ibcon#end of sib2, iclass 11, count 2 2006.257.04:57:39.55#ibcon#*after write, iclass 11, count 2 2006.257.04:57:39.55#ibcon#*before return 0, iclass 11, count 2 2006.257.04:57:39.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:39.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:39.55#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.04:57:39.55#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:39.55#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:39.67#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:39.67#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:39.67#ibcon#enter wrdev, iclass 11, count 0 2006.257.04:57:39.67#ibcon#first serial, iclass 11, count 0 2006.257.04:57:39.67#ibcon#enter sib2, iclass 11, count 0 2006.257.04:57:39.67#ibcon#flushed, iclass 11, count 0 2006.257.04:57:39.67#ibcon#about to write, iclass 11, count 0 2006.257.04:57:39.67#ibcon#wrote, iclass 11, count 0 2006.257.04:57:39.67#ibcon#about to read 3, iclass 11, count 0 2006.257.04:57:39.69#ibcon#read 3, iclass 11, count 0 2006.257.04:57:39.69#ibcon#about to read 4, iclass 11, count 0 2006.257.04:57:39.69#ibcon#read 4, iclass 11, count 0 2006.257.04:57:39.69#ibcon#about to read 5, iclass 11, count 0 2006.257.04:57:39.69#ibcon#read 5, iclass 11, count 0 2006.257.04:57:39.69#ibcon#about to read 6, iclass 11, count 0 2006.257.04:57:39.69#ibcon#read 6, iclass 11, count 0 2006.257.04:57:39.69#ibcon#end of sib2, iclass 11, count 0 2006.257.04:57:39.69#ibcon#*mode == 0, iclass 11, count 0 2006.257.04:57:39.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.04:57:39.69#ibcon#[25=USB\r\n] 2006.257.04:57:39.69#ibcon#*before write, iclass 11, count 0 2006.257.04:57:39.69#ibcon#enter sib2, iclass 11, count 0 2006.257.04:57:39.69#ibcon#flushed, iclass 11, count 0 2006.257.04:57:39.69#ibcon#about to write, iclass 11, count 0 2006.257.04:57:39.69#ibcon#wrote, iclass 11, count 0 2006.257.04:57:39.69#ibcon#about to read 3, iclass 11, count 0 2006.257.04:57:39.72#ibcon#read 3, iclass 11, count 0 2006.257.04:57:39.72#ibcon#about to read 4, iclass 11, count 0 2006.257.04:57:39.72#ibcon#read 4, iclass 11, count 0 2006.257.04:57:39.72#ibcon#about to read 5, iclass 11, count 0 2006.257.04:57:39.72#ibcon#read 5, iclass 11, count 0 2006.257.04:57:39.72#ibcon#about to read 6, iclass 11, count 0 2006.257.04:57:39.72#ibcon#read 6, iclass 11, count 0 2006.257.04:57:39.72#ibcon#end of sib2, iclass 11, count 0 2006.257.04:57:39.72#ibcon#*after write, iclass 11, count 0 2006.257.04:57:39.72#ibcon#*before return 0, iclass 11, count 0 2006.257.04:57:39.72#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:39.72#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:39.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.04:57:39.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.04:57:39.72$vck44/valo=4,624.99 2006.257.04:57:39.72#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.04:57:39.72#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.04:57:39.72#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:39.72#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:57:39.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:57:39.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:57:39.72#ibcon#enter wrdev, iclass 13, count 0 2006.257.04:57:39.72#ibcon#first serial, iclass 13, count 0 2006.257.04:57:39.72#ibcon#enter sib2, iclass 13, count 0 2006.257.04:57:39.72#ibcon#flushed, iclass 13, count 0 2006.257.04:57:39.72#ibcon#about to write, iclass 13, count 0 2006.257.04:57:39.72#ibcon#wrote, iclass 13, count 0 2006.257.04:57:39.72#ibcon#about to read 3, iclass 13, count 0 2006.257.04:57:39.74#ibcon#read 3, iclass 13, count 0 2006.257.04:57:39.74#ibcon#about to read 4, iclass 13, count 0 2006.257.04:57:39.74#ibcon#read 4, iclass 13, count 0 2006.257.04:57:39.74#ibcon#about to read 5, iclass 13, count 0 2006.257.04:57:39.74#ibcon#read 5, iclass 13, count 0 2006.257.04:57:39.74#ibcon#about to read 6, iclass 13, count 0 2006.257.04:57:39.74#ibcon#read 6, iclass 13, count 0 2006.257.04:57:39.74#ibcon#end of sib2, iclass 13, count 0 2006.257.04:57:39.74#ibcon#*mode == 0, iclass 13, count 0 2006.257.04:57:39.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.04:57:39.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.04:57:39.74#ibcon#*before write, iclass 13, count 0 2006.257.04:57:39.74#ibcon#enter sib2, iclass 13, count 0 2006.257.04:57:39.74#ibcon#flushed, iclass 13, count 0 2006.257.04:57:39.74#ibcon#about to write, iclass 13, count 0 2006.257.04:57:39.74#ibcon#wrote, iclass 13, count 0 2006.257.04:57:39.74#ibcon#about to read 3, iclass 13, count 0 2006.257.04:57:39.78#ibcon#read 3, iclass 13, count 0 2006.257.04:57:39.78#ibcon#about to read 4, iclass 13, count 0 2006.257.04:57:39.78#ibcon#read 4, iclass 13, count 0 2006.257.04:57:39.78#ibcon#about to read 5, iclass 13, count 0 2006.257.04:57:39.78#ibcon#read 5, iclass 13, count 0 2006.257.04:57:39.78#ibcon#about to read 6, iclass 13, count 0 2006.257.04:57:39.78#ibcon#read 6, iclass 13, count 0 2006.257.04:57:39.78#ibcon#end of sib2, iclass 13, count 0 2006.257.04:57:39.78#ibcon#*after write, iclass 13, count 0 2006.257.04:57:39.78#ibcon#*before return 0, iclass 13, count 0 2006.257.04:57:39.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:57:39.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.04:57:39.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.04:57:39.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.04:57:39.78$vck44/va=4,7 2006.257.04:57:39.78#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.04:57:39.78#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.04:57:39.78#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:39.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:57:39.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:57:39.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:57:39.84#ibcon#enter wrdev, iclass 15, count 2 2006.257.04:57:39.84#ibcon#first serial, iclass 15, count 2 2006.257.04:57:39.84#ibcon#enter sib2, iclass 15, count 2 2006.257.04:57:39.84#ibcon#flushed, iclass 15, count 2 2006.257.04:57:39.84#ibcon#about to write, iclass 15, count 2 2006.257.04:57:39.84#ibcon#wrote, iclass 15, count 2 2006.257.04:57:39.84#ibcon#about to read 3, iclass 15, count 2 2006.257.04:57:39.86#ibcon#read 3, iclass 15, count 2 2006.257.04:57:39.86#ibcon#about to read 4, iclass 15, count 2 2006.257.04:57:39.86#ibcon#read 4, iclass 15, count 2 2006.257.04:57:39.86#ibcon#about to read 5, iclass 15, count 2 2006.257.04:57:39.86#ibcon#read 5, iclass 15, count 2 2006.257.04:57:39.86#ibcon#about to read 6, iclass 15, count 2 2006.257.04:57:39.86#ibcon#read 6, iclass 15, count 2 2006.257.04:57:39.86#ibcon#end of sib2, iclass 15, count 2 2006.257.04:57:39.86#ibcon#*mode == 0, iclass 15, count 2 2006.257.04:57:39.86#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.04:57:39.86#ibcon#[25=AT04-07\r\n] 2006.257.04:57:39.86#ibcon#*before write, iclass 15, count 2 2006.257.04:57:39.86#ibcon#enter sib2, iclass 15, count 2 2006.257.04:57:39.86#ibcon#flushed, iclass 15, count 2 2006.257.04:57:39.86#ibcon#about to write, iclass 15, count 2 2006.257.04:57:39.86#ibcon#wrote, iclass 15, count 2 2006.257.04:57:39.86#ibcon#about to read 3, iclass 15, count 2 2006.257.04:57:39.89#ibcon#read 3, iclass 15, count 2 2006.257.04:57:39.89#ibcon#about to read 4, iclass 15, count 2 2006.257.04:57:39.89#ibcon#read 4, iclass 15, count 2 2006.257.04:57:39.89#ibcon#about to read 5, iclass 15, count 2 2006.257.04:57:39.89#ibcon#read 5, iclass 15, count 2 2006.257.04:57:39.89#ibcon#about to read 6, iclass 15, count 2 2006.257.04:57:39.89#ibcon#read 6, iclass 15, count 2 2006.257.04:57:39.89#ibcon#end of sib2, iclass 15, count 2 2006.257.04:57:39.89#ibcon#*after write, iclass 15, count 2 2006.257.04:57:39.89#ibcon#*before return 0, iclass 15, count 2 2006.257.04:57:39.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:57:39.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.04:57:39.89#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.04:57:39.89#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:39.89#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:57:40.01#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:57:40.01#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:57:40.01#ibcon#enter wrdev, iclass 15, count 0 2006.257.04:57:40.01#ibcon#first serial, iclass 15, count 0 2006.257.04:57:40.01#ibcon#enter sib2, iclass 15, count 0 2006.257.04:57:40.01#ibcon#flushed, iclass 15, count 0 2006.257.04:57:40.01#ibcon#about to write, iclass 15, count 0 2006.257.04:57:40.01#ibcon#wrote, iclass 15, count 0 2006.257.04:57:40.01#ibcon#about to read 3, iclass 15, count 0 2006.257.04:57:40.03#ibcon#read 3, iclass 15, count 0 2006.257.04:57:40.03#ibcon#about to read 4, iclass 15, count 0 2006.257.04:57:40.03#ibcon#read 4, iclass 15, count 0 2006.257.04:57:40.03#ibcon#about to read 5, iclass 15, count 0 2006.257.04:57:40.03#ibcon#read 5, iclass 15, count 0 2006.257.04:57:40.03#ibcon#about to read 6, iclass 15, count 0 2006.257.04:57:40.03#ibcon#read 6, iclass 15, count 0 2006.257.04:57:40.03#ibcon#end of sib2, iclass 15, count 0 2006.257.04:57:40.03#ibcon#*mode == 0, iclass 15, count 0 2006.257.04:57:40.03#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.04:57:40.03#ibcon#[25=USB\r\n] 2006.257.04:57:40.03#ibcon#*before write, iclass 15, count 0 2006.257.04:57:40.03#ibcon#enter sib2, iclass 15, count 0 2006.257.04:57:40.03#ibcon#flushed, iclass 15, count 0 2006.257.04:57:40.03#ibcon#about to write, iclass 15, count 0 2006.257.04:57:40.03#ibcon#wrote, iclass 15, count 0 2006.257.04:57:40.03#ibcon#about to read 3, iclass 15, count 0 2006.257.04:57:40.06#ibcon#read 3, iclass 15, count 0 2006.257.04:57:40.06#ibcon#about to read 4, iclass 15, count 0 2006.257.04:57:40.06#ibcon#read 4, iclass 15, count 0 2006.257.04:57:40.06#ibcon#about to read 5, iclass 15, count 0 2006.257.04:57:40.06#ibcon#read 5, iclass 15, count 0 2006.257.04:57:40.06#ibcon#about to read 6, iclass 15, count 0 2006.257.04:57:40.06#ibcon#read 6, iclass 15, count 0 2006.257.04:57:40.06#ibcon#end of sib2, iclass 15, count 0 2006.257.04:57:40.06#ibcon#*after write, iclass 15, count 0 2006.257.04:57:40.06#ibcon#*before return 0, iclass 15, count 0 2006.257.04:57:40.06#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:57:40.06#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.04:57:40.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.04:57:40.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.04:57:40.06$vck44/valo=5,734.99 2006.257.04:57:40.06#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.04:57:40.06#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.04:57:40.06#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:40.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:40.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:40.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:40.06#ibcon#enter wrdev, iclass 17, count 0 2006.257.04:57:40.06#ibcon#first serial, iclass 17, count 0 2006.257.04:57:40.06#ibcon#enter sib2, iclass 17, count 0 2006.257.04:57:40.06#ibcon#flushed, iclass 17, count 0 2006.257.04:57:40.06#ibcon#about to write, iclass 17, count 0 2006.257.04:57:40.06#ibcon#wrote, iclass 17, count 0 2006.257.04:57:40.06#ibcon#about to read 3, iclass 17, count 0 2006.257.04:57:40.08#ibcon#read 3, iclass 17, count 0 2006.257.04:57:40.08#ibcon#about to read 4, iclass 17, count 0 2006.257.04:57:40.08#ibcon#read 4, iclass 17, count 0 2006.257.04:57:40.08#ibcon#about to read 5, iclass 17, count 0 2006.257.04:57:40.08#ibcon#read 5, iclass 17, count 0 2006.257.04:57:40.08#ibcon#about to read 6, iclass 17, count 0 2006.257.04:57:40.08#ibcon#read 6, iclass 17, count 0 2006.257.04:57:40.08#ibcon#end of sib2, iclass 17, count 0 2006.257.04:57:40.08#ibcon#*mode == 0, iclass 17, count 0 2006.257.04:57:40.08#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.04:57:40.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.04:57:40.08#ibcon#*before write, iclass 17, count 0 2006.257.04:57:40.08#ibcon#enter sib2, iclass 17, count 0 2006.257.04:57:40.08#ibcon#flushed, iclass 17, count 0 2006.257.04:57:40.08#ibcon#about to write, iclass 17, count 0 2006.257.04:57:40.08#ibcon#wrote, iclass 17, count 0 2006.257.04:57:40.08#ibcon#about to read 3, iclass 17, count 0 2006.257.04:57:40.12#ibcon#read 3, iclass 17, count 0 2006.257.04:57:40.12#ibcon#about to read 4, iclass 17, count 0 2006.257.04:57:40.12#ibcon#read 4, iclass 17, count 0 2006.257.04:57:40.12#ibcon#about to read 5, iclass 17, count 0 2006.257.04:57:40.12#ibcon#read 5, iclass 17, count 0 2006.257.04:57:40.12#ibcon#about to read 6, iclass 17, count 0 2006.257.04:57:40.12#ibcon#read 6, iclass 17, count 0 2006.257.04:57:40.12#ibcon#end of sib2, iclass 17, count 0 2006.257.04:57:40.12#ibcon#*after write, iclass 17, count 0 2006.257.04:57:40.12#ibcon#*before return 0, iclass 17, count 0 2006.257.04:57:40.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:40.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:40.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.04:57:40.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.04:57:40.12$vck44/va=5,4 2006.257.04:57:40.12#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.04:57:40.12#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.04:57:40.12#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:40.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:40.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:40.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:40.18#ibcon#enter wrdev, iclass 19, count 2 2006.257.04:57:40.18#ibcon#first serial, iclass 19, count 2 2006.257.04:57:40.18#ibcon#enter sib2, iclass 19, count 2 2006.257.04:57:40.18#ibcon#flushed, iclass 19, count 2 2006.257.04:57:40.18#ibcon#about to write, iclass 19, count 2 2006.257.04:57:40.18#ibcon#wrote, iclass 19, count 2 2006.257.04:57:40.18#ibcon#about to read 3, iclass 19, count 2 2006.257.04:57:40.20#ibcon#read 3, iclass 19, count 2 2006.257.04:57:40.20#ibcon#about to read 4, iclass 19, count 2 2006.257.04:57:40.20#ibcon#read 4, iclass 19, count 2 2006.257.04:57:40.20#ibcon#about to read 5, iclass 19, count 2 2006.257.04:57:40.20#ibcon#read 5, iclass 19, count 2 2006.257.04:57:40.20#ibcon#about to read 6, iclass 19, count 2 2006.257.04:57:40.20#ibcon#read 6, iclass 19, count 2 2006.257.04:57:40.20#ibcon#end of sib2, iclass 19, count 2 2006.257.04:57:40.20#ibcon#*mode == 0, iclass 19, count 2 2006.257.04:57:40.20#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.04:57:40.20#ibcon#[25=AT05-04\r\n] 2006.257.04:57:40.20#ibcon#*before write, iclass 19, count 2 2006.257.04:57:40.20#ibcon#enter sib2, iclass 19, count 2 2006.257.04:57:40.20#ibcon#flushed, iclass 19, count 2 2006.257.04:57:40.20#ibcon#about to write, iclass 19, count 2 2006.257.04:57:40.20#ibcon#wrote, iclass 19, count 2 2006.257.04:57:40.20#ibcon#about to read 3, iclass 19, count 2 2006.257.04:57:40.23#ibcon#read 3, iclass 19, count 2 2006.257.04:57:40.23#ibcon#about to read 4, iclass 19, count 2 2006.257.04:57:40.23#ibcon#read 4, iclass 19, count 2 2006.257.04:57:40.23#ibcon#about to read 5, iclass 19, count 2 2006.257.04:57:40.23#ibcon#read 5, iclass 19, count 2 2006.257.04:57:40.23#ibcon#about to read 6, iclass 19, count 2 2006.257.04:57:40.23#ibcon#read 6, iclass 19, count 2 2006.257.04:57:40.23#ibcon#end of sib2, iclass 19, count 2 2006.257.04:57:40.23#ibcon#*after write, iclass 19, count 2 2006.257.04:57:40.23#ibcon#*before return 0, iclass 19, count 2 2006.257.04:57:40.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:40.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:40.23#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.04:57:40.23#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:40.23#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:40.35#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:40.35#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:40.35#ibcon#enter wrdev, iclass 19, count 0 2006.257.04:57:40.35#ibcon#first serial, iclass 19, count 0 2006.257.04:57:40.35#ibcon#enter sib2, iclass 19, count 0 2006.257.04:57:40.35#ibcon#flushed, iclass 19, count 0 2006.257.04:57:40.35#ibcon#about to write, iclass 19, count 0 2006.257.04:57:40.35#ibcon#wrote, iclass 19, count 0 2006.257.04:57:40.35#ibcon#about to read 3, iclass 19, count 0 2006.257.04:57:40.37#ibcon#read 3, iclass 19, count 0 2006.257.04:57:40.37#ibcon#about to read 4, iclass 19, count 0 2006.257.04:57:40.37#ibcon#read 4, iclass 19, count 0 2006.257.04:57:40.37#ibcon#about to read 5, iclass 19, count 0 2006.257.04:57:40.37#ibcon#read 5, iclass 19, count 0 2006.257.04:57:40.37#ibcon#about to read 6, iclass 19, count 0 2006.257.04:57:40.37#ibcon#read 6, iclass 19, count 0 2006.257.04:57:40.37#ibcon#end of sib2, iclass 19, count 0 2006.257.04:57:40.37#ibcon#*mode == 0, iclass 19, count 0 2006.257.04:57:40.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.04:57:40.37#ibcon#[25=USB\r\n] 2006.257.04:57:40.37#ibcon#*before write, iclass 19, count 0 2006.257.04:57:40.37#ibcon#enter sib2, iclass 19, count 0 2006.257.04:57:40.37#ibcon#flushed, iclass 19, count 0 2006.257.04:57:40.37#ibcon#about to write, iclass 19, count 0 2006.257.04:57:40.37#ibcon#wrote, iclass 19, count 0 2006.257.04:57:40.37#ibcon#about to read 3, iclass 19, count 0 2006.257.04:57:40.40#ibcon#read 3, iclass 19, count 0 2006.257.04:57:40.40#ibcon#about to read 4, iclass 19, count 0 2006.257.04:57:40.40#ibcon#read 4, iclass 19, count 0 2006.257.04:57:40.40#ibcon#about to read 5, iclass 19, count 0 2006.257.04:57:40.40#ibcon#read 5, iclass 19, count 0 2006.257.04:57:40.40#ibcon#about to read 6, iclass 19, count 0 2006.257.04:57:40.40#ibcon#read 6, iclass 19, count 0 2006.257.04:57:40.40#ibcon#end of sib2, iclass 19, count 0 2006.257.04:57:40.40#ibcon#*after write, iclass 19, count 0 2006.257.04:57:40.40#ibcon#*before return 0, iclass 19, count 0 2006.257.04:57:40.40#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:40.40#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:40.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.04:57:40.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.04:57:40.40$vck44/valo=6,814.99 2006.257.04:57:40.40#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.04:57:40.40#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.04:57:40.40#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:40.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:40.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:40.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:40.40#ibcon#enter wrdev, iclass 21, count 0 2006.257.04:57:40.40#ibcon#first serial, iclass 21, count 0 2006.257.04:57:40.40#ibcon#enter sib2, iclass 21, count 0 2006.257.04:57:40.40#ibcon#flushed, iclass 21, count 0 2006.257.04:57:40.40#ibcon#about to write, iclass 21, count 0 2006.257.04:57:40.40#ibcon#wrote, iclass 21, count 0 2006.257.04:57:40.40#ibcon#about to read 3, iclass 21, count 0 2006.257.04:57:40.42#ibcon#read 3, iclass 21, count 0 2006.257.04:57:40.42#ibcon#about to read 4, iclass 21, count 0 2006.257.04:57:40.42#ibcon#read 4, iclass 21, count 0 2006.257.04:57:40.42#ibcon#about to read 5, iclass 21, count 0 2006.257.04:57:40.42#ibcon#read 5, iclass 21, count 0 2006.257.04:57:40.42#ibcon#about to read 6, iclass 21, count 0 2006.257.04:57:40.42#ibcon#read 6, iclass 21, count 0 2006.257.04:57:40.42#ibcon#end of sib2, iclass 21, count 0 2006.257.04:57:40.42#ibcon#*mode == 0, iclass 21, count 0 2006.257.04:57:40.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.04:57:40.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.04:57:40.42#ibcon#*before write, iclass 21, count 0 2006.257.04:57:40.42#ibcon#enter sib2, iclass 21, count 0 2006.257.04:57:40.42#ibcon#flushed, iclass 21, count 0 2006.257.04:57:40.42#ibcon#about to write, iclass 21, count 0 2006.257.04:57:40.42#ibcon#wrote, iclass 21, count 0 2006.257.04:57:40.42#ibcon#about to read 3, iclass 21, count 0 2006.257.04:57:40.46#ibcon#read 3, iclass 21, count 0 2006.257.04:57:40.46#ibcon#about to read 4, iclass 21, count 0 2006.257.04:57:40.46#ibcon#read 4, iclass 21, count 0 2006.257.04:57:40.46#ibcon#about to read 5, iclass 21, count 0 2006.257.04:57:40.46#ibcon#read 5, iclass 21, count 0 2006.257.04:57:40.46#ibcon#about to read 6, iclass 21, count 0 2006.257.04:57:40.46#ibcon#read 6, iclass 21, count 0 2006.257.04:57:40.46#ibcon#end of sib2, iclass 21, count 0 2006.257.04:57:40.46#ibcon#*after write, iclass 21, count 0 2006.257.04:57:40.46#ibcon#*before return 0, iclass 21, count 0 2006.257.04:57:40.46#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:40.46#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:40.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.04:57:40.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.04:57:40.46$vck44/va=6,4 2006.257.04:57:40.46#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.04:57:40.46#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.04:57:40.46#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:40.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:40.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:40.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:40.52#ibcon#enter wrdev, iclass 23, count 2 2006.257.04:57:40.52#ibcon#first serial, iclass 23, count 2 2006.257.04:57:40.52#ibcon#enter sib2, iclass 23, count 2 2006.257.04:57:40.52#ibcon#flushed, iclass 23, count 2 2006.257.04:57:40.52#ibcon#about to write, iclass 23, count 2 2006.257.04:57:40.52#ibcon#wrote, iclass 23, count 2 2006.257.04:57:40.52#ibcon#about to read 3, iclass 23, count 2 2006.257.04:57:40.54#ibcon#read 3, iclass 23, count 2 2006.257.04:57:40.54#ibcon#about to read 4, iclass 23, count 2 2006.257.04:57:40.54#ibcon#read 4, iclass 23, count 2 2006.257.04:57:40.54#ibcon#about to read 5, iclass 23, count 2 2006.257.04:57:40.54#ibcon#read 5, iclass 23, count 2 2006.257.04:57:40.54#ibcon#about to read 6, iclass 23, count 2 2006.257.04:57:40.54#ibcon#read 6, iclass 23, count 2 2006.257.04:57:40.54#ibcon#end of sib2, iclass 23, count 2 2006.257.04:57:40.54#ibcon#*mode == 0, iclass 23, count 2 2006.257.04:57:40.54#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.04:57:40.54#ibcon#[25=AT06-04\r\n] 2006.257.04:57:40.54#ibcon#*before write, iclass 23, count 2 2006.257.04:57:40.54#ibcon#enter sib2, iclass 23, count 2 2006.257.04:57:40.54#ibcon#flushed, iclass 23, count 2 2006.257.04:57:40.54#ibcon#about to write, iclass 23, count 2 2006.257.04:57:40.54#ibcon#wrote, iclass 23, count 2 2006.257.04:57:40.54#ibcon#about to read 3, iclass 23, count 2 2006.257.04:57:40.57#ibcon#read 3, iclass 23, count 2 2006.257.04:57:40.57#ibcon#about to read 4, iclass 23, count 2 2006.257.04:57:40.57#ibcon#read 4, iclass 23, count 2 2006.257.04:57:40.57#ibcon#about to read 5, iclass 23, count 2 2006.257.04:57:40.57#ibcon#read 5, iclass 23, count 2 2006.257.04:57:40.57#ibcon#about to read 6, iclass 23, count 2 2006.257.04:57:40.57#ibcon#read 6, iclass 23, count 2 2006.257.04:57:40.57#ibcon#end of sib2, iclass 23, count 2 2006.257.04:57:40.57#ibcon#*after write, iclass 23, count 2 2006.257.04:57:40.57#ibcon#*before return 0, iclass 23, count 2 2006.257.04:57:40.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:40.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:40.57#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.04:57:40.57#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:40.57#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:40.69#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:40.69#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:40.69#ibcon#enter wrdev, iclass 23, count 0 2006.257.04:57:40.69#ibcon#first serial, iclass 23, count 0 2006.257.04:57:40.69#ibcon#enter sib2, iclass 23, count 0 2006.257.04:57:40.69#ibcon#flushed, iclass 23, count 0 2006.257.04:57:40.69#ibcon#about to write, iclass 23, count 0 2006.257.04:57:40.69#ibcon#wrote, iclass 23, count 0 2006.257.04:57:40.69#ibcon#about to read 3, iclass 23, count 0 2006.257.04:57:40.71#ibcon#read 3, iclass 23, count 0 2006.257.04:57:40.71#ibcon#about to read 4, iclass 23, count 0 2006.257.04:57:40.71#ibcon#read 4, iclass 23, count 0 2006.257.04:57:40.71#ibcon#about to read 5, iclass 23, count 0 2006.257.04:57:40.71#ibcon#read 5, iclass 23, count 0 2006.257.04:57:40.71#ibcon#about to read 6, iclass 23, count 0 2006.257.04:57:40.71#ibcon#read 6, iclass 23, count 0 2006.257.04:57:40.71#ibcon#end of sib2, iclass 23, count 0 2006.257.04:57:40.71#ibcon#*mode == 0, iclass 23, count 0 2006.257.04:57:40.71#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.04:57:40.71#ibcon#[25=USB\r\n] 2006.257.04:57:40.71#ibcon#*before write, iclass 23, count 0 2006.257.04:57:40.71#ibcon#enter sib2, iclass 23, count 0 2006.257.04:57:40.71#ibcon#flushed, iclass 23, count 0 2006.257.04:57:40.71#ibcon#about to write, iclass 23, count 0 2006.257.04:57:40.71#ibcon#wrote, iclass 23, count 0 2006.257.04:57:40.71#ibcon#about to read 3, iclass 23, count 0 2006.257.04:57:40.74#ibcon#read 3, iclass 23, count 0 2006.257.04:57:40.74#ibcon#about to read 4, iclass 23, count 0 2006.257.04:57:40.74#ibcon#read 4, iclass 23, count 0 2006.257.04:57:40.74#ibcon#about to read 5, iclass 23, count 0 2006.257.04:57:40.74#ibcon#read 5, iclass 23, count 0 2006.257.04:57:40.74#ibcon#about to read 6, iclass 23, count 0 2006.257.04:57:40.74#ibcon#read 6, iclass 23, count 0 2006.257.04:57:40.74#ibcon#end of sib2, iclass 23, count 0 2006.257.04:57:40.74#ibcon#*after write, iclass 23, count 0 2006.257.04:57:40.74#ibcon#*before return 0, iclass 23, count 0 2006.257.04:57:40.74#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:40.74#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:40.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.04:57:40.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.04:57:40.74$vck44/valo=7,864.99 2006.257.04:57:40.74#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.04:57:40.74#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.04:57:40.74#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:40.74#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:40.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:40.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:40.74#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:57:40.74#ibcon#first serial, iclass 25, count 0 2006.257.04:57:40.74#ibcon#enter sib2, iclass 25, count 0 2006.257.04:57:40.74#ibcon#flushed, iclass 25, count 0 2006.257.04:57:40.74#ibcon#about to write, iclass 25, count 0 2006.257.04:57:40.74#ibcon#wrote, iclass 25, count 0 2006.257.04:57:40.74#ibcon#about to read 3, iclass 25, count 0 2006.257.04:57:40.76#ibcon#read 3, iclass 25, count 0 2006.257.04:57:40.76#ibcon#about to read 4, iclass 25, count 0 2006.257.04:57:40.76#ibcon#read 4, iclass 25, count 0 2006.257.04:57:40.76#ibcon#about to read 5, iclass 25, count 0 2006.257.04:57:40.76#ibcon#read 5, iclass 25, count 0 2006.257.04:57:40.76#ibcon#about to read 6, iclass 25, count 0 2006.257.04:57:40.76#ibcon#read 6, iclass 25, count 0 2006.257.04:57:40.76#ibcon#end of sib2, iclass 25, count 0 2006.257.04:57:40.76#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:57:40.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:57:40.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.04:57:40.76#ibcon#*before write, iclass 25, count 0 2006.257.04:57:40.76#ibcon#enter sib2, iclass 25, count 0 2006.257.04:57:40.76#ibcon#flushed, iclass 25, count 0 2006.257.04:57:40.76#ibcon#about to write, iclass 25, count 0 2006.257.04:57:40.76#ibcon#wrote, iclass 25, count 0 2006.257.04:57:40.76#ibcon#about to read 3, iclass 25, count 0 2006.257.04:57:40.80#ibcon#read 3, iclass 25, count 0 2006.257.04:57:40.80#ibcon#about to read 4, iclass 25, count 0 2006.257.04:57:40.80#ibcon#read 4, iclass 25, count 0 2006.257.04:57:40.80#ibcon#about to read 5, iclass 25, count 0 2006.257.04:57:40.80#ibcon#read 5, iclass 25, count 0 2006.257.04:57:40.80#ibcon#about to read 6, iclass 25, count 0 2006.257.04:57:40.80#ibcon#read 6, iclass 25, count 0 2006.257.04:57:40.80#ibcon#end of sib2, iclass 25, count 0 2006.257.04:57:40.80#ibcon#*after write, iclass 25, count 0 2006.257.04:57:40.80#ibcon#*before return 0, iclass 25, count 0 2006.257.04:57:40.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:40.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:40.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:57:40.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:57:40.80$vck44/va=7,4 2006.257.04:57:40.80#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.04:57:40.80#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.04:57:40.80#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:40.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:40.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:40.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:40.86#ibcon#enter wrdev, iclass 27, count 2 2006.257.04:57:40.86#ibcon#first serial, iclass 27, count 2 2006.257.04:57:40.86#ibcon#enter sib2, iclass 27, count 2 2006.257.04:57:40.86#ibcon#flushed, iclass 27, count 2 2006.257.04:57:40.86#ibcon#about to write, iclass 27, count 2 2006.257.04:57:40.86#ibcon#wrote, iclass 27, count 2 2006.257.04:57:40.86#ibcon#about to read 3, iclass 27, count 2 2006.257.04:57:40.88#ibcon#read 3, iclass 27, count 2 2006.257.04:57:40.88#ibcon#about to read 4, iclass 27, count 2 2006.257.04:57:40.88#ibcon#read 4, iclass 27, count 2 2006.257.04:57:40.88#ibcon#about to read 5, iclass 27, count 2 2006.257.04:57:40.88#ibcon#read 5, iclass 27, count 2 2006.257.04:57:40.88#ibcon#about to read 6, iclass 27, count 2 2006.257.04:57:40.88#ibcon#read 6, iclass 27, count 2 2006.257.04:57:40.88#ibcon#end of sib2, iclass 27, count 2 2006.257.04:57:40.88#ibcon#*mode == 0, iclass 27, count 2 2006.257.04:57:40.88#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.04:57:40.88#ibcon#[25=AT07-04\r\n] 2006.257.04:57:40.88#ibcon#*before write, iclass 27, count 2 2006.257.04:57:40.88#ibcon#enter sib2, iclass 27, count 2 2006.257.04:57:40.88#ibcon#flushed, iclass 27, count 2 2006.257.04:57:40.88#ibcon#about to write, iclass 27, count 2 2006.257.04:57:40.88#ibcon#wrote, iclass 27, count 2 2006.257.04:57:40.88#ibcon#about to read 3, iclass 27, count 2 2006.257.04:57:40.91#ibcon#read 3, iclass 27, count 2 2006.257.04:57:40.91#ibcon#about to read 4, iclass 27, count 2 2006.257.04:57:40.91#ibcon#read 4, iclass 27, count 2 2006.257.04:57:40.91#ibcon#about to read 5, iclass 27, count 2 2006.257.04:57:40.91#ibcon#read 5, iclass 27, count 2 2006.257.04:57:40.91#ibcon#about to read 6, iclass 27, count 2 2006.257.04:57:40.91#ibcon#read 6, iclass 27, count 2 2006.257.04:57:40.91#ibcon#end of sib2, iclass 27, count 2 2006.257.04:57:40.91#ibcon#*after write, iclass 27, count 2 2006.257.04:57:40.91#ibcon#*before return 0, iclass 27, count 2 2006.257.04:57:40.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:40.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:40.91#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.04:57:40.91#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:40.91#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:41.03#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:41.03#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:41.03#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:57:41.03#ibcon#first serial, iclass 27, count 0 2006.257.04:57:41.03#ibcon#enter sib2, iclass 27, count 0 2006.257.04:57:41.03#ibcon#flushed, iclass 27, count 0 2006.257.04:57:41.03#ibcon#about to write, iclass 27, count 0 2006.257.04:57:41.03#ibcon#wrote, iclass 27, count 0 2006.257.04:57:41.03#ibcon#about to read 3, iclass 27, count 0 2006.257.04:57:41.05#ibcon#read 3, iclass 27, count 0 2006.257.04:57:41.05#ibcon#about to read 4, iclass 27, count 0 2006.257.04:57:41.05#ibcon#read 4, iclass 27, count 0 2006.257.04:57:41.05#ibcon#about to read 5, iclass 27, count 0 2006.257.04:57:41.05#ibcon#read 5, iclass 27, count 0 2006.257.04:57:41.05#ibcon#about to read 6, iclass 27, count 0 2006.257.04:57:41.05#ibcon#read 6, iclass 27, count 0 2006.257.04:57:41.05#ibcon#end of sib2, iclass 27, count 0 2006.257.04:57:41.05#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:57:41.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:57:41.05#ibcon#[25=USB\r\n] 2006.257.04:57:41.05#ibcon#*before write, iclass 27, count 0 2006.257.04:57:41.05#ibcon#enter sib2, iclass 27, count 0 2006.257.04:57:41.05#ibcon#flushed, iclass 27, count 0 2006.257.04:57:41.05#ibcon#about to write, iclass 27, count 0 2006.257.04:57:41.05#ibcon#wrote, iclass 27, count 0 2006.257.04:57:41.05#ibcon#about to read 3, iclass 27, count 0 2006.257.04:57:41.08#ibcon#read 3, iclass 27, count 0 2006.257.04:57:41.08#ibcon#about to read 4, iclass 27, count 0 2006.257.04:57:41.08#ibcon#read 4, iclass 27, count 0 2006.257.04:57:41.08#ibcon#about to read 5, iclass 27, count 0 2006.257.04:57:41.08#ibcon#read 5, iclass 27, count 0 2006.257.04:57:41.08#ibcon#about to read 6, iclass 27, count 0 2006.257.04:57:41.08#ibcon#read 6, iclass 27, count 0 2006.257.04:57:41.08#ibcon#end of sib2, iclass 27, count 0 2006.257.04:57:41.08#ibcon#*after write, iclass 27, count 0 2006.257.04:57:41.08#ibcon#*before return 0, iclass 27, count 0 2006.257.04:57:41.08#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:41.08#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:41.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:57:41.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:57:41.08$vck44/valo=8,884.99 2006.257.04:57:41.08#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.04:57:41.08#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.04:57:41.08#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:41.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:41.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:41.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:41.08#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:57:41.08#ibcon#first serial, iclass 29, count 0 2006.257.04:57:41.08#ibcon#enter sib2, iclass 29, count 0 2006.257.04:57:41.08#ibcon#flushed, iclass 29, count 0 2006.257.04:57:41.08#ibcon#about to write, iclass 29, count 0 2006.257.04:57:41.08#ibcon#wrote, iclass 29, count 0 2006.257.04:57:41.08#ibcon#about to read 3, iclass 29, count 0 2006.257.04:57:41.10#ibcon#read 3, iclass 29, count 0 2006.257.04:57:41.10#ibcon#about to read 4, iclass 29, count 0 2006.257.04:57:41.10#ibcon#read 4, iclass 29, count 0 2006.257.04:57:41.10#ibcon#about to read 5, iclass 29, count 0 2006.257.04:57:41.10#ibcon#read 5, iclass 29, count 0 2006.257.04:57:41.10#ibcon#about to read 6, iclass 29, count 0 2006.257.04:57:41.10#ibcon#read 6, iclass 29, count 0 2006.257.04:57:41.10#ibcon#end of sib2, iclass 29, count 0 2006.257.04:57:41.10#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:57:41.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:57:41.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.04:57:41.10#ibcon#*before write, iclass 29, count 0 2006.257.04:57:41.10#ibcon#enter sib2, iclass 29, count 0 2006.257.04:57:41.10#ibcon#flushed, iclass 29, count 0 2006.257.04:57:41.10#ibcon#about to write, iclass 29, count 0 2006.257.04:57:41.10#ibcon#wrote, iclass 29, count 0 2006.257.04:57:41.10#ibcon#about to read 3, iclass 29, count 0 2006.257.04:57:41.14#ibcon#read 3, iclass 29, count 0 2006.257.04:57:41.14#ibcon#about to read 4, iclass 29, count 0 2006.257.04:57:41.14#ibcon#read 4, iclass 29, count 0 2006.257.04:57:41.14#ibcon#about to read 5, iclass 29, count 0 2006.257.04:57:41.14#ibcon#read 5, iclass 29, count 0 2006.257.04:57:41.14#ibcon#about to read 6, iclass 29, count 0 2006.257.04:57:41.14#ibcon#read 6, iclass 29, count 0 2006.257.04:57:41.14#ibcon#end of sib2, iclass 29, count 0 2006.257.04:57:41.14#ibcon#*after write, iclass 29, count 0 2006.257.04:57:41.14#ibcon#*before return 0, iclass 29, count 0 2006.257.04:57:41.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:41.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:41.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:57:41.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:57:41.14$vck44/va=8,4 2006.257.04:57:41.14#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.04:57:41.14#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.04:57:41.14#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:41.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:41.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:41.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:41.20#ibcon#enter wrdev, iclass 31, count 2 2006.257.04:57:41.20#ibcon#first serial, iclass 31, count 2 2006.257.04:57:41.20#ibcon#enter sib2, iclass 31, count 2 2006.257.04:57:41.20#ibcon#flushed, iclass 31, count 2 2006.257.04:57:41.20#ibcon#about to write, iclass 31, count 2 2006.257.04:57:41.20#ibcon#wrote, iclass 31, count 2 2006.257.04:57:41.20#ibcon#about to read 3, iclass 31, count 2 2006.257.04:57:41.22#ibcon#read 3, iclass 31, count 2 2006.257.04:57:41.22#ibcon#about to read 4, iclass 31, count 2 2006.257.04:57:41.22#ibcon#read 4, iclass 31, count 2 2006.257.04:57:41.22#ibcon#about to read 5, iclass 31, count 2 2006.257.04:57:41.22#ibcon#read 5, iclass 31, count 2 2006.257.04:57:41.22#ibcon#about to read 6, iclass 31, count 2 2006.257.04:57:41.22#ibcon#read 6, iclass 31, count 2 2006.257.04:57:41.22#ibcon#end of sib2, iclass 31, count 2 2006.257.04:57:41.22#ibcon#*mode == 0, iclass 31, count 2 2006.257.04:57:41.22#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.04:57:41.22#ibcon#[25=AT08-04\r\n] 2006.257.04:57:41.22#ibcon#*before write, iclass 31, count 2 2006.257.04:57:41.22#ibcon#enter sib2, iclass 31, count 2 2006.257.04:57:41.22#ibcon#flushed, iclass 31, count 2 2006.257.04:57:41.22#ibcon#about to write, iclass 31, count 2 2006.257.04:57:41.22#ibcon#wrote, iclass 31, count 2 2006.257.04:57:41.22#ibcon#about to read 3, iclass 31, count 2 2006.257.04:57:41.25#ibcon#read 3, iclass 31, count 2 2006.257.04:57:41.25#ibcon#about to read 4, iclass 31, count 2 2006.257.04:57:41.25#ibcon#read 4, iclass 31, count 2 2006.257.04:57:41.25#ibcon#about to read 5, iclass 31, count 2 2006.257.04:57:41.25#ibcon#read 5, iclass 31, count 2 2006.257.04:57:41.25#ibcon#about to read 6, iclass 31, count 2 2006.257.04:57:41.25#ibcon#read 6, iclass 31, count 2 2006.257.04:57:41.25#ibcon#end of sib2, iclass 31, count 2 2006.257.04:57:41.25#ibcon#*after write, iclass 31, count 2 2006.257.04:57:41.25#ibcon#*before return 0, iclass 31, count 2 2006.257.04:57:41.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:41.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:41.25#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.04:57:41.25#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:41.25#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:41.37#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:41.37#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:41.37#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:57:41.37#ibcon#first serial, iclass 31, count 0 2006.257.04:57:41.37#ibcon#enter sib2, iclass 31, count 0 2006.257.04:57:41.37#ibcon#flushed, iclass 31, count 0 2006.257.04:57:41.37#ibcon#about to write, iclass 31, count 0 2006.257.04:57:41.37#ibcon#wrote, iclass 31, count 0 2006.257.04:57:41.37#ibcon#about to read 3, iclass 31, count 0 2006.257.04:57:41.39#ibcon#read 3, iclass 31, count 0 2006.257.04:57:41.39#ibcon#about to read 4, iclass 31, count 0 2006.257.04:57:41.39#ibcon#read 4, iclass 31, count 0 2006.257.04:57:41.39#ibcon#about to read 5, iclass 31, count 0 2006.257.04:57:41.39#ibcon#read 5, iclass 31, count 0 2006.257.04:57:41.39#ibcon#about to read 6, iclass 31, count 0 2006.257.04:57:41.39#ibcon#read 6, iclass 31, count 0 2006.257.04:57:41.39#ibcon#end of sib2, iclass 31, count 0 2006.257.04:57:41.39#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:57:41.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:57:41.39#ibcon#[25=USB\r\n] 2006.257.04:57:41.39#ibcon#*before write, iclass 31, count 0 2006.257.04:57:41.39#ibcon#enter sib2, iclass 31, count 0 2006.257.04:57:41.39#ibcon#flushed, iclass 31, count 0 2006.257.04:57:41.39#ibcon#about to write, iclass 31, count 0 2006.257.04:57:41.39#ibcon#wrote, iclass 31, count 0 2006.257.04:57:41.39#ibcon#about to read 3, iclass 31, count 0 2006.257.04:57:41.42#ibcon#read 3, iclass 31, count 0 2006.257.04:57:41.42#ibcon#about to read 4, iclass 31, count 0 2006.257.04:57:41.42#ibcon#read 4, iclass 31, count 0 2006.257.04:57:41.42#ibcon#about to read 5, iclass 31, count 0 2006.257.04:57:41.42#ibcon#read 5, iclass 31, count 0 2006.257.04:57:41.42#ibcon#about to read 6, iclass 31, count 0 2006.257.04:57:41.42#ibcon#read 6, iclass 31, count 0 2006.257.04:57:41.42#ibcon#end of sib2, iclass 31, count 0 2006.257.04:57:41.42#ibcon#*after write, iclass 31, count 0 2006.257.04:57:41.42#ibcon#*before return 0, iclass 31, count 0 2006.257.04:57:41.42#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:41.42#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:41.42#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:57:41.42#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:57:41.42$vck44/vblo=1,629.99 2006.257.04:57:41.42#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.04:57:41.42#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.04:57:41.42#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:41.42#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:41.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:41.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:41.42#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:57:41.42#ibcon#first serial, iclass 33, count 0 2006.257.04:57:41.42#ibcon#enter sib2, iclass 33, count 0 2006.257.04:57:41.42#ibcon#flushed, iclass 33, count 0 2006.257.04:57:41.42#ibcon#about to write, iclass 33, count 0 2006.257.04:57:41.42#ibcon#wrote, iclass 33, count 0 2006.257.04:57:41.42#ibcon#about to read 3, iclass 33, count 0 2006.257.04:57:41.44#ibcon#read 3, iclass 33, count 0 2006.257.04:57:41.44#ibcon#about to read 4, iclass 33, count 0 2006.257.04:57:41.44#ibcon#read 4, iclass 33, count 0 2006.257.04:57:41.44#ibcon#about to read 5, iclass 33, count 0 2006.257.04:57:41.44#ibcon#read 5, iclass 33, count 0 2006.257.04:57:41.44#ibcon#about to read 6, iclass 33, count 0 2006.257.04:57:41.44#ibcon#read 6, iclass 33, count 0 2006.257.04:57:41.44#ibcon#end of sib2, iclass 33, count 0 2006.257.04:57:41.44#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:57:41.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:57:41.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.04:57:41.44#ibcon#*before write, iclass 33, count 0 2006.257.04:57:41.44#ibcon#enter sib2, iclass 33, count 0 2006.257.04:57:41.44#ibcon#flushed, iclass 33, count 0 2006.257.04:57:41.44#ibcon#about to write, iclass 33, count 0 2006.257.04:57:41.44#ibcon#wrote, iclass 33, count 0 2006.257.04:57:41.44#ibcon#about to read 3, iclass 33, count 0 2006.257.04:57:41.48#ibcon#read 3, iclass 33, count 0 2006.257.04:57:41.48#ibcon#about to read 4, iclass 33, count 0 2006.257.04:57:41.48#ibcon#read 4, iclass 33, count 0 2006.257.04:57:41.48#ibcon#about to read 5, iclass 33, count 0 2006.257.04:57:41.48#ibcon#read 5, iclass 33, count 0 2006.257.04:57:41.48#ibcon#about to read 6, iclass 33, count 0 2006.257.04:57:41.48#ibcon#read 6, iclass 33, count 0 2006.257.04:57:41.48#ibcon#end of sib2, iclass 33, count 0 2006.257.04:57:41.48#ibcon#*after write, iclass 33, count 0 2006.257.04:57:41.48#ibcon#*before return 0, iclass 33, count 0 2006.257.04:57:41.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:41.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:41.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:57:41.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:57:41.48$vck44/vb=1,4 2006.257.04:57:41.48#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.04:57:41.48#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.04:57:41.48#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:41.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:57:41.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:57:41.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:57:41.48#ibcon#enter wrdev, iclass 35, count 2 2006.257.04:57:41.48#ibcon#first serial, iclass 35, count 2 2006.257.04:57:41.48#ibcon#enter sib2, iclass 35, count 2 2006.257.04:57:41.48#ibcon#flushed, iclass 35, count 2 2006.257.04:57:41.48#ibcon#about to write, iclass 35, count 2 2006.257.04:57:41.48#ibcon#wrote, iclass 35, count 2 2006.257.04:57:41.48#ibcon#about to read 3, iclass 35, count 2 2006.257.04:57:41.50#ibcon#read 3, iclass 35, count 2 2006.257.04:57:41.50#ibcon#about to read 4, iclass 35, count 2 2006.257.04:57:41.50#ibcon#read 4, iclass 35, count 2 2006.257.04:57:41.50#ibcon#about to read 5, iclass 35, count 2 2006.257.04:57:41.50#ibcon#read 5, iclass 35, count 2 2006.257.04:57:41.50#ibcon#about to read 6, iclass 35, count 2 2006.257.04:57:41.50#ibcon#read 6, iclass 35, count 2 2006.257.04:57:41.50#ibcon#end of sib2, iclass 35, count 2 2006.257.04:57:41.50#ibcon#*mode == 0, iclass 35, count 2 2006.257.04:57:41.50#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.04:57:41.50#ibcon#[27=AT01-04\r\n] 2006.257.04:57:41.50#ibcon#*before write, iclass 35, count 2 2006.257.04:57:41.50#ibcon#enter sib2, iclass 35, count 2 2006.257.04:57:41.50#ibcon#flushed, iclass 35, count 2 2006.257.04:57:41.50#ibcon#about to write, iclass 35, count 2 2006.257.04:57:41.50#ibcon#wrote, iclass 35, count 2 2006.257.04:57:41.50#ibcon#about to read 3, iclass 35, count 2 2006.257.04:57:41.53#ibcon#read 3, iclass 35, count 2 2006.257.04:57:41.53#ibcon#about to read 4, iclass 35, count 2 2006.257.04:57:41.53#ibcon#read 4, iclass 35, count 2 2006.257.04:57:41.53#ibcon#about to read 5, iclass 35, count 2 2006.257.04:57:41.53#ibcon#read 5, iclass 35, count 2 2006.257.04:57:41.53#ibcon#about to read 6, iclass 35, count 2 2006.257.04:57:41.53#ibcon#read 6, iclass 35, count 2 2006.257.04:57:41.53#ibcon#end of sib2, iclass 35, count 2 2006.257.04:57:41.53#ibcon#*after write, iclass 35, count 2 2006.257.04:57:41.53#ibcon#*before return 0, iclass 35, count 2 2006.257.04:57:41.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:57:41.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.04:57:41.53#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.04:57:41.53#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:41.53#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:57:41.65#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:57:41.65#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:57:41.65#ibcon#enter wrdev, iclass 35, count 0 2006.257.04:57:41.65#ibcon#first serial, iclass 35, count 0 2006.257.04:57:41.65#ibcon#enter sib2, iclass 35, count 0 2006.257.04:57:41.65#ibcon#flushed, iclass 35, count 0 2006.257.04:57:41.65#ibcon#about to write, iclass 35, count 0 2006.257.04:57:41.65#ibcon#wrote, iclass 35, count 0 2006.257.04:57:41.65#ibcon#about to read 3, iclass 35, count 0 2006.257.04:57:41.67#ibcon#read 3, iclass 35, count 0 2006.257.04:57:41.67#ibcon#about to read 4, iclass 35, count 0 2006.257.04:57:41.67#ibcon#read 4, iclass 35, count 0 2006.257.04:57:41.67#ibcon#about to read 5, iclass 35, count 0 2006.257.04:57:41.67#ibcon#read 5, iclass 35, count 0 2006.257.04:57:41.67#ibcon#about to read 6, iclass 35, count 0 2006.257.04:57:41.67#ibcon#read 6, iclass 35, count 0 2006.257.04:57:41.67#ibcon#end of sib2, iclass 35, count 0 2006.257.04:57:41.67#ibcon#*mode == 0, iclass 35, count 0 2006.257.04:57:41.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.04:57:41.67#ibcon#[27=USB\r\n] 2006.257.04:57:41.67#ibcon#*before write, iclass 35, count 0 2006.257.04:57:41.67#ibcon#enter sib2, iclass 35, count 0 2006.257.04:57:41.67#ibcon#flushed, iclass 35, count 0 2006.257.04:57:41.67#ibcon#about to write, iclass 35, count 0 2006.257.04:57:41.67#ibcon#wrote, iclass 35, count 0 2006.257.04:57:41.67#ibcon#about to read 3, iclass 35, count 0 2006.257.04:57:41.70#ibcon#read 3, iclass 35, count 0 2006.257.04:57:41.70#ibcon#about to read 4, iclass 35, count 0 2006.257.04:57:41.70#ibcon#read 4, iclass 35, count 0 2006.257.04:57:41.70#ibcon#about to read 5, iclass 35, count 0 2006.257.04:57:41.70#ibcon#read 5, iclass 35, count 0 2006.257.04:57:41.70#ibcon#about to read 6, iclass 35, count 0 2006.257.04:57:41.70#ibcon#read 6, iclass 35, count 0 2006.257.04:57:41.70#ibcon#end of sib2, iclass 35, count 0 2006.257.04:57:41.70#ibcon#*after write, iclass 35, count 0 2006.257.04:57:41.70#ibcon#*before return 0, iclass 35, count 0 2006.257.04:57:41.70#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:57:41.70#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.04:57:41.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.04:57:41.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.04:57:41.70$vck44/vblo=2,634.99 2006.257.04:57:41.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.04:57:41.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.04:57:41.70#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:41.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:41.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:41.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:41.70#ibcon#enter wrdev, iclass 37, count 0 2006.257.04:57:41.70#ibcon#first serial, iclass 37, count 0 2006.257.04:57:41.70#ibcon#enter sib2, iclass 37, count 0 2006.257.04:57:41.70#ibcon#flushed, iclass 37, count 0 2006.257.04:57:41.70#ibcon#about to write, iclass 37, count 0 2006.257.04:57:41.70#ibcon#wrote, iclass 37, count 0 2006.257.04:57:41.70#ibcon#about to read 3, iclass 37, count 0 2006.257.04:57:41.72#ibcon#read 3, iclass 37, count 0 2006.257.04:57:41.72#ibcon#about to read 4, iclass 37, count 0 2006.257.04:57:41.72#ibcon#read 4, iclass 37, count 0 2006.257.04:57:41.72#ibcon#about to read 5, iclass 37, count 0 2006.257.04:57:41.72#ibcon#read 5, iclass 37, count 0 2006.257.04:57:41.72#ibcon#about to read 6, iclass 37, count 0 2006.257.04:57:41.72#ibcon#read 6, iclass 37, count 0 2006.257.04:57:41.72#ibcon#end of sib2, iclass 37, count 0 2006.257.04:57:41.72#ibcon#*mode == 0, iclass 37, count 0 2006.257.04:57:41.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.04:57:41.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.04:57:41.72#ibcon#*before write, iclass 37, count 0 2006.257.04:57:41.72#ibcon#enter sib2, iclass 37, count 0 2006.257.04:57:41.72#ibcon#flushed, iclass 37, count 0 2006.257.04:57:41.72#ibcon#about to write, iclass 37, count 0 2006.257.04:57:41.72#ibcon#wrote, iclass 37, count 0 2006.257.04:57:41.72#ibcon#about to read 3, iclass 37, count 0 2006.257.04:57:41.76#ibcon#read 3, iclass 37, count 0 2006.257.04:57:41.76#ibcon#about to read 4, iclass 37, count 0 2006.257.04:57:41.76#ibcon#read 4, iclass 37, count 0 2006.257.04:57:41.76#ibcon#about to read 5, iclass 37, count 0 2006.257.04:57:41.76#ibcon#read 5, iclass 37, count 0 2006.257.04:57:41.76#ibcon#about to read 6, iclass 37, count 0 2006.257.04:57:41.76#ibcon#read 6, iclass 37, count 0 2006.257.04:57:41.76#ibcon#end of sib2, iclass 37, count 0 2006.257.04:57:41.76#ibcon#*after write, iclass 37, count 0 2006.257.04:57:41.76#ibcon#*before return 0, iclass 37, count 0 2006.257.04:57:41.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:41.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.04:57:41.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.04:57:41.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.04:57:41.76$vck44/vb=2,5 2006.257.04:57:41.76#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.04:57:41.76#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.04:57:41.76#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:41.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:41.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:41.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:41.82#ibcon#enter wrdev, iclass 39, count 2 2006.257.04:57:41.82#ibcon#first serial, iclass 39, count 2 2006.257.04:57:41.82#ibcon#enter sib2, iclass 39, count 2 2006.257.04:57:41.82#ibcon#flushed, iclass 39, count 2 2006.257.04:57:41.82#ibcon#about to write, iclass 39, count 2 2006.257.04:57:41.82#ibcon#wrote, iclass 39, count 2 2006.257.04:57:41.82#ibcon#about to read 3, iclass 39, count 2 2006.257.04:57:41.84#ibcon#read 3, iclass 39, count 2 2006.257.04:57:41.84#ibcon#about to read 4, iclass 39, count 2 2006.257.04:57:41.84#ibcon#read 4, iclass 39, count 2 2006.257.04:57:41.84#ibcon#about to read 5, iclass 39, count 2 2006.257.04:57:41.84#ibcon#read 5, iclass 39, count 2 2006.257.04:57:41.84#ibcon#about to read 6, iclass 39, count 2 2006.257.04:57:41.84#ibcon#read 6, iclass 39, count 2 2006.257.04:57:41.84#ibcon#end of sib2, iclass 39, count 2 2006.257.04:57:41.84#ibcon#*mode == 0, iclass 39, count 2 2006.257.04:57:41.84#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.04:57:41.84#ibcon#[27=AT02-05\r\n] 2006.257.04:57:41.84#ibcon#*before write, iclass 39, count 2 2006.257.04:57:41.84#ibcon#enter sib2, iclass 39, count 2 2006.257.04:57:41.84#ibcon#flushed, iclass 39, count 2 2006.257.04:57:41.84#ibcon#about to write, iclass 39, count 2 2006.257.04:57:41.84#ibcon#wrote, iclass 39, count 2 2006.257.04:57:41.84#ibcon#about to read 3, iclass 39, count 2 2006.257.04:57:41.87#ibcon#read 3, iclass 39, count 2 2006.257.04:57:41.87#ibcon#about to read 4, iclass 39, count 2 2006.257.04:57:41.87#ibcon#read 4, iclass 39, count 2 2006.257.04:57:41.87#ibcon#about to read 5, iclass 39, count 2 2006.257.04:57:41.87#ibcon#read 5, iclass 39, count 2 2006.257.04:57:41.87#ibcon#about to read 6, iclass 39, count 2 2006.257.04:57:41.87#ibcon#read 6, iclass 39, count 2 2006.257.04:57:41.87#ibcon#end of sib2, iclass 39, count 2 2006.257.04:57:41.87#ibcon#*after write, iclass 39, count 2 2006.257.04:57:41.87#ibcon#*before return 0, iclass 39, count 2 2006.257.04:57:41.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:41.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.04:57:41.87#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.04:57:41.87#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:41.87#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:41.99#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:41.99#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:41.99#ibcon#enter wrdev, iclass 39, count 0 2006.257.04:57:41.99#ibcon#first serial, iclass 39, count 0 2006.257.04:57:41.99#ibcon#enter sib2, iclass 39, count 0 2006.257.04:57:41.99#ibcon#flushed, iclass 39, count 0 2006.257.04:57:41.99#ibcon#about to write, iclass 39, count 0 2006.257.04:57:41.99#ibcon#wrote, iclass 39, count 0 2006.257.04:57:41.99#ibcon#about to read 3, iclass 39, count 0 2006.257.04:57:42.01#ibcon#read 3, iclass 39, count 0 2006.257.04:57:42.01#ibcon#about to read 4, iclass 39, count 0 2006.257.04:57:42.01#ibcon#read 4, iclass 39, count 0 2006.257.04:57:42.01#ibcon#about to read 5, iclass 39, count 0 2006.257.04:57:42.01#ibcon#read 5, iclass 39, count 0 2006.257.04:57:42.01#ibcon#about to read 6, iclass 39, count 0 2006.257.04:57:42.01#ibcon#read 6, iclass 39, count 0 2006.257.04:57:42.01#ibcon#end of sib2, iclass 39, count 0 2006.257.04:57:42.01#ibcon#*mode == 0, iclass 39, count 0 2006.257.04:57:42.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.04:57:42.01#ibcon#[27=USB\r\n] 2006.257.04:57:42.01#ibcon#*before write, iclass 39, count 0 2006.257.04:57:42.01#ibcon#enter sib2, iclass 39, count 0 2006.257.04:57:42.01#ibcon#flushed, iclass 39, count 0 2006.257.04:57:42.01#ibcon#about to write, iclass 39, count 0 2006.257.04:57:42.01#ibcon#wrote, iclass 39, count 0 2006.257.04:57:42.01#ibcon#about to read 3, iclass 39, count 0 2006.257.04:57:42.04#ibcon#read 3, iclass 39, count 0 2006.257.04:57:42.04#ibcon#about to read 4, iclass 39, count 0 2006.257.04:57:42.04#ibcon#read 4, iclass 39, count 0 2006.257.04:57:42.04#ibcon#about to read 5, iclass 39, count 0 2006.257.04:57:42.04#ibcon#read 5, iclass 39, count 0 2006.257.04:57:42.04#ibcon#about to read 6, iclass 39, count 0 2006.257.04:57:42.04#ibcon#read 6, iclass 39, count 0 2006.257.04:57:42.04#ibcon#end of sib2, iclass 39, count 0 2006.257.04:57:42.04#ibcon#*after write, iclass 39, count 0 2006.257.04:57:42.04#ibcon#*before return 0, iclass 39, count 0 2006.257.04:57:42.04#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:42.04#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.04:57:42.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.04:57:42.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.04:57:42.04$vck44/vblo=3,649.99 2006.257.04:57:42.04#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.04:57:42.04#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.04:57:42.04#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:42.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:42.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:42.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:42.04#ibcon#enter wrdev, iclass 3, count 0 2006.257.04:57:42.04#ibcon#first serial, iclass 3, count 0 2006.257.04:57:42.04#ibcon#enter sib2, iclass 3, count 0 2006.257.04:57:42.04#ibcon#flushed, iclass 3, count 0 2006.257.04:57:42.04#ibcon#about to write, iclass 3, count 0 2006.257.04:57:42.04#ibcon#wrote, iclass 3, count 0 2006.257.04:57:42.04#ibcon#about to read 3, iclass 3, count 0 2006.257.04:57:42.06#ibcon#read 3, iclass 3, count 0 2006.257.04:57:42.06#ibcon#about to read 4, iclass 3, count 0 2006.257.04:57:42.06#ibcon#read 4, iclass 3, count 0 2006.257.04:57:42.06#ibcon#about to read 5, iclass 3, count 0 2006.257.04:57:42.06#ibcon#read 5, iclass 3, count 0 2006.257.04:57:42.06#ibcon#about to read 6, iclass 3, count 0 2006.257.04:57:42.06#ibcon#read 6, iclass 3, count 0 2006.257.04:57:42.06#ibcon#end of sib2, iclass 3, count 0 2006.257.04:57:42.06#ibcon#*mode == 0, iclass 3, count 0 2006.257.04:57:42.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.04:57:42.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.04:57:42.06#ibcon#*before write, iclass 3, count 0 2006.257.04:57:42.06#ibcon#enter sib2, iclass 3, count 0 2006.257.04:57:42.06#ibcon#flushed, iclass 3, count 0 2006.257.04:57:42.06#ibcon#about to write, iclass 3, count 0 2006.257.04:57:42.06#ibcon#wrote, iclass 3, count 0 2006.257.04:57:42.06#ibcon#about to read 3, iclass 3, count 0 2006.257.04:57:42.10#ibcon#read 3, iclass 3, count 0 2006.257.04:57:42.10#ibcon#about to read 4, iclass 3, count 0 2006.257.04:57:42.10#ibcon#read 4, iclass 3, count 0 2006.257.04:57:42.10#ibcon#about to read 5, iclass 3, count 0 2006.257.04:57:42.10#ibcon#read 5, iclass 3, count 0 2006.257.04:57:42.10#ibcon#about to read 6, iclass 3, count 0 2006.257.04:57:42.10#ibcon#read 6, iclass 3, count 0 2006.257.04:57:42.10#ibcon#end of sib2, iclass 3, count 0 2006.257.04:57:42.10#ibcon#*after write, iclass 3, count 0 2006.257.04:57:42.10#ibcon#*before return 0, iclass 3, count 0 2006.257.04:57:42.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:42.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.04:57:42.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.04:57:42.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.04:57:42.10$vck44/vb=3,4 2006.257.04:57:42.10#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.04:57:42.10#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.04:57:42.10#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:42.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:42.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:42.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:42.16#ibcon#enter wrdev, iclass 5, count 2 2006.257.04:57:42.16#ibcon#first serial, iclass 5, count 2 2006.257.04:57:42.16#ibcon#enter sib2, iclass 5, count 2 2006.257.04:57:42.16#ibcon#flushed, iclass 5, count 2 2006.257.04:57:42.16#ibcon#about to write, iclass 5, count 2 2006.257.04:57:42.16#ibcon#wrote, iclass 5, count 2 2006.257.04:57:42.16#ibcon#about to read 3, iclass 5, count 2 2006.257.04:57:42.18#ibcon#read 3, iclass 5, count 2 2006.257.04:57:42.18#ibcon#about to read 4, iclass 5, count 2 2006.257.04:57:42.18#ibcon#read 4, iclass 5, count 2 2006.257.04:57:42.18#ibcon#about to read 5, iclass 5, count 2 2006.257.04:57:42.18#ibcon#read 5, iclass 5, count 2 2006.257.04:57:42.18#ibcon#about to read 6, iclass 5, count 2 2006.257.04:57:42.18#ibcon#read 6, iclass 5, count 2 2006.257.04:57:42.18#ibcon#end of sib2, iclass 5, count 2 2006.257.04:57:42.18#ibcon#*mode == 0, iclass 5, count 2 2006.257.04:57:42.18#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.04:57:42.18#ibcon#[27=AT03-04\r\n] 2006.257.04:57:42.18#ibcon#*before write, iclass 5, count 2 2006.257.04:57:42.18#ibcon#enter sib2, iclass 5, count 2 2006.257.04:57:42.18#ibcon#flushed, iclass 5, count 2 2006.257.04:57:42.18#ibcon#about to write, iclass 5, count 2 2006.257.04:57:42.18#ibcon#wrote, iclass 5, count 2 2006.257.04:57:42.18#ibcon#about to read 3, iclass 5, count 2 2006.257.04:57:42.21#ibcon#read 3, iclass 5, count 2 2006.257.04:57:42.21#ibcon#about to read 4, iclass 5, count 2 2006.257.04:57:42.21#ibcon#read 4, iclass 5, count 2 2006.257.04:57:42.21#ibcon#about to read 5, iclass 5, count 2 2006.257.04:57:42.21#ibcon#read 5, iclass 5, count 2 2006.257.04:57:42.21#ibcon#about to read 6, iclass 5, count 2 2006.257.04:57:42.21#ibcon#read 6, iclass 5, count 2 2006.257.04:57:42.21#ibcon#end of sib2, iclass 5, count 2 2006.257.04:57:42.21#ibcon#*after write, iclass 5, count 2 2006.257.04:57:42.21#ibcon#*before return 0, iclass 5, count 2 2006.257.04:57:42.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:42.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.04:57:42.21#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.04:57:42.21#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:42.21#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:42.33#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:42.33#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:42.33#ibcon#enter wrdev, iclass 5, count 0 2006.257.04:57:42.33#ibcon#first serial, iclass 5, count 0 2006.257.04:57:42.33#ibcon#enter sib2, iclass 5, count 0 2006.257.04:57:42.33#ibcon#flushed, iclass 5, count 0 2006.257.04:57:42.33#ibcon#about to write, iclass 5, count 0 2006.257.04:57:42.33#ibcon#wrote, iclass 5, count 0 2006.257.04:57:42.33#ibcon#about to read 3, iclass 5, count 0 2006.257.04:57:42.35#ibcon#read 3, iclass 5, count 0 2006.257.04:57:42.35#ibcon#about to read 4, iclass 5, count 0 2006.257.04:57:42.35#ibcon#read 4, iclass 5, count 0 2006.257.04:57:42.35#ibcon#about to read 5, iclass 5, count 0 2006.257.04:57:42.35#ibcon#read 5, iclass 5, count 0 2006.257.04:57:42.35#ibcon#about to read 6, iclass 5, count 0 2006.257.04:57:42.35#ibcon#read 6, iclass 5, count 0 2006.257.04:57:42.35#ibcon#end of sib2, iclass 5, count 0 2006.257.04:57:42.35#ibcon#*mode == 0, iclass 5, count 0 2006.257.04:57:42.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.04:57:42.35#ibcon#[27=USB\r\n] 2006.257.04:57:42.35#ibcon#*before write, iclass 5, count 0 2006.257.04:57:42.35#ibcon#enter sib2, iclass 5, count 0 2006.257.04:57:42.35#ibcon#flushed, iclass 5, count 0 2006.257.04:57:42.35#ibcon#about to write, iclass 5, count 0 2006.257.04:57:42.35#ibcon#wrote, iclass 5, count 0 2006.257.04:57:42.35#ibcon#about to read 3, iclass 5, count 0 2006.257.04:57:42.38#ibcon#read 3, iclass 5, count 0 2006.257.04:57:42.38#ibcon#about to read 4, iclass 5, count 0 2006.257.04:57:42.38#ibcon#read 4, iclass 5, count 0 2006.257.04:57:42.38#ibcon#about to read 5, iclass 5, count 0 2006.257.04:57:42.38#ibcon#read 5, iclass 5, count 0 2006.257.04:57:42.38#ibcon#about to read 6, iclass 5, count 0 2006.257.04:57:42.38#ibcon#read 6, iclass 5, count 0 2006.257.04:57:42.38#ibcon#end of sib2, iclass 5, count 0 2006.257.04:57:42.38#ibcon#*after write, iclass 5, count 0 2006.257.04:57:42.38#ibcon#*before return 0, iclass 5, count 0 2006.257.04:57:42.38#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:42.38#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.04:57:42.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.04:57:42.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.04:57:42.38$vck44/vblo=4,679.99 2006.257.04:57:42.38#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.04:57:42.38#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.04:57:42.38#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:42.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:42.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:42.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:42.38#ibcon#enter wrdev, iclass 7, count 0 2006.257.04:57:42.38#ibcon#first serial, iclass 7, count 0 2006.257.04:57:42.38#ibcon#enter sib2, iclass 7, count 0 2006.257.04:57:42.38#ibcon#flushed, iclass 7, count 0 2006.257.04:57:42.38#ibcon#about to write, iclass 7, count 0 2006.257.04:57:42.38#ibcon#wrote, iclass 7, count 0 2006.257.04:57:42.38#ibcon#about to read 3, iclass 7, count 0 2006.257.04:57:42.40#ibcon#read 3, iclass 7, count 0 2006.257.04:57:42.40#ibcon#about to read 4, iclass 7, count 0 2006.257.04:57:42.40#ibcon#read 4, iclass 7, count 0 2006.257.04:57:42.40#ibcon#about to read 5, iclass 7, count 0 2006.257.04:57:42.40#ibcon#read 5, iclass 7, count 0 2006.257.04:57:42.40#ibcon#about to read 6, iclass 7, count 0 2006.257.04:57:42.40#ibcon#read 6, iclass 7, count 0 2006.257.04:57:42.40#ibcon#end of sib2, iclass 7, count 0 2006.257.04:57:42.40#ibcon#*mode == 0, iclass 7, count 0 2006.257.04:57:42.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.04:57:42.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.04:57:42.40#ibcon#*before write, iclass 7, count 0 2006.257.04:57:42.40#ibcon#enter sib2, iclass 7, count 0 2006.257.04:57:42.40#ibcon#flushed, iclass 7, count 0 2006.257.04:57:42.40#ibcon#about to write, iclass 7, count 0 2006.257.04:57:42.40#ibcon#wrote, iclass 7, count 0 2006.257.04:57:42.40#ibcon#about to read 3, iclass 7, count 0 2006.257.04:57:42.44#ibcon#read 3, iclass 7, count 0 2006.257.04:57:42.44#ibcon#about to read 4, iclass 7, count 0 2006.257.04:57:42.44#ibcon#read 4, iclass 7, count 0 2006.257.04:57:42.44#ibcon#about to read 5, iclass 7, count 0 2006.257.04:57:42.44#ibcon#read 5, iclass 7, count 0 2006.257.04:57:42.44#ibcon#about to read 6, iclass 7, count 0 2006.257.04:57:42.44#ibcon#read 6, iclass 7, count 0 2006.257.04:57:42.44#ibcon#end of sib2, iclass 7, count 0 2006.257.04:57:42.44#ibcon#*after write, iclass 7, count 0 2006.257.04:57:42.44#ibcon#*before return 0, iclass 7, count 0 2006.257.04:57:42.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:42.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.04:57:42.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.04:57:42.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.04:57:42.44$vck44/vb=4,5 2006.257.04:57:42.44#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.04:57:42.44#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.04:57:42.44#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:42.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:42.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:42.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:42.50#ibcon#enter wrdev, iclass 11, count 2 2006.257.04:57:42.50#ibcon#first serial, iclass 11, count 2 2006.257.04:57:42.50#ibcon#enter sib2, iclass 11, count 2 2006.257.04:57:42.50#ibcon#flushed, iclass 11, count 2 2006.257.04:57:42.50#ibcon#about to write, iclass 11, count 2 2006.257.04:57:42.50#ibcon#wrote, iclass 11, count 2 2006.257.04:57:42.50#ibcon#about to read 3, iclass 11, count 2 2006.257.04:57:42.52#ibcon#read 3, iclass 11, count 2 2006.257.04:57:42.52#ibcon#about to read 4, iclass 11, count 2 2006.257.04:57:42.52#ibcon#read 4, iclass 11, count 2 2006.257.04:57:42.52#ibcon#about to read 5, iclass 11, count 2 2006.257.04:57:42.52#ibcon#read 5, iclass 11, count 2 2006.257.04:57:42.52#ibcon#about to read 6, iclass 11, count 2 2006.257.04:57:42.52#ibcon#read 6, iclass 11, count 2 2006.257.04:57:42.52#ibcon#end of sib2, iclass 11, count 2 2006.257.04:57:42.52#ibcon#*mode == 0, iclass 11, count 2 2006.257.04:57:42.52#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.04:57:42.52#ibcon#[27=AT04-05\r\n] 2006.257.04:57:42.52#ibcon#*before write, iclass 11, count 2 2006.257.04:57:42.52#ibcon#enter sib2, iclass 11, count 2 2006.257.04:57:42.52#ibcon#flushed, iclass 11, count 2 2006.257.04:57:42.52#ibcon#about to write, iclass 11, count 2 2006.257.04:57:42.52#ibcon#wrote, iclass 11, count 2 2006.257.04:57:42.52#ibcon#about to read 3, iclass 11, count 2 2006.257.04:57:42.55#ibcon#read 3, iclass 11, count 2 2006.257.04:57:42.55#ibcon#about to read 4, iclass 11, count 2 2006.257.04:57:42.55#ibcon#read 4, iclass 11, count 2 2006.257.04:57:42.55#ibcon#about to read 5, iclass 11, count 2 2006.257.04:57:42.55#ibcon#read 5, iclass 11, count 2 2006.257.04:57:42.55#ibcon#about to read 6, iclass 11, count 2 2006.257.04:57:42.55#ibcon#read 6, iclass 11, count 2 2006.257.04:57:42.55#ibcon#end of sib2, iclass 11, count 2 2006.257.04:57:42.55#ibcon#*after write, iclass 11, count 2 2006.257.04:57:42.55#ibcon#*before return 0, iclass 11, count 2 2006.257.04:57:42.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:42.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.04:57:42.55#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.04:57:42.55#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:42.55#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:42.65#abcon#<5=/14 1.7 4.7 19.68 931011.9\r\n> 2006.257.04:57:42.67#abcon#{5=INTERFACE CLEAR} 2006.257.04:57:42.67#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:42.67#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:42.67#ibcon#enter wrdev, iclass 11, count 0 2006.257.04:57:42.67#ibcon#first serial, iclass 11, count 0 2006.257.04:57:42.67#ibcon#enter sib2, iclass 11, count 0 2006.257.04:57:42.67#ibcon#flushed, iclass 11, count 0 2006.257.04:57:42.67#ibcon#about to write, iclass 11, count 0 2006.257.04:57:42.67#ibcon#wrote, iclass 11, count 0 2006.257.04:57:42.67#ibcon#about to read 3, iclass 11, count 0 2006.257.04:57:42.69#ibcon#read 3, iclass 11, count 0 2006.257.04:57:42.69#ibcon#about to read 4, iclass 11, count 0 2006.257.04:57:42.69#ibcon#read 4, iclass 11, count 0 2006.257.04:57:42.69#ibcon#about to read 5, iclass 11, count 0 2006.257.04:57:42.69#ibcon#read 5, iclass 11, count 0 2006.257.04:57:42.69#ibcon#about to read 6, iclass 11, count 0 2006.257.04:57:42.69#ibcon#read 6, iclass 11, count 0 2006.257.04:57:42.69#ibcon#end of sib2, iclass 11, count 0 2006.257.04:57:42.69#ibcon#*mode == 0, iclass 11, count 0 2006.257.04:57:42.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.04:57:42.69#ibcon#[27=USB\r\n] 2006.257.04:57:42.69#ibcon#*before write, iclass 11, count 0 2006.257.04:57:42.69#ibcon#enter sib2, iclass 11, count 0 2006.257.04:57:42.69#ibcon#flushed, iclass 11, count 0 2006.257.04:57:42.69#ibcon#about to write, iclass 11, count 0 2006.257.04:57:42.69#ibcon#wrote, iclass 11, count 0 2006.257.04:57:42.69#ibcon#about to read 3, iclass 11, count 0 2006.257.04:57:42.72#ibcon#read 3, iclass 11, count 0 2006.257.04:57:42.72#ibcon#about to read 4, iclass 11, count 0 2006.257.04:57:42.72#ibcon#read 4, iclass 11, count 0 2006.257.04:57:42.72#ibcon#about to read 5, iclass 11, count 0 2006.257.04:57:42.72#ibcon#read 5, iclass 11, count 0 2006.257.04:57:42.72#ibcon#about to read 6, iclass 11, count 0 2006.257.04:57:42.72#ibcon#read 6, iclass 11, count 0 2006.257.04:57:42.72#ibcon#end of sib2, iclass 11, count 0 2006.257.04:57:42.72#ibcon#*after write, iclass 11, count 0 2006.257.04:57:42.72#ibcon#*before return 0, iclass 11, count 0 2006.257.04:57:42.72#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:42.72#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.04:57:42.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.04:57:42.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.04:57:42.72$vck44/vblo=5,709.99 2006.257.04:57:42.72#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.04:57:42.72#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.04:57:42.72#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:42.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:42.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:42.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:42.72#ibcon#enter wrdev, iclass 17, count 0 2006.257.04:57:42.72#ibcon#first serial, iclass 17, count 0 2006.257.04:57:42.72#ibcon#enter sib2, iclass 17, count 0 2006.257.04:57:42.72#ibcon#flushed, iclass 17, count 0 2006.257.04:57:42.72#ibcon#about to write, iclass 17, count 0 2006.257.04:57:42.72#ibcon#wrote, iclass 17, count 0 2006.257.04:57:42.72#ibcon#about to read 3, iclass 17, count 0 2006.257.04:57:42.73#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:57:42.74#ibcon#read 3, iclass 17, count 0 2006.257.04:57:42.74#ibcon#about to read 4, iclass 17, count 0 2006.257.04:57:42.74#ibcon#read 4, iclass 17, count 0 2006.257.04:57:42.74#ibcon#about to read 5, iclass 17, count 0 2006.257.04:57:42.74#ibcon#read 5, iclass 17, count 0 2006.257.04:57:42.74#ibcon#about to read 6, iclass 17, count 0 2006.257.04:57:42.74#ibcon#read 6, iclass 17, count 0 2006.257.04:57:42.74#ibcon#end of sib2, iclass 17, count 0 2006.257.04:57:42.74#ibcon#*mode == 0, iclass 17, count 0 2006.257.04:57:42.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.04:57:42.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.04:57:42.74#ibcon#*before write, iclass 17, count 0 2006.257.04:57:42.74#ibcon#enter sib2, iclass 17, count 0 2006.257.04:57:42.74#ibcon#flushed, iclass 17, count 0 2006.257.04:57:42.74#ibcon#about to write, iclass 17, count 0 2006.257.04:57:42.74#ibcon#wrote, iclass 17, count 0 2006.257.04:57:42.74#ibcon#about to read 3, iclass 17, count 0 2006.257.04:57:42.78#ibcon#read 3, iclass 17, count 0 2006.257.04:57:42.78#ibcon#about to read 4, iclass 17, count 0 2006.257.04:57:42.78#ibcon#read 4, iclass 17, count 0 2006.257.04:57:42.78#ibcon#about to read 5, iclass 17, count 0 2006.257.04:57:42.78#ibcon#read 5, iclass 17, count 0 2006.257.04:57:42.78#ibcon#about to read 6, iclass 17, count 0 2006.257.04:57:42.78#ibcon#read 6, iclass 17, count 0 2006.257.04:57:42.78#ibcon#end of sib2, iclass 17, count 0 2006.257.04:57:42.78#ibcon#*after write, iclass 17, count 0 2006.257.04:57:42.78#ibcon#*before return 0, iclass 17, count 0 2006.257.04:57:42.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:42.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.04:57:42.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.04:57:42.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.04:57:42.78$vck44/vb=5,4 2006.257.04:57:42.78#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.04:57:42.78#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.04:57:42.78#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:42.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:42.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:42.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:42.84#ibcon#enter wrdev, iclass 19, count 2 2006.257.04:57:42.84#ibcon#first serial, iclass 19, count 2 2006.257.04:57:42.84#ibcon#enter sib2, iclass 19, count 2 2006.257.04:57:42.84#ibcon#flushed, iclass 19, count 2 2006.257.04:57:42.84#ibcon#about to write, iclass 19, count 2 2006.257.04:57:42.84#ibcon#wrote, iclass 19, count 2 2006.257.04:57:42.84#ibcon#about to read 3, iclass 19, count 2 2006.257.04:57:42.86#ibcon#read 3, iclass 19, count 2 2006.257.04:57:42.86#ibcon#about to read 4, iclass 19, count 2 2006.257.04:57:42.86#ibcon#read 4, iclass 19, count 2 2006.257.04:57:42.86#ibcon#about to read 5, iclass 19, count 2 2006.257.04:57:42.86#ibcon#read 5, iclass 19, count 2 2006.257.04:57:42.86#ibcon#about to read 6, iclass 19, count 2 2006.257.04:57:42.86#ibcon#read 6, iclass 19, count 2 2006.257.04:57:42.86#ibcon#end of sib2, iclass 19, count 2 2006.257.04:57:42.86#ibcon#*mode == 0, iclass 19, count 2 2006.257.04:57:42.86#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.04:57:42.86#ibcon#[27=AT05-04\r\n] 2006.257.04:57:42.86#ibcon#*before write, iclass 19, count 2 2006.257.04:57:42.86#ibcon#enter sib2, iclass 19, count 2 2006.257.04:57:42.86#ibcon#flushed, iclass 19, count 2 2006.257.04:57:42.86#ibcon#about to write, iclass 19, count 2 2006.257.04:57:42.86#ibcon#wrote, iclass 19, count 2 2006.257.04:57:42.86#ibcon#about to read 3, iclass 19, count 2 2006.257.04:57:42.89#ibcon#read 3, iclass 19, count 2 2006.257.04:57:42.89#ibcon#about to read 4, iclass 19, count 2 2006.257.04:57:42.89#ibcon#read 4, iclass 19, count 2 2006.257.04:57:42.89#ibcon#about to read 5, iclass 19, count 2 2006.257.04:57:42.89#ibcon#read 5, iclass 19, count 2 2006.257.04:57:42.89#ibcon#about to read 6, iclass 19, count 2 2006.257.04:57:42.89#ibcon#read 6, iclass 19, count 2 2006.257.04:57:42.89#ibcon#end of sib2, iclass 19, count 2 2006.257.04:57:42.89#ibcon#*after write, iclass 19, count 2 2006.257.04:57:42.89#ibcon#*before return 0, iclass 19, count 2 2006.257.04:57:42.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:42.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.04:57:42.89#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.04:57:42.89#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:42.89#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:43.01#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:43.01#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:43.01#ibcon#enter wrdev, iclass 19, count 0 2006.257.04:57:43.01#ibcon#first serial, iclass 19, count 0 2006.257.04:57:43.01#ibcon#enter sib2, iclass 19, count 0 2006.257.04:57:43.01#ibcon#flushed, iclass 19, count 0 2006.257.04:57:43.01#ibcon#about to write, iclass 19, count 0 2006.257.04:57:43.01#ibcon#wrote, iclass 19, count 0 2006.257.04:57:43.01#ibcon#about to read 3, iclass 19, count 0 2006.257.04:57:43.03#ibcon#read 3, iclass 19, count 0 2006.257.04:57:43.03#ibcon#about to read 4, iclass 19, count 0 2006.257.04:57:43.03#ibcon#read 4, iclass 19, count 0 2006.257.04:57:43.03#ibcon#about to read 5, iclass 19, count 0 2006.257.04:57:43.03#ibcon#read 5, iclass 19, count 0 2006.257.04:57:43.03#ibcon#about to read 6, iclass 19, count 0 2006.257.04:57:43.03#ibcon#read 6, iclass 19, count 0 2006.257.04:57:43.03#ibcon#end of sib2, iclass 19, count 0 2006.257.04:57:43.03#ibcon#*mode == 0, iclass 19, count 0 2006.257.04:57:43.03#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.04:57:43.03#ibcon#[27=USB\r\n] 2006.257.04:57:43.03#ibcon#*before write, iclass 19, count 0 2006.257.04:57:43.03#ibcon#enter sib2, iclass 19, count 0 2006.257.04:57:43.03#ibcon#flushed, iclass 19, count 0 2006.257.04:57:43.03#ibcon#about to write, iclass 19, count 0 2006.257.04:57:43.03#ibcon#wrote, iclass 19, count 0 2006.257.04:57:43.03#ibcon#about to read 3, iclass 19, count 0 2006.257.04:57:43.06#ibcon#read 3, iclass 19, count 0 2006.257.04:57:43.06#ibcon#about to read 4, iclass 19, count 0 2006.257.04:57:43.06#ibcon#read 4, iclass 19, count 0 2006.257.04:57:43.06#ibcon#about to read 5, iclass 19, count 0 2006.257.04:57:43.06#ibcon#read 5, iclass 19, count 0 2006.257.04:57:43.06#ibcon#about to read 6, iclass 19, count 0 2006.257.04:57:43.06#ibcon#read 6, iclass 19, count 0 2006.257.04:57:43.06#ibcon#end of sib2, iclass 19, count 0 2006.257.04:57:43.06#ibcon#*after write, iclass 19, count 0 2006.257.04:57:43.06#ibcon#*before return 0, iclass 19, count 0 2006.257.04:57:43.06#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:43.06#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.04:57:43.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.04:57:43.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.04:57:43.06$vck44/vblo=6,719.99 2006.257.04:57:43.06#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.04:57:43.06#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.04:57:43.06#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:43.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:43.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:43.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:43.06#ibcon#enter wrdev, iclass 21, count 0 2006.257.04:57:43.06#ibcon#first serial, iclass 21, count 0 2006.257.04:57:43.06#ibcon#enter sib2, iclass 21, count 0 2006.257.04:57:43.06#ibcon#flushed, iclass 21, count 0 2006.257.04:57:43.06#ibcon#about to write, iclass 21, count 0 2006.257.04:57:43.06#ibcon#wrote, iclass 21, count 0 2006.257.04:57:43.06#ibcon#about to read 3, iclass 21, count 0 2006.257.04:57:43.08#ibcon#read 3, iclass 21, count 0 2006.257.04:57:43.08#ibcon#about to read 4, iclass 21, count 0 2006.257.04:57:43.08#ibcon#read 4, iclass 21, count 0 2006.257.04:57:43.08#ibcon#about to read 5, iclass 21, count 0 2006.257.04:57:43.08#ibcon#read 5, iclass 21, count 0 2006.257.04:57:43.08#ibcon#about to read 6, iclass 21, count 0 2006.257.04:57:43.08#ibcon#read 6, iclass 21, count 0 2006.257.04:57:43.08#ibcon#end of sib2, iclass 21, count 0 2006.257.04:57:43.08#ibcon#*mode == 0, iclass 21, count 0 2006.257.04:57:43.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.04:57:43.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.04:57:43.08#ibcon#*before write, iclass 21, count 0 2006.257.04:57:43.08#ibcon#enter sib2, iclass 21, count 0 2006.257.04:57:43.08#ibcon#flushed, iclass 21, count 0 2006.257.04:57:43.08#ibcon#about to write, iclass 21, count 0 2006.257.04:57:43.08#ibcon#wrote, iclass 21, count 0 2006.257.04:57:43.08#ibcon#about to read 3, iclass 21, count 0 2006.257.04:57:43.12#ibcon#read 3, iclass 21, count 0 2006.257.04:57:43.12#ibcon#about to read 4, iclass 21, count 0 2006.257.04:57:43.12#ibcon#read 4, iclass 21, count 0 2006.257.04:57:43.12#ibcon#about to read 5, iclass 21, count 0 2006.257.04:57:43.12#ibcon#read 5, iclass 21, count 0 2006.257.04:57:43.12#ibcon#about to read 6, iclass 21, count 0 2006.257.04:57:43.12#ibcon#read 6, iclass 21, count 0 2006.257.04:57:43.12#ibcon#end of sib2, iclass 21, count 0 2006.257.04:57:43.12#ibcon#*after write, iclass 21, count 0 2006.257.04:57:43.12#ibcon#*before return 0, iclass 21, count 0 2006.257.04:57:43.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:43.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.04:57:43.12#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.04:57:43.12#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.04:57:43.12$vck44/vb=6,4 2006.257.04:57:43.12#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.04:57:43.12#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.04:57:43.12#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:43.12#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:43.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:43.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:43.18#ibcon#enter wrdev, iclass 23, count 2 2006.257.04:57:43.18#ibcon#first serial, iclass 23, count 2 2006.257.04:57:43.18#ibcon#enter sib2, iclass 23, count 2 2006.257.04:57:43.18#ibcon#flushed, iclass 23, count 2 2006.257.04:57:43.18#ibcon#about to write, iclass 23, count 2 2006.257.04:57:43.18#ibcon#wrote, iclass 23, count 2 2006.257.04:57:43.18#ibcon#about to read 3, iclass 23, count 2 2006.257.04:57:43.20#ibcon#read 3, iclass 23, count 2 2006.257.04:57:43.20#ibcon#about to read 4, iclass 23, count 2 2006.257.04:57:43.20#ibcon#read 4, iclass 23, count 2 2006.257.04:57:43.20#ibcon#about to read 5, iclass 23, count 2 2006.257.04:57:43.20#ibcon#read 5, iclass 23, count 2 2006.257.04:57:43.20#ibcon#about to read 6, iclass 23, count 2 2006.257.04:57:43.20#ibcon#read 6, iclass 23, count 2 2006.257.04:57:43.20#ibcon#end of sib2, iclass 23, count 2 2006.257.04:57:43.20#ibcon#*mode == 0, iclass 23, count 2 2006.257.04:57:43.20#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.04:57:43.20#ibcon#[27=AT06-04\r\n] 2006.257.04:57:43.20#ibcon#*before write, iclass 23, count 2 2006.257.04:57:43.20#ibcon#enter sib2, iclass 23, count 2 2006.257.04:57:43.20#ibcon#flushed, iclass 23, count 2 2006.257.04:57:43.20#ibcon#about to write, iclass 23, count 2 2006.257.04:57:43.20#ibcon#wrote, iclass 23, count 2 2006.257.04:57:43.20#ibcon#about to read 3, iclass 23, count 2 2006.257.04:57:43.23#ibcon#read 3, iclass 23, count 2 2006.257.04:57:43.23#ibcon#about to read 4, iclass 23, count 2 2006.257.04:57:43.23#ibcon#read 4, iclass 23, count 2 2006.257.04:57:43.23#ibcon#about to read 5, iclass 23, count 2 2006.257.04:57:43.23#ibcon#read 5, iclass 23, count 2 2006.257.04:57:43.23#ibcon#about to read 6, iclass 23, count 2 2006.257.04:57:43.23#ibcon#read 6, iclass 23, count 2 2006.257.04:57:43.23#ibcon#end of sib2, iclass 23, count 2 2006.257.04:57:43.23#ibcon#*after write, iclass 23, count 2 2006.257.04:57:43.23#ibcon#*before return 0, iclass 23, count 2 2006.257.04:57:43.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:43.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.04:57:43.23#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.04:57:43.23#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:43.23#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:43.35#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:43.35#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:43.35#ibcon#enter wrdev, iclass 23, count 0 2006.257.04:57:43.35#ibcon#first serial, iclass 23, count 0 2006.257.04:57:43.35#ibcon#enter sib2, iclass 23, count 0 2006.257.04:57:43.35#ibcon#flushed, iclass 23, count 0 2006.257.04:57:43.35#ibcon#about to write, iclass 23, count 0 2006.257.04:57:43.35#ibcon#wrote, iclass 23, count 0 2006.257.04:57:43.35#ibcon#about to read 3, iclass 23, count 0 2006.257.04:57:43.37#ibcon#read 3, iclass 23, count 0 2006.257.04:57:43.37#ibcon#about to read 4, iclass 23, count 0 2006.257.04:57:43.37#ibcon#read 4, iclass 23, count 0 2006.257.04:57:43.37#ibcon#about to read 5, iclass 23, count 0 2006.257.04:57:43.37#ibcon#read 5, iclass 23, count 0 2006.257.04:57:43.37#ibcon#about to read 6, iclass 23, count 0 2006.257.04:57:43.37#ibcon#read 6, iclass 23, count 0 2006.257.04:57:43.37#ibcon#end of sib2, iclass 23, count 0 2006.257.04:57:43.37#ibcon#*mode == 0, iclass 23, count 0 2006.257.04:57:43.37#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.04:57:43.37#ibcon#[27=USB\r\n] 2006.257.04:57:43.37#ibcon#*before write, iclass 23, count 0 2006.257.04:57:43.37#ibcon#enter sib2, iclass 23, count 0 2006.257.04:57:43.37#ibcon#flushed, iclass 23, count 0 2006.257.04:57:43.37#ibcon#about to write, iclass 23, count 0 2006.257.04:57:43.37#ibcon#wrote, iclass 23, count 0 2006.257.04:57:43.37#ibcon#about to read 3, iclass 23, count 0 2006.257.04:57:43.40#ibcon#read 3, iclass 23, count 0 2006.257.04:57:43.40#ibcon#about to read 4, iclass 23, count 0 2006.257.04:57:43.40#ibcon#read 4, iclass 23, count 0 2006.257.04:57:43.40#ibcon#about to read 5, iclass 23, count 0 2006.257.04:57:43.40#ibcon#read 5, iclass 23, count 0 2006.257.04:57:43.40#ibcon#about to read 6, iclass 23, count 0 2006.257.04:57:43.40#ibcon#read 6, iclass 23, count 0 2006.257.04:57:43.40#ibcon#end of sib2, iclass 23, count 0 2006.257.04:57:43.40#ibcon#*after write, iclass 23, count 0 2006.257.04:57:43.40#ibcon#*before return 0, iclass 23, count 0 2006.257.04:57:43.40#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:43.40#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.04:57:43.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.04:57:43.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.04:57:43.40$vck44/vblo=7,734.99 2006.257.04:57:43.40#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.04:57:43.40#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.04:57:43.40#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:43.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:43.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:43.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:43.40#ibcon#enter wrdev, iclass 25, count 0 2006.257.04:57:43.40#ibcon#first serial, iclass 25, count 0 2006.257.04:57:43.40#ibcon#enter sib2, iclass 25, count 0 2006.257.04:57:43.40#ibcon#flushed, iclass 25, count 0 2006.257.04:57:43.40#ibcon#about to write, iclass 25, count 0 2006.257.04:57:43.40#ibcon#wrote, iclass 25, count 0 2006.257.04:57:43.40#ibcon#about to read 3, iclass 25, count 0 2006.257.04:57:43.42#ibcon#read 3, iclass 25, count 0 2006.257.04:57:43.42#ibcon#about to read 4, iclass 25, count 0 2006.257.04:57:43.42#ibcon#read 4, iclass 25, count 0 2006.257.04:57:43.42#ibcon#about to read 5, iclass 25, count 0 2006.257.04:57:43.42#ibcon#read 5, iclass 25, count 0 2006.257.04:57:43.42#ibcon#about to read 6, iclass 25, count 0 2006.257.04:57:43.42#ibcon#read 6, iclass 25, count 0 2006.257.04:57:43.42#ibcon#end of sib2, iclass 25, count 0 2006.257.04:57:43.42#ibcon#*mode == 0, iclass 25, count 0 2006.257.04:57:43.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.04:57:43.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.04:57:43.42#ibcon#*before write, iclass 25, count 0 2006.257.04:57:43.42#ibcon#enter sib2, iclass 25, count 0 2006.257.04:57:43.42#ibcon#flushed, iclass 25, count 0 2006.257.04:57:43.42#ibcon#about to write, iclass 25, count 0 2006.257.04:57:43.42#ibcon#wrote, iclass 25, count 0 2006.257.04:57:43.42#ibcon#about to read 3, iclass 25, count 0 2006.257.04:57:43.46#ibcon#read 3, iclass 25, count 0 2006.257.04:57:43.46#ibcon#about to read 4, iclass 25, count 0 2006.257.04:57:43.46#ibcon#read 4, iclass 25, count 0 2006.257.04:57:43.46#ibcon#about to read 5, iclass 25, count 0 2006.257.04:57:43.46#ibcon#read 5, iclass 25, count 0 2006.257.04:57:43.46#ibcon#about to read 6, iclass 25, count 0 2006.257.04:57:43.46#ibcon#read 6, iclass 25, count 0 2006.257.04:57:43.46#ibcon#end of sib2, iclass 25, count 0 2006.257.04:57:43.46#ibcon#*after write, iclass 25, count 0 2006.257.04:57:43.46#ibcon#*before return 0, iclass 25, count 0 2006.257.04:57:43.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:43.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.04:57:43.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.04:57:43.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.04:57:43.46$vck44/vb=7,4 2006.257.04:57:43.46#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.04:57:43.46#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.04:57:43.46#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:43.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:43.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:43.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:43.52#ibcon#enter wrdev, iclass 27, count 2 2006.257.04:57:43.52#ibcon#first serial, iclass 27, count 2 2006.257.04:57:43.52#ibcon#enter sib2, iclass 27, count 2 2006.257.04:57:43.52#ibcon#flushed, iclass 27, count 2 2006.257.04:57:43.52#ibcon#about to write, iclass 27, count 2 2006.257.04:57:43.52#ibcon#wrote, iclass 27, count 2 2006.257.04:57:43.52#ibcon#about to read 3, iclass 27, count 2 2006.257.04:57:43.54#ibcon#read 3, iclass 27, count 2 2006.257.04:57:43.54#ibcon#about to read 4, iclass 27, count 2 2006.257.04:57:43.54#ibcon#read 4, iclass 27, count 2 2006.257.04:57:43.54#ibcon#about to read 5, iclass 27, count 2 2006.257.04:57:43.54#ibcon#read 5, iclass 27, count 2 2006.257.04:57:43.54#ibcon#about to read 6, iclass 27, count 2 2006.257.04:57:43.54#ibcon#read 6, iclass 27, count 2 2006.257.04:57:43.54#ibcon#end of sib2, iclass 27, count 2 2006.257.04:57:43.54#ibcon#*mode == 0, iclass 27, count 2 2006.257.04:57:43.54#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.04:57:43.54#ibcon#[27=AT07-04\r\n] 2006.257.04:57:43.54#ibcon#*before write, iclass 27, count 2 2006.257.04:57:43.54#ibcon#enter sib2, iclass 27, count 2 2006.257.04:57:43.54#ibcon#flushed, iclass 27, count 2 2006.257.04:57:43.54#ibcon#about to write, iclass 27, count 2 2006.257.04:57:43.54#ibcon#wrote, iclass 27, count 2 2006.257.04:57:43.54#ibcon#about to read 3, iclass 27, count 2 2006.257.04:57:43.57#ibcon#read 3, iclass 27, count 2 2006.257.04:57:43.57#ibcon#about to read 4, iclass 27, count 2 2006.257.04:57:43.57#ibcon#read 4, iclass 27, count 2 2006.257.04:57:43.57#ibcon#about to read 5, iclass 27, count 2 2006.257.04:57:43.57#ibcon#read 5, iclass 27, count 2 2006.257.04:57:43.57#ibcon#about to read 6, iclass 27, count 2 2006.257.04:57:43.57#ibcon#read 6, iclass 27, count 2 2006.257.04:57:43.57#ibcon#end of sib2, iclass 27, count 2 2006.257.04:57:43.57#ibcon#*after write, iclass 27, count 2 2006.257.04:57:43.57#ibcon#*before return 0, iclass 27, count 2 2006.257.04:57:43.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:43.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.04:57:43.57#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.04:57:43.57#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:43.57#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:43.69#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:43.69#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:43.69#ibcon#enter wrdev, iclass 27, count 0 2006.257.04:57:43.69#ibcon#first serial, iclass 27, count 0 2006.257.04:57:43.69#ibcon#enter sib2, iclass 27, count 0 2006.257.04:57:43.69#ibcon#flushed, iclass 27, count 0 2006.257.04:57:43.69#ibcon#about to write, iclass 27, count 0 2006.257.04:57:43.69#ibcon#wrote, iclass 27, count 0 2006.257.04:57:43.69#ibcon#about to read 3, iclass 27, count 0 2006.257.04:57:43.71#ibcon#read 3, iclass 27, count 0 2006.257.04:57:43.71#ibcon#about to read 4, iclass 27, count 0 2006.257.04:57:43.71#ibcon#read 4, iclass 27, count 0 2006.257.04:57:43.71#ibcon#about to read 5, iclass 27, count 0 2006.257.04:57:43.71#ibcon#read 5, iclass 27, count 0 2006.257.04:57:43.71#ibcon#about to read 6, iclass 27, count 0 2006.257.04:57:43.71#ibcon#read 6, iclass 27, count 0 2006.257.04:57:43.71#ibcon#end of sib2, iclass 27, count 0 2006.257.04:57:43.71#ibcon#*mode == 0, iclass 27, count 0 2006.257.04:57:43.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.04:57:43.71#ibcon#[27=USB\r\n] 2006.257.04:57:43.71#ibcon#*before write, iclass 27, count 0 2006.257.04:57:43.71#ibcon#enter sib2, iclass 27, count 0 2006.257.04:57:43.71#ibcon#flushed, iclass 27, count 0 2006.257.04:57:43.71#ibcon#about to write, iclass 27, count 0 2006.257.04:57:43.71#ibcon#wrote, iclass 27, count 0 2006.257.04:57:43.71#ibcon#about to read 3, iclass 27, count 0 2006.257.04:57:43.74#ibcon#read 3, iclass 27, count 0 2006.257.04:57:43.74#ibcon#about to read 4, iclass 27, count 0 2006.257.04:57:43.74#ibcon#read 4, iclass 27, count 0 2006.257.04:57:43.74#ibcon#about to read 5, iclass 27, count 0 2006.257.04:57:43.74#ibcon#read 5, iclass 27, count 0 2006.257.04:57:43.74#ibcon#about to read 6, iclass 27, count 0 2006.257.04:57:43.74#ibcon#read 6, iclass 27, count 0 2006.257.04:57:43.74#ibcon#end of sib2, iclass 27, count 0 2006.257.04:57:43.74#ibcon#*after write, iclass 27, count 0 2006.257.04:57:43.74#ibcon#*before return 0, iclass 27, count 0 2006.257.04:57:43.74#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:43.74#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.04:57:43.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.04:57:43.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.04:57:43.74$vck44/vblo=8,744.99 2006.257.04:57:43.74#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.04:57:43.74#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.04:57:43.74#ibcon#ireg 17 cls_cnt 0 2006.257.04:57:43.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:43.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:43.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:43.74#ibcon#enter wrdev, iclass 29, count 0 2006.257.04:57:43.74#ibcon#first serial, iclass 29, count 0 2006.257.04:57:43.74#ibcon#enter sib2, iclass 29, count 0 2006.257.04:57:43.74#ibcon#flushed, iclass 29, count 0 2006.257.04:57:43.74#ibcon#about to write, iclass 29, count 0 2006.257.04:57:43.74#ibcon#wrote, iclass 29, count 0 2006.257.04:57:43.74#ibcon#about to read 3, iclass 29, count 0 2006.257.04:57:43.76#ibcon#read 3, iclass 29, count 0 2006.257.04:57:43.76#ibcon#about to read 4, iclass 29, count 0 2006.257.04:57:43.76#ibcon#read 4, iclass 29, count 0 2006.257.04:57:43.76#ibcon#about to read 5, iclass 29, count 0 2006.257.04:57:43.76#ibcon#read 5, iclass 29, count 0 2006.257.04:57:43.76#ibcon#about to read 6, iclass 29, count 0 2006.257.04:57:43.76#ibcon#read 6, iclass 29, count 0 2006.257.04:57:43.76#ibcon#end of sib2, iclass 29, count 0 2006.257.04:57:43.76#ibcon#*mode == 0, iclass 29, count 0 2006.257.04:57:43.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.04:57:43.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.04:57:43.76#ibcon#*before write, iclass 29, count 0 2006.257.04:57:43.76#ibcon#enter sib2, iclass 29, count 0 2006.257.04:57:43.76#ibcon#flushed, iclass 29, count 0 2006.257.04:57:43.76#ibcon#about to write, iclass 29, count 0 2006.257.04:57:43.76#ibcon#wrote, iclass 29, count 0 2006.257.04:57:43.76#ibcon#about to read 3, iclass 29, count 0 2006.257.04:57:43.80#ibcon#read 3, iclass 29, count 0 2006.257.04:57:43.80#ibcon#about to read 4, iclass 29, count 0 2006.257.04:57:43.80#ibcon#read 4, iclass 29, count 0 2006.257.04:57:43.80#ibcon#about to read 5, iclass 29, count 0 2006.257.04:57:43.80#ibcon#read 5, iclass 29, count 0 2006.257.04:57:43.80#ibcon#about to read 6, iclass 29, count 0 2006.257.04:57:43.80#ibcon#read 6, iclass 29, count 0 2006.257.04:57:43.80#ibcon#end of sib2, iclass 29, count 0 2006.257.04:57:43.80#ibcon#*after write, iclass 29, count 0 2006.257.04:57:43.80#ibcon#*before return 0, iclass 29, count 0 2006.257.04:57:43.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:43.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.04:57:43.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.04:57:43.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.04:57:43.80$vck44/vb=8,4 2006.257.04:57:43.80#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.04:57:43.80#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.04:57:43.80#ibcon#ireg 11 cls_cnt 2 2006.257.04:57:43.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:43.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:43.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:43.86#ibcon#enter wrdev, iclass 31, count 2 2006.257.04:57:43.86#ibcon#first serial, iclass 31, count 2 2006.257.04:57:43.86#ibcon#enter sib2, iclass 31, count 2 2006.257.04:57:43.86#ibcon#flushed, iclass 31, count 2 2006.257.04:57:43.86#ibcon#about to write, iclass 31, count 2 2006.257.04:57:43.86#ibcon#wrote, iclass 31, count 2 2006.257.04:57:43.86#ibcon#about to read 3, iclass 31, count 2 2006.257.04:57:43.88#ibcon#read 3, iclass 31, count 2 2006.257.04:57:43.88#ibcon#about to read 4, iclass 31, count 2 2006.257.04:57:43.88#ibcon#read 4, iclass 31, count 2 2006.257.04:57:43.88#ibcon#about to read 5, iclass 31, count 2 2006.257.04:57:43.88#ibcon#read 5, iclass 31, count 2 2006.257.04:57:43.88#ibcon#about to read 6, iclass 31, count 2 2006.257.04:57:43.88#ibcon#read 6, iclass 31, count 2 2006.257.04:57:43.88#ibcon#end of sib2, iclass 31, count 2 2006.257.04:57:43.88#ibcon#*mode == 0, iclass 31, count 2 2006.257.04:57:43.88#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.04:57:43.88#ibcon#[27=AT08-04\r\n] 2006.257.04:57:43.88#ibcon#*before write, iclass 31, count 2 2006.257.04:57:43.88#ibcon#enter sib2, iclass 31, count 2 2006.257.04:57:43.88#ibcon#flushed, iclass 31, count 2 2006.257.04:57:43.88#ibcon#about to write, iclass 31, count 2 2006.257.04:57:43.88#ibcon#wrote, iclass 31, count 2 2006.257.04:57:43.88#ibcon#about to read 3, iclass 31, count 2 2006.257.04:57:43.91#ibcon#read 3, iclass 31, count 2 2006.257.04:57:43.91#ibcon#about to read 4, iclass 31, count 2 2006.257.04:57:43.91#ibcon#read 4, iclass 31, count 2 2006.257.04:57:43.91#ibcon#about to read 5, iclass 31, count 2 2006.257.04:57:43.91#ibcon#read 5, iclass 31, count 2 2006.257.04:57:43.91#ibcon#about to read 6, iclass 31, count 2 2006.257.04:57:43.91#ibcon#read 6, iclass 31, count 2 2006.257.04:57:43.91#ibcon#end of sib2, iclass 31, count 2 2006.257.04:57:43.91#ibcon#*after write, iclass 31, count 2 2006.257.04:57:43.91#ibcon#*before return 0, iclass 31, count 2 2006.257.04:57:43.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:43.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.04:57:43.91#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.04:57:43.91#ibcon#ireg 7 cls_cnt 0 2006.257.04:57:43.91#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:44.03#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:44.03#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:44.03#ibcon#enter wrdev, iclass 31, count 0 2006.257.04:57:44.03#ibcon#first serial, iclass 31, count 0 2006.257.04:57:44.03#ibcon#enter sib2, iclass 31, count 0 2006.257.04:57:44.03#ibcon#flushed, iclass 31, count 0 2006.257.04:57:44.03#ibcon#about to write, iclass 31, count 0 2006.257.04:57:44.03#ibcon#wrote, iclass 31, count 0 2006.257.04:57:44.03#ibcon#about to read 3, iclass 31, count 0 2006.257.04:57:44.05#ibcon#read 3, iclass 31, count 0 2006.257.04:57:44.05#ibcon#about to read 4, iclass 31, count 0 2006.257.04:57:44.05#ibcon#read 4, iclass 31, count 0 2006.257.04:57:44.05#ibcon#about to read 5, iclass 31, count 0 2006.257.04:57:44.05#ibcon#read 5, iclass 31, count 0 2006.257.04:57:44.05#ibcon#about to read 6, iclass 31, count 0 2006.257.04:57:44.05#ibcon#read 6, iclass 31, count 0 2006.257.04:57:44.05#ibcon#end of sib2, iclass 31, count 0 2006.257.04:57:44.05#ibcon#*mode == 0, iclass 31, count 0 2006.257.04:57:44.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.04:57:44.05#ibcon#[27=USB\r\n] 2006.257.04:57:44.05#ibcon#*before write, iclass 31, count 0 2006.257.04:57:44.05#ibcon#enter sib2, iclass 31, count 0 2006.257.04:57:44.05#ibcon#flushed, iclass 31, count 0 2006.257.04:57:44.05#ibcon#about to write, iclass 31, count 0 2006.257.04:57:44.05#ibcon#wrote, iclass 31, count 0 2006.257.04:57:44.05#ibcon#about to read 3, iclass 31, count 0 2006.257.04:57:44.08#ibcon#read 3, iclass 31, count 0 2006.257.04:57:44.08#ibcon#about to read 4, iclass 31, count 0 2006.257.04:57:44.08#ibcon#read 4, iclass 31, count 0 2006.257.04:57:44.08#ibcon#about to read 5, iclass 31, count 0 2006.257.04:57:44.08#ibcon#read 5, iclass 31, count 0 2006.257.04:57:44.08#ibcon#about to read 6, iclass 31, count 0 2006.257.04:57:44.08#ibcon#read 6, iclass 31, count 0 2006.257.04:57:44.08#ibcon#end of sib2, iclass 31, count 0 2006.257.04:57:44.08#ibcon#*after write, iclass 31, count 0 2006.257.04:57:44.08#ibcon#*before return 0, iclass 31, count 0 2006.257.04:57:44.08#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:44.08#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.04:57:44.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.04:57:44.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.04:57:44.08$vck44/vabw=wide 2006.257.04:57:44.08#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.04:57:44.08#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.04:57:44.08#ibcon#ireg 8 cls_cnt 0 2006.257.04:57:44.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:44.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:44.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:44.08#ibcon#enter wrdev, iclass 33, count 0 2006.257.04:57:44.08#ibcon#first serial, iclass 33, count 0 2006.257.04:57:44.08#ibcon#enter sib2, iclass 33, count 0 2006.257.04:57:44.08#ibcon#flushed, iclass 33, count 0 2006.257.04:57:44.08#ibcon#about to write, iclass 33, count 0 2006.257.04:57:44.08#ibcon#wrote, iclass 33, count 0 2006.257.04:57:44.08#ibcon#about to read 3, iclass 33, count 0 2006.257.04:57:44.10#ibcon#read 3, iclass 33, count 0 2006.257.04:57:44.10#ibcon#about to read 4, iclass 33, count 0 2006.257.04:57:44.10#ibcon#read 4, iclass 33, count 0 2006.257.04:57:44.10#ibcon#about to read 5, iclass 33, count 0 2006.257.04:57:44.10#ibcon#read 5, iclass 33, count 0 2006.257.04:57:44.10#ibcon#about to read 6, iclass 33, count 0 2006.257.04:57:44.10#ibcon#read 6, iclass 33, count 0 2006.257.04:57:44.10#ibcon#end of sib2, iclass 33, count 0 2006.257.04:57:44.10#ibcon#*mode == 0, iclass 33, count 0 2006.257.04:57:44.10#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.04:57:44.10#ibcon#[25=BW32\r\n] 2006.257.04:57:44.10#ibcon#*before write, iclass 33, count 0 2006.257.04:57:44.10#ibcon#enter sib2, iclass 33, count 0 2006.257.04:57:44.10#ibcon#flushed, iclass 33, count 0 2006.257.04:57:44.10#ibcon#about to write, iclass 33, count 0 2006.257.04:57:44.10#ibcon#wrote, iclass 33, count 0 2006.257.04:57:44.10#ibcon#about to read 3, iclass 33, count 0 2006.257.04:57:44.13#ibcon#read 3, iclass 33, count 0 2006.257.04:57:44.13#ibcon#about to read 4, iclass 33, count 0 2006.257.04:57:44.13#ibcon#read 4, iclass 33, count 0 2006.257.04:57:44.13#ibcon#about to read 5, iclass 33, count 0 2006.257.04:57:44.13#ibcon#read 5, iclass 33, count 0 2006.257.04:57:44.13#ibcon#about to read 6, iclass 33, count 0 2006.257.04:57:44.13#ibcon#read 6, iclass 33, count 0 2006.257.04:57:44.13#ibcon#end of sib2, iclass 33, count 0 2006.257.04:57:44.13#ibcon#*after write, iclass 33, count 0 2006.257.04:57:44.13#ibcon#*before return 0, iclass 33, count 0 2006.257.04:57:44.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:44.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.04:57:44.13#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.04:57:44.13#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.04:57:44.13$vck44/vbbw=wide 2006.257.04:57:44.13#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.04:57:44.13#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.04:57:44.13#ibcon#ireg 8 cls_cnt 0 2006.257.04:57:44.13#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:57:44.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:57:44.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:57:44.20#ibcon#enter wrdev, iclass 35, count 0 2006.257.04:57:44.20#ibcon#first serial, iclass 35, count 0 2006.257.04:57:44.20#ibcon#enter sib2, iclass 35, count 0 2006.257.04:57:44.20#ibcon#flushed, iclass 35, count 0 2006.257.04:57:44.20#ibcon#about to write, iclass 35, count 0 2006.257.04:57:44.20#ibcon#wrote, iclass 35, count 0 2006.257.04:57:44.20#ibcon#about to read 3, iclass 35, count 0 2006.257.04:57:44.22#ibcon#read 3, iclass 35, count 0 2006.257.04:57:44.22#ibcon#about to read 4, iclass 35, count 0 2006.257.04:57:44.22#ibcon#read 4, iclass 35, count 0 2006.257.04:57:44.22#ibcon#about to read 5, iclass 35, count 0 2006.257.04:57:44.22#ibcon#read 5, iclass 35, count 0 2006.257.04:57:44.22#ibcon#about to read 6, iclass 35, count 0 2006.257.04:57:44.22#ibcon#read 6, iclass 35, count 0 2006.257.04:57:44.22#ibcon#end of sib2, iclass 35, count 0 2006.257.04:57:44.22#ibcon#*mode == 0, iclass 35, count 0 2006.257.04:57:44.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.04:57:44.22#ibcon#[27=BW32\r\n] 2006.257.04:57:44.22#ibcon#*before write, iclass 35, count 0 2006.257.04:57:44.22#ibcon#enter sib2, iclass 35, count 0 2006.257.04:57:44.22#ibcon#flushed, iclass 35, count 0 2006.257.04:57:44.22#ibcon#about to write, iclass 35, count 0 2006.257.04:57:44.22#ibcon#wrote, iclass 35, count 0 2006.257.04:57:44.22#ibcon#about to read 3, iclass 35, count 0 2006.257.04:57:44.25#ibcon#read 3, iclass 35, count 0 2006.257.04:57:44.25#ibcon#about to read 4, iclass 35, count 0 2006.257.04:57:44.25#ibcon#read 4, iclass 35, count 0 2006.257.04:57:44.25#ibcon#about to read 5, iclass 35, count 0 2006.257.04:57:44.25#ibcon#read 5, iclass 35, count 0 2006.257.04:57:44.25#ibcon#about to read 6, iclass 35, count 0 2006.257.04:57:44.25#ibcon#read 6, iclass 35, count 0 2006.257.04:57:44.25#ibcon#end of sib2, iclass 35, count 0 2006.257.04:57:44.25#ibcon#*after write, iclass 35, count 0 2006.257.04:57:44.25#ibcon#*before return 0, iclass 35, count 0 2006.257.04:57:44.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:57:44.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.04:57:44.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.04:57:44.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.04:57:44.25$setupk4/ifdk4 2006.257.04:57:44.25$ifdk4/lo= 2006.257.04:57:44.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.04:57:44.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.04:57:44.25$ifdk4/patch= 2006.257.04:57:44.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.04:57:44.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.04:57:44.26$setupk4/!*+20s 2006.257.04:57:52.82#abcon#<5=/15 1.7 4.7 19.68 931011.9\r\n> 2006.257.04:57:52.84#abcon#{5=INTERFACE CLEAR} 2006.257.04:57:52.90#abcon#[5=S1D000X0/0*\r\n] 2006.257.04:57:54.14#trakl#Source acquired 2006.257.04:57:54.14#flagr#flagr/antenna,acquired 2006.257.04:57:58.77$setupk4/"tpicd 2006.257.04:57:58.77$setupk4/echo=off 2006.257.04:57:58.77$setupk4/xlog=off 2006.257.04:57:58.77:!2006.257.05:00:24 2006.257.05:00:24.00:preob 2006.257.05:00:25.13/onsource/TRACKING 2006.257.05:00:25.13:!2006.257.05:00:34 2006.257.05:00:34.00:"tape 2006.257.05:00:34.00:"st=record 2006.257.05:00:34.00:data_valid=on 2006.257.05:00:34.00:midob 2006.257.05:00:34.13/onsource/TRACKING 2006.257.05:00:34.13/wx/19.68,1012.0,93 2006.257.05:00:34.32/cable/+6.4839E-03 2006.257.05:00:35.41/va/01,08,usb,yes,36,39 2006.257.05:00:35.41/va/02,07,usb,yes,39,39 2006.257.05:00:35.41/va/03,08,usb,yes,35,37 2006.257.05:00:35.41/va/04,07,usb,yes,40,42 2006.257.05:00:35.41/va/05,04,usb,yes,36,36 2006.257.05:00:35.41/va/06,04,usb,yes,40,40 2006.257.05:00:35.41/va/07,04,usb,yes,41,41 2006.257.05:00:35.41/va/08,04,usb,yes,34,42 2006.257.05:00:35.64/valo/01,524.99,yes,locked 2006.257.05:00:35.64/valo/02,534.99,yes,locked 2006.257.05:00:35.64/valo/03,564.99,yes,locked 2006.257.05:00:35.64/valo/04,624.99,yes,locked 2006.257.05:00:35.64/valo/05,734.99,yes,locked 2006.257.05:00:35.64/valo/06,814.99,yes,locked 2006.257.05:00:35.64/valo/07,864.99,yes,locked 2006.257.05:00:35.64/valo/08,884.99,yes,locked 2006.257.05:00:36.73/vb/01,04,usb,yes,33,30 2006.257.05:00:36.73/vb/02,05,usb,yes,31,31 2006.257.05:00:36.73/vb/03,04,usb,yes,32,35 2006.257.05:00:36.73/vb/04,05,usb,yes,32,31 2006.257.05:00:36.73/vb/05,04,usb,yes,28,31 2006.257.05:00:36.73/vb/06,04,usb,yes,33,29 2006.257.05:00:36.73/vb/07,04,usb,yes,33,33 2006.257.05:00:36.73/vb/08,04,usb,yes,30,34 2006.257.05:00:36.96/vblo/01,629.99,yes,locked 2006.257.05:00:36.96/vblo/02,634.99,yes,locked 2006.257.05:00:36.96/vblo/03,649.99,yes,locked 2006.257.05:00:36.96/vblo/04,679.99,yes,locked 2006.257.05:00:36.96/vblo/05,709.99,yes,locked 2006.257.05:00:36.96/vblo/06,719.99,yes,locked 2006.257.05:00:36.96/vblo/07,734.99,yes,locked 2006.257.05:00:36.96/vblo/08,744.99,yes,locked 2006.257.05:00:37.11/vabw/8 2006.257.05:00:37.26/vbbw/8 2006.257.05:00:37.35/xfe/off,on,16.7 2006.257.05:00:37.72/ifatt/23,28,28,28 2006.257.05:00:38.07/fmout-gps/S +4.58E-07 2006.257.05:00:38.11:!2006.257.05:01:14 2006.257.05:01:14.01:data_valid=off 2006.257.05:01:14.01:"et 2006.257.05:01:14.02:!+3s 2006.257.05:01:17.04:"tape 2006.257.05:01:17.04:postob 2006.257.05:01:17.12/cable/+6.4839E-03 2006.257.05:01:17.12/wx/19.68,1012.0,93 2006.257.05:01:17.18/fmout-gps/S +4.58E-07 2006.257.05:01:17.18:scan_name=257-0502,jd0609,210 2006.257.05:01:17.18:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.257.05:01:19.13#flagr#flagr/antenna,new-source 2006.257.05:01:19.13:checkk5 2006.257.05:01:19.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:01:19.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:01:20.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:01:20.96/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:01:21.35/chk_obsdata//k5ts1/T2570500??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:01:21.75/chk_obsdata//k5ts2/T2570500??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:01:22.17/chk_obsdata//k5ts3/T2570500??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:01:22.57/chk_obsdata//k5ts4/T2570500??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:01:23.29/k5log//k5ts1_log_newline 2006.257.05:01:23.99/k5log//k5ts2_log_newline 2006.257.05:01:24.73/k5log//k5ts3_log_newline 2006.257.05:01:25.45/k5log//k5ts4_log_newline 2006.257.05:01:25.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:01:25.47:setupk4=1 2006.257.05:01:25.47$setupk4/echo=on 2006.257.05:01:25.47$setupk4/pcalon 2006.257.05:01:25.47$pcalon/"no phase cal control is implemented here 2006.257.05:01:25.47$setupk4/"tpicd=stop 2006.257.05:01:25.47$setupk4/"rec=synch_on 2006.257.05:01:25.47$setupk4/"rec_mode=128 2006.257.05:01:25.47$setupk4/!* 2006.257.05:01:25.47$setupk4/recpk4 2006.257.05:01:25.47$recpk4/recpatch= 2006.257.05:01:25.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:01:25.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:01:25.48$setupk4/vck44 2006.257.05:01:25.48$vck44/valo=1,524.99 2006.257.05:01:25.48#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.05:01:25.48#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.05:01:25.48#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:25.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:25.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:25.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:25.48#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:01:25.48#ibcon#first serial, iclass 16, count 0 2006.257.05:01:25.48#ibcon#enter sib2, iclass 16, count 0 2006.257.05:01:25.48#ibcon#flushed, iclass 16, count 0 2006.257.05:01:25.48#ibcon#about to write, iclass 16, count 0 2006.257.05:01:25.48#ibcon#wrote, iclass 16, count 0 2006.257.05:01:25.48#ibcon#about to read 3, iclass 16, count 0 2006.257.05:01:25.49#ibcon#read 3, iclass 16, count 0 2006.257.05:01:25.49#ibcon#about to read 4, iclass 16, count 0 2006.257.05:01:25.49#ibcon#read 4, iclass 16, count 0 2006.257.05:01:25.49#ibcon#about to read 5, iclass 16, count 0 2006.257.05:01:25.49#ibcon#read 5, iclass 16, count 0 2006.257.05:01:25.49#ibcon#about to read 6, iclass 16, count 0 2006.257.05:01:25.49#ibcon#read 6, iclass 16, count 0 2006.257.05:01:25.49#ibcon#end of sib2, iclass 16, count 0 2006.257.05:01:25.49#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:01:25.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:01:25.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:01:25.49#ibcon#*before write, iclass 16, count 0 2006.257.05:01:25.49#ibcon#enter sib2, iclass 16, count 0 2006.257.05:01:25.49#ibcon#flushed, iclass 16, count 0 2006.257.05:01:25.49#ibcon#about to write, iclass 16, count 0 2006.257.05:01:25.49#ibcon#wrote, iclass 16, count 0 2006.257.05:01:25.49#ibcon#about to read 3, iclass 16, count 0 2006.257.05:01:25.54#ibcon#read 3, iclass 16, count 0 2006.257.05:01:25.54#ibcon#about to read 4, iclass 16, count 0 2006.257.05:01:25.54#ibcon#read 4, iclass 16, count 0 2006.257.05:01:25.54#ibcon#about to read 5, iclass 16, count 0 2006.257.05:01:25.54#ibcon#read 5, iclass 16, count 0 2006.257.05:01:25.54#ibcon#about to read 6, iclass 16, count 0 2006.257.05:01:25.54#ibcon#read 6, iclass 16, count 0 2006.257.05:01:25.54#ibcon#end of sib2, iclass 16, count 0 2006.257.05:01:25.54#ibcon#*after write, iclass 16, count 0 2006.257.05:01:25.54#ibcon#*before return 0, iclass 16, count 0 2006.257.05:01:25.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:25.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:25.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:01:25.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:01:25.54$vck44/va=1,8 2006.257.05:01:25.54#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.05:01:25.54#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.05:01:25.54#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:25.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:25.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:25.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:25.54#ibcon#enter wrdev, iclass 18, count 2 2006.257.05:01:25.54#ibcon#first serial, iclass 18, count 2 2006.257.05:01:25.54#ibcon#enter sib2, iclass 18, count 2 2006.257.05:01:25.54#ibcon#flushed, iclass 18, count 2 2006.257.05:01:25.54#ibcon#about to write, iclass 18, count 2 2006.257.05:01:25.54#ibcon#wrote, iclass 18, count 2 2006.257.05:01:25.54#ibcon#about to read 3, iclass 18, count 2 2006.257.05:01:25.56#ibcon#read 3, iclass 18, count 2 2006.257.05:01:25.56#ibcon#about to read 4, iclass 18, count 2 2006.257.05:01:25.56#ibcon#read 4, iclass 18, count 2 2006.257.05:01:25.56#ibcon#about to read 5, iclass 18, count 2 2006.257.05:01:25.56#ibcon#read 5, iclass 18, count 2 2006.257.05:01:25.56#ibcon#about to read 6, iclass 18, count 2 2006.257.05:01:25.56#ibcon#read 6, iclass 18, count 2 2006.257.05:01:25.56#ibcon#end of sib2, iclass 18, count 2 2006.257.05:01:25.56#ibcon#*mode == 0, iclass 18, count 2 2006.257.05:01:25.56#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.05:01:25.56#ibcon#[25=AT01-08\r\n] 2006.257.05:01:25.56#ibcon#*before write, iclass 18, count 2 2006.257.05:01:25.56#ibcon#enter sib2, iclass 18, count 2 2006.257.05:01:25.56#ibcon#flushed, iclass 18, count 2 2006.257.05:01:25.56#ibcon#about to write, iclass 18, count 2 2006.257.05:01:25.56#ibcon#wrote, iclass 18, count 2 2006.257.05:01:25.56#ibcon#about to read 3, iclass 18, count 2 2006.257.05:01:25.59#ibcon#read 3, iclass 18, count 2 2006.257.05:01:25.59#ibcon#about to read 4, iclass 18, count 2 2006.257.05:01:25.59#ibcon#read 4, iclass 18, count 2 2006.257.05:01:25.59#ibcon#about to read 5, iclass 18, count 2 2006.257.05:01:25.59#ibcon#read 5, iclass 18, count 2 2006.257.05:01:25.59#ibcon#about to read 6, iclass 18, count 2 2006.257.05:01:25.59#ibcon#read 6, iclass 18, count 2 2006.257.05:01:25.59#ibcon#end of sib2, iclass 18, count 2 2006.257.05:01:25.59#ibcon#*after write, iclass 18, count 2 2006.257.05:01:25.59#ibcon#*before return 0, iclass 18, count 2 2006.257.05:01:25.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:25.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:25.59#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.05:01:25.59#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:25.59#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:25.71#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:25.71#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:25.71#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:01:25.71#ibcon#first serial, iclass 18, count 0 2006.257.05:01:25.71#ibcon#enter sib2, iclass 18, count 0 2006.257.05:01:25.71#ibcon#flushed, iclass 18, count 0 2006.257.05:01:25.71#ibcon#about to write, iclass 18, count 0 2006.257.05:01:25.71#ibcon#wrote, iclass 18, count 0 2006.257.05:01:25.71#ibcon#about to read 3, iclass 18, count 0 2006.257.05:01:25.73#ibcon#read 3, iclass 18, count 0 2006.257.05:01:25.73#ibcon#about to read 4, iclass 18, count 0 2006.257.05:01:25.73#ibcon#read 4, iclass 18, count 0 2006.257.05:01:25.73#ibcon#about to read 5, iclass 18, count 0 2006.257.05:01:25.73#ibcon#read 5, iclass 18, count 0 2006.257.05:01:25.73#ibcon#about to read 6, iclass 18, count 0 2006.257.05:01:25.73#ibcon#read 6, iclass 18, count 0 2006.257.05:01:25.73#ibcon#end of sib2, iclass 18, count 0 2006.257.05:01:25.73#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:01:25.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:01:25.73#ibcon#[25=USB\r\n] 2006.257.05:01:25.73#ibcon#*before write, iclass 18, count 0 2006.257.05:01:25.73#ibcon#enter sib2, iclass 18, count 0 2006.257.05:01:25.73#ibcon#flushed, iclass 18, count 0 2006.257.05:01:25.73#ibcon#about to write, iclass 18, count 0 2006.257.05:01:25.73#ibcon#wrote, iclass 18, count 0 2006.257.05:01:25.73#ibcon#about to read 3, iclass 18, count 0 2006.257.05:01:25.76#ibcon#read 3, iclass 18, count 0 2006.257.05:01:25.76#ibcon#about to read 4, iclass 18, count 0 2006.257.05:01:25.76#ibcon#read 4, iclass 18, count 0 2006.257.05:01:25.76#ibcon#about to read 5, iclass 18, count 0 2006.257.05:01:25.76#ibcon#read 5, iclass 18, count 0 2006.257.05:01:25.76#ibcon#about to read 6, iclass 18, count 0 2006.257.05:01:25.76#ibcon#read 6, iclass 18, count 0 2006.257.05:01:25.76#ibcon#end of sib2, iclass 18, count 0 2006.257.05:01:25.76#ibcon#*after write, iclass 18, count 0 2006.257.05:01:25.76#ibcon#*before return 0, iclass 18, count 0 2006.257.05:01:25.76#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:25.76#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:25.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:01:25.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:01:25.76$vck44/valo=2,534.99 2006.257.05:01:25.76#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.05:01:25.76#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.05:01:25.76#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:25.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:25.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:25.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:25.76#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:01:25.76#ibcon#first serial, iclass 20, count 0 2006.257.05:01:25.76#ibcon#enter sib2, iclass 20, count 0 2006.257.05:01:25.76#ibcon#flushed, iclass 20, count 0 2006.257.05:01:25.76#ibcon#about to write, iclass 20, count 0 2006.257.05:01:25.76#ibcon#wrote, iclass 20, count 0 2006.257.05:01:25.76#ibcon#about to read 3, iclass 20, count 0 2006.257.05:01:25.78#ibcon#read 3, iclass 20, count 0 2006.257.05:01:25.78#ibcon#about to read 4, iclass 20, count 0 2006.257.05:01:25.78#ibcon#read 4, iclass 20, count 0 2006.257.05:01:25.78#ibcon#about to read 5, iclass 20, count 0 2006.257.05:01:25.78#ibcon#read 5, iclass 20, count 0 2006.257.05:01:25.78#ibcon#about to read 6, iclass 20, count 0 2006.257.05:01:25.78#ibcon#read 6, iclass 20, count 0 2006.257.05:01:25.78#ibcon#end of sib2, iclass 20, count 0 2006.257.05:01:25.78#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:01:25.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:01:25.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:01:25.78#ibcon#*before write, iclass 20, count 0 2006.257.05:01:25.78#ibcon#enter sib2, iclass 20, count 0 2006.257.05:01:25.78#ibcon#flushed, iclass 20, count 0 2006.257.05:01:25.78#ibcon#about to write, iclass 20, count 0 2006.257.05:01:25.78#ibcon#wrote, iclass 20, count 0 2006.257.05:01:25.78#ibcon#about to read 3, iclass 20, count 0 2006.257.05:01:25.82#ibcon#read 3, iclass 20, count 0 2006.257.05:01:25.82#ibcon#about to read 4, iclass 20, count 0 2006.257.05:01:25.82#ibcon#read 4, iclass 20, count 0 2006.257.05:01:25.82#ibcon#about to read 5, iclass 20, count 0 2006.257.05:01:25.82#ibcon#read 5, iclass 20, count 0 2006.257.05:01:25.82#ibcon#about to read 6, iclass 20, count 0 2006.257.05:01:25.82#ibcon#read 6, iclass 20, count 0 2006.257.05:01:25.82#ibcon#end of sib2, iclass 20, count 0 2006.257.05:01:25.82#ibcon#*after write, iclass 20, count 0 2006.257.05:01:25.82#ibcon#*before return 0, iclass 20, count 0 2006.257.05:01:25.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:25.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:25.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:01:25.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:01:25.82$vck44/va=2,7 2006.257.05:01:25.82#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.05:01:25.82#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.05:01:25.82#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:25.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:25.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:25.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:25.88#ibcon#enter wrdev, iclass 22, count 2 2006.257.05:01:25.88#ibcon#first serial, iclass 22, count 2 2006.257.05:01:25.88#ibcon#enter sib2, iclass 22, count 2 2006.257.05:01:25.88#ibcon#flushed, iclass 22, count 2 2006.257.05:01:25.88#ibcon#about to write, iclass 22, count 2 2006.257.05:01:25.88#ibcon#wrote, iclass 22, count 2 2006.257.05:01:25.88#ibcon#about to read 3, iclass 22, count 2 2006.257.05:01:25.90#ibcon#read 3, iclass 22, count 2 2006.257.05:01:25.90#ibcon#about to read 4, iclass 22, count 2 2006.257.05:01:25.90#ibcon#read 4, iclass 22, count 2 2006.257.05:01:25.90#ibcon#about to read 5, iclass 22, count 2 2006.257.05:01:25.90#ibcon#read 5, iclass 22, count 2 2006.257.05:01:25.90#ibcon#about to read 6, iclass 22, count 2 2006.257.05:01:25.90#ibcon#read 6, iclass 22, count 2 2006.257.05:01:25.90#ibcon#end of sib2, iclass 22, count 2 2006.257.05:01:25.90#ibcon#*mode == 0, iclass 22, count 2 2006.257.05:01:25.90#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.05:01:25.90#ibcon#[25=AT02-07\r\n] 2006.257.05:01:25.90#ibcon#*before write, iclass 22, count 2 2006.257.05:01:25.90#ibcon#enter sib2, iclass 22, count 2 2006.257.05:01:25.90#ibcon#flushed, iclass 22, count 2 2006.257.05:01:25.90#ibcon#about to write, iclass 22, count 2 2006.257.05:01:25.90#ibcon#wrote, iclass 22, count 2 2006.257.05:01:25.90#ibcon#about to read 3, iclass 22, count 2 2006.257.05:01:25.93#ibcon#read 3, iclass 22, count 2 2006.257.05:01:25.93#ibcon#about to read 4, iclass 22, count 2 2006.257.05:01:25.93#ibcon#read 4, iclass 22, count 2 2006.257.05:01:25.93#ibcon#about to read 5, iclass 22, count 2 2006.257.05:01:25.93#ibcon#read 5, iclass 22, count 2 2006.257.05:01:25.93#ibcon#about to read 6, iclass 22, count 2 2006.257.05:01:25.93#ibcon#read 6, iclass 22, count 2 2006.257.05:01:25.93#ibcon#end of sib2, iclass 22, count 2 2006.257.05:01:25.93#ibcon#*after write, iclass 22, count 2 2006.257.05:01:25.93#ibcon#*before return 0, iclass 22, count 2 2006.257.05:01:25.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:25.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:25.93#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.05:01:25.93#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:25.93#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:26.05#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:26.05#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:26.05#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:01:26.05#ibcon#first serial, iclass 22, count 0 2006.257.05:01:26.05#ibcon#enter sib2, iclass 22, count 0 2006.257.05:01:26.05#ibcon#flushed, iclass 22, count 0 2006.257.05:01:26.05#ibcon#about to write, iclass 22, count 0 2006.257.05:01:26.05#ibcon#wrote, iclass 22, count 0 2006.257.05:01:26.05#ibcon#about to read 3, iclass 22, count 0 2006.257.05:01:26.07#ibcon#read 3, iclass 22, count 0 2006.257.05:01:26.07#ibcon#about to read 4, iclass 22, count 0 2006.257.05:01:26.07#ibcon#read 4, iclass 22, count 0 2006.257.05:01:26.07#ibcon#about to read 5, iclass 22, count 0 2006.257.05:01:26.07#ibcon#read 5, iclass 22, count 0 2006.257.05:01:26.07#ibcon#about to read 6, iclass 22, count 0 2006.257.05:01:26.07#ibcon#read 6, iclass 22, count 0 2006.257.05:01:26.07#ibcon#end of sib2, iclass 22, count 0 2006.257.05:01:26.07#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:01:26.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:01:26.07#ibcon#[25=USB\r\n] 2006.257.05:01:26.07#ibcon#*before write, iclass 22, count 0 2006.257.05:01:26.07#ibcon#enter sib2, iclass 22, count 0 2006.257.05:01:26.07#ibcon#flushed, iclass 22, count 0 2006.257.05:01:26.07#ibcon#about to write, iclass 22, count 0 2006.257.05:01:26.07#ibcon#wrote, iclass 22, count 0 2006.257.05:01:26.07#ibcon#about to read 3, iclass 22, count 0 2006.257.05:01:26.10#ibcon#read 3, iclass 22, count 0 2006.257.05:01:26.10#ibcon#about to read 4, iclass 22, count 0 2006.257.05:01:26.10#ibcon#read 4, iclass 22, count 0 2006.257.05:01:26.10#ibcon#about to read 5, iclass 22, count 0 2006.257.05:01:26.10#ibcon#read 5, iclass 22, count 0 2006.257.05:01:26.10#ibcon#about to read 6, iclass 22, count 0 2006.257.05:01:26.10#ibcon#read 6, iclass 22, count 0 2006.257.05:01:26.10#ibcon#end of sib2, iclass 22, count 0 2006.257.05:01:26.10#ibcon#*after write, iclass 22, count 0 2006.257.05:01:26.10#ibcon#*before return 0, iclass 22, count 0 2006.257.05:01:26.10#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:26.10#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:26.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:01:26.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:01:26.10$vck44/valo=3,564.99 2006.257.05:01:26.10#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.05:01:26.10#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.05:01:26.10#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:26.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:26.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:26.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:26.10#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:01:26.10#ibcon#first serial, iclass 24, count 0 2006.257.05:01:26.10#ibcon#enter sib2, iclass 24, count 0 2006.257.05:01:26.10#ibcon#flushed, iclass 24, count 0 2006.257.05:01:26.10#ibcon#about to write, iclass 24, count 0 2006.257.05:01:26.10#ibcon#wrote, iclass 24, count 0 2006.257.05:01:26.10#ibcon#about to read 3, iclass 24, count 0 2006.257.05:01:26.12#ibcon#read 3, iclass 24, count 0 2006.257.05:01:26.12#ibcon#about to read 4, iclass 24, count 0 2006.257.05:01:26.12#ibcon#read 4, iclass 24, count 0 2006.257.05:01:26.12#ibcon#about to read 5, iclass 24, count 0 2006.257.05:01:26.12#ibcon#read 5, iclass 24, count 0 2006.257.05:01:26.12#ibcon#about to read 6, iclass 24, count 0 2006.257.05:01:26.12#ibcon#read 6, iclass 24, count 0 2006.257.05:01:26.12#ibcon#end of sib2, iclass 24, count 0 2006.257.05:01:26.12#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:01:26.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:01:26.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:01:26.12#ibcon#*before write, iclass 24, count 0 2006.257.05:01:26.12#ibcon#enter sib2, iclass 24, count 0 2006.257.05:01:26.12#ibcon#flushed, iclass 24, count 0 2006.257.05:01:26.12#ibcon#about to write, iclass 24, count 0 2006.257.05:01:26.12#ibcon#wrote, iclass 24, count 0 2006.257.05:01:26.12#ibcon#about to read 3, iclass 24, count 0 2006.257.05:01:26.16#ibcon#read 3, iclass 24, count 0 2006.257.05:01:26.16#ibcon#about to read 4, iclass 24, count 0 2006.257.05:01:26.16#ibcon#read 4, iclass 24, count 0 2006.257.05:01:26.16#ibcon#about to read 5, iclass 24, count 0 2006.257.05:01:26.16#ibcon#read 5, iclass 24, count 0 2006.257.05:01:26.16#ibcon#about to read 6, iclass 24, count 0 2006.257.05:01:26.16#ibcon#read 6, iclass 24, count 0 2006.257.05:01:26.16#ibcon#end of sib2, iclass 24, count 0 2006.257.05:01:26.16#ibcon#*after write, iclass 24, count 0 2006.257.05:01:26.16#ibcon#*before return 0, iclass 24, count 0 2006.257.05:01:26.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:26.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:26.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:01:26.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:01:26.16$vck44/va=3,8 2006.257.05:01:26.16#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.05:01:26.16#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.05:01:26.16#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:26.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:26.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:26.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:26.22#ibcon#enter wrdev, iclass 26, count 2 2006.257.05:01:26.22#ibcon#first serial, iclass 26, count 2 2006.257.05:01:26.22#ibcon#enter sib2, iclass 26, count 2 2006.257.05:01:26.22#ibcon#flushed, iclass 26, count 2 2006.257.05:01:26.22#ibcon#about to write, iclass 26, count 2 2006.257.05:01:26.22#ibcon#wrote, iclass 26, count 2 2006.257.05:01:26.22#ibcon#about to read 3, iclass 26, count 2 2006.257.05:01:26.24#ibcon#read 3, iclass 26, count 2 2006.257.05:01:26.24#ibcon#about to read 4, iclass 26, count 2 2006.257.05:01:26.24#ibcon#read 4, iclass 26, count 2 2006.257.05:01:26.24#ibcon#about to read 5, iclass 26, count 2 2006.257.05:01:26.24#ibcon#read 5, iclass 26, count 2 2006.257.05:01:26.24#ibcon#about to read 6, iclass 26, count 2 2006.257.05:01:26.24#ibcon#read 6, iclass 26, count 2 2006.257.05:01:26.24#ibcon#end of sib2, iclass 26, count 2 2006.257.05:01:26.24#ibcon#*mode == 0, iclass 26, count 2 2006.257.05:01:26.24#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.05:01:26.24#ibcon#[25=AT03-08\r\n] 2006.257.05:01:26.24#ibcon#*before write, iclass 26, count 2 2006.257.05:01:26.24#ibcon#enter sib2, iclass 26, count 2 2006.257.05:01:26.24#ibcon#flushed, iclass 26, count 2 2006.257.05:01:26.24#ibcon#about to write, iclass 26, count 2 2006.257.05:01:26.24#ibcon#wrote, iclass 26, count 2 2006.257.05:01:26.24#ibcon#about to read 3, iclass 26, count 2 2006.257.05:01:26.27#ibcon#read 3, iclass 26, count 2 2006.257.05:01:26.27#ibcon#about to read 4, iclass 26, count 2 2006.257.05:01:26.27#ibcon#read 4, iclass 26, count 2 2006.257.05:01:26.27#ibcon#about to read 5, iclass 26, count 2 2006.257.05:01:26.27#ibcon#read 5, iclass 26, count 2 2006.257.05:01:26.27#ibcon#about to read 6, iclass 26, count 2 2006.257.05:01:26.27#ibcon#read 6, iclass 26, count 2 2006.257.05:01:26.27#ibcon#end of sib2, iclass 26, count 2 2006.257.05:01:26.27#ibcon#*after write, iclass 26, count 2 2006.257.05:01:26.27#ibcon#*before return 0, iclass 26, count 2 2006.257.05:01:26.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:26.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:26.27#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.05:01:26.27#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:26.27#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:26.39#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:26.39#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:26.39#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:01:26.39#ibcon#first serial, iclass 26, count 0 2006.257.05:01:26.39#ibcon#enter sib2, iclass 26, count 0 2006.257.05:01:26.39#ibcon#flushed, iclass 26, count 0 2006.257.05:01:26.39#ibcon#about to write, iclass 26, count 0 2006.257.05:01:26.39#ibcon#wrote, iclass 26, count 0 2006.257.05:01:26.39#ibcon#about to read 3, iclass 26, count 0 2006.257.05:01:26.41#ibcon#read 3, iclass 26, count 0 2006.257.05:01:26.41#ibcon#about to read 4, iclass 26, count 0 2006.257.05:01:26.41#ibcon#read 4, iclass 26, count 0 2006.257.05:01:26.41#ibcon#about to read 5, iclass 26, count 0 2006.257.05:01:26.41#ibcon#read 5, iclass 26, count 0 2006.257.05:01:26.41#ibcon#about to read 6, iclass 26, count 0 2006.257.05:01:26.41#ibcon#read 6, iclass 26, count 0 2006.257.05:01:26.41#ibcon#end of sib2, iclass 26, count 0 2006.257.05:01:26.41#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:01:26.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:01:26.41#ibcon#[25=USB\r\n] 2006.257.05:01:26.41#ibcon#*before write, iclass 26, count 0 2006.257.05:01:26.41#ibcon#enter sib2, iclass 26, count 0 2006.257.05:01:26.41#ibcon#flushed, iclass 26, count 0 2006.257.05:01:26.41#ibcon#about to write, iclass 26, count 0 2006.257.05:01:26.41#ibcon#wrote, iclass 26, count 0 2006.257.05:01:26.41#ibcon#about to read 3, iclass 26, count 0 2006.257.05:01:26.44#ibcon#read 3, iclass 26, count 0 2006.257.05:01:26.44#ibcon#about to read 4, iclass 26, count 0 2006.257.05:01:26.44#ibcon#read 4, iclass 26, count 0 2006.257.05:01:26.44#ibcon#about to read 5, iclass 26, count 0 2006.257.05:01:26.44#ibcon#read 5, iclass 26, count 0 2006.257.05:01:26.44#ibcon#about to read 6, iclass 26, count 0 2006.257.05:01:26.44#ibcon#read 6, iclass 26, count 0 2006.257.05:01:26.44#ibcon#end of sib2, iclass 26, count 0 2006.257.05:01:26.44#ibcon#*after write, iclass 26, count 0 2006.257.05:01:26.44#ibcon#*before return 0, iclass 26, count 0 2006.257.05:01:26.44#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:26.44#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:26.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:01:26.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:01:26.44$vck44/valo=4,624.99 2006.257.05:01:26.44#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.05:01:26.44#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.05:01:26.44#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:26.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:26.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:26.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:26.44#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:01:26.44#ibcon#first serial, iclass 28, count 0 2006.257.05:01:26.44#ibcon#enter sib2, iclass 28, count 0 2006.257.05:01:26.44#ibcon#flushed, iclass 28, count 0 2006.257.05:01:26.44#ibcon#about to write, iclass 28, count 0 2006.257.05:01:26.44#ibcon#wrote, iclass 28, count 0 2006.257.05:01:26.44#ibcon#about to read 3, iclass 28, count 0 2006.257.05:01:26.46#ibcon#read 3, iclass 28, count 0 2006.257.05:01:26.46#ibcon#about to read 4, iclass 28, count 0 2006.257.05:01:26.46#ibcon#read 4, iclass 28, count 0 2006.257.05:01:26.46#ibcon#about to read 5, iclass 28, count 0 2006.257.05:01:26.46#ibcon#read 5, iclass 28, count 0 2006.257.05:01:26.46#ibcon#about to read 6, iclass 28, count 0 2006.257.05:01:26.46#ibcon#read 6, iclass 28, count 0 2006.257.05:01:26.46#ibcon#end of sib2, iclass 28, count 0 2006.257.05:01:26.46#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:01:26.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:01:26.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:01:26.46#ibcon#*before write, iclass 28, count 0 2006.257.05:01:26.46#ibcon#enter sib2, iclass 28, count 0 2006.257.05:01:26.46#ibcon#flushed, iclass 28, count 0 2006.257.05:01:26.46#ibcon#about to write, iclass 28, count 0 2006.257.05:01:26.46#ibcon#wrote, iclass 28, count 0 2006.257.05:01:26.46#ibcon#about to read 3, iclass 28, count 0 2006.257.05:01:26.50#ibcon#read 3, iclass 28, count 0 2006.257.05:01:26.50#ibcon#about to read 4, iclass 28, count 0 2006.257.05:01:26.50#ibcon#read 4, iclass 28, count 0 2006.257.05:01:26.50#ibcon#about to read 5, iclass 28, count 0 2006.257.05:01:26.50#ibcon#read 5, iclass 28, count 0 2006.257.05:01:26.50#ibcon#about to read 6, iclass 28, count 0 2006.257.05:01:26.50#ibcon#read 6, iclass 28, count 0 2006.257.05:01:26.50#ibcon#end of sib2, iclass 28, count 0 2006.257.05:01:26.50#ibcon#*after write, iclass 28, count 0 2006.257.05:01:26.50#ibcon#*before return 0, iclass 28, count 0 2006.257.05:01:26.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:26.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:26.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:01:26.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:01:26.50$vck44/va=4,7 2006.257.05:01:26.50#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.05:01:26.50#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.05:01:26.50#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:26.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:26.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:26.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:26.56#ibcon#enter wrdev, iclass 30, count 2 2006.257.05:01:26.56#ibcon#first serial, iclass 30, count 2 2006.257.05:01:26.56#ibcon#enter sib2, iclass 30, count 2 2006.257.05:01:26.56#ibcon#flushed, iclass 30, count 2 2006.257.05:01:26.56#ibcon#about to write, iclass 30, count 2 2006.257.05:01:26.56#ibcon#wrote, iclass 30, count 2 2006.257.05:01:26.56#ibcon#about to read 3, iclass 30, count 2 2006.257.05:01:26.57#abcon#<5=/15 1.8 4.7 19.68 931012.0\r\n> 2006.257.05:01:26.58#ibcon#read 3, iclass 30, count 2 2006.257.05:01:26.58#ibcon#about to read 4, iclass 30, count 2 2006.257.05:01:26.58#ibcon#read 4, iclass 30, count 2 2006.257.05:01:26.58#ibcon#about to read 5, iclass 30, count 2 2006.257.05:01:26.58#ibcon#read 5, iclass 30, count 2 2006.257.05:01:26.58#ibcon#about to read 6, iclass 30, count 2 2006.257.05:01:26.58#ibcon#read 6, iclass 30, count 2 2006.257.05:01:26.58#ibcon#end of sib2, iclass 30, count 2 2006.257.05:01:26.58#ibcon#*mode == 0, iclass 30, count 2 2006.257.05:01:26.58#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.05:01:26.58#ibcon#[25=AT04-07\r\n] 2006.257.05:01:26.58#ibcon#*before write, iclass 30, count 2 2006.257.05:01:26.58#ibcon#enter sib2, iclass 30, count 2 2006.257.05:01:26.58#ibcon#flushed, iclass 30, count 2 2006.257.05:01:26.58#ibcon#about to write, iclass 30, count 2 2006.257.05:01:26.58#ibcon#wrote, iclass 30, count 2 2006.257.05:01:26.58#ibcon#about to read 3, iclass 30, count 2 2006.257.05:01:26.59#abcon#{5=INTERFACE CLEAR} 2006.257.05:01:26.61#ibcon#read 3, iclass 30, count 2 2006.257.05:01:26.61#ibcon#about to read 4, iclass 30, count 2 2006.257.05:01:26.61#ibcon#read 4, iclass 30, count 2 2006.257.05:01:26.61#ibcon#about to read 5, iclass 30, count 2 2006.257.05:01:26.61#ibcon#read 5, iclass 30, count 2 2006.257.05:01:26.61#ibcon#about to read 6, iclass 30, count 2 2006.257.05:01:26.61#ibcon#read 6, iclass 30, count 2 2006.257.05:01:26.61#ibcon#end of sib2, iclass 30, count 2 2006.257.05:01:26.61#ibcon#*after write, iclass 30, count 2 2006.257.05:01:26.61#ibcon#*before return 0, iclass 30, count 2 2006.257.05:01:26.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:26.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:26.61#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.05:01:26.61#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:26.61#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:26.65#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:01:26.73#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:26.73#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:26.73#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:01:26.73#ibcon#first serial, iclass 30, count 0 2006.257.05:01:26.73#ibcon#enter sib2, iclass 30, count 0 2006.257.05:01:26.73#ibcon#flushed, iclass 30, count 0 2006.257.05:01:26.73#ibcon#about to write, iclass 30, count 0 2006.257.05:01:26.73#ibcon#wrote, iclass 30, count 0 2006.257.05:01:26.73#ibcon#about to read 3, iclass 30, count 0 2006.257.05:01:26.75#ibcon#read 3, iclass 30, count 0 2006.257.05:01:26.75#ibcon#about to read 4, iclass 30, count 0 2006.257.05:01:26.75#ibcon#read 4, iclass 30, count 0 2006.257.05:01:26.75#ibcon#about to read 5, iclass 30, count 0 2006.257.05:01:26.75#ibcon#read 5, iclass 30, count 0 2006.257.05:01:26.75#ibcon#about to read 6, iclass 30, count 0 2006.257.05:01:26.75#ibcon#read 6, iclass 30, count 0 2006.257.05:01:26.75#ibcon#end of sib2, iclass 30, count 0 2006.257.05:01:26.75#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:01:26.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:01:26.75#ibcon#[25=USB\r\n] 2006.257.05:01:26.75#ibcon#*before write, iclass 30, count 0 2006.257.05:01:26.75#ibcon#enter sib2, iclass 30, count 0 2006.257.05:01:26.75#ibcon#flushed, iclass 30, count 0 2006.257.05:01:26.75#ibcon#about to write, iclass 30, count 0 2006.257.05:01:26.75#ibcon#wrote, iclass 30, count 0 2006.257.05:01:26.75#ibcon#about to read 3, iclass 30, count 0 2006.257.05:01:26.78#ibcon#read 3, iclass 30, count 0 2006.257.05:01:26.78#ibcon#about to read 4, iclass 30, count 0 2006.257.05:01:26.78#ibcon#read 4, iclass 30, count 0 2006.257.05:01:26.78#ibcon#about to read 5, iclass 30, count 0 2006.257.05:01:26.78#ibcon#read 5, iclass 30, count 0 2006.257.05:01:26.78#ibcon#about to read 6, iclass 30, count 0 2006.257.05:01:26.78#ibcon#read 6, iclass 30, count 0 2006.257.05:01:26.78#ibcon#end of sib2, iclass 30, count 0 2006.257.05:01:26.78#ibcon#*after write, iclass 30, count 0 2006.257.05:01:26.78#ibcon#*before return 0, iclass 30, count 0 2006.257.05:01:26.78#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:26.78#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:26.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:01:26.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:01:26.78$vck44/valo=5,734.99 2006.257.05:01:26.78#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.05:01:26.78#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.05:01:26.78#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:26.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:26.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:26.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:26.78#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:01:26.78#ibcon#first serial, iclass 36, count 0 2006.257.05:01:26.78#ibcon#enter sib2, iclass 36, count 0 2006.257.05:01:26.78#ibcon#flushed, iclass 36, count 0 2006.257.05:01:26.78#ibcon#about to write, iclass 36, count 0 2006.257.05:01:26.78#ibcon#wrote, iclass 36, count 0 2006.257.05:01:26.78#ibcon#about to read 3, iclass 36, count 0 2006.257.05:01:26.80#ibcon#read 3, iclass 36, count 0 2006.257.05:01:26.80#ibcon#about to read 4, iclass 36, count 0 2006.257.05:01:26.80#ibcon#read 4, iclass 36, count 0 2006.257.05:01:26.80#ibcon#about to read 5, iclass 36, count 0 2006.257.05:01:26.80#ibcon#read 5, iclass 36, count 0 2006.257.05:01:26.80#ibcon#about to read 6, iclass 36, count 0 2006.257.05:01:26.80#ibcon#read 6, iclass 36, count 0 2006.257.05:01:26.80#ibcon#end of sib2, iclass 36, count 0 2006.257.05:01:26.80#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:01:26.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:01:26.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:01:26.80#ibcon#*before write, iclass 36, count 0 2006.257.05:01:26.80#ibcon#enter sib2, iclass 36, count 0 2006.257.05:01:26.80#ibcon#flushed, iclass 36, count 0 2006.257.05:01:26.80#ibcon#about to write, iclass 36, count 0 2006.257.05:01:26.80#ibcon#wrote, iclass 36, count 0 2006.257.05:01:26.80#ibcon#about to read 3, iclass 36, count 0 2006.257.05:01:26.84#ibcon#read 3, iclass 36, count 0 2006.257.05:01:26.84#ibcon#about to read 4, iclass 36, count 0 2006.257.05:01:26.84#ibcon#read 4, iclass 36, count 0 2006.257.05:01:26.84#ibcon#about to read 5, iclass 36, count 0 2006.257.05:01:26.84#ibcon#read 5, iclass 36, count 0 2006.257.05:01:26.84#ibcon#about to read 6, iclass 36, count 0 2006.257.05:01:26.84#ibcon#read 6, iclass 36, count 0 2006.257.05:01:26.84#ibcon#end of sib2, iclass 36, count 0 2006.257.05:01:26.84#ibcon#*after write, iclass 36, count 0 2006.257.05:01:26.84#ibcon#*before return 0, iclass 36, count 0 2006.257.05:01:26.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:26.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:26.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:01:26.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:01:26.84$vck44/va=5,4 2006.257.05:01:26.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.05:01:26.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.05:01:26.84#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:26.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:26.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:26.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:26.90#ibcon#enter wrdev, iclass 38, count 2 2006.257.05:01:26.90#ibcon#first serial, iclass 38, count 2 2006.257.05:01:26.90#ibcon#enter sib2, iclass 38, count 2 2006.257.05:01:26.90#ibcon#flushed, iclass 38, count 2 2006.257.05:01:26.90#ibcon#about to write, iclass 38, count 2 2006.257.05:01:26.90#ibcon#wrote, iclass 38, count 2 2006.257.05:01:26.90#ibcon#about to read 3, iclass 38, count 2 2006.257.05:01:26.92#ibcon#read 3, iclass 38, count 2 2006.257.05:01:26.92#ibcon#about to read 4, iclass 38, count 2 2006.257.05:01:26.92#ibcon#read 4, iclass 38, count 2 2006.257.05:01:26.92#ibcon#about to read 5, iclass 38, count 2 2006.257.05:01:26.92#ibcon#read 5, iclass 38, count 2 2006.257.05:01:26.92#ibcon#about to read 6, iclass 38, count 2 2006.257.05:01:26.92#ibcon#read 6, iclass 38, count 2 2006.257.05:01:26.92#ibcon#end of sib2, iclass 38, count 2 2006.257.05:01:26.92#ibcon#*mode == 0, iclass 38, count 2 2006.257.05:01:26.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.05:01:26.92#ibcon#[25=AT05-04\r\n] 2006.257.05:01:26.92#ibcon#*before write, iclass 38, count 2 2006.257.05:01:26.92#ibcon#enter sib2, iclass 38, count 2 2006.257.05:01:26.92#ibcon#flushed, iclass 38, count 2 2006.257.05:01:26.92#ibcon#about to write, iclass 38, count 2 2006.257.05:01:26.92#ibcon#wrote, iclass 38, count 2 2006.257.05:01:26.92#ibcon#about to read 3, iclass 38, count 2 2006.257.05:01:26.95#ibcon#read 3, iclass 38, count 2 2006.257.05:01:26.95#ibcon#about to read 4, iclass 38, count 2 2006.257.05:01:26.95#ibcon#read 4, iclass 38, count 2 2006.257.05:01:26.95#ibcon#about to read 5, iclass 38, count 2 2006.257.05:01:26.95#ibcon#read 5, iclass 38, count 2 2006.257.05:01:26.95#ibcon#about to read 6, iclass 38, count 2 2006.257.05:01:26.95#ibcon#read 6, iclass 38, count 2 2006.257.05:01:26.95#ibcon#end of sib2, iclass 38, count 2 2006.257.05:01:26.95#ibcon#*after write, iclass 38, count 2 2006.257.05:01:26.95#ibcon#*before return 0, iclass 38, count 2 2006.257.05:01:26.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:26.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:26.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.05:01:26.95#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:26.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:27.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:27.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:27.07#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:01:27.07#ibcon#first serial, iclass 38, count 0 2006.257.05:01:27.07#ibcon#enter sib2, iclass 38, count 0 2006.257.05:01:27.07#ibcon#flushed, iclass 38, count 0 2006.257.05:01:27.07#ibcon#about to write, iclass 38, count 0 2006.257.05:01:27.07#ibcon#wrote, iclass 38, count 0 2006.257.05:01:27.07#ibcon#about to read 3, iclass 38, count 0 2006.257.05:01:27.09#ibcon#read 3, iclass 38, count 0 2006.257.05:01:27.09#ibcon#about to read 4, iclass 38, count 0 2006.257.05:01:27.09#ibcon#read 4, iclass 38, count 0 2006.257.05:01:27.09#ibcon#about to read 5, iclass 38, count 0 2006.257.05:01:27.09#ibcon#read 5, iclass 38, count 0 2006.257.05:01:27.09#ibcon#about to read 6, iclass 38, count 0 2006.257.05:01:27.09#ibcon#read 6, iclass 38, count 0 2006.257.05:01:27.09#ibcon#end of sib2, iclass 38, count 0 2006.257.05:01:27.09#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:01:27.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:01:27.09#ibcon#[25=USB\r\n] 2006.257.05:01:27.09#ibcon#*before write, iclass 38, count 0 2006.257.05:01:27.09#ibcon#enter sib2, iclass 38, count 0 2006.257.05:01:27.09#ibcon#flushed, iclass 38, count 0 2006.257.05:01:27.09#ibcon#about to write, iclass 38, count 0 2006.257.05:01:27.09#ibcon#wrote, iclass 38, count 0 2006.257.05:01:27.09#ibcon#about to read 3, iclass 38, count 0 2006.257.05:01:27.12#ibcon#read 3, iclass 38, count 0 2006.257.05:01:27.12#ibcon#about to read 4, iclass 38, count 0 2006.257.05:01:27.12#ibcon#read 4, iclass 38, count 0 2006.257.05:01:27.12#ibcon#about to read 5, iclass 38, count 0 2006.257.05:01:27.12#ibcon#read 5, iclass 38, count 0 2006.257.05:01:27.12#ibcon#about to read 6, iclass 38, count 0 2006.257.05:01:27.12#ibcon#read 6, iclass 38, count 0 2006.257.05:01:27.12#ibcon#end of sib2, iclass 38, count 0 2006.257.05:01:27.12#ibcon#*after write, iclass 38, count 0 2006.257.05:01:27.12#ibcon#*before return 0, iclass 38, count 0 2006.257.05:01:27.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:27.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:27.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:01:27.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:01:27.12$vck44/valo=6,814.99 2006.257.05:01:27.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.05:01:27.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.05:01:27.12#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:27.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:27.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:27.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:27.12#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:01:27.12#ibcon#first serial, iclass 40, count 0 2006.257.05:01:27.12#ibcon#enter sib2, iclass 40, count 0 2006.257.05:01:27.12#ibcon#flushed, iclass 40, count 0 2006.257.05:01:27.12#ibcon#about to write, iclass 40, count 0 2006.257.05:01:27.12#ibcon#wrote, iclass 40, count 0 2006.257.05:01:27.12#ibcon#about to read 3, iclass 40, count 0 2006.257.05:01:27.14#ibcon#read 3, iclass 40, count 0 2006.257.05:01:27.14#ibcon#about to read 4, iclass 40, count 0 2006.257.05:01:27.14#ibcon#read 4, iclass 40, count 0 2006.257.05:01:27.14#ibcon#about to read 5, iclass 40, count 0 2006.257.05:01:27.14#ibcon#read 5, iclass 40, count 0 2006.257.05:01:27.14#ibcon#about to read 6, iclass 40, count 0 2006.257.05:01:27.14#ibcon#read 6, iclass 40, count 0 2006.257.05:01:27.14#ibcon#end of sib2, iclass 40, count 0 2006.257.05:01:27.14#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:01:27.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:01:27.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:01:27.14#ibcon#*before write, iclass 40, count 0 2006.257.05:01:27.14#ibcon#enter sib2, iclass 40, count 0 2006.257.05:01:27.14#ibcon#flushed, iclass 40, count 0 2006.257.05:01:27.14#ibcon#about to write, iclass 40, count 0 2006.257.05:01:27.14#ibcon#wrote, iclass 40, count 0 2006.257.05:01:27.14#ibcon#about to read 3, iclass 40, count 0 2006.257.05:01:27.18#ibcon#read 3, iclass 40, count 0 2006.257.05:01:27.18#ibcon#about to read 4, iclass 40, count 0 2006.257.05:01:27.18#ibcon#read 4, iclass 40, count 0 2006.257.05:01:27.18#ibcon#about to read 5, iclass 40, count 0 2006.257.05:01:27.18#ibcon#read 5, iclass 40, count 0 2006.257.05:01:27.18#ibcon#about to read 6, iclass 40, count 0 2006.257.05:01:27.18#ibcon#read 6, iclass 40, count 0 2006.257.05:01:27.18#ibcon#end of sib2, iclass 40, count 0 2006.257.05:01:27.18#ibcon#*after write, iclass 40, count 0 2006.257.05:01:27.18#ibcon#*before return 0, iclass 40, count 0 2006.257.05:01:27.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:27.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:27.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:01:27.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:01:27.18$vck44/va=6,4 2006.257.05:01:27.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.05:01:27.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.05:01:27.18#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:27.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:27.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:27.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:27.24#ibcon#enter wrdev, iclass 4, count 2 2006.257.05:01:27.24#ibcon#first serial, iclass 4, count 2 2006.257.05:01:27.24#ibcon#enter sib2, iclass 4, count 2 2006.257.05:01:27.24#ibcon#flushed, iclass 4, count 2 2006.257.05:01:27.24#ibcon#about to write, iclass 4, count 2 2006.257.05:01:27.24#ibcon#wrote, iclass 4, count 2 2006.257.05:01:27.24#ibcon#about to read 3, iclass 4, count 2 2006.257.05:01:27.26#ibcon#read 3, iclass 4, count 2 2006.257.05:01:27.26#ibcon#about to read 4, iclass 4, count 2 2006.257.05:01:27.26#ibcon#read 4, iclass 4, count 2 2006.257.05:01:27.26#ibcon#about to read 5, iclass 4, count 2 2006.257.05:01:27.26#ibcon#read 5, iclass 4, count 2 2006.257.05:01:27.26#ibcon#about to read 6, iclass 4, count 2 2006.257.05:01:27.26#ibcon#read 6, iclass 4, count 2 2006.257.05:01:27.26#ibcon#end of sib2, iclass 4, count 2 2006.257.05:01:27.26#ibcon#*mode == 0, iclass 4, count 2 2006.257.05:01:27.26#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.05:01:27.26#ibcon#[25=AT06-04\r\n] 2006.257.05:01:27.26#ibcon#*before write, iclass 4, count 2 2006.257.05:01:27.26#ibcon#enter sib2, iclass 4, count 2 2006.257.05:01:27.26#ibcon#flushed, iclass 4, count 2 2006.257.05:01:27.26#ibcon#about to write, iclass 4, count 2 2006.257.05:01:27.26#ibcon#wrote, iclass 4, count 2 2006.257.05:01:27.26#ibcon#about to read 3, iclass 4, count 2 2006.257.05:01:27.29#ibcon#read 3, iclass 4, count 2 2006.257.05:01:27.29#ibcon#about to read 4, iclass 4, count 2 2006.257.05:01:27.29#ibcon#read 4, iclass 4, count 2 2006.257.05:01:27.29#ibcon#about to read 5, iclass 4, count 2 2006.257.05:01:27.29#ibcon#read 5, iclass 4, count 2 2006.257.05:01:27.29#ibcon#about to read 6, iclass 4, count 2 2006.257.05:01:27.29#ibcon#read 6, iclass 4, count 2 2006.257.05:01:27.29#ibcon#end of sib2, iclass 4, count 2 2006.257.05:01:27.29#ibcon#*after write, iclass 4, count 2 2006.257.05:01:27.29#ibcon#*before return 0, iclass 4, count 2 2006.257.05:01:27.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:27.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:27.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.05:01:27.29#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:27.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:27.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:27.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:27.41#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:01:27.41#ibcon#first serial, iclass 4, count 0 2006.257.05:01:27.41#ibcon#enter sib2, iclass 4, count 0 2006.257.05:01:27.41#ibcon#flushed, iclass 4, count 0 2006.257.05:01:27.41#ibcon#about to write, iclass 4, count 0 2006.257.05:01:27.41#ibcon#wrote, iclass 4, count 0 2006.257.05:01:27.41#ibcon#about to read 3, iclass 4, count 0 2006.257.05:01:27.43#ibcon#read 3, iclass 4, count 0 2006.257.05:01:27.43#ibcon#about to read 4, iclass 4, count 0 2006.257.05:01:27.43#ibcon#read 4, iclass 4, count 0 2006.257.05:01:27.43#ibcon#about to read 5, iclass 4, count 0 2006.257.05:01:27.43#ibcon#read 5, iclass 4, count 0 2006.257.05:01:27.43#ibcon#about to read 6, iclass 4, count 0 2006.257.05:01:27.43#ibcon#read 6, iclass 4, count 0 2006.257.05:01:27.43#ibcon#end of sib2, iclass 4, count 0 2006.257.05:01:27.43#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:01:27.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:01:27.43#ibcon#[25=USB\r\n] 2006.257.05:01:27.43#ibcon#*before write, iclass 4, count 0 2006.257.05:01:27.43#ibcon#enter sib2, iclass 4, count 0 2006.257.05:01:27.43#ibcon#flushed, iclass 4, count 0 2006.257.05:01:27.43#ibcon#about to write, iclass 4, count 0 2006.257.05:01:27.43#ibcon#wrote, iclass 4, count 0 2006.257.05:01:27.43#ibcon#about to read 3, iclass 4, count 0 2006.257.05:01:27.46#ibcon#read 3, iclass 4, count 0 2006.257.05:01:27.46#ibcon#about to read 4, iclass 4, count 0 2006.257.05:01:27.46#ibcon#read 4, iclass 4, count 0 2006.257.05:01:27.46#ibcon#about to read 5, iclass 4, count 0 2006.257.05:01:27.46#ibcon#read 5, iclass 4, count 0 2006.257.05:01:27.46#ibcon#about to read 6, iclass 4, count 0 2006.257.05:01:27.46#ibcon#read 6, iclass 4, count 0 2006.257.05:01:27.46#ibcon#end of sib2, iclass 4, count 0 2006.257.05:01:27.46#ibcon#*after write, iclass 4, count 0 2006.257.05:01:27.46#ibcon#*before return 0, iclass 4, count 0 2006.257.05:01:27.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:27.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:27.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:01:27.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:01:27.46$vck44/valo=7,864.99 2006.257.05:01:27.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.05:01:27.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.05:01:27.46#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:27.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:27.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:27.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:27.46#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:01:27.46#ibcon#first serial, iclass 6, count 0 2006.257.05:01:27.46#ibcon#enter sib2, iclass 6, count 0 2006.257.05:01:27.46#ibcon#flushed, iclass 6, count 0 2006.257.05:01:27.46#ibcon#about to write, iclass 6, count 0 2006.257.05:01:27.46#ibcon#wrote, iclass 6, count 0 2006.257.05:01:27.46#ibcon#about to read 3, iclass 6, count 0 2006.257.05:01:27.48#ibcon#read 3, iclass 6, count 0 2006.257.05:01:27.48#ibcon#about to read 4, iclass 6, count 0 2006.257.05:01:27.48#ibcon#read 4, iclass 6, count 0 2006.257.05:01:27.48#ibcon#about to read 5, iclass 6, count 0 2006.257.05:01:27.48#ibcon#read 5, iclass 6, count 0 2006.257.05:01:27.48#ibcon#about to read 6, iclass 6, count 0 2006.257.05:01:27.48#ibcon#read 6, iclass 6, count 0 2006.257.05:01:27.48#ibcon#end of sib2, iclass 6, count 0 2006.257.05:01:27.48#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:01:27.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:01:27.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:01:27.48#ibcon#*before write, iclass 6, count 0 2006.257.05:01:27.48#ibcon#enter sib2, iclass 6, count 0 2006.257.05:01:27.48#ibcon#flushed, iclass 6, count 0 2006.257.05:01:27.48#ibcon#about to write, iclass 6, count 0 2006.257.05:01:27.48#ibcon#wrote, iclass 6, count 0 2006.257.05:01:27.48#ibcon#about to read 3, iclass 6, count 0 2006.257.05:01:27.52#ibcon#read 3, iclass 6, count 0 2006.257.05:01:27.52#ibcon#about to read 4, iclass 6, count 0 2006.257.05:01:27.52#ibcon#read 4, iclass 6, count 0 2006.257.05:01:27.52#ibcon#about to read 5, iclass 6, count 0 2006.257.05:01:27.52#ibcon#read 5, iclass 6, count 0 2006.257.05:01:27.52#ibcon#about to read 6, iclass 6, count 0 2006.257.05:01:27.52#ibcon#read 6, iclass 6, count 0 2006.257.05:01:27.52#ibcon#end of sib2, iclass 6, count 0 2006.257.05:01:27.52#ibcon#*after write, iclass 6, count 0 2006.257.05:01:27.52#ibcon#*before return 0, iclass 6, count 0 2006.257.05:01:27.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:27.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:27.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:01:27.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:01:27.52$vck44/va=7,4 2006.257.05:01:27.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.05:01:27.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.05:01:27.52#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:27.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:27.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:27.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:27.58#ibcon#enter wrdev, iclass 10, count 2 2006.257.05:01:27.58#ibcon#first serial, iclass 10, count 2 2006.257.05:01:27.58#ibcon#enter sib2, iclass 10, count 2 2006.257.05:01:27.58#ibcon#flushed, iclass 10, count 2 2006.257.05:01:27.58#ibcon#about to write, iclass 10, count 2 2006.257.05:01:27.58#ibcon#wrote, iclass 10, count 2 2006.257.05:01:27.58#ibcon#about to read 3, iclass 10, count 2 2006.257.05:01:27.60#ibcon#read 3, iclass 10, count 2 2006.257.05:01:27.60#ibcon#about to read 4, iclass 10, count 2 2006.257.05:01:27.60#ibcon#read 4, iclass 10, count 2 2006.257.05:01:27.60#ibcon#about to read 5, iclass 10, count 2 2006.257.05:01:27.60#ibcon#read 5, iclass 10, count 2 2006.257.05:01:27.60#ibcon#about to read 6, iclass 10, count 2 2006.257.05:01:27.60#ibcon#read 6, iclass 10, count 2 2006.257.05:01:27.60#ibcon#end of sib2, iclass 10, count 2 2006.257.05:01:27.60#ibcon#*mode == 0, iclass 10, count 2 2006.257.05:01:27.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.05:01:27.60#ibcon#[25=AT07-04\r\n] 2006.257.05:01:27.60#ibcon#*before write, iclass 10, count 2 2006.257.05:01:27.60#ibcon#enter sib2, iclass 10, count 2 2006.257.05:01:27.60#ibcon#flushed, iclass 10, count 2 2006.257.05:01:27.60#ibcon#about to write, iclass 10, count 2 2006.257.05:01:27.60#ibcon#wrote, iclass 10, count 2 2006.257.05:01:27.60#ibcon#about to read 3, iclass 10, count 2 2006.257.05:01:27.63#ibcon#read 3, iclass 10, count 2 2006.257.05:01:27.63#ibcon#about to read 4, iclass 10, count 2 2006.257.05:01:27.63#ibcon#read 4, iclass 10, count 2 2006.257.05:01:27.63#ibcon#about to read 5, iclass 10, count 2 2006.257.05:01:27.63#ibcon#read 5, iclass 10, count 2 2006.257.05:01:27.63#ibcon#about to read 6, iclass 10, count 2 2006.257.05:01:27.63#ibcon#read 6, iclass 10, count 2 2006.257.05:01:27.63#ibcon#end of sib2, iclass 10, count 2 2006.257.05:01:27.63#ibcon#*after write, iclass 10, count 2 2006.257.05:01:27.63#ibcon#*before return 0, iclass 10, count 2 2006.257.05:01:27.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:27.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:27.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.05:01:27.63#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:27.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:27.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:27.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:27.75#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:01:27.75#ibcon#first serial, iclass 10, count 0 2006.257.05:01:27.75#ibcon#enter sib2, iclass 10, count 0 2006.257.05:01:27.75#ibcon#flushed, iclass 10, count 0 2006.257.05:01:27.75#ibcon#about to write, iclass 10, count 0 2006.257.05:01:27.75#ibcon#wrote, iclass 10, count 0 2006.257.05:01:27.75#ibcon#about to read 3, iclass 10, count 0 2006.257.05:01:27.77#ibcon#read 3, iclass 10, count 0 2006.257.05:01:27.77#ibcon#about to read 4, iclass 10, count 0 2006.257.05:01:27.77#ibcon#read 4, iclass 10, count 0 2006.257.05:01:27.77#ibcon#about to read 5, iclass 10, count 0 2006.257.05:01:27.77#ibcon#read 5, iclass 10, count 0 2006.257.05:01:27.77#ibcon#about to read 6, iclass 10, count 0 2006.257.05:01:27.77#ibcon#read 6, iclass 10, count 0 2006.257.05:01:27.77#ibcon#end of sib2, iclass 10, count 0 2006.257.05:01:27.77#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:01:27.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:01:27.77#ibcon#[25=USB\r\n] 2006.257.05:01:27.77#ibcon#*before write, iclass 10, count 0 2006.257.05:01:27.77#ibcon#enter sib2, iclass 10, count 0 2006.257.05:01:27.77#ibcon#flushed, iclass 10, count 0 2006.257.05:01:27.77#ibcon#about to write, iclass 10, count 0 2006.257.05:01:27.77#ibcon#wrote, iclass 10, count 0 2006.257.05:01:27.77#ibcon#about to read 3, iclass 10, count 0 2006.257.05:01:27.80#ibcon#read 3, iclass 10, count 0 2006.257.05:01:27.80#ibcon#about to read 4, iclass 10, count 0 2006.257.05:01:27.80#ibcon#read 4, iclass 10, count 0 2006.257.05:01:27.80#ibcon#about to read 5, iclass 10, count 0 2006.257.05:01:27.80#ibcon#read 5, iclass 10, count 0 2006.257.05:01:27.80#ibcon#about to read 6, iclass 10, count 0 2006.257.05:01:27.80#ibcon#read 6, iclass 10, count 0 2006.257.05:01:27.80#ibcon#end of sib2, iclass 10, count 0 2006.257.05:01:27.80#ibcon#*after write, iclass 10, count 0 2006.257.05:01:27.80#ibcon#*before return 0, iclass 10, count 0 2006.257.05:01:27.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:27.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:27.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:01:27.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:01:27.80$vck44/valo=8,884.99 2006.257.05:01:27.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.05:01:27.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.05:01:27.80#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:27.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:27.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:27.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:27.80#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:01:27.80#ibcon#first serial, iclass 12, count 0 2006.257.05:01:27.80#ibcon#enter sib2, iclass 12, count 0 2006.257.05:01:27.80#ibcon#flushed, iclass 12, count 0 2006.257.05:01:27.80#ibcon#about to write, iclass 12, count 0 2006.257.05:01:27.80#ibcon#wrote, iclass 12, count 0 2006.257.05:01:27.80#ibcon#about to read 3, iclass 12, count 0 2006.257.05:01:27.82#ibcon#read 3, iclass 12, count 0 2006.257.05:01:27.82#ibcon#about to read 4, iclass 12, count 0 2006.257.05:01:27.82#ibcon#read 4, iclass 12, count 0 2006.257.05:01:27.82#ibcon#about to read 5, iclass 12, count 0 2006.257.05:01:27.82#ibcon#read 5, iclass 12, count 0 2006.257.05:01:27.82#ibcon#about to read 6, iclass 12, count 0 2006.257.05:01:27.82#ibcon#read 6, iclass 12, count 0 2006.257.05:01:27.82#ibcon#end of sib2, iclass 12, count 0 2006.257.05:01:27.82#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:01:27.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:01:27.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:01:27.82#ibcon#*before write, iclass 12, count 0 2006.257.05:01:27.82#ibcon#enter sib2, iclass 12, count 0 2006.257.05:01:27.82#ibcon#flushed, iclass 12, count 0 2006.257.05:01:27.82#ibcon#about to write, iclass 12, count 0 2006.257.05:01:27.82#ibcon#wrote, iclass 12, count 0 2006.257.05:01:27.82#ibcon#about to read 3, iclass 12, count 0 2006.257.05:01:27.86#ibcon#read 3, iclass 12, count 0 2006.257.05:01:27.86#ibcon#about to read 4, iclass 12, count 0 2006.257.05:01:27.86#ibcon#read 4, iclass 12, count 0 2006.257.05:01:27.86#ibcon#about to read 5, iclass 12, count 0 2006.257.05:01:27.86#ibcon#read 5, iclass 12, count 0 2006.257.05:01:27.86#ibcon#about to read 6, iclass 12, count 0 2006.257.05:01:27.86#ibcon#read 6, iclass 12, count 0 2006.257.05:01:27.86#ibcon#end of sib2, iclass 12, count 0 2006.257.05:01:27.86#ibcon#*after write, iclass 12, count 0 2006.257.05:01:27.86#ibcon#*before return 0, iclass 12, count 0 2006.257.05:01:27.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:27.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:27.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:01:27.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:01:27.86$vck44/va=8,4 2006.257.05:01:27.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.05:01:27.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.05:01:27.86#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:27.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:01:27.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:01:27.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:01:27.92#ibcon#enter wrdev, iclass 14, count 2 2006.257.05:01:27.92#ibcon#first serial, iclass 14, count 2 2006.257.05:01:27.92#ibcon#enter sib2, iclass 14, count 2 2006.257.05:01:27.92#ibcon#flushed, iclass 14, count 2 2006.257.05:01:27.92#ibcon#about to write, iclass 14, count 2 2006.257.05:01:27.92#ibcon#wrote, iclass 14, count 2 2006.257.05:01:27.92#ibcon#about to read 3, iclass 14, count 2 2006.257.05:01:27.94#ibcon#read 3, iclass 14, count 2 2006.257.05:01:27.94#ibcon#about to read 4, iclass 14, count 2 2006.257.05:01:27.94#ibcon#read 4, iclass 14, count 2 2006.257.05:01:27.94#ibcon#about to read 5, iclass 14, count 2 2006.257.05:01:27.94#ibcon#read 5, iclass 14, count 2 2006.257.05:01:27.94#ibcon#about to read 6, iclass 14, count 2 2006.257.05:01:27.94#ibcon#read 6, iclass 14, count 2 2006.257.05:01:27.94#ibcon#end of sib2, iclass 14, count 2 2006.257.05:01:27.94#ibcon#*mode == 0, iclass 14, count 2 2006.257.05:01:27.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.05:01:27.94#ibcon#[25=AT08-04\r\n] 2006.257.05:01:27.94#ibcon#*before write, iclass 14, count 2 2006.257.05:01:27.94#ibcon#enter sib2, iclass 14, count 2 2006.257.05:01:27.94#ibcon#flushed, iclass 14, count 2 2006.257.05:01:27.94#ibcon#about to write, iclass 14, count 2 2006.257.05:01:27.94#ibcon#wrote, iclass 14, count 2 2006.257.05:01:27.94#ibcon#about to read 3, iclass 14, count 2 2006.257.05:01:27.97#ibcon#read 3, iclass 14, count 2 2006.257.05:01:27.97#ibcon#about to read 4, iclass 14, count 2 2006.257.05:01:27.97#ibcon#read 4, iclass 14, count 2 2006.257.05:01:27.97#ibcon#about to read 5, iclass 14, count 2 2006.257.05:01:27.97#ibcon#read 5, iclass 14, count 2 2006.257.05:01:27.97#ibcon#about to read 6, iclass 14, count 2 2006.257.05:01:27.97#ibcon#read 6, iclass 14, count 2 2006.257.05:01:27.97#ibcon#end of sib2, iclass 14, count 2 2006.257.05:01:27.97#ibcon#*after write, iclass 14, count 2 2006.257.05:01:27.97#ibcon#*before return 0, iclass 14, count 2 2006.257.05:01:27.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:01:27.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:01:27.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.05:01:27.97#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:27.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:01:28.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:01:28.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:01:28.09#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:01:28.09#ibcon#first serial, iclass 14, count 0 2006.257.05:01:28.09#ibcon#enter sib2, iclass 14, count 0 2006.257.05:01:28.09#ibcon#flushed, iclass 14, count 0 2006.257.05:01:28.09#ibcon#about to write, iclass 14, count 0 2006.257.05:01:28.09#ibcon#wrote, iclass 14, count 0 2006.257.05:01:28.09#ibcon#about to read 3, iclass 14, count 0 2006.257.05:01:28.11#ibcon#read 3, iclass 14, count 0 2006.257.05:01:28.11#ibcon#about to read 4, iclass 14, count 0 2006.257.05:01:28.11#ibcon#read 4, iclass 14, count 0 2006.257.05:01:28.11#ibcon#about to read 5, iclass 14, count 0 2006.257.05:01:28.11#ibcon#read 5, iclass 14, count 0 2006.257.05:01:28.11#ibcon#about to read 6, iclass 14, count 0 2006.257.05:01:28.11#ibcon#read 6, iclass 14, count 0 2006.257.05:01:28.11#ibcon#end of sib2, iclass 14, count 0 2006.257.05:01:28.11#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:01:28.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:01:28.11#ibcon#[25=USB\r\n] 2006.257.05:01:28.11#ibcon#*before write, iclass 14, count 0 2006.257.05:01:28.11#ibcon#enter sib2, iclass 14, count 0 2006.257.05:01:28.11#ibcon#flushed, iclass 14, count 0 2006.257.05:01:28.11#ibcon#about to write, iclass 14, count 0 2006.257.05:01:28.11#ibcon#wrote, iclass 14, count 0 2006.257.05:01:28.11#ibcon#about to read 3, iclass 14, count 0 2006.257.05:01:28.14#ibcon#read 3, iclass 14, count 0 2006.257.05:01:28.14#ibcon#about to read 4, iclass 14, count 0 2006.257.05:01:28.14#ibcon#read 4, iclass 14, count 0 2006.257.05:01:28.14#ibcon#about to read 5, iclass 14, count 0 2006.257.05:01:28.14#ibcon#read 5, iclass 14, count 0 2006.257.05:01:28.14#ibcon#about to read 6, iclass 14, count 0 2006.257.05:01:28.14#ibcon#read 6, iclass 14, count 0 2006.257.05:01:28.14#ibcon#end of sib2, iclass 14, count 0 2006.257.05:01:28.14#ibcon#*after write, iclass 14, count 0 2006.257.05:01:28.14#ibcon#*before return 0, iclass 14, count 0 2006.257.05:01:28.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:01:28.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:01:28.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:01:28.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:01:28.14$vck44/vblo=1,629.99 2006.257.05:01:28.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.05:01:28.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.05:01:28.14#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:28.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:28.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:28.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:28.14#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:01:28.14#ibcon#first serial, iclass 16, count 0 2006.257.05:01:28.14#ibcon#enter sib2, iclass 16, count 0 2006.257.05:01:28.14#ibcon#flushed, iclass 16, count 0 2006.257.05:01:28.14#ibcon#about to write, iclass 16, count 0 2006.257.05:01:28.14#ibcon#wrote, iclass 16, count 0 2006.257.05:01:28.14#ibcon#about to read 3, iclass 16, count 0 2006.257.05:01:28.16#ibcon#read 3, iclass 16, count 0 2006.257.05:01:28.16#ibcon#about to read 4, iclass 16, count 0 2006.257.05:01:28.16#ibcon#read 4, iclass 16, count 0 2006.257.05:01:28.16#ibcon#about to read 5, iclass 16, count 0 2006.257.05:01:28.16#ibcon#read 5, iclass 16, count 0 2006.257.05:01:28.16#ibcon#about to read 6, iclass 16, count 0 2006.257.05:01:28.16#ibcon#read 6, iclass 16, count 0 2006.257.05:01:28.16#ibcon#end of sib2, iclass 16, count 0 2006.257.05:01:28.16#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:01:28.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:01:28.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:01:28.16#ibcon#*before write, iclass 16, count 0 2006.257.05:01:28.16#ibcon#enter sib2, iclass 16, count 0 2006.257.05:01:28.16#ibcon#flushed, iclass 16, count 0 2006.257.05:01:28.16#ibcon#about to write, iclass 16, count 0 2006.257.05:01:28.16#ibcon#wrote, iclass 16, count 0 2006.257.05:01:28.16#ibcon#about to read 3, iclass 16, count 0 2006.257.05:01:28.20#ibcon#read 3, iclass 16, count 0 2006.257.05:01:28.20#ibcon#about to read 4, iclass 16, count 0 2006.257.05:01:28.20#ibcon#read 4, iclass 16, count 0 2006.257.05:01:28.20#ibcon#about to read 5, iclass 16, count 0 2006.257.05:01:28.20#ibcon#read 5, iclass 16, count 0 2006.257.05:01:28.20#ibcon#about to read 6, iclass 16, count 0 2006.257.05:01:28.20#ibcon#read 6, iclass 16, count 0 2006.257.05:01:28.20#ibcon#end of sib2, iclass 16, count 0 2006.257.05:01:28.20#ibcon#*after write, iclass 16, count 0 2006.257.05:01:28.20#ibcon#*before return 0, iclass 16, count 0 2006.257.05:01:28.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:28.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:01:28.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:01:28.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:01:28.20$vck44/vb=1,4 2006.257.05:01:28.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.05:01:28.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.05:01:28.20#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:28.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:28.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:28.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:28.20#ibcon#enter wrdev, iclass 18, count 2 2006.257.05:01:28.20#ibcon#first serial, iclass 18, count 2 2006.257.05:01:28.20#ibcon#enter sib2, iclass 18, count 2 2006.257.05:01:28.20#ibcon#flushed, iclass 18, count 2 2006.257.05:01:28.20#ibcon#about to write, iclass 18, count 2 2006.257.05:01:28.20#ibcon#wrote, iclass 18, count 2 2006.257.05:01:28.20#ibcon#about to read 3, iclass 18, count 2 2006.257.05:01:28.22#ibcon#read 3, iclass 18, count 2 2006.257.05:01:28.22#ibcon#about to read 4, iclass 18, count 2 2006.257.05:01:28.22#ibcon#read 4, iclass 18, count 2 2006.257.05:01:28.22#ibcon#about to read 5, iclass 18, count 2 2006.257.05:01:28.22#ibcon#read 5, iclass 18, count 2 2006.257.05:01:28.22#ibcon#about to read 6, iclass 18, count 2 2006.257.05:01:28.22#ibcon#read 6, iclass 18, count 2 2006.257.05:01:28.22#ibcon#end of sib2, iclass 18, count 2 2006.257.05:01:28.22#ibcon#*mode == 0, iclass 18, count 2 2006.257.05:01:28.22#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.05:01:28.22#ibcon#[27=AT01-04\r\n] 2006.257.05:01:28.22#ibcon#*before write, iclass 18, count 2 2006.257.05:01:28.22#ibcon#enter sib2, iclass 18, count 2 2006.257.05:01:28.22#ibcon#flushed, iclass 18, count 2 2006.257.05:01:28.22#ibcon#about to write, iclass 18, count 2 2006.257.05:01:28.22#ibcon#wrote, iclass 18, count 2 2006.257.05:01:28.22#ibcon#about to read 3, iclass 18, count 2 2006.257.05:01:28.25#ibcon#read 3, iclass 18, count 2 2006.257.05:01:28.25#ibcon#about to read 4, iclass 18, count 2 2006.257.05:01:28.25#ibcon#read 4, iclass 18, count 2 2006.257.05:01:28.25#ibcon#about to read 5, iclass 18, count 2 2006.257.05:01:28.25#ibcon#read 5, iclass 18, count 2 2006.257.05:01:28.25#ibcon#about to read 6, iclass 18, count 2 2006.257.05:01:28.25#ibcon#read 6, iclass 18, count 2 2006.257.05:01:28.25#ibcon#end of sib2, iclass 18, count 2 2006.257.05:01:28.25#ibcon#*after write, iclass 18, count 2 2006.257.05:01:28.25#ibcon#*before return 0, iclass 18, count 2 2006.257.05:01:28.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:28.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:01:28.25#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.05:01:28.25#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:28.25#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:28.37#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:28.37#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:28.37#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:01:28.37#ibcon#first serial, iclass 18, count 0 2006.257.05:01:28.37#ibcon#enter sib2, iclass 18, count 0 2006.257.05:01:28.37#ibcon#flushed, iclass 18, count 0 2006.257.05:01:28.37#ibcon#about to write, iclass 18, count 0 2006.257.05:01:28.37#ibcon#wrote, iclass 18, count 0 2006.257.05:01:28.37#ibcon#about to read 3, iclass 18, count 0 2006.257.05:01:28.39#ibcon#read 3, iclass 18, count 0 2006.257.05:01:28.39#ibcon#about to read 4, iclass 18, count 0 2006.257.05:01:28.39#ibcon#read 4, iclass 18, count 0 2006.257.05:01:28.39#ibcon#about to read 5, iclass 18, count 0 2006.257.05:01:28.39#ibcon#read 5, iclass 18, count 0 2006.257.05:01:28.39#ibcon#about to read 6, iclass 18, count 0 2006.257.05:01:28.39#ibcon#read 6, iclass 18, count 0 2006.257.05:01:28.39#ibcon#end of sib2, iclass 18, count 0 2006.257.05:01:28.39#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:01:28.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:01:28.39#ibcon#[27=USB\r\n] 2006.257.05:01:28.39#ibcon#*before write, iclass 18, count 0 2006.257.05:01:28.39#ibcon#enter sib2, iclass 18, count 0 2006.257.05:01:28.39#ibcon#flushed, iclass 18, count 0 2006.257.05:01:28.39#ibcon#about to write, iclass 18, count 0 2006.257.05:01:28.39#ibcon#wrote, iclass 18, count 0 2006.257.05:01:28.39#ibcon#about to read 3, iclass 18, count 0 2006.257.05:01:28.42#ibcon#read 3, iclass 18, count 0 2006.257.05:01:28.42#ibcon#about to read 4, iclass 18, count 0 2006.257.05:01:28.42#ibcon#read 4, iclass 18, count 0 2006.257.05:01:28.42#ibcon#about to read 5, iclass 18, count 0 2006.257.05:01:28.42#ibcon#read 5, iclass 18, count 0 2006.257.05:01:28.42#ibcon#about to read 6, iclass 18, count 0 2006.257.05:01:28.42#ibcon#read 6, iclass 18, count 0 2006.257.05:01:28.42#ibcon#end of sib2, iclass 18, count 0 2006.257.05:01:28.42#ibcon#*after write, iclass 18, count 0 2006.257.05:01:28.42#ibcon#*before return 0, iclass 18, count 0 2006.257.05:01:28.42#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:28.42#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:01:28.42#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:01:28.42#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:01:28.42$vck44/vblo=2,634.99 2006.257.05:01:28.42#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.05:01:28.42#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.05:01:28.42#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:28.42#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:28.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:28.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:28.42#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:01:28.42#ibcon#first serial, iclass 20, count 0 2006.257.05:01:28.42#ibcon#enter sib2, iclass 20, count 0 2006.257.05:01:28.42#ibcon#flushed, iclass 20, count 0 2006.257.05:01:28.42#ibcon#about to write, iclass 20, count 0 2006.257.05:01:28.42#ibcon#wrote, iclass 20, count 0 2006.257.05:01:28.42#ibcon#about to read 3, iclass 20, count 0 2006.257.05:01:28.44#ibcon#read 3, iclass 20, count 0 2006.257.05:01:28.44#ibcon#about to read 4, iclass 20, count 0 2006.257.05:01:28.44#ibcon#read 4, iclass 20, count 0 2006.257.05:01:28.44#ibcon#about to read 5, iclass 20, count 0 2006.257.05:01:28.44#ibcon#read 5, iclass 20, count 0 2006.257.05:01:28.44#ibcon#about to read 6, iclass 20, count 0 2006.257.05:01:28.44#ibcon#read 6, iclass 20, count 0 2006.257.05:01:28.44#ibcon#end of sib2, iclass 20, count 0 2006.257.05:01:28.44#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:01:28.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:01:28.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:01:28.44#ibcon#*before write, iclass 20, count 0 2006.257.05:01:28.44#ibcon#enter sib2, iclass 20, count 0 2006.257.05:01:28.44#ibcon#flushed, iclass 20, count 0 2006.257.05:01:28.44#ibcon#about to write, iclass 20, count 0 2006.257.05:01:28.44#ibcon#wrote, iclass 20, count 0 2006.257.05:01:28.44#ibcon#about to read 3, iclass 20, count 0 2006.257.05:01:28.48#ibcon#read 3, iclass 20, count 0 2006.257.05:01:28.48#ibcon#about to read 4, iclass 20, count 0 2006.257.05:01:28.48#ibcon#read 4, iclass 20, count 0 2006.257.05:01:28.48#ibcon#about to read 5, iclass 20, count 0 2006.257.05:01:28.48#ibcon#read 5, iclass 20, count 0 2006.257.05:01:28.48#ibcon#about to read 6, iclass 20, count 0 2006.257.05:01:28.48#ibcon#read 6, iclass 20, count 0 2006.257.05:01:28.48#ibcon#end of sib2, iclass 20, count 0 2006.257.05:01:28.48#ibcon#*after write, iclass 20, count 0 2006.257.05:01:28.48#ibcon#*before return 0, iclass 20, count 0 2006.257.05:01:28.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:28.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:01:28.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:01:28.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:01:28.48$vck44/vb=2,5 2006.257.05:01:28.48#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.05:01:28.48#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.05:01:28.48#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:28.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:28.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:28.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:28.54#ibcon#enter wrdev, iclass 22, count 2 2006.257.05:01:28.54#ibcon#first serial, iclass 22, count 2 2006.257.05:01:28.54#ibcon#enter sib2, iclass 22, count 2 2006.257.05:01:28.54#ibcon#flushed, iclass 22, count 2 2006.257.05:01:28.54#ibcon#about to write, iclass 22, count 2 2006.257.05:01:28.54#ibcon#wrote, iclass 22, count 2 2006.257.05:01:28.54#ibcon#about to read 3, iclass 22, count 2 2006.257.05:01:28.56#ibcon#read 3, iclass 22, count 2 2006.257.05:01:28.56#ibcon#about to read 4, iclass 22, count 2 2006.257.05:01:28.56#ibcon#read 4, iclass 22, count 2 2006.257.05:01:28.56#ibcon#about to read 5, iclass 22, count 2 2006.257.05:01:28.56#ibcon#read 5, iclass 22, count 2 2006.257.05:01:28.56#ibcon#about to read 6, iclass 22, count 2 2006.257.05:01:28.56#ibcon#read 6, iclass 22, count 2 2006.257.05:01:28.56#ibcon#end of sib2, iclass 22, count 2 2006.257.05:01:28.56#ibcon#*mode == 0, iclass 22, count 2 2006.257.05:01:28.56#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.05:01:28.56#ibcon#[27=AT02-05\r\n] 2006.257.05:01:28.56#ibcon#*before write, iclass 22, count 2 2006.257.05:01:28.56#ibcon#enter sib2, iclass 22, count 2 2006.257.05:01:28.56#ibcon#flushed, iclass 22, count 2 2006.257.05:01:28.56#ibcon#about to write, iclass 22, count 2 2006.257.05:01:28.56#ibcon#wrote, iclass 22, count 2 2006.257.05:01:28.56#ibcon#about to read 3, iclass 22, count 2 2006.257.05:01:28.59#ibcon#read 3, iclass 22, count 2 2006.257.05:01:28.59#ibcon#about to read 4, iclass 22, count 2 2006.257.05:01:28.59#ibcon#read 4, iclass 22, count 2 2006.257.05:01:28.59#ibcon#about to read 5, iclass 22, count 2 2006.257.05:01:28.59#ibcon#read 5, iclass 22, count 2 2006.257.05:01:28.59#ibcon#about to read 6, iclass 22, count 2 2006.257.05:01:28.59#ibcon#read 6, iclass 22, count 2 2006.257.05:01:28.59#ibcon#end of sib2, iclass 22, count 2 2006.257.05:01:28.59#ibcon#*after write, iclass 22, count 2 2006.257.05:01:28.59#ibcon#*before return 0, iclass 22, count 2 2006.257.05:01:28.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:28.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:01:28.59#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.05:01:28.59#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:28.59#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:28.71#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:28.71#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:28.71#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:01:28.71#ibcon#first serial, iclass 22, count 0 2006.257.05:01:28.71#ibcon#enter sib2, iclass 22, count 0 2006.257.05:01:28.71#ibcon#flushed, iclass 22, count 0 2006.257.05:01:28.71#ibcon#about to write, iclass 22, count 0 2006.257.05:01:28.71#ibcon#wrote, iclass 22, count 0 2006.257.05:01:28.71#ibcon#about to read 3, iclass 22, count 0 2006.257.05:01:28.73#ibcon#read 3, iclass 22, count 0 2006.257.05:01:28.73#ibcon#about to read 4, iclass 22, count 0 2006.257.05:01:28.73#ibcon#read 4, iclass 22, count 0 2006.257.05:01:28.73#ibcon#about to read 5, iclass 22, count 0 2006.257.05:01:28.73#ibcon#read 5, iclass 22, count 0 2006.257.05:01:28.73#ibcon#about to read 6, iclass 22, count 0 2006.257.05:01:28.73#ibcon#read 6, iclass 22, count 0 2006.257.05:01:28.73#ibcon#end of sib2, iclass 22, count 0 2006.257.05:01:28.73#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:01:28.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:01:28.73#ibcon#[27=USB\r\n] 2006.257.05:01:28.73#ibcon#*before write, iclass 22, count 0 2006.257.05:01:28.73#ibcon#enter sib2, iclass 22, count 0 2006.257.05:01:28.73#ibcon#flushed, iclass 22, count 0 2006.257.05:01:28.73#ibcon#about to write, iclass 22, count 0 2006.257.05:01:28.73#ibcon#wrote, iclass 22, count 0 2006.257.05:01:28.73#ibcon#about to read 3, iclass 22, count 0 2006.257.05:01:28.76#ibcon#read 3, iclass 22, count 0 2006.257.05:01:28.76#ibcon#about to read 4, iclass 22, count 0 2006.257.05:01:28.76#ibcon#read 4, iclass 22, count 0 2006.257.05:01:28.76#ibcon#about to read 5, iclass 22, count 0 2006.257.05:01:28.76#ibcon#read 5, iclass 22, count 0 2006.257.05:01:28.76#ibcon#about to read 6, iclass 22, count 0 2006.257.05:01:28.76#ibcon#read 6, iclass 22, count 0 2006.257.05:01:28.76#ibcon#end of sib2, iclass 22, count 0 2006.257.05:01:28.76#ibcon#*after write, iclass 22, count 0 2006.257.05:01:28.76#ibcon#*before return 0, iclass 22, count 0 2006.257.05:01:28.76#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:28.76#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:01:28.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:01:28.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:01:28.76$vck44/vblo=3,649.99 2006.257.05:01:28.76#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.05:01:28.76#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.05:01:28.76#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:28.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:28.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:28.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:28.76#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:01:28.76#ibcon#first serial, iclass 24, count 0 2006.257.05:01:28.76#ibcon#enter sib2, iclass 24, count 0 2006.257.05:01:28.76#ibcon#flushed, iclass 24, count 0 2006.257.05:01:28.76#ibcon#about to write, iclass 24, count 0 2006.257.05:01:28.76#ibcon#wrote, iclass 24, count 0 2006.257.05:01:28.76#ibcon#about to read 3, iclass 24, count 0 2006.257.05:01:28.78#ibcon#read 3, iclass 24, count 0 2006.257.05:01:28.78#ibcon#about to read 4, iclass 24, count 0 2006.257.05:01:28.78#ibcon#read 4, iclass 24, count 0 2006.257.05:01:28.78#ibcon#about to read 5, iclass 24, count 0 2006.257.05:01:28.78#ibcon#read 5, iclass 24, count 0 2006.257.05:01:28.78#ibcon#about to read 6, iclass 24, count 0 2006.257.05:01:28.78#ibcon#read 6, iclass 24, count 0 2006.257.05:01:28.78#ibcon#end of sib2, iclass 24, count 0 2006.257.05:01:28.78#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:01:28.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:01:28.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:01:28.78#ibcon#*before write, iclass 24, count 0 2006.257.05:01:28.78#ibcon#enter sib2, iclass 24, count 0 2006.257.05:01:28.78#ibcon#flushed, iclass 24, count 0 2006.257.05:01:28.78#ibcon#about to write, iclass 24, count 0 2006.257.05:01:28.78#ibcon#wrote, iclass 24, count 0 2006.257.05:01:28.78#ibcon#about to read 3, iclass 24, count 0 2006.257.05:01:28.82#ibcon#read 3, iclass 24, count 0 2006.257.05:01:28.82#ibcon#about to read 4, iclass 24, count 0 2006.257.05:01:28.82#ibcon#read 4, iclass 24, count 0 2006.257.05:01:28.82#ibcon#about to read 5, iclass 24, count 0 2006.257.05:01:28.82#ibcon#read 5, iclass 24, count 0 2006.257.05:01:28.82#ibcon#about to read 6, iclass 24, count 0 2006.257.05:01:28.82#ibcon#read 6, iclass 24, count 0 2006.257.05:01:28.82#ibcon#end of sib2, iclass 24, count 0 2006.257.05:01:28.82#ibcon#*after write, iclass 24, count 0 2006.257.05:01:28.82#ibcon#*before return 0, iclass 24, count 0 2006.257.05:01:28.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:28.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:01:28.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:01:28.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:01:28.82$vck44/vb=3,4 2006.257.05:01:28.82#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.05:01:28.82#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.05:01:28.82#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:28.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:28.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:28.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:28.88#ibcon#enter wrdev, iclass 26, count 2 2006.257.05:01:28.88#ibcon#first serial, iclass 26, count 2 2006.257.05:01:28.88#ibcon#enter sib2, iclass 26, count 2 2006.257.05:01:28.88#ibcon#flushed, iclass 26, count 2 2006.257.05:01:28.88#ibcon#about to write, iclass 26, count 2 2006.257.05:01:28.88#ibcon#wrote, iclass 26, count 2 2006.257.05:01:28.88#ibcon#about to read 3, iclass 26, count 2 2006.257.05:01:28.90#ibcon#read 3, iclass 26, count 2 2006.257.05:01:28.90#ibcon#about to read 4, iclass 26, count 2 2006.257.05:01:28.90#ibcon#read 4, iclass 26, count 2 2006.257.05:01:28.90#ibcon#about to read 5, iclass 26, count 2 2006.257.05:01:28.90#ibcon#read 5, iclass 26, count 2 2006.257.05:01:28.90#ibcon#about to read 6, iclass 26, count 2 2006.257.05:01:28.90#ibcon#read 6, iclass 26, count 2 2006.257.05:01:28.90#ibcon#end of sib2, iclass 26, count 2 2006.257.05:01:28.90#ibcon#*mode == 0, iclass 26, count 2 2006.257.05:01:28.90#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.05:01:28.90#ibcon#[27=AT03-04\r\n] 2006.257.05:01:28.90#ibcon#*before write, iclass 26, count 2 2006.257.05:01:28.90#ibcon#enter sib2, iclass 26, count 2 2006.257.05:01:28.90#ibcon#flushed, iclass 26, count 2 2006.257.05:01:28.90#ibcon#about to write, iclass 26, count 2 2006.257.05:01:28.90#ibcon#wrote, iclass 26, count 2 2006.257.05:01:28.90#ibcon#about to read 3, iclass 26, count 2 2006.257.05:01:28.93#ibcon#read 3, iclass 26, count 2 2006.257.05:01:28.93#ibcon#about to read 4, iclass 26, count 2 2006.257.05:01:28.93#ibcon#read 4, iclass 26, count 2 2006.257.05:01:28.93#ibcon#about to read 5, iclass 26, count 2 2006.257.05:01:28.93#ibcon#read 5, iclass 26, count 2 2006.257.05:01:28.93#ibcon#about to read 6, iclass 26, count 2 2006.257.05:01:28.93#ibcon#read 6, iclass 26, count 2 2006.257.05:01:28.93#ibcon#end of sib2, iclass 26, count 2 2006.257.05:01:28.93#ibcon#*after write, iclass 26, count 2 2006.257.05:01:28.93#ibcon#*before return 0, iclass 26, count 2 2006.257.05:01:28.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:28.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:01:28.93#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.05:01:28.93#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:28.93#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:29.05#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:29.05#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:29.05#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:01:29.05#ibcon#first serial, iclass 26, count 0 2006.257.05:01:29.05#ibcon#enter sib2, iclass 26, count 0 2006.257.05:01:29.05#ibcon#flushed, iclass 26, count 0 2006.257.05:01:29.05#ibcon#about to write, iclass 26, count 0 2006.257.05:01:29.05#ibcon#wrote, iclass 26, count 0 2006.257.05:01:29.05#ibcon#about to read 3, iclass 26, count 0 2006.257.05:01:29.07#ibcon#read 3, iclass 26, count 0 2006.257.05:01:29.07#ibcon#about to read 4, iclass 26, count 0 2006.257.05:01:29.07#ibcon#read 4, iclass 26, count 0 2006.257.05:01:29.07#ibcon#about to read 5, iclass 26, count 0 2006.257.05:01:29.07#ibcon#read 5, iclass 26, count 0 2006.257.05:01:29.07#ibcon#about to read 6, iclass 26, count 0 2006.257.05:01:29.07#ibcon#read 6, iclass 26, count 0 2006.257.05:01:29.07#ibcon#end of sib2, iclass 26, count 0 2006.257.05:01:29.07#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:01:29.07#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:01:29.07#ibcon#[27=USB\r\n] 2006.257.05:01:29.07#ibcon#*before write, iclass 26, count 0 2006.257.05:01:29.07#ibcon#enter sib2, iclass 26, count 0 2006.257.05:01:29.07#ibcon#flushed, iclass 26, count 0 2006.257.05:01:29.07#ibcon#about to write, iclass 26, count 0 2006.257.05:01:29.07#ibcon#wrote, iclass 26, count 0 2006.257.05:01:29.07#ibcon#about to read 3, iclass 26, count 0 2006.257.05:01:29.10#ibcon#read 3, iclass 26, count 0 2006.257.05:01:29.10#ibcon#about to read 4, iclass 26, count 0 2006.257.05:01:29.10#ibcon#read 4, iclass 26, count 0 2006.257.05:01:29.10#ibcon#about to read 5, iclass 26, count 0 2006.257.05:01:29.10#ibcon#read 5, iclass 26, count 0 2006.257.05:01:29.10#ibcon#about to read 6, iclass 26, count 0 2006.257.05:01:29.10#ibcon#read 6, iclass 26, count 0 2006.257.05:01:29.10#ibcon#end of sib2, iclass 26, count 0 2006.257.05:01:29.10#ibcon#*after write, iclass 26, count 0 2006.257.05:01:29.10#ibcon#*before return 0, iclass 26, count 0 2006.257.05:01:29.10#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:29.10#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:01:29.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:01:29.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:01:29.10$vck44/vblo=4,679.99 2006.257.05:01:29.10#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.05:01:29.10#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.05:01:29.10#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:29.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:29.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:29.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:29.10#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:01:29.10#ibcon#first serial, iclass 28, count 0 2006.257.05:01:29.10#ibcon#enter sib2, iclass 28, count 0 2006.257.05:01:29.10#ibcon#flushed, iclass 28, count 0 2006.257.05:01:29.10#ibcon#about to write, iclass 28, count 0 2006.257.05:01:29.10#ibcon#wrote, iclass 28, count 0 2006.257.05:01:29.10#ibcon#about to read 3, iclass 28, count 0 2006.257.05:01:29.12#ibcon#read 3, iclass 28, count 0 2006.257.05:01:29.12#ibcon#about to read 4, iclass 28, count 0 2006.257.05:01:29.12#ibcon#read 4, iclass 28, count 0 2006.257.05:01:29.12#ibcon#about to read 5, iclass 28, count 0 2006.257.05:01:29.12#ibcon#read 5, iclass 28, count 0 2006.257.05:01:29.12#ibcon#about to read 6, iclass 28, count 0 2006.257.05:01:29.12#ibcon#read 6, iclass 28, count 0 2006.257.05:01:29.12#ibcon#end of sib2, iclass 28, count 0 2006.257.05:01:29.12#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:01:29.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:01:29.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:01:29.12#ibcon#*before write, iclass 28, count 0 2006.257.05:01:29.12#ibcon#enter sib2, iclass 28, count 0 2006.257.05:01:29.12#ibcon#flushed, iclass 28, count 0 2006.257.05:01:29.12#ibcon#about to write, iclass 28, count 0 2006.257.05:01:29.12#ibcon#wrote, iclass 28, count 0 2006.257.05:01:29.12#ibcon#about to read 3, iclass 28, count 0 2006.257.05:01:29.16#ibcon#read 3, iclass 28, count 0 2006.257.05:01:29.16#ibcon#about to read 4, iclass 28, count 0 2006.257.05:01:29.16#ibcon#read 4, iclass 28, count 0 2006.257.05:01:29.16#ibcon#about to read 5, iclass 28, count 0 2006.257.05:01:29.16#ibcon#read 5, iclass 28, count 0 2006.257.05:01:29.16#ibcon#about to read 6, iclass 28, count 0 2006.257.05:01:29.16#ibcon#read 6, iclass 28, count 0 2006.257.05:01:29.16#ibcon#end of sib2, iclass 28, count 0 2006.257.05:01:29.16#ibcon#*after write, iclass 28, count 0 2006.257.05:01:29.16#ibcon#*before return 0, iclass 28, count 0 2006.257.05:01:29.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:29.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:01:29.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:01:29.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:01:29.16$vck44/vb=4,5 2006.257.05:01:29.16#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.05:01:29.16#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.05:01:29.16#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:29.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:29.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:29.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:29.22#ibcon#enter wrdev, iclass 30, count 2 2006.257.05:01:29.22#ibcon#first serial, iclass 30, count 2 2006.257.05:01:29.22#ibcon#enter sib2, iclass 30, count 2 2006.257.05:01:29.22#ibcon#flushed, iclass 30, count 2 2006.257.05:01:29.22#ibcon#about to write, iclass 30, count 2 2006.257.05:01:29.22#ibcon#wrote, iclass 30, count 2 2006.257.05:01:29.22#ibcon#about to read 3, iclass 30, count 2 2006.257.05:01:29.24#ibcon#read 3, iclass 30, count 2 2006.257.05:01:29.24#ibcon#about to read 4, iclass 30, count 2 2006.257.05:01:29.24#ibcon#read 4, iclass 30, count 2 2006.257.05:01:29.24#ibcon#about to read 5, iclass 30, count 2 2006.257.05:01:29.24#ibcon#read 5, iclass 30, count 2 2006.257.05:01:29.24#ibcon#about to read 6, iclass 30, count 2 2006.257.05:01:29.24#ibcon#read 6, iclass 30, count 2 2006.257.05:01:29.24#ibcon#end of sib2, iclass 30, count 2 2006.257.05:01:29.24#ibcon#*mode == 0, iclass 30, count 2 2006.257.05:01:29.24#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.05:01:29.24#ibcon#[27=AT04-05\r\n] 2006.257.05:01:29.24#ibcon#*before write, iclass 30, count 2 2006.257.05:01:29.24#ibcon#enter sib2, iclass 30, count 2 2006.257.05:01:29.24#ibcon#flushed, iclass 30, count 2 2006.257.05:01:29.24#ibcon#about to write, iclass 30, count 2 2006.257.05:01:29.24#ibcon#wrote, iclass 30, count 2 2006.257.05:01:29.24#ibcon#about to read 3, iclass 30, count 2 2006.257.05:01:29.27#ibcon#read 3, iclass 30, count 2 2006.257.05:01:29.27#ibcon#about to read 4, iclass 30, count 2 2006.257.05:01:29.27#ibcon#read 4, iclass 30, count 2 2006.257.05:01:29.27#ibcon#about to read 5, iclass 30, count 2 2006.257.05:01:29.27#ibcon#read 5, iclass 30, count 2 2006.257.05:01:29.27#ibcon#about to read 6, iclass 30, count 2 2006.257.05:01:29.27#ibcon#read 6, iclass 30, count 2 2006.257.05:01:29.27#ibcon#end of sib2, iclass 30, count 2 2006.257.05:01:29.27#ibcon#*after write, iclass 30, count 2 2006.257.05:01:29.27#ibcon#*before return 0, iclass 30, count 2 2006.257.05:01:29.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:29.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:01:29.27#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.05:01:29.27#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:29.27#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:29.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:29.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:29.39#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:01:29.39#ibcon#first serial, iclass 30, count 0 2006.257.05:01:29.39#ibcon#enter sib2, iclass 30, count 0 2006.257.05:01:29.39#ibcon#flushed, iclass 30, count 0 2006.257.05:01:29.39#ibcon#about to write, iclass 30, count 0 2006.257.05:01:29.39#ibcon#wrote, iclass 30, count 0 2006.257.05:01:29.39#ibcon#about to read 3, iclass 30, count 0 2006.257.05:01:29.41#ibcon#read 3, iclass 30, count 0 2006.257.05:01:29.41#ibcon#about to read 4, iclass 30, count 0 2006.257.05:01:29.41#ibcon#read 4, iclass 30, count 0 2006.257.05:01:29.41#ibcon#about to read 5, iclass 30, count 0 2006.257.05:01:29.41#ibcon#read 5, iclass 30, count 0 2006.257.05:01:29.41#ibcon#about to read 6, iclass 30, count 0 2006.257.05:01:29.41#ibcon#read 6, iclass 30, count 0 2006.257.05:01:29.41#ibcon#end of sib2, iclass 30, count 0 2006.257.05:01:29.41#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:01:29.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:01:29.41#ibcon#[27=USB\r\n] 2006.257.05:01:29.41#ibcon#*before write, iclass 30, count 0 2006.257.05:01:29.41#ibcon#enter sib2, iclass 30, count 0 2006.257.05:01:29.41#ibcon#flushed, iclass 30, count 0 2006.257.05:01:29.41#ibcon#about to write, iclass 30, count 0 2006.257.05:01:29.41#ibcon#wrote, iclass 30, count 0 2006.257.05:01:29.41#ibcon#about to read 3, iclass 30, count 0 2006.257.05:01:29.44#ibcon#read 3, iclass 30, count 0 2006.257.05:01:29.44#ibcon#about to read 4, iclass 30, count 0 2006.257.05:01:29.44#ibcon#read 4, iclass 30, count 0 2006.257.05:01:29.44#ibcon#about to read 5, iclass 30, count 0 2006.257.05:01:29.44#ibcon#read 5, iclass 30, count 0 2006.257.05:01:29.44#ibcon#about to read 6, iclass 30, count 0 2006.257.05:01:29.44#ibcon#read 6, iclass 30, count 0 2006.257.05:01:29.44#ibcon#end of sib2, iclass 30, count 0 2006.257.05:01:29.44#ibcon#*after write, iclass 30, count 0 2006.257.05:01:29.44#ibcon#*before return 0, iclass 30, count 0 2006.257.05:01:29.44#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:29.44#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:01:29.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:01:29.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:01:29.44$vck44/vblo=5,709.99 2006.257.05:01:29.44#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.05:01:29.44#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.05:01:29.44#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:29.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:01:29.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:01:29.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:01:29.44#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:01:29.44#ibcon#first serial, iclass 32, count 0 2006.257.05:01:29.44#ibcon#enter sib2, iclass 32, count 0 2006.257.05:01:29.44#ibcon#flushed, iclass 32, count 0 2006.257.05:01:29.44#ibcon#about to write, iclass 32, count 0 2006.257.05:01:29.44#ibcon#wrote, iclass 32, count 0 2006.257.05:01:29.44#ibcon#about to read 3, iclass 32, count 0 2006.257.05:01:29.46#ibcon#read 3, iclass 32, count 0 2006.257.05:01:29.46#ibcon#about to read 4, iclass 32, count 0 2006.257.05:01:29.46#ibcon#read 4, iclass 32, count 0 2006.257.05:01:29.46#ibcon#about to read 5, iclass 32, count 0 2006.257.05:01:29.46#ibcon#read 5, iclass 32, count 0 2006.257.05:01:29.46#ibcon#about to read 6, iclass 32, count 0 2006.257.05:01:29.46#ibcon#read 6, iclass 32, count 0 2006.257.05:01:29.46#ibcon#end of sib2, iclass 32, count 0 2006.257.05:01:29.46#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:01:29.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:01:29.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:01:29.46#ibcon#*before write, iclass 32, count 0 2006.257.05:01:29.46#ibcon#enter sib2, iclass 32, count 0 2006.257.05:01:29.46#ibcon#flushed, iclass 32, count 0 2006.257.05:01:29.46#ibcon#about to write, iclass 32, count 0 2006.257.05:01:29.46#ibcon#wrote, iclass 32, count 0 2006.257.05:01:29.46#ibcon#about to read 3, iclass 32, count 0 2006.257.05:01:29.50#ibcon#read 3, iclass 32, count 0 2006.257.05:01:29.50#ibcon#about to read 4, iclass 32, count 0 2006.257.05:01:29.50#ibcon#read 4, iclass 32, count 0 2006.257.05:01:29.50#ibcon#about to read 5, iclass 32, count 0 2006.257.05:01:29.50#ibcon#read 5, iclass 32, count 0 2006.257.05:01:29.50#ibcon#about to read 6, iclass 32, count 0 2006.257.05:01:29.50#ibcon#read 6, iclass 32, count 0 2006.257.05:01:29.50#ibcon#end of sib2, iclass 32, count 0 2006.257.05:01:29.50#ibcon#*after write, iclass 32, count 0 2006.257.05:01:29.50#ibcon#*before return 0, iclass 32, count 0 2006.257.05:01:29.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:01:29.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:01:29.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:01:29.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:01:29.50$vck44/vb=5,4 2006.257.05:01:29.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.05:01:29.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.05:01:29.50#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:29.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:01:29.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:01:29.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:01:29.56#ibcon#enter wrdev, iclass 34, count 2 2006.257.05:01:29.56#ibcon#first serial, iclass 34, count 2 2006.257.05:01:29.56#ibcon#enter sib2, iclass 34, count 2 2006.257.05:01:29.56#ibcon#flushed, iclass 34, count 2 2006.257.05:01:29.56#ibcon#about to write, iclass 34, count 2 2006.257.05:01:29.56#ibcon#wrote, iclass 34, count 2 2006.257.05:01:29.56#ibcon#about to read 3, iclass 34, count 2 2006.257.05:01:29.58#ibcon#read 3, iclass 34, count 2 2006.257.05:01:29.58#ibcon#about to read 4, iclass 34, count 2 2006.257.05:01:29.58#ibcon#read 4, iclass 34, count 2 2006.257.05:01:29.58#ibcon#about to read 5, iclass 34, count 2 2006.257.05:01:29.58#ibcon#read 5, iclass 34, count 2 2006.257.05:01:29.58#ibcon#about to read 6, iclass 34, count 2 2006.257.05:01:29.58#ibcon#read 6, iclass 34, count 2 2006.257.05:01:29.58#ibcon#end of sib2, iclass 34, count 2 2006.257.05:01:29.58#ibcon#*mode == 0, iclass 34, count 2 2006.257.05:01:29.58#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.05:01:29.58#ibcon#[27=AT05-04\r\n] 2006.257.05:01:29.58#ibcon#*before write, iclass 34, count 2 2006.257.05:01:29.58#ibcon#enter sib2, iclass 34, count 2 2006.257.05:01:29.58#ibcon#flushed, iclass 34, count 2 2006.257.05:01:29.58#ibcon#about to write, iclass 34, count 2 2006.257.05:01:29.58#ibcon#wrote, iclass 34, count 2 2006.257.05:01:29.58#ibcon#about to read 3, iclass 34, count 2 2006.257.05:01:29.61#ibcon#read 3, iclass 34, count 2 2006.257.05:01:29.61#ibcon#about to read 4, iclass 34, count 2 2006.257.05:01:29.61#ibcon#read 4, iclass 34, count 2 2006.257.05:01:29.61#ibcon#about to read 5, iclass 34, count 2 2006.257.05:01:29.61#ibcon#read 5, iclass 34, count 2 2006.257.05:01:29.61#ibcon#about to read 6, iclass 34, count 2 2006.257.05:01:29.61#ibcon#read 6, iclass 34, count 2 2006.257.05:01:29.61#ibcon#end of sib2, iclass 34, count 2 2006.257.05:01:29.61#ibcon#*after write, iclass 34, count 2 2006.257.05:01:29.61#ibcon#*before return 0, iclass 34, count 2 2006.257.05:01:29.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:01:29.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:01:29.61#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.05:01:29.61#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:29.61#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:01:29.73#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:01:29.73#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:01:29.73#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:01:29.73#ibcon#first serial, iclass 34, count 0 2006.257.05:01:29.73#ibcon#enter sib2, iclass 34, count 0 2006.257.05:01:29.73#ibcon#flushed, iclass 34, count 0 2006.257.05:01:29.73#ibcon#about to write, iclass 34, count 0 2006.257.05:01:29.73#ibcon#wrote, iclass 34, count 0 2006.257.05:01:29.73#ibcon#about to read 3, iclass 34, count 0 2006.257.05:01:29.75#ibcon#read 3, iclass 34, count 0 2006.257.05:01:29.75#ibcon#about to read 4, iclass 34, count 0 2006.257.05:01:29.75#ibcon#read 4, iclass 34, count 0 2006.257.05:01:29.75#ibcon#about to read 5, iclass 34, count 0 2006.257.05:01:29.75#ibcon#read 5, iclass 34, count 0 2006.257.05:01:29.75#ibcon#about to read 6, iclass 34, count 0 2006.257.05:01:29.75#ibcon#read 6, iclass 34, count 0 2006.257.05:01:29.75#ibcon#end of sib2, iclass 34, count 0 2006.257.05:01:29.75#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:01:29.75#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:01:29.75#ibcon#[27=USB\r\n] 2006.257.05:01:29.75#ibcon#*before write, iclass 34, count 0 2006.257.05:01:29.75#ibcon#enter sib2, iclass 34, count 0 2006.257.05:01:29.75#ibcon#flushed, iclass 34, count 0 2006.257.05:01:29.75#ibcon#about to write, iclass 34, count 0 2006.257.05:01:29.75#ibcon#wrote, iclass 34, count 0 2006.257.05:01:29.75#ibcon#about to read 3, iclass 34, count 0 2006.257.05:01:29.78#ibcon#read 3, iclass 34, count 0 2006.257.05:01:29.78#ibcon#about to read 4, iclass 34, count 0 2006.257.05:01:29.78#ibcon#read 4, iclass 34, count 0 2006.257.05:01:29.78#ibcon#about to read 5, iclass 34, count 0 2006.257.05:01:29.78#ibcon#read 5, iclass 34, count 0 2006.257.05:01:29.78#ibcon#about to read 6, iclass 34, count 0 2006.257.05:01:29.78#ibcon#read 6, iclass 34, count 0 2006.257.05:01:29.78#ibcon#end of sib2, iclass 34, count 0 2006.257.05:01:29.78#ibcon#*after write, iclass 34, count 0 2006.257.05:01:29.78#ibcon#*before return 0, iclass 34, count 0 2006.257.05:01:29.78#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:01:29.78#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:01:29.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:01:29.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:01:29.78$vck44/vblo=6,719.99 2006.257.05:01:29.78#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.05:01:29.78#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.05:01:29.78#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:29.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:29.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:29.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:29.78#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:01:29.78#ibcon#first serial, iclass 36, count 0 2006.257.05:01:29.78#ibcon#enter sib2, iclass 36, count 0 2006.257.05:01:29.78#ibcon#flushed, iclass 36, count 0 2006.257.05:01:29.78#ibcon#about to write, iclass 36, count 0 2006.257.05:01:29.78#ibcon#wrote, iclass 36, count 0 2006.257.05:01:29.78#ibcon#about to read 3, iclass 36, count 0 2006.257.05:01:29.80#ibcon#read 3, iclass 36, count 0 2006.257.05:01:29.80#ibcon#about to read 4, iclass 36, count 0 2006.257.05:01:29.80#ibcon#read 4, iclass 36, count 0 2006.257.05:01:29.80#ibcon#about to read 5, iclass 36, count 0 2006.257.05:01:29.80#ibcon#read 5, iclass 36, count 0 2006.257.05:01:29.80#ibcon#about to read 6, iclass 36, count 0 2006.257.05:01:29.80#ibcon#read 6, iclass 36, count 0 2006.257.05:01:29.80#ibcon#end of sib2, iclass 36, count 0 2006.257.05:01:29.80#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:01:29.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:01:29.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:01:29.80#ibcon#*before write, iclass 36, count 0 2006.257.05:01:29.80#ibcon#enter sib2, iclass 36, count 0 2006.257.05:01:29.80#ibcon#flushed, iclass 36, count 0 2006.257.05:01:29.80#ibcon#about to write, iclass 36, count 0 2006.257.05:01:29.80#ibcon#wrote, iclass 36, count 0 2006.257.05:01:29.80#ibcon#about to read 3, iclass 36, count 0 2006.257.05:01:29.84#ibcon#read 3, iclass 36, count 0 2006.257.05:01:29.84#ibcon#about to read 4, iclass 36, count 0 2006.257.05:01:29.84#ibcon#read 4, iclass 36, count 0 2006.257.05:01:29.84#ibcon#about to read 5, iclass 36, count 0 2006.257.05:01:29.84#ibcon#read 5, iclass 36, count 0 2006.257.05:01:29.84#ibcon#about to read 6, iclass 36, count 0 2006.257.05:01:29.84#ibcon#read 6, iclass 36, count 0 2006.257.05:01:29.84#ibcon#end of sib2, iclass 36, count 0 2006.257.05:01:29.84#ibcon#*after write, iclass 36, count 0 2006.257.05:01:29.84#ibcon#*before return 0, iclass 36, count 0 2006.257.05:01:29.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:29.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:01:29.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:01:29.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:01:29.84$vck44/vb=6,4 2006.257.05:01:29.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.05:01:29.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.05:01:29.84#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:29.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:29.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:29.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:29.90#ibcon#enter wrdev, iclass 38, count 2 2006.257.05:01:29.90#ibcon#first serial, iclass 38, count 2 2006.257.05:01:29.90#ibcon#enter sib2, iclass 38, count 2 2006.257.05:01:29.90#ibcon#flushed, iclass 38, count 2 2006.257.05:01:29.90#ibcon#about to write, iclass 38, count 2 2006.257.05:01:29.90#ibcon#wrote, iclass 38, count 2 2006.257.05:01:29.90#ibcon#about to read 3, iclass 38, count 2 2006.257.05:01:29.92#ibcon#read 3, iclass 38, count 2 2006.257.05:01:29.92#ibcon#about to read 4, iclass 38, count 2 2006.257.05:01:29.92#ibcon#read 4, iclass 38, count 2 2006.257.05:01:29.92#ibcon#about to read 5, iclass 38, count 2 2006.257.05:01:29.92#ibcon#read 5, iclass 38, count 2 2006.257.05:01:29.92#ibcon#about to read 6, iclass 38, count 2 2006.257.05:01:29.92#ibcon#read 6, iclass 38, count 2 2006.257.05:01:29.92#ibcon#end of sib2, iclass 38, count 2 2006.257.05:01:29.92#ibcon#*mode == 0, iclass 38, count 2 2006.257.05:01:29.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.05:01:29.92#ibcon#[27=AT06-04\r\n] 2006.257.05:01:29.92#ibcon#*before write, iclass 38, count 2 2006.257.05:01:29.92#ibcon#enter sib2, iclass 38, count 2 2006.257.05:01:29.92#ibcon#flushed, iclass 38, count 2 2006.257.05:01:29.92#ibcon#about to write, iclass 38, count 2 2006.257.05:01:29.92#ibcon#wrote, iclass 38, count 2 2006.257.05:01:29.92#ibcon#about to read 3, iclass 38, count 2 2006.257.05:01:29.95#ibcon#read 3, iclass 38, count 2 2006.257.05:01:29.95#ibcon#about to read 4, iclass 38, count 2 2006.257.05:01:29.95#ibcon#read 4, iclass 38, count 2 2006.257.05:01:29.95#ibcon#about to read 5, iclass 38, count 2 2006.257.05:01:29.95#ibcon#read 5, iclass 38, count 2 2006.257.05:01:29.95#ibcon#about to read 6, iclass 38, count 2 2006.257.05:01:29.95#ibcon#read 6, iclass 38, count 2 2006.257.05:01:29.95#ibcon#end of sib2, iclass 38, count 2 2006.257.05:01:29.95#ibcon#*after write, iclass 38, count 2 2006.257.05:01:29.95#ibcon#*before return 0, iclass 38, count 2 2006.257.05:01:29.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:29.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:01:29.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.05:01:29.95#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:29.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:30.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:30.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:30.07#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:01:30.07#ibcon#first serial, iclass 38, count 0 2006.257.05:01:30.07#ibcon#enter sib2, iclass 38, count 0 2006.257.05:01:30.07#ibcon#flushed, iclass 38, count 0 2006.257.05:01:30.07#ibcon#about to write, iclass 38, count 0 2006.257.05:01:30.07#ibcon#wrote, iclass 38, count 0 2006.257.05:01:30.07#ibcon#about to read 3, iclass 38, count 0 2006.257.05:01:30.09#ibcon#read 3, iclass 38, count 0 2006.257.05:01:30.09#ibcon#about to read 4, iclass 38, count 0 2006.257.05:01:30.09#ibcon#read 4, iclass 38, count 0 2006.257.05:01:30.09#ibcon#about to read 5, iclass 38, count 0 2006.257.05:01:30.09#ibcon#read 5, iclass 38, count 0 2006.257.05:01:30.09#ibcon#about to read 6, iclass 38, count 0 2006.257.05:01:30.09#ibcon#read 6, iclass 38, count 0 2006.257.05:01:30.09#ibcon#end of sib2, iclass 38, count 0 2006.257.05:01:30.09#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:01:30.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:01:30.09#ibcon#[27=USB\r\n] 2006.257.05:01:30.09#ibcon#*before write, iclass 38, count 0 2006.257.05:01:30.09#ibcon#enter sib2, iclass 38, count 0 2006.257.05:01:30.09#ibcon#flushed, iclass 38, count 0 2006.257.05:01:30.09#ibcon#about to write, iclass 38, count 0 2006.257.05:01:30.09#ibcon#wrote, iclass 38, count 0 2006.257.05:01:30.09#ibcon#about to read 3, iclass 38, count 0 2006.257.05:01:30.12#ibcon#read 3, iclass 38, count 0 2006.257.05:01:30.12#ibcon#about to read 4, iclass 38, count 0 2006.257.05:01:30.12#ibcon#read 4, iclass 38, count 0 2006.257.05:01:30.12#ibcon#about to read 5, iclass 38, count 0 2006.257.05:01:30.12#ibcon#read 5, iclass 38, count 0 2006.257.05:01:30.12#ibcon#about to read 6, iclass 38, count 0 2006.257.05:01:30.12#ibcon#read 6, iclass 38, count 0 2006.257.05:01:30.12#ibcon#end of sib2, iclass 38, count 0 2006.257.05:01:30.12#ibcon#*after write, iclass 38, count 0 2006.257.05:01:30.12#ibcon#*before return 0, iclass 38, count 0 2006.257.05:01:30.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:30.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:01:30.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:01:30.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:01:30.12$vck44/vblo=7,734.99 2006.257.05:01:30.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.05:01:30.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.05:01:30.12#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:30.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:30.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:30.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:30.12#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:01:30.12#ibcon#first serial, iclass 40, count 0 2006.257.05:01:30.12#ibcon#enter sib2, iclass 40, count 0 2006.257.05:01:30.12#ibcon#flushed, iclass 40, count 0 2006.257.05:01:30.12#ibcon#about to write, iclass 40, count 0 2006.257.05:01:30.12#ibcon#wrote, iclass 40, count 0 2006.257.05:01:30.12#ibcon#about to read 3, iclass 40, count 0 2006.257.05:01:30.14#ibcon#read 3, iclass 40, count 0 2006.257.05:01:30.14#ibcon#about to read 4, iclass 40, count 0 2006.257.05:01:30.14#ibcon#read 4, iclass 40, count 0 2006.257.05:01:30.14#ibcon#about to read 5, iclass 40, count 0 2006.257.05:01:30.14#ibcon#read 5, iclass 40, count 0 2006.257.05:01:30.14#ibcon#about to read 6, iclass 40, count 0 2006.257.05:01:30.14#ibcon#read 6, iclass 40, count 0 2006.257.05:01:30.14#ibcon#end of sib2, iclass 40, count 0 2006.257.05:01:30.14#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:01:30.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:01:30.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:01:30.14#ibcon#*before write, iclass 40, count 0 2006.257.05:01:30.14#ibcon#enter sib2, iclass 40, count 0 2006.257.05:01:30.14#ibcon#flushed, iclass 40, count 0 2006.257.05:01:30.14#ibcon#about to write, iclass 40, count 0 2006.257.05:01:30.14#ibcon#wrote, iclass 40, count 0 2006.257.05:01:30.14#ibcon#about to read 3, iclass 40, count 0 2006.257.05:01:30.18#ibcon#read 3, iclass 40, count 0 2006.257.05:01:30.18#ibcon#about to read 4, iclass 40, count 0 2006.257.05:01:30.18#ibcon#read 4, iclass 40, count 0 2006.257.05:01:30.18#ibcon#about to read 5, iclass 40, count 0 2006.257.05:01:30.18#ibcon#read 5, iclass 40, count 0 2006.257.05:01:30.18#ibcon#about to read 6, iclass 40, count 0 2006.257.05:01:30.18#ibcon#read 6, iclass 40, count 0 2006.257.05:01:30.18#ibcon#end of sib2, iclass 40, count 0 2006.257.05:01:30.18#ibcon#*after write, iclass 40, count 0 2006.257.05:01:30.18#ibcon#*before return 0, iclass 40, count 0 2006.257.05:01:30.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:30.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:01:30.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:01:30.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:01:30.18$vck44/vb=7,4 2006.257.05:01:30.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.05:01:30.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.05:01:30.18#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:30.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:30.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:30.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:30.24#ibcon#enter wrdev, iclass 4, count 2 2006.257.05:01:30.24#ibcon#first serial, iclass 4, count 2 2006.257.05:01:30.24#ibcon#enter sib2, iclass 4, count 2 2006.257.05:01:30.24#ibcon#flushed, iclass 4, count 2 2006.257.05:01:30.24#ibcon#about to write, iclass 4, count 2 2006.257.05:01:30.24#ibcon#wrote, iclass 4, count 2 2006.257.05:01:30.24#ibcon#about to read 3, iclass 4, count 2 2006.257.05:01:30.26#ibcon#read 3, iclass 4, count 2 2006.257.05:01:30.26#ibcon#about to read 4, iclass 4, count 2 2006.257.05:01:30.26#ibcon#read 4, iclass 4, count 2 2006.257.05:01:30.26#ibcon#about to read 5, iclass 4, count 2 2006.257.05:01:30.26#ibcon#read 5, iclass 4, count 2 2006.257.05:01:30.26#ibcon#about to read 6, iclass 4, count 2 2006.257.05:01:30.26#ibcon#read 6, iclass 4, count 2 2006.257.05:01:30.26#ibcon#end of sib2, iclass 4, count 2 2006.257.05:01:30.26#ibcon#*mode == 0, iclass 4, count 2 2006.257.05:01:30.26#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.05:01:30.26#ibcon#[27=AT07-04\r\n] 2006.257.05:01:30.26#ibcon#*before write, iclass 4, count 2 2006.257.05:01:30.26#ibcon#enter sib2, iclass 4, count 2 2006.257.05:01:30.26#ibcon#flushed, iclass 4, count 2 2006.257.05:01:30.26#ibcon#about to write, iclass 4, count 2 2006.257.05:01:30.26#ibcon#wrote, iclass 4, count 2 2006.257.05:01:30.26#ibcon#about to read 3, iclass 4, count 2 2006.257.05:01:30.29#ibcon#read 3, iclass 4, count 2 2006.257.05:01:30.29#ibcon#about to read 4, iclass 4, count 2 2006.257.05:01:30.29#ibcon#read 4, iclass 4, count 2 2006.257.05:01:30.29#ibcon#about to read 5, iclass 4, count 2 2006.257.05:01:30.29#ibcon#read 5, iclass 4, count 2 2006.257.05:01:30.29#ibcon#about to read 6, iclass 4, count 2 2006.257.05:01:30.29#ibcon#read 6, iclass 4, count 2 2006.257.05:01:30.29#ibcon#end of sib2, iclass 4, count 2 2006.257.05:01:30.29#ibcon#*after write, iclass 4, count 2 2006.257.05:01:30.29#ibcon#*before return 0, iclass 4, count 2 2006.257.05:01:30.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:30.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:01:30.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.05:01:30.29#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:30.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:30.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:30.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:30.41#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:01:30.41#ibcon#first serial, iclass 4, count 0 2006.257.05:01:30.41#ibcon#enter sib2, iclass 4, count 0 2006.257.05:01:30.41#ibcon#flushed, iclass 4, count 0 2006.257.05:01:30.41#ibcon#about to write, iclass 4, count 0 2006.257.05:01:30.41#ibcon#wrote, iclass 4, count 0 2006.257.05:01:30.41#ibcon#about to read 3, iclass 4, count 0 2006.257.05:01:30.43#ibcon#read 3, iclass 4, count 0 2006.257.05:01:30.43#ibcon#about to read 4, iclass 4, count 0 2006.257.05:01:30.43#ibcon#read 4, iclass 4, count 0 2006.257.05:01:30.43#ibcon#about to read 5, iclass 4, count 0 2006.257.05:01:30.43#ibcon#read 5, iclass 4, count 0 2006.257.05:01:30.43#ibcon#about to read 6, iclass 4, count 0 2006.257.05:01:30.43#ibcon#read 6, iclass 4, count 0 2006.257.05:01:30.43#ibcon#end of sib2, iclass 4, count 0 2006.257.05:01:30.43#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:01:30.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:01:30.43#ibcon#[27=USB\r\n] 2006.257.05:01:30.43#ibcon#*before write, iclass 4, count 0 2006.257.05:01:30.43#ibcon#enter sib2, iclass 4, count 0 2006.257.05:01:30.43#ibcon#flushed, iclass 4, count 0 2006.257.05:01:30.43#ibcon#about to write, iclass 4, count 0 2006.257.05:01:30.43#ibcon#wrote, iclass 4, count 0 2006.257.05:01:30.43#ibcon#about to read 3, iclass 4, count 0 2006.257.05:01:30.46#ibcon#read 3, iclass 4, count 0 2006.257.05:01:30.46#ibcon#about to read 4, iclass 4, count 0 2006.257.05:01:30.46#ibcon#read 4, iclass 4, count 0 2006.257.05:01:30.46#ibcon#about to read 5, iclass 4, count 0 2006.257.05:01:30.46#ibcon#read 5, iclass 4, count 0 2006.257.05:01:30.46#ibcon#about to read 6, iclass 4, count 0 2006.257.05:01:30.46#ibcon#read 6, iclass 4, count 0 2006.257.05:01:30.46#ibcon#end of sib2, iclass 4, count 0 2006.257.05:01:30.46#ibcon#*after write, iclass 4, count 0 2006.257.05:01:30.46#ibcon#*before return 0, iclass 4, count 0 2006.257.05:01:30.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:30.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:01:30.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:01:30.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:01:30.46$vck44/vblo=8,744.99 2006.257.05:01:30.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.05:01:30.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.05:01:30.46#ibcon#ireg 17 cls_cnt 0 2006.257.05:01:30.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:30.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:30.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:30.46#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:01:30.46#ibcon#first serial, iclass 6, count 0 2006.257.05:01:30.46#ibcon#enter sib2, iclass 6, count 0 2006.257.05:01:30.46#ibcon#flushed, iclass 6, count 0 2006.257.05:01:30.46#ibcon#about to write, iclass 6, count 0 2006.257.05:01:30.46#ibcon#wrote, iclass 6, count 0 2006.257.05:01:30.46#ibcon#about to read 3, iclass 6, count 0 2006.257.05:01:30.48#ibcon#read 3, iclass 6, count 0 2006.257.05:01:30.48#ibcon#about to read 4, iclass 6, count 0 2006.257.05:01:30.48#ibcon#read 4, iclass 6, count 0 2006.257.05:01:30.48#ibcon#about to read 5, iclass 6, count 0 2006.257.05:01:30.48#ibcon#read 5, iclass 6, count 0 2006.257.05:01:30.48#ibcon#about to read 6, iclass 6, count 0 2006.257.05:01:30.48#ibcon#read 6, iclass 6, count 0 2006.257.05:01:30.48#ibcon#end of sib2, iclass 6, count 0 2006.257.05:01:30.48#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:01:30.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:01:30.48#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:01:30.48#ibcon#*before write, iclass 6, count 0 2006.257.05:01:30.48#ibcon#enter sib2, iclass 6, count 0 2006.257.05:01:30.48#ibcon#flushed, iclass 6, count 0 2006.257.05:01:30.48#ibcon#about to write, iclass 6, count 0 2006.257.05:01:30.48#ibcon#wrote, iclass 6, count 0 2006.257.05:01:30.48#ibcon#about to read 3, iclass 6, count 0 2006.257.05:01:30.52#ibcon#read 3, iclass 6, count 0 2006.257.05:01:30.52#ibcon#about to read 4, iclass 6, count 0 2006.257.05:01:30.52#ibcon#read 4, iclass 6, count 0 2006.257.05:01:30.52#ibcon#about to read 5, iclass 6, count 0 2006.257.05:01:30.52#ibcon#read 5, iclass 6, count 0 2006.257.05:01:30.52#ibcon#about to read 6, iclass 6, count 0 2006.257.05:01:30.52#ibcon#read 6, iclass 6, count 0 2006.257.05:01:30.52#ibcon#end of sib2, iclass 6, count 0 2006.257.05:01:30.52#ibcon#*after write, iclass 6, count 0 2006.257.05:01:30.52#ibcon#*before return 0, iclass 6, count 0 2006.257.05:01:30.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:30.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:01:30.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:01:30.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:01:30.52$vck44/vb=8,4 2006.257.05:01:30.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.05:01:30.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.05:01:30.52#ibcon#ireg 11 cls_cnt 2 2006.257.05:01:30.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:30.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:30.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:30.58#ibcon#enter wrdev, iclass 10, count 2 2006.257.05:01:30.58#ibcon#first serial, iclass 10, count 2 2006.257.05:01:30.58#ibcon#enter sib2, iclass 10, count 2 2006.257.05:01:30.58#ibcon#flushed, iclass 10, count 2 2006.257.05:01:30.58#ibcon#about to write, iclass 10, count 2 2006.257.05:01:30.58#ibcon#wrote, iclass 10, count 2 2006.257.05:01:30.58#ibcon#about to read 3, iclass 10, count 2 2006.257.05:01:30.60#ibcon#read 3, iclass 10, count 2 2006.257.05:01:30.60#ibcon#about to read 4, iclass 10, count 2 2006.257.05:01:30.60#ibcon#read 4, iclass 10, count 2 2006.257.05:01:30.60#ibcon#about to read 5, iclass 10, count 2 2006.257.05:01:30.60#ibcon#read 5, iclass 10, count 2 2006.257.05:01:30.60#ibcon#about to read 6, iclass 10, count 2 2006.257.05:01:30.60#ibcon#read 6, iclass 10, count 2 2006.257.05:01:30.60#ibcon#end of sib2, iclass 10, count 2 2006.257.05:01:30.60#ibcon#*mode == 0, iclass 10, count 2 2006.257.05:01:30.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.05:01:30.60#ibcon#[27=AT08-04\r\n] 2006.257.05:01:30.60#ibcon#*before write, iclass 10, count 2 2006.257.05:01:30.60#ibcon#enter sib2, iclass 10, count 2 2006.257.05:01:30.60#ibcon#flushed, iclass 10, count 2 2006.257.05:01:30.60#ibcon#about to write, iclass 10, count 2 2006.257.05:01:30.60#ibcon#wrote, iclass 10, count 2 2006.257.05:01:30.60#ibcon#about to read 3, iclass 10, count 2 2006.257.05:01:30.63#ibcon#read 3, iclass 10, count 2 2006.257.05:01:30.63#ibcon#about to read 4, iclass 10, count 2 2006.257.05:01:30.63#ibcon#read 4, iclass 10, count 2 2006.257.05:01:30.63#ibcon#about to read 5, iclass 10, count 2 2006.257.05:01:30.63#ibcon#read 5, iclass 10, count 2 2006.257.05:01:30.63#ibcon#about to read 6, iclass 10, count 2 2006.257.05:01:30.63#ibcon#read 6, iclass 10, count 2 2006.257.05:01:30.63#ibcon#end of sib2, iclass 10, count 2 2006.257.05:01:30.63#ibcon#*after write, iclass 10, count 2 2006.257.05:01:30.63#ibcon#*before return 0, iclass 10, count 2 2006.257.05:01:30.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:30.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:01:30.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.05:01:30.63#ibcon#ireg 7 cls_cnt 0 2006.257.05:01:30.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:30.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:30.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:30.75#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:01:30.75#ibcon#first serial, iclass 10, count 0 2006.257.05:01:30.75#ibcon#enter sib2, iclass 10, count 0 2006.257.05:01:30.75#ibcon#flushed, iclass 10, count 0 2006.257.05:01:30.75#ibcon#about to write, iclass 10, count 0 2006.257.05:01:30.75#ibcon#wrote, iclass 10, count 0 2006.257.05:01:30.75#ibcon#about to read 3, iclass 10, count 0 2006.257.05:01:30.77#ibcon#read 3, iclass 10, count 0 2006.257.05:01:30.77#ibcon#about to read 4, iclass 10, count 0 2006.257.05:01:30.77#ibcon#read 4, iclass 10, count 0 2006.257.05:01:30.77#ibcon#about to read 5, iclass 10, count 0 2006.257.05:01:30.77#ibcon#read 5, iclass 10, count 0 2006.257.05:01:30.77#ibcon#about to read 6, iclass 10, count 0 2006.257.05:01:30.77#ibcon#read 6, iclass 10, count 0 2006.257.05:01:30.77#ibcon#end of sib2, iclass 10, count 0 2006.257.05:01:30.77#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:01:30.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:01:30.77#ibcon#[27=USB\r\n] 2006.257.05:01:30.77#ibcon#*before write, iclass 10, count 0 2006.257.05:01:30.77#ibcon#enter sib2, iclass 10, count 0 2006.257.05:01:30.77#ibcon#flushed, iclass 10, count 0 2006.257.05:01:30.77#ibcon#about to write, iclass 10, count 0 2006.257.05:01:30.77#ibcon#wrote, iclass 10, count 0 2006.257.05:01:30.77#ibcon#about to read 3, iclass 10, count 0 2006.257.05:01:30.80#ibcon#read 3, iclass 10, count 0 2006.257.05:01:30.80#ibcon#about to read 4, iclass 10, count 0 2006.257.05:01:30.80#ibcon#read 4, iclass 10, count 0 2006.257.05:01:30.80#ibcon#about to read 5, iclass 10, count 0 2006.257.05:01:30.80#ibcon#read 5, iclass 10, count 0 2006.257.05:01:30.80#ibcon#about to read 6, iclass 10, count 0 2006.257.05:01:30.80#ibcon#read 6, iclass 10, count 0 2006.257.05:01:30.80#ibcon#end of sib2, iclass 10, count 0 2006.257.05:01:30.80#ibcon#*after write, iclass 10, count 0 2006.257.05:01:30.80#ibcon#*before return 0, iclass 10, count 0 2006.257.05:01:30.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:30.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:01:30.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:01:30.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:01:30.80$vck44/vabw=wide 2006.257.05:01:30.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.05:01:30.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.05:01:30.80#ibcon#ireg 8 cls_cnt 0 2006.257.05:01:30.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:30.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:30.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:30.80#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:01:30.80#ibcon#first serial, iclass 12, count 0 2006.257.05:01:30.80#ibcon#enter sib2, iclass 12, count 0 2006.257.05:01:30.80#ibcon#flushed, iclass 12, count 0 2006.257.05:01:30.80#ibcon#about to write, iclass 12, count 0 2006.257.05:01:30.80#ibcon#wrote, iclass 12, count 0 2006.257.05:01:30.80#ibcon#about to read 3, iclass 12, count 0 2006.257.05:01:30.82#ibcon#read 3, iclass 12, count 0 2006.257.05:01:30.82#ibcon#about to read 4, iclass 12, count 0 2006.257.05:01:30.82#ibcon#read 4, iclass 12, count 0 2006.257.05:01:30.82#ibcon#about to read 5, iclass 12, count 0 2006.257.05:01:30.82#ibcon#read 5, iclass 12, count 0 2006.257.05:01:30.82#ibcon#about to read 6, iclass 12, count 0 2006.257.05:01:30.82#ibcon#read 6, iclass 12, count 0 2006.257.05:01:30.82#ibcon#end of sib2, iclass 12, count 0 2006.257.05:01:30.82#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:01:30.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:01:30.82#ibcon#[25=BW32\r\n] 2006.257.05:01:30.82#ibcon#*before write, iclass 12, count 0 2006.257.05:01:30.82#ibcon#enter sib2, iclass 12, count 0 2006.257.05:01:30.82#ibcon#flushed, iclass 12, count 0 2006.257.05:01:30.82#ibcon#about to write, iclass 12, count 0 2006.257.05:01:30.82#ibcon#wrote, iclass 12, count 0 2006.257.05:01:30.82#ibcon#about to read 3, iclass 12, count 0 2006.257.05:01:30.85#ibcon#read 3, iclass 12, count 0 2006.257.05:01:30.85#ibcon#about to read 4, iclass 12, count 0 2006.257.05:01:30.85#ibcon#read 4, iclass 12, count 0 2006.257.05:01:30.85#ibcon#about to read 5, iclass 12, count 0 2006.257.05:01:30.85#ibcon#read 5, iclass 12, count 0 2006.257.05:01:30.85#ibcon#about to read 6, iclass 12, count 0 2006.257.05:01:30.85#ibcon#read 6, iclass 12, count 0 2006.257.05:01:30.85#ibcon#end of sib2, iclass 12, count 0 2006.257.05:01:30.85#ibcon#*after write, iclass 12, count 0 2006.257.05:01:30.85#ibcon#*before return 0, iclass 12, count 0 2006.257.05:01:30.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:30.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:01:30.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:01:30.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:01:30.85$vck44/vbbw=wide 2006.257.05:01:30.85#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.05:01:30.85#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.05:01:30.85#ibcon#ireg 8 cls_cnt 0 2006.257.05:01:30.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:01:30.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:01:30.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:01:30.92#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:01:30.92#ibcon#first serial, iclass 14, count 0 2006.257.05:01:30.92#ibcon#enter sib2, iclass 14, count 0 2006.257.05:01:30.92#ibcon#flushed, iclass 14, count 0 2006.257.05:01:30.92#ibcon#about to write, iclass 14, count 0 2006.257.05:01:30.92#ibcon#wrote, iclass 14, count 0 2006.257.05:01:30.92#ibcon#about to read 3, iclass 14, count 0 2006.257.05:01:30.94#ibcon#read 3, iclass 14, count 0 2006.257.05:01:30.94#ibcon#about to read 4, iclass 14, count 0 2006.257.05:01:30.94#ibcon#read 4, iclass 14, count 0 2006.257.05:01:30.94#ibcon#about to read 5, iclass 14, count 0 2006.257.05:01:30.94#ibcon#read 5, iclass 14, count 0 2006.257.05:01:30.94#ibcon#about to read 6, iclass 14, count 0 2006.257.05:01:30.94#ibcon#read 6, iclass 14, count 0 2006.257.05:01:30.94#ibcon#end of sib2, iclass 14, count 0 2006.257.05:01:30.94#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:01:30.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:01:30.94#ibcon#[27=BW32\r\n] 2006.257.05:01:30.94#ibcon#*before write, iclass 14, count 0 2006.257.05:01:30.94#ibcon#enter sib2, iclass 14, count 0 2006.257.05:01:30.94#ibcon#flushed, iclass 14, count 0 2006.257.05:01:30.94#ibcon#about to write, iclass 14, count 0 2006.257.05:01:30.94#ibcon#wrote, iclass 14, count 0 2006.257.05:01:30.94#ibcon#about to read 3, iclass 14, count 0 2006.257.05:01:30.97#ibcon#read 3, iclass 14, count 0 2006.257.05:01:30.97#ibcon#about to read 4, iclass 14, count 0 2006.257.05:01:30.97#ibcon#read 4, iclass 14, count 0 2006.257.05:01:30.97#ibcon#about to read 5, iclass 14, count 0 2006.257.05:01:30.97#ibcon#read 5, iclass 14, count 0 2006.257.05:01:30.97#ibcon#about to read 6, iclass 14, count 0 2006.257.05:01:30.97#ibcon#read 6, iclass 14, count 0 2006.257.05:01:30.97#ibcon#end of sib2, iclass 14, count 0 2006.257.05:01:30.97#ibcon#*after write, iclass 14, count 0 2006.257.05:01:30.97#ibcon#*before return 0, iclass 14, count 0 2006.257.05:01:30.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:01:30.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:01:30.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:01:30.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:01:30.97$setupk4/ifdk4 2006.257.05:01:30.97$ifdk4/lo= 2006.257.05:01:30.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:01:30.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:01:30.97$ifdk4/patch= 2006.257.05:01:30.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:01:30.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:01:30.97$setupk4/!*+20s 2006.257.05:01:36.74#abcon#<5=/15 1.8 4.7 19.69 931012.0\r\n> 2006.257.05:01:36.76#abcon#{5=INTERFACE CLEAR} 2006.257.05:01:36.82#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:01:45.48$setupk4/"tpicd 2006.257.05:01:45.48$setupk4/echo=off 2006.257.05:01:45.48$setupk4/xlog=off 2006.257.05:01:45.48:!2006.257.05:02:40 2006.257.05:02:22.14#trakl#Source acquired 2006.257.05:02:23.14#flagr#flagr/antenna,acquired 2006.257.05:02:40.00:preob 2006.257.05:02:40.14/onsource/TRACKING 2006.257.05:02:40.14:!2006.257.05:02:50 2006.257.05:02:50.00:"tape 2006.257.05:02:50.00:"st=record 2006.257.05:02:50.00:data_valid=on 2006.257.05:02:50.00:midob 2006.257.05:02:50.14/onsource/TRACKING 2006.257.05:02:50.14/wx/19.69,1012.0,93 2006.257.05:02:50.32/cable/+6.4823E-03 2006.257.05:02:51.41/va/01,08,usb,yes,43,46 2006.257.05:02:51.41/va/02,07,usb,yes,46,47 2006.257.05:02:51.41/va/03,08,usb,yes,42,44 2006.257.05:02:51.41/va/04,07,usb,yes,48,50 2006.257.05:02:51.41/va/05,04,usb,yes,43,43 2006.257.05:02:51.41/va/06,04,usb,yes,48,47 2006.257.05:02:51.41/va/07,04,usb,yes,49,49 2006.257.05:02:51.41/va/08,04,usb,yes,41,50 2006.257.05:02:51.64/valo/01,524.99,yes,locked 2006.257.05:02:51.64/valo/02,534.99,yes,locked 2006.257.05:02:51.64/valo/03,564.99,yes,locked 2006.257.05:02:51.64/valo/04,624.99,yes,locked 2006.257.05:02:51.64/valo/05,734.99,yes,locked 2006.257.05:02:51.64/valo/06,814.99,yes,locked 2006.257.05:02:51.64/valo/07,864.99,yes,locked 2006.257.05:02:51.64/valo/08,884.99,yes,locked 2006.257.05:02:52.73/vb/01,04,usb,yes,53,99 2006.257.05:02:52.73/vb/02,05,usb,yes,33,96 2006.257.05:02:52.73/vb/03,04,usb,yes,31,84 2006.257.05:02:52.73/vb/04,05,usb,yes,31,30 2006.257.05:02:52.73/vb/05,04,usb,yes,31,33 2006.257.05:02:52.73/vb/06,04,usb,yes,36,31 2006.257.05:02:52.73/vb/07,04,usb,yes,33,33 2006.257.05:02:52.73/vb/08,04,usb,yes,31,35 2006.257.05:02:52.96/vblo/01,629.99,yes,locked 2006.257.05:02:52.96/vblo/02,634.99,yes,locked 2006.257.05:02:52.96/vblo/03,649.99,yes,locked 2006.257.05:02:52.96/vblo/04,679.99,yes,locked 2006.257.05:02:52.96/vblo/05,709.99,yes,locked 2006.257.05:02:52.96/vblo/06,719.99,yes,locked 2006.257.05:02:52.96/vblo/07,734.99,yes,locked 2006.257.05:02:52.96/vblo/08,744.99,yes,locked 2006.257.05:02:53.11/vabw/8 2006.257.05:02:53.26/vbbw/8 2006.257.05:02:53.35/xfe/off,on,16.5 2006.257.05:02:53.73/ifatt/23,28,28,28 2006.257.05:02:54.07/fmout-gps/S +4.56E-07 2006.257.05:02:54.11:!2006.257.05:06:20 2006.257.05:06:20.00:data_valid=off 2006.257.05:06:20.00:"et 2006.257.05:06:20.00:!+3s 2006.257.05:06:23.01:"tape 2006.257.05:06:23.01:postob 2006.257.05:06:23.12/cable/+6.4838E-03 2006.257.05:06:23.12/wx/19.68,1012.0,92 2006.257.05:06:24.07/fmout-gps/S +4.54E-07 2006.257.05:06:24.07:scan_name=257-0507,jd0609,200 2006.257.05:06:24.07:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.257.05:06:24.14#flagr#flagr/antenna,new-source 2006.257.05:06:25.14:checkk5 2006.257.05:06:25.62/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:06:26.01/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:06:26.42/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:06:27.30/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:06:27.70/chk_obsdata//k5ts1/T2570502??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.257.05:06:28.10/chk_obsdata//k5ts2/T2570502??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.257.05:06:28.51/chk_obsdata//k5ts3/T2570502??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.257.05:06:28.89/chk_obsdata//k5ts4/T2570502??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.257.05:06:29.63/k5log//k5ts1_log_newline 2006.257.05:06:30.35/k5log//k5ts2_log_newline 2006.257.05:06:31.09/k5log//k5ts3_log_newline 2006.257.05:06:31.80/k5log//k5ts4_log_newline 2006.257.05:06:31.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:06:31.83:setupk4=1 2006.257.05:06:31.83$setupk4/echo=on 2006.257.05:06:31.83$setupk4/pcalon 2006.257.05:06:31.83$pcalon/"no phase cal control is implemented here 2006.257.05:06:31.83$setupk4/"tpicd=stop 2006.257.05:06:31.83$setupk4/"rec=synch_on 2006.257.05:06:31.83$setupk4/"rec_mode=128 2006.257.05:06:31.83$setupk4/!* 2006.257.05:06:31.83$setupk4/recpk4 2006.257.05:06:31.83$recpk4/recpatch= 2006.257.05:06:31.83$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:06:31.83$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:06:31.83$setupk4/vck44 2006.257.05:06:31.83$vck44/valo=1,524.99 2006.257.05:06:31.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.05:06:31.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.05:06:31.83#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:31.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:06:31.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:06:31.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:06:31.83#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:06:31.83#ibcon#first serial, iclass 22, count 0 2006.257.05:06:31.83#ibcon#enter sib2, iclass 22, count 0 2006.257.05:06:31.83#ibcon#flushed, iclass 22, count 0 2006.257.05:06:31.83#ibcon#about to write, iclass 22, count 0 2006.257.05:06:31.83#ibcon#wrote, iclass 22, count 0 2006.257.05:06:31.83#ibcon#about to read 3, iclass 22, count 0 2006.257.05:06:31.85#ibcon#read 3, iclass 22, count 0 2006.257.05:06:31.85#ibcon#about to read 4, iclass 22, count 0 2006.257.05:06:31.85#ibcon#read 4, iclass 22, count 0 2006.257.05:06:31.85#ibcon#about to read 5, iclass 22, count 0 2006.257.05:06:31.85#ibcon#read 5, iclass 22, count 0 2006.257.05:06:31.85#ibcon#about to read 6, iclass 22, count 0 2006.257.05:06:31.85#ibcon#read 6, iclass 22, count 0 2006.257.05:06:31.85#ibcon#end of sib2, iclass 22, count 0 2006.257.05:06:31.85#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:06:31.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:06:31.85#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:06:31.85#ibcon#*before write, iclass 22, count 0 2006.257.05:06:31.85#ibcon#enter sib2, iclass 22, count 0 2006.257.05:06:31.85#ibcon#flushed, iclass 22, count 0 2006.257.05:06:31.85#ibcon#about to write, iclass 22, count 0 2006.257.05:06:31.85#ibcon#wrote, iclass 22, count 0 2006.257.05:06:31.85#ibcon#about to read 3, iclass 22, count 0 2006.257.05:06:31.90#ibcon#read 3, iclass 22, count 0 2006.257.05:06:31.90#ibcon#about to read 4, iclass 22, count 0 2006.257.05:06:31.90#ibcon#read 4, iclass 22, count 0 2006.257.05:06:31.90#ibcon#about to read 5, iclass 22, count 0 2006.257.05:06:31.90#ibcon#read 5, iclass 22, count 0 2006.257.05:06:31.90#ibcon#about to read 6, iclass 22, count 0 2006.257.05:06:31.90#ibcon#read 6, iclass 22, count 0 2006.257.05:06:31.90#ibcon#end of sib2, iclass 22, count 0 2006.257.05:06:31.90#ibcon#*after write, iclass 22, count 0 2006.257.05:06:31.90#ibcon#*before return 0, iclass 22, count 0 2006.257.05:06:31.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:06:31.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:06:31.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:06:31.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:06:31.90$vck44/va=1,8 2006.257.05:06:31.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.05:06:31.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.05:06:31.90#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:31.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:06:31.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:06:31.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:06:31.90#ibcon#enter wrdev, iclass 24, count 2 2006.257.05:06:31.90#ibcon#first serial, iclass 24, count 2 2006.257.05:06:31.90#ibcon#enter sib2, iclass 24, count 2 2006.257.05:06:31.90#ibcon#flushed, iclass 24, count 2 2006.257.05:06:31.90#ibcon#about to write, iclass 24, count 2 2006.257.05:06:31.90#ibcon#wrote, iclass 24, count 2 2006.257.05:06:31.90#ibcon#about to read 3, iclass 24, count 2 2006.257.05:06:31.92#ibcon#read 3, iclass 24, count 2 2006.257.05:06:31.92#ibcon#about to read 4, iclass 24, count 2 2006.257.05:06:31.92#ibcon#read 4, iclass 24, count 2 2006.257.05:06:31.92#ibcon#about to read 5, iclass 24, count 2 2006.257.05:06:31.92#ibcon#read 5, iclass 24, count 2 2006.257.05:06:31.92#ibcon#about to read 6, iclass 24, count 2 2006.257.05:06:31.92#ibcon#read 6, iclass 24, count 2 2006.257.05:06:31.92#ibcon#end of sib2, iclass 24, count 2 2006.257.05:06:31.92#ibcon#*mode == 0, iclass 24, count 2 2006.257.05:06:31.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.05:06:31.92#ibcon#[25=AT01-08\r\n] 2006.257.05:06:31.92#ibcon#*before write, iclass 24, count 2 2006.257.05:06:31.92#ibcon#enter sib2, iclass 24, count 2 2006.257.05:06:31.92#ibcon#flushed, iclass 24, count 2 2006.257.05:06:31.92#ibcon#about to write, iclass 24, count 2 2006.257.05:06:31.92#ibcon#wrote, iclass 24, count 2 2006.257.05:06:31.92#ibcon#about to read 3, iclass 24, count 2 2006.257.05:06:31.95#ibcon#read 3, iclass 24, count 2 2006.257.05:06:31.95#ibcon#about to read 4, iclass 24, count 2 2006.257.05:06:31.95#ibcon#read 4, iclass 24, count 2 2006.257.05:06:31.95#ibcon#about to read 5, iclass 24, count 2 2006.257.05:06:31.95#ibcon#read 5, iclass 24, count 2 2006.257.05:06:31.95#ibcon#about to read 6, iclass 24, count 2 2006.257.05:06:31.95#ibcon#read 6, iclass 24, count 2 2006.257.05:06:31.95#ibcon#end of sib2, iclass 24, count 2 2006.257.05:06:31.95#ibcon#*after write, iclass 24, count 2 2006.257.05:06:31.95#ibcon#*before return 0, iclass 24, count 2 2006.257.05:06:31.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:06:31.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:06:31.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.05:06:31.95#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:31.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:06:32.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:06:32.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:06:32.07#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:06:32.07#ibcon#first serial, iclass 24, count 0 2006.257.05:06:32.07#ibcon#enter sib2, iclass 24, count 0 2006.257.05:06:32.07#ibcon#flushed, iclass 24, count 0 2006.257.05:06:32.07#ibcon#about to write, iclass 24, count 0 2006.257.05:06:32.07#ibcon#wrote, iclass 24, count 0 2006.257.05:06:32.07#ibcon#about to read 3, iclass 24, count 0 2006.257.05:06:32.09#ibcon#read 3, iclass 24, count 0 2006.257.05:06:32.09#ibcon#about to read 4, iclass 24, count 0 2006.257.05:06:32.09#ibcon#read 4, iclass 24, count 0 2006.257.05:06:32.09#ibcon#about to read 5, iclass 24, count 0 2006.257.05:06:32.09#ibcon#read 5, iclass 24, count 0 2006.257.05:06:32.09#ibcon#about to read 6, iclass 24, count 0 2006.257.05:06:32.09#ibcon#read 6, iclass 24, count 0 2006.257.05:06:32.09#ibcon#end of sib2, iclass 24, count 0 2006.257.05:06:32.09#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:06:32.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:06:32.09#ibcon#[25=USB\r\n] 2006.257.05:06:32.09#ibcon#*before write, iclass 24, count 0 2006.257.05:06:32.09#ibcon#enter sib2, iclass 24, count 0 2006.257.05:06:32.09#ibcon#flushed, iclass 24, count 0 2006.257.05:06:32.09#ibcon#about to write, iclass 24, count 0 2006.257.05:06:32.09#ibcon#wrote, iclass 24, count 0 2006.257.05:06:32.09#ibcon#about to read 3, iclass 24, count 0 2006.257.05:06:32.12#ibcon#read 3, iclass 24, count 0 2006.257.05:06:32.12#ibcon#about to read 4, iclass 24, count 0 2006.257.05:06:32.12#ibcon#read 4, iclass 24, count 0 2006.257.05:06:32.12#ibcon#about to read 5, iclass 24, count 0 2006.257.05:06:32.12#ibcon#read 5, iclass 24, count 0 2006.257.05:06:32.12#ibcon#about to read 6, iclass 24, count 0 2006.257.05:06:32.12#ibcon#read 6, iclass 24, count 0 2006.257.05:06:32.12#ibcon#end of sib2, iclass 24, count 0 2006.257.05:06:32.12#ibcon#*after write, iclass 24, count 0 2006.257.05:06:32.12#ibcon#*before return 0, iclass 24, count 0 2006.257.05:06:32.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:06:32.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:06:32.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:06:32.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:06:32.12$vck44/valo=2,534.99 2006.257.05:06:32.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.05:06:32.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.05:06:32.12#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:32.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:32.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:32.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:32.12#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:06:32.12#ibcon#first serial, iclass 26, count 0 2006.257.05:06:32.12#ibcon#enter sib2, iclass 26, count 0 2006.257.05:06:32.12#ibcon#flushed, iclass 26, count 0 2006.257.05:06:32.12#ibcon#about to write, iclass 26, count 0 2006.257.05:06:32.12#ibcon#wrote, iclass 26, count 0 2006.257.05:06:32.12#ibcon#about to read 3, iclass 26, count 0 2006.257.05:06:32.14#ibcon#read 3, iclass 26, count 0 2006.257.05:06:32.14#ibcon#about to read 4, iclass 26, count 0 2006.257.05:06:32.14#ibcon#read 4, iclass 26, count 0 2006.257.05:06:32.14#ibcon#about to read 5, iclass 26, count 0 2006.257.05:06:32.14#ibcon#read 5, iclass 26, count 0 2006.257.05:06:32.14#ibcon#about to read 6, iclass 26, count 0 2006.257.05:06:32.14#ibcon#read 6, iclass 26, count 0 2006.257.05:06:32.14#ibcon#end of sib2, iclass 26, count 0 2006.257.05:06:32.14#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:06:32.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:06:32.14#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:06:32.14#ibcon#*before write, iclass 26, count 0 2006.257.05:06:32.14#ibcon#enter sib2, iclass 26, count 0 2006.257.05:06:32.14#ibcon#flushed, iclass 26, count 0 2006.257.05:06:32.14#ibcon#about to write, iclass 26, count 0 2006.257.05:06:32.14#ibcon#wrote, iclass 26, count 0 2006.257.05:06:32.14#ibcon#about to read 3, iclass 26, count 0 2006.257.05:06:32.18#ibcon#read 3, iclass 26, count 0 2006.257.05:06:32.18#ibcon#about to read 4, iclass 26, count 0 2006.257.05:06:32.18#ibcon#read 4, iclass 26, count 0 2006.257.05:06:32.18#ibcon#about to read 5, iclass 26, count 0 2006.257.05:06:32.18#ibcon#read 5, iclass 26, count 0 2006.257.05:06:32.18#ibcon#about to read 6, iclass 26, count 0 2006.257.05:06:32.18#ibcon#read 6, iclass 26, count 0 2006.257.05:06:32.18#ibcon#end of sib2, iclass 26, count 0 2006.257.05:06:32.18#ibcon#*after write, iclass 26, count 0 2006.257.05:06:32.18#ibcon#*before return 0, iclass 26, count 0 2006.257.05:06:32.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:32.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:32.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:06:32.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:06:32.18$vck44/va=2,7 2006.257.05:06:32.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.05:06:32.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.05:06:32.18#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:32.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:32.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:32.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:32.24#ibcon#enter wrdev, iclass 28, count 2 2006.257.05:06:32.24#ibcon#first serial, iclass 28, count 2 2006.257.05:06:32.24#ibcon#enter sib2, iclass 28, count 2 2006.257.05:06:32.24#ibcon#flushed, iclass 28, count 2 2006.257.05:06:32.24#ibcon#about to write, iclass 28, count 2 2006.257.05:06:32.24#ibcon#wrote, iclass 28, count 2 2006.257.05:06:32.24#ibcon#about to read 3, iclass 28, count 2 2006.257.05:06:32.26#ibcon#read 3, iclass 28, count 2 2006.257.05:06:32.26#ibcon#about to read 4, iclass 28, count 2 2006.257.05:06:32.26#ibcon#read 4, iclass 28, count 2 2006.257.05:06:32.26#ibcon#about to read 5, iclass 28, count 2 2006.257.05:06:32.26#ibcon#read 5, iclass 28, count 2 2006.257.05:06:32.26#ibcon#about to read 6, iclass 28, count 2 2006.257.05:06:32.26#ibcon#read 6, iclass 28, count 2 2006.257.05:06:32.26#ibcon#end of sib2, iclass 28, count 2 2006.257.05:06:32.26#ibcon#*mode == 0, iclass 28, count 2 2006.257.05:06:32.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.05:06:32.26#ibcon#[25=AT02-07\r\n] 2006.257.05:06:32.26#ibcon#*before write, iclass 28, count 2 2006.257.05:06:32.26#ibcon#enter sib2, iclass 28, count 2 2006.257.05:06:32.26#ibcon#flushed, iclass 28, count 2 2006.257.05:06:32.26#ibcon#about to write, iclass 28, count 2 2006.257.05:06:32.26#ibcon#wrote, iclass 28, count 2 2006.257.05:06:32.26#ibcon#about to read 3, iclass 28, count 2 2006.257.05:06:32.29#ibcon#read 3, iclass 28, count 2 2006.257.05:06:32.29#ibcon#about to read 4, iclass 28, count 2 2006.257.05:06:32.29#ibcon#read 4, iclass 28, count 2 2006.257.05:06:32.29#ibcon#about to read 5, iclass 28, count 2 2006.257.05:06:32.29#ibcon#read 5, iclass 28, count 2 2006.257.05:06:32.29#ibcon#about to read 6, iclass 28, count 2 2006.257.05:06:32.29#ibcon#read 6, iclass 28, count 2 2006.257.05:06:32.29#ibcon#end of sib2, iclass 28, count 2 2006.257.05:06:32.29#ibcon#*after write, iclass 28, count 2 2006.257.05:06:32.29#ibcon#*before return 0, iclass 28, count 2 2006.257.05:06:32.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:32.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:32.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.05:06:32.29#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:32.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:32.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:32.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:32.41#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:06:32.41#ibcon#first serial, iclass 28, count 0 2006.257.05:06:32.41#ibcon#enter sib2, iclass 28, count 0 2006.257.05:06:32.41#ibcon#flushed, iclass 28, count 0 2006.257.05:06:32.41#ibcon#about to write, iclass 28, count 0 2006.257.05:06:32.41#ibcon#wrote, iclass 28, count 0 2006.257.05:06:32.41#ibcon#about to read 3, iclass 28, count 0 2006.257.05:06:32.43#ibcon#read 3, iclass 28, count 0 2006.257.05:06:32.43#ibcon#about to read 4, iclass 28, count 0 2006.257.05:06:32.43#ibcon#read 4, iclass 28, count 0 2006.257.05:06:32.43#ibcon#about to read 5, iclass 28, count 0 2006.257.05:06:32.43#ibcon#read 5, iclass 28, count 0 2006.257.05:06:32.43#ibcon#about to read 6, iclass 28, count 0 2006.257.05:06:32.43#ibcon#read 6, iclass 28, count 0 2006.257.05:06:32.43#ibcon#end of sib2, iclass 28, count 0 2006.257.05:06:32.43#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:06:32.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:06:32.43#ibcon#[25=USB\r\n] 2006.257.05:06:32.43#ibcon#*before write, iclass 28, count 0 2006.257.05:06:32.43#ibcon#enter sib2, iclass 28, count 0 2006.257.05:06:32.43#ibcon#flushed, iclass 28, count 0 2006.257.05:06:32.43#ibcon#about to write, iclass 28, count 0 2006.257.05:06:32.43#ibcon#wrote, iclass 28, count 0 2006.257.05:06:32.43#ibcon#about to read 3, iclass 28, count 0 2006.257.05:06:32.46#ibcon#read 3, iclass 28, count 0 2006.257.05:06:32.46#ibcon#about to read 4, iclass 28, count 0 2006.257.05:06:32.46#ibcon#read 4, iclass 28, count 0 2006.257.05:06:32.46#ibcon#about to read 5, iclass 28, count 0 2006.257.05:06:32.46#ibcon#read 5, iclass 28, count 0 2006.257.05:06:32.46#ibcon#about to read 6, iclass 28, count 0 2006.257.05:06:32.46#ibcon#read 6, iclass 28, count 0 2006.257.05:06:32.46#ibcon#end of sib2, iclass 28, count 0 2006.257.05:06:32.46#ibcon#*after write, iclass 28, count 0 2006.257.05:06:32.46#ibcon#*before return 0, iclass 28, count 0 2006.257.05:06:32.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:32.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:32.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:06:32.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:06:32.46$vck44/valo=3,564.99 2006.257.05:06:32.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.05:06:32.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.05:06:32.46#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:32.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:32.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:32.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:32.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:06:32.46#ibcon#first serial, iclass 30, count 0 2006.257.05:06:32.46#ibcon#enter sib2, iclass 30, count 0 2006.257.05:06:32.46#ibcon#flushed, iclass 30, count 0 2006.257.05:06:32.46#ibcon#about to write, iclass 30, count 0 2006.257.05:06:32.46#ibcon#wrote, iclass 30, count 0 2006.257.05:06:32.46#ibcon#about to read 3, iclass 30, count 0 2006.257.05:06:32.48#ibcon#read 3, iclass 30, count 0 2006.257.05:06:32.48#ibcon#about to read 4, iclass 30, count 0 2006.257.05:06:32.48#ibcon#read 4, iclass 30, count 0 2006.257.05:06:32.48#ibcon#about to read 5, iclass 30, count 0 2006.257.05:06:32.48#ibcon#read 5, iclass 30, count 0 2006.257.05:06:32.48#ibcon#about to read 6, iclass 30, count 0 2006.257.05:06:32.48#ibcon#read 6, iclass 30, count 0 2006.257.05:06:32.48#ibcon#end of sib2, iclass 30, count 0 2006.257.05:06:32.48#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:06:32.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:06:32.48#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:06:32.48#ibcon#*before write, iclass 30, count 0 2006.257.05:06:32.48#ibcon#enter sib2, iclass 30, count 0 2006.257.05:06:32.48#ibcon#flushed, iclass 30, count 0 2006.257.05:06:32.48#ibcon#about to write, iclass 30, count 0 2006.257.05:06:32.48#ibcon#wrote, iclass 30, count 0 2006.257.05:06:32.48#ibcon#about to read 3, iclass 30, count 0 2006.257.05:06:32.52#ibcon#read 3, iclass 30, count 0 2006.257.05:06:32.52#ibcon#about to read 4, iclass 30, count 0 2006.257.05:06:32.52#ibcon#read 4, iclass 30, count 0 2006.257.05:06:32.52#ibcon#about to read 5, iclass 30, count 0 2006.257.05:06:32.52#ibcon#read 5, iclass 30, count 0 2006.257.05:06:32.52#ibcon#about to read 6, iclass 30, count 0 2006.257.05:06:32.52#ibcon#read 6, iclass 30, count 0 2006.257.05:06:32.52#ibcon#end of sib2, iclass 30, count 0 2006.257.05:06:32.52#ibcon#*after write, iclass 30, count 0 2006.257.05:06:32.52#ibcon#*before return 0, iclass 30, count 0 2006.257.05:06:32.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:32.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:32.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:06:32.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:06:32.52$vck44/va=3,8 2006.257.05:06:32.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.05:06:32.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.05:06:32.52#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:32.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:32.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:32.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:32.58#ibcon#enter wrdev, iclass 32, count 2 2006.257.05:06:32.58#ibcon#first serial, iclass 32, count 2 2006.257.05:06:32.58#ibcon#enter sib2, iclass 32, count 2 2006.257.05:06:32.58#ibcon#flushed, iclass 32, count 2 2006.257.05:06:32.58#ibcon#about to write, iclass 32, count 2 2006.257.05:06:32.58#ibcon#wrote, iclass 32, count 2 2006.257.05:06:32.58#ibcon#about to read 3, iclass 32, count 2 2006.257.05:06:32.60#ibcon#read 3, iclass 32, count 2 2006.257.05:06:32.60#ibcon#about to read 4, iclass 32, count 2 2006.257.05:06:32.60#ibcon#read 4, iclass 32, count 2 2006.257.05:06:32.60#ibcon#about to read 5, iclass 32, count 2 2006.257.05:06:32.60#ibcon#read 5, iclass 32, count 2 2006.257.05:06:32.60#ibcon#about to read 6, iclass 32, count 2 2006.257.05:06:32.60#ibcon#read 6, iclass 32, count 2 2006.257.05:06:32.60#ibcon#end of sib2, iclass 32, count 2 2006.257.05:06:32.60#ibcon#*mode == 0, iclass 32, count 2 2006.257.05:06:32.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.05:06:32.60#ibcon#[25=AT03-08\r\n] 2006.257.05:06:32.60#ibcon#*before write, iclass 32, count 2 2006.257.05:06:32.60#ibcon#enter sib2, iclass 32, count 2 2006.257.05:06:32.60#ibcon#flushed, iclass 32, count 2 2006.257.05:06:32.60#ibcon#about to write, iclass 32, count 2 2006.257.05:06:32.60#ibcon#wrote, iclass 32, count 2 2006.257.05:06:32.60#ibcon#about to read 3, iclass 32, count 2 2006.257.05:06:32.63#ibcon#read 3, iclass 32, count 2 2006.257.05:06:32.63#ibcon#about to read 4, iclass 32, count 2 2006.257.05:06:32.63#ibcon#read 4, iclass 32, count 2 2006.257.05:06:32.63#ibcon#about to read 5, iclass 32, count 2 2006.257.05:06:32.63#ibcon#read 5, iclass 32, count 2 2006.257.05:06:32.63#ibcon#about to read 6, iclass 32, count 2 2006.257.05:06:32.63#ibcon#read 6, iclass 32, count 2 2006.257.05:06:32.63#ibcon#end of sib2, iclass 32, count 2 2006.257.05:06:32.63#ibcon#*after write, iclass 32, count 2 2006.257.05:06:32.63#ibcon#*before return 0, iclass 32, count 2 2006.257.05:06:32.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:32.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:32.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.05:06:32.63#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:32.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:32.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:32.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:32.75#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:06:32.75#ibcon#first serial, iclass 32, count 0 2006.257.05:06:32.75#ibcon#enter sib2, iclass 32, count 0 2006.257.05:06:32.75#ibcon#flushed, iclass 32, count 0 2006.257.05:06:32.75#ibcon#about to write, iclass 32, count 0 2006.257.05:06:32.75#ibcon#wrote, iclass 32, count 0 2006.257.05:06:32.75#ibcon#about to read 3, iclass 32, count 0 2006.257.05:06:32.77#ibcon#read 3, iclass 32, count 0 2006.257.05:06:32.77#ibcon#about to read 4, iclass 32, count 0 2006.257.05:06:32.77#ibcon#read 4, iclass 32, count 0 2006.257.05:06:32.77#ibcon#about to read 5, iclass 32, count 0 2006.257.05:06:32.77#ibcon#read 5, iclass 32, count 0 2006.257.05:06:32.77#ibcon#about to read 6, iclass 32, count 0 2006.257.05:06:32.77#ibcon#read 6, iclass 32, count 0 2006.257.05:06:32.77#ibcon#end of sib2, iclass 32, count 0 2006.257.05:06:32.77#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:06:32.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:06:32.77#ibcon#[25=USB\r\n] 2006.257.05:06:32.77#ibcon#*before write, iclass 32, count 0 2006.257.05:06:32.77#ibcon#enter sib2, iclass 32, count 0 2006.257.05:06:32.77#ibcon#flushed, iclass 32, count 0 2006.257.05:06:32.77#ibcon#about to write, iclass 32, count 0 2006.257.05:06:32.77#ibcon#wrote, iclass 32, count 0 2006.257.05:06:32.77#ibcon#about to read 3, iclass 32, count 0 2006.257.05:06:32.80#ibcon#read 3, iclass 32, count 0 2006.257.05:06:32.80#ibcon#about to read 4, iclass 32, count 0 2006.257.05:06:32.80#ibcon#read 4, iclass 32, count 0 2006.257.05:06:32.80#ibcon#about to read 5, iclass 32, count 0 2006.257.05:06:32.80#ibcon#read 5, iclass 32, count 0 2006.257.05:06:32.80#ibcon#about to read 6, iclass 32, count 0 2006.257.05:06:32.80#ibcon#read 6, iclass 32, count 0 2006.257.05:06:32.80#ibcon#end of sib2, iclass 32, count 0 2006.257.05:06:32.80#ibcon#*after write, iclass 32, count 0 2006.257.05:06:32.80#ibcon#*before return 0, iclass 32, count 0 2006.257.05:06:32.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:32.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:32.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:06:32.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:06:32.80$vck44/valo=4,624.99 2006.257.05:06:32.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.05:06:32.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.05:06:32.80#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:32.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:32.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:32.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:32.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:06:32.80#ibcon#first serial, iclass 34, count 0 2006.257.05:06:32.80#ibcon#enter sib2, iclass 34, count 0 2006.257.05:06:32.80#ibcon#flushed, iclass 34, count 0 2006.257.05:06:32.80#ibcon#about to write, iclass 34, count 0 2006.257.05:06:32.80#ibcon#wrote, iclass 34, count 0 2006.257.05:06:32.80#ibcon#about to read 3, iclass 34, count 0 2006.257.05:06:32.82#ibcon#read 3, iclass 34, count 0 2006.257.05:06:32.82#ibcon#about to read 4, iclass 34, count 0 2006.257.05:06:32.82#ibcon#read 4, iclass 34, count 0 2006.257.05:06:32.82#ibcon#about to read 5, iclass 34, count 0 2006.257.05:06:32.82#ibcon#read 5, iclass 34, count 0 2006.257.05:06:32.82#ibcon#about to read 6, iclass 34, count 0 2006.257.05:06:32.82#ibcon#read 6, iclass 34, count 0 2006.257.05:06:32.82#ibcon#end of sib2, iclass 34, count 0 2006.257.05:06:32.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:06:32.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:06:32.82#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:06:32.82#ibcon#*before write, iclass 34, count 0 2006.257.05:06:32.82#ibcon#enter sib2, iclass 34, count 0 2006.257.05:06:32.82#ibcon#flushed, iclass 34, count 0 2006.257.05:06:32.82#ibcon#about to write, iclass 34, count 0 2006.257.05:06:32.82#ibcon#wrote, iclass 34, count 0 2006.257.05:06:32.82#ibcon#about to read 3, iclass 34, count 0 2006.257.05:06:32.86#ibcon#read 3, iclass 34, count 0 2006.257.05:06:32.86#ibcon#about to read 4, iclass 34, count 0 2006.257.05:06:32.86#ibcon#read 4, iclass 34, count 0 2006.257.05:06:32.86#ibcon#about to read 5, iclass 34, count 0 2006.257.05:06:32.86#ibcon#read 5, iclass 34, count 0 2006.257.05:06:32.86#ibcon#about to read 6, iclass 34, count 0 2006.257.05:06:32.86#ibcon#read 6, iclass 34, count 0 2006.257.05:06:32.86#ibcon#end of sib2, iclass 34, count 0 2006.257.05:06:32.86#ibcon#*after write, iclass 34, count 0 2006.257.05:06:32.86#ibcon#*before return 0, iclass 34, count 0 2006.257.05:06:32.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:32.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:32.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:06:32.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:06:32.86$vck44/va=4,7 2006.257.05:06:32.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.05:06:32.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.05:06:32.86#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:32.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:32.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:32.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:32.92#ibcon#enter wrdev, iclass 36, count 2 2006.257.05:06:32.92#ibcon#first serial, iclass 36, count 2 2006.257.05:06:32.92#ibcon#enter sib2, iclass 36, count 2 2006.257.05:06:32.92#ibcon#flushed, iclass 36, count 2 2006.257.05:06:32.92#ibcon#about to write, iclass 36, count 2 2006.257.05:06:32.92#ibcon#wrote, iclass 36, count 2 2006.257.05:06:32.92#ibcon#about to read 3, iclass 36, count 2 2006.257.05:06:32.94#ibcon#read 3, iclass 36, count 2 2006.257.05:06:32.94#ibcon#about to read 4, iclass 36, count 2 2006.257.05:06:32.94#ibcon#read 4, iclass 36, count 2 2006.257.05:06:32.94#ibcon#about to read 5, iclass 36, count 2 2006.257.05:06:32.94#ibcon#read 5, iclass 36, count 2 2006.257.05:06:32.94#ibcon#about to read 6, iclass 36, count 2 2006.257.05:06:32.94#ibcon#read 6, iclass 36, count 2 2006.257.05:06:32.94#ibcon#end of sib2, iclass 36, count 2 2006.257.05:06:32.94#ibcon#*mode == 0, iclass 36, count 2 2006.257.05:06:32.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.05:06:32.94#ibcon#[25=AT04-07\r\n] 2006.257.05:06:32.94#ibcon#*before write, iclass 36, count 2 2006.257.05:06:32.94#ibcon#enter sib2, iclass 36, count 2 2006.257.05:06:32.94#ibcon#flushed, iclass 36, count 2 2006.257.05:06:32.94#ibcon#about to write, iclass 36, count 2 2006.257.05:06:32.94#ibcon#wrote, iclass 36, count 2 2006.257.05:06:32.94#ibcon#about to read 3, iclass 36, count 2 2006.257.05:06:32.97#ibcon#read 3, iclass 36, count 2 2006.257.05:06:32.97#ibcon#about to read 4, iclass 36, count 2 2006.257.05:06:32.97#ibcon#read 4, iclass 36, count 2 2006.257.05:06:32.97#ibcon#about to read 5, iclass 36, count 2 2006.257.05:06:32.97#ibcon#read 5, iclass 36, count 2 2006.257.05:06:32.97#ibcon#about to read 6, iclass 36, count 2 2006.257.05:06:32.97#ibcon#read 6, iclass 36, count 2 2006.257.05:06:32.97#ibcon#end of sib2, iclass 36, count 2 2006.257.05:06:32.97#ibcon#*after write, iclass 36, count 2 2006.257.05:06:32.97#ibcon#*before return 0, iclass 36, count 2 2006.257.05:06:32.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:32.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:32.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.05:06:32.97#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:32.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:33.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:33.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:33.09#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:06:33.09#ibcon#first serial, iclass 36, count 0 2006.257.05:06:33.09#ibcon#enter sib2, iclass 36, count 0 2006.257.05:06:33.09#ibcon#flushed, iclass 36, count 0 2006.257.05:06:33.09#ibcon#about to write, iclass 36, count 0 2006.257.05:06:33.09#ibcon#wrote, iclass 36, count 0 2006.257.05:06:33.09#ibcon#about to read 3, iclass 36, count 0 2006.257.05:06:33.11#ibcon#read 3, iclass 36, count 0 2006.257.05:06:33.11#ibcon#about to read 4, iclass 36, count 0 2006.257.05:06:33.11#ibcon#read 4, iclass 36, count 0 2006.257.05:06:33.11#ibcon#about to read 5, iclass 36, count 0 2006.257.05:06:33.11#ibcon#read 5, iclass 36, count 0 2006.257.05:06:33.11#ibcon#about to read 6, iclass 36, count 0 2006.257.05:06:33.11#ibcon#read 6, iclass 36, count 0 2006.257.05:06:33.11#ibcon#end of sib2, iclass 36, count 0 2006.257.05:06:33.11#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:06:33.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:06:33.11#ibcon#[25=USB\r\n] 2006.257.05:06:33.11#ibcon#*before write, iclass 36, count 0 2006.257.05:06:33.11#ibcon#enter sib2, iclass 36, count 0 2006.257.05:06:33.11#ibcon#flushed, iclass 36, count 0 2006.257.05:06:33.11#ibcon#about to write, iclass 36, count 0 2006.257.05:06:33.11#ibcon#wrote, iclass 36, count 0 2006.257.05:06:33.11#ibcon#about to read 3, iclass 36, count 0 2006.257.05:06:33.14#ibcon#read 3, iclass 36, count 0 2006.257.05:06:33.14#ibcon#about to read 4, iclass 36, count 0 2006.257.05:06:33.14#ibcon#read 4, iclass 36, count 0 2006.257.05:06:33.14#ibcon#about to read 5, iclass 36, count 0 2006.257.05:06:33.14#ibcon#read 5, iclass 36, count 0 2006.257.05:06:33.14#ibcon#about to read 6, iclass 36, count 0 2006.257.05:06:33.14#ibcon#read 6, iclass 36, count 0 2006.257.05:06:33.14#ibcon#end of sib2, iclass 36, count 0 2006.257.05:06:33.14#ibcon#*after write, iclass 36, count 0 2006.257.05:06:33.14#ibcon#*before return 0, iclass 36, count 0 2006.257.05:06:33.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:33.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:33.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:06:33.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:06:33.14$vck44/valo=5,734.99 2006.257.05:06:33.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.05:06:33.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.05:06:33.14#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:33.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:33.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:33.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:33.14#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:06:33.14#ibcon#first serial, iclass 38, count 0 2006.257.05:06:33.14#ibcon#enter sib2, iclass 38, count 0 2006.257.05:06:33.14#ibcon#flushed, iclass 38, count 0 2006.257.05:06:33.14#ibcon#about to write, iclass 38, count 0 2006.257.05:06:33.14#ibcon#wrote, iclass 38, count 0 2006.257.05:06:33.14#ibcon#about to read 3, iclass 38, count 0 2006.257.05:06:33.16#ibcon#read 3, iclass 38, count 0 2006.257.05:06:33.16#ibcon#about to read 4, iclass 38, count 0 2006.257.05:06:33.16#ibcon#read 4, iclass 38, count 0 2006.257.05:06:33.16#ibcon#about to read 5, iclass 38, count 0 2006.257.05:06:33.16#ibcon#read 5, iclass 38, count 0 2006.257.05:06:33.16#ibcon#about to read 6, iclass 38, count 0 2006.257.05:06:33.16#ibcon#read 6, iclass 38, count 0 2006.257.05:06:33.16#ibcon#end of sib2, iclass 38, count 0 2006.257.05:06:33.16#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:06:33.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:06:33.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:06:33.16#ibcon#*before write, iclass 38, count 0 2006.257.05:06:33.16#ibcon#enter sib2, iclass 38, count 0 2006.257.05:06:33.16#ibcon#flushed, iclass 38, count 0 2006.257.05:06:33.16#ibcon#about to write, iclass 38, count 0 2006.257.05:06:33.16#ibcon#wrote, iclass 38, count 0 2006.257.05:06:33.16#ibcon#about to read 3, iclass 38, count 0 2006.257.05:06:33.20#ibcon#read 3, iclass 38, count 0 2006.257.05:06:33.20#ibcon#about to read 4, iclass 38, count 0 2006.257.05:06:33.20#ibcon#read 4, iclass 38, count 0 2006.257.05:06:33.20#ibcon#about to read 5, iclass 38, count 0 2006.257.05:06:33.20#ibcon#read 5, iclass 38, count 0 2006.257.05:06:33.20#ibcon#about to read 6, iclass 38, count 0 2006.257.05:06:33.20#ibcon#read 6, iclass 38, count 0 2006.257.05:06:33.20#ibcon#end of sib2, iclass 38, count 0 2006.257.05:06:33.20#ibcon#*after write, iclass 38, count 0 2006.257.05:06:33.20#ibcon#*before return 0, iclass 38, count 0 2006.257.05:06:33.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:33.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:33.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:06:33.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:06:33.20$vck44/va=5,4 2006.257.05:06:33.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.05:06:33.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.05:06:33.20#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:33.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:33.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:33.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:33.26#ibcon#enter wrdev, iclass 40, count 2 2006.257.05:06:33.26#ibcon#first serial, iclass 40, count 2 2006.257.05:06:33.26#ibcon#enter sib2, iclass 40, count 2 2006.257.05:06:33.26#ibcon#flushed, iclass 40, count 2 2006.257.05:06:33.26#ibcon#about to write, iclass 40, count 2 2006.257.05:06:33.26#ibcon#wrote, iclass 40, count 2 2006.257.05:06:33.26#ibcon#about to read 3, iclass 40, count 2 2006.257.05:06:33.28#ibcon#read 3, iclass 40, count 2 2006.257.05:06:33.28#ibcon#about to read 4, iclass 40, count 2 2006.257.05:06:33.28#ibcon#read 4, iclass 40, count 2 2006.257.05:06:33.28#ibcon#about to read 5, iclass 40, count 2 2006.257.05:06:33.28#ibcon#read 5, iclass 40, count 2 2006.257.05:06:33.28#ibcon#about to read 6, iclass 40, count 2 2006.257.05:06:33.28#ibcon#read 6, iclass 40, count 2 2006.257.05:06:33.28#ibcon#end of sib2, iclass 40, count 2 2006.257.05:06:33.28#ibcon#*mode == 0, iclass 40, count 2 2006.257.05:06:33.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.05:06:33.28#ibcon#[25=AT05-04\r\n] 2006.257.05:06:33.28#ibcon#*before write, iclass 40, count 2 2006.257.05:06:33.28#ibcon#enter sib2, iclass 40, count 2 2006.257.05:06:33.28#ibcon#flushed, iclass 40, count 2 2006.257.05:06:33.28#ibcon#about to write, iclass 40, count 2 2006.257.05:06:33.28#ibcon#wrote, iclass 40, count 2 2006.257.05:06:33.28#ibcon#about to read 3, iclass 40, count 2 2006.257.05:06:33.31#ibcon#read 3, iclass 40, count 2 2006.257.05:06:33.31#ibcon#about to read 4, iclass 40, count 2 2006.257.05:06:33.31#ibcon#read 4, iclass 40, count 2 2006.257.05:06:33.31#ibcon#about to read 5, iclass 40, count 2 2006.257.05:06:33.31#ibcon#read 5, iclass 40, count 2 2006.257.05:06:33.31#ibcon#about to read 6, iclass 40, count 2 2006.257.05:06:33.31#ibcon#read 6, iclass 40, count 2 2006.257.05:06:33.31#ibcon#end of sib2, iclass 40, count 2 2006.257.05:06:33.31#ibcon#*after write, iclass 40, count 2 2006.257.05:06:33.31#ibcon#*before return 0, iclass 40, count 2 2006.257.05:06:33.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:33.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:33.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.05:06:33.31#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:33.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:33.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:33.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:33.43#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:06:33.43#ibcon#first serial, iclass 40, count 0 2006.257.05:06:33.43#ibcon#enter sib2, iclass 40, count 0 2006.257.05:06:33.43#ibcon#flushed, iclass 40, count 0 2006.257.05:06:33.43#ibcon#about to write, iclass 40, count 0 2006.257.05:06:33.43#ibcon#wrote, iclass 40, count 0 2006.257.05:06:33.43#ibcon#about to read 3, iclass 40, count 0 2006.257.05:06:33.45#ibcon#read 3, iclass 40, count 0 2006.257.05:06:33.45#ibcon#about to read 4, iclass 40, count 0 2006.257.05:06:33.45#ibcon#read 4, iclass 40, count 0 2006.257.05:06:33.45#ibcon#about to read 5, iclass 40, count 0 2006.257.05:06:33.45#ibcon#read 5, iclass 40, count 0 2006.257.05:06:33.45#ibcon#about to read 6, iclass 40, count 0 2006.257.05:06:33.45#ibcon#read 6, iclass 40, count 0 2006.257.05:06:33.45#ibcon#end of sib2, iclass 40, count 0 2006.257.05:06:33.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:06:33.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:06:33.45#ibcon#[25=USB\r\n] 2006.257.05:06:33.45#ibcon#*before write, iclass 40, count 0 2006.257.05:06:33.45#ibcon#enter sib2, iclass 40, count 0 2006.257.05:06:33.45#ibcon#flushed, iclass 40, count 0 2006.257.05:06:33.45#ibcon#about to write, iclass 40, count 0 2006.257.05:06:33.45#ibcon#wrote, iclass 40, count 0 2006.257.05:06:33.45#ibcon#about to read 3, iclass 40, count 0 2006.257.05:06:33.48#ibcon#read 3, iclass 40, count 0 2006.257.05:06:33.48#ibcon#about to read 4, iclass 40, count 0 2006.257.05:06:33.48#ibcon#read 4, iclass 40, count 0 2006.257.05:06:33.48#ibcon#about to read 5, iclass 40, count 0 2006.257.05:06:33.48#ibcon#read 5, iclass 40, count 0 2006.257.05:06:33.48#ibcon#about to read 6, iclass 40, count 0 2006.257.05:06:33.48#ibcon#read 6, iclass 40, count 0 2006.257.05:06:33.48#ibcon#end of sib2, iclass 40, count 0 2006.257.05:06:33.48#ibcon#*after write, iclass 40, count 0 2006.257.05:06:33.48#ibcon#*before return 0, iclass 40, count 0 2006.257.05:06:33.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:33.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:33.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:06:33.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:06:33.48$vck44/valo=6,814.99 2006.257.05:06:33.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.05:06:33.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.05:06:33.48#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:33.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:33.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:33.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:33.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:06:33.48#ibcon#first serial, iclass 4, count 0 2006.257.05:06:33.48#ibcon#enter sib2, iclass 4, count 0 2006.257.05:06:33.48#ibcon#flushed, iclass 4, count 0 2006.257.05:06:33.48#ibcon#about to write, iclass 4, count 0 2006.257.05:06:33.48#ibcon#wrote, iclass 4, count 0 2006.257.05:06:33.48#ibcon#about to read 3, iclass 4, count 0 2006.257.05:06:33.50#ibcon#read 3, iclass 4, count 0 2006.257.05:06:33.50#ibcon#about to read 4, iclass 4, count 0 2006.257.05:06:33.50#ibcon#read 4, iclass 4, count 0 2006.257.05:06:33.50#ibcon#about to read 5, iclass 4, count 0 2006.257.05:06:33.50#ibcon#read 5, iclass 4, count 0 2006.257.05:06:33.50#ibcon#about to read 6, iclass 4, count 0 2006.257.05:06:33.50#ibcon#read 6, iclass 4, count 0 2006.257.05:06:33.50#ibcon#end of sib2, iclass 4, count 0 2006.257.05:06:33.50#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:06:33.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:06:33.50#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:06:33.50#ibcon#*before write, iclass 4, count 0 2006.257.05:06:33.50#ibcon#enter sib2, iclass 4, count 0 2006.257.05:06:33.50#ibcon#flushed, iclass 4, count 0 2006.257.05:06:33.50#ibcon#about to write, iclass 4, count 0 2006.257.05:06:33.50#ibcon#wrote, iclass 4, count 0 2006.257.05:06:33.50#ibcon#about to read 3, iclass 4, count 0 2006.257.05:06:33.54#ibcon#read 3, iclass 4, count 0 2006.257.05:06:33.54#ibcon#about to read 4, iclass 4, count 0 2006.257.05:06:33.54#ibcon#read 4, iclass 4, count 0 2006.257.05:06:33.54#ibcon#about to read 5, iclass 4, count 0 2006.257.05:06:33.54#ibcon#read 5, iclass 4, count 0 2006.257.05:06:33.54#ibcon#about to read 6, iclass 4, count 0 2006.257.05:06:33.54#ibcon#read 6, iclass 4, count 0 2006.257.05:06:33.54#ibcon#end of sib2, iclass 4, count 0 2006.257.05:06:33.54#ibcon#*after write, iclass 4, count 0 2006.257.05:06:33.54#ibcon#*before return 0, iclass 4, count 0 2006.257.05:06:33.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:33.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:33.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:06:33.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:06:33.54$vck44/va=6,4 2006.257.05:06:33.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.05:06:33.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.05:06:33.54#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:33.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:33.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:33.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:33.60#ibcon#enter wrdev, iclass 6, count 2 2006.257.05:06:33.60#ibcon#first serial, iclass 6, count 2 2006.257.05:06:33.60#ibcon#enter sib2, iclass 6, count 2 2006.257.05:06:33.60#ibcon#flushed, iclass 6, count 2 2006.257.05:06:33.60#ibcon#about to write, iclass 6, count 2 2006.257.05:06:33.60#ibcon#wrote, iclass 6, count 2 2006.257.05:06:33.60#ibcon#about to read 3, iclass 6, count 2 2006.257.05:06:33.62#ibcon#read 3, iclass 6, count 2 2006.257.05:06:33.62#ibcon#about to read 4, iclass 6, count 2 2006.257.05:06:33.62#ibcon#read 4, iclass 6, count 2 2006.257.05:06:33.62#ibcon#about to read 5, iclass 6, count 2 2006.257.05:06:33.62#ibcon#read 5, iclass 6, count 2 2006.257.05:06:33.62#ibcon#about to read 6, iclass 6, count 2 2006.257.05:06:33.62#ibcon#read 6, iclass 6, count 2 2006.257.05:06:33.62#ibcon#end of sib2, iclass 6, count 2 2006.257.05:06:33.62#ibcon#*mode == 0, iclass 6, count 2 2006.257.05:06:33.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.05:06:33.62#ibcon#[25=AT06-04\r\n] 2006.257.05:06:33.62#ibcon#*before write, iclass 6, count 2 2006.257.05:06:33.62#ibcon#enter sib2, iclass 6, count 2 2006.257.05:06:33.62#ibcon#flushed, iclass 6, count 2 2006.257.05:06:33.62#ibcon#about to write, iclass 6, count 2 2006.257.05:06:33.62#ibcon#wrote, iclass 6, count 2 2006.257.05:06:33.62#ibcon#about to read 3, iclass 6, count 2 2006.257.05:06:33.65#ibcon#read 3, iclass 6, count 2 2006.257.05:06:33.65#ibcon#about to read 4, iclass 6, count 2 2006.257.05:06:33.65#ibcon#read 4, iclass 6, count 2 2006.257.05:06:33.65#ibcon#about to read 5, iclass 6, count 2 2006.257.05:06:33.65#ibcon#read 5, iclass 6, count 2 2006.257.05:06:33.65#ibcon#about to read 6, iclass 6, count 2 2006.257.05:06:33.65#ibcon#read 6, iclass 6, count 2 2006.257.05:06:33.65#ibcon#end of sib2, iclass 6, count 2 2006.257.05:06:33.65#ibcon#*after write, iclass 6, count 2 2006.257.05:06:33.65#ibcon#*before return 0, iclass 6, count 2 2006.257.05:06:33.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:33.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:33.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.05:06:33.65#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:33.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:33.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:33.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:33.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:06:33.77#ibcon#first serial, iclass 6, count 0 2006.257.05:06:33.77#ibcon#enter sib2, iclass 6, count 0 2006.257.05:06:33.77#ibcon#flushed, iclass 6, count 0 2006.257.05:06:33.77#ibcon#about to write, iclass 6, count 0 2006.257.05:06:33.77#ibcon#wrote, iclass 6, count 0 2006.257.05:06:33.77#ibcon#about to read 3, iclass 6, count 0 2006.257.05:06:33.79#ibcon#read 3, iclass 6, count 0 2006.257.05:06:33.79#ibcon#about to read 4, iclass 6, count 0 2006.257.05:06:33.79#ibcon#read 4, iclass 6, count 0 2006.257.05:06:33.79#ibcon#about to read 5, iclass 6, count 0 2006.257.05:06:33.79#ibcon#read 5, iclass 6, count 0 2006.257.05:06:33.79#ibcon#about to read 6, iclass 6, count 0 2006.257.05:06:33.79#ibcon#read 6, iclass 6, count 0 2006.257.05:06:33.79#ibcon#end of sib2, iclass 6, count 0 2006.257.05:06:33.79#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:06:33.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:06:33.79#ibcon#[25=USB\r\n] 2006.257.05:06:33.79#ibcon#*before write, iclass 6, count 0 2006.257.05:06:33.79#ibcon#enter sib2, iclass 6, count 0 2006.257.05:06:33.79#ibcon#flushed, iclass 6, count 0 2006.257.05:06:33.79#ibcon#about to write, iclass 6, count 0 2006.257.05:06:33.79#ibcon#wrote, iclass 6, count 0 2006.257.05:06:33.79#ibcon#about to read 3, iclass 6, count 0 2006.257.05:06:33.82#ibcon#read 3, iclass 6, count 0 2006.257.05:06:33.82#ibcon#about to read 4, iclass 6, count 0 2006.257.05:06:33.82#ibcon#read 4, iclass 6, count 0 2006.257.05:06:33.82#ibcon#about to read 5, iclass 6, count 0 2006.257.05:06:33.82#ibcon#read 5, iclass 6, count 0 2006.257.05:06:33.82#ibcon#about to read 6, iclass 6, count 0 2006.257.05:06:33.82#ibcon#read 6, iclass 6, count 0 2006.257.05:06:33.82#ibcon#end of sib2, iclass 6, count 0 2006.257.05:06:33.82#ibcon#*after write, iclass 6, count 0 2006.257.05:06:33.82#ibcon#*before return 0, iclass 6, count 0 2006.257.05:06:33.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:33.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:33.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:06:33.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:06:33.82$vck44/valo=7,864.99 2006.257.05:06:33.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.05:06:33.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.05:06:33.82#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:33.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:33.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:33.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:33.82#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:06:33.82#ibcon#first serial, iclass 10, count 0 2006.257.05:06:33.82#ibcon#enter sib2, iclass 10, count 0 2006.257.05:06:33.82#ibcon#flushed, iclass 10, count 0 2006.257.05:06:33.82#ibcon#about to write, iclass 10, count 0 2006.257.05:06:33.82#ibcon#wrote, iclass 10, count 0 2006.257.05:06:33.82#ibcon#about to read 3, iclass 10, count 0 2006.257.05:06:33.84#ibcon#read 3, iclass 10, count 0 2006.257.05:06:33.84#ibcon#about to read 4, iclass 10, count 0 2006.257.05:06:33.84#ibcon#read 4, iclass 10, count 0 2006.257.05:06:33.84#ibcon#about to read 5, iclass 10, count 0 2006.257.05:06:33.84#ibcon#read 5, iclass 10, count 0 2006.257.05:06:33.84#ibcon#about to read 6, iclass 10, count 0 2006.257.05:06:33.84#ibcon#read 6, iclass 10, count 0 2006.257.05:06:33.84#ibcon#end of sib2, iclass 10, count 0 2006.257.05:06:33.84#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:06:33.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:06:33.84#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:06:33.84#ibcon#*before write, iclass 10, count 0 2006.257.05:06:33.84#ibcon#enter sib2, iclass 10, count 0 2006.257.05:06:33.84#ibcon#flushed, iclass 10, count 0 2006.257.05:06:33.84#ibcon#about to write, iclass 10, count 0 2006.257.05:06:33.84#ibcon#wrote, iclass 10, count 0 2006.257.05:06:33.84#ibcon#about to read 3, iclass 10, count 0 2006.257.05:06:33.88#ibcon#read 3, iclass 10, count 0 2006.257.05:06:33.88#ibcon#about to read 4, iclass 10, count 0 2006.257.05:06:33.88#ibcon#read 4, iclass 10, count 0 2006.257.05:06:33.88#ibcon#about to read 5, iclass 10, count 0 2006.257.05:06:33.88#ibcon#read 5, iclass 10, count 0 2006.257.05:06:33.88#ibcon#about to read 6, iclass 10, count 0 2006.257.05:06:33.88#ibcon#read 6, iclass 10, count 0 2006.257.05:06:33.88#ibcon#end of sib2, iclass 10, count 0 2006.257.05:06:33.88#ibcon#*after write, iclass 10, count 0 2006.257.05:06:33.88#ibcon#*before return 0, iclass 10, count 0 2006.257.05:06:33.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:33.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:33.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:06:33.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:06:33.88$vck44/va=7,4 2006.257.05:06:33.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.05:06:33.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.05:06:33.88#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:33.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:33.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:33.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:33.94#ibcon#enter wrdev, iclass 12, count 2 2006.257.05:06:33.94#ibcon#first serial, iclass 12, count 2 2006.257.05:06:33.94#ibcon#enter sib2, iclass 12, count 2 2006.257.05:06:33.94#ibcon#flushed, iclass 12, count 2 2006.257.05:06:33.94#ibcon#about to write, iclass 12, count 2 2006.257.05:06:33.94#ibcon#wrote, iclass 12, count 2 2006.257.05:06:33.94#ibcon#about to read 3, iclass 12, count 2 2006.257.05:06:33.96#ibcon#read 3, iclass 12, count 2 2006.257.05:06:33.96#ibcon#about to read 4, iclass 12, count 2 2006.257.05:06:33.96#ibcon#read 4, iclass 12, count 2 2006.257.05:06:33.96#ibcon#about to read 5, iclass 12, count 2 2006.257.05:06:33.96#ibcon#read 5, iclass 12, count 2 2006.257.05:06:33.96#ibcon#about to read 6, iclass 12, count 2 2006.257.05:06:33.96#ibcon#read 6, iclass 12, count 2 2006.257.05:06:33.96#ibcon#end of sib2, iclass 12, count 2 2006.257.05:06:33.96#ibcon#*mode == 0, iclass 12, count 2 2006.257.05:06:33.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.05:06:33.96#ibcon#[25=AT07-04\r\n] 2006.257.05:06:33.96#ibcon#*before write, iclass 12, count 2 2006.257.05:06:33.96#ibcon#enter sib2, iclass 12, count 2 2006.257.05:06:33.96#ibcon#flushed, iclass 12, count 2 2006.257.05:06:33.96#ibcon#about to write, iclass 12, count 2 2006.257.05:06:33.96#ibcon#wrote, iclass 12, count 2 2006.257.05:06:33.96#ibcon#about to read 3, iclass 12, count 2 2006.257.05:06:33.99#ibcon#read 3, iclass 12, count 2 2006.257.05:06:33.99#ibcon#about to read 4, iclass 12, count 2 2006.257.05:06:33.99#ibcon#read 4, iclass 12, count 2 2006.257.05:06:33.99#ibcon#about to read 5, iclass 12, count 2 2006.257.05:06:33.99#ibcon#read 5, iclass 12, count 2 2006.257.05:06:33.99#ibcon#about to read 6, iclass 12, count 2 2006.257.05:06:33.99#ibcon#read 6, iclass 12, count 2 2006.257.05:06:33.99#ibcon#end of sib2, iclass 12, count 2 2006.257.05:06:33.99#ibcon#*after write, iclass 12, count 2 2006.257.05:06:33.99#ibcon#*before return 0, iclass 12, count 2 2006.257.05:06:33.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:33.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:33.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.05:06:33.99#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:33.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:34.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:34.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:34.11#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:06:34.11#ibcon#first serial, iclass 12, count 0 2006.257.05:06:34.11#ibcon#enter sib2, iclass 12, count 0 2006.257.05:06:34.11#ibcon#flushed, iclass 12, count 0 2006.257.05:06:34.11#ibcon#about to write, iclass 12, count 0 2006.257.05:06:34.11#ibcon#wrote, iclass 12, count 0 2006.257.05:06:34.11#ibcon#about to read 3, iclass 12, count 0 2006.257.05:06:34.13#ibcon#read 3, iclass 12, count 0 2006.257.05:06:34.13#ibcon#about to read 4, iclass 12, count 0 2006.257.05:06:34.13#ibcon#read 4, iclass 12, count 0 2006.257.05:06:34.13#ibcon#about to read 5, iclass 12, count 0 2006.257.05:06:34.13#ibcon#read 5, iclass 12, count 0 2006.257.05:06:34.13#ibcon#about to read 6, iclass 12, count 0 2006.257.05:06:34.13#ibcon#read 6, iclass 12, count 0 2006.257.05:06:34.13#ibcon#end of sib2, iclass 12, count 0 2006.257.05:06:34.13#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:06:34.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:06:34.13#ibcon#[25=USB\r\n] 2006.257.05:06:34.13#ibcon#*before write, iclass 12, count 0 2006.257.05:06:34.13#ibcon#enter sib2, iclass 12, count 0 2006.257.05:06:34.13#ibcon#flushed, iclass 12, count 0 2006.257.05:06:34.13#ibcon#about to write, iclass 12, count 0 2006.257.05:06:34.13#ibcon#wrote, iclass 12, count 0 2006.257.05:06:34.13#ibcon#about to read 3, iclass 12, count 0 2006.257.05:06:34.16#ibcon#read 3, iclass 12, count 0 2006.257.05:06:34.16#ibcon#about to read 4, iclass 12, count 0 2006.257.05:06:34.16#ibcon#read 4, iclass 12, count 0 2006.257.05:06:34.16#ibcon#about to read 5, iclass 12, count 0 2006.257.05:06:34.16#ibcon#read 5, iclass 12, count 0 2006.257.05:06:34.16#ibcon#about to read 6, iclass 12, count 0 2006.257.05:06:34.16#ibcon#read 6, iclass 12, count 0 2006.257.05:06:34.16#ibcon#end of sib2, iclass 12, count 0 2006.257.05:06:34.16#ibcon#*after write, iclass 12, count 0 2006.257.05:06:34.16#ibcon#*before return 0, iclass 12, count 0 2006.257.05:06:34.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:34.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:34.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:06:34.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:06:34.16$vck44/valo=8,884.99 2006.257.05:06:34.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.05:06:34.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.05:06:34.16#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:34.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:34.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:34.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:34.16#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:06:34.16#ibcon#first serial, iclass 14, count 0 2006.257.05:06:34.16#ibcon#enter sib2, iclass 14, count 0 2006.257.05:06:34.16#ibcon#flushed, iclass 14, count 0 2006.257.05:06:34.16#ibcon#about to write, iclass 14, count 0 2006.257.05:06:34.16#ibcon#wrote, iclass 14, count 0 2006.257.05:06:34.16#ibcon#about to read 3, iclass 14, count 0 2006.257.05:06:34.18#ibcon#read 3, iclass 14, count 0 2006.257.05:06:34.18#ibcon#about to read 4, iclass 14, count 0 2006.257.05:06:34.18#ibcon#read 4, iclass 14, count 0 2006.257.05:06:34.18#ibcon#about to read 5, iclass 14, count 0 2006.257.05:06:34.18#ibcon#read 5, iclass 14, count 0 2006.257.05:06:34.18#ibcon#about to read 6, iclass 14, count 0 2006.257.05:06:34.18#ibcon#read 6, iclass 14, count 0 2006.257.05:06:34.18#ibcon#end of sib2, iclass 14, count 0 2006.257.05:06:34.18#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:06:34.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:06:34.18#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:06:34.18#ibcon#*before write, iclass 14, count 0 2006.257.05:06:34.18#ibcon#enter sib2, iclass 14, count 0 2006.257.05:06:34.18#ibcon#flushed, iclass 14, count 0 2006.257.05:06:34.18#ibcon#about to write, iclass 14, count 0 2006.257.05:06:34.18#ibcon#wrote, iclass 14, count 0 2006.257.05:06:34.18#ibcon#about to read 3, iclass 14, count 0 2006.257.05:06:34.22#ibcon#read 3, iclass 14, count 0 2006.257.05:06:34.22#ibcon#about to read 4, iclass 14, count 0 2006.257.05:06:34.22#ibcon#read 4, iclass 14, count 0 2006.257.05:06:34.22#ibcon#about to read 5, iclass 14, count 0 2006.257.05:06:34.22#ibcon#read 5, iclass 14, count 0 2006.257.05:06:34.22#ibcon#about to read 6, iclass 14, count 0 2006.257.05:06:34.22#ibcon#read 6, iclass 14, count 0 2006.257.05:06:34.22#ibcon#end of sib2, iclass 14, count 0 2006.257.05:06:34.22#ibcon#*after write, iclass 14, count 0 2006.257.05:06:34.22#ibcon#*before return 0, iclass 14, count 0 2006.257.05:06:34.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:34.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:34.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:06:34.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:06:34.22$vck44/va=8,4 2006.257.05:06:34.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.05:06:34.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.05:06:34.22#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:34.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:34.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:34.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:34.28#ibcon#enter wrdev, iclass 16, count 2 2006.257.05:06:34.28#ibcon#first serial, iclass 16, count 2 2006.257.05:06:34.28#ibcon#enter sib2, iclass 16, count 2 2006.257.05:06:34.28#ibcon#flushed, iclass 16, count 2 2006.257.05:06:34.28#ibcon#about to write, iclass 16, count 2 2006.257.05:06:34.28#ibcon#wrote, iclass 16, count 2 2006.257.05:06:34.28#ibcon#about to read 3, iclass 16, count 2 2006.257.05:06:34.30#ibcon#read 3, iclass 16, count 2 2006.257.05:06:34.30#ibcon#about to read 4, iclass 16, count 2 2006.257.05:06:34.30#ibcon#read 4, iclass 16, count 2 2006.257.05:06:34.30#ibcon#about to read 5, iclass 16, count 2 2006.257.05:06:34.30#ibcon#read 5, iclass 16, count 2 2006.257.05:06:34.30#ibcon#about to read 6, iclass 16, count 2 2006.257.05:06:34.30#ibcon#read 6, iclass 16, count 2 2006.257.05:06:34.30#ibcon#end of sib2, iclass 16, count 2 2006.257.05:06:34.30#ibcon#*mode == 0, iclass 16, count 2 2006.257.05:06:34.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.05:06:34.30#ibcon#[25=AT08-04\r\n] 2006.257.05:06:34.30#ibcon#*before write, iclass 16, count 2 2006.257.05:06:34.30#ibcon#enter sib2, iclass 16, count 2 2006.257.05:06:34.30#ibcon#flushed, iclass 16, count 2 2006.257.05:06:34.30#ibcon#about to write, iclass 16, count 2 2006.257.05:06:34.30#ibcon#wrote, iclass 16, count 2 2006.257.05:06:34.30#ibcon#about to read 3, iclass 16, count 2 2006.257.05:06:34.33#ibcon#read 3, iclass 16, count 2 2006.257.05:06:34.33#ibcon#about to read 4, iclass 16, count 2 2006.257.05:06:34.33#ibcon#read 4, iclass 16, count 2 2006.257.05:06:34.33#ibcon#about to read 5, iclass 16, count 2 2006.257.05:06:34.33#ibcon#read 5, iclass 16, count 2 2006.257.05:06:34.33#ibcon#about to read 6, iclass 16, count 2 2006.257.05:06:34.33#ibcon#read 6, iclass 16, count 2 2006.257.05:06:34.33#ibcon#end of sib2, iclass 16, count 2 2006.257.05:06:34.33#ibcon#*after write, iclass 16, count 2 2006.257.05:06:34.33#ibcon#*before return 0, iclass 16, count 2 2006.257.05:06:34.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:34.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:34.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.05:06:34.33#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:34.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:34.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:34.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:34.45#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:06:34.45#ibcon#first serial, iclass 16, count 0 2006.257.05:06:34.45#ibcon#enter sib2, iclass 16, count 0 2006.257.05:06:34.45#ibcon#flushed, iclass 16, count 0 2006.257.05:06:34.45#ibcon#about to write, iclass 16, count 0 2006.257.05:06:34.45#ibcon#wrote, iclass 16, count 0 2006.257.05:06:34.45#ibcon#about to read 3, iclass 16, count 0 2006.257.05:06:34.47#ibcon#read 3, iclass 16, count 0 2006.257.05:06:34.47#ibcon#about to read 4, iclass 16, count 0 2006.257.05:06:34.47#ibcon#read 4, iclass 16, count 0 2006.257.05:06:34.47#ibcon#about to read 5, iclass 16, count 0 2006.257.05:06:34.47#ibcon#read 5, iclass 16, count 0 2006.257.05:06:34.47#ibcon#about to read 6, iclass 16, count 0 2006.257.05:06:34.47#ibcon#read 6, iclass 16, count 0 2006.257.05:06:34.47#ibcon#end of sib2, iclass 16, count 0 2006.257.05:06:34.47#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:06:34.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:06:34.47#ibcon#[25=USB\r\n] 2006.257.05:06:34.47#ibcon#*before write, iclass 16, count 0 2006.257.05:06:34.47#ibcon#enter sib2, iclass 16, count 0 2006.257.05:06:34.47#ibcon#flushed, iclass 16, count 0 2006.257.05:06:34.47#ibcon#about to write, iclass 16, count 0 2006.257.05:06:34.47#ibcon#wrote, iclass 16, count 0 2006.257.05:06:34.47#ibcon#about to read 3, iclass 16, count 0 2006.257.05:06:34.50#ibcon#read 3, iclass 16, count 0 2006.257.05:06:34.50#ibcon#about to read 4, iclass 16, count 0 2006.257.05:06:34.50#ibcon#read 4, iclass 16, count 0 2006.257.05:06:34.50#ibcon#about to read 5, iclass 16, count 0 2006.257.05:06:34.50#ibcon#read 5, iclass 16, count 0 2006.257.05:06:34.50#ibcon#about to read 6, iclass 16, count 0 2006.257.05:06:34.50#ibcon#read 6, iclass 16, count 0 2006.257.05:06:34.50#ibcon#end of sib2, iclass 16, count 0 2006.257.05:06:34.50#ibcon#*after write, iclass 16, count 0 2006.257.05:06:34.50#ibcon#*before return 0, iclass 16, count 0 2006.257.05:06:34.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:34.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:34.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:06:34.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:06:34.50$vck44/vblo=1,629.99 2006.257.05:06:34.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.05:06:34.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.05:06:34.50#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:34.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:34.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:34.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:34.50#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:06:34.50#ibcon#first serial, iclass 18, count 0 2006.257.05:06:34.50#ibcon#enter sib2, iclass 18, count 0 2006.257.05:06:34.50#ibcon#flushed, iclass 18, count 0 2006.257.05:06:34.50#ibcon#about to write, iclass 18, count 0 2006.257.05:06:34.50#ibcon#wrote, iclass 18, count 0 2006.257.05:06:34.50#ibcon#about to read 3, iclass 18, count 0 2006.257.05:06:34.52#ibcon#read 3, iclass 18, count 0 2006.257.05:06:34.52#ibcon#about to read 4, iclass 18, count 0 2006.257.05:06:34.52#ibcon#read 4, iclass 18, count 0 2006.257.05:06:34.52#ibcon#about to read 5, iclass 18, count 0 2006.257.05:06:34.52#ibcon#read 5, iclass 18, count 0 2006.257.05:06:34.52#ibcon#about to read 6, iclass 18, count 0 2006.257.05:06:34.52#ibcon#read 6, iclass 18, count 0 2006.257.05:06:34.52#ibcon#end of sib2, iclass 18, count 0 2006.257.05:06:34.52#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:06:34.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:06:34.52#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:06:34.52#ibcon#*before write, iclass 18, count 0 2006.257.05:06:34.52#ibcon#enter sib2, iclass 18, count 0 2006.257.05:06:34.52#ibcon#flushed, iclass 18, count 0 2006.257.05:06:34.52#ibcon#about to write, iclass 18, count 0 2006.257.05:06:34.52#ibcon#wrote, iclass 18, count 0 2006.257.05:06:34.52#ibcon#about to read 3, iclass 18, count 0 2006.257.05:06:34.56#ibcon#read 3, iclass 18, count 0 2006.257.05:06:34.56#ibcon#about to read 4, iclass 18, count 0 2006.257.05:06:34.56#ibcon#read 4, iclass 18, count 0 2006.257.05:06:34.56#ibcon#about to read 5, iclass 18, count 0 2006.257.05:06:34.56#ibcon#read 5, iclass 18, count 0 2006.257.05:06:34.56#ibcon#about to read 6, iclass 18, count 0 2006.257.05:06:34.56#ibcon#read 6, iclass 18, count 0 2006.257.05:06:34.56#ibcon#end of sib2, iclass 18, count 0 2006.257.05:06:34.56#ibcon#*after write, iclass 18, count 0 2006.257.05:06:34.56#ibcon#*before return 0, iclass 18, count 0 2006.257.05:06:34.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:34.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:34.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:06:34.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:06:34.56$vck44/vb=1,4 2006.257.05:06:34.56#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.05:06:34.56#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.05:06:34.56#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:34.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:06:34.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:06:34.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:06:34.56#ibcon#enter wrdev, iclass 21, count 2 2006.257.05:06:34.56#ibcon#first serial, iclass 21, count 2 2006.257.05:06:34.56#ibcon#enter sib2, iclass 21, count 2 2006.257.05:06:34.56#ibcon#flushed, iclass 21, count 2 2006.257.05:06:34.56#ibcon#about to write, iclass 21, count 2 2006.257.05:06:34.56#ibcon#wrote, iclass 21, count 2 2006.257.05:06:34.56#ibcon#about to read 3, iclass 21, count 2 2006.257.05:06:34.58#ibcon#read 3, iclass 21, count 2 2006.257.05:06:34.58#ibcon#about to read 4, iclass 21, count 2 2006.257.05:06:34.58#ibcon#read 4, iclass 21, count 2 2006.257.05:06:34.58#ibcon#about to read 5, iclass 21, count 2 2006.257.05:06:34.58#ibcon#read 5, iclass 21, count 2 2006.257.05:06:34.58#ibcon#about to read 6, iclass 21, count 2 2006.257.05:06:34.58#ibcon#read 6, iclass 21, count 2 2006.257.05:06:34.58#ibcon#end of sib2, iclass 21, count 2 2006.257.05:06:34.58#ibcon#*mode == 0, iclass 21, count 2 2006.257.05:06:34.58#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.05:06:34.58#ibcon#[27=AT01-04\r\n] 2006.257.05:06:34.58#ibcon#*before write, iclass 21, count 2 2006.257.05:06:34.58#ibcon#enter sib2, iclass 21, count 2 2006.257.05:06:34.58#ibcon#flushed, iclass 21, count 2 2006.257.05:06:34.58#ibcon#about to write, iclass 21, count 2 2006.257.05:06:34.58#ibcon#wrote, iclass 21, count 2 2006.257.05:06:34.58#ibcon#about to read 3, iclass 21, count 2 2006.257.05:06:34.59#abcon#<5=/15 1.6 3.8 19.67 921012.0\r\n> 2006.257.05:06:34.61#abcon#{5=INTERFACE CLEAR} 2006.257.05:06:34.61#ibcon#read 3, iclass 21, count 2 2006.257.05:06:34.61#ibcon#about to read 4, iclass 21, count 2 2006.257.05:06:34.61#ibcon#read 4, iclass 21, count 2 2006.257.05:06:34.61#ibcon#about to read 5, iclass 21, count 2 2006.257.05:06:34.61#ibcon#read 5, iclass 21, count 2 2006.257.05:06:34.61#ibcon#about to read 6, iclass 21, count 2 2006.257.05:06:34.61#ibcon#read 6, iclass 21, count 2 2006.257.05:06:34.61#ibcon#end of sib2, iclass 21, count 2 2006.257.05:06:34.61#ibcon#*after write, iclass 21, count 2 2006.257.05:06:34.61#ibcon#*before return 0, iclass 21, count 2 2006.257.05:06:34.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:06:34.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:06:34.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.05:06:34.61#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:34.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:06:34.67#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:06:34.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:06:34.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:06:34.73#ibcon#enter wrdev, iclass 21, count 0 2006.257.05:06:34.73#ibcon#first serial, iclass 21, count 0 2006.257.05:06:34.73#ibcon#enter sib2, iclass 21, count 0 2006.257.05:06:34.73#ibcon#flushed, iclass 21, count 0 2006.257.05:06:34.73#ibcon#about to write, iclass 21, count 0 2006.257.05:06:34.73#ibcon#wrote, iclass 21, count 0 2006.257.05:06:34.73#ibcon#about to read 3, iclass 21, count 0 2006.257.05:06:34.75#ibcon#read 3, iclass 21, count 0 2006.257.05:06:34.75#ibcon#about to read 4, iclass 21, count 0 2006.257.05:06:34.75#ibcon#read 4, iclass 21, count 0 2006.257.05:06:34.75#ibcon#about to read 5, iclass 21, count 0 2006.257.05:06:34.75#ibcon#read 5, iclass 21, count 0 2006.257.05:06:34.75#ibcon#about to read 6, iclass 21, count 0 2006.257.05:06:34.75#ibcon#read 6, iclass 21, count 0 2006.257.05:06:34.75#ibcon#end of sib2, iclass 21, count 0 2006.257.05:06:34.75#ibcon#*mode == 0, iclass 21, count 0 2006.257.05:06:34.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.05:06:34.75#ibcon#[27=USB\r\n] 2006.257.05:06:34.75#ibcon#*before write, iclass 21, count 0 2006.257.05:06:34.75#ibcon#enter sib2, iclass 21, count 0 2006.257.05:06:34.75#ibcon#flushed, iclass 21, count 0 2006.257.05:06:34.75#ibcon#about to write, iclass 21, count 0 2006.257.05:06:34.75#ibcon#wrote, iclass 21, count 0 2006.257.05:06:34.75#ibcon#about to read 3, iclass 21, count 0 2006.257.05:06:34.78#ibcon#read 3, iclass 21, count 0 2006.257.05:06:34.78#ibcon#about to read 4, iclass 21, count 0 2006.257.05:06:34.78#ibcon#read 4, iclass 21, count 0 2006.257.05:06:34.78#ibcon#about to read 5, iclass 21, count 0 2006.257.05:06:34.78#ibcon#read 5, iclass 21, count 0 2006.257.05:06:34.78#ibcon#about to read 6, iclass 21, count 0 2006.257.05:06:34.78#ibcon#read 6, iclass 21, count 0 2006.257.05:06:34.78#ibcon#end of sib2, iclass 21, count 0 2006.257.05:06:34.78#ibcon#*after write, iclass 21, count 0 2006.257.05:06:34.78#ibcon#*before return 0, iclass 21, count 0 2006.257.05:06:34.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:06:34.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:06:34.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.05:06:34.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.05:06:34.78$vck44/vblo=2,634.99 2006.257.05:06:34.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.05:06:34.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.05:06:34.78#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:34.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:34.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:34.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:34.78#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:06:34.78#ibcon#first serial, iclass 26, count 0 2006.257.05:06:34.78#ibcon#enter sib2, iclass 26, count 0 2006.257.05:06:34.78#ibcon#flushed, iclass 26, count 0 2006.257.05:06:34.78#ibcon#about to write, iclass 26, count 0 2006.257.05:06:34.78#ibcon#wrote, iclass 26, count 0 2006.257.05:06:34.78#ibcon#about to read 3, iclass 26, count 0 2006.257.05:06:34.80#ibcon#read 3, iclass 26, count 0 2006.257.05:06:34.80#ibcon#about to read 4, iclass 26, count 0 2006.257.05:06:34.80#ibcon#read 4, iclass 26, count 0 2006.257.05:06:34.80#ibcon#about to read 5, iclass 26, count 0 2006.257.05:06:34.80#ibcon#read 5, iclass 26, count 0 2006.257.05:06:34.80#ibcon#about to read 6, iclass 26, count 0 2006.257.05:06:34.80#ibcon#read 6, iclass 26, count 0 2006.257.05:06:34.80#ibcon#end of sib2, iclass 26, count 0 2006.257.05:06:34.80#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:06:34.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:06:34.80#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:06:34.80#ibcon#*before write, iclass 26, count 0 2006.257.05:06:34.80#ibcon#enter sib2, iclass 26, count 0 2006.257.05:06:34.80#ibcon#flushed, iclass 26, count 0 2006.257.05:06:34.80#ibcon#about to write, iclass 26, count 0 2006.257.05:06:34.80#ibcon#wrote, iclass 26, count 0 2006.257.05:06:34.80#ibcon#about to read 3, iclass 26, count 0 2006.257.05:06:34.84#ibcon#read 3, iclass 26, count 0 2006.257.05:06:34.84#ibcon#about to read 4, iclass 26, count 0 2006.257.05:06:34.84#ibcon#read 4, iclass 26, count 0 2006.257.05:06:34.84#ibcon#about to read 5, iclass 26, count 0 2006.257.05:06:34.84#ibcon#read 5, iclass 26, count 0 2006.257.05:06:34.84#ibcon#about to read 6, iclass 26, count 0 2006.257.05:06:34.84#ibcon#read 6, iclass 26, count 0 2006.257.05:06:34.84#ibcon#end of sib2, iclass 26, count 0 2006.257.05:06:34.84#ibcon#*after write, iclass 26, count 0 2006.257.05:06:34.84#ibcon#*before return 0, iclass 26, count 0 2006.257.05:06:34.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:34.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:06:34.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:06:34.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:06:34.84$vck44/vb=2,5 2006.257.05:06:34.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.05:06:34.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.05:06:34.84#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:34.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:34.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:34.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:34.90#ibcon#enter wrdev, iclass 28, count 2 2006.257.05:06:34.90#ibcon#first serial, iclass 28, count 2 2006.257.05:06:34.90#ibcon#enter sib2, iclass 28, count 2 2006.257.05:06:34.90#ibcon#flushed, iclass 28, count 2 2006.257.05:06:34.90#ibcon#about to write, iclass 28, count 2 2006.257.05:06:34.90#ibcon#wrote, iclass 28, count 2 2006.257.05:06:34.90#ibcon#about to read 3, iclass 28, count 2 2006.257.05:06:34.92#ibcon#read 3, iclass 28, count 2 2006.257.05:06:34.92#ibcon#about to read 4, iclass 28, count 2 2006.257.05:06:34.92#ibcon#read 4, iclass 28, count 2 2006.257.05:06:34.92#ibcon#about to read 5, iclass 28, count 2 2006.257.05:06:34.92#ibcon#read 5, iclass 28, count 2 2006.257.05:06:34.92#ibcon#about to read 6, iclass 28, count 2 2006.257.05:06:34.92#ibcon#read 6, iclass 28, count 2 2006.257.05:06:34.92#ibcon#end of sib2, iclass 28, count 2 2006.257.05:06:34.92#ibcon#*mode == 0, iclass 28, count 2 2006.257.05:06:34.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.05:06:34.92#ibcon#[27=AT02-05\r\n] 2006.257.05:06:34.92#ibcon#*before write, iclass 28, count 2 2006.257.05:06:34.92#ibcon#enter sib2, iclass 28, count 2 2006.257.05:06:34.92#ibcon#flushed, iclass 28, count 2 2006.257.05:06:34.92#ibcon#about to write, iclass 28, count 2 2006.257.05:06:34.92#ibcon#wrote, iclass 28, count 2 2006.257.05:06:34.92#ibcon#about to read 3, iclass 28, count 2 2006.257.05:06:34.95#ibcon#read 3, iclass 28, count 2 2006.257.05:06:34.95#ibcon#about to read 4, iclass 28, count 2 2006.257.05:06:34.95#ibcon#read 4, iclass 28, count 2 2006.257.05:06:34.95#ibcon#about to read 5, iclass 28, count 2 2006.257.05:06:34.95#ibcon#read 5, iclass 28, count 2 2006.257.05:06:34.95#ibcon#about to read 6, iclass 28, count 2 2006.257.05:06:34.95#ibcon#read 6, iclass 28, count 2 2006.257.05:06:34.95#ibcon#end of sib2, iclass 28, count 2 2006.257.05:06:34.95#ibcon#*after write, iclass 28, count 2 2006.257.05:06:34.95#ibcon#*before return 0, iclass 28, count 2 2006.257.05:06:34.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:34.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:06:34.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.05:06:34.95#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:34.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:35.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:35.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:35.07#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:06:35.07#ibcon#first serial, iclass 28, count 0 2006.257.05:06:35.07#ibcon#enter sib2, iclass 28, count 0 2006.257.05:06:35.07#ibcon#flushed, iclass 28, count 0 2006.257.05:06:35.07#ibcon#about to write, iclass 28, count 0 2006.257.05:06:35.07#ibcon#wrote, iclass 28, count 0 2006.257.05:06:35.07#ibcon#about to read 3, iclass 28, count 0 2006.257.05:06:35.09#ibcon#read 3, iclass 28, count 0 2006.257.05:06:35.09#ibcon#about to read 4, iclass 28, count 0 2006.257.05:06:35.09#ibcon#read 4, iclass 28, count 0 2006.257.05:06:35.09#ibcon#about to read 5, iclass 28, count 0 2006.257.05:06:35.09#ibcon#read 5, iclass 28, count 0 2006.257.05:06:35.09#ibcon#about to read 6, iclass 28, count 0 2006.257.05:06:35.09#ibcon#read 6, iclass 28, count 0 2006.257.05:06:35.09#ibcon#end of sib2, iclass 28, count 0 2006.257.05:06:35.09#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:06:35.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:06:35.09#ibcon#[27=USB\r\n] 2006.257.05:06:35.09#ibcon#*before write, iclass 28, count 0 2006.257.05:06:35.09#ibcon#enter sib2, iclass 28, count 0 2006.257.05:06:35.09#ibcon#flushed, iclass 28, count 0 2006.257.05:06:35.09#ibcon#about to write, iclass 28, count 0 2006.257.05:06:35.09#ibcon#wrote, iclass 28, count 0 2006.257.05:06:35.09#ibcon#about to read 3, iclass 28, count 0 2006.257.05:06:35.12#ibcon#read 3, iclass 28, count 0 2006.257.05:06:35.12#ibcon#about to read 4, iclass 28, count 0 2006.257.05:06:35.12#ibcon#read 4, iclass 28, count 0 2006.257.05:06:35.12#ibcon#about to read 5, iclass 28, count 0 2006.257.05:06:35.12#ibcon#read 5, iclass 28, count 0 2006.257.05:06:35.12#ibcon#about to read 6, iclass 28, count 0 2006.257.05:06:35.12#ibcon#read 6, iclass 28, count 0 2006.257.05:06:35.12#ibcon#end of sib2, iclass 28, count 0 2006.257.05:06:35.12#ibcon#*after write, iclass 28, count 0 2006.257.05:06:35.12#ibcon#*before return 0, iclass 28, count 0 2006.257.05:06:35.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:35.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:06:35.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:06:35.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:06:35.12$vck44/vblo=3,649.99 2006.257.05:06:35.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.05:06:35.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.05:06:35.12#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:35.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:35.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:35.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:35.12#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:06:35.12#ibcon#first serial, iclass 30, count 0 2006.257.05:06:35.12#ibcon#enter sib2, iclass 30, count 0 2006.257.05:06:35.12#ibcon#flushed, iclass 30, count 0 2006.257.05:06:35.12#ibcon#about to write, iclass 30, count 0 2006.257.05:06:35.12#ibcon#wrote, iclass 30, count 0 2006.257.05:06:35.12#ibcon#about to read 3, iclass 30, count 0 2006.257.05:06:35.14#ibcon#read 3, iclass 30, count 0 2006.257.05:06:35.14#ibcon#about to read 4, iclass 30, count 0 2006.257.05:06:35.14#ibcon#read 4, iclass 30, count 0 2006.257.05:06:35.14#ibcon#about to read 5, iclass 30, count 0 2006.257.05:06:35.14#ibcon#read 5, iclass 30, count 0 2006.257.05:06:35.14#ibcon#about to read 6, iclass 30, count 0 2006.257.05:06:35.14#ibcon#read 6, iclass 30, count 0 2006.257.05:06:35.14#ibcon#end of sib2, iclass 30, count 0 2006.257.05:06:35.14#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:06:35.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:06:35.14#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:06:35.14#ibcon#*before write, iclass 30, count 0 2006.257.05:06:35.14#ibcon#enter sib2, iclass 30, count 0 2006.257.05:06:35.14#ibcon#flushed, iclass 30, count 0 2006.257.05:06:35.14#ibcon#about to write, iclass 30, count 0 2006.257.05:06:35.14#ibcon#wrote, iclass 30, count 0 2006.257.05:06:35.14#ibcon#about to read 3, iclass 30, count 0 2006.257.05:06:35.18#ibcon#read 3, iclass 30, count 0 2006.257.05:06:35.18#ibcon#about to read 4, iclass 30, count 0 2006.257.05:06:35.18#ibcon#read 4, iclass 30, count 0 2006.257.05:06:35.18#ibcon#about to read 5, iclass 30, count 0 2006.257.05:06:35.18#ibcon#read 5, iclass 30, count 0 2006.257.05:06:35.18#ibcon#about to read 6, iclass 30, count 0 2006.257.05:06:35.18#ibcon#read 6, iclass 30, count 0 2006.257.05:06:35.18#ibcon#end of sib2, iclass 30, count 0 2006.257.05:06:35.18#ibcon#*after write, iclass 30, count 0 2006.257.05:06:35.18#ibcon#*before return 0, iclass 30, count 0 2006.257.05:06:35.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:35.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:06:35.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:06:35.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:06:35.18$vck44/vb=3,4 2006.257.05:06:35.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.05:06:35.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.05:06:35.18#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:35.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:35.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:35.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:35.24#ibcon#enter wrdev, iclass 32, count 2 2006.257.05:06:35.24#ibcon#first serial, iclass 32, count 2 2006.257.05:06:35.24#ibcon#enter sib2, iclass 32, count 2 2006.257.05:06:35.24#ibcon#flushed, iclass 32, count 2 2006.257.05:06:35.24#ibcon#about to write, iclass 32, count 2 2006.257.05:06:35.24#ibcon#wrote, iclass 32, count 2 2006.257.05:06:35.24#ibcon#about to read 3, iclass 32, count 2 2006.257.05:06:35.26#ibcon#read 3, iclass 32, count 2 2006.257.05:06:35.26#ibcon#about to read 4, iclass 32, count 2 2006.257.05:06:35.26#ibcon#read 4, iclass 32, count 2 2006.257.05:06:35.26#ibcon#about to read 5, iclass 32, count 2 2006.257.05:06:35.26#ibcon#read 5, iclass 32, count 2 2006.257.05:06:35.26#ibcon#about to read 6, iclass 32, count 2 2006.257.05:06:35.26#ibcon#read 6, iclass 32, count 2 2006.257.05:06:35.26#ibcon#end of sib2, iclass 32, count 2 2006.257.05:06:35.26#ibcon#*mode == 0, iclass 32, count 2 2006.257.05:06:35.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.05:06:35.26#ibcon#[27=AT03-04\r\n] 2006.257.05:06:35.26#ibcon#*before write, iclass 32, count 2 2006.257.05:06:35.26#ibcon#enter sib2, iclass 32, count 2 2006.257.05:06:35.26#ibcon#flushed, iclass 32, count 2 2006.257.05:06:35.26#ibcon#about to write, iclass 32, count 2 2006.257.05:06:35.26#ibcon#wrote, iclass 32, count 2 2006.257.05:06:35.26#ibcon#about to read 3, iclass 32, count 2 2006.257.05:06:35.29#ibcon#read 3, iclass 32, count 2 2006.257.05:06:35.29#ibcon#about to read 4, iclass 32, count 2 2006.257.05:06:35.29#ibcon#read 4, iclass 32, count 2 2006.257.05:06:35.29#ibcon#about to read 5, iclass 32, count 2 2006.257.05:06:35.29#ibcon#read 5, iclass 32, count 2 2006.257.05:06:35.29#ibcon#about to read 6, iclass 32, count 2 2006.257.05:06:35.29#ibcon#read 6, iclass 32, count 2 2006.257.05:06:35.29#ibcon#end of sib2, iclass 32, count 2 2006.257.05:06:35.29#ibcon#*after write, iclass 32, count 2 2006.257.05:06:35.29#ibcon#*before return 0, iclass 32, count 2 2006.257.05:06:35.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:35.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:06:35.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.05:06:35.29#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:35.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:35.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:35.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:35.41#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:06:35.41#ibcon#first serial, iclass 32, count 0 2006.257.05:06:35.41#ibcon#enter sib2, iclass 32, count 0 2006.257.05:06:35.41#ibcon#flushed, iclass 32, count 0 2006.257.05:06:35.41#ibcon#about to write, iclass 32, count 0 2006.257.05:06:35.41#ibcon#wrote, iclass 32, count 0 2006.257.05:06:35.41#ibcon#about to read 3, iclass 32, count 0 2006.257.05:06:35.43#ibcon#read 3, iclass 32, count 0 2006.257.05:06:35.43#ibcon#about to read 4, iclass 32, count 0 2006.257.05:06:35.43#ibcon#read 4, iclass 32, count 0 2006.257.05:06:35.43#ibcon#about to read 5, iclass 32, count 0 2006.257.05:06:35.43#ibcon#read 5, iclass 32, count 0 2006.257.05:06:35.43#ibcon#about to read 6, iclass 32, count 0 2006.257.05:06:35.43#ibcon#read 6, iclass 32, count 0 2006.257.05:06:35.43#ibcon#end of sib2, iclass 32, count 0 2006.257.05:06:35.43#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:06:35.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:06:35.43#ibcon#[27=USB\r\n] 2006.257.05:06:35.43#ibcon#*before write, iclass 32, count 0 2006.257.05:06:35.43#ibcon#enter sib2, iclass 32, count 0 2006.257.05:06:35.43#ibcon#flushed, iclass 32, count 0 2006.257.05:06:35.43#ibcon#about to write, iclass 32, count 0 2006.257.05:06:35.43#ibcon#wrote, iclass 32, count 0 2006.257.05:06:35.43#ibcon#about to read 3, iclass 32, count 0 2006.257.05:06:35.46#ibcon#read 3, iclass 32, count 0 2006.257.05:06:35.46#ibcon#about to read 4, iclass 32, count 0 2006.257.05:06:35.46#ibcon#read 4, iclass 32, count 0 2006.257.05:06:35.46#ibcon#about to read 5, iclass 32, count 0 2006.257.05:06:35.46#ibcon#read 5, iclass 32, count 0 2006.257.05:06:35.46#ibcon#about to read 6, iclass 32, count 0 2006.257.05:06:35.46#ibcon#read 6, iclass 32, count 0 2006.257.05:06:35.46#ibcon#end of sib2, iclass 32, count 0 2006.257.05:06:35.46#ibcon#*after write, iclass 32, count 0 2006.257.05:06:35.46#ibcon#*before return 0, iclass 32, count 0 2006.257.05:06:35.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:35.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:06:35.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:06:35.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:06:35.46$vck44/vblo=4,679.99 2006.257.05:06:35.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.05:06:35.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.05:06:35.46#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:35.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:35.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:35.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:35.46#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:06:35.46#ibcon#first serial, iclass 34, count 0 2006.257.05:06:35.46#ibcon#enter sib2, iclass 34, count 0 2006.257.05:06:35.46#ibcon#flushed, iclass 34, count 0 2006.257.05:06:35.46#ibcon#about to write, iclass 34, count 0 2006.257.05:06:35.46#ibcon#wrote, iclass 34, count 0 2006.257.05:06:35.46#ibcon#about to read 3, iclass 34, count 0 2006.257.05:06:35.48#ibcon#read 3, iclass 34, count 0 2006.257.05:06:35.48#ibcon#about to read 4, iclass 34, count 0 2006.257.05:06:35.48#ibcon#read 4, iclass 34, count 0 2006.257.05:06:35.48#ibcon#about to read 5, iclass 34, count 0 2006.257.05:06:35.48#ibcon#read 5, iclass 34, count 0 2006.257.05:06:35.48#ibcon#about to read 6, iclass 34, count 0 2006.257.05:06:35.48#ibcon#read 6, iclass 34, count 0 2006.257.05:06:35.48#ibcon#end of sib2, iclass 34, count 0 2006.257.05:06:35.48#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:06:35.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:06:35.48#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:06:35.48#ibcon#*before write, iclass 34, count 0 2006.257.05:06:35.48#ibcon#enter sib2, iclass 34, count 0 2006.257.05:06:35.48#ibcon#flushed, iclass 34, count 0 2006.257.05:06:35.48#ibcon#about to write, iclass 34, count 0 2006.257.05:06:35.48#ibcon#wrote, iclass 34, count 0 2006.257.05:06:35.48#ibcon#about to read 3, iclass 34, count 0 2006.257.05:06:35.52#ibcon#read 3, iclass 34, count 0 2006.257.05:06:35.52#ibcon#about to read 4, iclass 34, count 0 2006.257.05:06:35.52#ibcon#read 4, iclass 34, count 0 2006.257.05:06:35.52#ibcon#about to read 5, iclass 34, count 0 2006.257.05:06:35.52#ibcon#read 5, iclass 34, count 0 2006.257.05:06:35.52#ibcon#about to read 6, iclass 34, count 0 2006.257.05:06:35.52#ibcon#read 6, iclass 34, count 0 2006.257.05:06:35.52#ibcon#end of sib2, iclass 34, count 0 2006.257.05:06:35.52#ibcon#*after write, iclass 34, count 0 2006.257.05:06:35.52#ibcon#*before return 0, iclass 34, count 0 2006.257.05:06:35.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:35.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:06:35.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:06:35.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:06:35.52$vck44/vb=4,5 2006.257.05:06:35.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.05:06:35.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.05:06:35.52#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:35.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:35.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:35.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:35.58#ibcon#enter wrdev, iclass 36, count 2 2006.257.05:06:35.58#ibcon#first serial, iclass 36, count 2 2006.257.05:06:35.58#ibcon#enter sib2, iclass 36, count 2 2006.257.05:06:35.58#ibcon#flushed, iclass 36, count 2 2006.257.05:06:35.58#ibcon#about to write, iclass 36, count 2 2006.257.05:06:35.58#ibcon#wrote, iclass 36, count 2 2006.257.05:06:35.58#ibcon#about to read 3, iclass 36, count 2 2006.257.05:06:35.60#ibcon#read 3, iclass 36, count 2 2006.257.05:06:35.60#ibcon#about to read 4, iclass 36, count 2 2006.257.05:06:35.60#ibcon#read 4, iclass 36, count 2 2006.257.05:06:35.60#ibcon#about to read 5, iclass 36, count 2 2006.257.05:06:35.60#ibcon#read 5, iclass 36, count 2 2006.257.05:06:35.60#ibcon#about to read 6, iclass 36, count 2 2006.257.05:06:35.60#ibcon#read 6, iclass 36, count 2 2006.257.05:06:35.60#ibcon#end of sib2, iclass 36, count 2 2006.257.05:06:35.60#ibcon#*mode == 0, iclass 36, count 2 2006.257.05:06:35.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.05:06:35.60#ibcon#[27=AT04-05\r\n] 2006.257.05:06:35.60#ibcon#*before write, iclass 36, count 2 2006.257.05:06:35.60#ibcon#enter sib2, iclass 36, count 2 2006.257.05:06:35.60#ibcon#flushed, iclass 36, count 2 2006.257.05:06:35.60#ibcon#about to write, iclass 36, count 2 2006.257.05:06:35.60#ibcon#wrote, iclass 36, count 2 2006.257.05:06:35.60#ibcon#about to read 3, iclass 36, count 2 2006.257.05:06:35.63#ibcon#read 3, iclass 36, count 2 2006.257.05:06:35.63#ibcon#about to read 4, iclass 36, count 2 2006.257.05:06:35.63#ibcon#read 4, iclass 36, count 2 2006.257.05:06:35.63#ibcon#about to read 5, iclass 36, count 2 2006.257.05:06:35.63#ibcon#read 5, iclass 36, count 2 2006.257.05:06:35.63#ibcon#about to read 6, iclass 36, count 2 2006.257.05:06:35.63#ibcon#read 6, iclass 36, count 2 2006.257.05:06:35.63#ibcon#end of sib2, iclass 36, count 2 2006.257.05:06:35.63#ibcon#*after write, iclass 36, count 2 2006.257.05:06:35.63#ibcon#*before return 0, iclass 36, count 2 2006.257.05:06:35.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:35.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:06:35.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.05:06:35.63#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:35.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:35.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:35.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:35.75#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:06:35.75#ibcon#first serial, iclass 36, count 0 2006.257.05:06:35.75#ibcon#enter sib2, iclass 36, count 0 2006.257.05:06:35.75#ibcon#flushed, iclass 36, count 0 2006.257.05:06:35.75#ibcon#about to write, iclass 36, count 0 2006.257.05:06:35.75#ibcon#wrote, iclass 36, count 0 2006.257.05:06:35.75#ibcon#about to read 3, iclass 36, count 0 2006.257.05:06:35.77#ibcon#read 3, iclass 36, count 0 2006.257.05:06:35.77#ibcon#about to read 4, iclass 36, count 0 2006.257.05:06:35.77#ibcon#read 4, iclass 36, count 0 2006.257.05:06:35.77#ibcon#about to read 5, iclass 36, count 0 2006.257.05:06:35.77#ibcon#read 5, iclass 36, count 0 2006.257.05:06:35.77#ibcon#about to read 6, iclass 36, count 0 2006.257.05:06:35.77#ibcon#read 6, iclass 36, count 0 2006.257.05:06:35.77#ibcon#end of sib2, iclass 36, count 0 2006.257.05:06:35.77#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:06:35.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:06:35.77#ibcon#[27=USB\r\n] 2006.257.05:06:35.77#ibcon#*before write, iclass 36, count 0 2006.257.05:06:35.77#ibcon#enter sib2, iclass 36, count 0 2006.257.05:06:35.77#ibcon#flushed, iclass 36, count 0 2006.257.05:06:35.77#ibcon#about to write, iclass 36, count 0 2006.257.05:06:35.77#ibcon#wrote, iclass 36, count 0 2006.257.05:06:35.77#ibcon#about to read 3, iclass 36, count 0 2006.257.05:06:35.80#ibcon#read 3, iclass 36, count 0 2006.257.05:06:35.80#ibcon#about to read 4, iclass 36, count 0 2006.257.05:06:35.80#ibcon#read 4, iclass 36, count 0 2006.257.05:06:35.80#ibcon#about to read 5, iclass 36, count 0 2006.257.05:06:35.80#ibcon#read 5, iclass 36, count 0 2006.257.05:06:35.80#ibcon#about to read 6, iclass 36, count 0 2006.257.05:06:35.80#ibcon#read 6, iclass 36, count 0 2006.257.05:06:35.80#ibcon#end of sib2, iclass 36, count 0 2006.257.05:06:35.80#ibcon#*after write, iclass 36, count 0 2006.257.05:06:35.80#ibcon#*before return 0, iclass 36, count 0 2006.257.05:06:35.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:35.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:06:35.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:06:35.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:06:35.80$vck44/vblo=5,709.99 2006.257.05:06:35.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.05:06:35.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.05:06:35.80#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:35.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:35.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:35.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:35.80#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:06:35.80#ibcon#first serial, iclass 38, count 0 2006.257.05:06:35.80#ibcon#enter sib2, iclass 38, count 0 2006.257.05:06:35.80#ibcon#flushed, iclass 38, count 0 2006.257.05:06:35.80#ibcon#about to write, iclass 38, count 0 2006.257.05:06:35.80#ibcon#wrote, iclass 38, count 0 2006.257.05:06:35.80#ibcon#about to read 3, iclass 38, count 0 2006.257.05:06:35.82#ibcon#read 3, iclass 38, count 0 2006.257.05:06:35.82#ibcon#about to read 4, iclass 38, count 0 2006.257.05:06:35.82#ibcon#read 4, iclass 38, count 0 2006.257.05:06:35.82#ibcon#about to read 5, iclass 38, count 0 2006.257.05:06:35.82#ibcon#read 5, iclass 38, count 0 2006.257.05:06:35.82#ibcon#about to read 6, iclass 38, count 0 2006.257.05:06:35.82#ibcon#read 6, iclass 38, count 0 2006.257.05:06:35.82#ibcon#end of sib2, iclass 38, count 0 2006.257.05:06:35.82#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:06:35.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:06:35.82#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:06:35.82#ibcon#*before write, iclass 38, count 0 2006.257.05:06:35.82#ibcon#enter sib2, iclass 38, count 0 2006.257.05:06:35.82#ibcon#flushed, iclass 38, count 0 2006.257.05:06:35.82#ibcon#about to write, iclass 38, count 0 2006.257.05:06:35.82#ibcon#wrote, iclass 38, count 0 2006.257.05:06:35.82#ibcon#about to read 3, iclass 38, count 0 2006.257.05:06:35.86#ibcon#read 3, iclass 38, count 0 2006.257.05:06:35.86#ibcon#about to read 4, iclass 38, count 0 2006.257.05:06:35.86#ibcon#read 4, iclass 38, count 0 2006.257.05:06:35.86#ibcon#about to read 5, iclass 38, count 0 2006.257.05:06:35.86#ibcon#read 5, iclass 38, count 0 2006.257.05:06:35.86#ibcon#about to read 6, iclass 38, count 0 2006.257.05:06:35.86#ibcon#read 6, iclass 38, count 0 2006.257.05:06:35.86#ibcon#end of sib2, iclass 38, count 0 2006.257.05:06:35.86#ibcon#*after write, iclass 38, count 0 2006.257.05:06:35.86#ibcon#*before return 0, iclass 38, count 0 2006.257.05:06:35.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:35.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:06:35.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:06:35.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:06:35.86$vck44/vb=5,4 2006.257.05:06:35.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.05:06:35.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.05:06:35.86#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:35.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:35.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:35.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:35.92#ibcon#enter wrdev, iclass 40, count 2 2006.257.05:06:35.92#ibcon#first serial, iclass 40, count 2 2006.257.05:06:35.92#ibcon#enter sib2, iclass 40, count 2 2006.257.05:06:35.92#ibcon#flushed, iclass 40, count 2 2006.257.05:06:35.92#ibcon#about to write, iclass 40, count 2 2006.257.05:06:35.92#ibcon#wrote, iclass 40, count 2 2006.257.05:06:35.92#ibcon#about to read 3, iclass 40, count 2 2006.257.05:06:35.94#ibcon#read 3, iclass 40, count 2 2006.257.05:06:35.94#ibcon#about to read 4, iclass 40, count 2 2006.257.05:06:35.94#ibcon#read 4, iclass 40, count 2 2006.257.05:06:35.94#ibcon#about to read 5, iclass 40, count 2 2006.257.05:06:35.94#ibcon#read 5, iclass 40, count 2 2006.257.05:06:35.94#ibcon#about to read 6, iclass 40, count 2 2006.257.05:06:35.94#ibcon#read 6, iclass 40, count 2 2006.257.05:06:35.94#ibcon#end of sib2, iclass 40, count 2 2006.257.05:06:35.94#ibcon#*mode == 0, iclass 40, count 2 2006.257.05:06:35.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.05:06:35.94#ibcon#[27=AT05-04\r\n] 2006.257.05:06:35.94#ibcon#*before write, iclass 40, count 2 2006.257.05:06:35.94#ibcon#enter sib2, iclass 40, count 2 2006.257.05:06:35.94#ibcon#flushed, iclass 40, count 2 2006.257.05:06:35.94#ibcon#about to write, iclass 40, count 2 2006.257.05:06:35.94#ibcon#wrote, iclass 40, count 2 2006.257.05:06:35.94#ibcon#about to read 3, iclass 40, count 2 2006.257.05:06:35.97#ibcon#read 3, iclass 40, count 2 2006.257.05:06:35.97#ibcon#about to read 4, iclass 40, count 2 2006.257.05:06:35.97#ibcon#read 4, iclass 40, count 2 2006.257.05:06:35.97#ibcon#about to read 5, iclass 40, count 2 2006.257.05:06:35.97#ibcon#read 5, iclass 40, count 2 2006.257.05:06:35.97#ibcon#about to read 6, iclass 40, count 2 2006.257.05:06:35.97#ibcon#read 6, iclass 40, count 2 2006.257.05:06:35.97#ibcon#end of sib2, iclass 40, count 2 2006.257.05:06:35.97#ibcon#*after write, iclass 40, count 2 2006.257.05:06:35.97#ibcon#*before return 0, iclass 40, count 2 2006.257.05:06:35.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:35.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:06:35.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.05:06:35.97#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:35.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:36.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:36.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:36.09#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:06:36.09#ibcon#first serial, iclass 40, count 0 2006.257.05:06:36.09#ibcon#enter sib2, iclass 40, count 0 2006.257.05:06:36.09#ibcon#flushed, iclass 40, count 0 2006.257.05:06:36.09#ibcon#about to write, iclass 40, count 0 2006.257.05:06:36.09#ibcon#wrote, iclass 40, count 0 2006.257.05:06:36.09#ibcon#about to read 3, iclass 40, count 0 2006.257.05:06:36.11#ibcon#read 3, iclass 40, count 0 2006.257.05:06:36.11#ibcon#about to read 4, iclass 40, count 0 2006.257.05:06:36.11#ibcon#read 4, iclass 40, count 0 2006.257.05:06:36.11#ibcon#about to read 5, iclass 40, count 0 2006.257.05:06:36.11#ibcon#read 5, iclass 40, count 0 2006.257.05:06:36.11#ibcon#about to read 6, iclass 40, count 0 2006.257.05:06:36.11#ibcon#read 6, iclass 40, count 0 2006.257.05:06:36.11#ibcon#end of sib2, iclass 40, count 0 2006.257.05:06:36.11#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:06:36.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:06:36.11#ibcon#[27=USB\r\n] 2006.257.05:06:36.11#ibcon#*before write, iclass 40, count 0 2006.257.05:06:36.11#ibcon#enter sib2, iclass 40, count 0 2006.257.05:06:36.11#ibcon#flushed, iclass 40, count 0 2006.257.05:06:36.11#ibcon#about to write, iclass 40, count 0 2006.257.05:06:36.11#ibcon#wrote, iclass 40, count 0 2006.257.05:06:36.11#ibcon#about to read 3, iclass 40, count 0 2006.257.05:06:36.14#ibcon#read 3, iclass 40, count 0 2006.257.05:06:36.14#ibcon#about to read 4, iclass 40, count 0 2006.257.05:06:36.14#ibcon#read 4, iclass 40, count 0 2006.257.05:06:36.14#ibcon#about to read 5, iclass 40, count 0 2006.257.05:06:36.14#ibcon#read 5, iclass 40, count 0 2006.257.05:06:36.14#ibcon#about to read 6, iclass 40, count 0 2006.257.05:06:36.14#ibcon#read 6, iclass 40, count 0 2006.257.05:06:36.14#ibcon#end of sib2, iclass 40, count 0 2006.257.05:06:36.14#ibcon#*after write, iclass 40, count 0 2006.257.05:06:36.14#ibcon#*before return 0, iclass 40, count 0 2006.257.05:06:36.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:36.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:06:36.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:06:36.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:06:36.14$vck44/vblo=6,719.99 2006.257.05:06:36.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.05:06:36.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.05:06:36.14#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:36.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:36.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:36.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:36.14#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:06:36.14#ibcon#first serial, iclass 4, count 0 2006.257.05:06:36.14#ibcon#enter sib2, iclass 4, count 0 2006.257.05:06:36.14#ibcon#flushed, iclass 4, count 0 2006.257.05:06:36.14#ibcon#about to write, iclass 4, count 0 2006.257.05:06:36.14#ibcon#wrote, iclass 4, count 0 2006.257.05:06:36.14#ibcon#about to read 3, iclass 4, count 0 2006.257.05:06:36.16#ibcon#read 3, iclass 4, count 0 2006.257.05:06:36.16#ibcon#about to read 4, iclass 4, count 0 2006.257.05:06:36.16#ibcon#read 4, iclass 4, count 0 2006.257.05:06:36.16#ibcon#about to read 5, iclass 4, count 0 2006.257.05:06:36.16#ibcon#read 5, iclass 4, count 0 2006.257.05:06:36.16#ibcon#about to read 6, iclass 4, count 0 2006.257.05:06:36.16#ibcon#read 6, iclass 4, count 0 2006.257.05:06:36.16#ibcon#end of sib2, iclass 4, count 0 2006.257.05:06:36.16#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:06:36.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:06:36.16#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:06:36.16#ibcon#*before write, iclass 4, count 0 2006.257.05:06:36.16#ibcon#enter sib2, iclass 4, count 0 2006.257.05:06:36.16#ibcon#flushed, iclass 4, count 0 2006.257.05:06:36.16#ibcon#about to write, iclass 4, count 0 2006.257.05:06:36.16#ibcon#wrote, iclass 4, count 0 2006.257.05:06:36.16#ibcon#about to read 3, iclass 4, count 0 2006.257.05:06:36.20#ibcon#read 3, iclass 4, count 0 2006.257.05:06:36.20#ibcon#about to read 4, iclass 4, count 0 2006.257.05:06:36.20#ibcon#read 4, iclass 4, count 0 2006.257.05:06:36.20#ibcon#about to read 5, iclass 4, count 0 2006.257.05:06:36.20#ibcon#read 5, iclass 4, count 0 2006.257.05:06:36.20#ibcon#about to read 6, iclass 4, count 0 2006.257.05:06:36.20#ibcon#read 6, iclass 4, count 0 2006.257.05:06:36.20#ibcon#end of sib2, iclass 4, count 0 2006.257.05:06:36.20#ibcon#*after write, iclass 4, count 0 2006.257.05:06:36.20#ibcon#*before return 0, iclass 4, count 0 2006.257.05:06:36.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:36.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:06:36.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:06:36.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:06:36.20$vck44/vb=6,4 2006.257.05:06:36.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.05:06:36.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.05:06:36.20#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:36.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:36.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:36.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:36.26#ibcon#enter wrdev, iclass 6, count 2 2006.257.05:06:36.26#ibcon#first serial, iclass 6, count 2 2006.257.05:06:36.26#ibcon#enter sib2, iclass 6, count 2 2006.257.05:06:36.26#ibcon#flushed, iclass 6, count 2 2006.257.05:06:36.26#ibcon#about to write, iclass 6, count 2 2006.257.05:06:36.26#ibcon#wrote, iclass 6, count 2 2006.257.05:06:36.26#ibcon#about to read 3, iclass 6, count 2 2006.257.05:06:36.28#ibcon#read 3, iclass 6, count 2 2006.257.05:06:36.28#ibcon#about to read 4, iclass 6, count 2 2006.257.05:06:36.28#ibcon#read 4, iclass 6, count 2 2006.257.05:06:36.28#ibcon#about to read 5, iclass 6, count 2 2006.257.05:06:36.28#ibcon#read 5, iclass 6, count 2 2006.257.05:06:36.28#ibcon#about to read 6, iclass 6, count 2 2006.257.05:06:36.28#ibcon#read 6, iclass 6, count 2 2006.257.05:06:36.28#ibcon#end of sib2, iclass 6, count 2 2006.257.05:06:36.28#ibcon#*mode == 0, iclass 6, count 2 2006.257.05:06:36.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.05:06:36.28#ibcon#[27=AT06-04\r\n] 2006.257.05:06:36.28#ibcon#*before write, iclass 6, count 2 2006.257.05:06:36.28#ibcon#enter sib2, iclass 6, count 2 2006.257.05:06:36.28#ibcon#flushed, iclass 6, count 2 2006.257.05:06:36.28#ibcon#about to write, iclass 6, count 2 2006.257.05:06:36.28#ibcon#wrote, iclass 6, count 2 2006.257.05:06:36.28#ibcon#about to read 3, iclass 6, count 2 2006.257.05:06:36.31#ibcon#read 3, iclass 6, count 2 2006.257.05:06:36.31#ibcon#about to read 4, iclass 6, count 2 2006.257.05:06:36.31#ibcon#read 4, iclass 6, count 2 2006.257.05:06:36.31#ibcon#about to read 5, iclass 6, count 2 2006.257.05:06:36.31#ibcon#read 5, iclass 6, count 2 2006.257.05:06:36.31#ibcon#about to read 6, iclass 6, count 2 2006.257.05:06:36.31#ibcon#read 6, iclass 6, count 2 2006.257.05:06:36.31#ibcon#end of sib2, iclass 6, count 2 2006.257.05:06:36.31#ibcon#*after write, iclass 6, count 2 2006.257.05:06:36.31#ibcon#*before return 0, iclass 6, count 2 2006.257.05:06:36.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:36.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:06:36.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.05:06:36.31#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:36.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:36.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:36.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:36.43#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:06:36.43#ibcon#first serial, iclass 6, count 0 2006.257.05:06:36.43#ibcon#enter sib2, iclass 6, count 0 2006.257.05:06:36.43#ibcon#flushed, iclass 6, count 0 2006.257.05:06:36.43#ibcon#about to write, iclass 6, count 0 2006.257.05:06:36.43#ibcon#wrote, iclass 6, count 0 2006.257.05:06:36.43#ibcon#about to read 3, iclass 6, count 0 2006.257.05:06:36.45#ibcon#read 3, iclass 6, count 0 2006.257.05:06:36.45#ibcon#about to read 4, iclass 6, count 0 2006.257.05:06:36.45#ibcon#read 4, iclass 6, count 0 2006.257.05:06:36.45#ibcon#about to read 5, iclass 6, count 0 2006.257.05:06:36.45#ibcon#read 5, iclass 6, count 0 2006.257.05:06:36.45#ibcon#about to read 6, iclass 6, count 0 2006.257.05:06:36.45#ibcon#read 6, iclass 6, count 0 2006.257.05:06:36.45#ibcon#end of sib2, iclass 6, count 0 2006.257.05:06:36.45#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:06:36.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:06:36.45#ibcon#[27=USB\r\n] 2006.257.05:06:36.45#ibcon#*before write, iclass 6, count 0 2006.257.05:06:36.45#ibcon#enter sib2, iclass 6, count 0 2006.257.05:06:36.45#ibcon#flushed, iclass 6, count 0 2006.257.05:06:36.45#ibcon#about to write, iclass 6, count 0 2006.257.05:06:36.45#ibcon#wrote, iclass 6, count 0 2006.257.05:06:36.45#ibcon#about to read 3, iclass 6, count 0 2006.257.05:06:36.48#ibcon#read 3, iclass 6, count 0 2006.257.05:06:36.48#ibcon#about to read 4, iclass 6, count 0 2006.257.05:06:36.48#ibcon#read 4, iclass 6, count 0 2006.257.05:06:36.48#ibcon#about to read 5, iclass 6, count 0 2006.257.05:06:36.48#ibcon#read 5, iclass 6, count 0 2006.257.05:06:36.48#ibcon#about to read 6, iclass 6, count 0 2006.257.05:06:36.48#ibcon#read 6, iclass 6, count 0 2006.257.05:06:36.48#ibcon#end of sib2, iclass 6, count 0 2006.257.05:06:36.48#ibcon#*after write, iclass 6, count 0 2006.257.05:06:36.48#ibcon#*before return 0, iclass 6, count 0 2006.257.05:06:36.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:36.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:06:36.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:06:36.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:06:36.48$vck44/vblo=7,734.99 2006.257.05:06:36.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.05:06:36.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.05:06:36.48#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:36.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:36.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:36.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:36.48#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:06:36.48#ibcon#first serial, iclass 10, count 0 2006.257.05:06:36.48#ibcon#enter sib2, iclass 10, count 0 2006.257.05:06:36.48#ibcon#flushed, iclass 10, count 0 2006.257.05:06:36.48#ibcon#about to write, iclass 10, count 0 2006.257.05:06:36.48#ibcon#wrote, iclass 10, count 0 2006.257.05:06:36.48#ibcon#about to read 3, iclass 10, count 0 2006.257.05:06:36.50#ibcon#read 3, iclass 10, count 0 2006.257.05:06:36.50#ibcon#about to read 4, iclass 10, count 0 2006.257.05:06:36.50#ibcon#read 4, iclass 10, count 0 2006.257.05:06:36.50#ibcon#about to read 5, iclass 10, count 0 2006.257.05:06:36.50#ibcon#read 5, iclass 10, count 0 2006.257.05:06:36.50#ibcon#about to read 6, iclass 10, count 0 2006.257.05:06:36.50#ibcon#read 6, iclass 10, count 0 2006.257.05:06:36.50#ibcon#end of sib2, iclass 10, count 0 2006.257.05:06:36.50#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:06:36.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:06:36.50#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:06:36.50#ibcon#*before write, iclass 10, count 0 2006.257.05:06:36.50#ibcon#enter sib2, iclass 10, count 0 2006.257.05:06:36.50#ibcon#flushed, iclass 10, count 0 2006.257.05:06:36.50#ibcon#about to write, iclass 10, count 0 2006.257.05:06:36.50#ibcon#wrote, iclass 10, count 0 2006.257.05:06:36.50#ibcon#about to read 3, iclass 10, count 0 2006.257.05:06:36.54#ibcon#read 3, iclass 10, count 0 2006.257.05:06:36.54#ibcon#about to read 4, iclass 10, count 0 2006.257.05:06:36.54#ibcon#read 4, iclass 10, count 0 2006.257.05:06:36.54#ibcon#about to read 5, iclass 10, count 0 2006.257.05:06:36.54#ibcon#read 5, iclass 10, count 0 2006.257.05:06:36.54#ibcon#about to read 6, iclass 10, count 0 2006.257.05:06:36.54#ibcon#read 6, iclass 10, count 0 2006.257.05:06:36.54#ibcon#end of sib2, iclass 10, count 0 2006.257.05:06:36.54#ibcon#*after write, iclass 10, count 0 2006.257.05:06:36.54#ibcon#*before return 0, iclass 10, count 0 2006.257.05:06:36.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:36.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:06:36.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:06:36.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:06:36.54$vck44/vb=7,4 2006.257.05:06:36.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.05:06:36.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.05:06:36.54#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:36.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:36.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:36.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:36.60#ibcon#enter wrdev, iclass 12, count 2 2006.257.05:06:36.60#ibcon#first serial, iclass 12, count 2 2006.257.05:06:36.60#ibcon#enter sib2, iclass 12, count 2 2006.257.05:06:36.60#ibcon#flushed, iclass 12, count 2 2006.257.05:06:36.60#ibcon#about to write, iclass 12, count 2 2006.257.05:06:36.60#ibcon#wrote, iclass 12, count 2 2006.257.05:06:36.60#ibcon#about to read 3, iclass 12, count 2 2006.257.05:06:36.62#ibcon#read 3, iclass 12, count 2 2006.257.05:06:36.62#ibcon#about to read 4, iclass 12, count 2 2006.257.05:06:36.62#ibcon#read 4, iclass 12, count 2 2006.257.05:06:36.62#ibcon#about to read 5, iclass 12, count 2 2006.257.05:06:36.62#ibcon#read 5, iclass 12, count 2 2006.257.05:06:36.62#ibcon#about to read 6, iclass 12, count 2 2006.257.05:06:36.62#ibcon#read 6, iclass 12, count 2 2006.257.05:06:36.62#ibcon#end of sib2, iclass 12, count 2 2006.257.05:06:36.62#ibcon#*mode == 0, iclass 12, count 2 2006.257.05:06:36.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.05:06:36.62#ibcon#[27=AT07-04\r\n] 2006.257.05:06:36.62#ibcon#*before write, iclass 12, count 2 2006.257.05:06:36.62#ibcon#enter sib2, iclass 12, count 2 2006.257.05:06:36.62#ibcon#flushed, iclass 12, count 2 2006.257.05:06:36.62#ibcon#about to write, iclass 12, count 2 2006.257.05:06:36.62#ibcon#wrote, iclass 12, count 2 2006.257.05:06:36.62#ibcon#about to read 3, iclass 12, count 2 2006.257.05:06:36.65#ibcon#read 3, iclass 12, count 2 2006.257.05:06:36.65#ibcon#about to read 4, iclass 12, count 2 2006.257.05:06:36.65#ibcon#read 4, iclass 12, count 2 2006.257.05:06:36.65#ibcon#about to read 5, iclass 12, count 2 2006.257.05:06:36.65#ibcon#read 5, iclass 12, count 2 2006.257.05:06:36.65#ibcon#about to read 6, iclass 12, count 2 2006.257.05:06:36.65#ibcon#read 6, iclass 12, count 2 2006.257.05:06:36.65#ibcon#end of sib2, iclass 12, count 2 2006.257.05:06:36.65#ibcon#*after write, iclass 12, count 2 2006.257.05:06:36.65#ibcon#*before return 0, iclass 12, count 2 2006.257.05:06:36.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:36.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:06:36.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.05:06:36.65#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:36.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:36.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:36.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:36.77#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:06:36.77#ibcon#first serial, iclass 12, count 0 2006.257.05:06:36.77#ibcon#enter sib2, iclass 12, count 0 2006.257.05:06:36.77#ibcon#flushed, iclass 12, count 0 2006.257.05:06:36.77#ibcon#about to write, iclass 12, count 0 2006.257.05:06:36.77#ibcon#wrote, iclass 12, count 0 2006.257.05:06:36.77#ibcon#about to read 3, iclass 12, count 0 2006.257.05:06:36.79#ibcon#read 3, iclass 12, count 0 2006.257.05:06:36.79#ibcon#about to read 4, iclass 12, count 0 2006.257.05:06:36.79#ibcon#read 4, iclass 12, count 0 2006.257.05:06:36.79#ibcon#about to read 5, iclass 12, count 0 2006.257.05:06:36.79#ibcon#read 5, iclass 12, count 0 2006.257.05:06:36.79#ibcon#about to read 6, iclass 12, count 0 2006.257.05:06:36.79#ibcon#read 6, iclass 12, count 0 2006.257.05:06:36.79#ibcon#end of sib2, iclass 12, count 0 2006.257.05:06:36.79#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:06:36.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:06:36.79#ibcon#[27=USB\r\n] 2006.257.05:06:36.79#ibcon#*before write, iclass 12, count 0 2006.257.05:06:36.79#ibcon#enter sib2, iclass 12, count 0 2006.257.05:06:36.79#ibcon#flushed, iclass 12, count 0 2006.257.05:06:36.79#ibcon#about to write, iclass 12, count 0 2006.257.05:06:36.79#ibcon#wrote, iclass 12, count 0 2006.257.05:06:36.79#ibcon#about to read 3, iclass 12, count 0 2006.257.05:06:36.82#ibcon#read 3, iclass 12, count 0 2006.257.05:06:36.82#ibcon#about to read 4, iclass 12, count 0 2006.257.05:06:36.82#ibcon#read 4, iclass 12, count 0 2006.257.05:06:36.82#ibcon#about to read 5, iclass 12, count 0 2006.257.05:06:36.82#ibcon#read 5, iclass 12, count 0 2006.257.05:06:36.82#ibcon#about to read 6, iclass 12, count 0 2006.257.05:06:36.82#ibcon#read 6, iclass 12, count 0 2006.257.05:06:36.82#ibcon#end of sib2, iclass 12, count 0 2006.257.05:06:36.82#ibcon#*after write, iclass 12, count 0 2006.257.05:06:36.82#ibcon#*before return 0, iclass 12, count 0 2006.257.05:06:36.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:36.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:06:36.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:06:36.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:06:36.82$vck44/vblo=8,744.99 2006.257.05:06:36.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.05:06:36.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.05:06:36.82#ibcon#ireg 17 cls_cnt 0 2006.257.05:06:36.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:36.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:36.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:36.82#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:06:36.82#ibcon#first serial, iclass 14, count 0 2006.257.05:06:36.82#ibcon#enter sib2, iclass 14, count 0 2006.257.05:06:36.82#ibcon#flushed, iclass 14, count 0 2006.257.05:06:36.82#ibcon#about to write, iclass 14, count 0 2006.257.05:06:36.82#ibcon#wrote, iclass 14, count 0 2006.257.05:06:36.82#ibcon#about to read 3, iclass 14, count 0 2006.257.05:06:36.84#ibcon#read 3, iclass 14, count 0 2006.257.05:06:36.84#ibcon#about to read 4, iclass 14, count 0 2006.257.05:06:36.84#ibcon#read 4, iclass 14, count 0 2006.257.05:06:36.84#ibcon#about to read 5, iclass 14, count 0 2006.257.05:06:36.84#ibcon#read 5, iclass 14, count 0 2006.257.05:06:36.84#ibcon#about to read 6, iclass 14, count 0 2006.257.05:06:36.84#ibcon#read 6, iclass 14, count 0 2006.257.05:06:36.84#ibcon#end of sib2, iclass 14, count 0 2006.257.05:06:36.84#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:06:36.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:06:36.84#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:06:36.84#ibcon#*before write, iclass 14, count 0 2006.257.05:06:36.84#ibcon#enter sib2, iclass 14, count 0 2006.257.05:06:36.84#ibcon#flushed, iclass 14, count 0 2006.257.05:06:36.84#ibcon#about to write, iclass 14, count 0 2006.257.05:06:36.84#ibcon#wrote, iclass 14, count 0 2006.257.05:06:36.84#ibcon#about to read 3, iclass 14, count 0 2006.257.05:06:36.88#ibcon#read 3, iclass 14, count 0 2006.257.05:06:36.88#ibcon#about to read 4, iclass 14, count 0 2006.257.05:06:36.88#ibcon#read 4, iclass 14, count 0 2006.257.05:06:36.88#ibcon#about to read 5, iclass 14, count 0 2006.257.05:06:36.88#ibcon#read 5, iclass 14, count 0 2006.257.05:06:36.88#ibcon#about to read 6, iclass 14, count 0 2006.257.05:06:36.88#ibcon#read 6, iclass 14, count 0 2006.257.05:06:36.88#ibcon#end of sib2, iclass 14, count 0 2006.257.05:06:36.88#ibcon#*after write, iclass 14, count 0 2006.257.05:06:36.88#ibcon#*before return 0, iclass 14, count 0 2006.257.05:06:36.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:36.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:06:36.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:06:36.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:06:36.88$vck44/vb=8,4 2006.257.05:06:36.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.05:06:36.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.05:06:36.88#ibcon#ireg 11 cls_cnt 2 2006.257.05:06:36.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:36.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:36.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:36.94#ibcon#enter wrdev, iclass 16, count 2 2006.257.05:06:36.94#ibcon#first serial, iclass 16, count 2 2006.257.05:06:36.94#ibcon#enter sib2, iclass 16, count 2 2006.257.05:06:36.94#ibcon#flushed, iclass 16, count 2 2006.257.05:06:36.94#ibcon#about to write, iclass 16, count 2 2006.257.05:06:36.94#ibcon#wrote, iclass 16, count 2 2006.257.05:06:36.94#ibcon#about to read 3, iclass 16, count 2 2006.257.05:06:36.96#ibcon#read 3, iclass 16, count 2 2006.257.05:06:36.96#ibcon#about to read 4, iclass 16, count 2 2006.257.05:06:36.96#ibcon#read 4, iclass 16, count 2 2006.257.05:06:36.96#ibcon#about to read 5, iclass 16, count 2 2006.257.05:06:36.96#ibcon#read 5, iclass 16, count 2 2006.257.05:06:36.96#ibcon#about to read 6, iclass 16, count 2 2006.257.05:06:36.96#ibcon#read 6, iclass 16, count 2 2006.257.05:06:36.96#ibcon#end of sib2, iclass 16, count 2 2006.257.05:06:36.96#ibcon#*mode == 0, iclass 16, count 2 2006.257.05:06:36.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.05:06:36.96#ibcon#[27=AT08-04\r\n] 2006.257.05:06:36.96#ibcon#*before write, iclass 16, count 2 2006.257.05:06:36.96#ibcon#enter sib2, iclass 16, count 2 2006.257.05:06:36.96#ibcon#flushed, iclass 16, count 2 2006.257.05:06:36.96#ibcon#about to write, iclass 16, count 2 2006.257.05:06:36.96#ibcon#wrote, iclass 16, count 2 2006.257.05:06:36.96#ibcon#about to read 3, iclass 16, count 2 2006.257.05:06:36.99#ibcon#read 3, iclass 16, count 2 2006.257.05:06:36.99#ibcon#about to read 4, iclass 16, count 2 2006.257.05:06:36.99#ibcon#read 4, iclass 16, count 2 2006.257.05:06:36.99#ibcon#about to read 5, iclass 16, count 2 2006.257.05:06:36.99#ibcon#read 5, iclass 16, count 2 2006.257.05:06:36.99#ibcon#about to read 6, iclass 16, count 2 2006.257.05:06:36.99#ibcon#read 6, iclass 16, count 2 2006.257.05:06:36.99#ibcon#end of sib2, iclass 16, count 2 2006.257.05:06:36.99#ibcon#*after write, iclass 16, count 2 2006.257.05:06:36.99#ibcon#*before return 0, iclass 16, count 2 2006.257.05:06:36.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:36.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:06:36.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.05:06:36.99#ibcon#ireg 7 cls_cnt 0 2006.257.05:06:36.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:37.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:37.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:37.11#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:06:37.11#ibcon#first serial, iclass 16, count 0 2006.257.05:06:37.11#ibcon#enter sib2, iclass 16, count 0 2006.257.05:06:37.11#ibcon#flushed, iclass 16, count 0 2006.257.05:06:37.11#ibcon#about to write, iclass 16, count 0 2006.257.05:06:37.11#ibcon#wrote, iclass 16, count 0 2006.257.05:06:37.11#ibcon#about to read 3, iclass 16, count 0 2006.257.05:06:37.13#ibcon#read 3, iclass 16, count 0 2006.257.05:06:37.13#ibcon#about to read 4, iclass 16, count 0 2006.257.05:06:37.13#ibcon#read 4, iclass 16, count 0 2006.257.05:06:37.13#ibcon#about to read 5, iclass 16, count 0 2006.257.05:06:37.13#ibcon#read 5, iclass 16, count 0 2006.257.05:06:37.13#ibcon#about to read 6, iclass 16, count 0 2006.257.05:06:37.13#ibcon#read 6, iclass 16, count 0 2006.257.05:06:37.13#ibcon#end of sib2, iclass 16, count 0 2006.257.05:06:37.13#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:06:37.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:06:37.13#ibcon#[27=USB\r\n] 2006.257.05:06:37.13#ibcon#*before write, iclass 16, count 0 2006.257.05:06:37.13#ibcon#enter sib2, iclass 16, count 0 2006.257.05:06:37.13#ibcon#flushed, iclass 16, count 0 2006.257.05:06:37.13#ibcon#about to write, iclass 16, count 0 2006.257.05:06:37.13#ibcon#wrote, iclass 16, count 0 2006.257.05:06:37.13#ibcon#about to read 3, iclass 16, count 0 2006.257.05:06:37.16#ibcon#read 3, iclass 16, count 0 2006.257.05:06:37.16#ibcon#about to read 4, iclass 16, count 0 2006.257.05:06:37.16#ibcon#read 4, iclass 16, count 0 2006.257.05:06:37.16#ibcon#about to read 5, iclass 16, count 0 2006.257.05:06:37.16#ibcon#read 5, iclass 16, count 0 2006.257.05:06:37.16#ibcon#about to read 6, iclass 16, count 0 2006.257.05:06:37.16#ibcon#read 6, iclass 16, count 0 2006.257.05:06:37.16#ibcon#end of sib2, iclass 16, count 0 2006.257.05:06:37.16#ibcon#*after write, iclass 16, count 0 2006.257.05:06:37.16#ibcon#*before return 0, iclass 16, count 0 2006.257.05:06:37.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:37.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:06:37.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:06:37.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:06:37.16$vck44/vabw=wide 2006.257.05:06:37.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.05:06:37.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.05:06:37.16#ibcon#ireg 8 cls_cnt 0 2006.257.05:06:37.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:37.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:37.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:37.16#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:06:37.16#ibcon#first serial, iclass 18, count 0 2006.257.05:06:37.16#ibcon#enter sib2, iclass 18, count 0 2006.257.05:06:37.16#ibcon#flushed, iclass 18, count 0 2006.257.05:06:37.16#ibcon#about to write, iclass 18, count 0 2006.257.05:06:37.16#ibcon#wrote, iclass 18, count 0 2006.257.05:06:37.16#ibcon#about to read 3, iclass 18, count 0 2006.257.05:06:37.18#ibcon#read 3, iclass 18, count 0 2006.257.05:06:37.18#ibcon#about to read 4, iclass 18, count 0 2006.257.05:06:37.18#ibcon#read 4, iclass 18, count 0 2006.257.05:06:37.18#ibcon#about to read 5, iclass 18, count 0 2006.257.05:06:37.18#ibcon#read 5, iclass 18, count 0 2006.257.05:06:37.18#ibcon#about to read 6, iclass 18, count 0 2006.257.05:06:37.18#ibcon#read 6, iclass 18, count 0 2006.257.05:06:37.18#ibcon#end of sib2, iclass 18, count 0 2006.257.05:06:37.18#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:06:37.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:06:37.18#ibcon#[25=BW32\r\n] 2006.257.05:06:37.18#ibcon#*before write, iclass 18, count 0 2006.257.05:06:37.18#ibcon#enter sib2, iclass 18, count 0 2006.257.05:06:37.18#ibcon#flushed, iclass 18, count 0 2006.257.05:06:37.18#ibcon#about to write, iclass 18, count 0 2006.257.05:06:37.18#ibcon#wrote, iclass 18, count 0 2006.257.05:06:37.18#ibcon#about to read 3, iclass 18, count 0 2006.257.05:06:37.21#ibcon#read 3, iclass 18, count 0 2006.257.05:06:37.21#ibcon#about to read 4, iclass 18, count 0 2006.257.05:06:37.21#ibcon#read 4, iclass 18, count 0 2006.257.05:06:37.21#ibcon#about to read 5, iclass 18, count 0 2006.257.05:06:37.21#ibcon#read 5, iclass 18, count 0 2006.257.05:06:37.21#ibcon#about to read 6, iclass 18, count 0 2006.257.05:06:37.21#ibcon#read 6, iclass 18, count 0 2006.257.05:06:37.21#ibcon#end of sib2, iclass 18, count 0 2006.257.05:06:37.21#ibcon#*after write, iclass 18, count 0 2006.257.05:06:37.21#ibcon#*before return 0, iclass 18, count 0 2006.257.05:06:37.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:37.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:06:37.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:06:37.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:06:37.21$vck44/vbbw=wide 2006.257.05:06:37.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.05:06:37.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.05:06:37.21#ibcon#ireg 8 cls_cnt 0 2006.257.05:06:37.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:06:37.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:06:37.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:06:37.28#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:06:37.28#ibcon#first serial, iclass 20, count 0 2006.257.05:06:37.28#ibcon#enter sib2, iclass 20, count 0 2006.257.05:06:37.28#ibcon#flushed, iclass 20, count 0 2006.257.05:06:37.28#ibcon#about to write, iclass 20, count 0 2006.257.05:06:37.28#ibcon#wrote, iclass 20, count 0 2006.257.05:06:37.28#ibcon#about to read 3, iclass 20, count 0 2006.257.05:06:37.30#ibcon#read 3, iclass 20, count 0 2006.257.05:06:37.30#ibcon#about to read 4, iclass 20, count 0 2006.257.05:06:37.30#ibcon#read 4, iclass 20, count 0 2006.257.05:06:37.30#ibcon#about to read 5, iclass 20, count 0 2006.257.05:06:37.30#ibcon#read 5, iclass 20, count 0 2006.257.05:06:37.30#ibcon#about to read 6, iclass 20, count 0 2006.257.05:06:37.30#ibcon#read 6, iclass 20, count 0 2006.257.05:06:37.30#ibcon#end of sib2, iclass 20, count 0 2006.257.05:06:37.30#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:06:37.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:06:37.30#ibcon#[27=BW32\r\n] 2006.257.05:06:37.30#ibcon#*before write, iclass 20, count 0 2006.257.05:06:37.30#ibcon#enter sib2, iclass 20, count 0 2006.257.05:06:37.30#ibcon#flushed, iclass 20, count 0 2006.257.05:06:37.30#ibcon#about to write, iclass 20, count 0 2006.257.05:06:37.30#ibcon#wrote, iclass 20, count 0 2006.257.05:06:37.30#ibcon#about to read 3, iclass 20, count 0 2006.257.05:06:37.33#ibcon#read 3, iclass 20, count 0 2006.257.05:06:37.33#ibcon#about to read 4, iclass 20, count 0 2006.257.05:06:37.33#ibcon#read 4, iclass 20, count 0 2006.257.05:06:37.33#ibcon#about to read 5, iclass 20, count 0 2006.257.05:06:37.33#ibcon#read 5, iclass 20, count 0 2006.257.05:06:37.33#ibcon#about to read 6, iclass 20, count 0 2006.257.05:06:37.33#ibcon#read 6, iclass 20, count 0 2006.257.05:06:37.33#ibcon#end of sib2, iclass 20, count 0 2006.257.05:06:37.33#ibcon#*after write, iclass 20, count 0 2006.257.05:06:37.33#ibcon#*before return 0, iclass 20, count 0 2006.257.05:06:37.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:06:37.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:06:37.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:06:37.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:06:37.33$setupk4/ifdk4 2006.257.05:06:37.33$ifdk4/lo= 2006.257.05:06:37.33$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:06:37.33$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:06:37.33$ifdk4/patch= 2006.257.05:06:37.33$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:06:37.33$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:06:37.33$setupk4/!*+20s 2006.257.05:06:44.76#abcon#<5=/15 1.6 3.8 19.67 931012.0\r\n> 2006.257.05:06:44.78#abcon#{5=INTERFACE CLEAR} 2006.257.05:06:44.84#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:06:49.14#trakl#Source acquired 2006.257.05:06:51.14#flagr#flagr/antenna,acquired 2006.257.05:06:51.84$setupk4/"tpicd 2006.257.05:06:51.84$setupk4/echo=off 2006.257.05:06:51.84$setupk4/xlog=off 2006.257.05:06:51.84:!2006.257.05:07:17 2006.257.05:07:17.00:preob 2006.257.05:07:17.14/onsource/TRACKING 2006.257.05:07:17.14:!2006.257.05:07:27 2006.257.05:07:27.00:"tape 2006.257.05:07:27.00:"st=record 2006.257.05:07:27.00:data_valid=on 2006.257.05:07:27.00:midob 2006.257.05:07:27.14/onsource/TRACKING 2006.257.05:07:27.14/wx/19.68,1012.0,93 2006.257.05:07:27.23/cable/+6.4821E-03 2006.257.05:07:28.32/va/01,08,usb,yes,31,33 2006.257.05:07:28.32/va/02,07,usb,yes,34,34 2006.257.05:07:28.32/va/03,08,usb,yes,30,32 2006.257.05:07:28.32/va/04,07,usb,yes,35,36 2006.257.05:07:28.32/va/05,04,usb,yes,31,32 2006.257.05:07:28.32/va/06,04,usb,yes,35,34 2006.257.05:07:28.32/va/07,04,usb,yes,35,36 2006.257.05:07:28.32/va/08,04,usb,yes,30,36 2006.257.05:07:28.55/valo/01,524.99,yes,locked 2006.257.05:07:28.55/valo/02,534.99,yes,locked 2006.257.05:07:28.55/valo/03,564.99,yes,locked 2006.257.05:07:28.55/valo/04,624.99,yes,locked 2006.257.05:07:28.55/valo/05,734.99,yes,locked 2006.257.05:07:28.55/valo/06,814.99,yes,locked 2006.257.05:07:28.55/valo/07,864.99,yes,locked 2006.257.05:07:28.55/valo/08,884.99,yes,locked 2006.257.05:07:29.64/vb/01,04,usb,yes,30,28 2006.257.05:07:29.64/vb/02,05,usb,yes,29,29 2006.257.05:07:29.64/vb/03,04,usb,yes,30,33 2006.257.05:07:29.64/vb/04,05,usb,yes,30,29 2006.257.05:07:29.64/vb/05,04,usb,yes,26,29 2006.257.05:07:29.64/vb/06,04,usb,yes,31,27 2006.257.05:07:29.64/vb/07,04,usb,yes,31,31 2006.257.05:07:29.64/vb/08,04,usb,yes,28,32 2006.257.05:07:29.88/vblo/01,629.99,yes,locked 2006.257.05:07:29.88/vblo/02,634.99,yes,locked 2006.257.05:07:29.88/vblo/03,649.99,yes,locked 2006.257.05:07:29.88/vblo/04,679.99,yes,locked 2006.257.05:07:29.88/vblo/05,709.99,yes,locked 2006.257.05:07:29.88/vblo/06,719.99,yes,locked 2006.257.05:07:29.88/vblo/07,734.99,yes,locked 2006.257.05:07:29.88/vblo/08,744.99,yes,locked 2006.257.05:07:30.03/vabw/8 2006.257.05:07:30.18/vbbw/8 2006.257.05:07:30.27/xfe/off,on,16.5 2006.257.05:07:30.65/ifatt/23,28,28,28 2006.257.05:07:31.07/fmout-gps/S +4.55E-07 2006.257.05:07:31.11:!2006.257.05:10:47 2006.257.05:10:47.00:data_valid=off 2006.257.05:10:47.00:"et 2006.257.05:10:47.00:!+3s 2006.257.05:10:50.03:"tape 2006.257.05:10:50.03:postob 2006.257.05:10:50.16/cable/+6.4819E-03 2006.257.05:10:50.16/wx/19.72,1012.0,92 2006.257.05:10:50.22/fmout-gps/S +4.53E-07 2006.257.05:10:50.22:scan_name=257-0514,jd0609,350 2006.257.05:10:50.22:source=oj287,085448.87,200630.6,2000.0,ccw 2006.257.05:10:51.14#flagr#flagr/antenna,new-source 2006.257.05:10:51.14:checkk5 2006.257.05:10:51.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:10:52.10/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:10:52.52/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:10:52.93/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:10:53.32/chk_obsdata//k5ts1/T2570507??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.05:10:53.71/chk_obsdata//k5ts2/T2570507??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.05:10:54.11/chk_obsdata//k5ts3/T2570507??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.05:10:54.53/chk_obsdata//k5ts4/T2570507??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.05:10:55.29/k5log//k5ts1_log_newline 2006.257.05:10:55.99/k5log//k5ts2_log_newline 2006.257.05:10:56.74/k5log//k5ts3_log_newline 2006.257.05:10:57.50/k5log//k5ts4_log_newline 2006.257.05:10:57.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:10:57.52:setupk4=1 2006.257.05:10:57.52$setupk4/echo=on 2006.257.05:10:57.52$setupk4/pcalon 2006.257.05:10:57.52$pcalon/"no phase cal control is implemented here 2006.257.05:10:57.52$setupk4/"tpicd=stop 2006.257.05:10:57.52$setupk4/"rec=synch_on 2006.257.05:10:57.52$setupk4/"rec_mode=128 2006.257.05:10:57.52$setupk4/!* 2006.257.05:10:57.52$setupk4/recpk4 2006.257.05:10:57.52$recpk4/recpatch= 2006.257.05:10:57.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:10:57.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:10:57.53$setupk4/vck44 2006.257.05:10:57.53$vck44/valo=1,524.99 2006.257.05:10:57.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.05:10:57.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.05:10:57.53#ibcon#ireg 17 cls_cnt 0 2006.257.05:10:57.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:10:57.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:10:57.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:10:57.53#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:10:57.53#ibcon#first serial, iclass 12, count 0 2006.257.05:10:57.53#ibcon#enter sib2, iclass 12, count 0 2006.257.05:10:57.53#ibcon#flushed, iclass 12, count 0 2006.257.05:10:57.53#ibcon#about to write, iclass 12, count 0 2006.257.05:10:57.53#ibcon#wrote, iclass 12, count 0 2006.257.05:10:57.53#ibcon#about to read 3, iclass 12, count 0 2006.257.05:10:57.55#ibcon#read 3, iclass 12, count 0 2006.257.05:10:57.55#ibcon#about to read 4, iclass 12, count 0 2006.257.05:10:57.55#ibcon#read 4, iclass 12, count 0 2006.257.05:10:57.55#ibcon#about to read 5, iclass 12, count 0 2006.257.05:10:57.55#ibcon#read 5, iclass 12, count 0 2006.257.05:10:57.55#ibcon#about to read 6, iclass 12, count 0 2006.257.05:10:57.55#ibcon#read 6, iclass 12, count 0 2006.257.05:10:57.55#ibcon#end of sib2, iclass 12, count 0 2006.257.05:10:57.55#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:10:57.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:10:57.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:10:57.55#ibcon#*before write, iclass 12, count 0 2006.257.05:10:57.55#ibcon#enter sib2, iclass 12, count 0 2006.257.05:10:57.55#ibcon#flushed, iclass 12, count 0 2006.257.05:10:57.55#ibcon#about to write, iclass 12, count 0 2006.257.05:10:57.55#ibcon#wrote, iclass 12, count 0 2006.257.05:10:57.55#ibcon#about to read 3, iclass 12, count 0 2006.257.05:10:57.60#ibcon#read 3, iclass 12, count 0 2006.257.05:10:57.60#ibcon#about to read 4, iclass 12, count 0 2006.257.05:10:57.60#ibcon#read 4, iclass 12, count 0 2006.257.05:10:57.60#ibcon#about to read 5, iclass 12, count 0 2006.257.05:10:57.60#ibcon#read 5, iclass 12, count 0 2006.257.05:10:57.60#ibcon#about to read 6, iclass 12, count 0 2006.257.05:10:57.60#ibcon#read 6, iclass 12, count 0 2006.257.05:10:57.60#ibcon#end of sib2, iclass 12, count 0 2006.257.05:10:57.60#ibcon#*after write, iclass 12, count 0 2006.257.05:10:57.60#ibcon#*before return 0, iclass 12, count 0 2006.257.05:10:57.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:10:57.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:10:57.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:10:57.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:10:57.60$vck44/va=1,8 2006.257.05:10:57.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.05:10:57.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.05:10:57.60#ibcon#ireg 11 cls_cnt 2 2006.257.05:10:57.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:10:57.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:10:57.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:10:57.60#ibcon#enter wrdev, iclass 14, count 2 2006.257.05:10:57.60#ibcon#first serial, iclass 14, count 2 2006.257.05:10:57.60#ibcon#enter sib2, iclass 14, count 2 2006.257.05:10:57.60#ibcon#flushed, iclass 14, count 2 2006.257.05:10:57.60#ibcon#about to write, iclass 14, count 2 2006.257.05:10:57.60#ibcon#wrote, iclass 14, count 2 2006.257.05:10:57.60#ibcon#about to read 3, iclass 14, count 2 2006.257.05:10:57.62#ibcon#read 3, iclass 14, count 2 2006.257.05:10:57.62#ibcon#about to read 4, iclass 14, count 2 2006.257.05:10:57.62#ibcon#read 4, iclass 14, count 2 2006.257.05:10:57.62#ibcon#about to read 5, iclass 14, count 2 2006.257.05:10:57.62#ibcon#read 5, iclass 14, count 2 2006.257.05:10:57.62#ibcon#about to read 6, iclass 14, count 2 2006.257.05:10:57.62#ibcon#read 6, iclass 14, count 2 2006.257.05:10:57.62#ibcon#end of sib2, iclass 14, count 2 2006.257.05:10:57.62#ibcon#*mode == 0, iclass 14, count 2 2006.257.05:10:57.62#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.05:10:57.62#ibcon#[25=AT01-08\r\n] 2006.257.05:10:57.62#ibcon#*before write, iclass 14, count 2 2006.257.05:10:57.62#ibcon#enter sib2, iclass 14, count 2 2006.257.05:10:57.62#ibcon#flushed, iclass 14, count 2 2006.257.05:10:57.62#ibcon#about to write, iclass 14, count 2 2006.257.05:10:57.62#ibcon#wrote, iclass 14, count 2 2006.257.05:10:57.62#ibcon#about to read 3, iclass 14, count 2 2006.257.05:10:57.65#ibcon#read 3, iclass 14, count 2 2006.257.05:10:57.65#ibcon#about to read 4, iclass 14, count 2 2006.257.05:10:57.65#ibcon#read 4, iclass 14, count 2 2006.257.05:10:57.65#ibcon#about to read 5, iclass 14, count 2 2006.257.05:10:57.65#ibcon#read 5, iclass 14, count 2 2006.257.05:10:57.65#ibcon#about to read 6, iclass 14, count 2 2006.257.05:10:57.65#ibcon#read 6, iclass 14, count 2 2006.257.05:10:57.65#ibcon#end of sib2, iclass 14, count 2 2006.257.05:10:57.65#ibcon#*after write, iclass 14, count 2 2006.257.05:10:57.65#ibcon#*before return 0, iclass 14, count 2 2006.257.05:10:57.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:10:57.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:10:57.65#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.05:10:57.65#ibcon#ireg 7 cls_cnt 0 2006.257.05:10:57.65#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:10:57.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:10:57.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:10:57.77#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:10:57.77#ibcon#first serial, iclass 14, count 0 2006.257.05:10:57.77#ibcon#enter sib2, iclass 14, count 0 2006.257.05:10:57.77#ibcon#flushed, iclass 14, count 0 2006.257.05:10:57.77#ibcon#about to write, iclass 14, count 0 2006.257.05:10:57.77#ibcon#wrote, iclass 14, count 0 2006.257.05:10:57.77#ibcon#about to read 3, iclass 14, count 0 2006.257.05:10:57.79#ibcon#read 3, iclass 14, count 0 2006.257.05:10:57.79#ibcon#about to read 4, iclass 14, count 0 2006.257.05:10:57.79#ibcon#read 4, iclass 14, count 0 2006.257.05:10:57.79#ibcon#about to read 5, iclass 14, count 0 2006.257.05:10:57.79#ibcon#read 5, iclass 14, count 0 2006.257.05:10:57.79#ibcon#about to read 6, iclass 14, count 0 2006.257.05:10:57.79#ibcon#read 6, iclass 14, count 0 2006.257.05:10:57.79#ibcon#end of sib2, iclass 14, count 0 2006.257.05:10:57.79#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:10:57.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:10:57.79#ibcon#[25=USB\r\n] 2006.257.05:10:57.79#ibcon#*before write, iclass 14, count 0 2006.257.05:10:57.79#ibcon#enter sib2, iclass 14, count 0 2006.257.05:10:57.79#ibcon#flushed, iclass 14, count 0 2006.257.05:10:57.79#ibcon#about to write, iclass 14, count 0 2006.257.05:10:57.79#ibcon#wrote, iclass 14, count 0 2006.257.05:10:57.79#ibcon#about to read 3, iclass 14, count 0 2006.257.05:10:57.82#ibcon#read 3, iclass 14, count 0 2006.257.05:10:57.82#ibcon#about to read 4, iclass 14, count 0 2006.257.05:10:57.82#ibcon#read 4, iclass 14, count 0 2006.257.05:10:57.82#ibcon#about to read 5, iclass 14, count 0 2006.257.05:10:57.82#ibcon#read 5, iclass 14, count 0 2006.257.05:10:57.82#ibcon#about to read 6, iclass 14, count 0 2006.257.05:10:57.82#ibcon#read 6, iclass 14, count 0 2006.257.05:10:57.82#ibcon#end of sib2, iclass 14, count 0 2006.257.05:10:57.82#ibcon#*after write, iclass 14, count 0 2006.257.05:10:57.82#ibcon#*before return 0, iclass 14, count 0 2006.257.05:10:57.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:10:57.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:10:57.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:10:57.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:10:57.82$vck44/valo=2,534.99 2006.257.05:10:57.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.05:10:57.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.05:10:57.82#ibcon#ireg 17 cls_cnt 0 2006.257.05:10:57.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:10:57.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:10:57.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:10:57.82#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:10:57.82#ibcon#first serial, iclass 16, count 0 2006.257.05:10:57.82#ibcon#enter sib2, iclass 16, count 0 2006.257.05:10:57.82#ibcon#flushed, iclass 16, count 0 2006.257.05:10:57.82#ibcon#about to write, iclass 16, count 0 2006.257.05:10:57.82#ibcon#wrote, iclass 16, count 0 2006.257.05:10:57.82#ibcon#about to read 3, iclass 16, count 0 2006.257.05:10:57.84#ibcon#read 3, iclass 16, count 0 2006.257.05:10:57.84#ibcon#about to read 4, iclass 16, count 0 2006.257.05:10:57.84#ibcon#read 4, iclass 16, count 0 2006.257.05:10:57.84#ibcon#about to read 5, iclass 16, count 0 2006.257.05:10:57.84#ibcon#read 5, iclass 16, count 0 2006.257.05:10:57.84#ibcon#about to read 6, iclass 16, count 0 2006.257.05:10:57.84#ibcon#read 6, iclass 16, count 0 2006.257.05:10:57.84#ibcon#end of sib2, iclass 16, count 0 2006.257.05:10:57.84#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:10:57.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:10:57.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:10:57.84#ibcon#*before write, iclass 16, count 0 2006.257.05:10:57.84#ibcon#enter sib2, iclass 16, count 0 2006.257.05:10:57.84#ibcon#flushed, iclass 16, count 0 2006.257.05:10:57.84#ibcon#about to write, iclass 16, count 0 2006.257.05:10:57.84#ibcon#wrote, iclass 16, count 0 2006.257.05:10:57.84#ibcon#about to read 3, iclass 16, count 0 2006.257.05:10:57.88#ibcon#read 3, iclass 16, count 0 2006.257.05:10:57.88#ibcon#about to read 4, iclass 16, count 0 2006.257.05:10:57.88#ibcon#read 4, iclass 16, count 0 2006.257.05:10:57.88#ibcon#about to read 5, iclass 16, count 0 2006.257.05:10:57.88#ibcon#read 5, iclass 16, count 0 2006.257.05:10:57.88#ibcon#about to read 6, iclass 16, count 0 2006.257.05:10:57.88#ibcon#read 6, iclass 16, count 0 2006.257.05:10:57.88#ibcon#end of sib2, iclass 16, count 0 2006.257.05:10:57.88#ibcon#*after write, iclass 16, count 0 2006.257.05:10:57.88#ibcon#*before return 0, iclass 16, count 0 2006.257.05:10:57.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:10:57.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:10:57.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:10:57.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:10:57.88$vck44/va=2,7 2006.257.05:10:57.88#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.05:10:57.88#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.05:10:57.88#ibcon#ireg 11 cls_cnt 2 2006.257.05:10:57.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:10:57.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:10:57.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:10:57.94#ibcon#enter wrdev, iclass 18, count 2 2006.257.05:10:57.94#ibcon#first serial, iclass 18, count 2 2006.257.05:10:57.94#ibcon#enter sib2, iclass 18, count 2 2006.257.05:10:57.94#ibcon#flushed, iclass 18, count 2 2006.257.05:10:57.94#ibcon#about to write, iclass 18, count 2 2006.257.05:10:57.94#ibcon#wrote, iclass 18, count 2 2006.257.05:10:57.94#ibcon#about to read 3, iclass 18, count 2 2006.257.05:10:57.96#ibcon#read 3, iclass 18, count 2 2006.257.05:10:57.96#ibcon#about to read 4, iclass 18, count 2 2006.257.05:10:57.96#ibcon#read 4, iclass 18, count 2 2006.257.05:10:57.96#ibcon#about to read 5, iclass 18, count 2 2006.257.05:10:57.96#ibcon#read 5, iclass 18, count 2 2006.257.05:10:57.96#ibcon#about to read 6, iclass 18, count 2 2006.257.05:10:57.96#ibcon#read 6, iclass 18, count 2 2006.257.05:10:57.96#ibcon#end of sib2, iclass 18, count 2 2006.257.05:10:57.96#ibcon#*mode == 0, iclass 18, count 2 2006.257.05:10:57.96#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.05:10:57.96#ibcon#[25=AT02-07\r\n] 2006.257.05:10:57.96#ibcon#*before write, iclass 18, count 2 2006.257.05:10:57.96#ibcon#enter sib2, iclass 18, count 2 2006.257.05:10:57.96#ibcon#flushed, iclass 18, count 2 2006.257.05:10:57.96#ibcon#about to write, iclass 18, count 2 2006.257.05:10:57.96#ibcon#wrote, iclass 18, count 2 2006.257.05:10:57.96#ibcon#about to read 3, iclass 18, count 2 2006.257.05:10:57.99#ibcon#read 3, iclass 18, count 2 2006.257.05:10:57.99#ibcon#about to read 4, iclass 18, count 2 2006.257.05:10:57.99#ibcon#read 4, iclass 18, count 2 2006.257.05:10:57.99#ibcon#about to read 5, iclass 18, count 2 2006.257.05:10:57.99#ibcon#read 5, iclass 18, count 2 2006.257.05:10:57.99#ibcon#about to read 6, iclass 18, count 2 2006.257.05:10:57.99#ibcon#read 6, iclass 18, count 2 2006.257.05:10:57.99#ibcon#end of sib2, iclass 18, count 2 2006.257.05:10:57.99#ibcon#*after write, iclass 18, count 2 2006.257.05:10:57.99#ibcon#*before return 0, iclass 18, count 2 2006.257.05:10:57.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:10:57.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:10:57.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.05:10:57.99#ibcon#ireg 7 cls_cnt 0 2006.257.05:10:57.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:10:58.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:10:58.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:10:58.11#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:10:58.11#ibcon#first serial, iclass 18, count 0 2006.257.05:10:58.11#ibcon#enter sib2, iclass 18, count 0 2006.257.05:10:58.11#ibcon#flushed, iclass 18, count 0 2006.257.05:10:58.11#ibcon#about to write, iclass 18, count 0 2006.257.05:10:58.11#ibcon#wrote, iclass 18, count 0 2006.257.05:10:58.11#ibcon#about to read 3, iclass 18, count 0 2006.257.05:10:58.13#ibcon#read 3, iclass 18, count 0 2006.257.05:10:58.13#ibcon#about to read 4, iclass 18, count 0 2006.257.05:10:58.13#ibcon#read 4, iclass 18, count 0 2006.257.05:10:58.13#ibcon#about to read 5, iclass 18, count 0 2006.257.05:10:58.13#ibcon#read 5, iclass 18, count 0 2006.257.05:10:58.13#ibcon#about to read 6, iclass 18, count 0 2006.257.05:10:58.13#ibcon#read 6, iclass 18, count 0 2006.257.05:10:58.13#ibcon#end of sib2, iclass 18, count 0 2006.257.05:10:58.13#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:10:58.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:10:58.13#ibcon#[25=USB\r\n] 2006.257.05:10:58.13#ibcon#*before write, iclass 18, count 0 2006.257.05:10:58.13#ibcon#enter sib2, iclass 18, count 0 2006.257.05:10:58.13#ibcon#flushed, iclass 18, count 0 2006.257.05:10:58.13#ibcon#about to write, iclass 18, count 0 2006.257.05:10:58.13#ibcon#wrote, iclass 18, count 0 2006.257.05:10:58.13#ibcon#about to read 3, iclass 18, count 0 2006.257.05:10:58.16#ibcon#read 3, iclass 18, count 0 2006.257.05:10:58.16#ibcon#about to read 4, iclass 18, count 0 2006.257.05:10:58.16#ibcon#read 4, iclass 18, count 0 2006.257.05:10:58.16#ibcon#about to read 5, iclass 18, count 0 2006.257.05:10:58.16#ibcon#read 5, iclass 18, count 0 2006.257.05:10:58.16#ibcon#about to read 6, iclass 18, count 0 2006.257.05:10:58.16#ibcon#read 6, iclass 18, count 0 2006.257.05:10:58.16#ibcon#end of sib2, iclass 18, count 0 2006.257.05:10:58.16#ibcon#*after write, iclass 18, count 0 2006.257.05:10:58.16#ibcon#*before return 0, iclass 18, count 0 2006.257.05:10:58.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:10:58.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:10:58.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:10:58.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:10:58.16$vck44/valo=3,564.99 2006.257.05:10:58.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.05:10:58.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.05:10:58.16#ibcon#ireg 17 cls_cnt 0 2006.257.05:10:58.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:10:58.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:10:58.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:10:58.16#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:10:58.16#ibcon#first serial, iclass 20, count 0 2006.257.05:10:58.16#ibcon#enter sib2, iclass 20, count 0 2006.257.05:10:58.16#ibcon#flushed, iclass 20, count 0 2006.257.05:10:58.16#ibcon#about to write, iclass 20, count 0 2006.257.05:10:58.16#ibcon#wrote, iclass 20, count 0 2006.257.05:10:58.16#ibcon#about to read 3, iclass 20, count 0 2006.257.05:10:58.18#ibcon#read 3, iclass 20, count 0 2006.257.05:10:58.18#ibcon#about to read 4, iclass 20, count 0 2006.257.05:10:58.18#ibcon#read 4, iclass 20, count 0 2006.257.05:10:58.18#ibcon#about to read 5, iclass 20, count 0 2006.257.05:10:58.18#ibcon#read 5, iclass 20, count 0 2006.257.05:10:58.18#ibcon#about to read 6, iclass 20, count 0 2006.257.05:10:58.18#ibcon#read 6, iclass 20, count 0 2006.257.05:10:58.18#ibcon#end of sib2, iclass 20, count 0 2006.257.05:10:58.18#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:10:58.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:10:58.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:10:58.18#ibcon#*before write, iclass 20, count 0 2006.257.05:10:58.18#ibcon#enter sib2, iclass 20, count 0 2006.257.05:10:58.18#ibcon#flushed, iclass 20, count 0 2006.257.05:10:58.18#ibcon#about to write, iclass 20, count 0 2006.257.05:10:58.18#ibcon#wrote, iclass 20, count 0 2006.257.05:10:58.18#ibcon#about to read 3, iclass 20, count 0 2006.257.05:10:58.22#ibcon#read 3, iclass 20, count 0 2006.257.05:10:58.22#ibcon#about to read 4, iclass 20, count 0 2006.257.05:10:58.22#ibcon#read 4, iclass 20, count 0 2006.257.05:10:58.22#ibcon#about to read 5, iclass 20, count 0 2006.257.05:10:58.22#ibcon#read 5, iclass 20, count 0 2006.257.05:10:58.22#ibcon#about to read 6, iclass 20, count 0 2006.257.05:10:58.22#ibcon#read 6, iclass 20, count 0 2006.257.05:10:58.22#ibcon#end of sib2, iclass 20, count 0 2006.257.05:10:58.22#ibcon#*after write, iclass 20, count 0 2006.257.05:10:58.22#ibcon#*before return 0, iclass 20, count 0 2006.257.05:10:58.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:10:58.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:10:58.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:10:58.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:10:58.22$vck44/va=3,8 2006.257.05:10:58.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.05:10:58.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.05:10:58.22#ibcon#ireg 11 cls_cnt 2 2006.257.05:10:58.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:10:58.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:10:58.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:10:58.28#ibcon#enter wrdev, iclass 22, count 2 2006.257.05:10:58.28#ibcon#first serial, iclass 22, count 2 2006.257.05:10:58.28#ibcon#enter sib2, iclass 22, count 2 2006.257.05:10:58.28#ibcon#flushed, iclass 22, count 2 2006.257.05:10:58.28#ibcon#about to write, iclass 22, count 2 2006.257.05:10:58.28#ibcon#wrote, iclass 22, count 2 2006.257.05:10:58.28#ibcon#about to read 3, iclass 22, count 2 2006.257.05:10:58.30#ibcon#read 3, iclass 22, count 2 2006.257.05:10:58.30#ibcon#about to read 4, iclass 22, count 2 2006.257.05:10:58.30#ibcon#read 4, iclass 22, count 2 2006.257.05:10:58.30#ibcon#about to read 5, iclass 22, count 2 2006.257.05:10:58.30#ibcon#read 5, iclass 22, count 2 2006.257.05:10:58.30#ibcon#about to read 6, iclass 22, count 2 2006.257.05:10:58.30#ibcon#read 6, iclass 22, count 2 2006.257.05:10:58.30#ibcon#end of sib2, iclass 22, count 2 2006.257.05:10:58.30#ibcon#*mode == 0, iclass 22, count 2 2006.257.05:10:58.30#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.05:10:58.30#ibcon#[25=AT03-08\r\n] 2006.257.05:10:58.30#ibcon#*before write, iclass 22, count 2 2006.257.05:10:58.30#ibcon#enter sib2, iclass 22, count 2 2006.257.05:10:58.30#ibcon#flushed, iclass 22, count 2 2006.257.05:10:58.30#ibcon#about to write, iclass 22, count 2 2006.257.05:10:58.30#ibcon#wrote, iclass 22, count 2 2006.257.05:10:58.30#ibcon#about to read 3, iclass 22, count 2 2006.257.05:10:58.33#ibcon#read 3, iclass 22, count 2 2006.257.05:10:58.33#ibcon#about to read 4, iclass 22, count 2 2006.257.05:10:58.33#ibcon#read 4, iclass 22, count 2 2006.257.05:10:58.33#ibcon#about to read 5, iclass 22, count 2 2006.257.05:10:58.33#ibcon#read 5, iclass 22, count 2 2006.257.05:10:58.33#ibcon#about to read 6, iclass 22, count 2 2006.257.05:10:58.33#ibcon#read 6, iclass 22, count 2 2006.257.05:10:58.33#ibcon#end of sib2, iclass 22, count 2 2006.257.05:10:58.33#ibcon#*after write, iclass 22, count 2 2006.257.05:10:58.33#ibcon#*before return 0, iclass 22, count 2 2006.257.05:10:58.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:10:58.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:10:58.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.05:10:58.33#ibcon#ireg 7 cls_cnt 0 2006.257.05:10:58.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:10:58.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:10:58.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:10:58.45#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:10:58.45#ibcon#first serial, iclass 22, count 0 2006.257.05:10:58.45#ibcon#enter sib2, iclass 22, count 0 2006.257.05:10:58.45#ibcon#flushed, iclass 22, count 0 2006.257.05:10:58.45#ibcon#about to write, iclass 22, count 0 2006.257.05:10:58.45#ibcon#wrote, iclass 22, count 0 2006.257.05:10:58.45#ibcon#about to read 3, iclass 22, count 0 2006.257.05:10:58.47#ibcon#read 3, iclass 22, count 0 2006.257.05:10:58.47#ibcon#about to read 4, iclass 22, count 0 2006.257.05:10:58.47#ibcon#read 4, iclass 22, count 0 2006.257.05:10:58.47#ibcon#about to read 5, iclass 22, count 0 2006.257.05:10:58.47#ibcon#read 5, iclass 22, count 0 2006.257.05:10:58.47#ibcon#about to read 6, iclass 22, count 0 2006.257.05:10:58.47#ibcon#read 6, iclass 22, count 0 2006.257.05:10:58.47#ibcon#end of sib2, iclass 22, count 0 2006.257.05:10:58.47#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:10:58.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:10:58.47#ibcon#[25=USB\r\n] 2006.257.05:10:58.47#ibcon#*before write, iclass 22, count 0 2006.257.05:10:58.47#ibcon#enter sib2, iclass 22, count 0 2006.257.05:10:58.47#ibcon#flushed, iclass 22, count 0 2006.257.05:10:58.47#ibcon#about to write, iclass 22, count 0 2006.257.05:10:58.47#ibcon#wrote, iclass 22, count 0 2006.257.05:10:58.47#ibcon#about to read 3, iclass 22, count 0 2006.257.05:10:58.50#ibcon#read 3, iclass 22, count 0 2006.257.05:10:58.50#ibcon#about to read 4, iclass 22, count 0 2006.257.05:10:58.50#ibcon#read 4, iclass 22, count 0 2006.257.05:10:58.50#ibcon#about to read 5, iclass 22, count 0 2006.257.05:10:58.50#ibcon#read 5, iclass 22, count 0 2006.257.05:10:58.50#ibcon#about to read 6, iclass 22, count 0 2006.257.05:10:58.50#ibcon#read 6, iclass 22, count 0 2006.257.05:10:58.50#ibcon#end of sib2, iclass 22, count 0 2006.257.05:10:58.50#ibcon#*after write, iclass 22, count 0 2006.257.05:10:58.50#ibcon#*before return 0, iclass 22, count 0 2006.257.05:10:58.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:10:58.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:10:58.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:10:58.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:10:58.50$vck44/valo=4,624.99 2006.257.05:10:58.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.05:10:58.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.05:10:58.50#ibcon#ireg 17 cls_cnt 0 2006.257.05:10:58.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:10:58.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:10:58.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:10:58.50#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:10:58.50#ibcon#first serial, iclass 24, count 0 2006.257.05:10:58.50#ibcon#enter sib2, iclass 24, count 0 2006.257.05:10:58.50#ibcon#flushed, iclass 24, count 0 2006.257.05:10:58.50#ibcon#about to write, iclass 24, count 0 2006.257.05:10:58.50#ibcon#wrote, iclass 24, count 0 2006.257.05:10:58.50#ibcon#about to read 3, iclass 24, count 0 2006.257.05:10:58.52#ibcon#read 3, iclass 24, count 0 2006.257.05:10:58.52#ibcon#about to read 4, iclass 24, count 0 2006.257.05:10:58.52#ibcon#read 4, iclass 24, count 0 2006.257.05:10:58.52#ibcon#about to read 5, iclass 24, count 0 2006.257.05:10:58.52#ibcon#read 5, iclass 24, count 0 2006.257.05:10:58.52#ibcon#about to read 6, iclass 24, count 0 2006.257.05:10:58.52#ibcon#read 6, iclass 24, count 0 2006.257.05:10:58.52#ibcon#end of sib2, iclass 24, count 0 2006.257.05:10:58.52#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:10:58.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:10:58.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:10:58.52#ibcon#*before write, iclass 24, count 0 2006.257.05:10:58.52#ibcon#enter sib2, iclass 24, count 0 2006.257.05:10:58.52#ibcon#flushed, iclass 24, count 0 2006.257.05:10:58.52#ibcon#about to write, iclass 24, count 0 2006.257.05:10:58.52#ibcon#wrote, iclass 24, count 0 2006.257.05:10:58.52#ibcon#about to read 3, iclass 24, count 0 2006.257.05:10:58.56#ibcon#read 3, iclass 24, count 0 2006.257.05:10:58.56#ibcon#about to read 4, iclass 24, count 0 2006.257.05:10:58.56#ibcon#read 4, iclass 24, count 0 2006.257.05:10:58.56#ibcon#about to read 5, iclass 24, count 0 2006.257.05:10:58.56#ibcon#read 5, iclass 24, count 0 2006.257.05:10:58.56#ibcon#about to read 6, iclass 24, count 0 2006.257.05:10:58.56#ibcon#read 6, iclass 24, count 0 2006.257.05:10:58.56#ibcon#end of sib2, iclass 24, count 0 2006.257.05:10:58.56#ibcon#*after write, iclass 24, count 0 2006.257.05:10:58.56#ibcon#*before return 0, iclass 24, count 0 2006.257.05:10:58.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:10:58.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:10:58.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:10:58.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:10:58.56$vck44/va=4,7 2006.257.05:10:58.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.05:10:58.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.05:10:58.56#ibcon#ireg 11 cls_cnt 2 2006.257.05:10:58.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:10:58.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:10:58.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:10:58.62#ibcon#enter wrdev, iclass 26, count 2 2006.257.05:10:58.62#ibcon#first serial, iclass 26, count 2 2006.257.05:10:58.62#ibcon#enter sib2, iclass 26, count 2 2006.257.05:10:58.62#ibcon#flushed, iclass 26, count 2 2006.257.05:10:58.62#ibcon#about to write, iclass 26, count 2 2006.257.05:10:58.62#ibcon#wrote, iclass 26, count 2 2006.257.05:10:58.62#ibcon#about to read 3, iclass 26, count 2 2006.257.05:10:58.64#ibcon#read 3, iclass 26, count 2 2006.257.05:10:58.64#ibcon#about to read 4, iclass 26, count 2 2006.257.05:10:58.64#ibcon#read 4, iclass 26, count 2 2006.257.05:10:58.64#ibcon#about to read 5, iclass 26, count 2 2006.257.05:10:58.64#ibcon#read 5, iclass 26, count 2 2006.257.05:10:58.64#ibcon#about to read 6, iclass 26, count 2 2006.257.05:10:58.64#ibcon#read 6, iclass 26, count 2 2006.257.05:10:58.64#ibcon#end of sib2, iclass 26, count 2 2006.257.05:10:58.64#ibcon#*mode == 0, iclass 26, count 2 2006.257.05:10:58.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.05:10:58.64#ibcon#[25=AT04-07\r\n] 2006.257.05:10:58.64#ibcon#*before write, iclass 26, count 2 2006.257.05:10:58.64#ibcon#enter sib2, iclass 26, count 2 2006.257.05:10:58.64#ibcon#flushed, iclass 26, count 2 2006.257.05:10:58.64#ibcon#about to write, iclass 26, count 2 2006.257.05:10:58.64#ibcon#wrote, iclass 26, count 2 2006.257.05:10:58.64#ibcon#about to read 3, iclass 26, count 2 2006.257.05:10:58.67#ibcon#read 3, iclass 26, count 2 2006.257.05:10:58.67#ibcon#about to read 4, iclass 26, count 2 2006.257.05:10:58.67#ibcon#read 4, iclass 26, count 2 2006.257.05:10:58.67#ibcon#about to read 5, iclass 26, count 2 2006.257.05:10:58.67#ibcon#read 5, iclass 26, count 2 2006.257.05:10:58.67#ibcon#about to read 6, iclass 26, count 2 2006.257.05:10:58.67#ibcon#read 6, iclass 26, count 2 2006.257.05:10:58.67#ibcon#end of sib2, iclass 26, count 2 2006.257.05:10:58.67#ibcon#*after write, iclass 26, count 2 2006.257.05:10:58.67#ibcon#*before return 0, iclass 26, count 2 2006.257.05:10:58.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:10:58.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:10:58.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.05:10:58.67#ibcon#ireg 7 cls_cnt 0 2006.257.05:10:58.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:10:58.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:10:58.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:10:58.79#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:10:58.79#ibcon#first serial, iclass 26, count 0 2006.257.05:10:58.79#ibcon#enter sib2, iclass 26, count 0 2006.257.05:10:58.79#ibcon#flushed, iclass 26, count 0 2006.257.05:10:58.79#ibcon#about to write, iclass 26, count 0 2006.257.05:10:58.79#ibcon#wrote, iclass 26, count 0 2006.257.05:10:58.79#ibcon#about to read 3, iclass 26, count 0 2006.257.05:10:58.81#ibcon#read 3, iclass 26, count 0 2006.257.05:10:58.81#ibcon#about to read 4, iclass 26, count 0 2006.257.05:10:58.81#ibcon#read 4, iclass 26, count 0 2006.257.05:10:58.81#ibcon#about to read 5, iclass 26, count 0 2006.257.05:10:58.81#ibcon#read 5, iclass 26, count 0 2006.257.05:10:58.81#ibcon#about to read 6, iclass 26, count 0 2006.257.05:10:58.81#ibcon#read 6, iclass 26, count 0 2006.257.05:10:58.81#ibcon#end of sib2, iclass 26, count 0 2006.257.05:10:58.81#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:10:58.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:10:58.81#ibcon#[25=USB\r\n] 2006.257.05:10:58.81#ibcon#*before write, iclass 26, count 0 2006.257.05:10:58.81#ibcon#enter sib2, iclass 26, count 0 2006.257.05:10:58.81#ibcon#flushed, iclass 26, count 0 2006.257.05:10:58.81#ibcon#about to write, iclass 26, count 0 2006.257.05:10:58.81#ibcon#wrote, iclass 26, count 0 2006.257.05:10:58.81#ibcon#about to read 3, iclass 26, count 0 2006.257.05:10:58.84#ibcon#read 3, iclass 26, count 0 2006.257.05:10:58.84#ibcon#about to read 4, iclass 26, count 0 2006.257.05:10:58.84#ibcon#read 4, iclass 26, count 0 2006.257.05:10:58.84#ibcon#about to read 5, iclass 26, count 0 2006.257.05:10:58.84#ibcon#read 5, iclass 26, count 0 2006.257.05:10:58.84#ibcon#about to read 6, iclass 26, count 0 2006.257.05:10:58.84#ibcon#read 6, iclass 26, count 0 2006.257.05:10:58.84#ibcon#end of sib2, iclass 26, count 0 2006.257.05:10:58.84#ibcon#*after write, iclass 26, count 0 2006.257.05:10:58.84#ibcon#*before return 0, iclass 26, count 0 2006.257.05:10:58.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:10:58.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:10:58.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:10:58.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:10:58.84$vck44/valo=5,734.99 2006.257.05:10:58.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.05:10:58.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.05:10:58.84#ibcon#ireg 17 cls_cnt 0 2006.257.05:10:58.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:10:58.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:10:58.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:10:58.84#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:10:58.84#ibcon#first serial, iclass 28, count 0 2006.257.05:10:58.84#ibcon#enter sib2, iclass 28, count 0 2006.257.05:10:58.84#ibcon#flushed, iclass 28, count 0 2006.257.05:10:58.84#ibcon#about to write, iclass 28, count 0 2006.257.05:10:58.84#ibcon#wrote, iclass 28, count 0 2006.257.05:10:58.84#ibcon#about to read 3, iclass 28, count 0 2006.257.05:10:58.86#ibcon#read 3, iclass 28, count 0 2006.257.05:10:58.86#ibcon#about to read 4, iclass 28, count 0 2006.257.05:10:58.86#ibcon#read 4, iclass 28, count 0 2006.257.05:10:58.86#ibcon#about to read 5, iclass 28, count 0 2006.257.05:10:58.86#ibcon#read 5, iclass 28, count 0 2006.257.05:10:58.86#ibcon#about to read 6, iclass 28, count 0 2006.257.05:10:58.86#ibcon#read 6, iclass 28, count 0 2006.257.05:10:58.86#ibcon#end of sib2, iclass 28, count 0 2006.257.05:10:58.86#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:10:58.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:10:58.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:10:58.86#ibcon#*before write, iclass 28, count 0 2006.257.05:10:58.86#ibcon#enter sib2, iclass 28, count 0 2006.257.05:10:58.86#ibcon#flushed, iclass 28, count 0 2006.257.05:10:58.86#ibcon#about to write, iclass 28, count 0 2006.257.05:10:58.86#ibcon#wrote, iclass 28, count 0 2006.257.05:10:58.86#ibcon#about to read 3, iclass 28, count 0 2006.257.05:10:58.90#ibcon#read 3, iclass 28, count 0 2006.257.05:10:58.90#ibcon#about to read 4, iclass 28, count 0 2006.257.05:10:58.90#ibcon#read 4, iclass 28, count 0 2006.257.05:10:58.90#ibcon#about to read 5, iclass 28, count 0 2006.257.05:10:58.90#ibcon#read 5, iclass 28, count 0 2006.257.05:10:58.90#ibcon#about to read 6, iclass 28, count 0 2006.257.05:10:58.90#ibcon#read 6, iclass 28, count 0 2006.257.05:10:58.90#ibcon#end of sib2, iclass 28, count 0 2006.257.05:10:58.90#ibcon#*after write, iclass 28, count 0 2006.257.05:10:58.90#ibcon#*before return 0, iclass 28, count 0 2006.257.05:10:58.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:10:58.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:10:58.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:10:58.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:10:58.90$vck44/va=5,4 2006.257.05:10:58.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.05:10:58.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.05:10:58.90#ibcon#ireg 11 cls_cnt 2 2006.257.05:10:58.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:10:58.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:10:58.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:10:58.96#ibcon#enter wrdev, iclass 30, count 2 2006.257.05:10:58.96#ibcon#first serial, iclass 30, count 2 2006.257.05:10:58.96#ibcon#enter sib2, iclass 30, count 2 2006.257.05:10:58.96#ibcon#flushed, iclass 30, count 2 2006.257.05:10:58.96#ibcon#about to write, iclass 30, count 2 2006.257.05:10:58.96#ibcon#wrote, iclass 30, count 2 2006.257.05:10:58.96#ibcon#about to read 3, iclass 30, count 2 2006.257.05:10:58.98#ibcon#read 3, iclass 30, count 2 2006.257.05:10:58.98#ibcon#about to read 4, iclass 30, count 2 2006.257.05:10:58.98#ibcon#read 4, iclass 30, count 2 2006.257.05:10:58.98#ibcon#about to read 5, iclass 30, count 2 2006.257.05:10:58.98#ibcon#read 5, iclass 30, count 2 2006.257.05:10:58.98#ibcon#about to read 6, iclass 30, count 2 2006.257.05:10:58.98#ibcon#read 6, iclass 30, count 2 2006.257.05:10:58.98#ibcon#end of sib2, iclass 30, count 2 2006.257.05:10:58.98#ibcon#*mode == 0, iclass 30, count 2 2006.257.05:10:58.98#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.05:10:58.98#ibcon#[25=AT05-04\r\n] 2006.257.05:10:58.98#ibcon#*before write, iclass 30, count 2 2006.257.05:10:58.98#ibcon#enter sib2, iclass 30, count 2 2006.257.05:10:58.98#ibcon#flushed, iclass 30, count 2 2006.257.05:10:58.98#ibcon#about to write, iclass 30, count 2 2006.257.05:10:58.98#ibcon#wrote, iclass 30, count 2 2006.257.05:10:58.98#ibcon#about to read 3, iclass 30, count 2 2006.257.05:10:59.01#ibcon#read 3, iclass 30, count 2 2006.257.05:10:59.01#ibcon#about to read 4, iclass 30, count 2 2006.257.05:10:59.01#ibcon#read 4, iclass 30, count 2 2006.257.05:10:59.01#ibcon#about to read 5, iclass 30, count 2 2006.257.05:10:59.01#ibcon#read 5, iclass 30, count 2 2006.257.05:10:59.01#ibcon#about to read 6, iclass 30, count 2 2006.257.05:10:59.01#ibcon#read 6, iclass 30, count 2 2006.257.05:10:59.01#ibcon#end of sib2, iclass 30, count 2 2006.257.05:10:59.01#ibcon#*after write, iclass 30, count 2 2006.257.05:10:59.01#ibcon#*before return 0, iclass 30, count 2 2006.257.05:10:59.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:10:59.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:10:59.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.05:10:59.01#ibcon#ireg 7 cls_cnt 0 2006.257.05:10:59.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:10:59.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:10:59.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:10:59.13#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:10:59.13#ibcon#first serial, iclass 30, count 0 2006.257.05:10:59.13#ibcon#enter sib2, iclass 30, count 0 2006.257.05:10:59.13#ibcon#flushed, iclass 30, count 0 2006.257.05:10:59.13#ibcon#about to write, iclass 30, count 0 2006.257.05:10:59.13#ibcon#wrote, iclass 30, count 0 2006.257.05:10:59.13#ibcon#about to read 3, iclass 30, count 0 2006.257.05:10:59.15#ibcon#read 3, iclass 30, count 0 2006.257.05:10:59.15#ibcon#about to read 4, iclass 30, count 0 2006.257.05:10:59.15#ibcon#read 4, iclass 30, count 0 2006.257.05:10:59.15#ibcon#about to read 5, iclass 30, count 0 2006.257.05:10:59.15#ibcon#read 5, iclass 30, count 0 2006.257.05:10:59.15#ibcon#about to read 6, iclass 30, count 0 2006.257.05:10:59.15#ibcon#read 6, iclass 30, count 0 2006.257.05:10:59.15#ibcon#end of sib2, iclass 30, count 0 2006.257.05:10:59.15#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:10:59.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:10:59.15#ibcon#[25=USB\r\n] 2006.257.05:10:59.15#ibcon#*before write, iclass 30, count 0 2006.257.05:10:59.15#ibcon#enter sib2, iclass 30, count 0 2006.257.05:10:59.15#ibcon#flushed, iclass 30, count 0 2006.257.05:10:59.15#ibcon#about to write, iclass 30, count 0 2006.257.05:10:59.15#ibcon#wrote, iclass 30, count 0 2006.257.05:10:59.15#ibcon#about to read 3, iclass 30, count 0 2006.257.05:10:59.18#ibcon#read 3, iclass 30, count 0 2006.257.05:10:59.18#ibcon#about to read 4, iclass 30, count 0 2006.257.05:10:59.18#ibcon#read 4, iclass 30, count 0 2006.257.05:10:59.18#ibcon#about to read 5, iclass 30, count 0 2006.257.05:10:59.18#ibcon#read 5, iclass 30, count 0 2006.257.05:10:59.18#ibcon#about to read 6, iclass 30, count 0 2006.257.05:10:59.18#ibcon#read 6, iclass 30, count 0 2006.257.05:10:59.18#ibcon#end of sib2, iclass 30, count 0 2006.257.05:10:59.18#ibcon#*after write, iclass 30, count 0 2006.257.05:10:59.18#ibcon#*before return 0, iclass 30, count 0 2006.257.05:10:59.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:10:59.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:10:59.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:10:59.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:10:59.18$vck44/valo=6,814.99 2006.257.05:10:59.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.05:10:59.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.05:10:59.18#ibcon#ireg 17 cls_cnt 0 2006.257.05:10:59.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:10:59.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:10:59.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:10:59.18#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:10:59.18#ibcon#first serial, iclass 32, count 0 2006.257.05:10:59.18#ibcon#enter sib2, iclass 32, count 0 2006.257.05:10:59.18#ibcon#flushed, iclass 32, count 0 2006.257.05:10:59.18#ibcon#about to write, iclass 32, count 0 2006.257.05:10:59.18#ibcon#wrote, iclass 32, count 0 2006.257.05:10:59.18#ibcon#about to read 3, iclass 32, count 0 2006.257.05:10:59.20#ibcon#read 3, iclass 32, count 0 2006.257.05:10:59.20#ibcon#about to read 4, iclass 32, count 0 2006.257.05:10:59.20#ibcon#read 4, iclass 32, count 0 2006.257.05:10:59.20#ibcon#about to read 5, iclass 32, count 0 2006.257.05:10:59.20#ibcon#read 5, iclass 32, count 0 2006.257.05:10:59.20#ibcon#about to read 6, iclass 32, count 0 2006.257.05:10:59.20#ibcon#read 6, iclass 32, count 0 2006.257.05:10:59.20#ibcon#end of sib2, iclass 32, count 0 2006.257.05:10:59.20#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:10:59.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:10:59.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:10:59.20#ibcon#*before write, iclass 32, count 0 2006.257.05:10:59.20#ibcon#enter sib2, iclass 32, count 0 2006.257.05:10:59.20#ibcon#flushed, iclass 32, count 0 2006.257.05:10:59.20#ibcon#about to write, iclass 32, count 0 2006.257.05:10:59.20#ibcon#wrote, iclass 32, count 0 2006.257.05:10:59.20#ibcon#about to read 3, iclass 32, count 0 2006.257.05:10:59.24#ibcon#read 3, iclass 32, count 0 2006.257.05:10:59.24#ibcon#about to read 4, iclass 32, count 0 2006.257.05:10:59.24#ibcon#read 4, iclass 32, count 0 2006.257.05:10:59.24#ibcon#about to read 5, iclass 32, count 0 2006.257.05:10:59.24#ibcon#read 5, iclass 32, count 0 2006.257.05:10:59.24#ibcon#about to read 6, iclass 32, count 0 2006.257.05:10:59.24#ibcon#read 6, iclass 32, count 0 2006.257.05:10:59.24#ibcon#end of sib2, iclass 32, count 0 2006.257.05:10:59.24#ibcon#*after write, iclass 32, count 0 2006.257.05:10:59.24#ibcon#*before return 0, iclass 32, count 0 2006.257.05:10:59.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:10:59.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:10:59.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:10:59.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:10:59.24$vck44/va=6,4 2006.257.05:10:59.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.05:10:59.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.05:10:59.24#ibcon#ireg 11 cls_cnt 2 2006.257.05:10:59.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:10:59.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:10:59.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:10:59.30#ibcon#enter wrdev, iclass 34, count 2 2006.257.05:10:59.30#ibcon#first serial, iclass 34, count 2 2006.257.05:10:59.30#ibcon#enter sib2, iclass 34, count 2 2006.257.05:10:59.30#ibcon#flushed, iclass 34, count 2 2006.257.05:10:59.30#ibcon#about to write, iclass 34, count 2 2006.257.05:10:59.30#ibcon#wrote, iclass 34, count 2 2006.257.05:10:59.30#ibcon#about to read 3, iclass 34, count 2 2006.257.05:10:59.32#ibcon#read 3, iclass 34, count 2 2006.257.05:10:59.32#ibcon#about to read 4, iclass 34, count 2 2006.257.05:10:59.32#ibcon#read 4, iclass 34, count 2 2006.257.05:10:59.32#ibcon#about to read 5, iclass 34, count 2 2006.257.05:10:59.32#ibcon#read 5, iclass 34, count 2 2006.257.05:10:59.32#ibcon#about to read 6, iclass 34, count 2 2006.257.05:10:59.32#ibcon#read 6, iclass 34, count 2 2006.257.05:10:59.32#ibcon#end of sib2, iclass 34, count 2 2006.257.05:10:59.32#ibcon#*mode == 0, iclass 34, count 2 2006.257.05:10:59.32#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.05:10:59.32#ibcon#[25=AT06-04\r\n] 2006.257.05:10:59.32#ibcon#*before write, iclass 34, count 2 2006.257.05:10:59.32#ibcon#enter sib2, iclass 34, count 2 2006.257.05:10:59.32#ibcon#flushed, iclass 34, count 2 2006.257.05:10:59.32#ibcon#about to write, iclass 34, count 2 2006.257.05:10:59.32#ibcon#wrote, iclass 34, count 2 2006.257.05:10:59.32#ibcon#about to read 3, iclass 34, count 2 2006.257.05:10:59.35#ibcon#read 3, iclass 34, count 2 2006.257.05:10:59.35#ibcon#about to read 4, iclass 34, count 2 2006.257.05:10:59.35#ibcon#read 4, iclass 34, count 2 2006.257.05:10:59.35#ibcon#about to read 5, iclass 34, count 2 2006.257.05:10:59.35#ibcon#read 5, iclass 34, count 2 2006.257.05:10:59.35#ibcon#about to read 6, iclass 34, count 2 2006.257.05:10:59.35#ibcon#read 6, iclass 34, count 2 2006.257.05:10:59.35#ibcon#end of sib2, iclass 34, count 2 2006.257.05:10:59.35#ibcon#*after write, iclass 34, count 2 2006.257.05:10:59.35#ibcon#*before return 0, iclass 34, count 2 2006.257.05:10:59.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:10:59.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:10:59.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.05:10:59.35#ibcon#ireg 7 cls_cnt 0 2006.257.05:10:59.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:10:59.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:10:59.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:10:59.47#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:10:59.47#ibcon#first serial, iclass 34, count 0 2006.257.05:10:59.47#ibcon#enter sib2, iclass 34, count 0 2006.257.05:10:59.47#ibcon#flushed, iclass 34, count 0 2006.257.05:10:59.47#ibcon#about to write, iclass 34, count 0 2006.257.05:10:59.47#ibcon#wrote, iclass 34, count 0 2006.257.05:10:59.47#ibcon#about to read 3, iclass 34, count 0 2006.257.05:10:59.49#ibcon#read 3, iclass 34, count 0 2006.257.05:10:59.49#ibcon#about to read 4, iclass 34, count 0 2006.257.05:10:59.49#ibcon#read 4, iclass 34, count 0 2006.257.05:10:59.49#ibcon#about to read 5, iclass 34, count 0 2006.257.05:10:59.49#ibcon#read 5, iclass 34, count 0 2006.257.05:10:59.49#ibcon#about to read 6, iclass 34, count 0 2006.257.05:10:59.49#ibcon#read 6, iclass 34, count 0 2006.257.05:10:59.49#ibcon#end of sib2, iclass 34, count 0 2006.257.05:10:59.49#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:10:59.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:10:59.49#ibcon#[25=USB\r\n] 2006.257.05:10:59.49#ibcon#*before write, iclass 34, count 0 2006.257.05:10:59.49#ibcon#enter sib2, iclass 34, count 0 2006.257.05:10:59.49#ibcon#flushed, iclass 34, count 0 2006.257.05:10:59.49#ibcon#about to write, iclass 34, count 0 2006.257.05:10:59.49#ibcon#wrote, iclass 34, count 0 2006.257.05:10:59.49#ibcon#about to read 3, iclass 34, count 0 2006.257.05:10:59.52#ibcon#read 3, iclass 34, count 0 2006.257.05:10:59.52#ibcon#about to read 4, iclass 34, count 0 2006.257.05:10:59.52#ibcon#read 4, iclass 34, count 0 2006.257.05:10:59.52#ibcon#about to read 5, iclass 34, count 0 2006.257.05:10:59.52#ibcon#read 5, iclass 34, count 0 2006.257.05:10:59.52#ibcon#about to read 6, iclass 34, count 0 2006.257.05:10:59.52#ibcon#read 6, iclass 34, count 0 2006.257.05:10:59.52#ibcon#end of sib2, iclass 34, count 0 2006.257.05:10:59.52#ibcon#*after write, iclass 34, count 0 2006.257.05:10:59.52#ibcon#*before return 0, iclass 34, count 0 2006.257.05:10:59.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:10:59.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:10:59.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:10:59.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:10:59.52$vck44/valo=7,864.99 2006.257.05:10:59.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.05:10:59.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.05:10:59.52#ibcon#ireg 17 cls_cnt 0 2006.257.05:10:59.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:10:59.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:10:59.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:10:59.52#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:10:59.52#ibcon#first serial, iclass 36, count 0 2006.257.05:10:59.52#ibcon#enter sib2, iclass 36, count 0 2006.257.05:10:59.52#ibcon#flushed, iclass 36, count 0 2006.257.05:10:59.52#ibcon#about to write, iclass 36, count 0 2006.257.05:10:59.52#ibcon#wrote, iclass 36, count 0 2006.257.05:10:59.52#ibcon#about to read 3, iclass 36, count 0 2006.257.05:10:59.54#ibcon#read 3, iclass 36, count 0 2006.257.05:10:59.54#ibcon#about to read 4, iclass 36, count 0 2006.257.05:10:59.54#ibcon#read 4, iclass 36, count 0 2006.257.05:10:59.54#ibcon#about to read 5, iclass 36, count 0 2006.257.05:10:59.54#ibcon#read 5, iclass 36, count 0 2006.257.05:10:59.54#ibcon#about to read 6, iclass 36, count 0 2006.257.05:10:59.54#ibcon#read 6, iclass 36, count 0 2006.257.05:10:59.54#ibcon#end of sib2, iclass 36, count 0 2006.257.05:10:59.54#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:10:59.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:10:59.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:10:59.54#ibcon#*before write, iclass 36, count 0 2006.257.05:10:59.54#ibcon#enter sib2, iclass 36, count 0 2006.257.05:10:59.54#ibcon#flushed, iclass 36, count 0 2006.257.05:10:59.54#ibcon#about to write, iclass 36, count 0 2006.257.05:10:59.54#ibcon#wrote, iclass 36, count 0 2006.257.05:10:59.54#ibcon#about to read 3, iclass 36, count 0 2006.257.05:10:59.58#ibcon#read 3, iclass 36, count 0 2006.257.05:10:59.58#ibcon#about to read 4, iclass 36, count 0 2006.257.05:10:59.58#ibcon#read 4, iclass 36, count 0 2006.257.05:10:59.58#ibcon#about to read 5, iclass 36, count 0 2006.257.05:10:59.58#ibcon#read 5, iclass 36, count 0 2006.257.05:10:59.58#ibcon#about to read 6, iclass 36, count 0 2006.257.05:10:59.58#ibcon#read 6, iclass 36, count 0 2006.257.05:10:59.58#ibcon#end of sib2, iclass 36, count 0 2006.257.05:10:59.58#ibcon#*after write, iclass 36, count 0 2006.257.05:10:59.58#ibcon#*before return 0, iclass 36, count 0 2006.257.05:10:59.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:10:59.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:10:59.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:10:59.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:10:59.58$vck44/va=7,4 2006.257.05:10:59.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.05:10:59.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.05:10:59.58#ibcon#ireg 11 cls_cnt 2 2006.257.05:10:59.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:10:59.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:10:59.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:10:59.64#ibcon#enter wrdev, iclass 38, count 2 2006.257.05:10:59.64#ibcon#first serial, iclass 38, count 2 2006.257.05:10:59.64#ibcon#enter sib2, iclass 38, count 2 2006.257.05:10:59.64#ibcon#flushed, iclass 38, count 2 2006.257.05:10:59.64#ibcon#about to write, iclass 38, count 2 2006.257.05:10:59.64#ibcon#wrote, iclass 38, count 2 2006.257.05:10:59.64#ibcon#about to read 3, iclass 38, count 2 2006.257.05:10:59.66#ibcon#read 3, iclass 38, count 2 2006.257.05:10:59.66#ibcon#about to read 4, iclass 38, count 2 2006.257.05:10:59.66#ibcon#read 4, iclass 38, count 2 2006.257.05:10:59.66#ibcon#about to read 5, iclass 38, count 2 2006.257.05:10:59.66#ibcon#read 5, iclass 38, count 2 2006.257.05:10:59.66#ibcon#about to read 6, iclass 38, count 2 2006.257.05:10:59.66#ibcon#read 6, iclass 38, count 2 2006.257.05:10:59.66#ibcon#end of sib2, iclass 38, count 2 2006.257.05:10:59.66#ibcon#*mode == 0, iclass 38, count 2 2006.257.05:10:59.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.05:10:59.66#ibcon#[25=AT07-04\r\n] 2006.257.05:10:59.66#ibcon#*before write, iclass 38, count 2 2006.257.05:10:59.66#ibcon#enter sib2, iclass 38, count 2 2006.257.05:10:59.66#ibcon#flushed, iclass 38, count 2 2006.257.05:10:59.66#ibcon#about to write, iclass 38, count 2 2006.257.05:10:59.66#ibcon#wrote, iclass 38, count 2 2006.257.05:10:59.66#ibcon#about to read 3, iclass 38, count 2 2006.257.05:10:59.69#ibcon#read 3, iclass 38, count 2 2006.257.05:10:59.69#ibcon#about to read 4, iclass 38, count 2 2006.257.05:10:59.69#ibcon#read 4, iclass 38, count 2 2006.257.05:10:59.69#ibcon#about to read 5, iclass 38, count 2 2006.257.05:10:59.69#ibcon#read 5, iclass 38, count 2 2006.257.05:10:59.69#ibcon#about to read 6, iclass 38, count 2 2006.257.05:10:59.69#ibcon#read 6, iclass 38, count 2 2006.257.05:10:59.69#ibcon#end of sib2, iclass 38, count 2 2006.257.05:10:59.69#ibcon#*after write, iclass 38, count 2 2006.257.05:10:59.69#ibcon#*before return 0, iclass 38, count 2 2006.257.05:10:59.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:10:59.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:10:59.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.05:10:59.69#ibcon#ireg 7 cls_cnt 0 2006.257.05:10:59.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:10:59.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:10:59.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:10:59.81#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:10:59.81#ibcon#first serial, iclass 38, count 0 2006.257.05:10:59.81#ibcon#enter sib2, iclass 38, count 0 2006.257.05:10:59.81#ibcon#flushed, iclass 38, count 0 2006.257.05:10:59.81#ibcon#about to write, iclass 38, count 0 2006.257.05:10:59.81#ibcon#wrote, iclass 38, count 0 2006.257.05:10:59.81#ibcon#about to read 3, iclass 38, count 0 2006.257.05:10:59.83#ibcon#read 3, iclass 38, count 0 2006.257.05:10:59.83#ibcon#about to read 4, iclass 38, count 0 2006.257.05:10:59.83#ibcon#read 4, iclass 38, count 0 2006.257.05:10:59.83#ibcon#about to read 5, iclass 38, count 0 2006.257.05:10:59.83#ibcon#read 5, iclass 38, count 0 2006.257.05:10:59.83#ibcon#about to read 6, iclass 38, count 0 2006.257.05:10:59.83#ibcon#read 6, iclass 38, count 0 2006.257.05:10:59.83#ibcon#end of sib2, iclass 38, count 0 2006.257.05:10:59.83#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:10:59.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:10:59.83#ibcon#[25=USB\r\n] 2006.257.05:10:59.83#ibcon#*before write, iclass 38, count 0 2006.257.05:10:59.83#ibcon#enter sib2, iclass 38, count 0 2006.257.05:10:59.83#ibcon#flushed, iclass 38, count 0 2006.257.05:10:59.83#ibcon#about to write, iclass 38, count 0 2006.257.05:10:59.83#ibcon#wrote, iclass 38, count 0 2006.257.05:10:59.83#ibcon#about to read 3, iclass 38, count 0 2006.257.05:10:59.86#ibcon#read 3, iclass 38, count 0 2006.257.05:10:59.86#ibcon#about to read 4, iclass 38, count 0 2006.257.05:10:59.86#ibcon#read 4, iclass 38, count 0 2006.257.05:10:59.86#ibcon#about to read 5, iclass 38, count 0 2006.257.05:10:59.86#ibcon#read 5, iclass 38, count 0 2006.257.05:10:59.86#ibcon#about to read 6, iclass 38, count 0 2006.257.05:10:59.86#ibcon#read 6, iclass 38, count 0 2006.257.05:10:59.86#ibcon#end of sib2, iclass 38, count 0 2006.257.05:10:59.86#ibcon#*after write, iclass 38, count 0 2006.257.05:10:59.86#ibcon#*before return 0, iclass 38, count 0 2006.257.05:10:59.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:10:59.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:10:59.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:10:59.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:10:59.86$vck44/valo=8,884.99 2006.257.05:10:59.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.05:10:59.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.05:10:59.86#ibcon#ireg 17 cls_cnt 0 2006.257.05:10:59.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:10:59.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:10:59.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:10:59.86#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:10:59.86#ibcon#first serial, iclass 40, count 0 2006.257.05:10:59.86#ibcon#enter sib2, iclass 40, count 0 2006.257.05:10:59.86#ibcon#flushed, iclass 40, count 0 2006.257.05:10:59.86#ibcon#about to write, iclass 40, count 0 2006.257.05:10:59.86#ibcon#wrote, iclass 40, count 0 2006.257.05:10:59.86#ibcon#about to read 3, iclass 40, count 0 2006.257.05:10:59.88#ibcon#read 3, iclass 40, count 0 2006.257.05:10:59.88#ibcon#about to read 4, iclass 40, count 0 2006.257.05:10:59.88#ibcon#read 4, iclass 40, count 0 2006.257.05:10:59.88#ibcon#about to read 5, iclass 40, count 0 2006.257.05:10:59.88#ibcon#read 5, iclass 40, count 0 2006.257.05:10:59.88#ibcon#about to read 6, iclass 40, count 0 2006.257.05:10:59.88#ibcon#read 6, iclass 40, count 0 2006.257.05:10:59.88#ibcon#end of sib2, iclass 40, count 0 2006.257.05:10:59.88#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:10:59.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:10:59.88#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:10:59.88#ibcon#*before write, iclass 40, count 0 2006.257.05:10:59.88#ibcon#enter sib2, iclass 40, count 0 2006.257.05:10:59.88#ibcon#flushed, iclass 40, count 0 2006.257.05:10:59.88#ibcon#about to write, iclass 40, count 0 2006.257.05:10:59.88#ibcon#wrote, iclass 40, count 0 2006.257.05:10:59.88#ibcon#about to read 3, iclass 40, count 0 2006.257.05:10:59.92#ibcon#read 3, iclass 40, count 0 2006.257.05:10:59.92#ibcon#about to read 4, iclass 40, count 0 2006.257.05:10:59.92#ibcon#read 4, iclass 40, count 0 2006.257.05:10:59.92#ibcon#about to read 5, iclass 40, count 0 2006.257.05:10:59.92#ibcon#read 5, iclass 40, count 0 2006.257.05:10:59.92#ibcon#about to read 6, iclass 40, count 0 2006.257.05:10:59.92#ibcon#read 6, iclass 40, count 0 2006.257.05:10:59.92#ibcon#end of sib2, iclass 40, count 0 2006.257.05:10:59.92#ibcon#*after write, iclass 40, count 0 2006.257.05:10:59.92#ibcon#*before return 0, iclass 40, count 0 2006.257.05:10:59.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:10:59.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:10:59.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:10:59.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:10:59.92$vck44/va=8,4 2006.257.05:10:59.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.05:10:59.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.05:10:59.92#ibcon#ireg 11 cls_cnt 2 2006.257.05:10:59.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:10:59.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:10:59.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:10:59.98#ibcon#enter wrdev, iclass 4, count 2 2006.257.05:10:59.98#ibcon#first serial, iclass 4, count 2 2006.257.05:10:59.98#ibcon#enter sib2, iclass 4, count 2 2006.257.05:10:59.98#ibcon#flushed, iclass 4, count 2 2006.257.05:10:59.98#ibcon#about to write, iclass 4, count 2 2006.257.05:10:59.98#ibcon#wrote, iclass 4, count 2 2006.257.05:10:59.98#ibcon#about to read 3, iclass 4, count 2 2006.257.05:11:00.00#ibcon#read 3, iclass 4, count 2 2006.257.05:11:00.00#ibcon#about to read 4, iclass 4, count 2 2006.257.05:11:00.00#ibcon#read 4, iclass 4, count 2 2006.257.05:11:00.00#ibcon#about to read 5, iclass 4, count 2 2006.257.05:11:00.00#ibcon#read 5, iclass 4, count 2 2006.257.05:11:00.00#ibcon#about to read 6, iclass 4, count 2 2006.257.05:11:00.00#ibcon#read 6, iclass 4, count 2 2006.257.05:11:00.00#ibcon#end of sib2, iclass 4, count 2 2006.257.05:11:00.00#ibcon#*mode == 0, iclass 4, count 2 2006.257.05:11:00.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.05:11:00.00#ibcon#[25=AT08-04\r\n] 2006.257.05:11:00.00#ibcon#*before write, iclass 4, count 2 2006.257.05:11:00.00#ibcon#enter sib2, iclass 4, count 2 2006.257.05:11:00.00#ibcon#flushed, iclass 4, count 2 2006.257.05:11:00.00#ibcon#about to write, iclass 4, count 2 2006.257.05:11:00.00#ibcon#wrote, iclass 4, count 2 2006.257.05:11:00.00#ibcon#about to read 3, iclass 4, count 2 2006.257.05:11:00.03#ibcon#read 3, iclass 4, count 2 2006.257.05:11:00.03#ibcon#about to read 4, iclass 4, count 2 2006.257.05:11:00.03#ibcon#read 4, iclass 4, count 2 2006.257.05:11:00.03#ibcon#about to read 5, iclass 4, count 2 2006.257.05:11:00.03#ibcon#read 5, iclass 4, count 2 2006.257.05:11:00.03#ibcon#about to read 6, iclass 4, count 2 2006.257.05:11:00.03#ibcon#read 6, iclass 4, count 2 2006.257.05:11:00.03#ibcon#end of sib2, iclass 4, count 2 2006.257.05:11:00.03#ibcon#*after write, iclass 4, count 2 2006.257.05:11:00.03#ibcon#*before return 0, iclass 4, count 2 2006.257.05:11:00.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:11:00.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:11:00.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.05:11:00.03#ibcon#ireg 7 cls_cnt 0 2006.257.05:11:00.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:00.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:00.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:00.15#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:11:00.15#ibcon#first serial, iclass 4, count 0 2006.257.05:11:00.15#ibcon#enter sib2, iclass 4, count 0 2006.257.05:11:00.15#ibcon#flushed, iclass 4, count 0 2006.257.05:11:00.15#ibcon#about to write, iclass 4, count 0 2006.257.05:11:00.15#ibcon#wrote, iclass 4, count 0 2006.257.05:11:00.15#ibcon#about to read 3, iclass 4, count 0 2006.257.05:11:00.17#ibcon#read 3, iclass 4, count 0 2006.257.05:11:00.17#ibcon#about to read 4, iclass 4, count 0 2006.257.05:11:00.17#ibcon#read 4, iclass 4, count 0 2006.257.05:11:00.17#ibcon#about to read 5, iclass 4, count 0 2006.257.05:11:00.17#ibcon#read 5, iclass 4, count 0 2006.257.05:11:00.17#ibcon#about to read 6, iclass 4, count 0 2006.257.05:11:00.17#ibcon#read 6, iclass 4, count 0 2006.257.05:11:00.17#ibcon#end of sib2, iclass 4, count 0 2006.257.05:11:00.17#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:11:00.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:11:00.17#ibcon#[25=USB\r\n] 2006.257.05:11:00.17#ibcon#*before write, iclass 4, count 0 2006.257.05:11:00.17#ibcon#enter sib2, iclass 4, count 0 2006.257.05:11:00.17#ibcon#flushed, iclass 4, count 0 2006.257.05:11:00.17#ibcon#about to write, iclass 4, count 0 2006.257.05:11:00.17#ibcon#wrote, iclass 4, count 0 2006.257.05:11:00.17#ibcon#about to read 3, iclass 4, count 0 2006.257.05:11:00.20#ibcon#read 3, iclass 4, count 0 2006.257.05:11:00.20#ibcon#about to read 4, iclass 4, count 0 2006.257.05:11:00.20#ibcon#read 4, iclass 4, count 0 2006.257.05:11:00.20#ibcon#about to read 5, iclass 4, count 0 2006.257.05:11:00.20#ibcon#read 5, iclass 4, count 0 2006.257.05:11:00.20#ibcon#about to read 6, iclass 4, count 0 2006.257.05:11:00.20#ibcon#read 6, iclass 4, count 0 2006.257.05:11:00.20#ibcon#end of sib2, iclass 4, count 0 2006.257.05:11:00.20#ibcon#*after write, iclass 4, count 0 2006.257.05:11:00.20#ibcon#*before return 0, iclass 4, count 0 2006.257.05:11:00.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:00.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:00.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:11:00.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:11:00.20$vck44/vblo=1,629.99 2006.257.05:11:00.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.05:11:00.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.05:11:00.20#ibcon#ireg 17 cls_cnt 0 2006.257.05:11:00.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:00.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:00.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:00.20#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:11:00.20#ibcon#first serial, iclass 6, count 0 2006.257.05:11:00.20#ibcon#enter sib2, iclass 6, count 0 2006.257.05:11:00.20#ibcon#flushed, iclass 6, count 0 2006.257.05:11:00.20#ibcon#about to write, iclass 6, count 0 2006.257.05:11:00.20#ibcon#wrote, iclass 6, count 0 2006.257.05:11:00.20#ibcon#about to read 3, iclass 6, count 0 2006.257.05:11:00.22#ibcon#read 3, iclass 6, count 0 2006.257.05:11:00.22#ibcon#about to read 4, iclass 6, count 0 2006.257.05:11:00.22#ibcon#read 4, iclass 6, count 0 2006.257.05:11:00.22#ibcon#about to read 5, iclass 6, count 0 2006.257.05:11:00.22#ibcon#read 5, iclass 6, count 0 2006.257.05:11:00.22#ibcon#about to read 6, iclass 6, count 0 2006.257.05:11:00.22#ibcon#read 6, iclass 6, count 0 2006.257.05:11:00.22#ibcon#end of sib2, iclass 6, count 0 2006.257.05:11:00.22#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:11:00.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:11:00.22#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:11:00.22#ibcon#*before write, iclass 6, count 0 2006.257.05:11:00.22#ibcon#enter sib2, iclass 6, count 0 2006.257.05:11:00.22#ibcon#flushed, iclass 6, count 0 2006.257.05:11:00.22#ibcon#about to write, iclass 6, count 0 2006.257.05:11:00.22#ibcon#wrote, iclass 6, count 0 2006.257.05:11:00.22#ibcon#about to read 3, iclass 6, count 0 2006.257.05:11:00.26#ibcon#read 3, iclass 6, count 0 2006.257.05:11:00.26#ibcon#about to read 4, iclass 6, count 0 2006.257.05:11:00.26#ibcon#read 4, iclass 6, count 0 2006.257.05:11:00.26#ibcon#about to read 5, iclass 6, count 0 2006.257.05:11:00.26#ibcon#read 5, iclass 6, count 0 2006.257.05:11:00.26#ibcon#about to read 6, iclass 6, count 0 2006.257.05:11:00.26#ibcon#read 6, iclass 6, count 0 2006.257.05:11:00.26#ibcon#end of sib2, iclass 6, count 0 2006.257.05:11:00.26#ibcon#*after write, iclass 6, count 0 2006.257.05:11:00.26#ibcon#*before return 0, iclass 6, count 0 2006.257.05:11:00.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:00.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:00.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:11:00.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:11:00.26$vck44/vb=1,4 2006.257.05:11:00.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.05:11:00.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.05:11:00.26#ibcon#ireg 11 cls_cnt 2 2006.257.05:11:00.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:11:00.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:11:00.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:11:00.26#ibcon#enter wrdev, iclass 10, count 2 2006.257.05:11:00.26#ibcon#first serial, iclass 10, count 2 2006.257.05:11:00.26#ibcon#enter sib2, iclass 10, count 2 2006.257.05:11:00.26#ibcon#flushed, iclass 10, count 2 2006.257.05:11:00.26#ibcon#about to write, iclass 10, count 2 2006.257.05:11:00.26#ibcon#wrote, iclass 10, count 2 2006.257.05:11:00.26#ibcon#about to read 3, iclass 10, count 2 2006.257.05:11:00.28#ibcon#read 3, iclass 10, count 2 2006.257.05:11:00.28#ibcon#about to read 4, iclass 10, count 2 2006.257.05:11:00.28#ibcon#read 4, iclass 10, count 2 2006.257.05:11:00.28#ibcon#about to read 5, iclass 10, count 2 2006.257.05:11:00.28#ibcon#read 5, iclass 10, count 2 2006.257.05:11:00.28#ibcon#about to read 6, iclass 10, count 2 2006.257.05:11:00.28#ibcon#read 6, iclass 10, count 2 2006.257.05:11:00.28#ibcon#end of sib2, iclass 10, count 2 2006.257.05:11:00.28#ibcon#*mode == 0, iclass 10, count 2 2006.257.05:11:00.28#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.05:11:00.28#ibcon#[27=AT01-04\r\n] 2006.257.05:11:00.28#ibcon#*before write, iclass 10, count 2 2006.257.05:11:00.28#ibcon#enter sib2, iclass 10, count 2 2006.257.05:11:00.28#ibcon#flushed, iclass 10, count 2 2006.257.05:11:00.28#ibcon#about to write, iclass 10, count 2 2006.257.05:11:00.28#ibcon#wrote, iclass 10, count 2 2006.257.05:11:00.28#ibcon#about to read 3, iclass 10, count 2 2006.257.05:11:00.31#ibcon#read 3, iclass 10, count 2 2006.257.05:11:00.31#ibcon#about to read 4, iclass 10, count 2 2006.257.05:11:00.31#ibcon#read 4, iclass 10, count 2 2006.257.05:11:00.31#ibcon#about to read 5, iclass 10, count 2 2006.257.05:11:00.31#ibcon#read 5, iclass 10, count 2 2006.257.05:11:00.31#ibcon#about to read 6, iclass 10, count 2 2006.257.05:11:00.31#ibcon#read 6, iclass 10, count 2 2006.257.05:11:00.31#ibcon#end of sib2, iclass 10, count 2 2006.257.05:11:00.31#ibcon#*after write, iclass 10, count 2 2006.257.05:11:00.31#ibcon#*before return 0, iclass 10, count 2 2006.257.05:11:00.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:11:00.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:11:00.31#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.05:11:00.31#ibcon#ireg 7 cls_cnt 0 2006.257.05:11:00.31#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:11:00.43#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:11:00.43#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:11:00.43#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:11:00.43#ibcon#first serial, iclass 10, count 0 2006.257.05:11:00.43#ibcon#enter sib2, iclass 10, count 0 2006.257.05:11:00.43#ibcon#flushed, iclass 10, count 0 2006.257.05:11:00.43#ibcon#about to write, iclass 10, count 0 2006.257.05:11:00.43#ibcon#wrote, iclass 10, count 0 2006.257.05:11:00.43#ibcon#about to read 3, iclass 10, count 0 2006.257.05:11:00.45#ibcon#read 3, iclass 10, count 0 2006.257.05:11:00.45#ibcon#about to read 4, iclass 10, count 0 2006.257.05:11:00.45#ibcon#read 4, iclass 10, count 0 2006.257.05:11:00.45#ibcon#about to read 5, iclass 10, count 0 2006.257.05:11:00.45#ibcon#read 5, iclass 10, count 0 2006.257.05:11:00.45#ibcon#about to read 6, iclass 10, count 0 2006.257.05:11:00.45#ibcon#read 6, iclass 10, count 0 2006.257.05:11:00.45#ibcon#end of sib2, iclass 10, count 0 2006.257.05:11:00.45#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:11:00.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:11:00.45#ibcon#[27=USB\r\n] 2006.257.05:11:00.45#ibcon#*before write, iclass 10, count 0 2006.257.05:11:00.45#ibcon#enter sib2, iclass 10, count 0 2006.257.05:11:00.45#ibcon#flushed, iclass 10, count 0 2006.257.05:11:00.45#ibcon#about to write, iclass 10, count 0 2006.257.05:11:00.45#ibcon#wrote, iclass 10, count 0 2006.257.05:11:00.45#ibcon#about to read 3, iclass 10, count 0 2006.257.05:11:00.48#ibcon#read 3, iclass 10, count 0 2006.257.05:11:00.48#ibcon#about to read 4, iclass 10, count 0 2006.257.05:11:00.48#ibcon#read 4, iclass 10, count 0 2006.257.05:11:00.48#ibcon#about to read 5, iclass 10, count 0 2006.257.05:11:00.48#ibcon#read 5, iclass 10, count 0 2006.257.05:11:00.48#ibcon#about to read 6, iclass 10, count 0 2006.257.05:11:00.48#ibcon#read 6, iclass 10, count 0 2006.257.05:11:00.48#ibcon#end of sib2, iclass 10, count 0 2006.257.05:11:00.48#ibcon#*after write, iclass 10, count 0 2006.257.05:11:00.48#ibcon#*before return 0, iclass 10, count 0 2006.257.05:11:00.48#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:11:00.48#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:11:00.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:11:00.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:11:00.48$vck44/vblo=2,634.99 2006.257.05:11:00.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.05:11:00.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.05:11:00.48#ibcon#ireg 17 cls_cnt 0 2006.257.05:11:00.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:11:00.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:11:00.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:11:00.48#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:11:00.48#ibcon#first serial, iclass 12, count 0 2006.257.05:11:00.48#ibcon#enter sib2, iclass 12, count 0 2006.257.05:11:00.48#ibcon#flushed, iclass 12, count 0 2006.257.05:11:00.48#ibcon#about to write, iclass 12, count 0 2006.257.05:11:00.48#ibcon#wrote, iclass 12, count 0 2006.257.05:11:00.48#ibcon#about to read 3, iclass 12, count 0 2006.257.05:11:00.50#ibcon#read 3, iclass 12, count 0 2006.257.05:11:00.50#ibcon#about to read 4, iclass 12, count 0 2006.257.05:11:00.50#ibcon#read 4, iclass 12, count 0 2006.257.05:11:00.50#ibcon#about to read 5, iclass 12, count 0 2006.257.05:11:00.50#ibcon#read 5, iclass 12, count 0 2006.257.05:11:00.50#ibcon#about to read 6, iclass 12, count 0 2006.257.05:11:00.50#ibcon#read 6, iclass 12, count 0 2006.257.05:11:00.50#ibcon#end of sib2, iclass 12, count 0 2006.257.05:11:00.50#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:11:00.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:11:00.50#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:11:00.50#ibcon#*before write, iclass 12, count 0 2006.257.05:11:00.50#ibcon#enter sib2, iclass 12, count 0 2006.257.05:11:00.50#ibcon#flushed, iclass 12, count 0 2006.257.05:11:00.50#ibcon#about to write, iclass 12, count 0 2006.257.05:11:00.50#ibcon#wrote, iclass 12, count 0 2006.257.05:11:00.50#ibcon#about to read 3, iclass 12, count 0 2006.257.05:11:00.54#ibcon#read 3, iclass 12, count 0 2006.257.05:11:00.54#ibcon#about to read 4, iclass 12, count 0 2006.257.05:11:00.54#ibcon#read 4, iclass 12, count 0 2006.257.05:11:00.54#ibcon#about to read 5, iclass 12, count 0 2006.257.05:11:00.54#ibcon#read 5, iclass 12, count 0 2006.257.05:11:00.54#ibcon#about to read 6, iclass 12, count 0 2006.257.05:11:00.54#ibcon#read 6, iclass 12, count 0 2006.257.05:11:00.54#ibcon#end of sib2, iclass 12, count 0 2006.257.05:11:00.54#ibcon#*after write, iclass 12, count 0 2006.257.05:11:00.54#ibcon#*before return 0, iclass 12, count 0 2006.257.05:11:00.54#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:11:00.54#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:11:00.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:11:00.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:11:00.54$vck44/vb=2,5 2006.257.05:11:00.54#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.05:11:00.54#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.05:11:00.54#ibcon#ireg 11 cls_cnt 2 2006.257.05:11:00.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:11:00.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:11:00.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:11:00.60#ibcon#enter wrdev, iclass 14, count 2 2006.257.05:11:00.60#ibcon#first serial, iclass 14, count 2 2006.257.05:11:00.60#ibcon#enter sib2, iclass 14, count 2 2006.257.05:11:00.60#ibcon#flushed, iclass 14, count 2 2006.257.05:11:00.60#ibcon#about to write, iclass 14, count 2 2006.257.05:11:00.60#ibcon#wrote, iclass 14, count 2 2006.257.05:11:00.60#ibcon#about to read 3, iclass 14, count 2 2006.257.05:11:00.62#ibcon#read 3, iclass 14, count 2 2006.257.05:11:00.62#ibcon#about to read 4, iclass 14, count 2 2006.257.05:11:00.62#ibcon#read 4, iclass 14, count 2 2006.257.05:11:00.62#ibcon#about to read 5, iclass 14, count 2 2006.257.05:11:00.62#ibcon#read 5, iclass 14, count 2 2006.257.05:11:00.62#ibcon#about to read 6, iclass 14, count 2 2006.257.05:11:00.62#ibcon#read 6, iclass 14, count 2 2006.257.05:11:00.62#ibcon#end of sib2, iclass 14, count 2 2006.257.05:11:00.62#ibcon#*mode == 0, iclass 14, count 2 2006.257.05:11:00.62#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.05:11:00.62#ibcon#[27=AT02-05\r\n] 2006.257.05:11:00.62#ibcon#*before write, iclass 14, count 2 2006.257.05:11:00.62#ibcon#enter sib2, iclass 14, count 2 2006.257.05:11:00.62#ibcon#flushed, iclass 14, count 2 2006.257.05:11:00.62#ibcon#about to write, iclass 14, count 2 2006.257.05:11:00.62#ibcon#wrote, iclass 14, count 2 2006.257.05:11:00.62#ibcon#about to read 3, iclass 14, count 2 2006.257.05:11:00.65#ibcon#read 3, iclass 14, count 2 2006.257.05:11:00.65#ibcon#about to read 4, iclass 14, count 2 2006.257.05:11:00.65#ibcon#read 4, iclass 14, count 2 2006.257.05:11:00.65#ibcon#about to read 5, iclass 14, count 2 2006.257.05:11:00.65#ibcon#read 5, iclass 14, count 2 2006.257.05:11:00.65#ibcon#about to read 6, iclass 14, count 2 2006.257.05:11:00.65#ibcon#read 6, iclass 14, count 2 2006.257.05:11:00.65#ibcon#end of sib2, iclass 14, count 2 2006.257.05:11:00.65#ibcon#*after write, iclass 14, count 2 2006.257.05:11:00.65#ibcon#*before return 0, iclass 14, count 2 2006.257.05:11:00.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:11:00.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:11:00.65#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.05:11:00.65#ibcon#ireg 7 cls_cnt 0 2006.257.05:11:00.65#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:11:00.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:11:00.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:11:00.77#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:11:00.77#ibcon#first serial, iclass 14, count 0 2006.257.05:11:00.77#ibcon#enter sib2, iclass 14, count 0 2006.257.05:11:00.77#ibcon#flushed, iclass 14, count 0 2006.257.05:11:00.77#ibcon#about to write, iclass 14, count 0 2006.257.05:11:00.77#ibcon#wrote, iclass 14, count 0 2006.257.05:11:00.77#ibcon#about to read 3, iclass 14, count 0 2006.257.05:11:00.79#ibcon#read 3, iclass 14, count 0 2006.257.05:11:00.79#ibcon#about to read 4, iclass 14, count 0 2006.257.05:11:00.79#ibcon#read 4, iclass 14, count 0 2006.257.05:11:00.79#ibcon#about to read 5, iclass 14, count 0 2006.257.05:11:00.79#ibcon#read 5, iclass 14, count 0 2006.257.05:11:00.79#ibcon#about to read 6, iclass 14, count 0 2006.257.05:11:00.79#ibcon#read 6, iclass 14, count 0 2006.257.05:11:00.79#ibcon#end of sib2, iclass 14, count 0 2006.257.05:11:00.79#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:11:00.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:11:00.79#ibcon#[27=USB\r\n] 2006.257.05:11:00.79#ibcon#*before write, iclass 14, count 0 2006.257.05:11:00.79#ibcon#enter sib2, iclass 14, count 0 2006.257.05:11:00.79#ibcon#flushed, iclass 14, count 0 2006.257.05:11:00.79#ibcon#about to write, iclass 14, count 0 2006.257.05:11:00.79#ibcon#wrote, iclass 14, count 0 2006.257.05:11:00.79#ibcon#about to read 3, iclass 14, count 0 2006.257.05:11:00.82#ibcon#read 3, iclass 14, count 0 2006.257.05:11:00.82#ibcon#about to read 4, iclass 14, count 0 2006.257.05:11:00.82#ibcon#read 4, iclass 14, count 0 2006.257.05:11:00.82#ibcon#about to read 5, iclass 14, count 0 2006.257.05:11:00.82#ibcon#read 5, iclass 14, count 0 2006.257.05:11:00.82#ibcon#about to read 6, iclass 14, count 0 2006.257.05:11:00.82#ibcon#read 6, iclass 14, count 0 2006.257.05:11:00.82#ibcon#end of sib2, iclass 14, count 0 2006.257.05:11:00.82#ibcon#*after write, iclass 14, count 0 2006.257.05:11:00.82#ibcon#*before return 0, iclass 14, count 0 2006.257.05:11:00.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:11:00.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:11:00.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:11:00.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:11:00.82$vck44/vblo=3,649.99 2006.257.05:11:00.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.05:11:00.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.05:11:00.82#ibcon#ireg 17 cls_cnt 0 2006.257.05:11:00.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:11:00.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:11:00.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:11:00.82#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:11:00.82#ibcon#first serial, iclass 16, count 0 2006.257.05:11:00.82#ibcon#enter sib2, iclass 16, count 0 2006.257.05:11:00.82#ibcon#flushed, iclass 16, count 0 2006.257.05:11:00.82#ibcon#about to write, iclass 16, count 0 2006.257.05:11:00.82#ibcon#wrote, iclass 16, count 0 2006.257.05:11:00.82#ibcon#about to read 3, iclass 16, count 0 2006.257.05:11:00.84#ibcon#read 3, iclass 16, count 0 2006.257.05:11:00.84#ibcon#about to read 4, iclass 16, count 0 2006.257.05:11:00.84#ibcon#read 4, iclass 16, count 0 2006.257.05:11:00.84#ibcon#about to read 5, iclass 16, count 0 2006.257.05:11:00.84#ibcon#read 5, iclass 16, count 0 2006.257.05:11:00.84#ibcon#about to read 6, iclass 16, count 0 2006.257.05:11:00.84#ibcon#read 6, iclass 16, count 0 2006.257.05:11:00.84#ibcon#end of sib2, iclass 16, count 0 2006.257.05:11:00.84#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:11:00.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:11:00.84#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:11:00.84#ibcon#*before write, iclass 16, count 0 2006.257.05:11:00.84#ibcon#enter sib2, iclass 16, count 0 2006.257.05:11:00.84#ibcon#flushed, iclass 16, count 0 2006.257.05:11:00.84#ibcon#about to write, iclass 16, count 0 2006.257.05:11:00.84#ibcon#wrote, iclass 16, count 0 2006.257.05:11:00.84#ibcon#about to read 3, iclass 16, count 0 2006.257.05:11:00.88#ibcon#read 3, iclass 16, count 0 2006.257.05:11:00.88#ibcon#about to read 4, iclass 16, count 0 2006.257.05:11:00.88#ibcon#read 4, iclass 16, count 0 2006.257.05:11:00.88#ibcon#about to read 5, iclass 16, count 0 2006.257.05:11:00.88#ibcon#read 5, iclass 16, count 0 2006.257.05:11:00.88#ibcon#about to read 6, iclass 16, count 0 2006.257.05:11:00.88#ibcon#read 6, iclass 16, count 0 2006.257.05:11:00.88#ibcon#end of sib2, iclass 16, count 0 2006.257.05:11:00.88#ibcon#*after write, iclass 16, count 0 2006.257.05:11:00.88#ibcon#*before return 0, iclass 16, count 0 2006.257.05:11:00.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:11:00.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:11:00.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:11:00.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:11:00.88$vck44/vb=3,4 2006.257.05:11:00.88#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.05:11:00.88#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.05:11:00.88#ibcon#ireg 11 cls_cnt 2 2006.257.05:11:00.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:11:00.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:11:00.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:11:00.94#ibcon#enter wrdev, iclass 18, count 2 2006.257.05:11:00.94#ibcon#first serial, iclass 18, count 2 2006.257.05:11:00.94#ibcon#enter sib2, iclass 18, count 2 2006.257.05:11:00.94#ibcon#flushed, iclass 18, count 2 2006.257.05:11:00.94#ibcon#about to write, iclass 18, count 2 2006.257.05:11:00.94#ibcon#wrote, iclass 18, count 2 2006.257.05:11:00.94#ibcon#about to read 3, iclass 18, count 2 2006.257.05:11:00.96#ibcon#read 3, iclass 18, count 2 2006.257.05:11:00.96#ibcon#about to read 4, iclass 18, count 2 2006.257.05:11:00.96#ibcon#read 4, iclass 18, count 2 2006.257.05:11:00.96#ibcon#about to read 5, iclass 18, count 2 2006.257.05:11:00.96#ibcon#read 5, iclass 18, count 2 2006.257.05:11:00.96#ibcon#about to read 6, iclass 18, count 2 2006.257.05:11:00.96#ibcon#read 6, iclass 18, count 2 2006.257.05:11:00.96#ibcon#end of sib2, iclass 18, count 2 2006.257.05:11:00.96#ibcon#*mode == 0, iclass 18, count 2 2006.257.05:11:00.96#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.05:11:00.96#ibcon#[27=AT03-04\r\n] 2006.257.05:11:00.96#ibcon#*before write, iclass 18, count 2 2006.257.05:11:00.96#ibcon#enter sib2, iclass 18, count 2 2006.257.05:11:00.96#ibcon#flushed, iclass 18, count 2 2006.257.05:11:00.96#ibcon#about to write, iclass 18, count 2 2006.257.05:11:00.96#ibcon#wrote, iclass 18, count 2 2006.257.05:11:00.96#ibcon#about to read 3, iclass 18, count 2 2006.257.05:11:00.99#ibcon#read 3, iclass 18, count 2 2006.257.05:11:00.99#ibcon#about to read 4, iclass 18, count 2 2006.257.05:11:00.99#ibcon#read 4, iclass 18, count 2 2006.257.05:11:00.99#ibcon#about to read 5, iclass 18, count 2 2006.257.05:11:00.99#ibcon#read 5, iclass 18, count 2 2006.257.05:11:00.99#ibcon#about to read 6, iclass 18, count 2 2006.257.05:11:00.99#ibcon#read 6, iclass 18, count 2 2006.257.05:11:00.99#ibcon#end of sib2, iclass 18, count 2 2006.257.05:11:00.99#ibcon#*after write, iclass 18, count 2 2006.257.05:11:00.99#ibcon#*before return 0, iclass 18, count 2 2006.257.05:11:00.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:11:00.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:11:00.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.05:11:00.99#ibcon#ireg 7 cls_cnt 0 2006.257.05:11:00.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:11:01.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:11:01.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:11:01.11#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:11:01.11#ibcon#first serial, iclass 18, count 0 2006.257.05:11:01.11#ibcon#enter sib2, iclass 18, count 0 2006.257.05:11:01.11#ibcon#flushed, iclass 18, count 0 2006.257.05:11:01.11#ibcon#about to write, iclass 18, count 0 2006.257.05:11:01.11#ibcon#wrote, iclass 18, count 0 2006.257.05:11:01.11#ibcon#about to read 3, iclass 18, count 0 2006.257.05:11:01.13#ibcon#read 3, iclass 18, count 0 2006.257.05:11:01.13#ibcon#about to read 4, iclass 18, count 0 2006.257.05:11:01.13#ibcon#read 4, iclass 18, count 0 2006.257.05:11:01.13#ibcon#about to read 5, iclass 18, count 0 2006.257.05:11:01.13#ibcon#read 5, iclass 18, count 0 2006.257.05:11:01.13#ibcon#about to read 6, iclass 18, count 0 2006.257.05:11:01.13#ibcon#read 6, iclass 18, count 0 2006.257.05:11:01.13#ibcon#end of sib2, iclass 18, count 0 2006.257.05:11:01.13#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:11:01.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:11:01.13#ibcon#[27=USB\r\n] 2006.257.05:11:01.13#ibcon#*before write, iclass 18, count 0 2006.257.05:11:01.13#ibcon#enter sib2, iclass 18, count 0 2006.257.05:11:01.13#ibcon#flushed, iclass 18, count 0 2006.257.05:11:01.13#ibcon#about to write, iclass 18, count 0 2006.257.05:11:01.13#ibcon#wrote, iclass 18, count 0 2006.257.05:11:01.13#ibcon#about to read 3, iclass 18, count 0 2006.257.05:11:01.16#ibcon#read 3, iclass 18, count 0 2006.257.05:11:01.16#ibcon#about to read 4, iclass 18, count 0 2006.257.05:11:01.16#ibcon#read 4, iclass 18, count 0 2006.257.05:11:01.16#ibcon#about to read 5, iclass 18, count 0 2006.257.05:11:01.16#ibcon#read 5, iclass 18, count 0 2006.257.05:11:01.16#ibcon#about to read 6, iclass 18, count 0 2006.257.05:11:01.16#ibcon#read 6, iclass 18, count 0 2006.257.05:11:01.16#ibcon#end of sib2, iclass 18, count 0 2006.257.05:11:01.16#ibcon#*after write, iclass 18, count 0 2006.257.05:11:01.16#ibcon#*before return 0, iclass 18, count 0 2006.257.05:11:01.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:11:01.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:11:01.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:11:01.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:11:01.16$vck44/vblo=4,679.99 2006.257.05:11:01.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.05:11:01.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.05:11:01.16#ibcon#ireg 17 cls_cnt 0 2006.257.05:11:01.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:11:01.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:11:01.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:11:01.16#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:11:01.16#ibcon#first serial, iclass 20, count 0 2006.257.05:11:01.16#ibcon#enter sib2, iclass 20, count 0 2006.257.05:11:01.16#ibcon#flushed, iclass 20, count 0 2006.257.05:11:01.16#ibcon#about to write, iclass 20, count 0 2006.257.05:11:01.16#ibcon#wrote, iclass 20, count 0 2006.257.05:11:01.16#ibcon#about to read 3, iclass 20, count 0 2006.257.05:11:01.18#ibcon#read 3, iclass 20, count 0 2006.257.05:11:01.18#ibcon#about to read 4, iclass 20, count 0 2006.257.05:11:01.18#ibcon#read 4, iclass 20, count 0 2006.257.05:11:01.18#ibcon#about to read 5, iclass 20, count 0 2006.257.05:11:01.18#ibcon#read 5, iclass 20, count 0 2006.257.05:11:01.18#ibcon#about to read 6, iclass 20, count 0 2006.257.05:11:01.18#ibcon#read 6, iclass 20, count 0 2006.257.05:11:01.18#ibcon#end of sib2, iclass 20, count 0 2006.257.05:11:01.18#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:11:01.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:11:01.18#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:11:01.18#ibcon#*before write, iclass 20, count 0 2006.257.05:11:01.18#ibcon#enter sib2, iclass 20, count 0 2006.257.05:11:01.18#ibcon#flushed, iclass 20, count 0 2006.257.05:11:01.18#ibcon#about to write, iclass 20, count 0 2006.257.05:11:01.18#ibcon#wrote, iclass 20, count 0 2006.257.05:11:01.18#ibcon#about to read 3, iclass 20, count 0 2006.257.05:11:01.22#ibcon#read 3, iclass 20, count 0 2006.257.05:11:01.22#ibcon#about to read 4, iclass 20, count 0 2006.257.05:11:01.22#ibcon#read 4, iclass 20, count 0 2006.257.05:11:01.22#ibcon#about to read 5, iclass 20, count 0 2006.257.05:11:01.22#ibcon#read 5, iclass 20, count 0 2006.257.05:11:01.22#ibcon#about to read 6, iclass 20, count 0 2006.257.05:11:01.22#ibcon#read 6, iclass 20, count 0 2006.257.05:11:01.22#ibcon#end of sib2, iclass 20, count 0 2006.257.05:11:01.22#ibcon#*after write, iclass 20, count 0 2006.257.05:11:01.22#ibcon#*before return 0, iclass 20, count 0 2006.257.05:11:01.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:11:01.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:11:01.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:11:01.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:11:01.22$vck44/vb=4,5 2006.257.05:11:01.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.05:11:01.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.05:11:01.22#ibcon#ireg 11 cls_cnt 2 2006.257.05:11:01.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:11:01.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:11:01.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:11:01.28#ibcon#enter wrdev, iclass 22, count 2 2006.257.05:11:01.28#ibcon#first serial, iclass 22, count 2 2006.257.05:11:01.28#ibcon#enter sib2, iclass 22, count 2 2006.257.05:11:01.28#ibcon#flushed, iclass 22, count 2 2006.257.05:11:01.28#ibcon#about to write, iclass 22, count 2 2006.257.05:11:01.28#ibcon#wrote, iclass 22, count 2 2006.257.05:11:01.28#ibcon#about to read 3, iclass 22, count 2 2006.257.05:11:01.30#ibcon#read 3, iclass 22, count 2 2006.257.05:11:01.30#ibcon#about to read 4, iclass 22, count 2 2006.257.05:11:01.30#ibcon#read 4, iclass 22, count 2 2006.257.05:11:01.30#ibcon#about to read 5, iclass 22, count 2 2006.257.05:11:01.30#ibcon#read 5, iclass 22, count 2 2006.257.05:11:01.30#ibcon#about to read 6, iclass 22, count 2 2006.257.05:11:01.30#ibcon#read 6, iclass 22, count 2 2006.257.05:11:01.30#ibcon#end of sib2, iclass 22, count 2 2006.257.05:11:01.30#ibcon#*mode == 0, iclass 22, count 2 2006.257.05:11:01.30#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.05:11:01.30#ibcon#[27=AT04-05\r\n] 2006.257.05:11:01.30#ibcon#*before write, iclass 22, count 2 2006.257.05:11:01.30#ibcon#enter sib2, iclass 22, count 2 2006.257.05:11:01.30#ibcon#flushed, iclass 22, count 2 2006.257.05:11:01.30#ibcon#about to write, iclass 22, count 2 2006.257.05:11:01.30#ibcon#wrote, iclass 22, count 2 2006.257.05:11:01.30#ibcon#about to read 3, iclass 22, count 2 2006.257.05:11:01.33#ibcon#read 3, iclass 22, count 2 2006.257.05:11:01.33#ibcon#about to read 4, iclass 22, count 2 2006.257.05:11:01.33#ibcon#read 4, iclass 22, count 2 2006.257.05:11:01.33#ibcon#about to read 5, iclass 22, count 2 2006.257.05:11:01.33#ibcon#read 5, iclass 22, count 2 2006.257.05:11:01.33#ibcon#about to read 6, iclass 22, count 2 2006.257.05:11:01.33#ibcon#read 6, iclass 22, count 2 2006.257.05:11:01.33#ibcon#end of sib2, iclass 22, count 2 2006.257.05:11:01.33#ibcon#*after write, iclass 22, count 2 2006.257.05:11:01.33#ibcon#*before return 0, iclass 22, count 2 2006.257.05:11:01.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:11:01.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:11:01.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.05:11:01.33#ibcon#ireg 7 cls_cnt 0 2006.257.05:11:01.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:11:01.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:11:01.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:11:01.45#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:11:01.45#ibcon#first serial, iclass 22, count 0 2006.257.05:11:01.45#ibcon#enter sib2, iclass 22, count 0 2006.257.05:11:01.45#ibcon#flushed, iclass 22, count 0 2006.257.05:11:01.45#ibcon#about to write, iclass 22, count 0 2006.257.05:11:01.45#ibcon#wrote, iclass 22, count 0 2006.257.05:11:01.45#ibcon#about to read 3, iclass 22, count 0 2006.257.05:11:01.47#ibcon#read 3, iclass 22, count 0 2006.257.05:11:01.47#ibcon#about to read 4, iclass 22, count 0 2006.257.05:11:01.47#ibcon#read 4, iclass 22, count 0 2006.257.05:11:01.47#ibcon#about to read 5, iclass 22, count 0 2006.257.05:11:01.47#ibcon#read 5, iclass 22, count 0 2006.257.05:11:01.47#ibcon#about to read 6, iclass 22, count 0 2006.257.05:11:01.47#ibcon#read 6, iclass 22, count 0 2006.257.05:11:01.47#ibcon#end of sib2, iclass 22, count 0 2006.257.05:11:01.47#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:11:01.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:11:01.47#ibcon#[27=USB\r\n] 2006.257.05:11:01.47#ibcon#*before write, iclass 22, count 0 2006.257.05:11:01.47#ibcon#enter sib2, iclass 22, count 0 2006.257.05:11:01.47#ibcon#flushed, iclass 22, count 0 2006.257.05:11:01.47#ibcon#about to write, iclass 22, count 0 2006.257.05:11:01.47#ibcon#wrote, iclass 22, count 0 2006.257.05:11:01.47#ibcon#about to read 3, iclass 22, count 0 2006.257.05:11:01.50#ibcon#read 3, iclass 22, count 0 2006.257.05:11:01.50#ibcon#about to read 4, iclass 22, count 0 2006.257.05:11:01.50#ibcon#read 4, iclass 22, count 0 2006.257.05:11:01.50#ibcon#about to read 5, iclass 22, count 0 2006.257.05:11:01.50#ibcon#read 5, iclass 22, count 0 2006.257.05:11:01.50#ibcon#about to read 6, iclass 22, count 0 2006.257.05:11:01.50#ibcon#read 6, iclass 22, count 0 2006.257.05:11:01.50#ibcon#end of sib2, iclass 22, count 0 2006.257.05:11:01.50#ibcon#*after write, iclass 22, count 0 2006.257.05:11:01.50#ibcon#*before return 0, iclass 22, count 0 2006.257.05:11:01.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:11:01.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:11:01.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:11:01.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:11:01.50$vck44/vblo=5,709.99 2006.257.05:11:01.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.05:11:01.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.05:11:01.50#ibcon#ireg 17 cls_cnt 0 2006.257.05:11:01.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:11:01.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:11:01.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:11:01.50#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:11:01.50#ibcon#first serial, iclass 24, count 0 2006.257.05:11:01.50#ibcon#enter sib2, iclass 24, count 0 2006.257.05:11:01.50#ibcon#flushed, iclass 24, count 0 2006.257.05:11:01.50#ibcon#about to write, iclass 24, count 0 2006.257.05:11:01.50#ibcon#wrote, iclass 24, count 0 2006.257.05:11:01.50#ibcon#about to read 3, iclass 24, count 0 2006.257.05:11:01.52#ibcon#read 3, iclass 24, count 0 2006.257.05:11:01.52#ibcon#about to read 4, iclass 24, count 0 2006.257.05:11:01.52#ibcon#read 4, iclass 24, count 0 2006.257.05:11:01.52#ibcon#about to read 5, iclass 24, count 0 2006.257.05:11:01.52#ibcon#read 5, iclass 24, count 0 2006.257.05:11:01.52#ibcon#about to read 6, iclass 24, count 0 2006.257.05:11:01.52#ibcon#read 6, iclass 24, count 0 2006.257.05:11:01.52#ibcon#end of sib2, iclass 24, count 0 2006.257.05:11:01.52#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:11:01.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:11:01.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:11:01.52#ibcon#*before write, iclass 24, count 0 2006.257.05:11:01.52#ibcon#enter sib2, iclass 24, count 0 2006.257.05:11:01.52#ibcon#flushed, iclass 24, count 0 2006.257.05:11:01.52#ibcon#about to write, iclass 24, count 0 2006.257.05:11:01.52#ibcon#wrote, iclass 24, count 0 2006.257.05:11:01.52#ibcon#about to read 3, iclass 24, count 0 2006.257.05:11:01.56#ibcon#read 3, iclass 24, count 0 2006.257.05:11:01.56#ibcon#about to read 4, iclass 24, count 0 2006.257.05:11:01.56#ibcon#read 4, iclass 24, count 0 2006.257.05:11:01.56#ibcon#about to read 5, iclass 24, count 0 2006.257.05:11:01.56#ibcon#read 5, iclass 24, count 0 2006.257.05:11:01.56#ibcon#about to read 6, iclass 24, count 0 2006.257.05:11:01.56#ibcon#read 6, iclass 24, count 0 2006.257.05:11:01.56#ibcon#end of sib2, iclass 24, count 0 2006.257.05:11:01.56#ibcon#*after write, iclass 24, count 0 2006.257.05:11:01.56#ibcon#*before return 0, iclass 24, count 0 2006.257.05:11:01.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:11:01.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:11:01.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:11:01.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:11:01.56$vck44/vb=5,4 2006.257.05:11:01.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.05:11:01.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.05:11:01.56#ibcon#ireg 11 cls_cnt 2 2006.257.05:11:01.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:11:01.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:11:01.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:11:01.62#ibcon#enter wrdev, iclass 26, count 2 2006.257.05:11:01.62#ibcon#first serial, iclass 26, count 2 2006.257.05:11:01.62#ibcon#enter sib2, iclass 26, count 2 2006.257.05:11:01.62#ibcon#flushed, iclass 26, count 2 2006.257.05:11:01.62#ibcon#about to write, iclass 26, count 2 2006.257.05:11:01.62#ibcon#wrote, iclass 26, count 2 2006.257.05:11:01.62#ibcon#about to read 3, iclass 26, count 2 2006.257.05:11:01.64#ibcon#read 3, iclass 26, count 2 2006.257.05:11:01.64#ibcon#about to read 4, iclass 26, count 2 2006.257.05:11:01.64#ibcon#read 4, iclass 26, count 2 2006.257.05:11:01.64#ibcon#about to read 5, iclass 26, count 2 2006.257.05:11:01.64#ibcon#read 5, iclass 26, count 2 2006.257.05:11:01.64#ibcon#about to read 6, iclass 26, count 2 2006.257.05:11:01.64#ibcon#read 6, iclass 26, count 2 2006.257.05:11:01.64#ibcon#end of sib2, iclass 26, count 2 2006.257.05:11:01.64#ibcon#*mode == 0, iclass 26, count 2 2006.257.05:11:01.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.05:11:01.64#ibcon#[27=AT05-04\r\n] 2006.257.05:11:01.64#ibcon#*before write, iclass 26, count 2 2006.257.05:11:01.64#ibcon#enter sib2, iclass 26, count 2 2006.257.05:11:01.64#ibcon#flushed, iclass 26, count 2 2006.257.05:11:01.64#ibcon#about to write, iclass 26, count 2 2006.257.05:11:01.64#ibcon#wrote, iclass 26, count 2 2006.257.05:11:01.64#ibcon#about to read 3, iclass 26, count 2 2006.257.05:11:01.67#ibcon#read 3, iclass 26, count 2 2006.257.05:11:01.67#ibcon#about to read 4, iclass 26, count 2 2006.257.05:11:01.67#ibcon#read 4, iclass 26, count 2 2006.257.05:11:01.67#ibcon#about to read 5, iclass 26, count 2 2006.257.05:11:01.67#ibcon#read 5, iclass 26, count 2 2006.257.05:11:01.67#ibcon#about to read 6, iclass 26, count 2 2006.257.05:11:01.67#ibcon#read 6, iclass 26, count 2 2006.257.05:11:01.67#ibcon#end of sib2, iclass 26, count 2 2006.257.05:11:01.67#ibcon#*after write, iclass 26, count 2 2006.257.05:11:01.67#ibcon#*before return 0, iclass 26, count 2 2006.257.05:11:01.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:11:01.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:11:01.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.05:11:01.67#ibcon#ireg 7 cls_cnt 0 2006.257.05:11:01.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:11:01.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:11:01.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:11:01.79#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:11:01.79#ibcon#first serial, iclass 26, count 0 2006.257.05:11:01.79#ibcon#enter sib2, iclass 26, count 0 2006.257.05:11:01.79#ibcon#flushed, iclass 26, count 0 2006.257.05:11:01.79#ibcon#about to write, iclass 26, count 0 2006.257.05:11:01.79#ibcon#wrote, iclass 26, count 0 2006.257.05:11:01.79#ibcon#about to read 3, iclass 26, count 0 2006.257.05:11:01.81#ibcon#read 3, iclass 26, count 0 2006.257.05:11:01.81#ibcon#about to read 4, iclass 26, count 0 2006.257.05:11:01.81#ibcon#read 4, iclass 26, count 0 2006.257.05:11:01.81#ibcon#about to read 5, iclass 26, count 0 2006.257.05:11:01.81#ibcon#read 5, iclass 26, count 0 2006.257.05:11:01.81#ibcon#about to read 6, iclass 26, count 0 2006.257.05:11:01.81#ibcon#read 6, iclass 26, count 0 2006.257.05:11:01.81#ibcon#end of sib2, iclass 26, count 0 2006.257.05:11:01.81#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:11:01.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:11:01.81#ibcon#[27=USB\r\n] 2006.257.05:11:01.81#ibcon#*before write, iclass 26, count 0 2006.257.05:11:01.81#ibcon#enter sib2, iclass 26, count 0 2006.257.05:11:01.81#ibcon#flushed, iclass 26, count 0 2006.257.05:11:01.81#ibcon#about to write, iclass 26, count 0 2006.257.05:11:01.81#ibcon#wrote, iclass 26, count 0 2006.257.05:11:01.81#ibcon#about to read 3, iclass 26, count 0 2006.257.05:11:01.84#abcon#<5=/15 1.7 3.8 19.72 921012.0\r\n> 2006.257.05:11:01.84#ibcon#read 3, iclass 26, count 0 2006.257.05:11:01.84#ibcon#about to read 4, iclass 26, count 0 2006.257.05:11:01.84#ibcon#read 4, iclass 26, count 0 2006.257.05:11:01.84#ibcon#about to read 5, iclass 26, count 0 2006.257.05:11:01.84#ibcon#read 5, iclass 26, count 0 2006.257.05:11:01.84#ibcon#about to read 6, iclass 26, count 0 2006.257.05:11:01.84#ibcon#read 6, iclass 26, count 0 2006.257.05:11:01.84#ibcon#end of sib2, iclass 26, count 0 2006.257.05:11:01.84#ibcon#*after write, iclass 26, count 0 2006.257.05:11:01.84#ibcon#*before return 0, iclass 26, count 0 2006.257.05:11:01.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:11:01.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:11:01.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:11:01.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:11:01.84$vck44/vblo=6,719.99 2006.257.05:11:01.84#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.05:11:01.84#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.05:11:01.84#ibcon#ireg 17 cls_cnt 0 2006.257.05:11:01.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:11:01.84#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:11:01.84#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:11:01.84#ibcon#enter wrdev, iclass 31, count 0 2006.257.05:11:01.84#ibcon#first serial, iclass 31, count 0 2006.257.05:11:01.84#ibcon#enter sib2, iclass 31, count 0 2006.257.05:11:01.84#ibcon#flushed, iclass 31, count 0 2006.257.05:11:01.84#ibcon#about to write, iclass 31, count 0 2006.257.05:11:01.84#ibcon#wrote, iclass 31, count 0 2006.257.05:11:01.84#ibcon#about to read 3, iclass 31, count 0 2006.257.05:11:01.86#abcon#{5=INTERFACE CLEAR} 2006.257.05:11:01.86#ibcon#read 3, iclass 31, count 0 2006.257.05:11:01.86#ibcon#about to read 4, iclass 31, count 0 2006.257.05:11:01.86#ibcon#read 4, iclass 31, count 0 2006.257.05:11:01.86#ibcon#about to read 5, iclass 31, count 0 2006.257.05:11:01.86#ibcon#read 5, iclass 31, count 0 2006.257.05:11:01.86#ibcon#about to read 6, iclass 31, count 0 2006.257.05:11:01.86#ibcon#read 6, iclass 31, count 0 2006.257.05:11:01.86#ibcon#end of sib2, iclass 31, count 0 2006.257.05:11:01.86#ibcon#*mode == 0, iclass 31, count 0 2006.257.05:11:01.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.05:11:01.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:11:01.86#ibcon#*before write, iclass 31, count 0 2006.257.05:11:01.86#ibcon#enter sib2, iclass 31, count 0 2006.257.05:11:01.86#ibcon#flushed, iclass 31, count 0 2006.257.05:11:01.86#ibcon#about to write, iclass 31, count 0 2006.257.05:11:01.86#ibcon#wrote, iclass 31, count 0 2006.257.05:11:01.86#ibcon#about to read 3, iclass 31, count 0 2006.257.05:11:01.90#ibcon#read 3, iclass 31, count 0 2006.257.05:11:01.90#ibcon#about to read 4, iclass 31, count 0 2006.257.05:11:01.90#ibcon#read 4, iclass 31, count 0 2006.257.05:11:01.90#ibcon#about to read 5, iclass 31, count 0 2006.257.05:11:01.90#ibcon#read 5, iclass 31, count 0 2006.257.05:11:01.90#ibcon#about to read 6, iclass 31, count 0 2006.257.05:11:01.90#ibcon#read 6, iclass 31, count 0 2006.257.05:11:01.90#ibcon#end of sib2, iclass 31, count 0 2006.257.05:11:01.90#ibcon#*after write, iclass 31, count 0 2006.257.05:11:01.90#ibcon#*before return 0, iclass 31, count 0 2006.257.05:11:01.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:11:01.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:11:01.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.05:11:01.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.05:11:01.90$vck44/vb=6,4 2006.257.05:11:01.90#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.05:11:01.90#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.05:11:01.90#ibcon#ireg 11 cls_cnt 2 2006.257.05:11:01.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:11:01.92#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:11:01.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:11:01.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:11:01.96#ibcon#enter wrdev, iclass 34, count 2 2006.257.05:11:01.96#ibcon#first serial, iclass 34, count 2 2006.257.05:11:01.96#ibcon#enter sib2, iclass 34, count 2 2006.257.05:11:01.96#ibcon#flushed, iclass 34, count 2 2006.257.05:11:01.96#ibcon#about to write, iclass 34, count 2 2006.257.05:11:01.96#ibcon#wrote, iclass 34, count 2 2006.257.05:11:01.96#ibcon#about to read 3, iclass 34, count 2 2006.257.05:11:01.98#ibcon#read 3, iclass 34, count 2 2006.257.05:11:01.98#ibcon#about to read 4, iclass 34, count 2 2006.257.05:11:01.98#ibcon#read 4, iclass 34, count 2 2006.257.05:11:01.98#ibcon#about to read 5, iclass 34, count 2 2006.257.05:11:01.98#ibcon#read 5, iclass 34, count 2 2006.257.05:11:01.98#ibcon#about to read 6, iclass 34, count 2 2006.257.05:11:01.98#ibcon#read 6, iclass 34, count 2 2006.257.05:11:01.98#ibcon#end of sib2, iclass 34, count 2 2006.257.05:11:01.98#ibcon#*mode == 0, iclass 34, count 2 2006.257.05:11:01.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.05:11:01.98#ibcon#[27=AT06-04\r\n] 2006.257.05:11:01.98#ibcon#*before write, iclass 34, count 2 2006.257.05:11:01.98#ibcon#enter sib2, iclass 34, count 2 2006.257.05:11:01.98#ibcon#flushed, iclass 34, count 2 2006.257.05:11:01.98#ibcon#about to write, iclass 34, count 2 2006.257.05:11:01.98#ibcon#wrote, iclass 34, count 2 2006.257.05:11:01.98#ibcon#about to read 3, iclass 34, count 2 2006.257.05:11:02.01#ibcon#read 3, iclass 34, count 2 2006.257.05:11:02.01#ibcon#about to read 4, iclass 34, count 2 2006.257.05:11:02.01#ibcon#read 4, iclass 34, count 2 2006.257.05:11:02.01#ibcon#about to read 5, iclass 34, count 2 2006.257.05:11:02.01#ibcon#read 5, iclass 34, count 2 2006.257.05:11:02.01#ibcon#about to read 6, iclass 34, count 2 2006.257.05:11:02.01#ibcon#read 6, iclass 34, count 2 2006.257.05:11:02.01#ibcon#end of sib2, iclass 34, count 2 2006.257.05:11:02.01#ibcon#*after write, iclass 34, count 2 2006.257.05:11:02.01#ibcon#*before return 0, iclass 34, count 2 2006.257.05:11:02.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:11:02.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:11:02.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.05:11:02.01#ibcon#ireg 7 cls_cnt 0 2006.257.05:11:02.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:11:02.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:11:02.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:11:02.13#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:11:02.13#ibcon#first serial, iclass 34, count 0 2006.257.05:11:02.13#ibcon#enter sib2, iclass 34, count 0 2006.257.05:11:02.13#ibcon#flushed, iclass 34, count 0 2006.257.05:11:02.13#ibcon#about to write, iclass 34, count 0 2006.257.05:11:02.13#ibcon#wrote, iclass 34, count 0 2006.257.05:11:02.13#ibcon#about to read 3, iclass 34, count 0 2006.257.05:11:02.15#ibcon#read 3, iclass 34, count 0 2006.257.05:11:02.15#ibcon#about to read 4, iclass 34, count 0 2006.257.05:11:02.15#ibcon#read 4, iclass 34, count 0 2006.257.05:11:02.15#ibcon#about to read 5, iclass 34, count 0 2006.257.05:11:02.15#ibcon#read 5, iclass 34, count 0 2006.257.05:11:02.15#ibcon#about to read 6, iclass 34, count 0 2006.257.05:11:02.15#ibcon#read 6, iclass 34, count 0 2006.257.05:11:02.15#ibcon#end of sib2, iclass 34, count 0 2006.257.05:11:02.15#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:11:02.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:11:02.15#ibcon#[27=USB\r\n] 2006.257.05:11:02.15#ibcon#*before write, iclass 34, count 0 2006.257.05:11:02.15#ibcon#enter sib2, iclass 34, count 0 2006.257.05:11:02.15#ibcon#flushed, iclass 34, count 0 2006.257.05:11:02.15#ibcon#about to write, iclass 34, count 0 2006.257.05:11:02.15#ibcon#wrote, iclass 34, count 0 2006.257.05:11:02.15#ibcon#about to read 3, iclass 34, count 0 2006.257.05:11:02.18#ibcon#read 3, iclass 34, count 0 2006.257.05:11:02.18#ibcon#about to read 4, iclass 34, count 0 2006.257.05:11:02.18#ibcon#read 4, iclass 34, count 0 2006.257.05:11:02.18#ibcon#about to read 5, iclass 34, count 0 2006.257.05:11:02.18#ibcon#read 5, iclass 34, count 0 2006.257.05:11:02.18#ibcon#about to read 6, iclass 34, count 0 2006.257.05:11:02.18#ibcon#read 6, iclass 34, count 0 2006.257.05:11:02.18#ibcon#end of sib2, iclass 34, count 0 2006.257.05:11:02.18#ibcon#*after write, iclass 34, count 0 2006.257.05:11:02.18#ibcon#*before return 0, iclass 34, count 0 2006.257.05:11:02.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:11:02.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:11:02.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:11:02.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:11:02.18$vck44/vblo=7,734.99 2006.257.05:11:02.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.05:11:02.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.05:11:02.18#ibcon#ireg 17 cls_cnt 0 2006.257.05:11:02.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:11:02.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:11:02.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:11:02.18#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:11:02.18#ibcon#first serial, iclass 36, count 0 2006.257.05:11:02.18#ibcon#enter sib2, iclass 36, count 0 2006.257.05:11:02.18#ibcon#flushed, iclass 36, count 0 2006.257.05:11:02.18#ibcon#about to write, iclass 36, count 0 2006.257.05:11:02.18#ibcon#wrote, iclass 36, count 0 2006.257.05:11:02.18#ibcon#about to read 3, iclass 36, count 0 2006.257.05:11:02.20#ibcon#read 3, iclass 36, count 0 2006.257.05:11:02.20#ibcon#about to read 4, iclass 36, count 0 2006.257.05:11:02.20#ibcon#read 4, iclass 36, count 0 2006.257.05:11:02.20#ibcon#about to read 5, iclass 36, count 0 2006.257.05:11:02.20#ibcon#read 5, iclass 36, count 0 2006.257.05:11:02.20#ibcon#about to read 6, iclass 36, count 0 2006.257.05:11:02.20#ibcon#read 6, iclass 36, count 0 2006.257.05:11:02.20#ibcon#end of sib2, iclass 36, count 0 2006.257.05:11:02.20#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:11:02.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:11:02.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:11:02.20#ibcon#*before write, iclass 36, count 0 2006.257.05:11:02.20#ibcon#enter sib2, iclass 36, count 0 2006.257.05:11:02.20#ibcon#flushed, iclass 36, count 0 2006.257.05:11:02.20#ibcon#about to write, iclass 36, count 0 2006.257.05:11:02.20#ibcon#wrote, iclass 36, count 0 2006.257.05:11:02.20#ibcon#about to read 3, iclass 36, count 0 2006.257.05:11:02.24#ibcon#read 3, iclass 36, count 0 2006.257.05:11:02.24#ibcon#about to read 4, iclass 36, count 0 2006.257.05:11:02.24#ibcon#read 4, iclass 36, count 0 2006.257.05:11:02.24#ibcon#about to read 5, iclass 36, count 0 2006.257.05:11:02.24#ibcon#read 5, iclass 36, count 0 2006.257.05:11:02.24#ibcon#about to read 6, iclass 36, count 0 2006.257.05:11:02.24#ibcon#read 6, iclass 36, count 0 2006.257.05:11:02.24#ibcon#end of sib2, iclass 36, count 0 2006.257.05:11:02.24#ibcon#*after write, iclass 36, count 0 2006.257.05:11:02.24#ibcon#*before return 0, iclass 36, count 0 2006.257.05:11:02.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:11:02.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:11:02.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:11:02.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:11:02.24$vck44/vb=7,4 2006.257.05:11:02.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.05:11:02.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.05:11:02.24#ibcon#ireg 11 cls_cnt 2 2006.257.05:11:02.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:11:02.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:11:02.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:11:02.30#ibcon#enter wrdev, iclass 38, count 2 2006.257.05:11:02.30#ibcon#first serial, iclass 38, count 2 2006.257.05:11:02.30#ibcon#enter sib2, iclass 38, count 2 2006.257.05:11:02.30#ibcon#flushed, iclass 38, count 2 2006.257.05:11:02.30#ibcon#about to write, iclass 38, count 2 2006.257.05:11:02.30#ibcon#wrote, iclass 38, count 2 2006.257.05:11:02.30#ibcon#about to read 3, iclass 38, count 2 2006.257.05:11:02.32#ibcon#read 3, iclass 38, count 2 2006.257.05:11:02.32#ibcon#about to read 4, iclass 38, count 2 2006.257.05:11:02.32#ibcon#read 4, iclass 38, count 2 2006.257.05:11:02.32#ibcon#about to read 5, iclass 38, count 2 2006.257.05:11:02.32#ibcon#read 5, iclass 38, count 2 2006.257.05:11:02.32#ibcon#about to read 6, iclass 38, count 2 2006.257.05:11:02.32#ibcon#read 6, iclass 38, count 2 2006.257.05:11:02.32#ibcon#end of sib2, iclass 38, count 2 2006.257.05:11:02.32#ibcon#*mode == 0, iclass 38, count 2 2006.257.05:11:02.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.05:11:02.32#ibcon#[27=AT07-04\r\n] 2006.257.05:11:02.32#ibcon#*before write, iclass 38, count 2 2006.257.05:11:02.32#ibcon#enter sib2, iclass 38, count 2 2006.257.05:11:02.32#ibcon#flushed, iclass 38, count 2 2006.257.05:11:02.32#ibcon#about to write, iclass 38, count 2 2006.257.05:11:02.32#ibcon#wrote, iclass 38, count 2 2006.257.05:11:02.32#ibcon#about to read 3, iclass 38, count 2 2006.257.05:11:02.35#ibcon#read 3, iclass 38, count 2 2006.257.05:11:02.35#ibcon#about to read 4, iclass 38, count 2 2006.257.05:11:02.35#ibcon#read 4, iclass 38, count 2 2006.257.05:11:02.35#ibcon#about to read 5, iclass 38, count 2 2006.257.05:11:02.35#ibcon#read 5, iclass 38, count 2 2006.257.05:11:02.35#ibcon#about to read 6, iclass 38, count 2 2006.257.05:11:02.35#ibcon#read 6, iclass 38, count 2 2006.257.05:11:02.35#ibcon#end of sib2, iclass 38, count 2 2006.257.05:11:02.35#ibcon#*after write, iclass 38, count 2 2006.257.05:11:02.35#ibcon#*before return 0, iclass 38, count 2 2006.257.05:11:02.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:11:02.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:11:02.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.05:11:02.35#ibcon#ireg 7 cls_cnt 0 2006.257.05:11:02.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:11:02.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:11:02.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:11:02.47#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:11:02.47#ibcon#first serial, iclass 38, count 0 2006.257.05:11:02.47#ibcon#enter sib2, iclass 38, count 0 2006.257.05:11:02.47#ibcon#flushed, iclass 38, count 0 2006.257.05:11:02.47#ibcon#about to write, iclass 38, count 0 2006.257.05:11:02.47#ibcon#wrote, iclass 38, count 0 2006.257.05:11:02.47#ibcon#about to read 3, iclass 38, count 0 2006.257.05:11:02.49#ibcon#read 3, iclass 38, count 0 2006.257.05:11:02.49#ibcon#about to read 4, iclass 38, count 0 2006.257.05:11:02.49#ibcon#read 4, iclass 38, count 0 2006.257.05:11:02.49#ibcon#about to read 5, iclass 38, count 0 2006.257.05:11:02.49#ibcon#read 5, iclass 38, count 0 2006.257.05:11:02.49#ibcon#about to read 6, iclass 38, count 0 2006.257.05:11:02.49#ibcon#read 6, iclass 38, count 0 2006.257.05:11:02.49#ibcon#end of sib2, iclass 38, count 0 2006.257.05:11:02.49#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:11:02.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:11:02.49#ibcon#[27=USB\r\n] 2006.257.05:11:02.49#ibcon#*before write, iclass 38, count 0 2006.257.05:11:02.49#ibcon#enter sib2, iclass 38, count 0 2006.257.05:11:02.49#ibcon#flushed, iclass 38, count 0 2006.257.05:11:02.49#ibcon#about to write, iclass 38, count 0 2006.257.05:11:02.49#ibcon#wrote, iclass 38, count 0 2006.257.05:11:02.49#ibcon#about to read 3, iclass 38, count 0 2006.257.05:11:02.52#ibcon#read 3, iclass 38, count 0 2006.257.05:11:02.52#ibcon#about to read 4, iclass 38, count 0 2006.257.05:11:02.52#ibcon#read 4, iclass 38, count 0 2006.257.05:11:02.52#ibcon#about to read 5, iclass 38, count 0 2006.257.05:11:02.52#ibcon#read 5, iclass 38, count 0 2006.257.05:11:02.52#ibcon#about to read 6, iclass 38, count 0 2006.257.05:11:02.52#ibcon#read 6, iclass 38, count 0 2006.257.05:11:02.52#ibcon#end of sib2, iclass 38, count 0 2006.257.05:11:02.52#ibcon#*after write, iclass 38, count 0 2006.257.05:11:02.52#ibcon#*before return 0, iclass 38, count 0 2006.257.05:11:02.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:11:02.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:11:02.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:11:02.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:11:02.52$vck44/vblo=8,744.99 2006.257.05:11:02.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.05:11:02.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.05:11:02.52#ibcon#ireg 17 cls_cnt 0 2006.257.05:11:02.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:11:02.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:11:02.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:11:02.52#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:11:02.52#ibcon#first serial, iclass 40, count 0 2006.257.05:11:02.52#ibcon#enter sib2, iclass 40, count 0 2006.257.05:11:02.52#ibcon#flushed, iclass 40, count 0 2006.257.05:11:02.52#ibcon#about to write, iclass 40, count 0 2006.257.05:11:02.52#ibcon#wrote, iclass 40, count 0 2006.257.05:11:02.52#ibcon#about to read 3, iclass 40, count 0 2006.257.05:11:02.54#ibcon#read 3, iclass 40, count 0 2006.257.05:11:02.54#ibcon#about to read 4, iclass 40, count 0 2006.257.05:11:02.54#ibcon#read 4, iclass 40, count 0 2006.257.05:11:02.54#ibcon#about to read 5, iclass 40, count 0 2006.257.05:11:02.54#ibcon#read 5, iclass 40, count 0 2006.257.05:11:02.54#ibcon#about to read 6, iclass 40, count 0 2006.257.05:11:02.54#ibcon#read 6, iclass 40, count 0 2006.257.05:11:02.54#ibcon#end of sib2, iclass 40, count 0 2006.257.05:11:02.54#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:11:02.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:11:02.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:11:02.54#ibcon#*before write, iclass 40, count 0 2006.257.05:11:02.54#ibcon#enter sib2, iclass 40, count 0 2006.257.05:11:02.54#ibcon#flushed, iclass 40, count 0 2006.257.05:11:02.54#ibcon#about to write, iclass 40, count 0 2006.257.05:11:02.54#ibcon#wrote, iclass 40, count 0 2006.257.05:11:02.54#ibcon#about to read 3, iclass 40, count 0 2006.257.05:11:02.58#ibcon#read 3, iclass 40, count 0 2006.257.05:11:02.58#ibcon#about to read 4, iclass 40, count 0 2006.257.05:11:02.58#ibcon#read 4, iclass 40, count 0 2006.257.05:11:02.58#ibcon#about to read 5, iclass 40, count 0 2006.257.05:11:02.58#ibcon#read 5, iclass 40, count 0 2006.257.05:11:02.58#ibcon#about to read 6, iclass 40, count 0 2006.257.05:11:02.58#ibcon#read 6, iclass 40, count 0 2006.257.05:11:02.58#ibcon#end of sib2, iclass 40, count 0 2006.257.05:11:02.58#ibcon#*after write, iclass 40, count 0 2006.257.05:11:02.58#ibcon#*before return 0, iclass 40, count 0 2006.257.05:11:02.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:11:02.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:11:02.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:11:02.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:11:02.58$vck44/vb=8,4 2006.257.05:11:02.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.05:11:02.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.05:11:02.58#ibcon#ireg 11 cls_cnt 2 2006.257.05:11:02.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:11:02.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:11:02.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:11:02.64#ibcon#enter wrdev, iclass 4, count 2 2006.257.05:11:02.64#ibcon#first serial, iclass 4, count 2 2006.257.05:11:02.64#ibcon#enter sib2, iclass 4, count 2 2006.257.05:11:02.64#ibcon#flushed, iclass 4, count 2 2006.257.05:11:02.64#ibcon#about to write, iclass 4, count 2 2006.257.05:11:02.64#ibcon#wrote, iclass 4, count 2 2006.257.05:11:02.64#ibcon#about to read 3, iclass 4, count 2 2006.257.05:11:02.66#ibcon#read 3, iclass 4, count 2 2006.257.05:11:02.66#ibcon#about to read 4, iclass 4, count 2 2006.257.05:11:02.66#ibcon#read 4, iclass 4, count 2 2006.257.05:11:02.66#ibcon#about to read 5, iclass 4, count 2 2006.257.05:11:02.66#ibcon#read 5, iclass 4, count 2 2006.257.05:11:02.66#ibcon#about to read 6, iclass 4, count 2 2006.257.05:11:02.66#ibcon#read 6, iclass 4, count 2 2006.257.05:11:02.66#ibcon#end of sib2, iclass 4, count 2 2006.257.05:11:02.66#ibcon#*mode == 0, iclass 4, count 2 2006.257.05:11:02.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.05:11:02.66#ibcon#[27=AT08-04\r\n] 2006.257.05:11:02.66#ibcon#*before write, iclass 4, count 2 2006.257.05:11:02.66#ibcon#enter sib2, iclass 4, count 2 2006.257.05:11:02.66#ibcon#flushed, iclass 4, count 2 2006.257.05:11:02.66#ibcon#about to write, iclass 4, count 2 2006.257.05:11:02.66#ibcon#wrote, iclass 4, count 2 2006.257.05:11:02.66#ibcon#about to read 3, iclass 4, count 2 2006.257.05:11:02.69#ibcon#read 3, iclass 4, count 2 2006.257.05:11:02.69#ibcon#about to read 4, iclass 4, count 2 2006.257.05:11:02.69#ibcon#read 4, iclass 4, count 2 2006.257.05:11:02.69#ibcon#about to read 5, iclass 4, count 2 2006.257.05:11:02.69#ibcon#read 5, iclass 4, count 2 2006.257.05:11:02.69#ibcon#about to read 6, iclass 4, count 2 2006.257.05:11:02.69#ibcon#read 6, iclass 4, count 2 2006.257.05:11:02.69#ibcon#end of sib2, iclass 4, count 2 2006.257.05:11:02.69#ibcon#*after write, iclass 4, count 2 2006.257.05:11:02.69#ibcon#*before return 0, iclass 4, count 2 2006.257.05:11:02.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:11:02.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:11:02.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.05:11:02.69#ibcon#ireg 7 cls_cnt 0 2006.257.05:11:02.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:02.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:02.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:02.81#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:11:02.81#ibcon#first serial, iclass 4, count 0 2006.257.05:11:02.81#ibcon#enter sib2, iclass 4, count 0 2006.257.05:11:02.81#ibcon#flushed, iclass 4, count 0 2006.257.05:11:02.81#ibcon#about to write, iclass 4, count 0 2006.257.05:11:02.81#ibcon#wrote, iclass 4, count 0 2006.257.05:11:02.81#ibcon#about to read 3, iclass 4, count 0 2006.257.05:11:02.83#ibcon#read 3, iclass 4, count 0 2006.257.05:11:02.83#ibcon#about to read 4, iclass 4, count 0 2006.257.05:11:02.83#ibcon#read 4, iclass 4, count 0 2006.257.05:11:02.83#ibcon#about to read 5, iclass 4, count 0 2006.257.05:11:02.83#ibcon#read 5, iclass 4, count 0 2006.257.05:11:02.83#ibcon#about to read 6, iclass 4, count 0 2006.257.05:11:02.83#ibcon#read 6, iclass 4, count 0 2006.257.05:11:02.83#ibcon#end of sib2, iclass 4, count 0 2006.257.05:11:02.83#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:11:02.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:11:02.83#ibcon#[27=USB\r\n] 2006.257.05:11:02.83#ibcon#*before write, iclass 4, count 0 2006.257.05:11:02.83#ibcon#enter sib2, iclass 4, count 0 2006.257.05:11:02.83#ibcon#flushed, iclass 4, count 0 2006.257.05:11:02.83#ibcon#about to write, iclass 4, count 0 2006.257.05:11:02.83#ibcon#wrote, iclass 4, count 0 2006.257.05:11:02.83#ibcon#about to read 3, iclass 4, count 0 2006.257.05:11:02.86#ibcon#read 3, iclass 4, count 0 2006.257.05:11:02.86#ibcon#about to read 4, iclass 4, count 0 2006.257.05:11:02.86#ibcon#read 4, iclass 4, count 0 2006.257.05:11:02.86#ibcon#about to read 5, iclass 4, count 0 2006.257.05:11:02.86#ibcon#read 5, iclass 4, count 0 2006.257.05:11:02.86#ibcon#about to read 6, iclass 4, count 0 2006.257.05:11:02.86#ibcon#read 6, iclass 4, count 0 2006.257.05:11:02.86#ibcon#end of sib2, iclass 4, count 0 2006.257.05:11:02.86#ibcon#*after write, iclass 4, count 0 2006.257.05:11:02.86#ibcon#*before return 0, iclass 4, count 0 2006.257.05:11:02.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:02.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:11:02.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:11:02.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:11:02.86$vck44/vabw=wide 2006.257.05:11:02.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.05:11:02.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.05:11:02.86#ibcon#ireg 8 cls_cnt 0 2006.257.05:11:02.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:02.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:02.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:02.86#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:11:02.86#ibcon#first serial, iclass 6, count 0 2006.257.05:11:02.86#ibcon#enter sib2, iclass 6, count 0 2006.257.05:11:02.86#ibcon#flushed, iclass 6, count 0 2006.257.05:11:02.86#ibcon#about to write, iclass 6, count 0 2006.257.05:11:02.86#ibcon#wrote, iclass 6, count 0 2006.257.05:11:02.86#ibcon#about to read 3, iclass 6, count 0 2006.257.05:11:02.88#ibcon#read 3, iclass 6, count 0 2006.257.05:11:02.88#ibcon#about to read 4, iclass 6, count 0 2006.257.05:11:02.88#ibcon#read 4, iclass 6, count 0 2006.257.05:11:02.88#ibcon#about to read 5, iclass 6, count 0 2006.257.05:11:02.88#ibcon#read 5, iclass 6, count 0 2006.257.05:11:02.88#ibcon#about to read 6, iclass 6, count 0 2006.257.05:11:02.88#ibcon#read 6, iclass 6, count 0 2006.257.05:11:02.88#ibcon#end of sib2, iclass 6, count 0 2006.257.05:11:02.88#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:11:02.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:11:02.88#ibcon#[25=BW32\r\n] 2006.257.05:11:02.88#ibcon#*before write, iclass 6, count 0 2006.257.05:11:02.88#ibcon#enter sib2, iclass 6, count 0 2006.257.05:11:02.88#ibcon#flushed, iclass 6, count 0 2006.257.05:11:02.88#ibcon#about to write, iclass 6, count 0 2006.257.05:11:02.88#ibcon#wrote, iclass 6, count 0 2006.257.05:11:02.88#ibcon#about to read 3, iclass 6, count 0 2006.257.05:11:02.91#ibcon#read 3, iclass 6, count 0 2006.257.05:11:02.91#ibcon#about to read 4, iclass 6, count 0 2006.257.05:11:02.91#ibcon#read 4, iclass 6, count 0 2006.257.05:11:02.91#ibcon#about to read 5, iclass 6, count 0 2006.257.05:11:02.91#ibcon#read 5, iclass 6, count 0 2006.257.05:11:02.91#ibcon#about to read 6, iclass 6, count 0 2006.257.05:11:02.91#ibcon#read 6, iclass 6, count 0 2006.257.05:11:02.91#ibcon#end of sib2, iclass 6, count 0 2006.257.05:11:02.91#ibcon#*after write, iclass 6, count 0 2006.257.05:11:02.91#ibcon#*before return 0, iclass 6, count 0 2006.257.05:11:02.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:02.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:11:02.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:11:02.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:11:02.91$vck44/vbbw=wide 2006.257.05:11:02.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.05:11:02.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.05:11:02.91#ibcon#ireg 8 cls_cnt 0 2006.257.05:11:02.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:11:02.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:11:02.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:11:02.98#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:11:02.98#ibcon#first serial, iclass 10, count 0 2006.257.05:11:02.98#ibcon#enter sib2, iclass 10, count 0 2006.257.05:11:02.98#ibcon#flushed, iclass 10, count 0 2006.257.05:11:02.98#ibcon#about to write, iclass 10, count 0 2006.257.05:11:02.98#ibcon#wrote, iclass 10, count 0 2006.257.05:11:02.98#ibcon#about to read 3, iclass 10, count 0 2006.257.05:11:03.00#ibcon#read 3, iclass 10, count 0 2006.257.05:11:03.00#ibcon#about to read 4, iclass 10, count 0 2006.257.05:11:03.00#ibcon#read 4, iclass 10, count 0 2006.257.05:11:03.00#ibcon#about to read 5, iclass 10, count 0 2006.257.05:11:03.00#ibcon#read 5, iclass 10, count 0 2006.257.05:11:03.00#ibcon#about to read 6, iclass 10, count 0 2006.257.05:11:03.00#ibcon#read 6, iclass 10, count 0 2006.257.05:11:03.00#ibcon#end of sib2, iclass 10, count 0 2006.257.05:11:03.00#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:11:03.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:11:03.00#ibcon#[27=BW32\r\n] 2006.257.05:11:03.00#ibcon#*before write, iclass 10, count 0 2006.257.05:11:03.00#ibcon#enter sib2, iclass 10, count 0 2006.257.05:11:03.00#ibcon#flushed, iclass 10, count 0 2006.257.05:11:03.00#ibcon#about to write, iclass 10, count 0 2006.257.05:11:03.00#ibcon#wrote, iclass 10, count 0 2006.257.05:11:03.00#ibcon#about to read 3, iclass 10, count 0 2006.257.05:11:03.03#ibcon#read 3, iclass 10, count 0 2006.257.05:11:03.03#ibcon#about to read 4, iclass 10, count 0 2006.257.05:11:03.03#ibcon#read 4, iclass 10, count 0 2006.257.05:11:03.03#ibcon#about to read 5, iclass 10, count 0 2006.257.05:11:03.03#ibcon#read 5, iclass 10, count 0 2006.257.05:11:03.03#ibcon#about to read 6, iclass 10, count 0 2006.257.05:11:03.03#ibcon#read 6, iclass 10, count 0 2006.257.05:11:03.03#ibcon#end of sib2, iclass 10, count 0 2006.257.05:11:03.03#ibcon#*after write, iclass 10, count 0 2006.257.05:11:03.03#ibcon#*before return 0, iclass 10, count 0 2006.257.05:11:03.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:11:03.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:11:03.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:11:03.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:11:03.03$setupk4/ifdk4 2006.257.05:11:03.03$ifdk4/lo= 2006.257.05:11:03.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:11:03.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:11:03.03$ifdk4/patch= 2006.257.05:11:03.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:11:03.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:11:03.03$setupk4/!*+20s 2006.257.05:11:12.01#abcon#<5=/15 1.7 3.8 19.73 921012.0\r\n> 2006.257.05:11:12.03#abcon#{5=INTERFACE CLEAR} 2006.257.05:11:12.09#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:11:17.53$setupk4/"tpicd 2006.257.05:11:17.53$setupk4/echo=off 2006.257.05:11:17.53$setupk4/xlog=off 2006.257.05:11:17.53:!2006.257.05:13:56 2006.257.05:11:21.14#trakl#Source acquired 2006.257.05:11:22.14#flagr#flagr/antenna,acquired 2006.257.05:13:56.00:preob 2006.257.05:13:56.14/onsource/TRACKING 2006.257.05:13:56.14:!2006.257.05:14:06 2006.257.05:14:06.00:"tape 2006.257.05:14:06.00:"st=record 2006.257.05:14:06.00:data_valid=on 2006.257.05:14:06.00:midob 2006.257.05:14:07.14/onsource/TRACKING 2006.257.05:14:07.14/wx/19.77,1012.1,91 2006.257.05:14:07.32/cable/+6.4813E-03 2006.257.05:14:08.41/va/01,08,usb,yes,33,35 2006.257.05:14:08.41/va/02,07,usb,yes,35,36 2006.257.05:14:08.41/va/03,08,usb,yes,32,34 2006.257.05:14:08.41/va/04,07,usb,yes,36,38 2006.257.05:14:08.41/va/05,04,usb,yes,33,33 2006.257.05:14:08.41/va/06,04,usb,yes,36,36 2006.257.05:14:08.41/va/07,04,usb,yes,37,38 2006.257.05:14:08.41/va/08,04,usb,yes,31,38 2006.257.05:14:08.64/valo/01,524.99,yes,locked 2006.257.05:14:08.64/valo/02,534.99,yes,locked 2006.257.05:14:08.64/valo/03,564.99,yes,locked 2006.257.05:14:08.64/valo/04,624.99,yes,locked 2006.257.05:14:08.64/valo/05,734.99,yes,locked 2006.257.05:14:08.64/valo/06,814.99,yes,locked 2006.257.05:14:08.64/valo/07,864.99,yes,locked 2006.257.05:14:08.64/valo/08,884.99,yes,locked 2006.257.05:14:09.73/vb/01,04,usb,yes,31,29 2006.257.05:14:09.73/vb/02,05,usb,yes,30,29 2006.257.05:14:09.73/vb/03,04,usb,yes,30,34 2006.257.05:14:09.73/vb/04,05,usb,yes,31,30 2006.257.05:14:09.73/vb/05,04,usb,yes,27,30 2006.257.05:14:09.73/vb/06,04,usb,yes,32,28 2006.257.05:14:09.73/vb/07,04,usb,yes,32,31 2006.257.05:14:09.73/vb/08,04,usb,yes,29,32 2006.257.05:14:09.97/vblo/01,629.99,yes,locked 2006.257.05:14:09.97/vblo/02,634.99,yes,locked 2006.257.05:14:09.97/vblo/03,649.99,yes,locked 2006.257.05:14:09.97/vblo/04,679.99,yes,locked 2006.257.05:14:09.97/vblo/05,709.99,yes,locked 2006.257.05:14:09.97/vblo/06,719.99,yes,locked 2006.257.05:14:09.97/vblo/07,734.99,yes,locked 2006.257.05:14:09.97/vblo/08,744.99,yes,locked 2006.257.05:14:10.12/vabw/8 2006.257.05:14:10.27/vbbw/8 2006.257.05:14:10.36/xfe/off,on,16.5 2006.257.05:14:10.73/ifatt/23,28,28,28 2006.257.05:14:11.08/fmout-gps/S +4.52E-07 2006.257.05:14:11.12:!2006.257.05:19:56 2006.257.05:19:56.00:data_valid=off 2006.257.05:19:56.00:"et 2006.257.05:19:56.00:!+3s 2006.257.05:19:59.01:"tape 2006.257.05:19:59.01:postob 2006.257.05:19:59.11/cable/+6.4814E-03 2006.257.05:19:59.11/wx/19.89,1012.2,91 2006.257.05:20:00.08/fmout-gps/S +4.55E-07 2006.257.05:20:00.08:scan_name=257-0525,jd0609,40 2006.257.05:20:00.08:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.05:20:01.14#flagr#flagr/antenna,new-source 2006.257.05:20:01.14:checkk5 2006.257.05:20:01.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:20:01.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:20:02.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:20:02.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:20:03.18/chk_obsdata//k5ts1/T2570514??a.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.257.05:20:03.58/chk_obsdata//k5ts2/T2570514??b.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.257.05:20:04.00/chk_obsdata//k5ts3/T2570514??c.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.257.05:20:04.39/chk_obsdata//k5ts4/T2570514??d.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.257.05:20:05.15/k5log//k5ts1_log_newline 2006.257.05:20:05.87/k5log//k5ts2_log_newline 2006.257.05:20:06.64/k5log//k5ts3_log_newline 2006.257.05:20:07.36/k5log//k5ts4_log_newline 2006.257.05:20:07.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:20:07.38:setupk4=1 2006.257.05:20:07.38$setupk4/echo=on 2006.257.05:20:07.38$setupk4/pcalon 2006.257.05:20:07.38$pcalon/"no phase cal control is implemented here 2006.257.05:20:07.38$setupk4/"tpicd=stop 2006.257.05:20:07.38$setupk4/"rec=synch_on 2006.257.05:20:07.38$setupk4/"rec_mode=128 2006.257.05:20:07.38$setupk4/!* 2006.257.05:20:07.38$setupk4/recpk4 2006.257.05:20:07.38$recpk4/recpatch= 2006.257.05:20:07.39$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:20:07.39$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:20:07.39$setupk4/vck44 2006.257.05:20:07.39$vck44/valo=1,524.99 2006.257.05:20:07.39#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.05:20:07.39#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.05:20:07.39#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:07.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:07.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:07.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:07.39#ibcon#enter wrdev, iclass 11, count 0 2006.257.05:20:07.39#ibcon#first serial, iclass 11, count 0 2006.257.05:20:07.39#ibcon#enter sib2, iclass 11, count 0 2006.257.05:20:07.39#ibcon#flushed, iclass 11, count 0 2006.257.05:20:07.39#ibcon#about to write, iclass 11, count 0 2006.257.05:20:07.39#ibcon#wrote, iclass 11, count 0 2006.257.05:20:07.39#ibcon#about to read 3, iclass 11, count 0 2006.257.05:20:07.41#ibcon#read 3, iclass 11, count 0 2006.257.05:20:07.41#ibcon#about to read 4, iclass 11, count 0 2006.257.05:20:07.41#ibcon#read 4, iclass 11, count 0 2006.257.05:20:07.41#ibcon#about to read 5, iclass 11, count 0 2006.257.05:20:07.41#ibcon#read 5, iclass 11, count 0 2006.257.05:20:07.41#ibcon#about to read 6, iclass 11, count 0 2006.257.05:20:07.41#ibcon#read 6, iclass 11, count 0 2006.257.05:20:07.41#ibcon#end of sib2, iclass 11, count 0 2006.257.05:20:07.41#ibcon#*mode == 0, iclass 11, count 0 2006.257.05:20:07.41#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.05:20:07.41#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:20:07.41#ibcon#*before write, iclass 11, count 0 2006.257.05:20:07.41#ibcon#enter sib2, iclass 11, count 0 2006.257.05:20:07.41#ibcon#flushed, iclass 11, count 0 2006.257.05:20:07.41#ibcon#about to write, iclass 11, count 0 2006.257.05:20:07.41#ibcon#wrote, iclass 11, count 0 2006.257.05:20:07.41#ibcon#about to read 3, iclass 11, count 0 2006.257.05:20:07.46#ibcon#read 3, iclass 11, count 0 2006.257.05:20:07.46#ibcon#about to read 4, iclass 11, count 0 2006.257.05:20:07.46#ibcon#read 4, iclass 11, count 0 2006.257.05:20:07.46#ibcon#about to read 5, iclass 11, count 0 2006.257.05:20:07.46#ibcon#read 5, iclass 11, count 0 2006.257.05:20:07.46#ibcon#about to read 6, iclass 11, count 0 2006.257.05:20:07.46#ibcon#read 6, iclass 11, count 0 2006.257.05:20:07.46#ibcon#end of sib2, iclass 11, count 0 2006.257.05:20:07.46#ibcon#*after write, iclass 11, count 0 2006.257.05:20:07.46#ibcon#*before return 0, iclass 11, count 0 2006.257.05:20:07.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:07.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:07.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.05:20:07.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.05:20:07.46$vck44/va=1,8 2006.257.05:20:07.46#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.05:20:07.46#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.05:20:07.46#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:07.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:07.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:07.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:07.46#ibcon#enter wrdev, iclass 13, count 2 2006.257.05:20:07.46#ibcon#first serial, iclass 13, count 2 2006.257.05:20:07.46#ibcon#enter sib2, iclass 13, count 2 2006.257.05:20:07.46#ibcon#flushed, iclass 13, count 2 2006.257.05:20:07.46#ibcon#about to write, iclass 13, count 2 2006.257.05:20:07.46#ibcon#wrote, iclass 13, count 2 2006.257.05:20:07.46#ibcon#about to read 3, iclass 13, count 2 2006.257.05:20:07.48#ibcon#read 3, iclass 13, count 2 2006.257.05:20:07.48#ibcon#about to read 4, iclass 13, count 2 2006.257.05:20:07.48#ibcon#read 4, iclass 13, count 2 2006.257.05:20:07.48#ibcon#about to read 5, iclass 13, count 2 2006.257.05:20:07.48#ibcon#read 5, iclass 13, count 2 2006.257.05:20:07.48#ibcon#about to read 6, iclass 13, count 2 2006.257.05:20:07.48#ibcon#read 6, iclass 13, count 2 2006.257.05:20:07.48#ibcon#end of sib2, iclass 13, count 2 2006.257.05:20:07.48#ibcon#*mode == 0, iclass 13, count 2 2006.257.05:20:07.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.05:20:07.48#ibcon#[25=AT01-08\r\n] 2006.257.05:20:07.48#ibcon#*before write, iclass 13, count 2 2006.257.05:20:07.48#ibcon#enter sib2, iclass 13, count 2 2006.257.05:20:07.48#ibcon#flushed, iclass 13, count 2 2006.257.05:20:07.48#ibcon#about to write, iclass 13, count 2 2006.257.05:20:07.48#ibcon#wrote, iclass 13, count 2 2006.257.05:20:07.48#ibcon#about to read 3, iclass 13, count 2 2006.257.05:20:07.51#ibcon#read 3, iclass 13, count 2 2006.257.05:20:07.51#ibcon#about to read 4, iclass 13, count 2 2006.257.05:20:07.51#ibcon#read 4, iclass 13, count 2 2006.257.05:20:07.51#ibcon#about to read 5, iclass 13, count 2 2006.257.05:20:07.51#ibcon#read 5, iclass 13, count 2 2006.257.05:20:07.51#ibcon#about to read 6, iclass 13, count 2 2006.257.05:20:07.51#ibcon#read 6, iclass 13, count 2 2006.257.05:20:07.51#ibcon#end of sib2, iclass 13, count 2 2006.257.05:20:07.51#ibcon#*after write, iclass 13, count 2 2006.257.05:20:07.51#ibcon#*before return 0, iclass 13, count 2 2006.257.05:20:07.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:07.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:07.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.05:20:07.51#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:07.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:07.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:07.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:07.63#ibcon#enter wrdev, iclass 13, count 0 2006.257.05:20:07.63#ibcon#first serial, iclass 13, count 0 2006.257.05:20:07.63#ibcon#enter sib2, iclass 13, count 0 2006.257.05:20:07.63#ibcon#flushed, iclass 13, count 0 2006.257.05:20:07.63#ibcon#about to write, iclass 13, count 0 2006.257.05:20:07.63#ibcon#wrote, iclass 13, count 0 2006.257.05:20:07.63#ibcon#about to read 3, iclass 13, count 0 2006.257.05:20:07.65#ibcon#read 3, iclass 13, count 0 2006.257.05:20:07.65#ibcon#about to read 4, iclass 13, count 0 2006.257.05:20:07.65#ibcon#read 4, iclass 13, count 0 2006.257.05:20:07.65#ibcon#about to read 5, iclass 13, count 0 2006.257.05:20:07.65#ibcon#read 5, iclass 13, count 0 2006.257.05:20:07.65#ibcon#about to read 6, iclass 13, count 0 2006.257.05:20:07.65#ibcon#read 6, iclass 13, count 0 2006.257.05:20:07.65#ibcon#end of sib2, iclass 13, count 0 2006.257.05:20:07.65#ibcon#*mode == 0, iclass 13, count 0 2006.257.05:20:07.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.05:20:07.65#ibcon#[25=USB\r\n] 2006.257.05:20:07.65#ibcon#*before write, iclass 13, count 0 2006.257.05:20:07.65#ibcon#enter sib2, iclass 13, count 0 2006.257.05:20:07.65#ibcon#flushed, iclass 13, count 0 2006.257.05:20:07.65#ibcon#about to write, iclass 13, count 0 2006.257.05:20:07.65#ibcon#wrote, iclass 13, count 0 2006.257.05:20:07.65#ibcon#about to read 3, iclass 13, count 0 2006.257.05:20:07.68#ibcon#read 3, iclass 13, count 0 2006.257.05:20:07.68#ibcon#about to read 4, iclass 13, count 0 2006.257.05:20:07.68#ibcon#read 4, iclass 13, count 0 2006.257.05:20:07.68#ibcon#about to read 5, iclass 13, count 0 2006.257.05:20:07.68#ibcon#read 5, iclass 13, count 0 2006.257.05:20:07.68#ibcon#about to read 6, iclass 13, count 0 2006.257.05:20:07.68#ibcon#read 6, iclass 13, count 0 2006.257.05:20:07.68#ibcon#end of sib2, iclass 13, count 0 2006.257.05:20:07.68#ibcon#*after write, iclass 13, count 0 2006.257.05:20:07.68#ibcon#*before return 0, iclass 13, count 0 2006.257.05:20:07.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:07.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:07.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.05:20:07.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.05:20:07.68$vck44/valo=2,534.99 2006.257.05:20:07.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.05:20:07.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.05:20:07.68#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:07.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:07.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:07.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:07.68#ibcon#enter wrdev, iclass 15, count 0 2006.257.05:20:07.68#ibcon#first serial, iclass 15, count 0 2006.257.05:20:07.68#ibcon#enter sib2, iclass 15, count 0 2006.257.05:20:07.68#ibcon#flushed, iclass 15, count 0 2006.257.05:20:07.68#ibcon#about to write, iclass 15, count 0 2006.257.05:20:07.68#ibcon#wrote, iclass 15, count 0 2006.257.05:20:07.68#ibcon#about to read 3, iclass 15, count 0 2006.257.05:20:07.70#ibcon#read 3, iclass 15, count 0 2006.257.05:20:07.70#ibcon#about to read 4, iclass 15, count 0 2006.257.05:20:07.70#ibcon#read 4, iclass 15, count 0 2006.257.05:20:07.70#ibcon#about to read 5, iclass 15, count 0 2006.257.05:20:07.70#ibcon#read 5, iclass 15, count 0 2006.257.05:20:07.70#ibcon#about to read 6, iclass 15, count 0 2006.257.05:20:07.70#ibcon#read 6, iclass 15, count 0 2006.257.05:20:07.70#ibcon#end of sib2, iclass 15, count 0 2006.257.05:20:07.70#ibcon#*mode == 0, iclass 15, count 0 2006.257.05:20:07.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.05:20:07.70#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:20:07.70#ibcon#*before write, iclass 15, count 0 2006.257.05:20:07.70#ibcon#enter sib2, iclass 15, count 0 2006.257.05:20:07.70#ibcon#flushed, iclass 15, count 0 2006.257.05:20:07.70#ibcon#about to write, iclass 15, count 0 2006.257.05:20:07.70#ibcon#wrote, iclass 15, count 0 2006.257.05:20:07.70#ibcon#about to read 3, iclass 15, count 0 2006.257.05:20:07.74#ibcon#read 3, iclass 15, count 0 2006.257.05:20:07.74#ibcon#about to read 4, iclass 15, count 0 2006.257.05:20:07.74#ibcon#read 4, iclass 15, count 0 2006.257.05:20:07.74#ibcon#about to read 5, iclass 15, count 0 2006.257.05:20:07.74#ibcon#read 5, iclass 15, count 0 2006.257.05:20:07.74#ibcon#about to read 6, iclass 15, count 0 2006.257.05:20:07.74#ibcon#read 6, iclass 15, count 0 2006.257.05:20:07.74#ibcon#end of sib2, iclass 15, count 0 2006.257.05:20:07.74#ibcon#*after write, iclass 15, count 0 2006.257.05:20:07.74#ibcon#*before return 0, iclass 15, count 0 2006.257.05:20:07.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:07.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:07.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.05:20:07.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.05:20:07.74$vck44/va=2,7 2006.257.05:20:07.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.05:20:07.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.05:20:07.74#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:07.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:07.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:07.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:07.80#ibcon#enter wrdev, iclass 17, count 2 2006.257.05:20:07.80#ibcon#first serial, iclass 17, count 2 2006.257.05:20:07.80#ibcon#enter sib2, iclass 17, count 2 2006.257.05:20:07.80#ibcon#flushed, iclass 17, count 2 2006.257.05:20:07.80#ibcon#about to write, iclass 17, count 2 2006.257.05:20:07.80#ibcon#wrote, iclass 17, count 2 2006.257.05:20:07.80#ibcon#about to read 3, iclass 17, count 2 2006.257.05:20:07.82#ibcon#read 3, iclass 17, count 2 2006.257.05:20:07.82#ibcon#about to read 4, iclass 17, count 2 2006.257.05:20:07.82#ibcon#read 4, iclass 17, count 2 2006.257.05:20:07.82#ibcon#about to read 5, iclass 17, count 2 2006.257.05:20:07.82#ibcon#read 5, iclass 17, count 2 2006.257.05:20:07.82#ibcon#about to read 6, iclass 17, count 2 2006.257.05:20:07.82#ibcon#read 6, iclass 17, count 2 2006.257.05:20:07.82#ibcon#end of sib2, iclass 17, count 2 2006.257.05:20:07.82#ibcon#*mode == 0, iclass 17, count 2 2006.257.05:20:07.82#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.05:20:07.82#ibcon#[25=AT02-07\r\n] 2006.257.05:20:07.82#ibcon#*before write, iclass 17, count 2 2006.257.05:20:07.82#ibcon#enter sib2, iclass 17, count 2 2006.257.05:20:07.82#ibcon#flushed, iclass 17, count 2 2006.257.05:20:07.82#ibcon#about to write, iclass 17, count 2 2006.257.05:20:07.82#ibcon#wrote, iclass 17, count 2 2006.257.05:20:07.82#ibcon#about to read 3, iclass 17, count 2 2006.257.05:20:07.85#ibcon#read 3, iclass 17, count 2 2006.257.05:20:07.85#ibcon#about to read 4, iclass 17, count 2 2006.257.05:20:07.85#ibcon#read 4, iclass 17, count 2 2006.257.05:20:07.85#ibcon#about to read 5, iclass 17, count 2 2006.257.05:20:07.85#ibcon#read 5, iclass 17, count 2 2006.257.05:20:07.85#ibcon#about to read 6, iclass 17, count 2 2006.257.05:20:07.85#ibcon#read 6, iclass 17, count 2 2006.257.05:20:07.85#ibcon#end of sib2, iclass 17, count 2 2006.257.05:20:07.85#ibcon#*after write, iclass 17, count 2 2006.257.05:20:07.85#ibcon#*before return 0, iclass 17, count 2 2006.257.05:20:07.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:07.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:07.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.05:20:07.85#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:07.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:07.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:07.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:07.97#ibcon#enter wrdev, iclass 17, count 0 2006.257.05:20:07.97#ibcon#first serial, iclass 17, count 0 2006.257.05:20:07.97#ibcon#enter sib2, iclass 17, count 0 2006.257.05:20:07.97#ibcon#flushed, iclass 17, count 0 2006.257.05:20:07.97#ibcon#about to write, iclass 17, count 0 2006.257.05:20:07.97#ibcon#wrote, iclass 17, count 0 2006.257.05:20:07.97#ibcon#about to read 3, iclass 17, count 0 2006.257.05:20:07.99#ibcon#read 3, iclass 17, count 0 2006.257.05:20:07.99#ibcon#about to read 4, iclass 17, count 0 2006.257.05:20:07.99#ibcon#read 4, iclass 17, count 0 2006.257.05:20:07.99#ibcon#about to read 5, iclass 17, count 0 2006.257.05:20:07.99#ibcon#read 5, iclass 17, count 0 2006.257.05:20:07.99#ibcon#about to read 6, iclass 17, count 0 2006.257.05:20:07.99#ibcon#read 6, iclass 17, count 0 2006.257.05:20:07.99#ibcon#end of sib2, iclass 17, count 0 2006.257.05:20:07.99#ibcon#*mode == 0, iclass 17, count 0 2006.257.05:20:07.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.05:20:07.99#ibcon#[25=USB\r\n] 2006.257.05:20:07.99#ibcon#*before write, iclass 17, count 0 2006.257.05:20:07.99#ibcon#enter sib2, iclass 17, count 0 2006.257.05:20:07.99#ibcon#flushed, iclass 17, count 0 2006.257.05:20:07.99#ibcon#about to write, iclass 17, count 0 2006.257.05:20:07.99#ibcon#wrote, iclass 17, count 0 2006.257.05:20:07.99#ibcon#about to read 3, iclass 17, count 0 2006.257.05:20:08.02#ibcon#read 3, iclass 17, count 0 2006.257.05:20:08.02#ibcon#about to read 4, iclass 17, count 0 2006.257.05:20:08.02#ibcon#read 4, iclass 17, count 0 2006.257.05:20:08.02#ibcon#about to read 5, iclass 17, count 0 2006.257.05:20:08.02#ibcon#read 5, iclass 17, count 0 2006.257.05:20:08.02#ibcon#about to read 6, iclass 17, count 0 2006.257.05:20:08.02#ibcon#read 6, iclass 17, count 0 2006.257.05:20:08.02#ibcon#end of sib2, iclass 17, count 0 2006.257.05:20:08.02#ibcon#*after write, iclass 17, count 0 2006.257.05:20:08.02#ibcon#*before return 0, iclass 17, count 0 2006.257.05:20:08.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:08.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:08.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.05:20:08.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.05:20:08.02$vck44/valo=3,564.99 2006.257.05:20:08.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.05:20:08.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.05:20:08.02#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:08.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:08.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:08.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:08.02#ibcon#enter wrdev, iclass 19, count 0 2006.257.05:20:08.02#ibcon#first serial, iclass 19, count 0 2006.257.05:20:08.02#ibcon#enter sib2, iclass 19, count 0 2006.257.05:20:08.02#ibcon#flushed, iclass 19, count 0 2006.257.05:20:08.02#ibcon#about to write, iclass 19, count 0 2006.257.05:20:08.02#ibcon#wrote, iclass 19, count 0 2006.257.05:20:08.02#ibcon#about to read 3, iclass 19, count 0 2006.257.05:20:08.04#ibcon#read 3, iclass 19, count 0 2006.257.05:20:08.04#ibcon#about to read 4, iclass 19, count 0 2006.257.05:20:08.04#ibcon#read 4, iclass 19, count 0 2006.257.05:20:08.04#ibcon#about to read 5, iclass 19, count 0 2006.257.05:20:08.04#ibcon#read 5, iclass 19, count 0 2006.257.05:20:08.04#ibcon#about to read 6, iclass 19, count 0 2006.257.05:20:08.04#ibcon#read 6, iclass 19, count 0 2006.257.05:20:08.04#ibcon#end of sib2, iclass 19, count 0 2006.257.05:20:08.04#ibcon#*mode == 0, iclass 19, count 0 2006.257.05:20:08.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.05:20:08.04#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:20:08.04#ibcon#*before write, iclass 19, count 0 2006.257.05:20:08.04#ibcon#enter sib2, iclass 19, count 0 2006.257.05:20:08.04#ibcon#flushed, iclass 19, count 0 2006.257.05:20:08.04#ibcon#about to write, iclass 19, count 0 2006.257.05:20:08.04#ibcon#wrote, iclass 19, count 0 2006.257.05:20:08.04#ibcon#about to read 3, iclass 19, count 0 2006.257.05:20:08.08#ibcon#read 3, iclass 19, count 0 2006.257.05:20:08.08#ibcon#about to read 4, iclass 19, count 0 2006.257.05:20:08.08#ibcon#read 4, iclass 19, count 0 2006.257.05:20:08.08#ibcon#about to read 5, iclass 19, count 0 2006.257.05:20:08.08#ibcon#read 5, iclass 19, count 0 2006.257.05:20:08.08#ibcon#about to read 6, iclass 19, count 0 2006.257.05:20:08.08#ibcon#read 6, iclass 19, count 0 2006.257.05:20:08.08#ibcon#end of sib2, iclass 19, count 0 2006.257.05:20:08.08#ibcon#*after write, iclass 19, count 0 2006.257.05:20:08.08#ibcon#*before return 0, iclass 19, count 0 2006.257.05:20:08.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:08.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:08.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.05:20:08.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.05:20:08.08$vck44/va=3,8 2006.257.05:20:08.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.05:20:08.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.05:20:08.08#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:08.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:20:08.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:20:08.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:20:08.14#ibcon#enter wrdev, iclass 21, count 2 2006.257.05:20:08.14#ibcon#first serial, iclass 21, count 2 2006.257.05:20:08.14#ibcon#enter sib2, iclass 21, count 2 2006.257.05:20:08.14#ibcon#flushed, iclass 21, count 2 2006.257.05:20:08.14#ibcon#about to write, iclass 21, count 2 2006.257.05:20:08.14#ibcon#wrote, iclass 21, count 2 2006.257.05:20:08.14#ibcon#about to read 3, iclass 21, count 2 2006.257.05:20:08.16#ibcon#read 3, iclass 21, count 2 2006.257.05:20:08.16#ibcon#about to read 4, iclass 21, count 2 2006.257.05:20:08.16#ibcon#read 4, iclass 21, count 2 2006.257.05:20:08.16#ibcon#about to read 5, iclass 21, count 2 2006.257.05:20:08.16#ibcon#read 5, iclass 21, count 2 2006.257.05:20:08.16#ibcon#about to read 6, iclass 21, count 2 2006.257.05:20:08.16#ibcon#read 6, iclass 21, count 2 2006.257.05:20:08.16#ibcon#end of sib2, iclass 21, count 2 2006.257.05:20:08.16#ibcon#*mode == 0, iclass 21, count 2 2006.257.05:20:08.16#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.05:20:08.16#ibcon#[25=AT03-08\r\n] 2006.257.05:20:08.16#ibcon#*before write, iclass 21, count 2 2006.257.05:20:08.16#ibcon#enter sib2, iclass 21, count 2 2006.257.05:20:08.16#ibcon#flushed, iclass 21, count 2 2006.257.05:20:08.16#ibcon#about to write, iclass 21, count 2 2006.257.05:20:08.16#ibcon#wrote, iclass 21, count 2 2006.257.05:20:08.16#ibcon#about to read 3, iclass 21, count 2 2006.257.05:20:08.19#ibcon#read 3, iclass 21, count 2 2006.257.05:20:08.19#ibcon#about to read 4, iclass 21, count 2 2006.257.05:20:08.19#ibcon#read 4, iclass 21, count 2 2006.257.05:20:08.19#ibcon#about to read 5, iclass 21, count 2 2006.257.05:20:08.19#ibcon#read 5, iclass 21, count 2 2006.257.05:20:08.19#ibcon#about to read 6, iclass 21, count 2 2006.257.05:20:08.19#ibcon#read 6, iclass 21, count 2 2006.257.05:20:08.19#ibcon#end of sib2, iclass 21, count 2 2006.257.05:20:08.19#ibcon#*after write, iclass 21, count 2 2006.257.05:20:08.19#ibcon#*before return 0, iclass 21, count 2 2006.257.05:20:08.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:20:08.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:20:08.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.05:20:08.19#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:08.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:20:08.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:20:08.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:20:08.31#ibcon#enter wrdev, iclass 21, count 0 2006.257.05:20:08.31#ibcon#first serial, iclass 21, count 0 2006.257.05:20:08.31#ibcon#enter sib2, iclass 21, count 0 2006.257.05:20:08.31#ibcon#flushed, iclass 21, count 0 2006.257.05:20:08.31#ibcon#about to write, iclass 21, count 0 2006.257.05:20:08.31#ibcon#wrote, iclass 21, count 0 2006.257.05:20:08.31#ibcon#about to read 3, iclass 21, count 0 2006.257.05:20:08.33#ibcon#read 3, iclass 21, count 0 2006.257.05:20:08.33#ibcon#about to read 4, iclass 21, count 0 2006.257.05:20:08.33#ibcon#read 4, iclass 21, count 0 2006.257.05:20:08.33#ibcon#about to read 5, iclass 21, count 0 2006.257.05:20:08.33#ibcon#read 5, iclass 21, count 0 2006.257.05:20:08.33#ibcon#about to read 6, iclass 21, count 0 2006.257.05:20:08.33#ibcon#read 6, iclass 21, count 0 2006.257.05:20:08.33#ibcon#end of sib2, iclass 21, count 0 2006.257.05:20:08.33#ibcon#*mode == 0, iclass 21, count 0 2006.257.05:20:08.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.05:20:08.33#ibcon#[25=USB\r\n] 2006.257.05:20:08.33#ibcon#*before write, iclass 21, count 0 2006.257.05:20:08.33#ibcon#enter sib2, iclass 21, count 0 2006.257.05:20:08.33#ibcon#flushed, iclass 21, count 0 2006.257.05:20:08.33#ibcon#about to write, iclass 21, count 0 2006.257.05:20:08.33#ibcon#wrote, iclass 21, count 0 2006.257.05:20:08.33#ibcon#about to read 3, iclass 21, count 0 2006.257.05:20:08.36#ibcon#read 3, iclass 21, count 0 2006.257.05:20:08.36#ibcon#about to read 4, iclass 21, count 0 2006.257.05:20:08.36#ibcon#read 4, iclass 21, count 0 2006.257.05:20:08.36#ibcon#about to read 5, iclass 21, count 0 2006.257.05:20:08.36#ibcon#read 5, iclass 21, count 0 2006.257.05:20:08.36#ibcon#about to read 6, iclass 21, count 0 2006.257.05:20:08.36#ibcon#read 6, iclass 21, count 0 2006.257.05:20:08.36#ibcon#end of sib2, iclass 21, count 0 2006.257.05:20:08.36#ibcon#*after write, iclass 21, count 0 2006.257.05:20:08.36#ibcon#*before return 0, iclass 21, count 0 2006.257.05:20:08.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:20:08.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:20:08.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.05:20:08.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.05:20:08.36$vck44/valo=4,624.99 2006.257.05:20:08.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.05:20:08.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.05:20:08.36#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:08.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:20:08.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:20:08.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:20:08.36#ibcon#enter wrdev, iclass 23, count 0 2006.257.05:20:08.36#ibcon#first serial, iclass 23, count 0 2006.257.05:20:08.36#ibcon#enter sib2, iclass 23, count 0 2006.257.05:20:08.36#ibcon#flushed, iclass 23, count 0 2006.257.05:20:08.36#ibcon#about to write, iclass 23, count 0 2006.257.05:20:08.36#ibcon#wrote, iclass 23, count 0 2006.257.05:20:08.36#ibcon#about to read 3, iclass 23, count 0 2006.257.05:20:08.38#ibcon#read 3, iclass 23, count 0 2006.257.05:20:08.38#ibcon#about to read 4, iclass 23, count 0 2006.257.05:20:08.38#ibcon#read 4, iclass 23, count 0 2006.257.05:20:08.38#ibcon#about to read 5, iclass 23, count 0 2006.257.05:20:08.38#ibcon#read 5, iclass 23, count 0 2006.257.05:20:08.38#ibcon#about to read 6, iclass 23, count 0 2006.257.05:20:08.38#ibcon#read 6, iclass 23, count 0 2006.257.05:20:08.38#ibcon#end of sib2, iclass 23, count 0 2006.257.05:20:08.38#ibcon#*mode == 0, iclass 23, count 0 2006.257.05:20:08.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.05:20:08.38#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:20:08.38#ibcon#*before write, iclass 23, count 0 2006.257.05:20:08.38#ibcon#enter sib2, iclass 23, count 0 2006.257.05:20:08.38#ibcon#flushed, iclass 23, count 0 2006.257.05:20:08.38#ibcon#about to write, iclass 23, count 0 2006.257.05:20:08.38#ibcon#wrote, iclass 23, count 0 2006.257.05:20:08.38#ibcon#about to read 3, iclass 23, count 0 2006.257.05:20:08.42#ibcon#read 3, iclass 23, count 0 2006.257.05:20:08.42#ibcon#about to read 4, iclass 23, count 0 2006.257.05:20:08.42#ibcon#read 4, iclass 23, count 0 2006.257.05:20:08.42#ibcon#about to read 5, iclass 23, count 0 2006.257.05:20:08.42#ibcon#read 5, iclass 23, count 0 2006.257.05:20:08.42#ibcon#about to read 6, iclass 23, count 0 2006.257.05:20:08.42#ibcon#read 6, iclass 23, count 0 2006.257.05:20:08.42#ibcon#end of sib2, iclass 23, count 0 2006.257.05:20:08.42#ibcon#*after write, iclass 23, count 0 2006.257.05:20:08.42#ibcon#*before return 0, iclass 23, count 0 2006.257.05:20:08.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:20:08.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:20:08.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.05:20:08.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.05:20:08.42$vck44/va=4,7 2006.257.05:20:08.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.05:20:08.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.05:20:08.42#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:08.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:20:08.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:20:08.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:20:08.48#ibcon#enter wrdev, iclass 25, count 2 2006.257.05:20:08.48#ibcon#first serial, iclass 25, count 2 2006.257.05:20:08.48#ibcon#enter sib2, iclass 25, count 2 2006.257.05:20:08.48#ibcon#flushed, iclass 25, count 2 2006.257.05:20:08.48#ibcon#about to write, iclass 25, count 2 2006.257.05:20:08.48#ibcon#wrote, iclass 25, count 2 2006.257.05:20:08.48#ibcon#about to read 3, iclass 25, count 2 2006.257.05:20:08.50#ibcon#read 3, iclass 25, count 2 2006.257.05:20:08.50#ibcon#about to read 4, iclass 25, count 2 2006.257.05:20:08.50#ibcon#read 4, iclass 25, count 2 2006.257.05:20:08.50#ibcon#about to read 5, iclass 25, count 2 2006.257.05:20:08.50#ibcon#read 5, iclass 25, count 2 2006.257.05:20:08.50#ibcon#about to read 6, iclass 25, count 2 2006.257.05:20:08.50#ibcon#read 6, iclass 25, count 2 2006.257.05:20:08.50#ibcon#end of sib2, iclass 25, count 2 2006.257.05:20:08.50#ibcon#*mode == 0, iclass 25, count 2 2006.257.05:20:08.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.05:20:08.50#ibcon#[25=AT04-07\r\n] 2006.257.05:20:08.50#ibcon#*before write, iclass 25, count 2 2006.257.05:20:08.50#ibcon#enter sib2, iclass 25, count 2 2006.257.05:20:08.50#ibcon#flushed, iclass 25, count 2 2006.257.05:20:08.50#ibcon#about to write, iclass 25, count 2 2006.257.05:20:08.50#ibcon#wrote, iclass 25, count 2 2006.257.05:20:08.50#ibcon#about to read 3, iclass 25, count 2 2006.257.05:20:08.53#ibcon#read 3, iclass 25, count 2 2006.257.05:20:08.53#ibcon#about to read 4, iclass 25, count 2 2006.257.05:20:08.53#ibcon#read 4, iclass 25, count 2 2006.257.05:20:08.53#ibcon#about to read 5, iclass 25, count 2 2006.257.05:20:08.53#ibcon#read 5, iclass 25, count 2 2006.257.05:20:08.53#ibcon#about to read 6, iclass 25, count 2 2006.257.05:20:08.53#ibcon#read 6, iclass 25, count 2 2006.257.05:20:08.53#ibcon#end of sib2, iclass 25, count 2 2006.257.05:20:08.53#ibcon#*after write, iclass 25, count 2 2006.257.05:20:08.53#ibcon#*before return 0, iclass 25, count 2 2006.257.05:20:08.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:20:08.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:20:08.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.05:20:08.53#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:08.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:20:08.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:20:08.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:20:08.65#ibcon#enter wrdev, iclass 25, count 0 2006.257.05:20:08.65#ibcon#first serial, iclass 25, count 0 2006.257.05:20:08.65#ibcon#enter sib2, iclass 25, count 0 2006.257.05:20:08.65#ibcon#flushed, iclass 25, count 0 2006.257.05:20:08.65#ibcon#about to write, iclass 25, count 0 2006.257.05:20:08.65#ibcon#wrote, iclass 25, count 0 2006.257.05:20:08.65#ibcon#about to read 3, iclass 25, count 0 2006.257.05:20:08.67#ibcon#read 3, iclass 25, count 0 2006.257.05:20:08.67#ibcon#about to read 4, iclass 25, count 0 2006.257.05:20:08.67#ibcon#read 4, iclass 25, count 0 2006.257.05:20:08.67#ibcon#about to read 5, iclass 25, count 0 2006.257.05:20:08.67#ibcon#read 5, iclass 25, count 0 2006.257.05:20:08.67#ibcon#about to read 6, iclass 25, count 0 2006.257.05:20:08.67#ibcon#read 6, iclass 25, count 0 2006.257.05:20:08.67#ibcon#end of sib2, iclass 25, count 0 2006.257.05:20:08.67#ibcon#*mode == 0, iclass 25, count 0 2006.257.05:20:08.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.05:20:08.67#ibcon#[25=USB\r\n] 2006.257.05:20:08.67#ibcon#*before write, iclass 25, count 0 2006.257.05:20:08.67#ibcon#enter sib2, iclass 25, count 0 2006.257.05:20:08.67#ibcon#flushed, iclass 25, count 0 2006.257.05:20:08.67#ibcon#about to write, iclass 25, count 0 2006.257.05:20:08.67#ibcon#wrote, iclass 25, count 0 2006.257.05:20:08.67#ibcon#about to read 3, iclass 25, count 0 2006.257.05:20:08.70#ibcon#read 3, iclass 25, count 0 2006.257.05:20:08.70#ibcon#about to read 4, iclass 25, count 0 2006.257.05:20:08.70#ibcon#read 4, iclass 25, count 0 2006.257.05:20:08.70#ibcon#about to read 5, iclass 25, count 0 2006.257.05:20:08.70#ibcon#read 5, iclass 25, count 0 2006.257.05:20:08.70#ibcon#about to read 6, iclass 25, count 0 2006.257.05:20:08.70#ibcon#read 6, iclass 25, count 0 2006.257.05:20:08.70#ibcon#end of sib2, iclass 25, count 0 2006.257.05:20:08.70#ibcon#*after write, iclass 25, count 0 2006.257.05:20:08.70#ibcon#*before return 0, iclass 25, count 0 2006.257.05:20:08.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:20:08.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:20:08.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.05:20:08.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.05:20:08.70$vck44/valo=5,734.99 2006.257.05:20:08.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.05:20:08.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.05:20:08.70#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:08.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:08.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:08.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:08.70#ibcon#enter wrdev, iclass 27, count 0 2006.257.05:20:08.70#ibcon#first serial, iclass 27, count 0 2006.257.05:20:08.70#ibcon#enter sib2, iclass 27, count 0 2006.257.05:20:08.70#ibcon#flushed, iclass 27, count 0 2006.257.05:20:08.70#ibcon#about to write, iclass 27, count 0 2006.257.05:20:08.70#ibcon#wrote, iclass 27, count 0 2006.257.05:20:08.70#ibcon#about to read 3, iclass 27, count 0 2006.257.05:20:08.72#ibcon#read 3, iclass 27, count 0 2006.257.05:20:08.72#ibcon#about to read 4, iclass 27, count 0 2006.257.05:20:08.72#ibcon#read 4, iclass 27, count 0 2006.257.05:20:08.72#ibcon#about to read 5, iclass 27, count 0 2006.257.05:20:08.72#ibcon#read 5, iclass 27, count 0 2006.257.05:20:08.72#ibcon#about to read 6, iclass 27, count 0 2006.257.05:20:08.72#ibcon#read 6, iclass 27, count 0 2006.257.05:20:08.72#ibcon#end of sib2, iclass 27, count 0 2006.257.05:20:08.72#ibcon#*mode == 0, iclass 27, count 0 2006.257.05:20:08.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.05:20:08.72#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:20:08.72#ibcon#*before write, iclass 27, count 0 2006.257.05:20:08.72#ibcon#enter sib2, iclass 27, count 0 2006.257.05:20:08.72#ibcon#flushed, iclass 27, count 0 2006.257.05:20:08.72#ibcon#about to write, iclass 27, count 0 2006.257.05:20:08.72#ibcon#wrote, iclass 27, count 0 2006.257.05:20:08.72#ibcon#about to read 3, iclass 27, count 0 2006.257.05:20:08.76#ibcon#read 3, iclass 27, count 0 2006.257.05:20:08.76#ibcon#about to read 4, iclass 27, count 0 2006.257.05:20:08.76#ibcon#read 4, iclass 27, count 0 2006.257.05:20:08.76#ibcon#about to read 5, iclass 27, count 0 2006.257.05:20:08.76#ibcon#read 5, iclass 27, count 0 2006.257.05:20:08.76#ibcon#about to read 6, iclass 27, count 0 2006.257.05:20:08.76#ibcon#read 6, iclass 27, count 0 2006.257.05:20:08.76#ibcon#end of sib2, iclass 27, count 0 2006.257.05:20:08.76#ibcon#*after write, iclass 27, count 0 2006.257.05:20:08.76#ibcon#*before return 0, iclass 27, count 0 2006.257.05:20:08.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:08.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:08.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.05:20:08.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.05:20:08.76$vck44/va=5,4 2006.257.05:20:08.76#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.05:20:08.76#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.05:20:08.76#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:08.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:08.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:08.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:08.82#ibcon#enter wrdev, iclass 29, count 2 2006.257.05:20:08.82#ibcon#first serial, iclass 29, count 2 2006.257.05:20:08.82#ibcon#enter sib2, iclass 29, count 2 2006.257.05:20:08.82#ibcon#flushed, iclass 29, count 2 2006.257.05:20:08.82#ibcon#about to write, iclass 29, count 2 2006.257.05:20:08.82#ibcon#wrote, iclass 29, count 2 2006.257.05:20:08.82#ibcon#about to read 3, iclass 29, count 2 2006.257.05:20:08.84#ibcon#read 3, iclass 29, count 2 2006.257.05:20:08.84#ibcon#about to read 4, iclass 29, count 2 2006.257.05:20:08.84#ibcon#read 4, iclass 29, count 2 2006.257.05:20:08.84#ibcon#about to read 5, iclass 29, count 2 2006.257.05:20:08.84#ibcon#read 5, iclass 29, count 2 2006.257.05:20:08.84#ibcon#about to read 6, iclass 29, count 2 2006.257.05:20:08.84#ibcon#read 6, iclass 29, count 2 2006.257.05:20:08.84#ibcon#end of sib2, iclass 29, count 2 2006.257.05:20:08.84#ibcon#*mode == 0, iclass 29, count 2 2006.257.05:20:08.84#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.05:20:08.84#ibcon#[25=AT05-04\r\n] 2006.257.05:20:08.84#ibcon#*before write, iclass 29, count 2 2006.257.05:20:08.84#ibcon#enter sib2, iclass 29, count 2 2006.257.05:20:08.84#ibcon#flushed, iclass 29, count 2 2006.257.05:20:08.84#ibcon#about to write, iclass 29, count 2 2006.257.05:20:08.84#ibcon#wrote, iclass 29, count 2 2006.257.05:20:08.84#ibcon#about to read 3, iclass 29, count 2 2006.257.05:20:08.87#ibcon#read 3, iclass 29, count 2 2006.257.05:20:08.87#ibcon#about to read 4, iclass 29, count 2 2006.257.05:20:08.87#ibcon#read 4, iclass 29, count 2 2006.257.05:20:08.87#ibcon#about to read 5, iclass 29, count 2 2006.257.05:20:08.87#ibcon#read 5, iclass 29, count 2 2006.257.05:20:08.87#ibcon#about to read 6, iclass 29, count 2 2006.257.05:20:08.87#ibcon#read 6, iclass 29, count 2 2006.257.05:20:08.87#ibcon#end of sib2, iclass 29, count 2 2006.257.05:20:08.87#ibcon#*after write, iclass 29, count 2 2006.257.05:20:08.87#ibcon#*before return 0, iclass 29, count 2 2006.257.05:20:08.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:08.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:08.87#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.05:20:08.87#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:08.87#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:08.99#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:08.99#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:08.99#ibcon#enter wrdev, iclass 29, count 0 2006.257.05:20:08.99#ibcon#first serial, iclass 29, count 0 2006.257.05:20:08.99#ibcon#enter sib2, iclass 29, count 0 2006.257.05:20:08.99#ibcon#flushed, iclass 29, count 0 2006.257.05:20:08.99#ibcon#about to write, iclass 29, count 0 2006.257.05:20:08.99#ibcon#wrote, iclass 29, count 0 2006.257.05:20:08.99#ibcon#about to read 3, iclass 29, count 0 2006.257.05:20:09.01#ibcon#read 3, iclass 29, count 0 2006.257.05:20:09.01#ibcon#about to read 4, iclass 29, count 0 2006.257.05:20:09.01#ibcon#read 4, iclass 29, count 0 2006.257.05:20:09.01#ibcon#about to read 5, iclass 29, count 0 2006.257.05:20:09.01#ibcon#read 5, iclass 29, count 0 2006.257.05:20:09.01#ibcon#about to read 6, iclass 29, count 0 2006.257.05:20:09.01#ibcon#read 6, iclass 29, count 0 2006.257.05:20:09.01#ibcon#end of sib2, iclass 29, count 0 2006.257.05:20:09.01#ibcon#*mode == 0, iclass 29, count 0 2006.257.05:20:09.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.05:20:09.01#ibcon#[25=USB\r\n] 2006.257.05:20:09.01#ibcon#*before write, iclass 29, count 0 2006.257.05:20:09.01#ibcon#enter sib2, iclass 29, count 0 2006.257.05:20:09.01#ibcon#flushed, iclass 29, count 0 2006.257.05:20:09.01#ibcon#about to write, iclass 29, count 0 2006.257.05:20:09.01#ibcon#wrote, iclass 29, count 0 2006.257.05:20:09.01#ibcon#about to read 3, iclass 29, count 0 2006.257.05:20:09.04#ibcon#read 3, iclass 29, count 0 2006.257.05:20:09.04#ibcon#about to read 4, iclass 29, count 0 2006.257.05:20:09.04#ibcon#read 4, iclass 29, count 0 2006.257.05:20:09.04#ibcon#about to read 5, iclass 29, count 0 2006.257.05:20:09.04#ibcon#read 5, iclass 29, count 0 2006.257.05:20:09.04#ibcon#about to read 6, iclass 29, count 0 2006.257.05:20:09.04#ibcon#read 6, iclass 29, count 0 2006.257.05:20:09.04#ibcon#end of sib2, iclass 29, count 0 2006.257.05:20:09.04#ibcon#*after write, iclass 29, count 0 2006.257.05:20:09.04#ibcon#*before return 0, iclass 29, count 0 2006.257.05:20:09.04#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:09.04#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:09.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.05:20:09.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.05:20:09.04$vck44/valo=6,814.99 2006.257.05:20:09.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.05:20:09.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.05:20:09.04#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:09.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:09.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:09.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:09.04#ibcon#enter wrdev, iclass 31, count 0 2006.257.05:20:09.04#ibcon#first serial, iclass 31, count 0 2006.257.05:20:09.04#ibcon#enter sib2, iclass 31, count 0 2006.257.05:20:09.04#ibcon#flushed, iclass 31, count 0 2006.257.05:20:09.04#ibcon#about to write, iclass 31, count 0 2006.257.05:20:09.04#ibcon#wrote, iclass 31, count 0 2006.257.05:20:09.04#ibcon#about to read 3, iclass 31, count 0 2006.257.05:20:09.06#ibcon#read 3, iclass 31, count 0 2006.257.05:20:09.06#ibcon#about to read 4, iclass 31, count 0 2006.257.05:20:09.06#ibcon#read 4, iclass 31, count 0 2006.257.05:20:09.06#ibcon#about to read 5, iclass 31, count 0 2006.257.05:20:09.06#ibcon#read 5, iclass 31, count 0 2006.257.05:20:09.06#ibcon#about to read 6, iclass 31, count 0 2006.257.05:20:09.06#ibcon#read 6, iclass 31, count 0 2006.257.05:20:09.06#ibcon#end of sib2, iclass 31, count 0 2006.257.05:20:09.06#ibcon#*mode == 0, iclass 31, count 0 2006.257.05:20:09.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.05:20:09.06#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:20:09.06#ibcon#*before write, iclass 31, count 0 2006.257.05:20:09.06#ibcon#enter sib2, iclass 31, count 0 2006.257.05:20:09.06#ibcon#flushed, iclass 31, count 0 2006.257.05:20:09.06#ibcon#about to write, iclass 31, count 0 2006.257.05:20:09.06#ibcon#wrote, iclass 31, count 0 2006.257.05:20:09.06#ibcon#about to read 3, iclass 31, count 0 2006.257.05:20:09.10#ibcon#read 3, iclass 31, count 0 2006.257.05:20:09.10#ibcon#about to read 4, iclass 31, count 0 2006.257.05:20:09.10#ibcon#read 4, iclass 31, count 0 2006.257.05:20:09.10#ibcon#about to read 5, iclass 31, count 0 2006.257.05:20:09.10#ibcon#read 5, iclass 31, count 0 2006.257.05:20:09.10#ibcon#about to read 6, iclass 31, count 0 2006.257.05:20:09.10#ibcon#read 6, iclass 31, count 0 2006.257.05:20:09.10#ibcon#end of sib2, iclass 31, count 0 2006.257.05:20:09.10#ibcon#*after write, iclass 31, count 0 2006.257.05:20:09.10#ibcon#*before return 0, iclass 31, count 0 2006.257.05:20:09.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:09.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:09.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.05:20:09.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.05:20:09.10$vck44/va=6,4 2006.257.05:20:09.10#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.05:20:09.10#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.05:20:09.10#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:09.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:09.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:09.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:09.16#ibcon#enter wrdev, iclass 33, count 2 2006.257.05:20:09.16#ibcon#first serial, iclass 33, count 2 2006.257.05:20:09.16#ibcon#enter sib2, iclass 33, count 2 2006.257.05:20:09.16#ibcon#flushed, iclass 33, count 2 2006.257.05:20:09.16#ibcon#about to write, iclass 33, count 2 2006.257.05:20:09.16#ibcon#wrote, iclass 33, count 2 2006.257.05:20:09.16#ibcon#about to read 3, iclass 33, count 2 2006.257.05:20:09.18#ibcon#read 3, iclass 33, count 2 2006.257.05:20:09.18#ibcon#about to read 4, iclass 33, count 2 2006.257.05:20:09.18#ibcon#read 4, iclass 33, count 2 2006.257.05:20:09.18#ibcon#about to read 5, iclass 33, count 2 2006.257.05:20:09.18#ibcon#read 5, iclass 33, count 2 2006.257.05:20:09.18#ibcon#about to read 6, iclass 33, count 2 2006.257.05:20:09.18#ibcon#read 6, iclass 33, count 2 2006.257.05:20:09.18#ibcon#end of sib2, iclass 33, count 2 2006.257.05:20:09.18#ibcon#*mode == 0, iclass 33, count 2 2006.257.05:20:09.18#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.05:20:09.18#ibcon#[25=AT06-04\r\n] 2006.257.05:20:09.18#ibcon#*before write, iclass 33, count 2 2006.257.05:20:09.18#ibcon#enter sib2, iclass 33, count 2 2006.257.05:20:09.18#ibcon#flushed, iclass 33, count 2 2006.257.05:20:09.18#ibcon#about to write, iclass 33, count 2 2006.257.05:20:09.18#ibcon#wrote, iclass 33, count 2 2006.257.05:20:09.18#ibcon#about to read 3, iclass 33, count 2 2006.257.05:20:09.21#ibcon#read 3, iclass 33, count 2 2006.257.05:20:09.21#ibcon#about to read 4, iclass 33, count 2 2006.257.05:20:09.21#ibcon#read 4, iclass 33, count 2 2006.257.05:20:09.21#ibcon#about to read 5, iclass 33, count 2 2006.257.05:20:09.21#ibcon#read 5, iclass 33, count 2 2006.257.05:20:09.21#ibcon#about to read 6, iclass 33, count 2 2006.257.05:20:09.21#ibcon#read 6, iclass 33, count 2 2006.257.05:20:09.21#ibcon#end of sib2, iclass 33, count 2 2006.257.05:20:09.21#ibcon#*after write, iclass 33, count 2 2006.257.05:20:09.21#ibcon#*before return 0, iclass 33, count 2 2006.257.05:20:09.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:09.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:09.21#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.05:20:09.21#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:09.21#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:09.33#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:09.33#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:09.33#ibcon#enter wrdev, iclass 33, count 0 2006.257.05:20:09.33#ibcon#first serial, iclass 33, count 0 2006.257.05:20:09.33#ibcon#enter sib2, iclass 33, count 0 2006.257.05:20:09.33#ibcon#flushed, iclass 33, count 0 2006.257.05:20:09.33#ibcon#about to write, iclass 33, count 0 2006.257.05:20:09.33#ibcon#wrote, iclass 33, count 0 2006.257.05:20:09.33#ibcon#about to read 3, iclass 33, count 0 2006.257.05:20:09.35#ibcon#read 3, iclass 33, count 0 2006.257.05:20:09.35#ibcon#about to read 4, iclass 33, count 0 2006.257.05:20:09.35#ibcon#read 4, iclass 33, count 0 2006.257.05:20:09.35#ibcon#about to read 5, iclass 33, count 0 2006.257.05:20:09.35#ibcon#read 5, iclass 33, count 0 2006.257.05:20:09.35#ibcon#about to read 6, iclass 33, count 0 2006.257.05:20:09.35#ibcon#read 6, iclass 33, count 0 2006.257.05:20:09.35#ibcon#end of sib2, iclass 33, count 0 2006.257.05:20:09.35#ibcon#*mode == 0, iclass 33, count 0 2006.257.05:20:09.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.05:20:09.35#ibcon#[25=USB\r\n] 2006.257.05:20:09.35#ibcon#*before write, iclass 33, count 0 2006.257.05:20:09.35#ibcon#enter sib2, iclass 33, count 0 2006.257.05:20:09.35#ibcon#flushed, iclass 33, count 0 2006.257.05:20:09.35#ibcon#about to write, iclass 33, count 0 2006.257.05:20:09.35#ibcon#wrote, iclass 33, count 0 2006.257.05:20:09.35#ibcon#about to read 3, iclass 33, count 0 2006.257.05:20:09.38#ibcon#read 3, iclass 33, count 0 2006.257.05:20:09.38#ibcon#about to read 4, iclass 33, count 0 2006.257.05:20:09.38#ibcon#read 4, iclass 33, count 0 2006.257.05:20:09.38#ibcon#about to read 5, iclass 33, count 0 2006.257.05:20:09.38#ibcon#read 5, iclass 33, count 0 2006.257.05:20:09.38#ibcon#about to read 6, iclass 33, count 0 2006.257.05:20:09.38#ibcon#read 6, iclass 33, count 0 2006.257.05:20:09.38#ibcon#end of sib2, iclass 33, count 0 2006.257.05:20:09.38#ibcon#*after write, iclass 33, count 0 2006.257.05:20:09.38#ibcon#*before return 0, iclass 33, count 0 2006.257.05:20:09.38#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:09.38#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:09.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.05:20:09.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.05:20:09.38$vck44/valo=7,864.99 2006.257.05:20:09.38#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.05:20:09.38#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.05:20:09.38#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:09.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:09.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:09.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:09.38#ibcon#enter wrdev, iclass 35, count 0 2006.257.05:20:09.38#ibcon#first serial, iclass 35, count 0 2006.257.05:20:09.38#ibcon#enter sib2, iclass 35, count 0 2006.257.05:20:09.38#ibcon#flushed, iclass 35, count 0 2006.257.05:20:09.38#ibcon#about to write, iclass 35, count 0 2006.257.05:20:09.38#ibcon#wrote, iclass 35, count 0 2006.257.05:20:09.38#ibcon#about to read 3, iclass 35, count 0 2006.257.05:20:09.40#ibcon#read 3, iclass 35, count 0 2006.257.05:20:09.40#ibcon#about to read 4, iclass 35, count 0 2006.257.05:20:09.40#ibcon#read 4, iclass 35, count 0 2006.257.05:20:09.40#ibcon#about to read 5, iclass 35, count 0 2006.257.05:20:09.40#ibcon#read 5, iclass 35, count 0 2006.257.05:20:09.40#ibcon#about to read 6, iclass 35, count 0 2006.257.05:20:09.40#ibcon#read 6, iclass 35, count 0 2006.257.05:20:09.40#ibcon#end of sib2, iclass 35, count 0 2006.257.05:20:09.40#ibcon#*mode == 0, iclass 35, count 0 2006.257.05:20:09.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.05:20:09.40#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:20:09.40#ibcon#*before write, iclass 35, count 0 2006.257.05:20:09.40#ibcon#enter sib2, iclass 35, count 0 2006.257.05:20:09.40#ibcon#flushed, iclass 35, count 0 2006.257.05:20:09.40#ibcon#about to write, iclass 35, count 0 2006.257.05:20:09.40#ibcon#wrote, iclass 35, count 0 2006.257.05:20:09.40#ibcon#about to read 3, iclass 35, count 0 2006.257.05:20:09.44#ibcon#read 3, iclass 35, count 0 2006.257.05:20:09.44#ibcon#about to read 4, iclass 35, count 0 2006.257.05:20:09.44#ibcon#read 4, iclass 35, count 0 2006.257.05:20:09.44#ibcon#about to read 5, iclass 35, count 0 2006.257.05:20:09.44#ibcon#read 5, iclass 35, count 0 2006.257.05:20:09.44#ibcon#about to read 6, iclass 35, count 0 2006.257.05:20:09.44#ibcon#read 6, iclass 35, count 0 2006.257.05:20:09.44#ibcon#end of sib2, iclass 35, count 0 2006.257.05:20:09.44#ibcon#*after write, iclass 35, count 0 2006.257.05:20:09.44#ibcon#*before return 0, iclass 35, count 0 2006.257.05:20:09.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:09.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:09.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.05:20:09.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.05:20:09.44$vck44/va=7,4 2006.257.05:20:09.44#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.05:20:09.44#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.05:20:09.44#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:09.44#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:09.50#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:09.50#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:09.50#ibcon#enter wrdev, iclass 37, count 2 2006.257.05:20:09.50#ibcon#first serial, iclass 37, count 2 2006.257.05:20:09.50#ibcon#enter sib2, iclass 37, count 2 2006.257.05:20:09.50#ibcon#flushed, iclass 37, count 2 2006.257.05:20:09.50#ibcon#about to write, iclass 37, count 2 2006.257.05:20:09.50#ibcon#wrote, iclass 37, count 2 2006.257.05:20:09.50#ibcon#about to read 3, iclass 37, count 2 2006.257.05:20:09.52#ibcon#read 3, iclass 37, count 2 2006.257.05:20:09.52#ibcon#about to read 4, iclass 37, count 2 2006.257.05:20:09.52#ibcon#read 4, iclass 37, count 2 2006.257.05:20:09.52#ibcon#about to read 5, iclass 37, count 2 2006.257.05:20:09.52#ibcon#read 5, iclass 37, count 2 2006.257.05:20:09.52#ibcon#about to read 6, iclass 37, count 2 2006.257.05:20:09.52#ibcon#read 6, iclass 37, count 2 2006.257.05:20:09.52#ibcon#end of sib2, iclass 37, count 2 2006.257.05:20:09.52#ibcon#*mode == 0, iclass 37, count 2 2006.257.05:20:09.52#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.05:20:09.52#ibcon#[25=AT07-04\r\n] 2006.257.05:20:09.52#ibcon#*before write, iclass 37, count 2 2006.257.05:20:09.52#ibcon#enter sib2, iclass 37, count 2 2006.257.05:20:09.52#ibcon#flushed, iclass 37, count 2 2006.257.05:20:09.52#ibcon#about to write, iclass 37, count 2 2006.257.05:20:09.52#ibcon#wrote, iclass 37, count 2 2006.257.05:20:09.52#ibcon#about to read 3, iclass 37, count 2 2006.257.05:20:09.55#ibcon#read 3, iclass 37, count 2 2006.257.05:20:09.55#ibcon#about to read 4, iclass 37, count 2 2006.257.05:20:09.55#ibcon#read 4, iclass 37, count 2 2006.257.05:20:09.55#ibcon#about to read 5, iclass 37, count 2 2006.257.05:20:09.55#ibcon#read 5, iclass 37, count 2 2006.257.05:20:09.55#ibcon#about to read 6, iclass 37, count 2 2006.257.05:20:09.55#ibcon#read 6, iclass 37, count 2 2006.257.05:20:09.55#ibcon#end of sib2, iclass 37, count 2 2006.257.05:20:09.55#ibcon#*after write, iclass 37, count 2 2006.257.05:20:09.55#ibcon#*before return 0, iclass 37, count 2 2006.257.05:20:09.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:09.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:09.55#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.05:20:09.55#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:09.55#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:09.67#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:09.67#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:09.67#ibcon#enter wrdev, iclass 37, count 0 2006.257.05:20:09.67#ibcon#first serial, iclass 37, count 0 2006.257.05:20:09.67#ibcon#enter sib2, iclass 37, count 0 2006.257.05:20:09.67#ibcon#flushed, iclass 37, count 0 2006.257.05:20:09.67#ibcon#about to write, iclass 37, count 0 2006.257.05:20:09.67#ibcon#wrote, iclass 37, count 0 2006.257.05:20:09.67#ibcon#about to read 3, iclass 37, count 0 2006.257.05:20:09.69#ibcon#read 3, iclass 37, count 0 2006.257.05:20:09.69#ibcon#about to read 4, iclass 37, count 0 2006.257.05:20:09.69#ibcon#read 4, iclass 37, count 0 2006.257.05:20:09.69#ibcon#about to read 5, iclass 37, count 0 2006.257.05:20:09.69#ibcon#read 5, iclass 37, count 0 2006.257.05:20:09.69#ibcon#about to read 6, iclass 37, count 0 2006.257.05:20:09.69#ibcon#read 6, iclass 37, count 0 2006.257.05:20:09.69#ibcon#end of sib2, iclass 37, count 0 2006.257.05:20:09.69#ibcon#*mode == 0, iclass 37, count 0 2006.257.05:20:09.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.05:20:09.69#ibcon#[25=USB\r\n] 2006.257.05:20:09.69#ibcon#*before write, iclass 37, count 0 2006.257.05:20:09.69#ibcon#enter sib2, iclass 37, count 0 2006.257.05:20:09.69#ibcon#flushed, iclass 37, count 0 2006.257.05:20:09.69#ibcon#about to write, iclass 37, count 0 2006.257.05:20:09.69#ibcon#wrote, iclass 37, count 0 2006.257.05:20:09.69#ibcon#about to read 3, iclass 37, count 0 2006.257.05:20:09.72#ibcon#read 3, iclass 37, count 0 2006.257.05:20:09.72#ibcon#about to read 4, iclass 37, count 0 2006.257.05:20:09.72#ibcon#read 4, iclass 37, count 0 2006.257.05:20:09.72#ibcon#about to read 5, iclass 37, count 0 2006.257.05:20:09.72#ibcon#read 5, iclass 37, count 0 2006.257.05:20:09.72#ibcon#about to read 6, iclass 37, count 0 2006.257.05:20:09.72#ibcon#read 6, iclass 37, count 0 2006.257.05:20:09.72#ibcon#end of sib2, iclass 37, count 0 2006.257.05:20:09.72#ibcon#*after write, iclass 37, count 0 2006.257.05:20:09.72#ibcon#*before return 0, iclass 37, count 0 2006.257.05:20:09.72#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:09.72#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:09.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.05:20:09.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.05:20:09.72$vck44/valo=8,884.99 2006.257.05:20:09.72#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.05:20:09.72#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.05:20:09.72#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:09.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:09.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:09.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:09.72#ibcon#enter wrdev, iclass 39, count 0 2006.257.05:20:09.72#ibcon#first serial, iclass 39, count 0 2006.257.05:20:09.72#ibcon#enter sib2, iclass 39, count 0 2006.257.05:20:09.72#ibcon#flushed, iclass 39, count 0 2006.257.05:20:09.72#ibcon#about to write, iclass 39, count 0 2006.257.05:20:09.72#ibcon#wrote, iclass 39, count 0 2006.257.05:20:09.72#ibcon#about to read 3, iclass 39, count 0 2006.257.05:20:09.74#ibcon#read 3, iclass 39, count 0 2006.257.05:20:09.74#ibcon#about to read 4, iclass 39, count 0 2006.257.05:20:09.74#ibcon#read 4, iclass 39, count 0 2006.257.05:20:09.74#ibcon#about to read 5, iclass 39, count 0 2006.257.05:20:09.74#ibcon#read 5, iclass 39, count 0 2006.257.05:20:09.74#ibcon#about to read 6, iclass 39, count 0 2006.257.05:20:09.74#ibcon#read 6, iclass 39, count 0 2006.257.05:20:09.74#ibcon#end of sib2, iclass 39, count 0 2006.257.05:20:09.74#ibcon#*mode == 0, iclass 39, count 0 2006.257.05:20:09.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.05:20:09.74#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:20:09.74#ibcon#*before write, iclass 39, count 0 2006.257.05:20:09.74#ibcon#enter sib2, iclass 39, count 0 2006.257.05:20:09.74#ibcon#flushed, iclass 39, count 0 2006.257.05:20:09.74#ibcon#about to write, iclass 39, count 0 2006.257.05:20:09.74#ibcon#wrote, iclass 39, count 0 2006.257.05:20:09.74#ibcon#about to read 3, iclass 39, count 0 2006.257.05:20:09.78#ibcon#read 3, iclass 39, count 0 2006.257.05:20:09.78#ibcon#about to read 4, iclass 39, count 0 2006.257.05:20:09.78#ibcon#read 4, iclass 39, count 0 2006.257.05:20:09.78#ibcon#about to read 5, iclass 39, count 0 2006.257.05:20:09.78#ibcon#read 5, iclass 39, count 0 2006.257.05:20:09.78#ibcon#about to read 6, iclass 39, count 0 2006.257.05:20:09.78#ibcon#read 6, iclass 39, count 0 2006.257.05:20:09.78#ibcon#end of sib2, iclass 39, count 0 2006.257.05:20:09.78#ibcon#*after write, iclass 39, count 0 2006.257.05:20:09.78#ibcon#*before return 0, iclass 39, count 0 2006.257.05:20:09.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:09.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:09.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.05:20:09.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.05:20:09.78$vck44/va=8,4 2006.257.05:20:09.78#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.05:20:09.78#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.05:20:09.78#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:09.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:09.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:09.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:09.84#ibcon#enter wrdev, iclass 3, count 2 2006.257.05:20:09.84#ibcon#first serial, iclass 3, count 2 2006.257.05:20:09.84#ibcon#enter sib2, iclass 3, count 2 2006.257.05:20:09.84#ibcon#flushed, iclass 3, count 2 2006.257.05:20:09.84#ibcon#about to write, iclass 3, count 2 2006.257.05:20:09.84#ibcon#wrote, iclass 3, count 2 2006.257.05:20:09.84#ibcon#about to read 3, iclass 3, count 2 2006.257.05:20:09.86#ibcon#read 3, iclass 3, count 2 2006.257.05:20:09.86#ibcon#about to read 4, iclass 3, count 2 2006.257.05:20:09.86#ibcon#read 4, iclass 3, count 2 2006.257.05:20:09.86#ibcon#about to read 5, iclass 3, count 2 2006.257.05:20:09.86#ibcon#read 5, iclass 3, count 2 2006.257.05:20:09.86#ibcon#about to read 6, iclass 3, count 2 2006.257.05:20:09.86#ibcon#read 6, iclass 3, count 2 2006.257.05:20:09.86#ibcon#end of sib2, iclass 3, count 2 2006.257.05:20:09.86#ibcon#*mode == 0, iclass 3, count 2 2006.257.05:20:09.86#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.05:20:09.86#ibcon#[25=AT08-04\r\n] 2006.257.05:20:09.86#ibcon#*before write, iclass 3, count 2 2006.257.05:20:09.86#ibcon#enter sib2, iclass 3, count 2 2006.257.05:20:09.86#ibcon#flushed, iclass 3, count 2 2006.257.05:20:09.86#ibcon#about to write, iclass 3, count 2 2006.257.05:20:09.86#ibcon#wrote, iclass 3, count 2 2006.257.05:20:09.86#ibcon#about to read 3, iclass 3, count 2 2006.257.05:20:09.89#ibcon#read 3, iclass 3, count 2 2006.257.05:20:09.89#ibcon#about to read 4, iclass 3, count 2 2006.257.05:20:09.89#ibcon#read 4, iclass 3, count 2 2006.257.05:20:09.89#ibcon#about to read 5, iclass 3, count 2 2006.257.05:20:09.89#ibcon#read 5, iclass 3, count 2 2006.257.05:20:09.89#ibcon#about to read 6, iclass 3, count 2 2006.257.05:20:09.89#ibcon#read 6, iclass 3, count 2 2006.257.05:20:09.89#ibcon#end of sib2, iclass 3, count 2 2006.257.05:20:09.89#ibcon#*after write, iclass 3, count 2 2006.257.05:20:09.89#ibcon#*before return 0, iclass 3, count 2 2006.257.05:20:09.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:09.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:09.89#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.05:20:09.89#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:09.89#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:10.01#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:10.01#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:10.01#ibcon#enter wrdev, iclass 3, count 0 2006.257.05:20:10.01#ibcon#first serial, iclass 3, count 0 2006.257.05:20:10.01#ibcon#enter sib2, iclass 3, count 0 2006.257.05:20:10.01#ibcon#flushed, iclass 3, count 0 2006.257.05:20:10.01#ibcon#about to write, iclass 3, count 0 2006.257.05:20:10.01#ibcon#wrote, iclass 3, count 0 2006.257.05:20:10.01#ibcon#about to read 3, iclass 3, count 0 2006.257.05:20:10.03#ibcon#read 3, iclass 3, count 0 2006.257.05:20:10.03#ibcon#about to read 4, iclass 3, count 0 2006.257.05:20:10.03#ibcon#read 4, iclass 3, count 0 2006.257.05:20:10.03#ibcon#about to read 5, iclass 3, count 0 2006.257.05:20:10.03#ibcon#read 5, iclass 3, count 0 2006.257.05:20:10.03#ibcon#about to read 6, iclass 3, count 0 2006.257.05:20:10.03#ibcon#read 6, iclass 3, count 0 2006.257.05:20:10.03#ibcon#end of sib2, iclass 3, count 0 2006.257.05:20:10.03#ibcon#*mode == 0, iclass 3, count 0 2006.257.05:20:10.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.05:20:10.03#ibcon#[25=USB\r\n] 2006.257.05:20:10.03#ibcon#*before write, iclass 3, count 0 2006.257.05:20:10.03#ibcon#enter sib2, iclass 3, count 0 2006.257.05:20:10.03#ibcon#flushed, iclass 3, count 0 2006.257.05:20:10.03#ibcon#about to write, iclass 3, count 0 2006.257.05:20:10.03#ibcon#wrote, iclass 3, count 0 2006.257.05:20:10.03#ibcon#about to read 3, iclass 3, count 0 2006.257.05:20:10.06#ibcon#read 3, iclass 3, count 0 2006.257.05:20:10.06#ibcon#about to read 4, iclass 3, count 0 2006.257.05:20:10.06#ibcon#read 4, iclass 3, count 0 2006.257.05:20:10.06#ibcon#about to read 5, iclass 3, count 0 2006.257.05:20:10.06#ibcon#read 5, iclass 3, count 0 2006.257.05:20:10.06#ibcon#about to read 6, iclass 3, count 0 2006.257.05:20:10.06#ibcon#read 6, iclass 3, count 0 2006.257.05:20:10.06#ibcon#end of sib2, iclass 3, count 0 2006.257.05:20:10.06#ibcon#*after write, iclass 3, count 0 2006.257.05:20:10.06#ibcon#*before return 0, iclass 3, count 0 2006.257.05:20:10.06#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:10.06#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:10.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.05:20:10.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.05:20:10.06$vck44/vblo=1,629.99 2006.257.05:20:10.06#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.05:20:10.06#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.05:20:10.06#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:10.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:10.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:10.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:10.06#ibcon#enter wrdev, iclass 5, count 0 2006.257.05:20:10.06#ibcon#first serial, iclass 5, count 0 2006.257.05:20:10.06#ibcon#enter sib2, iclass 5, count 0 2006.257.05:20:10.06#ibcon#flushed, iclass 5, count 0 2006.257.05:20:10.06#ibcon#about to write, iclass 5, count 0 2006.257.05:20:10.06#ibcon#wrote, iclass 5, count 0 2006.257.05:20:10.06#ibcon#about to read 3, iclass 5, count 0 2006.257.05:20:10.08#ibcon#read 3, iclass 5, count 0 2006.257.05:20:10.08#ibcon#about to read 4, iclass 5, count 0 2006.257.05:20:10.08#ibcon#read 4, iclass 5, count 0 2006.257.05:20:10.08#ibcon#about to read 5, iclass 5, count 0 2006.257.05:20:10.08#ibcon#read 5, iclass 5, count 0 2006.257.05:20:10.08#ibcon#about to read 6, iclass 5, count 0 2006.257.05:20:10.08#ibcon#read 6, iclass 5, count 0 2006.257.05:20:10.08#ibcon#end of sib2, iclass 5, count 0 2006.257.05:20:10.08#ibcon#*mode == 0, iclass 5, count 0 2006.257.05:20:10.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.05:20:10.08#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:20:10.08#ibcon#*before write, iclass 5, count 0 2006.257.05:20:10.08#ibcon#enter sib2, iclass 5, count 0 2006.257.05:20:10.08#ibcon#flushed, iclass 5, count 0 2006.257.05:20:10.08#ibcon#about to write, iclass 5, count 0 2006.257.05:20:10.08#ibcon#wrote, iclass 5, count 0 2006.257.05:20:10.08#ibcon#about to read 3, iclass 5, count 0 2006.257.05:20:10.12#ibcon#read 3, iclass 5, count 0 2006.257.05:20:10.12#ibcon#about to read 4, iclass 5, count 0 2006.257.05:20:10.12#ibcon#read 4, iclass 5, count 0 2006.257.05:20:10.12#ibcon#about to read 5, iclass 5, count 0 2006.257.05:20:10.12#ibcon#read 5, iclass 5, count 0 2006.257.05:20:10.12#ibcon#about to read 6, iclass 5, count 0 2006.257.05:20:10.12#ibcon#read 6, iclass 5, count 0 2006.257.05:20:10.12#ibcon#end of sib2, iclass 5, count 0 2006.257.05:20:10.12#ibcon#*after write, iclass 5, count 0 2006.257.05:20:10.12#ibcon#*before return 0, iclass 5, count 0 2006.257.05:20:10.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:10.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:10.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.05:20:10.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.05:20:10.12$vck44/vb=1,4 2006.257.05:20:10.12#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.05:20:10.12#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.05:20:10.12#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:10.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:20:10.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:20:10.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:20:10.12#ibcon#enter wrdev, iclass 7, count 2 2006.257.05:20:10.12#ibcon#first serial, iclass 7, count 2 2006.257.05:20:10.12#ibcon#enter sib2, iclass 7, count 2 2006.257.05:20:10.12#ibcon#flushed, iclass 7, count 2 2006.257.05:20:10.12#ibcon#about to write, iclass 7, count 2 2006.257.05:20:10.12#ibcon#wrote, iclass 7, count 2 2006.257.05:20:10.12#ibcon#about to read 3, iclass 7, count 2 2006.257.05:20:10.14#ibcon#read 3, iclass 7, count 2 2006.257.05:20:10.14#ibcon#about to read 4, iclass 7, count 2 2006.257.05:20:10.14#ibcon#read 4, iclass 7, count 2 2006.257.05:20:10.14#ibcon#about to read 5, iclass 7, count 2 2006.257.05:20:10.14#ibcon#read 5, iclass 7, count 2 2006.257.05:20:10.14#ibcon#about to read 6, iclass 7, count 2 2006.257.05:20:10.14#ibcon#read 6, iclass 7, count 2 2006.257.05:20:10.14#ibcon#end of sib2, iclass 7, count 2 2006.257.05:20:10.14#ibcon#*mode == 0, iclass 7, count 2 2006.257.05:20:10.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.05:20:10.14#ibcon#[27=AT01-04\r\n] 2006.257.05:20:10.14#ibcon#*before write, iclass 7, count 2 2006.257.05:20:10.14#ibcon#enter sib2, iclass 7, count 2 2006.257.05:20:10.14#ibcon#flushed, iclass 7, count 2 2006.257.05:20:10.14#ibcon#about to write, iclass 7, count 2 2006.257.05:20:10.14#ibcon#wrote, iclass 7, count 2 2006.257.05:20:10.14#ibcon#about to read 3, iclass 7, count 2 2006.257.05:20:10.17#ibcon#read 3, iclass 7, count 2 2006.257.05:20:10.17#ibcon#about to read 4, iclass 7, count 2 2006.257.05:20:10.17#ibcon#read 4, iclass 7, count 2 2006.257.05:20:10.17#ibcon#about to read 5, iclass 7, count 2 2006.257.05:20:10.17#ibcon#read 5, iclass 7, count 2 2006.257.05:20:10.17#ibcon#about to read 6, iclass 7, count 2 2006.257.05:20:10.17#ibcon#read 6, iclass 7, count 2 2006.257.05:20:10.17#ibcon#end of sib2, iclass 7, count 2 2006.257.05:20:10.17#ibcon#*after write, iclass 7, count 2 2006.257.05:20:10.17#ibcon#*before return 0, iclass 7, count 2 2006.257.05:20:10.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:20:10.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:20:10.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.05:20:10.17#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:10.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:20:10.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:20:10.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:20:10.29#ibcon#enter wrdev, iclass 7, count 0 2006.257.05:20:10.29#ibcon#first serial, iclass 7, count 0 2006.257.05:20:10.29#ibcon#enter sib2, iclass 7, count 0 2006.257.05:20:10.29#ibcon#flushed, iclass 7, count 0 2006.257.05:20:10.29#ibcon#about to write, iclass 7, count 0 2006.257.05:20:10.29#ibcon#wrote, iclass 7, count 0 2006.257.05:20:10.29#ibcon#about to read 3, iclass 7, count 0 2006.257.05:20:10.31#ibcon#read 3, iclass 7, count 0 2006.257.05:20:10.31#ibcon#about to read 4, iclass 7, count 0 2006.257.05:20:10.31#ibcon#read 4, iclass 7, count 0 2006.257.05:20:10.31#ibcon#about to read 5, iclass 7, count 0 2006.257.05:20:10.31#ibcon#read 5, iclass 7, count 0 2006.257.05:20:10.31#ibcon#about to read 6, iclass 7, count 0 2006.257.05:20:10.31#ibcon#read 6, iclass 7, count 0 2006.257.05:20:10.31#ibcon#end of sib2, iclass 7, count 0 2006.257.05:20:10.31#ibcon#*mode == 0, iclass 7, count 0 2006.257.05:20:10.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.05:20:10.31#ibcon#[27=USB\r\n] 2006.257.05:20:10.31#ibcon#*before write, iclass 7, count 0 2006.257.05:20:10.31#ibcon#enter sib2, iclass 7, count 0 2006.257.05:20:10.31#ibcon#flushed, iclass 7, count 0 2006.257.05:20:10.31#ibcon#about to write, iclass 7, count 0 2006.257.05:20:10.31#ibcon#wrote, iclass 7, count 0 2006.257.05:20:10.31#ibcon#about to read 3, iclass 7, count 0 2006.257.05:20:10.34#ibcon#read 3, iclass 7, count 0 2006.257.05:20:10.34#ibcon#about to read 4, iclass 7, count 0 2006.257.05:20:10.34#ibcon#read 4, iclass 7, count 0 2006.257.05:20:10.34#ibcon#about to read 5, iclass 7, count 0 2006.257.05:20:10.34#ibcon#read 5, iclass 7, count 0 2006.257.05:20:10.34#ibcon#about to read 6, iclass 7, count 0 2006.257.05:20:10.34#ibcon#read 6, iclass 7, count 0 2006.257.05:20:10.34#ibcon#end of sib2, iclass 7, count 0 2006.257.05:20:10.34#ibcon#*after write, iclass 7, count 0 2006.257.05:20:10.34#ibcon#*before return 0, iclass 7, count 0 2006.257.05:20:10.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:20:10.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:20:10.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.05:20:10.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.05:20:10.34$vck44/vblo=2,634.99 2006.257.05:20:10.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.05:20:10.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.05:20:10.34#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:10.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:10.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:10.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:10.34#ibcon#enter wrdev, iclass 11, count 0 2006.257.05:20:10.34#ibcon#first serial, iclass 11, count 0 2006.257.05:20:10.34#ibcon#enter sib2, iclass 11, count 0 2006.257.05:20:10.34#ibcon#flushed, iclass 11, count 0 2006.257.05:20:10.34#ibcon#about to write, iclass 11, count 0 2006.257.05:20:10.34#ibcon#wrote, iclass 11, count 0 2006.257.05:20:10.34#ibcon#about to read 3, iclass 11, count 0 2006.257.05:20:10.36#ibcon#read 3, iclass 11, count 0 2006.257.05:20:10.36#ibcon#about to read 4, iclass 11, count 0 2006.257.05:20:10.36#ibcon#read 4, iclass 11, count 0 2006.257.05:20:10.36#ibcon#about to read 5, iclass 11, count 0 2006.257.05:20:10.36#ibcon#read 5, iclass 11, count 0 2006.257.05:20:10.36#ibcon#about to read 6, iclass 11, count 0 2006.257.05:20:10.36#ibcon#read 6, iclass 11, count 0 2006.257.05:20:10.36#ibcon#end of sib2, iclass 11, count 0 2006.257.05:20:10.36#ibcon#*mode == 0, iclass 11, count 0 2006.257.05:20:10.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.05:20:10.36#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:20:10.36#ibcon#*before write, iclass 11, count 0 2006.257.05:20:10.36#ibcon#enter sib2, iclass 11, count 0 2006.257.05:20:10.36#ibcon#flushed, iclass 11, count 0 2006.257.05:20:10.36#ibcon#about to write, iclass 11, count 0 2006.257.05:20:10.36#ibcon#wrote, iclass 11, count 0 2006.257.05:20:10.36#ibcon#about to read 3, iclass 11, count 0 2006.257.05:20:10.40#ibcon#read 3, iclass 11, count 0 2006.257.05:20:10.40#ibcon#about to read 4, iclass 11, count 0 2006.257.05:20:10.40#ibcon#read 4, iclass 11, count 0 2006.257.05:20:10.40#ibcon#about to read 5, iclass 11, count 0 2006.257.05:20:10.40#ibcon#read 5, iclass 11, count 0 2006.257.05:20:10.40#ibcon#about to read 6, iclass 11, count 0 2006.257.05:20:10.40#ibcon#read 6, iclass 11, count 0 2006.257.05:20:10.40#ibcon#end of sib2, iclass 11, count 0 2006.257.05:20:10.40#ibcon#*after write, iclass 11, count 0 2006.257.05:20:10.40#ibcon#*before return 0, iclass 11, count 0 2006.257.05:20:10.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:10.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:20:10.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.05:20:10.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.05:20:10.40$vck44/vb=2,5 2006.257.05:20:10.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.05:20:10.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.05:20:10.40#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:10.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:10.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:10.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:10.46#ibcon#enter wrdev, iclass 13, count 2 2006.257.05:20:10.46#ibcon#first serial, iclass 13, count 2 2006.257.05:20:10.46#ibcon#enter sib2, iclass 13, count 2 2006.257.05:20:10.46#ibcon#flushed, iclass 13, count 2 2006.257.05:20:10.46#ibcon#about to write, iclass 13, count 2 2006.257.05:20:10.46#ibcon#wrote, iclass 13, count 2 2006.257.05:20:10.46#ibcon#about to read 3, iclass 13, count 2 2006.257.05:20:10.48#ibcon#read 3, iclass 13, count 2 2006.257.05:20:10.48#ibcon#about to read 4, iclass 13, count 2 2006.257.05:20:10.48#ibcon#read 4, iclass 13, count 2 2006.257.05:20:10.48#ibcon#about to read 5, iclass 13, count 2 2006.257.05:20:10.48#ibcon#read 5, iclass 13, count 2 2006.257.05:20:10.48#ibcon#about to read 6, iclass 13, count 2 2006.257.05:20:10.48#ibcon#read 6, iclass 13, count 2 2006.257.05:20:10.48#ibcon#end of sib2, iclass 13, count 2 2006.257.05:20:10.48#ibcon#*mode == 0, iclass 13, count 2 2006.257.05:20:10.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.05:20:10.48#ibcon#[27=AT02-05\r\n] 2006.257.05:20:10.48#ibcon#*before write, iclass 13, count 2 2006.257.05:20:10.48#ibcon#enter sib2, iclass 13, count 2 2006.257.05:20:10.48#ibcon#flushed, iclass 13, count 2 2006.257.05:20:10.48#ibcon#about to write, iclass 13, count 2 2006.257.05:20:10.48#ibcon#wrote, iclass 13, count 2 2006.257.05:20:10.48#ibcon#about to read 3, iclass 13, count 2 2006.257.05:20:10.51#ibcon#read 3, iclass 13, count 2 2006.257.05:20:10.51#ibcon#about to read 4, iclass 13, count 2 2006.257.05:20:10.51#ibcon#read 4, iclass 13, count 2 2006.257.05:20:10.51#ibcon#about to read 5, iclass 13, count 2 2006.257.05:20:10.51#ibcon#read 5, iclass 13, count 2 2006.257.05:20:10.51#ibcon#about to read 6, iclass 13, count 2 2006.257.05:20:10.51#ibcon#read 6, iclass 13, count 2 2006.257.05:20:10.51#ibcon#end of sib2, iclass 13, count 2 2006.257.05:20:10.51#ibcon#*after write, iclass 13, count 2 2006.257.05:20:10.51#ibcon#*before return 0, iclass 13, count 2 2006.257.05:20:10.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:10.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:20:10.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.05:20:10.51#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:10.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:10.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:10.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:10.63#ibcon#enter wrdev, iclass 13, count 0 2006.257.05:20:10.63#ibcon#first serial, iclass 13, count 0 2006.257.05:20:10.63#ibcon#enter sib2, iclass 13, count 0 2006.257.05:20:10.63#ibcon#flushed, iclass 13, count 0 2006.257.05:20:10.63#ibcon#about to write, iclass 13, count 0 2006.257.05:20:10.63#ibcon#wrote, iclass 13, count 0 2006.257.05:20:10.63#ibcon#about to read 3, iclass 13, count 0 2006.257.05:20:10.65#ibcon#read 3, iclass 13, count 0 2006.257.05:20:10.65#ibcon#about to read 4, iclass 13, count 0 2006.257.05:20:10.65#ibcon#read 4, iclass 13, count 0 2006.257.05:20:10.65#ibcon#about to read 5, iclass 13, count 0 2006.257.05:20:10.65#ibcon#read 5, iclass 13, count 0 2006.257.05:20:10.65#ibcon#about to read 6, iclass 13, count 0 2006.257.05:20:10.65#ibcon#read 6, iclass 13, count 0 2006.257.05:20:10.65#ibcon#end of sib2, iclass 13, count 0 2006.257.05:20:10.65#ibcon#*mode == 0, iclass 13, count 0 2006.257.05:20:10.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.05:20:10.65#ibcon#[27=USB\r\n] 2006.257.05:20:10.65#ibcon#*before write, iclass 13, count 0 2006.257.05:20:10.65#ibcon#enter sib2, iclass 13, count 0 2006.257.05:20:10.65#ibcon#flushed, iclass 13, count 0 2006.257.05:20:10.65#ibcon#about to write, iclass 13, count 0 2006.257.05:20:10.65#ibcon#wrote, iclass 13, count 0 2006.257.05:20:10.65#ibcon#about to read 3, iclass 13, count 0 2006.257.05:20:10.68#ibcon#read 3, iclass 13, count 0 2006.257.05:20:10.68#ibcon#about to read 4, iclass 13, count 0 2006.257.05:20:10.68#ibcon#read 4, iclass 13, count 0 2006.257.05:20:10.68#ibcon#about to read 5, iclass 13, count 0 2006.257.05:20:10.68#ibcon#read 5, iclass 13, count 0 2006.257.05:20:10.68#ibcon#about to read 6, iclass 13, count 0 2006.257.05:20:10.68#ibcon#read 6, iclass 13, count 0 2006.257.05:20:10.68#ibcon#end of sib2, iclass 13, count 0 2006.257.05:20:10.68#ibcon#*after write, iclass 13, count 0 2006.257.05:20:10.68#ibcon#*before return 0, iclass 13, count 0 2006.257.05:20:10.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:10.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:20:10.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.05:20:10.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.05:20:10.68$vck44/vblo=3,649.99 2006.257.05:20:10.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.05:20:10.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.05:20:10.68#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:10.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:10.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:10.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:10.68#ibcon#enter wrdev, iclass 15, count 0 2006.257.05:20:10.68#ibcon#first serial, iclass 15, count 0 2006.257.05:20:10.68#ibcon#enter sib2, iclass 15, count 0 2006.257.05:20:10.68#ibcon#flushed, iclass 15, count 0 2006.257.05:20:10.68#ibcon#about to write, iclass 15, count 0 2006.257.05:20:10.68#ibcon#wrote, iclass 15, count 0 2006.257.05:20:10.68#ibcon#about to read 3, iclass 15, count 0 2006.257.05:20:10.70#ibcon#read 3, iclass 15, count 0 2006.257.05:20:10.70#ibcon#about to read 4, iclass 15, count 0 2006.257.05:20:10.70#ibcon#read 4, iclass 15, count 0 2006.257.05:20:10.70#ibcon#about to read 5, iclass 15, count 0 2006.257.05:20:10.70#ibcon#read 5, iclass 15, count 0 2006.257.05:20:10.70#ibcon#about to read 6, iclass 15, count 0 2006.257.05:20:10.70#ibcon#read 6, iclass 15, count 0 2006.257.05:20:10.70#ibcon#end of sib2, iclass 15, count 0 2006.257.05:20:10.70#ibcon#*mode == 0, iclass 15, count 0 2006.257.05:20:10.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.05:20:10.70#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:20:10.70#ibcon#*before write, iclass 15, count 0 2006.257.05:20:10.70#ibcon#enter sib2, iclass 15, count 0 2006.257.05:20:10.70#ibcon#flushed, iclass 15, count 0 2006.257.05:20:10.70#ibcon#about to write, iclass 15, count 0 2006.257.05:20:10.70#ibcon#wrote, iclass 15, count 0 2006.257.05:20:10.70#ibcon#about to read 3, iclass 15, count 0 2006.257.05:20:10.74#ibcon#read 3, iclass 15, count 0 2006.257.05:20:10.74#ibcon#about to read 4, iclass 15, count 0 2006.257.05:20:10.74#ibcon#read 4, iclass 15, count 0 2006.257.05:20:10.74#ibcon#about to read 5, iclass 15, count 0 2006.257.05:20:10.74#ibcon#read 5, iclass 15, count 0 2006.257.05:20:10.74#ibcon#about to read 6, iclass 15, count 0 2006.257.05:20:10.74#ibcon#read 6, iclass 15, count 0 2006.257.05:20:10.74#ibcon#end of sib2, iclass 15, count 0 2006.257.05:20:10.74#ibcon#*after write, iclass 15, count 0 2006.257.05:20:10.74#ibcon#*before return 0, iclass 15, count 0 2006.257.05:20:10.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:10.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:20:10.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.05:20:10.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.05:20:10.74$vck44/vb=3,4 2006.257.05:20:10.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.05:20:10.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.05:20:10.74#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:10.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:10.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:10.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:10.80#ibcon#enter wrdev, iclass 17, count 2 2006.257.05:20:10.80#ibcon#first serial, iclass 17, count 2 2006.257.05:20:10.80#ibcon#enter sib2, iclass 17, count 2 2006.257.05:20:10.80#ibcon#flushed, iclass 17, count 2 2006.257.05:20:10.80#ibcon#about to write, iclass 17, count 2 2006.257.05:20:10.80#ibcon#wrote, iclass 17, count 2 2006.257.05:20:10.80#ibcon#about to read 3, iclass 17, count 2 2006.257.05:20:10.82#ibcon#read 3, iclass 17, count 2 2006.257.05:20:10.82#ibcon#about to read 4, iclass 17, count 2 2006.257.05:20:10.82#ibcon#read 4, iclass 17, count 2 2006.257.05:20:10.82#ibcon#about to read 5, iclass 17, count 2 2006.257.05:20:10.82#ibcon#read 5, iclass 17, count 2 2006.257.05:20:10.82#ibcon#about to read 6, iclass 17, count 2 2006.257.05:20:10.82#ibcon#read 6, iclass 17, count 2 2006.257.05:20:10.82#ibcon#end of sib2, iclass 17, count 2 2006.257.05:20:10.82#ibcon#*mode == 0, iclass 17, count 2 2006.257.05:20:10.82#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.05:20:10.82#ibcon#[27=AT03-04\r\n] 2006.257.05:20:10.82#ibcon#*before write, iclass 17, count 2 2006.257.05:20:10.82#ibcon#enter sib2, iclass 17, count 2 2006.257.05:20:10.82#ibcon#flushed, iclass 17, count 2 2006.257.05:20:10.82#ibcon#about to write, iclass 17, count 2 2006.257.05:20:10.82#ibcon#wrote, iclass 17, count 2 2006.257.05:20:10.82#ibcon#about to read 3, iclass 17, count 2 2006.257.05:20:10.85#ibcon#read 3, iclass 17, count 2 2006.257.05:20:10.85#ibcon#about to read 4, iclass 17, count 2 2006.257.05:20:10.85#ibcon#read 4, iclass 17, count 2 2006.257.05:20:10.85#ibcon#about to read 5, iclass 17, count 2 2006.257.05:20:10.85#ibcon#read 5, iclass 17, count 2 2006.257.05:20:10.85#ibcon#about to read 6, iclass 17, count 2 2006.257.05:20:10.85#ibcon#read 6, iclass 17, count 2 2006.257.05:20:10.85#ibcon#end of sib2, iclass 17, count 2 2006.257.05:20:10.85#ibcon#*after write, iclass 17, count 2 2006.257.05:20:10.85#ibcon#*before return 0, iclass 17, count 2 2006.257.05:20:10.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:10.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:20:10.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.05:20:10.85#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:10.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:10.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:10.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:10.97#ibcon#enter wrdev, iclass 17, count 0 2006.257.05:20:10.97#ibcon#first serial, iclass 17, count 0 2006.257.05:20:10.97#ibcon#enter sib2, iclass 17, count 0 2006.257.05:20:10.97#ibcon#flushed, iclass 17, count 0 2006.257.05:20:10.97#ibcon#about to write, iclass 17, count 0 2006.257.05:20:10.97#ibcon#wrote, iclass 17, count 0 2006.257.05:20:10.97#ibcon#about to read 3, iclass 17, count 0 2006.257.05:20:10.99#ibcon#read 3, iclass 17, count 0 2006.257.05:20:10.99#ibcon#about to read 4, iclass 17, count 0 2006.257.05:20:10.99#ibcon#read 4, iclass 17, count 0 2006.257.05:20:10.99#ibcon#about to read 5, iclass 17, count 0 2006.257.05:20:10.99#ibcon#read 5, iclass 17, count 0 2006.257.05:20:10.99#ibcon#about to read 6, iclass 17, count 0 2006.257.05:20:10.99#ibcon#read 6, iclass 17, count 0 2006.257.05:20:10.99#ibcon#end of sib2, iclass 17, count 0 2006.257.05:20:10.99#ibcon#*mode == 0, iclass 17, count 0 2006.257.05:20:10.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.05:20:10.99#ibcon#[27=USB\r\n] 2006.257.05:20:10.99#ibcon#*before write, iclass 17, count 0 2006.257.05:20:10.99#ibcon#enter sib2, iclass 17, count 0 2006.257.05:20:10.99#ibcon#flushed, iclass 17, count 0 2006.257.05:20:10.99#ibcon#about to write, iclass 17, count 0 2006.257.05:20:10.99#ibcon#wrote, iclass 17, count 0 2006.257.05:20:10.99#ibcon#about to read 3, iclass 17, count 0 2006.257.05:20:11.02#ibcon#read 3, iclass 17, count 0 2006.257.05:20:11.02#ibcon#about to read 4, iclass 17, count 0 2006.257.05:20:11.02#ibcon#read 4, iclass 17, count 0 2006.257.05:20:11.02#ibcon#about to read 5, iclass 17, count 0 2006.257.05:20:11.02#ibcon#read 5, iclass 17, count 0 2006.257.05:20:11.02#ibcon#about to read 6, iclass 17, count 0 2006.257.05:20:11.02#ibcon#read 6, iclass 17, count 0 2006.257.05:20:11.02#ibcon#end of sib2, iclass 17, count 0 2006.257.05:20:11.02#ibcon#*after write, iclass 17, count 0 2006.257.05:20:11.02#ibcon#*before return 0, iclass 17, count 0 2006.257.05:20:11.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:11.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:20:11.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.05:20:11.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.05:20:11.02$vck44/vblo=4,679.99 2006.257.05:20:11.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.05:20:11.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.05:20:11.02#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:11.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:11.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:11.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:11.02#ibcon#enter wrdev, iclass 19, count 0 2006.257.05:20:11.02#ibcon#first serial, iclass 19, count 0 2006.257.05:20:11.02#ibcon#enter sib2, iclass 19, count 0 2006.257.05:20:11.02#ibcon#flushed, iclass 19, count 0 2006.257.05:20:11.02#ibcon#about to write, iclass 19, count 0 2006.257.05:20:11.02#ibcon#wrote, iclass 19, count 0 2006.257.05:20:11.02#ibcon#about to read 3, iclass 19, count 0 2006.257.05:20:11.04#ibcon#read 3, iclass 19, count 0 2006.257.05:20:11.04#ibcon#about to read 4, iclass 19, count 0 2006.257.05:20:11.04#ibcon#read 4, iclass 19, count 0 2006.257.05:20:11.04#ibcon#about to read 5, iclass 19, count 0 2006.257.05:20:11.04#ibcon#read 5, iclass 19, count 0 2006.257.05:20:11.04#ibcon#about to read 6, iclass 19, count 0 2006.257.05:20:11.04#ibcon#read 6, iclass 19, count 0 2006.257.05:20:11.04#ibcon#end of sib2, iclass 19, count 0 2006.257.05:20:11.04#ibcon#*mode == 0, iclass 19, count 0 2006.257.05:20:11.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.05:20:11.04#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:20:11.04#ibcon#*before write, iclass 19, count 0 2006.257.05:20:11.04#ibcon#enter sib2, iclass 19, count 0 2006.257.05:20:11.04#ibcon#flushed, iclass 19, count 0 2006.257.05:20:11.04#ibcon#about to write, iclass 19, count 0 2006.257.05:20:11.04#ibcon#wrote, iclass 19, count 0 2006.257.05:20:11.04#ibcon#about to read 3, iclass 19, count 0 2006.257.05:20:11.08#ibcon#read 3, iclass 19, count 0 2006.257.05:20:11.08#ibcon#about to read 4, iclass 19, count 0 2006.257.05:20:11.08#ibcon#read 4, iclass 19, count 0 2006.257.05:20:11.08#ibcon#about to read 5, iclass 19, count 0 2006.257.05:20:11.08#ibcon#read 5, iclass 19, count 0 2006.257.05:20:11.08#ibcon#about to read 6, iclass 19, count 0 2006.257.05:20:11.08#ibcon#read 6, iclass 19, count 0 2006.257.05:20:11.08#ibcon#end of sib2, iclass 19, count 0 2006.257.05:20:11.08#ibcon#*after write, iclass 19, count 0 2006.257.05:20:11.08#ibcon#*before return 0, iclass 19, count 0 2006.257.05:20:11.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:11.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:20:11.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.05:20:11.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.05:20:11.08$vck44/vb=4,5 2006.257.05:20:11.08#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.05:20:11.08#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.05:20:11.08#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:11.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:20:11.12#abcon#<5=/16 1.3 3.2 19.90 911012.2\r\n> 2006.257.05:20:11.14#abcon#{5=INTERFACE CLEAR} 2006.257.05:20:11.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:20:11.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:20:11.14#ibcon#enter wrdev, iclass 22, count 2 2006.257.05:20:11.14#ibcon#first serial, iclass 22, count 2 2006.257.05:20:11.14#ibcon#enter sib2, iclass 22, count 2 2006.257.05:20:11.14#ibcon#flushed, iclass 22, count 2 2006.257.05:20:11.14#ibcon#about to write, iclass 22, count 2 2006.257.05:20:11.14#ibcon#wrote, iclass 22, count 2 2006.257.05:20:11.14#ibcon#about to read 3, iclass 22, count 2 2006.257.05:20:11.16#ibcon#read 3, iclass 22, count 2 2006.257.05:20:11.16#ibcon#about to read 4, iclass 22, count 2 2006.257.05:20:11.16#ibcon#read 4, iclass 22, count 2 2006.257.05:20:11.16#ibcon#about to read 5, iclass 22, count 2 2006.257.05:20:11.16#ibcon#read 5, iclass 22, count 2 2006.257.05:20:11.16#ibcon#about to read 6, iclass 22, count 2 2006.257.05:20:11.16#ibcon#read 6, iclass 22, count 2 2006.257.05:20:11.16#ibcon#end of sib2, iclass 22, count 2 2006.257.05:20:11.16#ibcon#*mode == 0, iclass 22, count 2 2006.257.05:20:11.16#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.05:20:11.16#ibcon#[27=AT04-05\r\n] 2006.257.05:20:11.16#ibcon#*before write, iclass 22, count 2 2006.257.05:20:11.16#ibcon#enter sib2, iclass 22, count 2 2006.257.05:20:11.16#ibcon#flushed, iclass 22, count 2 2006.257.05:20:11.16#ibcon#about to write, iclass 22, count 2 2006.257.05:20:11.16#ibcon#wrote, iclass 22, count 2 2006.257.05:20:11.16#ibcon#about to read 3, iclass 22, count 2 2006.257.05:20:11.19#ibcon#read 3, iclass 22, count 2 2006.257.05:20:11.19#ibcon#about to read 4, iclass 22, count 2 2006.257.05:20:11.19#ibcon#read 4, iclass 22, count 2 2006.257.05:20:11.19#ibcon#about to read 5, iclass 22, count 2 2006.257.05:20:11.19#ibcon#read 5, iclass 22, count 2 2006.257.05:20:11.19#ibcon#about to read 6, iclass 22, count 2 2006.257.05:20:11.19#ibcon#read 6, iclass 22, count 2 2006.257.05:20:11.19#ibcon#end of sib2, iclass 22, count 2 2006.257.05:20:11.19#ibcon#*after write, iclass 22, count 2 2006.257.05:20:11.19#ibcon#*before return 0, iclass 22, count 2 2006.257.05:20:11.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:20:11.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:20:11.19#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.05:20:11.19#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:11.19#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:20:11.20#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:20:11.31#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:20:11.31#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:20:11.31#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:20:11.31#ibcon#first serial, iclass 22, count 0 2006.257.05:20:11.31#ibcon#enter sib2, iclass 22, count 0 2006.257.05:20:11.31#ibcon#flushed, iclass 22, count 0 2006.257.05:20:11.31#ibcon#about to write, iclass 22, count 0 2006.257.05:20:11.31#ibcon#wrote, iclass 22, count 0 2006.257.05:20:11.31#ibcon#about to read 3, iclass 22, count 0 2006.257.05:20:11.33#ibcon#read 3, iclass 22, count 0 2006.257.05:20:11.33#ibcon#about to read 4, iclass 22, count 0 2006.257.05:20:11.33#ibcon#read 4, iclass 22, count 0 2006.257.05:20:11.33#ibcon#about to read 5, iclass 22, count 0 2006.257.05:20:11.33#ibcon#read 5, iclass 22, count 0 2006.257.05:20:11.33#ibcon#about to read 6, iclass 22, count 0 2006.257.05:20:11.33#ibcon#read 6, iclass 22, count 0 2006.257.05:20:11.33#ibcon#end of sib2, iclass 22, count 0 2006.257.05:20:11.33#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:20:11.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:20:11.33#ibcon#[27=USB\r\n] 2006.257.05:20:11.33#ibcon#*before write, iclass 22, count 0 2006.257.05:20:11.33#ibcon#enter sib2, iclass 22, count 0 2006.257.05:20:11.33#ibcon#flushed, iclass 22, count 0 2006.257.05:20:11.33#ibcon#about to write, iclass 22, count 0 2006.257.05:20:11.33#ibcon#wrote, iclass 22, count 0 2006.257.05:20:11.33#ibcon#about to read 3, iclass 22, count 0 2006.257.05:20:11.36#ibcon#read 3, iclass 22, count 0 2006.257.05:20:11.36#ibcon#about to read 4, iclass 22, count 0 2006.257.05:20:11.36#ibcon#read 4, iclass 22, count 0 2006.257.05:20:11.36#ibcon#about to read 5, iclass 22, count 0 2006.257.05:20:11.36#ibcon#read 5, iclass 22, count 0 2006.257.05:20:11.36#ibcon#about to read 6, iclass 22, count 0 2006.257.05:20:11.36#ibcon#read 6, iclass 22, count 0 2006.257.05:20:11.36#ibcon#end of sib2, iclass 22, count 0 2006.257.05:20:11.36#ibcon#*after write, iclass 22, count 0 2006.257.05:20:11.36#ibcon#*before return 0, iclass 22, count 0 2006.257.05:20:11.36#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:20:11.36#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:20:11.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:20:11.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:20:11.36$vck44/vblo=5,709.99 2006.257.05:20:11.36#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.05:20:11.36#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.05:20:11.36#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:11.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:11.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:11.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:11.36#ibcon#enter wrdev, iclass 27, count 0 2006.257.05:20:11.36#ibcon#first serial, iclass 27, count 0 2006.257.05:20:11.36#ibcon#enter sib2, iclass 27, count 0 2006.257.05:20:11.36#ibcon#flushed, iclass 27, count 0 2006.257.05:20:11.36#ibcon#about to write, iclass 27, count 0 2006.257.05:20:11.36#ibcon#wrote, iclass 27, count 0 2006.257.05:20:11.36#ibcon#about to read 3, iclass 27, count 0 2006.257.05:20:11.38#ibcon#read 3, iclass 27, count 0 2006.257.05:20:11.38#ibcon#about to read 4, iclass 27, count 0 2006.257.05:20:11.38#ibcon#read 4, iclass 27, count 0 2006.257.05:20:11.38#ibcon#about to read 5, iclass 27, count 0 2006.257.05:20:11.38#ibcon#read 5, iclass 27, count 0 2006.257.05:20:11.38#ibcon#about to read 6, iclass 27, count 0 2006.257.05:20:11.38#ibcon#read 6, iclass 27, count 0 2006.257.05:20:11.38#ibcon#end of sib2, iclass 27, count 0 2006.257.05:20:11.38#ibcon#*mode == 0, iclass 27, count 0 2006.257.05:20:11.38#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.05:20:11.38#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:20:11.38#ibcon#*before write, iclass 27, count 0 2006.257.05:20:11.38#ibcon#enter sib2, iclass 27, count 0 2006.257.05:20:11.38#ibcon#flushed, iclass 27, count 0 2006.257.05:20:11.38#ibcon#about to write, iclass 27, count 0 2006.257.05:20:11.38#ibcon#wrote, iclass 27, count 0 2006.257.05:20:11.38#ibcon#about to read 3, iclass 27, count 0 2006.257.05:20:11.42#ibcon#read 3, iclass 27, count 0 2006.257.05:20:11.42#ibcon#about to read 4, iclass 27, count 0 2006.257.05:20:11.42#ibcon#read 4, iclass 27, count 0 2006.257.05:20:11.42#ibcon#about to read 5, iclass 27, count 0 2006.257.05:20:11.42#ibcon#read 5, iclass 27, count 0 2006.257.05:20:11.42#ibcon#about to read 6, iclass 27, count 0 2006.257.05:20:11.42#ibcon#read 6, iclass 27, count 0 2006.257.05:20:11.42#ibcon#end of sib2, iclass 27, count 0 2006.257.05:20:11.42#ibcon#*after write, iclass 27, count 0 2006.257.05:20:11.42#ibcon#*before return 0, iclass 27, count 0 2006.257.05:20:11.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:11.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:20:11.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.05:20:11.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.05:20:11.42$vck44/vb=5,4 2006.257.05:20:11.42#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.05:20:11.42#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.05:20:11.42#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:11.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:11.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:11.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:11.48#ibcon#enter wrdev, iclass 29, count 2 2006.257.05:20:11.48#ibcon#first serial, iclass 29, count 2 2006.257.05:20:11.48#ibcon#enter sib2, iclass 29, count 2 2006.257.05:20:11.48#ibcon#flushed, iclass 29, count 2 2006.257.05:20:11.48#ibcon#about to write, iclass 29, count 2 2006.257.05:20:11.48#ibcon#wrote, iclass 29, count 2 2006.257.05:20:11.48#ibcon#about to read 3, iclass 29, count 2 2006.257.05:20:11.50#ibcon#read 3, iclass 29, count 2 2006.257.05:20:11.50#ibcon#about to read 4, iclass 29, count 2 2006.257.05:20:11.50#ibcon#read 4, iclass 29, count 2 2006.257.05:20:11.50#ibcon#about to read 5, iclass 29, count 2 2006.257.05:20:11.50#ibcon#read 5, iclass 29, count 2 2006.257.05:20:11.50#ibcon#about to read 6, iclass 29, count 2 2006.257.05:20:11.50#ibcon#read 6, iclass 29, count 2 2006.257.05:20:11.50#ibcon#end of sib2, iclass 29, count 2 2006.257.05:20:11.50#ibcon#*mode == 0, iclass 29, count 2 2006.257.05:20:11.50#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.05:20:11.50#ibcon#[27=AT05-04\r\n] 2006.257.05:20:11.50#ibcon#*before write, iclass 29, count 2 2006.257.05:20:11.50#ibcon#enter sib2, iclass 29, count 2 2006.257.05:20:11.50#ibcon#flushed, iclass 29, count 2 2006.257.05:20:11.50#ibcon#about to write, iclass 29, count 2 2006.257.05:20:11.50#ibcon#wrote, iclass 29, count 2 2006.257.05:20:11.50#ibcon#about to read 3, iclass 29, count 2 2006.257.05:20:11.53#ibcon#read 3, iclass 29, count 2 2006.257.05:20:11.53#ibcon#about to read 4, iclass 29, count 2 2006.257.05:20:11.53#ibcon#read 4, iclass 29, count 2 2006.257.05:20:11.53#ibcon#about to read 5, iclass 29, count 2 2006.257.05:20:11.53#ibcon#read 5, iclass 29, count 2 2006.257.05:20:11.53#ibcon#about to read 6, iclass 29, count 2 2006.257.05:20:11.53#ibcon#read 6, iclass 29, count 2 2006.257.05:20:11.53#ibcon#end of sib2, iclass 29, count 2 2006.257.05:20:11.53#ibcon#*after write, iclass 29, count 2 2006.257.05:20:11.53#ibcon#*before return 0, iclass 29, count 2 2006.257.05:20:11.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:11.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:20:11.53#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.05:20:11.53#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:11.53#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:11.65#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:11.65#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:11.65#ibcon#enter wrdev, iclass 29, count 0 2006.257.05:20:11.65#ibcon#first serial, iclass 29, count 0 2006.257.05:20:11.65#ibcon#enter sib2, iclass 29, count 0 2006.257.05:20:11.65#ibcon#flushed, iclass 29, count 0 2006.257.05:20:11.65#ibcon#about to write, iclass 29, count 0 2006.257.05:20:11.65#ibcon#wrote, iclass 29, count 0 2006.257.05:20:11.65#ibcon#about to read 3, iclass 29, count 0 2006.257.05:20:11.67#ibcon#read 3, iclass 29, count 0 2006.257.05:20:11.67#ibcon#about to read 4, iclass 29, count 0 2006.257.05:20:11.67#ibcon#read 4, iclass 29, count 0 2006.257.05:20:11.67#ibcon#about to read 5, iclass 29, count 0 2006.257.05:20:11.67#ibcon#read 5, iclass 29, count 0 2006.257.05:20:11.67#ibcon#about to read 6, iclass 29, count 0 2006.257.05:20:11.67#ibcon#read 6, iclass 29, count 0 2006.257.05:20:11.67#ibcon#end of sib2, iclass 29, count 0 2006.257.05:20:11.67#ibcon#*mode == 0, iclass 29, count 0 2006.257.05:20:11.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.05:20:11.67#ibcon#[27=USB\r\n] 2006.257.05:20:11.67#ibcon#*before write, iclass 29, count 0 2006.257.05:20:11.67#ibcon#enter sib2, iclass 29, count 0 2006.257.05:20:11.67#ibcon#flushed, iclass 29, count 0 2006.257.05:20:11.67#ibcon#about to write, iclass 29, count 0 2006.257.05:20:11.67#ibcon#wrote, iclass 29, count 0 2006.257.05:20:11.67#ibcon#about to read 3, iclass 29, count 0 2006.257.05:20:11.70#ibcon#read 3, iclass 29, count 0 2006.257.05:20:11.70#ibcon#about to read 4, iclass 29, count 0 2006.257.05:20:11.70#ibcon#read 4, iclass 29, count 0 2006.257.05:20:11.70#ibcon#about to read 5, iclass 29, count 0 2006.257.05:20:11.70#ibcon#read 5, iclass 29, count 0 2006.257.05:20:11.70#ibcon#about to read 6, iclass 29, count 0 2006.257.05:20:11.70#ibcon#read 6, iclass 29, count 0 2006.257.05:20:11.70#ibcon#end of sib2, iclass 29, count 0 2006.257.05:20:11.70#ibcon#*after write, iclass 29, count 0 2006.257.05:20:11.70#ibcon#*before return 0, iclass 29, count 0 2006.257.05:20:11.70#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:11.70#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:20:11.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.05:20:11.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.05:20:11.70$vck44/vblo=6,719.99 2006.257.05:20:11.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.05:20:11.70#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.05:20:11.70#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:11.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:11.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:11.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:11.70#ibcon#enter wrdev, iclass 31, count 0 2006.257.05:20:11.70#ibcon#first serial, iclass 31, count 0 2006.257.05:20:11.70#ibcon#enter sib2, iclass 31, count 0 2006.257.05:20:11.70#ibcon#flushed, iclass 31, count 0 2006.257.05:20:11.70#ibcon#about to write, iclass 31, count 0 2006.257.05:20:11.70#ibcon#wrote, iclass 31, count 0 2006.257.05:20:11.70#ibcon#about to read 3, iclass 31, count 0 2006.257.05:20:11.72#ibcon#read 3, iclass 31, count 0 2006.257.05:20:11.72#ibcon#about to read 4, iclass 31, count 0 2006.257.05:20:11.72#ibcon#read 4, iclass 31, count 0 2006.257.05:20:11.72#ibcon#about to read 5, iclass 31, count 0 2006.257.05:20:11.72#ibcon#read 5, iclass 31, count 0 2006.257.05:20:11.72#ibcon#about to read 6, iclass 31, count 0 2006.257.05:20:11.72#ibcon#read 6, iclass 31, count 0 2006.257.05:20:11.72#ibcon#end of sib2, iclass 31, count 0 2006.257.05:20:11.72#ibcon#*mode == 0, iclass 31, count 0 2006.257.05:20:11.72#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.05:20:11.72#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:20:11.72#ibcon#*before write, iclass 31, count 0 2006.257.05:20:11.72#ibcon#enter sib2, iclass 31, count 0 2006.257.05:20:11.72#ibcon#flushed, iclass 31, count 0 2006.257.05:20:11.72#ibcon#about to write, iclass 31, count 0 2006.257.05:20:11.72#ibcon#wrote, iclass 31, count 0 2006.257.05:20:11.72#ibcon#about to read 3, iclass 31, count 0 2006.257.05:20:11.76#ibcon#read 3, iclass 31, count 0 2006.257.05:20:11.76#ibcon#about to read 4, iclass 31, count 0 2006.257.05:20:11.76#ibcon#read 4, iclass 31, count 0 2006.257.05:20:11.76#ibcon#about to read 5, iclass 31, count 0 2006.257.05:20:11.76#ibcon#read 5, iclass 31, count 0 2006.257.05:20:11.76#ibcon#about to read 6, iclass 31, count 0 2006.257.05:20:11.76#ibcon#read 6, iclass 31, count 0 2006.257.05:20:11.76#ibcon#end of sib2, iclass 31, count 0 2006.257.05:20:11.76#ibcon#*after write, iclass 31, count 0 2006.257.05:20:11.76#ibcon#*before return 0, iclass 31, count 0 2006.257.05:20:11.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:11.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:20:11.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.05:20:11.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.05:20:11.76$vck44/vb=6,4 2006.257.05:20:11.76#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.05:20:11.76#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.05:20:11.76#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:11.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:11.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:11.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:11.82#ibcon#enter wrdev, iclass 33, count 2 2006.257.05:20:11.82#ibcon#first serial, iclass 33, count 2 2006.257.05:20:11.82#ibcon#enter sib2, iclass 33, count 2 2006.257.05:20:11.82#ibcon#flushed, iclass 33, count 2 2006.257.05:20:11.82#ibcon#about to write, iclass 33, count 2 2006.257.05:20:11.82#ibcon#wrote, iclass 33, count 2 2006.257.05:20:11.82#ibcon#about to read 3, iclass 33, count 2 2006.257.05:20:11.84#ibcon#read 3, iclass 33, count 2 2006.257.05:20:11.84#ibcon#about to read 4, iclass 33, count 2 2006.257.05:20:11.84#ibcon#read 4, iclass 33, count 2 2006.257.05:20:11.84#ibcon#about to read 5, iclass 33, count 2 2006.257.05:20:11.84#ibcon#read 5, iclass 33, count 2 2006.257.05:20:11.84#ibcon#about to read 6, iclass 33, count 2 2006.257.05:20:11.84#ibcon#read 6, iclass 33, count 2 2006.257.05:20:11.84#ibcon#end of sib2, iclass 33, count 2 2006.257.05:20:11.84#ibcon#*mode == 0, iclass 33, count 2 2006.257.05:20:11.84#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.05:20:11.84#ibcon#[27=AT06-04\r\n] 2006.257.05:20:11.84#ibcon#*before write, iclass 33, count 2 2006.257.05:20:11.84#ibcon#enter sib2, iclass 33, count 2 2006.257.05:20:11.84#ibcon#flushed, iclass 33, count 2 2006.257.05:20:11.84#ibcon#about to write, iclass 33, count 2 2006.257.05:20:11.84#ibcon#wrote, iclass 33, count 2 2006.257.05:20:11.84#ibcon#about to read 3, iclass 33, count 2 2006.257.05:20:11.87#ibcon#read 3, iclass 33, count 2 2006.257.05:20:11.87#ibcon#about to read 4, iclass 33, count 2 2006.257.05:20:11.87#ibcon#read 4, iclass 33, count 2 2006.257.05:20:11.87#ibcon#about to read 5, iclass 33, count 2 2006.257.05:20:11.87#ibcon#read 5, iclass 33, count 2 2006.257.05:20:11.87#ibcon#about to read 6, iclass 33, count 2 2006.257.05:20:11.87#ibcon#read 6, iclass 33, count 2 2006.257.05:20:11.87#ibcon#end of sib2, iclass 33, count 2 2006.257.05:20:11.87#ibcon#*after write, iclass 33, count 2 2006.257.05:20:11.87#ibcon#*before return 0, iclass 33, count 2 2006.257.05:20:11.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:11.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:20:11.87#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.05:20:11.87#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:11.87#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:11.99#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:11.99#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:11.99#ibcon#enter wrdev, iclass 33, count 0 2006.257.05:20:11.99#ibcon#first serial, iclass 33, count 0 2006.257.05:20:11.99#ibcon#enter sib2, iclass 33, count 0 2006.257.05:20:11.99#ibcon#flushed, iclass 33, count 0 2006.257.05:20:11.99#ibcon#about to write, iclass 33, count 0 2006.257.05:20:11.99#ibcon#wrote, iclass 33, count 0 2006.257.05:20:11.99#ibcon#about to read 3, iclass 33, count 0 2006.257.05:20:12.01#ibcon#read 3, iclass 33, count 0 2006.257.05:20:12.01#ibcon#about to read 4, iclass 33, count 0 2006.257.05:20:12.01#ibcon#read 4, iclass 33, count 0 2006.257.05:20:12.01#ibcon#about to read 5, iclass 33, count 0 2006.257.05:20:12.01#ibcon#read 5, iclass 33, count 0 2006.257.05:20:12.01#ibcon#about to read 6, iclass 33, count 0 2006.257.05:20:12.01#ibcon#read 6, iclass 33, count 0 2006.257.05:20:12.01#ibcon#end of sib2, iclass 33, count 0 2006.257.05:20:12.01#ibcon#*mode == 0, iclass 33, count 0 2006.257.05:20:12.01#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.05:20:12.01#ibcon#[27=USB\r\n] 2006.257.05:20:12.01#ibcon#*before write, iclass 33, count 0 2006.257.05:20:12.01#ibcon#enter sib2, iclass 33, count 0 2006.257.05:20:12.01#ibcon#flushed, iclass 33, count 0 2006.257.05:20:12.01#ibcon#about to write, iclass 33, count 0 2006.257.05:20:12.01#ibcon#wrote, iclass 33, count 0 2006.257.05:20:12.01#ibcon#about to read 3, iclass 33, count 0 2006.257.05:20:12.04#ibcon#read 3, iclass 33, count 0 2006.257.05:20:12.04#ibcon#about to read 4, iclass 33, count 0 2006.257.05:20:12.04#ibcon#read 4, iclass 33, count 0 2006.257.05:20:12.04#ibcon#about to read 5, iclass 33, count 0 2006.257.05:20:12.04#ibcon#read 5, iclass 33, count 0 2006.257.05:20:12.04#ibcon#about to read 6, iclass 33, count 0 2006.257.05:20:12.04#ibcon#read 6, iclass 33, count 0 2006.257.05:20:12.04#ibcon#end of sib2, iclass 33, count 0 2006.257.05:20:12.04#ibcon#*after write, iclass 33, count 0 2006.257.05:20:12.04#ibcon#*before return 0, iclass 33, count 0 2006.257.05:20:12.04#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:12.04#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:20:12.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.05:20:12.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.05:20:12.04$vck44/vblo=7,734.99 2006.257.05:20:12.04#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.05:20:12.04#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.05:20:12.04#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:12.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:12.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:12.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:12.04#ibcon#enter wrdev, iclass 35, count 0 2006.257.05:20:12.04#ibcon#first serial, iclass 35, count 0 2006.257.05:20:12.04#ibcon#enter sib2, iclass 35, count 0 2006.257.05:20:12.04#ibcon#flushed, iclass 35, count 0 2006.257.05:20:12.04#ibcon#about to write, iclass 35, count 0 2006.257.05:20:12.04#ibcon#wrote, iclass 35, count 0 2006.257.05:20:12.04#ibcon#about to read 3, iclass 35, count 0 2006.257.05:20:12.06#ibcon#read 3, iclass 35, count 0 2006.257.05:20:12.06#ibcon#about to read 4, iclass 35, count 0 2006.257.05:20:12.06#ibcon#read 4, iclass 35, count 0 2006.257.05:20:12.06#ibcon#about to read 5, iclass 35, count 0 2006.257.05:20:12.06#ibcon#read 5, iclass 35, count 0 2006.257.05:20:12.06#ibcon#about to read 6, iclass 35, count 0 2006.257.05:20:12.06#ibcon#read 6, iclass 35, count 0 2006.257.05:20:12.06#ibcon#end of sib2, iclass 35, count 0 2006.257.05:20:12.06#ibcon#*mode == 0, iclass 35, count 0 2006.257.05:20:12.06#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.05:20:12.06#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:20:12.06#ibcon#*before write, iclass 35, count 0 2006.257.05:20:12.06#ibcon#enter sib2, iclass 35, count 0 2006.257.05:20:12.06#ibcon#flushed, iclass 35, count 0 2006.257.05:20:12.06#ibcon#about to write, iclass 35, count 0 2006.257.05:20:12.06#ibcon#wrote, iclass 35, count 0 2006.257.05:20:12.06#ibcon#about to read 3, iclass 35, count 0 2006.257.05:20:12.10#ibcon#read 3, iclass 35, count 0 2006.257.05:20:12.10#ibcon#about to read 4, iclass 35, count 0 2006.257.05:20:12.10#ibcon#read 4, iclass 35, count 0 2006.257.05:20:12.10#ibcon#about to read 5, iclass 35, count 0 2006.257.05:20:12.10#ibcon#read 5, iclass 35, count 0 2006.257.05:20:12.10#ibcon#about to read 6, iclass 35, count 0 2006.257.05:20:12.10#ibcon#read 6, iclass 35, count 0 2006.257.05:20:12.10#ibcon#end of sib2, iclass 35, count 0 2006.257.05:20:12.10#ibcon#*after write, iclass 35, count 0 2006.257.05:20:12.10#ibcon#*before return 0, iclass 35, count 0 2006.257.05:20:12.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:12.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:20:12.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.05:20:12.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.05:20:12.10$vck44/vb=7,4 2006.257.05:20:12.10#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.05:20:12.10#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.05:20:12.10#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:12.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:12.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:12.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:12.16#ibcon#enter wrdev, iclass 37, count 2 2006.257.05:20:12.16#ibcon#first serial, iclass 37, count 2 2006.257.05:20:12.16#ibcon#enter sib2, iclass 37, count 2 2006.257.05:20:12.16#ibcon#flushed, iclass 37, count 2 2006.257.05:20:12.16#ibcon#about to write, iclass 37, count 2 2006.257.05:20:12.16#ibcon#wrote, iclass 37, count 2 2006.257.05:20:12.16#ibcon#about to read 3, iclass 37, count 2 2006.257.05:20:12.18#ibcon#read 3, iclass 37, count 2 2006.257.05:20:12.18#ibcon#about to read 4, iclass 37, count 2 2006.257.05:20:12.18#ibcon#read 4, iclass 37, count 2 2006.257.05:20:12.18#ibcon#about to read 5, iclass 37, count 2 2006.257.05:20:12.18#ibcon#read 5, iclass 37, count 2 2006.257.05:20:12.18#ibcon#about to read 6, iclass 37, count 2 2006.257.05:20:12.18#ibcon#read 6, iclass 37, count 2 2006.257.05:20:12.18#ibcon#end of sib2, iclass 37, count 2 2006.257.05:20:12.18#ibcon#*mode == 0, iclass 37, count 2 2006.257.05:20:12.18#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.05:20:12.18#ibcon#[27=AT07-04\r\n] 2006.257.05:20:12.18#ibcon#*before write, iclass 37, count 2 2006.257.05:20:12.18#ibcon#enter sib2, iclass 37, count 2 2006.257.05:20:12.18#ibcon#flushed, iclass 37, count 2 2006.257.05:20:12.18#ibcon#about to write, iclass 37, count 2 2006.257.05:20:12.18#ibcon#wrote, iclass 37, count 2 2006.257.05:20:12.18#ibcon#about to read 3, iclass 37, count 2 2006.257.05:20:12.21#ibcon#read 3, iclass 37, count 2 2006.257.05:20:12.21#ibcon#about to read 4, iclass 37, count 2 2006.257.05:20:12.21#ibcon#read 4, iclass 37, count 2 2006.257.05:20:12.21#ibcon#about to read 5, iclass 37, count 2 2006.257.05:20:12.21#ibcon#read 5, iclass 37, count 2 2006.257.05:20:12.21#ibcon#about to read 6, iclass 37, count 2 2006.257.05:20:12.21#ibcon#read 6, iclass 37, count 2 2006.257.05:20:12.21#ibcon#end of sib2, iclass 37, count 2 2006.257.05:20:12.21#ibcon#*after write, iclass 37, count 2 2006.257.05:20:12.21#ibcon#*before return 0, iclass 37, count 2 2006.257.05:20:12.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:12.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:20:12.21#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.05:20:12.21#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:12.21#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:12.33#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:12.33#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:12.33#ibcon#enter wrdev, iclass 37, count 0 2006.257.05:20:12.33#ibcon#first serial, iclass 37, count 0 2006.257.05:20:12.33#ibcon#enter sib2, iclass 37, count 0 2006.257.05:20:12.33#ibcon#flushed, iclass 37, count 0 2006.257.05:20:12.33#ibcon#about to write, iclass 37, count 0 2006.257.05:20:12.33#ibcon#wrote, iclass 37, count 0 2006.257.05:20:12.33#ibcon#about to read 3, iclass 37, count 0 2006.257.05:20:12.35#ibcon#read 3, iclass 37, count 0 2006.257.05:20:12.35#ibcon#about to read 4, iclass 37, count 0 2006.257.05:20:12.35#ibcon#read 4, iclass 37, count 0 2006.257.05:20:12.35#ibcon#about to read 5, iclass 37, count 0 2006.257.05:20:12.35#ibcon#read 5, iclass 37, count 0 2006.257.05:20:12.35#ibcon#about to read 6, iclass 37, count 0 2006.257.05:20:12.35#ibcon#read 6, iclass 37, count 0 2006.257.05:20:12.35#ibcon#end of sib2, iclass 37, count 0 2006.257.05:20:12.35#ibcon#*mode == 0, iclass 37, count 0 2006.257.05:20:12.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.05:20:12.35#ibcon#[27=USB\r\n] 2006.257.05:20:12.35#ibcon#*before write, iclass 37, count 0 2006.257.05:20:12.35#ibcon#enter sib2, iclass 37, count 0 2006.257.05:20:12.35#ibcon#flushed, iclass 37, count 0 2006.257.05:20:12.35#ibcon#about to write, iclass 37, count 0 2006.257.05:20:12.35#ibcon#wrote, iclass 37, count 0 2006.257.05:20:12.35#ibcon#about to read 3, iclass 37, count 0 2006.257.05:20:12.38#ibcon#read 3, iclass 37, count 0 2006.257.05:20:12.38#ibcon#about to read 4, iclass 37, count 0 2006.257.05:20:12.38#ibcon#read 4, iclass 37, count 0 2006.257.05:20:12.38#ibcon#about to read 5, iclass 37, count 0 2006.257.05:20:12.38#ibcon#read 5, iclass 37, count 0 2006.257.05:20:12.38#ibcon#about to read 6, iclass 37, count 0 2006.257.05:20:12.38#ibcon#read 6, iclass 37, count 0 2006.257.05:20:12.38#ibcon#end of sib2, iclass 37, count 0 2006.257.05:20:12.38#ibcon#*after write, iclass 37, count 0 2006.257.05:20:12.38#ibcon#*before return 0, iclass 37, count 0 2006.257.05:20:12.38#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:12.38#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:20:12.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.05:20:12.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.05:20:12.38$vck44/vblo=8,744.99 2006.257.05:20:12.38#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.05:20:12.38#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.05:20:12.38#ibcon#ireg 17 cls_cnt 0 2006.257.05:20:12.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:12.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:12.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:12.38#ibcon#enter wrdev, iclass 39, count 0 2006.257.05:20:12.38#ibcon#first serial, iclass 39, count 0 2006.257.05:20:12.38#ibcon#enter sib2, iclass 39, count 0 2006.257.05:20:12.38#ibcon#flushed, iclass 39, count 0 2006.257.05:20:12.38#ibcon#about to write, iclass 39, count 0 2006.257.05:20:12.38#ibcon#wrote, iclass 39, count 0 2006.257.05:20:12.38#ibcon#about to read 3, iclass 39, count 0 2006.257.05:20:12.40#ibcon#read 3, iclass 39, count 0 2006.257.05:20:12.40#ibcon#about to read 4, iclass 39, count 0 2006.257.05:20:12.40#ibcon#read 4, iclass 39, count 0 2006.257.05:20:12.40#ibcon#about to read 5, iclass 39, count 0 2006.257.05:20:12.40#ibcon#read 5, iclass 39, count 0 2006.257.05:20:12.40#ibcon#about to read 6, iclass 39, count 0 2006.257.05:20:12.40#ibcon#read 6, iclass 39, count 0 2006.257.05:20:12.40#ibcon#end of sib2, iclass 39, count 0 2006.257.05:20:12.40#ibcon#*mode == 0, iclass 39, count 0 2006.257.05:20:12.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.05:20:12.40#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:20:12.40#ibcon#*before write, iclass 39, count 0 2006.257.05:20:12.40#ibcon#enter sib2, iclass 39, count 0 2006.257.05:20:12.40#ibcon#flushed, iclass 39, count 0 2006.257.05:20:12.40#ibcon#about to write, iclass 39, count 0 2006.257.05:20:12.40#ibcon#wrote, iclass 39, count 0 2006.257.05:20:12.40#ibcon#about to read 3, iclass 39, count 0 2006.257.05:20:12.44#ibcon#read 3, iclass 39, count 0 2006.257.05:20:12.44#ibcon#about to read 4, iclass 39, count 0 2006.257.05:20:12.44#ibcon#read 4, iclass 39, count 0 2006.257.05:20:12.44#ibcon#about to read 5, iclass 39, count 0 2006.257.05:20:12.44#ibcon#read 5, iclass 39, count 0 2006.257.05:20:12.44#ibcon#about to read 6, iclass 39, count 0 2006.257.05:20:12.44#ibcon#read 6, iclass 39, count 0 2006.257.05:20:12.44#ibcon#end of sib2, iclass 39, count 0 2006.257.05:20:12.44#ibcon#*after write, iclass 39, count 0 2006.257.05:20:12.44#ibcon#*before return 0, iclass 39, count 0 2006.257.05:20:12.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:12.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:20:12.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.05:20:12.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.05:20:12.44$vck44/vb=8,4 2006.257.05:20:12.44#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.05:20:12.44#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.05:20:12.44#ibcon#ireg 11 cls_cnt 2 2006.257.05:20:12.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:12.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:12.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:12.50#ibcon#enter wrdev, iclass 3, count 2 2006.257.05:20:12.50#ibcon#first serial, iclass 3, count 2 2006.257.05:20:12.50#ibcon#enter sib2, iclass 3, count 2 2006.257.05:20:12.50#ibcon#flushed, iclass 3, count 2 2006.257.05:20:12.50#ibcon#about to write, iclass 3, count 2 2006.257.05:20:12.50#ibcon#wrote, iclass 3, count 2 2006.257.05:20:12.50#ibcon#about to read 3, iclass 3, count 2 2006.257.05:20:12.52#ibcon#read 3, iclass 3, count 2 2006.257.05:20:12.52#ibcon#about to read 4, iclass 3, count 2 2006.257.05:20:12.52#ibcon#read 4, iclass 3, count 2 2006.257.05:20:12.52#ibcon#about to read 5, iclass 3, count 2 2006.257.05:20:12.52#ibcon#read 5, iclass 3, count 2 2006.257.05:20:12.52#ibcon#about to read 6, iclass 3, count 2 2006.257.05:20:12.52#ibcon#read 6, iclass 3, count 2 2006.257.05:20:12.52#ibcon#end of sib2, iclass 3, count 2 2006.257.05:20:12.52#ibcon#*mode == 0, iclass 3, count 2 2006.257.05:20:12.52#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.05:20:12.52#ibcon#[27=AT08-04\r\n] 2006.257.05:20:12.52#ibcon#*before write, iclass 3, count 2 2006.257.05:20:12.52#ibcon#enter sib2, iclass 3, count 2 2006.257.05:20:12.52#ibcon#flushed, iclass 3, count 2 2006.257.05:20:12.52#ibcon#about to write, iclass 3, count 2 2006.257.05:20:12.52#ibcon#wrote, iclass 3, count 2 2006.257.05:20:12.52#ibcon#about to read 3, iclass 3, count 2 2006.257.05:20:12.55#ibcon#read 3, iclass 3, count 2 2006.257.05:20:12.55#ibcon#about to read 4, iclass 3, count 2 2006.257.05:20:12.55#ibcon#read 4, iclass 3, count 2 2006.257.05:20:12.55#ibcon#about to read 5, iclass 3, count 2 2006.257.05:20:12.55#ibcon#read 5, iclass 3, count 2 2006.257.05:20:12.55#ibcon#about to read 6, iclass 3, count 2 2006.257.05:20:12.55#ibcon#read 6, iclass 3, count 2 2006.257.05:20:12.55#ibcon#end of sib2, iclass 3, count 2 2006.257.05:20:12.55#ibcon#*after write, iclass 3, count 2 2006.257.05:20:12.55#ibcon#*before return 0, iclass 3, count 2 2006.257.05:20:12.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:12.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:20:12.55#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.05:20:12.55#ibcon#ireg 7 cls_cnt 0 2006.257.05:20:12.55#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:12.67#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:12.67#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:12.67#ibcon#enter wrdev, iclass 3, count 0 2006.257.05:20:12.67#ibcon#first serial, iclass 3, count 0 2006.257.05:20:12.67#ibcon#enter sib2, iclass 3, count 0 2006.257.05:20:12.67#ibcon#flushed, iclass 3, count 0 2006.257.05:20:12.67#ibcon#about to write, iclass 3, count 0 2006.257.05:20:12.67#ibcon#wrote, iclass 3, count 0 2006.257.05:20:12.67#ibcon#about to read 3, iclass 3, count 0 2006.257.05:20:12.69#ibcon#read 3, iclass 3, count 0 2006.257.05:20:12.69#ibcon#about to read 4, iclass 3, count 0 2006.257.05:20:12.69#ibcon#read 4, iclass 3, count 0 2006.257.05:20:12.69#ibcon#about to read 5, iclass 3, count 0 2006.257.05:20:12.69#ibcon#read 5, iclass 3, count 0 2006.257.05:20:12.69#ibcon#about to read 6, iclass 3, count 0 2006.257.05:20:12.69#ibcon#read 6, iclass 3, count 0 2006.257.05:20:12.69#ibcon#end of sib2, iclass 3, count 0 2006.257.05:20:12.69#ibcon#*mode == 0, iclass 3, count 0 2006.257.05:20:12.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.05:20:12.69#ibcon#[27=USB\r\n] 2006.257.05:20:12.69#ibcon#*before write, iclass 3, count 0 2006.257.05:20:12.69#ibcon#enter sib2, iclass 3, count 0 2006.257.05:20:12.69#ibcon#flushed, iclass 3, count 0 2006.257.05:20:12.69#ibcon#about to write, iclass 3, count 0 2006.257.05:20:12.69#ibcon#wrote, iclass 3, count 0 2006.257.05:20:12.69#ibcon#about to read 3, iclass 3, count 0 2006.257.05:20:12.72#ibcon#read 3, iclass 3, count 0 2006.257.05:20:12.72#ibcon#about to read 4, iclass 3, count 0 2006.257.05:20:12.72#ibcon#read 4, iclass 3, count 0 2006.257.05:20:12.72#ibcon#about to read 5, iclass 3, count 0 2006.257.05:20:12.72#ibcon#read 5, iclass 3, count 0 2006.257.05:20:12.72#ibcon#about to read 6, iclass 3, count 0 2006.257.05:20:12.72#ibcon#read 6, iclass 3, count 0 2006.257.05:20:12.72#ibcon#end of sib2, iclass 3, count 0 2006.257.05:20:12.72#ibcon#*after write, iclass 3, count 0 2006.257.05:20:12.72#ibcon#*before return 0, iclass 3, count 0 2006.257.05:20:12.72#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:12.72#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:20:12.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.05:20:12.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.05:20:12.72$vck44/vabw=wide 2006.257.05:20:12.72#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.05:20:12.72#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.05:20:12.72#ibcon#ireg 8 cls_cnt 0 2006.257.05:20:12.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:12.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:12.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:12.72#ibcon#enter wrdev, iclass 5, count 0 2006.257.05:20:12.72#ibcon#first serial, iclass 5, count 0 2006.257.05:20:12.72#ibcon#enter sib2, iclass 5, count 0 2006.257.05:20:12.72#ibcon#flushed, iclass 5, count 0 2006.257.05:20:12.72#ibcon#about to write, iclass 5, count 0 2006.257.05:20:12.72#ibcon#wrote, iclass 5, count 0 2006.257.05:20:12.72#ibcon#about to read 3, iclass 5, count 0 2006.257.05:20:12.74#ibcon#read 3, iclass 5, count 0 2006.257.05:20:12.74#ibcon#about to read 4, iclass 5, count 0 2006.257.05:20:12.74#ibcon#read 4, iclass 5, count 0 2006.257.05:20:12.74#ibcon#about to read 5, iclass 5, count 0 2006.257.05:20:12.74#ibcon#read 5, iclass 5, count 0 2006.257.05:20:12.74#ibcon#about to read 6, iclass 5, count 0 2006.257.05:20:12.74#ibcon#read 6, iclass 5, count 0 2006.257.05:20:12.74#ibcon#end of sib2, iclass 5, count 0 2006.257.05:20:12.74#ibcon#*mode == 0, iclass 5, count 0 2006.257.05:20:12.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.05:20:12.74#ibcon#[25=BW32\r\n] 2006.257.05:20:12.74#ibcon#*before write, iclass 5, count 0 2006.257.05:20:12.74#ibcon#enter sib2, iclass 5, count 0 2006.257.05:20:12.74#ibcon#flushed, iclass 5, count 0 2006.257.05:20:12.74#ibcon#about to write, iclass 5, count 0 2006.257.05:20:12.74#ibcon#wrote, iclass 5, count 0 2006.257.05:20:12.74#ibcon#about to read 3, iclass 5, count 0 2006.257.05:20:12.77#ibcon#read 3, iclass 5, count 0 2006.257.05:20:12.77#ibcon#about to read 4, iclass 5, count 0 2006.257.05:20:12.77#ibcon#read 4, iclass 5, count 0 2006.257.05:20:12.77#ibcon#about to read 5, iclass 5, count 0 2006.257.05:20:12.77#ibcon#read 5, iclass 5, count 0 2006.257.05:20:12.77#ibcon#about to read 6, iclass 5, count 0 2006.257.05:20:12.77#ibcon#read 6, iclass 5, count 0 2006.257.05:20:12.77#ibcon#end of sib2, iclass 5, count 0 2006.257.05:20:12.77#ibcon#*after write, iclass 5, count 0 2006.257.05:20:12.77#ibcon#*before return 0, iclass 5, count 0 2006.257.05:20:12.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:12.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:20:12.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.05:20:12.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.05:20:12.77$vck44/vbbw=wide 2006.257.05:20:12.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.05:20:12.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.05:20:12.77#ibcon#ireg 8 cls_cnt 0 2006.257.05:20:12.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:20:12.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:20:12.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:20:12.84#ibcon#enter wrdev, iclass 7, count 0 2006.257.05:20:12.84#ibcon#first serial, iclass 7, count 0 2006.257.05:20:12.84#ibcon#enter sib2, iclass 7, count 0 2006.257.05:20:12.84#ibcon#flushed, iclass 7, count 0 2006.257.05:20:12.84#ibcon#about to write, iclass 7, count 0 2006.257.05:20:12.84#ibcon#wrote, iclass 7, count 0 2006.257.05:20:12.84#ibcon#about to read 3, iclass 7, count 0 2006.257.05:20:12.86#ibcon#read 3, iclass 7, count 0 2006.257.05:20:12.86#ibcon#about to read 4, iclass 7, count 0 2006.257.05:20:12.86#ibcon#read 4, iclass 7, count 0 2006.257.05:20:12.86#ibcon#about to read 5, iclass 7, count 0 2006.257.05:20:12.86#ibcon#read 5, iclass 7, count 0 2006.257.05:20:12.86#ibcon#about to read 6, iclass 7, count 0 2006.257.05:20:12.86#ibcon#read 6, iclass 7, count 0 2006.257.05:20:12.86#ibcon#end of sib2, iclass 7, count 0 2006.257.05:20:12.86#ibcon#*mode == 0, iclass 7, count 0 2006.257.05:20:12.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.05:20:12.86#ibcon#[27=BW32\r\n] 2006.257.05:20:12.86#ibcon#*before write, iclass 7, count 0 2006.257.05:20:12.86#ibcon#enter sib2, iclass 7, count 0 2006.257.05:20:12.86#ibcon#flushed, iclass 7, count 0 2006.257.05:20:12.86#ibcon#about to write, iclass 7, count 0 2006.257.05:20:12.86#ibcon#wrote, iclass 7, count 0 2006.257.05:20:12.86#ibcon#about to read 3, iclass 7, count 0 2006.257.05:20:12.89#ibcon#read 3, iclass 7, count 0 2006.257.05:20:12.89#ibcon#about to read 4, iclass 7, count 0 2006.257.05:20:12.89#ibcon#read 4, iclass 7, count 0 2006.257.05:20:12.89#ibcon#about to read 5, iclass 7, count 0 2006.257.05:20:12.89#ibcon#read 5, iclass 7, count 0 2006.257.05:20:12.89#ibcon#about to read 6, iclass 7, count 0 2006.257.05:20:12.89#ibcon#read 6, iclass 7, count 0 2006.257.05:20:12.89#ibcon#end of sib2, iclass 7, count 0 2006.257.05:20:12.89#ibcon#*after write, iclass 7, count 0 2006.257.05:20:12.89#ibcon#*before return 0, iclass 7, count 0 2006.257.05:20:12.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:20:12.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:20:12.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.05:20:12.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.05:20:12.89$setupk4/ifdk4 2006.257.05:20:12.89$ifdk4/lo= 2006.257.05:20:12.89$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:20:12.89$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:20:12.89$ifdk4/patch= 2006.257.05:20:12.89$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:20:12.89$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:20:12.89$setupk4/!*+20s 2006.257.05:20:21.29#abcon#<5=/16 1.3 3.2 19.90 911012.2\r\n> 2006.257.05:20:21.31#abcon#{5=INTERFACE CLEAR} 2006.257.05:20:21.37#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:20:27.39$setupk4/"tpicd 2006.257.05:20:27.39$setupk4/echo=off 2006.257.05:20:27.39$setupk4/xlog=off 2006.257.05:20:27.39:!2006.257.05:25:09 2006.257.05:21:01.14#trakl#Source acquired 2006.257.05:21:03.14#flagr#flagr/antenna,acquired 2006.257.05:25:09.00:preob 2006.257.05:25:10.14/onsource/TRACKING 2006.257.05:25:10.14:!2006.257.05:25:19 2006.257.05:25:19.00:"tape 2006.257.05:25:19.00:"st=record 2006.257.05:25:19.00:data_valid=on 2006.257.05:25:19.00:midob 2006.257.05:25:19.13/onsource/TRACKING 2006.257.05:25:19.13/wx/19.94,1012.2,91 2006.257.05:25:19.35/cable/+6.4813E-03 2006.257.05:25:20.44/va/01,08,usb,yes,33,35 2006.257.05:25:20.44/va/02,07,usb,yes,35,36 2006.257.05:25:20.44/va/03,08,usb,yes,32,33 2006.257.05:25:20.44/va/04,07,usb,yes,36,38 2006.257.05:25:20.44/va/05,04,usb,yes,33,33 2006.257.05:25:20.44/va/06,04,usb,yes,36,36 2006.257.05:25:20.44/va/07,04,usb,yes,37,38 2006.257.05:25:20.44/va/08,04,usb,yes,31,38 2006.257.05:25:20.67/valo/01,524.99,yes,locked 2006.257.05:25:20.67/valo/02,534.99,yes,locked 2006.257.05:25:20.67/valo/03,564.99,yes,locked 2006.257.05:25:20.67/valo/04,624.99,yes,locked 2006.257.05:25:20.67/valo/05,734.99,yes,locked 2006.257.05:25:20.67/valo/06,814.99,yes,locked 2006.257.05:25:20.67/valo/07,864.99,yes,locked 2006.257.05:25:20.67/valo/08,884.99,yes,locked 2006.257.05:25:21.76/vb/01,04,usb,yes,31,29 2006.257.05:25:21.76/vb/02,05,usb,yes,29,29 2006.257.05:25:21.76/vb/03,04,usb,yes,30,33 2006.257.05:25:21.76/vb/04,05,usb,yes,31,30 2006.257.05:25:21.76/vb/05,04,usb,yes,27,29 2006.257.05:25:21.76/vb/06,04,usb,yes,32,28 2006.257.05:25:21.76/vb/07,04,usb,yes,31,31 2006.257.05:25:21.76/vb/08,04,usb,yes,29,32 2006.257.05:25:21.99/vblo/01,629.99,yes,locked 2006.257.05:25:21.99/vblo/02,634.99,yes,locked 2006.257.05:25:21.99/vblo/03,649.99,yes,locked 2006.257.05:25:21.99/vblo/04,679.99,yes,locked 2006.257.05:25:21.99/vblo/05,709.99,yes,locked 2006.257.05:25:21.99/vblo/06,719.99,yes,locked 2006.257.05:25:21.99/vblo/07,734.99,yes,locked 2006.257.05:25:21.99/vblo/08,744.99,yes,locked 2006.257.05:25:22.14/vabw/8 2006.257.05:25:22.29/vbbw/8 2006.257.05:25:22.38/xfe/off,on,16.7 2006.257.05:25:22.76/ifatt/23,28,28,28 2006.257.05:25:23.08/fmout-gps/S +4.58E-07 2006.257.05:25:23.12:!2006.257.05:25:59 2006.257.05:25:59.00:data_valid=off 2006.257.05:25:59.00:"et 2006.257.05:25:59.00:!+3s 2006.257.05:26:02.01:"tape 2006.257.05:26:02.01:postob 2006.257.05:26:02.12/cable/+6.4797E-03 2006.257.05:26:02.12/wx/19.96,1012.2,91 2006.257.05:26:03.08/fmout-gps/S +4.57E-07 2006.257.05:26:03.08:scan_name=257-0527,jd0609,300 2006.257.05:26:03.08:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.257.05:26:04.13#flagr#flagr/antenna,new-source 2006.257.05:26:04.13:checkk5 2006.257.05:26:04.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:26:04.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:26:05.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:26:05.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:26:06.13/chk_obsdata//k5ts1/T2570525??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:26:06.53/chk_obsdata//k5ts2/T2570525??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:26:06.95/chk_obsdata//k5ts3/T2570525??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:26:07.34/chk_obsdata//k5ts4/T2570525??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:26:08.05/k5log//k5ts1_log_newline 2006.257.05:26:08.77/k5log//k5ts2_log_newline 2006.257.05:26:09.50/k5log//k5ts3_log_newline 2006.257.05:26:10.21/k5log//k5ts4_log_newline 2006.257.05:26:10.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:26:10.23:setupk4=1 2006.257.05:26:10.23$setupk4/echo=on 2006.257.05:26:10.23$setupk4/pcalon 2006.257.05:26:10.23$pcalon/"no phase cal control is implemented here 2006.257.05:26:10.23$setupk4/"tpicd=stop 2006.257.05:26:10.23$setupk4/"rec=synch_on 2006.257.05:26:10.23$setupk4/"rec_mode=128 2006.257.05:26:10.23$setupk4/!* 2006.257.05:26:10.23$setupk4/recpk4 2006.257.05:26:10.23$recpk4/recpatch= 2006.257.05:26:10.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:26:10.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:26:10.24$setupk4/vck44 2006.257.05:26:10.24$vck44/valo=1,524.99 2006.257.05:26:10.24#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.05:26:10.24#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.05:26:10.24#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:10.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:10.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:10.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:10.24#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:26:10.24#ibcon#first serial, iclass 10, count 0 2006.257.05:26:10.24#ibcon#enter sib2, iclass 10, count 0 2006.257.05:26:10.24#ibcon#flushed, iclass 10, count 0 2006.257.05:26:10.24#ibcon#about to write, iclass 10, count 0 2006.257.05:26:10.24#ibcon#wrote, iclass 10, count 0 2006.257.05:26:10.24#ibcon#about to read 3, iclass 10, count 0 2006.257.05:26:10.25#ibcon#read 3, iclass 10, count 0 2006.257.05:26:10.25#ibcon#about to read 4, iclass 10, count 0 2006.257.05:26:10.26#ibcon#read 4, iclass 10, count 0 2006.257.05:26:10.26#ibcon#about to read 5, iclass 10, count 0 2006.257.05:26:10.26#ibcon#read 5, iclass 10, count 0 2006.257.05:26:10.26#ibcon#about to read 6, iclass 10, count 0 2006.257.05:26:10.26#ibcon#read 6, iclass 10, count 0 2006.257.05:26:10.26#ibcon#end of sib2, iclass 10, count 0 2006.257.05:26:10.26#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:26:10.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:26:10.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:26:10.26#ibcon#*before write, iclass 10, count 0 2006.257.05:26:10.26#ibcon#enter sib2, iclass 10, count 0 2006.257.05:26:10.26#ibcon#flushed, iclass 10, count 0 2006.257.05:26:10.26#ibcon#about to write, iclass 10, count 0 2006.257.05:26:10.26#ibcon#wrote, iclass 10, count 0 2006.257.05:26:10.26#ibcon#about to read 3, iclass 10, count 0 2006.257.05:26:10.30#ibcon#read 3, iclass 10, count 0 2006.257.05:26:10.30#ibcon#about to read 4, iclass 10, count 0 2006.257.05:26:10.31#ibcon#read 4, iclass 10, count 0 2006.257.05:26:10.31#ibcon#about to read 5, iclass 10, count 0 2006.257.05:26:10.31#ibcon#read 5, iclass 10, count 0 2006.257.05:26:10.31#ibcon#about to read 6, iclass 10, count 0 2006.257.05:26:10.31#ibcon#read 6, iclass 10, count 0 2006.257.05:26:10.31#ibcon#end of sib2, iclass 10, count 0 2006.257.05:26:10.31#ibcon#*after write, iclass 10, count 0 2006.257.05:26:10.31#ibcon#*before return 0, iclass 10, count 0 2006.257.05:26:10.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:10.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:10.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:26:10.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:26:10.31$vck44/va=1,8 2006.257.05:26:10.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.05:26:10.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.05:26:10.31#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:10.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:10.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:10.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:10.31#ibcon#enter wrdev, iclass 12, count 2 2006.257.05:26:10.31#ibcon#first serial, iclass 12, count 2 2006.257.05:26:10.31#ibcon#enter sib2, iclass 12, count 2 2006.257.05:26:10.31#ibcon#flushed, iclass 12, count 2 2006.257.05:26:10.31#ibcon#about to write, iclass 12, count 2 2006.257.05:26:10.31#ibcon#wrote, iclass 12, count 2 2006.257.05:26:10.31#ibcon#about to read 3, iclass 12, count 2 2006.257.05:26:10.32#ibcon#read 3, iclass 12, count 2 2006.257.05:26:10.32#ibcon#about to read 4, iclass 12, count 2 2006.257.05:26:10.32#ibcon#read 4, iclass 12, count 2 2006.257.05:26:10.32#ibcon#about to read 5, iclass 12, count 2 2006.257.05:26:10.33#ibcon#read 5, iclass 12, count 2 2006.257.05:26:10.33#ibcon#about to read 6, iclass 12, count 2 2006.257.05:26:10.33#ibcon#read 6, iclass 12, count 2 2006.257.05:26:10.33#ibcon#end of sib2, iclass 12, count 2 2006.257.05:26:10.33#ibcon#*mode == 0, iclass 12, count 2 2006.257.05:26:10.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.05:26:10.33#ibcon#[25=AT01-08\r\n] 2006.257.05:26:10.33#ibcon#*before write, iclass 12, count 2 2006.257.05:26:10.33#ibcon#enter sib2, iclass 12, count 2 2006.257.05:26:10.33#ibcon#flushed, iclass 12, count 2 2006.257.05:26:10.33#ibcon#about to write, iclass 12, count 2 2006.257.05:26:10.33#ibcon#wrote, iclass 12, count 2 2006.257.05:26:10.33#ibcon#about to read 3, iclass 12, count 2 2006.257.05:26:10.35#ibcon#read 3, iclass 12, count 2 2006.257.05:26:10.35#ibcon#about to read 4, iclass 12, count 2 2006.257.05:26:10.36#ibcon#read 4, iclass 12, count 2 2006.257.05:26:10.36#ibcon#about to read 5, iclass 12, count 2 2006.257.05:26:10.36#ibcon#read 5, iclass 12, count 2 2006.257.05:26:10.36#ibcon#about to read 6, iclass 12, count 2 2006.257.05:26:10.36#ibcon#read 6, iclass 12, count 2 2006.257.05:26:10.36#ibcon#end of sib2, iclass 12, count 2 2006.257.05:26:10.36#ibcon#*after write, iclass 12, count 2 2006.257.05:26:10.36#ibcon#*before return 0, iclass 12, count 2 2006.257.05:26:10.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:10.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:10.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.05:26:10.36#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:10.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:10.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:10.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:10.47#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:26:10.47#ibcon#first serial, iclass 12, count 0 2006.257.05:26:10.47#ibcon#enter sib2, iclass 12, count 0 2006.257.05:26:10.48#ibcon#flushed, iclass 12, count 0 2006.257.05:26:10.48#ibcon#about to write, iclass 12, count 0 2006.257.05:26:10.48#ibcon#wrote, iclass 12, count 0 2006.257.05:26:10.48#ibcon#about to read 3, iclass 12, count 0 2006.257.05:26:10.49#ibcon#read 3, iclass 12, count 0 2006.257.05:26:10.49#ibcon#about to read 4, iclass 12, count 0 2006.257.05:26:10.49#ibcon#read 4, iclass 12, count 0 2006.257.05:26:10.50#ibcon#about to read 5, iclass 12, count 0 2006.257.05:26:10.50#ibcon#read 5, iclass 12, count 0 2006.257.05:26:10.50#ibcon#about to read 6, iclass 12, count 0 2006.257.05:26:10.50#ibcon#read 6, iclass 12, count 0 2006.257.05:26:10.50#ibcon#end of sib2, iclass 12, count 0 2006.257.05:26:10.50#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:26:10.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:26:10.50#ibcon#[25=USB\r\n] 2006.257.05:26:10.50#ibcon#*before write, iclass 12, count 0 2006.257.05:26:10.50#ibcon#enter sib2, iclass 12, count 0 2006.257.05:26:10.50#ibcon#flushed, iclass 12, count 0 2006.257.05:26:10.50#ibcon#about to write, iclass 12, count 0 2006.257.05:26:10.50#ibcon#wrote, iclass 12, count 0 2006.257.05:26:10.50#ibcon#about to read 3, iclass 12, count 0 2006.257.05:26:10.52#ibcon#read 3, iclass 12, count 0 2006.257.05:26:10.52#ibcon#about to read 4, iclass 12, count 0 2006.257.05:26:10.52#ibcon#read 4, iclass 12, count 0 2006.257.05:26:10.53#ibcon#about to read 5, iclass 12, count 0 2006.257.05:26:10.53#ibcon#read 5, iclass 12, count 0 2006.257.05:26:10.53#ibcon#about to read 6, iclass 12, count 0 2006.257.05:26:10.53#ibcon#read 6, iclass 12, count 0 2006.257.05:26:10.53#ibcon#end of sib2, iclass 12, count 0 2006.257.05:26:10.53#ibcon#*after write, iclass 12, count 0 2006.257.05:26:10.53#ibcon#*before return 0, iclass 12, count 0 2006.257.05:26:10.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:10.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:10.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:26:10.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:26:10.53$vck44/valo=2,534.99 2006.257.05:26:10.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.05:26:10.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.05:26:10.53#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:10.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:10.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:10.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:10.53#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:26:10.53#ibcon#first serial, iclass 14, count 0 2006.257.05:26:10.53#ibcon#enter sib2, iclass 14, count 0 2006.257.05:26:10.53#ibcon#flushed, iclass 14, count 0 2006.257.05:26:10.53#ibcon#about to write, iclass 14, count 0 2006.257.05:26:10.53#ibcon#wrote, iclass 14, count 0 2006.257.05:26:10.53#ibcon#about to read 3, iclass 14, count 0 2006.257.05:26:10.54#ibcon#read 3, iclass 14, count 0 2006.257.05:26:10.54#ibcon#about to read 4, iclass 14, count 0 2006.257.05:26:10.54#ibcon#read 4, iclass 14, count 0 2006.257.05:26:10.55#ibcon#about to read 5, iclass 14, count 0 2006.257.05:26:10.55#ibcon#read 5, iclass 14, count 0 2006.257.05:26:10.55#ibcon#about to read 6, iclass 14, count 0 2006.257.05:26:10.55#ibcon#read 6, iclass 14, count 0 2006.257.05:26:10.55#ibcon#end of sib2, iclass 14, count 0 2006.257.05:26:10.55#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:26:10.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:26:10.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:26:10.55#ibcon#*before write, iclass 14, count 0 2006.257.05:26:10.55#ibcon#enter sib2, iclass 14, count 0 2006.257.05:26:10.55#ibcon#flushed, iclass 14, count 0 2006.257.05:26:10.55#ibcon#about to write, iclass 14, count 0 2006.257.05:26:10.55#ibcon#wrote, iclass 14, count 0 2006.257.05:26:10.55#ibcon#about to read 3, iclass 14, count 0 2006.257.05:26:10.58#ibcon#read 3, iclass 14, count 0 2006.257.05:26:10.58#ibcon#about to read 4, iclass 14, count 0 2006.257.05:26:10.58#ibcon#read 4, iclass 14, count 0 2006.257.05:26:10.59#ibcon#about to read 5, iclass 14, count 0 2006.257.05:26:10.59#ibcon#read 5, iclass 14, count 0 2006.257.05:26:10.59#ibcon#about to read 6, iclass 14, count 0 2006.257.05:26:10.59#ibcon#read 6, iclass 14, count 0 2006.257.05:26:10.59#ibcon#end of sib2, iclass 14, count 0 2006.257.05:26:10.59#ibcon#*after write, iclass 14, count 0 2006.257.05:26:10.59#ibcon#*before return 0, iclass 14, count 0 2006.257.05:26:10.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:10.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:10.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:26:10.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:26:10.59$vck44/va=2,7 2006.257.05:26:10.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.05:26:10.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.05:26:10.59#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:10.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:10.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:10.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:10.65#ibcon#enter wrdev, iclass 16, count 2 2006.257.05:26:10.65#ibcon#first serial, iclass 16, count 2 2006.257.05:26:10.65#ibcon#enter sib2, iclass 16, count 2 2006.257.05:26:10.65#ibcon#flushed, iclass 16, count 2 2006.257.05:26:10.65#ibcon#about to write, iclass 16, count 2 2006.257.05:26:10.65#ibcon#wrote, iclass 16, count 2 2006.257.05:26:10.65#ibcon#about to read 3, iclass 16, count 2 2006.257.05:26:10.66#ibcon#read 3, iclass 16, count 2 2006.257.05:26:10.66#ibcon#about to read 4, iclass 16, count 2 2006.257.05:26:10.66#ibcon#read 4, iclass 16, count 2 2006.257.05:26:10.66#ibcon#about to read 5, iclass 16, count 2 2006.257.05:26:10.66#ibcon#read 5, iclass 16, count 2 2006.257.05:26:10.67#ibcon#about to read 6, iclass 16, count 2 2006.257.05:26:10.67#ibcon#read 6, iclass 16, count 2 2006.257.05:26:10.67#ibcon#end of sib2, iclass 16, count 2 2006.257.05:26:10.67#ibcon#*mode == 0, iclass 16, count 2 2006.257.05:26:10.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.05:26:10.67#ibcon#[25=AT02-07\r\n] 2006.257.05:26:10.67#ibcon#*before write, iclass 16, count 2 2006.257.05:26:10.67#ibcon#enter sib2, iclass 16, count 2 2006.257.05:26:10.67#ibcon#flushed, iclass 16, count 2 2006.257.05:26:10.67#ibcon#about to write, iclass 16, count 2 2006.257.05:26:10.67#ibcon#wrote, iclass 16, count 2 2006.257.05:26:10.67#ibcon#about to read 3, iclass 16, count 2 2006.257.05:26:10.69#ibcon#read 3, iclass 16, count 2 2006.257.05:26:10.69#ibcon#about to read 4, iclass 16, count 2 2006.257.05:26:10.69#ibcon#read 4, iclass 16, count 2 2006.257.05:26:10.69#ibcon#about to read 5, iclass 16, count 2 2006.257.05:26:10.69#ibcon#read 5, iclass 16, count 2 2006.257.05:26:10.70#ibcon#about to read 6, iclass 16, count 2 2006.257.05:26:10.70#ibcon#read 6, iclass 16, count 2 2006.257.05:26:10.70#ibcon#end of sib2, iclass 16, count 2 2006.257.05:26:10.70#ibcon#*after write, iclass 16, count 2 2006.257.05:26:10.70#ibcon#*before return 0, iclass 16, count 2 2006.257.05:26:10.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:10.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:10.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.05:26:10.70#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:10.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:10.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:10.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:10.81#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:26:10.81#ibcon#first serial, iclass 16, count 0 2006.257.05:26:10.81#ibcon#enter sib2, iclass 16, count 0 2006.257.05:26:10.82#ibcon#flushed, iclass 16, count 0 2006.257.05:26:10.82#ibcon#about to write, iclass 16, count 0 2006.257.05:26:10.82#ibcon#wrote, iclass 16, count 0 2006.257.05:26:10.82#ibcon#about to read 3, iclass 16, count 0 2006.257.05:26:10.83#ibcon#read 3, iclass 16, count 0 2006.257.05:26:10.83#ibcon#about to read 4, iclass 16, count 0 2006.257.05:26:10.83#ibcon#read 4, iclass 16, count 0 2006.257.05:26:10.83#ibcon#about to read 5, iclass 16, count 0 2006.257.05:26:10.83#ibcon#read 5, iclass 16, count 0 2006.257.05:26:10.83#ibcon#about to read 6, iclass 16, count 0 2006.257.05:26:10.83#ibcon#read 6, iclass 16, count 0 2006.257.05:26:10.84#ibcon#end of sib2, iclass 16, count 0 2006.257.05:26:10.84#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:26:10.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:26:10.84#ibcon#[25=USB\r\n] 2006.257.05:26:10.84#ibcon#*before write, iclass 16, count 0 2006.257.05:26:10.84#ibcon#enter sib2, iclass 16, count 0 2006.257.05:26:10.84#ibcon#flushed, iclass 16, count 0 2006.257.05:26:10.84#ibcon#about to write, iclass 16, count 0 2006.257.05:26:10.84#ibcon#wrote, iclass 16, count 0 2006.257.05:26:10.84#ibcon#about to read 3, iclass 16, count 0 2006.257.05:26:10.86#ibcon#read 3, iclass 16, count 0 2006.257.05:26:10.86#ibcon#about to read 4, iclass 16, count 0 2006.257.05:26:10.86#ibcon#read 4, iclass 16, count 0 2006.257.05:26:10.86#ibcon#about to read 5, iclass 16, count 0 2006.257.05:26:10.87#ibcon#read 5, iclass 16, count 0 2006.257.05:26:10.87#ibcon#about to read 6, iclass 16, count 0 2006.257.05:26:10.87#ibcon#read 6, iclass 16, count 0 2006.257.05:26:10.87#ibcon#end of sib2, iclass 16, count 0 2006.257.05:26:10.87#ibcon#*after write, iclass 16, count 0 2006.257.05:26:10.87#ibcon#*before return 0, iclass 16, count 0 2006.257.05:26:10.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:10.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:10.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:26:10.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:26:10.87$vck44/valo=3,564.99 2006.257.05:26:10.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.05:26:10.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.05:26:10.87#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:10.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:10.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:10.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:10.87#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:26:10.87#ibcon#first serial, iclass 18, count 0 2006.257.05:26:10.87#ibcon#enter sib2, iclass 18, count 0 2006.257.05:26:10.87#ibcon#flushed, iclass 18, count 0 2006.257.05:26:10.87#ibcon#about to write, iclass 18, count 0 2006.257.05:26:10.87#ibcon#wrote, iclass 18, count 0 2006.257.05:26:10.87#ibcon#about to read 3, iclass 18, count 0 2006.257.05:26:10.88#ibcon#read 3, iclass 18, count 0 2006.257.05:26:10.88#ibcon#about to read 4, iclass 18, count 0 2006.257.05:26:10.88#ibcon#read 4, iclass 18, count 0 2006.257.05:26:10.88#ibcon#about to read 5, iclass 18, count 0 2006.257.05:26:10.88#ibcon#read 5, iclass 18, count 0 2006.257.05:26:10.88#ibcon#about to read 6, iclass 18, count 0 2006.257.05:26:10.89#ibcon#read 6, iclass 18, count 0 2006.257.05:26:10.89#ibcon#end of sib2, iclass 18, count 0 2006.257.05:26:10.89#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:26:10.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:26:10.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:26:10.89#ibcon#*before write, iclass 18, count 0 2006.257.05:26:10.89#ibcon#enter sib2, iclass 18, count 0 2006.257.05:26:10.89#ibcon#flushed, iclass 18, count 0 2006.257.05:26:10.89#ibcon#about to write, iclass 18, count 0 2006.257.05:26:10.89#ibcon#wrote, iclass 18, count 0 2006.257.05:26:10.89#ibcon#about to read 3, iclass 18, count 0 2006.257.05:26:10.92#ibcon#read 3, iclass 18, count 0 2006.257.05:26:10.92#ibcon#about to read 4, iclass 18, count 0 2006.257.05:26:10.93#ibcon#read 4, iclass 18, count 0 2006.257.05:26:10.93#ibcon#about to read 5, iclass 18, count 0 2006.257.05:26:10.93#ibcon#read 5, iclass 18, count 0 2006.257.05:26:10.93#ibcon#about to read 6, iclass 18, count 0 2006.257.05:26:10.93#ibcon#read 6, iclass 18, count 0 2006.257.05:26:10.93#ibcon#end of sib2, iclass 18, count 0 2006.257.05:26:10.93#ibcon#*after write, iclass 18, count 0 2006.257.05:26:10.93#ibcon#*before return 0, iclass 18, count 0 2006.257.05:26:10.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:10.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:10.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:26:10.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:26:10.93$vck44/va=3,8 2006.257.05:26:10.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.05:26:10.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.05:26:10.93#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:10.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:10.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:10.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:10.98#ibcon#enter wrdev, iclass 20, count 2 2006.257.05:26:10.99#ibcon#first serial, iclass 20, count 2 2006.257.05:26:10.99#ibcon#enter sib2, iclass 20, count 2 2006.257.05:26:10.99#ibcon#flushed, iclass 20, count 2 2006.257.05:26:10.99#ibcon#about to write, iclass 20, count 2 2006.257.05:26:10.99#ibcon#wrote, iclass 20, count 2 2006.257.05:26:10.99#ibcon#about to read 3, iclass 20, count 2 2006.257.05:26:11.00#ibcon#read 3, iclass 20, count 2 2006.257.05:26:11.00#ibcon#about to read 4, iclass 20, count 2 2006.257.05:26:11.01#ibcon#read 4, iclass 20, count 2 2006.257.05:26:11.01#ibcon#about to read 5, iclass 20, count 2 2006.257.05:26:11.01#ibcon#read 5, iclass 20, count 2 2006.257.05:26:11.01#ibcon#about to read 6, iclass 20, count 2 2006.257.05:26:11.01#ibcon#read 6, iclass 20, count 2 2006.257.05:26:11.01#ibcon#end of sib2, iclass 20, count 2 2006.257.05:26:11.01#ibcon#*mode == 0, iclass 20, count 2 2006.257.05:26:11.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.05:26:11.01#ibcon#[25=AT03-08\r\n] 2006.257.05:26:11.01#ibcon#*before write, iclass 20, count 2 2006.257.05:26:11.01#ibcon#enter sib2, iclass 20, count 2 2006.257.05:26:11.01#ibcon#flushed, iclass 20, count 2 2006.257.05:26:11.01#ibcon#about to write, iclass 20, count 2 2006.257.05:26:11.01#ibcon#wrote, iclass 20, count 2 2006.257.05:26:11.01#ibcon#about to read 3, iclass 20, count 2 2006.257.05:26:11.03#ibcon#read 3, iclass 20, count 2 2006.257.05:26:11.03#ibcon#about to read 4, iclass 20, count 2 2006.257.05:26:11.03#ibcon#read 4, iclass 20, count 2 2006.257.05:26:11.04#ibcon#about to read 5, iclass 20, count 2 2006.257.05:26:11.04#ibcon#read 5, iclass 20, count 2 2006.257.05:26:11.04#ibcon#about to read 6, iclass 20, count 2 2006.257.05:26:11.04#ibcon#read 6, iclass 20, count 2 2006.257.05:26:11.04#ibcon#end of sib2, iclass 20, count 2 2006.257.05:26:11.04#ibcon#*after write, iclass 20, count 2 2006.257.05:26:11.04#ibcon#*before return 0, iclass 20, count 2 2006.257.05:26:11.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:11.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:11.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.05:26:11.04#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:11.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:11.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:11.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:11.15#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:26:11.15#ibcon#first serial, iclass 20, count 0 2006.257.05:26:11.15#ibcon#enter sib2, iclass 20, count 0 2006.257.05:26:11.16#ibcon#flushed, iclass 20, count 0 2006.257.05:26:11.16#ibcon#about to write, iclass 20, count 0 2006.257.05:26:11.16#ibcon#wrote, iclass 20, count 0 2006.257.05:26:11.16#ibcon#about to read 3, iclass 20, count 0 2006.257.05:26:11.17#ibcon#read 3, iclass 20, count 0 2006.257.05:26:11.17#ibcon#about to read 4, iclass 20, count 0 2006.257.05:26:11.17#ibcon#read 4, iclass 20, count 0 2006.257.05:26:11.17#ibcon#about to read 5, iclass 20, count 0 2006.257.05:26:11.17#ibcon#read 5, iclass 20, count 0 2006.257.05:26:11.17#ibcon#about to read 6, iclass 20, count 0 2006.257.05:26:11.17#ibcon#read 6, iclass 20, count 0 2006.257.05:26:11.18#ibcon#end of sib2, iclass 20, count 0 2006.257.05:26:11.18#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:26:11.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:26:11.18#ibcon#[25=USB\r\n] 2006.257.05:26:11.18#ibcon#*before write, iclass 20, count 0 2006.257.05:26:11.18#ibcon#enter sib2, iclass 20, count 0 2006.257.05:26:11.18#ibcon#flushed, iclass 20, count 0 2006.257.05:26:11.18#ibcon#about to write, iclass 20, count 0 2006.257.05:26:11.18#ibcon#wrote, iclass 20, count 0 2006.257.05:26:11.18#ibcon#about to read 3, iclass 20, count 0 2006.257.05:26:11.20#ibcon#read 3, iclass 20, count 0 2006.257.05:26:11.20#ibcon#about to read 4, iclass 20, count 0 2006.257.05:26:11.20#ibcon#read 4, iclass 20, count 0 2006.257.05:26:11.20#ibcon#about to read 5, iclass 20, count 0 2006.257.05:26:11.21#ibcon#read 5, iclass 20, count 0 2006.257.05:26:11.21#ibcon#about to read 6, iclass 20, count 0 2006.257.05:26:11.21#ibcon#read 6, iclass 20, count 0 2006.257.05:26:11.21#ibcon#end of sib2, iclass 20, count 0 2006.257.05:26:11.21#ibcon#*after write, iclass 20, count 0 2006.257.05:26:11.21#ibcon#*before return 0, iclass 20, count 0 2006.257.05:26:11.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:11.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:11.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:26:11.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:26:11.21$vck44/valo=4,624.99 2006.257.05:26:11.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.05:26:11.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.05:26:11.21#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:11.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:11.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:11.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:11.21#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:26:11.21#ibcon#first serial, iclass 22, count 0 2006.257.05:26:11.21#ibcon#enter sib2, iclass 22, count 0 2006.257.05:26:11.21#ibcon#flushed, iclass 22, count 0 2006.257.05:26:11.21#ibcon#about to write, iclass 22, count 0 2006.257.05:26:11.21#ibcon#wrote, iclass 22, count 0 2006.257.05:26:11.21#ibcon#about to read 3, iclass 22, count 0 2006.257.05:26:11.22#ibcon#read 3, iclass 22, count 0 2006.257.05:26:11.22#ibcon#about to read 4, iclass 22, count 0 2006.257.05:26:11.22#ibcon#read 4, iclass 22, count 0 2006.257.05:26:11.23#ibcon#about to read 5, iclass 22, count 0 2006.257.05:26:11.23#ibcon#read 5, iclass 22, count 0 2006.257.05:26:11.23#ibcon#about to read 6, iclass 22, count 0 2006.257.05:26:11.23#ibcon#read 6, iclass 22, count 0 2006.257.05:26:11.23#ibcon#end of sib2, iclass 22, count 0 2006.257.05:26:11.23#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:26:11.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:26:11.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:26:11.23#ibcon#*before write, iclass 22, count 0 2006.257.05:26:11.23#ibcon#enter sib2, iclass 22, count 0 2006.257.05:26:11.23#ibcon#flushed, iclass 22, count 0 2006.257.05:26:11.23#ibcon#about to write, iclass 22, count 0 2006.257.05:26:11.23#ibcon#wrote, iclass 22, count 0 2006.257.05:26:11.23#ibcon#about to read 3, iclass 22, count 0 2006.257.05:26:11.26#ibcon#read 3, iclass 22, count 0 2006.257.05:26:11.26#ibcon#about to read 4, iclass 22, count 0 2006.257.05:26:11.26#ibcon#read 4, iclass 22, count 0 2006.257.05:26:11.26#ibcon#about to read 5, iclass 22, count 0 2006.257.05:26:11.27#ibcon#read 5, iclass 22, count 0 2006.257.05:26:11.27#ibcon#about to read 6, iclass 22, count 0 2006.257.05:26:11.27#ibcon#read 6, iclass 22, count 0 2006.257.05:26:11.27#ibcon#end of sib2, iclass 22, count 0 2006.257.05:26:11.27#ibcon#*after write, iclass 22, count 0 2006.257.05:26:11.27#ibcon#*before return 0, iclass 22, count 0 2006.257.05:26:11.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:11.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:11.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:26:11.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:26:11.27$vck44/va=4,7 2006.257.05:26:11.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.05:26:11.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.05:26:11.27#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:11.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:11.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:11.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:11.32#ibcon#enter wrdev, iclass 24, count 2 2006.257.05:26:11.32#ibcon#first serial, iclass 24, count 2 2006.257.05:26:11.32#ibcon#enter sib2, iclass 24, count 2 2006.257.05:26:11.33#ibcon#flushed, iclass 24, count 2 2006.257.05:26:11.33#ibcon#about to write, iclass 24, count 2 2006.257.05:26:11.33#ibcon#wrote, iclass 24, count 2 2006.257.05:26:11.33#ibcon#about to read 3, iclass 24, count 2 2006.257.05:26:11.34#ibcon#read 3, iclass 24, count 2 2006.257.05:26:11.34#ibcon#about to read 4, iclass 24, count 2 2006.257.05:26:11.34#ibcon#read 4, iclass 24, count 2 2006.257.05:26:11.34#ibcon#about to read 5, iclass 24, count 2 2006.257.05:26:11.34#ibcon#read 5, iclass 24, count 2 2006.257.05:26:11.34#ibcon#about to read 6, iclass 24, count 2 2006.257.05:26:11.35#ibcon#read 6, iclass 24, count 2 2006.257.05:26:11.35#ibcon#end of sib2, iclass 24, count 2 2006.257.05:26:11.35#ibcon#*mode == 0, iclass 24, count 2 2006.257.05:26:11.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.05:26:11.35#ibcon#[25=AT04-07\r\n] 2006.257.05:26:11.35#ibcon#*before write, iclass 24, count 2 2006.257.05:26:11.35#ibcon#enter sib2, iclass 24, count 2 2006.257.05:26:11.35#ibcon#flushed, iclass 24, count 2 2006.257.05:26:11.35#ibcon#about to write, iclass 24, count 2 2006.257.05:26:11.35#ibcon#wrote, iclass 24, count 2 2006.257.05:26:11.35#ibcon#about to read 3, iclass 24, count 2 2006.257.05:26:11.37#ibcon#read 3, iclass 24, count 2 2006.257.05:26:11.38#ibcon#about to read 4, iclass 24, count 2 2006.257.05:26:11.38#ibcon#read 4, iclass 24, count 2 2006.257.05:26:11.38#ibcon#about to read 5, iclass 24, count 2 2006.257.05:26:11.38#ibcon#read 5, iclass 24, count 2 2006.257.05:26:11.38#ibcon#about to read 6, iclass 24, count 2 2006.257.05:26:11.38#ibcon#read 6, iclass 24, count 2 2006.257.05:26:11.38#ibcon#end of sib2, iclass 24, count 2 2006.257.05:26:11.38#ibcon#*after write, iclass 24, count 2 2006.257.05:26:11.38#ibcon#*before return 0, iclass 24, count 2 2006.257.05:26:11.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:11.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:11.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.05:26:11.38#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:11.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:11.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:11.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:11.49#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:26:11.49#ibcon#first serial, iclass 24, count 0 2006.257.05:26:11.50#ibcon#enter sib2, iclass 24, count 0 2006.257.05:26:11.50#ibcon#flushed, iclass 24, count 0 2006.257.05:26:11.50#ibcon#about to write, iclass 24, count 0 2006.257.05:26:11.50#ibcon#wrote, iclass 24, count 0 2006.257.05:26:11.50#ibcon#about to read 3, iclass 24, count 0 2006.257.05:26:11.51#ibcon#read 3, iclass 24, count 0 2006.257.05:26:11.51#ibcon#about to read 4, iclass 24, count 0 2006.257.05:26:11.51#ibcon#read 4, iclass 24, count 0 2006.257.05:26:11.52#ibcon#about to read 5, iclass 24, count 0 2006.257.05:26:11.52#ibcon#read 5, iclass 24, count 0 2006.257.05:26:11.52#ibcon#about to read 6, iclass 24, count 0 2006.257.05:26:11.52#ibcon#read 6, iclass 24, count 0 2006.257.05:26:11.52#ibcon#end of sib2, iclass 24, count 0 2006.257.05:26:11.52#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:26:11.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:26:11.52#ibcon#[25=USB\r\n] 2006.257.05:26:11.52#ibcon#*before write, iclass 24, count 0 2006.257.05:26:11.52#ibcon#enter sib2, iclass 24, count 0 2006.257.05:26:11.52#ibcon#flushed, iclass 24, count 0 2006.257.05:26:11.52#ibcon#about to write, iclass 24, count 0 2006.257.05:26:11.52#ibcon#wrote, iclass 24, count 0 2006.257.05:26:11.52#ibcon#about to read 3, iclass 24, count 0 2006.257.05:26:11.54#ibcon#read 3, iclass 24, count 0 2006.257.05:26:11.54#ibcon#about to read 4, iclass 24, count 0 2006.257.05:26:11.54#ibcon#read 4, iclass 24, count 0 2006.257.05:26:11.54#ibcon#about to read 5, iclass 24, count 0 2006.257.05:26:11.54#ibcon#read 5, iclass 24, count 0 2006.257.05:26:11.55#ibcon#about to read 6, iclass 24, count 0 2006.257.05:26:11.55#ibcon#read 6, iclass 24, count 0 2006.257.05:26:11.55#ibcon#end of sib2, iclass 24, count 0 2006.257.05:26:11.55#ibcon#*after write, iclass 24, count 0 2006.257.05:26:11.55#ibcon#*before return 0, iclass 24, count 0 2006.257.05:26:11.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:11.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:11.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:26:11.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:26:11.55$vck44/valo=5,734.99 2006.257.05:26:11.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.05:26:11.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.05:26:11.55#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:11.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:11.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:11.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:11.55#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:26:11.55#ibcon#first serial, iclass 26, count 0 2006.257.05:26:11.55#ibcon#enter sib2, iclass 26, count 0 2006.257.05:26:11.55#ibcon#flushed, iclass 26, count 0 2006.257.05:26:11.55#ibcon#about to write, iclass 26, count 0 2006.257.05:26:11.55#ibcon#wrote, iclass 26, count 0 2006.257.05:26:11.55#ibcon#about to read 3, iclass 26, count 0 2006.257.05:26:11.56#ibcon#read 3, iclass 26, count 0 2006.257.05:26:11.56#ibcon#about to read 4, iclass 26, count 0 2006.257.05:26:11.56#ibcon#read 4, iclass 26, count 0 2006.257.05:26:11.56#ibcon#about to read 5, iclass 26, count 0 2006.257.05:26:11.56#ibcon#read 5, iclass 26, count 0 2006.257.05:26:11.56#ibcon#about to read 6, iclass 26, count 0 2006.257.05:26:11.56#ibcon#read 6, iclass 26, count 0 2006.257.05:26:11.57#ibcon#end of sib2, iclass 26, count 0 2006.257.05:26:11.57#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:26:11.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:26:11.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:26:11.57#ibcon#*before write, iclass 26, count 0 2006.257.05:26:11.57#ibcon#enter sib2, iclass 26, count 0 2006.257.05:26:11.57#ibcon#flushed, iclass 26, count 0 2006.257.05:26:11.57#ibcon#about to write, iclass 26, count 0 2006.257.05:26:11.57#ibcon#wrote, iclass 26, count 0 2006.257.05:26:11.57#ibcon#about to read 3, iclass 26, count 0 2006.257.05:26:11.60#ibcon#read 3, iclass 26, count 0 2006.257.05:26:11.60#ibcon#about to read 4, iclass 26, count 0 2006.257.05:26:11.60#ibcon#read 4, iclass 26, count 0 2006.257.05:26:11.60#ibcon#about to read 5, iclass 26, count 0 2006.257.05:26:11.61#ibcon#read 5, iclass 26, count 0 2006.257.05:26:11.61#ibcon#about to read 6, iclass 26, count 0 2006.257.05:26:11.61#ibcon#read 6, iclass 26, count 0 2006.257.05:26:11.61#ibcon#end of sib2, iclass 26, count 0 2006.257.05:26:11.61#ibcon#*after write, iclass 26, count 0 2006.257.05:26:11.61#ibcon#*before return 0, iclass 26, count 0 2006.257.05:26:11.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:11.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:11.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:26:11.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:26:11.61$vck44/va=5,4 2006.257.05:26:11.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.05:26:11.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.05:26:11.61#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:11.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:11.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:11.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:11.66#ibcon#enter wrdev, iclass 28, count 2 2006.257.05:26:11.66#ibcon#first serial, iclass 28, count 2 2006.257.05:26:11.66#ibcon#enter sib2, iclass 28, count 2 2006.257.05:26:11.67#ibcon#flushed, iclass 28, count 2 2006.257.05:26:11.67#ibcon#about to write, iclass 28, count 2 2006.257.05:26:11.67#ibcon#wrote, iclass 28, count 2 2006.257.05:26:11.67#ibcon#about to read 3, iclass 28, count 2 2006.257.05:26:11.68#ibcon#read 3, iclass 28, count 2 2006.257.05:26:11.68#ibcon#about to read 4, iclass 28, count 2 2006.257.05:26:11.68#ibcon#read 4, iclass 28, count 2 2006.257.05:26:11.68#ibcon#about to read 5, iclass 28, count 2 2006.257.05:26:11.68#ibcon#read 5, iclass 28, count 2 2006.257.05:26:11.68#ibcon#about to read 6, iclass 28, count 2 2006.257.05:26:11.68#ibcon#read 6, iclass 28, count 2 2006.257.05:26:11.69#ibcon#end of sib2, iclass 28, count 2 2006.257.05:26:11.69#ibcon#*mode == 0, iclass 28, count 2 2006.257.05:26:11.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.05:26:11.69#ibcon#[25=AT05-04\r\n] 2006.257.05:26:11.69#ibcon#*before write, iclass 28, count 2 2006.257.05:26:11.69#ibcon#enter sib2, iclass 28, count 2 2006.257.05:26:11.69#ibcon#flushed, iclass 28, count 2 2006.257.05:26:11.69#ibcon#about to write, iclass 28, count 2 2006.257.05:26:11.69#ibcon#wrote, iclass 28, count 2 2006.257.05:26:11.69#ibcon#about to read 3, iclass 28, count 2 2006.257.05:26:11.71#ibcon#read 3, iclass 28, count 2 2006.257.05:26:11.71#ibcon#about to read 4, iclass 28, count 2 2006.257.05:26:11.71#ibcon#read 4, iclass 28, count 2 2006.257.05:26:11.71#ibcon#about to read 5, iclass 28, count 2 2006.257.05:26:11.71#ibcon#read 5, iclass 28, count 2 2006.257.05:26:11.71#ibcon#about to read 6, iclass 28, count 2 2006.257.05:26:11.71#ibcon#read 6, iclass 28, count 2 2006.257.05:26:11.72#ibcon#end of sib2, iclass 28, count 2 2006.257.05:26:11.72#ibcon#*after write, iclass 28, count 2 2006.257.05:26:11.72#ibcon#*before return 0, iclass 28, count 2 2006.257.05:26:11.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:11.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:11.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.05:26:11.72#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:11.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:11.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:11.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:11.83#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:26:11.83#ibcon#first serial, iclass 28, count 0 2006.257.05:26:11.83#ibcon#enter sib2, iclass 28, count 0 2006.257.05:26:11.84#ibcon#flushed, iclass 28, count 0 2006.257.05:26:11.84#ibcon#about to write, iclass 28, count 0 2006.257.05:26:11.84#ibcon#wrote, iclass 28, count 0 2006.257.05:26:11.84#ibcon#about to read 3, iclass 28, count 0 2006.257.05:26:11.85#ibcon#read 3, iclass 28, count 0 2006.257.05:26:11.85#ibcon#about to read 4, iclass 28, count 0 2006.257.05:26:11.85#ibcon#read 4, iclass 28, count 0 2006.257.05:26:11.85#ibcon#about to read 5, iclass 28, count 0 2006.257.05:26:11.85#ibcon#read 5, iclass 28, count 0 2006.257.05:26:11.85#ibcon#about to read 6, iclass 28, count 0 2006.257.05:26:11.85#ibcon#read 6, iclass 28, count 0 2006.257.05:26:11.86#ibcon#end of sib2, iclass 28, count 0 2006.257.05:26:11.86#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:26:11.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:26:11.86#ibcon#[25=USB\r\n] 2006.257.05:26:11.86#ibcon#*before write, iclass 28, count 0 2006.257.05:26:11.86#ibcon#enter sib2, iclass 28, count 0 2006.257.05:26:11.86#ibcon#flushed, iclass 28, count 0 2006.257.05:26:11.86#ibcon#about to write, iclass 28, count 0 2006.257.05:26:11.86#ibcon#wrote, iclass 28, count 0 2006.257.05:26:11.86#ibcon#about to read 3, iclass 28, count 0 2006.257.05:26:11.88#ibcon#read 3, iclass 28, count 0 2006.257.05:26:11.88#ibcon#about to read 4, iclass 28, count 0 2006.257.05:26:11.89#ibcon#read 4, iclass 28, count 0 2006.257.05:26:11.89#ibcon#about to read 5, iclass 28, count 0 2006.257.05:26:11.89#ibcon#read 5, iclass 28, count 0 2006.257.05:26:11.89#ibcon#about to read 6, iclass 28, count 0 2006.257.05:26:11.89#ibcon#read 6, iclass 28, count 0 2006.257.05:26:11.89#ibcon#end of sib2, iclass 28, count 0 2006.257.05:26:11.89#ibcon#*after write, iclass 28, count 0 2006.257.05:26:11.89#ibcon#*before return 0, iclass 28, count 0 2006.257.05:26:11.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:11.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:11.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:26:11.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:26:11.89$vck44/valo=6,814.99 2006.257.05:26:11.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.05:26:11.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.05:26:11.89#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:11.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:11.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:11.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:11.89#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:26:11.89#ibcon#first serial, iclass 30, count 0 2006.257.05:26:11.89#ibcon#enter sib2, iclass 30, count 0 2006.257.05:26:11.89#ibcon#flushed, iclass 30, count 0 2006.257.05:26:11.89#ibcon#about to write, iclass 30, count 0 2006.257.05:26:11.89#ibcon#wrote, iclass 30, count 0 2006.257.05:26:11.89#ibcon#about to read 3, iclass 30, count 0 2006.257.05:26:11.90#ibcon#read 3, iclass 30, count 0 2006.257.05:26:11.90#ibcon#about to read 4, iclass 30, count 0 2006.257.05:26:11.91#ibcon#read 4, iclass 30, count 0 2006.257.05:26:11.91#ibcon#about to read 5, iclass 30, count 0 2006.257.05:26:11.91#ibcon#read 5, iclass 30, count 0 2006.257.05:26:11.91#ibcon#about to read 6, iclass 30, count 0 2006.257.05:26:11.91#ibcon#read 6, iclass 30, count 0 2006.257.05:26:11.91#ibcon#end of sib2, iclass 30, count 0 2006.257.05:26:11.91#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:26:11.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:26:11.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:26:11.91#ibcon#*before write, iclass 30, count 0 2006.257.05:26:11.91#ibcon#enter sib2, iclass 30, count 0 2006.257.05:26:11.91#ibcon#flushed, iclass 30, count 0 2006.257.05:26:11.91#ibcon#about to write, iclass 30, count 0 2006.257.05:26:11.91#ibcon#wrote, iclass 30, count 0 2006.257.05:26:11.91#ibcon#about to read 3, iclass 30, count 0 2006.257.05:26:11.94#ibcon#read 3, iclass 30, count 0 2006.257.05:26:11.94#ibcon#about to read 4, iclass 30, count 0 2006.257.05:26:11.95#ibcon#read 4, iclass 30, count 0 2006.257.05:26:11.95#ibcon#about to read 5, iclass 30, count 0 2006.257.05:26:11.95#ibcon#read 5, iclass 30, count 0 2006.257.05:26:11.95#ibcon#about to read 6, iclass 30, count 0 2006.257.05:26:11.95#ibcon#read 6, iclass 30, count 0 2006.257.05:26:11.95#ibcon#end of sib2, iclass 30, count 0 2006.257.05:26:11.95#ibcon#*after write, iclass 30, count 0 2006.257.05:26:11.95#ibcon#*before return 0, iclass 30, count 0 2006.257.05:26:11.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:11.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:11.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:26:11.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:26:11.95$vck44/va=6,4 2006.257.05:26:11.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.05:26:11.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.05:26:11.95#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:11.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:12.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:12.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:12.01#ibcon#enter wrdev, iclass 32, count 2 2006.257.05:26:12.01#ibcon#first serial, iclass 32, count 2 2006.257.05:26:12.01#ibcon#enter sib2, iclass 32, count 2 2006.257.05:26:12.01#ibcon#flushed, iclass 32, count 2 2006.257.05:26:12.01#ibcon#about to write, iclass 32, count 2 2006.257.05:26:12.01#ibcon#wrote, iclass 32, count 2 2006.257.05:26:12.01#ibcon#about to read 3, iclass 32, count 2 2006.257.05:26:12.02#ibcon#read 3, iclass 32, count 2 2006.257.05:26:12.02#ibcon#about to read 4, iclass 32, count 2 2006.257.05:26:12.02#ibcon#read 4, iclass 32, count 2 2006.257.05:26:12.02#ibcon#about to read 5, iclass 32, count 2 2006.257.05:26:12.02#ibcon#read 5, iclass 32, count 2 2006.257.05:26:12.03#ibcon#about to read 6, iclass 32, count 2 2006.257.05:26:12.03#ibcon#read 6, iclass 32, count 2 2006.257.05:26:12.03#ibcon#end of sib2, iclass 32, count 2 2006.257.05:26:12.03#ibcon#*mode == 0, iclass 32, count 2 2006.257.05:26:12.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.05:26:12.03#ibcon#[25=AT06-04\r\n] 2006.257.05:26:12.03#ibcon#*before write, iclass 32, count 2 2006.257.05:26:12.03#ibcon#enter sib2, iclass 32, count 2 2006.257.05:26:12.03#ibcon#flushed, iclass 32, count 2 2006.257.05:26:12.03#ibcon#about to write, iclass 32, count 2 2006.257.05:26:12.03#ibcon#wrote, iclass 32, count 2 2006.257.05:26:12.03#ibcon#about to read 3, iclass 32, count 2 2006.257.05:26:12.05#ibcon#read 3, iclass 32, count 2 2006.257.05:26:12.05#ibcon#about to read 4, iclass 32, count 2 2006.257.05:26:12.05#ibcon#read 4, iclass 32, count 2 2006.257.05:26:12.05#ibcon#about to read 5, iclass 32, count 2 2006.257.05:26:12.06#ibcon#read 5, iclass 32, count 2 2006.257.05:26:12.06#ibcon#about to read 6, iclass 32, count 2 2006.257.05:26:12.06#ibcon#read 6, iclass 32, count 2 2006.257.05:26:12.06#ibcon#end of sib2, iclass 32, count 2 2006.257.05:26:12.06#ibcon#*after write, iclass 32, count 2 2006.257.05:26:12.06#ibcon#*before return 0, iclass 32, count 2 2006.257.05:26:12.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:12.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:12.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.05:26:12.06#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:12.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:12.17#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:12.17#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:12.17#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:26:12.17#ibcon#first serial, iclass 32, count 0 2006.257.05:26:12.17#ibcon#enter sib2, iclass 32, count 0 2006.257.05:26:12.18#ibcon#flushed, iclass 32, count 0 2006.257.05:26:12.18#ibcon#about to write, iclass 32, count 0 2006.257.05:26:12.18#ibcon#wrote, iclass 32, count 0 2006.257.05:26:12.18#ibcon#about to read 3, iclass 32, count 0 2006.257.05:26:12.19#ibcon#read 3, iclass 32, count 0 2006.257.05:26:12.19#ibcon#about to read 4, iclass 32, count 0 2006.257.05:26:12.19#ibcon#read 4, iclass 32, count 0 2006.257.05:26:12.19#ibcon#about to read 5, iclass 32, count 0 2006.257.05:26:12.19#ibcon#read 5, iclass 32, count 0 2006.257.05:26:12.19#ibcon#about to read 6, iclass 32, count 0 2006.257.05:26:12.20#ibcon#read 6, iclass 32, count 0 2006.257.05:26:12.20#ibcon#end of sib2, iclass 32, count 0 2006.257.05:26:12.20#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:26:12.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:26:12.20#ibcon#[25=USB\r\n] 2006.257.05:26:12.20#ibcon#*before write, iclass 32, count 0 2006.257.05:26:12.20#ibcon#enter sib2, iclass 32, count 0 2006.257.05:26:12.20#ibcon#flushed, iclass 32, count 0 2006.257.05:26:12.20#ibcon#about to write, iclass 32, count 0 2006.257.05:26:12.20#ibcon#wrote, iclass 32, count 0 2006.257.05:26:12.20#ibcon#about to read 3, iclass 32, count 0 2006.257.05:26:12.22#ibcon#read 3, iclass 32, count 0 2006.257.05:26:12.22#ibcon#about to read 4, iclass 32, count 0 2006.257.05:26:12.22#ibcon#read 4, iclass 32, count 0 2006.257.05:26:12.22#ibcon#about to read 5, iclass 32, count 0 2006.257.05:26:12.22#ibcon#read 5, iclass 32, count 0 2006.257.05:26:12.23#ibcon#about to read 6, iclass 32, count 0 2006.257.05:26:12.23#ibcon#read 6, iclass 32, count 0 2006.257.05:26:12.23#ibcon#end of sib2, iclass 32, count 0 2006.257.05:26:12.23#ibcon#*after write, iclass 32, count 0 2006.257.05:26:12.23#ibcon#*before return 0, iclass 32, count 0 2006.257.05:26:12.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:12.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:12.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:26:12.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:26:12.23$vck44/valo=7,864.99 2006.257.05:26:12.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.05:26:12.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.05:26:12.23#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:12.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:12.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:12.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:12.23#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:26:12.23#ibcon#first serial, iclass 34, count 0 2006.257.05:26:12.23#ibcon#enter sib2, iclass 34, count 0 2006.257.05:26:12.23#ibcon#flushed, iclass 34, count 0 2006.257.05:26:12.23#ibcon#about to write, iclass 34, count 0 2006.257.05:26:12.23#ibcon#wrote, iclass 34, count 0 2006.257.05:26:12.23#ibcon#about to read 3, iclass 34, count 0 2006.257.05:26:12.24#ibcon#read 3, iclass 34, count 0 2006.257.05:26:12.24#ibcon#about to read 4, iclass 34, count 0 2006.257.05:26:12.24#ibcon#read 4, iclass 34, count 0 2006.257.05:26:12.25#ibcon#about to read 5, iclass 34, count 0 2006.257.05:26:12.25#ibcon#read 5, iclass 34, count 0 2006.257.05:26:12.25#ibcon#about to read 6, iclass 34, count 0 2006.257.05:26:12.25#ibcon#read 6, iclass 34, count 0 2006.257.05:26:12.25#ibcon#end of sib2, iclass 34, count 0 2006.257.05:26:12.25#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:26:12.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:26:12.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:26:12.25#ibcon#*before write, iclass 34, count 0 2006.257.05:26:12.25#ibcon#enter sib2, iclass 34, count 0 2006.257.05:26:12.25#ibcon#flushed, iclass 34, count 0 2006.257.05:26:12.25#ibcon#about to write, iclass 34, count 0 2006.257.05:26:12.25#ibcon#wrote, iclass 34, count 0 2006.257.05:26:12.25#ibcon#about to read 3, iclass 34, count 0 2006.257.05:26:12.28#ibcon#read 3, iclass 34, count 0 2006.257.05:26:12.28#ibcon#about to read 4, iclass 34, count 0 2006.257.05:26:12.28#ibcon#read 4, iclass 34, count 0 2006.257.05:26:12.28#ibcon#about to read 5, iclass 34, count 0 2006.257.05:26:12.28#ibcon#read 5, iclass 34, count 0 2006.257.05:26:12.28#ibcon#about to read 6, iclass 34, count 0 2006.257.05:26:12.29#ibcon#read 6, iclass 34, count 0 2006.257.05:26:12.29#ibcon#end of sib2, iclass 34, count 0 2006.257.05:26:12.29#ibcon#*after write, iclass 34, count 0 2006.257.05:26:12.29#ibcon#*before return 0, iclass 34, count 0 2006.257.05:26:12.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:12.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:12.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:26:12.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:26:12.29$vck44/va=7,4 2006.257.05:26:12.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.05:26:12.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.05:26:12.29#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:12.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:12.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:12.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:12.34#ibcon#enter wrdev, iclass 36, count 2 2006.257.05:26:12.34#ibcon#first serial, iclass 36, count 2 2006.257.05:26:12.34#ibcon#enter sib2, iclass 36, count 2 2006.257.05:26:12.35#ibcon#flushed, iclass 36, count 2 2006.257.05:26:12.35#ibcon#about to write, iclass 36, count 2 2006.257.05:26:12.35#ibcon#wrote, iclass 36, count 2 2006.257.05:26:12.35#ibcon#about to read 3, iclass 36, count 2 2006.257.05:26:12.36#ibcon#read 3, iclass 36, count 2 2006.257.05:26:12.36#ibcon#about to read 4, iclass 36, count 2 2006.257.05:26:12.36#ibcon#read 4, iclass 36, count 2 2006.257.05:26:12.36#ibcon#about to read 5, iclass 36, count 2 2006.257.05:26:12.36#ibcon#read 5, iclass 36, count 2 2006.257.05:26:12.36#ibcon#about to read 6, iclass 36, count 2 2006.257.05:26:12.36#ibcon#read 6, iclass 36, count 2 2006.257.05:26:12.37#ibcon#end of sib2, iclass 36, count 2 2006.257.05:26:12.37#ibcon#*mode == 0, iclass 36, count 2 2006.257.05:26:12.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.05:26:12.37#ibcon#[25=AT07-04\r\n] 2006.257.05:26:12.37#ibcon#*before write, iclass 36, count 2 2006.257.05:26:12.37#ibcon#enter sib2, iclass 36, count 2 2006.257.05:26:12.37#ibcon#flushed, iclass 36, count 2 2006.257.05:26:12.37#ibcon#about to write, iclass 36, count 2 2006.257.05:26:12.37#ibcon#wrote, iclass 36, count 2 2006.257.05:26:12.37#ibcon#about to read 3, iclass 36, count 2 2006.257.05:26:12.39#ibcon#read 3, iclass 36, count 2 2006.257.05:26:12.40#ibcon#about to read 4, iclass 36, count 2 2006.257.05:26:12.40#ibcon#read 4, iclass 36, count 2 2006.257.05:26:12.40#ibcon#about to read 5, iclass 36, count 2 2006.257.05:26:12.40#ibcon#read 5, iclass 36, count 2 2006.257.05:26:12.40#ibcon#about to read 6, iclass 36, count 2 2006.257.05:26:12.40#ibcon#read 6, iclass 36, count 2 2006.257.05:26:12.40#ibcon#end of sib2, iclass 36, count 2 2006.257.05:26:12.40#ibcon#*after write, iclass 36, count 2 2006.257.05:26:12.40#ibcon#*before return 0, iclass 36, count 2 2006.257.05:26:12.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:12.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:12.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.05:26:12.40#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:12.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:12.51#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:12.51#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:12.51#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:26:12.51#ibcon#first serial, iclass 36, count 0 2006.257.05:26:12.51#ibcon#enter sib2, iclass 36, count 0 2006.257.05:26:12.52#ibcon#flushed, iclass 36, count 0 2006.257.05:26:12.52#ibcon#about to write, iclass 36, count 0 2006.257.05:26:12.52#ibcon#wrote, iclass 36, count 0 2006.257.05:26:12.52#ibcon#about to read 3, iclass 36, count 0 2006.257.05:26:12.53#ibcon#read 3, iclass 36, count 0 2006.257.05:26:12.53#ibcon#about to read 4, iclass 36, count 0 2006.257.05:26:12.53#ibcon#read 4, iclass 36, count 0 2006.257.05:26:12.54#ibcon#about to read 5, iclass 36, count 0 2006.257.05:26:12.54#ibcon#read 5, iclass 36, count 0 2006.257.05:26:12.54#ibcon#about to read 6, iclass 36, count 0 2006.257.05:26:12.54#ibcon#read 6, iclass 36, count 0 2006.257.05:26:12.54#ibcon#end of sib2, iclass 36, count 0 2006.257.05:26:12.54#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:26:12.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:26:12.54#ibcon#[25=USB\r\n] 2006.257.05:26:12.54#ibcon#*before write, iclass 36, count 0 2006.257.05:26:12.54#ibcon#enter sib2, iclass 36, count 0 2006.257.05:26:12.54#ibcon#flushed, iclass 36, count 0 2006.257.05:26:12.54#ibcon#about to write, iclass 36, count 0 2006.257.05:26:12.54#ibcon#wrote, iclass 36, count 0 2006.257.05:26:12.54#ibcon#about to read 3, iclass 36, count 0 2006.257.05:26:12.56#ibcon#read 3, iclass 36, count 0 2006.257.05:26:12.56#ibcon#about to read 4, iclass 36, count 0 2006.257.05:26:12.56#ibcon#read 4, iclass 36, count 0 2006.257.05:26:12.56#ibcon#about to read 5, iclass 36, count 0 2006.257.05:26:12.56#ibcon#read 5, iclass 36, count 0 2006.257.05:26:12.57#ibcon#about to read 6, iclass 36, count 0 2006.257.05:26:12.57#ibcon#read 6, iclass 36, count 0 2006.257.05:26:12.57#ibcon#end of sib2, iclass 36, count 0 2006.257.05:26:12.57#ibcon#*after write, iclass 36, count 0 2006.257.05:26:12.57#ibcon#*before return 0, iclass 36, count 0 2006.257.05:26:12.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:12.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:12.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:26:12.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:26:12.57$vck44/valo=8,884.99 2006.257.05:26:12.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.05:26:12.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.05:26:12.57#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:12.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:12.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:12.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:12.57#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:26:12.57#ibcon#first serial, iclass 38, count 0 2006.257.05:26:12.57#ibcon#enter sib2, iclass 38, count 0 2006.257.05:26:12.57#ibcon#flushed, iclass 38, count 0 2006.257.05:26:12.57#ibcon#about to write, iclass 38, count 0 2006.257.05:26:12.57#ibcon#wrote, iclass 38, count 0 2006.257.05:26:12.57#ibcon#about to read 3, iclass 38, count 0 2006.257.05:26:12.58#ibcon#read 3, iclass 38, count 0 2006.257.05:26:12.58#ibcon#about to read 4, iclass 38, count 0 2006.257.05:26:12.58#ibcon#read 4, iclass 38, count 0 2006.257.05:26:12.58#ibcon#about to read 5, iclass 38, count 0 2006.257.05:26:12.58#ibcon#read 5, iclass 38, count 0 2006.257.05:26:12.59#ibcon#about to read 6, iclass 38, count 0 2006.257.05:26:12.59#ibcon#read 6, iclass 38, count 0 2006.257.05:26:12.59#ibcon#end of sib2, iclass 38, count 0 2006.257.05:26:12.59#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:26:12.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:26:12.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:26:12.59#ibcon#*before write, iclass 38, count 0 2006.257.05:26:12.59#ibcon#enter sib2, iclass 38, count 0 2006.257.05:26:12.59#ibcon#flushed, iclass 38, count 0 2006.257.05:26:12.59#ibcon#about to write, iclass 38, count 0 2006.257.05:26:12.59#ibcon#wrote, iclass 38, count 0 2006.257.05:26:12.59#ibcon#about to read 3, iclass 38, count 0 2006.257.05:26:12.62#ibcon#read 3, iclass 38, count 0 2006.257.05:26:12.62#ibcon#about to read 4, iclass 38, count 0 2006.257.05:26:12.62#ibcon#read 4, iclass 38, count 0 2006.257.05:26:12.62#ibcon#about to read 5, iclass 38, count 0 2006.257.05:26:12.62#ibcon#read 5, iclass 38, count 0 2006.257.05:26:12.63#ibcon#about to read 6, iclass 38, count 0 2006.257.05:26:12.63#ibcon#read 6, iclass 38, count 0 2006.257.05:26:12.63#ibcon#end of sib2, iclass 38, count 0 2006.257.05:26:12.63#ibcon#*after write, iclass 38, count 0 2006.257.05:26:12.63#ibcon#*before return 0, iclass 38, count 0 2006.257.05:26:12.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:12.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:12.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:26:12.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:26:12.63$vck44/va=8,4 2006.257.05:26:12.63#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.05:26:12.63#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.05:26:12.63#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:12.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:26:12.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:26:12.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:26:12.68#ibcon#enter wrdev, iclass 40, count 2 2006.257.05:26:12.69#ibcon#first serial, iclass 40, count 2 2006.257.05:26:12.69#ibcon#enter sib2, iclass 40, count 2 2006.257.05:26:12.69#ibcon#flushed, iclass 40, count 2 2006.257.05:26:12.69#ibcon#about to write, iclass 40, count 2 2006.257.05:26:12.69#ibcon#wrote, iclass 40, count 2 2006.257.05:26:12.69#ibcon#about to read 3, iclass 40, count 2 2006.257.05:26:12.70#ibcon#read 3, iclass 40, count 2 2006.257.05:26:12.70#ibcon#about to read 4, iclass 40, count 2 2006.257.05:26:12.70#ibcon#read 4, iclass 40, count 2 2006.257.05:26:12.71#ibcon#about to read 5, iclass 40, count 2 2006.257.05:26:12.71#ibcon#read 5, iclass 40, count 2 2006.257.05:26:12.71#ibcon#about to read 6, iclass 40, count 2 2006.257.05:26:12.71#ibcon#read 6, iclass 40, count 2 2006.257.05:26:12.71#ibcon#end of sib2, iclass 40, count 2 2006.257.05:26:12.71#ibcon#*mode == 0, iclass 40, count 2 2006.257.05:26:12.71#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.05:26:12.71#ibcon#[25=AT08-04\r\n] 2006.257.05:26:12.71#ibcon#*before write, iclass 40, count 2 2006.257.05:26:12.71#ibcon#enter sib2, iclass 40, count 2 2006.257.05:26:12.71#ibcon#flushed, iclass 40, count 2 2006.257.05:26:12.71#ibcon#about to write, iclass 40, count 2 2006.257.05:26:12.71#ibcon#wrote, iclass 40, count 2 2006.257.05:26:12.71#ibcon#about to read 3, iclass 40, count 2 2006.257.05:26:12.73#ibcon#read 3, iclass 40, count 2 2006.257.05:26:12.73#ibcon#about to read 4, iclass 40, count 2 2006.257.05:26:12.73#ibcon#read 4, iclass 40, count 2 2006.257.05:26:12.73#ibcon#about to read 5, iclass 40, count 2 2006.257.05:26:12.73#ibcon#read 5, iclass 40, count 2 2006.257.05:26:12.73#ibcon#about to read 6, iclass 40, count 2 2006.257.05:26:12.74#ibcon#read 6, iclass 40, count 2 2006.257.05:26:12.74#ibcon#end of sib2, iclass 40, count 2 2006.257.05:26:12.74#ibcon#*after write, iclass 40, count 2 2006.257.05:26:12.74#ibcon#*before return 0, iclass 40, count 2 2006.257.05:26:12.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:26:12.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:26:12.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.05:26:12.74#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:12.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:26:12.85#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:26:12.85#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:26:12.85#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:26:12.85#ibcon#first serial, iclass 40, count 0 2006.257.05:26:12.86#ibcon#enter sib2, iclass 40, count 0 2006.257.05:26:12.86#ibcon#flushed, iclass 40, count 0 2006.257.05:26:12.86#ibcon#about to write, iclass 40, count 0 2006.257.05:26:12.86#ibcon#wrote, iclass 40, count 0 2006.257.05:26:12.86#ibcon#about to read 3, iclass 40, count 0 2006.257.05:26:12.87#ibcon#read 3, iclass 40, count 0 2006.257.05:26:12.87#ibcon#about to read 4, iclass 40, count 0 2006.257.05:26:12.87#ibcon#read 4, iclass 40, count 0 2006.257.05:26:12.88#ibcon#about to read 5, iclass 40, count 0 2006.257.05:26:12.88#ibcon#read 5, iclass 40, count 0 2006.257.05:26:12.88#ibcon#about to read 6, iclass 40, count 0 2006.257.05:26:12.88#ibcon#read 6, iclass 40, count 0 2006.257.05:26:12.88#ibcon#end of sib2, iclass 40, count 0 2006.257.05:26:12.88#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:26:12.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:26:12.88#ibcon#[25=USB\r\n] 2006.257.05:26:12.88#ibcon#*before write, iclass 40, count 0 2006.257.05:26:12.88#ibcon#enter sib2, iclass 40, count 0 2006.257.05:26:12.88#ibcon#flushed, iclass 40, count 0 2006.257.05:26:12.88#ibcon#about to write, iclass 40, count 0 2006.257.05:26:12.88#ibcon#wrote, iclass 40, count 0 2006.257.05:26:12.88#ibcon#about to read 3, iclass 40, count 0 2006.257.05:26:12.90#ibcon#read 3, iclass 40, count 0 2006.257.05:26:12.90#ibcon#about to read 4, iclass 40, count 0 2006.257.05:26:12.90#ibcon#read 4, iclass 40, count 0 2006.257.05:26:12.90#ibcon#about to read 5, iclass 40, count 0 2006.257.05:26:12.91#ibcon#read 5, iclass 40, count 0 2006.257.05:26:12.91#ibcon#about to read 6, iclass 40, count 0 2006.257.05:26:12.91#ibcon#read 6, iclass 40, count 0 2006.257.05:26:12.91#ibcon#end of sib2, iclass 40, count 0 2006.257.05:26:12.91#ibcon#*after write, iclass 40, count 0 2006.257.05:26:12.91#ibcon#*before return 0, iclass 40, count 0 2006.257.05:26:12.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:26:12.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:26:12.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:26:12.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:26:12.91$vck44/vblo=1,629.99 2006.257.05:26:12.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.05:26:12.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.05:26:12.91#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:12.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:26:12.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:26:12.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:26:12.91#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:26:12.91#ibcon#first serial, iclass 4, count 0 2006.257.05:26:12.91#ibcon#enter sib2, iclass 4, count 0 2006.257.05:26:12.91#ibcon#flushed, iclass 4, count 0 2006.257.05:26:12.91#ibcon#about to write, iclass 4, count 0 2006.257.05:26:12.91#ibcon#wrote, iclass 4, count 0 2006.257.05:26:12.91#ibcon#about to read 3, iclass 4, count 0 2006.257.05:26:12.92#ibcon#read 3, iclass 4, count 0 2006.257.05:26:12.92#ibcon#about to read 4, iclass 4, count 0 2006.257.05:26:12.92#ibcon#read 4, iclass 4, count 0 2006.257.05:26:12.92#ibcon#about to read 5, iclass 4, count 0 2006.257.05:26:12.93#ibcon#read 5, iclass 4, count 0 2006.257.05:26:12.93#ibcon#about to read 6, iclass 4, count 0 2006.257.05:26:12.93#ibcon#read 6, iclass 4, count 0 2006.257.05:26:12.93#ibcon#end of sib2, iclass 4, count 0 2006.257.05:26:12.93#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:26:12.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:26:12.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:26:12.93#ibcon#*before write, iclass 4, count 0 2006.257.05:26:12.93#ibcon#enter sib2, iclass 4, count 0 2006.257.05:26:12.93#ibcon#flushed, iclass 4, count 0 2006.257.05:26:12.93#ibcon#about to write, iclass 4, count 0 2006.257.05:26:12.93#ibcon#wrote, iclass 4, count 0 2006.257.05:26:12.93#ibcon#about to read 3, iclass 4, count 0 2006.257.05:26:12.96#ibcon#read 3, iclass 4, count 0 2006.257.05:26:12.96#ibcon#about to read 4, iclass 4, count 0 2006.257.05:26:12.96#ibcon#read 4, iclass 4, count 0 2006.257.05:26:12.96#ibcon#about to read 5, iclass 4, count 0 2006.257.05:26:12.97#ibcon#read 5, iclass 4, count 0 2006.257.05:26:12.97#ibcon#about to read 6, iclass 4, count 0 2006.257.05:26:12.97#ibcon#read 6, iclass 4, count 0 2006.257.05:26:12.97#ibcon#end of sib2, iclass 4, count 0 2006.257.05:26:12.97#ibcon#*after write, iclass 4, count 0 2006.257.05:26:12.97#ibcon#*before return 0, iclass 4, count 0 2006.257.05:26:12.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:26:12.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:26:12.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:26:12.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:26:12.97$vck44/vb=1,4 2006.257.05:26:12.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.05:26:12.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.05:26:12.97#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:12.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:26:12.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:26:12.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:26:12.97#ibcon#enter wrdev, iclass 6, count 2 2006.257.05:26:12.97#ibcon#first serial, iclass 6, count 2 2006.257.05:26:12.97#ibcon#enter sib2, iclass 6, count 2 2006.257.05:26:12.97#ibcon#flushed, iclass 6, count 2 2006.257.05:26:12.97#ibcon#about to write, iclass 6, count 2 2006.257.05:26:12.97#ibcon#wrote, iclass 6, count 2 2006.257.05:26:12.97#ibcon#about to read 3, iclass 6, count 2 2006.257.05:26:12.98#ibcon#read 3, iclass 6, count 2 2006.257.05:26:12.98#ibcon#about to read 4, iclass 6, count 2 2006.257.05:26:12.98#ibcon#read 4, iclass 6, count 2 2006.257.05:26:12.99#ibcon#about to read 5, iclass 6, count 2 2006.257.05:26:12.99#ibcon#read 5, iclass 6, count 2 2006.257.05:26:12.99#ibcon#about to read 6, iclass 6, count 2 2006.257.05:26:12.99#ibcon#read 6, iclass 6, count 2 2006.257.05:26:12.99#ibcon#end of sib2, iclass 6, count 2 2006.257.05:26:12.99#ibcon#*mode == 0, iclass 6, count 2 2006.257.05:26:12.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.05:26:12.99#ibcon#[27=AT01-04\r\n] 2006.257.05:26:12.99#ibcon#*before write, iclass 6, count 2 2006.257.05:26:12.99#ibcon#enter sib2, iclass 6, count 2 2006.257.05:26:12.99#ibcon#flushed, iclass 6, count 2 2006.257.05:26:12.99#ibcon#about to write, iclass 6, count 2 2006.257.05:26:12.99#ibcon#wrote, iclass 6, count 2 2006.257.05:26:12.99#ibcon#about to read 3, iclass 6, count 2 2006.257.05:26:13.01#ibcon#read 3, iclass 6, count 2 2006.257.05:26:13.01#ibcon#about to read 4, iclass 6, count 2 2006.257.05:26:13.01#ibcon#read 4, iclass 6, count 2 2006.257.05:26:13.01#ibcon#about to read 5, iclass 6, count 2 2006.257.05:26:13.01#ibcon#read 5, iclass 6, count 2 2006.257.05:26:13.02#ibcon#about to read 6, iclass 6, count 2 2006.257.05:26:13.02#ibcon#read 6, iclass 6, count 2 2006.257.05:26:13.02#ibcon#end of sib2, iclass 6, count 2 2006.257.05:26:13.02#ibcon#*after write, iclass 6, count 2 2006.257.05:26:13.02#ibcon#*before return 0, iclass 6, count 2 2006.257.05:26:13.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:26:13.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:26:13.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.05:26:13.02#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:13.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:26:13.13#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:26:13.13#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:26:13.13#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:26:13.13#ibcon#first serial, iclass 6, count 0 2006.257.05:26:13.13#ibcon#enter sib2, iclass 6, count 0 2006.257.05:26:13.13#ibcon#flushed, iclass 6, count 0 2006.257.05:26:13.14#ibcon#about to write, iclass 6, count 0 2006.257.05:26:13.14#ibcon#wrote, iclass 6, count 0 2006.257.05:26:13.14#ibcon#about to read 3, iclass 6, count 0 2006.257.05:26:13.15#ibcon#read 3, iclass 6, count 0 2006.257.05:26:13.15#ibcon#about to read 4, iclass 6, count 0 2006.257.05:26:13.15#ibcon#read 4, iclass 6, count 0 2006.257.05:26:13.15#ibcon#about to read 5, iclass 6, count 0 2006.257.05:26:13.15#ibcon#read 5, iclass 6, count 0 2006.257.05:26:13.15#ibcon#about to read 6, iclass 6, count 0 2006.257.05:26:13.16#ibcon#read 6, iclass 6, count 0 2006.257.05:26:13.16#ibcon#end of sib2, iclass 6, count 0 2006.257.05:26:13.16#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:26:13.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:26:13.16#ibcon#[27=USB\r\n] 2006.257.05:26:13.16#ibcon#*before write, iclass 6, count 0 2006.257.05:26:13.16#ibcon#enter sib2, iclass 6, count 0 2006.257.05:26:13.16#ibcon#flushed, iclass 6, count 0 2006.257.05:26:13.16#ibcon#about to write, iclass 6, count 0 2006.257.05:26:13.16#ibcon#wrote, iclass 6, count 0 2006.257.05:26:13.16#ibcon#about to read 3, iclass 6, count 0 2006.257.05:26:13.18#ibcon#read 3, iclass 6, count 0 2006.257.05:26:13.18#ibcon#about to read 4, iclass 6, count 0 2006.257.05:26:13.18#ibcon#read 4, iclass 6, count 0 2006.257.05:26:13.18#ibcon#about to read 5, iclass 6, count 0 2006.257.05:26:13.18#ibcon#read 5, iclass 6, count 0 2006.257.05:26:13.18#ibcon#about to read 6, iclass 6, count 0 2006.257.05:26:13.19#ibcon#read 6, iclass 6, count 0 2006.257.05:26:13.19#ibcon#end of sib2, iclass 6, count 0 2006.257.05:26:13.19#ibcon#*after write, iclass 6, count 0 2006.257.05:26:13.19#ibcon#*before return 0, iclass 6, count 0 2006.257.05:26:13.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:26:13.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:26:13.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:26:13.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:26:13.19$vck44/vblo=2,634.99 2006.257.05:26:13.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.05:26:13.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.05:26:13.19#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:13.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:13.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:13.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:13.19#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:26:13.19#ibcon#first serial, iclass 10, count 0 2006.257.05:26:13.19#ibcon#enter sib2, iclass 10, count 0 2006.257.05:26:13.19#ibcon#flushed, iclass 10, count 0 2006.257.05:26:13.19#ibcon#about to write, iclass 10, count 0 2006.257.05:26:13.19#ibcon#wrote, iclass 10, count 0 2006.257.05:26:13.19#ibcon#about to read 3, iclass 10, count 0 2006.257.05:26:13.20#ibcon#read 3, iclass 10, count 0 2006.257.05:26:13.20#ibcon#about to read 4, iclass 10, count 0 2006.257.05:26:13.20#ibcon#read 4, iclass 10, count 0 2006.257.05:26:13.21#ibcon#about to read 5, iclass 10, count 0 2006.257.05:26:13.21#ibcon#read 5, iclass 10, count 0 2006.257.05:26:13.21#ibcon#about to read 6, iclass 10, count 0 2006.257.05:26:13.21#ibcon#read 6, iclass 10, count 0 2006.257.05:26:13.21#ibcon#end of sib2, iclass 10, count 0 2006.257.05:26:13.21#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:26:13.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:26:13.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:26:13.21#ibcon#*before write, iclass 10, count 0 2006.257.05:26:13.21#ibcon#enter sib2, iclass 10, count 0 2006.257.05:26:13.21#ibcon#flushed, iclass 10, count 0 2006.257.05:26:13.21#ibcon#about to write, iclass 10, count 0 2006.257.05:26:13.21#ibcon#wrote, iclass 10, count 0 2006.257.05:26:13.21#ibcon#about to read 3, iclass 10, count 0 2006.257.05:26:13.24#ibcon#read 3, iclass 10, count 0 2006.257.05:26:13.24#ibcon#about to read 4, iclass 10, count 0 2006.257.05:26:13.24#ibcon#read 4, iclass 10, count 0 2006.257.05:26:13.24#ibcon#about to read 5, iclass 10, count 0 2006.257.05:26:13.25#ibcon#read 5, iclass 10, count 0 2006.257.05:26:13.25#ibcon#about to read 6, iclass 10, count 0 2006.257.05:26:13.25#ibcon#read 6, iclass 10, count 0 2006.257.05:26:13.25#ibcon#end of sib2, iclass 10, count 0 2006.257.05:26:13.25#ibcon#*after write, iclass 10, count 0 2006.257.05:26:13.25#ibcon#*before return 0, iclass 10, count 0 2006.257.05:26:13.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:13.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:26:13.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:26:13.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:26:13.25$vck44/vb=2,5 2006.257.05:26:13.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.05:26:13.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.05:26:13.25#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:13.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:13.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:13.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:13.30#ibcon#enter wrdev, iclass 12, count 2 2006.257.05:26:13.30#ibcon#first serial, iclass 12, count 2 2006.257.05:26:13.30#ibcon#enter sib2, iclass 12, count 2 2006.257.05:26:13.31#ibcon#flushed, iclass 12, count 2 2006.257.05:26:13.31#ibcon#about to write, iclass 12, count 2 2006.257.05:26:13.31#ibcon#wrote, iclass 12, count 2 2006.257.05:26:13.31#ibcon#about to read 3, iclass 12, count 2 2006.257.05:26:13.32#ibcon#read 3, iclass 12, count 2 2006.257.05:26:13.32#ibcon#about to read 4, iclass 12, count 2 2006.257.05:26:13.32#ibcon#read 4, iclass 12, count 2 2006.257.05:26:13.32#ibcon#about to read 5, iclass 12, count 2 2006.257.05:26:13.32#ibcon#read 5, iclass 12, count 2 2006.257.05:26:13.32#ibcon#about to read 6, iclass 12, count 2 2006.257.05:26:13.32#ibcon#read 6, iclass 12, count 2 2006.257.05:26:13.33#ibcon#end of sib2, iclass 12, count 2 2006.257.05:26:13.33#ibcon#*mode == 0, iclass 12, count 2 2006.257.05:26:13.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.05:26:13.33#ibcon#[27=AT02-05\r\n] 2006.257.05:26:13.33#ibcon#*before write, iclass 12, count 2 2006.257.05:26:13.33#ibcon#enter sib2, iclass 12, count 2 2006.257.05:26:13.33#ibcon#flushed, iclass 12, count 2 2006.257.05:26:13.33#ibcon#about to write, iclass 12, count 2 2006.257.05:26:13.33#ibcon#wrote, iclass 12, count 2 2006.257.05:26:13.33#ibcon#about to read 3, iclass 12, count 2 2006.257.05:26:13.35#ibcon#read 3, iclass 12, count 2 2006.257.05:26:13.35#ibcon#about to read 4, iclass 12, count 2 2006.257.05:26:13.35#ibcon#read 4, iclass 12, count 2 2006.257.05:26:13.35#ibcon#about to read 5, iclass 12, count 2 2006.257.05:26:13.36#ibcon#read 5, iclass 12, count 2 2006.257.05:26:13.36#ibcon#about to read 6, iclass 12, count 2 2006.257.05:26:13.36#ibcon#read 6, iclass 12, count 2 2006.257.05:26:13.36#ibcon#end of sib2, iclass 12, count 2 2006.257.05:26:13.36#ibcon#*after write, iclass 12, count 2 2006.257.05:26:13.36#ibcon#*before return 0, iclass 12, count 2 2006.257.05:26:13.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:13.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:26:13.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.05:26:13.36#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:13.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:13.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:13.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:13.47#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:26:13.47#ibcon#first serial, iclass 12, count 0 2006.257.05:26:13.47#ibcon#enter sib2, iclass 12, count 0 2006.257.05:26:13.48#ibcon#flushed, iclass 12, count 0 2006.257.05:26:13.48#ibcon#about to write, iclass 12, count 0 2006.257.05:26:13.48#ibcon#wrote, iclass 12, count 0 2006.257.05:26:13.48#ibcon#about to read 3, iclass 12, count 0 2006.257.05:26:13.49#ibcon#read 3, iclass 12, count 0 2006.257.05:26:13.49#ibcon#about to read 4, iclass 12, count 0 2006.257.05:26:13.49#ibcon#read 4, iclass 12, count 0 2006.257.05:26:13.49#ibcon#about to read 5, iclass 12, count 0 2006.257.05:26:13.49#ibcon#read 5, iclass 12, count 0 2006.257.05:26:13.49#ibcon#about to read 6, iclass 12, count 0 2006.257.05:26:13.49#ibcon#read 6, iclass 12, count 0 2006.257.05:26:13.50#ibcon#end of sib2, iclass 12, count 0 2006.257.05:26:13.50#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:26:13.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:26:13.50#ibcon#[27=USB\r\n] 2006.257.05:26:13.50#ibcon#*before write, iclass 12, count 0 2006.257.05:26:13.50#ibcon#enter sib2, iclass 12, count 0 2006.257.05:26:13.50#ibcon#flushed, iclass 12, count 0 2006.257.05:26:13.50#ibcon#about to write, iclass 12, count 0 2006.257.05:26:13.50#ibcon#wrote, iclass 12, count 0 2006.257.05:26:13.50#ibcon#about to read 3, iclass 12, count 0 2006.257.05:26:13.52#ibcon#read 3, iclass 12, count 0 2006.257.05:26:13.52#ibcon#about to read 4, iclass 12, count 0 2006.257.05:26:13.52#ibcon#read 4, iclass 12, count 0 2006.257.05:26:13.52#ibcon#about to read 5, iclass 12, count 0 2006.257.05:26:13.53#ibcon#read 5, iclass 12, count 0 2006.257.05:26:13.53#ibcon#about to read 6, iclass 12, count 0 2006.257.05:26:13.53#ibcon#read 6, iclass 12, count 0 2006.257.05:26:13.53#ibcon#end of sib2, iclass 12, count 0 2006.257.05:26:13.53#ibcon#*after write, iclass 12, count 0 2006.257.05:26:13.53#ibcon#*before return 0, iclass 12, count 0 2006.257.05:26:13.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:13.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:26:13.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:26:13.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:26:13.53$vck44/vblo=3,649.99 2006.257.05:26:13.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.05:26:13.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.05:26:13.53#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:13.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:13.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:13.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:13.53#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:26:13.53#ibcon#first serial, iclass 14, count 0 2006.257.05:26:13.53#ibcon#enter sib2, iclass 14, count 0 2006.257.05:26:13.53#ibcon#flushed, iclass 14, count 0 2006.257.05:26:13.53#ibcon#about to write, iclass 14, count 0 2006.257.05:26:13.53#ibcon#wrote, iclass 14, count 0 2006.257.05:26:13.53#ibcon#about to read 3, iclass 14, count 0 2006.257.05:26:13.54#ibcon#read 3, iclass 14, count 0 2006.257.05:26:13.54#ibcon#about to read 4, iclass 14, count 0 2006.257.05:26:13.54#ibcon#read 4, iclass 14, count 0 2006.257.05:26:13.54#ibcon#about to read 5, iclass 14, count 0 2006.257.05:26:13.54#ibcon#read 5, iclass 14, count 0 2006.257.05:26:13.54#ibcon#about to read 6, iclass 14, count 0 2006.257.05:26:13.55#ibcon#read 6, iclass 14, count 0 2006.257.05:26:13.55#ibcon#end of sib2, iclass 14, count 0 2006.257.05:26:13.55#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:26:13.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:26:13.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:26:13.55#ibcon#*before write, iclass 14, count 0 2006.257.05:26:13.55#ibcon#enter sib2, iclass 14, count 0 2006.257.05:26:13.55#ibcon#flushed, iclass 14, count 0 2006.257.05:26:13.55#ibcon#about to write, iclass 14, count 0 2006.257.05:26:13.55#ibcon#wrote, iclass 14, count 0 2006.257.05:26:13.55#ibcon#about to read 3, iclass 14, count 0 2006.257.05:26:13.58#ibcon#read 3, iclass 14, count 0 2006.257.05:26:13.58#ibcon#about to read 4, iclass 14, count 0 2006.257.05:26:13.58#ibcon#read 4, iclass 14, count 0 2006.257.05:26:13.58#ibcon#about to read 5, iclass 14, count 0 2006.257.05:26:13.59#ibcon#read 5, iclass 14, count 0 2006.257.05:26:13.59#ibcon#about to read 6, iclass 14, count 0 2006.257.05:26:13.59#ibcon#read 6, iclass 14, count 0 2006.257.05:26:13.59#ibcon#end of sib2, iclass 14, count 0 2006.257.05:26:13.59#ibcon#*after write, iclass 14, count 0 2006.257.05:26:13.59#ibcon#*before return 0, iclass 14, count 0 2006.257.05:26:13.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:13.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:26:13.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:26:13.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:26:13.59$vck44/vb=3,4 2006.257.05:26:13.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.05:26:13.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.05:26:13.59#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:13.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:13.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:13.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:13.65#ibcon#enter wrdev, iclass 16, count 2 2006.257.05:26:13.65#ibcon#first serial, iclass 16, count 2 2006.257.05:26:13.65#ibcon#enter sib2, iclass 16, count 2 2006.257.05:26:13.65#ibcon#flushed, iclass 16, count 2 2006.257.05:26:13.65#ibcon#about to write, iclass 16, count 2 2006.257.05:26:13.65#ibcon#wrote, iclass 16, count 2 2006.257.05:26:13.65#ibcon#about to read 3, iclass 16, count 2 2006.257.05:26:13.66#ibcon#read 3, iclass 16, count 2 2006.257.05:26:13.66#ibcon#about to read 4, iclass 16, count 2 2006.257.05:26:13.66#ibcon#read 4, iclass 16, count 2 2006.257.05:26:13.66#ibcon#about to read 5, iclass 16, count 2 2006.257.05:26:13.67#ibcon#read 5, iclass 16, count 2 2006.257.05:26:13.67#ibcon#about to read 6, iclass 16, count 2 2006.257.05:26:13.67#ibcon#read 6, iclass 16, count 2 2006.257.05:26:13.67#ibcon#end of sib2, iclass 16, count 2 2006.257.05:26:13.67#ibcon#*mode == 0, iclass 16, count 2 2006.257.05:26:13.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.05:26:13.67#ibcon#[27=AT03-04\r\n] 2006.257.05:26:13.67#ibcon#*before write, iclass 16, count 2 2006.257.05:26:13.67#ibcon#enter sib2, iclass 16, count 2 2006.257.05:26:13.67#ibcon#flushed, iclass 16, count 2 2006.257.05:26:13.67#ibcon#about to write, iclass 16, count 2 2006.257.05:26:13.67#ibcon#wrote, iclass 16, count 2 2006.257.05:26:13.67#ibcon#about to read 3, iclass 16, count 2 2006.257.05:26:13.69#ibcon#read 3, iclass 16, count 2 2006.257.05:26:13.69#ibcon#about to read 4, iclass 16, count 2 2006.257.05:26:13.69#ibcon#read 4, iclass 16, count 2 2006.257.05:26:13.69#ibcon#about to read 5, iclass 16, count 2 2006.257.05:26:13.70#ibcon#read 5, iclass 16, count 2 2006.257.05:26:13.70#ibcon#about to read 6, iclass 16, count 2 2006.257.05:26:13.70#ibcon#read 6, iclass 16, count 2 2006.257.05:26:13.70#ibcon#end of sib2, iclass 16, count 2 2006.257.05:26:13.70#ibcon#*after write, iclass 16, count 2 2006.257.05:26:13.70#ibcon#*before return 0, iclass 16, count 2 2006.257.05:26:13.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:13.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:26:13.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.05:26:13.70#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:13.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:13.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:13.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:13.82#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:26:13.82#ibcon#first serial, iclass 16, count 0 2006.257.05:26:13.82#ibcon#enter sib2, iclass 16, count 0 2006.257.05:26:13.82#ibcon#flushed, iclass 16, count 0 2006.257.05:26:13.82#ibcon#about to write, iclass 16, count 0 2006.257.05:26:13.82#ibcon#wrote, iclass 16, count 0 2006.257.05:26:13.82#ibcon#about to read 3, iclass 16, count 0 2006.257.05:26:13.83#ibcon#read 3, iclass 16, count 0 2006.257.05:26:13.83#ibcon#about to read 4, iclass 16, count 0 2006.257.05:26:13.83#ibcon#read 4, iclass 16, count 0 2006.257.05:26:13.84#ibcon#about to read 5, iclass 16, count 0 2006.257.05:26:13.84#ibcon#read 5, iclass 16, count 0 2006.257.05:26:13.84#ibcon#about to read 6, iclass 16, count 0 2006.257.05:26:13.84#ibcon#read 6, iclass 16, count 0 2006.257.05:26:13.84#ibcon#end of sib2, iclass 16, count 0 2006.257.05:26:13.84#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:26:13.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:26:13.84#ibcon#[27=USB\r\n] 2006.257.05:26:13.84#ibcon#*before write, iclass 16, count 0 2006.257.05:26:13.84#ibcon#enter sib2, iclass 16, count 0 2006.257.05:26:13.84#ibcon#flushed, iclass 16, count 0 2006.257.05:26:13.84#ibcon#about to write, iclass 16, count 0 2006.257.05:26:13.84#ibcon#wrote, iclass 16, count 0 2006.257.05:26:13.84#ibcon#about to read 3, iclass 16, count 0 2006.257.05:26:13.86#ibcon#read 3, iclass 16, count 0 2006.257.05:26:13.86#ibcon#about to read 4, iclass 16, count 0 2006.257.05:26:13.86#ibcon#read 4, iclass 16, count 0 2006.257.05:26:13.86#ibcon#about to read 5, iclass 16, count 0 2006.257.05:26:13.87#ibcon#read 5, iclass 16, count 0 2006.257.05:26:13.87#ibcon#about to read 6, iclass 16, count 0 2006.257.05:26:13.87#ibcon#read 6, iclass 16, count 0 2006.257.05:26:13.87#ibcon#end of sib2, iclass 16, count 0 2006.257.05:26:13.87#ibcon#*after write, iclass 16, count 0 2006.257.05:26:13.87#ibcon#*before return 0, iclass 16, count 0 2006.257.05:26:13.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:13.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:26:13.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:26:13.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:26:13.87$vck44/vblo=4,679.99 2006.257.05:26:13.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.05:26:13.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.05:26:13.87#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:13.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:13.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:13.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:13.87#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:26:13.87#ibcon#first serial, iclass 18, count 0 2006.257.05:26:13.87#ibcon#enter sib2, iclass 18, count 0 2006.257.05:26:13.87#ibcon#flushed, iclass 18, count 0 2006.257.05:26:13.87#ibcon#about to write, iclass 18, count 0 2006.257.05:26:13.87#ibcon#wrote, iclass 18, count 0 2006.257.05:26:13.87#ibcon#about to read 3, iclass 18, count 0 2006.257.05:26:13.88#ibcon#read 3, iclass 18, count 0 2006.257.05:26:13.88#ibcon#about to read 4, iclass 18, count 0 2006.257.05:26:13.88#ibcon#read 4, iclass 18, count 0 2006.257.05:26:13.88#ibcon#about to read 5, iclass 18, count 0 2006.257.05:26:13.89#ibcon#read 5, iclass 18, count 0 2006.257.05:26:13.89#ibcon#about to read 6, iclass 18, count 0 2006.257.05:26:13.89#ibcon#read 6, iclass 18, count 0 2006.257.05:26:13.89#ibcon#end of sib2, iclass 18, count 0 2006.257.05:26:13.89#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:26:13.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:26:13.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:26:13.89#ibcon#*before write, iclass 18, count 0 2006.257.05:26:13.89#ibcon#enter sib2, iclass 18, count 0 2006.257.05:26:13.89#ibcon#flushed, iclass 18, count 0 2006.257.05:26:13.89#ibcon#about to write, iclass 18, count 0 2006.257.05:26:13.89#ibcon#wrote, iclass 18, count 0 2006.257.05:26:13.89#ibcon#about to read 3, iclass 18, count 0 2006.257.05:26:13.92#ibcon#read 3, iclass 18, count 0 2006.257.05:26:13.92#ibcon#about to read 4, iclass 18, count 0 2006.257.05:26:13.92#ibcon#read 4, iclass 18, count 0 2006.257.05:26:13.92#ibcon#about to read 5, iclass 18, count 0 2006.257.05:26:13.93#ibcon#read 5, iclass 18, count 0 2006.257.05:26:13.93#ibcon#about to read 6, iclass 18, count 0 2006.257.05:26:13.93#ibcon#read 6, iclass 18, count 0 2006.257.05:26:13.93#ibcon#end of sib2, iclass 18, count 0 2006.257.05:26:13.93#ibcon#*after write, iclass 18, count 0 2006.257.05:26:13.93#ibcon#*before return 0, iclass 18, count 0 2006.257.05:26:13.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:13.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:26:13.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:26:13.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:26:13.93$vck44/vb=4,5 2006.257.05:26:13.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.05:26:13.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.05:26:13.93#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:13.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:13.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:13.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:13.98#ibcon#enter wrdev, iclass 20, count 2 2006.257.05:26:13.98#ibcon#first serial, iclass 20, count 2 2006.257.05:26:13.98#ibcon#enter sib2, iclass 20, count 2 2006.257.05:26:13.99#ibcon#flushed, iclass 20, count 2 2006.257.05:26:13.99#ibcon#about to write, iclass 20, count 2 2006.257.05:26:13.99#ibcon#wrote, iclass 20, count 2 2006.257.05:26:13.99#ibcon#about to read 3, iclass 20, count 2 2006.257.05:26:14.00#ibcon#read 3, iclass 20, count 2 2006.257.05:26:14.00#ibcon#about to read 4, iclass 20, count 2 2006.257.05:26:14.00#ibcon#read 4, iclass 20, count 2 2006.257.05:26:14.00#ibcon#about to read 5, iclass 20, count 2 2006.257.05:26:14.00#ibcon#read 5, iclass 20, count 2 2006.257.05:26:14.00#ibcon#about to read 6, iclass 20, count 2 2006.257.05:26:14.01#ibcon#read 6, iclass 20, count 2 2006.257.05:26:14.01#ibcon#end of sib2, iclass 20, count 2 2006.257.05:26:14.01#ibcon#*mode == 0, iclass 20, count 2 2006.257.05:26:14.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.05:26:14.01#ibcon#[27=AT04-05\r\n] 2006.257.05:26:14.01#ibcon#*before write, iclass 20, count 2 2006.257.05:26:14.01#ibcon#enter sib2, iclass 20, count 2 2006.257.05:26:14.01#ibcon#flushed, iclass 20, count 2 2006.257.05:26:14.01#ibcon#about to write, iclass 20, count 2 2006.257.05:26:14.01#ibcon#wrote, iclass 20, count 2 2006.257.05:26:14.01#ibcon#about to read 3, iclass 20, count 2 2006.257.05:26:14.03#ibcon#read 3, iclass 20, count 2 2006.257.05:26:14.03#ibcon#about to read 4, iclass 20, count 2 2006.257.05:26:14.03#ibcon#read 4, iclass 20, count 2 2006.257.05:26:14.03#ibcon#about to read 5, iclass 20, count 2 2006.257.05:26:14.03#ibcon#read 5, iclass 20, count 2 2006.257.05:26:14.04#ibcon#about to read 6, iclass 20, count 2 2006.257.05:26:14.04#ibcon#read 6, iclass 20, count 2 2006.257.05:26:14.04#ibcon#end of sib2, iclass 20, count 2 2006.257.05:26:14.04#ibcon#*after write, iclass 20, count 2 2006.257.05:26:14.04#ibcon#*before return 0, iclass 20, count 2 2006.257.05:26:14.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:14.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:26:14.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.05:26:14.04#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:14.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:14.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:14.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:14.15#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:26:14.15#ibcon#first serial, iclass 20, count 0 2006.257.05:26:14.15#ibcon#enter sib2, iclass 20, count 0 2006.257.05:26:14.15#ibcon#flushed, iclass 20, count 0 2006.257.05:26:14.16#ibcon#about to write, iclass 20, count 0 2006.257.05:26:14.16#ibcon#wrote, iclass 20, count 0 2006.257.05:26:14.16#ibcon#about to read 3, iclass 20, count 0 2006.257.05:26:14.17#ibcon#read 3, iclass 20, count 0 2006.257.05:26:14.17#ibcon#about to read 4, iclass 20, count 0 2006.257.05:26:14.17#ibcon#read 4, iclass 20, count 0 2006.257.05:26:14.17#ibcon#about to read 5, iclass 20, count 0 2006.257.05:26:14.17#ibcon#read 5, iclass 20, count 0 2006.257.05:26:14.17#ibcon#about to read 6, iclass 20, count 0 2006.257.05:26:14.17#ibcon#read 6, iclass 20, count 0 2006.257.05:26:14.17#ibcon#end of sib2, iclass 20, count 0 2006.257.05:26:14.18#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:26:14.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:26:14.18#ibcon#[27=USB\r\n] 2006.257.05:26:14.18#ibcon#*before write, iclass 20, count 0 2006.257.05:26:14.18#ibcon#enter sib2, iclass 20, count 0 2006.257.05:26:14.18#ibcon#flushed, iclass 20, count 0 2006.257.05:26:14.18#ibcon#about to write, iclass 20, count 0 2006.257.05:26:14.18#ibcon#wrote, iclass 20, count 0 2006.257.05:26:14.18#ibcon#about to read 3, iclass 20, count 0 2006.257.05:26:14.20#ibcon#read 3, iclass 20, count 0 2006.257.05:26:14.20#ibcon#about to read 4, iclass 20, count 0 2006.257.05:26:14.20#ibcon#read 4, iclass 20, count 0 2006.257.05:26:14.21#ibcon#about to read 5, iclass 20, count 0 2006.257.05:26:14.21#ibcon#read 5, iclass 20, count 0 2006.257.05:26:14.21#ibcon#about to read 6, iclass 20, count 0 2006.257.05:26:14.21#ibcon#read 6, iclass 20, count 0 2006.257.05:26:14.21#ibcon#end of sib2, iclass 20, count 0 2006.257.05:26:14.21#ibcon#*after write, iclass 20, count 0 2006.257.05:26:14.21#ibcon#*before return 0, iclass 20, count 0 2006.257.05:26:14.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:14.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:26:14.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:26:14.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:26:14.21$vck44/vblo=5,709.99 2006.257.05:26:14.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.05:26:14.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.05:26:14.21#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:14.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:14.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:14.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:14.21#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:26:14.21#ibcon#first serial, iclass 22, count 0 2006.257.05:26:14.21#ibcon#enter sib2, iclass 22, count 0 2006.257.05:26:14.21#ibcon#flushed, iclass 22, count 0 2006.257.05:26:14.21#ibcon#about to write, iclass 22, count 0 2006.257.05:26:14.21#ibcon#wrote, iclass 22, count 0 2006.257.05:26:14.21#ibcon#about to read 3, iclass 22, count 0 2006.257.05:26:14.22#ibcon#read 3, iclass 22, count 0 2006.257.05:26:14.22#ibcon#about to read 4, iclass 22, count 0 2006.257.05:26:14.22#ibcon#read 4, iclass 22, count 0 2006.257.05:26:14.22#ibcon#about to read 5, iclass 22, count 0 2006.257.05:26:14.22#ibcon#read 5, iclass 22, count 0 2006.257.05:26:14.23#ibcon#about to read 6, iclass 22, count 0 2006.257.05:26:14.23#ibcon#read 6, iclass 22, count 0 2006.257.05:26:14.23#ibcon#end of sib2, iclass 22, count 0 2006.257.05:26:14.23#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:26:14.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:26:14.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:26:14.23#ibcon#*before write, iclass 22, count 0 2006.257.05:26:14.23#ibcon#enter sib2, iclass 22, count 0 2006.257.05:26:14.23#ibcon#flushed, iclass 22, count 0 2006.257.05:26:14.23#ibcon#about to write, iclass 22, count 0 2006.257.05:26:14.23#ibcon#wrote, iclass 22, count 0 2006.257.05:26:14.23#ibcon#about to read 3, iclass 22, count 0 2006.257.05:26:14.26#ibcon#read 3, iclass 22, count 0 2006.257.05:26:14.26#ibcon#about to read 4, iclass 22, count 0 2006.257.05:26:14.26#ibcon#read 4, iclass 22, count 0 2006.257.05:26:14.26#ibcon#about to read 5, iclass 22, count 0 2006.257.05:26:14.26#ibcon#read 5, iclass 22, count 0 2006.257.05:26:14.26#ibcon#about to read 6, iclass 22, count 0 2006.257.05:26:14.27#ibcon#read 6, iclass 22, count 0 2006.257.05:26:14.27#ibcon#end of sib2, iclass 22, count 0 2006.257.05:26:14.27#ibcon#*after write, iclass 22, count 0 2006.257.05:26:14.27#ibcon#*before return 0, iclass 22, count 0 2006.257.05:26:14.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:14.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:26:14.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:26:14.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:26:14.27$vck44/vb=5,4 2006.257.05:26:14.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.05:26:14.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.05:26:14.27#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:14.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:14.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:14.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:14.32#ibcon#enter wrdev, iclass 24, count 2 2006.257.05:26:14.32#ibcon#first serial, iclass 24, count 2 2006.257.05:26:14.32#ibcon#enter sib2, iclass 24, count 2 2006.257.05:26:14.33#ibcon#flushed, iclass 24, count 2 2006.257.05:26:14.33#ibcon#about to write, iclass 24, count 2 2006.257.05:26:14.33#ibcon#wrote, iclass 24, count 2 2006.257.05:26:14.33#ibcon#about to read 3, iclass 24, count 2 2006.257.05:26:14.34#ibcon#read 3, iclass 24, count 2 2006.257.05:26:14.34#ibcon#about to read 4, iclass 24, count 2 2006.257.05:26:14.34#ibcon#read 4, iclass 24, count 2 2006.257.05:26:14.35#ibcon#about to read 5, iclass 24, count 2 2006.257.05:26:14.35#ibcon#read 5, iclass 24, count 2 2006.257.05:26:14.35#ibcon#about to read 6, iclass 24, count 2 2006.257.05:26:14.35#ibcon#read 6, iclass 24, count 2 2006.257.05:26:14.35#ibcon#end of sib2, iclass 24, count 2 2006.257.05:26:14.35#ibcon#*mode == 0, iclass 24, count 2 2006.257.05:26:14.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.05:26:14.35#ibcon#[27=AT05-04\r\n] 2006.257.05:26:14.35#ibcon#*before write, iclass 24, count 2 2006.257.05:26:14.35#ibcon#enter sib2, iclass 24, count 2 2006.257.05:26:14.35#ibcon#flushed, iclass 24, count 2 2006.257.05:26:14.35#ibcon#about to write, iclass 24, count 2 2006.257.05:26:14.35#ibcon#wrote, iclass 24, count 2 2006.257.05:26:14.35#ibcon#about to read 3, iclass 24, count 2 2006.257.05:26:14.37#ibcon#read 3, iclass 24, count 2 2006.257.05:26:14.37#ibcon#about to read 4, iclass 24, count 2 2006.257.05:26:14.37#ibcon#read 4, iclass 24, count 2 2006.257.05:26:14.37#ibcon#about to read 5, iclass 24, count 2 2006.257.05:26:14.38#ibcon#read 5, iclass 24, count 2 2006.257.05:26:14.38#ibcon#about to read 6, iclass 24, count 2 2006.257.05:26:14.38#ibcon#read 6, iclass 24, count 2 2006.257.05:26:14.38#ibcon#end of sib2, iclass 24, count 2 2006.257.05:26:14.38#ibcon#*after write, iclass 24, count 2 2006.257.05:26:14.38#ibcon#*before return 0, iclass 24, count 2 2006.257.05:26:14.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:14.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:26:14.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.05:26:14.38#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:14.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:14.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:14.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:14.49#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:26:14.49#ibcon#first serial, iclass 24, count 0 2006.257.05:26:14.49#ibcon#enter sib2, iclass 24, count 0 2006.257.05:26:14.50#ibcon#flushed, iclass 24, count 0 2006.257.05:26:14.50#ibcon#about to write, iclass 24, count 0 2006.257.05:26:14.50#ibcon#wrote, iclass 24, count 0 2006.257.05:26:14.50#ibcon#about to read 3, iclass 24, count 0 2006.257.05:26:14.51#ibcon#read 3, iclass 24, count 0 2006.257.05:26:14.51#ibcon#about to read 4, iclass 24, count 0 2006.257.05:26:14.51#ibcon#read 4, iclass 24, count 0 2006.257.05:26:14.51#ibcon#about to read 5, iclass 24, count 0 2006.257.05:26:14.51#ibcon#read 5, iclass 24, count 0 2006.257.05:26:14.51#ibcon#about to read 6, iclass 24, count 0 2006.257.05:26:14.52#ibcon#read 6, iclass 24, count 0 2006.257.05:26:14.52#ibcon#end of sib2, iclass 24, count 0 2006.257.05:26:14.52#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:26:14.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:26:14.52#ibcon#[27=USB\r\n] 2006.257.05:26:14.52#ibcon#*before write, iclass 24, count 0 2006.257.05:26:14.52#ibcon#enter sib2, iclass 24, count 0 2006.257.05:26:14.52#ibcon#flushed, iclass 24, count 0 2006.257.05:26:14.52#ibcon#about to write, iclass 24, count 0 2006.257.05:26:14.52#ibcon#wrote, iclass 24, count 0 2006.257.05:26:14.52#ibcon#about to read 3, iclass 24, count 0 2006.257.05:26:14.54#ibcon#read 3, iclass 24, count 0 2006.257.05:26:14.54#ibcon#about to read 4, iclass 24, count 0 2006.257.05:26:14.54#ibcon#read 4, iclass 24, count 0 2006.257.05:26:14.54#ibcon#about to read 5, iclass 24, count 0 2006.257.05:26:14.55#ibcon#read 5, iclass 24, count 0 2006.257.05:26:14.55#ibcon#about to read 6, iclass 24, count 0 2006.257.05:26:14.55#ibcon#read 6, iclass 24, count 0 2006.257.05:26:14.55#ibcon#end of sib2, iclass 24, count 0 2006.257.05:26:14.55#ibcon#*after write, iclass 24, count 0 2006.257.05:26:14.55#ibcon#*before return 0, iclass 24, count 0 2006.257.05:26:14.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:14.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:26:14.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:26:14.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:26:14.55$vck44/vblo=6,719.99 2006.257.05:26:14.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.05:26:14.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.05:26:14.55#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:14.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:14.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:14.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:14.55#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:26:14.55#ibcon#first serial, iclass 26, count 0 2006.257.05:26:14.55#ibcon#enter sib2, iclass 26, count 0 2006.257.05:26:14.55#ibcon#flushed, iclass 26, count 0 2006.257.05:26:14.55#ibcon#about to write, iclass 26, count 0 2006.257.05:26:14.55#ibcon#wrote, iclass 26, count 0 2006.257.05:26:14.55#ibcon#about to read 3, iclass 26, count 0 2006.257.05:26:14.56#ibcon#read 3, iclass 26, count 0 2006.257.05:26:14.56#ibcon#about to read 4, iclass 26, count 0 2006.257.05:26:14.56#ibcon#read 4, iclass 26, count 0 2006.257.05:26:14.56#ibcon#about to read 5, iclass 26, count 0 2006.257.05:26:14.56#ibcon#read 5, iclass 26, count 0 2006.257.05:26:14.56#ibcon#about to read 6, iclass 26, count 0 2006.257.05:26:14.57#ibcon#read 6, iclass 26, count 0 2006.257.05:26:14.57#ibcon#end of sib2, iclass 26, count 0 2006.257.05:26:14.57#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:26:14.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:26:14.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:26:14.57#ibcon#*before write, iclass 26, count 0 2006.257.05:26:14.57#ibcon#enter sib2, iclass 26, count 0 2006.257.05:26:14.57#ibcon#flushed, iclass 26, count 0 2006.257.05:26:14.57#ibcon#about to write, iclass 26, count 0 2006.257.05:26:14.57#ibcon#wrote, iclass 26, count 0 2006.257.05:26:14.57#ibcon#about to read 3, iclass 26, count 0 2006.257.05:26:14.60#ibcon#read 3, iclass 26, count 0 2006.257.05:26:14.60#ibcon#about to read 4, iclass 26, count 0 2006.257.05:26:14.60#ibcon#read 4, iclass 26, count 0 2006.257.05:26:14.60#ibcon#about to read 5, iclass 26, count 0 2006.257.05:26:14.61#ibcon#read 5, iclass 26, count 0 2006.257.05:26:14.61#ibcon#about to read 6, iclass 26, count 0 2006.257.05:26:14.61#ibcon#read 6, iclass 26, count 0 2006.257.05:26:14.61#ibcon#end of sib2, iclass 26, count 0 2006.257.05:26:14.61#ibcon#*after write, iclass 26, count 0 2006.257.05:26:14.61#ibcon#*before return 0, iclass 26, count 0 2006.257.05:26:14.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:14.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:26:14.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:26:14.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:26:14.61$vck44/vb=6,4 2006.257.05:26:14.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.05:26:14.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.05:26:14.61#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:14.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:14.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:14.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:14.66#ibcon#enter wrdev, iclass 28, count 2 2006.257.05:26:14.66#ibcon#first serial, iclass 28, count 2 2006.257.05:26:14.66#ibcon#enter sib2, iclass 28, count 2 2006.257.05:26:14.67#ibcon#flushed, iclass 28, count 2 2006.257.05:26:14.67#ibcon#about to write, iclass 28, count 2 2006.257.05:26:14.67#ibcon#wrote, iclass 28, count 2 2006.257.05:26:14.67#ibcon#about to read 3, iclass 28, count 2 2006.257.05:26:14.68#ibcon#read 3, iclass 28, count 2 2006.257.05:26:14.68#ibcon#about to read 4, iclass 28, count 2 2006.257.05:26:14.68#ibcon#read 4, iclass 28, count 2 2006.257.05:26:14.68#ibcon#about to read 5, iclass 28, count 2 2006.257.05:26:14.69#ibcon#read 5, iclass 28, count 2 2006.257.05:26:14.69#ibcon#about to read 6, iclass 28, count 2 2006.257.05:26:14.69#ibcon#read 6, iclass 28, count 2 2006.257.05:26:14.69#ibcon#end of sib2, iclass 28, count 2 2006.257.05:26:14.69#ibcon#*mode == 0, iclass 28, count 2 2006.257.05:26:14.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.05:26:14.69#ibcon#[27=AT06-04\r\n] 2006.257.05:26:14.69#ibcon#*before write, iclass 28, count 2 2006.257.05:26:14.69#ibcon#enter sib2, iclass 28, count 2 2006.257.05:26:14.69#ibcon#flushed, iclass 28, count 2 2006.257.05:26:14.69#ibcon#about to write, iclass 28, count 2 2006.257.05:26:14.69#ibcon#wrote, iclass 28, count 2 2006.257.05:26:14.69#ibcon#about to read 3, iclass 28, count 2 2006.257.05:26:14.71#ibcon#read 3, iclass 28, count 2 2006.257.05:26:14.71#ibcon#about to read 4, iclass 28, count 2 2006.257.05:26:14.71#ibcon#read 4, iclass 28, count 2 2006.257.05:26:14.71#ibcon#about to read 5, iclass 28, count 2 2006.257.05:26:14.71#ibcon#read 5, iclass 28, count 2 2006.257.05:26:14.71#ibcon#about to read 6, iclass 28, count 2 2006.257.05:26:14.71#ibcon#read 6, iclass 28, count 2 2006.257.05:26:14.72#ibcon#end of sib2, iclass 28, count 2 2006.257.05:26:14.72#ibcon#*after write, iclass 28, count 2 2006.257.05:26:14.72#ibcon#*before return 0, iclass 28, count 2 2006.257.05:26:14.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:14.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:26:14.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.05:26:14.72#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:14.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:14.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:14.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:14.83#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:26:14.83#ibcon#first serial, iclass 28, count 0 2006.257.05:26:14.83#ibcon#enter sib2, iclass 28, count 0 2006.257.05:26:14.84#ibcon#flushed, iclass 28, count 0 2006.257.05:26:14.84#ibcon#about to write, iclass 28, count 0 2006.257.05:26:14.84#ibcon#wrote, iclass 28, count 0 2006.257.05:26:14.84#ibcon#about to read 3, iclass 28, count 0 2006.257.05:26:14.85#ibcon#read 3, iclass 28, count 0 2006.257.05:26:14.85#ibcon#about to read 4, iclass 28, count 0 2006.257.05:26:14.85#ibcon#read 4, iclass 28, count 0 2006.257.05:26:14.86#ibcon#about to read 5, iclass 28, count 0 2006.257.05:26:14.86#ibcon#read 5, iclass 28, count 0 2006.257.05:26:14.86#ibcon#about to read 6, iclass 28, count 0 2006.257.05:26:14.86#ibcon#read 6, iclass 28, count 0 2006.257.05:26:14.86#ibcon#end of sib2, iclass 28, count 0 2006.257.05:26:14.86#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:26:14.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:26:14.86#ibcon#[27=USB\r\n] 2006.257.05:26:14.86#ibcon#*before write, iclass 28, count 0 2006.257.05:26:14.86#ibcon#enter sib2, iclass 28, count 0 2006.257.05:26:14.86#ibcon#flushed, iclass 28, count 0 2006.257.05:26:14.86#ibcon#about to write, iclass 28, count 0 2006.257.05:26:14.86#ibcon#wrote, iclass 28, count 0 2006.257.05:26:14.86#ibcon#about to read 3, iclass 28, count 0 2006.257.05:26:14.88#ibcon#read 3, iclass 28, count 0 2006.257.05:26:14.88#ibcon#about to read 4, iclass 28, count 0 2006.257.05:26:14.88#ibcon#read 4, iclass 28, count 0 2006.257.05:26:14.88#ibcon#about to read 5, iclass 28, count 0 2006.257.05:26:14.89#ibcon#read 5, iclass 28, count 0 2006.257.05:26:14.89#ibcon#about to read 6, iclass 28, count 0 2006.257.05:26:14.89#ibcon#read 6, iclass 28, count 0 2006.257.05:26:14.89#ibcon#end of sib2, iclass 28, count 0 2006.257.05:26:14.89#ibcon#*after write, iclass 28, count 0 2006.257.05:26:14.89#ibcon#*before return 0, iclass 28, count 0 2006.257.05:26:14.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:14.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:26:14.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:26:14.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:26:14.89$vck44/vblo=7,734.99 2006.257.05:26:14.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.05:26:14.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.05:26:14.89#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:14.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:14.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:14.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:14.89#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:26:14.89#ibcon#first serial, iclass 30, count 0 2006.257.05:26:14.89#ibcon#enter sib2, iclass 30, count 0 2006.257.05:26:14.89#ibcon#flushed, iclass 30, count 0 2006.257.05:26:14.89#ibcon#about to write, iclass 30, count 0 2006.257.05:26:14.89#ibcon#wrote, iclass 30, count 0 2006.257.05:26:14.89#ibcon#about to read 3, iclass 30, count 0 2006.257.05:26:14.90#ibcon#read 3, iclass 30, count 0 2006.257.05:26:14.90#ibcon#about to read 4, iclass 30, count 0 2006.257.05:26:14.90#ibcon#read 4, iclass 30, count 0 2006.257.05:26:14.90#ibcon#about to read 5, iclass 30, count 0 2006.257.05:26:14.90#ibcon#read 5, iclass 30, count 0 2006.257.05:26:14.91#ibcon#about to read 6, iclass 30, count 0 2006.257.05:26:14.91#ibcon#read 6, iclass 30, count 0 2006.257.05:26:14.91#ibcon#end of sib2, iclass 30, count 0 2006.257.05:26:14.91#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:26:14.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:26:14.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:26:14.91#ibcon#*before write, iclass 30, count 0 2006.257.05:26:14.91#ibcon#enter sib2, iclass 30, count 0 2006.257.05:26:14.91#ibcon#flushed, iclass 30, count 0 2006.257.05:26:14.91#ibcon#about to write, iclass 30, count 0 2006.257.05:26:14.91#ibcon#wrote, iclass 30, count 0 2006.257.05:26:14.91#ibcon#about to read 3, iclass 30, count 0 2006.257.05:26:14.94#ibcon#read 3, iclass 30, count 0 2006.257.05:26:14.94#ibcon#about to read 4, iclass 30, count 0 2006.257.05:26:14.94#ibcon#read 4, iclass 30, count 0 2006.257.05:26:14.94#ibcon#about to read 5, iclass 30, count 0 2006.257.05:26:14.94#ibcon#read 5, iclass 30, count 0 2006.257.05:26:14.95#ibcon#about to read 6, iclass 30, count 0 2006.257.05:26:14.95#ibcon#read 6, iclass 30, count 0 2006.257.05:26:14.95#ibcon#end of sib2, iclass 30, count 0 2006.257.05:26:14.95#ibcon#*after write, iclass 30, count 0 2006.257.05:26:14.95#ibcon#*before return 0, iclass 30, count 0 2006.257.05:26:14.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:14.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:26:14.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:26:14.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:26:14.95$vck44/vb=7,4 2006.257.05:26:14.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.05:26:14.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.05:26:14.95#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:14.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:15.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:15.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:15.01#ibcon#enter wrdev, iclass 32, count 2 2006.257.05:26:15.01#ibcon#first serial, iclass 32, count 2 2006.257.05:26:15.01#ibcon#enter sib2, iclass 32, count 2 2006.257.05:26:15.01#ibcon#flushed, iclass 32, count 2 2006.257.05:26:15.01#ibcon#about to write, iclass 32, count 2 2006.257.05:26:15.01#ibcon#wrote, iclass 32, count 2 2006.257.05:26:15.01#ibcon#about to read 3, iclass 32, count 2 2006.257.05:26:15.02#ibcon#read 3, iclass 32, count 2 2006.257.05:26:15.02#ibcon#about to read 4, iclass 32, count 2 2006.257.05:26:15.02#ibcon#read 4, iclass 32, count 2 2006.257.05:26:15.02#ibcon#about to read 5, iclass 32, count 2 2006.257.05:26:15.03#ibcon#read 5, iclass 32, count 2 2006.257.05:26:15.03#ibcon#about to read 6, iclass 32, count 2 2006.257.05:26:15.03#ibcon#read 6, iclass 32, count 2 2006.257.05:26:15.03#ibcon#end of sib2, iclass 32, count 2 2006.257.05:26:15.03#ibcon#*mode == 0, iclass 32, count 2 2006.257.05:26:15.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.05:26:15.03#ibcon#[27=AT07-04\r\n] 2006.257.05:26:15.03#ibcon#*before write, iclass 32, count 2 2006.257.05:26:15.03#ibcon#enter sib2, iclass 32, count 2 2006.257.05:26:15.03#ibcon#flushed, iclass 32, count 2 2006.257.05:26:15.03#ibcon#about to write, iclass 32, count 2 2006.257.05:26:15.03#ibcon#wrote, iclass 32, count 2 2006.257.05:26:15.03#ibcon#about to read 3, iclass 32, count 2 2006.257.05:26:15.05#ibcon#read 3, iclass 32, count 2 2006.257.05:26:15.05#ibcon#about to read 4, iclass 32, count 2 2006.257.05:26:15.05#ibcon#read 4, iclass 32, count 2 2006.257.05:26:15.05#ibcon#about to read 5, iclass 32, count 2 2006.257.05:26:15.06#ibcon#read 5, iclass 32, count 2 2006.257.05:26:15.06#ibcon#about to read 6, iclass 32, count 2 2006.257.05:26:15.06#ibcon#read 6, iclass 32, count 2 2006.257.05:26:15.06#ibcon#end of sib2, iclass 32, count 2 2006.257.05:26:15.06#ibcon#*after write, iclass 32, count 2 2006.257.05:26:15.06#ibcon#*before return 0, iclass 32, count 2 2006.257.05:26:15.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:15.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:26:15.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.05:26:15.06#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:15.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:15.17#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:15.17#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:15.17#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:26:15.17#ibcon#first serial, iclass 32, count 0 2006.257.05:26:15.17#ibcon#enter sib2, iclass 32, count 0 2006.257.05:26:15.17#ibcon#flushed, iclass 32, count 0 2006.257.05:26:15.18#ibcon#about to write, iclass 32, count 0 2006.257.05:26:15.18#ibcon#wrote, iclass 32, count 0 2006.257.05:26:15.18#ibcon#about to read 3, iclass 32, count 0 2006.257.05:26:15.19#ibcon#read 3, iclass 32, count 0 2006.257.05:26:15.19#ibcon#about to read 4, iclass 32, count 0 2006.257.05:26:15.19#ibcon#read 4, iclass 32, count 0 2006.257.05:26:15.19#ibcon#about to read 5, iclass 32, count 0 2006.257.05:26:15.19#ibcon#read 5, iclass 32, count 0 2006.257.05:26:15.19#ibcon#about to read 6, iclass 32, count 0 2006.257.05:26:15.19#ibcon#read 6, iclass 32, count 0 2006.257.05:26:15.20#ibcon#end of sib2, iclass 32, count 0 2006.257.05:26:15.20#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:26:15.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:26:15.20#ibcon#[27=USB\r\n] 2006.257.05:26:15.20#ibcon#*before write, iclass 32, count 0 2006.257.05:26:15.20#ibcon#enter sib2, iclass 32, count 0 2006.257.05:26:15.20#ibcon#flushed, iclass 32, count 0 2006.257.05:26:15.20#ibcon#about to write, iclass 32, count 0 2006.257.05:26:15.20#ibcon#wrote, iclass 32, count 0 2006.257.05:26:15.20#ibcon#about to read 3, iclass 32, count 0 2006.257.05:26:15.22#ibcon#read 3, iclass 32, count 0 2006.257.05:26:15.22#ibcon#about to read 4, iclass 32, count 0 2006.257.05:26:15.22#ibcon#read 4, iclass 32, count 0 2006.257.05:26:15.22#ibcon#about to read 5, iclass 32, count 0 2006.257.05:26:15.22#ibcon#read 5, iclass 32, count 0 2006.257.05:26:15.22#ibcon#about to read 6, iclass 32, count 0 2006.257.05:26:15.23#ibcon#read 6, iclass 32, count 0 2006.257.05:26:15.23#ibcon#end of sib2, iclass 32, count 0 2006.257.05:26:15.23#ibcon#*after write, iclass 32, count 0 2006.257.05:26:15.23#ibcon#*before return 0, iclass 32, count 0 2006.257.05:26:15.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:15.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:26:15.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:26:15.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:26:15.23$vck44/vblo=8,744.99 2006.257.05:26:15.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.05:26:15.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.05:26:15.23#ibcon#ireg 17 cls_cnt 0 2006.257.05:26:15.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:15.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:15.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:15.23#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:26:15.23#ibcon#first serial, iclass 34, count 0 2006.257.05:26:15.23#ibcon#enter sib2, iclass 34, count 0 2006.257.05:26:15.23#ibcon#flushed, iclass 34, count 0 2006.257.05:26:15.23#ibcon#about to write, iclass 34, count 0 2006.257.05:26:15.23#ibcon#wrote, iclass 34, count 0 2006.257.05:26:15.23#ibcon#about to read 3, iclass 34, count 0 2006.257.05:26:15.24#ibcon#read 3, iclass 34, count 0 2006.257.05:26:15.24#ibcon#about to read 4, iclass 34, count 0 2006.257.05:26:15.25#ibcon#read 4, iclass 34, count 0 2006.257.05:26:15.25#ibcon#about to read 5, iclass 34, count 0 2006.257.05:26:15.25#ibcon#read 5, iclass 34, count 0 2006.257.05:26:15.25#ibcon#about to read 6, iclass 34, count 0 2006.257.05:26:15.25#ibcon#read 6, iclass 34, count 0 2006.257.05:26:15.25#ibcon#end of sib2, iclass 34, count 0 2006.257.05:26:15.25#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:26:15.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:26:15.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:26:15.25#ibcon#*before write, iclass 34, count 0 2006.257.05:26:15.25#ibcon#enter sib2, iclass 34, count 0 2006.257.05:26:15.25#ibcon#flushed, iclass 34, count 0 2006.257.05:26:15.25#ibcon#about to write, iclass 34, count 0 2006.257.05:26:15.25#ibcon#wrote, iclass 34, count 0 2006.257.05:26:15.25#ibcon#about to read 3, iclass 34, count 0 2006.257.05:26:15.28#ibcon#read 3, iclass 34, count 0 2006.257.05:26:15.28#ibcon#about to read 4, iclass 34, count 0 2006.257.05:26:15.28#ibcon#read 4, iclass 34, count 0 2006.257.05:26:15.28#ibcon#about to read 5, iclass 34, count 0 2006.257.05:26:15.29#ibcon#read 5, iclass 34, count 0 2006.257.05:26:15.29#ibcon#about to read 6, iclass 34, count 0 2006.257.05:26:15.29#ibcon#read 6, iclass 34, count 0 2006.257.05:26:15.29#ibcon#end of sib2, iclass 34, count 0 2006.257.05:26:15.29#ibcon#*after write, iclass 34, count 0 2006.257.05:26:15.29#ibcon#*before return 0, iclass 34, count 0 2006.257.05:26:15.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:15.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:26:15.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:26:15.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:26:15.29$vck44/vb=8,4 2006.257.05:26:15.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.05:26:15.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.05:26:15.29#ibcon#ireg 11 cls_cnt 2 2006.257.05:26:15.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:15.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:15.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:15.34#ibcon#enter wrdev, iclass 36, count 2 2006.257.05:26:15.34#ibcon#first serial, iclass 36, count 2 2006.257.05:26:15.34#ibcon#enter sib2, iclass 36, count 2 2006.257.05:26:15.35#ibcon#flushed, iclass 36, count 2 2006.257.05:26:15.35#ibcon#about to write, iclass 36, count 2 2006.257.05:26:15.35#ibcon#wrote, iclass 36, count 2 2006.257.05:26:15.35#ibcon#about to read 3, iclass 36, count 2 2006.257.05:26:15.36#ibcon#read 3, iclass 36, count 2 2006.257.05:26:15.36#ibcon#about to read 4, iclass 36, count 2 2006.257.05:26:15.36#ibcon#read 4, iclass 36, count 2 2006.257.05:26:15.36#ibcon#about to read 5, iclass 36, count 2 2006.257.05:26:15.37#ibcon#read 5, iclass 36, count 2 2006.257.05:26:15.37#ibcon#about to read 6, iclass 36, count 2 2006.257.05:26:15.37#ibcon#read 6, iclass 36, count 2 2006.257.05:26:15.37#ibcon#end of sib2, iclass 36, count 2 2006.257.05:26:15.37#ibcon#*mode == 0, iclass 36, count 2 2006.257.05:26:15.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.05:26:15.37#ibcon#[27=AT08-04\r\n] 2006.257.05:26:15.37#ibcon#*before write, iclass 36, count 2 2006.257.05:26:15.37#ibcon#enter sib2, iclass 36, count 2 2006.257.05:26:15.37#ibcon#flushed, iclass 36, count 2 2006.257.05:26:15.37#ibcon#about to write, iclass 36, count 2 2006.257.05:26:15.37#ibcon#wrote, iclass 36, count 2 2006.257.05:26:15.37#ibcon#about to read 3, iclass 36, count 2 2006.257.05:26:15.39#ibcon#read 3, iclass 36, count 2 2006.257.05:26:15.39#ibcon#about to read 4, iclass 36, count 2 2006.257.05:26:15.39#ibcon#read 4, iclass 36, count 2 2006.257.05:26:15.39#ibcon#about to read 5, iclass 36, count 2 2006.257.05:26:15.40#ibcon#read 5, iclass 36, count 2 2006.257.05:26:15.40#ibcon#about to read 6, iclass 36, count 2 2006.257.05:26:15.40#ibcon#read 6, iclass 36, count 2 2006.257.05:26:15.40#ibcon#end of sib2, iclass 36, count 2 2006.257.05:26:15.40#ibcon#*after write, iclass 36, count 2 2006.257.05:26:15.40#ibcon#*before return 0, iclass 36, count 2 2006.257.05:26:15.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:15.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:26:15.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.05:26:15.40#ibcon#ireg 7 cls_cnt 0 2006.257.05:26:15.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:15.51#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:15.51#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:15.51#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:26:15.51#ibcon#first serial, iclass 36, count 0 2006.257.05:26:15.51#ibcon#enter sib2, iclass 36, count 0 2006.257.05:26:15.51#ibcon#flushed, iclass 36, count 0 2006.257.05:26:15.52#ibcon#about to write, iclass 36, count 0 2006.257.05:26:15.52#ibcon#wrote, iclass 36, count 0 2006.257.05:26:15.52#ibcon#about to read 3, iclass 36, count 0 2006.257.05:26:15.53#ibcon#read 3, iclass 36, count 0 2006.257.05:26:15.53#ibcon#about to read 4, iclass 36, count 0 2006.257.05:26:15.53#ibcon#read 4, iclass 36, count 0 2006.257.05:26:15.53#ibcon#about to read 5, iclass 36, count 0 2006.257.05:26:15.54#ibcon#read 5, iclass 36, count 0 2006.257.05:26:15.54#ibcon#about to read 6, iclass 36, count 0 2006.257.05:26:15.54#ibcon#read 6, iclass 36, count 0 2006.257.05:26:15.54#ibcon#end of sib2, iclass 36, count 0 2006.257.05:26:15.54#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:26:15.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:26:15.54#ibcon#[27=USB\r\n] 2006.257.05:26:15.54#ibcon#*before write, iclass 36, count 0 2006.257.05:26:15.54#ibcon#enter sib2, iclass 36, count 0 2006.257.05:26:15.54#ibcon#flushed, iclass 36, count 0 2006.257.05:26:15.54#ibcon#about to write, iclass 36, count 0 2006.257.05:26:15.54#ibcon#wrote, iclass 36, count 0 2006.257.05:26:15.54#ibcon#about to read 3, iclass 36, count 0 2006.257.05:26:15.56#ibcon#read 3, iclass 36, count 0 2006.257.05:26:15.56#ibcon#about to read 4, iclass 36, count 0 2006.257.05:26:15.56#ibcon#read 4, iclass 36, count 0 2006.257.05:26:15.56#ibcon#about to read 5, iclass 36, count 0 2006.257.05:26:15.57#ibcon#read 5, iclass 36, count 0 2006.257.05:26:15.57#ibcon#about to read 6, iclass 36, count 0 2006.257.05:26:15.57#ibcon#read 6, iclass 36, count 0 2006.257.05:26:15.57#ibcon#end of sib2, iclass 36, count 0 2006.257.05:26:15.57#ibcon#*after write, iclass 36, count 0 2006.257.05:26:15.57#ibcon#*before return 0, iclass 36, count 0 2006.257.05:26:15.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:15.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:26:15.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:26:15.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:26:15.57$vck44/vabw=wide 2006.257.05:26:15.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.05:26:15.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.05:26:15.57#ibcon#ireg 8 cls_cnt 0 2006.257.05:26:15.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:15.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:15.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:15.57#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:26:15.57#ibcon#first serial, iclass 38, count 0 2006.257.05:26:15.57#ibcon#enter sib2, iclass 38, count 0 2006.257.05:26:15.57#ibcon#flushed, iclass 38, count 0 2006.257.05:26:15.57#ibcon#about to write, iclass 38, count 0 2006.257.05:26:15.57#ibcon#wrote, iclass 38, count 0 2006.257.05:26:15.57#ibcon#about to read 3, iclass 38, count 0 2006.257.05:26:15.58#ibcon#read 3, iclass 38, count 0 2006.257.05:26:15.58#ibcon#about to read 4, iclass 38, count 0 2006.257.05:26:15.58#ibcon#read 4, iclass 38, count 0 2006.257.05:26:15.58#ibcon#about to read 5, iclass 38, count 0 2006.257.05:26:15.58#ibcon#read 5, iclass 38, count 0 2006.257.05:26:15.59#ibcon#about to read 6, iclass 38, count 0 2006.257.05:26:15.59#ibcon#read 6, iclass 38, count 0 2006.257.05:26:15.59#ibcon#end of sib2, iclass 38, count 0 2006.257.05:26:15.59#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:26:15.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:26:15.59#ibcon#[25=BW32\r\n] 2006.257.05:26:15.59#ibcon#*before write, iclass 38, count 0 2006.257.05:26:15.59#ibcon#enter sib2, iclass 38, count 0 2006.257.05:26:15.59#ibcon#flushed, iclass 38, count 0 2006.257.05:26:15.59#ibcon#about to write, iclass 38, count 0 2006.257.05:26:15.59#ibcon#wrote, iclass 38, count 0 2006.257.05:26:15.59#ibcon#about to read 3, iclass 38, count 0 2006.257.05:26:15.61#ibcon#read 3, iclass 38, count 0 2006.257.05:26:15.61#ibcon#about to read 4, iclass 38, count 0 2006.257.05:26:15.61#ibcon#read 4, iclass 38, count 0 2006.257.05:26:15.61#ibcon#about to read 5, iclass 38, count 0 2006.257.05:26:15.61#ibcon#read 5, iclass 38, count 0 2006.257.05:26:15.62#ibcon#about to read 6, iclass 38, count 0 2006.257.05:26:15.62#ibcon#read 6, iclass 38, count 0 2006.257.05:26:15.62#ibcon#end of sib2, iclass 38, count 0 2006.257.05:26:15.62#ibcon#*after write, iclass 38, count 0 2006.257.05:26:15.62#ibcon#*before return 0, iclass 38, count 0 2006.257.05:26:15.62#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:15.62#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:26:15.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:26:15.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:26:15.62$vck44/vbbw=wide 2006.257.05:26:15.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.05:26:15.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.05:26:15.62#ibcon#ireg 8 cls_cnt 0 2006.257.05:26:15.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:26:15.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:26:15.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:26:15.68#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:26:15.68#ibcon#first serial, iclass 40, count 0 2006.257.05:26:15.68#ibcon#enter sib2, iclass 40, count 0 2006.257.05:26:15.69#ibcon#flushed, iclass 40, count 0 2006.257.05:26:15.69#ibcon#about to write, iclass 40, count 0 2006.257.05:26:15.69#ibcon#wrote, iclass 40, count 0 2006.257.05:26:15.69#ibcon#about to read 3, iclass 40, count 0 2006.257.05:26:15.70#ibcon#read 3, iclass 40, count 0 2006.257.05:26:15.70#ibcon#about to read 4, iclass 40, count 0 2006.257.05:26:15.70#ibcon#read 4, iclass 40, count 0 2006.257.05:26:15.70#ibcon#about to read 5, iclass 40, count 0 2006.257.05:26:15.70#ibcon#read 5, iclass 40, count 0 2006.257.05:26:15.70#ibcon#about to read 6, iclass 40, count 0 2006.257.05:26:15.71#ibcon#read 6, iclass 40, count 0 2006.257.05:26:15.71#ibcon#end of sib2, iclass 40, count 0 2006.257.05:26:15.71#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:26:15.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:26:15.71#ibcon#[27=BW32\r\n] 2006.257.05:26:15.71#ibcon#*before write, iclass 40, count 0 2006.257.05:26:15.71#ibcon#enter sib2, iclass 40, count 0 2006.257.05:26:15.71#ibcon#flushed, iclass 40, count 0 2006.257.05:26:15.71#ibcon#about to write, iclass 40, count 0 2006.257.05:26:15.71#ibcon#wrote, iclass 40, count 0 2006.257.05:26:15.71#ibcon#about to read 3, iclass 40, count 0 2006.257.05:26:15.73#ibcon#read 3, iclass 40, count 0 2006.257.05:26:15.74#ibcon#about to read 4, iclass 40, count 0 2006.257.05:26:15.74#ibcon#read 4, iclass 40, count 0 2006.257.05:26:15.74#ibcon#about to read 5, iclass 40, count 0 2006.257.05:26:15.74#ibcon#read 5, iclass 40, count 0 2006.257.05:26:15.74#ibcon#about to read 6, iclass 40, count 0 2006.257.05:26:15.74#ibcon#read 6, iclass 40, count 0 2006.257.05:26:15.74#ibcon#end of sib2, iclass 40, count 0 2006.257.05:26:15.74#ibcon#*after write, iclass 40, count 0 2006.257.05:26:15.74#ibcon#*before return 0, iclass 40, count 0 2006.257.05:26:15.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:26:15.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:26:15.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:26:15.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:26:15.74$setupk4/ifdk4 2006.257.05:26:15.74$ifdk4/lo= 2006.257.05:26:15.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:26:15.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:26:15.74$ifdk4/patch= 2006.257.05:26:15.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:26:15.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:26:15.74$setupk4/!*+20s 2006.257.05:26:17.23#abcon#<5=/15 1.1 3.0 19.96 911012.2\r\n> 2006.257.05:26:17.25#abcon#{5=INTERFACE CLEAR} 2006.257.05:26:17.31#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:26:23.13#trakl#Source acquired 2006.257.05:26:23.14#flagr#flagr/antenna,acquired 2006.257.05:26:27.40#abcon#<5=/15 1.1 3.0 19.97 911012.2\r\n> 2006.257.05:26:27.42#abcon#{5=INTERFACE CLEAR} 2006.257.05:26:27.48#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:26:30.25$setupk4/"tpicd 2006.257.05:26:30.26$setupk4/echo=off 2006.257.05:26:30.26$setupk4/xlog=off 2006.257.05:26:30.26:!2006.257.05:27:26 2006.257.05:27:26.02:preob 2006.257.05:27:27.15/onsource/TRACKING 2006.257.05:27:27.15:!2006.257.05:27:36 2006.257.05:27:36.02:"tape 2006.257.05:27:36.02:"st=record 2006.257.05:27:36.02:data_valid=on 2006.257.05:27:36.02:midob 2006.257.05:27:37.15/onsource/TRACKING 2006.257.05:27:37.15/wx/19.97,1012.2,91 2006.257.05:27:37.26/cable/+6.4811E-03 2006.257.05:27:38.35/va/01,08,usb,yes,33,35 2006.257.05:27:38.35/va/02,07,usb,yes,36,36 2006.257.05:27:38.35/va/03,08,usb,yes,32,34 2006.257.05:27:38.35/va/04,07,usb,yes,37,38 2006.257.05:27:38.35/va/05,04,usb,yes,33,33 2006.257.05:27:38.35/va/06,04,usb,yes,37,36 2006.257.05:27:38.35/va/07,04,usb,yes,38,38 2006.257.05:27:38.35/va/08,04,usb,yes,31,38 2006.257.05:27:38.58/valo/01,524.99,yes,locked 2006.257.05:27:38.58/valo/02,534.99,yes,locked 2006.257.05:27:38.58/valo/03,564.99,yes,locked 2006.257.05:27:38.58/valo/04,624.99,yes,locked 2006.257.05:27:38.58/valo/05,734.99,yes,locked 2006.257.05:27:38.58/valo/06,814.99,yes,locked 2006.257.05:27:38.58/valo/07,864.99,yes,locked 2006.257.05:27:38.58/valo/08,884.99,yes,locked 2006.257.05:27:39.67/vb/01,04,usb,yes,31,29 2006.257.05:27:39.67/vb/02,05,usb,yes,29,29 2006.257.05:27:39.67/vb/03,04,usb,yes,30,33 2006.257.05:27:39.67/vb/04,05,usb,yes,31,30 2006.257.05:27:39.67/vb/05,04,usb,yes,27,30 2006.257.05:27:39.67/vb/06,04,usb,yes,32,28 2006.257.05:27:39.67/vb/07,04,usb,yes,31,31 2006.257.05:27:39.67/vb/08,04,usb,yes,29,32 2006.257.05:27:39.91/vblo/01,629.99,yes,locked 2006.257.05:27:39.91/vblo/02,634.99,yes,locked 2006.257.05:27:39.91/vblo/03,649.99,yes,locked 2006.257.05:27:39.91/vblo/04,679.99,yes,locked 2006.257.05:27:39.91/vblo/05,709.99,yes,locked 2006.257.05:27:39.91/vblo/06,719.99,yes,locked 2006.257.05:27:39.91/vblo/07,734.99,yes,locked 2006.257.05:27:39.91/vblo/08,744.99,yes,locked 2006.257.05:27:40.06/vabw/8 2006.257.05:27:40.21/vbbw/8 2006.257.05:27:40.30/xfe/off,on,16.7 2006.257.05:27:40.68/ifatt/23,28,28,28 2006.257.05:27:41.07/fmout-gps/S +4.57E-07 2006.257.05:27:41.11:!2006.257.05:32:36 2006.257.05:32:36.01:data_valid=off 2006.257.05:32:36.02:"et 2006.257.05:32:36.02:!+3s 2006.257.05:32:39.04:"tape 2006.257.05:32:39.05:postob 2006.257.05:32:39.10/cable/+6.4806E-03 2006.257.05:32:39.11/wx/20.02,1012.2,90 2006.257.05:32:39.16/fmout-gps/S +4.55E-07 2006.257.05:32:39.16:scan_name=257-0536,jd0609,50 2006.257.05:32:39.16:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.05:32:40.14#flagr#flagr/antenna,new-source 2006.257.05:32:40.15:checkk5 2006.257.05:32:40.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:32:40.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:32:41.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:32:41.81/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:32:42.20/chk_obsdata//k5ts1/T2570527??a.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.257.05:32:42.59/chk_obsdata//k5ts2/T2570527??b.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.257.05:32:42.99/chk_obsdata//k5ts3/T2570527??c.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.257.05:32:43.39/chk_obsdata//k5ts4/T2570527??d.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.257.05:32:44.16/k5log//k5ts1_log_newline 2006.257.05:32:44.88/k5log//k5ts2_log_newline 2006.257.05:32:45.64/k5log//k5ts3_log_newline 2006.257.05:32:46.35/k5log//k5ts4_log_newline 2006.257.05:32:46.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:32:46.38:setupk4=1 2006.257.05:32:46.38$setupk4/echo=on 2006.257.05:32:46.38$setupk4/pcalon 2006.257.05:32:46.38$pcalon/"no phase cal control is implemented here 2006.257.05:32:46.38$setupk4/"tpicd=stop 2006.257.05:32:46.38$setupk4/"rec=synch_on 2006.257.05:32:46.38$setupk4/"rec_mode=128 2006.257.05:32:46.38$setupk4/!* 2006.257.05:32:46.38$setupk4/recpk4 2006.257.05:32:46.38$recpk4/recpatch= 2006.257.05:32:46.38$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:32:46.38$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:32:46.38$setupk4/vck44 2006.257.05:32:46.38$vck44/valo=1,524.99 2006.257.05:32:46.38#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.05:32:46.38#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.05:32:46.38#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:46.38#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:46.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:46.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:46.38#ibcon#enter wrdev, iclass 21, count 0 2006.257.05:32:46.38#ibcon#first serial, iclass 21, count 0 2006.257.05:32:46.38#ibcon#enter sib2, iclass 21, count 0 2006.257.05:32:46.38#ibcon#flushed, iclass 21, count 0 2006.257.05:32:46.38#ibcon#about to write, iclass 21, count 0 2006.257.05:32:46.38#ibcon#wrote, iclass 21, count 0 2006.257.05:32:46.38#ibcon#about to read 3, iclass 21, count 0 2006.257.05:32:46.40#ibcon#read 3, iclass 21, count 0 2006.257.05:32:46.40#ibcon#about to read 4, iclass 21, count 0 2006.257.05:32:46.40#ibcon#read 4, iclass 21, count 0 2006.257.05:32:46.40#ibcon#about to read 5, iclass 21, count 0 2006.257.05:32:46.40#ibcon#read 5, iclass 21, count 0 2006.257.05:32:46.40#ibcon#about to read 6, iclass 21, count 0 2006.257.05:32:46.40#ibcon#read 6, iclass 21, count 0 2006.257.05:32:46.40#ibcon#end of sib2, iclass 21, count 0 2006.257.05:32:46.40#ibcon#*mode == 0, iclass 21, count 0 2006.257.05:32:46.40#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.05:32:46.40#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:32:46.40#ibcon#*before write, iclass 21, count 0 2006.257.05:32:46.40#ibcon#enter sib2, iclass 21, count 0 2006.257.05:32:46.40#ibcon#flushed, iclass 21, count 0 2006.257.05:32:46.40#ibcon#about to write, iclass 21, count 0 2006.257.05:32:46.40#ibcon#wrote, iclass 21, count 0 2006.257.05:32:46.40#ibcon#about to read 3, iclass 21, count 0 2006.257.05:32:46.45#ibcon#read 3, iclass 21, count 0 2006.257.05:32:46.45#ibcon#about to read 4, iclass 21, count 0 2006.257.05:32:46.45#ibcon#read 4, iclass 21, count 0 2006.257.05:32:46.45#ibcon#about to read 5, iclass 21, count 0 2006.257.05:32:46.45#ibcon#read 5, iclass 21, count 0 2006.257.05:32:46.45#ibcon#about to read 6, iclass 21, count 0 2006.257.05:32:46.45#ibcon#read 6, iclass 21, count 0 2006.257.05:32:46.45#ibcon#end of sib2, iclass 21, count 0 2006.257.05:32:46.45#ibcon#*after write, iclass 21, count 0 2006.257.05:32:46.45#ibcon#*before return 0, iclass 21, count 0 2006.257.05:32:46.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:46.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:46.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.05:32:46.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.05:32:46.45$vck44/va=1,8 2006.257.05:32:46.45#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.05:32:46.45#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.05:32:46.45#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:46.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:46.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:46.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:46.45#ibcon#enter wrdev, iclass 23, count 2 2006.257.05:32:46.45#ibcon#first serial, iclass 23, count 2 2006.257.05:32:46.45#ibcon#enter sib2, iclass 23, count 2 2006.257.05:32:46.45#ibcon#flushed, iclass 23, count 2 2006.257.05:32:46.45#ibcon#about to write, iclass 23, count 2 2006.257.05:32:46.45#ibcon#wrote, iclass 23, count 2 2006.257.05:32:46.45#ibcon#about to read 3, iclass 23, count 2 2006.257.05:32:46.47#ibcon#read 3, iclass 23, count 2 2006.257.05:32:46.47#ibcon#about to read 4, iclass 23, count 2 2006.257.05:32:46.47#ibcon#read 4, iclass 23, count 2 2006.257.05:32:46.47#ibcon#about to read 5, iclass 23, count 2 2006.257.05:32:46.47#ibcon#read 5, iclass 23, count 2 2006.257.05:32:46.47#ibcon#about to read 6, iclass 23, count 2 2006.257.05:32:46.47#ibcon#read 6, iclass 23, count 2 2006.257.05:32:46.47#ibcon#end of sib2, iclass 23, count 2 2006.257.05:32:46.47#ibcon#*mode == 0, iclass 23, count 2 2006.257.05:32:46.47#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.05:32:46.47#ibcon#[25=AT01-08\r\n] 2006.257.05:32:46.47#ibcon#*before write, iclass 23, count 2 2006.257.05:32:46.47#ibcon#enter sib2, iclass 23, count 2 2006.257.05:32:46.47#ibcon#flushed, iclass 23, count 2 2006.257.05:32:46.47#ibcon#about to write, iclass 23, count 2 2006.257.05:32:46.47#ibcon#wrote, iclass 23, count 2 2006.257.05:32:46.47#ibcon#about to read 3, iclass 23, count 2 2006.257.05:32:46.50#ibcon#read 3, iclass 23, count 2 2006.257.05:32:46.50#ibcon#about to read 4, iclass 23, count 2 2006.257.05:32:46.50#ibcon#read 4, iclass 23, count 2 2006.257.05:32:46.50#ibcon#about to read 5, iclass 23, count 2 2006.257.05:32:46.50#ibcon#read 5, iclass 23, count 2 2006.257.05:32:46.50#ibcon#about to read 6, iclass 23, count 2 2006.257.05:32:46.50#ibcon#read 6, iclass 23, count 2 2006.257.05:32:46.50#ibcon#end of sib2, iclass 23, count 2 2006.257.05:32:46.50#ibcon#*after write, iclass 23, count 2 2006.257.05:32:46.50#ibcon#*before return 0, iclass 23, count 2 2006.257.05:32:46.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:46.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:46.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.05:32:46.50#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:46.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:46.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:46.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:46.62#ibcon#enter wrdev, iclass 23, count 0 2006.257.05:32:46.62#ibcon#first serial, iclass 23, count 0 2006.257.05:32:46.62#ibcon#enter sib2, iclass 23, count 0 2006.257.05:32:46.62#ibcon#flushed, iclass 23, count 0 2006.257.05:32:46.62#ibcon#about to write, iclass 23, count 0 2006.257.05:32:46.62#ibcon#wrote, iclass 23, count 0 2006.257.05:32:46.62#ibcon#about to read 3, iclass 23, count 0 2006.257.05:32:46.64#ibcon#read 3, iclass 23, count 0 2006.257.05:32:46.64#ibcon#about to read 4, iclass 23, count 0 2006.257.05:32:46.64#ibcon#read 4, iclass 23, count 0 2006.257.05:32:46.64#ibcon#about to read 5, iclass 23, count 0 2006.257.05:32:46.64#ibcon#read 5, iclass 23, count 0 2006.257.05:32:46.64#ibcon#about to read 6, iclass 23, count 0 2006.257.05:32:46.64#ibcon#read 6, iclass 23, count 0 2006.257.05:32:46.64#ibcon#end of sib2, iclass 23, count 0 2006.257.05:32:46.64#ibcon#*mode == 0, iclass 23, count 0 2006.257.05:32:46.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.05:32:46.64#ibcon#[25=USB\r\n] 2006.257.05:32:46.64#ibcon#*before write, iclass 23, count 0 2006.257.05:32:46.64#ibcon#enter sib2, iclass 23, count 0 2006.257.05:32:46.64#ibcon#flushed, iclass 23, count 0 2006.257.05:32:46.64#ibcon#about to write, iclass 23, count 0 2006.257.05:32:46.64#ibcon#wrote, iclass 23, count 0 2006.257.05:32:46.64#ibcon#about to read 3, iclass 23, count 0 2006.257.05:32:46.67#ibcon#read 3, iclass 23, count 0 2006.257.05:32:46.67#ibcon#about to read 4, iclass 23, count 0 2006.257.05:32:46.67#ibcon#read 4, iclass 23, count 0 2006.257.05:32:46.67#ibcon#about to read 5, iclass 23, count 0 2006.257.05:32:46.67#ibcon#read 5, iclass 23, count 0 2006.257.05:32:46.67#ibcon#about to read 6, iclass 23, count 0 2006.257.05:32:46.67#ibcon#read 6, iclass 23, count 0 2006.257.05:32:46.67#ibcon#end of sib2, iclass 23, count 0 2006.257.05:32:46.67#ibcon#*after write, iclass 23, count 0 2006.257.05:32:46.67#ibcon#*before return 0, iclass 23, count 0 2006.257.05:32:46.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:46.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:46.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.05:32:46.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.05:32:46.67$vck44/valo=2,534.99 2006.257.05:32:46.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.05:32:46.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.05:32:46.67#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:46.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:46.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:46.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:46.67#ibcon#enter wrdev, iclass 25, count 0 2006.257.05:32:46.67#ibcon#first serial, iclass 25, count 0 2006.257.05:32:46.67#ibcon#enter sib2, iclass 25, count 0 2006.257.05:32:46.67#ibcon#flushed, iclass 25, count 0 2006.257.05:32:46.67#ibcon#about to write, iclass 25, count 0 2006.257.05:32:46.67#ibcon#wrote, iclass 25, count 0 2006.257.05:32:46.67#ibcon#about to read 3, iclass 25, count 0 2006.257.05:32:46.69#ibcon#read 3, iclass 25, count 0 2006.257.05:32:46.69#ibcon#about to read 4, iclass 25, count 0 2006.257.05:32:46.69#ibcon#read 4, iclass 25, count 0 2006.257.05:32:46.69#ibcon#about to read 5, iclass 25, count 0 2006.257.05:32:46.69#ibcon#read 5, iclass 25, count 0 2006.257.05:32:46.69#ibcon#about to read 6, iclass 25, count 0 2006.257.05:32:46.69#ibcon#read 6, iclass 25, count 0 2006.257.05:32:46.69#ibcon#end of sib2, iclass 25, count 0 2006.257.05:32:46.69#ibcon#*mode == 0, iclass 25, count 0 2006.257.05:32:46.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.05:32:46.69#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:32:46.69#ibcon#*before write, iclass 25, count 0 2006.257.05:32:46.69#ibcon#enter sib2, iclass 25, count 0 2006.257.05:32:46.69#ibcon#flushed, iclass 25, count 0 2006.257.05:32:46.69#ibcon#about to write, iclass 25, count 0 2006.257.05:32:46.69#ibcon#wrote, iclass 25, count 0 2006.257.05:32:46.69#ibcon#about to read 3, iclass 25, count 0 2006.257.05:32:46.73#ibcon#read 3, iclass 25, count 0 2006.257.05:32:46.73#ibcon#about to read 4, iclass 25, count 0 2006.257.05:32:46.73#ibcon#read 4, iclass 25, count 0 2006.257.05:32:46.73#ibcon#about to read 5, iclass 25, count 0 2006.257.05:32:46.73#ibcon#read 5, iclass 25, count 0 2006.257.05:32:46.73#ibcon#about to read 6, iclass 25, count 0 2006.257.05:32:46.73#ibcon#read 6, iclass 25, count 0 2006.257.05:32:46.73#ibcon#end of sib2, iclass 25, count 0 2006.257.05:32:46.73#ibcon#*after write, iclass 25, count 0 2006.257.05:32:46.73#ibcon#*before return 0, iclass 25, count 0 2006.257.05:32:46.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:46.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:46.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.05:32:46.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.05:32:46.73$vck44/va=2,7 2006.257.05:32:46.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.05:32:46.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.05:32:46.73#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:46.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:46.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:46.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:46.79#ibcon#enter wrdev, iclass 27, count 2 2006.257.05:32:46.79#ibcon#first serial, iclass 27, count 2 2006.257.05:32:46.79#ibcon#enter sib2, iclass 27, count 2 2006.257.05:32:46.79#ibcon#flushed, iclass 27, count 2 2006.257.05:32:46.79#ibcon#about to write, iclass 27, count 2 2006.257.05:32:46.79#ibcon#wrote, iclass 27, count 2 2006.257.05:32:46.79#ibcon#about to read 3, iclass 27, count 2 2006.257.05:32:46.81#ibcon#read 3, iclass 27, count 2 2006.257.05:32:46.81#ibcon#about to read 4, iclass 27, count 2 2006.257.05:32:46.81#ibcon#read 4, iclass 27, count 2 2006.257.05:32:46.81#ibcon#about to read 5, iclass 27, count 2 2006.257.05:32:46.81#ibcon#read 5, iclass 27, count 2 2006.257.05:32:46.81#ibcon#about to read 6, iclass 27, count 2 2006.257.05:32:46.81#ibcon#read 6, iclass 27, count 2 2006.257.05:32:46.81#ibcon#end of sib2, iclass 27, count 2 2006.257.05:32:46.81#ibcon#*mode == 0, iclass 27, count 2 2006.257.05:32:46.81#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.05:32:46.81#ibcon#[25=AT02-07\r\n] 2006.257.05:32:46.81#ibcon#*before write, iclass 27, count 2 2006.257.05:32:46.81#ibcon#enter sib2, iclass 27, count 2 2006.257.05:32:46.81#ibcon#flushed, iclass 27, count 2 2006.257.05:32:46.81#ibcon#about to write, iclass 27, count 2 2006.257.05:32:46.81#ibcon#wrote, iclass 27, count 2 2006.257.05:32:46.81#ibcon#about to read 3, iclass 27, count 2 2006.257.05:32:46.84#ibcon#read 3, iclass 27, count 2 2006.257.05:32:46.84#ibcon#about to read 4, iclass 27, count 2 2006.257.05:32:46.84#ibcon#read 4, iclass 27, count 2 2006.257.05:32:46.84#ibcon#about to read 5, iclass 27, count 2 2006.257.05:32:46.84#ibcon#read 5, iclass 27, count 2 2006.257.05:32:46.84#ibcon#about to read 6, iclass 27, count 2 2006.257.05:32:46.84#ibcon#read 6, iclass 27, count 2 2006.257.05:32:46.84#ibcon#end of sib2, iclass 27, count 2 2006.257.05:32:46.84#ibcon#*after write, iclass 27, count 2 2006.257.05:32:46.84#ibcon#*before return 0, iclass 27, count 2 2006.257.05:32:46.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:46.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:46.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.05:32:46.84#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:46.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:46.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:46.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:46.96#ibcon#enter wrdev, iclass 27, count 0 2006.257.05:32:46.96#ibcon#first serial, iclass 27, count 0 2006.257.05:32:46.96#ibcon#enter sib2, iclass 27, count 0 2006.257.05:32:46.96#ibcon#flushed, iclass 27, count 0 2006.257.05:32:46.96#ibcon#about to write, iclass 27, count 0 2006.257.05:32:46.96#ibcon#wrote, iclass 27, count 0 2006.257.05:32:46.96#ibcon#about to read 3, iclass 27, count 0 2006.257.05:32:46.98#ibcon#read 3, iclass 27, count 0 2006.257.05:32:46.98#ibcon#about to read 4, iclass 27, count 0 2006.257.05:32:46.98#ibcon#read 4, iclass 27, count 0 2006.257.05:32:46.98#ibcon#about to read 5, iclass 27, count 0 2006.257.05:32:46.98#ibcon#read 5, iclass 27, count 0 2006.257.05:32:46.98#ibcon#about to read 6, iclass 27, count 0 2006.257.05:32:46.98#ibcon#read 6, iclass 27, count 0 2006.257.05:32:46.98#ibcon#end of sib2, iclass 27, count 0 2006.257.05:32:46.98#ibcon#*mode == 0, iclass 27, count 0 2006.257.05:32:46.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.05:32:46.98#ibcon#[25=USB\r\n] 2006.257.05:32:46.98#ibcon#*before write, iclass 27, count 0 2006.257.05:32:46.98#ibcon#enter sib2, iclass 27, count 0 2006.257.05:32:46.98#ibcon#flushed, iclass 27, count 0 2006.257.05:32:46.98#ibcon#about to write, iclass 27, count 0 2006.257.05:32:46.98#ibcon#wrote, iclass 27, count 0 2006.257.05:32:46.98#ibcon#about to read 3, iclass 27, count 0 2006.257.05:32:47.01#ibcon#read 3, iclass 27, count 0 2006.257.05:32:47.01#ibcon#about to read 4, iclass 27, count 0 2006.257.05:32:47.01#ibcon#read 4, iclass 27, count 0 2006.257.05:32:47.01#ibcon#about to read 5, iclass 27, count 0 2006.257.05:32:47.01#ibcon#read 5, iclass 27, count 0 2006.257.05:32:47.01#ibcon#about to read 6, iclass 27, count 0 2006.257.05:32:47.01#ibcon#read 6, iclass 27, count 0 2006.257.05:32:47.01#ibcon#end of sib2, iclass 27, count 0 2006.257.05:32:47.01#ibcon#*after write, iclass 27, count 0 2006.257.05:32:47.01#ibcon#*before return 0, iclass 27, count 0 2006.257.05:32:47.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:47.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:47.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.05:32:47.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.05:32:47.01$vck44/valo=3,564.99 2006.257.05:32:47.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.05:32:47.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.05:32:47.01#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:47.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:47.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:47.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:47.01#ibcon#enter wrdev, iclass 29, count 0 2006.257.05:32:47.01#ibcon#first serial, iclass 29, count 0 2006.257.05:32:47.01#ibcon#enter sib2, iclass 29, count 0 2006.257.05:32:47.01#ibcon#flushed, iclass 29, count 0 2006.257.05:32:47.01#ibcon#about to write, iclass 29, count 0 2006.257.05:32:47.01#ibcon#wrote, iclass 29, count 0 2006.257.05:32:47.01#ibcon#about to read 3, iclass 29, count 0 2006.257.05:32:47.03#ibcon#read 3, iclass 29, count 0 2006.257.05:32:47.03#ibcon#about to read 4, iclass 29, count 0 2006.257.05:32:47.03#ibcon#read 4, iclass 29, count 0 2006.257.05:32:47.03#ibcon#about to read 5, iclass 29, count 0 2006.257.05:32:47.03#ibcon#read 5, iclass 29, count 0 2006.257.05:32:47.03#ibcon#about to read 6, iclass 29, count 0 2006.257.05:32:47.03#ibcon#read 6, iclass 29, count 0 2006.257.05:32:47.03#ibcon#end of sib2, iclass 29, count 0 2006.257.05:32:47.03#ibcon#*mode == 0, iclass 29, count 0 2006.257.05:32:47.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.05:32:47.03#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:32:47.03#ibcon#*before write, iclass 29, count 0 2006.257.05:32:47.03#ibcon#enter sib2, iclass 29, count 0 2006.257.05:32:47.03#ibcon#flushed, iclass 29, count 0 2006.257.05:32:47.03#ibcon#about to write, iclass 29, count 0 2006.257.05:32:47.03#ibcon#wrote, iclass 29, count 0 2006.257.05:32:47.03#ibcon#about to read 3, iclass 29, count 0 2006.257.05:32:47.07#ibcon#read 3, iclass 29, count 0 2006.257.05:32:47.07#ibcon#about to read 4, iclass 29, count 0 2006.257.05:32:47.07#ibcon#read 4, iclass 29, count 0 2006.257.05:32:47.07#ibcon#about to read 5, iclass 29, count 0 2006.257.05:32:47.07#ibcon#read 5, iclass 29, count 0 2006.257.05:32:47.07#ibcon#about to read 6, iclass 29, count 0 2006.257.05:32:47.07#ibcon#read 6, iclass 29, count 0 2006.257.05:32:47.07#ibcon#end of sib2, iclass 29, count 0 2006.257.05:32:47.07#ibcon#*after write, iclass 29, count 0 2006.257.05:32:47.07#ibcon#*before return 0, iclass 29, count 0 2006.257.05:32:47.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:47.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:47.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.05:32:47.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.05:32:47.07$vck44/va=3,8 2006.257.05:32:47.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.05:32:47.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.05:32:47.07#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:47.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:47.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:47.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:47.13#ibcon#enter wrdev, iclass 31, count 2 2006.257.05:32:47.13#ibcon#first serial, iclass 31, count 2 2006.257.05:32:47.13#ibcon#enter sib2, iclass 31, count 2 2006.257.05:32:47.13#ibcon#flushed, iclass 31, count 2 2006.257.05:32:47.13#ibcon#about to write, iclass 31, count 2 2006.257.05:32:47.13#ibcon#wrote, iclass 31, count 2 2006.257.05:32:47.13#ibcon#about to read 3, iclass 31, count 2 2006.257.05:32:47.15#ibcon#read 3, iclass 31, count 2 2006.257.05:32:47.15#ibcon#about to read 4, iclass 31, count 2 2006.257.05:32:47.15#ibcon#read 4, iclass 31, count 2 2006.257.05:32:47.15#ibcon#about to read 5, iclass 31, count 2 2006.257.05:32:47.15#ibcon#read 5, iclass 31, count 2 2006.257.05:32:47.15#ibcon#about to read 6, iclass 31, count 2 2006.257.05:32:47.15#ibcon#read 6, iclass 31, count 2 2006.257.05:32:47.15#ibcon#end of sib2, iclass 31, count 2 2006.257.05:32:47.15#ibcon#*mode == 0, iclass 31, count 2 2006.257.05:32:47.15#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.05:32:47.15#ibcon#[25=AT03-08\r\n] 2006.257.05:32:47.15#ibcon#*before write, iclass 31, count 2 2006.257.05:32:47.15#ibcon#enter sib2, iclass 31, count 2 2006.257.05:32:47.15#ibcon#flushed, iclass 31, count 2 2006.257.05:32:47.15#ibcon#about to write, iclass 31, count 2 2006.257.05:32:47.15#ibcon#wrote, iclass 31, count 2 2006.257.05:32:47.15#ibcon#about to read 3, iclass 31, count 2 2006.257.05:32:47.18#ibcon#read 3, iclass 31, count 2 2006.257.05:32:47.18#ibcon#about to read 4, iclass 31, count 2 2006.257.05:32:47.18#ibcon#read 4, iclass 31, count 2 2006.257.05:32:47.18#ibcon#about to read 5, iclass 31, count 2 2006.257.05:32:47.18#ibcon#read 5, iclass 31, count 2 2006.257.05:32:47.18#ibcon#about to read 6, iclass 31, count 2 2006.257.05:32:47.18#ibcon#read 6, iclass 31, count 2 2006.257.05:32:47.18#ibcon#end of sib2, iclass 31, count 2 2006.257.05:32:47.18#ibcon#*after write, iclass 31, count 2 2006.257.05:32:47.18#ibcon#*before return 0, iclass 31, count 2 2006.257.05:32:47.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:47.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:47.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.05:32:47.18#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:47.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:47.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:47.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:47.30#ibcon#enter wrdev, iclass 31, count 0 2006.257.05:32:47.30#ibcon#first serial, iclass 31, count 0 2006.257.05:32:47.30#ibcon#enter sib2, iclass 31, count 0 2006.257.05:32:47.30#ibcon#flushed, iclass 31, count 0 2006.257.05:32:47.30#ibcon#about to write, iclass 31, count 0 2006.257.05:32:47.30#ibcon#wrote, iclass 31, count 0 2006.257.05:32:47.30#ibcon#about to read 3, iclass 31, count 0 2006.257.05:32:47.32#ibcon#read 3, iclass 31, count 0 2006.257.05:32:47.32#ibcon#about to read 4, iclass 31, count 0 2006.257.05:32:47.32#ibcon#read 4, iclass 31, count 0 2006.257.05:32:47.32#ibcon#about to read 5, iclass 31, count 0 2006.257.05:32:47.32#ibcon#read 5, iclass 31, count 0 2006.257.05:32:47.32#ibcon#about to read 6, iclass 31, count 0 2006.257.05:32:47.32#ibcon#read 6, iclass 31, count 0 2006.257.05:32:47.32#ibcon#end of sib2, iclass 31, count 0 2006.257.05:32:47.32#ibcon#*mode == 0, iclass 31, count 0 2006.257.05:32:47.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.05:32:47.32#ibcon#[25=USB\r\n] 2006.257.05:32:47.32#ibcon#*before write, iclass 31, count 0 2006.257.05:32:47.32#ibcon#enter sib2, iclass 31, count 0 2006.257.05:32:47.32#ibcon#flushed, iclass 31, count 0 2006.257.05:32:47.32#ibcon#about to write, iclass 31, count 0 2006.257.05:32:47.32#ibcon#wrote, iclass 31, count 0 2006.257.05:32:47.32#ibcon#about to read 3, iclass 31, count 0 2006.257.05:32:47.35#ibcon#read 3, iclass 31, count 0 2006.257.05:32:47.35#ibcon#about to read 4, iclass 31, count 0 2006.257.05:32:47.35#ibcon#read 4, iclass 31, count 0 2006.257.05:32:47.35#ibcon#about to read 5, iclass 31, count 0 2006.257.05:32:47.35#ibcon#read 5, iclass 31, count 0 2006.257.05:32:47.35#ibcon#about to read 6, iclass 31, count 0 2006.257.05:32:47.35#ibcon#read 6, iclass 31, count 0 2006.257.05:32:47.35#ibcon#end of sib2, iclass 31, count 0 2006.257.05:32:47.35#ibcon#*after write, iclass 31, count 0 2006.257.05:32:47.35#ibcon#*before return 0, iclass 31, count 0 2006.257.05:32:47.35#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:47.35#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:47.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.05:32:47.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.05:32:47.35$vck44/valo=4,624.99 2006.257.05:32:47.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.05:32:47.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.05:32:47.35#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:47.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:47.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:47.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:47.35#ibcon#enter wrdev, iclass 33, count 0 2006.257.05:32:47.35#ibcon#first serial, iclass 33, count 0 2006.257.05:32:47.35#ibcon#enter sib2, iclass 33, count 0 2006.257.05:32:47.35#ibcon#flushed, iclass 33, count 0 2006.257.05:32:47.35#ibcon#about to write, iclass 33, count 0 2006.257.05:32:47.35#ibcon#wrote, iclass 33, count 0 2006.257.05:32:47.35#ibcon#about to read 3, iclass 33, count 0 2006.257.05:32:47.37#ibcon#read 3, iclass 33, count 0 2006.257.05:32:47.37#ibcon#about to read 4, iclass 33, count 0 2006.257.05:32:47.37#ibcon#read 4, iclass 33, count 0 2006.257.05:32:47.37#ibcon#about to read 5, iclass 33, count 0 2006.257.05:32:47.37#ibcon#read 5, iclass 33, count 0 2006.257.05:32:47.37#ibcon#about to read 6, iclass 33, count 0 2006.257.05:32:47.37#ibcon#read 6, iclass 33, count 0 2006.257.05:32:47.37#ibcon#end of sib2, iclass 33, count 0 2006.257.05:32:47.37#ibcon#*mode == 0, iclass 33, count 0 2006.257.05:32:47.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.05:32:47.37#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:32:47.37#ibcon#*before write, iclass 33, count 0 2006.257.05:32:47.37#ibcon#enter sib2, iclass 33, count 0 2006.257.05:32:47.37#ibcon#flushed, iclass 33, count 0 2006.257.05:32:47.37#ibcon#about to write, iclass 33, count 0 2006.257.05:32:47.37#ibcon#wrote, iclass 33, count 0 2006.257.05:32:47.37#ibcon#about to read 3, iclass 33, count 0 2006.257.05:32:47.41#ibcon#read 3, iclass 33, count 0 2006.257.05:32:47.41#ibcon#about to read 4, iclass 33, count 0 2006.257.05:32:47.41#ibcon#read 4, iclass 33, count 0 2006.257.05:32:47.41#ibcon#about to read 5, iclass 33, count 0 2006.257.05:32:47.41#ibcon#read 5, iclass 33, count 0 2006.257.05:32:47.41#ibcon#about to read 6, iclass 33, count 0 2006.257.05:32:47.41#ibcon#read 6, iclass 33, count 0 2006.257.05:32:47.41#ibcon#end of sib2, iclass 33, count 0 2006.257.05:32:47.41#ibcon#*after write, iclass 33, count 0 2006.257.05:32:47.41#ibcon#*before return 0, iclass 33, count 0 2006.257.05:32:47.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:47.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:47.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.05:32:47.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.05:32:47.41$vck44/va=4,7 2006.257.05:32:47.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.05:32:47.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.05:32:47.41#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:47.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:47.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:47.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:47.47#ibcon#enter wrdev, iclass 35, count 2 2006.257.05:32:47.47#ibcon#first serial, iclass 35, count 2 2006.257.05:32:47.47#ibcon#enter sib2, iclass 35, count 2 2006.257.05:32:47.47#ibcon#flushed, iclass 35, count 2 2006.257.05:32:47.47#ibcon#about to write, iclass 35, count 2 2006.257.05:32:47.47#ibcon#wrote, iclass 35, count 2 2006.257.05:32:47.47#ibcon#about to read 3, iclass 35, count 2 2006.257.05:32:47.49#ibcon#read 3, iclass 35, count 2 2006.257.05:32:47.49#ibcon#about to read 4, iclass 35, count 2 2006.257.05:32:47.49#ibcon#read 4, iclass 35, count 2 2006.257.05:32:47.49#ibcon#about to read 5, iclass 35, count 2 2006.257.05:32:47.49#ibcon#read 5, iclass 35, count 2 2006.257.05:32:47.49#ibcon#about to read 6, iclass 35, count 2 2006.257.05:32:47.49#ibcon#read 6, iclass 35, count 2 2006.257.05:32:47.49#ibcon#end of sib2, iclass 35, count 2 2006.257.05:32:47.49#ibcon#*mode == 0, iclass 35, count 2 2006.257.05:32:47.49#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.05:32:47.49#ibcon#[25=AT04-07\r\n] 2006.257.05:32:47.49#ibcon#*before write, iclass 35, count 2 2006.257.05:32:47.49#ibcon#enter sib2, iclass 35, count 2 2006.257.05:32:47.49#ibcon#flushed, iclass 35, count 2 2006.257.05:32:47.49#ibcon#about to write, iclass 35, count 2 2006.257.05:32:47.49#ibcon#wrote, iclass 35, count 2 2006.257.05:32:47.49#ibcon#about to read 3, iclass 35, count 2 2006.257.05:32:47.52#ibcon#read 3, iclass 35, count 2 2006.257.05:32:47.52#ibcon#about to read 4, iclass 35, count 2 2006.257.05:32:47.52#ibcon#read 4, iclass 35, count 2 2006.257.05:32:47.52#ibcon#about to read 5, iclass 35, count 2 2006.257.05:32:47.52#ibcon#read 5, iclass 35, count 2 2006.257.05:32:47.52#ibcon#about to read 6, iclass 35, count 2 2006.257.05:32:47.52#ibcon#read 6, iclass 35, count 2 2006.257.05:32:47.52#ibcon#end of sib2, iclass 35, count 2 2006.257.05:32:47.52#ibcon#*after write, iclass 35, count 2 2006.257.05:32:47.52#ibcon#*before return 0, iclass 35, count 2 2006.257.05:32:47.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:47.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:47.52#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.05:32:47.52#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:47.52#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:47.64#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:47.64#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:47.64#ibcon#enter wrdev, iclass 35, count 0 2006.257.05:32:47.64#ibcon#first serial, iclass 35, count 0 2006.257.05:32:47.64#ibcon#enter sib2, iclass 35, count 0 2006.257.05:32:47.64#ibcon#flushed, iclass 35, count 0 2006.257.05:32:47.64#ibcon#about to write, iclass 35, count 0 2006.257.05:32:47.64#ibcon#wrote, iclass 35, count 0 2006.257.05:32:47.64#ibcon#about to read 3, iclass 35, count 0 2006.257.05:32:47.66#ibcon#read 3, iclass 35, count 0 2006.257.05:32:47.66#ibcon#about to read 4, iclass 35, count 0 2006.257.05:32:47.66#ibcon#read 4, iclass 35, count 0 2006.257.05:32:47.66#ibcon#about to read 5, iclass 35, count 0 2006.257.05:32:47.66#ibcon#read 5, iclass 35, count 0 2006.257.05:32:47.66#ibcon#about to read 6, iclass 35, count 0 2006.257.05:32:47.66#ibcon#read 6, iclass 35, count 0 2006.257.05:32:47.66#ibcon#end of sib2, iclass 35, count 0 2006.257.05:32:47.66#ibcon#*mode == 0, iclass 35, count 0 2006.257.05:32:47.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.05:32:47.66#ibcon#[25=USB\r\n] 2006.257.05:32:47.66#ibcon#*before write, iclass 35, count 0 2006.257.05:32:47.66#ibcon#enter sib2, iclass 35, count 0 2006.257.05:32:47.66#ibcon#flushed, iclass 35, count 0 2006.257.05:32:47.66#ibcon#about to write, iclass 35, count 0 2006.257.05:32:47.66#ibcon#wrote, iclass 35, count 0 2006.257.05:32:47.66#ibcon#about to read 3, iclass 35, count 0 2006.257.05:32:47.69#ibcon#read 3, iclass 35, count 0 2006.257.05:32:47.69#ibcon#about to read 4, iclass 35, count 0 2006.257.05:32:47.69#ibcon#read 4, iclass 35, count 0 2006.257.05:32:47.69#ibcon#about to read 5, iclass 35, count 0 2006.257.05:32:47.69#ibcon#read 5, iclass 35, count 0 2006.257.05:32:47.69#ibcon#about to read 6, iclass 35, count 0 2006.257.05:32:47.69#ibcon#read 6, iclass 35, count 0 2006.257.05:32:47.69#ibcon#end of sib2, iclass 35, count 0 2006.257.05:32:47.69#ibcon#*after write, iclass 35, count 0 2006.257.05:32:47.69#ibcon#*before return 0, iclass 35, count 0 2006.257.05:32:47.69#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:47.69#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:47.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.05:32:47.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.05:32:47.69$vck44/valo=5,734.99 2006.257.05:32:47.69#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.05:32:47.69#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.05:32:47.69#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:47.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:47.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:47.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:47.69#ibcon#enter wrdev, iclass 37, count 0 2006.257.05:32:47.69#ibcon#first serial, iclass 37, count 0 2006.257.05:32:47.69#ibcon#enter sib2, iclass 37, count 0 2006.257.05:32:47.69#ibcon#flushed, iclass 37, count 0 2006.257.05:32:47.69#ibcon#about to write, iclass 37, count 0 2006.257.05:32:47.69#ibcon#wrote, iclass 37, count 0 2006.257.05:32:47.69#ibcon#about to read 3, iclass 37, count 0 2006.257.05:32:47.71#ibcon#read 3, iclass 37, count 0 2006.257.05:32:47.71#ibcon#about to read 4, iclass 37, count 0 2006.257.05:32:47.71#ibcon#read 4, iclass 37, count 0 2006.257.05:32:47.71#ibcon#about to read 5, iclass 37, count 0 2006.257.05:32:47.71#ibcon#read 5, iclass 37, count 0 2006.257.05:32:47.71#ibcon#about to read 6, iclass 37, count 0 2006.257.05:32:47.71#ibcon#read 6, iclass 37, count 0 2006.257.05:32:47.71#ibcon#end of sib2, iclass 37, count 0 2006.257.05:32:47.71#ibcon#*mode == 0, iclass 37, count 0 2006.257.05:32:47.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.05:32:47.71#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:32:47.71#ibcon#*before write, iclass 37, count 0 2006.257.05:32:47.71#ibcon#enter sib2, iclass 37, count 0 2006.257.05:32:47.71#ibcon#flushed, iclass 37, count 0 2006.257.05:32:47.71#ibcon#about to write, iclass 37, count 0 2006.257.05:32:47.71#ibcon#wrote, iclass 37, count 0 2006.257.05:32:47.71#ibcon#about to read 3, iclass 37, count 0 2006.257.05:32:47.75#ibcon#read 3, iclass 37, count 0 2006.257.05:32:47.75#ibcon#about to read 4, iclass 37, count 0 2006.257.05:32:47.75#ibcon#read 4, iclass 37, count 0 2006.257.05:32:47.75#ibcon#about to read 5, iclass 37, count 0 2006.257.05:32:47.75#ibcon#read 5, iclass 37, count 0 2006.257.05:32:47.75#ibcon#about to read 6, iclass 37, count 0 2006.257.05:32:47.75#ibcon#read 6, iclass 37, count 0 2006.257.05:32:47.75#ibcon#end of sib2, iclass 37, count 0 2006.257.05:32:47.75#ibcon#*after write, iclass 37, count 0 2006.257.05:32:47.75#ibcon#*before return 0, iclass 37, count 0 2006.257.05:32:47.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:47.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:47.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.05:32:47.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.05:32:47.75$vck44/va=5,4 2006.257.05:32:47.75#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.05:32:47.75#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.05:32:47.75#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:47.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:47.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:47.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:47.81#ibcon#enter wrdev, iclass 39, count 2 2006.257.05:32:47.81#ibcon#first serial, iclass 39, count 2 2006.257.05:32:47.81#ibcon#enter sib2, iclass 39, count 2 2006.257.05:32:47.81#ibcon#flushed, iclass 39, count 2 2006.257.05:32:47.81#ibcon#about to write, iclass 39, count 2 2006.257.05:32:47.81#ibcon#wrote, iclass 39, count 2 2006.257.05:32:47.81#ibcon#about to read 3, iclass 39, count 2 2006.257.05:32:47.83#ibcon#read 3, iclass 39, count 2 2006.257.05:32:47.83#ibcon#about to read 4, iclass 39, count 2 2006.257.05:32:47.83#ibcon#read 4, iclass 39, count 2 2006.257.05:32:47.83#ibcon#about to read 5, iclass 39, count 2 2006.257.05:32:47.83#ibcon#read 5, iclass 39, count 2 2006.257.05:32:47.83#ibcon#about to read 6, iclass 39, count 2 2006.257.05:32:47.83#ibcon#read 6, iclass 39, count 2 2006.257.05:32:47.83#ibcon#end of sib2, iclass 39, count 2 2006.257.05:32:47.83#ibcon#*mode == 0, iclass 39, count 2 2006.257.05:32:47.83#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.05:32:47.83#ibcon#[25=AT05-04\r\n] 2006.257.05:32:47.83#ibcon#*before write, iclass 39, count 2 2006.257.05:32:47.83#ibcon#enter sib2, iclass 39, count 2 2006.257.05:32:47.83#ibcon#flushed, iclass 39, count 2 2006.257.05:32:47.83#ibcon#about to write, iclass 39, count 2 2006.257.05:32:47.83#ibcon#wrote, iclass 39, count 2 2006.257.05:32:47.83#ibcon#about to read 3, iclass 39, count 2 2006.257.05:32:47.86#ibcon#read 3, iclass 39, count 2 2006.257.05:32:47.86#ibcon#about to read 4, iclass 39, count 2 2006.257.05:32:47.86#ibcon#read 4, iclass 39, count 2 2006.257.05:32:47.86#ibcon#about to read 5, iclass 39, count 2 2006.257.05:32:47.86#ibcon#read 5, iclass 39, count 2 2006.257.05:32:47.86#ibcon#about to read 6, iclass 39, count 2 2006.257.05:32:47.86#ibcon#read 6, iclass 39, count 2 2006.257.05:32:47.86#ibcon#end of sib2, iclass 39, count 2 2006.257.05:32:47.86#ibcon#*after write, iclass 39, count 2 2006.257.05:32:47.86#ibcon#*before return 0, iclass 39, count 2 2006.257.05:32:47.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:47.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:47.86#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.05:32:47.86#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:47.86#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:47.98#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:47.98#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:47.98#ibcon#enter wrdev, iclass 39, count 0 2006.257.05:32:47.98#ibcon#first serial, iclass 39, count 0 2006.257.05:32:47.98#ibcon#enter sib2, iclass 39, count 0 2006.257.05:32:47.98#ibcon#flushed, iclass 39, count 0 2006.257.05:32:47.98#ibcon#about to write, iclass 39, count 0 2006.257.05:32:47.98#ibcon#wrote, iclass 39, count 0 2006.257.05:32:47.98#ibcon#about to read 3, iclass 39, count 0 2006.257.05:32:48.00#ibcon#read 3, iclass 39, count 0 2006.257.05:32:48.00#ibcon#about to read 4, iclass 39, count 0 2006.257.05:32:48.00#ibcon#read 4, iclass 39, count 0 2006.257.05:32:48.00#ibcon#about to read 5, iclass 39, count 0 2006.257.05:32:48.00#ibcon#read 5, iclass 39, count 0 2006.257.05:32:48.00#ibcon#about to read 6, iclass 39, count 0 2006.257.05:32:48.00#ibcon#read 6, iclass 39, count 0 2006.257.05:32:48.00#ibcon#end of sib2, iclass 39, count 0 2006.257.05:32:48.00#ibcon#*mode == 0, iclass 39, count 0 2006.257.05:32:48.00#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.05:32:48.00#ibcon#[25=USB\r\n] 2006.257.05:32:48.00#ibcon#*before write, iclass 39, count 0 2006.257.05:32:48.00#ibcon#enter sib2, iclass 39, count 0 2006.257.05:32:48.00#ibcon#flushed, iclass 39, count 0 2006.257.05:32:48.00#ibcon#about to write, iclass 39, count 0 2006.257.05:32:48.00#ibcon#wrote, iclass 39, count 0 2006.257.05:32:48.00#ibcon#about to read 3, iclass 39, count 0 2006.257.05:32:48.03#ibcon#read 3, iclass 39, count 0 2006.257.05:32:48.03#ibcon#about to read 4, iclass 39, count 0 2006.257.05:32:48.03#ibcon#read 4, iclass 39, count 0 2006.257.05:32:48.03#ibcon#about to read 5, iclass 39, count 0 2006.257.05:32:48.03#ibcon#read 5, iclass 39, count 0 2006.257.05:32:48.03#ibcon#about to read 6, iclass 39, count 0 2006.257.05:32:48.03#ibcon#read 6, iclass 39, count 0 2006.257.05:32:48.03#ibcon#end of sib2, iclass 39, count 0 2006.257.05:32:48.03#ibcon#*after write, iclass 39, count 0 2006.257.05:32:48.03#ibcon#*before return 0, iclass 39, count 0 2006.257.05:32:48.03#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:48.03#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:48.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.05:32:48.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.05:32:48.03$vck44/valo=6,814.99 2006.257.05:32:48.03#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.05:32:48.03#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.05:32:48.03#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:48.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:48.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:48.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:48.03#ibcon#enter wrdev, iclass 3, count 0 2006.257.05:32:48.03#ibcon#first serial, iclass 3, count 0 2006.257.05:32:48.03#ibcon#enter sib2, iclass 3, count 0 2006.257.05:32:48.03#ibcon#flushed, iclass 3, count 0 2006.257.05:32:48.03#ibcon#about to write, iclass 3, count 0 2006.257.05:32:48.03#ibcon#wrote, iclass 3, count 0 2006.257.05:32:48.03#ibcon#about to read 3, iclass 3, count 0 2006.257.05:32:48.05#ibcon#read 3, iclass 3, count 0 2006.257.05:32:48.05#ibcon#about to read 4, iclass 3, count 0 2006.257.05:32:48.05#ibcon#read 4, iclass 3, count 0 2006.257.05:32:48.05#ibcon#about to read 5, iclass 3, count 0 2006.257.05:32:48.05#ibcon#read 5, iclass 3, count 0 2006.257.05:32:48.05#ibcon#about to read 6, iclass 3, count 0 2006.257.05:32:48.05#ibcon#read 6, iclass 3, count 0 2006.257.05:32:48.05#ibcon#end of sib2, iclass 3, count 0 2006.257.05:32:48.05#ibcon#*mode == 0, iclass 3, count 0 2006.257.05:32:48.05#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.05:32:48.05#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:32:48.05#ibcon#*before write, iclass 3, count 0 2006.257.05:32:48.05#ibcon#enter sib2, iclass 3, count 0 2006.257.05:32:48.05#ibcon#flushed, iclass 3, count 0 2006.257.05:32:48.05#ibcon#about to write, iclass 3, count 0 2006.257.05:32:48.05#ibcon#wrote, iclass 3, count 0 2006.257.05:32:48.05#ibcon#about to read 3, iclass 3, count 0 2006.257.05:32:48.09#ibcon#read 3, iclass 3, count 0 2006.257.05:32:48.09#ibcon#about to read 4, iclass 3, count 0 2006.257.05:32:48.09#ibcon#read 4, iclass 3, count 0 2006.257.05:32:48.09#ibcon#about to read 5, iclass 3, count 0 2006.257.05:32:48.09#ibcon#read 5, iclass 3, count 0 2006.257.05:32:48.09#ibcon#about to read 6, iclass 3, count 0 2006.257.05:32:48.09#ibcon#read 6, iclass 3, count 0 2006.257.05:32:48.09#ibcon#end of sib2, iclass 3, count 0 2006.257.05:32:48.09#ibcon#*after write, iclass 3, count 0 2006.257.05:32:48.09#ibcon#*before return 0, iclass 3, count 0 2006.257.05:32:48.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:48.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:48.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.05:32:48.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.05:32:48.09$vck44/va=6,4 2006.257.05:32:48.09#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.05:32:48.09#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.05:32:48.09#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:48.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:48.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:48.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:48.15#ibcon#enter wrdev, iclass 5, count 2 2006.257.05:32:48.15#ibcon#first serial, iclass 5, count 2 2006.257.05:32:48.15#ibcon#enter sib2, iclass 5, count 2 2006.257.05:32:48.15#ibcon#flushed, iclass 5, count 2 2006.257.05:32:48.15#ibcon#about to write, iclass 5, count 2 2006.257.05:32:48.15#ibcon#wrote, iclass 5, count 2 2006.257.05:32:48.15#ibcon#about to read 3, iclass 5, count 2 2006.257.05:32:48.17#ibcon#read 3, iclass 5, count 2 2006.257.05:32:48.17#ibcon#about to read 4, iclass 5, count 2 2006.257.05:32:48.17#ibcon#read 4, iclass 5, count 2 2006.257.05:32:48.17#ibcon#about to read 5, iclass 5, count 2 2006.257.05:32:48.17#ibcon#read 5, iclass 5, count 2 2006.257.05:32:48.17#ibcon#about to read 6, iclass 5, count 2 2006.257.05:32:48.17#ibcon#read 6, iclass 5, count 2 2006.257.05:32:48.17#ibcon#end of sib2, iclass 5, count 2 2006.257.05:32:48.17#ibcon#*mode == 0, iclass 5, count 2 2006.257.05:32:48.17#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.05:32:48.17#ibcon#[25=AT06-04\r\n] 2006.257.05:32:48.17#ibcon#*before write, iclass 5, count 2 2006.257.05:32:48.17#ibcon#enter sib2, iclass 5, count 2 2006.257.05:32:48.17#ibcon#flushed, iclass 5, count 2 2006.257.05:32:48.17#ibcon#about to write, iclass 5, count 2 2006.257.05:32:48.17#ibcon#wrote, iclass 5, count 2 2006.257.05:32:48.17#ibcon#about to read 3, iclass 5, count 2 2006.257.05:32:48.20#ibcon#read 3, iclass 5, count 2 2006.257.05:32:48.20#ibcon#about to read 4, iclass 5, count 2 2006.257.05:32:48.20#ibcon#read 4, iclass 5, count 2 2006.257.05:32:48.20#ibcon#about to read 5, iclass 5, count 2 2006.257.05:32:48.20#ibcon#read 5, iclass 5, count 2 2006.257.05:32:48.20#ibcon#about to read 6, iclass 5, count 2 2006.257.05:32:48.20#ibcon#read 6, iclass 5, count 2 2006.257.05:32:48.20#ibcon#end of sib2, iclass 5, count 2 2006.257.05:32:48.20#ibcon#*after write, iclass 5, count 2 2006.257.05:32:48.20#ibcon#*before return 0, iclass 5, count 2 2006.257.05:32:48.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:48.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:48.20#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.05:32:48.20#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:48.20#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:48.32#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:48.32#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:48.32#ibcon#enter wrdev, iclass 5, count 0 2006.257.05:32:48.32#ibcon#first serial, iclass 5, count 0 2006.257.05:32:48.32#ibcon#enter sib2, iclass 5, count 0 2006.257.05:32:48.32#ibcon#flushed, iclass 5, count 0 2006.257.05:32:48.32#ibcon#about to write, iclass 5, count 0 2006.257.05:32:48.32#ibcon#wrote, iclass 5, count 0 2006.257.05:32:48.32#ibcon#about to read 3, iclass 5, count 0 2006.257.05:32:48.34#ibcon#read 3, iclass 5, count 0 2006.257.05:32:48.34#ibcon#about to read 4, iclass 5, count 0 2006.257.05:32:48.34#ibcon#read 4, iclass 5, count 0 2006.257.05:32:48.34#ibcon#about to read 5, iclass 5, count 0 2006.257.05:32:48.34#ibcon#read 5, iclass 5, count 0 2006.257.05:32:48.34#ibcon#about to read 6, iclass 5, count 0 2006.257.05:32:48.34#ibcon#read 6, iclass 5, count 0 2006.257.05:32:48.34#ibcon#end of sib2, iclass 5, count 0 2006.257.05:32:48.34#ibcon#*mode == 0, iclass 5, count 0 2006.257.05:32:48.34#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.05:32:48.34#ibcon#[25=USB\r\n] 2006.257.05:32:48.34#ibcon#*before write, iclass 5, count 0 2006.257.05:32:48.34#ibcon#enter sib2, iclass 5, count 0 2006.257.05:32:48.34#ibcon#flushed, iclass 5, count 0 2006.257.05:32:48.34#ibcon#about to write, iclass 5, count 0 2006.257.05:32:48.34#ibcon#wrote, iclass 5, count 0 2006.257.05:32:48.34#ibcon#about to read 3, iclass 5, count 0 2006.257.05:32:48.37#ibcon#read 3, iclass 5, count 0 2006.257.05:32:48.37#ibcon#about to read 4, iclass 5, count 0 2006.257.05:32:48.37#ibcon#read 4, iclass 5, count 0 2006.257.05:32:48.37#ibcon#about to read 5, iclass 5, count 0 2006.257.05:32:48.37#ibcon#read 5, iclass 5, count 0 2006.257.05:32:48.37#ibcon#about to read 6, iclass 5, count 0 2006.257.05:32:48.37#ibcon#read 6, iclass 5, count 0 2006.257.05:32:48.37#ibcon#end of sib2, iclass 5, count 0 2006.257.05:32:48.37#ibcon#*after write, iclass 5, count 0 2006.257.05:32:48.37#ibcon#*before return 0, iclass 5, count 0 2006.257.05:32:48.37#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:48.37#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:48.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.05:32:48.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.05:32:48.37$vck44/valo=7,864.99 2006.257.05:32:48.37#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.05:32:48.37#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.05:32:48.37#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:48.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:48.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:48.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:48.37#ibcon#enter wrdev, iclass 7, count 0 2006.257.05:32:48.37#ibcon#first serial, iclass 7, count 0 2006.257.05:32:48.37#ibcon#enter sib2, iclass 7, count 0 2006.257.05:32:48.37#ibcon#flushed, iclass 7, count 0 2006.257.05:32:48.37#ibcon#about to write, iclass 7, count 0 2006.257.05:32:48.37#ibcon#wrote, iclass 7, count 0 2006.257.05:32:48.37#ibcon#about to read 3, iclass 7, count 0 2006.257.05:32:48.39#ibcon#read 3, iclass 7, count 0 2006.257.05:32:48.39#ibcon#about to read 4, iclass 7, count 0 2006.257.05:32:48.39#ibcon#read 4, iclass 7, count 0 2006.257.05:32:48.39#ibcon#about to read 5, iclass 7, count 0 2006.257.05:32:48.39#ibcon#read 5, iclass 7, count 0 2006.257.05:32:48.39#ibcon#about to read 6, iclass 7, count 0 2006.257.05:32:48.39#ibcon#read 6, iclass 7, count 0 2006.257.05:32:48.39#ibcon#end of sib2, iclass 7, count 0 2006.257.05:32:48.39#ibcon#*mode == 0, iclass 7, count 0 2006.257.05:32:48.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.05:32:48.39#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:32:48.39#ibcon#*before write, iclass 7, count 0 2006.257.05:32:48.39#ibcon#enter sib2, iclass 7, count 0 2006.257.05:32:48.39#ibcon#flushed, iclass 7, count 0 2006.257.05:32:48.39#ibcon#about to write, iclass 7, count 0 2006.257.05:32:48.39#ibcon#wrote, iclass 7, count 0 2006.257.05:32:48.39#ibcon#about to read 3, iclass 7, count 0 2006.257.05:32:48.43#ibcon#read 3, iclass 7, count 0 2006.257.05:32:48.43#ibcon#about to read 4, iclass 7, count 0 2006.257.05:32:48.43#ibcon#read 4, iclass 7, count 0 2006.257.05:32:48.43#ibcon#about to read 5, iclass 7, count 0 2006.257.05:32:48.43#ibcon#read 5, iclass 7, count 0 2006.257.05:32:48.43#ibcon#about to read 6, iclass 7, count 0 2006.257.05:32:48.43#ibcon#read 6, iclass 7, count 0 2006.257.05:32:48.43#ibcon#end of sib2, iclass 7, count 0 2006.257.05:32:48.43#ibcon#*after write, iclass 7, count 0 2006.257.05:32:48.43#ibcon#*before return 0, iclass 7, count 0 2006.257.05:32:48.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:48.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:48.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.05:32:48.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.05:32:48.43$vck44/va=7,4 2006.257.05:32:48.43#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.05:32:48.43#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.05:32:48.43#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:48.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:48.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:48.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:48.49#ibcon#enter wrdev, iclass 11, count 2 2006.257.05:32:48.49#ibcon#first serial, iclass 11, count 2 2006.257.05:32:48.49#ibcon#enter sib2, iclass 11, count 2 2006.257.05:32:48.49#ibcon#flushed, iclass 11, count 2 2006.257.05:32:48.49#ibcon#about to write, iclass 11, count 2 2006.257.05:32:48.49#ibcon#wrote, iclass 11, count 2 2006.257.05:32:48.49#ibcon#about to read 3, iclass 11, count 2 2006.257.05:32:48.51#ibcon#read 3, iclass 11, count 2 2006.257.05:32:48.51#ibcon#about to read 4, iclass 11, count 2 2006.257.05:32:48.51#ibcon#read 4, iclass 11, count 2 2006.257.05:32:48.51#ibcon#about to read 5, iclass 11, count 2 2006.257.05:32:48.51#ibcon#read 5, iclass 11, count 2 2006.257.05:32:48.51#ibcon#about to read 6, iclass 11, count 2 2006.257.05:32:48.51#ibcon#read 6, iclass 11, count 2 2006.257.05:32:48.51#ibcon#end of sib2, iclass 11, count 2 2006.257.05:32:48.51#ibcon#*mode == 0, iclass 11, count 2 2006.257.05:32:48.51#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.05:32:48.51#ibcon#[25=AT07-04\r\n] 2006.257.05:32:48.51#ibcon#*before write, iclass 11, count 2 2006.257.05:32:48.51#ibcon#enter sib2, iclass 11, count 2 2006.257.05:32:48.51#ibcon#flushed, iclass 11, count 2 2006.257.05:32:48.51#ibcon#about to write, iclass 11, count 2 2006.257.05:32:48.51#ibcon#wrote, iclass 11, count 2 2006.257.05:32:48.51#ibcon#about to read 3, iclass 11, count 2 2006.257.05:32:48.54#ibcon#read 3, iclass 11, count 2 2006.257.05:32:48.54#ibcon#about to read 4, iclass 11, count 2 2006.257.05:32:48.54#ibcon#read 4, iclass 11, count 2 2006.257.05:32:48.54#ibcon#about to read 5, iclass 11, count 2 2006.257.05:32:48.54#ibcon#read 5, iclass 11, count 2 2006.257.05:32:48.54#ibcon#about to read 6, iclass 11, count 2 2006.257.05:32:48.54#ibcon#read 6, iclass 11, count 2 2006.257.05:32:48.54#ibcon#end of sib2, iclass 11, count 2 2006.257.05:32:48.54#ibcon#*after write, iclass 11, count 2 2006.257.05:32:48.54#ibcon#*before return 0, iclass 11, count 2 2006.257.05:32:48.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:48.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:48.54#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.05:32:48.54#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:48.54#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:48.66#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:48.66#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:48.66#ibcon#enter wrdev, iclass 11, count 0 2006.257.05:32:48.66#ibcon#first serial, iclass 11, count 0 2006.257.05:32:48.66#ibcon#enter sib2, iclass 11, count 0 2006.257.05:32:48.66#ibcon#flushed, iclass 11, count 0 2006.257.05:32:48.66#ibcon#about to write, iclass 11, count 0 2006.257.05:32:48.66#ibcon#wrote, iclass 11, count 0 2006.257.05:32:48.66#ibcon#about to read 3, iclass 11, count 0 2006.257.05:32:48.68#ibcon#read 3, iclass 11, count 0 2006.257.05:32:48.68#ibcon#about to read 4, iclass 11, count 0 2006.257.05:32:48.68#ibcon#read 4, iclass 11, count 0 2006.257.05:32:48.68#ibcon#about to read 5, iclass 11, count 0 2006.257.05:32:48.68#ibcon#read 5, iclass 11, count 0 2006.257.05:32:48.68#ibcon#about to read 6, iclass 11, count 0 2006.257.05:32:48.68#ibcon#read 6, iclass 11, count 0 2006.257.05:32:48.68#ibcon#end of sib2, iclass 11, count 0 2006.257.05:32:48.68#ibcon#*mode == 0, iclass 11, count 0 2006.257.05:32:48.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.05:32:48.68#ibcon#[25=USB\r\n] 2006.257.05:32:48.68#ibcon#*before write, iclass 11, count 0 2006.257.05:32:48.68#ibcon#enter sib2, iclass 11, count 0 2006.257.05:32:48.68#ibcon#flushed, iclass 11, count 0 2006.257.05:32:48.68#ibcon#about to write, iclass 11, count 0 2006.257.05:32:48.68#ibcon#wrote, iclass 11, count 0 2006.257.05:32:48.68#ibcon#about to read 3, iclass 11, count 0 2006.257.05:32:48.71#ibcon#read 3, iclass 11, count 0 2006.257.05:32:48.71#ibcon#about to read 4, iclass 11, count 0 2006.257.05:32:48.71#ibcon#read 4, iclass 11, count 0 2006.257.05:32:48.71#ibcon#about to read 5, iclass 11, count 0 2006.257.05:32:48.71#ibcon#read 5, iclass 11, count 0 2006.257.05:32:48.71#ibcon#about to read 6, iclass 11, count 0 2006.257.05:32:48.71#ibcon#read 6, iclass 11, count 0 2006.257.05:32:48.71#ibcon#end of sib2, iclass 11, count 0 2006.257.05:32:48.71#ibcon#*after write, iclass 11, count 0 2006.257.05:32:48.71#ibcon#*before return 0, iclass 11, count 0 2006.257.05:32:48.71#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:48.71#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:48.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.05:32:48.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.05:32:48.71$vck44/valo=8,884.99 2006.257.05:32:48.71#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.05:32:48.71#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.05:32:48.71#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:48.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:48.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:48.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:48.71#ibcon#enter wrdev, iclass 13, count 0 2006.257.05:32:48.71#ibcon#first serial, iclass 13, count 0 2006.257.05:32:48.71#ibcon#enter sib2, iclass 13, count 0 2006.257.05:32:48.71#ibcon#flushed, iclass 13, count 0 2006.257.05:32:48.71#ibcon#about to write, iclass 13, count 0 2006.257.05:32:48.71#ibcon#wrote, iclass 13, count 0 2006.257.05:32:48.71#ibcon#about to read 3, iclass 13, count 0 2006.257.05:32:48.73#ibcon#read 3, iclass 13, count 0 2006.257.05:32:48.73#ibcon#about to read 4, iclass 13, count 0 2006.257.05:32:48.73#ibcon#read 4, iclass 13, count 0 2006.257.05:32:48.73#ibcon#about to read 5, iclass 13, count 0 2006.257.05:32:48.73#ibcon#read 5, iclass 13, count 0 2006.257.05:32:48.73#ibcon#about to read 6, iclass 13, count 0 2006.257.05:32:48.73#ibcon#read 6, iclass 13, count 0 2006.257.05:32:48.73#ibcon#end of sib2, iclass 13, count 0 2006.257.05:32:48.73#ibcon#*mode == 0, iclass 13, count 0 2006.257.05:32:48.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.05:32:48.73#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:32:48.73#ibcon#*before write, iclass 13, count 0 2006.257.05:32:48.73#ibcon#enter sib2, iclass 13, count 0 2006.257.05:32:48.73#ibcon#flushed, iclass 13, count 0 2006.257.05:32:48.73#ibcon#about to write, iclass 13, count 0 2006.257.05:32:48.73#ibcon#wrote, iclass 13, count 0 2006.257.05:32:48.73#ibcon#about to read 3, iclass 13, count 0 2006.257.05:32:48.77#ibcon#read 3, iclass 13, count 0 2006.257.05:32:48.77#ibcon#about to read 4, iclass 13, count 0 2006.257.05:32:48.77#ibcon#read 4, iclass 13, count 0 2006.257.05:32:48.77#ibcon#about to read 5, iclass 13, count 0 2006.257.05:32:48.77#ibcon#read 5, iclass 13, count 0 2006.257.05:32:48.77#ibcon#about to read 6, iclass 13, count 0 2006.257.05:32:48.77#ibcon#read 6, iclass 13, count 0 2006.257.05:32:48.77#ibcon#end of sib2, iclass 13, count 0 2006.257.05:32:48.77#ibcon#*after write, iclass 13, count 0 2006.257.05:32:48.77#ibcon#*before return 0, iclass 13, count 0 2006.257.05:32:48.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:48.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:48.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.05:32:48.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.05:32:48.77$vck44/va=8,4 2006.257.05:32:48.77#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.05:32:48.77#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.05:32:48.77#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:48.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:32:48.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:32:48.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:32:48.83#ibcon#enter wrdev, iclass 15, count 2 2006.257.05:32:48.83#ibcon#first serial, iclass 15, count 2 2006.257.05:32:48.83#ibcon#enter sib2, iclass 15, count 2 2006.257.05:32:48.83#ibcon#flushed, iclass 15, count 2 2006.257.05:32:48.83#ibcon#about to write, iclass 15, count 2 2006.257.05:32:48.83#ibcon#wrote, iclass 15, count 2 2006.257.05:32:48.83#ibcon#about to read 3, iclass 15, count 2 2006.257.05:32:48.85#ibcon#read 3, iclass 15, count 2 2006.257.05:32:48.85#ibcon#about to read 4, iclass 15, count 2 2006.257.05:32:48.85#ibcon#read 4, iclass 15, count 2 2006.257.05:32:48.85#ibcon#about to read 5, iclass 15, count 2 2006.257.05:32:48.85#ibcon#read 5, iclass 15, count 2 2006.257.05:32:48.85#ibcon#about to read 6, iclass 15, count 2 2006.257.05:32:48.85#ibcon#read 6, iclass 15, count 2 2006.257.05:32:48.85#ibcon#end of sib2, iclass 15, count 2 2006.257.05:32:48.85#ibcon#*mode == 0, iclass 15, count 2 2006.257.05:32:48.85#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.05:32:48.85#ibcon#[25=AT08-04\r\n] 2006.257.05:32:48.85#ibcon#*before write, iclass 15, count 2 2006.257.05:32:48.85#ibcon#enter sib2, iclass 15, count 2 2006.257.05:32:48.85#ibcon#flushed, iclass 15, count 2 2006.257.05:32:48.85#ibcon#about to write, iclass 15, count 2 2006.257.05:32:48.85#ibcon#wrote, iclass 15, count 2 2006.257.05:32:48.85#ibcon#about to read 3, iclass 15, count 2 2006.257.05:32:48.88#ibcon#read 3, iclass 15, count 2 2006.257.05:32:48.88#ibcon#about to read 4, iclass 15, count 2 2006.257.05:32:48.88#ibcon#read 4, iclass 15, count 2 2006.257.05:32:48.88#ibcon#about to read 5, iclass 15, count 2 2006.257.05:32:48.88#ibcon#read 5, iclass 15, count 2 2006.257.05:32:48.88#ibcon#about to read 6, iclass 15, count 2 2006.257.05:32:48.88#ibcon#read 6, iclass 15, count 2 2006.257.05:32:48.88#ibcon#end of sib2, iclass 15, count 2 2006.257.05:32:48.88#ibcon#*after write, iclass 15, count 2 2006.257.05:32:48.88#ibcon#*before return 0, iclass 15, count 2 2006.257.05:32:48.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:32:48.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:32:48.88#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.05:32:48.88#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:48.88#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:32:49.00#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:32:49.00#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:32:49.00#ibcon#enter wrdev, iclass 15, count 0 2006.257.05:32:49.00#ibcon#first serial, iclass 15, count 0 2006.257.05:32:49.00#ibcon#enter sib2, iclass 15, count 0 2006.257.05:32:49.00#ibcon#flushed, iclass 15, count 0 2006.257.05:32:49.00#ibcon#about to write, iclass 15, count 0 2006.257.05:32:49.00#ibcon#wrote, iclass 15, count 0 2006.257.05:32:49.00#ibcon#about to read 3, iclass 15, count 0 2006.257.05:32:49.02#ibcon#read 3, iclass 15, count 0 2006.257.05:32:49.02#ibcon#about to read 4, iclass 15, count 0 2006.257.05:32:49.02#ibcon#read 4, iclass 15, count 0 2006.257.05:32:49.02#ibcon#about to read 5, iclass 15, count 0 2006.257.05:32:49.02#ibcon#read 5, iclass 15, count 0 2006.257.05:32:49.02#ibcon#about to read 6, iclass 15, count 0 2006.257.05:32:49.02#ibcon#read 6, iclass 15, count 0 2006.257.05:32:49.02#ibcon#end of sib2, iclass 15, count 0 2006.257.05:32:49.02#ibcon#*mode == 0, iclass 15, count 0 2006.257.05:32:49.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.05:32:49.02#ibcon#[25=USB\r\n] 2006.257.05:32:49.02#ibcon#*before write, iclass 15, count 0 2006.257.05:32:49.02#ibcon#enter sib2, iclass 15, count 0 2006.257.05:32:49.02#ibcon#flushed, iclass 15, count 0 2006.257.05:32:49.02#ibcon#about to write, iclass 15, count 0 2006.257.05:32:49.02#ibcon#wrote, iclass 15, count 0 2006.257.05:32:49.02#ibcon#about to read 3, iclass 15, count 0 2006.257.05:32:49.05#ibcon#read 3, iclass 15, count 0 2006.257.05:32:49.05#ibcon#about to read 4, iclass 15, count 0 2006.257.05:32:49.05#ibcon#read 4, iclass 15, count 0 2006.257.05:32:49.05#ibcon#about to read 5, iclass 15, count 0 2006.257.05:32:49.05#ibcon#read 5, iclass 15, count 0 2006.257.05:32:49.05#ibcon#about to read 6, iclass 15, count 0 2006.257.05:32:49.05#ibcon#read 6, iclass 15, count 0 2006.257.05:32:49.05#ibcon#end of sib2, iclass 15, count 0 2006.257.05:32:49.05#ibcon#*after write, iclass 15, count 0 2006.257.05:32:49.05#ibcon#*before return 0, iclass 15, count 0 2006.257.05:32:49.05#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:32:49.05#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:32:49.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.05:32:49.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.05:32:49.05$vck44/vblo=1,629.99 2006.257.05:32:49.05#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.05:32:49.05#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.05:32:49.05#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:49.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:32:49.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:32:49.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:32:49.05#ibcon#enter wrdev, iclass 17, count 0 2006.257.05:32:49.05#ibcon#first serial, iclass 17, count 0 2006.257.05:32:49.05#ibcon#enter sib2, iclass 17, count 0 2006.257.05:32:49.05#ibcon#flushed, iclass 17, count 0 2006.257.05:32:49.05#ibcon#about to write, iclass 17, count 0 2006.257.05:32:49.05#ibcon#wrote, iclass 17, count 0 2006.257.05:32:49.05#ibcon#about to read 3, iclass 17, count 0 2006.257.05:32:49.07#ibcon#read 3, iclass 17, count 0 2006.257.05:32:49.07#ibcon#about to read 4, iclass 17, count 0 2006.257.05:32:49.07#ibcon#read 4, iclass 17, count 0 2006.257.05:32:49.07#ibcon#about to read 5, iclass 17, count 0 2006.257.05:32:49.07#ibcon#read 5, iclass 17, count 0 2006.257.05:32:49.07#ibcon#about to read 6, iclass 17, count 0 2006.257.05:32:49.07#ibcon#read 6, iclass 17, count 0 2006.257.05:32:49.07#ibcon#end of sib2, iclass 17, count 0 2006.257.05:32:49.07#ibcon#*mode == 0, iclass 17, count 0 2006.257.05:32:49.07#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.05:32:49.07#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:32:49.07#ibcon#*before write, iclass 17, count 0 2006.257.05:32:49.07#ibcon#enter sib2, iclass 17, count 0 2006.257.05:32:49.07#ibcon#flushed, iclass 17, count 0 2006.257.05:32:49.07#ibcon#about to write, iclass 17, count 0 2006.257.05:32:49.07#ibcon#wrote, iclass 17, count 0 2006.257.05:32:49.07#ibcon#about to read 3, iclass 17, count 0 2006.257.05:32:49.11#ibcon#read 3, iclass 17, count 0 2006.257.05:32:49.11#ibcon#about to read 4, iclass 17, count 0 2006.257.05:32:49.11#ibcon#read 4, iclass 17, count 0 2006.257.05:32:49.11#ibcon#about to read 5, iclass 17, count 0 2006.257.05:32:49.11#ibcon#read 5, iclass 17, count 0 2006.257.05:32:49.11#ibcon#about to read 6, iclass 17, count 0 2006.257.05:32:49.11#ibcon#read 6, iclass 17, count 0 2006.257.05:32:49.11#ibcon#end of sib2, iclass 17, count 0 2006.257.05:32:49.11#ibcon#*after write, iclass 17, count 0 2006.257.05:32:49.11#ibcon#*before return 0, iclass 17, count 0 2006.257.05:32:49.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:32:49.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:32:49.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.05:32:49.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.05:32:49.11$vck44/vb=1,4 2006.257.05:32:49.11#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.05:32:49.11#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.05:32:49.11#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:49.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:32:49.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:32:49.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:32:49.11#ibcon#enter wrdev, iclass 19, count 2 2006.257.05:32:49.11#ibcon#first serial, iclass 19, count 2 2006.257.05:32:49.11#ibcon#enter sib2, iclass 19, count 2 2006.257.05:32:49.11#ibcon#flushed, iclass 19, count 2 2006.257.05:32:49.11#ibcon#about to write, iclass 19, count 2 2006.257.05:32:49.11#ibcon#wrote, iclass 19, count 2 2006.257.05:32:49.11#ibcon#about to read 3, iclass 19, count 2 2006.257.05:32:49.13#ibcon#read 3, iclass 19, count 2 2006.257.05:32:49.13#ibcon#about to read 4, iclass 19, count 2 2006.257.05:32:49.13#ibcon#read 4, iclass 19, count 2 2006.257.05:32:49.13#ibcon#about to read 5, iclass 19, count 2 2006.257.05:32:49.13#ibcon#read 5, iclass 19, count 2 2006.257.05:32:49.13#ibcon#about to read 6, iclass 19, count 2 2006.257.05:32:49.13#ibcon#read 6, iclass 19, count 2 2006.257.05:32:49.13#ibcon#end of sib2, iclass 19, count 2 2006.257.05:32:49.13#ibcon#*mode == 0, iclass 19, count 2 2006.257.05:32:49.13#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.05:32:49.13#ibcon#[27=AT01-04\r\n] 2006.257.05:32:49.13#ibcon#*before write, iclass 19, count 2 2006.257.05:32:49.13#ibcon#enter sib2, iclass 19, count 2 2006.257.05:32:49.13#ibcon#flushed, iclass 19, count 2 2006.257.05:32:49.13#ibcon#about to write, iclass 19, count 2 2006.257.05:32:49.13#ibcon#wrote, iclass 19, count 2 2006.257.05:32:49.13#ibcon#about to read 3, iclass 19, count 2 2006.257.05:32:49.16#ibcon#read 3, iclass 19, count 2 2006.257.05:32:49.16#ibcon#about to read 4, iclass 19, count 2 2006.257.05:32:49.16#ibcon#read 4, iclass 19, count 2 2006.257.05:32:49.16#ibcon#about to read 5, iclass 19, count 2 2006.257.05:32:49.16#ibcon#read 5, iclass 19, count 2 2006.257.05:32:49.16#ibcon#about to read 6, iclass 19, count 2 2006.257.05:32:49.16#ibcon#read 6, iclass 19, count 2 2006.257.05:32:49.16#ibcon#end of sib2, iclass 19, count 2 2006.257.05:32:49.16#ibcon#*after write, iclass 19, count 2 2006.257.05:32:49.16#ibcon#*before return 0, iclass 19, count 2 2006.257.05:32:49.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:32:49.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:32:49.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.05:32:49.16#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:49.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:32:49.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:32:49.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:32:49.28#ibcon#enter wrdev, iclass 19, count 0 2006.257.05:32:49.28#ibcon#first serial, iclass 19, count 0 2006.257.05:32:49.28#ibcon#enter sib2, iclass 19, count 0 2006.257.05:32:49.28#ibcon#flushed, iclass 19, count 0 2006.257.05:32:49.28#ibcon#about to write, iclass 19, count 0 2006.257.05:32:49.28#ibcon#wrote, iclass 19, count 0 2006.257.05:32:49.28#ibcon#about to read 3, iclass 19, count 0 2006.257.05:32:49.30#ibcon#read 3, iclass 19, count 0 2006.257.05:32:49.30#ibcon#about to read 4, iclass 19, count 0 2006.257.05:32:49.30#ibcon#read 4, iclass 19, count 0 2006.257.05:32:49.30#ibcon#about to read 5, iclass 19, count 0 2006.257.05:32:49.30#ibcon#read 5, iclass 19, count 0 2006.257.05:32:49.30#ibcon#about to read 6, iclass 19, count 0 2006.257.05:32:49.30#ibcon#read 6, iclass 19, count 0 2006.257.05:32:49.30#ibcon#end of sib2, iclass 19, count 0 2006.257.05:32:49.30#ibcon#*mode == 0, iclass 19, count 0 2006.257.05:32:49.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.05:32:49.30#ibcon#[27=USB\r\n] 2006.257.05:32:49.30#ibcon#*before write, iclass 19, count 0 2006.257.05:32:49.30#ibcon#enter sib2, iclass 19, count 0 2006.257.05:32:49.30#ibcon#flushed, iclass 19, count 0 2006.257.05:32:49.30#ibcon#about to write, iclass 19, count 0 2006.257.05:32:49.30#ibcon#wrote, iclass 19, count 0 2006.257.05:32:49.30#ibcon#about to read 3, iclass 19, count 0 2006.257.05:32:49.33#ibcon#read 3, iclass 19, count 0 2006.257.05:32:49.33#ibcon#about to read 4, iclass 19, count 0 2006.257.05:32:49.33#ibcon#read 4, iclass 19, count 0 2006.257.05:32:49.33#ibcon#about to read 5, iclass 19, count 0 2006.257.05:32:49.33#ibcon#read 5, iclass 19, count 0 2006.257.05:32:49.33#ibcon#about to read 6, iclass 19, count 0 2006.257.05:32:49.33#ibcon#read 6, iclass 19, count 0 2006.257.05:32:49.33#ibcon#end of sib2, iclass 19, count 0 2006.257.05:32:49.33#ibcon#*after write, iclass 19, count 0 2006.257.05:32:49.33#ibcon#*before return 0, iclass 19, count 0 2006.257.05:32:49.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:32:49.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:32:49.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.05:32:49.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.05:32:49.33$vck44/vblo=2,634.99 2006.257.05:32:49.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.05:32:49.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.05:32:49.33#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:49.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:49.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:49.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:49.33#ibcon#enter wrdev, iclass 21, count 0 2006.257.05:32:49.33#ibcon#first serial, iclass 21, count 0 2006.257.05:32:49.33#ibcon#enter sib2, iclass 21, count 0 2006.257.05:32:49.33#ibcon#flushed, iclass 21, count 0 2006.257.05:32:49.33#ibcon#about to write, iclass 21, count 0 2006.257.05:32:49.33#ibcon#wrote, iclass 21, count 0 2006.257.05:32:49.33#ibcon#about to read 3, iclass 21, count 0 2006.257.05:32:49.35#ibcon#read 3, iclass 21, count 0 2006.257.05:32:49.35#ibcon#about to read 4, iclass 21, count 0 2006.257.05:32:49.35#ibcon#read 4, iclass 21, count 0 2006.257.05:32:49.35#ibcon#about to read 5, iclass 21, count 0 2006.257.05:32:49.35#ibcon#read 5, iclass 21, count 0 2006.257.05:32:49.35#ibcon#about to read 6, iclass 21, count 0 2006.257.05:32:49.35#ibcon#read 6, iclass 21, count 0 2006.257.05:32:49.35#ibcon#end of sib2, iclass 21, count 0 2006.257.05:32:49.35#ibcon#*mode == 0, iclass 21, count 0 2006.257.05:32:49.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.05:32:49.35#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:32:49.35#ibcon#*before write, iclass 21, count 0 2006.257.05:32:49.35#ibcon#enter sib2, iclass 21, count 0 2006.257.05:32:49.35#ibcon#flushed, iclass 21, count 0 2006.257.05:32:49.35#ibcon#about to write, iclass 21, count 0 2006.257.05:32:49.35#ibcon#wrote, iclass 21, count 0 2006.257.05:32:49.35#ibcon#about to read 3, iclass 21, count 0 2006.257.05:32:49.39#ibcon#read 3, iclass 21, count 0 2006.257.05:32:49.39#ibcon#about to read 4, iclass 21, count 0 2006.257.05:32:49.39#ibcon#read 4, iclass 21, count 0 2006.257.05:32:49.39#ibcon#about to read 5, iclass 21, count 0 2006.257.05:32:49.39#ibcon#read 5, iclass 21, count 0 2006.257.05:32:49.39#ibcon#about to read 6, iclass 21, count 0 2006.257.05:32:49.39#ibcon#read 6, iclass 21, count 0 2006.257.05:32:49.39#ibcon#end of sib2, iclass 21, count 0 2006.257.05:32:49.39#ibcon#*after write, iclass 21, count 0 2006.257.05:32:49.39#ibcon#*before return 0, iclass 21, count 0 2006.257.05:32:49.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:49.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:32:49.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.05:32:49.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.05:32:49.39$vck44/vb=2,5 2006.257.05:32:49.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.05:32:49.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.05:32:49.39#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:49.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:49.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:49.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:49.45#ibcon#enter wrdev, iclass 23, count 2 2006.257.05:32:49.45#ibcon#first serial, iclass 23, count 2 2006.257.05:32:49.45#ibcon#enter sib2, iclass 23, count 2 2006.257.05:32:49.45#ibcon#flushed, iclass 23, count 2 2006.257.05:32:49.45#ibcon#about to write, iclass 23, count 2 2006.257.05:32:49.45#ibcon#wrote, iclass 23, count 2 2006.257.05:32:49.45#ibcon#about to read 3, iclass 23, count 2 2006.257.05:32:49.47#ibcon#read 3, iclass 23, count 2 2006.257.05:32:49.47#ibcon#about to read 4, iclass 23, count 2 2006.257.05:32:49.47#ibcon#read 4, iclass 23, count 2 2006.257.05:32:49.47#ibcon#about to read 5, iclass 23, count 2 2006.257.05:32:49.47#ibcon#read 5, iclass 23, count 2 2006.257.05:32:49.47#ibcon#about to read 6, iclass 23, count 2 2006.257.05:32:49.47#ibcon#read 6, iclass 23, count 2 2006.257.05:32:49.47#ibcon#end of sib2, iclass 23, count 2 2006.257.05:32:49.47#ibcon#*mode == 0, iclass 23, count 2 2006.257.05:32:49.47#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.05:32:49.47#ibcon#[27=AT02-05\r\n] 2006.257.05:32:49.47#ibcon#*before write, iclass 23, count 2 2006.257.05:32:49.47#ibcon#enter sib2, iclass 23, count 2 2006.257.05:32:49.47#ibcon#flushed, iclass 23, count 2 2006.257.05:32:49.47#ibcon#about to write, iclass 23, count 2 2006.257.05:32:49.47#ibcon#wrote, iclass 23, count 2 2006.257.05:32:49.47#ibcon#about to read 3, iclass 23, count 2 2006.257.05:32:49.50#ibcon#read 3, iclass 23, count 2 2006.257.05:32:49.50#ibcon#about to read 4, iclass 23, count 2 2006.257.05:32:49.50#ibcon#read 4, iclass 23, count 2 2006.257.05:32:49.50#ibcon#about to read 5, iclass 23, count 2 2006.257.05:32:49.50#ibcon#read 5, iclass 23, count 2 2006.257.05:32:49.50#ibcon#about to read 6, iclass 23, count 2 2006.257.05:32:49.50#ibcon#read 6, iclass 23, count 2 2006.257.05:32:49.50#ibcon#end of sib2, iclass 23, count 2 2006.257.05:32:49.50#ibcon#*after write, iclass 23, count 2 2006.257.05:32:49.50#ibcon#*before return 0, iclass 23, count 2 2006.257.05:32:49.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:49.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:32:49.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.05:32:49.50#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:49.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:49.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:49.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:49.62#ibcon#enter wrdev, iclass 23, count 0 2006.257.05:32:49.62#ibcon#first serial, iclass 23, count 0 2006.257.05:32:49.62#ibcon#enter sib2, iclass 23, count 0 2006.257.05:32:49.62#ibcon#flushed, iclass 23, count 0 2006.257.05:32:49.62#ibcon#about to write, iclass 23, count 0 2006.257.05:32:49.62#ibcon#wrote, iclass 23, count 0 2006.257.05:32:49.62#ibcon#about to read 3, iclass 23, count 0 2006.257.05:32:49.64#ibcon#read 3, iclass 23, count 0 2006.257.05:32:49.64#ibcon#about to read 4, iclass 23, count 0 2006.257.05:32:49.64#ibcon#read 4, iclass 23, count 0 2006.257.05:32:49.64#ibcon#about to read 5, iclass 23, count 0 2006.257.05:32:49.64#ibcon#read 5, iclass 23, count 0 2006.257.05:32:49.64#ibcon#about to read 6, iclass 23, count 0 2006.257.05:32:49.64#ibcon#read 6, iclass 23, count 0 2006.257.05:32:49.64#ibcon#end of sib2, iclass 23, count 0 2006.257.05:32:49.64#ibcon#*mode == 0, iclass 23, count 0 2006.257.05:32:49.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.05:32:49.64#ibcon#[27=USB\r\n] 2006.257.05:32:49.64#ibcon#*before write, iclass 23, count 0 2006.257.05:32:49.64#ibcon#enter sib2, iclass 23, count 0 2006.257.05:32:49.64#ibcon#flushed, iclass 23, count 0 2006.257.05:32:49.64#ibcon#about to write, iclass 23, count 0 2006.257.05:32:49.64#ibcon#wrote, iclass 23, count 0 2006.257.05:32:49.64#ibcon#about to read 3, iclass 23, count 0 2006.257.05:32:49.67#ibcon#read 3, iclass 23, count 0 2006.257.05:32:49.67#ibcon#about to read 4, iclass 23, count 0 2006.257.05:32:49.67#ibcon#read 4, iclass 23, count 0 2006.257.05:32:49.67#ibcon#about to read 5, iclass 23, count 0 2006.257.05:32:49.67#ibcon#read 5, iclass 23, count 0 2006.257.05:32:49.67#ibcon#about to read 6, iclass 23, count 0 2006.257.05:32:49.67#ibcon#read 6, iclass 23, count 0 2006.257.05:32:49.67#ibcon#end of sib2, iclass 23, count 0 2006.257.05:32:49.67#ibcon#*after write, iclass 23, count 0 2006.257.05:32:49.67#ibcon#*before return 0, iclass 23, count 0 2006.257.05:32:49.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:49.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:32:49.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.05:32:49.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.05:32:49.67$vck44/vblo=3,649.99 2006.257.05:32:49.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.05:32:49.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.05:32:49.67#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:49.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:49.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:49.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:49.67#ibcon#enter wrdev, iclass 25, count 0 2006.257.05:32:49.67#ibcon#first serial, iclass 25, count 0 2006.257.05:32:49.67#ibcon#enter sib2, iclass 25, count 0 2006.257.05:32:49.67#ibcon#flushed, iclass 25, count 0 2006.257.05:32:49.67#ibcon#about to write, iclass 25, count 0 2006.257.05:32:49.67#ibcon#wrote, iclass 25, count 0 2006.257.05:32:49.67#ibcon#about to read 3, iclass 25, count 0 2006.257.05:32:49.69#ibcon#read 3, iclass 25, count 0 2006.257.05:32:49.69#ibcon#about to read 4, iclass 25, count 0 2006.257.05:32:49.69#ibcon#read 4, iclass 25, count 0 2006.257.05:32:49.69#ibcon#about to read 5, iclass 25, count 0 2006.257.05:32:49.69#ibcon#read 5, iclass 25, count 0 2006.257.05:32:49.69#ibcon#about to read 6, iclass 25, count 0 2006.257.05:32:49.69#ibcon#read 6, iclass 25, count 0 2006.257.05:32:49.69#ibcon#end of sib2, iclass 25, count 0 2006.257.05:32:49.69#ibcon#*mode == 0, iclass 25, count 0 2006.257.05:32:49.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.05:32:49.69#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:32:49.69#ibcon#*before write, iclass 25, count 0 2006.257.05:32:49.69#ibcon#enter sib2, iclass 25, count 0 2006.257.05:32:49.69#ibcon#flushed, iclass 25, count 0 2006.257.05:32:49.69#ibcon#about to write, iclass 25, count 0 2006.257.05:32:49.69#ibcon#wrote, iclass 25, count 0 2006.257.05:32:49.69#ibcon#about to read 3, iclass 25, count 0 2006.257.05:32:49.73#ibcon#read 3, iclass 25, count 0 2006.257.05:32:49.73#ibcon#about to read 4, iclass 25, count 0 2006.257.05:32:49.73#ibcon#read 4, iclass 25, count 0 2006.257.05:32:49.73#ibcon#about to read 5, iclass 25, count 0 2006.257.05:32:49.73#ibcon#read 5, iclass 25, count 0 2006.257.05:32:49.73#ibcon#about to read 6, iclass 25, count 0 2006.257.05:32:49.73#ibcon#read 6, iclass 25, count 0 2006.257.05:32:49.73#ibcon#end of sib2, iclass 25, count 0 2006.257.05:32:49.73#ibcon#*after write, iclass 25, count 0 2006.257.05:32:49.73#ibcon#*before return 0, iclass 25, count 0 2006.257.05:32:49.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:49.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:32:49.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.05:32:49.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.05:32:49.73$vck44/vb=3,4 2006.257.05:32:49.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.05:32:49.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.05:32:49.73#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:49.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:49.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:49.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:49.79#ibcon#enter wrdev, iclass 27, count 2 2006.257.05:32:49.79#ibcon#first serial, iclass 27, count 2 2006.257.05:32:49.79#ibcon#enter sib2, iclass 27, count 2 2006.257.05:32:49.79#ibcon#flushed, iclass 27, count 2 2006.257.05:32:49.79#ibcon#about to write, iclass 27, count 2 2006.257.05:32:49.79#ibcon#wrote, iclass 27, count 2 2006.257.05:32:49.79#ibcon#about to read 3, iclass 27, count 2 2006.257.05:32:49.81#ibcon#read 3, iclass 27, count 2 2006.257.05:32:49.81#ibcon#about to read 4, iclass 27, count 2 2006.257.05:32:49.81#ibcon#read 4, iclass 27, count 2 2006.257.05:32:49.81#ibcon#about to read 5, iclass 27, count 2 2006.257.05:32:49.81#ibcon#read 5, iclass 27, count 2 2006.257.05:32:49.81#ibcon#about to read 6, iclass 27, count 2 2006.257.05:32:49.81#ibcon#read 6, iclass 27, count 2 2006.257.05:32:49.81#ibcon#end of sib2, iclass 27, count 2 2006.257.05:32:49.81#ibcon#*mode == 0, iclass 27, count 2 2006.257.05:32:49.81#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.05:32:49.81#ibcon#[27=AT03-04\r\n] 2006.257.05:32:49.81#ibcon#*before write, iclass 27, count 2 2006.257.05:32:49.81#ibcon#enter sib2, iclass 27, count 2 2006.257.05:32:49.81#ibcon#flushed, iclass 27, count 2 2006.257.05:32:49.81#ibcon#about to write, iclass 27, count 2 2006.257.05:32:49.81#ibcon#wrote, iclass 27, count 2 2006.257.05:32:49.81#ibcon#about to read 3, iclass 27, count 2 2006.257.05:32:49.84#ibcon#read 3, iclass 27, count 2 2006.257.05:32:49.84#ibcon#about to read 4, iclass 27, count 2 2006.257.05:32:49.84#ibcon#read 4, iclass 27, count 2 2006.257.05:32:49.84#ibcon#about to read 5, iclass 27, count 2 2006.257.05:32:49.84#ibcon#read 5, iclass 27, count 2 2006.257.05:32:49.84#ibcon#about to read 6, iclass 27, count 2 2006.257.05:32:49.84#ibcon#read 6, iclass 27, count 2 2006.257.05:32:49.84#ibcon#end of sib2, iclass 27, count 2 2006.257.05:32:49.84#ibcon#*after write, iclass 27, count 2 2006.257.05:32:49.84#ibcon#*before return 0, iclass 27, count 2 2006.257.05:32:49.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:49.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:32:49.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.05:32:49.84#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:49.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:49.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:49.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:49.96#ibcon#enter wrdev, iclass 27, count 0 2006.257.05:32:49.96#ibcon#first serial, iclass 27, count 0 2006.257.05:32:49.96#ibcon#enter sib2, iclass 27, count 0 2006.257.05:32:49.96#ibcon#flushed, iclass 27, count 0 2006.257.05:32:49.96#ibcon#about to write, iclass 27, count 0 2006.257.05:32:49.96#ibcon#wrote, iclass 27, count 0 2006.257.05:32:49.96#ibcon#about to read 3, iclass 27, count 0 2006.257.05:32:49.98#ibcon#read 3, iclass 27, count 0 2006.257.05:32:49.98#ibcon#about to read 4, iclass 27, count 0 2006.257.05:32:49.98#ibcon#read 4, iclass 27, count 0 2006.257.05:32:49.98#ibcon#about to read 5, iclass 27, count 0 2006.257.05:32:49.98#ibcon#read 5, iclass 27, count 0 2006.257.05:32:49.98#ibcon#about to read 6, iclass 27, count 0 2006.257.05:32:49.98#ibcon#read 6, iclass 27, count 0 2006.257.05:32:49.98#ibcon#end of sib2, iclass 27, count 0 2006.257.05:32:49.98#ibcon#*mode == 0, iclass 27, count 0 2006.257.05:32:49.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.05:32:49.98#ibcon#[27=USB\r\n] 2006.257.05:32:49.98#ibcon#*before write, iclass 27, count 0 2006.257.05:32:49.98#ibcon#enter sib2, iclass 27, count 0 2006.257.05:32:49.98#ibcon#flushed, iclass 27, count 0 2006.257.05:32:49.98#ibcon#about to write, iclass 27, count 0 2006.257.05:32:49.98#ibcon#wrote, iclass 27, count 0 2006.257.05:32:49.98#ibcon#about to read 3, iclass 27, count 0 2006.257.05:32:50.01#ibcon#read 3, iclass 27, count 0 2006.257.05:32:50.01#ibcon#about to read 4, iclass 27, count 0 2006.257.05:32:50.01#ibcon#read 4, iclass 27, count 0 2006.257.05:32:50.01#ibcon#about to read 5, iclass 27, count 0 2006.257.05:32:50.01#ibcon#read 5, iclass 27, count 0 2006.257.05:32:50.01#ibcon#about to read 6, iclass 27, count 0 2006.257.05:32:50.01#ibcon#read 6, iclass 27, count 0 2006.257.05:32:50.01#ibcon#end of sib2, iclass 27, count 0 2006.257.05:32:50.01#ibcon#*after write, iclass 27, count 0 2006.257.05:32:50.01#ibcon#*before return 0, iclass 27, count 0 2006.257.05:32:50.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:50.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:32:50.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.05:32:50.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.05:32:50.01$vck44/vblo=4,679.99 2006.257.05:32:50.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.05:32:50.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.05:32:50.01#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:50.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:50.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:50.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:50.01#ibcon#enter wrdev, iclass 29, count 0 2006.257.05:32:50.01#ibcon#first serial, iclass 29, count 0 2006.257.05:32:50.01#ibcon#enter sib2, iclass 29, count 0 2006.257.05:32:50.01#ibcon#flushed, iclass 29, count 0 2006.257.05:32:50.01#ibcon#about to write, iclass 29, count 0 2006.257.05:32:50.01#ibcon#wrote, iclass 29, count 0 2006.257.05:32:50.01#ibcon#about to read 3, iclass 29, count 0 2006.257.05:32:50.03#ibcon#read 3, iclass 29, count 0 2006.257.05:32:50.03#ibcon#about to read 4, iclass 29, count 0 2006.257.05:32:50.03#ibcon#read 4, iclass 29, count 0 2006.257.05:32:50.03#ibcon#about to read 5, iclass 29, count 0 2006.257.05:32:50.03#ibcon#read 5, iclass 29, count 0 2006.257.05:32:50.03#ibcon#about to read 6, iclass 29, count 0 2006.257.05:32:50.03#ibcon#read 6, iclass 29, count 0 2006.257.05:32:50.03#ibcon#end of sib2, iclass 29, count 0 2006.257.05:32:50.03#ibcon#*mode == 0, iclass 29, count 0 2006.257.05:32:50.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.05:32:50.03#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:32:50.03#ibcon#*before write, iclass 29, count 0 2006.257.05:32:50.03#ibcon#enter sib2, iclass 29, count 0 2006.257.05:32:50.03#ibcon#flushed, iclass 29, count 0 2006.257.05:32:50.03#ibcon#about to write, iclass 29, count 0 2006.257.05:32:50.03#ibcon#wrote, iclass 29, count 0 2006.257.05:32:50.03#ibcon#about to read 3, iclass 29, count 0 2006.257.05:32:50.07#ibcon#read 3, iclass 29, count 0 2006.257.05:32:50.07#ibcon#about to read 4, iclass 29, count 0 2006.257.05:32:50.07#ibcon#read 4, iclass 29, count 0 2006.257.05:32:50.07#ibcon#about to read 5, iclass 29, count 0 2006.257.05:32:50.07#ibcon#read 5, iclass 29, count 0 2006.257.05:32:50.07#ibcon#about to read 6, iclass 29, count 0 2006.257.05:32:50.07#ibcon#read 6, iclass 29, count 0 2006.257.05:32:50.07#ibcon#end of sib2, iclass 29, count 0 2006.257.05:32:50.07#ibcon#*after write, iclass 29, count 0 2006.257.05:32:50.07#ibcon#*before return 0, iclass 29, count 0 2006.257.05:32:50.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:50.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:32:50.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.05:32:50.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.05:32:50.07$vck44/vb=4,5 2006.257.05:32:50.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.05:32:50.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.05:32:50.07#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:50.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:50.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:50.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:50.13#ibcon#enter wrdev, iclass 31, count 2 2006.257.05:32:50.13#ibcon#first serial, iclass 31, count 2 2006.257.05:32:50.13#ibcon#enter sib2, iclass 31, count 2 2006.257.05:32:50.13#ibcon#flushed, iclass 31, count 2 2006.257.05:32:50.13#ibcon#about to write, iclass 31, count 2 2006.257.05:32:50.13#ibcon#wrote, iclass 31, count 2 2006.257.05:32:50.13#ibcon#about to read 3, iclass 31, count 2 2006.257.05:32:50.15#ibcon#read 3, iclass 31, count 2 2006.257.05:32:50.15#ibcon#about to read 4, iclass 31, count 2 2006.257.05:32:50.15#ibcon#read 4, iclass 31, count 2 2006.257.05:32:50.15#ibcon#about to read 5, iclass 31, count 2 2006.257.05:32:50.15#ibcon#read 5, iclass 31, count 2 2006.257.05:32:50.15#ibcon#about to read 6, iclass 31, count 2 2006.257.05:32:50.15#ibcon#read 6, iclass 31, count 2 2006.257.05:32:50.15#ibcon#end of sib2, iclass 31, count 2 2006.257.05:32:50.15#ibcon#*mode == 0, iclass 31, count 2 2006.257.05:32:50.15#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.05:32:50.15#ibcon#[27=AT04-05\r\n] 2006.257.05:32:50.15#ibcon#*before write, iclass 31, count 2 2006.257.05:32:50.15#ibcon#enter sib2, iclass 31, count 2 2006.257.05:32:50.15#ibcon#flushed, iclass 31, count 2 2006.257.05:32:50.15#ibcon#about to write, iclass 31, count 2 2006.257.05:32:50.15#ibcon#wrote, iclass 31, count 2 2006.257.05:32:50.15#ibcon#about to read 3, iclass 31, count 2 2006.257.05:32:50.18#ibcon#read 3, iclass 31, count 2 2006.257.05:32:50.18#ibcon#about to read 4, iclass 31, count 2 2006.257.05:32:50.18#ibcon#read 4, iclass 31, count 2 2006.257.05:32:50.18#ibcon#about to read 5, iclass 31, count 2 2006.257.05:32:50.18#ibcon#read 5, iclass 31, count 2 2006.257.05:32:50.18#ibcon#about to read 6, iclass 31, count 2 2006.257.05:32:50.18#ibcon#read 6, iclass 31, count 2 2006.257.05:32:50.18#ibcon#end of sib2, iclass 31, count 2 2006.257.05:32:50.18#ibcon#*after write, iclass 31, count 2 2006.257.05:32:50.18#ibcon#*before return 0, iclass 31, count 2 2006.257.05:32:50.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:50.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:32:50.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.05:32:50.18#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:50.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:50.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:50.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:50.30#ibcon#enter wrdev, iclass 31, count 0 2006.257.05:32:50.30#ibcon#first serial, iclass 31, count 0 2006.257.05:32:50.30#ibcon#enter sib2, iclass 31, count 0 2006.257.05:32:50.30#ibcon#flushed, iclass 31, count 0 2006.257.05:32:50.30#ibcon#about to write, iclass 31, count 0 2006.257.05:32:50.30#ibcon#wrote, iclass 31, count 0 2006.257.05:32:50.30#ibcon#about to read 3, iclass 31, count 0 2006.257.05:32:50.32#ibcon#read 3, iclass 31, count 0 2006.257.05:32:50.32#ibcon#about to read 4, iclass 31, count 0 2006.257.05:32:50.32#ibcon#read 4, iclass 31, count 0 2006.257.05:32:50.32#ibcon#about to read 5, iclass 31, count 0 2006.257.05:32:50.32#ibcon#read 5, iclass 31, count 0 2006.257.05:32:50.32#ibcon#about to read 6, iclass 31, count 0 2006.257.05:32:50.32#ibcon#read 6, iclass 31, count 0 2006.257.05:32:50.32#ibcon#end of sib2, iclass 31, count 0 2006.257.05:32:50.32#ibcon#*mode == 0, iclass 31, count 0 2006.257.05:32:50.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.05:32:50.32#ibcon#[27=USB\r\n] 2006.257.05:32:50.32#ibcon#*before write, iclass 31, count 0 2006.257.05:32:50.32#ibcon#enter sib2, iclass 31, count 0 2006.257.05:32:50.32#ibcon#flushed, iclass 31, count 0 2006.257.05:32:50.32#ibcon#about to write, iclass 31, count 0 2006.257.05:32:50.32#ibcon#wrote, iclass 31, count 0 2006.257.05:32:50.32#ibcon#about to read 3, iclass 31, count 0 2006.257.05:32:50.35#ibcon#read 3, iclass 31, count 0 2006.257.05:32:50.35#ibcon#about to read 4, iclass 31, count 0 2006.257.05:32:50.35#ibcon#read 4, iclass 31, count 0 2006.257.05:32:50.35#ibcon#about to read 5, iclass 31, count 0 2006.257.05:32:50.35#ibcon#read 5, iclass 31, count 0 2006.257.05:32:50.35#ibcon#about to read 6, iclass 31, count 0 2006.257.05:32:50.35#ibcon#read 6, iclass 31, count 0 2006.257.05:32:50.35#ibcon#end of sib2, iclass 31, count 0 2006.257.05:32:50.35#ibcon#*after write, iclass 31, count 0 2006.257.05:32:50.35#ibcon#*before return 0, iclass 31, count 0 2006.257.05:32:50.35#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:50.35#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:32:50.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.05:32:50.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.05:32:50.35$vck44/vblo=5,709.99 2006.257.05:32:50.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.05:32:50.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.05:32:50.35#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:50.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:50.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:50.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:50.35#ibcon#enter wrdev, iclass 33, count 0 2006.257.05:32:50.35#ibcon#first serial, iclass 33, count 0 2006.257.05:32:50.35#ibcon#enter sib2, iclass 33, count 0 2006.257.05:32:50.35#ibcon#flushed, iclass 33, count 0 2006.257.05:32:50.35#ibcon#about to write, iclass 33, count 0 2006.257.05:32:50.35#ibcon#wrote, iclass 33, count 0 2006.257.05:32:50.35#ibcon#about to read 3, iclass 33, count 0 2006.257.05:32:50.37#ibcon#read 3, iclass 33, count 0 2006.257.05:32:50.37#ibcon#about to read 4, iclass 33, count 0 2006.257.05:32:50.37#ibcon#read 4, iclass 33, count 0 2006.257.05:32:50.37#ibcon#about to read 5, iclass 33, count 0 2006.257.05:32:50.37#ibcon#read 5, iclass 33, count 0 2006.257.05:32:50.37#ibcon#about to read 6, iclass 33, count 0 2006.257.05:32:50.37#ibcon#read 6, iclass 33, count 0 2006.257.05:32:50.37#ibcon#end of sib2, iclass 33, count 0 2006.257.05:32:50.37#ibcon#*mode == 0, iclass 33, count 0 2006.257.05:32:50.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.05:32:50.37#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:32:50.37#ibcon#*before write, iclass 33, count 0 2006.257.05:32:50.37#ibcon#enter sib2, iclass 33, count 0 2006.257.05:32:50.37#ibcon#flushed, iclass 33, count 0 2006.257.05:32:50.37#ibcon#about to write, iclass 33, count 0 2006.257.05:32:50.37#ibcon#wrote, iclass 33, count 0 2006.257.05:32:50.37#ibcon#about to read 3, iclass 33, count 0 2006.257.05:32:50.41#ibcon#read 3, iclass 33, count 0 2006.257.05:32:50.41#ibcon#about to read 4, iclass 33, count 0 2006.257.05:32:50.41#ibcon#read 4, iclass 33, count 0 2006.257.05:32:50.41#ibcon#about to read 5, iclass 33, count 0 2006.257.05:32:50.41#ibcon#read 5, iclass 33, count 0 2006.257.05:32:50.41#ibcon#about to read 6, iclass 33, count 0 2006.257.05:32:50.41#ibcon#read 6, iclass 33, count 0 2006.257.05:32:50.41#ibcon#end of sib2, iclass 33, count 0 2006.257.05:32:50.41#ibcon#*after write, iclass 33, count 0 2006.257.05:32:50.41#ibcon#*before return 0, iclass 33, count 0 2006.257.05:32:50.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:50.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:32:50.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.05:32:50.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.05:32:50.41$vck44/vb=5,4 2006.257.05:32:50.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.05:32:50.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.05:32:50.41#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:50.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:50.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:50.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:50.47#ibcon#enter wrdev, iclass 35, count 2 2006.257.05:32:50.47#ibcon#first serial, iclass 35, count 2 2006.257.05:32:50.47#ibcon#enter sib2, iclass 35, count 2 2006.257.05:32:50.47#ibcon#flushed, iclass 35, count 2 2006.257.05:32:50.47#ibcon#about to write, iclass 35, count 2 2006.257.05:32:50.47#ibcon#wrote, iclass 35, count 2 2006.257.05:32:50.47#ibcon#about to read 3, iclass 35, count 2 2006.257.05:32:50.49#ibcon#read 3, iclass 35, count 2 2006.257.05:32:50.49#ibcon#about to read 4, iclass 35, count 2 2006.257.05:32:50.49#ibcon#read 4, iclass 35, count 2 2006.257.05:32:50.49#ibcon#about to read 5, iclass 35, count 2 2006.257.05:32:50.49#ibcon#read 5, iclass 35, count 2 2006.257.05:32:50.49#ibcon#about to read 6, iclass 35, count 2 2006.257.05:32:50.49#ibcon#read 6, iclass 35, count 2 2006.257.05:32:50.49#ibcon#end of sib2, iclass 35, count 2 2006.257.05:32:50.49#ibcon#*mode == 0, iclass 35, count 2 2006.257.05:32:50.49#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.05:32:50.49#ibcon#[27=AT05-04\r\n] 2006.257.05:32:50.49#ibcon#*before write, iclass 35, count 2 2006.257.05:32:50.49#ibcon#enter sib2, iclass 35, count 2 2006.257.05:32:50.49#ibcon#flushed, iclass 35, count 2 2006.257.05:32:50.49#ibcon#about to write, iclass 35, count 2 2006.257.05:32:50.49#ibcon#wrote, iclass 35, count 2 2006.257.05:32:50.49#ibcon#about to read 3, iclass 35, count 2 2006.257.05:32:50.52#ibcon#read 3, iclass 35, count 2 2006.257.05:32:50.52#ibcon#about to read 4, iclass 35, count 2 2006.257.05:32:50.52#ibcon#read 4, iclass 35, count 2 2006.257.05:32:50.52#ibcon#about to read 5, iclass 35, count 2 2006.257.05:32:50.52#ibcon#read 5, iclass 35, count 2 2006.257.05:32:50.52#ibcon#about to read 6, iclass 35, count 2 2006.257.05:32:50.52#ibcon#read 6, iclass 35, count 2 2006.257.05:32:50.52#ibcon#end of sib2, iclass 35, count 2 2006.257.05:32:50.52#ibcon#*after write, iclass 35, count 2 2006.257.05:32:50.52#ibcon#*before return 0, iclass 35, count 2 2006.257.05:32:50.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:50.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:32:50.52#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.05:32:50.52#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:50.52#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:50.64#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:50.64#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:50.64#ibcon#enter wrdev, iclass 35, count 0 2006.257.05:32:50.64#ibcon#first serial, iclass 35, count 0 2006.257.05:32:50.64#ibcon#enter sib2, iclass 35, count 0 2006.257.05:32:50.64#ibcon#flushed, iclass 35, count 0 2006.257.05:32:50.64#ibcon#about to write, iclass 35, count 0 2006.257.05:32:50.64#ibcon#wrote, iclass 35, count 0 2006.257.05:32:50.64#ibcon#about to read 3, iclass 35, count 0 2006.257.05:32:50.66#ibcon#read 3, iclass 35, count 0 2006.257.05:32:50.66#ibcon#about to read 4, iclass 35, count 0 2006.257.05:32:50.66#ibcon#read 4, iclass 35, count 0 2006.257.05:32:50.66#ibcon#about to read 5, iclass 35, count 0 2006.257.05:32:50.66#ibcon#read 5, iclass 35, count 0 2006.257.05:32:50.66#ibcon#about to read 6, iclass 35, count 0 2006.257.05:32:50.66#ibcon#read 6, iclass 35, count 0 2006.257.05:32:50.66#ibcon#end of sib2, iclass 35, count 0 2006.257.05:32:50.66#ibcon#*mode == 0, iclass 35, count 0 2006.257.05:32:50.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.05:32:50.66#ibcon#[27=USB\r\n] 2006.257.05:32:50.66#ibcon#*before write, iclass 35, count 0 2006.257.05:32:50.66#ibcon#enter sib2, iclass 35, count 0 2006.257.05:32:50.66#ibcon#flushed, iclass 35, count 0 2006.257.05:32:50.66#ibcon#about to write, iclass 35, count 0 2006.257.05:32:50.66#ibcon#wrote, iclass 35, count 0 2006.257.05:32:50.66#ibcon#about to read 3, iclass 35, count 0 2006.257.05:32:50.69#ibcon#read 3, iclass 35, count 0 2006.257.05:32:50.69#ibcon#about to read 4, iclass 35, count 0 2006.257.05:32:50.69#ibcon#read 4, iclass 35, count 0 2006.257.05:32:50.69#ibcon#about to read 5, iclass 35, count 0 2006.257.05:32:50.69#ibcon#read 5, iclass 35, count 0 2006.257.05:32:50.69#ibcon#about to read 6, iclass 35, count 0 2006.257.05:32:50.69#ibcon#read 6, iclass 35, count 0 2006.257.05:32:50.69#ibcon#end of sib2, iclass 35, count 0 2006.257.05:32:50.69#ibcon#*after write, iclass 35, count 0 2006.257.05:32:50.69#ibcon#*before return 0, iclass 35, count 0 2006.257.05:32:50.69#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:50.69#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:32:50.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.05:32:50.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.05:32:50.69$vck44/vblo=6,719.99 2006.257.05:32:50.69#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.05:32:50.69#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.05:32:50.69#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:50.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:50.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:50.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:50.69#ibcon#enter wrdev, iclass 37, count 0 2006.257.05:32:50.69#ibcon#first serial, iclass 37, count 0 2006.257.05:32:50.69#ibcon#enter sib2, iclass 37, count 0 2006.257.05:32:50.69#ibcon#flushed, iclass 37, count 0 2006.257.05:32:50.69#ibcon#about to write, iclass 37, count 0 2006.257.05:32:50.69#ibcon#wrote, iclass 37, count 0 2006.257.05:32:50.69#ibcon#about to read 3, iclass 37, count 0 2006.257.05:32:50.71#ibcon#read 3, iclass 37, count 0 2006.257.05:32:50.71#ibcon#about to read 4, iclass 37, count 0 2006.257.05:32:50.71#ibcon#read 4, iclass 37, count 0 2006.257.05:32:50.71#ibcon#about to read 5, iclass 37, count 0 2006.257.05:32:50.71#ibcon#read 5, iclass 37, count 0 2006.257.05:32:50.71#ibcon#about to read 6, iclass 37, count 0 2006.257.05:32:50.71#ibcon#read 6, iclass 37, count 0 2006.257.05:32:50.71#ibcon#end of sib2, iclass 37, count 0 2006.257.05:32:50.71#ibcon#*mode == 0, iclass 37, count 0 2006.257.05:32:50.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.05:32:50.71#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:32:50.71#ibcon#*before write, iclass 37, count 0 2006.257.05:32:50.71#ibcon#enter sib2, iclass 37, count 0 2006.257.05:32:50.71#ibcon#flushed, iclass 37, count 0 2006.257.05:32:50.71#ibcon#about to write, iclass 37, count 0 2006.257.05:32:50.71#ibcon#wrote, iclass 37, count 0 2006.257.05:32:50.71#ibcon#about to read 3, iclass 37, count 0 2006.257.05:32:50.75#ibcon#read 3, iclass 37, count 0 2006.257.05:32:50.75#ibcon#about to read 4, iclass 37, count 0 2006.257.05:32:50.75#ibcon#read 4, iclass 37, count 0 2006.257.05:32:50.75#ibcon#about to read 5, iclass 37, count 0 2006.257.05:32:50.75#ibcon#read 5, iclass 37, count 0 2006.257.05:32:50.75#ibcon#about to read 6, iclass 37, count 0 2006.257.05:32:50.75#ibcon#read 6, iclass 37, count 0 2006.257.05:32:50.75#ibcon#end of sib2, iclass 37, count 0 2006.257.05:32:50.75#ibcon#*after write, iclass 37, count 0 2006.257.05:32:50.75#ibcon#*before return 0, iclass 37, count 0 2006.257.05:32:50.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:50.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:32:50.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.05:32:50.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.05:32:50.75$vck44/vb=6,4 2006.257.05:32:50.75#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.05:32:50.75#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.05:32:50.75#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:50.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:50.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:50.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:50.81#ibcon#enter wrdev, iclass 39, count 2 2006.257.05:32:50.81#ibcon#first serial, iclass 39, count 2 2006.257.05:32:50.81#ibcon#enter sib2, iclass 39, count 2 2006.257.05:32:50.81#ibcon#flushed, iclass 39, count 2 2006.257.05:32:50.81#ibcon#about to write, iclass 39, count 2 2006.257.05:32:50.81#ibcon#wrote, iclass 39, count 2 2006.257.05:32:50.81#ibcon#about to read 3, iclass 39, count 2 2006.257.05:32:50.83#ibcon#read 3, iclass 39, count 2 2006.257.05:32:50.83#ibcon#about to read 4, iclass 39, count 2 2006.257.05:32:50.83#ibcon#read 4, iclass 39, count 2 2006.257.05:32:50.83#ibcon#about to read 5, iclass 39, count 2 2006.257.05:32:50.83#ibcon#read 5, iclass 39, count 2 2006.257.05:32:50.83#ibcon#about to read 6, iclass 39, count 2 2006.257.05:32:50.83#ibcon#read 6, iclass 39, count 2 2006.257.05:32:50.83#ibcon#end of sib2, iclass 39, count 2 2006.257.05:32:50.83#ibcon#*mode == 0, iclass 39, count 2 2006.257.05:32:50.83#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.05:32:50.83#ibcon#[27=AT06-04\r\n] 2006.257.05:32:50.83#ibcon#*before write, iclass 39, count 2 2006.257.05:32:50.83#ibcon#enter sib2, iclass 39, count 2 2006.257.05:32:50.83#ibcon#flushed, iclass 39, count 2 2006.257.05:32:50.83#ibcon#about to write, iclass 39, count 2 2006.257.05:32:50.83#ibcon#wrote, iclass 39, count 2 2006.257.05:32:50.83#ibcon#about to read 3, iclass 39, count 2 2006.257.05:32:50.86#ibcon#read 3, iclass 39, count 2 2006.257.05:32:50.86#ibcon#about to read 4, iclass 39, count 2 2006.257.05:32:50.86#ibcon#read 4, iclass 39, count 2 2006.257.05:32:50.86#ibcon#about to read 5, iclass 39, count 2 2006.257.05:32:50.86#ibcon#read 5, iclass 39, count 2 2006.257.05:32:50.86#ibcon#about to read 6, iclass 39, count 2 2006.257.05:32:50.86#ibcon#read 6, iclass 39, count 2 2006.257.05:32:50.86#ibcon#end of sib2, iclass 39, count 2 2006.257.05:32:50.86#ibcon#*after write, iclass 39, count 2 2006.257.05:32:50.86#ibcon#*before return 0, iclass 39, count 2 2006.257.05:32:50.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:50.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:32:50.86#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.05:32:50.86#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:50.86#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:50.98#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:50.98#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:50.98#ibcon#enter wrdev, iclass 39, count 0 2006.257.05:32:50.98#ibcon#first serial, iclass 39, count 0 2006.257.05:32:50.98#ibcon#enter sib2, iclass 39, count 0 2006.257.05:32:50.98#ibcon#flushed, iclass 39, count 0 2006.257.05:32:50.98#ibcon#about to write, iclass 39, count 0 2006.257.05:32:50.98#ibcon#wrote, iclass 39, count 0 2006.257.05:32:50.98#ibcon#about to read 3, iclass 39, count 0 2006.257.05:32:51.00#ibcon#read 3, iclass 39, count 0 2006.257.05:32:51.00#ibcon#about to read 4, iclass 39, count 0 2006.257.05:32:51.00#ibcon#read 4, iclass 39, count 0 2006.257.05:32:51.00#ibcon#about to read 5, iclass 39, count 0 2006.257.05:32:51.00#ibcon#read 5, iclass 39, count 0 2006.257.05:32:51.00#ibcon#about to read 6, iclass 39, count 0 2006.257.05:32:51.00#ibcon#read 6, iclass 39, count 0 2006.257.05:32:51.00#ibcon#end of sib2, iclass 39, count 0 2006.257.05:32:51.00#ibcon#*mode == 0, iclass 39, count 0 2006.257.05:32:51.00#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.05:32:51.00#ibcon#[27=USB\r\n] 2006.257.05:32:51.00#ibcon#*before write, iclass 39, count 0 2006.257.05:32:51.00#ibcon#enter sib2, iclass 39, count 0 2006.257.05:32:51.00#ibcon#flushed, iclass 39, count 0 2006.257.05:32:51.00#ibcon#about to write, iclass 39, count 0 2006.257.05:32:51.00#ibcon#wrote, iclass 39, count 0 2006.257.05:32:51.00#ibcon#about to read 3, iclass 39, count 0 2006.257.05:32:51.03#ibcon#read 3, iclass 39, count 0 2006.257.05:32:51.03#ibcon#about to read 4, iclass 39, count 0 2006.257.05:32:51.03#ibcon#read 4, iclass 39, count 0 2006.257.05:32:51.03#ibcon#about to read 5, iclass 39, count 0 2006.257.05:32:51.03#ibcon#read 5, iclass 39, count 0 2006.257.05:32:51.03#ibcon#about to read 6, iclass 39, count 0 2006.257.05:32:51.03#ibcon#read 6, iclass 39, count 0 2006.257.05:32:51.03#ibcon#end of sib2, iclass 39, count 0 2006.257.05:32:51.03#ibcon#*after write, iclass 39, count 0 2006.257.05:32:51.03#ibcon#*before return 0, iclass 39, count 0 2006.257.05:32:51.03#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:51.03#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:32:51.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.05:32:51.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.05:32:51.03$vck44/vblo=7,734.99 2006.257.05:32:51.03#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.05:32:51.03#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.05:32:51.03#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:51.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:51.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:51.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:51.03#ibcon#enter wrdev, iclass 3, count 0 2006.257.05:32:51.03#ibcon#first serial, iclass 3, count 0 2006.257.05:32:51.03#ibcon#enter sib2, iclass 3, count 0 2006.257.05:32:51.03#ibcon#flushed, iclass 3, count 0 2006.257.05:32:51.03#ibcon#about to write, iclass 3, count 0 2006.257.05:32:51.03#ibcon#wrote, iclass 3, count 0 2006.257.05:32:51.03#ibcon#about to read 3, iclass 3, count 0 2006.257.05:32:51.05#ibcon#read 3, iclass 3, count 0 2006.257.05:32:51.05#ibcon#about to read 4, iclass 3, count 0 2006.257.05:32:51.05#ibcon#read 4, iclass 3, count 0 2006.257.05:32:51.05#ibcon#about to read 5, iclass 3, count 0 2006.257.05:32:51.05#ibcon#read 5, iclass 3, count 0 2006.257.05:32:51.05#ibcon#about to read 6, iclass 3, count 0 2006.257.05:32:51.05#ibcon#read 6, iclass 3, count 0 2006.257.05:32:51.05#ibcon#end of sib2, iclass 3, count 0 2006.257.05:32:51.05#ibcon#*mode == 0, iclass 3, count 0 2006.257.05:32:51.05#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.05:32:51.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:32:51.05#ibcon#*before write, iclass 3, count 0 2006.257.05:32:51.05#ibcon#enter sib2, iclass 3, count 0 2006.257.05:32:51.05#ibcon#flushed, iclass 3, count 0 2006.257.05:32:51.05#ibcon#about to write, iclass 3, count 0 2006.257.05:32:51.05#ibcon#wrote, iclass 3, count 0 2006.257.05:32:51.05#ibcon#about to read 3, iclass 3, count 0 2006.257.05:32:51.09#ibcon#read 3, iclass 3, count 0 2006.257.05:32:51.09#ibcon#about to read 4, iclass 3, count 0 2006.257.05:32:51.09#ibcon#read 4, iclass 3, count 0 2006.257.05:32:51.09#ibcon#about to read 5, iclass 3, count 0 2006.257.05:32:51.09#ibcon#read 5, iclass 3, count 0 2006.257.05:32:51.09#ibcon#about to read 6, iclass 3, count 0 2006.257.05:32:51.09#ibcon#read 6, iclass 3, count 0 2006.257.05:32:51.09#ibcon#end of sib2, iclass 3, count 0 2006.257.05:32:51.09#ibcon#*after write, iclass 3, count 0 2006.257.05:32:51.09#ibcon#*before return 0, iclass 3, count 0 2006.257.05:32:51.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:51.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:32:51.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.05:32:51.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.05:32:51.09$vck44/vb=7,4 2006.257.05:32:51.09#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.05:32:51.09#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.05:32:51.09#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:51.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:51.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:51.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:51.15#ibcon#enter wrdev, iclass 5, count 2 2006.257.05:32:51.15#ibcon#first serial, iclass 5, count 2 2006.257.05:32:51.15#ibcon#enter sib2, iclass 5, count 2 2006.257.05:32:51.15#ibcon#flushed, iclass 5, count 2 2006.257.05:32:51.15#ibcon#about to write, iclass 5, count 2 2006.257.05:32:51.15#ibcon#wrote, iclass 5, count 2 2006.257.05:32:51.15#ibcon#about to read 3, iclass 5, count 2 2006.257.05:32:51.17#ibcon#read 3, iclass 5, count 2 2006.257.05:32:51.17#ibcon#about to read 4, iclass 5, count 2 2006.257.05:32:51.17#ibcon#read 4, iclass 5, count 2 2006.257.05:32:51.17#ibcon#about to read 5, iclass 5, count 2 2006.257.05:32:51.17#ibcon#read 5, iclass 5, count 2 2006.257.05:32:51.17#ibcon#about to read 6, iclass 5, count 2 2006.257.05:32:51.17#ibcon#read 6, iclass 5, count 2 2006.257.05:32:51.17#ibcon#end of sib2, iclass 5, count 2 2006.257.05:32:51.17#ibcon#*mode == 0, iclass 5, count 2 2006.257.05:32:51.17#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.05:32:51.17#ibcon#[27=AT07-04\r\n] 2006.257.05:32:51.17#ibcon#*before write, iclass 5, count 2 2006.257.05:32:51.17#ibcon#enter sib2, iclass 5, count 2 2006.257.05:32:51.17#ibcon#flushed, iclass 5, count 2 2006.257.05:32:51.17#ibcon#about to write, iclass 5, count 2 2006.257.05:32:51.17#ibcon#wrote, iclass 5, count 2 2006.257.05:32:51.17#ibcon#about to read 3, iclass 5, count 2 2006.257.05:32:51.20#ibcon#read 3, iclass 5, count 2 2006.257.05:32:51.20#ibcon#about to read 4, iclass 5, count 2 2006.257.05:32:51.20#ibcon#read 4, iclass 5, count 2 2006.257.05:32:51.20#ibcon#about to read 5, iclass 5, count 2 2006.257.05:32:51.20#ibcon#read 5, iclass 5, count 2 2006.257.05:32:51.20#ibcon#about to read 6, iclass 5, count 2 2006.257.05:32:51.20#ibcon#read 6, iclass 5, count 2 2006.257.05:32:51.20#ibcon#end of sib2, iclass 5, count 2 2006.257.05:32:51.20#ibcon#*after write, iclass 5, count 2 2006.257.05:32:51.20#ibcon#*before return 0, iclass 5, count 2 2006.257.05:32:51.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:51.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:32:51.20#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.05:32:51.20#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:51.20#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:51.32#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:51.32#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:51.32#ibcon#enter wrdev, iclass 5, count 0 2006.257.05:32:51.32#ibcon#first serial, iclass 5, count 0 2006.257.05:32:51.32#ibcon#enter sib2, iclass 5, count 0 2006.257.05:32:51.32#ibcon#flushed, iclass 5, count 0 2006.257.05:32:51.32#ibcon#about to write, iclass 5, count 0 2006.257.05:32:51.32#ibcon#wrote, iclass 5, count 0 2006.257.05:32:51.32#ibcon#about to read 3, iclass 5, count 0 2006.257.05:32:51.34#ibcon#read 3, iclass 5, count 0 2006.257.05:32:51.34#ibcon#about to read 4, iclass 5, count 0 2006.257.05:32:51.34#ibcon#read 4, iclass 5, count 0 2006.257.05:32:51.34#ibcon#about to read 5, iclass 5, count 0 2006.257.05:32:51.34#ibcon#read 5, iclass 5, count 0 2006.257.05:32:51.34#ibcon#about to read 6, iclass 5, count 0 2006.257.05:32:51.34#ibcon#read 6, iclass 5, count 0 2006.257.05:32:51.34#ibcon#end of sib2, iclass 5, count 0 2006.257.05:32:51.34#ibcon#*mode == 0, iclass 5, count 0 2006.257.05:32:51.34#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.05:32:51.34#ibcon#[27=USB\r\n] 2006.257.05:32:51.34#ibcon#*before write, iclass 5, count 0 2006.257.05:32:51.34#ibcon#enter sib2, iclass 5, count 0 2006.257.05:32:51.34#ibcon#flushed, iclass 5, count 0 2006.257.05:32:51.34#ibcon#about to write, iclass 5, count 0 2006.257.05:32:51.34#ibcon#wrote, iclass 5, count 0 2006.257.05:32:51.34#ibcon#about to read 3, iclass 5, count 0 2006.257.05:32:51.37#ibcon#read 3, iclass 5, count 0 2006.257.05:32:51.37#ibcon#about to read 4, iclass 5, count 0 2006.257.05:32:51.37#ibcon#read 4, iclass 5, count 0 2006.257.05:32:51.37#ibcon#about to read 5, iclass 5, count 0 2006.257.05:32:51.37#ibcon#read 5, iclass 5, count 0 2006.257.05:32:51.37#ibcon#about to read 6, iclass 5, count 0 2006.257.05:32:51.37#ibcon#read 6, iclass 5, count 0 2006.257.05:32:51.37#ibcon#end of sib2, iclass 5, count 0 2006.257.05:32:51.37#ibcon#*after write, iclass 5, count 0 2006.257.05:32:51.37#ibcon#*before return 0, iclass 5, count 0 2006.257.05:32:51.37#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:51.37#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:32:51.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.05:32:51.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.05:32:51.37$vck44/vblo=8,744.99 2006.257.05:32:51.37#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.05:32:51.37#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.05:32:51.37#ibcon#ireg 17 cls_cnt 0 2006.257.05:32:51.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:51.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:51.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:51.37#ibcon#enter wrdev, iclass 7, count 0 2006.257.05:32:51.37#ibcon#first serial, iclass 7, count 0 2006.257.05:32:51.37#ibcon#enter sib2, iclass 7, count 0 2006.257.05:32:51.37#ibcon#flushed, iclass 7, count 0 2006.257.05:32:51.37#ibcon#about to write, iclass 7, count 0 2006.257.05:32:51.37#ibcon#wrote, iclass 7, count 0 2006.257.05:32:51.37#ibcon#about to read 3, iclass 7, count 0 2006.257.05:32:51.39#ibcon#read 3, iclass 7, count 0 2006.257.05:32:51.39#ibcon#about to read 4, iclass 7, count 0 2006.257.05:32:51.39#ibcon#read 4, iclass 7, count 0 2006.257.05:32:51.39#ibcon#about to read 5, iclass 7, count 0 2006.257.05:32:51.39#ibcon#read 5, iclass 7, count 0 2006.257.05:32:51.39#ibcon#about to read 6, iclass 7, count 0 2006.257.05:32:51.39#ibcon#read 6, iclass 7, count 0 2006.257.05:32:51.39#ibcon#end of sib2, iclass 7, count 0 2006.257.05:32:51.39#ibcon#*mode == 0, iclass 7, count 0 2006.257.05:32:51.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.05:32:51.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:32:51.39#ibcon#*before write, iclass 7, count 0 2006.257.05:32:51.39#ibcon#enter sib2, iclass 7, count 0 2006.257.05:32:51.39#ibcon#flushed, iclass 7, count 0 2006.257.05:32:51.39#ibcon#about to write, iclass 7, count 0 2006.257.05:32:51.39#ibcon#wrote, iclass 7, count 0 2006.257.05:32:51.39#ibcon#about to read 3, iclass 7, count 0 2006.257.05:32:51.43#ibcon#read 3, iclass 7, count 0 2006.257.05:32:51.43#ibcon#about to read 4, iclass 7, count 0 2006.257.05:32:51.43#ibcon#read 4, iclass 7, count 0 2006.257.05:32:51.43#ibcon#about to read 5, iclass 7, count 0 2006.257.05:32:51.43#ibcon#read 5, iclass 7, count 0 2006.257.05:32:51.43#ibcon#about to read 6, iclass 7, count 0 2006.257.05:32:51.43#ibcon#read 6, iclass 7, count 0 2006.257.05:32:51.43#ibcon#end of sib2, iclass 7, count 0 2006.257.05:32:51.43#ibcon#*after write, iclass 7, count 0 2006.257.05:32:51.43#ibcon#*before return 0, iclass 7, count 0 2006.257.05:32:51.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:51.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:32:51.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.05:32:51.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.05:32:51.43$vck44/vb=8,4 2006.257.05:32:51.43#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.05:32:51.43#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.05:32:51.43#ibcon#ireg 11 cls_cnt 2 2006.257.05:32:51.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:51.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:51.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:51.49#ibcon#enter wrdev, iclass 11, count 2 2006.257.05:32:51.49#ibcon#first serial, iclass 11, count 2 2006.257.05:32:51.49#ibcon#enter sib2, iclass 11, count 2 2006.257.05:32:51.49#ibcon#flushed, iclass 11, count 2 2006.257.05:32:51.49#ibcon#about to write, iclass 11, count 2 2006.257.05:32:51.49#ibcon#wrote, iclass 11, count 2 2006.257.05:32:51.49#ibcon#about to read 3, iclass 11, count 2 2006.257.05:32:51.51#ibcon#read 3, iclass 11, count 2 2006.257.05:32:51.51#ibcon#about to read 4, iclass 11, count 2 2006.257.05:32:51.51#ibcon#read 4, iclass 11, count 2 2006.257.05:32:51.51#ibcon#about to read 5, iclass 11, count 2 2006.257.05:32:51.51#ibcon#read 5, iclass 11, count 2 2006.257.05:32:51.51#ibcon#about to read 6, iclass 11, count 2 2006.257.05:32:51.51#ibcon#read 6, iclass 11, count 2 2006.257.05:32:51.51#ibcon#end of sib2, iclass 11, count 2 2006.257.05:32:51.51#ibcon#*mode == 0, iclass 11, count 2 2006.257.05:32:51.51#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.05:32:51.51#ibcon#[27=AT08-04\r\n] 2006.257.05:32:51.51#ibcon#*before write, iclass 11, count 2 2006.257.05:32:51.51#ibcon#enter sib2, iclass 11, count 2 2006.257.05:32:51.51#ibcon#flushed, iclass 11, count 2 2006.257.05:32:51.51#ibcon#about to write, iclass 11, count 2 2006.257.05:32:51.51#ibcon#wrote, iclass 11, count 2 2006.257.05:32:51.51#ibcon#about to read 3, iclass 11, count 2 2006.257.05:32:51.54#ibcon#read 3, iclass 11, count 2 2006.257.05:32:51.54#ibcon#about to read 4, iclass 11, count 2 2006.257.05:32:51.54#ibcon#read 4, iclass 11, count 2 2006.257.05:32:51.54#ibcon#about to read 5, iclass 11, count 2 2006.257.05:32:51.54#ibcon#read 5, iclass 11, count 2 2006.257.05:32:51.54#ibcon#about to read 6, iclass 11, count 2 2006.257.05:32:51.54#ibcon#read 6, iclass 11, count 2 2006.257.05:32:51.54#ibcon#end of sib2, iclass 11, count 2 2006.257.05:32:51.54#ibcon#*after write, iclass 11, count 2 2006.257.05:32:51.54#ibcon#*before return 0, iclass 11, count 2 2006.257.05:32:51.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:51.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:32:51.54#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.05:32:51.54#ibcon#ireg 7 cls_cnt 0 2006.257.05:32:51.54#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:51.66#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:51.66#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:51.66#ibcon#enter wrdev, iclass 11, count 0 2006.257.05:32:51.66#ibcon#first serial, iclass 11, count 0 2006.257.05:32:51.66#ibcon#enter sib2, iclass 11, count 0 2006.257.05:32:51.66#ibcon#flushed, iclass 11, count 0 2006.257.05:32:51.66#ibcon#about to write, iclass 11, count 0 2006.257.05:32:51.66#ibcon#wrote, iclass 11, count 0 2006.257.05:32:51.66#ibcon#about to read 3, iclass 11, count 0 2006.257.05:32:51.68#ibcon#read 3, iclass 11, count 0 2006.257.05:32:51.68#ibcon#about to read 4, iclass 11, count 0 2006.257.05:32:51.68#ibcon#read 4, iclass 11, count 0 2006.257.05:32:51.68#ibcon#about to read 5, iclass 11, count 0 2006.257.05:32:51.68#ibcon#read 5, iclass 11, count 0 2006.257.05:32:51.68#ibcon#about to read 6, iclass 11, count 0 2006.257.05:32:51.68#ibcon#read 6, iclass 11, count 0 2006.257.05:32:51.68#ibcon#end of sib2, iclass 11, count 0 2006.257.05:32:51.68#ibcon#*mode == 0, iclass 11, count 0 2006.257.05:32:51.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.05:32:51.68#ibcon#[27=USB\r\n] 2006.257.05:32:51.68#ibcon#*before write, iclass 11, count 0 2006.257.05:32:51.68#ibcon#enter sib2, iclass 11, count 0 2006.257.05:32:51.68#ibcon#flushed, iclass 11, count 0 2006.257.05:32:51.68#ibcon#about to write, iclass 11, count 0 2006.257.05:32:51.68#ibcon#wrote, iclass 11, count 0 2006.257.05:32:51.68#ibcon#about to read 3, iclass 11, count 0 2006.257.05:32:51.71#ibcon#read 3, iclass 11, count 0 2006.257.05:32:51.71#ibcon#about to read 4, iclass 11, count 0 2006.257.05:32:51.71#ibcon#read 4, iclass 11, count 0 2006.257.05:32:51.71#ibcon#about to read 5, iclass 11, count 0 2006.257.05:32:51.71#ibcon#read 5, iclass 11, count 0 2006.257.05:32:51.71#ibcon#about to read 6, iclass 11, count 0 2006.257.05:32:51.71#ibcon#read 6, iclass 11, count 0 2006.257.05:32:51.71#ibcon#end of sib2, iclass 11, count 0 2006.257.05:32:51.71#ibcon#*after write, iclass 11, count 0 2006.257.05:32:51.71#ibcon#*before return 0, iclass 11, count 0 2006.257.05:32:51.71#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:51.71#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:32:51.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.05:32:51.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.05:32:51.71$vck44/vabw=wide 2006.257.05:32:51.71#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.05:32:51.71#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.05:32:51.71#ibcon#ireg 8 cls_cnt 0 2006.257.05:32:51.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:51.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:51.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:51.71#ibcon#enter wrdev, iclass 13, count 0 2006.257.05:32:51.71#ibcon#first serial, iclass 13, count 0 2006.257.05:32:51.71#ibcon#enter sib2, iclass 13, count 0 2006.257.05:32:51.71#ibcon#flushed, iclass 13, count 0 2006.257.05:32:51.71#ibcon#about to write, iclass 13, count 0 2006.257.05:32:51.71#ibcon#wrote, iclass 13, count 0 2006.257.05:32:51.71#ibcon#about to read 3, iclass 13, count 0 2006.257.05:32:51.73#ibcon#read 3, iclass 13, count 0 2006.257.05:32:51.73#ibcon#about to read 4, iclass 13, count 0 2006.257.05:32:51.73#ibcon#read 4, iclass 13, count 0 2006.257.05:32:51.73#ibcon#about to read 5, iclass 13, count 0 2006.257.05:32:51.73#ibcon#read 5, iclass 13, count 0 2006.257.05:32:51.73#ibcon#about to read 6, iclass 13, count 0 2006.257.05:32:51.73#ibcon#read 6, iclass 13, count 0 2006.257.05:32:51.73#ibcon#end of sib2, iclass 13, count 0 2006.257.05:32:51.73#ibcon#*mode == 0, iclass 13, count 0 2006.257.05:32:51.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.05:32:51.73#ibcon#[25=BW32\r\n] 2006.257.05:32:51.73#ibcon#*before write, iclass 13, count 0 2006.257.05:32:51.73#ibcon#enter sib2, iclass 13, count 0 2006.257.05:32:51.73#ibcon#flushed, iclass 13, count 0 2006.257.05:32:51.73#ibcon#about to write, iclass 13, count 0 2006.257.05:32:51.73#ibcon#wrote, iclass 13, count 0 2006.257.05:32:51.73#ibcon#about to read 3, iclass 13, count 0 2006.257.05:32:51.76#ibcon#read 3, iclass 13, count 0 2006.257.05:32:51.76#ibcon#about to read 4, iclass 13, count 0 2006.257.05:32:51.76#ibcon#read 4, iclass 13, count 0 2006.257.05:32:51.76#ibcon#about to read 5, iclass 13, count 0 2006.257.05:32:51.76#ibcon#read 5, iclass 13, count 0 2006.257.05:32:51.76#ibcon#about to read 6, iclass 13, count 0 2006.257.05:32:51.76#ibcon#read 6, iclass 13, count 0 2006.257.05:32:51.76#ibcon#end of sib2, iclass 13, count 0 2006.257.05:32:51.76#ibcon#*after write, iclass 13, count 0 2006.257.05:32:51.76#ibcon#*before return 0, iclass 13, count 0 2006.257.05:32:51.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:51.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:32:51.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.05:32:51.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.05:32:51.76$vck44/vbbw=wide 2006.257.05:32:51.76#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.05:32:51.76#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.05:32:51.76#ibcon#ireg 8 cls_cnt 0 2006.257.05:32:51.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:32:51.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:32:51.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:32:51.83#ibcon#enter wrdev, iclass 15, count 0 2006.257.05:32:51.83#ibcon#first serial, iclass 15, count 0 2006.257.05:32:51.83#ibcon#enter sib2, iclass 15, count 0 2006.257.05:32:51.83#ibcon#flushed, iclass 15, count 0 2006.257.05:32:51.83#ibcon#about to write, iclass 15, count 0 2006.257.05:32:51.83#ibcon#wrote, iclass 15, count 0 2006.257.05:32:51.83#ibcon#about to read 3, iclass 15, count 0 2006.257.05:32:51.85#ibcon#read 3, iclass 15, count 0 2006.257.05:32:51.85#ibcon#about to read 4, iclass 15, count 0 2006.257.05:32:51.85#ibcon#read 4, iclass 15, count 0 2006.257.05:32:51.85#ibcon#about to read 5, iclass 15, count 0 2006.257.05:32:51.85#ibcon#read 5, iclass 15, count 0 2006.257.05:32:51.85#ibcon#about to read 6, iclass 15, count 0 2006.257.05:32:51.85#ibcon#read 6, iclass 15, count 0 2006.257.05:32:51.85#ibcon#end of sib2, iclass 15, count 0 2006.257.05:32:51.85#ibcon#*mode == 0, iclass 15, count 0 2006.257.05:32:51.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.05:32:51.85#ibcon#[27=BW32\r\n] 2006.257.05:32:51.85#ibcon#*before write, iclass 15, count 0 2006.257.05:32:51.85#ibcon#enter sib2, iclass 15, count 0 2006.257.05:32:51.85#ibcon#flushed, iclass 15, count 0 2006.257.05:32:51.85#ibcon#about to write, iclass 15, count 0 2006.257.05:32:51.85#ibcon#wrote, iclass 15, count 0 2006.257.05:32:51.85#ibcon#about to read 3, iclass 15, count 0 2006.257.05:32:51.88#ibcon#read 3, iclass 15, count 0 2006.257.05:32:51.88#ibcon#about to read 4, iclass 15, count 0 2006.257.05:32:51.88#ibcon#read 4, iclass 15, count 0 2006.257.05:32:51.88#ibcon#about to read 5, iclass 15, count 0 2006.257.05:32:51.88#ibcon#read 5, iclass 15, count 0 2006.257.05:32:51.88#ibcon#about to read 6, iclass 15, count 0 2006.257.05:32:51.88#ibcon#read 6, iclass 15, count 0 2006.257.05:32:51.88#ibcon#end of sib2, iclass 15, count 0 2006.257.05:32:51.88#ibcon#*after write, iclass 15, count 0 2006.257.05:32:51.88#ibcon#*before return 0, iclass 15, count 0 2006.257.05:32:51.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:32:51.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:32:51.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.05:32:51.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.05:32:51.88$setupk4/ifdk4 2006.257.05:32:51.88$ifdk4/lo= 2006.257.05:32:51.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:32:51.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:32:51.88$ifdk4/patch= 2006.257.05:32:51.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:32:51.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:32:51.88$setupk4/!*+20s 2006.257.05:32:54.00#abcon#<5=/15 1.3 3.1 20.02 901012.2\r\n> 2006.257.05:32:54.02#abcon#{5=INTERFACE CLEAR} 2006.257.05:32:54.08#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:33:04.17#abcon#<5=/15 1.4 3.4 20.02 901012.2\r\n> 2006.257.05:33:04.19#abcon#{5=INTERFACE CLEAR} 2006.257.05:33:04.25#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:33:06.39$setupk4/"tpicd 2006.257.05:33:06.39$setupk4/echo=off 2006.257.05:33:06.39$setupk4/xlog=off 2006.257.05:33:06.39:!2006.257.05:35:51 2006.257.05:33:09.14#trakl#Source acquired 2006.257.05:33:11.14#flagr#flagr/antenna,acquired 2006.257.05:35:51.00:preob 2006.257.05:35:51.14/onsource/TRACKING 2006.257.05:35:51.14:!2006.257.05:36:01 2006.257.05:36:01.00:"tape 2006.257.05:36:01.00:"st=record 2006.257.05:36:01.00:data_valid=on 2006.257.05:36:01.00:midob 2006.257.05:36:02.14/onsource/TRACKING 2006.257.05:36:02.14/wx/20.02,1012.2,89 2006.257.05:36:02.28/cable/+6.4816E-03 2006.257.05:36:03.37/va/01,08,usb,yes,31,33 2006.257.05:36:03.37/va/02,07,usb,yes,34,34 2006.257.05:36:03.37/va/03,08,usb,yes,30,32 2006.257.05:36:03.37/va/04,07,usb,yes,35,36 2006.257.05:36:03.37/va/05,04,usb,yes,31,32 2006.257.05:36:03.37/va/06,04,usb,yes,35,34 2006.257.05:36:03.37/va/07,04,usb,yes,36,36 2006.257.05:36:03.37/va/08,04,usb,yes,30,36 2006.257.05:36:03.60/valo/01,524.99,yes,locked 2006.257.05:36:03.60/valo/02,534.99,yes,locked 2006.257.05:36:03.60/valo/03,564.99,yes,locked 2006.257.05:36:03.60/valo/04,624.99,yes,locked 2006.257.05:36:03.60/valo/05,734.99,yes,locked 2006.257.05:36:03.60/valo/06,814.99,yes,locked 2006.257.05:36:03.60/valo/07,864.99,yes,locked 2006.257.05:36:03.60/valo/08,884.99,yes,locked 2006.257.05:36:04.69/vb/01,04,usb,yes,30,28 2006.257.05:36:04.69/vb/02,05,usb,yes,28,28 2006.257.05:36:04.69/vb/03,04,usb,yes,29,32 2006.257.05:36:04.69/vb/04,05,usb,yes,29,28 2006.257.05:36:04.69/vb/05,04,usb,yes,26,28 2006.257.05:36:04.69/vb/06,04,usb,yes,30,27 2006.257.05:36:04.69/vb/07,04,usb,yes,30,30 2006.257.05:36:04.69/vb/08,04,usb,yes,27,31 2006.257.05:36:04.93/vblo/01,629.99,yes,locked 2006.257.05:36:04.93/vblo/02,634.99,yes,locked 2006.257.05:36:04.93/vblo/03,649.99,yes,locked 2006.257.05:36:04.93/vblo/04,679.99,yes,locked 2006.257.05:36:04.93/vblo/05,709.99,yes,locked 2006.257.05:36:04.93/vblo/06,719.99,yes,locked 2006.257.05:36:04.93/vblo/07,734.99,yes,locked 2006.257.05:36:04.93/vblo/08,744.99,yes,locked 2006.257.05:36:05.08/vabw/8 2006.257.05:36:05.23/vbbw/8 2006.257.05:36:05.32/xfe/off,on,16.7 2006.257.05:36:05.69/ifatt/23,28,28,28 2006.257.05:36:06.07/fmout-gps/S +4.54E-07 2006.257.05:36:06.11:!2006.257.05:36:51 2006.257.05:36:51.01:data_valid=off 2006.257.05:36:51.02:"et 2006.257.05:36:51.02:!+3s 2006.257.05:36:54.04:"tape 2006.257.05:36:54.04:postob 2006.257.05:36:54.12/cable/+6.4798E-03 2006.257.05:36:54.12/wx/20.01,1012.2,90 2006.257.05:36:54.18/fmout-gps/S +4.55E-07 2006.257.05:36:54.18:scan_name=257-0541,jd0609,220 2006.257.05:36:54.18:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.257.05:36:55.14#flagr#flagr/antenna,new-source 2006.257.05:36:55.15:checkk5 2006.257.05:36:55.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:36:55.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:36:56.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:36:56.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:36:57.17/chk_obsdata//k5ts1/T2570536??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.05:36:57.56/chk_obsdata//k5ts2/T2570536??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.05:36:57.98/chk_obsdata//k5ts3/T2570536??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.05:36:58.39/chk_obsdata//k5ts4/T2570536??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.05:36:59.10/k5log//k5ts1_log_newline 2006.257.05:36:59.82/k5log//k5ts2_log_newline 2006.257.05:37:00.58/k5log//k5ts3_log_newline 2006.257.05:37:01.30/k5log//k5ts4_log_newline 2006.257.05:37:01.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:37:01.32:setupk4=1 2006.257.05:37:01.32$setupk4/echo=on 2006.257.05:37:01.32$setupk4/pcalon 2006.257.05:37:01.32$pcalon/"no phase cal control is implemented here 2006.257.05:37:01.32$setupk4/"tpicd=stop 2006.257.05:37:01.32$setupk4/"rec=synch_on 2006.257.05:37:01.32$setupk4/"rec_mode=128 2006.257.05:37:01.32$setupk4/!* 2006.257.05:37:01.32$setupk4/recpk4 2006.257.05:37:01.32$recpk4/recpatch= 2006.257.05:37:01.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:37:01.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:37:01.32$setupk4/vck44 2006.257.05:37:01.32$vck44/valo=1,524.99 2006.257.05:37:01.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.05:37:01.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.05:37:01.32#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:01.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:01.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:01.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:01.32#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:37:01.32#ibcon#first serial, iclass 12, count 0 2006.257.05:37:01.32#ibcon#enter sib2, iclass 12, count 0 2006.257.05:37:01.32#ibcon#flushed, iclass 12, count 0 2006.257.05:37:01.32#ibcon#about to write, iclass 12, count 0 2006.257.05:37:01.32#ibcon#wrote, iclass 12, count 0 2006.257.05:37:01.32#ibcon#about to read 3, iclass 12, count 0 2006.257.05:37:01.34#ibcon#read 3, iclass 12, count 0 2006.257.05:37:01.34#ibcon#about to read 4, iclass 12, count 0 2006.257.05:37:01.34#ibcon#read 4, iclass 12, count 0 2006.257.05:37:01.34#ibcon#about to read 5, iclass 12, count 0 2006.257.05:37:01.34#ibcon#read 5, iclass 12, count 0 2006.257.05:37:01.34#ibcon#about to read 6, iclass 12, count 0 2006.257.05:37:01.34#ibcon#read 6, iclass 12, count 0 2006.257.05:37:01.34#ibcon#end of sib2, iclass 12, count 0 2006.257.05:37:01.34#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:37:01.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:37:01.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:37:01.34#ibcon#*before write, iclass 12, count 0 2006.257.05:37:01.34#ibcon#enter sib2, iclass 12, count 0 2006.257.05:37:01.34#ibcon#flushed, iclass 12, count 0 2006.257.05:37:01.34#ibcon#about to write, iclass 12, count 0 2006.257.05:37:01.34#ibcon#wrote, iclass 12, count 0 2006.257.05:37:01.34#ibcon#about to read 3, iclass 12, count 0 2006.257.05:37:01.39#ibcon#read 3, iclass 12, count 0 2006.257.05:37:01.39#ibcon#about to read 4, iclass 12, count 0 2006.257.05:37:01.39#ibcon#read 4, iclass 12, count 0 2006.257.05:37:01.39#ibcon#about to read 5, iclass 12, count 0 2006.257.05:37:01.39#ibcon#read 5, iclass 12, count 0 2006.257.05:37:01.39#ibcon#about to read 6, iclass 12, count 0 2006.257.05:37:01.39#ibcon#read 6, iclass 12, count 0 2006.257.05:37:01.39#ibcon#end of sib2, iclass 12, count 0 2006.257.05:37:01.39#ibcon#*after write, iclass 12, count 0 2006.257.05:37:01.39#ibcon#*before return 0, iclass 12, count 0 2006.257.05:37:01.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:01.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:01.39#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:37:01.39#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:37:01.39$vck44/va=1,8 2006.257.05:37:01.39#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.05:37:01.39#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.05:37:01.39#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:01.39#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:01.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:01.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:01.39#ibcon#enter wrdev, iclass 14, count 2 2006.257.05:37:01.39#ibcon#first serial, iclass 14, count 2 2006.257.05:37:01.39#ibcon#enter sib2, iclass 14, count 2 2006.257.05:37:01.39#ibcon#flushed, iclass 14, count 2 2006.257.05:37:01.39#ibcon#about to write, iclass 14, count 2 2006.257.05:37:01.39#ibcon#wrote, iclass 14, count 2 2006.257.05:37:01.39#ibcon#about to read 3, iclass 14, count 2 2006.257.05:37:01.41#ibcon#read 3, iclass 14, count 2 2006.257.05:37:01.41#ibcon#about to read 4, iclass 14, count 2 2006.257.05:37:01.41#ibcon#read 4, iclass 14, count 2 2006.257.05:37:01.41#ibcon#about to read 5, iclass 14, count 2 2006.257.05:37:01.41#ibcon#read 5, iclass 14, count 2 2006.257.05:37:01.41#ibcon#about to read 6, iclass 14, count 2 2006.257.05:37:01.41#ibcon#read 6, iclass 14, count 2 2006.257.05:37:01.41#ibcon#end of sib2, iclass 14, count 2 2006.257.05:37:01.41#ibcon#*mode == 0, iclass 14, count 2 2006.257.05:37:01.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.05:37:01.41#ibcon#[25=AT01-08\r\n] 2006.257.05:37:01.41#ibcon#*before write, iclass 14, count 2 2006.257.05:37:01.41#ibcon#enter sib2, iclass 14, count 2 2006.257.05:37:01.41#ibcon#flushed, iclass 14, count 2 2006.257.05:37:01.41#ibcon#about to write, iclass 14, count 2 2006.257.05:37:01.41#ibcon#wrote, iclass 14, count 2 2006.257.05:37:01.41#ibcon#about to read 3, iclass 14, count 2 2006.257.05:37:01.44#ibcon#read 3, iclass 14, count 2 2006.257.05:37:01.44#ibcon#about to read 4, iclass 14, count 2 2006.257.05:37:01.44#ibcon#read 4, iclass 14, count 2 2006.257.05:37:01.44#ibcon#about to read 5, iclass 14, count 2 2006.257.05:37:01.44#ibcon#read 5, iclass 14, count 2 2006.257.05:37:01.44#ibcon#about to read 6, iclass 14, count 2 2006.257.05:37:01.44#ibcon#read 6, iclass 14, count 2 2006.257.05:37:01.44#ibcon#end of sib2, iclass 14, count 2 2006.257.05:37:01.44#ibcon#*after write, iclass 14, count 2 2006.257.05:37:01.44#ibcon#*before return 0, iclass 14, count 2 2006.257.05:37:01.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:01.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:01.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.05:37:01.44#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:01.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:01.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:01.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:01.56#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:37:01.56#ibcon#first serial, iclass 14, count 0 2006.257.05:37:01.56#ibcon#enter sib2, iclass 14, count 0 2006.257.05:37:01.56#ibcon#flushed, iclass 14, count 0 2006.257.05:37:01.56#ibcon#about to write, iclass 14, count 0 2006.257.05:37:01.56#ibcon#wrote, iclass 14, count 0 2006.257.05:37:01.56#ibcon#about to read 3, iclass 14, count 0 2006.257.05:37:01.58#ibcon#read 3, iclass 14, count 0 2006.257.05:37:01.58#ibcon#about to read 4, iclass 14, count 0 2006.257.05:37:01.58#ibcon#read 4, iclass 14, count 0 2006.257.05:37:01.58#ibcon#about to read 5, iclass 14, count 0 2006.257.05:37:01.58#ibcon#read 5, iclass 14, count 0 2006.257.05:37:01.58#ibcon#about to read 6, iclass 14, count 0 2006.257.05:37:01.58#ibcon#read 6, iclass 14, count 0 2006.257.05:37:01.58#ibcon#end of sib2, iclass 14, count 0 2006.257.05:37:01.58#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:37:01.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:37:01.58#ibcon#[25=USB\r\n] 2006.257.05:37:01.58#ibcon#*before write, iclass 14, count 0 2006.257.05:37:01.58#ibcon#enter sib2, iclass 14, count 0 2006.257.05:37:01.58#ibcon#flushed, iclass 14, count 0 2006.257.05:37:01.58#ibcon#about to write, iclass 14, count 0 2006.257.05:37:01.58#ibcon#wrote, iclass 14, count 0 2006.257.05:37:01.58#ibcon#about to read 3, iclass 14, count 0 2006.257.05:37:01.61#ibcon#read 3, iclass 14, count 0 2006.257.05:37:01.61#ibcon#about to read 4, iclass 14, count 0 2006.257.05:37:01.61#ibcon#read 4, iclass 14, count 0 2006.257.05:37:01.61#ibcon#about to read 5, iclass 14, count 0 2006.257.05:37:01.61#ibcon#read 5, iclass 14, count 0 2006.257.05:37:01.61#ibcon#about to read 6, iclass 14, count 0 2006.257.05:37:01.61#ibcon#read 6, iclass 14, count 0 2006.257.05:37:01.61#ibcon#end of sib2, iclass 14, count 0 2006.257.05:37:01.61#ibcon#*after write, iclass 14, count 0 2006.257.05:37:01.61#ibcon#*before return 0, iclass 14, count 0 2006.257.05:37:01.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:01.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:01.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:37:01.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:37:01.61$vck44/valo=2,534.99 2006.257.05:37:01.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.05:37:01.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.05:37:01.61#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:01.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:01.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:01.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:01.61#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:37:01.61#ibcon#first serial, iclass 16, count 0 2006.257.05:37:01.61#ibcon#enter sib2, iclass 16, count 0 2006.257.05:37:01.61#ibcon#flushed, iclass 16, count 0 2006.257.05:37:01.61#ibcon#about to write, iclass 16, count 0 2006.257.05:37:01.61#ibcon#wrote, iclass 16, count 0 2006.257.05:37:01.61#ibcon#about to read 3, iclass 16, count 0 2006.257.05:37:01.63#ibcon#read 3, iclass 16, count 0 2006.257.05:37:01.63#ibcon#about to read 4, iclass 16, count 0 2006.257.05:37:01.63#ibcon#read 4, iclass 16, count 0 2006.257.05:37:01.63#ibcon#about to read 5, iclass 16, count 0 2006.257.05:37:01.63#ibcon#read 5, iclass 16, count 0 2006.257.05:37:01.63#ibcon#about to read 6, iclass 16, count 0 2006.257.05:37:01.63#ibcon#read 6, iclass 16, count 0 2006.257.05:37:01.63#ibcon#end of sib2, iclass 16, count 0 2006.257.05:37:01.63#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:37:01.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:37:01.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:37:01.63#ibcon#*before write, iclass 16, count 0 2006.257.05:37:01.63#ibcon#enter sib2, iclass 16, count 0 2006.257.05:37:01.63#ibcon#flushed, iclass 16, count 0 2006.257.05:37:01.63#ibcon#about to write, iclass 16, count 0 2006.257.05:37:01.63#ibcon#wrote, iclass 16, count 0 2006.257.05:37:01.63#ibcon#about to read 3, iclass 16, count 0 2006.257.05:37:01.67#ibcon#read 3, iclass 16, count 0 2006.257.05:37:01.67#ibcon#about to read 4, iclass 16, count 0 2006.257.05:37:01.67#ibcon#read 4, iclass 16, count 0 2006.257.05:37:01.67#ibcon#about to read 5, iclass 16, count 0 2006.257.05:37:01.67#ibcon#read 5, iclass 16, count 0 2006.257.05:37:01.67#ibcon#about to read 6, iclass 16, count 0 2006.257.05:37:01.67#ibcon#read 6, iclass 16, count 0 2006.257.05:37:01.67#ibcon#end of sib2, iclass 16, count 0 2006.257.05:37:01.67#ibcon#*after write, iclass 16, count 0 2006.257.05:37:01.67#ibcon#*before return 0, iclass 16, count 0 2006.257.05:37:01.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:01.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:01.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:37:01.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:37:01.67$vck44/va=2,7 2006.257.05:37:01.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.05:37:01.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.05:37:01.67#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:01.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:01.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:01.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:01.73#ibcon#enter wrdev, iclass 18, count 2 2006.257.05:37:01.73#ibcon#first serial, iclass 18, count 2 2006.257.05:37:01.73#ibcon#enter sib2, iclass 18, count 2 2006.257.05:37:01.73#ibcon#flushed, iclass 18, count 2 2006.257.05:37:01.73#ibcon#about to write, iclass 18, count 2 2006.257.05:37:01.73#ibcon#wrote, iclass 18, count 2 2006.257.05:37:01.73#ibcon#about to read 3, iclass 18, count 2 2006.257.05:37:01.75#ibcon#read 3, iclass 18, count 2 2006.257.05:37:01.75#ibcon#about to read 4, iclass 18, count 2 2006.257.05:37:01.75#ibcon#read 4, iclass 18, count 2 2006.257.05:37:01.75#ibcon#about to read 5, iclass 18, count 2 2006.257.05:37:01.75#ibcon#read 5, iclass 18, count 2 2006.257.05:37:01.75#ibcon#about to read 6, iclass 18, count 2 2006.257.05:37:01.75#ibcon#read 6, iclass 18, count 2 2006.257.05:37:01.75#ibcon#end of sib2, iclass 18, count 2 2006.257.05:37:01.75#ibcon#*mode == 0, iclass 18, count 2 2006.257.05:37:01.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.05:37:01.75#ibcon#[25=AT02-07\r\n] 2006.257.05:37:01.75#ibcon#*before write, iclass 18, count 2 2006.257.05:37:01.75#ibcon#enter sib2, iclass 18, count 2 2006.257.05:37:01.75#ibcon#flushed, iclass 18, count 2 2006.257.05:37:01.75#ibcon#about to write, iclass 18, count 2 2006.257.05:37:01.75#ibcon#wrote, iclass 18, count 2 2006.257.05:37:01.75#ibcon#about to read 3, iclass 18, count 2 2006.257.05:37:01.78#ibcon#read 3, iclass 18, count 2 2006.257.05:37:01.78#ibcon#about to read 4, iclass 18, count 2 2006.257.05:37:01.78#ibcon#read 4, iclass 18, count 2 2006.257.05:37:01.78#ibcon#about to read 5, iclass 18, count 2 2006.257.05:37:01.78#ibcon#read 5, iclass 18, count 2 2006.257.05:37:01.78#ibcon#about to read 6, iclass 18, count 2 2006.257.05:37:01.78#ibcon#read 6, iclass 18, count 2 2006.257.05:37:01.78#ibcon#end of sib2, iclass 18, count 2 2006.257.05:37:01.78#ibcon#*after write, iclass 18, count 2 2006.257.05:37:01.78#ibcon#*before return 0, iclass 18, count 2 2006.257.05:37:01.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:01.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:01.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.05:37:01.78#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:01.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:01.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:01.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:01.90#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:37:01.90#ibcon#first serial, iclass 18, count 0 2006.257.05:37:01.90#ibcon#enter sib2, iclass 18, count 0 2006.257.05:37:01.90#ibcon#flushed, iclass 18, count 0 2006.257.05:37:01.90#ibcon#about to write, iclass 18, count 0 2006.257.05:37:01.90#ibcon#wrote, iclass 18, count 0 2006.257.05:37:01.90#ibcon#about to read 3, iclass 18, count 0 2006.257.05:37:01.92#ibcon#read 3, iclass 18, count 0 2006.257.05:37:01.92#ibcon#about to read 4, iclass 18, count 0 2006.257.05:37:01.92#ibcon#read 4, iclass 18, count 0 2006.257.05:37:01.92#ibcon#about to read 5, iclass 18, count 0 2006.257.05:37:01.92#ibcon#read 5, iclass 18, count 0 2006.257.05:37:01.92#ibcon#about to read 6, iclass 18, count 0 2006.257.05:37:01.92#ibcon#read 6, iclass 18, count 0 2006.257.05:37:01.92#ibcon#end of sib2, iclass 18, count 0 2006.257.05:37:01.92#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:37:01.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:37:01.92#ibcon#[25=USB\r\n] 2006.257.05:37:01.92#ibcon#*before write, iclass 18, count 0 2006.257.05:37:01.92#ibcon#enter sib2, iclass 18, count 0 2006.257.05:37:01.92#ibcon#flushed, iclass 18, count 0 2006.257.05:37:01.92#ibcon#about to write, iclass 18, count 0 2006.257.05:37:01.92#ibcon#wrote, iclass 18, count 0 2006.257.05:37:01.92#ibcon#about to read 3, iclass 18, count 0 2006.257.05:37:01.95#ibcon#read 3, iclass 18, count 0 2006.257.05:37:01.95#ibcon#about to read 4, iclass 18, count 0 2006.257.05:37:01.95#ibcon#read 4, iclass 18, count 0 2006.257.05:37:01.95#ibcon#about to read 5, iclass 18, count 0 2006.257.05:37:01.95#ibcon#read 5, iclass 18, count 0 2006.257.05:37:01.95#ibcon#about to read 6, iclass 18, count 0 2006.257.05:37:01.95#ibcon#read 6, iclass 18, count 0 2006.257.05:37:01.95#ibcon#end of sib2, iclass 18, count 0 2006.257.05:37:01.95#ibcon#*after write, iclass 18, count 0 2006.257.05:37:01.95#ibcon#*before return 0, iclass 18, count 0 2006.257.05:37:01.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:01.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:01.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:37:01.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:37:01.95$vck44/valo=3,564.99 2006.257.05:37:01.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.05:37:01.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.05:37:01.95#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:01.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:01.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:01.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:01.95#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:37:01.95#ibcon#first serial, iclass 20, count 0 2006.257.05:37:01.95#ibcon#enter sib2, iclass 20, count 0 2006.257.05:37:01.95#ibcon#flushed, iclass 20, count 0 2006.257.05:37:01.95#ibcon#about to write, iclass 20, count 0 2006.257.05:37:01.95#ibcon#wrote, iclass 20, count 0 2006.257.05:37:01.95#ibcon#about to read 3, iclass 20, count 0 2006.257.05:37:01.97#ibcon#read 3, iclass 20, count 0 2006.257.05:37:01.97#ibcon#about to read 4, iclass 20, count 0 2006.257.05:37:01.97#ibcon#read 4, iclass 20, count 0 2006.257.05:37:01.97#ibcon#about to read 5, iclass 20, count 0 2006.257.05:37:01.97#ibcon#read 5, iclass 20, count 0 2006.257.05:37:01.97#ibcon#about to read 6, iclass 20, count 0 2006.257.05:37:01.97#ibcon#read 6, iclass 20, count 0 2006.257.05:37:01.97#ibcon#end of sib2, iclass 20, count 0 2006.257.05:37:01.97#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:37:01.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:37:01.97#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:37:01.97#ibcon#*before write, iclass 20, count 0 2006.257.05:37:01.97#ibcon#enter sib2, iclass 20, count 0 2006.257.05:37:01.97#ibcon#flushed, iclass 20, count 0 2006.257.05:37:01.97#ibcon#about to write, iclass 20, count 0 2006.257.05:37:01.97#ibcon#wrote, iclass 20, count 0 2006.257.05:37:01.97#ibcon#about to read 3, iclass 20, count 0 2006.257.05:37:02.01#ibcon#read 3, iclass 20, count 0 2006.257.05:37:02.01#ibcon#about to read 4, iclass 20, count 0 2006.257.05:37:02.01#ibcon#read 4, iclass 20, count 0 2006.257.05:37:02.01#ibcon#about to read 5, iclass 20, count 0 2006.257.05:37:02.01#ibcon#read 5, iclass 20, count 0 2006.257.05:37:02.01#ibcon#about to read 6, iclass 20, count 0 2006.257.05:37:02.01#ibcon#read 6, iclass 20, count 0 2006.257.05:37:02.01#ibcon#end of sib2, iclass 20, count 0 2006.257.05:37:02.01#ibcon#*after write, iclass 20, count 0 2006.257.05:37:02.01#ibcon#*before return 0, iclass 20, count 0 2006.257.05:37:02.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:02.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:02.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:37:02.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:37:02.01$vck44/va=3,8 2006.257.05:37:02.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.05:37:02.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.05:37:02.01#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:02.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:02.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:02.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:02.07#ibcon#enter wrdev, iclass 22, count 2 2006.257.05:37:02.07#ibcon#first serial, iclass 22, count 2 2006.257.05:37:02.07#ibcon#enter sib2, iclass 22, count 2 2006.257.05:37:02.07#ibcon#flushed, iclass 22, count 2 2006.257.05:37:02.07#ibcon#about to write, iclass 22, count 2 2006.257.05:37:02.07#ibcon#wrote, iclass 22, count 2 2006.257.05:37:02.07#ibcon#about to read 3, iclass 22, count 2 2006.257.05:37:02.09#ibcon#read 3, iclass 22, count 2 2006.257.05:37:02.09#ibcon#about to read 4, iclass 22, count 2 2006.257.05:37:02.09#ibcon#read 4, iclass 22, count 2 2006.257.05:37:02.09#ibcon#about to read 5, iclass 22, count 2 2006.257.05:37:02.09#ibcon#read 5, iclass 22, count 2 2006.257.05:37:02.09#ibcon#about to read 6, iclass 22, count 2 2006.257.05:37:02.09#ibcon#read 6, iclass 22, count 2 2006.257.05:37:02.09#ibcon#end of sib2, iclass 22, count 2 2006.257.05:37:02.09#ibcon#*mode == 0, iclass 22, count 2 2006.257.05:37:02.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.05:37:02.09#ibcon#[25=AT03-08\r\n] 2006.257.05:37:02.09#ibcon#*before write, iclass 22, count 2 2006.257.05:37:02.09#ibcon#enter sib2, iclass 22, count 2 2006.257.05:37:02.09#ibcon#flushed, iclass 22, count 2 2006.257.05:37:02.09#ibcon#about to write, iclass 22, count 2 2006.257.05:37:02.09#ibcon#wrote, iclass 22, count 2 2006.257.05:37:02.09#ibcon#about to read 3, iclass 22, count 2 2006.257.05:37:02.12#ibcon#read 3, iclass 22, count 2 2006.257.05:37:02.12#ibcon#about to read 4, iclass 22, count 2 2006.257.05:37:02.12#ibcon#read 4, iclass 22, count 2 2006.257.05:37:02.12#ibcon#about to read 5, iclass 22, count 2 2006.257.05:37:02.12#ibcon#read 5, iclass 22, count 2 2006.257.05:37:02.12#ibcon#about to read 6, iclass 22, count 2 2006.257.05:37:02.12#ibcon#read 6, iclass 22, count 2 2006.257.05:37:02.12#ibcon#end of sib2, iclass 22, count 2 2006.257.05:37:02.12#ibcon#*after write, iclass 22, count 2 2006.257.05:37:02.12#ibcon#*before return 0, iclass 22, count 2 2006.257.05:37:02.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:02.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:02.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.05:37:02.12#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:02.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:02.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:02.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:02.24#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:37:02.24#ibcon#first serial, iclass 22, count 0 2006.257.05:37:02.24#ibcon#enter sib2, iclass 22, count 0 2006.257.05:37:02.24#ibcon#flushed, iclass 22, count 0 2006.257.05:37:02.24#ibcon#about to write, iclass 22, count 0 2006.257.05:37:02.24#ibcon#wrote, iclass 22, count 0 2006.257.05:37:02.24#ibcon#about to read 3, iclass 22, count 0 2006.257.05:37:02.26#ibcon#read 3, iclass 22, count 0 2006.257.05:37:02.26#ibcon#about to read 4, iclass 22, count 0 2006.257.05:37:02.26#ibcon#read 4, iclass 22, count 0 2006.257.05:37:02.26#ibcon#about to read 5, iclass 22, count 0 2006.257.05:37:02.26#ibcon#read 5, iclass 22, count 0 2006.257.05:37:02.26#ibcon#about to read 6, iclass 22, count 0 2006.257.05:37:02.26#ibcon#read 6, iclass 22, count 0 2006.257.05:37:02.26#ibcon#end of sib2, iclass 22, count 0 2006.257.05:37:02.26#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:37:02.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:37:02.26#ibcon#[25=USB\r\n] 2006.257.05:37:02.26#ibcon#*before write, iclass 22, count 0 2006.257.05:37:02.26#ibcon#enter sib2, iclass 22, count 0 2006.257.05:37:02.26#ibcon#flushed, iclass 22, count 0 2006.257.05:37:02.26#ibcon#about to write, iclass 22, count 0 2006.257.05:37:02.26#ibcon#wrote, iclass 22, count 0 2006.257.05:37:02.26#ibcon#about to read 3, iclass 22, count 0 2006.257.05:37:02.29#ibcon#read 3, iclass 22, count 0 2006.257.05:37:02.29#ibcon#about to read 4, iclass 22, count 0 2006.257.05:37:02.29#ibcon#read 4, iclass 22, count 0 2006.257.05:37:02.29#ibcon#about to read 5, iclass 22, count 0 2006.257.05:37:02.29#ibcon#read 5, iclass 22, count 0 2006.257.05:37:02.29#ibcon#about to read 6, iclass 22, count 0 2006.257.05:37:02.29#ibcon#read 6, iclass 22, count 0 2006.257.05:37:02.29#ibcon#end of sib2, iclass 22, count 0 2006.257.05:37:02.29#ibcon#*after write, iclass 22, count 0 2006.257.05:37:02.29#ibcon#*before return 0, iclass 22, count 0 2006.257.05:37:02.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:02.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:02.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:37:02.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:37:02.29$vck44/valo=4,624.99 2006.257.05:37:02.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.05:37:02.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.05:37:02.29#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:02.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:02.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:02.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:02.29#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:37:02.29#ibcon#first serial, iclass 24, count 0 2006.257.05:37:02.29#ibcon#enter sib2, iclass 24, count 0 2006.257.05:37:02.29#ibcon#flushed, iclass 24, count 0 2006.257.05:37:02.29#ibcon#about to write, iclass 24, count 0 2006.257.05:37:02.29#ibcon#wrote, iclass 24, count 0 2006.257.05:37:02.29#ibcon#about to read 3, iclass 24, count 0 2006.257.05:37:02.31#ibcon#read 3, iclass 24, count 0 2006.257.05:37:02.31#ibcon#about to read 4, iclass 24, count 0 2006.257.05:37:02.31#ibcon#read 4, iclass 24, count 0 2006.257.05:37:02.31#ibcon#about to read 5, iclass 24, count 0 2006.257.05:37:02.31#ibcon#read 5, iclass 24, count 0 2006.257.05:37:02.31#ibcon#about to read 6, iclass 24, count 0 2006.257.05:37:02.31#ibcon#read 6, iclass 24, count 0 2006.257.05:37:02.31#ibcon#end of sib2, iclass 24, count 0 2006.257.05:37:02.31#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:37:02.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:37:02.31#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:37:02.31#ibcon#*before write, iclass 24, count 0 2006.257.05:37:02.31#ibcon#enter sib2, iclass 24, count 0 2006.257.05:37:02.31#ibcon#flushed, iclass 24, count 0 2006.257.05:37:02.31#ibcon#about to write, iclass 24, count 0 2006.257.05:37:02.31#ibcon#wrote, iclass 24, count 0 2006.257.05:37:02.31#ibcon#about to read 3, iclass 24, count 0 2006.257.05:37:02.35#ibcon#read 3, iclass 24, count 0 2006.257.05:37:02.35#ibcon#about to read 4, iclass 24, count 0 2006.257.05:37:02.35#ibcon#read 4, iclass 24, count 0 2006.257.05:37:02.35#ibcon#about to read 5, iclass 24, count 0 2006.257.05:37:02.35#ibcon#read 5, iclass 24, count 0 2006.257.05:37:02.35#ibcon#about to read 6, iclass 24, count 0 2006.257.05:37:02.35#ibcon#read 6, iclass 24, count 0 2006.257.05:37:02.35#ibcon#end of sib2, iclass 24, count 0 2006.257.05:37:02.35#ibcon#*after write, iclass 24, count 0 2006.257.05:37:02.35#ibcon#*before return 0, iclass 24, count 0 2006.257.05:37:02.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:02.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:02.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:37:02.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:37:02.35$vck44/va=4,7 2006.257.05:37:02.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.05:37:02.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.05:37:02.35#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:02.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:02.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:02.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:02.41#ibcon#enter wrdev, iclass 26, count 2 2006.257.05:37:02.41#ibcon#first serial, iclass 26, count 2 2006.257.05:37:02.41#ibcon#enter sib2, iclass 26, count 2 2006.257.05:37:02.41#ibcon#flushed, iclass 26, count 2 2006.257.05:37:02.41#ibcon#about to write, iclass 26, count 2 2006.257.05:37:02.41#ibcon#wrote, iclass 26, count 2 2006.257.05:37:02.41#ibcon#about to read 3, iclass 26, count 2 2006.257.05:37:02.43#ibcon#read 3, iclass 26, count 2 2006.257.05:37:02.43#ibcon#about to read 4, iclass 26, count 2 2006.257.05:37:02.43#ibcon#read 4, iclass 26, count 2 2006.257.05:37:02.43#ibcon#about to read 5, iclass 26, count 2 2006.257.05:37:02.43#ibcon#read 5, iclass 26, count 2 2006.257.05:37:02.43#ibcon#about to read 6, iclass 26, count 2 2006.257.05:37:02.43#ibcon#read 6, iclass 26, count 2 2006.257.05:37:02.43#ibcon#end of sib2, iclass 26, count 2 2006.257.05:37:02.43#ibcon#*mode == 0, iclass 26, count 2 2006.257.05:37:02.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.05:37:02.43#ibcon#[25=AT04-07\r\n] 2006.257.05:37:02.43#ibcon#*before write, iclass 26, count 2 2006.257.05:37:02.43#ibcon#enter sib2, iclass 26, count 2 2006.257.05:37:02.43#ibcon#flushed, iclass 26, count 2 2006.257.05:37:02.43#ibcon#about to write, iclass 26, count 2 2006.257.05:37:02.43#ibcon#wrote, iclass 26, count 2 2006.257.05:37:02.43#ibcon#about to read 3, iclass 26, count 2 2006.257.05:37:02.46#ibcon#read 3, iclass 26, count 2 2006.257.05:37:02.46#ibcon#about to read 4, iclass 26, count 2 2006.257.05:37:02.46#ibcon#read 4, iclass 26, count 2 2006.257.05:37:02.46#ibcon#about to read 5, iclass 26, count 2 2006.257.05:37:02.46#ibcon#read 5, iclass 26, count 2 2006.257.05:37:02.46#ibcon#about to read 6, iclass 26, count 2 2006.257.05:37:02.46#ibcon#read 6, iclass 26, count 2 2006.257.05:37:02.46#ibcon#end of sib2, iclass 26, count 2 2006.257.05:37:02.46#ibcon#*after write, iclass 26, count 2 2006.257.05:37:02.46#ibcon#*before return 0, iclass 26, count 2 2006.257.05:37:02.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:02.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:02.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.05:37:02.46#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:02.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:02.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:02.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:02.58#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:37:02.58#ibcon#first serial, iclass 26, count 0 2006.257.05:37:02.58#ibcon#enter sib2, iclass 26, count 0 2006.257.05:37:02.58#ibcon#flushed, iclass 26, count 0 2006.257.05:37:02.58#ibcon#about to write, iclass 26, count 0 2006.257.05:37:02.58#ibcon#wrote, iclass 26, count 0 2006.257.05:37:02.58#ibcon#about to read 3, iclass 26, count 0 2006.257.05:37:02.60#ibcon#read 3, iclass 26, count 0 2006.257.05:37:02.60#ibcon#about to read 4, iclass 26, count 0 2006.257.05:37:02.60#ibcon#read 4, iclass 26, count 0 2006.257.05:37:02.60#ibcon#about to read 5, iclass 26, count 0 2006.257.05:37:02.60#ibcon#read 5, iclass 26, count 0 2006.257.05:37:02.60#ibcon#about to read 6, iclass 26, count 0 2006.257.05:37:02.60#ibcon#read 6, iclass 26, count 0 2006.257.05:37:02.60#ibcon#end of sib2, iclass 26, count 0 2006.257.05:37:02.60#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:37:02.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:37:02.60#ibcon#[25=USB\r\n] 2006.257.05:37:02.60#ibcon#*before write, iclass 26, count 0 2006.257.05:37:02.60#ibcon#enter sib2, iclass 26, count 0 2006.257.05:37:02.60#ibcon#flushed, iclass 26, count 0 2006.257.05:37:02.60#ibcon#about to write, iclass 26, count 0 2006.257.05:37:02.60#ibcon#wrote, iclass 26, count 0 2006.257.05:37:02.60#ibcon#about to read 3, iclass 26, count 0 2006.257.05:37:02.63#ibcon#read 3, iclass 26, count 0 2006.257.05:37:02.63#ibcon#about to read 4, iclass 26, count 0 2006.257.05:37:02.63#ibcon#read 4, iclass 26, count 0 2006.257.05:37:02.63#ibcon#about to read 5, iclass 26, count 0 2006.257.05:37:02.63#ibcon#read 5, iclass 26, count 0 2006.257.05:37:02.63#ibcon#about to read 6, iclass 26, count 0 2006.257.05:37:02.63#ibcon#read 6, iclass 26, count 0 2006.257.05:37:02.63#ibcon#end of sib2, iclass 26, count 0 2006.257.05:37:02.63#ibcon#*after write, iclass 26, count 0 2006.257.05:37:02.63#ibcon#*before return 0, iclass 26, count 0 2006.257.05:37:02.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:02.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:02.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:37:02.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:37:02.63$vck44/valo=5,734.99 2006.257.05:37:02.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.05:37:02.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.05:37:02.63#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:02.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:02.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:02.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:02.63#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:37:02.63#ibcon#first serial, iclass 28, count 0 2006.257.05:37:02.63#ibcon#enter sib2, iclass 28, count 0 2006.257.05:37:02.63#ibcon#flushed, iclass 28, count 0 2006.257.05:37:02.63#ibcon#about to write, iclass 28, count 0 2006.257.05:37:02.63#ibcon#wrote, iclass 28, count 0 2006.257.05:37:02.63#ibcon#about to read 3, iclass 28, count 0 2006.257.05:37:02.65#ibcon#read 3, iclass 28, count 0 2006.257.05:37:02.65#ibcon#about to read 4, iclass 28, count 0 2006.257.05:37:02.65#ibcon#read 4, iclass 28, count 0 2006.257.05:37:02.65#ibcon#about to read 5, iclass 28, count 0 2006.257.05:37:02.65#ibcon#read 5, iclass 28, count 0 2006.257.05:37:02.65#ibcon#about to read 6, iclass 28, count 0 2006.257.05:37:02.65#ibcon#read 6, iclass 28, count 0 2006.257.05:37:02.65#ibcon#end of sib2, iclass 28, count 0 2006.257.05:37:02.65#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:37:02.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:37:02.65#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:37:02.65#ibcon#*before write, iclass 28, count 0 2006.257.05:37:02.65#ibcon#enter sib2, iclass 28, count 0 2006.257.05:37:02.65#ibcon#flushed, iclass 28, count 0 2006.257.05:37:02.65#ibcon#about to write, iclass 28, count 0 2006.257.05:37:02.65#ibcon#wrote, iclass 28, count 0 2006.257.05:37:02.65#ibcon#about to read 3, iclass 28, count 0 2006.257.05:37:02.69#ibcon#read 3, iclass 28, count 0 2006.257.05:37:02.69#ibcon#about to read 4, iclass 28, count 0 2006.257.05:37:02.69#ibcon#read 4, iclass 28, count 0 2006.257.05:37:02.69#ibcon#about to read 5, iclass 28, count 0 2006.257.05:37:02.69#ibcon#read 5, iclass 28, count 0 2006.257.05:37:02.69#ibcon#about to read 6, iclass 28, count 0 2006.257.05:37:02.69#ibcon#read 6, iclass 28, count 0 2006.257.05:37:02.69#ibcon#end of sib2, iclass 28, count 0 2006.257.05:37:02.69#ibcon#*after write, iclass 28, count 0 2006.257.05:37:02.69#ibcon#*before return 0, iclass 28, count 0 2006.257.05:37:02.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:02.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:02.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:37:02.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:37:02.69$vck44/va=5,4 2006.257.05:37:02.69#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.05:37:02.69#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.05:37:02.69#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:02.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:02.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:02.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:02.75#ibcon#enter wrdev, iclass 30, count 2 2006.257.05:37:02.75#ibcon#first serial, iclass 30, count 2 2006.257.05:37:02.75#ibcon#enter sib2, iclass 30, count 2 2006.257.05:37:02.75#ibcon#flushed, iclass 30, count 2 2006.257.05:37:02.75#ibcon#about to write, iclass 30, count 2 2006.257.05:37:02.75#ibcon#wrote, iclass 30, count 2 2006.257.05:37:02.75#ibcon#about to read 3, iclass 30, count 2 2006.257.05:37:02.77#ibcon#read 3, iclass 30, count 2 2006.257.05:37:02.77#ibcon#about to read 4, iclass 30, count 2 2006.257.05:37:02.77#ibcon#read 4, iclass 30, count 2 2006.257.05:37:02.77#ibcon#about to read 5, iclass 30, count 2 2006.257.05:37:02.77#ibcon#read 5, iclass 30, count 2 2006.257.05:37:02.77#ibcon#about to read 6, iclass 30, count 2 2006.257.05:37:02.77#ibcon#read 6, iclass 30, count 2 2006.257.05:37:02.77#ibcon#end of sib2, iclass 30, count 2 2006.257.05:37:02.77#ibcon#*mode == 0, iclass 30, count 2 2006.257.05:37:02.77#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.05:37:02.77#ibcon#[25=AT05-04\r\n] 2006.257.05:37:02.77#ibcon#*before write, iclass 30, count 2 2006.257.05:37:02.77#ibcon#enter sib2, iclass 30, count 2 2006.257.05:37:02.77#ibcon#flushed, iclass 30, count 2 2006.257.05:37:02.77#ibcon#about to write, iclass 30, count 2 2006.257.05:37:02.77#ibcon#wrote, iclass 30, count 2 2006.257.05:37:02.77#ibcon#about to read 3, iclass 30, count 2 2006.257.05:37:02.80#ibcon#read 3, iclass 30, count 2 2006.257.05:37:02.80#ibcon#about to read 4, iclass 30, count 2 2006.257.05:37:02.80#ibcon#read 4, iclass 30, count 2 2006.257.05:37:02.80#ibcon#about to read 5, iclass 30, count 2 2006.257.05:37:02.80#ibcon#read 5, iclass 30, count 2 2006.257.05:37:02.80#ibcon#about to read 6, iclass 30, count 2 2006.257.05:37:02.80#ibcon#read 6, iclass 30, count 2 2006.257.05:37:02.80#ibcon#end of sib2, iclass 30, count 2 2006.257.05:37:02.80#ibcon#*after write, iclass 30, count 2 2006.257.05:37:02.80#ibcon#*before return 0, iclass 30, count 2 2006.257.05:37:02.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:02.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:02.80#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.05:37:02.80#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:02.80#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:02.92#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:02.92#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:02.92#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:37:02.92#ibcon#first serial, iclass 30, count 0 2006.257.05:37:02.92#ibcon#enter sib2, iclass 30, count 0 2006.257.05:37:02.92#ibcon#flushed, iclass 30, count 0 2006.257.05:37:02.92#ibcon#about to write, iclass 30, count 0 2006.257.05:37:02.92#ibcon#wrote, iclass 30, count 0 2006.257.05:37:02.92#ibcon#about to read 3, iclass 30, count 0 2006.257.05:37:02.94#ibcon#read 3, iclass 30, count 0 2006.257.05:37:02.94#ibcon#about to read 4, iclass 30, count 0 2006.257.05:37:02.94#ibcon#read 4, iclass 30, count 0 2006.257.05:37:02.94#ibcon#about to read 5, iclass 30, count 0 2006.257.05:37:02.94#ibcon#read 5, iclass 30, count 0 2006.257.05:37:02.94#ibcon#about to read 6, iclass 30, count 0 2006.257.05:37:02.94#ibcon#read 6, iclass 30, count 0 2006.257.05:37:02.94#ibcon#end of sib2, iclass 30, count 0 2006.257.05:37:02.94#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:37:02.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:37:02.94#ibcon#[25=USB\r\n] 2006.257.05:37:02.94#ibcon#*before write, iclass 30, count 0 2006.257.05:37:02.94#ibcon#enter sib2, iclass 30, count 0 2006.257.05:37:02.94#ibcon#flushed, iclass 30, count 0 2006.257.05:37:02.94#ibcon#about to write, iclass 30, count 0 2006.257.05:37:02.94#ibcon#wrote, iclass 30, count 0 2006.257.05:37:02.94#ibcon#about to read 3, iclass 30, count 0 2006.257.05:37:02.97#ibcon#read 3, iclass 30, count 0 2006.257.05:37:02.97#ibcon#about to read 4, iclass 30, count 0 2006.257.05:37:02.97#ibcon#read 4, iclass 30, count 0 2006.257.05:37:02.97#ibcon#about to read 5, iclass 30, count 0 2006.257.05:37:02.97#ibcon#read 5, iclass 30, count 0 2006.257.05:37:02.97#ibcon#about to read 6, iclass 30, count 0 2006.257.05:37:02.97#ibcon#read 6, iclass 30, count 0 2006.257.05:37:02.97#ibcon#end of sib2, iclass 30, count 0 2006.257.05:37:02.97#ibcon#*after write, iclass 30, count 0 2006.257.05:37:02.97#ibcon#*before return 0, iclass 30, count 0 2006.257.05:37:02.97#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:02.97#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:02.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:37:02.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:37:02.97$vck44/valo=6,814.99 2006.257.05:37:02.97#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.05:37:02.97#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.05:37:02.97#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:02.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:02.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:02.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:02.97#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:37:02.97#ibcon#first serial, iclass 32, count 0 2006.257.05:37:02.97#ibcon#enter sib2, iclass 32, count 0 2006.257.05:37:02.97#ibcon#flushed, iclass 32, count 0 2006.257.05:37:02.97#ibcon#about to write, iclass 32, count 0 2006.257.05:37:02.97#ibcon#wrote, iclass 32, count 0 2006.257.05:37:02.97#ibcon#about to read 3, iclass 32, count 0 2006.257.05:37:02.99#ibcon#read 3, iclass 32, count 0 2006.257.05:37:02.99#ibcon#about to read 4, iclass 32, count 0 2006.257.05:37:02.99#ibcon#read 4, iclass 32, count 0 2006.257.05:37:02.99#ibcon#about to read 5, iclass 32, count 0 2006.257.05:37:02.99#ibcon#read 5, iclass 32, count 0 2006.257.05:37:02.99#ibcon#about to read 6, iclass 32, count 0 2006.257.05:37:02.99#ibcon#read 6, iclass 32, count 0 2006.257.05:37:02.99#ibcon#end of sib2, iclass 32, count 0 2006.257.05:37:02.99#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:37:02.99#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:37:02.99#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:37:02.99#ibcon#*before write, iclass 32, count 0 2006.257.05:37:02.99#ibcon#enter sib2, iclass 32, count 0 2006.257.05:37:02.99#ibcon#flushed, iclass 32, count 0 2006.257.05:37:02.99#ibcon#about to write, iclass 32, count 0 2006.257.05:37:02.99#ibcon#wrote, iclass 32, count 0 2006.257.05:37:02.99#ibcon#about to read 3, iclass 32, count 0 2006.257.05:37:03.03#ibcon#read 3, iclass 32, count 0 2006.257.05:37:03.03#ibcon#about to read 4, iclass 32, count 0 2006.257.05:37:03.03#ibcon#read 4, iclass 32, count 0 2006.257.05:37:03.03#ibcon#about to read 5, iclass 32, count 0 2006.257.05:37:03.03#ibcon#read 5, iclass 32, count 0 2006.257.05:37:03.03#ibcon#about to read 6, iclass 32, count 0 2006.257.05:37:03.03#ibcon#read 6, iclass 32, count 0 2006.257.05:37:03.03#ibcon#end of sib2, iclass 32, count 0 2006.257.05:37:03.03#ibcon#*after write, iclass 32, count 0 2006.257.05:37:03.03#ibcon#*before return 0, iclass 32, count 0 2006.257.05:37:03.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:03.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:03.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:37:03.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:37:03.03$vck44/va=6,4 2006.257.05:37:03.03#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.05:37:03.03#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.05:37:03.03#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:03.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:03.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:03.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:03.09#ibcon#enter wrdev, iclass 34, count 2 2006.257.05:37:03.09#ibcon#first serial, iclass 34, count 2 2006.257.05:37:03.09#ibcon#enter sib2, iclass 34, count 2 2006.257.05:37:03.09#ibcon#flushed, iclass 34, count 2 2006.257.05:37:03.09#ibcon#about to write, iclass 34, count 2 2006.257.05:37:03.09#ibcon#wrote, iclass 34, count 2 2006.257.05:37:03.09#ibcon#about to read 3, iclass 34, count 2 2006.257.05:37:03.11#ibcon#read 3, iclass 34, count 2 2006.257.05:37:03.11#ibcon#about to read 4, iclass 34, count 2 2006.257.05:37:03.11#ibcon#read 4, iclass 34, count 2 2006.257.05:37:03.11#ibcon#about to read 5, iclass 34, count 2 2006.257.05:37:03.11#ibcon#read 5, iclass 34, count 2 2006.257.05:37:03.11#ibcon#about to read 6, iclass 34, count 2 2006.257.05:37:03.11#ibcon#read 6, iclass 34, count 2 2006.257.05:37:03.11#ibcon#end of sib2, iclass 34, count 2 2006.257.05:37:03.11#ibcon#*mode == 0, iclass 34, count 2 2006.257.05:37:03.11#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.05:37:03.11#ibcon#[25=AT06-04\r\n] 2006.257.05:37:03.11#ibcon#*before write, iclass 34, count 2 2006.257.05:37:03.11#ibcon#enter sib2, iclass 34, count 2 2006.257.05:37:03.11#ibcon#flushed, iclass 34, count 2 2006.257.05:37:03.11#ibcon#about to write, iclass 34, count 2 2006.257.05:37:03.11#ibcon#wrote, iclass 34, count 2 2006.257.05:37:03.11#ibcon#about to read 3, iclass 34, count 2 2006.257.05:37:03.14#ibcon#read 3, iclass 34, count 2 2006.257.05:37:03.14#ibcon#about to read 4, iclass 34, count 2 2006.257.05:37:03.14#ibcon#read 4, iclass 34, count 2 2006.257.05:37:03.14#ibcon#about to read 5, iclass 34, count 2 2006.257.05:37:03.14#ibcon#read 5, iclass 34, count 2 2006.257.05:37:03.14#ibcon#about to read 6, iclass 34, count 2 2006.257.05:37:03.14#ibcon#read 6, iclass 34, count 2 2006.257.05:37:03.14#ibcon#end of sib2, iclass 34, count 2 2006.257.05:37:03.14#ibcon#*after write, iclass 34, count 2 2006.257.05:37:03.14#ibcon#*before return 0, iclass 34, count 2 2006.257.05:37:03.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:03.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:03.14#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.05:37:03.14#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:03.14#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:03.26#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:03.26#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:03.26#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:37:03.26#ibcon#first serial, iclass 34, count 0 2006.257.05:37:03.26#ibcon#enter sib2, iclass 34, count 0 2006.257.05:37:03.26#ibcon#flushed, iclass 34, count 0 2006.257.05:37:03.26#ibcon#about to write, iclass 34, count 0 2006.257.05:37:03.26#ibcon#wrote, iclass 34, count 0 2006.257.05:37:03.26#ibcon#about to read 3, iclass 34, count 0 2006.257.05:37:03.28#ibcon#read 3, iclass 34, count 0 2006.257.05:37:03.28#ibcon#about to read 4, iclass 34, count 0 2006.257.05:37:03.28#ibcon#read 4, iclass 34, count 0 2006.257.05:37:03.28#ibcon#about to read 5, iclass 34, count 0 2006.257.05:37:03.28#ibcon#read 5, iclass 34, count 0 2006.257.05:37:03.28#ibcon#about to read 6, iclass 34, count 0 2006.257.05:37:03.28#ibcon#read 6, iclass 34, count 0 2006.257.05:37:03.28#ibcon#end of sib2, iclass 34, count 0 2006.257.05:37:03.28#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:37:03.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:37:03.28#ibcon#[25=USB\r\n] 2006.257.05:37:03.28#ibcon#*before write, iclass 34, count 0 2006.257.05:37:03.28#ibcon#enter sib2, iclass 34, count 0 2006.257.05:37:03.28#ibcon#flushed, iclass 34, count 0 2006.257.05:37:03.28#ibcon#about to write, iclass 34, count 0 2006.257.05:37:03.28#ibcon#wrote, iclass 34, count 0 2006.257.05:37:03.28#ibcon#about to read 3, iclass 34, count 0 2006.257.05:37:03.31#ibcon#read 3, iclass 34, count 0 2006.257.05:37:03.31#ibcon#about to read 4, iclass 34, count 0 2006.257.05:37:03.31#ibcon#read 4, iclass 34, count 0 2006.257.05:37:03.31#ibcon#about to read 5, iclass 34, count 0 2006.257.05:37:03.31#ibcon#read 5, iclass 34, count 0 2006.257.05:37:03.31#ibcon#about to read 6, iclass 34, count 0 2006.257.05:37:03.31#ibcon#read 6, iclass 34, count 0 2006.257.05:37:03.31#ibcon#end of sib2, iclass 34, count 0 2006.257.05:37:03.31#ibcon#*after write, iclass 34, count 0 2006.257.05:37:03.31#ibcon#*before return 0, iclass 34, count 0 2006.257.05:37:03.31#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:03.31#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:03.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:37:03.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:37:03.31$vck44/valo=7,864.99 2006.257.05:37:03.31#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.05:37:03.31#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.05:37:03.31#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:03.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:03.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:03.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:03.31#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:37:03.31#ibcon#first serial, iclass 36, count 0 2006.257.05:37:03.31#ibcon#enter sib2, iclass 36, count 0 2006.257.05:37:03.31#ibcon#flushed, iclass 36, count 0 2006.257.05:37:03.31#ibcon#about to write, iclass 36, count 0 2006.257.05:37:03.31#ibcon#wrote, iclass 36, count 0 2006.257.05:37:03.31#ibcon#about to read 3, iclass 36, count 0 2006.257.05:37:03.33#ibcon#read 3, iclass 36, count 0 2006.257.05:37:03.33#ibcon#about to read 4, iclass 36, count 0 2006.257.05:37:03.33#ibcon#read 4, iclass 36, count 0 2006.257.05:37:03.33#ibcon#about to read 5, iclass 36, count 0 2006.257.05:37:03.33#ibcon#read 5, iclass 36, count 0 2006.257.05:37:03.33#ibcon#about to read 6, iclass 36, count 0 2006.257.05:37:03.33#ibcon#read 6, iclass 36, count 0 2006.257.05:37:03.33#ibcon#end of sib2, iclass 36, count 0 2006.257.05:37:03.33#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:37:03.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:37:03.33#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:37:03.33#ibcon#*before write, iclass 36, count 0 2006.257.05:37:03.33#ibcon#enter sib2, iclass 36, count 0 2006.257.05:37:03.33#ibcon#flushed, iclass 36, count 0 2006.257.05:37:03.33#ibcon#about to write, iclass 36, count 0 2006.257.05:37:03.33#ibcon#wrote, iclass 36, count 0 2006.257.05:37:03.33#ibcon#about to read 3, iclass 36, count 0 2006.257.05:37:03.37#ibcon#read 3, iclass 36, count 0 2006.257.05:37:03.37#ibcon#about to read 4, iclass 36, count 0 2006.257.05:37:03.37#ibcon#read 4, iclass 36, count 0 2006.257.05:37:03.37#ibcon#about to read 5, iclass 36, count 0 2006.257.05:37:03.37#ibcon#read 5, iclass 36, count 0 2006.257.05:37:03.37#ibcon#about to read 6, iclass 36, count 0 2006.257.05:37:03.37#ibcon#read 6, iclass 36, count 0 2006.257.05:37:03.37#ibcon#end of sib2, iclass 36, count 0 2006.257.05:37:03.37#ibcon#*after write, iclass 36, count 0 2006.257.05:37:03.37#ibcon#*before return 0, iclass 36, count 0 2006.257.05:37:03.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:03.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:03.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:37:03.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:37:03.37$vck44/va=7,4 2006.257.05:37:03.37#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.05:37:03.37#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.05:37:03.37#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:03.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:03.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:03.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:03.43#ibcon#enter wrdev, iclass 38, count 2 2006.257.05:37:03.43#ibcon#first serial, iclass 38, count 2 2006.257.05:37:03.43#ibcon#enter sib2, iclass 38, count 2 2006.257.05:37:03.43#ibcon#flushed, iclass 38, count 2 2006.257.05:37:03.43#ibcon#about to write, iclass 38, count 2 2006.257.05:37:03.43#ibcon#wrote, iclass 38, count 2 2006.257.05:37:03.43#ibcon#about to read 3, iclass 38, count 2 2006.257.05:37:03.45#ibcon#read 3, iclass 38, count 2 2006.257.05:37:03.45#ibcon#about to read 4, iclass 38, count 2 2006.257.05:37:03.45#ibcon#read 4, iclass 38, count 2 2006.257.05:37:03.45#ibcon#about to read 5, iclass 38, count 2 2006.257.05:37:03.45#ibcon#read 5, iclass 38, count 2 2006.257.05:37:03.45#ibcon#about to read 6, iclass 38, count 2 2006.257.05:37:03.45#ibcon#read 6, iclass 38, count 2 2006.257.05:37:03.45#ibcon#end of sib2, iclass 38, count 2 2006.257.05:37:03.45#ibcon#*mode == 0, iclass 38, count 2 2006.257.05:37:03.45#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.05:37:03.45#ibcon#[25=AT07-04\r\n] 2006.257.05:37:03.45#ibcon#*before write, iclass 38, count 2 2006.257.05:37:03.45#ibcon#enter sib2, iclass 38, count 2 2006.257.05:37:03.45#ibcon#flushed, iclass 38, count 2 2006.257.05:37:03.45#ibcon#about to write, iclass 38, count 2 2006.257.05:37:03.45#ibcon#wrote, iclass 38, count 2 2006.257.05:37:03.45#ibcon#about to read 3, iclass 38, count 2 2006.257.05:37:03.48#ibcon#read 3, iclass 38, count 2 2006.257.05:37:03.48#ibcon#about to read 4, iclass 38, count 2 2006.257.05:37:03.48#ibcon#read 4, iclass 38, count 2 2006.257.05:37:03.48#ibcon#about to read 5, iclass 38, count 2 2006.257.05:37:03.48#ibcon#read 5, iclass 38, count 2 2006.257.05:37:03.48#ibcon#about to read 6, iclass 38, count 2 2006.257.05:37:03.48#ibcon#read 6, iclass 38, count 2 2006.257.05:37:03.48#ibcon#end of sib2, iclass 38, count 2 2006.257.05:37:03.48#ibcon#*after write, iclass 38, count 2 2006.257.05:37:03.48#ibcon#*before return 0, iclass 38, count 2 2006.257.05:37:03.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:03.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:03.48#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.05:37:03.48#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:03.48#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:03.60#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:03.60#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:03.60#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:37:03.60#ibcon#first serial, iclass 38, count 0 2006.257.05:37:03.60#ibcon#enter sib2, iclass 38, count 0 2006.257.05:37:03.60#ibcon#flushed, iclass 38, count 0 2006.257.05:37:03.60#ibcon#about to write, iclass 38, count 0 2006.257.05:37:03.60#ibcon#wrote, iclass 38, count 0 2006.257.05:37:03.60#ibcon#about to read 3, iclass 38, count 0 2006.257.05:37:03.62#ibcon#read 3, iclass 38, count 0 2006.257.05:37:03.62#ibcon#about to read 4, iclass 38, count 0 2006.257.05:37:03.62#ibcon#read 4, iclass 38, count 0 2006.257.05:37:03.62#ibcon#about to read 5, iclass 38, count 0 2006.257.05:37:03.62#ibcon#read 5, iclass 38, count 0 2006.257.05:37:03.62#ibcon#about to read 6, iclass 38, count 0 2006.257.05:37:03.62#ibcon#read 6, iclass 38, count 0 2006.257.05:37:03.62#ibcon#end of sib2, iclass 38, count 0 2006.257.05:37:03.62#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:37:03.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:37:03.62#ibcon#[25=USB\r\n] 2006.257.05:37:03.62#ibcon#*before write, iclass 38, count 0 2006.257.05:37:03.62#ibcon#enter sib2, iclass 38, count 0 2006.257.05:37:03.62#ibcon#flushed, iclass 38, count 0 2006.257.05:37:03.62#ibcon#about to write, iclass 38, count 0 2006.257.05:37:03.62#ibcon#wrote, iclass 38, count 0 2006.257.05:37:03.62#ibcon#about to read 3, iclass 38, count 0 2006.257.05:37:03.65#ibcon#read 3, iclass 38, count 0 2006.257.05:37:03.65#ibcon#about to read 4, iclass 38, count 0 2006.257.05:37:03.65#ibcon#read 4, iclass 38, count 0 2006.257.05:37:03.65#ibcon#about to read 5, iclass 38, count 0 2006.257.05:37:03.65#ibcon#read 5, iclass 38, count 0 2006.257.05:37:03.65#ibcon#about to read 6, iclass 38, count 0 2006.257.05:37:03.65#ibcon#read 6, iclass 38, count 0 2006.257.05:37:03.65#ibcon#end of sib2, iclass 38, count 0 2006.257.05:37:03.65#ibcon#*after write, iclass 38, count 0 2006.257.05:37:03.65#ibcon#*before return 0, iclass 38, count 0 2006.257.05:37:03.65#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:03.65#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:03.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:37:03.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:37:03.65$vck44/valo=8,884.99 2006.257.05:37:03.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.05:37:03.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.05:37:03.65#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:03.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:03.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:03.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:03.65#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:37:03.65#ibcon#first serial, iclass 40, count 0 2006.257.05:37:03.65#ibcon#enter sib2, iclass 40, count 0 2006.257.05:37:03.65#ibcon#flushed, iclass 40, count 0 2006.257.05:37:03.65#ibcon#about to write, iclass 40, count 0 2006.257.05:37:03.65#ibcon#wrote, iclass 40, count 0 2006.257.05:37:03.65#ibcon#about to read 3, iclass 40, count 0 2006.257.05:37:03.67#ibcon#read 3, iclass 40, count 0 2006.257.05:37:03.67#ibcon#about to read 4, iclass 40, count 0 2006.257.05:37:03.67#ibcon#read 4, iclass 40, count 0 2006.257.05:37:03.67#ibcon#about to read 5, iclass 40, count 0 2006.257.05:37:03.67#ibcon#read 5, iclass 40, count 0 2006.257.05:37:03.67#ibcon#about to read 6, iclass 40, count 0 2006.257.05:37:03.67#ibcon#read 6, iclass 40, count 0 2006.257.05:37:03.67#ibcon#end of sib2, iclass 40, count 0 2006.257.05:37:03.67#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:37:03.67#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:37:03.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:37:03.67#ibcon#*before write, iclass 40, count 0 2006.257.05:37:03.67#ibcon#enter sib2, iclass 40, count 0 2006.257.05:37:03.67#ibcon#flushed, iclass 40, count 0 2006.257.05:37:03.67#ibcon#about to write, iclass 40, count 0 2006.257.05:37:03.67#ibcon#wrote, iclass 40, count 0 2006.257.05:37:03.67#ibcon#about to read 3, iclass 40, count 0 2006.257.05:37:03.71#ibcon#read 3, iclass 40, count 0 2006.257.05:37:03.71#ibcon#about to read 4, iclass 40, count 0 2006.257.05:37:03.71#ibcon#read 4, iclass 40, count 0 2006.257.05:37:03.71#ibcon#about to read 5, iclass 40, count 0 2006.257.05:37:03.71#ibcon#read 5, iclass 40, count 0 2006.257.05:37:03.71#ibcon#about to read 6, iclass 40, count 0 2006.257.05:37:03.71#ibcon#read 6, iclass 40, count 0 2006.257.05:37:03.71#ibcon#end of sib2, iclass 40, count 0 2006.257.05:37:03.71#ibcon#*after write, iclass 40, count 0 2006.257.05:37:03.71#ibcon#*before return 0, iclass 40, count 0 2006.257.05:37:03.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:03.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:03.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:37:03.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:37:03.71$vck44/va=8,4 2006.257.05:37:03.71#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.05:37:03.71#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.05:37:03.71#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:03.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:37:03.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:37:03.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:37:03.77#ibcon#enter wrdev, iclass 4, count 2 2006.257.05:37:03.77#ibcon#first serial, iclass 4, count 2 2006.257.05:37:03.77#ibcon#enter sib2, iclass 4, count 2 2006.257.05:37:03.77#ibcon#flushed, iclass 4, count 2 2006.257.05:37:03.77#ibcon#about to write, iclass 4, count 2 2006.257.05:37:03.77#ibcon#wrote, iclass 4, count 2 2006.257.05:37:03.77#ibcon#about to read 3, iclass 4, count 2 2006.257.05:37:03.79#ibcon#read 3, iclass 4, count 2 2006.257.05:37:03.79#ibcon#about to read 4, iclass 4, count 2 2006.257.05:37:03.79#ibcon#read 4, iclass 4, count 2 2006.257.05:37:03.79#ibcon#about to read 5, iclass 4, count 2 2006.257.05:37:03.79#ibcon#read 5, iclass 4, count 2 2006.257.05:37:03.79#ibcon#about to read 6, iclass 4, count 2 2006.257.05:37:03.79#ibcon#read 6, iclass 4, count 2 2006.257.05:37:03.79#ibcon#end of sib2, iclass 4, count 2 2006.257.05:37:03.79#ibcon#*mode == 0, iclass 4, count 2 2006.257.05:37:03.79#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.05:37:03.79#ibcon#[25=AT08-04\r\n] 2006.257.05:37:03.79#ibcon#*before write, iclass 4, count 2 2006.257.05:37:03.79#ibcon#enter sib2, iclass 4, count 2 2006.257.05:37:03.79#ibcon#flushed, iclass 4, count 2 2006.257.05:37:03.79#ibcon#about to write, iclass 4, count 2 2006.257.05:37:03.79#ibcon#wrote, iclass 4, count 2 2006.257.05:37:03.79#ibcon#about to read 3, iclass 4, count 2 2006.257.05:37:03.82#ibcon#read 3, iclass 4, count 2 2006.257.05:37:03.82#ibcon#about to read 4, iclass 4, count 2 2006.257.05:37:03.82#ibcon#read 4, iclass 4, count 2 2006.257.05:37:03.82#ibcon#about to read 5, iclass 4, count 2 2006.257.05:37:03.82#ibcon#read 5, iclass 4, count 2 2006.257.05:37:03.82#ibcon#about to read 6, iclass 4, count 2 2006.257.05:37:03.82#ibcon#read 6, iclass 4, count 2 2006.257.05:37:03.82#ibcon#end of sib2, iclass 4, count 2 2006.257.05:37:03.82#ibcon#*after write, iclass 4, count 2 2006.257.05:37:03.82#ibcon#*before return 0, iclass 4, count 2 2006.257.05:37:03.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:37:03.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:37:03.82#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.05:37:03.82#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:03.82#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:37:03.94#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:37:03.94#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:37:03.94#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:37:03.94#ibcon#first serial, iclass 4, count 0 2006.257.05:37:03.94#ibcon#enter sib2, iclass 4, count 0 2006.257.05:37:03.94#ibcon#flushed, iclass 4, count 0 2006.257.05:37:03.94#ibcon#about to write, iclass 4, count 0 2006.257.05:37:03.94#ibcon#wrote, iclass 4, count 0 2006.257.05:37:03.94#ibcon#about to read 3, iclass 4, count 0 2006.257.05:37:03.96#ibcon#read 3, iclass 4, count 0 2006.257.05:37:03.96#ibcon#about to read 4, iclass 4, count 0 2006.257.05:37:03.96#ibcon#read 4, iclass 4, count 0 2006.257.05:37:03.96#ibcon#about to read 5, iclass 4, count 0 2006.257.05:37:03.96#ibcon#read 5, iclass 4, count 0 2006.257.05:37:03.96#ibcon#about to read 6, iclass 4, count 0 2006.257.05:37:03.96#ibcon#read 6, iclass 4, count 0 2006.257.05:37:03.96#ibcon#end of sib2, iclass 4, count 0 2006.257.05:37:03.96#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:37:03.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:37:03.96#ibcon#[25=USB\r\n] 2006.257.05:37:03.96#ibcon#*before write, iclass 4, count 0 2006.257.05:37:03.96#ibcon#enter sib2, iclass 4, count 0 2006.257.05:37:03.96#ibcon#flushed, iclass 4, count 0 2006.257.05:37:03.96#ibcon#about to write, iclass 4, count 0 2006.257.05:37:03.96#ibcon#wrote, iclass 4, count 0 2006.257.05:37:03.96#ibcon#about to read 3, iclass 4, count 0 2006.257.05:37:03.99#ibcon#read 3, iclass 4, count 0 2006.257.05:37:03.99#ibcon#about to read 4, iclass 4, count 0 2006.257.05:37:03.99#ibcon#read 4, iclass 4, count 0 2006.257.05:37:03.99#ibcon#about to read 5, iclass 4, count 0 2006.257.05:37:03.99#ibcon#read 5, iclass 4, count 0 2006.257.05:37:03.99#ibcon#about to read 6, iclass 4, count 0 2006.257.05:37:03.99#ibcon#read 6, iclass 4, count 0 2006.257.05:37:03.99#ibcon#end of sib2, iclass 4, count 0 2006.257.05:37:03.99#ibcon#*after write, iclass 4, count 0 2006.257.05:37:03.99#ibcon#*before return 0, iclass 4, count 0 2006.257.05:37:03.99#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:37:03.99#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:37:03.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:37:03.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:37:03.99$vck44/vblo=1,629.99 2006.257.05:37:03.99#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.05:37:03.99#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.05:37:03.99#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:03.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:37:03.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:37:03.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:37:03.99#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:37:03.99#ibcon#first serial, iclass 6, count 0 2006.257.05:37:03.99#ibcon#enter sib2, iclass 6, count 0 2006.257.05:37:03.99#ibcon#flushed, iclass 6, count 0 2006.257.05:37:03.99#ibcon#about to write, iclass 6, count 0 2006.257.05:37:03.99#ibcon#wrote, iclass 6, count 0 2006.257.05:37:03.99#ibcon#about to read 3, iclass 6, count 0 2006.257.05:37:04.01#ibcon#read 3, iclass 6, count 0 2006.257.05:37:04.01#ibcon#about to read 4, iclass 6, count 0 2006.257.05:37:04.01#ibcon#read 4, iclass 6, count 0 2006.257.05:37:04.01#ibcon#about to read 5, iclass 6, count 0 2006.257.05:37:04.01#ibcon#read 5, iclass 6, count 0 2006.257.05:37:04.01#ibcon#about to read 6, iclass 6, count 0 2006.257.05:37:04.01#ibcon#read 6, iclass 6, count 0 2006.257.05:37:04.01#ibcon#end of sib2, iclass 6, count 0 2006.257.05:37:04.01#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:37:04.01#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:37:04.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:37:04.01#ibcon#*before write, iclass 6, count 0 2006.257.05:37:04.01#ibcon#enter sib2, iclass 6, count 0 2006.257.05:37:04.01#ibcon#flushed, iclass 6, count 0 2006.257.05:37:04.01#ibcon#about to write, iclass 6, count 0 2006.257.05:37:04.01#ibcon#wrote, iclass 6, count 0 2006.257.05:37:04.01#ibcon#about to read 3, iclass 6, count 0 2006.257.05:37:04.05#ibcon#read 3, iclass 6, count 0 2006.257.05:37:04.05#ibcon#about to read 4, iclass 6, count 0 2006.257.05:37:04.05#ibcon#read 4, iclass 6, count 0 2006.257.05:37:04.05#ibcon#about to read 5, iclass 6, count 0 2006.257.05:37:04.05#ibcon#read 5, iclass 6, count 0 2006.257.05:37:04.05#ibcon#about to read 6, iclass 6, count 0 2006.257.05:37:04.05#ibcon#read 6, iclass 6, count 0 2006.257.05:37:04.05#ibcon#end of sib2, iclass 6, count 0 2006.257.05:37:04.05#ibcon#*after write, iclass 6, count 0 2006.257.05:37:04.05#ibcon#*before return 0, iclass 6, count 0 2006.257.05:37:04.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:37:04.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:37:04.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:37:04.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:37:04.05$vck44/vb=1,4 2006.257.05:37:04.05#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.05:37:04.05#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.05:37:04.05#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:04.05#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:37:04.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:37:04.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:37:04.05#ibcon#enter wrdev, iclass 10, count 2 2006.257.05:37:04.05#ibcon#first serial, iclass 10, count 2 2006.257.05:37:04.05#ibcon#enter sib2, iclass 10, count 2 2006.257.05:37:04.05#ibcon#flushed, iclass 10, count 2 2006.257.05:37:04.05#ibcon#about to write, iclass 10, count 2 2006.257.05:37:04.05#ibcon#wrote, iclass 10, count 2 2006.257.05:37:04.05#ibcon#about to read 3, iclass 10, count 2 2006.257.05:37:04.07#ibcon#read 3, iclass 10, count 2 2006.257.05:37:04.07#ibcon#about to read 4, iclass 10, count 2 2006.257.05:37:04.07#ibcon#read 4, iclass 10, count 2 2006.257.05:37:04.07#ibcon#about to read 5, iclass 10, count 2 2006.257.05:37:04.07#ibcon#read 5, iclass 10, count 2 2006.257.05:37:04.07#ibcon#about to read 6, iclass 10, count 2 2006.257.05:37:04.07#ibcon#read 6, iclass 10, count 2 2006.257.05:37:04.07#ibcon#end of sib2, iclass 10, count 2 2006.257.05:37:04.07#ibcon#*mode == 0, iclass 10, count 2 2006.257.05:37:04.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.05:37:04.07#ibcon#[27=AT01-04\r\n] 2006.257.05:37:04.07#ibcon#*before write, iclass 10, count 2 2006.257.05:37:04.07#ibcon#enter sib2, iclass 10, count 2 2006.257.05:37:04.07#ibcon#flushed, iclass 10, count 2 2006.257.05:37:04.07#ibcon#about to write, iclass 10, count 2 2006.257.05:37:04.07#ibcon#wrote, iclass 10, count 2 2006.257.05:37:04.07#ibcon#about to read 3, iclass 10, count 2 2006.257.05:37:04.10#ibcon#read 3, iclass 10, count 2 2006.257.05:37:04.10#ibcon#about to read 4, iclass 10, count 2 2006.257.05:37:04.10#ibcon#read 4, iclass 10, count 2 2006.257.05:37:04.10#ibcon#about to read 5, iclass 10, count 2 2006.257.05:37:04.10#ibcon#read 5, iclass 10, count 2 2006.257.05:37:04.10#ibcon#about to read 6, iclass 10, count 2 2006.257.05:37:04.10#ibcon#read 6, iclass 10, count 2 2006.257.05:37:04.10#ibcon#end of sib2, iclass 10, count 2 2006.257.05:37:04.10#ibcon#*after write, iclass 10, count 2 2006.257.05:37:04.10#ibcon#*before return 0, iclass 10, count 2 2006.257.05:37:04.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:37:04.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:37:04.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.05:37:04.10#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:04.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:37:04.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:37:04.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:37:04.22#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:37:04.22#ibcon#first serial, iclass 10, count 0 2006.257.05:37:04.22#ibcon#enter sib2, iclass 10, count 0 2006.257.05:37:04.22#ibcon#flushed, iclass 10, count 0 2006.257.05:37:04.22#ibcon#about to write, iclass 10, count 0 2006.257.05:37:04.22#ibcon#wrote, iclass 10, count 0 2006.257.05:37:04.22#ibcon#about to read 3, iclass 10, count 0 2006.257.05:37:04.24#ibcon#read 3, iclass 10, count 0 2006.257.05:37:04.24#ibcon#about to read 4, iclass 10, count 0 2006.257.05:37:04.24#ibcon#read 4, iclass 10, count 0 2006.257.05:37:04.24#ibcon#about to read 5, iclass 10, count 0 2006.257.05:37:04.24#ibcon#read 5, iclass 10, count 0 2006.257.05:37:04.24#ibcon#about to read 6, iclass 10, count 0 2006.257.05:37:04.24#ibcon#read 6, iclass 10, count 0 2006.257.05:37:04.24#ibcon#end of sib2, iclass 10, count 0 2006.257.05:37:04.24#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:37:04.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:37:04.24#ibcon#[27=USB\r\n] 2006.257.05:37:04.24#ibcon#*before write, iclass 10, count 0 2006.257.05:37:04.24#ibcon#enter sib2, iclass 10, count 0 2006.257.05:37:04.24#ibcon#flushed, iclass 10, count 0 2006.257.05:37:04.24#ibcon#about to write, iclass 10, count 0 2006.257.05:37:04.24#ibcon#wrote, iclass 10, count 0 2006.257.05:37:04.24#ibcon#about to read 3, iclass 10, count 0 2006.257.05:37:04.27#ibcon#read 3, iclass 10, count 0 2006.257.05:37:04.27#ibcon#about to read 4, iclass 10, count 0 2006.257.05:37:04.27#ibcon#read 4, iclass 10, count 0 2006.257.05:37:04.27#ibcon#about to read 5, iclass 10, count 0 2006.257.05:37:04.27#ibcon#read 5, iclass 10, count 0 2006.257.05:37:04.27#ibcon#about to read 6, iclass 10, count 0 2006.257.05:37:04.27#ibcon#read 6, iclass 10, count 0 2006.257.05:37:04.27#ibcon#end of sib2, iclass 10, count 0 2006.257.05:37:04.27#ibcon#*after write, iclass 10, count 0 2006.257.05:37:04.27#ibcon#*before return 0, iclass 10, count 0 2006.257.05:37:04.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:37:04.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:37:04.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:37:04.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:37:04.27$vck44/vblo=2,634.99 2006.257.05:37:04.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.05:37:04.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.05:37:04.27#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:04.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:04.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:04.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:04.27#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:37:04.27#ibcon#first serial, iclass 12, count 0 2006.257.05:37:04.27#ibcon#enter sib2, iclass 12, count 0 2006.257.05:37:04.27#ibcon#flushed, iclass 12, count 0 2006.257.05:37:04.27#ibcon#about to write, iclass 12, count 0 2006.257.05:37:04.27#ibcon#wrote, iclass 12, count 0 2006.257.05:37:04.27#ibcon#about to read 3, iclass 12, count 0 2006.257.05:37:04.29#ibcon#read 3, iclass 12, count 0 2006.257.05:37:04.29#ibcon#about to read 4, iclass 12, count 0 2006.257.05:37:04.29#ibcon#read 4, iclass 12, count 0 2006.257.05:37:04.29#ibcon#about to read 5, iclass 12, count 0 2006.257.05:37:04.29#ibcon#read 5, iclass 12, count 0 2006.257.05:37:04.29#ibcon#about to read 6, iclass 12, count 0 2006.257.05:37:04.29#ibcon#read 6, iclass 12, count 0 2006.257.05:37:04.29#ibcon#end of sib2, iclass 12, count 0 2006.257.05:37:04.29#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:37:04.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:37:04.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:37:04.29#ibcon#*before write, iclass 12, count 0 2006.257.05:37:04.29#ibcon#enter sib2, iclass 12, count 0 2006.257.05:37:04.29#ibcon#flushed, iclass 12, count 0 2006.257.05:37:04.29#ibcon#about to write, iclass 12, count 0 2006.257.05:37:04.29#ibcon#wrote, iclass 12, count 0 2006.257.05:37:04.29#ibcon#about to read 3, iclass 12, count 0 2006.257.05:37:04.33#ibcon#read 3, iclass 12, count 0 2006.257.05:37:04.33#ibcon#about to read 4, iclass 12, count 0 2006.257.05:37:04.33#ibcon#read 4, iclass 12, count 0 2006.257.05:37:04.33#ibcon#about to read 5, iclass 12, count 0 2006.257.05:37:04.33#ibcon#read 5, iclass 12, count 0 2006.257.05:37:04.33#ibcon#about to read 6, iclass 12, count 0 2006.257.05:37:04.33#ibcon#read 6, iclass 12, count 0 2006.257.05:37:04.33#ibcon#end of sib2, iclass 12, count 0 2006.257.05:37:04.33#ibcon#*after write, iclass 12, count 0 2006.257.05:37:04.33#ibcon#*before return 0, iclass 12, count 0 2006.257.05:37:04.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:04.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:37:04.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:37:04.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:37:04.33$vck44/vb=2,5 2006.257.05:37:04.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.05:37:04.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.05:37:04.33#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:04.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:04.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:04.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:04.39#ibcon#enter wrdev, iclass 14, count 2 2006.257.05:37:04.39#ibcon#first serial, iclass 14, count 2 2006.257.05:37:04.39#ibcon#enter sib2, iclass 14, count 2 2006.257.05:37:04.39#ibcon#flushed, iclass 14, count 2 2006.257.05:37:04.39#ibcon#about to write, iclass 14, count 2 2006.257.05:37:04.39#ibcon#wrote, iclass 14, count 2 2006.257.05:37:04.39#ibcon#about to read 3, iclass 14, count 2 2006.257.05:37:04.41#ibcon#read 3, iclass 14, count 2 2006.257.05:37:04.41#ibcon#about to read 4, iclass 14, count 2 2006.257.05:37:04.41#ibcon#read 4, iclass 14, count 2 2006.257.05:37:04.41#ibcon#about to read 5, iclass 14, count 2 2006.257.05:37:04.41#ibcon#read 5, iclass 14, count 2 2006.257.05:37:04.41#ibcon#about to read 6, iclass 14, count 2 2006.257.05:37:04.41#ibcon#read 6, iclass 14, count 2 2006.257.05:37:04.41#ibcon#end of sib2, iclass 14, count 2 2006.257.05:37:04.41#ibcon#*mode == 0, iclass 14, count 2 2006.257.05:37:04.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.05:37:04.41#ibcon#[27=AT02-05\r\n] 2006.257.05:37:04.41#ibcon#*before write, iclass 14, count 2 2006.257.05:37:04.41#ibcon#enter sib2, iclass 14, count 2 2006.257.05:37:04.41#ibcon#flushed, iclass 14, count 2 2006.257.05:37:04.41#ibcon#about to write, iclass 14, count 2 2006.257.05:37:04.41#ibcon#wrote, iclass 14, count 2 2006.257.05:37:04.41#ibcon#about to read 3, iclass 14, count 2 2006.257.05:37:04.44#ibcon#read 3, iclass 14, count 2 2006.257.05:37:04.44#ibcon#about to read 4, iclass 14, count 2 2006.257.05:37:04.44#ibcon#read 4, iclass 14, count 2 2006.257.05:37:04.44#ibcon#about to read 5, iclass 14, count 2 2006.257.05:37:04.44#ibcon#read 5, iclass 14, count 2 2006.257.05:37:04.44#ibcon#about to read 6, iclass 14, count 2 2006.257.05:37:04.44#ibcon#read 6, iclass 14, count 2 2006.257.05:37:04.44#ibcon#end of sib2, iclass 14, count 2 2006.257.05:37:04.44#ibcon#*after write, iclass 14, count 2 2006.257.05:37:04.44#ibcon#*before return 0, iclass 14, count 2 2006.257.05:37:04.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:04.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:37:04.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.05:37:04.44#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:04.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:04.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:04.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:04.56#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:37:04.56#ibcon#first serial, iclass 14, count 0 2006.257.05:37:04.56#ibcon#enter sib2, iclass 14, count 0 2006.257.05:37:04.56#ibcon#flushed, iclass 14, count 0 2006.257.05:37:04.56#ibcon#about to write, iclass 14, count 0 2006.257.05:37:04.56#ibcon#wrote, iclass 14, count 0 2006.257.05:37:04.56#ibcon#about to read 3, iclass 14, count 0 2006.257.05:37:04.58#ibcon#read 3, iclass 14, count 0 2006.257.05:37:04.58#ibcon#about to read 4, iclass 14, count 0 2006.257.05:37:04.58#ibcon#read 4, iclass 14, count 0 2006.257.05:37:04.58#ibcon#about to read 5, iclass 14, count 0 2006.257.05:37:04.58#ibcon#read 5, iclass 14, count 0 2006.257.05:37:04.58#ibcon#about to read 6, iclass 14, count 0 2006.257.05:37:04.58#ibcon#read 6, iclass 14, count 0 2006.257.05:37:04.58#ibcon#end of sib2, iclass 14, count 0 2006.257.05:37:04.58#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:37:04.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:37:04.58#ibcon#[27=USB\r\n] 2006.257.05:37:04.58#ibcon#*before write, iclass 14, count 0 2006.257.05:37:04.58#ibcon#enter sib2, iclass 14, count 0 2006.257.05:37:04.58#ibcon#flushed, iclass 14, count 0 2006.257.05:37:04.58#ibcon#about to write, iclass 14, count 0 2006.257.05:37:04.58#ibcon#wrote, iclass 14, count 0 2006.257.05:37:04.58#ibcon#about to read 3, iclass 14, count 0 2006.257.05:37:04.61#ibcon#read 3, iclass 14, count 0 2006.257.05:37:04.61#ibcon#about to read 4, iclass 14, count 0 2006.257.05:37:04.61#ibcon#read 4, iclass 14, count 0 2006.257.05:37:04.61#ibcon#about to read 5, iclass 14, count 0 2006.257.05:37:04.61#ibcon#read 5, iclass 14, count 0 2006.257.05:37:04.61#ibcon#about to read 6, iclass 14, count 0 2006.257.05:37:04.61#ibcon#read 6, iclass 14, count 0 2006.257.05:37:04.61#ibcon#end of sib2, iclass 14, count 0 2006.257.05:37:04.61#ibcon#*after write, iclass 14, count 0 2006.257.05:37:04.61#ibcon#*before return 0, iclass 14, count 0 2006.257.05:37:04.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:04.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:37:04.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:37:04.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:37:04.61$vck44/vblo=3,649.99 2006.257.05:37:04.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.05:37:04.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.05:37:04.61#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:04.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:04.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:04.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:04.61#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:37:04.61#ibcon#first serial, iclass 16, count 0 2006.257.05:37:04.61#ibcon#enter sib2, iclass 16, count 0 2006.257.05:37:04.61#ibcon#flushed, iclass 16, count 0 2006.257.05:37:04.61#ibcon#about to write, iclass 16, count 0 2006.257.05:37:04.61#ibcon#wrote, iclass 16, count 0 2006.257.05:37:04.61#ibcon#about to read 3, iclass 16, count 0 2006.257.05:37:04.63#ibcon#read 3, iclass 16, count 0 2006.257.05:37:04.63#ibcon#about to read 4, iclass 16, count 0 2006.257.05:37:04.63#ibcon#read 4, iclass 16, count 0 2006.257.05:37:04.63#ibcon#about to read 5, iclass 16, count 0 2006.257.05:37:04.63#ibcon#read 5, iclass 16, count 0 2006.257.05:37:04.63#ibcon#about to read 6, iclass 16, count 0 2006.257.05:37:04.63#ibcon#read 6, iclass 16, count 0 2006.257.05:37:04.63#ibcon#end of sib2, iclass 16, count 0 2006.257.05:37:04.63#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:37:04.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:37:04.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:37:04.63#ibcon#*before write, iclass 16, count 0 2006.257.05:37:04.63#ibcon#enter sib2, iclass 16, count 0 2006.257.05:37:04.63#ibcon#flushed, iclass 16, count 0 2006.257.05:37:04.63#ibcon#about to write, iclass 16, count 0 2006.257.05:37:04.63#ibcon#wrote, iclass 16, count 0 2006.257.05:37:04.63#ibcon#about to read 3, iclass 16, count 0 2006.257.05:37:04.67#ibcon#read 3, iclass 16, count 0 2006.257.05:37:04.67#ibcon#about to read 4, iclass 16, count 0 2006.257.05:37:04.67#ibcon#read 4, iclass 16, count 0 2006.257.05:37:04.67#ibcon#about to read 5, iclass 16, count 0 2006.257.05:37:04.67#ibcon#read 5, iclass 16, count 0 2006.257.05:37:04.67#ibcon#about to read 6, iclass 16, count 0 2006.257.05:37:04.67#ibcon#read 6, iclass 16, count 0 2006.257.05:37:04.67#ibcon#end of sib2, iclass 16, count 0 2006.257.05:37:04.67#ibcon#*after write, iclass 16, count 0 2006.257.05:37:04.67#ibcon#*before return 0, iclass 16, count 0 2006.257.05:37:04.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:04.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:37:04.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:37:04.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:37:04.67$vck44/vb=3,4 2006.257.05:37:04.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.05:37:04.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.05:37:04.67#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:04.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:04.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:04.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:04.73#ibcon#enter wrdev, iclass 18, count 2 2006.257.05:37:04.73#ibcon#first serial, iclass 18, count 2 2006.257.05:37:04.73#ibcon#enter sib2, iclass 18, count 2 2006.257.05:37:04.73#ibcon#flushed, iclass 18, count 2 2006.257.05:37:04.73#ibcon#about to write, iclass 18, count 2 2006.257.05:37:04.73#ibcon#wrote, iclass 18, count 2 2006.257.05:37:04.73#ibcon#about to read 3, iclass 18, count 2 2006.257.05:37:04.75#ibcon#read 3, iclass 18, count 2 2006.257.05:37:04.75#ibcon#about to read 4, iclass 18, count 2 2006.257.05:37:04.75#ibcon#read 4, iclass 18, count 2 2006.257.05:37:04.75#ibcon#about to read 5, iclass 18, count 2 2006.257.05:37:04.75#ibcon#read 5, iclass 18, count 2 2006.257.05:37:04.75#ibcon#about to read 6, iclass 18, count 2 2006.257.05:37:04.75#ibcon#read 6, iclass 18, count 2 2006.257.05:37:04.75#ibcon#end of sib2, iclass 18, count 2 2006.257.05:37:04.75#ibcon#*mode == 0, iclass 18, count 2 2006.257.05:37:04.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.05:37:04.75#ibcon#[27=AT03-04\r\n] 2006.257.05:37:04.75#ibcon#*before write, iclass 18, count 2 2006.257.05:37:04.75#ibcon#enter sib2, iclass 18, count 2 2006.257.05:37:04.75#ibcon#flushed, iclass 18, count 2 2006.257.05:37:04.75#ibcon#about to write, iclass 18, count 2 2006.257.05:37:04.75#ibcon#wrote, iclass 18, count 2 2006.257.05:37:04.75#ibcon#about to read 3, iclass 18, count 2 2006.257.05:37:04.78#ibcon#read 3, iclass 18, count 2 2006.257.05:37:04.78#ibcon#about to read 4, iclass 18, count 2 2006.257.05:37:04.78#ibcon#read 4, iclass 18, count 2 2006.257.05:37:04.78#ibcon#about to read 5, iclass 18, count 2 2006.257.05:37:04.78#ibcon#read 5, iclass 18, count 2 2006.257.05:37:04.78#ibcon#about to read 6, iclass 18, count 2 2006.257.05:37:04.78#ibcon#read 6, iclass 18, count 2 2006.257.05:37:04.78#ibcon#end of sib2, iclass 18, count 2 2006.257.05:37:04.78#ibcon#*after write, iclass 18, count 2 2006.257.05:37:04.78#ibcon#*before return 0, iclass 18, count 2 2006.257.05:37:04.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:04.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:37:04.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.05:37:04.78#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:04.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:04.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:04.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:04.90#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:37:04.90#ibcon#first serial, iclass 18, count 0 2006.257.05:37:04.90#ibcon#enter sib2, iclass 18, count 0 2006.257.05:37:04.90#ibcon#flushed, iclass 18, count 0 2006.257.05:37:04.90#ibcon#about to write, iclass 18, count 0 2006.257.05:37:04.90#ibcon#wrote, iclass 18, count 0 2006.257.05:37:04.90#ibcon#about to read 3, iclass 18, count 0 2006.257.05:37:04.92#ibcon#read 3, iclass 18, count 0 2006.257.05:37:04.92#ibcon#about to read 4, iclass 18, count 0 2006.257.05:37:04.92#ibcon#read 4, iclass 18, count 0 2006.257.05:37:04.92#ibcon#about to read 5, iclass 18, count 0 2006.257.05:37:04.92#ibcon#read 5, iclass 18, count 0 2006.257.05:37:04.92#ibcon#about to read 6, iclass 18, count 0 2006.257.05:37:04.92#ibcon#read 6, iclass 18, count 0 2006.257.05:37:04.92#ibcon#end of sib2, iclass 18, count 0 2006.257.05:37:04.92#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:37:04.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:37:04.92#ibcon#[27=USB\r\n] 2006.257.05:37:04.92#ibcon#*before write, iclass 18, count 0 2006.257.05:37:04.92#ibcon#enter sib2, iclass 18, count 0 2006.257.05:37:04.92#ibcon#flushed, iclass 18, count 0 2006.257.05:37:04.92#ibcon#about to write, iclass 18, count 0 2006.257.05:37:04.92#ibcon#wrote, iclass 18, count 0 2006.257.05:37:04.92#ibcon#about to read 3, iclass 18, count 0 2006.257.05:37:04.95#ibcon#read 3, iclass 18, count 0 2006.257.05:37:04.95#ibcon#about to read 4, iclass 18, count 0 2006.257.05:37:04.95#ibcon#read 4, iclass 18, count 0 2006.257.05:37:04.95#ibcon#about to read 5, iclass 18, count 0 2006.257.05:37:04.95#ibcon#read 5, iclass 18, count 0 2006.257.05:37:04.95#ibcon#about to read 6, iclass 18, count 0 2006.257.05:37:04.95#ibcon#read 6, iclass 18, count 0 2006.257.05:37:04.95#ibcon#end of sib2, iclass 18, count 0 2006.257.05:37:04.95#ibcon#*after write, iclass 18, count 0 2006.257.05:37:04.95#ibcon#*before return 0, iclass 18, count 0 2006.257.05:37:04.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:04.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:37:04.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:37:04.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:37:04.95$vck44/vblo=4,679.99 2006.257.05:37:04.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.05:37:04.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.05:37:04.95#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:04.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:04.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:04.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:04.95#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:37:04.95#ibcon#first serial, iclass 20, count 0 2006.257.05:37:04.95#ibcon#enter sib2, iclass 20, count 0 2006.257.05:37:04.95#ibcon#flushed, iclass 20, count 0 2006.257.05:37:04.95#ibcon#about to write, iclass 20, count 0 2006.257.05:37:04.95#ibcon#wrote, iclass 20, count 0 2006.257.05:37:04.95#ibcon#about to read 3, iclass 20, count 0 2006.257.05:37:04.97#ibcon#read 3, iclass 20, count 0 2006.257.05:37:04.97#ibcon#about to read 4, iclass 20, count 0 2006.257.05:37:04.97#ibcon#read 4, iclass 20, count 0 2006.257.05:37:04.97#ibcon#about to read 5, iclass 20, count 0 2006.257.05:37:04.97#ibcon#read 5, iclass 20, count 0 2006.257.05:37:04.97#ibcon#about to read 6, iclass 20, count 0 2006.257.05:37:04.97#ibcon#read 6, iclass 20, count 0 2006.257.05:37:04.97#ibcon#end of sib2, iclass 20, count 0 2006.257.05:37:04.97#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:37:04.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:37:04.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:37:04.97#ibcon#*before write, iclass 20, count 0 2006.257.05:37:04.97#ibcon#enter sib2, iclass 20, count 0 2006.257.05:37:04.97#ibcon#flushed, iclass 20, count 0 2006.257.05:37:04.97#ibcon#about to write, iclass 20, count 0 2006.257.05:37:04.97#ibcon#wrote, iclass 20, count 0 2006.257.05:37:04.97#ibcon#about to read 3, iclass 20, count 0 2006.257.05:37:05.01#ibcon#read 3, iclass 20, count 0 2006.257.05:37:05.01#ibcon#about to read 4, iclass 20, count 0 2006.257.05:37:05.01#ibcon#read 4, iclass 20, count 0 2006.257.05:37:05.01#ibcon#about to read 5, iclass 20, count 0 2006.257.05:37:05.01#ibcon#read 5, iclass 20, count 0 2006.257.05:37:05.01#ibcon#about to read 6, iclass 20, count 0 2006.257.05:37:05.01#ibcon#read 6, iclass 20, count 0 2006.257.05:37:05.01#ibcon#end of sib2, iclass 20, count 0 2006.257.05:37:05.01#ibcon#*after write, iclass 20, count 0 2006.257.05:37:05.01#ibcon#*before return 0, iclass 20, count 0 2006.257.05:37:05.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:05.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:37:05.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:37:05.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:37:05.01$vck44/vb=4,5 2006.257.05:37:05.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.05:37:05.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.05:37:05.01#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:05.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:05.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:05.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:05.07#ibcon#enter wrdev, iclass 22, count 2 2006.257.05:37:05.07#ibcon#first serial, iclass 22, count 2 2006.257.05:37:05.07#ibcon#enter sib2, iclass 22, count 2 2006.257.05:37:05.07#ibcon#flushed, iclass 22, count 2 2006.257.05:37:05.07#ibcon#about to write, iclass 22, count 2 2006.257.05:37:05.07#ibcon#wrote, iclass 22, count 2 2006.257.05:37:05.07#ibcon#about to read 3, iclass 22, count 2 2006.257.05:37:05.09#ibcon#read 3, iclass 22, count 2 2006.257.05:37:05.09#ibcon#about to read 4, iclass 22, count 2 2006.257.05:37:05.09#ibcon#read 4, iclass 22, count 2 2006.257.05:37:05.09#ibcon#about to read 5, iclass 22, count 2 2006.257.05:37:05.09#ibcon#read 5, iclass 22, count 2 2006.257.05:37:05.09#ibcon#about to read 6, iclass 22, count 2 2006.257.05:37:05.09#ibcon#read 6, iclass 22, count 2 2006.257.05:37:05.09#ibcon#end of sib2, iclass 22, count 2 2006.257.05:37:05.09#ibcon#*mode == 0, iclass 22, count 2 2006.257.05:37:05.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.05:37:05.09#ibcon#[27=AT04-05\r\n] 2006.257.05:37:05.09#ibcon#*before write, iclass 22, count 2 2006.257.05:37:05.09#ibcon#enter sib2, iclass 22, count 2 2006.257.05:37:05.09#ibcon#flushed, iclass 22, count 2 2006.257.05:37:05.09#ibcon#about to write, iclass 22, count 2 2006.257.05:37:05.09#ibcon#wrote, iclass 22, count 2 2006.257.05:37:05.09#ibcon#about to read 3, iclass 22, count 2 2006.257.05:37:05.12#ibcon#read 3, iclass 22, count 2 2006.257.05:37:05.12#ibcon#about to read 4, iclass 22, count 2 2006.257.05:37:05.12#ibcon#read 4, iclass 22, count 2 2006.257.05:37:05.12#ibcon#about to read 5, iclass 22, count 2 2006.257.05:37:05.12#ibcon#read 5, iclass 22, count 2 2006.257.05:37:05.12#ibcon#about to read 6, iclass 22, count 2 2006.257.05:37:05.12#ibcon#read 6, iclass 22, count 2 2006.257.05:37:05.12#ibcon#end of sib2, iclass 22, count 2 2006.257.05:37:05.12#ibcon#*after write, iclass 22, count 2 2006.257.05:37:05.12#ibcon#*before return 0, iclass 22, count 2 2006.257.05:37:05.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:05.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:37:05.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.05:37:05.12#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:05.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:05.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:05.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:05.24#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:37:05.24#ibcon#first serial, iclass 22, count 0 2006.257.05:37:05.24#ibcon#enter sib2, iclass 22, count 0 2006.257.05:37:05.24#ibcon#flushed, iclass 22, count 0 2006.257.05:37:05.24#ibcon#about to write, iclass 22, count 0 2006.257.05:37:05.24#ibcon#wrote, iclass 22, count 0 2006.257.05:37:05.24#ibcon#about to read 3, iclass 22, count 0 2006.257.05:37:05.26#ibcon#read 3, iclass 22, count 0 2006.257.05:37:05.26#ibcon#about to read 4, iclass 22, count 0 2006.257.05:37:05.26#ibcon#read 4, iclass 22, count 0 2006.257.05:37:05.26#ibcon#about to read 5, iclass 22, count 0 2006.257.05:37:05.26#ibcon#read 5, iclass 22, count 0 2006.257.05:37:05.26#ibcon#about to read 6, iclass 22, count 0 2006.257.05:37:05.26#ibcon#read 6, iclass 22, count 0 2006.257.05:37:05.26#ibcon#end of sib2, iclass 22, count 0 2006.257.05:37:05.26#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:37:05.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:37:05.26#ibcon#[27=USB\r\n] 2006.257.05:37:05.26#ibcon#*before write, iclass 22, count 0 2006.257.05:37:05.26#ibcon#enter sib2, iclass 22, count 0 2006.257.05:37:05.26#ibcon#flushed, iclass 22, count 0 2006.257.05:37:05.26#ibcon#about to write, iclass 22, count 0 2006.257.05:37:05.26#ibcon#wrote, iclass 22, count 0 2006.257.05:37:05.26#ibcon#about to read 3, iclass 22, count 0 2006.257.05:37:05.29#ibcon#read 3, iclass 22, count 0 2006.257.05:37:05.29#ibcon#about to read 4, iclass 22, count 0 2006.257.05:37:05.29#ibcon#read 4, iclass 22, count 0 2006.257.05:37:05.29#ibcon#about to read 5, iclass 22, count 0 2006.257.05:37:05.29#ibcon#read 5, iclass 22, count 0 2006.257.05:37:05.29#ibcon#about to read 6, iclass 22, count 0 2006.257.05:37:05.29#ibcon#read 6, iclass 22, count 0 2006.257.05:37:05.29#ibcon#end of sib2, iclass 22, count 0 2006.257.05:37:05.29#ibcon#*after write, iclass 22, count 0 2006.257.05:37:05.29#ibcon#*before return 0, iclass 22, count 0 2006.257.05:37:05.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:05.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:37:05.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:37:05.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:37:05.29$vck44/vblo=5,709.99 2006.257.05:37:05.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.05:37:05.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.05:37:05.29#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:05.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:05.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:05.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:05.29#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:37:05.29#ibcon#first serial, iclass 24, count 0 2006.257.05:37:05.29#ibcon#enter sib2, iclass 24, count 0 2006.257.05:37:05.29#ibcon#flushed, iclass 24, count 0 2006.257.05:37:05.29#ibcon#about to write, iclass 24, count 0 2006.257.05:37:05.29#ibcon#wrote, iclass 24, count 0 2006.257.05:37:05.29#ibcon#about to read 3, iclass 24, count 0 2006.257.05:37:05.31#ibcon#read 3, iclass 24, count 0 2006.257.05:37:05.31#ibcon#about to read 4, iclass 24, count 0 2006.257.05:37:05.31#ibcon#read 4, iclass 24, count 0 2006.257.05:37:05.31#ibcon#about to read 5, iclass 24, count 0 2006.257.05:37:05.31#ibcon#read 5, iclass 24, count 0 2006.257.05:37:05.31#ibcon#about to read 6, iclass 24, count 0 2006.257.05:37:05.31#ibcon#read 6, iclass 24, count 0 2006.257.05:37:05.31#ibcon#end of sib2, iclass 24, count 0 2006.257.05:37:05.31#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:37:05.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:37:05.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:37:05.31#ibcon#*before write, iclass 24, count 0 2006.257.05:37:05.31#ibcon#enter sib2, iclass 24, count 0 2006.257.05:37:05.31#ibcon#flushed, iclass 24, count 0 2006.257.05:37:05.31#ibcon#about to write, iclass 24, count 0 2006.257.05:37:05.31#ibcon#wrote, iclass 24, count 0 2006.257.05:37:05.31#ibcon#about to read 3, iclass 24, count 0 2006.257.05:37:05.35#ibcon#read 3, iclass 24, count 0 2006.257.05:37:05.35#ibcon#about to read 4, iclass 24, count 0 2006.257.05:37:05.35#ibcon#read 4, iclass 24, count 0 2006.257.05:37:05.35#ibcon#about to read 5, iclass 24, count 0 2006.257.05:37:05.35#ibcon#read 5, iclass 24, count 0 2006.257.05:37:05.35#ibcon#about to read 6, iclass 24, count 0 2006.257.05:37:05.35#ibcon#read 6, iclass 24, count 0 2006.257.05:37:05.35#ibcon#end of sib2, iclass 24, count 0 2006.257.05:37:05.35#ibcon#*after write, iclass 24, count 0 2006.257.05:37:05.35#ibcon#*before return 0, iclass 24, count 0 2006.257.05:37:05.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:05.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:37:05.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:37:05.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:37:05.35$vck44/vb=5,4 2006.257.05:37:05.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.05:37:05.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.05:37:05.35#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:05.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:05.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:05.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:05.41#ibcon#enter wrdev, iclass 26, count 2 2006.257.05:37:05.41#ibcon#first serial, iclass 26, count 2 2006.257.05:37:05.41#ibcon#enter sib2, iclass 26, count 2 2006.257.05:37:05.41#ibcon#flushed, iclass 26, count 2 2006.257.05:37:05.41#ibcon#about to write, iclass 26, count 2 2006.257.05:37:05.41#ibcon#wrote, iclass 26, count 2 2006.257.05:37:05.41#ibcon#about to read 3, iclass 26, count 2 2006.257.05:37:05.43#ibcon#read 3, iclass 26, count 2 2006.257.05:37:05.43#ibcon#about to read 4, iclass 26, count 2 2006.257.05:37:05.43#ibcon#read 4, iclass 26, count 2 2006.257.05:37:05.43#ibcon#about to read 5, iclass 26, count 2 2006.257.05:37:05.43#ibcon#read 5, iclass 26, count 2 2006.257.05:37:05.43#ibcon#about to read 6, iclass 26, count 2 2006.257.05:37:05.43#ibcon#read 6, iclass 26, count 2 2006.257.05:37:05.43#ibcon#end of sib2, iclass 26, count 2 2006.257.05:37:05.43#ibcon#*mode == 0, iclass 26, count 2 2006.257.05:37:05.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.05:37:05.43#ibcon#[27=AT05-04\r\n] 2006.257.05:37:05.43#ibcon#*before write, iclass 26, count 2 2006.257.05:37:05.43#ibcon#enter sib2, iclass 26, count 2 2006.257.05:37:05.43#ibcon#flushed, iclass 26, count 2 2006.257.05:37:05.43#ibcon#about to write, iclass 26, count 2 2006.257.05:37:05.43#ibcon#wrote, iclass 26, count 2 2006.257.05:37:05.43#ibcon#about to read 3, iclass 26, count 2 2006.257.05:37:05.46#ibcon#read 3, iclass 26, count 2 2006.257.05:37:05.46#ibcon#about to read 4, iclass 26, count 2 2006.257.05:37:05.46#ibcon#read 4, iclass 26, count 2 2006.257.05:37:05.46#ibcon#about to read 5, iclass 26, count 2 2006.257.05:37:05.46#ibcon#read 5, iclass 26, count 2 2006.257.05:37:05.46#ibcon#about to read 6, iclass 26, count 2 2006.257.05:37:05.46#ibcon#read 6, iclass 26, count 2 2006.257.05:37:05.46#ibcon#end of sib2, iclass 26, count 2 2006.257.05:37:05.46#ibcon#*after write, iclass 26, count 2 2006.257.05:37:05.46#ibcon#*before return 0, iclass 26, count 2 2006.257.05:37:05.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:05.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:37:05.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.05:37:05.46#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:05.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:05.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:05.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:05.58#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:37:05.58#ibcon#first serial, iclass 26, count 0 2006.257.05:37:05.58#ibcon#enter sib2, iclass 26, count 0 2006.257.05:37:05.58#ibcon#flushed, iclass 26, count 0 2006.257.05:37:05.58#ibcon#about to write, iclass 26, count 0 2006.257.05:37:05.58#ibcon#wrote, iclass 26, count 0 2006.257.05:37:05.58#ibcon#about to read 3, iclass 26, count 0 2006.257.05:37:05.60#ibcon#read 3, iclass 26, count 0 2006.257.05:37:05.60#ibcon#about to read 4, iclass 26, count 0 2006.257.05:37:05.60#ibcon#read 4, iclass 26, count 0 2006.257.05:37:05.60#ibcon#about to read 5, iclass 26, count 0 2006.257.05:37:05.60#ibcon#read 5, iclass 26, count 0 2006.257.05:37:05.60#ibcon#about to read 6, iclass 26, count 0 2006.257.05:37:05.60#ibcon#read 6, iclass 26, count 0 2006.257.05:37:05.60#ibcon#end of sib2, iclass 26, count 0 2006.257.05:37:05.60#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:37:05.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:37:05.60#ibcon#[27=USB\r\n] 2006.257.05:37:05.60#ibcon#*before write, iclass 26, count 0 2006.257.05:37:05.60#ibcon#enter sib2, iclass 26, count 0 2006.257.05:37:05.60#ibcon#flushed, iclass 26, count 0 2006.257.05:37:05.60#ibcon#about to write, iclass 26, count 0 2006.257.05:37:05.60#ibcon#wrote, iclass 26, count 0 2006.257.05:37:05.60#ibcon#about to read 3, iclass 26, count 0 2006.257.05:37:05.63#ibcon#read 3, iclass 26, count 0 2006.257.05:37:05.63#ibcon#about to read 4, iclass 26, count 0 2006.257.05:37:05.63#ibcon#read 4, iclass 26, count 0 2006.257.05:37:05.63#ibcon#about to read 5, iclass 26, count 0 2006.257.05:37:05.63#ibcon#read 5, iclass 26, count 0 2006.257.05:37:05.63#ibcon#about to read 6, iclass 26, count 0 2006.257.05:37:05.63#ibcon#read 6, iclass 26, count 0 2006.257.05:37:05.63#ibcon#end of sib2, iclass 26, count 0 2006.257.05:37:05.63#ibcon#*after write, iclass 26, count 0 2006.257.05:37:05.63#ibcon#*before return 0, iclass 26, count 0 2006.257.05:37:05.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:05.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:37:05.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:37:05.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:37:05.63$vck44/vblo=6,719.99 2006.257.05:37:05.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.05:37:05.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.05:37:05.63#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:05.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:05.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:05.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:05.63#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:37:05.63#ibcon#first serial, iclass 28, count 0 2006.257.05:37:05.63#ibcon#enter sib2, iclass 28, count 0 2006.257.05:37:05.63#ibcon#flushed, iclass 28, count 0 2006.257.05:37:05.63#ibcon#about to write, iclass 28, count 0 2006.257.05:37:05.63#ibcon#wrote, iclass 28, count 0 2006.257.05:37:05.63#ibcon#about to read 3, iclass 28, count 0 2006.257.05:37:05.65#ibcon#read 3, iclass 28, count 0 2006.257.05:37:05.65#ibcon#about to read 4, iclass 28, count 0 2006.257.05:37:05.65#ibcon#read 4, iclass 28, count 0 2006.257.05:37:05.65#ibcon#about to read 5, iclass 28, count 0 2006.257.05:37:05.65#ibcon#read 5, iclass 28, count 0 2006.257.05:37:05.65#ibcon#about to read 6, iclass 28, count 0 2006.257.05:37:05.65#ibcon#read 6, iclass 28, count 0 2006.257.05:37:05.65#ibcon#end of sib2, iclass 28, count 0 2006.257.05:37:05.65#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:37:05.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:37:05.65#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:37:05.65#ibcon#*before write, iclass 28, count 0 2006.257.05:37:05.65#ibcon#enter sib2, iclass 28, count 0 2006.257.05:37:05.65#ibcon#flushed, iclass 28, count 0 2006.257.05:37:05.65#ibcon#about to write, iclass 28, count 0 2006.257.05:37:05.65#ibcon#wrote, iclass 28, count 0 2006.257.05:37:05.65#ibcon#about to read 3, iclass 28, count 0 2006.257.05:37:05.69#ibcon#read 3, iclass 28, count 0 2006.257.05:37:05.69#ibcon#about to read 4, iclass 28, count 0 2006.257.05:37:05.69#ibcon#read 4, iclass 28, count 0 2006.257.05:37:05.69#ibcon#about to read 5, iclass 28, count 0 2006.257.05:37:05.69#ibcon#read 5, iclass 28, count 0 2006.257.05:37:05.69#ibcon#about to read 6, iclass 28, count 0 2006.257.05:37:05.69#ibcon#read 6, iclass 28, count 0 2006.257.05:37:05.69#ibcon#end of sib2, iclass 28, count 0 2006.257.05:37:05.69#ibcon#*after write, iclass 28, count 0 2006.257.05:37:05.69#ibcon#*before return 0, iclass 28, count 0 2006.257.05:37:05.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:05.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:37:05.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:37:05.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:37:05.69$vck44/vb=6,4 2006.257.05:37:05.69#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.05:37:05.69#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.05:37:05.69#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:05.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:05.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:05.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:05.75#ibcon#enter wrdev, iclass 30, count 2 2006.257.05:37:05.75#ibcon#first serial, iclass 30, count 2 2006.257.05:37:05.75#ibcon#enter sib2, iclass 30, count 2 2006.257.05:37:05.75#ibcon#flushed, iclass 30, count 2 2006.257.05:37:05.75#ibcon#about to write, iclass 30, count 2 2006.257.05:37:05.75#ibcon#wrote, iclass 30, count 2 2006.257.05:37:05.75#ibcon#about to read 3, iclass 30, count 2 2006.257.05:37:05.77#ibcon#read 3, iclass 30, count 2 2006.257.05:37:05.77#ibcon#about to read 4, iclass 30, count 2 2006.257.05:37:05.77#ibcon#read 4, iclass 30, count 2 2006.257.05:37:05.77#ibcon#about to read 5, iclass 30, count 2 2006.257.05:37:05.77#ibcon#read 5, iclass 30, count 2 2006.257.05:37:05.77#ibcon#about to read 6, iclass 30, count 2 2006.257.05:37:05.77#ibcon#read 6, iclass 30, count 2 2006.257.05:37:05.77#ibcon#end of sib2, iclass 30, count 2 2006.257.05:37:05.77#ibcon#*mode == 0, iclass 30, count 2 2006.257.05:37:05.77#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.05:37:05.77#ibcon#[27=AT06-04\r\n] 2006.257.05:37:05.77#ibcon#*before write, iclass 30, count 2 2006.257.05:37:05.77#ibcon#enter sib2, iclass 30, count 2 2006.257.05:37:05.77#ibcon#flushed, iclass 30, count 2 2006.257.05:37:05.77#ibcon#about to write, iclass 30, count 2 2006.257.05:37:05.77#ibcon#wrote, iclass 30, count 2 2006.257.05:37:05.77#ibcon#about to read 3, iclass 30, count 2 2006.257.05:37:05.80#ibcon#read 3, iclass 30, count 2 2006.257.05:37:05.80#ibcon#about to read 4, iclass 30, count 2 2006.257.05:37:05.80#ibcon#read 4, iclass 30, count 2 2006.257.05:37:05.80#ibcon#about to read 5, iclass 30, count 2 2006.257.05:37:05.80#ibcon#read 5, iclass 30, count 2 2006.257.05:37:05.80#ibcon#about to read 6, iclass 30, count 2 2006.257.05:37:05.80#ibcon#read 6, iclass 30, count 2 2006.257.05:37:05.80#ibcon#end of sib2, iclass 30, count 2 2006.257.05:37:05.80#ibcon#*after write, iclass 30, count 2 2006.257.05:37:05.80#ibcon#*before return 0, iclass 30, count 2 2006.257.05:37:05.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:05.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:37:05.80#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.05:37:05.80#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:05.80#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:05.92#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:05.92#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:05.92#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:37:05.92#ibcon#first serial, iclass 30, count 0 2006.257.05:37:05.92#ibcon#enter sib2, iclass 30, count 0 2006.257.05:37:05.92#ibcon#flushed, iclass 30, count 0 2006.257.05:37:05.92#ibcon#about to write, iclass 30, count 0 2006.257.05:37:05.92#ibcon#wrote, iclass 30, count 0 2006.257.05:37:05.92#ibcon#about to read 3, iclass 30, count 0 2006.257.05:37:05.94#ibcon#read 3, iclass 30, count 0 2006.257.05:37:05.94#ibcon#about to read 4, iclass 30, count 0 2006.257.05:37:05.94#ibcon#read 4, iclass 30, count 0 2006.257.05:37:05.94#ibcon#about to read 5, iclass 30, count 0 2006.257.05:37:05.94#ibcon#read 5, iclass 30, count 0 2006.257.05:37:05.94#ibcon#about to read 6, iclass 30, count 0 2006.257.05:37:05.94#ibcon#read 6, iclass 30, count 0 2006.257.05:37:05.94#ibcon#end of sib2, iclass 30, count 0 2006.257.05:37:05.94#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:37:05.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:37:05.94#ibcon#[27=USB\r\n] 2006.257.05:37:05.94#ibcon#*before write, iclass 30, count 0 2006.257.05:37:05.94#ibcon#enter sib2, iclass 30, count 0 2006.257.05:37:05.94#ibcon#flushed, iclass 30, count 0 2006.257.05:37:05.94#ibcon#about to write, iclass 30, count 0 2006.257.05:37:05.94#ibcon#wrote, iclass 30, count 0 2006.257.05:37:05.94#ibcon#about to read 3, iclass 30, count 0 2006.257.05:37:05.97#ibcon#read 3, iclass 30, count 0 2006.257.05:37:05.97#ibcon#about to read 4, iclass 30, count 0 2006.257.05:37:05.97#ibcon#read 4, iclass 30, count 0 2006.257.05:37:05.97#ibcon#about to read 5, iclass 30, count 0 2006.257.05:37:05.97#ibcon#read 5, iclass 30, count 0 2006.257.05:37:05.97#ibcon#about to read 6, iclass 30, count 0 2006.257.05:37:05.97#ibcon#read 6, iclass 30, count 0 2006.257.05:37:05.97#ibcon#end of sib2, iclass 30, count 0 2006.257.05:37:05.97#ibcon#*after write, iclass 30, count 0 2006.257.05:37:05.97#ibcon#*before return 0, iclass 30, count 0 2006.257.05:37:05.97#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:05.97#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:37:05.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:37:05.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:37:05.97$vck44/vblo=7,734.99 2006.257.05:37:05.97#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.05:37:05.97#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.05:37:05.97#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:05.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:05.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:05.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:05.97#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:37:05.97#ibcon#first serial, iclass 32, count 0 2006.257.05:37:05.97#ibcon#enter sib2, iclass 32, count 0 2006.257.05:37:05.97#ibcon#flushed, iclass 32, count 0 2006.257.05:37:05.97#ibcon#about to write, iclass 32, count 0 2006.257.05:37:05.97#ibcon#wrote, iclass 32, count 0 2006.257.05:37:05.97#ibcon#about to read 3, iclass 32, count 0 2006.257.05:37:05.99#ibcon#read 3, iclass 32, count 0 2006.257.05:37:05.99#ibcon#about to read 4, iclass 32, count 0 2006.257.05:37:05.99#ibcon#read 4, iclass 32, count 0 2006.257.05:37:05.99#ibcon#about to read 5, iclass 32, count 0 2006.257.05:37:05.99#ibcon#read 5, iclass 32, count 0 2006.257.05:37:05.99#ibcon#about to read 6, iclass 32, count 0 2006.257.05:37:05.99#ibcon#read 6, iclass 32, count 0 2006.257.05:37:05.99#ibcon#end of sib2, iclass 32, count 0 2006.257.05:37:05.99#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:37:05.99#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:37:05.99#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:37:05.99#ibcon#*before write, iclass 32, count 0 2006.257.05:37:05.99#ibcon#enter sib2, iclass 32, count 0 2006.257.05:37:05.99#ibcon#flushed, iclass 32, count 0 2006.257.05:37:05.99#ibcon#about to write, iclass 32, count 0 2006.257.05:37:05.99#ibcon#wrote, iclass 32, count 0 2006.257.05:37:05.99#ibcon#about to read 3, iclass 32, count 0 2006.257.05:37:06.03#ibcon#read 3, iclass 32, count 0 2006.257.05:37:06.03#ibcon#about to read 4, iclass 32, count 0 2006.257.05:37:06.03#ibcon#read 4, iclass 32, count 0 2006.257.05:37:06.03#ibcon#about to read 5, iclass 32, count 0 2006.257.05:37:06.03#ibcon#read 5, iclass 32, count 0 2006.257.05:37:06.03#ibcon#about to read 6, iclass 32, count 0 2006.257.05:37:06.03#ibcon#read 6, iclass 32, count 0 2006.257.05:37:06.03#ibcon#end of sib2, iclass 32, count 0 2006.257.05:37:06.03#ibcon#*after write, iclass 32, count 0 2006.257.05:37:06.03#ibcon#*before return 0, iclass 32, count 0 2006.257.05:37:06.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:06.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:37:06.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:37:06.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:37:06.03$vck44/vb=7,4 2006.257.05:37:06.03#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.05:37:06.03#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.05:37:06.03#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:06.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:06.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:06.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:06.09#ibcon#enter wrdev, iclass 34, count 2 2006.257.05:37:06.09#ibcon#first serial, iclass 34, count 2 2006.257.05:37:06.09#ibcon#enter sib2, iclass 34, count 2 2006.257.05:37:06.09#ibcon#flushed, iclass 34, count 2 2006.257.05:37:06.09#ibcon#about to write, iclass 34, count 2 2006.257.05:37:06.09#ibcon#wrote, iclass 34, count 2 2006.257.05:37:06.09#ibcon#about to read 3, iclass 34, count 2 2006.257.05:37:06.11#ibcon#read 3, iclass 34, count 2 2006.257.05:37:06.11#ibcon#about to read 4, iclass 34, count 2 2006.257.05:37:06.11#ibcon#read 4, iclass 34, count 2 2006.257.05:37:06.11#ibcon#about to read 5, iclass 34, count 2 2006.257.05:37:06.11#ibcon#read 5, iclass 34, count 2 2006.257.05:37:06.11#ibcon#about to read 6, iclass 34, count 2 2006.257.05:37:06.11#ibcon#read 6, iclass 34, count 2 2006.257.05:37:06.11#ibcon#end of sib2, iclass 34, count 2 2006.257.05:37:06.11#ibcon#*mode == 0, iclass 34, count 2 2006.257.05:37:06.11#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.05:37:06.11#ibcon#[27=AT07-04\r\n] 2006.257.05:37:06.11#ibcon#*before write, iclass 34, count 2 2006.257.05:37:06.11#ibcon#enter sib2, iclass 34, count 2 2006.257.05:37:06.11#ibcon#flushed, iclass 34, count 2 2006.257.05:37:06.11#ibcon#about to write, iclass 34, count 2 2006.257.05:37:06.11#ibcon#wrote, iclass 34, count 2 2006.257.05:37:06.11#ibcon#about to read 3, iclass 34, count 2 2006.257.05:37:06.14#ibcon#read 3, iclass 34, count 2 2006.257.05:37:06.14#ibcon#about to read 4, iclass 34, count 2 2006.257.05:37:06.14#ibcon#read 4, iclass 34, count 2 2006.257.05:37:06.14#ibcon#about to read 5, iclass 34, count 2 2006.257.05:37:06.14#ibcon#read 5, iclass 34, count 2 2006.257.05:37:06.14#ibcon#about to read 6, iclass 34, count 2 2006.257.05:37:06.14#ibcon#read 6, iclass 34, count 2 2006.257.05:37:06.14#ibcon#end of sib2, iclass 34, count 2 2006.257.05:37:06.14#ibcon#*after write, iclass 34, count 2 2006.257.05:37:06.14#ibcon#*before return 0, iclass 34, count 2 2006.257.05:37:06.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:06.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:37:06.14#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.05:37:06.14#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:06.14#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:06.26#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:06.26#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:06.26#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:37:06.26#ibcon#first serial, iclass 34, count 0 2006.257.05:37:06.26#ibcon#enter sib2, iclass 34, count 0 2006.257.05:37:06.26#ibcon#flushed, iclass 34, count 0 2006.257.05:37:06.26#ibcon#about to write, iclass 34, count 0 2006.257.05:37:06.26#ibcon#wrote, iclass 34, count 0 2006.257.05:37:06.26#ibcon#about to read 3, iclass 34, count 0 2006.257.05:37:06.28#ibcon#read 3, iclass 34, count 0 2006.257.05:37:06.28#ibcon#about to read 4, iclass 34, count 0 2006.257.05:37:06.28#ibcon#read 4, iclass 34, count 0 2006.257.05:37:06.28#ibcon#about to read 5, iclass 34, count 0 2006.257.05:37:06.28#ibcon#read 5, iclass 34, count 0 2006.257.05:37:06.28#ibcon#about to read 6, iclass 34, count 0 2006.257.05:37:06.28#ibcon#read 6, iclass 34, count 0 2006.257.05:37:06.28#ibcon#end of sib2, iclass 34, count 0 2006.257.05:37:06.28#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:37:06.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:37:06.28#ibcon#[27=USB\r\n] 2006.257.05:37:06.28#ibcon#*before write, iclass 34, count 0 2006.257.05:37:06.28#ibcon#enter sib2, iclass 34, count 0 2006.257.05:37:06.28#ibcon#flushed, iclass 34, count 0 2006.257.05:37:06.28#ibcon#about to write, iclass 34, count 0 2006.257.05:37:06.28#ibcon#wrote, iclass 34, count 0 2006.257.05:37:06.28#ibcon#about to read 3, iclass 34, count 0 2006.257.05:37:06.31#ibcon#read 3, iclass 34, count 0 2006.257.05:37:06.31#ibcon#about to read 4, iclass 34, count 0 2006.257.05:37:06.31#ibcon#read 4, iclass 34, count 0 2006.257.05:37:06.31#ibcon#about to read 5, iclass 34, count 0 2006.257.05:37:06.31#ibcon#read 5, iclass 34, count 0 2006.257.05:37:06.31#ibcon#about to read 6, iclass 34, count 0 2006.257.05:37:06.31#ibcon#read 6, iclass 34, count 0 2006.257.05:37:06.31#ibcon#end of sib2, iclass 34, count 0 2006.257.05:37:06.31#ibcon#*after write, iclass 34, count 0 2006.257.05:37:06.31#ibcon#*before return 0, iclass 34, count 0 2006.257.05:37:06.31#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:06.31#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:37:06.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:37:06.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:37:06.31$vck44/vblo=8,744.99 2006.257.05:37:06.31#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.05:37:06.31#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.05:37:06.31#ibcon#ireg 17 cls_cnt 0 2006.257.05:37:06.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:06.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:06.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:06.31#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:37:06.31#ibcon#first serial, iclass 36, count 0 2006.257.05:37:06.31#ibcon#enter sib2, iclass 36, count 0 2006.257.05:37:06.31#ibcon#flushed, iclass 36, count 0 2006.257.05:37:06.31#ibcon#about to write, iclass 36, count 0 2006.257.05:37:06.31#ibcon#wrote, iclass 36, count 0 2006.257.05:37:06.31#ibcon#about to read 3, iclass 36, count 0 2006.257.05:37:06.33#ibcon#read 3, iclass 36, count 0 2006.257.05:37:06.33#ibcon#about to read 4, iclass 36, count 0 2006.257.05:37:06.33#ibcon#read 4, iclass 36, count 0 2006.257.05:37:06.33#ibcon#about to read 5, iclass 36, count 0 2006.257.05:37:06.33#ibcon#read 5, iclass 36, count 0 2006.257.05:37:06.33#ibcon#about to read 6, iclass 36, count 0 2006.257.05:37:06.33#ibcon#read 6, iclass 36, count 0 2006.257.05:37:06.33#ibcon#end of sib2, iclass 36, count 0 2006.257.05:37:06.33#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:37:06.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:37:06.33#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:37:06.33#ibcon#*before write, iclass 36, count 0 2006.257.05:37:06.33#ibcon#enter sib2, iclass 36, count 0 2006.257.05:37:06.33#ibcon#flushed, iclass 36, count 0 2006.257.05:37:06.33#ibcon#about to write, iclass 36, count 0 2006.257.05:37:06.33#ibcon#wrote, iclass 36, count 0 2006.257.05:37:06.33#ibcon#about to read 3, iclass 36, count 0 2006.257.05:37:06.37#ibcon#read 3, iclass 36, count 0 2006.257.05:37:06.37#ibcon#about to read 4, iclass 36, count 0 2006.257.05:37:06.37#ibcon#read 4, iclass 36, count 0 2006.257.05:37:06.37#ibcon#about to read 5, iclass 36, count 0 2006.257.05:37:06.37#ibcon#read 5, iclass 36, count 0 2006.257.05:37:06.37#ibcon#about to read 6, iclass 36, count 0 2006.257.05:37:06.37#ibcon#read 6, iclass 36, count 0 2006.257.05:37:06.37#ibcon#end of sib2, iclass 36, count 0 2006.257.05:37:06.37#ibcon#*after write, iclass 36, count 0 2006.257.05:37:06.37#ibcon#*before return 0, iclass 36, count 0 2006.257.05:37:06.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:06.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:37:06.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:37:06.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:37:06.37$vck44/vb=8,4 2006.257.05:37:06.37#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.05:37:06.37#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.05:37:06.37#ibcon#ireg 11 cls_cnt 2 2006.257.05:37:06.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:06.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:06.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:06.43#ibcon#enter wrdev, iclass 38, count 2 2006.257.05:37:06.43#ibcon#first serial, iclass 38, count 2 2006.257.05:37:06.43#ibcon#enter sib2, iclass 38, count 2 2006.257.05:37:06.43#ibcon#flushed, iclass 38, count 2 2006.257.05:37:06.43#ibcon#about to write, iclass 38, count 2 2006.257.05:37:06.43#ibcon#wrote, iclass 38, count 2 2006.257.05:37:06.43#ibcon#about to read 3, iclass 38, count 2 2006.257.05:37:06.45#ibcon#read 3, iclass 38, count 2 2006.257.05:37:06.45#ibcon#about to read 4, iclass 38, count 2 2006.257.05:37:06.45#ibcon#read 4, iclass 38, count 2 2006.257.05:37:06.45#ibcon#about to read 5, iclass 38, count 2 2006.257.05:37:06.45#ibcon#read 5, iclass 38, count 2 2006.257.05:37:06.45#ibcon#about to read 6, iclass 38, count 2 2006.257.05:37:06.45#ibcon#read 6, iclass 38, count 2 2006.257.05:37:06.45#ibcon#end of sib2, iclass 38, count 2 2006.257.05:37:06.45#ibcon#*mode == 0, iclass 38, count 2 2006.257.05:37:06.45#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.05:37:06.45#ibcon#[27=AT08-04\r\n] 2006.257.05:37:06.45#ibcon#*before write, iclass 38, count 2 2006.257.05:37:06.45#ibcon#enter sib2, iclass 38, count 2 2006.257.05:37:06.45#ibcon#flushed, iclass 38, count 2 2006.257.05:37:06.45#ibcon#about to write, iclass 38, count 2 2006.257.05:37:06.45#ibcon#wrote, iclass 38, count 2 2006.257.05:37:06.45#ibcon#about to read 3, iclass 38, count 2 2006.257.05:37:06.48#ibcon#read 3, iclass 38, count 2 2006.257.05:37:06.48#ibcon#about to read 4, iclass 38, count 2 2006.257.05:37:06.48#ibcon#read 4, iclass 38, count 2 2006.257.05:37:06.48#ibcon#about to read 5, iclass 38, count 2 2006.257.05:37:06.48#ibcon#read 5, iclass 38, count 2 2006.257.05:37:06.48#ibcon#about to read 6, iclass 38, count 2 2006.257.05:37:06.48#ibcon#read 6, iclass 38, count 2 2006.257.05:37:06.48#ibcon#end of sib2, iclass 38, count 2 2006.257.05:37:06.48#ibcon#*after write, iclass 38, count 2 2006.257.05:37:06.48#ibcon#*before return 0, iclass 38, count 2 2006.257.05:37:06.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:06.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:37:06.48#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.05:37:06.48#ibcon#ireg 7 cls_cnt 0 2006.257.05:37:06.48#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:06.60#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:06.60#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:06.60#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:37:06.60#ibcon#first serial, iclass 38, count 0 2006.257.05:37:06.60#ibcon#enter sib2, iclass 38, count 0 2006.257.05:37:06.60#ibcon#flushed, iclass 38, count 0 2006.257.05:37:06.60#ibcon#about to write, iclass 38, count 0 2006.257.05:37:06.60#ibcon#wrote, iclass 38, count 0 2006.257.05:37:06.60#ibcon#about to read 3, iclass 38, count 0 2006.257.05:37:06.62#ibcon#read 3, iclass 38, count 0 2006.257.05:37:06.62#ibcon#about to read 4, iclass 38, count 0 2006.257.05:37:06.62#ibcon#read 4, iclass 38, count 0 2006.257.05:37:06.62#ibcon#about to read 5, iclass 38, count 0 2006.257.05:37:06.62#ibcon#read 5, iclass 38, count 0 2006.257.05:37:06.62#ibcon#about to read 6, iclass 38, count 0 2006.257.05:37:06.62#ibcon#read 6, iclass 38, count 0 2006.257.05:37:06.62#ibcon#end of sib2, iclass 38, count 0 2006.257.05:37:06.62#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:37:06.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:37:06.62#ibcon#[27=USB\r\n] 2006.257.05:37:06.62#ibcon#*before write, iclass 38, count 0 2006.257.05:37:06.62#ibcon#enter sib2, iclass 38, count 0 2006.257.05:37:06.62#ibcon#flushed, iclass 38, count 0 2006.257.05:37:06.62#ibcon#about to write, iclass 38, count 0 2006.257.05:37:06.62#ibcon#wrote, iclass 38, count 0 2006.257.05:37:06.62#ibcon#about to read 3, iclass 38, count 0 2006.257.05:37:06.65#ibcon#read 3, iclass 38, count 0 2006.257.05:37:06.65#ibcon#about to read 4, iclass 38, count 0 2006.257.05:37:06.65#ibcon#read 4, iclass 38, count 0 2006.257.05:37:06.65#ibcon#about to read 5, iclass 38, count 0 2006.257.05:37:06.65#ibcon#read 5, iclass 38, count 0 2006.257.05:37:06.65#ibcon#about to read 6, iclass 38, count 0 2006.257.05:37:06.65#ibcon#read 6, iclass 38, count 0 2006.257.05:37:06.65#ibcon#end of sib2, iclass 38, count 0 2006.257.05:37:06.65#ibcon#*after write, iclass 38, count 0 2006.257.05:37:06.65#ibcon#*before return 0, iclass 38, count 0 2006.257.05:37:06.65#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:06.65#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:37:06.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:37:06.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:37:06.65$vck44/vabw=wide 2006.257.05:37:06.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.05:37:06.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.05:37:06.65#ibcon#ireg 8 cls_cnt 0 2006.257.05:37:06.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:06.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:06.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:06.65#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:37:06.65#ibcon#first serial, iclass 40, count 0 2006.257.05:37:06.65#ibcon#enter sib2, iclass 40, count 0 2006.257.05:37:06.65#ibcon#flushed, iclass 40, count 0 2006.257.05:37:06.65#ibcon#about to write, iclass 40, count 0 2006.257.05:37:06.65#ibcon#wrote, iclass 40, count 0 2006.257.05:37:06.65#ibcon#about to read 3, iclass 40, count 0 2006.257.05:37:06.67#ibcon#read 3, iclass 40, count 0 2006.257.05:37:06.67#ibcon#about to read 4, iclass 40, count 0 2006.257.05:37:06.67#ibcon#read 4, iclass 40, count 0 2006.257.05:37:06.67#ibcon#about to read 5, iclass 40, count 0 2006.257.05:37:06.67#ibcon#read 5, iclass 40, count 0 2006.257.05:37:06.67#ibcon#about to read 6, iclass 40, count 0 2006.257.05:37:06.67#ibcon#read 6, iclass 40, count 0 2006.257.05:37:06.67#ibcon#end of sib2, iclass 40, count 0 2006.257.05:37:06.67#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:37:06.67#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:37:06.67#ibcon#[25=BW32\r\n] 2006.257.05:37:06.67#ibcon#*before write, iclass 40, count 0 2006.257.05:37:06.67#ibcon#enter sib2, iclass 40, count 0 2006.257.05:37:06.67#ibcon#flushed, iclass 40, count 0 2006.257.05:37:06.67#ibcon#about to write, iclass 40, count 0 2006.257.05:37:06.67#ibcon#wrote, iclass 40, count 0 2006.257.05:37:06.67#ibcon#about to read 3, iclass 40, count 0 2006.257.05:37:06.70#ibcon#read 3, iclass 40, count 0 2006.257.05:37:06.70#ibcon#about to read 4, iclass 40, count 0 2006.257.05:37:06.70#ibcon#read 4, iclass 40, count 0 2006.257.05:37:06.70#ibcon#about to read 5, iclass 40, count 0 2006.257.05:37:06.70#ibcon#read 5, iclass 40, count 0 2006.257.05:37:06.70#ibcon#about to read 6, iclass 40, count 0 2006.257.05:37:06.70#ibcon#read 6, iclass 40, count 0 2006.257.05:37:06.70#ibcon#end of sib2, iclass 40, count 0 2006.257.05:37:06.70#ibcon#*after write, iclass 40, count 0 2006.257.05:37:06.70#ibcon#*before return 0, iclass 40, count 0 2006.257.05:37:06.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:06.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:37:06.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:37:06.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:37:06.70$vck44/vbbw=wide 2006.257.05:37:06.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.05:37:06.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.05:37:06.70#ibcon#ireg 8 cls_cnt 0 2006.257.05:37:06.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:37:06.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:37:06.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:37:06.77#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:37:06.77#ibcon#first serial, iclass 4, count 0 2006.257.05:37:06.77#ibcon#enter sib2, iclass 4, count 0 2006.257.05:37:06.77#ibcon#flushed, iclass 4, count 0 2006.257.05:37:06.77#ibcon#about to write, iclass 4, count 0 2006.257.05:37:06.77#ibcon#wrote, iclass 4, count 0 2006.257.05:37:06.77#ibcon#about to read 3, iclass 4, count 0 2006.257.05:37:06.79#ibcon#read 3, iclass 4, count 0 2006.257.05:37:06.79#ibcon#about to read 4, iclass 4, count 0 2006.257.05:37:06.79#ibcon#read 4, iclass 4, count 0 2006.257.05:37:06.79#ibcon#about to read 5, iclass 4, count 0 2006.257.05:37:06.79#ibcon#read 5, iclass 4, count 0 2006.257.05:37:06.79#ibcon#about to read 6, iclass 4, count 0 2006.257.05:37:06.79#ibcon#read 6, iclass 4, count 0 2006.257.05:37:06.79#ibcon#end of sib2, iclass 4, count 0 2006.257.05:37:06.79#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:37:06.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:37:06.79#ibcon#[27=BW32\r\n] 2006.257.05:37:06.79#ibcon#*before write, iclass 4, count 0 2006.257.05:37:06.79#ibcon#enter sib2, iclass 4, count 0 2006.257.05:37:06.79#ibcon#flushed, iclass 4, count 0 2006.257.05:37:06.79#ibcon#about to write, iclass 4, count 0 2006.257.05:37:06.79#ibcon#wrote, iclass 4, count 0 2006.257.05:37:06.79#ibcon#about to read 3, iclass 4, count 0 2006.257.05:37:06.82#ibcon#read 3, iclass 4, count 0 2006.257.05:37:06.82#ibcon#about to read 4, iclass 4, count 0 2006.257.05:37:06.82#ibcon#read 4, iclass 4, count 0 2006.257.05:37:06.82#ibcon#about to read 5, iclass 4, count 0 2006.257.05:37:06.82#ibcon#read 5, iclass 4, count 0 2006.257.05:37:06.82#ibcon#about to read 6, iclass 4, count 0 2006.257.05:37:06.82#ibcon#read 6, iclass 4, count 0 2006.257.05:37:06.82#ibcon#end of sib2, iclass 4, count 0 2006.257.05:37:06.82#ibcon#*after write, iclass 4, count 0 2006.257.05:37:06.82#ibcon#*before return 0, iclass 4, count 0 2006.257.05:37:06.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:37:06.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:37:06.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:37:06.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:37:06.82$setupk4/ifdk4 2006.257.05:37:06.82$ifdk4/lo= 2006.257.05:37:06.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:37:06.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:37:06.82$ifdk4/patch= 2006.257.05:37:06.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:37:06.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:37:06.82$setupk4/!*+20s 2006.257.05:37:08.25#abcon#<5=/15 1.5 3.4 20.01 901012.2\r\n> 2006.257.05:37:08.27#abcon#{5=INTERFACE CLEAR} 2006.257.05:37:08.33#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:37:18.42#abcon#<5=/15 1.5 3.4 20.01 901012.2\r\n> 2006.257.05:37:18.44#abcon#{5=INTERFACE CLEAR} 2006.257.05:37:18.50#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:37:21.33$setupk4/"tpicd 2006.257.05:37:21.33$setupk4/echo=off 2006.257.05:37:21.33$setupk4/xlog=off 2006.257.05:37:21.33:!2006.257.05:41:44 2006.257.05:37:38.14#trakl#Source acquired 2006.257.05:37:38.14#flagr#flagr/antenna,acquired 2006.257.05:41:44.00:preob 2006.257.05:41:45.14/onsource/TRACKING 2006.257.05:41:45.14:!2006.257.05:41:54 2006.257.05:41:54.00:"tape 2006.257.05:41:54.00:"st=record 2006.257.05:41:54.00:data_valid=on 2006.257.05:41:54.00:midob 2006.257.05:41:54.14/onsource/TRACKING 2006.257.05:41:54.14/wx/20.01,1012.2,89 2006.257.05:41:54.24/cable/+6.4812E-03 2006.257.05:41:55.33/va/01,08,usb,yes,32,34 2006.257.05:41:55.33/va/02,07,usb,yes,34,35 2006.257.05:41:55.33/va/03,08,usb,yes,31,32 2006.257.05:41:55.33/va/04,07,usb,yes,35,37 2006.257.05:41:55.33/va/05,04,usb,yes,32,32 2006.257.05:41:55.33/va/06,04,usb,yes,35,35 2006.257.05:41:55.33/va/07,04,usb,yes,36,37 2006.257.05:41:55.33/va/08,04,usb,yes,30,37 2006.257.05:41:55.56/valo/01,524.99,yes,locked 2006.257.05:41:55.56/valo/02,534.99,yes,locked 2006.257.05:41:55.56/valo/03,564.99,yes,locked 2006.257.05:41:55.56/valo/04,624.99,yes,locked 2006.257.05:41:55.56/valo/05,734.99,yes,locked 2006.257.05:41:55.56/valo/06,814.99,yes,locked 2006.257.05:41:55.56/valo/07,864.99,yes,locked 2006.257.05:41:55.56/valo/08,884.99,yes,locked 2006.257.05:41:56.65/vb/01,04,usb,yes,30,28 2006.257.05:41:56.65/vb/02,05,usb,yes,29,29 2006.257.05:41:56.65/vb/03,04,usb,yes,30,33 2006.257.05:41:56.65/vb/04,05,usb,yes,30,29 2006.257.05:41:56.65/vb/05,04,usb,yes,27,29 2006.257.05:41:56.65/vb/06,04,usb,yes,31,27 2006.257.05:41:56.65/vb/07,04,usb,yes,31,31 2006.257.05:41:56.65/vb/08,04,usb,yes,28,31 2006.257.05:41:56.89/vblo/01,629.99,yes,locked 2006.257.05:41:56.89/vblo/02,634.99,yes,locked 2006.257.05:41:56.89/vblo/03,649.99,yes,locked 2006.257.05:41:56.89/vblo/04,679.99,yes,locked 2006.257.05:41:56.89/vblo/05,709.99,yes,locked 2006.257.05:41:56.89/vblo/06,719.99,yes,locked 2006.257.05:41:56.89/vblo/07,734.99,yes,locked 2006.257.05:41:56.89/vblo/08,744.99,yes,locked 2006.257.05:41:57.04/vabw/8 2006.257.05:41:57.19/vbbw/8 2006.257.05:41:57.28/xfe/off,on,16.7 2006.257.05:41:57.66/ifatt/23,28,28,28 2006.257.05:41:58.08/fmout-gps/S +4.54E-07 2006.257.05:41:58.12:!2006.257.05:45:34 2006.257.05:45:34.00:data_valid=off 2006.257.05:45:34.00:"et 2006.257.05:45:34.00:!+3s 2006.257.05:45:37.01:"tape 2006.257.05:45:37.01:postob 2006.257.05:45:37.24/cable/+6.4809E-03 2006.257.05:45:37.24/wx/20.02,1012.1,89 2006.257.05:45:38.07/fmout-gps/S +4.55E-07 2006.257.05:45:38.07:scan_name=257-0548,jd0609,90 2006.257.05:45:38.07:source=3c274,123049.42,122328.0,2000.0,ccw 2006.257.05:45:39.14#flagr#flagr/antenna,new-source 2006.257.05:45:39.14:checkk5 2006.257.05:45:39.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:45:39.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:45:40.39/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:45:40.78/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:45:41.18/chk_obsdata//k5ts1/T2570541??a.dat file size is correct (nominal:880MB, actual:880MB). 2006.257.05:45:41.58/chk_obsdata//k5ts2/T2570541??b.dat file size is correct (nominal:880MB, actual:880MB). 2006.257.05:45:41.99/chk_obsdata//k5ts3/T2570541??c.dat file size is correct (nominal:880MB, actual:880MB). 2006.257.05:45:42.36/chk_obsdata//k5ts4/T2570541??d.dat file size is correct (nominal:880MB, actual:880MB). 2006.257.05:45:43.09/k5log//k5ts1_log_newline 2006.257.05:45:43.80/k5log//k5ts2_log_newline 2006.257.05:45:44.54/k5log//k5ts3_log_newline 2006.257.05:45:45.25/k5log//k5ts4_log_newline 2006.257.05:45:45.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:45:45.27:setupk4=1 2006.257.05:45:45.27$setupk4/echo=on 2006.257.05:45:45.27$setupk4/pcalon 2006.257.05:45:45.27$pcalon/"no phase cal control is implemented here 2006.257.05:45:45.27$setupk4/"tpicd=stop 2006.257.05:45:45.27$setupk4/"rec=synch_on 2006.257.05:45:45.27$setupk4/"rec_mode=128 2006.257.05:45:45.27$setupk4/!* 2006.257.05:45:45.27$setupk4/recpk4 2006.257.05:45:45.27$recpk4/recpatch= 2006.257.05:45:45.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:45:45.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:45:45.27$setupk4/vck44 2006.257.05:45:45.27$vck44/valo=1,524.99 2006.257.05:45:45.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.05:45:45.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.05:45:45.27#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:45.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:45.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:45.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:45.27#ibcon#enter wrdev, iclass 35, count 0 2006.257.05:45:45.27#ibcon#first serial, iclass 35, count 0 2006.257.05:45:45.27#ibcon#enter sib2, iclass 35, count 0 2006.257.05:45:45.27#ibcon#flushed, iclass 35, count 0 2006.257.05:45:45.27#ibcon#about to write, iclass 35, count 0 2006.257.05:45:45.27#ibcon#wrote, iclass 35, count 0 2006.257.05:45:45.27#ibcon#about to read 3, iclass 35, count 0 2006.257.05:45:45.29#ibcon#read 3, iclass 35, count 0 2006.257.05:45:45.29#ibcon#about to read 4, iclass 35, count 0 2006.257.05:45:45.29#ibcon#read 4, iclass 35, count 0 2006.257.05:45:45.29#ibcon#about to read 5, iclass 35, count 0 2006.257.05:45:45.29#ibcon#read 5, iclass 35, count 0 2006.257.05:45:45.29#ibcon#about to read 6, iclass 35, count 0 2006.257.05:45:45.29#ibcon#read 6, iclass 35, count 0 2006.257.05:45:45.29#ibcon#end of sib2, iclass 35, count 0 2006.257.05:45:45.29#ibcon#*mode == 0, iclass 35, count 0 2006.257.05:45:45.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.05:45:45.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:45:45.29#ibcon#*before write, iclass 35, count 0 2006.257.05:45:45.29#ibcon#enter sib2, iclass 35, count 0 2006.257.05:45:45.29#ibcon#flushed, iclass 35, count 0 2006.257.05:45:45.29#ibcon#about to write, iclass 35, count 0 2006.257.05:45:45.29#ibcon#wrote, iclass 35, count 0 2006.257.05:45:45.29#ibcon#about to read 3, iclass 35, count 0 2006.257.05:45:45.34#ibcon#read 3, iclass 35, count 0 2006.257.05:45:45.34#ibcon#about to read 4, iclass 35, count 0 2006.257.05:45:45.34#ibcon#read 4, iclass 35, count 0 2006.257.05:45:45.34#ibcon#about to read 5, iclass 35, count 0 2006.257.05:45:45.34#ibcon#read 5, iclass 35, count 0 2006.257.05:45:45.34#ibcon#about to read 6, iclass 35, count 0 2006.257.05:45:45.34#ibcon#read 6, iclass 35, count 0 2006.257.05:45:45.34#ibcon#end of sib2, iclass 35, count 0 2006.257.05:45:45.34#ibcon#*after write, iclass 35, count 0 2006.257.05:45:45.34#ibcon#*before return 0, iclass 35, count 0 2006.257.05:45:45.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:45.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:45.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.05:45:45.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.05:45:45.34$vck44/va=1,8 2006.257.05:45:45.34#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.05:45:45.34#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.05:45:45.34#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:45.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:45.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:45.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:45.34#ibcon#enter wrdev, iclass 37, count 2 2006.257.05:45:45.34#ibcon#first serial, iclass 37, count 2 2006.257.05:45:45.34#ibcon#enter sib2, iclass 37, count 2 2006.257.05:45:45.34#ibcon#flushed, iclass 37, count 2 2006.257.05:45:45.34#ibcon#about to write, iclass 37, count 2 2006.257.05:45:45.34#ibcon#wrote, iclass 37, count 2 2006.257.05:45:45.34#ibcon#about to read 3, iclass 37, count 2 2006.257.05:45:45.36#ibcon#read 3, iclass 37, count 2 2006.257.05:45:45.36#ibcon#about to read 4, iclass 37, count 2 2006.257.05:45:45.36#ibcon#read 4, iclass 37, count 2 2006.257.05:45:45.36#ibcon#about to read 5, iclass 37, count 2 2006.257.05:45:45.36#ibcon#read 5, iclass 37, count 2 2006.257.05:45:45.36#ibcon#about to read 6, iclass 37, count 2 2006.257.05:45:45.36#ibcon#read 6, iclass 37, count 2 2006.257.05:45:45.36#ibcon#end of sib2, iclass 37, count 2 2006.257.05:45:45.36#ibcon#*mode == 0, iclass 37, count 2 2006.257.05:45:45.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.05:45:45.36#ibcon#[25=AT01-08\r\n] 2006.257.05:45:45.36#ibcon#*before write, iclass 37, count 2 2006.257.05:45:45.36#ibcon#enter sib2, iclass 37, count 2 2006.257.05:45:45.36#ibcon#flushed, iclass 37, count 2 2006.257.05:45:45.36#ibcon#about to write, iclass 37, count 2 2006.257.05:45:45.36#ibcon#wrote, iclass 37, count 2 2006.257.05:45:45.36#ibcon#about to read 3, iclass 37, count 2 2006.257.05:45:45.39#ibcon#read 3, iclass 37, count 2 2006.257.05:45:45.39#ibcon#about to read 4, iclass 37, count 2 2006.257.05:45:45.39#ibcon#read 4, iclass 37, count 2 2006.257.05:45:45.39#ibcon#about to read 5, iclass 37, count 2 2006.257.05:45:45.39#ibcon#read 5, iclass 37, count 2 2006.257.05:45:45.39#ibcon#about to read 6, iclass 37, count 2 2006.257.05:45:45.39#ibcon#read 6, iclass 37, count 2 2006.257.05:45:45.39#ibcon#end of sib2, iclass 37, count 2 2006.257.05:45:45.39#ibcon#*after write, iclass 37, count 2 2006.257.05:45:45.39#ibcon#*before return 0, iclass 37, count 2 2006.257.05:45:45.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:45.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:45.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.05:45:45.39#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:45.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:45.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:45.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:45.51#ibcon#enter wrdev, iclass 37, count 0 2006.257.05:45:45.51#ibcon#first serial, iclass 37, count 0 2006.257.05:45:45.51#ibcon#enter sib2, iclass 37, count 0 2006.257.05:45:45.51#ibcon#flushed, iclass 37, count 0 2006.257.05:45:45.51#ibcon#about to write, iclass 37, count 0 2006.257.05:45:45.51#ibcon#wrote, iclass 37, count 0 2006.257.05:45:45.51#ibcon#about to read 3, iclass 37, count 0 2006.257.05:45:45.53#ibcon#read 3, iclass 37, count 0 2006.257.05:45:45.53#ibcon#about to read 4, iclass 37, count 0 2006.257.05:45:45.53#ibcon#read 4, iclass 37, count 0 2006.257.05:45:45.53#ibcon#about to read 5, iclass 37, count 0 2006.257.05:45:45.53#ibcon#read 5, iclass 37, count 0 2006.257.05:45:45.53#ibcon#about to read 6, iclass 37, count 0 2006.257.05:45:45.53#ibcon#read 6, iclass 37, count 0 2006.257.05:45:45.53#ibcon#end of sib2, iclass 37, count 0 2006.257.05:45:45.53#ibcon#*mode == 0, iclass 37, count 0 2006.257.05:45:45.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.05:45:45.53#ibcon#[25=USB\r\n] 2006.257.05:45:45.53#ibcon#*before write, iclass 37, count 0 2006.257.05:45:45.53#ibcon#enter sib2, iclass 37, count 0 2006.257.05:45:45.53#ibcon#flushed, iclass 37, count 0 2006.257.05:45:45.53#ibcon#about to write, iclass 37, count 0 2006.257.05:45:45.53#ibcon#wrote, iclass 37, count 0 2006.257.05:45:45.53#ibcon#about to read 3, iclass 37, count 0 2006.257.05:45:45.56#ibcon#read 3, iclass 37, count 0 2006.257.05:45:45.56#ibcon#about to read 4, iclass 37, count 0 2006.257.05:45:45.56#ibcon#read 4, iclass 37, count 0 2006.257.05:45:45.56#ibcon#about to read 5, iclass 37, count 0 2006.257.05:45:45.56#ibcon#read 5, iclass 37, count 0 2006.257.05:45:45.56#ibcon#about to read 6, iclass 37, count 0 2006.257.05:45:45.56#ibcon#read 6, iclass 37, count 0 2006.257.05:45:45.56#ibcon#end of sib2, iclass 37, count 0 2006.257.05:45:45.56#ibcon#*after write, iclass 37, count 0 2006.257.05:45:45.56#ibcon#*before return 0, iclass 37, count 0 2006.257.05:45:45.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:45.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:45.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.05:45:45.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.05:45:45.56$vck44/valo=2,534.99 2006.257.05:45:45.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.05:45:45.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.05:45:45.56#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:45.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:45.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:45.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:45.56#ibcon#enter wrdev, iclass 39, count 0 2006.257.05:45:45.56#ibcon#first serial, iclass 39, count 0 2006.257.05:45:45.56#ibcon#enter sib2, iclass 39, count 0 2006.257.05:45:45.56#ibcon#flushed, iclass 39, count 0 2006.257.05:45:45.56#ibcon#about to write, iclass 39, count 0 2006.257.05:45:45.56#ibcon#wrote, iclass 39, count 0 2006.257.05:45:45.56#ibcon#about to read 3, iclass 39, count 0 2006.257.05:45:45.58#ibcon#read 3, iclass 39, count 0 2006.257.05:45:45.58#ibcon#about to read 4, iclass 39, count 0 2006.257.05:45:45.58#ibcon#read 4, iclass 39, count 0 2006.257.05:45:45.58#ibcon#about to read 5, iclass 39, count 0 2006.257.05:45:45.58#ibcon#read 5, iclass 39, count 0 2006.257.05:45:45.58#ibcon#about to read 6, iclass 39, count 0 2006.257.05:45:45.58#ibcon#read 6, iclass 39, count 0 2006.257.05:45:45.58#ibcon#end of sib2, iclass 39, count 0 2006.257.05:45:45.58#ibcon#*mode == 0, iclass 39, count 0 2006.257.05:45:45.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.05:45:45.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:45:45.58#ibcon#*before write, iclass 39, count 0 2006.257.05:45:45.58#ibcon#enter sib2, iclass 39, count 0 2006.257.05:45:45.58#ibcon#flushed, iclass 39, count 0 2006.257.05:45:45.58#ibcon#about to write, iclass 39, count 0 2006.257.05:45:45.58#ibcon#wrote, iclass 39, count 0 2006.257.05:45:45.58#ibcon#about to read 3, iclass 39, count 0 2006.257.05:45:45.62#ibcon#read 3, iclass 39, count 0 2006.257.05:45:45.62#ibcon#about to read 4, iclass 39, count 0 2006.257.05:45:45.62#ibcon#read 4, iclass 39, count 0 2006.257.05:45:45.62#ibcon#about to read 5, iclass 39, count 0 2006.257.05:45:45.62#ibcon#read 5, iclass 39, count 0 2006.257.05:45:45.62#ibcon#about to read 6, iclass 39, count 0 2006.257.05:45:45.62#ibcon#read 6, iclass 39, count 0 2006.257.05:45:45.62#ibcon#end of sib2, iclass 39, count 0 2006.257.05:45:45.62#ibcon#*after write, iclass 39, count 0 2006.257.05:45:45.62#ibcon#*before return 0, iclass 39, count 0 2006.257.05:45:45.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:45.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:45.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.05:45:45.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.05:45:45.62$vck44/va=2,7 2006.257.05:45:45.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.05:45:45.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.05:45:45.62#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:45.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:45.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:45.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:45.68#ibcon#enter wrdev, iclass 3, count 2 2006.257.05:45:45.68#ibcon#first serial, iclass 3, count 2 2006.257.05:45:45.68#ibcon#enter sib2, iclass 3, count 2 2006.257.05:45:45.68#ibcon#flushed, iclass 3, count 2 2006.257.05:45:45.68#ibcon#about to write, iclass 3, count 2 2006.257.05:45:45.68#ibcon#wrote, iclass 3, count 2 2006.257.05:45:45.68#ibcon#about to read 3, iclass 3, count 2 2006.257.05:45:45.70#ibcon#read 3, iclass 3, count 2 2006.257.05:45:45.70#ibcon#about to read 4, iclass 3, count 2 2006.257.05:45:45.70#ibcon#read 4, iclass 3, count 2 2006.257.05:45:45.70#ibcon#about to read 5, iclass 3, count 2 2006.257.05:45:45.70#ibcon#read 5, iclass 3, count 2 2006.257.05:45:45.70#ibcon#about to read 6, iclass 3, count 2 2006.257.05:45:45.70#ibcon#read 6, iclass 3, count 2 2006.257.05:45:45.70#ibcon#end of sib2, iclass 3, count 2 2006.257.05:45:45.70#ibcon#*mode == 0, iclass 3, count 2 2006.257.05:45:45.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.05:45:45.70#ibcon#[25=AT02-07\r\n] 2006.257.05:45:45.70#ibcon#*before write, iclass 3, count 2 2006.257.05:45:45.70#ibcon#enter sib2, iclass 3, count 2 2006.257.05:45:45.70#ibcon#flushed, iclass 3, count 2 2006.257.05:45:45.70#ibcon#about to write, iclass 3, count 2 2006.257.05:45:45.70#ibcon#wrote, iclass 3, count 2 2006.257.05:45:45.70#ibcon#about to read 3, iclass 3, count 2 2006.257.05:45:45.73#ibcon#read 3, iclass 3, count 2 2006.257.05:45:45.73#ibcon#about to read 4, iclass 3, count 2 2006.257.05:45:45.73#ibcon#read 4, iclass 3, count 2 2006.257.05:45:45.73#ibcon#about to read 5, iclass 3, count 2 2006.257.05:45:45.73#ibcon#read 5, iclass 3, count 2 2006.257.05:45:45.73#ibcon#about to read 6, iclass 3, count 2 2006.257.05:45:45.73#ibcon#read 6, iclass 3, count 2 2006.257.05:45:45.73#ibcon#end of sib2, iclass 3, count 2 2006.257.05:45:45.73#ibcon#*after write, iclass 3, count 2 2006.257.05:45:45.73#ibcon#*before return 0, iclass 3, count 2 2006.257.05:45:45.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:45.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:45.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.05:45:45.73#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:45.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:45.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:45.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:45.85#ibcon#enter wrdev, iclass 3, count 0 2006.257.05:45:45.85#ibcon#first serial, iclass 3, count 0 2006.257.05:45:45.85#ibcon#enter sib2, iclass 3, count 0 2006.257.05:45:45.85#ibcon#flushed, iclass 3, count 0 2006.257.05:45:45.85#ibcon#about to write, iclass 3, count 0 2006.257.05:45:45.85#ibcon#wrote, iclass 3, count 0 2006.257.05:45:45.85#ibcon#about to read 3, iclass 3, count 0 2006.257.05:45:45.87#ibcon#read 3, iclass 3, count 0 2006.257.05:45:45.87#ibcon#about to read 4, iclass 3, count 0 2006.257.05:45:45.87#ibcon#read 4, iclass 3, count 0 2006.257.05:45:45.87#ibcon#about to read 5, iclass 3, count 0 2006.257.05:45:45.87#ibcon#read 5, iclass 3, count 0 2006.257.05:45:45.87#ibcon#about to read 6, iclass 3, count 0 2006.257.05:45:45.87#ibcon#read 6, iclass 3, count 0 2006.257.05:45:45.87#ibcon#end of sib2, iclass 3, count 0 2006.257.05:45:45.87#ibcon#*mode == 0, iclass 3, count 0 2006.257.05:45:45.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.05:45:45.87#ibcon#[25=USB\r\n] 2006.257.05:45:45.87#ibcon#*before write, iclass 3, count 0 2006.257.05:45:45.87#ibcon#enter sib2, iclass 3, count 0 2006.257.05:45:45.87#ibcon#flushed, iclass 3, count 0 2006.257.05:45:45.87#ibcon#about to write, iclass 3, count 0 2006.257.05:45:45.87#ibcon#wrote, iclass 3, count 0 2006.257.05:45:45.87#ibcon#about to read 3, iclass 3, count 0 2006.257.05:45:45.90#ibcon#read 3, iclass 3, count 0 2006.257.05:45:45.90#ibcon#about to read 4, iclass 3, count 0 2006.257.05:45:45.90#ibcon#read 4, iclass 3, count 0 2006.257.05:45:45.90#ibcon#about to read 5, iclass 3, count 0 2006.257.05:45:45.90#ibcon#read 5, iclass 3, count 0 2006.257.05:45:45.90#ibcon#about to read 6, iclass 3, count 0 2006.257.05:45:45.90#ibcon#read 6, iclass 3, count 0 2006.257.05:45:45.90#ibcon#end of sib2, iclass 3, count 0 2006.257.05:45:45.90#ibcon#*after write, iclass 3, count 0 2006.257.05:45:45.90#ibcon#*before return 0, iclass 3, count 0 2006.257.05:45:45.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:45.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:45.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.05:45:45.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.05:45:45.90$vck44/valo=3,564.99 2006.257.05:45:45.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.05:45:45.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.05:45:45.90#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:45.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:45.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:45.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:45.90#ibcon#enter wrdev, iclass 5, count 0 2006.257.05:45:45.90#ibcon#first serial, iclass 5, count 0 2006.257.05:45:45.90#ibcon#enter sib2, iclass 5, count 0 2006.257.05:45:45.90#ibcon#flushed, iclass 5, count 0 2006.257.05:45:45.90#ibcon#about to write, iclass 5, count 0 2006.257.05:45:45.90#ibcon#wrote, iclass 5, count 0 2006.257.05:45:45.90#ibcon#about to read 3, iclass 5, count 0 2006.257.05:45:45.92#ibcon#read 3, iclass 5, count 0 2006.257.05:45:45.92#ibcon#about to read 4, iclass 5, count 0 2006.257.05:45:45.92#ibcon#read 4, iclass 5, count 0 2006.257.05:45:45.92#ibcon#about to read 5, iclass 5, count 0 2006.257.05:45:45.92#ibcon#read 5, iclass 5, count 0 2006.257.05:45:45.92#ibcon#about to read 6, iclass 5, count 0 2006.257.05:45:45.92#ibcon#read 6, iclass 5, count 0 2006.257.05:45:45.92#ibcon#end of sib2, iclass 5, count 0 2006.257.05:45:45.92#ibcon#*mode == 0, iclass 5, count 0 2006.257.05:45:45.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.05:45:45.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:45:45.92#ibcon#*before write, iclass 5, count 0 2006.257.05:45:45.92#ibcon#enter sib2, iclass 5, count 0 2006.257.05:45:45.92#ibcon#flushed, iclass 5, count 0 2006.257.05:45:45.92#ibcon#about to write, iclass 5, count 0 2006.257.05:45:45.92#ibcon#wrote, iclass 5, count 0 2006.257.05:45:45.92#ibcon#about to read 3, iclass 5, count 0 2006.257.05:45:45.96#ibcon#read 3, iclass 5, count 0 2006.257.05:45:45.96#ibcon#about to read 4, iclass 5, count 0 2006.257.05:45:45.96#ibcon#read 4, iclass 5, count 0 2006.257.05:45:45.96#ibcon#about to read 5, iclass 5, count 0 2006.257.05:45:45.96#ibcon#read 5, iclass 5, count 0 2006.257.05:45:45.96#ibcon#about to read 6, iclass 5, count 0 2006.257.05:45:45.96#ibcon#read 6, iclass 5, count 0 2006.257.05:45:45.96#ibcon#end of sib2, iclass 5, count 0 2006.257.05:45:45.96#ibcon#*after write, iclass 5, count 0 2006.257.05:45:45.96#ibcon#*before return 0, iclass 5, count 0 2006.257.05:45:45.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:45.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:45.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.05:45:45.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.05:45:45.96$vck44/va=3,8 2006.257.05:45:45.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.05:45:45.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.05:45:45.96#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:45.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:46.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:46.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:46.02#ibcon#enter wrdev, iclass 7, count 2 2006.257.05:45:46.02#ibcon#first serial, iclass 7, count 2 2006.257.05:45:46.02#ibcon#enter sib2, iclass 7, count 2 2006.257.05:45:46.02#ibcon#flushed, iclass 7, count 2 2006.257.05:45:46.02#ibcon#about to write, iclass 7, count 2 2006.257.05:45:46.02#ibcon#wrote, iclass 7, count 2 2006.257.05:45:46.02#ibcon#about to read 3, iclass 7, count 2 2006.257.05:45:46.04#ibcon#read 3, iclass 7, count 2 2006.257.05:45:46.04#ibcon#about to read 4, iclass 7, count 2 2006.257.05:45:46.04#ibcon#read 4, iclass 7, count 2 2006.257.05:45:46.04#ibcon#about to read 5, iclass 7, count 2 2006.257.05:45:46.04#ibcon#read 5, iclass 7, count 2 2006.257.05:45:46.04#ibcon#about to read 6, iclass 7, count 2 2006.257.05:45:46.04#ibcon#read 6, iclass 7, count 2 2006.257.05:45:46.04#ibcon#end of sib2, iclass 7, count 2 2006.257.05:45:46.04#ibcon#*mode == 0, iclass 7, count 2 2006.257.05:45:46.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.05:45:46.04#ibcon#[25=AT03-08\r\n] 2006.257.05:45:46.04#ibcon#*before write, iclass 7, count 2 2006.257.05:45:46.04#ibcon#enter sib2, iclass 7, count 2 2006.257.05:45:46.04#ibcon#flushed, iclass 7, count 2 2006.257.05:45:46.04#ibcon#about to write, iclass 7, count 2 2006.257.05:45:46.04#ibcon#wrote, iclass 7, count 2 2006.257.05:45:46.04#ibcon#about to read 3, iclass 7, count 2 2006.257.05:45:46.07#ibcon#read 3, iclass 7, count 2 2006.257.05:45:46.07#ibcon#about to read 4, iclass 7, count 2 2006.257.05:45:46.07#ibcon#read 4, iclass 7, count 2 2006.257.05:45:46.07#ibcon#about to read 5, iclass 7, count 2 2006.257.05:45:46.07#ibcon#read 5, iclass 7, count 2 2006.257.05:45:46.07#ibcon#about to read 6, iclass 7, count 2 2006.257.05:45:46.07#ibcon#read 6, iclass 7, count 2 2006.257.05:45:46.07#ibcon#end of sib2, iclass 7, count 2 2006.257.05:45:46.07#ibcon#*after write, iclass 7, count 2 2006.257.05:45:46.07#ibcon#*before return 0, iclass 7, count 2 2006.257.05:45:46.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:46.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:46.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.05:45:46.07#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:46.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:46.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:46.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:46.19#ibcon#enter wrdev, iclass 7, count 0 2006.257.05:45:46.19#ibcon#first serial, iclass 7, count 0 2006.257.05:45:46.19#ibcon#enter sib2, iclass 7, count 0 2006.257.05:45:46.19#ibcon#flushed, iclass 7, count 0 2006.257.05:45:46.19#ibcon#about to write, iclass 7, count 0 2006.257.05:45:46.19#ibcon#wrote, iclass 7, count 0 2006.257.05:45:46.19#ibcon#about to read 3, iclass 7, count 0 2006.257.05:45:46.21#ibcon#read 3, iclass 7, count 0 2006.257.05:45:46.21#ibcon#about to read 4, iclass 7, count 0 2006.257.05:45:46.21#ibcon#read 4, iclass 7, count 0 2006.257.05:45:46.21#ibcon#about to read 5, iclass 7, count 0 2006.257.05:45:46.21#ibcon#read 5, iclass 7, count 0 2006.257.05:45:46.21#ibcon#about to read 6, iclass 7, count 0 2006.257.05:45:46.21#ibcon#read 6, iclass 7, count 0 2006.257.05:45:46.21#ibcon#end of sib2, iclass 7, count 0 2006.257.05:45:46.21#ibcon#*mode == 0, iclass 7, count 0 2006.257.05:45:46.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.05:45:46.21#ibcon#[25=USB\r\n] 2006.257.05:45:46.21#ibcon#*before write, iclass 7, count 0 2006.257.05:45:46.21#ibcon#enter sib2, iclass 7, count 0 2006.257.05:45:46.21#ibcon#flushed, iclass 7, count 0 2006.257.05:45:46.21#ibcon#about to write, iclass 7, count 0 2006.257.05:45:46.21#ibcon#wrote, iclass 7, count 0 2006.257.05:45:46.21#ibcon#about to read 3, iclass 7, count 0 2006.257.05:45:46.24#ibcon#read 3, iclass 7, count 0 2006.257.05:45:46.24#ibcon#about to read 4, iclass 7, count 0 2006.257.05:45:46.24#ibcon#read 4, iclass 7, count 0 2006.257.05:45:46.24#ibcon#about to read 5, iclass 7, count 0 2006.257.05:45:46.24#ibcon#read 5, iclass 7, count 0 2006.257.05:45:46.24#ibcon#about to read 6, iclass 7, count 0 2006.257.05:45:46.24#ibcon#read 6, iclass 7, count 0 2006.257.05:45:46.24#ibcon#end of sib2, iclass 7, count 0 2006.257.05:45:46.24#ibcon#*after write, iclass 7, count 0 2006.257.05:45:46.24#ibcon#*before return 0, iclass 7, count 0 2006.257.05:45:46.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:46.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:46.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.05:45:46.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.05:45:46.24$vck44/valo=4,624.99 2006.257.05:45:46.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.05:45:46.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.05:45:46.24#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:46.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:46.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:46.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:46.24#ibcon#enter wrdev, iclass 11, count 0 2006.257.05:45:46.24#ibcon#first serial, iclass 11, count 0 2006.257.05:45:46.24#ibcon#enter sib2, iclass 11, count 0 2006.257.05:45:46.24#ibcon#flushed, iclass 11, count 0 2006.257.05:45:46.24#ibcon#about to write, iclass 11, count 0 2006.257.05:45:46.24#ibcon#wrote, iclass 11, count 0 2006.257.05:45:46.24#ibcon#about to read 3, iclass 11, count 0 2006.257.05:45:46.26#ibcon#read 3, iclass 11, count 0 2006.257.05:45:46.26#ibcon#about to read 4, iclass 11, count 0 2006.257.05:45:46.26#ibcon#read 4, iclass 11, count 0 2006.257.05:45:46.26#ibcon#about to read 5, iclass 11, count 0 2006.257.05:45:46.26#ibcon#read 5, iclass 11, count 0 2006.257.05:45:46.26#ibcon#about to read 6, iclass 11, count 0 2006.257.05:45:46.26#ibcon#read 6, iclass 11, count 0 2006.257.05:45:46.26#ibcon#end of sib2, iclass 11, count 0 2006.257.05:45:46.26#ibcon#*mode == 0, iclass 11, count 0 2006.257.05:45:46.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.05:45:46.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:45:46.26#ibcon#*before write, iclass 11, count 0 2006.257.05:45:46.26#ibcon#enter sib2, iclass 11, count 0 2006.257.05:45:46.26#ibcon#flushed, iclass 11, count 0 2006.257.05:45:46.26#ibcon#about to write, iclass 11, count 0 2006.257.05:45:46.26#ibcon#wrote, iclass 11, count 0 2006.257.05:45:46.26#ibcon#about to read 3, iclass 11, count 0 2006.257.05:45:46.30#ibcon#read 3, iclass 11, count 0 2006.257.05:45:46.30#ibcon#about to read 4, iclass 11, count 0 2006.257.05:45:46.30#ibcon#read 4, iclass 11, count 0 2006.257.05:45:46.30#ibcon#about to read 5, iclass 11, count 0 2006.257.05:45:46.30#ibcon#read 5, iclass 11, count 0 2006.257.05:45:46.30#ibcon#about to read 6, iclass 11, count 0 2006.257.05:45:46.30#ibcon#read 6, iclass 11, count 0 2006.257.05:45:46.30#ibcon#end of sib2, iclass 11, count 0 2006.257.05:45:46.30#ibcon#*after write, iclass 11, count 0 2006.257.05:45:46.30#ibcon#*before return 0, iclass 11, count 0 2006.257.05:45:46.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:46.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:46.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.05:45:46.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.05:45:46.30$vck44/va=4,7 2006.257.05:45:46.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.05:45:46.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.05:45:46.30#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:46.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:46.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:46.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:46.36#ibcon#enter wrdev, iclass 13, count 2 2006.257.05:45:46.36#ibcon#first serial, iclass 13, count 2 2006.257.05:45:46.36#ibcon#enter sib2, iclass 13, count 2 2006.257.05:45:46.36#ibcon#flushed, iclass 13, count 2 2006.257.05:45:46.36#ibcon#about to write, iclass 13, count 2 2006.257.05:45:46.36#ibcon#wrote, iclass 13, count 2 2006.257.05:45:46.36#ibcon#about to read 3, iclass 13, count 2 2006.257.05:45:46.38#ibcon#read 3, iclass 13, count 2 2006.257.05:45:46.38#ibcon#about to read 4, iclass 13, count 2 2006.257.05:45:46.38#ibcon#read 4, iclass 13, count 2 2006.257.05:45:46.38#ibcon#about to read 5, iclass 13, count 2 2006.257.05:45:46.38#ibcon#read 5, iclass 13, count 2 2006.257.05:45:46.38#ibcon#about to read 6, iclass 13, count 2 2006.257.05:45:46.38#ibcon#read 6, iclass 13, count 2 2006.257.05:45:46.38#ibcon#end of sib2, iclass 13, count 2 2006.257.05:45:46.38#ibcon#*mode == 0, iclass 13, count 2 2006.257.05:45:46.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.05:45:46.38#ibcon#[25=AT04-07\r\n] 2006.257.05:45:46.38#ibcon#*before write, iclass 13, count 2 2006.257.05:45:46.38#ibcon#enter sib2, iclass 13, count 2 2006.257.05:45:46.38#ibcon#flushed, iclass 13, count 2 2006.257.05:45:46.38#ibcon#about to write, iclass 13, count 2 2006.257.05:45:46.38#ibcon#wrote, iclass 13, count 2 2006.257.05:45:46.38#ibcon#about to read 3, iclass 13, count 2 2006.257.05:45:46.41#ibcon#read 3, iclass 13, count 2 2006.257.05:45:46.41#ibcon#about to read 4, iclass 13, count 2 2006.257.05:45:46.41#ibcon#read 4, iclass 13, count 2 2006.257.05:45:46.41#ibcon#about to read 5, iclass 13, count 2 2006.257.05:45:46.41#ibcon#read 5, iclass 13, count 2 2006.257.05:45:46.41#ibcon#about to read 6, iclass 13, count 2 2006.257.05:45:46.41#ibcon#read 6, iclass 13, count 2 2006.257.05:45:46.41#ibcon#end of sib2, iclass 13, count 2 2006.257.05:45:46.41#ibcon#*after write, iclass 13, count 2 2006.257.05:45:46.41#ibcon#*before return 0, iclass 13, count 2 2006.257.05:45:46.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:46.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:46.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.05:45:46.41#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:46.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:46.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:46.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:46.53#ibcon#enter wrdev, iclass 13, count 0 2006.257.05:45:46.53#ibcon#first serial, iclass 13, count 0 2006.257.05:45:46.53#ibcon#enter sib2, iclass 13, count 0 2006.257.05:45:46.53#ibcon#flushed, iclass 13, count 0 2006.257.05:45:46.53#ibcon#about to write, iclass 13, count 0 2006.257.05:45:46.53#ibcon#wrote, iclass 13, count 0 2006.257.05:45:46.53#ibcon#about to read 3, iclass 13, count 0 2006.257.05:45:46.55#ibcon#read 3, iclass 13, count 0 2006.257.05:45:46.55#ibcon#about to read 4, iclass 13, count 0 2006.257.05:45:46.55#ibcon#read 4, iclass 13, count 0 2006.257.05:45:46.55#ibcon#about to read 5, iclass 13, count 0 2006.257.05:45:46.55#ibcon#read 5, iclass 13, count 0 2006.257.05:45:46.55#ibcon#about to read 6, iclass 13, count 0 2006.257.05:45:46.55#ibcon#read 6, iclass 13, count 0 2006.257.05:45:46.55#ibcon#end of sib2, iclass 13, count 0 2006.257.05:45:46.55#ibcon#*mode == 0, iclass 13, count 0 2006.257.05:45:46.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.05:45:46.55#ibcon#[25=USB\r\n] 2006.257.05:45:46.55#ibcon#*before write, iclass 13, count 0 2006.257.05:45:46.55#ibcon#enter sib2, iclass 13, count 0 2006.257.05:45:46.55#ibcon#flushed, iclass 13, count 0 2006.257.05:45:46.55#ibcon#about to write, iclass 13, count 0 2006.257.05:45:46.55#ibcon#wrote, iclass 13, count 0 2006.257.05:45:46.55#ibcon#about to read 3, iclass 13, count 0 2006.257.05:45:46.58#ibcon#read 3, iclass 13, count 0 2006.257.05:45:46.58#ibcon#about to read 4, iclass 13, count 0 2006.257.05:45:46.58#ibcon#read 4, iclass 13, count 0 2006.257.05:45:46.58#ibcon#about to read 5, iclass 13, count 0 2006.257.05:45:46.58#ibcon#read 5, iclass 13, count 0 2006.257.05:45:46.58#ibcon#about to read 6, iclass 13, count 0 2006.257.05:45:46.58#ibcon#read 6, iclass 13, count 0 2006.257.05:45:46.58#ibcon#end of sib2, iclass 13, count 0 2006.257.05:45:46.58#ibcon#*after write, iclass 13, count 0 2006.257.05:45:46.58#ibcon#*before return 0, iclass 13, count 0 2006.257.05:45:46.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:46.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:46.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.05:45:46.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.05:45:46.58$vck44/valo=5,734.99 2006.257.05:45:46.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.05:45:46.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.05:45:46.58#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:46.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:46.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:46.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:46.58#ibcon#enter wrdev, iclass 15, count 0 2006.257.05:45:46.58#ibcon#first serial, iclass 15, count 0 2006.257.05:45:46.58#ibcon#enter sib2, iclass 15, count 0 2006.257.05:45:46.58#ibcon#flushed, iclass 15, count 0 2006.257.05:45:46.58#ibcon#about to write, iclass 15, count 0 2006.257.05:45:46.58#ibcon#wrote, iclass 15, count 0 2006.257.05:45:46.58#ibcon#about to read 3, iclass 15, count 0 2006.257.05:45:46.60#ibcon#read 3, iclass 15, count 0 2006.257.05:45:46.60#ibcon#about to read 4, iclass 15, count 0 2006.257.05:45:46.60#ibcon#read 4, iclass 15, count 0 2006.257.05:45:46.60#ibcon#about to read 5, iclass 15, count 0 2006.257.05:45:46.60#ibcon#read 5, iclass 15, count 0 2006.257.05:45:46.60#ibcon#about to read 6, iclass 15, count 0 2006.257.05:45:46.60#ibcon#read 6, iclass 15, count 0 2006.257.05:45:46.60#ibcon#end of sib2, iclass 15, count 0 2006.257.05:45:46.60#ibcon#*mode == 0, iclass 15, count 0 2006.257.05:45:46.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.05:45:46.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:45:46.60#ibcon#*before write, iclass 15, count 0 2006.257.05:45:46.60#ibcon#enter sib2, iclass 15, count 0 2006.257.05:45:46.60#ibcon#flushed, iclass 15, count 0 2006.257.05:45:46.60#ibcon#about to write, iclass 15, count 0 2006.257.05:45:46.60#ibcon#wrote, iclass 15, count 0 2006.257.05:45:46.60#ibcon#about to read 3, iclass 15, count 0 2006.257.05:45:46.64#ibcon#read 3, iclass 15, count 0 2006.257.05:45:46.64#ibcon#about to read 4, iclass 15, count 0 2006.257.05:45:46.64#ibcon#read 4, iclass 15, count 0 2006.257.05:45:46.64#ibcon#about to read 5, iclass 15, count 0 2006.257.05:45:46.64#ibcon#read 5, iclass 15, count 0 2006.257.05:45:46.64#ibcon#about to read 6, iclass 15, count 0 2006.257.05:45:46.64#ibcon#read 6, iclass 15, count 0 2006.257.05:45:46.64#ibcon#end of sib2, iclass 15, count 0 2006.257.05:45:46.64#ibcon#*after write, iclass 15, count 0 2006.257.05:45:46.64#ibcon#*before return 0, iclass 15, count 0 2006.257.05:45:46.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:46.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:46.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.05:45:46.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.05:45:46.64$vck44/va=5,4 2006.257.05:45:46.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.05:45:46.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.05:45:46.64#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:46.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:46.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:46.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:46.70#ibcon#enter wrdev, iclass 17, count 2 2006.257.05:45:46.70#ibcon#first serial, iclass 17, count 2 2006.257.05:45:46.70#ibcon#enter sib2, iclass 17, count 2 2006.257.05:45:46.70#ibcon#flushed, iclass 17, count 2 2006.257.05:45:46.70#ibcon#about to write, iclass 17, count 2 2006.257.05:45:46.70#ibcon#wrote, iclass 17, count 2 2006.257.05:45:46.70#ibcon#about to read 3, iclass 17, count 2 2006.257.05:45:46.72#ibcon#read 3, iclass 17, count 2 2006.257.05:45:46.72#ibcon#about to read 4, iclass 17, count 2 2006.257.05:45:46.72#ibcon#read 4, iclass 17, count 2 2006.257.05:45:46.72#ibcon#about to read 5, iclass 17, count 2 2006.257.05:45:46.72#ibcon#read 5, iclass 17, count 2 2006.257.05:45:46.72#ibcon#about to read 6, iclass 17, count 2 2006.257.05:45:46.72#ibcon#read 6, iclass 17, count 2 2006.257.05:45:46.72#ibcon#end of sib2, iclass 17, count 2 2006.257.05:45:46.72#ibcon#*mode == 0, iclass 17, count 2 2006.257.05:45:46.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.05:45:46.72#ibcon#[25=AT05-04\r\n] 2006.257.05:45:46.72#ibcon#*before write, iclass 17, count 2 2006.257.05:45:46.72#ibcon#enter sib2, iclass 17, count 2 2006.257.05:45:46.72#ibcon#flushed, iclass 17, count 2 2006.257.05:45:46.72#ibcon#about to write, iclass 17, count 2 2006.257.05:45:46.72#ibcon#wrote, iclass 17, count 2 2006.257.05:45:46.72#ibcon#about to read 3, iclass 17, count 2 2006.257.05:45:46.75#ibcon#read 3, iclass 17, count 2 2006.257.05:45:46.75#ibcon#about to read 4, iclass 17, count 2 2006.257.05:45:46.75#ibcon#read 4, iclass 17, count 2 2006.257.05:45:46.75#ibcon#about to read 5, iclass 17, count 2 2006.257.05:45:46.75#ibcon#read 5, iclass 17, count 2 2006.257.05:45:46.75#ibcon#about to read 6, iclass 17, count 2 2006.257.05:45:46.75#ibcon#read 6, iclass 17, count 2 2006.257.05:45:46.75#ibcon#end of sib2, iclass 17, count 2 2006.257.05:45:46.75#ibcon#*after write, iclass 17, count 2 2006.257.05:45:46.75#ibcon#*before return 0, iclass 17, count 2 2006.257.05:45:46.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:46.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:46.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.05:45:46.75#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:46.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:46.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:46.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:46.87#ibcon#enter wrdev, iclass 17, count 0 2006.257.05:45:46.87#ibcon#first serial, iclass 17, count 0 2006.257.05:45:46.87#ibcon#enter sib2, iclass 17, count 0 2006.257.05:45:46.87#ibcon#flushed, iclass 17, count 0 2006.257.05:45:46.87#ibcon#about to write, iclass 17, count 0 2006.257.05:45:46.87#ibcon#wrote, iclass 17, count 0 2006.257.05:45:46.87#ibcon#about to read 3, iclass 17, count 0 2006.257.05:45:46.89#ibcon#read 3, iclass 17, count 0 2006.257.05:45:46.89#ibcon#about to read 4, iclass 17, count 0 2006.257.05:45:46.89#ibcon#read 4, iclass 17, count 0 2006.257.05:45:46.89#ibcon#about to read 5, iclass 17, count 0 2006.257.05:45:46.89#ibcon#read 5, iclass 17, count 0 2006.257.05:45:46.89#ibcon#about to read 6, iclass 17, count 0 2006.257.05:45:46.89#ibcon#read 6, iclass 17, count 0 2006.257.05:45:46.89#ibcon#end of sib2, iclass 17, count 0 2006.257.05:45:46.89#ibcon#*mode == 0, iclass 17, count 0 2006.257.05:45:46.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.05:45:46.89#ibcon#[25=USB\r\n] 2006.257.05:45:46.89#ibcon#*before write, iclass 17, count 0 2006.257.05:45:46.89#ibcon#enter sib2, iclass 17, count 0 2006.257.05:45:46.89#ibcon#flushed, iclass 17, count 0 2006.257.05:45:46.89#ibcon#about to write, iclass 17, count 0 2006.257.05:45:46.89#ibcon#wrote, iclass 17, count 0 2006.257.05:45:46.89#ibcon#about to read 3, iclass 17, count 0 2006.257.05:45:46.92#ibcon#read 3, iclass 17, count 0 2006.257.05:45:46.92#ibcon#about to read 4, iclass 17, count 0 2006.257.05:45:46.92#ibcon#read 4, iclass 17, count 0 2006.257.05:45:46.92#ibcon#about to read 5, iclass 17, count 0 2006.257.05:45:46.92#ibcon#read 5, iclass 17, count 0 2006.257.05:45:46.92#ibcon#about to read 6, iclass 17, count 0 2006.257.05:45:46.92#ibcon#read 6, iclass 17, count 0 2006.257.05:45:46.92#ibcon#end of sib2, iclass 17, count 0 2006.257.05:45:46.92#ibcon#*after write, iclass 17, count 0 2006.257.05:45:46.92#ibcon#*before return 0, iclass 17, count 0 2006.257.05:45:46.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:46.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:46.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.05:45:46.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.05:45:46.92$vck44/valo=6,814.99 2006.257.05:45:46.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.05:45:46.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.05:45:46.92#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:46.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:46.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:46.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:46.92#ibcon#enter wrdev, iclass 19, count 0 2006.257.05:45:46.92#ibcon#first serial, iclass 19, count 0 2006.257.05:45:46.92#ibcon#enter sib2, iclass 19, count 0 2006.257.05:45:46.92#ibcon#flushed, iclass 19, count 0 2006.257.05:45:46.92#ibcon#about to write, iclass 19, count 0 2006.257.05:45:46.92#ibcon#wrote, iclass 19, count 0 2006.257.05:45:46.92#ibcon#about to read 3, iclass 19, count 0 2006.257.05:45:46.94#ibcon#read 3, iclass 19, count 0 2006.257.05:45:46.94#ibcon#about to read 4, iclass 19, count 0 2006.257.05:45:46.94#ibcon#read 4, iclass 19, count 0 2006.257.05:45:46.94#ibcon#about to read 5, iclass 19, count 0 2006.257.05:45:46.94#ibcon#read 5, iclass 19, count 0 2006.257.05:45:46.94#ibcon#about to read 6, iclass 19, count 0 2006.257.05:45:46.94#ibcon#read 6, iclass 19, count 0 2006.257.05:45:46.94#ibcon#end of sib2, iclass 19, count 0 2006.257.05:45:46.94#ibcon#*mode == 0, iclass 19, count 0 2006.257.05:45:46.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.05:45:46.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:45:46.94#ibcon#*before write, iclass 19, count 0 2006.257.05:45:46.94#ibcon#enter sib2, iclass 19, count 0 2006.257.05:45:46.94#ibcon#flushed, iclass 19, count 0 2006.257.05:45:46.94#ibcon#about to write, iclass 19, count 0 2006.257.05:45:46.94#ibcon#wrote, iclass 19, count 0 2006.257.05:45:46.94#ibcon#about to read 3, iclass 19, count 0 2006.257.05:45:46.98#ibcon#read 3, iclass 19, count 0 2006.257.05:45:46.98#ibcon#about to read 4, iclass 19, count 0 2006.257.05:45:46.98#ibcon#read 4, iclass 19, count 0 2006.257.05:45:46.98#ibcon#about to read 5, iclass 19, count 0 2006.257.05:45:46.98#ibcon#read 5, iclass 19, count 0 2006.257.05:45:46.98#ibcon#about to read 6, iclass 19, count 0 2006.257.05:45:46.98#ibcon#read 6, iclass 19, count 0 2006.257.05:45:46.98#ibcon#end of sib2, iclass 19, count 0 2006.257.05:45:46.98#ibcon#*after write, iclass 19, count 0 2006.257.05:45:46.98#ibcon#*before return 0, iclass 19, count 0 2006.257.05:45:46.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:46.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:46.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.05:45:46.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.05:45:46.98$vck44/va=6,4 2006.257.05:45:46.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.05:45:46.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.05:45:46.98#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:46.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:47.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:47.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:47.04#ibcon#enter wrdev, iclass 21, count 2 2006.257.05:45:47.04#ibcon#first serial, iclass 21, count 2 2006.257.05:45:47.04#ibcon#enter sib2, iclass 21, count 2 2006.257.05:45:47.04#ibcon#flushed, iclass 21, count 2 2006.257.05:45:47.04#ibcon#about to write, iclass 21, count 2 2006.257.05:45:47.04#ibcon#wrote, iclass 21, count 2 2006.257.05:45:47.04#ibcon#about to read 3, iclass 21, count 2 2006.257.05:45:47.06#ibcon#read 3, iclass 21, count 2 2006.257.05:45:47.06#ibcon#about to read 4, iclass 21, count 2 2006.257.05:45:47.06#ibcon#read 4, iclass 21, count 2 2006.257.05:45:47.06#ibcon#about to read 5, iclass 21, count 2 2006.257.05:45:47.06#ibcon#read 5, iclass 21, count 2 2006.257.05:45:47.06#ibcon#about to read 6, iclass 21, count 2 2006.257.05:45:47.06#ibcon#read 6, iclass 21, count 2 2006.257.05:45:47.06#ibcon#end of sib2, iclass 21, count 2 2006.257.05:45:47.06#ibcon#*mode == 0, iclass 21, count 2 2006.257.05:45:47.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.05:45:47.06#ibcon#[25=AT06-04\r\n] 2006.257.05:45:47.06#ibcon#*before write, iclass 21, count 2 2006.257.05:45:47.06#ibcon#enter sib2, iclass 21, count 2 2006.257.05:45:47.06#ibcon#flushed, iclass 21, count 2 2006.257.05:45:47.06#ibcon#about to write, iclass 21, count 2 2006.257.05:45:47.06#ibcon#wrote, iclass 21, count 2 2006.257.05:45:47.06#ibcon#about to read 3, iclass 21, count 2 2006.257.05:45:47.09#ibcon#read 3, iclass 21, count 2 2006.257.05:45:47.09#ibcon#about to read 4, iclass 21, count 2 2006.257.05:45:47.09#ibcon#read 4, iclass 21, count 2 2006.257.05:45:47.09#ibcon#about to read 5, iclass 21, count 2 2006.257.05:45:47.09#ibcon#read 5, iclass 21, count 2 2006.257.05:45:47.09#ibcon#about to read 6, iclass 21, count 2 2006.257.05:45:47.09#ibcon#read 6, iclass 21, count 2 2006.257.05:45:47.09#ibcon#end of sib2, iclass 21, count 2 2006.257.05:45:47.09#ibcon#*after write, iclass 21, count 2 2006.257.05:45:47.09#ibcon#*before return 0, iclass 21, count 2 2006.257.05:45:47.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:47.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:47.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.05:45:47.09#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:47.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:47.15#abcon#<5=/16 1.7 6.2 20.03 881012.1\r\n> 2006.257.05:45:47.17#abcon#{5=INTERFACE CLEAR} 2006.257.05:45:47.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:47.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:47.21#ibcon#enter wrdev, iclass 21, count 0 2006.257.05:45:47.21#ibcon#first serial, iclass 21, count 0 2006.257.05:45:47.21#ibcon#enter sib2, iclass 21, count 0 2006.257.05:45:47.21#ibcon#flushed, iclass 21, count 0 2006.257.05:45:47.21#ibcon#about to write, iclass 21, count 0 2006.257.05:45:47.21#ibcon#wrote, iclass 21, count 0 2006.257.05:45:47.21#ibcon#about to read 3, iclass 21, count 0 2006.257.05:45:47.23#ibcon#read 3, iclass 21, count 0 2006.257.05:45:47.23#ibcon#about to read 4, iclass 21, count 0 2006.257.05:45:47.23#ibcon#read 4, iclass 21, count 0 2006.257.05:45:47.23#ibcon#about to read 5, iclass 21, count 0 2006.257.05:45:47.23#ibcon#read 5, iclass 21, count 0 2006.257.05:45:47.23#ibcon#about to read 6, iclass 21, count 0 2006.257.05:45:47.23#ibcon#read 6, iclass 21, count 0 2006.257.05:45:47.23#ibcon#end of sib2, iclass 21, count 0 2006.257.05:45:47.23#ibcon#*mode == 0, iclass 21, count 0 2006.257.05:45:47.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.05:45:47.23#ibcon#[25=USB\r\n] 2006.257.05:45:47.23#ibcon#*before write, iclass 21, count 0 2006.257.05:45:47.23#ibcon#enter sib2, iclass 21, count 0 2006.257.05:45:47.23#ibcon#flushed, iclass 21, count 0 2006.257.05:45:47.23#ibcon#about to write, iclass 21, count 0 2006.257.05:45:47.23#ibcon#wrote, iclass 21, count 0 2006.257.05:45:47.23#ibcon#about to read 3, iclass 21, count 0 2006.257.05:45:47.23#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:45:47.26#ibcon#read 3, iclass 21, count 0 2006.257.05:45:47.26#ibcon#about to read 4, iclass 21, count 0 2006.257.05:45:47.26#ibcon#read 4, iclass 21, count 0 2006.257.05:45:47.26#ibcon#about to read 5, iclass 21, count 0 2006.257.05:45:47.26#ibcon#read 5, iclass 21, count 0 2006.257.05:45:47.26#ibcon#about to read 6, iclass 21, count 0 2006.257.05:45:47.26#ibcon#read 6, iclass 21, count 0 2006.257.05:45:47.26#ibcon#end of sib2, iclass 21, count 0 2006.257.05:45:47.26#ibcon#*after write, iclass 21, count 0 2006.257.05:45:47.26#ibcon#*before return 0, iclass 21, count 0 2006.257.05:45:47.26#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:47.26#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:47.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.05:45:47.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.05:45:47.26$vck44/valo=7,864.99 2006.257.05:45:47.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.05:45:47.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.05:45:47.26#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:47.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:47.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:47.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:47.26#ibcon#enter wrdev, iclass 27, count 0 2006.257.05:45:47.26#ibcon#first serial, iclass 27, count 0 2006.257.05:45:47.26#ibcon#enter sib2, iclass 27, count 0 2006.257.05:45:47.26#ibcon#flushed, iclass 27, count 0 2006.257.05:45:47.26#ibcon#about to write, iclass 27, count 0 2006.257.05:45:47.26#ibcon#wrote, iclass 27, count 0 2006.257.05:45:47.26#ibcon#about to read 3, iclass 27, count 0 2006.257.05:45:47.28#ibcon#read 3, iclass 27, count 0 2006.257.05:45:47.28#ibcon#about to read 4, iclass 27, count 0 2006.257.05:45:47.28#ibcon#read 4, iclass 27, count 0 2006.257.05:45:47.28#ibcon#about to read 5, iclass 27, count 0 2006.257.05:45:47.28#ibcon#read 5, iclass 27, count 0 2006.257.05:45:47.28#ibcon#about to read 6, iclass 27, count 0 2006.257.05:45:47.28#ibcon#read 6, iclass 27, count 0 2006.257.05:45:47.28#ibcon#end of sib2, iclass 27, count 0 2006.257.05:45:47.28#ibcon#*mode == 0, iclass 27, count 0 2006.257.05:45:47.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.05:45:47.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:45:47.28#ibcon#*before write, iclass 27, count 0 2006.257.05:45:47.28#ibcon#enter sib2, iclass 27, count 0 2006.257.05:45:47.28#ibcon#flushed, iclass 27, count 0 2006.257.05:45:47.28#ibcon#about to write, iclass 27, count 0 2006.257.05:45:47.28#ibcon#wrote, iclass 27, count 0 2006.257.05:45:47.28#ibcon#about to read 3, iclass 27, count 0 2006.257.05:45:47.32#ibcon#read 3, iclass 27, count 0 2006.257.05:45:47.32#ibcon#about to read 4, iclass 27, count 0 2006.257.05:45:47.32#ibcon#read 4, iclass 27, count 0 2006.257.05:45:47.32#ibcon#about to read 5, iclass 27, count 0 2006.257.05:45:47.32#ibcon#read 5, iclass 27, count 0 2006.257.05:45:47.32#ibcon#about to read 6, iclass 27, count 0 2006.257.05:45:47.32#ibcon#read 6, iclass 27, count 0 2006.257.05:45:47.32#ibcon#end of sib2, iclass 27, count 0 2006.257.05:45:47.32#ibcon#*after write, iclass 27, count 0 2006.257.05:45:47.32#ibcon#*before return 0, iclass 27, count 0 2006.257.05:45:47.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:47.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:47.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.05:45:47.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.05:45:47.32$vck44/va=7,4 2006.257.05:45:47.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.05:45:47.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.05:45:47.32#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:47.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:47.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:47.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:47.38#ibcon#enter wrdev, iclass 29, count 2 2006.257.05:45:47.38#ibcon#first serial, iclass 29, count 2 2006.257.05:45:47.38#ibcon#enter sib2, iclass 29, count 2 2006.257.05:45:47.38#ibcon#flushed, iclass 29, count 2 2006.257.05:45:47.38#ibcon#about to write, iclass 29, count 2 2006.257.05:45:47.38#ibcon#wrote, iclass 29, count 2 2006.257.05:45:47.38#ibcon#about to read 3, iclass 29, count 2 2006.257.05:45:47.40#ibcon#read 3, iclass 29, count 2 2006.257.05:45:47.40#ibcon#about to read 4, iclass 29, count 2 2006.257.05:45:47.40#ibcon#read 4, iclass 29, count 2 2006.257.05:45:47.40#ibcon#about to read 5, iclass 29, count 2 2006.257.05:45:47.40#ibcon#read 5, iclass 29, count 2 2006.257.05:45:47.40#ibcon#about to read 6, iclass 29, count 2 2006.257.05:45:47.40#ibcon#read 6, iclass 29, count 2 2006.257.05:45:47.40#ibcon#end of sib2, iclass 29, count 2 2006.257.05:45:47.40#ibcon#*mode == 0, iclass 29, count 2 2006.257.05:45:47.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.05:45:47.40#ibcon#[25=AT07-04\r\n] 2006.257.05:45:47.40#ibcon#*before write, iclass 29, count 2 2006.257.05:45:47.40#ibcon#enter sib2, iclass 29, count 2 2006.257.05:45:47.40#ibcon#flushed, iclass 29, count 2 2006.257.05:45:47.40#ibcon#about to write, iclass 29, count 2 2006.257.05:45:47.40#ibcon#wrote, iclass 29, count 2 2006.257.05:45:47.40#ibcon#about to read 3, iclass 29, count 2 2006.257.05:45:47.43#ibcon#read 3, iclass 29, count 2 2006.257.05:45:47.43#ibcon#about to read 4, iclass 29, count 2 2006.257.05:45:47.43#ibcon#read 4, iclass 29, count 2 2006.257.05:45:47.43#ibcon#about to read 5, iclass 29, count 2 2006.257.05:45:47.43#ibcon#read 5, iclass 29, count 2 2006.257.05:45:47.43#ibcon#about to read 6, iclass 29, count 2 2006.257.05:45:47.43#ibcon#read 6, iclass 29, count 2 2006.257.05:45:47.43#ibcon#end of sib2, iclass 29, count 2 2006.257.05:45:47.43#ibcon#*after write, iclass 29, count 2 2006.257.05:45:47.43#ibcon#*before return 0, iclass 29, count 2 2006.257.05:45:47.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:47.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:47.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.05:45:47.43#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:47.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:47.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:47.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:47.55#ibcon#enter wrdev, iclass 29, count 0 2006.257.05:45:47.55#ibcon#first serial, iclass 29, count 0 2006.257.05:45:47.55#ibcon#enter sib2, iclass 29, count 0 2006.257.05:45:47.55#ibcon#flushed, iclass 29, count 0 2006.257.05:45:47.55#ibcon#about to write, iclass 29, count 0 2006.257.05:45:47.55#ibcon#wrote, iclass 29, count 0 2006.257.05:45:47.55#ibcon#about to read 3, iclass 29, count 0 2006.257.05:45:47.57#ibcon#read 3, iclass 29, count 0 2006.257.05:45:47.57#ibcon#about to read 4, iclass 29, count 0 2006.257.05:45:47.57#ibcon#read 4, iclass 29, count 0 2006.257.05:45:47.57#ibcon#about to read 5, iclass 29, count 0 2006.257.05:45:47.57#ibcon#read 5, iclass 29, count 0 2006.257.05:45:47.57#ibcon#about to read 6, iclass 29, count 0 2006.257.05:45:47.57#ibcon#read 6, iclass 29, count 0 2006.257.05:45:47.57#ibcon#end of sib2, iclass 29, count 0 2006.257.05:45:47.57#ibcon#*mode == 0, iclass 29, count 0 2006.257.05:45:47.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.05:45:47.57#ibcon#[25=USB\r\n] 2006.257.05:45:47.57#ibcon#*before write, iclass 29, count 0 2006.257.05:45:47.57#ibcon#enter sib2, iclass 29, count 0 2006.257.05:45:47.57#ibcon#flushed, iclass 29, count 0 2006.257.05:45:47.57#ibcon#about to write, iclass 29, count 0 2006.257.05:45:47.57#ibcon#wrote, iclass 29, count 0 2006.257.05:45:47.57#ibcon#about to read 3, iclass 29, count 0 2006.257.05:45:47.60#ibcon#read 3, iclass 29, count 0 2006.257.05:45:47.60#ibcon#about to read 4, iclass 29, count 0 2006.257.05:45:47.60#ibcon#read 4, iclass 29, count 0 2006.257.05:45:47.60#ibcon#about to read 5, iclass 29, count 0 2006.257.05:45:47.60#ibcon#read 5, iclass 29, count 0 2006.257.05:45:47.60#ibcon#about to read 6, iclass 29, count 0 2006.257.05:45:47.60#ibcon#read 6, iclass 29, count 0 2006.257.05:45:47.60#ibcon#end of sib2, iclass 29, count 0 2006.257.05:45:47.60#ibcon#*after write, iclass 29, count 0 2006.257.05:45:47.60#ibcon#*before return 0, iclass 29, count 0 2006.257.05:45:47.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:47.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:47.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.05:45:47.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.05:45:47.60$vck44/valo=8,884.99 2006.257.05:45:47.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.05:45:47.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.05:45:47.60#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:47.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:47.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:47.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:47.60#ibcon#enter wrdev, iclass 31, count 0 2006.257.05:45:47.60#ibcon#first serial, iclass 31, count 0 2006.257.05:45:47.60#ibcon#enter sib2, iclass 31, count 0 2006.257.05:45:47.60#ibcon#flushed, iclass 31, count 0 2006.257.05:45:47.60#ibcon#about to write, iclass 31, count 0 2006.257.05:45:47.60#ibcon#wrote, iclass 31, count 0 2006.257.05:45:47.60#ibcon#about to read 3, iclass 31, count 0 2006.257.05:45:47.62#ibcon#read 3, iclass 31, count 0 2006.257.05:45:47.62#ibcon#about to read 4, iclass 31, count 0 2006.257.05:45:47.62#ibcon#read 4, iclass 31, count 0 2006.257.05:45:47.62#ibcon#about to read 5, iclass 31, count 0 2006.257.05:45:47.62#ibcon#read 5, iclass 31, count 0 2006.257.05:45:47.62#ibcon#about to read 6, iclass 31, count 0 2006.257.05:45:47.62#ibcon#read 6, iclass 31, count 0 2006.257.05:45:47.62#ibcon#end of sib2, iclass 31, count 0 2006.257.05:45:47.62#ibcon#*mode == 0, iclass 31, count 0 2006.257.05:45:47.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.05:45:47.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:45:47.62#ibcon#*before write, iclass 31, count 0 2006.257.05:45:47.62#ibcon#enter sib2, iclass 31, count 0 2006.257.05:45:47.62#ibcon#flushed, iclass 31, count 0 2006.257.05:45:47.62#ibcon#about to write, iclass 31, count 0 2006.257.05:45:47.62#ibcon#wrote, iclass 31, count 0 2006.257.05:45:47.62#ibcon#about to read 3, iclass 31, count 0 2006.257.05:45:47.66#ibcon#read 3, iclass 31, count 0 2006.257.05:45:47.66#ibcon#about to read 4, iclass 31, count 0 2006.257.05:45:47.66#ibcon#read 4, iclass 31, count 0 2006.257.05:45:47.66#ibcon#about to read 5, iclass 31, count 0 2006.257.05:45:47.66#ibcon#read 5, iclass 31, count 0 2006.257.05:45:47.66#ibcon#about to read 6, iclass 31, count 0 2006.257.05:45:47.66#ibcon#read 6, iclass 31, count 0 2006.257.05:45:47.66#ibcon#end of sib2, iclass 31, count 0 2006.257.05:45:47.66#ibcon#*after write, iclass 31, count 0 2006.257.05:45:47.66#ibcon#*before return 0, iclass 31, count 0 2006.257.05:45:47.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:47.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:47.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.05:45:47.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.05:45:47.66$vck44/va=8,4 2006.257.05:45:47.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.05:45:47.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.05:45:47.66#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:47.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:45:47.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:45:47.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:45:47.72#ibcon#enter wrdev, iclass 33, count 2 2006.257.05:45:47.72#ibcon#first serial, iclass 33, count 2 2006.257.05:45:47.72#ibcon#enter sib2, iclass 33, count 2 2006.257.05:45:47.72#ibcon#flushed, iclass 33, count 2 2006.257.05:45:47.72#ibcon#about to write, iclass 33, count 2 2006.257.05:45:47.72#ibcon#wrote, iclass 33, count 2 2006.257.05:45:47.72#ibcon#about to read 3, iclass 33, count 2 2006.257.05:45:47.74#ibcon#read 3, iclass 33, count 2 2006.257.05:45:47.74#ibcon#about to read 4, iclass 33, count 2 2006.257.05:45:47.74#ibcon#read 4, iclass 33, count 2 2006.257.05:45:47.74#ibcon#about to read 5, iclass 33, count 2 2006.257.05:45:47.74#ibcon#read 5, iclass 33, count 2 2006.257.05:45:47.74#ibcon#about to read 6, iclass 33, count 2 2006.257.05:45:47.74#ibcon#read 6, iclass 33, count 2 2006.257.05:45:47.74#ibcon#end of sib2, iclass 33, count 2 2006.257.05:45:47.74#ibcon#*mode == 0, iclass 33, count 2 2006.257.05:45:47.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.05:45:47.74#ibcon#[25=AT08-04\r\n] 2006.257.05:45:47.74#ibcon#*before write, iclass 33, count 2 2006.257.05:45:47.74#ibcon#enter sib2, iclass 33, count 2 2006.257.05:45:47.74#ibcon#flushed, iclass 33, count 2 2006.257.05:45:47.74#ibcon#about to write, iclass 33, count 2 2006.257.05:45:47.74#ibcon#wrote, iclass 33, count 2 2006.257.05:45:47.74#ibcon#about to read 3, iclass 33, count 2 2006.257.05:45:47.77#ibcon#read 3, iclass 33, count 2 2006.257.05:45:47.77#ibcon#about to read 4, iclass 33, count 2 2006.257.05:45:47.77#ibcon#read 4, iclass 33, count 2 2006.257.05:45:47.77#ibcon#about to read 5, iclass 33, count 2 2006.257.05:45:47.77#ibcon#read 5, iclass 33, count 2 2006.257.05:45:47.77#ibcon#about to read 6, iclass 33, count 2 2006.257.05:45:47.77#ibcon#read 6, iclass 33, count 2 2006.257.05:45:47.77#ibcon#end of sib2, iclass 33, count 2 2006.257.05:45:47.77#ibcon#*after write, iclass 33, count 2 2006.257.05:45:47.77#ibcon#*before return 0, iclass 33, count 2 2006.257.05:45:47.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:45:47.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.05:45:47.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.05:45:47.77#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:47.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:45:47.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:45:47.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:45:47.89#ibcon#enter wrdev, iclass 33, count 0 2006.257.05:45:47.89#ibcon#first serial, iclass 33, count 0 2006.257.05:45:47.89#ibcon#enter sib2, iclass 33, count 0 2006.257.05:45:47.89#ibcon#flushed, iclass 33, count 0 2006.257.05:45:47.89#ibcon#about to write, iclass 33, count 0 2006.257.05:45:47.89#ibcon#wrote, iclass 33, count 0 2006.257.05:45:47.89#ibcon#about to read 3, iclass 33, count 0 2006.257.05:45:47.91#ibcon#read 3, iclass 33, count 0 2006.257.05:45:47.91#ibcon#about to read 4, iclass 33, count 0 2006.257.05:45:47.91#ibcon#read 4, iclass 33, count 0 2006.257.05:45:47.91#ibcon#about to read 5, iclass 33, count 0 2006.257.05:45:47.91#ibcon#read 5, iclass 33, count 0 2006.257.05:45:47.91#ibcon#about to read 6, iclass 33, count 0 2006.257.05:45:47.91#ibcon#read 6, iclass 33, count 0 2006.257.05:45:47.91#ibcon#end of sib2, iclass 33, count 0 2006.257.05:45:47.91#ibcon#*mode == 0, iclass 33, count 0 2006.257.05:45:47.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.05:45:47.91#ibcon#[25=USB\r\n] 2006.257.05:45:47.91#ibcon#*before write, iclass 33, count 0 2006.257.05:45:47.91#ibcon#enter sib2, iclass 33, count 0 2006.257.05:45:47.91#ibcon#flushed, iclass 33, count 0 2006.257.05:45:47.91#ibcon#about to write, iclass 33, count 0 2006.257.05:45:47.91#ibcon#wrote, iclass 33, count 0 2006.257.05:45:47.91#ibcon#about to read 3, iclass 33, count 0 2006.257.05:45:47.94#ibcon#read 3, iclass 33, count 0 2006.257.05:45:47.94#ibcon#about to read 4, iclass 33, count 0 2006.257.05:45:47.94#ibcon#read 4, iclass 33, count 0 2006.257.05:45:47.94#ibcon#about to read 5, iclass 33, count 0 2006.257.05:45:47.94#ibcon#read 5, iclass 33, count 0 2006.257.05:45:47.94#ibcon#about to read 6, iclass 33, count 0 2006.257.05:45:47.94#ibcon#read 6, iclass 33, count 0 2006.257.05:45:47.94#ibcon#end of sib2, iclass 33, count 0 2006.257.05:45:47.94#ibcon#*after write, iclass 33, count 0 2006.257.05:45:47.94#ibcon#*before return 0, iclass 33, count 0 2006.257.05:45:47.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:45:47.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.05:45:47.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.05:45:47.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.05:45:47.94$vck44/vblo=1,629.99 2006.257.05:45:47.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.05:45:47.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.05:45:47.94#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:47.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:47.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:47.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:47.94#ibcon#enter wrdev, iclass 35, count 0 2006.257.05:45:47.94#ibcon#first serial, iclass 35, count 0 2006.257.05:45:47.94#ibcon#enter sib2, iclass 35, count 0 2006.257.05:45:47.94#ibcon#flushed, iclass 35, count 0 2006.257.05:45:47.94#ibcon#about to write, iclass 35, count 0 2006.257.05:45:47.94#ibcon#wrote, iclass 35, count 0 2006.257.05:45:47.94#ibcon#about to read 3, iclass 35, count 0 2006.257.05:45:47.96#ibcon#read 3, iclass 35, count 0 2006.257.05:45:47.96#ibcon#about to read 4, iclass 35, count 0 2006.257.05:45:47.96#ibcon#read 4, iclass 35, count 0 2006.257.05:45:47.96#ibcon#about to read 5, iclass 35, count 0 2006.257.05:45:47.96#ibcon#read 5, iclass 35, count 0 2006.257.05:45:47.96#ibcon#about to read 6, iclass 35, count 0 2006.257.05:45:47.96#ibcon#read 6, iclass 35, count 0 2006.257.05:45:47.96#ibcon#end of sib2, iclass 35, count 0 2006.257.05:45:47.96#ibcon#*mode == 0, iclass 35, count 0 2006.257.05:45:47.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.05:45:47.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:45:47.96#ibcon#*before write, iclass 35, count 0 2006.257.05:45:47.96#ibcon#enter sib2, iclass 35, count 0 2006.257.05:45:47.96#ibcon#flushed, iclass 35, count 0 2006.257.05:45:47.96#ibcon#about to write, iclass 35, count 0 2006.257.05:45:47.96#ibcon#wrote, iclass 35, count 0 2006.257.05:45:47.96#ibcon#about to read 3, iclass 35, count 0 2006.257.05:45:48.00#ibcon#read 3, iclass 35, count 0 2006.257.05:45:48.00#ibcon#about to read 4, iclass 35, count 0 2006.257.05:45:48.00#ibcon#read 4, iclass 35, count 0 2006.257.05:45:48.00#ibcon#about to read 5, iclass 35, count 0 2006.257.05:45:48.00#ibcon#read 5, iclass 35, count 0 2006.257.05:45:48.00#ibcon#about to read 6, iclass 35, count 0 2006.257.05:45:48.00#ibcon#read 6, iclass 35, count 0 2006.257.05:45:48.00#ibcon#end of sib2, iclass 35, count 0 2006.257.05:45:48.00#ibcon#*after write, iclass 35, count 0 2006.257.05:45:48.00#ibcon#*before return 0, iclass 35, count 0 2006.257.05:45:48.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:48.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.05:45:48.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.05:45:48.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.05:45:48.00$vck44/vb=1,4 2006.257.05:45:48.00#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.05:45:48.00#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.05:45:48.00#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:48.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:48.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:48.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:48.00#ibcon#enter wrdev, iclass 37, count 2 2006.257.05:45:48.00#ibcon#first serial, iclass 37, count 2 2006.257.05:45:48.00#ibcon#enter sib2, iclass 37, count 2 2006.257.05:45:48.00#ibcon#flushed, iclass 37, count 2 2006.257.05:45:48.00#ibcon#about to write, iclass 37, count 2 2006.257.05:45:48.00#ibcon#wrote, iclass 37, count 2 2006.257.05:45:48.00#ibcon#about to read 3, iclass 37, count 2 2006.257.05:45:48.02#ibcon#read 3, iclass 37, count 2 2006.257.05:45:48.02#ibcon#about to read 4, iclass 37, count 2 2006.257.05:45:48.02#ibcon#read 4, iclass 37, count 2 2006.257.05:45:48.02#ibcon#about to read 5, iclass 37, count 2 2006.257.05:45:48.02#ibcon#read 5, iclass 37, count 2 2006.257.05:45:48.02#ibcon#about to read 6, iclass 37, count 2 2006.257.05:45:48.02#ibcon#read 6, iclass 37, count 2 2006.257.05:45:48.02#ibcon#end of sib2, iclass 37, count 2 2006.257.05:45:48.02#ibcon#*mode == 0, iclass 37, count 2 2006.257.05:45:48.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.05:45:48.02#ibcon#[27=AT01-04\r\n] 2006.257.05:45:48.02#ibcon#*before write, iclass 37, count 2 2006.257.05:45:48.02#ibcon#enter sib2, iclass 37, count 2 2006.257.05:45:48.02#ibcon#flushed, iclass 37, count 2 2006.257.05:45:48.02#ibcon#about to write, iclass 37, count 2 2006.257.05:45:48.02#ibcon#wrote, iclass 37, count 2 2006.257.05:45:48.02#ibcon#about to read 3, iclass 37, count 2 2006.257.05:45:48.05#ibcon#read 3, iclass 37, count 2 2006.257.05:45:48.05#ibcon#about to read 4, iclass 37, count 2 2006.257.05:45:48.05#ibcon#read 4, iclass 37, count 2 2006.257.05:45:48.05#ibcon#about to read 5, iclass 37, count 2 2006.257.05:45:48.05#ibcon#read 5, iclass 37, count 2 2006.257.05:45:48.05#ibcon#about to read 6, iclass 37, count 2 2006.257.05:45:48.05#ibcon#read 6, iclass 37, count 2 2006.257.05:45:48.05#ibcon#end of sib2, iclass 37, count 2 2006.257.05:45:48.05#ibcon#*after write, iclass 37, count 2 2006.257.05:45:48.05#ibcon#*before return 0, iclass 37, count 2 2006.257.05:45:48.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:48.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.05:45:48.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.05:45:48.05#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:48.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:48.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:48.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:48.17#ibcon#enter wrdev, iclass 37, count 0 2006.257.05:45:48.17#ibcon#first serial, iclass 37, count 0 2006.257.05:45:48.17#ibcon#enter sib2, iclass 37, count 0 2006.257.05:45:48.17#ibcon#flushed, iclass 37, count 0 2006.257.05:45:48.17#ibcon#about to write, iclass 37, count 0 2006.257.05:45:48.17#ibcon#wrote, iclass 37, count 0 2006.257.05:45:48.17#ibcon#about to read 3, iclass 37, count 0 2006.257.05:45:48.19#ibcon#read 3, iclass 37, count 0 2006.257.05:45:48.19#ibcon#about to read 4, iclass 37, count 0 2006.257.05:45:48.19#ibcon#read 4, iclass 37, count 0 2006.257.05:45:48.19#ibcon#about to read 5, iclass 37, count 0 2006.257.05:45:48.19#ibcon#read 5, iclass 37, count 0 2006.257.05:45:48.19#ibcon#about to read 6, iclass 37, count 0 2006.257.05:45:48.19#ibcon#read 6, iclass 37, count 0 2006.257.05:45:48.19#ibcon#end of sib2, iclass 37, count 0 2006.257.05:45:48.19#ibcon#*mode == 0, iclass 37, count 0 2006.257.05:45:48.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.05:45:48.19#ibcon#[27=USB\r\n] 2006.257.05:45:48.19#ibcon#*before write, iclass 37, count 0 2006.257.05:45:48.19#ibcon#enter sib2, iclass 37, count 0 2006.257.05:45:48.19#ibcon#flushed, iclass 37, count 0 2006.257.05:45:48.19#ibcon#about to write, iclass 37, count 0 2006.257.05:45:48.19#ibcon#wrote, iclass 37, count 0 2006.257.05:45:48.19#ibcon#about to read 3, iclass 37, count 0 2006.257.05:45:48.22#ibcon#read 3, iclass 37, count 0 2006.257.05:45:48.22#ibcon#about to read 4, iclass 37, count 0 2006.257.05:45:48.22#ibcon#read 4, iclass 37, count 0 2006.257.05:45:48.22#ibcon#about to read 5, iclass 37, count 0 2006.257.05:45:48.22#ibcon#read 5, iclass 37, count 0 2006.257.05:45:48.22#ibcon#about to read 6, iclass 37, count 0 2006.257.05:45:48.22#ibcon#read 6, iclass 37, count 0 2006.257.05:45:48.22#ibcon#end of sib2, iclass 37, count 0 2006.257.05:45:48.22#ibcon#*after write, iclass 37, count 0 2006.257.05:45:48.22#ibcon#*before return 0, iclass 37, count 0 2006.257.05:45:48.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:48.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.05:45:48.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.05:45:48.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.05:45:48.22$vck44/vblo=2,634.99 2006.257.05:45:48.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.05:45:48.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.05:45:48.22#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:48.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:48.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:48.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:48.22#ibcon#enter wrdev, iclass 39, count 0 2006.257.05:45:48.22#ibcon#first serial, iclass 39, count 0 2006.257.05:45:48.22#ibcon#enter sib2, iclass 39, count 0 2006.257.05:45:48.22#ibcon#flushed, iclass 39, count 0 2006.257.05:45:48.22#ibcon#about to write, iclass 39, count 0 2006.257.05:45:48.22#ibcon#wrote, iclass 39, count 0 2006.257.05:45:48.22#ibcon#about to read 3, iclass 39, count 0 2006.257.05:45:48.24#ibcon#read 3, iclass 39, count 0 2006.257.05:45:48.24#ibcon#about to read 4, iclass 39, count 0 2006.257.05:45:48.24#ibcon#read 4, iclass 39, count 0 2006.257.05:45:48.24#ibcon#about to read 5, iclass 39, count 0 2006.257.05:45:48.24#ibcon#read 5, iclass 39, count 0 2006.257.05:45:48.24#ibcon#about to read 6, iclass 39, count 0 2006.257.05:45:48.24#ibcon#read 6, iclass 39, count 0 2006.257.05:45:48.24#ibcon#end of sib2, iclass 39, count 0 2006.257.05:45:48.24#ibcon#*mode == 0, iclass 39, count 0 2006.257.05:45:48.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.05:45:48.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:45:48.24#ibcon#*before write, iclass 39, count 0 2006.257.05:45:48.24#ibcon#enter sib2, iclass 39, count 0 2006.257.05:45:48.24#ibcon#flushed, iclass 39, count 0 2006.257.05:45:48.24#ibcon#about to write, iclass 39, count 0 2006.257.05:45:48.24#ibcon#wrote, iclass 39, count 0 2006.257.05:45:48.24#ibcon#about to read 3, iclass 39, count 0 2006.257.05:45:48.28#ibcon#read 3, iclass 39, count 0 2006.257.05:45:48.28#ibcon#about to read 4, iclass 39, count 0 2006.257.05:45:48.28#ibcon#read 4, iclass 39, count 0 2006.257.05:45:48.28#ibcon#about to read 5, iclass 39, count 0 2006.257.05:45:48.28#ibcon#read 5, iclass 39, count 0 2006.257.05:45:48.28#ibcon#about to read 6, iclass 39, count 0 2006.257.05:45:48.28#ibcon#read 6, iclass 39, count 0 2006.257.05:45:48.28#ibcon#end of sib2, iclass 39, count 0 2006.257.05:45:48.28#ibcon#*after write, iclass 39, count 0 2006.257.05:45:48.28#ibcon#*before return 0, iclass 39, count 0 2006.257.05:45:48.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:48.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.05:45:48.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.05:45:48.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.05:45:48.28$vck44/vb=2,5 2006.257.05:45:48.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.05:45:48.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.05:45:48.28#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:48.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:48.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:48.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:48.34#ibcon#enter wrdev, iclass 3, count 2 2006.257.05:45:48.34#ibcon#first serial, iclass 3, count 2 2006.257.05:45:48.34#ibcon#enter sib2, iclass 3, count 2 2006.257.05:45:48.34#ibcon#flushed, iclass 3, count 2 2006.257.05:45:48.34#ibcon#about to write, iclass 3, count 2 2006.257.05:45:48.34#ibcon#wrote, iclass 3, count 2 2006.257.05:45:48.34#ibcon#about to read 3, iclass 3, count 2 2006.257.05:45:48.36#ibcon#read 3, iclass 3, count 2 2006.257.05:45:48.36#ibcon#about to read 4, iclass 3, count 2 2006.257.05:45:48.36#ibcon#read 4, iclass 3, count 2 2006.257.05:45:48.36#ibcon#about to read 5, iclass 3, count 2 2006.257.05:45:48.36#ibcon#read 5, iclass 3, count 2 2006.257.05:45:48.36#ibcon#about to read 6, iclass 3, count 2 2006.257.05:45:48.36#ibcon#read 6, iclass 3, count 2 2006.257.05:45:48.36#ibcon#end of sib2, iclass 3, count 2 2006.257.05:45:48.36#ibcon#*mode == 0, iclass 3, count 2 2006.257.05:45:48.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.05:45:48.36#ibcon#[27=AT02-05\r\n] 2006.257.05:45:48.36#ibcon#*before write, iclass 3, count 2 2006.257.05:45:48.36#ibcon#enter sib2, iclass 3, count 2 2006.257.05:45:48.36#ibcon#flushed, iclass 3, count 2 2006.257.05:45:48.36#ibcon#about to write, iclass 3, count 2 2006.257.05:45:48.36#ibcon#wrote, iclass 3, count 2 2006.257.05:45:48.36#ibcon#about to read 3, iclass 3, count 2 2006.257.05:45:48.39#ibcon#read 3, iclass 3, count 2 2006.257.05:45:48.39#ibcon#about to read 4, iclass 3, count 2 2006.257.05:45:48.39#ibcon#read 4, iclass 3, count 2 2006.257.05:45:48.39#ibcon#about to read 5, iclass 3, count 2 2006.257.05:45:48.39#ibcon#read 5, iclass 3, count 2 2006.257.05:45:48.39#ibcon#about to read 6, iclass 3, count 2 2006.257.05:45:48.39#ibcon#read 6, iclass 3, count 2 2006.257.05:45:48.39#ibcon#end of sib2, iclass 3, count 2 2006.257.05:45:48.39#ibcon#*after write, iclass 3, count 2 2006.257.05:45:48.39#ibcon#*before return 0, iclass 3, count 2 2006.257.05:45:48.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:48.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.05:45:48.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.05:45:48.39#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:48.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:48.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:48.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:48.51#ibcon#enter wrdev, iclass 3, count 0 2006.257.05:45:48.51#ibcon#first serial, iclass 3, count 0 2006.257.05:45:48.51#ibcon#enter sib2, iclass 3, count 0 2006.257.05:45:48.51#ibcon#flushed, iclass 3, count 0 2006.257.05:45:48.51#ibcon#about to write, iclass 3, count 0 2006.257.05:45:48.51#ibcon#wrote, iclass 3, count 0 2006.257.05:45:48.51#ibcon#about to read 3, iclass 3, count 0 2006.257.05:45:48.53#ibcon#read 3, iclass 3, count 0 2006.257.05:45:48.53#ibcon#about to read 4, iclass 3, count 0 2006.257.05:45:48.53#ibcon#read 4, iclass 3, count 0 2006.257.05:45:48.53#ibcon#about to read 5, iclass 3, count 0 2006.257.05:45:48.53#ibcon#read 5, iclass 3, count 0 2006.257.05:45:48.53#ibcon#about to read 6, iclass 3, count 0 2006.257.05:45:48.53#ibcon#read 6, iclass 3, count 0 2006.257.05:45:48.53#ibcon#end of sib2, iclass 3, count 0 2006.257.05:45:48.53#ibcon#*mode == 0, iclass 3, count 0 2006.257.05:45:48.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.05:45:48.53#ibcon#[27=USB\r\n] 2006.257.05:45:48.53#ibcon#*before write, iclass 3, count 0 2006.257.05:45:48.53#ibcon#enter sib2, iclass 3, count 0 2006.257.05:45:48.53#ibcon#flushed, iclass 3, count 0 2006.257.05:45:48.53#ibcon#about to write, iclass 3, count 0 2006.257.05:45:48.53#ibcon#wrote, iclass 3, count 0 2006.257.05:45:48.53#ibcon#about to read 3, iclass 3, count 0 2006.257.05:45:48.56#ibcon#read 3, iclass 3, count 0 2006.257.05:45:48.56#ibcon#about to read 4, iclass 3, count 0 2006.257.05:45:48.56#ibcon#read 4, iclass 3, count 0 2006.257.05:45:48.56#ibcon#about to read 5, iclass 3, count 0 2006.257.05:45:48.56#ibcon#read 5, iclass 3, count 0 2006.257.05:45:48.56#ibcon#about to read 6, iclass 3, count 0 2006.257.05:45:48.56#ibcon#read 6, iclass 3, count 0 2006.257.05:45:48.56#ibcon#end of sib2, iclass 3, count 0 2006.257.05:45:48.56#ibcon#*after write, iclass 3, count 0 2006.257.05:45:48.56#ibcon#*before return 0, iclass 3, count 0 2006.257.05:45:48.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:48.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.05:45:48.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.05:45:48.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.05:45:48.56$vck44/vblo=3,649.99 2006.257.05:45:48.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.05:45:48.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.05:45:48.56#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:48.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:48.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:48.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:48.56#ibcon#enter wrdev, iclass 5, count 0 2006.257.05:45:48.56#ibcon#first serial, iclass 5, count 0 2006.257.05:45:48.56#ibcon#enter sib2, iclass 5, count 0 2006.257.05:45:48.56#ibcon#flushed, iclass 5, count 0 2006.257.05:45:48.56#ibcon#about to write, iclass 5, count 0 2006.257.05:45:48.56#ibcon#wrote, iclass 5, count 0 2006.257.05:45:48.56#ibcon#about to read 3, iclass 5, count 0 2006.257.05:45:48.58#ibcon#read 3, iclass 5, count 0 2006.257.05:45:48.58#ibcon#about to read 4, iclass 5, count 0 2006.257.05:45:48.58#ibcon#read 4, iclass 5, count 0 2006.257.05:45:48.58#ibcon#about to read 5, iclass 5, count 0 2006.257.05:45:48.58#ibcon#read 5, iclass 5, count 0 2006.257.05:45:48.58#ibcon#about to read 6, iclass 5, count 0 2006.257.05:45:48.58#ibcon#read 6, iclass 5, count 0 2006.257.05:45:48.58#ibcon#end of sib2, iclass 5, count 0 2006.257.05:45:48.58#ibcon#*mode == 0, iclass 5, count 0 2006.257.05:45:48.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.05:45:48.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:45:48.58#ibcon#*before write, iclass 5, count 0 2006.257.05:45:48.58#ibcon#enter sib2, iclass 5, count 0 2006.257.05:45:48.58#ibcon#flushed, iclass 5, count 0 2006.257.05:45:48.58#ibcon#about to write, iclass 5, count 0 2006.257.05:45:48.58#ibcon#wrote, iclass 5, count 0 2006.257.05:45:48.58#ibcon#about to read 3, iclass 5, count 0 2006.257.05:45:48.62#ibcon#read 3, iclass 5, count 0 2006.257.05:45:48.62#ibcon#about to read 4, iclass 5, count 0 2006.257.05:45:48.62#ibcon#read 4, iclass 5, count 0 2006.257.05:45:48.62#ibcon#about to read 5, iclass 5, count 0 2006.257.05:45:48.62#ibcon#read 5, iclass 5, count 0 2006.257.05:45:48.62#ibcon#about to read 6, iclass 5, count 0 2006.257.05:45:48.62#ibcon#read 6, iclass 5, count 0 2006.257.05:45:48.62#ibcon#end of sib2, iclass 5, count 0 2006.257.05:45:48.62#ibcon#*after write, iclass 5, count 0 2006.257.05:45:48.62#ibcon#*before return 0, iclass 5, count 0 2006.257.05:45:48.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:48.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.05:45:48.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.05:45:48.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.05:45:48.62$vck44/vb=3,4 2006.257.05:45:48.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.05:45:48.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.05:45:48.62#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:48.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:48.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:48.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:48.68#ibcon#enter wrdev, iclass 7, count 2 2006.257.05:45:48.68#ibcon#first serial, iclass 7, count 2 2006.257.05:45:48.68#ibcon#enter sib2, iclass 7, count 2 2006.257.05:45:48.68#ibcon#flushed, iclass 7, count 2 2006.257.05:45:48.68#ibcon#about to write, iclass 7, count 2 2006.257.05:45:48.68#ibcon#wrote, iclass 7, count 2 2006.257.05:45:48.68#ibcon#about to read 3, iclass 7, count 2 2006.257.05:45:48.70#ibcon#read 3, iclass 7, count 2 2006.257.05:45:48.70#ibcon#about to read 4, iclass 7, count 2 2006.257.05:45:48.70#ibcon#read 4, iclass 7, count 2 2006.257.05:45:48.70#ibcon#about to read 5, iclass 7, count 2 2006.257.05:45:48.70#ibcon#read 5, iclass 7, count 2 2006.257.05:45:48.70#ibcon#about to read 6, iclass 7, count 2 2006.257.05:45:48.70#ibcon#read 6, iclass 7, count 2 2006.257.05:45:48.70#ibcon#end of sib2, iclass 7, count 2 2006.257.05:45:48.70#ibcon#*mode == 0, iclass 7, count 2 2006.257.05:45:48.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.05:45:48.70#ibcon#[27=AT03-04\r\n] 2006.257.05:45:48.70#ibcon#*before write, iclass 7, count 2 2006.257.05:45:48.70#ibcon#enter sib2, iclass 7, count 2 2006.257.05:45:48.70#ibcon#flushed, iclass 7, count 2 2006.257.05:45:48.70#ibcon#about to write, iclass 7, count 2 2006.257.05:45:48.70#ibcon#wrote, iclass 7, count 2 2006.257.05:45:48.70#ibcon#about to read 3, iclass 7, count 2 2006.257.05:45:48.73#ibcon#read 3, iclass 7, count 2 2006.257.05:45:48.73#ibcon#about to read 4, iclass 7, count 2 2006.257.05:45:48.73#ibcon#read 4, iclass 7, count 2 2006.257.05:45:48.73#ibcon#about to read 5, iclass 7, count 2 2006.257.05:45:48.73#ibcon#read 5, iclass 7, count 2 2006.257.05:45:48.73#ibcon#about to read 6, iclass 7, count 2 2006.257.05:45:48.73#ibcon#read 6, iclass 7, count 2 2006.257.05:45:48.73#ibcon#end of sib2, iclass 7, count 2 2006.257.05:45:48.73#ibcon#*after write, iclass 7, count 2 2006.257.05:45:48.73#ibcon#*before return 0, iclass 7, count 2 2006.257.05:45:48.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:48.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.05:45:48.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.05:45:48.73#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:48.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:48.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:48.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:48.85#ibcon#enter wrdev, iclass 7, count 0 2006.257.05:45:48.85#ibcon#first serial, iclass 7, count 0 2006.257.05:45:48.85#ibcon#enter sib2, iclass 7, count 0 2006.257.05:45:48.85#ibcon#flushed, iclass 7, count 0 2006.257.05:45:48.85#ibcon#about to write, iclass 7, count 0 2006.257.05:45:48.85#ibcon#wrote, iclass 7, count 0 2006.257.05:45:48.85#ibcon#about to read 3, iclass 7, count 0 2006.257.05:45:48.87#ibcon#read 3, iclass 7, count 0 2006.257.05:45:48.87#ibcon#about to read 4, iclass 7, count 0 2006.257.05:45:48.87#ibcon#read 4, iclass 7, count 0 2006.257.05:45:48.87#ibcon#about to read 5, iclass 7, count 0 2006.257.05:45:48.87#ibcon#read 5, iclass 7, count 0 2006.257.05:45:48.87#ibcon#about to read 6, iclass 7, count 0 2006.257.05:45:48.87#ibcon#read 6, iclass 7, count 0 2006.257.05:45:48.87#ibcon#end of sib2, iclass 7, count 0 2006.257.05:45:48.87#ibcon#*mode == 0, iclass 7, count 0 2006.257.05:45:48.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.05:45:48.87#ibcon#[27=USB\r\n] 2006.257.05:45:48.87#ibcon#*before write, iclass 7, count 0 2006.257.05:45:48.87#ibcon#enter sib2, iclass 7, count 0 2006.257.05:45:48.87#ibcon#flushed, iclass 7, count 0 2006.257.05:45:48.87#ibcon#about to write, iclass 7, count 0 2006.257.05:45:48.87#ibcon#wrote, iclass 7, count 0 2006.257.05:45:48.87#ibcon#about to read 3, iclass 7, count 0 2006.257.05:45:48.90#ibcon#read 3, iclass 7, count 0 2006.257.05:45:48.90#ibcon#about to read 4, iclass 7, count 0 2006.257.05:45:48.90#ibcon#read 4, iclass 7, count 0 2006.257.05:45:48.90#ibcon#about to read 5, iclass 7, count 0 2006.257.05:45:48.90#ibcon#read 5, iclass 7, count 0 2006.257.05:45:48.90#ibcon#about to read 6, iclass 7, count 0 2006.257.05:45:48.90#ibcon#read 6, iclass 7, count 0 2006.257.05:45:48.90#ibcon#end of sib2, iclass 7, count 0 2006.257.05:45:48.90#ibcon#*after write, iclass 7, count 0 2006.257.05:45:48.90#ibcon#*before return 0, iclass 7, count 0 2006.257.05:45:48.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:48.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.05:45:48.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.05:45:48.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.05:45:48.90$vck44/vblo=4,679.99 2006.257.05:45:48.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.05:45:48.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.05:45:48.90#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:48.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:48.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:48.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:48.90#ibcon#enter wrdev, iclass 11, count 0 2006.257.05:45:48.90#ibcon#first serial, iclass 11, count 0 2006.257.05:45:48.90#ibcon#enter sib2, iclass 11, count 0 2006.257.05:45:48.90#ibcon#flushed, iclass 11, count 0 2006.257.05:45:48.90#ibcon#about to write, iclass 11, count 0 2006.257.05:45:48.90#ibcon#wrote, iclass 11, count 0 2006.257.05:45:48.90#ibcon#about to read 3, iclass 11, count 0 2006.257.05:45:48.92#ibcon#read 3, iclass 11, count 0 2006.257.05:45:48.92#ibcon#about to read 4, iclass 11, count 0 2006.257.05:45:48.92#ibcon#read 4, iclass 11, count 0 2006.257.05:45:48.92#ibcon#about to read 5, iclass 11, count 0 2006.257.05:45:48.92#ibcon#read 5, iclass 11, count 0 2006.257.05:45:48.92#ibcon#about to read 6, iclass 11, count 0 2006.257.05:45:48.92#ibcon#read 6, iclass 11, count 0 2006.257.05:45:48.92#ibcon#end of sib2, iclass 11, count 0 2006.257.05:45:48.92#ibcon#*mode == 0, iclass 11, count 0 2006.257.05:45:48.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.05:45:48.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:45:48.92#ibcon#*before write, iclass 11, count 0 2006.257.05:45:48.92#ibcon#enter sib2, iclass 11, count 0 2006.257.05:45:48.92#ibcon#flushed, iclass 11, count 0 2006.257.05:45:48.92#ibcon#about to write, iclass 11, count 0 2006.257.05:45:48.92#ibcon#wrote, iclass 11, count 0 2006.257.05:45:48.92#ibcon#about to read 3, iclass 11, count 0 2006.257.05:45:48.96#ibcon#read 3, iclass 11, count 0 2006.257.05:45:48.96#ibcon#about to read 4, iclass 11, count 0 2006.257.05:45:48.96#ibcon#read 4, iclass 11, count 0 2006.257.05:45:48.96#ibcon#about to read 5, iclass 11, count 0 2006.257.05:45:48.96#ibcon#read 5, iclass 11, count 0 2006.257.05:45:48.96#ibcon#about to read 6, iclass 11, count 0 2006.257.05:45:48.96#ibcon#read 6, iclass 11, count 0 2006.257.05:45:48.96#ibcon#end of sib2, iclass 11, count 0 2006.257.05:45:48.96#ibcon#*after write, iclass 11, count 0 2006.257.05:45:48.96#ibcon#*before return 0, iclass 11, count 0 2006.257.05:45:48.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:48.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.05:45:48.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.05:45:48.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.05:45:48.96$vck44/vb=4,5 2006.257.05:45:48.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.05:45:48.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.05:45:48.96#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:48.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:49.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:49.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:49.02#ibcon#enter wrdev, iclass 13, count 2 2006.257.05:45:49.02#ibcon#first serial, iclass 13, count 2 2006.257.05:45:49.02#ibcon#enter sib2, iclass 13, count 2 2006.257.05:45:49.02#ibcon#flushed, iclass 13, count 2 2006.257.05:45:49.02#ibcon#about to write, iclass 13, count 2 2006.257.05:45:49.02#ibcon#wrote, iclass 13, count 2 2006.257.05:45:49.02#ibcon#about to read 3, iclass 13, count 2 2006.257.05:45:49.04#ibcon#read 3, iclass 13, count 2 2006.257.05:45:49.04#ibcon#about to read 4, iclass 13, count 2 2006.257.05:45:49.04#ibcon#read 4, iclass 13, count 2 2006.257.05:45:49.04#ibcon#about to read 5, iclass 13, count 2 2006.257.05:45:49.04#ibcon#read 5, iclass 13, count 2 2006.257.05:45:49.04#ibcon#about to read 6, iclass 13, count 2 2006.257.05:45:49.04#ibcon#read 6, iclass 13, count 2 2006.257.05:45:49.04#ibcon#end of sib2, iclass 13, count 2 2006.257.05:45:49.04#ibcon#*mode == 0, iclass 13, count 2 2006.257.05:45:49.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.05:45:49.04#ibcon#[27=AT04-05\r\n] 2006.257.05:45:49.04#ibcon#*before write, iclass 13, count 2 2006.257.05:45:49.04#ibcon#enter sib2, iclass 13, count 2 2006.257.05:45:49.04#ibcon#flushed, iclass 13, count 2 2006.257.05:45:49.04#ibcon#about to write, iclass 13, count 2 2006.257.05:45:49.04#ibcon#wrote, iclass 13, count 2 2006.257.05:45:49.04#ibcon#about to read 3, iclass 13, count 2 2006.257.05:45:49.07#ibcon#read 3, iclass 13, count 2 2006.257.05:45:49.07#ibcon#about to read 4, iclass 13, count 2 2006.257.05:45:49.07#ibcon#read 4, iclass 13, count 2 2006.257.05:45:49.07#ibcon#about to read 5, iclass 13, count 2 2006.257.05:45:49.07#ibcon#read 5, iclass 13, count 2 2006.257.05:45:49.07#ibcon#about to read 6, iclass 13, count 2 2006.257.05:45:49.07#ibcon#read 6, iclass 13, count 2 2006.257.05:45:49.07#ibcon#end of sib2, iclass 13, count 2 2006.257.05:45:49.07#ibcon#*after write, iclass 13, count 2 2006.257.05:45:49.07#ibcon#*before return 0, iclass 13, count 2 2006.257.05:45:49.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:49.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.05:45:49.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.05:45:49.07#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:49.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:49.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:49.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:49.19#ibcon#enter wrdev, iclass 13, count 0 2006.257.05:45:49.19#ibcon#first serial, iclass 13, count 0 2006.257.05:45:49.19#ibcon#enter sib2, iclass 13, count 0 2006.257.05:45:49.19#ibcon#flushed, iclass 13, count 0 2006.257.05:45:49.19#ibcon#about to write, iclass 13, count 0 2006.257.05:45:49.19#ibcon#wrote, iclass 13, count 0 2006.257.05:45:49.19#ibcon#about to read 3, iclass 13, count 0 2006.257.05:45:49.21#ibcon#read 3, iclass 13, count 0 2006.257.05:45:49.21#ibcon#about to read 4, iclass 13, count 0 2006.257.05:45:49.21#ibcon#read 4, iclass 13, count 0 2006.257.05:45:49.21#ibcon#about to read 5, iclass 13, count 0 2006.257.05:45:49.21#ibcon#read 5, iclass 13, count 0 2006.257.05:45:49.21#ibcon#about to read 6, iclass 13, count 0 2006.257.05:45:49.21#ibcon#read 6, iclass 13, count 0 2006.257.05:45:49.21#ibcon#end of sib2, iclass 13, count 0 2006.257.05:45:49.21#ibcon#*mode == 0, iclass 13, count 0 2006.257.05:45:49.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.05:45:49.21#ibcon#[27=USB\r\n] 2006.257.05:45:49.21#ibcon#*before write, iclass 13, count 0 2006.257.05:45:49.21#ibcon#enter sib2, iclass 13, count 0 2006.257.05:45:49.21#ibcon#flushed, iclass 13, count 0 2006.257.05:45:49.21#ibcon#about to write, iclass 13, count 0 2006.257.05:45:49.21#ibcon#wrote, iclass 13, count 0 2006.257.05:45:49.21#ibcon#about to read 3, iclass 13, count 0 2006.257.05:45:49.24#ibcon#read 3, iclass 13, count 0 2006.257.05:45:49.24#ibcon#about to read 4, iclass 13, count 0 2006.257.05:45:49.24#ibcon#read 4, iclass 13, count 0 2006.257.05:45:49.24#ibcon#about to read 5, iclass 13, count 0 2006.257.05:45:49.24#ibcon#read 5, iclass 13, count 0 2006.257.05:45:49.24#ibcon#about to read 6, iclass 13, count 0 2006.257.05:45:49.24#ibcon#read 6, iclass 13, count 0 2006.257.05:45:49.24#ibcon#end of sib2, iclass 13, count 0 2006.257.05:45:49.24#ibcon#*after write, iclass 13, count 0 2006.257.05:45:49.24#ibcon#*before return 0, iclass 13, count 0 2006.257.05:45:49.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:49.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.05:45:49.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.05:45:49.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.05:45:49.24$vck44/vblo=5,709.99 2006.257.05:45:49.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.05:45:49.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.05:45:49.24#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:49.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:49.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:49.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:49.24#ibcon#enter wrdev, iclass 15, count 0 2006.257.05:45:49.24#ibcon#first serial, iclass 15, count 0 2006.257.05:45:49.24#ibcon#enter sib2, iclass 15, count 0 2006.257.05:45:49.24#ibcon#flushed, iclass 15, count 0 2006.257.05:45:49.24#ibcon#about to write, iclass 15, count 0 2006.257.05:45:49.24#ibcon#wrote, iclass 15, count 0 2006.257.05:45:49.24#ibcon#about to read 3, iclass 15, count 0 2006.257.05:45:49.26#ibcon#read 3, iclass 15, count 0 2006.257.05:45:49.26#ibcon#about to read 4, iclass 15, count 0 2006.257.05:45:49.26#ibcon#read 4, iclass 15, count 0 2006.257.05:45:49.26#ibcon#about to read 5, iclass 15, count 0 2006.257.05:45:49.26#ibcon#read 5, iclass 15, count 0 2006.257.05:45:49.26#ibcon#about to read 6, iclass 15, count 0 2006.257.05:45:49.26#ibcon#read 6, iclass 15, count 0 2006.257.05:45:49.26#ibcon#end of sib2, iclass 15, count 0 2006.257.05:45:49.26#ibcon#*mode == 0, iclass 15, count 0 2006.257.05:45:49.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.05:45:49.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:45:49.26#ibcon#*before write, iclass 15, count 0 2006.257.05:45:49.26#ibcon#enter sib2, iclass 15, count 0 2006.257.05:45:49.26#ibcon#flushed, iclass 15, count 0 2006.257.05:45:49.26#ibcon#about to write, iclass 15, count 0 2006.257.05:45:49.26#ibcon#wrote, iclass 15, count 0 2006.257.05:45:49.26#ibcon#about to read 3, iclass 15, count 0 2006.257.05:45:49.30#ibcon#read 3, iclass 15, count 0 2006.257.05:45:49.30#ibcon#about to read 4, iclass 15, count 0 2006.257.05:45:49.30#ibcon#read 4, iclass 15, count 0 2006.257.05:45:49.30#ibcon#about to read 5, iclass 15, count 0 2006.257.05:45:49.30#ibcon#read 5, iclass 15, count 0 2006.257.05:45:49.30#ibcon#about to read 6, iclass 15, count 0 2006.257.05:45:49.30#ibcon#read 6, iclass 15, count 0 2006.257.05:45:49.30#ibcon#end of sib2, iclass 15, count 0 2006.257.05:45:49.30#ibcon#*after write, iclass 15, count 0 2006.257.05:45:49.30#ibcon#*before return 0, iclass 15, count 0 2006.257.05:45:49.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:49.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.05:45:49.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.05:45:49.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.05:45:49.30$vck44/vb=5,4 2006.257.05:45:49.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.05:45:49.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.05:45:49.30#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:49.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:49.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:49.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:49.36#ibcon#enter wrdev, iclass 17, count 2 2006.257.05:45:49.36#ibcon#first serial, iclass 17, count 2 2006.257.05:45:49.36#ibcon#enter sib2, iclass 17, count 2 2006.257.05:45:49.36#ibcon#flushed, iclass 17, count 2 2006.257.05:45:49.36#ibcon#about to write, iclass 17, count 2 2006.257.05:45:49.36#ibcon#wrote, iclass 17, count 2 2006.257.05:45:49.36#ibcon#about to read 3, iclass 17, count 2 2006.257.05:45:49.38#ibcon#read 3, iclass 17, count 2 2006.257.05:45:49.38#ibcon#about to read 4, iclass 17, count 2 2006.257.05:45:49.38#ibcon#read 4, iclass 17, count 2 2006.257.05:45:49.38#ibcon#about to read 5, iclass 17, count 2 2006.257.05:45:49.38#ibcon#read 5, iclass 17, count 2 2006.257.05:45:49.38#ibcon#about to read 6, iclass 17, count 2 2006.257.05:45:49.38#ibcon#read 6, iclass 17, count 2 2006.257.05:45:49.38#ibcon#end of sib2, iclass 17, count 2 2006.257.05:45:49.38#ibcon#*mode == 0, iclass 17, count 2 2006.257.05:45:49.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.05:45:49.38#ibcon#[27=AT05-04\r\n] 2006.257.05:45:49.38#ibcon#*before write, iclass 17, count 2 2006.257.05:45:49.38#ibcon#enter sib2, iclass 17, count 2 2006.257.05:45:49.38#ibcon#flushed, iclass 17, count 2 2006.257.05:45:49.38#ibcon#about to write, iclass 17, count 2 2006.257.05:45:49.38#ibcon#wrote, iclass 17, count 2 2006.257.05:45:49.38#ibcon#about to read 3, iclass 17, count 2 2006.257.05:45:49.41#ibcon#read 3, iclass 17, count 2 2006.257.05:45:49.41#ibcon#about to read 4, iclass 17, count 2 2006.257.05:45:49.41#ibcon#read 4, iclass 17, count 2 2006.257.05:45:49.41#ibcon#about to read 5, iclass 17, count 2 2006.257.05:45:49.41#ibcon#read 5, iclass 17, count 2 2006.257.05:45:49.41#ibcon#about to read 6, iclass 17, count 2 2006.257.05:45:49.41#ibcon#read 6, iclass 17, count 2 2006.257.05:45:49.41#ibcon#end of sib2, iclass 17, count 2 2006.257.05:45:49.41#ibcon#*after write, iclass 17, count 2 2006.257.05:45:49.41#ibcon#*before return 0, iclass 17, count 2 2006.257.05:45:49.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:49.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.05:45:49.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.05:45:49.41#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:49.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:49.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:49.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:49.53#ibcon#enter wrdev, iclass 17, count 0 2006.257.05:45:49.53#ibcon#first serial, iclass 17, count 0 2006.257.05:45:49.53#ibcon#enter sib2, iclass 17, count 0 2006.257.05:45:49.53#ibcon#flushed, iclass 17, count 0 2006.257.05:45:49.53#ibcon#about to write, iclass 17, count 0 2006.257.05:45:49.53#ibcon#wrote, iclass 17, count 0 2006.257.05:45:49.53#ibcon#about to read 3, iclass 17, count 0 2006.257.05:45:49.55#ibcon#read 3, iclass 17, count 0 2006.257.05:45:49.55#ibcon#about to read 4, iclass 17, count 0 2006.257.05:45:49.55#ibcon#read 4, iclass 17, count 0 2006.257.05:45:49.55#ibcon#about to read 5, iclass 17, count 0 2006.257.05:45:49.55#ibcon#read 5, iclass 17, count 0 2006.257.05:45:49.55#ibcon#about to read 6, iclass 17, count 0 2006.257.05:45:49.55#ibcon#read 6, iclass 17, count 0 2006.257.05:45:49.55#ibcon#end of sib2, iclass 17, count 0 2006.257.05:45:49.55#ibcon#*mode == 0, iclass 17, count 0 2006.257.05:45:49.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.05:45:49.55#ibcon#[27=USB\r\n] 2006.257.05:45:49.55#ibcon#*before write, iclass 17, count 0 2006.257.05:45:49.55#ibcon#enter sib2, iclass 17, count 0 2006.257.05:45:49.55#ibcon#flushed, iclass 17, count 0 2006.257.05:45:49.55#ibcon#about to write, iclass 17, count 0 2006.257.05:45:49.55#ibcon#wrote, iclass 17, count 0 2006.257.05:45:49.55#ibcon#about to read 3, iclass 17, count 0 2006.257.05:45:49.58#ibcon#read 3, iclass 17, count 0 2006.257.05:45:49.58#ibcon#about to read 4, iclass 17, count 0 2006.257.05:45:49.58#ibcon#read 4, iclass 17, count 0 2006.257.05:45:49.58#ibcon#about to read 5, iclass 17, count 0 2006.257.05:45:49.58#ibcon#read 5, iclass 17, count 0 2006.257.05:45:49.58#ibcon#about to read 6, iclass 17, count 0 2006.257.05:45:49.58#ibcon#read 6, iclass 17, count 0 2006.257.05:45:49.58#ibcon#end of sib2, iclass 17, count 0 2006.257.05:45:49.58#ibcon#*after write, iclass 17, count 0 2006.257.05:45:49.58#ibcon#*before return 0, iclass 17, count 0 2006.257.05:45:49.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:49.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.05:45:49.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.05:45:49.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.05:45:49.58$vck44/vblo=6,719.99 2006.257.05:45:49.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.05:45:49.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.05:45:49.58#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:49.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:49.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:49.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:49.58#ibcon#enter wrdev, iclass 19, count 0 2006.257.05:45:49.58#ibcon#first serial, iclass 19, count 0 2006.257.05:45:49.58#ibcon#enter sib2, iclass 19, count 0 2006.257.05:45:49.58#ibcon#flushed, iclass 19, count 0 2006.257.05:45:49.58#ibcon#about to write, iclass 19, count 0 2006.257.05:45:49.58#ibcon#wrote, iclass 19, count 0 2006.257.05:45:49.58#ibcon#about to read 3, iclass 19, count 0 2006.257.05:45:49.60#ibcon#read 3, iclass 19, count 0 2006.257.05:45:49.60#ibcon#about to read 4, iclass 19, count 0 2006.257.05:45:49.60#ibcon#read 4, iclass 19, count 0 2006.257.05:45:49.60#ibcon#about to read 5, iclass 19, count 0 2006.257.05:45:49.60#ibcon#read 5, iclass 19, count 0 2006.257.05:45:49.60#ibcon#about to read 6, iclass 19, count 0 2006.257.05:45:49.60#ibcon#read 6, iclass 19, count 0 2006.257.05:45:49.60#ibcon#end of sib2, iclass 19, count 0 2006.257.05:45:49.60#ibcon#*mode == 0, iclass 19, count 0 2006.257.05:45:49.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.05:45:49.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:45:49.60#ibcon#*before write, iclass 19, count 0 2006.257.05:45:49.60#ibcon#enter sib2, iclass 19, count 0 2006.257.05:45:49.60#ibcon#flushed, iclass 19, count 0 2006.257.05:45:49.60#ibcon#about to write, iclass 19, count 0 2006.257.05:45:49.60#ibcon#wrote, iclass 19, count 0 2006.257.05:45:49.60#ibcon#about to read 3, iclass 19, count 0 2006.257.05:45:49.64#ibcon#read 3, iclass 19, count 0 2006.257.05:45:49.64#ibcon#about to read 4, iclass 19, count 0 2006.257.05:45:49.64#ibcon#read 4, iclass 19, count 0 2006.257.05:45:49.64#ibcon#about to read 5, iclass 19, count 0 2006.257.05:45:49.64#ibcon#read 5, iclass 19, count 0 2006.257.05:45:49.64#ibcon#about to read 6, iclass 19, count 0 2006.257.05:45:49.64#ibcon#read 6, iclass 19, count 0 2006.257.05:45:49.64#ibcon#end of sib2, iclass 19, count 0 2006.257.05:45:49.64#ibcon#*after write, iclass 19, count 0 2006.257.05:45:49.64#ibcon#*before return 0, iclass 19, count 0 2006.257.05:45:49.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:49.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.05:45:49.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.05:45:49.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.05:45:49.64$vck44/vb=6,4 2006.257.05:45:49.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.05:45:49.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.05:45:49.64#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:49.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:49.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:49.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:49.70#ibcon#enter wrdev, iclass 21, count 2 2006.257.05:45:49.70#ibcon#first serial, iclass 21, count 2 2006.257.05:45:49.70#ibcon#enter sib2, iclass 21, count 2 2006.257.05:45:49.70#ibcon#flushed, iclass 21, count 2 2006.257.05:45:49.70#ibcon#about to write, iclass 21, count 2 2006.257.05:45:49.70#ibcon#wrote, iclass 21, count 2 2006.257.05:45:49.70#ibcon#about to read 3, iclass 21, count 2 2006.257.05:45:49.72#ibcon#read 3, iclass 21, count 2 2006.257.05:45:49.72#ibcon#about to read 4, iclass 21, count 2 2006.257.05:45:49.72#ibcon#read 4, iclass 21, count 2 2006.257.05:45:49.72#ibcon#about to read 5, iclass 21, count 2 2006.257.05:45:49.72#ibcon#read 5, iclass 21, count 2 2006.257.05:45:49.72#ibcon#about to read 6, iclass 21, count 2 2006.257.05:45:49.72#ibcon#read 6, iclass 21, count 2 2006.257.05:45:49.72#ibcon#end of sib2, iclass 21, count 2 2006.257.05:45:49.72#ibcon#*mode == 0, iclass 21, count 2 2006.257.05:45:49.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.05:45:49.72#ibcon#[27=AT06-04\r\n] 2006.257.05:45:49.72#ibcon#*before write, iclass 21, count 2 2006.257.05:45:49.72#ibcon#enter sib2, iclass 21, count 2 2006.257.05:45:49.72#ibcon#flushed, iclass 21, count 2 2006.257.05:45:49.72#ibcon#about to write, iclass 21, count 2 2006.257.05:45:49.72#ibcon#wrote, iclass 21, count 2 2006.257.05:45:49.72#ibcon#about to read 3, iclass 21, count 2 2006.257.05:45:49.75#ibcon#read 3, iclass 21, count 2 2006.257.05:45:49.75#ibcon#about to read 4, iclass 21, count 2 2006.257.05:45:49.75#ibcon#read 4, iclass 21, count 2 2006.257.05:45:49.75#ibcon#about to read 5, iclass 21, count 2 2006.257.05:45:49.75#ibcon#read 5, iclass 21, count 2 2006.257.05:45:49.75#ibcon#about to read 6, iclass 21, count 2 2006.257.05:45:49.75#ibcon#read 6, iclass 21, count 2 2006.257.05:45:49.75#ibcon#end of sib2, iclass 21, count 2 2006.257.05:45:49.75#ibcon#*after write, iclass 21, count 2 2006.257.05:45:49.75#ibcon#*before return 0, iclass 21, count 2 2006.257.05:45:49.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:49.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.05:45:49.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.05:45:49.75#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:49.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:49.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:49.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:49.87#ibcon#enter wrdev, iclass 21, count 0 2006.257.05:45:49.87#ibcon#first serial, iclass 21, count 0 2006.257.05:45:49.87#ibcon#enter sib2, iclass 21, count 0 2006.257.05:45:49.87#ibcon#flushed, iclass 21, count 0 2006.257.05:45:49.87#ibcon#about to write, iclass 21, count 0 2006.257.05:45:49.87#ibcon#wrote, iclass 21, count 0 2006.257.05:45:49.87#ibcon#about to read 3, iclass 21, count 0 2006.257.05:45:49.89#ibcon#read 3, iclass 21, count 0 2006.257.05:45:49.89#ibcon#about to read 4, iclass 21, count 0 2006.257.05:45:49.89#ibcon#read 4, iclass 21, count 0 2006.257.05:45:49.89#ibcon#about to read 5, iclass 21, count 0 2006.257.05:45:49.89#ibcon#read 5, iclass 21, count 0 2006.257.05:45:49.89#ibcon#about to read 6, iclass 21, count 0 2006.257.05:45:49.89#ibcon#read 6, iclass 21, count 0 2006.257.05:45:49.89#ibcon#end of sib2, iclass 21, count 0 2006.257.05:45:49.89#ibcon#*mode == 0, iclass 21, count 0 2006.257.05:45:49.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.05:45:49.89#ibcon#[27=USB\r\n] 2006.257.05:45:49.89#ibcon#*before write, iclass 21, count 0 2006.257.05:45:49.89#ibcon#enter sib2, iclass 21, count 0 2006.257.05:45:49.89#ibcon#flushed, iclass 21, count 0 2006.257.05:45:49.89#ibcon#about to write, iclass 21, count 0 2006.257.05:45:49.89#ibcon#wrote, iclass 21, count 0 2006.257.05:45:49.89#ibcon#about to read 3, iclass 21, count 0 2006.257.05:45:49.92#ibcon#read 3, iclass 21, count 0 2006.257.05:45:49.92#ibcon#about to read 4, iclass 21, count 0 2006.257.05:45:49.92#ibcon#read 4, iclass 21, count 0 2006.257.05:45:49.92#ibcon#about to read 5, iclass 21, count 0 2006.257.05:45:49.92#ibcon#read 5, iclass 21, count 0 2006.257.05:45:49.92#ibcon#about to read 6, iclass 21, count 0 2006.257.05:45:49.92#ibcon#read 6, iclass 21, count 0 2006.257.05:45:49.92#ibcon#end of sib2, iclass 21, count 0 2006.257.05:45:49.92#ibcon#*after write, iclass 21, count 0 2006.257.05:45:49.92#ibcon#*before return 0, iclass 21, count 0 2006.257.05:45:49.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:49.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.05:45:49.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.05:45:49.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.05:45:49.92$vck44/vblo=7,734.99 2006.257.05:45:49.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.05:45:49.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.05:45:49.92#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:49.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:45:49.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:45:49.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:45:49.92#ibcon#enter wrdev, iclass 23, count 0 2006.257.05:45:49.92#ibcon#first serial, iclass 23, count 0 2006.257.05:45:49.92#ibcon#enter sib2, iclass 23, count 0 2006.257.05:45:49.92#ibcon#flushed, iclass 23, count 0 2006.257.05:45:49.92#ibcon#about to write, iclass 23, count 0 2006.257.05:45:49.92#ibcon#wrote, iclass 23, count 0 2006.257.05:45:49.92#ibcon#about to read 3, iclass 23, count 0 2006.257.05:45:49.94#ibcon#read 3, iclass 23, count 0 2006.257.05:45:49.94#ibcon#about to read 4, iclass 23, count 0 2006.257.05:45:49.94#ibcon#read 4, iclass 23, count 0 2006.257.05:45:49.94#ibcon#about to read 5, iclass 23, count 0 2006.257.05:45:49.94#ibcon#read 5, iclass 23, count 0 2006.257.05:45:49.94#ibcon#about to read 6, iclass 23, count 0 2006.257.05:45:49.94#ibcon#read 6, iclass 23, count 0 2006.257.05:45:49.94#ibcon#end of sib2, iclass 23, count 0 2006.257.05:45:49.94#ibcon#*mode == 0, iclass 23, count 0 2006.257.05:45:49.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.05:45:49.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:45:49.94#ibcon#*before write, iclass 23, count 0 2006.257.05:45:49.94#ibcon#enter sib2, iclass 23, count 0 2006.257.05:45:49.94#ibcon#flushed, iclass 23, count 0 2006.257.05:45:49.94#ibcon#about to write, iclass 23, count 0 2006.257.05:45:49.94#ibcon#wrote, iclass 23, count 0 2006.257.05:45:49.94#ibcon#about to read 3, iclass 23, count 0 2006.257.05:45:49.98#ibcon#read 3, iclass 23, count 0 2006.257.05:45:49.98#ibcon#about to read 4, iclass 23, count 0 2006.257.05:45:49.98#ibcon#read 4, iclass 23, count 0 2006.257.05:45:49.98#ibcon#about to read 5, iclass 23, count 0 2006.257.05:45:49.98#ibcon#read 5, iclass 23, count 0 2006.257.05:45:49.98#ibcon#about to read 6, iclass 23, count 0 2006.257.05:45:49.98#ibcon#read 6, iclass 23, count 0 2006.257.05:45:49.98#ibcon#end of sib2, iclass 23, count 0 2006.257.05:45:49.98#ibcon#*after write, iclass 23, count 0 2006.257.05:45:49.98#ibcon#*before return 0, iclass 23, count 0 2006.257.05:45:49.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:45:49.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:45:49.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.05:45:49.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.05:45:49.98$vck44/vb=7,4 2006.257.05:45:49.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.05:45:49.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.05:45:49.98#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:49.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:45:50.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:45:50.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:45:50.04#ibcon#enter wrdev, iclass 25, count 2 2006.257.05:45:50.04#ibcon#first serial, iclass 25, count 2 2006.257.05:45:50.04#ibcon#enter sib2, iclass 25, count 2 2006.257.05:45:50.04#ibcon#flushed, iclass 25, count 2 2006.257.05:45:50.04#ibcon#about to write, iclass 25, count 2 2006.257.05:45:50.04#ibcon#wrote, iclass 25, count 2 2006.257.05:45:50.04#ibcon#about to read 3, iclass 25, count 2 2006.257.05:45:50.06#ibcon#read 3, iclass 25, count 2 2006.257.05:45:50.06#ibcon#about to read 4, iclass 25, count 2 2006.257.05:45:50.06#ibcon#read 4, iclass 25, count 2 2006.257.05:45:50.06#ibcon#about to read 5, iclass 25, count 2 2006.257.05:45:50.06#ibcon#read 5, iclass 25, count 2 2006.257.05:45:50.06#ibcon#about to read 6, iclass 25, count 2 2006.257.05:45:50.06#ibcon#read 6, iclass 25, count 2 2006.257.05:45:50.06#ibcon#end of sib2, iclass 25, count 2 2006.257.05:45:50.06#ibcon#*mode == 0, iclass 25, count 2 2006.257.05:45:50.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.05:45:50.06#ibcon#[27=AT07-04\r\n] 2006.257.05:45:50.06#ibcon#*before write, iclass 25, count 2 2006.257.05:45:50.06#ibcon#enter sib2, iclass 25, count 2 2006.257.05:45:50.06#ibcon#flushed, iclass 25, count 2 2006.257.05:45:50.06#ibcon#about to write, iclass 25, count 2 2006.257.05:45:50.06#ibcon#wrote, iclass 25, count 2 2006.257.05:45:50.06#ibcon#about to read 3, iclass 25, count 2 2006.257.05:45:50.09#ibcon#read 3, iclass 25, count 2 2006.257.05:45:50.09#ibcon#about to read 4, iclass 25, count 2 2006.257.05:45:50.09#ibcon#read 4, iclass 25, count 2 2006.257.05:45:50.09#ibcon#about to read 5, iclass 25, count 2 2006.257.05:45:50.09#ibcon#read 5, iclass 25, count 2 2006.257.05:45:50.09#ibcon#about to read 6, iclass 25, count 2 2006.257.05:45:50.09#ibcon#read 6, iclass 25, count 2 2006.257.05:45:50.09#ibcon#end of sib2, iclass 25, count 2 2006.257.05:45:50.09#ibcon#*after write, iclass 25, count 2 2006.257.05:45:50.09#ibcon#*before return 0, iclass 25, count 2 2006.257.05:45:50.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:45:50.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.05:45:50.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.05:45:50.09#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:50.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:45:50.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:45:50.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:45:50.21#ibcon#enter wrdev, iclass 25, count 0 2006.257.05:45:50.21#ibcon#first serial, iclass 25, count 0 2006.257.05:45:50.21#ibcon#enter sib2, iclass 25, count 0 2006.257.05:45:50.21#ibcon#flushed, iclass 25, count 0 2006.257.05:45:50.21#ibcon#about to write, iclass 25, count 0 2006.257.05:45:50.21#ibcon#wrote, iclass 25, count 0 2006.257.05:45:50.21#ibcon#about to read 3, iclass 25, count 0 2006.257.05:45:50.23#ibcon#read 3, iclass 25, count 0 2006.257.05:45:50.23#ibcon#about to read 4, iclass 25, count 0 2006.257.05:45:50.23#ibcon#read 4, iclass 25, count 0 2006.257.05:45:50.23#ibcon#about to read 5, iclass 25, count 0 2006.257.05:45:50.23#ibcon#read 5, iclass 25, count 0 2006.257.05:45:50.23#ibcon#about to read 6, iclass 25, count 0 2006.257.05:45:50.23#ibcon#read 6, iclass 25, count 0 2006.257.05:45:50.23#ibcon#end of sib2, iclass 25, count 0 2006.257.05:45:50.23#ibcon#*mode == 0, iclass 25, count 0 2006.257.05:45:50.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.05:45:50.23#ibcon#[27=USB\r\n] 2006.257.05:45:50.23#ibcon#*before write, iclass 25, count 0 2006.257.05:45:50.23#ibcon#enter sib2, iclass 25, count 0 2006.257.05:45:50.23#ibcon#flushed, iclass 25, count 0 2006.257.05:45:50.23#ibcon#about to write, iclass 25, count 0 2006.257.05:45:50.23#ibcon#wrote, iclass 25, count 0 2006.257.05:45:50.23#ibcon#about to read 3, iclass 25, count 0 2006.257.05:45:50.26#ibcon#read 3, iclass 25, count 0 2006.257.05:45:50.26#ibcon#about to read 4, iclass 25, count 0 2006.257.05:45:50.26#ibcon#read 4, iclass 25, count 0 2006.257.05:45:50.26#ibcon#about to read 5, iclass 25, count 0 2006.257.05:45:50.26#ibcon#read 5, iclass 25, count 0 2006.257.05:45:50.26#ibcon#about to read 6, iclass 25, count 0 2006.257.05:45:50.26#ibcon#read 6, iclass 25, count 0 2006.257.05:45:50.26#ibcon#end of sib2, iclass 25, count 0 2006.257.05:45:50.26#ibcon#*after write, iclass 25, count 0 2006.257.05:45:50.26#ibcon#*before return 0, iclass 25, count 0 2006.257.05:45:50.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:45:50.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.05:45:50.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.05:45:50.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.05:45:50.26$vck44/vblo=8,744.99 2006.257.05:45:50.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.05:45:50.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.05:45:50.26#ibcon#ireg 17 cls_cnt 0 2006.257.05:45:50.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:50.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:50.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:50.26#ibcon#enter wrdev, iclass 27, count 0 2006.257.05:45:50.26#ibcon#first serial, iclass 27, count 0 2006.257.05:45:50.26#ibcon#enter sib2, iclass 27, count 0 2006.257.05:45:50.26#ibcon#flushed, iclass 27, count 0 2006.257.05:45:50.26#ibcon#about to write, iclass 27, count 0 2006.257.05:45:50.26#ibcon#wrote, iclass 27, count 0 2006.257.05:45:50.26#ibcon#about to read 3, iclass 27, count 0 2006.257.05:45:50.28#ibcon#read 3, iclass 27, count 0 2006.257.05:45:50.28#ibcon#about to read 4, iclass 27, count 0 2006.257.05:45:50.28#ibcon#read 4, iclass 27, count 0 2006.257.05:45:50.28#ibcon#about to read 5, iclass 27, count 0 2006.257.05:45:50.28#ibcon#read 5, iclass 27, count 0 2006.257.05:45:50.28#ibcon#about to read 6, iclass 27, count 0 2006.257.05:45:50.28#ibcon#read 6, iclass 27, count 0 2006.257.05:45:50.28#ibcon#end of sib2, iclass 27, count 0 2006.257.05:45:50.28#ibcon#*mode == 0, iclass 27, count 0 2006.257.05:45:50.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.05:45:50.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:45:50.28#ibcon#*before write, iclass 27, count 0 2006.257.05:45:50.28#ibcon#enter sib2, iclass 27, count 0 2006.257.05:45:50.28#ibcon#flushed, iclass 27, count 0 2006.257.05:45:50.28#ibcon#about to write, iclass 27, count 0 2006.257.05:45:50.28#ibcon#wrote, iclass 27, count 0 2006.257.05:45:50.28#ibcon#about to read 3, iclass 27, count 0 2006.257.05:45:50.32#ibcon#read 3, iclass 27, count 0 2006.257.05:45:50.32#ibcon#about to read 4, iclass 27, count 0 2006.257.05:45:50.32#ibcon#read 4, iclass 27, count 0 2006.257.05:45:50.32#ibcon#about to read 5, iclass 27, count 0 2006.257.05:45:50.32#ibcon#read 5, iclass 27, count 0 2006.257.05:45:50.32#ibcon#about to read 6, iclass 27, count 0 2006.257.05:45:50.32#ibcon#read 6, iclass 27, count 0 2006.257.05:45:50.32#ibcon#end of sib2, iclass 27, count 0 2006.257.05:45:50.32#ibcon#*after write, iclass 27, count 0 2006.257.05:45:50.32#ibcon#*before return 0, iclass 27, count 0 2006.257.05:45:50.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:50.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.05:45:50.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.05:45:50.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.05:45:50.32$vck44/vb=8,4 2006.257.05:45:50.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.05:45:50.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.05:45:50.32#ibcon#ireg 11 cls_cnt 2 2006.257.05:45:50.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:50.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:50.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:50.38#ibcon#enter wrdev, iclass 29, count 2 2006.257.05:45:50.38#ibcon#first serial, iclass 29, count 2 2006.257.05:45:50.38#ibcon#enter sib2, iclass 29, count 2 2006.257.05:45:50.38#ibcon#flushed, iclass 29, count 2 2006.257.05:45:50.38#ibcon#about to write, iclass 29, count 2 2006.257.05:45:50.38#ibcon#wrote, iclass 29, count 2 2006.257.05:45:50.38#ibcon#about to read 3, iclass 29, count 2 2006.257.05:45:50.40#ibcon#read 3, iclass 29, count 2 2006.257.05:45:50.40#ibcon#about to read 4, iclass 29, count 2 2006.257.05:45:50.40#ibcon#read 4, iclass 29, count 2 2006.257.05:45:50.40#ibcon#about to read 5, iclass 29, count 2 2006.257.05:45:50.40#ibcon#read 5, iclass 29, count 2 2006.257.05:45:50.40#ibcon#about to read 6, iclass 29, count 2 2006.257.05:45:50.40#ibcon#read 6, iclass 29, count 2 2006.257.05:45:50.40#ibcon#end of sib2, iclass 29, count 2 2006.257.05:45:50.40#ibcon#*mode == 0, iclass 29, count 2 2006.257.05:45:50.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.05:45:50.40#ibcon#[27=AT08-04\r\n] 2006.257.05:45:50.40#ibcon#*before write, iclass 29, count 2 2006.257.05:45:50.40#ibcon#enter sib2, iclass 29, count 2 2006.257.05:45:50.40#ibcon#flushed, iclass 29, count 2 2006.257.05:45:50.40#ibcon#about to write, iclass 29, count 2 2006.257.05:45:50.40#ibcon#wrote, iclass 29, count 2 2006.257.05:45:50.40#ibcon#about to read 3, iclass 29, count 2 2006.257.05:45:50.43#ibcon#read 3, iclass 29, count 2 2006.257.05:45:50.43#ibcon#about to read 4, iclass 29, count 2 2006.257.05:45:50.43#ibcon#read 4, iclass 29, count 2 2006.257.05:45:50.43#ibcon#about to read 5, iclass 29, count 2 2006.257.05:45:50.43#ibcon#read 5, iclass 29, count 2 2006.257.05:45:50.43#ibcon#about to read 6, iclass 29, count 2 2006.257.05:45:50.43#ibcon#read 6, iclass 29, count 2 2006.257.05:45:50.43#ibcon#end of sib2, iclass 29, count 2 2006.257.05:45:50.43#ibcon#*after write, iclass 29, count 2 2006.257.05:45:50.43#ibcon#*before return 0, iclass 29, count 2 2006.257.05:45:50.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:50.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.05:45:50.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.05:45:50.43#ibcon#ireg 7 cls_cnt 0 2006.257.05:45:50.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:50.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:50.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:50.55#ibcon#enter wrdev, iclass 29, count 0 2006.257.05:45:50.55#ibcon#first serial, iclass 29, count 0 2006.257.05:45:50.55#ibcon#enter sib2, iclass 29, count 0 2006.257.05:45:50.55#ibcon#flushed, iclass 29, count 0 2006.257.05:45:50.55#ibcon#about to write, iclass 29, count 0 2006.257.05:45:50.55#ibcon#wrote, iclass 29, count 0 2006.257.05:45:50.55#ibcon#about to read 3, iclass 29, count 0 2006.257.05:45:50.57#ibcon#read 3, iclass 29, count 0 2006.257.05:45:50.57#ibcon#about to read 4, iclass 29, count 0 2006.257.05:45:50.57#ibcon#read 4, iclass 29, count 0 2006.257.05:45:50.57#ibcon#about to read 5, iclass 29, count 0 2006.257.05:45:50.57#ibcon#read 5, iclass 29, count 0 2006.257.05:45:50.57#ibcon#about to read 6, iclass 29, count 0 2006.257.05:45:50.57#ibcon#read 6, iclass 29, count 0 2006.257.05:45:50.57#ibcon#end of sib2, iclass 29, count 0 2006.257.05:45:50.57#ibcon#*mode == 0, iclass 29, count 0 2006.257.05:45:50.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.05:45:50.57#ibcon#[27=USB\r\n] 2006.257.05:45:50.57#ibcon#*before write, iclass 29, count 0 2006.257.05:45:50.57#ibcon#enter sib2, iclass 29, count 0 2006.257.05:45:50.57#ibcon#flushed, iclass 29, count 0 2006.257.05:45:50.57#ibcon#about to write, iclass 29, count 0 2006.257.05:45:50.57#ibcon#wrote, iclass 29, count 0 2006.257.05:45:50.57#ibcon#about to read 3, iclass 29, count 0 2006.257.05:45:50.60#ibcon#read 3, iclass 29, count 0 2006.257.05:45:50.60#ibcon#about to read 4, iclass 29, count 0 2006.257.05:45:50.60#ibcon#read 4, iclass 29, count 0 2006.257.05:45:50.60#ibcon#about to read 5, iclass 29, count 0 2006.257.05:45:50.60#ibcon#read 5, iclass 29, count 0 2006.257.05:45:50.60#ibcon#about to read 6, iclass 29, count 0 2006.257.05:45:50.60#ibcon#read 6, iclass 29, count 0 2006.257.05:45:50.60#ibcon#end of sib2, iclass 29, count 0 2006.257.05:45:50.60#ibcon#*after write, iclass 29, count 0 2006.257.05:45:50.60#ibcon#*before return 0, iclass 29, count 0 2006.257.05:45:50.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:50.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.05:45:50.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.05:45:50.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.05:45:50.60$vck44/vabw=wide 2006.257.05:45:50.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.05:45:50.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.05:45:50.60#ibcon#ireg 8 cls_cnt 0 2006.257.05:45:50.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:50.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:50.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:50.60#ibcon#enter wrdev, iclass 31, count 0 2006.257.05:45:50.60#ibcon#first serial, iclass 31, count 0 2006.257.05:45:50.60#ibcon#enter sib2, iclass 31, count 0 2006.257.05:45:50.60#ibcon#flushed, iclass 31, count 0 2006.257.05:45:50.60#ibcon#about to write, iclass 31, count 0 2006.257.05:45:50.60#ibcon#wrote, iclass 31, count 0 2006.257.05:45:50.60#ibcon#about to read 3, iclass 31, count 0 2006.257.05:45:50.62#ibcon#read 3, iclass 31, count 0 2006.257.05:45:50.62#ibcon#about to read 4, iclass 31, count 0 2006.257.05:45:50.62#ibcon#read 4, iclass 31, count 0 2006.257.05:45:50.62#ibcon#about to read 5, iclass 31, count 0 2006.257.05:45:50.62#ibcon#read 5, iclass 31, count 0 2006.257.05:45:50.62#ibcon#about to read 6, iclass 31, count 0 2006.257.05:45:50.62#ibcon#read 6, iclass 31, count 0 2006.257.05:45:50.62#ibcon#end of sib2, iclass 31, count 0 2006.257.05:45:50.62#ibcon#*mode == 0, iclass 31, count 0 2006.257.05:45:50.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.05:45:50.62#ibcon#[25=BW32\r\n] 2006.257.05:45:50.62#ibcon#*before write, iclass 31, count 0 2006.257.05:45:50.62#ibcon#enter sib2, iclass 31, count 0 2006.257.05:45:50.62#ibcon#flushed, iclass 31, count 0 2006.257.05:45:50.62#ibcon#about to write, iclass 31, count 0 2006.257.05:45:50.62#ibcon#wrote, iclass 31, count 0 2006.257.05:45:50.62#ibcon#about to read 3, iclass 31, count 0 2006.257.05:45:50.65#ibcon#read 3, iclass 31, count 0 2006.257.05:45:50.65#ibcon#about to read 4, iclass 31, count 0 2006.257.05:45:50.65#ibcon#read 4, iclass 31, count 0 2006.257.05:45:50.65#ibcon#about to read 5, iclass 31, count 0 2006.257.05:45:50.65#ibcon#read 5, iclass 31, count 0 2006.257.05:45:50.65#ibcon#about to read 6, iclass 31, count 0 2006.257.05:45:50.65#ibcon#read 6, iclass 31, count 0 2006.257.05:45:50.65#ibcon#end of sib2, iclass 31, count 0 2006.257.05:45:50.65#ibcon#*after write, iclass 31, count 0 2006.257.05:45:50.65#ibcon#*before return 0, iclass 31, count 0 2006.257.05:45:50.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:50.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.05:45:50.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.05:45:50.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.05:45:50.65$vck44/vbbw=wide 2006.257.05:45:50.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.05:45:50.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.05:45:50.65#ibcon#ireg 8 cls_cnt 0 2006.257.05:45:50.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:45:50.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:45:50.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:45:50.72#ibcon#enter wrdev, iclass 33, count 0 2006.257.05:45:50.72#ibcon#first serial, iclass 33, count 0 2006.257.05:45:50.72#ibcon#enter sib2, iclass 33, count 0 2006.257.05:45:50.72#ibcon#flushed, iclass 33, count 0 2006.257.05:45:50.72#ibcon#about to write, iclass 33, count 0 2006.257.05:45:50.72#ibcon#wrote, iclass 33, count 0 2006.257.05:45:50.72#ibcon#about to read 3, iclass 33, count 0 2006.257.05:45:50.74#ibcon#read 3, iclass 33, count 0 2006.257.05:45:50.74#ibcon#about to read 4, iclass 33, count 0 2006.257.05:45:50.74#ibcon#read 4, iclass 33, count 0 2006.257.05:45:50.74#ibcon#about to read 5, iclass 33, count 0 2006.257.05:45:50.74#ibcon#read 5, iclass 33, count 0 2006.257.05:45:50.74#ibcon#about to read 6, iclass 33, count 0 2006.257.05:45:50.74#ibcon#read 6, iclass 33, count 0 2006.257.05:45:50.74#ibcon#end of sib2, iclass 33, count 0 2006.257.05:45:50.74#ibcon#*mode == 0, iclass 33, count 0 2006.257.05:45:50.74#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.05:45:50.74#ibcon#[27=BW32\r\n] 2006.257.05:45:50.74#ibcon#*before write, iclass 33, count 0 2006.257.05:45:50.74#ibcon#enter sib2, iclass 33, count 0 2006.257.05:45:50.74#ibcon#flushed, iclass 33, count 0 2006.257.05:45:50.74#ibcon#about to write, iclass 33, count 0 2006.257.05:45:50.74#ibcon#wrote, iclass 33, count 0 2006.257.05:45:50.74#ibcon#about to read 3, iclass 33, count 0 2006.257.05:45:50.77#ibcon#read 3, iclass 33, count 0 2006.257.05:45:50.77#ibcon#about to read 4, iclass 33, count 0 2006.257.05:45:50.77#ibcon#read 4, iclass 33, count 0 2006.257.05:45:50.77#ibcon#about to read 5, iclass 33, count 0 2006.257.05:45:50.77#ibcon#read 5, iclass 33, count 0 2006.257.05:45:50.77#ibcon#about to read 6, iclass 33, count 0 2006.257.05:45:50.77#ibcon#read 6, iclass 33, count 0 2006.257.05:45:50.77#ibcon#end of sib2, iclass 33, count 0 2006.257.05:45:50.77#ibcon#*after write, iclass 33, count 0 2006.257.05:45:50.77#ibcon#*before return 0, iclass 33, count 0 2006.257.05:45:50.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:45:50.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:45:50.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.05:45:50.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.05:45:50.77$setupk4/ifdk4 2006.257.05:45:50.77$ifdk4/lo= 2006.257.05:45:50.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:45:50.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:45:50.77$ifdk4/patch= 2006.257.05:45:50.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:45:50.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:45:50.77$setupk4/!*+20s 2006.257.05:45:57.32#abcon#<5=/16 1.7 6.2 20.03 881012.1\r\n> 2006.257.05:45:57.34#abcon#{5=INTERFACE CLEAR} 2006.257.05:45:57.40#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:46:01.14#trakl#Source acquired 2006.257.05:46:01.14#flagr#flagr/antenna,acquired 2006.257.05:46:05.28$setupk4/"tpicd 2006.257.05:46:05.28$setupk4/echo=off 2006.257.05:46:05.28$setupk4/xlog=off 2006.257.05:46:05.28:!2006.257.05:48:21 2006.257.05:48:21.00:preob 2006.257.05:48:21.14/onsource/TRACKING 2006.257.05:48:21.14:!2006.257.05:48:31 2006.257.05:48:31.00:"tape 2006.257.05:48:31.00:"st=record 2006.257.05:48:31.00:data_valid=on 2006.257.05:48:31.00:midob 2006.257.05:48:31.14/onsource/TRACKING 2006.257.05:48:31.14/wx/20.03,1012.1,89 2006.257.05:48:31.20/cable/+6.4810E-03 2006.257.05:48:32.29/va/01,08,usb,yes,33,36 2006.257.05:48:32.29/va/02,07,usb,yes,36,37 2006.257.05:48:32.29/va/03,08,usb,yes,33,34 2006.257.05:48:32.29/va/04,07,usb,yes,37,39 2006.257.05:48:32.29/va/05,04,usb,yes,33,34 2006.257.05:48:32.29/va/06,04,usb,yes,37,37 2006.257.05:48:32.29/va/07,04,usb,yes,38,38 2006.257.05:48:32.29/va/08,04,usb,yes,32,39 2006.257.05:48:32.52/valo/01,524.99,yes,locked 2006.257.05:48:32.52/valo/02,534.99,yes,locked 2006.257.05:48:32.52/valo/03,564.99,yes,locked 2006.257.05:48:32.52/valo/04,624.99,yes,locked 2006.257.05:48:32.52/valo/05,734.99,yes,locked 2006.257.05:48:32.52/valo/06,814.99,yes,locked 2006.257.05:48:32.52/valo/07,864.99,yes,locked 2006.257.05:48:32.52/valo/08,884.99,yes,locked 2006.257.05:48:33.61/vb/01,04,usb,yes,38,35 2006.257.05:48:33.61/vb/02,05,usb,yes,36,35 2006.257.05:48:33.61/vb/03,04,usb,yes,37,41 2006.257.05:48:33.61/vb/04,05,usb,yes,37,36 2006.257.05:48:33.61/vb/05,04,usb,yes,33,36 2006.257.05:48:33.61/vb/06,04,usb,yes,38,34 2006.257.05:48:33.61/vb/07,04,usb,yes,38,38 2006.257.05:48:33.61/vb/08,04,usb,yes,34,38 2006.257.05:48:33.84/vblo/01,629.99,yes,locked 2006.257.05:48:33.84/vblo/02,634.99,yes,locked 2006.257.05:48:33.84/vblo/03,649.99,yes,locked 2006.257.05:48:33.84/vblo/04,679.99,yes,locked 2006.257.05:48:33.84/vblo/05,709.99,yes,locked 2006.257.05:48:33.84/vblo/06,719.99,yes,locked 2006.257.05:48:33.84/vblo/07,734.99,yes,locked 2006.257.05:48:33.84/vblo/08,744.99,yes,locked 2006.257.05:48:33.99/vabw/8 2006.257.05:48:34.14/vbbw/8 2006.257.05:48:34.23/xfe/off,on,16.5 2006.257.05:48:34.62/ifatt/23,28,28,28 2006.257.05:48:35.07/fmout-gps/S +4.53E-07 2006.257.05:48:35.11:!2006.257.05:50:01 2006.257.05:50:01.00:data_valid=off 2006.257.05:50:01.00:"et 2006.257.05:50:01.00:!+3s 2006.257.05:50:04.01:"tape 2006.257.05:50:04.01:postob 2006.257.05:50:04.08/cable/+6.4825E-03 2006.257.05:50:04.08/wx/20.05,1012.1,90 2006.257.05:50:05.08/fmout-gps/S +4.52E-07 2006.257.05:50:05.08:scan_name=257-0553,jd0609,40 2006.257.05:50:05.08:source=1424-418,142756.30,-420619.4,2000.0,ccw 2006.257.05:50:05.14#flagr#flagr/antenna,new-source 2006.257.05:50:06.14:checkk5 2006.257.05:50:06.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:50:06.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:50:07.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:50:07.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:50:08.21/chk_obsdata//k5ts1/T2570548??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.05:50:08.60/chk_obsdata//k5ts2/T2570548??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.05:50:09.02/chk_obsdata//k5ts3/T2570548??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.05:50:09.41/chk_obsdata//k5ts4/T2570548??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.05:50:10.13/k5log//k5ts1_log_newline 2006.257.05:50:10.85/k5log//k5ts2_log_newline 2006.257.05:50:11.59/k5log//k5ts3_log_newline 2006.257.05:50:12.32/k5log//k5ts4_log_newline 2006.257.05:50:12.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:50:12.35:setupk4=1 2006.257.05:50:12.35$setupk4/echo=on 2006.257.05:50:12.35$setupk4/pcalon 2006.257.05:50:12.35$pcalon/"no phase cal control is implemented here 2006.257.05:50:12.35$setupk4/"tpicd=stop 2006.257.05:50:12.35$setupk4/"rec=synch_on 2006.257.05:50:12.35$setupk4/"rec_mode=128 2006.257.05:50:12.35$setupk4/!* 2006.257.05:50:12.35$setupk4/recpk4 2006.257.05:50:12.35$recpk4/recpatch= 2006.257.05:50:12.35$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:50:12.35$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:50:12.35$setupk4/vck44 2006.257.05:50:12.35$vck44/valo=1,524.99 2006.257.05:50:12.35#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.05:50:12.35#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.05:50:12.35#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:12.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:12.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:12.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:12.35#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:50:12.35#ibcon#first serial, iclass 34, count 0 2006.257.05:50:12.35#ibcon#enter sib2, iclass 34, count 0 2006.257.05:50:12.35#ibcon#flushed, iclass 34, count 0 2006.257.05:50:12.35#ibcon#about to write, iclass 34, count 0 2006.257.05:50:12.35#ibcon#wrote, iclass 34, count 0 2006.257.05:50:12.35#ibcon#about to read 3, iclass 34, count 0 2006.257.05:50:12.37#ibcon#read 3, iclass 34, count 0 2006.257.05:50:12.37#ibcon#about to read 4, iclass 34, count 0 2006.257.05:50:12.37#ibcon#read 4, iclass 34, count 0 2006.257.05:50:12.37#ibcon#about to read 5, iclass 34, count 0 2006.257.05:50:12.37#ibcon#read 5, iclass 34, count 0 2006.257.05:50:12.37#ibcon#about to read 6, iclass 34, count 0 2006.257.05:50:12.37#ibcon#read 6, iclass 34, count 0 2006.257.05:50:12.37#ibcon#end of sib2, iclass 34, count 0 2006.257.05:50:12.37#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:50:12.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:50:12.37#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:50:12.37#ibcon#*before write, iclass 34, count 0 2006.257.05:50:12.37#ibcon#enter sib2, iclass 34, count 0 2006.257.05:50:12.37#ibcon#flushed, iclass 34, count 0 2006.257.05:50:12.37#ibcon#about to write, iclass 34, count 0 2006.257.05:50:12.37#ibcon#wrote, iclass 34, count 0 2006.257.05:50:12.37#ibcon#about to read 3, iclass 34, count 0 2006.257.05:50:12.42#ibcon#read 3, iclass 34, count 0 2006.257.05:50:12.42#ibcon#about to read 4, iclass 34, count 0 2006.257.05:50:12.42#ibcon#read 4, iclass 34, count 0 2006.257.05:50:12.42#ibcon#about to read 5, iclass 34, count 0 2006.257.05:50:12.42#ibcon#read 5, iclass 34, count 0 2006.257.05:50:12.42#ibcon#about to read 6, iclass 34, count 0 2006.257.05:50:12.42#ibcon#read 6, iclass 34, count 0 2006.257.05:50:12.42#ibcon#end of sib2, iclass 34, count 0 2006.257.05:50:12.42#ibcon#*after write, iclass 34, count 0 2006.257.05:50:12.42#ibcon#*before return 0, iclass 34, count 0 2006.257.05:50:12.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:12.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:12.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:50:12.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:50:12.42$vck44/va=1,8 2006.257.05:50:12.42#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.05:50:12.42#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.05:50:12.42#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:12.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:12.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:12.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:12.42#ibcon#enter wrdev, iclass 36, count 2 2006.257.05:50:12.42#ibcon#first serial, iclass 36, count 2 2006.257.05:50:12.42#ibcon#enter sib2, iclass 36, count 2 2006.257.05:50:12.42#ibcon#flushed, iclass 36, count 2 2006.257.05:50:12.42#ibcon#about to write, iclass 36, count 2 2006.257.05:50:12.42#ibcon#wrote, iclass 36, count 2 2006.257.05:50:12.42#ibcon#about to read 3, iclass 36, count 2 2006.257.05:50:12.44#ibcon#read 3, iclass 36, count 2 2006.257.05:50:12.44#ibcon#about to read 4, iclass 36, count 2 2006.257.05:50:12.44#ibcon#read 4, iclass 36, count 2 2006.257.05:50:12.44#ibcon#about to read 5, iclass 36, count 2 2006.257.05:50:12.44#ibcon#read 5, iclass 36, count 2 2006.257.05:50:12.44#ibcon#about to read 6, iclass 36, count 2 2006.257.05:50:12.44#ibcon#read 6, iclass 36, count 2 2006.257.05:50:12.44#ibcon#end of sib2, iclass 36, count 2 2006.257.05:50:12.44#ibcon#*mode == 0, iclass 36, count 2 2006.257.05:50:12.44#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.05:50:12.44#ibcon#[25=AT01-08\r\n] 2006.257.05:50:12.44#ibcon#*before write, iclass 36, count 2 2006.257.05:50:12.44#ibcon#enter sib2, iclass 36, count 2 2006.257.05:50:12.44#ibcon#flushed, iclass 36, count 2 2006.257.05:50:12.44#ibcon#about to write, iclass 36, count 2 2006.257.05:50:12.44#ibcon#wrote, iclass 36, count 2 2006.257.05:50:12.44#ibcon#about to read 3, iclass 36, count 2 2006.257.05:50:12.47#ibcon#read 3, iclass 36, count 2 2006.257.05:50:12.47#ibcon#about to read 4, iclass 36, count 2 2006.257.05:50:12.47#ibcon#read 4, iclass 36, count 2 2006.257.05:50:12.47#ibcon#about to read 5, iclass 36, count 2 2006.257.05:50:12.47#ibcon#read 5, iclass 36, count 2 2006.257.05:50:12.47#ibcon#about to read 6, iclass 36, count 2 2006.257.05:50:12.47#ibcon#read 6, iclass 36, count 2 2006.257.05:50:12.47#ibcon#end of sib2, iclass 36, count 2 2006.257.05:50:12.47#ibcon#*after write, iclass 36, count 2 2006.257.05:50:12.47#ibcon#*before return 0, iclass 36, count 2 2006.257.05:50:12.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:12.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:12.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.05:50:12.47#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:12.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:12.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:12.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:12.59#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:50:12.59#ibcon#first serial, iclass 36, count 0 2006.257.05:50:12.59#ibcon#enter sib2, iclass 36, count 0 2006.257.05:50:12.59#ibcon#flushed, iclass 36, count 0 2006.257.05:50:12.59#ibcon#about to write, iclass 36, count 0 2006.257.05:50:12.59#ibcon#wrote, iclass 36, count 0 2006.257.05:50:12.59#ibcon#about to read 3, iclass 36, count 0 2006.257.05:50:12.61#ibcon#read 3, iclass 36, count 0 2006.257.05:50:12.61#ibcon#about to read 4, iclass 36, count 0 2006.257.05:50:12.61#ibcon#read 4, iclass 36, count 0 2006.257.05:50:12.61#ibcon#about to read 5, iclass 36, count 0 2006.257.05:50:12.61#ibcon#read 5, iclass 36, count 0 2006.257.05:50:12.61#ibcon#about to read 6, iclass 36, count 0 2006.257.05:50:12.61#ibcon#read 6, iclass 36, count 0 2006.257.05:50:12.61#ibcon#end of sib2, iclass 36, count 0 2006.257.05:50:12.61#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:50:12.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:50:12.61#ibcon#[25=USB\r\n] 2006.257.05:50:12.61#ibcon#*before write, iclass 36, count 0 2006.257.05:50:12.61#ibcon#enter sib2, iclass 36, count 0 2006.257.05:50:12.61#ibcon#flushed, iclass 36, count 0 2006.257.05:50:12.61#ibcon#about to write, iclass 36, count 0 2006.257.05:50:12.61#ibcon#wrote, iclass 36, count 0 2006.257.05:50:12.61#ibcon#about to read 3, iclass 36, count 0 2006.257.05:50:12.64#ibcon#read 3, iclass 36, count 0 2006.257.05:50:12.64#ibcon#about to read 4, iclass 36, count 0 2006.257.05:50:12.64#ibcon#read 4, iclass 36, count 0 2006.257.05:50:12.64#ibcon#about to read 5, iclass 36, count 0 2006.257.05:50:12.64#ibcon#read 5, iclass 36, count 0 2006.257.05:50:12.64#ibcon#about to read 6, iclass 36, count 0 2006.257.05:50:12.64#ibcon#read 6, iclass 36, count 0 2006.257.05:50:12.64#ibcon#end of sib2, iclass 36, count 0 2006.257.05:50:12.64#ibcon#*after write, iclass 36, count 0 2006.257.05:50:12.64#ibcon#*before return 0, iclass 36, count 0 2006.257.05:50:12.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:12.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:12.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:50:12.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:50:12.64$vck44/valo=2,534.99 2006.257.05:50:12.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.05:50:12.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.05:50:12.64#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:12.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:12.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:12.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:12.64#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:50:12.64#ibcon#first serial, iclass 38, count 0 2006.257.05:50:12.64#ibcon#enter sib2, iclass 38, count 0 2006.257.05:50:12.64#ibcon#flushed, iclass 38, count 0 2006.257.05:50:12.64#ibcon#about to write, iclass 38, count 0 2006.257.05:50:12.64#ibcon#wrote, iclass 38, count 0 2006.257.05:50:12.64#ibcon#about to read 3, iclass 38, count 0 2006.257.05:50:12.66#ibcon#read 3, iclass 38, count 0 2006.257.05:50:12.66#ibcon#about to read 4, iclass 38, count 0 2006.257.05:50:12.66#ibcon#read 4, iclass 38, count 0 2006.257.05:50:12.66#ibcon#about to read 5, iclass 38, count 0 2006.257.05:50:12.66#ibcon#read 5, iclass 38, count 0 2006.257.05:50:12.66#ibcon#about to read 6, iclass 38, count 0 2006.257.05:50:12.66#ibcon#read 6, iclass 38, count 0 2006.257.05:50:12.66#ibcon#end of sib2, iclass 38, count 0 2006.257.05:50:12.66#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:50:12.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:50:12.66#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:50:12.66#ibcon#*before write, iclass 38, count 0 2006.257.05:50:12.66#ibcon#enter sib2, iclass 38, count 0 2006.257.05:50:12.66#ibcon#flushed, iclass 38, count 0 2006.257.05:50:12.66#ibcon#about to write, iclass 38, count 0 2006.257.05:50:12.66#ibcon#wrote, iclass 38, count 0 2006.257.05:50:12.66#ibcon#about to read 3, iclass 38, count 0 2006.257.05:50:12.70#ibcon#read 3, iclass 38, count 0 2006.257.05:50:12.70#ibcon#about to read 4, iclass 38, count 0 2006.257.05:50:12.70#ibcon#read 4, iclass 38, count 0 2006.257.05:50:12.70#ibcon#about to read 5, iclass 38, count 0 2006.257.05:50:12.70#ibcon#read 5, iclass 38, count 0 2006.257.05:50:12.70#ibcon#about to read 6, iclass 38, count 0 2006.257.05:50:12.70#ibcon#read 6, iclass 38, count 0 2006.257.05:50:12.70#ibcon#end of sib2, iclass 38, count 0 2006.257.05:50:12.70#ibcon#*after write, iclass 38, count 0 2006.257.05:50:12.70#ibcon#*before return 0, iclass 38, count 0 2006.257.05:50:12.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:12.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:12.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:50:12.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:50:12.70$vck44/va=2,7 2006.257.05:50:12.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.05:50:12.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.05:50:12.70#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:12.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:12.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:12.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:12.76#ibcon#enter wrdev, iclass 40, count 2 2006.257.05:50:12.76#ibcon#first serial, iclass 40, count 2 2006.257.05:50:12.76#ibcon#enter sib2, iclass 40, count 2 2006.257.05:50:12.76#ibcon#flushed, iclass 40, count 2 2006.257.05:50:12.76#ibcon#about to write, iclass 40, count 2 2006.257.05:50:12.76#ibcon#wrote, iclass 40, count 2 2006.257.05:50:12.76#ibcon#about to read 3, iclass 40, count 2 2006.257.05:50:12.78#ibcon#read 3, iclass 40, count 2 2006.257.05:50:12.78#ibcon#about to read 4, iclass 40, count 2 2006.257.05:50:12.78#ibcon#read 4, iclass 40, count 2 2006.257.05:50:12.78#ibcon#about to read 5, iclass 40, count 2 2006.257.05:50:12.78#ibcon#read 5, iclass 40, count 2 2006.257.05:50:12.78#ibcon#about to read 6, iclass 40, count 2 2006.257.05:50:12.78#ibcon#read 6, iclass 40, count 2 2006.257.05:50:12.78#ibcon#end of sib2, iclass 40, count 2 2006.257.05:50:12.78#ibcon#*mode == 0, iclass 40, count 2 2006.257.05:50:12.78#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.05:50:12.78#ibcon#[25=AT02-07\r\n] 2006.257.05:50:12.78#ibcon#*before write, iclass 40, count 2 2006.257.05:50:12.78#ibcon#enter sib2, iclass 40, count 2 2006.257.05:50:12.78#ibcon#flushed, iclass 40, count 2 2006.257.05:50:12.78#ibcon#about to write, iclass 40, count 2 2006.257.05:50:12.78#ibcon#wrote, iclass 40, count 2 2006.257.05:50:12.78#ibcon#about to read 3, iclass 40, count 2 2006.257.05:50:12.81#ibcon#read 3, iclass 40, count 2 2006.257.05:50:12.81#ibcon#about to read 4, iclass 40, count 2 2006.257.05:50:12.81#ibcon#read 4, iclass 40, count 2 2006.257.05:50:12.81#ibcon#about to read 5, iclass 40, count 2 2006.257.05:50:12.81#ibcon#read 5, iclass 40, count 2 2006.257.05:50:12.81#ibcon#about to read 6, iclass 40, count 2 2006.257.05:50:12.81#ibcon#read 6, iclass 40, count 2 2006.257.05:50:12.81#ibcon#end of sib2, iclass 40, count 2 2006.257.05:50:12.81#ibcon#*after write, iclass 40, count 2 2006.257.05:50:12.81#ibcon#*before return 0, iclass 40, count 2 2006.257.05:50:12.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:12.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:12.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.05:50:12.81#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:12.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:12.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:12.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:12.93#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:50:12.93#ibcon#first serial, iclass 40, count 0 2006.257.05:50:12.93#ibcon#enter sib2, iclass 40, count 0 2006.257.05:50:12.93#ibcon#flushed, iclass 40, count 0 2006.257.05:50:12.93#ibcon#about to write, iclass 40, count 0 2006.257.05:50:12.93#ibcon#wrote, iclass 40, count 0 2006.257.05:50:12.93#ibcon#about to read 3, iclass 40, count 0 2006.257.05:50:12.95#ibcon#read 3, iclass 40, count 0 2006.257.05:50:12.95#ibcon#about to read 4, iclass 40, count 0 2006.257.05:50:12.95#ibcon#read 4, iclass 40, count 0 2006.257.05:50:12.95#ibcon#about to read 5, iclass 40, count 0 2006.257.05:50:12.95#ibcon#read 5, iclass 40, count 0 2006.257.05:50:12.95#ibcon#about to read 6, iclass 40, count 0 2006.257.05:50:12.95#ibcon#read 6, iclass 40, count 0 2006.257.05:50:12.95#ibcon#end of sib2, iclass 40, count 0 2006.257.05:50:12.95#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:50:12.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:50:12.95#ibcon#[25=USB\r\n] 2006.257.05:50:12.95#ibcon#*before write, iclass 40, count 0 2006.257.05:50:12.95#ibcon#enter sib2, iclass 40, count 0 2006.257.05:50:12.95#ibcon#flushed, iclass 40, count 0 2006.257.05:50:12.95#ibcon#about to write, iclass 40, count 0 2006.257.05:50:12.95#ibcon#wrote, iclass 40, count 0 2006.257.05:50:12.95#ibcon#about to read 3, iclass 40, count 0 2006.257.05:50:12.98#ibcon#read 3, iclass 40, count 0 2006.257.05:50:12.98#ibcon#about to read 4, iclass 40, count 0 2006.257.05:50:12.98#ibcon#read 4, iclass 40, count 0 2006.257.05:50:12.98#ibcon#about to read 5, iclass 40, count 0 2006.257.05:50:12.98#ibcon#read 5, iclass 40, count 0 2006.257.05:50:12.98#ibcon#about to read 6, iclass 40, count 0 2006.257.05:50:12.98#ibcon#read 6, iclass 40, count 0 2006.257.05:50:12.98#ibcon#end of sib2, iclass 40, count 0 2006.257.05:50:12.98#ibcon#*after write, iclass 40, count 0 2006.257.05:50:12.98#ibcon#*before return 0, iclass 40, count 0 2006.257.05:50:12.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:12.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:12.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:50:12.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:50:12.98$vck44/valo=3,564.99 2006.257.05:50:12.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.05:50:12.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.05:50:12.98#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:12.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:12.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:12.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:12.98#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:50:12.98#ibcon#first serial, iclass 4, count 0 2006.257.05:50:12.98#ibcon#enter sib2, iclass 4, count 0 2006.257.05:50:12.98#ibcon#flushed, iclass 4, count 0 2006.257.05:50:12.98#ibcon#about to write, iclass 4, count 0 2006.257.05:50:12.98#ibcon#wrote, iclass 4, count 0 2006.257.05:50:12.98#ibcon#about to read 3, iclass 4, count 0 2006.257.05:50:13.00#ibcon#read 3, iclass 4, count 0 2006.257.05:50:13.00#ibcon#about to read 4, iclass 4, count 0 2006.257.05:50:13.00#ibcon#read 4, iclass 4, count 0 2006.257.05:50:13.00#ibcon#about to read 5, iclass 4, count 0 2006.257.05:50:13.00#ibcon#read 5, iclass 4, count 0 2006.257.05:50:13.00#ibcon#about to read 6, iclass 4, count 0 2006.257.05:50:13.00#ibcon#read 6, iclass 4, count 0 2006.257.05:50:13.00#ibcon#end of sib2, iclass 4, count 0 2006.257.05:50:13.00#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:50:13.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:50:13.00#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:50:13.00#ibcon#*before write, iclass 4, count 0 2006.257.05:50:13.00#ibcon#enter sib2, iclass 4, count 0 2006.257.05:50:13.00#ibcon#flushed, iclass 4, count 0 2006.257.05:50:13.00#ibcon#about to write, iclass 4, count 0 2006.257.05:50:13.00#ibcon#wrote, iclass 4, count 0 2006.257.05:50:13.00#ibcon#about to read 3, iclass 4, count 0 2006.257.05:50:13.04#ibcon#read 3, iclass 4, count 0 2006.257.05:50:13.04#ibcon#about to read 4, iclass 4, count 0 2006.257.05:50:13.04#ibcon#read 4, iclass 4, count 0 2006.257.05:50:13.04#ibcon#about to read 5, iclass 4, count 0 2006.257.05:50:13.04#ibcon#read 5, iclass 4, count 0 2006.257.05:50:13.04#ibcon#about to read 6, iclass 4, count 0 2006.257.05:50:13.04#ibcon#read 6, iclass 4, count 0 2006.257.05:50:13.04#ibcon#end of sib2, iclass 4, count 0 2006.257.05:50:13.04#ibcon#*after write, iclass 4, count 0 2006.257.05:50:13.04#ibcon#*before return 0, iclass 4, count 0 2006.257.05:50:13.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:13.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:13.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:50:13.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:50:13.04$vck44/va=3,8 2006.257.05:50:13.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.05:50:13.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.05:50:13.04#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:13.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:13.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:13.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:13.10#ibcon#enter wrdev, iclass 6, count 2 2006.257.05:50:13.10#ibcon#first serial, iclass 6, count 2 2006.257.05:50:13.10#ibcon#enter sib2, iclass 6, count 2 2006.257.05:50:13.10#ibcon#flushed, iclass 6, count 2 2006.257.05:50:13.10#ibcon#about to write, iclass 6, count 2 2006.257.05:50:13.10#ibcon#wrote, iclass 6, count 2 2006.257.05:50:13.10#ibcon#about to read 3, iclass 6, count 2 2006.257.05:50:13.12#ibcon#read 3, iclass 6, count 2 2006.257.05:50:13.12#ibcon#about to read 4, iclass 6, count 2 2006.257.05:50:13.12#ibcon#read 4, iclass 6, count 2 2006.257.05:50:13.12#ibcon#about to read 5, iclass 6, count 2 2006.257.05:50:13.12#ibcon#read 5, iclass 6, count 2 2006.257.05:50:13.12#ibcon#about to read 6, iclass 6, count 2 2006.257.05:50:13.12#ibcon#read 6, iclass 6, count 2 2006.257.05:50:13.12#ibcon#end of sib2, iclass 6, count 2 2006.257.05:50:13.12#ibcon#*mode == 0, iclass 6, count 2 2006.257.05:50:13.12#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.05:50:13.12#ibcon#[25=AT03-08\r\n] 2006.257.05:50:13.12#ibcon#*before write, iclass 6, count 2 2006.257.05:50:13.12#ibcon#enter sib2, iclass 6, count 2 2006.257.05:50:13.12#ibcon#flushed, iclass 6, count 2 2006.257.05:50:13.12#ibcon#about to write, iclass 6, count 2 2006.257.05:50:13.12#ibcon#wrote, iclass 6, count 2 2006.257.05:50:13.12#ibcon#about to read 3, iclass 6, count 2 2006.257.05:50:13.15#ibcon#read 3, iclass 6, count 2 2006.257.05:50:13.15#ibcon#about to read 4, iclass 6, count 2 2006.257.05:50:13.15#ibcon#read 4, iclass 6, count 2 2006.257.05:50:13.15#ibcon#about to read 5, iclass 6, count 2 2006.257.05:50:13.15#ibcon#read 5, iclass 6, count 2 2006.257.05:50:13.15#ibcon#about to read 6, iclass 6, count 2 2006.257.05:50:13.15#ibcon#read 6, iclass 6, count 2 2006.257.05:50:13.15#ibcon#end of sib2, iclass 6, count 2 2006.257.05:50:13.15#ibcon#*after write, iclass 6, count 2 2006.257.05:50:13.15#ibcon#*before return 0, iclass 6, count 2 2006.257.05:50:13.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:13.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:13.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.05:50:13.15#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:13.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:13.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:13.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:13.27#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:50:13.27#ibcon#first serial, iclass 6, count 0 2006.257.05:50:13.27#ibcon#enter sib2, iclass 6, count 0 2006.257.05:50:13.27#ibcon#flushed, iclass 6, count 0 2006.257.05:50:13.27#ibcon#about to write, iclass 6, count 0 2006.257.05:50:13.27#ibcon#wrote, iclass 6, count 0 2006.257.05:50:13.27#ibcon#about to read 3, iclass 6, count 0 2006.257.05:50:13.29#ibcon#read 3, iclass 6, count 0 2006.257.05:50:13.29#ibcon#about to read 4, iclass 6, count 0 2006.257.05:50:13.29#ibcon#read 4, iclass 6, count 0 2006.257.05:50:13.29#ibcon#about to read 5, iclass 6, count 0 2006.257.05:50:13.29#ibcon#read 5, iclass 6, count 0 2006.257.05:50:13.29#ibcon#about to read 6, iclass 6, count 0 2006.257.05:50:13.29#ibcon#read 6, iclass 6, count 0 2006.257.05:50:13.29#ibcon#end of sib2, iclass 6, count 0 2006.257.05:50:13.29#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:50:13.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:50:13.29#ibcon#[25=USB\r\n] 2006.257.05:50:13.29#ibcon#*before write, iclass 6, count 0 2006.257.05:50:13.29#ibcon#enter sib2, iclass 6, count 0 2006.257.05:50:13.29#ibcon#flushed, iclass 6, count 0 2006.257.05:50:13.29#ibcon#about to write, iclass 6, count 0 2006.257.05:50:13.29#ibcon#wrote, iclass 6, count 0 2006.257.05:50:13.29#ibcon#about to read 3, iclass 6, count 0 2006.257.05:50:13.32#ibcon#read 3, iclass 6, count 0 2006.257.05:50:13.32#ibcon#about to read 4, iclass 6, count 0 2006.257.05:50:13.32#ibcon#read 4, iclass 6, count 0 2006.257.05:50:13.32#ibcon#about to read 5, iclass 6, count 0 2006.257.05:50:13.32#ibcon#read 5, iclass 6, count 0 2006.257.05:50:13.32#ibcon#about to read 6, iclass 6, count 0 2006.257.05:50:13.32#ibcon#read 6, iclass 6, count 0 2006.257.05:50:13.32#ibcon#end of sib2, iclass 6, count 0 2006.257.05:50:13.32#ibcon#*after write, iclass 6, count 0 2006.257.05:50:13.32#ibcon#*before return 0, iclass 6, count 0 2006.257.05:50:13.32#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:13.32#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:13.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:50:13.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:50:13.32$vck44/valo=4,624.99 2006.257.05:50:13.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.05:50:13.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.05:50:13.32#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:13.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:13.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:13.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:13.32#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:50:13.32#ibcon#first serial, iclass 10, count 0 2006.257.05:50:13.32#ibcon#enter sib2, iclass 10, count 0 2006.257.05:50:13.32#ibcon#flushed, iclass 10, count 0 2006.257.05:50:13.32#ibcon#about to write, iclass 10, count 0 2006.257.05:50:13.32#ibcon#wrote, iclass 10, count 0 2006.257.05:50:13.32#ibcon#about to read 3, iclass 10, count 0 2006.257.05:50:13.34#ibcon#read 3, iclass 10, count 0 2006.257.05:50:13.34#ibcon#about to read 4, iclass 10, count 0 2006.257.05:50:13.34#ibcon#read 4, iclass 10, count 0 2006.257.05:50:13.34#ibcon#about to read 5, iclass 10, count 0 2006.257.05:50:13.34#ibcon#read 5, iclass 10, count 0 2006.257.05:50:13.34#ibcon#about to read 6, iclass 10, count 0 2006.257.05:50:13.34#ibcon#read 6, iclass 10, count 0 2006.257.05:50:13.34#ibcon#end of sib2, iclass 10, count 0 2006.257.05:50:13.34#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:50:13.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:50:13.34#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:50:13.34#ibcon#*before write, iclass 10, count 0 2006.257.05:50:13.34#ibcon#enter sib2, iclass 10, count 0 2006.257.05:50:13.34#ibcon#flushed, iclass 10, count 0 2006.257.05:50:13.34#ibcon#about to write, iclass 10, count 0 2006.257.05:50:13.34#ibcon#wrote, iclass 10, count 0 2006.257.05:50:13.34#ibcon#about to read 3, iclass 10, count 0 2006.257.05:50:13.38#ibcon#read 3, iclass 10, count 0 2006.257.05:50:13.38#ibcon#about to read 4, iclass 10, count 0 2006.257.05:50:13.38#ibcon#read 4, iclass 10, count 0 2006.257.05:50:13.38#ibcon#about to read 5, iclass 10, count 0 2006.257.05:50:13.38#ibcon#read 5, iclass 10, count 0 2006.257.05:50:13.38#ibcon#about to read 6, iclass 10, count 0 2006.257.05:50:13.38#ibcon#read 6, iclass 10, count 0 2006.257.05:50:13.38#ibcon#end of sib2, iclass 10, count 0 2006.257.05:50:13.38#ibcon#*after write, iclass 10, count 0 2006.257.05:50:13.38#ibcon#*before return 0, iclass 10, count 0 2006.257.05:50:13.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:13.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:13.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:50:13.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:50:13.38$vck44/va=4,7 2006.257.05:50:13.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.05:50:13.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.05:50:13.38#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:13.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:13.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:13.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:13.44#ibcon#enter wrdev, iclass 12, count 2 2006.257.05:50:13.44#ibcon#first serial, iclass 12, count 2 2006.257.05:50:13.44#ibcon#enter sib2, iclass 12, count 2 2006.257.05:50:13.44#ibcon#flushed, iclass 12, count 2 2006.257.05:50:13.44#ibcon#about to write, iclass 12, count 2 2006.257.05:50:13.44#ibcon#wrote, iclass 12, count 2 2006.257.05:50:13.44#ibcon#about to read 3, iclass 12, count 2 2006.257.05:50:13.46#ibcon#read 3, iclass 12, count 2 2006.257.05:50:13.46#ibcon#about to read 4, iclass 12, count 2 2006.257.05:50:13.46#ibcon#read 4, iclass 12, count 2 2006.257.05:50:13.46#ibcon#about to read 5, iclass 12, count 2 2006.257.05:50:13.46#ibcon#read 5, iclass 12, count 2 2006.257.05:50:13.46#ibcon#about to read 6, iclass 12, count 2 2006.257.05:50:13.46#ibcon#read 6, iclass 12, count 2 2006.257.05:50:13.46#ibcon#end of sib2, iclass 12, count 2 2006.257.05:50:13.46#ibcon#*mode == 0, iclass 12, count 2 2006.257.05:50:13.46#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.05:50:13.46#ibcon#[25=AT04-07\r\n] 2006.257.05:50:13.46#ibcon#*before write, iclass 12, count 2 2006.257.05:50:13.46#ibcon#enter sib2, iclass 12, count 2 2006.257.05:50:13.46#ibcon#flushed, iclass 12, count 2 2006.257.05:50:13.46#ibcon#about to write, iclass 12, count 2 2006.257.05:50:13.46#ibcon#wrote, iclass 12, count 2 2006.257.05:50:13.46#ibcon#about to read 3, iclass 12, count 2 2006.257.05:50:13.49#ibcon#read 3, iclass 12, count 2 2006.257.05:50:13.49#ibcon#about to read 4, iclass 12, count 2 2006.257.05:50:13.49#ibcon#read 4, iclass 12, count 2 2006.257.05:50:13.49#ibcon#about to read 5, iclass 12, count 2 2006.257.05:50:13.49#ibcon#read 5, iclass 12, count 2 2006.257.05:50:13.49#ibcon#about to read 6, iclass 12, count 2 2006.257.05:50:13.49#ibcon#read 6, iclass 12, count 2 2006.257.05:50:13.49#ibcon#end of sib2, iclass 12, count 2 2006.257.05:50:13.49#ibcon#*after write, iclass 12, count 2 2006.257.05:50:13.49#ibcon#*before return 0, iclass 12, count 2 2006.257.05:50:13.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:13.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:13.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.05:50:13.49#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:13.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:13.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:13.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:13.61#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:50:13.61#ibcon#first serial, iclass 12, count 0 2006.257.05:50:13.61#ibcon#enter sib2, iclass 12, count 0 2006.257.05:50:13.61#ibcon#flushed, iclass 12, count 0 2006.257.05:50:13.61#ibcon#about to write, iclass 12, count 0 2006.257.05:50:13.61#ibcon#wrote, iclass 12, count 0 2006.257.05:50:13.61#ibcon#about to read 3, iclass 12, count 0 2006.257.05:50:13.63#ibcon#read 3, iclass 12, count 0 2006.257.05:50:13.63#ibcon#about to read 4, iclass 12, count 0 2006.257.05:50:13.63#ibcon#read 4, iclass 12, count 0 2006.257.05:50:13.63#ibcon#about to read 5, iclass 12, count 0 2006.257.05:50:13.63#ibcon#read 5, iclass 12, count 0 2006.257.05:50:13.63#ibcon#about to read 6, iclass 12, count 0 2006.257.05:50:13.63#ibcon#read 6, iclass 12, count 0 2006.257.05:50:13.63#ibcon#end of sib2, iclass 12, count 0 2006.257.05:50:13.63#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:50:13.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:50:13.63#ibcon#[25=USB\r\n] 2006.257.05:50:13.63#ibcon#*before write, iclass 12, count 0 2006.257.05:50:13.63#ibcon#enter sib2, iclass 12, count 0 2006.257.05:50:13.63#ibcon#flushed, iclass 12, count 0 2006.257.05:50:13.63#ibcon#about to write, iclass 12, count 0 2006.257.05:50:13.63#ibcon#wrote, iclass 12, count 0 2006.257.05:50:13.63#ibcon#about to read 3, iclass 12, count 0 2006.257.05:50:13.66#ibcon#read 3, iclass 12, count 0 2006.257.05:50:13.66#ibcon#about to read 4, iclass 12, count 0 2006.257.05:50:13.66#ibcon#read 4, iclass 12, count 0 2006.257.05:50:13.66#ibcon#about to read 5, iclass 12, count 0 2006.257.05:50:13.66#ibcon#read 5, iclass 12, count 0 2006.257.05:50:13.66#ibcon#about to read 6, iclass 12, count 0 2006.257.05:50:13.66#ibcon#read 6, iclass 12, count 0 2006.257.05:50:13.66#ibcon#end of sib2, iclass 12, count 0 2006.257.05:50:13.66#ibcon#*after write, iclass 12, count 0 2006.257.05:50:13.66#ibcon#*before return 0, iclass 12, count 0 2006.257.05:50:13.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:13.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:13.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:50:13.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:50:13.66$vck44/valo=5,734.99 2006.257.05:50:13.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.05:50:13.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.05:50:13.66#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:13.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:13.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:13.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:13.66#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:50:13.66#ibcon#first serial, iclass 14, count 0 2006.257.05:50:13.66#ibcon#enter sib2, iclass 14, count 0 2006.257.05:50:13.66#ibcon#flushed, iclass 14, count 0 2006.257.05:50:13.66#ibcon#about to write, iclass 14, count 0 2006.257.05:50:13.66#ibcon#wrote, iclass 14, count 0 2006.257.05:50:13.66#ibcon#about to read 3, iclass 14, count 0 2006.257.05:50:13.68#ibcon#read 3, iclass 14, count 0 2006.257.05:50:13.68#ibcon#about to read 4, iclass 14, count 0 2006.257.05:50:13.68#ibcon#read 4, iclass 14, count 0 2006.257.05:50:13.68#ibcon#about to read 5, iclass 14, count 0 2006.257.05:50:13.68#ibcon#read 5, iclass 14, count 0 2006.257.05:50:13.68#ibcon#about to read 6, iclass 14, count 0 2006.257.05:50:13.68#ibcon#read 6, iclass 14, count 0 2006.257.05:50:13.68#ibcon#end of sib2, iclass 14, count 0 2006.257.05:50:13.68#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:50:13.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:50:13.68#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:50:13.68#ibcon#*before write, iclass 14, count 0 2006.257.05:50:13.68#ibcon#enter sib2, iclass 14, count 0 2006.257.05:50:13.68#ibcon#flushed, iclass 14, count 0 2006.257.05:50:13.68#ibcon#about to write, iclass 14, count 0 2006.257.05:50:13.68#ibcon#wrote, iclass 14, count 0 2006.257.05:50:13.68#ibcon#about to read 3, iclass 14, count 0 2006.257.05:50:13.72#ibcon#read 3, iclass 14, count 0 2006.257.05:50:13.72#ibcon#about to read 4, iclass 14, count 0 2006.257.05:50:13.72#ibcon#read 4, iclass 14, count 0 2006.257.05:50:13.72#ibcon#about to read 5, iclass 14, count 0 2006.257.05:50:13.72#ibcon#read 5, iclass 14, count 0 2006.257.05:50:13.72#ibcon#about to read 6, iclass 14, count 0 2006.257.05:50:13.72#ibcon#read 6, iclass 14, count 0 2006.257.05:50:13.72#ibcon#end of sib2, iclass 14, count 0 2006.257.05:50:13.72#ibcon#*after write, iclass 14, count 0 2006.257.05:50:13.72#ibcon#*before return 0, iclass 14, count 0 2006.257.05:50:13.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:13.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:13.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:50:13.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:50:13.72$vck44/va=5,4 2006.257.05:50:13.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.05:50:13.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.05:50:13.72#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:13.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:13.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:13.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:13.78#ibcon#enter wrdev, iclass 16, count 2 2006.257.05:50:13.78#ibcon#first serial, iclass 16, count 2 2006.257.05:50:13.78#ibcon#enter sib2, iclass 16, count 2 2006.257.05:50:13.78#ibcon#flushed, iclass 16, count 2 2006.257.05:50:13.78#ibcon#about to write, iclass 16, count 2 2006.257.05:50:13.78#ibcon#wrote, iclass 16, count 2 2006.257.05:50:13.78#ibcon#about to read 3, iclass 16, count 2 2006.257.05:50:13.80#ibcon#read 3, iclass 16, count 2 2006.257.05:50:13.80#ibcon#about to read 4, iclass 16, count 2 2006.257.05:50:13.80#ibcon#read 4, iclass 16, count 2 2006.257.05:50:13.80#ibcon#about to read 5, iclass 16, count 2 2006.257.05:50:13.80#ibcon#read 5, iclass 16, count 2 2006.257.05:50:13.80#ibcon#about to read 6, iclass 16, count 2 2006.257.05:50:13.80#ibcon#read 6, iclass 16, count 2 2006.257.05:50:13.80#ibcon#end of sib2, iclass 16, count 2 2006.257.05:50:13.80#ibcon#*mode == 0, iclass 16, count 2 2006.257.05:50:13.80#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.05:50:13.80#ibcon#[25=AT05-04\r\n] 2006.257.05:50:13.80#ibcon#*before write, iclass 16, count 2 2006.257.05:50:13.80#ibcon#enter sib2, iclass 16, count 2 2006.257.05:50:13.80#ibcon#flushed, iclass 16, count 2 2006.257.05:50:13.80#ibcon#about to write, iclass 16, count 2 2006.257.05:50:13.80#ibcon#wrote, iclass 16, count 2 2006.257.05:50:13.80#ibcon#about to read 3, iclass 16, count 2 2006.257.05:50:13.83#ibcon#read 3, iclass 16, count 2 2006.257.05:50:13.83#ibcon#about to read 4, iclass 16, count 2 2006.257.05:50:13.83#ibcon#read 4, iclass 16, count 2 2006.257.05:50:13.83#ibcon#about to read 5, iclass 16, count 2 2006.257.05:50:13.83#ibcon#read 5, iclass 16, count 2 2006.257.05:50:13.83#ibcon#about to read 6, iclass 16, count 2 2006.257.05:50:13.83#ibcon#read 6, iclass 16, count 2 2006.257.05:50:13.83#ibcon#end of sib2, iclass 16, count 2 2006.257.05:50:13.83#ibcon#*after write, iclass 16, count 2 2006.257.05:50:13.83#ibcon#*before return 0, iclass 16, count 2 2006.257.05:50:13.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:13.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:13.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.05:50:13.83#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:13.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:13.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:13.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:13.95#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:50:13.95#ibcon#first serial, iclass 16, count 0 2006.257.05:50:13.95#ibcon#enter sib2, iclass 16, count 0 2006.257.05:50:13.95#ibcon#flushed, iclass 16, count 0 2006.257.05:50:13.95#ibcon#about to write, iclass 16, count 0 2006.257.05:50:13.95#ibcon#wrote, iclass 16, count 0 2006.257.05:50:13.95#ibcon#about to read 3, iclass 16, count 0 2006.257.05:50:13.97#ibcon#read 3, iclass 16, count 0 2006.257.05:50:13.97#ibcon#about to read 4, iclass 16, count 0 2006.257.05:50:13.97#ibcon#read 4, iclass 16, count 0 2006.257.05:50:13.97#ibcon#about to read 5, iclass 16, count 0 2006.257.05:50:13.97#ibcon#read 5, iclass 16, count 0 2006.257.05:50:13.97#ibcon#about to read 6, iclass 16, count 0 2006.257.05:50:13.97#ibcon#read 6, iclass 16, count 0 2006.257.05:50:13.97#ibcon#end of sib2, iclass 16, count 0 2006.257.05:50:13.97#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:50:13.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:50:13.97#ibcon#[25=USB\r\n] 2006.257.05:50:13.97#ibcon#*before write, iclass 16, count 0 2006.257.05:50:13.97#ibcon#enter sib2, iclass 16, count 0 2006.257.05:50:13.97#ibcon#flushed, iclass 16, count 0 2006.257.05:50:13.97#ibcon#about to write, iclass 16, count 0 2006.257.05:50:13.97#ibcon#wrote, iclass 16, count 0 2006.257.05:50:13.97#ibcon#about to read 3, iclass 16, count 0 2006.257.05:50:14.00#ibcon#read 3, iclass 16, count 0 2006.257.05:50:14.00#ibcon#about to read 4, iclass 16, count 0 2006.257.05:50:14.00#ibcon#read 4, iclass 16, count 0 2006.257.05:50:14.00#ibcon#about to read 5, iclass 16, count 0 2006.257.05:50:14.00#ibcon#read 5, iclass 16, count 0 2006.257.05:50:14.00#ibcon#about to read 6, iclass 16, count 0 2006.257.05:50:14.00#ibcon#read 6, iclass 16, count 0 2006.257.05:50:14.00#ibcon#end of sib2, iclass 16, count 0 2006.257.05:50:14.00#ibcon#*after write, iclass 16, count 0 2006.257.05:50:14.00#ibcon#*before return 0, iclass 16, count 0 2006.257.05:50:14.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:14.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:14.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:50:14.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:50:14.00$vck44/valo=6,814.99 2006.257.05:50:14.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.05:50:14.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.05:50:14.00#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:14.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:14.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:14.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:14.00#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:50:14.00#ibcon#first serial, iclass 18, count 0 2006.257.05:50:14.00#ibcon#enter sib2, iclass 18, count 0 2006.257.05:50:14.00#ibcon#flushed, iclass 18, count 0 2006.257.05:50:14.00#ibcon#about to write, iclass 18, count 0 2006.257.05:50:14.00#ibcon#wrote, iclass 18, count 0 2006.257.05:50:14.00#ibcon#about to read 3, iclass 18, count 0 2006.257.05:50:14.02#ibcon#read 3, iclass 18, count 0 2006.257.05:50:14.02#ibcon#about to read 4, iclass 18, count 0 2006.257.05:50:14.02#ibcon#read 4, iclass 18, count 0 2006.257.05:50:14.02#ibcon#about to read 5, iclass 18, count 0 2006.257.05:50:14.02#ibcon#read 5, iclass 18, count 0 2006.257.05:50:14.02#ibcon#about to read 6, iclass 18, count 0 2006.257.05:50:14.02#ibcon#read 6, iclass 18, count 0 2006.257.05:50:14.02#ibcon#end of sib2, iclass 18, count 0 2006.257.05:50:14.02#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:50:14.02#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:50:14.02#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:50:14.02#ibcon#*before write, iclass 18, count 0 2006.257.05:50:14.02#ibcon#enter sib2, iclass 18, count 0 2006.257.05:50:14.02#ibcon#flushed, iclass 18, count 0 2006.257.05:50:14.02#ibcon#about to write, iclass 18, count 0 2006.257.05:50:14.02#ibcon#wrote, iclass 18, count 0 2006.257.05:50:14.02#ibcon#about to read 3, iclass 18, count 0 2006.257.05:50:14.06#ibcon#read 3, iclass 18, count 0 2006.257.05:50:14.06#ibcon#about to read 4, iclass 18, count 0 2006.257.05:50:14.06#ibcon#read 4, iclass 18, count 0 2006.257.05:50:14.06#ibcon#about to read 5, iclass 18, count 0 2006.257.05:50:14.06#ibcon#read 5, iclass 18, count 0 2006.257.05:50:14.06#ibcon#about to read 6, iclass 18, count 0 2006.257.05:50:14.06#ibcon#read 6, iclass 18, count 0 2006.257.05:50:14.06#ibcon#end of sib2, iclass 18, count 0 2006.257.05:50:14.06#ibcon#*after write, iclass 18, count 0 2006.257.05:50:14.06#ibcon#*before return 0, iclass 18, count 0 2006.257.05:50:14.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:14.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:14.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:50:14.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:50:14.06$vck44/va=6,4 2006.257.05:50:14.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.05:50:14.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.05:50:14.06#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:14.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:14.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:14.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:14.12#ibcon#enter wrdev, iclass 20, count 2 2006.257.05:50:14.12#ibcon#first serial, iclass 20, count 2 2006.257.05:50:14.12#ibcon#enter sib2, iclass 20, count 2 2006.257.05:50:14.12#ibcon#flushed, iclass 20, count 2 2006.257.05:50:14.12#ibcon#about to write, iclass 20, count 2 2006.257.05:50:14.12#ibcon#wrote, iclass 20, count 2 2006.257.05:50:14.12#ibcon#about to read 3, iclass 20, count 2 2006.257.05:50:14.14#ibcon#read 3, iclass 20, count 2 2006.257.05:50:14.14#ibcon#about to read 4, iclass 20, count 2 2006.257.05:50:14.14#ibcon#read 4, iclass 20, count 2 2006.257.05:50:14.14#ibcon#about to read 5, iclass 20, count 2 2006.257.05:50:14.14#ibcon#read 5, iclass 20, count 2 2006.257.05:50:14.14#ibcon#about to read 6, iclass 20, count 2 2006.257.05:50:14.14#ibcon#read 6, iclass 20, count 2 2006.257.05:50:14.14#ibcon#end of sib2, iclass 20, count 2 2006.257.05:50:14.14#ibcon#*mode == 0, iclass 20, count 2 2006.257.05:50:14.14#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.05:50:14.14#ibcon#[25=AT06-04\r\n] 2006.257.05:50:14.14#ibcon#*before write, iclass 20, count 2 2006.257.05:50:14.14#ibcon#enter sib2, iclass 20, count 2 2006.257.05:50:14.14#ibcon#flushed, iclass 20, count 2 2006.257.05:50:14.14#ibcon#about to write, iclass 20, count 2 2006.257.05:50:14.14#ibcon#wrote, iclass 20, count 2 2006.257.05:50:14.14#ibcon#about to read 3, iclass 20, count 2 2006.257.05:50:14.17#ibcon#read 3, iclass 20, count 2 2006.257.05:50:14.17#ibcon#about to read 4, iclass 20, count 2 2006.257.05:50:14.17#ibcon#read 4, iclass 20, count 2 2006.257.05:50:14.17#ibcon#about to read 5, iclass 20, count 2 2006.257.05:50:14.17#ibcon#read 5, iclass 20, count 2 2006.257.05:50:14.17#ibcon#about to read 6, iclass 20, count 2 2006.257.05:50:14.17#ibcon#read 6, iclass 20, count 2 2006.257.05:50:14.17#ibcon#end of sib2, iclass 20, count 2 2006.257.05:50:14.17#ibcon#*after write, iclass 20, count 2 2006.257.05:50:14.17#ibcon#*before return 0, iclass 20, count 2 2006.257.05:50:14.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:14.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:14.17#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.05:50:14.17#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:14.17#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:14.29#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:14.29#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:14.29#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:50:14.29#ibcon#first serial, iclass 20, count 0 2006.257.05:50:14.29#ibcon#enter sib2, iclass 20, count 0 2006.257.05:50:14.29#ibcon#flushed, iclass 20, count 0 2006.257.05:50:14.29#ibcon#about to write, iclass 20, count 0 2006.257.05:50:14.29#ibcon#wrote, iclass 20, count 0 2006.257.05:50:14.29#ibcon#about to read 3, iclass 20, count 0 2006.257.05:50:14.31#ibcon#read 3, iclass 20, count 0 2006.257.05:50:14.31#ibcon#about to read 4, iclass 20, count 0 2006.257.05:50:14.31#ibcon#read 4, iclass 20, count 0 2006.257.05:50:14.31#ibcon#about to read 5, iclass 20, count 0 2006.257.05:50:14.31#ibcon#read 5, iclass 20, count 0 2006.257.05:50:14.31#ibcon#about to read 6, iclass 20, count 0 2006.257.05:50:14.31#ibcon#read 6, iclass 20, count 0 2006.257.05:50:14.31#ibcon#end of sib2, iclass 20, count 0 2006.257.05:50:14.31#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:50:14.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:50:14.31#ibcon#[25=USB\r\n] 2006.257.05:50:14.31#ibcon#*before write, iclass 20, count 0 2006.257.05:50:14.31#ibcon#enter sib2, iclass 20, count 0 2006.257.05:50:14.31#ibcon#flushed, iclass 20, count 0 2006.257.05:50:14.31#ibcon#about to write, iclass 20, count 0 2006.257.05:50:14.31#ibcon#wrote, iclass 20, count 0 2006.257.05:50:14.31#ibcon#about to read 3, iclass 20, count 0 2006.257.05:50:14.34#ibcon#read 3, iclass 20, count 0 2006.257.05:50:14.34#ibcon#about to read 4, iclass 20, count 0 2006.257.05:50:14.34#ibcon#read 4, iclass 20, count 0 2006.257.05:50:14.34#ibcon#about to read 5, iclass 20, count 0 2006.257.05:50:14.34#ibcon#read 5, iclass 20, count 0 2006.257.05:50:14.34#ibcon#about to read 6, iclass 20, count 0 2006.257.05:50:14.34#ibcon#read 6, iclass 20, count 0 2006.257.05:50:14.34#ibcon#end of sib2, iclass 20, count 0 2006.257.05:50:14.34#ibcon#*after write, iclass 20, count 0 2006.257.05:50:14.34#ibcon#*before return 0, iclass 20, count 0 2006.257.05:50:14.34#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:14.34#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:14.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:50:14.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:50:14.34$vck44/valo=7,864.99 2006.257.05:50:14.34#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.05:50:14.34#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.05:50:14.34#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:14.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:14.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:14.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:14.34#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:50:14.34#ibcon#first serial, iclass 22, count 0 2006.257.05:50:14.34#ibcon#enter sib2, iclass 22, count 0 2006.257.05:50:14.34#ibcon#flushed, iclass 22, count 0 2006.257.05:50:14.34#ibcon#about to write, iclass 22, count 0 2006.257.05:50:14.34#ibcon#wrote, iclass 22, count 0 2006.257.05:50:14.34#ibcon#about to read 3, iclass 22, count 0 2006.257.05:50:14.36#ibcon#read 3, iclass 22, count 0 2006.257.05:50:14.36#ibcon#about to read 4, iclass 22, count 0 2006.257.05:50:14.36#ibcon#read 4, iclass 22, count 0 2006.257.05:50:14.36#ibcon#about to read 5, iclass 22, count 0 2006.257.05:50:14.36#ibcon#read 5, iclass 22, count 0 2006.257.05:50:14.36#ibcon#about to read 6, iclass 22, count 0 2006.257.05:50:14.36#ibcon#read 6, iclass 22, count 0 2006.257.05:50:14.36#ibcon#end of sib2, iclass 22, count 0 2006.257.05:50:14.36#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:50:14.36#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:50:14.36#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:50:14.36#ibcon#*before write, iclass 22, count 0 2006.257.05:50:14.36#ibcon#enter sib2, iclass 22, count 0 2006.257.05:50:14.36#ibcon#flushed, iclass 22, count 0 2006.257.05:50:14.36#ibcon#about to write, iclass 22, count 0 2006.257.05:50:14.36#ibcon#wrote, iclass 22, count 0 2006.257.05:50:14.36#ibcon#about to read 3, iclass 22, count 0 2006.257.05:50:14.40#ibcon#read 3, iclass 22, count 0 2006.257.05:50:14.40#ibcon#about to read 4, iclass 22, count 0 2006.257.05:50:14.40#ibcon#read 4, iclass 22, count 0 2006.257.05:50:14.40#ibcon#about to read 5, iclass 22, count 0 2006.257.05:50:14.40#ibcon#read 5, iclass 22, count 0 2006.257.05:50:14.40#ibcon#about to read 6, iclass 22, count 0 2006.257.05:50:14.40#ibcon#read 6, iclass 22, count 0 2006.257.05:50:14.40#ibcon#end of sib2, iclass 22, count 0 2006.257.05:50:14.40#ibcon#*after write, iclass 22, count 0 2006.257.05:50:14.40#ibcon#*before return 0, iclass 22, count 0 2006.257.05:50:14.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:14.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:14.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:50:14.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:50:14.40$vck44/va=7,4 2006.257.05:50:14.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.05:50:14.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.05:50:14.40#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:14.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:14.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:14.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:14.46#ibcon#enter wrdev, iclass 24, count 2 2006.257.05:50:14.46#ibcon#first serial, iclass 24, count 2 2006.257.05:50:14.46#ibcon#enter sib2, iclass 24, count 2 2006.257.05:50:14.46#ibcon#flushed, iclass 24, count 2 2006.257.05:50:14.46#ibcon#about to write, iclass 24, count 2 2006.257.05:50:14.46#ibcon#wrote, iclass 24, count 2 2006.257.05:50:14.46#ibcon#about to read 3, iclass 24, count 2 2006.257.05:50:14.48#ibcon#read 3, iclass 24, count 2 2006.257.05:50:14.48#ibcon#about to read 4, iclass 24, count 2 2006.257.05:50:14.48#ibcon#read 4, iclass 24, count 2 2006.257.05:50:14.48#ibcon#about to read 5, iclass 24, count 2 2006.257.05:50:14.48#ibcon#read 5, iclass 24, count 2 2006.257.05:50:14.48#ibcon#about to read 6, iclass 24, count 2 2006.257.05:50:14.48#ibcon#read 6, iclass 24, count 2 2006.257.05:50:14.48#ibcon#end of sib2, iclass 24, count 2 2006.257.05:50:14.48#ibcon#*mode == 0, iclass 24, count 2 2006.257.05:50:14.48#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.05:50:14.48#ibcon#[25=AT07-04\r\n] 2006.257.05:50:14.48#ibcon#*before write, iclass 24, count 2 2006.257.05:50:14.48#ibcon#enter sib2, iclass 24, count 2 2006.257.05:50:14.48#ibcon#flushed, iclass 24, count 2 2006.257.05:50:14.48#ibcon#about to write, iclass 24, count 2 2006.257.05:50:14.48#ibcon#wrote, iclass 24, count 2 2006.257.05:50:14.48#ibcon#about to read 3, iclass 24, count 2 2006.257.05:50:14.51#ibcon#read 3, iclass 24, count 2 2006.257.05:50:14.51#ibcon#about to read 4, iclass 24, count 2 2006.257.05:50:14.51#ibcon#read 4, iclass 24, count 2 2006.257.05:50:14.51#ibcon#about to read 5, iclass 24, count 2 2006.257.05:50:14.51#ibcon#read 5, iclass 24, count 2 2006.257.05:50:14.51#ibcon#about to read 6, iclass 24, count 2 2006.257.05:50:14.51#ibcon#read 6, iclass 24, count 2 2006.257.05:50:14.51#ibcon#end of sib2, iclass 24, count 2 2006.257.05:50:14.51#ibcon#*after write, iclass 24, count 2 2006.257.05:50:14.51#ibcon#*before return 0, iclass 24, count 2 2006.257.05:50:14.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:14.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:14.51#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.05:50:14.51#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:14.51#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:14.63#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:14.63#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:14.63#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:50:14.63#ibcon#first serial, iclass 24, count 0 2006.257.05:50:14.63#ibcon#enter sib2, iclass 24, count 0 2006.257.05:50:14.63#ibcon#flushed, iclass 24, count 0 2006.257.05:50:14.63#ibcon#about to write, iclass 24, count 0 2006.257.05:50:14.63#ibcon#wrote, iclass 24, count 0 2006.257.05:50:14.63#ibcon#about to read 3, iclass 24, count 0 2006.257.05:50:14.65#ibcon#read 3, iclass 24, count 0 2006.257.05:50:14.65#ibcon#about to read 4, iclass 24, count 0 2006.257.05:50:14.65#ibcon#read 4, iclass 24, count 0 2006.257.05:50:14.65#ibcon#about to read 5, iclass 24, count 0 2006.257.05:50:14.65#ibcon#read 5, iclass 24, count 0 2006.257.05:50:14.65#ibcon#about to read 6, iclass 24, count 0 2006.257.05:50:14.65#ibcon#read 6, iclass 24, count 0 2006.257.05:50:14.65#ibcon#end of sib2, iclass 24, count 0 2006.257.05:50:14.65#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:50:14.65#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:50:14.65#ibcon#[25=USB\r\n] 2006.257.05:50:14.65#ibcon#*before write, iclass 24, count 0 2006.257.05:50:14.65#ibcon#enter sib2, iclass 24, count 0 2006.257.05:50:14.65#ibcon#flushed, iclass 24, count 0 2006.257.05:50:14.65#ibcon#about to write, iclass 24, count 0 2006.257.05:50:14.65#ibcon#wrote, iclass 24, count 0 2006.257.05:50:14.65#ibcon#about to read 3, iclass 24, count 0 2006.257.05:50:14.68#ibcon#read 3, iclass 24, count 0 2006.257.05:50:14.68#ibcon#about to read 4, iclass 24, count 0 2006.257.05:50:14.68#ibcon#read 4, iclass 24, count 0 2006.257.05:50:14.68#ibcon#about to read 5, iclass 24, count 0 2006.257.05:50:14.68#ibcon#read 5, iclass 24, count 0 2006.257.05:50:14.68#ibcon#about to read 6, iclass 24, count 0 2006.257.05:50:14.68#ibcon#read 6, iclass 24, count 0 2006.257.05:50:14.68#ibcon#end of sib2, iclass 24, count 0 2006.257.05:50:14.68#ibcon#*after write, iclass 24, count 0 2006.257.05:50:14.68#ibcon#*before return 0, iclass 24, count 0 2006.257.05:50:14.68#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:14.68#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:14.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:50:14.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:50:14.68$vck44/valo=8,884.99 2006.257.05:50:14.68#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.05:50:14.68#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.05:50:14.68#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:14.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:14.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:14.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:14.68#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:50:14.68#ibcon#first serial, iclass 26, count 0 2006.257.05:50:14.68#ibcon#enter sib2, iclass 26, count 0 2006.257.05:50:14.68#ibcon#flushed, iclass 26, count 0 2006.257.05:50:14.68#ibcon#about to write, iclass 26, count 0 2006.257.05:50:14.68#ibcon#wrote, iclass 26, count 0 2006.257.05:50:14.68#ibcon#about to read 3, iclass 26, count 0 2006.257.05:50:14.70#ibcon#read 3, iclass 26, count 0 2006.257.05:50:14.70#ibcon#about to read 4, iclass 26, count 0 2006.257.05:50:14.70#ibcon#read 4, iclass 26, count 0 2006.257.05:50:14.70#ibcon#about to read 5, iclass 26, count 0 2006.257.05:50:14.70#ibcon#read 5, iclass 26, count 0 2006.257.05:50:14.70#ibcon#about to read 6, iclass 26, count 0 2006.257.05:50:14.70#ibcon#read 6, iclass 26, count 0 2006.257.05:50:14.70#ibcon#end of sib2, iclass 26, count 0 2006.257.05:50:14.70#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:50:14.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:50:14.70#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:50:14.70#ibcon#*before write, iclass 26, count 0 2006.257.05:50:14.70#ibcon#enter sib2, iclass 26, count 0 2006.257.05:50:14.70#ibcon#flushed, iclass 26, count 0 2006.257.05:50:14.70#ibcon#about to write, iclass 26, count 0 2006.257.05:50:14.70#ibcon#wrote, iclass 26, count 0 2006.257.05:50:14.70#ibcon#about to read 3, iclass 26, count 0 2006.257.05:50:14.74#ibcon#read 3, iclass 26, count 0 2006.257.05:50:14.74#ibcon#about to read 4, iclass 26, count 0 2006.257.05:50:14.74#ibcon#read 4, iclass 26, count 0 2006.257.05:50:14.74#ibcon#about to read 5, iclass 26, count 0 2006.257.05:50:14.74#ibcon#read 5, iclass 26, count 0 2006.257.05:50:14.74#ibcon#about to read 6, iclass 26, count 0 2006.257.05:50:14.74#ibcon#read 6, iclass 26, count 0 2006.257.05:50:14.74#ibcon#end of sib2, iclass 26, count 0 2006.257.05:50:14.74#ibcon#*after write, iclass 26, count 0 2006.257.05:50:14.74#ibcon#*before return 0, iclass 26, count 0 2006.257.05:50:14.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:14.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:14.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:50:14.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:50:14.74$vck44/va=8,4 2006.257.05:50:14.74#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.05:50:14.74#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.05:50:14.74#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:14.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:50:14.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:50:14.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:50:14.80#ibcon#enter wrdev, iclass 28, count 2 2006.257.05:50:14.80#ibcon#first serial, iclass 28, count 2 2006.257.05:50:14.80#ibcon#enter sib2, iclass 28, count 2 2006.257.05:50:14.80#ibcon#flushed, iclass 28, count 2 2006.257.05:50:14.80#ibcon#about to write, iclass 28, count 2 2006.257.05:50:14.80#ibcon#wrote, iclass 28, count 2 2006.257.05:50:14.80#ibcon#about to read 3, iclass 28, count 2 2006.257.05:50:14.82#ibcon#read 3, iclass 28, count 2 2006.257.05:50:14.82#ibcon#about to read 4, iclass 28, count 2 2006.257.05:50:14.82#ibcon#read 4, iclass 28, count 2 2006.257.05:50:14.82#ibcon#about to read 5, iclass 28, count 2 2006.257.05:50:14.82#ibcon#read 5, iclass 28, count 2 2006.257.05:50:14.82#ibcon#about to read 6, iclass 28, count 2 2006.257.05:50:14.82#ibcon#read 6, iclass 28, count 2 2006.257.05:50:14.82#ibcon#end of sib2, iclass 28, count 2 2006.257.05:50:14.82#ibcon#*mode == 0, iclass 28, count 2 2006.257.05:50:14.82#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.05:50:14.82#ibcon#[25=AT08-04\r\n] 2006.257.05:50:14.82#ibcon#*before write, iclass 28, count 2 2006.257.05:50:14.82#ibcon#enter sib2, iclass 28, count 2 2006.257.05:50:14.82#ibcon#flushed, iclass 28, count 2 2006.257.05:50:14.82#ibcon#about to write, iclass 28, count 2 2006.257.05:50:14.82#ibcon#wrote, iclass 28, count 2 2006.257.05:50:14.82#ibcon#about to read 3, iclass 28, count 2 2006.257.05:50:14.85#ibcon#read 3, iclass 28, count 2 2006.257.05:50:14.85#ibcon#about to read 4, iclass 28, count 2 2006.257.05:50:14.85#ibcon#read 4, iclass 28, count 2 2006.257.05:50:14.85#ibcon#about to read 5, iclass 28, count 2 2006.257.05:50:14.85#ibcon#read 5, iclass 28, count 2 2006.257.05:50:14.85#ibcon#about to read 6, iclass 28, count 2 2006.257.05:50:14.85#ibcon#read 6, iclass 28, count 2 2006.257.05:50:14.85#ibcon#end of sib2, iclass 28, count 2 2006.257.05:50:14.85#ibcon#*after write, iclass 28, count 2 2006.257.05:50:14.85#ibcon#*before return 0, iclass 28, count 2 2006.257.05:50:14.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:50:14.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.05:50:14.85#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.05:50:14.85#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:14.85#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:50:14.97#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:50:14.97#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:50:14.97#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:50:14.97#ibcon#first serial, iclass 28, count 0 2006.257.05:50:14.97#ibcon#enter sib2, iclass 28, count 0 2006.257.05:50:14.97#ibcon#flushed, iclass 28, count 0 2006.257.05:50:14.97#ibcon#about to write, iclass 28, count 0 2006.257.05:50:14.97#ibcon#wrote, iclass 28, count 0 2006.257.05:50:14.97#ibcon#about to read 3, iclass 28, count 0 2006.257.05:50:14.99#ibcon#read 3, iclass 28, count 0 2006.257.05:50:14.99#ibcon#about to read 4, iclass 28, count 0 2006.257.05:50:14.99#ibcon#read 4, iclass 28, count 0 2006.257.05:50:14.99#ibcon#about to read 5, iclass 28, count 0 2006.257.05:50:14.99#ibcon#read 5, iclass 28, count 0 2006.257.05:50:14.99#ibcon#about to read 6, iclass 28, count 0 2006.257.05:50:14.99#ibcon#read 6, iclass 28, count 0 2006.257.05:50:14.99#ibcon#end of sib2, iclass 28, count 0 2006.257.05:50:14.99#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:50:14.99#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:50:14.99#ibcon#[25=USB\r\n] 2006.257.05:50:14.99#ibcon#*before write, iclass 28, count 0 2006.257.05:50:14.99#ibcon#enter sib2, iclass 28, count 0 2006.257.05:50:14.99#ibcon#flushed, iclass 28, count 0 2006.257.05:50:14.99#ibcon#about to write, iclass 28, count 0 2006.257.05:50:14.99#ibcon#wrote, iclass 28, count 0 2006.257.05:50:14.99#ibcon#about to read 3, iclass 28, count 0 2006.257.05:50:15.02#ibcon#read 3, iclass 28, count 0 2006.257.05:50:15.02#ibcon#about to read 4, iclass 28, count 0 2006.257.05:50:15.02#ibcon#read 4, iclass 28, count 0 2006.257.05:50:15.02#ibcon#about to read 5, iclass 28, count 0 2006.257.05:50:15.02#ibcon#read 5, iclass 28, count 0 2006.257.05:50:15.02#ibcon#about to read 6, iclass 28, count 0 2006.257.05:50:15.02#ibcon#read 6, iclass 28, count 0 2006.257.05:50:15.02#ibcon#end of sib2, iclass 28, count 0 2006.257.05:50:15.02#ibcon#*after write, iclass 28, count 0 2006.257.05:50:15.02#ibcon#*before return 0, iclass 28, count 0 2006.257.05:50:15.02#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:50:15.02#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.05:50:15.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:50:15.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:50:15.02$vck44/vblo=1,629.99 2006.257.05:50:15.02#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.05:50:15.02#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.05:50:15.02#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:15.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:50:15.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:50:15.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:50:15.02#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:50:15.02#ibcon#first serial, iclass 30, count 0 2006.257.05:50:15.02#ibcon#enter sib2, iclass 30, count 0 2006.257.05:50:15.02#ibcon#flushed, iclass 30, count 0 2006.257.05:50:15.02#ibcon#about to write, iclass 30, count 0 2006.257.05:50:15.02#ibcon#wrote, iclass 30, count 0 2006.257.05:50:15.02#ibcon#about to read 3, iclass 30, count 0 2006.257.05:50:15.04#ibcon#read 3, iclass 30, count 0 2006.257.05:50:15.04#ibcon#about to read 4, iclass 30, count 0 2006.257.05:50:15.04#ibcon#read 4, iclass 30, count 0 2006.257.05:50:15.04#ibcon#about to read 5, iclass 30, count 0 2006.257.05:50:15.04#ibcon#read 5, iclass 30, count 0 2006.257.05:50:15.04#ibcon#about to read 6, iclass 30, count 0 2006.257.05:50:15.04#ibcon#read 6, iclass 30, count 0 2006.257.05:50:15.04#ibcon#end of sib2, iclass 30, count 0 2006.257.05:50:15.04#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:50:15.04#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:50:15.04#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:50:15.04#ibcon#*before write, iclass 30, count 0 2006.257.05:50:15.04#ibcon#enter sib2, iclass 30, count 0 2006.257.05:50:15.04#ibcon#flushed, iclass 30, count 0 2006.257.05:50:15.04#ibcon#about to write, iclass 30, count 0 2006.257.05:50:15.04#ibcon#wrote, iclass 30, count 0 2006.257.05:50:15.04#ibcon#about to read 3, iclass 30, count 0 2006.257.05:50:15.08#ibcon#read 3, iclass 30, count 0 2006.257.05:50:15.08#ibcon#about to read 4, iclass 30, count 0 2006.257.05:50:15.08#ibcon#read 4, iclass 30, count 0 2006.257.05:50:15.08#ibcon#about to read 5, iclass 30, count 0 2006.257.05:50:15.08#ibcon#read 5, iclass 30, count 0 2006.257.05:50:15.08#ibcon#about to read 6, iclass 30, count 0 2006.257.05:50:15.08#ibcon#read 6, iclass 30, count 0 2006.257.05:50:15.08#ibcon#end of sib2, iclass 30, count 0 2006.257.05:50:15.08#ibcon#*after write, iclass 30, count 0 2006.257.05:50:15.08#ibcon#*before return 0, iclass 30, count 0 2006.257.05:50:15.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:50:15.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:50:15.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:50:15.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:50:15.08$vck44/vb=1,4 2006.257.05:50:15.08#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.05:50:15.08#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.05:50:15.08#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:15.08#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:50:15.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:50:15.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:50:15.08#ibcon#enter wrdev, iclass 32, count 2 2006.257.05:50:15.08#ibcon#first serial, iclass 32, count 2 2006.257.05:50:15.08#ibcon#enter sib2, iclass 32, count 2 2006.257.05:50:15.08#ibcon#flushed, iclass 32, count 2 2006.257.05:50:15.08#ibcon#about to write, iclass 32, count 2 2006.257.05:50:15.08#ibcon#wrote, iclass 32, count 2 2006.257.05:50:15.08#ibcon#about to read 3, iclass 32, count 2 2006.257.05:50:15.10#ibcon#read 3, iclass 32, count 2 2006.257.05:50:15.10#ibcon#about to read 4, iclass 32, count 2 2006.257.05:50:15.10#ibcon#read 4, iclass 32, count 2 2006.257.05:50:15.10#ibcon#about to read 5, iclass 32, count 2 2006.257.05:50:15.10#ibcon#read 5, iclass 32, count 2 2006.257.05:50:15.10#ibcon#about to read 6, iclass 32, count 2 2006.257.05:50:15.10#ibcon#read 6, iclass 32, count 2 2006.257.05:50:15.10#ibcon#end of sib2, iclass 32, count 2 2006.257.05:50:15.10#ibcon#*mode == 0, iclass 32, count 2 2006.257.05:50:15.10#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.05:50:15.10#ibcon#[27=AT01-04\r\n] 2006.257.05:50:15.10#ibcon#*before write, iclass 32, count 2 2006.257.05:50:15.10#ibcon#enter sib2, iclass 32, count 2 2006.257.05:50:15.10#ibcon#flushed, iclass 32, count 2 2006.257.05:50:15.10#ibcon#about to write, iclass 32, count 2 2006.257.05:50:15.10#ibcon#wrote, iclass 32, count 2 2006.257.05:50:15.10#ibcon#about to read 3, iclass 32, count 2 2006.257.05:50:15.13#ibcon#read 3, iclass 32, count 2 2006.257.05:50:15.13#ibcon#about to read 4, iclass 32, count 2 2006.257.05:50:15.13#ibcon#read 4, iclass 32, count 2 2006.257.05:50:15.13#ibcon#about to read 5, iclass 32, count 2 2006.257.05:50:15.13#ibcon#read 5, iclass 32, count 2 2006.257.05:50:15.13#ibcon#about to read 6, iclass 32, count 2 2006.257.05:50:15.13#ibcon#read 6, iclass 32, count 2 2006.257.05:50:15.13#ibcon#end of sib2, iclass 32, count 2 2006.257.05:50:15.13#ibcon#*after write, iclass 32, count 2 2006.257.05:50:15.13#ibcon#*before return 0, iclass 32, count 2 2006.257.05:50:15.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:50:15.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.05:50:15.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.05:50:15.13#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:15.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:50:15.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:50:15.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:50:15.25#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:50:15.25#ibcon#first serial, iclass 32, count 0 2006.257.05:50:15.25#ibcon#enter sib2, iclass 32, count 0 2006.257.05:50:15.25#ibcon#flushed, iclass 32, count 0 2006.257.05:50:15.25#ibcon#about to write, iclass 32, count 0 2006.257.05:50:15.25#ibcon#wrote, iclass 32, count 0 2006.257.05:50:15.25#ibcon#about to read 3, iclass 32, count 0 2006.257.05:50:15.27#ibcon#read 3, iclass 32, count 0 2006.257.05:50:15.27#ibcon#about to read 4, iclass 32, count 0 2006.257.05:50:15.27#ibcon#read 4, iclass 32, count 0 2006.257.05:50:15.27#ibcon#about to read 5, iclass 32, count 0 2006.257.05:50:15.27#ibcon#read 5, iclass 32, count 0 2006.257.05:50:15.27#ibcon#about to read 6, iclass 32, count 0 2006.257.05:50:15.27#ibcon#read 6, iclass 32, count 0 2006.257.05:50:15.27#ibcon#end of sib2, iclass 32, count 0 2006.257.05:50:15.27#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:50:15.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:50:15.27#ibcon#[27=USB\r\n] 2006.257.05:50:15.27#ibcon#*before write, iclass 32, count 0 2006.257.05:50:15.27#ibcon#enter sib2, iclass 32, count 0 2006.257.05:50:15.27#ibcon#flushed, iclass 32, count 0 2006.257.05:50:15.27#ibcon#about to write, iclass 32, count 0 2006.257.05:50:15.27#ibcon#wrote, iclass 32, count 0 2006.257.05:50:15.27#ibcon#about to read 3, iclass 32, count 0 2006.257.05:50:15.30#ibcon#read 3, iclass 32, count 0 2006.257.05:50:15.30#ibcon#about to read 4, iclass 32, count 0 2006.257.05:50:15.30#ibcon#read 4, iclass 32, count 0 2006.257.05:50:15.30#ibcon#about to read 5, iclass 32, count 0 2006.257.05:50:15.30#ibcon#read 5, iclass 32, count 0 2006.257.05:50:15.30#ibcon#about to read 6, iclass 32, count 0 2006.257.05:50:15.30#ibcon#read 6, iclass 32, count 0 2006.257.05:50:15.30#ibcon#end of sib2, iclass 32, count 0 2006.257.05:50:15.30#ibcon#*after write, iclass 32, count 0 2006.257.05:50:15.30#ibcon#*before return 0, iclass 32, count 0 2006.257.05:50:15.30#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:50:15.30#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.05:50:15.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:50:15.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:50:15.30$vck44/vblo=2,634.99 2006.257.05:50:15.30#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.05:50:15.30#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.05:50:15.30#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:15.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:15.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:15.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:15.30#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:50:15.30#ibcon#first serial, iclass 34, count 0 2006.257.05:50:15.30#ibcon#enter sib2, iclass 34, count 0 2006.257.05:50:15.30#ibcon#flushed, iclass 34, count 0 2006.257.05:50:15.30#ibcon#about to write, iclass 34, count 0 2006.257.05:50:15.30#ibcon#wrote, iclass 34, count 0 2006.257.05:50:15.30#ibcon#about to read 3, iclass 34, count 0 2006.257.05:50:15.32#ibcon#read 3, iclass 34, count 0 2006.257.05:50:15.32#ibcon#about to read 4, iclass 34, count 0 2006.257.05:50:15.32#ibcon#read 4, iclass 34, count 0 2006.257.05:50:15.32#ibcon#about to read 5, iclass 34, count 0 2006.257.05:50:15.32#ibcon#read 5, iclass 34, count 0 2006.257.05:50:15.32#ibcon#about to read 6, iclass 34, count 0 2006.257.05:50:15.32#ibcon#read 6, iclass 34, count 0 2006.257.05:50:15.32#ibcon#end of sib2, iclass 34, count 0 2006.257.05:50:15.32#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:50:15.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:50:15.32#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:50:15.32#ibcon#*before write, iclass 34, count 0 2006.257.05:50:15.32#ibcon#enter sib2, iclass 34, count 0 2006.257.05:50:15.32#ibcon#flushed, iclass 34, count 0 2006.257.05:50:15.32#ibcon#about to write, iclass 34, count 0 2006.257.05:50:15.32#ibcon#wrote, iclass 34, count 0 2006.257.05:50:15.32#ibcon#about to read 3, iclass 34, count 0 2006.257.05:50:15.36#ibcon#read 3, iclass 34, count 0 2006.257.05:50:15.36#ibcon#about to read 4, iclass 34, count 0 2006.257.05:50:15.36#ibcon#read 4, iclass 34, count 0 2006.257.05:50:15.36#ibcon#about to read 5, iclass 34, count 0 2006.257.05:50:15.36#ibcon#read 5, iclass 34, count 0 2006.257.05:50:15.36#ibcon#about to read 6, iclass 34, count 0 2006.257.05:50:15.36#ibcon#read 6, iclass 34, count 0 2006.257.05:50:15.36#ibcon#end of sib2, iclass 34, count 0 2006.257.05:50:15.36#ibcon#*after write, iclass 34, count 0 2006.257.05:50:15.36#ibcon#*before return 0, iclass 34, count 0 2006.257.05:50:15.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:15.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.05:50:15.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:50:15.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:50:15.36$vck44/vb=2,5 2006.257.05:50:15.36#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.05:50:15.36#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.05:50:15.36#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:15.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:15.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:15.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:15.42#ibcon#enter wrdev, iclass 36, count 2 2006.257.05:50:15.42#ibcon#first serial, iclass 36, count 2 2006.257.05:50:15.42#ibcon#enter sib2, iclass 36, count 2 2006.257.05:50:15.42#ibcon#flushed, iclass 36, count 2 2006.257.05:50:15.42#ibcon#about to write, iclass 36, count 2 2006.257.05:50:15.42#ibcon#wrote, iclass 36, count 2 2006.257.05:50:15.42#ibcon#about to read 3, iclass 36, count 2 2006.257.05:50:15.44#ibcon#read 3, iclass 36, count 2 2006.257.05:50:15.44#ibcon#about to read 4, iclass 36, count 2 2006.257.05:50:15.44#ibcon#read 4, iclass 36, count 2 2006.257.05:50:15.44#ibcon#about to read 5, iclass 36, count 2 2006.257.05:50:15.44#ibcon#read 5, iclass 36, count 2 2006.257.05:50:15.44#ibcon#about to read 6, iclass 36, count 2 2006.257.05:50:15.44#ibcon#read 6, iclass 36, count 2 2006.257.05:50:15.44#ibcon#end of sib2, iclass 36, count 2 2006.257.05:50:15.44#ibcon#*mode == 0, iclass 36, count 2 2006.257.05:50:15.44#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.05:50:15.44#ibcon#[27=AT02-05\r\n] 2006.257.05:50:15.44#ibcon#*before write, iclass 36, count 2 2006.257.05:50:15.44#ibcon#enter sib2, iclass 36, count 2 2006.257.05:50:15.44#ibcon#flushed, iclass 36, count 2 2006.257.05:50:15.44#ibcon#about to write, iclass 36, count 2 2006.257.05:50:15.44#ibcon#wrote, iclass 36, count 2 2006.257.05:50:15.44#ibcon#about to read 3, iclass 36, count 2 2006.257.05:50:15.47#ibcon#read 3, iclass 36, count 2 2006.257.05:50:15.47#ibcon#about to read 4, iclass 36, count 2 2006.257.05:50:15.47#ibcon#read 4, iclass 36, count 2 2006.257.05:50:15.47#ibcon#about to read 5, iclass 36, count 2 2006.257.05:50:15.47#ibcon#read 5, iclass 36, count 2 2006.257.05:50:15.47#ibcon#about to read 6, iclass 36, count 2 2006.257.05:50:15.47#ibcon#read 6, iclass 36, count 2 2006.257.05:50:15.47#ibcon#end of sib2, iclass 36, count 2 2006.257.05:50:15.47#ibcon#*after write, iclass 36, count 2 2006.257.05:50:15.47#ibcon#*before return 0, iclass 36, count 2 2006.257.05:50:15.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:15.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.05:50:15.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.05:50:15.47#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:15.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:15.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:15.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:15.59#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:50:15.59#ibcon#first serial, iclass 36, count 0 2006.257.05:50:15.59#ibcon#enter sib2, iclass 36, count 0 2006.257.05:50:15.59#ibcon#flushed, iclass 36, count 0 2006.257.05:50:15.59#ibcon#about to write, iclass 36, count 0 2006.257.05:50:15.59#ibcon#wrote, iclass 36, count 0 2006.257.05:50:15.59#ibcon#about to read 3, iclass 36, count 0 2006.257.05:50:15.61#ibcon#read 3, iclass 36, count 0 2006.257.05:50:15.61#ibcon#about to read 4, iclass 36, count 0 2006.257.05:50:15.61#ibcon#read 4, iclass 36, count 0 2006.257.05:50:15.61#ibcon#about to read 5, iclass 36, count 0 2006.257.05:50:15.61#ibcon#read 5, iclass 36, count 0 2006.257.05:50:15.61#ibcon#about to read 6, iclass 36, count 0 2006.257.05:50:15.61#ibcon#read 6, iclass 36, count 0 2006.257.05:50:15.61#ibcon#end of sib2, iclass 36, count 0 2006.257.05:50:15.61#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:50:15.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:50:15.61#ibcon#[27=USB\r\n] 2006.257.05:50:15.61#ibcon#*before write, iclass 36, count 0 2006.257.05:50:15.61#ibcon#enter sib2, iclass 36, count 0 2006.257.05:50:15.61#ibcon#flushed, iclass 36, count 0 2006.257.05:50:15.61#ibcon#about to write, iclass 36, count 0 2006.257.05:50:15.61#ibcon#wrote, iclass 36, count 0 2006.257.05:50:15.61#ibcon#about to read 3, iclass 36, count 0 2006.257.05:50:15.64#ibcon#read 3, iclass 36, count 0 2006.257.05:50:15.64#ibcon#about to read 4, iclass 36, count 0 2006.257.05:50:15.64#ibcon#read 4, iclass 36, count 0 2006.257.05:50:15.64#ibcon#about to read 5, iclass 36, count 0 2006.257.05:50:15.64#ibcon#read 5, iclass 36, count 0 2006.257.05:50:15.64#ibcon#about to read 6, iclass 36, count 0 2006.257.05:50:15.64#ibcon#read 6, iclass 36, count 0 2006.257.05:50:15.64#ibcon#end of sib2, iclass 36, count 0 2006.257.05:50:15.64#ibcon#*after write, iclass 36, count 0 2006.257.05:50:15.64#ibcon#*before return 0, iclass 36, count 0 2006.257.05:50:15.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:15.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.05:50:15.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:50:15.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:50:15.64$vck44/vblo=3,649.99 2006.257.05:50:15.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.05:50:15.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.05:50:15.64#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:15.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:15.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:15.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:15.64#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:50:15.64#ibcon#first serial, iclass 38, count 0 2006.257.05:50:15.64#ibcon#enter sib2, iclass 38, count 0 2006.257.05:50:15.64#ibcon#flushed, iclass 38, count 0 2006.257.05:50:15.64#ibcon#about to write, iclass 38, count 0 2006.257.05:50:15.64#ibcon#wrote, iclass 38, count 0 2006.257.05:50:15.64#ibcon#about to read 3, iclass 38, count 0 2006.257.05:50:15.66#ibcon#read 3, iclass 38, count 0 2006.257.05:50:15.66#ibcon#about to read 4, iclass 38, count 0 2006.257.05:50:15.66#ibcon#read 4, iclass 38, count 0 2006.257.05:50:15.66#ibcon#about to read 5, iclass 38, count 0 2006.257.05:50:15.66#ibcon#read 5, iclass 38, count 0 2006.257.05:50:15.66#ibcon#about to read 6, iclass 38, count 0 2006.257.05:50:15.66#ibcon#read 6, iclass 38, count 0 2006.257.05:50:15.66#ibcon#end of sib2, iclass 38, count 0 2006.257.05:50:15.66#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:50:15.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:50:15.66#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:50:15.66#ibcon#*before write, iclass 38, count 0 2006.257.05:50:15.66#ibcon#enter sib2, iclass 38, count 0 2006.257.05:50:15.66#ibcon#flushed, iclass 38, count 0 2006.257.05:50:15.66#ibcon#about to write, iclass 38, count 0 2006.257.05:50:15.66#ibcon#wrote, iclass 38, count 0 2006.257.05:50:15.66#ibcon#about to read 3, iclass 38, count 0 2006.257.05:50:15.70#ibcon#read 3, iclass 38, count 0 2006.257.05:50:15.70#ibcon#about to read 4, iclass 38, count 0 2006.257.05:50:15.70#ibcon#read 4, iclass 38, count 0 2006.257.05:50:15.70#ibcon#about to read 5, iclass 38, count 0 2006.257.05:50:15.70#ibcon#read 5, iclass 38, count 0 2006.257.05:50:15.70#ibcon#about to read 6, iclass 38, count 0 2006.257.05:50:15.70#ibcon#read 6, iclass 38, count 0 2006.257.05:50:15.70#ibcon#end of sib2, iclass 38, count 0 2006.257.05:50:15.70#ibcon#*after write, iclass 38, count 0 2006.257.05:50:15.70#ibcon#*before return 0, iclass 38, count 0 2006.257.05:50:15.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:15.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.05:50:15.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:50:15.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:50:15.70$vck44/vb=3,4 2006.257.05:50:15.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.05:50:15.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.05:50:15.70#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:15.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:15.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:15.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:15.76#ibcon#enter wrdev, iclass 40, count 2 2006.257.05:50:15.76#ibcon#first serial, iclass 40, count 2 2006.257.05:50:15.76#ibcon#enter sib2, iclass 40, count 2 2006.257.05:50:15.76#ibcon#flushed, iclass 40, count 2 2006.257.05:50:15.76#ibcon#about to write, iclass 40, count 2 2006.257.05:50:15.76#ibcon#wrote, iclass 40, count 2 2006.257.05:50:15.76#ibcon#about to read 3, iclass 40, count 2 2006.257.05:50:15.78#ibcon#read 3, iclass 40, count 2 2006.257.05:50:15.78#ibcon#about to read 4, iclass 40, count 2 2006.257.05:50:15.78#ibcon#read 4, iclass 40, count 2 2006.257.05:50:15.78#ibcon#about to read 5, iclass 40, count 2 2006.257.05:50:15.78#ibcon#read 5, iclass 40, count 2 2006.257.05:50:15.78#ibcon#about to read 6, iclass 40, count 2 2006.257.05:50:15.78#ibcon#read 6, iclass 40, count 2 2006.257.05:50:15.78#ibcon#end of sib2, iclass 40, count 2 2006.257.05:50:15.78#ibcon#*mode == 0, iclass 40, count 2 2006.257.05:50:15.78#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.05:50:15.78#ibcon#[27=AT03-04\r\n] 2006.257.05:50:15.78#ibcon#*before write, iclass 40, count 2 2006.257.05:50:15.78#ibcon#enter sib2, iclass 40, count 2 2006.257.05:50:15.78#ibcon#flushed, iclass 40, count 2 2006.257.05:50:15.78#ibcon#about to write, iclass 40, count 2 2006.257.05:50:15.78#ibcon#wrote, iclass 40, count 2 2006.257.05:50:15.78#ibcon#about to read 3, iclass 40, count 2 2006.257.05:50:15.81#ibcon#read 3, iclass 40, count 2 2006.257.05:50:15.81#ibcon#about to read 4, iclass 40, count 2 2006.257.05:50:15.81#ibcon#read 4, iclass 40, count 2 2006.257.05:50:15.81#ibcon#about to read 5, iclass 40, count 2 2006.257.05:50:15.81#ibcon#read 5, iclass 40, count 2 2006.257.05:50:15.81#ibcon#about to read 6, iclass 40, count 2 2006.257.05:50:15.81#ibcon#read 6, iclass 40, count 2 2006.257.05:50:15.81#ibcon#end of sib2, iclass 40, count 2 2006.257.05:50:15.81#ibcon#*after write, iclass 40, count 2 2006.257.05:50:15.81#ibcon#*before return 0, iclass 40, count 2 2006.257.05:50:15.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:15.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.05:50:15.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.05:50:15.81#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:15.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:15.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:15.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:15.93#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:50:15.93#ibcon#first serial, iclass 40, count 0 2006.257.05:50:15.93#ibcon#enter sib2, iclass 40, count 0 2006.257.05:50:15.93#ibcon#flushed, iclass 40, count 0 2006.257.05:50:15.93#ibcon#about to write, iclass 40, count 0 2006.257.05:50:15.93#ibcon#wrote, iclass 40, count 0 2006.257.05:50:15.93#ibcon#about to read 3, iclass 40, count 0 2006.257.05:50:15.95#ibcon#read 3, iclass 40, count 0 2006.257.05:50:15.95#ibcon#about to read 4, iclass 40, count 0 2006.257.05:50:15.95#ibcon#read 4, iclass 40, count 0 2006.257.05:50:15.95#ibcon#about to read 5, iclass 40, count 0 2006.257.05:50:15.95#ibcon#read 5, iclass 40, count 0 2006.257.05:50:15.95#ibcon#about to read 6, iclass 40, count 0 2006.257.05:50:15.95#ibcon#read 6, iclass 40, count 0 2006.257.05:50:15.95#ibcon#end of sib2, iclass 40, count 0 2006.257.05:50:15.95#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:50:15.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:50:15.95#ibcon#[27=USB\r\n] 2006.257.05:50:15.95#ibcon#*before write, iclass 40, count 0 2006.257.05:50:15.95#ibcon#enter sib2, iclass 40, count 0 2006.257.05:50:15.95#ibcon#flushed, iclass 40, count 0 2006.257.05:50:15.95#ibcon#about to write, iclass 40, count 0 2006.257.05:50:15.95#ibcon#wrote, iclass 40, count 0 2006.257.05:50:15.95#ibcon#about to read 3, iclass 40, count 0 2006.257.05:50:15.98#ibcon#read 3, iclass 40, count 0 2006.257.05:50:15.98#ibcon#about to read 4, iclass 40, count 0 2006.257.05:50:15.98#ibcon#read 4, iclass 40, count 0 2006.257.05:50:15.98#ibcon#about to read 5, iclass 40, count 0 2006.257.05:50:15.98#ibcon#read 5, iclass 40, count 0 2006.257.05:50:15.98#ibcon#about to read 6, iclass 40, count 0 2006.257.05:50:15.98#ibcon#read 6, iclass 40, count 0 2006.257.05:50:15.98#ibcon#end of sib2, iclass 40, count 0 2006.257.05:50:15.98#ibcon#*after write, iclass 40, count 0 2006.257.05:50:15.98#ibcon#*before return 0, iclass 40, count 0 2006.257.05:50:15.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:15.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.05:50:15.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:50:15.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:50:15.98$vck44/vblo=4,679.99 2006.257.05:50:15.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.05:50:15.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.05:50:15.98#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:15.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:15.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:15.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:15.98#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:50:15.98#ibcon#first serial, iclass 4, count 0 2006.257.05:50:15.98#ibcon#enter sib2, iclass 4, count 0 2006.257.05:50:15.98#ibcon#flushed, iclass 4, count 0 2006.257.05:50:15.98#ibcon#about to write, iclass 4, count 0 2006.257.05:50:15.98#ibcon#wrote, iclass 4, count 0 2006.257.05:50:15.98#ibcon#about to read 3, iclass 4, count 0 2006.257.05:50:16.00#ibcon#read 3, iclass 4, count 0 2006.257.05:50:16.00#ibcon#about to read 4, iclass 4, count 0 2006.257.05:50:16.00#ibcon#read 4, iclass 4, count 0 2006.257.05:50:16.00#ibcon#about to read 5, iclass 4, count 0 2006.257.05:50:16.00#ibcon#read 5, iclass 4, count 0 2006.257.05:50:16.00#ibcon#about to read 6, iclass 4, count 0 2006.257.05:50:16.00#ibcon#read 6, iclass 4, count 0 2006.257.05:50:16.00#ibcon#end of sib2, iclass 4, count 0 2006.257.05:50:16.00#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:50:16.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:50:16.00#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:50:16.00#ibcon#*before write, iclass 4, count 0 2006.257.05:50:16.00#ibcon#enter sib2, iclass 4, count 0 2006.257.05:50:16.00#ibcon#flushed, iclass 4, count 0 2006.257.05:50:16.00#ibcon#about to write, iclass 4, count 0 2006.257.05:50:16.00#ibcon#wrote, iclass 4, count 0 2006.257.05:50:16.00#ibcon#about to read 3, iclass 4, count 0 2006.257.05:50:16.04#ibcon#read 3, iclass 4, count 0 2006.257.05:50:16.04#ibcon#about to read 4, iclass 4, count 0 2006.257.05:50:16.04#ibcon#read 4, iclass 4, count 0 2006.257.05:50:16.04#ibcon#about to read 5, iclass 4, count 0 2006.257.05:50:16.04#ibcon#read 5, iclass 4, count 0 2006.257.05:50:16.04#ibcon#about to read 6, iclass 4, count 0 2006.257.05:50:16.04#ibcon#read 6, iclass 4, count 0 2006.257.05:50:16.04#ibcon#end of sib2, iclass 4, count 0 2006.257.05:50:16.04#ibcon#*after write, iclass 4, count 0 2006.257.05:50:16.04#ibcon#*before return 0, iclass 4, count 0 2006.257.05:50:16.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:16.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.05:50:16.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:50:16.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:50:16.04$vck44/vb=4,5 2006.257.05:50:16.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.05:50:16.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.05:50:16.04#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:16.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:16.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:16.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:16.10#ibcon#enter wrdev, iclass 6, count 2 2006.257.05:50:16.10#ibcon#first serial, iclass 6, count 2 2006.257.05:50:16.10#ibcon#enter sib2, iclass 6, count 2 2006.257.05:50:16.10#ibcon#flushed, iclass 6, count 2 2006.257.05:50:16.10#ibcon#about to write, iclass 6, count 2 2006.257.05:50:16.10#ibcon#wrote, iclass 6, count 2 2006.257.05:50:16.10#ibcon#about to read 3, iclass 6, count 2 2006.257.05:50:16.12#ibcon#read 3, iclass 6, count 2 2006.257.05:50:16.12#ibcon#about to read 4, iclass 6, count 2 2006.257.05:50:16.12#ibcon#read 4, iclass 6, count 2 2006.257.05:50:16.12#ibcon#about to read 5, iclass 6, count 2 2006.257.05:50:16.12#ibcon#read 5, iclass 6, count 2 2006.257.05:50:16.12#ibcon#about to read 6, iclass 6, count 2 2006.257.05:50:16.12#ibcon#read 6, iclass 6, count 2 2006.257.05:50:16.12#ibcon#end of sib2, iclass 6, count 2 2006.257.05:50:16.12#ibcon#*mode == 0, iclass 6, count 2 2006.257.05:50:16.12#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.05:50:16.12#ibcon#[27=AT04-05\r\n] 2006.257.05:50:16.12#ibcon#*before write, iclass 6, count 2 2006.257.05:50:16.12#ibcon#enter sib2, iclass 6, count 2 2006.257.05:50:16.12#ibcon#flushed, iclass 6, count 2 2006.257.05:50:16.12#ibcon#about to write, iclass 6, count 2 2006.257.05:50:16.12#ibcon#wrote, iclass 6, count 2 2006.257.05:50:16.12#ibcon#about to read 3, iclass 6, count 2 2006.257.05:50:16.15#ibcon#read 3, iclass 6, count 2 2006.257.05:50:16.15#ibcon#about to read 4, iclass 6, count 2 2006.257.05:50:16.15#ibcon#read 4, iclass 6, count 2 2006.257.05:50:16.15#ibcon#about to read 5, iclass 6, count 2 2006.257.05:50:16.15#ibcon#read 5, iclass 6, count 2 2006.257.05:50:16.15#ibcon#about to read 6, iclass 6, count 2 2006.257.05:50:16.15#ibcon#read 6, iclass 6, count 2 2006.257.05:50:16.15#ibcon#end of sib2, iclass 6, count 2 2006.257.05:50:16.15#ibcon#*after write, iclass 6, count 2 2006.257.05:50:16.15#ibcon#*before return 0, iclass 6, count 2 2006.257.05:50:16.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:16.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.05:50:16.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.05:50:16.15#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:16.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:16.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:16.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:16.27#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:50:16.27#ibcon#first serial, iclass 6, count 0 2006.257.05:50:16.27#ibcon#enter sib2, iclass 6, count 0 2006.257.05:50:16.27#ibcon#flushed, iclass 6, count 0 2006.257.05:50:16.27#ibcon#about to write, iclass 6, count 0 2006.257.05:50:16.27#ibcon#wrote, iclass 6, count 0 2006.257.05:50:16.27#ibcon#about to read 3, iclass 6, count 0 2006.257.05:50:16.29#ibcon#read 3, iclass 6, count 0 2006.257.05:50:16.29#ibcon#about to read 4, iclass 6, count 0 2006.257.05:50:16.29#ibcon#read 4, iclass 6, count 0 2006.257.05:50:16.29#ibcon#about to read 5, iclass 6, count 0 2006.257.05:50:16.29#ibcon#read 5, iclass 6, count 0 2006.257.05:50:16.29#ibcon#about to read 6, iclass 6, count 0 2006.257.05:50:16.29#ibcon#read 6, iclass 6, count 0 2006.257.05:50:16.29#ibcon#end of sib2, iclass 6, count 0 2006.257.05:50:16.29#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:50:16.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:50:16.29#ibcon#[27=USB\r\n] 2006.257.05:50:16.29#ibcon#*before write, iclass 6, count 0 2006.257.05:50:16.29#ibcon#enter sib2, iclass 6, count 0 2006.257.05:50:16.29#ibcon#flushed, iclass 6, count 0 2006.257.05:50:16.29#ibcon#about to write, iclass 6, count 0 2006.257.05:50:16.29#ibcon#wrote, iclass 6, count 0 2006.257.05:50:16.29#ibcon#about to read 3, iclass 6, count 0 2006.257.05:50:16.32#ibcon#read 3, iclass 6, count 0 2006.257.05:50:16.32#ibcon#about to read 4, iclass 6, count 0 2006.257.05:50:16.32#ibcon#read 4, iclass 6, count 0 2006.257.05:50:16.32#ibcon#about to read 5, iclass 6, count 0 2006.257.05:50:16.32#ibcon#read 5, iclass 6, count 0 2006.257.05:50:16.32#ibcon#about to read 6, iclass 6, count 0 2006.257.05:50:16.32#ibcon#read 6, iclass 6, count 0 2006.257.05:50:16.32#ibcon#end of sib2, iclass 6, count 0 2006.257.05:50:16.32#ibcon#*after write, iclass 6, count 0 2006.257.05:50:16.32#ibcon#*before return 0, iclass 6, count 0 2006.257.05:50:16.32#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:16.32#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.05:50:16.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:50:16.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:50:16.32$vck44/vblo=5,709.99 2006.257.05:50:16.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.05:50:16.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.05:50:16.32#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:16.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:16.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:16.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:16.32#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:50:16.32#ibcon#first serial, iclass 10, count 0 2006.257.05:50:16.32#ibcon#enter sib2, iclass 10, count 0 2006.257.05:50:16.32#ibcon#flushed, iclass 10, count 0 2006.257.05:50:16.32#ibcon#about to write, iclass 10, count 0 2006.257.05:50:16.32#ibcon#wrote, iclass 10, count 0 2006.257.05:50:16.32#ibcon#about to read 3, iclass 10, count 0 2006.257.05:50:16.34#ibcon#read 3, iclass 10, count 0 2006.257.05:50:16.34#ibcon#about to read 4, iclass 10, count 0 2006.257.05:50:16.34#ibcon#read 4, iclass 10, count 0 2006.257.05:50:16.34#ibcon#about to read 5, iclass 10, count 0 2006.257.05:50:16.34#ibcon#read 5, iclass 10, count 0 2006.257.05:50:16.34#ibcon#about to read 6, iclass 10, count 0 2006.257.05:50:16.34#ibcon#read 6, iclass 10, count 0 2006.257.05:50:16.34#ibcon#end of sib2, iclass 10, count 0 2006.257.05:50:16.34#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:50:16.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:50:16.34#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:50:16.34#ibcon#*before write, iclass 10, count 0 2006.257.05:50:16.34#ibcon#enter sib2, iclass 10, count 0 2006.257.05:50:16.34#ibcon#flushed, iclass 10, count 0 2006.257.05:50:16.34#ibcon#about to write, iclass 10, count 0 2006.257.05:50:16.34#ibcon#wrote, iclass 10, count 0 2006.257.05:50:16.34#ibcon#about to read 3, iclass 10, count 0 2006.257.05:50:16.38#ibcon#read 3, iclass 10, count 0 2006.257.05:50:16.38#ibcon#about to read 4, iclass 10, count 0 2006.257.05:50:16.38#ibcon#read 4, iclass 10, count 0 2006.257.05:50:16.38#ibcon#about to read 5, iclass 10, count 0 2006.257.05:50:16.38#ibcon#read 5, iclass 10, count 0 2006.257.05:50:16.38#ibcon#about to read 6, iclass 10, count 0 2006.257.05:50:16.38#ibcon#read 6, iclass 10, count 0 2006.257.05:50:16.38#ibcon#end of sib2, iclass 10, count 0 2006.257.05:50:16.38#ibcon#*after write, iclass 10, count 0 2006.257.05:50:16.38#ibcon#*before return 0, iclass 10, count 0 2006.257.05:50:16.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:16.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.05:50:16.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:50:16.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:50:16.38$vck44/vb=5,4 2006.257.05:50:16.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.05:50:16.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.05:50:16.38#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:16.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:16.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:16.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:16.44#ibcon#enter wrdev, iclass 12, count 2 2006.257.05:50:16.44#ibcon#first serial, iclass 12, count 2 2006.257.05:50:16.44#ibcon#enter sib2, iclass 12, count 2 2006.257.05:50:16.44#ibcon#flushed, iclass 12, count 2 2006.257.05:50:16.44#ibcon#about to write, iclass 12, count 2 2006.257.05:50:16.44#ibcon#wrote, iclass 12, count 2 2006.257.05:50:16.44#ibcon#about to read 3, iclass 12, count 2 2006.257.05:50:16.46#ibcon#read 3, iclass 12, count 2 2006.257.05:50:16.46#ibcon#about to read 4, iclass 12, count 2 2006.257.05:50:16.46#ibcon#read 4, iclass 12, count 2 2006.257.05:50:16.46#ibcon#about to read 5, iclass 12, count 2 2006.257.05:50:16.46#ibcon#read 5, iclass 12, count 2 2006.257.05:50:16.46#ibcon#about to read 6, iclass 12, count 2 2006.257.05:50:16.46#ibcon#read 6, iclass 12, count 2 2006.257.05:50:16.46#ibcon#end of sib2, iclass 12, count 2 2006.257.05:50:16.46#ibcon#*mode == 0, iclass 12, count 2 2006.257.05:50:16.46#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.05:50:16.46#ibcon#[27=AT05-04\r\n] 2006.257.05:50:16.46#ibcon#*before write, iclass 12, count 2 2006.257.05:50:16.46#ibcon#enter sib2, iclass 12, count 2 2006.257.05:50:16.46#ibcon#flushed, iclass 12, count 2 2006.257.05:50:16.46#ibcon#about to write, iclass 12, count 2 2006.257.05:50:16.46#ibcon#wrote, iclass 12, count 2 2006.257.05:50:16.46#ibcon#about to read 3, iclass 12, count 2 2006.257.05:50:16.49#ibcon#read 3, iclass 12, count 2 2006.257.05:50:16.49#ibcon#about to read 4, iclass 12, count 2 2006.257.05:50:16.49#ibcon#read 4, iclass 12, count 2 2006.257.05:50:16.49#ibcon#about to read 5, iclass 12, count 2 2006.257.05:50:16.49#ibcon#read 5, iclass 12, count 2 2006.257.05:50:16.49#ibcon#about to read 6, iclass 12, count 2 2006.257.05:50:16.49#ibcon#read 6, iclass 12, count 2 2006.257.05:50:16.49#ibcon#end of sib2, iclass 12, count 2 2006.257.05:50:16.49#ibcon#*after write, iclass 12, count 2 2006.257.05:50:16.49#ibcon#*before return 0, iclass 12, count 2 2006.257.05:50:16.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:16.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.05:50:16.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.05:50:16.49#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:16.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:16.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:16.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:16.61#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:50:16.61#ibcon#first serial, iclass 12, count 0 2006.257.05:50:16.61#ibcon#enter sib2, iclass 12, count 0 2006.257.05:50:16.61#ibcon#flushed, iclass 12, count 0 2006.257.05:50:16.61#ibcon#about to write, iclass 12, count 0 2006.257.05:50:16.61#ibcon#wrote, iclass 12, count 0 2006.257.05:50:16.61#ibcon#about to read 3, iclass 12, count 0 2006.257.05:50:16.63#ibcon#read 3, iclass 12, count 0 2006.257.05:50:16.63#ibcon#about to read 4, iclass 12, count 0 2006.257.05:50:16.63#ibcon#read 4, iclass 12, count 0 2006.257.05:50:16.63#ibcon#about to read 5, iclass 12, count 0 2006.257.05:50:16.63#ibcon#read 5, iclass 12, count 0 2006.257.05:50:16.63#ibcon#about to read 6, iclass 12, count 0 2006.257.05:50:16.63#ibcon#read 6, iclass 12, count 0 2006.257.05:50:16.63#ibcon#end of sib2, iclass 12, count 0 2006.257.05:50:16.63#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:50:16.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:50:16.63#ibcon#[27=USB\r\n] 2006.257.05:50:16.63#ibcon#*before write, iclass 12, count 0 2006.257.05:50:16.63#ibcon#enter sib2, iclass 12, count 0 2006.257.05:50:16.63#ibcon#flushed, iclass 12, count 0 2006.257.05:50:16.63#ibcon#about to write, iclass 12, count 0 2006.257.05:50:16.63#ibcon#wrote, iclass 12, count 0 2006.257.05:50:16.63#ibcon#about to read 3, iclass 12, count 0 2006.257.05:50:16.66#ibcon#read 3, iclass 12, count 0 2006.257.05:50:16.66#ibcon#about to read 4, iclass 12, count 0 2006.257.05:50:16.66#ibcon#read 4, iclass 12, count 0 2006.257.05:50:16.66#ibcon#about to read 5, iclass 12, count 0 2006.257.05:50:16.66#ibcon#read 5, iclass 12, count 0 2006.257.05:50:16.66#ibcon#about to read 6, iclass 12, count 0 2006.257.05:50:16.66#ibcon#read 6, iclass 12, count 0 2006.257.05:50:16.66#ibcon#end of sib2, iclass 12, count 0 2006.257.05:50:16.66#ibcon#*after write, iclass 12, count 0 2006.257.05:50:16.66#ibcon#*before return 0, iclass 12, count 0 2006.257.05:50:16.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:16.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.05:50:16.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:50:16.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:50:16.66$vck44/vblo=6,719.99 2006.257.05:50:16.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.05:50:16.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.05:50:16.66#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:16.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:16.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:16.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:16.66#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:50:16.66#ibcon#first serial, iclass 14, count 0 2006.257.05:50:16.66#ibcon#enter sib2, iclass 14, count 0 2006.257.05:50:16.66#ibcon#flushed, iclass 14, count 0 2006.257.05:50:16.66#ibcon#about to write, iclass 14, count 0 2006.257.05:50:16.66#ibcon#wrote, iclass 14, count 0 2006.257.05:50:16.66#ibcon#about to read 3, iclass 14, count 0 2006.257.05:50:16.68#ibcon#read 3, iclass 14, count 0 2006.257.05:50:16.68#ibcon#about to read 4, iclass 14, count 0 2006.257.05:50:16.68#ibcon#read 4, iclass 14, count 0 2006.257.05:50:16.68#ibcon#about to read 5, iclass 14, count 0 2006.257.05:50:16.68#ibcon#read 5, iclass 14, count 0 2006.257.05:50:16.68#ibcon#about to read 6, iclass 14, count 0 2006.257.05:50:16.68#ibcon#read 6, iclass 14, count 0 2006.257.05:50:16.68#ibcon#end of sib2, iclass 14, count 0 2006.257.05:50:16.68#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:50:16.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:50:16.68#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:50:16.68#ibcon#*before write, iclass 14, count 0 2006.257.05:50:16.68#ibcon#enter sib2, iclass 14, count 0 2006.257.05:50:16.68#ibcon#flushed, iclass 14, count 0 2006.257.05:50:16.68#ibcon#about to write, iclass 14, count 0 2006.257.05:50:16.68#ibcon#wrote, iclass 14, count 0 2006.257.05:50:16.68#ibcon#about to read 3, iclass 14, count 0 2006.257.05:50:16.72#ibcon#read 3, iclass 14, count 0 2006.257.05:50:16.72#ibcon#about to read 4, iclass 14, count 0 2006.257.05:50:16.72#ibcon#read 4, iclass 14, count 0 2006.257.05:50:16.72#ibcon#about to read 5, iclass 14, count 0 2006.257.05:50:16.72#ibcon#read 5, iclass 14, count 0 2006.257.05:50:16.72#ibcon#about to read 6, iclass 14, count 0 2006.257.05:50:16.72#ibcon#read 6, iclass 14, count 0 2006.257.05:50:16.72#ibcon#end of sib2, iclass 14, count 0 2006.257.05:50:16.72#ibcon#*after write, iclass 14, count 0 2006.257.05:50:16.72#ibcon#*before return 0, iclass 14, count 0 2006.257.05:50:16.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:16.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.05:50:16.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:50:16.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:50:16.72$vck44/vb=6,4 2006.257.05:50:16.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.05:50:16.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.05:50:16.72#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:16.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:16.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:16.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:16.78#ibcon#enter wrdev, iclass 16, count 2 2006.257.05:50:16.78#ibcon#first serial, iclass 16, count 2 2006.257.05:50:16.78#ibcon#enter sib2, iclass 16, count 2 2006.257.05:50:16.78#ibcon#flushed, iclass 16, count 2 2006.257.05:50:16.78#ibcon#about to write, iclass 16, count 2 2006.257.05:50:16.78#ibcon#wrote, iclass 16, count 2 2006.257.05:50:16.78#ibcon#about to read 3, iclass 16, count 2 2006.257.05:50:16.80#ibcon#read 3, iclass 16, count 2 2006.257.05:50:16.80#ibcon#about to read 4, iclass 16, count 2 2006.257.05:50:16.80#ibcon#read 4, iclass 16, count 2 2006.257.05:50:16.80#ibcon#about to read 5, iclass 16, count 2 2006.257.05:50:16.80#ibcon#read 5, iclass 16, count 2 2006.257.05:50:16.80#ibcon#about to read 6, iclass 16, count 2 2006.257.05:50:16.80#ibcon#read 6, iclass 16, count 2 2006.257.05:50:16.80#ibcon#end of sib2, iclass 16, count 2 2006.257.05:50:16.80#ibcon#*mode == 0, iclass 16, count 2 2006.257.05:50:16.80#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.05:50:16.80#ibcon#[27=AT06-04\r\n] 2006.257.05:50:16.80#ibcon#*before write, iclass 16, count 2 2006.257.05:50:16.80#ibcon#enter sib2, iclass 16, count 2 2006.257.05:50:16.80#ibcon#flushed, iclass 16, count 2 2006.257.05:50:16.80#ibcon#about to write, iclass 16, count 2 2006.257.05:50:16.80#ibcon#wrote, iclass 16, count 2 2006.257.05:50:16.80#ibcon#about to read 3, iclass 16, count 2 2006.257.05:50:16.83#ibcon#read 3, iclass 16, count 2 2006.257.05:50:16.83#ibcon#about to read 4, iclass 16, count 2 2006.257.05:50:16.83#ibcon#read 4, iclass 16, count 2 2006.257.05:50:16.83#ibcon#about to read 5, iclass 16, count 2 2006.257.05:50:16.83#ibcon#read 5, iclass 16, count 2 2006.257.05:50:16.83#ibcon#about to read 6, iclass 16, count 2 2006.257.05:50:16.83#ibcon#read 6, iclass 16, count 2 2006.257.05:50:16.83#ibcon#end of sib2, iclass 16, count 2 2006.257.05:50:16.83#ibcon#*after write, iclass 16, count 2 2006.257.05:50:16.83#ibcon#*before return 0, iclass 16, count 2 2006.257.05:50:16.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:16.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.05:50:16.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.05:50:16.83#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:16.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:16.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:16.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:16.95#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:50:16.95#ibcon#first serial, iclass 16, count 0 2006.257.05:50:16.95#ibcon#enter sib2, iclass 16, count 0 2006.257.05:50:16.95#ibcon#flushed, iclass 16, count 0 2006.257.05:50:16.95#ibcon#about to write, iclass 16, count 0 2006.257.05:50:16.95#ibcon#wrote, iclass 16, count 0 2006.257.05:50:16.95#ibcon#about to read 3, iclass 16, count 0 2006.257.05:50:16.97#ibcon#read 3, iclass 16, count 0 2006.257.05:50:16.97#ibcon#about to read 4, iclass 16, count 0 2006.257.05:50:16.97#ibcon#read 4, iclass 16, count 0 2006.257.05:50:16.97#ibcon#about to read 5, iclass 16, count 0 2006.257.05:50:16.97#ibcon#read 5, iclass 16, count 0 2006.257.05:50:16.97#ibcon#about to read 6, iclass 16, count 0 2006.257.05:50:16.97#ibcon#read 6, iclass 16, count 0 2006.257.05:50:16.97#ibcon#end of sib2, iclass 16, count 0 2006.257.05:50:16.97#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:50:16.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:50:16.97#ibcon#[27=USB\r\n] 2006.257.05:50:16.97#ibcon#*before write, iclass 16, count 0 2006.257.05:50:16.97#ibcon#enter sib2, iclass 16, count 0 2006.257.05:50:16.97#ibcon#flushed, iclass 16, count 0 2006.257.05:50:16.97#ibcon#about to write, iclass 16, count 0 2006.257.05:50:16.97#ibcon#wrote, iclass 16, count 0 2006.257.05:50:16.97#ibcon#about to read 3, iclass 16, count 0 2006.257.05:50:17.00#ibcon#read 3, iclass 16, count 0 2006.257.05:50:17.00#ibcon#about to read 4, iclass 16, count 0 2006.257.05:50:17.00#ibcon#read 4, iclass 16, count 0 2006.257.05:50:17.00#ibcon#about to read 5, iclass 16, count 0 2006.257.05:50:17.00#ibcon#read 5, iclass 16, count 0 2006.257.05:50:17.00#ibcon#about to read 6, iclass 16, count 0 2006.257.05:50:17.00#ibcon#read 6, iclass 16, count 0 2006.257.05:50:17.00#ibcon#end of sib2, iclass 16, count 0 2006.257.05:50:17.00#ibcon#*after write, iclass 16, count 0 2006.257.05:50:17.00#ibcon#*before return 0, iclass 16, count 0 2006.257.05:50:17.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:17.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.05:50:17.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:50:17.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:50:17.00$vck44/vblo=7,734.99 2006.257.05:50:17.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.05:50:17.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.05:50:17.00#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:17.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:17.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:17.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:17.00#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:50:17.00#ibcon#first serial, iclass 18, count 0 2006.257.05:50:17.00#ibcon#enter sib2, iclass 18, count 0 2006.257.05:50:17.00#ibcon#flushed, iclass 18, count 0 2006.257.05:50:17.00#ibcon#about to write, iclass 18, count 0 2006.257.05:50:17.00#ibcon#wrote, iclass 18, count 0 2006.257.05:50:17.00#ibcon#about to read 3, iclass 18, count 0 2006.257.05:50:17.02#ibcon#read 3, iclass 18, count 0 2006.257.05:50:17.02#ibcon#about to read 4, iclass 18, count 0 2006.257.05:50:17.02#ibcon#read 4, iclass 18, count 0 2006.257.05:50:17.02#ibcon#about to read 5, iclass 18, count 0 2006.257.05:50:17.02#ibcon#read 5, iclass 18, count 0 2006.257.05:50:17.02#ibcon#about to read 6, iclass 18, count 0 2006.257.05:50:17.02#ibcon#read 6, iclass 18, count 0 2006.257.05:50:17.02#ibcon#end of sib2, iclass 18, count 0 2006.257.05:50:17.02#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:50:17.02#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:50:17.02#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:50:17.02#ibcon#*before write, iclass 18, count 0 2006.257.05:50:17.02#ibcon#enter sib2, iclass 18, count 0 2006.257.05:50:17.02#ibcon#flushed, iclass 18, count 0 2006.257.05:50:17.02#ibcon#about to write, iclass 18, count 0 2006.257.05:50:17.02#ibcon#wrote, iclass 18, count 0 2006.257.05:50:17.02#ibcon#about to read 3, iclass 18, count 0 2006.257.05:50:17.06#ibcon#read 3, iclass 18, count 0 2006.257.05:50:17.06#ibcon#about to read 4, iclass 18, count 0 2006.257.05:50:17.06#ibcon#read 4, iclass 18, count 0 2006.257.05:50:17.06#ibcon#about to read 5, iclass 18, count 0 2006.257.05:50:17.06#ibcon#read 5, iclass 18, count 0 2006.257.05:50:17.06#ibcon#about to read 6, iclass 18, count 0 2006.257.05:50:17.06#ibcon#read 6, iclass 18, count 0 2006.257.05:50:17.06#ibcon#end of sib2, iclass 18, count 0 2006.257.05:50:17.06#ibcon#*after write, iclass 18, count 0 2006.257.05:50:17.06#ibcon#*before return 0, iclass 18, count 0 2006.257.05:50:17.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:17.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.05:50:17.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:50:17.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:50:17.06$vck44/vb=7,4 2006.257.05:50:17.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.05:50:17.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.05:50:17.06#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:17.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:17.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:17.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:17.12#ibcon#enter wrdev, iclass 20, count 2 2006.257.05:50:17.12#ibcon#first serial, iclass 20, count 2 2006.257.05:50:17.12#ibcon#enter sib2, iclass 20, count 2 2006.257.05:50:17.12#ibcon#flushed, iclass 20, count 2 2006.257.05:50:17.12#ibcon#about to write, iclass 20, count 2 2006.257.05:50:17.12#ibcon#wrote, iclass 20, count 2 2006.257.05:50:17.12#ibcon#about to read 3, iclass 20, count 2 2006.257.05:50:17.14#ibcon#read 3, iclass 20, count 2 2006.257.05:50:17.14#ibcon#about to read 4, iclass 20, count 2 2006.257.05:50:17.14#ibcon#read 4, iclass 20, count 2 2006.257.05:50:17.14#ibcon#about to read 5, iclass 20, count 2 2006.257.05:50:17.14#ibcon#read 5, iclass 20, count 2 2006.257.05:50:17.14#ibcon#about to read 6, iclass 20, count 2 2006.257.05:50:17.14#ibcon#read 6, iclass 20, count 2 2006.257.05:50:17.14#ibcon#end of sib2, iclass 20, count 2 2006.257.05:50:17.14#ibcon#*mode == 0, iclass 20, count 2 2006.257.05:50:17.14#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.05:50:17.14#ibcon#[27=AT07-04\r\n] 2006.257.05:50:17.14#ibcon#*before write, iclass 20, count 2 2006.257.05:50:17.14#ibcon#enter sib2, iclass 20, count 2 2006.257.05:50:17.14#ibcon#flushed, iclass 20, count 2 2006.257.05:50:17.14#ibcon#about to write, iclass 20, count 2 2006.257.05:50:17.14#ibcon#wrote, iclass 20, count 2 2006.257.05:50:17.14#ibcon#about to read 3, iclass 20, count 2 2006.257.05:50:17.17#ibcon#read 3, iclass 20, count 2 2006.257.05:50:17.17#ibcon#about to read 4, iclass 20, count 2 2006.257.05:50:17.17#ibcon#read 4, iclass 20, count 2 2006.257.05:50:17.17#ibcon#about to read 5, iclass 20, count 2 2006.257.05:50:17.17#ibcon#read 5, iclass 20, count 2 2006.257.05:50:17.17#ibcon#about to read 6, iclass 20, count 2 2006.257.05:50:17.17#ibcon#read 6, iclass 20, count 2 2006.257.05:50:17.17#ibcon#end of sib2, iclass 20, count 2 2006.257.05:50:17.17#ibcon#*after write, iclass 20, count 2 2006.257.05:50:17.17#ibcon#*before return 0, iclass 20, count 2 2006.257.05:50:17.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:17.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.05:50:17.17#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.05:50:17.17#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:17.17#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:17.29#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:17.29#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:17.29#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:50:17.29#ibcon#first serial, iclass 20, count 0 2006.257.05:50:17.29#ibcon#enter sib2, iclass 20, count 0 2006.257.05:50:17.29#ibcon#flushed, iclass 20, count 0 2006.257.05:50:17.29#ibcon#about to write, iclass 20, count 0 2006.257.05:50:17.29#ibcon#wrote, iclass 20, count 0 2006.257.05:50:17.29#ibcon#about to read 3, iclass 20, count 0 2006.257.05:50:17.31#ibcon#read 3, iclass 20, count 0 2006.257.05:50:17.31#ibcon#about to read 4, iclass 20, count 0 2006.257.05:50:17.31#ibcon#read 4, iclass 20, count 0 2006.257.05:50:17.31#ibcon#about to read 5, iclass 20, count 0 2006.257.05:50:17.31#ibcon#read 5, iclass 20, count 0 2006.257.05:50:17.31#ibcon#about to read 6, iclass 20, count 0 2006.257.05:50:17.31#ibcon#read 6, iclass 20, count 0 2006.257.05:50:17.31#ibcon#end of sib2, iclass 20, count 0 2006.257.05:50:17.31#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:50:17.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:50:17.31#ibcon#[27=USB\r\n] 2006.257.05:50:17.31#ibcon#*before write, iclass 20, count 0 2006.257.05:50:17.31#ibcon#enter sib2, iclass 20, count 0 2006.257.05:50:17.31#ibcon#flushed, iclass 20, count 0 2006.257.05:50:17.31#ibcon#about to write, iclass 20, count 0 2006.257.05:50:17.31#ibcon#wrote, iclass 20, count 0 2006.257.05:50:17.31#ibcon#about to read 3, iclass 20, count 0 2006.257.05:50:17.34#ibcon#read 3, iclass 20, count 0 2006.257.05:50:17.34#ibcon#about to read 4, iclass 20, count 0 2006.257.05:50:17.34#ibcon#read 4, iclass 20, count 0 2006.257.05:50:17.34#ibcon#about to read 5, iclass 20, count 0 2006.257.05:50:17.34#ibcon#read 5, iclass 20, count 0 2006.257.05:50:17.34#ibcon#about to read 6, iclass 20, count 0 2006.257.05:50:17.34#ibcon#read 6, iclass 20, count 0 2006.257.05:50:17.34#ibcon#end of sib2, iclass 20, count 0 2006.257.05:50:17.34#ibcon#*after write, iclass 20, count 0 2006.257.05:50:17.34#ibcon#*before return 0, iclass 20, count 0 2006.257.05:50:17.34#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:17.34#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.05:50:17.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:50:17.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:50:17.34$vck44/vblo=8,744.99 2006.257.05:50:17.34#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.05:50:17.34#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.05:50:17.34#ibcon#ireg 17 cls_cnt 0 2006.257.05:50:17.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:17.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:17.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:17.34#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:50:17.34#ibcon#first serial, iclass 22, count 0 2006.257.05:50:17.34#ibcon#enter sib2, iclass 22, count 0 2006.257.05:50:17.34#ibcon#flushed, iclass 22, count 0 2006.257.05:50:17.34#ibcon#about to write, iclass 22, count 0 2006.257.05:50:17.34#ibcon#wrote, iclass 22, count 0 2006.257.05:50:17.34#ibcon#about to read 3, iclass 22, count 0 2006.257.05:50:17.36#ibcon#read 3, iclass 22, count 0 2006.257.05:50:17.36#ibcon#about to read 4, iclass 22, count 0 2006.257.05:50:17.36#ibcon#read 4, iclass 22, count 0 2006.257.05:50:17.36#ibcon#about to read 5, iclass 22, count 0 2006.257.05:50:17.36#ibcon#read 5, iclass 22, count 0 2006.257.05:50:17.36#ibcon#about to read 6, iclass 22, count 0 2006.257.05:50:17.36#ibcon#read 6, iclass 22, count 0 2006.257.05:50:17.36#ibcon#end of sib2, iclass 22, count 0 2006.257.05:50:17.36#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:50:17.36#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:50:17.36#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:50:17.36#ibcon#*before write, iclass 22, count 0 2006.257.05:50:17.36#ibcon#enter sib2, iclass 22, count 0 2006.257.05:50:17.36#ibcon#flushed, iclass 22, count 0 2006.257.05:50:17.36#ibcon#about to write, iclass 22, count 0 2006.257.05:50:17.36#ibcon#wrote, iclass 22, count 0 2006.257.05:50:17.36#ibcon#about to read 3, iclass 22, count 0 2006.257.05:50:17.40#ibcon#read 3, iclass 22, count 0 2006.257.05:50:17.40#ibcon#about to read 4, iclass 22, count 0 2006.257.05:50:17.40#ibcon#read 4, iclass 22, count 0 2006.257.05:50:17.40#ibcon#about to read 5, iclass 22, count 0 2006.257.05:50:17.40#ibcon#read 5, iclass 22, count 0 2006.257.05:50:17.40#ibcon#about to read 6, iclass 22, count 0 2006.257.05:50:17.40#ibcon#read 6, iclass 22, count 0 2006.257.05:50:17.40#ibcon#end of sib2, iclass 22, count 0 2006.257.05:50:17.40#ibcon#*after write, iclass 22, count 0 2006.257.05:50:17.40#ibcon#*before return 0, iclass 22, count 0 2006.257.05:50:17.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:17.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.05:50:17.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:50:17.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:50:17.40$vck44/vb=8,4 2006.257.05:50:17.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.05:50:17.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.05:50:17.40#ibcon#ireg 11 cls_cnt 2 2006.257.05:50:17.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:17.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:17.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:17.46#ibcon#enter wrdev, iclass 24, count 2 2006.257.05:50:17.46#ibcon#first serial, iclass 24, count 2 2006.257.05:50:17.46#ibcon#enter sib2, iclass 24, count 2 2006.257.05:50:17.46#ibcon#flushed, iclass 24, count 2 2006.257.05:50:17.46#ibcon#about to write, iclass 24, count 2 2006.257.05:50:17.46#ibcon#wrote, iclass 24, count 2 2006.257.05:50:17.46#ibcon#about to read 3, iclass 24, count 2 2006.257.05:50:17.48#ibcon#read 3, iclass 24, count 2 2006.257.05:50:17.48#ibcon#about to read 4, iclass 24, count 2 2006.257.05:50:17.48#ibcon#read 4, iclass 24, count 2 2006.257.05:50:17.48#ibcon#about to read 5, iclass 24, count 2 2006.257.05:50:17.48#ibcon#read 5, iclass 24, count 2 2006.257.05:50:17.48#ibcon#about to read 6, iclass 24, count 2 2006.257.05:50:17.48#ibcon#read 6, iclass 24, count 2 2006.257.05:50:17.48#ibcon#end of sib2, iclass 24, count 2 2006.257.05:50:17.48#ibcon#*mode == 0, iclass 24, count 2 2006.257.05:50:17.48#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.05:50:17.48#ibcon#[27=AT08-04\r\n] 2006.257.05:50:17.48#ibcon#*before write, iclass 24, count 2 2006.257.05:50:17.48#ibcon#enter sib2, iclass 24, count 2 2006.257.05:50:17.48#ibcon#flushed, iclass 24, count 2 2006.257.05:50:17.48#ibcon#about to write, iclass 24, count 2 2006.257.05:50:17.48#ibcon#wrote, iclass 24, count 2 2006.257.05:50:17.48#ibcon#about to read 3, iclass 24, count 2 2006.257.05:50:17.51#ibcon#read 3, iclass 24, count 2 2006.257.05:50:17.51#ibcon#about to read 4, iclass 24, count 2 2006.257.05:50:17.51#ibcon#read 4, iclass 24, count 2 2006.257.05:50:17.51#ibcon#about to read 5, iclass 24, count 2 2006.257.05:50:17.51#ibcon#read 5, iclass 24, count 2 2006.257.05:50:17.51#ibcon#about to read 6, iclass 24, count 2 2006.257.05:50:17.51#ibcon#read 6, iclass 24, count 2 2006.257.05:50:17.51#ibcon#end of sib2, iclass 24, count 2 2006.257.05:50:17.51#ibcon#*after write, iclass 24, count 2 2006.257.05:50:17.51#ibcon#*before return 0, iclass 24, count 2 2006.257.05:50:17.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:17.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.05:50:17.51#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.05:50:17.51#ibcon#ireg 7 cls_cnt 0 2006.257.05:50:17.51#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:17.63#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:17.63#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:17.63#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:50:17.63#ibcon#first serial, iclass 24, count 0 2006.257.05:50:17.63#ibcon#enter sib2, iclass 24, count 0 2006.257.05:50:17.63#ibcon#flushed, iclass 24, count 0 2006.257.05:50:17.63#ibcon#about to write, iclass 24, count 0 2006.257.05:50:17.63#ibcon#wrote, iclass 24, count 0 2006.257.05:50:17.63#ibcon#about to read 3, iclass 24, count 0 2006.257.05:50:17.65#ibcon#read 3, iclass 24, count 0 2006.257.05:50:17.65#ibcon#about to read 4, iclass 24, count 0 2006.257.05:50:17.65#ibcon#read 4, iclass 24, count 0 2006.257.05:50:17.65#ibcon#about to read 5, iclass 24, count 0 2006.257.05:50:17.65#ibcon#read 5, iclass 24, count 0 2006.257.05:50:17.65#ibcon#about to read 6, iclass 24, count 0 2006.257.05:50:17.65#ibcon#read 6, iclass 24, count 0 2006.257.05:50:17.65#ibcon#end of sib2, iclass 24, count 0 2006.257.05:50:17.65#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:50:17.65#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:50:17.65#ibcon#[27=USB\r\n] 2006.257.05:50:17.65#ibcon#*before write, iclass 24, count 0 2006.257.05:50:17.65#ibcon#enter sib2, iclass 24, count 0 2006.257.05:50:17.65#ibcon#flushed, iclass 24, count 0 2006.257.05:50:17.65#ibcon#about to write, iclass 24, count 0 2006.257.05:50:17.65#ibcon#wrote, iclass 24, count 0 2006.257.05:50:17.65#ibcon#about to read 3, iclass 24, count 0 2006.257.05:50:17.68#ibcon#read 3, iclass 24, count 0 2006.257.05:50:17.68#ibcon#about to read 4, iclass 24, count 0 2006.257.05:50:17.68#ibcon#read 4, iclass 24, count 0 2006.257.05:50:17.68#ibcon#about to read 5, iclass 24, count 0 2006.257.05:50:17.68#ibcon#read 5, iclass 24, count 0 2006.257.05:50:17.68#ibcon#about to read 6, iclass 24, count 0 2006.257.05:50:17.68#ibcon#read 6, iclass 24, count 0 2006.257.05:50:17.68#ibcon#end of sib2, iclass 24, count 0 2006.257.05:50:17.68#ibcon#*after write, iclass 24, count 0 2006.257.05:50:17.68#ibcon#*before return 0, iclass 24, count 0 2006.257.05:50:17.68#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:17.68#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.05:50:17.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:50:17.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:50:17.68$vck44/vabw=wide 2006.257.05:50:17.68#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.05:50:17.68#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.05:50:17.68#ibcon#ireg 8 cls_cnt 0 2006.257.05:50:17.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:17.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:17.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:17.68#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:50:17.68#ibcon#first serial, iclass 26, count 0 2006.257.05:50:17.68#ibcon#enter sib2, iclass 26, count 0 2006.257.05:50:17.68#ibcon#flushed, iclass 26, count 0 2006.257.05:50:17.68#ibcon#about to write, iclass 26, count 0 2006.257.05:50:17.68#ibcon#wrote, iclass 26, count 0 2006.257.05:50:17.68#ibcon#about to read 3, iclass 26, count 0 2006.257.05:50:17.70#ibcon#read 3, iclass 26, count 0 2006.257.05:50:17.70#ibcon#about to read 4, iclass 26, count 0 2006.257.05:50:17.70#ibcon#read 4, iclass 26, count 0 2006.257.05:50:17.70#ibcon#about to read 5, iclass 26, count 0 2006.257.05:50:17.70#ibcon#read 5, iclass 26, count 0 2006.257.05:50:17.70#ibcon#about to read 6, iclass 26, count 0 2006.257.05:50:17.70#ibcon#read 6, iclass 26, count 0 2006.257.05:50:17.70#ibcon#end of sib2, iclass 26, count 0 2006.257.05:50:17.70#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:50:17.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:50:17.70#ibcon#[25=BW32\r\n] 2006.257.05:50:17.70#ibcon#*before write, iclass 26, count 0 2006.257.05:50:17.70#ibcon#enter sib2, iclass 26, count 0 2006.257.05:50:17.70#ibcon#flushed, iclass 26, count 0 2006.257.05:50:17.70#ibcon#about to write, iclass 26, count 0 2006.257.05:50:17.70#ibcon#wrote, iclass 26, count 0 2006.257.05:50:17.70#ibcon#about to read 3, iclass 26, count 0 2006.257.05:50:17.73#ibcon#read 3, iclass 26, count 0 2006.257.05:50:17.73#ibcon#about to read 4, iclass 26, count 0 2006.257.05:50:17.73#ibcon#read 4, iclass 26, count 0 2006.257.05:50:17.73#ibcon#about to read 5, iclass 26, count 0 2006.257.05:50:17.73#ibcon#read 5, iclass 26, count 0 2006.257.05:50:17.73#ibcon#about to read 6, iclass 26, count 0 2006.257.05:50:17.73#ibcon#read 6, iclass 26, count 0 2006.257.05:50:17.73#ibcon#end of sib2, iclass 26, count 0 2006.257.05:50:17.73#ibcon#*after write, iclass 26, count 0 2006.257.05:50:17.73#ibcon#*before return 0, iclass 26, count 0 2006.257.05:50:17.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:17.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.05:50:17.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:50:17.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:50:17.73$vck44/vbbw=wide 2006.257.05:50:17.73#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.05:50:17.73#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.05:50:17.73#ibcon#ireg 8 cls_cnt 0 2006.257.05:50:17.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:50:17.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:50:17.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:50:17.80#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:50:17.80#ibcon#first serial, iclass 28, count 0 2006.257.05:50:17.80#ibcon#enter sib2, iclass 28, count 0 2006.257.05:50:17.80#ibcon#flushed, iclass 28, count 0 2006.257.05:50:17.80#ibcon#about to write, iclass 28, count 0 2006.257.05:50:17.80#ibcon#wrote, iclass 28, count 0 2006.257.05:50:17.80#ibcon#about to read 3, iclass 28, count 0 2006.257.05:50:17.82#ibcon#read 3, iclass 28, count 0 2006.257.05:50:17.82#ibcon#about to read 4, iclass 28, count 0 2006.257.05:50:17.82#ibcon#read 4, iclass 28, count 0 2006.257.05:50:17.82#ibcon#about to read 5, iclass 28, count 0 2006.257.05:50:17.82#ibcon#read 5, iclass 28, count 0 2006.257.05:50:17.82#ibcon#about to read 6, iclass 28, count 0 2006.257.05:50:17.82#ibcon#read 6, iclass 28, count 0 2006.257.05:50:17.82#ibcon#end of sib2, iclass 28, count 0 2006.257.05:50:17.82#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:50:17.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:50:17.82#ibcon#[27=BW32\r\n] 2006.257.05:50:17.82#ibcon#*before write, iclass 28, count 0 2006.257.05:50:17.82#ibcon#enter sib2, iclass 28, count 0 2006.257.05:50:17.82#ibcon#flushed, iclass 28, count 0 2006.257.05:50:17.82#ibcon#about to write, iclass 28, count 0 2006.257.05:50:17.82#ibcon#wrote, iclass 28, count 0 2006.257.05:50:17.82#ibcon#about to read 3, iclass 28, count 0 2006.257.05:50:17.85#ibcon#read 3, iclass 28, count 0 2006.257.05:50:17.85#ibcon#about to read 4, iclass 28, count 0 2006.257.05:50:17.85#ibcon#read 4, iclass 28, count 0 2006.257.05:50:17.85#ibcon#about to read 5, iclass 28, count 0 2006.257.05:50:17.85#ibcon#read 5, iclass 28, count 0 2006.257.05:50:17.85#ibcon#about to read 6, iclass 28, count 0 2006.257.05:50:17.85#ibcon#read 6, iclass 28, count 0 2006.257.05:50:17.85#ibcon#end of sib2, iclass 28, count 0 2006.257.05:50:17.85#ibcon#*after write, iclass 28, count 0 2006.257.05:50:17.85#ibcon#*before return 0, iclass 28, count 0 2006.257.05:50:17.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:50:17.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:50:17.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:50:17.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:50:17.85$setupk4/ifdk4 2006.257.05:50:17.85$ifdk4/lo= 2006.257.05:50:17.85$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:50:17.85$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:50:17.85$ifdk4/patch= 2006.257.05:50:17.85$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:50:17.85$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:50:17.85$setupk4/!*+20s 2006.257.05:50:21.80#abcon#<5=/16 1.5 4.8 20.05 901012.1\r\n> 2006.257.05:50:21.82#abcon#{5=INTERFACE CLEAR} 2006.257.05:50:21.88#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:50:31.97#abcon#<5=/16 1.5 4.4 20.05 901012.1\r\n> 2006.257.05:50:31.99#abcon#{5=INTERFACE CLEAR} 2006.257.05:50:32.05#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:50:32.36$setupk4/"tpicd 2006.257.05:50:32.36$setupk4/echo=off 2006.257.05:50:32.36$setupk4/xlog=off 2006.257.05:50:32.36:!2006.257.05:53:30 2006.257.05:50:33.13#trakl#Source acquired 2006.257.05:50:35.14#flagr#flagr/antenna,acquired 2006.257.05:53:30.00:preob 2006.257.05:53:30.14/onsource/TRACKING 2006.257.05:53:30.14:!2006.257.05:53:40 2006.257.05:53:40.00:"tape 2006.257.05:53:40.00:"st=record 2006.257.05:53:40.00:data_valid=on 2006.257.05:53:40.00:midob 2006.257.05:53:41.14/onsource/TRACKING 2006.257.05:53:41.14/wx/20.06,1012.1,89 2006.257.05:53:41.35/cable/+6.4810E-03 2006.257.05:53:42.44/va/01,08,usb,yes,36,38 2006.257.05:53:42.44/va/02,07,usb,yes,39,39 2006.257.05:53:42.44/va/03,08,usb,yes,35,37 2006.257.05:53:42.44/va/04,07,usb,yes,40,42 2006.257.05:53:42.44/va/05,04,usb,yes,36,36 2006.257.05:53:42.44/va/06,04,usb,yes,40,39 2006.257.05:53:42.44/va/07,04,usb,yes,41,41 2006.257.05:53:42.44/va/08,04,usb,yes,34,42 2006.257.05:53:42.67/valo/01,524.99,yes,locked 2006.257.05:53:42.67/valo/02,534.99,yes,locked 2006.257.05:53:42.67/valo/03,564.99,yes,locked 2006.257.05:53:42.67/valo/04,624.99,yes,locked 2006.257.05:53:42.67/valo/05,734.99,yes,locked 2006.257.05:53:42.67/valo/06,814.99,yes,locked 2006.257.05:53:42.67/valo/07,864.99,yes,locked 2006.257.05:53:42.67/valo/08,884.99,yes,locked 2006.257.05:53:43.76/vb/01,04,usb,yes,33,31 2006.257.05:53:43.76/vb/02,05,usb,yes,32,31 2006.257.05:53:43.76/vb/03,04,usb,yes,32,36 2006.257.05:53:43.76/vb/04,05,usb,yes,33,32 2006.257.05:53:43.76/vb/05,04,usb,yes,29,32 2006.257.05:53:43.76/vb/06,04,usb,yes,34,30 2006.257.05:53:43.76/vb/07,04,usb,yes,34,34 2006.257.05:53:43.76/vb/08,04,usb,yes,31,35 2006.257.05:53:44.00/vblo/01,629.99,yes,locked 2006.257.05:53:44.00/vblo/02,634.99,yes,locked 2006.257.05:53:44.00/vblo/03,649.99,yes,locked 2006.257.05:53:44.00/vblo/04,679.99,yes,locked 2006.257.05:53:44.00/vblo/05,709.99,yes,locked 2006.257.05:53:44.00/vblo/06,719.99,yes,locked 2006.257.05:53:44.00/vblo/07,734.99,yes,locked 2006.257.05:53:44.00/vblo/08,744.99,yes,locked 2006.257.05:53:44.15/vabw/8 2006.257.05:53:44.30/vbbw/8 2006.257.05:53:44.39/xfe/off,on,16.7 2006.257.05:53:44.76/ifatt/23,28,28,28 2006.257.05:53:45.08/fmout-gps/S +4.52E-07 2006.257.05:53:45.12:!2006.257.05:54:20 2006.257.05:54:20.00:data_valid=off 2006.257.05:54:20.00:"et 2006.257.05:54:20.00:!+3s 2006.257.05:54:23.01:"tape 2006.257.05:54:23.01:postob 2006.257.05:54:23.24/cable/+6.4796E-03 2006.257.05:54:23.24/wx/20.06,1012.1,89 2006.257.05:54:24.08/fmout-gps/S +4.52E-07 2006.257.05:54:24.08:scan_name=257-0558,jd0609,40 2006.257.05:54:24.08:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.257.05:54:25.14#flagr#flagr/antenna,new-source 2006.257.05:54:25.14:checkk5 2006.257.05:54:25.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:54:25.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:54:26.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:54:26.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:54:27.15/chk_obsdata//k5ts1/T2570553??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.05:54:27.55/chk_obsdata//k5ts2/T2570553??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.05:54:27.95/chk_obsdata//k5ts3/T2570553??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.05:54:28.35/chk_obsdata//k5ts4/T2570553??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.05:54:29.08/k5log//k5ts1_log_newline 2006.257.05:54:29.80/k5log//k5ts2_log_newline 2006.257.05:54:30.54/k5log//k5ts3_log_newline 2006.257.05:54:31.26/k5log//k5ts4_log_newline 2006.257.05:54:31.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:54:31.28:setupk4=1 2006.257.05:54:31.28$setupk4/echo=on 2006.257.05:54:31.28$setupk4/pcalon 2006.257.05:54:31.28$pcalon/"no phase cal control is implemented here 2006.257.05:54:31.28$setupk4/"tpicd=stop 2006.257.05:54:31.28$setupk4/"rec=synch_on 2006.257.05:54:31.28$setupk4/"rec_mode=128 2006.257.05:54:31.28$setupk4/!* 2006.257.05:54:31.28$setupk4/recpk4 2006.257.05:54:31.28$recpk4/recpatch= 2006.257.05:54:31.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:54:31.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:54:31.29$setupk4/vck44 2006.257.05:54:31.29$vck44/valo=1,524.99 2006.257.05:54:31.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.05:54:31.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.05:54:31.29#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:31.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:31.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:31.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:31.29#ibcon#enter wrdev, iclass 25, count 0 2006.257.05:54:31.29#ibcon#first serial, iclass 25, count 0 2006.257.05:54:31.29#ibcon#enter sib2, iclass 25, count 0 2006.257.05:54:31.29#ibcon#flushed, iclass 25, count 0 2006.257.05:54:31.29#ibcon#about to write, iclass 25, count 0 2006.257.05:54:31.29#ibcon#wrote, iclass 25, count 0 2006.257.05:54:31.29#ibcon#about to read 3, iclass 25, count 0 2006.257.05:54:31.31#ibcon#read 3, iclass 25, count 0 2006.257.05:54:31.31#ibcon#about to read 4, iclass 25, count 0 2006.257.05:54:31.31#ibcon#read 4, iclass 25, count 0 2006.257.05:54:31.31#ibcon#about to read 5, iclass 25, count 0 2006.257.05:54:31.31#ibcon#read 5, iclass 25, count 0 2006.257.05:54:31.31#ibcon#about to read 6, iclass 25, count 0 2006.257.05:54:31.31#ibcon#read 6, iclass 25, count 0 2006.257.05:54:31.31#ibcon#end of sib2, iclass 25, count 0 2006.257.05:54:31.31#ibcon#*mode == 0, iclass 25, count 0 2006.257.05:54:31.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.05:54:31.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:54:31.31#ibcon#*before write, iclass 25, count 0 2006.257.05:54:31.31#ibcon#enter sib2, iclass 25, count 0 2006.257.05:54:31.31#ibcon#flushed, iclass 25, count 0 2006.257.05:54:31.31#ibcon#about to write, iclass 25, count 0 2006.257.05:54:31.31#ibcon#wrote, iclass 25, count 0 2006.257.05:54:31.31#ibcon#about to read 3, iclass 25, count 0 2006.257.05:54:31.36#ibcon#read 3, iclass 25, count 0 2006.257.05:54:31.36#ibcon#about to read 4, iclass 25, count 0 2006.257.05:54:31.36#ibcon#read 4, iclass 25, count 0 2006.257.05:54:31.36#ibcon#about to read 5, iclass 25, count 0 2006.257.05:54:31.36#ibcon#read 5, iclass 25, count 0 2006.257.05:54:31.36#ibcon#about to read 6, iclass 25, count 0 2006.257.05:54:31.36#ibcon#read 6, iclass 25, count 0 2006.257.05:54:31.36#ibcon#end of sib2, iclass 25, count 0 2006.257.05:54:31.36#ibcon#*after write, iclass 25, count 0 2006.257.05:54:31.36#ibcon#*before return 0, iclass 25, count 0 2006.257.05:54:31.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:31.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:31.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.05:54:31.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.05:54:31.36$vck44/va=1,8 2006.257.05:54:31.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.05:54:31.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.05:54:31.36#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:31.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:31.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:31.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:31.36#ibcon#enter wrdev, iclass 27, count 2 2006.257.05:54:31.36#ibcon#first serial, iclass 27, count 2 2006.257.05:54:31.36#ibcon#enter sib2, iclass 27, count 2 2006.257.05:54:31.36#ibcon#flushed, iclass 27, count 2 2006.257.05:54:31.36#ibcon#about to write, iclass 27, count 2 2006.257.05:54:31.36#ibcon#wrote, iclass 27, count 2 2006.257.05:54:31.36#ibcon#about to read 3, iclass 27, count 2 2006.257.05:54:31.38#ibcon#read 3, iclass 27, count 2 2006.257.05:54:31.38#ibcon#about to read 4, iclass 27, count 2 2006.257.05:54:31.38#ibcon#read 4, iclass 27, count 2 2006.257.05:54:31.38#ibcon#about to read 5, iclass 27, count 2 2006.257.05:54:31.38#ibcon#read 5, iclass 27, count 2 2006.257.05:54:31.38#ibcon#about to read 6, iclass 27, count 2 2006.257.05:54:31.38#ibcon#read 6, iclass 27, count 2 2006.257.05:54:31.38#ibcon#end of sib2, iclass 27, count 2 2006.257.05:54:31.38#ibcon#*mode == 0, iclass 27, count 2 2006.257.05:54:31.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.05:54:31.38#ibcon#[25=AT01-08\r\n] 2006.257.05:54:31.38#ibcon#*before write, iclass 27, count 2 2006.257.05:54:31.38#ibcon#enter sib2, iclass 27, count 2 2006.257.05:54:31.38#ibcon#flushed, iclass 27, count 2 2006.257.05:54:31.38#ibcon#about to write, iclass 27, count 2 2006.257.05:54:31.38#ibcon#wrote, iclass 27, count 2 2006.257.05:54:31.38#ibcon#about to read 3, iclass 27, count 2 2006.257.05:54:31.41#ibcon#read 3, iclass 27, count 2 2006.257.05:54:31.41#ibcon#about to read 4, iclass 27, count 2 2006.257.05:54:31.41#ibcon#read 4, iclass 27, count 2 2006.257.05:54:31.41#ibcon#about to read 5, iclass 27, count 2 2006.257.05:54:31.41#ibcon#read 5, iclass 27, count 2 2006.257.05:54:31.41#ibcon#about to read 6, iclass 27, count 2 2006.257.05:54:31.41#ibcon#read 6, iclass 27, count 2 2006.257.05:54:31.41#ibcon#end of sib2, iclass 27, count 2 2006.257.05:54:31.41#ibcon#*after write, iclass 27, count 2 2006.257.05:54:31.41#ibcon#*before return 0, iclass 27, count 2 2006.257.05:54:31.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:31.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:31.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.05:54:31.41#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:31.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:31.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:31.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:31.53#ibcon#enter wrdev, iclass 27, count 0 2006.257.05:54:31.53#ibcon#first serial, iclass 27, count 0 2006.257.05:54:31.53#ibcon#enter sib2, iclass 27, count 0 2006.257.05:54:31.53#ibcon#flushed, iclass 27, count 0 2006.257.05:54:31.53#ibcon#about to write, iclass 27, count 0 2006.257.05:54:31.53#ibcon#wrote, iclass 27, count 0 2006.257.05:54:31.53#ibcon#about to read 3, iclass 27, count 0 2006.257.05:54:31.55#ibcon#read 3, iclass 27, count 0 2006.257.05:54:31.55#ibcon#about to read 4, iclass 27, count 0 2006.257.05:54:31.55#ibcon#read 4, iclass 27, count 0 2006.257.05:54:31.55#ibcon#about to read 5, iclass 27, count 0 2006.257.05:54:31.55#ibcon#read 5, iclass 27, count 0 2006.257.05:54:31.55#ibcon#about to read 6, iclass 27, count 0 2006.257.05:54:31.55#ibcon#read 6, iclass 27, count 0 2006.257.05:54:31.55#ibcon#end of sib2, iclass 27, count 0 2006.257.05:54:31.55#ibcon#*mode == 0, iclass 27, count 0 2006.257.05:54:31.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.05:54:31.55#ibcon#[25=USB\r\n] 2006.257.05:54:31.55#ibcon#*before write, iclass 27, count 0 2006.257.05:54:31.55#ibcon#enter sib2, iclass 27, count 0 2006.257.05:54:31.55#ibcon#flushed, iclass 27, count 0 2006.257.05:54:31.55#ibcon#about to write, iclass 27, count 0 2006.257.05:54:31.55#ibcon#wrote, iclass 27, count 0 2006.257.05:54:31.55#ibcon#about to read 3, iclass 27, count 0 2006.257.05:54:31.58#ibcon#read 3, iclass 27, count 0 2006.257.05:54:31.58#ibcon#about to read 4, iclass 27, count 0 2006.257.05:54:31.58#ibcon#read 4, iclass 27, count 0 2006.257.05:54:31.58#ibcon#about to read 5, iclass 27, count 0 2006.257.05:54:31.58#ibcon#read 5, iclass 27, count 0 2006.257.05:54:31.58#ibcon#about to read 6, iclass 27, count 0 2006.257.05:54:31.58#ibcon#read 6, iclass 27, count 0 2006.257.05:54:31.58#ibcon#end of sib2, iclass 27, count 0 2006.257.05:54:31.58#ibcon#*after write, iclass 27, count 0 2006.257.05:54:31.58#ibcon#*before return 0, iclass 27, count 0 2006.257.05:54:31.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:31.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:31.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.05:54:31.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.05:54:31.58$vck44/valo=2,534.99 2006.257.05:54:31.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.05:54:31.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.05:54:31.58#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:31.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:31.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:31.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:31.58#ibcon#enter wrdev, iclass 29, count 0 2006.257.05:54:31.58#ibcon#first serial, iclass 29, count 0 2006.257.05:54:31.58#ibcon#enter sib2, iclass 29, count 0 2006.257.05:54:31.58#ibcon#flushed, iclass 29, count 0 2006.257.05:54:31.58#ibcon#about to write, iclass 29, count 0 2006.257.05:54:31.58#ibcon#wrote, iclass 29, count 0 2006.257.05:54:31.58#ibcon#about to read 3, iclass 29, count 0 2006.257.05:54:31.60#ibcon#read 3, iclass 29, count 0 2006.257.05:54:31.60#ibcon#about to read 4, iclass 29, count 0 2006.257.05:54:31.60#ibcon#read 4, iclass 29, count 0 2006.257.05:54:31.60#ibcon#about to read 5, iclass 29, count 0 2006.257.05:54:31.60#ibcon#read 5, iclass 29, count 0 2006.257.05:54:31.60#ibcon#about to read 6, iclass 29, count 0 2006.257.05:54:31.60#ibcon#read 6, iclass 29, count 0 2006.257.05:54:31.60#ibcon#end of sib2, iclass 29, count 0 2006.257.05:54:31.60#ibcon#*mode == 0, iclass 29, count 0 2006.257.05:54:31.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.05:54:31.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:54:31.60#ibcon#*before write, iclass 29, count 0 2006.257.05:54:31.60#ibcon#enter sib2, iclass 29, count 0 2006.257.05:54:31.60#ibcon#flushed, iclass 29, count 0 2006.257.05:54:31.60#ibcon#about to write, iclass 29, count 0 2006.257.05:54:31.60#ibcon#wrote, iclass 29, count 0 2006.257.05:54:31.60#ibcon#about to read 3, iclass 29, count 0 2006.257.05:54:31.64#ibcon#read 3, iclass 29, count 0 2006.257.05:54:31.64#ibcon#about to read 4, iclass 29, count 0 2006.257.05:54:31.64#ibcon#read 4, iclass 29, count 0 2006.257.05:54:31.64#ibcon#about to read 5, iclass 29, count 0 2006.257.05:54:31.64#ibcon#read 5, iclass 29, count 0 2006.257.05:54:31.64#ibcon#about to read 6, iclass 29, count 0 2006.257.05:54:31.64#ibcon#read 6, iclass 29, count 0 2006.257.05:54:31.64#ibcon#end of sib2, iclass 29, count 0 2006.257.05:54:31.64#ibcon#*after write, iclass 29, count 0 2006.257.05:54:31.64#ibcon#*before return 0, iclass 29, count 0 2006.257.05:54:31.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:31.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:31.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.05:54:31.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.05:54:31.64$vck44/va=2,7 2006.257.05:54:31.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.05:54:31.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.05:54:31.64#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:31.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:31.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:31.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:31.70#ibcon#enter wrdev, iclass 31, count 2 2006.257.05:54:31.70#ibcon#first serial, iclass 31, count 2 2006.257.05:54:31.70#ibcon#enter sib2, iclass 31, count 2 2006.257.05:54:31.70#ibcon#flushed, iclass 31, count 2 2006.257.05:54:31.70#ibcon#about to write, iclass 31, count 2 2006.257.05:54:31.70#ibcon#wrote, iclass 31, count 2 2006.257.05:54:31.70#ibcon#about to read 3, iclass 31, count 2 2006.257.05:54:31.72#ibcon#read 3, iclass 31, count 2 2006.257.05:54:31.72#ibcon#about to read 4, iclass 31, count 2 2006.257.05:54:31.72#ibcon#read 4, iclass 31, count 2 2006.257.05:54:31.72#ibcon#about to read 5, iclass 31, count 2 2006.257.05:54:31.72#ibcon#read 5, iclass 31, count 2 2006.257.05:54:31.72#ibcon#about to read 6, iclass 31, count 2 2006.257.05:54:31.72#ibcon#read 6, iclass 31, count 2 2006.257.05:54:31.72#ibcon#end of sib2, iclass 31, count 2 2006.257.05:54:31.72#ibcon#*mode == 0, iclass 31, count 2 2006.257.05:54:31.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.05:54:31.72#ibcon#[25=AT02-07\r\n] 2006.257.05:54:31.72#ibcon#*before write, iclass 31, count 2 2006.257.05:54:31.72#ibcon#enter sib2, iclass 31, count 2 2006.257.05:54:31.72#ibcon#flushed, iclass 31, count 2 2006.257.05:54:31.72#ibcon#about to write, iclass 31, count 2 2006.257.05:54:31.72#ibcon#wrote, iclass 31, count 2 2006.257.05:54:31.72#ibcon#about to read 3, iclass 31, count 2 2006.257.05:54:31.75#ibcon#read 3, iclass 31, count 2 2006.257.05:54:31.75#ibcon#about to read 4, iclass 31, count 2 2006.257.05:54:31.75#ibcon#read 4, iclass 31, count 2 2006.257.05:54:31.75#ibcon#about to read 5, iclass 31, count 2 2006.257.05:54:31.75#ibcon#read 5, iclass 31, count 2 2006.257.05:54:31.75#ibcon#about to read 6, iclass 31, count 2 2006.257.05:54:31.75#ibcon#read 6, iclass 31, count 2 2006.257.05:54:31.75#ibcon#end of sib2, iclass 31, count 2 2006.257.05:54:31.75#ibcon#*after write, iclass 31, count 2 2006.257.05:54:31.75#ibcon#*before return 0, iclass 31, count 2 2006.257.05:54:31.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:31.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:31.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.05:54:31.75#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:31.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:31.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:31.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:31.87#ibcon#enter wrdev, iclass 31, count 0 2006.257.05:54:31.87#ibcon#first serial, iclass 31, count 0 2006.257.05:54:31.87#ibcon#enter sib2, iclass 31, count 0 2006.257.05:54:31.87#ibcon#flushed, iclass 31, count 0 2006.257.05:54:31.87#ibcon#about to write, iclass 31, count 0 2006.257.05:54:31.87#ibcon#wrote, iclass 31, count 0 2006.257.05:54:31.87#ibcon#about to read 3, iclass 31, count 0 2006.257.05:54:31.89#ibcon#read 3, iclass 31, count 0 2006.257.05:54:31.89#ibcon#about to read 4, iclass 31, count 0 2006.257.05:54:31.89#ibcon#read 4, iclass 31, count 0 2006.257.05:54:31.89#ibcon#about to read 5, iclass 31, count 0 2006.257.05:54:31.89#ibcon#read 5, iclass 31, count 0 2006.257.05:54:31.89#ibcon#about to read 6, iclass 31, count 0 2006.257.05:54:31.89#ibcon#read 6, iclass 31, count 0 2006.257.05:54:31.89#ibcon#end of sib2, iclass 31, count 0 2006.257.05:54:31.89#ibcon#*mode == 0, iclass 31, count 0 2006.257.05:54:31.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.05:54:31.89#ibcon#[25=USB\r\n] 2006.257.05:54:31.89#ibcon#*before write, iclass 31, count 0 2006.257.05:54:31.89#ibcon#enter sib2, iclass 31, count 0 2006.257.05:54:31.89#ibcon#flushed, iclass 31, count 0 2006.257.05:54:31.89#ibcon#about to write, iclass 31, count 0 2006.257.05:54:31.89#ibcon#wrote, iclass 31, count 0 2006.257.05:54:31.89#ibcon#about to read 3, iclass 31, count 0 2006.257.05:54:31.92#ibcon#read 3, iclass 31, count 0 2006.257.05:54:31.92#ibcon#about to read 4, iclass 31, count 0 2006.257.05:54:31.92#ibcon#read 4, iclass 31, count 0 2006.257.05:54:31.92#ibcon#about to read 5, iclass 31, count 0 2006.257.05:54:31.92#ibcon#read 5, iclass 31, count 0 2006.257.05:54:31.92#ibcon#about to read 6, iclass 31, count 0 2006.257.05:54:31.92#ibcon#read 6, iclass 31, count 0 2006.257.05:54:31.92#ibcon#end of sib2, iclass 31, count 0 2006.257.05:54:31.92#ibcon#*after write, iclass 31, count 0 2006.257.05:54:31.92#ibcon#*before return 0, iclass 31, count 0 2006.257.05:54:31.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:31.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:31.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.05:54:31.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.05:54:31.92$vck44/valo=3,564.99 2006.257.05:54:31.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.05:54:31.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.05:54:31.92#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:31.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:31.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:31.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:31.92#ibcon#enter wrdev, iclass 33, count 0 2006.257.05:54:31.92#ibcon#first serial, iclass 33, count 0 2006.257.05:54:31.92#ibcon#enter sib2, iclass 33, count 0 2006.257.05:54:31.92#ibcon#flushed, iclass 33, count 0 2006.257.05:54:31.92#ibcon#about to write, iclass 33, count 0 2006.257.05:54:31.92#ibcon#wrote, iclass 33, count 0 2006.257.05:54:31.92#ibcon#about to read 3, iclass 33, count 0 2006.257.05:54:31.94#ibcon#read 3, iclass 33, count 0 2006.257.05:54:31.94#ibcon#about to read 4, iclass 33, count 0 2006.257.05:54:31.94#ibcon#read 4, iclass 33, count 0 2006.257.05:54:31.94#ibcon#about to read 5, iclass 33, count 0 2006.257.05:54:31.94#ibcon#read 5, iclass 33, count 0 2006.257.05:54:31.94#ibcon#about to read 6, iclass 33, count 0 2006.257.05:54:31.94#ibcon#read 6, iclass 33, count 0 2006.257.05:54:31.94#ibcon#end of sib2, iclass 33, count 0 2006.257.05:54:31.94#ibcon#*mode == 0, iclass 33, count 0 2006.257.05:54:31.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.05:54:31.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:54:31.94#ibcon#*before write, iclass 33, count 0 2006.257.05:54:31.94#ibcon#enter sib2, iclass 33, count 0 2006.257.05:54:31.94#ibcon#flushed, iclass 33, count 0 2006.257.05:54:31.94#ibcon#about to write, iclass 33, count 0 2006.257.05:54:31.94#ibcon#wrote, iclass 33, count 0 2006.257.05:54:31.94#ibcon#about to read 3, iclass 33, count 0 2006.257.05:54:31.98#ibcon#read 3, iclass 33, count 0 2006.257.05:54:31.98#ibcon#about to read 4, iclass 33, count 0 2006.257.05:54:31.98#ibcon#read 4, iclass 33, count 0 2006.257.05:54:31.98#ibcon#about to read 5, iclass 33, count 0 2006.257.05:54:31.98#ibcon#read 5, iclass 33, count 0 2006.257.05:54:31.98#ibcon#about to read 6, iclass 33, count 0 2006.257.05:54:31.98#ibcon#read 6, iclass 33, count 0 2006.257.05:54:31.98#ibcon#end of sib2, iclass 33, count 0 2006.257.05:54:31.98#ibcon#*after write, iclass 33, count 0 2006.257.05:54:31.98#ibcon#*before return 0, iclass 33, count 0 2006.257.05:54:31.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:31.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:31.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.05:54:31.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.05:54:31.98$vck44/va=3,8 2006.257.05:54:31.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.05:54:31.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.05:54:31.98#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:31.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:32.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:32.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:32.04#ibcon#enter wrdev, iclass 35, count 2 2006.257.05:54:32.04#ibcon#first serial, iclass 35, count 2 2006.257.05:54:32.04#ibcon#enter sib2, iclass 35, count 2 2006.257.05:54:32.04#ibcon#flushed, iclass 35, count 2 2006.257.05:54:32.04#ibcon#about to write, iclass 35, count 2 2006.257.05:54:32.04#ibcon#wrote, iclass 35, count 2 2006.257.05:54:32.04#ibcon#about to read 3, iclass 35, count 2 2006.257.05:54:32.06#ibcon#read 3, iclass 35, count 2 2006.257.05:54:32.06#ibcon#about to read 4, iclass 35, count 2 2006.257.05:54:32.06#ibcon#read 4, iclass 35, count 2 2006.257.05:54:32.06#ibcon#about to read 5, iclass 35, count 2 2006.257.05:54:32.06#ibcon#read 5, iclass 35, count 2 2006.257.05:54:32.06#ibcon#about to read 6, iclass 35, count 2 2006.257.05:54:32.06#ibcon#read 6, iclass 35, count 2 2006.257.05:54:32.06#ibcon#end of sib2, iclass 35, count 2 2006.257.05:54:32.06#ibcon#*mode == 0, iclass 35, count 2 2006.257.05:54:32.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.05:54:32.06#ibcon#[25=AT03-08\r\n] 2006.257.05:54:32.06#ibcon#*before write, iclass 35, count 2 2006.257.05:54:32.06#ibcon#enter sib2, iclass 35, count 2 2006.257.05:54:32.06#ibcon#flushed, iclass 35, count 2 2006.257.05:54:32.06#ibcon#about to write, iclass 35, count 2 2006.257.05:54:32.06#ibcon#wrote, iclass 35, count 2 2006.257.05:54:32.06#ibcon#about to read 3, iclass 35, count 2 2006.257.05:54:32.09#ibcon#read 3, iclass 35, count 2 2006.257.05:54:32.09#ibcon#about to read 4, iclass 35, count 2 2006.257.05:54:32.09#ibcon#read 4, iclass 35, count 2 2006.257.05:54:32.09#ibcon#about to read 5, iclass 35, count 2 2006.257.05:54:32.09#ibcon#read 5, iclass 35, count 2 2006.257.05:54:32.09#ibcon#about to read 6, iclass 35, count 2 2006.257.05:54:32.09#ibcon#read 6, iclass 35, count 2 2006.257.05:54:32.09#ibcon#end of sib2, iclass 35, count 2 2006.257.05:54:32.09#ibcon#*after write, iclass 35, count 2 2006.257.05:54:32.09#ibcon#*before return 0, iclass 35, count 2 2006.257.05:54:32.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:32.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:32.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.05:54:32.09#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:32.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:32.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:32.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:32.21#ibcon#enter wrdev, iclass 35, count 0 2006.257.05:54:32.21#ibcon#first serial, iclass 35, count 0 2006.257.05:54:32.21#ibcon#enter sib2, iclass 35, count 0 2006.257.05:54:32.21#ibcon#flushed, iclass 35, count 0 2006.257.05:54:32.21#ibcon#about to write, iclass 35, count 0 2006.257.05:54:32.21#ibcon#wrote, iclass 35, count 0 2006.257.05:54:32.21#ibcon#about to read 3, iclass 35, count 0 2006.257.05:54:32.23#ibcon#read 3, iclass 35, count 0 2006.257.05:54:32.23#ibcon#about to read 4, iclass 35, count 0 2006.257.05:54:32.23#ibcon#read 4, iclass 35, count 0 2006.257.05:54:32.23#ibcon#about to read 5, iclass 35, count 0 2006.257.05:54:32.23#ibcon#read 5, iclass 35, count 0 2006.257.05:54:32.23#ibcon#about to read 6, iclass 35, count 0 2006.257.05:54:32.23#ibcon#read 6, iclass 35, count 0 2006.257.05:54:32.23#ibcon#end of sib2, iclass 35, count 0 2006.257.05:54:32.23#ibcon#*mode == 0, iclass 35, count 0 2006.257.05:54:32.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.05:54:32.23#ibcon#[25=USB\r\n] 2006.257.05:54:32.23#ibcon#*before write, iclass 35, count 0 2006.257.05:54:32.23#ibcon#enter sib2, iclass 35, count 0 2006.257.05:54:32.23#ibcon#flushed, iclass 35, count 0 2006.257.05:54:32.23#ibcon#about to write, iclass 35, count 0 2006.257.05:54:32.23#ibcon#wrote, iclass 35, count 0 2006.257.05:54:32.23#ibcon#about to read 3, iclass 35, count 0 2006.257.05:54:32.26#ibcon#read 3, iclass 35, count 0 2006.257.05:54:32.26#ibcon#about to read 4, iclass 35, count 0 2006.257.05:54:32.26#ibcon#read 4, iclass 35, count 0 2006.257.05:54:32.26#ibcon#about to read 5, iclass 35, count 0 2006.257.05:54:32.26#ibcon#read 5, iclass 35, count 0 2006.257.05:54:32.26#ibcon#about to read 6, iclass 35, count 0 2006.257.05:54:32.26#ibcon#read 6, iclass 35, count 0 2006.257.05:54:32.26#ibcon#end of sib2, iclass 35, count 0 2006.257.05:54:32.26#ibcon#*after write, iclass 35, count 0 2006.257.05:54:32.26#ibcon#*before return 0, iclass 35, count 0 2006.257.05:54:32.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:32.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:32.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.05:54:32.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.05:54:32.26$vck44/valo=4,624.99 2006.257.05:54:32.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.05:54:32.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.05:54:32.26#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:32.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:32.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:32.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:32.26#ibcon#enter wrdev, iclass 37, count 0 2006.257.05:54:32.26#ibcon#first serial, iclass 37, count 0 2006.257.05:54:32.26#ibcon#enter sib2, iclass 37, count 0 2006.257.05:54:32.26#ibcon#flushed, iclass 37, count 0 2006.257.05:54:32.26#ibcon#about to write, iclass 37, count 0 2006.257.05:54:32.26#ibcon#wrote, iclass 37, count 0 2006.257.05:54:32.26#ibcon#about to read 3, iclass 37, count 0 2006.257.05:54:32.28#ibcon#read 3, iclass 37, count 0 2006.257.05:54:32.28#ibcon#about to read 4, iclass 37, count 0 2006.257.05:54:32.28#ibcon#read 4, iclass 37, count 0 2006.257.05:54:32.28#ibcon#about to read 5, iclass 37, count 0 2006.257.05:54:32.28#ibcon#read 5, iclass 37, count 0 2006.257.05:54:32.28#ibcon#about to read 6, iclass 37, count 0 2006.257.05:54:32.28#ibcon#read 6, iclass 37, count 0 2006.257.05:54:32.28#ibcon#end of sib2, iclass 37, count 0 2006.257.05:54:32.28#ibcon#*mode == 0, iclass 37, count 0 2006.257.05:54:32.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.05:54:32.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:54:32.28#ibcon#*before write, iclass 37, count 0 2006.257.05:54:32.28#ibcon#enter sib2, iclass 37, count 0 2006.257.05:54:32.28#ibcon#flushed, iclass 37, count 0 2006.257.05:54:32.28#ibcon#about to write, iclass 37, count 0 2006.257.05:54:32.28#ibcon#wrote, iclass 37, count 0 2006.257.05:54:32.28#ibcon#about to read 3, iclass 37, count 0 2006.257.05:54:32.32#ibcon#read 3, iclass 37, count 0 2006.257.05:54:32.32#ibcon#about to read 4, iclass 37, count 0 2006.257.05:54:32.32#ibcon#read 4, iclass 37, count 0 2006.257.05:54:32.32#ibcon#about to read 5, iclass 37, count 0 2006.257.05:54:32.32#ibcon#read 5, iclass 37, count 0 2006.257.05:54:32.32#ibcon#about to read 6, iclass 37, count 0 2006.257.05:54:32.32#ibcon#read 6, iclass 37, count 0 2006.257.05:54:32.32#ibcon#end of sib2, iclass 37, count 0 2006.257.05:54:32.32#ibcon#*after write, iclass 37, count 0 2006.257.05:54:32.32#ibcon#*before return 0, iclass 37, count 0 2006.257.05:54:32.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:32.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:32.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.05:54:32.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.05:54:32.32$vck44/va=4,7 2006.257.05:54:32.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.05:54:32.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.05:54:32.32#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:32.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:32.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:32.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:32.38#ibcon#enter wrdev, iclass 39, count 2 2006.257.05:54:32.38#ibcon#first serial, iclass 39, count 2 2006.257.05:54:32.38#ibcon#enter sib2, iclass 39, count 2 2006.257.05:54:32.38#ibcon#flushed, iclass 39, count 2 2006.257.05:54:32.38#ibcon#about to write, iclass 39, count 2 2006.257.05:54:32.38#ibcon#wrote, iclass 39, count 2 2006.257.05:54:32.38#ibcon#about to read 3, iclass 39, count 2 2006.257.05:54:32.40#ibcon#read 3, iclass 39, count 2 2006.257.05:54:32.40#ibcon#about to read 4, iclass 39, count 2 2006.257.05:54:32.40#ibcon#read 4, iclass 39, count 2 2006.257.05:54:32.40#ibcon#about to read 5, iclass 39, count 2 2006.257.05:54:32.40#ibcon#read 5, iclass 39, count 2 2006.257.05:54:32.40#ibcon#about to read 6, iclass 39, count 2 2006.257.05:54:32.40#ibcon#read 6, iclass 39, count 2 2006.257.05:54:32.40#ibcon#end of sib2, iclass 39, count 2 2006.257.05:54:32.40#ibcon#*mode == 0, iclass 39, count 2 2006.257.05:54:32.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.05:54:32.40#ibcon#[25=AT04-07\r\n] 2006.257.05:54:32.40#ibcon#*before write, iclass 39, count 2 2006.257.05:54:32.40#ibcon#enter sib2, iclass 39, count 2 2006.257.05:54:32.40#ibcon#flushed, iclass 39, count 2 2006.257.05:54:32.40#ibcon#about to write, iclass 39, count 2 2006.257.05:54:32.40#ibcon#wrote, iclass 39, count 2 2006.257.05:54:32.40#ibcon#about to read 3, iclass 39, count 2 2006.257.05:54:32.43#ibcon#read 3, iclass 39, count 2 2006.257.05:54:32.43#ibcon#about to read 4, iclass 39, count 2 2006.257.05:54:32.43#ibcon#read 4, iclass 39, count 2 2006.257.05:54:32.43#ibcon#about to read 5, iclass 39, count 2 2006.257.05:54:32.43#ibcon#read 5, iclass 39, count 2 2006.257.05:54:32.43#ibcon#about to read 6, iclass 39, count 2 2006.257.05:54:32.43#ibcon#read 6, iclass 39, count 2 2006.257.05:54:32.43#ibcon#end of sib2, iclass 39, count 2 2006.257.05:54:32.43#ibcon#*after write, iclass 39, count 2 2006.257.05:54:32.43#ibcon#*before return 0, iclass 39, count 2 2006.257.05:54:32.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:32.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:32.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.05:54:32.43#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:32.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:32.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:32.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:32.55#ibcon#enter wrdev, iclass 39, count 0 2006.257.05:54:32.55#ibcon#first serial, iclass 39, count 0 2006.257.05:54:32.55#ibcon#enter sib2, iclass 39, count 0 2006.257.05:54:32.55#ibcon#flushed, iclass 39, count 0 2006.257.05:54:32.55#ibcon#about to write, iclass 39, count 0 2006.257.05:54:32.55#ibcon#wrote, iclass 39, count 0 2006.257.05:54:32.55#ibcon#about to read 3, iclass 39, count 0 2006.257.05:54:32.57#ibcon#read 3, iclass 39, count 0 2006.257.05:54:32.57#ibcon#about to read 4, iclass 39, count 0 2006.257.05:54:32.57#ibcon#read 4, iclass 39, count 0 2006.257.05:54:32.57#ibcon#about to read 5, iclass 39, count 0 2006.257.05:54:32.57#ibcon#read 5, iclass 39, count 0 2006.257.05:54:32.57#ibcon#about to read 6, iclass 39, count 0 2006.257.05:54:32.57#ibcon#read 6, iclass 39, count 0 2006.257.05:54:32.57#ibcon#end of sib2, iclass 39, count 0 2006.257.05:54:32.57#ibcon#*mode == 0, iclass 39, count 0 2006.257.05:54:32.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.05:54:32.57#ibcon#[25=USB\r\n] 2006.257.05:54:32.57#ibcon#*before write, iclass 39, count 0 2006.257.05:54:32.57#ibcon#enter sib2, iclass 39, count 0 2006.257.05:54:32.57#ibcon#flushed, iclass 39, count 0 2006.257.05:54:32.57#ibcon#about to write, iclass 39, count 0 2006.257.05:54:32.57#ibcon#wrote, iclass 39, count 0 2006.257.05:54:32.57#ibcon#about to read 3, iclass 39, count 0 2006.257.05:54:32.60#ibcon#read 3, iclass 39, count 0 2006.257.05:54:32.60#ibcon#about to read 4, iclass 39, count 0 2006.257.05:54:32.60#ibcon#read 4, iclass 39, count 0 2006.257.05:54:32.60#ibcon#about to read 5, iclass 39, count 0 2006.257.05:54:32.60#ibcon#read 5, iclass 39, count 0 2006.257.05:54:32.60#ibcon#about to read 6, iclass 39, count 0 2006.257.05:54:32.60#ibcon#read 6, iclass 39, count 0 2006.257.05:54:32.60#ibcon#end of sib2, iclass 39, count 0 2006.257.05:54:32.60#ibcon#*after write, iclass 39, count 0 2006.257.05:54:32.60#ibcon#*before return 0, iclass 39, count 0 2006.257.05:54:32.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:32.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:32.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.05:54:32.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.05:54:32.60$vck44/valo=5,734.99 2006.257.05:54:32.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.05:54:32.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.05:54:32.60#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:32.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:32.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:32.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:32.60#ibcon#enter wrdev, iclass 3, count 0 2006.257.05:54:32.60#ibcon#first serial, iclass 3, count 0 2006.257.05:54:32.60#ibcon#enter sib2, iclass 3, count 0 2006.257.05:54:32.60#ibcon#flushed, iclass 3, count 0 2006.257.05:54:32.60#ibcon#about to write, iclass 3, count 0 2006.257.05:54:32.60#ibcon#wrote, iclass 3, count 0 2006.257.05:54:32.60#ibcon#about to read 3, iclass 3, count 0 2006.257.05:54:32.62#ibcon#read 3, iclass 3, count 0 2006.257.05:54:32.62#ibcon#about to read 4, iclass 3, count 0 2006.257.05:54:32.62#ibcon#read 4, iclass 3, count 0 2006.257.05:54:32.62#ibcon#about to read 5, iclass 3, count 0 2006.257.05:54:32.62#ibcon#read 5, iclass 3, count 0 2006.257.05:54:32.62#ibcon#about to read 6, iclass 3, count 0 2006.257.05:54:32.62#ibcon#read 6, iclass 3, count 0 2006.257.05:54:32.62#ibcon#end of sib2, iclass 3, count 0 2006.257.05:54:32.62#ibcon#*mode == 0, iclass 3, count 0 2006.257.05:54:32.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.05:54:32.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:54:32.62#ibcon#*before write, iclass 3, count 0 2006.257.05:54:32.62#ibcon#enter sib2, iclass 3, count 0 2006.257.05:54:32.62#ibcon#flushed, iclass 3, count 0 2006.257.05:54:32.62#ibcon#about to write, iclass 3, count 0 2006.257.05:54:32.62#ibcon#wrote, iclass 3, count 0 2006.257.05:54:32.62#ibcon#about to read 3, iclass 3, count 0 2006.257.05:54:32.66#ibcon#read 3, iclass 3, count 0 2006.257.05:54:32.66#ibcon#about to read 4, iclass 3, count 0 2006.257.05:54:32.66#ibcon#read 4, iclass 3, count 0 2006.257.05:54:32.66#ibcon#about to read 5, iclass 3, count 0 2006.257.05:54:32.66#ibcon#read 5, iclass 3, count 0 2006.257.05:54:32.66#ibcon#about to read 6, iclass 3, count 0 2006.257.05:54:32.66#ibcon#read 6, iclass 3, count 0 2006.257.05:54:32.66#ibcon#end of sib2, iclass 3, count 0 2006.257.05:54:32.66#ibcon#*after write, iclass 3, count 0 2006.257.05:54:32.66#ibcon#*before return 0, iclass 3, count 0 2006.257.05:54:32.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:32.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:32.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.05:54:32.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.05:54:32.66$vck44/va=5,4 2006.257.05:54:32.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.05:54:32.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.05:54:32.66#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:32.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:32.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:32.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:32.72#ibcon#enter wrdev, iclass 5, count 2 2006.257.05:54:32.72#ibcon#first serial, iclass 5, count 2 2006.257.05:54:32.72#ibcon#enter sib2, iclass 5, count 2 2006.257.05:54:32.72#ibcon#flushed, iclass 5, count 2 2006.257.05:54:32.72#ibcon#about to write, iclass 5, count 2 2006.257.05:54:32.72#ibcon#wrote, iclass 5, count 2 2006.257.05:54:32.72#ibcon#about to read 3, iclass 5, count 2 2006.257.05:54:32.74#ibcon#read 3, iclass 5, count 2 2006.257.05:54:32.74#ibcon#about to read 4, iclass 5, count 2 2006.257.05:54:32.74#ibcon#read 4, iclass 5, count 2 2006.257.05:54:32.74#ibcon#about to read 5, iclass 5, count 2 2006.257.05:54:32.74#ibcon#read 5, iclass 5, count 2 2006.257.05:54:32.74#ibcon#about to read 6, iclass 5, count 2 2006.257.05:54:32.74#ibcon#read 6, iclass 5, count 2 2006.257.05:54:32.74#ibcon#end of sib2, iclass 5, count 2 2006.257.05:54:32.74#ibcon#*mode == 0, iclass 5, count 2 2006.257.05:54:32.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.05:54:32.74#ibcon#[25=AT05-04\r\n] 2006.257.05:54:32.74#ibcon#*before write, iclass 5, count 2 2006.257.05:54:32.74#ibcon#enter sib2, iclass 5, count 2 2006.257.05:54:32.74#ibcon#flushed, iclass 5, count 2 2006.257.05:54:32.74#ibcon#about to write, iclass 5, count 2 2006.257.05:54:32.74#ibcon#wrote, iclass 5, count 2 2006.257.05:54:32.74#ibcon#about to read 3, iclass 5, count 2 2006.257.05:54:32.77#ibcon#read 3, iclass 5, count 2 2006.257.05:54:32.77#ibcon#about to read 4, iclass 5, count 2 2006.257.05:54:32.77#ibcon#read 4, iclass 5, count 2 2006.257.05:54:32.77#ibcon#about to read 5, iclass 5, count 2 2006.257.05:54:32.77#ibcon#read 5, iclass 5, count 2 2006.257.05:54:32.77#ibcon#about to read 6, iclass 5, count 2 2006.257.05:54:32.77#ibcon#read 6, iclass 5, count 2 2006.257.05:54:32.77#ibcon#end of sib2, iclass 5, count 2 2006.257.05:54:32.77#ibcon#*after write, iclass 5, count 2 2006.257.05:54:32.77#ibcon#*before return 0, iclass 5, count 2 2006.257.05:54:32.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:32.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:32.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.05:54:32.77#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:32.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:32.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:32.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:32.89#ibcon#enter wrdev, iclass 5, count 0 2006.257.05:54:32.89#ibcon#first serial, iclass 5, count 0 2006.257.05:54:32.89#ibcon#enter sib2, iclass 5, count 0 2006.257.05:54:32.89#ibcon#flushed, iclass 5, count 0 2006.257.05:54:32.89#ibcon#about to write, iclass 5, count 0 2006.257.05:54:32.89#ibcon#wrote, iclass 5, count 0 2006.257.05:54:32.89#ibcon#about to read 3, iclass 5, count 0 2006.257.05:54:32.91#ibcon#read 3, iclass 5, count 0 2006.257.05:54:32.91#ibcon#about to read 4, iclass 5, count 0 2006.257.05:54:32.91#ibcon#read 4, iclass 5, count 0 2006.257.05:54:32.91#ibcon#about to read 5, iclass 5, count 0 2006.257.05:54:32.91#ibcon#read 5, iclass 5, count 0 2006.257.05:54:32.91#ibcon#about to read 6, iclass 5, count 0 2006.257.05:54:32.91#ibcon#read 6, iclass 5, count 0 2006.257.05:54:32.91#ibcon#end of sib2, iclass 5, count 0 2006.257.05:54:32.91#ibcon#*mode == 0, iclass 5, count 0 2006.257.05:54:32.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.05:54:32.91#ibcon#[25=USB\r\n] 2006.257.05:54:32.91#ibcon#*before write, iclass 5, count 0 2006.257.05:54:32.91#ibcon#enter sib2, iclass 5, count 0 2006.257.05:54:32.91#ibcon#flushed, iclass 5, count 0 2006.257.05:54:32.91#ibcon#about to write, iclass 5, count 0 2006.257.05:54:32.91#ibcon#wrote, iclass 5, count 0 2006.257.05:54:32.91#ibcon#about to read 3, iclass 5, count 0 2006.257.05:54:32.94#ibcon#read 3, iclass 5, count 0 2006.257.05:54:32.94#ibcon#about to read 4, iclass 5, count 0 2006.257.05:54:32.94#ibcon#read 4, iclass 5, count 0 2006.257.05:54:32.94#ibcon#about to read 5, iclass 5, count 0 2006.257.05:54:32.94#ibcon#read 5, iclass 5, count 0 2006.257.05:54:32.94#ibcon#about to read 6, iclass 5, count 0 2006.257.05:54:32.94#ibcon#read 6, iclass 5, count 0 2006.257.05:54:32.94#ibcon#end of sib2, iclass 5, count 0 2006.257.05:54:32.94#ibcon#*after write, iclass 5, count 0 2006.257.05:54:32.94#ibcon#*before return 0, iclass 5, count 0 2006.257.05:54:32.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:32.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:32.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.05:54:32.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.05:54:32.94$vck44/valo=6,814.99 2006.257.05:54:32.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.05:54:32.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.05:54:32.94#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:32.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:32.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:32.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:32.94#ibcon#enter wrdev, iclass 7, count 0 2006.257.05:54:32.94#ibcon#first serial, iclass 7, count 0 2006.257.05:54:32.94#ibcon#enter sib2, iclass 7, count 0 2006.257.05:54:32.94#ibcon#flushed, iclass 7, count 0 2006.257.05:54:32.94#ibcon#about to write, iclass 7, count 0 2006.257.05:54:32.94#ibcon#wrote, iclass 7, count 0 2006.257.05:54:32.94#ibcon#about to read 3, iclass 7, count 0 2006.257.05:54:32.96#ibcon#read 3, iclass 7, count 0 2006.257.05:54:32.96#ibcon#about to read 4, iclass 7, count 0 2006.257.05:54:32.96#ibcon#read 4, iclass 7, count 0 2006.257.05:54:32.96#ibcon#about to read 5, iclass 7, count 0 2006.257.05:54:32.96#ibcon#read 5, iclass 7, count 0 2006.257.05:54:32.96#ibcon#about to read 6, iclass 7, count 0 2006.257.05:54:32.96#ibcon#read 6, iclass 7, count 0 2006.257.05:54:32.96#ibcon#end of sib2, iclass 7, count 0 2006.257.05:54:32.96#ibcon#*mode == 0, iclass 7, count 0 2006.257.05:54:32.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.05:54:32.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:54:32.96#ibcon#*before write, iclass 7, count 0 2006.257.05:54:32.96#ibcon#enter sib2, iclass 7, count 0 2006.257.05:54:32.96#ibcon#flushed, iclass 7, count 0 2006.257.05:54:32.96#ibcon#about to write, iclass 7, count 0 2006.257.05:54:32.96#ibcon#wrote, iclass 7, count 0 2006.257.05:54:32.96#ibcon#about to read 3, iclass 7, count 0 2006.257.05:54:33.00#ibcon#read 3, iclass 7, count 0 2006.257.05:54:33.00#ibcon#about to read 4, iclass 7, count 0 2006.257.05:54:33.00#ibcon#read 4, iclass 7, count 0 2006.257.05:54:33.00#ibcon#about to read 5, iclass 7, count 0 2006.257.05:54:33.00#ibcon#read 5, iclass 7, count 0 2006.257.05:54:33.00#ibcon#about to read 6, iclass 7, count 0 2006.257.05:54:33.00#ibcon#read 6, iclass 7, count 0 2006.257.05:54:33.00#ibcon#end of sib2, iclass 7, count 0 2006.257.05:54:33.00#ibcon#*after write, iclass 7, count 0 2006.257.05:54:33.00#ibcon#*before return 0, iclass 7, count 0 2006.257.05:54:33.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:33.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:33.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.05:54:33.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.05:54:33.00$vck44/va=6,4 2006.257.05:54:33.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.05:54:33.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.05:54:33.00#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:33.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:33.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:33.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:33.06#ibcon#enter wrdev, iclass 11, count 2 2006.257.05:54:33.06#ibcon#first serial, iclass 11, count 2 2006.257.05:54:33.06#ibcon#enter sib2, iclass 11, count 2 2006.257.05:54:33.06#ibcon#flushed, iclass 11, count 2 2006.257.05:54:33.06#ibcon#about to write, iclass 11, count 2 2006.257.05:54:33.06#ibcon#wrote, iclass 11, count 2 2006.257.05:54:33.06#ibcon#about to read 3, iclass 11, count 2 2006.257.05:54:33.08#ibcon#read 3, iclass 11, count 2 2006.257.05:54:33.08#ibcon#about to read 4, iclass 11, count 2 2006.257.05:54:33.08#ibcon#read 4, iclass 11, count 2 2006.257.05:54:33.08#ibcon#about to read 5, iclass 11, count 2 2006.257.05:54:33.08#ibcon#read 5, iclass 11, count 2 2006.257.05:54:33.08#ibcon#about to read 6, iclass 11, count 2 2006.257.05:54:33.08#ibcon#read 6, iclass 11, count 2 2006.257.05:54:33.08#ibcon#end of sib2, iclass 11, count 2 2006.257.05:54:33.08#ibcon#*mode == 0, iclass 11, count 2 2006.257.05:54:33.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.05:54:33.08#ibcon#[25=AT06-04\r\n] 2006.257.05:54:33.08#ibcon#*before write, iclass 11, count 2 2006.257.05:54:33.08#ibcon#enter sib2, iclass 11, count 2 2006.257.05:54:33.08#ibcon#flushed, iclass 11, count 2 2006.257.05:54:33.08#ibcon#about to write, iclass 11, count 2 2006.257.05:54:33.08#ibcon#wrote, iclass 11, count 2 2006.257.05:54:33.08#ibcon#about to read 3, iclass 11, count 2 2006.257.05:54:33.11#ibcon#read 3, iclass 11, count 2 2006.257.05:54:33.11#ibcon#about to read 4, iclass 11, count 2 2006.257.05:54:33.11#ibcon#read 4, iclass 11, count 2 2006.257.05:54:33.11#ibcon#about to read 5, iclass 11, count 2 2006.257.05:54:33.11#ibcon#read 5, iclass 11, count 2 2006.257.05:54:33.11#ibcon#about to read 6, iclass 11, count 2 2006.257.05:54:33.11#ibcon#read 6, iclass 11, count 2 2006.257.05:54:33.11#ibcon#end of sib2, iclass 11, count 2 2006.257.05:54:33.11#ibcon#*after write, iclass 11, count 2 2006.257.05:54:33.11#ibcon#*before return 0, iclass 11, count 2 2006.257.05:54:33.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:33.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:33.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.05:54:33.11#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:33.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:33.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:33.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:33.23#ibcon#enter wrdev, iclass 11, count 0 2006.257.05:54:33.23#ibcon#first serial, iclass 11, count 0 2006.257.05:54:33.23#ibcon#enter sib2, iclass 11, count 0 2006.257.05:54:33.23#ibcon#flushed, iclass 11, count 0 2006.257.05:54:33.23#ibcon#about to write, iclass 11, count 0 2006.257.05:54:33.23#ibcon#wrote, iclass 11, count 0 2006.257.05:54:33.23#ibcon#about to read 3, iclass 11, count 0 2006.257.05:54:33.25#ibcon#read 3, iclass 11, count 0 2006.257.05:54:33.25#ibcon#about to read 4, iclass 11, count 0 2006.257.05:54:33.25#ibcon#read 4, iclass 11, count 0 2006.257.05:54:33.25#ibcon#about to read 5, iclass 11, count 0 2006.257.05:54:33.25#ibcon#read 5, iclass 11, count 0 2006.257.05:54:33.25#ibcon#about to read 6, iclass 11, count 0 2006.257.05:54:33.25#ibcon#read 6, iclass 11, count 0 2006.257.05:54:33.25#ibcon#end of sib2, iclass 11, count 0 2006.257.05:54:33.25#ibcon#*mode == 0, iclass 11, count 0 2006.257.05:54:33.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.05:54:33.25#ibcon#[25=USB\r\n] 2006.257.05:54:33.25#ibcon#*before write, iclass 11, count 0 2006.257.05:54:33.25#ibcon#enter sib2, iclass 11, count 0 2006.257.05:54:33.25#ibcon#flushed, iclass 11, count 0 2006.257.05:54:33.25#ibcon#about to write, iclass 11, count 0 2006.257.05:54:33.25#ibcon#wrote, iclass 11, count 0 2006.257.05:54:33.25#ibcon#about to read 3, iclass 11, count 0 2006.257.05:54:33.28#ibcon#read 3, iclass 11, count 0 2006.257.05:54:33.28#ibcon#about to read 4, iclass 11, count 0 2006.257.05:54:33.28#ibcon#read 4, iclass 11, count 0 2006.257.05:54:33.28#ibcon#about to read 5, iclass 11, count 0 2006.257.05:54:33.28#ibcon#read 5, iclass 11, count 0 2006.257.05:54:33.28#ibcon#about to read 6, iclass 11, count 0 2006.257.05:54:33.28#ibcon#read 6, iclass 11, count 0 2006.257.05:54:33.28#ibcon#end of sib2, iclass 11, count 0 2006.257.05:54:33.28#ibcon#*after write, iclass 11, count 0 2006.257.05:54:33.28#ibcon#*before return 0, iclass 11, count 0 2006.257.05:54:33.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:33.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:33.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.05:54:33.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.05:54:33.28$vck44/valo=7,864.99 2006.257.05:54:33.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.05:54:33.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.05:54:33.28#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:33.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:54:33.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:54:33.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:54:33.28#ibcon#enter wrdev, iclass 13, count 0 2006.257.05:54:33.28#ibcon#first serial, iclass 13, count 0 2006.257.05:54:33.28#ibcon#enter sib2, iclass 13, count 0 2006.257.05:54:33.28#ibcon#flushed, iclass 13, count 0 2006.257.05:54:33.28#ibcon#about to write, iclass 13, count 0 2006.257.05:54:33.28#ibcon#wrote, iclass 13, count 0 2006.257.05:54:33.28#ibcon#about to read 3, iclass 13, count 0 2006.257.05:54:33.30#ibcon#read 3, iclass 13, count 0 2006.257.05:54:33.30#ibcon#about to read 4, iclass 13, count 0 2006.257.05:54:33.30#ibcon#read 4, iclass 13, count 0 2006.257.05:54:33.30#ibcon#about to read 5, iclass 13, count 0 2006.257.05:54:33.30#ibcon#read 5, iclass 13, count 0 2006.257.05:54:33.30#ibcon#about to read 6, iclass 13, count 0 2006.257.05:54:33.30#ibcon#read 6, iclass 13, count 0 2006.257.05:54:33.30#ibcon#end of sib2, iclass 13, count 0 2006.257.05:54:33.30#ibcon#*mode == 0, iclass 13, count 0 2006.257.05:54:33.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.05:54:33.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:54:33.30#ibcon#*before write, iclass 13, count 0 2006.257.05:54:33.30#ibcon#enter sib2, iclass 13, count 0 2006.257.05:54:33.30#ibcon#flushed, iclass 13, count 0 2006.257.05:54:33.30#ibcon#about to write, iclass 13, count 0 2006.257.05:54:33.30#ibcon#wrote, iclass 13, count 0 2006.257.05:54:33.30#ibcon#about to read 3, iclass 13, count 0 2006.257.05:54:33.34#ibcon#read 3, iclass 13, count 0 2006.257.05:54:33.34#ibcon#about to read 4, iclass 13, count 0 2006.257.05:54:33.34#ibcon#read 4, iclass 13, count 0 2006.257.05:54:33.34#ibcon#about to read 5, iclass 13, count 0 2006.257.05:54:33.34#ibcon#read 5, iclass 13, count 0 2006.257.05:54:33.34#ibcon#about to read 6, iclass 13, count 0 2006.257.05:54:33.34#ibcon#read 6, iclass 13, count 0 2006.257.05:54:33.34#ibcon#end of sib2, iclass 13, count 0 2006.257.05:54:33.34#ibcon#*after write, iclass 13, count 0 2006.257.05:54:33.34#ibcon#*before return 0, iclass 13, count 0 2006.257.05:54:33.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:54:33.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.05:54:33.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.05:54:33.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.05:54:33.34$vck44/va=7,4 2006.257.05:54:33.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.05:54:33.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.05:54:33.34#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:33.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:54:33.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:54:33.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:54:33.40#ibcon#enter wrdev, iclass 15, count 2 2006.257.05:54:33.40#ibcon#first serial, iclass 15, count 2 2006.257.05:54:33.40#ibcon#enter sib2, iclass 15, count 2 2006.257.05:54:33.40#ibcon#flushed, iclass 15, count 2 2006.257.05:54:33.40#ibcon#about to write, iclass 15, count 2 2006.257.05:54:33.40#ibcon#wrote, iclass 15, count 2 2006.257.05:54:33.40#ibcon#about to read 3, iclass 15, count 2 2006.257.05:54:33.42#ibcon#read 3, iclass 15, count 2 2006.257.05:54:33.42#ibcon#about to read 4, iclass 15, count 2 2006.257.05:54:33.42#ibcon#read 4, iclass 15, count 2 2006.257.05:54:33.42#ibcon#about to read 5, iclass 15, count 2 2006.257.05:54:33.42#ibcon#read 5, iclass 15, count 2 2006.257.05:54:33.42#ibcon#about to read 6, iclass 15, count 2 2006.257.05:54:33.42#ibcon#read 6, iclass 15, count 2 2006.257.05:54:33.42#ibcon#end of sib2, iclass 15, count 2 2006.257.05:54:33.42#ibcon#*mode == 0, iclass 15, count 2 2006.257.05:54:33.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.05:54:33.42#ibcon#[25=AT07-04\r\n] 2006.257.05:54:33.42#ibcon#*before write, iclass 15, count 2 2006.257.05:54:33.42#ibcon#enter sib2, iclass 15, count 2 2006.257.05:54:33.42#ibcon#flushed, iclass 15, count 2 2006.257.05:54:33.42#ibcon#about to write, iclass 15, count 2 2006.257.05:54:33.42#ibcon#wrote, iclass 15, count 2 2006.257.05:54:33.42#ibcon#about to read 3, iclass 15, count 2 2006.257.05:54:33.45#ibcon#read 3, iclass 15, count 2 2006.257.05:54:33.45#ibcon#about to read 4, iclass 15, count 2 2006.257.05:54:33.45#ibcon#read 4, iclass 15, count 2 2006.257.05:54:33.45#ibcon#about to read 5, iclass 15, count 2 2006.257.05:54:33.45#ibcon#read 5, iclass 15, count 2 2006.257.05:54:33.45#ibcon#about to read 6, iclass 15, count 2 2006.257.05:54:33.45#ibcon#read 6, iclass 15, count 2 2006.257.05:54:33.45#ibcon#end of sib2, iclass 15, count 2 2006.257.05:54:33.45#ibcon#*after write, iclass 15, count 2 2006.257.05:54:33.45#ibcon#*before return 0, iclass 15, count 2 2006.257.05:54:33.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:54:33.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.05:54:33.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.05:54:33.45#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:33.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:54:33.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:54:33.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:54:33.57#ibcon#enter wrdev, iclass 15, count 0 2006.257.05:54:33.57#ibcon#first serial, iclass 15, count 0 2006.257.05:54:33.57#ibcon#enter sib2, iclass 15, count 0 2006.257.05:54:33.57#ibcon#flushed, iclass 15, count 0 2006.257.05:54:33.57#ibcon#about to write, iclass 15, count 0 2006.257.05:54:33.57#ibcon#wrote, iclass 15, count 0 2006.257.05:54:33.57#ibcon#about to read 3, iclass 15, count 0 2006.257.05:54:33.59#ibcon#read 3, iclass 15, count 0 2006.257.05:54:33.59#ibcon#about to read 4, iclass 15, count 0 2006.257.05:54:33.59#ibcon#read 4, iclass 15, count 0 2006.257.05:54:33.59#ibcon#about to read 5, iclass 15, count 0 2006.257.05:54:33.59#ibcon#read 5, iclass 15, count 0 2006.257.05:54:33.59#ibcon#about to read 6, iclass 15, count 0 2006.257.05:54:33.59#ibcon#read 6, iclass 15, count 0 2006.257.05:54:33.59#ibcon#end of sib2, iclass 15, count 0 2006.257.05:54:33.59#ibcon#*mode == 0, iclass 15, count 0 2006.257.05:54:33.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.05:54:33.59#ibcon#[25=USB\r\n] 2006.257.05:54:33.59#ibcon#*before write, iclass 15, count 0 2006.257.05:54:33.59#ibcon#enter sib2, iclass 15, count 0 2006.257.05:54:33.59#ibcon#flushed, iclass 15, count 0 2006.257.05:54:33.59#ibcon#about to write, iclass 15, count 0 2006.257.05:54:33.59#ibcon#wrote, iclass 15, count 0 2006.257.05:54:33.59#ibcon#about to read 3, iclass 15, count 0 2006.257.05:54:33.62#ibcon#read 3, iclass 15, count 0 2006.257.05:54:33.62#ibcon#about to read 4, iclass 15, count 0 2006.257.05:54:33.62#ibcon#read 4, iclass 15, count 0 2006.257.05:54:33.62#ibcon#about to read 5, iclass 15, count 0 2006.257.05:54:33.62#ibcon#read 5, iclass 15, count 0 2006.257.05:54:33.62#ibcon#about to read 6, iclass 15, count 0 2006.257.05:54:33.62#ibcon#read 6, iclass 15, count 0 2006.257.05:54:33.62#ibcon#end of sib2, iclass 15, count 0 2006.257.05:54:33.62#ibcon#*after write, iclass 15, count 0 2006.257.05:54:33.62#ibcon#*before return 0, iclass 15, count 0 2006.257.05:54:33.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:54:33.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.05:54:33.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.05:54:33.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.05:54:33.62$vck44/valo=8,884.99 2006.257.05:54:33.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.05:54:33.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.05:54:33.62#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:33.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:33.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:33.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:33.62#ibcon#enter wrdev, iclass 17, count 0 2006.257.05:54:33.62#ibcon#first serial, iclass 17, count 0 2006.257.05:54:33.62#ibcon#enter sib2, iclass 17, count 0 2006.257.05:54:33.62#ibcon#flushed, iclass 17, count 0 2006.257.05:54:33.62#ibcon#about to write, iclass 17, count 0 2006.257.05:54:33.62#ibcon#wrote, iclass 17, count 0 2006.257.05:54:33.62#ibcon#about to read 3, iclass 17, count 0 2006.257.05:54:33.64#ibcon#read 3, iclass 17, count 0 2006.257.05:54:33.64#ibcon#about to read 4, iclass 17, count 0 2006.257.05:54:33.64#ibcon#read 4, iclass 17, count 0 2006.257.05:54:33.64#ibcon#about to read 5, iclass 17, count 0 2006.257.05:54:33.64#ibcon#read 5, iclass 17, count 0 2006.257.05:54:33.64#ibcon#about to read 6, iclass 17, count 0 2006.257.05:54:33.64#ibcon#read 6, iclass 17, count 0 2006.257.05:54:33.64#ibcon#end of sib2, iclass 17, count 0 2006.257.05:54:33.64#ibcon#*mode == 0, iclass 17, count 0 2006.257.05:54:33.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.05:54:33.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:54:33.64#ibcon#*before write, iclass 17, count 0 2006.257.05:54:33.64#ibcon#enter sib2, iclass 17, count 0 2006.257.05:54:33.64#ibcon#flushed, iclass 17, count 0 2006.257.05:54:33.64#ibcon#about to write, iclass 17, count 0 2006.257.05:54:33.64#ibcon#wrote, iclass 17, count 0 2006.257.05:54:33.64#ibcon#about to read 3, iclass 17, count 0 2006.257.05:54:33.68#ibcon#read 3, iclass 17, count 0 2006.257.05:54:33.68#ibcon#about to read 4, iclass 17, count 0 2006.257.05:54:33.68#ibcon#read 4, iclass 17, count 0 2006.257.05:54:33.68#ibcon#about to read 5, iclass 17, count 0 2006.257.05:54:33.68#ibcon#read 5, iclass 17, count 0 2006.257.05:54:33.68#ibcon#about to read 6, iclass 17, count 0 2006.257.05:54:33.68#ibcon#read 6, iclass 17, count 0 2006.257.05:54:33.68#ibcon#end of sib2, iclass 17, count 0 2006.257.05:54:33.68#ibcon#*after write, iclass 17, count 0 2006.257.05:54:33.68#ibcon#*before return 0, iclass 17, count 0 2006.257.05:54:33.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:33.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:33.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.05:54:33.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.05:54:33.68$vck44/va=8,4 2006.257.05:54:33.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.05:54:33.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.05:54:33.68#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:33.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:33.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:33.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:33.74#ibcon#enter wrdev, iclass 19, count 2 2006.257.05:54:33.74#ibcon#first serial, iclass 19, count 2 2006.257.05:54:33.74#ibcon#enter sib2, iclass 19, count 2 2006.257.05:54:33.74#ibcon#flushed, iclass 19, count 2 2006.257.05:54:33.74#ibcon#about to write, iclass 19, count 2 2006.257.05:54:33.74#ibcon#wrote, iclass 19, count 2 2006.257.05:54:33.74#ibcon#about to read 3, iclass 19, count 2 2006.257.05:54:33.76#ibcon#read 3, iclass 19, count 2 2006.257.05:54:33.76#ibcon#about to read 4, iclass 19, count 2 2006.257.05:54:33.76#ibcon#read 4, iclass 19, count 2 2006.257.05:54:33.76#ibcon#about to read 5, iclass 19, count 2 2006.257.05:54:33.76#ibcon#read 5, iclass 19, count 2 2006.257.05:54:33.76#ibcon#about to read 6, iclass 19, count 2 2006.257.05:54:33.76#ibcon#read 6, iclass 19, count 2 2006.257.05:54:33.76#ibcon#end of sib2, iclass 19, count 2 2006.257.05:54:33.76#ibcon#*mode == 0, iclass 19, count 2 2006.257.05:54:33.76#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.05:54:33.76#ibcon#[25=AT08-04\r\n] 2006.257.05:54:33.76#ibcon#*before write, iclass 19, count 2 2006.257.05:54:33.76#ibcon#enter sib2, iclass 19, count 2 2006.257.05:54:33.76#ibcon#flushed, iclass 19, count 2 2006.257.05:54:33.76#ibcon#about to write, iclass 19, count 2 2006.257.05:54:33.76#ibcon#wrote, iclass 19, count 2 2006.257.05:54:33.76#ibcon#about to read 3, iclass 19, count 2 2006.257.05:54:33.79#ibcon#read 3, iclass 19, count 2 2006.257.05:54:33.79#ibcon#about to read 4, iclass 19, count 2 2006.257.05:54:33.79#ibcon#read 4, iclass 19, count 2 2006.257.05:54:33.79#ibcon#about to read 5, iclass 19, count 2 2006.257.05:54:33.79#ibcon#read 5, iclass 19, count 2 2006.257.05:54:33.79#ibcon#about to read 6, iclass 19, count 2 2006.257.05:54:33.79#ibcon#read 6, iclass 19, count 2 2006.257.05:54:33.79#ibcon#end of sib2, iclass 19, count 2 2006.257.05:54:33.79#ibcon#*after write, iclass 19, count 2 2006.257.05:54:33.79#ibcon#*before return 0, iclass 19, count 2 2006.257.05:54:33.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:33.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:33.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.05:54:33.79#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:33.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:33.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:33.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:33.91#ibcon#enter wrdev, iclass 19, count 0 2006.257.05:54:33.91#ibcon#first serial, iclass 19, count 0 2006.257.05:54:33.91#ibcon#enter sib2, iclass 19, count 0 2006.257.05:54:33.91#ibcon#flushed, iclass 19, count 0 2006.257.05:54:33.91#ibcon#about to write, iclass 19, count 0 2006.257.05:54:33.91#ibcon#wrote, iclass 19, count 0 2006.257.05:54:33.91#ibcon#about to read 3, iclass 19, count 0 2006.257.05:54:33.93#ibcon#read 3, iclass 19, count 0 2006.257.05:54:33.93#ibcon#about to read 4, iclass 19, count 0 2006.257.05:54:33.93#ibcon#read 4, iclass 19, count 0 2006.257.05:54:33.93#ibcon#about to read 5, iclass 19, count 0 2006.257.05:54:33.93#ibcon#read 5, iclass 19, count 0 2006.257.05:54:33.93#ibcon#about to read 6, iclass 19, count 0 2006.257.05:54:33.93#ibcon#read 6, iclass 19, count 0 2006.257.05:54:33.93#ibcon#end of sib2, iclass 19, count 0 2006.257.05:54:33.93#ibcon#*mode == 0, iclass 19, count 0 2006.257.05:54:33.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.05:54:33.93#ibcon#[25=USB\r\n] 2006.257.05:54:33.93#ibcon#*before write, iclass 19, count 0 2006.257.05:54:33.93#ibcon#enter sib2, iclass 19, count 0 2006.257.05:54:33.93#ibcon#flushed, iclass 19, count 0 2006.257.05:54:33.93#ibcon#about to write, iclass 19, count 0 2006.257.05:54:33.93#ibcon#wrote, iclass 19, count 0 2006.257.05:54:33.93#ibcon#about to read 3, iclass 19, count 0 2006.257.05:54:33.96#ibcon#read 3, iclass 19, count 0 2006.257.05:54:33.96#ibcon#about to read 4, iclass 19, count 0 2006.257.05:54:33.96#ibcon#read 4, iclass 19, count 0 2006.257.05:54:33.96#ibcon#about to read 5, iclass 19, count 0 2006.257.05:54:33.96#ibcon#read 5, iclass 19, count 0 2006.257.05:54:33.96#ibcon#about to read 6, iclass 19, count 0 2006.257.05:54:33.96#ibcon#read 6, iclass 19, count 0 2006.257.05:54:33.96#ibcon#end of sib2, iclass 19, count 0 2006.257.05:54:33.96#ibcon#*after write, iclass 19, count 0 2006.257.05:54:33.96#ibcon#*before return 0, iclass 19, count 0 2006.257.05:54:33.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:33.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:33.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.05:54:33.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.05:54:33.96$vck44/vblo=1,629.99 2006.257.05:54:33.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.05:54:33.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.05:54:33.96#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:33.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:33.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:33.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:33.96#ibcon#enter wrdev, iclass 21, count 0 2006.257.05:54:33.96#ibcon#first serial, iclass 21, count 0 2006.257.05:54:33.96#ibcon#enter sib2, iclass 21, count 0 2006.257.05:54:33.96#ibcon#flushed, iclass 21, count 0 2006.257.05:54:33.96#ibcon#about to write, iclass 21, count 0 2006.257.05:54:33.96#ibcon#wrote, iclass 21, count 0 2006.257.05:54:33.96#ibcon#about to read 3, iclass 21, count 0 2006.257.05:54:33.98#ibcon#read 3, iclass 21, count 0 2006.257.05:54:33.98#ibcon#about to read 4, iclass 21, count 0 2006.257.05:54:33.98#ibcon#read 4, iclass 21, count 0 2006.257.05:54:33.98#ibcon#about to read 5, iclass 21, count 0 2006.257.05:54:33.98#ibcon#read 5, iclass 21, count 0 2006.257.05:54:33.98#ibcon#about to read 6, iclass 21, count 0 2006.257.05:54:33.98#ibcon#read 6, iclass 21, count 0 2006.257.05:54:33.98#ibcon#end of sib2, iclass 21, count 0 2006.257.05:54:33.98#ibcon#*mode == 0, iclass 21, count 0 2006.257.05:54:33.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.05:54:33.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:54:33.98#ibcon#*before write, iclass 21, count 0 2006.257.05:54:33.98#ibcon#enter sib2, iclass 21, count 0 2006.257.05:54:33.98#ibcon#flushed, iclass 21, count 0 2006.257.05:54:33.98#ibcon#about to write, iclass 21, count 0 2006.257.05:54:33.98#ibcon#wrote, iclass 21, count 0 2006.257.05:54:33.98#ibcon#about to read 3, iclass 21, count 0 2006.257.05:54:34.02#ibcon#read 3, iclass 21, count 0 2006.257.05:54:34.02#ibcon#about to read 4, iclass 21, count 0 2006.257.05:54:34.02#ibcon#read 4, iclass 21, count 0 2006.257.05:54:34.02#ibcon#about to read 5, iclass 21, count 0 2006.257.05:54:34.02#ibcon#read 5, iclass 21, count 0 2006.257.05:54:34.02#ibcon#about to read 6, iclass 21, count 0 2006.257.05:54:34.02#ibcon#read 6, iclass 21, count 0 2006.257.05:54:34.02#ibcon#end of sib2, iclass 21, count 0 2006.257.05:54:34.02#ibcon#*after write, iclass 21, count 0 2006.257.05:54:34.02#ibcon#*before return 0, iclass 21, count 0 2006.257.05:54:34.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:34.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:34.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.05:54:34.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.05:54:34.02$vck44/vb=1,4 2006.257.05:54:34.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.05:54:34.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.05:54:34.02#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:34.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:54:34.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:54:34.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:54:34.02#ibcon#enter wrdev, iclass 23, count 2 2006.257.05:54:34.02#ibcon#first serial, iclass 23, count 2 2006.257.05:54:34.02#ibcon#enter sib2, iclass 23, count 2 2006.257.05:54:34.02#ibcon#flushed, iclass 23, count 2 2006.257.05:54:34.02#ibcon#about to write, iclass 23, count 2 2006.257.05:54:34.02#ibcon#wrote, iclass 23, count 2 2006.257.05:54:34.02#ibcon#about to read 3, iclass 23, count 2 2006.257.05:54:34.04#ibcon#read 3, iclass 23, count 2 2006.257.05:54:34.04#ibcon#about to read 4, iclass 23, count 2 2006.257.05:54:34.04#ibcon#read 4, iclass 23, count 2 2006.257.05:54:34.04#ibcon#about to read 5, iclass 23, count 2 2006.257.05:54:34.04#ibcon#read 5, iclass 23, count 2 2006.257.05:54:34.04#ibcon#about to read 6, iclass 23, count 2 2006.257.05:54:34.04#ibcon#read 6, iclass 23, count 2 2006.257.05:54:34.04#ibcon#end of sib2, iclass 23, count 2 2006.257.05:54:34.04#ibcon#*mode == 0, iclass 23, count 2 2006.257.05:54:34.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.05:54:34.04#ibcon#[27=AT01-04\r\n] 2006.257.05:54:34.04#ibcon#*before write, iclass 23, count 2 2006.257.05:54:34.04#ibcon#enter sib2, iclass 23, count 2 2006.257.05:54:34.04#ibcon#flushed, iclass 23, count 2 2006.257.05:54:34.04#ibcon#about to write, iclass 23, count 2 2006.257.05:54:34.04#ibcon#wrote, iclass 23, count 2 2006.257.05:54:34.04#ibcon#about to read 3, iclass 23, count 2 2006.257.05:54:34.07#ibcon#read 3, iclass 23, count 2 2006.257.05:54:34.07#ibcon#about to read 4, iclass 23, count 2 2006.257.05:54:34.07#ibcon#read 4, iclass 23, count 2 2006.257.05:54:34.07#ibcon#about to read 5, iclass 23, count 2 2006.257.05:54:34.07#ibcon#read 5, iclass 23, count 2 2006.257.05:54:34.07#ibcon#about to read 6, iclass 23, count 2 2006.257.05:54:34.07#ibcon#read 6, iclass 23, count 2 2006.257.05:54:34.07#ibcon#end of sib2, iclass 23, count 2 2006.257.05:54:34.07#ibcon#*after write, iclass 23, count 2 2006.257.05:54:34.07#ibcon#*before return 0, iclass 23, count 2 2006.257.05:54:34.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:54:34.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.05:54:34.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.05:54:34.07#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:34.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:54:34.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:54:34.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:54:34.19#ibcon#enter wrdev, iclass 23, count 0 2006.257.05:54:34.19#ibcon#first serial, iclass 23, count 0 2006.257.05:54:34.19#ibcon#enter sib2, iclass 23, count 0 2006.257.05:54:34.19#ibcon#flushed, iclass 23, count 0 2006.257.05:54:34.19#ibcon#about to write, iclass 23, count 0 2006.257.05:54:34.19#ibcon#wrote, iclass 23, count 0 2006.257.05:54:34.19#ibcon#about to read 3, iclass 23, count 0 2006.257.05:54:34.21#ibcon#read 3, iclass 23, count 0 2006.257.05:54:34.21#ibcon#about to read 4, iclass 23, count 0 2006.257.05:54:34.21#ibcon#read 4, iclass 23, count 0 2006.257.05:54:34.21#ibcon#about to read 5, iclass 23, count 0 2006.257.05:54:34.21#ibcon#read 5, iclass 23, count 0 2006.257.05:54:34.21#ibcon#about to read 6, iclass 23, count 0 2006.257.05:54:34.21#ibcon#read 6, iclass 23, count 0 2006.257.05:54:34.21#ibcon#end of sib2, iclass 23, count 0 2006.257.05:54:34.21#ibcon#*mode == 0, iclass 23, count 0 2006.257.05:54:34.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.05:54:34.21#ibcon#[27=USB\r\n] 2006.257.05:54:34.21#ibcon#*before write, iclass 23, count 0 2006.257.05:54:34.21#ibcon#enter sib2, iclass 23, count 0 2006.257.05:54:34.21#ibcon#flushed, iclass 23, count 0 2006.257.05:54:34.21#ibcon#about to write, iclass 23, count 0 2006.257.05:54:34.21#ibcon#wrote, iclass 23, count 0 2006.257.05:54:34.21#ibcon#about to read 3, iclass 23, count 0 2006.257.05:54:34.24#ibcon#read 3, iclass 23, count 0 2006.257.05:54:34.24#ibcon#about to read 4, iclass 23, count 0 2006.257.05:54:34.24#ibcon#read 4, iclass 23, count 0 2006.257.05:54:34.24#ibcon#about to read 5, iclass 23, count 0 2006.257.05:54:34.24#ibcon#read 5, iclass 23, count 0 2006.257.05:54:34.24#ibcon#about to read 6, iclass 23, count 0 2006.257.05:54:34.24#ibcon#read 6, iclass 23, count 0 2006.257.05:54:34.24#ibcon#end of sib2, iclass 23, count 0 2006.257.05:54:34.24#ibcon#*after write, iclass 23, count 0 2006.257.05:54:34.24#ibcon#*before return 0, iclass 23, count 0 2006.257.05:54:34.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:54:34.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.05:54:34.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.05:54:34.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.05:54:34.24$vck44/vblo=2,634.99 2006.257.05:54:34.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.05:54:34.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.05:54:34.24#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:34.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:34.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:34.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:34.24#ibcon#enter wrdev, iclass 25, count 0 2006.257.05:54:34.24#ibcon#first serial, iclass 25, count 0 2006.257.05:54:34.24#ibcon#enter sib2, iclass 25, count 0 2006.257.05:54:34.24#ibcon#flushed, iclass 25, count 0 2006.257.05:54:34.24#ibcon#about to write, iclass 25, count 0 2006.257.05:54:34.24#ibcon#wrote, iclass 25, count 0 2006.257.05:54:34.24#ibcon#about to read 3, iclass 25, count 0 2006.257.05:54:34.26#ibcon#read 3, iclass 25, count 0 2006.257.05:54:34.26#ibcon#about to read 4, iclass 25, count 0 2006.257.05:54:34.26#ibcon#read 4, iclass 25, count 0 2006.257.05:54:34.26#ibcon#about to read 5, iclass 25, count 0 2006.257.05:54:34.26#ibcon#read 5, iclass 25, count 0 2006.257.05:54:34.26#ibcon#about to read 6, iclass 25, count 0 2006.257.05:54:34.26#ibcon#read 6, iclass 25, count 0 2006.257.05:54:34.26#ibcon#end of sib2, iclass 25, count 0 2006.257.05:54:34.26#ibcon#*mode == 0, iclass 25, count 0 2006.257.05:54:34.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.05:54:34.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:54:34.26#ibcon#*before write, iclass 25, count 0 2006.257.05:54:34.26#ibcon#enter sib2, iclass 25, count 0 2006.257.05:54:34.26#ibcon#flushed, iclass 25, count 0 2006.257.05:54:34.26#ibcon#about to write, iclass 25, count 0 2006.257.05:54:34.26#ibcon#wrote, iclass 25, count 0 2006.257.05:54:34.26#ibcon#about to read 3, iclass 25, count 0 2006.257.05:54:34.30#ibcon#read 3, iclass 25, count 0 2006.257.05:54:34.30#ibcon#about to read 4, iclass 25, count 0 2006.257.05:54:34.30#ibcon#read 4, iclass 25, count 0 2006.257.05:54:34.30#ibcon#about to read 5, iclass 25, count 0 2006.257.05:54:34.30#ibcon#read 5, iclass 25, count 0 2006.257.05:54:34.30#ibcon#about to read 6, iclass 25, count 0 2006.257.05:54:34.30#ibcon#read 6, iclass 25, count 0 2006.257.05:54:34.30#ibcon#end of sib2, iclass 25, count 0 2006.257.05:54:34.30#ibcon#*after write, iclass 25, count 0 2006.257.05:54:34.30#ibcon#*before return 0, iclass 25, count 0 2006.257.05:54:34.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:34.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.05:54:34.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.05:54:34.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.05:54:34.30$vck44/vb=2,5 2006.257.05:54:34.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.05:54:34.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.05:54:34.30#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:34.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:34.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:34.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:34.36#ibcon#enter wrdev, iclass 27, count 2 2006.257.05:54:34.36#ibcon#first serial, iclass 27, count 2 2006.257.05:54:34.36#ibcon#enter sib2, iclass 27, count 2 2006.257.05:54:34.36#ibcon#flushed, iclass 27, count 2 2006.257.05:54:34.36#ibcon#about to write, iclass 27, count 2 2006.257.05:54:34.36#ibcon#wrote, iclass 27, count 2 2006.257.05:54:34.36#ibcon#about to read 3, iclass 27, count 2 2006.257.05:54:34.38#ibcon#read 3, iclass 27, count 2 2006.257.05:54:34.38#ibcon#about to read 4, iclass 27, count 2 2006.257.05:54:34.38#ibcon#read 4, iclass 27, count 2 2006.257.05:54:34.38#ibcon#about to read 5, iclass 27, count 2 2006.257.05:54:34.38#ibcon#read 5, iclass 27, count 2 2006.257.05:54:34.38#ibcon#about to read 6, iclass 27, count 2 2006.257.05:54:34.38#ibcon#read 6, iclass 27, count 2 2006.257.05:54:34.38#ibcon#end of sib2, iclass 27, count 2 2006.257.05:54:34.38#ibcon#*mode == 0, iclass 27, count 2 2006.257.05:54:34.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.05:54:34.38#ibcon#[27=AT02-05\r\n] 2006.257.05:54:34.38#ibcon#*before write, iclass 27, count 2 2006.257.05:54:34.38#ibcon#enter sib2, iclass 27, count 2 2006.257.05:54:34.38#ibcon#flushed, iclass 27, count 2 2006.257.05:54:34.38#ibcon#about to write, iclass 27, count 2 2006.257.05:54:34.38#ibcon#wrote, iclass 27, count 2 2006.257.05:54:34.38#ibcon#about to read 3, iclass 27, count 2 2006.257.05:54:34.41#ibcon#read 3, iclass 27, count 2 2006.257.05:54:34.41#ibcon#about to read 4, iclass 27, count 2 2006.257.05:54:34.41#ibcon#read 4, iclass 27, count 2 2006.257.05:54:34.41#ibcon#about to read 5, iclass 27, count 2 2006.257.05:54:34.41#ibcon#read 5, iclass 27, count 2 2006.257.05:54:34.41#ibcon#about to read 6, iclass 27, count 2 2006.257.05:54:34.41#ibcon#read 6, iclass 27, count 2 2006.257.05:54:34.41#ibcon#end of sib2, iclass 27, count 2 2006.257.05:54:34.41#ibcon#*after write, iclass 27, count 2 2006.257.05:54:34.41#ibcon#*before return 0, iclass 27, count 2 2006.257.05:54:34.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:34.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.05:54:34.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.05:54:34.41#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:34.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:34.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:34.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:34.53#ibcon#enter wrdev, iclass 27, count 0 2006.257.05:54:34.53#ibcon#first serial, iclass 27, count 0 2006.257.05:54:34.53#ibcon#enter sib2, iclass 27, count 0 2006.257.05:54:34.53#ibcon#flushed, iclass 27, count 0 2006.257.05:54:34.53#ibcon#about to write, iclass 27, count 0 2006.257.05:54:34.53#ibcon#wrote, iclass 27, count 0 2006.257.05:54:34.53#ibcon#about to read 3, iclass 27, count 0 2006.257.05:54:34.55#ibcon#read 3, iclass 27, count 0 2006.257.05:54:34.55#ibcon#about to read 4, iclass 27, count 0 2006.257.05:54:34.55#ibcon#read 4, iclass 27, count 0 2006.257.05:54:34.55#ibcon#about to read 5, iclass 27, count 0 2006.257.05:54:34.55#ibcon#read 5, iclass 27, count 0 2006.257.05:54:34.55#ibcon#about to read 6, iclass 27, count 0 2006.257.05:54:34.55#ibcon#read 6, iclass 27, count 0 2006.257.05:54:34.55#ibcon#end of sib2, iclass 27, count 0 2006.257.05:54:34.55#ibcon#*mode == 0, iclass 27, count 0 2006.257.05:54:34.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.05:54:34.55#ibcon#[27=USB\r\n] 2006.257.05:54:34.55#ibcon#*before write, iclass 27, count 0 2006.257.05:54:34.55#ibcon#enter sib2, iclass 27, count 0 2006.257.05:54:34.55#ibcon#flushed, iclass 27, count 0 2006.257.05:54:34.55#ibcon#about to write, iclass 27, count 0 2006.257.05:54:34.55#ibcon#wrote, iclass 27, count 0 2006.257.05:54:34.55#ibcon#about to read 3, iclass 27, count 0 2006.257.05:54:34.58#ibcon#read 3, iclass 27, count 0 2006.257.05:54:34.58#ibcon#about to read 4, iclass 27, count 0 2006.257.05:54:34.58#ibcon#read 4, iclass 27, count 0 2006.257.05:54:34.58#ibcon#about to read 5, iclass 27, count 0 2006.257.05:54:34.58#ibcon#read 5, iclass 27, count 0 2006.257.05:54:34.58#ibcon#about to read 6, iclass 27, count 0 2006.257.05:54:34.58#ibcon#read 6, iclass 27, count 0 2006.257.05:54:34.58#ibcon#end of sib2, iclass 27, count 0 2006.257.05:54:34.58#ibcon#*after write, iclass 27, count 0 2006.257.05:54:34.58#ibcon#*before return 0, iclass 27, count 0 2006.257.05:54:34.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:34.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.05:54:34.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.05:54:34.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.05:54:34.58$vck44/vblo=3,649.99 2006.257.05:54:34.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.05:54:34.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.05:54:34.58#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:34.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:34.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:34.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:34.58#ibcon#enter wrdev, iclass 29, count 0 2006.257.05:54:34.58#ibcon#first serial, iclass 29, count 0 2006.257.05:54:34.58#ibcon#enter sib2, iclass 29, count 0 2006.257.05:54:34.58#ibcon#flushed, iclass 29, count 0 2006.257.05:54:34.58#ibcon#about to write, iclass 29, count 0 2006.257.05:54:34.58#ibcon#wrote, iclass 29, count 0 2006.257.05:54:34.58#ibcon#about to read 3, iclass 29, count 0 2006.257.05:54:34.60#ibcon#read 3, iclass 29, count 0 2006.257.05:54:34.60#ibcon#about to read 4, iclass 29, count 0 2006.257.05:54:34.60#ibcon#read 4, iclass 29, count 0 2006.257.05:54:34.60#ibcon#about to read 5, iclass 29, count 0 2006.257.05:54:34.60#ibcon#read 5, iclass 29, count 0 2006.257.05:54:34.60#ibcon#about to read 6, iclass 29, count 0 2006.257.05:54:34.60#ibcon#read 6, iclass 29, count 0 2006.257.05:54:34.60#ibcon#end of sib2, iclass 29, count 0 2006.257.05:54:34.60#ibcon#*mode == 0, iclass 29, count 0 2006.257.05:54:34.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.05:54:34.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:54:34.60#ibcon#*before write, iclass 29, count 0 2006.257.05:54:34.60#ibcon#enter sib2, iclass 29, count 0 2006.257.05:54:34.60#ibcon#flushed, iclass 29, count 0 2006.257.05:54:34.60#ibcon#about to write, iclass 29, count 0 2006.257.05:54:34.60#ibcon#wrote, iclass 29, count 0 2006.257.05:54:34.60#ibcon#about to read 3, iclass 29, count 0 2006.257.05:54:34.64#ibcon#read 3, iclass 29, count 0 2006.257.05:54:34.64#ibcon#about to read 4, iclass 29, count 0 2006.257.05:54:34.64#ibcon#read 4, iclass 29, count 0 2006.257.05:54:34.64#ibcon#about to read 5, iclass 29, count 0 2006.257.05:54:34.64#ibcon#read 5, iclass 29, count 0 2006.257.05:54:34.64#ibcon#about to read 6, iclass 29, count 0 2006.257.05:54:34.64#ibcon#read 6, iclass 29, count 0 2006.257.05:54:34.64#ibcon#end of sib2, iclass 29, count 0 2006.257.05:54:34.64#ibcon#*after write, iclass 29, count 0 2006.257.05:54:34.64#ibcon#*before return 0, iclass 29, count 0 2006.257.05:54:34.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:34.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.05:54:34.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.05:54:34.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.05:54:34.64$vck44/vb=3,4 2006.257.05:54:34.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.05:54:34.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.05:54:34.64#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:34.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:34.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:34.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:34.70#ibcon#enter wrdev, iclass 31, count 2 2006.257.05:54:34.70#ibcon#first serial, iclass 31, count 2 2006.257.05:54:34.70#ibcon#enter sib2, iclass 31, count 2 2006.257.05:54:34.70#ibcon#flushed, iclass 31, count 2 2006.257.05:54:34.70#ibcon#about to write, iclass 31, count 2 2006.257.05:54:34.70#ibcon#wrote, iclass 31, count 2 2006.257.05:54:34.70#ibcon#about to read 3, iclass 31, count 2 2006.257.05:54:34.72#ibcon#read 3, iclass 31, count 2 2006.257.05:54:34.72#ibcon#about to read 4, iclass 31, count 2 2006.257.05:54:34.72#ibcon#read 4, iclass 31, count 2 2006.257.05:54:34.72#ibcon#about to read 5, iclass 31, count 2 2006.257.05:54:34.72#ibcon#read 5, iclass 31, count 2 2006.257.05:54:34.72#ibcon#about to read 6, iclass 31, count 2 2006.257.05:54:34.72#ibcon#read 6, iclass 31, count 2 2006.257.05:54:34.72#ibcon#end of sib2, iclass 31, count 2 2006.257.05:54:34.72#ibcon#*mode == 0, iclass 31, count 2 2006.257.05:54:34.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.05:54:34.72#ibcon#[27=AT03-04\r\n] 2006.257.05:54:34.72#ibcon#*before write, iclass 31, count 2 2006.257.05:54:34.72#ibcon#enter sib2, iclass 31, count 2 2006.257.05:54:34.72#ibcon#flushed, iclass 31, count 2 2006.257.05:54:34.72#ibcon#about to write, iclass 31, count 2 2006.257.05:54:34.72#ibcon#wrote, iclass 31, count 2 2006.257.05:54:34.72#ibcon#about to read 3, iclass 31, count 2 2006.257.05:54:34.75#ibcon#read 3, iclass 31, count 2 2006.257.05:54:34.75#ibcon#about to read 4, iclass 31, count 2 2006.257.05:54:34.75#ibcon#read 4, iclass 31, count 2 2006.257.05:54:34.75#ibcon#about to read 5, iclass 31, count 2 2006.257.05:54:34.75#ibcon#read 5, iclass 31, count 2 2006.257.05:54:34.75#ibcon#about to read 6, iclass 31, count 2 2006.257.05:54:34.75#ibcon#read 6, iclass 31, count 2 2006.257.05:54:34.75#ibcon#end of sib2, iclass 31, count 2 2006.257.05:54:34.75#ibcon#*after write, iclass 31, count 2 2006.257.05:54:34.75#ibcon#*before return 0, iclass 31, count 2 2006.257.05:54:34.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:34.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.05:54:34.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.05:54:34.75#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:34.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:34.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:34.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:34.87#ibcon#enter wrdev, iclass 31, count 0 2006.257.05:54:34.87#ibcon#first serial, iclass 31, count 0 2006.257.05:54:34.87#ibcon#enter sib2, iclass 31, count 0 2006.257.05:54:34.87#ibcon#flushed, iclass 31, count 0 2006.257.05:54:34.87#ibcon#about to write, iclass 31, count 0 2006.257.05:54:34.87#ibcon#wrote, iclass 31, count 0 2006.257.05:54:34.87#ibcon#about to read 3, iclass 31, count 0 2006.257.05:54:34.89#ibcon#read 3, iclass 31, count 0 2006.257.05:54:34.89#ibcon#about to read 4, iclass 31, count 0 2006.257.05:54:34.89#ibcon#read 4, iclass 31, count 0 2006.257.05:54:34.89#ibcon#about to read 5, iclass 31, count 0 2006.257.05:54:34.89#ibcon#read 5, iclass 31, count 0 2006.257.05:54:34.89#ibcon#about to read 6, iclass 31, count 0 2006.257.05:54:34.89#ibcon#read 6, iclass 31, count 0 2006.257.05:54:34.89#ibcon#end of sib2, iclass 31, count 0 2006.257.05:54:34.89#ibcon#*mode == 0, iclass 31, count 0 2006.257.05:54:34.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.05:54:34.89#ibcon#[27=USB\r\n] 2006.257.05:54:34.89#ibcon#*before write, iclass 31, count 0 2006.257.05:54:34.89#ibcon#enter sib2, iclass 31, count 0 2006.257.05:54:34.89#ibcon#flushed, iclass 31, count 0 2006.257.05:54:34.89#ibcon#about to write, iclass 31, count 0 2006.257.05:54:34.89#ibcon#wrote, iclass 31, count 0 2006.257.05:54:34.89#ibcon#about to read 3, iclass 31, count 0 2006.257.05:54:34.92#ibcon#read 3, iclass 31, count 0 2006.257.05:54:34.92#ibcon#about to read 4, iclass 31, count 0 2006.257.05:54:34.92#ibcon#read 4, iclass 31, count 0 2006.257.05:54:34.92#ibcon#about to read 5, iclass 31, count 0 2006.257.05:54:34.92#ibcon#read 5, iclass 31, count 0 2006.257.05:54:34.92#ibcon#about to read 6, iclass 31, count 0 2006.257.05:54:34.92#ibcon#read 6, iclass 31, count 0 2006.257.05:54:34.92#ibcon#end of sib2, iclass 31, count 0 2006.257.05:54:34.92#ibcon#*after write, iclass 31, count 0 2006.257.05:54:34.92#ibcon#*before return 0, iclass 31, count 0 2006.257.05:54:34.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:34.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.05:54:34.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.05:54:34.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.05:54:34.92$vck44/vblo=4,679.99 2006.257.05:54:34.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.05:54:34.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.05:54:34.92#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:34.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:34.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:34.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:34.92#ibcon#enter wrdev, iclass 33, count 0 2006.257.05:54:34.92#ibcon#first serial, iclass 33, count 0 2006.257.05:54:34.92#ibcon#enter sib2, iclass 33, count 0 2006.257.05:54:34.92#ibcon#flushed, iclass 33, count 0 2006.257.05:54:34.92#ibcon#about to write, iclass 33, count 0 2006.257.05:54:34.92#ibcon#wrote, iclass 33, count 0 2006.257.05:54:34.92#ibcon#about to read 3, iclass 33, count 0 2006.257.05:54:34.94#ibcon#read 3, iclass 33, count 0 2006.257.05:54:34.94#ibcon#about to read 4, iclass 33, count 0 2006.257.05:54:34.94#ibcon#read 4, iclass 33, count 0 2006.257.05:54:34.94#ibcon#about to read 5, iclass 33, count 0 2006.257.05:54:34.94#ibcon#read 5, iclass 33, count 0 2006.257.05:54:34.94#ibcon#about to read 6, iclass 33, count 0 2006.257.05:54:34.94#ibcon#read 6, iclass 33, count 0 2006.257.05:54:34.94#ibcon#end of sib2, iclass 33, count 0 2006.257.05:54:34.94#ibcon#*mode == 0, iclass 33, count 0 2006.257.05:54:34.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.05:54:34.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:54:34.94#ibcon#*before write, iclass 33, count 0 2006.257.05:54:34.94#ibcon#enter sib2, iclass 33, count 0 2006.257.05:54:34.94#ibcon#flushed, iclass 33, count 0 2006.257.05:54:34.94#ibcon#about to write, iclass 33, count 0 2006.257.05:54:34.94#ibcon#wrote, iclass 33, count 0 2006.257.05:54:34.94#ibcon#about to read 3, iclass 33, count 0 2006.257.05:54:34.98#ibcon#read 3, iclass 33, count 0 2006.257.05:54:34.98#ibcon#about to read 4, iclass 33, count 0 2006.257.05:54:34.98#ibcon#read 4, iclass 33, count 0 2006.257.05:54:34.98#ibcon#about to read 5, iclass 33, count 0 2006.257.05:54:34.98#ibcon#read 5, iclass 33, count 0 2006.257.05:54:34.98#ibcon#about to read 6, iclass 33, count 0 2006.257.05:54:34.98#ibcon#read 6, iclass 33, count 0 2006.257.05:54:34.98#ibcon#end of sib2, iclass 33, count 0 2006.257.05:54:34.98#ibcon#*after write, iclass 33, count 0 2006.257.05:54:34.98#ibcon#*before return 0, iclass 33, count 0 2006.257.05:54:34.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:34.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.05:54:34.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.05:54:34.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.05:54:34.98$vck44/vb=4,5 2006.257.05:54:34.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.05:54:34.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.05:54:34.98#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:34.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:35.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:35.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:35.04#ibcon#enter wrdev, iclass 35, count 2 2006.257.05:54:35.04#ibcon#first serial, iclass 35, count 2 2006.257.05:54:35.04#ibcon#enter sib2, iclass 35, count 2 2006.257.05:54:35.04#ibcon#flushed, iclass 35, count 2 2006.257.05:54:35.04#ibcon#about to write, iclass 35, count 2 2006.257.05:54:35.04#ibcon#wrote, iclass 35, count 2 2006.257.05:54:35.04#ibcon#about to read 3, iclass 35, count 2 2006.257.05:54:35.06#ibcon#read 3, iclass 35, count 2 2006.257.05:54:35.06#ibcon#about to read 4, iclass 35, count 2 2006.257.05:54:35.06#ibcon#read 4, iclass 35, count 2 2006.257.05:54:35.06#ibcon#about to read 5, iclass 35, count 2 2006.257.05:54:35.06#ibcon#read 5, iclass 35, count 2 2006.257.05:54:35.06#ibcon#about to read 6, iclass 35, count 2 2006.257.05:54:35.06#ibcon#read 6, iclass 35, count 2 2006.257.05:54:35.06#ibcon#end of sib2, iclass 35, count 2 2006.257.05:54:35.06#ibcon#*mode == 0, iclass 35, count 2 2006.257.05:54:35.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.05:54:35.06#ibcon#[27=AT04-05\r\n] 2006.257.05:54:35.06#ibcon#*before write, iclass 35, count 2 2006.257.05:54:35.06#ibcon#enter sib2, iclass 35, count 2 2006.257.05:54:35.06#ibcon#flushed, iclass 35, count 2 2006.257.05:54:35.06#ibcon#about to write, iclass 35, count 2 2006.257.05:54:35.06#ibcon#wrote, iclass 35, count 2 2006.257.05:54:35.06#ibcon#about to read 3, iclass 35, count 2 2006.257.05:54:35.09#ibcon#read 3, iclass 35, count 2 2006.257.05:54:35.09#ibcon#about to read 4, iclass 35, count 2 2006.257.05:54:35.09#ibcon#read 4, iclass 35, count 2 2006.257.05:54:35.09#ibcon#about to read 5, iclass 35, count 2 2006.257.05:54:35.09#ibcon#read 5, iclass 35, count 2 2006.257.05:54:35.09#ibcon#about to read 6, iclass 35, count 2 2006.257.05:54:35.09#ibcon#read 6, iclass 35, count 2 2006.257.05:54:35.09#ibcon#end of sib2, iclass 35, count 2 2006.257.05:54:35.09#ibcon#*after write, iclass 35, count 2 2006.257.05:54:35.09#ibcon#*before return 0, iclass 35, count 2 2006.257.05:54:35.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:35.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.05:54:35.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.05:54:35.09#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:35.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:35.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:35.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:35.21#ibcon#enter wrdev, iclass 35, count 0 2006.257.05:54:35.21#ibcon#first serial, iclass 35, count 0 2006.257.05:54:35.21#ibcon#enter sib2, iclass 35, count 0 2006.257.05:54:35.21#ibcon#flushed, iclass 35, count 0 2006.257.05:54:35.21#ibcon#about to write, iclass 35, count 0 2006.257.05:54:35.21#ibcon#wrote, iclass 35, count 0 2006.257.05:54:35.21#ibcon#about to read 3, iclass 35, count 0 2006.257.05:54:35.23#ibcon#read 3, iclass 35, count 0 2006.257.05:54:35.23#ibcon#about to read 4, iclass 35, count 0 2006.257.05:54:35.23#ibcon#read 4, iclass 35, count 0 2006.257.05:54:35.23#ibcon#about to read 5, iclass 35, count 0 2006.257.05:54:35.23#ibcon#read 5, iclass 35, count 0 2006.257.05:54:35.23#ibcon#about to read 6, iclass 35, count 0 2006.257.05:54:35.23#ibcon#read 6, iclass 35, count 0 2006.257.05:54:35.23#ibcon#end of sib2, iclass 35, count 0 2006.257.05:54:35.23#ibcon#*mode == 0, iclass 35, count 0 2006.257.05:54:35.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.05:54:35.23#ibcon#[27=USB\r\n] 2006.257.05:54:35.23#ibcon#*before write, iclass 35, count 0 2006.257.05:54:35.23#ibcon#enter sib2, iclass 35, count 0 2006.257.05:54:35.23#ibcon#flushed, iclass 35, count 0 2006.257.05:54:35.23#ibcon#about to write, iclass 35, count 0 2006.257.05:54:35.23#ibcon#wrote, iclass 35, count 0 2006.257.05:54:35.23#ibcon#about to read 3, iclass 35, count 0 2006.257.05:54:35.26#ibcon#read 3, iclass 35, count 0 2006.257.05:54:35.26#ibcon#about to read 4, iclass 35, count 0 2006.257.05:54:35.26#ibcon#read 4, iclass 35, count 0 2006.257.05:54:35.26#ibcon#about to read 5, iclass 35, count 0 2006.257.05:54:35.26#ibcon#read 5, iclass 35, count 0 2006.257.05:54:35.26#ibcon#about to read 6, iclass 35, count 0 2006.257.05:54:35.26#ibcon#read 6, iclass 35, count 0 2006.257.05:54:35.26#ibcon#end of sib2, iclass 35, count 0 2006.257.05:54:35.26#ibcon#*after write, iclass 35, count 0 2006.257.05:54:35.26#ibcon#*before return 0, iclass 35, count 0 2006.257.05:54:35.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:35.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.05:54:35.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.05:54:35.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.05:54:35.26$vck44/vblo=5,709.99 2006.257.05:54:35.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.05:54:35.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.05:54:35.26#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:35.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:35.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:35.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:35.26#ibcon#enter wrdev, iclass 37, count 0 2006.257.05:54:35.26#ibcon#first serial, iclass 37, count 0 2006.257.05:54:35.26#ibcon#enter sib2, iclass 37, count 0 2006.257.05:54:35.26#ibcon#flushed, iclass 37, count 0 2006.257.05:54:35.26#ibcon#about to write, iclass 37, count 0 2006.257.05:54:35.26#ibcon#wrote, iclass 37, count 0 2006.257.05:54:35.26#ibcon#about to read 3, iclass 37, count 0 2006.257.05:54:35.28#ibcon#read 3, iclass 37, count 0 2006.257.05:54:35.28#ibcon#about to read 4, iclass 37, count 0 2006.257.05:54:35.28#ibcon#read 4, iclass 37, count 0 2006.257.05:54:35.28#ibcon#about to read 5, iclass 37, count 0 2006.257.05:54:35.28#ibcon#read 5, iclass 37, count 0 2006.257.05:54:35.28#ibcon#about to read 6, iclass 37, count 0 2006.257.05:54:35.28#ibcon#read 6, iclass 37, count 0 2006.257.05:54:35.28#ibcon#end of sib2, iclass 37, count 0 2006.257.05:54:35.28#ibcon#*mode == 0, iclass 37, count 0 2006.257.05:54:35.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.05:54:35.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:54:35.28#ibcon#*before write, iclass 37, count 0 2006.257.05:54:35.28#ibcon#enter sib2, iclass 37, count 0 2006.257.05:54:35.28#ibcon#flushed, iclass 37, count 0 2006.257.05:54:35.28#ibcon#about to write, iclass 37, count 0 2006.257.05:54:35.28#ibcon#wrote, iclass 37, count 0 2006.257.05:54:35.28#ibcon#about to read 3, iclass 37, count 0 2006.257.05:54:35.32#ibcon#read 3, iclass 37, count 0 2006.257.05:54:35.32#ibcon#about to read 4, iclass 37, count 0 2006.257.05:54:35.32#ibcon#read 4, iclass 37, count 0 2006.257.05:54:35.32#ibcon#about to read 5, iclass 37, count 0 2006.257.05:54:35.32#ibcon#read 5, iclass 37, count 0 2006.257.05:54:35.32#ibcon#about to read 6, iclass 37, count 0 2006.257.05:54:35.32#ibcon#read 6, iclass 37, count 0 2006.257.05:54:35.32#ibcon#end of sib2, iclass 37, count 0 2006.257.05:54:35.32#ibcon#*after write, iclass 37, count 0 2006.257.05:54:35.32#ibcon#*before return 0, iclass 37, count 0 2006.257.05:54:35.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:35.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.05:54:35.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.05:54:35.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.05:54:35.32$vck44/vb=5,4 2006.257.05:54:35.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.05:54:35.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.05:54:35.32#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:35.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:35.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:35.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:35.38#ibcon#enter wrdev, iclass 39, count 2 2006.257.05:54:35.38#ibcon#first serial, iclass 39, count 2 2006.257.05:54:35.38#ibcon#enter sib2, iclass 39, count 2 2006.257.05:54:35.38#ibcon#flushed, iclass 39, count 2 2006.257.05:54:35.38#ibcon#about to write, iclass 39, count 2 2006.257.05:54:35.38#ibcon#wrote, iclass 39, count 2 2006.257.05:54:35.38#ibcon#about to read 3, iclass 39, count 2 2006.257.05:54:35.40#ibcon#read 3, iclass 39, count 2 2006.257.05:54:35.40#ibcon#about to read 4, iclass 39, count 2 2006.257.05:54:35.40#ibcon#read 4, iclass 39, count 2 2006.257.05:54:35.40#ibcon#about to read 5, iclass 39, count 2 2006.257.05:54:35.40#ibcon#read 5, iclass 39, count 2 2006.257.05:54:35.40#ibcon#about to read 6, iclass 39, count 2 2006.257.05:54:35.40#ibcon#read 6, iclass 39, count 2 2006.257.05:54:35.40#ibcon#end of sib2, iclass 39, count 2 2006.257.05:54:35.40#ibcon#*mode == 0, iclass 39, count 2 2006.257.05:54:35.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.05:54:35.40#ibcon#[27=AT05-04\r\n] 2006.257.05:54:35.40#ibcon#*before write, iclass 39, count 2 2006.257.05:54:35.40#ibcon#enter sib2, iclass 39, count 2 2006.257.05:54:35.40#ibcon#flushed, iclass 39, count 2 2006.257.05:54:35.40#ibcon#about to write, iclass 39, count 2 2006.257.05:54:35.40#ibcon#wrote, iclass 39, count 2 2006.257.05:54:35.40#ibcon#about to read 3, iclass 39, count 2 2006.257.05:54:35.43#ibcon#read 3, iclass 39, count 2 2006.257.05:54:35.43#ibcon#about to read 4, iclass 39, count 2 2006.257.05:54:35.43#ibcon#read 4, iclass 39, count 2 2006.257.05:54:35.43#ibcon#about to read 5, iclass 39, count 2 2006.257.05:54:35.43#ibcon#read 5, iclass 39, count 2 2006.257.05:54:35.43#ibcon#about to read 6, iclass 39, count 2 2006.257.05:54:35.43#ibcon#read 6, iclass 39, count 2 2006.257.05:54:35.43#ibcon#end of sib2, iclass 39, count 2 2006.257.05:54:35.43#ibcon#*after write, iclass 39, count 2 2006.257.05:54:35.43#ibcon#*before return 0, iclass 39, count 2 2006.257.05:54:35.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:35.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.05:54:35.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.05:54:35.43#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:35.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:35.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:35.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:35.55#ibcon#enter wrdev, iclass 39, count 0 2006.257.05:54:35.55#ibcon#first serial, iclass 39, count 0 2006.257.05:54:35.55#ibcon#enter sib2, iclass 39, count 0 2006.257.05:54:35.55#ibcon#flushed, iclass 39, count 0 2006.257.05:54:35.55#ibcon#about to write, iclass 39, count 0 2006.257.05:54:35.55#ibcon#wrote, iclass 39, count 0 2006.257.05:54:35.55#ibcon#about to read 3, iclass 39, count 0 2006.257.05:54:35.57#ibcon#read 3, iclass 39, count 0 2006.257.05:54:35.57#ibcon#about to read 4, iclass 39, count 0 2006.257.05:54:35.57#ibcon#read 4, iclass 39, count 0 2006.257.05:54:35.57#ibcon#about to read 5, iclass 39, count 0 2006.257.05:54:35.57#ibcon#read 5, iclass 39, count 0 2006.257.05:54:35.57#ibcon#about to read 6, iclass 39, count 0 2006.257.05:54:35.57#ibcon#read 6, iclass 39, count 0 2006.257.05:54:35.57#ibcon#end of sib2, iclass 39, count 0 2006.257.05:54:35.57#ibcon#*mode == 0, iclass 39, count 0 2006.257.05:54:35.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.05:54:35.57#ibcon#[27=USB\r\n] 2006.257.05:54:35.57#ibcon#*before write, iclass 39, count 0 2006.257.05:54:35.57#ibcon#enter sib2, iclass 39, count 0 2006.257.05:54:35.57#ibcon#flushed, iclass 39, count 0 2006.257.05:54:35.57#ibcon#about to write, iclass 39, count 0 2006.257.05:54:35.57#ibcon#wrote, iclass 39, count 0 2006.257.05:54:35.57#ibcon#about to read 3, iclass 39, count 0 2006.257.05:54:35.60#ibcon#read 3, iclass 39, count 0 2006.257.05:54:35.60#ibcon#about to read 4, iclass 39, count 0 2006.257.05:54:35.60#ibcon#read 4, iclass 39, count 0 2006.257.05:54:35.60#ibcon#about to read 5, iclass 39, count 0 2006.257.05:54:35.60#ibcon#read 5, iclass 39, count 0 2006.257.05:54:35.60#ibcon#about to read 6, iclass 39, count 0 2006.257.05:54:35.60#ibcon#read 6, iclass 39, count 0 2006.257.05:54:35.60#ibcon#end of sib2, iclass 39, count 0 2006.257.05:54:35.60#ibcon#*after write, iclass 39, count 0 2006.257.05:54:35.60#ibcon#*before return 0, iclass 39, count 0 2006.257.05:54:35.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:35.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.05:54:35.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.05:54:35.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.05:54:35.60$vck44/vblo=6,719.99 2006.257.05:54:35.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.05:54:35.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.05:54:35.60#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:35.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:35.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:35.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:35.60#ibcon#enter wrdev, iclass 3, count 0 2006.257.05:54:35.60#ibcon#first serial, iclass 3, count 0 2006.257.05:54:35.60#ibcon#enter sib2, iclass 3, count 0 2006.257.05:54:35.60#ibcon#flushed, iclass 3, count 0 2006.257.05:54:35.60#ibcon#about to write, iclass 3, count 0 2006.257.05:54:35.60#ibcon#wrote, iclass 3, count 0 2006.257.05:54:35.60#ibcon#about to read 3, iclass 3, count 0 2006.257.05:54:35.62#ibcon#read 3, iclass 3, count 0 2006.257.05:54:35.62#ibcon#about to read 4, iclass 3, count 0 2006.257.05:54:35.62#ibcon#read 4, iclass 3, count 0 2006.257.05:54:35.62#ibcon#about to read 5, iclass 3, count 0 2006.257.05:54:35.62#ibcon#read 5, iclass 3, count 0 2006.257.05:54:35.62#ibcon#about to read 6, iclass 3, count 0 2006.257.05:54:35.62#ibcon#read 6, iclass 3, count 0 2006.257.05:54:35.62#ibcon#end of sib2, iclass 3, count 0 2006.257.05:54:35.62#ibcon#*mode == 0, iclass 3, count 0 2006.257.05:54:35.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.05:54:35.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:54:35.62#ibcon#*before write, iclass 3, count 0 2006.257.05:54:35.62#ibcon#enter sib2, iclass 3, count 0 2006.257.05:54:35.62#ibcon#flushed, iclass 3, count 0 2006.257.05:54:35.62#ibcon#about to write, iclass 3, count 0 2006.257.05:54:35.62#ibcon#wrote, iclass 3, count 0 2006.257.05:54:35.62#ibcon#about to read 3, iclass 3, count 0 2006.257.05:54:35.66#ibcon#read 3, iclass 3, count 0 2006.257.05:54:35.66#ibcon#about to read 4, iclass 3, count 0 2006.257.05:54:35.66#ibcon#read 4, iclass 3, count 0 2006.257.05:54:35.66#ibcon#about to read 5, iclass 3, count 0 2006.257.05:54:35.66#ibcon#read 5, iclass 3, count 0 2006.257.05:54:35.66#ibcon#about to read 6, iclass 3, count 0 2006.257.05:54:35.66#ibcon#read 6, iclass 3, count 0 2006.257.05:54:35.66#ibcon#end of sib2, iclass 3, count 0 2006.257.05:54:35.66#ibcon#*after write, iclass 3, count 0 2006.257.05:54:35.66#ibcon#*before return 0, iclass 3, count 0 2006.257.05:54:35.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:35.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.05:54:35.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.05:54:35.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.05:54:35.66$vck44/vb=6,4 2006.257.05:54:35.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.05:54:35.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.05:54:35.66#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:35.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:35.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:35.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:35.72#ibcon#enter wrdev, iclass 5, count 2 2006.257.05:54:35.72#ibcon#first serial, iclass 5, count 2 2006.257.05:54:35.72#ibcon#enter sib2, iclass 5, count 2 2006.257.05:54:35.72#ibcon#flushed, iclass 5, count 2 2006.257.05:54:35.72#ibcon#about to write, iclass 5, count 2 2006.257.05:54:35.72#ibcon#wrote, iclass 5, count 2 2006.257.05:54:35.72#ibcon#about to read 3, iclass 5, count 2 2006.257.05:54:35.74#ibcon#read 3, iclass 5, count 2 2006.257.05:54:35.74#ibcon#about to read 4, iclass 5, count 2 2006.257.05:54:35.74#ibcon#read 4, iclass 5, count 2 2006.257.05:54:35.74#ibcon#about to read 5, iclass 5, count 2 2006.257.05:54:35.74#ibcon#read 5, iclass 5, count 2 2006.257.05:54:35.74#ibcon#about to read 6, iclass 5, count 2 2006.257.05:54:35.74#ibcon#read 6, iclass 5, count 2 2006.257.05:54:35.74#ibcon#end of sib2, iclass 5, count 2 2006.257.05:54:35.74#ibcon#*mode == 0, iclass 5, count 2 2006.257.05:54:35.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.05:54:35.74#ibcon#[27=AT06-04\r\n] 2006.257.05:54:35.74#ibcon#*before write, iclass 5, count 2 2006.257.05:54:35.74#ibcon#enter sib2, iclass 5, count 2 2006.257.05:54:35.74#ibcon#flushed, iclass 5, count 2 2006.257.05:54:35.74#ibcon#about to write, iclass 5, count 2 2006.257.05:54:35.74#ibcon#wrote, iclass 5, count 2 2006.257.05:54:35.74#ibcon#about to read 3, iclass 5, count 2 2006.257.05:54:35.77#ibcon#read 3, iclass 5, count 2 2006.257.05:54:35.77#ibcon#about to read 4, iclass 5, count 2 2006.257.05:54:35.77#ibcon#read 4, iclass 5, count 2 2006.257.05:54:35.77#ibcon#about to read 5, iclass 5, count 2 2006.257.05:54:35.77#ibcon#read 5, iclass 5, count 2 2006.257.05:54:35.77#ibcon#about to read 6, iclass 5, count 2 2006.257.05:54:35.77#ibcon#read 6, iclass 5, count 2 2006.257.05:54:35.77#ibcon#end of sib2, iclass 5, count 2 2006.257.05:54:35.77#ibcon#*after write, iclass 5, count 2 2006.257.05:54:35.77#ibcon#*before return 0, iclass 5, count 2 2006.257.05:54:35.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:35.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.05:54:35.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.05:54:35.77#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:35.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:35.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:35.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:35.89#ibcon#enter wrdev, iclass 5, count 0 2006.257.05:54:35.89#ibcon#first serial, iclass 5, count 0 2006.257.05:54:35.89#ibcon#enter sib2, iclass 5, count 0 2006.257.05:54:35.89#ibcon#flushed, iclass 5, count 0 2006.257.05:54:35.89#ibcon#about to write, iclass 5, count 0 2006.257.05:54:35.89#ibcon#wrote, iclass 5, count 0 2006.257.05:54:35.89#ibcon#about to read 3, iclass 5, count 0 2006.257.05:54:35.91#ibcon#read 3, iclass 5, count 0 2006.257.05:54:35.91#ibcon#about to read 4, iclass 5, count 0 2006.257.05:54:35.91#ibcon#read 4, iclass 5, count 0 2006.257.05:54:35.91#ibcon#about to read 5, iclass 5, count 0 2006.257.05:54:35.91#ibcon#read 5, iclass 5, count 0 2006.257.05:54:35.91#ibcon#about to read 6, iclass 5, count 0 2006.257.05:54:35.91#ibcon#read 6, iclass 5, count 0 2006.257.05:54:35.91#ibcon#end of sib2, iclass 5, count 0 2006.257.05:54:35.91#ibcon#*mode == 0, iclass 5, count 0 2006.257.05:54:35.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.05:54:35.91#ibcon#[27=USB\r\n] 2006.257.05:54:35.91#ibcon#*before write, iclass 5, count 0 2006.257.05:54:35.91#ibcon#enter sib2, iclass 5, count 0 2006.257.05:54:35.91#ibcon#flushed, iclass 5, count 0 2006.257.05:54:35.91#ibcon#about to write, iclass 5, count 0 2006.257.05:54:35.91#ibcon#wrote, iclass 5, count 0 2006.257.05:54:35.91#ibcon#about to read 3, iclass 5, count 0 2006.257.05:54:35.94#ibcon#read 3, iclass 5, count 0 2006.257.05:54:35.94#ibcon#about to read 4, iclass 5, count 0 2006.257.05:54:35.94#ibcon#read 4, iclass 5, count 0 2006.257.05:54:35.94#ibcon#about to read 5, iclass 5, count 0 2006.257.05:54:35.94#ibcon#read 5, iclass 5, count 0 2006.257.05:54:35.94#ibcon#about to read 6, iclass 5, count 0 2006.257.05:54:35.94#ibcon#read 6, iclass 5, count 0 2006.257.05:54:35.94#ibcon#end of sib2, iclass 5, count 0 2006.257.05:54:35.94#ibcon#*after write, iclass 5, count 0 2006.257.05:54:35.94#ibcon#*before return 0, iclass 5, count 0 2006.257.05:54:35.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:35.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.05:54:35.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.05:54:35.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.05:54:35.94$vck44/vblo=7,734.99 2006.257.05:54:35.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.05:54:35.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.05:54:35.94#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:35.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:35.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:35.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:35.94#ibcon#enter wrdev, iclass 7, count 0 2006.257.05:54:35.94#ibcon#first serial, iclass 7, count 0 2006.257.05:54:35.94#ibcon#enter sib2, iclass 7, count 0 2006.257.05:54:35.94#ibcon#flushed, iclass 7, count 0 2006.257.05:54:35.94#ibcon#about to write, iclass 7, count 0 2006.257.05:54:35.94#ibcon#wrote, iclass 7, count 0 2006.257.05:54:35.94#ibcon#about to read 3, iclass 7, count 0 2006.257.05:54:35.96#ibcon#read 3, iclass 7, count 0 2006.257.05:54:35.96#ibcon#about to read 4, iclass 7, count 0 2006.257.05:54:35.96#ibcon#read 4, iclass 7, count 0 2006.257.05:54:35.96#ibcon#about to read 5, iclass 7, count 0 2006.257.05:54:35.96#ibcon#read 5, iclass 7, count 0 2006.257.05:54:35.96#ibcon#about to read 6, iclass 7, count 0 2006.257.05:54:35.96#ibcon#read 6, iclass 7, count 0 2006.257.05:54:35.96#ibcon#end of sib2, iclass 7, count 0 2006.257.05:54:35.96#ibcon#*mode == 0, iclass 7, count 0 2006.257.05:54:35.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.05:54:35.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:54:35.96#ibcon#*before write, iclass 7, count 0 2006.257.05:54:35.96#ibcon#enter sib2, iclass 7, count 0 2006.257.05:54:35.96#ibcon#flushed, iclass 7, count 0 2006.257.05:54:35.96#ibcon#about to write, iclass 7, count 0 2006.257.05:54:35.96#ibcon#wrote, iclass 7, count 0 2006.257.05:54:35.96#ibcon#about to read 3, iclass 7, count 0 2006.257.05:54:36.00#ibcon#read 3, iclass 7, count 0 2006.257.05:54:36.00#ibcon#about to read 4, iclass 7, count 0 2006.257.05:54:36.00#ibcon#read 4, iclass 7, count 0 2006.257.05:54:36.00#ibcon#about to read 5, iclass 7, count 0 2006.257.05:54:36.00#ibcon#read 5, iclass 7, count 0 2006.257.05:54:36.00#ibcon#about to read 6, iclass 7, count 0 2006.257.05:54:36.00#ibcon#read 6, iclass 7, count 0 2006.257.05:54:36.00#ibcon#end of sib2, iclass 7, count 0 2006.257.05:54:36.00#ibcon#*after write, iclass 7, count 0 2006.257.05:54:36.00#ibcon#*before return 0, iclass 7, count 0 2006.257.05:54:36.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:36.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.05:54:36.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.05:54:36.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.05:54:36.00$vck44/vb=7,4 2006.257.05:54:36.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.05:54:36.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.05:54:36.00#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:36.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:36.06#abcon#<5=/16 1.4 4.2 20.07 891012.1\r\n> 2006.257.05:54:36.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:36.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:36.06#ibcon#enter wrdev, iclass 11, count 2 2006.257.05:54:36.06#ibcon#first serial, iclass 11, count 2 2006.257.05:54:36.06#ibcon#enter sib2, iclass 11, count 2 2006.257.05:54:36.06#ibcon#flushed, iclass 11, count 2 2006.257.05:54:36.06#ibcon#about to write, iclass 11, count 2 2006.257.05:54:36.06#ibcon#wrote, iclass 11, count 2 2006.257.05:54:36.06#ibcon#about to read 3, iclass 11, count 2 2006.257.05:54:36.08#ibcon#read 3, iclass 11, count 2 2006.257.05:54:36.08#ibcon#about to read 4, iclass 11, count 2 2006.257.05:54:36.08#ibcon#read 4, iclass 11, count 2 2006.257.05:54:36.08#ibcon#about to read 5, iclass 11, count 2 2006.257.05:54:36.08#ibcon#read 5, iclass 11, count 2 2006.257.05:54:36.08#ibcon#about to read 6, iclass 11, count 2 2006.257.05:54:36.08#ibcon#read 6, iclass 11, count 2 2006.257.05:54:36.08#ibcon#end of sib2, iclass 11, count 2 2006.257.05:54:36.08#ibcon#*mode == 0, iclass 11, count 2 2006.257.05:54:36.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.05:54:36.08#ibcon#[27=AT07-04\r\n] 2006.257.05:54:36.08#ibcon#*before write, iclass 11, count 2 2006.257.05:54:36.08#ibcon#enter sib2, iclass 11, count 2 2006.257.05:54:36.08#ibcon#flushed, iclass 11, count 2 2006.257.05:54:36.08#ibcon#about to write, iclass 11, count 2 2006.257.05:54:36.08#ibcon#wrote, iclass 11, count 2 2006.257.05:54:36.08#ibcon#about to read 3, iclass 11, count 2 2006.257.05:54:36.08#abcon#{5=INTERFACE CLEAR} 2006.257.05:54:36.11#ibcon#read 3, iclass 11, count 2 2006.257.05:54:36.11#ibcon#about to read 4, iclass 11, count 2 2006.257.05:54:36.11#ibcon#read 4, iclass 11, count 2 2006.257.05:54:36.11#ibcon#about to read 5, iclass 11, count 2 2006.257.05:54:36.11#ibcon#read 5, iclass 11, count 2 2006.257.05:54:36.11#ibcon#about to read 6, iclass 11, count 2 2006.257.05:54:36.11#ibcon#read 6, iclass 11, count 2 2006.257.05:54:36.11#ibcon#end of sib2, iclass 11, count 2 2006.257.05:54:36.11#ibcon#*after write, iclass 11, count 2 2006.257.05:54:36.11#ibcon#*before return 0, iclass 11, count 2 2006.257.05:54:36.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:36.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.05:54:36.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.05:54:36.11#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:36.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:36.14#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:54:36.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:36.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:36.23#ibcon#enter wrdev, iclass 11, count 0 2006.257.05:54:36.23#ibcon#first serial, iclass 11, count 0 2006.257.05:54:36.23#ibcon#enter sib2, iclass 11, count 0 2006.257.05:54:36.23#ibcon#flushed, iclass 11, count 0 2006.257.05:54:36.23#ibcon#about to write, iclass 11, count 0 2006.257.05:54:36.23#ibcon#wrote, iclass 11, count 0 2006.257.05:54:36.23#ibcon#about to read 3, iclass 11, count 0 2006.257.05:54:36.25#ibcon#read 3, iclass 11, count 0 2006.257.05:54:36.25#ibcon#about to read 4, iclass 11, count 0 2006.257.05:54:36.25#ibcon#read 4, iclass 11, count 0 2006.257.05:54:36.25#ibcon#about to read 5, iclass 11, count 0 2006.257.05:54:36.25#ibcon#read 5, iclass 11, count 0 2006.257.05:54:36.25#ibcon#about to read 6, iclass 11, count 0 2006.257.05:54:36.25#ibcon#read 6, iclass 11, count 0 2006.257.05:54:36.25#ibcon#end of sib2, iclass 11, count 0 2006.257.05:54:36.25#ibcon#*mode == 0, iclass 11, count 0 2006.257.05:54:36.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.05:54:36.25#ibcon#[27=USB\r\n] 2006.257.05:54:36.25#ibcon#*before write, iclass 11, count 0 2006.257.05:54:36.25#ibcon#enter sib2, iclass 11, count 0 2006.257.05:54:36.25#ibcon#flushed, iclass 11, count 0 2006.257.05:54:36.25#ibcon#about to write, iclass 11, count 0 2006.257.05:54:36.25#ibcon#wrote, iclass 11, count 0 2006.257.05:54:36.25#ibcon#about to read 3, iclass 11, count 0 2006.257.05:54:36.28#ibcon#read 3, iclass 11, count 0 2006.257.05:54:36.28#ibcon#about to read 4, iclass 11, count 0 2006.257.05:54:36.28#ibcon#read 4, iclass 11, count 0 2006.257.05:54:36.28#ibcon#about to read 5, iclass 11, count 0 2006.257.05:54:36.28#ibcon#read 5, iclass 11, count 0 2006.257.05:54:36.28#ibcon#about to read 6, iclass 11, count 0 2006.257.05:54:36.28#ibcon#read 6, iclass 11, count 0 2006.257.05:54:36.28#ibcon#end of sib2, iclass 11, count 0 2006.257.05:54:36.28#ibcon#*after write, iclass 11, count 0 2006.257.05:54:36.28#ibcon#*before return 0, iclass 11, count 0 2006.257.05:54:36.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:36.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.05:54:36.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.05:54:36.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.05:54:36.28$vck44/vblo=8,744.99 2006.257.05:54:36.28#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.05:54:36.28#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.05:54:36.28#ibcon#ireg 17 cls_cnt 0 2006.257.05:54:36.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:36.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:36.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:36.28#ibcon#enter wrdev, iclass 17, count 0 2006.257.05:54:36.28#ibcon#first serial, iclass 17, count 0 2006.257.05:54:36.28#ibcon#enter sib2, iclass 17, count 0 2006.257.05:54:36.28#ibcon#flushed, iclass 17, count 0 2006.257.05:54:36.28#ibcon#about to write, iclass 17, count 0 2006.257.05:54:36.28#ibcon#wrote, iclass 17, count 0 2006.257.05:54:36.28#ibcon#about to read 3, iclass 17, count 0 2006.257.05:54:36.30#ibcon#read 3, iclass 17, count 0 2006.257.05:54:36.30#ibcon#about to read 4, iclass 17, count 0 2006.257.05:54:36.30#ibcon#read 4, iclass 17, count 0 2006.257.05:54:36.30#ibcon#about to read 5, iclass 17, count 0 2006.257.05:54:36.30#ibcon#read 5, iclass 17, count 0 2006.257.05:54:36.30#ibcon#about to read 6, iclass 17, count 0 2006.257.05:54:36.30#ibcon#read 6, iclass 17, count 0 2006.257.05:54:36.30#ibcon#end of sib2, iclass 17, count 0 2006.257.05:54:36.30#ibcon#*mode == 0, iclass 17, count 0 2006.257.05:54:36.30#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.05:54:36.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:54:36.30#ibcon#*before write, iclass 17, count 0 2006.257.05:54:36.30#ibcon#enter sib2, iclass 17, count 0 2006.257.05:54:36.30#ibcon#flushed, iclass 17, count 0 2006.257.05:54:36.30#ibcon#about to write, iclass 17, count 0 2006.257.05:54:36.30#ibcon#wrote, iclass 17, count 0 2006.257.05:54:36.30#ibcon#about to read 3, iclass 17, count 0 2006.257.05:54:36.34#ibcon#read 3, iclass 17, count 0 2006.257.05:54:36.34#ibcon#about to read 4, iclass 17, count 0 2006.257.05:54:36.34#ibcon#read 4, iclass 17, count 0 2006.257.05:54:36.34#ibcon#about to read 5, iclass 17, count 0 2006.257.05:54:36.34#ibcon#read 5, iclass 17, count 0 2006.257.05:54:36.34#ibcon#about to read 6, iclass 17, count 0 2006.257.05:54:36.34#ibcon#read 6, iclass 17, count 0 2006.257.05:54:36.34#ibcon#end of sib2, iclass 17, count 0 2006.257.05:54:36.34#ibcon#*after write, iclass 17, count 0 2006.257.05:54:36.34#ibcon#*before return 0, iclass 17, count 0 2006.257.05:54:36.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:36.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.05:54:36.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.05:54:36.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.05:54:36.34$vck44/vb=8,4 2006.257.05:54:36.34#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.05:54:36.34#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.05:54:36.34#ibcon#ireg 11 cls_cnt 2 2006.257.05:54:36.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:36.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:36.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:36.40#ibcon#enter wrdev, iclass 19, count 2 2006.257.05:54:36.40#ibcon#first serial, iclass 19, count 2 2006.257.05:54:36.40#ibcon#enter sib2, iclass 19, count 2 2006.257.05:54:36.40#ibcon#flushed, iclass 19, count 2 2006.257.05:54:36.40#ibcon#about to write, iclass 19, count 2 2006.257.05:54:36.40#ibcon#wrote, iclass 19, count 2 2006.257.05:54:36.40#ibcon#about to read 3, iclass 19, count 2 2006.257.05:54:36.42#ibcon#read 3, iclass 19, count 2 2006.257.05:54:36.42#ibcon#about to read 4, iclass 19, count 2 2006.257.05:54:36.42#ibcon#read 4, iclass 19, count 2 2006.257.05:54:36.42#ibcon#about to read 5, iclass 19, count 2 2006.257.05:54:36.42#ibcon#read 5, iclass 19, count 2 2006.257.05:54:36.42#ibcon#about to read 6, iclass 19, count 2 2006.257.05:54:36.42#ibcon#read 6, iclass 19, count 2 2006.257.05:54:36.42#ibcon#end of sib2, iclass 19, count 2 2006.257.05:54:36.42#ibcon#*mode == 0, iclass 19, count 2 2006.257.05:54:36.42#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.05:54:36.42#ibcon#[27=AT08-04\r\n] 2006.257.05:54:36.42#ibcon#*before write, iclass 19, count 2 2006.257.05:54:36.42#ibcon#enter sib2, iclass 19, count 2 2006.257.05:54:36.42#ibcon#flushed, iclass 19, count 2 2006.257.05:54:36.42#ibcon#about to write, iclass 19, count 2 2006.257.05:54:36.42#ibcon#wrote, iclass 19, count 2 2006.257.05:54:36.42#ibcon#about to read 3, iclass 19, count 2 2006.257.05:54:36.45#ibcon#read 3, iclass 19, count 2 2006.257.05:54:36.45#ibcon#about to read 4, iclass 19, count 2 2006.257.05:54:36.45#ibcon#read 4, iclass 19, count 2 2006.257.05:54:36.45#ibcon#about to read 5, iclass 19, count 2 2006.257.05:54:36.45#ibcon#read 5, iclass 19, count 2 2006.257.05:54:36.45#ibcon#about to read 6, iclass 19, count 2 2006.257.05:54:36.45#ibcon#read 6, iclass 19, count 2 2006.257.05:54:36.45#ibcon#end of sib2, iclass 19, count 2 2006.257.05:54:36.45#ibcon#*after write, iclass 19, count 2 2006.257.05:54:36.45#ibcon#*before return 0, iclass 19, count 2 2006.257.05:54:36.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:36.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.05:54:36.45#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.05:54:36.45#ibcon#ireg 7 cls_cnt 0 2006.257.05:54:36.45#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:36.57#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:36.57#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:36.57#ibcon#enter wrdev, iclass 19, count 0 2006.257.05:54:36.57#ibcon#first serial, iclass 19, count 0 2006.257.05:54:36.57#ibcon#enter sib2, iclass 19, count 0 2006.257.05:54:36.57#ibcon#flushed, iclass 19, count 0 2006.257.05:54:36.57#ibcon#about to write, iclass 19, count 0 2006.257.05:54:36.57#ibcon#wrote, iclass 19, count 0 2006.257.05:54:36.57#ibcon#about to read 3, iclass 19, count 0 2006.257.05:54:36.59#ibcon#read 3, iclass 19, count 0 2006.257.05:54:36.59#ibcon#about to read 4, iclass 19, count 0 2006.257.05:54:36.59#ibcon#read 4, iclass 19, count 0 2006.257.05:54:36.59#ibcon#about to read 5, iclass 19, count 0 2006.257.05:54:36.59#ibcon#read 5, iclass 19, count 0 2006.257.05:54:36.59#ibcon#about to read 6, iclass 19, count 0 2006.257.05:54:36.59#ibcon#read 6, iclass 19, count 0 2006.257.05:54:36.59#ibcon#end of sib2, iclass 19, count 0 2006.257.05:54:36.59#ibcon#*mode == 0, iclass 19, count 0 2006.257.05:54:36.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.05:54:36.59#ibcon#[27=USB\r\n] 2006.257.05:54:36.59#ibcon#*before write, iclass 19, count 0 2006.257.05:54:36.59#ibcon#enter sib2, iclass 19, count 0 2006.257.05:54:36.59#ibcon#flushed, iclass 19, count 0 2006.257.05:54:36.59#ibcon#about to write, iclass 19, count 0 2006.257.05:54:36.59#ibcon#wrote, iclass 19, count 0 2006.257.05:54:36.59#ibcon#about to read 3, iclass 19, count 0 2006.257.05:54:36.62#ibcon#read 3, iclass 19, count 0 2006.257.05:54:36.62#ibcon#about to read 4, iclass 19, count 0 2006.257.05:54:36.62#ibcon#read 4, iclass 19, count 0 2006.257.05:54:36.62#ibcon#about to read 5, iclass 19, count 0 2006.257.05:54:36.62#ibcon#read 5, iclass 19, count 0 2006.257.05:54:36.62#ibcon#about to read 6, iclass 19, count 0 2006.257.05:54:36.62#ibcon#read 6, iclass 19, count 0 2006.257.05:54:36.62#ibcon#end of sib2, iclass 19, count 0 2006.257.05:54:36.62#ibcon#*after write, iclass 19, count 0 2006.257.05:54:36.62#ibcon#*before return 0, iclass 19, count 0 2006.257.05:54:36.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:36.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.05:54:36.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.05:54:36.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.05:54:36.62$vck44/vabw=wide 2006.257.05:54:36.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.05:54:36.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.05:54:36.62#ibcon#ireg 8 cls_cnt 0 2006.257.05:54:36.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:36.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:36.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:36.62#ibcon#enter wrdev, iclass 21, count 0 2006.257.05:54:36.62#ibcon#first serial, iclass 21, count 0 2006.257.05:54:36.62#ibcon#enter sib2, iclass 21, count 0 2006.257.05:54:36.62#ibcon#flushed, iclass 21, count 0 2006.257.05:54:36.62#ibcon#about to write, iclass 21, count 0 2006.257.05:54:36.62#ibcon#wrote, iclass 21, count 0 2006.257.05:54:36.62#ibcon#about to read 3, iclass 21, count 0 2006.257.05:54:36.64#ibcon#read 3, iclass 21, count 0 2006.257.05:54:36.64#ibcon#about to read 4, iclass 21, count 0 2006.257.05:54:36.64#ibcon#read 4, iclass 21, count 0 2006.257.05:54:36.64#ibcon#about to read 5, iclass 21, count 0 2006.257.05:54:36.64#ibcon#read 5, iclass 21, count 0 2006.257.05:54:36.64#ibcon#about to read 6, iclass 21, count 0 2006.257.05:54:36.64#ibcon#read 6, iclass 21, count 0 2006.257.05:54:36.64#ibcon#end of sib2, iclass 21, count 0 2006.257.05:54:36.64#ibcon#*mode == 0, iclass 21, count 0 2006.257.05:54:36.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.05:54:36.64#ibcon#[25=BW32\r\n] 2006.257.05:54:36.64#ibcon#*before write, iclass 21, count 0 2006.257.05:54:36.64#ibcon#enter sib2, iclass 21, count 0 2006.257.05:54:36.64#ibcon#flushed, iclass 21, count 0 2006.257.05:54:36.64#ibcon#about to write, iclass 21, count 0 2006.257.05:54:36.64#ibcon#wrote, iclass 21, count 0 2006.257.05:54:36.64#ibcon#about to read 3, iclass 21, count 0 2006.257.05:54:36.67#ibcon#read 3, iclass 21, count 0 2006.257.05:54:36.67#ibcon#about to read 4, iclass 21, count 0 2006.257.05:54:36.67#ibcon#read 4, iclass 21, count 0 2006.257.05:54:36.67#ibcon#about to read 5, iclass 21, count 0 2006.257.05:54:36.67#ibcon#read 5, iclass 21, count 0 2006.257.05:54:36.67#ibcon#about to read 6, iclass 21, count 0 2006.257.05:54:36.67#ibcon#read 6, iclass 21, count 0 2006.257.05:54:36.67#ibcon#end of sib2, iclass 21, count 0 2006.257.05:54:36.67#ibcon#*after write, iclass 21, count 0 2006.257.05:54:36.67#ibcon#*before return 0, iclass 21, count 0 2006.257.05:54:36.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:36.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.05:54:36.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.05:54:36.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.05:54:36.67$vck44/vbbw=wide 2006.257.05:54:36.67#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.05:54:36.67#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.05:54:36.67#ibcon#ireg 8 cls_cnt 0 2006.257.05:54:36.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:54:36.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:54:36.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:54:36.74#ibcon#enter wrdev, iclass 23, count 0 2006.257.05:54:36.74#ibcon#first serial, iclass 23, count 0 2006.257.05:54:36.74#ibcon#enter sib2, iclass 23, count 0 2006.257.05:54:36.74#ibcon#flushed, iclass 23, count 0 2006.257.05:54:36.74#ibcon#about to write, iclass 23, count 0 2006.257.05:54:36.74#ibcon#wrote, iclass 23, count 0 2006.257.05:54:36.74#ibcon#about to read 3, iclass 23, count 0 2006.257.05:54:36.76#ibcon#read 3, iclass 23, count 0 2006.257.05:54:36.76#ibcon#about to read 4, iclass 23, count 0 2006.257.05:54:36.76#ibcon#read 4, iclass 23, count 0 2006.257.05:54:36.76#ibcon#about to read 5, iclass 23, count 0 2006.257.05:54:36.76#ibcon#read 5, iclass 23, count 0 2006.257.05:54:36.76#ibcon#about to read 6, iclass 23, count 0 2006.257.05:54:36.76#ibcon#read 6, iclass 23, count 0 2006.257.05:54:36.76#ibcon#end of sib2, iclass 23, count 0 2006.257.05:54:36.76#ibcon#*mode == 0, iclass 23, count 0 2006.257.05:54:36.76#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.05:54:36.76#ibcon#[27=BW32\r\n] 2006.257.05:54:36.76#ibcon#*before write, iclass 23, count 0 2006.257.05:54:36.76#ibcon#enter sib2, iclass 23, count 0 2006.257.05:54:36.76#ibcon#flushed, iclass 23, count 0 2006.257.05:54:36.76#ibcon#about to write, iclass 23, count 0 2006.257.05:54:36.76#ibcon#wrote, iclass 23, count 0 2006.257.05:54:36.76#ibcon#about to read 3, iclass 23, count 0 2006.257.05:54:36.79#ibcon#read 3, iclass 23, count 0 2006.257.05:54:36.79#ibcon#about to read 4, iclass 23, count 0 2006.257.05:54:36.79#ibcon#read 4, iclass 23, count 0 2006.257.05:54:36.79#ibcon#about to read 5, iclass 23, count 0 2006.257.05:54:36.79#ibcon#read 5, iclass 23, count 0 2006.257.05:54:36.79#ibcon#about to read 6, iclass 23, count 0 2006.257.05:54:36.79#ibcon#read 6, iclass 23, count 0 2006.257.05:54:36.79#ibcon#end of sib2, iclass 23, count 0 2006.257.05:54:36.79#ibcon#*after write, iclass 23, count 0 2006.257.05:54:36.79#ibcon#*before return 0, iclass 23, count 0 2006.257.05:54:36.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:54:36.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.05:54:36.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.05:54:36.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.05:54:36.79$setupk4/ifdk4 2006.257.05:54:36.79$ifdk4/lo= 2006.257.05:54:36.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:54:36.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:54:36.79$ifdk4/patch= 2006.257.05:54:36.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:54:36.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:54:36.79$setupk4/!*+20s 2006.257.05:54:46.23#abcon#<5=/16 1.4 4.2 20.07 891012.1\r\n> 2006.257.05:54:46.25#abcon#{5=INTERFACE CLEAR} 2006.257.05:54:46.31#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:54:51.29$setupk4/"tpicd 2006.257.05:54:51.29$setupk4/echo=off 2006.257.05:54:51.29$setupk4/xlog=off 2006.257.05:54:51.29:!2006.257.05:58:28 2006.257.05:54:54.14#trakl#Source acquired 2006.257.05:54:56.14#flagr#flagr/antenna,acquired 2006.257.05:58:28.00:preob 2006.257.05:58:28.14/onsource/TRACKING 2006.257.05:58:28.14:!2006.257.05:58:38 2006.257.05:58:38.00:"tape 2006.257.05:58:38.00:"st=record 2006.257.05:58:38.00:data_valid=on 2006.257.05:58:38.00:midob 2006.257.05:58:38.14/onsource/TRACKING 2006.257.05:58:38.14/wx/20.13,1012.2,89 2006.257.05:58:38.36/cable/+6.4795E-03 2006.257.05:58:39.45/va/01,08,usb,yes,40,43 2006.257.05:58:39.45/va/02,07,usb,yes,43,44 2006.257.05:58:39.45/va/03,08,usb,yes,39,41 2006.257.05:58:39.45/va/04,07,usb,yes,44,47 2006.257.05:58:39.45/va/05,04,usb,yes,40,41 2006.257.05:58:39.45/va/06,04,usb,yes,44,44 2006.257.05:58:39.45/va/07,04,usb,yes,46,46 2006.257.05:58:39.45/va/08,04,usb,yes,38,46 2006.257.05:58:39.68/valo/01,524.99,yes,locked 2006.257.05:58:39.68/valo/02,534.99,yes,locked 2006.257.05:58:39.68/valo/03,564.99,yes,locked 2006.257.05:58:39.68/valo/04,624.99,yes,locked 2006.257.05:58:39.68/valo/05,734.99,yes,locked 2006.257.05:58:39.68/valo/06,814.99,yes,locked 2006.257.05:58:39.68/valo/07,864.99,yes,locked 2006.257.05:58:39.68/valo/08,884.99,yes,locked 2006.257.05:58:40.77/vb/01,04,usb,yes,34,31 2006.257.05:58:40.77/vb/02,05,usb,yes,32,32 2006.257.05:58:40.77/vb/03,04,usb,yes,33,37 2006.257.05:58:40.77/vb/04,05,usb,yes,34,32 2006.257.05:58:40.77/vb/05,04,usb,yes,30,33 2006.257.05:58:40.77/vb/06,04,usb,yes,35,31 2006.257.05:58:40.77/vb/07,04,usb,yes,35,35 2006.257.05:58:40.77/vb/08,04,usb,yes,32,36 2006.257.05:58:41.00/vblo/01,629.99,yes,locked 2006.257.05:58:41.00/vblo/02,634.99,yes,locked 2006.257.05:58:41.00/vblo/03,649.99,yes,locked 2006.257.05:58:41.00/vblo/04,679.99,yes,locked 2006.257.05:58:41.00/vblo/05,709.99,yes,locked 2006.257.05:58:41.00/vblo/06,719.99,yes,locked 2006.257.05:58:41.00/vblo/07,734.99,yes,locked 2006.257.05:58:41.00/vblo/08,744.99,yes,locked 2006.257.05:58:41.15/vabw/8 2006.257.05:58:41.30/vbbw/8 2006.257.05:58:41.39/xfe/off,on,16.7 2006.257.05:58:41.77/ifatt/23,28,28,28 2006.257.05:58:42.08/fmout-gps/S +4.51E-07 2006.257.05:58:42.12:!2006.257.05:59:18 2006.257.05:59:18.00:data_valid=off 2006.257.05:59:18.00:"et 2006.257.05:59:18.00:!+3s 2006.257.05:59:21.01:"tape 2006.257.05:59:21.01:postob 2006.257.05:59:21.11/cable/+6.4791E-03 2006.257.05:59:21.11/wx/20.13,1012.2,89 2006.257.05:59:22.07/fmout-gps/S +4.53E-07 2006.257.05:59:22.07:scan_name=257-0600,jd0609,40 2006.257.05:59:22.07:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.05:59:23.13#flagr#flagr/antenna,new-source 2006.257.05:59:23.13:checkk5 2006.257.05:59:23.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.05:59:23.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.05:59:24.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.05:59:24.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.05:59:25.11/chk_obsdata//k5ts1/T2570558??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:59:25.51/chk_obsdata//k5ts2/T2570558??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:59:25.92/chk_obsdata//k5ts3/T2570558??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:59:26.33/chk_obsdata//k5ts4/T2570558??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.05:59:27.05/k5log//k5ts1_log_newline 2006.257.05:59:27.79/k5log//k5ts2_log_newline 2006.257.05:59:28.51/k5log//k5ts3_log_newline 2006.257.05:59:29.23/k5log//k5ts4_log_newline 2006.257.05:59:29.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.05:59:29.25:setupk4=1 2006.257.05:59:29.25$setupk4/echo=on 2006.257.05:59:29.25$setupk4/pcalon 2006.257.05:59:29.25$pcalon/"no phase cal control is implemented here 2006.257.05:59:29.25$setupk4/"tpicd=stop 2006.257.05:59:29.26$setupk4/"rec=synch_on 2006.257.05:59:29.26$setupk4/"rec_mode=128 2006.257.05:59:29.26$setupk4/!* 2006.257.05:59:29.26$setupk4/recpk4 2006.257.05:59:29.26$recpk4/recpatch= 2006.257.05:59:29.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.05:59:29.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.05:59:29.26$setupk4/vck44 2006.257.05:59:29.26$vck44/valo=1,524.99 2006.257.05:59:29.26#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.05:59:29.26#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.05:59:29.26#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:29.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:29.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:29.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:29.26#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:59:29.26#ibcon#first serial, iclass 32, count 0 2006.257.05:59:29.26#ibcon#enter sib2, iclass 32, count 0 2006.257.05:59:29.26#ibcon#flushed, iclass 32, count 0 2006.257.05:59:29.26#ibcon#about to write, iclass 32, count 0 2006.257.05:59:29.26#ibcon#wrote, iclass 32, count 0 2006.257.05:59:29.26#ibcon#about to read 3, iclass 32, count 0 2006.257.05:59:29.28#ibcon#read 3, iclass 32, count 0 2006.257.05:59:29.28#ibcon#about to read 4, iclass 32, count 0 2006.257.05:59:29.28#ibcon#read 4, iclass 32, count 0 2006.257.05:59:29.28#ibcon#about to read 5, iclass 32, count 0 2006.257.05:59:29.28#ibcon#read 5, iclass 32, count 0 2006.257.05:59:29.28#ibcon#about to read 6, iclass 32, count 0 2006.257.05:59:29.28#ibcon#read 6, iclass 32, count 0 2006.257.05:59:29.28#ibcon#end of sib2, iclass 32, count 0 2006.257.05:59:29.28#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:59:29.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:59:29.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.05:59:29.28#ibcon#*before write, iclass 32, count 0 2006.257.05:59:29.28#ibcon#enter sib2, iclass 32, count 0 2006.257.05:59:29.28#ibcon#flushed, iclass 32, count 0 2006.257.05:59:29.28#ibcon#about to write, iclass 32, count 0 2006.257.05:59:29.28#ibcon#wrote, iclass 32, count 0 2006.257.05:59:29.28#ibcon#about to read 3, iclass 32, count 0 2006.257.05:59:29.33#ibcon#read 3, iclass 32, count 0 2006.257.05:59:29.33#ibcon#about to read 4, iclass 32, count 0 2006.257.05:59:29.33#ibcon#read 4, iclass 32, count 0 2006.257.05:59:29.33#ibcon#about to read 5, iclass 32, count 0 2006.257.05:59:29.33#ibcon#read 5, iclass 32, count 0 2006.257.05:59:29.33#ibcon#about to read 6, iclass 32, count 0 2006.257.05:59:29.33#ibcon#read 6, iclass 32, count 0 2006.257.05:59:29.33#ibcon#end of sib2, iclass 32, count 0 2006.257.05:59:29.33#ibcon#*after write, iclass 32, count 0 2006.257.05:59:29.33#ibcon#*before return 0, iclass 32, count 0 2006.257.05:59:29.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:29.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:29.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:59:29.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:59:29.33$vck44/va=1,8 2006.257.05:59:29.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.05:59:29.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.05:59:29.33#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:29.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:29.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:29.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:29.33#ibcon#enter wrdev, iclass 34, count 2 2006.257.05:59:29.33#ibcon#first serial, iclass 34, count 2 2006.257.05:59:29.33#ibcon#enter sib2, iclass 34, count 2 2006.257.05:59:29.33#ibcon#flushed, iclass 34, count 2 2006.257.05:59:29.33#ibcon#about to write, iclass 34, count 2 2006.257.05:59:29.33#ibcon#wrote, iclass 34, count 2 2006.257.05:59:29.33#ibcon#about to read 3, iclass 34, count 2 2006.257.05:59:29.35#ibcon#read 3, iclass 34, count 2 2006.257.05:59:29.35#ibcon#about to read 4, iclass 34, count 2 2006.257.05:59:29.35#ibcon#read 4, iclass 34, count 2 2006.257.05:59:29.35#ibcon#about to read 5, iclass 34, count 2 2006.257.05:59:29.35#ibcon#read 5, iclass 34, count 2 2006.257.05:59:29.35#ibcon#about to read 6, iclass 34, count 2 2006.257.05:59:29.35#ibcon#read 6, iclass 34, count 2 2006.257.05:59:29.35#ibcon#end of sib2, iclass 34, count 2 2006.257.05:59:29.35#ibcon#*mode == 0, iclass 34, count 2 2006.257.05:59:29.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.05:59:29.35#ibcon#[25=AT01-08\r\n] 2006.257.05:59:29.35#ibcon#*before write, iclass 34, count 2 2006.257.05:59:29.35#ibcon#enter sib2, iclass 34, count 2 2006.257.05:59:29.35#ibcon#flushed, iclass 34, count 2 2006.257.05:59:29.35#ibcon#about to write, iclass 34, count 2 2006.257.05:59:29.35#ibcon#wrote, iclass 34, count 2 2006.257.05:59:29.35#ibcon#about to read 3, iclass 34, count 2 2006.257.05:59:29.38#ibcon#read 3, iclass 34, count 2 2006.257.05:59:29.38#ibcon#about to read 4, iclass 34, count 2 2006.257.05:59:29.38#ibcon#read 4, iclass 34, count 2 2006.257.05:59:29.38#ibcon#about to read 5, iclass 34, count 2 2006.257.05:59:29.38#ibcon#read 5, iclass 34, count 2 2006.257.05:59:29.38#ibcon#about to read 6, iclass 34, count 2 2006.257.05:59:29.38#ibcon#read 6, iclass 34, count 2 2006.257.05:59:29.38#ibcon#end of sib2, iclass 34, count 2 2006.257.05:59:29.38#ibcon#*after write, iclass 34, count 2 2006.257.05:59:29.38#ibcon#*before return 0, iclass 34, count 2 2006.257.05:59:29.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:29.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:29.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.05:59:29.38#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:29.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:29.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:29.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:29.50#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:59:29.50#ibcon#first serial, iclass 34, count 0 2006.257.05:59:29.50#ibcon#enter sib2, iclass 34, count 0 2006.257.05:59:29.50#ibcon#flushed, iclass 34, count 0 2006.257.05:59:29.50#ibcon#about to write, iclass 34, count 0 2006.257.05:59:29.50#ibcon#wrote, iclass 34, count 0 2006.257.05:59:29.50#ibcon#about to read 3, iclass 34, count 0 2006.257.05:59:29.52#ibcon#read 3, iclass 34, count 0 2006.257.05:59:29.52#ibcon#about to read 4, iclass 34, count 0 2006.257.05:59:29.52#ibcon#read 4, iclass 34, count 0 2006.257.05:59:29.52#ibcon#about to read 5, iclass 34, count 0 2006.257.05:59:29.52#ibcon#read 5, iclass 34, count 0 2006.257.05:59:29.52#ibcon#about to read 6, iclass 34, count 0 2006.257.05:59:29.52#ibcon#read 6, iclass 34, count 0 2006.257.05:59:29.52#ibcon#end of sib2, iclass 34, count 0 2006.257.05:59:29.52#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:59:29.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:59:29.52#ibcon#[25=USB\r\n] 2006.257.05:59:29.52#ibcon#*before write, iclass 34, count 0 2006.257.05:59:29.52#ibcon#enter sib2, iclass 34, count 0 2006.257.05:59:29.52#ibcon#flushed, iclass 34, count 0 2006.257.05:59:29.52#ibcon#about to write, iclass 34, count 0 2006.257.05:59:29.52#ibcon#wrote, iclass 34, count 0 2006.257.05:59:29.52#ibcon#about to read 3, iclass 34, count 0 2006.257.05:59:29.55#ibcon#read 3, iclass 34, count 0 2006.257.05:59:29.55#ibcon#about to read 4, iclass 34, count 0 2006.257.05:59:29.55#ibcon#read 4, iclass 34, count 0 2006.257.05:59:29.55#ibcon#about to read 5, iclass 34, count 0 2006.257.05:59:29.55#ibcon#read 5, iclass 34, count 0 2006.257.05:59:29.55#ibcon#about to read 6, iclass 34, count 0 2006.257.05:59:29.55#ibcon#read 6, iclass 34, count 0 2006.257.05:59:29.55#ibcon#end of sib2, iclass 34, count 0 2006.257.05:59:29.55#ibcon#*after write, iclass 34, count 0 2006.257.05:59:29.55#ibcon#*before return 0, iclass 34, count 0 2006.257.05:59:29.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:29.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:29.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:59:29.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:59:29.55$vck44/valo=2,534.99 2006.257.05:59:29.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.05:59:29.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.05:59:29.55#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:29.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:29.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:29.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:29.55#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:59:29.55#ibcon#first serial, iclass 36, count 0 2006.257.05:59:29.55#ibcon#enter sib2, iclass 36, count 0 2006.257.05:59:29.55#ibcon#flushed, iclass 36, count 0 2006.257.05:59:29.55#ibcon#about to write, iclass 36, count 0 2006.257.05:59:29.55#ibcon#wrote, iclass 36, count 0 2006.257.05:59:29.55#ibcon#about to read 3, iclass 36, count 0 2006.257.05:59:29.57#ibcon#read 3, iclass 36, count 0 2006.257.05:59:29.57#ibcon#about to read 4, iclass 36, count 0 2006.257.05:59:29.57#ibcon#read 4, iclass 36, count 0 2006.257.05:59:29.57#ibcon#about to read 5, iclass 36, count 0 2006.257.05:59:29.57#ibcon#read 5, iclass 36, count 0 2006.257.05:59:29.57#ibcon#about to read 6, iclass 36, count 0 2006.257.05:59:29.57#ibcon#read 6, iclass 36, count 0 2006.257.05:59:29.57#ibcon#end of sib2, iclass 36, count 0 2006.257.05:59:29.57#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:59:29.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:59:29.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.05:59:29.57#ibcon#*before write, iclass 36, count 0 2006.257.05:59:29.57#ibcon#enter sib2, iclass 36, count 0 2006.257.05:59:29.57#ibcon#flushed, iclass 36, count 0 2006.257.05:59:29.57#ibcon#about to write, iclass 36, count 0 2006.257.05:59:29.57#ibcon#wrote, iclass 36, count 0 2006.257.05:59:29.57#ibcon#about to read 3, iclass 36, count 0 2006.257.05:59:29.61#ibcon#read 3, iclass 36, count 0 2006.257.05:59:29.61#ibcon#about to read 4, iclass 36, count 0 2006.257.05:59:29.61#ibcon#read 4, iclass 36, count 0 2006.257.05:59:29.61#ibcon#about to read 5, iclass 36, count 0 2006.257.05:59:29.61#ibcon#read 5, iclass 36, count 0 2006.257.05:59:29.61#ibcon#about to read 6, iclass 36, count 0 2006.257.05:59:29.61#ibcon#read 6, iclass 36, count 0 2006.257.05:59:29.61#ibcon#end of sib2, iclass 36, count 0 2006.257.05:59:29.61#ibcon#*after write, iclass 36, count 0 2006.257.05:59:29.61#ibcon#*before return 0, iclass 36, count 0 2006.257.05:59:29.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:29.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:29.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:59:29.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:59:29.61$vck44/va=2,7 2006.257.05:59:29.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.05:59:29.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.05:59:29.61#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:29.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:29.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:29.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:29.67#ibcon#enter wrdev, iclass 38, count 2 2006.257.05:59:29.67#ibcon#first serial, iclass 38, count 2 2006.257.05:59:29.67#ibcon#enter sib2, iclass 38, count 2 2006.257.05:59:29.67#ibcon#flushed, iclass 38, count 2 2006.257.05:59:29.67#ibcon#about to write, iclass 38, count 2 2006.257.05:59:29.67#ibcon#wrote, iclass 38, count 2 2006.257.05:59:29.67#ibcon#about to read 3, iclass 38, count 2 2006.257.05:59:29.69#ibcon#read 3, iclass 38, count 2 2006.257.05:59:29.69#ibcon#about to read 4, iclass 38, count 2 2006.257.05:59:29.69#ibcon#read 4, iclass 38, count 2 2006.257.05:59:29.69#ibcon#about to read 5, iclass 38, count 2 2006.257.05:59:29.69#ibcon#read 5, iclass 38, count 2 2006.257.05:59:29.69#ibcon#about to read 6, iclass 38, count 2 2006.257.05:59:29.69#ibcon#read 6, iclass 38, count 2 2006.257.05:59:29.69#ibcon#end of sib2, iclass 38, count 2 2006.257.05:59:29.69#ibcon#*mode == 0, iclass 38, count 2 2006.257.05:59:29.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.05:59:29.69#ibcon#[25=AT02-07\r\n] 2006.257.05:59:29.69#ibcon#*before write, iclass 38, count 2 2006.257.05:59:29.69#ibcon#enter sib2, iclass 38, count 2 2006.257.05:59:29.69#ibcon#flushed, iclass 38, count 2 2006.257.05:59:29.69#ibcon#about to write, iclass 38, count 2 2006.257.05:59:29.69#ibcon#wrote, iclass 38, count 2 2006.257.05:59:29.69#ibcon#about to read 3, iclass 38, count 2 2006.257.05:59:29.72#ibcon#read 3, iclass 38, count 2 2006.257.05:59:29.72#ibcon#about to read 4, iclass 38, count 2 2006.257.05:59:29.72#ibcon#read 4, iclass 38, count 2 2006.257.05:59:29.72#ibcon#about to read 5, iclass 38, count 2 2006.257.05:59:29.72#ibcon#read 5, iclass 38, count 2 2006.257.05:59:29.72#ibcon#about to read 6, iclass 38, count 2 2006.257.05:59:29.72#ibcon#read 6, iclass 38, count 2 2006.257.05:59:29.72#ibcon#end of sib2, iclass 38, count 2 2006.257.05:59:29.72#ibcon#*after write, iclass 38, count 2 2006.257.05:59:29.72#ibcon#*before return 0, iclass 38, count 2 2006.257.05:59:29.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:29.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:29.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.05:59:29.72#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:29.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:29.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:29.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:29.84#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:59:29.84#ibcon#first serial, iclass 38, count 0 2006.257.05:59:29.84#ibcon#enter sib2, iclass 38, count 0 2006.257.05:59:29.84#ibcon#flushed, iclass 38, count 0 2006.257.05:59:29.84#ibcon#about to write, iclass 38, count 0 2006.257.05:59:29.84#ibcon#wrote, iclass 38, count 0 2006.257.05:59:29.84#ibcon#about to read 3, iclass 38, count 0 2006.257.05:59:29.86#ibcon#read 3, iclass 38, count 0 2006.257.05:59:29.86#ibcon#about to read 4, iclass 38, count 0 2006.257.05:59:29.86#ibcon#read 4, iclass 38, count 0 2006.257.05:59:29.86#ibcon#about to read 5, iclass 38, count 0 2006.257.05:59:29.86#ibcon#read 5, iclass 38, count 0 2006.257.05:59:29.86#ibcon#about to read 6, iclass 38, count 0 2006.257.05:59:29.86#ibcon#read 6, iclass 38, count 0 2006.257.05:59:29.86#ibcon#end of sib2, iclass 38, count 0 2006.257.05:59:29.86#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:59:29.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:59:29.86#ibcon#[25=USB\r\n] 2006.257.05:59:29.86#ibcon#*before write, iclass 38, count 0 2006.257.05:59:29.86#ibcon#enter sib2, iclass 38, count 0 2006.257.05:59:29.86#ibcon#flushed, iclass 38, count 0 2006.257.05:59:29.86#ibcon#about to write, iclass 38, count 0 2006.257.05:59:29.86#ibcon#wrote, iclass 38, count 0 2006.257.05:59:29.86#ibcon#about to read 3, iclass 38, count 0 2006.257.05:59:29.89#ibcon#read 3, iclass 38, count 0 2006.257.05:59:29.89#ibcon#about to read 4, iclass 38, count 0 2006.257.05:59:29.89#ibcon#read 4, iclass 38, count 0 2006.257.05:59:29.89#ibcon#about to read 5, iclass 38, count 0 2006.257.05:59:29.89#ibcon#read 5, iclass 38, count 0 2006.257.05:59:29.89#ibcon#about to read 6, iclass 38, count 0 2006.257.05:59:29.89#ibcon#read 6, iclass 38, count 0 2006.257.05:59:29.89#ibcon#end of sib2, iclass 38, count 0 2006.257.05:59:29.89#ibcon#*after write, iclass 38, count 0 2006.257.05:59:29.89#ibcon#*before return 0, iclass 38, count 0 2006.257.05:59:29.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:29.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:29.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:59:29.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:59:29.89$vck44/valo=3,564.99 2006.257.05:59:29.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.05:59:29.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.05:59:29.89#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:29.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:29.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:29.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:29.89#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:59:29.89#ibcon#first serial, iclass 40, count 0 2006.257.05:59:29.89#ibcon#enter sib2, iclass 40, count 0 2006.257.05:59:29.89#ibcon#flushed, iclass 40, count 0 2006.257.05:59:29.89#ibcon#about to write, iclass 40, count 0 2006.257.05:59:29.89#ibcon#wrote, iclass 40, count 0 2006.257.05:59:29.89#ibcon#about to read 3, iclass 40, count 0 2006.257.05:59:29.91#ibcon#read 3, iclass 40, count 0 2006.257.05:59:29.91#ibcon#about to read 4, iclass 40, count 0 2006.257.05:59:29.91#ibcon#read 4, iclass 40, count 0 2006.257.05:59:29.91#ibcon#about to read 5, iclass 40, count 0 2006.257.05:59:29.91#ibcon#read 5, iclass 40, count 0 2006.257.05:59:29.91#ibcon#about to read 6, iclass 40, count 0 2006.257.05:59:29.91#ibcon#read 6, iclass 40, count 0 2006.257.05:59:29.91#ibcon#end of sib2, iclass 40, count 0 2006.257.05:59:29.91#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:59:29.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:59:29.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.05:59:29.91#ibcon#*before write, iclass 40, count 0 2006.257.05:59:29.91#ibcon#enter sib2, iclass 40, count 0 2006.257.05:59:29.91#ibcon#flushed, iclass 40, count 0 2006.257.05:59:29.91#ibcon#about to write, iclass 40, count 0 2006.257.05:59:29.91#ibcon#wrote, iclass 40, count 0 2006.257.05:59:29.91#ibcon#about to read 3, iclass 40, count 0 2006.257.05:59:29.95#ibcon#read 3, iclass 40, count 0 2006.257.05:59:29.95#ibcon#about to read 4, iclass 40, count 0 2006.257.05:59:29.95#ibcon#read 4, iclass 40, count 0 2006.257.05:59:29.95#ibcon#about to read 5, iclass 40, count 0 2006.257.05:59:29.95#ibcon#read 5, iclass 40, count 0 2006.257.05:59:29.95#ibcon#about to read 6, iclass 40, count 0 2006.257.05:59:29.95#ibcon#read 6, iclass 40, count 0 2006.257.05:59:29.95#ibcon#end of sib2, iclass 40, count 0 2006.257.05:59:29.95#ibcon#*after write, iclass 40, count 0 2006.257.05:59:29.95#ibcon#*before return 0, iclass 40, count 0 2006.257.05:59:29.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:29.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:29.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:59:29.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:59:29.95$vck44/va=3,8 2006.257.05:59:29.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.05:59:29.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.05:59:29.95#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:29.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:30.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:30.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:30.01#ibcon#enter wrdev, iclass 4, count 2 2006.257.05:59:30.01#ibcon#first serial, iclass 4, count 2 2006.257.05:59:30.01#ibcon#enter sib2, iclass 4, count 2 2006.257.05:59:30.01#ibcon#flushed, iclass 4, count 2 2006.257.05:59:30.01#ibcon#about to write, iclass 4, count 2 2006.257.05:59:30.01#ibcon#wrote, iclass 4, count 2 2006.257.05:59:30.01#ibcon#about to read 3, iclass 4, count 2 2006.257.05:59:30.03#ibcon#read 3, iclass 4, count 2 2006.257.05:59:30.03#ibcon#about to read 4, iclass 4, count 2 2006.257.05:59:30.03#ibcon#read 4, iclass 4, count 2 2006.257.05:59:30.03#ibcon#about to read 5, iclass 4, count 2 2006.257.05:59:30.03#ibcon#read 5, iclass 4, count 2 2006.257.05:59:30.03#ibcon#about to read 6, iclass 4, count 2 2006.257.05:59:30.03#ibcon#read 6, iclass 4, count 2 2006.257.05:59:30.03#ibcon#end of sib2, iclass 4, count 2 2006.257.05:59:30.03#ibcon#*mode == 0, iclass 4, count 2 2006.257.05:59:30.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.05:59:30.03#ibcon#[25=AT03-08\r\n] 2006.257.05:59:30.03#ibcon#*before write, iclass 4, count 2 2006.257.05:59:30.03#ibcon#enter sib2, iclass 4, count 2 2006.257.05:59:30.03#ibcon#flushed, iclass 4, count 2 2006.257.05:59:30.03#ibcon#about to write, iclass 4, count 2 2006.257.05:59:30.03#ibcon#wrote, iclass 4, count 2 2006.257.05:59:30.03#ibcon#about to read 3, iclass 4, count 2 2006.257.05:59:30.06#ibcon#read 3, iclass 4, count 2 2006.257.05:59:30.06#ibcon#about to read 4, iclass 4, count 2 2006.257.05:59:30.06#ibcon#read 4, iclass 4, count 2 2006.257.05:59:30.06#ibcon#about to read 5, iclass 4, count 2 2006.257.05:59:30.06#ibcon#read 5, iclass 4, count 2 2006.257.05:59:30.06#ibcon#about to read 6, iclass 4, count 2 2006.257.05:59:30.06#ibcon#read 6, iclass 4, count 2 2006.257.05:59:30.06#ibcon#end of sib2, iclass 4, count 2 2006.257.05:59:30.06#ibcon#*after write, iclass 4, count 2 2006.257.05:59:30.06#ibcon#*before return 0, iclass 4, count 2 2006.257.05:59:30.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:30.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:30.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.05:59:30.06#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:30.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:30.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:30.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:30.18#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:59:30.18#ibcon#first serial, iclass 4, count 0 2006.257.05:59:30.18#ibcon#enter sib2, iclass 4, count 0 2006.257.05:59:30.18#ibcon#flushed, iclass 4, count 0 2006.257.05:59:30.18#ibcon#about to write, iclass 4, count 0 2006.257.05:59:30.18#ibcon#wrote, iclass 4, count 0 2006.257.05:59:30.18#ibcon#about to read 3, iclass 4, count 0 2006.257.05:59:30.20#ibcon#read 3, iclass 4, count 0 2006.257.05:59:30.20#ibcon#about to read 4, iclass 4, count 0 2006.257.05:59:30.20#ibcon#read 4, iclass 4, count 0 2006.257.05:59:30.20#ibcon#about to read 5, iclass 4, count 0 2006.257.05:59:30.20#ibcon#read 5, iclass 4, count 0 2006.257.05:59:30.20#ibcon#about to read 6, iclass 4, count 0 2006.257.05:59:30.20#ibcon#read 6, iclass 4, count 0 2006.257.05:59:30.20#ibcon#end of sib2, iclass 4, count 0 2006.257.05:59:30.20#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:59:30.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:59:30.20#ibcon#[25=USB\r\n] 2006.257.05:59:30.20#ibcon#*before write, iclass 4, count 0 2006.257.05:59:30.20#ibcon#enter sib2, iclass 4, count 0 2006.257.05:59:30.20#ibcon#flushed, iclass 4, count 0 2006.257.05:59:30.20#ibcon#about to write, iclass 4, count 0 2006.257.05:59:30.20#ibcon#wrote, iclass 4, count 0 2006.257.05:59:30.20#ibcon#about to read 3, iclass 4, count 0 2006.257.05:59:30.23#ibcon#read 3, iclass 4, count 0 2006.257.05:59:30.23#ibcon#about to read 4, iclass 4, count 0 2006.257.05:59:30.23#ibcon#read 4, iclass 4, count 0 2006.257.05:59:30.23#ibcon#about to read 5, iclass 4, count 0 2006.257.05:59:30.23#ibcon#read 5, iclass 4, count 0 2006.257.05:59:30.23#ibcon#about to read 6, iclass 4, count 0 2006.257.05:59:30.23#ibcon#read 6, iclass 4, count 0 2006.257.05:59:30.23#ibcon#end of sib2, iclass 4, count 0 2006.257.05:59:30.23#ibcon#*after write, iclass 4, count 0 2006.257.05:59:30.23#ibcon#*before return 0, iclass 4, count 0 2006.257.05:59:30.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:30.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:30.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:59:30.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:59:30.23$vck44/valo=4,624.99 2006.257.05:59:30.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.05:59:30.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.05:59:30.23#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:30.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:30.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:30.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:30.23#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:59:30.23#ibcon#first serial, iclass 6, count 0 2006.257.05:59:30.23#ibcon#enter sib2, iclass 6, count 0 2006.257.05:59:30.23#ibcon#flushed, iclass 6, count 0 2006.257.05:59:30.23#ibcon#about to write, iclass 6, count 0 2006.257.05:59:30.23#ibcon#wrote, iclass 6, count 0 2006.257.05:59:30.23#ibcon#about to read 3, iclass 6, count 0 2006.257.05:59:30.25#ibcon#read 3, iclass 6, count 0 2006.257.05:59:30.25#ibcon#about to read 4, iclass 6, count 0 2006.257.05:59:30.25#ibcon#read 4, iclass 6, count 0 2006.257.05:59:30.25#ibcon#about to read 5, iclass 6, count 0 2006.257.05:59:30.25#ibcon#read 5, iclass 6, count 0 2006.257.05:59:30.25#ibcon#about to read 6, iclass 6, count 0 2006.257.05:59:30.25#ibcon#read 6, iclass 6, count 0 2006.257.05:59:30.25#ibcon#end of sib2, iclass 6, count 0 2006.257.05:59:30.25#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:59:30.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:59:30.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.05:59:30.25#ibcon#*before write, iclass 6, count 0 2006.257.05:59:30.25#ibcon#enter sib2, iclass 6, count 0 2006.257.05:59:30.25#ibcon#flushed, iclass 6, count 0 2006.257.05:59:30.25#ibcon#about to write, iclass 6, count 0 2006.257.05:59:30.25#ibcon#wrote, iclass 6, count 0 2006.257.05:59:30.25#ibcon#about to read 3, iclass 6, count 0 2006.257.05:59:30.29#ibcon#read 3, iclass 6, count 0 2006.257.05:59:30.29#ibcon#about to read 4, iclass 6, count 0 2006.257.05:59:30.29#ibcon#read 4, iclass 6, count 0 2006.257.05:59:30.29#ibcon#about to read 5, iclass 6, count 0 2006.257.05:59:30.29#ibcon#read 5, iclass 6, count 0 2006.257.05:59:30.29#ibcon#about to read 6, iclass 6, count 0 2006.257.05:59:30.29#ibcon#read 6, iclass 6, count 0 2006.257.05:59:30.29#ibcon#end of sib2, iclass 6, count 0 2006.257.05:59:30.29#ibcon#*after write, iclass 6, count 0 2006.257.05:59:30.29#ibcon#*before return 0, iclass 6, count 0 2006.257.05:59:30.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:30.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:30.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:59:30.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:59:30.29$vck44/va=4,7 2006.257.05:59:30.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.05:59:30.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.05:59:30.29#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:30.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:30.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:30.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:30.35#ibcon#enter wrdev, iclass 10, count 2 2006.257.05:59:30.35#ibcon#first serial, iclass 10, count 2 2006.257.05:59:30.35#ibcon#enter sib2, iclass 10, count 2 2006.257.05:59:30.35#ibcon#flushed, iclass 10, count 2 2006.257.05:59:30.35#ibcon#about to write, iclass 10, count 2 2006.257.05:59:30.35#ibcon#wrote, iclass 10, count 2 2006.257.05:59:30.35#ibcon#about to read 3, iclass 10, count 2 2006.257.05:59:30.37#ibcon#read 3, iclass 10, count 2 2006.257.05:59:30.37#ibcon#about to read 4, iclass 10, count 2 2006.257.05:59:30.37#ibcon#read 4, iclass 10, count 2 2006.257.05:59:30.37#ibcon#about to read 5, iclass 10, count 2 2006.257.05:59:30.37#ibcon#read 5, iclass 10, count 2 2006.257.05:59:30.37#ibcon#about to read 6, iclass 10, count 2 2006.257.05:59:30.37#ibcon#read 6, iclass 10, count 2 2006.257.05:59:30.37#ibcon#end of sib2, iclass 10, count 2 2006.257.05:59:30.37#ibcon#*mode == 0, iclass 10, count 2 2006.257.05:59:30.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.05:59:30.37#ibcon#[25=AT04-07\r\n] 2006.257.05:59:30.37#ibcon#*before write, iclass 10, count 2 2006.257.05:59:30.37#ibcon#enter sib2, iclass 10, count 2 2006.257.05:59:30.37#ibcon#flushed, iclass 10, count 2 2006.257.05:59:30.37#ibcon#about to write, iclass 10, count 2 2006.257.05:59:30.37#ibcon#wrote, iclass 10, count 2 2006.257.05:59:30.37#ibcon#about to read 3, iclass 10, count 2 2006.257.05:59:30.40#ibcon#read 3, iclass 10, count 2 2006.257.05:59:30.40#ibcon#about to read 4, iclass 10, count 2 2006.257.05:59:30.40#ibcon#read 4, iclass 10, count 2 2006.257.05:59:30.40#ibcon#about to read 5, iclass 10, count 2 2006.257.05:59:30.40#ibcon#read 5, iclass 10, count 2 2006.257.05:59:30.40#ibcon#about to read 6, iclass 10, count 2 2006.257.05:59:30.40#ibcon#read 6, iclass 10, count 2 2006.257.05:59:30.40#ibcon#end of sib2, iclass 10, count 2 2006.257.05:59:30.40#ibcon#*after write, iclass 10, count 2 2006.257.05:59:30.40#ibcon#*before return 0, iclass 10, count 2 2006.257.05:59:30.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:30.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:30.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.05:59:30.40#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:30.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:30.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:30.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:30.52#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:59:30.52#ibcon#first serial, iclass 10, count 0 2006.257.05:59:30.52#ibcon#enter sib2, iclass 10, count 0 2006.257.05:59:30.52#ibcon#flushed, iclass 10, count 0 2006.257.05:59:30.52#ibcon#about to write, iclass 10, count 0 2006.257.05:59:30.52#ibcon#wrote, iclass 10, count 0 2006.257.05:59:30.52#ibcon#about to read 3, iclass 10, count 0 2006.257.05:59:30.54#ibcon#read 3, iclass 10, count 0 2006.257.05:59:30.54#ibcon#about to read 4, iclass 10, count 0 2006.257.05:59:30.54#ibcon#read 4, iclass 10, count 0 2006.257.05:59:30.54#ibcon#about to read 5, iclass 10, count 0 2006.257.05:59:30.54#ibcon#read 5, iclass 10, count 0 2006.257.05:59:30.54#ibcon#about to read 6, iclass 10, count 0 2006.257.05:59:30.54#ibcon#read 6, iclass 10, count 0 2006.257.05:59:30.54#ibcon#end of sib2, iclass 10, count 0 2006.257.05:59:30.54#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:59:30.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:59:30.54#ibcon#[25=USB\r\n] 2006.257.05:59:30.54#ibcon#*before write, iclass 10, count 0 2006.257.05:59:30.54#ibcon#enter sib2, iclass 10, count 0 2006.257.05:59:30.54#ibcon#flushed, iclass 10, count 0 2006.257.05:59:30.54#ibcon#about to write, iclass 10, count 0 2006.257.05:59:30.54#ibcon#wrote, iclass 10, count 0 2006.257.05:59:30.54#ibcon#about to read 3, iclass 10, count 0 2006.257.05:59:30.57#ibcon#read 3, iclass 10, count 0 2006.257.05:59:30.57#ibcon#about to read 4, iclass 10, count 0 2006.257.05:59:30.57#ibcon#read 4, iclass 10, count 0 2006.257.05:59:30.57#ibcon#about to read 5, iclass 10, count 0 2006.257.05:59:30.57#ibcon#read 5, iclass 10, count 0 2006.257.05:59:30.57#ibcon#about to read 6, iclass 10, count 0 2006.257.05:59:30.57#ibcon#read 6, iclass 10, count 0 2006.257.05:59:30.57#ibcon#end of sib2, iclass 10, count 0 2006.257.05:59:30.57#ibcon#*after write, iclass 10, count 0 2006.257.05:59:30.57#ibcon#*before return 0, iclass 10, count 0 2006.257.05:59:30.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:30.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:30.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:59:30.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:59:30.57$vck44/valo=5,734.99 2006.257.05:59:30.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.05:59:30.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.05:59:30.57#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:30.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:30.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:30.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:30.57#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:59:30.57#ibcon#first serial, iclass 12, count 0 2006.257.05:59:30.57#ibcon#enter sib2, iclass 12, count 0 2006.257.05:59:30.57#ibcon#flushed, iclass 12, count 0 2006.257.05:59:30.57#ibcon#about to write, iclass 12, count 0 2006.257.05:59:30.57#ibcon#wrote, iclass 12, count 0 2006.257.05:59:30.57#ibcon#about to read 3, iclass 12, count 0 2006.257.05:59:30.59#ibcon#read 3, iclass 12, count 0 2006.257.05:59:30.59#ibcon#about to read 4, iclass 12, count 0 2006.257.05:59:30.59#ibcon#read 4, iclass 12, count 0 2006.257.05:59:30.59#ibcon#about to read 5, iclass 12, count 0 2006.257.05:59:30.59#ibcon#read 5, iclass 12, count 0 2006.257.05:59:30.59#ibcon#about to read 6, iclass 12, count 0 2006.257.05:59:30.59#ibcon#read 6, iclass 12, count 0 2006.257.05:59:30.59#ibcon#end of sib2, iclass 12, count 0 2006.257.05:59:30.59#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:59:30.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:59:30.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.05:59:30.59#ibcon#*before write, iclass 12, count 0 2006.257.05:59:30.59#ibcon#enter sib2, iclass 12, count 0 2006.257.05:59:30.59#ibcon#flushed, iclass 12, count 0 2006.257.05:59:30.59#ibcon#about to write, iclass 12, count 0 2006.257.05:59:30.59#ibcon#wrote, iclass 12, count 0 2006.257.05:59:30.59#ibcon#about to read 3, iclass 12, count 0 2006.257.05:59:30.63#ibcon#read 3, iclass 12, count 0 2006.257.05:59:30.63#ibcon#about to read 4, iclass 12, count 0 2006.257.05:59:30.63#ibcon#read 4, iclass 12, count 0 2006.257.05:59:30.63#ibcon#about to read 5, iclass 12, count 0 2006.257.05:59:30.63#ibcon#read 5, iclass 12, count 0 2006.257.05:59:30.63#ibcon#about to read 6, iclass 12, count 0 2006.257.05:59:30.63#ibcon#read 6, iclass 12, count 0 2006.257.05:59:30.63#ibcon#end of sib2, iclass 12, count 0 2006.257.05:59:30.63#ibcon#*after write, iclass 12, count 0 2006.257.05:59:30.63#ibcon#*before return 0, iclass 12, count 0 2006.257.05:59:30.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:30.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:30.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:59:30.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:59:30.63$vck44/va=5,4 2006.257.05:59:30.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.05:59:30.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.05:59:30.63#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:30.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:30.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:30.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:30.69#ibcon#enter wrdev, iclass 14, count 2 2006.257.05:59:30.69#ibcon#first serial, iclass 14, count 2 2006.257.05:59:30.69#ibcon#enter sib2, iclass 14, count 2 2006.257.05:59:30.69#ibcon#flushed, iclass 14, count 2 2006.257.05:59:30.69#ibcon#about to write, iclass 14, count 2 2006.257.05:59:30.69#ibcon#wrote, iclass 14, count 2 2006.257.05:59:30.69#ibcon#about to read 3, iclass 14, count 2 2006.257.05:59:30.71#ibcon#read 3, iclass 14, count 2 2006.257.05:59:30.71#ibcon#about to read 4, iclass 14, count 2 2006.257.05:59:30.71#ibcon#read 4, iclass 14, count 2 2006.257.05:59:30.71#ibcon#about to read 5, iclass 14, count 2 2006.257.05:59:30.71#ibcon#read 5, iclass 14, count 2 2006.257.05:59:30.71#ibcon#about to read 6, iclass 14, count 2 2006.257.05:59:30.71#ibcon#read 6, iclass 14, count 2 2006.257.05:59:30.71#ibcon#end of sib2, iclass 14, count 2 2006.257.05:59:30.71#ibcon#*mode == 0, iclass 14, count 2 2006.257.05:59:30.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.05:59:30.71#ibcon#[25=AT05-04\r\n] 2006.257.05:59:30.71#ibcon#*before write, iclass 14, count 2 2006.257.05:59:30.71#ibcon#enter sib2, iclass 14, count 2 2006.257.05:59:30.71#ibcon#flushed, iclass 14, count 2 2006.257.05:59:30.71#ibcon#about to write, iclass 14, count 2 2006.257.05:59:30.71#ibcon#wrote, iclass 14, count 2 2006.257.05:59:30.71#ibcon#about to read 3, iclass 14, count 2 2006.257.05:59:30.74#ibcon#read 3, iclass 14, count 2 2006.257.05:59:30.74#ibcon#about to read 4, iclass 14, count 2 2006.257.05:59:30.74#ibcon#read 4, iclass 14, count 2 2006.257.05:59:30.74#ibcon#about to read 5, iclass 14, count 2 2006.257.05:59:30.74#ibcon#read 5, iclass 14, count 2 2006.257.05:59:30.74#ibcon#about to read 6, iclass 14, count 2 2006.257.05:59:30.74#ibcon#read 6, iclass 14, count 2 2006.257.05:59:30.74#ibcon#end of sib2, iclass 14, count 2 2006.257.05:59:30.74#ibcon#*after write, iclass 14, count 2 2006.257.05:59:30.74#ibcon#*before return 0, iclass 14, count 2 2006.257.05:59:30.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:30.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:30.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.05:59:30.74#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:30.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:30.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:30.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:30.86#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:59:30.86#ibcon#first serial, iclass 14, count 0 2006.257.05:59:30.86#ibcon#enter sib2, iclass 14, count 0 2006.257.05:59:30.86#ibcon#flushed, iclass 14, count 0 2006.257.05:59:30.86#ibcon#about to write, iclass 14, count 0 2006.257.05:59:30.86#ibcon#wrote, iclass 14, count 0 2006.257.05:59:30.86#ibcon#about to read 3, iclass 14, count 0 2006.257.05:59:30.88#ibcon#read 3, iclass 14, count 0 2006.257.05:59:30.88#ibcon#about to read 4, iclass 14, count 0 2006.257.05:59:30.88#ibcon#read 4, iclass 14, count 0 2006.257.05:59:30.88#ibcon#about to read 5, iclass 14, count 0 2006.257.05:59:30.88#ibcon#read 5, iclass 14, count 0 2006.257.05:59:30.88#ibcon#about to read 6, iclass 14, count 0 2006.257.05:59:30.88#ibcon#read 6, iclass 14, count 0 2006.257.05:59:30.88#ibcon#end of sib2, iclass 14, count 0 2006.257.05:59:30.88#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:59:30.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:59:30.88#ibcon#[25=USB\r\n] 2006.257.05:59:30.88#ibcon#*before write, iclass 14, count 0 2006.257.05:59:30.88#ibcon#enter sib2, iclass 14, count 0 2006.257.05:59:30.88#ibcon#flushed, iclass 14, count 0 2006.257.05:59:30.88#ibcon#about to write, iclass 14, count 0 2006.257.05:59:30.88#ibcon#wrote, iclass 14, count 0 2006.257.05:59:30.88#ibcon#about to read 3, iclass 14, count 0 2006.257.05:59:30.91#ibcon#read 3, iclass 14, count 0 2006.257.05:59:30.91#ibcon#about to read 4, iclass 14, count 0 2006.257.05:59:30.91#ibcon#read 4, iclass 14, count 0 2006.257.05:59:30.91#ibcon#about to read 5, iclass 14, count 0 2006.257.05:59:30.91#ibcon#read 5, iclass 14, count 0 2006.257.05:59:30.91#ibcon#about to read 6, iclass 14, count 0 2006.257.05:59:30.91#ibcon#read 6, iclass 14, count 0 2006.257.05:59:30.91#ibcon#end of sib2, iclass 14, count 0 2006.257.05:59:30.91#ibcon#*after write, iclass 14, count 0 2006.257.05:59:30.91#ibcon#*before return 0, iclass 14, count 0 2006.257.05:59:30.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:30.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:30.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:59:30.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:59:30.91$vck44/valo=6,814.99 2006.257.05:59:30.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.05:59:30.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.05:59:30.91#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:30.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:30.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:30.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:30.91#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:59:30.91#ibcon#first serial, iclass 16, count 0 2006.257.05:59:30.91#ibcon#enter sib2, iclass 16, count 0 2006.257.05:59:30.91#ibcon#flushed, iclass 16, count 0 2006.257.05:59:30.91#ibcon#about to write, iclass 16, count 0 2006.257.05:59:30.91#ibcon#wrote, iclass 16, count 0 2006.257.05:59:30.91#ibcon#about to read 3, iclass 16, count 0 2006.257.05:59:30.93#ibcon#read 3, iclass 16, count 0 2006.257.05:59:30.93#ibcon#about to read 4, iclass 16, count 0 2006.257.05:59:30.93#ibcon#read 4, iclass 16, count 0 2006.257.05:59:30.93#ibcon#about to read 5, iclass 16, count 0 2006.257.05:59:30.93#ibcon#read 5, iclass 16, count 0 2006.257.05:59:30.93#ibcon#about to read 6, iclass 16, count 0 2006.257.05:59:30.93#ibcon#read 6, iclass 16, count 0 2006.257.05:59:30.93#ibcon#end of sib2, iclass 16, count 0 2006.257.05:59:30.93#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:59:30.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:59:30.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.05:59:30.93#ibcon#*before write, iclass 16, count 0 2006.257.05:59:30.93#ibcon#enter sib2, iclass 16, count 0 2006.257.05:59:30.93#ibcon#flushed, iclass 16, count 0 2006.257.05:59:30.93#ibcon#about to write, iclass 16, count 0 2006.257.05:59:30.93#ibcon#wrote, iclass 16, count 0 2006.257.05:59:30.93#ibcon#about to read 3, iclass 16, count 0 2006.257.05:59:30.97#ibcon#read 3, iclass 16, count 0 2006.257.05:59:30.97#ibcon#about to read 4, iclass 16, count 0 2006.257.05:59:30.97#ibcon#read 4, iclass 16, count 0 2006.257.05:59:30.97#ibcon#about to read 5, iclass 16, count 0 2006.257.05:59:30.97#ibcon#read 5, iclass 16, count 0 2006.257.05:59:30.97#ibcon#about to read 6, iclass 16, count 0 2006.257.05:59:30.97#ibcon#read 6, iclass 16, count 0 2006.257.05:59:30.97#ibcon#end of sib2, iclass 16, count 0 2006.257.05:59:30.97#ibcon#*after write, iclass 16, count 0 2006.257.05:59:30.97#ibcon#*before return 0, iclass 16, count 0 2006.257.05:59:30.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:30.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:30.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:59:30.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:59:30.97$vck44/va=6,4 2006.257.05:59:30.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.05:59:30.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.05:59:30.97#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:30.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:31.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:31.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:31.03#ibcon#enter wrdev, iclass 18, count 2 2006.257.05:59:31.03#ibcon#first serial, iclass 18, count 2 2006.257.05:59:31.03#ibcon#enter sib2, iclass 18, count 2 2006.257.05:59:31.03#ibcon#flushed, iclass 18, count 2 2006.257.05:59:31.03#ibcon#about to write, iclass 18, count 2 2006.257.05:59:31.03#ibcon#wrote, iclass 18, count 2 2006.257.05:59:31.03#ibcon#about to read 3, iclass 18, count 2 2006.257.05:59:31.05#ibcon#read 3, iclass 18, count 2 2006.257.05:59:31.05#ibcon#about to read 4, iclass 18, count 2 2006.257.05:59:31.05#ibcon#read 4, iclass 18, count 2 2006.257.05:59:31.05#ibcon#about to read 5, iclass 18, count 2 2006.257.05:59:31.05#ibcon#read 5, iclass 18, count 2 2006.257.05:59:31.05#ibcon#about to read 6, iclass 18, count 2 2006.257.05:59:31.05#ibcon#read 6, iclass 18, count 2 2006.257.05:59:31.05#ibcon#end of sib2, iclass 18, count 2 2006.257.05:59:31.05#ibcon#*mode == 0, iclass 18, count 2 2006.257.05:59:31.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.05:59:31.05#ibcon#[25=AT06-04\r\n] 2006.257.05:59:31.05#ibcon#*before write, iclass 18, count 2 2006.257.05:59:31.05#ibcon#enter sib2, iclass 18, count 2 2006.257.05:59:31.05#ibcon#flushed, iclass 18, count 2 2006.257.05:59:31.05#ibcon#about to write, iclass 18, count 2 2006.257.05:59:31.05#ibcon#wrote, iclass 18, count 2 2006.257.05:59:31.05#ibcon#about to read 3, iclass 18, count 2 2006.257.05:59:31.08#ibcon#read 3, iclass 18, count 2 2006.257.05:59:31.08#ibcon#about to read 4, iclass 18, count 2 2006.257.05:59:31.08#ibcon#read 4, iclass 18, count 2 2006.257.05:59:31.08#ibcon#about to read 5, iclass 18, count 2 2006.257.05:59:31.08#ibcon#read 5, iclass 18, count 2 2006.257.05:59:31.08#ibcon#about to read 6, iclass 18, count 2 2006.257.05:59:31.08#ibcon#read 6, iclass 18, count 2 2006.257.05:59:31.08#ibcon#end of sib2, iclass 18, count 2 2006.257.05:59:31.08#ibcon#*after write, iclass 18, count 2 2006.257.05:59:31.08#ibcon#*before return 0, iclass 18, count 2 2006.257.05:59:31.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:31.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:31.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.05:59:31.08#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:31.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:31.12#abcon#<5=/16 1.4 4.7 20.13 881012.2\r\n> 2006.257.05:59:31.14#abcon#{5=INTERFACE CLEAR} 2006.257.05:59:31.20#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:59:31.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:31.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:31.20#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:59:31.20#ibcon#first serial, iclass 18, count 0 2006.257.05:59:31.20#ibcon#enter sib2, iclass 18, count 0 2006.257.05:59:31.20#ibcon#flushed, iclass 18, count 0 2006.257.05:59:31.20#ibcon#about to write, iclass 18, count 0 2006.257.05:59:31.20#ibcon#wrote, iclass 18, count 0 2006.257.05:59:31.20#ibcon#about to read 3, iclass 18, count 0 2006.257.05:59:31.22#ibcon#read 3, iclass 18, count 0 2006.257.05:59:31.22#ibcon#about to read 4, iclass 18, count 0 2006.257.05:59:31.22#ibcon#read 4, iclass 18, count 0 2006.257.05:59:31.22#ibcon#about to read 5, iclass 18, count 0 2006.257.05:59:31.22#ibcon#read 5, iclass 18, count 0 2006.257.05:59:31.22#ibcon#about to read 6, iclass 18, count 0 2006.257.05:59:31.22#ibcon#read 6, iclass 18, count 0 2006.257.05:59:31.22#ibcon#end of sib2, iclass 18, count 0 2006.257.05:59:31.22#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:59:31.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:59:31.22#ibcon#[25=USB\r\n] 2006.257.05:59:31.22#ibcon#*before write, iclass 18, count 0 2006.257.05:59:31.22#ibcon#enter sib2, iclass 18, count 0 2006.257.05:59:31.22#ibcon#flushed, iclass 18, count 0 2006.257.05:59:31.22#ibcon#about to write, iclass 18, count 0 2006.257.05:59:31.22#ibcon#wrote, iclass 18, count 0 2006.257.05:59:31.22#ibcon#about to read 3, iclass 18, count 0 2006.257.05:59:31.25#ibcon#read 3, iclass 18, count 0 2006.257.05:59:31.25#ibcon#about to read 4, iclass 18, count 0 2006.257.05:59:31.25#ibcon#read 4, iclass 18, count 0 2006.257.05:59:31.25#ibcon#about to read 5, iclass 18, count 0 2006.257.05:59:31.25#ibcon#read 5, iclass 18, count 0 2006.257.05:59:31.25#ibcon#about to read 6, iclass 18, count 0 2006.257.05:59:31.25#ibcon#read 6, iclass 18, count 0 2006.257.05:59:31.25#ibcon#end of sib2, iclass 18, count 0 2006.257.05:59:31.25#ibcon#*after write, iclass 18, count 0 2006.257.05:59:31.25#ibcon#*before return 0, iclass 18, count 0 2006.257.05:59:31.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:31.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:31.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:59:31.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:59:31.25$vck44/valo=7,864.99 2006.257.05:59:31.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.05:59:31.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.05:59:31.25#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:31.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:31.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:31.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:31.25#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:59:31.25#ibcon#first serial, iclass 24, count 0 2006.257.05:59:31.25#ibcon#enter sib2, iclass 24, count 0 2006.257.05:59:31.25#ibcon#flushed, iclass 24, count 0 2006.257.05:59:31.25#ibcon#about to write, iclass 24, count 0 2006.257.05:59:31.25#ibcon#wrote, iclass 24, count 0 2006.257.05:59:31.25#ibcon#about to read 3, iclass 24, count 0 2006.257.05:59:31.27#ibcon#read 3, iclass 24, count 0 2006.257.05:59:31.27#ibcon#about to read 4, iclass 24, count 0 2006.257.05:59:31.27#ibcon#read 4, iclass 24, count 0 2006.257.05:59:31.27#ibcon#about to read 5, iclass 24, count 0 2006.257.05:59:31.27#ibcon#read 5, iclass 24, count 0 2006.257.05:59:31.27#ibcon#about to read 6, iclass 24, count 0 2006.257.05:59:31.27#ibcon#read 6, iclass 24, count 0 2006.257.05:59:31.27#ibcon#end of sib2, iclass 24, count 0 2006.257.05:59:31.27#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:59:31.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:59:31.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.05:59:31.27#ibcon#*before write, iclass 24, count 0 2006.257.05:59:31.27#ibcon#enter sib2, iclass 24, count 0 2006.257.05:59:31.27#ibcon#flushed, iclass 24, count 0 2006.257.05:59:31.27#ibcon#about to write, iclass 24, count 0 2006.257.05:59:31.27#ibcon#wrote, iclass 24, count 0 2006.257.05:59:31.27#ibcon#about to read 3, iclass 24, count 0 2006.257.05:59:31.31#ibcon#read 3, iclass 24, count 0 2006.257.05:59:31.31#ibcon#about to read 4, iclass 24, count 0 2006.257.05:59:31.31#ibcon#read 4, iclass 24, count 0 2006.257.05:59:31.31#ibcon#about to read 5, iclass 24, count 0 2006.257.05:59:31.31#ibcon#read 5, iclass 24, count 0 2006.257.05:59:31.31#ibcon#about to read 6, iclass 24, count 0 2006.257.05:59:31.31#ibcon#read 6, iclass 24, count 0 2006.257.05:59:31.31#ibcon#end of sib2, iclass 24, count 0 2006.257.05:59:31.31#ibcon#*after write, iclass 24, count 0 2006.257.05:59:31.31#ibcon#*before return 0, iclass 24, count 0 2006.257.05:59:31.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:31.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:31.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:59:31.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:59:31.31$vck44/va=7,4 2006.257.05:59:31.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.05:59:31.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.05:59:31.31#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:31.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:31.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:31.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:31.37#ibcon#enter wrdev, iclass 26, count 2 2006.257.05:59:31.37#ibcon#first serial, iclass 26, count 2 2006.257.05:59:31.37#ibcon#enter sib2, iclass 26, count 2 2006.257.05:59:31.37#ibcon#flushed, iclass 26, count 2 2006.257.05:59:31.37#ibcon#about to write, iclass 26, count 2 2006.257.05:59:31.37#ibcon#wrote, iclass 26, count 2 2006.257.05:59:31.37#ibcon#about to read 3, iclass 26, count 2 2006.257.05:59:31.39#ibcon#read 3, iclass 26, count 2 2006.257.05:59:31.39#ibcon#about to read 4, iclass 26, count 2 2006.257.05:59:31.39#ibcon#read 4, iclass 26, count 2 2006.257.05:59:31.39#ibcon#about to read 5, iclass 26, count 2 2006.257.05:59:31.39#ibcon#read 5, iclass 26, count 2 2006.257.05:59:31.39#ibcon#about to read 6, iclass 26, count 2 2006.257.05:59:31.39#ibcon#read 6, iclass 26, count 2 2006.257.05:59:31.39#ibcon#end of sib2, iclass 26, count 2 2006.257.05:59:31.39#ibcon#*mode == 0, iclass 26, count 2 2006.257.05:59:31.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.05:59:31.39#ibcon#[25=AT07-04\r\n] 2006.257.05:59:31.39#ibcon#*before write, iclass 26, count 2 2006.257.05:59:31.39#ibcon#enter sib2, iclass 26, count 2 2006.257.05:59:31.39#ibcon#flushed, iclass 26, count 2 2006.257.05:59:31.39#ibcon#about to write, iclass 26, count 2 2006.257.05:59:31.39#ibcon#wrote, iclass 26, count 2 2006.257.05:59:31.39#ibcon#about to read 3, iclass 26, count 2 2006.257.05:59:31.42#ibcon#read 3, iclass 26, count 2 2006.257.05:59:31.42#ibcon#about to read 4, iclass 26, count 2 2006.257.05:59:31.42#ibcon#read 4, iclass 26, count 2 2006.257.05:59:31.42#ibcon#about to read 5, iclass 26, count 2 2006.257.05:59:31.42#ibcon#read 5, iclass 26, count 2 2006.257.05:59:31.42#ibcon#about to read 6, iclass 26, count 2 2006.257.05:59:31.42#ibcon#read 6, iclass 26, count 2 2006.257.05:59:31.42#ibcon#end of sib2, iclass 26, count 2 2006.257.05:59:31.42#ibcon#*after write, iclass 26, count 2 2006.257.05:59:31.42#ibcon#*before return 0, iclass 26, count 2 2006.257.05:59:31.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:31.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:31.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.05:59:31.42#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:31.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:31.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:31.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:31.54#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:59:31.54#ibcon#first serial, iclass 26, count 0 2006.257.05:59:31.54#ibcon#enter sib2, iclass 26, count 0 2006.257.05:59:31.54#ibcon#flushed, iclass 26, count 0 2006.257.05:59:31.54#ibcon#about to write, iclass 26, count 0 2006.257.05:59:31.54#ibcon#wrote, iclass 26, count 0 2006.257.05:59:31.54#ibcon#about to read 3, iclass 26, count 0 2006.257.05:59:31.56#ibcon#read 3, iclass 26, count 0 2006.257.05:59:31.56#ibcon#about to read 4, iclass 26, count 0 2006.257.05:59:31.56#ibcon#read 4, iclass 26, count 0 2006.257.05:59:31.56#ibcon#about to read 5, iclass 26, count 0 2006.257.05:59:31.56#ibcon#read 5, iclass 26, count 0 2006.257.05:59:31.56#ibcon#about to read 6, iclass 26, count 0 2006.257.05:59:31.56#ibcon#read 6, iclass 26, count 0 2006.257.05:59:31.56#ibcon#end of sib2, iclass 26, count 0 2006.257.05:59:31.56#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:59:31.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:59:31.56#ibcon#[25=USB\r\n] 2006.257.05:59:31.56#ibcon#*before write, iclass 26, count 0 2006.257.05:59:31.56#ibcon#enter sib2, iclass 26, count 0 2006.257.05:59:31.56#ibcon#flushed, iclass 26, count 0 2006.257.05:59:31.56#ibcon#about to write, iclass 26, count 0 2006.257.05:59:31.56#ibcon#wrote, iclass 26, count 0 2006.257.05:59:31.56#ibcon#about to read 3, iclass 26, count 0 2006.257.05:59:31.59#ibcon#read 3, iclass 26, count 0 2006.257.05:59:31.59#ibcon#about to read 4, iclass 26, count 0 2006.257.05:59:31.59#ibcon#read 4, iclass 26, count 0 2006.257.05:59:31.59#ibcon#about to read 5, iclass 26, count 0 2006.257.05:59:31.59#ibcon#read 5, iclass 26, count 0 2006.257.05:59:31.59#ibcon#about to read 6, iclass 26, count 0 2006.257.05:59:31.59#ibcon#read 6, iclass 26, count 0 2006.257.05:59:31.59#ibcon#end of sib2, iclass 26, count 0 2006.257.05:59:31.59#ibcon#*after write, iclass 26, count 0 2006.257.05:59:31.59#ibcon#*before return 0, iclass 26, count 0 2006.257.05:59:31.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:31.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:31.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:59:31.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:59:31.59$vck44/valo=8,884.99 2006.257.05:59:31.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.05:59:31.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.05:59:31.59#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:31.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:31.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:31.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:31.59#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:59:31.59#ibcon#first serial, iclass 28, count 0 2006.257.05:59:31.59#ibcon#enter sib2, iclass 28, count 0 2006.257.05:59:31.59#ibcon#flushed, iclass 28, count 0 2006.257.05:59:31.59#ibcon#about to write, iclass 28, count 0 2006.257.05:59:31.59#ibcon#wrote, iclass 28, count 0 2006.257.05:59:31.59#ibcon#about to read 3, iclass 28, count 0 2006.257.05:59:31.61#ibcon#read 3, iclass 28, count 0 2006.257.05:59:31.61#ibcon#about to read 4, iclass 28, count 0 2006.257.05:59:31.61#ibcon#read 4, iclass 28, count 0 2006.257.05:59:31.61#ibcon#about to read 5, iclass 28, count 0 2006.257.05:59:31.61#ibcon#read 5, iclass 28, count 0 2006.257.05:59:31.61#ibcon#about to read 6, iclass 28, count 0 2006.257.05:59:31.61#ibcon#read 6, iclass 28, count 0 2006.257.05:59:31.61#ibcon#end of sib2, iclass 28, count 0 2006.257.05:59:31.61#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:59:31.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:59:31.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.05:59:31.61#ibcon#*before write, iclass 28, count 0 2006.257.05:59:31.61#ibcon#enter sib2, iclass 28, count 0 2006.257.05:59:31.61#ibcon#flushed, iclass 28, count 0 2006.257.05:59:31.61#ibcon#about to write, iclass 28, count 0 2006.257.05:59:31.61#ibcon#wrote, iclass 28, count 0 2006.257.05:59:31.61#ibcon#about to read 3, iclass 28, count 0 2006.257.05:59:31.65#ibcon#read 3, iclass 28, count 0 2006.257.05:59:31.65#ibcon#about to read 4, iclass 28, count 0 2006.257.05:59:31.65#ibcon#read 4, iclass 28, count 0 2006.257.05:59:31.65#ibcon#about to read 5, iclass 28, count 0 2006.257.05:59:31.65#ibcon#read 5, iclass 28, count 0 2006.257.05:59:31.65#ibcon#about to read 6, iclass 28, count 0 2006.257.05:59:31.65#ibcon#read 6, iclass 28, count 0 2006.257.05:59:31.65#ibcon#end of sib2, iclass 28, count 0 2006.257.05:59:31.65#ibcon#*after write, iclass 28, count 0 2006.257.05:59:31.65#ibcon#*before return 0, iclass 28, count 0 2006.257.05:59:31.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:31.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:31.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:59:31.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:59:31.65$vck44/va=8,4 2006.257.05:59:31.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.05:59:31.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.05:59:31.65#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:31.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:59:31.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:59:31.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:59:31.71#ibcon#enter wrdev, iclass 30, count 2 2006.257.05:59:31.71#ibcon#first serial, iclass 30, count 2 2006.257.05:59:31.71#ibcon#enter sib2, iclass 30, count 2 2006.257.05:59:31.71#ibcon#flushed, iclass 30, count 2 2006.257.05:59:31.71#ibcon#about to write, iclass 30, count 2 2006.257.05:59:31.71#ibcon#wrote, iclass 30, count 2 2006.257.05:59:31.71#ibcon#about to read 3, iclass 30, count 2 2006.257.05:59:31.73#ibcon#read 3, iclass 30, count 2 2006.257.05:59:31.73#ibcon#about to read 4, iclass 30, count 2 2006.257.05:59:31.73#ibcon#read 4, iclass 30, count 2 2006.257.05:59:31.73#ibcon#about to read 5, iclass 30, count 2 2006.257.05:59:31.73#ibcon#read 5, iclass 30, count 2 2006.257.05:59:31.73#ibcon#about to read 6, iclass 30, count 2 2006.257.05:59:31.73#ibcon#read 6, iclass 30, count 2 2006.257.05:59:31.73#ibcon#end of sib2, iclass 30, count 2 2006.257.05:59:31.73#ibcon#*mode == 0, iclass 30, count 2 2006.257.05:59:31.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.05:59:31.73#ibcon#[25=AT08-04\r\n] 2006.257.05:59:31.73#ibcon#*before write, iclass 30, count 2 2006.257.05:59:31.73#ibcon#enter sib2, iclass 30, count 2 2006.257.05:59:31.73#ibcon#flushed, iclass 30, count 2 2006.257.05:59:31.73#ibcon#about to write, iclass 30, count 2 2006.257.05:59:31.73#ibcon#wrote, iclass 30, count 2 2006.257.05:59:31.73#ibcon#about to read 3, iclass 30, count 2 2006.257.05:59:31.76#ibcon#read 3, iclass 30, count 2 2006.257.05:59:31.76#ibcon#about to read 4, iclass 30, count 2 2006.257.05:59:31.76#ibcon#read 4, iclass 30, count 2 2006.257.05:59:31.76#ibcon#about to read 5, iclass 30, count 2 2006.257.05:59:31.76#ibcon#read 5, iclass 30, count 2 2006.257.05:59:31.76#ibcon#about to read 6, iclass 30, count 2 2006.257.05:59:31.76#ibcon#read 6, iclass 30, count 2 2006.257.05:59:31.76#ibcon#end of sib2, iclass 30, count 2 2006.257.05:59:31.76#ibcon#*after write, iclass 30, count 2 2006.257.05:59:31.76#ibcon#*before return 0, iclass 30, count 2 2006.257.05:59:31.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:59:31.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.05:59:31.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.05:59:31.76#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:31.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:59:31.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:59:31.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:59:31.88#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:59:31.88#ibcon#first serial, iclass 30, count 0 2006.257.05:59:31.88#ibcon#enter sib2, iclass 30, count 0 2006.257.05:59:31.88#ibcon#flushed, iclass 30, count 0 2006.257.05:59:31.88#ibcon#about to write, iclass 30, count 0 2006.257.05:59:31.88#ibcon#wrote, iclass 30, count 0 2006.257.05:59:31.88#ibcon#about to read 3, iclass 30, count 0 2006.257.05:59:31.90#ibcon#read 3, iclass 30, count 0 2006.257.05:59:31.90#ibcon#about to read 4, iclass 30, count 0 2006.257.05:59:31.90#ibcon#read 4, iclass 30, count 0 2006.257.05:59:31.90#ibcon#about to read 5, iclass 30, count 0 2006.257.05:59:31.90#ibcon#read 5, iclass 30, count 0 2006.257.05:59:31.90#ibcon#about to read 6, iclass 30, count 0 2006.257.05:59:31.90#ibcon#read 6, iclass 30, count 0 2006.257.05:59:31.90#ibcon#end of sib2, iclass 30, count 0 2006.257.05:59:31.90#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:59:31.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:59:31.90#ibcon#[25=USB\r\n] 2006.257.05:59:31.90#ibcon#*before write, iclass 30, count 0 2006.257.05:59:31.90#ibcon#enter sib2, iclass 30, count 0 2006.257.05:59:31.90#ibcon#flushed, iclass 30, count 0 2006.257.05:59:31.90#ibcon#about to write, iclass 30, count 0 2006.257.05:59:31.90#ibcon#wrote, iclass 30, count 0 2006.257.05:59:31.90#ibcon#about to read 3, iclass 30, count 0 2006.257.05:59:31.93#ibcon#read 3, iclass 30, count 0 2006.257.05:59:31.93#ibcon#about to read 4, iclass 30, count 0 2006.257.05:59:31.93#ibcon#read 4, iclass 30, count 0 2006.257.05:59:31.93#ibcon#about to read 5, iclass 30, count 0 2006.257.05:59:31.93#ibcon#read 5, iclass 30, count 0 2006.257.05:59:31.93#ibcon#about to read 6, iclass 30, count 0 2006.257.05:59:31.93#ibcon#read 6, iclass 30, count 0 2006.257.05:59:31.93#ibcon#end of sib2, iclass 30, count 0 2006.257.05:59:31.93#ibcon#*after write, iclass 30, count 0 2006.257.05:59:31.93#ibcon#*before return 0, iclass 30, count 0 2006.257.05:59:31.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:59:31.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.05:59:31.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:59:31.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:59:31.93$vck44/vblo=1,629.99 2006.257.05:59:31.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.05:59:31.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.05:59:31.93#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:31.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:31.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:31.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:31.93#ibcon#enter wrdev, iclass 32, count 0 2006.257.05:59:31.93#ibcon#first serial, iclass 32, count 0 2006.257.05:59:31.93#ibcon#enter sib2, iclass 32, count 0 2006.257.05:59:31.93#ibcon#flushed, iclass 32, count 0 2006.257.05:59:31.93#ibcon#about to write, iclass 32, count 0 2006.257.05:59:31.93#ibcon#wrote, iclass 32, count 0 2006.257.05:59:31.93#ibcon#about to read 3, iclass 32, count 0 2006.257.05:59:31.95#ibcon#read 3, iclass 32, count 0 2006.257.05:59:31.95#ibcon#about to read 4, iclass 32, count 0 2006.257.05:59:31.95#ibcon#read 4, iclass 32, count 0 2006.257.05:59:31.95#ibcon#about to read 5, iclass 32, count 0 2006.257.05:59:31.95#ibcon#read 5, iclass 32, count 0 2006.257.05:59:31.95#ibcon#about to read 6, iclass 32, count 0 2006.257.05:59:31.95#ibcon#read 6, iclass 32, count 0 2006.257.05:59:31.95#ibcon#end of sib2, iclass 32, count 0 2006.257.05:59:31.95#ibcon#*mode == 0, iclass 32, count 0 2006.257.05:59:31.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.05:59:31.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.05:59:31.95#ibcon#*before write, iclass 32, count 0 2006.257.05:59:31.95#ibcon#enter sib2, iclass 32, count 0 2006.257.05:59:31.95#ibcon#flushed, iclass 32, count 0 2006.257.05:59:31.95#ibcon#about to write, iclass 32, count 0 2006.257.05:59:31.95#ibcon#wrote, iclass 32, count 0 2006.257.05:59:31.95#ibcon#about to read 3, iclass 32, count 0 2006.257.05:59:31.99#ibcon#read 3, iclass 32, count 0 2006.257.05:59:31.99#ibcon#about to read 4, iclass 32, count 0 2006.257.05:59:31.99#ibcon#read 4, iclass 32, count 0 2006.257.05:59:31.99#ibcon#about to read 5, iclass 32, count 0 2006.257.05:59:31.99#ibcon#read 5, iclass 32, count 0 2006.257.05:59:31.99#ibcon#about to read 6, iclass 32, count 0 2006.257.05:59:31.99#ibcon#read 6, iclass 32, count 0 2006.257.05:59:31.99#ibcon#end of sib2, iclass 32, count 0 2006.257.05:59:31.99#ibcon#*after write, iclass 32, count 0 2006.257.05:59:31.99#ibcon#*before return 0, iclass 32, count 0 2006.257.05:59:31.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:31.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.05:59:31.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.05:59:31.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.05:59:31.99$vck44/vb=1,4 2006.257.05:59:31.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.05:59:31.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.05:59:31.99#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:31.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:31.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:31.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:31.99#ibcon#enter wrdev, iclass 34, count 2 2006.257.05:59:31.99#ibcon#first serial, iclass 34, count 2 2006.257.05:59:31.99#ibcon#enter sib2, iclass 34, count 2 2006.257.05:59:31.99#ibcon#flushed, iclass 34, count 2 2006.257.05:59:31.99#ibcon#about to write, iclass 34, count 2 2006.257.05:59:31.99#ibcon#wrote, iclass 34, count 2 2006.257.05:59:31.99#ibcon#about to read 3, iclass 34, count 2 2006.257.05:59:32.01#ibcon#read 3, iclass 34, count 2 2006.257.05:59:32.01#ibcon#about to read 4, iclass 34, count 2 2006.257.05:59:32.01#ibcon#read 4, iclass 34, count 2 2006.257.05:59:32.01#ibcon#about to read 5, iclass 34, count 2 2006.257.05:59:32.01#ibcon#read 5, iclass 34, count 2 2006.257.05:59:32.01#ibcon#about to read 6, iclass 34, count 2 2006.257.05:59:32.01#ibcon#read 6, iclass 34, count 2 2006.257.05:59:32.01#ibcon#end of sib2, iclass 34, count 2 2006.257.05:59:32.01#ibcon#*mode == 0, iclass 34, count 2 2006.257.05:59:32.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.05:59:32.01#ibcon#[27=AT01-04\r\n] 2006.257.05:59:32.01#ibcon#*before write, iclass 34, count 2 2006.257.05:59:32.01#ibcon#enter sib2, iclass 34, count 2 2006.257.05:59:32.01#ibcon#flushed, iclass 34, count 2 2006.257.05:59:32.01#ibcon#about to write, iclass 34, count 2 2006.257.05:59:32.01#ibcon#wrote, iclass 34, count 2 2006.257.05:59:32.01#ibcon#about to read 3, iclass 34, count 2 2006.257.05:59:32.04#ibcon#read 3, iclass 34, count 2 2006.257.05:59:32.04#ibcon#about to read 4, iclass 34, count 2 2006.257.05:59:32.04#ibcon#read 4, iclass 34, count 2 2006.257.05:59:32.04#ibcon#about to read 5, iclass 34, count 2 2006.257.05:59:32.04#ibcon#read 5, iclass 34, count 2 2006.257.05:59:32.04#ibcon#about to read 6, iclass 34, count 2 2006.257.05:59:32.04#ibcon#read 6, iclass 34, count 2 2006.257.05:59:32.04#ibcon#end of sib2, iclass 34, count 2 2006.257.05:59:32.04#ibcon#*after write, iclass 34, count 2 2006.257.05:59:32.04#ibcon#*before return 0, iclass 34, count 2 2006.257.05:59:32.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:32.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.05:59:32.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.05:59:32.04#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:32.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:32.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:32.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:32.16#ibcon#enter wrdev, iclass 34, count 0 2006.257.05:59:32.16#ibcon#first serial, iclass 34, count 0 2006.257.05:59:32.16#ibcon#enter sib2, iclass 34, count 0 2006.257.05:59:32.16#ibcon#flushed, iclass 34, count 0 2006.257.05:59:32.16#ibcon#about to write, iclass 34, count 0 2006.257.05:59:32.16#ibcon#wrote, iclass 34, count 0 2006.257.05:59:32.16#ibcon#about to read 3, iclass 34, count 0 2006.257.05:59:32.18#ibcon#read 3, iclass 34, count 0 2006.257.05:59:32.18#ibcon#about to read 4, iclass 34, count 0 2006.257.05:59:32.18#ibcon#read 4, iclass 34, count 0 2006.257.05:59:32.18#ibcon#about to read 5, iclass 34, count 0 2006.257.05:59:32.18#ibcon#read 5, iclass 34, count 0 2006.257.05:59:32.18#ibcon#about to read 6, iclass 34, count 0 2006.257.05:59:32.18#ibcon#read 6, iclass 34, count 0 2006.257.05:59:32.18#ibcon#end of sib2, iclass 34, count 0 2006.257.05:59:32.18#ibcon#*mode == 0, iclass 34, count 0 2006.257.05:59:32.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.05:59:32.18#ibcon#[27=USB\r\n] 2006.257.05:59:32.18#ibcon#*before write, iclass 34, count 0 2006.257.05:59:32.18#ibcon#enter sib2, iclass 34, count 0 2006.257.05:59:32.18#ibcon#flushed, iclass 34, count 0 2006.257.05:59:32.18#ibcon#about to write, iclass 34, count 0 2006.257.05:59:32.18#ibcon#wrote, iclass 34, count 0 2006.257.05:59:32.18#ibcon#about to read 3, iclass 34, count 0 2006.257.05:59:32.21#ibcon#read 3, iclass 34, count 0 2006.257.05:59:32.21#ibcon#about to read 4, iclass 34, count 0 2006.257.05:59:32.21#ibcon#read 4, iclass 34, count 0 2006.257.05:59:32.21#ibcon#about to read 5, iclass 34, count 0 2006.257.05:59:32.21#ibcon#read 5, iclass 34, count 0 2006.257.05:59:32.21#ibcon#about to read 6, iclass 34, count 0 2006.257.05:59:32.21#ibcon#read 6, iclass 34, count 0 2006.257.05:59:32.21#ibcon#end of sib2, iclass 34, count 0 2006.257.05:59:32.21#ibcon#*after write, iclass 34, count 0 2006.257.05:59:32.21#ibcon#*before return 0, iclass 34, count 0 2006.257.05:59:32.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:32.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.05:59:32.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.05:59:32.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.05:59:32.21$vck44/vblo=2,634.99 2006.257.05:59:32.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.05:59:32.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.05:59:32.21#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:32.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:32.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:32.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:32.21#ibcon#enter wrdev, iclass 36, count 0 2006.257.05:59:32.21#ibcon#first serial, iclass 36, count 0 2006.257.05:59:32.21#ibcon#enter sib2, iclass 36, count 0 2006.257.05:59:32.21#ibcon#flushed, iclass 36, count 0 2006.257.05:59:32.21#ibcon#about to write, iclass 36, count 0 2006.257.05:59:32.21#ibcon#wrote, iclass 36, count 0 2006.257.05:59:32.21#ibcon#about to read 3, iclass 36, count 0 2006.257.05:59:32.23#ibcon#read 3, iclass 36, count 0 2006.257.05:59:32.23#ibcon#about to read 4, iclass 36, count 0 2006.257.05:59:32.23#ibcon#read 4, iclass 36, count 0 2006.257.05:59:32.23#ibcon#about to read 5, iclass 36, count 0 2006.257.05:59:32.23#ibcon#read 5, iclass 36, count 0 2006.257.05:59:32.23#ibcon#about to read 6, iclass 36, count 0 2006.257.05:59:32.23#ibcon#read 6, iclass 36, count 0 2006.257.05:59:32.23#ibcon#end of sib2, iclass 36, count 0 2006.257.05:59:32.23#ibcon#*mode == 0, iclass 36, count 0 2006.257.05:59:32.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.05:59:32.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.05:59:32.23#ibcon#*before write, iclass 36, count 0 2006.257.05:59:32.23#ibcon#enter sib2, iclass 36, count 0 2006.257.05:59:32.23#ibcon#flushed, iclass 36, count 0 2006.257.05:59:32.23#ibcon#about to write, iclass 36, count 0 2006.257.05:59:32.23#ibcon#wrote, iclass 36, count 0 2006.257.05:59:32.23#ibcon#about to read 3, iclass 36, count 0 2006.257.05:59:32.27#ibcon#read 3, iclass 36, count 0 2006.257.05:59:32.27#ibcon#about to read 4, iclass 36, count 0 2006.257.05:59:32.27#ibcon#read 4, iclass 36, count 0 2006.257.05:59:32.27#ibcon#about to read 5, iclass 36, count 0 2006.257.05:59:32.27#ibcon#read 5, iclass 36, count 0 2006.257.05:59:32.27#ibcon#about to read 6, iclass 36, count 0 2006.257.05:59:32.27#ibcon#read 6, iclass 36, count 0 2006.257.05:59:32.27#ibcon#end of sib2, iclass 36, count 0 2006.257.05:59:32.27#ibcon#*after write, iclass 36, count 0 2006.257.05:59:32.27#ibcon#*before return 0, iclass 36, count 0 2006.257.05:59:32.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:32.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.05:59:32.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.05:59:32.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.05:59:32.27$vck44/vb=2,5 2006.257.05:59:32.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.05:59:32.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.05:59:32.27#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:32.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:32.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:32.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:32.33#ibcon#enter wrdev, iclass 38, count 2 2006.257.05:59:32.33#ibcon#first serial, iclass 38, count 2 2006.257.05:59:32.33#ibcon#enter sib2, iclass 38, count 2 2006.257.05:59:32.33#ibcon#flushed, iclass 38, count 2 2006.257.05:59:32.33#ibcon#about to write, iclass 38, count 2 2006.257.05:59:32.33#ibcon#wrote, iclass 38, count 2 2006.257.05:59:32.33#ibcon#about to read 3, iclass 38, count 2 2006.257.05:59:32.35#ibcon#read 3, iclass 38, count 2 2006.257.05:59:32.35#ibcon#about to read 4, iclass 38, count 2 2006.257.05:59:32.35#ibcon#read 4, iclass 38, count 2 2006.257.05:59:32.35#ibcon#about to read 5, iclass 38, count 2 2006.257.05:59:32.35#ibcon#read 5, iclass 38, count 2 2006.257.05:59:32.35#ibcon#about to read 6, iclass 38, count 2 2006.257.05:59:32.35#ibcon#read 6, iclass 38, count 2 2006.257.05:59:32.35#ibcon#end of sib2, iclass 38, count 2 2006.257.05:59:32.35#ibcon#*mode == 0, iclass 38, count 2 2006.257.05:59:32.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.05:59:32.35#ibcon#[27=AT02-05\r\n] 2006.257.05:59:32.35#ibcon#*before write, iclass 38, count 2 2006.257.05:59:32.35#ibcon#enter sib2, iclass 38, count 2 2006.257.05:59:32.35#ibcon#flushed, iclass 38, count 2 2006.257.05:59:32.35#ibcon#about to write, iclass 38, count 2 2006.257.05:59:32.35#ibcon#wrote, iclass 38, count 2 2006.257.05:59:32.35#ibcon#about to read 3, iclass 38, count 2 2006.257.05:59:32.38#ibcon#read 3, iclass 38, count 2 2006.257.05:59:32.38#ibcon#about to read 4, iclass 38, count 2 2006.257.05:59:32.38#ibcon#read 4, iclass 38, count 2 2006.257.05:59:32.38#ibcon#about to read 5, iclass 38, count 2 2006.257.05:59:32.38#ibcon#read 5, iclass 38, count 2 2006.257.05:59:32.38#ibcon#about to read 6, iclass 38, count 2 2006.257.05:59:32.38#ibcon#read 6, iclass 38, count 2 2006.257.05:59:32.38#ibcon#end of sib2, iclass 38, count 2 2006.257.05:59:32.38#ibcon#*after write, iclass 38, count 2 2006.257.05:59:32.38#ibcon#*before return 0, iclass 38, count 2 2006.257.05:59:32.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:32.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.05:59:32.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.05:59:32.38#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:32.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:32.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:32.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:32.50#ibcon#enter wrdev, iclass 38, count 0 2006.257.05:59:32.50#ibcon#first serial, iclass 38, count 0 2006.257.05:59:32.50#ibcon#enter sib2, iclass 38, count 0 2006.257.05:59:32.50#ibcon#flushed, iclass 38, count 0 2006.257.05:59:32.50#ibcon#about to write, iclass 38, count 0 2006.257.05:59:32.50#ibcon#wrote, iclass 38, count 0 2006.257.05:59:32.50#ibcon#about to read 3, iclass 38, count 0 2006.257.05:59:32.52#ibcon#read 3, iclass 38, count 0 2006.257.05:59:32.52#ibcon#about to read 4, iclass 38, count 0 2006.257.05:59:32.52#ibcon#read 4, iclass 38, count 0 2006.257.05:59:32.52#ibcon#about to read 5, iclass 38, count 0 2006.257.05:59:32.52#ibcon#read 5, iclass 38, count 0 2006.257.05:59:32.52#ibcon#about to read 6, iclass 38, count 0 2006.257.05:59:32.52#ibcon#read 6, iclass 38, count 0 2006.257.05:59:32.52#ibcon#end of sib2, iclass 38, count 0 2006.257.05:59:32.52#ibcon#*mode == 0, iclass 38, count 0 2006.257.05:59:32.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.05:59:32.52#ibcon#[27=USB\r\n] 2006.257.05:59:32.52#ibcon#*before write, iclass 38, count 0 2006.257.05:59:32.52#ibcon#enter sib2, iclass 38, count 0 2006.257.05:59:32.52#ibcon#flushed, iclass 38, count 0 2006.257.05:59:32.52#ibcon#about to write, iclass 38, count 0 2006.257.05:59:32.52#ibcon#wrote, iclass 38, count 0 2006.257.05:59:32.52#ibcon#about to read 3, iclass 38, count 0 2006.257.05:59:32.55#ibcon#read 3, iclass 38, count 0 2006.257.05:59:32.55#ibcon#about to read 4, iclass 38, count 0 2006.257.05:59:32.55#ibcon#read 4, iclass 38, count 0 2006.257.05:59:32.55#ibcon#about to read 5, iclass 38, count 0 2006.257.05:59:32.55#ibcon#read 5, iclass 38, count 0 2006.257.05:59:32.55#ibcon#about to read 6, iclass 38, count 0 2006.257.05:59:32.55#ibcon#read 6, iclass 38, count 0 2006.257.05:59:32.55#ibcon#end of sib2, iclass 38, count 0 2006.257.05:59:32.55#ibcon#*after write, iclass 38, count 0 2006.257.05:59:32.55#ibcon#*before return 0, iclass 38, count 0 2006.257.05:59:32.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:32.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.05:59:32.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.05:59:32.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.05:59:32.55$vck44/vblo=3,649.99 2006.257.05:59:32.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.05:59:32.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.05:59:32.55#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:32.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:32.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:32.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:32.55#ibcon#enter wrdev, iclass 40, count 0 2006.257.05:59:32.55#ibcon#first serial, iclass 40, count 0 2006.257.05:59:32.55#ibcon#enter sib2, iclass 40, count 0 2006.257.05:59:32.55#ibcon#flushed, iclass 40, count 0 2006.257.05:59:32.55#ibcon#about to write, iclass 40, count 0 2006.257.05:59:32.55#ibcon#wrote, iclass 40, count 0 2006.257.05:59:32.55#ibcon#about to read 3, iclass 40, count 0 2006.257.05:59:32.57#ibcon#read 3, iclass 40, count 0 2006.257.05:59:32.57#ibcon#about to read 4, iclass 40, count 0 2006.257.05:59:32.57#ibcon#read 4, iclass 40, count 0 2006.257.05:59:32.57#ibcon#about to read 5, iclass 40, count 0 2006.257.05:59:32.57#ibcon#read 5, iclass 40, count 0 2006.257.05:59:32.57#ibcon#about to read 6, iclass 40, count 0 2006.257.05:59:32.57#ibcon#read 6, iclass 40, count 0 2006.257.05:59:32.57#ibcon#end of sib2, iclass 40, count 0 2006.257.05:59:32.57#ibcon#*mode == 0, iclass 40, count 0 2006.257.05:59:32.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.05:59:32.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.05:59:32.57#ibcon#*before write, iclass 40, count 0 2006.257.05:59:32.57#ibcon#enter sib2, iclass 40, count 0 2006.257.05:59:32.57#ibcon#flushed, iclass 40, count 0 2006.257.05:59:32.57#ibcon#about to write, iclass 40, count 0 2006.257.05:59:32.57#ibcon#wrote, iclass 40, count 0 2006.257.05:59:32.57#ibcon#about to read 3, iclass 40, count 0 2006.257.05:59:32.61#ibcon#read 3, iclass 40, count 0 2006.257.05:59:32.61#ibcon#about to read 4, iclass 40, count 0 2006.257.05:59:32.61#ibcon#read 4, iclass 40, count 0 2006.257.05:59:32.61#ibcon#about to read 5, iclass 40, count 0 2006.257.05:59:32.61#ibcon#read 5, iclass 40, count 0 2006.257.05:59:32.61#ibcon#about to read 6, iclass 40, count 0 2006.257.05:59:32.61#ibcon#read 6, iclass 40, count 0 2006.257.05:59:32.61#ibcon#end of sib2, iclass 40, count 0 2006.257.05:59:32.61#ibcon#*after write, iclass 40, count 0 2006.257.05:59:32.61#ibcon#*before return 0, iclass 40, count 0 2006.257.05:59:32.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:32.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.05:59:32.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.05:59:32.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.05:59:32.61$vck44/vb=3,4 2006.257.05:59:32.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.05:59:32.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.05:59:32.61#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:32.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:32.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:32.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:32.67#ibcon#enter wrdev, iclass 4, count 2 2006.257.05:59:32.67#ibcon#first serial, iclass 4, count 2 2006.257.05:59:32.67#ibcon#enter sib2, iclass 4, count 2 2006.257.05:59:32.67#ibcon#flushed, iclass 4, count 2 2006.257.05:59:32.67#ibcon#about to write, iclass 4, count 2 2006.257.05:59:32.67#ibcon#wrote, iclass 4, count 2 2006.257.05:59:32.67#ibcon#about to read 3, iclass 4, count 2 2006.257.05:59:32.69#ibcon#read 3, iclass 4, count 2 2006.257.05:59:32.69#ibcon#about to read 4, iclass 4, count 2 2006.257.05:59:32.69#ibcon#read 4, iclass 4, count 2 2006.257.05:59:32.69#ibcon#about to read 5, iclass 4, count 2 2006.257.05:59:32.69#ibcon#read 5, iclass 4, count 2 2006.257.05:59:32.69#ibcon#about to read 6, iclass 4, count 2 2006.257.05:59:32.69#ibcon#read 6, iclass 4, count 2 2006.257.05:59:32.69#ibcon#end of sib2, iclass 4, count 2 2006.257.05:59:32.69#ibcon#*mode == 0, iclass 4, count 2 2006.257.05:59:32.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.05:59:32.69#ibcon#[27=AT03-04\r\n] 2006.257.05:59:32.69#ibcon#*before write, iclass 4, count 2 2006.257.05:59:32.69#ibcon#enter sib2, iclass 4, count 2 2006.257.05:59:32.69#ibcon#flushed, iclass 4, count 2 2006.257.05:59:32.69#ibcon#about to write, iclass 4, count 2 2006.257.05:59:32.69#ibcon#wrote, iclass 4, count 2 2006.257.05:59:32.69#ibcon#about to read 3, iclass 4, count 2 2006.257.05:59:32.72#ibcon#read 3, iclass 4, count 2 2006.257.05:59:32.72#ibcon#about to read 4, iclass 4, count 2 2006.257.05:59:32.72#ibcon#read 4, iclass 4, count 2 2006.257.05:59:32.72#ibcon#about to read 5, iclass 4, count 2 2006.257.05:59:32.72#ibcon#read 5, iclass 4, count 2 2006.257.05:59:32.72#ibcon#about to read 6, iclass 4, count 2 2006.257.05:59:32.72#ibcon#read 6, iclass 4, count 2 2006.257.05:59:32.72#ibcon#end of sib2, iclass 4, count 2 2006.257.05:59:32.72#ibcon#*after write, iclass 4, count 2 2006.257.05:59:32.72#ibcon#*before return 0, iclass 4, count 2 2006.257.05:59:32.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:32.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.05:59:32.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.05:59:32.72#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:32.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:32.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:32.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:32.84#ibcon#enter wrdev, iclass 4, count 0 2006.257.05:59:32.84#ibcon#first serial, iclass 4, count 0 2006.257.05:59:32.84#ibcon#enter sib2, iclass 4, count 0 2006.257.05:59:32.84#ibcon#flushed, iclass 4, count 0 2006.257.05:59:32.84#ibcon#about to write, iclass 4, count 0 2006.257.05:59:32.84#ibcon#wrote, iclass 4, count 0 2006.257.05:59:32.84#ibcon#about to read 3, iclass 4, count 0 2006.257.05:59:32.86#ibcon#read 3, iclass 4, count 0 2006.257.05:59:32.86#ibcon#about to read 4, iclass 4, count 0 2006.257.05:59:32.86#ibcon#read 4, iclass 4, count 0 2006.257.05:59:32.86#ibcon#about to read 5, iclass 4, count 0 2006.257.05:59:32.86#ibcon#read 5, iclass 4, count 0 2006.257.05:59:32.86#ibcon#about to read 6, iclass 4, count 0 2006.257.05:59:32.86#ibcon#read 6, iclass 4, count 0 2006.257.05:59:32.86#ibcon#end of sib2, iclass 4, count 0 2006.257.05:59:32.86#ibcon#*mode == 0, iclass 4, count 0 2006.257.05:59:32.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.05:59:32.86#ibcon#[27=USB\r\n] 2006.257.05:59:32.86#ibcon#*before write, iclass 4, count 0 2006.257.05:59:32.86#ibcon#enter sib2, iclass 4, count 0 2006.257.05:59:32.86#ibcon#flushed, iclass 4, count 0 2006.257.05:59:32.86#ibcon#about to write, iclass 4, count 0 2006.257.05:59:32.86#ibcon#wrote, iclass 4, count 0 2006.257.05:59:32.86#ibcon#about to read 3, iclass 4, count 0 2006.257.05:59:32.89#ibcon#read 3, iclass 4, count 0 2006.257.05:59:32.89#ibcon#about to read 4, iclass 4, count 0 2006.257.05:59:32.89#ibcon#read 4, iclass 4, count 0 2006.257.05:59:32.89#ibcon#about to read 5, iclass 4, count 0 2006.257.05:59:32.89#ibcon#read 5, iclass 4, count 0 2006.257.05:59:32.89#ibcon#about to read 6, iclass 4, count 0 2006.257.05:59:32.89#ibcon#read 6, iclass 4, count 0 2006.257.05:59:32.89#ibcon#end of sib2, iclass 4, count 0 2006.257.05:59:32.89#ibcon#*after write, iclass 4, count 0 2006.257.05:59:32.89#ibcon#*before return 0, iclass 4, count 0 2006.257.05:59:32.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:32.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.05:59:32.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.05:59:32.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.05:59:32.89$vck44/vblo=4,679.99 2006.257.05:59:32.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.05:59:32.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.05:59:32.89#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:32.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:32.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:32.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:32.89#ibcon#enter wrdev, iclass 6, count 0 2006.257.05:59:32.89#ibcon#first serial, iclass 6, count 0 2006.257.05:59:32.89#ibcon#enter sib2, iclass 6, count 0 2006.257.05:59:32.89#ibcon#flushed, iclass 6, count 0 2006.257.05:59:32.89#ibcon#about to write, iclass 6, count 0 2006.257.05:59:32.89#ibcon#wrote, iclass 6, count 0 2006.257.05:59:32.89#ibcon#about to read 3, iclass 6, count 0 2006.257.05:59:32.91#ibcon#read 3, iclass 6, count 0 2006.257.05:59:32.91#ibcon#about to read 4, iclass 6, count 0 2006.257.05:59:32.91#ibcon#read 4, iclass 6, count 0 2006.257.05:59:32.91#ibcon#about to read 5, iclass 6, count 0 2006.257.05:59:32.91#ibcon#read 5, iclass 6, count 0 2006.257.05:59:32.91#ibcon#about to read 6, iclass 6, count 0 2006.257.05:59:32.91#ibcon#read 6, iclass 6, count 0 2006.257.05:59:32.91#ibcon#end of sib2, iclass 6, count 0 2006.257.05:59:32.91#ibcon#*mode == 0, iclass 6, count 0 2006.257.05:59:32.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.05:59:32.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.05:59:32.91#ibcon#*before write, iclass 6, count 0 2006.257.05:59:32.91#ibcon#enter sib2, iclass 6, count 0 2006.257.05:59:32.91#ibcon#flushed, iclass 6, count 0 2006.257.05:59:32.91#ibcon#about to write, iclass 6, count 0 2006.257.05:59:32.91#ibcon#wrote, iclass 6, count 0 2006.257.05:59:32.91#ibcon#about to read 3, iclass 6, count 0 2006.257.05:59:32.95#ibcon#read 3, iclass 6, count 0 2006.257.05:59:32.95#ibcon#about to read 4, iclass 6, count 0 2006.257.05:59:32.95#ibcon#read 4, iclass 6, count 0 2006.257.05:59:32.95#ibcon#about to read 5, iclass 6, count 0 2006.257.05:59:32.95#ibcon#read 5, iclass 6, count 0 2006.257.05:59:32.95#ibcon#about to read 6, iclass 6, count 0 2006.257.05:59:32.95#ibcon#read 6, iclass 6, count 0 2006.257.05:59:32.95#ibcon#end of sib2, iclass 6, count 0 2006.257.05:59:32.95#ibcon#*after write, iclass 6, count 0 2006.257.05:59:32.95#ibcon#*before return 0, iclass 6, count 0 2006.257.05:59:32.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:32.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.05:59:32.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.05:59:32.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.05:59:32.95$vck44/vb=4,5 2006.257.05:59:32.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.05:59:32.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.05:59:32.95#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:32.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:33.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:33.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:33.01#ibcon#enter wrdev, iclass 10, count 2 2006.257.05:59:33.01#ibcon#first serial, iclass 10, count 2 2006.257.05:59:33.01#ibcon#enter sib2, iclass 10, count 2 2006.257.05:59:33.01#ibcon#flushed, iclass 10, count 2 2006.257.05:59:33.01#ibcon#about to write, iclass 10, count 2 2006.257.05:59:33.01#ibcon#wrote, iclass 10, count 2 2006.257.05:59:33.01#ibcon#about to read 3, iclass 10, count 2 2006.257.05:59:33.03#ibcon#read 3, iclass 10, count 2 2006.257.05:59:33.03#ibcon#about to read 4, iclass 10, count 2 2006.257.05:59:33.03#ibcon#read 4, iclass 10, count 2 2006.257.05:59:33.03#ibcon#about to read 5, iclass 10, count 2 2006.257.05:59:33.03#ibcon#read 5, iclass 10, count 2 2006.257.05:59:33.03#ibcon#about to read 6, iclass 10, count 2 2006.257.05:59:33.03#ibcon#read 6, iclass 10, count 2 2006.257.05:59:33.03#ibcon#end of sib2, iclass 10, count 2 2006.257.05:59:33.03#ibcon#*mode == 0, iclass 10, count 2 2006.257.05:59:33.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.05:59:33.03#ibcon#[27=AT04-05\r\n] 2006.257.05:59:33.03#ibcon#*before write, iclass 10, count 2 2006.257.05:59:33.03#ibcon#enter sib2, iclass 10, count 2 2006.257.05:59:33.03#ibcon#flushed, iclass 10, count 2 2006.257.05:59:33.03#ibcon#about to write, iclass 10, count 2 2006.257.05:59:33.03#ibcon#wrote, iclass 10, count 2 2006.257.05:59:33.03#ibcon#about to read 3, iclass 10, count 2 2006.257.05:59:33.06#ibcon#read 3, iclass 10, count 2 2006.257.05:59:33.06#ibcon#about to read 4, iclass 10, count 2 2006.257.05:59:33.06#ibcon#read 4, iclass 10, count 2 2006.257.05:59:33.06#ibcon#about to read 5, iclass 10, count 2 2006.257.05:59:33.06#ibcon#read 5, iclass 10, count 2 2006.257.05:59:33.06#ibcon#about to read 6, iclass 10, count 2 2006.257.05:59:33.06#ibcon#read 6, iclass 10, count 2 2006.257.05:59:33.06#ibcon#end of sib2, iclass 10, count 2 2006.257.05:59:33.06#ibcon#*after write, iclass 10, count 2 2006.257.05:59:33.06#ibcon#*before return 0, iclass 10, count 2 2006.257.05:59:33.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:33.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.05:59:33.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.05:59:33.06#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:33.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:33.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:33.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:33.18#ibcon#enter wrdev, iclass 10, count 0 2006.257.05:59:33.18#ibcon#first serial, iclass 10, count 0 2006.257.05:59:33.18#ibcon#enter sib2, iclass 10, count 0 2006.257.05:59:33.18#ibcon#flushed, iclass 10, count 0 2006.257.05:59:33.18#ibcon#about to write, iclass 10, count 0 2006.257.05:59:33.18#ibcon#wrote, iclass 10, count 0 2006.257.05:59:33.18#ibcon#about to read 3, iclass 10, count 0 2006.257.05:59:33.20#ibcon#read 3, iclass 10, count 0 2006.257.05:59:33.20#ibcon#about to read 4, iclass 10, count 0 2006.257.05:59:33.20#ibcon#read 4, iclass 10, count 0 2006.257.05:59:33.20#ibcon#about to read 5, iclass 10, count 0 2006.257.05:59:33.20#ibcon#read 5, iclass 10, count 0 2006.257.05:59:33.20#ibcon#about to read 6, iclass 10, count 0 2006.257.05:59:33.20#ibcon#read 6, iclass 10, count 0 2006.257.05:59:33.20#ibcon#end of sib2, iclass 10, count 0 2006.257.05:59:33.20#ibcon#*mode == 0, iclass 10, count 0 2006.257.05:59:33.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.05:59:33.20#ibcon#[27=USB\r\n] 2006.257.05:59:33.20#ibcon#*before write, iclass 10, count 0 2006.257.05:59:33.20#ibcon#enter sib2, iclass 10, count 0 2006.257.05:59:33.20#ibcon#flushed, iclass 10, count 0 2006.257.05:59:33.20#ibcon#about to write, iclass 10, count 0 2006.257.05:59:33.20#ibcon#wrote, iclass 10, count 0 2006.257.05:59:33.20#ibcon#about to read 3, iclass 10, count 0 2006.257.05:59:33.23#ibcon#read 3, iclass 10, count 0 2006.257.05:59:33.23#ibcon#about to read 4, iclass 10, count 0 2006.257.05:59:33.23#ibcon#read 4, iclass 10, count 0 2006.257.05:59:33.23#ibcon#about to read 5, iclass 10, count 0 2006.257.05:59:33.23#ibcon#read 5, iclass 10, count 0 2006.257.05:59:33.23#ibcon#about to read 6, iclass 10, count 0 2006.257.05:59:33.23#ibcon#read 6, iclass 10, count 0 2006.257.05:59:33.23#ibcon#end of sib2, iclass 10, count 0 2006.257.05:59:33.23#ibcon#*after write, iclass 10, count 0 2006.257.05:59:33.23#ibcon#*before return 0, iclass 10, count 0 2006.257.05:59:33.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:33.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.05:59:33.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.05:59:33.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.05:59:33.23$vck44/vblo=5,709.99 2006.257.05:59:33.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.05:59:33.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.05:59:33.23#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:33.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:33.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:33.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:33.23#ibcon#enter wrdev, iclass 12, count 0 2006.257.05:59:33.23#ibcon#first serial, iclass 12, count 0 2006.257.05:59:33.23#ibcon#enter sib2, iclass 12, count 0 2006.257.05:59:33.23#ibcon#flushed, iclass 12, count 0 2006.257.05:59:33.23#ibcon#about to write, iclass 12, count 0 2006.257.05:59:33.23#ibcon#wrote, iclass 12, count 0 2006.257.05:59:33.23#ibcon#about to read 3, iclass 12, count 0 2006.257.05:59:33.25#ibcon#read 3, iclass 12, count 0 2006.257.05:59:33.25#ibcon#about to read 4, iclass 12, count 0 2006.257.05:59:33.25#ibcon#read 4, iclass 12, count 0 2006.257.05:59:33.25#ibcon#about to read 5, iclass 12, count 0 2006.257.05:59:33.25#ibcon#read 5, iclass 12, count 0 2006.257.05:59:33.25#ibcon#about to read 6, iclass 12, count 0 2006.257.05:59:33.25#ibcon#read 6, iclass 12, count 0 2006.257.05:59:33.25#ibcon#end of sib2, iclass 12, count 0 2006.257.05:59:33.25#ibcon#*mode == 0, iclass 12, count 0 2006.257.05:59:33.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.05:59:33.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.05:59:33.25#ibcon#*before write, iclass 12, count 0 2006.257.05:59:33.25#ibcon#enter sib2, iclass 12, count 0 2006.257.05:59:33.25#ibcon#flushed, iclass 12, count 0 2006.257.05:59:33.25#ibcon#about to write, iclass 12, count 0 2006.257.05:59:33.25#ibcon#wrote, iclass 12, count 0 2006.257.05:59:33.25#ibcon#about to read 3, iclass 12, count 0 2006.257.05:59:33.29#ibcon#read 3, iclass 12, count 0 2006.257.05:59:33.29#ibcon#about to read 4, iclass 12, count 0 2006.257.05:59:33.29#ibcon#read 4, iclass 12, count 0 2006.257.05:59:33.29#ibcon#about to read 5, iclass 12, count 0 2006.257.05:59:33.29#ibcon#read 5, iclass 12, count 0 2006.257.05:59:33.29#ibcon#about to read 6, iclass 12, count 0 2006.257.05:59:33.29#ibcon#read 6, iclass 12, count 0 2006.257.05:59:33.29#ibcon#end of sib2, iclass 12, count 0 2006.257.05:59:33.29#ibcon#*after write, iclass 12, count 0 2006.257.05:59:33.29#ibcon#*before return 0, iclass 12, count 0 2006.257.05:59:33.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:33.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.05:59:33.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.05:59:33.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.05:59:33.29$vck44/vb=5,4 2006.257.05:59:33.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.05:59:33.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.05:59:33.29#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:33.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:33.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:33.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:33.35#ibcon#enter wrdev, iclass 14, count 2 2006.257.05:59:33.35#ibcon#first serial, iclass 14, count 2 2006.257.05:59:33.35#ibcon#enter sib2, iclass 14, count 2 2006.257.05:59:33.35#ibcon#flushed, iclass 14, count 2 2006.257.05:59:33.35#ibcon#about to write, iclass 14, count 2 2006.257.05:59:33.35#ibcon#wrote, iclass 14, count 2 2006.257.05:59:33.35#ibcon#about to read 3, iclass 14, count 2 2006.257.05:59:33.37#ibcon#read 3, iclass 14, count 2 2006.257.05:59:33.37#ibcon#about to read 4, iclass 14, count 2 2006.257.05:59:33.37#ibcon#read 4, iclass 14, count 2 2006.257.05:59:33.37#ibcon#about to read 5, iclass 14, count 2 2006.257.05:59:33.37#ibcon#read 5, iclass 14, count 2 2006.257.05:59:33.37#ibcon#about to read 6, iclass 14, count 2 2006.257.05:59:33.37#ibcon#read 6, iclass 14, count 2 2006.257.05:59:33.37#ibcon#end of sib2, iclass 14, count 2 2006.257.05:59:33.37#ibcon#*mode == 0, iclass 14, count 2 2006.257.05:59:33.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.05:59:33.37#ibcon#[27=AT05-04\r\n] 2006.257.05:59:33.37#ibcon#*before write, iclass 14, count 2 2006.257.05:59:33.37#ibcon#enter sib2, iclass 14, count 2 2006.257.05:59:33.37#ibcon#flushed, iclass 14, count 2 2006.257.05:59:33.37#ibcon#about to write, iclass 14, count 2 2006.257.05:59:33.37#ibcon#wrote, iclass 14, count 2 2006.257.05:59:33.37#ibcon#about to read 3, iclass 14, count 2 2006.257.05:59:33.40#ibcon#read 3, iclass 14, count 2 2006.257.05:59:33.40#ibcon#about to read 4, iclass 14, count 2 2006.257.05:59:33.40#ibcon#read 4, iclass 14, count 2 2006.257.05:59:33.40#ibcon#about to read 5, iclass 14, count 2 2006.257.05:59:33.40#ibcon#read 5, iclass 14, count 2 2006.257.05:59:33.40#ibcon#about to read 6, iclass 14, count 2 2006.257.05:59:33.40#ibcon#read 6, iclass 14, count 2 2006.257.05:59:33.40#ibcon#end of sib2, iclass 14, count 2 2006.257.05:59:33.40#ibcon#*after write, iclass 14, count 2 2006.257.05:59:33.40#ibcon#*before return 0, iclass 14, count 2 2006.257.05:59:33.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:33.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.05:59:33.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.05:59:33.40#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:33.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:33.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:33.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:33.52#ibcon#enter wrdev, iclass 14, count 0 2006.257.05:59:33.52#ibcon#first serial, iclass 14, count 0 2006.257.05:59:33.52#ibcon#enter sib2, iclass 14, count 0 2006.257.05:59:33.52#ibcon#flushed, iclass 14, count 0 2006.257.05:59:33.52#ibcon#about to write, iclass 14, count 0 2006.257.05:59:33.52#ibcon#wrote, iclass 14, count 0 2006.257.05:59:33.52#ibcon#about to read 3, iclass 14, count 0 2006.257.05:59:33.54#ibcon#read 3, iclass 14, count 0 2006.257.05:59:33.54#ibcon#about to read 4, iclass 14, count 0 2006.257.05:59:33.54#ibcon#read 4, iclass 14, count 0 2006.257.05:59:33.54#ibcon#about to read 5, iclass 14, count 0 2006.257.05:59:33.54#ibcon#read 5, iclass 14, count 0 2006.257.05:59:33.54#ibcon#about to read 6, iclass 14, count 0 2006.257.05:59:33.54#ibcon#read 6, iclass 14, count 0 2006.257.05:59:33.54#ibcon#end of sib2, iclass 14, count 0 2006.257.05:59:33.54#ibcon#*mode == 0, iclass 14, count 0 2006.257.05:59:33.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.05:59:33.54#ibcon#[27=USB\r\n] 2006.257.05:59:33.54#ibcon#*before write, iclass 14, count 0 2006.257.05:59:33.54#ibcon#enter sib2, iclass 14, count 0 2006.257.05:59:33.54#ibcon#flushed, iclass 14, count 0 2006.257.05:59:33.54#ibcon#about to write, iclass 14, count 0 2006.257.05:59:33.54#ibcon#wrote, iclass 14, count 0 2006.257.05:59:33.54#ibcon#about to read 3, iclass 14, count 0 2006.257.05:59:33.57#ibcon#read 3, iclass 14, count 0 2006.257.05:59:33.57#ibcon#about to read 4, iclass 14, count 0 2006.257.05:59:33.57#ibcon#read 4, iclass 14, count 0 2006.257.05:59:33.57#ibcon#about to read 5, iclass 14, count 0 2006.257.05:59:33.57#ibcon#read 5, iclass 14, count 0 2006.257.05:59:33.57#ibcon#about to read 6, iclass 14, count 0 2006.257.05:59:33.57#ibcon#read 6, iclass 14, count 0 2006.257.05:59:33.57#ibcon#end of sib2, iclass 14, count 0 2006.257.05:59:33.57#ibcon#*after write, iclass 14, count 0 2006.257.05:59:33.57#ibcon#*before return 0, iclass 14, count 0 2006.257.05:59:33.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:33.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.05:59:33.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.05:59:33.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.05:59:33.57$vck44/vblo=6,719.99 2006.257.05:59:33.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.05:59:33.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.05:59:33.57#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:33.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:33.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:33.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:33.57#ibcon#enter wrdev, iclass 16, count 0 2006.257.05:59:33.57#ibcon#first serial, iclass 16, count 0 2006.257.05:59:33.57#ibcon#enter sib2, iclass 16, count 0 2006.257.05:59:33.57#ibcon#flushed, iclass 16, count 0 2006.257.05:59:33.57#ibcon#about to write, iclass 16, count 0 2006.257.05:59:33.57#ibcon#wrote, iclass 16, count 0 2006.257.05:59:33.57#ibcon#about to read 3, iclass 16, count 0 2006.257.05:59:33.59#ibcon#read 3, iclass 16, count 0 2006.257.05:59:33.59#ibcon#about to read 4, iclass 16, count 0 2006.257.05:59:33.59#ibcon#read 4, iclass 16, count 0 2006.257.05:59:33.59#ibcon#about to read 5, iclass 16, count 0 2006.257.05:59:33.59#ibcon#read 5, iclass 16, count 0 2006.257.05:59:33.59#ibcon#about to read 6, iclass 16, count 0 2006.257.05:59:33.59#ibcon#read 6, iclass 16, count 0 2006.257.05:59:33.59#ibcon#end of sib2, iclass 16, count 0 2006.257.05:59:33.59#ibcon#*mode == 0, iclass 16, count 0 2006.257.05:59:33.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.05:59:33.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.05:59:33.59#ibcon#*before write, iclass 16, count 0 2006.257.05:59:33.59#ibcon#enter sib2, iclass 16, count 0 2006.257.05:59:33.59#ibcon#flushed, iclass 16, count 0 2006.257.05:59:33.59#ibcon#about to write, iclass 16, count 0 2006.257.05:59:33.59#ibcon#wrote, iclass 16, count 0 2006.257.05:59:33.59#ibcon#about to read 3, iclass 16, count 0 2006.257.05:59:33.63#ibcon#read 3, iclass 16, count 0 2006.257.05:59:33.63#ibcon#about to read 4, iclass 16, count 0 2006.257.05:59:33.63#ibcon#read 4, iclass 16, count 0 2006.257.05:59:33.63#ibcon#about to read 5, iclass 16, count 0 2006.257.05:59:33.63#ibcon#read 5, iclass 16, count 0 2006.257.05:59:33.63#ibcon#about to read 6, iclass 16, count 0 2006.257.05:59:33.63#ibcon#read 6, iclass 16, count 0 2006.257.05:59:33.63#ibcon#end of sib2, iclass 16, count 0 2006.257.05:59:33.63#ibcon#*after write, iclass 16, count 0 2006.257.05:59:33.63#ibcon#*before return 0, iclass 16, count 0 2006.257.05:59:33.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:33.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.05:59:33.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.05:59:33.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.05:59:33.63$vck44/vb=6,4 2006.257.05:59:33.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.05:59:33.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.05:59:33.63#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:33.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:33.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:33.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:33.69#ibcon#enter wrdev, iclass 18, count 2 2006.257.05:59:33.69#ibcon#first serial, iclass 18, count 2 2006.257.05:59:33.69#ibcon#enter sib2, iclass 18, count 2 2006.257.05:59:33.69#ibcon#flushed, iclass 18, count 2 2006.257.05:59:33.69#ibcon#about to write, iclass 18, count 2 2006.257.05:59:33.69#ibcon#wrote, iclass 18, count 2 2006.257.05:59:33.69#ibcon#about to read 3, iclass 18, count 2 2006.257.05:59:33.71#ibcon#read 3, iclass 18, count 2 2006.257.05:59:33.71#ibcon#about to read 4, iclass 18, count 2 2006.257.05:59:33.71#ibcon#read 4, iclass 18, count 2 2006.257.05:59:33.71#ibcon#about to read 5, iclass 18, count 2 2006.257.05:59:33.71#ibcon#read 5, iclass 18, count 2 2006.257.05:59:33.71#ibcon#about to read 6, iclass 18, count 2 2006.257.05:59:33.71#ibcon#read 6, iclass 18, count 2 2006.257.05:59:33.71#ibcon#end of sib2, iclass 18, count 2 2006.257.05:59:33.71#ibcon#*mode == 0, iclass 18, count 2 2006.257.05:59:33.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.05:59:33.71#ibcon#[27=AT06-04\r\n] 2006.257.05:59:33.71#ibcon#*before write, iclass 18, count 2 2006.257.05:59:33.71#ibcon#enter sib2, iclass 18, count 2 2006.257.05:59:33.71#ibcon#flushed, iclass 18, count 2 2006.257.05:59:33.71#ibcon#about to write, iclass 18, count 2 2006.257.05:59:33.71#ibcon#wrote, iclass 18, count 2 2006.257.05:59:33.71#ibcon#about to read 3, iclass 18, count 2 2006.257.05:59:33.74#ibcon#read 3, iclass 18, count 2 2006.257.05:59:33.74#ibcon#about to read 4, iclass 18, count 2 2006.257.05:59:33.74#ibcon#read 4, iclass 18, count 2 2006.257.05:59:33.74#ibcon#about to read 5, iclass 18, count 2 2006.257.05:59:33.74#ibcon#read 5, iclass 18, count 2 2006.257.05:59:33.74#ibcon#about to read 6, iclass 18, count 2 2006.257.05:59:33.74#ibcon#read 6, iclass 18, count 2 2006.257.05:59:33.74#ibcon#end of sib2, iclass 18, count 2 2006.257.05:59:33.74#ibcon#*after write, iclass 18, count 2 2006.257.05:59:33.74#ibcon#*before return 0, iclass 18, count 2 2006.257.05:59:33.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:33.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.05:59:33.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.05:59:33.74#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:33.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:33.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:33.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:33.86#ibcon#enter wrdev, iclass 18, count 0 2006.257.05:59:33.86#ibcon#first serial, iclass 18, count 0 2006.257.05:59:33.86#ibcon#enter sib2, iclass 18, count 0 2006.257.05:59:33.86#ibcon#flushed, iclass 18, count 0 2006.257.05:59:33.86#ibcon#about to write, iclass 18, count 0 2006.257.05:59:33.86#ibcon#wrote, iclass 18, count 0 2006.257.05:59:33.86#ibcon#about to read 3, iclass 18, count 0 2006.257.05:59:33.88#ibcon#read 3, iclass 18, count 0 2006.257.05:59:33.88#ibcon#about to read 4, iclass 18, count 0 2006.257.05:59:33.88#ibcon#read 4, iclass 18, count 0 2006.257.05:59:33.88#ibcon#about to read 5, iclass 18, count 0 2006.257.05:59:33.88#ibcon#read 5, iclass 18, count 0 2006.257.05:59:33.88#ibcon#about to read 6, iclass 18, count 0 2006.257.05:59:33.88#ibcon#read 6, iclass 18, count 0 2006.257.05:59:33.88#ibcon#end of sib2, iclass 18, count 0 2006.257.05:59:33.88#ibcon#*mode == 0, iclass 18, count 0 2006.257.05:59:33.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.05:59:33.88#ibcon#[27=USB\r\n] 2006.257.05:59:33.88#ibcon#*before write, iclass 18, count 0 2006.257.05:59:33.88#ibcon#enter sib2, iclass 18, count 0 2006.257.05:59:33.88#ibcon#flushed, iclass 18, count 0 2006.257.05:59:33.88#ibcon#about to write, iclass 18, count 0 2006.257.05:59:33.88#ibcon#wrote, iclass 18, count 0 2006.257.05:59:33.88#ibcon#about to read 3, iclass 18, count 0 2006.257.05:59:33.91#ibcon#read 3, iclass 18, count 0 2006.257.05:59:33.91#ibcon#about to read 4, iclass 18, count 0 2006.257.05:59:33.91#ibcon#read 4, iclass 18, count 0 2006.257.05:59:33.91#ibcon#about to read 5, iclass 18, count 0 2006.257.05:59:33.91#ibcon#read 5, iclass 18, count 0 2006.257.05:59:33.91#ibcon#about to read 6, iclass 18, count 0 2006.257.05:59:33.91#ibcon#read 6, iclass 18, count 0 2006.257.05:59:33.91#ibcon#end of sib2, iclass 18, count 0 2006.257.05:59:33.91#ibcon#*after write, iclass 18, count 0 2006.257.05:59:33.91#ibcon#*before return 0, iclass 18, count 0 2006.257.05:59:33.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:33.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.05:59:33.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.05:59:33.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.05:59:33.91$vck44/vblo=7,734.99 2006.257.05:59:33.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.05:59:33.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.05:59:33.91#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:33.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:59:33.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:59:33.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:59:33.91#ibcon#enter wrdev, iclass 20, count 0 2006.257.05:59:33.91#ibcon#first serial, iclass 20, count 0 2006.257.05:59:33.91#ibcon#enter sib2, iclass 20, count 0 2006.257.05:59:33.91#ibcon#flushed, iclass 20, count 0 2006.257.05:59:33.91#ibcon#about to write, iclass 20, count 0 2006.257.05:59:33.91#ibcon#wrote, iclass 20, count 0 2006.257.05:59:33.91#ibcon#about to read 3, iclass 20, count 0 2006.257.05:59:33.93#ibcon#read 3, iclass 20, count 0 2006.257.05:59:33.93#ibcon#about to read 4, iclass 20, count 0 2006.257.05:59:33.93#ibcon#read 4, iclass 20, count 0 2006.257.05:59:33.93#ibcon#about to read 5, iclass 20, count 0 2006.257.05:59:33.93#ibcon#read 5, iclass 20, count 0 2006.257.05:59:33.93#ibcon#about to read 6, iclass 20, count 0 2006.257.05:59:33.93#ibcon#read 6, iclass 20, count 0 2006.257.05:59:33.93#ibcon#end of sib2, iclass 20, count 0 2006.257.05:59:33.93#ibcon#*mode == 0, iclass 20, count 0 2006.257.05:59:33.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.05:59:33.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.05:59:33.93#ibcon#*before write, iclass 20, count 0 2006.257.05:59:33.93#ibcon#enter sib2, iclass 20, count 0 2006.257.05:59:33.93#ibcon#flushed, iclass 20, count 0 2006.257.05:59:33.93#ibcon#about to write, iclass 20, count 0 2006.257.05:59:33.93#ibcon#wrote, iclass 20, count 0 2006.257.05:59:33.93#ibcon#about to read 3, iclass 20, count 0 2006.257.05:59:33.97#ibcon#read 3, iclass 20, count 0 2006.257.05:59:33.97#ibcon#about to read 4, iclass 20, count 0 2006.257.05:59:33.97#ibcon#read 4, iclass 20, count 0 2006.257.05:59:33.97#ibcon#about to read 5, iclass 20, count 0 2006.257.05:59:33.97#ibcon#read 5, iclass 20, count 0 2006.257.05:59:33.97#ibcon#about to read 6, iclass 20, count 0 2006.257.05:59:33.97#ibcon#read 6, iclass 20, count 0 2006.257.05:59:33.97#ibcon#end of sib2, iclass 20, count 0 2006.257.05:59:33.97#ibcon#*after write, iclass 20, count 0 2006.257.05:59:33.97#ibcon#*before return 0, iclass 20, count 0 2006.257.05:59:33.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:59:33.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.05:59:33.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.05:59:33.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.05:59:33.97$vck44/vb=7,4 2006.257.05:59:33.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.05:59:33.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.05:59:33.97#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:33.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:59:34.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:59:34.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:59:34.03#ibcon#enter wrdev, iclass 22, count 2 2006.257.05:59:34.03#ibcon#first serial, iclass 22, count 2 2006.257.05:59:34.03#ibcon#enter sib2, iclass 22, count 2 2006.257.05:59:34.03#ibcon#flushed, iclass 22, count 2 2006.257.05:59:34.03#ibcon#about to write, iclass 22, count 2 2006.257.05:59:34.03#ibcon#wrote, iclass 22, count 2 2006.257.05:59:34.03#ibcon#about to read 3, iclass 22, count 2 2006.257.05:59:34.05#ibcon#read 3, iclass 22, count 2 2006.257.05:59:34.05#ibcon#about to read 4, iclass 22, count 2 2006.257.05:59:34.05#ibcon#read 4, iclass 22, count 2 2006.257.05:59:34.05#ibcon#about to read 5, iclass 22, count 2 2006.257.05:59:34.05#ibcon#read 5, iclass 22, count 2 2006.257.05:59:34.05#ibcon#about to read 6, iclass 22, count 2 2006.257.05:59:34.05#ibcon#read 6, iclass 22, count 2 2006.257.05:59:34.05#ibcon#end of sib2, iclass 22, count 2 2006.257.05:59:34.05#ibcon#*mode == 0, iclass 22, count 2 2006.257.05:59:34.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.05:59:34.05#ibcon#[27=AT07-04\r\n] 2006.257.05:59:34.05#ibcon#*before write, iclass 22, count 2 2006.257.05:59:34.05#ibcon#enter sib2, iclass 22, count 2 2006.257.05:59:34.05#ibcon#flushed, iclass 22, count 2 2006.257.05:59:34.05#ibcon#about to write, iclass 22, count 2 2006.257.05:59:34.05#ibcon#wrote, iclass 22, count 2 2006.257.05:59:34.05#ibcon#about to read 3, iclass 22, count 2 2006.257.05:59:34.08#ibcon#read 3, iclass 22, count 2 2006.257.05:59:34.08#ibcon#about to read 4, iclass 22, count 2 2006.257.05:59:34.08#ibcon#read 4, iclass 22, count 2 2006.257.05:59:34.08#ibcon#about to read 5, iclass 22, count 2 2006.257.05:59:34.08#ibcon#read 5, iclass 22, count 2 2006.257.05:59:34.08#ibcon#about to read 6, iclass 22, count 2 2006.257.05:59:34.08#ibcon#read 6, iclass 22, count 2 2006.257.05:59:34.08#ibcon#end of sib2, iclass 22, count 2 2006.257.05:59:34.08#ibcon#*after write, iclass 22, count 2 2006.257.05:59:34.08#ibcon#*before return 0, iclass 22, count 2 2006.257.05:59:34.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:59:34.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.05:59:34.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.05:59:34.08#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:34.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:59:34.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:59:34.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:59:34.20#ibcon#enter wrdev, iclass 22, count 0 2006.257.05:59:34.20#ibcon#first serial, iclass 22, count 0 2006.257.05:59:34.20#ibcon#enter sib2, iclass 22, count 0 2006.257.05:59:34.20#ibcon#flushed, iclass 22, count 0 2006.257.05:59:34.20#ibcon#about to write, iclass 22, count 0 2006.257.05:59:34.20#ibcon#wrote, iclass 22, count 0 2006.257.05:59:34.20#ibcon#about to read 3, iclass 22, count 0 2006.257.05:59:34.22#ibcon#read 3, iclass 22, count 0 2006.257.05:59:34.22#ibcon#about to read 4, iclass 22, count 0 2006.257.05:59:34.22#ibcon#read 4, iclass 22, count 0 2006.257.05:59:34.22#ibcon#about to read 5, iclass 22, count 0 2006.257.05:59:34.22#ibcon#read 5, iclass 22, count 0 2006.257.05:59:34.22#ibcon#about to read 6, iclass 22, count 0 2006.257.05:59:34.22#ibcon#read 6, iclass 22, count 0 2006.257.05:59:34.22#ibcon#end of sib2, iclass 22, count 0 2006.257.05:59:34.22#ibcon#*mode == 0, iclass 22, count 0 2006.257.05:59:34.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.05:59:34.22#ibcon#[27=USB\r\n] 2006.257.05:59:34.22#ibcon#*before write, iclass 22, count 0 2006.257.05:59:34.22#ibcon#enter sib2, iclass 22, count 0 2006.257.05:59:34.22#ibcon#flushed, iclass 22, count 0 2006.257.05:59:34.22#ibcon#about to write, iclass 22, count 0 2006.257.05:59:34.22#ibcon#wrote, iclass 22, count 0 2006.257.05:59:34.22#ibcon#about to read 3, iclass 22, count 0 2006.257.05:59:34.25#ibcon#read 3, iclass 22, count 0 2006.257.05:59:34.25#ibcon#about to read 4, iclass 22, count 0 2006.257.05:59:34.25#ibcon#read 4, iclass 22, count 0 2006.257.05:59:34.25#ibcon#about to read 5, iclass 22, count 0 2006.257.05:59:34.25#ibcon#read 5, iclass 22, count 0 2006.257.05:59:34.25#ibcon#about to read 6, iclass 22, count 0 2006.257.05:59:34.25#ibcon#read 6, iclass 22, count 0 2006.257.05:59:34.25#ibcon#end of sib2, iclass 22, count 0 2006.257.05:59:34.25#ibcon#*after write, iclass 22, count 0 2006.257.05:59:34.25#ibcon#*before return 0, iclass 22, count 0 2006.257.05:59:34.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:59:34.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.05:59:34.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.05:59:34.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.05:59:34.25$vck44/vblo=8,744.99 2006.257.05:59:34.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.05:59:34.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.05:59:34.25#ibcon#ireg 17 cls_cnt 0 2006.257.05:59:34.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:34.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:34.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:34.25#ibcon#enter wrdev, iclass 24, count 0 2006.257.05:59:34.25#ibcon#first serial, iclass 24, count 0 2006.257.05:59:34.25#ibcon#enter sib2, iclass 24, count 0 2006.257.05:59:34.25#ibcon#flushed, iclass 24, count 0 2006.257.05:59:34.25#ibcon#about to write, iclass 24, count 0 2006.257.05:59:34.25#ibcon#wrote, iclass 24, count 0 2006.257.05:59:34.25#ibcon#about to read 3, iclass 24, count 0 2006.257.05:59:34.27#ibcon#read 3, iclass 24, count 0 2006.257.05:59:34.27#ibcon#about to read 4, iclass 24, count 0 2006.257.05:59:34.27#ibcon#read 4, iclass 24, count 0 2006.257.05:59:34.27#ibcon#about to read 5, iclass 24, count 0 2006.257.05:59:34.27#ibcon#read 5, iclass 24, count 0 2006.257.05:59:34.27#ibcon#about to read 6, iclass 24, count 0 2006.257.05:59:34.27#ibcon#read 6, iclass 24, count 0 2006.257.05:59:34.27#ibcon#end of sib2, iclass 24, count 0 2006.257.05:59:34.27#ibcon#*mode == 0, iclass 24, count 0 2006.257.05:59:34.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.05:59:34.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.05:59:34.27#ibcon#*before write, iclass 24, count 0 2006.257.05:59:34.27#ibcon#enter sib2, iclass 24, count 0 2006.257.05:59:34.27#ibcon#flushed, iclass 24, count 0 2006.257.05:59:34.27#ibcon#about to write, iclass 24, count 0 2006.257.05:59:34.27#ibcon#wrote, iclass 24, count 0 2006.257.05:59:34.27#ibcon#about to read 3, iclass 24, count 0 2006.257.05:59:34.31#ibcon#read 3, iclass 24, count 0 2006.257.05:59:34.31#ibcon#about to read 4, iclass 24, count 0 2006.257.05:59:34.31#ibcon#read 4, iclass 24, count 0 2006.257.05:59:34.31#ibcon#about to read 5, iclass 24, count 0 2006.257.05:59:34.31#ibcon#read 5, iclass 24, count 0 2006.257.05:59:34.31#ibcon#about to read 6, iclass 24, count 0 2006.257.05:59:34.31#ibcon#read 6, iclass 24, count 0 2006.257.05:59:34.31#ibcon#end of sib2, iclass 24, count 0 2006.257.05:59:34.31#ibcon#*after write, iclass 24, count 0 2006.257.05:59:34.31#ibcon#*before return 0, iclass 24, count 0 2006.257.05:59:34.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:34.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.05:59:34.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.05:59:34.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.05:59:34.31$vck44/vb=8,4 2006.257.05:59:34.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.05:59:34.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.05:59:34.31#ibcon#ireg 11 cls_cnt 2 2006.257.05:59:34.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:34.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:34.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:34.37#ibcon#enter wrdev, iclass 26, count 2 2006.257.05:59:34.37#ibcon#first serial, iclass 26, count 2 2006.257.05:59:34.37#ibcon#enter sib2, iclass 26, count 2 2006.257.05:59:34.37#ibcon#flushed, iclass 26, count 2 2006.257.05:59:34.37#ibcon#about to write, iclass 26, count 2 2006.257.05:59:34.37#ibcon#wrote, iclass 26, count 2 2006.257.05:59:34.37#ibcon#about to read 3, iclass 26, count 2 2006.257.05:59:34.39#ibcon#read 3, iclass 26, count 2 2006.257.05:59:34.39#ibcon#about to read 4, iclass 26, count 2 2006.257.05:59:34.39#ibcon#read 4, iclass 26, count 2 2006.257.05:59:34.39#ibcon#about to read 5, iclass 26, count 2 2006.257.05:59:34.39#ibcon#read 5, iclass 26, count 2 2006.257.05:59:34.39#ibcon#about to read 6, iclass 26, count 2 2006.257.05:59:34.39#ibcon#read 6, iclass 26, count 2 2006.257.05:59:34.39#ibcon#end of sib2, iclass 26, count 2 2006.257.05:59:34.39#ibcon#*mode == 0, iclass 26, count 2 2006.257.05:59:34.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.05:59:34.39#ibcon#[27=AT08-04\r\n] 2006.257.05:59:34.39#ibcon#*before write, iclass 26, count 2 2006.257.05:59:34.39#ibcon#enter sib2, iclass 26, count 2 2006.257.05:59:34.39#ibcon#flushed, iclass 26, count 2 2006.257.05:59:34.39#ibcon#about to write, iclass 26, count 2 2006.257.05:59:34.39#ibcon#wrote, iclass 26, count 2 2006.257.05:59:34.39#ibcon#about to read 3, iclass 26, count 2 2006.257.05:59:34.42#ibcon#read 3, iclass 26, count 2 2006.257.05:59:34.42#ibcon#about to read 4, iclass 26, count 2 2006.257.05:59:34.42#ibcon#read 4, iclass 26, count 2 2006.257.05:59:34.42#ibcon#about to read 5, iclass 26, count 2 2006.257.05:59:34.42#ibcon#read 5, iclass 26, count 2 2006.257.05:59:34.42#ibcon#about to read 6, iclass 26, count 2 2006.257.05:59:34.42#ibcon#read 6, iclass 26, count 2 2006.257.05:59:34.42#ibcon#end of sib2, iclass 26, count 2 2006.257.05:59:34.42#ibcon#*after write, iclass 26, count 2 2006.257.05:59:34.42#ibcon#*before return 0, iclass 26, count 2 2006.257.05:59:34.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:34.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.05:59:34.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.05:59:34.42#ibcon#ireg 7 cls_cnt 0 2006.257.05:59:34.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:34.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:34.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:34.54#ibcon#enter wrdev, iclass 26, count 0 2006.257.05:59:34.54#ibcon#first serial, iclass 26, count 0 2006.257.05:59:34.54#ibcon#enter sib2, iclass 26, count 0 2006.257.05:59:34.54#ibcon#flushed, iclass 26, count 0 2006.257.05:59:34.54#ibcon#about to write, iclass 26, count 0 2006.257.05:59:34.54#ibcon#wrote, iclass 26, count 0 2006.257.05:59:34.54#ibcon#about to read 3, iclass 26, count 0 2006.257.05:59:34.56#ibcon#read 3, iclass 26, count 0 2006.257.05:59:34.56#ibcon#about to read 4, iclass 26, count 0 2006.257.05:59:34.56#ibcon#read 4, iclass 26, count 0 2006.257.05:59:34.56#ibcon#about to read 5, iclass 26, count 0 2006.257.05:59:34.56#ibcon#read 5, iclass 26, count 0 2006.257.05:59:34.56#ibcon#about to read 6, iclass 26, count 0 2006.257.05:59:34.56#ibcon#read 6, iclass 26, count 0 2006.257.05:59:34.56#ibcon#end of sib2, iclass 26, count 0 2006.257.05:59:34.56#ibcon#*mode == 0, iclass 26, count 0 2006.257.05:59:34.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.05:59:34.56#ibcon#[27=USB\r\n] 2006.257.05:59:34.56#ibcon#*before write, iclass 26, count 0 2006.257.05:59:34.56#ibcon#enter sib2, iclass 26, count 0 2006.257.05:59:34.56#ibcon#flushed, iclass 26, count 0 2006.257.05:59:34.56#ibcon#about to write, iclass 26, count 0 2006.257.05:59:34.56#ibcon#wrote, iclass 26, count 0 2006.257.05:59:34.56#ibcon#about to read 3, iclass 26, count 0 2006.257.05:59:34.59#ibcon#read 3, iclass 26, count 0 2006.257.05:59:34.59#ibcon#about to read 4, iclass 26, count 0 2006.257.05:59:34.59#ibcon#read 4, iclass 26, count 0 2006.257.05:59:34.59#ibcon#about to read 5, iclass 26, count 0 2006.257.05:59:34.59#ibcon#read 5, iclass 26, count 0 2006.257.05:59:34.59#ibcon#about to read 6, iclass 26, count 0 2006.257.05:59:34.59#ibcon#read 6, iclass 26, count 0 2006.257.05:59:34.59#ibcon#end of sib2, iclass 26, count 0 2006.257.05:59:34.59#ibcon#*after write, iclass 26, count 0 2006.257.05:59:34.59#ibcon#*before return 0, iclass 26, count 0 2006.257.05:59:34.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:34.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.05:59:34.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.05:59:34.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.05:59:34.59$vck44/vabw=wide 2006.257.05:59:34.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.05:59:34.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.05:59:34.59#ibcon#ireg 8 cls_cnt 0 2006.257.05:59:34.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:34.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:34.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:34.59#ibcon#enter wrdev, iclass 28, count 0 2006.257.05:59:34.59#ibcon#first serial, iclass 28, count 0 2006.257.05:59:34.59#ibcon#enter sib2, iclass 28, count 0 2006.257.05:59:34.59#ibcon#flushed, iclass 28, count 0 2006.257.05:59:34.59#ibcon#about to write, iclass 28, count 0 2006.257.05:59:34.59#ibcon#wrote, iclass 28, count 0 2006.257.05:59:34.59#ibcon#about to read 3, iclass 28, count 0 2006.257.05:59:34.61#ibcon#read 3, iclass 28, count 0 2006.257.05:59:34.61#ibcon#about to read 4, iclass 28, count 0 2006.257.05:59:34.61#ibcon#read 4, iclass 28, count 0 2006.257.05:59:34.61#ibcon#about to read 5, iclass 28, count 0 2006.257.05:59:34.61#ibcon#read 5, iclass 28, count 0 2006.257.05:59:34.61#ibcon#about to read 6, iclass 28, count 0 2006.257.05:59:34.61#ibcon#read 6, iclass 28, count 0 2006.257.05:59:34.61#ibcon#end of sib2, iclass 28, count 0 2006.257.05:59:34.61#ibcon#*mode == 0, iclass 28, count 0 2006.257.05:59:34.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.05:59:34.61#ibcon#[25=BW32\r\n] 2006.257.05:59:34.61#ibcon#*before write, iclass 28, count 0 2006.257.05:59:34.61#ibcon#enter sib2, iclass 28, count 0 2006.257.05:59:34.61#ibcon#flushed, iclass 28, count 0 2006.257.05:59:34.61#ibcon#about to write, iclass 28, count 0 2006.257.05:59:34.61#ibcon#wrote, iclass 28, count 0 2006.257.05:59:34.61#ibcon#about to read 3, iclass 28, count 0 2006.257.05:59:34.64#ibcon#read 3, iclass 28, count 0 2006.257.05:59:34.64#ibcon#about to read 4, iclass 28, count 0 2006.257.05:59:34.64#ibcon#read 4, iclass 28, count 0 2006.257.05:59:34.64#ibcon#about to read 5, iclass 28, count 0 2006.257.05:59:34.64#ibcon#read 5, iclass 28, count 0 2006.257.05:59:34.64#ibcon#about to read 6, iclass 28, count 0 2006.257.05:59:34.64#ibcon#read 6, iclass 28, count 0 2006.257.05:59:34.64#ibcon#end of sib2, iclass 28, count 0 2006.257.05:59:34.64#ibcon#*after write, iclass 28, count 0 2006.257.05:59:34.64#ibcon#*before return 0, iclass 28, count 0 2006.257.05:59:34.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:34.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.05:59:34.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.05:59:34.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.05:59:34.64$vck44/vbbw=wide 2006.257.05:59:34.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.05:59:34.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.05:59:34.64#ibcon#ireg 8 cls_cnt 0 2006.257.05:59:34.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:59:34.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:59:34.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:59:34.71#ibcon#enter wrdev, iclass 30, count 0 2006.257.05:59:34.71#ibcon#first serial, iclass 30, count 0 2006.257.05:59:34.71#ibcon#enter sib2, iclass 30, count 0 2006.257.05:59:34.71#ibcon#flushed, iclass 30, count 0 2006.257.05:59:34.71#ibcon#about to write, iclass 30, count 0 2006.257.05:59:34.71#ibcon#wrote, iclass 30, count 0 2006.257.05:59:34.71#ibcon#about to read 3, iclass 30, count 0 2006.257.05:59:34.73#ibcon#read 3, iclass 30, count 0 2006.257.05:59:34.73#ibcon#about to read 4, iclass 30, count 0 2006.257.05:59:34.73#ibcon#read 4, iclass 30, count 0 2006.257.05:59:34.73#ibcon#about to read 5, iclass 30, count 0 2006.257.05:59:34.73#ibcon#read 5, iclass 30, count 0 2006.257.05:59:34.73#ibcon#about to read 6, iclass 30, count 0 2006.257.05:59:34.73#ibcon#read 6, iclass 30, count 0 2006.257.05:59:34.73#ibcon#end of sib2, iclass 30, count 0 2006.257.05:59:34.73#ibcon#*mode == 0, iclass 30, count 0 2006.257.05:59:34.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.05:59:34.73#ibcon#[27=BW32\r\n] 2006.257.05:59:34.73#ibcon#*before write, iclass 30, count 0 2006.257.05:59:34.73#ibcon#enter sib2, iclass 30, count 0 2006.257.05:59:34.73#ibcon#flushed, iclass 30, count 0 2006.257.05:59:34.73#ibcon#about to write, iclass 30, count 0 2006.257.05:59:34.73#ibcon#wrote, iclass 30, count 0 2006.257.05:59:34.73#ibcon#about to read 3, iclass 30, count 0 2006.257.05:59:34.76#ibcon#read 3, iclass 30, count 0 2006.257.05:59:34.76#ibcon#about to read 4, iclass 30, count 0 2006.257.05:59:34.76#ibcon#read 4, iclass 30, count 0 2006.257.05:59:34.76#ibcon#about to read 5, iclass 30, count 0 2006.257.05:59:34.76#ibcon#read 5, iclass 30, count 0 2006.257.05:59:34.76#ibcon#about to read 6, iclass 30, count 0 2006.257.05:59:34.76#ibcon#read 6, iclass 30, count 0 2006.257.05:59:34.76#ibcon#end of sib2, iclass 30, count 0 2006.257.05:59:34.76#ibcon#*after write, iclass 30, count 0 2006.257.05:59:34.76#ibcon#*before return 0, iclass 30, count 0 2006.257.05:59:34.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:59:34.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.05:59:34.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.05:59:34.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.05:59:34.76$setupk4/ifdk4 2006.257.05:59:34.76$ifdk4/lo= 2006.257.05:59:34.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.05:59:34.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.05:59:34.76$ifdk4/patch= 2006.257.05:59:34.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.05:59:34.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.05:59:34.76$setupk4/!*+20s 2006.257.05:59:41.29#abcon#<5=/16 1.4 4.7 20.13 881012.2\r\n> 2006.257.05:59:41.31#abcon#{5=INTERFACE CLEAR} 2006.257.05:59:41.37#abcon#[5=S1D000X0/0*\r\n] 2006.257.05:59:44.13#trakl#Source acquired 2006.257.05:59:45.13#flagr#flagr/antenna,acquired 2006.257.05:59:49.27$setupk4/"tpicd 2006.257.05:59:49.27$setupk4/echo=off 2006.257.05:59:49.27$setupk4/xlog=off 2006.257.05:59:49.27:!2006.257.05:59:57 2006.257.05:59:57.00:preob 2006.257.05:59:58.13/onsource/TRACKING 2006.257.05:59:58.13:!2006.257.06:00:07 2006.257.06:00:07.00:"tape 2006.257.06:00:07.00:"st=record 2006.257.06:00:07.00:data_valid=on 2006.257.06:00:07.00:midob 2006.257.06:00:07.13/onsource/TRACKING 2006.257.06:00:07.13/wx/20.13,1012.2,89 2006.257.06:00:07.28/cable/+6.4795E-03 2006.257.06:00:08.37/va/01,08,usb,yes,32,34 2006.257.06:00:08.37/va/02,07,usb,yes,35,35 2006.257.06:00:08.37/va/03,08,usb,yes,31,33 2006.257.06:00:08.37/va/04,07,usb,yes,36,37 2006.257.06:00:08.37/va/05,04,usb,yes,32,32 2006.257.06:00:08.37/va/06,04,usb,yes,36,35 2006.257.06:00:08.37/va/07,04,usb,yes,37,37 2006.257.06:00:08.37/va/08,04,usb,yes,30,37 2006.257.06:00:08.60/valo/01,524.99,yes,locked 2006.257.06:00:08.60/valo/02,534.99,yes,locked 2006.257.06:00:08.60/valo/03,564.99,yes,locked 2006.257.06:00:08.60/valo/04,624.99,yes,locked 2006.257.06:00:08.60/valo/05,734.99,yes,locked 2006.257.06:00:08.60/valo/06,814.99,yes,locked 2006.257.06:00:08.60/valo/07,864.99,yes,locked 2006.257.06:00:08.60/valo/08,884.99,yes,locked 2006.257.06:00:09.69/vb/01,04,usb,yes,31,29 2006.257.06:00:09.69/vb/02,05,usb,yes,29,29 2006.257.06:00:09.69/vb/03,04,usb,yes,30,33 2006.257.06:00:09.69/vb/04,05,usb,yes,30,29 2006.257.06:00:09.69/vb/05,04,usb,yes,27,29 2006.257.06:00:09.69/vb/06,04,usb,yes,31,27 2006.257.06:00:09.69/vb/07,04,usb,yes,31,31 2006.257.06:00:09.69/vb/08,04,usb,yes,28,32 2006.257.06:00:09.92/vblo/01,629.99,yes,locked 2006.257.06:00:09.92/vblo/02,634.99,yes,locked 2006.257.06:00:09.92/vblo/03,649.99,yes,locked 2006.257.06:00:09.92/vblo/04,679.99,yes,locked 2006.257.06:00:09.92/vblo/05,709.99,yes,locked 2006.257.06:00:09.92/vblo/06,719.99,yes,locked 2006.257.06:00:09.92/vblo/07,734.99,yes,locked 2006.257.06:00:09.92/vblo/08,744.99,yes,locked 2006.257.06:00:10.07/vabw/8 2006.257.06:00:10.22/vbbw/8 2006.257.06:00:10.31/xfe/off,on,16.7 2006.257.06:00:10.68/ifatt/23,28,28,28 2006.257.06:00:11.08/fmout-gps/S +4.52E-07 2006.257.06:00:11.12:!2006.257.06:00:47 2006.257.06:00:47.00:data_valid=off 2006.257.06:00:47.00:"et 2006.257.06:00:47.00:!+3s 2006.257.06:00:50.01:"tape 2006.257.06:00:50.01:postob 2006.257.06:00:50.20/cable/+6.4800E-03 2006.257.06:00:50.20/wx/20.14,1012.2,89 2006.257.06:00:51.08/fmout-gps/S +4.53E-07 2006.257.06:00:51.08:scan_name=257-0604,jd0609,40 2006.257.06:00:51.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.257.06:00:52.13#flagr#flagr/antenna,new-source 2006.257.06:00:52.13:checkk5 2006.257.06:00:52.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:00:52.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:00:53.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:00:53.70/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:00:54.09/chk_obsdata//k5ts1/T2570600??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:00:54.50/chk_obsdata//k5ts2/T2570600??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:00:54.90/chk_obsdata//k5ts3/T2570600??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:00:55.32/chk_obsdata//k5ts4/T2570600??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:00:56.04/k5log//k5ts1_log_newline 2006.257.06:00:56.76/k5log//k5ts2_log_newline 2006.257.06:00:57.52/k5log//k5ts3_log_newline 2006.257.06:00:58.21/k5log//k5ts4_log_newline 2006.257.06:00:58.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:00:58.24:setupk4=1 2006.257.06:00:58.24$setupk4/echo=on 2006.257.06:00:58.24$setupk4/pcalon 2006.257.06:00:58.24$pcalon/"no phase cal control is implemented here 2006.257.06:00:58.24$setupk4/"tpicd=stop 2006.257.06:00:58.24$setupk4/"rec=synch_on 2006.257.06:00:58.24$setupk4/"rec_mode=128 2006.257.06:00:58.24$setupk4/!* 2006.257.06:00:58.24$setupk4/recpk4 2006.257.06:00:58.24$recpk4/recpatch= 2006.257.06:00:58.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:00:58.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:00:58.24$setupk4/vck44 2006.257.06:00:58.24$vck44/valo=1,524.99 2006.257.06:00:58.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.06:00:58.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.06:00:58.24#ibcon#ireg 17 cls_cnt 0 2006.257.06:00:58.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:00:58.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:00:58.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:00:58.24#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:00:58.24#ibcon#first serial, iclass 31, count 0 2006.257.06:00:58.24#ibcon#enter sib2, iclass 31, count 0 2006.257.06:00:58.24#ibcon#flushed, iclass 31, count 0 2006.257.06:00:58.24#ibcon#about to write, iclass 31, count 0 2006.257.06:00:58.24#ibcon#wrote, iclass 31, count 0 2006.257.06:00:58.24#ibcon#about to read 3, iclass 31, count 0 2006.257.06:00:58.26#ibcon#read 3, iclass 31, count 0 2006.257.06:00:58.26#ibcon#about to read 4, iclass 31, count 0 2006.257.06:00:58.26#ibcon#read 4, iclass 31, count 0 2006.257.06:00:58.26#ibcon#about to read 5, iclass 31, count 0 2006.257.06:00:58.26#ibcon#read 5, iclass 31, count 0 2006.257.06:00:58.26#ibcon#about to read 6, iclass 31, count 0 2006.257.06:00:58.26#ibcon#read 6, iclass 31, count 0 2006.257.06:00:58.26#ibcon#end of sib2, iclass 31, count 0 2006.257.06:00:58.26#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:00:58.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:00:58.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:00:58.26#ibcon#*before write, iclass 31, count 0 2006.257.06:00:58.26#ibcon#enter sib2, iclass 31, count 0 2006.257.06:00:58.26#ibcon#flushed, iclass 31, count 0 2006.257.06:00:58.26#ibcon#about to write, iclass 31, count 0 2006.257.06:00:58.26#ibcon#wrote, iclass 31, count 0 2006.257.06:00:58.26#ibcon#about to read 3, iclass 31, count 0 2006.257.06:00:58.31#ibcon#read 3, iclass 31, count 0 2006.257.06:00:58.31#ibcon#about to read 4, iclass 31, count 0 2006.257.06:00:58.31#ibcon#read 4, iclass 31, count 0 2006.257.06:00:58.31#ibcon#about to read 5, iclass 31, count 0 2006.257.06:00:58.31#ibcon#read 5, iclass 31, count 0 2006.257.06:00:58.31#ibcon#about to read 6, iclass 31, count 0 2006.257.06:00:58.31#ibcon#read 6, iclass 31, count 0 2006.257.06:00:58.31#ibcon#end of sib2, iclass 31, count 0 2006.257.06:00:58.31#ibcon#*after write, iclass 31, count 0 2006.257.06:00:58.31#ibcon#*before return 0, iclass 31, count 0 2006.257.06:00:58.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:00:58.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:00:58.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:00:58.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:00:58.31$vck44/va=1,8 2006.257.06:00:58.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.06:00:58.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.06:00:58.31#ibcon#ireg 11 cls_cnt 2 2006.257.06:00:58.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:00:58.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:00:58.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:00:58.31#ibcon#enter wrdev, iclass 33, count 2 2006.257.06:00:58.31#ibcon#first serial, iclass 33, count 2 2006.257.06:00:58.31#ibcon#enter sib2, iclass 33, count 2 2006.257.06:00:58.31#ibcon#flushed, iclass 33, count 2 2006.257.06:00:58.31#ibcon#about to write, iclass 33, count 2 2006.257.06:00:58.31#ibcon#wrote, iclass 33, count 2 2006.257.06:00:58.31#ibcon#about to read 3, iclass 33, count 2 2006.257.06:00:58.33#ibcon#read 3, iclass 33, count 2 2006.257.06:00:58.33#ibcon#about to read 4, iclass 33, count 2 2006.257.06:00:58.33#ibcon#read 4, iclass 33, count 2 2006.257.06:00:58.33#ibcon#about to read 5, iclass 33, count 2 2006.257.06:00:58.33#ibcon#read 5, iclass 33, count 2 2006.257.06:00:58.33#ibcon#about to read 6, iclass 33, count 2 2006.257.06:00:58.33#ibcon#read 6, iclass 33, count 2 2006.257.06:00:58.33#ibcon#end of sib2, iclass 33, count 2 2006.257.06:00:58.33#ibcon#*mode == 0, iclass 33, count 2 2006.257.06:00:58.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.06:00:58.33#ibcon#[25=AT01-08\r\n] 2006.257.06:00:58.33#ibcon#*before write, iclass 33, count 2 2006.257.06:00:58.33#ibcon#enter sib2, iclass 33, count 2 2006.257.06:00:58.33#ibcon#flushed, iclass 33, count 2 2006.257.06:00:58.33#ibcon#about to write, iclass 33, count 2 2006.257.06:00:58.33#ibcon#wrote, iclass 33, count 2 2006.257.06:00:58.33#ibcon#about to read 3, iclass 33, count 2 2006.257.06:00:58.36#ibcon#read 3, iclass 33, count 2 2006.257.06:00:58.36#ibcon#about to read 4, iclass 33, count 2 2006.257.06:00:58.36#ibcon#read 4, iclass 33, count 2 2006.257.06:00:58.36#ibcon#about to read 5, iclass 33, count 2 2006.257.06:00:58.36#ibcon#read 5, iclass 33, count 2 2006.257.06:00:58.36#ibcon#about to read 6, iclass 33, count 2 2006.257.06:00:58.36#ibcon#read 6, iclass 33, count 2 2006.257.06:00:58.36#ibcon#end of sib2, iclass 33, count 2 2006.257.06:00:58.36#ibcon#*after write, iclass 33, count 2 2006.257.06:00:58.36#ibcon#*before return 0, iclass 33, count 2 2006.257.06:00:58.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:00:58.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:00:58.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.06:00:58.36#ibcon#ireg 7 cls_cnt 0 2006.257.06:00:58.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:00:58.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:00:58.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:00:58.48#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:00:58.48#ibcon#first serial, iclass 33, count 0 2006.257.06:00:58.48#ibcon#enter sib2, iclass 33, count 0 2006.257.06:00:58.48#ibcon#flushed, iclass 33, count 0 2006.257.06:00:58.48#ibcon#about to write, iclass 33, count 0 2006.257.06:00:58.48#ibcon#wrote, iclass 33, count 0 2006.257.06:00:58.48#ibcon#about to read 3, iclass 33, count 0 2006.257.06:00:58.50#ibcon#read 3, iclass 33, count 0 2006.257.06:00:58.50#ibcon#about to read 4, iclass 33, count 0 2006.257.06:00:58.50#ibcon#read 4, iclass 33, count 0 2006.257.06:00:58.50#ibcon#about to read 5, iclass 33, count 0 2006.257.06:00:58.50#ibcon#read 5, iclass 33, count 0 2006.257.06:00:58.50#ibcon#about to read 6, iclass 33, count 0 2006.257.06:00:58.50#ibcon#read 6, iclass 33, count 0 2006.257.06:00:58.50#ibcon#end of sib2, iclass 33, count 0 2006.257.06:00:58.50#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:00:58.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:00:58.50#ibcon#[25=USB\r\n] 2006.257.06:00:58.50#ibcon#*before write, iclass 33, count 0 2006.257.06:00:58.50#ibcon#enter sib2, iclass 33, count 0 2006.257.06:00:58.50#ibcon#flushed, iclass 33, count 0 2006.257.06:00:58.50#ibcon#about to write, iclass 33, count 0 2006.257.06:00:58.50#ibcon#wrote, iclass 33, count 0 2006.257.06:00:58.50#ibcon#about to read 3, iclass 33, count 0 2006.257.06:00:58.53#ibcon#read 3, iclass 33, count 0 2006.257.06:00:58.53#ibcon#about to read 4, iclass 33, count 0 2006.257.06:00:58.53#ibcon#read 4, iclass 33, count 0 2006.257.06:00:58.53#ibcon#about to read 5, iclass 33, count 0 2006.257.06:00:58.53#ibcon#read 5, iclass 33, count 0 2006.257.06:00:58.53#ibcon#about to read 6, iclass 33, count 0 2006.257.06:00:58.53#ibcon#read 6, iclass 33, count 0 2006.257.06:00:58.53#ibcon#end of sib2, iclass 33, count 0 2006.257.06:00:58.53#ibcon#*after write, iclass 33, count 0 2006.257.06:00:58.53#ibcon#*before return 0, iclass 33, count 0 2006.257.06:00:58.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:00:58.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:00:58.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:00:58.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:00:58.53$vck44/valo=2,534.99 2006.257.06:00:58.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:00:58.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:00:58.53#ibcon#ireg 17 cls_cnt 0 2006.257.06:00:58.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:00:58.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:00:58.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:00:58.53#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:00:58.53#ibcon#first serial, iclass 35, count 0 2006.257.06:00:58.53#ibcon#enter sib2, iclass 35, count 0 2006.257.06:00:58.53#ibcon#flushed, iclass 35, count 0 2006.257.06:00:58.53#ibcon#about to write, iclass 35, count 0 2006.257.06:00:58.53#ibcon#wrote, iclass 35, count 0 2006.257.06:00:58.53#ibcon#about to read 3, iclass 35, count 0 2006.257.06:00:58.55#ibcon#read 3, iclass 35, count 0 2006.257.06:00:58.55#ibcon#about to read 4, iclass 35, count 0 2006.257.06:00:58.55#ibcon#read 4, iclass 35, count 0 2006.257.06:00:58.55#ibcon#about to read 5, iclass 35, count 0 2006.257.06:00:58.55#ibcon#read 5, iclass 35, count 0 2006.257.06:00:58.55#ibcon#about to read 6, iclass 35, count 0 2006.257.06:00:58.55#ibcon#read 6, iclass 35, count 0 2006.257.06:00:58.55#ibcon#end of sib2, iclass 35, count 0 2006.257.06:00:58.55#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:00:58.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:00:58.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:00:58.55#ibcon#*before write, iclass 35, count 0 2006.257.06:00:58.55#ibcon#enter sib2, iclass 35, count 0 2006.257.06:00:58.55#ibcon#flushed, iclass 35, count 0 2006.257.06:00:58.55#ibcon#about to write, iclass 35, count 0 2006.257.06:00:58.55#ibcon#wrote, iclass 35, count 0 2006.257.06:00:58.55#ibcon#about to read 3, iclass 35, count 0 2006.257.06:00:58.59#ibcon#read 3, iclass 35, count 0 2006.257.06:00:58.59#ibcon#about to read 4, iclass 35, count 0 2006.257.06:00:58.59#ibcon#read 4, iclass 35, count 0 2006.257.06:00:58.59#ibcon#about to read 5, iclass 35, count 0 2006.257.06:00:58.59#ibcon#read 5, iclass 35, count 0 2006.257.06:00:58.59#ibcon#about to read 6, iclass 35, count 0 2006.257.06:00:58.59#ibcon#read 6, iclass 35, count 0 2006.257.06:00:58.59#ibcon#end of sib2, iclass 35, count 0 2006.257.06:00:58.59#ibcon#*after write, iclass 35, count 0 2006.257.06:00:58.59#ibcon#*before return 0, iclass 35, count 0 2006.257.06:00:58.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:00:58.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:00:58.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:00:58.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:00:58.59$vck44/va=2,7 2006.257.06:00:58.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.06:00:58.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.06:00:58.59#ibcon#ireg 11 cls_cnt 2 2006.257.06:00:58.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:00:58.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:00:58.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:00:58.65#ibcon#enter wrdev, iclass 37, count 2 2006.257.06:00:58.65#ibcon#first serial, iclass 37, count 2 2006.257.06:00:58.65#ibcon#enter sib2, iclass 37, count 2 2006.257.06:00:58.65#ibcon#flushed, iclass 37, count 2 2006.257.06:00:58.65#ibcon#about to write, iclass 37, count 2 2006.257.06:00:58.65#ibcon#wrote, iclass 37, count 2 2006.257.06:00:58.65#ibcon#about to read 3, iclass 37, count 2 2006.257.06:00:58.67#ibcon#read 3, iclass 37, count 2 2006.257.06:00:58.67#ibcon#about to read 4, iclass 37, count 2 2006.257.06:00:58.67#ibcon#read 4, iclass 37, count 2 2006.257.06:00:58.67#ibcon#about to read 5, iclass 37, count 2 2006.257.06:00:58.67#ibcon#read 5, iclass 37, count 2 2006.257.06:00:58.67#ibcon#about to read 6, iclass 37, count 2 2006.257.06:00:58.67#ibcon#read 6, iclass 37, count 2 2006.257.06:00:58.67#ibcon#end of sib2, iclass 37, count 2 2006.257.06:00:58.67#ibcon#*mode == 0, iclass 37, count 2 2006.257.06:00:58.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.06:00:58.67#ibcon#[25=AT02-07\r\n] 2006.257.06:00:58.67#ibcon#*before write, iclass 37, count 2 2006.257.06:00:58.67#ibcon#enter sib2, iclass 37, count 2 2006.257.06:00:58.67#ibcon#flushed, iclass 37, count 2 2006.257.06:00:58.67#ibcon#about to write, iclass 37, count 2 2006.257.06:00:58.67#ibcon#wrote, iclass 37, count 2 2006.257.06:00:58.67#ibcon#about to read 3, iclass 37, count 2 2006.257.06:00:58.70#ibcon#read 3, iclass 37, count 2 2006.257.06:00:58.70#ibcon#about to read 4, iclass 37, count 2 2006.257.06:00:58.70#ibcon#read 4, iclass 37, count 2 2006.257.06:00:58.70#ibcon#about to read 5, iclass 37, count 2 2006.257.06:00:58.70#ibcon#read 5, iclass 37, count 2 2006.257.06:00:58.70#ibcon#about to read 6, iclass 37, count 2 2006.257.06:00:58.70#ibcon#read 6, iclass 37, count 2 2006.257.06:00:58.70#ibcon#end of sib2, iclass 37, count 2 2006.257.06:00:58.70#ibcon#*after write, iclass 37, count 2 2006.257.06:00:58.70#ibcon#*before return 0, iclass 37, count 2 2006.257.06:00:58.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:00:58.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:00:58.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.06:00:58.70#ibcon#ireg 7 cls_cnt 0 2006.257.06:00:58.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:00:58.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:00:58.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:00:58.82#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:00:58.82#ibcon#first serial, iclass 37, count 0 2006.257.06:00:58.82#ibcon#enter sib2, iclass 37, count 0 2006.257.06:00:58.82#ibcon#flushed, iclass 37, count 0 2006.257.06:00:58.82#ibcon#about to write, iclass 37, count 0 2006.257.06:00:58.82#ibcon#wrote, iclass 37, count 0 2006.257.06:00:58.82#ibcon#about to read 3, iclass 37, count 0 2006.257.06:00:58.84#ibcon#read 3, iclass 37, count 0 2006.257.06:00:58.84#ibcon#about to read 4, iclass 37, count 0 2006.257.06:00:58.84#ibcon#read 4, iclass 37, count 0 2006.257.06:00:58.84#ibcon#about to read 5, iclass 37, count 0 2006.257.06:00:58.84#ibcon#read 5, iclass 37, count 0 2006.257.06:00:58.84#ibcon#about to read 6, iclass 37, count 0 2006.257.06:00:58.84#ibcon#read 6, iclass 37, count 0 2006.257.06:00:58.84#ibcon#end of sib2, iclass 37, count 0 2006.257.06:00:58.84#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:00:58.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:00:58.84#ibcon#[25=USB\r\n] 2006.257.06:00:58.84#ibcon#*before write, iclass 37, count 0 2006.257.06:00:58.84#ibcon#enter sib2, iclass 37, count 0 2006.257.06:00:58.84#ibcon#flushed, iclass 37, count 0 2006.257.06:00:58.84#ibcon#about to write, iclass 37, count 0 2006.257.06:00:58.84#ibcon#wrote, iclass 37, count 0 2006.257.06:00:58.84#ibcon#about to read 3, iclass 37, count 0 2006.257.06:00:58.87#ibcon#read 3, iclass 37, count 0 2006.257.06:00:58.87#ibcon#about to read 4, iclass 37, count 0 2006.257.06:00:58.87#ibcon#read 4, iclass 37, count 0 2006.257.06:00:58.87#ibcon#about to read 5, iclass 37, count 0 2006.257.06:00:58.87#ibcon#read 5, iclass 37, count 0 2006.257.06:00:58.87#ibcon#about to read 6, iclass 37, count 0 2006.257.06:00:58.87#ibcon#read 6, iclass 37, count 0 2006.257.06:00:58.87#ibcon#end of sib2, iclass 37, count 0 2006.257.06:00:58.87#ibcon#*after write, iclass 37, count 0 2006.257.06:00:58.87#ibcon#*before return 0, iclass 37, count 0 2006.257.06:00:58.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:00:58.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:00:58.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:00:58.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:00:58.87$vck44/valo=3,564.99 2006.257.06:00:58.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.06:00:58.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.06:00:58.87#ibcon#ireg 17 cls_cnt 0 2006.257.06:00:58.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:00:58.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:00:58.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:00:58.87#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:00:58.87#ibcon#first serial, iclass 39, count 0 2006.257.06:00:58.87#ibcon#enter sib2, iclass 39, count 0 2006.257.06:00:58.87#ibcon#flushed, iclass 39, count 0 2006.257.06:00:58.87#ibcon#about to write, iclass 39, count 0 2006.257.06:00:58.87#ibcon#wrote, iclass 39, count 0 2006.257.06:00:58.87#ibcon#about to read 3, iclass 39, count 0 2006.257.06:00:58.89#ibcon#read 3, iclass 39, count 0 2006.257.06:00:58.89#ibcon#about to read 4, iclass 39, count 0 2006.257.06:00:58.89#ibcon#read 4, iclass 39, count 0 2006.257.06:00:58.89#ibcon#about to read 5, iclass 39, count 0 2006.257.06:00:58.89#ibcon#read 5, iclass 39, count 0 2006.257.06:00:58.89#ibcon#about to read 6, iclass 39, count 0 2006.257.06:00:58.89#ibcon#read 6, iclass 39, count 0 2006.257.06:00:58.89#ibcon#end of sib2, iclass 39, count 0 2006.257.06:00:58.89#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:00:58.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:00:58.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:00:58.89#ibcon#*before write, iclass 39, count 0 2006.257.06:00:58.89#ibcon#enter sib2, iclass 39, count 0 2006.257.06:00:58.89#ibcon#flushed, iclass 39, count 0 2006.257.06:00:58.89#ibcon#about to write, iclass 39, count 0 2006.257.06:00:58.89#ibcon#wrote, iclass 39, count 0 2006.257.06:00:58.89#ibcon#about to read 3, iclass 39, count 0 2006.257.06:00:58.93#ibcon#read 3, iclass 39, count 0 2006.257.06:00:58.93#ibcon#about to read 4, iclass 39, count 0 2006.257.06:00:58.93#ibcon#read 4, iclass 39, count 0 2006.257.06:00:58.93#ibcon#about to read 5, iclass 39, count 0 2006.257.06:00:58.93#ibcon#read 5, iclass 39, count 0 2006.257.06:00:58.93#ibcon#about to read 6, iclass 39, count 0 2006.257.06:00:58.93#ibcon#read 6, iclass 39, count 0 2006.257.06:00:58.93#ibcon#end of sib2, iclass 39, count 0 2006.257.06:00:58.93#ibcon#*after write, iclass 39, count 0 2006.257.06:00:58.93#ibcon#*before return 0, iclass 39, count 0 2006.257.06:00:58.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:00:58.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:00:58.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:00:58.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:00:58.93$vck44/va=3,8 2006.257.06:00:58.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.06:00:58.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.06:00:58.93#ibcon#ireg 11 cls_cnt 2 2006.257.06:00:58.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:00:58.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:00:58.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:00:58.99#ibcon#enter wrdev, iclass 3, count 2 2006.257.06:00:58.99#ibcon#first serial, iclass 3, count 2 2006.257.06:00:58.99#ibcon#enter sib2, iclass 3, count 2 2006.257.06:00:58.99#ibcon#flushed, iclass 3, count 2 2006.257.06:00:58.99#ibcon#about to write, iclass 3, count 2 2006.257.06:00:58.99#ibcon#wrote, iclass 3, count 2 2006.257.06:00:58.99#ibcon#about to read 3, iclass 3, count 2 2006.257.06:00:59.01#ibcon#read 3, iclass 3, count 2 2006.257.06:00:59.01#ibcon#about to read 4, iclass 3, count 2 2006.257.06:00:59.01#ibcon#read 4, iclass 3, count 2 2006.257.06:00:59.01#ibcon#about to read 5, iclass 3, count 2 2006.257.06:00:59.01#ibcon#read 5, iclass 3, count 2 2006.257.06:00:59.01#ibcon#about to read 6, iclass 3, count 2 2006.257.06:00:59.01#ibcon#read 6, iclass 3, count 2 2006.257.06:00:59.01#ibcon#end of sib2, iclass 3, count 2 2006.257.06:00:59.01#ibcon#*mode == 0, iclass 3, count 2 2006.257.06:00:59.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.06:00:59.01#ibcon#[25=AT03-08\r\n] 2006.257.06:00:59.01#ibcon#*before write, iclass 3, count 2 2006.257.06:00:59.01#ibcon#enter sib2, iclass 3, count 2 2006.257.06:00:59.01#ibcon#flushed, iclass 3, count 2 2006.257.06:00:59.01#ibcon#about to write, iclass 3, count 2 2006.257.06:00:59.01#ibcon#wrote, iclass 3, count 2 2006.257.06:00:59.01#ibcon#about to read 3, iclass 3, count 2 2006.257.06:00:59.04#ibcon#read 3, iclass 3, count 2 2006.257.06:00:59.04#ibcon#about to read 4, iclass 3, count 2 2006.257.06:00:59.04#ibcon#read 4, iclass 3, count 2 2006.257.06:00:59.04#ibcon#about to read 5, iclass 3, count 2 2006.257.06:00:59.04#ibcon#read 5, iclass 3, count 2 2006.257.06:00:59.04#ibcon#about to read 6, iclass 3, count 2 2006.257.06:00:59.04#ibcon#read 6, iclass 3, count 2 2006.257.06:00:59.04#ibcon#end of sib2, iclass 3, count 2 2006.257.06:00:59.04#ibcon#*after write, iclass 3, count 2 2006.257.06:00:59.04#ibcon#*before return 0, iclass 3, count 2 2006.257.06:00:59.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:00:59.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:00:59.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.06:00:59.04#ibcon#ireg 7 cls_cnt 0 2006.257.06:00:59.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:00:59.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:00:59.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:00:59.16#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:00:59.16#ibcon#first serial, iclass 3, count 0 2006.257.06:00:59.16#ibcon#enter sib2, iclass 3, count 0 2006.257.06:00:59.16#ibcon#flushed, iclass 3, count 0 2006.257.06:00:59.16#ibcon#about to write, iclass 3, count 0 2006.257.06:00:59.16#ibcon#wrote, iclass 3, count 0 2006.257.06:00:59.16#ibcon#about to read 3, iclass 3, count 0 2006.257.06:00:59.18#ibcon#read 3, iclass 3, count 0 2006.257.06:00:59.18#ibcon#about to read 4, iclass 3, count 0 2006.257.06:00:59.18#ibcon#read 4, iclass 3, count 0 2006.257.06:00:59.18#ibcon#about to read 5, iclass 3, count 0 2006.257.06:00:59.18#ibcon#read 5, iclass 3, count 0 2006.257.06:00:59.18#ibcon#about to read 6, iclass 3, count 0 2006.257.06:00:59.18#ibcon#read 6, iclass 3, count 0 2006.257.06:00:59.18#ibcon#end of sib2, iclass 3, count 0 2006.257.06:00:59.18#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:00:59.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:00:59.18#ibcon#[25=USB\r\n] 2006.257.06:00:59.18#ibcon#*before write, iclass 3, count 0 2006.257.06:00:59.18#ibcon#enter sib2, iclass 3, count 0 2006.257.06:00:59.18#ibcon#flushed, iclass 3, count 0 2006.257.06:00:59.18#ibcon#about to write, iclass 3, count 0 2006.257.06:00:59.18#ibcon#wrote, iclass 3, count 0 2006.257.06:00:59.18#ibcon#about to read 3, iclass 3, count 0 2006.257.06:00:59.21#ibcon#read 3, iclass 3, count 0 2006.257.06:00:59.21#ibcon#about to read 4, iclass 3, count 0 2006.257.06:00:59.21#ibcon#read 4, iclass 3, count 0 2006.257.06:00:59.21#ibcon#about to read 5, iclass 3, count 0 2006.257.06:00:59.21#ibcon#read 5, iclass 3, count 0 2006.257.06:00:59.21#ibcon#about to read 6, iclass 3, count 0 2006.257.06:00:59.21#ibcon#read 6, iclass 3, count 0 2006.257.06:00:59.21#ibcon#end of sib2, iclass 3, count 0 2006.257.06:00:59.21#ibcon#*after write, iclass 3, count 0 2006.257.06:00:59.21#ibcon#*before return 0, iclass 3, count 0 2006.257.06:00:59.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:00:59.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:00:59.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:00:59.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:00:59.21$vck44/valo=4,624.99 2006.257.06:00:59.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.06:00:59.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.06:00:59.21#ibcon#ireg 17 cls_cnt 0 2006.257.06:00:59.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:00:59.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:00:59.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:00:59.21#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:00:59.21#ibcon#first serial, iclass 5, count 0 2006.257.06:00:59.21#ibcon#enter sib2, iclass 5, count 0 2006.257.06:00:59.21#ibcon#flushed, iclass 5, count 0 2006.257.06:00:59.21#ibcon#about to write, iclass 5, count 0 2006.257.06:00:59.21#ibcon#wrote, iclass 5, count 0 2006.257.06:00:59.21#ibcon#about to read 3, iclass 5, count 0 2006.257.06:00:59.23#ibcon#read 3, iclass 5, count 0 2006.257.06:00:59.23#ibcon#about to read 4, iclass 5, count 0 2006.257.06:00:59.23#ibcon#read 4, iclass 5, count 0 2006.257.06:00:59.23#ibcon#about to read 5, iclass 5, count 0 2006.257.06:00:59.23#ibcon#read 5, iclass 5, count 0 2006.257.06:00:59.23#ibcon#about to read 6, iclass 5, count 0 2006.257.06:00:59.23#ibcon#read 6, iclass 5, count 0 2006.257.06:00:59.23#ibcon#end of sib2, iclass 5, count 0 2006.257.06:00:59.23#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:00:59.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:00:59.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:00:59.23#ibcon#*before write, iclass 5, count 0 2006.257.06:00:59.23#ibcon#enter sib2, iclass 5, count 0 2006.257.06:00:59.23#ibcon#flushed, iclass 5, count 0 2006.257.06:00:59.23#ibcon#about to write, iclass 5, count 0 2006.257.06:00:59.23#ibcon#wrote, iclass 5, count 0 2006.257.06:00:59.23#ibcon#about to read 3, iclass 5, count 0 2006.257.06:00:59.27#ibcon#read 3, iclass 5, count 0 2006.257.06:00:59.27#ibcon#about to read 4, iclass 5, count 0 2006.257.06:00:59.27#ibcon#read 4, iclass 5, count 0 2006.257.06:00:59.27#ibcon#about to read 5, iclass 5, count 0 2006.257.06:00:59.27#ibcon#read 5, iclass 5, count 0 2006.257.06:00:59.27#ibcon#about to read 6, iclass 5, count 0 2006.257.06:00:59.27#ibcon#read 6, iclass 5, count 0 2006.257.06:00:59.27#ibcon#end of sib2, iclass 5, count 0 2006.257.06:00:59.27#ibcon#*after write, iclass 5, count 0 2006.257.06:00:59.27#ibcon#*before return 0, iclass 5, count 0 2006.257.06:00:59.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:00:59.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:00:59.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:00:59.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:00:59.27$vck44/va=4,7 2006.257.06:00:59.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.06:00:59.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.06:00:59.27#ibcon#ireg 11 cls_cnt 2 2006.257.06:00:59.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:00:59.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:00:59.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:00:59.33#ibcon#enter wrdev, iclass 7, count 2 2006.257.06:00:59.33#ibcon#first serial, iclass 7, count 2 2006.257.06:00:59.33#ibcon#enter sib2, iclass 7, count 2 2006.257.06:00:59.33#ibcon#flushed, iclass 7, count 2 2006.257.06:00:59.33#ibcon#about to write, iclass 7, count 2 2006.257.06:00:59.33#ibcon#wrote, iclass 7, count 2 2006.257.06:00:59.33#ibcon#about to read 3, iclass 7, count 2 2006.257.06:00:59.35#ibcon#read 3, iclass 7, count 2 2006.257.06:00:59.35#ibcon#about to read 4, iclass 7, count 2 2006.257.06:00:59.35#ibcon#read 4, iclass 7, count 2 2006.257.06:00:59.35#ibcon#about to read 5, iclass 7, count 2 2006.257.06:00:59.35#ibcon#read 5, iclass 7, count 2 2006.257.06:00:59.35#ibcon#about to read 6, iclass 7, count 2 2006.257.06:00:59.35#ibcon#read 6, iclass 7, count 2 2006.257.06:00:59.35#ibcon#end of sib2, iclass 7, count 2 2006.257.06:00:59.35#ibcon#*mode == 0, iclass 7, count 2 2006.257.06:00:59.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.06:00:59.35#ibcon#[25=AT04-07\r\n] 2006.257.06:00:59.35#ibcon#*before write, iclass 7, count 2 2006.257.06:00:59.35#ibcon#enter sib2, iclass 7, count 2 2006.257.06:00:59.35#ibcon#flushed, iclass 7, count 2 2006.257.06:00:59.35#ibcon#about to write, iclass 7, count 2 2006.257.06:00:59.35#ibcon#wrote, iclass 7, count 2 2006.257.06:00:59.35#ibcon#about to read 3, iclass 7, count 2 2006.257.06:00:59.38#ibcon#read 3, iclass 7, count 2 2006.257.06:00:59.38#ibcon#about to read 4, iclass 7, count 2 2006.257.06:00:59.38#ibcon#read 4, iclass 7, count 2 2006.257.06:00:59.38#ibcon#about to read 5, iclass 7, count 2 2006.257.06:00:59.38#ibcon#read 5, iclass 7, count 2 2006.257.06:00:59.38#ibcon#about to read 6, iclass 7, count 2 2006.257.06:00:59.38#ibcon#read 6, iclass 7, count 2 2006.257.06:00:59.38#ibcon#end of sib2, iclass 7, count 2 2006.257.06:00:59.38#ibcon#*after write, iclass 7, count 2 2006.257.06:00:59.38#ibcon#*before return 0, iclass 7, count 2 2006.257.06:00:59.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:00:59.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:00:59.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.06:00:59.38#ibcon#ireg 7 cls_cnt 0 2006.257.06:00:59.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:00:59.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:00:59.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:00:59.50#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:00:59.50#ibcon#first serial, iclass 7, count 0 2006.257.06:00:59.50#ibcon#enter sib2, iclass 7, count 0 2006.257.06:00:59.50#ibcon#flushed, iclass 7, count 0 2006.257.06:00:59.50#ibcon#about to write, iclass 7, count 0 2006.257.06:00:59.50#ibcon#wrote, iclass 7, count 0 2006.257.06:00:59.50#ibcon#about to read 3, iclass 7, count 0 2006.257.06:00:59.52#ibcon#read 3, iclass 7, count 0 2006.257.06:00:59.52#ibcon#about to read 4, iclass 7, count 0 2006.257.06:00:59.52#ibcon#read 4, iclass 7, count 0 2006.257.06:00:59.52#ibcon#about to read 5, iclass 7, count 0 2006.257.06:00:59.52#ibcon#read 5, iclass 7, count 0 2006.257.06:00:59.52#ibcon#about to read 6, iclass 7, count 0 2006.257.06:00:59.52#ibcon#read 6, iclass 7, count 0 2006.257.06:00:59.52#ibcon#end of sib2, iclass 7, count 0 2006.257.06:00:59.52#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:00:59.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:00:59.52#ibcon#[25=USB\r\n] 2006.257.06:00:59.52#ibcon#*before write, iclass 7, count 0 2006.257.06:00:59.52#ibcon#enter sib2, iclass 7, count 0 2006.257.06:00:59.52#ibcon#flushed, iclass 7, count 0 2006.257.06:00:59.52#ibcon#about to write, iclass 7, count 0 2006.257.06:00:59.52#ibcon#wrote, iclass 7, count 0 2006.257.06:00:59.52#ibcon#about to read 3, iclass 7, count 0 2006.257.06:00:59.55#ibcon#read 3, iclass 7, count 0 2006.257.06:00:59.55#ibcon#about to read 4, iclass 7, count 0 2006.257.06:00:59.55#ibcon#read 4, iclass 7, count 0 2006.257.06:00:59.55#ibcon#about to read 5, iclass 7, count 0 2006.257.06:00:59.55#ibcon#read 5, iclass 7, count 0 2006.257.06:00:59.55#ibcon#about to read 6, iclass 7, count 0 2006.257.06:00:59.55#ibcon#read 6, iclass 7, count 0 2006.257.06:00:59.55#ibcon#end of sib2, iclass 7, count 0 2006.257.06:00:59.55#ibcon#*after write, iclass 7, count 0 2006.257.06:00:59.55#ibcon#*before return 0, iclass 7, count 0 2006.257.06:00:59.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:00:59.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:00:59.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:00:59.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:00:59.55$vck44/valo=5,734.99 2006.257.06:00:59.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.06:00:59.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.06:00:59.55#ibcon#ireg 17 cls_cnt 0 2006.257.06:00:59.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:00:59.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:00:59.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:00:59.55#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:00:59.55#ibcon#first serial, iclass 11, count 0 2006.257.06:00:59.55#ibcon#enter sib2, iclass 11, count 0 2006.257.06:00:59.55#ibcon#flushed, iclass 11, count 0 2006.257.06:00:59.55#ibcon#about to write, iclass 11, count 0 2006.257.06:00:59.55#ibcon#wrote, iclass 11, count 0 2006.257.06:00:59.55#ibcon#about to read 3, iclass 11, count 0 2006.257.06:00:59.57#ibcon#read 3, iclass 11, count 0 2006.257.06:00:59.57#ibcon#about to read 4, iclass 11, count 0 2006.257.06:00:59.57#ibcon#read 4, iclass 11, count 0 2006.257.06:00:59.57#ibcon#about to read 5, iclass 11, count 0 2006.257.06:00:59.57#ibcon#read 5, iclass 11, count 0 2006.257.06:00:59.57#ibcon#about to read 6, iclass 11, count 0 2006.257.06:00:59.57#ibcon#read 6, iclass 11, count 0 2006.257.06:00:59.57#ibcon#end of sib2, iclass 11, count 0 2006.257.06:00:59.57#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:00:59.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:00:59.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:00:59.57#ibcon#*before write, iclass 11, count 0 2006.257.06:00:59.57#ibcon#enter sib2, iclass 11, count 0 2006.257.06:00:59.57#ibcon#flushed, iclass 11, count 0 2006.257.06:00:59.57#ibcon#about to write, iclass 11, count 0 2006.257.06:00:59.57#ibcon#wrote, iclass 11, count 0 2006.257.06:00:59.57#ibcon#about to read 3, iclass 11, count 0 2006.257.06:00:59.61#ibcon#read 3, iclass 11, count 0 2006.257.06:00:59.61#ibcon#about to read 4, iclass 11, count 0 2006.257.06:00:59.61#ibcon#read 4, iclass 11, count 0 2006.257.06:00:59.61#ibcon#about to read 5, iclass 11, count 0 2006.257.06:00:59.61#ibcon#read 5, iclass 11, count 0 2006.257.06:00:59.61#ibcon#about to read 6, iclass 11, count 0 2006.257.06:00:59.61#ibcon#read 6, iclass 11, count 0 2006.257.06:00:59.61#ibcon#end of sib2, iclass 11, count 0 2006.257.06:00:59.61#ibcon#*after write, iclass 11, count 0 2006.257.06:00:59.61#ibcon#*before return 0, iclass 11, count 0 2006.257.06:00:59.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:00:59.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:00:59.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:00:59.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:00:59.61$vck44/va=5,4 2006.257.06:00:59.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.06:00:59.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.06:00:59.61#ibcon#ireg 11 cls_cnt 2 2006.257.06:00:59.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:00:59.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:00:59.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:00:59.67#ibcon#enter wrdev, iclass 13, count 2 2006.257.06:00:59.67#ibcon#first serial, iclass 13, count 2 2006.257.06:00:59.67#ibcon#enter sib2, iclass 13, count 2 2006.257.06:00:59.67#ibcon#flushed, iclass 13, count 2 2006.257.06:00:59.67#ibcon#about to write, iclass 13, count 2 2006.257.06:00:59.67#ibcon#wrote, iclass 13, count 2 2006.257.06:00:59.67#ibcon#about to read 3, iclass 13, count 2 2006.257.06:00:59.69#ibcon#read 3, iclass 13, count 2 2006.257.06:00:59.69#ibcon#about to read 4, iclass 13, count 2 2006.257.06:00:59.69#ibcon#read 4, iclass 13, count 2 2006.257.06:00:59.69#ibcon#about to read 5, iclass 13, count 2 2006.257.06:00:59.69#ibcon#read 5, iclass 13, count 2 2006.257.06:00:59.69#ibcon#about to read 6, iclass 13, count 2 2006.257.06:00:59.69#ibcon#read 6, iclass 13, count 2 2006.257.06:00:59.69#ibcon#end of sib2, iclass 13, count 2 2006.257.06:00:59.69#ibcon#*mode == 0, iclass 13, count 2 2006.257.06:00:59.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.06:00:59.69#ibcon#[25=AT05-04\r\n] 2006.257.06:00:59.69#ibcon#*before write, iclass 13, count 2 2006.257.06:00:59.69#ibcon#enter sib2, iclass 13, count 2 2006.257.06:00:59.69#ibcon#flushed, iclass 13, count 2 2006.257.06:00:59.69#ibcon#about to write, iclass 13, count 2 2006.257.06:00:59.69#ibcon#wrote, iclass 13, count 2 2006.257.06:00:59.69#ibcon#about to read 3, iclass 13, count 2 2006.257.06:00:59.72#ibcon#read 3, iclass 13, count 2 2006.257.06:00:59.72#ibcon#about to read 4, iclass 13, count 2 2006.257.06:00:59.72#ibcon#read 4, iclass 13, count 2 2006.257.06:00:59.72#ibcon#about to read 5, iclass 13, count 2 2006.257.06:00:59.72#ibcon#read 5, iclass 13, count 2 2006.257.06:00:59.72#ibcon#about to read 6, iclass 13, count 2 2006.257.06:00:59.72#ibcon#read 6, iclass 13, count 2 2006.257.06:00:59.72#ibcon#end of sib2, iclass 13, count 2 2006.257.06:00:59.72#ibcon#*after write, iclass 13, count 2 2006.257.06:00:59.72#ibcon#*before return 0, iclass 13, count 2 2006.257.06:00:59.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:00:59.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:00:59.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.06:00:59.72#ibcon#ireg 7 cls_cnt 0 2006.257.06:00:59.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:00:59.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:00:59.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:00:59.84#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:00:59.84#ibcon#first serial, iclass 13, count 0 2006.257.06:00:59.84#ibcon#enter sib2, iclass 13, count 0 2006.257.06:00:59.84#ibcon#flushed, iclass 13, count 0 2006.257.06:00:59.84#ibcon#about to write, iclass 13, count 0 2006.257.06:00:59.84#ibcon#wrote, iclass 13, count 0 2006.257.06:00:59.84#ibcon#about to read 3, iclass 13, count 0 2006.257.06:00:59.86#ibcon#read 3, iclass 13, count 0 2006.257.06:00:59.86#ibcon#about to read 4, iclass 13, count 0 2006.257.06:00:59.86#ibcon#read 4, iclass 13, count 0 2006.257.06:00:59.86#ibcon#about to read 5, iclass 13, count 0 2006.257.06:00:59.86#ibcon#read 5, iclass 13, count 0 2006.257.06:00:59.86#ibcon#about to read 6, iclass 13, count 0 2006.257.06:00:59.86#ibcon#read 6, iclass 13, count 0 2006.257.06:00:59.86#ibcon#end of sib2, iclass 13, count 0 2006.257.06:00:59.86#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:00:59.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:00:59.86#ibcon#[25=USB\r\n] 2006.257.06:00:59.86#ibcon#*before write, iclass 13, count 0 2006.257.06:00:59.86#ibcon#enter sib2, iclass 13, count 0 2006.257.06:00:59.86#ibcon#flushed, iclass 13, count 0 2006.257.06:00:59.86#ibcon#about to write, iclass 13, count 0 2006.257.06:00:59.86#ibcon#wrote, iclass 13, count 0 2006.257.06:00:59.86#ibcon#about to read 3, iclass 13, count 0 2006.257.06:00:59.89#ibcon#read 3, iclass 13, count 0 2006.257.06:00:59.89#ibcon#about to read 4, iclass 13, count 0 2006.257.06:00:59.89#ibcon#read 4, iclass 13, count 0 2006.257.06:00:59.89#ibcon#about to read 5, iclass 13, count 0 2006.257.06:00:59.89#ibcon#read 5, iclass 13, count 0 2006.257.06:00:59.89#ibcon#about to read 6, iclass 13, count 0 2006.257.06:00:59.89#ibcon#read 6, iclass 13, count 0 2006.257.06:00:59.89#ibcon#end of sib2, iclass 13, count 0 2006.257.06:00:59.89#ibcon#*after write, iclass 13, count 0 2006.257.06:00:59.89#ibcon#*before return 0, iclass 13, count 0 2006.257.06:00:59.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:00:59.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:00:59.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:00:59.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:00:59.89$vck44/valo=6,814.99 2006.257.06:00:59.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.06:00:59.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.06:00:59.89#ibcon#ireg 17 cls_cnt 0 2006.257.06:00:59.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:00:59.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:00:59.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:00:59.89#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:00:59.89#ibcon#first serial, iclass 15, count 0 2006.257.06:00:59.89#ibcon#enter sib2, iclass 15, count 0 2006.257.06:00:59.89#ibcon#flushed, iclass 15, count 0 2006.257.06:00:59.89#ibcon#about to write, iclass 15, count 0 2006.257.06:00:59.89#ibcon#wrote, iclass 15, count 0 2006.257.06:00:59.89#ibcon#about to read 3, iclass 15, count 0 2006.257.06:00:59.91#ibcon#read 3, iclass 15, count 0 2006.257.06:00:59.91#ibcon#about to read 4, iclass 15, count 0 2006.257.06:00:59.91#ibcon#read 4, iclass 15, count 0 2006.257.06:00:59.91#ibcon#about to read 5, iclass 15, count 0 2006.257.06:00:59.91#ibcon#read 5, iclass 15, count 0 2006.257.06:00:59.91#ibcon#about to read 6, iclass 15, count 0 2006.257.06:00:59.91#ibcon#read 6, iclass 15, count 0 2006.257.06:00:59.91#ibcon#end of sib2, iclass 15, count 0 2006.257.06:00:59.91#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:00:59.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:00:59.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:00:59.91#ibcon#*before write, iclass 15, count 0 2006.257.06:00:59.91#ibcon#enter sib2, iclass 15, count 0 2006.257.06:00:59.91#ibcon#flushed, iclass 15, count 0 2006.257.06:00:59.91#ibcon#about to write, iclass 15, count 0 2006.257.06:00:59.91#ibcon#wrote, iclass 15, count 0 2006.257.06:00:59.91#ibcon#about to read 3, iclass 15, count 0 2006.257.06:00:59.95#ibcon#read 3, iclass 15, count 0 2006.257.06:00:59.95#ibcon#about to read 4, iclass 15, count 0 2006.257.06:00:59.95#ibcon#read 4, iclass 15, count 0 2006.257.06:00:59.95#ibcon#about to read 5, iclass 15, count 0 2006.257.06:00:59.95#ibcon#read 5, iclass 15, count 0 2006.257.06:00:59.95#ibcon#about to read 6, iclass 15, count 0 2006.257.06:00:59.95#ibcon#read 6, iclass 15, count 0 2006.257.06:00:59.95#ibcon#end of sib2, iclass 15, count 0 2006.257.06:00:59.95#ibcon#*after write, iclass 15, count 0 2006.257.06:00:59.95#ibcon#*before return 0, iclass 15, count 0 2006.257.06:00:59.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:00:59.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:00:59.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:00:59.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:00:59.95$vck44/va=6,4 2006.257.06:00:59.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.06:00:59.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.06:00:59.95#ibcon#ireg 11 cls_cnt 2 2006.257.06:00:59.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:01:00.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:01:00.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:01:00.01#ibcon#enter wrdev, iclass 17, count 2 2006.257.06:01:00.01#ibcon#first serial, iclass 17, count 2 2006.257.06:01:00.01#ibcon#enter sib2, iclass 17, count 2 2006.257.06:01:00.01#ibcon#flushed, iclass 17, count 2 2006.257.06:01:00.01#ibcon#about to write, iclass 17, count 2 2006.257.06:01:00.01#ibcon#wrote, iclass 17, count 2 2006.257.06:01:00.01#ibcon#about to read 3, iclass 17, count 2 2006.257.06:01:00.03#ibcon#read 3, iclass 17, count 2 2006.257.06:01:00.03#ibcon#about to read 4, iclass 17, count 2 2006.257.06:01:00.03#ibcon#read 4, iclass 17, count 2 2006.257.06:01:00.03#ibcon#about to read 5, iclass 17, count 2 2006.257.06:01:00.03#ibcon#read 5, iclass 17, count 2 2006.257.06:01:00.03#ibcon#about to read 6, iclass 17, count 2 2006.257.06:01:00.03#ibcon#read 6, iclass 17, count 2 2006.257.06:01:00.03#ibcon#end of sib2, iclass 17, count 2 2006.257.06:01:00.03#ibcon#*mode == 0, iclass 17, count 2 2006.257.06:01:00.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.06:01:00.03#ibcon#[25=AT06-04\r\n] 2006.257.06:01:00.03#ibcon#*before write, iclass 17, count 2 2006.257.06:01:00.03#ibcon#enter sib2, iclass 17, count 2 2006.257.06:01:00.03#ibcon#flushed, iclass 17, count 2 2006.257.06:01:00.03#ibcon#about to write, iclass 17, count 2 2006.257.06:01:00.03#ibcon#wrote, iclass 17, count 2 2006.257.06:01:00.03#ibcon#about to read 3, iclass 17, count 2 2006.257.06:01:00.06#ibcon#read 3, iclass 17, count 2 2006.257.06:01:00.06#ibcon#about to read 4, iclass 17, count 2 2006.257.06:01:00.06#ibcon#read 4, iclass 17, count 2 2006.257.06:01:00.06#ibcon#about to read 5, iclass 17, count 2 2006.257.06:01:00.06#ibcon#read 5, iclass 17, count 2 2006.257.06:01:00.06#ibcon#about to read 6, iclass 17, count 2 2006.257.06:01:00.06#ibcon#read 6, iclass 17, count 2 2006.257.06:01:00.06#ibcon#end of sib2, iclass 17, count 2 2006.257.06:01:00.06#ibcon#*after write, iclass 17, count 2 2006.257.06:01:00.06#ibcon#*before return 0, iclass 17, count 2 2006.257.06:01:00.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:01:00.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:01:00.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.06:01:00.06#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:00.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:01:00.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:01:00.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:01:00.18#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:01:00.18#ibcon#first serial, iclass 17, count 0 2006.257.06:01:00.18#ibcon#enter sib2, iclass 17, count 0 2006.257.06:01:00.18#ibcon#flushed, iclass 17, count 0 2006.257.06:01:00.18#ibcon#about to write, iclass 17, count 0 2006.257.06:01:00.18#ibcon#wrote, iclass 17, count 0 2006.257.06:01:00.18#ibcon#about to read 3, iclass 17, count 0 2006.257.06:01:00.20#ibcon#read 3, iclass 17, count 0 2006.257.06:01:00.20#ibcon#about to read 4, iclass 17, count 0 2006.257.06:01:00.20#ibcon#read 4, iclass 17, count 0 2006.257.06:01:00.20#ibcon#about to read 5, iclass 17, count 0 2006.257.06:01:00.20#ibcon#read 5, iclass 17, count 0 2006.257.06:01:00.20#ibcon#about to read 6, iclass 17, count 0 2006.257.06:01:00.20#ibcon#read 6, iclass 17, count 0 2006.257.06:01:00.20#ibcon#end of sib2, iclass 17, count 0 2006.257.06:01:00.20#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:01:00.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:01:00.20#ibcon#[25=USB\r\n] 2006.257.06:01:00.20#ibcon#*before write, iclass 17, count 0 2006.257.06:01:00.20#ibcon#enter sib2, iclass 17, count 0 2006.257.06:01:00.20#ibcon#flushed, iclass 17, count 0 2006.257.06:01:00.20#ibcon#about to write, iclass 17, count 0 2006.257.06:01:00.20#ibcon#wrote, iclass 17, count 0 2006.257.06:01:00.20#ibcon#about to read 3, iclass 17, count 0 2006.257.06:01:00.23#ibcon#read 3, iclass 17, count 0 2006.257.06:01:00.23#ibcon#about to read 4, iclass 17, count 0 2006.257.06:01:00.23#ibcon#read 4, iclass 17, count 0 2006.257.06:01:00.23#ibcon#about to read 5, iclass 17, count 0 2006.257.06:01:00.23#ibcon#read 5, iclass 17, count 0 2006.257.06:01:00.23#ibcon#about to read 6, iclass 17, count 0 2006.257.06:01:00.23#ibcon#read 6, iclass 17, count 0 2006.257.06:01:00.23#ibcon#end of sib2, iclass 17, count 0 2006.257.06:01:00.23#ibcon#*after write, iclass 17, count 0 2006.257.06:01:00.23#ibcon#*before return 0, iclass 17, count 0 2006.257.06:01:00.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:01:00.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:01:00.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:01:00.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:01:00.23$vck44/valo=7,864.99 2006.257.06:01:00.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.06:01:00.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.06:01:00.23#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:00.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:00.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:00.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:00.23#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:01:00.23#ibcon#first serial, iclass 19, count 0 2006.257.06:01:00.23#ibcon#enter sib2, iclass 19, count 0 2006.257.06:01:00.23#ibcon#flushed, iclass 19, count 0 2006.257.06:01:00.23#ibcon#about to write, iclass 19, count 0 2006.257.06:01:00.23#ibcon#wrote, iclass 19, count 0 2006.257.06:01:00.23#ibcon#about to read 3, iclass 19, count 0 2006.257.06:01:00.25#ibcon#read 3, iclass 19, count 0 2006.257.06:01:00.25#ibcon#about to read 4, iclass 19, count 0 2006.257.06:01:00.25#ibcon#read 4, iclass 19, count 0 2006.257.06:01:00.25#ibcon#about to read 5, iclass 19, count 0 2006.257.06:01:00.25#ibcon#read 5, iclass 19, count 0 2006.257.06:01:00.25#ibcon#about to read 6, iclass 19, count 0 2006.257.06:01:00.25#ibcon#read 6, iclass 19, count 0 2006.257.06:01:00.25#ibcon#end of sib2, iclass 19, count 0 2006.257.06:01:00.25#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:01:00.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:01:00.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:01:00.25#ibcon#*before write, iclass 19, count 0 2006.257.06:01:00.25#ibcon#enter sib2, iclass 19, count 0 2006.257.06:01:00.25#ibcon#flushed, iclass 19, count 0 2006.257.06:01:00.25#ibcon#about to write, iclass 19, count 0 2006.257.06:01:00.25#ibcon#wrote, iclass 19, count 0 2006.257.06:01:00.25#ibcon#about to read 3, iclass 19, count 0 2006.257.06:01:00.29#ibcon#read 3, iclass 19, count 0 2006.257.06:01:00.29#ibcon#about to read 4, iclass 19, count 0 2006.257.06:01:00.29#ibcon#read 4, iclass 19, count 0 2006.257.06:01:00.29#ibcon#about to read 5, iclass 19, count 0 2006.257.06:01:00.29#ibcon#read 5, iclass 19, count 0 2006.257.06:01:00.29#ibcon#about to read 6, iclass 19, count 0 2006.257.06:01:00.29#ibcon#read 6, iclass 19, count 0 2006.257.06:01:00.29#ibcon#end of sib2, iclass 19, count 0 2006.257.06:01:00.29#ibcon#*after write, iclass 19, count 0 2006.257.06:01:00.29#ibcon#*before return 0, iclass 19, count 0 2006.257.06:01:00.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:00.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:00.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:01:00.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:01:00.29$vck44/va=7,4 2006.257.06:01:00.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.06:01:00.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.06:01:00.29#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:00.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:00.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:00.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:00.35#ibcon#enter wrdev, iclass 21, count 2 2006.257.06:01:00.35#ibcon#first serial, iclass 21, count 2 2006.257.06:01:00.35#ibcon#enter sib2, iclass 21, count 2 2006.257.06:01:00.35#ibcon#flushed, iclass 21, count 2 2006.257.06:01:00.35#ibcon#about to write, iclass 21, count 2 2006.257.06:01:00.35#ibcon#wrote, iclass 21, count 2 2006.257.06:01:00.35#ibcon#about to read 3, iclass 21, count 2 2006.257.06:01:00.37#ibcon#read 3, iclass 21, count 2 2006.257.06:01:00.37#ibcon#about to read 4, iclass 21, count 2 2006.257.06:01:00.37#ibcon#read 4, iclass 21, count 2 2006.257.06:01:00.37#ibcon#about to read 5, iclass 21, count 2 2006.257.06:01:00.37#ibcon#read 5, iclass 21, count 2 2006.257.06:01:00.37#ibcon#about to read 6, iclass 21, count 2 2006.257.06:01:00.37#ibcon#read 6, iclass 21, count 2 2006.257.06:01:00.37#ibcon#end of sib2, iclass 21, count 2 2006.257.06:01:00.37#ibcon#*mode == 0, iclass 21, count 2 2006.257.06:01:00.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.06:01:00.37#ibcon#[25=AT07-04\r\n] 2006.257.06:01:00.37#ibcon#*before write, iclass 21, count 2 2006.257.06:01:00.37#ibcon#enter sib2, iclass 21, count 2 2006.257.06:01:00.37#ibcon#flushed, iclass 21, count 2 2006.257.06:01:00.37#ibcon#about to write, iclass 21, count 2 2006.257.06:01:00.37#ibcon#wrote, iclass 21, count 2 2006.257.06:01:00.37#ibcon#about to read 3, iclass 21, count 2 2006.257.06:01:00.40#ibcon#read 3, iclass 21, count 2 2006.257.06:01:00.40#ibcon#about to read 4, iclass 21, count 2 2006.257.06:01:00.40#ibcon#read 4, iclass 21, count 2 2006.257.06:01:00.40#ibcon#about to read 5, iclass 21, count 2 2006.257.06:01:00.40#ibcon#read 5, iclass 21, count 2 2006.257.06:01:00.40#ibcon#about to read 6, iclass 21, count 2 2006.257.06:01:00.40#ibcon#read 6, iclass 21, count 2 2006.257.06:01:00.40#ibcon#end of sib2, iclass 21, count 2 2006.257.06:01:00.40#ibcon#*after write, iclass 21, count 2 2006.257.06:01:00.40#ibcon#*before return 0, iclass 21, count 2 2006.257.06:01:00.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:00.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:00.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.06:01:00.40#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:00.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:00.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:00.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:00.52#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:01:00.52#ibcon#first serial, iclass 21, count 0 2006.257.06:01:00.52#ibcon#enter sib2, iclass 21, count 0 2006.257.06:01:00.52#ibcon#flushed, iclass 21, count 0 2006.257.06:01:00.52#ibcon#about to write, iclass 21, count 0 2006.257.06:01:00.52#ibcon#wrote, iclass 21, count 0 2006.257.06:01:00.52#ibcon#about to read 3, iclass 21, count 0 2006.257.06:01:00.54#ibcon#read 3, iclass 21, count 0 2006.257.06:01:00.54#ibcon#about to read 4, iclass 21, count 0 2006.257.06:01:00.54#ibcon#read 4, iclass 21, count 0 2006.257.06:01:00.54#ibcon#about to read 5, iclass 21, count 0 2006.257.06:01:00.54#ibcon#read 5, iclass 21, count 0 2006.257.06:01:00.54#ibcon#about to read 6, iclass 21, count 0 2006.257.06:01:00.54#ibcon#read 6, iclass 21, count 0 2006.257.06:01:00.54#ibcon#end of sib2, iclass 21, count 0 2006.257.06:01:00.54#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:01:00.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:01:00.54#ibcon#[25=USB\r\n] 2006.257.06:01:00.54#ibcon#*before write, iclass 21, count 0 2006.257.06:01:00.54#ibcon#enter sib2, iclass 21, count 0 2006.257.06:01:00.54#ibcon#flushed, iclass 21, count 0 2006.257.06:01:00.54#ibcon#about to write, iclass 21, count 0 2006.257.06:01:00.54#ibcon#wrote, iclass 21, count 0 2006.257.06:01:00.54#ibcon#about to read 3, iclass 21, count 0 2006.257.06:01:00.57#ibcon#read 3, iclass 21, count 0 2006.257.06:01:00.57#ibcon#about to read 4, iclass 21, count 0 2006.257.06:01:00.57#ibcon#read 4, iclass 21, count 0 2006.257.06:01:00.57#ibcon#about to read 5, iclass 21, count 0 2006.257.06:01:00.57#ibcon#read 5, iclass 21, count 0 2006.257.06:01:00.57#ibcon#about to read 6, iclass 21, count 0 2006.257.06:01:00.57#ibcon#read 6, iclass 21, count 0 2006.257.06:01:00.57#ibcon#end of sib2, iclass 21, count 0 2006.257.06:01:00.57#ibcon#*after write, iclass 21, count 0 2006.257.06:01:00.57#ibcon#*before return 0, iclass 21, count 0 2006.257.06:01:00.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:00.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:00.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:01:00.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:01:00.57$vck44/valo=8,884.99 2006.257.06:01:00.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.06:01:00.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.06:01:00.57#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:00.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:00.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:00.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:00.57#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:01:00.57#ibcon#first serial, iclass 23, count 0 2006.257.06:01:00.57#ibcon#enter sib2, iclass 23, count 0 2006.257.06:01:00.57#ibcon#flushed, iclass 23, count 0 2006.257.06:01:00.57#ibcon#about to write, iclass 23, count 0 2006.257.06:01:00.57#ibcon#wrote, iclass 23, count 0 2006.257.06:01:00.57#ibcon#about to read 3, iclass 23, count 0 2006.257.06:01:00.59#ibcon#read 3, iclass 23, count 0 2006.257.06:01:00.59#ibcon#about to read 4, iclass 23, count 0 2006.257.06:01:00.59#ibcon#read 4, iclass 23, count 0 2006.257.06:01:00.59#ibcon#about to read 5, iclass 23, count 0 2006.257.06:01:00.59#ibcon#read 5, iclass 23, count 0 2006.257.06:01:00.59#ibcon#about to read 6, iclass 23, count 0 2006.257.06:01:00.59#ibcon#read 6, iclass 23, count 0 2006.257.06:01:00.59#ibcon#end of sib2, iclass 23, count 0 2006.257.06:01:00.59#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:01:00.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:01:00.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:01:00.59#ibcon#*before write, iclass 23, count 0 2006.257.06:01:00.59#ibcon#enter sib2, iclass 23, count 0 2006.257.06:01:00.59#ibcon#flushed, iclass 23, count 0 2006.257.06:01:00.59#ibcon#about to write, iclass 23, count 0 2006.257.06:01:00.59#ibcon#wrote, iclass 23, count 0 2006.257.06:01:00.59#ibcon#about to read 3, iclass 23, count 0 2006.257.06:01:00.63#ibcon#read 3, iclass 23, count 0 2006.257.06:01:00.63#ibcon#about to read 4, iclass 23, count 0 2006.257.06:01:00.63#ibcon#read 4, iclass 23, count 0 2006.257.06:01:00.63#ibcon#about to read 5, iclass 23, count 0 2006.257.06:01:00.63#ibcon#read 5, iclass 23, count 0 2006.257.06:01:00.63#ibcon#about to read 6, iclass 23, count 0 2006.257.06:01:00.63#ibcon#read 6, iclass 23, count 0 2006.257.06:01:00.63#ibcon#end of sib2, iclass 23, count 0 2006.257.06:01:00.63#ibcon#*after write, iclass 23, count 0 2006.257.06:01:00.63#ibcon#*before return 0, iclass 23, count 0 2006.257.06:01:00.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:00.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:00.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:01:00.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:01:00.63$vck44/va=8,4 2006.257.06:01:00.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.06:01:00.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.06:01:00.63#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:00.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:00.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:00.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:00.69#ibcon#enter wrdev, iclass 25, count 2 2006.257.06:01:00.69#ibcon#first serial, iclass 25, count 2 2006.257.06:01:00.69#ibcon#enter sib2, iclass 25, count 2 2006.257.06:01:00.69#ibcon#flushed, iclass 25, count 2 2006.257.06:01:00.69#ibcon#about to write, iclass 25, count 2 2006.257.06:01:00.69#ibcon#wrote, iclass 25, count 2 2006.257.06:01:00.69#ibcon#about to read 3, iclass 25, count 2 2006.257.06:01:00.71#ibcon#read 3, iclass 25, count 2 2006.257.06:01:00.71#ibcon#about to read 4, iclass 25, count 2 2006.257.06:01:00.71#ibcon#read 4, iclass 25, count 2 2006.257.06:01:00.71#ibcon#about to read 5, iclass 25, count 2 2006.257.06:01:00.71#ibcon#read 5, iclass 25, count 2 2006.257.06:01:00.71#ibcon#about to read 6, iclass 25, count 2 2006.257.06:01:00.71#ibcon#read 6, iclass 25, count 2 2006.257.06:01:00.71#ibcon#end of sib2, iclass 25, count 2 2006.257.06:01:00.71#ibcon#*mode == 0, iclass 25, count 2 2006.257.06:01:00.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.06:01:00.71#ibcon#[25=AT08-04\r\n] 2006.257.06:01:00.71#ibcon#*before write, iclass 25, count 2 2006.257.06:01:00.71#ibcon#enter sib2, iclass 25, count 2 2006.257.06:01:00.71#ibcon#flushed, iclass 25, count 2 2006.257.06:01:00.71#ibcon#about to write, iclass 25, count 2 2006.257.06:01:00.71#ibcon#wrote, iclass 25, count 2 2006.257.06:01:00.71#ibcon#about to read 3, iclass 25, count 2 2006.257.06:01:00.74#ibcon#read 3, iclass 25, count 2 2006.257.06:01:00.74#ibcon#about to read 4, iclass 25, count 2 2006.257.06:01:00.74#ibcon#read 4, iclass 25, count 2 2006.257.06:01:00.74#ibcon#about to read 5, iclass 25, count 2 2006.257.06:01:00.74#ibcon#read 5, iclass 25, count 2 2006.257.06:01:00.74#ibcon#about to read 6, iclass 25, count 2 2006.257.06:01:00.74#ibcon#read 6, iclass 25, count 2 2006.257.06:01:00.74#ibcon#end of sib2, iclass 25, count 2 2006.257.06:01:00.74#ibcon#*after write, iclass 25, count 2 2006.257.06:01:00.74#ibcon#*before return 0, iclass 25, count 2 2006.257.06:01:00.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:00.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:00.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.06:01:00.74#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:00.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:00.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:00.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:00.86#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:01:00.86#ibcon#first serial, iclass 25, count 0 2006.257.06:01:00.86#ibcon#enter sib2, iclass 25, count 0 2006.257.06:01:00.86#ibcon#flushed, iclass 25, count 0 2006.257.06:01:00.86#ibcon#about to write, iclass 25, count 0 2006.257.06:01:00.86#ibcon#wrote, iclass 25, count 0 2006.257.06:01:00.86#ibcon#about to read 3, iclass 25, count 0 2006.257.06:01:00.88#ibcon#read 3, iclass 25, count 0 2006.257.06:01:00.88#ibcon#about to read 4, iclass 25, count 0 2006.257.06:01:00.88#ibcon#read 4, iclass 25, count 0 2006.257.06:01:00.88#ibcon#about to read 5, iclass 25, count 0 2006.257.06:01:00.88#ibcon#read 5, iclass 25, count 0 2006.257.06:01:00.88#ibcon#about to read 6, iclass 25, count 0 2006.257.06:01:00.88#ibcon#read 6, iclass 25, count 0 2006.257.06:01:00.88#ibcon#end of sib2, iclass 25, count 0 2006.257.06:01:00.88#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:01:00.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:01:00.88#ibcon#[25=USB\r\n] 2006.257.06:01:00.88#ibcon#*before write, iclass 25, count 0 2006.257.06:01:00.88#ibcon#enter sib2, iclass 25, count 0 2006.257.06:01:00.88#ibcon#flushed, iclass 25, count 0 2006.257.06:01:00.88#ibcon#about to write, iclass 25, count 0 2006.257.06:01:00.88#ibcon#wrote, iclass 25, count 0 2006.257.06:01:00.88#ibcon#about to read 3, iclass 25, count 0 2006.257.06:01:00.91#ibcon#read 3, iclass 25, count 0 2006.257.06:01:00.91#ibcon#about to read 4, iclass 25, count 0 2006.257.06:01:00.91#ibcon#read 4, iclass 25, count 0 2006.257.06:01:00.91#ibcon#about to read 5, iclass 25, count 0 2006.257.06:01:00.91#ibcon#read 5, iclass 25, count 0 2006.257.06:01:00.91#ibcon#about to read 6, iclass 25, count 0 2006.257.06:01:00.91#ibcon#read 6, iclass 25, count 0 2006.257.06:01:00.91#ibcon#end of sib2, iclass 25, count 0 2006.257.06:01:00.91#ibcon#*after write, iclass 25, count 0 2006.257.06:01:00.91#ibcon#*before return 0, iclass 25, count 0 2006.257.06:01:00.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:00.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:00.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:01:00.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:01:00.91$vck44/vblo=1,629.99 2006.257.06:01:00.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.06:01:00.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.06:01:00.91#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:00.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:00.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:00.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:00.91#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:01:00.91#ibcon#first serial, iclass 27, count 0 2006.257.06:01:00.91#ibcon#enter sib2, iclass 27, count 0 2006.257.06:01:00.91#ibcon#flushed, iclass 27, count 0 2006.257.06:01:00.91#ibcon#about to write, iclass 27, count 0 2006.257.06:01:00.91#ibcon#wrote, iclass 27, count 0 2006.257.06:01:00.91#ibcon#about to read 3, iclass 27, count 0 2006.257.06:01:00.93#ibcon#read 3, iclass 27, count 0 2006.257.06:01:00.93#ibcon#about to read 4, iclass 27, count 0 2006.257.06:01:00.93#ibcon#read 4, iclass 27, count 0 2006.257.06:01:00.93#ibcon#about to read 5, iclass 27, count 0 2006.257.06:01:00.93#ibcon#read 5, iclass 27, count 0 2006.257.06:01:00.93#ibcon#about to read 6, iclass 27, count 0 2006.257.06:01:00.93#ibcon#read 6, iclass 27, count 0 2006.257.06:01:00.93#ibcon#end of sib2, iclass 27, count 0 2006.257.06:01:00.93#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:01:00.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:01:00.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:01:00.93#ibcon#*before write, iclass 27, count 0 2006.257.06:01:00.93#ibcon#enter sib2, iclass 27, count 0 2006.257.06:01:00.93#ibcon#flushed, iclass 27, count 0 2006.257.06:01:00.93#ibcon#about to write, iclass 27, count 0 2006.257.06:01:00.93#ibcon#wrote, iclass 27, count 0 2006.257.06:01:00.93#ibcon#about to read 3, iclass 27, count 0 2006.257.06:01:00.97#ibcon#read 3, iclass 27, count 0 2006.257.06:01:00.97#ibcon#about to read 4, iclass 27, count 0 2006.257.06:01:00.97#ibcon#read 4, iclass 27, count 0 2006.257.06:01:00.97#ibcon#about to read 5, iclass 27, count 0 2006.257.06:01:00.97#ibcon#read 5, iclass 27, count 0 2006.257.06:01:00.97#ibcon#about to read 6, iclass 27, count 0 2006.257.06:01:00.97#ibcon#read 6, iclass 27, count 0 2006.257.06:01:00.97#ibcon#end of sib2, iclass 27, count 0 2006.257.06:01:00.97#ibcon#*after write, iclass 27, count 0 2006.257.06:01:00.97#ibcon#*before return 0, iclass 27, count 0 2006.257.06:01:00.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:00.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:00.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:01:00.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:01:00.97$vck44/vb=1,4 2006.257.06:01:00.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.06:01:00.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.06:01:00.97#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:00.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:01:00.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:01:00.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:01:00.97#ibcon#enter wrdev, iclass 29, count 2 2006.257.06:01:00.97#ibcon#first serial, iclass 29, count 2 2006.257.06:01:00.97#ibcon#enter sib2, iclass 29, count 2 2006.257.06:01:00.97#ibcon#flushed, iclass 29, count 2 2006.257.06:01:00.97#ibcon#about to write, iclass 29, count 2 2006.257.06:01:00.97#ibcon#wrote, iclass 29, count 2 2006.257.06:01:00.97#ibcon#about to read 3, iclass 29, count 2 2006.257.06:01:00.99#ibcon#read 3, iclass 29, count 2 2006.257.06:01:00.99#ibcon#about to read 4, iclass 29, count 2 2006.257.06:01:00.99#ibcon#read 4, iclass 29, count 2 2006.257.06:01:00.99#ibcon#about to read 5, iclass 29, count 2 2006.257.06:01:00.99#ibcon#read 5, iclass 29, count 2 2006.257.06:01:00.99#ibcon#about to read 6, iclass 29, count 2 2006.257.06:01:00.99#ibcon#read 6, iclass 29, count 2 2006.257.06:01:00.99#ibcon#end of sib2, iclass 29, count 2 2006.257.06:01:00.99#ibcon#*mode == 0, iclass 29, count 2 2006.257.06:01:00.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.06:01:00.99#ibcon#[27=AT01-04\r\n] 2006.257.06:01:00.99#ibcon#*before write, iclass 29, count 2 2006.257.06:01:00.99#ibcon#enter sib2, iclass 29, count 2 2006.257.06:01:00.99#ibcon#flushed, iclass 29, count 2 2006.257.06:01:00.99#ibcon#about to write, iclass 29, count 2 2006.257.06:01:00.99#ibcon#wrote, iclass 29, count 2 2006.257.06:01:00.99#ibcon#about to read 3, iclass 29, count 2 2006.257.06:01:01.02#ibcon#read 3, iclass 29, count 2 2006.257.06:01:01.02#ibcon#about to read 4, iclass 29, count 2 2006.257.06:01:01.02#ibcon#read 4, iclass 29, count 2 2006.257.06:01:01.02#ibcon#about to read 5, iclass 29, count 2 2006.257.06:01:01.02#ibcon#read 5, iclass 29, count 2 2006.257.06:01:01.02#ibcon#about to read 6, iclass 29, count 2 2006.257.06:01:01.02#ibcon#read 6, iclass 29, count 2 2006.257.06:01:01.02#ibcon#end of sib2, iclass 29, count 2 2006.257.06:01:01.02#ibcon#*after write, iclass 29, count 2 2006.257.06:01:01.02#ibcon#*before return 0, iclass 29, count 2 2006.257.06:01:01.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:01:01.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:01:01.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.06:01:01.02#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:01.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:01:01.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:01:01.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:01:01.14#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:01:01.14#ibcon#first serial, iclass 29, count 0 2006.257.06:01:01.14#ibcon#enter sib2, iclass 29, count 0 2006.257.06:01:01.14#ibcon#flushed, iclass 29, count 0 2006.257.06:01:01.14#ibcon#about to write, iclass 29, count 0 2006.257.06:01:01.14#ibcon#wrote, iclass 29, count 0 2006.257.06:01:01.14#ibcon#about to read 3, iclass 29, count 0 2006.257.06:01:01.16#ibcon#read 3, iclass 29, count 0 2006.257.06:01:01.16#ibcon#about to read 4, iclass 29, count 0 2006.257.06:01:01.16#ibcon#read 4, iclass 29, count 0 2006.257.06:01:01.16#ibcon#about to read 5, iclass 29, count 0 2006.257.06:01:01.16#ibcon#read 5, iclass 29, count 0 2006.257.06:01:01.16#ibcon#about to read 6, iclass 29, count 0 2006.257.06:01:01.16#ibcon#read 6, iclass 29, count 0 2006.257.06:01:01.16#ibcon#end of sib2, iclass 29, count 0 2006.257.06:01:01.16#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:01:01.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:01:01.16#ibcon#[27=USB\r\n] 2006.257.06:01:01.16#ibcon#*before write, iclass 29, count 0 2006.257.06:01:01.16#ibcon#enter sib2, iclass 29, count 0 2006.257.06:01:01.16#ibcon#flushed, iclass 29, count 0 2006.257.06:01:01.16#ibcon#about to write, iclass 29, count 0 2006.257.06:01:01.16#ibcon#wrote, iclass 29, count 0 2006.257.06:01:01.16#ibcon#about to read 3, iclass 29, count 0 2006.257.06:01:01.19#ibcon#read 3, iclass 29, count 0 2006.257.06:01:01.19#ibcon#about to read 4, iclass 29, count 0 2006.257.06:01:01.19#ibcon#read 4, iclass 29, count 0 2006.257.06:01:01.19#ibcon#about to read 5, iclass 29, count 0 2006.257.06:01:01.19#ibcon#read 5, iclass 29, count 0 2006.257.06:01:01.19#ibcon#about to read 6, iclass 29, count 0 2006.257.06:01:01.19#ibcon#read 6, iclass 29, count 0 2006.257.06:01:01.19#ibcon#end of sib2, iclass 29, count 0 2006.257.06:01:01.19#ibcon#*after write, iclass 29, count 0 2006.257.06:01:01.19#ibcon#*before return 0, iclass 29, count 0 2006.257.06:01:01.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:01:01.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:01:01.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:01:01.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:01:01.19$vck44/vblo=2,634.99 2006.257.06:01:01.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.06:01:01.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.06:01:01.19#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:01.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:01:01.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:01:01.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:01:01.19#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:01:01.19#ibcon#first serial, iclass 31, count 0 2006.257.06:01:01.19#ibcon#enter sib2, iclass 31, count 0 2006.257.06:01:01.19#ibcon#flushed, iclass 31, count 0 2006.257.06:01:01.19#ibcon#about to write, iclass 31, count 0 2006.257.06:01:01.19#ibcon#wrote, iclass 31, count 0 2006.257.06:01:01.19#ibcon#about to read 3, iclass 31, count 0 2006.257.06:01:01.21#ibcon#read 3, iclass 31, count 0 2006.257.06:01:01.21#ibcon#about to read 4, iclass 31, count 0 2006.257.06:01:01.21#ibcon#read 4, iclass 31, count 0 2006.257.06:01:01.21#ibcon#about to read 5, iclass 31, count 0 2006.257.06:01:01.21#ibcon#read 5, iclass 31, count 0 2006.257.06:01:01.21#ibcon#about to read 6, iclass 31, count 0 2006.257.06:01:01.21#ibcon#read 6, iclass 31, count 0 2006.257.06:01:01.21#ibcon#end of sib2, iclass 31, count 0 2006.257.06:01:01.21#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:01:01.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:01:01.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:01:01.21#ibcon#*before write, iclass 31, count 0 2006.257.06:01:01.21#ibcon#enter sib2, iclass 31, count 0 2006.257.06:01:01.21#ibcon#flushed, iclass 31, count 0 2006.257.06:01:01.21#ibcon#about to write, iclass 31, count 0 2006.257.06:01:01.21#ibcon#wrote, iclass 31, count 0 2006.257.06:01:01.21#ibcon#about to read 3, iclass 31, count 0 2006.257.06:01:01.25#ibcon#read 3, iclass 31, count 0 2006.257.06:01:01.25#ibcon#about to read 4, iclass 31, count 0 2006.257.06:01:01.25#ibcon#read 4, iclass 31, count 0 2006.257.06:01:01.25#ibcon#about to read 5, iclass 31, count 0 2006.257.06:01:01.25#ibcon#read 5, iclass 31, count 0 2006.257.06:01:01.25#ibcon#about to read 6, iclass 31, count 0 2006.257.06:01:01.25#ibcon#read 6, iclass 31, count 0 2006.257.06:01:01.25#ibcon#end of sib2, iclass 31, count 0 2006.257.06:01:01.25#ibcon#*after write, iclass 31, count 0 2006.257.06:01:01.25#ibcon#*before return 0, iclass 31, count 0 2006.257.06:01:01.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:01:01.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:01:01.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:01:01.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:01:01.25$vck44/vb=2,5 2006.257.06:01:01.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.06:01:01.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.06:01:01.25#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:01.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:01:01.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:01:01.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:01:01.31#ibcon#enter wrdev, iclass 33, count 2 2006.257.06:01:01.31#ibcon#first serial, iclass 33, count 2 2006.257.06:01:01.31#ibcon#enter sib2, iclass 33, count 2 2006.257.06:01:01.31#ibcon#flushed, iclass 33, count 2 2006.257.06:01:01.31#ibcon#about to write, iclass 33, count 2 2006.257.06:01:01.31#ibcon#wrote, iclass 33, count 2 2006.257.06:01:01.31#ibcon#about to read 3, iclass 33, count 2 2006.257.06:01:01.33#ibcon#read 3, iclass 33, count 2 2006.257.06:01:01.33#ibcon#about to read 4, iclass 33, count 2 2006.257.06:01:01.33#ibcon#read 4, iclass 33, count 2 2006.257.06:01:01.33#ibcon#about to read 5, iclass 33, count 2 2006.257.06:01:01.33#ibcon#read 5, iclass 33, count 2 2006.257.06:01:01.33#ibcon#about to read 6, iclass 33, count 2 2006.257.06:01:01.33#ibcon#read 6, iclass 33, count 2 2006.257.06:01:01.33#ibcon#end of sib2, iclass 33, count 2 2006.257.06:01:01.33#ibcon#*mode == 0, iclass 33, count 2 2006.257.06:01:01.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.06:01:01.33#ibcon#[27=AT02-05\r\n] 2006.257.06:01:01.33#ibcon#*before write, iclass 33, count 2 2006.257.06:01:01.33#ibcon#enter sib2, iclass 33, count 2 2006.257.06:01:01.33#ibcon#flushed, iclass 33, count 2 2006.257.06:01:01.33#ibcon#about to write, iclass 33, count 2 2006.257.06:01:01.33#ibcon#wrote, iclass 33, count 2 2006.257.06:01:01.33#ibcon#about to read 3, iclass 33, count 2 2006.257.06:01:01.36#ibcon#read 3, iclass 33, count 2 2006.257.06:01:01.36#ibcon#about to read 4, iclass 33, count 2 2006.257.06:01:01.36#ibcon#read 4, iclass 33, count 2 2006.257.06:01:01.36#ibcon#about to read 5, iclass 33, count 2 2006.257.06:01:01.36#ibcon#read 5, iclass 33, count 2 2006.257.06:01:01.36#ibcon#about to read 6, iclass 33, count 2 2006.257.06:01:01.36#ibcon#read 6, iclass 33, count 2 2006.257.06:01:01.36#ibcon#end of sib2, iclass 33, count 2 2006.257.06:01:01.36#ibcon#*after write, iclass 33, count 2 2006.257.06:01:01.36#ibcon#*before return 0, iclass 33, count 2 2006.257.06:01:01.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:01:01.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:01:01.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.06:01:01.36#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:01.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:01:01.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:01:01.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:01:01.48#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:01:01.48#ibcon#first serial, iclass 33, count 0 2006.257.06:01:01.48#ibcon#enter sib2, iclass 33, count 0 2006.257.06:01:01.48#ibcon#flushed, iclass 33, count 0 2006.257.06:01:01.48#ibcon#about to write, iclass 33, count 0 2006.257.06:01:01.48#ibcon#wrote, iclass 33, count 0 2006.257.06:01:01.48#ibcon#about to read 3, iclass 33, count 0 2006.257.06:01:01.50#ibcon#read 3, iclass 33, count 0 2006.257.06:01:01.50#ibcon#about to read 4, iclass 33, count 0 2006.257.06:01:01.50#ibcon#read 4, iclass 33, count 0 2006.257.06:01:01.50#ibcon#about to read 5, iclass 33, count 0 2006.257.06:01:01.50#ibcon#read 5, iclass 33, count 0 2006.257.06:01:01.50#ibcon#about to read 6, iclass 33, count 0 2006.257.06:01:01.50#ibcon#read 6, iclass 33, count 0 2006.257.06:01:01.50#ibcon#end of sib2, iclass 33, count 0 2006.257.06:01:01.50#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:01:01.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:01:01.50#ibcon#[27=USB\r\n] 2006.257.06:01:01.50#ibcon#*before write, iclass 33, count 0 2006.257.06:01:01.50#ibcon#enter sib2, iclass 33, count 0 2006.257.06:01:01.50#ibcon#flushed, iclass 33, count 0 2006.257.06:01:01.50#ibcon#about to write, iclass 33, count 0 2006.257.06:01:01.50#ibcon#wrote, iclass 33, count 0 2006.257.06:01:01.50#ibcon#about to read 3, iclass 33, count 0 2006.257.06:01:01.53#ibcon#read 3, iclass 33, count 0 2006.257.06:01:01.53#ibcon#about to read 4, iclass 33, count 0 2006.257.06:01:01.53#ibcon#read 4, iclass 33, count 0 2006.257.06:01:01.53#ibcon#about to read 5, iclass 33, count 0 2006.257.06:01:01.53#ibcon#read 5, iclass 33, count 0 2006.257.06:01:01.53#ibcon#about to read 6, iclass 33, count 0 2006.257.06:01:01.53#ibcon#read 6, iclass 33, count 0 2006.257.06:01:01.53#ibcon#end of sib2, iclass 33, count 0 2006.257.06:01:01.53#ibcon#*after write, iclass 33, count 0 2006.257.06:01:01.53#ibcon#*before return 0, iclass 33, count 0 2006.257.06:01:01.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:01:01.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:01:01.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:01:01.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:01:01.53$vck44/vblo=3,649.99 2006.257.06:01:01.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:01:01.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:01:01.53#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:01.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:01:01.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:01:01.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:01:01.53#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:01:01.53#ibcon#first serial, iclass 35, count 0 2006.257.06:01:01.53#ibcon#enter sib2, iclass 35, count 0 2006.257.06:01:01.53#ibcon#flushed, iclass 35, count 0 2006.257.06:01:01.53#ibcon#about to write, iclass 35, count 0 2006.257.06:01:01.53#ibcon#wrote, iclass 35, count 0 2006.257.06:01:01.53#ibcon#about to read 3, iclass 35, count 0 2006.257.06:01:01.55#ibcon#read 3, iclass 35, count 0 2006.257.06:01:01.55#ibcon#about to read 4, iclass 35, count 0 2006.257.06:01:01.55#ibcon#read 4, iclass 35, count 0 2006.257.06:01:01.55#ibcon#about to read 5, iclass 35, count 0 2006.257.06:01:01.55#ibcon#read 5, iclass 35, count 0 2006.257.06:01:01.55#ibcon#about to read 6, iclass 35, count 0 2006.257.06:01:01.55#ibcon#read 6, iclass 35, count 0 2006.257.06:01:01.55#ibcon#end of sib2, iclass 35, count 0 2006.257.06:01:01.55#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:01:01.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:01:01.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:01:01.55#ibcon#*before write, iclass 35, count 0 2006.257.06:01:01.55#ibcon#enter sib2, iclass 35, count 0 2006.257.06:01:01.55#ibcon#flushed, iclass 35, count 0 2006.257.06:01:01.55#ibcon#about to write, iclass 35, count 0 2006.257.06:01:01.55#ibcon#wrote, iclass 35, count 0 2006.257.06:01:01.55#ibcon#about to read 3, iclass 35, count 0 2006.257.06:01:01.59#ibcon#read 3, iclass 35, count 0 2006.257.06:01:01.59#ibcon#about to read 4, iclass 35, count 0 2006.257.06:01:01.59#ibcon#read 4, iclass 35, count 0 2006.257.06:01:01.59#ibcon#about to read 5, iclass 35, count 0 2006.257.06:01:01.59#ibcon#read 5, iclass 35, count 0 2006.257.06:01:01.59#ibcon#about to read 6, iclass 35, count 0 2006.257.06:01:01.59#ibcon#read 6, iclass 35, count 0 2006.257.06:01:01.59#ibcon#end of sib2, iclass 35, count 0 2006.257.06:01:01.59#ibcon#*after write, iclass 35, count 0 2006.257.06:01:01.59#ibcon#*before return 0, iclass 35, count 0 2006.257.06:01:01.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:01:01.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:01:01.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:01:01.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:01:01.59$vck44/vb=3,4 2006.257.06:01:01.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.06:01:01.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.06:01:01.59#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:01.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:01:01.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:01:01.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:01:01.65#ibcon#enter wrdev, iclass 37, count 2 2006.257.06:01:01.65#ibcon#first serial, iclass 37, count 2 2006.257.06:01:01.65#ibcon#enter sib2, iclass 37, count 2 2006.257.06:01:01.65#ibcon#flushed, iclass 37, count 2 2006.257.06:01:01.65#ibcon#about to write, iclass 37, count 2 2006.257.06:01:01.65#ibcon#wrote, iclass 37, count 2 2006.257.06:01:01.65#ibcon#about to read 3, iclass 37, count 2 2006.257.06:01:01.67#ibcon#read 3, iclass 37, count 2 2006.257.06:01:01.67#ibcon#about to read 4, iclass 37, count 2 2006.257.06:01:01.67#ibcon#read 4, iclass 37, count 2 2006.257.06:01:01.67#ibcon#about to read 5, iclass 37, count 2 2006.257.06:01:01.67#ibcon#read 5, iclass 37, count 2 2006.257.06:01:01.67#ibcon#about to read 6, iclass 37, count 2 2006.257.06:01:01.67#ibcon#read 6, iclass 37, count 2 2006.257.06:01:01.67#ibcon#end of sib2, iclass 37, count 2 2006.257.06:01:01.67#ibcon#*mode == 0, iclass 37, count 2 2006.257.06:01:01.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.06:01:01.67#ibcon#[27=AT03-04\r\n] 2006.257.06:01:01.67#ibcon#*before write, iclass 37, count 2 2006.257.06:01:01.67#ibcon#enter sib2, iclass 37, count 2 2006.257.06:01:01.67#ibcon#flushed, iclass 37, count 2 2006.257.06:01:01.67#ibcon#about to write, iclass 37, count 2 2006.257.06:01:01.67#ibcon#wrote, iclass 37, count 2 2006.257.06:01:01.67#ibcon#about to read 3, iclass 37, count 2 2006.257.06:01:01.70#ibcon#read 3, iclass 37, count 2 2006.257.06:01:01.70#ibcon#about to read 4, iclass 37, count 2 2006.257.06:01:01.70#ibcon#read 4, iclass 37, count 2 2006.257.06:01:01.70#ibcon#about to read 5, iclass 37, count 2 2006.257.06:01:01.70#ibcon#read 5, iclass 37, count 2 2006.257.06:01:01.70#ibcon#about to read 6, iclass 37, count 2 2006.257.06:01:01.70#ibcon#read 6, iclass 37, count 2 2006.257.06:01:01.70#ibcon#end of sib2, iclass 37, count 2 2006.257.06:01:01.70#ibcon#*after write, iclass 37, count 2 2006.257.06:01:01.70#ibcon#*before return 0, iclass 37, count 2 2006.257.06:01:01.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:01:01.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:01:01.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.06:01:01.70#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:01.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:01:01.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:01:01.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:01:01.82#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:01:01.82#ibcon#first serial, iclass 37, count 0 2006.257.06:01:01.82#ibcon#enter sib2, iclass 37, count 0 2006.257.06:01:01.82#ibcon#flushed, iclass 37, count 0 2006.257.06:01:01.82#ibcon#about to write, iclass 37, count 0 2006.257.06:01:01.82#ibcon#wrote, iclass 37, count 0 2006.257.06:01:01.82#ibcon#about to read 3, iclass 37, count 0 2006.257.06:01:01.84#ibcon#read 3, iclass 37, count 0 2006.257.06:01:01.84#ibcon#about to read 4, iclass 37, count 0 2006.257.06:01:01.84#ibcon#read 4, iclass 37, count 0 2006.257.06:01:01.84#ibcon#about to read 5, iclass 37, count 0 2006.257.06:01:01.84#ibcon#read 5, iclass 37, count 0 2006.257.06:01:01.84#ibcon#about to read 6, iclass 37, count 0 2006.257.06:01:01.84#ibcon#read 6, iclass 37, count 0 2006.257.06:01:01.84#ibcon#end of sib2, iclass 37, count 0 2006.257.06:01:01.84#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:01:01.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:01:01.84#ibcon#[27=USB\r\n] 2006.257.06:01:01.84#ibcon#*before write, iclass 37, count 0 2006.257.06:01:01.84#ibcon#enter sib2, iclass 37, count 0 2006.257.06:01:01.84#ibcon#flushed, iclass 37, count 0 2006.257.06:01:01.84#ibcon#about to write, iclass 37, count 0 2006.257.06:01:01.84#ibcon#wrote, iclass 37, count 0 2006.257.06:01:01.84#ibcon#about to read 3, iclass 37, count 0 2006.257.06:01:01.87#ibcon#read 3, iclass 37, count 0 2006.257.06:01:01.87#ibcon#about to read 4, iclass 37, count 0 2006.257.06:01:01.87#ibcon#read 4, iclass 37, count 0 2006.257.06:01:01.87#ibcon#about to read 5, iclass 37, count 0 2006.257.06:01:01.87#ibcon#read 5, iclass 37, count 0 2006.257.06:01:01.87#ibcon#about to read 6, iclass 37, count 0 2006.257.06:01:01.87#ibcon#read 6, iclass 37, count 0 2006.257.06:01:01.87#ibcon#end of sib2, iclass 37, count 0 2006.257.06:01:01.87#ibcon#*after write, iclass 37, count 0 2006.257.06:01:01.87#ibcon#*before return 0, iclass 37, count 0 2006.257.06:01:01.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:01:01.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:01:01.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:01:01.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:01:01.87$vck44/vblo=4,679.99 2006.257.06:01:01.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.06:01:01.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.06:01:01.87#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:01.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:01:01.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:01:01.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:01:01.87#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:01:01.87#ibcon#first serial, iclass 39, count 0 2006.257.06:01:01.87#ibcon#enter sib2, iclass 39, count 0 2006.257.06:01:01.87#ibcon#flushed, iclass 39, count 0 2006.257.06:01:01.87#ibcon#about to write, iclass 39, count 0 2006.257.06:01:01.87#ibcon#wrote, iclass 39, count 0 2006.257.06:01:01.87#ibcon#about to read 3, iclass 39, count 0 2006.257.06:01:01.89#ibcon#read 3, iclass 39, count 0 2006.257.06:01:01.89#ibcon#about to read 4, iclass 39, count 0 2006.257.06:01:01.89#ibcon#read 4, iclass 39, count 0 2006.257.06:01:01.89#ibcon#about to read 5, iclass 39, count 0 2006.257.06:01:01.89#ibcon#read 5, iclass 39, count 0 2006.257.06:01:01.89#ibcon#about to read 6, iclass 39, count 0 2006.257.06:01:01.89#ibcon#read 6, iclass 39, count 0 2006.257.06:01:01.89#ibcon#end of sib2, iclass 39, count 0 2006.257.06:01:01.89#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:01:01.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:01:01.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:01:01.89#ibcon#*before write, iclass 39, count 0 2006.257.06:01:01.89#ibcon#enter sib2, iclass 39, count 0 2006.257.06:01:01.89#ibcon#flushed, iclass 39, count 0 2006.257.06:01:01.89#ibcon#about to write, iclass 39, count 0 2006.257.06:01:01.89#ibcon#wrote, iclass 39, count 0 2006.257.06:01:01.89#ibcon#about to read 3, iclass 39, count 0 2006.257.06:01:01.93#ibcon#read 3, iclass 39, count 0 2006.257.06:01:01.93#ibcon#about to read 4, iclass 39, count 0 2006.257.06:01:01.93#ibcon#read 4, iclass 39, count 0 2006.257.06:01:01.93#ibcon#about to read 5, iclass 39, count 0 2006.257.06:01:01.93#ibcon#read 5, iclass 39, count 0 2006.257.06:01:01.93#ibcon#about to read 6, iclass 39, count 0 2006.257.06:01:01.93#ibcon#read 6, iclass 39, count 0 2006.257.06:01:01.93#ibcon#end of sib2, iclass 39, count 0 2006.257.06:01:01.93#ibcon#*after write, iclass 39, count 0 2006.257.06:01:01.93#ibcon#*before return 0, iclass 39, count 0 2006.257.06:01:01.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:01:01.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:01:01.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:01:01.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:01:01.93$vck44/vb=4,5 2006.257.06:01:01.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.06:01:01.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.06:01:01.93#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:01.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:01:01.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:01:01.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:01:01.99#ibcon#enter wrdev, iclass 3, count 2 2006.257.06:01:01.99#ibcon#first serial, iclass 3, count 2 2006.257.06:01:01.99#ibcon#enter sib2, iclass 3, count 2 2006.257.06:01:01.99#ibcon#flushed, iclass 3, count 2 2006.257.06:01:01.99#ibcon#about to write, iclass 3, count 2 2006.257.06:01:01.99#ibcon#wrote, iclass 3, count 2 2006.257.06:01:01.99#ibcon#about to read 3, iclass 3, count 2 2006.257.06:01:02.01#ibcon#read 3, iclass 3, count 2 2006.257.06:01:02.01#ibcon#about to read 4, iclass 3, count 2 2006.257.06:01:02.01#ibcon#read 4, iclass 3, count 2 2006.257.06:01:02.01#ibcon#about to read 5, iclass 3, count 2 2006.257.06:01:02.01#ibcon#read 5, iclass 3, count 2 2006.257.06:01:02.01#ibcon#about to read 6, iclass 3, count 2 2006.257.06:01:02.01#ibcon#read 6, iclass 3, count 2 2006.257.06:01:02.01#ibcon#end of sib2, iclass 3, count 2 2006.257.06:01:02.01#ibcon#*mode == 0, iclass 3, count 2 2006.257.06:01:02.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.06:01:02.01#ibcon#[27=AT04-05\r\n] 2006.257.06:01:02.01#ibcon#*before write, iclass 3, count 2 2006.257.06:01:02.01#ibcon#enter sib2, iclass 3, count 2 2006.257.06:01:02.01#ibcon#flushed, iclass 3, count 2 2006.257.06:01:02.01#ibcon#about to write, iclass 3, count 2 2006.257.06:01:02.01#ibcon#wrote, iclass 3, count 2 2006.257.06:01:02.01#ibcon#about to read 3, iclass 3, count 2 2006.257.06:01:02.04#ibcon#read 3, iclass 3, count 2 2006.257.06:01:02.04#ibcon#about to read 4, iclass 3, count 2 2006.257.06:01:02.04#ibcon#read 4, iclass 3, count 2 2006.257.06:01:02.04#ibcon#about to read 5, iclass 3, count 2 2006.257.06:01:02.04#ibcon#read 5, iclass 3, count 2 2006.257.06:01:02.04#ibcon#about to read 6, iclass 3, count 2 2006.257.06:01:02.04#ibcon#read 6, iclass 3, count 2 2006.257.06:01:02.04#ibcon#end of sib2, iclass 3, count 2 2006.257.06:01:02.04#ibcon#*after write, iclass 3, count 2 2006.257.06:01:02.04#ibcon#*before return 0, iclass 3, count 2 2006.257.06:01:02.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:01:02.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:01:02.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.06:01:02.04#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:02.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:01:02.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:01:02.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:01:02.16#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:01:02.16#ibcon#first serial, iclass 3, count 0 2006.257.06:01:02.16#ibcon#enter sib2, iclass 3, count 0 2006.257.06:01:02.16#ibcon#flushed, iclass 3, count 0 2006.257.06:01:02.16#ibcon#about to write, iclass 3, count 0 2006.257.06:01:02.16#ibcon#wrote, iclass 3, count 0 2006.257.06:01:02.16#ibcon#about to read 3, iclass 3, count 0 2006.257.06:01:02.18#ibcon#read 3, iclass 3, count 0 2006.257.06:01:02.18#ibcon#about to read 4, iclass 3, count 0 2006.257.06:01:02.18#ibcon#read 4, iclass 3, count 0 2006.257.06:01:02.18#ibcon#about to read 5, iclass 3, count 0 2006.257.06:01:02.18#ibcon#read 5, iclass 3, count 0 2006.257.06:01:02.18#ibcon#about to read 6, iclass 3, count 0 2006.257.06:01:02.18#ibcon#read 6, iclass 3, count 0 2006.257.06:01:02.18#ibcon#end of sib2, iclass 3, count 0 2006.257.06:01:02.18#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:01:02.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:01:02.18#ibcon#[27=USB\r\n] 2006.257.06:01:02.18#ibcon#*before write, iclass 3, count 0 2006.257.06:01:02.18#ibcon#enter sib2, iclass 3, count 0 2006.257.06:01:02.18#ibcon#flushed, iclass 3, count 0 2006.257.06:01:02.18#ibcon#about to write, iclass 3, count 0 2006.257.06:01:02.18#ibcon#wrote, iclass 3, count 0 2006.257.06:01:02.18#ibcon#about to read 3, iclass 3, count 0 2006.257.06:01:02.21#ibcon#read 3, iclass 3, count 0 2006.257.06:01:02.21#ibcon#about to read 4, iclass 3, count 0 2006.257.06:01:02.21#ibcon#read 4, iclass 3, count 0 2006.257.06:01:02.21#ibcon#about to read 5, iclass 3, count 0 2006.257.06:01:02.21#ibcon#read 5, iclass 3, count 0 2006.257.06:01:02.21#ibcon#about to read 6, iclass 3, count 0 2006.257.06:01:02.21#ibcon#read 6, iclass 3, count 0 2006.257.06:01:02.21#ibcon#end of sib2, iclass 3, count 0 2006.257.06:01:02.21#ibcon#*after write, iclass 3, count 0 2006.257.06:01:02.21#ibcon#*before return 0, iclass 3, count 0 2006.257.06:01:02.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:01:02.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:01:02.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:01:02.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:01:02.21$vck44/vblo=5,709.99 2006.257.06:01:02.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.06:01:02.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.06:01:02.21#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:02.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:01:02.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:01:02.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:01:02.21#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:01:02.21#ibcon#first serial, iclass 5, count 0 2006.257.06:01:02.21#ibcon#enter sib2, iclass 5, count 0 2006.257.06:01:02.21#ibcon#flushed, iclass 5, count 0 2006.257.06:01:02.21#ibcon#about to write, iclass 5, count 0 2006.257.06:01:02.21#ibcon#wrote, iclass 5, count 0 2006.257.06:01:02.21#ibcon#about to read 3, iclass 5, count 0 2006.257.06:01:02.23#ibcon#read 3, iclass 5, count 0 2006.257.06:01:02.23#ibcon#about to read 4, iclass 5, count 0 2006.257.06:01:02.23#ibcon#read 4, iclass 5, count 0 2006.257.06:01:02.23#ibcon#about to read 5, iclass 5, count 0 2006.257.06:01:02.23#ibcon#read 5, iclass 5, count 0 2006.257.06:01:02.23#ibcon#about to read 6, iclass 5, count 0 2006.257.06:01:02.23#ibcon#read 6, iclass 5, count 0 2006.257.06:01:02.23#ibcon#end of sib2, iclass 5, count 0 2006.257.06:01:02.23#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:01:02.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:01:02.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:01:02.23#ibcon#*before write, iclass 5, count 0 2006.257.06:01:02.23#ibcon#enter sib2, iclass 5, count 0 2006.257.06:01:02.23#ibcon#flushed, iclass 5, count 0 2006.257.06:01:02.23#ibcon#about to write, iclass 5, count 0 2006.257.06:01:02.23#ibcon#wrote, iclass 5, count 0 2006.257.06:01:02.23#ibcon#about to read 3, iclass 5, count 0 2006.257.06:01:02.27#ibcon#read 3, iclass 5, count 0 2006.257.06:01:02.27#ibcon#about to read 4, iclass 5, count 0 2006.257.06:01:02.27#ibcon#read 4, iclass 5, count 0 2006.257.06:01:02.27#ibcon#about to read 5, iclass 5, count 0 2006.257.06:01:02.27#ibcon#read 5, iclass 5, count 0 2006.257.06:01:02.27#ibcon#about to read 6, iclass 5, count 0 2006.257.06:01:02.27#ibcon#read 6, iclass 5, count 0 2006.257.06:01:02.27#ibcon#end of sib2, iclass 5, count 0 2006.257.06:01:02.27#ibcon#*after write, iclass 5, count 0 2006.257.06:01:02.27#ibcon#*before return 0, iclass 5, count 0 2006.257.06:01:02.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:01:02.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:01:02.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:01:02.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:01:02.27$vck44/vb=5,4 2006.257.06:01:02.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.06:01:02.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.06:01:02.27#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:02.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:01:02.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:01:02.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:01:02.33#ibcon#enter wrdev, iclass 7, count 2 2006.257.06:01:02.33#ibcon#first serial, iclass 7, count 2 2006.257.06:01:02.33#ibcon#enter sib2, iclass 7, count 2 2006.257.06:01:02.33#ibcon#flushed, iclass 7, count 2 2006.257.06:01:02.33#ibcon#about to write, iclass 7, count 2 2006.257.06:01:02.33#ibcon#wrote, iclass 7, count 2 2006.257.06:01:02.33#ibcon#about to read 3, iclass 7, count 2 2006.257.06:01:02.35#ibcon#read 3, iclass 7, count 2 2006.257.06:01:02.35#ibcon#about to read 4, iclass 7, count 2 2006.257.06:01:02.35#ibcon#read 4, iclass 7, count 2 2006.257.06:01:02.35#ibcon#about to read 5, iclass 7, count 2 2006.257.06:01:02.35#ibcon#read 5, iclass 7, count 2 2006.257.06:01:02.35#ibcon#about to read 6, iclass 7, count 2 2006.257.06:01:02.35#ibcon#read 6, iclass 7, count 2 2006.257.06:01:02.35#ibcon#end of sib2, iclass 7, count 2 2006.257.06:01:02.35#ibcon#*mode == 0, iclass 7, count 2 2006.257.06:01:02.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.06:01:02.35#ibcon#[27=AT05-04\r\n] 2006.257.06:01:02.35#ibcon#*before write, iclass 7, count 2 2006.257.06:01:02.35#ibcon#enter sib2, iclass 7, count 2 2006.257.06:01:02.35#ibcon#flushed, iclass 7, count 2 2006.257.06:01:02.35#ibcon#about to write, iclass 7, count 2 2006.257.06:01:02.35#ibcon#wrote, iclass 7, count 2 2006.257.06:01:02.35#ibcon#about to read 3, iclass 7, count 2 2006.257.06:01:02.38#ibcon#read 3, iclass 7, count 2 2006.257.06:01:02.38#ibcon#about to read 4, iclass 7, count 2 2006.257.06:01:02.38#ibcon#read 4, iclass 7, count 2 2006.257.06:01:02.38#ibcon#about to read 5, iclass 7, count 2 2006.257.06:01:02.38#ibcon#read 5, iclass 7, count 2 2006.257.06:01:02.38#ibcon#about to read 6, iclass 7, count 2 2006.257.06:01:02.38#ibcon#read 6, iclass 7, count 2 2006.257.06:01:02.38#ibcon#end of sib2, iclass 7, count 2 2006.257.06:01:02.38#ibcon#*after write, iclass 7, count 2 2006.257.06:01:02.38#ibcon#*before return 0, iclass 7, count 2 2006.257.06:01:02.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:01:02.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:01:02.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.06:01:02.38#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:02.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:01:02.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:01:02.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:01:02.50#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:01:02.50#ibcon#first serial, iclass 7, count 0 2006.257.06:01:02.50#ibcon#enter sib2, iclass 7, count 0 2006.257.06:01:02.50#ibcon#flushed, iclass 7, count 0 2006.257.06:01:02.50#ibcon#about to write, iclass 7, count 0 2006.257.06:01:02.50#ibcon#wrote, iclass 7, count 0 2006.257.06:01:02.50#ibcon#about to read 3, iclass 7, count 0 2006.257.06:01:02.52#ibcon#read 3, iclass 7, count 0 2006.257.06:01:02.52#ibcon#about to read 4, iclass 7, count 0 2006.257.06:01:02.52#ibcon#read 4, iclass 7, count 0 2006.257.06:01:02.52#ibcon#about to read 5, iclass 7, count 0 2006.257.06:01:02.52#ibcon#read 5, iclass 7, count 0 2006.257.06:01:02.52#ibcon#about to read 6, iclass 7, count 0 2006.257.06:01:02.52#ibcon#read 6, iclass 7, count 0 2006.257.06:01:02.52#ibcon#end of sib2, iclass 7, count 0 2006.257.06:01:02.52#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:01:02.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:01:02.52#ibcon#[27=USB\r\n] 2006.257.06:01:02.52#ibcon#*before write, iclass 7, count 0 2006.257.06:01:02.52#ibcon#enter sib2, iclass 7, count 0 2006.257.06:01:02.52#ibcon#flushed, iclass 7, count 0 2006.257.06:01:02.52#ibcon#about to write, iclass 7, count 0 2006.257.06:01:02.52#ibcon#wrote, iclass 7, count 0 2006.257.06:01:02.52#ibcon#about to read 3, iclass 7, count 0 2006.257.06:01:02.55#ibcon#read 3, iclass 7, count 0 2006.257.06:01:02.55#ibcon#about to read 4, iclass 7, count 0 2006.257.06:01:02.55#ibcon#read 4, iclass 7, count 0 2006.257.06:01:02.55#ibcon#about to read 5, iclass 7, count 0 2006.257.06:01:02.55#ibcon#read 5, iclass 7, count 0 2006.257.06:01:02.55#ibcon#about to read 6, iclass 7, count 0 2006.257.06:01:02.55#ibcon#read 6, iclass 7, count 0 2006.257.06:01:02.55#ibcon#end of sib2, iclass 7, count 0 2006.257.06:01:02.55#ibcon#*after write, iclass 7, count 0 2006.257.06:01:02.55#ibcon#*before return 0, iclass 7, count 0 2006.257.06:01:02.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:01:02.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:01:02.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:01:02.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:01:02.55$vck44/vblo=6,719.99 2006.257.06:01:02.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.06:01:02.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.06:01:02.55#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:02.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:01:02.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:01:02.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:01:02.55#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:01:02.55#ibcon#first serial, iclass 11, count 0 2006.257.06:01:02.55#ibcon#enter sib2, iclass 11, count 0 2006.257.06:01:02.55#ibcon#flushed, iclass 11, count 0 2006.257.06:01:02.55#ibcon#about to write, iclass 11, count 0 2006.257.06:01:02.55#ibcon#wrote, iclass 11, count 0 2006.257.06:01:02.55#ibcon#about to read 3, iclass 11, count 0 2006.257.06:01:02.57#ibcon#read 3, iclass 11, count 0 2006.257.06:01:02.57#ibcon#about to read 4, iclass 11, count 0 2006.257.06:01:02.57#ibcon#read 4, iclass 11, count 0 2006.257.06:01:02.57#ibcon#about to read 5, iclass 11, count 0 2006.257.06:01:02.57#ibcon#read 5, iclass 11, count 0 2006.257.06:01:02.57#ibcon#about to read 6, iclass 11, count 0 2006.257.06:01:02.57#ibcon#read 6, iclass 11, count 0 2006.257.06:01:02.57#ibcon#end of sib2, iclass 11, count 0 2006.257.06:01:02.57#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:01:02.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:01:02.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:01:02.57#ibcon#*before write, iclass 11, count 0 2006.257.06:01:02.57#ibcon#enter sib2, iclass 11, count 0 2006.257.06:01:02.57#ibcon#flushed, iclass 11, count 0 2006.257.06:01:02.57#ibcon#about to write, iclass 11, count 0 2006.257.06:01:02.57#ibcon#wrote, iclass 11, count 0 2006.257.06:01:02.57#ibcon#about to read 3, iclass 11, count 0 2006.257.06:01:02.61#ibcon#read 3, iclass 11, count 0 2006.257.06:01:02.61#ibcon#about to read 4, iclass 11, count 0 2006.257.06:01:02.61#ibcon#read 4, iclass 11, count 0 2006.257.06:01:02.61#ibcon#about to read 5, iclass 11, count 0 2006.257.06:01:02.61#ibcon#read 5, iclass 11, count 0 2006.257.06:01:02.61#ibcon#about to read 6, iclass 11, count 0 2006.257.06:01:02.61#ibcon#read 6, iclass 11, count 0 2006.257.06:01:02.61#ibcon#end of sib2, iclass 11, count 0 2006.257.06:01:02.61#ibcon#*after write, iclass 11, count 0 2006.257.06:01:02.61#ibcon#*before return 0, iclass 11, count 0 2006.257.06:01:02.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:01:02.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:01:02.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:01:02.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:01:02.61$vck44/vb=6,4 2006.257.06:01:02.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.06:01:02.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.06:01:02.61#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:02.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:01:02.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:01:02.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:01:02.67#ibcon#enter wrdev, iclass 13, count 2 2006.257.06:01:02.67#ibcon#first serial, iclass 13, count 2 2006.257.06:01:02.67#ibcon#enter sib2, iclass 13, count 2 2006.257.06:01:02.67#ibcon#flushed, iclass 13, count 2 2006.257.06:01:02.67#ibcon#about to write, iclass 13, count 2 2006.257.06:01:02.67#ibcon#wrote, iclass 13, count 2 2006.257.06:01:02.67#ibcon#about to read 3, iclass 13, count 2 2006.257.06:01:02.69#ibcon#read 3, iclass 13, count 2 2006.257.06:01:02.69#ibcon#about to read 4, iclass 13, count 2 2006.257.06:01:02.69#ibcon#read 4, iclass 13, count 2 2006.257.06:01:02.69#ibcon#about to read 5, iclass 13, count 2 2006.257.06:01:02.69#ibcon#read 5, iclass 13, count 2 2006.257.06:01:02.69#ibcon#about to read 6, iclass 13, count 2 2006.257.06:01:02.69#ibcon#read 6, iclass 13, count 2 2006.257.06:01:02.69#ibcon#end of sib2, iclass 13, count 2 2006.257.06:01:02.69#ibcon#*mode == 0, iclass 13, count 2 2006.257.06:01:02.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.06:01:02.69#ibcon#[27=AT06-04\r\n] 2006.257.06:01:02.69#ibcon#*before write, iclass 13, count 2 2006.257.06:01:02.69#ibcon#enter sib2, iclass 13, count 2 2006.257.06:01:02.69#ibcon#flushed, iclass 13, count 2 2006.257.06:01:02.69#ibcon#about to write, iclass 13, count 2 2006.257.06:01:02.69#ibcon#wrote, iclass 13, count 2 2006.257.06:01:02.69#ibcon#about to read 3, iclass 13, count 2 2006.257.06:01:02.72#ibcon#read 3, iclass 13, count 2 2006.257.06:01:02.72#ibcon#about to read 4, iclass 13, count 2 2006.257.06:01:02.72#ibcon#read 4, iclass 13, count 2 2006.257.06:01:02.72#ibcon#about to read 5, iclass 13, count 2 2006.257.06:01:02.72#ibcon#read 5, iclass 13, count 2 2006.257.06:01:02.72#ibcon#about to read 6, iclass 13, count 2 2006.257.06:01:02.72#ibcon#read 6, iclass 13, count 2 2006.257.06:01:02.72#ibcon#end of sib2, iclass 13, count 2 2006.257.06:01:02.72#ibcon#*after write, iclass 13, count 2 2006.257.06:01:02.72#ibcon#*before return 0, iclass 13, count 2 2006.257.06:01:02.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:01:02.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:01:02.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.06:01:02.72#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:02.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:01:02.74#abcon#<5=/16 1.3 4.7 20.14 891012.2\r\n> 2006.257.06:01:02.76#abcon#{5=INTERFACE CLEAR} 2006.257.06:01:02.82#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:01:02.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:01:02.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:01:02.84#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:01:02.84#ibcon#first serial, iclass 13, count 0 2006.257.06:01:02.84#ibcon#enter sib2, iclass 13, count 0 2006.257.06:01:02.84#ibcon#flushed, iclass 13, count 0 2006.257.06:01:02.84#ibcon#about to write, iclass 13, count 0 2006.257.06:01:02.84#ibcon#wrote, iclass 13, count 0 2006.257.06:01:02.84#ibcon#about to read 3, iclass 13, count 0 2006.257.06:01:02.86#ibcon#read 3, iclass 13, count 0 2006.257.06:01:02.86#ibcon#about to read 4, iclass 13, count 0 2006.257.06:01:02.86#ibcon#read 4, iclass 13, count 0 2006.257.06:01:02.86#ibcon#about to read 5, iclass 13, count 0 2006.257.06:01:02.86#ibcon#read 5, iclass 13, count 0 2006.257.06:01:02.86#ibcon#about to read 6, iclass 13, count 0 2006.257.06:01:02.86#ibcon#read 6, iclass 13, count 0 2006.257.06:01:02.86#ibcon#end of sib2, iclass 13, count 0 2006.257.06:01:02.86#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:01:02.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:01:02.86#ibcon#[27=USB\r\n] 2006.257.06:01:02.86#ibcon#*before write, iclass 13, count 0 2006.257.06:01:02.86#ibcon#enter sib2, iclass 13, count 0 2006.257.06:01:02.86#ibcon#flushed, iclass 13, count 0 2006.257.06:01:02.86#ibcon#about to write, iclass 13, count 0 2006.257.06:01:02.86#ibcon#wrote, iclass 13, count 0 2006.257.06:01:02.86#ibcon#about to read 3, iclass 13, count 0 2006.257.06:01:02.89#ibcon#read 3, iclass 13, count 0 2006.257.06:01:02.89#ibcon#about to read 4, iclass 13, count 0 2006.257.06:01:02.89#ibcon#read 4, iclass 13, count 0 2006.257.06:01:02.89#ibcon#about to read 5, iclass 13, count 0 2006.257.06:01:02.89#ibcon#read 5, iclass 13, count 0 2006.257.06:01:02.89#ibcon#about to read 6, iclass 13, count 0 2006.257.06:01:02.89#ibcon#read 6, iclass 13, count 0 2006.257.06:01:02.89#ibcon#end of sib2, iclass 13, count 0 2006.257.06:01:02.89#ibcon#*after write, iclass 13, count 0 2006.257.06:01:02.89#ibcon#*before return 0, iclass 13, count 0 2006.257.06:01:02.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:01:02.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:01:02.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:01:02.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:01:02.89$vck44/vblo=7,734.99 2006.257.06:01:02.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.06:01:02.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.06:01:02.89#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:02.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:02.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:02.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:02.89#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:01:02.89#ibcon#first serial, iclass 19, count 0 2006.257.06:01:02.89#ibcon#enter sib2, iclass 19, count 0 2006.257.06:01:02.89#ibcon#flushed, iclass 19, count 0 2006.257.06:01:02.89#ibcon#about to write, iclass 19, count 0 2006.257.06:01:02.89#ibcon#wrote, iclass 19, count 0 2006.257.06:01:02.89#ibcon#about to read 3, iclass 19, count 0 2006.257.06:01:02.91#ibcon#read 3, iclass 19, count 0 2006.257.06:01:02.91#ibcon#about to read 4, iclass 19, count 0 2006.257.06:01:02.91#ibcon#read 4, iclass 19, count 0 2006.257.06:01:02.91#ibcon#about to read 5, iclass 19, count 0 2006.257.06:01:02.91#ibcon#read 5, iclass 19, count 0 2006.257.06:01:02.91#ibcon#about to read 6, iclass 19, count 0 2006.257.06:01:02.91#ibcon#read 6, iclass 19, count 0 2006.257.06:01:02.91#ibcon#end of sib2, iclass 19, count 0 2006.257.06:01:02.91#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:01:02.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:01:02.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:01:02.91#ibcon#*before write, iclass 19, count 0 2006.257.06:01:02.91#ibcon#enter sib2, iclass 19, count 0 2006.257.06:01:02.91#ibcon#flushed, iclass 19, count 0 2006.257.06:01:02.91#ibcon#about to write, iclass 19, count 0 2006.257.06:01:02.91#ibcon#wrote, iclass 19, count 0 2006.257.06:01:02.91#ibcon#about to read 3, iclass 19, count 0 2006.257.06:01:02.95#ibcon#read 3, iclass 19, count 0 2006.257.06:01:02.95#ibcon#about to read 4, iclass 19, count 0 2006.257.06:01:02.95#ibcon#read 4, iclass 19, count 0 2006.257.06:01:02.95#ibcon#about to read 5, iclass 19, count 0 2006.257.06:01:02.95#ibcon#read 5, iclass 19, count 0 2006.257.06:01:02.95#ibcon#about to read 6, iclass 19, count 0 2006.257.06:01:02.95#ibcon#read 6, iclass 19, count 0 2006.257.06:01:02.95#ibcon#end of sib2, iclass 19, count 0 2006.257.06:01:02.95#ibcon#*after write, iclass 19, count 0 2006.257.06:01:02.95#ibcon#*before return 0, iclass 19, count 0 2006.257.06:01:02.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:02.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:01:02.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:01:02.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:01:02.95$vck44/vb=7,4 2006.257.06:01:02.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.06:01:02.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.06:01:02.95#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:02.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:03.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:03.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:03.01#ibcon#enter wrdev, iclass 21, count 2 2006.257.06:01:03.01#ibcon#first serial, iclass 21, count 2 2006.257.06:01:03.01#ibcon#enter sib2, iclass 21, count 2 2006.257.06:01:03.01#ibcon#flushed, iclass 21, count 2 2006.257.06:01:03.01#ibcon#about to write, iclass 21, count 2 2006.257.06:01:03.01#ibcon#wrote, iclass 21, count 2 2006.257.06:01:03.01#ibcon#about to read 3, iclass 21, count 2 2006.257.06:01:03.03#ibcon#read 3, iclass 21, count 2 2006.257.06:01:03.03#ibcon#about to read 4, iclass 21, count 2 2006.257.06:01:03.03#ibcon#read 4, iclass 21, count 2 2006.257.06:01:03.03#ibcon#about to read 5, iclass 21, count 2 2006.257.06:01:03.03#ibcon#read 5, iclass 21, count 2 2006.257.06:01:03.03#ibcon#about to read 6, iclass 21, count 2 2006.257.06:01:03.03#ibcon#read 6, iclass 21, count 2 2006.257.06:01:03.03#ibcon#end of sib2, iclass 21, count 2 2006.257.06:01:03.03#ibcon#*mode == 0, iclass 21, count 2 2006.257.06:01:03.03#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.06:01:03.03#ibcon#[27=AT07-04\r\n] 2006.257.06:01:03.03#ibcon#*before write, iclass 21, count 2 2006.257.06:01:03.03#ibcon#enter sib2, iclass 21, count 2 2006.257.06:01:03.03#ibcon#flushed, iclass 21, count 2 2006.257.06:01:03.03#ibcon#about to write, iclass 21, count 2 2006.257.06:01:03.03#ibcon#wrote, iclass 21, count 2 2006.257.06:01:03.03#ibcon#about to read 3, iclass 21, count 2 2006.257.06:01:03.06#ibcon#read 3, iclass 21, count 2 2006.257.06:01:03.06#ibcon#about to read 4, iclass 21, count 2 2006.257.06:01:03.06#ibcon#read 4, iclass 21, count 2 2006.257.06:01:03.06#ibcon#about to read 5, iclass 21, count 2 2006.257.06:01:03.06#ibcon#read 5, iclass 21, count 2 2006.257.06:01:03.06#ibcon#about to read 6, iclass 21, count 2 2006.257.06:01:03.06#ibcon#read 6, iclass 21, count 2 2006.257.06:01:03.06#ibcon#end of sib2, iclass 21, count 2 2006.257.06:01:03.06#ibcon#*after write, iclass 21, count 2 2006.257.06:01:03.06#ibcon#*before return 0, iclass 21, count 2 2006.257.06:01:03.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:03.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:01:03.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.06:01:03.06#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:03.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:03.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:03.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:03.18#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:01:03.18#ibcon#first serial, iclass 21, count 0 2006.257.06:01:03.18#ibcon#enter sib2, iclass 21, count 0 2006.257.06:01:03.18#ibcon#flushed, iclass 21, count 0 2006.257.06:01:03.18#ibcon#about to write, iclass 21, count 0 2006.257.06:01:03.18#ibcon#wrote, iclass 21, count 0 2006.257.06:01:03.18#ibcon#about to read 3, iclass 21, count 0 2006.257.06:01:03.20#ibcon#read 3, iclass 21, count 0 2006.257.06:01:03.20#ibcon#about to read 4, iclass 21, count 0 2006.257.06:01:03.20#ibcon#read 4, iclass 21, count 0 2006.257.06:01:03.20#ibcon#about to read 5, iclass 21, count 0 2006.257.06:01:03.20#ibcon#read 5, iclass 21, count 0 2006.257.06:01:03.20#ibcon#about to read 6, iclass 21, count 0 2006.257.06:01:03.20#ibcon#read 6, iclass 21, count 0 2006.257.06:01:03.20#ibcon#end of sib2, iclass 21, count 0 2006.257.06:01:03.20#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:01:03.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:01:03.20#ibcon#[27=USB\r\n] 2006.257.06:01:03.20#ibcon#*before write, iclass 21, count 0 2006.257.06:01:03.20#ibcon#enter sib2, iclass 21, count 0 2006.257.06:01:03.20#ibcon#flushed, iclass 21, count 0 2006.257.06:01:03.20#ibcon#about to write, iclass 21, count 0 2006.257.06:01:03.20#ibcon#wrote, iclass 21, count 0 2006.257.06:01:03.20#ibcon#about to read 3, iclass 21, count 0 2006.257.06:01:03.23#ibcon#read 3, iclass 21, count 0 2006.257.06:01:03.23#ibcon#about to read 4, iclass 21, count 0 2006.257.06:01:03.23#ibcon#read 4, iclass 21, count 0 2006.257.06:01:03.23#ibcon#about to read 5, iclass 21, count 0 2006.257.06:01:03.23#ibcon#read 5, iclass 21, count 0 2006.257.06:01:03.23#ibcon#about to read 6, iclass 21, count 0 2006.257.06:01:03.23#ibcon#read 6, iclass 21, count 0 2006.257.06:01:03.23#ibcon#end of sib2, iclass 21, count 0 2006.257.06:01:03.23#ibcon#*after write, iclass 21, count 0 2006.257.06:01:03.23#ibcon#*before return 0, iclass 21, count 0 2006.257.06:01:03.23#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:03.23#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:01:03.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:01:03.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:01:03.23$vck44/vblo=8,744.99 2006.257.06:01:03.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.06:01:03.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.06:01:03.23#ibcon#ireg 17 cls_cnt 0 2006.257.06:01:03.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:03.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:03.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:03.23#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:01:03.23#ibcon#first serial, iclass 23, count 0 2006.257.06:01:03.23#ibcon#enter sib2, iclass 23, count 0 2006.257.06:01:03.23#ibcon#flushed, iclass 23, count 0 2006.257.06:01:03.23#ibcon#about to write, iclass 23, count 0 2006.257.06:01:03.23#ibcon#wrote, iclass 23, count 0 2006.257.06:01:03.23#ibcon#about to read 3, iclass 23, count 0 2006.257.06:01:03.25#ibcon#read 3, iclass 23, count 0 2006.257.06:01:03.25#ibcon#about to read 4, iclass 23, count 0 2006.257.06:01:03.25#ibcon#read 4, iclass 23, count 0 2006.257.06:01:03.25#ibcon#about to read 5, iclass 23, count 0 2006.257.06:01:03.25#ibcon#read 5, iclass 23, count 0 2006.257.06:01:03.25#ibcon#about to read 6, iclass 23, count 0 2006.257.06:01:03.25#ibcon#read 6, iclass 23, count 0 2006.257.06:01:03.25#ibcon#end of sib2, iclass 23, count 0 2006.257.06:01:03.25#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:01:03.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:01:03.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:01:03.25#ibcon#*before write, iclass 23, count 0 2006.257.06:01:03.25#ibcon#enter sib2, iclass 23, count 0 2006.257.06:01:03.25#ibcon#flushed, iclass 23, count 0 2006.257.06:01:03.25#ibcon#about to write, iclass 23, count 0 2006.257.06:01:03.25#ibcon#wrote, iclass 23, count 0 2006.257.06:01:03.25#ibcon#about to read 3, iclass 23, count 0 2006.257.06:01:03.29#ibcon#read 3, iclass 23, count 0 2006.257.06:01:03.29#ibcon#about to read 4, iclass 23, count 0 2006.257.06:01:03.29#ibcon#read 4, iclass 23, count 0 2006.257.06:01:03.29#ibcon#about to read 5, iclass 23, count 0 2006.257.06:01:03.29#ibcon#read 5, iclass 23, count 0 2006.257.06:01:03.29#ibcon#about to read 6, iclass 23, count 0 2006.257.06:01:03.29#ibcon#read 6, iclass 23, count 0 2006.257.06:01:03.29#ibcon#end of sib2, iclass 23, count 0 2006.257.06:01:03.29#ibcon#*after write, iclass 23, count 0 2006.257.06:01:03.29#ibcon#*before return 0, iclass 23, count 0 2006.257.06:01:03.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:03.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:01:03.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:01:03.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:01:03.29$vck44/vb=8,4 2006.257.06:01:03.29#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.06:01:03.29#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.06:01:03.29#ibcon#ireg 11 cls_cnt 2 2006.257.06:01:03.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:03.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:03.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:03.35#ibcon#enter wrdev, iclass 25, count 2 2006.257.06:01:03.35#ibcon#first serial, iclass 25, count 2 2006.257.06:01:03.35#ibcon#enter sib2, iclass 25, count 2 2006.257.06:01:03.35#ibcon#flushed, iclass 25, count 2 2006.257.06:01:03.35#ibcon#about to write, iclass 25, count 2 2006.257.06:01:03.35#ibcon#wrote, iclass 25, count 2 2006.257.06:01:03.35#ibcon#about to read 3, iclass 25, count 2 2006.257.06:01:03.37#ibcon#read 3, iclass 25, count 2 2006.257.06:01:03.37#ibcon#about to read 4, iclass 25, count 2 2006.257.06:01:03.37#ibcon#read 4, iclass 25, count 2 2006.257.06:01:03.37#ibcon#about to read 5, iclass 25, count 2 2006.257.06:01:03.37#ibcon#read 5, iclass 25, count 2 2006.257.06:01:03.37#ibcon#about to read 6, iclass 25, count 2 2006.257.06:01:03.37#ibcon#read 6, iclass 25, count 2 2006.257.06:01:03.37#ibcon#end of sib2, iclass 25, count 2 2006.257.06:01:03.37#ibcon#*mode == 0, iclass 25, count 2 2006.257.06:01:03.37#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.06:01:03.37#ibcon#[27=AT08-04\r\n] 2006.257.06:01:03.37#ibcon#*before write, iclass 25, count 2 2006.257.06:01:03.37#ibcon#enter sib2, iclass 25, count 2 2006.257.06:01:03.37#ibcon#flushed, iclass 25, count 2 2006.257.06:01:03.37#ibcon#about to write, iclass 25, count 2 2006.257.06:01:03.37#ibcon#wrote, iclass 25, count 2 2006.257.06:01:03.37#ibcon#about to read 3, iclass 25, count 2 2006.257.06:01:03.40#ibcon#read 3, iclass 25, count 2 2006.257.06:01:03.40#ibcon#about to read 4, iclass 25, count 2 2006.257.06:01:03.40#ibcon#read 4, iclass 25, count 2 2006.257.06:01:03.40#ibcon#about to read 5, iclass 25, count 2 2006.257.06:01:03.40#ibcon#read 5, iclass 25, count 2 2006.257.06:01:03.40#ibcon#about to read 6, iclass 25, count 2 2006.257.06:01:03.40#ibcon#read 6, iclass 25, count 2 2006.257.06:01:03.40#ibcon#end of sib2, iclass 25, count 2 2006.257.06:01:03.40#ibcon#*after write, iclass 25, count 2 2006.257.06:01:03.40#ibcon#*before return 0, iclass 25, count 2 2006.257.06:01:03.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:03.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:01:03.40#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.06:01:03.40#ibcon#ireg 7 cls_cnt 0 2006.257.06:01:03.40#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:03.52#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:03.52#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:03.52#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:01:03.52#ibcon#first serial, iclass 25, count 0 2006.257.06:01:03.52#ibcon#enter sib2, iclass 25, count 0 2006.257.06:01:03.52#ibcon#flushed, iclass 25, count 0 2006.257.06:01:03.52#ibcon#about to write, iclass 25, count 0 2006.257.06:01:03.52#ibcon#wrote, iclass 25, count 0 2006.257.06:01:03.52#ibcon#about to read 3, iclass 25, count 0 2006.257.06:01:03.54#ibcon#read 3, iclass 25, count 0 2006.257.06:01:03.54#ibcon#about to read 4, iclass 25, count 0 2006.257.06:01:03.54#ibcon#read 4, iclass 25, count 0 2006.257.06:01:03.54#ibcon#about to read 5, iclass 25, count 0 2006.257.06:01:03.54#ibcon#read 5, iclass 25, count 0 2006.257.06:01:03.54#ibcon#about to read 6, iclass 25, count 0 2006.257.06:01:03.54#ibcon#read 6, iclass 25, count 0 2006.257.06:01:03.54#ibcon#end of sib2, iclass 25, count 0 2006.257.06:01:03.54#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:01:03.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:01:03.54#ibcon#[27=USB\r\n] 2006.257.06:01:03.54#ibcon#*before write, iclass 25, count 0 2006.257.06:01:03.54#ibcon#enter sib2, iclass 25, count 0 2006.257.06:01:03.54#ibcon#flushed, iclass 25, count 0 2006.257.06:01:03.54#ibcon#about to write, iclass 25, count 0 2006.257.06:01:03.54#ibcon#wrote, iclass 25, count 0 2006.257.06:01:03.54#ibcon#about to read 3, iclass 25, count 0 2006.257.06:01:03.57#ibcon#read 3, iclass 25, count 0 2006.257.06:01:03.57#ibcon#about to read 4, iclass 25, count 0 2006.257.06:01:03.57#ibcon#read 4, iclass 25, count 0 2006.257.06:01:03.57#ibcon#about to read 5, iclass 25, count 0 2006.257.06:01:03.57#ibcon#read 5, iclass 25, count 0 2006.257.06:01:03.57#ibcon#about to read 6, iclass 25, count 0 2006.257.06:01:03.57#ibcon#read 6, iclass 25, count 0 2006.257.06:01:03.57#ibcon#end of sib2, iclass 25, count 0 2006.257.06:01:03.57#ibcon#*after write, iclass 25, count 0 2006.257.06:01:03.57#ibcon#*before return 0, iclass 25, count 0 2006.257.06:01:03.57#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:03.57#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:01:03.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:01:03.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:01:03.57$vck44/vabw=wide 2006.257.06:01:03.57#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.06:01:03.57#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.06:01:03.57#ibcon#ireg 8 cls_cnt 0 2006.257.06:01:03.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:03.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:03.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:03.57#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:01:03.57#ibcon#first serial, iclass 27, count 0 2006.257.06:01:03.57#ibcon#enter sib2, iclass 27, count 0 2006.257.06:01:03.57#ibcon#flushed, iclass 27, count 0 2006.257.06:01:03.57#ibcon#about to write, iclass 27, count 0 2006.257.06:01:03.57#ibcon#wrote, iclass 27, count 0 2006.257.06:01:03.57#ibcon#about to read 3, iclass 27, count 0 2006.257.06:01:03.59#ibcon#read 3, iclass 27, count 0 2006.257.06:01:03.59#ibcon#about to read 4, iclass 27, count 0 2006.257.06:01:03.59#ibcon#read 4, iclass 27, count 0 2006.257.06:01:03.59#ibcon#about to read 5, iclass 27, count 0 2006.257.06:01:03.59#ibcon#read 5, iclass 27, count 0 2006.257.06:01:03.59#ibcon#about to read 6, iclass 27, count 0 2006.257.06:01:03.59#ibcon#read 6, iclass 27, count 0 2006.257.06:01:03.59#ibcon#end of sib2, iclass 27, count 0 2006.257.06:01:03.59#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:01:03.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:01:03.59#ibcon#[25=BW32\r\n] 2006.257.06:01:03.59#ibcon#*before write, iclass 27, count 0 2006.257.06:01:03.59#ibcon#enter sib2, iclass 27, count 0 2006.257.06:01:03.59#ibcon#flushed, iclass 27, count 0 2006.257.06:01:03.59#ibcon#about to write, iclass 27, count 0 2006.257.06:01:03.59#ibcon#wrote, iclass 27, count 0 2006.257.06:01:03.59#ibcon#about to read 3, iclass 27, count 0 2006.257.06:01:03.62#ibcon#read 3, iclass 27, count 0 2006.257.06:01:03.62#ibcon#about to read 4, iclass 27, count 0 2006.257.06:01:03.62#ibcon#read 4, iclass 27, count 0 2006.257.06:01:03.62#ibcon#about to read 5, iclass 27, count 0 2006.257.06:01:03.62#ibcon#read 5, iclass 27, count 0 2006.257.06:01:03.62#ibcon#about to read 6, iclass 27, count 0 2006.257.06:01:03.62#ibcon#read 6, iclass 27, count 0 2006.257.06:01:03.62#ibcon#end of sib2, iclass 27, count 0 2006.257.06:01:03.62#ibcon#*after write, iclass 27, count 0 2006.257.06:01:03.62#ibcon#*before return 0, iclass 27, count 0 2006.257.06:01:03.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:03.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:01:03.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:01:03.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:01:03.62$vck44/vbbw=wide 2006.257.06:01:03.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.06:01:03.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.06:01:03.62#ibcon#ireg 8 cls_cnt 0 2006.257.06:01:03.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:01:03.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:01:03.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:01:03.69#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:01:03.69#ibcon#first serial, iclass 29, count 0 2006.257.06:01:03.69#ibcon#enter sib2, iclass 29, count 0 2006.257.06:01:03.69#ibcon#flushed, iclass 29, count 0 2006.257.06:01:03.69#ibcon#about to write, iclass 29, count 0 2006.257.06:01:03.69#ibcon#wrote, iclass 29, count 0 2006.257.06:01:03.69#ibcon#about to read 3, iclass 29, count 0 2006.257.06:01:03.71#ibcon#read 3, iclass 29, count 0 2006.257.06:01:03.71#ibcon#about to read 4, iclass 29, count 0 2006.257.06:01:03.71#ibcon#read 4, iclass 29, count 0 2006.257.06:01:03.71#ibcon#about to read 5, iclass 29, count 0 2006.257.06:01:03.71#ibcon#read 5, iclass 29, count 0 2006.257.06:01:03.71#ibcon#about to read 6, iclass 29, count 0 2006.257.06:01:03.71#ibcon#read 6, iclass 29, count 0 2006.257.06:01:03.71#ibcon#end of sib2, iclass 29, count 0 2006.257.06:01:03.71#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:01:03.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:01:03.71#ibcon#[27=BW32\r\n] 2006.257.06:01:03.71#ibcon#*before write, iclass 29, count 0 2006.257.06:01:03.71#ibcon#enter sib2, iclass 29, count 0 2006.257.06:01:03.71#ibcon#flushed, iclass 29, count 0 2006.257.06:01:03.71#ibcon#about to write, iclass 29, count 0 2006.257.06:01:03.71#ibcon#wrote, iclass 29, count 0 2006.257.06:01:03.71#ibcon#about to read 3, iclass 29, count 0 2006.257.06:01:03.74#ibcon#read 3, iclass 29, count 0 2006.257.06:01:03.74#ibcon#about to read 4, iclass 29, count 0 2006.257.06:01:03.74#ibcon#read 4, iclass 29, count 0 2006.257.06:01:03.74#ibcon#about to read 5, iclass 29, count 0 2006.257.06:01:03.74#ibcon#read 5, iclass 29, count 0 2006.257.06:01:03.74#ibcon#about to read 6, iclass 29, count 0 2006.257.06:01:03.74#ibcon#read 6, iclass 29, count 0 2006.257.06:01:03.74#ibcon#end of sib2, iclass 29, count 0 2006.257.06:01:03.74#ibcon#*after write, iclass 29, count 0 2006.257.06:01:03.74#ibcon#*before return 0, iclass 29, count 0 2006.257.06:01:03.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:01:03.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:01:03.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:01:03.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:01:03.74$setupk4/ifdk4 2006.257.06:01:03.74$ifdk4/lo= 2006.257.06:01:03.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:01:03.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:01:03.74$ifdk4/patch= 2006.257.06:01:03.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:01:03.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:01:03.74$setupk4/!*+20s 2006.257.06:01:12.91#abcon#<5=/16 1.3 4.7 20.14 891012.2\r\n> 2006.257.06:01:12.93#abcon#{5=INTERFACE CLEAR} 2006.257.06:01:12.99#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:01:18.25$setupk4/"tpicd 2006.257.06:01:18.25$setupk4/echo=off 2006.257.06:01:18.25$setupk4/xlog=off 2006.257.06:01:18.25:!2006.257.06:03:50 2006.257.06:01:55.14#trakl#Source acquired 2006.257.06:01:56.14#flagr#flagr/antenna,acquired 2006.257.06:03:50.02:preob 2006.257.06:03:51.15/onsource/TRACKING 2006.257.06:03:51.15:!2006.257.06:04:00 2006.257.06:04:00.02:"tape 2006.257.06:04:00.02:"st=record 2006.257.06:04:00.02:data_valid=on 2006.257.06:04:00.02:midob 2006.257.06:04:01.15/onsource/TRACKING 2006.257.06:04:01.15/wx/20.17,1012.1,89 2006.257.06:04:01.24/cable/+6.4803E-03 2006.257.06:04:02.33/va/01,08,usb,yes,33,35 2006.257.06:04:02.33/va/02,07,usb,yes,35,36 2006.257.06:04:02.33/va/03,08,usb,yes,32,34 2006.257.06:04:02.33/va/04,07,usb,yes,36,38 2006.257.06:04:02.33/va/05,04,usb,yes,33,33 2006.257.06:04:02.33/va/06,04,usb,yes,36,36 2006.257.06:04:02.33/va/07,04,usb,yes,37,38 2006.257.06:04:02.33/va/08,04,usb,yes,31,38 2006.257.06:04:02.56/valo/01,524.99,yes,locked 2006.257.06:04:02.56/valo/02,534.99,yes,locked 2006.257.06:04:02.56/valo/03,564.99,yes,locked 2006.257.06:04:02.56/valo/04,624.99,yes,locked 2006.257.06:04:02.56/valo/05,734.99,yes,locked 2006.257.06:04:02.56/valo/06,814.99,yes,locked 2006.257.06:04:02.56/valo/07,864.99,yes,locked 2006.257.06:04:02.56/valo/08,884.99,yes,locked 2006.257.06:04:03.65/vb/01,04,usb,yes,31,29 2006.257.06:04:03.65/vb/02,05,usb,yes,30,30 2006.257.06:04:03.65/vb/03,04,usb,yes,31,34 2006.257.06:04:03.65/vb/04,05,usb,yes,31,30 2006.257.06:04:03.65/vb/05,04,usb,yes,28,30 2006.257.06:04:03.65/vb/06,04,usb,yes,32,28 2006.257.06:04:03.65/vb/07,04,usb,yes,32,32 2006.257.06:04:03.65/vb/08,04,usb,yes,29,33 2006.257.06:04:03.89/vblo/01,629.99,yes,locked 2006.257.06:04:03.89/vblo/02,634.99,yes,locked 2006.257.06:04:03.89/vblo/03,649.99,yes,locked 2006.257.06:04:03.89/vblo/04,679.99,yes,locked 2006.257.06:04:03.89/vblo/05,709.99,yes,locked 2006.257.06:04:03.89/vblo/06,719.99,yes,locked 2006.257.06:04:03.89/vblo/07,734.99,yes,locked 2006.257.06:04:03.89/vblo/08,744.99,yes,locked 2006.257.06:04:04.04/vabw/8 2006.257.06:04:04.19/vbbw/8 2006.257.06:04:04.36/xfe/off,on,16.7 2006.257.06:04:04.74/ifatt/23,28,28,28 2006.257.06:04:05.07/fmout-gps/S +4.56E-07 2006.257.06:04:05.11:!2006.257.06:04:40 2006.257.06:04:40.02:data_valid=off 2006.257.06:04:40.02:"et 2006.257.06:04:40.02:!+3s 2006.257.06:04:43.04:"tape 2006.257.06:04:43.05:postob 2006.257.06:04:43.27/cable/+6.4792E-03 2006.257.06:04:43.28/wx/20.18,1012.1,89 2006.257.06:04:43.33/fmout-gps/S +4.56E-07 2006.257.06:04:43.34:scan_name=257-0606,jd0609,240 2006.257.06:04:43.34:source=1803+784,180045.68,782804.0,2000.0,cw 2006.257.06:04:44.15#flagr#flagr/antenna,new-source 2006.257.06:04:44.15:checkk5 2006.257.06:04:44.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:04:44.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:04:45.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:04:45.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:04:46.18/chk_obsdata//k5ts1/T2570604??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:04:46.58/chk_obsdata//k5ts2/T2570604??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:04:46.98/chk_obsdata//k5ts3/T2570604??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:04:47.39/chk_obsdata//k5ts4/T2570604??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:04:48.13/k5log//k5ts1_log_newline 2006.257.06:04:48.84/k5log//k5ts2_log_newline 2006.257.06:04:49.61/k5log//k5ts3_log_newline 2006.257.06:04:50.34/k5log//k5ts4_log_newline 2006.257.06:04:50.37/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:04:50.37:setupk4=1 2006.257.06:04:50.37$setupk4/echo=on 2006.257.06:04:50.37$setupk4/pcalon 2006.257.06:04:50.37$pcalon/"no phase cal control is implemented here 2006.257.06:04:50.37$setupk4/"tpicd=stop 2006.257.06:04:50.37$setupk4/"rec=synch_on 2006.257.06:04:50.37$setupk4/"rec_mode=128 2006.257.06:04:50.37$setupk4/!* 2006.257.06:04:50.37$setupk4/recpk4 2006.257.06:04:50.37$recpk4/recpatch= 2006.257.06:04:50.37$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:04:50.37$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:04:50.37$setupk4/vck44 2006.257.06:04:50.37$vck44/valo=1,524.99 2006.257.06:04:50.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.06:04:50.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.06:04:50.37#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:50.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:50.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:50.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:50.37#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:04:50.37#ibcon#first serial, iclass 14, count 0 2006.257.06:04:50.37#ibcon#enter sib2, iclass 14, count 0 2006.257.06:04:50.37#ibcon#flushed, iclass 14, count 0 2006.257.06:04:50.37#ibcon#about to write, iclass 14, count 0 2006.257.06:04:50.37#ibcon#wrote, iclass 14, count 0 2006.257.06:04:50.37#ibcon#about to read 3, iclass 14, count 0 2006.257.06:04:50.38#ibcon#read 3, iclass 14, count 0 2006.257.06:04:50.38#ibcon#about to read 4, iclass 14, count 0 2006.257.06:04:50.38#ibcon#read 4, iclass 14, count 0 2006.257.06:04:50.38#ibcon#about to read 5, iclass 14, count 0 2006.257.06:04:50.38#ibcon#read 5, iclass 14, count 0 2006.257.06:04:50.38#ibcon#about to read 6, iclass 14, count 0 2006.257.06:04:50.38#ibcon#read 6, iclass 14, count 0 2006.257.06:04:50.38#ibcon#end of sib2, iclass 14, count 0 2006.257.06:04:50.38#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:04:50.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:04:50.38#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:04:50.38#ibcon#*before write, iclass 14, count 0 2006.257.06:04:50.38#ibcon#enter sib2, iclass 14, count 0 2006.257.06:04:50.38#ibcon#flushed, iclass 14, count 0 2006.257.06:04:50.38#ibcon#about to write, iclass 14, count 0 2006.257.06:04:50.38#ibcon#wrote, iclass 14, count 0 2006.257.06:04:50.38#ibcon#about to read 3, iclass 14, count 0 2006.257.06:04:50.43#ibcon#read 3, iclass 14, count 0 2006.257.06:04:50.43#ibcon#about to read 4, iclass 14, count 0 2006.257.06:04:50.43#ibcon#read 4, iclass 14, count 0 2006.257.06:04:50.43#ibcon#about to read 5, iclass 14, count 0 2006.257.06:04:50.43#ibcon#read 5, iclass 14, count 0 2006.257.06:04:50.43#ibcon#about to read 6, iclass 14, count 0 2006.257.06:04:50.43#ibcon#read 6, iclass 14, count 0 2006.257.06:04:50.43#ibcon#end of sib2, iclass 14, count 0 2006.257.06:04:50.43#ibcon#*after write, iclass 14, count 0 2006.257.06:04:50.43#ibcon#*before return 0, iclass 14, count 0 2006.257.06:04:50.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:50.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:50.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:04:50.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:04:50.43$vck44/va=1,8 2006.257.06:04:50.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.06:04:50.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.06:04:50.43#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:50.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:50.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:50.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:50.43#ibcon#enter wrdev, iclass 16, count 2 2006.257.06:04:50.43#ibcon#first serial, iclass 16, count 2 2006.257.06:04:50.44#ibcon#enter sib2, iclass 16, count 2 2006.257.06:04:50.44#ibcon#flushed, iclass 16, count 2 2006.257.06:04:50.44#ibcon#about to write, iclass 16, count 2 2006.257.06:04:50.44#ibcon#wrote, iclass 16, count 2 2006.257.06:04:50.44#ibcon#about to read 3, iclass 16, count 2 2006.257.06:04:50.45#ibcon#read 3, iclass 16, count 2 2006.257.06:04:50.45#ibcon#about to read 4, iclass 16, count 2 2006.257.06:04:50.45#ibcon#read 4, iclass 16, count 2 2006.257.06:04:50.45#ibcon#about to read 5, iclass 16, count 2 2006.257.06:04:50.45#ibcon#read 5, iclass 16, count 2 2006.257.06:04:50.45#ibcon#about to read 6, iclass 16, count 2 2006.257.06:04:50.45#ibcon#read 6, iclass 16, count 2 2006.257.06:04:50.45#ibcon#end of sib2, iclass 16, count 2 2006.257.06:04:50.45#ibcon#*mode == 0, iclass 16, count 2 2006.257.06:04:50.45#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.06:04:50.45#ibcon#[25=AT01-08\r\n] 2006.257.06:04:50.45#ibcon#*before write, iclass 16, count 2 2006.257.06:04:50.45#ibcon#enter sib2, iclass 16, count 2 2006.257.06:04:50.45#ibcon#flushed, iclass 16, count 2 2006.257.06:04:50.45#ibcon#about to write, iclass 16, count 2 2006.257.06:04:50.45#ibcon#wrote, iclass 16, count 2 2006.257.06:04:50.45#ibcon#about to read 3, iclass 16, count 2 2006.257.06:04:50.48#ibcon#read 3, iclass 16, count 2 2006.257.06:04:50.48#ibcon#about to read 4, iclass 16, count 2 2006.257.06:04:50.48#ibcon#read 4, iclass 16, count 2 2006.257.06:04:50.48#ibcon#about to read 5, iclass 16, count 2 2006.257.06:04:50.48#ibcon#read 5, iclass 16, count 2 2006.257.06:04:50.48#ibcon#about to read 6, iclass 16, count 2 2006.257.06:04:50.48#ibcon#read 6, iclass 16, count 2 2006.257.06:04:50.48#ibcon#end of sib2, iclass 16, count 2 2006.257.06:04:50.48#ibcon#*after write, iclass 16, count 2 2006.257.06:04:50.48#ibcon#*before return 0, iclass 16, count 2 2006.257.06:04:50.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:50.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:50.48#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.06:04:50.48#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:50.48#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:50.60#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:50.60#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:50.60#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:04:50.60#ibcon#first serial, iclass 16, count 0 2006.257.06:04:50.60#ibcon#enter sib2, iclass 16, count 0 2006.257.06:04:50.60#ibcon#flushed, iclass 16, count 0 2006.257.06:04:50.60#ibcon#about to write, iclass 16, count 0 2006.257.06:04:50.60#ibcon#wrote, iclass 16, count 0 2006.257.06:04:50.60#ibcon#about to read 3, iclass 16, count 0 2006.257.06:04:50.62#ibcon#read 3, iclass 16, count 0 2006.257.06:04:50.62#ibcon#about to read 4, iclass 16, count 0 2006.257.06:04:50.62#ibcon#read 4, iclass 16, count 0 2006.257.06:04:50.62#ibcon#about to read 5, iclass 16, count 0 2006.257.06:04:50.62#ibcon#read 5, iclass 16, count 0 2006.257.06:04:50.62#ibcon#about to read 6, iclass 16, count 0 2006.257.06:04:50.62#ibcon#read 6, iclass 16, count 0 2006.257.06:04:50.62#ibcon#end of sib2, iclass 16, count 0 2006.257.06:04:50.62#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:04:50.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:04:50.62#ibcon#[25=USB\r\n] 2006.257.06:04:50.62#ibcon#*before write, iclass 16, count 0 2006.257.06:04:50.62#ibcon#enter sib2, iclass 16, count 0 2006.257.06:04:50.62#ibcon#flushed, iclass 16, count 0 2006.257.06:04:50.62#ibcon#about to write, iclass 16, count 0 2006.257.06:04:50.62#ibcon#wrote, iclass 16, count 0 2006.257.06:04:50.62#ibcon#about to read 3, iclass 16, count 0 2006.257.06:04:50.65#ibcon#read 3, iclass 16, count 0 2006.257.06:04:50.65#ibcon#about to read 4, iclass 16, count 0 2006.257.06:04:50.65#ibcon#read 4, iclass 16, count 0 2006.257.06:04:50.65#ibcon#about to read 5, iclass 16, count 0 2006.257.06:04:50.65#ibcon#read 5, iclass 16, count 0 2006.257.06:04:50.65#ibcon#about to read 6, iclass 16, count 0 2006.257.06:04:50.65#ibcon#read 6, iclass 16, count 0 2006.257.06:04:50.65#ibcon#end of sib2, iclass 16, count 0 2006.257.06:04:50.65#ibcon#*after write, iclass 16, count 0 2006.257.06:04:50.65#ibcon#*before return 0, iclass 16, count 0 2006.257.06:04:50.65#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:50.65#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:50.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:04:50.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:04:50.65$vck44/valo=2,534.99 2006.257.06:04:50.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.06:04:50.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.06:04:50.65#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:50.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:50.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:50.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:50.65#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:04:50.66#ibcon#first serial, iclass 18, count 0 2006.257.06:04:50.66#ibcon#enter sib2, iclass 18, count 0 2006.257.06:04:50.66#ibcon#flushed, iclass 18, count 0 2006.257.06:04:50.66#ibcon#about to write, iclass 18, count 0 2006.257.06:04:50.66#ibcon#wrote, iclass 18, count 0 2006.257.06:04:50.66#ibcon#about to read 3, iclass 18, count 0 2006.257.06:04:50.67#ibcon#read 3, iclass 18, count 0 2006.257.06:04:50.67#ibcon#about to read 4, iclass 18, count 0 2006.257.06:04:50.67#ibcon#read 4, iclass 18, count 0 2006.257.06:04:50.67#ibcon#about to read 5, iclass 18, count 0 2006.257.06:04:50.67#ibcon#read 5, iclass 18, count 0 2006.257.06:04:50.67#ibcon#about to read 6, iclass 18, count 0 2006.257.06:04:50.67#ibcon#read 6, iclass 18, count 0 2006.257.06:04:50.67#ibcon#end of sib2, iclass 18, count 0 2006.257.06:04:50.67#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:04:50.67#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:04:50.67#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:04:50.67#ibcon#*before write, iclass 18, count 0 2006.257.06:04:50.67#ibcon#enter sib2, iclass 18, count 0 2006.257.06:04:50.67#ibcon#flushed, iclass 18, count 0 2006.257.06:04:50.67#ibcon#about to write, iclass 18, count 0 2006.257.06:04:50.67#ibcon#wrote, iclass 18, count 0 2006.257.06:04:50.67#ibcon#about to read 3, iclass 18, count 0 2006.257.06:04:50.71#ibcon#read 3, iclass 18, count 0 2006.257.06:04:50.71#ibcon#about to read 4, iclass 18, count 0 2006.257.06:04:50.71#ibcon#read 4, iclass 18, count 0 2006.257.06:04:50.71#ibcon#about to read 5, iclass 18, count 0 2006.257.06:04:50.71#ibcon#read 5, iclass 18, count 0 2006.257.06:04:50.71#ibcon#about to read 6, iclass 18, count 0 2006.257.06:04:50.71#ibcon#read 6, iclass 18, count 0 2006.257.06:04:50.71#ibcon#end of sib2, iclass 18, count 0 2006.257.06:04:50.71#ibcon#*after write, iclass 18, count 0 2006.257.06:04:50.71#ibcon#*before return 0, iclass 18, count 0 2006.257.06:04:50.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:50.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:50.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:04:50.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:04:50.71$vck44/va=2,7 2006.257.06:04:50.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.06:04:50.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.06:04:50.71#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:50.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:50.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:50.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:50.77#ibcon#enter wrdev, iclass 20, count 2 2006.257.06:04:50.77#ibcon#first serial, iclass 20, count 2 2006.257.06:04:50.77#ibcon#enter sib2, iclass 20, count 2 2006.257.06:04:50.77#ibcon#flushed, iclass 20, count 2 2006.257.06:04:50.77#ibcon#about to write, iclass 20, count 2 2006.257.06:04:50.77#ibcon#wrote, iclass 20, count 2 2006.257.06:04:50.77#ibcon#about to read 3, iclass 20, count 2 2006.257.06:04:50.79#ibcon#read 3, iclass 20, count 2 2006.257.06:04:50.79#ibcon#about to read 4, iclass 20, count 2 2006.257.06:04:50.79#ibcon#read 4, iclass 20, count 2 2006.257.06:04:50.79#ibcon#about to read 5, iclass 20, count 2 2006.257.06:04:50.79#ibcon#read 5, iclass 20, count 2 2006.257.06:04:50.79#ibcon#about to read 6, iclass 20, count 2 2006.257.06:04:50.79#ibcon#read 6, iclass 20, count 2 2006.257.06:04:50.79#ibcon#end of sib2, iclass 20, count 2 2006.257.06:04:50.79#ibcon#*mode == 0, iclass 20, count 2 2006.257.06:04:50.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.06:04:50.79#ibcon#[25=AT02-07\r\n] 2006.257.06:04:50.79#ibcon#*before write, iclass 20, count 2 2006.257.06:04:50.79#ibcon#enter sib2, iclass 20, count 2 2006.257.06:04:50.79#ibcon#flushed, iclass 20, count 2 2006.257.06:04:50.79#ibcon#about to write, iclass 20, count 2 2006.257.06:04:50.79#ibcon#wrote, iclass 20, count 2 2006.257.06:04:50.79#ibcon#about to read 3, iclass 20, count 2 2006.257.06:04:50.82#ibcon#read 3, iclass 20, count 2 2006.257.06:04:50.82#ibcon#about to read 4, iclass 20, count 2 2006.257.06:04:50.82#ibcon#read 4, iclass 20, count 2 2006.257.06:04:50.82#ibcon#about to read 5, iclass 20, count 2 2006.257.06:04:50.82#ibcon#read 5, iclass 20, count 2 2006.257.06:04:50.82#ibcon#about to read 6, iclass 20, count 2 2006.257.06:04:50.82#ibcon#read 6, iclass 20, count 2 2006.257.06:04:50.82#ibcon#end of sib2, iclass 20, count 2 2006.257.06:04:50.82#ibcon#*after write, iclass 20, count 2 2006.257.06:04:50.82#ibcon#*before return 0, iclass 20, count 2 2006.257.06:04:50.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:50.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:50.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.06:04:50.82#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:50.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:50.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:50.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:50.94#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:04:50.94#ibcon#first serial, iclass 20, count 0 2006.257.06:04:50.94#ibcon#enter sib2, iclass 20, count 0 2006.257.06:04:50.94#ibcon#flushed, iclass 20, count 0 2006.257.06:04:50.94#ibcon#about to write, iclass 20, count 0 2006.257.06:04:50.94#ibcon#wrote, iclass 20, count 0 2006.257.06:04:50.94#ibcon#about to read 3, iclass 20, count 0 2006.257.06:04:50.96#ibcon#read 3, iclass 20, count 0 2006.257.06:04:50.96#ibcon#about to read 4, iclass 20, count 0 2006.257.06:04:50.96#ibcon#read 4, iclass 20, count 0 2006.257.06:04:50.96#ibcon#about to read 5, iclass 20, count 0 2006.257.06:04:50.96#ibcon#read 5, iclass 20, count 0 2006.257.06:04:50.96#ibcon#about to read 6, iclass 20, count 0 2006.257.06:04:50.96#ibcon#read 6, iclass 20, count 0 2006.257.06:04:50.96#ibcon#end of sib2, iclass 20, count 0 2006.257.06:04:50.96#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:04:50.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:04:50.96#ibcon#[25=USB\r\n] 2006.257.06:04:50.96#ibcon#*before write, iclass 20, count 0 2006.257.06:04:50.96#ibcon#enter sib2, iclass 20, count 0 2006.257.06:04:50.96#ibcon#flushed, iclass 20, count 0 2006.257.06:04:50.96#ibcon#about to write, iclass 20, count 0 2006.257.06:04:50.96#ibcon#wrote, iclass 20, count 0 2006.257.06:04:50.96#ibcon#about to read 3, iclass 20, count 0 2006.257.06:04:50.99#ibcon#read 3, iclass 20, count 0 2006.257.06:04:50.99#ibcon#about to read 4, iclass 20, count 0 2006.257.06:04:50.99#ibcon#read 4, iclass 20, count 0 2006.257.06:04:50.99#ibcon#about to read 5, iclass 20, count 0 2006.257.06:04:50.99#ibcon#read 5, iclass 20, count 0 2006.257.06:04:50.99#ibcon#about to read 6, iclass 20, count 0 2006.257.06:04:50.99#ibcon#read 6, iclass 20, count 0 2006.257.06:04:50.99#ibcon#end of sib2, iclass 20, count 0 2006.257.06:04:50.99#ibcon#*after write, iclass 20, count 0 2006.257.06:04:50.99#ibcon#*before return 0, iclass 20, count 0 2006.257.06:04:50.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:50.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:50.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:04:50.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:04:50.99$vck44/valo=3,564.99 2006.257.06:04:50.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.06:04:50.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.06:04:50.99#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:50.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:50.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:51.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:51.00#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:04:51.00#ibcon#first serial, iclass 22, count 0 2006.257.06:04:51.00#ibcon#enter sib2, iclass 22, count 0 2006.257.06:04:51.00#ibcon#flushed, iclass 22, count 0 2006.257.06:04:51.00#ibcon#about to write, iclass 22, count 0 2006.257.06:04:51.00#ibcon#wrote, iclass 22, count 0 2006.257.06:04:51.00#ibcon#about to read 3, iclass 22, count 0 2006.257.06:04:51.01#ibcon#read 3, iclass 22, count 0 2006.257.06:04:51.01#ibcon#about to read 4, iclass 22, count 0 2006.257.06:04:51.01#ibcon#read 4, iclass 22, count 0 2006.257.06:04:51.01#ibcon#about to read 5, iclass 22, count 0 2006.257.06:04:51.01#ibcon#read 5, iclass 22, count 0 2006.257.06:04:51.01#ibcon#about to read 6, iclass 22, count 0 2006.257.06:04:51.01#ibcon#read 6, iclass 22, count 0 2006.257.06:04:51.01#ibcon#end of sib2, iclass 22, count 0 2006.257.06:04:51.01#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:04:51.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:04:51.01#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:04:51.01#ibcon#*before write, iclass 22, count 0 2006.257.06:04:51.01#ibcon#enter sib2, iclass 22, count 0 2006.257.06:04:51.01#ibcon#flushed, iclass 22, count 0 2006.257.06:04:51.01#ibcon#about to write, iclass 22, count 0 2006.257.06:04:51.01#ibcon#wrote, iclass 22, count 0 2006.257.06:04:51.01#ibcon#about to read 3, iclass 22, count 0 2006.257.06:04:51.05#ibcon#read 3, iclass 22, count 0 2006.257.06:04:51.05#ibcon#about to read 4, iclass 22, count 0 2006.257.06:04:51.05#ibcon#read 4, iclass 22, count 0 2006.257.06:04:51.05#ibcon#about to read 5, iclass 22, count 0 2006.257.06:04:51.05#ibcon#read 5, iclass 22, count 0 2006.257.06:04:51.05#ibcon#about to read 6, iclass 22, count 0 2006.257.06:04:51.05#ibcon#read 6, iclass 22, count 0 2006.257.06:04:51.05#ibcon#end of sib2, iclass 22, count 0 2006.257.06:04:51.05#ibcon#*after write, iclass 22, count 0 2006.257.06:04:51.05#ibcon#*before return 0, iclass 22, count 0 2006.257.06:04:51.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:51.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:51.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:04:51.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:04:51.05$vck44/va=3,8 2006.257.06:04:51.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.06:04:51.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.06:04:51.05#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:51.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:51.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:51.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:51.11#ibcon#enter wrdev, iclass 24, count 2 2006.257.06:04:51.11#ibcon#first serial, iclass 24, count 2 2006.257.06:04:51.11#ibcon#enter sib2, iclass 24, count 2 2006.257.06:04:51.11#ibcon#flushed, iclass 24, count 2 2006.257.06:04:51.11#ibcon#about to write, iclass 24, count 2 2006.257.06:04:51.11#ibcon#wrote, iclass 24, count 2 2006.257.06:04:51.11#ibcon#about to read 3, iclass 24, count 2 2006.257.06:04:51.13#ibcon#read 3, iclass 24, count 2 2006.257.06:04:51.13#ibcon#about to read 4, iclass 24, count 2 2006.257.06:04:51.13#ibcon#read 4, iclass 24, count 2 2006.257.06:04:51.13#ibcon#about to read 5, iclass 24, count 2 2006.257.06:04:51.13#ibcon#read 5, iclass 24, count 2 2006.257.06:04:51.13#ibcon#about to read 6, iclass 24, count 2 2006.257.06:04:51.13#ibcon#read 6, iclass 24, count 2 2006.257.06:04:51.13#ibcon#end of sib2, iclass 24, count 2 2006.257.06:04:51.13#ibcon#*mode == 0, iclass 24, count 2 2006.257.06:04:51.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.06:04:51.13#ibcon#[25=AT03-08\r\n] 2006.257.06:04:51.13#ibcon#*before write, iclass 24, count 2 2006.257.06:04:51.13#ibcon#enter sib2, iclass 24, count 2 2006.257.06:04:51.13#ibcon#flushed, iclass 24, count 2 2006.257.06:04:51.13#ibcon#about to write, iclass 24, count 2 2006.257.06:04:51.13#ibcon#wrote, iclass 24, count 2 2006.257.06:04:51.13#ibcon#about to read 3, iclass 24, count 2 2006.257.06:04:51.16#ibcon#read 3, iclass 24, count 2 2006.257.06:04:51.16#ibcon#about to read 4, iclass 24, count 2 2006.257.06:04:51.16#ibcon#read 4, iclass 24, count 2 2006.257.06:04:51.16#ibcon#about to read 5, iclass 24, count 2 2006.257.06:04:51.16#ibcon#read 5, iclass 24, count 2 2006.257.06:04:51.16#ibcon#about to read 6, iclass 24, count 2 2006.257.06:04:51.16#ibcon#read 6, iclass 24, count 2 2006.257.06:04:51.16#ibcon#end of sib2, iclass 24, count 2 2006.257.06:04:51.16#ibcon#*after write, iclass 24, count 2 2006.257.06:04:51.16#ibcon#*before return 0, iclass 24, count 2 2006.257.06:04:51.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:51.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:51.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.06:04:51.16#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:51.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:51.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:51.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:51.28#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:04:51.28#ibcon#first serial, iclass 24, count 0 2006.257.06:04:51.28#ibcon#enter sib2, iclass 24, count 0 2006.257.06:04:51.28#ibcon#flushed, iclass 24, count 0 2006.257.06:04:51.28#ibcon#about to write, iclass 24, count 0 2006.257.06:04:51.28#ibcon#wrote, iclass 24, count 0 2006.257.06:04:51.28#ibcon#about to read 3, iclass 24, count 0 2006.257.06:04:51.30#ibcon#read 3, iclass 24, count 0 2006.257.06:04:51.30#ibcon#about to read 4, iclass 24, count 0 2006.257.06:04:51.30#ibcon#read 4, iclass 24, count 0 2006.257.06:04:51.30#ibcon#about to read 5, iclass 24, count 0 2006.257.06:04:51.30#ibcon#read 5, iclass 24, count 0 2006.257.06:04:51.30#ibcon#about to read 6, iclass 24, count 0 2006.257.06:04:51.30#ibcon#read 6, iclass 24, count 0 2006.257.06:04:51.30#ibcon#end of sib2, iclass 24, count 0 2006.257.06:04:51.30#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:04:51.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:04:51.30#ibcon#[25=USB\r\n] 2006.257.06:04:51.30#ibcon#*before write, iclass 24, count 0 2006.257.06:04:51.30#ibcon#enter sib2, iclass 24, count 0 2006.257.06:04:51.30#ibcon#flushed, iclass 24, count 0 2006.257.06:04:51.30#ibcon#about to write, iclass 24, count 0 2006.257.06:04:51.30#ibcon#wrote, iclass 24, count 0 2006.257.06:04:51.30#ibcon#about to read 3, iclass 24, count 0 2006.257.06:04:51.33#ibcon#read 3, iclass 24, count 0 2006.257.06:04:51.33#ibcon#about to read 4, iclass 24, count 0 2006.257.06:04:51.33#ibcon#read 4, iclass 24, count 0 2006.257.06:04:51.33#ibcon#about to read 5, iclass 24, count 0 2006.257.06:04:51.33#ibcon#read 5, iclass 24, count 0 2006.257.06:04:51.33#ibcon#about to read 6, iclass 24, count 0 2006.257.06:04:51.33#ibcon#read 6, iclass 24, count 0 2006.257.06:04:51.33#ibcon#end of sib2, iclass 24, count 0 2006.257.06:04:51.33#ibcon#*after write, iclass 24, count 0 2006.257.06:04:51.33#ibcon#*before return 0, iclass 24, count 0 2006.257.06:04:51.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:51.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:51.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:04:51.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:04:51.33$vck44/valo=4,624.99 2006.257.06:04:51.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.06:04:51.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.06:04:51.33#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:51.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:51.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:51.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:51.34#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:04:51.34#ibcon#first serial, iclass 26, count 0 2006.257.06:04:51.34#ibcon#enter sib2, iclass 26, count 0 2006.257.06:04:51.34#ibcon#flushed, iclass 26, count 0 2006.257.06:04:51.34#ibcon#about to write, iclass 26, count 0 2006.257.06:04:51.34#ibcon#wrote, iclass 26, count 0 2006.257.06:04:51.34#ibcon#about to read 3, iclass 26, count 0 2006.257.06:04:51.35#ibcon#read 3, iclass 26, count 0 2006.257.06:04:51.35#ibcon#about to read 4, iclass 26, count 0 2006.257.06:04:51.35#ibcon#read 4, iclass 26, count 0 2006.257.06:04:51.35#ibcon#about to read 5, iclass 26, count 0 2006.257.06:04:51.35#ibcon#read 5, iclass 26, count 0 2006.257.06:04:51.35#ibcon#about to read 6, iclass 26, count 0 2006.257.06:04:51.35#ibcon#read 6, iclass 26, count 0 2006.257.06:04:51.35#ibcon#end of sib2, iclass 26, count 0 2006.257.06:04:51.35#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:04:51.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:04:51.35#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:04:51.35#ibcon#*before write, iclass 26, count 0 2006.257.06:04:51.35#ibcon#enter sib2, iclass 26, count 0 2006.257.06:04:51.35#ibcon#flushed, iclass 26, count 0 2006.257.06:04:51.35#ibcon#about to write, iclass 26, count 0 2006.257.06:04:51.35#ibcon#wrote, iclass 26, count 0 2006.257.06:04:51.35#ibcon#about to read 3, iclass 26, count 0 2006.257.06:04:51.39#ibcon#read 3, iclass 26, count 0 2006.257.06:04:51.39#ibcon#about to read 4, iclass 26, count 0 2006.257.06:04:51.39#ibcon#read 4, iclass 26, count 0 2006.257.06:04:51.39#ibcon#about to read 5, iclass 26, count 0 2006.257.06:04:51.39#ibcon#read 5, iclass 26, count 0 2006.257.06:04:51.39#ibcon#about to read 6, iclass 26, count 0 2006.257.06:04:51.39#ibcon#read 6, iclass 26, count 0 2006.257.06:04:51.39#ibcon#end of sib2, iclass 26, count 0 2006.257.06:04:51.39#ibcon#*after write, iclass 26, count 0 2006.257.06:04:51.39#ibcon#*before return 0, iclass 26, count 0 2006.257.06:04:51.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:51.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:51.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:04:51.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:04:51.39$vck44/va=4,7 2006.257.06:04:51.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.06:04:51.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.06:04:51.39#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:51.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:51.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:51.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:51.45#ibcon#enter wrdev, iclass 28, count 2 2006.257.06:04:51.45#ibcon#first serial, iclass 28, count 2 2006.257.06:04:51.45#ibcon#enter sib2, iclass 28, count 2 2006.257.06:04:51.45#ibcon#flushed, iclass 28, count 2 2006.257.06:04:51.45#ibcon#about to write, iclass 28, count 2 2006.257.06:04:51.45#ibcon#wrote, iclass 28, count 2 2006.257.06:04:51.45#ibcon#about to read 3, iclass 28, count 2 2006.257.06:04:51.47#ibcon#read 3, iclass 28, count 2 2006.257.06:04:51.47#ibcon#about to read 4, iclass 28, count 2 2006.257.06:04:51.47#ibcon#read 4, iclass 28, count 2 2006.257.06:04:51.47#ibcon#about to read 5, iclass 28, count 2 2006.257.06:04:51.47#ibcon#read 5, iclass 28, count 2 2006.257.06:04:51.47#ibcon#about to read 6, iclass 28, count 2 2006.257.06:04:51.47#ibcon#read 6, iclass 28, count 2 2006.257.06:04:51.47#ibcon#end of sib2, iclass 28, count 2 2006.257.06:04:51.47#ibcon#*mode == 0, iclass 28, count 2 2006.257.06:04:51.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.06:04:51.47#ibcon#[25=AT04-07\r\n] 2006.257.06:04:51.47#ibcon#*before write, iclass 28, count 2 2006.257.06:04:51.47#ibcon#enter sib2, iclass 28, count 2 2006.257.06:04:51.47#ibcon#flushed, iclass 28, count 2 2006.257.06:04:51.47#ibcon#about to write, iclass 28, count 2 2006.257.06:04:51.47#ibcon#wrote, iclass 28, count 2 2006.257.06:04:51.47#ibcon#about to read 3, iclass 28, count 2 2006.257.06:04:51.50#ibcon#read 3, iclass 28, count 2 2006.257.06:04:51.50#ibcon#about to read 4, iclass 28, count 2 2006.257.06:04:51.50#ibcon#read 4, iclass 28, count 2 2006.257.06:04:51.50#ibcon#about to read 5, iclass 28, count 2 2006.257.06:04:51.50#ibcon#read 5, iclass 28, count 2 2006.257.06:04:51.50#ibcon#about to read 6, iclass 28, count 2 2006.257.06:04:51.50#ibcon#read 6, iclass 28, count 2 2006.257.06:04:51.50#ibcon#end of sib2, iclass 28, count 2 2006.257.06:04:51.50#ibcon#*after write, iclass 28, count 2 2006.257.06:04:51.50#ibcon#*before return 0, iclass 28, count 2 2006.257.06:04:51.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:51.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:51.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.06:04:51.50#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:51.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:51.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:51.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:51.62#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:04:51.62#ibcon#first serial, iclass 28, count 0 2006.257.06:04:51.62#ibcon#enter sib2, iclass 28, count 0 2006.257.06:04:51.62#ibcon#flushed, iclass 28, count 0 2006.257.06:04:51.62#ibcon#about to write, iclass 28, count 0 2006.257.06:04:51.62#ibcon#wrote, iclass 28, count 0 2006.257.06:04:51.62#ibcon#about to read 3, iclass 28, count 0 2006.257.06:04:51.64#ibcon#read 3, iclass 28, count 0 2006.257.06:04:51.64#ibcon#about to read 4, iclass 28, count 0 2006.257.06:04:51.64#ibcon#read 4, iclass 28, count 0 2006.257.06:04:51.64#ibcon#about to read 5, iclass 28, count 0 2006.257.06:04:51.64#ibcon#read 5, iclass 28, count 0 2006.257.06:04:51.64#ibcon#about to read 6, iclass 28, count 0 2006.257.06:04:51.64#ibcon#read 6, iclass 28, count 0 2006.257.06:04:51.64#ibcon#end of sib2, iclass 28, count 0 2006.257.06:04:51.64#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:04:51.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:04:51.64#ibcon#[25=USB\r\n] 2006.257.06:04:51.64#ibcon#*before write, iclass 28, count 0 2006.257.06:04:51.64#ibcon#enter sib2, iclass 28, count 0 2006.257.06:04:51.64#ibcon#flushed, iclass 28, count 0 2006.257.06:04:51.64#ibcon#about to write, iclass 28, count 0 2006.257.06:04:51.64#ibcon#wrote, iclass 28, count 0 2006.257.06:04:51.64#ibcon#about to read 3, iclass 28, count 0 2006.257.06:04:51.67#ibcon#read 3, iclass 28, count 0 2006.257.06:04:51.67#ibcon#about to read 4, iclass 28, count 0 2006.257.06:04:51.67#ibcon#read 4, iclass 28, count 0 2006.257.06:04:51.67#ibcon#about to read 5, iclass 28, count 0 2006.257.06:04:51.67#ibcon#read 5, iclass 28, count 0 2006.257.06:04:51.67#ibcon#about to read 6, iclass 28, count 0 2006.257.06:04:51.67#ibcon#read 6, iclass 28, count 0 2006.257.06:04:51.67#ibcon#end of sib2, iclass 28, count 0 2006.257.06:04:51.67#ibcon#*after write, iclass 28, count 0 2006.257.06:04:51.67#ibcon#*before return 0, iclass 28, count 0 2006.257.06:04:51.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:51.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:51.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:04:51.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:04:51.67$vck44/valo=5,734.99 2006.257.06:04:51.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.06:04:51.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.06:04:51.67#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:51.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:51.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:51.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:51.68#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:04:51.68#ibcon#first serial, iclass 30, count 0 2006.257.06:04:51.68#ibcon#enter sib2, iclass 30, count 0 2006.257.06:04:51.68#ibcon#flushed, iclass 30, count 0 2006.257.06:04:51.68#ibcon#about to write, iclass 30, count 0 2006.257.06:04:51.68#ibcon#wrote, iclass 30, count 0 2006.257.06:04:51.68#ibcon#about to read 3, iclass 30, count 0 2006.257.06:04:51.69#ibcon#read 3, iclass 30, count 0 2006.257.06:04:51.69#ibcon#about to read 4, iclass 30, count 0 2006.257.06:04:51.69#ibcon#read 4, iclass 30, count 0 2006.257.06:04:51.69#ibcon#about to read 5, iclass 30, count 0 2006.257.06:04:51.69#ibcon#read 5, iclass 30, count 0 2006.257.06:04:51.69#ibcon#about to read 6, iclass 30, count 0 2006.257.06:04:51.69#ibcon#read 6, iclass 30, count 0 2006.257.06:04:51.69#ibcon#end of sib2, iclass 30, count 0 2006.257.06:04:51.69#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:04:51.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:04:51.69#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:04:51.69#ibcon#*before write, iclass 30, count 0 2006.257.06:04:51.69#ibcon#enter sib2, iclass 30, count 0 2006.257.06:04:51.69#ibcon#flushed, iclass 30, count 0 2006.257.06:04:51.69#ibcon#about to write, iclass 30, count 0 2006.257.06:04:51.69#ibcon#wrote, iclass 30, count 0 2006.257.06:04:51.69#ibcon#about to read 3, iclass 30, count 0 2006.257.06:04:51.73#ibcon#read 3, iclass 30, count 0 2006.257.06:04:51.73#ibcon#about to read 4, iclass 30, count 0 2006.257.06:04:51.73#ibcon#read 4, iclass 30, count 0 2006.257.06:04:51.73#ibcon#about to read 5, iclass 30, count 0 2006.257.06:04:51.73#ibcon#read 5, iclass 30, count 0 2006.257.06:04:51.73#ibcon#about to read 6, iclass 30, count 0 2006.257.06:04:51.73#ibcon#read 6, iclass 30, count 0 2006.257.06:04:51.73#ibcon#end of sib2, iclass 30, count 0 2006.257.06:04:51.73#ibcon#*after write, iclass 30, count 0 2006.257.06:04:51.73#ibcon#*before return 0, iclass 30, count 0 2006.257.06:04:51.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:51.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:51.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:04:51.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:04:51.73$vck44/va=5,4 2006.257.06:04:51.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.06:04:51.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.06:04:51.73#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:51.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:51.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:51.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:51.79#ibcon#enter wrdev, iclass 32, count 2 2006.257.06:04:51.79#ibcon#first serial, iclass 32, count 2 2006.257.06:04:51.79#ibcon#enter sib2, iclass 32, count 2 2006.257.06:04:51.79#ibcon#flushed, iclass 32, count 2 2006.257.06:04:51.79#ibcon#about to write, iclass 32, count 2 2006.257.06:04:51.79#ibcon#wrote, iclass 32, count 2 2006.257.06:04:51.79#ibcon#about to read 3, iclass 32, count 2 2006.257.06:04:51.81#ibcon#read 3, iclass 32, count 2 2006.257.06:04:51.81#ibcon#about to read 4, iclass 32, count 2 2006.257.06:04:51.81#ibcon#read 4, iclass 32, count 2 2006.257.06:04:51.81#ibcon#about to read 5, iclass 32, count 2 2006.257.06:04:51.81#ibcon#read 5, iclass 32, count 2 2006.257.06:04:51.81#ibcon#about to read 6, iclass 32, count 2 2006.257.06:04:51.81#ibcon#read 6, iclass 32, count 2 2006.257.06:04:51.81#ibcon#end of sib2, iclass 32, count 2 2006.257.06:04:51.81#ibcon#*mode == 0, iclass 32, count 2 2006.257.06:04:51.81#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.06:04:51.81#ibcon#[25=AT05-04\r\n] 2006.257.06:04:51.81#ibcon#*before write, iclass 32, count 2 2006.257.06:04:51.81#ibcon#enter sib2, iclass 32, count 2 2006.257.06:04:51.81#ibcon#flushed, iclass 32, count 2 2006.257.06:04:51.81#ibcon#about to write, iclass 32, count 2 2006.257.06:04:51.81#ibcon#wrote, iclass 32, count 2 2006.257.06:04:51.81#ibcon#about to read 3, iclass 32, count 2 2006.257.06:04:51.84#ibcon#read 3, iclass 32, count 2 2006.257.06:04:51.84#ibcon#about to read 4, iclass 32, count 2 2006.257.06:04:51.84#ibcon#read 4, iclass 32, count 2 2006.257.06:04:51.84#ibcon#about to read 5, iclass 32, count 2 2006.257.06:04:51.84#ibcon#read 5, iclass 32, count 2 2006.257.06:04:51.84#ibcon#about to read 6, iclass 32, count 2 2006.257.06:04:51.84#ibcon#read 6, iclass 32, count 2 2006.257.06:04:51.84#ibcon#end of sib2, iclass 32, count 2 2006.257.06:04:51.84#ibcon#*after write, iclass 32, count 2 2006.257.06:04:51.84#ibcon#*before return 0, iclass 32, count 2 2006.257.06:04:51.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:51.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:51.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.06:04:51.84#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:51.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:51.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:51.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:51.96#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:04:51.96#ibcon#first serial, iclass 32, count 0 2006.257.06:04:51.96#ibcon#enter sib2, iclass 32, count 0 2006.257.06:04:51.96#ibcon#flushed, iclass 32, count 0 2006.257.06:04:51.96#ibcon#about to write, iclass 32, count 0 2006.257.06:04:51.96#ibcon#wrote, iclass 32, count 0 2006.257.06:04:51.96#ibcon#about to read 3, iclass 32, count 0 2006.257.06:04:51.98#ibcon#read 3, iclass 32, count 0 2006.257.06:04:51.98#ibcon#about to read 4, iclass 32, count 0 2006.257.06:04:51.98#ibcon#read 4, iclass 32, count 0 2006.257.06:04:51.98#ibcon#about to read 5, iclass 32, count 0 2006.257.06:04:51.98#ibcon#read 5, iclass 32, count 0 2006.257.06:04:51.98#ibcon#about to read 6, iclass 32, count 0 2006.257.06:04:51.98#ibcon#read 6, iclass 32, count 0 2006.257.06:04:51.98#ibcon#end of sib2, iclass 32, count 0 2006.257.06:04:51.98#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:04:51.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:04:51.98#ibcon#[25=USB\r\n] 2006.257.06:04:51.98#ibcon#*before write, iclass 32, count 0 2006.257.06:04:51.98#ibcon#enter sib2, iclass 32, count 0 2006.257.06:04:51.98#ibcon#flushed, iclass 32, count 0 2006.257.06:04:51.98#ibcon#about to write, iclass 32, count 0 2006.257.06:04:51.98#ibcon#wrote, iclass 32, count 0 2006.257.06:04:51.98#ibcon#about to read 3, iclass 32, count 0 2006.257.06:04:52.01#ibcon#read 3, iclass 32, count 0 2006.257.06:04:52.01#ibcon#about to read 4, iclass 32, count 0 2006.257.06:04:52.01#ibcon#read 4, iclass 32, count 0 2006.257.06:04:52.01#ibcon#about to read 5, iclass 32, count 0 2006.257.06:04:52.01#ibcon#read 5, iclass 32, count 0 2006.257.06:04:52.01#ibcon#about to read 6, iclass 32, count 0 2006.257.06:04:52.01#ibcon#read 6, iclass 32, count 0 2006.257.06:04:52.01#ibcon#end of sib2, iclass 32, count 0 2006.257.06:04:52.01#ibcon#*after write, iclass 32, count 0 2006.257.06:04:52.01#ibcon#*before return 0, iclass 32, count 0 2006.257.06:04:52.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:52.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:52.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:04:52.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:04:52.01$vck44/valo=6,814.99 2006.257.06:04:52.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.06:04:52.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.06:04:52.01#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:52.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:52.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:52.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:52.01#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:04:52.01#ibcon#first serial, iclass 34, count 0 2006.257.06:04:52.02#ibcon#enter sib2, iclass 34, count 0 2006.257.06:04:52.02#ibcon#flushed, iclass 34, count 0 2006.257.06:04:52.02#ibcon#about to write, iclass 34, count 0 2006.257.06:04:52.02#ibcon#wrote, iclass 34, count 0 2006.257.06:04:52.02#ibcon#about to read 3, iclass 34, count 0 2006.257.06:04:52.03#ibcon#read 3, iclass 34, count 0 2006.257.06:04:52.03#ibcon#about to read 4, iclass 34, count 0 2006.257.06:04:52.03#ibcon#read 4, iclass 34, count 0 2006.257.06:04:52.03#ibcon#about to read 5, iclass 34, count 0 2006.257.06:04:52.03#ibcon#read 5, iclass 34, count 0 2006.257.06:04:52.03#ibcon#about to read 6, iclass 34, count 0 2006.257.06:04:52.03#ibcon#read 6, iclass 34, count 0 2006.257.06:04:52.03#ibcon#end of sib2, iclass 34, count 0 2006.257.06:04:52.03#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:04:52.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:04:52.03#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:04:52.03#ibcon#*before write, iclass 34, count 0 2006.257.06:04:52.03#ibcon#enter sib2, iclass 34, count 0 2006.257.06:04:52.03#ibcon#flushed, iclass 34, count 0 2006.257.06:04:52.03#ibcon#about to write, iclass 34, count 0 2006.257.06:04:52.03#ibcon#wrote, iclass 34, count 0 2006.257.06:04:52.03#ibcon#about to read 3, iclass 34, count 0 2006.257.06:04:52.07#ibcon#read 3, iclass 34, count 0 2006.257.06:04:52.07#ibcon#about to read 4, iclass 34, count 0 2006.257.06:04:52.07#ibcon#read 4, iclass 34, count 0 2006.257.06:04:52.07#ibcon#about to read 5, iclass 34, count 0 2006.257.06:04:52.07#ibcon#read 5, iclass 34, count 0 2006.257.06:04:52.07#ibcon#about to read 6, iclass 34, count 0 2006.257.06:04:52.07#ibcon#read 6, iclass 34, count 0 2006.257.06:04:52.07#ibcon#end of sib2, iclass 34, count 0 2006.257.06:04:52.07#ibcon#*after write, iclass 34, count 0 2006.257.06:04:52.07#ibcon#*before return 0, iclass 34, count 0 2006.257.06:04:52.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:52.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:52.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:04:52.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:04:52.07$vck44/va=6,4 2006.257.06:04:52.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.06:04:52.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.06:04:52.07#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:52.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:52.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:52.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:52.13#ibcon#enter wrdev, iclass 36, count 2 2006.257.06:04:52.13#ibcon#first serial, iclass 36, count 2 2006.257.06:04:52.13#ibcon#enter sib2, iclass 36, count 2 2006.257.06:04:52.13#ibcon#flushed, iclass 36, count 2 2006.257.06:04:52.13#ibcon#about to write, iclass 36, count 2 2006.257.06:04:52.13#ibcon#wrote, iclass 36, count 2 2006.257.06:04:52.13#ibcon#about to read 3, iclass 36, count 2 2006.257.06:04:52.15#ibcon#read 3, iclass 36, count 2 2006.257.06:04:52.15#ibcon#about to read 4, iclass 36, count 2 2006.257.06:04:52.15#ibcon#read 4, iclass 36, count 2 2006.257.06:04:52.15#ibcon#about to read 5, iclass 36, count 2 2006.257.06:04:52.15#ibcon#read 5, iclass 36, count 2 2006.257.06:04:52.15#ibcon#about to read 6, iclass 36, count 2 2006.257.06:04:52.15#ibcon#read 6, iclass 36, count 2 2006.257.06:04:52.15#ibcon#end of sib2, iclass 36, count 2 2006.257.06:04:52.15#ibcon#*mode == 0, iclass 36, count 2 2006.257.06:04:52.15#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.06:04:52.15#ibcon#[25=AT06-04\r\n] 2006.257.06:04:52.15#ibcon#*before write, iclass 36, count 2 2006.257.06:04:52.15#ibcon#enter sib2, iclass 36, count 2 2006.257.06:04:52.15#ibcon#flushed, iclass 36, count 2 2006.257.06:04:52.15#ibcon#about to write, iclass 36, count 2 2006.257.06:04:52.15#ibcon#wrote, iclass 36, count 2 2006.257.06:04:52.15#ibcon#about to read 3, iclass 36, count 2 2006.257.06:04:52.18#ibcon#read 3, iclass 36, count 2 2006.257.06:04:52.18#ibcon#about to read 4, iclass 36, count 2 2006.257.06:04:52.18#ibcon#read 4, iclass 36, count 2 2006.257.06:04:52.18#ibcon#about to read 5, iclass 36, count 2 2006.257.06:04:52.18#ibcon#read 5, iclass 36, count 2 2006.257.06:04:52.18#ibcon#about to read 6, iclass 36, count 2 2006.257.06:04:52.18#ibcon#read 6, iclass 36, count 2 2006.257.06:04:52.18#ibcon#end of sib2, iclass 36, count 2 2006.257.06:04:52.18#ibcon#*after write, iclass 36, count 2 2006.257.06:04:52.18#ibcon#*before return 0, iclass 36, count 2 2006.257.06:04:52.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:52.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:52.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.06:04:52.18#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:52.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:52.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:52.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:52.30#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:04:52.30#ibcon#first serial, iclass 36, count 0 2006.257.06:04:52.30#ibcon#enter sib2, iclass 36, count 0 2006.257.06:04:52.30#ibcon#flushed, iclass 36, count 0 2006.257.06:04:52.30#ibcon#about to write, iclass 36, count 0 2006.257.06:04:52.30#ibcon#wrote, iclass 36, count 0 2006.257.06:04:52.30#ibcon#about to read 3, iclass 36, count 0 2006.257.06:04:52.32#ibcon#read 3, iclass 36, count 0 2006.257.06:04:52.32#ibcon#about to read 4, iclass 36, count 0 2006.257.06:04:52.32#ibcon#read 4, iclass 36, count 0 2006.257.06:04:52.32#ibcon#about to read 5, iclass 36, count 0 2006.257.06:04:52.32#ibcon#read 5, iclass 36, count 0 2006.257.06:04:52.32#ibcon#about to read 6, iclass 36, count 0 2006.257.06:04:52.32#ibcon#read 6, iclass 36, count 0 2006.257.06:04:52.32#ibcon#end of sib2, iclass 36, count 0 2006.257.06:04:52.32#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:04:52.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:04:52.32#ibcon#[25=USB\r\n] 2006.257.06:04:52.32#ibcon#*before write, iclass 36, count 0 2006.257.06:04:52.32#ibcon#enter sib2, iclass 36, count 0 2006.257.06:04:52.32#ibcon#flushed, iclass 36, count 0 2006.257.06:04:52.32#ibcon#about to write, iclass 36, count 0 2006.257.06:04:52.32#ibcon#wrote, iclass 36, count 0 2006.257.06:04:52.32#ibcon#about to read 3, iclass 36, count 0 2006.257.06:04:52.35#ibcon#read 3, iclass 36, count 0 2006.257.06:04:52.35#ibcon#about to read 4, iclass 36, count 0 2006.257.06:04:52.35#ibcon#read 4, iclass 36, count 0 2006.257.06:04:52.35#ibcon#about to read 5, iclass 36, count 0 2006.257.06:04:52.35#ibcon#read 5, iclass 36, count 0 2006.257.06:04:52.35#ibcon#about to read 6, iclass 36, count 0 2006.257.06:04:52.35#ibcon#read 6, iclass 36, count 0 2006.257.06:04:52.35#ibcon#end of sib2, iclass 36, count 0 2006.257.06:04:52.35#ibcon#*after write, iclass 36, count 0 2006.257.06:04:52.35#ibcon#*before return 0, iclass 36, count 0 2006.257.06:04:52.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:52.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:52.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:04:52.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:04:52.36$vck44/valo=7,864.99 2006.257.06:04:52.36#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.06:04:52.36#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.06:04:52.36#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:52.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:52.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:52.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:52.36#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:04:52.36#ibcon#first serial, iclass 38, count 0 2006.257.06:04:52.36#ibcon#enter sib2, iclass 38, count 0 2006.257.06:04:52.36#ibcon#flushed, iclass 38, count 0 2006.257.06:04:52.36#ibcon#about to write, iclass 38, count 0 2006.257.06:04:52.36#ibcon#wrote, iclass 38, count 0 2006.257.06:04:52.36#ibcon#about to read 3, iclass 38, count 0 2006.257.06:04:52.37#ibcon#read 3, iclass 38, count 0 2006.257.06:04:52.37#ibcon#about to read 4, iclass 38, count 0 2006.257.06:04:52.37#ibcon#read 4, iclass 38, count 0 2006.257.06:04:52.37#ibcon#about to read 5, iclass 38, count 0 2006.257.06:04:52.37#ibcon#read 5, iclass 38, count 0 2006.257.06:04:52.37#ibcon#about to read 6, iclass 38, count 0 2006.257.06:04:52.37#ibcon#read 6, iclass 38, count 0 2006.257.06:04:52.37#ibcon#end of sib2, iclass 38, count 0 2006.257.06:04:52.37#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:04:52.37#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:04:52.37#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:04:52.37#ibcon#*before write, iclass 38, count 0 2006.257.06:04:52.37#ibcon#enter sib2, iclass 38, count 0 2006.257.06:04:52.37#ibcon#flushed, iclass 38, count 0 2006.257.06:04:52.37#ibcon#about to write, iclass 38, count 0 2006.257.06:04:52.37#ibcon#wrote, iclass 38, count 0 2006.257.06:04:52.37#ibcon#about to read 3, iclass 38, count 0 2006.257.06:04:52.41#ibcon#read 3, iclass 38, count 0 2006.257.06:04:52.41#ibcon#about to read 4, iclass 38, count 0 2006.257.06:04:52.41#ibcon#read 4, iclass 38, count 0 2006.257.06:04:52.41#ibcon#about to read 5, iclass 38, count 0 2006.257.06:04:52.41#ibcon#read 5, iclass 38, count 0 2006.257.06:04:52.41#ibcon#about to read 6, iclass 38, count 0 2006.257.06:04:52.41#ibcon#read 6, iclass 38, count 0 2006.257.06:04:52.41#ibcon#end of sib2, iclass 38, count 0 2006.257.06:04:52.41#ibcon#*after write, iclass 38, count 0 2006.257.06:04:52.41#ibcon#*before return 0, iclass 38, count 0 2006.257.06:04:52.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:52.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:52.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:04:52.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:04:52.41$vck44/va=7,4 2006.257.06:04:52.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.06:04:52.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.06:04:52.41#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:52.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:52.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:52.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:52.47#ibcon#enter wrdev, iclass 40, count 2 2006.257.06:04:52.47#ibcon#first serial, iclass 40, count 2 2006.257.06:04:52.47#ibcon#enter sib2, iclass 40, count 2 2006.257.06:04:52.47#ibcon#flushed, iclass 40, count 2 2006.257.06:04:52.47#ibcon#about to write, iclass 40, count 2 2006.257.06:04:52.47#ibcon#wrote, iclass 40, count 2 2006.257.06:04:52.47#ibcon#about to read 3, iclass 40, count 2 2006.257.06:04:52.49#ibcon#read 3, iclass 40, count 2 2006.257.06:04:52.49#ibcon#about to read 4, iclass 40, count 2 2006.257.06:04:52.49#ibcon#read 4, iclass 40, count 2 2006.257.06:04:52.49#ibcon#about to read 5, iclass 40, count 2 2006.257.06:04:52.49#ibcon#read 5, iclass 40, count 2 2006.257.06:04:52.49#ibcon#about to read 6, iclass 40, count 2 2006.257.06:04:52.49#ibcon#read 6, iclass 40, count 2 2006.257.06:04:52.49#ibcon#end of sib2, iclass 40, count 2 2006.257.06:04:52.49#ibcon#*mode == 0, iclass 40, count 2 2006.257.06:04:52.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.06:04:52.49#ibcon#[25=AT07-04\r\n] 2006.257.06:04:52.49#ibcon#*before write, iclass 40, count 2 2006.257.06:04:52.49#ibcon#enter sib2, iclass 40, count 2 2006.257.06:04:52.49#ibcon#flushed, iclass 40, count 2 2006.257.06:04:52.49#ibcon#about to write, iclass 40, count 2 2006.257.06:04:52.49#ibcon#wrote, iclass 40, count 2 2006.257.06:04:52.49#ibcon#about to read 3, iclass 40, count 2 2006.257.06:04:52.52#ibcon#read 3, iclass 40, count 2 2006.257.06:04:52.52#ibcon#about to read 4, iclass 40, count 2 2006.257.06:04:52.52#ibcon#read 4, iclass 40, count 2 2006.257.06:04:52.52#ibcon#about to read 5, iclass 40, count 2 2006.257.06:04:52.52#ibcon#read 5, iclass 40, count 2 2006.257.06:04:52.52#ibcon#about to read 6, iclass 40, count 2 2006.257.06:04:52.52#ibcon#read 6, iclass 40, count 2 2006.257.06:04:52.52#ibcon#end of sib2, iclass 40, count 2 2006.257.06:04:52.52#ibcon#*after write, iclass 40, count 2 2006.257.06:04:52.52#ibcon#*before return 0, iclass 40, count 2 2006.257.06:04:52.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:52.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:52.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.06:04:52.52#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:52.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:52.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:52.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:52.64#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:04:52.64#ibcon#first serial, iclass 40, count 0 2006.257.06:04:52.64#ibcon#enter sib2, iclass 40, count 0 2006.257.06:04:52.64#ibcon#flushed, iclass 40, count 0 2006.257.06:04:52.64#ibcon#about to write, iclass 40, count 0 2006.257.06:04:52.64#ibcon#wrote, iclass 40, count 0 2006.257.06:04:52.64#ibcon#about to read 3, iclass 40, count 0 2006.257.06:04:52.66#ibcon#read 3, iclass 40, count 0 2006.257.06:04:52.66#ibcon#about to read 4, iclass 40, count 0 2006.257.06:04:52.66#ibcon#read 4, iclass 40, count 0 2006.257.06:04:52.66#ibcon#about to read 5, iclass 40, count 0 2006.257.06:04:52.66#ibcon#read 5, iclass 40, count 0 2006.257.06:04:52.66#ibcon#about to read 6, iclass 40, count 0 2006.257.06:04:52.66#ibcon#read 6, iclass 40, count 0 2006.257.06:04:52.66#ibcon#end of sib2, iclass 40, count 0 2006.257.06:04:52.66#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:04:52.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:04:52.66#ibcon#[25=USB\r\n] 2006.257.06:04:52.66#ibcon#*before write, iclass 40, count 0 2006.257.06:04:52.66#ibcon#enter sib2, iclass 40, count 0 2006.257.06:04:52.66#ibcon#flushed, iclass 40, count 0 2006.257.06:04:52.66#ibcon#about to write, iclass 40, count 0 2006.257.06:04:52.66#ibcon#wrote, iclass 40, count 0 2006.257.06:04:52.66#ibcon#about to read 3, iclass 40, count 0 2006.257.06:04:52.69#ibcon#read 3, iclass 40, count 0 2006.257.06:04:52.69#ibcon#about to read 4, iclass 40, count 0 2006.257.06:04:52.69#ibcon#read 4, iclass 40, count 0 2006.257.06:04:52.69#ibcon#about to read 5, iclass 40, count 0 2006.257.06:04:52.69#ibcon#read 5, iclass 40, count 0 2006.257.06:04:52.69#ibcon#about to read 6, iclass 40, count 0 2006.257.06:04:52.69#ibcon#read 6, iclass 40, count 0 2006.257.06:04:52.69#ibcon#end of sib2, iclass 40, count 0 2006.257.06:04:52.69#ibcon#*after write, iclass 40, count 0 2006.257.06:04:52.69#ibcon#*before return 0, iclass 40, count 0 2006.257.06:04:52.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:52.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:52.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:04:52.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:04:52.69$vck44/valo=8,884.99 2006.257.06:04:52.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.06:04:52.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.06:04:52.69#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:52.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:52.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:52.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:52.69#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:04:52.69#ibcon#first serial, iclass 4, count 0 2006.257.06:04:52.69#ibcon#enter sib2, iclass 4, count 0 2006.257.06:04:52.70#ibcon#flushed, iclass 4, count 0 2006.257.06:04:52.70#ibcon#about to write, iclass 4, count 0 2006.257.06:04:52.70#ibcon#wrote, iclass 4, count 0 2006.257.06:04:52.70#ibcon#about to read 3, iclass 4, count 0 2006.257.06:04:52.71#ibcon#read 3, iclass 4, count 0 2006.257.06:04:52.71#ibcon#about to read 4, iclass 4, count 0 2006.257.06:04:52.71#ibcon#read 4, iclass 4, count 0 2006.257.06:04:52.71#ibcon#about to read 5, iclass 4, count 0 2006.257.06:04:52.71#ibcon#read 5, iclass 4, count 0 2006.257.06:04:52.71#ibcon#about to read 6, iclass 4, count 0 2006.257.06:04:52.71#ibcon#read 6, iclass 4, count 0 2006.257.06:04:52.71#ibcon#end of sib2, iclass 4, count 0 2006.257.06:04:52.71#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:04:52.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:04:52.71#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:04:52.71#ibcon#*before write, iclass 4, count 0 2006.257.06:04:52.71#ibcon#enter sib2, iclass 4, count 0 2006.257.06:04:52.71#ibcon#flushed, iclass 4, count 0 2006.257.06:04:52.71#ibcon#about to write, iclass 4, count 0 2006.257.06:04:52.71#ibcon#wrote, iclass 4, count 0 2006.257.06:04:52.71#ibcon#about to read 3, iclass 4, count 0 2006.257.06:04:52.75#ibcon#read 3, iclass 4, count 0 2006.257.06:04:52.75#ibcon#about to read 4, iclass 4, count 0 2006.257.06:04:52.75#ibcon#read 4, iclass 4, count 0 2006.257.06:04:52.75#ibcon#about to read 5, iclass 4, count 0 2006.257.06:04:52.75#ibcon#read 5, iclass 4, count 0 2006.257.06:04:52.75#ibcon#about to read 6, iclass 4, count 0 2006.257.06:04:52.75#ibcon#read 6, iclass 4, count 0 2006.257.06:04:52.75#ibcon#end of sib2, iclass 4, count 0 2006.257.06:04:52.75#ibcon#*after write, iclass 4, count 0 2006.257.06:04:52.75#ibcon#*before return 0, iclass 4, count 0 2006.257.06:04:52.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:52.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:52.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:04:52.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:04:52.75$vck44/va=8,4 2006.257.06:04:52.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.06:04:52.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.06:04:52.75#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:52.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:04:52.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:04:52.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:04:52.81#ibcon#enter wrdev, iclass 6, count 2 2006.257.06:04:52.81#ibcon#first serial, iclass 6, count 2 2006.257.06:04:52.81#ibcon#enter sib2, iclass 6, count 2 2006.257.06:04:52.81#ibcon#flushed, iclass 6, count 2 2006.257.06:04:52.81#ibcon#about to write, iclass 6, count 2 2006.257.06:04:52.81#ibcon#wrote, iclass 6, count 2 2006.257.06:04:52.81#ibcon#about to read 3, iclass 6, count 2 2006.257.06:04:52.83#ibcon#read 3, iclass 6, count 2 2006.257.06:04:52.83#ibcon#about to read 4, iclass 6, count 2 2006.257.06:04:52.83#ibcon#read 4, iclass 6, count 2 2006.257.06:04:52.83#ibcon#about to read 5, iclass 6, count 2 2006.257.06:04:52.83#ibcon#read 5, iclass 6, count 2 2006.257.06:04:52.83#ibcon#about to read 6, iclass 6, count 2 2006.257.06:04:52.83#ibcon#read 6, iclass 6, count 2 2006.257.06:04:52.83#ibcon#end of sib2, iclass 6, count 2 2006.257.06:04:52.83#ibcon#*mode == 0, iclass 6, count 2 2006.257.06:04:52.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.06:04:52.83#ibcon#[25=AT08-04\r\n] 2006.257.06:04:52.83#ibcon#*before write, iclass 6, count 2 2006.257.06:04:52.83#ibcon#enter sib2, iclass 6, count 2 2006.257.06:04:52.83#ibcon#flushed, iclass 6, count 2 2006.257.06:04:52.83#ibcon#about to write, iclass 6, count 2 2006.257.06:04:52.83#ibcon#wrote, iclass 6, count 2 2006.257.06:04:52.83#ibcon#about to read 3, iclass 6, count 2 2006.257.06:04:52.86#ibcon#read 3, iclass 6, count 2 2006.257.06:04:52.86#ibcon#about to read 4, iclass 6, count 2 2006.257.06:04:52.86#ibcon#read 4, iclass 6, count 2 2006.257.06:04:52.86#ibcon#about to read 5, iclass 6, count 2 2006.257.06:04:52.86#ibcon#read 5, iclass 6, count 2 2006.257.06:04:52.86#ibcon#about to read 6, iclass 6, count 2 2006.257.06:04:52.86#ibcon#read 6, iclass 6, count 2 2006.257.06:04:52.86#ibcon#end of sib2, iclass 6, count 2 2006.257.06:04:52.86#ibcon#*after write, iclass 6, count 2 2006.257.06:04:52.86#ibcon#*before return 0, iclass 6, count 2 2006.257.06:04:52.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:04:52.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:04:52.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.06:04:52.86#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:52.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:04:52.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:04:52.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:04:52.98#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:04:52.98#ibcon#first serial, iclass 6, count 0 2006.257.06:04:52.98#ibcon#enter sib2, iclass 6, count 0 2006.257.06:04:52.98#ibcon#flushed, iclass 6, count 0 2006.257.06:04:52.98#ibcon#about to write, iclass 6, count 0 2006.257.06:04:52.98#ibcon#wrote, iclass 6, count 0 2006.257.06:04:52.98#ibcon#about to read 3, iclass 6, count 0 2006.257.06:04:53.00#ibcon#read 3, iclass 6, count 0 2006.257.06:04:53.00#ibcon#about to read 4, iclass 6, count 0 2006.257.06:04:53.00#ibcon#read 4, iclass 6, count 0 2006.257.06:04:53.00#ibcon#about to read 5, iclass 6, count 0 2006.257.06:04:53.00#ibcon#read 5, iclass 6, count 0 2006.257.06:04:53.00#ibcon#about to read 6, iclass 6, count 0 2006.257.06:04:53.00#ibcon#read 6, iclass 6, count 0 2006.257.06:04:53.00#ibcon#end of sib2, iclass 6, count 0 2006.257.06:04:53.00#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:04:53.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:04:53.00#ibcon#[25=USB\r\n] 2006.257.06:04:53.00#ibcon#*before write, iclass 6, count 0 2006.257.06:04:53.00#ibcon#enter sib2, iclass 6, count 0 2006.257.06:04:53.00#ibcon#flushed, iclass 6, count 0 2006.257.06:04:53.00#ibcon#about to write, iclass 6, count 0 2006.257.06:04:53.00#ibcon#wrote, iclass 6, count 0 2006.257.06:04:53.00#ibcon#about to read 3, iclass 6, count 0 2006.257.06:04:53.03#ibcon#read 3, iclass 6, count 0 2006.257.06:04:53.03#ibcon#about to read 4, iclass 6, count 0 2006.257.06:04:53.03#ibcon#read 4, iclass 6, count 0 2006.257.06:04:53.03#ibcon#about to read 5, iclass 6, count 0 2006.257.06:04:53.03#ibcon#read 5, iclass 6, count 0 2006.257.06:04:53.03#ibcon#about to read 6, iclass 6, count 0 2006.257.06:04:53.03#ibcon#read 6, iclass 6, count 0 2006.257.06:04:53.03#ibcon#end of sib2, iclass 6, count 0 2006.257.06:04:53.03#ibcon#*after write, iclass 6, count 0 2006.257.06:04:53.03#ibcon#*before return 0, iclass 6, count 0 2006.257.06:04:53.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:04:53.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:04:53.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:04:53.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:04:53.03$vck44/vblo=1,629.99 2006.257.06:04:53.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.06:04:53.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.06:04:53.03#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:53.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:04:53.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:04:53.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:04:53.03#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:04:53.04#ibcon#first serial, iclass 10, count 0 2006.257.06:04:53.04#ibcon#enter sib2, iclass 10, count 0 2006.257.06:04:53.04#ibcon#flushed, iclass 10, count 0 2006.257.06:04:53.04#ibcon#about to write, iclass 10, count 0 2006.257.06:04:53.04#ibcon#wrote, iclass 10, count 0 2006.257.06:04:53.04#ibcon#about to read 3, iclass 10, count 0 2006.257.06:04:53.05#ibcon#read 3, iclass 10, count 0 2006.257.06:04:53.05#ibcon#about to read 4, iclass 10, count 0 2006.257.06:04:53.05#ibcon#read 4, iclass 10, count 0 2006.257.06:04:53.05#ibcon#about to read 5, iclass 10, count 0 2006.257.06:04:53.05#ibcon#read 5, iclass 10, count 0 2006.257.06:04:53.05#ibcon#about to read 6, iclass 10, count 0 2006.257.06:04:53.05#ibcon#read 6, iclass 10, count 0 2006.257.06:04:53.05#ibcon#end of sib2, iclass 10, count 0 2006.257.06:04:53.05#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:04:53.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:04:53.05#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:04:53.05#ibcon#*before write, iclass 10, count 0 2006.257.06:04:53.05#ibcon#enter sib2, iclass 10, count 0 2006.257.06:04:53.05#ibcon#flushed, iclass 10, count 0 2006.257.06:04:53.05#ibcon#about to write, iclass 10, count 0 2006.257.06:04:53.05#ibcon#wrote, iclass 10, count 0 2006.257.06:04:53.05#ibcon#about to read 3, iclass 10, count 0 2006.257.06:04:53.09#ibcon#read 3, iclass 10, count 0 2006.257.06:04:53.09#ibcon#about to read 4, iclass 10, count 0 2006.257.06:04:53.09#ibcon#read 4, iclass 10, count 0 2006.257.06:04:53.09#ibcon#about to read 5, iclass 10, count 0 2006.257.06:04:53.09#ibcon#read 5, iclass 10, count 0 2006.257.06:04:53.09#ibcon#about to read 6, iclass 10, count 0 2006.257.06:04:53.09#ibcon#read 6, iclass 10, count 0 2006.257.06:04:53.09#ibcon#end of sib2, iclass 10, count 0 2006.257.06:04:53.09#ibcon#*after write, iclass 10, count 0 2006.257.06:04:53.09#ibcon#*before return 0, iclass 10, count 0 2006.257.06:04:53.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:04:53.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:04:53.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:04:53.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:04:53.09$vck44/vb=1,4 2006.257.06:04:53.09#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.06:04:53.09#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.06:04:53.09#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:53.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:04:53.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:04:53.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:04:53.09#ibcon#enter wrdev, iclass 12, count 2 2006.257.06:04:53.10#ibcon#first serial, iclass 12, count 2 2006.257.06:04:53.10#ibcon#enter sib2, iclass 12, count 2 2006.257.06:04:53.10#ibcon#flushed, iclass 12, count 2 2006.257.06:04:53.10#ibcon#about to write, iclass 12, count 2 2006.257.06:04:53.10#ibcon#wrote, iclass 12, count 2 2006.257.06:04:53.10#ibcon#about to read 3, iclass 12, count 2 2006.257.06:04:53.11#ibcon#read 3, iclass 12, count 2 2006.257.06:04:53.11#ibcon#about to read 4, iclass 12, count 2 2006.257.06:04:53.11#ibcon#read 4, iclass 12, count 2 2006.257.06:04:53.11#ibcon#about to read 5, iclass 12, count 2 2006.257.06:04:53.11#ibcon#read 5, iclass 12, count 2 2006.257.06:04:53.11#ibcon#about to read 6, iclass 12, count 2 2006.257.06:04:53.11#ibcon#read 6, iclass 12, count 2 2006.257.06:04:53.11#ibcon#end of sib2, iclass 12, count 2 2006.257.06:04:53.11#ibcon#*mode == 0, iclass 12, count 2 2006.257.06:04:53.11#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.06:04:53.11#ibcon#[27=AT01-04\r\n] 2006.257.06:04:53.11#ibcon#*before write, iclass 12, count 2 2006.257.06:04:53.11#ibcon#enter sib2, iclass 12, count 2 2006.257.06:04:53.11#ibcon#flushed, iclass 12, count 2 2006.257.06:04:53.11#ibcon#about to write, iclass 12, count 2 2006.257.06:04:53.11#ibcon#wrote, iclass 12, count 2 2006.257.06:04:53.11#ibcon#about to read 3, iclass 12, count 2 2006.257.06:04:53.14#ibcon#read 3, iclass 12, count 2 2006.257.06:04:53.15#ibcon#about to read 4, iclass 12, count 2 2006.257.06:04:53.15#ibcon#read 4, iclass 12, count 2 2006.257.06:04:53.15#ibcon#about to read 5, iclass 12, count 2 2006.257.06:04:53.15#ibcon#read 5, iclass 12, count 2 2006.257.06:04:53.15#ibcon#about to read 6, iclass 12, count 2 2006.257.06:04:53.15#ibcon#read 6, iclass 12, count 2 2006.257.06:04:53.15#ibcon#end of sib2, iclass 12, count 2 2006.257.06:04:53.15#ibcon#*after write, iclass 12, count 2 2006.257.06:04:53.15#ibcon#*before return 0, iclass 12, count 2 2006.257.06:04:53.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:04:53.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:04:53.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.06:04:53.15#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:53.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:04:53.26#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:04:53.26#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:04:53.26#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:04:53.26#ibcon#first serial, iclass 12, count 0 2006.257.06:04:53.26#ibcon#enter sib2, iclass 12, count 0 2006.257.06:04:53.26#ibcon#flushed, iclass 12, count 0 2006.257.06:04:53.26#ibcon#about to write, iclass 12, count 0 2006.257.06:04:53.26#ibcon#wrote, iclass 12, count 0 2006.257.06:04:53.26#ibcon#about to read 3, iclass 12, count 0 2006.257.06:04:53.28#ibcon#read 3, iclass 12, count 0 2006.257.06:04:53.28#ibcon#about to read 4, iclass 12, count 0 2006.257.06:04:53.28#ibcon#read 4, iclass 12, count 0 2006.257.06:04:53.28#ibcon#about to read 5, iclass 12, count 0 2006.257.06:04:53.28#ibcon#read 5, iclass 12, count 0 2006.257.06:04:53.28#ibcon#about to read 6, iclass 12, count 0 2006.257.06:04:53.28#ibcon#read 6, iclass 12, count 0 2006.257.06:04:53.28#ibcon#end of sib2, iclass 12, count 0 2006.257.06:04:53.28#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:04:53.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:04:53.28#ibcon#[27=USB\r\n] 2006.257.06:04:53.28#ibcon#*before write, iclass 12, count 0 2006.257.06:04:53.28#ibcon#enter sib2, iclass 12, count 0 2006.257.06:04:53.28#ibcon#flushed, iclass 12, count 0 2006.257.06:04:53.28#ibcon#about to write, iclass 12, count 0 2006.257.06:04:53.28#ibcon#wrote, iclass 12, count 0 2006.257.06:04:53.28#ibcon#about to read 3, iclass 12, count 0 2006.257.06:04:53.31#ibcon#read 3, iclass 12, count 0 2006.257.06:04:53.31#ibcon#about to read 4, iclass 12, count 0 2006.257.06:04:53.31#ibcon#read 4, iclass 12, count 0 2006.257.06:04:53.31#ibcon#about to read 5, iclass 12, count 0 2006.257.06:04:53.31#ibcon#read 5, iclass 12, count 0 2006.257.06:04:53.31#ibcon#about to read 6, iclass 12, count 0 2006.257.06:04:53.31#ibcon#read 6, iclass 12, count 0 2006.257.06:04:53.31#ibcon#end of sib2, iclass 12, count 0 2006.257.06:04:53.31#ibcon#*after write, iclass 12, count 0 2006.257.06:04:53.31#ibcon#*before return 0, iclass 12, count 0 2006.257.06:04:53.31#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:04:53.31#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:04:53.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:04:53.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:04:53.31$vck44/vblo=2,634.99 2006.257.06:04:53.31#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.06:04:53.31#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.06:04:53.31#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:53.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:53.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:53.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:53.31#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:04:53.31#ibcon#first serial, iclass 14, count 0 2006.257.06:04:53.32#ibcon#enter sib2, iclass 14, count 0 2006.257.06:04:53.32#ibcon#flushed, iclass 14, count 0 2006.257.06:04:53.32#ibcon#about to write, iclass 14, count 0 2006.257.06:04:53.32#ibcon#wrote, iclass 14, count 0 2006.257.06:04:53.32#ibcon#about to read 3, iclass 14, count 0 2006.257.06:04:53.33#ibcon#read 3, iclass 14, count 0 2006.257.06:04:53.33#ibcon#about to read 4, iclass 14, count 0 2006.257.06:04:53.33#ibcon#read 4, iclass 14, count 0 2006.257.06:04:53.33#ibcon#about to read 5, iclass 14, count 0 2006.257.06:04:53.33#ibcon#read 5, iclass 14, count 0 2006.257.06:04:53.33#ibcon#about to read 6, iclass 14, count 0 2006.257.06:04:53.33#ibcon#read 6, iclass 14, count 0 2006.257.06:04:53.33#ibcon#end of sib2, iclass 14, count 0 2006.257.06:04:53.33#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:04:53.33#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:04:53.33#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:04:53.33#ibcon#*before write, iclass 14, count 0 2006.257.06:04:53.33#ibcon#enter sib2, iclass 14, count 0 2006.257.06:04:53.33#ibcon#flushed, iclass 14, count 0 2006.257.06:04:53.33#ibcon#about to write, iclass 14, count 0 2006.257.06:04:53.33#ibcon#wrote, iclass 14, count 0 2006.257.06:04:53.33#ibcon#about to read 3, iclass 14, count 0 2006.257.06:04:53.37#ibcon#read 3, iclass 14, count 0 2006.257.06:04:53.37#ibcon#about to read 4, iclass 14, count 0 2006.257.06:04:53.37#ibcon#read 4, iclass 14, count 0 2006.257.06:04:53.37#ibcon#about to read 5, iclass 14, count 0 2006.257.06:04:53.37#ibcon#read 5, iclass 14, count 0 2006.257.06:04:53.37#ibcon#about to read 6, iclass 14, count 0 2006.257.06:04:53.37#ibcon#read 6, iclass 14, count 0 2006.257.06:04:53.37#ibcon#end of sib2, iclass 14, count 0 2006.257.06:04:53.37#ibcon#*after write, iclass 14, count 0 2006.257.06:04:53.37#ibcon#*before return 0, iclass 14, count 0 2006.257.06:04:53.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:53.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:04:53.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:04:53.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:04:53.37$vck44/vb=2,5 2006.257.06:04:53.37#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.06:04:53.37#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.06:04:53.37#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:53.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:53.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:53.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:53.43#ibcon#enter wrdev, iclass 16, count 2 2006.257.06:04:53.43#ibcon#first serial, iclass 16, count 2 2006.257.06:04:53.43#ibcon#enter sib2, iclass 16, count 2 2006.257.06:04:53.43#ibcon#flushed, iclass 16, count 2 2006.257.06:04:53.43#ibcon#about to write, iclass 16, count 2 2006.257.06:04:53.43#ibcon#wrote, iclass 16, count 2 2006.257.06:04:53.43#ibcon#about to read 3, iclass 16, count 2 2006.257.06:04:53.45#ibcon#read 3, iclass 16, count 2 2006.257.06:04:53.45#ibcon#about to read 4, iclass 16, count 2 2006.257.06:04:53.45#ibcon#read 4, iclass 16, count 2 2006.257.06:04:53.45#ibcon#about to read 5, iclass 16, count 2 2006.257.06:04:53.45#ibcon#read 5, iclass 16, count 2 2006.257.06:04:53.45#ibcon#about to read 6, iclass 16, count 2 2006.257.06:04:53.45#ibcon#read 6, iclass 16, count 2 2006.257.06:04:53.45#ibcon#end of sib2, iclass 16, count 2 2006.257.06:04:53.45#ibcon#*mode == 0, iclass 16, count 2 2006.257.06:04:53.45#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.06:04:53.45#ibcon#[27=AT02-05\r\n] 2006.257.06:04:53.45#ibcon#*before write, iclass 16, count 2 2006.257.06:04:53.45#ibcon#enter sib2, iclass 16, count 2 2006.257.06:04:53.45#ibcon#flushed, iclass 16, count 2 2006.257.06:04:53.45#ibcon#about to write, iclass 16, count 2 2006.257.06:04:53.45#ibcon#wrote, iclass 16, count 2 2006.257.06:04:53.45#ibcon#about to read 3, iclass 16, count 2 2006.257.06:04:53.48#ibcon#read 3, iclass 16, count 2 2006.257.06:04:53.48#ibcon#about to read 4, iclass 16, count 2 2006.257.06:04:53.48#ibcon#read 4, iclass 16, count 2 2006.257.06:04:53.48#ibcon#about to read 5, iclass 16, count 2 2006.257.06:04:53.48#ibcon#read 5, iclass 16, count 2 2006.257.06:04:53.48#ibcon#about to read 6, iclass 16, count 2 2006.257.06:04:53.48#ibcon#read 6, iclass 16, count 2 2006.257.06:04:53.48#ibcon#end of sib2, iclass 16, count 2 2006.257.06:04:53.48#ibcon#*after write, iclass 16, count 2 2006.257.06:04:53.48#ibcon#*before return 0, iclass 16, count 2 2006.257.06:04:53.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:53.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:04:53.48#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.06:04:53.48#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:53.48#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:53.60#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:53.60#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:53.60#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:04:53.60#ibcon#first serial, iclass 16, count 0 2006.257.06:04:53.60#ibcon#enter sib2, iclass 16, count 0 2006.257.06:04:53.60#ibcon#flushed, iclass 16, count 0 2006.257.06:04:53.60#ibcon#about to write, iclass 16, count 0 2006.257.06:04:53.60#ibcon#wrote, iclass 16, count 0 2006.257.06:04:53.60#ibcon#about to read 3, iclass 16, count 0 2006.257.06:04:53.62#ibcon#read 3, iclass 16, count 0 2006.257.06:04:53.62#ibcon#about to read 4, iclass 16, count 0 2006.257.06:04:53.62#ibcon#read 4, iclass 16, count 0 2006.257.06:04:53.62#ibcon#about to read 5, iclass 16, count 0 2006.257.06:04:53.62#ibcon#read 5, iclass 16, count 0 2006.257.06:04:53.62#ibcon#about to read 6, iclass 16, count 0 2006.257.06:04:53.62#ibcon#read 6, iclass 16, count 0 2006.257.06:04:53.62#ibcon#end of sib2, iclass 16, count 0 2006.257.06:04:53.62#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:04:53.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:04:53.62#ibcon#[27=USB\r\n] 2006.257.06:04:53.62#ibcon#*before write, iclass 16, count 0 2006.257.06:04:53.62#ibcon#enter sib2, iclass 16, count 0 2006.257.06:04:53.62#ibcon#flushed, iclass 16, count 0 2006.257.06:04:53.62#ibcon#about to write, iclass 16, count 0 2006.257.06:04:53.62#ibcon#wrote, iclass 16, count 0 2006.257.06:04:53.62#ibcon#about to read 3, iclass 16, count 0 2006.257.06:04:53.65#ibcon#read 3, iclass 16, count 0 2006.257.06:04:53.65#ibcon#about to read 4, iclass 16, count 0 2006.257.06:04:53.65#ibcon#read 4, iclass 16, count 0 2006.257.06:04:53.65#ibcon#about to read 5, iclass 16, count 0 2006.257.06:04:53.65#ibcon#read 5, iclass 16, count 0 2006.257.06:04:53.65#ibcon#about to read 6, iclass 16, count 0 2006.257.06:04:53.65#ibcon#read 6, iclass 16, count 0 2006.257.06:04:53.65#ibcon#end of sib2, iclass 16, count 0 2006.257.06:04:53.65#ibcon#*after write, iclass 16, count 0 2006.257.06:04:53.65#ibcon#*before return 0, iclass 16, count 0 2006.257.06:04:53.65#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:53.65#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:04:53.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:04:53.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:04:53.65$vck44/vblo=3,649.99 2006.257.06:04:53.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.06:04:53.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.06:04:53.65#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:53.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:53.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:53.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:53.65#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:04:53.66#ibcon#first serial, iclass 18, count 0 2006.257.06:04:53.66#ibcon#enter sib2, iclass 18, count 0 2006.257.06:04:53.66#ibcon#flushed, iclass 18, count 0 2006.257.06:04:53.66#ibcon#about to write, iclass 18, count 0 2006.257.06:04:53.66#ibcon#wrote, iclass 18, count 0 2006.257.06:04:53.66#ibcon#about to read 3, iclass 18, count 0 2006.257.06:04:53.67#ibcon#read 3, iclass 18, count 0 2006.257.06:04:53.67#ibcon#about to read 4, iclass 18, count 0 2006.257.06:04:53.67#ibcon#read 4, iclass 18, count 0 2006.257.06:04:53.67#ibcon#about to read 5, iclass 18, count 0 2006.257.06:04:53.67#ibcon#read 5, iclass 18, count 0 2006.257.06:04:53.67#ibcon#about to read 6, iclass 18, count 0 2006.257.06:04:53.67#ibcon#read 6, iclass 18, count 0 2006.257.06:04:53.67#ibcon#end of sib2, iclass 18, count 0 2006.257.06:04:53.67#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:04:53.67#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:04:53.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:04:53.67#ibcon#*before write, iclass 18, count 0 2006.257.06:04:53.67#ibcon#enter sib2, iclass 18, count 0 2006.257.06:04:53.67#ibcon#flushed, iclass 18, count 0 2006.257.06:04:53.67#ibcon#about to write, iclass 18, count 0 2006.257.06:04:53.67#ibcon#wrote, iclass 18, count 0 2006.257.06:04:53.67#ibcon#about to read 3, iclass 18, count 0 2006.257.06:04:53.71#ibcon#read 3, iclass 18, count 0 2006.257.06:04:53.71#ibcon#about to read 4, iclass 18, count 0 2006.257.06:04:53.71#ibcon#read 4, iclass 18, count 0 2006.257.06:04:53.71#ibcon#about to read 5, iclass 18, count 0 2006.257.06:04:53.71#ibcon#read 5, iclass 18, count 0 2006.257.06:04:53.71#ibcon#about to read 6, iclass 18, count 0 2006.257.06:04:53.71#ibcon#read 6, iclass 18, count 0 2006.257.06:04:53.71#ibcon#end of sib2, iclass 18, count 0 2006.257.06:04:53.71#ibcon#*after write, iclass 18, count 0 2006.257.06:04:53.71#ibcon#*before return 0, iclass 18, count 0 2006.257.06:04:53.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:53.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:04:53.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:04:53.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:04:53.71$vck44/vb=3,4 2006.257.06:04:53.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.06:04:53.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.06:04:53.71#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:53.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:53.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:53.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:53.77#ibcon#enter wrdev, iclass 20, count 2 2006.257.06:04:53.77#ibcon#first serial, iclass 20, count 2 2006.257.06:04:53.77#ibcon#enter sib2, iclass 20, count 2 2006.257.06:04:53.77#ibcon#flushed, iclass 20, count 2 2006.257.06:04:53.77#ibcon#about to write, iclass 20, count 2 2006.257.06:04:53.77#ibcon#wrote, iclass 20, count 2 2006.257.06:04:53.77#ibcon#about to read 3, iclass 20, count 2 2006.257.06:04:53.79#ibcon#read 3, iclass 20, count 2 2006.257.06:04:53.79#ibcon#about to read 4, iclass 20, count 2 2006.257.06:04:53.79#ibcon#read 4, iclass 20, count 2 2006.257.06:04:53.79#ibcon#about to read 5, iclass 20, count 2 2006.257.06:04:53.79#ibcon#read 5, iclass 20, count 2 2006.257.06:04:53.79#ibcon#about to read 6, iclass 20, count 2 2006.257.06:04:53.79#ibcon#read 6, iclass 20, count 2 2006.257.06:04:53.79#ibcon#end of sib2, iclass 20, count 2 2006.257.06:04:53.79#ibcon#*mode == 0, iclass 20, count 2 2006.257.06:04:53.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.06:04:53.79#ibcon#[27=AT03-04\r\n] 2006.257.06:04:53.79#ibcon#*before write, iclass 20, count 2 2006.257.06:04:53.79#ibcon#enter sib2, iclass 20, count 2 2006.257.06:04:53.79#ibcon#flushed, iclass 20, count 2 2006.257.06:04:53.79#ibcon#about to write, iclass 20, count 2 2006.257.06:04:53.79#ibcon#wrote, iclass 20, count 2 2006.257.06:04:53.79#ibcon#about to read 3, iclass 20, count 2 2006.257.06:04:53.82#ibcon#read 3, iclass 20, count 2 2006.257.06:04:53.82#ibcon#about to read 4, iclass 20, count 2 2006.257.06:04:53.82#ibcon#read 4, iclass 20, count 2 2006.257.06:04:53.82#ibcon#about to read 5, iclass 20, count 2 2006.257.06:04:53.82#ibcon#read 5, iclass 20, count 2 2006.257.06:04:53.82#ibcon#about to read 6, iclass 20, count 2 2006.257.06:04:53.82#ibcon#read 6, iclass 20, count 2 2006.257.06:04:53.82#ibcon#end of sib2, iclass 20, count 2 2006.257.06:04:53.82#ibcon#*after write, iclass 20, count 2 2006.257.06:04:53.82#ibcon#*before return 0, iclass 20, count 2 2006.257.06:04:53.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:53.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:04:53.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.06:04:53.82#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:53.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:53.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:53.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:53.94#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:04:53.94#ibcon#first serial, iclass 20, count 0 2006.257.06:04:53.94#ibcon#enter sib2, iclass 20, count 0 2006.257.06:04:53.94#ibcon#flushed, iclass 20, count 0 2006.257.06:04:53.94#ibcon#about to write, iclass 20, count 0 2006.257.06:04:53.94#ibcon#wrote, iclass 20, count 0 2006.257.06:04:53.94#ibcon#about to read 3, iclass 20, count 0 2006.257.06:04:53.96#ibcon#read 3, iclass 20, count 0 2006.257.06:04:53.96#ibcon#about to read 4, iclass 20, count 0 2006.257.06:04:53.96#ibcon#read 4, iclass 20, count 0 2006.257.06:04:53.96#ibcon#about to read 5, iclass 20, count 0 2006.257.06:04:53.96#ibcon#read 5, iclass 20, count 0 2006.257.06:04:53.96#ibcon#about to read 6, iclass 20, count 0 2006.257.06:04:53.96#ibcon#read 6, iclass 20, count 0 2006.257.06:04:53.96#ibcon#end of sib2, iclass 20, count 0 2006.257.06:04:53.96#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:04:53.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:04:53.96#ibcon#[27=USB\r\n] 2006.257.06:04:53.96#ibcon#*before write, iclass 20, count 0 2006.257.06:04:53.96#ibcon#enter sib2, iclass 20, count 0 2006.257.06:04:53.96#ibcon#flushed, iclass 20, count 0 2006.257.06:04:53.96#ibcon#about to write, iclass 20, count 0 2006.257.06:04:53.96#ibcon#wrote, iclass 20, count 0 2006.257.06:04:53.96#ibcon#about to read 3, iclass 20, count 0 2006.257.06:04:53.99#ibcon#read 3, iclass 20, count 0 2006.257.06:04:53.99#ibcon#about to read 4, iclass 20, count 0 2006.257.06:04:53.99#ibcon#read 4, iclass 20, count 0 2006.257.06:04:53.99#ibcon#about to read 5, iclass 20, count 0 2006.257.06:04:53.99#ibcon#read 5, iclass 20, count 0 2006.257.06:04:53.99#ibcon#about to read 6, iclass 20, count 0 2006.257.06:04:53.99#ibcon#read 6, iclass 20, count 0 2006.257.06:04:53.99#ibcon#end of sib2, iclass 20, count 0 2006.257.06:04:53.99#ibcon#*after write, iclass 20, count 0 2006.257.06:04:53.99#ibcon#*before return 0, iclass 20, count 0 2006.257.06:04:53.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:53.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:04:53.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:04:53.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:04:53.99$vck44/vblo=4,679.99 2006.257.06:04:53.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.06:04:53.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.06:04:53.99#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:53.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:53.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:54.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:54.00#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:04:54.00#ibcon#first serial, iclass 22, count 0 2006.257.06:04:54.00#ibcon#enter sib2, iclass 22, count 0 2006.257.06:04:54.00#ibcon#flushed, iclass 22, count 0 2006.257.06:04:54.00#ibcon#about to write, iclass 22, count 0 2006.257.06:04:54.00#ibcon#wrote, iclass 22, count 0 2006.257.06:04:54.00#ibcon#about to read 3, iclass 22, count 0 2006.257.06:04:54.01#ibcon#read 3, iclass 22, count 0 2006.257.06:04:54.01#ibcon#about to read 4, iclass 22, count 0 2006.257.06:04:54.01#ibcon#read 4, iclass 22, count 0 2006.257.06:04:54.01#ibcon#about to read 5, iclass 22, count 0 2006.257.06:04:54.01#ibcon#read 5, iclass 22, count 0 2006.257.06:04:54.01#ibcon#about to read 6, iclass 22, count 0 2006.257.06:04:54.01#ibcon#read 6, iclass 22, count 0 2006.257.06:04:54.01#ibcon#end of sib2, iclass 22, count 0 2006.257.06:04:54.01#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:04:54.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:04:54.01#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:04:54.01#ibcon#*before write, iclass 22, count 0 2006.257.06:04:54.01#ibcon#enter sib2, iclass 22, count 0 2006.257.06:04:54.01#ibcon#flushed, iclass 22, count 0 2006.257.06:04:54.01#ibcon#about to write, iclass 22, count 0 2006.257.06:04:54.01#ibcon#wrote, iclass 22, count 0 2006.257.06:04:54.01#ibcon#about to read 3, iclass 22, count 0 2006.257.06:04:54.05#ibcon#read 3, iclass 22, count 0 2006.257.06:04:54.05#ibcon#about to read 4, iclass 22, count 0 2006.257.06:04:54.05#ibcon#read 4, iclass 22, count 0 2006.257.06:04:54.05#ibcon#about to read 5, iclass 22, count 0 2006.257.06:04:54.05#ibcon#read 5, iclass 22, count 0 2006.257.06:04:54.05#ibcon#about to read 6, iclass 22, count 0 2006.257.06:04:54.05#ibcon#read 6, iclass 22, count 0 2006.257.06:04:54.05#ibcon#end of sib2, iclass 22, count 0 2006.257.06:04:54.05#ibcon#*after write, iclass 22, count 0 2006.257.06:04:54.05#ibcon#*before return 0, iclass 22, count 0 2006.257.06:04:54.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:54.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:04:54.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:04:54.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:04:54.05$vck44/vb=4,5 2006.257.06:04:54.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.06:04:54.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.06:04:54.05#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:54.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:54.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:54.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:54.11#ibcon#enter wrdev, iclass 24, count 2 2006.257.06:04:54.11#ibcon#first serial, iclass 24, count 2 2006.257.06:04:54.11#ibcon#enter sib2, iclass 24, count 2 2006.257.06:04:54.11#ibcon#flushed, iclass 24, count 2 2006.257.06:04:54.11#ibcon#about to write, iclass 24, count 2 2006.257.06:04:54.11#ibcon#wrote, iclass 24, count 2 2006.257.06:04:54.11#ibcon#about to read 3, iclass 24, count 2 2006.257.06:04:54.13#ibcon#read 3, iclass 24, count 2 2006.257.06:04:54.13#ibcon#about to read 4, iclass 24, count 2 2006.257.06:04:54.13#ibcon#read 4, iclass 24, count 2 2006.257.06:04:54.13#ibcon#about to read 5, iclass 24, count 2 2006.257.06:04:54.13#ibcon#read 5, iclass 24, count 2 2006.257.06:04:54.13#ibcon#about to read 6, iclass 24, count 2 2006.257.06:04:54.13#ibcon#read 6, iclass 24, count 2 2006.257.06:04:54.13#ibcon#end of sib2, iclass 24, count 2 2006.257.06:04:54.13#ibcon#*mode == 0, iclass 24, count 2 2006.257.06:04:54.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.06:04:54.13#ibcon#[27=AT04-05\r\n] 2006.257.06:04:54.13#ibcon#*before write, iclass 24, count 2 2006.257.06:04:54.13#ibcon#enter sib2, iclass 24, count 2 2006.257.06:04:54.13#ibcon#flushed, iclass 24, count 2 2006.257.06:04:54.13#ibcon#about to write, iclass 24, count 2 2006.257.06:04:54.13#ibcon#wrote, iclass 24, count 2 2006.257.06:04:54.13#ibcon#about to read 3, iclass 24, count 2 2006.257.06:04:54.16#ibcon#read 3, iclass 24, count 2 2006.257.06:04:54.16#ibcon#about to read 4, iclass 24, count 2 2006.257.06:04:54.16#ibcon#read 4, iclass 24, count 2 2006.257.06:04:54.16#ibcon#about to read 5, iclass 24, count 2 2006.257.06:04:54.16#ibcon#read 5, iclass 24, count 2 2006.257.06:04:54.16#ibcon#about to read 6, iclass 24, count 2 2006.257.06:04:54.16#ibcon#read 6, iclass 24, count 2 2006.257.06:04:54.16#ibcon#end of sib2, iclass 24, count 2 2006.257.06:04:54.16#ibcon#*after write, iclass 24, count 2 2006.257.06:04:54.16#ibcon#*before return 0, iclass 24, count 2 2006.257.06:04:54.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:54.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:04:54.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.06:04:54.16#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:54.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:54.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:54.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:54.28#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:04:54.28#ibcon#first serial, iclass 24, count 0 2006.257.06:04:54.28#ibcon#enter sib2, iclass 24, count 0 2006.257.06:04:54.28#ibcon#flushed, iclass 24, count 0 2006.257.06:04:54.28#ibcon#about to write, iclass 24, count 0 2006.257.06:04:54.28#ibcon#wrote, iclass 24, count 0 2006.257.06:04:54.28#ibcon#about to read 3, iclass 24, count 0 2006.257.06:04:54.30#ibcon#read 3, iclass 24, count 0 2006.257.06:04:54.30#ibcon#about to read 4, iclass 24, count 0 2006.257.06:04:54.30#ibcon#read 4, iclass 24, count 0 2006.257.06:04:54.30#ibcon#about to read 5, iclass 24, count 0 2006.257.06:04:54.30#ibcon#read 5, iclass 24, count 0 2006.257.06:04:54.30#ibcon#about to read 6, iclass 24, count 0 2006.257.06:04:54.30#ibcon#read 6, iclass 24, count 0 2006.257.06:04:54.30#ibcon#end of sib2, iclass 24, count 0 2006.257.06:04:54.30#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:04:54.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:04:54.30#ibcon#[27=USB\r\n] 2006.257.06:04:54.30#ibcon#*before write, iclass 24, count 0 2006.257.06:04:54.30#ibcon#enter sib2, iclass 24, count 0 2006.257.06:04:54.30#ibcon#flushed, iclass 24, count 0 2006.257.06:04:54.30#ibcon#about to write, iclass 24, count 0 2006.257.06:04:54.30#ibcon#wrote, iclass 24, count 0 2006.257.06:04:54.30#ibcon#about to read 3, iclass 24, count 0 2006.257.06:04:54.33#ibcon#read 3, iclass 24, count 0 2006.257.06:04:54.33#ibcon#about to read 4, iclass 24, count 0 2006.257.06:04:54.33#ibcon#read 4, iclass 24, count 0 2006.257.06:04:54.33#ibcon#about to read 5, iclass 24, count 0 2006.257.06:04:54.33#ibcon#read 5, iclass 24, count 0 2006.257.06:04:54.33#ibcon#about to read 6, iclass 24, count 0 2006.257.06:04:54.33#ibcon#read 6, iclass 24, count 0 2006.257.06:04:54.33#ibcon#end of sib2, iclass 24, count 0 2006.257.06:04:54.33#ibcon#*after write, iclass 24, count 0 2006.257.06:04:54.33#ibcon#*before return 0, iclass 24, count 0 2006.257.06:04:54.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:54.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:04:54.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:04:54.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:04:54.33$vck44/vblo=5,709.99 2006.257.06:04:54.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.06:04:54.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.06:04:54.33#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:54.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:54.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:54.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:54.33#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:04:54.34#ibcon#first serial, iclass 26, count 0 2006.257.06:04:54.34#ibcon#enter sib2, iclass 26, count 0 2006.257.06:04:54.34#ibcon#flushed, iclass 26, count 0 2006.257.06:04:54.34#ibcon#about to write, iclass 26, count 0 2006.257.06:04:54.34#ibcon#wrote, iclass 26, count 0 2006.257.06:04:54.34#ibcon#about to read 3, iclass 26, count 0 2006.257.06:04:54.35#ibcon#read 3, iclass 26, count 0 2006.257.06:04:54.35#ibcon#about to read 4, iclass 26, count 0 2006.257.06:04:54.35#ibcon#read 4, iclass 26, count 0 2006.257.06:04:54.35#ibcon#about to read 5, iclass 26, count 0 2006.257.06:04:54.35#ibcon#read 5, iclass 26, count 0 2006.257.06:04:54.35#ibcon#about to read 6, iclass 26, count 0 2006.257.06:04:54.35#ibcon#read 6, iclass 26, count 0 2006.257.06:04:54.35#ibcon#end of sib2, iclass 26, count 0 2006.257.06:04:54.35#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:04:54.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:04:54.35#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:04:54.35#ibcon#*before write, iclass 26, count 0 2006.257.06:04:54.35#ibcon#enter sib2, iclass 26, count 0 2006.257.06:04:54.35#ibcon#flushed, iclass 26, count 0 2006.257.06:04:54.35#ibcon#about to write, iclass 26, count 0 2006.257.06:04:54.35#ibcon#wrote, iclass 26, count 0 2006.257.06:04:54.35#ibcon#about to read 3, iclass 26, count 0 2006.257.06:04:54.39#ibcon#read 3, iclass 26, count 0 2006.257.06:04:54.39#ibcon#about to read 4, iclass 26, count 0 2006.257.06:04:54.39#ibcon#read 4, iclass 26, count 0 2006.257.06:04:54.39#ibcon#about to read 5, iclass 26, count 0 2006.257.06:04:54.39#ibcon#read 5, iclass 26, count 0 2006.257.06:04:54.39#ibcon#about to read 6, iclass 26, count 0 2006.257.06:04:54.39#ibcon#read 6, iclass 26, count 0 2006.257.06:04:54.39#ibcon#end of sib2, iclass 26, count 0 2006.257.06:04:54.39#ibcon#*after write, iclass 26, count 0 2006.257.06:04:54.39#ibcon#*before return 0, iclass 26, count 0 2006.257.06:04:54.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:54.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:04:54.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:04:54.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:04:54.39$vck44/vb=5,4 2006.257.06:04:54.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.06:04:54.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.06:04:54.39#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:54.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:54.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:54.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:54.44#ibcon#enter wrdev, iclass 28, count 2 2006.257.06:04:54.44#ibcon#first serial, iclass 28, count 2 2006.257.06:04:54.44#ibcon#enter sib2, iclass 28, count 2 2006.257.06:04:54.44#ibcon#flushed, iclass 28, count 2 2006.257.06:04:54.44#ibcon#about to write, iclass 28, count 2 2006.257.06:04:54.44#ibcon#wrote, iclass 28, count 2 2006.257.06:04:54.44#ibcon#about to read 3, iclass 28, count 2 2006.257.06:04:54.46#ibcon#read 3, iclass 28, count 2 2006.257.06:04:54.46#ibcon#about to read 4, iclass 28, count 2 2006.257.06:04:54.46#ibcon#read 4, iclass 28, count 2 2006.257.06:04:54.46#ibcon#about to read 5, iclass 28, count 2 2006.257.06:04:54.46#ibcon#read 5, iclass 28, count 2 2006.257.06:04:54.46#ibcon#about to read 6, iclass 28, count 2 2006.257.06:04:54.46#ibcon#read 6, iclass 28, count 2 2006.257.06:04:54.46#ibcon#end of sib2, iclass 28, count 2 2006.257.06:04:54.46#ibcon#*mode == 0, iclass 28, count 2 2006.257.06:04:54.46#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.06:04:54.46#ibcon#[27=AT05-04\r\n] 2006.257.06:04:54.46#ibcon#*before write, iclass 28, count 2 2006.257.06:04:54.46#ibcon#enter sib2, iclass 28, count 2 2006.257.06:04:54.46#ibcon#flushed, iclass 28, count 2 2006.257.06:04:54.46#ibcon#about to write, iclass 28, count 2 2006.257.06:04:54.46#ibcon#wrote, iclass 28, count 2 2006.257.06:04:54.46#ibcon#about to read 3, iclass 28, count 2 2006.257.06:04:54.49#ibcon#read 3, iclass 28, count 2 2006.257.06:04:54.49#ibcon#about to read 4, iclass 28, count 2 2006.257.06:04:54.49#ibcon#read 4, iclass 28, count 2 2006.257.06:04:54.49#ibcon#about to read 5, iclass 28, count 2 2006.257.06:04:54.49#ibcon#read 5, iclass 28, count 2 2006.257.06:04:54.49#ibcon#about to read 6, iclass 28, count 2 2006.257.06:04:54.49#ibcon#read 6, iclass 28, count 2 2006.257.06:04:54.49#ibcon#end of sib2, iclass 28, count 2 2006.257.06:04:54.49#ibcon#*after write, iclass 28, count 2 2006.257.06:04:54.49#ibcon#*before return 0, iclass 28, count 2 2006.257.06:04:54.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:54.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:04:54.49#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.06:04:54.49#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:54.49#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:54.61#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:54.61#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:54.61#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:04:54.61#ibcon#first serial, iclass 28, count 0 2006.257.06:04:54.61#ibcon#enter sib2, iclass 28, count 0 2006.257.06:04:54.61#ibcon#flushed, iclass 28, count 0 2006.257.06:04:54.61#ibcon#about to write, iclass 28, count 0 2006.257.06:04:54.61#ibcon#wrote, iclass 28, count 0 2006.257.06:04:54.61#ibcon#about to read 3, iclass 28, count 0 2006.257.06:04:54.63#ibcon#read 3, iclass 28, count 0 2006.257.06:04:54.63#ibcon#about to read 4, iclass 28, count 0 2006.257.06:04:54.63#ibcon#read 4, iclass 28, count 0 2006.257.06:04:54.63#ibcon#about to read 5, iclass 28, count 0 2006.257.06:04:54.63#ibcon#read 5, iclass 28, count 0 2006.257.06:04:54.63#ibcon#about to read 6, iclass 28, count 0 2006.257.06:04:54.63#ibcon#read 6, iclass 28, count 0 2006.257.06:04:54.63#ibcon#end of sib2, iclass 28, count 0 2006.257.06:04:54.63#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:04:54.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:04:54.63#ibcon#[27=USB\r\n] 2006.257.06:04:54.63#ibcon#*before write, iclass 28, count 0 2006.257.06:04:54.63#ibcon#enter sib2, iclass 28, count 0 2006.257.06:04:54.63#ibcon#flushed, iclass 28, count 0 2006.257.06:04:54.63#ibcon#about to write, iclass 28, count 0 2006.257.06:04:54.63#ibcon#wrote, iclass 28, count 0 2006.257.06:04:54.63#ibcon#about to read 3, iclass 28, count 0 2006.257.06:04:54.66#ibcon#read 3, iclass 28, count 0 2006.257.06:04:54.66#ibcon#about to read 4, iclass 28, count 0 2006.257.06:04:54.66#ibcon#read 4, iclass 28, count 0 2006.257.06:04:54.66#ibcon#about to read 5, iclass 28, count 0 2006.257.06:04:54.66#ibcon#read 5, iclass 28, count 0 2006.257.06:04:54.66#ibcon#about to read 6, iclass 28, count 0 2006.257.06:04:54.66#ibcon#read 6, iclass 28, count 0 2006.257.06:04:54.66#ibcon#end of sib2, iclass 28, count 0 2006.257.06:04:54.66#ibcon#*after write, iclass 28, count 0 2006.257.06:04:54.66#ibcon#*before return 0, iclass 28, count 0 2006.257.06:04:54.66#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:54.66#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:04:54.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:04:54.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:04:54.66$vck44/vblo=6,719.99 2006.257.06:04:54.66#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.06:04:54.66#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.06:04:54.66#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:54.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:54.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:54.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:54.66#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:04:54.66#ibcon#first serial, iclass 30, count 0 2006.257.06:04:54.66#ibcon#enter sib2, iclass 30, count 0 2006.257.06:04:54.67#ibcon#flushed, iclass 30, count 0 2006.257.06:04:54.67#ibcon#about to write, iclass 30, count 0 2006.257.06:04:54.67#ibcon#wrote, iclass 30, count 0 2006.257.06:04:54.67#ibcon#about to read 3, iclass 30, count 0 2006.257.06:04:54.68#ibcon#read 3, iclass 30, count 0 2006.257.06:04:54.68#ibcon#about to read 4, iclass 30, count 0 2006.257.06:04:54.68#ibcon#read 4, iclass 30, count 0 2006.257.06:04:54.68#ibcon#about to read 5, iclass 30, count 0 2006.257.06:04:54.68#ibcon#read 5, iclass 30, count 0 2006.257.06:04:54.68#ibcon#about to read 6, iclass 30, count 0 2006.257.06:04:54.68#ibcon#read 6, iclass 30, count 0 2006.257.06:04:54.68#ibcon#end of sib2, iclass 30, count 0 2006.257.06:04:54.68#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:04:54.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:04:54.68#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:04:54.68#ibcon#*before write, iclass 30, count 0 2006.257.06:04:54.68#ibcon#enter sib2, iclass 30, count 0 2006.257.06:04:54.68#ibcon#flushed, iclass 30, count 0 2006.257.06:04:54.68#ibcon#about to write, iclass 30, count 0 2006.257.06:04:54.68#ibcon#wrote, iclass 30, count 0 2006.257.06:04:54.68#ibcon#about to read 3, iclass 30, count 0 2006.257.06:04:54.72#ibcon#read 3, iclass 30, count 0 2006.257.06:04:54.72#ibcon#about to read 4, iclass 30, count 0 2006.257.06:04:54.72#ibcon#read 4, iclass 30, count 0 2006.257.06:04:54.72#ibcon#about to read 5, iclass 30, count 0 2006.257.06:04:54.72#ibcon#read 5, iclass 30, count 0 2006.257.06:04:54.72#ibcon#about to read 6, iclass 30, count 0 2006.257.06:04:54.72#ibcon#read 6, iclass 30, count 0 2006.257.06:04:54.72#ibcon#end of sib2, iclass 30, count 0 2006.257.06:04:54.72#ibcon#*after write, iclass 30, count 0 2006.257.06:04:54.72#ibcon#*before return 0, iclass 30, count 0 2006.257.06:04:54.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:54.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:04:54.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:04:54.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:04:54.72$vck44/vb=6,4 2006.257.06:04:54.72#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.06:04:54.72#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.06:04:54.72#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:54.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:54.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:54.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:54.78#ibcon#enter wrdev, iclass 32, count 2 2006.257.06:04:54.78#ibcon#first serial, iclass 32, count 2 2006.257.06:04:54.78#ibcon#enter sib2, iclass 32, count 2 2006.257.06:04:54.78#ibcon#flushed, iclass 32, count 2 2006.257.06:04:54.78#ibcon#about to write, iclass 32, count 2 2006.257.06:04:54.78#ibcon#wrote, iclass 32, count 2 2006.257.06:04:54.78#ibcon#about to read 3, iclass 32, count 2 2006.257.06:04:54.80#ibcon#read 3, iclass 32, count 2 2006.257.06:04:54.80#ibcon#about to read 4, iclass 32, count 2 2006.257.06:04:54.80#ibcon#read 4, iclass 32, count 2 2006.257.06:04:54.80#ibcon#about to read 5, iclass 32, count 2 2006.257.06:04:54.80#ibcon#read 5, iclass 32, count 2 2006.257.06:04:54.80#ibcon#about to read 6, iclass 32, count 2 2006.257.06:04:54.80#ibcon#read 6, iclass 32, count 2 2006.257.06:04:54.80#ibcon#end of sib2, iclass 32, count 2 2006.257.06:04:54.80#ibcon#*mode == 0, iclass 32, count 2 2006.257.06:04:54.80#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.06:04:54.80#ibcon#[27=AT06-04\r\n] 2006.257.06:04:54.80#ibcon#*before write, iclass 32, count 2 2006.257.06:04:54.80#ibcon#enter sib2, iclass 32, count 2 2006.257.06:04:54.80#ibcon#flushed, iclass 32, count 2 2006.257.06:04:54.80#ibcon#about to write, iclass 32, count 2 2006.257.06:04:54.80#ibcon#wrote, iclass 32, count 2 2006.257.06:04:54.80#ibcon#about to read 3, iclass 32, count 2 2006.257.06:04:54.83#ibcon#read 3, iclass 32, count 2 2006.257.06:04:54.83#ibcon#about to read 4, iclass 32, count 2 2006.257.06:04:54.83#ibcon#read 4, iclass 32, count 2 2006.257.06:04:54.83#ibcon#about to read 5, iclass 32, count 2 2006.257.06:04:54.83#ibcon#read 5, iclass 32, count 2 2006.257.06:04:54.83#ibcon#about to read 6, iclass 32, count 2 2006.257.06:04:54.83#ibcon#read 6, iclass 32, count 2 2006.257.06:04:54.83#ibcon#end of sib2, iclass 32, count 2 2006.257.06:04:54.83#ibcon#*after write, iclass 32, count 2 2006.257.06:04:54.83#ibcon#*before return 0, iclass 32, count 2 2006.257.06:04:54.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:54.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:04:54.83#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.06:04:54.83#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:54.83#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:54.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:54.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:54.95#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:04:54.95#ibcon#first serial, iclass 32, count 0 2006.257.06:04:54.95#ibcon#enter sib2, iclass 32, count 0 2006.257.06:04:54.95#ibcon#flushed, iclass 32, count 0 2006.257.06:04:54.95#ibcon#about to write, iclass 32, count 0 2006.257.06:04:54.95#ibcon#wrote, iclass 32, count 0 2006.257.06:04:54.95#ibcon#about to read 3, iclass 32, count 0 2006.257.06:04:54.97#ibcon#read 3, iclass 32, count 0 2006.257.06:04:54.97#ibcon#about to read 4, iclass 32, count 0 2006.257.06:04:54.97#ibcon#read 4, iclass 32, count 0 2006.257.06:04:54.97#ibcon#about to read 5, iclass 32, count 0 2006.257.06:04:54.97#ibcon#read 5, iclass 32, count 0 2006.257.06:04:54.97#ibcon#about to read 6, iclass 32, count 0 2006.257.06:04:54.97#ibcon#read 6, iclass 32, count 0 2006.257.06:04:54.97#ibcon#end of sib2, iclass 32, count 0 2006.257.06:04:54.97#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:04:54.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:04:54.97#ibcon#[27=USB\r\n] 2006.257.06:04:54.97#ibcon#*before write, iclass 32, count 0 2006.257.06:04:54.97#ibcon#enter sib2, iclass 32, count 0 2006.257.06:04:54.97#ibcon#flushed, iclass 32, count 0 2006.257.06:04:54.97#ibcon#about to write, iclass 32, count 0 2006.257.06:04:54.97#ibcon#wrote, iclass 32, count 0 2006.257.06:04:54.97#ibcon#about to read 3, iclass 32, count 0 2006.257.06:04:55.00#ibcon#read 3, iclass 32, count 0 2006.257.06:04:55.00#ibcon#about to read 4, iclass 32, count 0 2006.257.06:04:55.00#ibcon#read 4, iclass 32, count 0 2006.257.06:04:55.00#ibcon#about to read 5, iclass 32, count 0 2006.257.06:04:55.00#ibcon#read 5, iclass 32, count 0 2006.257.06:04:55.00#ibcon#about to read 6, iclass 32, count 0 2006.257.06:04:55.00#ibcon#read 6, iclass 32, count 0 2006.257.06:04:55.00#ibcon#end of sib2, iclass 32, count 0 2006.257.06:04:55.00#ibcon#*after write, iclass 32, count 0 2006.257.06:04:55.00#ibcon#*before return 0, iclass 32, count 0 2006.257.06:04:55.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:55.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:04:55.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:04:55.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:04:55.00$vck44/vblo=7,734.99 2006.257.06:04:55.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.06:04:55.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.06:04:55.00#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:55.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:55.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:55.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:55.00#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:04:55.01#ibcon#first serial, iclass 34, count 0 2006.257.06:04:55.01#ibcon#enter sib2, iclass 34, count 0 2006.257.06:04:55.01#ibcon#flushed, iclass 34, count 0 2006.257.06:04:55.01#ibcon#about to write, iclass 34, count 0 2006.257.06:04:55.01#ibcon#wrote, iclass 34, count 0 2006.257.06:04:55.01#ibcon#about to read 3, iclass 34, count 0 2006.257.06:04:55.02#ibcon#read 3, iclass 34, count 0 2006.257.06:04:55.02#ibcon#about to read 4, iclass 34, count 0 2006.257.06:04:55.02#ibcon#read 4, iclass 34, count 0 2006.257.06:04:55.02#ibcon#about to read 5, iclass 34, count 0 2006.257.06:04:55.02#ibcon#read 5, iclass 34, count 0 2006.257.06:04:55.02#ibcon#about to read 6, iclass 34, count 0 2006.257.06:04:55.02#ibcon#read 6, iclass 34, count 0 2006.257.06:04:55.02#ibcon#end of sib2, iclass 34, count 0 2006.257.06:04:55.02#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:04:55.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:04:55.02#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:04:55.02#ibcon#*before write, iclass 34, count 0 2006.257.06:04:55.02#ibcon#enter sib2, iclass 34, count 0 2006.257.06:04:55.02#ibcon#flushed, iclass 34, count 0 2006.257.06:04:55.02#ibcon#about to write, iclass 34, count 0 2006.257.06:04:55.02#ibcon#wrote, iclass 34, count 0 2006.257.06:04:55.02#ibcon#about to read 3, iclass 34, count 0 2006.257.06:04:55.06#ibcon#read 3, iclass 34, count 0 2006.257.06:04:55.06#ibcon#about to read 4, iclass 34, count 0 2006.257.06:04:55.06#ibcon#read 4, iclass 34, count 0 2006.257.06:04:55.06#ibcon#about to read 5, iclass 34, count 0 2006.257.06:04:55.06#ibcon#read 5, iclass 34, count 0 2006.257.06:04:55.06#ibcon#about to read 6, iclass 34, count 0 2006.257.06:04:55.06#ibcon#read 6, iclass 34, count 0 2006.257.06:04:55.06#ibcon#end of sib2, iclass 34, count 0 2006.257.06:04:55.06#ibcon#*after write, iclass 34, count 0 2006.257.06:04:55.06#ibcon#*before return 0, iclass 34, count 0 2006.257.06:04:55.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:55.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:04:55.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:04:55.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:04:55.06$vck44/vb=7,4 2006.257.06:04:55.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.06:04:55.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.06:04:55.06#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:55.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:55.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:55.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:55.12#ibcon#enter wrdev, iclass 36, count 2 2006.257.06:04:55.12#ibcon#first serial, iclass 36, count 2 2006.257.06:04:55.12#ibcon#enter sib2, iclass 36, count 2 2006.257.06:04:55.12#ibcon#flushed, iclass 36, count 2 2006.257.06:04:55.12#ibcon#about to write, iclass 36, count 2 2006.257.06:04:55.12#ibcon#wrote, iclass 36, count 2 2006.257.06:04:55.12#ibcon#about to read 3, iclass 36, count 2 2006.257.06:04:55.14#ibcon#read 3, iclass 36, count 2 2006.257.06:04:55.14#ibcon#about to read 4, iclass 36, count 2 2006.257.06:04:55.14#ibcon#read 4, iclass 36, count 2 2006.257.06:04:55.14#ibcon#about to read 5, iclass 36, count 2 2006.257.06:04:55.14#ibcon#read 5, iclass 36, count 2 2006.257.06:04:55.14#ibcon#about to read 6, iclass 36, count 2 2006.257.06:04:55.14#ibcon#read 6, iclass 36, count 2 2006.257.06:04:55.14#ibcon#end of sib2, iclass 36, count 2 2006.257.06:04:55.14#ibcon#*mode == 0, iclass 36, count 2 2006.257.06:04:55.14#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.06:04:55.14#ibcon#[27=AT07-04\r\n] 2006.257.06:04:55.14#ibcon#*before write, iclass 36, count 2 2006.257.06:04:55.14#ibcon#enter sib2, iclass 36, count 2 2006.257.06:04:55.14#ibcon#flushed, iclass 36, count 2 2006.257.06:04:55.14#ibcon#about to write, iclass 36, count 2 2006.257.06:04:55.14#ibcon#wrote, iclass 36, count 2 2006.257.06:04:55.14#ibcon#about to read 3, iclass 36, count 2 2006.257.06:04:55.17#ibcon#read 3, iclass 36, count 2 2006.257.06:04:55.17#ibcon#about to read 4, iclass 36, count 2 2006.257.06:04:55.17#ibcon#read 4, iclass 36, count 2 2006.257.06:04:55.17#ibcon#about to read 5, iclass 36, count 2 2006.257.06:04:55.17#ibcon#read 5, iclass 36, count 2 2006.257.06:04:55.17#ibcon#about to read 6, iclass 36, count 2 2006.257.06:04:55.17#ibcon#read 6, iclass 36, count 2 2006.257.06:04:55.17#ibcon#end of sib2, iclass 36, count 2 2006.257.06:04:55.17#ibcon#*after write, iclass 36, count 2 2006.257.06:04:55.17#ibcon#*before return 0, iclass 36, count 2 2006.257.06:04:55.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:55.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:04:55.17#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.06:04:55.17#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:55.17#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:55.29#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:55.29#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:55.29#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:04:55.29#ibcon#first serial, iclass 36, count 0 2006.257.06:04:55.29#ibcon#enter sib2, iclass 36, count 0 2006.257.06:04:55.29#ibcon#flushed, iclass 36, count 0 2006.257.06:04:55.29#ibcon#about to write, iclass 36, count 0 2006.257.06:04:55.29#ibcon#wrote, iclass 36, count 0 2006.257.06:04:55.29#ibcon#about to read 3, iclass 36, count 0 2006.257.06:04:55.31#ibcon#read 3, iclass 36, count 0 2006.257.06:04:55.31#ibcon#about to read 4, iclass 36, count 0 2006.257.06:04:55.31#ibcon#read 4, iclass 36, count 0 2006.257.06:04:55.31#ibcon#about to read 5, iclass 36, count 0 2006.257.06:04:55.31#ibcon#read 5, iclass 36, count 0 2006.257.06:04:55.31#ibcon#about to read 6, iclass 36, count 0 2006.257.06:04:55.31#ibcon#read 6, iclass 36, count 0 2006.257.06:04:55.31#ibcon#end of sib2, iclass 36, count 0 2006.257.06:04:55.31#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:04:55.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:04:55.31#ibcon#[27=USB\r\n] 2006.257.06:04:55.31#ibcon#*before write, iclass 36, count 0 2006.257.06:04:55.31#ibcon#enter sib2, iclass 36, count 0 2006.257.06:04:55.31#ibcon#flushed, iclass 36, count 0 2006.257.06:04:55.31#ibcon#about to write, iclass 36, count 0 2006.257.06:04:55.31#ibcon#wrote, iclass 36, count 0 2006.257.06:04:55.31#ibcon#about to read 3, iclass 36, count 0 2006.257.06:04:55.34#ibcon#read 3, iclass 36, count 0 2006.257.06:04:55.34#ibcon#about to read 4, iclass 36, count 0 2006.257.06:04:55.34#ibcon#read 4, iclass 36, count 0 2006.257.06:04:55.34#ibcon#about to read 5, iclass 36, count 0 2006.257.06:04:55.34#ibcon#read 5, iclass 36, count 0 2006.257.06:04:55.34#ibcon#about to read 6, iclass 36, count 0 2006.257.06:04:55.34#ibcon#read 6, iclass 36, count 0 2006.257.06:04:55.34#ibcon#end of sib2, iclass 36, count 0 2006.257.06:04:55.34#ibcon#*after write, iclass 36, count 0 2006.257.06:04:55.34#ibcon#*before return 0, iclass 36, count 0 2006.257.06:04:55.34#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:55.34#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:04:55.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:04:55.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:04:55.34$vck44/vblo=8,744.99 2006.257.06:04:55.34#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.06:04:55.34#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.06:04:55.34#ibcon#ireg 17 cls_cnt 0 2006.257.06:04:55.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:55.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:55.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:55.34#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:04:55.34#ibcon#first serial, iclass 38, count 0 2006.257.06:04:55.34#ibcon#enter sib2, iclass 38, count 0 2006.257.06:04:55.34#ibcon#flushed, iclass 38, count 0 2006.257.06:04:55.35#ibcon#about to write, iclass 38, count 0 2006.257.06:04:55.35#ibcon#wrote, iclass 38, count 0 2006.257.06:04:55.35#ibcon#about to read 3, iclass 38, count 0 2006.257.06:04:55.36#ibcon#read 3, iclass 38, count 0 2006.257.06:04:55.36#ibcon#about to read 4, iclass 38, count 0 2006.257.06:04:55.36#ibcon#read 4, iclass 38, count 0 2006.257.06:04:55.36#ibcon#about to read 5, iclass 38, count 0 2006.257.06:04:55.36#ibcon#read 5, iclass 38, count 0 2006.257.06:04:55.36#ibcon#about to read 6, iclass 38, count 0 2006.257.06:04:55.36#ibcon#read 6, iclass 38, count 0 2006.257.06:04:55.36#ibcon#end of sib2, iclass 38, count 0 2006.257.06:04:55.36#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:04:55.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:04:55.36#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:04:55.36#ibcon#*before write, iclass 38, count 0 2006.257.06:04:55.36#ibcon#enter sib2, iclass 38, count 0 2006.257.06:04:55.36#ibcon#flushed, iclass 38, count 0 2006.257.06:04:55.36#ibcon#about to write, iclass 38, count 0 2006.257.06:04:55.36#ibcon#wrote, iclass 38, count 0 2006.257.06:04:55.36#ibcon#about to read 3, iclass 38, count 0 2006.257.06:04:55.40#ibcon#read 3, iclass 38, count 0 2006.257.06:04:55.40#ibcon#about to read 4, iclass 38, count 0 2006.257.06:04:55.40#ibcon#read 4, iclass 38, count 0 2006.257.06:04:55.40#ibcon#about to read 5, iclass 38, count 0 2006.257.06:04:55.40#ibcon#read 5, iclass 38, count 0 2006.257.06:04:55.40#ibcon#about to read 6, iclass 38, count 0 2006.257.06:04:55.40#ibcon#read 6, iclass 38, count 0 2006.257.06:04:55.40#ibcon#end of sib2, iclass 38, count 0 2006.257.06:04:55.40#ibcon#*after write, iclass 38, count 0 2006.257.06:04:55.40#ibcon#*before return 0, iclass 38, count 0 2006.257.06:04:55.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:55.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:04:55.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:04:55.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:04:55.40$vck44/vb=8,4 2006.257.06:04:55.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.06:04:55.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.06:04:55.40#ibcon#ireg 11 cls_cnt 2 2006.257.06:04:55.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:55.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:55.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:55.46#ibcon#enter wrdev, iclass 40, count 2 2006.257.06:04:55.46#ibcon#first serial, iclass 40, count 2 2006.257.06:04:55.46#ibcon#enter sib2, iclass 40, count 2 2006.257.06:04:55.46#ibcon#flushed, iclass 40, count 2 2006.257.06:04:55.46#ibcon#about to write, iclass 40, count 2 2006.257.06:04:55.46#ibcon#wrote, iclass 40, count 2 2006.257.06:04:55.46#ibcon#about to read 3, iclass 40, count 2 2006.257.06:04:55.48#ibcon#read 3, iclass 40, count 2 2006.257.06:04:55.48#ibcon#about to read 4, iclass 40, count 2 2006.257.06:04:55.48#ibcon#read 4, iclass 40, count 2 2006.257.06:04:55.48#ibcon#about to read 5, iclass 40, count 2 2006.257.06:04:55.48#ibcon#read 5, iclass 40, count 2 2006.257.06:04:55.48#ibcon#about to read 6, iclass 40, count 2 2006.257.06:04:55.48#ibcon#read 6, iclass 40, count 2 2006.257.06:04:55.48#ibcon#end of sib2, iclass 40, count 2 2006.257.06:04:55.48#ibcon#*mode == 0, iclass 40, count 2 2006.257.06:04:55.48#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.06:04:55.48#ibcon#[27=AT08-04\r\n] 2006.257.06:04:55.48#ibcon#*before write, iclass 40, count 2 2006.257.06:04:55.48#ibcon#enter sib2, iclass 40, count 2 2006.257.06:04:55.48#ibcon#flushed, iclass 40, count 2 2006.257.06:04:55.48#ibcon#about to write, iclass 40, count 2 2006.257.06:04:55.48#ibcon#wrote, iclass 40, count 2 2006.257.06:04:55.48#ibcon#about to read 3, iclass 40, count 2 2006.257.06:04:55.51#ibcon#read 3, iclass 40, count 2 2006.257.06:04:55.51#ibcon#about to read 4, iclass 40, count 2 2006.257.06:04:55.51#ibcon#read 4, iclass 40, count 2 2006.257.06:04:55.51#ibcon#about to read 5, iclass 40, count 2 2006.257.06:04:55.51#ibcon#read 5, iclass 40, count 2 2006.257.06:04:55.51#ibcon#about to read 6, iclass 40, count 2 2006.257.06:04:55.51#ibcon#read 6, iclass 40, count 2 2006.257.06:04:55.51#ibcon#end of sib2, iclass 40, count 2 2006.257.06:04:55.51#ibcon#*after write, iclass 40, count 2 2006.257.06:04:55.51#ibcon#*before return 0, iclass 40, count 2 2006.257.06:04:55.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:55.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:04:55.51#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.06:04:55.51#ibcon#ireg 7 cls_cnt 0 2006.257.06:04:55.51#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:55.63#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:55.63#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:55.63#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:04:55.63#ibcon#first serial, iclass 40, count 0 2006.257.06:04:55.63#ibcon#enter sib2, iclass 40, count 0 2006.257.06:04:55.63#ibcon#flushed, iclass 40, count 0 2006.257.06:04:55.63#ibcon#about to write, iclass 40, count 0 2006.257.06:04:55.63#ibcon#wrote, iclass 40, count 0 2006.257.06:04:55.63#ibcon#about to read 3, iclass 40, count 0 2006.257.06:04:55.65#ibcon#read 3, iclass 40, count 0 2006.257.06:04:55.65#ibcon#about to read 4, iclass 40, count 0 2006.257.06:04:55.65#ibcon#read 4, iclass 40, count 0 2006.257.06:04:55.65#ibcon#about to read 5, iclass 40, count 0 2006.257.06:04:55.65#ibcon#read 5, iclass 40, count 0 2006.257.06:04:55.65#ibcon#about to read 6, iclass 40, count 0 2006.257.06:04:55.65#ibcon#read 6, iclass 40, count 0 2006.257.06:04:55.65#ibcon#end of sib2, iclass 40, count 0 2006.257.06:04:55.65#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:04:55.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:04:55.65#ibcon#[27=USB\r\n] 2006.257.06:04:55.65#ibcon#*before write, iclass 40, count 0 2006.257.06:04:55.65#ibcon#enter sib2, iclass 40, count 0 2006.257.06:04:55.65#ibcon#flushed, iclass 40, count 0 2006.257.06:04:55.65#ibcon#about to write, iclass 40, count 0 2006.257.06:04:55.65#ibcon#wrote, iclass 40, count 0 2006.257.06:04:55.65#ibcon#about to read 3, iclass 40, count 0 2006.257.06:04:55.68#ibcon#read 3, iclass 40, count 0 2006.257.06:04:55.68#ibcon#about to read 4, iclass 40, count 0 2006.257.06:04:55.68#ibcon#read 4, iclass 40, count 0 2006.257.06:04:55.68#ibcon#about to read 5, iclass 40, count 0 2006.257.06:04:55.68#ibcon#read 5, iclass 40, count 0 2006.257.06:04:55.68#ibcon#about to read 6, iclass 40, count 0 2006.257.06:04:55.68#ibcon#read 6, iclass 40, count 0 2006.257.06:04:55.68#ibcon#end of sib2, iclass 40, count 0 2006.257.06:04:55.68#ibcon#*after write, iclass 40, count 0 2006.257.06:04:55.68#ibcon#*before return 0, iclass 40, count 0 2006.257.06:04:55.68#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:55.68#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:04:55.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:04:55.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:04:55.68$vck44/vabw=wide 2006.257.06:04:55.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.06:04:55.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.06:04:55.68#ibcon#ireg 8 cls_cnt 0 2006.257.06:04:55.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:55.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:55.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:55.68#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:04:55.68#ibcon#first serial, iclass 4, count 0 2006.257.06:04:55.68#ibcon#enter sib2, iclass 4, count 0 2006.257.06:04:55.69#ibcon#flushed, iclass 4, count 0 2006.257.06:04:55.69#ibcon#about to write, iclass 4, count 0 2006.257.06:04:55.69#ibcon#wrote, iclass 4, count 0 2006.257.06:04:55.69#ibcon#about to read 3, iclass 4, count 0 2006.257.06:04:55.70#ibcon#read 3, iclass 4, count 0 2006.257.06:04:55.70#ibcon#about to read 4, iclass 4, count 0 2006.257.06:04:55.70#ibcon#read 4, iclass 4, count 0 2006.257.06:04:55.70#ibcon#about to read 5, iclass 4, count 0 2006.257.06:04:55.70#ibcon#read 5, iclass 4, count 0 2006.257.06:04:55.70#ibcon#about to read 6, iclass 4, count 0 2006.257.06:04:55.70#ibcon#read 6, iclass 4, count 0 2006.257.06:04:55.70#ibcon#end of sib2, iclass 4, count 0 2006.257.06:04:55.70#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:04:55.70#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:04:55.70#ibcon#[25=BW32\r\n] 2006.257.06:04:55.70#ibcon#*before write, iclass 4, count 0 2006.257.06:04:55.70#ibcon#enter sib2, iclass 4, count 0 2006.257.06:04:55.70#ibcon#flushed, iclass 4, count 0 2006.257.06:04:55.70#ibcon#about to write, iclass 4, count 0 2006.257.06:04:55.70#ibcon#wrote, iclass 4, count 0 2006.257.06:04:55.70#ibcon#about to read 3, iclass 4, count 0 2006.257.06:04:55.73#ibcon#read 3, iclass 4, count 0 2006.257.06:04:55.73#ibcon#about to read 4, iclass 4, count 0 2006.257.06:04:55.73#ibcon#read 4, iclass 4, count 0 2006.257.06:04:55.73#ibcon#about to read 5, iclass 4, count 0 2006.257.06:04:55.73#ibcon#read 5, iclass 4, count 0 2006.257.06:04:55.73#ibcon#about to read 6, iclass 4, count 0 2006.257.06:04:55.73#ibcon#read 6, iclass 4, count 0 2006.257.06:04:55.73#ibcon#end of sib2, iclass 4, count 0 2006.257.06:04:55.73#ibcon#*after write, iclass 4, count 0 2006.257.06:04:55.73#ibcon#*before return 0, iclass 4, count 0 2006.257.06:04:55.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:55.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:04:55.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:04:55.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:04:55.73$vck44/vbbw=wide 2006.257.06:04:55.73#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.06:04:55.73#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.06:04:55.73#ibcon#ireg 8 cls_cnt 0 2006.257.06:04:55.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:04:55.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:04:55.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:04:55.80#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:04:55.80#ibcon#first serial, iclass 6, count 0 2006.257.06:04:55.80#ibcon#enter sib2, iclass 6, count 0 2006.257.06:04:55.80#ibcon#flushed, iclass 6, count 0 2006.257.06:04:55.80#ibcon#about to write, iclass 6, count 0 2006.257.06:04:55.80#ibcon#wrote, iclass 6, count 0 2006.257.06:04:55.80#ibcon#about to read 3, iclass 6, count 0 2006.257.06:04:55.82#ibcon#read 3, iclass 6, count 0 2006.257.06:04:55.82#ibcon#about to read 4, iclass 6, count 0 2006.257.06:04:55.82#ibcon#read 4, iclass 6, count 0 2006.257.06:04:55.82#ibcon#about to read 5, iclass 6, count 0 2006.257.06:04:55.82#ibcon#read 5, iclass 6, count 0 2006.257.06:04:55.82#ibcon#about to read 6, iclass 6, count 0 2006.257.06:04:55.82#ibcon#read 6, iclass 6, count 0 2006.257.06:04:55.82#ibcon#end of sib2, iclass 6, count 0 2006.257.06:04:55.82#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:04:55.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:04:55.82#ibcon#[27=BW32\r\n] 2006.257.06:04:55.82#ibcon#*before write, iclass 6, count 0 2006.257.06:04:55.82#ibcon#enter sib2, iclass 6, count 0 2006.257.06:04:55.82#ibcon#flushed, iclass 6, count 0 2006.257.06:04:55.82#ibcon#about to write, iclass 6, count 0 2006.257.06:04:55.82#ibcon#wrote, iclass 6, count 0 2006.257.06:04:55.82#ibcon#about to read 3, iclass 6, count 0 2006.257.06:04:55.85#ibcon#read 3, iclass 6, count 0 2006.257.06:04:55.85#ibcon#about to read 4, iclass 6, count 0 2006.257.06:04:55.85#ibcon#read 4, iclass 6, count 0 2006.257.06:04:55.85#ibcon#about to read 5, iclass 6, count 0 2006.257.06:04:55.85#ibcon#read 5, iclass 6, count 0 2006.257.06:04:55.85#ibcon#about to read 6, iclass 6, count 0 2006.257.06:04:55.85#ibcon#read 6, iclass 6, count 0 2006.257.06:04:55.85#ibcon#end of sib2, iclass 6, count 0 2006.257.06:04:55.85#ibcon#*after write, iclass 6, count 0 2006.257.06:04:55.85#ibcon#*before return 0, iclass 6, count 0 2006.257.06:04:55.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:04:55.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:04:55.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:04:55.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:04:55.85$setupk4/ifdk4 2006.257.06:04:55.85$ifdk4/lo= 2006.257.06:04:55.86$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:04:55.86$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:04:55.86$ifdk4/patch= 2006.257.06:04:55.86$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:04:55.86$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:04:55.86$setupk4/!*+20s 2006.257.06:04:56.66#abcon#<5=/16 1.1 4.7 20.19 891012.1\r\n> 2006.257.06:04:56.68#abcon#{5=INTERFACE CLEAR} 2006.257.06:04:56.74#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:05:06.83#abcon#<5=/16 1.1 4.7 20.19 891012.1\r\n> 2006.257.06:05:06.85#abcon#{5=INTERFACE CLEAR} 2006.257.06:05:06.91#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:05:10.39$setupk4/"tpicd 2006.257.06:05:10.39$setupk4/echo=off 2006.257.06:05:10.39$setupk4/xlog=off 2006.257.06:05:10.39:!2006.257.06:06:12 2006.257.06:05:16.14#trakl#Source acquired 2006.257.06:05:16.14#flagr#flagr/antenna,acquired 2006.257.06:06:12.00:preob 2006.257.06:06:12.14/onsource/TRACKING 2006.257.06:06:12.14:!2006.257.06:06:22 2006.257.06:06:22.00:"tape 2006.257.06:06:22.00:"st=record 2006.257.06:06:22.00:data_valid=on 2006.257.06:06:22.00:midob 2006.257.06:06:22.14/onsource/TRACKING 2006.257.06:06:22.15/wx/20.21,1012.1,89 2006.257.06:06:22.24/cable/+6.4794E-03 2006.257.06:06:23.33/va/01,08,usb,yes,31,34 2006.257.06:06:23.33/va/02,07,usb,yes,34,34 2006.257.06:06:23.33/va/03,08,usb,yes,30,32 2006.257.06:06:23.33/va/04,07,usb,yes,35,36 2006.257.06:06:23.33/va/05,04,usb,yes,31,32 2006.257.06:06:23.33/va/06,04,usb,yes,35,34 2006.257.06:06:23.33/va/07,04,usb,yes,36,36 2006.257.06:06:23.33/va/08,04,usb,yes,30,36 2006.257.06:06:23.56/valo/01,524.99,yes,locked 2006.257.06:06:23.56/valo/02,534.99,yes,locked 2006.257.06:06:23.56/valo/03,564.99,yes,locked 2006.257.06:06:23.56/valo/04,624.99,yes,locked 2006.257.06:06:23.56/valo/05,734.99,yes,locked 2006.257.06:06:23.56/valo/06,814.99,yes,locked 2006.257.06:06:23.56/valo/07,864.99,yes,locked 2006.257.06:06:23.56/valo/08,884.99,yes,locked 2006.257.06:06:24.65/vb/01,04,usb,yes,30,28 2006.257.06:06:24.65/vb/02,05,usb,yes,28,28 2006.257.06:06:24.65/vb/03,04,usb,yes,29,32 2006.257.06:06:24.65/vb/04,05,usb,yes,29,29 2006.257.06:06:24.65/vb/05,04,usb,yes,26,28 2006.257.06:06:24.65/vb/06,04,usb,yes,31,27 2006.257.06:06:24.65/vb/07,04,usb,yes,30,30 2006.257.06:06:24.65/vb/08,04,usb,yes,28,31 2006.257.06:06:24.88/vblo/01,629.99,yes,locked 2006.257.06:06:24.88/vblo/02,634.99,yes,locked 2006.257.06:06:24.88/vblo/03,649.99,yes,locked 2006.257.06:06:24.88/vblo/04,679.99,yes,locked 2006.257.06:06:24.88/vblo/05,709.99,yes,locked 2006.257.06:06:24.88/vblo/06,719.99,yes,locked 2006.257.06:06:24.88/vblo/07,734.99,yes,locked 2006.257.06:06:24.88/vblo/08,744.99,yes,locked 2006.257.06:06:25.03/vabw/8 2006.257.06:06:25.18/vbbw/8 2006.257.06:06:25.27/xfe/off,on,16.7 2006.257.06:06:25.65/ifatt/23,28,28,28 2006.257.06:06:26.07/fmout-gps/S +4.56E-07 2006.257.06:06:26.11:!2006.257.06:10:22 2006.257.06:10:22.01:data_valid=off 2006.257.06:10:22.02:"et 2006.257.06:10:22.02:!+3s 2006.257.06:10:25.04:"tape 2006.257.06:10:25.04:postob 2006.257.06:10:25.20/cable/+6.4797E-03 2006.257.06:10:25.21/wx/20.29,1012.1,89 2006.257.06:10:25.26/fmout-gps/S +4.54E-07 2006.257.06:10:25.27:scan_name=257-0611,jd0609,310 2006.257.06:10:25.27:source=2201+315,220314.98,314538.3,2000.0,cw 2006.257.06:10:26.14#flagr#flagr/antenna,new-source 2006.257.06:10:26.15:checkk5 2006.257.06:10:26.58/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:10:26.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:10:27.39/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:10:27.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:10:28.15/chk_obsdata//k5ts1/T2570606??a.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.06:10:28.56/chk_obsdata//k5ts2/T2570606??b.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.06:10:28.96/chk_obsdata//k5ts3/T2570606??c.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.06:10:29.37/chk_obsdata//k5ts4/T2570606??d.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.06:10:30.11/k5log//k5ts1_log_newline 2006.257.06:10:30.83/k5log//k5ts2_log_newline 2006.257.06:10:31.57/k5log//k5ts3_log_newline 2006.257.06:10:32.30/k5log//k5ts4_log_newline 2006.257.06:10:32.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:10:32.32:setupk4=1 2006.257.06:10:32.32$setupk4/echo=on 2006.257.06:10:32.32$setupk4/pcalon 2006.257.06:10:32.32$pcalon/"no phase cal control is implemented here 2006.257.06:10:32.32$setupk4/"tpicd=stop 2006.257.06:10:32.32$setupk4/"rec=synch_on 2006.257.06:10:32.32$setupk4/"rec_mode=128 2006.257.06:10:32.32$setupk4/!* 2006.257.06:10:32.32$setupk4/recpk4 2006.257.06:10:32.32$recpk4/recpatch= 2006.257.06:10:32.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:10:32.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:10:32.32$setupk4/vck44 2006.257.06:10:32.32$vck44/valo=1,524.99 2006.257.06:10:32.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.06:10:32.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.06:10:32.32#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:32.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:32.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:32.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:32.32#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:10:32.32#ibcon#first serial, iclass 37, count 0 2006.257.06:10:32.32#ibcon#enter sib2, iclass 37, count 0 2006.257.06:10:32.32#ibcon#flushed, iclass 37, count 0 2006.257.06:10:32.32#ibcon#about to write, iclass 37, count 0 2006.257.06:10:32.32#ibcon#wrote, iclass 37, count 0 2006.257.06:10:32.32#ibcon#about to read 3, iclass 37, count 0 2006.257.06:10:32.34#ibcon#read 3, iclass 37, count 0 2006.257.06:10:32.34#ibcon#about to read 4, iclass 37, count 0 2006.257.06:10:32.34#ibcon#read 4, iclass 37, count 0 2006.257.06:10:32.34#ibcon#about to read 5, iclass 37, count 0 2006.257.06:10:32.34#ibcon#read 5, iclass 37, count 0 2006.257.06:10:32.34#ibcon#about to read 6, iclass 37, count 0 2006.257.06:10:32.34#ibcon#read 6, iclass 37, count 0 2006.257.06:10:32.34#ibcon#end of sib2, iclass 37, count 0 2006.257.06:10:32.34#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:10:32.34#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:10:32.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:10:32.34#ibcon#*before write, iclass 37, count 0 2006.257.06:10:32.34#ibcon#enter sib2, iclass 37, count 0 2006.257.06:10:32.34#ibcon#flushed, iclass 37, count 0 2006.257.06:10:32.34#ibcon#about to write, iclass 37, count 0 2006.257.06:10:32.34#ibcon#wrote, iclass 37, count 0 2006.257.06:10:32.34#ibcon#about to read 3, iclass 37, count 0 2006.257.06:10:32.39#ibcon#read 3, iclass 37, count 0 2006.257.06:10:32.39#ibcon#about to read 4, iclass 37, count 0 2006.257.06:10:32.39#ibcon#read 4, iclass 37, count 0 2006.257.06:10:32.39#ibcon#about to read 5, iclass 37, count 0 2006.257.06:10:32.39#ibcon#read 5, iclass 37, count 0 2006.257.06:10:32.39#ibcon#about to read 6, iclass 37, count 0 2006.257.06:10:32.39#ibcon#read 6, iclass 37, count 0 2006.257.06:10:32.39#ibcon#end of sib2, iclass 37, count 0 2006.257.06:10:32.39#ibcon#*after write, iclass 37, count 0 2006.257.06:10:32.39#ibcon#*before return 0, iclass 37, count 0 2006.257.06:10:32.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:32.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:32.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:10:32.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:10:32.39$vck44/va=1,8 2006.257.06:10:32.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.06:10:32.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.06:10:32.39#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:32.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:32.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:32.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:32.39#ibcon#enter wrdev, iclass 39, count 2 2006.257.06:10:32.39#ibcon#first serial, iclass 39, count 2 2006.257.06:10:32.39#ibcon#enter sib2, iclass 39, count 2 2006.257.06:10:32.39#ibcon#flushed, iclass 39, count 2 2006.257.06:10:32.39#ibcon#about to write, iclass 39, count 2 2006.257.06:10:32.39#ibcon#wrote, iclass 39, count 2 2006.257.06:10:32.39#ibcon#about to read 3, iclass 39, count 2 2006.257.06:10:32.41#ibcon#read 3, iclass 39, count 2 2006.257.06:10:32.41#ibcon#about to read 4, iclass 39, count 2 2006.257.06:10:32.41#ibcon#read 4, iclass 39, count 2 2006.257.06:10:32.41#ibcon#about to read 5, iclass 39, count 2 2006.257.06:10:32.41#ibcon#read 5, iclass 39, count 2 2006.257.06:10:32.41#ibcon#about to read 6, iclass 39, count 2 2006.257.06:10:32.41#ibcon#read 6, iclass 39, count 2 2006.257.06:10:32.41#ibcon#end of sib2, iclass 39, count 2 2006.257.06:10:32.41#ibcon#*mode == 0, iclass 39, count 2 2006.257.06:10:32.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.06:10:32.41#ibcon#[25=AT01-08\r\n] 2006.257.06:10:32.41#ibcon#*before write, iclass 39, count 2 2006.257.06:10:32.41#ibcon#enter sib2, iclass 39, count 2 2006.257.06:10:32.41#ibcon#flushed, iclass 39, count 2 2006.257.06:10:32.41#ibcon#about to write, iclass 39, count 2 2006.257.06:10:32.41#ibcon#wrote, iclass 39, count 2 2006.257.06:10:32.41#ibcon#about to read 3, iclass 39, count 2 2006.257.06:10:32.44#ibcon#read 3, iclass 39, count 2 2006.257.06:10:32.44#ibcon#about to read 4, iclass 39, count 2 2006.257.06:10:32.44#ibcon#read 4, iclass 39, count 2 2006.257.06:10:32.44#ibcon#about to read 5, iclass 39, count 2 2006.257.06:10:32.44#ibcon#read 5, iclass 39, count 2 2006.257.06:10:32.44#ibcon#about to read 6, iclass 39, count 2 2006.257.06:10:32.44#ibcon#read 6, iclass 39, count 2 2006.257.06:10:32.44#ibcon#end of sib2, iclass 39, count 2 2006.257.06:10:32.44#ibcon#*after write, iclass 39, count 2 2006.257.06:10:32.44#ibcon#*before return 0, iclass 39, count 2 2006.257.06:10:32.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:32.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:32.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.06:10:32.44#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:32.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:32.46#abcon#<5=/15 1.1 2.5 20.30 891012.1\r\n> 2006.257.06:10:32.48#abcon#{5=INTERFACE CLEAR} 2006.257.06:10:32.54#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:10:32.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:32.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:32.56#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:10:32.56#ibcon#first serial, iclass 39, count 0 2006.257.06:10:32.56#ibcon#enter sib2, iclass 39, count 0 2006.257.06:10:32.56#ibcon#flushed, iclass 39, count 0 2006.257.06:10:32.56#ibcon#about to write, iclass 39, count 0 2006.257.06:10:32.56#ibcon#wrote, iclass 39, count 0 2006.257.06:10:32.56#ibcon#about to read 3, iclass 39, count 0 2006.257.06:10:32.58#ibcon#read 3, iclass 39, count 0 2006.257.06:10:32.58#ibcon#about to read 4, iclass 39, count 0 2006.257.06:10:32.58#ibcon#read 4, iclass 39, count 0 2006.257.06:10:32.58#ibcon#about to read 5, iclass 39, count 0 2006.257.06:10:32.58#ibcon#read 5, iclass 39, count 0 2006.257.06:10:32.58#ibcon#about to read 6, iclass 39, count 0 2006.257.06:10:32.58#ibcon#read 6, iclass 39, count 0 2006.257.06:10:32.58#ibcon#end of sib2, iclass 39, count 0 2006.257.06:10:32.58#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:10:32.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:10:32.58#ibcon#[25=USB\r\n] 2006.257.06:10:32.58#ibcon#*before write, iclass 39, count 0 2006.257.06:10:32.58#ibcon#enter sib2, iclass 39, count 0 2006.257.06:10:32.58#ibcon#flushed, iclass 39, count 0 2006.257.06:10:32.58#ibcon#about to write, iclass 39, count 0 2006.257.06:10:32.58#ibcon#wrote, iclass 39, count 0 2006.257.06:10:32.58#ibcon#about to read 3, iclass 39, count 0 2006.257.06:10:32.61#ibcon#read 3, iclass 39, count 0 2006.257.06:10:32.61#ibcon#about to read 4, iclass 39, count 0 2006.257.06:10:32.61#ibcon#read 4, iclass 39, count 0 2006.257.06:10:32.61#ibcon#about to read 5, iclass 39, count 0 2006.257.06:10:32.61#ibcon#read 5, iclass 39, count 0 2006.257.06:10:32.61#ibcon#about to read 6, iclass 39, count 0 2006.257.06:10:32.61#ibcon#read 6, iclass 39, count 0 2006.257.06:10:32.61#ibcon#end of sib2, iclass 39, count 0 2006.257.06:10:32.61#ibcon#*after write, iclass 39, count 0 2006.257.06:10:32.61#ibcon#*before return 0, iclass 39, count 0 2006.257.06:10:32.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:32.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:32.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:10:32.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:10:32.61$vck44/valo=2,534.99 2006.257.06:10:32.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.06:10:32.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.06:10:32.61#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:32.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:32.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:32.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:32.61#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:10:32.61#ibcon#first serial, iclass 7, count 0 2006.257.06:10:32.61#ibcon#enter sib2, iclass 7, count 0 2006.257.06:10:32.61#ibcon#flushed, iclass 7, count 0 2006.257.06:10:32.61#ibcon#about to write, iclass 7, count 0 2006.257.06:10:32.61#ibcon#wrote, iclass 7, count 0 2006.257.06:10:32.61#ibcon#about to read 3, iclass 7, count 0 2006.257.06:10:32.63#ibcon#read 3, iclass 7, count 0 2006.257.06:10:32.63#ibcon#about to read 4, iclass 7, count 0 2006.257.06:10:32.63#ibcon#read 4, iclass 7, count 0 2006.257.06:10:32.63#ibcon#about to read 5, iclass 7, count 0 2006.257.06:10:32.63#ibcon#read 5, iclass 7, count 0 2006.257.06:10:32.63#ibcon#about to read 6, iclass 7, count 0 2006.257.06:10:32.63#ibcon#read 6, iclass 7, count 0 2006.257.06:10:32.63#ibcon#end of sib2, iclass 7, count 0 2006.257.06:10:32.63#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:10:32.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:10:32.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:10:32.63#ibcon#*before write, iclass 7, count 0 2006.257.06:10:32.63#ibcon#enter sib2, iclass 7, count 0 2006.257.06:10:32.63#ibcon#flushed, iclass 7, count 0 2006.257.06:10:32.63#ibcon#about to write, iclass 7, count 0 2006.257.06:10:32.63#ibcon#wrote, iclass 7, count 0 2006.257.06:10:32.63#ibcon#about to read 3, iclass 7, count 0 2006.257.06:10:32.67#ibcon#read 3, iclass 7, count 0 2006.257.06:10:32.67#ibcon#about to read 4, iclass 7, count 0 2006.257.06:10:32.67#ibcon#read 4, iclass 7, count 0 2006.257.06:10:32.67#ibcon#about to read 5, iclass 7, count 0 2006.257.06:10:32.67#ibcon#read 5, iclass 7, count 0 2006.257.06:10:32.67#ibcon#about to read 6, iclass 7, count 0 2006.257.06:10:32.67#ibcon#read 6, iclass 7, count 0 2006.257.06:10:32.67#ibcon#end of sib2, iclass 7, count 0 2006.257.06:10:32.67#ibcon#*after write, iclass 7, count 0 2006.257.06:10:32.67#ibcon#*before return 0, iclass 7, count 0 2006.257.06:10:32.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:32.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:32.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:10:32.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:10:32.67$vck44/va=2,7 2006.257.06:10:32.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.06:10:32.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.06:10:32.67#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:32.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:32.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:32.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:32.73#ibcon#enter wrdev, iclass 11, count 2 2006.257.06:10:32.73#ibcon#first serial, iclass 11, count 2 2006.257.06:10:32.73#ibcon#enter sib2, iclass 11, count 2 2006.257.06:10:32.73#ibcon#flushed, iclass 11, count 2 2006.257.06:10:32.73#ibcon#about to write, iclass 11, count 2 2006.257.06:10:32.73#ibcon#wrote, iclass 11, count 2 2006.257.06:10:32.73#ibcon#about to read 3, iclass 11, count 2 2006.257.06:10:32.75#ibcon#read 3, iclass 11, count 2 2006.257.06:10:32.75#ibcon#about to read 4, iclass 11, count 2 2006.257.06:10:32.75#ibcon#read 4, iclass 11, count 2 2006.257.06:10:32.75#ibcon#about to read 5, iclass 11, count 2 2006.257.06:10:32.75#ibcon#read 5, iclass 11, count 2 2006.257.06:10:32.75#ibcon#about to read 6, iclass 11, count 2 2006.257.06:10:32.75#ibcon#read 6, iclass 11, count 2 2006.257.06:10:32.75#ibcon#end of sib2, iclass 11, count 2 2006.257.06:10:32.75#ibcon#*mode == 0, iclass 11, count 2 2006.257.06:10:32.75#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.06:10:32.75#ibcon#[25=AT02-07\r\n] 2006.257.06:10:32.75#ibcon#*before write, iclass 11, count 2 2006.257.06:10:32.75#ibcon#enter sib2, iclass 11, count 2 2006.257.06:10:32.75#ibcon#flushed, iclass 11, count 2 2006.257.06:10:32.75#ibcon#about to write, iclass 11, count 2 2006.257.06:10:32.75#ibcon#wrote, iclass 11, count 2 2006.257.06:10:32.75#ibcon#about to read 3, iclass 11, count 2 2006.257.06:10:32.78#ibcon#read 3, iclass 11, count 2 2006.257.06:10:32.78#ibcon#about to read 4, iclass 11, count 2 2006.257.06:10:32.78#ibcon#read 4, iclass 11, count 2 2006.257.06:10:32.78#ibcon#about to read 5, iclass 11, count 2 2006.257.06:10:32.78#ibcon#read 5, iclass 11, count 2 2006.257.06:10:32.78#ibcon#about to read 6, iclass 11, count 2 2006.257.06:10:32.78#ibcon#read 6, iclass 11, count 2 2006.257.06:10:32.78#ibcon#end of sib2, iclass 11, count 2 2006.257.06:10:32.78#ibcon#*after write, iclass 11, count 2 2006.257.06:10:32.78#ibcon#*before return 0, iclass 11, count 2 2006.257.06:10:32.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:32.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:32.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.06:10:32.78#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:32.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:32.90#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:32.90#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:32.90#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:10:32.90#ibcon#first serial, iclass 11, count 0 2006.257.06:10:32.90#ibcon#enter sib2, iclass 11, count 0 2006.257.06:10:32.90#ibcon#flushed, iclass 11, count 0 2006.257.06:10:32.90#ibcon#about to write, iclass 11, count 0 2006.257.06:10:32.90#ibcon#wrote, iclass 11, count 0 2006.257.06:10:32.90#ibcon#about to read 3, iclass 11, count 0 2006.257.06:10:32.92#ibcon#read 3, iclass 11, count 0 2006.257.06:10:32.92#ibcon#about to read 4, iclass 11, count 0 2006.257.06:10:32.92#ibcon#read 4, iclass 11, count 0 2006.257.06:10:32.92#ibcon#about to read 5, iclass 11, count 0 2006.257.06:10:32.92#ibcon#read 5, iclass 11, count 0 2006.257.06:10:32.92#ibcon#about to read 6, iclass 11, count 0 2006.257.06:10:32.92#ibcon#read 6, iclass 11, count 0 2006.257.06:10:32.92#ibcon#end of sib2, iclass 11, count 0 2006.257.06:10:32.92#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:10:32.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:10:32.92#ibcon#[25=USB\r\n] 2006.257.06:10:32.92#ibcon#*before write, iclass 11, count 0 2006.257.06:10:32.92#ibcon#enter sib2, iclass 11, count 0 2006.257.06:10:32.92#ibcon#flushed, iclass 11, count 0 2006.257.06:10:32.92#ibcon#about to write, iclass 11, count 0 2006.257.06:10:32.92#ibcon#wrote, iclass 11, count 0 2006.257.06:10:32.92#ibcon#about to read 3, iclass 11, count 0 2006.257.06:10:32.95#ibcon#read 3, iclass 11, count 0 2006.257.06:10:32.95#ibcon#about to read 4, iclass 11, count 0 2006.257.06:10:32.95#ibcon#read 4, iclass 11, count 0 2006.257.06:10:32.95#ibcon#about to read 5, iclass 11, count 0 2006.257.06:10:32.95#ibcon#read 5, iclass 11, count 0 2006.257.06:10:32.95#ibcon#about to read 6, iclass 11, count 0 2006.257.06:10:32.95#ibcon#read 6, iclass 11, count 0 2006.257.06:10:32.95#ibcon#end of sib2, iclass 11, count 0 2006.257.06:10:32.95#ibcon#*after write, iclass 11, count 0 2006.257.06:10:32.95#ibcon#*before return 0, iclass 11, count 0 2006.257.06:10:32.95#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:32.95#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:32.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:10:32.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:10:32.95$vck44/valo=3,564.99 2006.257.06:10:32.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.06:10:32.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.06:10:32.95#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:32.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:32.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:32.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:32.95#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:10:32.95#ibcon#first serial, iclass 13, count 0 2006.257.06:10:32.95#ibcon#enter sib2, iclass 13, count 0 2006.257.06:10:32.95#ibcon#flushed, iclass 13, count 0 2006.257.06:10:32.95#ibcon#about to write, iclass 13, count 0 2006.257.06:10:32.95#ibcon#wrote, iclass 13, count 0 2006.257.06:10:32.95#ibcon#about to read 3, iclass 13, count 0 2006.257.06:10:32.97#ibcon#read 3, iclass 13, count 0 2006.257.06:10:32.97#ibcon#about to read 4, iclass 13, count 0 2006.257.06:10:32.97#ibcon#read 4, iclass 13, count 0 2006.257.06:10:32.97#ibcon#about to read 5, iclass 13, count 0 2006.257.06:10:32.97#ibcon#read 5, iclass 13, count 0 2006.257.06:10:32.97#ibcon#about to read 6, iclass 13, count 0 2006.257.06:10:32.97#ibcon#read 6, iclass 13, count 0 2006.257.06:10:32.97#ibcon#end of sib2, iclass 13, count 0 2006.257.06:10:32.97#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:10:32.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:10:32.97#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:10:32.97#ibcon#*before write, iclass 13, count 0 2006.257.06:10:32.97#ibcon#enter sib2, iclass 13, count 0 2006.257.06:10:32.97#ibcon#flushed, iclass 13, count 0 2006.257.06:10:32.97#ibcon#about to write, iclass 13, count 0 2006.257.06:10:32.97#ibcon#wrote, iclass 13, count 0 2006.257.06:10:32.97#ibcon#about to read 3, iclass 13, count 0 2006.257.06:10:33.01#ibcon#read 3, iclass 13, count 0 2006.257.06:10:33.01#ibcon#about to read 4, iclass 13, count 0 2006.257.06:10:33.01#ibcon#read 4, iclass 13, count 0 2006.257.06:10:33.01#ibcon#about to read 5, iclass 13, count 0 2006.257.06:10:33.01#ibcon#read 5, iclass 13, count 0 2006.257.06:10:33.01#ibcon#about to read 6, iclass 13, count 0 2006.257.06:10:33.01#ibcon#read 6, iclass 13, count 0 2006.257.06:10:33.01#ibcon#end of sib2, iclass 13, count 0 2006.257.06:10:33.01#ibcon#*after write, iclass 13, count 0 2006.257.06:10:33.01#ibcon#*before return 0, iclass 13, count 0 2006.257.06:10:33.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:33.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:33.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:10:33.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:10:33.01$vck44/va=3,8 2006.257.06:10:33.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.06:10:33.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.06:10:33.01#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:33.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:33.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:33.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:33.07#ibcon#enter wrdev, iclass 15, count 2 2006.257.06:10:33.07#ibcon#first serial, iclass 15, count 2 2006.257.06:10:33.07#ibcon#enter sib2, iclass 15, count 2 2006.257.06:10:33.07#ibcon#flushed, iclass 15, count 2 2006.257.06:10:33.07#ibcon#about to write, iclass 15, count 2 2006.257.06:10:33.07#ibcon#wrote, iclass 15, count 2 2006.257.06:10:33.07#ibcon#about to read 3, iclass 15, count 2 2006.257.06:10:33.09#ibcon#read 3, iclass 15, count 2 2006.257.06:10:33.09#ibcon#about to read 4, iclass 15, count 2 2006.257.06:10:33.09#ibcon#read 4, iclass 15, count 2 2006.257.06:10:33.09#ibcon#about to read 5, iclass 15, count 2 2006.257.06:10:33.09#ibcon#read 5, iclass 15, count 2 2006.257.06:10:33.09#ibcon#about to read 6, iclass 15, count 2 2006.257.06:10:33.09#ibcon#read 6, iclass 15, count 2 2006.257.06:10:33.09#ibcon#end of sib2, iclass 15, count 2 2006.257.06:10:33.09#ibcon#*mode == 0, iclass 15, count 2 2006.257.06:10:33.09#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.06:10:33.09#ibcon#[25=AT03-08\r\n] 2006.257.06:10:33.09#ibcon#*before write, iclass 15, count 2 2006.257.06:10:33.09#ibcon#enter sib2, iclass 15, count 2 2006.257.06:10:33.09#ibcon#flushed, iclass 15, count 2 2006.257.06:10:33.09#ibcon#about to write, iclass 15, count 2 2006.257.06:10:33.09#ibcon#wrote, iclass 15, count 2 2006.257.06:10:33.09#ibcon#about to read 3, iclass 15, count 2 2006.257.06:10:33.12#ibcon#read 3, iclass 15, count 2 2006.257.06:10:33.12#ibcon#about to read 4, iclass 15, count 2 2006.257.06:10:33.12#ibcon#read 4, iclass 15, count 2 2006.257.06:10:33.12#ibcon#about to read 5, iclass 15, count 2 2006.257.06:10:33.12#ibcon#read 5, iclass 15, count 2 2006.257.06:10:33.12#ibcon#about to read 6, iclass 15, count 2 2006.257.06:10:33.12#ibcon#read 6, iclass 15, count 2 2006.257.06:10:33.12#ibcon#end of sib2, iclass 15, count 2 2006.257.06:10:33.12#ibcon#*after write, iclass 15, count 2 2006.257.06:10:33.12#ibcon#*before return 0, iclass 15, count 2 2006.257.06:10:33.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:33.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:33.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.06:10:33.12#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:33.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:33.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:33.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:33.24#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:10:33.24#ibcon#first serial, iclass 15, count 0 2006.257.06:10:33.24#ibcon#enter sib2, iclass 15, count 0 2006.257.06:10:33.24#ibcon#flushed, iclass 15, count 0 2006.257.06:10:33.24#ibcon#about to write, iclass 15, count 0 2006.257.06:10:33.24#ibcon#wrote, iclass 15, count 0 2006.257.06:10:33.24#ibcon#about to read 3, iclass 15, count 0 2006.257.06:10:33.26#ibcon#read 3, iclass 15, count 0 2006.257.06:10:33.26#ibcon#about to read 4, iclass 15, count 0 2006.257.06:10:33.26#ibcon#read 4, iclass 15, count 0 2006.257.06:10:33.26#ibcon#about to read 5, iclass 15, count 0 2006.257.06:10:33.26#ibcon#read 5, iclass 15, count 0 2006.257.06:10:33.26#ibcon#about to read 6, iclass 15, count 0 2006.257.06:10:33.26#ibcon#read 6, iclass 15, count 0 2006.257.06:10:33.26#ibcon#end of sib2, iclass 15, count 0 2006.257.06:10:33.26#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:10:33.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:10:33.26#ibcon#[25=USB\r\n] 2006.257.06:10:33.26#ibcon#*before write, iclass 15, count 0 2006.257.06:10:33.26#ibcon#enter sib2, iclass 15, count 0 2006.257.06:10:33.26#ibcon#flushed, iclass 15, count 0 2006.257.06:10:33.26#ibcon#about to write, iclass 15, count 0 2006.257.06:10:33.26#ibcon#wrote, iclass 15, count 0 2006.257.06:10:33.26#ibcon#about to read 3, iclass 15, count 0 2006.257.06:10:33.29#ibcon#read 3, iclass 15, count 0 2006.257.06:10:33.29#ibcon#about to read 4, iclass 15, count 0 2006.257.06:10:33.29#ibcon#read 4, iclass 15, count 0 2006.257.06:10:33.29#ibcon#about to read 5, iclass 15, count 0 2006.257.06:10:33.29#ibcon#read 5, iclass 15, count 0 2006.257.06:10:33.29#ibcon#about to read 6, iclass 15, count 0 2006.257.06:10:33.29#ibcon#read 6, iclass 15, count 0 2006.257.06:10:33.29#ibcon#end of sib2, iclass 15, count 0 2006.257.06:10:33.29#ibcon#*after write, iclass 15, count 0 2006.257.06:10:33.29#ibcon#*before return 0, iclass 15, count 0 2006.257.06:10:33.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:33.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:33.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:10:33.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:10:33.29$vck44/valo=4,624.99 2006.257.06:10:33.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.06:10:33.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.06:10:33.29#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:33.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:33.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:33.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:33.29#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:10:33.29#ibcon#first serial, iclass 17, count 0 2006.257.06:10:33.29#ibcon#enter sib2, iclass 17, count 0 2006.257.06:10:33.29#ibcon#flushed, iclass 17, count 0 2006.257.06:10:33.29#ibcon#about to write, iclass 17, count 0 2006.257.06:10:33.29#ibcon#wrote, iclass 17, count 0 2006.257.06:10:33.29#ibcon#about to read 3, iclass 17, count 0 2006.257.06:10:33.31#ibcon#read 3, iclass 17, count 0 2006.257.06:10:33.31#ibcon#about to read 4, iclass 17, count 0 2006.257.06:10:33.31#ibcon#read 4, iclass 17, count 0 2006.257.06:10:33.31#ibcon#about to read 5, iclass 17, count 0 2006.257.06:10:33.31#ibcon#read 5, iclass 17, count 0 2006.257.06:10:33.31#ibcon#about to read 6, iclass 17, count 0 2006.257.06:10:33.31#ibcon#read 6, iclass 17, count 0 2006.257.06:10:33.31#ibcon#end of sib2, iclass 17, count 0 2006.257.06:10:33.31#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:10:33.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:10:33.31#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:10:33.31#ibcon#*before write, iclass 17, count 0 2006.257.06:10:33.31#ibcon#enter sib2, iclass 17, count 0 2006.257.06:10:33.31#ibcon#flushed, iclass 17, count 0 2006.257.06:10:33.31#ibcon#about to write, iclass 17, count 0 2006.257.06:10:33.31#ibcon#wrote, iclass 17, count 0 2006.257.06:10:33.31#ibcon#about to read 3, iclass 17, count 0 2006.257.06:10:33.35#ibcon#read 3, iclass 17, count 0 2006.257.06:10:33.35#ibcon#about to read 4, iclass 17, count 0 2006.257.06:10:33.35#ibcon#read 4, iclass 17, count 0 2006.257.06:10:33.35#ibcon#about to read 5, iclass 17, count 0 2006.257.06:10:33.35#ibcon#read 5, iclass 17, count 0 2006.257.06:10:33.35#ibcon#about to read 6, iclass 17, count 0 2006.257.06:10:33.35#ibcon#read 6, iclass 17, count 0 2006.257.06:10:33.35#ibcon#end of sib2, iclass 17, count 0 2006.257.06:10:33.35#ibcon#*after write, iclass 17, count 0 2006.257.06:10:33.35#ibcon#*before return 0, iclass 17, count 0 2006.257.06:10:33.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:33.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:33.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:10:33.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:10:33.35$vck44/va=4,7 2006.257.06:10:33.35#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.06:10:33.35#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.06:10:33.35#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:33.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:33.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:33.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:33.41#ibcon#enter wrdev, iclass 19, count 2 2006.257.06:10:33.41#ibcon#first serial, iclass 19, count 2 2006.257.06:10:33.41#ibcon#enter sib2, iclass 19, count 2 2006.257.06:10:33.41#ibcon#flushed, iclass 19, count 2 2006.257.06:10:33.41#ibcon#about to write, iclass 19, count 2 2006.257.06:10:33.41#ibcon#wrote, iclass 19, count 2 2006.257.06:10:33.41#ibcon#about to read 3, iclass 19, count 2 2006.257.06:10:33.43#ibcon#read 3, iclass 19, count 2 2006.257.06:10:33.43#ibcon#about to read 4, iclass 19, count 2 2006.257.06:10:33.43#ibcon#read 4, iclass 19, count 2 2006.257.06:10:33.43#ibcon#about to read 5, iclass 19, count 2 2006.257.06:10:33.43#ibcon#read 5, iclass 19, count 2 2006.257.06:10:33.43#ibcon#about to read 6, iclass 19, count 2 2006.257.06:10:33.43#ibcon#read 6, iclass 19, count 2 2006.257.06:10:33.43#ibcon#end of sib2, iclass 19, count 2 2006.257.06:10:33.43#ibcon#*mode == 0, iclass 19, count 2 2006.257.06:10:33.43#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.06:10:33.43#ibcon#[25=AT04-07\r\n] 2006.257.06:10:33.43#ibcon#*before write, iclass 19, count 2 2006.257.06:10:33.43#ibcon#enter sib2, iclass 19, count 2 2006.257.06:10:33.43#ibcon#flushed, iclass 19, count 2 2006.257.06:10:33.43#ibcon#about to write, iclass 19, count 2 2006.257.06:10:33.43#ibcon#wrote, iclass 19, count 2 2006.257.06:10:33.43#ibcon#about to read 3, iclass 19, count 2 2006.257.06:10:33.46#ibcon#read 3, iclass 19, count 2 2006.257.06:10:33.46#ibcon#about to read 4, iclass 19, count 2 2006.257.06:10:33.46#ibcon#read 4, iclass 19, count 2 2006.257.06:10:33.46#ibcon#about to read 5, iclass 19, count 2 2006.257.06:10:33.46#ibcon#read 5, iclass 19, count 2 2006.257.06:10:33.46#ibcon#about to read 6, iclass 19, count 2 2006.257.06:10:33.46#ibcon#read 6, iclass 19, count 2 2006.257.06:10:33.46#ibcon#end of sib2, iclass 19, count 2 2006.257.06:10:33.46#ibcon#*after write, iclass 19, count 2 2006.257.06:10:33.46#ibcon#*before return 0, iclass 19, count 2 2006.257.06:10:33.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:33.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:33.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.06:10:33.46#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:33.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:33.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:33.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:33.58#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:10:33.58#ibcon#first serial, iclass 19, count 0 2006.257.06:10:33.58#ibcon#enter sib2, iclass 19, count 0 2006.257.06:10:33.58#ibcon#flushed, iclass 19, count 0 2006.257.06:10:33.58#ibcon#about to write, iclass 19, count 0 2006.257.06:10:33.58#ibcon#wrote, iclass 19, count 0 2006.257.06:10:33.58#ibcon#about to read 3, iclass 19, count 0 2006.257.06:10:33.60#ibcon#read 3, iclass 19, count 0 2006.257.06:10:33.60#ibcon#about to read 4, iclass 19, count 0 2006.257.06:10:33.60#ibcon#read 4, iclass 19, count 0 2006.257.06:10:33.60#ibcon#about to read 5, iclass 19, count 0 2006.257.06:10:33.60#ibcon#read 5, iclass 19, count 0 2006.257.06:10:33.60#ibcon#about to read 6, iclass 19, count 0 2006.257.06:10:33.60#ibcon#read 6, iclass 19, count 0 2006.257.06:10:33.60#ibcon#end of sib2, iclass 19, count 0 2006.257.06:10:33.60#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:10:33.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:10:33.60#ibcon#[25=USB\r\n] 2006.257.06:10:33.60#ibcon#*before write, iclass 19, count 0 2006.257.06:10:33.60#ibcon#enter sib2, iclass 19, count 0 2006.257.06:10:33.60#ibcon#flushed, iclass 19, count 0 2006.257.06:10:33.60#ibcon#about to write, iclass 19, count 0 2006.257.06:10:33.60#ibcon#wrote, iclass 19, count 0 2006.257.06:10:33.60#ibcon#about to read 3, iclass 19, count 0 2006.257.06:10:33.63#ibcon#read 3, iclass 19, count 0 2006.257.06:10:33.63#ibcon#about to read 4, iclass 19, count 0 2006.257.06:10:33.63#ibcon#read 4, iclass 19, count 0 2006.257.06:10:33.63#ibcon#about to read 5, iclass 19, count 0 2006.257.06:10:33.63#ibcon#read 5, iclass 19, count 0 2006.257.06:10:33.63#ibcon#about to read 6, iclass 19, count 0 2006.257.06:10:33.63#ibcon#read 6, iclass 19, count 0 2006.257.06:10:33.63#ibcon#end of sib2, iclass 19, count 0 2006.257.06:10:33.63#ibcon#*after write, iclass 19, count 0 2006.257.06:10:33.63#ibcon#*before return 0, iclass 19, count 0 2006.257.06:10:33.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:33.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:33.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:10:33.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:10:33.63$vck44/valo=5,734.99 2006.257.06:10:33.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.06:10:33.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.06:10:33.63#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:33.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:33.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:33.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:33.63#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:10:33.63#ibcon#first serial, iclass 21, count 0 2006.257.06:10:33.63#ibcon#enter sib2, iclass 21, count 0 2006.257.06:10:33.63#ibcon#flushed, iclass 21, count 0 2006.257.06:10:33.63#ibcon#about to write, iclass 21, count 0 2006.257.06:10:33.63#ibcon#wrote, iclass 21, count 0 2006.257.06:10:33.63#ibcon#about to read 3, iclass 21, count 0 2006.257.06:10:33.65#ibcon#read 3, iclass 21, count 0 2006.257.06:10:33.65#ibcon#about to read 4, iclass 21, count 0 2006.257.06:10:33.65#ibcon#read 4, iclass 21, count 0 2006.257.06:10:33.65#ibcon#about to read 5, iclass 21, count 0 2006.257.06:10:33.65#ibcon#read 5, iclass 21, count 0 2006.257.06:10:33.65#ibcon#about to read 6, iclass 21, count 0 2006.257.06:10:33.65#ibcon#read 6, iclass 21, count 0 2006.257.06:10:33.65#ibcon#end of sib2, iclass 21, count 0 2006.257.06:10:33.65#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:10:33.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:10:33.65#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:10:33.65#ibcon#*before write, iclass 21, count 0 2006.257.06:10:33.65#ibcon#enter sib2, iclass 21, count 0 2006.257.06:10:33.65#ibcon#flushed, iclass 21, count 0 2006.257.06:10:33.65#ibcon#about to write, iclass 21, count 0 2006.257.06:10:33.65#ibcon#wrote, iclass 21, count 0 2006.257.06:10:33.65#ibcon#about to read 3, iclass 21, count 0 2006.257.06:10:33.69#ibcon#read 3, iclass 21, count 0 2006.257.06:10:33.69#ibcon#about to read 4, iclass 21, count 0 2006.257.06:10:33.69#ibcon#read 4, iclass 21, count 0 2006.257.06:10:33.69#ibcon#about to read 5, iclass 21, count 0 2006.257.06:10:33.69#ibcon#read 5, iclass 21, count 0 2006.257.06:10:33.69#ibcon#about to read 6, iclass 21, count 0 2006.257.06:10:33.69#ibcon#read 6, iclass 21, count 0 2006.257.06:10:33.69#ibcon#end of sib2, iclass 21, count 0 2006.257.06:10:33.69#ibcon#*after write, iclass 21, count 0 2006.257.06:10:33.69#ibcon#*before return 0, iclass 21, count 0 2006.257.06:10:33.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:33.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:33.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:10:33.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:10:33.69$vck44/va=5,4 2006.257.06:10:33.69#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.06:10:33.69#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.06:10:33.69#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:33.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:33.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:33.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:33.75#ibcon#enter wrdev, iclass 23, count 2 2006.257.06:10:33.75#ibcon#first serial, iclass 23, count 2 2006.257.06:10:33.75#ibcon#enter sib2, iclass 23, count 2 2006.257.06:10:33.75#ibcon#flushed, iclass 23, count 2 2006.257.06:10:33.75#ibcon#about to write, iclass 23, count 2 2006.257.06:10:33.75#ibcon#wrote, iclass 23, count 2 2006.257.06:10:33.75#ibcon#about to read 3, iclass 23, count 2 2006.257.06:10:33.77#ibcon#read 3, iclass 23, count 2 2006.257.06:10:33.77#ibcon#about to read 4, iclass 23, count 2 2006.257.06:10:33.77#ibcon#read 4, iclass 23, count 2 2006.257.06:10:33.77#ibcon#about to read 5, iclass 23, count 2 2006.257.06:10:33.77#ibcon#read 5, iclass 23, count 2 2006.257.06:10:33.77#ibcon#about to read 6, iclass 23, count 2 2006.257.06:10:33.77#ibcon#read 6, iclass 23, count 2 2006.257.06:10:33.77#ibcon#end of sib2, iclass 23, count 2 2006.257.06:10:33.77#ibcon#*mode == 0, iclass 23, count 2 2006.257.06:10:33.77#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.06:10:33.77#ibcon#[25=AT05-04\r\n] 2006.257.06:10:33.77#ibcon#*before write, iclass 23, count 2 2006.257.06:10:33.77#ibcon#enter sib2, iclass 23, count 2 2006.257.06:10:33.77#ibcon#flushed, iclass 23, count 2 2006.257.06:10:33.77#ibcon#about to write, iclass 23, count 2 2006.257.06:10:33.77#ibcon#wrote, iclass 23, count 2 2006.257.06:10:33.77#ibcon#about to read 3, iclass 23, count 2 2006.257.06:10:33.80#ibcon#read 3, iclass 23, count 2 2006.257.06:10:33.80#ibcon#about to read 4, iclass 23, count 2 2006.257.06:10:33.80#ibcon#read 4, iclass 23, count 2 2006.257.06:10:33.80#ibcon#about to read 5, iclass 23, count 2 2006.257.06:10:33.80#ibcon#read 5, iclass 23, count 2 2006.257.06:10:33.80#ibcon#about to read 6, iclass 23, count 2 2006.257.06:10:33.80#ibcon#read 6, iclass 23, count 2 2006.257.06:10:33.80#ibcon#end of sib2, iclass 23, count 2 2006.257.06:10:33.80#ibcon#*after write, iclass 23, count 2 2006.257.06:10:33.80#ibcon#*before return 0, iclass 23, count 2 2006.257.06:10:33.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:33.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:33.80#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.06:10:33.80#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:33.80#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:33.92#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:33.92#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:33.92#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:10:33.92#ibcon#first serial, iclass 23, count 0 2006.257.06:10:33.92#ibcon#enter sib2, iclass 23, count 0 2006.257.06:10:33.92#ibcon#flushed, iclass 23, count 0 2006.257.06:10:33.92#ibcon#about to write, iclass 23, count 0 2006.257.06:10:33.92#ibcon#wrote, iclass 23, count 0 2006.257.06:10:33.92#ibcon#about to read 3, iclass 23, count 0 2006.257.06:10:33.94#ibcon#read 3, iclass 23, count 0 2006.257.06:10:33.94#ibcon#about to read 4, iclass 23, count 0 2006.257.06:10:33.94#ibcon#read 4, iclass 23, count 0 2006.257.06:10:33.94#ibcon#about to read 5, iclass 23, count 0 2006.257.06:10:33.94#ibcon#read 5, iclass 23, count 0 2006.257.06:10:33.94#ibcon#about to read 6, iclass 23, count 0 2006.257.06:10:33.94#ibcon#read 6, iclass 23, count 0 2006.257.06:10:33.94#ibcon#end of sib2, iclass 23, count 0 2006.257.06:10:33.94#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:10:33.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:10:33.94#ibcon#[25=USB\r\n] 2006.257.06:10:33.94#ibcon#*before write, iclass 23, count 0 2006.257.06:10:33.94#ibcon#enter sib2, iclass 23, count 0 2006.257.06:10:33.94#ibcon#flushed, iclass 23, count 0 2006.257.06:10:33.94#ibcon#about to write, iclass 23, count 0 2006.257.06:10:33.94#ibcon#wrote, iclass 23, count 0 2006.257.06:10:33.94#ibcon#about to read 3, iclass 23, count 0 2006.257.06:10:33.97#ibcon#read 3, iclass 23, count 0 2006.257.06:10:33.97#ibcon#about to read 4, iclass 23, count 0 2006.257.06:10:33.97#ibcon#read 4, iclass 23, count 0 2006.257.06:10:33.97#ibcon#about to read 5, iclass 23, count 0 2006.257.06:10:33.97#ibcon#read 5, iclass 23, count 0 2006.257.06:10:33.97#ibcon#about to read 6, iclass 23, count 0 2006.257.06:10:33.97#ibcon#read 6, iclass 23, count 0 2006.257.06:10:33.97#ibcon#end of sib2, iclass 23, count 0 2006.257.06:10:33.97#ibcon#*after write, iclass 23, count 0 2006.257.06:10:33.97#ibcon#*before return 0, iclass 23, count 0 2006.257.06:10:33.97#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:33.97#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:33.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:10:33.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:10:33.97$vck44/valo=6,814.99 2006.257.06:10:33.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.06:10:33.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.06:10:33.97#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:33.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:33.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:33.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:33.97#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:10:33.97#ibcon#first serial, iclass 25, count 0 2006.257.06:10:33.97#ibcon#enter sib2, iclass 25, count 0 2006.257.06:10:33.97#ibcon#flushed, iclass 25, count 0 2006.257.06:10:33.97#ibcon#about to write, iclass 25, count 0 2006.257.06:10:33.97#ibcon#wrote, iclass 25, count 0 2006.257.06:10:33.97#ibcon#about to read 3, iclass 25, count 0 2006.257.06:10:33.99#ibcon#read 3, iclass 25, count 0 2006.257.06:10:33.99#ibcon#about to read 4, iclass 25, count 0 2006.257.06:10:33.99#ibcon#read 4, iclass 25, count 0 2006.257.06:10:33.99#ibcon#about to read 5, iclass 25, count 0 2006.257.06:10:33.99#ibcon#read 5, iclass 25, count 0 2006.257.06:10:33.99#ibcon#about to read 6, iclass 25, count 0 2006.257.06:10:33.99#ibcon#read 6, iclass 25, count 0 2006.257.06:10:33.99#ibcon#end of sib2, iclass 25, count 0 2006.257.06:10:33.99#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:10:33.99#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:10:33.99#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:10:33.99#ibcon#*before write, iclass 25, count 0 2006.257.06:10:33.99#ibcon#enter sib2, iclass 25, count 0 2006.257.06:10:33.99#ibcon#flushed, iclass 25, count 0 2006.257.06:10:33.99#ibcon#about to write, iclass 25, count 0 2006.257.06:10:33.99#ibcon#wrote, iclass 25, count 0 2006.257.06:10:33.99#ibcon#about to read 3, iclass 25, count 0 2006.257.06:10:34.03#ibcon#read 3, iclass 25, count 0 2006.257.06:10:34.03#ibcon#about to read 4, iclass 25, count 0 2006.257.06:10:34.03#ibcon#read 4, iclass 25, count 0 2006.257.06:10:34.03#ibcon#about to read 5, iclass 25, count 0 2006.257.06:10:34.03#ibcon#read 5, iclass 25, count 0 2006.257.06:10:34.03#ibcon#about to read 6, iclass 25, count 0 2006.257.06:10:34.03#ibcon#read 6, iclass 25, count 0 2006.257.06:10:34.03#ibcon#end of sib2, iclass 25, count 0 2006.257.06:10:34.03#ibcon#*after write, iclass 25, count 0 2006.257.06:10:34.03#ibcon#*before return 0, iclass 25, count 0 2006.257.06:10:34.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:34.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:34.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:10:34.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:10:34.03$vck44/va=6,4 2006.257.06:10:34.03#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.06:10:34.03#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.06:10:34.03#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:34.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:34.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:34.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:34.09#ibcon#enter wrdev, iclass 27, count 2 2006.257.06:10:34.09#ibcon#first serial, iclass 27, count 2 2006.257.06:10:34.09#ibcon#enter sib2, iclass 27, count 2 2006.257.06:10:34.09#ibcon#flushed, iclass 27, count 2 2006.257.06:10:34.09#ibcon#about to write, iclass 27, count 2 2006.257.06:10:34.09#ibcon#wrote, iclass 27, count 2 2006.257.06:10:34.09#ibcon#about to read 3, iclass 27, count 2 2006.257.06:10:34.11#ibcon#read 3, iclass 27, count 2 2006.257.06:10:34.11#ibcon#about to read 4, iclass 27, count 2 2006.257.06:10:34.11#ibcon#read 4, iclass 27, count 2 2006.257.06:10:34.11#ibcon#about to read 5, iclass 27, count 2 2006.257.06:10:34.11#ibcon#read 5, iclass 27, count 2 2006.257.06:10:34.11#ibcon#about to read 6, iclass 27, count 2 2006.257.06:10:34.11#ibcon#read 6, iclass 27, count 2 2006.257.06:10:34.11#ibcon#end of sib2, iclass 27, count 2 2006.257.06:10:34.11#ibcon#*mode == 0, iclass 27, count 2 2006.257.06:10:34.11#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.06:10:34.11#ibcon#[25=AT06-04\r\n] 2006.257.06:10:34.11#ibcon#*before write, iclass 27, count 2 2006.257.06:10:34.11#ibcon#enter sib2, iclass 27, count 2 2006.257.06:10:34.11#ibcon#flushed, iclass 27, count 2 2006.257.06:10:34.11#ibcon#about to write, iclass 27, count 2 2006.257.06:10:34.11#ibcon#wrote, iclass 27, count 2 2006.257.06:10:34.11#ibcon#about to read 3, iclass 27, count 2 2006.257.06:10:34.14#ibcon#read 3, iclass 27, count 2 2006.257.06:10:34.14#ibcon#about to read 4, iclass 27, count 2 2006.257.06:10:34.14#ibcon#read 4, iclass 27, count 2 2006.257.06:10:34.14#ibcon#about to read 5, iclass 27, count 2 2006.257.06:10:34.14#ibcon#read 5, iclass 27, count 2 2006.257.06:10:34.14#ibcon#about to read 6, iclass 27, count 2 2006.257.06:10:34.14#ibcon#read 6, iclass 27, count 2 2006.257.06:10:34.14#ibcon#end of sib2, iclass 27, count 2 2006.257.06:10:34.14#ibcon#*after write, iclass 27, count 2 2006.257.06:10:34.14#ibcon#*before return 0, iclass 27, count 2 2006.257.06:10:34.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:34.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:34.14#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.06:10:34.14#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:34.14#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:34.26#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:34.26#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:34.26#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:10:34.26#ibcon#first serial, iclass 27, count 0 2006.257.06:10:34.26#ibcon#enter sib2, iclass 27, count 0 2006.257.06:10:34.26#ibcon#flushed, iclass 27, count 0 2006.257.06:10:34.26#ibcon#about to write, iclass 27, count 0 2006.257.06:10:34.26#ibcon#wrote, iclass 27, count 0 2006.257.06:10:34.26#ibcon#about to read 3, iclass 27, count 0 2006.257.06:10:34.28#ibcon#read 3, iclass 27, count 0 2006.257.06:10:34.28#ibcon#about to read 4, iclass 27, count 0 2006.257.06:10:34.28#ibcon#read 4, iclass 27, count 0 2006.257.06:10:34.28#ibcon#about to read 5, iclass 27, count 0 2006.257.06:10:34.28#ibcon#read 5, iclass 27, count 0 2006.257.06:10:34.28#ibcon#about to read 6, iclass 27, count 0 2006.257.06:10:34.28#ibcon#read 6, iclass 27, count 0 2006.257.06:10:34.28#ibcon#end of sib2, iclass 27, count 0 2006.257.06:10:34.28#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:10:34.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:10:34.28#ibcon#[25=USB\r\n] 2006.257.06:10:34.28#ibcon#*before write, iclass 27, count 0 2006.257.06:10:34.28#ibcon#enter sib2, iclass 27, count 0 2006.257.06:10:34.28#ibcon#flushed, iclass 27, count 0 2006.257.06:10:34.28#ibcon#about to write, iclass 27, count 0 2006.257.06:10:34.28#ibcon#wrote, iclass 27, count 0 2006.257.06:10:34.28#ibcon#about to read 3, iclass 27, count 0 2006.257.06:10:34.31#ibcon#read 3, iclass 27, count 0 2006.257.06:10:34.31#ibcon#about to read 4, iclass 27, count 0 2006.257.06:10:34.31#ibcon#read 4, iclass 27, count 0 2006.257.06:10:34.31#ibcon#about to read 5, iclass 27, count 0 2006.257.06:10:34.31#ibcon#read 5, iclass 27, count 0 2006.257.06:10:34.31#ibcon#about to read 6, iclass 27, count 0 2006.257.06:10:34.31#ibcon#read 6, iclass 27, count 0 2006.257.06:10:34.31#ibcon#end of sib2, iclass 27, count 0 2006.257.06:10:34.31#ibcon#*after write, iclass 27, count 0 2006.257.06:10:34.31#ibcon#*before return 0, iclass 27, count 0 2006.257.06:10:34.31#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:34.31#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:34.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:10:34.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:10:34.31$vck44/valo=7,864.99 2006.257.06:10:34.31#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.06:10:34.31#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.06:10:34.31#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:34.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:34.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:34.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:34.31#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:10:34.31#ibcon#first serial, iclass 29, count 0 2006.257.06:10:34.31#ibcon#enter sib2, iclass 29, count 0 2006.257.06:10:34.31#ibcon#flushed, iclass 29, count 0 2006.257.06:10:34.31#ibcon#about to write, iclass 29, count 0 2006.257.06:10:34.31#ibcon#wrote, iclass 29, count 0 2006.257.06:10:34.31#ibcon#about to read 3, iclass 29, count 0 2006.257.06:10:34.33#ibcon#read 3, iclass 29, count 0 2006.257.06:10:34.33#ibcon#about to read 4, iclass 29, count 0 2006.257.06:10:34.33#ibcon#read 4, iclass 29, count 0 2006.257.06:10:34.33#ibcon#about to read 5, iclass 29, count 0 2006.257.06:10:34.33#ibcon#read 5, iclass 29, count 0 2006.257.06:10:34.33#ibcon#about to read 6, iclass 29, count 0 2006.257.06:10:34.33#ibcon#read 6, iclass 29, count 0 2006.257.06:10:34.33#ibcon#end of sib2, iclass 29, count 0 2006.257.06:10:34.33#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:10:34.33#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:10:34.33#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:10:34.33#ibcon#*before write, iclass 29, count 0 2006.257.06:10:34.33#ibcon#enter sib2, iclass 29, count 0 2006.257.06:10:34.33#ibcon#flushed, iclass 29, count 0 2006.257.06:10:34.33#ibcon#about to write, iclass 29, count 0 2006.257.06:10:34.33#ibcon#wrote, iclass 29, count 0 2006.257.06:10:34.33#ibcon#about to read 3, iclass 29, count 0 2006.257.06:10:34.37#ibcon#read 3, iclass 29, count 0 2006.257.06:10:34.37#ibcon#about to read 4, iclass 29, count 0 2006.257.06:10:34.37#ibcon#read 4, iclass 29, count 0 2006.257.06:10:34.37#ibcon#about to read 5, iclass 29, count 0 2006.257.06:10:34.37#ibcon#read 5, iclass 29, count 0 2006.257.06:10:34.37#ibcon#about to read 6, iclass 29, count 0 2006.257.06:10:34.37#ibcon#read 6, iclass 29, count 0 2006.257.06:10:34.37#ibcon#end of sib2, iclass 29, count 0 2006.257.06:10:34.37#ibcon#*after write, iclass 29, count 0 2006.257.06:10:34.37#ibcon#*before return 0, iclass 29, count 0 2006.257.06:10:34.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:34.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:34.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:10:34.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:10:34.37$vck44/va=7,4 2006.257.06:10:34.37#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.06:10:34.37#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.06:10:34.37#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:34.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:34.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:34.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:34.43#ibcon#enter wrdev, iclass 31, count 2 2006.257.06:10:34.43#ibcon#first serial, iclass 31, count 2 2006.257.06:10:34.43#ibcon#enter sib2, iclass 31, count 2 2006.257.06:10:34.43#ibcon#flushed, iclass 31, count 2 2006.257.06:10:34.43#ibcon#about to write, iclass 31, count 2 2006.257.06:10:34.43#ibcon#wrote, iclass 31, count 2 2006.257.06:10:34.43#ibcon#about to read 3, iclass 31, count 2 2006.257.06:10:34.45#ibcon#read 3, iclass 31, count 2 2006.257.06:10:34.45#ibcon#about to read 4, iclass 31, count 2 2006.257.06:10:34.45#ibcon#read 4, iclass 31, count 2 2006.257.06:10:34.45#ibcon#about to read 5, iclass 31, count 2 2006.257.06:10:34.45#ibcon#read 5, iclass 31, count 2 2006.257.06:10:34.45#ibcon#about to read 6, iclass 31, count 2 2006.257.06:10:34.45#ibcon#read 6, iclass 31, count 2 2006.257.06:10:34.45#ibcon#end of sib2, iclass 31, count 2 2006.257.06:10:34.45#ibcon#*mode == 0, iclass 31, count 2 2006.257.06:10:34.45#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.06:10:34.45#ibcon#[25=AT07-04\r\n] 2006.257.06:10:34.45#ibcon#*before write, iclass 31, count 2 2006.257.06:10:34.45#ibcon#enter sib2, iclass 31, count 2 2006.257.06:10:34.45#ibcon#flushed, iclass 31, count 2 2006.257.06:10:34.45#ibcon#about to write, iclass 31, count 2 2006.257.06:10:34.45#ibcon#wrote, iclass 31, count 2 2006.257.06:10:34.45#ibcon#about to read 3, iclass 31, count 2 2006.257.06:10:34.48#ibcon#read 3, iclass 31, count 2 2006.257.06:10:34.48#ibcon#about to read 4, iclass 31, count 2 2006.257.06:10:34.48#ibcon#read 4, iclass 31, count 2 2006.257.06:10:34.48#ibcon#about to read 5, iclass 31, count 2 2006.257.06:10:34.48#ibcon#read 5, iclass 31, count 2 2006.257.06:10:34.48#ibcon#about to read 6, iclass 31, count 2 2006.257.06:10:34.48#ibcon#read 6, iclass 31, count 2 2006.257.06:10:34.48#ibcon#end of sib2, iclass 31, count 2 2006.257.06:10:34.48#ibcon#*after write, iclass 31, count 2 2006.257.06:10:34.48#ibcon#*before return 0, iclass 31, count 2 2006.257.06:10:34.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:34.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:34.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.06:10:34.48#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:34.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:34.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:34.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:34.60#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:10:34.60#ibcon#first serial, iclass 31, count 0 2006.257.06:10:34.60#ibcon#enter sib2, iclass 31, count 0 2006.257.06:10:34.60#ibcon#flushed, iclass 31, count 0 2006.257.06:10:34.60#ibcon#about to write, iclass 31, count 0 2006.257.06:10:34.60#ibcon#wrote, iclass 31, count 0 2006.257.06:10:34.60#ibcon#about to read 3, iclass 31, count 0 2006.257.06:10:34.62#ibcon#read 3, iclass 31, count 0 2006.257.06:10:34.62#ibcon#about to read 4, iclass 31, count 0 2006.257.06:10:34.62#ibcon#read 4, iclass 31, count 0 2006.257.06:10:34.62#ibcon#about to read 5, iclass 31, count 0 2006.257.06:10:34.62#ibcon#read 5, iclass 31, count 0 2006.257.06:10:34.62#ibcon#about to read 6, iclass 31, count 0 2006.257.06:10:34.62#ibcon#read 6, iclass 31, count 0 2006.257.06:10:34.62#ibcon#end of sib2, iclass 31, count 0 2006.257.06:10:34.62#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:10:34.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:10:34.62#ibcon#[25=USB\r\n] 2006.257.06:10:34.62#ibcon#*before write, iclass 31, count 0 2006.257.06:10:34.62#ibcon#enter sib2, iclass 31, count 0 2006.257.06:10:34.62#ibcon#flushed, iclass 31, count 0 2006.257.06:10:34.62#ibcon#about to write, iclass 31, count 0 2006.257.06:10:34.62#ibcon#wrote, iclass 31, count 0 2006.257.06:10:34.62#ibcon#about to read 3, iclass 31, count 0 2006.257.06:10:34.65#ibcon#read 3, iclass 31, count 0 2006.257.06:10:34.65#ibcon#about to read 4, iclass 31, count 0 2006.257.06:10:34.65#ibcon#read 4, iclass 31, count 0 2006.257.06:10:34.65#ibcon#about to read 5, iclass 31, count 0 2006.257.06:10:34.65#ibcon#read 5, iclass 31, count 0 2006.257.06:10:34.65#ibcon#about to read 6, iclass 31, count 0 2006.257.06:10:34.65#ibcon#read 6, iclass 31, count 0 2006.257.06:10:34.65#ibcon#end of sib2, iclass 31, count 0 2006.257.06:10:34.65#ibcon#*after write, iclass 31, count 0 2006.257.06:10:34.65#ibcon#*before return 0, iclass 31, count 0 2006.257.06:10:34.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:34.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:34.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:10:34.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:10:34.65$vck44/valo=8,884.99 2006.257.06:10:34.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.06:10:34.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.06:10:34.65#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:34.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:34.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:34.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:34.65#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:10:34.65#ibcon#first serial, iclass 33, count 0 2006.257.06:10:34.65#ibcon#enter sib2, iclass 33, count 0 2006.257.06:10:34.65#ibcon#flushed, iclass 33, count 0 2006.257.06:10:34.65#ibcon#about to write, iclass 33, count 0 2006.257.06:10:34.65#ibcon#wrote, iclass 33, count 0 2006.257.06:10:34.65#ibcon#about to read 3, iclass 33, count 0 2006.257.06:10:34.67#ibcon#read 3, iclass 33, count 0 2006.257.06:10:34.67#ibcon#about to read 4, iclass 33, count 0 2006.257.06:10:34.67#ibcon#read 4, iclass 33, count 0 2006.257.06:10:34.67#ibcon#about to read 5, iclass 33, count 0 2006.257.06:10:34.67#ibcon#read 5, iclass 33, count 0 2006.257.06:10:34.67#ibcon#about to read 6, iclass 33, count 0 2006.257.06:10:34.67#ibcon#read 6, iclass 33, count 0 2006.257.06:10:34.67#ibcon#end of sib2, iclass 33, count 0 2006.257.06:10:34.67#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:10:34.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:10:34.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:10:34.67#ibcon#*before write, iclass 33, count 0 2006.257.06:10:34.67#ibcon#enter sib2, iclass 33, count 0 2006.257.06:10:34.67#ibcon#flushed, iclass 33, count 0 2006.257.06:10:34.67#ibcon#about to write, iclass 33, count 0 2006.257.06:10:34.67#ibcon#wrote, iclass 33, count 0 2006.257.06:10:34.67#ibcon#about to read 3, iclass 33, count 0 2006.257.06:10:34.71#ibcon#read 3, iclass 33, count 0 2006.257.06:10:34.71#ibcon#about to read 4, iclass 33, count 0 2006.257.06:10:34.71#ibcon#read 4, iclass 33, count 0 2006.257.06:10:34.71#ibcon#about to read 5, iclass 33, count 0 2006.257.06:10:34.71#ibcon#read 5, iclass 33, count 0 2006.257.06:10:34.71#ibcon#about to read 6, iclass 33, count 0 2006.257.06:10:34.71#ibcon#read 6, iclass 33, count 0 2006.257.06:10:34.71#ibcon#end of sib2, iclass 33, count 0 2006.257.06:10:34.71#ibcon#*after write, iclass 33, count 0 2006.257.06:10:34.71#ibcon#*before return 0, iclass 33, count 0 2006.257.06:10:34.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:34.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:34.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:10:34.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:10:34.71$vck44/va=8,4 2006.257.06:10:34.71#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.06:10:34.71#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.06:10:34.71#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:34.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:10:34.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:10:34.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:10:34.77#ibcon#enter wrdev, iclass 35, count 2 2006.257.06:10:34.77#ibcon#first serial, iclass 35, count 2 2006.257.06:10:34.77#ibcon#enter sib2, iclass 35, count 2 2006.257.06:10:34.77#ibcon#flushed, iclass 35, count 2 2006.257.06:10:34.77#ibcon#about to write, iclass 35, count 2 2006.257.06:10:34.77#ibcon#wrote, iclass 35, count 2 2006.257.06:10:34.77#ibcon#about to read 3, iclass 35, count 2 2006.257.06:10:34.79#ibcon#read 3, iclass 35, count 2 2006.257.06:10:34.79#ibcon#about to read 4, iclass 35, count 2 2006.257.06:10:34.79#ibcon#read 4, iclass 35, count 2 2006.257.06:10:34.79#ibcon#about to read 5, iclass 35, count 2 2006.257.06:10:34.79#ibcon#read 5, iclass 35, count 2 2006.257.06:10:34.79#ibcon#about to read 6, iclass 35, count 2 2006.257.06:10:34.79#ibcon#read 6, iclass 35, count 2 2006.257.06:10:34.79#ibcon#end of sib2, iclass 35, count 2 2006.257.06:10:34.79#ibcon#*mode == 0, iclass 35, count 2 2006.257.06:10:34.79#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.06:10:34.79#ibcon#[25=AT08-04\r\n] 2006.257.06:10:34.79#ibcon#*before write, iclass 35, count 2 2006.257.06:10:34.79#ibcon#enter sib2, iclass 35, count 2 2006.257.06:10:34.79#ibcon#flushed, iclass 35, count 2 2006.257.06:10:34.79#ibcon#about to write, iclass 35, count 2 2006.257.06:10:34.79#ibcon#wrote, iclass 35, count 2 2006.257.06:10:34.79#ibcon#about to read 3, iclass 35, count 2 2006.257.06:10:34.82#ibcon#read 3, iclass 35, count 2 2006.257.06:10:34.82#ibcon#about to read 4, iclass 35, count 2 2006.257.06:10:34.82#ibcon#read 4, iclass 35, count 2 2006.257.06:10:34.82#ibcon#about to read 5, iclass 35, count 2 2006.257.06:10:34.82#ibcon#read 5, iclass 35, count 2 2006.257.06:10:34.82#ibcon#about to read 6, iclass 35, count 2 2006.257.06:10:34.82#ibcon#read 6, iclass 35, count 2 2006.257.06:10:34.82#ibcon#end of sib2, iclass 35, count 2 2006.257.06:10:34.82#ibcon#*after write, iclass 35, count 2 2006.257.06:10:34.82#ibcon#*before return 0, iclass 35, count 2 2006.257.06:10:34.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:10:34.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:10:34.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.06:10:34.82#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:34.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:10:34.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:10:34.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:10:34.94#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:10:34.94#ibcon#first serial, iclass 35, count 0 2006.257.06:10:34.94#ibcon#enter sib2, iclass 35, count 0 2006.257.06:10:34.94#ibcon#flushed, iclass 35, count 0 2006.257.06:10:34.94#ibcon#about to write, iclass 35, count 0 2006.257.06:10:34.94#ibcon#wrote, iclass 35, count 0 2006.257.06:10:34.94#ibcon#about to read 3, iclass 35, count 0 2006.257.06:10:34.96#ibcon#read 3, iclass 35, count 0 2006.257.06:10:34.96#ibcon#about to read 4, iclass 35, count 0 2006.257.06:10:34.96#ibcon#read 4, iclass 35, count 0 2006.257.06:10:34.96#ibcon#about to read 5, iclass 35, count 0 2006.257.06:10:34.96#ibcon#read 5, iclass 35, count 0 2006.257.06:10:34.96#ibcon#about to read 6, iclass 35, count 0 2006.257.06:10:34.96#ibcon#read 6, iclass 35, count 0 2006.257.06:10:34.96#ibcon#end of sib2, iclass 35, count 0 2006.257.06:10:34.96#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:10:34.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:10:34.96#ibcon#[25=USB\r\n] 2006.257.06:10:34.96#ibcon#*before write, iclass 35, count 0 2006.257.06:10:34.96#ibcon#enter sib2, iclass 35, count 0 2006.257.06:10:34.96#ibcon#flushed, iclass 35, count 0 2006.257.06:10:34.96#ibcon#about to write, iclass 35, count 0 2006.257.06:10:34.96#ibcon#wrote, iclass 35, count 0 2006.257.06:10:34.96#ibcon#about to read 3, iclass 35, count 0 2006.257.06:10:34.99#ibcon#read 3, iclass 35, count 0 2006.257.06:10:34.99#ibcon#about to read 4, iclass 35, count 0 2006.257.06:10:34.99#ibcon#read 4, iclass 35, count 0 2006.257.06:10:34.99#ibcon#about to read 5, iclass 35, count 0 2006.257.06:10:34.99#ibcon#read 5, iclass 35, count 0 2006.257.06:10:34.99#ibcon#about to read 6, iclass 35, count 0 2006.257.06:10:34.99#ibcon#read 6, iclass 35, count 0 2006.257.06:10:34.99#ibcon#end of sib2, iclass 35, count 0 2006.257.06:10:34.99#ibcon#*after write, iclass 35, count 0 2006.257.06:10:34.99#ibcon#*before return 0, iclass 35, count 0 2006.257.06:10:34.99#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:10:34.99#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:10:34.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:10:34.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:10:34.99$vck44/vblo=1,629.99 2006.257.06:10:34.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.06:10:34.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.06:10:34.99#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:34.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:34.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:34.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:34.99#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:10:34.99#ibcon#first serial, iclass 37, count 0 2006.257.06:10:34.99#ibcon#enter sib2, iclass 37, count 0 2006.257.06:10:34.99#ibcon#flushed, iclass 37, count 0 2006.257.06:10:34.99#ibcon#about to write, iclass 37, count 0 2006.257.06:10:34.99#ibcon#wrote, iclass 37, count 0 2006.257.06:10:34.99#ibcon#about to read 3, iclass 37, count 0 2006.257.06:10:35.01#ibcon#read 3, iclass 37, count 0 2006.257.06:10:35.01#ibcon#about to read 4, iclass 37, count 0 2006.257.06:10:35.01#ibcon#read 4, iclass 37, count 0 2006.257.06:10:35.01#ibcon#about to read 5, iclass 37, count 0 2006.257.06:10:35.01#ibcon#read 5, iclass 37, count 0 2006.257.06:10:35.01#ibcon#about to read 6, iclass 37, count 0 2006.257.06:10:35.01#ibcon#read 6, iclass 37, count 0 2006.257.06:10:35.01#ibcon#end of sib2, iclass 37, count 0 2006.257.06:10:35.01#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:10:35.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:10:35.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:10:35.01#ibcon#*before write, iclass 37, count 0 2006.257.06:10:35.01#ibcon#enter sib2, iclass 37, count 0 2006.257.06:10:35.01#ibcon#flushed, iclass 37, count 0 2006.257.06:10:35.01#ibcon#about to write, iclass 37, count 0 2006.257.06:10:35.01#ibcon#wrote, iclass 37, count 0 2006.257.06:10:35.01#ibcon#about to read 3, iclass 37, count 0 2006.257.06:10:35.05#ibcon#read 3, iclass 37, count 0 2006.257.06:10:35.05#ibcon#about to read 4, iclass 37, count 0 2006.257.06:10:35.05#ibcon#read 4, iclass 37, count 0 2006.257.06:10:35.05#ibcon#about to read 5, iclass 37, count 0 2006.257.06:10:35.05#ibcon#read 5, iclass 37, count 0 2006.257.06:10:35.05#ibcon#about to read 6, iclass 37, count 0 2006.257.06:10:35.05#ibcon#read 6, iclass 37, count 0 2006.257.06:10:35.05#ibcon#end of sib2, iclass 37, count 0 2006.257.06:10:35.05#ibcon#*after write, iclass 37, count 0 2006.257.06:10:35.05#ibcon#*before return 0, iclass 37, count 0 2006.257.06:10:35.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:35.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:10:35.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:10:35.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:10:35.05$vck44/vb=1,4 2006.257.06:10:35.05#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.06:10:35.05#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.06:10:35.05#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:35.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:35.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:35.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:35.05#ibcon#enter wrdev, iclass 39, count 2 2006.257.06:10:35.05#ibcon#first serial, iclass 39, count 2 2006.257.06:10:35.05#ibcon#enter sib2, iclass 39, count 2 2006.257.06:10:35.05#ibcon#flushed, iclass 39, count 2 2006.257.06:10:35.05#ibcon#about to write, iclass 39, count 2 2006.257.06:10:35.05#ibcon#wrote, iclass 39, count 2 2006.257.06:10:35.05#ibcon#about to read 3, iclass 39, count 2 2006.257.06:10:35.07#ibcon#read 3, iclass 39, count 2 2006.257.06:10:35.07#ibcon#about to read 4, iclass 39, count 2 2006.257.06:10:35.07#ibcon#read 4, iclass 39, count 2 2006.257.06:10:35.07#ibcon#about to read 5, iclass 39, count 2 2006.257.06:10:35.07#ibcon#read 5, iclass 39, count 2 2006.257.06:10:35.07#ibcon#about to read 6, iclass 39, count 2 2006.257.06:10:35.07#ibcon#read 6, iclass 39, count 2 2006.257.06:10:35.07#ibcon#end of sib2, iclass 39, count 2 2006.257.06:10:35.07#ibcon#*mode == 0, iclass 39, count 2 2006.257.06:10:35.07#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.06:10:35.07#ibcon#[27=AT01-04\r\n] 2006.257.06:10:35.07#ibcon#*before write, iclass 39, count 2 2006.257.06:10:35.07#ibcon#enter sib2, iclass 39, count 2 2006.257.06:10:35.07#ibcon#flushed, iclass 39, count 2 2006.257.06:10:35.07#ibcon#about to write, iclass 39, count 2 2006.257.06:10:35.07#ibcon#wrote, iclass 39, count 2 2006.257.06:10:35.07#ibcon#about to read 3, iclass 39, count 2 2006.257.06:10:35.10#ibcon#read 3, iclass 39, count 2 2006.257.06:10:35.10#ibcon#about to read 4, iclass 39, count 2 2006.257.06:10:35.10#ibcon#read 4, iclass 39, count 2 2006.257.06:10:35.10#ibcon#about to read 5, iclass 39, count 2 2006.257.06:10:35.10#ibcon#read 5, iclass 39, count 2 2006.257.06:10:35.10#ibcon#about to read 6, iclass 39, count 2 2006.257.06:10:35.10#ibcon#read 6, iclass 39, count 2 2006.257.06:10:35.10#ibcon#end of sib2, iclass 39, count 2 2006.257.06:10:35.10#ibcon#*after write, iclass 39, count 2 2006.257.06:10:35.10#ibcon#*before return 0, iclass 39, count 2 2006.257.06:10:35.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:35.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:10:35.10#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.06:10:35.10#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:35.10#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:35.22#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:35.22#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:35.22#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:10:35.22#ibcon#first serial, iclass 39, count 0 2006.257.06:10:35.22#ibcon#enter sib2, iclass 39, count 0 2006.257.06:10:35.22#ibcon#flushed, iclass 39, count 0 2006.257.06:10:35.22#ibcon#about to write, iclass 39, count 0 2006.257.06:10:35.22#ibcon#wrote, iclass 39, count 0 2006.257.06:10:35.22#ibcon#about to read 3, iclass 39, count 0 2006.257.06:10:35.24#ibcon#read 3, iclass 39, count 0 2006.257.06:10:35.24#ibcon#about to read 4, iclass 39, count 0 2006.257.06:10:35.24#ibcon#read 4, iclass 39, count 0 2006.257.06:10:35.24#ibcon#about to read 5, iclass 39, count 0 2006.257.06:10:35.24#ibcon#read 5, iclass 39, count 0 2006.257.06:10:35.24#ibcon#about to read 6, iclass 39, count 0 2006.257.06:10:35.24#ibcon#read 6, iclass 39, count 0 2006.257.06:10:35.24#ibcon#end of sib2, iclass 39, count 0 2006.257.06:10:35.24#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:10:35.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:10:35.24#ibcon#[27=USB\r\n] 2006.257.06:10:35.24#ibcon#*before write, iclass 39, count 0 2006.257.06:10:35.24#ibcon#enter sib2, iclass 39, count 0 2006.257.06:10:35.24#ibcon#flushed, iclass 39, count 0 2006.257.06:10:35.24#ibcon#about to write, iclass 39, count 0 2006.257.06:10:35.24#ibcon#wrote, iclass 39, count 0 2006.257.06:10:35.24#ibcon#about to read 3, iclass 39, count 0 2006.257.06:10:35.27#ibcon#read 3, iclass 39, count 0 2006.257.06:10:35.27#ibcon#about to read 4, iclass 39, count 0 2006.257.06:10:35.27#ibcon#read 4, iclass 39, count 0 2006.257.06:10:35.27#ibcon#about to read 5, iclass 39, count 0 2006.257.06:10:35.27#ibcon#read 5, iclass 39, count 0 2006.257.06:10:35.27#ibcon#about to read 6, iclass 39, count 0 2006.257.06:10:35.27#ibcon#read 6, iclass 39, count 0 2006.257.06:10:35.27#ibcon#end of sib2, iclass 39, count 0 2006.257.06:10:35.27#ibcon#*after write, iclass 39, count 0 2006.257.06:10:35.27#ibcon#*before return 0, iclass 39, count 0 2006.257.06:10:35.27#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:35.27#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:10:35.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:10:35.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:10:35.27$vck44/vblo=2,634.99 2006.257.06:10:35.27#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.06:10:35.27#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.06:10:35.27#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:35.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:10:35.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:10:35.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:10:35.27#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:10:35.27#ibcon#first serial, iclass 3, count 0 2006.257.06:10:35.27#ibcon#enter sib2, iclass 3, count 0 2006.257.06:10:35.27#ibcon#flushed, iclass 3, count 0 2006.257.06:10:35.27#ibcon#about to write, iclass 3, count 0 2006.257.06:10:35.27#ibcon#wrote, iclass 3, count 0 2006.257.06:10:35.27#ibcon#about to read 3, iclass 3, count 0 2006.257.06:10:35.29#ibcon#read 3, iclass 3, count 0 2006.257.06:10:35.29#ibcon#about to read 4, iclass 3, count 0 2006.257.06:10:35.29#ibcon#read 4, iclass 3, count 0 2006.257.06:10:35.29#ibcon#about to read 5, iclass 3, count 0 2006.257.06:10:35.29#ibcon#read 5, iclass 3, count 0 2006.257.06:10:35.29#ibcon#about to read 6, iclass 3, count 0 2006.257.06:10:35.29#ibcon#read 6, iclass 3, count 0 2006.257.06:10:35.29#ibcon#end of sib2, iclass 3, count 0 2006.257.06:10:35.29#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:10:35.29#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:10:35.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:10:35.29#ibcon#*before write, iclass 3, count 0 2006.257.06:10:35.29#ibcon#enter sib2, iclass 3, count 0 2006.257.06:10:35.29#ibcon#flushed, iclass 3, count 0 2006.257.06:10:35.29#ibcon#about to write, iclass 3, count 0 2006.257.06:10:35.29#ibcon#wrote, iclass 3, count 0 2006.257.06:10:35.29#ibcon#about to read 3, iclass 3, count 0 2006.257.06:10:35.33#ibcon#read 3, iclass 3, count 0 2006.257.06:10:35.33#ibcon#about to read 4, iclass 3, count 0 2006.257.06:10:35.33#ibcon#read 4, iclass 3, count 0 2006.257.06:10:35.33#ibcon#about to read 5, iclass 3, count 0 2006.257.06:10:35.33#ibcon#read 5, iclass 3, count 0 2006.257.06:10:35.33#ibcon#about to read 6, iclass 3, count 0 2006.257.06:10:35.33#ibcon#read 6, iclass 3, count 0 2006.257.06:10:35.33#ibcon#end of sib2, iclass 3, count 0 2006.257.06:10:35.33#ibcon#*after write, iclass 3, count 0 2006.257.06:10:35.33#ibcon#*before return 0, iclass 3, count 0 2006.257.06:10:35.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:10:35.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:10:35.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:10:35.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:10:35.33$vck44/vb=2,5 2006.257.06:10:35.33#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.06:10:35.33#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.06:10:35.33#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:35.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:10:35.39#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:10:35.39#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:10:35.39#ibcon#enter wrdev, iclass 5, count 2 2006.257.06:10:35.39#ibcon#first serial, iclass 5, count 2 2006.257.06:10:35.39#ibcon#enter sib2, iclass 5, count 2 2006.257.06:10:35.39#ibcon#flushed, iclass 5, count 2 2006.257.06:10:35.39#ibcon#about to write, iclass 5, count 2 2006.257.06:10:35.39#ibcon#wrote, iclass 5, count 2 2006.257.06:10:35.39#ibcon#about to read 3, iclass 5, count 2 2006.257.06:10:35.41#ibcon#read 3, iclass 5, count 2 2006.257.06:10:35.41#ibcon#about to read 4, iclass 5, count 2 2006.257.06:10:35.41#ibcon#read 4, iclass 5, count 2 2006.257.06:10:35.41#ibcon#about to read 5, iclass 5, count 2 2006.257.06:10:35.41#ibcon#read 5, iclass 5, count 2 2006.257.06:10:35.41#ibcon#about to read 6, iclass 5, count 2 2006.257.06:10:35.41#ibcon#read 6, iclass 5, count 2 2006.257.06:10:35.41#ibcon#end of sib2, iclass 5, count 2 2006.257.06:10:35.41#ibcon#*mode == 0, iclass 5, count 2 2006.257.06:10:35.41#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.06:10:35.41#ibcon#[27=AT02-05\r\n] 2006.257.06:10:35.41#ibcon#*before write, iclass 5, count 2 2006.257.06:10:35.41#ibcon#enter sib2, iclass 5, count 2 2006.257.06:10:35.41#ibcon#flushed, iclass 5, count 2 2006.257.06:10:35.41#ibcon#about to write, iclass 5, count 2 2006.257.06:10:35.41#ibcon#wrote, iclass 5, count 2 2006.257.06:10:35.41#ibcon#about to read 3, iclass 5, count 2 2006.257.06:10:35.44#ibcon#read 3, iclass 5, count 2 2006.257.06:10:35.44#ibcon#about to read 4, iclass 5, count 2 2006.257.06:10:35.44#ibcon#read 4, iclass 5, count 2 2006.257.06:10:35.44#ibcon#about to read 5, iclass 5, count 2 2006.257.06:10:35.44#ibcon#read 5, iclass 5, count 2 2006.257.06:10:35.44#ibcon#about to read 6, iclass 5, count 2 2006.257.06:10:35.44#ibcon#read 6, iclass 5, count 2 2006.257.06:10:35.44#ibcon#end of sib2, iclass 5, count 2 2006.257.06:10:35.44#ibcon#*after write, iclass 5, count 2 2006.257.06:10:35.44#ibcon#*before return 0, iclass 5, count 2 2006.257.06:10:35.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:10:35.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:10:35.44#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.06:10:35.44#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:35.44#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:10:35.56#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:10:35.56#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:10:35.56#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:10:35.56#ibcon#first serial, iclass 5, count 0 2006.257.06:10:35.56#ibcon#enter sib2, iclass 5, count 0 2006.257.06:10:35.56#ibcon#flushed, iclass 5, count 0 2006.257.06:10:35.56#ibcon#about to write, iclass 5, count 0 2006.257.06:10:35.56#ibcon#wrote, iclass 5, count 0 2006.257.06:10:35.56#ibcon#about to read 3, iclass 5, count 0 2006.257.06:10:35.58#ibcon#read 3, iclass 5, count 0 2006.257.06:10:35.58#ibcon#about to read 4, iclass 5, count 0 2006.257.06:10:35.58#ibcon#read 4, iclass 5, count 0 2006.257.06:10:35.58#ibcon#about to read 5, iclass 5, count 0 2006.257.06:10:35.58#ibcon#read 5, iclass 5, count 0 2006.257.06:10:35.58#ibcon#about to read 6, iclass 5, count 0 2006.257.06:10:35.58#ibcon#read 6, iclass 5, count 0 2006.257.06:10:35.58#ibcon#end of sib2, iclass 5, count 0 2006.257.06:10:35.58#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:10:35.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:10:35.58#ibcon#[27=USB\r\n] 2006.257.06:10:35.58#ibcon#*before write, iclass 5, count 0 2006.257.06:10:35.58#ibcon#enter sib2, iclass 5, count 0 2006.257.06:10:35.58#ibcon#flushed, iclass 5, count 0 2006.257.06:10:35.58#ibcon#about to write, iclass 5, count 0 2006.257.06:10:35.58#ibcon#wrote, iclass 5, count 0 2006.257.06:10:35.58#ibcon#about to read 3, iclass 5, count 0 2006.257.06:10:35.61#ibcon#read 3, iclass 5, count 0 2006.257.06:10:35.61#ibcon#about to read 4, iclass 5, count 0 2006.257.06:10:35.61#ibcon#read 4, iclass 5, count 0 2006.257.06:10:35.61#ibcon#about to read 5, iclass 5, count 0 2006.257.06:10:35.61#ibcon#read 5, iclass 5, count 0 2006.257.06:10:35.61#ibcon#about to read 6, iclass 5, count 0 2006.257.06:10:35.61#ibcon#read 6, iclass 5, count 0 2006.257.06:10:35.61#ibcon#end of sib2, iclass 5, count 0 2006.257.06:10:35.61#ibcon#*after write, iclass 5, count 0 2006.257.06:10:35.61#ibcon#*before return 0, iclass 5, count 0 2006.257.06:10:35.61#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:10:35.61#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:10:35.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:10:35.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:10:35.61$vck44/vblo=3,649.99 2006.257.06:10:35.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.06:10:35.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.06:10:35.61#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:35.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:35.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:35.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:35.61#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:10:35.61#ibcon#first serial, iclass 7, count 0 2006.257.06:10:35.61#ibcon#enter sib2, iclass 7, count 0 2006.257.06:10:35.61#ibcon#flushed, iclass 7, count 0 2006.257.06:10:35.61#ibcon#about to write, iclass 7, count 0 2006.257.06:10:35.61#ibcon#wrote, iclass 7, count 0 2006.257.06:10:35.61#ibcon#about to read 3, iclass 7, count 0 2006.257.06:10:35.63#ibcon#read 3, iclass 7, count 0 2006.257.06:10:35.63#ibcon#about to read 4, iclass 7, count 0 2006.257.06:10:35.63#ibcon#read 4, iclass 7, count 0 2006.257.06:10:35.63#ibcon#about to read 5, iclass 7, count 0 2006.257.06:10:35.63#ibcon#read 5, iclass 7, count 0 2006.257.06:10:35.63#ibcon#about to read 6, iclass 7, count 0 2006.257.06:10:35.63#ibcon#read 6, iclass 7, count 0 2006.257.06:10:35.63#ibcon#end of sib2, iclass 7, count 0 2006.257.06:10:35.63#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:10:35.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:10:35.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:10:35.63#ibcon#*before write, iclass 7, count 0 2006.257.06:10:35.63#ibcon#enter sib2, iclass 7, count 0 2006.257.06:10:35.63#ibcon#flushed, iclass 7, count 0 2006.257.06:10:35.63#ibcon#about to write, iclass 7, count 0 2006.257.06:10:35.63#ibcon#wrote, iclass 7, count 0 2006.257.06:10:35.63#ibcon#about to read 3, iclass 7, count 0 2006.257.06:10:35.67#ibcon#read 3, iclass 7, count 0 2006.257.06:10:35.67#ibcon#about to read 4, iclass 7, count 0 2006.257.06:10:35.67#ibcon#read 4, iclass 7, count 0 2006.257.06:10:35.67#ibcon#about to read 5, iclass 7, count 0 2006.257.06:10:35.67#ibcon#read 5, iclass 7, count 0 2006.257.06:10:35.67#ibcon#about to read 6, iclass 7, count 0 2006.257.06:10:35.67#ibcon#read 6, iclass 7, count 0 2006.257.06:10:35.67#ibcon#end of sib2, iclass 7, count 0 2006.257.06:10:35.67#ibcon#*after write, iclass 7, count 0 2006.257.06:10:35.67#ibcon#*before return 0, iclass 7, count 0 2006.257.06:10:35.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:35.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:10:35.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:10:35.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:10:35.67$vck44/vb=3,4 2006.257.06:10:35.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.06:10:35.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.06:10:35.67#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:35.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:35.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:35.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:35.73#ibcon#enter wrdev, iclass 11, count 2 2006.257.06:10:35.73#ibcon#first serial, iclass 11, count 2 2006.257.06:10:35.73#ibcon#enter sib2, iclass 11, count 2 2006.257.06:10:35.73#ibcon#flushed, iclass 11, count 2 2006.257.06:10:35.73#ibcon#about to write, iclass 11, count 2 2006.257.06:10:35.73#ibcon#wrote, iclass 11, count 2 2006.257.06:10:35.73#ibcon#about to read 3, iclass 11, count 2 2006.257.06:10:35.75#ibcon#read 3, iclass 11, count 2 2006.257.06:10:35.75#ibcon#about to read 4, iclass 11, count 2 2006.257.06:10:35.75#ibcon#read 4, iclass 11, count 2 2006.257.06:10:35.75#ibcon#about to read 5, iclass 11, count 2 2006.257.06:10:35.75#ibcon#read 5, iclass 11, count 2 2006.257.06:10:35.75#ibcon#about to read 6, iclass 11, count 2 2006.257.06:10:35.75#ibcon#read 6, iclass 11, count 2 2006.257.06:10:35.75#ibcon#end of sib2, iclass 11, count 2 2006.257.06:10:35.75#ibcon#*mode == 0, iclass 11, count 2 2006.257.06:10:35.75#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.06:10:35.75#ibcon#[27=AT03-04\r\n] 2006.257.06:10:35.75#ibcon#*before write, iclass 11, count 2 2006.257.06:10:35.75#ibcon#enter sib2, iclass 11, count 2 2006.257.06:10:35.75#ibcon#flushed, iclass 11, count 2 2006.257.06:10:35.75#ibcon#about to write, iclass 11, count 2 2006.257.06:10:35.75#ibcon#wrote, iclass 11, count 2 2006.257.06:10:35.75#ibcon#about to read 3, iclass 11, count 2 2006.257.06:10:35.78#ibcon#read 3, iclass 11, count 2 2006.257.06:10:35.78#ibcon#about to read 4, iclass 11, count 2 2006.257.06:10:35.78#ibcon#read 4, iclass 11, count 2 2006.257.06:10:35.78#ibcon#about to read 5, iclass 11, count 2 2006.257.06:10:35.78#ibcon#read 5, iclass 11, count 2 2006.257.06:10:35.78#ibcon#about to read 6, iclass 11, count 2 2006.257.06:10:35.78#ibcon#read 6, iclass 11, count 2 2006.257.06:10:35.78#ibcon#end of sib2, iclass 11, count 2 2006.257.06:10:35.78#ibcon#*after write, iclass 11, count 2 2006.257.06:10:35.78#ibcon#*before return 0, iclass 11, count 2 2006.257.06:10:35.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:35.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:10:35.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.06:10:35.78#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:35.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:35.90#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:35.90#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:35.90#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:10:35.90#ibcon#first serial, iclass 11, count 0 2006.257.06:10:35.90#ibcon#enter sib2, iclass 11, count 0 2006.257.06:10:35.90#ibcon#flushed, iclass 11, count 0 2006.257.06:10:35.90#ibcon#about to write, iclass 11, count 0 2006.257.06:10:35.90#ibcon#wrote, iclass 11, count 0 2006.257.06:10:35.90#ibcon#about to read 3, iclass 11, count 0 2006.257.06:10:35.92#ibcon#read 3, iclass 11, count 0 2006.257.06:10:35.92#ibcon#about to read 4, iclass 11, count 0 2006.257.06:10:35.92#ibcon#read 4, iclass 11, count 0 2006.257.06:10:35.92#ibcon#about to read 5, iclass 11, count 0 2006.257.06:10:35.92#ibcon#read 5, iclass 11, count 0 2006.257.06:10:35.92#ibcon#about to read 6, iclass 11, count 0 2006.257.06:10:35.92#ibcon#read 6, iclass 11, count 0 2006.257.06:10:35.92#ibcon#end of sib2, iclass 11, count 0 2006.257.06:10:35.92#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:10:35.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:10:35.92#ibcon#[27=USB\r\n] 2006.257.06:10:35.92#ibcon#*before write, iclass 11, count 0 2006.257.06:10:35.92#ibcon#enter sib2, iclass 11, count 0 2006.257.06:10:35.92#ibcon#flushed, iclass 11, count 0 2006.257.06:10:35.92#ibcon#about to write, iclass 11, count 0 2006.257.06:10:35.92#ibcon#wrote, iclass 11, count 0 2006.257.06:10:35.92#ibcon#about to read 3, iclass 11, count 0 2006.257.06:10:35.95#ibcon#read 3, iclass 11, count 0 2006.257.06:10:35.95#ibcon#about to read 4, iclass 11, count 0 2006.257.06:10:35.95#ibcon#read 4, iclass 11, count 0 2006.257.06:10:35.95#ibcon#about to read 5, iclass 11, count 0 2006.257.06:10:35.95#ibcon#read 5, iclass 11, count 0 2006.257.06:10:35.95#ibcon#about to read 6, iclass 11, count 0 2006.257.06:10:35.95#ibcon#read 6, iclass 11, count 0 2006.257.06:10:35.95#ibcon#end of sib2, iclass 11, count 0 2006.257.06:10:35.95#ibcon#*after write, iclass 11, count 0 2006.257.06:10:35.95#ibcon#*before return 0, iclass 11, count 0 2006.257.06:10:35.95#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:35.95#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:10:35.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:10:35.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:10:35.95$vck44/vblo=4,679.99 2006.257.06:10:35.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.06:10:35.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.06:10:35.95#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:35.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:35.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:35.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:35.95#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:10:35.95#ibcon#first serial, iclass 13, count 0 2006.257.06:10:35.95#ibcon#enter sib2, iclass 13, count 0 2006.257.06:10:35.95#ibcon#flushed, iclass 13, count 0 2006.257.06:10:35.95#ibcon#about to write, iclass 13, count 0 2006.257.06:10:35.95#ibcon#wrote, iclass 13, count 0 2006.257.06:10:35.95#ibcon#about to read 3, iclass 13, count 0 2006.257.06:10:35.97#ibcon#read 3, iclass 13, count 0 2006.257.06:10:35.97#ibcon#about to read 4, iclass 13, count 0 2006.257.06:10:35.97#ibcon#read 4, iclass 13, count 0 2006.257.06:10:35.97#ibcon#about to read 5, iclass 13, count 0 2006.257.06:10:35.97#ibcon#read 5, iclass 13, count 0 2006.257.06:10:35.97#ibcon#about to read 6, iclass 13, count 0 2006.257.06:10:35.97#ibcon#read 6, iclass 13, count 0 2006.257.06:10:35.97#ibcon#end of sib2, iclass 13, count 0 2006.257.06:10:35.97#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:10:35.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:10:35.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:10:35.97#ibcon#*before write, iclass 13, count 0 2006.257.06:10:35.97#ibcon#enter sib2, iclass 13, count 0 2006.257.06:10:35.97#ibcon#flushed, iclass 13, count 0 2006.257.06:10:35.97#ibcon#about to write, iclass 13, count 0 2006.257.06:10:35.97#ibcon#wrote, iclass 13, count 0 2006.257.06:10:35.97#ibcon#about to read 3, iclass 13, count 0 2006.257.06:10:36.01#ibcon#read 3, iclass 13, count 0 2006.257.06:10:36.01#ibcon#about to read 4, iclass 13, count 0 2006.257.06:10:36.01#ibcon#read 4, iclass 13, count 0 2006.257.06:10:36.01#ibcon#about to read 5, iclass 13, count 0 2006.257.06:10:36.01#ibcon#read 5, iclass 13, count 0 2006.257.06:10:36.01#ibcon#about to read 6, iclass 13, count 0 2006.257.06:10:36.01#ibcon#read 6, iclass 13, count 0 2006.257.06:10:36.01#ibcon#end of sib2, iclass 13, count 0 2006.257.06:10:36.01#ibcon#*after write, iclass 13, count 0 2006.257.06:10:36.01#ibcon#*before return 0, iclass 13, count 0 2006.257.06:10:36.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:36.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:10:36.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:10:36.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:10:36.01$vck44/vb=4,5 2006.257.06:10:36.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.06:10:36.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.06:10:36.01#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:36.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:36.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:36.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:36.07#ibcon#enter wrdev, iclass 15, count 2 2006.257.06:10:36.07#ibcon#first serial, iclass 15, count 2 2006.257.06:10:36.07#ibcon#enter sib2, iclass 15, count 2 2006.257.06:10:36.07#ibcon#flushed, iclass 15, count 2 2006.257.06:10:36.07#ibcon#about to write, iclass 15, count 2 2006.257.06:10:36.07#ibcon#wrote, iclass 15, count 2 2006.257.06:10:36.07#ibcon#about to read 3, iclass 15, count 2 2006.257.06:10:36.09#ibcon#read 3, iclass 15, count 2 2006.257.06:10:36.09#ibcon#about to read 4, iclass 15, count 2 2006.257.06:10:36.09#ibcon#read 4, iclass 15, count 2 2006.257.06:10:36.09#ibcon#about to read 5, iclass 15, count 2 2006.257.06:10:36.09#ibcon#read 5, iclass 15, count 2 2006.257.06:10:36.09#ibcon#about to read 6, iclass 15, count 2 2006.257.06:10:36.09#ibcon#read 6, iclass 15, count 2 2006.257.06:10:36.09#ibcon#end of sib2, iclass 15, count 2 2006.257.06:10:36.09#ibcon#*mode == 0, iclass 15, count 2 2006.257.06:10:36.09#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.06:10:36.09#ibcon#[27=AT04-05\r\n] 2006.257.06:10:36.09#ibcon#*before write, iclass 15, count 2 2006.257.06:10:36.09#ibcon#enter sib2, iclass 15, count 2 2006.257.06:10:36.09#ibcon#flushed, iclass 15, count 2 2006.257.06:10:36.09#ibcon#about to write, iclass 15, count 2 2006.257.06:10:36.09#ibcon#wrote, iclass 15, count 2 2006.257.06:10:36.09#ibcon#about to read 3, iclass 15, count 2 2006.257.06:10:36.12#ibcon#read 3, iclass 15, count 2 2006.257.06:10:36.12#ibcon#about to read 4, iclass 15, count 2 2006.257.06:10:36.12#ibcon#read 4, iclass 15, count 2 2006.257.06:10:36.12#ibcon#about to read 5, iclass 15, count 2 2006.257.06:10:36.12#ibcon#read 5, iclass 15, count 2 2006.257.06:10:36.12#ibcon#about to read 6, iclass 15, count 2 2006.257.06:10:36.12#ibcon#read 6, iclass 15, count 2 2006.257.06:10:36.12#ibcon#end of sib2, iclass 15, count 2 2006.257.06:10:36.12#ibcon#*after write, iclass 15, count 2 2006.257.06:10:36.12#ibcon#*before return 0, iclass 15, count 2 2006.257.06:10:36.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:36.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:10:36.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.06:10:36.12#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:36.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:36.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:36.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:36.24#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:10:36.24#ibcon#first serial, iclass 15, count 0 2006.257.06:10:36.24#ibcon#enter sib2, iclass 15, count 0 2006.257.06:10:36.24#ibcon#flushed, iclass 15, count 0 2006.257.06:10:36.24#ibcon#about to write, iclass 15, count 0 2006.257.06:10:36.24#ibcon#wrote, iclass 15, count 0 2006.257.06:10:36.24#ibcon#about to read 3, iclass 15, count 0 2006.257.06:10:36.26#ibcon#read 3, iclass 15, count 0 2006.257.06:10:36.26#ibcon#about to read 4, iclass 15, count 0 2006.257.06:10:36.26#ibcon#read 4, iclass 15, count 0 2006.257.06:10:36.26#ibcon#about to read 5, iclass 15, count 0 2006.257.06:10:36.26#ibcon#read 5, iclass 15, count 0 2006.257.06:10:36.26#ibcon#about to read 6, iclass 15, count 0 2006.257.06:10:36.26#ibcon#read 6, iclass 15, count 0 2006.257.06:10:36.26#ibcon#end of sib2, iclass 15, count 0 2006.257.06:10:36.26#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:10:36.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:10:36.26#ibcon#[27=USB\r\n] 2006.257.06:10:36.26#ibcon#*before write, iclass 15, count 0 2006.257.06:10:36.26#ibcon#enter sib2, iclass 15, count 0 2006.257.06:10:36.26#ibcon#flushed, iclass 15, count 0 2006.257.06:10:36.26#ibcon#about to write, iclass 15, count 0 2006.257.06:10:36.26#ibcon#wrote, iclass 15, count 0 2006.257.06:10:36.26#ibcon#about to read 3, iclass 15, count 0 2006.257.06:10:36.29#ibcon#read 3, iclass 15, count 0 2006.257.06:10:36.29#ibcon#about to read 4, iclass 15, count 0 2006.257.06:10:36.29#ibcon#read 4, iclass 15, count 0 2006.257.06:10:36.29#ibcon#about to read 5, iclass 15, count 0 2006.257.06:10:36.29#ibcon#read 5, iclass 15, count 0 2006.257.06:10:36.29#ibcon#about to read 6, iclass 15, count 0 2006.257.06:10:36.29#ibcon#read 6, iclass 15, count 0 2006.257.06:10:36.29#ibcon#end of sib2, iclass 15, count 0 2006.257.06:10:36.29#ibcon#*after write, iclass 15, count 0 2006.257.06:10:36.29#ibcon#*before return 0, iclass 15, count 0 2006.257.06:10:36.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:36.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:10:36.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:10:36.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:10:36.29$vck44/vblo=5,709.99 2006.257.06:10:36.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.06:10:36.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.06:10:36.29#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:36.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:36.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:36.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:36.29#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:10:36.29#ibcon#first serial, iclass 17, count 0 2006.257.06:10:36.29#ibcon#enter sib2, iclass 17, count 0 2006.257.06:10:36.29#ibcon#flushed, iclass 17, count 0 2006.257.06:10:36.29#ibcon#about to write, iclass 17, count 0 2006.257.06:10:36.29#ibcon#wrote, iclass 17, count 0 2006.257.06:10:36.29#ibcon#about to read 3, iclass 17, count 0 2006.257.06:10:36.31#ibcon#read 3, iclass 17, count 0 2006.257.06:10:36.31#ibcon#about to read 4, iclass 17, count 0 2006.257.06:10:36.31#ibcon#read 4, iclass 17, count 0 2006.257.06:10:36.31#ibcon#about to read 5, iclass 17, count 0 2006.257.06:10:36.31#ibcon#read 5, iclass 17, count 0 2006.257.06:10:36.31#ibcon#about to read 6, iclass 17, count 0 2006.257.06:10:36.31#ibcon#read 6, iclass 17, count 0 2006.257.06:10:36.31#ibcon#end of sib2, iclass 17, count 0 2006.257.06:10:36.31#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:10:36.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:10:36.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:10:36.31#ibcon#*before write, iclass 17, count 0 2006.257.06:10:36.31#ibcon#enter sib2, iclass 17, count 0 2006.257.06:10:36.31#ibcon#flushed, iclass 17, count 0 2006.257.06:10:36.31#ibcon#about to write, iclass 17, count 0 2006.257.06:10:36.31#ibcon#wrote, iclass 17, count 0 2006.257.06:10:36.31#ibcon#about to read 3, iclass 17, count 0 2006.257.06:10:36.35#ibcon#read 3, iclass 17, count 0 2006.257.06:10:36.35#ibcon#about to read 4, iclass 17, count 0 2006.257.06:10:36.35#ibcon#read 4, iclass 17, count 0 2006.257.06:10:36.35#ibcon#about to read 5, iclass 17, count 0 2006.257.06:10:36.35#ibcon#read 5, iclass 17, count 0 2006.257.06:10:36.35#ibcon#about to read 6, iclass 17, count 0 2006.257.06:10:36.35#ibcon#read 6, iclass 17, count 0 2006.257.06:10:36.35#ibcon#end of sib2, iclass 17, count 0 2006.257.06:10:36.35#ibcon#*after write, iclass 17, count 0 2006.257.06:10:36.35#ibcon#*before return 0, iclass 17, count 0 2006.257.06:10:36.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:36.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:10:36.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:10:36.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:10:36.35$vck44/vb=5,4 2006.257.06:10:36.35#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.06:10:36.35#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.06:10:36.35#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:36.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:36.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:36.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:36.41#ibcon#enter wrdev, iclass 19, count 2 2006.257.06:10:36.41#ibcon#first serial, iclass 19, count 2 2006.257.06:10:36.41#ibcon#enter sib2, iclass 19, count 2 2006.257.06:10:36.41#ibcon#flushed, iclass 19, count 2 2006.257.06:10:36.41#ibcon#about to write, iclass 19, count 2 2006.257.06:10:36.41#ibcon#wrote, iclass 19, count 2 2006.257.06:10:36.41#ibcon#about to read 3, iclass 19, count 2 2006.257.06:10:36.43#ibcon#read 3, iclass 19, count 2 2006.257.06:10:36.43#ibcon#about to read 4, iclass 19, count 2 2006.257.06:10:36.43#ibcon#read 4, iclass 19, count 2 2006.257.06:10:36.43#ibcon#about to read 5, iclass 19, count 2 2006.257.06:10:36.43#ibcon#read 5, iclass 19, count 2 2006.257.06:10:36.43#ibcon#about to read 6, iclass 19, count 2 2006.257.06:10:36.43#ibcon#read 6, iclass 19, count 2 2006.257.06:10:36.43#ibcon#end of sib2, iclass 19, count 2 2006.257.06:10:36.43#ibcon#*mode == 0, iclass 19, count 2 2006.257.06:10:36.43#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.06:10:36.43#ibcon#[27=AT05-04\r\n] 2006.257.06:10:36.43#ibcon#*before write, iclass 19, count 2 2006.257.06:10:36.43#ibcon#enter sib2, iclass 19, count 2 2006.257.06:10:36.43#ibcon#flushed, iclass 19, count 2 2006.257.06:10:36.43#ibcon#about to write, iclass 19, count 2 2006.257.06:10:36.43#ibcon#wrote, iclass 19, count 2 2006.257.06:10:36.43#ibcon#about to read 3, iclass 19, count 2 2006.257.06:10:36.46#ibcon#read 3, iclass 19, count 2 2006.257.06:10:36.46#ibcon#about to read 4, iclass 19, count 2 2006.257.06:10:36.46#ibcon#read 4, iclass 19, count 2 2006.257.06:10:36.46#ibcon#about to read 5, iclass 19, count 2 2006.257.06:10:36.46#ibcon#read 5, iclass 19, count 2 2006.257.06:10:36.46#ibcon#about to read 6, iclass 19, count 2 2006.257.06:10:36.46#ibcon#read 6, iclass 19, count 2 2006.257.06:10:36.46#ibcon#end of sib2, iclass 19, count 2 2006.257.06:10:36.46#ibcon#*after write, iclass 19, count 2 2006.257.06:10:36.46#ibcon#*before return 0, iclass 19, count 2 2006.257.06:10:36.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:36.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:10:36.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.06:10:36.46#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:36.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:36.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:36.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:36.58#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:10:36.58#ibcon#first serial, iclass 19, count 0 2006.257.06:10:36.58#ibcon#enter sib2, iclass 19, count 0 2006.257.06:10:36.58#ibcon#flushed, iclass 19, count 0 2006.257.06:10:36.58#ibcon#about to write, iclass 19, count 0 2006.257.06:10:36.58#ibcon#wrote, iclass 19, count 0 2006.257.06:10:36.58#ibcon#about to read 3, iclass 19, count 0 2006.257.06:10:36.60#ibcon#read 3, iclass 19, count 0 2006.257.06:10:36.60#ibcon#about to read 4, iclass 19, count 0 2006.257.06:10:36.60#ibcon#read 4, iclass 19, count 0 2006.257.06:10:36.60#ibcon#about to read 5, iclass 19, count 0 2006.257.06:10:36.60#ibcon#read 5, iclass 19, count 0 2006.257.06:10:36.60#ibcon#about to read 6, iclass 19, count 0 2006.257.06:10:36.60#ibcon#read 6, iclass 19, count 0 2006.257.06:10:36.60#ibcon#end of sib2, iclass 19, count 0 2006.257.06:10:36.60#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:10:36.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:10:36.60#ibcon#[27=USB\r\n] 2006.257.06:10:36.60#ibcon#*before write, iclass 19, count 0 2006.257.06:10:36.60#ibcon#enter sib2, iclass 19, count 0 2006.257.06:10:36.60#ibcon#flushed, iclass 19, count 0 2006.257.06:10:36.60#ibcon#about to write, iclass 19, count 0 2006.257.06:10:36.60#ibcon#wrote, iclass 19, count 0 2006.257.06:10:36.60#ibcon#about to read 3, iclass 19, count 0 2006.257.06:10:36.63#ibcon#read 3, iclass 19, count 0 2006.257.06:10:36.63#ibcon#about to read 4, iclass 19, count 0 2006.257.06:10:36.63#ibcon#read 4, iclass 19, count 0 2006.257.06:10:36.63#ibcon#about to read 5, iclass 19, count 0 2006.257.06:10:36.63#ibcon#read 5, iclass 19, count 0 2006.257.06:10:36.63#ibcon#about to read 6, iclass 19, count 0 2006.257.06:10:36.63#ibcon#read 6, iclass 19, count 0 2006.257.06:10:36.63#ibcon#end of sib2, iclass 19, count 0 2006.257.06:10:36.63#ibcon#*after write, iclass 19, count 0 2006.257.06:10:36.63#ibcon#*before return 0, iclass 19, count 0 2006.257.06:10:36.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:36.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:10:36.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:10:36.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:10:36.63$vck44/vblo=6,719.99 2006.257.06:10:36.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.06:10:36.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.06:10:36.63#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:36.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:36.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:36.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:36.63#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:10:36.63#ibcon#first serial, iclass 21, count 0 2006.257.06:10:36.63#ibcon#enter sib2, iclass 21, count 0 2006.257.06:10:36.63#ibcon#flushed, iclass 21, count 0 2006.257.06:10:36.63#ibcon#about to write, iclass 21, count 0 2006.257.06:10:36.63#ibcon#wrote, iclass 21, count 0 2006.257.06:10:36.63#ibcon#about to read 3, iclass 21, count 0 2006.257.06:10:36.65#ibcon#read 3, iclass 21, count 0 2006.257.06:10:36.65#ibcon#about to read 4, iclass 21, count 0 2006.257.06:10:36.65#ibcon#read 4, iclass 21, count 0 2006.257.06:10:36.65#ibcon#about to read 5, iclass 21, count 0 2006.257.06:10:36.65#ibcon#read 5, iclass 21, count 0 2006.257.06:10:36.65#ibcon#about to read 6, iclass 21, count 0 2006.257.06:10:36.65#ibcon#read 6, iclass 21, count 0 2006.257.06:10:36.65#ibcon#end of sib2, iclass 21, count 0 2006.257.06:10:36.65#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:10:36.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:10:36.65#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:10:36.65#ibcon#*before write, iclass 21, count 0 2006.257.06:10:36.65#ibcon#enter sib2, iclass 21, count 0 2006.257.06:10:36.65#ibcon#flushed, iclass 21, count 0 2006.257.06:10:36.65#ibcon#about to write, iclass 21, count 0 2006.257.06:10:36.65#ibcon#wrote, iclass 21, count 0 2006.257.06:10:36.65#ibcon#about to read 3, iclass 21, count 0 2006.257.06:10:36.69#ibcon#read 3, iclass 21, count 0 2006.257.06:10:36.69#ibcon#about to read 4, iclass 21, count 0 2006.257.06:10:36.69#ibcon#read 4, iclass 21, count 0 2006.257.06:10:36.69#ibcon#about to read 5, iclass 21, count 0 2006.257.06:10:36.69#ibcon#read 5, iclass 21, count 0 2006.257.06:10:36.69#ibcon#about to read 6, iclass 21, count 0 2006.257.06:10:36.69#ibcon#read 6, iclass 21, count 0 2006.257.06:10:36.69#ibcon#end of sib2, iclass 21, count 0 2006.257.06:10:36.69#ibcon#*after write, iclass 21, count 0 2006.257.06:10:36.69#ibcon#*before return 0, iclass 21, count 0 2006.257.06:10:36.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:36.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:10:36.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:10:36.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:10:36.69$vck44/vb=6,4 2006.257.06:10:36.69#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.06:10:36.69#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.06:10:36.69#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:36.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:36.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:36.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:36.75#ibcon#enter wrdev, iclass 23, count 2 2006.257.06:10:36.75#ibcon#first serial, iclass 23, count 2 2006.257.06:10:36.75#ibcon#enter sib2, iclass 23, count 2 2006.257.06:10:36.75#ibcon#flushed, iclass 23, count 2 2006.257.06:10:36.75#ibcon#about to write, iclass 23, count 2 2006.257.06:10:36.75#ibcon#wrote, iclass 23, count 2 2006.257.06:10:36.75#ibcon#about to read 3, iclass 23, count 2 2006.257.06:10:36.77#ibcon#read 3, iclass 23, count 2 2006.257.06:10:36.77#ibcon#about to read 4, iclass 23, count 2 2006.257.06:10:36.77#ibcon#read 4, iclass 23, count 2 2006.257.06:10:36.77#ibcon#about to read 5, iclass 23, count 2 2006.257.06:10:36.77#ibcon#read 5, iclass 23, count 2 2006.257.06:10:36.77#ibcon#about to read 6, iclass 23, count 2 2006.257.06:10:36.77#ibcon#read 6, iclass 23, count 2 2006.257.06:10:36.77#ibcon#end of sib2, iclass 23, count 2 2006.257.06:10:36.77#ibcon#*mode == 0, iclass 23, count 2 2006.257.06:10:36.77#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.06:10:36.77#ibcon#[27=AT06-04\r\n] 2006.257.06:10:36.77#ibcon#*before write, iclass 23, count 2 2006.257.06:10:36.77#ibcon#enter sib2, iclass 23, count 2 2006.257.06:10:36.77#ibcon#flushed, iclass 23, count 2 2006.257.06:10:36.77#ibcon#about to write, iclass 23, count 2 2006.257.06:10:36.77#ibcon#wrote, iclass 23, count 2 2006.257.06:10:36.77#ibcon#about to read 3, iclass 23, count 2 2006.257.06:10:36.80#ibcon#read 3, iclass 23, count 2 2006.257.06:10:36.80#ibcon#about to read 4, iclass 23, count 2 2006.257.06:10:36.80#ibcon#read 4, iclass 23, count 2 2006.257.06:10:36.80#ibcon#about to read 5, iclass 23, count 2 2006.257.06:10:36.80#ibcon#read 5, iclass 23, count 2 2006.257.06:10:36.80#ibcon#about to read 6, iclass 23, count 2 2006.257.06:10:36.80#ibcon#read 6, iclass 23, count 2 2006.257.06:10:36.80#ibcon#end of sib2, iclass 23, count 2 2006.257.06:10:36.80#ibcon#*after write, iclass 23, count 2 2006.257.06:10:36.80#ibcon#*before return 0, iclass 23, count 2 2006.257.06:10:36.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:36.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:10:36.80#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.06:10:36.80#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:36.80#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:36.92#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:36.92#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:36.92#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:10:36.92#ibcon#first serial, iclass 23, count 0 2006.257.06:10:36.92#ibcon#enter sib2, iclass 23, count 0 2006.257.06:10:36.92#ibcon#flushed, iclass 23, count 0 2006.257.06:10:36.92#ibcon#about to write, iclass 23, count 0 2006.257.06:10:36.92#ibcon#wrote, iclass 23, count 0 2006.257.06:10:36.92#ibcon#about to read 3, iclass 23, count 0 2006.257.06:10:36.94#ibcon#read 3, iclass 23, count 0 2006.257.06:10:36.94#ibcon#about to read 4, iclass 23, count 0 2006.257.06:10:36.94#ibcon#read 4, iclass 23, count 0 2006.257.06:10:36.94#ibcon#about to read 5, iclass 23, count 0 2006.257.06:10:36.94#ibcon#read 5, iclass 23, count 0 2006.257.06:10:36.94#ibcon#about to read 6, iclass 23, count 0 2006.257.06:10:36.94#ibcon#read 6, iclass 23, count 0 2006.257.06:10:36.94#ibcon#end of sib2, iclass 23, count 0 2006.257.06:10:36.94#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:10:36.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:10:36.94#ibcon#[27=USB\r\n] 2006.257.06:10:36.94#ibcon#*before write, iclass 23, count 0 2006.257.06:10:36.94#ibcon#enter sib2, iclass 23, count 0 2006.257.06:10:36.94#ibcon#flushed, iclass 23, count 0 2006.257.06:10:36.94#ibcon#about to write, iclass 23, count 0 2006.257.06:10:36.94#ibcon#wrote, iclass 23, count 0 2006.257.06:10:36.94#ibcon#about to read 3, iclass 23, count 0 2006.257.06:10:36.97#ibcon#read 3, iclass 23, count 0 2006.257.06:10:36.97#ibcon#about to read 4, iclass 23, count 0 2006.257.06:10:36.97#ibcon#read 4, iclass 23, count 0 2006.257.06:10:36.97#ibcon#about to read 5, iclass 23, count 0 2006.257.06:10:36.97#ibcon#read 5, iclass 23, count 0 2006.257.06:10:36.97#ibcon#about to read 6, iclass 23, count 0 2006.257.06:10:36.97#ibcon#read 6, iclass 23, count 0 2006.257.06:10:36.97#ibcon#end of sib2, iclass 23, count 0 2006.257.06:10:36.97#ibcon#*after write, iclass 23, count 0 2006.257.06:10:36.97#ibcon#*before return 0, iclass 23, count 0 2006.257.06:10:36.97#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:36.97#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:10:36.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:10:36.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:10:36.97$vck44/vblo=7,734.99 2006.257.06:10:36.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.06:10:36.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.06:10:36.97#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:36.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:36.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:36.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:36.97#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:10:36.97#ibcon#first serial, iclass 25, count 0 2006.257.06:10:36.97#ibcon#enter sib2, iclass 25, count 0 2006.257.06:10:36.97#ibcon#flushed, iclass 25, count 0 2006.257.06:10:36.97#ibcon#about to write, iclass 25, count 0 2006.257.06:10:36.97#ibcon#wrote, iclass 25, count 0 2006.257.06:10:36.97#ibcon#about to read 3, iclass 25, count 0 2006.257.06:10:36.99#ibcon#read 3, iclass 25, count 0 2006.257.06:10:36.99#ibcon#about to read 4, iclass 25, count 0 2006.257.06:10:36.99#ibcon#read 4, iclass 25, count 0 2006.257.06:10:36.99#ibcon#about to read 5, iclass 25, count 0 2006.257.06:10:36.99#ibcon#read 5, iclass 25, count 0 2006.257.06:10:36.99#ibcon#about to read 6, iclass 25, count 0 2006.257.06:10:36.99#ibcon#read 6, iclass 25, count 0 2006.257.06:10:36.99#ibcon#end of sib2, iclass 25, count 0 2006.257.06:10:36.99#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:10:36.99#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:10:36.99#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:10:36.99#ibcon#*before write, iclass 25, count 0 2006.257.06:10:36.99#ibcon#enter sib2, iclass 25, count 0 2006.257.06:10:36.99#ibcon#flushed, iclass 25, count 0 2006.257.06:10:36.99#ibcon#about to write, iclass 25, count 0 2006.257.06:10:36.99#ibcon#wrote, iclass 25, count 0 2006.257.06:10:36.99#ibcon#about to read 3, iclass 25, count 0 2006.257.06:10:37.03#ibcon#read 3, iclass 25, count 0 2006.257.06:10:37.03#ibcon#about to read 4, iclass 25, count 0 2006.257.06:10:37.03#ibcon#read 4, iclass 25, count 0 2006.257.06:10:37.03#ibcon#about to read 5, iclass 25, count 0 2006.257.06:10:37.03#ibcon#read 5, iclass 25, count 0 2006.257.06:10:37.03#ibcon#about to read 6, iclass 25, count 0 2006.257.06:10:37.03#ibcon#read 6, iclass 25, count 0 2006.257.06:10:37.03#ibcon#end of sib2, iclass 25, count 0 2006.257.06:10:37.03#ibcon#*after write, iclass 25, count 0 2006.257.06:10:37.03#ibcon#*before return 0, iclass 25, count 0 2006.257.06:10:37.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:37.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:10:37.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:10:37.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:10:37.03$vck44/vb=7,4 2006.257.06:10:37.03#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.06:10:37.03#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.06:10:37.03#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:37.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:37.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:37.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:37.09#ibcon#enter wrdev, iclass 27, count 2 2006.257.06:10:37.09#ibcon#first serial, iclass 27, count 2 2006.257.06:10:37.09#ibcon#enter sib2, iclass 27, count 2 2006.257.06:10:37.09#ibcon#flushed, iclass 27, count 2 2006.257.06:10:37.09#ibcon#about to write, iclass 27, count 2 2006.257.06:10:37.09#ibcon#wrote, iclass 27, count 2 2006.257.06:10:37.09#ibcon#about to read 3, iclass 27, count 2 2006.257.06:10:37.11#ibcon#read 3, iclass 27, count 2 2006.257.06:10:37.11#ibcon#about to read 4, iclass 27, count 2 2006.257.06:10:37.11#ibcon#read 4, iclass 27, count 2 2006.257.06:10:37.11#ibcon#about to read 5, iclass 27, count 2 2006.257.06:10:37.11#ibcon#read 5, iclass 27, count 2 2006.257.06:10:37.11#ibcon#about to read 6, iclass 27, count 2 2006.257.06:10:37.11#ibcon#read 6, iclass 27, count 2 2006.257.06:10:37.11#ibcon#end of sib2, iclass 27, count 2 2006.257.06:10:37.11#ibcon#*mode == 0, iclass 27, count 2 2006.257.06:10:37.11#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.06:10:37.11#ibcon#[27=AT07-04\r\n] 2006.257.06:10:37.11#ibcon#*before write, iclass 27, count 2 2006.257.06:10:37.11#ibcon#enter sib2, iclass 27, count 2 2006.257.06:10:37.11#ibcon#flushed, iclass 27, count 2 2006.257.06:10:37.11#ibcon#about to write, iclass 27, count 2 2006.257.06:10:37.11#ibcon#wrote, iclass 27, count 2 2006.257.06:10:37.11#ibcon#about to read 3, iclass 27, count 2 2006.257.06:10:37.14#ibcon#read 3, iclass 27, count 2 2006.257.06:10:37.14#ibcon#about to read 4, iclass 27, count 2 2006.257.06:10:37.14#ibcon#read 4, iclass 27, count 2 2006.257.06:10:37.14#ibcon#about to read 5, iclass 27, count 2 2006.257.06:10:37.14#ibcon#read 5, iclass 27, count 2 2006.257.06:10:37.14#ibcon#about to read 6, iclass 27, count 2 2006.257.06:10:37.14#ibcon#read 6, iclass 27, count 2 2006.257.06:10:37.14#ibcon#end of sib2, iclass 27, count 2 2006.257.06:10:37.14#ibcon#*after write, iclass 27, count 2 2006.257.06:10:37.14#ibcon#*before return 0, iclass 27, count 2 2006.257.06:10:37.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:37.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:10:37.14#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.06:10:37.14#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:37.14#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:37.26#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:37.26#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:37.26#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:10:37.26#ibcon#first serial, iclass 27, count 0 2006.257.06:10:37.26#ibcon#enter sib2, iclass 27, count 0 2006.257.06:10:37.26#ibcon#flushed, iclass 27, count 0 2006.257.06:10:37.26#ibcon#about to write, iclass 27, count 0 2006.257.06:10:37.26#ibcon#wrote, iclass 27, count 0 2006.257.06:10:37.26#ibcon#about to read 3, iclass 27, count 0 2006.257.06:10:37.28#ibcon#read 3, iclass 27, count 0 2006.257.06:10:37.28#ibcon#about to read 4, iclass 27, count 0 2006.257.06:10:37.28#ibcon#read 4, iclass 27, count 0 2006.257.06:10:37.28#ibcon#about to read 5, iclass 27, count 0 2006.257.06:10:37.28#ibcon#read 5, iclass 27, count 0 2006.257.06:10:37.28#ibcon#about to read 6, iclass 27, count 0 2006.257.06:10:37.28#ibcon#read 6, iclass 27, count 0 2006.257.06:10:37.28#ibcon#end of sib2, iclass 27, count 0 2006.257.06:10:37.28#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:10:37.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:10:37.28#ibcon#[27=USB\r\n] 2006.257.06:10:37.28#ibcon#*before write, iclass 27, count 0 2006.257.06:10:37.28#ibcon#enter sib2, iclass 27, count 0 2006.257.06:10:37.28#ibcon#flushed, iclass 27, count 0 2006.257.06:10:37.28#ibcon#about to write, iclass 27, count 0 2006.257.06:10:37.28#ibcon#wrote, iclass 27, count 0 2006.257.06:10:37.28#ibcon#about to read 3, iclass 27, count 0 2006.257.06:10:37.31#ibcon#read 3, iclass 27, count 0 2006.257.06:10:37.31#ibcon#about to read 4, iclass 27, count 0 2006.257.06:10:37.31#ibcon#read 4, iclass 27, count 0 2006.257.06:10:37.31#ibcon#about to read 5, iclass 27, count 0 2006.257.06:10:37.31#ibcon#read 5, iclass 27, count 0 2006.257.06:10:37.31#ibcon#about to read 6, iclass 27, count 0 2006.257.06:10:37.31#ibcon#read 6, iclass 27, count 0 2006.257.06:10:37.31#ibcon#end of sib2, iclass 27, count 0 2006.257.06:10:37.31#ibcon#*after write, iclass 27, count 0 2006.257.06:10:37.31#ibcon#*before return 0, iclass 27, count 0 2006.257.06:10:37.31#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:37.31#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:10:37.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:10:37.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:10:37.31$vck44/vblo=8,744.99 2006.257.06:10:37.31#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.06:10:37.31#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.06:10:37.31#ibcon#ireg 17 cls_cnt 0 2006.257.06:10:37.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:37.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:37.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:37.31#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:10:37.31#ibcon#first serial, iclass 29, count 0 2006.257.06:10:37.31#ibcon#enter sib2, iclass 29, count 0 2006.257.06:10:37.31#ibcon#flushed, iclass 29, count 0 2006.257.06:10:37.31#ibcon#about to write, iclass 29, count 0 2006.257.06:10:37.31#ibcon#wrote, iclass 29, count 0 2006.257.06:10:37.31#ibcon#about to read 3, iclass 29, count 0 2006.257.06:10:37.33#ibcon#read 3, iclass 29, count 0 2006.257.06:10:37.33#ibcon#about to read 4, iclass 29, count 0 2006.257.06:10:37.33#ibcon#read 4, iclass 29, count 0 2006.257.06:10:37.33#ibcon#about to read 5, iclass 29, count 0 2006.257.06:10:37.33#ibcon#read 5, iclass 29, count 0 2006.257.06:10:37.33#ibcon#about to read 6, iclass 29, count 0 2006.257.06:10:37.33#ibcon#read 6, iclass 29, count 0 2006.257.06:10:37.33#ibcon#end of sib2, iclass 29, count 0 2006.257.06:10:37.33#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:10:37.33#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:10:37.33#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:10:37.33#ibcon#*before write, iclass 29, count 0 2006.257.06:10:37.33#ibcon#enter sib2, iclass 29, count 0 2006.257.06:10:37.33#ibcon#flushed, iclass 29, count 0 2006.257.06:10:37.33#ibcon#about to write, iclass 29, count 0 2006.257.06:10:37.33#ibcon#wrote, iclass 29, count 0 2006.257.06:10:37.33#ibcon#about to read 3, iclass 29, count 0 2006.257.06:10:37.37#ibcon#read 3, iclass 29, count 0 2006.257.06:10:37.37#ibcon#about to read 4, iclass 29, count 0 2006.257.06:10:37.37#ibcon#read 4, iclass 29, count 0 2006.257.06:10:37.37#ibcon#about to read 5, iclass 29, count 0 2006.257.06:10:37.37#ibcon#read 5, iclass 29, count 0 2006.257.06:10:37.37#ibcon#about to read 6, iclass 29, count 0 2006.257.06:10:37.37#ibcon#read 6, iclass 29, count 0 2006.257.06:10:37.37#ibcon#end of sib2, iclass 29, count 0 2006.257.06:10:37.37#ibcon#*after write, iclass 29, count 0 2006.257.06:10:37.37#ibcon#*before return 0, iclass 29, count 0 2006.257.06:10:37.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:37.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:10:37.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:10:37.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:10:37.37$vck44/vb=8,4 2006.257.06:10:37.37#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.06:10:37.37#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.06:10:37.37#ibcon#ireg 11 cls_cnt 2 2006.257.06:10:37.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:37.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:37.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:37.43#ibcon#enter wrdev, iclass 31, count 2 2006.257.06:10:37.43#ibcon#first serial, iclass 31, count 2 2006.257.06:10:37.43#ibcon#enter sib2, iclass 31, count 2 2006.257.06:10:37.43#ibcon#flushed, iclass 31, count 2 2006.257.06:10:37.43#ibcon#about to write, iclass 31, count 2 2006.257.06:10:37.43#ibcon#wrote, iclass 31, count 2 2006.257.06:10:37.43#ibcon#about to read 3, iclass 31, count 2 2006.257.06:10:37.45#ibcon#read 3, iclass 31, count 2 2006.257.06:10:37.45#ibcon#about to read 4, iclass 31, count 2 2006.257.06:10:37.45#ibcon#read 4, iclass 31, count 2 2006.257.06:10:37.45#ibcon#about to read 5, iclass 31, count 2 2006.257.06:10:37.45#ibcon#read 5, iclass 31, count 2 2006.257.06:10:37.45#ibcon#about to read 6, iclass 31, count 2 2006.257.06:10:37.45#ibcon#read 6, iclass 31, count 2 2006.257.06:10:37.45#ibcon#end of sib2, iclass 31, count 2 2006.257.06:10:37.45#ibcon#*mode == 0, iclass 31, count 2 2006.257.06:10:37.45#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.06:10:37.45#ibcon#[27=AT08-04\r\n] 2006.257.06:10:37.45#ibcon#*before write, iclass 31, count 2 2006.257.06:10:37.45#ibcon#enter sib2, iclass 31, count 2 2006.257.06:10:37.45#ibcon#flushed, iclass 31, count 2 2006.257.06:10:37.45#ibcon#about to write, iclass 31, count 2 2006.257.06:10:37.45#ibcon#wrote, iclass 31, count 2 2006.257.06:10:37.45#ibcon#about to read 3, iclass 31, count 2 2006.257.06:10:37.48#ibcon#read 3, iclass 31, count 2 2006.257.06:10:37.48#ibcon#about to read 4, iclass 31, count 2 2006.257.06:10:37.48#ibcon#read 4, iclass 31, count 2 2006.257.06:10:37.48#ibcon#about to read 5, iclass 31, count 2 2006.257.06:10:37.48#ibcon#read 5, iclass 31, count 2 2006.257.06:10:37.48#ibcon#about to read 6, iclass 31, count 2 2006.257.06:10:37.48#ibcon#read 6, iclass 31, count 2 2006.257.06:10:37.48#ibcon#end of sib2, iclass 31, count 2 2006.257.06:10:37.48#ibcon#*after write, iclass 31, count 2 2006.257.06:10:37.48#ibcon#*before return 0, iclass 31, count 2 2006.257.06:10:37.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:37.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:10:37.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.06:10:37.48#ibcon#ireg 7 cls_cnt 0 2006.257.06:10:37.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:37.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:37.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:37.60#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:10:37.60#ibcon#first serial, iclass 31, count 0 2006.257.06:10:37.60#ibcon#enter sib2, iclass 31, count 0 2006.257.06:10:37.60#ibcon#flushed, iclass 31, count 0 2006.257.06:10:37.60#ibcon#about to write, iclass 31, count 0 2006.257.06:10:37.60#ibcon#wrote, iclass 31, count 0 2006.257.06:10:37.60#ibcon#about to read 3, iclass 31, count 0 2006.257.06:10:37.62#ibcon#read 3, iclass 31, count 0 2006.257.06:10:37.62#ibcon#about to read 4, iclass 31, count 0 2006.257.06:10:37.62#ibcon#read 4, iclass 31, count 0 2006.257.06:10:37.62#ibcon#about to read 5, iclass 31, count 0 2006.257.06:10:37.62#ibcon#read 5, iclass 31, count 0 2006.257.06:10:37.62#ibcon#about to read 6, iclass 31, count 0 2006.257.06:10:37.62#ibcon#read 6, iclass 31, count 0 2006.257.06:10:37.62#ibcon#end of sib2, iclass 31, count 0 2006.257.06:10:37.62#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:10:37.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:10:37.62#ibcon#[27=USB\r\n] 2006.257.06:10:37.62#ibcon#*before write, iclass 31, count 0 2006.257.06:10:37.62#ibcon#enter sib2, iclass 31, count 0 2006.257.06:10:37.62#ibcon#flushed, iclass 31, count 0 2006.257.06:10:37.62#ibcon#about to write, iclass 31, count 0 2006.257.06:10:37.62#ibcon#wrote, iclass 31, count 0 2006.257.06:10:37.62#ibcon#about to read 3, iclass 31, count 0 2006.257.06:10:37.65#ibcon#read 3, iclass 31, count 0 2006.257.06:10:37.65#ibcon#about to read 4, iclass 31, count 0 2006.257.06:10:37.65#ibcon#read 4, iclass 31, count 0 2006.257.06:10:37.65#ibcon#about to read 5, iclass 31, count 0 2006.257.06:10:37.65#ibcon#read 5, iclass 31, count 0 2006.257.06:10:37.65#ibcon#about to read 6, iclass 31, count 0 2006.257.06:10:37.65#ibcon#read 6, iclass 31, count 0 2006.257.06:10:37.65#ibcon#end of sib2, iclass 31, count 0 2006.257.06:10:37.65#ibcon#*after write, iclass 31, count 0 2006.257.06:10:37.65#ibcon#*before return 0, iclass 31, count 0 2006.257.06:10:37.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:37.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:10:37.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:10:37.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:10:37.65$vck44/vabw=wide 2006.257.06:10:37.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.06:10:37.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.06:10:37.65#ibcon#ireg 8 cls_cnt 0 2006.257.06:10:37.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:37.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:37.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:37.65#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:10:37.65#ibcon#first serial, iclass 33, count 0 2006.257.06:10:37.65#ibcon#enter sib2, iclass 33, count 0 2006.257.06:10:37.65#ibcon#flushed, iclass 33, count 0 2006.257.06:10:37.65#ibcon#about to write, iclass 33, count 0 2006.257.06:10:37.65#ibcon#wrote, iclass 33, count 0 2006.257.06:10:37.65#ibcon#about to read 3, iclass 33, count 0 2006.257.06:10:37.67#ibcon#read 3, iclass 33, count 0 2006.257.06:10:37.67#ibcon#about to read 4, iclass 33, count 0 2006.257.06:10:37.67#ibcon#read 4, iclass 33, count 0 2006.257.06:10:37.67#ibcon#about to read 5, iclass 33, count 0 2006.257.06:10:37.67#ibcon#read 5, iclass 33, count 0 2006.257.06:10:37.67#ibcon#about to read 6, iclass 33, count 0 2006.257.06:10:37.67#ibcon#read 6, iclass 33, count 0 2006.257.06:10:37.67#ibcon#end of sib2, iclass 33, count 0 2006.257.06:10:37.67#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:10:37.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:10:37.67#ibcon#[25=BW32\r\n] 2006.257.06:10:37.67#ibcon#*before write, iclass 33, count 0 2006.257.06:10:37.67#ibcon#enter sib2, iclass 33, count 0 2006.257.06:10:37.67#ibcon#flushed, iclass 33, count 0 2006.257.06:10:37.67#ibcon#about to write, iclass 33, count 0 2006.257.06:10:37.67#ibcon#wrote, iclass 33, count 0 2006.257.06:10:37.67#ibcon#about to read 3, iclass 33, count 0 2006.257.06:10:37.70#ibcon#read 3, iclass 33, count 0 2006.257.06:10:37.70#ibcon#about to read 4, iclass 33, count 0 2006.257.06:10:37.70#ibcon#read 4, iclass 33, count 0 2006.257.06:10:37.70#ibcon#about to read 5, iclass 33, count 0 2006.257.06:10:37.70#ibcon#read 5, iclass 33, count 0 2006.257.06:10:37.70#ibcon#about to read 6, iclass 33, count 0 2006.257.06:10:37.70#ibcon#read 6, iclass 33, count 0 2006.257.06:10:37.70#ibcon#end of sib2, iclass 33, count 0 2006.257.06:10:37.70#ibcon#*after write, iclass 33, count 0 2006.257.06:10:37.70#ibcon#*before return 0, iclass 33, count 0 2006.257.06:10:37.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:37.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:10:37.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:10:37.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:10:37.70$vck44/vbbw=wide 2006.257.06:10:37.70#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:10:37.70#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:10:37.70#ibcon#ireg 8 cls_cnt 0 2006.257.06:10:37.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:10:37.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:10:37.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:10:37.77#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:10:37.77#ibcon#first serial, iclass 35, count 0 2006.257.06:10:37.77#ibcon#enter sib2, iclass 35, count 0 2006.257.06:10:37.77#ibcon#flushed, iclass 35, count 0 2006.257.06:10:37.77#ibcon#about to write, iclass 35, count 0 2006.257.06:10:37.77#ibcon#wrote, iclass 35, count 0 2006.257.06:10:37.77#ibcon#about to read 3, iclass 35, count 0 2006.257.06:10:37.79#ibcon#read 3, iclass 35, count 0 2006.257.06:10:37.79#ibcon#about to read 4, iclass 35, count 0 2006.257.06:10:37.79#ibcon#read 4, iclass 35, count 0 2006.257.06:10:37.79#ibcon#about to read 5, iclass 35, count 0 2006.257.06:10:37.79#ibcon#read 5, iclass 35, count 0 2006.257.06:10:37.79#ibcon#about to read 6, iclass 35, count 0 2006.257.06:10:37.79#ibcon#read 6, iclass 35, count 0 2006.257.06:10:37.79#ibcon#end of sib2, iclass 35, count 0 2006.257.06:10:37.79#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:10:37.79#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:10:37.79#ibcon#[27=BW32\r\n] 2006.257.06:10:37.79#ibcon#*before write, iclass 35, count 0 2006.257.06:10:37.79#ibcon#enter sib2, iclass 35, count 0 2006.257.06:10:37.79#ibcon#flushed, iclass 35, count 0 2006.257.06:10:37.79#ibcon#about to write, iclass 35, count 0 2006.257.06:10:37.79#ibcon#wrote, iclass 35, count 0 2006.257.06:10:37.79#ibcon#about to read 3, iclass 35, count 0 2006.257.06:10:37.82#ibcon#read 3, iclass 35, count 0 2006.257.06:10:37.82#ibcon#about to read 4, iclass 35, count 0 2006.257.06:10:37.82#ibcon#read 4, iclass 35, count 0 2006.257.06:10:37.82#ibcon#about to read 5, iclass 35, count 0 2006.257.06:10:37.82#ibcon#read 5, iclass 35, count 0 2006.257.06:10:37.82#ibcon#about to read 6, iclass 35, count 0 2006.257.06:10:37.82#ibcon#read 6, iclass 35, count 0 2006.257.06:10:37.82#ibcon#end of sib2, iclass 35, count 0 2006.257.06:10:37.82#ibcon#*after write, iclass 35, count 0 2006.257.06:10:37.82#ibcon#*before return 0, iclass 35, count 0 2006.257.06:10:37.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:10:37.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:10:37.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:10:37.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:10:37.82$setupk4/ifdk4 2006.257.06:10:37.82$ifdk4/lo= 2006.257.06:10:37.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:10:37.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:10:37.82$ifdk4/patch= 2006.257.06:10:37.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:10:37.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:10:37.82$setupk4/!*+20s 2006.257.06:10:42.63#abcon#<5=/15 1.0 2.5 20.30 891012.1\r\n> 2006.257.06:10:42.65#abcon#{5=INTERFACE CLEAR} 2006.257.06:10:42.71#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:10:50.14#trakl#Source acquired 2006.257.06:10:52.14#flagr#flagr/antenna,acquired 2006.257.06:10:52.33$setupk4/"tpicd 2006.257.06:10:52.33$setupk4/echo=off 2006.257.06:10:52.33$setupk4/xlog=off 2006.257.06:10:52.33:!2006.257.06:11:24 2006.257.06:11:24.00:preob 2006.257.06:11:24.14/onsource/TRACKING 2006.257.06:11:24.14:!2006.257.06:11:34 2006.257.06:11:34.00:"tape 2006.257.06:11:34.00:"st=record 2006.257.06:11:34.00:data_valid=on 2006.257.06:11:34.00:midob 2006.257.06:11:34.14/onsource/TRACKING 2006.257.06:11:34.14/wx/20.32,1012.1,88 2006.257.06:11:34.36/cable/+6.4799E-03 2006.257.06:11:35.45/va/01,08,usb,yes,37,40 2006.257.06:11:35.45/va/02,07,usb,yes,40,41 2006.257.06:11:35.45/va/03,08,usb,yes,36,38 2006.257.06:11:35.45/va/04,07,usb,yes,42,44 2006.257.06:11:35.45/va/05,04,usb,yes,37,38 2006.257.06:11:35.45/va/06,04,usb,yes,42,41 2006.257.06:11:35.45/va/07,04,usb,yes,43,43 2006.257.06:11:35.45/va/08,04,usb,yes,36,43 2006.257.06:11:35.68/valo/01,524.99,yes,locked 2006.257.06:11:35.68/valo/02,534.99,yes,locked 2006.257.06:11:35.68/valo/03,564.99,yes,locked 2006.257.06:11:35.68/valo/04,624.99,yes,locked 2006.257.06:11:35.68/valo/05,734.99,yes,locked 2006.257.06:11:35.68/valo/06,814.99,yes,locked 2006.257.06:11:35.68/valo/07,864.99,yes,locked 2006.257.06:11:35.68/valo/08,884.99,yes,locked 2006.257.06:11:36.77/vb/01,04,usb,yes,35,32 2006.257.06:11:36.77/vb/02,05,usb,yes,33,33 2006.257.06:11:36.77/vb/03,04,usb,yes,34,37 2006.257.06:11:36.77/vb/04,05,usb,yes,34,33 2006.257.06:11:36.77/vb/05,04,usb,yes,31,33 2006.257.06:11:36.77/vb/06,04,usb,yes,36,31 2006.257.06:11:36.77/vb/07,04,usb,yes,35,35 2006.257.06:11:36.77/vb/08,04,usb,yes,32,36 2006.257.06:11:37.00/vblo/01,629.99,yes,locked 2006.257.06:11:37.00/vblo/02,634.99,yes,locked 2006.257.06:11:37.00/vblo/03,649.99,yes,locked 2006.257.06:11:37.00/vblo/04,679.99,yes,locked 2006.257.06:11:37.00/vblo/05,709.99,yes,locked 2006.257.06:11:37.00/vblo/06,719.99,yes,locked 2006.257.06:11:37.00/vblo/07,734.99,yes,locked 2006.257.06:11:37.00/vblo/08,744.99,yes,locked 2006.257.06:11:37.15/vabw/8 2006.257.06:11:37.30/vbbw/8 2006.257.06:11:37.45/xfe/off,on,16.5 2006.257.06:11:37.82/ifatt/23,28,28,28 2006.257.06:11:38.07/fmout-gps/S +4.55E-07 2006.257.06:11:38.11:!2006.257.06:16:44 2006.257.06:16:44.00:data_valid=off 2006.257.06:16:44.00:"et 2006.257.06:16:44.01:!+3s 2006.257.06:16:47.03:"tape 2006.257.06:16:47.03:postob 2006.257.06:16:47.11/cable/+6.4797E-03 2006.257.06:16:47.11/wx/20.38,1012.2,88 2006.257.06:16:47.17/fmout-gps/S +4.54E-07 2006.257.06:16:47.17:scan_name=257-0617,jd0609,170 2006.257.06:16:47.17:source=0059+581,010245.76,582411.1,2000.0,cw 2006.257.06:16:49.13#flagr#flagr/antenna,new-source 2006.257.06:16:49.13:checkk5 2006.257.06:16:49.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:16:49.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:16:50.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:16:50.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:16:51.16/chk_obsdata//k5ts1/T2570611??a.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.257.06:16:51.55/chk_obsdata//k5ts2/T2570611??b.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.257.06:16:51.96/chk_obsdata//k5ts3/T2570611??c.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.257.06:16:52.36/chk_obsdata//k5ts4/T2570611??d.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.257.06:16:53.09/k5log//k5ts1_log_newline 2006.257.06:16:53.81/k5log//k5ts2_log_newline 2006.257.06:16:54.57/k5log//k5ts3_log_newline 2006.257.06:16:55.28/k5log//k5ts4_log_newline 2006.257.06:16:55.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:16:55.31:setupk4=1 2006.257.06:16:55.31$setupk4/echo=on 2006.257.06:16:55.31$setupk4/pcalon 2006.257.06:16:55.31$pcalon/"no phase cal control is implemented here 2006.257.06:16:55.31$setupk4/"tpicd=stop 2006.257.06:16:55.31$setupk4/"rec=synch_on 2006.257.06:16:55.31$setupk4/"rec_mode=128 2006.257.06:16:55.31$setupk4/!* 2006.257.06:16:55.31$setupk4/recpk4 2006.257.06:16:55.31$recpk4/recpatch= 2006.257.06:16:55.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:16:55.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:16:55.31$setupk4/vck44 2006.257.06:16:55.31$vck44/valo=1,524.99 2006.257.06:16:55.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.06:16:55.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.06:16:55.31#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:55.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:55.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:55.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:55.31#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:16:55.31#ibcon#first serial, iclass 6, count 0 2006.257.06:16:55.31#ibcon#enter sib2, iclass 6, count 0 2006.257.06:16:55.31#ibcon#flushed, iclass 6, count 0 2006.257.06:16:55.31#ibcon#about to write, iclass 6, count 0 2006.257.06:16:55.31#ibcon#wrote, iclass 6, count 0 2006.257.06:16:55.31#ibcon#about to read 3, iclass 6, count 0 2006.257.06:16:55.33#ibcon#read 3, iclass 6, count 0 2006.257.06:16:55.33#ibcon#about to read 4, iclass 6, count 0 2006.257.06:16:55.33#ibcon#read 4, iclass 6, count 0 2006.257.06:16:55.33#ibcon#about to read 5, iclass 6, count 0 2006.257.06:16:55.33#ibcon#read 5, iclass 6, count 0 2006.257.06:16:55.33#ibcon#about to read 6, iclass 6, count 0 2006.257.06:16:55.33#ibcon#read 6, iclass 6, count 0 2006.257.06:16:55.33#ibcon#end of sib2, iclass 6, count 0 2006.257.06:16:55.33#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:16:55.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:16:55.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:16:55.33#ibcon#*before write, iclass 6, count 0 2006.257.06:16:55.33#ibcon#enter sib2, iclass 6, count 0 2006.257.06:16:55.33#ibcon#flushed, iclass 6, count 0 2006.257.06:16:55.33#ibcon#about to write, iclass 6, count 0 2006.257.06:16:55.33#ibcon#wrote, iclass 6, count 0 2006.257.06:16:55.33#ibcon#about to read 3, iclass 6, count 0 2006.257.06:16:55.38#ibcon#read 3, iclass 6, count 0 2006.257.06:16:55.38#ibcon#about to read 4, iclass 6, count 0 2006.257.06:16:55.38#ibcon#read 4, iclass 6, count 0 2006.257.06:16:55.38#ibcon#about to read 5, iclass 6, count 0 2006.257.06:16:55.38#ibcon#read 5, iclass 6, count 0 2006.257.06:16:55.38#ibcon#about to read 6, iclass 6, count 0 2006.257.06:16:55.38#ibcon#read 6, iclass 6, count 0 2006.257.06:16:55.38#ibcon#end of sib2, iclass 6, count 0 2006.257.06:16:55.38#ibcon#*after write, iclass 6, count 0 2006.257.06:16:55.38#ibcon#*before return 0, iclass 6, count 0 2006.257.06:16:55.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:55.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:55.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:16:55.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:16:55.38$vck44/va=1,8 2006.257.06:16:55.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.06:16:55.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.06:16:55.38#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:55.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:55.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:55.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:55.38#ibcon#enter wrdev, iclass 10, count 2 2006.257.06:16:55.38#ibcon#first serial, iclass 10, count 2 2006.257.06:16:55.38#ibcon#enter sib2, iclass 10, count 2 2006.257.06:16:55.38#ibcon#flushed, iclass 10, count 2 2006.257.06:16:55.38#ibcon#about to write, iclass 10, count 2 2006.257.06:16:55.38#ibcon#wrote, iclass 10, count 2 2006.257.06:16:55.38#ibcon#about to read 3, iclass 10, count 2 2006.257.06:16:55.40#ibcon#read 3, iclass 10, count 2 2006.257.06:16:55.40#ibcon#about to read 4, iclass 10, count 2 2006.257.06:16:55.40#ibcon#read 4, iclass 10, count 2 2006.257.06:16:55.40#ibcon#about to read 5, iclass 10, count 2 2006.257.06:16:55.40#ibcon#read 5, iclass 10, count 2 2006.257.06:16:55.40#ibcon#about to read 6, iclass 10, count 2 2006.257.06:16:55.40#ibcon#read 6, iclass 10, count 2 2006.257.06:16:55.40#ibcon#end of sib2, iclass 10, count 2 2006.257.06:16:55.40#ibcon#*mode == 0, iclass 10, count 2 2006.257.06:16:55.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.06:16:55.40#ibcon#[25=AT01-08\r\n] 2006.257.06:16:55.40#ibcon#*before write, iclass 10, count 2 2006.257.06:16:55.40#ibcon#enter sib2, iclass 10, count 2 2006.257.06:16:55.40#ibcon#flushed, iclass 10, count 2 2006.257.06:16:55.40#ibcon#about to write, iclass 10, count 2 2006.257.06:16:55.40#ibcon#wrote, iclass 10, count 2 2006.257.06:16:55.40#ibcon#about to read 3, iclass 10, count 2 2006.257.06:16:55.43#ibcon#read 3, iclass 10, count 2 2006.257.06:16:55.43#ibcon#about to read 4, iclass 10, count 2 2006.257.06:16:55.43#ibcon#read 4, iclass 10, count 2 2006.257.06:16:55.43#ibcon#about to read 5, iclass 10, count 2 2006.257.06:16:55.43#ibcon#read 5, iclass 10, count 2 2006.257.06:16:55.43#ibcon#about to read 6, iclass 10, count 2 2006.257.06:16:55.43#ibcon#read 6, iclass 10, count 2 2006.257.06:16:55.43#ibcon#end of sib2, iclass 10, count 2 2006.257.06:16:55.43#ibcon#*after write, iclass 10, count 2 2006.257.06:16:55.43#ibcon#*before return 0, iclass 10, count 2 2006.257.06:16:55.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:55.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:55.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.06:16:55.43#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:55.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:55.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:55.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:55.55#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:16:55.55#ibcon#first serial, iclass 10, count 0 2006.257.06:16:55.55#ibcon#enter sib2, iclass 10, count 0 2006.257.06:16:55.55#ibcon#flushed, iclass 10, count 0 2006.257.06:16:55.55#ibcon#about to write, iclass 10, count 0 2006.257.06:16:55.55#ibcon#wrote, iclass 10, count 0 2006.257.06:16:55.55#ibcon#about to read 3, iclass 10, count 0 2006.257.06:16:55.57#ibcon#read 3, iclass 10, count 0 2006.257.06:16:55.57#ibcon#about to read 4, iclass 10, count 0 2006.257.06:16:55.57#ibcon#read 4, iclass 10, count 0 2006.257.06:16:55.57#ibcon#about to read 5, iclass 10, count 0 2006.257.06:16:55.57#ibcon#read 5, iclass 10, count 0 2006.257.06:16:55.57#ibcon#about to read 6, iclass 10, count 0 2006.257.06:16:55.57#ibcon#read 6, iclass 10, count 0 2006.257.06:16:55.57#ibcon#end of sib2, iclass 10, count 0 2006.257.06:16:55.57#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:16:55.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:16:55.57#ibcon#[25=USB\r\n] 2006.257.06:16:55.57#ibcon#*before write, iclass 10, count 0 2006.257.06:16:55.57#ibcon#enter sib2, iclass 10, count 0 2006.257.06:16:55.57#ibcon#flushed, iclass 10, count 0 2006.257.06:16:55.57#ibcon#about to write, iclass 10, count 0 2006.257.06:16:55.57#ibcon#wrote, iclass 10, count 0 2006.257.06:16:55.57#ibcon#about to read 3, iclass 10, count 0 2006.257.06:16:55.60#ibcon#read 3, iclass 10, count 0 2006.257.06:16:55.60#ibcon#about to read 4, iclass 10, count 0 2006.257.06:16:55.60#ibcon#read 4, iclass 10, count 0 2006.257.06:16:55.60#ibcon#about to read 5, iclass 10, count 0 2006.257.06:16:55.60#ibcon#read 5, iclass 10, count 0 2006.257.06:16:55.60#ibcon#about to read 6, iclass 10, count 0 2006.257.06:16:55.60#ibcon#read 6, iclass 10, count 0 2006.257.06:16:55.60#ibcon#end of sib2, iclass 10, count 0 2006.257.06:16:55.60#ibcon#*after write, iclass 10, count 0 2006.257.06:16:55.60#ibcon#*before return 0, iclass 10, count 0 2006.257.06:16:55.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:55.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:55.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:16:55.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:16:55.60$vck44/valo=2,534.99 2006.257.06:16:55.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.06:16:55.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.06:16:55.60#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:55.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:55.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:55.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:55.60#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:16:55.60#ibcon#first serial, iclass 12, count 0 2006.257.06:16:55.60#ibcon#enter sib2, iclass 12, count 0 2006.257.06:16:55.60#ibcon#flushed, iclass 12, count 0 2006.257.06:16:55.60#ibcon#about to write, iclass 12, count 0 2006.257.06:16:55.60#ibcon#wrote, iclass 12, count 0 2006.257.06:16:55.60#ibcon#about to read 3, iclass 12, count 0 2006.257.06:16:55.62#ibcon#read 3, iclass 12, count 0 2006.257.06:16:55.62#ibcon#about to read 4, iclass 12, count 0 2006.257.06:16:55.62#ibcon#read 4, iclass 12, count 0 2006.257.06:16:55.62#ibcon#about to read 5, iclass 12, count 0 2006.257.06:16:55.62#ibcon#read 5, iclass 12, count 0 2006.257.06:16:55.62#ibcon#about to read 6, iclass 12, count 0 2006.257.06:16:55.62#ibcon#read 6, iclass 12, count 0 2006.257.06:16:55.62#ibcon#end of sib2, iclass 12, count 0 2006.257.06:16:55.62#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:16:55.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:16:55.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:16:55.62#ibcon#*before write, iclass 12, count 0 2006.257.06:16:55.62#ibcon#enter sib2, iclass 12, count 0 2006.257.06:16:55.62#ibcon#flushed, iclass 12, count 0 2006.257.06:16:55.62#ibcon#about to write, iclass 12, count 0 2006.257.06:16:55.62#ibcon#wrote, iclass 12, count 0 2006.257.06:16:55.62#ibcon#about to read 3, iclass 12, count 0 2006.257.06:16:55.66#ibcon#read 3, iclass 12, count 0 2006.257.06:16:55.66#ibcon#about to read 4, iclass 12, count 0 2006.257.06:16:55.66#ibcon#read 4, iclass 12, count 0 2006.257.06:16:55.66#ibcon#about to read 5, iclass 12, count 0 2006.257.06:16:55.66#ibcon#read 5, iclass 12, count 0 2006.257.06:16:55.66#ibcon#about to read 6, iclass 12, count 0 2006.257.06:16:55.66#ibcon#read 6, iclass 12, count 0 2006.257.06:16:55.66#ibcon#end of sib2, iclass 12, count 0 2006.257.06:16:55.66#ibcon#*after write, iclass 12, count 0 2006.257.06:16:55.66#ibcon#*before return 0, iclass 12, count 0 2006.257.06:16:55.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:55.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:55.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:16:55.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:16:55.66$vck44/va=2,7 2006.257.06:16:55.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.06:16:55.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.06:16:55.66#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:55.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:55.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:55.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:55.72#ibcon#enter wrdev, iclass 14, count 2 2006.257.06:16:55.72#ibcon#first serial, iclass 14, count 2 2006.257.06:16:55.72#ibcon#enter sib2, iclass 14, count 2 2006.257.06:16:55.72#ibcon#flushed, iclass 14, count 2 2006.257.06:16:55.72#ibcon#about to write, iclass 14, count 2 2006.257.06:16:55.72#ibcon#wrote, iclass 14, count 2 2006.257.06:16:55.72#ibcon#about to read 3, iclass 14, count 2 2006.257.06:16:55.74#ibcon#read 3, iclass 14, count 2 2006.257.06:16:55.74#ibcon#about to read 4, iclass 14, count 2 2006.257.06:16:55.74#ibcon#read 4, iclass 14, count 2 2006.257.06:16:55.74#ibcon#about to read 5, iclass 14, count 2 2006.257.06:16:55.74#ibcon#read 5, iclass 14, count 2 2006.257.06:16:55.74#ibcon#about to read 6, iclass 14, count 2 2006.257.06:16:55.74#ibcon#read 6, iclass 14, count 2 2006.257.06:16:55.74#ibcon#end of sib2, iclass 14, count 2 2006.257.06:16:55.74#ibcon#*mode == 0, iclass 14, count 2 2006.257.06:16:55.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.06:16:55.74#ibcon#[25=AT02-07\r\n] 2006.257.06:16:55.74#ibcon#*before write, iclass 14, count 2 2006.257.06:16:55.74#ibcon#enter sib2, iclass 14, count 2 2006.257.06:16:55.74#ibcon#flushed, iclass 14, count 2 2006.257.06:16:55.74#ibcon#about to write, iclass 14, count 2 2006.257.06:16:55.74#ibcon#wrote, iclass 14, count 2 2006.257.06:16:55.74#ibcon#about to read 3, iclass 14, count 2 2006.257.06:16:55.77#ibcon#read 3, iclass 14, count 2 2006.257.06:16:55.77#ibcon#about to read 4, iclass 14, count 2 2006.257.06:16:55.77#ibcon#read 4, iclass 14, count 2 2006.257.06:16:55.77#ibcon#about to read 5, iclass 14, count 2 2006.257.06:16:55.77#ibcon#read 5, iclass 14, count 2 2006.257.06:16:55.77#ibcon#about to read 6, iclass 14, count 2 2006.257.06:16:55.77#ibcon#read 6, iclass 14, count 2 2006.257.06:16:55.77#ibcon#end of sib2, iclass 14, count 2 2006.257.06:16:55.77#ibcon#*after write, iclass 14, count 2 2006.257.06:16:55.77#ibcon#*before return 0, iclass 14, count 2 2006.257.06:16:55.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:55.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:55.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.06:16:55.77#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:55.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:55.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:55.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:55.89#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:16:55.89#ibcon#first serial, iclass 14, count 0 2006.257.06:16:55.89#ibcon#enter sib2, iclass 14, count 0 2006.257.06:16:55.89#ibcon#flushed, iclass 14, count 0 2006.257.06:16:55.89#ibcon#about to write, iclass 14, count 0 2006.257.06:16:55.89#ibcon#wrote, iclass 14, count 0 2006.257.06:16:55.89#ibcon#about to read 3, iclass 14, count 0 2006.257.06:16:55.91#ibcon#read 3, iclass 14, count 0 2006.257.06:16:55.91#ibcon#about to read 4, iclass 14, count 0 2006.257.06:16:55.91#ibcon#read 4, iclass 14, count 0 2006.257.06:16:55.91#ibcon#about to read 5, iclass 14, count 0 2006.257.06:16:55.91#ibcon#read 5, iclass 14, count 0 2006.257.06:16:55.91#ibcon#about to read 6, iclass 14, count 0 2006.257.06:16:55.91#ibcon#read 6, iclass 14, count 0 2006.257.06:16:55.91#ibcon#end of sib2, iclass 14, count 0 2006.257.06:16:55.91#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:16:55.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:16:55.91#ibcon#[25=USB\r\n] 2006.257.06:16:55.91#ibcon#*before write, iclass 14, count 0 2006.257.06:16:55.91#ibcon#enter sib2, iclass 14, count 0 2006.257.06:16:55.91#ibcon#flushed, iclass 14, count 0 2006.257.06:16:55.91#ibcon#about to write, iclass 14, count 0 2006.257.06:16:55.91#ibcon#wrote, iclass 14, count 0 2006.257.06:16:55.91#ibcon#about to read 3, iclass 14, count 0 2006.257.06:16:55.94#ibcon#read 3, iclass 14, count 0 2006.257.06:16:55.94#ibcon#about to read 4, iclass 14, count 0 2006.257.06:16:55.94#ibcon#read 4, iclass 14, count 0 2006.257.06:16:55.94#ibcon#about to read 5, iclass 14, count 0 2006.257.06:16:55.94#ibcon#read 5, iclass 14, count 0 2006.257.06:16:55.94#ibcon#about to read 6, iclass 14, count 0 2006.257.06:16:55.94#ibcon#read 6, iclass 14, count 0 2006.257.06:16:55.94#ibcon#end of sib2, iclass 14, count 0 2006.257.06:16:55.94#ibcon#*after write, iclass 14, count 0 2006.257.06:16:55.94#ibcon#*before return 0, iclass 14, count 0 2006.257.06:16:55.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:55.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:55.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:16:55.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:16:55.94$vck44/valo=3,564.99 2006.257.06:16:55.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.06:16:55.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.06:16:55.94#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:55.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:55.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:55.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:55.94#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:16:55.94#ibcon#first serial, iclass 16, count 0 2006.257.06:16:55.94#ibcon#enter sib2, iclass 16, count 0 2006.257.06:16:55.94#ibcon#flushed, iclass 16, count 0 2006.257.06:16:55.94#ibcon#about to write, iclass 16, count 0 2006.257.06:16:55.94#ibcon#wrote, iclass 16, count 0 2006.257.06:16:55.94#ibcon#about to read 3, iclass 16, count 0 2006.257.06:16:55.96#ibcon#read 3, iclass 16, count 0 2006.257.06:16:55.96#ibcon#about to read 4, iclass 16, count 0 2006.257.06:16:55.96#ibcon#read 4, iclass 16, count 0 2006.257.06:16:55.96#ibcon#about to read 5, iclass 16, count 0 2006.257.06:16:55.96#ibcon#read 5, iclass 16, count 0 2006.257.06:16:55.96#ibcon#about to read 6, iclass 16, count 0 2006.257.06:16:55.96#ibcon#read 6, iclass 16, count 0 2006.257.06:16:55.96#ibcon#end of sib2, iclass 16, count 0 2006.257.06:16:55.96#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:16:55.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:16:55.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:16:55.96#ibcon#*before write, iclass 16, count 0 2006.257.06:16:55.96#ibcon#enter sib2, iclass 16, count 0 2006.257.06:16:55.96#ibcon#flushed, iclass 16, count 0 2006.257.06:16:55.96#ibcon#about to write, iclass 16, count 0 2006.257.06:16:55.96#ibcon#wrote, iclass 16, count 0 2006.257.06:16:55.96#ibcon#about to read 3, iclass 16, count 0 2006.257.06:16:56.00#ibcon#read 3, iclass 16, count 0 2006.257.06:16:56.00#ibcon#about to read 4, iclass 16, count 0 2006.257.06:16:56.00#ibcon#read 4, iclass 16, count 0 2006.257.06:16:56.00#ibcon#about to read 5, iclass 16, count 0 2006.257.06:16:56.00#ibcon#read 5, iclass 16, count 0 2006.257.06:16:56.00#ibcon#about to read 6, iclass 16, count 0 2006.257.06:16:56.00#ibcon#read 6, iclass 16, count 0 2006.257.06:16:56.00#ibcon#end of sib2, iclass 16, count 0 2006.257.06:16:56.00#ibcon#*after write, iclass 16, count 0 2006.257.06:16:56.00#ibcon#*before return 0, iclass 16, count 0 2006.257.06:16:56.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:56.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:56.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:16:56.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:16:56.00$vck44/va=3,8 2006.257.06:16:56.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.06:16:56.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.06:16:56.00#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:56.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:56.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:56.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:56.06#ibcon#enter wrdev, iclass 18, count 2 2006.257.06:16:56.06#ibcon#first serial, iclass 18, count 2 2006.257.06:16:56.06#ibcon#enter sib2, iclass 18, count 2 2006.257.06:16:56.06#ibcon#flushed, iclass 18, count 2 2006.257.06:16:56.06#ibcon#about to write, iclass 18, count 2 2006.257.06:16:56.06#ibcon#wrote, iclass 18, count 2 2006.257.06:16:56.06#ibcon#about to read 3, iclass 18, count 2 2006.257.06:16:56.08#ibcon#read 3, iclass 18, count 2 2006.257.06:16:56.08#ibcon#about to read 4, iclass 18, count 2 2006.257.06:16:56.08#ibcon#read 4, iclass 18, count 2 2006.257.06:16:56.08#ibcon#about to read 5, iclass 18, count 2 2006.257.06:16:56.08#ibcon#read 5, iclass 18, count 2 2006.257.06:16:56.08#ibcon#about to read 6, iclass 18, count 2 2006.257.06:16:56.08#ibcon#read 6, iclass 18, count 2 2006.257.06:16:56.08#ibcon#end of sib2, iclass 18, count 2 2006.257.06:16:56.08#ibcon#*mode == 0, iclass 18, count 2 2006.257.06:16:56.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.06:16:56.08#ibcon#[25=AT03-08\r\n] 2006.257.06:16:56.08#ibcon#*before write, iclass 18, count 2 2006.257.06:16:56.08#ibcon#enter sib2, iclass 18, count 2 2006.257.06:16:56.08#ibcon#flushed, iclass 18, count 2 2006.257.06:16:56.08#ibcon#about to write, iclass 18, count 2 2006.257.06:16:56.08#ibcon#wrote, iclass 18, count 2 2006.257.06:16:56.08#ibcon#about to read 3, iclass 18, count 2 2006.257.06:16:56.11#ibcon#read 3, iclass 18, count 2 2006.257.06:16:56.11#ibcon#about to read 4, iclass 18, count 2 2006.257.06:16:56.11#ibcon#read 4, iclass 18, count 2 2006.257.06:16:56.11#ibcon#about to read 5, iclass 18, count 2 2006.257.06:16:56.11#ibcon#read 5, iclass 18, count 2 2006.257.06:16:56.11#ibcon#about to read 6, iclass 18, count 2 2006.257.06:16:56.11#ibcon#read 6, iclass 18, count 2 2006.257.06:16:56.11#ibcon#end of sib2, iclass 18, count 2 2006.257.06:16:56.11#ibcon#*after write, iclass 18, count 2 2006.257.06:16:56.11#ibcon#*before return 0, iclass 18, count 2 2006.257.06:16:56.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:56.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:56.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.06:16:56.11#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:56.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:56.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:56.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:56.23#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:16:56.23#ibcon#first serial, iclass 18, count 0 2006.257.06:16:56.23#ibcon#enter sib2, iclass 18, count 0 2006.257.06:16:56.23#ibcon#flushed, iclass 18, count 0 2006.257.06:16:56.23#ibcon#about to write, iclass 18, count 0 2006.257.06:16:56.23#ibcon#wrote, iclass 18, count 0 2006.257.06:16:56.23#ibcon#about to read 3, iclass 18, count 0 2006.257.06:16:56.25#ibcon#read 3, iclass 18, count 0 2006.257.06:16:56.25#ibcon#about to read 4, iclass 18, count 0 2006.257.06:16:56.25#ibcon#read 4, iclass 18, count 0 2006.257.06:16:56.25#ibcon#about to read 5, iclass 18, count 0 2006.257.06:16:56.25#ibcon#read 5, iclass 18, count 0 2006.257.06:16:56.25#ibcon#about to read 6, iclass 18, count 0 2006.257.06:16:56.25#ibcon#read 6, iclass 18, count 0 2006.257.06:16:56.25#ibcon#end of sib2, iclass 18, count 0 2006.257.06:16:56.25#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:16:56.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:16:56.25#ibcon#[25=USB\r\n] 2006.257.06:16:56.25#ibcon#*before write, iclass 18, count 0 2006.257.06:16:56.25#ibcon#enter sib2, iclass 18, count 0 2006.257.06:16:56.25#ibcon#flushed, iclass 18, count 0 2006.257.06:16:56.25#ibcon#about to write, iclass 18, count 0 2006.257.06:16:56.25#ibcon#wrote, iclass 18, count 0 2006.257.06:16:56.25#ibcon#about to read 3, iclass 18, count 0 2006.257.06:16:56.28#ibcon#read 3, iclass 18, count 0 2006.257.06:16:56.28#ibcon#about to read 4, iclass 18, count 0 2006.257.06:16:56.28#ibcon#read 4, iclass 18, count 0 2006.257.06:16:56.28#ibcon#about to read 5, iclass 18, count 0 2006.257.06:16:56.28#ibcon#read 5, iclass 18, count 0 2006.257.06:16:56.28#ibcon#about to read 6, iclass 18, count 0 2006.257.06:16:56.28#ibcon#read 6, iclass 18, count 0 2006.257.06:16:56.28#ibcon#end of sib2, iclass 18, count 0 2006.257.06:16:56.28#ibcon#*after write, iclass 18, count 0 2006.257.06:16:56.28#ibcon#*before return 0, iclass 18, count 0 2006.257.06:16:56.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:56.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:56.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:16:56.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:16:56.28$vck44/valo=4,624.99 2006.257.06:16:56.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.06:16:56.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.06:16:56.28#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:56.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:16:56.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:16:56.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:16:56.28#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:16:56.28#ibcon#first serial, iclass 20, count 0 2006.257.06:16:56.28#ibcon#enter sib2, iclass 20, count 0 2006.257.06:16:56.28#ibcon#flushed, iclass 20, count 0 2006.257.06:16:56.28#ibcon#about to write, iclass 20, count 0 2006.257.06:16:56.28#ibcon#wrote, iclass 20, count 0 2006.257.06:16:56.28#ibcon#about to read 3, iclass 20, count 0 2006.257.06:16:56.30#ibcon#read 3, iclass 20, count 0 2006.257.06:16:56.30#ibcon#about to read 4, iclass 20, count 0 2006.257.06:16:56.30#ibcon#read 4, iclass 20, count 0 2006.257.06:16:56.30#ibcon#about to read 5, iclass 20, count 0 2006.257.06:16:56.30#ibcon#read 5, iclass 20, count 0 2006.257.06:16:56.30#ibcon#about to read 6, iclass 20, count 0 2006.257.06:16:56.30#ibcon#read 6, iclass 20, count 0 2006.257.06:16:56.30#ibcon#end of sib2, iclass 20, count 0 2006.257.06:16:56.30#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:16:56.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:16:56.30#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:16:56.30#ibcon#*before write, iclass 20, count 0 2006.257.06:16:56.30#ibcon#enter sib2, iclass 20, count 0 2006.257.06:16:56.30#ibcon#flushed, iclass 20, count 0 2006.257.06:16:56.30#ibcon#about to write, iclass 20, count 0 2006.257.06:16:56.30#ibcon#wrote, iclass 20, count 0 2006.257.06:16:56.30#ibcon#about to read 3, iclass 20, count 0 2006.257.06:16:56.34#ibcon#read 3, iclass 20, count 0 2006.257.06:16:56.34#ibcon#about to read 4, iclass 20, count 0 2006.257.06:16:56.34#ibcon#read 4, iclass 20, count 0 2006.257.06:16:56.34#ibcon#about to read 5, iclass 20, count 0 2006.257.06:16:56.34#ibcon#read 5, iclass 20, count 0 2006.257.06:16:56.34#ibcon#about to read 6, iclass 20, count 0 2006.257.06:16:56.34#ibcon#read 6, iclass 20, count 0 2006.257.06:16:56.34#ibcon#end of sib2, iclass 20, count 0 2006.257.06:16:56.34#ibcon#*after write, iclass 20, count 0 2006.257.06:16:56.34#ibcon#*before return 0, iclass 20, count 0 2006.257.06:16:56.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:16:56.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:16:56.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:16:56.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:16:56.34$vck44/va=4,7 2006.257.06:16:56.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.06:16:56.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.06:16:56.34#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:56.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:16:56.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:16:56.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:16:56.40#ibcon#enter wrdev, iclass 22, count 2 2006.257.06:16:56.40#ibcon#first serial, iclass 22, count 2 2006.257.06:16:56.40#ibcon#enter sib2, iclass 22, count 2 2006.257.06:16:56.40#ibcon#flushed, iclass 22, count 2 2006.257.06:16:56.40#ibcon#about to write, iclass 22, count 2 2006.257.06:16:56.40#ibcon#wrote, iclass 22, count 2 2006.257.06:16:56.40#ibcon#about to read 3, iclass 22, count 2 2006.257.06:16:56.42#ibcon#read 3, iclass 22, count 2 2006.257.06:16:56.42#ibcon#about to read 4, iclass 22, count 2 2006.257.06:16:56.42#ibcon#read 4, iclass 22, count 2 2006.257.06:16:56.42#ibcon#about to read 5, iclass 22, count 2 2006.257.06:16:56.42#ibcon#read 5, iclass 22, count 2 2006.257.06:16:56.42#ibcon#about to read 6, iclass 22, count 2 2006.257.06:16:56.42#ibcon#read 6, iclass 22, count 2 2006.257.06:16:56.42#ibcon#end of sib2, iclass 22, count 2 2006.257.06:16:56.42#ibcon#*mode == 0, iclass 22, count 2 2006.257.06:16:56.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.06:16:56.42#ibcon#[25=AT04-07\r\n] 2006.257.06:16:56.42#ibcon#*before write, iclass 22, count 2 2006.257.06:16:56.42#ibcon#enter sib2, iclass 22, count 2 2006.257.06:16:56.42#ibcon#flushed, iclass 22, count 2 2006.257.06:16:56.42#ibcon#about to write, iclass 22, count 2 2006.257.06:16:56.42#ibcon#wrote, iclass 22, count 2 2006.257.06:16:56.42#ibcon#about to read 3, iclass 22, count 2 2006.257.06:16:56.45#ibcon#read 3, iclass 22, count 2 2006.257.06:16:56.45#ibcon#about to read 4, iclass 22, count 2 2006.257.06:16:56.45#ibcon#read 4, iclass 22, count 2 2006.257.06:16:56.45#ibcon#about to read 5, iclass 22, count 2 2006.257.06:16:56.45#ibcon#read 5, iclass 22, count 2 2006.257.06:16:56.45#ibcon#about to read 6, iclass 22, count 2 2006.257.06:16:56.45#ibcon#read 6, iclass 22, count 2 2006.257.06:16:56.45#ibcon#end of sib2, iclass 22, count 2 2006.257.06:16:56.45#ibcon#*after write, iclass 22, count 2 2006.257.06:16:56.45#ibcon#*before return 0, iclass 22, count 2 2006.257.06:16:56.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:16:56.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:16:56.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.06:16:56.45#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:56.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:16:56.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:16:56.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:16:56.57#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:16:56.57#ibcon#first serial, iclass 22, count 0 2006.257.06:16:56.57#ibcon#enter sib2, iclass 22, count 0 2006.257.06:16:56.57#ibcon#flushed, iclass 22, count 0 2006.257.06:16:56.57#ibcon#about to write, iclass 22, count 0 2006.257.06:16:56.57#ibcon#wrote, iclass 22, count 0 2006.257.06:16:56.57#ibcon#about to read 3, iclass 22, count 0 2006.257.06:16:56.59#ibcon#read 3, iclass 22, count 0 2006.257.06:16:56.59#ibcon#about to read 4, iclass 22, count 0 2006.257.06:16:56.59#ibcon#read 4, iclass 22, count 0 2006.257.06:16:56.59#ibcon#about to read 5, iclass 22, count 0 2006.257.06:16:56.59#ibcon#read 5, iclass 22, count 0 2006.257.06:16:56.59#ibcon#about to read 6, iclass 22, count 0 2006.257.06:16:56.59#ibcon#read 6, iclass 22, count 0 2006.257.06:16:56.59#ibcon#end of sib2, iclass 22, count 0 2006.257.06:16:56.59#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:16:56.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:16:56.59#ibcon#[25=USB\r\n] 2006.257.06:16:56.59#ibcon#*before write, iclass 22, count 0 2006.257.06:16:56.59#ibcon#enter sib2, iclass 22, count 0 2006.257.06:16:56.59#ibcon#flushed, iclass 22, count 0 2006.257.06:16:56.59#ibcon#about to write, iclass 22, count 0 2006.257.06:16:56.59#ibcon#wrote, iclass 22, count 0 2006.257.06:16:56.59#ibcon#about to read 3, iclass 22, count 0 2006.257.06:16:56.62#ibcon#read 3, iclass 22, count 0 2006.257.06:16:56.62#ibcon#about to read 4, iclass 22, count 0 2006.257.06:16:56.62#ibcon#read 4, iclass 22, count 0 2006.257.06:16:56.62#ibcon#about to read 5, iclass 22, count 0 2006.257.06:16:56.62#ibcon#read 5, iclass 22, count 0 2006.257.06:16:56.62#ibcon#about to read 6, iclass 22, count 0 2006.257.06:16:56.62#ibcon#read 6, iclass 22, count 0 2006.257.06:16:56.62#ibcon#end of sib2, iclass 22, count 0 2006.257.06:16:56.62#ibcon#*after write, iclass 22, count 0 2006.257.06:16:56.62#ibcon#*before return 0, iclass 22, count 0 2006.257.06:16:56.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:16:56.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:16:56.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:16:56.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:16:56.62$vck44/valo=5,734.99 2006.257.06:16:56.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.06:16:56.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.06:16:56.62#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:56.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:56.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:56.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:56.62#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:16:56.62#ibcon#first serial, iclass 24, count 0 2006.257.06:16:56.62#ibcon#enter sib2, iclass 24, count 0 2006.257.06:16:56.62#ibcon#flushed, iclass 24, count 0 2006.257.06:16:56.62#ibcon#about to write, iclass 24, count 0 2006.257.06:16:56.62#ibcon#wrote, iclass 24, count 0 2006.257.06:16:56.62#ibcon#about to read 3, iclass 24, count 0 2006.257.06:16:56.64#ibcon#read 3, iclass 24, count 0 2006.257.06:16:56.64#ibcon#about to read 4, iclass 24, count 0 2006.257.06:16:56.64#ibcon#read 4, iclass 24, count 0 2006.257.06:16:56.64#ibcon#about to read 5, iclass 24, count 0 2006.257.06:16:56.64#ibcon#read 5, iclass 24, count 0 2006.257.06:16:56.64#ibcon#about to read 6, iclass 24, count 0 2006.257.06:16:56.64#ibcon#read 6, iclass 24, count 0 2006.257.06:16:56.64#ibcon#end of sib2, iclass 24, count 0 2006.257.06:16:56.64#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:16:56.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:16:56.64#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:16:56.64#ibcon#*before write, iclass 24, count 0 2006.257.06:16:56.64#ibcon#enter sib2, iclass 24, count 0 2006.257.06:16:56.64#ibcon#flushed, iclass 24, count 0 2006.257.06:16:56.64#ibcon#about to write, iclass 24, count 0 2006.257.06:16:56.64#ibcon#wrote, iclass 24, count 0 2006.257.06:16:56.64#ibcon#about to read 3, iclass 24, count 0 2006.257.06:16:56.68#ibcon#read 3, iclass 24, count 0 2006.257.06:16:56.68#ibcon#about to read 4, iclass 24, count 0 2006.257.06:16:56.68#ibcon#read 4, iclass 24, count 0 2006.257.06:16:56.68#ibcon#about to read 5, iclass 24, count 0 2006.257.06:16:56.68#ibcon#read 5, iclass 24, count 0 2006.257.06:16:56.68#ibcon#about to read 6, iclass 24, count 0 2006.257.06:16:56.68#ibcon#read 6, iclass 24, count 0 2006.257.06:16:56.68#ibcon#end of sib2, iclass 24, count 0 2006.257.06:16:56.68#ibcon#*after write, iclass 24, count 0 2006.257.06:16:56.68#ibcon#*before return 0, iclass 24, count 0 2006.257.06:16:56.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:56.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:56.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:16:56.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:16:56.68$vck44/va=5,4 2006.257.06:16:56.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.06:16:56.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.06:16:56.68#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:56.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:56.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:56.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:56.74#ibcon#enter wrdev, iclass 26, count 2 2006.257.06:16:56.74#ibcon#first serial, iclass 26, count 2 2006.257.06:16:56.74#ibcon#enter sib2, iclass 26, count 2 2006.257.06:16:56.74#ibcon#flushed, iclass 26, count 2 2006.257.06:16:56.74#ibcon#about to write, iclass 26, count 2 2006.257.06:16:56.74#ibcon#wrote, iclass 26, count 2 2006.257.06:16:56.74#ibcon#about to read 3, iclass 26, count 2 2006.257.06:16:56.76#ibcon#read 3, iclass 26, count 2 2006.257.06:16:56.76#ibcon#about to read 4, iclass 26, count 2 2006.257.06:16:56.76#ibcon#read 4, iclass 26, count 2 2006.257.06:16:56.76#ibcon#about to read 5, iclass 26, count 2 2006.257.06:16:56.76#ibcon#read 5, iclass 26, count 2 2006.257.06:16:56.76#ibcon#about to read 6, iclass 26, count 2 2006.257.06:16:56.76#ibcon#read 6, iclass 26, count 2 2006.257.06:16:56.76#ibcon#end of sib2, iclass 26, count 2 2006.257.06:16:56.76#ibcon#*mode == 0, iclass 26, count 2 2006.257.06:16:56.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.06:16:56.76#ibcon#[25=AT05-04\r\n] 2006.257.06:16:56.76#ibcon#*before write, iclass 26, count 2 2006.257.06:16:56.76#ibcon#enter sib2, iclass 26, count 2 2006.257.06:16:56.76#ibcon#flushed, iclass 26, count 2 2006.257.06:16:56.76#ibcon#about to write, iclass 26, count 2 2006.257.06:16:56.76#ibcon#wrote, iclass 26, count 2 2006.257.06:16:56.76#ibcon#about to read 3, iclass 26, count 2 2006.257.06:16:56.79#ibcon#read 3, iclass 26, count 2 2006.257.06:16:56.79#ibcon#about to read 4, iclass 26, count 2 2006.257.06:16:56.79#ibcon#read 4, iclass 26, count 2 2006.257.06:16:56.79#ibcon#about to read 5, iclass 26, count 2 2006.257.06:16:56.79#ibcon#read 5, iclass 26, count 2 2006.257.06:16:56.79#ibcon#about to read 6, iclass 26, count 2 2006.257.06:16:56.79#ibcon#read 6, iclass 26, count 2 2006.257.06:16:56.79#ibcon#end of sib2, iclass 26, count 2 2006.257.06:16:56.79#ibcon#*after write, iclass 26, count 2 2006.257.06:16:56.79#ibcon#*before return 0, iclass 26, count 2 2006.257.06:16:56.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:56.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:56.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.06:16:56.79#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:56.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:56.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:56.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:56.91#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:16:56.91#ibcon#first serial, iclass 26, count 0 2006.257.06:16:56.91#ibcon#enter sib2, iclass 26, count 0 2006.257.06:16:56.91#ibcon#flushed, iclass 26, count 0 2006.257.06:16:56.91#ibcon#about to write, iclass 26, count 0 2006.257.06:16:56.91#ibcon#wrote, iclass 26, count 0 2006.257.06:16:56.91#ibcon#about to read 3, iclass 26, count 0 2006.257.06:16:56.93#ibcon#read 3, iclass 26, count 0 2006.257.06:16:56.93#ibcon#about to read 4, iclass 26, count 0 2006.257.06:16:56.93#ibcon#read 4, iclass 26, count 0 2006.257.06:16:56.93#ibcon#about to read 5, iclass 26, count 0 2006.257.06:16:56.93#ibcon#read 5, iclass 26, count 0 2006.257.06:16:56.93#ibcon#about to read 6, iclass 26, count 0 2006.257.06:16:56.93#ibcon#read 6, iclass 26, count 0 2006.257.06:16:56.93#ibcon#end of sib2, iclass 26, count 0 2006.257.06:16:56.93#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:16:56.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:16:56.93#ibcon#[25=USB\r\n] 2006.257.06:16:56.93#ibcon#*before write, iclass 26, count 0 2006.257.06:16:56.93#ibcon#enter sib2, iclass 26, count 0 2006.257.06:16:56.93#ibcon#flushed, iclass 26, count 0 2006.257.06:16:56.93#ibcon#about to write, iclass 26, count 0 2006.257.06:16:56.93#ibcon#wrote, iclass 26, count 0 2006.257.06:16:56.93#ibcon#about to read 3, iclass 26, count 0 2006.257.06:16:56.96#ibcon#read 3, iclass 26, count 0 2006.257.06:16:56.96#ibcon#about to read 4, iclass 26, count 0 2006.257.06:16:56.96#ibcon#read 4, iclass 26, count 0 2006.257.06:16:56.96#ibcon#about to read 5, iclass 26, count 0 2006.257.06:16:56.96#ibcon#read 5, iclass 26, count 0 2006.257.06:16:56.96#ibcon#about to read 6, iclass 26, count 0 2006.257.06:16:56.96#ibcon#read 6, iclass 26, count 0 2006.257.06:16:56.96#ibcon#end of sib2, iclass 26, count 0 2006.257.06:16:56.96#ibcon#*after write, iclass 26, count 0 2006.257.06:16:56.96#ibcon#*before return 0, iclass 26, count 0 2006.257.06:16:56.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:56.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:56.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:16:56.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:16:56.96$vck44/valo=6,814.99 2006.257.06:16:56.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.06:16:56.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.06:16:56.96#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:56.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:56.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:56.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:56.96#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:16:56.96#ibcon#first serial, iclass 28, count 0 2006.257.06:16:56.96#ibcon#enter sib2, iclass 28, count 0 2006.257.06:16:56.96#ibcon#flushed, iclass 28, count 0 2006.257.06:16:56.96#ibcon#about to write, iclass 28, count 0 2006.257.06:16:56.96#ibcon#wrote, iclass 28, count 0 2006.257.06:16:56.96#ibcon#about to read 3, iclass 28, count 0 2006.257.06:16:56.98#ibcon#read 3, iclass 28, count 0 2006.257.06:16:56.98#ibcon#about to read 4, iclass 28, count 0 2006.257.06:16:56.98#ibcon#read 4, iclass 28, count 0 2006.257.06:16:56.98#ibcon#about to read 5, iclass 28, count 0 2006.257.06:16:56.98#ibcon#read 5, iclass 28, count 0 2006.257.06:16:56.98#ibcon#about to read 6, iclass 28, count 0 2006.257.06:16:56.98#ibcon#read 6, iclass 28, count 0 2006.257.06:16:56.98#ibcon#end of sib2, iclass 28, count 0 2006.257.06:16:56.98#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:16:56.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:16:56.98#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:16:56.98#ibcon#*before write, iclass 28, count 0 2006.257.06:16:56.98#ibcon#enter sib2, iclass 28, count 0 2006.257.06:16:56.98#ibcon#flushed, iclass 28, count 0 2006.257.06:16:56.98#ibcon#about to write, iclass 28, count 0 2006.257.06:16:56.98#ibcon#wrote, iclass 28, count 0 2006.257.06:16:56.98#ibcon#about to read 3, iclass 28, count 0 2006.257.06:16:57.02#ibcon#read 3, iclass 28, count 0 2006.257.06:16:57.02#ibcon#about to read 4, iclass 28, count 0 2006.257.06:16:57.02#ibcon#read 4, iclass 28, count 0 2006.257.06:16:57.02#ibcon#about to read 5, iclass 28, count 0 2006.257.06:16:57.02#ibcon#read 5, iclass 28, count 0 2006.257.06:16:57.02#ibcon#about to read 6, iclass 28, count 0 2006.257.06:16:57.02#ibcon#read 6, iclass 28, count 0 2006.257.06:16:57.02#ibcon#end of sib2, iclass 28, count 0 2006.257.06:16:57.02#ibcon#*after write, iclass 28, count 0 2006.257.06:16:57.02#ibcon#*before return 0, iclass 28, count 0 2006.257.06:16:57.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:57.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:57.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:16:57.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:16:57.02$vck44/va=6,4 2006.257.06:16:57.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.06:16:57.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.06:16:57.02#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:57.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:57.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:57.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:57.08#ibcon#enter wrdev, iclass 30, count 2 2006.257.06:16:57.08#ibcon#first serial, iclass 30, count 2 2006.257.06:16:57.08#ibcon#enter sib2, iclass 30, count 2 2006.257.06:16:57.08#ibcon#flushed, iclass 30, count 2 2006.257.06:16:57.08#ibcon#about to write, iclass 30, count 2 2006.257.06:16:57.08#ibcon#wrote, iclass 30, count 2 2006.257.06:16:57.08#ibcon#about to read 3, iclass 30, count 2 2006.257.06:16:57.10#ibcon#read 3, iclass 30, count 2 2006.257.06:16:57.10#ibcon#about to read 4, iclass 30, count 2 2006.257.06:16:57.10#ibcon#read 4, iclass 30, count 2 2006.257.06:16:57.10#ibcon#about to read 5, iclass 30, count 2 2006.257.06:16:57.10#ibcon#read 5, iclass 30, count 2 2006.257.06:16:57.10#ibcon#about to read 6, iclass 30, count 2 2006.257.06:16:57.10#ibcon#read 6, iclass 30, count 2 2006.257.06:16:57.10#ibcon#end of sib2, iclass 30, count 2 2006.257.06:16:57.10#ibcon#*mode == 0, iclass 30, count 2 2006.257.06:16:57.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.06:16:57.10#ibcon#[25=AT06-04\r\n] 2006.257.06:16:57.10#ibcon#*before write, iclass 30, count 2 2006.257.06:16:57.10#ibcon#enter sib2, iclass 30, count 2 2006.257.06:16:57.10#ibcon#flushed, iclass 30, count 2 2006.257.06:16:57.10#ibcon#about to write, iclass 30, count 2 2006.257.06:16:57.10#ibcon#wrote, iclass 30, count 2 2006.257.06:16:57.10#ibcon#about to read 3, iclass 30, count 2 2006.257.06:16:57.13#ibcon#read 3, iclass 30, count 2 2006.257.06:16:57.13#ibcon#about to read 4, iclass 30, count 2 2006.257.06:16:57.13#ibcon#read 4, iclass 30, count 2 2006.257.06:16:57.13#ibcon#about to read 5, iclass 30, count 2 2006.257.06:16:57.13#ibcon#read 5, iclass 30, count 2 2006.257.06:16:57.13#ibcon#about to read 6, iclass 30, count 2 2006.257.06:16:57.13#ibcon#read 6, iclass 30, count 2 2006.257.06:16:57.13#ibcon#end of sib2, iclass 30, count 2 2006.257.06:16:57.13#ibcon#*after write, iclass 30, count 2 2006.257.06:16:57.13#ibcon#*before return 0, iclass 30, count 2 2006.257.06:16:57.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:57.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:57.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.06:16:57.13#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:57.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:57.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:57.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:57.25#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:16:57.25#ibcon#first serial, iclass 30, count 0 2006.257.06:16:57.25#ibcon#enter sib2, iclass 30, count 0 2006.257.06:16:57.25#ibcon#flushed, iclass 30, count 0 2006.257.06:16:57.25#ibcon#about to write, iclass 30, count 0 2006.257.06:16:57.25#ibcon#wrote, iclass 30, count 0 2006.257.06:16:57.25#ibcon#about to read 3, iclass 30, count 0 2006.257.06:16:57.27#ibcon#read 3, iclass 30, count 0 2006.257.06:16:57.27#ibcon#about to read 4, iclass 30, count 0 2006.257.06:16:57.27#ibcon#read 4, iclass 30, count 0 2006.257.06:16:57.27#ibcon#about to read 5, iclass 30, count 0 2006.257.06:16:57.27#ibcon#read 5, iclass 30, count 0 2006.257.06:16:57.27#ibcon#about to read 6, iclass 30, count 0 2006.257.06:16:57.27#ibcon#read 6, iclass 30, count 0 2006.257.06:16:57.27#ibcon#end of sib2, iclass 30, count 0 2006.257.06:16:57.27#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:16:57.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:16:57.27#ibcon#[25=USB\r\n] 2006.257.06:16:57.27#ibcon#*before write, iclass 30, count 0 2006.257.06:16:57.27#ibcon#enter sib2, iclass 30, count 0 2006.257.06:16:57.27#ibcon#flushed, iclass 30, count 0 2006.257.06:16:57.27#ibcon#about to write, iclass 30, count 0 2006.257.06:16:57.27#ibcon#wrote, iclass 30, count 0 2006.257.06:16:57.27#ibcon#about to read 3, iclass 30, count 0 2006.257.06:16:57.30#ibcon#read 3, iclass 30, count 0 2006.257.06:16:57.30#ibcon#about to read 4, iclass 30, count 0 2006.257.06:16:57.30#ibcon#read 4, iclass 30, count 0 2006.257.06:16:57.30#ibcon#about to read 5, iclass 30, count 0 2006.257.06:16:57.30#ibcon#read 5, iclass 30, count 0 2006.257.06:16:57.30#ibcon#about to read 6, iclass 30, count 0 2006.257.06:16:57.30#ibcon#read 6, iclass 30, count 0 2006.257.06:16:57.30#ibcon#end of sib2, iclass 30, count 0 2006.257.06:16:57.30#ibcon#*after write, iclass 30, count 0 2006.257.06:16:57.30#ibcon#*before return 0, iclass 30, count 0 2006.257.06:16:57.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:57.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:57.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:16:57.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:16:57.30$vck44/valo=7,864.99 2006.257.06:16:57.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.06:16:57.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.06:16:57.30#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:57.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:16:57.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:16:57.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:16:57.30#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:16:57.30#ibcon#first serial, iclass 32, count 0 2006.257.06:16:57.30#ibcon#enter sib2, iclass 32, count 0 2006.257.06:16:57.30#ibcon#flushed, iclass 32, count 0 2006.257.06:16:57.30#ibcon#about to write, iclass 32, count 0 2006.257.06:16:57.30#ibcon#wrote, iclass 32, count 0 2006.257.06:16:57.30#ibcon#about to read 3, iclass 32, count 0 2006.257.06:16:57.32#ibcon#read 3, iclass 32, count 0 2006.257.06:16:57.32#ibcon#about to read 4, iclass 32, count 0 2006.257.06:16:57.32#ibcon#read 4, iclass 32, count 0 2006.257.06:16:57.32#ibcon#about to read 5, iclass 32, count 0 2006.257.06:16:57.32#ibcon#read 5, iclass 32, count 0 2006.257.06:16:57.32#ibcon#about to read 6, iclass 32, count 0 2006.257.06:16:57.32#ibcon#read 6, iclass 32, count 0 2006.257.06:16:57.32#ibcon#end of sib2, iclass 32, count 0 2006.257.06:16:57.32#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:16:57.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:16:57.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:16:57.32#ibcon#*before write, iclass 32, count 0 2006.257.06:16:57.32#ibcon#enter sib2, iclass 32, count 0 2006.257.06:16:57.32#ibcon#flushed, iclass 32, count 0 2006.257.06:16:57.32#ibcon#about to write, iclass 32, count 0 2006.257.06:16:57.32#ibcon#wrote, iclass 32, count 0 2006.257.06:16:57.32#ibcon#about to read 3, iclass 32, count 0 2006.257.06:16:57.36#ibcon#read 3, iclass 32, count 0 2006.257.06:16:57.36#ibcon#about to read 4, iclass 32, count 0 2006.257.06:16:57.36#ibcon#read 4, iclass 32, count 0 2006.257.06:16:57.36#ibcon#about to read 5, iclass 32, count 0 2006.257.06:16:57.36#ibcon#read 5, iclass 32, count 0 2006.257.06:16:57.36#ibcon#about to read 6, iclass 32, count 0 2006.257.06:16:57.36#ibcon#read 6, iclass 32, count 0 2006.257.06:16:57.36#ibcon#end of sib2, iclass 32, count 0 2006.257.06:16:57.36#ibcon#*after write, iclass 32, count 0 2006.257.06:16:57.36#ibcon#*before return 0, iclass 32, count 0 2006.257.06:16:57.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:16:57.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:16:57.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:16:57.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:16:57.36$vck44/va=7,4 2006.257.06:16:57.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.06:16:57.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.06:16:57.36#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:57.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:16:57.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:16:57.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:16:57.42#ibcon#enter wrdev, iclass 34, count 2 2006.257.06:16:57.42#ibcon#first serial, iclass 34, count 2 2006.257.06:16:57.42#ibcon#enter sib2, iclass 34, count 2 2006.257.06:16:57.42#ibcon#flushed, iclass 34, count 2 2006.257.06:16:57.42#ibcon#about to write, iclass 34, count 2 2006.257.06:16:57.42#ibcon#wrote, iclass 34, count 2 2006.257.06:16:57.42#ibcon#about to read 3, iclass 34, count 2 2006.257.06:16:57.44#ibcon#read 3, iclass 34, count 2 2006.257.06:16:57.44#ibcon#about to read 4, iclass 34, count 2 2006.257.06:16:57.44#ibcon#read 4, iclass 34, count 2 2006.257.06:16:57.44#ibcon#about to read 5, iclass 34, count 2 2006.257.06:16:57.44#ibcon#read 5, iclass 34, count 2 2006.257.06:16:57.44#ibcon#about to read 6, iclass 34, count 2 2006.257.06:16:57.44#ibcon#read 6, iclass 34, count 2 2006.257.06:16:57.44#ibcon#end of sib2, iclass 34, count 2 2006.257.06:16:57.44#ibcon#*mode == 0, iclass 34, count 2 2006.257.06:16:57.44#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.06:16:57.44#ibcon#[25=AT07-04\r\n] 2006.257.06:16:57.44#ibcon#*before write, iclass 34, count 2 2006.257.06:16:57.44#ibcon#enter sib2, iclass 34, count 2 2006.257.06:16:57.44#ibcon#flushed, iclass 34, count 2 2006.257.06:16:57.44#ibcon#about to write, iclass 34, count 2 2006.257.06:16:57.44#ibcon#wrote, iclass 34, count 2 2006.257.06:16:57.44#ibcon#about to read 3, iclass 34, count 2 2006.257.06:16:57.47#ibcon#read 3, iclass 34, count 2 2006.257.06:16:57.47#ibcon#about to read 4, iclass 34, count 2 2006.257.06:16:57.47#ibcon#read 4, iclass 34, count 2 2006.257.06:16:57.47#ibcon#about to read 5, iclass 34, count 2 2006.257.06:16:57.47#ibcon#read 5, iclass 34, count 2 2006.257.06:16:57.47#ibcon#about to read 6, iclass 34, count 2 2006.257.06:16:57.47#ibcon#read 6, iclass 34, count 2 2006.257.06:16:57.47#ibcon#end of sib2, iclass 34, count 2 2006.257.06:16:57.47#ibcon#*after write, iclass 34, count 2 2006.257.06:16:57.47#ibcon#*before return 0, iclass 34, count 2 2006.257.06:16:57.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:16:57.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:16:57.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.06:16:57.47#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:57.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:16:57.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:16:57.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:16:57.59#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:16:57.59#ibcon#first serial, iclass 34, count 0 2006.257.06:16:57.59#ibcon#enter sib2, iclass 34, count 0 2006.257.06:16:57.59#ibcon#flushed, iclass 34, count 0 2006.257.06:16:57.59#ibcon#about to write, iclass 34, count 0 2006.257.06:16:57.59#ibcon#wrote, iclass 34, count 0 2006.257.06:16:57.59#ibcon#about to read 3, iclass 34, count 0 2006.257.06:16:57.61#ibcon#read 3, iclass 34, count 0 2006.257.06:16:57.61#ibcon#about to read 4, iclass 34, count 0 2006.257.06:16:57.61#ibcon#read 4, iclass 34, count 0 2006.257.06:16:57.61#ibcon#about to read 5, iclass 34, count 0 2006.257.06:16:57.61#ibcon#read 5, iclass 34, count 0 2006.257.06:16:57.61#ibcon#about to read 6, iclass 34, count 0 2006.257.06:16:57.61#ibcon#read 6, iclass 34, count 0 2006.257.06:16:57.61#ibcon#end of sib2, iclass 34, count 0 2006.257.06:16:57.61#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:16:57.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:16:57.61#ibcon#[25=USB\r\n] 2006.257.06:16:57.61#ibcon#*before write, iclass 34, count 0 2006.257.06:16:57.61#ibcon#enter sib2, iclass 34, count 0 2006.257.06:16:57.61#ibcon#flushed, iclass 34, count 0 2006.257.06:16:57.61#ibcon#about to write, iclass 34, count 0 2006.257.06:16:57.61#ibcon#wrote, iclass 34, count 0 2006.257.06:16:57.61#ibcon#about to read 3, iclass 34, count 0 2006.257.06:16:57.64#ibcon#read 3, iclass 34, count 0 2006.257.06:16:57.64#ibcon#about to read 4, iclass 34, count 0 2006.257.06:16:57.64#ibcon#read 4, iclass 34, count 0 2006.257.06:16:57.64#ibcon#about to read 5, iclass 34, count 0 2006.257.06:16:57.64#ibcon#read 5, iclass 34, count 0 2006.257.06:16:57.64#ibcon#about to read 6, iclass 34, count 0 2006.257.06:16:57.64#ibcon#read 6, iclass 34, count 0 2006.257.06:16:57.64#ibcon#end of sib2, iclass 34, count 0 2006.257.06:16:57.64#ibcon#*after write, iclass 34, count 0 2006.257.06:16:57.64#ibcon#*before return 0, iclass 34, count 0 2006.257.06:16:57.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:16:57.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:16:57.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:16:57.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:16:57.64$vck44/valo=8,884.99 2006.257.06:16:57.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.06:16:57.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.06:16:57.64#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:57.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:16:57.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:16:57.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:16:57.64#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:16:57.64#ibcon#first serial, iclass 36, count 0 2006.257.06:16:57.64#ibcon#enter sib2, iclass 36, count 0 2006.257.06:16:57.64#ibcon#flushed, iclass 36, count 0 2006.257.06:16:57.64#ibcon#about to write, iclass 36, count 0 2006.257.06:16:57.64#ibcon#wrote, iclass 36, count 0 2006.257.06:16:57.64#ibcon#about to read 3, iclass 36, count 0 2006.257.06:16:57.66#ibcon#read 3, iclass 36, count 0 2006.257.06:16:57.66#ibcon#about to read 4, iclass 36, count 0 2006.257.06:16:57.66#ibcon#read 4, iclass 36, count 0 2006.257.06:16:57.66#ibcon#about to read 5, iclass 36, count 0 2006.257.06:16:57.66#ibcon#read 5, iclass 36, count 0 2006.257.06:16:57.66#ibcon#about to read 6, iclass 36, count 0 2006.257.06:16:57.66#ibcon#read 6, iclass 36, count 0 2006.257.06:16:57.66#ibcon#end of sib2, iclass 36, count 0 2006.257.06:16:57.66#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:16:57.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:16:57.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:16:57.66#ibcon#*before write, iclass 36, count 0 2006.257.06:16:57.66#ibcon#enter sib2, iclass 36, count 0 2006.257.06:16:57.66#ibcon#flushed, iclass 36, count 0 2006.257.06:16:57.66#ibcon#about to write, iclass 36, count 0 2006.257.06:16:57.66#ibcon#wrote, iclass 36, count 0 2006.257.06:16:57.66#ibcon#about to read 3, iclass 36, count 0 2006.257.06:16:57.70#ibcon#read 3, iclass 36, count 0 2006.257.06:16:57.70#ibcon#about to read 4, iclass 36, count 0 2006.257.06:16:57.70#ibcon#read 4, iclass 36, count 0 2006.257.06:16:57.70#ibcon#about to read 5, iclass 36, count 0 2006.257.06:16:57.70#ibcon#read 5, iclass 36, count 0 2006.257.06:16:57.70#ibcon#about to read 6, iclass 36, count 0 2006.257.06:16:57.70#ibcon#read 6, iclass 36, count 0 2006.257.06:16:57.70#ibcon#end of sib2, iclass 36, count 0 2006.257.06:16:57.70#ibcon#*after write, iclass 36, count 0 2006.257.06:16:57.70#ibcon#*before return 0, iclass 36, count 0 2006.257.06:16:57.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:16:57.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:16:57.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:16:57.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:16:57.70$vck44/va=8,4 2006.257.06:16:57.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.06:16:57.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.06:16:57.70#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:57.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:16:57.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:16:57.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:16:57.76#ibcon#enter wrdev, iclass 38, count 2 2006.257.06:16:57.76#ibcon#first serial, iclass 38, count 2 2006.257.06:16:57.76#ibcon#enter sib2, iclass 38, count 2 2006.257.06:16:57.76#ibcon#flushed, iclass 38, count 2 2006.257.06:16:57.76#ibcon#about to write, iclass 38, count 2 2006.257.06:16:57.76#ibcon#wrote, iclass 38, count 2 2006.257.06:16:57.76#ibcon#about to read 3, iclass 38, count 2 2006.257.06:16:57.78#ibcon#read 3, iclass 38, count 2 2006.257.06:16:57.78#ibcon#about to read 4, iclass 38, count 2 2006.257.06:16:57.78#ibcon#read 4, iclass 38, count 2 2006.257.06:16:57.78#ibcon#about to read 5, iclass 38, count 2 2006.257.06:16:57.78#ibcon#read 5, iclass 38, count 2 2006.257.06:16:57.78#ibcon#about to read 6, iclass 38, count 2 2006.257.06:16:57.78#ibcon#read 6, iclass 38, count 2 2006.257.06:16:57.78#ibcon#end of sib2, iclass 38, count 2 2006.257.06:16:57.78#ibcon#*mode == 0, iclass 38, count 2 2006.257.06:16:57.78#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.06:16:57.78#ibcon#[25=AT08-04\r\n] 2006.257.06:16:57.78#ibcon#*before write, iclass 38, count 2 2006.257.06:16:57.78#ibcon#enter sib2, iclass 38, count 2 2006.257.06:16:57.78#ibcon#flushed, iclass 38, count 2 2006.257.06:16:57.78#ibcon#about to write, iclass 38, count 2 2006.257.06:16:57.78#ibcon#wrote, iclass 38, count 2 2006.257.06:16:57.78#ibcon#about to read 3, iclass 38, count 2 2006.257.06:16:57.81#ibcon#read 3, iclass 38, count 2 2006.257.06:16:57.81#ibcon#about to read 4, iclass 38, count 2 2006.257.06:16:57.81#ibcon#read 4, iclass 38, count 2 2006.257.06:16:57.81#ibcon#about to read 5, iclass 38, count 2 2006.257.06:16:57.81#ibcon#read 5, iclass 38, count 2 2006.257.06:16:57.81#ibcon#about to read 6, iclass 38, count 2 2006.257.06:16:57.81#ibcon#read 6, iclass 38, count 2 2006.257.06:16:57.81#ibcon#end of sib2, iclass 38, count 2 2006.257.06:16:57.81#ibcon#*after write, iclass 38, count 2 2006.257.06:16:57.81#ibcon#*before return 0, iclass 38, count 2 2006.257.06:16:57.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:16:57.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:16:57.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.06:16:57.81#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:57.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:16:57.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:16:57.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:16:57.93#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:16:57.93#ibcon#first serial, iclass 38, count 0 2006.257.06:16:57.93#ibcon#enter sib2, iclass 38, count 0 2006.257.06:16:57.93#ibcon#flushed, iclass 38, count 0 2006.257.06:16:57.93#ibcon#about to write, iclass 38, count 0 2006.257.06:16:57.93#ibcon#wrote, iclass 38, count 0 2006.257.06:16:57.93#ibcon#about to read 3, iclass 38, count 0 2006.257.06:16:57.95#ibcon#read 3, iclass 38, count 0 2006.257.06:16:57.95#ibcon#about to read 4, iclass 38, count 0 2006.257.06:16:57.95#ibcon#read 4, iclass 38, count 0 2006.257.06:16:57.95#ibcon#about to read 5, iclass 38, count 0 2006.257.06:16:57.95#ibcon#read 5, iclass 38, count 0 2006.257.06:16:57.95#ibcon#about to read 6, iclass 38, count 0 2006.257.06:16:57.95#ibcon#read 6, iclass 38, count 0 2006.257.06:16:57.95#ibcon#end of sib2, iclass 38, count 0 2006.257.06:16:57.95#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:16:57.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:16:57.95#ibcon#[25=USB\r\n] 2006.257.06:16:57.95#ibcon#*before write, iclass 38, count 0 2006.257.06:16:57.95#ibcon#enter sib2, iclass 38, count 0 2006.257.06:16:57.95#ibcon#flushed, iclass 38, count 0 2006.257.06:16:57.95#ibcon#about to write, iclass 38, count 0 2006.257.06:16:57.95#ibcon#wrote, iclass 38, count 0 2006.257.06:16:57.95#ibcon#about to read 3, iclass 38, count 0 2006.257.06:16:57.98#ibcon#read 3, iclass 38, count 0 2006.257.06:16:57.98#ibcon#about to read 4, iclass 38, count 0 2006.257.06:16:57.98#ibcon#read 4, iclass 38, count 0 2006.257.06:16:57.98#ibcon#about to read 5, iclass 38, count 0 2006.257.06:16:57.98#ibcon#read 5, iclass 38, count 0 2006.257.06:16:57.98#ibcon#about to read 6, iclass 38, count 0 2006.257.06:16:57.98#ibcon#read 6, iclass 38, count 0 2006.257.06:16:57.98#ibcon#end of sib2, iclass 38, count 0 2006.257.06:16:57.98#ibcon#*after write, iclass 38, count 0 2006.257.06:16:57.98#ibcon#*before return 0, iclass 38, count 0 2006.257.06:16:57.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:16:57.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:16:57.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:16:57.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:16:57.98$vck44/vblo=1,629.99 2006.257.06:16:57.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.06:16:57.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.06:16:57.98#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:57.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:16:57.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:16:57.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:16:57.98#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:16:57.98#ibcon#first serial, iclass 40, count 0 2006.257.06:16:57.98#ibcon#enter sib2, iclass 40, count 0 2006.257.06:16:57.98#ibcon#flushed, iclass 40, count 0 2006.257.06:16:57.98#ibcon#about to write, iclass 40, count 0 2006.257.06:16:57.98#ibcon#wrote, iclass 40, count 0 2006.257.06:16:57.98#ibcon#about to read 3, iclass 40, count 0 2006.257.06:16:58.00#ibcon#read 3, iclass 40, count 0 2006.257.06:16:58.00#ibcon#about to read 4, iclass 40, count 0 2006.257.06:16:58.00#ibcon#read 4, iclass 40, count 0 2006.257.06:16:58.00#ibcon#about to read 5, iclass 40, count 0 2006.257.06:16:58.00#ibcon#read 5, iclass 40, count 0 2006.257.06:16:58.00#ibcon#about to read 6, iclass 40, count 0 2006.257.06:16:58.00#ibcon#read 6, iclass 40, count 0 2006.257.06:16:58.00#ibcon#end of sib2, iclass 40, count 0 2006.257.06:16:58.00#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:16:58.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:16:58.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:16:58.00#ibcon#*before write, iclass 40, count 0 2006.257.06:16:58.00#ibcon#enter sib2, iclass 40, count 0 2006.257.06:16:58.00#ibcon#flushed, iclass 40, count 0 2006.257.06:16:58.00#ibcon#about to write, iclass 40, count 0 2006.257.06:16:58.00#ibcon#wrote, iclass 40, count 0 2006.257.06:16:58.00#ibcon#about to read 3, iclass 40, count 0 2006.257.06:16:58.04#ibcon#read 3, iclass 40, count 0 2006.257.06:16:58.04#ibcon#about to read 4, iclass 40, count 0 2006.257.06:16:58.04#ibcon#read 4, iclass 40, count 0 2006.257.06:16:58.04#ibcon#about to read 5, iclass 40, count 0 2006.257.06:16:58.04#ibcon#read 5, iclass 40, count 0 2006.257.06:16:58.04#ibcon#about to read 6, iclass 40, count 0 2006.257.06:16:58.04#ibcon#read 6, iclass 40, count 0 2006.257.06:16:58.04#ibcon#end of sib2, iclass 40, count 0 2006.257.06:16:58.04#ibcon#*after write, iclass 40, count 0 2006.257.06:16:58.04#ibcon#*before return 0, iclass 40, count 0 2006.257.06:16:58.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:16:58.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:16:58.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:16:58.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:16:58.04$vck44/vb=1,4 2006.257.06:16:58.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.06:16:58.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.06:16:58.04#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:58.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:16:58.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:16:58.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:16:58.04#ibcon#enter wrdev, iclass 4, count 2 2006.257.06:16:58.04#ibcon#first serial, iclass 4, count 2 2006.257.06:16:58.04#ibcon#enter sib2, iclass 4, count 2 2006.257.06:16:58.04#ibcon#flushed, iclass 4, count 2 2006.257.06:16:58.04#ibcon#about to write, iclass 4, count 2 2006.257.06:16:58.04#ibcon#wrote, iclass 4, count 2 2006.257.06:16:58.04#ibcon#about to read 3, iclass 4, count 2 2006.257.06:16:58.06#ibcon#read 3, iclass 4, count 2 2006.257.06:16:58.06#ibcon#about to read 4, iclass 4, count 2 2006.257.06:16:58.06#ibcon#read 4, iclass 4, count 2 2006.257.06:16:58.06#ibcon#about to read 5, iclass 4, count 2 2006.257.06:16:58.06#ibcon#read 5, iclass 4, count 2 2006.257.06:16:58.06#ibcon#about to read 6, iclass 4, count 2 2006.257.06:16:58.06#ibcon#read 6, iclass 4, count 2 2006.257.06:16:58.06#ibcon#end of sib2, iclass 4, count 2 2006.257.06:16:58.06#ibcon#*mode == 0, iclass 4, count 2 2006.257.06:16:58.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.06:16:58.06#ibcon#[27=AT01-04\r\n] 2006.257.06:16:58.06#ibcon#*before write, iclass 4, count 2 2006.257.06:16:58.06#ibcon#enter sib2, iclass 4, count 2 2006.257.06:16:58.06#ibcon#flushed, iclass 4, count 2 2006.257.06:16:58.06#ibcon#about to write, iclass 4, count 2 2006.257.06:16:58.06#ibcon#wrote, iclass 4, count 2 2006.257.06:16:58.06#ibcon#about to read 3, iclass 4, count 2 2006.257.06:16:58.09#ibcon#read 3, iclass 4, count 2 2006.257.06:16:58.09#ibcon#about to read 4, iclass 4, count 2 2006.257.06:16:58.09#ibcon#read 4, iclass 4, count 2 2006.257.06:16:58.09#ibcon#about to read 5, iclass 4, count 2 2006.257.06:16:58.09#ibcon#read 5, iclass 4, count 2 2006.257.06:16:58.09#ibcon#about to read 6, iclass 4, count 2 2006.257.06:16:58.09#ibcon#read 6, iclass 4, count 2 2006.257.06:16:58.09#ibcon#end of sib2, iclass 4, count 2 2006.257.06:16:58.09#ibcon#*after write, iclass 4, count 2 2006.257.06:16:58.09#ibcon#*before return 0, iclass 4, count 2 2006.257.06:16:58.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:16:58.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:16:58.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.06:16:58.09#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:58.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:16:58.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:16:58.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:16:58.21#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:16:58.21#ibcon#first serial, iclass 4, count 0 2006.257.06:16:58.21#ibcon#enter sib2, iclass 4, count 0 2006.257.06:16:58.21#ibcon#flushed, iclass 4, count 0 2006.257.06:16:58.21#ibcon#about to write, iclass 4, count 0 2006.257.06:16:58.21#ibcon#wrote, iclass 4, count 0 2006.257.06:16:58.21#ibcon#about to read 3, iclass 4, count 0 2006.257.06:16:58.23#ibcon#read 3, iclass 4, count 0 2006.257.06:16:58.23#ibcon#about to read 4, iclass 4, count 0 2006.257.06:16:58.23#ibcon#read 4, iclass 4, count 0 2006.257.06:16:58.23#ibcon#about to read 5, iclass 4, count 0 2006.257.06:16:58.23#ibcon#read 5, iclass 4, count 0 2006.257.06:16:58.23#ibcon#about to read 6, iclass 4, count 0 2006.257.06:16:58.23#ibcon#read 6, iclass 4, count 0 2006.257.06:16:58.23#ibcon#end of sib2, iclass 4, count 0 2006.257.06:16:58.23#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:16:58.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:16:58.23#ibcon#[27=USB\r\n] 2006.257.06:16:58.23#ibcon#*before write, iclass 4, count 0 2006.257.06:16:58.23#ibcon#enter sib2, iclass 4, count 0 2006.257.06:16:58.23#ibcon#flushed, iclass 4, count 0 2006.257.06:16:58.23#ibcon#about to write, iclass 4, count 0 2006.257.06:16:58.23#ibcon#wrote, iclass 4, count 0 2006.257.06:16:58.23#ibcon#about to read 3, iclass 4, count 0 2006.257.06:16:58.26#ibcon#read 3, iclass 4, count 0 2006.257.06:16:58.26#ibcon#about to read 4, iclass 4, count 0 2006.257.06:16:58.26#ibcon#read 4, iclass 4, count 0 2006.257.06:16:58.26#ibcon#about to read 5, iclass 4, count 0 2006.257.06:16:58.26#ibcon#read 5, iclass 4, count 0 2006.257.06:16:58.26#ibcon#about to read 6, iclass 4, count 0 2006.257.06:16:58.26#ibcon#read 6, iclass 4, count 0 2006.257.06:16:58.26#ibcon#end of sib2, iclass 4, count 0 2006.257.06:16:58.26#ibcon#*after write, iclass 4, count 0 2006.257.06:16:58.26#ibcon#*before return 0, iclass 4, count 0 2006.257.06:16:58.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:16:58.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:16:58.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:16:58.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:16:58.26$vck44/vblo=2,634.99 2006.257.06:16:58.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.06:16:58.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.06:16:58.26#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:58.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:58.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:58.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:58.26#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:16:58.26#ibcon#first serial, iclass 6, count 0 2006.257.06:16:58.26#ibcon#enter sib2, iclass 6, count 0 2006.257.06:16:58.26#ibcon#flushed, iclass 6, count 0 2006.257.06:16:58.26#ibcon#about to write, iclass 6, count 0 2006.257.06:16:58.26#ibcon#wrote, iclass 6, count 0 2006.257.06:16:58.26#ibcon#about to read 3, iclass 6, count 0 2006.257.06:16:58.28#ibcon#read 3, iclass 6, count 0 2006.257.06:16:58.28#ibcon#about to read 4, iclass 6, count 0 2006.257.06:16:58.28#ibcon#read 4, iclass 6, count 0 2006.257.06:16:58.28#ibcon#about to read 5, iclass 6, count 0 2006.257.06:16:58.28#ibcon#read 5, iclass 6, count 0 2006.257.06:16:58.28#ibcon#about to read 6, iclass 6, count 0 2006.257.06:16:58.28#ibcon#read 6, iclass 6, count 0 2006.257.06:16:58.28#ibcon#end of sib2, iclass 6, count 0 2006.257.06:16:58.28#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:16:58.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:16:58.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:16:58.28#ibcon#*before write, iclass 6, count 0 2006.257.06:16:58.28#ibcon#enter sib2, iclass 6, count 0 2006.257.06:16:58.28#ibcon#flushed, iclass 6, count 0 2006.257.06:16:58.28#ibcon#about to write, iclass 6, count 0 2006.257.06:16:58.28#ibcon#wrote, iclass 6, count 0 2006.257.06:16:58.28#ibcon#about to read 3, iclass 6, count 0 2006.257.06:16:58.32#ibcon#read 3, iclass 6, count 0 2006.257.06:16:58.32#ibcon#about to read 4, iclass 6, count 0 2006.257.06:16:58.32#ibcon#read 4, iclass 6, count 0 2006.257.06:16:58.32#ibcon#about to read 5, iclass 6, count 0 2006.257.06:16:58.32#ibcon#read 5, iclass 6, count 0 2006.257.06:16:58.32#ibcon#about to read 6, iclass 6, count 0 2006.257.06:16:58.32#ibcon#read 6, iclass 6, count 0 2006.257.06:16:58.32#ibcon#end of sib2, iclass 6, count 0 2006.257.06:16:58.32#ibcon#*after write, iclass 6, count 0 2006.257.06:16:58.32#ibcon#*before return 0, iclass 6, count 0 2006.257.06:16:58.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:58.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:16:58.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:16:58.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:16:58.32$vck44/vb=2,5 2006.257.06:16:58.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.06:16:58.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.06:16:58.32#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:58.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:58.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:58.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:58.38#ibcon#enter wrdev, iclass 10, count 2 2006.257.06:16:58.38#ibcon#first serial, iclass 10, count 2 2006.257.06:16:58.38#ibcon#enter sib2, iclass 10, count 2 2006.257.06:16:58.38#ibcon#flushed, iclass 10, count 2 2006.257.06:16:58.38#ibcon#about to write, iclass 10, count 2 2006.257.06:16:58.38#ibcon#wrote, iclass 10, count 2 2006.257.06:16:58.38#ibcon#about to read 3, iclass 10, count 2 2006.257.06:16:58.40#ibcon#read 3, iclass 10, count 2 2006.257.06:16:58.40#ibcon#about to read 4, iclass 10, count 2 2006.257.06:16:58.40#ibcon#read 4, iclass 10, count 2 2006.257.06:16:58.40#ibcon#about to read 5, iclass 10, count 2 2006.257.06:16:58.40#ibcon#read 5, iclass 10, count 2 2006.257.06:16:58.40#ibcon#about to read 6, iclass 10, count 2 2006.257.06:16:58.40#ibcon#read 6, iclass 10, count 2 2006.257.06:16:58.40#ibcon#end of sib2, iclass 10, count 2 2006.257.06:16:58.40#ibcon#*mode == 0, iclass 10, count 2 2006.257.06:16:58.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.06:16:58.40#ibcon#[27=AT02-05\r\n] 2006.257.06:16:58.40#ibcon#*before write, iclass 10, count 2 2006.257.06:16:58.40#ibcon#enter sib2, iclass 10, count 2 2006.257.06:16:58.40#ibcon#flushed, iclass 10, count 2 2006.257.06:16:58.40#ibcon#about to write, iclass 10, count 2 2006.257.06:16:58.40#ibcon#wrote, iclass 10, count 2 2006.257.06:16:58.40#ibcon#about to read 3, iclass 10, count 2 2006.257.06:16:58.43#ibcon#read 3, iclass 10, count 2 2006.257.06:16:58.43#ibcon#about to read 4, iclass 10, count 2 2006.257.06:16:58.43#ibcon#read 4, iclass 10, count 2 2006.257.06:16:58.43#ibcon#about to read 5, iclass 10, count 2 2006.257.06:16:58.43#ibcon#read 5, iclass 10, count 2 2006.257.06:16:58.43#ibcon#about to read 6, iclass 10, count 2 2006.257.06:16:58.43#ibcon#read 6, iclass 10, count 2 2006.257.06:16:58.43#ibcon#end of sib2, iclass 10, count 2 2006.257.06:16:58.43#ibcon#*after write, iclass 10, count 2 2006.257.06:16:58.43#ibcon#*before return 0, iclass 10, count 2 2006.257.06:16:58.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:58.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:16:58.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.06:16:58.43#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:58.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:58.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:58.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:58.55#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:16:58.55#ibcon#first serial, iclass 10, count 0 2006.257.06:16:58.55#ibcon#enter sib2, iclass 10, count 0 2006.257.06:16:58.55#ibcon#flushed, iclass 10, count 0 2006.257.06:16:58.55#ibcon#about to write, iclass 10, count 0 2006.257.06:16:58.55#ibcon#wrote, iclass 10, count 0 2006.257.06:16:58.55#ibcon#about to read 3, iclass 10, count 0 2006.257.06:16:58.57#ibcon#read 3, iclass 10, count 0 2006.257.06:16:58.57#ibcon#about to read 4, iclass 10, count 0 2006.257.06:16:58.57#ibcon#read 4, iclass 10, count 0 2006.257.06:16:58.57#ibcon#about to read 5, iclass 10, count 0 2006.257.06:16:58.57#ibcon#read 5, iclass 10, count 0 2006.257.06:16:58.57#ibcon#about to read 6, iclass 10, count 0 2006.257.06:16:58.57#ibcon#read 6, iclass 10, count 0 2006.257.06:16:58.57#ibcon#end of sib2, iclass 10, count 0 2006.257.06:16:58.57#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:16:58.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:16:58.57#ibcon#[27=USB\r\n] 2006.257.06:16:58.57#ibcon#*before write, iclass 10, count 0 2006.257.06:16:58.57#ibcon#enter sib2, iclass 10, count 0 2006.257.06:16:58.57#ibcon#flushed, iclass 10, count 0 2006.257.06:16:58.57#ibcon#about to write, iclass 10, count 0 2006.257.06:16:58.57#ibcon#wrote, iclass 10, count 0 2006.257.06:16:58.57#ibcon#about to read 3, iclass 10, count 0 2006.257.06:16:58.60#ibcon#read 3, iclass 10, count 0 2006.257.06:16:58.60#ibcon#about to read 4, iclass 10, count 0 2006.257.06:16:58.60#ibcon#read 4, iclass 10, count 0 2006.257.06:16:58.60#ibcon#about to read 5, iclass 10, count 0 2006.257.06:16:58.60#ibcon#read 5, iclass 10, count 0 2006.257.06:16:58.60#ibcon#about to read 6, iclass 10, count 0 2006.257.06:16:58.60#ibcon#read 6, iclass 10, count 0 2006.257.06:16:58.60#ibcon#end of sib2, iclass 10, count 0 2006.257.06:16:58.60#ibcon#*after write, iclass 10, count 0 2006.257.06:16:58.60#ibcon#*before return 0, iclass 10, count 0 2006.257.06:16:58.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:58.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:16:58.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:16:58.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:16:58.60$vck44/vblo=3,649.99 2006.257.06:16:58.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.06:16:58.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.06:16:58.60#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:58.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:58.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:58.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:58.60#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:16:58.60#ibcon#first serial, iclass 12, count 0 2006.257.06:16:58.60#ibcon#enter sib2, iclass 12, count 0 2006.257.06:16:58.60#ibcon#flushed, iclass 12, count 0 2006.257.06:16:58.60#ibcon#about to write, iclass 12, count 0 2006.257.06:16:58.60#ibcon#wrote, iclass 12, count 0 2006.257.06:16:58.60#ibcon#about to read 3, iclass 12, count 0 2006.257.06:16:58.62#ibcon#read 3, iclass 12, count 0 2006.257.06:16:58.62#ibcon#about to read 4, iclass 12, count 0 2006.257.06:16:58.62#ibcon#read 4, iclass 12, count 0 2006.257.06:16:58.62#ibcon#about to read 5, iclass 12, count 0 2006.257.06:16:58.62#ibcon#read 5, iclass 12, count 0 2006.257.06:16:58.62#ibcon#about to read 6, iclass 12, count 0 2006.257.06:16:58.62#ibcon#read 6, iclass 12, count 0 2006.257.06:16:58.62#ibcon#end of sib2, iclass 12, count 0 2006.257.06:16:58.62#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:16:58.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:16:58.62#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:16:58.62#ibcon#*before write, iclass 12, count 0 2006.257.06:16:58.62#ibcon#enter sib2, iclass 12, count 0 2006.257.06:16:58.62#ibcon#flushed, iclass 12, count 0 2006.257.06:16:58.62#ibcon#about to write, iclass 12, count 0 2006.257.06:16:58.62#ibcon#wrote, iclass 12, count 0 2006.257.06:16:58.62#ibcon#about to read 3, iclass 12, count 0 2006.257.06:16:58.66#ibcon#read 3, iclass 12, count 0 2006.257.06:16:58.66#ibcon#about to read 4, iclass 12, count 0 2006.257.06:16:58.66#ibcon#read 4, iclass 12, count 0 2006.257.06:16:58.66#ibcon#about to read 5, iclass 12, count 0 2006.257.06:16:58.66#ibcon#read 5, iclass 12, count 0 2006.257.06:16:58.66#ibcon#about to read 6, iclass 12, count 0 2006.257.06:16:58.66#ibcon#read 6, iclass 12, count 0 2006.257.06:16:58.66#ibcon#end of sib2, iclass 12, count 0 2006.257.06:16:58.66#ibcon#*after write, iclass 12, count 0 2006.257.06:16:58.66#ibcon#*before return 0, iclass 12, count 0 2006.257.06:16:58.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:58.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:16:58.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:16:58.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:16:58.66$vck44/vb=3,4 2006.257.06:16:58.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.06:16:58.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.06:16:58.66#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:58.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:58.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:58.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:58.72#ibcon#enter wrdev, iclass 14, count 2 2006.257.06:16:58.72#ibcon#first serial, iclass 14, count 2 2006.257.06:16:58.72#ibcon#enter sib2, iclass 14, count 2 2006.257.06:16:58.72#ibcon#flushed, iclass 14, count 2 2006.257.06:16:58.72#ibcon#about to write, iclass 14, count 2 2006.257.06:16:58.72#ibcon#wrote, iclass 14, count 2 2006.257.06:16:58.72#ibcon#about to read 3, iclass 14, count 2 2006.257.06:16:58.74#ibcon#read 3, iclass 14, count 2 2006.257.06:16:58.74#ibcon#about to read 4, iclass 14, count 2 2006.257.06:16:58.74#ibcon#read 4, iclass 14, count 2 2006.257.06:16:58.74#ibcon#about to read 5, iclass 14, count 2 2006.257.06:16:58.74#ibcon#read 5, iclass 14, count 2 2006.257.06:16:58.74#ibcon#about to read 6, iclass 14, count 2 2006.257.06:16:58.74#ibcon#read 6, iclass 14, count 2 2006.257.06:16:58.74#ibcon#end of sib2, iclass 14, count 2 2006.257.06:16:58.74#ibcon#*mode == 0, iclass 14, count 2 2006.257.06:16:58.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.06:16:58.74#ibcon#[27=AT03-04\r\n] 2006.257.06:16:58.74#ibcon#*before write, iclass 14, count 2 2006.257.06:16:58.74#ibcon#enter sib2, iclass 14, count 2 2006.257.06:16:58.74#ibcon#flushed, iclass 14, count 2 2006.257.06:16:58.74#ibcon#about to write, iclass 14, count 2 2006.257.06:16:58.74#ibcon#wrote, iclass 14, count 2 2006.257.06:16:58.74#ibcon#about to read 3, iclass 14, count 2 2006.257.06:16:58.77#ibcon#read 3, iclass 14, count 2 2006.257.06:16:58.77#ibcon#about to read 4, iclass 14, count 2 2006.257.06:16:58.77#ibcon#read 4, iclass 14, count 2 2006.257.06:16:58.77#ibcon#about to read 5, iclass 14, count 2 2006.257.06:16:58.77#ibcon#read 5, iclass 14, count 2 2006.257.06:16:58.77#ibcon#about to read 6, iclass 14, count 2 2006.257.06:16:58.77#ibcon#read 6, iclass 14, count 2 2006.257.06:16:58.77#ibcon#end of sib2, iclass 14, count 2 2006.257.06:16:58.77#ibcon#*after write, iclass 14, count 2 2006.257.06:16:58.77#ibcon#*before return 0, iclass 14, count 2 2006.257.06:16:58.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:58.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:16:58.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.06:16:58.77#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:58.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:58.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:58.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:58.89#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:16:58.89#ibcon#first serial, iclass 14, count 0 2006.257.06:16:58.89#ibcon#enter sib2, iclass 14, count 0 2006.257.06:16:58.89#ibcon#flushed, iclass 14, count 0 2006.257.06:16:58.89#ibcon#about to write, iclass 14, count 0 2006.257.06:16:58.89#ibcon#wrote, iclass 14, count 0 2006.257.06:16:58.89#ibcon#about to read 3, iclass 14, count 0 2006.257.06:16:58.91#ibcon#read 3, iclass 14, count 0 2006.257.06:16:58.91#ibcon#about to read 4, iclass 14, count 0 2006.257.06:16:58.91#ibcon#read 4, iclass 14, count 0 2006.257.06:16:58.91#ibcon#about to read 5, iclass 14, count 0 2006.257.06:16:58.91#ibcon#read 5, iclass 14, count 0 2006.257.06:16:58.91#ibcon#about to read 6, iclass 14, count 0 2006.257.06:16:58.91#ibcon#read 6, iclass 14, count 0 2006.257.06:16:58.91#ibcon#end of sib2, iclass 14, count 0 2006.257.06:16:58.91#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:16:58.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:16:58.91#ibcon#[27=USB\r\n] 2006.257.06:16:58.91#ibcon#*before write, iclass 14, count 0 2006.257.06:16:58.91#ibcon#enter sib2, iclass 14, count 0 2006.257.06:16:58.91#ibcon#flushed, iclass 14, count 0 2006.257.06:16:58.91#ibcon#about to write, iclass 14, count 0 2006.257.06:16:58.91#ibcon#wrote, iclass 14, count 0 2006.257.06:16:58.91#ibcon#about to read 3, iclass 14, count 0 2006.257.06:16:58.94#ibcon#read 3, iclass 14, count 0 2006.257.06:16:58.94#ibcon#about to read 4, iclass 14, count 0 2006.257.06:16:58.94#ibcon#read 4, iclass 14, count 0 2006.257.06:16:58.94#ibcon#about to read 5, iclass 14, count 0 2006.257.06:16:58.94#ibcon#read 5, iclass 14, count 0 2006.257.06:16:58.94#ibcon#about to read 6, iclass 14, count 0 2006.257.06:16:58.94#ibcon#read 6, iclass 14, count 0 2006.257.06:16:58.94#ibcon#end of sib2, iclass 14, count 0 2006.257.06:16:58.94#ibcon#*after write, iclass 14, count 0 2006.257.06:16:58.94#ibcon#*before return 0, iclass 14, count 0 2006.257.06:16:58.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:58.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:16:58.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:16:58.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:16:58.94$vck44/vblo=4,679.99 2006.257.06:16:58.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.06:16:58.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.06:16:58.94#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:58.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:58.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:58.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:58.94#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:16:58.94#ibcon#first serial, iclass 16, count 0 2006.257.06:16:58.94#ibcon#enter sib2, iclass 16, count 0 2006.257.06:16:58.94#ibcon#flushed, iclass 16, count 0 2006.257.06:16:58.94#ibcon#about to write, iclass 16, count 0 2006.257.06:16:58.94#ibcon#wrote, iclass 16, count 0 2006.257.06:16:58.94#ibcon#about to read 3, iclass 16, count 0 2006.257.06:16:58.96#ibcon#read 3, iclass 16, count 0 2006.257.06:16:58.96#ibcon#about to read 4, iclass 16, count 0 2006.257.06:16:58.96#ibcon#read 4, iclass 16, count 0 2006.257.06:16:58.96#ibcon#about to read 5, iclass 16, count 0 2006.257.06:16:58.96#ibcon#read 5, iclass 16, count 0 2006.257.06:16:58.96#ibcon#about to read 6, iclass 16, count 0 2006.257.06:16:58.96#ibcon#read 6, iclass 16, count 0 2006.257.06:16:58.96#ibcon#end of sib2, iclass 16, count 0 2006.257.06:16:58.96#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:16:58.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:16:58.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:16:58.96#ibcon#*before write, iclass 16, count 0 2006.257.06:16:58.96#ibcon#enter sib2, iclass 16, count 0 2006.257.06:16:58.96#ibcon#flushed, iclass 16, count 0 2006.257.06:16:58.96#ibcon#about to write, iclass 16, count 0 2006.257.06:16:58.96#ibcon#wrote, iclass 16, count 0 2006.257.06:16:58.96#ibcon#about to read 3, iclass 16, count 0 2006.257.06:16:59.00#ibcon#read 3, iclass 16, count 0 2006.257.06:16:59.00#ibcon#about to read 4, iclass 16, count 0 2006.257.06:16:59.00#ibcon#read 4, iclass 16, count 0 2006.257.06:16:59.00#ibcon#about to read 5, iclass 16, count 0 2006.257.06:16:59.00#ibcon#read 5, iclass 16, count 0 2006.257.06:16:59.00#ibcon#about to read 6, iclass 16, count 0 2006.257.06:16:59.00#ibcon#read 6, iclass 16, count 0 2006.257.06:16:59.00#ibcon#end of sib2, iclass 16, count 0 2006.257.06:16:59.00#ibcon#*after write, iclass 16, count 0 2006.257.06:16:59.00#ibcon#*before return 0, iclass 16, count 0 2006.257.06:16:59.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:59.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:16:59.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:16:59.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:16:59.00$vck44/vb=4,5 2006.257.06:16:59.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.06:16:59.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.06:16:59.00#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:59.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:59.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:59.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:59.06#ibcon#enter wrdev, iclass 18, count 2 2006.257.06:16:59.06#ibcon#first serial, iclass 18, count 2 2006.257.06:16:59.06#ibcon#enter sib2, iclass 18, count 2 2006.257.06:16:59.06#ibcon#flushed, iclass 18, count 2 2006.257.06:16:59.06#ibcon#about to write, iclass 18, count 2 2006.257.06:16:59.06#ibcon#wrote, iclass 18, count 2 2006.257.06:16:59.06#ibcon#about to read 3, iclass 18, count 2 2006.257.06:16:59.07#abcon#<5=/15 1.2 3.4 20.39 891012.2\r\n> 2006.257.06:16:59.08#ibcon#read 3, iclass 18, count 2 2006.257.06:16:59.08#ibcon#about to read 4, iclass 18, count 2 2006.257.06:16:59.08#ibcon#read 4, iclass 18, count 2 2006.257.06:16:59.08#ibcon#about to read 5, iclass 18, count 2 2006.257.06:16:59.08#ibcon#read 5, iclass 18, count 2 2006.257.06:16:59.08#ibcon#about to read 6, iclass 18, count 2 2006.257.06:16:59.08#ibcon#read 6, iclass 18, count 2 2006.257.06:16:59.08#ibcon#end of sib2, iclass 18, count 2 2006.257.06:16:59.08#ibcon#*mode == 0, iclass 18, count 2 2006.257.06:16:59.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.06:16:59.08#ibcon#[27=AT04-05\r\n] 2006.257.06:16:59.08#ibcon#*before write, iclass 18, count 2 2006.257.06:16:59.08#ibcon#enter sib2, iclass 18, count 2 2006.257.06:16:59.08#ibcon#flushed, iclass 18, count 2 2006.257.06:16:59.08#ibcon#about to write, iclass 18, count 2 2006.257.06:16:59.08#ibcon#wrote, iclass 18, count 2 2006.257.06:16:59.08#ibcon#about to read 3, iclass 18, count 2 2006.257.06:16:59.09#abcon#{5=INTERFACE CLEAR} 2006.257.06:16:59.11#ibcon#read 3, iclass 18, count 2 2006.257.06:16:59.11#ibcon#about to read 4, iclass 18, count 2 2006.257.06:16:59.11#ibcon#read 4, iclass 18, count 2 2006.257.06:16:59.11#ibcon#about to read 5, iclass 18, count 2 2006.257.06:16:59.11#ibcon#read 5, iclass 18, count 2 2006.257.06:16:59.11#ibcon#about to read 6, iclass 18, count 2 2006.257.06:16:59.11#ibcon#read 6, iclass 18, count 2 2006.257.06:16:59.11#ibcon#end of sib2, iclass 18, count 2 2006.257.06:16:59.11#ibcon#*after write, iclass 18, count 2 2006.257.06:16:59.11#ibcon#*before return 0, iclass 18, count 2 2006.257.06:16:59.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:59.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:16:59.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.06:16:59.11#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:59.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:59.15#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:16:59.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:59.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:59.23#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:16:59.23#ibcon#first serial, iclass 18, count 0 2006.257.06:16:59.23#ibcon#enter sib2, iclass 18, count 0 2006.257.06:16:59.23#ibcon#flushed, iclass 18, count 0 2006.257.06:16:59.23#ibcon#about to write, iclass 18, count 0 2006.257.06:16:59.23#ibcon#wrote, iclass 18, count 0 2006.257.06:16:59.23#ibcon#about to read 3, iclass 18, count 0 2006.257.06:16:59.25#ibcon#read 3, iclass 18, count 0 2006.257.06:16:59.25#ibcon#about to read 4, iclass 18, count 0 2006.257.06:16:59.25#ibcon#read 4, iclass 18, count 0 2006.257.06:16:59.25#ibcon#about to read 5, iclass 18, count 0 2006.257.06:16:59.25#ibcon#read 5, iclass 18, count 0 2006.257.06:16:59.25#ibcon#about to read 6, iclass 18, count 0 2006.257.06:16:59.25#ibcon#read 6, iclass 18, count 0 2006.257.06:16:59.25#ibcon#end of sib2, iclass 18, count 0 2006.257.06:16:59.25#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:16:59.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:16:59.25#ibcon#[27=USB\r\n] 2006.257.06:16:59.25#ibcon#*before write, iclass 18, count 0 2006.257.06:16:59.25#ibcon#enter sib2, iclass 18, count 0 2006.257.06:16:59.25#ibcon#flushed, iclass 18, count 0 2006.257.06:16:59.25#ibcon#about to write, iclass 18, count 0 2006.257.06:16:59.25#ibcon#wrote, iclass 18, count 0 2006.257.06:16:59.25#ibcon#about to read 3, iclass 18, count 0 2006.257.06:16:59.28#ibcon#read 3, iclass 18, count 0 2006.257.06:16:59.28#ibcon#about to read 4, iclass 18, count 0 2006.257.06:16:59.28#ibcon#read 4, iclass 18, count 0 2006.257.06:16:59.28#ibcon#about to read 5, iclass 18, count 0 2006.257.06:16:59.28#ibcon#read 5, iclass 18, count 0 2006.257.06:16:59.28#ibcon#about to read 6, iclass 18, count 0 2006.257.06:16:59.28#ibcon#read 6, iclass 18, count 0 2006.257.06:16:59.28#ibcon#end of sib2, iclass 18, count 0 2006.257.06:16:59.28#ibcon#*after write, iclass 18, count 0 2006.257.06:16:59.28#ibcon#*before return 0, iclass 18, count 0 2006.257.06:16:59.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:59.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:16:59.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:16:59.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:16:59.28$vck44/vblo=5,709.99 2006.257.06:16:59.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.06:16:59.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.06:16:59.28#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:59.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:59.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:59.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:59.28#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:16:59.28#ibcon#first serial, iclass 24, count 0 2006.257.06:16:59.28#ibcon#enter sib2, iclass 24, count 0 2006.257.06:16:59.28#ibcon#flushed, iclass 24, count 0 2006.257.06:16:59.28#ibcon#about to write, iclass 24, count 0 2006.257.06:16:59.28#ibcon#wrote, iclass 24, count 0 2006.257.06:16:59.28#ibcon#about to read 3, iclass 24, count 0 2006.257.06:16:59.30#ibcon#read 3, iclass 24, count 0 2006.257.06:16:59.30#ibcon#about to read 4, iclass 24, count 0 2006.257.06:16:59.30#ibcon#read 4, iclass 24, count 0 2006.257.06:16:59.30#ibcon#about to read 5, iclass 24, count 0 2006.257.06:16:59.30#ibcon#read 5, iclass 24, count 0 2006.257.06:16:59.30#ibcon#about to read 6, iclass 24, count 0 2006.257.06:16:59.30#ibcon#read 6, iclass 24, count 0 2006.257.06:16:59.30#ibcon#end of sib2, iclass 24, count 0 2006.257.06:16:59.30#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:16:59.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:16:59.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:16:59.30#ibcon#*before write, iclass 24, count 0 2006.257.06:16:59.30#ibcon#enter sib2, iclass 24, count 0 2006.257.06:16:59.30#ibcon#flushed, iclass 24, count 0 2006.257.06:16:59.30#ibcon#about to write, iclass 24, count 0 2006.257.06:16:59.30#ibcon#wrote, iclass 24, count 0 2006.257.06:16:59.30#ibcon#about to read 3, iclass 24, count 0 2006.257.06:16:59.34#ibcon#read 3, iclass 24, count 0 2006.257.06:16:59.34#ibcon#about to read 4, iclass 24, count 0 2006.257.06:16:59.34#ibcon#read 4, iclass 24, count 0 2006.257.06:16:59.34#ibcon#about to read 5, iclass 24, count 0 2006.257.06:16:59.34#ibcon#read 5, iclass 24, count 0 2006.257.06:16:59.34#ibcon#about to read 6, iclass 24, count 0 2006.257.06:16:59.34#ibcon#read 6, iclass 24, count 0 2006.257.06:16:59.34#ibcon#end of sib2, iclass 24, count 0 2006.257.06:16:59.34#ibcon#*after write, iclass 24, count 0 2006.257.06:16:59.34#ibcon#*before return 0, iclass 24, count 0 2006.257.06:16:59.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:59.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:16:59.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:16:59.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:16:59.34$vck44/vb=5,4 2006.257.06:16:59.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.06:16:59.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.06:16:59.34#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:59.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:59.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:59.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:59.40#ibcon#enter wrdev, iclass 26, count 2 2006.257.06:16:59.40#ibcon#first serial, iclass 26, count 2 2006.257.06:16:59.40#ibcon#enter sib2, iclass 26, count 2 2006.257.06:16:59.40#ibcon#flushed, iclass 26, count 2 2006.257.06:16:59.40#ibcon#about to write, iclass 26, count 2 2006.257.06:16:59.40#ibcon#wrote, iclass 26, count 2 2006.257.06:16:59.40#ibcon#about to read 3, iclass 26, count 2 2006.257.06:16:59.42#ibcon#read 3, iclass 26, count 2 2006.257.06:16:59.42#ibcon#about to read 4, iclass 26, count 2 2006.257.06:16:59.42#ibcon#read 4, iclass 26, count 2 2006.257.06:16:59.42#ibcon#about to read 5, iclass 26, count 2 2006.257.06:16:59.42#ibcon#read 5, iclass 26, count 2 2006.257.06:16:59.42#ibcon#about to read 6, iclass 26, count 2 2006.257.06:16:59.42#ibcon#read 6, iclass 26, count 2 2006.257.06:16:59.42#ibcon#end of sib2, iclass 26, count 2 2006.257.06:16:59.42#ibcon#*mode == 0, iclass 26, count 2 2006.257.06:16:59.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.06:16:59.42#ibcon#[27=AT05-04\r\n] 2006.257.06:16:59.42#ibcon#*before write, iclass 26, count 2 2006.257.06:16:59.42#ibcon#enter sib2, iclass 26, count 2 2006.257.06:16:59.42#ibcon#flushed, iclass 26, count 2 2006.257.06:16:59.42#ibcon#about to write, iclass 26, count 2 2006.257.06:16:59.42#ibcon#wrote, iclass 26, count 2 2006.257.06:16:59.42#ibcon#about to read 3, iclass 26, count 2 2006.257.06:16:59.45#ibcon#read 3, iclass 26, count 2 2006.257.06:16:59.45#ibcon#about to read 4, iclass 26, count 2 2006.257.06:16:59.45#ibcon#read 4, iclass 26, count 2 2006.257.06:16:59.45#ibcon#about to read 5, iclass 26, count 2 2006.257.06:16:59.45#ibcon#read 5, iclass 26, count 2 2006.257.06:16:59.45#ibcon#about to read 6, iclass 26, count 2 2006.257.06:16:59.45#ibcon#read 6, iclass 26, count 2 2006.257.06:16:59.45#ibcon#end of sib2, iclass 26, count 2 2006.257.06:16:59.45#ibcon#*after write, iclass 26, count 2 2006.257.06:16:59.45#ibcon#*before return 0, iclass 26, count 2 2006.257.06:16:59.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:59.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:16:59.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.06:16:59.45#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:59.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:59.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:59.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:59.57#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:16:59.57#ibcon#first serial, iclass 26, count 0 2006.257.06:16:59.57#ibcon#enter sib2, iclass 26, count 0 2006.257.06:16:59.57#ibcon#flushed, iclass 26, count 0 2006.257.06:16:59.57#ibcon#about to write, iclass 26, count 0 2006.257.06:16:59.57#ibcon#wrote, iclass 26, count 0 2006.257.06:16:59.57#ibcon#about to read 3, iclass 26, count 0 2006.257.06:16:59.59#ibcon#read 3, iclass 26, count 0 2006.257.06:16:59.59#ibcon#about to read 4, iclass 26, count 0 2006.257.06:16:59.59#ibcon#read 4, iclass 26, count 0 2006.257.06:16:59.59#ibcon#about to read 5, iclass 26, count 0 2006.257.06:16:59.59#ibcon#read 5, iclass 26, count 0 2006.257.06:16:59.59#ibcon#about to read 6, iclass 26, count 0 2006.257.06:16:59.59#ibcon#read 6, iclass 26, count 0 2006.257.06:16:59.59#ibcon#end of sib2, iclass 26, count 0 2006.257.06:16:59.59#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:16:59.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:16:59.59#ibcon#[27=USB\r\n] 2006.257.06:16:59.59#ibcon#*before write, iclass 26, count 0 2006.257.06:16:59.59#ibcon#enter sib2, iclass 26, count 0 2006.257.06:16:59.59#ibcon#flushed, iclass 26, count 0 2006.257.06:16:59.59#ibcon#about to write, iclass 26, count 0 2006.257.06:16:59.59#ibcon#wrote, iclass 26, count 0 2006.257.06:16:59.59#ibcon#about to read 3, iclass 26, count 0 2006.257.06:16:59.62#ibcon#read 3, iclass 26, count 0 2006.257.06:16:59.62#ibcon#about to read 4, iclass 26, count 0 2006.257.06:16:59.62#ibcon#read 4, iclass 26, count 0 2006.257.06:16:59.62#ibcon#about to read 5, iclass 26, count 0 2006.257.06:16:59.62#ibcon#read 5, iclass 26, count 0 2006.257.06:16:59.62#ibcon#about to read 6, iclass 26, count 0 2006.257.06:16:59.62#ibcon#read 6, iclass 26, count 0 2006.257.06:16:59.62#ibcon#end of sib2, iclass 26, count 0 2006.257.06:16:59.62#ibcon#*after write, iclass 26, count 0 2006.257.06:16:59.62#ibcon#*before return 0, iclass 26, count 0 2006.257.06:16:59.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:59.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:16:59.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:16:59.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:16:59.62$vck44/vblo=6,719.99 2006.257.06:16:59.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.06:16:59.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.06:16:59.62#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:59.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:59.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:59.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:59.62#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:16:59.62#ibcon#first serial, iclass 28, count 0 2006.257.06:16:59.62#ibcon#enter sib2, iclass 28, count 0 2006.257.06:16:59.62#ibcon#flushed, iclass 28, count 0 2006.257.06:16:59.62#ibcon#about to write, iclass 28, count 0 2006.257.06:16:59.62#ibcon#wrote, iclass 28, count 0 2006.257.06:16:59.62#ibcon#about to read 3, iclass 28, count 0 2006.257.06:16:59.64#ibcon#read 3, iclass 28, count 0 2006.257.06:16:59.64#ibcon#about to read 4, iclass 28, count 0 2006.257.06:16:59.64#ibcon#read 4, iclass 28, count 0 2006.257.06:16:59.64#ibcon#about to read 5, iclass 28, count 0 2006.257.06:16:59.64#ibcon#read 5, iclass 28, count 0 2006.257.06:16:59.64#ibcon#about to read 6, iclass 28, count 0 2006.257.06:16:59.64#ibcon#read 6, iclass 28, count 0 2006.257.06:16:59.64#ibcon#end of sib2, iclass 28, count 0 2006.257.06:16:59.64#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:16:59.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:16:59.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:16:59.64#ibcon#*before write, iclass 28, count 0 2006.257.06:16:59.64#ibcon#enter sib2, iclass 28, count 0 2006.257.06:16:59.64#ibcon#flushed, iclass 28, count 0 2006.257.06:16:59.64#ibcon#about to write, iclass 28, count 0 2006.257.06:16:59.64#ibcon#wrote, iclass 28, count 0 2006.257.06:16:59.64#ibcon#about to read 3, iclass 28, count 0 2006.257.06:16:59.68#ibcon#read 3, iclass 28, count 0 2006.257.06:16:59.68#ibcon#about to read 4, iclass 28, count 0 2006.257.06:16:59.68#ibcon#read 4, iclass 28, count 0 2006.257.06:16:59.68#ibcon#about to read 5, iclass 28, count 0 2006.257.06:16:59.68#ibcon#read 5, iclass 28, count 0 2006.257.06:16:59.68#ibcon#about to read 6, iclass 28, count 0 2006.257.06:16:59.68#ibcon#read 6, iclass 28, count 0 2006.257.06:16:59.68#ibcon#end of sib2, iclass 28, count 0 2006.257.06:16:59.68#ibcon#*after write, iclass 28, count 0 2006.257.06:16:59.68#ibcon#*before return 0, iclass 28, count 0 2006.257.06:16:59.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:59.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:16:59.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:16:59.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:16:59.68$vck44/vb=6,4 2006.257.06:16:59.68#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.06:16:59.68#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.06:16:59.68#ibcon#ireg 11 cls_cnt 2 2006.257.06:16:59.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:59.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:59.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:59.74#ibcon#enter wrdev, iclass 30, count 2 2006.257.06:16:59.74#ibcon#first serial, iclass 30, count 2 2006.257.06:16:59.74#ibcon#enter sib2, iclass 30, count 2 2006.257.06:16:59.74#ibcon#flushed, iclass 30, count 2 2006.257.06:16:59.74#ibcon#about to write, iclass 30, count 2 2006.257.06:16:59.74#ibcon#wrote, iclass 30, count 2 2006.257.06:16:59.74#ibcon#about to read 3, iclass 30, count 2 2006.257.06:16:59.76#ibcon#read 3, iclass 30, count 2 2006.257.06:16:59.76#ibcon#about to read 4, iclass 30, count 2 2006.257.06:16:59.76#ibcon#read 4, iclass 30, count 2 2006.257.06:16:59.76#ibcon#about to read 5, iclass 30, count 2 2006.257.06:16:59.76#ibcon#read 5, iclass 30, count 2 2006.257.06:16:59.76#ibcon#about to read 6, iclass 30, count 2 2006.257.06:16:59.76#ibcon#read 6, iclass 30, count 2 2006.257.06:16:59.76#ibcon#end of sib2, iclass 30, count 2 2006.257.06:16:59.76#ibcon#*mode == 0, iclass 30, count 2 2006.257.06:16:59.76#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.06:16:59.76#ibcon#[27=AT06-04\r\n] 2006.257.06:16:59.76#ibcon#*before write, iclass 30, count 2 2006.257.06:16:59.76#ibcon#enter sib2, iclass 30, count 2 2006.257.06:16:59.76#ibcon#flushed, iclass 30, count 2 2006.257.06:16:59.76#ibcon#about to write, iclass 30, count 2 2006.257.06:16:59.76#ibcon#wrote, iclass 30, count 2 2006.257.06:16:59.76#ibcon#about to read 3, iclass 30, count 2 2006.257.06:16:59.79#ibcon#read 3, iclass 30, count 2 2006.257.06:16:59.79#ibcon#about to read 4, iclass 30, count 2 2006.257.06:16:59.79#ibcon#read 4, iclass 30, count 2 2006.257.06:16:59.79#ibcon#about to read 5, iclass 30, count 2 2006.257.06:16:59.79#ibcon#read 5, iclass 30, count 2 2006.257.06:16:59.79#ibcon#about to read 6, iclass 30, count 2 2006.257.06:16:59.79#ibcon#read 6, iclass 30, count 2 2006.257.06:16:59.79#ibcon#end of sib2, iclass 30, count 2 2006.257.06:16:59.79#ibcon#*after write, iclass 30, count 2 2006.257.06:16:59.79#ibcon#*before return 0, iclass 30, count 2 2006.257.06:16:59.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:59.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:16:59.79#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.06:16:59.79#ibcon#ireg 7 cls_cnt 0 2006.257.06:16:59.79#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:59.91#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:59.91#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:59.91#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:16:59.91#ibcon#first serial, iclass 30, count 0 2006.257.06:16:59.91#ibcon#enter sib2, iclass 30, count 0 2006.257.06:16:59.91#ibcon#flushed, iclass 30, count 0 2006.257.06:16:59.91#ibcon#about to write, iclass 30, count 0 2006.257.06:16:59.91#ibcon#wrote, iclass 30, count 0 2006.257.06:16:59.91#ibcon#about to read 3, iclass 30, count 0 2006.257.06:16:59.93#ibcon#read 3, iclass 30, count 0 2006.257.06:16:59.93#ibcon#about to read 4, iclass 30, count 0 2006.257.06:16:59.93#ibcon#read 4, iclass 30, count 0 2006.257.06:16:59.93#ibcon#about to read 5, iclass 30, count 0 2006.257.06:16:59.93#ibcon#read 5, iclass 30, count 0 2006.257.06:16:59.93#ibcon#about to read 6, iclass 30, count 0 2006.257.06:16:59.93#ibcon#read 6, iclass 30, count 0 2006.257.06:16:59.93#ibcon#end of sib2, iclass 30, count 0 2006.257.06:16:59.93#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:16:59.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:16:59.93#ibcon#[27=USB\r\n] 2006.257.06:16:59.93#ibcon#*before write, iclass 30, count 0 2006.257.06:16:59.93#ibcon#enter sib2, iclass 30, count 0 2006.257.06:16:59.93#ibcon#flushed, iclass 30, count 0 2006.257.06:16:59.93#ibcon#about to write, iclass 30, count 0 2006.257.06:16:59.93#ibcon#wrote, iclass 30, count 0 2006.257.06:16:59.93#ibcon#about to read 3, iclass 30, count 0 2006.257.06:16:59.96#ibcon#read 3, iclass 30, count 0 2006.257.06:16:59.96#ibcon#about to read 4, iclass 30, count 0 2006.257.06:16:59.96#ibcon#read 4, iclass 30, count 0 2006.257.06:16:59.96#ibcon#about to read 5, iclass 30, count 0 2006.257.06:16:59.96#ibcon#read 5, iclass 30, count 0 2006.257.06:16:59.96#ibcon#about to read 6, iclass 30, count 0 2006.257.06:16:59.96#ibcon#read 6, iclass 30, count 0 2006.257.06:16:59.96#ibcon#end of sib2, iclass 30, count 0 2006.257.06:16:59.96#ibcon#*after write, iclass 30, count 0 2006.257.06:16:59.96#ibcon#*before return 0, iclass 30, count 0 2006.257.06:16:59.96#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:59.96#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:16:59.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:16:59.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:16:59.96$vck44/vblo=7,734.99 2006.257.06:16:59.96#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.06:16:59.96#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.06:16:59.96#ibcon#ireg 17 cls_cnt 0 2006.257.06:16:59.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:16:59.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:16:59.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:16:59.96#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:16:59.96#ibcon#first serial, iclass 32, count 0 2006.257.06:16:59.96#ibcon#enter sib2, iclass 32, count 0 2006.257.06:16:59.96#ibcon#flushed, iclass 32, count 0 2006.257.06:16:59.96#ibcon#about to write, iclass 32, count 0 2006.257.06:16:59.96#ibcon#wrote, iclass 32, count 0 2006.257.06:16:59.96#ibcon#about to read 3, iclass 32, count 0 2006.257.06:16:59.98#ibcon#read 3, iclass 32, count 0 2006.257.06:16:59.98#ibcon#about to read 4, iclass 32, count 0 2006.257.06:16:59.98#ibcon#read 4, iclass 32, count 0 2006.257.06:16:59.98#ibcon#about to read 5, iclass 32, count 0 2006.257.06:16:59.98#ibcon#read 5, iclass 32, count 0 2006.257.06:16:59.98#ibcon#about to read 6, iclass 32, count 0 2006.257.06:16:59.98#ibcon#read 6, iclass 32, count 0 2006.257.06:16:59.98#ibcon#end of sib2, iclass 32, count 0 2006.257.06:16:59.98#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:16:59.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:16:59.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:16:59.98#ibcon#*before write, iclass 32, count 0 2006.257.06:16:59.98#ibcon#enter sib2, iclass 32, count 0 2006.257.06:16:59.98#ibcon#flushed, iclass 32, count 0 2006.257.06:16:59.98#ibcon#about to write, iclass 32, count 0 2006.257.06:16:59.98#ibcon#wrote, iclass 32, count 0 2006.257.06:16:59.98#ibcon#about to read 3, iclass 32, count 0 2006.257.06:17:00.02#ibcon#read 3, iclass 32, count 0 2006.257.06:17:00.02#ibcon#about to read 4, iclass 32, count 0 2006.257.06:17:00.02#ibcon#read 4, iclass 32, count 0 2006.257.06:17:00.02#ibcon#about to read 5, iclass 32, count 0 2006.257.06:17:00.02#ibcon#read 5, iclass 32, count 0 2006.257.06:17:00.02#ibcon#about to read 6, iclass 32, count 0 2006.257.06:17:00.02#ibcon#read 6, iclass 32, count 0 2006.257.06:17:00.02#ibcon#end of sib2, iclass 32, count 0 2006.257.06:17:00.02#ibcon#*after write, iclass 32, count 0 2006.257.06:17:00.02#ibcon#*before return 0, iclass 32, count 0 2006.257.06:17:00.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:17:00.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:17:00.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:17:00.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:17:00.02$vck44/vb=7,4 2006.257.06:17:00.02#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.06:17:00.02#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.06:17:00.02#ibcon#ireg 11 cls_cnt 2 2006.257.06:17:00.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:17:00.08#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:17:00.08#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:17:00.08#ibcon#enter wrdev, iclass 34, count 2 2006.257.06:17:00.08#ibcon#first serial, iclass 34, count 2 2006.257.06:17:00.08#ibcon#enter sib2, iclass 34, count 2 2006.257.06:17:00.08#ibcon#flushed, iclass 34, count 2 2006.257.06:17:00.08#ibcon#about to write, iclass 34, count 2 2006.257.06:17:00.08#ibcon#wrote, iclass 34, count 2 2006.257.06:17:00.08#ibcon#about to read 3, iclass 34, count 2 2006.257.06:17:00.10#ibcon#read 3, iclass 34, count 2 2006.257.06:17:00.10#ibcon#about to read 4, iclass 34, count 2 2006.257.06:17:00.10#ibcon#read 4, iclass 34, count 2 2006.257.06:17:00.10#ibcon#about to read 5, iclass 34, count 2 2006.257.06:17:00.10#ibcon#read 5, iclass 34, count 2 2006.257.06:17:00.10#ibcon#about to read 6, iclass 34, count 2 2006.257.06:17:00.10#ibcon#read 6, iclass 34, count 2 2006.257.06:17:00.10#ibcon#end of sib2, iclass 34, count 2 2006.257.06:17:00.10#ibcon#*mode == 0, iclass 34, count 2 2006.257.06:17:00.10#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.06:17:00.10#ibcon#[27=AT07-04\r\n] 2006.257.06:17:00.10#ibcon#*before write, iclass 34, count 2 2006.257.06:17:00.10#ibcon#enter sib2, iclass 34, count 2 2006.257.06:17:00.10#ibcon#flushed, iclass 34, count 2 2006.257.06:17:00.10#ibcon#about to write, iclass 34, count 2 2006.257.06:17:00.10#ibcon#wrote, iclass 34, count 2 2006.257.06:17:00.10#ibcon#about to read 3, iclass 34, count 2 2006.257.06:17:00.13#ibcon#read 3, iclass 34, count 2 2006.257.06:17:00.13#ibcon#about to read 4, iclass 34, count 2 2006.257.06:17:00.13#ibcon#read 4, iclass 34, count 2 2006.257.06:17:00.13#ibcon#about to read 5, iclass 34, count 2 2006.257.06:17:00.13#ibcon#read 5, iclass 34, count 2 2006.257.06:17:00.13#ibcon#about to read 6, iclass 34, count 2 2006.257.06:17:00.13#ibcon#read 6, iclass 34, count 2 2006.257.06:17:00.13#ibcon#end of sib2, iclass 34, count 2 2006.257.06:17:00.13#ibcon#*after write, iclass 34, count 2 2006.257.06:17:00.13#ibcon#*before return 0, iclass 34, count 2 2006.257.06:17:00.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:17:00.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:17:00.13#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.06:17:00.13#ibcon#ireg 7 cls_cnt 0 2006.257.06:17:00.13#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:17:00.25#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:17:00.25#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:17:00.25#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:17:00.25#ibcon#first serial, iclass 34, count 0 2006.257.06:17:00.25#ibcon#enter sib2, iclass 34, count 0 2006.257.06:17:00.25#ibcon#flushed, iclass 34, count 0 2006.257.06:17:00.25#ibcon#about to write, iclass 34, count 0 2006.257.06:17:00.25#ibcon#wrote, iclass 34, count 0 2006.257.06:17:00.25#ibcon#about to read 3, iclass 34, count 0 2006.257.06:17:00.27#ibcon#read 3, iclass 34, count 0 2006.257.06:17:00.27#ibcon#about to read 4, iclass 34, count 0 2006.257.06:17:00.27#ibcon#read 4, iclass 34, count 0 2006.257.06:17:00.27#ibcon#about to read 5, iclass 34, count 0 2006.257.06:17:00.27#ibcon#read 5, iclass 34, count 0 2006.257.06:17:00.27#ibcon#about to read 6, iclass 34, count 0 2006.257.06:17:00.27#ibcon#read 6, iclass 34, count 0 2006.257.06:17:00.27#ibcon#end of sib2, iclass 34, count 0 2006.257.06:17:00.27#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:17:00.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:17:00.27#ibcon#[27=USB\r\n] 2006.257.06:17:00.27#ibcon#*before write, iclass 34, count 0 2006.257.06:17:00.27#ibcon#enter sib2, iclass 34, count 0 2006.257.06:17:00.27#ibcon#flushed, iclass 34, count 0 2006.257.06:17:00.27#ibcon#about to write, iclass 34, count 0 2006.257.06:17:00.27#ibcon#wrote, iclass 34, count 0 2006.257.06:17:00.27#ibcon#about to read 3, iclass 34, count 0 2006.257.06:17:00.30#ibcon#read 3, iclass 34, count 0 2006.257.06:17:00.30#ibcon#about to read 4, iclass 34, count 0 2006.257.06:17:00.30#ibcon#read 4, iclass 34, count 0 2006.257.06:17:00.30#ibcon#about to read 5, iclass 34, count 0 2006.257.06:17:00.30#ibcon#read 5, iclass 34, count 0 2006.257.06:17:00.30#ibcon#about to read 6, iclass 34, count 0 2006.257.06:17:00.30#ibcon#read 6, iclass 34, count 0 2006.257.06:17:00.30#ibcon#end of sib2, iclass 34, count 0 2006.257.06:17:00.30#ibcon#*after write, iclass 34, count 0 2006.257.06:17:00.30#ibcon#*before return 0, iclass 34, count 0 2006.257.06:17:00.30#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:17:00.30#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:17:00.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:17:00.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:17:00.30$vck44/vblo=8,744.99 2006.257.06:17:00.30#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.06:17:00.30#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.06:17:00.30#ibcon#ireg 17 cls_cnt 0 2006.257.06:17:00.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:17:00.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:17:00.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:17:00.30#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:17:00.30#ibcon#first serial, iclass 36, count 0 2006.257.06:17:00.30#ibcon#enter sib2, iclass 36, count 0 2006.257.06:17:00.30#ibcon#flushed, iclass 36, count 0 2006.257.06:17:00.30#ibcon#about to write, iclass 36, count 0 2006.257.06:17:00.30#ibcon#wrote, iclass 36, count 0 2006.257.06:17:00.30#ibcon#about to read 3, iclass 36, count 0 2006.257.06:17:00.32#ibcon#read 3, iclass 36, count 0 2006.257.06:17:00.32#ibcon#about to read 4, iclass 36, count 0 2006.257.06:17:00.32#ibcon#read 4, iclass 36, count 0 2006.257.06:17:00.32#ibcon#about to read 5, iclass 36, count 0 2006.257.06:17:00.32#ibcon#read 5, iclass 36, count 0 2006.257.06:17:00.32#ibcon#about to read 6, iclass 36, count 0 2006.257.06:17:00.32#ibcon#read 6, iclass 36, count 0 2006.257.06:17:00.32#ibcon#end of sib2, iclass 36, count 0 2006.257.06:17:00.32#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:17:00.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:17:00.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:17:00.32#ibcon#*before write, iclass 36, count 0 2006.257.06:17:00.32#ibcon#enter sib2, iclass 36, count 0 2006.257.06:17:00.32#ibcon#flushed, iclass 36, count 0 2006.257.06:17:00.32#ibcon#about to write, iclass 36, count 0 2006.257.06:17:00.32#ibcon#wrote, iclass 36, count 0 2006.257.06:17:00.32#ibcon#about to read 3, iclass 36, count 0 2006.257.06:17:00.36#ibcon#read 3, iclass 36, count 0 2006.257.06:17:00.36#ibcon#about to read 4, iclass 36, count 0 2006.257.06:17:00.36#ibcon#read 4, iclass 36, count 0 2006.257.06:17:00.36#ibcon#about to read 5, iclass 36, count 0 2006.257.06:17:00.36#ibcon#read 5, iclass 36, count 0 2006.257.06:17:00.36#ibcon#about to read 6, iclass 36, count 0 2006.257.06:17:00.36#ibcon#read 6, iclass 36, count 0 2006.257.06:17:00.36#ibcon#end of sib2, iclass 36, count 0 2006.257.06:17:00.36#ibcon#*after write, iclass 36, count 0 2006.257.06:17:00.36#ibcon#*before return 0, iclass 36, count 0 2006.257.06:17:00.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:17:00.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:17:00.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:17:00.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:17:00.36$vck44/vb=8,4 2006.257.06:17:00.36#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.06:17:00.36#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.06:17:00.36#ibcon#ireg 11 cls_cnt 2 2006.257.06:17:00.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:17:00.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:17:00.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:17:00.42#ibcon#enter wrdev, iclass 38, count 2 2006.257.06:17:00.42#ibcon#first serial, iclass 38, count 2 2006.257.06:17:00.42#ibcon#enter sib2, iclass 38, count 2 2006.257.06:17:00.42#ibcon#flushed, iclass 38, count 2 2006.257.06:17:00.42#ibcon#about to write, iclass 38, count 2 2006.257.06:17:00.42#ibcon#wrote, iclass 38, count 2 2006.257.06:17:00.42#ibcon#about to read 3, iclass 38, count 2 2006.257.06:17:00.44#ibcon#read 3, iclass 38, count 2 2006.257.06:17:00.44#ibcon#about to read 4, iclass 38, count 2 2006.257.06:17:00.44#ibcon#read 4, iclass 38, count 2 2006.257.06:17:00.44#ibcon#about to read 5, iclass 38, count 2 2006.257.06:17:00.44#ibcon#read 5, iclass 38, count 2 2006.257.06:17:00.44#ibcon#about to read 6, iclass 38, count 2 2006.257.06:17:00.44#ibcon#read 6, iclass 38, count 2 2006.257.06:17:00.44#ibcon#end of sib2, iclass 38, count 2 2006.257.06:17:00.44#ibcon#*mode == 0, iclass 38, count 2 2006.257.06:17:00.44#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.06:17:00.44#ibcon#[27=AT08-04\r\n] 2006.257.06:17:00.44#ibcon#*before write, iclass 38, count 2 2006.257.06:17:00.44#ibcon#enter sib2, iclass 38, count 2 2006.257.06:17:00.44#ibcon#flushed, iclass 38, count 2 2006.257.06:17:00.44#ibcon#about to write, iclass 38, count 2 2006.257.06:17:00.44#ibcon#wrote, iclass 38, count 2 2006.257.06:17:00.44#ibcon#about to read 3, iclass 38, count 2 2006.257.06:17:00.47#ibcon#read 3, iclass 38, count 2 2006.257.06:17:00.47#ibcon#about to read 4, iclass 38, count 2 2006.257.06:17:00.47#ibcon#read 4, iclass 38, count 2 2006.257.06:17:00.47#ibcon#about to read 5, iclass 38, count 2 2006.257.06:17:00.47#ibcon#read 5, iclass 38, count 2 2006.257.06:17:00.47#ibcon#about to read 6, iclass 38, count 2 2006.257.06:17:00.47#ibcon#read 6, iclass 38, count 2 2006.257.06:17:00.47#ibcon#end of sib2, iclass 38, count 2 2006.257.06:17:00.47#ibcon#*after write, iclass 38, count 2 2006.257.06:17:00.47#ibcon#*before return 0, iclass 38, count 2 2006.257.06:17:00.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:17:00.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:17:00.47#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.06:17:00.47#ibcon#ireg 7 cls_cnt 0 2006.257.06:17:00.47#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:17:00.59#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:17:00.59#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:17:00.59#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:17:00.59#ibcon#first serial, iclass 38, count 0 2006.257.06:17:00.59#ibcon#enter sib2, iclass 38, count 0 2006.257.06:17:00.59#ibcon#flushed, iclass 38, count 0 2006.257.06:17:00.59#ibcon#about to write, iclass 38, count 0 2006.257.06:17:00.59#ibcon#wrote, iclass 38, count 0 2006.257.06:17:00.59#ibcon#about to read 3, iclass 38, count 0 2006.257.06:17:00.61#ibcon#read 3, iclass 38, count 0 2006.257.06:17:00.61#ibcon#about to read 4, iclass 38, count 0 2006.257.06:17:00.61#ibcon#read 4, iclass 38, count 0 2006.257.06:17:00.61#ibcon#about to read 5, iclass 38, count 0 2006.257.06:17:00.61#ibcon#read 5, iclass 38, count 0 2006.257.06:17:00.61#ibcon#about to read 6, iclass 38, count 0 2006.257.06:17:00.61#ibcon#read 6, iclass 38, count 0 2006.257.06:17:00.61#ibcon#end of sib2, iclass 38, count 0 2006.257.06:17:00.61#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:17:00.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:17:00.61#ibcon#[27=USB\r\n] 2006.257.06:17:00.61#ibcon#*before write, iclass 38, count 0 2006.257.06:17:00.61#ibcon#enter sib2, iclass 38, count 0 2006.257.06:17:00.61#ibcon#flushed, iclass 38, count 0 2006.257.06:17:00.61#ibcon#about to write, iclass 38, count 0 2006.257.06:17:00.61#ibcon#wrote, iclass 38, count 0 2006.257.06:17:00.61#ibcon#about to read 3, iclass 38, count 0 2006.257.06:17:00.64#ibcon#read 3, iclass 38, count 0 2006.257.06:17:00.64#ibcon#about to read 4, iclass 38, count 0 2006.257.06:17:00.64#ibcon#read 4, iclass 38, count 0 2006.257.06:17:00.64#ibcon#about to read 5, iclass 38, count 0 2006.257.06:17:00.64#ibcon#read 5, iclass 38, count 0 2006.257.06:17:00.64#ibcon#about to read 6, iclass 38, count 0 2006.257.06:17:00.64#ibcon#read 6, iclass 38, count 0 2006.257.06:17:00.64#ibcon#end of sib2, iclass 38, count 0 2006.257.06:17:00.64#ibcon#*after write, iclass 38, count 0 2006.257.06:17:00.64#ibcon#*before return 0, iclass 38, count 0 2006.257.06:17:00.64#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:17:00.64#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:17:00.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:17:00.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:17:00.64$vck44/vabw=wide 2006.257.06:17:00.64#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.06:17:00.64#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.06:17:00.64#ibcon#ireg 8 cls_cnt 0 2006.257.06:17:00.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:17:00.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:17:00.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:17:00.64#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:17:00.64#ibcon#first serial, iclass 40, count 0 2006.257.06:17:00.64#ibcon#enter sib2, iclass 40, count 0 2006.257.06:17:00.64#ibcon#flushed, iclass 40, count 0 2006.257.06:17:00.64#ibcon#about to write, iclass 40, count 0 2006.257.06:17:00.64#ibcon#wrote, iclass 40, count 0 2006.257.06:17:00.64#ibcon#about to read 3, iclass 40, count 0 2006.257.06:17:00.66#ibcon#read 3, iclass 40, count 0 2006.257.06:17:00.66#ibcon#about to read 4, iclass 40, count 0 2006.257.06:17:00.66#ibcon#read 4, iclass 40, count 0 2006.257.06:17:00.66#ibcon#about to read 5, iclass 40, count 0 2006.257.06:17:00.66#ibcon#read 5, iclass 40, count 0 2006.257.06:17:00.66#ibcon#about to read 6, iclass 40, count 0 2006.257.06:17:00.66#ibcon#read 6, iclass 40, count 0 2006.257.06:17:00.66#ibcon#end of sib2, iclass 40, count 0 2006.257.06:17:00.66#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:17:00.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:17:00.66#ibcon#[25=BW32\r\n] 2006.257.06:17:00.66#ibcon#*before write, iclass 40, count 0 2006.257.06:17:00.66#ibcon#enter sib2, iclass 40, count 0 2006.257.06:17:00.66#ibcon#flushed, iclass 40, count 0 2006.257.06:17:00.66#ibcon#about to write, iclass 40, count 0 2006.257.06:17:00.66#ibcon#wrote, iclass 40, count 0 2006.257.06:17:00.66#ibcon#about to read 3, iclass 40, count 0 2006.257.06:17:00.69#ibcon#read 3, iclass 40, count 0 2006.257.06:17:00.69#ibcon#about to read 4, iclass 40, count 0 2006.257.06:17:00.69#ibcon#read 4, iclass 40, count 0 2006.257.06:17:00.69#ibcon#about to read 5, iclass 40, count 0 2006.257.06:17:00.69#ibcon#read 5, iclass 40, count 0 2006.257.06:17:00.69#ibcon#about to read 6, iclass 40, count 0 2006.257.06:17:00.69#ibcon#read 6, iclass 40, count 0 2006.257.06:17:00.69#ibcon#end of sib2, iclass 40, count 0 2006.257.06:17:00.69#ibcon#*after write, iclass 40, count 0 2006.257.06:17:00.69#ibcon#*before return 0, iclass 40, count 0 2006.257.06:17:00.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:17:00.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:17:00.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:17:00.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:17:00.69$vck44/vbbw=wide 2006.257.06:17:00.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.06:17:00.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.06:17:00.69#ibcon#ireg 8 cls_cnt 0 2006.257.06:17:00.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:17:00.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:17:00.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:17:00.76#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:17:00.76#ibcon#first serial, iclass 4, count 0 2006.257.06:17:00.76#ibcon#enter sib2, iclass 4, count 0 2006.257.06:17:00.76#ibcon#flushed, iclass 4, count 0 2006.257.06:17:00.76#ibcon#about to write, iclass 4, count 0 2006.257.06:17:00.76#ibcon#wrote, iclass 4, count 0 2006.257.06:17:00.76#ibcon#about to read 3, iclass 4, count 0 2006.257.06:17:00.78#ibcon#read 3, iclass 4, count 0 2006.257.06:17:00.78#ibcon#about to read 4, iclass 4, count 0 2006.257.06:17:00.78#ibcon#read 4, iclass 4, count 0 2006.257.06:17:00.78#ibcon#about to read 5, iclass 4, count 0 2006.257.06:17:00.78#ibcon#read 5, iclass 4, count 0 2006.257.06:17:00.78#ibcon#about to read 6, iclass 4, count 0 2006.257.06:17:00.78#ibcon#read 6, iclass 4, count 0 2006.257.06:17:00.78#ibcon#end of sib2, iclass 4, count 0 2006.257.06:17:00.78#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:17:00.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:17:00.78#ibcon#[27=BW32\r\n] 2006.257.06:17:00.78#ibcon#*before write, iclass 4, count 0 2006.257.06:17:00.78#ibcon#enter sib2, iclass 4, count 0 2006.257.06:17:00.78#ibcon#flushed, iclass 4, count 0 2006.257.06:17:00.78#ibcon#about to write, iclass 4, count 0 2006.257.06:17:00.78#ibcon#wrote, iclass 4, count 0 2006.257.06:17:00.78#ibcon#about to read 3, iclass 4, count 0 2006.257.06:17:00.81#ibcon#read 3, iclass 4, count 0 2006.257.06:17:00.81#ibcon#about to read 4, iclass 4, count 0 2006.257.06:17:00.81#ibcon#read 4, iclass 4, count 0 2006.257.06:17:00.81#ibcon#about to read 5, iclass 4, count 0 2006.257.06:17:00.81#ibcon#read 5, iclass 4, count 0 2006.257.06:17:00.81#ibcon#about to read 6, iclass 4, count 0 2006.257.06:17:00.81#ibcon#read 6, iclass 4, count 0 2006.257.06:17:00.81#ibcon#end of sib2, iclass 4, count 0 2006.257.06:17:00.81#ibcon#*after write, iclass 4, count 0 2006.257.06:17:00.81#ibcon#*before return 0, iclass 4, count 0 2006.257.06:17:00.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:17:00.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:17:00.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:17:00.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:17:00.81$setupk4/ifdk4 2006.257.06:17:00.81$ifdk4/lo= 2006.257.06:17:00.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:17:00.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:17:00.81$ifdk4/patch= 2006.257.06:17:00.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:17:00.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:17:00.81$setupk4/!*+20s 2006.257.06:17:09.24#abcon#<5=/15 1.2 3.4 20.39 891012.2\r\n> 2006.257.06:17:09.26#abcon#{5=INTERFACE CLEAR} 2006.257.06:17:09.32#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:17:11.13#trakl#Source acquired 2006.257.06:17:11.13#flagr#flagr/antenna,acquired 2006.257.06:17:15.32$setupk4/"tpicd 2006.257.06:17:15.32$setupk4/echo=off 2006.257.06:17:15.32$setupk4/xlog=off 2006.257.06:17:15.32:!2006.257.06:17:42 2006.257.06:17:42.00:preob 2006.257.06:17:42.13/onsource/TRACKING 2006.257.06:17:42.13:!2006.257.06:17:52 2006.257.06:17:52.00:"tape 2006.257.06:17:52.00:"st=record 2006.257.06:17:52.00:data_valid=on 2006.257.06:17:52.00:midob 2006.257.06:17:53.13/onsource/TRACKING 2006.257.06:17:53.13/wx/20.40,1012.2,88 2006.257.06:17:53.28/cable/+6.4792E-03 2006.257.06:17:54.37/va/01,08,usb,yes,37,40 2006.257.06:17:54.37/va/02,07,usb,yes,40,41 2006.257.06:17:54.37/va/03,08,usb,yes,36,38 2006.257.06:17:54.37/va/04,07,usb,yes,42,44 2006.257.06:17:54.37/va/05,04,usb,yes,37,38 2006.257.06:17:54.37/va/06,04,usb,yes,41,41 2006.257.06:17:54.37/va/07,04,usb,yes,43,43 2006.257.06:17:54.37/va/08,04,usb,yes,36,43 2006.257.06:17:54.60/valo/01,524.99,yes,locked 2006.257.06:17:54.60/valo/02,534.99,yes,locked 2006.257.06:17:54.60/valo/03,564.99,yes,locked 2006.257.06:17:54.60/valo/04,624.99,yes,locked 2006.257.06:17:54.60/valo/05,734.99,yes,locked 2006.257.06:17:54.60/valo/06,814.99,yes,locked 2006.257.06:17:54.60/valo/07,864.99,yes,locked 2006.257.06:17:54.60/valo/08,884.99,yes,locked 2006.257.06:17:55.69/vb/01,04,usb,yes,47,98 2006.257.06:17:55.69/vb/02,05,usb,yes,31,96 2006.257.06:17:55.69/vb/03,04,usb,yes,31,78 2006.257.06:17:55.69/vb/04,05,usb,yes,30,29 2006.257.06:17:55.69/vb/05,04,usb,yes,30,32 2006.257.06:17:55.69/vb/06,04,usb,yes,35,30 2006.257.06:17:55.69/vb/07,04,usb,yes,32,32 2006.257.06:17:55.69/vb/08,04,usb,yes,29,33 2006.257.06:17:55.93/vblo/01,629.99,yes,locked 2006.257.06:17:55.93/vblo/02,634.99,yes,locked 2006.257.06:17:55.93/vblo/03,649.99,yes,locked 2006.257.06:17:55.93/vblo/04,679.99,yes,locked 2006.257.06:17:55.93/vblo/05,709.99,yes,locked 2006.257.06:17:55.93/vblo/06,719.99,yes,locked 2006.257.06:17:55.93/vblo/07,734.99,yes,locked 2006.257.06:17:55.93/vblo/08,744.99,yes,locked 2006.257.06:17:56.08/vabw/8 2006.257.06:17:56.23/vbbw/8 2006.257.06:17:56.32/xfe/off,on,16.5 2006.257.06:17:56.70/ifatt/23,28,28,28 2006.257.06:17:57.07/fmout-gps/S +4.54E-07 2006.257.06:17:57.11:!2006.257.06:20:42 2006.257.06:20:42.00:data_valid=off 2006.257.06:20:42.00:"et 2006.257.06:20:42.00:!+3s 2006.257.06:20:45.03:"tape 2006.257.06:20:45.03:postob 2006.257.06:20:45.24/cable/+6.4777E-03 2006.257.06:20:45.24/wx/20.42,1012.2,89 2006.257.06:20:45.30/fmout-gps/S +4.54E-07 2006.257.06:20:45.30:scan_name=257-0623,jd0609,280 2006.257.06:20:45.30:source=1622-253,162546.89,-252738.3,2000.0,cw 2006.257.06:20:46.14#flagr#flagr/antenna,new-source 2006.257.06:20:46.14:checkk5 2006.257.06:20:46.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:20:46.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:20:47.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:20:47.72/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:20:48.11/chk_obsdata//k5ts1/T2570617??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.06:20:48.51/chk_obsdata//k5ts2/T2570617??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.06:20:48.93/chk_obsdata//k5ts3/T2570617??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.06:20:49.34/chk_obsdata//k5ts4/T2570617??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.06:20:50.08/k5log//k5ts1_log_newline 2006.257.06:20:50.80/k5log//k5ts2_log_newline 2006.257.06:20:51.55/k5log//k5ts3_log_newline 2006.257.06:20:52.26/k5log//k5ts4_log_newline 2006.257.06:20:52.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:20:52.29:setupk4=1 2006.257.06:20:52.29$setupk4/echo=on 2006.257.06:20:52.29$setupk4/pcalon 2006.257.06:20:52.29$pcalon/"no phase cal control is implemented here 2006.257.06:20:52.29$setupk4/"tpicd=stop 2006.257.06:20:52.29$setupk4/"rec=synch_on 2006.257.06:20:52.29$setupk4/"rec_mode=128 2006.257.06:20:52.29$setupk4/!* 2006.257.06:20:52.29$setupk4/recpk4 2006.257.06:20:52.29$recpk4/recpatch= 2006.257.06:20:52.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:20:52.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:20:52.29$setupk4/vck44 2006.257.06:20:52.29$vck44/valo=1,524.99 2006.257.06:20:52.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.06:20:52.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.06:20:52.29#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:52.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:52.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:52.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:52.29#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:20:52.29#ibcon#first serial, iclass 27, count 0 2006.257.06:20:52.29#ibcon#enter sib2, iclass 27, count 0 2006.257.06:20:52.29#ibcon#flushed, iclass 27, count 0 2006.257.06:20:52.29#ibcon#about to write, iclass 27, count 0 2006.257.06:20:52.29#ibcon#wrote, iclass 27, count 0 2006.257.06:20:52.29#ibcon#about to read 3, iclass 27, count 0 2006.257.06:20:52.31#ibcon#read 3, iclass 27, count 0 2006.257.06:20:52.31#ibcon#about to read 4, iclass 27, count 0 2006.257.06:20:52.31#ibcon#read 4, iclass 27, count 0 2006.257.06:20:52.31#ibcon#about to read 5, iclass 27, count 0 2006.257.06:20:52.31#ibcon#read 5, iclass 27, count 0 2006.257.06:20:52.31#ibcon#about to read 6, iclass 27, count 0 2006.257.06:20:52.31#ibcon#read 6, iclass 27, count 0 2006.257.06:20:52.31#ibcon#end of sib2, iclass 27, count 0 2006.257.06:20:52.31#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:20:52.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:20:52.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:20:52.31#ibcon#*before write, iclass 27, count 0 2006.257.06:20:52.31#ibcon#enter sib2, iclass 27, count 0 2006.257.06:20:52.31#ibcon#flushed, iclass 27, count 0 2006.257.06:20:52.31#ibcon#about to write, iclass 27, count 0 2006.257.06:20:52.31#ibcon#wrote, iclass 27, count 0 2006.257.06:20:52.31#ibcon#about to read 3, iclass 27, count 0 2006.257.06:20:52.36#ibcon#read 3, iclass 27, count 0 2006.257.06:20:52.36#ibcon#about to read 4, iclass 27, count 0 2006.257.06:20:52.36#ibcon#read 4, iclass 27, count 0 2006.257.06:20:52.36#ibcon#about to read 5, iclass 27, count 0 2006.257.06:20:52.36#ibcon#read 5, iclass 27, count 0 2006.257.06:20:52.36#ibcon#about to read 6, iclass 27, count 0 2006.257.06:20:52.36#ibcon#read 6, iclass 27, count 0 2006.257.06:20:52.36#ibcon#end of sib2, iclass 27, count 0 2006.257.06:20:52.36#ibcon#*after write, iclass 27, count 0 2006.257.06:20:52.36#ibcon#*before return 0, iclass 27, count 0 2006.257.06:20:52.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:52.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:52.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:20:52.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:20:52.36$vck44/va=1,8 2006.257.06:20:52.36#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.06:20:52.36#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.06:20:52.36#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:52.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:52.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:52.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:52.36#ibcon#enter wrdev, iclass 29, count 2 2006.257.06:20:52.36#ibcon#first serial, iclass 29, count 2 2006.257.06:20:52.36#ibcon#enter sib2, iclass 29, count 2 2006.257.06:20:52.36#ibcon#flushed, iclass 29, count 2 2006.257.06:20:52.36#ibcon#about to write, iclass 29, count 2 2006.257.06:20:52.36#ibcon#wrote, iclass 29, count 2 2006.257.06:20:52.36#ibcon#about to read 3, iclass 29, count 2 2006.257.06:20:52.38#ibcon#read 3, iclass 29, count 2 2006.257.06:20:52.38#ibcon#about to read 4, iclass 29, count 2 2006.257.06:20:52.38#ibcon#read 4, iclass 29, count 2 2006.257.06:20:52.38#ibcon#about to read 5, iclass 29, count 2 2006.257.06:20:52.38#ibcon#read 5, iclass 29, count 2 2006.257.06:20:52.38#ibcon#about to read 6, iclass 29, count 2 2006.257.06:20:52.38#ibcon#read 6, iclass 29, count 2 2006.257.06:20:52.38#ibcon#end of sib2, iclass 29, count 2 2006.257.06:20:52.38#ibcon#*mode == 0, iclass 29, count 2 2006.257.06:20:52.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.06:20:52.38#ibcon#[25=AT01-08\r\n] 2006.257.06:20:52.38#ibcon#*before write, iclass 29, count 2 2006.257.06:20:52.38#ibcon#enter sib2, iclass 29, count 2 2006.257.06:20:52.38#ibcon#flushed, iclass 29, count 2 2006.257.06:20:52.38#ibcon#about to write, iclass 29, count 2 2006.257.06:20:52.38#ibcon#wrote, iclass 29, count 2 2006.257.06:20:52.38#ibcon#about to read 3, iclass 29, count 2 2006.257.06:20:52.41#ibcon#read 3, iclass 29, count 2 2006.257.06:20:52.41#ibcon#about to read 4, iclass 29, count 2 2006.257.06:20:52.41#ibcon#read 4, iclass 29, count 2 2006.257.06:20:52.41#ibcon#about to read 5, iclass 29, count 2 2006.257.06:20:52.41#ibcon#read 5, iclass 29, count 2 2006.257.06:20:52.41#ibcon#about to read 6, iclass 29, count 2 2006.257.06:20:52.41#ibcon#read 6, iclass 29, count 2 2006.257.06:20:52.41#ibcon#end of sib2, iclass 29, count 2 2006.257.06:20:52.41#ibcon#*after write, iclass 29, count 2 2006.257.06:20:52.41#ibcon#*before return 0, iclass 29, count 2 2006.257.06:20:52.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:52.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:52.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.06:20:52.41#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:52.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:52.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:52.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:52.53#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:20:52.53#ibcon#first serial, iclass 29, count 0 2006.257.06:20:52.53#ibcon#enter sib2, iclass 29, count 0 2006.257.06:20:52.53#ibcon#flushed, iclass 29, count 0 2006.257.06:20:52.53#ibcon#about to write, iclass 29, count 0 2006.257.06:20:52.53#ibcon#wrote, iclass 29, count 0 2006.257.06:20:52.53#ibcon#about to read 3, iclass 29, count 0 2006.257.06:20:52.55#ibcon#read 3, iclass 29, count 0 2006.257.06:20:52.55#ibcon#about to read 4, iclass 29, count 0 2006.257.06:20:52.55#ibcon#read 4, iclass 29, count 0 2006.257.06:20:52.55#ibcon#about to read 5, iclass 29, count 0 2006.257.06:20:52.55#ibcon#read 5, iclass 29, count 0 2006.257.06:20:52.55#ibcon#about to read 6, iclass 29, count 0 2006.257.06:20:52.55#ibcon#read 6, iclass 29, count 0 2006.257.06:20:52.55#ibcon#end of sib2, iclass 29, count 0 2006.257.06:20:52.55#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:20:52.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:20:52.55#ibcon#[25=USB\r\n] 2006.257.06:20:52.55#ibcon#*before write, iclass 29, count 0 2006.257.06:20:52.55#ibcon#enter sib2, iclass 29, count 0 2006.257.06:20:52.55#ibcon#flushed, iclass 29, count 0 2006.257.06:20:52.55#ibcon#about to write, iclass 29, count 0 2006.257.06:20:52.55#ibcon#wrote, iclass 29, count 0 2006.257.06:20:52.55#ibcon#about to read 3, iclass 29, count 0 2006.257.06:20:52.58#ibcon#read 3, iclass 29, count 0 2006.257.06:20:52.58#ibcon#about to read 4, iclass 29, count 0 2006.257.06:20:52.58#ibcon#read 4, iclass 29, count 0 2006.257.06:20:52.58#ibcon#about to read 5, iclass 29, count 0 2006.257.06:20:52.58#ibcon#read 5, iclass 29, count 0 2006.257.06:20:52.58#ibcon#about to read 6, iclass 29, count 0 2006.257.06:20:52.58#ibcon#read 6, iclass 29, count 0 2006.257.06:20:52.58#ibcon#end of sib2, iclass 29, count 0 2006.257.06:20:52.58#ibcon#*after write, iclass 29, count 0 2006.257.06:20:52.58#ibcon#*before return 0, iclass 29, count 0 2006.257.06:20:52.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:52.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:52.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:20:52.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:20:52.58$vck44/valo=2,534.99 2006.257.06:20:52.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.06:20:52.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.06:20:52.58#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:52.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:52.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:52.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:52.58#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:20:52.58#ibcon#first serial, iclass 31, count 0 2006.257.06:20:52.58#ibcon#enter sib2, iclass 31, count 0 2006.257.06:20:52.58#ibcon#flushed, iclass 31, count 0 2006.257.06:20:52.58#ibcon#about to write, iclass 31, count 0 2006.257.06:20:52.58#ibcon#wrote, iclass 31, count 0 2006.257.06:20:52.58#ibcon#about to read 3, iclass 31, count 0 2006.257.06:20:52.60#ibcon#read 3, iclass 31, count 0 2006.257.06:20:52.60#ibcon#about to read 4, iclass 31, count 0 2006.257.06:20:52.60#ibcon#read 4, iclass 31, count 0 2006.257.06:20:52.60#ibcon#about to read 5, iclass 31, count 0 2006.257.06:20:52.60#ibcon#read 5, iclass 31, count 0 2006.257.06:20:52.60#ibcon#about to read 6, iclass 31, count 0 2006.257.06:20:52.60#ibcon#read 6, iclass 31, count 0 2006.257.06:20:52.60#ibcon#end of sib2, iclass 31, count 0 2006.257.06:20:52.60#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:20:52.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:20:52.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:20:52.60#ibcon#*before write, iclass 31, count 0 2006.257.06:20:52.60#ibcon#enter sib2, iclass 31, count 0 2006.257.06:20:52.60#ibcon#flushed, iclass 31, count 0 2006.257.06:20:52.60#ibcon#about to write, iclass 31, count 0 2006.257.06:20:52.60#ibcon#wrote, iclass 31, count 0 2006.257.06:20:52.60#ibcon#about to read 3, iclass 31, count 0 2006.257.06:20:52.64#ibcon#read 3, iclass 31, count 0 2006.257.06:20:52.64#ibcon#about to read 4, iclass 31, count 0 2006.257.06:20:52.64#ibcon#read 4, iclass 31, count 0 2006.257.06:20:52.64#ibcon#about to read 5, iclass 31, count 0 2006.257.06:20:52.64#ibcon#read 5, iclass 31, count 0 2006.257.06:20:52.64#ibcon#about to read 6, iclass 31, count 0 2006.257.06:20:52.64#ibcon#read 6, iclass 31, count 0 2006.257.06:20:52.64#ibcon#end of sib2, iclass 31, count 0 2006.257.06:20:52.64#ibcon#*after write, iclass 31, count 0 2006.257.06:20:52.64#ibcon#*before return 0, iclass 31, count 0 2006.257.06:20:52.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:52.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:52.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:20:52.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:20:52.64$vck44/va=2,7 2006.257.06:20:52.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.06:20:52.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.06:20:52.64#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:52.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:52.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:52.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:52.70#ibcon#enter wrdev, iclass 33, count 2 2006.257.06:20:52.70#ibcon#first serial, iclass 33, count 2 2006.257.06:20:52.70#ibcon#enter sib2, iclass 33, count 2 2006.257.06:20:52.70#ibcon#flushed, iclass 33, count 2 2006.257.06:20:52.70#ibcon#about to write, iclass 33, count 2 2006.257.06:20:52.70#ibcon#wrote, iclass 33, count 2 2006.257.06:20:52.70#ibcon#about to read 3, iclass 33, count 2 2006.257.06:20:52.72#ibcon#read 3, iclass 33, count 2 2006.257.06:20:52.72#ibcon#about to read 4, iclass 33, count 2 2006.257.06:20:52.72#ibcon#read 4, iclass 33, count 2 2006.257.06:20:52.72#ibcon#about to read 5, iclass 33, count 2 2006.257.06:20:52.72#ibcon#read 5, iclass 33, count 2 2006.257.06:20:52.72#ibcon#about to read 6, iclass 33, count 2 2006.257.06:20:52.72#ibcon#read 6, iclass 33, count 2 2006.257.06:20:52.72#ibcon#end of sib2, iclass 33, count 2 2006.257.06:20:52.72#ibcon#*mode == 0, iclass 33, count 2 2006.257.06:20:52.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.06:20:52.72#ibcon#[25=AT02-07\r\n] 2006.257.06:20:52.72#ibcon#*before write, iclass 33, count 2 2006.257.06:20:52.72#ibcon#enter sib2, iclass 33, count 2 2006.257.06:20:52.72#ibcon#flushed, iclass 33, count 2 2006.257.06:20:52.72#ibcon#about to write, iclass 33, count 2 2006.257.06:20:52.72#ibcon#wrote, iclass 33, count 2 2006.257.06:20:52.72#ibcon#about to read 3, iclass 33, count 2 2006.257.06:20:52.75#ibcon#read 3, iclass 33, count 2 2006.257.06:20:52.75#ibcon#about to read 4, iclass 33, count 2 2006.257.06:20:52.75#ibcon#read 4, iclass 33, count 2 2006.257.06:20:52.75#ibcon#about to read 5, iclass 33, count 2 2006.257.06:20:52.75#ibcon#read 5, iclass 33, count 2 2006.257.06:20:52.75#ibcon#about to read 6, iclass 33, count 2 2006.257.06:20:52.75#ibcon#read 6, iclass 33, count 2 2006.257.06:20:52.75#ibcon#end of sib2, iclass 33, count 2 2006.257.06:20:52.75#ibcon#*after write, iclass 33, count 2 2006.257.06:20:52.75#ibcon#*before return 0, iclass 33, count 2 2006.257.06:20:52.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:52.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:52.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.06:20:52.75#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:52.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:52.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:52.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:52.87#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:20:52.87#ibcon#first serial, iclass 33, count 0 2006.257.06:20:52.87#ibcon#enter sib2, iclass 33, count 0 2006.257.06:20:52.87#ibcon#flushed, iclass 33, count 0 2006.257.06:20:52.87#ibcon#about to write, iclass 33, count 0 2006.257.06:20:52.87#ibcon#wrote, iclass 33, count 0 2006.257.06:20:52.87#ibcon#about to read 3, iclass 33, count 0 2006.257.06:20:52.89#ibcon#read 3, iclass 33, count 0 2006.257.06:20:52.89#ibcon#about to read 4, iclass 33, count 0 2006.257.06:20:52.89#ibcon#read 4, iclass 33, count 0 2006.257.06:20:52.89#ibcon#about to read 5, iclass 33, count 0 2006.257.06:20:52.89#ibcon#read 5, iclass 33, count 0 2006.257.06:20:52.89#ibcon#about to read 6, iclass 33, count 0 2006.257.06:20:52.89#ibcon#read 6, iclass 33, count 0 2006.257.06:20:52.89#ibcon#end of sib2, iclass 33, count 0 2006.257.06:20:52.89#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:20:52.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:20:52.89#ibcon#[25=USB\r\n] 2006.257.06:20:52.89#ibcon#*before write, iclass 33, count 0 2006.257.06:20:52.89#ibcon#enter sib2, iclass 33, count 0 2006.257.06:20:52.89#ibcon#flushed, iclass 33, count 0 2006.257.06:20:52.89#ibcon#about to write, iclass 33, count 0 2006.257.06:20:52.89#ibcon#wrote, iclass 33, count 0 2006.257.06:20:52.89#ibcon#about to read 3, iclass 33, count 0 2006.257.06:20:52.92#ibcon#read 3, iclass 33, count 0 2006.257.06:20:52.92#ibcon#about to read 4, iclass 33, count 0 2006.257.06:20:52.92#ibcon#read 4, iclass 33, count 0 2006.257.06:20:52.92#ibcon#about to read 5, iclass 33, count 0 2006.257.06:20:52.92#ibcon#read 5, iclass 33, count 0 2006.257.06:20:52.92#ibcon#about to read 6, iclass 33, count 0 2006.257.06:20:52.92#ibcon#read 6, iclass 33, count 0 2006.257.06:20:52.92#ibcon#end of sib2, iclass 33, count 0 2006.257.06:20:52.92#ibcon#*after write, iclass 33, count 0 2006.257.06:20:52.92#ibcon#*before return 0, iclass 33, count 0 2006.257.06:20:52.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:52.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:52.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:20:52.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:20:52.92$vck44/valo=3,564.99 2006.257.06:20:52.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:20:52.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:20:52.92#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:52.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:52.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:52.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:52.92#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:20:52.92#ibcon#first serial, iclass 35, count 0 2006.257.06:20:52.92#ibcon#enter sib2, iclass 35, count 0 2006.257.06:20:52.92#ibcon#flushed, iclass 35, count 0 2006.257.06:20:52.92#ibcon#about to write, iclass 35, count 0 2006.257.06:20:52.92#ibcon#wrote, iclass 35, count 0 2006.257.06:20:52.92#ibcon#about to read 3, iclass 35, count 0 2006.257.06:20:52.94#ibcon#read 3, iclass 35, count 0 2006.257.06:20:52.94#ibcon#about to read 4, iclass 35, count 0 2006.257.06:20:52.94#ibcon#read 4, iclass 35, count 0 2006.257.06:20:52.94#ibcon#about to read 5, iclass 35, count 0 2006.257.06:20:52.94#ibcon#read 5, iclass 35, count 0 2006.257.06:20:52.94#ibcon#about to read 6, iclass 35, count 0 2006.257.06:20:52.94#ibcon#read 6, iclass 35, count 0 2006.257.06:20:52.94#ibcon#end of sib2, iclass 35, count 0 2006.257.06:20:52.94#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:20:52.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:20:52.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:20:52.94#ibcon#*before write, iclass 35, count 0 2006.257.06:20:52.94#ibcon#enter sib2, iclass 35, count 0 2006.257.06:20:52.94#ibcon#flushed, iclass 35, count 0 2006.257.06:20:52.94#ibcon#about to write, iclass 35, count 0 2006.257.06:20:52.94#ibcon#wrote, iclass 35, count 0 2006.257.06:20:52.94#ibcon#about to read 3, iclass 35, count 0 2006.257.06:20:52.98#abcon#<5=/15 1.2 3.4 20.43 891012.2\r\n> 2006.257.06:20:52.98#ibcon#read 3, iclass 35, count 0 2006.257.06:20:52.98#ibcon#about to read 4, iclass 35, count 0 2006.257.06:20:52.98#ibcon#read 4, iclass 35, count 0 2006.257.06:20:52.98#ibcon#about to read 5, iclass 35, count 0 2006.257.06:20:52.98#ibcon#read 5, iclass 35, count 0 2006.257.06:20:52.98#ibcon#about to read 6, iclass 35, count 0 2006.257.06:20:52.98#ibcon#read 6, iclass 35, count 0 2006.257.06:20:52.98#ibcon#end of sib2, iclass 35, count 0 2006.257.06:20:52.98#ibcon#*after write, iclass 35, count 0 2006.257.06:20:52.98#ibcon#*before return 0, iclass 35, count 0 2006.257.06:20:52.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:52.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:52.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:20:52.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:20:52.98$vck44/va=3,8 2006.257.06:20:52.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.06:20:52.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.06:20:52.98#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:52.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:20:53.00#abcon#{5=INTERFACE CLEAR} 2006.257.06:20:53.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:20:53.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:20:53.04#ibcon#enter wrdev, iclass 40, count 2 2006.257.06:20:53.04#ibcon#first serial, iclass 40, count 2 2006.257.06:20:53.04#ibcon#enter sib2, iclass 40, count 2 2006.257.06:20:53.04#ibcon#flushed, iclass 40, count 2 2006.257.06:20:53.04#ibcon#about to write, iclass 40, count 2 2006.257.06:20:53.04#ibcon#wrote, iclass 40, count 2 2006.257.06:20:53.04#ibcon#about to read 3, iclass 40, count 2 2006.257.06:20:53.06#ibcon#read 3, iclass 40, count 2 2006.257.06:20:53.06#ibcon#about to read 4, iclass 40, count 2 2006.257.06:20:53.06#ibcon#read 4, iclass 40, count 2 2006.257.06:20:53.06#ibcon#about to read 5, iclass 40, count 2 2006.257.06:20:53.06#ibcon#read 5, iclass 40, count 2 2006.257.06:20:53.06#ibcon#about to read 6, iclass 40, count 2 2006.257.06:20:53.06#ibcon#read 6, iclass 40, count 2 2006.257.06:20:53.06#ibcon#end of sib2, iclass 40, count 2 2006.257.06:20:53.06#ibcon#*mode == 0, iclass 40, count 2 2006.257.06:20:53.06#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.06:20:53.06#ibcon#[25=AT03-08\r\n] 2006.257.06:20:53.06#ibcon#*before write, iclass 40, count 2 2006.257.06:20:53.06#ibcon#enter sib2, iclass 40, count 2 2006.257.06:20:53.06#ibcon#flushed, iclass 40, count 2 2006.257.06:20:53.06#ibcon#about to write, iclass 40, count 2 2006.257.06:20:53.06#ibcon#wrote, iclass 40, count 2 2006.257.06:20:53.06#ibcon#about to read 3, iclass 40, count 2 2006.257.06:20:53.06#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:20:53.09#ibcon#read 3, iclass 40, count 2 2006.257.06:20:53.09#ibcon#about to read 4, iclass 40, count 2 2006.257.06:20:53.09#ibcon#read 4, iclass 40, count 2 2006.257.06:20:53.09#ibcon#about to read 5, iclass 40, count 2 2006.257.06:20:53.09#ibcon#read 5, iclass 40, count 2 2006.257.06:20:53.09#ibcon#about to read 6, iclass 40, count 2 2006.257.06:20:53.09#ibcon#read 6, iclass 40, count 2 2006.257.06:20:53.09#ibcon#end of sib2, iclass 40, count 2 2006.257.06:20:53.09#ibcon#*after write, iclass 40, count 2 2006.257.06:20:53.09#ibcon#*before return 0, iclass 40, count 2 2006.257.06:20:53.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:20:53.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:20:53.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.06:20:53.09#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:53.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:20:53.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:20:53.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:20:53.21#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:20:53.21#ibcon#first serial, iclass 40, count 0 2006.257.06:20:53.21#ibcon#enter sib2, iclass 40, count 0 2006.257.06:20:53.21#ibcon#flushed, iclass 40, count 0 2006.257.06:20:53.21#ibcon#about to write, iclass 40, count 0 2006.257.06:20:53.21#ibcon#wrote, iclass 40, count 0 2006.257.06:20:53.21#ibcon#about to read 3, iclass 40, count 0 2006.257.06:20:53.23#ibcon#read 3, iclass 40, count 0 2006.257.06:20:53.23#ibcon#about to read 4, iclass 40, count 0 2006.257.06:20:53.23#ibcon#read 4, iclass 40, count 0 2006.257.06:20:53.23#ibcon#about to read 5, iclass 40, count 0 2006.257.06:20:53.23#ibcon#read 5, iclass 40, count 0 2006.257.06:20:53.23#ibcon#about to read 6, iclass 40, count 0 2006.257.06:20:53.23#ibcon#read 6, iclass 40, count 0 2006.257.06:20:53.23#ibcon#end of sib2, iclass 40, count 0 2006.257.06:20:53.23#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:20:53.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:20:53.23#ibcon#[25=USB\r\n] 2006.257.06:20:53.23#ibcon#*before write, iclass 40, count 0 2006.257.06:20:53.23#ibcon#enter sib2, iclass 40, count 0 2006.257.06:20:53.23#ibcon#flushed, iclass 40, count 0 2006.257.06:20:53.23#ibcon#about to write, iclass 40, count 0 2006.257.06:20:53.23#ibcon#wrote, iclass 40, count 0 2006.257.06:20:53.23#ibcon#about to read 3, iclass 40, count 0 2006.257.06:20:53.26#ibcon#read 3, iclass 40, count 0 2006.257.06:20:53.26#ibcon#about to read 4, iclass 40, count 0 2006.257.06:20:53.26#ibcon#read 4, iclass 40, count 0 2006.257.06:20:53.26#ibcon#about to read 5, iclass 40, count 0 2006.257.06:20:53.26#ibcon#read 5, iclass 40, count 0 2006.257.06:20:53.26#ibcon#about to read 6, iclass 40, count 0 2006.257.06:20:53.26#ibcon#read 6, iclass 40, count 0 2006.257.06:20:53.26#ibcon#end of sib2, iclass 40, count 0 2006.257.06:20:53.26#ibcon#*after write, iclass 40, count 0 2006.257.06:20:53.26#ibcon#*before return 0, iclass 40, count 0 2006.257.06:20:53.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:20:53.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:20:53.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:20:53.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:20:53.26$vck44/valo=4,624.99 2006.257.06:20:53.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.06:20:53.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.06:20:53.26#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:53.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:53.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:53.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:53.26#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:20:53.26#ibcon#first serial, iclass 5, count 0 2006.257.06:20:53.26#ibcon#enter sib2, iclass 5, count 0 2006.257.06:20:53.26#ibcon#flushed, iclass 5, count 0 2006.257.06:20:53.26#ibcon#about to write, iclass 5, count 0 2006.257.06:20:53.26#ibcon#wrote, iclass 5, count 0 2006.257.06:20:53.26#ibcon#about to read 3, iclass 5, count 0 2006.257.06:20:53.28#ibcon#read 3, iclass 5, count 0 2006.257.06:20:53.28#ibcon#about to read 4, iclass 5, count 0 2006.257.06:20:53.28#ibcon#read 4, iclass 5, count 0 2006.257.06:20:53.28#ibcon#about to read 5, iclass 5, count 0 2006.257.06:20:53.28#ibcon#read 5, iclass 5, count 0 2006.257.06:20:53.28#ibcon#about to read 6, iclass 5, count 0 2006.257.06:20:53.28#ibcon#read 6, iclass 5, count 0 2006.257.06:20:53.28#ibcon#end of sib2, iclass 5, count 0 2006.257.06:20:53.28#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:20:53.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:20:53.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:20:53.28#ibcon#*before write, iclass 5, count 0 2006.257.06:20:53.28#ibcon#enter sib2, iclass 5, count 0 2006.257.06:20:53.28#ibcon#flushed, iclass 5, count 0 2006.257.06:20:53.28#ibcon#about to write, iclass 5, count 0 2006.257.06:20:53.28#ibcon#wrote, iclass 5, count 0 2006.257.06:20:53.28#ibcon#about to read 3, iclass 5, count 0 2006.257.06:20:53.32#ibcon#read 3, iclass 5, count 0 2006.257.06:20:53.32#ibcon#about to read 4, iclass 5, count 0 2006.257.06:20:53.32#ibcon#read 4, iclass 5, count 0 2006.257.06:20:53.32#ibcon#about to read 5, iclass 5, count 0 2006.257.06:20:53.32#ibcon#read 5, iclass 5, count 0 2006.257.06:20:53.32#ibcon#about to read 6, iclass 5, count 0 2006.257.06:20:53.32#ibcon#read 6, iclass 5, count 0 2006.257.06:20:53.32#ibcon#end of sib2, iclass 5, count 0 2006.257.06:20:53.32#ibcon#*after write, iclass 5, count 0 2006.257.06:20:53.32#ibcon#*before return 0, iclass 5, count 0 2006.257.06:20:53.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:53.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:53.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:20:53.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:20:53.32$vck44/va=4,7 2006.257.06:20:53.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.06:20:53.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.06:20:53.32#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:53.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:53.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:53.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:53.38#ibcon#enter wrdev, iclass 7, count 2 2006.257.06:20:53.38#ibcon#first serial, iclass 7, count 2 2006.257.06:20:53.38#ibcon#enter sib2, iclass 7, count 2 2006.257.06:20:53.38#ibcon#flushed, iclass 7, count 2 2006.257.06:20:53.38#ibcon#about to write, iclass 7, count 2 2006.257.06:20:53.38#ibcon#wrote, iclass 7, count 2 2006.257.06:20:53.38#ibcon#about to read 3, iclass 7, count 2 2006.257.06:20:53.40#ibcon#read 3, iclass 7, count 2 2006.257.06:20:53.40#ibcon#about to read 4, iclass 7, count 2 2006.257.06:20:53.40#ibcon#read 4, iclass 7, count 2 2006.257.06:20:53.40#ibcon#about to read 5, iclass 7, count 2 2006.257.06:20:53.40#ibcon#read 5, iclass 7, count 2 2006.257.06:20:53.40#ibcon#about to read 6, iclass 7, count 2 2006.257.06:20:53.40#ibcon#read 6, iclass 7, count 2 2006.257.06:20:53.40#ibcon#end of sib2, iclass 7, count 2 2006.257.06:20:53.40#ibcon#*mode == 0, iclass 7, count 2 2006.257.06:20:53.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.06:20:53.40#ibcon#[25=AT04-07\r\n] 2006.257.06:20:53.40#ibcon#*before write, iclass 7, count 2 2006.257.06:20:53.40#ibcon#enter sib2, iclass 7, count 2 2006.257.06:20:53.40#ibcon#flushed, iclass 7, count 2 2006.257.06:20:53.40#ibcon#about to write, iclass 7, count 2 2006.257.06:20:53.40#ibcon#wrote, iclass 7, count 2 2006.257.06:20:53.40#ibcon#about to read 3, iclass 7, count 2 2006.257.06:20:53.43#ibcon#read 3, iclass 7, count 2 2006.257.06:20:53.43#ibcon#about to read 4, iclass 7, count 2 2006.257.06:20:53.43#ibcon#read 4, iclass 7, count 2 2006.257.06:20:53.43#ibcon#about to read 5, iclass 7, count 2 2006.257.06:20:53.43#ibcon#read 5, iclass 7, count 2 2006.257.06:20:53.43#ibcon#about to read 6, iclass 7, count 2 2006.257.06:20:53.43#ibcon#read 6, iclass 7, count 2 2006.257.06:20:53.43#ibcon#end of sib2, iclass 7, count 2 2006.257.06:20:53.43#ibcon#*after write, iclass 7, count 2 2006.257.06:20:53.43#ibcon#*before return 0, iclass 7, count 2 2006.257.06:20:53.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:53.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:53.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.06:20:53.43#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:53.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:53.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:53.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:53.55#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:20:53.55#ibcon#first serial, iclass 7, count 0 2006.257.06:20:53.55#ibcon#enter sib2, iclass 7, count 0 2006.257.06:20:53.55#ibcon#flushed, iclass 7, count 0 2006.257.06:20:53.55#ibcon#about to write, iclass 7, count 0 2006.257.06:20:53.55#ibcon#wrote, iclass 7, count 0 2006.257.06:20:53.55#ibcon#about to read 3, iclass 7, count 0 2006.257.06:20:53.57#ibcon#read 3, iclass 7, count 0 2006.257.06:20:53.57#ibcon#about to read 4, iclass 7, count 0 2006.257.06:20:53.57#ibcon#read 4, iclass 7, count 0 2006.257.06:20:53.57#ibcon#about to read 5, iclass 7, count 0 2006.257.06:20:53.57#ibcon#read 5, iclass 7, count 0 2006.257.06:20:53.57#ibcon#about to read 6, iclass 7, count 0 2006.257.06:20:53.57#ibcon#read 6, iclass 7, count 0 2006.257.06:20:53.57#ibcon#end of sib2, iclass 7, count 0 2006.257.06:20:53.57#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:20:53.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:20:53.57#ibcon#[25=USB\r\n] 2006.257.06:20:53.57#ibcon#*before write, iclass 7, count 0 2006.257.06:20:53.57#ibcon#enter sib2, iclass 7, count 0 2006.257.06:20:53.57#ibcon#flushed, iclass 7, count 0 2006.257.06:20:53.57#ibcon#about to write, iclass 7, count 0 2006.257.06:20:53.57#ibcon#wrote, iclass 7, count 0 2006.257.06:20:53.57#ibcon#about to read 3, iclass 7, count 0 2006.257.06:20:53.60#ibcon#read 3, iclass 7, count 0 2006.257.06:20:53.60#ibcon#about to read 4, iclass 7, count 0 2006.257.06:20:53.60#ibcon#read 4, iclass 7, count 0 2006.257.06:20:53.60#ibcon#about to read 5, iclass 7, count 0 2006.257.06:20:53.60#ibcon#read 5, iclass 7, count 0 2006.257.06:20:53.60#ibcon#about to read 6, iclass 7, count 0 2006.257.06:20:53.60#ibcon#read 6, iclass 7, count 0 2006.257.06:20:53.60#ibcon#end of sib2, iclass 7, count 0 2006.257.06:20:53.60#ibcon#*after write, iclass 7, count 0 2006.257.06:20:53.60#ibcon#*before return 0, iclass 7, count 0 2006.257.06:20:53.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:53.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:53.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:20:53.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:20:53.60$vck44/valo=5,734.99 2006.257.06:20:53.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.06:20:53.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.06:20:53.60#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:53.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:53.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:53.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:53.60#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:20:53.60#ibcon#first serial, iclass 11, count 0 2006.257.06:20:53.60#ibcon#enter sib2, iclass 11, count 0 2006.257.06:20:53.60#ibcon#flushed, iclass 11, count 0 2006.257.06:20:53.60#ibcon#about to write, iclass 11, count 0 2006.257.06:20:53.60#ibcon#wrote, iclass 11, count 0 2006.257.06:20:53.60#ibcon#about to read 3, iclass 11, count 0 2006.257.06:20:53.62#ibcon#read 3, iclass 11, count 0 2006.257.06:20:53.62#ibcon#about to read 4, iclass 11, count 0 2006.257.06:20:53.62#ibcon#read 4, iclass 11, count 0 2006.257.06:20:53.62#ibcon#about to read 5, iclass 11, count 0 2006.257.06:20:53.62#ibcon#read 5, iclass 11, count 0 2006.257.06:20:53.62#ibcon#about to read 6, iclass 11, count 0 2006.257.06:20:53.62#ibcon#read 6, iclass 11, count 0 2006.257.06:20:53.62#ibcon#end of sib2, iclass 11, count 0 2006.257.06:20:53.62#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:20:53.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:20:53.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:20:53.62#ibcon#*before write, iclass 11, count 0 2006.257.06:20:53.62#ibcon#enter sib2, iclass 11, count 0 2006.257.06:20:53.62#ibcon#flushed, iclass 11, count 0 2006.257.06:20:53.62#ibcon#about to write, iclass 11, count 0 2006.257.06:20:53.62#ibcon#wrote, iclass 11, count 0 2006.257.06:20:53.62#ibcon#about to read 3, iclass 11, count 0 2006.257.06:20:53.66#ibcon#read 3, iclass 11, count 0 2006.257.06:20:53.66#ibcon#about to read 4, iclass 11, count 0 2006.257.06:20:53.66#ibcon#read 4, iclass 11, count 0 2006.257.06:20:53.66#ibcon#about to read 5, iclass 11, count 0 2006.257.06:20:53.66#ibcon#read 5, iclass 11, count 0 2006.257.06:20:53.66#ibcon#about to read 6, iclass 11, count 0 2006.257.06:20:53.66#ibcon#read 6, iclass 11, count 0 2006.257.06:20:53.66#ibcon#end of sib2, iclass 11, count 0 2006.257.06:20:53.66#ibcon#*after write, iclass 11, count 0 2006.257.06:20:53.66#ibcon#*before return 0, iclass 11, count 0 2006.257.06:20:53.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:53.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:53.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:20:53.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:20:53.66$vck44/va=5,4 2006.257.06:20:53.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.06:20:53.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.06:20:53.66#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:53.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:53.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:53.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:53.72#ibcon#enter wrdev, iclass 13, count 2 2006.257.06:20:53.72#ibcon#first serial, iclass 13, count 2 2006.257.06:20:53.72#ibcon#enter sib2, iclass 13, count 2 2006.257.06:20:53.72#ibcon#flushed, iclass 13, count 2 2006.257.06:20:53.72#ibcon#about to write, iclass 13, count 2 2006.257.06:20:53.72#ibcon#wrote, iclass 13, count 2 2006.257.06:20:53.72#ibcon#about to read 3, iclass 13, count 2 2006.257.06:20:53.74#ibcon#read 3, iclass 13, count 2 2006.257.06:20:53.74#ibcon#about to read 4, iclass 13, count 2 2006.257.06:20:53.74#ibcon#read 4, iclass 13, count 2 2006.257.06:20:53.74#ibcon#about to read 5, iclass 13, count 2 2006.257.06:20:53.74#ibcon#read 5, iclass 13, count 2 2006.257.06:20:53.74#ibcon#about to read 6, iclass 13, count 2 2006.257.06:20:53.74#ibcon#read 6, iclass 13, count 2 2006.257.06:20:53.74#ibcon#end of sib2, iclass 13, count 2 2006.257.06:20:53.74#ibcon#*mode == 0, iclass 13, count 2 2006.257.06:20:53.74#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.06:20:53.74#ibcon#[25=AT05-04\r\n] 2006.257.06:20:53.74#ibcon#*before write, iclass 13, count 2 2006.257.06:20:53.74#ibcon#enter sib2, iclass 13, count 2 2006.257.06:20:53.74#ibcon#flushed, iclass 13, count 2 2006.257.06:20:53.74#ibcon#about to write, iclass 13, count 2 2006.257.06:20:53.74#ibcon#wrote, iclass 13, count 2 2006.257.06:20:53.74#ibcon#about to read 3, iclass 13, count 2 2006.257.06:20:53.77#ibcon#read 3, iclass 13, count 2 2006.257.06:20:53.77#ibcon#about to read 4, iclass 13, count 2 2006.257.06:20:53.77#ibcon#read 4, iclass 13, count 2 2006.257.06:20:53.77#ibcon#about to read 5, iclass 13, count 2 2006.257.06:20:53.77#ibcon#read 5, iclass 13, count 2 2006.257.06:20:53.77#ibcon#about to read 6, iclass 13, count 2 2006.257.06:20:53.77#ibcon#read 6, iclass 13, count 2 2006.257.06:20:53.77#ibcon#end of sib2, iclass 13, count 2 2006.257.06:20:53.77#ibcon#*after write, iclass 13, count 2 2006.257.06:20:53.77#ibcon#*before return 0, iclass 13, count 2 2006.257.06:20:53.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:53.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:53.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.06:20:53.77#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:53.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:53.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:53.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:53.89#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:20:53.89#ibcon#first serial, iclass 13, count 0 2006.257.06:20:53.89#ibcon#enter sib2, iclass 13, count 0 2006.257.06:20:53.89#ibcon#flushed, iclass 13, count 0 2006.257.06:20:53.89#ibcon#about to write, iclass 13, count 0 2006.257.06:20:53.89#ibcon#wrote, iclass 13, count 0 2006.257.06:20:53.89#ibcon#about to read 3, iclass 13, count 0 2006.257.06:20:53.91#ibcon#read 3, iclass 13, count 0 2006.257.06:20:53.91#ibcon#about to read 4, iclass 13, count 0 2006.257.06:20:53.91#ibcon#read 4, iclass 13, count 0 2006.257.06:20:53.91#ibcon#about to read 5, iclass 13, count 0 2006.257.06:20:53.91#ibcon#read 5, iclass 13, count 0 2006.257.06:20:53.91#ibcon#about to read 6, iclass 13, count 0 2006.257.06:20:53.91#ibcon#read 6, iclass 13, count 0 2006.257.06:20:53.91#ibcon#end of sib2, iclass 13, count 0 2006.257.06:20:53.91#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:20:53.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:20:53.91#ibcon#[25=USB\r\n] 2006.257.06:20:53.91#ibcon#*before write, iclass 13, count 0 2006.257.06:20:53.91#ibcon#enter sib2, iclass 13, count 0 2006.257.06:20:53.91#ibcon#flushed, iclass 13, count 0 2006.257.06:20:53.91#ibcon#about to write, iclass 13, count 0 2006.257.06:20:53.91#ibcon#wrote, iclass 13, count 0 2006.257.06:20:53.91#ibcon#about to read 3, iclass 13, count 0 2006.257.06:20:53.94#ibcon#read 3, iclass 13, count 0 2006.257.06:20:53.94#ibcon#about to read 4, iclass 13, count 0 2006.257.06:20:53.94#ibcon#read 4, iclass 13, count 0 2006.257.06:20:53.94#ibcon#about to read 5, iclass 13, count 0 2006.257.06:20:53.94#ibcon#read 5, iclass 13, count 0 2006.257.06:20:53.94#ibcon#about to read 6, iclass 13, count 0 2006.257.06:20:53.94#ibcon#read 6, iclass 13, count 0 2006.257.06:20:53.94#ibcon#end of sib2, iclass 13, count 0 2006.257.06:20:53.94#ibcon#*after write, iclass 13, count 0 2006.257.06:20:53.94#ibcon#*before return 0, iclass 13, count 0 2006.257.06:20:53.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:53.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:53.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:20:53.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:20:53.94$vck44/valo=6,814.99 2006.257.06:20:53.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.06:20:53.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.06:20:53.94#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:53.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:53.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:53.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:53.94#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:20:53.94#ibcon#first serial, iclass 15, count 0 2006.257.06:20:53.94#ibcon#enter sib2, iclass 15, count 0 2006.257.06:20:53.94#ibcon#flushed, iclass 15, count 0 2006.257.06:20:53.94#ibcon#about to write, iclass 15, count 0 2006.257.06:20:53.94#ibcon#wrote, iclass 15, count 0 2006.257.06:20:53.94#ibcon#about to read 3, iclass 15, count 0 2006.257.06:20:53.96#ibcon#read 3, iclass 15, count 0 2006.257.06:20:53.96#ibcon#about to read 4, iclass 15, count 0 2006.257.06:20:53.96#ibcon#read 4, iclass 15, count 0 2006.257.06:20:53.96#ibcon#about to read 5, iclass 15, count 0 2006.257.06:20:53.96#ibcon#read 5, iclass 15, count 0 2006.257.06:20:53.96#ibcon#about to read 6, iclass 15, count 0 2006.257.06:20:53.96#ibcon#read 6, iclass 15, count 0 2006.257.06:20:53.96#ibcon#end of sib2, iclass 15, count 0 2006.257.06:20:53.96#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:20:53.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:20:53.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:20:53.96#ibcon#*before write, iclass 15, count 0 2006.257.06:20:53.96#ibcon#enter sib2, iclass 15, count 0 2006.257.06:20:53.96#ibcon#flushed, iclass 15, count 0 2006.257.06:20:53.96#ibcon#about to write, iclass 15, count 0 2006.257.06:20:53.96#ibcon#wrote, iclass 15, count 0 2006.257.06:20:53.96#ibcon#about to read 3, iclass 15, count 0 2006.257.06:20:54.00#ibcon#read 3, iclass 15, count 0 2006.257.06:20:54.00#ibcon#about to read 4, iclass 15, count 0 2006.257.06:20:54.00#ibcon#read 4, iclass 15, count 0 2006.257.06:20:54.00#ibcon#about to read 5, iclass 15, count 0 2006.257.06:20:54.00#ibcon#read 5, iclass 15, count 0 2006.257.06:20:54.00#ibcon#about to read 6, iclass 15, count 0 2006.257.06:20:54.00#ibcon#read 6, iclass 15, count 0 2006.257.06:20:54.00#ibcon#end of sib2, iclass 15, count 0 2006.257.06:20:54.00#ibcon#*after write, iclass 15, count 0 2006.257.06:20:54.00#ibcon#*before return 0, iclass 15, count 0 2006.257.06:20:54.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:54.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:54.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:20:54.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:20:54.00$vck44/va=6,4 2006.257.06:20:54.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.06:20:54.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.06:20:54.00#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:54.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:54.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:54.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:54.06#ibcon#enter wrdev, iclass 17, count 2 2006.257.06:20:54.06#ibcon#first serial, iclass 17, count 2 2006.257.06:20:54.06#ibcon#enter sib2, iclass 17, count 2 2006.257.06:20:54.06#ibcon#flushed, iclass 17, count 2 2006.257.06:20:54.06#ibcon#about to write, iclass 17, count 2 2006.257.06:20:54.06#ibcon#wrote, iclass 17, count 2 2006.257.06:20:54.06#ibcon#about to read 3, iclass 17, count 2 2006.257.06:20:54.08#ibcon#read 3, iclass 17, count 2 2006.257.06:20:54.08#ibcon#about to read 4, iclass 17, count 2 2006.257.06:20:54.08#ibcon#read 4, iclass 17, count 2 2006.257.06:20:54.08#ibcon#about to read 5, iclass 17, count 2 2006.257.06:20:54.08#ibcon#read 5, iclass 17, count 2 2006.257.06:20:54.08#ibcon#about to read 6, iclass 17, count 2 2006.257.06:20:54.08#ibcon#read 6, iclass 17, count 2 2006.257.06:20:54.08#ibcon#end of sib2, iclass 17, count 2 2006.257.06:20:54.08#ibcon#*mode == 0, iclass 17, count 2 2006.257.06:20:54.08#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.06:20:54.08#ibcon#[25=AT06-04\r\n] 2006.257.06:20:54.08#ibcon#*before write, iclass 17, count 2 2006.257.06:20:54.08#ibcon#enter sib2, iclass 17, count 2 2006.257.06:20:54.08#ibcon#flushed, iclass 17, count 2 2006.257.06:20:54.08#ibcon#about to write, iclass 17, count 2 2006.257.06:20:54.08#ibcon#wrote, iclass 17, count 2 2006.257.06:20:54.08#ibcon#about to read 3, iclass 17, count 2 2006.257.06:20:54.11#ibcon#read 3, iclass 17, count 2 2006.257.06:20:54.11#ibcon#about to read 4, iclass 17, count 2 2006.257.06:20:54.11#ibcon#read 4, iclass 17, count 2 2006.257.06:20:54.11#ibcon#about to read 5, iclass 17, count 2 2006.257.06:20:54.11#ibcon#read 5, iclass 17, count 2 2006.257.06:20:54.11#ibcon#about to read 6, iclass 17, count 2 2006.257.06:20:54.11#ibcon#read 6, iclass 17, count 2 2006.257.06:20:54.11#ibcon#end of sib2, iclass 17, count 2 2006.257.06:20:54.11#ibcon#*after write, iclass 17, count 2 2006.257.06:20:54.11#ibcon#*before return 0, iclass 17, count 2 2006.257.06:20:54.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:54.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:54.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.06:20:54.11#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:54.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:54.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:54.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:54.23#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:20:54.23#ibcon#first serial, iclass 17, count 0 2006.257.06:20:54.23#ibcon#enter sib2, iclass 17, count 0 2006.257.06:20:54.23#ibcon#flushed, iclass 17, count 0 2006.257.06:20:54.23#ibcon#about to write, iclass 17, count 0 2006.257.06:20:54.23#ibcon#wrote, iclass 17, count 0 2006.257.06:20:54.23#ibcon#about to read 3, iclass 17, count 0 2006.257.06:20:54.25#ibcon#read 3, iclass 17, count 0 2006.257.06:20:54.25#ibcon#about to read 4, iclass 17, count 0 2006.257.06:20:54.25#ibcon#read 4, iclass 17, count 0 2006.257.06:20:54.25#ibcon#about to read 5, iclass 17, count 0 2006.257.06:20:54.25#ibcon#read 5, iclass 17, count 0 2006.257.06:20:54.25#ibcon#about to read 6, iclass 17, count 0 2006.257.06:20:54.25#ibcon#read 6, iclass 17, count 0 2006.257.06:20:54.25#ibcon#end of sib2, iclass 17, count 0 2006.257.06:20:54.25#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:20:54.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:20:54.25#ibcon#[25=USB\r\n] 2006.257.06:20:54.25#ibcon#*before write, iclass 17, count 0 2006.257.06:20:54.25#ibcon#enter sib2, iclass 17, count 0 2006.257.06:20:54.25#ibcon#flushed, iclass 17, count 0 2006.257.06:20:54.25#ibcon#about to write, iclass 17, count 0 2006.257.06:20:54.25#ibcon#wrote, iclass 17, count 0 2006.257.06:20:54.25#ibcon#about to read 3, iclass 17, count 0 2006.257.06:20:54.28#ibcon#read 3, iclass 17, count 0 2006.257.06:20:54.28#ibcon#about to read 4, iclass 17, count 0 2006.257.06:20:54.28#ibcon#read 4, iclass 17, count 0 2006.257.06:20:54.28#ibcon#about to read 5, iclass 17, count 0 2006.257.06:20:54.28#ibcon#read 5, iclass 17, count 0 2006.257.06:20:54.28#ibcon#about to read 6, iclass 17, count 0 2006.257.06:20:54.28#ibcon#read 6, iclass 17, count 0 2006.257.06:20:54.28#ibcon#end of sib2, iclass 17, count 0 2006.257.06:20:54.28#ibcon#*after write, iclass 17, count 0 2006.257.06:20:54.28#ibcon#*before return 0, iclass 17, count 0 2006.257.06:20:54.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:54.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:54.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:20:54.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:20:54.28$vck44/valo=7,864.99 2006.257.06:20:54.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.06:20:54.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.06:20:54.28#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:54.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:54.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:54.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:54.28#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:20:54.28#ibcon#first serial, iclass 19, count 0 2006.257.06:20:54.28#ibcon#enter sib2, iclass 19, count 0 2006.257.06:20:54.28#ibcon#flushed, iclass 19, count 0 2006.257.06:20:54.28#ibcon#about to write, iclass 19, count 0 2006.257.06:20:54.28#ibcon#wrote, iclass 19, count 0 2006.257.06:20:54.28#ibcon#about to read 3, iclass 19, count 0 2006.257.06:20:54.30#ibcon#read 3, iclass 19, count 0 2006.257.06:20:54.30#ibcon#about to read 4, iclass 19, count 0 2006.257.06:20:54.30#ibcon#read 4, iclass 19, count 0 2006.257.06:20:54.30#ibcon#about to read 5, iclass 19, count 0 2006.257.06:20:54.30#ibcon#read 5, iclass 19, count 0 2006.257.06:20:54.30#ibcon#about to read 6, iclass 19, count 0 2006.257.06:20:54.30#ibcon#read 6, iclass 19, count 0 2006.257.06:20:54.30#ibcon#end of sib2, iclass 19, count 0 2006.257.06:20:54.30#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:20:54.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:20:54.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:20:54.30#ibcon#*before write, iclass 19, count 0 2006.257.06:20:54.30#ibcon#enter sib2, iclass 19, count 0 2006.257.06:20:54.30#ibcon#flushed, iclass 19, count 0 2006.257.06:20:54.30#ibcon#about to write, iclass 19, count 0 2006.257.06:20:54.30#ibcon#wrote, iclass 19, count 0 2006.257.06:20:54.30#ibcon#about to read 3, iclass 19, count 0 2006.257.06:20:54.34#ibcon#read 3, iclass 19, count 0 2006.257.06:20:54.34#ibcon#about to read 4, iclass 19, count 0 2006.257.06:20:54.34#ibcon#read 4, iclass 19, count 0 2006.257.06:20:54.34#ibcon#about to read 5, iclass 19, count 0 2006.257.06:20:54.34#ibcon#read 5, iclass 19, count 0 2006.257.06:20:54.34#ibcon#about to read 6, iclass 19, count 0 2006.257.06:20:54.34#ibcon#read 6, iclass 19, count 0 2006.257.06:20:54.34#ibcon#end of sib2, iclass 19, count 0 2006.257.06:20:54.34#ibcon#*after write, iclass 19, count 0 2006.257.06:20:54.34#ibcon#*before return 0, iclass 19, count 0 2006.257.06:20:54.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:54.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:54.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:20:54.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:20:54.34$vck44/va=7,4 2006.257.06:20:54.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.06:20:54.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.06:20:54.34#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:54.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:54.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:54.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:54.40#ibcon#enter wrdev, iclass 21, count 2 2006.257.06:20:54.40#ibcon#first serial, iclass 21, count 2 2006.257.06:20:54.40#ibcon#enter sib2, iclass 21, count 2 2006.257.06:20:54.40#ibcon#flushed, iclass 21, count 2 2006.257.06:20:54.40#ibcon#about to write, iclass 21, count 2 2006.257.06:20:54.40#ibcon#wrote, iclass 21, count 2 2006.257.06:20:54.40#ibcon#about to read 3, iclass 21, count 2 2006.257.06:20:54.42#ibcon#read 3, iclass 21, count 2 2006.257.06:20:54.42#ibcon#about to read 4, iclass 21, count 2 2006.257.06:20:54.42#ibcon#read 4, iclass 21, count 2 2006.257.06:20:54.42#ibcon#about to read 5, iclass 21, count 2 2006.257.06:20:54.42#ibcon#read 5, iclass 21, count 2 2006.257.06:20:54.42#ibcon#about to read 6, iclass 21, count 2 2006.257.06:20:54.42#ibcon#read 6, iclass 21, count 2 2006.257.06:20:54.42#ibcon#end of sib2, iclass 21, count 2 2006.257.06:20:54.42#ibcon#*mode == 0, iclass 21, count 2 2006.257.06:20:54.42#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.06:20:54.42#ibcon#[25=AT07-04\r\n] 2006.257.06:20:54.42#ibcon#*before write, iclass 21, count 2 2006.257.06:20:54.42#ibcon#enter sib2, iclass 21, count 2 2006.257.06:20:54.42#ibcon#flushed, iclass 21, count 2 2006.257.06:20:54.42#ibcon#about to write, iclass 21, count 2 2006.257.06:20:54.42#ibcon#wrote, iclass 21, count 2 2006.257.06:20:54.42#ibcon#about to read 3, iclass 21, count 2 2006.257.06:20:54.45#ibcon#read 3, iclass 21, count 2 2006.257.06:20:54.45#ibcon#about to read 4, iclass 21, count 2 2006.257.06:20:54.45#ibcon#read 4, iclass 21, count 2 2006.257.06:20:54.45#ibcon#about to read 5, iclass 21, count 2 2006.257.06:20:54.45#ibcon#read 5, iclass 21, count 2 2006.257.06:20:54.45#ibcon#about to read 6, iclass 21, count 2 2006.257.06:20:54.45#ibcon#read 6, iclass 21, count 2 2006.257.06:20:54.45#ibcon#end of sib2, iclass 21, count 2 2006.257.06:20:54.45#ibcon#*after write, iclass 21, count 2 2006.257.06:20:54.45#ibcon#*before return 0, iclass 21, count 2 2006.257.06:20:54.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:54.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:54.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.06:20:54.45#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:54.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:54.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:54.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:54.57#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:20:54.57#ibcon#first serial, iclass 21, count 0 2006.257.06:20:54.57#ibcon#enter sib2, iclass 21, count 0 2006.257.06:20:54.57#ibcon#flushed, iclass 21, count 0 2006.257.06:20:54.57#ibcon#about to write, iclass 21, count 0 2006.257.06:20:54.57#ibcon#wrote, iclass 21, count 0 2006.257.06:20:54.57#ibcon#about to read 3, iclass 21, count 0 2006.257.06:20:54.59#ibcon#read 3, iclass 21, count 0 2006.257.06:20:54.59#ibcon#about to read 4, iclass 21, count 0 2006.257.06:20:54.59#ibcon#read 4, iclass 21, count 0 2006.257.06:20:54.59#ibcon#about to read 5, iclass 21, count 0 2006.257.06:20:54.59#ibcon#read 5, iclass 21, count 0 2006.257.06:20:54.59#ibcon#about to read 6, iclass 21, count 0 2006.257.06:20:54.59#ibcon#read 6, iclass 21, count 0 2006.257.06:20:54.59#ibcon#end of sib2, iclass 21, count 0 2006.257.06:20:54.59#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:20:54.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:20:54.59#ibcon#[25=USB\r\n] 2006.257.06:20:54.59#ibcon#*before write, iclass 21, count 0 2006.257.06:20:54.59#ibcon#enter sib2, iclass 21, count 0 2006.257.06:20:54.59#ibcon#flushed, iclass 21, count 0 2006.257.06:20:54.59#ibcon#about to write, iclass 21, count 0 2006.257.06:20:54.59#ibcon#wrote, iclass 21, count 0 2006.257.06:20:54.59#ibcon#about to read 3, iclass 21, count 0 2006.257.06:20:54.62#ibcon#read 3, iclass 21, count 0 2006.257.06:20:54.62#ibcon#about to read 4, iclass 21, count 0 2006.257.06:20:54.62#ibcon#read 4, iclass 21, count 0 2006.257.06:20:54.62#ibcon#about to read 5, iclass 21, count 0 2006.257.06:20:54.62#ibcon#read 5, iclass 21, count 0 2006.257.06:20:54.62#ibcon#about to read 6, iclass 21, count 0 2006.257.06:20:54.62#ibcon#read 6, iclass 21, count 0 2006.257.06:20:54.62#ibcon#end of sib2, iclass 21, count 0 2006.257.06:20:54.62#ibcon#*after write, iclass 21, count 0 2006.257.06:20:54.62#ibcon#*before return 0, iclass 21, count 0 2006.257.06:20:54.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:54.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:54.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:20:54.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:20:54.62$vck44/valo=8,884.99 2006.257.06:20:54.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.06:20:54.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.06:20:54.62#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:54.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:54.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:54.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:54.62#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:20:54.62#ibcon#first serial, iclass 23, count 0 2006.257.06:20:54.62#ibcon#enter sib2, iclass 23, count 0 2006.257.06:20:54.62#ibcon#flushed, iclass 23, count 0 2006.257.06:20:54.62#ibcon#about to write, iclass 23, count 0 2006.257.06:20:54.62#ibcon#wrote, iclass 23, count 0 2006.257.06:20:54.62#ibcon#about to read 3, iclass 23, count 0 2006.257.06:20:54.64#ibcon#read 3, iclass 23, count 0 2006.257.06:20:54.64#ibcon#about to read 4, iclass 23, count 0 2006.257.06:20:54.64#ibcon#read 4, iclass 23, count 0 2006.257.06:20:54.64#ibcon#about to read 5, iclass 23, count 0 2006.257.06:20:54.64#ibcon#read 5, iclass 23, count 0 2006.257.06:20:54.64#ibcon#about to read 6, iclass 23, count 0 2006.257.06:20:54.64#ibcon#read 6, iclass 23, count 0 2006.257.06:20:54.64#ibcon#end of sib2, iclass 23, count 0 2006.257.06:20:54.64#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:20:54.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:20:54.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:20:54.64#ibcon#*before write, iclass 23, count 0 2006.257.06:20:54.64#ibcon#enter sib2, iclass 23, count 0 2006.257.06:20:54.64#ibcon#flushed, iclass 23, count 0 2006.257.06:20:54.64#ibcon#about to write, iclass 23, count 0 2006.257.06:20:54.64#ibcon#wrote, iclass 23, count 0 2006.257.06:20:54.64#ibcon#about to read 3, iclass 23, count 0 2006.257.06:20:54.68#ibcon#read 3, iclass 23, count 0 2006.257.06:20:54.68#ibcon#about to read 4, iclass 23, count 0 2006.257.06:20:54.68#ibcon#read 4, iclass 23, count 0 2006.257.06:20:54.68#ibcon#about to read 5, iclass 23, count 0 2006.257.06:20:54.68#ibcon#read 5, iclass 23, count 0 2006.257.06:20:54.68#ibcon#about to read 6, iclass 23, count 0 2006.257.06:20:54.68#ibcon#read 6, iclass 23, count 0 2006.257.06:20:54.68#ibcon#end of sib2, iclass 23, count 0 2006.257.06:20:54.68#ibcon#*after write, iclass 23, count 0 2006.257.06:20:54.68#ibcon#*before return 0, iclass 23, count 0 2006.257.06:20:54.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:54.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:54.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:20:54.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:20:54.68$vck44/va=8,4 2006.257.06:20:54.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.06:20:54.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.06:20:54.68#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:54.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:20:54.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:20:54.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:20:54.74#ibcon#enter wrdev, iclass 25, count 2 2006.257.06:20:54.74#ibcon#first serial, iclass 25, count 2 2006.257.06:20:54.74#ibcon#enter sib2, iclass 25, count 2 2006.257.06:20:54.74#ibcon#flushed, iclass 25, count 2 2006.257.06:20:54.74#ibcon#about to write, iclass 25, count 2 2006.257.06:20:54.74#ibcon#wrote, iclass 25, count 2 2006.257.06:20:54.74#ibcon#about to read 3, iclass 25, count 2 2006.257.06:20:54.76#ibcon#read 3, iclass 25, count 2 2006.257.06:20:54.76#ibcon#about to read 4, iclass 25, count 2 2006.257.06:20:54.76#ibcon#read 4, iclass 25, count 2 2006.257.06:20:54.76#ibcon#about to read 5, iclass 25, count 2 2006.257.06:20:54.76#ibcon#read 5, iclass 25, count 2 2006.257.06:20:54.76#ibcon#about to read 6, iclass 25, count 2 2006.257.06:20:54.76#ibcon#read 6, iclass 25, count 2 2006.257.06:20:54.76#ibcon#end of sib2, iclass 25, count 2 2006.257.06:20:54.76#ibcon#*mode == 0, iclass 25, count 2 2006.257.06:20:54.76#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.06:20:54.76#ibcon#[25=AT08-04\r\n] 2006.257.06:20:54.76#ibcon#*before write, iclass 25, count 2 2006.257.06:20:54.76#ibcon#enter sib2, iclass 25, count 2 2006.257.06:20:54.76#ibcon#flushed, iclass 25, count 2 2006.257.06:20:54.76#ibcon#about to write, iclass 25, count 2 2006.257.06:20:54.76#ibcon#wrote, iclass 25, count 2 2006.257.06:20:54.76#ibcon#about to read 3, iclass 25, count 2 2006.257.06:20:54.79#ibcon#read 3, iclass 25, count 2 2006.257.06:20:54.79#ibcon#about to read 4, iclass 25, count 2 2006.257.06:20:54.79#ibcon#read 4, iclass 25, count 2 2006.257.06:20:54.79#ibcon#about to read 5, iclass 25, count 2 2006.257.06:20:54.79#ibcon#read 5, iclass 25, count 2 2006.257.06:20:54.79#ibcon#about to read 6, iclass 25, count 2 2006.257.06:20:54.79#ibcon#read 6, iclass 25, count 2 2006.257.06:20:54.79#ibcon#end of sib2, iclass 25, count 2 2006.257.06:20:54.79#ibcon#*after write, iclass 25, count 2 2006.257.06:20:54.79#ibcon#*before return 0, iclass 25, count 2 2006.257.06:20:54.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:20:54.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:20:54.79#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.06:20:54.79#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:54.79#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:20:54.91#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:20:54.91#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:20:54.91#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:20:54.91#ibcon#first serial, iclass 25, count 0 2006.257.06:20:54.91#ibcon#enter sib2, iclass 25, count 0 2006.257.06:20:54.91#ibcon#flushed, iclass 25, count 0 2006.257.06:20:54.91#ibcon#about to write, iclass 25, count 0 2006.257.06:20:54.91#ibcon#wrote, iclass 25, count 0 2006.257.06:20:54.91#ibcon#about to read 3, iclass 25, count 0 2006.257.06:20:54.93#ibcon#read 3, iclass 25, count 0 2006.257.06:20:54.93#ibcon#about to read 4, iclass 25, count 0 2006.257.06:20:54.93#ibcon#read 4, iclass 25, count 0 2006.257.06:20:54.93#ibcon#about to read 5, iclass 25, count 0 2006.257.06:20:54.93#ibcon#read 5, iclass 25, count 0 2006.257.06:20:54.93#ibcon#about to read 6, iclass 25, count 0 2006.257.06:20:54.93#ibcon#read 6, iclass 25, count 0 2006.257.06:20:54.93#ibcon#end of sib2, iclass 25, count 0 2006.257.06:20:54.93#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:20:54.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:20:54.93#ibcon#[25=USB\r\n] 2006.257.06:20:54.93#ibcon#*before write, iclass 25, count 0 2006.257.06:20:54.93#ibcon#enter sib2, iclass 25, count 0 2006.257.06:20:54.93#ibcon#flushed, iclass 25, count 0 2006.257.06:20:54.93#ibcon#about to write, iclass 25, count 0 2006.257.06:20:54.93#ibcon#wrote, iclass 25, count 0 2006.257.06:20:54.93#ibcon#about to read 3, iclass 25, count 0 2006.257.06:20:54.96#ibcon#read 3, iclass 25, count 0 2006.257.06:20:54.96#ibcon#about to read 4, iclass 25, count 0 2006.257.06:20:54.96#ibcon#read 4, iclass 25, count 0 2006.257.06:20:54.96#ibcon#about to read 5, iclass 25, count 0 2006.257.06:20:54.96#ibcon#read 5, iclass 25, count 0 2006.257.06:20:54.96#ibcon#about to read 6, iclass 25, count 0 2006.257.06:20:54.96#ibcon#read 6, iclass 25, count 0 2006.257.06:20:54.96#ibcon#end of sib2, iclass 25, count 0 2006.257.06:20:54.96#ibcon#*after write, iclass 25, count 0 2006.257.06:20:54.96#ibcon#*before return 0, iclass 25, count 0 2006.257.06:20:54.96#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:20:54.96#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:20:54.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:20:54.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:20:54.96$vck44/vblo=1,629.99 2006.257.06:20:54.96#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.06:20:54.96#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.06:20:54.96#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:54.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:54.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:54.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:54.96#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:20:54.96#ibcon#first serial, iclass 27, count 0 2006.257.06:20:54.96#ibcon#enter sib2, iclass 27, count 0 2006.257.06:20:54.96#ibcon#flushed, iclass 27, count 0 2006.257.06:20:54.96#ibcon#about to write, iclass 27, count 0 2006.257.06:20:54.96#ibcon#wrote, iclass 27, count 0 2006.257.06:20:54.96#ibcon#about to read 3, iclass 27, count 0 2006.257.06:20:54.98#ibcon#read 3, iclass 27, count 0 2006.257.06:20:54.98#ibcon#about to read 4, iclass 27, count 0 2006.257.06:20:54.98#ibcon#read 4, iclass 27, count 0 2006.257.06:20:54.98#ibcon#about to read 5, iclass 27, count 0 2006.257.06:20:54.98#ibcon#read 5, iclass 27, count 0 2006.257.06:20:54.98#ibcon#about to read 6, iclass 27, count 0 2006.257.06:20:54.98#ibcon#read 6, iclass 27, count 0 2006.257.06:20:54.98#ibcon#end of sib2, iclass 27, count 0 2006.257.06:20:54.98#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:20:54.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:20:54.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:20:54.98#ibcon#*before write, iclass 27, count 0 2006.257.06:20:54.98#ibcon#enter sib2, iclass 27, count 0 2006.257.06:20:54.98#ibcon#flushed, iclass 27, count 0 2006.257.06:20:54.98#ibcon#about to write, iclass 27, count 0 2006.257.06:20:54.98#ibcon#wrote, iclass 27, count 0 2006.257.06:20:54.98#ibcon#about to read 3, iclass 27, count 0 2006.257.06:20:55.02#ibcon#read 3, iclass 27, count 0 2006.257.06:20:55.02#ibcon#about to read 4, iclass 27, count 0 2006.257.06:20:55.02#ibcon#read 4, iclass 27, count 0 2006.257.06:20:55.02#ibcon#about to read 5, iclass 27, count 0 2006.257.06:20:55.02#ibcon#read 5, iclass 27, count 0 2006.257.06:20:55.02#ibcon#about to read 6, iclass 27, count 0 2006.257.06:20:55.02#ibcon#read 6, iclass 27, count 0 2006.257.06:20:55.02#ibcon#end of sib2, iclass 27, count 0 2006.257.06:20:55.02#ibcon#*after write, iclass 27, count 0 2006.257.06:20:55.02#ibcon#*before return 0, iclass 27, count 0 2006.257.06:20:55.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:55.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:20:55.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:20:55.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:20:55.02$vck44/vb=1,4 2006.257.06:20:55.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.06:20:55.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.06:20:55.02#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:55.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:55.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:55.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:55.02#ibcon#enter wrdev, iclass 29, count 2 2006.257.06:20:55.02#ibcon#first serial, iclass 29, count 2 2006.257.06:20:55.02#ibcon#enter sib2, iclass 29, count 2 2006.257.06:20:55.02#ibcon#flushed, iclass 29, count 2 2006.257.06:20:55.02#ibcon#about to write, iclass 29, count 2 2006.257.06:20:55.02#ibcon#wrote, iclass 29, count 2 2006.257.06:20:55.02#ibcon#about to read 3, iclass 29, count 2 2006.257.06:20:55.04#ibcon#read 3, iclass 29, count 2 2006.257.06:20:55.04#ibcon#about to read 4, iclass 29, count 2 2006.257.06:20:55.04#ibcon#read 4, iclass 29, count 2 2006.257.06:20:55.04#ibcon#about to read 5, iclass 29, count 2 2006.257.06:20:55.04#ibcon#read 5, iclass 29, count 2 2006.257.06:20:55.04#ibcon#about to read 6, iclass 29, count 2 2006.257.06:20:55.04#ibcon#read 6, iclass 29, count 2 2006.257.06:20:55.04#ibcon#end of sib2, iclass 29, count 2 2006.257.06:20:55.04#ibcon#*mode == 0, iclass 29, count 2 2006.257.06:20:55.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.06:20:55.04#ibcon#[27=AT01-04\r\n] 2006.257.06:20:55.04#ibcon#*before write, iclass 29, count 2 2006.257.06:20:55.04#ibcon#enter sib2, iclass 29, count 2 2006.257.06:20:55.04#ibcon#flushed, iclass 29, count 2 2006.257.06:20:55.04#ibcon#about to write, iclass 29, count 2 2006.257.06:20:55.04#ibcon#wrote, iclass 29, count 2 2006.257.06:20:55.04#ibcon#about to read 3, iclass 29, count 2 2006.257.06:20:55.07#ibcon#read 3, iclass 29, count 2 2006.257.06:20:55.07#ibcon#about to read 4, iclass 29, count 2 2006.257.06:20:55.07#ibcon#read 4, iclass 29, count 2 2006.257.06:20:55.07#ibcon#about to read 5, iclass 29, count 2 2006.257.06:20:55.07#ibcon#read 5, iclass 29, count 2 2006.257.06:20:55.07#ibcon#about to read 6, iclass 29, count 2 2006.257.06:20:55.07#ibcon#read 6, iclass 29, count 2 2006.257.06:20:55.07#ibcon#end of sib2, iclass 29, count 2 2006.257.06:20:55.07#ibcon#*after write, iclass 29, count 2 2006.257.06:20:55.07#ibcon#*before return 0, iclass 29, count 2 2006.257.06:20:55.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:55.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:20:55.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.06:20:55.07#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:55.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:55.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:55.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:55.19#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:20:55.19#ibcon#first serial, iclass 29, count 0 2006.257.06:20:55.19#ibcon#enter sib2, iclass 29, count 0 2006.257.06:20:55.19#ibcon#flushed, iclass 29, count 0 2006.257.06:20:55.19#ibcon#about to write, iclass 29, count 0 2006.257.06:20:55.19#ibcon#wrote, iclass 29, count 0 2006.257.06:20:55.19#ibcon#about to read 3, iclass 29, count 0 2006.257.06:20:55.21#ibcon#read 3, iclass 29, count 0 2006.257.06:20:55.21#ibcon#about to read 4, iclass 29, count 0 2006.257.06:20:55.21#ibcon#read 4, iclass 29, count 0 2006.257.06:20:55.21#ibcon#about to read 5, iclass 29, count 0 2006.257.06:20:55.21#ibcon#read 5, iclass 29, count 0 2006.257.06:20:55.21#ibcon#about to read 6, iclass 29, count 0 2006.257.06:20:55.21#ibcon#read 6, iclass 29, count 0 2006.257.06:20:55.21#ibcon#end of sib2, iclass 29, count 0 2006.257.06:20:55.21#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:20:55.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:20:55.21#ibcon#[27=USB\r\n] 2006.257.06:20:55.21#ibcon#*before write, iclass 29, count 0 2006.257.06:20:55.21#ibcon#enter sib2, iclass 29, count 0 2006.257.06:20:55.21#ibcon#flushed, iclass 29, count 0 2006.257.06:20:55.21#ibcon#about to write, iclass 29, count 0 2006.257.06:20:55.21#ibcon#wrote, iclass 29, count 0 2006.257.06:20:55.21#ibcon#about to read 3, iclass 29, count 0 2006.257.06:20:55.24#ibcon#read 3, iclass 29, count 0 2006.257.06:20:55.24#ibcon#about to read 4, iclass 29, count 0 2006.257.06:20:55.24#ibcon#read 4, iclass 29, count 0 2006.257.06:20:55.24#ibcon#about to read 5, iclass 29, count 0 2006.257.06:20:55.24#ibcon#read 5, iclass 29, count 0 2006.257.06:20:55.24#ibcon#about to read 6, iclass 29, count 0 2006.257.06:20:55.24#ibcon#read 6, iclass 29, count 0 2006.257.06:20:55.24#ibcon#end of sib2, iclass 29, count 0 2006.257.06:20:55.24#ibcon#*after write, iclass 29, count 0 2006.257.06:20:55.24#ibcon#*before return 0, iclass 29, count 0 2006.257.06:20:55.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:55.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:20:55.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:20:55.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:20:55.24$vck44/vblo=2,634.99 2006.257.06:20:55.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.06:20:55.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.06:20:55.24#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:55.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:55.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:55.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:55.24#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:20:55.24#ibcon#first serial, iclass 31, count 0 2006.257.06:20:55.24#ibcon#enter sib2, iclass 31, count 0 2006.257.06:20:55.24#ibcon#flushed, iclass 31, count 0 2006.257.06:20:55.24#ibcon#about to write, iclass 31, count 0 2006.257.06:20:55.24#ibcon#wrote, iclass 31, count 0 2006.257.06:20:55.24#ibcon#about to read 3, iclass 31, count 0 2006.257.06:20:55.26#ibcon#read 3, iclass 31, count 0 2006.257.06:20:55.26#ibcon#about to read 4, iclass 31, count 0 2006.257.06:20:55.26#ibcon#read 4, iclass 31, count 0 2006.257.06:20:55.26#ibcon#about to read 5, iclass 31, count 0 2006.257.06:20:55.26#ibcon#read 5, iclass 31, count 0 2006.257.06:20:55.26#ibcon#about to read 6, iclass 31, count 0 2006.257.06:20:55.26#ibcon#read 6, iclass 31, count 0 2006.257.06:20:55.26#ibcon#end of sib2, iclass 31, count 0 2006.257.06:20:55.26#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:20:55.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:20:55.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:20:55.26#ibcon#*before write, iclass 31, count 0 2006.257.06:20:55.26#ibcon#enter sib2, iclass 31, count 0 2006.257.06:20:55.26#ibcon#flushed, iclass 31, count 0 2006.257.06:20:55.26#ibcon#about to write, iclass 31, count 0 2006.257.06:20:55.26#ibcon#wrote, iclass 31, count 0 2006.257.06:20:55.26#ibcon#about to read 3, iclass 31, count 0 2006.257.06:20:55.30#ibcon#read 3, iclass 31, count 0 2006.257.06:20:55.30#ibcon#about to read 4, iclass 31, count 0 2006.257.06:20:55.30#ibcon#read 4, iclass 31, count 0 2006.257.06:20:55.30#ibcon#about to read 5, iclass 31, count 0 2006.257.06:20:55.30#ibcon#read 5, iclass 31, count 0 2006.257.06:20:55.30#ibcon#about to read 6, iclass 31, count 0 2006.257.06:20:55.30#ibcon#read 6, iclass 31, count 0 2006.257.06:20:55.30#ibcon#end of sib2, iclass 31, count 0 2006.257.06:20:55.30#ibcon#*after write, iclass 31, count 0 2006.257.06:20:55.30#ibcon#*before return 0, iclass 31, count 0 2006.257.06:20:55.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:55.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:20:55.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:20:55.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:20:55.30$vck44/vb=2,5 2006.257.06:20:55.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.06:20:55.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.06:20:55.30#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:55.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:55.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:55.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:55.36#ibcon#enter wrdev, iclass 33, count 2 2006.257.06:20:55.36#ibcon#first serial, iclass 33, count 2 2006.257.06:20:55.36#ibcon#enter sib2, iclass 33, count 2 2006.257.06:20:55.36#ibcon#flushed, iclass 33, count 2 2006.257.06:20:55.36#ibcon#about to write, iclass 33, count 2 2006.257.06:20:55.36#ibcon#wrote, iclass 33, count 2 2006.257.06:20:55.36#ibcon#about to read 3, iclass 33, count 2 2006.257.06:20:55.38#ibcon#read 3, iclass 33, count 2 2006.257.06:20:55.38#ibcon#about to read 4, iclass 33, count 2 2006.257.06:20:55.38#ibcon#read 4, iclass 33, count 2 2006.257.06:20:55.38#ibcon#about to read 5, iclass 33, count 2 2006.257.06:20:55.38#ibcon#read 5, iclass 33, count 2 2006.257.06:20:55.38#ibcon#about to read 6, iclass 33, count 2 2006.257.06:20:55.38#ibcon#read 6, iclass 33, count 2 2006.257.06:20:55.38#ibcon#end of sib2, iclass 33, count 2 2006.257.06:20:55.38#ibcon#*mode == 0, iclass 33, count 2 2006.257.06:20:55.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.06:20:55.38#ibcon#[27=AT02-05\r\n] 2006.257.06:20:55.38#ibcon#*before write, iclass 33, count 2 2006.257.06:20:55.38#ibcon#enter sib2, iclass 33, count 2 2006.257.06:20:55.38#ibcon#flushed, iclass 33, count 2 2006.257.06:20:55.38#ibcon#about to write, iclass 33, count 2 2006.257.06:20:55.38#ibcon#wrote, iclass 33, count 2 2006.257.06:20:55.38#ibcon#about to read 3, iclass 33, count 2 2006.257.06:20:55.41#ibcon#read 3, iclass 33, count 2 2006.257.06:20:55.41#ibcon#about to read 4, iclass 33, count 2 2006.257.06:20:55.41#ibcon#read 4, iclass 33, count 2 2006.257.06:20:55.41#ibcon#about to read 5, iclass 33, count 2 2006.257.06:20:55.41#ibcon#read 5, iclass 33, count 2 2006.257.06:20:55.41#ibcon#about to read 6, iclass 33, count 2 2006.257.06:20:55.41#ibcon#read 6, iclass 33, count 2 2006.257.06:20:55.41#ibcon#end of sib2, iclass 33, count 2 2006.257.06:20:55.41#ibcon#*after write, iclass 33, count 2 2006.257.06:20:55.41#ibcon#*before return 0, iclass 33, count 2 2006.257.06:20:55.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:55.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:20:55.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.06:20:55.41#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:55.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:55.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:55.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:55.53#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:20:55.53#ibcon#first serial, iclass 33, count 0 2006.257.06:20:55.53#ibcon#enter sib2, iclass 33, count 0 2006.257.06:20:55.53#ibcon#flushed, iclass 33, count 0 2006.257.06:20:55.53#ibcon#about to write, iclass 33, count 0 2006.257.06:20:55.53#ibcon#wrote, iclass 33, count 0 2006.257.06:20:55.53#ibcon#about to read 3, iclass 33, count 0 2006.257.06:20:55.55#ibcon#read 3, iclass 33, count 0 2006.257.06:20:55.55#ibcon#about to read 4, iclass 33, count 0 2006.257.06:20:55.55#ibcon#read 4, iclass 33, count 0 2006.257.06:20:55.55#ibcon#about to read 5, iclass 33, count 0 2006.257.06:20:55.55#ibcon#read 5, iclass 33, count 0 2006.257.06:20:55.55#ibcon#about to read 6, iclass 33, count 0 2006.257.06:20:55.55#ibcon#read 6, iclass 33, count 0 2006.257.06:20:55.55#ibcon#end of sib2, iclass 33, count 0 2006.257.06:20:55.55#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:20:55.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:20:55.55#ibcon#[27=USB\r\n] 2006.257.06:20:55.55#ibcon#*before write, iclass 33, count 0 2006.257.06:20:55.55#ibcon#enter sib2, iclass 33, count 0 2006.257.06:20:55.55#ibcon#flushed, iclass 33, count 0 2006.257.06:20:55.55#ibcon#about to write, iclass 33, count 0 2006.257.06:20:55.55#ibcon#wrote, iclass 33, count 0 2006.257.06:20:55.55#ibcon#about to read 3, iclass 33, count 0 2006.257.06:20:55.58#ibcon#read 3, iclass 33, count 0 2006.257.06:20:55.58#ibcon#about to read 4, iclass 33, count 0 2006.257.06:20:55.58#ibcon#read 4, iclass 33, count 0 2006.257.06:20:55.58#ibcon#about to read 5, iclass 33, count 0 2006.257.06:20:55.58#ibcon#read 5, iclass 33, count 0 2006.257.06:20:55.58#ibcon#about to read 6, iclass 33, count 0 2006.257.06:20:55.58#ibcon#read 6, iclass 33, count 0 2006.257.06:20:55.58#ibcon#end of sib2, iclass 33, count 0 2006.257.06:20:55.58#ibcon#*after write, iclass 33, count 0 2006.257.06:20:55.58#ibcon#*before return 0, iclass 33, count 0 2006.257.06:20:55.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:55.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:20:55.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:20:55.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:20:55.58$vck44/vblo=3,649.99 2006.257.06:20:55.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:20:55.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:20:55.58#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:55.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:55.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:55.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:55.58#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:20:55.58#ibcon#first serial, iclass 35, count 0 2006.257.06:20:55.58#ibcon#enter sib2, iclass 35, count 0 2006.257.06:20:55.58#ibcon#flushed, iclass 35, count 0 2006.257.06:20:55.58#ibcon#about to write, iclass 35, count 0 2006.257.06:20:55.58#ibcon#wrote, iclass 35, count 0 2006.257.06:20:55.58#ibcon#about to read 3, iclass 35, count 0 2006.257.06:20:55.60#ibcon#read 3, iclass 35, count 0 2006.257.06:20:55.60#ibcon#about to read 4, iclass 35, count 0 2006.257.06:20:55.60#ibcon#read 4, iclass 35, count 0 2006.257.06:20:55.60#ibcon#about to read 5, iclass 35, count 0 2006.257.06:20:55.60#ibcon#read 5, iclass 35, count 0 2006.257.06:20:55.60#ibcon#about to read 6, iclass 35, count 0 2006.257.06:20:55.60#ibcon#read 6, iclass 35, count 0 2006.257.06:20:55.60#ibcon#end of sib2, iclass 35, count 0 2006.257.06:20:55.60#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:20:55.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:20:55.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:20:55.60#ibcon#*before write, iclass 35, count 0 2006.257.06:20:55.60#ibcon#enter sib2, iclass 35, count 0 2006.257.06:20:55.60#ibcon#flushed, iclass 35, count 0 2006.257.06:20:55.60#ibcon#about to write, iclass 35, count 0 2006.257.06:20:55.60#ibcon#wrote, iclass 35, count 0 2006.257.06:20:55.60#ibcon#about to read 3, iclass 35, count 0 2006.257.06:20:55.64#ibcon#read 3, iclass 35, count 0 2006.257.06:20:55.64#ibcon#about to read 4, iclass 35, count 0 2006.257.06:20:55.64#ibcon#read 4, iclass 35, count 0 2006.257.06:20:55.64#ibcon#about to read 5, iclass 35, count 0 2006.257.06:20:55.64#ibcon#read 5, iclass 35, count 0 2006.257.06:20:55.64#ibcon#about to read 6, iclass 35, count 0 2006.257.06:20:55.64#ibcon#read 6, iclass 35, count 0 2006.257.06:20:55.64#ibcon#end of sib2, iclass 35, count 0 2006.257.06:20:55.64#ibcon#*after write, iclass 35, count 0 2006.257.06:20:55.64#ibcon#*before return 0, iclass 35, count 0 2006.257.06:20:55.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:55.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:20:55.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:20:55.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:20:55.64$vck44/vb=3,4 2006.257.06:20:55.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.06:20:55.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.06:20:55.64#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:55.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:20:55.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:20:55.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:20:55.70#ibcon#enter wrdev, iclass 37, count 2 2006.257.06:20:55.70#ibcon#first serial, iclass 37, count 2 2006.257.06:20:55.70#ibcon#enter sib2, iclass 37, count 2 2006.257.06:20:55.70#ibcon#flushed, iclass 37, count 2 2006.257.06:20:55.70#ibcon#about to write, iclass 37, count 2 2006.257.06:20:55.70#ibcon#wrote, iclass 37, count 2 2006.257.06:20:55.70#ibcon#about to read 3, iclass 37, count 2 2006.257.06:20:55.72#ibcon#read 3, iclass 37, count 2 2006.257.06:20:55.72#ibcon#about to read 4, iclass 37, count 2 2006.257.06:20:55.72#ibcon#read 4, iclass 37, count 2 2006.257.06:20:55.72#ibcon#about to read 5, iclass 37, count 2 2006.257.06:20:55.72#ibcon#read 5, iclass 37, count 2 2006.257.06:20:55.72#ibcon#about to read 6, iclass 37, count 2 2006.257.06:20:55.72#ibcon#read 6, iclass 37, count 2 2006.257.06:20:55.72#ibcon#end of sib2, iclass 37, count 2 2006.257.06:20:55.72#ibcon#*mode == 0, iclass 37, count 2 2006.257.06:20:55.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.06:20:55.72#ibcon#[27=AT03-04\r\n] 2006.257.06:20:55.72#ibcon#*before write, iclass 37, count 2 2006.257.06:20:55.72#ibcon#enter sib2, iclass 37, count 2 2006.257.06:20:55.72#ibcon#flushed, iclass 37, count 2 2006.257.06:20:55.72#ibcon#about to write, iclass 37, count 2 2006.257.06:20:55.72#ibcon#wrote, iclass 37, count 2 2006.257.06:20:55.72#ibcon#about to read 3, iclass 37, count 2 2006.257.06:20:55.75#ibcon#read 3, iclass 37, count 2 2006.257.06:20:55.75#ibcon#about to read 4, iclass 37, count 2 2006.257.06:20:55.75#ibcon#read 4, iclass 37, count 2 2006.257.06:20:55.75#ibcon#about to read 5, iclass 37, count 2 2006.257.06:20:55.75#ibcon#read 5, iclass 37, count 2 2006.257.06:20:55.75#ibcon#about to read 6, iclass 37, count 2 2006.257.06:20:55.75#ibcon#read 6, iclass 37, count 2 2006.257.06:20:55.75#ibcon#end of sib2, iclass 37, count 2 2006.257.06:20:55.75#ibcon#*after write, iclass 37, count 2 2006.257.06:20:55.75#ibcon#*before return 0, iclass 37, count 2 2006.257.06:20:55.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:20:55.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:20:55.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.06:20:55.75#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:55.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:20:55.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:20:55.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:20:55.87#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:20:55.87#ibcon#first serial, iclass 37, count 0 2006.257.06:20:55.87#ibcon#enter sib2, iclass 37, count 0 2006.257.06:20:55.87#ibcon#flushed, iclass 37, count 0 2006.257.06:20:55.87#ibcon#about to write, iclass 37, count 0 2006.257.06:20:55.87#ibcon#wrote, iclass 37, count 0 2006.257.06:20:55.87#ibcon#about to read 3, iclass 37, count 0 2006.257.06:20:55.89#ibcon#read 3, iclass 37, count 0 2006.257.06:20:55.89#ibcon#about to read 4, iclass 37, count 0 2006.257.06:20:55.89#ibcon#read 4, iclass 37, count 0 2006.257.06:20:55.89#ibcon#about to read 5, iclass 37, count 0 2006.257.06:20:55.89#ibcon#read 5, iclass 37, count 0 2006.257.06:20:55.89#ibcon#about to read 6, iclass 37, count 0 2006.257.06:20:55.89#ibcon#read 6, iclass 37, count 0 2006.257.06:20:55.89#ibcon#end of sib2, iclass 37, count 0 2006.257.06:20:55.89#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:20:55.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:20:55.89#ibcon#[27=USB\r\n] 2006.257.06:20:55.89#ibcon#*before write, iclass 37, count 0 2006.257.06:20:55.89#ibcon#enter sib2, iclass 37, count 0 2006.257.06:20:55.89#ibcon#flushed, iclass 37, count 0 2006.257.06:20:55.89#ibcon#about to write, iclass 37, count 0 2006.257.06:20:55.89#ibcon#wrote, iclass 37, count 0 2006.257.06:20:55.89#ibcon#about to read 3, iclass 37, count 0 2006.257.06:20:55.92#ibcon#read 3, iclass 37, count 0 2006.257.06:20:55.92#ibcon#about to read 4, iclass 37, count 0 2006.257.06:20:55.92#ibcon#read 4, iclass 37, count 0 2006.257.06:20:55.92#ibcon#about to read 5, iclass 37, count 0 2006.257.06:20:55.92#ibcon#read 5, iclass 37, count 0 2006.257.06:20:55.92#ibcon#about to read 6, iclass 37, count 0 2006.257.06:20:55.92#ibcon#read 6, iclass 37, count 0 2006.257.06:20:55.92#ibcon#end of sib2, iclass 37, count 0 2006.257.06:20:55.92#ibcon#*after write, iclass 37, count 0 2006.257.06:20:55.92#ibcon#*before return 0, iclass 37, count 0 2006.257.06:20:55.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:20:55.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:20:55.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:20:55.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:20:55.92$vck44/vblo=4,679.99 2006.257.06:20:55.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.06:20:55.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.06:20:55.92#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:55.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:20:55.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:20:55.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:20:55.92#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:20:55.92#ibcon#first serial, iclass 39, count 0 2006.257.06:20:55.92#ibcon#enter sib2, iclass 39, count 0 2006.257.06:20:55.92#ibcon#flushed, iclass 39, count 0 2006.257.06:20:55.92#ibcon#about to write, iclass 39, count 0 2006.257.06:20:55.92#ibcon#wrote, iclass 39, count 0 2006.257.06:20:55.92#ibcon#about to read 3, iclass 39, count 0 2006.257.06:20:55.94#ibcon#read 3, iclass 39, count 0 2006.257.06:20:55.94#ibcon#about to read 4, iclass 39, count 0 2006.257.06:20:55.94#ibcon#read 4, iclass 39, count 0 2006.257.06:20:55.94#ibcon#about to read 5, iclass 39, count 0 2006.257.06:20:55.94#ibcon#read 5, iclass 39, count 0 2006.257.06:20:55.94#ibcon#about to read 6, iclass 39, count 0 2006.257.06:20:55.94#ibcon#read 6, iclass 39, count 0 2006.257.06:20:55.94#ibcon#end of sib2, iclass 39, count 0 2006.257.06:20:55.94#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:20:55.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:20:55.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:20:55.94#ibcon#*before write, iclass 39, count 0 2006.257.06:20:55.94#ibcon#enter sib2, iclass 39, count 0 2006.257.06:20:55.94#ibcon#flushed, iclass 39, count 0 2006.257.06:20:55.94#ibcon#about to write, iclass 39, count 0 2006.257.06:20:55.94#ibcon#wrote, iclass 39, count 0 2006.257.06:20:55.94#ibcon#about to read 3, iclass 39, count 0 2006.257.06:20:55.98#ibcon#read 3, iclass 39, count 0 2006.257.06:20:55.98#ibcon#about to read 4, iclass 39, count 0 2006.257.06:20:55.98#ibcon#read 4, iclass 39, count 0 2006.257.06:20:55.98#ibcon#about to read 5, iclass 39, count 0 2006.257.06:20:55.98#ibcon#read 5, iclass 39, count 0 2006.257.06:20:55.98#ibcon#about to read 6, iclass 39, count 0 2006.257.06:20:55.98#ibcon#read 6, iclass 39, count 0 2006.257.06:20:55.98#ibcon#end of sib2, iclass 39, count 0 2006.257.06:20:55.98#ibcon#*after write, iclass 39, count 0 2006.257.06:20:55.98#ibcon#*before return 0, iclass 39, count 0 2006.257.06:20:55.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:20:55.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:20:55.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:20:55.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:20:55.98$vck44/vb=4,5 2006.257.06:20:55.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.06:20:55.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.06:20:55.98#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:55.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:20:56.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:20:56.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:20:56.04#ibcon#enter wrdev, iclass 3, count 2 2006.257.06:20:56.04#ibcon#first serial, iclass 3, count 2 2006.257.06:20:56.04#ibcon#enter sib2, iclass 3, count 2 2006.257.06:20:56.04#ibcon#flushed, iclass 3, count 2 2006.257.06:20:56.04#ibcon#about to write, iclass 3, count 2 2006.257.06:20:56.04#ibcon#wrote, iclass 3, count 2 2006.257.06:20:56.04#ibcon#about to read 3, iclass 3, count 2 2006.257.06:20:56.06#ibcon#read 3, iclass 3, count 2 2006.257.06:20:56.06#ibcon#about to read 4, iclass 3, count 2 2006.257.06:20:56.06#ibcon#read 4, iclass 3, count 2 2006.257.06:20:56.06#ibcon#about to read 5, iclass 3, count 2 2006.257.06:20:56.06#ibcon#read 5, iclass 3, count 2 2006.257.06:20:56.06#ibcon#about to read 6, iclass 3, count 2 2006.257.06:20:56.06#ibcon#read 6, iclass 3, count 2 2006.257.06:20:56.06#ibcon#end of sib2, iclass 3, count 2 2006.257.06:20:56.06#ibcon#*mode == 0, iclass 3, count 2 2006.257.06:20:56.06#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.06:20:56.06#ibcon#[27=AT04-05\r\n] 2006.257.06:20:56.06#ibcon#*before write, iclass 3, count 2 2006.257.06:20:56.06#ibcon#enter sib2, iclass 3, count 2 2006.257.06:20:56.06#ibcon#flushed, iclass 3, count 2 2006.257.06:20:56.06#ibcon#about to write, iclass 3, count 2 2006.257.06:20:56.06#ibcon#wrote, iclass 3, count 2 2006.257.06:20:56.06#ibcon#about to read 3, iclass 3, count 2 2006.257.06:20:56.09#ibcon#read 3, iclass 3, count 2 2006.257.06:20:56.09#ibcon#about to read 4, iclass 3, count 2 2006.257.06:20:56.09#ibcon#read 4, iclass 3, count 2 2006.257.06:20:56.09#ibcon#about to read 5, iclass 3, count 2 2006.257.06:20:56.09#ibcon#read 5, iclass 3, count 2 2006.257.06:20:56.09#ibcon#about to read 6, iclass 3, count 2 2006.257.06:20:56.09#ibcon#read 6, iclass 3, count 2 2006.257.06:20:56.09#ibcon#end of sib2, iclass 3, count 2 2006.257.06:20:56.09#ibcon#*after write, iclass 3, count 2 2006.257.06:20:56.09#ibcon#*before return 0, iclass 3, count 2 2006.257.06:20:56.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:20:56.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:20:56.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.06:20:56.09#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:56.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:20:56.21#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:20:56.21#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:20:56.21#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:20:56.21#ibcon#first serial, iclass 3, count 0 2006.257.06:20:56.21#ibcon#enter sib2, iclass 3, count 0 2006.257.06:20:56.21#ibcon#flushed, iclass 3, count 0 2006.257.06:20:56.21#ibcon#about to write, iclass 3, count 0 2006.257.06:20:56.21#ibcon#wrote, iclass 3, count 0 2006.257.06:20:56.21#ibcon#about to read 3, iclass 3, count 0 2006.257.06:20:56.23#ibcon#read 3, iclass 3, count 0 2006.257.06:20:56.23#ibcon#about to read 4, iclass 3, count 0 2006.257.06:20:56.23#ibcon#read 4, iclass 3, count 0 2006.257.06:20:56.23#ibcon#about to read 5, iclass 3, count 0 2006.257.06:20:56.23#ibcon#read 5, iclass 3, count 0 2006.257.06:20:56.23#ibcon#about to read 6, iclass 3, count 0 2006.257.06:20:56.23#ibcon#read 6, iclass 3, count 0 2006.257.06:20:56.23#ibcon#end of sib2, iclass 3, count 0 2006.257.06:20:56.23#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:20:56.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:20:56.23#ibcon#[27=USB\r\n] 2006.257.06:20:56.23#ibcon#*before write, iclass 3, count 0 2006.257.06:20:56.23#ibcon#enter sib2, iclass 3, count 0 2006.257.06:20:56.23#ibcon#flushed, iclass 3, count 0 2006.257.06:20:56.23#ibcon#about to write, iclass 3, count 0 2006.257.06:20:56.23#ibcon#wrote, iclass 3, count 0 2006.257.06:20:56.23#ibcon#about to read 3, iclass 3, count 0 2006.257.06:20:56.26#ibcon#read 3, iclass 3, count 0 2006.257.06:20:56.26#ibcon#about to read 4, iclass 3, count 0 2006.257.06:20:56.26#ibcon#read 4, iclass 3, count 0 2006.257.06:20:56.26#ibcon#about to read 5, iclass 3, count 0 2006.257.06:20:56.26#ibcon#read 5, iclass 3, count 0 2006.257.06:20:56.26#ibcon#about to read 6, iclass 3, count 0 2006.257.06:20:56.26#ibcon#read 6, iclass 3, count 0 2006.257.06:20:56.26#ibcon#end of sib2, iclass 3, count 0 2006.257.06:20:56.26#ibcon#*after write, iclass 3, count 0 2006.257.06:20:56.26#ibcon#*before return 0, iclass 3, count 0 2006.257.06:20:56.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:20:56.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:20:56.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:20:56.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:20:56.26$vck44/vblo=5,709.99 2006.257.06:20:56.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.06:20:56.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.06:20:56.26#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:56.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:56.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:56.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:56.26#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:20:56.26#ibcon#first serial, iclass 5, count 0 2006.257.06:20:56.26#ibcon#enter sib2, iclass 5, count 0 2006.257.06:20:56.26#ibcon#flushed, iclass 5, count 0 2006.257.06:20:56.26#ibcon#about to write, iclass 5, count 0 2006.257.06:20:56.26#ibcon#wrote, iclass 5, count 0 2006.257.06:20:56.26#ibcon#about to read 3, iclass 5, count 0 2006.257.06:20:56.28#ibcon#read 3, iclass 5, count 0 2006.257.06:20:56.28#ibcon#about to read 4, iclass 5, count 0 2006.257.06:20:56.28#ibcon#read 4, iclass 5, count 0 2006.257.06:20:56.28#ibcon#about to read 5, iclass 5, count 0 2006.257.06:20:56.28#ibcon#read 5, iclass 5, count 0 2006.257.06:20:56.28#ibcon#about to read 6, iclass 5, count 0 2006.257.06:20:56.28#ibcon#read 6, iclass 5, count 0 2006.257.06:20:56.28#ibcon#end of sib2, iclass 5, count 0 2006.257.06:20:56.28#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:20:56.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:20:56.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:20:56.28#ibcon#*before write, iclass 5, count 0 2006.257.06:20:56.28#ibcon#enter sib2, iclass 5, count 0 2006.257.06:20:56.28#ibcon#flushed, iclass 5, count 0 2006.257.06:20:56.28#ibcon#about to write, iclass 5, count 0 2006.257.06:20:56.28#ibcon#wrote, iclass 5, count 0 2006.257.06:20:56.28#ibcon#about to read 3, iclass 5, count 0 2006.257.06:20:56.32#ibcon#read 3, iclass 5, count 0 2006.257.06:20:56.32#ibcon#about to read 4, iclass 5, count 0 2006.257.06:20:56.32#ibcon#read 4, iclass 5, count 0 2006.257.06:20:56.32#ibcon#about to read 5, iclass 5, count 0 2006.257.06:20:56.32#ibcon#read 5, iclass 5, count 0 2006.257.06:20:56.32#ibcon#about to read 6, iclass 5, count 0 2006.257.06:20:56.32#ibcon#read 6, iclass 5, count 0 2006.257.06:20:56.32#ibcon#end of sib2, iclass 5, count 0 2006.257.06:20:56.32#ibcon#*after write, iclass 5, count 0 2006.257.06:20:56.32#ibcon#*before return 0, iclass 5, count 0 2006.257.06:20:56.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:56.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:20:56.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:20:56.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:20:56.32$vck44/vb=5,4 2006.257.06:20:56.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.06:20:56.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.06:20:56.32#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:56.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:56.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:56.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:56.38#ibcon#enter wrdev, iclass 7, count 2 2006.257.06:20:56.38#ibcon#first serial, iclass 7, count 2 2006.257.06:20:56.38#ibcon#enter sib2, iclass 7, count 2 2006.257.06:20:56.38#ibcon#flushed, iclass 7, count 2 2006.257.06:20:56.38#ibcon#about to write, iclass 7, count 2 2006.257.06:20:56.38#ibcon#wrote, iclass 7, count 2 2006.257.06:20:56.38#ibcon#about to read 3, iclass 7, count 2 2006.257.06:20:56.40#ibcon#read 3, iclass 7, count 2 2006.257.06:20:56.40#ibcon#about to read 4, iclass 7, count 2 2006.257.06:20:56.40#ibcon#read 4, iclass 7, count 2 2006.257.06:20:56.40#ibcon#about to read 5, iclass 7, count 2 2006.257.06:20:56.40#ibcon#read 5, iclass 7, count 2 2006.257.06:20:56.40#ibcon#about to read 6, iclass 7, count 2 2006.257.06:20:56.40#ibcon#read 6, iclass 7, count 2 2006.257.06:20:56.40#ibcon#end of sib2, iclass 7, count 2 2006.257.06:20:56.40#ibcon#*mode == 0, iclass 7, count 2 2006.257.06:20:56.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.06:20:56.40#ibcon#[27=AT05-04\r\n] 2006.257.06:20:56.40#ibcon#*before write, iclass 7, count 2 2006.257.06:20:56.40#ibcon#enter sib2, iclass 7, count 2 2006.257.06:20:56.40#ibcon#flushed, iclass 7, count 2 2006.257.06:20:56.40#ibcon#about to write, iclass 7, count 2 2006.257.06:20:56.40#ibcon#wrote, iclass 7, count 2 2006.257.06:20:56.40#ibcon#about to read 3, iclass 7, count 2 2006.257.06:20:56.43#ibcon#read 3, iclass 7, count 2 2006.257.06:20:56.43#ibcon#about to read 4, iclass 7, count 2 2006.257.06:20:56.43#ibcon#read 4, iclass 7, count 2 2006.257.06:20:56.43#ibcon#about to read 5, iclass 7, count 2 2006.257.06:20:56.43#ibcon#read 5, iclass 7, count 2 2006.257.06:20:56.43#ibcon#about to read 6, iclass 7, count 2 2006.257.06:20:56.43#ibcon#read 6, iclass 7, count 2 2006.257.06:20:56.43#ibcon#end of sib2, iclass 7, count 2 2006.257.06:20:56.43#ibcon#*after write, iclass 7, count 2 2006.257.06:20:56.43#ibcon#*before return 0, iclass 7, count 2 2006.257.06:20:56.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:56.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:20:56.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.06:20:56.43#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:56.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:56.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:56.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:56.55#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:20:56.55#ibcon#first serial, iclass 7, count 0 2006.257.06:20:56.55#ibcon#enter sib2, iclass 7, count 0 2006.257.06:20:56.55#ibcon#flushed, iclass 7, count 0 2006.257.06:20:56.55#ibcon#about to write, iclass 7, count 0 2006.257.06:20:56.55#ibcon#wrote, iclass 7, count 0 2006.257.06:20:56.55#ibcon#about to read 3, iclass 7, count 0 2006.257.06:20:56.57#ibcon#read 3, iclass 7, count 0 2006.257.06:20:56.57#ibcon#about to read 4, iclass 7, count 0 2006.257.06:20:56.57#ibcon#read 4, iclass 7, count 0 2006.257.06:20:56.57#ibcon#about to read 5, iclass 7, count 0 2006.257.06:20:56.57#ibcon#read 5, iclass 7, count 0 2006.257.06:20:56.57#ibcon#about to read 6, iclass 7, count 0 2006.257.06:20:56.57#ibcon#read 6, iclass 7, count 0 2006.257.06:20:56.57#ibcon#end of sib2, iclass 7, count 0 2006.257.06:20:56.57#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:20:56.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:20:56.57#ibcon#[27=USB\r\n] 2006.257.06:20:56.57#ibcon#*before write, iclass 7, count 0 2006.257.06:20:56.57#ibcon#enter sib2, iclass 7, count 0 2006.257.06:20:56.57#ibcon#flushed, iclass 7, count 0 2006.257.06:20:56.57#ibcon#about to write, iclass 7, count 0 2006.257.06:20:56.57#ibcon#wrote, iclass 7, count 0 2006.257.06:20:56.57#ibcon#about to read 3, iclass 7, count 0 2006.257.06:20:56.60#ibcon#read 3, iclass 7, count 0 2006.257.06:20:56.60#ibcon#about to read 4, iclass 7, count 0 2006.257.06:20:56.60#ibcon#read 4, iclass 7, count 0 2006.257.06:20:56.60#ibcon#about to read 5, iclass 7, count 0 2006.257.06:20:56.60#ibcon#read 5, iclass 7, count 0 2006.257.06:20:56.60#ibcon#about to read 6, iclass 7, count 0 2006.257.06:20:56.60#ibcon#read 6, iclass 7, count 0 2006.257.06:20:56.60#ibcon#end of sib2, iclass 7, count 0 2006.257.06:20:56.60#ibcon#*after write, iclass 7, count 0 2006.257.06:20:56.60#ibcon#*before return 0, iclass 7, count 0 2006.257.06:20:56.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:56.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:20:56.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:20:56.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:20:56.60$vck44/vblo=6,719.99 2006.257.06:20:56.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.06:20:56.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.06:20:56.60#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:56.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:56.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:56.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:56.60#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:20:56.60#ibcon#first serial, iclass 11, count 0 2006.257.06:20:56.60#ibcon#enter sib2, iclass 11, count 0 2006.257.06:20:56.60#ibcon#flushed, iclass 11, count 0 2006.257.06:20:56.60#ibcon#about to write, iclass 11, count 0 2006.257.06:20:56.60#ibcon#wrote, iclass 11, count 0 2006.257.06:20:56.60#ibcon#about to read 3, iclass 11, count 0 2006.257.06:20:56.62#ibcon#read 3, iclass 11, count 0 2006.257.06:20:56.62#ibcon#about to read 4, iclass 11, count 0 2006.257.06:20:56.62#ibcon#read 4, iclass 11, count 0 2006.257.06:20:56.62#ibcon#about to read 5, iclass 11, count 0 2006.257.06:20:56.62#ibcon#read 5, iclass 11, count 0 2006.257.06:20:56.62#ibcon#about to read 6, iclass 11, count 0 2006.257.06:20:56.62#ibcon#read 6, iclass 11, count 0 2006.257.06:20:56.62#ibcon#end of sib2, iclass 11, count 0 2006.257.06:20:56.62#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:20:56.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:20:56.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:20:56.62#ibcon#*before write, iclass 11, count 0 2006.257.06:20:56.62#ibcon#enter sib2, iclass 11, count 0 2006.257.06:20:56.62#ibcon#flushed, iclass 11, count 0 2006.257.06:20:56.62#ibcon#about to write, iclass 11, count 0 2006.257.06:20:56.62#ibcon#wrote, iclass 11, count 0 2006.257.06:20:56.62#ibcon#about to read 3, iclass 11, count 0 2006.257.06:20:56.66#ibcon#read 3, iclass 11, count 0 2006.257.06:20:56.66#ibcon#about to read 4, iclass 11, count 0 2006.257.06:20:56.66#ibcon#read 4, iclass 11, count 0 2006.257.06:20:56.66#ibcon#about to read 5, iclass 11, count 0 2006.257.06:20:56.66#ibcon#read 5, iclass 11, count 0 2006.257.06:20:56.66#ibcon#about to read 6, iclass 11, count 0 2006.257.06:20:56.66#ibcon#read 6, iclass 11, count 0 2006.257.06:20:56.66#ibcon#end of sib2, iclass 11, count 0 2006.257.06:20:56.66#ibcon#*after write, iclass 11, count 0 2006.257.06:20:56.66#ibcon#*before return 0, iclass 11, count 0 2006.257.06:20:56.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:56.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:20:56.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:20:56.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:20:56.66$vck44/vb=6,4 2006.257.06:20:56.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.06:20:56.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.06:20:56.66#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:56.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:56.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:56.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:56.72#ibcon#enter wrdev, iclass 13, count 2 2006.257.06:20:56.72#ibcon#first serial, iclass 13, count 2 2006.257.06:20:56.72#ibcon#enter sib2, iclass 13, count 2 2006.257.06:20:56.72#ibcon#flushed, iclass 13, count 2 2006.257.06:20:56.72#ibcon#about to write, iclass 13, count 2 2006.257.06:20:56.72#ibcon#wrote, iclass 13, count 2 2006.257.06:20:56.72#ibcon#about to read 3, iclass 13, count 2 2006.257.06:20:56.74#ibcon#read 3, iclass 13, count 2 2006.257.06:20:56.74#ibcon#about to read 4, iclass 13, count 2 2006.257.06:20:56.74#ibcon#read 4, iclass 13, count 2 2006.257.06:20:56.74#ibcon#about to read 5, iclass 13, count 2 2006.257.06:20:56.74#ibcon#read 5, iclass 13, count 2 2006.257.06:20:56.74#ibcon#about to read 6, iclass 13, count 2 2006.257.06:20:56.74#ibcon#read 6, iclass 13, count 2 2006.257.06:20:56.74#ibcon#end of sib2, iclass 13, count 2 2006.257.06:20:56.74#ibcon#*mode == 0, iclass 13, count 2 2006.257.06:20:56.74#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.06:20:56.74#ibcon#[27=AT06-04\r\n] 2006.257.06:20:56.74#ibcon#*before write, iclass 13, count 2 2006.257.06:20:56.74#ibcon#enter sib2, iclass 13, count 2 2006.257.06:20:56.74#ibcon#flushed, iclass 13, count 2 2006.257.06:20:56.74#ibcon#about to write, iclass 13, count 2 2006.257.06:20:56.74#ibcon#wrote, iclass 13, count 2 2006.257.06:20:56.74#ibcon#about to read 3, iclass 13, count 2 2006.257.06:20:56.77#ibcon#read 3, iclass 13, count 2 2006.257.06:20:56.77#ibcon#about to read 4, iclass 13, count 2 2006.257.06:20:56.77#ibcon#read 4, iclass 13, count 2 2006.257.06:20:56.77#ibcon#about to read 5, iclass 13, count 2 2006.257.06:20:56.77#ibcon#read 5, iclass 13, count 2 2006.257.06:20:56.77#ibcon#about to read 6, iclass 13, count 2 2006.257.06:20:56.77#ibcon#read 6, iclass 13, count 2 2006.257.06:20:56.77#ibcon#end of sib2, iclass 13, count 2 2006.257.06:20:56.77#ibcon#*after write, iclass 13, count 2 2006.257.06:20:56.77#ibcon#*before return 0, iclass 13, count 2 2006.257.06:20:56.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:56.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:20:56.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.06:20:56.77#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:56.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:56.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:56.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:56.89#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:20:56.89#ibcon#first serial, iclass 13, count 0 2006.257.06:20:56.89#ibcon#enter sib2, iclass 13, count 0 2006.257.06:20:56.89#ibcon#flushed, iclass 13, count 0 2006.257.06:20:56.89#ibcon#about to write, iclass 13, count 0 2006.257.06:20:56.89#ibcon#wrote, iclass 13, count 0 2006.257.06:20:56.89#ibcon#about to read 3, iclass 13, count 0 2006.257.06:20:56.91#ibcon#read 3, iclass 13, count 0 2006.257.06:20:56.91#ibcon#about to read 4, iclass 13, count 0 2006.257.06:20:56.91#ibcon#read 4, iclass 13, count 0 2006.257.06:20:56.91#ibcon#about to read 5, iclass 13, count 0 2006.257.06:20:56.91#ibcon#read 5, iclass 13, count 0 2006.257.06:20:56.91#ibcon#about to read 6, iclass 13, count 0 2006.257.06:20:56.91#ibcon#read 6, iclass 13, count 0 2006.257.06:20:56.91#ibcon#end of sib2, iclass 13, count 0 2006.257.06:20:56.91#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:20:56.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:20:56.91#ibcon#[27=USB\r\n] 2006.257.06:20:56.91#ibcon#*before write, iclass 13, count 0 2006.257.06:20:56.91#ibcon#enter sib2, iclass 13, count 0 2006.257.06:20:56.91#ibcon#flushed, iclass 13, count 0 2006.257.06:20:56.91#ibcon#about to write, iclass 13, count 0 2006.257.06:20:56.91#ibcon#wrote, iclass 13, count 0 2006.257.06:20:56.91#ibcon#about to read 3, iclass 13, count 0 2006.257.06:20:56.94#ibcon#read 3, iclass 13, count 0 2006.257.06:20:56.94#ibcon#about to read 4, iclass 13, count 0 2006.257.06:20:56.94#ibcon#read 4, iclass 13, count 0 2006.257.06:20:56.94#ibcon#about to read 5, iclass 13, count 0 2006.257.06:20:56.94#ibcon#read 5, iclass 13, count 0 2006.257.06:20:56.94#ibcon#about to read 6, iclass 13, count 0 2006.257.06:20:56.94#ibcon#read 6, iclass 13, count 0 2006.257.06:20:56.94#ibcon#end of sib2, iclass 13, count 0 2006.257.06:20:56.94#ibcon#*after write, iclass 13, count 0 2006.257.06:20:56.94#ibcon#*before return 0, iclass 13, count 0 2006.257.06:20:56.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:56.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:20:56.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:20:56.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:20:56.94$vck44/vblo=7,734.99 2006.257.06:20:56.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.06:20:56.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.06:20:56.94#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:56.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:56.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:56.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:56.94#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:20:56.94#ibcon#first serial, iclass 15, count 0 2006.257.06:20:56.94#ibcon#enter sib2, iclass 15, count 0 2006.257.06:20:56.94#ibcon#flushed, iclass 15, count 0 2006.257.06:20:56.94#ibcon#about to write, iclass 15, count 0 2006.257.06:20:56.94#ibcon#wrote, iclass 15, count 0 2006.257.06:20:56.94#ibcon#about to read 3, iclass 15, count 0 2006.257.06:20:56.96#ibcon#read 3, iclass 15, count 0 2006.257.06:20:56.96#ibcon#about to read 4, iclass 15, count 0 2006.257.06:20:56.96#ibcon#read 4, iclass 15, count 0 2006.257.06:20:56.96#ibcon#about to read 5, iclass 15, count 0 2006.257.06:20:56.96#ibcon#read 5, iclass 15, count 0 2006.257.06:20:56.96#ibcon#about to read 6, iclass 15, count 0 2006.257.06:20:56.96#ibcon#read 6, iclass 15, count 0 2006.257.06:20:56.96#ibcon#end of sib2, iclass 15, count 0 2006.257.06:20:56.96#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:20:56.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:20:56.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:20:56.96#ibcon#*before write, iclass 15, count 0 2006.257.06:20:56.96#ibcon#enter sib2, iclass 15, count 0 2006.257.06:20:56.96#ibcon#flushed, iclass 15, count 0 2006.257.06:20:56.96#ibcon#about to write, iclass 15, count 0 2006.257.06:20:56.96#ibcon#wrote, iclass 15, count 0 2006.257.06:20:56.96#ibcon#about to read 3, iclass 15, count 0 2006.257.06:20:57.00#ibcon#read 3, iclass 15, count 0 2006.257.06:20:57.00#ibcon#about to read 4, iclass 15, count 0 2006.257.06:20:57.00#ibcon#read 4, iclass 15, count 0 2006.257.06:20:57.00#ibcon#about to read 5, iclass 15, count 0 2006.257.06:20:57.00#ibcon#read 5, iclass 15, count 0 2006.257.06:20:57.00#ibcon#about to read 6, iclass 15, count 0 2006.257.06:20:57.00#ibcon#read 6, iclass 15, count 0 2006.257.06:20:57.00#ibcon#end of sib2, iclass 15, count 0 2006.257.06:20:57.00#ibcon#*after write, iclass 15, count 0 2006.257.06:20:57.00#ibcon#*before return 0, iclass 15, count 0 2006.257.06:20:57.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:57.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:20:57.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:20:57.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:20:57.00$vck44/vb=7,4 2006.257.06:20:57.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.06:20:57.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.06:20:57.00#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:57.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:57.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:57.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:57.06#ibcon#enter wrdev, iclass 17, count 2 2006.257.06:20:57.06#ibcon#first serial, iclass 17, count 2 2006.257.06:20:57.06#ibcon#enter sib2, iclass 17, count 2 2006.257.06:20:57.06#ibcon#flushed, iclass 17, count 2 2006.257.06:20:57.06#ibcon#about to write, iclass 17, count 2 2006.257.06:20:57.06#ibcon#wrote, iclass 17, count 2 2006.257.06:20:57.06#ibcon#about to read 3, iclass 17, count 2 2006.257.06:20:57.08#ibcon#read 3, iclass 17, count 2 2006.257.06:20:57.08#ibcon#about to read 4, iclass 17, count 2 2006.257.06:20:57.08#ibcon#read 4, iclass 17, count 2 2006.257.06:20:57.08#ibcon#about to read 5, iclass 17, count 2 2006.257.06:20:57.08#ibcon#read 5, iclass 17, count 2 2006.257.06:20:57.08#ibcon#about to read 6, iclass 17, count 2 2006.257.06:20:57.08#ibcon#read 6, iclass 17, count 2 2006.257.06:20:57.08#ibcon#end of sib2, iclass 17, count 2 2006.257.06:20:57.08#ibcon#*mode == 0, iclass 17, count 2 2006.257.06:20:57.08#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.06:20:57.08#ibcon#[27=AT07-04\r\n] 2006.257.06:20:57.08#ibcon#*before write, iclass 17, count 2 2006.257.06:20:57.08#ibcon#enter sib2, iclass 17, count 2 2006.257.06:20:57.08#ibcon#flushed, iclass 17, count 2 2006.257.06:20:57.08#ibcon#about to write, iclass 17, count 2 2006.257.06:20:57.08#ibcon#wrote, iclass 17, count 2 2006.257.06:20:57.08#ibcon#about to read 3, iclass 17, count 2 2006.257.06:20:57.11#ibcon#read 3, iclass 17, count 2 2006.257.06:20:57.11#ibcon#about to read 4, iclass 17, count 2 2006.257.06:20:57.11#ibcon#read 4, iclass 17, count 2 2006.257.06:20:57.11#ibcon#about to read 5, iclass 17, count 2 2006.257.06:20:57.11#ibcon#read 5, iclass 17, count 2 2006.257.06:20:57.11#ibcon#about to read 6, iclass 17, count 2 2006.257.06:20:57.11#ibcon#read 6, iclass 17, count 2 2006.257.06:20:57.11#ibcon#end of sib2, iclass 17, count 2 2006.257.06:20:57.11#ibcon#*after write, iclass 17, count 2 2006.257.06:20:57.11#ibcon#*before return 0, iclass 17, count 2 2006.257.06:20:57.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:57.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:20:57.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.06:20:57.11#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:57.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:57.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:57.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:57.23#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:20:57.23#ibcon#first serial, iclass 17, count 0 2006.257.06:20:57.23#ibcon#enter sib2, iclass 17, count 0 2006.257.06:20:57.23#ibcon#flushed, iclass 17, count 0 2006.257.06:20:57.23#ibcon#about to write, iclass 17, count 0 2006.257.06:20:57.23#ibcon#wrote, iclass 17, count 0 2006.257.06:20:57.23#ibcon#about to read 3, iclass 17, count 0 2006.257.06:20:57.25#ibcon#read 3, iclass 17, count 0 2006.257.06:20:57.25#ibcon#about to read 4, iclass 17, count 0 2006.257.06:20:57.25#ibcon#read 4, iclass 17, count 0 2006.257.06:20:57.25#ibcon#about to read 5, iclass 17, count 0 2006.257.06:20:57.25#ibcon#read 5, iclass 17, count 0 2006.257.06:20:57.25#ibcon#about to read 6, iclass 17, count 0 2006.257.06:20:57.25#ibcon#read 6, iclass 17, count 0 2006.257.06:20:57.25#ibcon#end of sib2, iclass 17, count 0 2006.257.06:20:57.25#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:20:57.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:20:57.25#ibcon#[27=USB\r\n] 2006.257.06:20:57.25#ibcon#*before write, iclass 17, count 0 2006.257.06:20:57.25#ibcon#enter sib2, iclass 17, count 0 2006.257.06:20:57.25#ibcon#flushed, iclass 17, count 0 2006.257.06:20:57.25#ibcon#about to write, iclass 17, count 0 2006.257.06:20:57.25#ibcon#wrote, iclass 17, count 0 2006.257.06:20:57.25#ibcon#about to read 3, iclass 17, count 0 2006.257.06:20:57.28#ibcon#read 3, iclass 17, count 0 2006.257.06:20:57.28#ibcon#about to read 4, iclass 17, count 0 2006.257.06:20:57.28#ibcon#read 4, iclass 17, count 0 2006.257.06:20:57.28#ibcon#about to read 5, iclass 17, count 0 2006.257.06:20:57.28#ibcon#read 5, iclass 17, count 0 2006.257.06:20:57.28#ibcon#about to read 6, iclass 17, count 0 2006.257.06:20:57.28#ibcon#read 6, iclass 17, count 0 2006.257.06:20:57.28#ibcon#end of sib2, iclass 17, count 0 2006.257.06:20:57.28#ibcon#*after write, iclass 17, count 0 2006.257.06:20:57.28#ibcon#*before return 0, iclass 17, count 0 2006.257.06:20:57.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:57.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:20:57.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:20:57.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:20:57.28$vck44/vblo=8,744.99 2006.257.06:20:57.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.06:20:57.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.06:20:57.28#ibcon#ireg 17 cls_cnt 0 2006.257.06:20:57.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:57.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:57.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:57.28#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:20:57.28#ibcon#first serial, iclass 19, count 0 2006.257.06:20:57.28#ibcon#enter sib2, iclass 19, count 0 2006.257.06:20:57.28#ibcon#flushed, iclass 19, count 0 2006.257.06:20:57.28#ibcon#about to write, iclass 19, count 0 2006.257.06:20:57.28#ibcon#wrote, iclass 19, count 0 2006.257.06:20:57.28#ibcon#about to read 3, iclass 19, count 0 2006.257.06:20:57.30#ibcon#read 3, iclass 19, count 0 2006.257.06:20:57.30#ibcon#about to read 4, iclass 19, count 0 2006.257.06:20:57.30#ibcon#read 4, iclass 19, count 0 2006.257.06:20:57.30#ibcon#about to read 5, iclass 19, count 0 2006.257.06:20:57.30#ibcon#read 5, iclass 19, count 0 2006.257.06:20:57.30#ibcon#about to read 6, iclass 19, count 0 2006.257.06:20:57.30#ibcon#read 6, iclass 19, count 0 2006.257.06:20:57.30#ibcon#end of sib2, iclass 19, count 0 2006.257.06:20:57.30#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:20:57.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:20:57.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:20:57.30#ibcon#*before write, iclass 19, count 0 2006.257.06:20:57.30#ibcon#enter sib2, iclass 19, count 0 2006.257.06:20:57.30#ibcon#flushed, iclass 19, count 0 2006.257.06:20:57.30#ibcon#about to write, iclass 19, count 0 2006.257.06:20:57.30#ibcon#wrote, iclass 19, count 0 2006.257.06:20:57.30#ibcon#about to read 3, iclass 19, count 0 2006.257.06:20:57.34#ibcon#read 3, iclass 19, count 0 2006.257.06:20:57.34#ibcon#about to read 4, iclass 19, count 0 2006.257.06:20:57.34#ibcon#read 4, iclass 19, count 0 2006.257.06:20:57.34#ibcon#about to read 5, iclass 19, count 0 2006.257.06:20:57.34#ibcon#read 5, iclass 19, count 0 2006.257.06:20:57.34#ibcon#about to read 6, iclass 19, count 0 2006.257.06:20:57.34#ibcon#read 6, iclass 19, count 0 2006.257.06:20:57.34#ibcon#end of sib2, iclass 19, count 0 2006.257.06:20:57.34#ibcon#*after write, iclass 19, count 0 2006.257.06:20:57.34#ibcon#*before return 0, iclass 19, count 0 2006.257.06:20:57.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:57.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:20:57.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:20:57.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:20:57.34$vck44/vb=8,4 2006.257.06:20:57.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.06:20:57.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.06:20:57.34#ibcon#ireg 11 cls_cnt 2 2006.257.06:20:57.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:57.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:57.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:57.40#ibcon#enter wrdev, iclass 21, count 2 2006.257.06:20:57.40#ibcon#first serial, iclass 21, count 2 2006.257.06:20:57.40#ibcon#enter sib2, iclass 21, count 2 2006.257.06:20:57.40#ibcon#flushed, iclass 21, count 2 2006.257.06:20:57.40#ibcon#about to write, iclass 21, count 2 2006.257.06:20:57.40#ibcon#wrote, iclass 21, count 2 2006.257.06:20:57.40#ibcon#about to read 3, iclass 21, count 2 2006.257.06:20:57.42#ibcon#read 3, iclass 21, count 2 2006.257.06:20:57.42#ibcon#about to read 4, iclass 21, count 2 2006.257.06:20:57.42#ibcon#read 4, iclass 21, count 2 2006.257.06:20:57.42#ibcon#about to read 5, iclass 21, count 2 2006.257.06:20:57.42#ibcon#read 5, iclass 21, count 2 2006.257.06:20:57.42#ibcon#about to read 6, iclass 21, count 2 2006.257.06:20:57.42#ibcon#read 6, iclass 21, count 2 2006.257.06:20:57.42#ibcon#end of sib2, iclass 21, count 2 2006.257.06:20:57.42#ibcon#*mode == 0, iclass 21, count 2 2006.257.06:20:57.42#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.06:20:57.42#ibcon#[27=AT08-04\r\n] 2006.257.06:20:57.42#ibcon#*before write, iclass 21, count 2 2006.257.06:20:57.42#ibcon#enter sib2, iclass 21, count 2 2006.257.06:20:57.42#ibcon#flushed, iclass 21, count 2 2006.257.06:20:57.42#ibcon#about to write, iclass 21, count 2 2006.257.06:20:57.42#ibcon#wrote, iclass 21, count 2 2006.257.06:20:57.42#ibcon#about to read 3, iclass 21, count 2 2006.257.06:20:57.45#ibcon#read 3, iclass 21, count 2 2006.257.06:20:57.45#ibcon#about to read 4, iclass 21, count 2 2006.257.06:20:57.45#ibcon#read 4, iclass 21, count 2 2006.257.06:20:57.45#ibcon#about to read 5, iclass 21, count 2 2006.257.06:20:57.45#ibcon#read 5, iclass 21, count 2 2006.257.06:20:57.45#ibcon#about to read 6, iclass 21, count 2 2006.257.06:20:57.45#ibcon#read 6, iclass 21, count 2 2006.257.06:20:57.45#ibcon#end of sib2, iclass 21, count 2 2006.257.06:20:57.45#ibcon#*after write, iclass 21, count 2 2006.257.06:20:57.45#ibcon#*before return 0, iclass 21, count 2 2006.257.06:20:57.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:57.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:20:57.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.06:20:57.45#ibcon#ireg 7 cls_cnt 0 2006.257.06:20:57.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:57.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:57.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:57.57#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:20:57.57#ibcon#first serial, iclass 21, count 0 2006.257.06:20:57.57#ibcon#enter sib2, iclass 21, count 0 2006.257.06:20:57.57#ibcon#flushed, iclass 21, count 0 2006.257.06:20:57.57#ibcon#about to write, iclass 21, count 0 2006.257.06:20:57.57#ibcon#wrote, iclass 21, count 0 2006.257.06:20:57.57#ibcon#about to read 3, iclass 21, count 0 2006.257.06:20:57.59#ibcon#read 3, iclass 21, count 0 2006.257.06:20:57.59#ibcon#about to read 4, iclass 21, count 0 2006.257.06:20:57.59#ibcon#read 4, iclass 21, count 0 2006.257.06:20:57.59#ibcon#about to read 5, iclass 21, count 0 2006.257.06:20:57.59#ibcon#read 5, iclass 21, count 0 2006.257.06:20:57.59#ibcon#about to read 6, iclass 21, count 0 2006.257.06:20:57.59#ibcon#read 6, iclass 21, count 0 2006.257.06:20:57.59#ibcon#end of sib2, iclass 21, count 0 2006.257.06:20:57.59#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:20:57.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:20:57.59#ibcon#[27=USB\r\n] 2006.257.06:20:57.59#ibcon#*before write, iclass 21, count 0 2006.257.06:20:57.59#ibcon#enter sib2, iclass 21, count 0 2006.257.06:20:57.59#ibcon#flushed, iclass 21, count 0 2006.257.06:20:57.59#ibcon#about to write, iclass 21, count 0 2006.257.06:20:57.59#ibcon#wrote, iclass 21, count 0 2006.257.06:20:57.59#ibcon#about to read 3, iclass 21, count 0 2006.257.06:20:57.62#ibcon#read 3, iclass 21, count 0 2006.257.06:20:57.62#ibcon#about to read 4, iclass 21, count 0 2006.257.06:20:57.62#ibcon#read 4, iclass 21, count 0 2006.257.06:20:57.62#ibcon#about to read 5, iclass 21, count 0 2006.257.06:20:57.62#ibcon#read 5, iclass 21, count 0 2006.257.06:20:57.62#ibcon#about to read 6, iclass 21, count 0 2006.257.06:20:57.62#ibcon#read 6, iclass 21, count 0 2006.257.06:20:57.62#ibcon#end of sib2, iclass 21, count 0 2006.257.06:20:57.62#ibcon#*after write, iclass 21, count 0 2006.257.06:20:57.62#ibcon#*before return 0, iclass 21, count 0 2006.257.06:20:57.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:57.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:20:57.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:20:57.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:20:57.62$vck44/vabw=wide 2006.257.06:20:57.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.06:20:57.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.06:20:57.62#ibcon#ireg 8 cls_cnt 0 2006.257.06:20:57.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:57.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:57.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:57.62#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:20:57.62#ibcon#first serial, iclass 23, count 0 2006.257.06:20:57.62#ibcon#enter sib2, iclass 23, count 0 2006.257.06:20:57.62#ibcon#flushed, iclass 23, count 0 2006.257.06:20:57.62#ibcon#about to write, iclass 23, count 0 2006.257.06:20:57.62#ibcon#wrote, iclass 23, count 0 2006.257.06:20:57.62#ibcon#about to read 3, iclass 23, count 0 2006.257.06:20:57.64#ibcon#read 3, iclass 23, count 0 2006.257.06:20:57.64#ibcon#about to read 4, iclass 23, count 0 2006.257.06:20:57.64#ibcon#read 4, iclass 23, count 0 2006.257.06:20:57.64#ibcon#about to read 5, iclass 23, count 0 2006.257.06:20:57.64#ibcon#read 5, iclass 23, count 0 2006.257.06:20:57.64#ibcon#about to read 6, iclass 23, count 0 2006.257.06:20:57.64#ibcon#read 6, iclass 23, count 0 2006.257.06:20:57.64#ibcon#end of sib2, iclass 23, count 0 2006.257.06:20:57.64#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:20:57.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:20:57.64#ibcon#[25=BW32\r\n] 2006.257.06:20:57.64#ibcon#*before write, iclass 23, count 0 2006.257.06:20:57.64#ibcon#enter sib2, iclass 23, count 0 2006.257.06:20:57.64#ibcon#flushed, iclass 23, count 0 2006.257.06:20:57.64#ibcon#about to write, iclass 23, count 0 2006.257.06:20:57.64#ibcon#wrote, iclass 23, count 0 2006.257.06:20:57.64#ibcon#about to read 3, iclass 23, count 0 2006.257.06:20:57.67#ibcon#read 3, iclass 23, count 0 2006.257.06:20:57.67#ibcon#about to read 4, iclass 23, count 0 2006.257.06:20:57.67#ibcon#read 4, iclass 23, count 0 2006.257.06:20:57.67#ibcon#about to read 5, iclass 23, count 0 2006.257.06:20:57.67#ibcon#read 5, iclass 23, count 0 2006.257.06:20:57.67#ibcon#about to read 6, iclass 23, count 0 2006.257.06:20:57.67#ibcon#read 6, iclass 23, count 0 2006.257.06:20:57.67#ibcon#end of sib2, iclass 23, count 0 2006.257.06:20:57.67#ibcon#*after write, iclass 23, count 0 2006.257.06:20:57.67#ibcon#*before return 0, iclass 23, count 0 2006.257.06:20:57.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:57.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:20:57.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:20:57.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:20:57.67$vck44/vbbw=wide 2006.257.06:20:57.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.06:20:57.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.06:20:57.67#ibcon#ireg 8 cls_cnt 0 2006.257.06:20:57.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:20:57.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:20:57.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:20:57.74#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:20:57.74#ibcon#first serial, iclass 25, count 0 2006.257.06:20:57.74#ibcon#enter sib2, iclass 25, count 0 2006.257.06:20:57.74#ibcon#flushed, iclass 25, count 0 2006.257.06:20:57.74#ibcon#about to write, iclass 25, count 0 2006.257.06:20:57.74#ibcon#wrote, iclass 25, count 0 2006.257.06:20:57.74#ibcon#about to read 3, iclass 25, count 0 2006.257.06:20:57.76#ibcon#read 3, iclass 25, count 0 2006.257.06:20:57.76#ibcon#about to read 4, iclass 25, count 0 2006.257.06:20:57.76#ibcon#read 4, iclass 25, count 0 2006.257.06:20:57.76#ibcon#about to read 5, iclass 25, count 0 2006.257.06:20:57.76#ibcon#read 5, iclass 25, count 0 2006.257.06:20:57.76#ibcon#about to read 6, iclass 25, count 0 2006.257.06:20:57.76#ibcon#read 6, iclass 25, count 0 2006.257.06:20:57.76#ibcon#end of sib2, iclass 25, count 0 2006.257.06:20:57.76#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:20:57.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:20:57.76#ibcon#[27=BW32\r\n] 2006.257.06:20:57.76#ibcon#*before write, iclass 25, count 0 2006.257.06:20:57.76#ibcon#enter sib2, iclass 25, count 0 2006.257.06:20:57.76#ibcon#flushed, iclass 25, count 0 2006.257.06:20:57.76#ibcon#about to write, iclass 25, count 0 2006.257.06:20:57.76#ibcon#wrote, iclass 25, count 0 2006.257.06:20:57.76#ibcon#about to read 3, iclass 25, count 0 2006.257.06:20:57.79#ibcon#read 3, iclass 25, count 0 2006.257.06:20:57.79#ibcon#about to read 4, iclass 25, count 0 2006.257.06:20:57.79#ibcon#read 4, iclass 25, count 0 2006.257.06:20:57.79#ibcon#about to read 5, iclass 25, count 0 2006.257.06:20:57.79#ibcon#read 5, iclass 25, count 0 2006.257.06:20:57.79#ibcon#about to read 6, iclass 25, count 0 2006.257.06:20:57.79#ibcon#read 6, iclass 25, count 0 2006.257.06:20:57.79#ibcon#end of sib2, iclass 25, count 0 2006.257.06:20:57.79#ibcon#*after write, iclass 25, count 0 2006.257.06:20:57.79#ibcon#*before return 0, iclass 25, count 0 2006.257.06:20:57.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:20:57.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:20:57.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:20:57.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:20:57.79$setupk4/ifdk4 2006.257.06:20:57.79$ifdk4/lo= 2006.257.06:20:57.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:20:57.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:20:57.79$ifdk4/patch= 2006.257.06:20:57.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:20:57.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:20:57.79$setupk4/!*+20s 2006.257.06:21:03.15#abcon#<5=/15 1.2 3.4 20.43 891012.2\r\n> 2006.257.06:21:03.17#abcon#{5=INTERFACE CLEAR} 2006.257.06:21:03.23#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:21:12.30$setupk4/"tpicd 2006.257.06:21:12.30$setupk4/echo=off 2006.257.06:21:12.30$setupk4/xlog=off 2006.257.06:21:12.30:!2006.257.06:23:26 2006.257.06:21:40.14#trakl#Source acquired 2006.257.06:21:41.14#flagr#flagr/antenna,acquired 2006.257.06:23:26.00:preob 2006.257.06:23:27.14/onsource/TRACKING 2006.257.06:23:27.14:!2006.257.06:23:36 2006.257.06:23:36.00:"tape 2006.257.06:23:36.00:"st=record 2006.257.06:23:36.00:data_valid=on 2006.257.06:23:36.00:midob 2006.257.06:23:36.14/onsource/TRACKING 2006.257.06:23:36.14/wx/20.44,1012.2,89 2006.257.06:23:36.31/cable/+6.4787E-03 2006.257.06:23:37.40/va/01,08,usb,yes,32,35 2006.257.06:23:37.40/va/02,07,usb,yes,35,35 2006.257.06:23:37.40/va/03,08,usb,yes,31,33 2006.257.06:23:37.40/va/04,07,usb,yes,36,38 2006.257.06:23:37.40/va/05,04,usb,yes,32,33 2006.257.06:23:37.40/va/06,04,usb,yes,36,35 2006.257.06:23:37.40/va/07,04,usb,yes,37,37 2006.257.06:23:37.40/va/08,04,usb,yes,31,38 2006.257.06:23:37.63/valo/01,524.99,yes,locked 2006.257.06:23:37.63/valo/02,534.99,yes,locked 2006.257.06:23:37.63/valo/03,564.99,yes,locked 2006.257.06:23:37.63/valo/04,624.99,yes,locked 2006.257.06:23:37.63/valo/05,734.99,yes,locked 2006.257.06:23:37.63/valo/06,814.99,yes,locked 2006.257.06:23:37.63/valo/07,864.99,yes,locked 2006.257.06:23:37.63/valo/08,884.99,yes,locked 2006.257.06:23:38.72/vb/01,04,usb,yes,31,29 2006.257.06:23:38.72/vb/02,05,usb,yes,29,29 2006.257.06:23:38.72/vb/03,04,usb,yes,30,33 2006.257.06:23:38.72/vb/04,05,usb,yes,30,29 2006.257.06:23:38.72/vb/05,04,usb,yes,27,29 2006.257.06:23:38.72/vb/06,04,usb,yes,31,28 2006.257.06:23:38.72/vb/07,04,usb,yes,31,31 2006.257.06:23:38.72/vb/08,04,usb,yes,29,32 2006.257.06:23:38.96/vblo/01,629.99,yes,locked 2006.257.06:23:38.96/vblo/02,634.99,yes,locked 2006.257.06:23:38.96/vblo/03,649.99,yes,locked 2006.257.06:23:38.96/vblo/04,679.99,yes,locked 2006.257.06:23:38.96/vblo/05,709.99,yes,locked 2006.257.06:23:38.96/vblo/06,719.99,yes,locked 2006.257.06:23:38.96/vblo/07,734.99,yes,locked 2006.257.06:23:38.96/vblo/08,744.99,yes,locked 2006.257.06:23:39.11/vabw/8 2006.257.06:23:39.26/vbbw/8 2006.257.06:23:39.35/xfe/off,on,16.5 2006.257.06:23:39.73/ifatt/23,28,28,28 2006.257.06:23:40.08/fmout-gps/S +4.54E-07 2006.257.06:23:40.12:!2006.257.06:28:16 2006.257.06:28:16.00:data_valid=off 2006.257.06:28:16.00:"et 2006.257.06:28:16.00:!+3s 2006.257.06:28:19.01:"tape 2006.257.06:28:19.01:postob 2006.257.06:28:19.20/cable/+6.4783E-03 2006.257.06:28:19.20/wx/20.48,1012.2,89 2006.257.06:28:20.08/fmout-gps/S +4.52E-07 2006.257.06:28:20.08:scan_name=257-0631,jd0609,220 2006.257.06:28:20.08:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.257.06:28:21.14:checkk5 2006.257.06:28:21.14#flagr#flagr/antenna,new-source 2006.257.06:28:21.61/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:28:22.01/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:28:22.43/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:28:22.81/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:28:23.21/chk_obsdata//k5ts1/T2570623??a.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.257.06:28:23.63/chk_obsdata//k5ts2/T2570623??b.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.257.06:28:24.05/chk_obsdata//k5ts3/T2570623??c.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.257.06:28:24.44/chk_obsdata//k5ts4/T2570623??d.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.257.06:28:25.17/k5log//k5ts1_log_newline 2006.257.06:28:25.90/k5log//k5ts2_log_newline 2006.257.06:28:26.65/k5log//k5ts3_log_newline 2006.257.06:28:27.38/k5log//k5ts4_log_newline 2006.257.06:28:27.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:28:27.40:setupk4=1 2006.257.06:28:27.40$setupk4/echo=on 2006.257.06:28:27.40$setupk4/pcalon 2006.257.06:28:27.40$pcalon/"no phase cal control is implemented here 2006.257.06:28:27.40$setupk4/"tpicd=stop 2006.257.06:28:27.40$setupk4/"rec=synch_on 2006.257.06:28:27.40$setupk4/"rec_mode=128 2006.257.06:28:27.40$setupk4/!* 2006.257.06:28:27.40$setupk4/recpk4 2006.257.06:28:27.40$recpk4/recpatch= 2006.257.06:28:27.40$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:28:27.40$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:28:27.40$setupk4/vck44 2006.257.06:28:27.40$vck44/valo=1,524.99 2006.257.06:28:27.40#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.06:28:27.40#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.06:28:27.40#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:27.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:27.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:27.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:27.40#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:28:27.40#ibcon#first serial, iclass 26, count 0 2006.257.06:28:27.40#ibcon#enter sib2, iclass 26, count 0 2006.257.06:28:27.40#ibcon#flushed, iclass 26, count 0 2006.257.06:28:27.40#ibcon#about to write, iclass 26, count 0 2006.257.06:28:27.40#ibcon#wrote, iclass 26, count 0 2006.257.06:28:27.40#ibcon#about to read 3, iclass 26, count 0 2006.257.06:28:27.42#ibcon#read 3, iclass 26, count 0 2006.257.06:28:27.42#ibcon#about to read 4, iclass 26, count 0 2006.257.06:28:27.42#ibcon#read 4, iclass 26, count 0 2006.257.06:28:27.42#ibcon#about to read 5, iclass 26, count 0 2006.257.06:28:27.42#ibcon#read 5, iclass 26, count 0 2006.257.06:28:27.42#ibcon#about to read 6, iclass 26, count 0 2006.257.06:28:27.42#ibcon#read 6, iclass 26, count 0 2006.257.06:28:27.42#ibcon#end of sib2, iclass 26, count 0 2006.257.06:28:27.42#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:28:27.42#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:28:27.42#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:28:27.42#ibcon#*before write, iclass 26, count 0 2006.257.06:28:27.42#ibcon#enter sib2, iclass 26, count 0 2006.257.06:28:27.42#ibcon#flushed, iclass 26, count 0 2006.257.06:28:27.42#ibcon#about to write, iclass 26, count 0 2006.257.06:28:27.42#ibcon#wrote, iclass 26, count 0 2006.257.06:28:27.42#ibcon#about to read 3, iclass 26, count 0 2006.257.06:28:27.47#ibcon#read 3, iclass 26, count 0 2006.257.06:28:27.47#ibcon#about to read 4, iclass 26, count 0 2006.257.06:28:27.47#ibcon#read 4, iclass 26, count 0 2006.257.06:28:27.47#ibcon#about to read 5, iclass 26, count 0 2006.257.06:28:27.47#ibcon#read 5, iclass 26, count 0 2006.257.06:28:27.47#ibcon#about to read 6, iclass 26, count 0 2006.257.06:28:27.47#ibcon#read 6, iclass 26, count 0 2006.257.06:28:27.47#ibcon#end of sib2, iclass 26, count 0 2006.257.06:28:27.47#ibcon#*after write, iclass 26, count 0 2006.257.06:28:27.47#ibcon#*before return 0, iclass 26, count 0 2006.257.06:28:27.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:27.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:27.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:28:27.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:28:27.47$vck44/va=1,8 2006.257.06:28:27.47#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.06:28:27.47#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.06:28:27.47#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:27.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:27.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:27.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:27.47#ibcon#enter wrdev, iclass 28, count 2 2006.257.06:28:27.47#ibcon#first serial, iclass 28, count 2 2006.257.06:28:27.47#ibcon#enter sib2, iclass 28, count 2 2006.257.06:28:27.47#ibcon#flushed, iclass 28, count 2 2006.257.06:28:27.47#ibcon#about to write, iclass 28, count 2 2006.257.06:28:27.47#ibcon#wrote, iclass 28, count 2 2006.257.06:28:27.47#ibcon#about to read 3, iclass 28, count 2 2006.257.06:28:27.49#ibcon#read 3, iclass 28, count 2 2006.257.06:28:27.49#ibcon#about to read 4, iclass 28, count 2 2006.257.06:28:27.49#ibcon#read 4, iclass 28, count 2 2006.257.06:28:27.49#ibcon#about to read 5, iclass 28, count 2 2006.257.06:28:27.49#ibcon#read 5, iclass 28, count 2 2006.257.06:28:27.49#ibcon#about to read 6, iclass 28, count 2 2006.257.06:28:27.49#ibcon#read 6, iclass 28, count 2 2006.257.06:28:27.49#ibcon#end of sib2, iclass 28, count 2 2006.257.06:28:27.49#ibcon#*mode == 0, iclass 28, count 2 2006.257.06:28:27.49#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.06:28:27.49#ibcon#[25=AT01-08\r\n] 2006.257.06:28:27.49#ibcon#*before write, iclass 28, count 2 2006.257.06:28:27.49#ibcon#enter sib2, iclass 28, count 2 2006.257.06:28:27.49#ibcon#flushed, iclass 28, count 2 2006.257.06:28:27.49#ibcon#about to write, iclass 28, count 2 2006.257.06:28:27.49#ibcon#wrote, iclass 28, count 2 2006.257.06:28:27.49#ibcon#about to read 3, iclass 28, count 2 2006.257.06:28:27.52#ibcon#read 3, iclass 28, count 2 2006.257.06:28:27.52#ibcon#about to read 4, iclass 28, count 2 2006.257.06:28:27.52#ibcon#read 4, iclass 28, count 2 2006.257.06:28:27.52#ibcon#about to read 5, iclass 28, count 2 2006.257.06:28:27.52#ibcon#read 5, iclass 28, count 2 2006.257.06:28:27.52#ibcon#about to read 6, iclass 28, count 2 2006.257.06:28:27.52#ibcon#read 6, iclass 28, count 2 2006.257.06:28:27.52#ibcon#end of sib2, iclass 28, count 2 2006.257.06:28:27.52#ibcon#*after write, iclass 28, count 2 2006.257.06:28:27.52#ibcon#*before return 0, iclass 28, count 2 2006.257.06:28:27.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:27.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:27.52#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.06:28:27.52#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:27.52#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:27.64#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:27.64#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:27.64#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:28:27.64#ibcon#first serial, iclass 28, count 0 2006.257.06:28:27.64#ibcon#enter sib2, iclass 28, count 0 2006.257.06:28:27.64#ibcon#flushed, iclass 28, count 0 2006.257.06:28:27.64#ibcon#about to write, iclass 28, count 0 2006.257.06:28:27.64#ibcon#wrote, iclass 28, count 0 2006.257.06:28:27.64#ibcon#about to read 3, iclass 28, count 0 2006.257.06:28:27.66#ibcon#read 3, iclass 28, count 0 2006.257.06:28:27.66#ibcon#about to read 4, iclass 28, count 0 2006.257.06:28:27.66#ibcon#read 4, iclass 28, count 0 2006.257.06:28:27.66#ibcon#about to read 5, iclass 28, count 0 2006.257.06:28:27.66#ibcon#read 5, iclass 28, count 0 2006.257.06:28:27.66#ibcon#about to read 6, iclass 28, count 0 2006.257.06:28:27.66#ibcon#read 6, iclass 28, count 0 2006.257.06:28:27.66#ibcon#end of sib2, iclass 28, count 0 2006.257.06:28:27.66#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:28:27.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:28:27.66#ibcon#[25=USB\r\n] 2006.257.06:28:27.66#ibcon#*before write, iclass 28, count 0 2006.257.06:28:27.66#ibcon#enter sib2, iclass 28, count 0 2006.257.06:28:27.66#ibcon#flushed, iclass 28, count 0 2006.257.06:28:27.66#ibcon#about to write, iclass 28, count 0 2006.257.06:28:27.66#ibcon#wrote, iclass 28, count 0 2006.257.06:28:27.66#ibcon#about to read 3, iclass 28, count 0 2006.257.06:28:27.69#ibcon#read 3, iclass 28, count 0 2006.257.06:28:27.69#ibcon#about to read 4, iclass 28, count 0 2006.257.06:28:27.69#ibcon#read 4, iclass 28, count 0 2006.257.06:28:27.69#ibcon#about to read 5, iclass 28, count 0 2006.257.06:28:27.69#ibcon#read 5, iclass 28, count 0 2006.257.06:28:27.69#ibcon#about to read 6, iclass 28, count 0 2006.257.06:28:27.69#ibcon#read 6, iclass 28, count 0 2006.257.06:28:27.69#ibcon#end of sib2, iclass 28, count 0 2006.257.06:28:27.69#ibcon#*after write, iclass 28, count 0 2006.257.06:28:27.69#ibcon#*before return 0, iclass 28, count 0 2006.257.06:28:27.69#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:27.69#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:27.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:28:27.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:28:27.69$vck44/valo=2,534.99 2006.257.06:28:27.69#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.06:28:27.69#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.06:28:27.69#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:27.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:27.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:27.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:27.69#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:28:27.69#ibcon#first serial, iclass 30, count 0 2006.257.06:28:27.69#ibcon#enter sib2, iclass 30, count 0 2006.257.06:28:27.69#ibcon#flushed, iclass 30, count 0 2006.257.06:28:27.69#ibcon#about to write, iclass 30, count 0 2006.257.06:28:27.69#ibcon#wrote, iclass 30, count 0 2006.257.06:28:27.69#ibcon#about to read 3, iclass 30, count 0 2006.257.06:28:27.71#ibcon#read 3, iclass 30, count 0 2006.257.06:28:27.71#ibcon#about to read 4, iclass 30, count 0 2006.257.06:28:27.71#ibcon#read 4, iclass 30, count 0 2006.257.06:28:27.71#ibcon#about to read 5, iclass 30, count 0 2006.257.06:28:27.71#ibcon#read 5, iclass 30, count 0 2006.257.06:28:27.71#ibcon#about to read 6, iclass 30, count 0 2006.257.06:28:27.71#ibcon#read 6, iclass 30, count 0 2006.257.06:28:27.71#ibcon#end of sib2, iclass 30, count 0 2006.257.06:28:27.71#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:28:27.71#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:28:27.71#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:28:27.71#ibcon#*before write, iclass 30, count 0 2006.257.06:28:27.71#ibcon#enter sib2, iclass 30, count 0 2006.257.06:28:27.71#ibcon#flushed, iclass 30, count 0 2006.257.06:28:27.71#ibcon#about to write, iclass 30, count 0 2006.257.06:28:27.71#ibcon#wrote, iclass 30, count 0 2006.257.06:28:27.71#ibcon#about to read 3, iclass 30, count 0 2006.257.06:28:27.75#ibcon#read 3, iclass 30, count 0 2006.257.06:28:27.75#ibcon#about to read 4, iclass 30, count 0 2006.257.06:28:27.75#ibcon#read 4, iclass 30, count 0 2006.257.06:28:27.75#ibcon#about to read 5, iclass 30, count 0 2006.257.06:28:27.75#ibcon#read 5, iclass 30, count 0 2006.257.06:28:27.75#ibcon#about to read 6, iclass 30, count 0 2006.257.06:28:27.75#ibcon#read 6, iclass 30, count 0 2006.257.06:28:27.75#ibcon#end of sib2, iclass 30, count 0 2006.257.06:28:27.75#ibcon#*after write, iclass 30, count 0 2006.257.06:28:27.75#ibcon#*before return 0, iclass 30, count 0 2006.257.06:28:27.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:27.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:27.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:28:27.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:28:27.75$vck44/va=2,7 2006.257.06:28:27.75#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.06:28:27.75#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.06:28:27.75#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:27.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:27.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:27.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:27.81#ibcon#enter wrdev, iclass 32, count 2 2006.257.06:28:27.81#ibcon#first serial, iclass 32, count 2 2006.257.06:28:27.81#ibcon#enter sib2, iclass 32, count 2 2006.257.06:28:27.81#ibcon#flushed, iclass 32, count 2 2006.257.06:28:27.81#ibcon#about to write, iclass 32, count 2 2006.257.06:28:27.81#ibcon#wrote, iclass 32, count 2 2006.257.06:28:27.81#ibcon#about to read 3, iclass 32, count 2 2006.257.06:28:27.83#ibcon#read 3, iclass 32, count 2 2006.257.06:28:27.83#ibcon#about to read 4, iclass 32, count 2 2006.257.06:28:27.83#ibcon#read 4, iclass 32, count 2 2006.257.06:28:27.83#ibcon#about to read 5, iclass 32, count 2 2006.257.06:28:27.83#ibcon#read 5, iclass 32, count 2 2006.257.06:28:27.83#ibcon#about to read 6, iclass 32, count 2 2006.257.06:28:27.83#ibcon#read 6, iclass 32, count 2 2006.257.06:28:27.83#ibcon#end of sib2, iclass 32, count 2 2006.257.06:28:27.83#ibcon#*mode == 0, iclass 32, count 2 2006.257.06:28:27.83#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.06:28:27.83#ibcon#[25=AT02-07\r\n] 2006.257.06:28:27.83#ibcon#*before write, iclass 32, count 2 2006.257.06:28:27.83#ibcon#enter sib2, iclass 32, count 2 2006.257.06:28:27.83#ibcon#flushed, iclass 32, count 2 2006.257.06:28:27.83#ibcon#about to write, iclass 32, count 2 2006.257.06:28:27.83#ibcon#wrote, iclass 32, count 2 2006.257.06:28:27.83#ibcon#about to read 3, iclass 32, count 2 2006.257.06:28:27.86#ibcon#read 3, iclass 32, count 2 2006.257.06:28:27.86#ibcon#about to read 4, iclass 32, count 2 2006.257.06:28:27.86#ibcon#read 4, iclass 32, count 2 2006.257.06:28:27.86#ibcon#about to read 5, iclass 32, count 2 2006.257.06:28:27.86#ibcon#read 5, iclass 32, count 2 2006.257.06:28:27.86#ibcon#about to read 6, iclass 32, count 2 2006.257.06:28:27.86#ibcon#read 6, iclass 32, count 2 2006.257.06:28:27.86#ibcon#end of sib2, iclass 32, count 2 2006.257.06:28:27.86#ibcon#*after write, iclass 32, count 2 2006.257.06:28:27.86#ibcon#*before return 0, iclass 32, count 2 2006.257.06:28:27.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:27.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:27.86#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.06:28:27.86#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:27.86#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:27.98#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:27.98#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:27.98#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:28:27.98#ibcon#first serial, iclass 32, count 0 2006.257.06:28:27.98#ibcon#enter sib2, iclass 32, count 0 2006.257.06:28:27.98#ibcon#flushed, iclass 32, count 0 2006.257.06:28:27.98#ibcon#about to write, iclass 32, count 0 2006.257.06:28:27.98#ibcon#wrote, iclass 32, count 0 2006.257.06:28:27.98#ibcon#about to read 3, iclass 32, count 0 2006.257.06:28:28.00#ibcon#read 3, iclass 32, count 0 2006.257.06:28:28.00#ibcon#about to read 4, iclass 32, count 0 2006.257.06:28:28.00#ibcon#read 4, iclass 32, count 0 2006.257.06:28:28.00#ibcon#about to read 5, iclass 32, count 0 2006.257.06:28:28.00#ibcon#read 5, iclass 32, count 0 2006.257.06:28:28.00#ibcon#about to read 6, iclass 32, count 0 2006.257.06:28:28.00#ibcon#read 6, iclass 32, count 0 2006.257.06:28:28.00#ibcon#end of sib2, iclass 32, count 0 2006.257.06:28:28.00#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:28:28.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:28:28.00#ibcon#[25=USB\r\n] 2006.257.06:28:28.00#ibcon#*before write, iclass 32, count 0 2006.257.06:28:28.00#ibcon#enter sib2, iclass 32, count 0 2006.257.06:28:28.00#ibcon#flushed, iclass 32, count 0 2006.257.06:28:28.00#ibcon#about to write, iclass 32, count 0 2006.257.06:28:28.00#ibcon#wrote, iclass 32, count 0 2006.257.06:28:28.00#ibcon#about to read 3, iclass 32, count 0 2006.257.06:28:28.03#ibcon#read 3, iclass 32, count 0 2006.257.06:28:28.03#ibcon#about to read 4, iclass 32, count 0 2006.257.06:28:28.03#ibcon#read 4, iclass 32, count 0 2006.257.06:28:28.03#ibcon#about to read 5, iclass 32, count 0 2006.257.06:28:28.03#ibcon#read 5, iclass 32, count 0 2006.257.06:28:28.03#ibcon#about to read 6, iclass 32, count 0 2006.257.06:28:28.03#ibcon#read 6, iclass 32, count 0 2006.257.06:28:28.03#ibcon#end of sib2, iclass 32, count 0 2006.257.06:28:28.03#ibcon#*after write, iclass 32, count 0 2006.257.06:28:28.03#ibcon#*before return 0, iclass 32, count 0 2006.257.06:28:28.03#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:28.03#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:28.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:28:28.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:28:28.03$vck44/valo=3,564.99 2006.257.06:28:28.03#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.06:28:28.03#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.06:28:28.03#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:28.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:28:28.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:28:28.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:28:28.03#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:28:28.03#ibcon#first serial, iclass 34, count 0 2006.257.06:28:28.03#ibcon#enter sib2, iclass 34, count 0 2006.257.06:28:28.03#ibcon#flushed, iclass 34, count 0 2006.257.06:28:28.03#ibcon#about to write, iclass 34, count 0 2006.257.06:28:28.03#ibcon#wrote, iclass 34, count 0 2006.257.06:28:28.03#ibcon#about to read 3, iclass 34, count 0 2006.257.06:28:28.05#ibcon#read 3, iclass 34, count 0 2006.257.06:28:28.05#ibcon#about to read 4, iclass 34, count 0 2006.257.06:28:28.05#ibcon#read 4, iclass 34, count 0 2006.257.06:28:28.05#ibcon#about to read 5, iclass 34, count 0 2006.257.06:28:28.05#ibcon#read 5, iclass 34, count 0 2006.257.06:28:28.05#ibcon#about to read 6, iclass 34, count 0 2006.257.06:28:28.05#ibcon#read 6, iclass 34, count 0 2006.257.06:28:28.05#ibcon#end of sib2, iclass 34, count 0 2006.257.06:28:28.05#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:28:28.05#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:28:28.05#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:28:28.05#ibcon#*before write, iclass 34, count 0 2006.257.06:28:28.05#ibcon#enter sib2, iclass 34, count 0 2006.257.06:28:28.05#ibcon#flushed, iclass 34, count 0 2006.257.06:28:28.05#ibcon#about to write, iclass 34, count 0 2006.257.06:28:28.05#ibcon#wrote, iclass 34, count 0 2006.257.06:28:28.05#ibcon#about to read 3, iclass 34, count 0 2006.257.06:28:28.09#ibcon#read 3, iclass 34, count 0 2006.257.06:28:28.09#ibcon#about to read 4, iclass 34, count 0 2006.257.06:28:28.09#ibcon#read 4, iclass 34, count 0 2006.257.06:28:28.09#ibcon#about to read 5, iclass 34, count 0 2006.257.06:28:28.09#ibcon#read 5, iclass 34, count 0 2006.257.06:28:28.09#ibcon#about to read 6, iclass 34, count 0 2006.257.06:28:28.09#ibcon#read 6, iclass 34, count 0 2006.257.06:28:28.09#ibcon#end of sib2, iclass 34, count 0 2006.257.06:28:28.09#ibcon#*after write, iclass 34, count 0 2006.257.06:28:28.09#ibcon#*before return 0, iclass 34, count 0 2006.257.06:28:28.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:28:28.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:28:28.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:28:28.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:28:28.09$vck44/va=3,8 2006.257.06:28:28.09#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.06:28:28.09#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.06:28:28.09#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:28.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:28:28.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:28:28.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:28:28.15#ibcon#enter wrdev, iclass 36, count 2 2006.257.06:28:28.15#ibcon#first serial, iclass 36, count 2 2006.257.06:28:28.15#ibcon#enter sib2, iclass 36, count 2 2006.257.06:28:28.15#ibcon#flushed, iclass 36, count 2 2006.257.06:28:28.15#ibcon#about to write, iclass 36, count 2 2006.257.06:28:28.15#ibcon#wrote, iclass 36, count 2 2006.257.06:28:28.15#ibcon#about to read 3, iclass 36, count 2 2006.257.06:28:28.17#ibcon#read 3, iclass 36, count 2 2006.257.06:28:28.17#ibcon#about to read 4, iclass 36, count 2 2006.257.06:28:28.17#ibcon#read 4, iclass 36, count 2 2006.257.06:28:28.17#ibcon#about to read 5, iclass 36, count 2 2006.257.06:28:28.17#ibcon#read 5, iclass 36, count 2 2006.257.06:28:28.17#ibcon#about to read 6, iclass 36, count 2 2006.257.06:28:28.17#ibcon#read 6, iclass 36, count 2 2006.257.06:28:28.17#ibcon#end of sib2, iclass 36, count 2 2006.257.06:28:28.17#ibcon#*mode == 0, iclass 36, count 2 2006.257.06:28:28.17#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.06:28:28.17#ibcon#[25=AT03-08\r\n] 2006.257.06:28:28.17#ibcon#*before write, iclass 36, count 2 2006.257.06:28:28.17#ibcon#enter sib2, iclass 36, count 2 2006.257.06:28:28.17#ibcon#flushed, iclass 36, count 2 2006.257.06:28:28.17#ibcon#about to write, iclass 36, count 2 2006.257.06:28:28.17#ibcon#wrote, iclass 36, count 2 2006.257.06:28:28.17#ibcon#about to read 3, iclass 36, count 2 2006.257.06:28:28.20#ibcon#read 3, iclass 36, count 2 2006.257.06:28:28.20#ibcon#about to read 4, iclass 36, count 2 2006.257.06:28:28.20#ibcon#read 4, iclass 36, count 2 2006.257.06:28:28.20#ibcon#about to read 5, iclass 36, count 2 2006.257.06:28:28.20#ibcon#read 5, iclass 36, count 2 2006.257.06:28:28.20#ibcon#about to read 6, iclass 36, count 2 2006.257.06:28:28.20#ibcon#read 6, iclass 36, count 2 2006.257.06:28:28.20#ibcon#end of sib2, iclass 36, count 2 2006.257.06:28:28.20#ibcon#*after write, iclass 36, count 2 2006.257.06:28:28.20#ibcon#*before return 0, iclass 36, count 2 2006.257.06:28:28.20#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:28:28.20#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:28:28.20#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.06:28:28.20#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:28.20#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:28:28.32#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:28:28.32#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:28:28.32#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:28:28.32#ibcon#first serial, iclass 36, count 0 2006.257.06:28:28.32#ibcon#enter sib2, iclass 36, count 0 2006.257.06:28:28.32#ibcon#flushed, iclass 36, count 0 2006.257.06:28:28.32#ibcon#about to write, iclass 36, count 0 2006.257.06:28:28.32#ibcon#wrote, iclass 36, count 0 2006.257.06:28:28.32#ibcon#about to read 3, iclass 36, count 0 2006.257.06:28:28.34#ibcon#read 3, iclass 36, count 0 2006.257.06:28:28.34#ibcon#about to read 4, iclass 36, count 0 2006.257.06:28:28.34#ibcon#read 4, iclass 36, count 0 2006.257.06:28:28.34#ibcon#about to read 5, iclass 36, count 0 2006.257.06:28:28.34#ibcon#read 5, iclass 36, count 0 2006.257.06:28:28.34#ibcon#about to read 6, iclass 36, count 0 2006.257.06:28:28.34#ibcon#read 6, iclass 36, count 0 2006.257.06:28:28.34#ibcon#end of sib2, iclass 36, count 0 2006.257.06:28:28.34#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:28:28.34#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:28:28.34#ibcon#[25=USB\r\n] 2006.257.06:28:28.34#ibcon#*before write, iclass 36, count 0 2006.257.06:28:28.34#ibcon#enter sib2, iclass 36, count 0 2006.257.06:28:28.34#ibcon#flushed, iclass 36, count 0 2006.257.06:28:28.34#ibcon#about to write, iclass 36, count 0 2006.257.06:28:28.34#ibcon#wrote, iclass 36, count 0 2006.257.06:28:28.34#ibcon#about to read 3, iclass 36, count 0 2006.257.06:28:28.37#ibcon#read 3, iclass 36, count 0 2006.257.06:28:28.37#ibcon#about to read 4, iclass 36, count 0 2006.257.06:28:28.37#ibcon#read 4, iclass 36, count 0 2006.257.06:28:28.37#ibcon#about to read 5, iclass 36, count 0 2006.257.06:28:28.37#ibcon#read 5, iclass 36, count 0 2006.257.06:28:28.37#ibcon#about to read 6, iclass 36, count 0 2006.257.06:28:28.37#ibcon#read 6, iclass 36, count 0 2006.257.06:28:28.37#ibcon#end of sib2, iclass 36, count 0 2006.257.06:28:28.37#ibcon#*after write, iclass 36, count 0 2006.257.06:28:28.37#ibcon#*before return 0, iclass 36, count 0 2006.257.06:28:28.37#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:28:28.37#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:28:28.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:28:28.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:28:28.37$vck44/valo=4,624.99 2006.257.06:28:28.37#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.06:28:28.37#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.06:28:28.37#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:28.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:28.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:28.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:28.37#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:28:28.37#ibcon#first serial, iclass 38, count 0 2006.257.06:28:28.37#ibcon#enter sib2, iclass 38, count 0 2006.257.06:28:28.37#ibcon#flushed, iclass 38, count 0 2006.257.06:28:28.37#ibcon#about to write, iclass 38, count 0 2006.257.06:28:28.37#ibcon#wrote, iclass 38, count 0 2006.257.06:28:28.37#ibcon#about to read 3, iclass 38, count 0 2006.257.06:28:28.39#ibcon#read 3, iclass 38, count 0 2006.257.06:28:28.39#ibcon#about to read 4, iclass 38, count 0 2006.257.06:28:28.39#ibcon#read 4, iclass 38, count 0 2006.257.06:28:28.39#ibcon#about to read 5, iclass 38, count 0 2006.257.06:28:28.39#ibcon#read 5, iclass 38, count 0 2006.257.06:28:28.39#ibcon#about to read 6, iclass 38, count 0 2006.257.06:28:28.39#ibcon#read 6, iclass 38, count 0 2006.257.06:28:28.39#ibcon#end of sib2, iclass 38, count 0 2006.257.06:28:28.39#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:28:28.39#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:28:28.39#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:28:28.39#ibcon#*before write, iclass 38, count 0 2006.257.06:28:28.39#ibcon#enter sib2, iclass 38, count 0 2006.257.06:28:28.39#ibcon#flushed, iclass 38, count 0 2006.257.06:28:28.39#ibcon#about to write, iclass 38, count 0 2006.257.06:28:28.39#ibcon#wrote, iclass 38, count 0 2006.257.06:28:28.39#ibcon#about to read 3, iclass 38, count 0 2006.257.06:28:28.43#ibcon#read 3, iclass 38, count 0 2006.257.06:28:28.43#ibcon#about to read 4, iclass 38, count 0 2006.257.06:28:28.43#ibcon#read 4, iclass 38, count 0 2006.257.06:28:28.43#ibcon#about to read 5, iclass 38, count 0 2006.257.06:28:28.43#ibcon#read 5, iclass 38, count 0 2006.257.06:28:28.43#ibcon#about to read 6, iclass 38, count 0 2006.257.06:28:28.43#ibcon#read 6, iclass 38, count 0 2006.257.06:28:28.43#ibcon#end of sib2, iclass 38, count 0 2006.257.06:28:28.43#ibcon#*after write, iclass 38, count 0 2006.257.06:28:28.43#ibcon#*before return 0, iclass 38, count 0 2006.257.06:28:28.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:28.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:28.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:28:28.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:28:28.43$vck44/va=4,7 2006.257.06:28:28.43#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.06:28:28.43#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.06:28:28.43#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:28.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:28.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:28.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:28.49#ibcon#enter wrdev, iclass 40, count 2 2006.257.06:28:28.49#ibcon#first serial, iclass 40, count 2 2006.257.06:28:28.49#ibcon#enter sib2, iclass 40, count 2 2006.257.06:28:28.49#ibcon#flushed, iclass 40, count 2 2006.257.06:28:28.49#ibcon#about to write, iclass 40, count 2 2006.257.06:28:28.49#ibcon#wrote, iclass 40, count 2 2006.257.06:28:28.49#ibcon#about to read 3, iclass 40, count 2 2006.257.06:28:28.51#ibcon#read 3, iclass 40, count 2 2006.257.06:28:28.51#ibcon#about to read 4, iclass 40, count 2 2006.257.06:28:28.51#ibcon#read 4, iclass 40, count 2 2006.257.06:28:28.51#ibcon#about to read 5, iclass 40, count 2 2006.257.06:28:28.51#ibcon#read 5, iclass 40, count 2 2006.257.06:28:28.51#ibcon#about to read 6, iclass 40, count 2 2006.257.06:28:28.51#ibcon#read 6, iclass 40, count 2 2006.257.06:28:28.51#ibcon#end of sib2, iclass 40, count 2 2006.257.06:28:28.51#ibcon#*mode == 0, iclass 40, count 2 2006.257.06:28:28.51#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.06:28:28.51#ibcon#[25=AT04-07\r\n] 2006.257.06:28:28.51#ibcon#*before write, iclass 40, count 2 2006.257.06:28:28.51#ibcon#enter sib2, iclass 40, count 2 2006.257.06:28:28.51#ibcon#flushed, iclass 40, count 2 2006.257.06:28:28.51#ibcon#about to write, iclass 40, count 2 2006.257.06:28:28.51#ibcon#wrote, iclass 40, count 2 2006.257.06:28:28.51#ibcon#about to read 3, iclass 40, count 2 2006.257.06:28:28.54#ibcon#read 3, iclass 40, count 2 2006.257.06:28:28.54#ibcon#about to read 4, iclass 40, count 2 2006.257.06:28:28.54#ibcon#read 4, iclass 40, count 2 2006.257.06:28:28.54#ibcon#about to read 5, iclass 40, count 2 2006.257.06:28:28.54#ibcon#read 5, iclass 40, count 2 2006.257.06:28:28.54#ibcon#about to read 6, iclass 40, count 2 2006.257.06:28:28.54#ibcon#read 6, iclass 40, count 2 2006.257.06:28:28.54#ibcon#end of sib2, iclass 40, count 2 2006.257.06:28:28.54#ibcon#*after write, iclass 40, count 2 2006.257.06:28:28.54#ibcon#*before return 0, iclass 40, count 2 2006.257.06:28:28.54#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:28.54#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:28.54#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.06:28:28.54#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:28.54#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:28.66#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:28.66#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:28.66#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:28:28.66#ibcon#first serial, iclass 40, count 0 2006.257.06:28:28.66#ibcon#enter sib2, iclass 40, count 0 2006.257.06:28:28.66#ibcon#flushed, iclass 40, count 0 2006.257.06:28:28.66#ibcon#about to write, iclass 40, count 0 2006.257.06:28:28.66#ibcon#wrote, iclass 40, count 0 2006.257.06:28:28.66#ibcon#about to read 3, iclass 40, count 0 2006.257.06:28:28.68#ibcon#read 3, iclass 40, count 0 2006.257.06:28:28.68#ibcon#about to read 4, iclass 40, count 0 2006.257.06:28:28.68#ibcon#read 4, iclass 40, count 0 2006.257.06:28:28.68#ibcon#about to read 5, iclass 40, count 0 2006.257.06:28:28.68#ibcon#read 5, iclass 40, count 0 2006.257.06:28:28.68#ibcon#about to read 6, iclass 40, count 0 2006.257.06:28:28.68#ibcon#read 6, iclass 40, count 0 2006.257.06:28:28.68#ibcon#end of sib2, iclass 40, count 0 2006.257.06:28:28.68#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:28:28.68#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:28:28.68#ibcon#[25=USB\r\n] 2006.257.06:28:28.68#ibcon#*before write, iclass 40, count 0 2006.257.06:28:28.68#ibcon#enter sib2, iclass 40, count 0 2006.257.06:28:28.68#ibcon#flushed, iclass 40, count 0 2006.257.06:28:28.68#ibcon#about to write, iclass 40, count 0 2006.257.06:28:28.68#ibcon#wrote, iclass 40, count 0 2006.257.06:28:28.68#ibcon#about to read 3, iclass 40, count 0 2006.257.06:28:28.71#ibcon#read 3, iclass 40, count 0 2006.257.06:28:28.71#ibcon#about to read 4, iclass 40, count 0 2006.257.06:28:28.71#ibcon#read 4, iclass 40, count 0 2006.257.06:28:28.71#ibcon#about to read 5, iclass 40, count 0 2006.257.06:28:28.71#ibcon#read 5, iclass 40, count 0 2006.257.06:28:28.71#ibcon#about to read 6, iclass 40, count 0 2006.257.06:28:28.71#ibcon#read 6, iclass 40, count 0 2006.257.06:28:28.71#ibcon#end of sib2, iclass 40, count 0 2006.257.06:28:28.71#ibcon#*after write, iclass 40, count 0 2006.257.06:28:28.71#ibcon#*before return 0, iclass 40, count 0 2006.257.06:28:28.71#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:28.71#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:28.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:28:28.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:28:28.71$vck44/valo=5,734.99 2006.257.06:28:28.71#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.06:28:28.71#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.06:28:28.71#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:28.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:28.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:28.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:28.71#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:28:28.71#ibcon#first serial, iclass 4, count 0 2006.257.06:28:28.71#ibcon#enter sib2, iclass 4, count 0 2006.257.06:28:28.71#ibcon#flushed, iclass 4, count 0 2006.257.06:28:28.71#ibcon#about to write, iclass 4, count 0 2006.257.06:28:28.71#ibcon#wrote, iclass 4, count 0 2006.257.06:28:28.71#ibcon#about to read 3, iclass 4, count 0 2006.257.06:28:28.73#ibcon#read 3, iclass 4, count 0 2006.257.06:28:28.73#ibcon#about to read 4, iclass 4, count 0 2006.257.06:28:28.73#ibcon#read 4, iclass 4, count 0 2006.257.06:28:28.73#ibcon#about to read 5, iclass 4, count 0 2006.257.06:28:28.73#ibcon#read 5, iclass 4, count 0 2006.257.06:28:28.73#ibcon#about to read 6, iclass 4, count 0 2006.257.06:28:28.73#ibcon#read 6, iclass 4, count 0 2006.257.06:28:28.73#ibcon#end of sib2, iclass 4, count 0 2006.257.06:28:28.73#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:28:28.73#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:28:28.73#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:28:28.73#ibcon#*before write, iclass 4, count 0 2006.257.06:28:28.73#ibcon#enter sib2, iclass 4, count 0 2006.257.06:28:28.73#ibcon#flushed, iclass 4, count 0 2006.257.06:28:28.73#ibcon#about to write, iclass 4, count 0 2006.257.06:28:28.73#ibcon#wrote, iclass 4, count 0 2006.257.06:28:28.73#ibcon#about to read 3, iclass 4, count 0 2006.257.06:28:28.77#ibcon#read 3, iclass 4, count 0 2006.257.06:28:28.77#ibcon#about to read 4, iclass 4, count 0 2006.257.06:28:28.77#ibcon#read 4, iclass 4, count 0 2006.257.06:28:28.77#ibcon#about to read 5, iclass 4, count 0 2006.257.06:28:28.77#ibcon#read 5, iclass 4, count 0 2006.257.06:28:28.77#ibcon#about to read 6, iclass 4, count 0 2006.257.06:28:28.77#ibcon#read 6, iclass 4, count 0 2006.257.06:28:28.77#ibcon#end of sib2, iclass 4, count 0 2006.257.06:28:28.77#ibcon#*after write, iclass 4, count 0 2006.257.06:28:28.77#ibcon#*before return 0, iclass 4, count 0 2006.257.06:28:28.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:28.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:28.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:28:28.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:28:28.77$vck44/va=5,4 2006.257.06:28:28.77#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.06:28:28.77#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.06:28:28.77#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:28.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:28.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:28.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:28.83#ibcon#enter wrdev, iclass 6, count 2 2006.257.06:28:28.83#ibcon#first serial, iclass 6, count 2 2006.257.06:28:28.83#ibcon#enter sib2, iclass 6, count 2 2006.257.06:28:28.83#ibcon#flushed, iclass 6, count 2 2006.257.06:28:28.83#ibcon#about to write, iclass 6, count 2 2006.257.06:28:28.83#ibcon#wrote, iclass 6, count 2 2006.257.06:28:28.83#ibcon#about to read 3, iclass 6, count 2 2006.257.06:28:28.85#ibcon#read 3, iclass 6, count 2 2006.257.06:28:28.85#ibcon#about to read 4, iclass 6, count 2 2006.257.06:28:28.85#ibcon#read 4, iclass 6, count 2 2006.257.06:28:28.85#ibcon#about to read 5, iclass 6, count 2 2006.257.06:28:28.85#ibcon#read 5, iclass 6, count 2 2006.257.06:28:28.85#ibcon#about to read 6, iclass 6, count 2 2006.257.06:28:28.85#ibcon#read 6, iclass 6, count 2 2006.257.06:28:28.85#ibcon#end of sib2, iclass 6, count 2 2006.257.06:28:28.85#ibcon#*mode == 0, iclass 6, count 2 2006.257.06:28:28.85#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.06:28:28.85#ibcon#[25=AT05-04\r\n] 2006.257.06:28:28.85#ibcon#*before write, iclass 6, count 2 2006.257.06:28:28.85#ibcon#enter sib2, iclass 6, count 2 2006.257.06:28:28.85#ibcon#flushed, iclass 6, count 2 2006.257.06:28:28.85#ibcon#about to write, iclass 6, count 2 2006.257.06:28:28.85#ibcon#wrote, iclass 6, count 2 2006.257.06:28:28.85#ibcon#about to read 3, iclass 6, count 2 2006.257.06:28:28.88#ibcon#read 3, iclass 6, count 2 2006.257.06:28:28.88#ibcon#about to read 4, iclass 6, count 2 2006.257.06:28:28.88#ibcon#read 4, iclass 6, count 2 2006.257.06:28:28.88#ibcon#about to read 5, iclass 6, count 2 2006.257.06:28:28.88#ibcon#read 5, iclass 6, count 2 2006.257.06:28:28.88#ibcon#about to read 6, iclass 6, count 2 2006.257.06:28:28.88#ibcon#read 6, iclass 6, count 2 2006.257.06:28:28.88#ibcon#end of sib2, iclass 6, count 2 2006.257.06:28:28.88#ibcon#*after write, iclass 6, count 2 2006.257.06:28:28.88#ibcon#*before return 0, iclass 6, count 2 2006.257.06:28:28.88#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:28.88#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:28.88#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.06:28:28.88#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:28.88#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:29.00#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:29.00#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:29.00#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:28:29.00#ibcon#first serial, iclass 6, count 0 2006.257.06:28:29.00#ibcon#enter sib2, iclass 6, count 0 2006.257.06:28:29.00#ibcon#flushed, iclass 6, count 0 2006.257.06:28:29.00#ibcon#about to write, iclass 6, count 0 2006.257.06:28:29.00#ibcon#wrote, iclass 6, count 0 2006.257.06:28:29.00#ibcon#about to read 3, iclass 6, count 0 2006.257.06:28:29.02#ibcon#read 3, iclass 6, count 0 2006.257.06:28:29.02#ibcon#about to read 4, iclass 6, count 0 2006.257.06:28:29.02#ibcon#read 4, iclass 6, count 0 2006.257.06:28:29.02#ibcon#about to read 5, iclass 6, count 0 2006.257.06:28:29.02#ibcon#read 5, iclass 6, count 0 2006.257.06:28:29.02#ibcon#about to read 6, iclass 6, count 0 2006.257.06:28:29.02#ibcon#read 6, iclass 6, count 0 2006.257.06:28:29.02#ibcon#end of sib2, iclass 6, count 0 2006.257.06:28:29.02#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:28:29.02#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:28:29.02#ibcon#[25=USB\r\n] 2006.257.06:28:29.02#ibcon#*before write, iclass 6, count 0 2006.257.06:28:29.02#ibcon#enter sib2, iclass 6, count 0 2006.257.06:28:29.02#ibcon#flushed, iclass 6, count 0 2006.257.06:28:29.02#ibcon#about to write, iclass 6, count 0 2006.257.06:28:29.02#ibcon#wrote, iclass 6, count 0 2006.257.06:28:29.02#ibcon#about to read 3, iclass 6, count 0 2006.257.06:28:29.05#ibcon#read 3, iclass 6, count 0 2006.257.06:28:29.05#ibcon#about to read 4, iclass 6, count 0 2006.257.06:28:29.05#ibcon#read 4, iclass 6, count 0 2006.257.06:28:29.05#ibcon#about to read 5, iclass 6, count 0 2006.257.06:28:29.05#ibcon#read 5, iclass 6, count 0 2006.257.06:28:29.05#ibcon#about to read 6, iclass 6, count 0 2006.257.06:28:29.05#ibcon#read 6, iclass 6, count 0 2006.257.06:28:29.05#ibcon#end of sib2, iclass 6, count 0 2006.257.06:28:29.05#ibcon#*after write, iclass 6, count 0 2006.257.06:28:29.05#ibcon#*before return 0, iclass 6, count 0 2006.257.06:28:29.05#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:29.05#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:29.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:28:29.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:28:29.05$vck44/valo=6,814.99 2006.257.06:28:29.05#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.06:28:29.05#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.06:28:29.05#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:29.05#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:29.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:29.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:29.05#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:28:29.05#ibcon#first serial, iclass 10, count 0 2006.257.06:28:29.05#ibcon#enter sib2, iclass 10, count 0 2006.257.06:28:29.05#ibcon#flushed, iclass 10, count 0 2006.257.06:28:29.05#ibcon#about to write, iclass 10, count 0 2006.257.06:28:29.05#ibcon#wrote, iclass 10, count 0 2006.257.06:28:29.05#ibcon#about to read 3, iclass 10, count 0 2006.257.06:28:29.07#ibcon#read 3, iclass 10, count 0 2006.257.06:28:29.07#ibcon#about to read 4, iclass 10, count 0 2006.257.06:28:29.07#ibcon#read 4, iclass 10, count 0 2006.257.06:28:29.07#ibcon#about to read 5, iclass 10, count 0 2006.257.06:28:29.07#ibcon#read 5, iclass 10, count 0 2006.257.06:28:29.07#ibcon#about to read 6, iclass 10, count 0 2006.257.06:28:29.07#ibcon#read 6, iclass 10, count 0 2006.257.06:28:29.07#ibcon#end of sib2, iclass 10, count 0 2006.257.06:28:29.07#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:28:29.07#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:28:29.07#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:28:29.07#ibcon#*before write, iclass 10, count 0 2006.257.06:28:29.07#ibcon#enter sib2, iclass 10, count 0 2006.257.06:28:29.07#ibcon#flushed, iclass 10, count 0 2006.257.06:28:29.07#ibcon#about to write, iclass 10, count 0 2006.257.06:28:29.07#ibcon#wrote, iclass 10, count 0 2006.257.06:28:29.07#ibcon#about to read 3, iclass 10, count 0 2006.257.06:28:29.11#ibcon#read 3, iclass 10, count 0 2006.257.06:28:29.11#ibcon#about to read 4, iclass 10, count 0 2006.257.06:28:29.11#ibcon#read 4, iclass 10, count 0 2006.257.06:28:29.11#ibcon#about to read 5, iclass 10, count 0 2006.257.06:28:29.11#ibcon#read 5, iclass 10, count 0 2006.257.06:28:29.11#ibcon#about to read 6, iclass 10, count 0 2006.257.06:28:29.11#ibcon#read 6, iclass 10, count 0 2006.257.06:28:29.11#ibcon#end of sib2, iclass 10, count 0 2006.257.06:28:29.11#ibcon#*after write, iclass 10, count 0 2006.257.06:28:29.11#ibcon#*before return 0, iclass 10, count 0 2006.257.06:28:29.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:29.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:29.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:28:29.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:28:29.11$vck44/va=6,4 2006.257.06:28:29.11#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.06:28:29.11#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.06:28:29.11#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:29.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:29.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:29.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:29.17#ibcon#enter wrdev, iclass 12, count 2 2006.257.06:28:29.17#ibcon#first serial, iclass 12, count 2 2006.257.06:28:29.17#ibcon#enter sib2, iclass 12, count 2 2006.257.06:28:29.17#ibcon#flushed, iclass 12, count 2 2006.257.06:28:29.17#ibcon#about to write, iclass 12, count 2 2006.257.06:28:29.17#ibcon#wrote, iclass 12, count 2 2006.257.06:28:29.17#ibcon#about to read 3, iclass 12, count 2 2006.257.06:28:29.19#ibcon#read 3, iclass 12, count 2 2006.257.06:28:29.19#ibcon#about to read 4, iclass 12, count 2 2006.257.06:28:29.19#ibcon#read 4, iclass 12, count 2 2006.257.06:28:29.19#ibcon#about to read 5, iclass 12, count 2 2006.257.06:28:29.19#ibcon#read 5, iclass 12, count 2 2006.257.06:28:29.19#ibcon#about to read 6, iclass 12, count 2 2006.257.06:28:29.19#ibcon#read 6, iclass 12, count 2 2006.257.06:28:29.19#ibcon#end of sib2, iclass 12, count 2 2006.257.06:28:29.19#ibcon#*mode == 0, iclass 12, count 2 2006.257.06:28:29.19#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.06:28:29.19#ibcon#[25=AT06-04\r\n] 2006.257.06:28:29.19#ibcon#*before write, iclass 12, count 2 2006.257.06:28:29.19#ibcon#enter sib2, iclass 12, count 2 2006.257.06:28:29.19#ibcon#flushed, iclass 12, count 2 2006.257.06:28:29.19#ibcon#about to write, iclass 12, count 2 2006.257.06:28:29.19#ibcon#wrote, iclass 12, count 2 2006.257.06:28:29.19#ibcon#about to read 3, iclass 12, count 2 2006.257.06:28:29.22#ibcon#read 3, iclass 12, count 2 2006.257.06:28:29.22#ibcon#about to read 4, iclass 12, count 2 2006.257.06:28:29.22#ibcon#read 4, iclass 12, count 2 2006.257.06:28:29.22#ibcon#about to read 5, iclass 12, count 2 2006.257.06:28:29.22#ibcon#read 5, iclass 12, count 2 2006.257.06:28:29.22#ibcon#about to read 6, iclass 12, count 2 2006.257.06:28:29.22#ibcon#read 6, iclass 12, count 2 2006.257.06:28:29.22#ibcon#end of sib2, iclass 12, count 2 2006.257.06:28:29.22#ibcon#*after write, iclass 12, count 2 2006.257.06:28:29.22#ibcon#*before return 0, iclass 12, count 2 2006.257.06:28:29.22#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:29.22#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:29.22#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.06:28:29.22#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:29.22#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:29.34#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:29.34#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:29.34#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:28:29.34#ibcon#first serial, iclass 12, count 0 2006.257.06:28:29.34#ibcon#enter sib2, iclass 12, count 0 2006.257.06:28:29.34#ibcon#flushed, iclass 12, count 0 2006.257.06:28:29.34#ibcon#about to write, iclass 12, count 0 2006.257.06:28:29.34#ibcon#wrote, iclass 12, count 0 2006.257.06:28:29.34#ibcon#about to read 3, iclass 12, count 0 2006.257.06:28:29.36#ibcon#read 3, iclass 12, count 0 2006.257.06:28:29.36#ibcon#about to read 4, iclass 12, count 0 2006.257.06:28:29.36#ibcon#read 4, iclass 12, count 0 2006.257.06:28:29.36#ibcon#about to read 5, iclass 12, count 0 2006.257.06:28:29.36#ibcon#read 5, iclass 12, count 0 2006.257.06:28:29.36#ibcon#about to read 6, iclass 12, count 0 2006.257.06:28:29.36#ibcon#read 6, iclass 12, count 0 2006.257.06:28:29.36#ibcon#end of sib2, iclass 12, count 0 2006.257.06:28:29.36#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:28:29.36#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:28:29.36#ibcon#[25=USB\r\n] 2006.257.06:28:29.36#ibcon#*before write, iclass 12, count 0 2006.257.06:28:29.36#ibcon#enter sib2, iclass 12, count 0 2006.257.06:28:29.36#ibcon#flushed, iclass 12, count 0 2006.257.06:28:29.36#ibcon#about to write, iclass 12, count 0 2006.257.06:28:29.36#ibcon#wrote, iclass 12, count 0 2006.257.06:28:29.36#ibcon#about to read 3, iclass 12, count 0 2006.257.06:28:29.39#ibcon#read 3, iclass 12, count 0 2006.257.06:28:29.39#ibcon#about to read 4, iclass 12, count 0 2006.257.06:28:29.39#ibcon#read 4, iclass 12, count 0 2006.257.06:28:29.39#ibcon#about to read 5, iclass 12, count 0 2006.257.06:28:29.39#ibcon#read 5, iclass 12, count 0 2006.257.06:28:29.39#ibcon#about to read 6, iclass 12, count 0 2006.257.06:28:29.39#ibcon#read 6, iclass 12, count 0 2006.257.06:28:29.39#ibcon#end of sib2, iclass 12, count 0 2006.257.06:28:29.39#ibcon#*after write, iclass 12, count 0 2006.257.06:28:29.39#ibcon#*before return 0, iclass 12, count 0 2006.257.06:28:29.39#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:29.39#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:29.39#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:28:29.39#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:28:29.39$vck44/valo=7,864.99 2006.257.06:28:29.39#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.06:28:29.39#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.06:28:29.39#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:29.39#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:29.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:29.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:29.39#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:28:29.39#ibcon#first serial, iclass 14, count 0 2006.257.06:28:29.39#ibcon#enter sib2, iclass 14, count 0 2006.257.06:28:29.39#ibcon#flushed, iclass 14, count 0 2006.257.06:28:29.39#ibcon#about to write, iclass 14, count 0 2006.257.06:28:29.39#ibcon#wrote, iclass 14, count 0 2006.257.06:28:29.39#ibcon#about to read 3, iclass 14, count 0 2006.257.06:28:29.41#ibcon#read 3, iclass 14, count 0 2006.257.06:28:29.41#ibcon#about to read 4, iclass 14, count 0 2006.257.06:28:29.41#ibcon#read 4, iclass 14, count 0 2006.257.06:28:29.41#ibcon#about to read 5, iclass 14, count 0 2006.257.06:28:29.41#ibcon#read 5, iclass 14, count 0 2006.257.06:28:29.41#ibcon#about to read 6, iclass 14, count 0 2006.257.06:28:29.41#ibcon#read 6, iclass 14, count 0 2006.257.06:28:29.41#ibcon#end of sib2, iclass 14, count 0 2006.257.06:28:29.41#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:28:29.41#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:28:29.41#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:28:29.41#ibcon#*before write, iclass 14, count 0 2006.257.06:28:29.41#ibcon#enter sib2, iclass 14, count 0 2006.257.06:28:29.41#ibcon#flushed, iclass 14, count 0 2006.257.06:28:29.41#ibcon#about to write, iclass 14, count 0 2006.257.06:28:29.41#ibcon#wrote, iclass 14, count 0 2006.257.06:28:29.41#ibcon#about to read 3, iclass 14, count 0 2006.257.06:28:29.45#ibcon#read 3, iclass 14, count 0 2006.257.06:28:29.45#ibcon#about to read 4, iclass 14, count 0 2006.257.06:28:29.45#ibcon#read 4, iclass 14, count 0 2006.257.06:28:29.45#ibcon#about to read 5, iclass 14, count 0 2006.257.06:28:29.45#ibcon#read 5, iclass 14, count 0 2006.257.06:28:29.45#ibcon#about to read 6, iclass 14, count 0 2006.257.06:28:29.45#ibcon#read 6, iclass 14, count 0 2006.257.06:28:29.45#ibcon#end of sib2, iclass 14, count 0 2006.257.06:28:29.45#ibcon#*after write, iclass 14, count 0 2006.257.06:28:29.45#ibcon#*before return 0, iclass 14, count 0 2006.257.06:28:29.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:29.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:29.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:28:29.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:28:29.45$vck44/va=7,4 2006.257.06:28:29.45#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.06:28:29.45#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.06:28:29.45#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:29.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:29.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:29.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:29.51#ibcon#enter wrdev, iclass 16, count 2 2006.257.06:28:29.51#ibcon#first serial, iclass 16, count 2 2006.257.06:28:29.51#ibcon#enter sib2, iclass 16, count 2 2006.257.06:28:29.51#ibcon#flushed, iclass 16, count 2 2006.257.06:28:29.51#ibcon#about to write, iclass 16, count 2 2006.257.06:28:29.51#ibcon#wrote, iclass 16, count 2 2006.257.06:28:29.51#ibcon#about to read 3, iclass 16, count 2 2006.257.06:28:29.53#ibcon#read 3, iclass 16, count 2 2006.257.06:28:29.53#ibcon#about to read 4, iclass 16, count 2 2006.257.06:28:29.53#ibcon#read 4, iclass 16, count 2 2006.257.06:28:29.53#ibcon#about to read 5, iclass 16, count 2 2006.257.06:28:29.53#ibcon#read 5, iclass 16, count 2 2006.257.06:28:29.53#ibcon#about to read 6, iclass 16, count 2 2006.257.06:28:29.53#ibcon#read 6, iclass 16, count 2 2006.257.06:28:29.53#ibcon#end of sib2, iclass 16, count 2 2006.257.06:28:29.53#ibcon#*mode == 0, iclass 16, count 2 2006.257.06:28:29.53#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.06:28:29.53#ibcon#[25=AT07-04\r\n] 2006.257.06:28:29.53#ibcon#*before write, iclass 16, count 2 2006.257.06:28:29.53#ibcon#enter sib2, iclass 16, count 2 2006.257.06:28:29.53#ibcon#flushed, iclass 16, count 2 2006.257.06:28:29.53#ibcon#about to write, iclass 16, count 2 2006.257.06:28:29.53#ibcon#wrote, iclass 16, count 2 2006.257.06:28:29.53#ibcon#about to read 3, iclass 16, count 2 2006.257.06:28:29.56#ibcon#read 3, iclass 16, count 2 2006.257.06:28:29.56#ibcon#about to read 4, iclass 16, count 2 2006.257.06:28:29.56#ibcon#read 4, iclass 16, count 2 2006.257.06:28:29.56#ibcon#about to read 5, iclass 16, count 2 2006.257.06:28:29.56#ibcon#read 5, iclass 16, count 2 2006.257.06:28:29.56#ibcon#about to read 6, iclass 16, count 2 2006.257.06:28:29.56#ibcon#read 6, iclass 16, count 2 2006.257.06:28:29.56#ibcon#end of sib2, iclass 16, count 2 2006.257.06:28:29.56#ibcon#*after write, iclass 16, count 2 2006.257.06:28:29.56#ibcon#*before return 0, iclass 16, count 2 2006.257.06:28:29.56#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:29.56#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:29.56#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.06:28:29.56#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:29.56#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:29.68#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:29.68#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:29.68#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:28:29.68#ibcon#first serial, iclass 16, count 0 2006.257.06:28:29.68#ibcon#enter sib2, iclass 16, count 0 2006.257.06:28:29.68#ibcon#flushed, iclass 16, count 0 2006.257.06:28:29.68#ibcon#about to write, iclass 16, count 0 2006.257.06:28:29.68#ibcon#wrote, iclass 16, count 0 2006.257.06:28:29.68#ibcon#about to read 3, iclass 16, count 0 2006.257.06:28:29.70#ibcon#read 3, iclass 16, count 0 2006.257.06:28:29.70#ibcon#about to read 4, iclass 16, count 0 2006.257.06:28:29.70#ibcon#read 4, iclass 16, count 0 2006.257.06:28:29.70#ibcon#about to read 5, iclass 16, count 0 2006.257.06:28:29.70#ibcon#read 5, iclass 16, count 0 2006.257.06:28:29.70#ibcon#about to read 6, iclass 16, count 0 2006.257.06:28:29.70#ibcon#read 6, iclass 16, count 0 2006.257.06:28:29.70#ibcon#end of sib2, iclass 16, count 0 2006.257.06:28:29.70#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:28:29.70#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:28:29.70#ibcon#[25=USB\r\n] 2006.257.06:28:29.70#ibcon#*before write, iclass 16, count 0 2006.257.06:28:29.70#ibcon#enter sib2, iclass 16, count 0 2006.257.06:28:29.70#ibcon#flushed, iclass 16, count 0 2006.257.06:28:29.70#ibcon#about to write, iclass 16, count 0 2006.257.06:28:29.70#ibcon#wrote, iclass 16, count 0 2006.257.06:28:29.70#ibcon#about to read 3, iclass 16, count 0 2006.257.06:28:29.73#ibcon#read 3, iclass 16, count 0 2006.257.06:28:29.73#ibcon#about to read 4, iclass 16, count 0 2006.257.06:28:29.73#ibcon#read 4, iclass 16, count 0 2006.257.06:28:29.73#ibcon#about to read 5, iclass 16, count 0 2006.257.06:28:29.73#ibcon#read 5, iclass 16, count 0 2006.257.06:28:29.73#ibcon#about to read 6, iclass 16, count 0 2006.257.06:28:29.73#ibcon#read 6, iclass 16, count 0 2006.257.06:28:29.73#ibcon#end of sib2, iclass 16, count 0 2006.257.06:28:29.73#ibcon#*after write, iclass 16, count 0 2006.257.06:28:29.73#ibcon#*before return 0, iclass 16, count 0 2006.257.06:28:29.73#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:29.73#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:29.73#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:28:29.73#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:28:29.73$vck44/valo=8,884.99 2006.257.06:28:29.73#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.06:28:29.73#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.06:28:29.73#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:29.73#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:29.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:29.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:29.73#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:28:29.73#ibcon#first serial, iclass 18, count 0 2006.257.06:28:29.73#ibcon#enter sib2, iclass 18, count 0 2006.257.06:28:29.73#ibcon#flushed, iclass 18, count 0 2006.257.06:28:29.73#ibcon#about to write, iclass 18, count 0 2006.257.06:28:29.73#ibcon#wrote, iclass 18, count 0 2006.257.06:28:29.73#ibcon#about to read 3, iclass 18, count 0 2006.257.06:28:29.75#ibcon#read 3, iclass 18, count 0 2006.257.06:28:29.75#ibcon#about to read 4, iclass 18, count 0 2006.257.06:28:29.75#ibcon#read 4, iclass 18, count 0 2006.257.06:28:29.75#ibcon#about to read 5, iclass 18, count 0 2006.257.06:28:29.75#ibcon#read 5, iclass 18, count 0 2006.257.06:28:29.75#ibcon#about to read 6, iclass 18, count 0 2006.257.06:28:29.75#ibcon#read 6, iclass 18, count 0 2006.257.06:28:29.75#ibcon#end of sib2, iclass 18, count 0 2006.257.06:28:29.75#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:28:29.75#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:28:29.75#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:28:29.75#ibcon#*before write, iclass 18, count 0 2006.257.06:28:29.75#ibcon#enter sib2, iclass 18, count 0 2006.257.06:28:29.75#ibcon#flushed, iclass 18, count 0 2006.257.06:28:29.75#ibcon#about to write, iclass 18, count 0 2006.257.06:28:29.75#ibcon#wrote, iclass 18, count 0 2006.257.06:28:29.75#ibcon#about to read 3, iclass 18, count 0 2006.257.06:28:29.79#ibcon#read 3, iclass 18, count 0 2006.257.06:28:29.79#ibcon#about to read 4, iclass 18, count 0 2006.257.06:28:29.79#ibcon#read 4, iclass 18, count 0 2006.257.06:28:29.79#ibcon#about to read 5, iclass 18, count 0 2006.257.06:28:29.79#ibcon#read 5, iclass 18, count 0 2006.257.06:28:29.79#ibcon#about to read 6, iclass 18, count 0 2006.257.06:28:29.79#ibcon#read 6, iclass 18, count 0 2006.257.06:28:29.79#ibcon#end of sib2, iclass 18, count 0 2006.257.06:28:29.79#ibcon#*after write, iclass 18, count 0 2006.257.06:28:29.79#ibcon#*before return 0, iclass 18, count 0 2006.257.06:28:29.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:29.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:29.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:28:29.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:28:29.79$vck44/va=8,4 2006.257.06:28:29.79#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.06:28:29.79#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.06:28:29.79#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:29.79#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:29.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:29.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:29.85#ibcon#enter wrdev, iclass 20, count 2 2006.257.06:28:29.85#ibcon#first serial, iclass 20, count 2 2006.257.06:28:29.85#ibcon#enter sib2, iclass 20, count 2 2006.257.06:28:29.85#ibcon#flushed, iclass 20, count 2 2006.257.06:28:29.85#ibcon#about to write, iclass 20, count 2 2006.257.06:28:29.85#ibcon#wrote, iclass 20, count 2 2006.257.06:28:29.85#ibcon#about to read 3, iclass 20, count 2 2006.257.06:28:29.87#ibcon#read 3, iclass 20, count 2 2006.257.06:28:29.87#ibcon#about to read 4, iclass 20, count 2 2006.257.06:28:29.87#ibcon#read 4, iclass 20, count 2 2006.257.06:28:29.87#ibcon#about to read 5, iclass 20, count 2 2006.257.06:28:29.87#ibcon#read 5, iclass 20, count 2 2006.257.06:28:29.87#ibcon#about to read 6, iclass 20, count 2 2006.257.06:28:29.87#ibcon#read 6, iclass 20, count 2 2006.257.06:28:29.87#ibcon#end of sib2, iclass 20, count 2 2006.257.06:28:29.87#ibcon#*mode == 0, iclass 20, count 2 2006.257.06:28:29.87#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.06:28:29.87#ibcon#[25=AT08-04\r\n] 2006.257.06:28:29.87#ibcon#*before write, iclass 20, count 2 2006.257.06:28:29.87#ibcon#enter sib2, iclass 20, count 2 2006.257.06:28:29.87#ibcon#flushed, iclass 20, count 2 2006.257.06:28:29.87#ibcon#about to write, iclass 20, count 2 2006.257.06:28:29.87#ibcon#wrote, iclass 20, count 2 2006.257.06:28:29.87#ibcon#about to read 3, iclass 20, count 2 2006.257.06:28:29.90#ibcon#read 3, iclass 20, count 2 2006.257.06:28:29.90#ibcon#about to read 4, iclass 20, count 2 2006.257.06:28:29.90#ibcon#read 4, iclass 20, count 2 2006.257.06:28:29.90#ibcon#about to read 5, iclass 20, count 2 2006.257.06:28:29.90#ibcon#read 5, iclass 20, count 2 2006.257.06:28:29.90#ibcon#about to read 6, iclass 20, count 2 2006.257.06:28:29.90#ibcon#read 6, iclass 20, count 2 2006.257.06:28:29.90#ibcon#end of sib2, iclass 20, count 2 2006.257.06:28:29.90#ibcon#*after write, iclass 20, count 2 2006.257.06:28:29.90#ibcon#*before return 0, iclass 20, count 2 2006.257.06:28:29.90#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:29.90#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:29.90#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.06:28:29.90#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:29.90#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:30.02#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:30.02#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:30.02#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:28:30.02#ibcon#first serial, iclass 20, count 0 2006.257.06:28:30.02#ibcon#enter sib2, iclass 20, count 0 2006.257.06:28:30.02#ibcon#flushed, iclass 20, count 0 2006.257.06:28:30.02#ibcon#about to write, iclass 20, count 0 2006.257.06:28:30.02#ibcon#wrote, iclass 20, count 0 2006.257.06:28:30.02#ibcon#about to read 3, iclass 20, count 0 2006.257.06:28:30.04#ibcon#read 3, iclass 20, count 0 2006.257.06:28:30.04#ibcon#about to read 4, iclass 20, count 0 2006.257.06:28:30.04#ibcon#read 4, iclass 20, count 0 2006.257.06:28:30.04#ibcon#about to read 5, iclass 20, count 0 2006.257.06:28:30.04#ibcon#read 5, iclass 20, count 0 2006.257.06:28:30.04#ibcon#about to read 6, iclass 20, count 0 2006.257.06:28:30.04#ibcon#read 6, iclass 20, count 0 2006.257.06:28:30.04#ibcon#end of sib2, iclass 20, count 0 2006.257.06:28:30.04#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:28:30.04#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:28:30.04#ibcon#[25=USB\r\n] 2006.257.06:28:30.04#ibcon#*before write, iclass 20, count 0 2006.257.06:28:30.04#ibcon#enter sib2, iclass 20, count 0 2006.257.06:28:30.04#ibcon#flushed, iclass 20, count 0 2006.257.06:28:30.04#ibcon#about to write, iclass 20, count 0 2006.257.06:28:30.04#ibcon#wrote, iclass 20, count 0 2006.257.06:28:30.04#ibcon#about to read 3, iclass 20, count 0 2006.257.06:28:30.07#ibcon#read 3, iclass 20, count 0 2006.257.06:28:30.07#ibcon#about to read 4, iclass 20, count 0 2006.257.06:28:30.07#ibcon#read 4, iclass 20, count 0 2006.257.06:28:30.07#ibcon#about to read 5, iclass 20, count 0 2006.257.06:28:30.07#ibcon#read 5, iclass 20, count 0 2006.257.06:28:30.07#ibcon#about to read 6, iclass 20, count 0 2006.257.06:28:30.07#ibcon#read 6, iclass 20, count 0 2006.257.06:28:30.07#ibcon#end of sib2, iclass 20, count 0 2006.257.06:28:30.07#ibcon#*after write, iclass 20, count 0 2006.257.06:28:30.07#ibcon#*before return 0, iclass 20, count 0 2006.257.06:28:30.07#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:30.07#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:30.07#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:28:30.07#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:28:30.07$vck44/vblo=1,629.99 2006.257.06:28:30.07#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.06:28:30.07#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.06:28:30.07#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:30.07#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:30.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:30.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:30.07#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:28:30.07#ibcon#first serial, iclass 22, count 0 2006.257.06:28:30.07#ibcon#enter sib2, iclass 22, count 0 2006.257.06:28:30.07#ibcon#flushed, iclass 22, count 0 2006.257.06:28:30.07#ibcon#about to write, iclass 22, count 0 2006.257.06:28:30.07#ibcon#wrote, iclass 22, count 0 2006.257.06:28:30.07#ibcon#about to read 3, iclass 22, count 0 2006.257.06:28:30.09#ibcon#read 3, iclass 22, count 0 2006.257.06:28:30.09#ibcon#about to read 4, iclass 22, count 0 2006.257.06:28:30.09#ibcon#read 4, iclass 22, count 0 2006.257.06:28:30.09#ibcon#about to read 5, iclass 22, count 0 2006.257.06:28:30.09#ibcon#read 5, iclass 22, count 0 2006.257.06:28:30.09#ibcon#about to read 6, iclass 22, count 0 2006.257.06:28:30.09#ibcon#read 6, iclass 22, count 0 2006.257.06:28:30.09#ibcon#end of sib2, iclass 22, count 0 2006.257.06:28:30.09#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:28:30.09#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:28:30.09#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:28:30.09#ibcon#*before write, iclass 22, count 0 2006.257.06:28:30.09#ibcon#enter sib2, iclass 22, count 0 2006.257.06:28:30.09#ibcon#flushed, iclass 22, count 0 2006.257.06:28:30.09#ibcon#about to write, iclass 22, count 0 2006.257.06:28:30.09#ibcon#wrote, iclass 22, count 0 2006.257.06:28:30.09#ibcon#about to read 3, iclass 22, count 0 2006.257.06:28:30.13#ibcon#read 3, iclass 22, count 0 2006.257.06:28:30.13#ibcon#about to read 4, iclass 22, count 0 2006.257.06:28:30.13#ibcon#read 4, iclass 22, count 0 2006.257.06:28:30.13#ibcon#about to read 5, iclass 22, count 0 2006.257.06:28:30.13#ibcon#read 5, iclass 22, count 0 2006.257.06:28:30.13#ibcon#about to read 6, iclass 22, count 0 2006.257.06:28:30.13#ibcon#read 6, iclass 22, count 0 2006.257.06:28:30.13#ibcon#end of sib2, iclass 22, count 0 2006.257.06:28:30.13#ibcon#*after write, iclass 22, count 0 2006.257.06:28:30.13#ibcon#*before return 0, iclass 22, count 0 2006.257.06:28:30.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:30.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:30.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:28:30.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:28:30.13$vck44/vb=1,4 2006.257.06:28:30.13#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.06:28:30.13#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.06:28:30.13#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:30.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:28:30.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:28:30.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:28:30.13#ibcon#enter wrdev, iclass 24, count 2 2006.257.06:28:30.13#ibcon#first serial, iclass 24, count 2 2006.257.06:28:30.13#ibcon#enter sib2, iclass 24, count 2 2006.257.06:28:30.13#ibcon#flushed, iclass 24, count 2 2006.257.06:28:30.13#ibcon#about to write, iclass 24, count 2 2006.257.06:28:30.13#ibcon#wrote, iclass 24, count 2 2006.257.06:28:30.13#ibcon#about to read 3, iclass 24, count 2 2006.257.06:28:30.15#ibcon#read 3, iclass 24, count 2 2006.257.06:28:30.15#ibcon#about to read 4, iclass 24, count 2 2006.257.06:28:30.15#ibcon#read 4, iclass 24, count 2 2006.257.06:28:30.15#ibcon#about to read 5, iclass 24, count 2 2006.257.06:28:30.15#ibcon#read 5, iclass 24, count 2 2006.257.06:28:30.15#ibcon#about to read 6, iclass 24, count 2 2006.257.06:28:30.15#ibcon#read 6, iclass 24, count 2 2006.257.06:28:30.15#ibcon#end of sib2, iclass 24, count 2 2006.257.06:28:30.15#ibcon#*mode == 0, iclass 24, count 2 2006.257.06:28:30.15#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.06:28:30.15#ibcon#[27=AT01-04\r\n] 2006.257.06:28:30.15#ibcon#*before write, iclass 24, count 2 2006.257.06:28:30.15#ibcon#enter sib2, iclass 24, count 2 2006.257.06:28:30.15#ibcon#flushed, iclass 24, count 2 2006.257.06:28:30.15#ibcon#about to write, iclass 24, count 2 2006.257.06:28:30.15#ibcon#wrote, iclass 24, count 2 2006.257.06:28:30.15#ibcon#about to read 3, iclass 24, count 2 2006.257.06:28:30.18#ibcon#read 3, iclass 24, count 2 2006.257.06:28:30.18#ibcon#about to read 4, iclass 24, count 2 2006.257.06:28:30.18#ibcon#read 4, iclass 24, count 2 2006.257.06:28:30.18#ibcon#about to read 5, iclass 24, count 2 2006.257.06:28:30.18#ibcon#read 5, iclass 24, count 2 2006.257.06:28:30.18#ibcon#about to read 6, iclass 24, count 2 2006.257.06:28:30.18#ibcon#read 6, iclass 24, count 2 2006.257.06:28:30.18#ibcon#end of sib2, iclass 24, count 2 2006.257.06:28:30.18#ibcon#*after write, iclass 24, count 2 2006.257.06:28:30.18#ibcon#*before return 0, iclass 24, count 2 2006.257.06:28:30.18#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:28:30.18#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:28:30.18#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.06:28:30.18#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:30.18#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:28:30.30#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:28:30.30#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:28:30.30#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:28:30.30#ibcon#first serial, iclass 24, count 0 2006.257.06:28:30.30#ibcon#enter sib2, iclass 24, count 0 2006.257.06:28:30.30#ibcon#flushed, iclass 24, count 0 2006.257.06:28:30.30#ibcon#about to write, iclass 24, count 0 2006.257.06:28:30.30#ibcon#wrote, iclass 24, count 0 2006.257.06:28:30.30#ibcon#about to read 3, iclass 24, count 0 2006.257.06:28:30.32#ibcon#read 3, iclass 24, count 0 2006.257.06:28:30.32#ibcon#about to read 4, iclass 24, count 0 2006.257.06:28:30.32#ibcon#read 4, iclass 24, count 0 2006.257.06:28:30.32#ibcon#about to read 5, iclass 24, count 0 2006.257.06:28:30.32#ibcon#read 5, iclass 24, count 0 2006.257.06:28:30.32#ibcon#about to read 6, iclass 24, count 0 2006.257.06:28:30.32#ibcon#read 6, iclass 24, count 0 2006.257.06:28:30.32#ibcon#end of sib2, iclass 24, count 0 2006.257.06:28:30.32#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:28:30.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:28:30.32#ibcon#[27=USB\r\n] 2006.257.06:28:30.32#ibcon#*before write, iclass 24, count 0 2006.257.06:28:30.32#ibcon#enter sib2, iclass 24, count 0 2006.257.06:28:30.32#ibcon#flushed, iclass 24, count 0 2006.257.06:28:30.32#ibcon#about to write, iclass 24, count 0 2006.257.06:28:30.32#ibcon#wrote, iclass 24, count 0 2006.257.06:28:30.32#ibcon#about to read 3, iclass 24, count 0 2006.257.06:28:30.35#ibcon#read 3, iclass 24, count 0 2006.257.06:28:30.35#ibcon#about to read 4, iclass 24, count 0 2006.257.06:28:30.35#ibcon#read 4, iclass 24, count 0 2006.257.06:28:30.35#ibcon#about to read 5, iclass 24, count 0 2006.257.06:28:30.35#ibcon#read 5, iclass 24, count 0 2006.257.06:28:30.35#ibcon#about to read 6, iclass 24, count 0 2006.257.06:28:30.35#ibcon#read 6, iclass 24, count 0 2006.257.06:28:30.35#ibcon#end of sib2, iclass 24, count 0 2006.257.06:28:30.35#ibcon#*after write, iclass 24, count 0 2006.257.06:28:30.35#ibcon#*before return 0, iclass 24, count 0 2006.257.06:28:30.35#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:28:30.35#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:28:30.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:28:30.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:28:30.35$vck44/vblo=2,634.99 2006.257.06:28:30.35#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.06:28:30.35#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.06:28:30.35#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:30.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:30.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:30.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:30.35#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:28:30.35#ibcon#first serial, iclass 26, count 0 2006.257.06:28:30.35#ibcon#enter sib2, iclass 26, count 0 2006.257.06:28:30.35#ibcon#flushed, iclass 26, count 0 2006.257.06:28:30.35#ibcon#about to write, iclass 26, count 0 2006.257.06:28:30.35#ibcon#wrote, iclass 26, count 0 2006.257.06:28:30.35#ibcon#about to read 3, iclass 26, count 0 2006.257.06:28:30.37#ibcon#read 3, iclass 26, count 0 2006.257.06:28:30.37#ibcon#about to read 4, iclass 26, count 0 2006.257.06:28:30.37#ibcon#read 4, iclass 26, count 0 2006.257.06:28:30.37#ibcon#about to read 5, iclass 26, count 0 2006.257.06:28:30.37#ibcon#read 5, iclass 26, count 0 2006.257.06:28:30.37#ibcon#about to read 6, iclass 26, count 0 2006.257.06:28:30.37#ibcon#read 6, iclass 26, count 0 2006.257.06:28:30.37#ibcon#end of sib2, iclass 26, count 0 2006.257.06:28:30.37#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:28:30.37#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:28:30.37#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:28:30.37#ibcon#*before write, iclass 26, count 0 2006.257.06:28:30.37#ibcon#enter sib2, iclass 26, count 0 2006.257.06:28:30.37#ibcon#flushed, iclass 26, count 0 2006.257.06:28:30.37#ibcon#about to write, iclass 26, count 0 2006.257.06:28:30.37#ibcon#wrote, iclass 26, count 0 2006.257.06:28:30.37#ibcon#about to read 3, iclass 26, count 0 2006.257.06:28:30.41#ibcon#read 3, iclass 26, count 0 2006.257.06:28:30.41#ibcon#about to read 4, iclass 26, count 0 2006.257.06:28:30.41#ibcon#read 4, iclass 26, count 0 2006.257.06:28:30.41#ibcon#about to read 5, iclass 26, count 0 2006.257.06:28:30.41#ibcon#read 5, iclass 26, count 0 2006.257.06:28:30.41#ibcon#about to read 6, iclass 26, count 0 2006.257.06:28:30.41#ibcon#read 6, iclass 26, count 0 2006.257.06:28:30.41#ibcon#end of sib2, iclass 26, count 0 2006.257.06:28:30.41#ibcon#*after write, iclass 26, count 0 2006.257.06:28:30.41#ibcon#*before return 0, iclass 26, count 0 2006.257.06:28:30.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:30.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:28:30.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:28:30.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:28:30.41$vck44/vb=2,5 2006.257.06:28:30.41#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.06:28:30.41#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.06:28:30.41#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:30.41#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:30.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:30.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:30.47#ibcon#enter wrdev, iclass 28, count 2 2006.257.06:28:30.47#ibcon#first serial, iclass 28, count 2 2006.257.06:28:30.47#ibcon#enter sib2, iclass 28, count 2 2006.257.06:28:30.47#ibcon#flushed, iclass 28, count 2 2006.257.06:28:30.47#ibcon#about to write, iclass 28, count 2 2006.257.06:28:30.47#ibcon#wrote, iclass 28, count 2 2006.257.06:28:30.47#ibcon#about to read 3, iclass 28, count 2 2006.257.06:28:30.49#ibcon#read 3, iclass 28, count 2 2006.257.06:28:30.49#ibcon#about to read 4, iclass 28, count 2 2006.257.06:28:30.49#ibcon#read 4, iclass 28, count 2 2006.257.06:28:30.49#ibcon#about to read 5, iclass 28, count 2 2006.257.06:28:30.49#ibcon#read 5, iclass 28, count 2 2006.257.06:28:30.49#ibcon#about to read 6, iclass 28, count 2 2006.257.06:28:30.49#ibcon#read 6, iclass 28, count 2 2006.257.06:28:30.49#ibcon#end of sib2, iclass 28, count 2 2006.257.06:28:30.49#ibcon#*mode == 0, iclass 28, count 2 2006.257.06:28:30.49#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.06:28:30.49#ibcon#[27=AT02-05\r\n] 2006.257.06:28:30.49#ibcon#*before write, iclass 28, count 2 2006.257.06:28:30.49#ibcon#enter sib2, iclass 28, count 2 2006.257.06:28:30.49#ibcon#flushed, iclass 28, count 2 2006.257.06:28:30.49#ibcon#about to write, iclass 28, count 2 2006.257.06:28:30.49#ibcon#wrote, iclass 28, count 2 2006.257.06:28:30.49#ibcon#about to read 3, iclass 28, count 2 2006.257.06:28:30.52#ibcon#read 3, iclass 28, count 2 2006.257.06:28:30.52#ibcon#about to read 4, iclass 28, count 2 2006.257.06:28:30.52#ibcon#read 4, iclass 28, count 2 2006.257.06:28:30.52#ibcon#about to read 5, iclass 28, count 2 2006.257.06:28:30.52#ibcon#read 5, iclass 28, count 2 2006.257.06:28:30.52#ibcon#about to read 6, iclass 28, count 2 2006.257.06:28:30.52#ibcon#read 6, iclass 28, count 2 2006.257.06:28:30.52#ibcon#end of sib2, iclass 28, count 2 2006.257.06:28:30.52#ibcon#*after write, iclass 28, count 2 2006.257.06:28:30.52#ibcon#*before return 0, iclass 28, count 2 2006.257.06:28:30.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:30.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:28:30.52#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.06:28:30.52#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:30.52#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:30.64#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:30.64#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:30.64#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:28:30.64#ibcon#first serial, iclass 28, count 0 2006.257.06:28:30.64#ibcon#enter sib2, iclass 28, count 0 2006.257.06:28:30.64#ibcon#flushed, iclass 28, count 0 2006.257.06:28:30.64#ibcon#about to write, iclass 28, count 0 2006.257.06:28:30.64#ibcon#wrote, iclass 28, count 0 2006.257.06:28:30.64#ibcon#about to read 3, iclass 28, count 0 2006.257.06:28:30.66#ibcon#read 3, iclass 28, count 0 2006.257.06:28:30.66#ibcon#about to read 4, iclass 28, count 0 2006.257.06:28:30.66#ibcon#read 4, iclass 28, count 0 2006.257.06:28:30.66#ibcon#about to read 5, iclass 28, count 0 2006.257.06:28:30.66#ibcon#read 5, iclass 28, count 0 2006.257.06:28:30.66#ibcon#about to read 6, iclass 28, count 0 2006.257.06:28:30.66#ibcon#read 6, iclass 28, count 0 2006.257.06:28:30.66#ibcon#end of sib2, iclass 28, count 0 2006.257.06:28:30.66#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:28:30.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:28:30.66#ibcon#[27=USB\r\n] 2006.257.06:28:30.66#ibcon#*before write, iclass 28, count 0 2006.257.06:28:30.66#ibcon#enter sib2, iclass 28, count 0 2006.257.06:28:30.66#ibcon#flushed, iclass 28, count 0 2006.257.06:28:30.66#ibcon#about to write, iclass 28, count 0 2006.257.06:28:30.66#ibcon#wrote, iclass 28, count 0 2006.257.06:28:30.66#ibcon#about to read 3, iclass 28, count 0 2006.257.06:28:30.69#ibcon#read 3, iclass 28, count 0 2006.257.06:28:30.69#ibcon#about to read 4, iclass 28, count 0 2006.257.06:28:30.69#ibcon#read 4, iclass 28, count 0 2006.257.06:28:30.69#ibcon#about to read 5, iclass 28, count 0 2006.257.06:28:30.69#ibcon#read 5, iclass 28, count 0 2006.257.06:28:30.69#ibcon#about to read 6, iclass 28, count 0 2006.257.06:28:30.69#ibcon#read 6, iclass 28, count 0 2006.257.06:28:30.69#ibcon#end of sib2, iclass 28, count 0 2006.257.06:28:30.69#ibcon#*after write, iclass 28, count 0 2006.257.06:28:30.69#ibcon#*before return 0, iclass 28, count 0 2006.257.06:28:30.69#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:30.69#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:28:30.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:28:30.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:28:30.69$vck44/vblo=3,649.99 2006.257.06:28:30.69#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.06:28:30.69#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.06:28:30.69#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:30.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:30.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:30.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:30.69#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:28:30.69#ibcon#first serial, iclass 30, count 0 2006.257.06:28:30.69#ibcon#enter sib2, iclass 30, count 0 2006.257.06:28:30.69#ibcon#flushed, iclass 30, count 0 2006.257.06:28:30.69#ibcon#about to write, iclass 30, count 0 2006.257.06:28:30.69#ibcon#wrote, iclass 30, count 0 2006.257.06:28:30.69#ibcon#about to read 3, iclass 30, count 0 2006.257.06:28:30.71#ibcon#read 3, iclass 30, count 0 2006.257.06:28:30.71#ibcon#about to read 4, iclass 30, count 0 2006.257.06:28:30.71#ibcon#read 4, iclass 30, count 0 2006.257.06:28:30.71#ibcon#about to read 5, iclass 30, count 0 2006.257.06:28:30.71#ibcon#read 5, iclass 30, count 0 2006.257.06:28:30.71#ibcon#about to read 6, iclass 30, count 0 2006.257.06:28:30.71#ibcon#read 6, iclass 30, count 0 2006.257.06:28:30.71#ibcon#end of sib2, iclass 30, count 0 2006.257.06:28:30.71#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:28:30.71#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:28:30.71#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:28:30.71#ibcon#*before write, iclass 30, count 0 2006.257.06:28:30.71#ibcon#enter sib2, iclass 30, count 0 2006.257.06:28:30.71#ibcon#flushed, iclass 30, count 0 2006.257.06:28:30.71#ibcon#about to write, iclass 30, count 0 2006.257.06:28:30.71#ibcon#wrote, iclass 30, count 0 2006.257.06:28:30.71#ibcon#about to read 3, iclass 30, count 0 2006.257.06:28:30.75#ibcon#read 3, iclass 30, count 0 2006.257.06:28:30.75#ibcon#about to read 4, iclass 30, count 0 2006.257.06:28:30.75#ibcon#read 4, iclass 30, count 0 2006.257.06:28:30.75#ibcon#about to read 5, iclass 30, count 0 2006.257.06:28:30.75#ibcon#read 5, iclass 30, count 0 2006.257.06:28:30.75#ibcon#about to read 6, iclass 30, count 0 2006.257.06:28:30.75#ibcon#read 6, iclass 30, count 0 2006.257.06:28:30.75#ibcon#end of sib2, iclass 30, count 0 2006.257.06:28:30.75#ibcon#*after write, iclass 30, count 0 2006.257.06:28:30.75#ibcon#*before return 0, iclass 30, count 0 2006.257.06:28:30.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:30.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:28:30.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:28:30.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:28:30.75$vck44/vb=3,4 2006.257.06:28:30.75#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.06:28:30.75#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.06:28:30.75#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:30.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:30.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:30.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:30.81#ibcon#enter wrdev, iclass 32, count 2 2006.257.06:28:30.81#ibcon#first serial, iclass 32, count 2 2006.257.06:28:30.81#ibcon#enter sib2, iclass 32, count 2 2006.257.06:28:30.81#ibcon#flushed, iclass 32, count 2 2006.257.06:28:30.81#ibcon#about to write, iclass 32, count 2 2006.257.06:28:30.81#ibcon#wrote, iclass 32, count 2 2006.257.06:28:30.81#ibcon#about to read 3, iclass 32, count 2 2006.257.06:28:30.83#ibcon#read 3, iclass 32, count 2 2006.257.06:28:30.83#ibcon#about to read 4, iclass 32, count 2 2006.257.06:28:30.83#ibcon#read 4, iclass 32, count 2 2006.257.06:28:30.83#ibcon#about to read 5, iclass 32, count 2 2006.257.06:28:30.83#ibcon#read 5, iclass 32, count 2 2006.257.06:28:30.83#ibcon#about to read 6, iclass 32, count 2 2006.257.06:28:30.83#ibcon#read 6, iclass 32, count 2 2006.257.06:28:30.83#ibcon#end of sib2, iclass 32, count 2 2006.257.06:28:30.83#ibcon#*mode == 0, iclass 32, count 2 2006.257.06:28:30.83#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.06:28:30.83#ibcon#[27=AT03-04\r\n] 2006.257.06:28:30.83#ibcon#*before write, iclass 32, count 2 2006.257.06:28:30.83#ibcon#enter sib2, iclass 32, count 2 2006.257.06:28:30.83#ibcon#flushed, iclass 32, count 2 2006.257.06:28:30.83#ibcon#about to write, iclass 32, count 2 2006.257.06:28:30.83#ibcon#wrote, iclass 32, count 2 2006.257.06:28:30.83#ibcon#about to read 3, iclass 32, count 2 2006.257.06:28:30.86#ibcon#read 3, iclass 32, count 2 2006.257.06:28:30.86#ibcon#about to read 4, iclass 32, count 2 2006.257.06:28:30.86#ibcon#read 4, iclass 32, count 2 2006.257.06:28:30.86#ibcon#about to read 5, iclass 32, count 2 2006.257.06:28:30.86#ibcon#read 5, iclass 32, count 2 2006.257.06:28:30.86#ibcon#about to read 6, iclass 32, count 2 2006.257.06:28:30.86#ibcon#read 6, iclass 32, count 2 2006.257.06:28:30.86#ibcon#end of sib2, iclass 32, count 2 2006.257.06:28:30.86#ibcon#*after write, iclass 32, count 2 2006.257.06:28:30.86#ibcon#*before return 0, iclass 32, count 2 2006.257.06:28:30.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:30.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:28:30.86#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.06:28:30.86#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:30.86#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:30.94#abcon#<5=/15 0.8 2.8 20.49 891012.2\r\n> 2006.257.06:28:30.96#abcon#{5=INTERFACE CLEAR} 2006.257.06:28:30.98#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:30.98#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:30.98#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:28:30.98#ibcon#first serial, iclass 32, count 0 2006.257.06:28:30.98#ibcon#enter sib2, iclass 32, count 0 2006.257.06:28:30.98#ibcon#flushed, iclass 32, count 0 2006.257.06:28:30.98#ibcon#about to write, iclass 32, count 0 2006.257.06:28:30.98#ibcon#wrote, iclass 32, count 0 2006.257.06:28:30.98#ibcon#about to read 3, iclass 32, count 0 2006.257.06:28:31.00#ibcon#read 3, iclass 32, count 0 2006.257.06:28:31.00#ibcon#about to read 4, iclass 32, count 0 2006.257.06:28:31.00#ibcon#read 4, iclass 32, count 0 2006.257.06:28:31.00#ibcon#about to read 5, iclass 32, count 0 2006.257.06:28:31.00#ibcon#read 5, iclass 32, count 0 2006.257.06:28:31.00#ibcon#about to read 6, iclass 32, count 0 2006.257.06:28:31.00#ibcon#read 6, iclass 32, count 0 2006.257.06:28:31.00#ibcon#end of sib2, iclass 32, count 0 2006.257.06:28:31.00#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:28:31.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:28:31.00#ibcon#[27=USB\r\n] 2006.257.06:28:31.00#ibcon#*before write, iclass 32, count 0 2006.257.06:28:31.00#ibcon#enter sib2, iclass 32, count 0 2006.257.06:28:31.00#ibcon#flushed, iclass 32, count 0 2006.257.06:28:31.00#ibcon#about to write, iclass 32, count 0 2006.257.06:28:31.00#ibcon#wrote, iclass 32, count 0 2006.257.06:28:31.00#ibcon#about to read 3, iclass 32, count 0 2006.257.06:28:31.02#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:28:31.03#ibcon#read 3, iclass 32, count 0 2006.257.06:28:31.03#ibcon#about to read 4, iclass 32, count 0 2006.257.06:28:31.03#ibcon#read 4, iclass 32, count 0 2006.257.06:28:31.03#ibcon#about to read 5, iclass 32, count 0 2006.257.06:28:31.03#ibcon#read 5, iclass 32, count 0 2006.257.06:28:31.03#ibcon#about to read 6, iclass 32, count 0 2006.257.06:28:31.03#ibcon#read 6, iclass 32, count 0 2006.257.06:28:31.03#ibcon#end of sib2, iclass 32, count 0 2006.257.06:28:31.03#ibcon#*after write, iclass 32, count 0 2006.257.06:28:31.03#ibcon#*before return 0, iclass 32, count 0 2006.257.06:28:31.03#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:31.03#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:28:31.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:28:31.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:28:31.03$vck44/vblo=4,679.99 2006.257.06:28:31.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.06:28:31.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.06:28:31.03#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:31.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:31.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:31.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:31.03#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:28:31.03#ibcon#first serial, iclass 38, count 0 2006.257.06:28:31.03#ibcon#enter sib2, iclass 38, count 0 2006.257.06:28:31.03#ibcon#flushed, iclass 38, count 0 2006.257.06:28:31.03#ibcon#about to write, iclass 38, count 0 2006.257.06:28:31.03#ibcon#wrote, iclass 38, count 0 2006.257.06:28:31.03#ibcon#about to read 3, iclass 38, count 0 2006.257.06:28:31.05#ibcon#read 3, iclass 38, count 0 2006.257.06:28:31.05#ibcon#about to read 4, iclass 38, count 0 2006.257.06:28:31.05#ibcon#read 4, iclass 38, count 0 2006.257.06:28:31.05#ibcon#about to read 5, iclass 38, count 0 2006.257.06:28:31.05#ibcon#read 5, iclass 38, count 0 2006.257.06:28:31.05#ibcon#about to read 6, iclass 38, count 0 2006.257.06:28:31.05#ibcon#read 6, iclass 38, count 0 2006.257.06:28:31.05#ibcon#end of sib2, iclass 38, count 0 2006.257.06:28:31.05#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:28:31.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:28:31.05#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:28:31.05#ibcon#*before write, iclass 38, count 0 2006.257.06:28:31.05#ibcon#enter sib2, iclass 38, count 0 2006.257.06:28:31.05#ibcon#flushed, iclass 38, count 0 2006.257.06:28:31.05#ibcon#about to write, iclass 38, count 0 2006.257.06:28:31.05#ibcon#wrote, iclass 38, count 0 2006.257.06:28:31.05#ibcon#about to read 3, iclass 38, count 0 2006.257.06:28:31.09#ibcon#read 3, iclass 38, count 0 2006.257.06:28:31.09#ibcon#about to read 4, iclass 38, count 0 2006.257.06:28:31.09#ibcon#read 4, iclass 38, count 0 2006.257.06:28:31.09#ibcon#about to read 5, iclass 38, count 0 2006.257.06:28:31.09#ibcon#read 5, iclass 38, count 0 2006.257.06:28:31.09#ibcon#about to read 6, iclass 38, count 0 2006.257.06:28:31.09#ibcon#read 6, iclass 38, count 0 2006.257.06:28:31.09#ibcon#end of sib2, iclass 38, count 0 2006.257.06:28:31.09#ibcon#*after write, iclass 38, count 0 2006.257.06:28:31.09#ibcon#*before return 0, iclass 38, count 0 2006.257.06:28:31.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:31.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:28:31.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:28:31.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:28:31.09$vck44/vb=4,5 2006.257.06:28:31.09#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.06:28:31.09#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.06:28:31.09#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:31.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:31.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:31.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:31.15#ibcon#enter wrdev, iclass 40, count 2 2006.257.06:28:31.15#ibcon#first serial, iclass 40, count 2 2006.257.06:28:31.15#ibcon#enter sib2, iclass 40, count 2 2006.257.06:28:31.15#ibcon#flushed, iclass 40, count 2 2006.257.06:28:31.15#ibcon#about to write, iclass 40, count 2 2006.257.06:28:31.15#ibcon#wrote, iclass 40, count 2 2006.257.06:28:31.15#ibcon#about to read 3, iclass 40, count 2 2006.257.06:28:31.17#ibcon#read 3, iclass 40, count 2 2006.257.06:28:31.17#ibcon#about to read 4, iclass 40, count 2 2006.257.06:28:31.17#ibcon#read 4, iclass 40, count 2 2006.257.06:28:31.17#ibcon#about to read 5, iclass 40, count 2 2006.257.06:28:31.17#ibcon#read 5, iclass 40, count 2 2006.257.06:28:31.17#ibcon#about to read 6, iclass 40, count 2 2006.257.06:28:31.17#ibcon#read 6, iclass 40, count 2 2006.257.06:28:31.17#ibcon#end of sib2, iclass 40, count 2 2006.257.06:28:31.17#ibcon#*mode == 0, iclass 40, count 2 2006.257.06:28:31.17#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.06:28:31.17#ibcon#[27=AT04-05\r\n] 2006.257.06:28:31.17#ibcon#*before write, iclass 40, count 2 2006.257.06:28:31.17#ibcon#enter sib2, iclass 40, count 2 2006.257.06:28:31.17#ibcon#flushed, iclass 40, count 2 2006.257.06:28:31.17#ibcon#about to write, iclass 40, count 2 2006.257.06:28:31.17#ibcon#wrote, iclass 40, count 2 2006.257.06:28:31.17#ibcon#about to read 3, iclass 40, count 2 2006.257.06:28:31.20#ibcon#read 3, iclass 40, count 2 2006.257.06:28:31.20#ibcon#about to read 4, iclass 40, count 2 2006.257.06:28:31.20#ibcon#read 4, iclass 40, count 2 2006.257.06:28:31.20#ibcon#about to read 5, iclass 40, count 2 2006.257.06:28:31.20#ibcon#read 5, iclass 40, count 2 2006.257.06:28:31.20#ibcon#about to read 6, iclass 40, count 2 2006.257.06:28:31.20#ibcon#read 6, iclass 40, count 2 2006.257.06:28:31.20#ibcon#end of sib2, iclass 40, count 2 2006.257.06:28:31.20#ibcon#*after write, iclass 40, count 2 2006.257.06:28:31.20#ibcon#*before return 0, iclass 40, count 2 2006.257.06:28:31.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:31.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:28:31.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.06:28:31.20#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:31.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:31.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:31.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:31.32#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:28:31.32#ibcon#first serial, iclass 40, count 0 2006.257.06:28:31.32#ibcon#enter sib2, iclass 40, count 0 2006.257.06:28:31.32#ibcon#flushed, iclass 40, count 0 2006.257.06:28:31.32#ibcon#about to write, iclass 40, count 0 2006.257.06:28:31.32#ibcon#wrote, iclass 40, count 0 2006.257.06:28:31.32#ibcon#about to read 3, iclass 40, count 0 2006.257.06:28:31.34#ibcon#read 3, iclass 40, count 0 2006.257.06:28:31.34#ibcon#about to read 4, iclass 40, count 0 2006.257.06:28:31.34#ibcon#read 4, iclass 40, count 0 2006.257.06:28:31.34#ibcon#about to read 5, iclass 40, count 0 2006.257.06:28:31.34#ibcon#read 5, iclass 40, count 0 2006.257.06:28:31.34#ibcon#about to read 6, iclass 40, count 0 2006.257.06:28:31.34#ibcon#read 6, iclass 40, count 0 2006.257.06:28:31.34#ibcon#end of sib2, iclass 40, count 0 2006.257.06:28:31.34#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:28:31.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:28:31.34#ibcon#[27=USB\r\n] 2006.257.06:28:31.34#ibcon#*before write, iclass 40, count 0 2006.257.06:28:31.34#ibcon#enter sib2, iclass 40, count 0 2006.257.06:28:31.34#ibcon#flushed, iclass 40, count 0 2006.257.06:28:31.34#ibcon#about to write, iclass 40, count 0 2006.257.06:28:31.34#ibcon#wrote, iclass 40, count 0 2006.257.06:28:31.34#ibcon#about to read 3, iclass 40, count 0 2006.257.06:28:31.37#ibcon#read 3, iclass 40, count 0 2006.257.06:28:31.37#ibcon#about to read 4, iclass 40, count 0 2006.257.06:28:31.37#ibcon#read 4, iclass 40, count 0 2006.257.06:28:31.37#ibcon#about to read 5, iclass 40, count 0 2006.257.06:28:31.37#ibcon#read 5, iclass 40, count 0 2006.257.06:28:31.37#ibcon#about to read 6, iclass 40, count 0 2006.257.06:28:31.37#ibcon#read 6, iclass 40, count 0 2006.257.06:28:31.37#ibcon#end of sib2, iclass 40, count 0 2006.257.06:28:31.37#ibcon#*after write, iclass 40, count 0 2006.257.06:28:31.37#ibcon#*before return 0, iclass 40, count 0 2006.257.06:28:31.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:31.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:28:31.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:28:31.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:28:31.37$vck44/vblo=5,709.99 2006.257.06:28:31.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.06:28:31.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.06:28:31.37#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:31.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:31.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:31.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:31.37#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:28:31.37#ibcon#first serial, iclass 4, count 0 2006.257.06:28:31.37#ibcon#enter sib2, iclass 4, count 0 2006.257.06:28:31.37#ibcon#flushed, iclass 4, count 0 2006.257.06:28:31.37#ibcon#about to write, iclass 4, count 0 2006.257.06:28:31.37#ibcon#wrote, iclass 4, count 0 2006.257.06:28:31.37#ibcon#about to read 3, iclass 4, count 0 2006.257.06:28:31.39#ibcon#read 3, iclass 4, count 0 2006.257.06:28:31.39#ibcon#about to read 4, iclass 4, count 0 2006.257.06:28:31.39#ibcon#read 4, iclass 4, count 0 2006.257.06:28:31.39#ibcon#about to read 5, iclass 4, count 0 2006.257.06:28:31.39#ibcon#read 5, iclass 4, count 0 2006.257.06:28:31.39#ibcon#about to read 6, iclass 4, count 0 2006.257.06:28:31.39#ibcon#read 6, iclass 4, count 0 2006.257.06:28:31.39#ibcon#end of sib2, iclass 4, count 0 2006.257.06:28:31.39#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:28:31.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:28:31.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:28:31.39#ibcon#*before write, iclass 4, count 0 2006.257.06:28:31.39#ibcon#enter sib2, iclass 4, count 0 2006.257.06:28:31.39#ibcon#flushed, iclass 4, count 0 2006.257.06:28:31.39#ibcon#about to write, iclass 4, count 0 2006.257.06:28:31.39#ibcon#wrote, iclass 4, count 0 2006.257.06:28:31.39#ibcon#about to read 3, iclass 4, count 0 2006.257.06:28:31.43#ibcon#read 3, iclass 4, count 0 2006.257.06:28:31.43#ibcon#about to read 4, iclass 4, count 0 2006.257.06:28:31.43#ibcon#read 4, iclass 4, count 0 2006.257.06:28:31.43#ibcon#about to read 5, iclass 4, count 0 2006.257.06:28:31.43#ibcon#read 5, iclass 4, count 0 2006.257.06:28:31.43#ibcon#about to read 6, iclass 4, count 0 2006.257.06:28:31.43#ibcon#read 6, iclass 4, count 0 2006.257.06:28:31.43#ibcon#end of sib2, iclass 4, count 0 2006.257.06:28:31.43#ibcon#*after write, iclass 4, count 0 2006.257.06:28:31.43#ibcon#*before return 0, iclass 4, count 0 2006.257.06:28:31.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:31.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:28:31.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:28:31.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:28:31.43$vck44/vb=5,4 2006.257.06:28:31.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.06:28:31.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.06:28:31.43#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:31.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:31.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:31.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:31.49#ibcon#enter wrdev, iclass 6, count 2 2006.257.06:28:31.49#ibcon#first serial, iclass 6, count 2 2006.257.06:28:31.49#ibcon#enter sib2, iclass 6, count 2 2006.257.06:28:31.49#ibcon#flushed, iclass 6, count 2 2006.257.06:28:31.49#ibcon#about to write, iclass 6, count 2 2006.257.06:28:31.49#ibcon#wrote, iclass 6, count 2 2006.257.06:28:31.49#ibcon#about to read 3, iclass 6, count 2 2006.257.06:28:31.51#ibcon#read 3, iclass 6, count 2 2006.257.06:28:31.51#ibcon#about to read 4, iclass 6, count 2 2006.257.06:28:31.51#ibcon#read 4, iclass 6, count 2 2006.257.06:28:31.51#ibcon#about to read 5, iclass 6, count 2 2006.257.06:28:31.51#ibcon#read 5, iclass 6, count 2 2006.257.06:28:31.51#ibcon#about to read 6, iclass 6, count 2 2006.257.06:28:31.51#ibcon#read 6, iclass 6, count 2 2006.257.06:28:31.51#ibcon#end of sib2, iclass 6, count 2 2006.257.06:28:31.51#ibcon#*mode == 0, iclass 6, count 2 2006.257.06:28:31.51#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.06:28:31.51#ibcon#[27=AT05-04\r\n] 2006.257.06:28:31.51#ibcon#*before write, iclass 6, count 2 2006.257.06:28:31.51#ibcon#enter sib2, iclass 6, count 2 2006.257.06:28:31.51#ibcon#flushed, iclass 6, count 2 2006.257.06:28:31.51#ibcon#about to write, iclass 6, count 2 2006.257.06:28:31.51#ibcon#wrote, iclass 6, count 2 2006.257.06:28:31.51#ibcon#about to read 3, iclass 6, count 2 2006.257.06:28:31.54#ibcon#read 3, iclass 6, count 2 2006.257.06:28:31.54#ibcon#about to read 4, iclass 6, count 2 2006.257.06:28:31.54#ibcon#read 4, iclass 6, count 2 2006.257.06:28:31.54#ibcon#about to read 5, iclass 6, count 2 2006.257.06:28:31.54#ibcon#read 5, iclass 6, count 2 2006.257.06:28:31.54#ibcon#about to read 6, iclass 6, count 2 2006.257.06:28:31.54#ibcon#read 6, iclass 6, count 2 2006.257.06:28:31.54#ibcon#end of sib2, iclass 6, count 2 2006.257.06:28:31.54#ibcon#*after write, iclass 6, count 2 2006.257.06:28:31.54#ibcon#*before return 0, iclass 6, count 2 2006.257.06:28:31.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:31.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:28:31.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.06:28:31.54#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:31.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:31.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:31.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:31.66#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:28:31.66#ibcon#first serial, iclass 6, count 0 2006.257.06:28:31.66#ibcon#enter sib2, iclass 6, count 0 2006.257.06:28:31.66#ibcon#flushed, iclass 6, count 0 2006.257.06:28:31.66#ibcon#about to write, iclass 6, count 0 2006.257.06:28:31.66#ibcon#wrote, iclass 6, count 0 2006.257.06:28:31.66#ibcon#about to read 3, iclass 6, count 0 2006.257.06:28:31.68#ibcon#read 3, iclass 6, count 0 2006.257.06:28:31.68#ibcon#about to read 4, iclass 6, count 0 2006.257.06:28:31.68#ibcon#read 4, iclass 6, count 0 2006.257.06:28:31.68#ibcon#about to read 5, iclass 6, count 0 2006.257.06:28:31.68#ibcon#read 5, iclass 6, count 0 2006.257.06:28:31.68#ibcon#about to read 6, iclass 6, count 0 2006.257.06:28:31.68#ibcon#read 6, iclass 6, count 0 2006.257.06:28:31.68#ibcon#end of sib2, iclass 6, count 0 2006.257.06:28:31.68#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:28:31.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:28:31.68#ibcon#[27=USB\r\n] 2006.257.06:28:31.68#ibcon#*before write, iclass 6, count 0 2006.257.06:28:31.68#ibcon#enter sib2, iclass 6, count 0 2006.257.06:28:31.68#ibcon#flushed, iclass 6, count 0 2006.257.06:28:31.68#ibcon#about to write, iclass 6, count 0 2006.257.06:28:31.68#ibcon#wrote, iclass 6, count 0 2006.257.06:28:31.68#ibcon#about to read 3, iclass 6, count 0 2006.257.06:28:31.71#ibcon#read 3, iclass 6, count 0 2006.257.06:28:31.71#ibcon#about to read 4, iclass 6, count 0 2006.257.06:28:31.71#ibcon#read 4, iclass 6, count 0 2006.257.06:28:31.71#ibcon#about to read 5, iclass 6, count 0 2006.257.06:28:31.71#ibcon#read 5, iclass 6, count 0 2006.257.06:28:31.71#ibcon#about to read 6, iclass 6, count 0 2006.257.06:28:31.71#ibcon#read 6, iclass 6, count 0 2006.257.06:28:31.71#ibcon#end of sib2, iclass 6, count 0 2006.257.06:28:31.71#ibcon#*after write, iclass 6, count 0 2006.257.06:28:31.71#ibcon#*before return 0, iclass 6, count 0 2006.257.06:28:31.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:31.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:28:31.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:28:31.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:28:31.71$vck44/vblo=6,719.99 2006.257.06:28:31.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.06:28:31.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.06:28:31.71#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:31.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:31.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:31.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:31.71#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:28:31.71#ibcon#first serial, iclass 10, count 0 2006.257.06:28:31.71#ibcon#enter sib2, iclass 10, count 0 2006.257.06:28:31.71#ibcon#flushed, iclass 10, count 0 2006.257.06:28:31.71#ibcon#about to write, iclass 10, count 0 2006.257.06:28:31.71#ibcon#wrote, iclass 10, count 0 2006.257.06:28:31.71#ibcon#about to read 3, iclass 10, count 0 2006.257.06:28:31.73#ibcon#read 3, iclass 10, count 0 2006.257.06:28:31.73#ibcon#about to read 4, iclass 10, count 0 2006.257.06:28:31.73#ibcon#read 4, iclass 10, count 0 2006.257.06:28:31.73#ibcon#about to read 5, iclass 10, count 0 2006.257.06:28:31.73#ibcon#read 5, iclass 10, count 0 2006.257.06:28:31.73#ibcon#about to read 6, iclass 10, count 0 2006.257.06:28:31.73#ibcon#read 6, iclass 10, count 0 2006.257.06:28:31.73#ibcon#end of sib2, iclass 10, count 0 2006.257.06:28:31.73#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:28:31.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:28:31.73#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:28:31.73#ibcon#*before write, iclass 10, count 0 2006.257.06:28:31.73#ibcon#enter sib2, iclass 10, count 0 2006.257.06:28:31.73#ibcon#flushed, iclass 10, count 0 2006.257.06:28:31.73#ibcon#about to write, iclass 10, count 0 2006.257.06:28:31.73#ibcon#wrote, iclass 10, count 0 2006.257.06:28:31.73#ibcon#about to read 3, iclass 10, count 0 2006.257.06:28:31.77#ibcon#read 3, iclass 10, count 0 2006.257.06:28:31.77#ibcon#about to read 4, iclass 10, count 0 2006.257.06:28:31.77#ibcon#read 4, iclass 10, count 0 2006.257.06:28:31.77#ibcon#about to read 5, iclass 10, count 0 2006.257.06:28:31.77#ibcon#read 5, iclass 10, count 0 2006.257.06:28:31.77#ibcon#about to read 6, iclass 10, count 0 2006.257.06:28:31.77#ibcon#read 6, iclass 10, count 0 2006.257.06:28:31.77#ibcon#end of sib2, iclass 10, count 0 2006.257.06:28:31.77#ibcon#*after write, iclass 10, count 0 2006.257.06:28:31.77#ibcon#*before return 0, iclass 10, count 0 2006.257.06:28:31.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:31.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:28:31.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:28:31.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:28:31.77$vck44/vb=6,4 2006.257.06:28:31.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.06:28:31.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.06:28:31.77#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:31.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:31.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:31.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:31.83#ibcon#enter wrdev, iclass 12, count 2 2006.257.06:28:31.83#ibcon#first serial, iclass 12, count 2 2006.257.06:28:31.83#ibcon#enter sib2, iclass 12, count 2 2006.257.06:28:31.83#ibcon#flushed, iclass 12, count 2 2006.257.06:28:31.83#ibcon#about to write, iclass 12, count 2 2006.257.06:28:31.83#ibcon#wrote, iclass 12, count 2 2006.257.06:28:31.83#ibcon#about to read 3, iclass 12, count 2 2006.257.06:28:31.85#ibcon#read 3, iclass 12, count 2 2006.257.06:28:31.85#ibcon#about to read 4, iclass 12, count 2 2006.257.06:28:31.85#ibcon#read 4, iclass 12, count 2 2006.257.06:28:31.85#ibcon#about to read 5, iclass 12, count 2 2006.257.06:28:31.85#ibcon#read 5, iclass 12, count 2 2006.257.06:28:31.85#ibcon#about to read 6, iclass 12, count 2 2006.257.06:28:31.85#ibcon#read 6, iclass 12, count 2 2006.257.06:28:31.85#ibcon#end of sib2, iclass 12, count 2 2006.257.06:28:31.85#ibcon#*mode == 0, iclass 12, count 2 2006.257.06:28:31.85#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.06:28:31.85#ibcon#[27=AT06-04\r\n] 2006.257.06:28:31.85#ibcon#*before write, iclass 12, count 2 2006.257.06:28:31.85#ibcon#enter sib2, iclass 12, count 2 2006.257.06:28:31.85#ibcon#flushed, iclass 12, count 2 2006.257.06:28:31.85#ibcon#about to write, iclass 12, count 2 2006.257.06:28:31.85#ibcon#wrote, iclass 12, count 2 2006.257.06:28:31.85#ibcon#about to read 3, iclass 12, count 2 2006.257.06:28:31.88#ibcon#read 3, iclass 12, count 2 2006.257.06:28:31.88#ibcon#about to read 4, iclass 12, count 2 2006.257.06:28:31.88#ibcon#read 4, iclass 12, count 2 2006.257.06:28:31.88#ibcon#about to read 5, iclass 12, count 2 2006.257.06:28:31.88#ibcon#read 5, iclass 12, count 2 2006.257.06:28:31.88#ibcon#about to read 6, iclass 12, count 2 2006.257.06:28:31.88#ibcon#read 6, iclass 12, count 2 2006.257.06:28:31.88#ibcon#end of sib2, iclass 12, count 2 2006.257.06:28:31.88#ibcon#*after write, iclass 12, count 2 2006.257.06:28:31.88#ibcon#*before return 0, iclass 12, count 2 2006.257.06:28:31.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:31.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:28:31.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.06:28:31.88#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:31.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:32.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:32.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:32.00#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:28:32.00#ibcon#first serial, iclass 12, count 0 2006.257.06:28:32.00#ibcon#enter sib2, iclass 12, count 0 2006.257.06:28:32.00#ibcon#flushed, iclass 12, count 0 2006.257.06:28:32.00#ibcon#about to write, iclass 12, count 0 2006.257.06:28:32.00#ibcon#wrote, iclass 12, count 0 2006.257.06:28:32.00#ibcon#about to read 3, iclass 12, count 0 2006.257.06:28:32.02#ibcon#read 3, iclass 12, count 0 2006.257.06:28:32.02#ibcon#about to read 4, iclass 12, count 0 2006.257.06:28:32.02#ibcon#read 4, iclass 12, count 0 2006.257.06:28:32.02#ibcon#about to read 5, iclass 12, count 0 2006.257.06:28:32.02#ibcon#read 5, iclass 12, count 0 2006.257.06:28:32.02#ibcon#about to read 6, iclass 12, count 0 2006.257.06:28:32.02#ibcon#read 6, iclass 12, count 0 2006.257.06:28:32.02#ibcon#end of sib2, iclass 12, count 0 2006.257.06:28:32.02#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:28:32.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:28:32.02#ibcon#[27=USB\r\n] 2006.257.06:28:32.02#ibcon#*before write, iclass 12, count 0 2006.257.06:28:32.02#ibcon#enter sib2, iclass 12, count 0 2006.257.06:28:32.02#ibcon#flushed, iclass 12, count 0 2006.257.06:28:32.02#ibcon#about to write, iclass 12, count 0 2006.257.06:28:32.02#ibcon#wrote, iclass 12, count 0 2006.257.06:28:32.02#ibcon#about to read 3, iclass 12, count 0 2006.257.06:28:32.05#ibcon#read 3, iclass 12, count 0 2006.257.06:28:32.05#ibcon#about to read 4, iclass 12, count 0 2006.257.06:28:32.05#ibcon#read 4, iclass 12, count 0 2006.257.06:28:32.05#ibcon#about to read 5, iclass 12, count 0 2006.257.06:28:32.05#ibcon#read 5, iclass 12, count 0 2006.257.06:28:32.05#ibcon#about to read 6, iclass 12, count 0 2006.257.06:28:32.05#ibcon#read 6, iclass 12, count 0 2006.257.06:28:32.05#ibcon#end of sib2, iclass 12, count 0 2006.257.06:28:32.05#ibcon#*after write, iclass 12, count 0 2006.257.06:28:32.05#ibcon#*before return 0, iclass 12, count 0 2006.257.06:28:32.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:32.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:28:32.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:28:32.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:28:32.05$vck44/vblo=7,734.99 2006.257.06:28:32.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.06:28:32.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.06:28:32.05#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:32.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:32.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:32.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:32.05#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:28:32.05#ibcon#first serial, iclass 14, count 0 2006.257.06:28:32.05#ibcon#enter sib2, iclass 14, count 0 2006.257.06:28:32.05#ibcon#flushed, iclass 14, count 0 2006.257.06:28:32.05#ibcon#about to write, iclass 14, count 0 2006.257.06:28:32.05#ibcon#wrote, iclass 14, count 0 2006.257.06:28:32.05#ibcon#about to read 3, iclass 14, count 0 2006.257.06:28:32.07#ibcon#read 3, iclass 14, count 0 2006.257.06:28:32.07#ibcon#about to read 4, iclass 14, count 0 2006.257.06:28:32.07#ibcon#read 4, iclass 14, count 0 2006.257.06:28:32.07#ibcon#about to read 5, iclass 14, count 0 2006.257.06:28:32.07#ibcon#read 5, iclass 14, count 0 2006.257.06:28:32.07#ibcon#about to read 6, iclass 14, count 0 2006.257.06:28:32.07#ibcon#read 6, iclass 14, count 0 2006.257.06:28:32.07#ibcon#end of sib2, iclass 14, count 0 2006.257.06:28:32.07#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:28:32.07#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:28:32.07#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:28:32.07#ibcon#*before write, iclass 14, count 0 2006.257.06:28:32.07#ibcon#enter sib2, iclass 14, count 0 2006.257.06:28:32.07#ibcon#flushed, iclass 14, count 0 2006.257.06:28:32.07#ibcon#about to write, iclass 14, count 0 2006.257.06:28:32.07#ibcon#wrote, iclass 14, count 0 2006.257.06:28:32.07#ibcon#about to read 3, iclass 14, count 0 2006.257.06:28:32.11#ibcon#read 3, iclass 14, count 0 2006.257.06:28:32.11#ibcon#about to read 4, iclass 14, count 0 2006.257.06:28:32.11#ibcon#read 4, iclass 14, count 0 2006.257.06:28:32.11#ibcon#about to read 5, iclass 14, count 0 2006.257.06:28:32.11#ibcon#read 5, iclass 14, count 0 2006.257.06:28:32.11#ibcon#about to read 6, iclass 14, count 0 2006.257.06:28:32.11#ibcon#read 6, iclass 14, count 0 2006.257.06:28:32.11#ibcon#end of sib2, iclass 14, count 0 2006.257.06:28:32.11#ibcon#*after write, iclass 14, count 0 2006.257.06:28:32.11#ibcon#*before return 0, iclass 14, count 0 2006.257.06:28:32.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:32.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:28:32.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:28:32.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:28:32.11$vck44/vb=7,4 2006.257.06:28:32.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.06:28:32.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.06:28:32.11#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:32.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:32.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:32.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:32.17#ibcon#enter wrdev, iclass 16, count 2 2006.257.06:28:32.17#ibcon#first serial, iclass 16, count 2 2006.257.06:28:32.17#ibcon#enter sib2, iclass 16, count 2 2006.257.06:28:32.17#ibcon#flushed, iclass 16, count 2 2006.257.06:28:32.17#ibcon#about to write, iclass 16, count 2 2006.257.06:28:32.17#ibcon#wrote, iclass 16, count 2 2006.257.06:28:32.17#ibcon#about to read 3, iclass 16, count 2 2006.257.06:28:32.19#ibcon#read 3, iclass 16, count 2 2006.257.06:28:32.19#ibcon#about to read 4, iclass 16, count 2 2006.257.06:28:32.19#ibcon#read 4, iclass 16, count 2 2006.257.06:28:32.19#ibcon#about to read 5, iclass 16, count 2 2006.257.06:28:32.19#ibcon#read 5, iclass 16, count 2 2006.257.06:28:32.19#ibcon#about to read 6, iclass 16, count 2 2006.257.06:28:32.19#ibcon#read 6, iclass 16, count 2 2006.257.06:28:32.19#ibcon#end of sib2, iclass 16, count 2 2006.257.06:28:32.19#ibcon#*mode == 0, iclass 16, count 2 2006.257.06:28:32.19#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.06:28:32.19#ibcon#[27=AT07-04\r\n] 2006.257.06:28:32.19#ibcon#*before write, iclass 16, count 2 2006.257.06:28:32.19#ibcon#enter sib2, iclass 16, count 2 2006.257.06:28:32.19#ibcon#flushed, iclass 16, count 2 2006.257.06:28:32.19#ibcon#about to write, iclass 16, count 2 2006.257.06:28:32.19#ibcon#wrote, iclass 16, count 2 2006.257.06:28:32.19#ibcon#about to read 3, iclass 16, count 2 2006.257.06:28:32.22#ibcon#read 3, iclass 16, count 2 2006.257.06:28:32.22#ibcon#about to read 4, iclass 16, count 2 2006.257.06:28:32.22#ibcon#read 4, iclass 16, count 2 2006.257.06:28:32.22#ibcon#about to read 5, iclass 16, count 2 2006.257.06:28:32.22#ibcon#read 5, iclass 16, count 2 2006.257.06:28:32.22#ibcon#about to read 6, iclass 16, count 2 2006.257.06:28:32.22#ibcon#read 6, iclass 16, count 2 2006.257.06:28:32.22#ibcon#end of sib2, iclass 16, count 2 2006.257.06:28:32.22#ibcon#*after write, iclass 16, count 2 2006.257.06:28:32.22#ibcon#*before return 0, iclass 16, count 2 2006.257.06:28:32.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:32.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:28:32.22#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.06:28:32.22#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:32.22#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:32.34#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:32.34#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:32.34#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:28:32.34#ibcon#first serial, iclass 16, count 0 2006.257.06:28:32.34#ibcon#enter sib2, iclass 16, count 0 2006.257.06:28:32.34#ibcon#flushed, iclass 16, count 0 2006.257.06:28:32.34#ibcon#about to write, iclass 16, count 0 2006.257.06:28:32.34#ibcon#wrote, iclass 16, count 0 2006.257.06:28:32.34#ibcon#about to read 3, iclass 16, count 0 2006.257.06:28:32.36#ibcon#read 3, iclass 16, count 0 2006.257.06:28:32.36#ibcon#about to read 4, iclass 16, count 0 2006.257.06:28:32.36#ibcon#read 4, iclass 16, count 0 2006.257.06:28:32.36#ibcon#about to read 5, iclass 16, count 0 2006.257.06:28:32.36#ibcon#read 5, iclass 16, count 0 2006.257.06:28:32.36#ibcon#about to read 6, iclass 16, count 0 2006.257.06:28:32.36#ibcon#read 6, iclass 16, count 0 2006.257.06:28:32.36#ibcon#end of sib2, iclass 16, count 0 2006.257.06:28:32.36#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:28:32.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:28:32.36#ibcon#[27=USB\r\n] 2006.257.06:28:32.36#ibcon#*before write, iclass 16, count 0 2006.257.06:28:32.36#ibcon#enter sib2, iclass 16, count 0 2006.257.06:28:32.36#ibcon#flushed, iclass 16, count 0 2006.257.06:28:32.36#ibcon#about to write, iclass 16, count 0 2006.257.06:28:32.36#ibcon#wrote, iclass 16, count 0 2006.257.06:28:32.36#ibcon#about to read 3, iclass 16, count 0 2006.257.06:28:32.39#ibcon#read 3, iclass 16, count 0 2006.257.06:28:32.39#ibcon#about to read 4, iclass 16, count 0 2006.257.06:28:32.39#ibcon#read 4, iclass 16, count 0 2006.257.06:28:32.39#ibcon#about to read 5, iclass 16, count 0 2006.257.06:28:32.39#ibcon#read 5, iclass 16, count 0 2006.257.06:28:32.39#ibcon#about to read 6, iclass 16, count 0 2006.257.06:28:32.39#ibcon#read 6, iclass 16, count 0 2006.257.06:28:32.39#ibcon#end of sib2, iclass 16, count 0 2006.257.06:28:32.39#ibcon#*after write, iclass 16, count 0 2006.257.06:28:32.39#ibcon#*before return 0, iclass 16, count 0 2006.257.06:28:32.39#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:32.39#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:28:32.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:28:32.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:28:32.39$vck44/vblo=8,744.99 2006.257.06:28:32.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.06:28:32.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.06:28:32.39#ibcon#ireg 17 cls_cnt 0 2006.257.06:28:32.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:32.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:32.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:32.39#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:28:32.39#ibcon#first serial, iclass 18, count 0 2006.257.06:28:32.39#ibcon#enter sib2, iclass 18, count 0 2006.257.06:28:32.39#ibcon#flushed, iclass 18, count 0 2006.257.06:28:32.39#ibcon#about to write, iclass 18, count 0 2006.257.06:28:32.39#ibcon#wrote, iclass 18, count 0 2006.257.06:28:32.39#ibcon#about to read 3, iclass 18, count 0 2006.257.06:28:32.41#ibcon#read 3, iclass 18, count 0 2006.257.06:28:32.41#ibcon#about to read 4, iclass 18, count 0 2006.257.06:28:32.41#ibcon#read 4, iclass 18, count 0 2006.257.06:28:32.41#ibcon#about to read 5, iclass 18, count 0 2006.257.06:28:32.41#ibcon#read 5, iclass 18, count 0 2006.257.06:28:32.41#ibcon#about to read 6, iclass 18, count 0 2006.257.06:28:32.41#ibcon#read 6, iclass 18, count 0 2006.257.06:28:32.41#ibcon#end of sib2, iclass 18, count 0 2006.257.06:28:32.41#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:28:32.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:28:32.41#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:28:32.41#ibcon#*before write, iclass 18, count 0 2006.257.06:28:32.41#ibcon#enter sib2, iclass 18, count 0 2006.257.06:28:32.41#ibcon#flushed, iclass 18, count 0 2006.257.06:28:32.41#ibcon#about to write, iclass 18, count 0 2006.257.06:28:32.41#ibcon#wrote, iclass 18, count 0 2006.257.06:28:32.41#ibcon#about to read 3, iclass 18, count 0 2006.257.06:28:32.45#ibcon#read 3, iclass 18, count 0 2006.257.06:28:32.45#ibcon#about to read 4, iclass 18, count 0 2006.257.06:28:32.45#ibcon#read 4, iclass 18, count 0 2006.257.06:28:32.45#ibcon#about to read 5, iclass 18, count 0 2006.257.06:28:32.45#ibcon#read 5, iclass 18, count 0 2006.257.06:28:32.45#ibcon#about to read 6, iclass 18, count 0 2006.257.06:28:32.45#ibcon#read 6, iclass 18, count 0 2006.257.06:28:32.45#ibcon#end of sib2, iclass 18, count 0 2006.257.06:28:32.45#ibcon#*after write, iclass 18, count 0 2006.257.06:28:32.45#ibcon#*before return 0, iclass 18, count 0 2006.257.06:28:32.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:32.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:28:32.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:28:32.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:28:32.45$vck44/vb=8,4 2006.257.06:28:32.45#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.06:28:32.45#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.06:28:32.45#ibcon#ireg 11 cls_cnt 2 2006.257.06:28:32.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:32.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:32.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:32.51#ibcon#enter wrdev, iclass 20, count 2 2006.257.06:28:32.51#ibcon#first serial, iclass 20, count 2 2006.257.06:28:32.51#ibcon#enter sib2, iclass 20, count 2 2006.257.06:28:32.51#ibcon#flushed, iclass 20, count 2 2006.257.06:28:32.51#ibcon#about to write, iclass 20, count 2 2006.257.06:28:32.51#ibcon#wrote, iclass 20, count 2 2006.257.06:28:32.51#ibcon#about to read 3, iclass 20, count 2 2006.257.06:28:32.53#ibcon#read 3, iclass 20, count 2 2006.257.06:28:32.53#ibcon#about to read 4, iclass 20, count 2 2006.257.06:28:32.53#ibcon#read 4, iclass 20, count 2 2006.257.06:28:32.53#ibcon#about to read 5, iclass 20, count 2 2006.257.06:28:32.53#ibcon#read 5, iclass 20, count 2 2006.257.06:28:32.53#ibcon#about to read 6, iclass 20, count 2 2006.257.06:28:32.53#ibcon#read 6, iclass 20, count 2 2006.257.06:28:32.53#ibcon#end of sib2, iclass 20, count 2 2006.257.06:28:32.53#ibcon#*mode == 0, iclass 20, count 2 2006.257.06:28:32.53#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.06:28:32.53#ibcon#[27=AT08-04\r\n] 2006.257.06:28:32.53#ibcon#*before write, iclass 20, count 2 2006.257.06:28:32.53#ibcon#enter sib2, iclass 20, count 2 2006.257.06:28:32.53#ibcon#flushed, iclass 20, count 2 2006.257.06:28:32.53#ibcon#about to write, iclass 20, count 2 2006.257.06:28:32.53#ibcon#wrote, iclass 20, count 2 2006.257.06:28:32.53#ibcon#about to read 3, iclass 20, count 2 2006.257.06:28:32.56#ibcon#read 3, iclass 20, count 2 2006.257.06:28:32.56#ibcon#about to read 4, iclass 20, count 2 2006.257.06:28:32.56#ibcon#read 4, iclass 20, count 2 2006.257.06:28:32.56#ibcon#about to read 5, iclass 20, count 2 2006.257.06:28:32.56#ibcon#read 5, iclass 20, count 2 2006.257.06:28:32.56#ibcon#about to read 6, iclass 20, count 2 2006.257.06:28:32.56#ibcon#read 6, iclass 20, count 2 2006.257.06:28:32.56#ibcon#end of sib2, iclass 20, count 2 2006.257.06:28:32.56#ibcon#*after write, iclass 20, count 2 2006.257.06:28:32.56#ibcon#*before return 0, iclass 20, count 2 2006.257.06:28:32.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:32.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:28:32.56#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.06:28:32.56#ibcon#ireg 7 cls_cnt 0 2006.257.06:28:32.56#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:32.68#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:32.68#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:32.68#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:28:32.68#ibcon#first serial, iclass 20, count 0 2006.257.06:28:32.68#ibcon#enter sib2, iclass 20, count 0 2006.257.06:28:32.68#ibcon#flushed, iclass 20, count 0 2006.257.06:28:32.68#ibcon#about to write, iclass 20, count 0 2006.257.06:28:32.68#ibcon#wrote, iclass 20, count 0 2006.257.06:28:32.68#ibcon#about to read 3, iclass 20, count 0 2006.257.06:28:32.70#ibcon#read 3, iclass 20, count 0 2006.257.06:28:32.70#ibcon#about to read 4, iclass 20, count 0 2006.257.06:28:32.70#ibcon#read 4, iclass 20, count 0 2006.257.06:28:32.70#ibcon#about to read 5, iclass 20, count 0 2006.257.06:28:32.70#ibcon#read 5, iclass 20, count 0 2006.257.06:28:32.70#ibcon#about to read 6, iclass 20, count 0 2006.257.06:28:32.70#ibcon#read 6, iclass 20, count 0 2006.257.06:28:32.70#ibcon#end of sib2, iclass 20, count 0 2006.257.06:28:32.70#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:28:32.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:28:32.70#ibcon#[27=USB\r\n] 2006.257.06:28:32.70#ibcon#*before write, iclass 20, count 0 2006.257.06:28:32.70#ibcon#enter sib2, iclass 20, count 0 2006.257.06:28:32.70#ibcon#flushed, iclass 20, count 0 2006.257.06:28:32.70#ibcon#about to write, iclass 20, count 0 2006.257.06:28:32.70#ibcon#wrote, iclass 20, count 0 2006.257.06:28:32.70#ibcon#about to read 3, iclass 20, count 0 2006.257.06:28:32.73#ibcon#read 3, iclass 20, count 0 2006.257.06:28:32.73#ibcon#about to read 4, iclass 20, count 0 2006.257.06:28:32.73#ibcon#read 4, iclass 20, count 0 2006.257.06:28:32.73#ibcon#about to read 5, iclass 20, count 0 2006.257.06:28:32.73#ibcon#read 5, iclass 20, count 0 2006.257.06:28:32.73#ibcon#about to read 6, iclass 20, count 0 2006.257.06:28:32.73#ibcon#read 6, iclass 20, count 0 2006.257.06:28:32.73#ibcon#end of sib2, iclass 20, count 0 2006.257.06:28:32.73#ibcon#*after write, iclass 20, count 0 2006.257.06:28:32.73#ibcon#*before return 0, iclass 20, count 0 2006.257.06:28:32.73#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:32.73#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:28:32.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:28:32.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:28:32.73$vck44/vabw=wide 2006.257.06:28:32.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.06:28:32.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.06:28:32.73#ibcon#ireg 8 cls_cnt 0 2006.257.06:28:32.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:32.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:32.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:32.73#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:28:32.73#ibcon#first serial, iclass 22, count 0 2006.257.06:28:32.73#ibcon#enter sib2, iclass 22, count 0 2006.257.06:28:32.73#ibcon#flushed, iclass 22, count 0 2006.257.06:28:32.73#ibcon#about to write, iclass 22, count 0 2006.257.06:28:32.73#ibcon#wrote, iclass 22, count 0 2006.257.06:28:32.73#ibcon#about to read 3, iclass 22, count 0 2006.257.06:28:32.75#ibcon#read 3, iclass 22, count 0 2006.257.06:28:32.75#ibcon#about to read 4, iclass 22, count 0 2006.257.06:28:32.75#ibcon#read 4, iclass 22, count 0 2006.257.06:28:32.75#ibcon#about to read 5, iclass 22, count 0 2006.257.06:28:32.75#ibcon#read 5, iclass 22, count 0 2006.257.06:28:32.75#ibcon#about to read 6, iclass 22, count 0 2006.257.06:28:32.75#ibcon#read 6, iclass 22, count 0 2006.257.06:28:32.75#ibcon#end of sib2, iclass 22, count 0 2006.257.06:28:32.75#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:28:32.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:28:32.75#ibcon#[25=BW32\r\n] 2006.257.06:28:32.75#ibcon#*before write, iclass 22, count 0 2006.257.06:28:32.75#ibcon#enter sib2, iclass 22, count 0 2006.257.06:28:32.75#ibcon#flushed, iclass 22, count 0 2006.257.06:28:32.75#ibcon#about to write, iclass 22, count 0 2006.257.06:28:32.75#ibcon#wrote, iclass 22, count 0 2006.257.06:28:32.75#ibcon#about to read 3, iclass 22, count 0 2006.257.06:28:32.78#ibcon#read 3, iclass 22, count 0 2006.257.06:28:32.78#ibcon#about to read 4, iclass 22, count 0 2006.257.06:28:32.78#ibcon#read 4, iclass 22, count 0 2006.257.06:28:32.78#ibcon#about to read 5, iclass 22, count 0 2006.257.06:28:32.78#ibcon#read 5, iclass 22, count 0 2006.257.06:28:32.78#ibcon#about to read 6, iclass 22, count 0 2006.257.06:28:32.78#ibcon#read 6, iclass 22, count 0 2006.257.06:28:32.78#ibcon#end of sib2, iclass 22, count 0 2006.257.06:28:32.78#ibcon#*after write, iclass 22, count 0 2006.257.06:28:32.78#ibcon#*before return 0, iclass 22, count 0 2006.257.06:28:32.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:32.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:28:32.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:28:32.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:28:32.78$vck44/vbbw=wide 2006.257.06:28:32.78#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.06:28:32.78#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.06:28:32.78#ibcon#ireg 8 cls_cnt 0 2006.257.06:28:32.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:28:32.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:28:32.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:28:32.85#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:28:32.85#ibcon#first serial, iclass 24, count 0 2006.257.06:28:32.85#ibcon#enter sib2, iclass 24, count 0 2006.257.06:28:32.85#ibcon#flushed, iclass 24, count 0 2006.257.06:28:32.85#ibcon#about to write, iclass 24, count 0 2006.257.06:28:32.85#ibcon#wrote, iclass 24, count 0 2006.257.06:28:32.85#ibcon#about to read 3, iclass 24, count 0 2006.257.06:28:32.87#ibcon#read 3, iclass 24, count 0 2006.257.06:28:32.87#ibcon#about to read 4, iclass 24, count 0 2006.257.06:28:32.87#ibcon#read 4, iclass 24, count 0 2006.257.06:28:32.87#ibcon#about to read 5, iclass 24, count 0 2006.257.06:28:32.87#ibcon#read 5, iclass 24, count 0 2006.257.06:28:32.87#ibcon#about to read 6, iclass 24, count 0 2006.257.06:28:32.87#ibcon#read 6, iclass 24, count 0 2006.257.06:28:32.87#ibcon#end of sib2, iclass 24, count 0 2006.257.06:28:32.87#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:28:32.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:28:32.87#ibcon#[27=BW32\r\n] 2006.257.06:28:32.87#ibcon#*before write, iclass 24, count 0 2006.257.06:28:32.87#ibcon#enter sib2, iclass 24, count 0 2006.257.06:28:32.87#ibcon#flushed, iclass 24, count 0 2006.257.06:28:32.87#ibcon#about to write, iclass 24, count 0 2006.257.06:28:32.87#ibcon#wrote, iclass 24, count 0 2006.257.06:28:32.87#ibcon#about to read 3, iclass 24, count 0 2006.257.06:28:32.90#ibcon#read 3, iclass 24, count 0 2006.257.06:28:32.90#ibcon#about to read 4, iclass 24, count 0 2006.257.06:28:32.90#ibcon#read 4, iclass 24, count 0 2006.257.06:28:32.90#ibcon#about to read 5, iclass 24, count 0 2006.257.06:28:32.90#ibcon#read 5, iclass 24, count 0 2006.257.06:28:32.90#ibcon#about to read 6, iclass 24, count 0 2006.257.06:28:32.90#ibcon#read 6, iclass 24, count 0 2006.257.06:28:32.90#ibcon#end of sib2, iclass 24, count 0 2006.257.06:28:32.90#ibcon#*after write, iclass 24, count 0 2006.257.06:28:32.90#ibcon#*before return 0, iclass 24, count 0 2006.257.06:28:32.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:28:32.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:28:32.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:28:32.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:28:32.90$setupk4/ifdk4 2006.257.06:28:32.90$ifdk4/lo= 2006.257.06:28:32.90$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:28:32.90$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:28:32.90$ifdk4/patch= 2006.257.06:28:32.90$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:28:32.90$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:28:32.90$setupk4/!*+20s 2006.257.06:28:41.11#abcon#<5=/15 0.8 2.8 20.50 891012.2\r\n> 2006.257.06:28:41.13#abcon#{5=INTERFACE CLEAR} 2006.257.06:28:41.19#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:28:45.14#trakl#Source acquired 2006.257.06:28:46.14#flagr#flagr/antenna,acquired 2006.257.06:28:47.41$setupk4/"tpicd 2006.257.06:28:47.41$setupk4/echo=off 2006.257.06:28:47.41$setupk4/xlog=off 2006.257.06:28:47.41:!2006.257.06:31:33 2006.257.06:31:33.00:preob 2006.257.06:31:33.14/onsource/TRACKING 2006.257.06:31:33.14:!2006.257.06:31:43 2006.257.06:31:43.00:"tape 2006.257.06:31:43.00:"st=record 2006.257.06:31:43.00:data_valid=on 2006.257.06:31:43.00:midob 2006.257.06:31:43.14/onsource/TRACKING 2006.257.06:31:43.14/wx/20.54,1012.2,89 2006.257.06:31:43.28/cable/+6.4798E-03 2006.257.06:31:44.37/va/01,08,usb,yes,32,34 2006.257.06:31:44.37/va/02,07,usb,yes,34,35 2006.257.06:31:44.37/va/03,08,usb,yes,31,32 2006.257.06:31:44.37/va/04,07,usb,yes,35,37 2006.257.06:31:44.37/va/05,04,usb,yes,32,32 2006.257.06:31:44.37/va/06,04,usb,yes,35,35 2006.257.06:31:44.37/va/07,04,usb,yes,36,37 2006.257.06:31:44.37/va/08,04,usb,yes,30,37 2006.257.06:31:44.60/valo/01,524.99,yes,locked 2006.257.06:31:44.60/valo/02,534.99,yes,locked 2006.257.06:31:44.60/valo/03,564.99,yes,locked 2006.257.06:31:44.60/valo/04,624.99,yes,locked 2006.257.06:31:44.60/valo/05,734.99,yes,locked 2006.257.06:31:44.60/valo/06,814.99,yes,locked 2006.257.06:31:44.60/valo/07,864.99,yes,locked 2006.257.06:31:44.60/valo/08,884.99,yes,locked 2006.257.06:31:45.69/vb/01,04,usb,yes,31,29 2006.257.06:31:45.69/vb/02,05,usb,yes,29,29 2006.257.06:31:45.69/vb/03,04,usb,yes,30,33 2006.257.06:31:45.69/vb/04,05,usb,yes,30,29 2006.257.06:31:45.69/vb/05,04,usb,yes,27,29 2006.257.06:31:45.69/vb/06,04,usb,yes,31,27 2006.257.06:31:45.69/vb/07,04,usb,yes,31,31 2006.257.06:31:45.69/vb/08,04,usb,yes,28,32 2006.257.06:31:45.93/vblo/01,629.99,yes,locked 2006.257.06:31:45.93/vblo/02,634.99,yes,locked 2006.257.06:31:45.93/vblo/03,649.99,yes,locked 2006.257.06:31:45.93/vblo/04,679.99,yes,locked 2006.257.06:31:45.93/vblo/05,709.99,yes,locked 2006.257.06:31:45.93/vblo/06,719.99,yes,locked 2006.257.06:31:45.93/vblo/07,734.99,yes,locked 2006.257.06:31:45.93/vblo/08,744.99,yes,locked 2006.257.06:31:46.08/vabw/8 2006.257.06:31:46.23/vbbw/8 2006.257.06:31:46.32/xfe/off,on,16.5 2006.257.06:31:46.69/ifatt/23,28,28,28 2006.257.06:31:47.08/fmout-gps/S +4.50E-07 2006.257.06:31:47.12:!2006.257.06:35:23 2006.257.06:35:23.01:data_valid=off 2006.257.06:35:23.01:"et 2006.257.06:35:23.01:!+3s 2006.257.06:35:26.02:"tape 2006.257.06:35:26.02:postob 2006.257.06:35:26.12/cable/+6.4790E-03 2006.257.06:35:26.12/wx/20.59,1012.3,89 2006.257.06:35:27.08/fmout-gps/S +4.50E-07 2006.257.06:35:27.08:scan_name=257-0638,jd0609,40 2006.257.06:35:27.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.257.06:35:28.14#flagr#flagr/antenna,new-source 2006.257.06:35:28.14:checkk5 2006.257.06:35:28.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:35:28.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:35:29.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:35:29.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:35:30.13/chk_obsdata//k5ts1/T2570631??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.06:35:30.50/chk_obsdata//k5ts2/T2570631??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.06:35:30.91/chk_obsdata//k5ts3/T2570631??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.06:35:31.32/chk_obsdata//k5ts4/T2570631??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.06:35:32.06/k5log//k5ts1_log_newline 2006.257.06:35:32.80/k5log//k5ts2_log_newline 2006.257.06:35:33.54/k5log//k5ts3_log_newline 2006.257.06:35:34.26/k5log//k5ts4_log_newline 2006.257.06:35:34.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:35:34.28:setupk4=1 2006.257.06:35:34.28$setupk4/echo=on 2006.257.06:35:34.28$setupk4/pcalon 2006.257.06:35:34.28$pcalon/"no phase cal control is implemented here 2006.257.06:35:34.28$setupk4/"tpicd=stop 2006.257.06:35:34.28$setupk4/"rec=synch_on 2006.257.06:35:34.28$setupk4/"rec_mode=128 2006.257.06:35:34.28$setupk4/!* 2006.257.06:35:34.28$setupk4/recpk4 2006.257.06:35:34.28$recpk4/recpatch= 2006.257.06:35:34.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:35:34.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:35:34.29$setupk4/vck44 2006.257.06:35:34.29$vck44/valo=1,524.99 2006.257.06:35:34.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.06:35:34.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.06:35:34.29#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:34.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:34.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:34.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:34.29#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:35:34.29#ibcon#first serial, iclass 13, count 0 2006.257.06:35:34.29#ibcon#enter sib2, iclass 13, count 0 2006.257.06:35:34.29#ibcon#flushed, iclass 13, count 0 2006.257.06:35:34.29#ibcon#about to write, iclass 13, count 0 2006.257.06:35:34.29#ibcon#wrote, iclass 13, count 0 2006.257.06:35:34.29#ibcon#about to read 3, iclass 13, count 0 2006.257.06:35:34.31#ibcon#read 3, iclass 13, count 0 2006.257.06:35:34.31#ibcon#about to read 4, iclass 13, count 0 2006.257.06:35:34.31#ibcon#read 4, iclass 13, count 0 2006.257.06:35:34.31#ibcon#about to read 5, iclass 13, count 0 2006.257.06:35:34.31#ibcon#read 5, iclass 13, count 0 2006.257.06:35:34.31#ibcon#about to read 6, iclass 13, count 0 2006.257.06:35:34.31#ibcon#read 6, iclass 13, count 0 2006.257.06:35:34.31#ibcon#end of sib2, iclass 13, count 0 2006.257.06:35:34.31#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:35:34.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:35:34.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:35:34.31#ibcon#*before write, iclass 13, count 0 2006.257.06:35:34.31#ibcon#enter sib2, iclass 13, count 0 2006.257.06:35:34.31#ibcon#flushed, iclass 13, count 0 2006.257.06:35:34.31#ibcon#about to write, iclass 13, count 0 2006.257.06:35:34.31#ibcon#wrote, iclass 13, count 0 2006.257.06:35:34.31#ibcon#about to read 3, iclass 13, count 0 2006.257.06:35:34.36#ibcon#read 3, iclass 13, count 0 2006.257.06:35:34.36#ibcon#about to read 4, iclass 13, count 0 2006.257.06:35:34.36#ibcon#read 4, iclass 13, count 0 2006.257.06:35:34.36#ibcon#about to read 5, iclass 13, count 0 2006.257.06:35:34.36#ibcon#read 5, iclass 13, count 0 2006.257.06:35:34.36#ibcon#about to read 6, iclass 13, count 0 2006.257.06:35:34.36#ibcon#read 6, iclass 13, count 0 2006.257.06:35:34.36#ibcon#end of sib2, iclass 13, count 0 2006.257.06:35:34.36#ibcon#*after write, iclass 13, count 0 2006.257.06:35:34.36#ibcon#*before return 0, iclass 13, count 0 2006.257.06:35:34.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:34.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:34.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:35:34.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:35:34.36$vck44/va=1,8 2006.257.06:35:34.36#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.06:35:34.36#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.06:35:34.36#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:34.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:34.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:34.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:34.36#ibcon#enter wrdev, iclass 15, count 2 2006.257.06:35:34.36#ibcon#first serial, iclass 15, count 2 2006.257.06:35:34.36#ibcon#enter sib2, iclass 15, count 2 2006.257.06:35:34.36#ibcon#flushed, iclass 15, count 2 2006.257.06:35:34.36#ibcon#about to write, iclass 15, count 2 2006.257.06:35:34.36#ibcon#wrote, iclass 15, count 2 2006.257.06:35:34.36#ibcon#about to read 3, iclass 15, count 2 2006.257.06:35:34.38#ibcon#read 3, iclass 15, count 2 2006.257.06:35:34.38#ibcon#about to read 4, iclass 15, count 2 2006.257.06:35:34.38#ibcon#read 4, iclass 15, count 2 2006.257.06:35:34.38#ibcon#about to read 5, iclass 15, count 2 2006.257.06:35:34.38#ibcon#read 5, iclass 15, count 2 2006.257.06:35:34.38#ibcon#about to read 6, iclass 15, count 2 2006.257.06:35:34.38#ibcon#read 6, iclass 15, count 2 2006.257.06:35:34.38#ibcon#end of sib2, iclass 15, count 2 2006.257.06:35:34.38#ibcon#*mode == 0, iclass 15, count 2 2006.257.06:35:34.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.06:35:34.38#ibcon#[25=AT01-08\r\n] 2006.257.06:35:34.38#ibcon#*before write, iclass 15, count 2 2006.257.06:35:34.38#ibcon#enter sib2, iclass 15, count 2 2006.257.06:35:34.38#ibcon#flushed, iclass 15, count 2 2006.257.06:35:34.38#ibcon#about to write, iclass 15, count 2 2006.257.06:35:34.38#ibcon#wrote, iclass 15, count 2 2006.257.06:35:34.38#ibcon#about to read 3, iclass 15, count 2 2006.257.06:35:34.41#ibcon#read 3, iclass 15, count 2 2006.257.06:35:34.41#ibcon#about to read 4, iclass 15, count 2 2006.257.06:35:34.41#ibcon#read 4, iclass 15, count 2 2006.257.06:35:34.41#ibcon#about to read 5, iclass 15, count 2 2006.257.06:35:34.41#ibcon#read 5, iclass 15, count 2 2006.257.06:35:34.41#ibcon#about to read 6, iclass 15, count 2 2006.257.06:35:34.41#ibcon#read 6, iclass 15, count 2 2006.257.06:35:34.41#ibcon#end of sib2, iclass 15, count 2 2006.257.06:35:34.41#ibcon#*after write, iclass 15, count 2 2006.257.06:35:34.41#ibcon#*before return 0, iclass 15, count 2 2006.257.06:35:34.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:34.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:34.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.06:35:34.41#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:34.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:34.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:34.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:34.53#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:35:34.53#ibcon#first serial, iclass 15, count 0 2006.257.06:35:34.53#ibcon#enter sib2, iclass 15, count 0 2006.257.06:35:34.53#ibcon#flushed, iclass 15, count 0 2006.257.06:35:34.53#ibcon#about to write, iclass 15, count 0 2006.257.06:35:34.53#ibcon#wrote, iclass 15, count 0 2006.257.06:35:34.53#ibcon#about to read 3, iclass 15, count 0 2006.257.06:35:34.55#ibcon#read 3, iclass 15, count 0 2006.257.06:35:34.55#ibcon#about to read 4, iclass 15, count 0 2006.257.06:35:34.55#ibcon#read 4, iclass 15, count 0 2006.257.06:35:34.55#ibcon#about to read 5, iclass 15, count 0 2006.257.06:35:34.55#ibcon#read 5, iclass 15, count 0 2006.257.06:35:34.55#ibcon#about to read 6, iclass 15, count 0 2006.257.06:35:34.55#ibcon#read 6, iclass 15, count 0 2006.257.06:35:34.55#ibcon#end of sib2, iclass 15, count 0 2006.257.06:35:34.55#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:35:34.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:35:34.55#ibcon#[25=USB\r\n] 2006.257.06:35:34.55#ibcon#*before write, iclass 15, count 0 2006.257.06:35:34.55#ibcon#enter sib2, iclass 15, count 0 2006.257.06:35:34.55#ibcon#flushed, iclass 15, count 0 2006.257.06:35:34.55#ibcon#about to write, iclass 15, count 0 2006.257.06:35:34.55#ibcon#wrote, iclass 15, count 0 2006.257.06:35:34.55#ibcon#about to read 3, iclass 15, count 0 2006.257.06:35:34.58#ibcon#read 3, iclass 15, count 0 2006.257.06:35:34.58#ibcon#about to read 4, iclass 15, count 0 2006.257.06:35:34.58#ibcon#read 4, iclass 15, count 0 2006.257.06:35:34.58#ibcon#about to read 5, iclass 15, count 0 2006.257.06:35:34.58#ibcon#read 5, iclass 15, count 0 2006.257.06:35:34.58#ibcon#about to read 6, iclass 15, count 0 2006.257.06:35:34.58#ibcon#read 6, iclass 15, count 0 2006.257.06:35:34.58#ibcon#end of sib2, iclass 15, count 0 2006.257.06:35:34.58#ibcon#*after write, iclass 15, count 0 2006.257.06:35:34.58#ibcon#*before return 0, iclass 15, count 0 2006.257.06:35:34.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:34.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:34.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:35:34.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:35:34.58$vck44/valo=2,534.99 2006.257.06:35:34.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.06:35:34.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.06:35:34.58#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:34.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:34.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:34.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:34.58#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:35:34.58#ibcon#first serial, iclass 17, count 0 2006.257.06:35:34.58#ibcon#enter sib2, iclass 17, count 0 2006.257.06:35:34.58#ibcon#flushed, iclass 17, count 0 2006.257.06:35:34.58#ibcon#about to write, iclass 17, count 0 2006.257.06:35:34.58#ibcon#wrote, iclass 17, count 0 2006.257.06:35:34.58#ibcon#about to read 3, iclass 17, count 0 2006.257.06:35:34.60#ibcon#read 3, iclass 17, count 0 2006.257.06:35:34.60#ibcon#about to read 4, iclass 17, count 0 2006.257.06:35:34.60#ibcon#read 4, iclass 17, count 0 2006.257.06:35:34.60#ibcon#about to read 5, iclass 17, count 0 2006.257.06:35:34.60#ibcon#read 5, iclass 17, count 0 2006.257.06:35:34.60#ibcon#about to read 6, iclass 17, count 0 2006.257.06:35:34.60#ibcon#read 6, iclass 17, count 0 2006.257.06:35:34.60#ibcon#end of sib2, iclass 17, count 0 2006.257.06:35:34.60#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:35:34.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:35:34.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:35:34.60#ibcon#*before write, iclass 17, count 0 2006.257.06:35:34.60#ibcon#enter sib2, iclass 17, count 0 2006.257.06:35:34.60#ibcon#flushed, iclass 17, count 0 2006.257.06:35:34.60#ibcon#about to write, iclass 17, count 0 2006.257.06:35:34.60#ibcon#wrote, iclass 17, count 0 2006.257.06:35:34.60#ibcon#about to read 3, iclass 17, count 0 2006.257.06:35:34.64#ibcon#read 3, iclass 17, count 0 2006.257.06:35:34.64#ibcon#about to read 4, iclass 17, count 0 2006.257.06:35:34.64#ibcon#read 4, iclass 17, count 0 2006.257.06:35:34.64#ibcon#about to read 5, iclass 17, count 0 2006.257.06:35:34.64#ibcon#read 5, iclass 17, count 0 2006.257.06:35:34.64#ibcon#about to read 6, iclass 17, count 0 2006.257.06:35:34.64#ibcon#read 6, iclass 17, count 0 2006.257.06:35:34.64#ibcon#end of sib2, iclass 17, count 0 2006.257.06:35:34.64#ibcon#*after write, iclass 17, count 0 2006.257.06:35:34.64#ibcon#*before return 0, iclass 17, count 0 2006.257.06:35:34.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:34.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:34.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:35:34.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:35:34.64$vck44/va=2,7 2006.257.06:35:34.64#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.06:35:34.64#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.06:35:34.64#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:34.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:34.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:34.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:34.70#ibcon#enter wrdev, iclass 19, count 2 2006.257.06:35:34.70#ibcon#first serial, iclass 19, count 2 2006.257.06:35:34.70#ibcon#enter sib2, iclass 19, count 2 2006.257.06:35:34.70#ibcon#flushed, iclass 19, count 2 2006.257.06:35:34.70#ibcon#about to write, iclass 19, count 2 2006.257.06:35:34.70#ibcon#wrote, iclass 19, count 2 2006.257.06:35:34.70#ibcon#about to read 3, iclass 19, count 2 2006.257.06:35:34.72#ibcon#read 3, iclass 19, count 2 2006.257.06:35:34.72#ibcon#about to read 4, iclass 19, count 2 2006.257.06:35:34.72#ibcon#read 4, iclass 19, count 2 2006.257.06:35:34.72#ibcon#about to read 5, iclass 19, count 2 2006.257.06:35:34.72#ibcon#read 5, iclass 19, count 2 2006.257.06:35:34.72#ibcon#about to read 6, iclass 19, count 2 2006.257.06:35:34.72#ibcon#read 6, iclass 19, count 2 2006.257.06:35:34.72#ibcon#end of sib2, iclass 19, count 2 2006.257.06:35:34.72#ibcon#*mode == 0, iclass 19, count 2 2006.257.06:35:34.72#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.06:35:34.72#ibcon#[25=AT02-07\r\n] 2006.257.06:35:34.72#ibcon#*before write, iclass 19, count 2 2006.257.06:35:34.72#ibcon#enter sib2, iclass 19, count 2 2006.257.06:35:34.72#ibcon#flushed, iclass 19, count 2 2006.257.06:35:34.72#ibcon#about to write, iclass 19, count 2 2006.257.06:35:34.72#ibcon#wrote, iclass 19, count 2 2006.257.06:35:34.72#ibcon#about to read 3, iclass 19, count 2 2006.257.06:35:34.75#ibcon#read 3, iclass 19, count 2 2006.257.06:35:34.75#ibcon#about to read 4, iclass 19, count 2 2006.257.06:35:34.75#ibcon#read 4, iclass 19, count 2 2006.257.06:35:34.75#ibcon#about to read 5, iclass 19, count 2 2006.257.06:35:34.75#ibcon#read 5, iclass 19, count 2 2006.257.06:35:34.75#ibcon#about to read 6, iclass 19, count 2 2006.257.06:35:34.75#ibcon#read 6, iclass 19, count 2 2006.257.06:35:34.75#ibcon#end of sib2, iclass 19, count 2 2006.257.06:35:34.75#ibcon#*after write, iclass 19, count 2 2006.257.06:35:34.75#ibcon#*before return 0, iclass 19, count 2 2006.257.06:35:34.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:34.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:34.75#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.06:35:34.75#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:34.75#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:34.87#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:34.87#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:34.87#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:35:34.87#ibcon#first serial, iclass 19, count 0 2006.257.06:35:34.87#ibcon#enter sib2, iclass 19, count 0 2006.257.06:35:34.87#ibcon#flushed, iclass 19, count 0 2006.257.06:35:34.87#ibcon#about to write, iclass 19, count 0 2006.257.06:35:34.87#ibcon#wrote, iclass 19, count 0 2006.257.06:35:34.87#ibcon#about to read 3, iclass 19, count 0 2006.257.06:35:34.89#ibcon#read 3, iclass 19, count 0 2006.257.06:35:34.89#ibcon#about to read 4, iclass 19, count 0 2006.257.06:35:34.89#ibcon#read 4, iclass 19, count 0 2006.257.06:35:34.89#ibcon#about to read 5, iclass 19, count 0 2006.257.06:35:34.89#ibcon#read 5, iclass 19, count 0 2006.257.06:35:34.89#ibcon#about to read 6, iclass 19, count 0 2006.257.06:35:34.89#ibcon#read 6, iclass 19, count 0 2006.257.06:35:34.89#ibcon#end of sib2, iclass 19, count 0 2006.257.06:35:34.89#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:35:34.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:35:34.89#ibcon#[25=USB\r\n] 2006.257.06:35:34.89#ibcon#*before write, iclass 19, count 0 2006.257.06:35:34.89#ibcon#enter sib2, iclass 19, count 0 2006.257.06:35:34.89#ibcon#flushed, iclass 19, count 0 2006.257.06:35:34.89#ibcon#about to write, iclass 19, count 0 2006.257.06:35:34.89#ibcon#wrote, iclass 19, count 0 2006.257.06:35:34.89#ibcon#about to read 3, iclass 19, count 0 2006.257.06:35:34.92#ibcon#read 3, iclass 19, count 0 2006.257.06:35:34.92#ibcon#about to read 4, iclass 19, count 0 2006.257.06:35:34.92#ibcon#read 4, iclass 19, count 0 2006.257.06:35:34.92#ibcon#about to read 5, iclass 19, count 0 2006.257.06:35:34.92#ibcon#read 5, iclass 19, count 0 2006.257.06:35:34.92#ibcon#about to read 6, iclass 19, count 0 2006.257.06:35:34.92#ibcon#read 6, iclass 19, count 0 2006.257.06:35:34.92#ibcon#end of sib2, iclass 19, count 0 2006.257.06:35:34.92#ibcon#*after write, iclass 19, count 0 2006.257.06:35:34.92#ibcon#*before return 0, iclass 19, count 0 2006.257.06:35:34.92#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:34.92#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:34.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:35:34.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:35:34.92$vck44/valo=3,564.99 2006.257.06:35:34.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.06:35:34.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.06:35:34.92#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:34.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:34.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:34.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:34.92#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:35:34.92#ibcon#first serial, iclass 21, count 0 2006.257.06:35:34.92#ibcon#enter sib2, iclass 21, count 0 2006.257.06:35:34.92#ibcon#flushed, iclass 21, count 0 2006.257.06:35:34.92#ibcon#about to write, iclass 21, count 0 2006.257.06:35:34.92#ibcon#wrote, iclass 21, count 0 2006.257.06:35:34.92#ibcon#about to read 3, iclass 21, count 0 2006.257.06:35:34.94#ibcon#read 3, iclass 21, count 0 2006.257.06:35:34.94#ibcon#about to read 4, iclass 21, count 0 2006.257.06:35:34.94#ibcon#read 4, iclass 21, count 0 2006.257.06:35:34.94#ibcon#about to read 5, iclass 21, count 0 2006.257.06:35:34.94#ibcon#read 5, iclass 21, count 0 2006.257.06:35:34.94#ibcon#about to read 6, iclass 21, count 0 2006.257.06:35:34.94#ibcon#read 6, iclass 21, count 0 2006.257.06:35:34.94#ibcon#end of sib2, iclass 21, count 0 2006.257.06:35:34.94#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:35:34.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:35:34.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:35:34.94#ibcon#*before write, iclass 21, count 0 2006.257.06:35:34.94#ibcon#enter sib2, iclass 21, count 0 2006.257.06:35:34.94#ibcon#flushed, iclass 21, count 0 2006.257.06:35:34.94#ibcon#about to write, iclass 21, count 0 2006.257.06:35:34.94#ibcon#wrote, iclass 21, count 0 2006.257.06:35:34.94#ibcon#about to read 3, iclass 21, count 0 2006.257.06:35:34.98#ibcon#read 3, iclass 21, count 0 2006.257.06:35:34.98#ibcon#about to read 4, iclass 21, count 0 2006.257.06:35:34.98#ibcon#read 4, iclass 21, count 0 2006.257.06:35:34.98#ibcon#about to read 5, iclass 21, count 0 2006.257.06:35:34.98#ibcon#read 5, iclass 21, count 0 2006.257.06:35:34.98#ibcon#about to read 6, iclass 21, count 0 2006.257.06:35:34.98#ibcon#read 6, iclass 21, count 0 2006.257.06:35:34.98#ibcon#end of sib2, iclass 21, count 0 2006.257.06:35:34.98#ibcon#*after write, iclass 21, count 0 2006.257.06:35:34.98#ibcon#*before return 0, iclass 21, count 0 2006.257.06:35:34.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:34.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:34.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:35:34.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:35:34.98$vck44/va=3,8 2006.257.06:35:34.98#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.06:35:34.98#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.06:35:34.98#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:34.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:35.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:35.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:35.04#ibcon#enter wrdev, iclass 23, count 2 2006.257.06:35:35.04#ibcon#first serial, iclass 23, count 2 2006.257.06:35:35.04#ibcon#enter sib2, iclass 23, count 2 2006.257.06:35:35.04#ibcon#flushed, iclass 23, count 2 2006.257.06:35:35.04#ibcon#about to write, iclass 23, count 2 2006.257.06:35:35.04#ibcon#wrote, iclass 23, count 2 2006.257.06:35:35.04#ibcon#about to read 3, iclass 23, count 2 2006.257.06:35:35.06#ibcon#read 3, iclass 23, count 2 2006.257.06:35:35.06#ibcon#about to read 4, iclass 23, count 2 2006.257.06:35:35.06#ibcon#read 4, iclass 23, count 2 2006.257.06:35:35.06#ibcon#about to read 5, iclass 23, count 2 2006.257.06:35:35.06#ibcon#read 5, iclass 23, count 2 2006.257.06:35:35.06#ibcon#about to read 6, iclass 23, count 2 2006.257.06:35:35.06#ibcon#read 6, iclass 23, count 2 2006.257.06:35:35.06#ibcon#end of sib2, iclass 23, count 2 2006.257.06:35:35.06#ibcon#*mode == 0, iclass 23, count 2 2006.257.06:35:35.06#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.06:35:35.06#ibcon#[25=AT03-08\r\n] 2006.257.06:35:35.06#ibcon#*before write, iclass 23, count 2 2006.257.06:35:35.06#ibcon#enter sib2, iclass 23, count 2 2006.257.06:35:35.06#ibcon#flushed, iclass 23, count 2 2006.257.06:35:35.06#ibcon#about to write, iclass 23, count 2 2006.257.06:35:35.06#ibcon#wrote, iclass 23, count 2 2006.257.06:35:35.06#ibcon#about to read 3, iclass 23, count 2 2006.257.06:35:35.09#ibcon#read 3, iclass 23, count 2 2006.257.06:35:35.09#ibcon#about to read 4, iclass 23, count 2 2006.257.06:35:35.09#ibcon#read 4, iclass 23, count 2 2006.257.06:35:35.09#ibcon#about to read 5, iclass 23, count 2 2006.257.06:35:35.09#ibcon#read 5, iclass 23, count 2 2006.257.06:35:35.09#ibcon#about to read 6, iclass 23, count 2 2006.257.06:35:35.09#ibcon#read 6, iclass 23, count 2 2006.257.06:35:35.09#ibcon#end of sib2, iclass 23, count 2 2006.257.06:35:35.09#ibcon#*after write, iclass 23, count 2 2006.257.06:35:35.09#ibcon#*before return 0, iclass 23, count 2 2006.257.06:35:35.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:35.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:35.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.06:35:35.09#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:35.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:35.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:35.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:35.21#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:35:35.21#ibcon#first serial, iclass 23, count 0 2006.257.06:35:35.21#ibcon#enter sib2, iclass 23, count 0 2006.257.06:35:35.21#ibcon#flushed, iclass 23, count 0 2006.257.06:35:35.21#ibcon#about to write, iclass 23, count 0 2006.257.06:35:35.21#ibcon#wrote, iclass 23, count 0 2006.257.06:35:35.21#ibcon#about to read 3, iclass 23, count 0 2006.257.06:35:35.23#ibcon#read 3, iclass 23, count 0 2006.257.06:35:35.23#ibcon#about to read 4, iclass 23, count 0 2006.257.06:35:35.23#ibcon#read 4, iclass 23, count 0 2006.257.06:35:35.23#ibcon#about to read 5, iclass 23, count 0 2006.257.06:35:35.23#ibcon#read 5, iclass 23, count 0 2006.257.06:35:35.23#ibcon#about to read 6, iclass 23, count 0 2006.257.06:35:35.23#ibcon#read 6, iclass 23, count 0 2006.257.06:35:35.23#ibcon#end of sib2, iclass 23, count 0 2006.257.06:35:35.23#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:35:35.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:35:35.23#ibcon#[25=USB\r\n] 2006.257.06:35:35.23#ibcon#*before write, iclass 23, count 0 2006.257.06:35:35.23#ibcon#enter sib2, iclass 23, count 0 2006.257.06:35:35.23#ibcon#flushed, iclass 23, count 0 2006.257.06:35:35.23#ibcon#about to write, iclass 23, count 0 2006.257.06:35:35.23#ibcon#wrote, iclass 23, count 0 2006.257.06:35:35.23#ibcon#about to read 3, iclass 23, count 0 2006.257.06:35:35.26#ibcon#read 3, iclass 23, count 0 2006.257.06:35:35.26#ibcon#about to read 4, iclass 23, count 0 2006.257.06:35:35.26#ibcon#read 4, iclass 23, count 0 2006.257.06:35:35.26#ibcon#about to read 5, iclass 23, count 0 2006.257.06:35:35.26#ibcon#read 5, iclass 23, count 0 2006.257.06:35:35.26#ibcon#about to read 6, iclass 23, count 0 2006.257.06:35:35.26#ibcon#read 6, iclass 23, count 0 2006.257.06:35:35.26#ibcon#end of sib2, iclass 23, count 0 2006.257.06:35:35.26#ibcon#*after write, iclass 23, count 0 2006.257.06:35:35.26#ibcon#*before return 0, iclass 23, count 0 2006.257.06:35:35.26#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:35.26#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:35.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:35:35.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:35:35.26$vck44/valo=4,624.99 2006.257.06:35:35.26#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.06:35:35.26#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.06:35:35.26#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:35.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:35:35.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:35:35.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:35:35.26#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:35:35.26#ibcon#first serial, iclass 25, count 0 2006.257.06:35:35.26#ibcon#enter sib2, iclass 25, count 0 2006.257.06:35:35.26#ibcon#flushed, iclass 25, count 0 2006.257.06:35:35.26#ibcon#about to write, iclass 25, count 0 2006.257.06:35:35.26#ibcon#wrote, iclass 25, count 0 2006.257.06:35:35.26#ibcon#about to read 3, iclass 25, count 0 2006.257.06:35:35.28#ibcon#read 3, iclass 25, count 0 2006.257.06:35:35.28#ibcon#about to read 4, iclass 25, count 0 2006.257.06:35:35.28#ibcon#read 4, iclass 25, count 0 2006.257.06:35:35.28#ibcon#about to read 5, iclass 25, count 0 2006.257.06:35:35.28#ibcon#read 5, iclass 25, count 0 2006.257.06:35:35.28#ibcon#about to read 6, iclass 25, count 0 2006.257.06:35:35.28#ibcon#read 6, iclass 25, count 0 2006.257.06:35:35.28#ibcon#end of sib2, iclass 25, count 0 2006.257.06:35:35.28#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:35:35.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:35:35.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:35:35.28#ibcon#*before write, iclass 25, count 0 2006.257.06:35:35.28#ibcon#enter sib2, iclass 25, count 0 2006.257.06:35:35.28#ibcon#flushed, iclass 25, count 0 2006.257.06:35:35.28#ibcon#about to write, iclass 25, count 0 2006.257.06:35:35.28#ibcon#wrote, iclass 25, count 0 2006.257.06:35:35.28#ibcon#about to read 3, iclass 25, count 0 2006.257.06:35:35.32#ibcon#read 3, iclass 25, count 0 2006.257.06:35:35.32#ibcon#about to read 4, iclass 25, count 0 2006.257.06:35:35.32#ibcon#read 4, iclass 25, count 0 2006.257.06:35:35.32#ibcon#about to read 5, iclass 25, count 0 2006.257.06:35:35.32#ibcon#read 5, iclass 25, count 0 2006.257.06:35:35.32#ibcon#about to read 6, iclass 25, count 0 2006.257.06:35:35.32#ibcon#read 6, iclass 25, count 0 2006.257.06:35:35.32#ibcon#end of sib2, iclass 25, count 0 2006.257.06:35:35.32#ibcon#*after write, iclass 25, count 0 2006.257.06:35:35.32#ibcon#*before return 0, iclass 25, count 0 2006.257.06:35:35.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:35:35.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:35:35.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:35:35.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:35:35.32$vck44/va=4,7 2006.257.06:35:35.32#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.06:35:35.32#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.06:35:35.32#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:35.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:35:35.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:35:35.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:35:35.38#ibcon#enter wrdev, iclass 27, count 2 2006.257.06:35:35.38#ibcon#first serial, iclass 27, count 2 2006.257.06:35:35.38#ibcon#enter sib2, iclass 27, count 2 2006.257.06:35:35.38#ibcon#flushed, iclass 27, count 2 2006.257.06:35:35.38#ibcon#about to write, iclass 27, count 2 2006.257.06:35:35.38#ibcon#wrote, iclass 27, count 2 2006.257.06:35:35.38#ibcon#about to read 3, iclass 27, count 2 2006.257.06:35:35.40#ibcon#read 3, iclass 27, count 2 2006.257.06:35:35.40#ibcon#about to read 4, iclass 27, count 2 2006.257.06:35:35.40#ibcon#read 4, iclass 27, count 2 2006.257.06:35:35.40#ibcon#about to read 5, iclass 27, count 2 2006.257.06:35:35.40#ibcon#read 5, iclass 27, count 2 2006.257.06:35:35.40#ibcon#about to read 6, iclass 27, count 2 2006.257.06:35:35.40#ibcon#read 6, iclass 27, count 2 2006.257.06:35:35.40#ibcon#end of sib2, iclass 27, count 2 2006.257.06:35:35.40#ibcon#*mode == 0, iclass 27, count 2 2006.257.06:35:35.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.06:35:35.40#ibcon#[25=AT04-07\r\n] 2006.257.06:35:35.40#ibcon#*before write, iclass 27, count 2 2006.257.06:35:35.40#ibcon#enter sib2, iclass 27, count 2 2006.257.06:35:35.40#ibcon#flushed, iclass 27, count 2 2006.257.06:35:35.40#ibcon#about to write, iclass 27, count 2 2006.257.06:35:35.40#ibcon#wrote, iclass 27, count 2 2006.257.06:35:35.40#ibcon#about to read 3, iclass 27, count 2 2006.257.06:35:35.43#ibcon#read 3, iclass 27, count 2 2006.257.06:35:35.43#ibcon#about to read 4, iclass 27, count 2 2006.257.06:35:35.43#ibcon#read 4, iclass 27, count 2 2006.257.06:35:35.43#ibcon#about to read 5, iclass 27, count 2 2006.257.06:35:35.43#ibcon#read 5, iclass 27, count 2 2006.257.06:35:35.43#ibcon#about to read 6, iclass 27, count 2 2006.257.06:35:35.43#ibcon#read 6, iclass 27, count 2 2006.257.06:35:35.43#ibcon#end of sib2, iclass 27, count 2 2006.257.06:35:35.43#ibcon#*after write, iclass 27, count 2 2006.257.06:35:35.43#ibcon#*before return 0, iclass 27, count 2 2006.257.06:35:35.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:35:35.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:35:35.43#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.06:35:35.43#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:35.43#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:35:35.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:35:35.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:35:35.55#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:35:35.55#ibcon#first serial, iclass 27, count 0 2006.257.06:35:35.55#ibcon#enter sib2, iclass 27, count 0 2006.257.06:35:35.55#ibcon#flushed, iclass 27, count 0 2006.257.06:35:35.55#ibcon#about to write, iclass 27, count 0 2006.257.06:35:35.55#ibcon#wrote, iclass 27, count 0 2006.257.06:35:35.55#ibcon#about to read 3, iclass 27, count 0 2006.257.06:35:35.57#ibcon#read 3, iclass 27, count 0 2006.257.06:35:35.57#ibcon#about to read 4, iclass 27, count 0 2006.257.06:35:35.57#ibcon#read 4, iclass 27, count 0 2006.257.06:35:35.57#ibcon#about to read 5, iclass 27, count 0 2006.257.06:35:35.57#ibcon#read 5, iclass 27, count 0 2006.257.06:35:35.57#ibcon#about to read 6, iclass 27, count 0 2006.257.06:35:35.57#ibcon#read 6, iclass 27, count 0 2006.257.06:35:35.57#ibcon#end of sib2, iclass 27, count 0 2006.257.06:35:35.57#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:35:35.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:35:35.57#ibcon#[25=USB\r\n] 2006.257.06:35:35.57#ibcon#*before write, iclass 27, count 0 2006.257.06:35:35.57#ibcon#enter sib2, iclass 27, count 0 2006.257.06:35:35.57#ibcon#flushed, iclass 27, count 0 2006.257.06:35:35.57#ibcon#about to write, iclass 27, count 0 2006.257.06:35:35.57#ibcon#wrote, iclass 27, count 0 2006.257.06:35:35.57#ibcon#about to read 3, iclass 27, count 0 2006.257.06:35:35.60#ibcon#read 3, iclass 27, count 0 2006.257.06:35:35.60#ibcon#about to read 4, iclass 27, count 0 2006.257.06:35:35.60#ibcon#read 4, iclass 27, count 0 2006.257.06:35:35.60#ibcon#about to read 5, iclass 27, count 0 2006.257.06:35:35.60#ibcon#read 5, iclass 27, count 0 2006.257.06:35:35.60#ibcon#about to read 6, iclass 27, count 0 2006.257.06:35:35.60#ibcon#read 6, iclass 27, count 0 2006.257.06:35:35.60#ibcon#end of sib2, iclass 27, count 0 2006.257.06:35:35.60#ibcon#*after write, iclass 27, count 0 2006.257.06:35:35.60#ibcon#*before return 0, iclass 27, count 0 2006.257.06:35:35.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:35:35.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:35:35.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:35:35.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:35:35.60$vck44/valo=5,734.99 2006.257.06:35:35.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.06:35:35.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.06:35:35.60#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:35.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:35.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:35.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:35.60#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:35:35.60#ibcon#first serial, iclass 29, count 0 2006.257.06:35:35.60#ibcon#enter sib2, iclass 29, count 0 2006.257.06:35:35.60#ibcon#flushed, iclass 29, count 0 2006.257.06:35:35.60#ibcon#about to write, iclass 29, count 0 2006.257.06:35:35.60#ibcon#wrote, iclass 29, count 0 2006.257.06:35:35.60#ibcon#about to read 3, iclass 29, count 0 2006.257.06:35:35.62#ibcon#read 3, iclass 29, count 0 2006.257.06:35:35.62#ibcon#about to read 4, iclass 29, count 0 2006.257.06:35:35.62#ibcon#read 4, iclass 29, count 0 2006.257.06:35:35.62#ibcon#about to read 5, iclass 29, count 0 2006.257.06:35:35.62#ibcon#read 5, iclass 29, count 0 2006.257.06:35:35.62#ibcon#about to read 6, iclass 29, count 0 2006.257.06:35:35.62#ibcon#read 6, iclass 29, count 0 2006.257.06:35:35.62#ibcon#end of sib2, iclass 29, count 0 2006.257.06:35:35.62#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:35:35.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:35:35.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:35:35.62#ibcon#*before write, iclass 29, count 0 2006.257.06:35:35.62#ibcon#enter sib2, iclass 29, count 0 2006.257.06:35:35.62#ibcon#flushed, iclass 29, count 0 2006.257.06:35:35.62#ibcon#about to write, iclass 29, count 0 2006.257.06:35:35.62#ibcon#wrote, iclass 29, count 0 2006.257.06:35:35.62#ibcon#about to read 3, iclass 29, count 0 2006.257.06:35:35.66#ibcon#read 3, iclass 29, count 0 2006.257.06:35:35.66#ibcon#about to read 4, iclass 29, count 0 2006.257.06:35:35.66#ibcon#read 4, iclass 29, count 0 2006.257.06:35:35.66#ibcon#about to read 5, iclass 29, count 0 2006.257.06:35:35.66#ibcon#read 5, iclass 29, count 0 2006.257.06:35:35.66#ibcon#about to read 6, iclass 29, count 0 2006.257.06:35:35.66#ibcon#read 6, iclass 29, count 0 2006.257.06:35:35.66#ibcon#end of sib2, iclass 29, count 0 2006.257.06:35:35.66#ibcon#*after write, iclass 29, count 0 2006.257.06:35:35.66#ibcon#*before return 0, iclass 29, count 0 2006.257.06:35:35.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:35.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:35.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:35:35.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:35:35.66$vck44/va=5,4 2006.257.06:35:35.66#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.06:35:35.66#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.06:35:35.66#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:35.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:35.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:35.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:35.72#ibcon#enter wrdev, iclass 31, count 2 2006.257.06:35:35.72#ibcon#first serial, iclass 31, count 2 2006.257.06:35:35.72#ibcon#enter sib2, iclass 31, count 2 2006.257.06:35:35.72#ibcon#flushed, iclass 31, count 2 2006.257.06:35:35.72#ibcon#about to write, iclass 31, count 2 2006.257.06:35:35.72#ibcon#wrote, iclass 31, count 2 2006.257.06:35:35.72#ibcon#about to read 3, iclass 31, count 2 2006.257.06:35:35.74#ibcon#read 3, iclass 31, count 2 2006.257.06:35:35.74#ibcon#about to read 4, iclass 31, count 2 2006.257.06:35:35.74#ibcon#read 4, iclass 31, count 2 2006.257.06:35:35.74#ibcon#about to read 5, iclass 31, count 2 2006.257.06:35:35.74#ibcon#read 5, iclass 31, count 2 2006.257.06:35:35.74#ibcon#about to read 6, iclass 31, count 2 2006.257.06:35:35.74#ibcon#read 6, iclass 31, count 2 2006.257.06:35:35.74#ibcon#end of sib2, iclass 31, count 2 2006.257.06:35:35.74#ibcon#*mode == 0, iclass 31, count 2 2006.257.06:35:35.74#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.06:35:35.74#ibcon#[25=AT05-04\r\n] 2006.257.06:35:35.74#ibcon#*before write, iclass 31, count 2 2006.257.06:35:35.74#ibcon#enter sib2, iclass 31, count 2 2006.257.06:35:35.74#ibcon#flushed, iclass 31, count 2 2006.257.06:35:35.74#ibcon#about to write, iclass 31, count 2 2006.257.06:35:35.74#ibcon#wrote, iclass 31, count 2 2006.257.06:35:35.74#ibcon#about to read 3, iclass 31, count 2 2006.257.06:35:35.77#ibcon#read 3, iclass 31, count 2 2006.257.06:35:35.77#ibcon#about to read 4, iclass 31, count 2 2006.257.06:35:35.77#ibcon#read 4, iclass 31, count 2 2006.257.06:35:35.77#ibcon#about to read 5, iclass 31, count 2 2006.257.06:35:35.77#ibcon#read 5, iclass 31, count 2 2006.257.06:35:35.77#ibcon#about to read 6, iclass 31, count 2 2006.257.06:35:35.77#ibcon#read 6, iclass 31, count 2 2006.257.06:35:35.77#ibcon#end of sib2, iclass 31, count 2 2006.257.06:35:35.77#ibcon#*after write, iclass 31, count 2 2006.257.06:35:35.77#ibcon#*before return 0, iclass 31, count 2 2006.257.06:35:35.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:35.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:35.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.06:35:35.77#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:35.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:35.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:35.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:35.89#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:35:35.89#ibcon#first serial, iclass 31, count 0 2006.257.06:35:35.89#ibcon#enter sib2, iclass 31, count 0 2006.257.06:35:35.89#ibcon#flushed, iclass 31, count 0 2006.257.06:35:35.89#ibcon#about to write, iclass 31, count 0 2006.257.06:35:35.89#ibcon#wrote, iclass 31, count 0 2006.257.06:35:35.89#ibcon#about to read 3, iclass 31, count 0 2006.257.06:35:35.91#ibcon#read 3, iclass 31, count 0 2006.257.06:35:35.91#ibcon#about to read 4, iclass 31, count 0 2006.257.06:35:35.91#ibcon#read 4, iclass 31, count 0 2006.257.06:35:35.91#ibcon#about to read 5, iclass 31, count 0 2006.257.06:35:35.91#ibcon#read 5, iclass 31, count 0 2006.257.06:35:35.91#ibcon#about to read 6, iclass 31, count 0 2006.257.06:35:35.91#ibcon#read 6, iclass 31, count 0 2006.257.06:35:35.91#ibcon#end of sib2, iclass 31, count 0 2006.257.06:35:35.91#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:35:35.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:35:35.91#ibcon#[25=USB\r\n] 2006.257.06:35:35.91#ibcon#*before write, iclass 31, count 0 2006.257.06:35:35.91#ibcon#enter sib2, iclass 31, count 0 2006.257.06:35:35.91#ibcon#flushed, iclass 31, count 0 2006.257.06:35:35.91#ibcon#about to write, iclass 31, count 0 2006.257.06:35:35.91#ibcon#wrote, iclass 31, count 0 2006.257.06:35:35.91#ibcon#about to read 3, iclass 31, count 0 2006.257.06:35:35.94#ibcon#read 3, iclass 31, count 0 2006.257.06:35:35.94#ibcon#about to read 4, iclass 31, count 0 2006.257.06:35:35.94#ibcon#read 4, iclass 31, count 0 2006.257.06:35:35.94#ibcon#about to read 5, iclass 31, count 0 2006.257.06:35:35.94#ibcon#read 5, iclass 31, count 0 2006.257.06:35:35.94#ibcon#about to read 6, iclass 31, count 0 2006.257.06:35:35.94#ibcon#read 6, iclass 31, count 0 2006.257.06:35:35.94#ibcon#end of sib2, iclass 31, count 0 2006.257.06:35:35.94#ibcon#*after write, iclass 31, count 0 2006.257.06:35:35.94#ibcon#*before return 0, iclass 31, count 0 2006.257.06:35:35.94#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:35.94#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:35.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:35:35.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:35:35.94$vck44/valo=6,814.99 2006.257.06:35:35.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.06:35:35.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.06:35:35.94#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:35.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:35.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:35.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:35.94#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:35:35.94#ibcon#first serial, iclass 33, count 0 2006.257.06:35:35.94#ibcon#enter sib2, iclass 33, count 0 2006.257.06:35:35.94#ibcon#flushed, iclass 33, count 0 2006.257.06:35:35.94#ibcon#about to write, iclass 33, count 0 2006.257.06:35:35.94#ibcon#wrote, iclass 33, count 0 2006.257.06:35:35.94#ibcon#about to read 3, iclass 33, count 0 2006.257.06:35:35.96#ibcon#read 3, iclass 33, count 0 2006.257.06:35:35.96#ibcon#about to read 4, iclass 33, count 0 2006.257.06:35:35.96#ibcon#read 4, iclass 33, count 0 2006.257.06:35:35.96#ibcon#about to read 5, iclass 33, count 0 2006.257.06:35:35.96#ibcon#read 5, iclass 33, count 0 2006.257.06:35:35.96#ibcon#about to read 6, iclass 33, count 0 2006.257.06:35:35.96#ibcon#read 6, iclass 33, count 0 2006.257.06:35:35.96#ibcon#end of sib2, iclass 33, count 0 2006.257.06:35:35.96#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:35:35.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:35:35.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:35:35.96#ibcon#*before write, iclass 33, count 0 2006.257.06:35:35.96#ibcon#enter sib2, iclass 33, count 0 2006.257.06:35:35.96#ibcon#flushed, iclass 33, count 0 2006.257.06:35:35.96#ibcon#about to write, iclass 33, count 0 2006.257.06:35:35.96#ibcon#wrote, iclass 33, count 0 2006.257.06:35:35.96#ibcon#about to read 3, iclass 33, count 0 2006.257.06:35:36.00#ibcon#read 3, iclass 33, count 0 2006.257.06:35:36.00#ibcon#about to read 4, iclass 33, count 0 2006.257.06:35:36.00#ibcon#read 4, iclass 33, count 0 2006.257.06:35:36.00#ibcon#about to read 5, iclass 33, count 0 2006.257.06:35:36.00#ibcon#read 5, iclass 33, count 0 2006.257.06:35:36.00#ibcon#about to read 6, iclass 33, count 0 2006.257.06:35:36.00#ibcon#read 6, iclass 33, count 0 2006.257.06:35:36.00#ibcon#end of sib2, iclass 33, count 0 2006.257.06:35:36.00#ibcon#*after write, iclass 33, count 0 2006.257.06:35:36.00#ibcon#*before return 0, iclass 33, count 0 2006.257.06:35:36.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:36.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:36.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:35:36.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:35:36.00$vck44/va=6,4 2006.257.06:35:36.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.06:35:36.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.06:35:36.00#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:36.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:36.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:36.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:36.06#ibcon#enter wrdev, iclass 35, count 2 2006.257.06:35:36.06#ibcon#first serial, iclass 35, count 2 2006.257.06:35:36.06#ibcon#enter sib2, iclass 35, count 2 2006.257.06:35:36.06#ibcon#flushed, iclass 35, count 2 2006.257.06:35:36.06#ibcon#about to write, iclass 35, count 2 2006.257.06:35:36.06#ibcon#wrote, iclass 35, count 2 2006.257.06:35:36.06#ibcon#about to read 3, iclass 35, count 2 2006.257.06:35:36.08#ibcon#read 3, iclass 35, count 2 2006.257.06:35:36.08#ibcon#about to read 4, iclass 35, count 2 2006.257.06:35:36.08#ibcon#read 4, iclass 35, count 2 2006.257.06:35:36.08#ibcon#about to read 5, iclass 35, count 2 2006.257.06:35:36.08#ibcon#read 5, iclass 35, count 2 2006.257.06:35:36.08#ibcon#about to read 6, iclass 35, count 2 2006.257.06:35:36.08#ibcon#read 6, iclass 35, count 2 2006.257.06:35:36.08#ibcon#end of sib2, iclass 35, count 2 2006.257.06:35:36.08#ibcon#*mode == 0, iclass 35, count 2 2006.257.06:35:36.08#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.06:35:36.08#ibcon#[25=AT06-04\r\n] 2006.257.06:35:36.08#ibcon#*before write, iclass 35, count 2 2006.257.06:35:36.08#ibcon#enter sib2, iclass 35, count 2 2006.257.06:35:36.08#ibcon#flushed, iclass 35, count 2 2006.257.06:35:36.08#ibcon#about to write, iclass 35, count 2 2006.257.06:35:36.08#ibcon#wrote, iclass 35, count 2 2006.257.06:35:36.08#ibcon#about to read 3, iclass 35, count 2 2006.257.06:35:36.11#ibcon#read 3, iclass 35, count 2 2006.257.06:35:36.11#ibcon#about to read 4, iclass 35, count 2 2006.257.06:35:36.11#ibcon#read 4, iclass 35, count 2 2006.257.06:35:36.11#ibcon#about to read 5, iclass 35, count 2 2006.257.06:35:36.11#ibcon#read 5, iclass 35, count 2 2006.257.06:35:36.11#ibcon#about to read 6, iclass 35, count 2 2006.257.06:35:36.11#ibcon#read 6, iclass 35, count 2 2006.257.06:35:36.11#ibcon#end of sib2, iclass 35, count 2 2006.257.06:35:36.11#ibcon#*after write, iclass 35, count 2 2006.257.06:35:36.11#ibcon#*before return 0, iclass 35, count 2 2006.257.06:35:36.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:36.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:36.11#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.06:35:36.11#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:36.11#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:36.23#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:36.23#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:36.23#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:35:36.23#ibcon#first serial, iclass 35, count 0 2006.257.06:35:36.23#ibcon#enter sib2, iclass 35, count 0 2006.257.06:35:36.23#ibcon#flushed, iclass 35, count 0 2006.257.06:35:36.23#ibcon#about to write, iclass 35, count 0 2006.257.06:35:36.23#ibcon#wrote, iclass 35, count 0 2006.257.06:35:36.23#ibcon#about to read 3, iclass 35, count 0 2006.257.06:35:36.25#ibcon#read 3, iclass 35, count 0 2006.257.06:35:36.25#ibcon#about to read 4, iclass 35, count 0 2006.257.06:35:36.25#ibcon#read 4, iclass 35, count 0 2006.257.06:35:36.25#ibcon#about to read 5, iclass 35, count 0 2006.257.06:35:36.25#ibcon#read 5, iclass 35, count 0 2006.257.06:35:36.25#ibcon#about to read 6, iclass 35, count 0 2006.257.06:35:36.25#ibcon#read 6, iclass 35, count 0 2006.257.06:35:36.25#ibcon#end of sib2, iclass 35, count 0 2006.257.06:35:36.25#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:35:36.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:35:36.25#ibcon#[25=USB\r\n] 2006.257.06:35:36.25#ibcon#*before write, iclass 35, count 0 2006.257.06:35:36.25#ibcon#enter sib2, iclass 35, count 0 2006.257.06:35:36.25#ibcon#flushed, iclass 35, count 0 2006.257.06:35:36.25#ibcon#about to write, iclass 35, count 0 2006.257.06:35:36.25#ibcon#wrote, iclass 35, count 0 2006.257.06:35:36.25#ibcon#about to read 3, iclass 35, count 0 2006.257.06:35:36.28#ibcon#read 3, iclass 35, count 0 2006.257.06:35:36.28#ibcon#about to read 4, iclass 35, count 0 2006.257.06:35:36.28#ibcon#read 4, iclass 35, count 0 2006.257.06:35:36.28#ibcon#about to read 5, iclass 35, count 0 2006.257.06:35:36.28#ibcon#read 5, iclass 35, count 0 2006.257.06:35:36.28#ibcon#about to read 6, iclass 35, count 0 2006.257.06:35:36.28#ibcon#read 6, iclass 35, count 0 2006.257.06:35:36.28#ibcon#end of sib2, iclass 35, count 0 2006.257.06:35:36.28#ibcon#*after write, iclass 35, count 0 2006.257.06:35:36.28#ibcon#*before return 0, iclass 35, count 0 2006.257.06:35:36.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:36.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:36.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:35:36.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:35:36.28$vck44/valo=7,864.99 2006.257.06:35:36.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.06:35:36.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.06:35:36.28#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:36.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:36.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:36.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:36.28#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:35:36.28#ibcon#first serial, iclass 37, count 0 2006.257.06:35:36.28#ibcon#enter sib2, iclass 37, count 0 2006.257.06:35:36.28#ibcon#flushed, iclass 37, count 0 2006.257.06:35:36.28#ibcon#about to write, iclass 37, count 0 2006.257.06:35:36.28#ibcon#wrote, iclass 37, count 0 2006.257.06:35:36.28#ibcon#about to read 3, iclass 37, count 0 2006.257.06:35:36.30#ibcon#read 3, iclass 37, count 0 2006.257.06:35:36.30#ibcon#about to read 4, iclass 37, count 0 2006.257.06:35:36.30#ibcon#read 4, iclass 37, count 0 2006.257.06:35:36.30#ibcon#about to read 5, iclass 37, count 0 2006.257.06:35:36.30#ibcon#read 5, iclass 37, count 0 2006.257.06:35:36.30#ibcon#about to read 6, iclass 37, count 0 2006.257.06:35:36.30#ibcon#read 6, iclass 37, count 0 2006.257.06:35:36.30#ibcon#end of sib2, iclass 37, count 0 2006.257.06:35:36.30#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:35:36.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:35:36.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:35:36.30#ibcon#*before write, iclass 37, count 0 2006.257.06:35:36.30#ibcon#enter sib2, iclass 37, count 0 2006.257.06:35:36.30#ibcon#flushed, iclass 37, count 0 2006.257.06:35:36.30#ibcon#about to write, iclass 37, count 0 2006.257.06:35:36.30#ibcon#wrote, iclass 37, count 0 2006.257.06:35:36.30#ibcon#about to read 3, iclass 37, count 0 2006.257.06:35:36.34#ibcon#read 3, iclass 37, count 0 2006.257.06:35:36.34#ibcon#about to read 4, iclass 37, count 0 2006.257.06:35:36.34#ibcon#read 4, iclass 37, count 0 2006.257.06:35:36.34#ibcon#about to read 5, iclass 37, count 0 2006.257.06:35:36.34#ibcon#read 5, iclass 37, count 0 2006.257.06:35:36.34#ibcon#about to read 6, iclass 37, count 0 2006.257.06:35:36.34#ibcon#read 6, iclass 37, count 0 2006.257.06:35:36.34#ibcon#end of sib2, iclass 37, count 0 2006.257.06:35:36.34#ibcon#*after write, iclass 37, count 0 2006.257.06:35:36.34#ibcon#*before return 0, iclass 37, count 0 2006.257.06:35:36.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:36.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:36.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:35:36.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:35:36.34$vck44/va=7,4 2006.257.06:35:36.34#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.06:35:36.34#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.06:35:36.34#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:36.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:36.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:36.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:36.40#ibcon#enter wrdev, iclass 39, count 2 2006.257.06:35:36.40#ibcon#first serial, iclass 39, count 2 2006.257.06:35:36.40#ibcon#enter sib2, iclass 39, count 2 2006.257.06:35:36.40#ibcon#flushed, iclass 39, count 2 2006.257.06:35:36.40#ibcon#about to write, iclass 39, count 2 2006.257.06:35:36.40#ibcon#wrote, iclass 39, count 2 2006.257.06:35:36.40#ibcon#about to read 3, iclass 39, count 2 2006.257.06:35:36.42#ibcon#read 3, iclass 39, count 2 2006.257.06:35:36.42#ibcon#about to read 4, iclass 39, count 2 2006.257.06:35:36.42#ibcon#read 4, iclass 39, count 2 2006.257.06:35:36.42#ibcon#about to read 5, iclass 39, count 2 2006.257.06:35:36.42#ibcon#read 5, iclass 39, count 2 2006.257.06:35:36.42#ibcon#about to read 6, iclass 39, count 2 2006.257.06:35:36.42#ibcon#read 6, iclass 39, count 2 2006.257.06:35:36.42#ibcon#end of sib2, iclass 39, count 2 2006.257.06:35:36.42#ibcon#*mode == 0, iclass 39, count 2 2006.257.06:35:36.42#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.06:35:36.42#ibcon#[25=AT07-04\r\n] 2006.257.06:35:36.42#ibcon#*before write, iclass 39, count 2 2006.257.06:35:36.42#ibcon#enter sib2, iclass 39, count 2 2006.257.06:35:36.42#ibcon#flushed, iclass 39, count 2 2006.257.06:35:36.42#ibcon#about to write, iclass 39, count 2 2006.257.06:35:36.42#ibcon#wrote, iclass 39, count 2 2006.257.06:35:36.42#ibcon#about to read 3, iclass 39, count 2 2006.257.06:35:36.45#ibcon#read 3, iclass 39, count 2 2006.257.06:35:36.45#ibcon#about to read 4, iclass 39, count 2 2006.257.06:35:36.45#ibcon#read 4, iclass 39, count 2 2006.257.06:35:36.45#ibcon#about to read 5, iclass 39, count 2 2006.257.06:35:36.45#ibcon#read 5, iclass 39, count 2 2006.257.06:35:36.45#ibcon#about to read 6, iclass 39, count 2 2006.257.06:35:36.45#ibcon#read 6, iclass 39, count 2 2006.257.06:35:36.45#ibcon#end of sib2, iclass 39, count 2 2006.257.06:35:36.45#ibcon#*after write, iclass 39, count 2 2006.257.06:35:36.45#ibcon#*before return 0, iclass 39, count 2 2006.257.06:35:36.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:36.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:36.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.06:35:36.45#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:36.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:36.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:36.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:36.57#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:35:36.57#ibcon#first serial, iclass 39, count 0 2006.257.06:35:36.57#ibcon#enter sib2, iclass 39, count 0 2006.257.06:35:36.57#ibcon#flushed, iclass 39, count 0 2006.257.06:35:36.57#ibcon#about to write, iclass 39, count 0 2006.257.06:35:36.57#ibcon#wrote, iclass 39, count 0 2006.257.06:35:36.57#ibcon#about to read 3, iclass 39, count 0 2006.257.06:35:36.59#ibcon#read 3, iclass 39, count 0 2006.257.06:35:36.59#ibcon#about to read 4, iclass 39, count 0 2006.257.06:35:36.59#ibcon#read 4, iclass 39, count 0 2006.257.06:35:36.59#ibcon#about to read 5, iclass 39, count 0 2006.257.06:35:36.59#ibcon#read 5, iclass 39, count 0 2006.257.06:35:36.59#ibcon#about to read 6, iclass 39, count 0 2006.257.06:35:36.59#ibcon#read 6, iclass 39, count 0 2006.257.06:35:36.59#ibcon#end of sib2, iclass 39, count 0 2006.257.06:35:36.59#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:35:36.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:35:36.59#ibcon#[25=USB\r\n] 2006.257.06:35:36.59#ibcon#*before write, iclass 39, count 0 2006.257.06:35:36.59#ibcon#enter sib2, iclass 39, count 0 2006.257.06:35:36.59#ibcon#flushed, iclass 39, count 0 2006.257.06:35:36.59#ibcon#about to write, iclass 39, count 0 2006.257.06:35:36.59#ibcon#wrote, iclass 39, count 0 2006.257.06:35:36.59#ibcon#about to read 3, iclass 39, count 0 2006.257.06:35:36.62#ibcon#read 3, iclass 39, count 0 2006.257.06:35:36.62#ibcon#about to read 4, iclass 39, count 0 2006.257.06:35:36.62#ibcon#read 4, iclass 39, count 0 2006.257.06:35:36.62#ibcon#about to read 5, iclass 39, count 0 2006.257.06:35:36.62#ibcon#read 5, iclass 39, count 0 2006.257.06:35:36.62#ibcon#about to read 6, iclass 39, count 0 2006.257.06:35:36.62#ibcon#read 6, iclass 39, count 0 2006.257.06:35:36.62#ibcon#end of sib2, iclass 39, count 0 2006.257.06:35:36.62#ibcon#*after write, iclass 39, count 0 2006.257.06:35:36.62#ibcon#*before return 0, iclass 39, count 0 2006.257.06:35:36.62#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:36.62#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:36.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:35:36.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:35:36.62$vck44/valo=8,884.99 2006.257.06:35:36.62#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.06:35:36.62#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.06:35:36.62#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:36.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:36.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:36.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:36.62#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:35:36.62#ibcon#first serial, iclass 3, count 0 2006.257.06:35:36.62#ibcon#enter sib2, iclass 3, count 0 2006.257.06:35:36.62#ibcon#flushed, iclass 3, count 0 2006.257.06:35:36.62#ibcon#about to write, iclass 3, count 0 2006.257.06:35:36.62#ibcon#wrote, iclass 3, count 0 2006.257.06:35:36.62#ibcon#about to read 3, iclass 3, count 0 2006.257.06:35:36.64#ibcon#read 3, iclass 3, count 0 2006.257.06:35:36.64#ibcon#about to read 4, iclass 3, count 0 2006.257.06:35:36.64#ibcon#read 4, iclass 3, count 0 2006.257.06:35:36.64#ibcon#about to read 5, iclass 3, count 0 2006.257.06:35:36.64#ibcon#read 5, iclass 3, count 0 2006.257.06:35:36.64#ibcon#about to read 6, iclass 3, count 0 2006.257.06:35:36.64#ibcon#read 6, iclass 3, count 0 2006.257.06:35:36.64#ibcon#end of sib2, iclass 3, count 0 2006.257.06:35:36.64#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:35:36.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:35:36.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:35:36.64#ibcon#*before write, iclass 3, count 0 2006.257.06:35:36.64#ibcon#enter sib2, iclass 3, count 0 2006.257.06:35:36.64#ibcon#flushed, iclass 3, count 0 2006.257.06:35:36.64#ibcon#about to write, iclass 3, count 0 2006.257.06:35:36.64#ibcon#wrote, iclass 3, count 0 2006.257.06:35:36.64#ibcon#about to read 3, iclass 3, count 0 2006.257.06:35:36.68#ibcon#read 3, iclass 3, count 0 2006.257.06:35:36.68#ibcon#about to read 4, iclass 3, count 0 2006.257.06:35:36.68#ibcon#read 4, iclass 3, count 0 2006.257.06:35:36.68#ibcon#about to read 5, iclass 3, count 0 2006.257.06:35:36.68#ibcon#read 5, iclass 3, count 0 2006.257.06:35:36.68#ibcon#about to read 6, iclass 3, count 0 2006.257.06:35:36.68#ibcon#read 6, iclass 3, count 0 2006.257.06:35:36.68#ibcon#end of sib2, iclass 3, count 0 2006.257.06:35:36.68#ibcon#*after write, iclass 3, count 0 2006.257.06:35:36.68#ibcon#*before return 0, iclass 3, count 0 2006.257.06:35:36.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:36.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:36.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:35:36.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:35:36.68$vck44/va=8,4 2006.257.06:35:36.68#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.06:35:36.68#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.06:35:36.68#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:36.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:36.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:36.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:36.74#ibcon#enter wrdev, iclass 5, count 2 2006.257.06:35:36.74#ibcon#first serial, iclass 5, count 2 2006.257.06:35:36.74#ibcon#enter sib2, iclass 5, count 2 2006.257.06:35:36.74#ibcon#flushed, iclass 5, count 2 2006.257.06:35:36.74#ibcon#about to write, iclass 5, count 2 2006.257.06:35:36.74#ibcon#wrote, iclass 5, count 2 2006.257.06:35:36.74#ibcon#about to read 3, iclass 5, count 2 2006.257.06:35:36.76#ibcon#read 3, iclass 5, count 2 2006.257.06:35:36.76#ibcon#about to read 4, iclass 5, count 2 2006.257.06:35:36.76#ibcon#read 4, iclass 5, count 2 2006.257.06:35:36.76#ibcon#about to read 5, iclass 5, count 2 2006.257.06:35:36.76#ibcon#read 5, iclass 5, count 2 2006.257.06:35:36.76#ibcon#about to read 6, iclass 5, count 2 2006.257.06:35:36.76#ibcon#read 6, iclass 5, count 2 2006.257.06:35:36.76#ibcon#end of sib2, iclass 5, count 2 2006.257.06:35:36.76#ibcon#*mode == 0, iclass 5, count 2 2006.257.06:35:36.76#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.06:35:36.76#ibcon#[25=AT08-04\r\n] 2006.257.06:35:36.76#ibcon#*before write, iclass 5, count 2 2006.257.06:35:36.76#ibcon#enter sib2, iclass 5, count 2 2006.257.06:35:36.76#ibcon#flushed, iclass 5, count 2 2006.257.06:35:36.76#ibcon#about to write, iclass 5, count 2 2006.257.06:35:36.76#ibcon#wrote, iclass 5, count 2 2006.257.06:35:36.76#ibcon#about to read 3, iclass 5, count 2 2006.257.06:35:36.79#ibcon#read 3, iclass 5, count 2 2006.257.06:35:36.79#ibcon#about to read 4, iclass 5, count 2 2006.257.06:35:36.79#ibcon#read 4, iclass 5, count 2 2006.257.06:35:36.79#ibcon#about to read 5, iclass 5, count 2 2006.257.06:35:36.79#ibcon#read 5, iclass 5, count 2 2006.257.06:35:36.79#ibcon#about to read 6, iclass 5, count 2 2006.257.06:35:36.79#ibcon#read 6, iclass 5, count 2 2006.257.06:35:36.79#ibcon#end of sib2, iclass 5, count 2 2006.257.06:35:36.79#ibcon#*after write, iclass 5, count 2 2006.257.06:35:36.79#ibcon#*before return 0, iclass 5, count 2 2006.257.06:35:36.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:36.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:36.79#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.06:35:36.79#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:36.79#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:36.91#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:36.91#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:36.91#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:35:36.91#ibcon#first serial, iclass 5, count 0 2006.257.06:35:36.91#ibcon#enter sib2, iclass 5, count 0 2006.257.06:35:36.91#ibcon#flushed, iclass 5, count 0 2006.257.06:35:36.91#ibcon#about to write, iclass 5, count 0 2006.257.06:35:36.91#ibcon#wrote, iclass 5, count 0 2006.257.06:35:36.91#ibcon#about to read 3, iclass 5, count 0 2006.257.06:35:36.93#ibcon#read 3, iclass 5, count 0 2006.257.06:35:36.93#ibcon#about to read 4, iclass 5, count 0 2006.257.06:35:36.93#ibcon#read 4, iclass 5, count 0 2006.257.06:35:36.93#ibcon#about to read 5, iclass 5, count 0 2006.257.06:35:36.93#ibcon#read 5, iclass 5, count 0 2006.257.06:35:36.93#ibcon#about to read 6, iclass 5, count 0 2006.257.06:35:36.93#ibcon#read 6, iclass 5, count 0 2006.257.06:35:36.93#ibcon#end of sib2, iclass 5, count 0 2006.257.06:35:36.93#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:35:36.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:35:36.93#ibcon#[25=USB\r\n] 2006.257.06:35:36.93#ibcon#*before write, iclass 5, count 0 2006.257.06:35:36.93#ibcon#enter sib2, iclass 5, count 0 2006.257.06:35:36.93#ibcon#flushed, iclass 5, count 0 2006.257.06:35:36.93#ibcon#about to write, iclass 5, count 0 2006.257.06:35:36.93#ibcon#wrote, iclass 5, count 0 2006.257.06:35:36.93#ibcon#about to read 3, iclass 5, count 0 2006.257.06:35:36.96#ibcon#read 3, iclass 5, count 0 2006.257.06:35:36.96#ibcon#about to read 4, iclass 5, count 0 2006.257.06:35:36.96#ibcon#read 4, iclass 5, count 0 2006.257.06:35:36.96#ibcon#about to read 5, iclass 5, count 0 2006.257.06:35:36.96#ibcon#read 5, iclass 5, count 0 2006.257.06:35:36.96#ibcon#about to read 6, iclass 5, count 0 2006.257.06:35:36.96#ibcon#read 6, iclass 5, count 0 2006.257.06:35:36.96#ibcon#end of sib2, iclass 5, count 0 2006.257.06:35:36.96#ibcon#*after write, iclass 5, count 0 2006.257.06:35:36.96#ibcon#*before return 0, iclass 5, count 0 2006.257.06:35:36.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:36.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:36.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:35:36.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:35:36.96$vck44/vblo=1,629.99 2006.257.06:35:36.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.06:35:36.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.06:35:36.96#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:36.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:36.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:36.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:36.96#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:35:36.96#ibcon#first serial, iclass 7, count 0 2006.257.06:35:36.96#ibcon#enter sib2, iclass 7, count 0 2006.257.06:35:36.96#ibcon#flushed, iclass 7, count 0 2006.257.06:35:36.96#ibcon#about to write, iclass 7, count 0 2006.257.06:35:36.96#ibcon#wrote, iclass 7, count 0 2006.257.06:35:36.96#ibcon#about to read 3, iclass 7, count 0 2006.257.06:35:36.98#ibcon#read 3, iclass 7, count 0 2006.257.06:35:36.98#ibcon#about to read 4, iclass 7, count 0 2006.257.06:35:36.98#ibcon#read 4, iclass 7, count 0 2006.257.06:35:36.98#ibcon#about to read 5, iclass 7, count 0 2006.257.06:35:36.98#ibcon#read 5, iclass 7, count 0 2006.257.06:35:36.98#ibcon#about to read 6, iclass 7, count 0 2006.257.06:35:36.98#ibcon#read 6, iclass 7, count 0 2006.257.06:35:36.98#ibcon#end of sib2, iclass 7, count 0 2006.257.06:35:36.98#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:35:36.98#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:35:36.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:35:36.98#ibcon#*before write, iclass 7, count 0 2006.257.06:35:36.98#ibcon#enter sib2, iclass 7, count 0 2006.257.06:35:36.98#ibcon#flushed, iclass 7, count 0 2006.257.06:35:36.98#ibcon#about to write, iclass 7, count 0 2006.257.06:35:36.98#ibcon#wrote, iclass 7, count 0 2006.257.06:35:36.98#ibcon#about to read 3, iclass 7, count 0 2006.257.06:35:37.02#ibcon#read 3, iclass 7, count 0 2006.257.06:35:37.02#ibcon#about to read 4, iclass 7, count 0 2006.257.06:35:37.02#ibcon#read 4, iclass 7, count 0 2006.257.06:35:37.02#ibcon#about to read 5, iclass 7, count 0 2006.257.06:35:37.02#ibcon#read 5, iclass 7, count 0 2006.257.06:35:37.02#ibcon#about to read 6, iclass 7, count 0 2006.257.06:35:37.02#ibcon#read 6, iclass 7, count 0 2006.257.06:35:37.02#ibcon#end of sib2, iclass 7, count 0 2006.257.06:35:37.02#ibcon#*after write, iclass 7, count 0 2006.257.06:35:37.02#ibcon#*before return 0, iclass 7, count 0 2006.257.06:35:37.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:37.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:37.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:35:37.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:35:37.02$vck44/vb=1,4 2006.257.06:35:37.02#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.06:35:37.02#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.06:35:37.02#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:37.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:35:37.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:35:37.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:35:37.02#ibcon#enter wrdev, iclass 11, count 2 2006.257.06:35:37.02#ibcon#first serial, iclass 11, count 2 2006.257.06:35:37.02#ibcon#enter sib2, iclass 11, count 2 2006.257.06:35:37.02#ibcon#flushed, iclass 11, count 2 2006.257.06:35:37.02#ibcon#about to write, iclass 11, count 2 2006.257.06:35:37.02#ibcon#wrote, iclass 11, count 2 2006.257.06:35:37.02#ibcon#about to read 3, iclass 11, count 2 2006.257.06:35:37.04#ibcon#read 3, iclass 11, count 2 2006.257.06:35:37.04#ibcon#about to read 4, iclass 11, count 2 2006.257.06:35:37.04#ibcon#read 4, iclass 11, count 2 2006.257.06:35:37.04#ibcon#about to read 5, iclass 11, count 2 2006.257.06:35:37.04#ibcon#read 5, iclass 11, count 2 2006.257.06:35:37.04#ibcon#about to read 6, iclass 11, count 2 2006.257.06:35:37.04#ibcon#read 6, iclass 11, count 2 2006.257.06:35:37.04#ibcon#end of sib2, iclass 11, count 2 2006.257.06:35:37.04#ibcon#*mode == 0, iclass 11, count 2 2006.257.06:35:37.04#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.06:35:37.04#ibcon#[27=AT01-04\r\n] 2006.257.06:35:37.04#ibcon#*before write, iclass 11, count 2 2006.257.06:35:37.04#ibcon#enter sib2, iclass 11, count 2 2006.257.06:35:37.04#ibcon#flushed, iclass 11, count 2 2006.257.06:35:37.04#ibcon#about to write, iclass 11, count 2 2006.257.06:35:37.04#ibcon#wrote, iclass 11, count 2 2006.257.06:35:37.04#ibcon#about to read 3, iclass 11, count 2 2006.257.06:35:37.07#ibcon#read 3, iclass 11, count 2 2006.257.06:35:37.07#ibcon#about to read 4, iclass 11, count 2 2006.257.06:35:37.07#ibcon#read 4, iclass 11, count 2 2006.257.06:35:37.07#ibcon#about to read 5, iclass 11, count 2 2006.257.06:35:37.07#ibcon#read 5, iclass 11, count 2 2006.257.06:35:37.07#ibcon#about to read 6, iclass 11, count 2 2006.257.06:35:37.07#ibcon#read 6, iclass 11, count 2 2006.257.06:35:37.07#ibcon#end of sib2, iclass 11, count 2 2006.257.06:35:37.07#ibcon#*after write, iclass 11, count 2 2006.257.06:35:37.07#ibcon#*before return 0, iclass 11, count 2 2006.257.06:35:37.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:35:37.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:35:37.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.06:35:37.07#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:37.07#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:35:37.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:35:37.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:35:37.19#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:35:37.19#ibcon#first serial, iclass 11, count 0 2006.257.06:35:37.19#ibcon#enter sib2, iclass 11, count 0 2006.257.06:35:37.19#ibcon#flushed, iclass 11, count 0 2006.257.06:35:37.19#ibcon#about to write, iclass 11, count 0 2006.257.06:35:37.19#ibcon#wrote, iclass 11, count 0 2006.257.06:35:37.19#ibcon#about to read 3, iclass 11, count 0 2006.257.06:35:37.21#ibcon#read 3, iclass 11, count 0 2006.257.06:35:37.21#ibcon#about to read 4, iclass 11, count 0 2006.257.06:35:37.21#ibcon#read 4, iclass 11, count 0 2006.257.06:35:37.21#ibcon#about to read 5, iclass 11, count 0 2006.257.06:35:37.21#ibcon#read 5, iclass 11, count 0 2006.257.06:35:37.21#ibcon#about to read 6, iclass 11, count 0 2006.257.06:35:37.21#ibcon#read 6, iclass 11, count 0 2006.257.06:35:37.21#ibcon#end of sib2, iclass 11, count 0 2006.257.06:35:37.21#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:35:37.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:35:37.21#ibcon#[27=USB\r\n] 2006.257.06:35:37.21#ibcon#*before write, iclass 11, count 0 2006.257.06:35:37.21#ibcon#enter sib2, iclass 11, count 0 2006.257.06:35:37.21#ibcon#flushed, iclass 11, count 0 2006.257.06:35:37.21#ibcon#about to write, iclass 11, count 0 2006.257.06:35:37.21#ibcon#wrote, iclass 11, count 0 2006.257.06:35:37.21#ibcon#about to read 3, iclass 11, count 0 2006.257.06:35:37.24#ibcon#read 3, iclass 11, count 0 2006.257.06:35:37.24#ibcon#about to read 4, iclass 11, count 0 2006.257.06:35:37.24#ibcon#read 4, iclass 11, count 0 2006.257.06:35:37.24#ibcon#about to read 5, iclass 11, count 0 2006.257.06:35:37.24#ibcon#read 5, iclass 11, count 0 2006.257.06:35:37.24#ibcon#about to read 6, iclass 11, count 0 2006.257.06:35:37.24#ibcon#read 6, iclass 11, count 0 2006.257.06:35:37.24#ibcon#end of sib2, iclass 11, count 0 2006.257.06:35:37.24#ibcon#*after write, iclass 11, count 0 2006.257.06:35:37.24#ibcon#*before return 0, iclass 11, count 0 2006.257.06:35:37.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:35:37.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:35:37.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:35:37.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:35:37.24$vck44/vblo=2,634.99 2006.257.06:35:37.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.06:35:37.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.06:35:37.24#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:37.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:37.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:37.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:37.24#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:35:37.24#ibcon#first serial, iclass 13, count 0 2006.257.06:35:37.24#ibcon#enter sib2, iclass 13, count 0 2006.257.06:35:37.24#ibcon#flushed, iclass 13, count 0 2006.257.06:35:37.24#ibcon#about to write, iclass 13, count 0 2006.257.06:35:37.24#ibcon#wrote, iclass 13, count 0 2006.257.06:35:37.24#ibcon#about to read 3, iclass 13, count 0 2006.257.06:35:37.26#ibcon#read 3, iclass 13, count 0 2006.257.06:35:37.26#ibcon#about to read 4, iclass 13, count 0 2006.257.06:35:37.26#ibcon#read 4, iclass 13, count 0 2006.257.06:35:37.26#ibcon#about to read 5, iclass 13, count 0 2006.257.06:35:37.26#ibcon#read 5, iclass 13, count 0 2006.257.06:35:37.26#ibcon#about to read 6, iclass 13, count 0 2006.257.06:35:37.26#ibcon#read 6, iclass 13, count 0 2006.257.06:35:37.26#ibcon#end of sib2, iclass 13, count 0 2006.257.06:35:37.26#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:35:37.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:35:37.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:35:37.26#ibcon#*before write, iclass 13, count 0 2006.257.06:35:37.26#ibcon#enter sib2, iclass 13, count 0 2006.257.06:35:37.26#ibcon#flushed, iclass 13, count 0 2006.257.06:35:37.26#ibcon#about to write, iclass 13, count 0 2006.257.06:35:37.26#ibcon#wrote, iclass 13, count 0 2006.257.06:35:37.26#ibcon#about to read 3, iclass 13, count 0 2006.257.06:35:37.30#ibcon#read 3, iclass 13, count 0 2006.257.06:35:37.30#ibcon#about to read 4, iclass 13, count 0 2006.257.06:35:37.30#ibcon#read 4, iclass 13, count 0 2006.257.06:35:37.30#ibcon#about to read 5, iclass 13, count 0 2006.257.06:35:37.30#ibcon#read 5, iclass 13, count 0 2006.257.06:35:37.30#ibcon#about to read 6, iclass 13, count 0 2006.257.06:35:37.30#ibcon#read 6, iclass 13, count 0 2006.257.06:35:37.30#ibcon#end of sib2, iclass 13, count 0 2006.257.06:35:37.30#ibcon#*after write, iclass 13, count 0 2006.257.06:35:37.30#ibcon#*before return 0, iclass 13, count 0 2006.257.06:35:37.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:37.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:35:37.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:35:37.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:35:37.30$vck44/vb=2,5 2006.257.06:35:37.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.06:35:37.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.06:35:37.30#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:37.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:37.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:37.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:37.36#ibcon#enter wrdev, iclass 15, count 2 2006.257.06:35:37.36#ibcon#first serial, iclass 15, count 2 2006.257.06:35:37.36#ibcon#enter sib2, iclass 15, count 2 2006.257.06:35:37.36#ibcon#flushed, iclass 15, count 2 2006.257.06:35:37.36#ibcon#about to write, iclass 15, count 2 2006.257.06:35:37.36#ibcon#wrote, iclass 15, count 2 2006.257.06:35:37.36#ibcon#about to read 3, iclass 15, count 2 2006.257.06:35:37.38#ibcon#read 3, iclass 15, count 2 2006.257.06:35:37.38#ibcon#about to read 4, iclass 15, count 2 2006.257.06:35:37.38#ibcon#read 4, iclass 15, count 2 2006.257.06:35:37.38#ibcon#about to read 5, iclass 15, count 2 2006.257.06:35:37.38#ibcon#read 5, iclass 15, count 2 2006.257.06:35:37.38#ibcon#about to read 6, iclass 15, count 2 2006.257.06:35:37.38#ibcon#read 6, iclass 15, count 2 2006.257.06:35:37.38#ibcon#end of sib2, iclass 15, count 2 2006.257.06:35:37.38#ibcon#*mode == 0, iclass 15, count 2 2006.257.06:35:37.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.06:35:37.38#ibcon#[27=AT02-05\r\n] 2006.257.06:35:37.38#ibcon#*before write, iclass 15, count 2 2006.257.06:35:37.38#ibcon#enter sib2, iclass 15, count 2 2006.257.06:35:37.38#ibcon#flushed, iclass 15, count 2 2006.257.06:35:37.38#ibcon#about to write, iclass 15, count 2 2006.257.06:35:37.38#ibcon#wrote, iclass 15, count 2 2006.257.06:35:37.38#ibcon#about to read 3, iclass 15, count 2 2006.257.06:35:37.41#ibcon#read 3, iclass 15, count 2 2006.257.06:35:37.41#ibcon#about to read 4, iclass 15, count 2 2006.257.06:35:37.41#ibcon#read 4, iclass 15, count 2 2006.257.06:35:37.41#ibcon#about to read 5, iclass 15, count 2 2006.257.06:35:37.41#ibcon#read 5, iclass 15, count 2 2006.257.06:35:37.41#ibcon#about to read 6, iclass 15, count 2 2006.257.06:35:37.41#ibcon#read 6, iclass 15, count 2 2006.257.06:35:37.41#ibcon#end of sib2, iclass 15, count 2 2006.257.06:35:37.41#ibcon#*after write, iclass 15, count 2 2006.257.06:35:37.41#ibcon#*before return 0, iclass 15, count 2 2006.257.06:35:37.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:37.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:35:37.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.06:35:37.41#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:37.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:37.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:37.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:37.53#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:35:37.53#ibcon#first serial, iclass 15, count 0 2006.257.06:35:37.53#ibcon#enter sib2, iclass 15, count 0 2006.257.06:35:37.53#ibcon#flushed, iclass 15, count 0 2006.257.06:35:37.53#ibcon#about to write, iclass 15, count 0 2006.257.06:35:37.53#ibcon#wrote, iclass 15, count 0 2006.257.06:35:37.53#ibcon#about to read 3, iclass 15, count 0 2006.257.06:35:37.55#ibcon#read 3, iclass 15, count 0 2006.257.06:35:37.55#ibcon#about to read 4, iclass 15, count 0 2006.257.06:35:37.55#ibcon#read 4, iclass 15, count 0 2006.257.06:35:37.55#ibcon#about to read 5, iclass 15, count 0 2006.257.06:35:37.55#ibcon#read 5, iclass 15, count 0 2006.257.06:35:37.55#ibcon#about to read 6, iclass 15, count 0 2006.257.06:35:37.55#ibcon#read 6, iclass 15, count 0 2006.257.06:35:37.55#ibcon#end of sib2, iclass 15, count 0 2006.257.06:35:37.55#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:35:37.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:35:37.55#ibcon#[27=USB\r\n] 2006.257.06:35:37.55#ibcon#*before write, iclass 15, count 0 2006.257.06:35:37.55#ibcon#enter sib2, iclass 15, count 0 2006.257.06:35:37.55#ibcon#flushed, iclass 15, count 0 2006.257.06:35:37.55#ibcon#about to write, iclass 15, count 0 2006.257.06:35:37.55#ibcon#wrote, iclass 15, count 0 2006.257.06:35:37.55#ibcon#about to read 3, iclass 15, count 0 2006.257.06:35:37.58#ibcon#read 3, iclass 15, count 0 2006.257.06:35:37.58#ibcon#about to read 4, iclass 15, count 0 2006.257.06:35:37.58#ibcon#read 4, iclass 15, count 0 2006.257.06:35:37.58#ibcon#about to read 5, iclass 15, count 0 2006.257.06:35:37.58#ibcon#read 5, iclass 15, count 0 2006.257.06:35:37.58#ibcon#about to read 6, iclass 15, count 0 2006.257.06:35:37.58#ibcon#read 6, iclass 15, count 0 2006.257.06:35:37.58#ibcon#end of sib2, iclass 15, count 0 2006.257.06:35:37.58#ibcon#*after write, iclass 15, count 0 2006.257.06:35:37.58#ibcon#*before return 0, iclass 15, count 0 2006.257.06:35:37.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:37.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:35:37.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:35:37.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:35:37.58$vck44/vblo=3,649.99 2006.257.06:35:37.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.06:35:37.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.06:35:37.58#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:37.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:37.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:37.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:37.58#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:35:37.58#ibcon#first serial, iclass 17, count 0 2006.257.06:35:37.58#ibcon#enter sib2, iclass 17, count 0 2006.257.06:35:37.58#ibcon#flushed, iclass 17, count 0 2006.257.06:35:37.58#ibcon#about to write, iclass 17, count 0 2006.257.06:35:37.58#ibcon#wrote, iclass 17, count 0 2006.257.06:35:37.58#ibcon#about to read 3, iclass 17, count 0 2006.257.06:35:37.60#ibcon#read 3, iclass 17, count 0 2006.257.06:35:37.60#ibcon#about to read 4, iclass 17, count 0 2006.257.06:35:37.60#ibcon#read 4, iclass 17, count 0 2006.257.06:35:37.60#ibcon#about to read 5, iclass 17, count 0 2006.257.06:35:37.60#ibcon#read 5, iclass 17, count 0 2006.257.06:35:37.60#ibcon#about to read 6, iclass 17, count 0 2006.257.06:35:37.60#ibcon#read 6, iclass 17, count 0 2006.257.06:35:37.60#ibcon#end of sib2, iclass 17, count 0 2006.257.06:35:37.60#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:35:37.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:35:37.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:35:37.60#ibcon#*before write, iclass 17, count 0 2006.257.06:35:37.60#ibcon#enter sib2, iclass 17, count 0 2006.257.06:35:37.60#ibcon#flushed, iclass 17, count 0 2006.257.06:35:37.60#ibcon#about to write, iclass 17, count 0 2006.257.06:35:37.60#ibcon#wrote, iclass 17, count 0 2006.257.06:35:37.60#ibcon#about to read 3, iclass 17, count 0 2006.257.06:35:37.64#ibcon#read 3, iclass 17, count 0 2006.257.06:35:37.64#ibcon#about to read 4, iclass 17, count 0 2006.257.06:35:37.64#ibcon#read 4, iclass 17, count 0 2006.257.06:35:37.64#ibcon#about to read 5, iclass 17, count 0 2006.257.06:35:37.64#ibcon#read 5, iclass 17, count 0 2006.257.06:35:37.64#ibcon#about to read 6, iclass 17, count 0 2006.257.06:35:37.64#ibcon#read 6, iclass 17, count 0 2006.257.06:35:37.64#ibcon#end of sib2, iclass 17, count 0 2006.257.06:35:37.64#ibcon#*after write, iclass 17, count 0 2006.257.06:35:37.64#ibcon#*before return 0, iclass 17, count 0 2006.257.06:35:37.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:37.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:35:37.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:35:37.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:35:37.64$vck44/vb=3,4 2006.257.06:35:37.64#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.06:35:37.64#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.06:35:37.64#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:37.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:37.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:37.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:37.70#ibcon#enter wrdev, iclass 19, count 2 2006.257.06:35:37.70#ibcon#first serial, iclass 19, count 2 2006.257.06:35:37.70#ibcon#enter sib2, iclass 19, count 2 2006.257.06:35:37.70#ibcon#flushed, iclass 19, count 2 2006.257.06:35:37.70#ibcon#about to write, iclass 19, count 2 2006.257.06:35:37.70#ibcon#wrote, iclass 19, count 2 2006.257.06:35:37.70#ibcon#about to read 3, iclass 19, count 2 2006.257.06:35:37.72#ibcon#read 3, iclass 19, count 2 2006.257.06:35:37.72#ibcon#about to read 4, iclass 19, count 2 2006.257.06:35:37.72#ibcon#read 4, iclass 19, count 2 2006.257.06:35:37.72#ibcon#about to read 5, iclass 19, count 2 2006.257.06:35:37.72#ibcon#read 5, iclass 19, count 2 2006.257.06:35:37.72#ibcon#about to read 6, iclass 19, count 2 2006.257.06:35:37.72#ibcon#read 6, iclass 19, count 2 2006.257.06:35:37.72#ibcon#end of sib2, iclass 19, count 2 2006.257.06:35:37.72#ibcon#*mode == 0, iclass 19, count 2 2006.257.06:35:37.72#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.06:35:37.72#ibcon#[27=AT03-04\r\n] 2006.257.06:35:37.72#ibcon#*before write, iclass 19, count 2 2006.257.06:35:37.72#ibcon#enter sib2, iclass 19, count 2 2006.257.06:35:37.72#ibcon#flushed, iclass 19, count 2 2006.257.06:35:37.72#ibcon#about to write, iclass 19, count 2 2006.257.06:35:37.72#ibcon#wrote, iclass 19, count 2 2006.257.06:35:37.72#ibcon#about to read 3, iclass 19, count 2 2006.257.06:35:37.75#ibcon#read 3, iclass 19, count 2 2006.257.06:35:37.75#ibcon#about to read 4, iclass 19, count 2 2006.257.06:35:37.75#ibcon#read 4, iclass 19, count 2 2006.257.06:35:37.75#ibcon#about to read 5, iclass 19, count 2 2006.257.06:35:37.75#ibcon#read 5, iclass 19, count 2 2006.257.06:35:37.75#ibcon#about to read 6, iclass 19, count 2 2006.257.06:35:37.75#ibcon#read 6, iclass 19, count 2 2006.257.06:35:37.75#ibcon#end of sib2, iclass 19, count 2 2006.257.06:35:37.75#ibcon#*after write, iclass 19, count 2 2006.257.06:35:37.75#ibcon#*before return 0, iclass 19, count 2 2006.257.06:35:37.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:37.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:35:37.75#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.06:35:37.75#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:37.75#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:37.87#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:37.87#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:37.87#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:35:37.87#ibcon#first serial, iclass 19, count 0 2006.257.06:35:37.87#ibcon#enter sib2, iclass 19, count 0 2006.257.06:35:37.87#ibcon#flushed, iclass 19, count 0 2006.257.06:35:37.87#ibcon#about to write, iclass 19, count 0 2006.257.06:35:37.87#ibcon#wrote, iclass 19, count 0 2006.257.06:35:37.87#ibcon#about to read 3, iclass 19, count 0 2006.257.06:35:37.89#ibcon#read 3, iclass 19, count 0 2006.257.06:35:37.89#ibcon#about to read 4, iclass 19, count 0 2006.257.06:35:37.89#ibcon#read 4, iclass 19, count 0 2006.257.06:35:37.89#ibcon#about to read 5, iclass 19, count 0 2006.257.06:35:37.89#ibcon#read 5, iclass 19, count 0 2006.257.06:35:37.89#ibcon#about to read 6, iclass 19, count 0 2006.257.06:35:37.89#ibcon#read 6, iclass 19, count 0 2006.257.06:35:37.89#ibcon#end of sib2, iclass 19, count 0 2006.257.06:35:37.89#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:35:37.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:35:37.89#ibcon#[27=USB\r\n] 2006.257.06:35:37.89#ibcon#*before write, iclass 19, count 0 2006.257.06:35:37.89#ibcon#enter sib2, iclass 19, count 0 2006.257.06:35:37.89#ibcon#flushed, iclass 19, count 0 2006.257.06:35:37.89#ibcon#about to write, iclass 19, count 0 2006.257.06:35:37.89#ibcon#wrote, iclass 19, count 0 2006.257.06:35:37.89#ibcon#about to read 3, iclass 19, count 0 2006.257.06:35:37.92#ibcon#read 3, iclass 19, count 0 2006.257.06:35:37.92#ibcon#about to read 4, iclass 19, count 0 2006.257.06:35:37.92#ibcon#read 4, iclass 19, count 0 2006.257.06:35:37.92#ibcon#about to read 5, iclass 19, count 0 2006.257.06:35:37.92#ibcon#read 5, iclass 19, count 0 2006.257.06:35:37.92#ibcon#about to read 6, iclass 19, count 0 2006.257.06:35:37.92#ibcon#read 6, iclass 19, count 0 2006.257.06:35:37.92#ibcon#end of sib2, iclass 19, count 0 2006.257.06:35:37.92#ibcon#*after write, iclass 19, count 0 2006.257.06:35:37.92#ibcon#*before return 0, iclass 19, count 0 2006.257.06:35:37.92#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:37.92#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:35:37.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:35:37.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:35:37.92$vck44/vblo=4,679.99 2006.257.06:35:37.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.06:35:37.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.06:35:37.92#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:37.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:37.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:37.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:37.92#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:35:37.92#ibcon#first serial, iclass 21, count 0 2006.257.06:35:37.92#ibcon#enter sib2, iclass 21, count 0 2006.257.06:35:37.92#ibcon#flushed, iclass 21, count 0 2006.257.06:35:37.92#ibcon#about to write, iclass 21, count 0 2006.257.06:35:37.92#ibcon#wrote, iclass 21, count 0 2006.257.06:35:37.92#ibcon#about to read 3, iclass 21, count 0 2006.257.06:35:37.94#ibcon#read 3, iclass 21, count 0 2006.257.06:35:37.94#ibcon#about to read 4, iclass 21, count 0 2006.257.06:35:37.94#ibcon#read 4, iclass 21, count 0 2006.257.06:35:37.94#ibcon#about to read 5, iclass 21, count 0 2006.257.06:35:37.94#ibcon#read 5, iclass 21, count 0 2006.257.06:35:37.94#ibcon#about to read 6, iclass 21, count 0 2006.257.06:35:37.94#ibcon#read 6, iclass 21, count 0 2006.257.06:35:37.94#ibcon#end of sib2, iclass 21, count 0 2006.257.06:35:37.94#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:35:37.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:35:37.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:35:37.94#ibcon#*before write, iclass 21, count 0 2006.257.06:35:37.94#ibcon#enter sib2, iclass 21, count 0 2006.257.06:35:37.94#ibcon#flushed, iclass 21, count 0 2006.257.06:35:37.94#ibcon#about to write, iclass 21, count 0 2006.257.06:35:37.94#ibcon#wrote, iclass 21, count 0 2006.257.06:35:37.94#ibcon#about to read 3, iclass 21, count 0 2006.257.06:35:37.98#ibcon#read 3, iclass 21, count 0 2006.257.06:35:37.98#ibcon#about to read 4, iclass 21, count 0 2006.257.06:35:37.98#ibcon#read 4, iclass 21, count 0 2006.257.06:35:37.98#ibcon#about to read 5, iclass 21, count 0 2006.257.06:35:37.98#ibcon#read 5, iclass 21, count 0 2006.257.06:35:37.98#ibcon#about to read 6, iclass 21, count 0 2006.257.06:35:37.98#ibcon#read 6, iclass 21, count 0 2006.257.06:35:37.98#ibcon#end of sib2, iclass 21, count 0 2006.257.06:35:37.98#ibcon#*after write, iclass 21, count 0 2006.257.06:35:37.98#ibcon#*before return 0, iclass 21, count 0 2006.257.06:35:37.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:37.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:35:37.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:35:37.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:35:37.98$vck44/vb=4,5 2006.257.06:35:37.98#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.06:35:37.98#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.06:35:37.98#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:37.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:38.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:38.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:38.04#ibcon#enter wrdev, iclass 23, count 2 2006.257.06:35:38.04#ibcon#first serial, iclass 23, count 2 2006.257.06:35:38.04#ibcon#enter sib2, iclass 23, count 2 2006.257.06:35:38.04#ibcon#flushed, iclass 23, count 2 2006.257.06:35:38.04#ibcon#about to write, iclass 23, count 2 2006.257.06:35:38.04#ibcon#wrote, iclass 23, count 2 2006.257.06:35:38.04#ibcon#about to read 3, iclass 23, count 2 2006.257.06:35:38.06#ibcon#read 3, iclass 23, count 2 2006.257.06:35:38.06#ibcon#about to read 4, iclass 23, count 2 2006.257.06:35:38.06#ibcon#read 4, iclass 23, count 2 2006.257.06:35:38.06#ibcon#about to read 5, iclass 23, count 2 2006.257.06:35:38.06#ibcon#read 5, iclass 23, count 2 2006.257.06:35:38.06#ibcon#about to read 6, iclass 23, count 2 2006.257.06:35:38.06#ibcon#read 6, iclass 23, count 2 2006.257.06:35:38.06#ibcon#end of sib2, iclass 23, count 2 2006.257.06:35:38.06#ibcon#*mode == 0, iclass 23, count 2 2006.257.06:35:38.06#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.06:35:38.06#ibcon#[27=AT04-05\r\n] 2006.257.06:35:38.06#ibcon#*before write, iclass 23, count 2 2006.257.06:35:38.06#ibcon#enter sib2, iclass 23, count 2 2006.257.06:35:38.06#ibcon#flushed, iclass 23, count 2 2006.257.06:35:38.06#ibcon#about to write, iclass 23, count 2 2006.257.06:35:38.06#ibcon#wrote, iclass 23, count 2 2006.257.06:35:38.06#ibcon#about to read 3, iclass 23, count 2 2006.257.06:35:38.08#abcon#<5=/15 0.6 2.3 20.60 891012.3\r\n> 2006.257.06:35:38.09#ibcon#read 3, iclass 23, count 2 2006.257.06:35:38.09#ibcon#about to read 4, iclass 23, count 2 2006.257.06:35:38.09#ibcon#read 4, iclass 23, count 2 2006.257.06:35:38.09#ibcon#about to read 5, iclass 23, count 2 2006.257.06:35:38.09#ibcon#read 5, iclass 23, count 2 2006.257.06:35:38.09#ibcon#about to read 6, iclass 23, count 2 2006.257.06:35:38.09#ibcon#read 6, iclass 23, count 2 2006.257.06:35:38.09#ibcon#end of sib2, iclass 23, count 2 2006.257.06:35:38.09#ibcon#*after write, iclass 23, count 2 2006.257.06:35:38.09#ibcon#*before return 0, iclass 23, count 2 2006.257.06:35:38.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:38.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:35:38.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.06:35:38.09#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:38.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:38.10#abcon#{5=INTERFACE CLEAR} 2006.257.06:35:38.16#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:35:38.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:38.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:38.21#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:35:38.21#ibcon#first serial, iclass 23, count 0 2006.257.06:35:38.21#ibcon#enter sib2, iclass 23, count 0 2006.257.06:35:38.21#ibcon#flushed, iclass 23, count 0 2006.257.06:35:38.21#ibcon#about to write, iclass 23, count 0 2006.257.06:35:38.21#ibcon#wrote, iclass 23, count 0 2006.257.06:35:38.21#ibcon#about to read 3, iclass 23, count 0 2006.257.06:35:38.23#ibcon#read 3, iclass 23, count 0 2006.257.06:35:38.23#ibcon#about to read 4, iclass 23, count 0 2006.257.06:35:38.23#ibcon#read 4, iclass 23, count 0 2006.257.06:35:38.23#ibcon#about to read 5, iclass 23, count 0 2006.257.06:35:38.23#ibcon#read 5, iclass 23, count 0 2006.257.06:35:38.23#ibcon#about to read 6, iclass 23, count 0 2006.257.06:35:38.23#ibcon#read 6, iclass 23, count 0 2006.257.06:35:38.23#ibcon#end of sib2, iclass 23, count 0 2006.257.06:35:38.23#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:35:38.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:35:38.23#ibcon#[27=USB\r\n] 2006.257.06:35:38.23#ibcon#*before write, iclass 23, count 0 2006.257.06:35:38.23#ibcon#enter sib2, iclass 23, count 0 2006.257.06:35:38.23#ibcon#flushed, iclass 23, count 0 2006.257.06:35:38.23#ibcon#about to write, iclass 23, count 0 2006.257.06:35:38.23#ibcon#wrote, iclass 23, count 0 2006.257.06:35:38.23#ibcon#about to read 3, iclass 23, count 0 2006.257.06:35:38.26#ibcon#read 3, iclass 23, count 0 2006.257.06:35:38.26#ibcon#about to read 4, iclass 23, count 0 2006.257.06:35:38.26#ibcon#read 4, iclass 23, count 0 2006.257.06:35:38.26#ibcon#about to read 5, iclass 23, count 0 2006.257.06:35:38.26#ibcon#read 5, iclass 23, count 0 2006.257.06:35:38.26#ibcon#about to read 6, iclass 23, count 0 2006.257.06:35:38.26#ibcon#read 6, iclass 23, count 0 2006.257.06:35:38.26#ibcon#end of sib2, iclass 23, count 0 2006.257.06:35:38.26#ibcon#*after write, iclass 23, count 0 2006.257.06:35:38.26#ibcon#*before return 0, iclass 23, count 0 2006.257.06:35:38.26#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:38.26#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:35:38.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:35:38.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:35:38.26$vck44/vblo=5,709.99 2006.257.06:35:38.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.06:35:38.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.06:35:38.26#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:38.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:38.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:38.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:38.26#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:35:38.26#ibcon#first serial, iclass 29, count 0 2006.257.06:35:38.26#ibcon#enter sib2, iclass 29, count 0 2006.257.06:35:38.26#ibcon#flushed, iclass 29, count 0 2006.257.06:35:38.26#ibcon#about to write, iclass 29, count 0 2006.257.06:35:38.26#ibcon#wrote, iclass 29, count 0 2006.257.06:35:38.26#ibcon#about to read 3, iclass 29, count 0 2006.257.06:35:38.28#ibcon#read 3, iclass 29, count 0 2006.257.06:35:38.28#ibcon#about to read 4, iclass 29, count 0 2006.257.06:35:38.28#ibcon#read 4, iclass 29, count 0 2006.257.06:35:38.28#ibcon#about to read 5, iclass 29, count 0 2006.257.06:35:38.28#ibcon#read 5, iclass 29, count 0 2006.257.06:35:38.28#ibcon#about to read 6, iclass 29, count 0 2006.257.06:35:38.28#ibcon#read 6, iclass 29, count 0 2006.257.06:35:38.28#ibcon#end of sib2, iclass 29, count 0 2006.257.06:35:38.28#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:35:38.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:35:38.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:35:38.28#ibcon#*before write, iclass 29, count 0 2006.257.06:35:38.28#ibcon#enter sib2, iclass 29, count 0 2006.257.06:35:38.28#ibcon#flushed, iclass 29, count 0 2006.257.06:35:38.28#ibcon#about to write, iclass 29, count 0 2006.257.06:35:38.28#ibcon#wrote, iclass 29, count 0 2006.257.06:35:38.28#ibcon#about to read 3, iclass 29, count 0 2006.257.06:35:38.32#ibcon#read 3, iclass 29, count 0 2006.257.06:35:38.32#ibcon#about to read 4, iclass 29, count 0 2006.257.06:35:38.32#ibcon#read 4, iclass 29, count 0 2006.257.06:35:38.32#ibcon#about to read 5, iclass 29, count 0 2006.257.06:35:38.32#ibcon#read 5, iclass 29, count 0 2006.257.06:35:38.32#ibcon#about to read 6, iclass 29, count 0 2006.257.06:35:38.32#ibcon#read 6, iclass 29, count 0 2006.257.06:35:38.32#ibcon#end of sib2, iclass 29, count 0 2006.257.06:35:38.32#ibcon#*after write, iclass 29, count 0 2006.257.06:35:38.32#ibcon#*before return 0, iclass 29, count 0 2006.257.06:35:38.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:38.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:35:38.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:35:38.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:35:38.32$vck44/vb=5,4 2006.257.06:35:38.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.06:35:38.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.06:35:38.32#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:38.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:38.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:38.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:38.38#ibcon#enter wrdev, iclass 31, count 2 2006.257.06:35:38.38#ibcon#first serial, iclass 31, count 2 2006.257.06:35:38.38#ibcon#enter sib2, iclass 31, count 2 2006.257.06:35:38.38#ibcon#flushed, iclass 31, count 2 2006.257.06:35:38.38#ibcon#about to write, iclass 31, count 2 2006.257.06:35:38.38#ibcon#wrote, iclass 31, count 2 2006.257.06:35:38.38#ibcon#about to read 3, iclass 31, count 2 2006.257.06:35:38.40#ibcon#read 3, iclass 31, count 2 2006.257.06:35:38.40#ibcon#about to read 4, iclass 31, count 2 2006.257.06:35:38.40#ibcon#read 4, iclass 31, count 2 2006.257.06:35:38.40#ibcon#about to read 5, iclass 31, count 2 2006.257.06:35:38.40#ibcon#read 5, iclass 31, count 2 2006.257.06:35:38.40#ibcon#about to read 6, iclass 31, count 2 2006.257.06:35:38.40#ibcon#read 6, iclass 31, count 2 2006.257.06:35:38.40#ibcon#end of sib2, iclass 31, count 2 2006.257.06:35:38.40#ibcon#*mode == 0, iclass 31, count 2 2006.257.06:35:38.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.06:35:38.40#ibcon#[27=AT05-04\r\n] 2006.257.06:35:38.40#ibcon#*before write, iclass 31, count 2 2006.257.06:35:38.40#ibcon#enter sib2, iclass 31, count 2 2006.257.06:35:38.40#ibcon#flushed, iclass 31, count 2 2006.257.06:35:38.40#ibcon#about to write, iclass 31, count 2 2006.257.06:35:38.40#ibcon#wrote, iclass 31, count 2 2006.257.06:35:38.40#ibcon#about to read 3, iclass 31, count 2 2006.257.06:35:38.43#ibcon#read 3, iclass 31, count 2 2006.257.06:35:38.43#ibcon#about to read 4, iclass 31, count 2 2006.257.06:35:38.43#ibcon#read 4, iclass 31, count 2 2006.257.06:35:38.43#ibcon#about to read 5, iclass 31, count 2 2006.257.06:35:38.43#ibcon#read 5, iclass 31, count 2 2006.257.06:35:38.43#ibcon#about to read 6, iclass 31, count 2 2006.257.06:35:38.43#ibcon#read 6, iclass 31, count 2 2006.257.06:35:38.43#ibcon#end of sib2, iclass 31, count 2 2006.257.06:35:38.43#ibcon#*after write, iclass 31, count 2 2006.257.06:35:38.43#ibcon#*before return 0, iclass 31, count 2 2006.257.06:35:38.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:38.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:35:38.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.06:35:38.43#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:38.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:38.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:38.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:38.55#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:35:38.55#ibcon#first serial, iclass 31, count 0 2006.257.06:35:38.55#ibcon#enter sib2, iclass 31, count 0 2006.257.06:35:38.55#ibcon#flushed, iclass 31, count 0 2006.257.06:35:38.55#ibcon#about to write, iclass 31, count 0 2006.257.06:35:38.55#ibcon#wrote, iclass 31, count 0 2006.257.06:35:38.55#ibcon#about to read 3, iclass 31, count 0 2006.257.06:35:38.57#ibcon#read 3, iclass 31, count 0 2006.257.06:35:38.57#ibcon#about to read 4, iclass 31, count 0 2006.257.06:35:38.57#ibcon#read 4, iclass 31, count 0 2006.257.06:35:38.57#ibcon#about to read 5, iclass 31, count 0 2006.257.06:35:38.57#ibcon#read 5, iclass 31, count 0 2006.257.06:35:38.57#ibcon#about to read 6, iclass 31, count 0 2006.257.06:35:38.57#ibcon#read 6, iclass 31, count 0 2006.257.06:35:38.57#ibcon#end of sib2, iclass 31, count 0 2006.257.06:35:38.57#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:35:38.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:35:38.57#ibcon#[27=USB\r\n] 2006.257.06:35:38.57#ibcon#*before write, iclass 31, count 0 2006.257.06:35:38.57#ibcon#enter sib2, iclass 31, count 0 2006.257.06:35:38.57#ibcon#flushed, iclass 31, count 0 2006.257.06:35:38.57#ibcon#about to write, iclass 31, count 0 2006.257.06:35:38.57#ibcon#wrote, iclass 31, count 0 2006.257.06:35:38.57#ibcon#about to read 3, iclass 31, count 0 2006.257.06:35:38.60#ibcon#read 3, iclass 31, count 0 2006.257.06:35:38.60#ibcon#about to read 4, iclass 31, count 0 2006.257.06:35:38.60#ibcon#read 4, iclass 31, count 0 2006.257.06:35:38.60#ibcon#about to read 5, iclass 31, count 0 2006.257.06:35:38.60#ibcon#read 5, iclass 31, count 0 2006.257.06:35:38.60#ibcon#about to read 6, iclass 31, count 0 2006.257.06:35:38.60#ibcon#read 6, iclass 31, count 0 2006.257.06:35:38.60#ibcon#end of sib2, iclass 31, count 0 2006.257.06:35:38.60#ibcon#*after write, iclass 31, count 0 2006.257.06:35:38.60#ibcon#*before return 0, iclass 31, count 0 2006.257.06:35:38.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:38.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:35:38.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:35:38.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:35:38.60$vck44/vblo=6,719.99 2006.257.06:35:38.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.06:35:38.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.06:35:38.60#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:38.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:38.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:38.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:38.60#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:35:38.60#ibcon#first serial, iclass 33, count 0 2006.257.06:35:38.60#ibcon#enter sib2, iclass 33, count 0 2006.257.06:35:38.60#ibcon#flushed, iclass 33, count 0 2006.257.06:35:38.60#ibcon#about to write, iclass 33, count 0 2006.257.06:35:38.60#ibcon#wrote, iclass 33, count 0 2006.257.06:35:38.60#ibcon#about to read 3, iclass 33, count 0 2006.257.06:35:38.62#ibcon#read 3, iclass 33, count 0 2006.257.06:35:38.62#ibcon#about to read 4, iclass 33, count 0 2006.257.06:35:38.62#ibcon#read 4, iclass 33, count 0 2006.257.06:35:38.62#ibcon#about to read 5, iclass 33, count 0 2006.257.06:35:38.62#ibcon#read 5, iclass 33, count 0 2006.257.06:35:38.62#ibcon#about to read 6, iclass 33, count 0 2006.257.06:35:38.62#ibcon#read 6, iclass 33, count 0 2006.257.06:35:38.62#ibcon#end of sib2, iclass 33, count 0 2006.257.06:35:38.62#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:35:38.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:35:38.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:35:38.62#ibcon#*before write, iclass 33, count 0 2006.257.06:35:38.62#ibcon#enter sib2, iclass 33, count 0 2006.257.06:35:38.62#ibcon#flushed, iclass 33, count 0 2006.257.06:35:38.62#ibcon#about to write, iclass 33, count 0 2006.257.06:35:38.62#ibcon#wrote, iclass 33, count 0 2006.257.06:35:38.62#ibcon#about to read 3, iclass 33, count 0 2006.257.06:35:38.66#ibcon#read 3, iclass 33, count 0 2006.257.06:35:38.66#ibcon#about to read 4, iclass 33, count 0 2006.257.06:35:38.66#ibcon#read 4, iclass 33, count 0 2006.257.06:35:38.66#ibcon#about to read 5, iclass 33, count 0 2006.257.06:35:38.66#ibcon#read 5, iclass 33, count 0 2006.257.06:35:38.66#ibcon#about to read 6, iclass 33, count 0 2006.257.06:35:38.66#ibcon#read 6, iclass 33, count 0 2006.257.06:35:38.66#ibcon#end of sib2, iclass 33, count 0 2006.257.06:35:38.66#ibcon#*after write, iclass 33, count 0 2006.257.06:35:38.66#ibcon#*before return 0, iclass 33, count 0 2006.257.06:35:38.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:38.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:35:38.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:35:38.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:35:38.66$vck44/vb=6,4 2006.257.06:35:38.66#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.06:35:38.66#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.06:35:38.66#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:38.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:38.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:38.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:38.72#ibcon#enter wrdev, iclass 35, count 2 2006.257.06:35:38.72#ibcon#first serial, iclass 35, count 2 2006.257.06:35:38.72#ibcon#enter sib2, iclass 35, count 2 2006.257.06:35:38.72#ibcon#flushed, iclass 35, count 2 2006.257.06:35:38.72#ibcon#about to write, iclass 35, count 2 2006.257.06:35:38.72#ibcon#wrote, iclass 35, count 2 2006.257.06:35:38.72#ibcon#about to read 3, iclass 35, count 2 2006.257.06:35:38.74#ibcon#read 3, iclass 35, count 2 2006.257.06:35:38.74#ibcon#about to read 4, iclass 35, count 2 2006.257.06:35:38.74#ibcon#read 4, iclass 35, count 2 2006.257.06:35:38.74#ibcon#about to read 5, iclass 35, count 2 2006.257.06:35:38.74#ibcon#read 5, iclass 35, count 2 2006.257.06:35:38.74#ibcon#about to read 6, iclass 35, count 2 2006.257.06:35:38.74#ibcon#read 6, iclass 35, count 2 2006.257.06:35:38.74#ibcon#end of sib2, iclass 35, count 2 2006.257.06:35:38.74#ibcon#*mode == 0, iclass 35, count 2 2006.257.06:35:38.74#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.06:35:38.74#ibcon#[27=AT06-04\r\n] 2006.257.06:35:38.74#ibcon#*before write, iclass 35, count 2 2006.257.06:35:38.74#ibcon#enter sib2, iclass 35, count 2 2006.257.06:35:38.74#ibcon#flushed, iclass 35, count 2 2006.257.06:35:38.74#ibcon#about to write, iclass 35, count 2 2006.257.06:35:38.74#ibcon#wrote, iclass 35, count 2 2006.257.06:35:38.74#ibcon#about to read 3, iclass 35, count 2 2006.257.06:35:38.77#ibcon#read 3, iclass 35, count 2 2006.257.06:35:38.77#ibcon#about to read 4, iclass 35, count 2 2006.257.06:35:38.77#ibcon#read 4, iclass 35, count 2 2006.257.06:35:38.77#ibcon#about to read 5, iclass 35, count 2 2006.257.06:35:38.77#ibcon#read 5, iclass 35, count 2 2006.257.06:35:38.77#ibcon#about to read 6, iclass 35, count 2 2006.257.06:35:38.77#ibcon#read 6, iclass 35, count 2 2006.257.06:35:38.77#ibcon#end of sib2, iclass 35, count 2 2006.257.06:35:38.77#ibcon#*after write, iclass 35, count 2 2006.257.06:35:38.77#ibcon#*before return 0, iclass 35, count 2 2006.257.06:35:38.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:38.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:35:38.77#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.06:35:38.77#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:38.77#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:38.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:38.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:38.89#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:35:38.89#ibcon#first serial, iclass 35, count 0 2006.257.06:35:38.89#ibcon#enter sib2, iclass 35, count 0 2006.257.06:35:38.89#ibcon#flushed, iclass 35, count 0 2006.257.06:35:38.89#ibcon#about to write, iclass 35, count 0 2006.257.06:35:38.89#ibcon#wrote, iclass 35, count 0 2006.257.06:35:38.89#ibcon#about to read 3, iclass 35, count 0 2006.257.06:35:38.91#ibcon#read 3, iclass 35, count 0 2006.257.06:35:38.91#ibcon#about to read 4, iclass 35, count 0 2006.257.06:35:38.91#ibcon#read 4, iclass 35, count 0 2006.257.06:35:38.91#ibcon#about to read 5, iclass 35, count 0 2006.257.06:35:38.91#ibcon#read 5, iclass 35, count 0 2006.257.06:35:38.91#ibcon#about to read 6, iclass 35, count 0 2006.257.06:35:38.91#ibcon#read 6, iclass 35, count 0 2006.257.06:35:38.91#ibcon#end of sib2, iclass 35, count 0 2006.257.06:35:38.91#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:35:38.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:35:38.91#ibcon#[27=USB\r\n] 2006.257.06:35:38.91#ibcon#*before write, iclass 35, count 0 2006.257.06:35:38.91#ibcon#enter sib2, iclass 35, count 0 2006.257.06:35:38.91#ibcon#flushed, iclass 35, count 0 2006.257.06:35:38.91#ibcon#about to write, iclass 35, count 0 2006.257.06:35:38.91#ibcon#wrote, iclass 35, count 0 2006.257.06:35:38.91#ibcon#about to read 3, iclass 35, count 0 2006.257.06:35:38.94#ibcon#read 3, iclass 35, count 0 2006.257.06:35:38.94#ibcon#about to read 4, iclass 35, count 0 2006.257.06:35:38.94#ibcon#read 4, iclass 35, count 0 2006.257.06:35:38.94#ibcon#about to read 5, iclass 35, count 0 2006.257.06:35:38.94#ibcon#read 5, iclass 35, count 0 2006.257.06:35:38.94#ibcon#about to read 6, iclass 35, count 0 2006.257.06:35:38.94#ibcon#read 6, iclass 35, count 0 2006.257.06:35:38.94#ibcon#end of sib2, iclass 35, count 0 2006.257.06:35:38.94#ibcon#*after write, iclass 35, count 0 2006.257.06:35:38.94#ibcon#*before return 0, iclass 35, count 0 2006.257.06:35:38.94#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:38.94#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:35:38.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:35:38.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:35:38.94$vck44/vblo=7,734.99 2006.257.06:35:38.94#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.06:35:38.94#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.06:35:38.94#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:38.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:38.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:38.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:38.94#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:35:38.94#ibcon#first serial, iclass 37, count 0 2006.257.06:35:38.94#ibcon#enter sib2, iclass 37, count 0 2006.257.06:35:38.94#ibcon#flushed, iclass 37, count 0 2006.257.06:35:38.94#ibcon#about to write, iclass 37, count 0 2006.257.06:35:38.94#ibcon#wrote, iclass 37, count 0 2006.257.06:35:38.94#ibcon#about to read 3, iclass 37, count 0 2006.257.06:35:38.96#ibcon#read 3, iclass 37, count 0 2006.257.06:35:38.96#ibcon#about to read 4, iclass 37, count 0 2006.257.06:35:38.96#ibcon#read 4, iclass 37, count 0 2006.257.06:35:38.96#ibcon#about to read 5, iclass 37, count 0 2006.257.06:35:38.96#ibcon#read 5, iclass 37, count 0 2006.257.06:35:38.96#ibcon#about to read 6, iclass 37, count 0 2006.257.06:35:38.96#ibcon#read 6, iclass 37, count 0 2006.257.06:35:38.96#ibcon#end of sib2, iclass 37, count 0 2006.257.06:35:38.96#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:35:38.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:35:38.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:35:38.96#ibcon#*before write, iclass 37, count 0 2006.257.06:35:38.96#ibcon#enter sib2, iclass 37, count 0 2006.257.06:35:38.96#ibcon#flushed, iclass 37, count 0 2006.257.06:35:38.96#ibcon#about to write, iclass 37, count 0 2006.257.06:35:38.96#ibcon#wrote, iclass 37, count 0 2006.257.06:35:38.96#ibcon#about to read 3, iclass 37, count 0 2006.257.06:35:39.00#ibcon#read 3, iclass 37, count 0 2006.257.06:35:39.00#ibcon#about to read 4, iclass 37, count 0 2006.257.06:35:39.00#ibcon#read 4, iclass 37, count 0 2006.257.06:35:39.00#ibcon#about to read 5, iclass 37, count 0 2006.257.06:35:39.00#ibcon#read 5, iclass 37, count 0 2006.257.06:35:39.00#ibcon#about to read 6, iclass 37, count 0 2006.257.06:35:39.00#ibcon#read 6, iclass 37, count 0 2006.257.06:35:39.00#ibcon#end of sib2, iclass 37, count 0 2006.257.06:35:39.00#ibcon#*after write, iclass 37, count 0 2006.257.06:35:39.00#ibcon#*before return 0, iclass 37, count 0 2006.257.06:35:39.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:39.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:35:39.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:35:39.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:35:39.00$vck44/vb=7,4 2006.257.06:35:39.00#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.06:35:39.00#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.06:35:39.00#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:39.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:39.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:39.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:39.06#ibcon#enter wrdev, iclass 39, count 2 2006.257.06:35:39.06#ibcon#first serial, iclass 39, count 2 2006.257.06:35:39.06#ibcon#enter sib2, iclass 39, count 2 2006.257.06:35:39.06#ibcon#flushed, iclass 39, count 2 2006.257.06:35:39.06#ibcon#about to write, iclass 39, count 2 2006.257.06:35:39.06#ibcon#wrote, iclass 39, count 2 2006.257.06:35:39.06#ibcon#about to read 3, iclass 39, count 2 2006.257.06:35:39.08#ibcon#read 3, iclass 39, count 2 2006.257.06:35:39.08#ibcon#about to read 4, iclass 39, count 2 2006.257.06:35:39.08#ibcon#read 4, iclass 39, count 2 2006.257.06:35:39.08#ibcon#about to read 5, iclass 39, count 2 2006.257.06:35:39.08#ibcon#read 5, iclass 39, count 2 2006.257.06:35:39.08#ibcon#about to read 6, iclass 39, count 2 2006.257.06:35:39.08#ibcon#read 6, iclass 39, count 2 2006.257.06:35:39.08#ibcon#end of sib2, iclass 39, count 2 2006.257.06:35:39.08#ibcon#*mode == 0, iclass 39, count 2 2006.257.06:35:39.08#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.06:35:39.08#ibcon#[27=AT07-04\r\n] 2006.257.06:35:39.08#ibcon#*before write, iclass 39, count 2 2006.257.06:35:39.08#ibcon#enter sib2, iclass 39, count 2 2006.257.06:35:39.08#ibcon#flushed, iclass 39, count 2 2006.257.06:35:39.08#ibcon#about to write, iclass 39, count 2 2006.257.06:35:39.08#ibcon#wrote, iclass 39, count 2 2006.257.06:35:39.08#ibcon#about to read 3, iclass 39, count 2 2006.257.06:35:39.11#ibcon#read 3, iclass 39, count 2 2006.257.06:35:39.11#ibcon#about to read 4, iclass 39, count 2 2006.257.06:35:39.11#ibcon#read 4, iclass 39, count 2 2006.257.06:35:39.11#ibcon#about to read 5, iclass 39, count 2 2006.257.06:35:39.11#ibcon#read 5, iclass 39, count 2 2006.257.06:35:39.11#ibcon#about to read 6, iclass 39, count 2 2006.257.06:35:39.11#ibcon#read 6, iclass 39, count 2 2006.257.06:35:39.11#ibcon#end of sib2, iclass 39, count 2 2006.257.06:35:39.11#ibcon#*after write, iclass 39, count 2 2006.257.06:35:39.11#ibcon#*before return 0, iclass 39, count 2 2006.257.06:35:39.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:39.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:35:39.11#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.06:35:39.11#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:39.11#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:39.23#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:39.23#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:39.23#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:35:39.23#ibcon#first serial, iclass 39, count 0 2006.257.06:35:39.23#ibcon#enter sib2, iclass 39, count 0 2006.257.06:35:39.23#ibcon#flushed, iclass 39, count 0 2006.257.06:35:39.23#ibcon#about to write, iclass 39, count 0 2006.257.06:35:39.23#ibcon#wrote, iclass 39, count 0 2006.257.06:35:39.23#ibcon#about to read 3, iclass 39, count 0 2006.257.06:35:39.25#ibcon#read 3, iclass 39, count 0 2006.257.06:35:39.25#ibcon#about to read 4, iclass 39, count 0 2006.257.06:35:39.25#ibcon#read 4, iclass 39, count 0 2006.257.06:35:39.25#ibcon#about to read 5, iclass 39, count 0 2006.257.06:35:39.25#ibcon#read 5, iclass 39, count 0 2006.257.06:35:39.25#ibcon#about to read 6, iclass 39, count 0 2006.257.06:35:39.25#ibcon#read 6, iclass 39, count 0 2006.257.06:35:39.25#ibcon#end of sib2, iclass 39, count 0 2006.257.06:35:39.25#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:35:39.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:35:39.25#ibcon#[27=USB\r\n] 2006.257.06:35:39.25#ibcon#*before write, iclass 39, count 0 2006.257.06:35:39.25#ibcon#enter sib2, iclass 39, count 0 2006.257.06:35:39.25#ibcon#flushed, iclass 39, count 0 2006.257.06:35:39.25#ibcon#about to write, iclass 39, count 0 2006.257.06:35:39.25#ibcon#wrote, iclass 39, count 0 2006.257.06:35:39.25#ibcon#about to read 3, iclass 39, count 0 2006.257.06:35:39.28#ibcon#read 3, iclass 39, count 0 2006.257.06:35:39.28#ibcon#about to read 4, iclass 39, count 0 2006.257.06:35:39.28#ibcon#read 4, iclass 39, count 0 2006.257.06:35:39.28#ibcon#about to read 5, iclass 39, count 0 2006.257.06:35:39.28#ibcon#read 5, iclass 39, count 0 2006.257.06:35:39.28#ibcon#about to read 6, iclass 39, count 0 2006.257.06:35:39.28#ibcon#read 6, iclass 39, count 0 2006.257.06:35:39.28#ibcon#end of sib2, iclass 39, count 0 2006.257.06:35:39.28#ibcon#*after write, iclass 39, count 0 2006.257.06:35:39.28#ibcon#*before return 0, iclass 39, count 0 2006.257.06:35:39.28#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:39.28#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:35:39.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:35:39.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:35:39.28$vck44/vblo=8,744.99 2006.257.06:35:39.28#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.06:35:39.28#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.06:35:39.28#ibcon#ireg 17 cls_cnt 0 2006.257.06:35:39.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:39.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:39.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:39.28#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:35:39.28#ibcon#first serial, iclass 3, count 0 2006.257.06:35:39.28#ibcon#enter sib2, iclass 3, count 0 2006.257.06:35:39.28#ibcon#flushed, iclass 3, count 0 2006.257.06:35:39.28#ibcon#about to write, iclass 3, count 0 2006.257.06:35:39.28#ibcon#wrote, iclass 3, count 0 2006.257.06:35:39.28#ibcon#about to read 3, iclass 3, count 0 2006.257.06:35:39.30#ibcon#read 3, iclass 3, count 0 2006.257.06:35:39.30#ibcon#about to read 4, iclass 3, count 0 2006.257.06:35:39.30#ibcon#read 4, iclass 3, count 0 2006.257.06:35:39.30#ibcon#about to read 5, iclass 3, count 0 2006.257.06:35:39.30#ibcon#read 5, iclass 3, count 0 2006.257.06:35:39.30#ibcon#about to read 6, iclass 3, count 0 2006.257.06:35:39.30#ibcon#read 6, iclass 3, count 0 2006.257.06:35:39.30#ibcon#end of sib2, iclass 3, count 0 2006.257.06:35:39.30#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:35:39.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:35:39.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:35:39.30#ibcon#*before write, iclass 3, count 0 2006.257.06:35:39.30#ibcon#enter sib2, iclass 3, count 0 2006.257.06:35:39.30#ibcon#flushed, iclass 3, count 0 2006.257.06:35:39.30#ibcon#about to write, iclass 3, count 0 2006.257.06:35:39.30#ibcon#wrote, iclass 3, count 0 2006.257.06:35:39.30#ibcon#about to read 3, iclass 3, count 0 2006.257.06:35:39.34#ibcon#read 3, iclass 3, count 0 2006.257.06:35:39.34#ibcon#about to read 4, iclass 3, count 0 2006.257.06:35:39.34#ibcon#read 4, iclass 3, count 0 2006.257.06:35:39.34#ibcon#about to read 5, iclass 3, count 0 2006.257.06:35:39.34#ibcon#read 5, iclass 3, count 0 2006.257.06:35:39.34#ibcon#about to read 6, iclass 3, count 0 2006.257.06:35:39.34#ibcon#read 6, iclass 3, count 0 2006.257.06:35:39.34#ibcon#end of sib2, iclass 3, count 0 2006.257.06:35:39.34#ibcon#*after write, iclass 3, count 0 2006.257.06:35:39.34#ibcon#*before return 0, iclass 3, count 0 2006.257.06:35:39.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:39.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:35:39.34#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:35:39.34#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:35:39.34$vck44/vb=8,4 2006.257.06:35:39.34#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.06:35:39.34#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.06:35:39.34#ibcon#ireg 11 cls_cnt 2 2006.257.06:35:39.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:39.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:39.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:39.40#ibcon#enter wrdev, iclass 5, count 2 2006.257.06:35:39.40#ibcon#first serial, iclass 5, count 2 2006.257.06:35:39.40#ibcon#enter sib2, iclass 5, count 2 2006.257.06:35:39.40#ibcon#flushed, iclass 5, count 2 2006.257.06:35:39.40#ibcon#about to write, iclass 5, count 2 2006.257.06:35:39.40#ibcon#wrote, iclass 5, count 2 2006.257.06:35:39.40#ibcon#about to read 3, iclass 5, count 2 2006.257.06:35:39.42#ibcon#read 3, iclass 5, count 2 2006.257.06:35:39.42#ibcon#about to read 4, iclass 5, count 2 2006.257.06:35:39.42#ibcon#read 4, iclass 5, count 2 2006.257.06:35:39.42#ibcon#about to read 5, iclass 5, count 2 2006.257.06:35:39.42#ibcon#read 5, iclass 5, count 2 2006.257.06:35:39.42#ibcon#about to read 6, iclass 5, count 2 2006.257.06:35:39.42#ibcon#read 6, iclass 5, count 2 2006.257.06:35:39.42#ibcon#end of sib2, iclass 5, count 2 2006.257.06:35:39.42#ibcon#*mode == 0, iclass 5, count 2 2006.257.06:35:39.42#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.06:35:39.42#ibcon#[27=AT08-04\r\n] 2006.257.06:35:39.42#ibcon#*before write, iclass 5, count 2 2006.257.06:35:39.42#ibcon#enter sib2, iclass 5, count 2 2006.257.06:35:39.42#ibcon#flushed, iclass 5, count 2 2006.257.06:35:39.42#ibcon#about to write, iclass 5, count 2 2006.257.06:35:39.42#ibcon#wrote, iclass 5, count 2 2006.257.06:35:39.42#ibcon#about to read 3, iclass 5, count 2 2006.257.06:35:39.45#ibcon#read 3, iclass 5, count 2 2006.257.06:35:39.45#ibcon#about to read 4, iclass 5, count 2 2006.257.06:35:39.45#ibcon#read 4, iclass 5, count 2 2006.257.06:35:39.45#ibcon#about to read 5, iclass 5, count 2 2006.257.06:35:39.45#ibcon#read 5, iclass 5, count 2 2006.257.06:35:39.45#ibcon#about to read 6, iclass 5, count 2 2006.257.06:35:39.45#ibcon#read 6, iclass 5, count 2 2006.257.06:35:39.45#ibcon#end of sib2, iclass 5, count 2 2006.257.06:35:39.45#ibcon#*after write, iclass 5, count 2 2006.257.06:35:39.45#ibcon#*before return 0, iclass 5, count 2 2006.257.06:35:39.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:39.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:35:39.45#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.06:35:39.45#ibcon#ireg 7 cls_cnt 0 2006.257.06:35:39.45#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:39.57#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:39.57#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:39.57#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:35:39.57#ibcon#first serial, iclass 5, count 0 2006.257.06:35:39.57#ibcon#enter sib2, iclass 5, count 0 2006.257.06:35:39.57#ibcon#flushed, iclass 5, count 0 2006.257.06:35:39.57#ibcon#about to write, iclass 5, count 0 2006.257.06:35:39.57#ibcon#wrote, iclass 5, count 0 2006.257.06:35:39.57#ibcon#about to read 3, iclass 5, count 0 2006.257.06:35:39.59#ibcon#read 3, iclass 5, count 0 2006.257.06:35:39.59#ibcon#about to read 4, iclass 5, count 0 2006.257.06:35:39.59#ibcon#read 4, iclass 5, count 0 2006.257.06:35:39.59#ibcon#about to read 5, iclass 5, count 0 2006.257.06:35:39.59#ibcon#read 5, iclass 5, count 0 2006.257.06:35:39.59#ibcon#about to read 6, iclass 5, count 0 2006.257.06:35:39.59#ibcon#read 6, iclass 5, count 0 2006.257.06:35:39.59#ibcon#end of sib2, iclass 5, count 0 2006.257.06:35:39.59#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:35:39.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:35:39.59#ibcon#[27=USB\r\n] 2006.257.06:35:39.59#ibcon#*before write, iclass 5, count 0 2006.257.06:35:39.59#ibcon#enter sib2, iclass 5, count 0 2006.257.06:35:39.59#ibcon#flushed, iclass 5, count 0 2006.257.06:35:39.59#ibcon#about to write, iclass 5, count 0 2006.257.06:35:39.59#ibcon#wrote, iclass 5, count 0 2006.257.06:35:39.59#ibcon#about to read 3, iclass 5, count 0 2006.257.06:35:39.62#ibcon#read 3, iclass 5, count 0 2006.257.06:35:39.62#ibcon#about to read 4, iclass 5, count 0 2006.257.06:35:39.62#ibcon#read 4, iclass 5, count 0 2006.257.06:35:39.62#ibcon#about to read 5, iclass 5, count 0 2006.257.06:35:39.62#ibcon#read 5, iclass 5, count 0 2006.257.06:35:39.62#ibcon#about to read 6, iclass 5, count 0 2006.257.06:35:39.62#ibcon#read 6, iclass 5, count 0 2006.257.06:35:39.62#ibcon#end of sib2, iclass 5, count 0 2006.257.06:35:39.62#ibcon#*after write, iclass 5, count 0 2006.257.06:35:39.62#ibcon#*before return 0, iclass 5, count 0 2006.257.06:35:39.62#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:39.62#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:35:39.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:35:39.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:35:39.62$vck44/vabw=wide 2006.257.06:35:39.62#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.06:35:39.62#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.06:35:39.62#ibcon#ireg 8 cls_cnt 0 2006.257.06:35:39.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:39.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:39.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:39.62#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:35:39.62#ibcon#first serial, iclass 7, count 0 2006.257.06:35:39.62#ibcon#enter sib2, iclass 7, count 0 2006.257.06:35:39.62#ibcon#flushed, iclass 7, count 0 2006.257.06:35:39.62#ibcon#about to write, iclass 7, count 0 2006.257.06:35:39.62#ibcon#wrote, iclass 7, count 0 2006.257.06:35:39.62#ibcon#about to read 3, iclass 7, count 0 2006.257.06:35:39.64#ibcon#read 3, iclass 7, count 0 2006.257.06:35:39.64#ibcon#about to read 4, iclass 7, count 0 2006.257.06:35:39.64#ibcon#read 4, iclass 7, count 0 2006.257.06:35:39.64#ibcon#about to read 5, iclass 7, count 0 2006.257.06:35:39.64#ibcon#read 5, iclass 7, count 0 2006.257.06:35:39.64#ibcon#about to read 6, iclass 7, count 0 2006.257.06:35:39.64#ibcon#read 6, iclass 7, count 0 2006.257.06:35:39.64#ibcon#end of sib2, iclass 7, count 0 2006.257.06:35:39.64#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:35:39.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:35:39.64#ibcon#[25=BW32\r\n] 2006.257.06:35:39.64#ibcon#*before write, iclass 7, count 0 2006.257.06:35:39.64#ibcon#enter sib2, iclass 7, count 0 2006.257.06:35:39.64#ibcon#flushed, iclass 7, count 0 2006.257.06:35:39.64#ibcon#about to write, iclass 7, count 0 2006.257.06:35:39.64#ibcon#wrote, iclass 7, count 0 2006.257.06:35:39.64#ibcon#about to read 3, iclass 7, count 0 2006.257.06:35:39.67#ibcon#read 3, iclass 7, count 0 2006.257.06:35:39.67#ibcon#about to read 4, iclass 7, count 0 2006.257.06:35:39.67#ibcon#read 4, iclass 7, count 0 2006.257.06:35:39.67#ibcon#about to read 5, iclass 7, count 0 2006.257.06:35:39.67#ibcon#read 5, iclass 7, count 0 2006.257.06:35:39.67#ibcon#about to read 6, iclass 7, count 0 2006.257.06:35:39.67#ibcon#read 6, iclass 7, count 0 2006.257.06:35:39.67#ibcon#end of sib2, iclass 7, count 0 2006.257.06:35:39.67#ibcon#*after write, iclass 7, count 0 2006.257.06:35:39.67#ibcon#*before return 0, iclass 7, count 0 2006.257.06:35:39.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:39.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:35:39.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:35:39.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:35:39.67$vck44/vbbw=wide 2006.257.06:35:39.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.06:35:39.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.06:35:39.67#ibcon#ireg 8 cls_cnt 0 2006.257.06:35:39.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:35:39.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:35:39.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:35:39.74#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:35:39.74#ibcon#first serial, iclass 11, count 0 2006.257.06:35:39.74#ibcon#enter sib2, iclass 11, count 0 2006.257.06:35:39.74#ibcon#flushed, iclass 11, count 0 2006.257.06:35:39.74#ibcon#about to write, iclass 11, count 0 2006.257.06:35:39.74#ibcon#wrote, iclass 11, count 0 2006.257.06:35:39.74#ibcon#about to read 3, iclass 11, count 0 2006.257.06:35:39.76#ibcon#read 3, iclass 11, count 0 2006.257.06:35:39.76#ibcon#about to read 4, iclass 11, count 0 2006.257.06:35:39.76#ibcon#read 4, iclass 11, count 0 2006.257.06:35:39.76#ibcon#about to read 5, iclass 11, count 0 2006.257.06:35:39.76#ibcon#read 5, iclass 11, count 0 2006.257.06:35:39.76#ibcon#about to read 6, iclass 11, count 0 2006.257.06:35:39.76#ibcon#read 6, iclass 11, count 0 2006.257.06:35:39.76#ibcon#end of sib2, iclass 11, count 0 2006.257.06:35:39.76#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:35:39.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:35:39.76#ibcon#[27=BW32\r\n] 2006.257.06:35:39.76#ibcon#*before write, iclass 11, count 0 2006.257.06:35:39.76#ibcon#enter sib2, iclass 11, count 0 2006.257.06:35:39.76#ibcon#flushed, iclass 11, count 0 2006.257.06:35:39.76#ibcon#about to write, iclass 11, count 0 2006.257.06:35:39.76#ibcon#wrote, iclass 11, count 0 2006.257.06:35:39.76#ibcon#about to read 3, iclass 11, count 0 2006.257.06:35:39.79#ibcon#read 3, iclass 11, count 0 2006.257.06:35:39.79#ibcon#about to read 4, iclass 11, count 0 2006.257.06:35:39.79#ibcon#read 4, iclass 11, count 0 2006.257.06:35:39.79#ibcon#about to read 5, iclass 11, count 0 2006.257.06:35:39.79#ibcon#read 5, iclass 11, count 0 2006.257.06:35:39.79#ibcon#about to read 6, iclass 11, count 0 2006.257.06:35:39.79#ibcon#read 6, iclass 11, count 0 2006.257.06:35:39.79#ibcon#end of sib2, iclass 11, count 0 2006.257.06:35:39.79#ibcon#*after write, iclass 11, count 0 2006.257.06:35:39.79#ibcon#*before return 0, iclass 11, count 0 2006.257.06:35:39.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:35:39.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:35:39.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:35:39.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:35:39.79$setupk4/ifdk4 2006.257.06:35:39.79$ifdk4/lo= 2006.257.06:35:39.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:35:39.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:35:39.79$ifdk4/patch= 2006.257.06:35:39.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:35:39.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:35:39.79$setupk4/!*+20s 2006.257.06:35:48.25#abcon#<5=/15 0.6 2.3 20.60 891012.3\r\n> 2006.257.06:35:48.27#abcon#{5=INTERFACE CLEAR} 2006.257.06:35:48.33#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:35:54.29$setupk4/"tpicd 2006.257.06:35:54.29$setupk4/echo=off 2006.257.06:35:54.29$setupk4/xlog=off 2006.257.06:35:54.29:!2006.257.06:38:29 2006.257.06:36:02.14#trakl#Source acquired 2006.257.06:36:02.14#flagr#flagr/antenna,acquired 2006.257.06:38:29.02:preob 2006.257.06:38:30.15/onsource/TRACKING 2006.257.06:38:30.15:!2006.257.06:38:39 2006.257.06:38:39.01:"tape 2006.257.06:38:39.02:"st=record 2006.257.06:38:39.02:data_valid=on 2006.257.06:38:39.02:midob 2006.257.06:38:40.15/onsource/TRACKING 2006.257.06:38:40.15/wx/20.65,1012.3,89 2006.257.06:38:40.27/cable/+6.4791E-03 2006.257.06:38:41.36/va/01,08,usb,yes,31,34 2006.257.06:38:41.36/va/02,07,usb,yes,34,34 2006.257.06:38:41.36/va/03,08,usb,yes,31,32 2006.257.06:38:41.36/va/04,07,usb,yes,35,37 2006.257.06:38:41.37/va/05,04,usb,yes,31,32 2006.257.06:38:41.37/va/06,04,usb,yes,35,35 2006.257.06:38:41.37/va/07,04,usb,yes,36,36 2006.257.06:38:41.37/va/08,04,usb,yes,30,37 2006.257.06:38:41.60/valo/01,524.99,yes,locked 2006.257.06:38:41.60/valo/02,534.99,yes,locked 2006.257.06:38:41.60/valo/03,564.99,yes,locked 2006.257.06:38:41.60/valo/04,624.99,yes,locked 2006.257.06:38:41.60/valo/05,734.99,yes,locked 2006.257.06:38:41.60/valo/06,814.99,yes,locked 2006.257.06:38:41.60/valo/07,864.99,yes,locked 2006.257.06:38:41.60/valo/08,884.99,yes,locked 2006.257.06:38:42.68/vb/01,04,usb,yes,31,29 2006.257.06:38:42.68/vb/02,05,usb,yes,29,29 2006.257.06:38:42.68/vb/03,04,usb,yes,30,33 2006.257.06:38:42.69/vb/04,05,usb,yes,30,29 2006.257.06:38:42.69/vb/05,04,usb,yes,27,29 2006.257.06:38:42.69/vb/06,04,usb,yes,31,28 2006.257.06:38:42.69/vb/07,04,usb,yes,31,31 2006.257.06:38:42.69/vb/08,04,usb,yes,29,32 2006.257.06:38:42.92/vblo/01,629.99,yes,locked 2006.257.06:38:42.92/vblo/02,634.99,yes,locked 2006.257.06:38:42.92/vblo/03,649.99,yes,locked 2006.257.06:38:42.92/vblo/04,679.99,yes,locked 2006.257.06:38:42.92/vblo/05,709.99,yes,locked 2006.257.06:38:42.92/vblo/06,719.99,yes,locked 2006.257.06:38:42.92/vblo/07,734.99,yes,locked 2006.257.06:38:42.92/vblo/08,744.99,yes,locked 2006.257.06:38:43.06/vabw/8 2006.257.06:38:43.21/vbbw/8 2006.257.06:38:43.30/xfe/off,on,16.7 2006.257.06:38:43.67/ifatt/23,28,28,28 2006.257.06:38:44.07/fmout-gps/S +4.47E-07 2006.257.06:38:44.11:!2006.257.06:39:19 2006.257.06:39:19.02:data_valid=off 2006.257.06:39:19.02:"et 2006.257.06:39:19.02:!+3s 2006.257.06:39:22.04:"tape 2006.257.06:39:22.05:postob 2006.257.06:39:22.15/cable/+6.4789E-03 2006.257.06:39:22.16/wx/20.66,1012.3,90 2006.257.06:39:22.21/fmout-gps/S +4.47E-07 2006.257.06:39:22.22:scan_name=257-0640,jd0609,40 2006.257.06:39:22.22:source=3c345,164258.81,394837.0,2000.0,cw 2006.257.06:39:23.15#flagr#flagr/antenna,new-source 2006.257.06:39:23.15:checkk5 2006.257.06:39:23.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:39:23.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:39:24.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:39:24.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:39:25.15/chk_obsdata//k5ts1/T2570638??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.06:39:25.55/chk_obsdata//k5ts2/T2570638??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.06:39:25.99/chk_obsdata//k5ts3/T2570638??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.06:39:26.38/chk_obsdata//k5ts4/T2570638??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.06:39:27.09/k5log//k5ts1_log_newline 2006.257.06:39:27.82/k5log//k5ts2_log_newline 2006.257.06:39:28.55/k5log//k5ts3_log_newline 2006.257.06:39:29.29/k5log//k5ts4_log_newline 2006.257.06:39:29.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:39:29.31:setupk4=1 2006.257.06:39:29.31$setupk4/echo=on 2006.257.06:39:29.31$setupk4/pcalon 2006.257.06:39:29.31$pcalon/"no phase cal control is implemented here 2006.257.06:39:29.31$setupk4/"tpicd=stop 2006.257.06:39:29.31$setupk4/"rec=synch_on 2006.257.06:39:29.31$setupk4/"rec_mode=128 2006.257.06:39:29.31$setupk4/!* 2006.257.06:39:29.31$setupk4/recpk4 2006.257.06:39:29.31$recpk4/recpatch= 2006.257.06:39:29.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:39:29.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:39:29.32$setupk4/vck44 2006.257.06:39:29.32$vck44/valo=1,524.99 2006.257.06:39:29.32#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.06:39:29.32#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.06:39:29.32#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:29.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:39:29.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:39:29.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:39:29.32#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:39:29.32#ibcon#first serial, iclass 32, count 0 2006.257.06:39:29.32#ibcon#enter sib2, iclass 32, count 0 2006.257.06:39:29.32#ibcon#flushed, iclass 32, count 0 2006.257.06:39:29.32#ibcon#about to write, iclass 32, count 0 2006.257.06:39:29.32#ibcon#wrote, iclass 32, count 0 2006.257.06:39:29.32#ibcon#about to read 3, iclass 32, count 0 2006.257.06:39:29.33#ibcon#read 3, iclass 32, count 0 2006.257.06:39:29.33#ibcon#about to read 4, iclass 32, count 0 2006.257.06:39:29.33#ibcon#read 4, iclass 32, count 0 2006.257.06:39:29.33#ibcon#about to read 5, iclass 32, count 0 2006.257.06:39:29.33#ibcon#read 5, iclass 32, count 0 2006.257.06:39:29.33#ibcon#about to read 6, iclass 32, count 0 2006.257.06:39:29.33#ibcon#read 6, iclass 32, count 0 2006.257.06:39:29.33#ibcon#end of sib2, iclass 32, count 0 2006.257.06:39:29.33#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:39:29.33#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:39:29.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:39:29.33#ibcon#*before write, iclass 32, count 0 2006.257.06:39:29.33#ibcon#enter sib2, iclass 32, count 0 2006.257.06:39:29.33#ibcon#flushed, iclass 32, count 0 2006.257.06:39:29.33#ibcon#about to write, iclass 32, count 0 2006.257.06:39:29.33#ibcon#wrote, iclass 32, count 0 2006.257.06:39:29.33#ibcon#about to read 3, iclass 32, count 0 2006.257.06:39:29.38#ibcon#read 3, iclass 32, count 0 2006.257.06:39:29.38#ibcon#about to read 4, iclass 32, count 0 2006.257.06:39:29.38#ibcon#read 4, iclass 32, count 0 2006.257.06:39:29.38#ibcon#about to read 5, iclass 32, count 0 2006.257.06:39:29.38#ibcon#read 5, iclass 32, count 0 2006.257.06:39:29.38#ibcon#about to read 6, iclass 32, count 0 2006.257.06:39:29.38#ibcon#read 6, iclass 32, count 0 2006.257.06:39:29.38#ibcon#end of sib2, iclass 32, count 0 2006.257.06:39:29.38#ibcon#*after write, iclass 32, count 0 2006.257.06:39:29.38#ibcon#*before return 0, iclass 32, count 0 2006.257.06:39:29.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:39:29.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:39:29.38#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:39:29.38#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:39:29.39$vck44/va=1,8 2006.257.06:39:29.39#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.06:39:29.39#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.06:39:29.39#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:29.39#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:39:29.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:39:29.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:39:29.39#ibcon#enter wrdev, iclass 34, count 2 2006.257.06:39:29.39#ibcon#first serial, iclass 34, count 2 2006.257.06:39:29.39#ibcon#enter sib2, iclass 34, count 2 2006.257.06:39:29.39#ibcon#flushed, iclass 34, count 2 2006.257.06:39:29.39#ibcon#about to write, iclass 34, count 2 2006.257.06:39:29.39#ibcon#wrote, iclass 34, count 2 2006.257.06:39:29.39#ibcon#about to read 3, iclass 34, count 2 2006.257.06:39:29.40#ibcon#read 3, iclass 34, count 2 2006.257.06:39:29.40#ibcon#about to read 4, iclass 34, count 2 2006.257.06:39:29.40#ibcon#read 4, iclass 34, count 2 2006.257.06:39:29.40#ibcon#about to read 5, iclass 34, count 2 2006.257.06:39:29.40#ibcon#read 5, iclass 34, count 2 2006.257.06:39:29.40#ibcon#about to read 6, iclass 34, count 2 2006.257.06:39:29.40#ibcon#read 6, iclass 34, count 2 2006.257.06:39:29.40#ibcon#end of sib2, iclass 34, count 2 2006.257.06:39:29.40#ibcon#*mode == 0, iclass 34, count 2 2006.257.06:39:29.40#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.06:39:29.40#ibcon#[25=AT01-08\r\n] 2006.257.06:39:29.40#ibcon#*before write, iclass 34, count 2 2006.257.06:39:29.40#ibcon#enter sib2, iclass 34, count 2 2006.257.06:39:29.40#ibcon#flushed, iclass 34, count 2 2006.257.06:39:29.40#ibcon#about to write, iclass 34, count 2 2006.257.06:39:29.40#ibcon#wrote, iclass 34, count 2 2006.257.06:39:29.40#ibcon#about to read 3, iclass 34, count 2 2006.257.06:39:29.43#ibcon#read 3, iclass 34, count 2 2006.257.06:39:29.43#ibcon#about to read 4, iclass 34, count 2 2006.257.06:39:29.43#ibcon#read 4, iclass 34, count 2 2006.257.06:39:29.43#ibcon#about to read 5, iclass 34, count 2 2006.257.06:39:29.43#ibcon#read 5, iclass 34, count 2 2006.257.06:39:29.43#ibcon#about to read 6, iclass 34, count 2 2006.257.06:39:29.43#ibcon#read 6, iclass 34, count 2 2006.257.06:39:29.43#ibcon#end of sib2, iclass 34, count 2 2006.257.06:39:29.43#ibcon#*after write, iclass 34, count 2 2006.257.06:39:29.43#ibcon#*before return 0, iclass 34, count 2 2006.257.06:39:29.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:39:29.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:39:29.43#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.06:39:29.43#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:29.43#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:39:29.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:39:29.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:39:29.55#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:39:29.55#ibcon#first serial, iclass 34, count 0 2006.257.06:39:29.55#ibcon#enter sib2, iclass 34, count 0 2006.257.06:39:29.55#ibcon#flushed, iclass 34, count 0 2006.257.06:39:29.55#ibcon#about to write, iclass 34, count 0 2006.257.06:39:29.55#ibcon#wrote, iclass 34, count 0 2006.257.06:39:29.55#ibcon#about to read 3, iclass 34, count 0 2006.257.06:39:29.57#ibcon#read 3, iclass 34, count 0 2006.257.06:39:29.57#ibcon#about to read 4, iclass 34, count 0 2006.257.06:39:29.57#ibcon#read 4, iclass 34, count 0 2006.257.06:39:29.57#ibcon#about to read 5, iclass 34, count 0 2006.257.06:39:29.57#ibcon#read 5, iclass 34, count 0 2006.257.06:39:29.57#ibcon#about to read 6, iclass 34, count 0 2006.257.06:39:29.57#ibcon#read 6, iclass 34, count 0 2006.257.06:39:29.57#ibcon#end of sib2, iclass 34, count 0 2006.257.06:39:29.57#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:39:29.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:39:29.57#ibcon#[25=USB\r\n] 2006.257.06:39:29.57#ibcon#*before write, iclass 34, count 0 2006.257.06:39:29.57#ibcon#enter sib2, iclass 34, count 0 2006.257.06:39:29.57#ibcon#flushed, iclass 34, count 0 2006.257.06:39:29.57#ibcon#about to write, iclass 34, count 0 2006.257.06:39:29.57#ibcon#wrote, iclass 34, count 0 2006.257.06:39:29.57#ibcon#about to read 3, iclass 34, count 0 2006.257.06:39:29.60#ibcon#read 3, iclass 34, count 0 2006.257.06:39:29.60#ibcon#about to read 4, iclass 34, count 0 2006.257.06:39:29.60#ibcon#read 4, iclass 34, count 0 2006.257.06:39:29.60#ibcon#about to read 5, iclass 34, count 0 2006.257.06:39:29.60#ibcon#read 5, iclass 34, count 0 2006.257.06:39:29.60#ibcon#about to read 6, iclass 34, count 0 2006.257.06:39:29.60#ibcon#read 6, iclass 34, count 0 2006.257.06:39:29.60#ibcon#end of sib2, iclass 34, count 0 2006.257.06:39:29.60#ibcon#*after write, iclass 34, count 0 2006.257.06:39:29.60#ibcon#*before return 0, iclass 34, count 0 2006.257.06:39:29.60#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:39:29.60#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:39:29.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:39:29.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:39:29.61$vck44/valo=2,534.99 2006.257.06:39:29.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.06:39:29.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.06:39:29.61#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:29.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:29.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:29.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:29.61#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:39:29.61#ibcon#first serial, iclass 36, count 0 2006.257.06:39:29.61#ibcon#enter sib2, iclass 36, count 0 2006.257.06:39:29.61#ibcon#flushed, iclass 36, count 0 2006.257.06:39:29.61#ibcon#about to write, iclass 36, count 0 2006.257.06:39:29.61#ibcon#wrote, iclass 36, count 0 2006.257.06:39:29.61#ibcon#about to read 3, iclass 36, count 0 2006.257.06:39:29.62#ibcon#read 3, iclass 36, count 0 2006.257.06:39:29.62#ibcon#about to read 4, iclass 36, count 0 2006.257.06:39:29.62#ibcon#read 4, iclass 36, count 0 2006.257.06:39:29.62#ibcon#about to read 5, iclass 36, count 0 2006.257.06:39:29.62#ibcon#read 5, iclass 36, count 0 2006.257.06:39:29.62#ibcon#about to read 6, iclass 36, count 0 2006.257.06:39:29.62#ibcon#read 6, iclass 36, count 0 2006.257.06:39:29.62#ibcon#end of sib2, iclass 36, count 0 2006.257.06:39:29.62#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:39:29.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:39:29.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:39:29.62#ibcon#*before write, iclass 36, count 0 2006.257.06:39:29.62#ibcon#enter sib2, iclass 36, count 0 2006.257.06:39:29.62#ibcon#flushed, iclass 36, count 0 2006.257.06:39:29.62#ibcon#about to write, iclass 36, count 0 2006.257.06:39:29.62#ibcon#wrote, iclass 36, count 0 2006.257.06:39:29.62#ibcon#about to read 3, iclass 36, count 0 2006.257.06:39:29.66#ibcon#read 3, iclass 36, count 0 2006.257.06:39:29.66#ibcon#about to read 4, iclass 36, count 0 2006.257.06:39:29.66#ibcon#read 4, iclass 36, count 0 2006.257.06:39:29.66#ibcon#about to read 5, iclass 36, count 0 2006.257.06:39:29.66#ibcon#read 5, iclass 36, count 0 2006.257.06:39:29.66#ibcon#about to read 6, iclass 36, count 0 2006.257.06:39:29.66#ibcon#read 6, iclass 36, count 0 2006.257.06:39:29.66#ibcon#end of sib2, iclass 36, count 0 2006.257.06:39:29.66#ibcon#*after write, iclass 36, count 0 2006.257.06:39:29.66#ibcon#*before return 0, iclass 36, count 0 2006.257.06:39:29.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:29.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:29.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:39:29.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:39:29.67$vck44/va=2,7 2006.257.06:39:29.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.06:39:29.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.06:39:29.67#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:29.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:29.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:29.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:29.71#ibcon#enter wrdev, iclass 38, count 2 2006.257.06:39:29.71#ibcon#first serial, iclass 38, count 2 2006.257.06:39:29.71#ibcon#enter sib2, iclass 38, count 2 2006.257.06:39:29.71#ibcon#flushed, iclass 38, count 2 2006.257.06:39:29.71#ibcon#about to write, iclass 38, count 2 2006.257.06:39:29.71#ibcon#wrote, iclass 38, count 2 2006.257.06:39:29.71#ibcon#about to read 3, iclass 38, count 2 2006.257.06:39:29.73#ibcon#read 3, iclass 38, count 2 2006.257.06:39:29.73#ibcon#about to read 4, iclass 38, count 2 2006.257.06:39:29.73#ibcon#read 4, iclass 38, count 2 2006.257.06:39:29.73#ibcon#about to read 5, iclass 38, count 2 2006.257.06:39:29.73#ibcon#read 5, iclass 38, count 2 2006.257.06:39:29.73#ibcon#about to read 6, iclass 38, count 2 2006.257.06:39:29.73#ibcon#read 6, iclass 38, count 2 2006.257.06:39:29.73#ibcon#end of sib2, iclass 38, count 2 2006.257.06:39:29.73#ibcon#*mode == 0, iclass 38, count 2 2006.257.06:39:29.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.06:39:29.73#ibcon#[25=AT02-07\r\n] 2006.257.06:39:29.73#ibcon#*before write, iclass 38, count 2 2006.257.06:39:29.73#ibcon#enter sib2, iclass 38, count 2 2006.257.06:39:29.73#ibcon#flushed, iclass 38, count 2 2006.257.06:39:29.73#ibcon#about to write, iclass 38, count 2 2006.257.06:39:29.73#ibcon#wrote, iclass 38, count 2 2006.257.06:39:29.73#ibcon#about to read 3, iclass 38, count 2 2006.257.06:39:29.76#ibcon#read 3, iclass 38, count 2 2006.257.06:39:29.76#ibcon#about to read 4, iclass 38, count 2 2006.257.06:39:29.76#ibcon#read 4, iclass 38, count 2 2006.257.06:39:29.76#ibcon#about to read 5, iclass 38, count 2 2006.257.06:39:29.76#ibcon#read 5, iclass 38, count 2 2006.257.06:39:29.76#ibcon#about to read 6, iclass 38, count 2 2006.257.06:39:29.76#ibcon#read 6, iclass 38, count 2 2006.257.06:39:29.76#ibcon#end of sib2, iclass 38, count 2 2006.257.06:39:29.76#ibcon#*after write, iclass 38, count 2 2006.257.06:39:29.76#ibcon#*before return 0, iclass 38, count 2 2006.257.06:39:29.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:29.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:29.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.06:39:29.76#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:29.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:29.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:29.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:29.88#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:39:29.88#ibcon#first serial, iclass 38, count 0 2006.257.06:39:29.88#ibcon#enter sib2, iclass 38, count 0 2006.257.06:39:29.88#ibcon#flushed, iclass 38, count 0 2006.257.06:39:29.88#ibcon#about to write, iclass 38, count 0 2006.257.06:39:29.88#ibcon#wrote, iclass 38, count 0 2006.257.06:39:29.88#ibcon#about to read 3, iclass 38, count 0 2006.257.06:39:29.90#ibcon#read 3, iclass 38, count 0 2006.257.06:39:29.90#ibcon#about to read 4, iclass 38, count 0 2006.257.06:39:29.90#ibcon#read 4, iclass 38, count 0 2006.257.06:39:29.90#ibcon#about to read 5, iclass 38, count 0 2006.257.06:39:29.90#ibcon#read 5, iclass 38, count 0 2006.257.06:39:29.90#ibcon#about to read 6, iclass 38, count 0 2006.257.06:39:29.90#ibcon#read 6, iclass 38, count 0 2006.257.06:39:29.90#ibcon#end of sib2, iclass 38, count 0 2006.257.06:39:29.90#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:39:29.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:39:29.90#ibcon#[25=USB\r\n] 2006.257.06:39:29.90#ibcon#*before write, iclass 38, count 0 2006.257.06:39:29.90#ibcon#enter sib2, iclass 38, count 0 2006.257.06:39:29.90#ibcon#flushed, iclass 38, count 0 2006.257.06:39:29.90#ibcon#about to write, iclass 38, count 0 2006.257.06:39:29.90#ibcon#wrote, iclass 38, count 0 2006.257.06:39:29.90#ibcon#about to read 3, iclass 38, count 0 2006.257.06:39:29.93#ibcon#read 3, iclass 38, count 0 2006.257.06:39:29.93#ibcon#about to read 4, iclass 38, count 0 2006.257.06:39:29.93#ibcon#read 4, iclass 38, count 0 2006.257.06:39:29.93#ibcon#about to read 5, iclass 38, count 0 2006.257.06:39:29.93#ibcon#read 5, iclass 38, count 0 2006.257.06:39:29.93#ibcon#about to read 6, iclass 38, count 0 2006.257.06:39:29.93#ibcon#read 6, iclass 38, count 0 2006.257.06:39:29.93#ibcon#end of sib2, iclass 38, count 0 2006.257.06:39:29.93#ibcon#*after write, iclass 38, count 0 2006.257.06:39:29.93#ibcon#*before return 0, iclass 38, count 0 2006.257.06:39:29.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:29.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:29.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:39:29.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:39:29.94$vck44/valo=3,564.99 2006.257.06:39:29.94#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.06:39:29.94#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.06:39:29.94#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:29.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:29.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:29.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:29.94#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:39:29.94#ibcon#first serial, iclass 40, count 0 2006.257.06:39:29.94#ibcon#enter sib2, iclass 40, count 0 2006.257.06:39:29.94#ibcon#flushed, iclass 40, count 0 2006.257.06:39:29.94#ibcon#about to write, iclass 40, count 0 2006.257.06:39:29.94#ibcon#wrote, iclass 40, count 0 2006.257.06:39:29.94#ibcon#about to read 3, iclass 40, count 0 2006.257.06:39:29.95#ibcon#read 3, iclass 40, count 0 2006.257.06:39:29.95#ibcon#about to read 4, iclass 40, count 0 2006.257.06:39:29.95#ibcon#read 4, iclass 40, count 0 2006.257.06:39:29.95#ibcon#about to read 5, iclass 40, count 0 2006.257.06:39:29.95#ibcon#read 5, iclass 40, count 0 2006.257.06:39:29.95#ibcon#about to read 6, iclass 40, count 0 2006.257.06:39:29.95#ibcon#read 6, iclass 40, count 0 2006.257.06:39:29.95#ibcon#end of sib2, iclass 40, count 0 2006.257.06:39:29.95#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:39:29.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:39:29.95#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:39:29.95#ibcon#*before write, iclass 40, count 0 2006.257.06:39:29.95#ibcon#enter sib2, iclass 40, count 0 2006.257.06:39:29.95#ibcon#flushed, iclass 40, count 0 2006.257.06:39:29.95#ibcon#about to write, iclass 40, count 0 2006.257.06:39:29.95#ibcon#wrote, iclass 40, count 0 2006.257.06:39:29.95#ibcon#about to read 3, iclass 40, count 0 2006.257.06:39:29.99#ibcon#read 3, iclass 40, count 0 2006.257.06:39:29.99#ibcon#about to read 4, iclass 40, count 0 2006.257.06:39:29.99#ibcon#read 4, iclass 40, count 0 2006.257.06:39:29.99#ibcon#about to read 5, iclass 40, count 0 2006.257.06:39:29.99#ibcon#read 5, iclass 40, count 0 2006.257.06:39:29.99#ibcon#about to read 6, iclass 40, count 0 2006.257.06:39:29.99#ibcon#read 6, iclass 40, count 0 2006.257.06:39:29.99#ibcon#end of sib2, iclass 40, count 0 2006.257.06:39:29.99#ibcon#*after write, iclass 40, count 0 2006.257.06:39:29.99#ibcon#*before return 0, iclass 40, count 0 2006.257.06:39:29.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:29.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:29.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:39:29.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:39:30.00$vck44/va=3,8 2006.257.06:39:30.00#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.06:39:30.00#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.06:39:30.00#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:30.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:30.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:30.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:30.04#ibcon#enter wrdev, iclass 4, count 2 2006.257.06:39:30.04#ibcon#first serial, iclass 4, count 2 2006.257.06:39:30.04#ibcon#enter sib2, iclass 4, count 2 2006.257.06:39:30.04#ibcon#flushed, iclass 4, count 2 2006.257.06:39:30.04#ibcon#about to write, iclass 4, count 2 2006.257.06:39:30.04#ibcon#wrote, iclass 4, count 2 2006.257.06:39:30.04#ibcon#about to read 3, iclass 4, count 2 2006.257.06:39:30.06#ibcon#read 3, iclass 4, count 2 2006.257.06:39:30.06#ibcon#about to read 4, iclass 4, count 2 2006.257.06:39:30.06#ibcon#read 4, iclass 4, count 2 2006.257.06:39:30.06#ibcon#about to read 5, iclass 4, count 2 2006.257.06:39:30.06#ibcon#read 5, iclass 4, count 2 2006.257.06:39:30.06#ibcon#about to read 6, iclass 4, count 2 2006.257.06:39:30.06#ibcon#read 6, iclass 4, count 2 2006.257.06:39:30.06#ibcon#end of sib2, iclass 4, count 2 2006.257.06:39:30.06#ibcon#*mode == 0, iclass 4, count 2 2006.257.06:39:30.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.06:39:30.06#ibcon#[25=AT03-08\r\n] 2006.257.06:39:30.06#ibcon#*before write, iclass 4, count 2 2006.257.06:39:30.06#ibcon#enter sib2, iclass 4, count 2 2006.257.06:39:30.06#ibcon#flushed, iclass 4, count 2 2006.257.06:39:30.06#ibcon#about to write, iclass 4, count 2 2006.257.06:39:30.06#ibcon#wrote, iclass 4, count 2 2006.257.06:39:30.06#ibcon#about to read 3, iclass 4, count 2 2006.257.06:39:30.09#ibcon#read 3, iclass 4, count 2 2006.257.06:39:30.09#ibcon#about to read 4, iclass 4, count 2 2006.257.06:39:30.09#ibcon#read 4, iclass 4, count 2 2006.257.06:39:30.09#ibcon#about to read 5, iclass 4, count 2 2006.257.06:39:30.09#ibcon#read 5, iclass 4, count 2 2006.257.06:39:30.09#ibcon#about to read 6, iclass 4, count 2 2006.257.06:39:30.09#ibcon#read 6, iclass 4, count 2 2006.257.06:39:30.09#ibcon#end of sib2, iclass 4, count 2 2006.257.06:39:30.09#ibcon#*after write, iclass 4, count 2 2006.257.06:39:30.09#ibcon#*before return 0, iclass 4, count 2 2006.257.06:39:30.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:30.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:30.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.06:39:30.09#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:30.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:30.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:30.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:30.21#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:39:30.21#ibcon#first serial, iclass 4, count 0 2006.257.06:39:30.21#ibcon#enter sib2, iclass 4, count 0 2006.257.06:39:30.21#ibcon#flushed, iclass 4, count 0 2006.257.06:39:30.21#ibcon#about to write, iclass 4, count 0 2006.257.06:39:30.21#ibcon#wrote, iclass 4, count 0 2006.257.06:39:30.21#ibcon#about to read 3, iclass 4, count 0 2006.257.06:39:30.23#ibcon#read 3, iclass 4, count 0 2006.257.06:39:30.23#ibcon#about to read 4, iclass 4, count 0 2006.257.06:39:30.23#ibcon#read 4, iclass 4, count 0 2006.257.06:39:30.23#ibcon#about to read 5, iclass 4, count 0 2006.257.06:39:30.23#ibcon#read 5, iclass 4, count 0 2006.257.06:39:30.23#ibcon#about to read 6, iclass 4, count 0 2006.257.06:39:30.23#ibcon#read 6, iclass 4, count 0 2006.257.06:39:30.23#ibcon#end of sib2, iclass 4, count 0 2006.257.06:39:30.23#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:39:30.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:39:30.23#ibcon#[25=USB\r\n] 2006.257.06:39:30.23#ibcon#*before write, iclass 4, count 0 2006.257.06:39:30.23#ibcon#enter sib2, iclass 4, count 0 2006.257.06:39:30.23#ibcon#flushed, iclass 4, count 0 2006.257.06:39:30.23#ibcon#about to write, iclass 4, count 0 2006.257.06:39:30.23#ibcon#wrote, iclass 4, count 0 2006.257.06:39:30.23#ibcon#about to read 3, iclass 4, count 0 2006.257.06:39:30.26#ibcon#read 3, iclass 4, count 0 2006.257.06:39:30.26#ibcon#about to read 4, iclass 4, count 0 2006.257.06:39:30.26#ibcon#read 4, iclass 4, count 0 2006.257.06:39:30.26#ibcon#about to read 5, iclass 4, count 0 2006.257.06:39:30.26#ibcon#read 5, iclass 4, count 0 2006.257.06:39:30.26#ibcon#about to read 6, iclass 4, count 0 2006.257.06:39:30.26#ibcon#read 6, iclass 4, count 0 2006.257.06:39:30.26#ibcon#end of sib2, iclass 4, count 0 2006.257.06:39:30.26#ibcon#*after write, iclass 4, count 0 2006.257.06:39:30.26#ibcon#*before return 0, iclass 4, count 0 2006.257.06:39:30.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:30.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:30.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:39:30.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:39:30.27$vck44/valo=4,624.99 2006.257.06:39:30.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.06:39:30.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.06:39:30.27#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:30.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:30.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:30.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:30.27#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:39:30.27#ibcon#first serial, iclass 6, count 0 2006.257.06:39:30.27#ibcon#enter sib2, iclass 6, count 0 2006.257.06:39:30.27#ibcon#flushed, iclass 6, count 0 2006.257.06:39:30.27#ibcon#about to write, iclass 6, count 0 2006.257.06:39:30.27#ibcon#wrote, iclass 6, count 0 2006.257.06:39:30.27#ibcon#about to read 3, iclass 6, count 0 2006.257.06:39:30.28#ibcon#read 3, iclass 6, count 0 2006.257.06:39:30.28#ibcon#about to read 4, iclass 6, count 0 2006.257.06:39:30.28#ibcon#read 4, iclass 6, count 0 2006.257.06:39:30.28#ibcon#about to read 5, iclass 6, count 0 2006.257.06:39:30.28#ibcon#read 5, iclass 6, count 0 2006.257.06:39:30.28#ibcon#about to read 6, iclass 6, count 0 2006.257.06:39:30.28#ibcon#read 6, iclass 6, count 0 2006.257.06:39:30.28#ibcon#end of sib2, iclass 6, count 0 2006.257.06:39:30.28#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:39:30.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:39:30.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:39:30.28#ibcon#*before write, iclass 6, count 0 2006.257.06:39:30.28#ibcon#enter sib2, iclass 6, count 0 2006.257.06:39:30.28#ibcon#flushed, iclass 6, count 0 2006.257.06:39:30.28#ibcon#about to write, iclass 6, count 0 2006.257.06:39:30.28#ibcon#wrote, iclass 6, count 0 2006.257.06:39:30.28#ibcon#about to read 3, iclass 6, count 0 2006.257.06:39:30.32#ibcon#read 3, iclass 6, count 0 2006.257.06:39:30.32#ibcon#about to read 4, iclass 6, count 0 2006.257.06:39:30.32#ibcon#read 4, iclass 6, count 0 2006.257.06:39:30.32#ibcon#about to read 5, iclass 6, count 0 2006.257.06:39:30.32#ibcon#read 5, iclass 6, count 0 2006.257.06:39:30.32#ibcon#about to read 6, iclass 6, count 0 2006.257.06:39:30.32#ibcon#read 6, iclass 6, count 0 2006.257.06:39:30.32#ibcon#end of sib2, iclass 6, count 0 2006.257.06:39:30.32#ibcon#*after write, iclass 6, count 0 2006.257.06:39:30.32#ibcon#*before return 0, iclass 6, count 0 2006.257.06:39:30.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:30.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:30.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:39:30.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:39:30.33$vck44/va=4,7 2006.257.06:39:30.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.06:39:30.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.06:39:30.33#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:30.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:30.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:30.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:30.37#ibcon#enter wrdev, iclass 10, count 2 2006.257.06:39:30.37#ibcon#first serial, iclass 10, count 2 2006.257.06:39:30.37#ibcon#enter sib2, iclass 10, count 2 2006.257.06:39:30.37#ibcon#flushed, iclass 10, count 2 2006.257.06:39:30.37#ibcon#about to write, iclass 10, count 2 2006.257.06:39:30.37#ibcon#wrote, iclass 10, count 2 2006.257.06:39:30.37#ibcon#about to read 3, iclass 10, count 2 2006.257.06:39:30.39#ibcon#read 3, iclass 10, count 2 2006.257.06:39:30.39#ibcon#about to read 4, iclass 10, count 2 2006.257.06:39:30.39#ibcon#read 4, iclass 10, count 2 2006.257.06:39:30.39#ibcon#about to read 5, iclass 10, count 2 2006.257.06:39:30.39#ibcon#read 5, iclass 10, count 2 2006.257.06:39:30.39#ibcon#about to read 6, iclass 10, count 2 2006.257.06:39:30.39#ibcon#read 6, iclass 10, count 2 2006.257.06:39:30.39#ibcon#end of sib2, iclass 10, count 2 2006.257.06:39:30.39#ibcon#*mode == 0, iclass 10, count 2 2006.257.06:39:30.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.06:39:30.39#ibcon#[25=AT04-07\r\n] 2006.257.06:39:30.39#ibcon#*before write, iclass 10, count 2 2006.257.06:39:30.39#ibcon#enter sib2, iclass 10, count 2 2006.257.06:39:30.39#ibcon#flushed, iclass 10, count 2 2006.257.06:39:30.39#ibcon#about to write, iclass 10, count 2 2006.257.06:39:30.39#ibcon#wrote, iclass 10, count 2 2006.257.06:39:30.39#ibcon#about to read 3, iclass 10, count 2 2006.257.06:39:30.42#ibcon#read 3, iclass 10, count 2 2006.257.06:39:30.42#ibcon#about to read 4, iclass 10, count 2 2006.257.06:39:30.42#ibcon#read 4, iclass 10, count 2 2006.257.06:39:30.42#ibcon#about to read 5, iclass 10, count 2 2006.257.06:39:30.42#ibcon#read 5, iclass 10, count 2 2006.257.06:39:30.42#ibcon#about to read 6, iclass 10, count 2 2006.257.06:39:30.42#ibcon#read 6, iclass 10, count 2 2006.257.06:39:30.42#ibcon#end of sib2, iclass 10, count 2 2006.257.06:39:30.42#ibcon#*after write, iclass 10, count 2 2006.257.06:39:30.42#ibcon#*before return 0, iclass 10, count 2 2006.257.06:39:30.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:30.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:30.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.06:39:30.42#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:30.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:30.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:30.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:30.54#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:39:30.54#ibcon#first serial, iclass 10, count 0 2006.257.06:39:30.54#ibcon#enter sib2, iclass 10, count 0 2006.257.06:39:30.54#ibcon#flushed, iclass 10, count 0 2006.257.06:39:30.54#ibcon#about to write, iclass 10, count 0 2006.257.06:39:30.54#ibcon#wrote, iclass 10, count 0 2006.257.06:39:30.54#ibcon#about to read 3, iclass 10, count 0 2006.257.06:39:30.56#ibcon#read 3, iclass 10, count 0 2006.257.06:39:30.56#ibcon#about to read 4, iclass 10, count 0 2006.257.06:39:30.56#ibcon#read 4, iclass 10, count 0 2006.257.06:39:30.56#ibcon#about to read 5, iclass 10, count 0 2006.257.06:39:30.56#ibcon#read 5, iclass 10, count 0 2006.257.06:39:30.56#ibcon#about to read 6, iclass 10, count 0 2006.257.06:39:30.56#ibcon#read 6, iclass 10, count 0 2006.257.06:39:30.56#ibcon#end of sib2, iclass 10, count 0 2006.257.06:39:30.56#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:39:30.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:39:30.56#ibcon#[25=USB\r\n] 2006.257.06:39:30.56#ibcon#*before write, iclass 10, count 0 2006.257.06:39:30.56#ibcon#enter sib2, iclass 10, count 0 2006.257.06:39:30.56#ibcon#flushed, iclass 10, count 0 2006.257.06:39:30.56#ibcon#about to write, iclass 10, count 0 2006.257.06:39:30.56#ibcon#wrote, iclass 10, count 0 2006.257.06:39:30.56#ibcon#about to read 3, iclass 10, count 0 2006.257.06:39:30.59#ibcon#read 3, iclass 10, count 0 2006.257.06:39:30.59#ibcon#about to read 4, iclass 10, count 0 2006.257.06:39:30.59#ibcon#read 4, iclass 10, count 0 2006.257.06:39:30.59#ibcon#about to read 5, iclass 10, count 0 2006.257.06:39:30.59#ibcon#read 5, iclass 10, count 0 2006.257.06:39:30.59#ibcon#about to read 6, iclass 10, count 0 2006.257.06:39:30.59#ibcon#read 6, iclass 10, count 0 2006.257.06:39:30.59#ibcon#end of sib2, iclass 10, count 0 2006.257.06:39:30.59#ibcon#*after write, iclass 10, count 0 2006.257.06:39:30.59#ibcon#*before return 0, iclass 10, count 0 2006.257.06:39:30.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:30.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:30.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:39:30.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:39:30.60$vck44/valo=5,734.99 2006.257.06:39:30.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.06:39:30.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.06:39:30.60#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:30.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:30.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:30.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:30.60#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:39:30.60#ibcon#first serial, iclass 12, count 0 2006.257.06:39:30.60#ibcon#enter sib2, iclass 12, count 0 2006.257.06:39:30.60#ibcon#flushed, iclass 12, count 0 2006.257.06:39:30.60#ibcon#about to write, iclass 12, count 0 2006.257.06:39:30.60#ibcon#wrote, iclass 12, count 0 2006.257.06:39:30.60#ibcon#about to read 3, iclass 12, count 0 2006.257.06:39:30.61#ibcon#read 3, iclass 12, count 0 2006.257.06:39:30.61#ibcon#about to read 4, iclass 12, count 0 2006.257.06:39:30.61#ibcon#read 4, iclass 12, count 0 2006.257.06:39:30.61#ibcon#about to read 5, iclass 12, count 0 2006.257.06:39:30.61#ibcon#read 5, iclass 12, count 0 2006.257.06:39:30.61#ibcon#about to read 6, iclass 12, count 0 2006.257.06:39:30.61#ibcon#read 6, iclass 12, count 0 2006.257.06:39:30.61#ibcon#end of sib2, iclass 12, count 0 2006.257.06:39:30.61#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:39:30.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:39:30.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:39:30.61#ibcon#*before write, iclass 12, count 0 2006.257.06:39:30.61#ibcon#enter sib2, iclass 12, count 0 2006.257.06:39:30.61#ibcon#flushed, iclass 12, count 0 2006.257.06:39:30.61#ibcon#about to write, iclass 12, count 0 2006.257.06:39:30.61#ibcon#wrote, iclass 12, count 0 2006.257.06:39:30.61#ibcon#about to read 3, iclass 12, count 0 2006.257.06:39:30.65#ibcon#read 3, iclass 12, count 0 2006.257.06:39:30.65#ibcon#about to read 4, iclass 12, count 0 2006.257.06:39:30.65#ibcon#read 4, iclass 12, count 0 2006.257.06:39:30.65#ibcon#about to read 5, iclass 12, count 0 2006.257.06:39:30.65#ibcon#read 5, iclass 12, count 0 2006.257.06:39:30.65#ibcon#about to read 6, iclass 12, count 0 2006.257.06:39:30.65#ibcon#read 6, iclass 12, count 0 2006.257.06:39:30.65#ibcon#end of sib2, iclass 12, count 0 2006.257.06:39:30.65#ibcon#*after write, iclass 12, count 0 2006.257.06:39:30.65#ibcon#*before return 0, iclass 12, count 0 2006.257.06:39:30.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:30.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:30.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:39:30.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:39:30.66$vck44/va=5,4 2006.257.06:39:30.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.06:39:30.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.06:39:30.66#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:30.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:30.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:30.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:30.70#ibcon#enter wrdev, iclass 14, count 2 2006.257.06:39:30.70#ibcon#first serial, iclass 14, count 2 2006.257.06:39:30.70#ibcon#enter sib2, iclass 14, count 2 2006.257.06:39:30.70#ibcon#flushed, iclass 14, count 2 2006.257.06:39:30.70#ibcon#about to write, iclass 14, count 2 2006.257.06:39:30.70#ibcon#wrote, iclass 14, count 2 2006.257.06:39:30.70#ibcon#about to read 3, iclass 14, count 2 2006.257.06:39:30.72#ibcon#read 3, iclass 14, count 2 2006.257.06:39:30.72#ibcon#about to read 4, iclass 14, count 2 2006.257.06:39:30.72#ibcon#read 4, iclass 14, count 2 2006.257.06:39:30.72#ibcon#about to read 5, iclass 14, count 2 2006.257.06:39:30.72#ibcon#read 5, iclass 14, count 2 2006.257.06:39:30.72#ibcon#about to read 6, iclass 14, count 2 2006.257.06:39:30.72#ibcon#read 6, iclass 14, count 2 2006.257.06:39:30.72#ibcon#end of sib2, iclass 14, count 2 2006.257.06:39:30.72#ibcon#*mode == 0, iclass 14, count 2 2006.257.06:39:30.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.06:39:30.72#ibcon#[25=AT05-04\r\n] 2006.257.06:39:30.72#ibcon#*before write, iclass 14, count 2 2006.257.06:39:30.72#ibcon#enter sib2, iclass 14, count 2 2006.257.06:39:30.72#ibcon#flushed, iclass 14, count 2 2006.257.06:39:30.72#ibcon#about to write, iclass 14, count 2 2006.257.06:39:30.72#ibcon#wrote, iclass 14, count 2 2006.257.06:39:30.72#ibcon#about to read 3, iclass 14, count 2 2006.257.06:39:30.75#ibcon#read 3, iclass 14, count 2 2006.257.06:39:30.75#ibcon#about to read 4, iclass 14, count 2 2006.257.06:39:30.75#ibcon#read 4, iclass 14, count 2 2006.257.06:39:30.75#ibcon#about to read 5, iclass 14, count 2 2006.257.06:39:30.75#ibcon#read 5, iclass 14, count 2 2006.257.06:39:30.75#ibcon#about to read 6, iclass 14, count 2 2006.257.06:39:30.75#ibcon#read 6, iclass 14, count 2 2006.257.06:39:30.75#ibcon#end of sib2, iclass 14, count 2 2006.257.06:39:30.75#ibcon#*after write, iclass 14, count 2 2006.257.06:39:30.75#ibcon#*before return 0, iclass 14, count 2 2006.257.06:39:30.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:30.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:30.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.06:39:30.75#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:30.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:30.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:30.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:30.87#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:39:30.87#ibcon#first serial, iclass 14, count 0 2006.257.06:39:30.87#ibcon#enter sib2, iclass 14, count 0 2006.257.06:39:30.87#ibcon#flushed, iclass 14, count 0 2006.257.06:39:30.87#ibcon#about to write, iclass 14, count 0 2006.257.06:39:30.87#ibcon#wrote, iclass 14, count 0 2006.257.06:39:30.87#ibcon#about to read 3, iclass 14, count 0 2006.257.06:39:30.89#ibcon#read 3, iclass 14, count 0 2006.257.06:39:30.89#ibcon#about to read 4, iclass 14, count 0 2006.257.06:39:30.89#ibcon#read 4, iclass 14, count 0 2006.257.06:39:30.89#ibcon#about to read 5, iclass 14, count 0 2006.257.06:39:30.89#ibcon#read 5, iclass 14, count 0 2006.257.06:39:30.89#ibcon#about to read 6, iclass 14, count 0 2006.257.06:39:30.89#ibcon#read 6, iclass 14, count 0 2006.257.06:39:30.89#ibcon#end of sib2, iclass 14, count 0 2006.257.06:39:30.89#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:39:30.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:39:30.89#ibcon#[25=USB\r\n] 2006.257.06:39:30.89#ibcon#*before write, iclass 14, count 0 2006.257.06:39:30.89#ibcon#enter sib2, iclass 14, count 0 2006.257.06:39:30.89#ibcon#flushed, iclass 14, count 0 2006.257.06:39:30.89#ibcon#about to write, iclass 14, count 0 2006.257.06:39:30.89#ibcon#wrote, iclass 14, count 0 2006.257.06:39:30.89#ibcon#about to read 3, iclass 14, count 0 2006.257.06:39:30.92#ibcon#read 3, iclass 14, count 0 2006.257.06:39:30.92#ibcon#about to read 4, iclass 14, count 0 2006.257.06:39:30.92#ibcon#read 4, iclass 14, count 0 2006.257.06:39:30.92#ibcon#about to read 5, iclass 14, count 0 2006.257.06:39:30.92#ibcon#read 5, iclass 14, count 0 2006.257.06:39:30.92#ibcon#about to read 6, iclass 14, count 0 2006.257.06:39:30.92#ibcon#read 6, iclass 14, count 0 2006.257.06:39:30.92#ibcon#end of sib2, iclass 14, count 0 2006.257.06:39:30.92#ibcon#*after write, iclass 14, count 0 2006.257.06:39:30.92#ibcon#*before return 0, iclass 14, count 0 2006.257.06:39:30.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:30.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:30.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:39:30.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:39:30.93$vck44/valo=6,814.99 2006.257.06:39:30.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.06:39:30.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.06:39:30.93#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:30.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:30.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:30.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:30.93#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:39:30.93#ibcon#first serial, iclass 16, count 0 2006.257.06:39:30.93#ibcon#enter sib2, iclass 16, count 0 2006.257.06:39:30.93#ibcon#flushed, iclass 16, count 0 2006.257.06:39:30.93#ibcon#about to write, iclass 16, count 0 2006.257.06:39:30.93#ibcon#wrote, iclass 16, count 0 2006.257.06:39:30.93#ibcon#about to read 3, iclass 16, count 0 2006.257.06:39:30.94#ibcon#read 3, iclass 16, count 0 2006.257.06:39:30.94#ibcon#about to read 4, iclass 16, count 0 2006.257.06:39:30.94#ibcon#read 4, iclass 16, count 0 2006.257.06:39:30.94#ibcon#about to read 5, iclass 16, count 0 2006.257.06:39:30.94#ibcon#read 5, iclass 16, count 0 2006.257.06:39:30.94#ibcon#about to read 6, iclass 16, count 0 2006.257.06:39:30.94#ibcon#read 6, iclass 16, count 0 2006.257.06:39:30.94#ibcon#end of sib2, iclass 16, count 0 2006.257.06:39:30.94#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:39:30.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:39:30.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:39:30.94#ibcon#*before write, iclass 16, count 0 2006.257.06:39:30.94#ibcon#enter sib2, iclass 16, count 0 2006.257.06:39:30.94#ibcon#flushed, iclass 16, count 0 2006.257.06:39:30.94#ibcon#about to write, iclass 16, count 0 2006.257.06:39:30.94#ibcon#wrote, iclass 16, count 0 2006.257.06:39:30.94#ibcon#about to read 3, iclass 16, count 0 2006.257.06:39:30.98#ibcon#read 3, iclass 16, count 0 2006.257.06:39:30.98#ibcon#about to read 4, iclass 16, count 0 2006.257.06:39:30.98#ibcon#read 4, iclass 16, count 0 2006.257.06:39:30.98#ibcon#about to read 5, iclass 16, count 0 2006.257.06:39:30.98#ibcon#read 5, iclass 16, count 0 2006.257.06:39:30.98#ibcon#about to read 6, iclass 16, count 0 2006.257.06:39:30.98#ibcon#read 6, iclass 16, count 0 2006.257.06:39:30.98#ibcon#end of sib2, iclass 16, count 0 2006.257.06:39:30.98#ibcon#*after write, iclass 16, count 0 2006.257.06:39:30.98#ibcon#*before return 0, iclass 16, count 0 2006.257.06:39:30.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:30.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:30.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:39:30.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:39:30.99$vck44/va=6,4 2006.257.06:39:30.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.06:39:30.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.06:39:30.99#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:30.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:31.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:31.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:31.03#ibcon#enter wrdev, iclass 18, count 2 2006.257.06:39:31.03#ibcon#first serial, iclass 18, count 2 2006.257.06:39:31.03#ibcon#enter sib2, iclass 18, count 2 2006.257.06:39:31.03#ibcon#flushed, iclass 18, count 2 2006.257.06:39:31.03#ibcon#about to write, iclass 18, count 2 2006.257.06:39:31.03#ibcon#wrote, iclass 18, count 2 2006.257.06:39:31.03#ibcon#about to read 3, iclass 18, count 2 2006.257.06:39:31.05#ibcon#read 3, iclass 18, count 2 2006.257.06:39:31.05#ibcon#about to read 4, iclass 18, count 2 2006.257.06:39:31.05#ibcon#read 4, iclass 18, count 2 2006.257.06:39:31.05#ibcon#about to read 5, iclass 18, count 2 2006.257.06:39:31.05#ibcon#read 5, iclass 18, count 2 2006.257.06:39:31.05#ibcon#about to read 6, iclass 18, count 2 2006.257.06:39:31.05#ibcon#read 6, iclass 18, count 2 2006.257.06:39:31.05#ibcon#end of sib2, iclass 18, count 2 2006.257.06:39:31.05#ibcon#*mode == 0, iclass 18, count 2 2006.257.06:39:31.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.06:39:31.05#ibcon#[25=AT06-04\r\n] 2006.257.06:39:31.05#ibcon#*before write, iclass 18, count 2 2006.257.06:39:31.05#ibcon#enter sib2, iclass 18, count 2 2006.257.06:39:31.05#ibcon#flushed, iclass 18, count 2 2006.257.06:39:31.05#ibcon#about to write, iclass 18, count 2 2006.257.06:39:31.05#ibcon#wrote, iclass 18, count 2 2006.257.06:39:31.05#ibcon#about to read 3, iclass 18, count 2 2006.257.06:39:31.08#ibcon#read 3, iclass 18, count 2 2006.257.06:39:31.08#ibcon#about to read 4, iclass 18, count 2 2006.257.06:39:31.08#ibcon#read 4, iclass 18, count 2 2006.257.06:39:31.08#ibcon#about to read 5, iclass 18, count 2 2006.257.06:39:31.08#ibcon#read 5, iclass 18, count 2 2006.257.06:39:31.08#ibcon#about to read 6, iclass 18, count 2 2006.257.06:39:31.08#ibcon#read 6, iclass 18, count 2 2006.257.06:39:31.08#ibcon#end of sib2, iclass 18, count 2 2006.257.06:39:31.08#ibcon#*after write, iclass 18, count 2 2006.257.06:39:31.08#ibcon#*before return 0, iclass 18, count 2 2006.257.06:39:31.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:31.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:31.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.06:39:31.08#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:31.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:31.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:31.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:31.20#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:39:31.20#ibcon#first serial, iclass 18, count 0 2006.257.06:39:31.20#ibcon#enter sib2, iclass 18, count 0 2006.257.06:39:31.20#ibcon#flushed, iclass 18, count 0 2006.257.06:39:31.20#ibcon#about to write, iclass 18, count 0 2006.257.06:39:31.20#ibcon#wrote, iclass 18, count 0 2006.257.06:39:31.20#ibcon#about to read 3, iclass 18, count 0 2006.257.06:39:31.22#ibcon#read 3, iclass 18, count 0 2006.257.06:39:31.22#ibcon#about to read 4, iclass 18, count 0 2006.257.06:39:31.22#ibcon#read 4, iclass 18, count 0 2006.257.06:39:31.22#ibcon#about to read 5, iclass 18, count 0 2006.257.06:39:31.22#ibcon#read 5, iclass 18, count 0 2006.257.06:39:31.22#ibcon#about to read 6, iclass 18, count 0 2006.257.06:39:31.22#ibcon#read 6, iclass 18, count 0 2006.257.06:39:31.22#ibcon#end of sib2, iclass 18, count 0 2006.257.06:39:31.22#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:39:31.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:39:31.22#ibcon#[25=USB\r\n] 2006.257.06:39:31.22#ibcon#*before write, iclass 18, count 0 2006.257.06:39:31.22#ibcon#enter sib2, iclass 18, count 0 2006.257.06:39:31.22#ibcon#flushed, iclass 18, count 0 2006.257.06:39:31.22#ibcon#about to write, iclass 18, count 0 2006.257.06:39:31.22#ibcon#wrote, iclass 18, count 0 2006.257.06:39:31.22#ibcon#about to read 3, iclass 18, count 0 2006.257.06:39:31.25#ibcon#read 3, iclass 18, count 0 2006.257.06:39:31.25#ibcon#about to read 4, iclass 18, count 0 2006.257.06:39:31.25#ibcon#read 4, iclass 18, count 0 2006.257.06:39:31.25#ibcon#about to read 5, iclass 18, count 0 2006.257.06:39:31.25#ibcon#read 5, iclass 18, count 0 2006.257.06:39:31.25#ibcon#about to read 6, iclass 18, count 0 2006.257.06:39:31.25#ibcon#read 6, iclass 18, count 0 2006.257.06:39:31.25#ibcon#end of sib2, iclass 18, count 0 2006.257.06:39:31.25#ibcon#*after write, iclass 18, count 0 2006.257.06:39:31.25#ibcon#*before return 0, iclass 18, count 0 2006.257.06:39:31.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:31.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:31.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:39:31.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:39:31.26$vck44/valo=7,864.99 2006.257.06:39:31.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.06:39:31.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.06:39:31.26#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:31.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:31.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:31.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:31.26#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:39:31.26#ibcon#first serial, iclass 20, count 0 2006.257.06:39:31.26#ibcon#enter sib2, iclass 20, count 0 2006.257.06:39:31.26#ibcon#flushed, iclass 20, count 0 2006.257.06:39:31.26#ibcon#about to write, iclass 20, count 0 2006.257.06:39:31.26#ibcon#wrote, iclass 20, count 0 2006.257.06:39:31.26#ibcon#about to read 3, iclass 20, count 0 2006.257.06:39:31.27#ibcon#read 3, iclass 20, count 0 2006.257.06:39:31.27#ibcon#about to read 4, iclass 20, count 0 2006.257.06:39:31.27#ibcon#read 4, iclass 20, count 0 2006.257.06:39:31.27#ibcon#about to read 5, iclass 20, count 0 2006.257.06:39:31.27#ibcon#read 5, iclass 20, count 0 2006.257.06:39:31.27#ibcon#about to read 6, iclass 20, count 0 2006.257.06:39:31.27#ibcon#read 6, iclass 20, count 0 2006.257.06:39:31.27#ibcon#end of sib2, iclass 20, count 0 2006.257.06:39:31.27#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:39:31.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:39:31.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:39:31.27#ibcon#*before write, iclass 20, count 0 2006.257.06:39:31.27#ibcon#enter sib2, iclass 20, count 0 2006.257.06:39:31.27#ibcon#flushed, iclass 20, count 0 2006.257.06:39:31.27#ibcon#about to write, iclass 20, count 0 2006.257.06:39:31.27#ibcon#wrote, iclass 20, count 0 2006.257.06:39:31.27#ibcon#about to read 3, iclass 20, count 0 2006.257.06:39:31.31#ibcon#read 3, iclass 20, count 0 2006.257.06:39:31.31#ibcon#about to read 4, iclass 20, count 0 2006.257.06:39:31.31#ibcon#read 4, iclass 20, count 0 2006.257.06:39:31.31#ibcon#about to read 5, iclass 20, count 0 2006.257.06:39:31.31#ibcon#read 5, iclass 20, count 0 2006.257.06:39:31.31#ibcon#about to read 6, iclass 20, count 0 2006.257.06:39:31.31#ibcon#read 6, iclass 20, count 0 2006.257.06:39:31.31#ibcon#end of sib2, iclass 20, count 0 2006.257.06:39:31.31#ibcon#*after write, iclass 20, count 0 2006.257.06:39:31.31#ibcon#*before return 0, iclass 20, count 0 2006.257.06:39:31.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:31.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:31.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:39:31.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:39:31.32$vck44/va=7,4 2006.257.06:39:31.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.06:39:31.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.06:39:31.32#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:31.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:31.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:31.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:31.36#ibcon#enter wrdev, iclass 22, count 2 2006.257.06:39:31.36#ibcon#first serial, iclass 22, count 2 2006.257.06:39:31.36#ibcon#enter sib2, iclass 22, count 2 2006.257.06:39:31.36#ibcon#flushed, iclass 22, count 2 2006.257.06:39:31.36#ibcon#about to write, iclass 22, count 2 2006.257.06:39:31.36#ibcon#wrote, iclass 22, count 2 2006.257.06:39:31.36#ibcon#about to read 3, iclass 22, count 2 2006.257.06:39:31.38#ibcon#read 3, iclass 22, count 2 2006.257.06:39:31.38#ibcon#about to read 4, iclass 22, count 2 2006.257.06:39:31.38#ibcon#read 4, iclass 22, count 2 2006.257.06:39:31.38#ibcon#about to read 5, iclass 22, count 2 2006.257.06:39:31.38#ibcon#read 5, iclass 22, count 2 2006.257.06:39:31.38#ibcon#about to read 6, iclass 22, count 2 2006.257.06:39:31.38#ibcon#read 6, iclass 22, count 2 2006.257.06:39:31.38#ibcon#end of sib2, iclass 22, count 2 2006.257.06:39:31.38#ibcon#*mode == 0, iclass 22, count 2 2006.257.06:39:31.38#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.06:39:31.38#ibcon#[25=AT07-04\r\n] 2006.257.06:39:31.38#ibcon#*before write, iclass 22, count 2 2006.257.06:39:31.38#ibcon#enter sib2, iclass 22, count 2 2006.257.06:39:31.38#ibcon#flushed, iclass 22, count 2 2006.257.06:39:31.38#ibcon#about to write, iclass 22, count 2 2006.257.06:39:31.38#ibcon#wrote, iclass 22, count 2 2006.257.06:39:31.38#ibcon#about to read 3, iclass 22, count 2 2006.257.06:39:31.41#ibcon#read 3, iclass 22, count 2 2006.257.06:39:31.41#ibcon#about to read 4, iclass 22, count 2 2006.257.06:39:31.41#ibcon#read 4, iclass 22, count 2 2006.257.06:39:31.41#ibcon#about to read 5, iclass 22, count 2 2006.257.06:39:31.41#ibcon#read 5, iclass 22, count 2 2006.257.06:39:31.41#ibcon#about to read 6, iclass 22, count 2 2006.257.06:39:31.41#ibcon#read 6, iclass 22, count 2 2006.257.06:39:31.41#ibcon#end of sib2, iclass 22, count 2 2006.257.06:39:31.41#ibcon#*after write, iclass 22, count 2 2006.257.06:39:31.41#ibcon#*before return 0, iclass 22, count 2 2006.257.06:39:31.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:31.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:31.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.06:39:31.41#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:31.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:31.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:31.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:31.53#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:39:31.53#ibcon#first serial, iclass 22, count 0 2006.257.06:39:31.53#ibcon#enter sib2, iclass 22, count 0 2006.257.06:39:31.53#ibcon#flushed, iclass 22, count 0 2006.257.06:39:31.53#ibcon#about to write, iclass 22, count 0 2006.257.06:39:31.53#ibcon#wrote, iclass 22, count 0 2006.257.06:39:31.53#ibcon#about to read 3, iclass 22, count 0 2006.257.06:39:31.55#ibcon#read 3, iclass 22, count 0 2006.257.06:39:31.55#ibcon#about to read 4, iclass 22, count 0 2006.257.06:39:31.55#ibcon#read 4, iclass 22, count 0 2006.257.06:39:31.55#ibcon#about to read 5, iclass 22, count 0 2006.257.06:39:31.55#ibcon#read 5, iclass 22, count 0 2006.257.06:39:31.55#ibcon#about to read 6, iclass 22, count 0 2006.257.06:39:31.55#ibcon#read 6, iclass 22, count 0 2006.257.06:39:31.55#ibcon#end of sib2, iclass 22, count 0 2006.257.06:39:31.55#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:39:31.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:39:31.55#ibcon#[25=USB\r\n] 2006.257.06:39:31.55#ibcon#*before write, iclass 22, count 0 2006.257.06:39:31.55#ibcon#enter sib2, iclass 22, count 0 2006.257.06:39:31.55#ibcon#flushed, iclass 22, count 0 2006.257.06:39:31.55#ibcon#about to write, iclass 22, count 0 2006.257.06:39:31.55#ibcon#wrote, iclass 22, count 0 2006.257.06:39:31.55#ibcon#about to read 3, iclass 22, count 0 2006.257.06:39:31.58#ibcon#read 3, iclass 22, count 0 2006.257.06:39:31.58#ibcon#about to read 4, iclass 22, count 0 2006.257.06:39:31.58#ibcon#read 4, iclass 22, count 0 2006.257.06:39:31.58#ibcon#about to read 5, iclass 22, count 0 2006.257.06:39:31.58#ibcon#read 5, iclass 22, count 0 2006.257.06:39:31.58#ibcon#about to read 6, iclass 22, count 0 2006.257.06:39:31.58#ibcon#read 6, iclass 22, count 0 2006.257.06:39:31.58#ibcon#end of sib2, iclass 22, count 0 2006.257.06:39:31.58#ibcon#*after write, iclass 22, count 0 2006.257.06:39:31.58#ibcon#*before return 0, iclass 22, count 0 2006.257.06:39:31.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:31.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:31.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:39:31.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:39:31.59$vck44/valo=8,884.99 2006.257.06:39:31.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.06:39:31.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.06:39:31.59#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:31.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:31.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:31.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:31.59#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:39:31.59#ibcon#first serial, iclass 24, count 0 2006.257.06:39:31.59#ibcon#enter sib2, iclass 24, count 0 2006.257.06:39:31.59#ibcon#flushed, iclass 24, count 0 2006.257.06:39:31.59#ibcon#about to write, iclass 24, count 0 2006.257.06:39:31.59#ibcon#wrote, iclass 24, count 0 2006.257.06:39:31.59#ibcon#about to read 3, iclass 24, count 0 2006.257.06:39:31.60#ibcon#read 3, iclass 24, count 0 2006.257.06:39:31.60#ibcon#about to read 4, iclass 24, count 0 2006.257.06:39:31.60#ibcon#read 4, iclass 24, count 0 2006.257.06:39:31.60#ibcon#about to read 5, iclass 24, count 0 2006.257.06:39:31.60#ibcon#read 5, iclass 24, count 0 2006.257.06:39:31.60#ibcon#about to read 6, iclass 24, count 0 2006.257.06:39:31.60#ibcon#read 6, iclass 24, count 0 2006.257.06:39:31.60#ibcon#end of sib2, iclass 24, count 0 2006.257.06:39:31.60#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:39:31.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:39:31.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:39:31.60#ibcon#*before write, iclass 24, count 0 2006.257.06:39:31.60#ibcon#enter sib2, iclass 24, count 0 2006.257.06:39:31.60#ibcon#flushed, iclass 24, count 0 2006.257.06:39:31.60#ibcon#about to write, iclass 24, count 0 2006.257.06:39:31.60#ibcon#wrote, iclass 24, count 0 2006.257.06:39:31.60#ibcon#about to read 3, iclass 24, count 0 2006.257.06:39:31.64#ibcon#read 3, iclass 24, count 0 2006.257.06:39:31.64#ibcon#about to read 4, iclass 24, count 0 2006.257.06:39:31.64#ibcon#read 4, iclass 24, count 0 2006.257.06:39:31.64#ibcon#about to read 5, iclass 24, count 0 2006.257.06:39:31.64#ibcon#read 5, iclass 24, count 0 2006.257.06:39:31.64#ibcon#about to read 6, iclass 24, count 0 2006.257.06:39:31.64#ibcon#read 6, iclass 24, count 0 2006.257.06:39:31.64#ibcon#end of sib2, iclass 24, count 0 2006.257.06:39:31.64#ibcon#*after write, iclass 24, count 0 2006.257.06:39:31.64#ibcon#*before return 0, iclass 24, count 0 2006.257.06:39:31.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:31.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:31.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:39:31.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:39:31.65$vck44/va=8,4 2006.257.06:39:31.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.06:39:31.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.06:39:31.65#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:31.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:31.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:31.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:31.69#ibcon#enter wrdev, iclass 26, count 2 2006.257.06:39:31.69#ibcon#first serial, iclass 26, count 2 2006.257.06:39:31.69#ibcon#enter sib2, iclass 26, count 2 2006.257.06:39:31.69#ibcon#flushed, iclass 26, count 2 2006.257.06:39:31.69#ibcon#about to write, iclass 26, count 2 2006.257.06:39:31.69#ibcon#wrote, iclass 26, count 2 2006.257.06:39:31.69#ibcon#about to read 3, iclass 26, count 2 2006.257.06:39:31.71#ibcon#read 3, iclass 26, count 2 2006.257.06:39:31.71#ibcon#about to read 4, iclass 26, count 2 2006.257.06:39:31.71#ibcon#read 4, iclass 26, count 2 2006.257.06:39:31.71#ibcon#about to read 5, iclass 26, count 2 2006.257.06:39:31.71#ibcon#read 5, iclass 26, count 2 2006.257.06:39:31.71#ibcon#about to read 6, iclass 26, count 2 2006.257.06:39:31.71#ibcon#read 6, iclass 26, count 2 2006.257.06:39:31.71#ibcon#end of sib2, iclass 26, count 2 2006.257.06:39:31.71#ibcon#*mode == 0, iclass 26, count 2 2006.257.06:39:31.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.06:39:31.71#ibcon#[25=AT08-04\r\n] 2006.257.06:39:31.71#ibcon#*before write, iclass 26, count 2 2006.257.06:39:31.71#ibcon#enter sib2, iclass 26, count 2 2006.257.06:39:31.71#ibcon#flushed, iclass 26, count 2 2006.257.06:39:31.71#ibcon#about to write, iclass 26, count 2 2006.257.06:39:31.71#ibcon#wrote, iclass 26, count 2 2006.257.06:39:31.71#ibcon#about to read 3, iclass 26, count 2 2006.257.06:39:31.74#ibcon#read 3, iclass 26, count 2 2006.257.06:39:31.74#ibcon#about to read 4, iclass 26, count 2 2006.257.06:39:31.74#ibcon#read 4, iclass 26, count 2 2006.257.06:39:31.74#ibcon#about to read 5, iclass 26, count 2 2006.257.06:39:31.74#ibcon#read 5, iclass 26, count 2 2006.257.06:39:31.74#ibcon#about to read 6, iclass 26, count 2 2006.257.06:39:31.74#ibcon#read 6, iclass 26, count 2 2006.257.06:39:31.74#ibcon#end of sib2, iclass 26, count 2 2006.257.06:39:31.74#ibcon#*after write, iclass 26, count 2 2006.257.06:39:31.74#ibcon#*before return 0, iclass 26, count 2 2006.257.06:39:31.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:31.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:31.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.06:39:31.74#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:31.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:31.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:31.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:31.86#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:39:31.86#ibcon#first serial, iclass 26, count 0 2006.257.06:39:31.86#ibcon#enter sib2, iclass 26, count 0 2006.257.06:39:31.86#ibcon#flushed, iclass 26, count 0 2006.257.06:39:31.86#ibcon#about to write, iclass 26, count 0 2006.257.06:39:31.86#ibcon#wrote, iclass 26, count 0 2006.257.06:39:31.86#ibcon#about to read 3, iclass 26, count 0 2006.257.06:39:31.88#ibcon#read 3, iclass 26, count 0 2006.257.06:39:31.88#ibcon#about to read 4, iclass 26, count 0 2006.257.06:39:31.88#ibcon#read 4, iclass 26, count 0 2006.257.06:39:31.88#ibcon#about to read 5, iclass 26, count 0 2006.257.06:39:31.88#ibcon#read 5, iclass 26, count 0 2006.257.06:39:31.88#ibcon#about to read 6, iclass 26, count 0 2006.257.06:39:31.88#ibcon#read 6, iclass 26, count 0 2006.257.06:39:31.88#ibcon#end of sib2, iclass 26, count 0 2006.257.06:39:31.88#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:39:31.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:39:31.88#ibcon#[25=USB\r\n] 2006.257.06:39:31.88#ibcon#*before write, iclass 26, count 0 2006.257.06:39:31.88#ibcon#enter sib2, iclass 26, count 0 2006.257.06:39:31.88#ibcon#flushed, iclass 26, count 0 2006.257.06:39:31.88#ibcon#about to write, iclass 26, count 0 2006.257.06:39:31.88#ibcon#wrote, iclass 26, count 0 2006.257.06:39:31.88#ibcon#about to read 3, iclass 26, count 0 2006.257.06:39:31.91#ibcon#read 3, iclass 26, count 0 2006.257.06:39:31.91#ibcon#about to read 4, iclass 26, count 0 2006.257.06:39:31.91#ibcon#read 4, iclass 26, count 0 2006.257.06:39:31.91#ibcon#about to read 5, iclass 26, count 0 2006.257.06:39:31.91#ibcon#read 5, iclass 26, count 0 2006.257.06:39:31.91#ibcon#about to read 6, iclass 26, count 0 2006.257.06:39:31.91#ibcon#read 6, iclass 26, count 0 2006.257.06:39:31.91#ibcon#end of sib2, iclass 26, count 0 2006.257.06:39:31.91#ibcon#*after write, iclass 26, count 0 2006.257.06:39:31.91#ibcon#*before return 0, iclass 26, count 0 2006.257.06:39:31.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:31.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:31.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:39:31.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:39:31.92$vck44/vblo=1,629.99 2006.257.06:39:31.92#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.06:39:31.92#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.06:39:31.92#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:31.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:31.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:31.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:31.92#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:39:31.92#ibcon#first serial, iclass 28, count 0 2006.257.06:39:31.92#ibcon#enter sib2, iclass 28, count 0 2006.257.06:39:31.92#ibcon#flushed, iclass 28, count 0 2006.257.06:39:31.92#ibcon#about to write, iclass 28, count 0 2006.257.06:39:31.92#ibcon#wrote, iclass 28, count 0 2006.257.06:39:31.92#ibcon#about to read 3, iclass 28, count 0 2006.257.06:39:31.93#ibcon#read 3, iclass 28, count 0 2006.257.06:39:31.93#ibcon#about to read 4, iclass 28, count 0 2006.257.06:39:31.93#ibcon#read 4, iclass 28, count 0 2006.257.06:39:31.93#ibcon#about to read 5, iclass 28, count 0 2006.257.06:39:31.93#ibcon#read 5, iclass 28, count 0 2006.257.06:39:31.93#ibcon#about to read 6, iclass 28, count 0 2006.257.06:39:31.93#ibcon#read 6, iclass 28, count 0 2006.257.06:39:31.93#ibcon#end of sib2, iclass 28, count 0 2006.257.06:39:31.93#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:39:31.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:39:31.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:39:31.93#ibcon#*before write, iclass 28, count 0 2006.257.06:39:31.93#ibcon#enter sib2, iclass 28, count 0 2006.257.06:39:31.93#ibcon#flushed, iclass 28, count 0 2006.257.06:39:31.93#ibcon#about to write, iclass 28, count 0 2006.257.06:39:31.93#ibcon#wrote, iclass 28, count 0 2006.257.06:39:31.94#ibcon#about to read 3, iclass 28, count 0 2006.257.06:39:31.97#ibcon#read 3, iclass 28, count 0 2006.257.06:39:31.97#ibcon#about to read 4, iclass 28, count 0 2006.257.06:39:31.97#ibcon#read 4, iclass 28, count 0 2006.257.06:39:31.97#ibcon#about to read 5, iclass 28, count 0 2006.257.06:39:31.97#ibcon#read 5, iclass 28, count 0 2006.257.06:39:31.97#ibcon#about to read 6, iclass 28, count 0 2006.257.06:39:31.97#ibcon#read 6, iclass 28, count 0 2006.257.06:39:31.97#ibcon#end of sib2, iclass 28, count 0 2006.257.06:39:31.97#ibcon#*after write, iclass 28, count 0 2006.257.06:39:31.97#ibcon#*before return 0, iclass 28, count 0 2006.257.06:39:31.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:31.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:31.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:39:31.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:39:31.98$vck44/vb=1,4 2006.257.06:39:31.98#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.06:39:31.98#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.06:39:31.98#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:31.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:39:31.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:39:31.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:39:31.98#ibcon#enter wrdev, iclass 30, count 2 2006.257.06:39:31.98#ibcon#first serial, iclass 30, count 2 2006.257.06:39:31.98#ibcon#enter sib2, iclass 30, count 2 2006.257.06:39:31.98#ibcon#flushed, iclass 30, count 2 2006.257.06:39:31.98#ibcon#about to write, iclass 30, count 2 2006.257.06:39:31.98#ibcon#wrote, iclass 30, count 2 2006.257.06:39:31.98#ibcon#about to read 3, iclass 30, count 2 2006.257.06:39:31.99#ibcon#read 3, iclass 30, count 2 2006.257.06:39:31.99#ibcon#about to read 4, iclass 30, count 2 2006.257.06:39:31.99#ibcon#read 4, iclass 30, count 2 2006.257.06:39:31.99#ibcon#about to read 5, iclass 30, count 2 2006.257.06:39:31.99#ibcon#read 5, iclass 30, count 2 2006.257.06:39:31.99#ibcon#about to read 6, iclass 30, count 2 2006.257.06:39:31.99#ibcon#read 6, iclass 30, count 2 2006.257.06:39:31.99#ibcon#end of sib2, iclass 30, count 2 2006.257.06:39:31.99#ibcon#*mode == 0, iclass 30, count 2 2006.257.06:39:31.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.06:39:31.99#ibcon#[27=AT01-04\r\n] 2006.257.06:39:31.99#ibcon#*before write, iclass 30, count 2 2006.257.06:39:31.99#ibcon#enter sib2, iclass 30, count 2 2006.257.06:39:31.99#ibcon#flushed, iclass 30, count 2 2006.257.06:39:31.99#ibcon#about to write, iclass 30, count 2 2006.257.06:39:31.99#ibcon#wrote, iclass 30, count 2 2006.257.06:39:31.99#ibcon#about to read 3, iclass 30, count 2 2006.257.06:39:32.02#ibcon#read 3, iclass 30, count 2 2006.257.06:39:32.02#ibcon#about to read 4, iclass 30, count 2 2006.257.06:39:32.02#ibcon#read 4, iclass 30, count 2 2006.257.06:39:32.02#ibcon#about to read 5, iclass 30, count 2 2006.257.06:39:32.02#ibcon#read 5, iclass 30, count 2 2006.257.06:39:32.02#ibcon#about to read 6, iclass 30, count 2 2006.257.06:39:32.02#ibcon#read 6, iclass 30, count 2 2006.257.06:39:32.02#ibcon#end of sib2, iclass 30, count 2 2006.257.06:39:32.02#ibcon#*after write, iclass 30, count 2 2006.257.06:39:32.02#ibcon#*before return 0, iclass 30, count 2 2006.257.06:39:32.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:39:32.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:39:32.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.06:39:32.02#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:32.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:39:32.12#abcon#<5=/15 0.7 2.3 20.67 891012.2\r\n> 2006.257.06:39:32.14#abcon#{5=INTERFACE CLEAR} 2006.257.06:39:32.15#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:39:32.15#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:39:32.15#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:39:32.15#ibcon#first serial, iclass 30, count 0 2006.257.06:39:32.15#ibcon#enter sib2, iclass 30, count 0 2006.257.06:39:32.15#ibcon#flushed, iclass 30, count 0 2006.257.06:39:32.15#ibcon#about to write, iclass 30, count 0 2006.257.06:39:32.15#ibcon#wrote, iclass 30, count 0 2006.257.06:39:32.15#ibcon#about to read 3, iclass 30, count 0 2006.257.06:39:32.16#ibcon#read 3, iclass 30, count 0 2006.257.06:39:32.16#ibcon#about to read 4, iclass 30, count 0 2006.257.06:39:32.16#ibcon#read 4, iclass 30, count 0 2006.257.06:39:32.16#ibcon#about to read 5, iclass 30, count 0 2006.257.06:39:32.16#ibcon#read 5, iclass 30, count 0 2006.257.06:39:32.16#ibcon#about to read 6, iclass 30, count 0 2006.257.06:39:32.16#ibcon#read 6, iclass 30, count 0 2006.257.06:39:32.16#ibcon#end of sib2, iclass 30, count 0 2006.257.06:39:32.16#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:39:32.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:39:32.16#ibcon#[27=USB\r\n] 2006.257.06:39:32.16#ibcon#*before write, iclass 30, count 0 2006.257.06:39:32.16#ibcon#enter sib2, iclass 30, count 0 2006.257.06:39:32.16#ibcon#flushed, iclass 30, count 0 2006.257.06:39:32.16#ibcon#about to write, iclass 30, count 0 2006.257.06:39:32.16#ibcon#wrote, iclass 30, count 0 2006.257.06:39:32.16#ibcon#about to read 3, iclass 30, count 0 2006.257.06:39:32.19#ibcon#read 3, iclass 30, count 0 2006.257.06:39:32.19#ibcon#about to read 4, iclass 30, count 0 2006.257.06:39:32.19#ibcon#read 4, iclass 30, count 0 2006.257.06:39:32.19#ibcon#about to read 5, iclass 30, count 0 2006.257.06:39:32.19#ibcon#read 5, iclass 30, count 0 2006.257.06:39:32.19#ibcon#about to read 6, iclass 30, count 0 2006.257.06:39:32.19#ibcon#read 6, iclass 30, count 0 2006.257.06:39:32.19#ibcon#end of sib2, iclass 30, count 0 2006.257.06:39:32.19#ibcon#*after write, iclass 30, count 0 2006.257.06:39:32.19#ibcon#*before return 0, iclass 30, count 0 2006.257.06:39:32.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:39:32.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:39:32.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:39:32.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:39:32.20$vck44/vblo=2,634.99 2006.257.06:39:32.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.06:39:32.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.06:39:32.20#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:32.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:32.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:32.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:32.20#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:39:32.20#ibcon#first serial, iclass 36, count 0 2006.257.06:39:32.20#ibcon#enter sib2, iclass 36, count 0 2006.257.06:39:32.20#ibcon#flushed, iclass 36, count 0 2006.257.06:39:32.20#ibcon#about to write, iclass 36, count 0 2006.257.06:39:32.20#ibcon#wrote, iclass 36, count 0 2006.257.06:39:32.20#ibcon#about to read 3, iclass 36, count 0 2006.257.06:39:32.20#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:39:32.21#ibcon#read 3, iclass 36, count 0 2006.257.06:39:32.21#ibcon#about to read 4, iclass 36, count 0 2006.257.06:39:32.21#ibcon#read 4, iclass 36, count 0 2006.257.06:39:32.21#ibcon#about to read 5, iclass 36, count 0 2006.257.06:39:32.21#ibcon#read 5, iclass 36, count 0 2006.257.06:39:32.21#ibcon#about to read 6, iclass 36, count 0 2006.257.06:39:32.21#ibcon#read 6, iclass 36, count 0 2006.257.06:39:32.21#ibcon#end of sib2, iclass 36, count 0 2006.257.06:39:32.21#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:39:32.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:39:32.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:39:32.21#ibcon#*before write, iclass 36, count 0 2006.257.06:39:32.21#ibcon#enter sib2, iclass 36, count 0 2006.257.06:39:32.21#ibcon#flushed, iclass 36, count 0 2006.257.06:39:32.21#ibcon#about to write, iclass 36, count 0 2006.257.06:39:32.21#ibcon#wrote, iclass 36, count 0 2006.257.06:39:32.21#ibcon#about to read 3, iclass 36, count 0 2006.257.06:39:32.25#ibcon#read 3, iclass 36, count 0 2006.257.06:39:32.25#ibcon#about to read 4, iclass 36, count 0 2006.257.06:39:32.25#ibcon#read 4, iclass 36, count 0 2006.257.06:39:32.25#ibcon#about to read 5, iclass 36, count 0 2006.257.06:39:32.25#ibcon#read 5, iclass 36, count 0 2006.257.06:39:32.25#ibcon#about to read 6, iclass 36, count 0 2006.257.06:39:32.25#ibcon#read 6, iclass 36, count 0 2006.257.06:39:32.25#ibcon#end of sib2, iclass 36, count 0 2006.257.06:39:32.25#ibcon#*after write, iclass 36, count 0 2006.257.06:39:32.25#ibcon#*before return 0, iclass 36, count 0 2006.257.06:39:32.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:32.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:39:32.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:39:32.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:39:32.26$vck44/vb=2,5 2006.257.06:39:32.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.06:39:32.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.06:39:32.26#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:32.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:32.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:32.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:32.30#ibcon#enter wrdev, iclass 38, count 2 2006.257.06:39:32.30#ibcon#first serial, iclass 38, count 2 2006.257.06:39:32.30#ibcon#enter sib2, iclass 38, count 2 2006.257.06:39:32.30#ibcon#flushed, iclass 38, count 2 2006.257.06:39:32.30#ibcon#about to write, iclass 38, count 2 2006.257.06:39:32.30#ibcon#wrote, iclass 38, count 2 2006.257.06:39:32.30#ibcon#about to read 3, iclass 38, count 2 2006.257.06:39:32.32#ibcon#read 3, iclass 38, count 2 2006.257.06:39:32.32#ibcon#about to read 4, iclass 38, count 2 2006.257.06:39:32.32#ibcon#read 4, iclass 38, count 2 2006.257.06:39:32.32#ibcon#about to read 5, iclass 38, count 2 2006.257.06:39:32.32#ibcon#read 5, iclass 38, count 2 2006.257.06:39:32.32#ibcon#about to read 6, iclass 38, count 2 2006.257.06:39:32.32#ibcon#read 6, iclass 38, count 2 2006.257.06:39:32.32#ibcon#end of sib2, iclass 38, count 2 2006.257.06:39:32.32#ibcon#*mode == 0, iclass 38, count 2 2006.257.06:39:32.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.06:39:32.32#ibcon#[27=AT02-05\r\n] 2006.257.06:39:32.32#ibcon#*before write, iclass 38, count 2 2006.257.06:39:32.32#ibcon#enter sib2, iclass 38, count 2 2006.257.06:39:32.32#ibcon#flushed, iclass 38, count 2 2006.257.06:39:32.32#ibcon#about to write, iclass 38, count 2 2006.257.06:39:32.32#ibcon#wrote, iclass 38, count 2 2006.257.06:39:32.32#ibcon#about to read 3, iclass 38, count 2 2006.257.06:39:32.35#ibcon#read 3, iclass 38, count 2 2006.257.06:39:32.35#ibcon#about to read 4, iclass 38, count 2 2006.257.06:39:32.35#ibcon#read 4, iclass 38, count 2 2006.257.06:39:32.35#ibcon#about to read 5, iclass 38, count 2 2006.257.06:39:32.35#ibcon#read 5, iclass 38, count 2 2006.257.06:39:32.35#ibcon#about to read 6, iclass 38, count 2 2006.257.06:39:32.35#ibcon#read 6, iclass 38, count 2 2006.257.06:39:32.35#ibcon#end of sib2, iclass 38, count 2 2006.257.06:39:32.35#ibcon#*after write, iclass 38, count 2 2006.257.06:39:32.35#ibcon#*before return 0, iclass 38, count 2 2006.257.06:39:32.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:32.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:39:32.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.06:39:32.35#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:32.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:32.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:32.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:32.47#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:39:32.47#ibcon#first serial, iclass 38, count 0 2006.257.06:39:32.47#ibcon#enter sib2, iclass 38, count 0 2006.257.06:39:32.47#ibcon#flushed, iclass 38, count 0 2006.257.06:39:32.47#ibcon#about to write, iclass 38, count 0 2006.257.06:39:32.47#ibcon#wrote, iclass 38, count 0 2006.257.06:39:32.47#ibcon#about to read 3, iclass 38, count 0 2006.257.06:39:32.49#ibcon#read 3, iclass 38, count 0 2006.257.06:39:32.49#ibcon#about to read 4, iclass 38, count 0 2006.257.06:39:32.49#ibcon#read 4, iclass 38, count 0 2006.257.06:39:32.49#ibcon#about to read 5, iclass 38, count 0 2006.257.06:39:32.49#ibcon#read 5, iclass 38, count 0 2006.257.06:39:32.49#ibcon#about to read 6, iclass 38, count 0 2006.257.06:39:32.49#ibcon#read 6, iclass 38, count 0 2006.257.06:39:32.49#ibcon#end of sib2, iclass 38, count 0 2006.257.06:39:32.49#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:39:32.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:39:32.49#ibcon#[27=USB\r\n] 2006.257.06:39:32.49#ibcon#*before write, iclass 38, count 0 2006.257.06:39:32.49#ibcon#enter sib2, iclass 38, count 0 2006.257.06:39:32.49#ibcon#flushed, iclass 38, count 0 2006.257.06:39:32.49#ibcon#about to write, iclass 38, count 0 2006.257.06:39:32.49#ibcon#wrote, iclass 38, count 0 2006.257.06:39:32.49#ibcon#about to read 3, iclass 38, count 0 2006.257.06:39:32.52#ibcon#read 3, iclass 38, count 0 2006.257.06:39:32.52#ibcon#about to read 4, iclass 38, count 0 2006.257.06:39:32.52#ibcon#read 4, iclass 38, count 0 2006.257.06:39:32.52#ibcon#about to read 5, iclass 38, count 0 2006.257.06:39:32.52#ibcon#read 5, iclass 38, count 0 2006.257.06:39:32.52#ibcon#about to read 6, iclass 38, count 0 2006.257.06:39:32.52#ibcon#read 6, iclass 38, count 0 2006.257.06:39:32.52#ibcon#end of sib2, iclass 38, count 0 2006.257.06:39:32.52#ibcon#*after write, iclass 38, count 0 2006.257.06:39:32.52#ibcon#*before return 0, iclass 38, count 0 2006.257.06:39:32.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:32.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:39:32.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:39:32.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:39:32.53$vck44/vblo=3,649.99 2006.257.06:39:32.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.06:39:32.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.06:39:32.53#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:32.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:32.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:32.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:32.53#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:39:32.53#ibcon#first serial, iclass 40, count 0 2006.257.06:39:32.53#ibcon#enter sib2, iclass 40, count 0 2006.257.06:39:32.53#ibcon#flushed, iclass 40, count 0 2006.257.06:39:32.53#ibcon#about to write, iclass 40, count 0 2006.257.06:39:32.53#ibcon#wrote, iclass 40, count 0 2006.257.06:39:32.53#ibcon#about to read 3, iclass 40, count 0 2006.257.06:39:32.54#ibcon#read 3, iclass 40, count 0 2006.257.06:39:32.54#ibcon#about to read 4, iclass 40, count 0 2006.257.06:39:32.54#ibcon#read 4, iclass 40, count 0 2006.257.06:39:32.54#ibcon#about to read 5, iclass 40, count 0 2006.257.06:39:32.54#ibcon#read 5, iclass 40, count 0 2006.257.06:39:32.54#ibcon#about to read 6, iclass 40, count 0 2006.257.06:39:32.54#ibcon#read 6, iclass 40, count 0 2006.257.06:39:32.54#ibcon#end of sib2, iclass 40, count 0 2006.257.06:39:32.54#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:39:32.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:39:32.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:39:32.54#ibcon#*before write, iclass 40, count 0 2006.257.06:39:32.54#ibcon#enter sib2, iclass 40, count 0 2006.257.06:39:32.54#ibcon#flushed, iclass 40, count 0 2006.257.06:39:32.54#ibcon#about to write, iclass 40, count 0 2006.257.06:39:32.54#ibcon#wrote, iclass 40, count 0 2006.257.06:39:32.54#ibcon#about to read 3, iclass 40, count 0 2006.257.06:39:32.58#ibcon#read 3, iclass 40, count 0 2006.257.06:39:32.58#ibcon#about to read 4, iclass 40, count 0 2006.257.06:39:32.58#ibcon#read 4, iclass 40, count 0 2006.257.06:39:32.58#ibcon#about to read 5, iclass 40, count 0 2006.257.06:39:32.58#ibcon#read 5, iclass 40, count 0 2006.257.06:39:32.58#ibcon#about to read 6, iclass 40, count 0 2006.257.06:39:32.58#ibcon#read 6, iclass 40, count 0 2006.257.06:39:32.58#ibcon#end of sib2, iclass 40, count 0 2006.257.06:39:32.58#ibcon#*after write, iclass 40, count 0 2006.257.06:39:32.58#ibcon#*before return 0, iclass 40, count 0 2006.257.06:39:32.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:32.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:39:32.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:39:32.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:39:32.59$vck44/vb=3,4 2006.257.06:39:32.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.06:39:32.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.06:39:32.59#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:32.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:32.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:32.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:32.63#ibcon#enter wrdev, iclass 4, count 2 2006.257.06:39:32.63#ibcon#first serial, iclass 4, count 2 2006.257.06:39:32.63#ibcon#enter sib2, iclass 4, count 2 2006.257.06:39:32.63#ibcon#flushed, iclass 4, count 2 2006.257.06:39:32.63#ibcon#about to write, iclass 4, count 2 2006.257.06:39:32.63#ibcon#wrote, iclass 4, count 2 2006.257.06:39:32.63#ibcon#about to read 3, iclass 4, count 2 2006.257.06:39:32.65#ibcon#read 3, iclass 4, count 2 2006.257.06:39:32.65#ibcon#about to read 4, iclass 4, count 2 2006.257.06:39:32.65#ibcon#read 4, iclass 4, count 2 2006.257.06:39:32.65#ibcon#about to read 5, iclass 4, count 2 2006.257.06:39:32.65#ibcon#read 5, iclass 4, count 2 2006.257.06:39:32.65#ibcon#about to read 6, iclass 4, count 2 2006.257.06:39:32.65#ibcon#read 6, iclass 4, count 2 2006.257.06:39:32.65#ibcon#end of sib2, iclass 4, count 2 2006.257.06:39:32.65#ibcon#*mode == 0, iclass 4, count 2 2006.257.06:39:32.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.06:39:32.65#ibcon#[27=AT03-04\r\n] 2006.257.06:39:32.65#ibcon#*before write, iclass 4, count 2 2006.257.06:39:32.65#ibcon#enter sib2, iclass 4, count 2 2006.257.06:39:32.65#ibcon#flushed, iclass 4, count 2 2006.257.06:39:32.65#ibcon#about to write, iclass 4, count 2 2006.257.06:39:32.65#ibcon#wrote, iclass 4, count 2 2006.257.06:39:32.65#ibcon#about to read 3, iclass 4, count 2 2006.257.06:39:32.68#ibcon#read 3, iclass 4, count 2 2006.257.06:39:32.68#ibcon#about to read 4, iclass 4, count 2 2006.257.06:39:32.68#ibcon#read 4, iclass 4, count 2 2006.257.06:39:32.68#ibcon#about to read 5, iclass 4, count 2 2006.257.06:39:32.68#ibcon#read 5, iclass 4, count 2 2006.257.06:39:32.68#ibcon#about to read 6, iclass 4, count 2 2006.257.06:39:32.68#ibcon#read 6, iclass 4, count 2 2006.257.06:39:32.68#ibcon#end of sib2, iclass 4, count 2 2006.257.06:39:32.68#ibcon#*after write, iclass 4, count 2 2006.257.06:39:32.68#ibcon#*before return 0, iclass 4, count 2 2006.257.06:39:32.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:32.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:39:32.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.06:39:32.68#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:32.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:32.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:32.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:32.80#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:39:32.80#ibcon#first serial, iclass 4, count 0 2006.257.06:39:32.80#ibcon#enter sib2, iclass 4, count 0 2006.257.06:39:32.80#ibcon#flushed, iclass 4, count 0 2006.257.06:39:32.80#ibcon#about to write, iclass 4, count 0 2006.257.06:39:32.80#ibcon#wrote, iclass 4, count 0 2006.257.06:39:32.80#ibcon#about to read 3, iclass 4, count 0 2006.257.06:39:32.82#ibcon#read 3, iclass 4, count 0 2006.257.06:39:32.82#ibcon#about to read 4, iclass 4, count 0 2006.257.06:39:32.82#ibcon#read 4, iclass 4, count 0 2006.257.06:39:32.82#ibcon#about to read 5, iclass 4, count 0 2006.257.06:39:32.82#ibcon#read 5, iclass 4, count 0 2006.257.06:39:32.82#ibcon#about to read 6, iclass 4, count 0 2006.257.06:39:32.82#ibcon#read 6, iclass 4, count 0 2006.257.06:39:32.82#ibcon#end of sib2, iclass 4, count 0 2006.257.06:39:32.82#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:39:32.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:39:32.82#ibcon#[27=USB\r\n] 2006.257.06:39:32.82#ibcon#*before write, iclass 4, count 0 2006.257.06:39:32.82#ibcon#enter sib2, iclass 4, count 0 2006.257.06:39:32.82#ibcon#flushed, iclass 4, count 0 2006.257.06:39:32.82#ibcon#about to write, iclass 4, count 0 2006.257.06:39:32.82#ibcon#wrote, iclass 4, count 0 2006.257.06:39:32.82#ibcon#about to read 3, iclass 4, count 0 2006.257.06:39:32.85#ibcon#read 3, iclass 4, count 0 2006.257.06:39:32.85#ibcon#about to read 4, iclass 4, count 0 2006.257.06:39:32.85#ibcon#read 4, iclass 4, count 0 2006.257.06:39:32.85#ibcon#about to read 5, iclass 4, count 0 2006.257.06:39:32.85#ibcon#read 5, iclass 4, count 0 2006.257.06:39:32.85#ibcon#about to read 6, iclass 4, count 0 2006.257.06:39:32.85#ibcon#read 6, iclass 4, count 0 2006.257.06:39:32.85#ibcon#end of sib2, iclass 4, count 0 2006.257.06:39:32.85#ibcon#*after write, iclass 4, count 0 2006.257.06:39:32.85#ibcon#*before return 0, iclass 4, count 0 2006.257.06:39:32.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:32.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:39:32.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:39:32.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:39:32.86$vck44/vblo=4,679.99 2006.257.06:39:32.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.06:39:32.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.06:39:32.86#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:32.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:32.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:32.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:32.86#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:39:32.86#ibcon#first serial, iclass 6, count 0 2006.257.06:39:32.86#ibcon#enter sib2, iclass 6, count 0 2006.257.06:39:32.86#ibcon#flushed, iclass 6, count 0 2006.257.06:39:32.86#ibcon#about to write, iclass 6, count 0 2006.257.06:39:32.86#ibcon#wrote, iclass 6, count 0 2006.257.06:39:32.86#ibcon#about to read 3, iclass 6, count 0 2006.257.06:39:32.87#ibcon#read 3, iclass 6, count 0 2006.257.06:39:32.87#ibcon#about to read 4, iclass 6, count 0 2006.257.06:39:32.87#ibcon#read 4, iclass 6, count 0 2006.257.06:39:32.87#ibcon#about to read 5, iclass 6, count 0 2006.257.06:39:32.87#ibcon#read 5, iclass 6, count 0 2006.257.06:39:32.87#ibcon#about to read 6, iclass 6, count 0 2006.257.06:39:32.87#ibcon#read 6, iclass 6, count 0 2006.257.06:39:32.87#ibcon#end of sib2, iclass 6, count 0 2006.257.06:39:32.87#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:39:32.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:39:32.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:39:32.87#ibcon#*before write, iclass 6, count 0 2006.257.06:39:32.87#ibcon#enter sib2, iclass 6, count 0 2006.257.06:39:32.87#ibcon#flushed, iclass 6, count 0 2006.257.06:39:32.87#ibcon#about to write, iclass 6, count 0 2006.257.06:39:32.87#ibcon#wrote, iclass 6, count 0 2006.257.06:39:32.87#ibcon#about to read 3, iclass 6, count 0 2006.257.06:39:32.91#ibcon#read 3, iclass 6, count 0 2006.257.06:39:32.91#ibcon#about to read 4, iclass 6, count 0 2006.257.06:39:32.91#ibcon#read 4, iclass 6, count 0 2006.257.06:39:32.91#ibcon#about to read 5, iclass 6, count 0 2006.257.06:39:32.91#ibcon#read 5, iclass 6, count 0 2006.257.06:39:32.91#ibcon#about to read 6, iclass 6, count 0 2006.257.06:39:32.91#ibcon#read 6, iclass 6, count 0 2006.257.06:39:32.91#ibcon#end of sib2, iclass 6, count 0 2006.257.06:39:32.91#ibcon#*after write, iclass 6, count 0 2006.257.06:39:32.91#ibcon#*before return 0, iclass 6, count 0 2006.257.06:39:32.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:32.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:39:32.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:39:32.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:39:32.92$vck44/vb=4,5 2006.257.06:39:32.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.06:39:32.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.06:39:32.92#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:32.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:32.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:32.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:32.96#ibcon#enter wrdev, iclass 10, count 2 2006.257.06:39:32.96#ibcon#first serial, iclass 10, count 2 2006.257.06:39:32.96#ibcon#enter sib2, iclass 10, count 2 2006.257.06:39:32.96#ibcon#flushed, iclass 10, count 2 2006.257.06:39:32.96#ibcon#about to write, iclass 10, count 2 2006.257.06:39:32.96#ibcon#wrote, iclass 10, count 2 2006.257.06:39:32.96#ibcon#about to read 3, iclass 10, count 2 2006.257.06:39:32.98#ibcon#read 3, iclass 10, count 2 2006.257.06:39:32.98#ibcon#about to read 4, iclass 10, count 2 2006.257.06:39:32.98#ibcon#read 4, iclass 10, count 2 2006.257.06:39:32.98#ibcon#about to read 5, iclass 10, count 2 2006.257.06:39:32.98#ibcon#read 5, iclass 10, count 2 2006.257.06:39:32.98#ibcon#about to read 6, iclass 10, count 2 2006.257.06:39:32.98#ibcon#read 6, iclass 10, count 2 2006.257.06:39:32.98#ibcon#end of sib2, iclass 10, count 2 2006.257.06:39:32.98#ibcon#*mode == 0, iclass 10, count 2 2006.257.06:39:32.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.06:39:32.98#ibcon#[27=AT04-05\r\n] 2006.257.06:39:32.98#ibcon#*before write, iclass 10, count 2 2006.257.06:39:32.98#ibcon#enter sib2, iclass 10, count 2 2006.257.06:39:32.98#ibcon#flushed, iclass 10, count 2 2006.257.06:39:32.98#ibcon#about to write, iclass 10, count 2 2006.257.06:39:32.98#ibcon#wrote, iclass 10, count 2 2006.257.06:39:32.98#ibcon#about to read 3, iclass 10, count 2 2006.257.06:39:33.01#ibcon#read 3, iclass 10, count 2 2006.257.06:39:33.01#ibcon#about to read 4, iclass 10, count 2 2006.257.06:39:33.01#ibcon#read 4, iclass 10, count 2 2006.257.06:39:33.01#ibcon#about to read 5, iclass 10, count 2 2006.257.06:39:33.01#ibcon#read 5, iclass 10, count 2 2006.257.06:39:33.01#ibcon#about to read 6, iclass 10, count 2 2006.257.06:39:33.01#ibcon#read 6, iclass 10, count 2 2006.257.06:39:33.01#ibcon#end of sib2, iclass 10, count 2 2006.257.06:39:33.01#ibcon#*after write, iclass 10, count 2 2006.257.06:39:33.01#ibcon#*before return 0, iclass 10, count 2 2006.257.06:39:33.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:33.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:39:33.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.06:39:33.01#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:33.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:33.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:33.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:33.13#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:39:33.13#ibcon#first serial, iclass 10, count 0 2006.257.06:39:33.13#ibcon#enter sib2, iclass 10, count 0 2006.257.06:39:33.13#ibcon#flushed, iclass 10, count 0 2006.257.06:39:33.13#ibcon#about to write, iclass 10, count 0 2006.257.06:39:33.13#ibcon#wrote, iclass 10, count 0 2006.257.06:39:33.13#ibcon#about to read 3, iclass 10, count 0 2006.257.06:39:33.15#ibcon#read 3, iclass 10, count 0 2006.257.06:39:33.15#ibcon#about to read 4, iclass 10, count 0 2006.257.06:39:33.15#ibcon#read 4, iclass 10, count 0 2006.257.06:39:33.15#ibcon#about to read 5, iclass 10, count 0 2006.257.06:39:33.15#ibcon#read 5, iclass 10, count 0 2006.257.06:39:33.15#ibcon#about to read 6, iclass 10, count 0 2006.257.06:39:33.15#ibcon#read 6, iclass 10, count 0 2006.257.06:39:33.15#ibcon#end of sib2, iclass 10, count 0 2006.257.06:39:33.15#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:39:33.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:39:33.15#ibcon#[27=USB\r\n] 2006.257.06:39:33.15#ibcon#*before write, iclass 10, count 0 2006.257.06:39:33.15#ibcon#enter sib2, iclass 10, count 0 2006.257.06:39:33.15#ibcon#flushed, iclass 10, count 0 2006.257.06:39:33.15#ibcon#about to write, iclass 10, count 0 2006.257.06:39:33.15#ibcon#wrote, iclass 10, count 0 2006.257.06:39:33.15#ibcon#about to read 3, iclass 10, count 0 2006.257.06:39:33.18#ibcon#read 3, iclass 10, count 0 2006.257.06:39:33.18#ibcon#about to read 4, iclass 10, count 0 2006.257.06:39:33.18#ibcon#read 4, iclass 10, count 0 2006.257.06:39:33.18#ibcon#about to read 5, iclass 10, count 0 2006.257.06:39:33.18#ibcon#read 5, iclass 10, count 0 2006.257.06:39:33.18#ibcon#about to read 6, iclass 10, count 0 2006.257.06:39:33.18#ibcon#read 6, iclass 10, count 0 2006.257.06:39:33.18#ibcon#end of sib2, iclass 10, count 0 2006.257.06:39:33.18#ibcon#*after write, iclass 10, count 0 2006.257.06:39:33.18#ibcon#*before return 0, iclass 10, count 0 2006.257.06:39:33.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:33.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:39:33.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:39:33.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:39:33.19$vck44/vblo=5,709.99 2006.257.06:39:33.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.06:39:33.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.06:39:33.19#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:33.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:33.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:33.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:33.19#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:39:33.19#ibcon#first serial, iclass 12, count 0 2006.257.06:39:33.19#ibcon#enter sib2, iclass 12, count 0 2006.257.06:39:33.19#ibcon#flushed, iclass 12, count 0 2006.257.06:39:33.19#ibcon#about to write, iclass 12, count 0 2006.257.06:39:33.19#ibcon#wrote, iclass 12, count 0 2006.257.06:39:33.19#ibcon#about to read 3, iclass 12, count 0 2006.257.06:39:33.20#ibcon#read 3, iclass 12, count 0 2006.257.06:39:33.20#ibcon#about to read 4, iclass 12, count 0 2006.257.06:39:33.20#ibcon#read 4, iclass 12, count 0 2006.257.06:39:33.20#ibcon#about to read 5, iclass 12, count 0 2006.257.06:39:33.20#ibcon#read 5, iclass 12, count 0 2006.257.06:39:33.20#ibcon#about to read 6, iclass 12, count 0 2006.257.06:39:33.20#ibcon#read 6, iclass 12, count 0 2006.257.06:39:33.20#ibcon#end of sib2, iclass 12, count 0 2006.257.06:39:33.20#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:39:33.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:39:33.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:39:33.20#ibcon#*before write, iclass 12, count 0 2006.257.06:39:33.20#ibcon#enter sib2, iclass 12, count 0 2006.257.06:39:33.20#ibcon#flushed, iclass 12, count 0 2006.257.06:39:33.20#ibcon#about to write, iclass 12, count 0 2006.257.06:39:33.20#ibcon#wrote, iclass 12, count 0 2006.257.06:39:33.20#ibcon#about to read 3, iclass 12, count 0 2006.257.06:39:33.24#ibcon#read 3, iclass 12, count 0 2006.257.06:39:33.24#ibcon#about to read 4, iclass 12, count 0 2006.257.06:39:33.24#ibcon#read 4, iclass 12, count 0 2006.257.06:39:33.24#ibcon#about to read 5, iclass 12, count 0 2006.257.06:39:33.24#ibcon#read 5, iclass 12, count 0 2006.257.06:39:33.24#ibcon#about to read 6, iclass 12, count 0 2006.257.06:39:33.24#ibcon#read 6, iclass 12, count 0 2006.257.06:39:33.24#ibcon#end of sib2, iclass 12, count 0 2006.257.06:39:33.24#ibcon#*after write, iclass 12, count 0 2006.257.06:39:33.24#ibcon#*before return 0, iclass 12, count 0 2006.257.06:39:33.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:33.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:39:33.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:39:33.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:39:33.25$vck44/vb=5,4 2006.257.06:39:33.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.06:39:33.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.06:39:33.25#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:33.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:33.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:33.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:33.29#ibcon#enter wrdev, iclass 14, count 2 2006.257.06:39:33.29#ibcon#first serial, iclass 14, count 2 2006.257.06:39:33.29#ibcon#enter sib2, iclass 14, count 2 2006.257.06:39:33.29#ibcon#flushed, iclass 14, count 2 2006.257.06:39:33.29#ibcon#about to write, iclass 14, count 2 2006.257.06:39:33.29#ibcon#wrote, iclass 14, count 2 2006.257.06:39:33.29#ibcon#about to read 3, iclass 14, count 2 2006.257.06:39:33.31#ibcon#read 3, iclass 14, count 2 2006.257.06:39:33.31#ibcon#about to read 4, iclass 14, count 2 2006.257.06:39:33.31#ibcon#read 4, iclass 14, count 2 2006.257.06:39:33.31#ibcon#about to read 5, iclass 14, count 2 2006.257.06:39:33.31#ibcon#read 5, iclass 14, count 2 2006.257.06:39:33.31#ibcon#about to read 6, iclass 14, count 2 2006.257.06:39:33.31#ibcon#read 6, iclass 14, count 2 2006.257.06:39:33.31#ibcon#end of sib2, iclass 14, count 2 2006.257.06:39:33.31#ibcon#*mode == 0, iclass 14, count 2 2006.257.06:39:33.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.06:39:33.31#ibcon#[27=AT05-04\r\n] 2006.257.06:39:33.31#ibcon#*before write, iclass 14, count 2 2006.257.06:39:33.31#ibcon#enter sib2, iclass 14, count 2 2006.257.06:39:33.31#ibcon#flushed, iclass 14, count 2 2006.257.06:39:33.31#ibcon#about to write, iclass 14, count 2 2006.257.06:39:33.31#ibcon#wrote, iclass 14, count 2 2006.257.06:39:33.31#ibcon#about to read 3, iclass 14, count 2 2006.257.06:39:33.34#ibcon#read 3, iclass 14, count 2 2006.257.06:39:33.34#ibcon#about to read 4, iclass 14, count 2 2006.257.06:39:33.34#ibcon#read 4, iclass 14, count 2 2006.257.06:39:33.34#ibcon#about to read 5, iclass 14, count 2 2006.257.06:39:33.34#ibcon#read 5, iclass 14, count 2 2006.257.06:39:33.34#ibcon#about to read 6, iclass 14, count 2 2006.257.06:39:33.34#ibcon#read 6, iclass 14, count 2 2006.257.06:39:33.34#ibcon#end of sib2, iclass 14, count 2 2006.257.06:39:33.34#ibcon#*after write, iclass 14, count 2 2006.257.06:39:33.34#ibcon#*before return 0, iclass 14, count 2 2006.257.06:39:33.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:33.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:39:33.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.06:39:33.34#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:33.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:33.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:33.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:33.46#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:39:33.46#ibcon#first serial, iclass 14, count 0 2006.257.06:39:33.46#ibcon#enter sib2, iclass 14, count 0 2006.257.06:39:33.46#ibcon#flushed, iclass 14, count 0 2006.257.06:39:33.46#ibcon#about to write, iclass 14, count 0 2006.257.06:39:33.46#ibcon#wrote, iclass 14, count 0 2006.257.06:39:33.46#ibcon#about to read 3, iclass 14, count 0 2006.257.06:39:33.48#ibcon#read 3, iclass 14, count 0 2006.257.06:39:33.48#ibcon#about to read 4, iclass 14, count 0 2006.257.06:39:33.48#ibcon#read 4, iclass 14, count 0 2006.257.06:39:33.48#ibcon#about to read 5, iclass 14, count 0 2006.257.06:39:33.48#ibcon#read 5, iclass 14, count 0 2006.257.06:39:33.48#ibcon#about to read 6, iclass 14, count 0 2006.257.06:39:33.48#ibcon#read 6, iclass 14, count 0 2006.257.06:39:33.48#ibcon#end of sib2, iclass 14, count 0 2006.257.06:39:33.48#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:39:33.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:39:33.48#ibcon#[27=USB\r\n] 2006.257.06:39:33.48#ibcon#*before write, iclass 14, count 0 2006.257.06:39:33.48#ibcon#enter sib2, iclass 14, count 0 2006.257.06:39:33.48#ibcon#flushed, iclass 14, count 0 2006.257.06:39:33.48#ibcon#about to write, iclass 14, count 0 2006.257.06:39:33.48#ibcon#wrote, iclass 14, count 0 2006.257.06:39:33.48#ibcon#about to read 3, iclass 14, count 0 2006.257.06:39:33.51#ibcon#read 3, iclass 14, count 0 2006.257.06:39:33.51#ibcon#about to read 4, iclass 14, count 0 2006.257.06:39:33.51#ibcon#read 4, iclass 14, count 0 2006.257.06:39:33.51#ibcon#about to read 5, iclass 14, count 0 2006.257.06:39:33.51#ibcon#read 5, iclass 14, count 0 2006.257.06:39:33.51#ibcon#about to read 6, iclass 14, count 0 2006.257.06:39:33.51#ibcon#read 6, iclass 14, count 0 2006.257.06:39:33.51#ibcon#end of sib2, iclass 14, count 0 2006.257.06:39:33.51#ibcon#*after write, iclass 14, count 0 2006.257.06:39:33.51#ibcon#*before return 0, iclass 14, count 0 2006.257.06:39:33.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:33.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:39:33.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:39:33.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:39:33.52$vck44/vblo=6,719.99 2006.257.06:39:33.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.06:39:33.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.06:39:33.52#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:33.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:33.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:33.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:33.52#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:39:33.52#ibcon#first serial, iclass 16, count 0 2006.257.06:39:33.52#ibcon#enter sib2, iclass 16, count 0 2006.257.06:39:33.52#ibcon#flushed, iclass 16, count 0 2006.257.06:39:33.52#ibcon#about to write, iclass 16, count 0 2006.257.06:39:33.52#ibcon#wrote, iclass 16, count 0 2006.257.06:39:33.52#ibcon#about to read 3, iclass 16, count 0 2006.257.06:39:33.53#ibcon#read 3, iclass 16, count 0 2006.257.06:39:33.53#ibcon#about to read 4, iclass 16, count 0 2006.257.06:39:33.53#ibcon#read 4, iclass 16, count 0 2006.257.06:39:33.53#ibcon#about to read 5, iclass 16, count 0 2006.257.06:39:33.53#ibcon#read 5, iclass 16, count 0 2006.257.06:39:33.53#ibcon#about to read 6, iclass 16, count 0 2006.257.06:39:33.53#ibcon#read 6, iclass 16, count 0 2006.257.06:39:33.53#ibcon#end of sib2, iclass 16, count 0 2006.257.06:39:33.53#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:39:33.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:39:33.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:39:33.53#ibcon#*before write, iclass 16, count 0 2006.257.06:39:33.53#ibcon#enter sib2, iclass 16, count 0 2006.257.06:39:33.53#ibcon#flushed, iclass 16, count 0 2006.257.06:39:33.53#ibcon#about to write, iclass 16, count 0 2006.257.06:39:33.53#ibcon#wrote, iclass 16, count 0 2006.257.06:39:33.53#ibcon#about to read 3, iclass 16, count 0 2006.257.06:39:33.57#ibcon#read 3, iclass 16, count 0 2006.257.06:39:33.57#ibcon#about to read 4, iclass 16, count 0 2006.257.06:39:33.57#ibcon#read 4, iclass 16, count 0 2006.257.06:39:33.57#ibcon#about to read 5, iclass 16, count 0 2006.257.06:39:33.57#ibcon#read 5, iclass 16, count 0 2006.257.06:39:33.57#ibcon#about to read 6, iclass 16, count 0 2006.257.06:39:33.57#ibcon#read 6, iclass 16, count 0 2006.257.06:39:33.57#ibcon#end of sib2, iclass 16, count 0 2006.257.06:39:33.57#ibcon#*after write, iclass 16, count 0 2006.257.06:39:33.57#ibcon#*before return 0, iclass 16, count 0 2006.257.06:39:33.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:33.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:39:33.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:39:33.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:39:33.58$vck44/vb=6,4 2006.257.06:39:33.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.06:39:33.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.06:39:33.58#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:33.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:33.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:33.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:33.62#ibcon#enter wrdev, iclass 18, count 2 2006.257.06:39:33.62#ibcon#first serial, iclass 18, count 2 2006.257.06:39:33.62#ibcon#enter sib2, iclass 18, count 2 2006.257.06:39:33.62#ibcon#flushed, iclass 18, count 2 2006.257.06:39:33.62#ibcon#about to write, iclass 18, count 2 2006.257.06:39:33.62#ibcon#wrote, iclass 18, count 2 2006.257.06:39:33.62#ibcon#about to read 3, iclass 18, count 2 2006.257.06:39:33.64#ibcon#read 3, iclass 18, count 2 2006.257.06:39:33.64#ibcon#about to read 4, iclass 18, count 2 2006.257.06:39:33.64#ibcon#read 4, iclass 18, count 2 2006.257.06:39:33.64#ibcon#about to read 5, iclass 18, count 2 2006.257.06:39:33.64#ibcon#read 5, iclass 18, count 2 2006.257.06:39:33.64#ibcon#about to read 6, iclass 18, count 2 2006.257.06:39:33.64#ibcon#read 6, iclass 18, count 2 2006.257.06:39:33.64#ibcon#end of sib2, iclass 18, count 2 2006.257.06:39:33.64#ibcon#*mode == 0, iclass 18, count 2 2006.257.06:39:33.64#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.06:39:33.64#ibcon#[27=AT06-04\r\n] 2006.257.06:39:33.64#ibcon#*before write, iclass 18, count 2 2006.257.06:39:33.64#ibcon#enter sib2, iclass 18, count 2 2006.257.06:39:33.64#ibcon#flushed, iclass 18, count 2 2006.257.06:39:33.64#ibcon#about to write, iclass 18, count 2 2006.257.06:39:33.64#ibcon#wrote, iclass 18, count 2 2006.257.06:39:33.64#ibcon#about to read 3, iclass 18, count 2 2006.257.06:39:33.67#ibcon#read 3, iclass 18, count 2 2006.257.06:39:33.67#ibcon#about to read 4, iclass 18, count 2 2006.257.06:39:33.67#ibcon#read 4, iclass 18, count 2 2006.257.06:39:33.67#ibcon#about to read 5, iclass 18, count 2 2006.257.06:39:33.67#ibcon#read 5, iclass 18, count 2 2006.257.06:39:33.67#ibcon#about to read 6, iclass 18, count 2 2006.257.06:39:33.67#ibcon#read 6, iclass 18, count 2 2006.257.06:39:33.67#ibcon#end of sib2, iclass 18, count 2 2006.257.06:39:33.67#ibcon#*after write, iclass 18, count 2 2006.257.06:39:33.67#ibcon#*before return 0, iclass 18, count 2 2006.257.06:39:33.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:33.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:39:33.67#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.06:39:33.67#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:33.67#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:33.79#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:33.79#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:33.79#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:39:33.79#ibcon#first serial, iclass 18, count 0 2006.257.06:39:33.79#ibcon#enter sib2, iclass 18, count 0 2006.257.06:39:33.79#ibcon#flushed, iclass 18, count 0 2006.257.06:39:33.79#ibcon#about to write, iclass 18, count 0 2006.257.06:39:33.79#ibcon#wrote, iclass 18, count 0 2006.257.06:39:33.79#ibcon#about to read 3, iclass 18, count 0 2006.257.06:39:33.81#ibcon#read 3, iclass 18, count 0 2006.257.06:39:33.81#ibcon#about to read 4, iclass 18, count 0 2006.257.06:39:33.81#ibcon#read 4, iclass 18, count 0 2006.257.06:39:33.81#ibcon#about to read 5, iclass 18, count 0 2006.257.06:39:33.81#ibcon#read 5, iclass 18, count 0 2006.257.06:39:33.81#ibcon#about to read 6, iclass 18, count 0 2006.257.06:39:33.81#ibcon#read 6, iclass 18, count 0 2006.257.06:39:33.81#ibcon#end of sib2, iclass 18, count 0 2006.257.06:39:33.81#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:39:33.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:39:33.81#ibcon#[27=USB\r\n] 2006.257.06:39:33.81#ibcon#*before write, iclass 18, count 0 2006.257.06:39:33.81#ibcon#enter sib2, iclass 18, count 0 2006.257.06:39:33.81#ibcon#flushed, iclass 18, count 0 2006.257.06:39:33.81#ibcon#about to write, iclass 18, count 0 2006.257.06:39:33.81#ibcon#wrote, iclass 18, count 0 2006.257.06:39:33.81#ibcon#about to read 3, iclass 18, count 0 2006.257.06:39:33.84#ibcon#read 3, iclass 18, count 0 2006.257.06:39:33.84#ibcon#about to read 4, iclass 18, count 0 2006.257.06:39:33.84#ibcon#read 4, iclass 18, count 0 2006.257.06:39:33.84#ibcon#about to read 5, iclass 18, count 0 2006.257.06:39:33.84#ibcon#read 5, iclass 18, count 0 2006.257.06:39:33.84#ibcon#about to read 6, iclass 18, count 0 2006.257.06:39:33.84#ibcon#read 6, iclass 18, count 0 2006.257.06:39:33.84#ibcon#end of sib2, iclass 18, count 0 2006.257.06:39:33.84#ibcon#*after write, iclass 18, count 0 2006.257.06:39:33.84#ibcon#*before return 0, iclass 18, count 0 2006.257.06:39:33.84#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:33.84#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:39:33.84#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:39:33.84#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:39:33.85$vck44/vblo=7,734.99 2006.257.06:39:33.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.06:39:33.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.06:39:33.85#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:33.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:33.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:33.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:33.85#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:39:33.85#ibcon#first serial, iclass 20, count 0 2006.257.06:39:33.85#ibcon#enter sib2, iclass 20, count 0 2006.257.06:39:33.85#ibcon#flushed, iclass 20, count 0 2006.257.06:39:33.85#ibcon#about to write, iclass 20, count 0 2006.257.06:39:33.85#ibcon#wrote, iclass 20, count 0 2006.257.06:39:33.85#ibcon#about to read 3, iclass 20, count 0 2006.257.06:39:33.86#ibcon#read 3, iclass 20, count 0 2006.257.06:39:33.86#ibcon#about to read 4, iclass 20, count 0 2006.257.06:39:33.86#ibcon#read 4, iclass 20, count 0 2006.257.06:39:33.86#ibcon#about to read 5, iclass 20, count 0 2006.257.06:39:33.86#ibcon#read 5, iclass 20, count 0 2006.257.06:39:33.86#ibcon#about to read 6, iclass 20, count 0 2006.257.06:39:33.86#ibcon#read 6, iclass 20, count 0 2006.257.06:39:33.86#ibcon#end of sib2, iclass 20, count 0 2006.257.06:39:33.86#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:39:33.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:39:33.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:39:33.86#ibcon#*before write, iclass 20, count 0 2006.257.06:39:33.86#ibcon#enter sib2, iclass 20, count 0 2006.257.06:39:33.86#ibcon#flushed, iclass 20, count 0 2006.257.06:39:33.86#ibcon#about to write, iclass 20, count 0 2006.257.06:39:33.86#ibcon#wrote, iclass 20, count 0 2006.257.06:39:33.86#ibcon#about to read 3, iclass 20, count 0 2006.257.06:39:33.90#ibcon#read 3, iclass 20, count 0 2006.257.06:39:33.90#ibcon#about to read 4, iclass 20, count 0 2006.257.06:39:33.90#ibcon#read 4, iclass 20, count 0 2006.257.06:39:33.90#ibcon#about to read 5, iclass 20, count 0 2006.257.06:39:33.90#ibcon#read 5, iclass 20, count 0 2006.257.06:39:33.90#ibcon#about to read 6, iclass 20, count 0 2006.257.06:39:33.90#ibcon#read 6, iclass 20, count 0 2006.257.06:39:33.90#ibcon#end of sib2, iclass 20, count 0 2006.257.06:39:33.90#ibcon#*after write, iclass 20, count 0 2006.257.06:39:33.90#ibcon#*before return 0, iclass 20, count 0 2006.257.06:39:33.90#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:33.90#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:39:33.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:39:33.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:39:33.91$vck44/vb=7,4 2006.257.06:39:33.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.06:39:33.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.06:39:33.91#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:33.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:33.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:33.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:33.95#ibcon#enter wrdev, iclass 22, count 2 2006.257.06:39:33.95#ibcon#first serial, iclass 22, count 2 2006.257.06:39:33.95#ibcon#enter sib2, iclass 22, count 2 2006.257.06:39:33.95#ibcon#flushed, iclass 22, count 2 2006.257.06:39:33.95#ibcon#about to write, iclass 22, count 2 2006.257.06:39:33.95#ibcon#wrote, iclass 22, count 2 2006.257.06:39:33.95#ibcon#about to read 3, iclass 22, count 2 2006.257.06:39:33.97#ibcon#read 3, iclass 22, count 2 2006.257.06:39:33.97#ibcon#about to read 4, iclass 22, count 2 2006.257.06:39:33.97#ibcon#read 4, iclass 22, count 2 2006.257.06:39:33.97#ibcon#about to read 5, iclass 22, count 2 2006.257.06:39:33.97#ibcon#read 5, iclass 22, count 2 2006.257.06:39:33.97#ibcon#about to read 6, iclass 22, count 2 2006.257.06:39:33.97#ibcon#read 6, iclass 22, count 2 2006.257.06:39:33.97#ibcon#end of sib2, iclass 22, count 2 2006.257.06:39:33.97#ibcon#*mode == 0, iclass 22, count 2 2006.257.06:39:33.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.06:39:33.97#ibcon#[27=AT07-04\r\n] 2006.257.06:39:33.97#ibcon#*before write, iclass 22, count 2 2006.257.06:39:33.97#ibcon#enter sib2, iclass 22, count 2 2006.257.06:39:33.97#ibcon#flushed, iclass 22, count 2 2006.257.06:39:33.97#ibcon#about to write, iclass 22, count 2 2006.257.06:39:33.97#ibcon#wrote, iclass 22, count 2 2006.257.06:39:33.97#ibcon#about to read 3, iclass 22, count 2 2006.257.06:39:34.00#ibcon#read 3, iclass 22, count 2 2006.257.06:39:34.00#ibcon#about to read 4, iclass 22, count 2 2006.257.06:39:34.00#ibcon#read 4, iclass 22, count 2 2006.257.06:39:34.00#ibcon#about to read 5, iclass 22, count 2 2006.257.06:39:34.00#ibcon#read 5, iclass 22, count 2 2006.257.06:39:34.00#ibcon#about to read 6, iclass 22, count 2 2006.257.06:39:34.00#ibcon#read 6, iclass 22, count 2 2006.257.06:39:34.00#ibcon#end of sib2, iclass 22, count 2 2006.257.06:39:34.00#ibcon#*after write, iclass 22, count 2 2006.257.06:39:34.00#ibcon#*before return 0, iclass 22, count 2 2006.257.06:39:34.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:34.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:39:34.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.06:39:34.00#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:34.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:34.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:34.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:34.12#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:39:34.12#ibcon#first serial, iclass 22, count 0 2006.257.06:39:34.12#ibcon#enter sib2, iclass 22, count 0 2006.257.06:39:34.12#ibcon#flushed, iclass 22, count 0 2006.257.06:39:34.12#ibcon#about to write, iclass 22, count 0 2006.257.06:39:34.12#ibcon#wrote, iclass 22, count 0 2006.257.06:39:34.12#ibcon#about to read 3, iclass 22, count 0 2006.257.06:39:34.14#ibcon#read 3, iclass 22, count 0 2006.257.06:39:34.14#ibcon#about to read 4, iclass 22, count 0 2006.257.06:39:34.14#ibcon#read 4, iclass 22, count 0 2006.257.06:39:34.14#ibcon#about to read 5, iclass 22, count 0 2006.257.06:39:34.14#ibcon#read 5, iclass 22, count 0 2006.257.06:39:34.14#ibcon#about to read 6, iclass 22, count 0 2006.257.06:39:34.14#ibcon#read 6, iclass 22, count 0 2006.257.06:39:34.14#ibcon#end of sib2, iclass 22, count 0 2006.257.06:39:34.14#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:39:34.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:39:34.14#ibcon#[27=USB\r\n] 2006.257.06:39:34.14#ibcon#*before write, iclass 22, count 0 2006.257.06:39:34.14#ibcon#enter sib2, iclass 22, count 0 2006.257.06:39:34.14#ibcon#flushed, iclass 22, count 0 2006.257.06:39:34.14#ibcon#about to write, iclass 22, count 0 2006.257.06:39:34.14#ibcon#wrote, iclass 22, count 0 2006.257.06:39:34.14#ibcon#about to read 3, iclass 22, count 0 2006.257.06:39:34.17#ibcon#read 3, iclass 22, count 0 2006.257.06:39:34.17#ibcon#about to read 4, iclass 22, count 0 2006.257.06:39:34.17#ibcon#read 4, iclass 22, count 0 2006.257.06:39:34.17#ibcon#about to read 5, iclass 22, count 0 2006.257.06:39:34.17#ibcon#read 5, iclass 22, count 0 2006.257.06:39:34.17#ibcon#about to read 6, iclass 22, count 0 2006.257.06:39:34.17#ibcon#read 6, iclass 22, count 0 2006.257.06:39:34.17#ibcon#end of sib2, iclass 22, count 0 2006.257.06:39:34.17#ibcon#*after write, iclass 22, count 0 2006.257.06:39:34.17#ibcon#*before return 0, iclass 22, count 0 2006.257.06:39:34.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:34.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:39:34.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:39:34.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:39:34.18$vck44/vblo=8,744.99 2006.257.06:39:34.18#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.06:39:34.18#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.06:39:34.18#ibcon#ireg 17 cls_cnt 0 2006.257.06:39:34.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:34.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:34.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:34.18#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:39:34.18#ibcon#first serial, iclass 24, count 0 2006.257.06:39:34.18#ibcon#enter sib2, iclass 24, count 0 2006.257.06:39:34.18#ibcon#flushed, iclass 24, count 0 2006.257.06:39:34.18#ibcon#about to write, iclass 24, count 0 2006.257.06:39:34.18#ibcon#wrote, iclass 24, count 0 2006.257.06:39:34.18#ibcon#about to read 3, iclass 24, count 0 2006.257.06:39:34.19#ibcon#read 3, iclass 24, count 0 2006.257.06:39:34.19#ibcon#about to read 4, iclass 24, count 0 2006.257.06:39:34.19#ibcon#read 4, iclass 24, count 0 2006.257.06:39:34.19#ibcon#about to read 5, iclass 24, count 0 2006.257.06:39:34.19#ibcon#read 5, iclass 24, count 0 2006.257.06:39:34.19#ibcon#about to read 6, iclass 24, count 0 2006.257.06:39:34.19#ibcon#read 6, iclass 24, count 0 2006.257.06:39:34.19#ibcon#end of sib2, iclass 24, count 0 2006.257.06:39:34.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:39:34.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:39:34.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:39:34.19#ibcon#*before write, iclass 24, count 0 2006.257.06:39:34.19#ibcon#enter sib2, iclass 24, count 0 2006.257.06:39:34.19#ibcon#flushed, iclass 24, count 0 2006.257.06:39:34.19#ibcon#about to write, iclass 24, count 0 2006.257.06:39:34.19#ibcon#wrote, iclass 24, count 0 2006.257.06:39:34.19#ibcon#about to read 3, iclass 24, count 0 2006.257.06:39:34.23#ibcon#read 3, iclass 24, count 0 2006.257.06:39:34.23#ibcon#about to read 4, iclass 24, count 0 2006.257.06:39:34.23#ibcon#read 4, iclass 24, count 0 2006.257.06:39:34.23#ibcon#about to read 5, iclass 24, count 0 2006.257.06:39:34.23#ibcon#read 5, iclass 24, count 0 2006.257.06:39:34.23#ibcon#about to read 6, iclass 24, count 0 2006.257.06:39:34.23#ibcon#read 6, iclass 24, count 0 2006.257.06:39:34.23#ibcon#end of sib2, iclass 24, count 0 2006.257.06:39:34.23#ibcon#*after write, iclass 24, count 0 2006.257.06:39:34.23#ibcon#*before return 0, iclass 24, count 0 2006.257.06:39:34.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:34.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:39:34.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:39:34.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:39:34.24$vck44/vb=8,4 2006.257.06:39:34.24#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.06:39:34.24#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.06:39:34.24#ibcon#ireg 11 cls_cnt 2 2006.257.06:39:34.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:34.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:34.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:34.28#ibcon#enter wrdev, iclass 26, count 2 2006.257.06:39:34.28#ibcon#first serial, iclass 26, count 2 2006.257.06:39:34.28#ibcon#enter sib2, iclass 26, count 2 2006.257.06:39:34.28#ibcon#flushed, iclass 26, count 2 2006.257.06:39:34.28#ibcon#about to write, iclass 26, count 2 2006.257.06:39:34.28#ibcon#wrote, iclass 26, count 2 2006.257.06:39:34.28#ibcon#about to read 3, iclass 26, count 2 2006.257.06:39:34.30#ibcon#read 3, iclass 26, count 2 2006.257.06:39:34.30#ibcon#about to read 4, iclass 26, count 2 2006.257.06:39:34.30#ibcon#read 4, iclass 26, count 2 2006.257.06:39:34.30#ibcon#about to read 5, iclass 26, count 2 2006.257.06:39:34.30#ibcon#read 5, iclass 26, count 2 2006.257.06:39:34.30#ibcon#about to read 6, iclass 26, count 2 2006.257.06:39:34.30#ibcon#read 6, iclass 26, count 2 2006.257.06:39:34.30#ibcon#end of sib2, iclass 26, count 2 2006.257.06:39:34.30#ibcon#*mode == 0, iclass 26, count 2 2006.257.06:39:34.30#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.06:39:34.30#ibcon#[27=AT08-04\r\n] 2006.257.06:39:34.30#ibcon#*before write, iclass 26, count 2 2006.257.06:39:34.30#ibcon#enter sib2, iclass 26, count 2 2006.257.06:39:34.30#ibcon#flushed, iclass 26, count 2 2006.257.06:39:34.30#ibcon#about to write, iclass 26, count 2 2006.257.06:39:34.30#ibcon#wrote, iclass 26, count 2 2006.257.06:39:34.30#ibcon#about to read 3, iclass 26, count 2 2006.257.06:39:34.33#ibcon#read 3, iclass 26, count 2 2006.257.06:39:34.33#ibcon#about to read 4, iclass 26, count 2 2006.257.06:39:34.33#ibcon#read 4, iclass 26, count 2 2006.257.06:39:34.33#ibcon#about to read 5, iclass 26, count 2 2006.257.06:39:34.33#ibcon#read 5, iclass 26, count 2 2006.257.06:39:34.33#ibcon#about to read 6, iclass 26, count 2 2006.257.06:39:34.33#ibcon#read 6, iclass 26, count 2 2006.257.06:39:34.33#ibcon#end of sib2, iclass 26, count 2 2006.257.06:39:34.33#ibcon#*after write, iclass 26, count 2 2006.257.06:39:34.33#ibcon#*before return 0, iclass 26, count 2 2006.257.06:39:34.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:34.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:39:34.33#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.06:39:34.33#ibcon#ireg 7 cls_cnt 0 2006.257.06:39:34.33#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:34.45#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:34.45#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:34.45#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:39:34.45#ibcon#first serial, iclass 26, count 0 2006.257.06:39:34.45#ibcon#enter sib2, iclass 26, count 0 2006.257.06:39:34.45#ibcon#flushed, iclass 26, count 0 2006.257.06:39:34.45#ibcon#about to write, iclass 26, count 0 2006.257.06:39:34.45#ibcon#wrote, iclass 26, count 0 2006.257.06:39:34.45#ibcon#about to read 3, iclass 26, count 0 2006.257.06:39:34.47#ibcon#read 3, iclass 26, count 0 2006.257.06:39:34.47#ibcon#about to read 4, iclass 26, count 0 2006.257.06:39:34.47#ibcon#read 4, iclass 26, count 0 2006.257.06:39:34.47#ibcon#about to read 5, iclass 26, count 0 2006.257.06:39:34.47#ibcon#read 5, iclass 26, count 0 2006.257.06:39:34.47#ibcon#about to read 6, iclass 26, count 0 2006.257.06:39:34.47#ibcon#read 6, iclass 26, count 0 2006.257.06:39:34.47#ibcon#end of sib2, iclass 26, count 0 2006.257.06:39:34.47#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:39:34.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:39:34.47#ibcon#[27=USB\r\n] 2006.257.06:39:34.47#ibcon#*before write, iclass 26, count 0 2006.257.06:39:34.47#ibcon#enter sib2, iclass 26, count 0 2006.257.06:39:34.47#ibcon#flushed, iclass 26, count 0 2006.257.06:39:34.47#ibcon#about to write, iclass 26, count 0 2006.257.06:39:34.47#ibcon#wrote, iclass 26, count 0 2006.257.06:39:34.47#ibcon#about to read 3, iclass 26, count 0 2006.257.06:39:34.50#ibcon#read 3, iclass 26, count 0 2006.257.06:39:34.50#ibcon#about to read 4, iclass 26, count 0 2006.257.06:39:34.50#ibcon#read 4, iclass 26, count 0 2006.257.06:39:34.50#ibcon#about to read 5, iclass 26, count 0 2006.257.06:39:34.50#ibcon#read 5, iclass 26, count 0 2006.257.06:39:34.50#ibcon#about to read 6, iclass 26, count 0 2006.257.06:39:34.50#ibcon#read 6, iclass 26, count 0 2006.257.06:39:34.50#ibcon#end of sib2, iclass 26, count 0 2006.257.06:39:34.50#ibcon#*after write, iclass 26, count 0 2006.257.06:39:34.50#ibcon#*before return 0, iclass 26, count 0 2006.257.06:39:34.50#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:34.50#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:39:34.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:39:34.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:39:34.51$vck44/vabw=wide 2006.257.06:39:34.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.06:39:34.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.06:39:34.51#ibcon#ireg 8 cls_cnt 0 2006.257.06:39:34.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:34.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:34.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:34.51#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:39:34.51#ibcon#first serial, iclass 28, count 0 2006.257.06:39:34.51#ibcon#enter sib2, iclass 28, count 0 2006.257.06:39:34.51#ibcon#flushed, iclass 28, count 0 2006.257.06:39:34.51#ibcon#about to write, iclass 28, count 0 2006.257.06:39:34.51#ibcon#wrote, iclass 28, count 0 2006.257.06:39:34.51#ibcon#about to read 3, iclass 28, count 0 2006.257.06:39:34.52#ibcon#read 3, iclass 28, count 0 2006.257.06:39:34.52#ibcon#about to read 4, iclass 28, count 0 2006.257.06:39:34.52#ibcon#read 4, iclass 28, count 0 2006.257.06:39:34.52#ibcon#about to read 5, iclass 28, count 0 2006.257.06:39:34.52#ibcon#read 5, iclass 28, count 0 2006.257.06:39:34.52#ibcon#about to read 6, iclass 28, count 0 2006.257.06:39:34.52#ibcon#read 6, iclass 28, count 0 2006.257.06:39:34.52#ibcon#end of sib2, iclass 28, count 0 2006.257.06:39:34.52#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:39:34.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:39:34.52#ibcon#[25=BW32\r\n] 2006.257.06:39:34.52#ibcon#*before write, iclass 28, count 0 2006.257.06:39:34.52#ibcon#enter sib2, iclass 28, count 0 2006.257.06:39:34.52#ibcon#flushed, iclass 28, count 0 2006.257.06:39:34.52#ibcon#about to write, iclass 28, count 0 2006.257.06:39:34.52#ibcon#wrote, iclass 28, count 0 2006.257.06:39:34.52#ibcon#about to read 3, iclass 28, count 0 2006.257.06:39:34.55#ibcon#read 3, iclass 28, count 0 2006.257.06:39:34.55#ibcon#about to read 4, iclass 28, count 0 2006.257.06:39:34.55#ibcon#read 4, iclass 28, count 0 2006.257.06:39:34.55#ibcon#about to read 5, iclass 28, count 0 2006.257.06:39:34.55#ibcon#read 5, iclass 28, count 0 2006.257.06:39:34.55#ibcon#about to read 6, iclass 28, count 0 2006.257.06:39:34.55#ibcon#read 6, iclass 28, count 0 2006.257.06:39:34.55#ibcon#end of sib2, iclass 28, count 0 2006.257.06:39:34.55#ibcon#*after write, iclass 28, count 0 2006.257.06:39:34.55#ibcon#*before return 0, iclass 28, count 0 2006.257.06:39:34.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:34.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:39:34.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:39:34.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:39:34.56$vck44/vbbw=wide 2006.257.06:39:34.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.06:39:34.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.06:39:34.56#ibcon#ireg 8 cls_cnt 0 2006.257.06:39:34.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:39:34.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:39:34.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:39:34.61#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:39:34.61#ibcon#first serial, iclass 30, count 0 2006.257.06:39:34.61#ibcon#enter sib2, iclass 30, count 0 2006.257.06:39:34.61#ibcon#flushed, iclass 30, count 0 2006.257.06:39:34.61#ibcon#about to write, iclass 30, count 0 2006.257.06:39:34.61#ibcon#wrote, iclass 30, count 0 2006.257.06:39:34.61#ibcon#about to read 3, iclass 30, count 0 2006.257.06:39:34.63#ibcon#read 3, iclass 30, count 0 2006.257.06:39:34.63#ibcon#about to read 4, iclass 30, count 0 2006.257.06:39:34.63#ibcon#read 4, iclass 30, count 0 2006.257.06:39:34.63#ibcon#about to read 5, iclass 30, count 0 2006.257.06:39:34.63#ibcon#read 5, iclass 30, count 0 2006.257.06:39:34.63#ibcon#about to read 6, iclass 30, count 0 2006.257.06:39:34.63#ibcon#read 6, iclass 30, count 0 2006.257.06:39:34.63#ibcon#end of sib2, iclass 30, count 0 2006.257.06:39:34.63#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:39:34.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:39:34.63#ibcon#[27=BW32\r\n] 2006.257.06:39:34.63#ibcon#*before write, iclass 30, count 0 2006.257.06:39:34.63#ibcon#enter sib2, iclass 30, count 0 2006.257.06:39:34.63#ibcon#flushed, iclass 30, count 0 2006.257.06:39:34.63#ibcon#about to write, iclass 30, count 0 2006.257.06:39:34.63#ibcon#wrote, iclass 30, count 0 2006.257.06:39:34.63#ibcon#about to read 3, iclass 30, count 0 2006.257.06:39:34.66#ibcon#read 3, iclass 30, count 0 2006.257.06:39:34.66#ibcon#about to read 4, iclass 30, count 0 2006.257.06:39:34.66#ibcon#read 4, iclass 30, count 0 2006.257.06:39:34.66#ibcon#about to read 5, iclass 30, count 0 2006.257.06:39:34.66#ibcon#read 5, iclass 30, count 0 2006.257.06:39:34.66#ibcon#about to read 6, iclass 30, count 0 2006.257.06:39:34.66#ibcon#read 6, iclass 30, count 0 2006.257.06:39:34.66#ibcon#end of sib2, iclass 30, count 0 2006.257.06:39:34.66#ibcon#*after write, iclass 30, count 0 2006.257.06:39:34.66#ibcon#*before return 0, iclass 30, count 0 2006.257.06:39:34.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:39:34.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:39:34.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:39:34.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:39:34.67$setupk4/ifdk4 2006.257.06:39:34.67$ifdk4/lo= 2006.257.06:39:34.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:39:34.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:39:34.67$ifdk4/patch= 2006.257.06:39:34.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:39:34.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:39:34.67$setupk4/!*+20s 2006.257.06:39:42.29#abcon#<5=/15 0.6 2.3 20.67 891012.3\r\n> 2006.257.06:39:42.31#abcon#{5=INTERFACE CLEAR} 2006.257.06:39:42.37#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:39:49.33$setupk4/"tpicd 2006.257.06:39:49.33$setupk4/echo=off 2006.257.06:39:49.33$setupk4/xlog=off 2006.257.06:39:49.34:!2006.257.06:40:46 2006.257.06:39:53.14#trakl#Source acquired 2006.257.06:39:55.15#flagr#flagr/antenna,acquired 2006.257.06:40:46.01:preob 2006.257.06:40:47.14/onsource/TRACKING 2006.257.06:40:47.15:!2006.257.06:40:56 2006.257.06:40:56.01:"tape 2006.257.06:40:56.01:"st=record 2006.257.06:40:56.02:data_valid=on 2006.257.06:40:56.02:midob 2006.257.06:40:57.14/onsource/TRACKING 2006.257.06:40:57.15/wx/20.67,1012.3,88 2006.257.06:40:57.36/cable/+6.4785E-03 2006.257.06:40:58.45/va/01,08,usb,yes,31,33 2006.257.06:40:58.45/va/02,07,usb,yes,33,34 2006.257.06:40:58.45/va/03,08,usb,yes,30,32 2006.257.06:40:58.45/va/04,07,usb,yes,34,36 2006.257.06:40:58.45/va/05,04,usb,yes,31,31 2006.257.06:40:58.45/va/06,04,usb,yes,34,34 2006.257.06:40:58.45/va/07,04,usb,yes,35,36 2006.257.06:40:58.45/va/08,04,usb,yes,29,36 2006.257.06:40:58.68/valo/01,524.99,yes,locked 2006.257.06:40:58.68/valo/02,534.99,yes,locked 2006.257.06:40:58.68/valo/03,564.99,yes,locked 2006.257.06:40:58.68/valo/04,624.99,yes,locked 2006.257.06:40:58.68/valo/05,734.99,yes,locked 2006.257.06:40:58.68/valo/06,814.99,yes,locked 2006.257.06:40:58.68/valo/07,864.99,yes,locked 2006.257.06:40:58.68/valo/08,884.99,yes,locked 2006.257.06:40:59.77/vb/01,04,usb,yes,30,28 2006.257.06:40:59.77/vb/02,05,usb,yes,29,29 2006.257.06:40:59.77/vb/03,04,usb,yes,30,33 2006.257.06:40:59.77/vb/04,05,usb,yes,30,29 2006.257.06:40:59.77/vb/05,04,usb,yes,27,29 2006.257.06:40:59.77/vb/06,04,usb,yes,31,27 2006.257.06:40:59.77/vb/07,04,usb,yes,31,31 2006.257.06:40:59.77/vb/08,04,usb,yes,28,32 2006.257.06:41:00.00/vblo/01,629.99,yes,locked 2006.257.06:41:00.00/vblo/02,634.99,yes,locked 2006.257.06:41:00.00/vblo/03,649.99,yes,locked 2006.257.06:41:00.00/vblo/04,679.99,yes,locked 2006.257.06:41:00.00/vblo/05,709.99,yes,locked 2006.257.06:41:00.00/vblo/06,719.99,yes,locked 2006.257.06:41:00.00/vblo/07,734.99,yes,locked 2006.257.06:41:00.00/vblo/08,744.99,yes,locked 2006.257.06:41:00.15/vabw/8 2006.257.06:41:00.30/vbbw/8 2006.257.06:41:00.39/xfe/off,on,16.7 2006.257.06:41:00.76/ifatt/23,28,28,28 2006.257.06:41:01.07/fmout-gps/S +4.47E-07 2006.257.06:41:01.11:!2006.257.06:41:36 2006.257.06:41:36.00:data_valid=off 2006.257.06:41:36.00:"et 2006.257.06:41:36.01:!+3s 2006.257.06:41:39.03:"tape 2006.257.06:41:39.03:postob 2006.257.06:41:39.16/cable/+6.4771E-03 2006.257.06:41:39.16/wx/20.66,1012.3,88 2006.257.06:41:39.22/fmout-gps/S +4.47E-07 2006.257.06:41:39.22:scan_name=257-0642,jd0609,50 2006.257.06:41:39.23:source=1611+343,161341.06,341247.9,2000.0,cw 2006.257.06:41:40.13#flagr#flagr/antenna,new-source 2006.257.06:41:40.14:checkk5 2006.257.06:41:40.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:41:40.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:41:41.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:41:41.72/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:41:42.11/chk_obsdata//k5ts1/T2570640??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:41:42.51/chk_obsdata//k5ts2/T2570640??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:41:42.94/chk_obsdata//k5ts3/T2570640??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:41:43.32/chk_obsdata//k5ts4/T2570640??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:41:44.06/k5log//k5ts1_log_newline 2006.257.06:41:44.80/k5log//k5ts2_log_newline 2006.257.06:41:45.52/k5log//k5ts3_log_newline 2006.257.06:41:46.24/k5log//k5ts4_log_newline 2006.257.06:41:46.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:41:46.26:setupk4=1 2006.257.06:41:46.26$setupk4/echo=on 2006.257.06:41:46.26$setupk4/pcalon 2006.257.06:41:46.26$pcalon/"no phase cal control is implemented here 2006.257.06:41:46.26$setupk4/"tpicd=stop 2006.257.06:41:46.26$setupk4/"rec=synch_on 2006.257.06:41:46.26$setupk4/"rec_mode=128 2006.257.06:41:46.26$setupk4/!* 2006.257.06:41:46.26$setupk4/recpk4 2006.257.06:41:46.26$recpk4/recpatch= 2006.257.06:41:46.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:41:46.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:41:46.27$setupk4/vck44 2006.257.06:41:46.27$vck44/valo=1,524.99 2006.257.06:41:46.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.06:41:46.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.06:41:46.27#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:46.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:46.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:46.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:46.27#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:41:46.27#ibcon#first serial, iclass 15, count 0 2006.257.06:41:46.27#ibcon#enter sib2, iclass 15, count 0 2006.257.06:41:46.27#ibcon#flushed, iclass 15, count 0 2006.257.06:41:46.27#ibcon#about to write, iclass 15, count 0 2006.257.06:41:46.27#ibcon#wrote, iclass 15, count 0 2006.257.06:41:46.27#ibcon#about to read 3, iclass 15, count 0 2006.257.06:41:46.28#ibcon#read 3, iclass 15, count 0 2006.257.06:41:46.28#ibcon#about to read 4, iclass 15, count 0 2006.257.06:41:46.28#ibcon#read 4, iclass 15, count 0 2006.257.06:41:46.28#ibcon#about to read 5, iclass 15, count 0 2006.257.06:41:46.28#ibcon#read 5, iclass 15, count 0 2006.257.06:41:46.28#ibcon#about to read 6, iclass 15, count 0 2006.257.06:41:46.28#ibcon#read 6, iclass 15, count 0 2006.257.06:41:46.28#ibcon#end of sib2, iclass 15, count 0 2006.257.06:41:46.28#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:41:46.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:41:46.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:41:46.28#ibcon#*before write, iclass 15, count 0 2006.257.06:41:46.28#ibcon#enter sib2, iclass 15, count 0 2006.257.06:41:46.28#ibcon#flushed, iclass 15, count 0 2006.257.06:41:46.28#ibcon#about to write, iclass 15, count 0 2006.257.06:41:46.28#ibcon#wrote, iclass 15, count 0 2006.257.06:41:46.28#ibcon#about to read 3, iclass 15, count 0 2006.257.06:41:46.33#ibcon#read 3, iclass 15, count 0 2006.257.06:41:46.33#ibcon#about to read 4, iclass 15, count 0 2006.257.06:41:46.33#ibcon#read 4, iclass 15, count 0 2006.257.06:41:46.33#ibcon#about to read 5, iclass 15, count 0 2006.257.06:41:46.33#ibcon#read 5, iclass 15, count 0 2006.257.06:41:46.33#ibcon#about to read 6, iclass 15, count 0 2006.257.06:41:46.33#ibcon#read 6, iclass 15, count 0 2006.257.06:41:46.33#ibcon#end of sib2, iclass 15, count 0 2006.257.06:41:46.33#ibcon#*after write, iclass 15, count 0 2006.257.06:41:46.33#ibcon#*before return 0, iclass 15, count 0 2006.257.06:41:46.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:46.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:46.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:41:46.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:41:46.33$vck44/va=1,8 2006.257.06:41:46.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.06:41:46.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.06:41:46.33#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:46.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:46.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:46.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:46.33#ibcon#enter wrdev, iclass 17, count 2 2006.257.06:41:46.33#ibcon#first serial, iclass 17, count 2 2006.257.06:41:46.33#ibcon#enter sib2, iclass 17, count 2 2006.257.06:41:46.33#ibcon#flushed, iclass 17, count 2 2006.257.06:41:46.33#ibcon#about to write, iclass 17, count 2 2006.257.06:41:46.33#ibcon#wrote, iclass 17, count 2 2006.257.06:41:46.33#ibcon#about to read 3, iclass 17, count 2 2006.257.06:41:46.35#ibcon#read 3, iclass 17, count 2 2006.257.06:41:46.35#ibcon#about to read 4, iclass 17, count 2 2006.257.06:41:46.35#ibcon#read 4, iclass 17, count 2 2006.257.06:41:46.35#ibcon#about to read 5, iclass 17, count 2 2006.257.06:41:46.35#ibcon#read 5, iclass 17, count 2 2006.257.06:41:46.35#ibcon#about to read 6, iclass 17, count 2 2006.257.06:41:46.35#ibcon#read 6, iclass 17, count 2 2006.257.06:41:46.35#ibcon#end of sib2, iclass 17, count 2 2006.257.06:41:46.35#ibcon#*mode == 0, iclass 17, count 2 2006.257.06:41:46.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.06:41:46.35#ibcon#[25=AT01-08\r\n] 2006.257.06:41:46.35#ibcon#*before write, iclass 17, count 2 2006.257.06:41:46.35#ibcon#enter sib2, iclass 17, count 2 2006.257.06:41:46.35#ibcon#flushed, iclass 17, count 2 2006.257.06:41:46.35#ibcon#about to write, iclass 17, count 2 2006.257.06:41:46.35#ibcon#wrote, iclass 17, count 2 2006.257.06:41:46.35#ibcon#about to read 3, iclass 17, count 2 2006.257.06:41:46.38#ibcon#read 3, iclass 17, count 2 2006.257.06:41:46.38#ibcon#about to read 4, iclass 17, count 2 2006.257.06:41:46.38#ibcon#read 4, iclass 17, count 2 2006.257.06:41:46.38#ibcon#about to read 5, iclass 17, count 2 2006.257.06:41:46.38#ibcon#read 5, iclass 17, count 2 2006.257.06:41:46.38#ibcon#about to read 6, iclass 17, count 2 2006.257.06:41:46.38#ibcon#read 6, iclass 17, count 2 2006.257.06:41:46.38#ibcon#end of sib2, iclass 17, count 2 2006.257.06:41:46.38#ibcon#*after write, iclass 17, count 2 2006.257.06:41:46.38#ibcon#*before return 0, iclass 17, count 2 2006.257.06:41:46.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:46.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:46.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.06:41:46.38#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:46.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:46.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:46.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:46.50#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:41:46.50#ibcon#first serial, iclass 17, count 0 2006.257.06:41:46.50#ibcon#enter sib2, iclass 17, count 0 2006.257.06:41:46.50#ibcon#flushed, iclass 17, count 0 2006.257.06:41:46.50#ibcon#about to write, iclass 17, count 0 2006.257.06:41:46.50#ibcon#wrote, iclass 17, count 0 2006.257.06:41:46.50#ibcon#about to read 3, iclass 17, count 0 2006.257.06:41:46.52#ibcon#read 3, iclass 17, count 0 2006.257.06:41:46.52#ibcon#about to read 4, iclass 17, count 0 2006.257.06:41:46.52#ibcon#read 4, iclass 17, count 0 2006.257.06:41:46.52#ibcon#about to read 5, iclass 17, count 0 2006.257.06:41:46.52#ibcon#read 5, iclass 17, count 0 2006.257.06:41:46.52#ibcon#about to read 6, iclass 17, count 0 2006.257.06:41:46.52#ibcon#read 6, iclass 17, count 0 2006.257.06:41:46.52#ibcon#end of sib2, iclass 17, count 0 2006.257.06:41:46.52#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:41:46.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:41:46.52#ibcon#[25=USB\r\n] 2006.257.06:41:46.52#ibcon#*before write, iclass 17, count 0 2006.257.06:41:46.52#ibcon#enter sib2, iclass 17, count 0 2006.257.06:41:46.52#ibcon#flushed, iclass 17, count 0 2006.257.06:41:46.52#ibcon#about to write, iclass 17, count 0 2006.257.06:41:46.52#ibcon#wrote, iclass 17, count 0 2006.257.06:41:46.52#ibcon#about to read 3, iclass 17, count 0 2006.257.06:41:46.55#ibcon#read 3, iclass 17, count 0 2006.257.06:41:46.55#ibcon#about to read 4, iclass 17, count 0 2006.257.06:41:46.55#ibcon#read 4, iclass 17, count 0 2006.257.06:41:46.55#ibcon#about to read 5, iclass 17, count 0 2006.257.06:41:46.55#ibcon#read 5, iclass 17, count 0 2006.257.06:41:46.55#ibcon#about to read 6, iclass 17, count 0 2006.257.06:41:46.55#ibcon#read 6, iclass 17, count 0 2006.257.06:41:46.55#ibcon#end of sib2, iclass 17, count 0 2006.257.06:41:46.55#ibcon#*after write, iclass 17, count 0 2006.257.06:41:46.55#ibcon#*before return 0, iclass 17, count 0 2006.257.06:41:46.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:46.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:46.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:41:46.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:41:46.55$vck44/valo=2,534.99 2006.257.06:41:46.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.06:41:46.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.06:41:46.55#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:46.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:46.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:46.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:46.55#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:41:46.55#ibcon#first serial, iclass 19, count 0 2006.257.06:41:46.55#ibcon#enter sib2, iclass 19, count 0 2006.257.06:41:46.55#ibcon#flushed, iclass 19, count 0 2006.257.06:41:46.55#ibcon#about to write, iclass 19, count 0 2006.257.06:41:46.55#ibcon#wrote, iclass 19, count 0 2006.257.06:41:46.55#ibcon#about to read 3, iclass 19, count 0 2006.257.06:41:46.57#ibcon#read 3, iclass 19, count 0 2006.257.06:41:46.57#ibcon#about to read 4, iclass 19, count 0 2006.257.06:41:46.57#ibcon#read 4, iclass 19, count 0 2006.257.06:41:46.57#ibcon#about to read 5, iclass 19, count 0 2006.257.06:41:46.57#ibcon#read 5, iclass 19, count 0 2006.257.06:41:46.57#ibcon#about to read 6, iclass 19, count 0 2006.257.06:41:46.57#ibcon#read 6, iclass 19, count 0 2006.257.06:41:46.57#ibcon#end of sib2, iclass 19, count 0 2006.257.06:41:46.57#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:41:46.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:41:46.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:41:46.57#ibcon#*before write, iclass 19, count 0 2006.257.06:41:46.57#ibcon#enter sib2, iclass 19, count 0 2006.257.06:41:46.57#ibcon#flushed, iclass 19, count 0 2006.257.06:41:46.57#ibcon#about to write, iclass 19, count 0 2006.257.06:41:46.57#ibcon#wrote, iclass 19, count 0 2006.257.06:41:46.57#ibcon#about to read 3, iclass 19, count 0 2006.257.06:41:46.61#ibcon#read 3, iclass 19, count 0 2006.257.06:41:46.61#ibcon#about to read 4, iclass 19, count 0 2006.257.06:41:46.61#ibcon#read 4, iclass 19, count 0 2006.257.06:41:46.61#ibcon#about to read 5, iclass 19, count 0 2006.257.06:41:46.61#ibcon#read 5, iclass 19, count 0 2006.257.06:41:46.61#ibcon#about to read 6, iclass 19, count 0 2006.257.06:41:46.61#ibcon#read 6, iclass 19, count 0 2006.257.06:41:46.61#ibcon#end of sib2, iclass 19, count 0 2006.257.06:41:46.61#ibcon#*after write, iclass 19, count 0 2006.257.06:41:46.61#ibcon#*before return 0, iclass 19, count 0 2006.257.06:41:46.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:46.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:46.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:41:46.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:41:46.61$vck44/va=2,7 2006.257.06:41:46.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.06:41:46.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.06:41:46.61#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:46.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:46.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:46.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:46.67#ibcon#enter wrdev, iclass 21, count 2 2006.257.06:41:46.67#ibcon#first serial, iclass 21, count 2 2006.257.06:41:46.67#ibcon#enter sib2, iclass 21, count 2 2006.257.06:41:46.67#ibcon#flushed, iclass 21, count 2 2006.257.06:41:46.67#ibcon#about to write, iclass 21, count 2 2006.257.06:41:46.67#ibcon#wrote, iclass 21, count 2 2006.257.06:41:46.67#ibcon#about to read 3, iclass 21, count 2 2006.257.06:41:46.69#ibcon#read 3, iclass 21, count 2 2006.257.06:41:46.69#ibcon#about to read 4, iclass 21, count 2 2006.257.06:41:46.69#ibcon#read 4, iclass 21, count 2 2006.257.06:41:46.69#ibcon#about to read 5, iclass 21, count 2 2006.257.06:41:46.69#ibcon#read 5, iclass 21, count 2 2006.257.06:41:46.69#ibcon#about to read 6, iclass 21, count 2 2006.257.06:41:46.69#ibcon#read 6, iclass 21, count 2 2006.257.06:41:46.69#ibcon#end of sib2, iclass 21, count 2 2006.257.06:41:46.69#ibcon#*mode == 0, iclass 21, count 2 2006.257.06:41:46.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.06:41:46.69#ibcon#[25=AT02-07\r\n] 2006.257.06:41:46.69#ibcon#*before write, iclass 21, count 2 2006.257.06:41:46.69#ibcon#enter sib2, iclass 21, count 2 2006.257.06:41:46.69#ibcon#flushed, iclass 21, count 2 2006.257.06:41:46.69#ibcon#about to write, iclass 21, count 2 2006.257.06:41:46.69#ibcon#wrote, iclass 21, count 2 2006.257.06:41:46.69#ibcon#about to read 3, iclass 21, count 2 2006.257.06:41:46.72#ibcon#read 3, iclass 21, count 2 2006.257.06:41:46.72#ibcon#about to read 4, iclass 21, count 2 2006.257.06:41:46.72#ibcon#read 4, iclass 21, count 2 2006.257.06:41:46.72#ibcon#about to read 5, iclass 21, count 2 2006.257.06:41:46.72#ibcon#read 5, iclass 21, count 2 2006.257.06:41:46.72#ibcon#about to read 6, iclass 21, count 2 2006.257.06:41:46.72#ibcon#read 6, iclass 21, count 2 2006.257.06:41:46.72#ibcon#end of sib2, iclass 21, count 2 2006.257.06:41:46.72#ibcon#*after write, iclass 21, count 2 2006.257.06:41:46.72#ibcon#*before return 0, iclass 21, count 2 2006.257.06:41:46.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:46.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:46.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.06:41:46.72#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:46.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:46.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:46.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:46.84#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:41:46.84#ibcon#first serial, iclass 21, count 0 2006.257.06:41:46.84#ibcon#enter sib2, iclass 21, count 0 2006.257.06:41:46.84#ibcon#flushed, iclass 21, count 0 2006.257.06:41:46.84#ibcon#about to write, iclass 21, count 0 2006.257.06:41:46.84#ibcon#wrote, iclass 21, count 0 2006.257.06:41:46.84#ibcon#about to read 3, iclass 21, count 0 2006.257.06:41:46.86#ibcon#read 3, iclass 21, count 0 2006.257.06:41:46.86#ibcon#about to read 4, iclass 21, count 0 2006.257.06:41:46.86#ibcon#read 4, iclass 21, count 0 2006.257.06:41:46.86#ibcon#about to read 5, iclass 21, count 0 2006.257.06:41:46.86#ibcon#read 5, iclass 21, count 0 2006.257.06:41:46.86#ibcon#about to read 6, iclass 21, count 0 2006.257.06:41:46.86#ibcon#read 6, iclass 21, count 0 2006.257.06:41:46.86#ibcon#end of sib2, iclass 21, count 0 2006.257.06:41:46.86#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:41:46.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:41:46.86#ibcon#[25=USB\r\n] 2006.257.06:41:46.86#ibcon#*before write, iclass 21, count 0 2006.257.06:41:46.86#ibcon#enter sib2, iclass 21, count 0 2006.257.06:41:46.86#ibcon#flushed, iclass 21, count 0 2006.257.06:41:46.86#ibcon#about to write, iclass 21, count 0 2006.257.06:41:46.86#ibcon#wrote, iclass 21, count 0 2006.257.06:41:46.86#ibcon#about to read 3, iclass 21, count 0 2006.257.06:41:46.89#ibcon#read 3, iclass 21, count 0 2006.257.06:41:46.89#ibcon#about to read 4, iclass 21, count 0 2006.257.06:41:46.89#ibcon#read 4, iclass 21, count 0 2006.257.06:41:46.89#ibcon#about to read 5, iclass 21, count 0 2006.257.06:41:46.89#ibcon#read 5, iclass 21, count 0 2006.257.06:41:46.89#ibcon#about to read 6, iclass 21, count 0 2006.257.06:41:46.89#ibcon#read 6, iclass 21, count 0 2006.257.06:41:46.89#ibcon#end of sib2, iclass 21, count 0 2006.257.06:41:46.89#ibcon#*after write, iclass 21, count 0 2006.257.06:41:46.89#ibcon#*before return 0, iclass 21, count 0 2006.257.06:41:46.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:46.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:46.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:41:46.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:41:46.89$vck44/valo=3,564.99 2006.257.06:41:46.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.06:41:46.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.06:41:46.89#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:46.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:46.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:46.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:46.89#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:41:46.89#ibcon#first serial, iclass 23, count 0 2006.257.06:41:46.89#ibcon#enter sib2, iclass 23, count 0 2006.257.06:41:46.89#ibcon#flushed, iclass 23, count 0 2006.257.06:41:46.89#ibcon#about to write, iclass 23, count 0 2006.257.06:41:46.89#ibcon#wrote, iclass 23, count 0 2006.257.06:41:46.89#ibcon#about to read 3, iclass 23, count 0 2006.257.06:41:46.91#ibcon#read 3, iclass 23, count 0 2006.257.06:41:46.91#ibcon#about to read 4, iclass 23, count 0 2006.257.06:41:46.91#ibcon#read 4, iclass 23, count 0 2006.257.06:41:46.91#ibcon#about to read 5, iclass 23, count 0 2006.257.06:41:46.91#ibcon#read 5, iclass 23, count 0 2006.257.06:41:46.91#ibcon#about to read 6, iclass 23, count 0 2006.257.06:41:46.91#ibcon#read 6, iclass 23, count 0 2006.257.06:41:46.91#ibcon#end of sib2, iclass 23, count 0 2006.257.06:41:46.91#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:41:46.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:41:46.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:41:46.91#ibcon#*before write, iclass 23, count 0 2006.257.06:41:46.91#ibcon#enter sib2, iclass 23, count 0 2006.257.06:41:46.91#ibcon#flushed, iclass 23, count 0 2006.257.06:41:46.91#ibcon#about to write, iclass 23, count 0 2006.257.06:41:46.91#ibcon#wrote, iclass 23, count 0 2006.257.06:41:46.91#ibcon#about to read 3, iclass 23, count 0 2006.257.06:41:46.95#ibcon#read 3, iclass 23, count 0 2006.257.06:41:46.95#ibcon#about to read 4, iclass 23, count 0 2006.257.06:41:46.95#ibcon#read 4, iclass 23, count 0 2006.257.06:41:46.95#ibcon#about to read 5, iclass 23, count 0 2006.257.06:41:46.95#ibcon#read 5, iclass 23, count 0 2006.257.06:41:46.95#ibcon#about to read 6, iclass 23, count 0 2006.257.06:41:46.95#ibcon#read 6, iclass 23, count 0 2006.257.06:41:46.95#ibcon#end of sib2, iclass 23, count 0 2006.257.06:41:46.95#ibcon#*after write, iclass 23, count 0 2006.257.06:41:46.95#ibcon#*before return 0, iclass 23, count 0 2006.257.06:41:46.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:46.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:46.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:41:46.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:41:46.95$vck44/va=3,8 2006.257.06:41:46.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.06:41:46.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.06:41:46.95#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:46.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:47.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:47.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:47.01#ibcon#enter wrdev, iclass 25, count 2 2006.257.06:41:47.01#ibcon#first serial, iclass 25, count 2 2006.257.06:41:47.01#ibcon#enter sib2, iclass 25, count 2 2006.257.06:41:47.01#ibcon#flushed, iclass 25, count 2 2006.257.06:41:47.01#ibcon#about to write, iclass 25, count 2 2006.257.06:41:47.01#ibcon#wrote, iclass 25, count 2 2006.257.06:41:47.01#ibcon#about to read 3, iclass 25, count 2 2006.257.06:41:47.03#ibcon#read 3, iclass 25, count 2 2006.257.06:41:47.03#ibcon#about to read 4, iclass 25, count 2 2006.257.06:41:47.03#ibcon#read 4, iclass 25, count 2 2006.257.06:41:47.03#ibcon#about to read 5, iclass 25, count 2 2006.257.06:41:47.03#ibcon#read 5, iclass 25, count 2 2006.257.06:41:47.03#ibcon#about to read 6, iclass 25, count 2 2006.257.06:41:47.03#ibcon#read 6, iclass 25, count 2 2006.257.06:41:47.03#ibcon#end of sib2, iclass 25, count 2 2006.257.06:41:47.03#ibcon#*mode == 0, iclass 25, count 2 2006.257.06:41:47.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.06:41:47.03#ibcon#[25=AT03-08\r\n] 2006.257.06:41:47.03#ibcon#*before write, iclass 25, count 2 2006.257.06:41:47.03#ibcon#enter sib2, iclass 25, count 2 2006.257.06:41:47.03#ibcon#flushed, iclass 25, count 2 2006.257.06:41:47.03#ibcon#about to write, iclass 25, count 2 2006.257.06:41:47.03#ibcon#wrote, iclass 25, count 2 2006.257.06:41:47.03#ibcon#about to read 3, iclass 25, count 2 2006.257.06:41:47.06#ibcon#read 3, iclass 25, count 2 2006.257.06:41:47.06#ibcon#about to read 4, iclass 25, count 2 2006.257.06:41:47.06#ibcon#read 4, iclass 25, count 2 2006.257.06:41:47.06#ibcon#about to read 5, iclass 25, count 2 2006.257.06:41:47.06#ibcon#read 5, iclass 25, count 2 2006.257.06:41:47.06#ibcon#about to read 6, iclass 25, count 2 2006.257.06:41:47.06#ibcon#read 6, iclass 25, count 2 2006.257.06:41:47.06#ibcon#end of sib2, iclass 25, count 2 2006.257.06:41:47.06#ibcon#*after write, iclass 25, count 2 2006.257.06:41:47.06#ibcon#*before return 0, iclass 25, count 2 2006.257.06:41:47.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:47.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:47.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.06:41:47.06#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:47.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:47.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:47.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:47.18#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:41:47.18#ibcon#first serial, iclass 25, count 0 2006.257.06:41:47.18#ibcon#enter sib2, iclass 25, count 0 2006.257.06:41:47.18#ibcon#flushed, iclass 25, count 0 2006.257.06:41:47.18#ibcon#about to write, iclass 25, count 0 2006.257.06:41:47.18#ibcon#wrote, iclass 25, count 0 2006.257.06:41:47.18#ibcon#about to read 3, iclass 25, count 0 2006.257.06:41:47.20#ibcon#read 3, iclass 25, count 0 2006.257.06:41:47.20#ibcon#about to read 4, iclass 25, count 0 2006.257.06:41:47.20#ibcon#read 4, iclass 25, count 0 2006.257.06:41:47.20#ibcon#about to read 5, iclass 25, count 0 2006.257.06:41:47.20#ibcon#read 5, iclass 25, count 0 2006.257.06:41:47.20#ibcon#about to read 6, iclass 25, count 0 2006.257.06:41:47.20#ibcon#read 6, iclass 25, count 0 2006.257.06:41:47.20#ibcon#end of sib2, iclass 25, count 0 2006.257.06:41:47.20#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:41:47.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:41:47.20#ibcon#[25=USB\r\n] 2006.257.06:41:47.20#ibcon#*before write, iclass 25, count 0 2006.257.06:41:47.20#ibcon#enter sib2, iclass 25, count 0 2006.257.06:41:47.20#ibcon#flushed, iclass 25, count 0 2006.257.06:41:47.20#ibcon#about to write, iclass 25, count 0 2006.257.06:41:47.20#ibcon#wrote, iclass 25, count 0 2006.257.06:41:47.20#ibcon#about to read 3, iclass 25, count 0 2006.257.06:41:47.23#ibcon#read 3, iclass 25, count 0 2006.257.06:41:47.23#ibcon#about to read 4, iclass 25, count 0 2006.257.06:41:47.23#ibcon#read 4, iclass 25, count 0 2006.257.06:41:47.23#ibcon#about to read 5, iclass 25, count 0 2006.257.06:41:47.23#ibcon#read 5, iclass 25, count 0 2006.257.06:41:47.23#ibcon#about to read 6, iclass 25, count 0 2006.257.06:41:47.23#ibcon#read 6, iclass 25, count 0 2006.257.06:41:47.23#ibcon#end of sib2, iclass 25, count 0 2006.257.06:41:47.23#ibcon#*after write, iclass 25, count 0 2006.257.06:41:47.23#ibcon#*before return 0, iclass 25, count 0 2006.257.06:41:47.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:47.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:47.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:41:47.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:41:47.23$vck44/valo=4,624.99 2006.257.06:41:47.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.06:41:47.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.06:41:47.23#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:47.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:47.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:47.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:47.23#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:41:47.23#ibcon#first serial, iclass 27, count 0 2006.257.06:41:47.23#ibcon#enter sib2, iclass 27, count 0 2006.257.06:41:47.23#ibcon#flushed, iclass 27, count 0 2006.257.06:41:47.23#ibcon#about to write, iclass 27, count 0 2006.257.06:41:47.23#ibcon#wrote, iclass 27, count 0 2006.257.06:41:47.23#ibcon#about to read 3, iclass 27, count 0 2006.257.06:41:47.25#ibcon#read 3, iclass 27, count 0 2006.257.06:41:47.25#ibcon#about to read 4, iclass 27, count 0 2006.257.06:41:47.25#ibcon#read 4, iclass 27, count 0 2006.257.06:41:47.25#ibcon#about to read 5, iclass 27, count 0 2006.257.06:41:47.25#ibcon#read 5, iclass 27, count 0 2006.257.06:41:47.25#ibcon#about to read 6, iclass 27, count 0 2006.257.06:41:47.25#ibcon#read 6, iclass 27, count 0 2006.257.06:41:47.25#ibcon#end of sib2, iclass 27, count 0 2006.257.06:41:47.25#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:41:47.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:41:47.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:41:47.25#ibcon#*before write, iclass 27, count 0 2006.257.06:41:47.25#ibcon#enter sib2, iclass 27, count 0 2006.257.06:41:47.25#ibcon#flushed, iclass 27, count 0 2006.257.06:41:47.25#ibcon#about to write, iclass 27, count 0 2006.257.06:41:47.25#ibcon#wrote, iclass 27, count 0 2006.257.06:41:47.25#ibcon#about to read 3, iclass 27, count 0 2006.257.06:41:47.29#ibcon#read 3, iclass 27, count 0 2006.257.06:41:47.29#ibcon#about to read 4, iclass 27, count 0 2006.257.06:41:47.29#ibcon#read 4, iclass 27, count 0 2006.257.06:41:47.29#ibcon#about to read 5, iclass 27, count 0 2006.257.06:41:47.29#ibcon#read 5, iclass 27, count 0 2006.257.06:41:47.29#ibcon#about to read 6, iclass 27, count 0 2006.257.06:41:47.29#ibcon#read 6, iclass 27, count 0 2006.257.06:41:47.29#ibcon#end of sib2, iclass 27, count 0 2006.257.06:41:47.29#ibcon#*after write, iclass 27, count 0 2006.257.06:41:47.29#ibcon#*before return 0, iclass 27, count 0 2006.257.06:41:47.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:47.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:47.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:41:47.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:41:47.29$vck44/va=4,7 2006.257.06:41:47.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.06:41:47.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.06:41:47.29#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:47.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:47.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:47.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:47.35#ibcon#enter wrdev, iclass 29, count 2 2006.257.06:41:47.35#ibcon#first serial, iclass 29, count 2 2006.257.06:41:47.35#ibcon#enter sib2, iclass 29, count 2 2006.257.06:41:47.35#ibcon#flushed, iclass 29, count 2 2006.257.06:41:47.35#ibcon#about to write, iclass 29, count 2 2006.257.06:41:47.35#ibcon#wrote, iclass 29, count 2 2006.257.06:41:47.35#ibcon#about to read 3, iclass 29, count 2 2006.257.06:41:47.37#ibcon#read 3, iclass 29, count 2 2006.257.06:41:47.37#ibcon#about to read 4, iclass 29, count 2 2006.257.06:41:47.37#ibcon#read 4, iclass 29, count 2 2006.257.06:41:47.37#ibcon#about to read 5, iclass 29, count 2 2006.257.06:41:47.37#ibcon#read 5, iclass 29, count 2 2006.257.06:41:47.37#ibcon#about to read 6, iclass 29, count 2 2006.257.06:41:47.37#ibcon#read 6, iclass 29, count 2 2006.257.06:41:47.37#ibcon#end of sib2, iclass 29, count 2 2006.257.06:41:47.37#ibcon#*mode == 0, iclass 29, count 2 2006.257.06:41:47.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.06:41:47.37#ibcon#[25=AT04-07\r\n] 2006.257.06:41:47.37#ibcon#*before write, iclass 29, count 2 2006.257.06:41:47.37#ibcon#enter sib2, iclass 29, count 2 2006.257.06:41:47.37#ibcon#flushed, iclass 29, count 2 2006.257.06:41:47.37#ibcon#about to write, iclass 29, count 2 2006.257.06:41:47.37#ibcon#wrote, iclass 29, count 2 2006.257.06:41:47.37#ibcon#about to read 3, iclass 29, count 2 2006.257.06:41:47.40#ibcon#read 3, iclass 29, count 2 2006.257.06:41:47.40#ibcon#about to read 4, iclass 29, count 2 2006.257.06:41:47.40#ibcon#read 4, iclass 29, count 2 2006.257.06:41:47.40#ibcon#about to read 5, iclass 29, count 2 2006.257.06:41:47.40#ibcon#read 5, iclass 29, count 2 2006.257.06:41:47.40#ibcon#about to read 6, iclass 29, count 2 2006.257.06:41:47.40#ibcon#read 6, iclass 29, count 2 2006.257.06:41:47.40#ibcon#end of sib2, iclass 29, count 2 2006.257.06:41:47.40#ibcon#*after write, iclass 29, count 2 2006.257.06:41:47.40#ibcon#*before return 0, iclass 29, count 2 2006.257.06:41:47.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:47.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:47.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.06:41:47.40#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:47.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:47.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:47.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:47.52#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:41:47.52#ibcon#first serial, iclass 29, count 0 2006.257.06:41:47.52#ibcon#enter sib2, iclass 29, count 0 2006.257.06:41:47.52#ibcon#flushed, iclass 29, count 0 2006.257.06:41:47.52#ibcon#about to write, iclass 29, count 0 2006.257.06:41:47.52#ibcon#wrote, iclass 29, count 0 2006.257.06:41:47.52#ibcon#about to read 3, iclass 29, count 0 2006.257.06:41:47.54#ibcon#read 3, iclass 29, count 0 2006.257.06:41:47.54#ibcon#about to read 4, iclass 29, count 0 2006.257.06:41:47.54#ibcon#read 4, iclass 29, count 0 2006.257.06:41:47.54#ibcon#about to read 5, iclass 29, count 0 2006.257.06:41:47.54#ibcon#read 5, iclass 29, count 0 2006.257.06:41:47.54#ibcon#about to read 6, iclass 29, count 0 2006.257.06:41:47.54#ibcon#read 6, iclass 29, count 0 2006.257.06:41:47.54#ibcon#end of sib2, iclass 29, count 0 2006.257.06:41:47.54#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:41:47.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:41:47.54#ibcon#[25=USB\r\n] 2006.257.06:41:47.54#ibcon#*before write, iclass 29, count 0 2006.257.06:41:47.54#ibcon#enter sib2, iclass 29, count 0 2006.257.06:41:47.54#ibcon#flushed, iclass 29, count 0 2006.257.06:41:47.54#ibcon#about to write, iclass 29, count 0 2006.257.06:41:47.54#ibcon#wrote, iclass 29, count 0 2006.257.06:41:47.54#ibcon#about to read 3, iclass 29, count 0 2006.257.06:41:47.57#ibcon#read 3, iclass 29, count 0 2006.257.06:41:47.57#ibcon#about to read 4, iclass 29, count 0 2006.257.06:41:47.57#ibcon#read 4, iclass 29, count 0 2006.257.06:41:47.57#ibcon#about to read 5, iclass 29, count 0 2006.257.06:41:47.57#ibcon#read 5, iclass 29, count 0 2006.257.06:41:47.57#ibcon#about to read 6, iclass 29, count 0 2006.257.06:41:47.57#ibcon#read 6, iclass 29, count 0 2006.257.06:41:47.57#ibcon#end of sib2, iclass 29, count 0 2006.257.06:41:47.57#ibcon#*after write, iclass 29, count 0 2006.257.06:41:47.57#ibcon#*before return 0, iclass 29, count 0 2006.257.06:41:47.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:47.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:47.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:41:47.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:41:47.57$vck44/valo=5,734.99 2006.257.06:41:47.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.06:41:47.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.06:41:47.57#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:47.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:47.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:47.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:47.57#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:41:47.57#ibcon#first serial, iclass 31, count 0 2006.257.06:41:47.57#ibcon#enter sib2, iclass 31, count 0 2006.257.06:41:47.57#ibcon#flushed, iclass 31, count 0 2006.257.06:41:47.57#ibcon#about to write, iclass 31, count 0 2006.257.06:41:47.57#ibcon#wrote, iclass 31, count 0 2006.257.06:41:47.57#ibcon#about to read 3, iclass 31, count 0 2006.257.06:41:47.59#ibcon#read 3, iclass 31, count 0 2006.257.06:41:47.59#ibcon#about to read 4, iclass 31, count 0 2006.257.06:41:47.59#ibcon#read 4, iclass 31, count 0 2006.257.06:41:47.59#ibcon#about to read 5, iclass 31, count 0 2006.257.06:41:47.59#ibcon#read 5, iclass 31, count 0 2006.257.06:41:47.59#ibcon#about to read 6, iclass 31, count 0 2006.257.06:41:47.59#ibcon#read 6, iclass 31, count 0 2006.257.06:41:47.59#ibcon#end of sib2, iclass 31, count 0 2006.257.06:41:47.59#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:41:47.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:41:47.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:41:47.59#ibcon#*before write, iclass 31, count 0 2006.257.06:41:47.59#ibcon#enter sib2, iclass 31, count 0 2006.257.06:41:47.59#ibcon#flushed, iclass 31, count 0 2006.257.06:41:47.59#ibcon#about to write, iclass 31, count 0 2006.257.06:41:47.59#ibcon#wrote, iclass 31, count 0 2006.257.06:41:47.59#ibcon#about to read 3, iclass 31, count 0 2006.257.06:41:47.63#ibcon#read 3, iclass 31, count 0 2006.257.06:41:47.63#ibcon#about to read 4, iclass 31, count 0 2006.257.06:41:47.63#ibcon#read 4, iclass 31, count 0 2006.257.06:41:47.63#ibcon#about to read 5, iclass 31, count 0 2006.257.06:41:47.63#ibcon#read 5, iclass 31, count 0 2006.257.06:41:47.63#ibcon#about to read 6, iclass 31, count 0 2006.257.06:41:47.63#ibcon#read 6, iclass 31, count 0 2006.257.06:41:47.63#ibcon#end of sib2, iclass 31, count 0 2006.257.06:41:47.63#ibcon#*after write, iclass 31, count 0 2006.257.06:41:47.63#ibcon#*before return 0, iclass 31, count 0 2006.257.06:41:47.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:47.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:47.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:41:47.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:41:47.63$vck44/va=5,4 2006.257.06:41:47.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.06:41:47.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.06:41:47.63#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:47.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:47.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:47.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:47.69#ibcon#enter wrdev, iclass 33, count 2 2006.257.06:41:47.69#ibcon#first serial, iclass 33, count 2 2006.257.06:41:47.69#ibcon#enter sib2, iclass 33, count 2 2006.257.06:41:47.69#ibcon#flushed, iclass 33, count 2 2006.257.06:41:47.69#ibcon#about to write, iclass 33, count 2 2006.257.06:41:47.69#ibcon#wrote, iclass 33, count 2 2006.257.06:41:47.69#ibcon#about to read 3, iclass 33, count 2 2006.257.06:41:47.71#ibcon#read 3, iclass 33, count 2 2006.257.06:41:47.71#ibcon#about to read 4, iclass 33, count 2 2006.257.06:41:47.71#ibcon#read 4, iclass 33, count 2 2006.257.06:41:47.71#ibcon#about to read 5, iclass 33, count 2 2006.257.06:41:47.71#ibcon#read 5, iclass 33, count 2 2006.257.06:41:47.71#ibcon#about to read 6, iclass 33, count 2 2006.257.06:41:47.71#ibcon#read 6, iclass 33, count 2 2006.257.06:41:47.71#ibcon#end of sib2, iclass 33, count 2 2006.257.06:41:47.71#ibcon#*mode == 0, iclass 33, count 2 2006.257.06:41:47.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.06:41:47.71#ibcon#[25=AT05-04\r\n] 2006.257.06:41:47.71#ibcon#*before write, iclass 33, count 2 2006.257.06:41:47.71#ibcon#enter sib2, iclass 33, count 2 2006.257.06:41:47.71#ibcon#flushed, iclass 33, count 2 2006.257.06:41:47.71#ibcon#about to write, iclass 33, count 2 2006.257.06:41:47.71#ibcon#wrote, iclass 33, count 2 2006.257.06:41:47.71#ibcon#about to read 3, iclass 33, count 2 2006.257.06:41:47.74#ibcon#read 3, iclass 33, count 2 2006.257.06:41:47.74#ibcon#about to read 4, iclass 33, count 2 2006.257.06:41:47.74#ibcon#read 4, iclass 33, count 2 2006.257.06:41:47.74#ibcon#about to read 5, iclass 33, count 2 2006.257.06:41:47.74#ibcon#read 5, iclass 33, count 2 2006.257.06:41:47.74#ibcon#about to read 6, iclass 33, count 2 2006.257.06:41:47.74#ibcon#read 6, iclass 33, count 2 2006.257.06:41:47.74#ibcon#end of sib2, iclass 33, count 2 2006.257.06:41:47.74#ibcon#*after write, iclass 33, count 2 2006.257.06:41:47.74#ibcon#*before return 0, iclass 33, count 2 2006.257.06:41:47.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:47.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:47.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.06:41:47.74#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:47.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:47.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:47.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:47.86#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:41:47.86#ibcon#first serial, iclass 33, count 0 2006.257.06:41:47.86#ibcon#enter sib2, iclass 33, count 0 2006.257.06:41:47.86#ibcon#flushed, iclass 33, count 0 2006.257.06:41:47.86#ibcon#about to write, iclass 33, count 0 2006.257.06:41:47.86#ibcon#wrote, iclass 33, count 0 2006.257.06:41:47.86#ibcon#about to read 3, iclass 33, count 0 2006.257.06:41:47.88#ibcon#read 3, iclass 33, count 0 2006.257.06:41:47.88#ibcon#about to read 4, iclass 33, count 0 2006.257.06:41:47.88#ibcon#read 4, iclass 33, count 0 2006.257.06:41:47.88#ibcon#about to read 5, iclass 33, count 0 2006.257.06:41:47.88#ibcon#read 5, iclass 33, count 0 2006.257.06:41:47.88#ibcon#about to read 6, iclass 33, count 0 2006.257.06:41:47.88#ibcon#read 6, iclass 33, count 0 2006.257.06:41:47.88#ibcon#end of sib2, iclass 33, count 0 2006.257.06:41:47.88#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:41:47.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:41:47.88#ibcon#[25=USB\r\n] 2006.257.06:41:47.88#ibcon#*before write, iclass 33, count 0 2006.257.06:41:47.88#ibcon#enter sib2, iclass 33, count 0 2006.257.06:41:47.88#ibcon#flushed, iclass 33, count 0 2006.257.06:41:47.88#ibcon#about to write, iclass 33, count 0 2006.257.06:41:47.88#ibcon#wrote, iclass 33, count 0 2006.257.06:41:47.88#ibcon#about to read 3, iclass 33, count 0 2006.257.06:41:47.91#ibcon#read 3, iclass 33, count 0 2006.257.06:41:47.91#ibcon#about to read 4, iclass 33, count 0 2006.257.06:41:47.91#ibcon#read 4, iclass 33, count 0 2006.257.06:41:47.91#ibcon#about to read 5, iclass 33, count 0 2006.257.06:41:47.91#ibcon#read 5, iclass 33, count 0 2006.257.06:41:47.91#ibcon#about to read 6, iclass 33, count 0 2006.257.06:41:47.91#ibcon#read 6, iclass 33, count 0 2006.257.06:41:47.91#ibcon#end of sib2, iclass 33, count 0 2006.257.06:41:47.91#ibcon#*after write, iclass 33, count 0 2006.257.06:41:47.91#ibcon#*before return 0, iclass 33, count 0 2006.257.06:41:47.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:47.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:47.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:41:47.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:41:47.91$vck44/valo=6,814.99 2006.257.06:41:47.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:41:47.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:41:47.91#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:47.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:47.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:47.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:47.91#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:41:47.91#ibcon#first serial, iclass 35, count 0 2006.257.06:41:47.91#ibcon#enter sib2, iclass 35, count 0 2006.257.06:41:47.91#ibcon#flushed, iclass 35, count 0 2006.257.06:41:47.91#ibcon#about to write, iclass 35, count 0 2006.257.06:41:47.91#ibcon#wrote, iclass 35, count 0 2006.257.06:41:47.91#ibcon#about to read 3, iclass 35, count 0 2006.257.06:41:47.93#ibcon#read 3, iclass 35, count 0 2006.257.06:41:47.93#ibcon#about to read 4, iclass 35, count 0 2006.257.06:41:47.93#ibcon#read 4, iclass 35, count 0 2006.257.06:41:47.93#ibcon#about to read 5, iclass 35, count 0 2006.257.06:41:47.93#ibcon#read 5, iclass 35, count 0 2006.257.06:41:47.93#ibcon#about to read 6, iclass 35, count 0 2006.257.06:41:47.93#ibcon#read 6, iclass 35, count 0 2006.257.06:41:47.93#ibcon#end of sib2, iclass 35, count 0 2006.257.06:41:47.93#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:41:47.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:41:47.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:41:47.93#ibcon#*before write, iclass 35, count 0 2006.257.06:41:47.93#ibcon#enter sib2, iclass 35, count 0 2006.257.06:41:47.93#ibcon#flushed, iclass 35, count 0 2006.257.06:41:47.93#ibcon#about to write, iclass 35, count 0 2006.257.06:41:47.93#ibcon#wrote, iclass 35, count 0 2006.257.06:41:47.93#ibcon#about to read 3, iclass 35, count 0 2006.257.06:41:47.97#ibcon#read 3, iclass 35, count 0 2006.257.06:41:47.97#ibcon#about to read 4, iclass 35, count 0 2006.257.06:41:47.97#ibcon#read 4, iclass 35, count 0 2006.257.06:41:47.97#ibcon#about to read 5, iclass 35, count 0 2006.257.06:41:47.97#ibcon#read 5, iclass 35, count 0 2006.257.06:41:47.97#ibcon#about to read 6, iclass 35, count 0 2006.257.06:41:47.97#ibcon#read 6, iclass 35, count 0 2006.257.06:41:47.97#ibcon#end of sib2, iclass 35, count 0 2006.257.06:41:47.97#ibcon#*after write, iclass 35, count 0 2006.257.06:41:47.97#ibcon#*before return 0, iclass 35, count 0 2006.257.06:41:47.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:47.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:47.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:41:47.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:41:47.97$vck44/va=6,4 2006.257.06:41:47.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.06:41:47.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.06:41:47.97#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:47.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:48.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:48.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:48.03#ibcon#enter wrdev, iclass 37, count 2 2006.257.06:41:48.03#ibcon#first serial, iclass 37, count 2 2006.257.06:41:48.03#ibcon#enter sib2, iclass 37, count 2 2006.257.06:41:48.03#ibcon#flushed, iclass 37, count 2 2006.257.06:41:48.03#ibcon#about to write, iclass 37, count 2 2006.257.06:41:48.03#ibcon#wrote, iclass 37, count 2 2006.257.06:41:48.03#ibcon#about to read 3, iclass 37, count 2 2006.257.06:41:48.05#ibcon#read 3, iclass 37, count 2 2006.257.06:41:48.05#ibcon#about to read 4, iclass 37, count 2 2006.257.06:41:48.05#ibcon#read 4, iclass 37, count 2 2006.257.06:41:48.05#ibcon#about to read 5, iclass 37, count 2 2006.257.06:41:48.05#ibcon#read 5, iclass 37, count 2 2006.257.06:41:48.05#ibcon#about to read 6, iclass 37, count 2 2006.257.06:41:48.05#ibcon#read 6, iclass 37, count 2 2006.257.06:41:48.05#ibcon#end of sib2, iclass 37, count 2 2006.257.06:41:48.05#ibcon#*mode == 0, iclass 37, count 2 2006.257.06:41:48.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.06:41:48.05#ibcon#[25=AT06-04\r\n] 2006.257.06:41:48.05#ibcon#*before write, iclass 37, count 2 2006.257.06:41:48.05#ibcon#enter sib2, iclass 37, count 2 2006.257.06:41:48.05#ibcon#flushed, iclass 37, count 2 2006.257.06:41:48.05#ibcon#about to write, iclass 37, count 2 2006.257.06:41:48.05#ibcon#wrote, iclass 37, count 2 2006.257.06:41:48.05#ibcon#about to read 3, iclass 37, count 2 2006.257.06:41:48.08#ibcon#read 3, iclass 37, count 2 2006.257.06:41:48.08#ibcon#about to read 4, iclass 37, count 2 2006.257.06:41:48.08#ibcon#read 4, iclass 37, count 2 2006.257.06:41:48.08#ibcon#about to read 5, iclass 37, count 2 2006.257.06:41:48.08#ibcon#read 5, iclass 37, count 2 2006.257.06:41:48.08#ibcon#about to read 6, iclass 37, count 2 2006.257.06:41:48.08#ibcon#read 6, iclass 37, count 2 2006.257.06:41:48.08#ibcon#end of sib2, iclass 37, count 2 2006.257.06:41:48.08#ibcon#*after write, iclass 37, count 2 2006.257.06:41:48.08#ibcon#*before return 0, iclass 37, count 2 2006.257.06:41:48.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:48.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:48.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.06:41:48.08#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:48.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:48.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:48.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:48.20#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:41:48.20#ibcon#first serial, iclass 37, count 0 2006.257.06:41:48.20#ibcon#enter sib2, iclass 37, count 0 2006.257.06:41:48.20#ibcon#flushed, iclass 37, count 0 2006.257.06:41:48.20#ibcon#about to write, iclass 37, count 0 2006.257.06:41:48.20#ibcon#wrote, iclass 37, count 0 2006.257.06:41:48.20#ibcon#about to read 3, iclass 37, count 0 2006.257.06:41:48.22#ibcon#read 3, iclass 37, count 0 2006.257.06:41:48.22#ibcon#about to read 4, iclass 37, count 0 2006.257.06:41:48.22#ibcon#read 4, iclass 37, count 0 2006.257.06:41:48.22#ibcon#about to read 5, iclass 37, count 0 2006.257.06:41:48.22#ibcon#read 5, iclass 37, count 0 2006.257.06:41:48.22#ibcon#about to read 6, iclass 37, count 0 2006.257.06:41:48.22#ibcon#read 6, iclass 37, count 0 2006.257.06:41:48.22#ibcon#end of sib2, iclass 37, count 0 2006.257.06:41:48.22#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:41:48.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:41:48.22#ibcon#[25=USB\r\n] 2006.257.06:41:48.22#ibcon#*before write, iclass 37, count 0 2006.257.06:41:48.22#ibcon#enter sib2, iclass 37, count 0 2006.257.06:41:48.22#ibcon#flushed, iclass 37, count 0 2006.257.06:41:48.22#ibcon#about to write, iclass 37, count 0 2006.257.06:41:48.22#ibcon#wrote, iclass 37, count 0 2006.257.06:41:48.22#ibcon#about to read 3, iclass 37, count 0 2006.257.06:41:48.25#ibcon#read 3, iclass 37, count 0 2006.257.06:41:48.25#ibcon#about to read 4, iclass 37, count 0 2006.257.06:41:48.25#ibcon#read 4, iclass 37, count 0 2006.257.06:41:48.25#ibcon#about to read 5, iclass 37, count 0 2006.257.06:41:48.25#ibcon#read 5, iclass 37, count 0 2006.257.06:41:48.25#ibcon#about to read 6, iclass 37, count 0 2006.257.06:41:48.25#ibcon#read 6, iclass 37, count 0 2006.257.06:41:48.25#ibcon#end of sib2, iclass 37, count 0 2006.257.06:41:48.25#ibcon#*after write, iclass 37, count 0 2006.257.06:41:48.25#ibcon#*before return 0, iclass 37, count 0 2006.257.06:41:48.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:48.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:48.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:41:48.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:41:48.25$vck44/valo=7,864.99 2006.257.06:41:48.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.06:41:48.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.06:41:48.25#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:48.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:48.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:48.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:48.25#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:41:48.25#ibcon#first serial, iclass 39, count 0 2006.257.06:41:48.25#ibcon#enter sib2, iclass 39, count 0 2006.257.06:41:48.25#ibcon#flushed, iclass 39, count 0 2006.257.06:41:48.25#ibcon#about to write, iclass 39, count 0 2006.257.06:41:48.25#ibcon#wrote, iclass 39, count 0 2006.257.06:41:48.25#ibcon#about to read 3, iclass 39, count 0 2006.257.06:41:48.27#ibcon#read 3, iclass 39, count 0 2006.257.06:41:48.27#ibcon#about to read 4, iclass 39, count 0 2006.257.06:41:48.27#ibcon#read 4, iclass 39, count 0 2006.257.06:41:48.27#ibcon#about to read 5, iclass 39, count 0 2006.257.06:41:48.27#ibcon#read 5, iclass 39, count 0 2006.257.06:41:48.27#ibcon#about to read 6, iclass 39, count 0 2006.257.06:41:48.27#ibcon#read 6, iclass 39, count 0 2006.257.06:41:48.27#ibcon#end of sib2, iclass 39, count 0 2006.257.06:41:48.27#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:41:48.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:41:48.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:41:48.27#ibcon#*before write, iclass 39, count 0 2006.257.06:41:48.27#ibcon#enter sib2, iclass 39, count 0 2006.257.06:41:48.27#ibcon#flushed, iclass 39, count 0 2006.257.06:41:48.27#ibcon#about to write, iclass 39, count 0 2006.257.06:41:48.27#ibcon#wrote, iclass 39, count 0 2006.257.06:41:48.27#ibcon#about to read 3, iclass 39, count 0 2006.257.06:41:48.31#ibcon#read 3, iclass 39, count 0 2006.257.06:41:48.31#ibcon#about to read 4, iclass 39, count 0 2006.257.06:41:48.31#ibcon#read 4, iclass 39, count 0 2006.257.06:41:48.31#ibcon#about to read 5, iclass 39, count 0 2006.257.06:41:48.31#ibcon#read 5, iclass 39, count 0 2006.257.06:41:48.31#ibcon#about to read 6, iclass 39, count 0 2006.257.06:41:48.31#ibcon#read 6, iclass 39, count 0 2006.257.06:41:48.31#ibcon#end of sib2, iclass 39, count 0 2006.257.06:41:48.31#ibcon#*after write, iclass 39, count 0 2006.257.06:41:48.31#ibcon#*before return 0, iclass 39, count 0 2006.257.06:41:48.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:48.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:48.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:41:48.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:41:48.31$vck44/va=7,4 2006.257.06:41:48.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.06:41:48.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.06:41:48.31#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:48.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:48.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:48.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:48.37#ibcon#enter wrdev, iclass 3, count 2 2006.257.06:41:48.37#ibcon#first serial, iclass 3, count 2 2006.257.06:41:48.37#ibcon#enter sib2, iclass 3, count 2 2006.257.06:41:48.37#ibcon#flushed, iclass 3, count 2 2006.257.06:41:48.37#ibcon#about to write, iclass 3, count 2 2006.257.06:41:48.37#ibcon#wrote, iclass 3, count 2 2006.257.06:41:48.37#ibcon#about to read 3, iclass 3, count 2 2006.257.06:41:48.39#ibcon#read 3, iclass 3, count 2 2006.257.06:41:48.39#ibcon#about to read 4, iclass 3, count 2 2006.257.06:41:48.39#ibcon#read 4, iclass 3, count 2 2006.257.06:41:48.39#ibcon#about to read 5, iclass 3, count 2 2006.257.06:41:48.39#ibcon#read 5, iclass 3, count 2 2006.257.06:41:48.39#ibcon#about to read 6, iclass 3, count 2 2006.257.06:41:48.39#ibcon#read 6, iclass 3, count 2 2006.257.06:41:48.39#ibcon#end of sib2, iclass 3, count 2 2006.257.06:41:48.39#ibcon#*mode == 0, iclass 3, count 2 2006.257.06:41:48.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.06:41:48.39#ibcon#[25=AT07-04\r\n] 2006.257.06:41:48.39#ibcon#*before write, iclass 3, count 2 2006.257.06:41:48.39#ibcon#enter sib2, iclass 3, count 2 2006.257.06:41:48.39#ibcon#flushed, iclass 3, count 2 2006.257.06:41:48.39#ibcon#about to write, iclass 3, count 2 2006.257.06:41:48.39#ibcon#wrote, iclass 3, count 2 2006.257.06:41:48.39#ibcon#about to read 3, iclass 3, count 2 2006.257.06:41:48.42#ibcon#read 3, iclass 3, count 2 2006.257.06:41:48.42#ibcon#about to read 4, iclass 3, count 2 2006.257.06:41:48.42#ibcon#read 4, iclass 3, count 2 2006.257.06:41:48.42#ibcon#about to read 5, iclass 3, count 2 2006.257.06:41:48.42#ibcon#read 5, iclass 3, count 2 2006.257.06:41:48.42#ibcon#about to read 6, iclass 3, count 2 2006.257.06:41:48.42#ibcon#read 6, iclass 3, count 2 2006.257.06:41:48.42#ibcon#end of sib2, iclass 3, count 2 2006.257.06:41:48.42#ibcon#*after write, iclass 3, count 2 2006.257.06:41:48.42#ibcon#*before return 0, iclass 3, count 2 2006.257.06:41:48.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:48.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:48.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.06:41:48.42#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:48.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:48.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:48.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:48.54#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:41:48.54#ibcon#first serial, iclass 3, count 0 2006.257.06:41:48.54#ibcon#enter sib2, iclass 3, count 0 2006.257.06:41:48.54#ibcon#flushed, iclass 3, count 0 2006.257.06:41:48.54#ibcon#about to write, iclass 3, count 0 2006.257.06:41:48.54#ibcon#wrote, iclass 3, count 0 2006.257.06:41:48.54#ibcon#about to read 3, iclass 3, count 0 2006.257.06:41:48.56#ibcon#read 3, iclass 3, count 0 2006.257.06:41:48.56#ibcon#about to read 4, iclass 3, count 0 2006.257.06:41:48.56#ibcon#read 4, iclass 3, count 0 2006.257.06:41:48.56#ibcon#about to read 5, iclass 3, count 0 2006.257.06:41:48.56#ibcon#read 5, iclass 3, count 0 2006.257.06:41:48.56#ibcon#about to read 6, iclass 3, count 0 2006.257.06:41:48.56#ibcon#read 6, iclass 3, count 0 2006.257.06:41:48.56#ibcon#end of sib2, iclass 3, count 0 2006.257.06:41:48.56#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:41:48.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:41:48.56#ibcon#[25=USB\r\n] 2006.257.06:41:48.56#ibcon#*before write, iclass 3, count 0 2006.257.06:41:48.56#ibcon#enter sib2, iclass 3, count 0 2006.257.06:41:48.56#ibcon#flushed, iclass 3, count 0 2006.257.06:41:48.56#ibcon#about to write, iclass 3, count 0 2006.257.06:41:48.56#ibcon#wrote, iclass 3, count 0 2006.257.06:41:48.56#ibcon#about to read 3, iclass 3, count 0 2006.257.06:41:48.59#ibcon#read 3, iclass 3, count 0 2006.257.06:41:48.59#ibcon#about to read 4, iclass 3, count 0 2006.257.06:41:48.59#ibcon#read 4, iclass 3, count 0 2006.257.06:41:48.59#ibcon#about to read 5, iclass 3, count 0 2006.257.06:41:48.59#ibcon#read 5, iclass 3, count 0 2006.257.06:41:48.59#ibcon#about to read 6, iclass 3, count 0 2006.257.06:41:48.59#ibcon#read 6, iclass 3, count 0 2006.257.06:41:48.59#ibcon#end of sib2, iclass 3, count 0 2006.257.06:41:48.59#ibcon#*after write, iclass 3, count 0 2006.257.06:41:48.59#ibcon#*before return 0, iclass 3, count 0 2006.257.06:41:48.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:48.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:48.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:41:48.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:41:48.59$vck44/valo=8,884.99 2006.257.06:41:48.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.06:41:48.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.06:41:48.59#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:48.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:48.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:48.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:48.59#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:41:48.59#ibcon#first serial, iclass 5, count 0 2006.257.06:41:48.59#ibcon#enter sib2, iclass 5, count 0 2006.257.06:41:48.59#ibcon#flushed, iclass 5, count 0 2006.257.06:41:48.59#ibcon#about to write, iclass 5, count 0 2006.257.06:41:48.59#ibcon#wrote, iclass 5, count 0 2006.257.06:41:48.59#ibcon#about to read 3, iclass 5, count 0 2006.257.06:41:48.61#ibcon#read 3, iclass 5, count 0 2006.257.06:41:48.61#ibcon#about to read 4, iclass 5, count 0 2006.257.06:41:48.61#ibcon#read 4, iclass 5, count 0 2006.257.06:41:48.61#ibcon#about to read 5, iclass 5, count 0 2006.257.06:41:48.61#ibcon#read 5, iclass 5, count 0 2006.257.06:41:48.61#ibcon#about to read 6, iclass 5, count 0 2006.257.06:41:48.61#ibcon#read 6, iclass 5, count 0 2006.257.06:41:48.61#ibcon#end of sib2, iclass 5, count 0 2006.257.06:41:48.61#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:41:48.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:41:48.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:41:48.61#ibcon#*before write, iclass 5, count 0 2006.257.06:41:48.61#ibcon#enter sib2, iclass 5, count 0 2006.257.06:41:48.61#ibcon#flushed, iclass 5, count 0 2006.257.06:41:48.61#ibcon#about to write, iclass 5, count 0 2006.257.06:41:48.61#ibcon#wrote, iclass 5, count 0 2006.257.06:41:48.61#ibcon#about to read 3, iclass 5, count 0 2006.257.06:41:48.65#ibcon#read 3, iclass 5, count 0 2006.257.06:41:48.65#ibcon#about to read 4, iclass 5, count 0 2006.257.06:41:48.65#ibcon#read 4, iclass 5, count 0 2006.257.06:41:48.65#ibcon#about to read 5, iclass 5, count 0 2006.257.06:41:48.65#ibcon#read 5, iclass 5, count 0 2006.257.06:41:48.65#ibcon#about to read 6, iclass 5, count 0 2006.257.06:41:48.65#ibcon#read 6, iclass 5, count 0 2006.257.06:41:48.65#ibcon#end of sib2, iclass 5, count 0 2006.257.06:41:48.65#ibcon#*after write, iclass 5, count 0 2006.257.06:41:48.65#ibcon#*before return 0, iclass 5, count 0 2006.257.06:41:48.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:48.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:48.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:41:48.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:41:48.65$vck44/va=8,4 2006.257.06:41:48.65#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.06:41:48.65#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.06:41:48.65#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:48.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:41:48.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:41:48.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:41:48.71#ibcon#enter wrdev, iclass 7, count 2 2006.257.06:41:48.71#ibcon#first serial, iclass 7, count 2 2006.257.06:41:48.71#ibcon#enter sib2, iclass 7, count 2 2006.257.06:41:48.71#ibcon#flushed, iclass 7, count 2 2006.257.06:41:48.71#ibcon#about to write, iclass 7, count 2 2006.257.06:41:48.71#ibcon#wrote, iclass 7, count 2 2006.257.06:41:48.71#ibcon#about to read 3, iclass 7, count 2 2006.257.06:41:48.73#ibcon#read 3, iclass 7, count 2 2006.257.06:41:48.73#ibcon#about to read 4, iclass 7, count 2 2006.257.06:41:48.73#ibcon#read 4, iclass 7, count 2 2006.257.06:41:48.73#ibcon#about to read 5, iclass 7, count 2 2006.257.06:41:48.73#ibcon#read 5, iclass 7, count 2 2006.257.06:41:48.73#ibcon#about to read 6, iclass 7, count 2 2006.257.06:41:48.73#ibcon#read 6, iclass 7, count 2 2006.257.06:41:48.73#ibcon#end of sib2, iclass 7, count 2 2006.257.06:41:48.73#ibcon#*mode == 0, iclass 7, count 2 2006.257.06:41:48.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.06:41:48.73#ibcon#[25=AT08-04\r\n] 2006.257.06:41:48.73#ibcon#*before write, iclass 7, count 2 2006.257.06:41:48.73#ibcon#enter sib2, iclass 7, count 2 2006.257.06:41:48.73#ibcon#flushed, iclass 7, count 2 2006.257.06:41:48.73#ibcon#about to write, iclass 7, count 2 2006.257.06:41:48.73#ibcon#wrote, iclass 7, count 2 2006.257.06:41:48.73#ibcon#about to read 3, iclass 7, count 2 2006.257.06:41:48.76#ibcon#read 3, iclass 7, count 2 2006.257.06:41:48.76#ibcon#about to read 4, iclass 7, count 2 2006.257.06:41:48.76#ibcon#read 4, iclass 7, count 2 2006.257.06:41:48.76#ibcon#about to read 5, iclass 7, count 2 2006.257.06:41:48.76#ibcon#read 5, iclass 7, count 2 2006.257.06:41:48.76#ibcon#about to read 6, iclass 7, count 2 2006.257.06:41:48.76#ibcon#read 6, iclass 7, count 2 2006.257.06:41:48.76#ibcon#end of sib2, iclass 7, count 2 2006.257.06:41:48.76#ibcon#*after write, iclass 7, count 2 2006.257.06:41:48.76#ibcon#*before return 0, iclass 7, count 2 2006.257.06:41:48.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:41:48.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:41:48.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.06:41:48.76#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:48.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:41:48.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:41:48.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:41:48.88#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:41:48.88#ibcon#first serial, iclass 7, count 0 2006.257.06:41:48.88#ibcon#enter sib2, iclass 7, count 0 2006.257.06:41:48.88#ibcon#flushed, iclass 7, count 0 2006.257.06:41:48.88#ibcon#about to write, iclass 7, count 0 2006.257.06:41:48.88#ibcon#wrote, iclass 7, count 0 2006.257.06:41:48.88#ibcon#about to read 3, iclass 7, count 0 2006.257.06:41:48.90#ibcon#read 3, iclass 7, count 0 2006.257.06:41:48.90#ibcon#about to read 4, iclass 7, count 0 2006.257.06:41:48.90#ibcon#read 4, iclass 7, count 0 2006.257.06:41:48.90#ibcon#about to read 5, iclass 7, count 0 2006.257.06:41:48.90#ibcon#read 5, iclass 7, count 0 2006.257.06:41:48.90#ibcon#about to read 6, iclass 7, count 0 2006.257.06:41:48.90#ibcon#read 6, iclass 7, count 0 2006.257.06:41:48.90#ibcon#end of sib2, iclass 7, count 0 2006.257.06:41:48.90#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:41:48.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:41:48.90#ibcon#[25=USB\r\n] 2006.257.06:41:48.90#ibcon#*before write, iclass 7, count 0 2006.257.06:41:48.90#ibcon#enter sib2, iclass 7, count 0 2006.257.06:41:48.90#ibcon#flushed, iclass 7, count 0 2006.257.06:41:48.90#ibcon#about to write, iclass 7, count 0 2006.257.06:41:48.90#ibcon#wrote, iclass 7, count 0 2006.257.06:41:48.90#ibcon#about to read 3, iclass 7, count 0 2006.257.06:41:48.93#ibcon#read 3, iclass 7, count 0 2006.257.06:41:48.93#ibcon#about to read 4, iclass 7, count 0 2006.257.06:41:48.93#ibcon#read 4, iclass 7, count 0 2006.257.06:41:48.93#ibcon#about to read 5, iclass 7, count 0 2006.257.06:41:48.93#ibcon#read 5, iclass 7, count 0 2006.257.06:41:48.93#ibcon#about to read 6, iclass 7, count 0 2006.257.06:41:48.93#ibcon#read 6, iclass 7, count 0 2006.257.06:41:48.93#ibcon#end of sib2, iclass 7, count 0 2006.257.06:41:48.93#ibcon#*after write, iclass 7, count 0 2006.257.06:41:48.93#ibcon#*before return 0, iclass 7, count 0 2006.257.06:41:48.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:41:48.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:41:48.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:41:48.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:41:48.93$vck44/vblo=1,629.99 2006.257.06:41:48.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.06:41:48.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.06:41:48.93#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:48.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:41:48.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:41:48.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:41:48.93#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:41:48.93#ibcon#first serial, iclass 11, count 0 2006.257.06:41:48.93#ibcon#enter sib2, iclass 11, count 0 2006.257.06:41:48.93#ibcon#flushed, iclass 11, count 0 2006.257.06:41:48.93#ibcon#about to write, iclass 11, count 0 2006.257.06:41:48.93#ibcon#wrote, iclass 11, count 0 2006.257.06:41:48.93#ibcon#about to read 3, iclass 11, count 0 2006.257.06:41:48.95#ibcon#read 3, iclass 11, count 0 2006.257.06:41:48.95#ibcon#about to read 4, iclass 11, count 0 2006.257.06:41:48.95#ibcon#read 4, iclass 11, count 0 2006.257.06:41:48.95#ibcon#about to read 5, iclass 11, count 0 2006.257.06:41:48.95#ibcon#read 5, iclass 11, count 0 2006.257.06:41:48.95#ibcon#about to read 6, iclass 11, count 0 2006.257.06:41:48.95#ibcon#read 6, iclass 11, count 0 2006.257.06:41:48.95#ibcon#end of sib2, iclass 11, count 0 2006.257.06:41:48.95#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:41:48.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:41:48.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:41:48.95#ibcon#*before write, iclass 11, count 0 2006.257.06:41:48.95#ibcon#enter sib2, iclass 11, count 0 2006.257.06:41:48.95#ibcon#flushed, iclass 11, count 0 2006.257.06:41:48.95#ibcon#about to write, iclass 11, count 0 2006.257.06:41:48.95#ibcon#wrote, iclass 11, count 0 2006.257.06:41:48.95#ibcon#about to read 3, iclass 11, count 0 2006.257.06:41:48.99#ibcon#read 3, iclass 11, count 0 2006.257.06:41:48.99#ibcon#about to read 4, iclass 11, count 0 2006.257.06:41:48.99#ibcon#read 4, iclass 11, count 0 2006.257.06:41:48.99#ibcon#about to read 5, iclass 11, count 0 2006.257.06:41:48.99#ibcon#read 5, iclass 11, count 0 2006.257.06:41:48.99#ibcon#about to read 6, iclass 11, count 0 2006.257.06:41:48.99#ibcon#read 6, iclass 11, count 0 2006.257.06:41:48.99#ibcon#end of sib2, iclass 11, count 0 2006.257.06:41:48.99#ibcon#*after write, iclass 11, count 0 2006.257.06:41:48.99#ibcon#*before return 0, iclass 11, count 0 2006.257.06:41:48.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:41:48.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:41:48.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:41:48.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:41:48.99$vck44/vb=1,4 2006.257.06:41:48.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.06:41:48.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.06:41:48.99#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:48.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:41:48.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:41:48.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:41:48.99#ibcon#enter wrdev, iclass 13, count 2 2006.257.06:41:48.99#ibcon#first serial, iclass 13, count 2 2006.257.06:41:48.99#ibcon#enter sib2, iclass 13, count 2 2006.257.06:41:48.99#ibcon#flushed, iclass 13, count 2 2006.257.06:41:48.99#ibcon#about to write, iclass 13, count 2 2006.257.06:41:48.99#ibcon#wrote, iclass 13, count 2 2006.257.06:41:48.99#ibcon#about to read 3, iclass 13, count 2 2006.257.06:41:49.01#ibcon#read 3, iclass 13, count 2 2006.257.06:41:49.01#ibcon#about to read 4, iclass 13, count 2 2006.257.06:41:49.01#ibcon#read 4, iclass 13, count 2 2006.257.06:41:49.01#ibcon#about to read 5, iclass 13, count 2 2006.257.06:41:49.01#ibcon#read 5, iclass 13, count 2 2006.257.06:41:49.01#ibcon#about to read 6, iclass 13, count 2 2006.257.06:41:49.01#ibcon#read 6, iclass 13, count 2 2006.257.06:41:49.01#ibcon#end of sib2, iclass 13, count 2 2006.257.06:41:49.01#ibcon#*mode == 0, iclass 13, count 2 2006.257.06:41:49.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.06:41:49.01#ibcon#[27=AT01-04\r\n] 2006.257.06:41:49.01#ibcon#*before write, iclass 13, count 2 2006.257.06:41:49.01#ibcon#enter sib2, iclass 13, count 2 2006.257.06:41:49.01#ibcon#flushed, iclass 13, count 2 2006.257.06:41:49.01#ibcon#about to write, iclass 13, count 2 2006.257.06:41:49.01#ibcon#wrote, iclass 13, count 2 2006.257.06:41:49.01#ibcon#about to read 3, iclass 13, count 2 2006.257.06:41:49.04#ibcon#read 3, iclass 13, count 2 2006.257.06:41:49.04#ibcon#about to read 4, iclass 13, count 2 2006.257.06:41:49.04#ibcon#read 4, iclass 13, count 2 2006.257.06:41:49.04#ibcon#about to read 5, iclass 13, count 2 2006.257.06:41:49.04#ibcon#read 5, iclass 13, count 2 2006.257.06:41:49.04#ibcon#about to read 6, iclass 13, count 2 2006.257.06:41:49.04#ibcon#read 6, iclass 13, count 2 2006.257.06:41:49.04#ibcon#end of sib2, iclass 13, count 2 2006.257.06:41:49.04#ibcon#*after write, iclass 13, count 2 2006.257.06:41:49.04#ibcon#*before return 0, iclass 13, count 2 2006.257.06:41:49.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:41:49.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:41:49.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.06:41:49.04#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:49.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:41:49.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:41:49.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:41:49.16#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:41:49.16#ibcon#first serial, iclass 13, count 0 2006.257.06:41:49.16#ibcon#enter sib2, iclass 13, count 0 2006.257.06:41:49.16#ibcon#flushed, iclass 13, count 0 2006.257.06:41:49.16#ibcon#about to write, iclass 13, count 0 2006.257.06:41:49.16#ibcon#wrote, iclass 13, count 0 2006.257.06:41:49.16#ibcon#about to read 3, iclass 13, count 0 2006.257.06:41:49.18#ibcon#read 3, iclass 13, count 0 2006.257.06:41:49.18#ibcon#about to read 4, iclass 13, count 0 2006.257.06:41:49.18#ibcon#read 4, iclass 13, count 0 2006.257.06:41:49.18#ibcon#about to read 5, iclass 13, count 0 2006.257.06:41:49.18#ibcon#read 5, iclass 13, count 0 2006.257.06:41:49.18#ibcon#about to read 6, iclass 13, count 0 2006.257.06:41:49.18#ibcon#read 6, iclass 13, count 0 2006.257.06:41:49.18#ibcon#end of sib2, iclass 13, count 0 2006.257.06:41:49.18#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:41:49.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:41:49.18#ibcon#[27=USB\r\n] 2006.257.06:41:49.18#ibcon#*before write, iclass 13, count 0 2006.257.06:41:49.18#ibcon#enter sib2, iclass 13, count 0 2006.257.06:41:49.18#ibcon#flushed, iclass 13, count 0 2006.257.06:41:49.18#ibcon#about to write, iclass 13, count 0 2006.257.06:41:49.18#ibcon#wrote, iclass 13, count 0 2006.257.06:41:49.18#ibcon#about to read 3, iclass 13, count 0 2006.257.06:41:49.21#ibcon#read 3, iclass 13, count 0 2006.257.06:41:49.21#ibcon#about to read 4, iclass 13, count 0 2006.257.06:41:49.21#ibcon#read 4, iclass 13, count 0 2006.257.06:41:49.21#ibcon#about to read 5, iclass 13, count 0 2006.257.06:41:49.21#ibcon#read 5, iclass 13, count 0 2006.257.06:41:49.21#ibcon#about to read 6, iclass 13, count 0 2006.257.06:41:49.21#ibcon#read 6, iclass 13, count 0 2006.257.06:41:49.21#ibcon#end of sib2, iclass 13, count 0 2006.257.06:41:49.21#ibcon#*after write, iclass 13, count 0 2006.257.06:41:49.21#ibcon#*before return 0, iclass 13, count 0 2006.257.06:41:49.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:41:49.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:41:49.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:41:49.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:41:49.21$vck44/vblo=2,634.99 2006.257.06:41:49.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.06:41:49.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.06:41:49.21#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:49.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:49.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:49.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:49.21#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:41:49.21#ibcon#first serial, iclass 15, count 0 2006.257.06:41:49.21#ibcon#enter sib2, iclass 15, count 0 2006.257.06:41:49.21#ibcon#flushed, iclass 15, count 0 2006.257.06:41:49.21#ibcon#about to write, iclass 15, count 0 2006.257.06:41:49.21#ibcon#wrote, iclass 15, count 0 2006.257.06:41:49.21#ibcon#about to read 3, iclass 15, count 0 2006.257.06:41:49.23#ibcon#read 3, iclass 15, count 0 2006.257.06:41:49.23#ibcon#about to read 4, iclass 15, count 0 2006.257.06:41:49.23#ibcon#read 4, iclass 15, count 0 2006.257.06:41:49.23#ibcon#about to read 5, iclass 15, count 0 2006.257.06:41:49.23#ibcon#read 5, iclass 15, count 0 2006.257.06:41:49.23#ibcon#about to read 6, iclass 15, count 0 2006.257.06:41:49.23#ibcon#read 6, iclass 15, count 0 2006.257.06:41:49.23#ibcon#end of sib2, iclass 15, count 0 2006.257.06:41:49.23#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:41:49.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:41:49.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:41:49.23#ibcon#*before write, iclass 15, count 0 2006.257.06:41:49.23#ibcon#enter sib2, iclass 15, count 0 2006.257.06:41:49.23#ibcon#flushed, iclass 15, count 0 2006.257.06:41:49.23#ibcon#about to write, iclass 15, count 0 2006.257.06:41:49.23#ibcon#wrote, iclass 15, count 0 2006.257.06:41:49.23#ibcon#about to read 3, iclass 15, count 0 2006.257.06:41:49.27#ibcon#read 3, iclass 15, count 0 2006.257.06:41:49.27#ibcon#about to read 4, iclass 15, count 0 2006.257.06:41:49.27#ibcon#read 4, iclass 15, count 0 2006.257.06:41:49.27#ibcon#about to read 5, iclass 15, count 0 2006.257.06:41:49.27#ibcon#read 5, iclass 15, count 0 2006.257.06:41:49.27#ibcon#about to read 6, iclass 15, count 0 2006.257.06:41:49.27#ibcon#read 6, iclass 15, count 0 2006.257.06:41:49.27#ibcon#end of sib2, iclass 15, count 0 2006.257.06:41:49.27#ibcon#*after write, iclass 15, count 0 2006.257.06:41:49.27#ibcon#*before return 0, iclass 15, count 0 2006.257.06:41:49.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:49.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:41:49.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:41:49.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:41:49.27$vck44/vb=2,5 2006.257.06:41:49.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.06:41:49.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.06:41:49.27#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:49.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:49.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:49.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:49.33#ibcon#enter wrdev, iclass 17, count 2 2006.257.06:41:49.33#ibcon#first serial, iclass 17, count 2 2006.257.06:41:49.33#ibcon#enter sib2, iclass 17, count 2 2006.257.06:41:49.33#ibcon#flushed, iclass 17, count 2 2006.257.06:41:49.33#ibcon#about to write, iclass 17, count 2 2006.257.06:41:49.33#ibcon#wrote, iclass 17, count 2 2006.257.06:41:49.33#ibcon#about to read 3, iclass 17, count 2 2006.257.06:41:49.35#ibcon#read 3, iclass 17, count 2 2006.257.06:41:49.35#ibcon#about to read 4, iclass 17, count 2 2006.257.06:41:49.35#ibcon#read 4, iclass 17, count 2 2006.257.06:41:49.35#ibcon#about to read 5, iclass 17, count 2 2006.257.06:41:49.35#ibcon#read 5, iclass 17, count 2 2006.257.06:41:49.35#ibcon#about to read 6, iclass 17, count 2 2006.257.06:41:49.35#ibcon#read 6, iclass 17, count 2 2006.257.06:41:49.35#ibcon#end of sib2, iclass 17, count 2 2006.257.06:41:49.35#ibcon#*mode == 0, iclass 17, count 2 2006.257.06:41:49.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.06:41:49.35#ibcon#[27=AT02-05\r\n] 2006.257.06:41:49.35#ibcon#*before write, iclass 17, count 2 2006.257.06:41:49.35#ibcon#enter sib2, iclass 17, count 2 2006.257.06:41:49.35#ibcon#flushed, iclass 17, count 2 2006.257.06:41:49.35#ibcon#about to write, iclass 17, count 2 2006.257.06:41:49.35#ibcon#wrote, iclass 17, count 2 2006.257.06:41:49.35#ibcon#about to read 3, iclass 17, count 2 2006.257.06:41:49.38#ibcon#read 3, iclass 17, count 2 2006.257.06:41:49.38#ibcon#about to read 4, iclass 17, count 2 2006.257.06:41:49.38#ibcon#read 4, iclass 17, count 2 2006.257.06:41:49.38#ibcon#about to read 5, iclass 17, count 2 2006.257.06:41:49.38#ibcon#read 5, iclass 17, count 2 2006.257.06:41:49.38#ibcon#about to read 6, iclass 17, count 2 2006.257.06:41:49.38#ibcon#read 6, iclass 17, count 2 2006.257.06:41:49.38#ibcon#end of sib2, iclass 17, count 2 2006.257.06:41:49.38#ibcon#*after write, iclass 17, count 2 2006.257.06:41:49.38#ibcon#*before return 0, iclass 17, count 2 2006.257.06:41:49.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:49.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:41:49.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.06:41:49.38#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:49.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:49.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:49.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:49.50#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:41:49.50#ibcon#first serial, iclass 17, count 0 2006.257.06:41:49.50#ibcon#enter sib2, iclass 17, count 0 2006.257.06:41:49.50#ibcon#flushed, iclass 17, count 0 2006.257.06:41:49.50#ibcon#about to write, iclass 17, count 0 2006.257.06:41:49.50#ibcon#wrote, iclass 17, count 0 2006.257.06:41:49.50#ibcon#about to read 3, iclass 17, count 0 2006.257.06:41:49.52#ibcon#read 3, iclass 17, count 0 2006.257.06:41:49.52#ibcon#about to read 4, iclass 17, count 0 2006.257.06:41:49.52#ibcon#read 4, iclass 17, count 0 2006.257.06:41:49.52#ibcon#about to read 5, iclass 17, count 0 2006.257.06:41:49.52#ibcon#read 5, iclass 17, count 0 2006.257.06:41:49.52#ibcon#about to read 6, iclass 17, count 0 2006.257.06:41:49.52#ibcon#read 6, iclass 17, count 0 2006.257.06:41:49.52#ibcon#end of sib2, iclass 17, count 0 2006.257.06:41:49.52#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:41:49.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:41:49.52#ibcon#[27=USB\r\n] 2006.257.06:41:49.52#ibcon#*before write, iclass 17, count 0 2006.257.06:41:49.52#ibcon#enter sib2, iclass 17, count 0 2006.257.06:41:49.52#ibcon#flushed, iclass 17, count 0 2006.257.06:41:49.52#ibcon#about to write, iclass 17, count 0 2006.257.06:41:49.52#ibcon#wrote, iclass 17, count 0 2006.257.06:41:49.52#ibcon#about to read 3, iclass 17, count 0 2006.257.06:41:49.55#ibcon#read 3, iclass 17, count 0 2006.257.06:41:49.55#ibcon#about to read 4, iclass 17, count 0 2006.257.06:41:49.55#ibcon#read 4, iclass 17, count 0 2006.257.06:41:49.55#ibcon#about to read 5, iclass 17, count 0 2006.257.06:41:49.55#ibcon#read 5, iclass 17, count 0 2006.257.06:41:49.55#ibcon#about to read 6, iclass 17, count 0 2006.257.06:41:49.55#ibcon#read 6, iclass 17, count 0 2006.257.06:41:49.55#ibcon#end of sib2, iclass 17, count 0 2006.257.06:41:49.55#ibcon#*after write, iclass 17, count 0 2006.257.06:41:49.55#ibcon#*before return 0, iclass 17, count 0 2006.257.06:41:49.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:49.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:41:49.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:41:49.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:41:49.55$vck44/vblo=3,649.99 2006.257.06:41:49.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.06:41:49.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.06:41:49.55#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:49.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:49.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:49.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:49.55#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:41:49.55#ibcon#first serial, iclass 19, count 0 2006.257.06:41:49.55#ibcon#enter sib2, iclass 19, count 0 2006.257.06:41:49.55#ibcon#flushed, iclass 19, count 0 2006.257.06:41:49.55#ibcon#about to write, iclass 19, count 0 2006.257.06:41:49.55#ibcon#wrote, iclass 19, count 0 2006.257.06:41:49.55#ibcon#about to read 3, iclass 19, count 0 2006.257.06:41:49.57#ibcon#read 3, iclass 19, count 0 2006.257.06:41:49.57#ibcon#about to read 4, iclass 19, count 0 2006.257.06:41:49.57#ibcon#read 4, iclass 19, count 0 2006.257.06:41:49.57#ibcon#about to read 5, iclass 19, count 0 2006.257.06:41:49.57#ibcon#read 5, iclass 19, count 0 2006.257.06:41:49.57#ibcon#about to read 6, iclass 19, count 0 2006.257.06:41:49.57#ibcon#read 6, iclass 19, count 0 2006.257.06:41:49.57#ibcon#end of sib2, iclass 19, count 0 2006.257.06:41:49.57#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:41:49.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:41:49.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:41:49.57#ibcon#*before write, iclass 19, count 0 2006.257.06:41:49.57#ibcon#enter sib2, iclass 19, count 0 2006.257.06:41:49.57#ibcon#flushed, iclass 19, count 0 2006.257.06:41:49.57#ibcon#about to write, iclass 19, count 0 2006.257.06:41:49.57#ibcon#wrote, iclass 19, count 0 2006.257.06:41:49.57#ibcon#about to read 3, iclass 19, count 0 2006.257.06:41:49.61#ibcon#read 3, iclass 19, count 0 2006.257.06:41:49.61#ibcon#about to read 4, iclass 19, count 0 2006.257.06:41:49.61#ibcon#read 4, iclass 19, count 0 2006.257.06:41:49.61#ibcon#about to read 5, iclass 19, count 0 2006.257.06:41:49.61#ibcon#read 5, iclass 19, count 0 2006.257.06:41:49.61#ibcon#about to read 6, iclass 19, count 0 2006.257.06:41:49.61#ibcon#read 6, iclass 19, count 0 2006.257.06:41:49.61#ibcon#end of sib2, iclass 19, count 0 2006.257.06:41:49.61#ibcon#*after write, iclass 19, count 0 2006.257.06:41:49.61#ibcon#*before return 0, iclass 19, count 0 2006.257.06:41:49.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:49.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:41:49.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:41:49.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:41:49.61$vck44/vb=3,4 2006.257.06:41:49.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.06:41:49.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.06:41:49.61#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:49.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:49.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:49.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:49.67#ibcon#enter wrdev, iclass 21, count 2 2006.257.06:41:49.67#ibcon#first serial, iclass 21, count 2 2006.257.06:41:49.67#ibcon#enter sib2, iclass 21, count 2 2006.257.06:41:49.67#ibcon#flushed, iclass 21, count 2 2006.257.06:41:49.67#ibcon#about to write, iclass 21, count 2 2006.257.06:41:49.67#ibcon#wrote, iclass 21, count 2 2006.257.06:41:49.67#ibcon#about to read 3, iclass 21, count 2 2006.257.06:41:49.69#ibcon#read 3, iclass 21, count 2 2006.257.06:41:49.69#ibcon#about to read 4, iclass 21, count 2 2006.257.06:41:49.69#ibcon#read 4, iclass 21, count 2 2006.257.06:41:49.69#ibcon#about to read 5, iclass 21, count 2 2006.257.06:41:49.69#ibcon#read 5, iclass 21, count 2 2006.257.06:41:49.69#ibcon#about to read 6, iclass 21, count 2 2006.257.06:41:49.69#ibcon#read 6, iclass 21, count 2 2006.257.06:41:49.69#ibcon#end of sib2, iclass 21, count 2 2006.257.06:41:49.69#ibcon#*mode == 0, iclass 21, count 2 2006.257.06:41:49.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.06:41:49.69#ibcon#[27=AT03-04\r\n] 2006.257.06:41:49.69#ibcon#*before write, iclass 21, count 2 2006.257.06:41:49.69#ibcon#enter sib2, iclass 21, count 2 2006.257.06:41:49.69#ibcon#flushed, iclass 21, count 2 2006.257.06:41:49.69#ibcon#about to write, iclass 21, count 2 2006.257.06:41:49.69#ibcon#wrote, iclass 21, count 2 2006.257.06:41:49.69#ibcon#about to read 3, iclass 21, count 2 2006.257.06:41:49.72#ibcon#read 3, iclass 21, count 2 2006.257.06:41:49.72#ibcon#about to read 4, iclass 21, count 2 2006.257.06:41:49.72#ibcon#read 4, iclass 21, count 2 2006.257.06:41:49.72#ibcon#about to read 5, iclass 21, count 2 2006.257.06:41:49.72#ibcon#read 5, iclass 21, count 2 2006.257.06:41:49.72#ibcon#about to read 6, iclass 21, count 2 2006.257.06:41:49.72#ibcon#read 6, iclass 21, count 2 2006.257.06:41:49.72#ibcon#end of sib2, iclass 21, count 2 2006.257.06:41:49.72#ibcon#*after write, iclass 21, count 2 2006.257.06:41:49.72#ibcon#*before return 0, iclass 21, count 2 2006.257.06:41:49.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:49.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:41:49.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.06:41:49.72#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:49.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:49.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:49.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:49.84#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:41:49.84#ibcon#first serial, iclass 21, count 0 2006.257.06:41:49.84#ibcon#enter sib2, iclass 21, count 0 2006.257.06:41:49.84#ibcon#flushed, iclass 21, count 0 2006.257.06:41:49.84#ibcon#about to write, iclass 21, count 0 2006.257.06:41:49.84#ibcon#wrote, iclass 21, count 0 2006.257.06:41:49.84#ibcon#about to read 3, iclass 21, count 0 2006.257.06:41:49.86#ibcon#read 3, iclass 21, count 0 2006.257.06:41:49.86#ibcon#about to read 4, iclass 21, count 0 2006.257.06:41:49.86#ibcon#read 4, iclass 21, count 0 2006.257.06:41:49.86#ibcon#about to read 5, iclass 21, count 0 2006.257.06:41:49.86#ibcon#read 5, iclass 21, count 0 2006.257.06:41:49.86#ibcon#about to read 6, iclass 21, count 0 2006.257.06:41:49.86#ibcon#read 6, iclass 21, count 0 2006.257.06:41:49.86#ibcon#end of sib2, iclass 21, count 0 2006.257.06:41:49.86#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:41:49.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:41:49.86#ibcon#[27=USB\r\n] 2006.257.06:41:49.86#ibcon#*before write, iclass 21, count 0 2006.257.06:41:49.86#ibcon#enter sib2, iclass 21, count 0 2006.257.06:41:49.86#ibcon#flushed, iclass 21, count 0 2006.257.06:41:49.86#ibcon#about to write, iclass 21, count 0 2006.257.06:41:49.86#ibcon#wrote, iclass 21, count 0 2006.257.06:41:49.86#ibcon#about to read 3, iclass 21, count 0 2006.257.06:41:49.89#ibcon#read 3, iclass 21, count 0 2006.257.06:41:49.89#ibcon#about to read 4, iclass 21, count 0 2006.257.06:41:49.89#ibcon#read 4, iclass 21, count 0 2006.257.06:41:49.89#ibcon#about to read 5, iclass 21, count 0 2006.257.06:41:49.89#ibcon#read 5, iclass 21, count 0 2006.257.06:41:49.89#ibcon#about to read 6, iclass 21, count 0 2006.257.06:41:49.89#ibcon#read 6, iclass 21, count 0 2006.257.06:41:49.89#ibcon#end of sib2, iclass 21, count 0 2006.257.06:41:49.89#ibcon#*after write, iclass 21, count 0 2006.257.06:41:49.89#ibcon#*before return 0, iclass 21, count 0 2006.257.06:41:49.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:49.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:41:49.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:41:49.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:41:49.89$vck44/vblo=4,679.99 2006.257.06:41:49.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.06:41:49.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.06:41:49.89#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:49.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:49.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:49.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:49.89#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:41:49.89#ibcon#first serial, iclass 23, count 0 2006.257.06:41:49.89#ibcon#enter sib2, iclass 23, count 0 2006.257.06:41:49.89#ibcon#flushed, iclass 23, count 0 2006.257.06:41:49.89#ibcon#about to write, iclass 23, count 0 2006.257.06:41:49.89#ibcon#wrote, iclass 23, count 0 2006.257.06:41:49.89#ibcon#about to read 3, iclass 23, count 0 2006.257.06:41:49.91#ibcon#read 3, iclass 23, count 0 2006.257.06:41:49.91#ibcon#about to read 4, iclass 23, count 0 2006.257.06:41:49.91#ibcon#read 4, iclass 23, count 0 2006.257.06:41:49.91#ibcon#about to read 5, iclass 23, count 0 2006.257.06:41:49.91#ibcon#read 5, iclass 23, count 0 2006.257.06:41:49.91#ibcon#about to read 6, iclass 23, count 0 2006.257.06:41:49.91#ibcon#read 6, iclass 23, count 0 2006.257.06:41:49.91#ibcon#end of sib2, iclass 23, count 0 2006.257.06:41:49.91#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:41:49.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:41:49.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:41:49.91#ibcon#*before write, iclass 23, count 0 2006.257.06:41:49.91#ibcon#enter sib2, iclass 23, count 0 2006.257.06:41:49.91#ibcon#flushed, iclass 23, count 0 2006.257.06:41:49.91#ibcon#about to write, iclass 23, count 0 2006.257.06:41:49.91#ibcon#wrote, iclass 23, count 0 2006.257.06:41:49.91#ibcon#about to read 3, iclass 23, count 0 2006.257.06:41:49.95#ibcon#read 3, iclass 23, count 0 2006.257.06:41:49.95#ibcon#about to read 4, iclass 23, count 0 2006.257.06:41:49.95#ibcon#read 4, iclass 23, count 0 2006.257.06:41:49.95#ibcon#about to read 5, iclass 23, count 0 2006.257.06:41:49.95#ibcon#read 5, iclass 23, count 0 2006.257.06:41:49.95#ibcon#about to read 6, iclass 23, count 0 2006.257.06:41:49.95#ibcon#read 6, iclass 23, count 0 2006.257.06:41:49.95#ibcon#end of sib2, iclass 23, count 0 2006.257.06:41:49.95#ibcon#*after write, iclass 23, count 0 2006.257.06:41:49.95#ibcon#*before return 0, iclass 23, count 0 2006.257.06:41:49.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:49.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:41:49.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:41:49.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:41:49.95$vck44/vb=4,5 2006.257.06:41:49.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.06:41:49.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.06:41:49.95#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:49.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:50.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:50.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:50.01#ibcon#enter wrdev, iclass 25, count 2 2006.257.06:41:50.01#ibcon#first serial, iclass 25, count 2 2006.257.06:41:50.01#ibcon#enter sib2, iclass 25, count 2 2006.257.06:41:50.01#ibcon#flushed, iclass 25, count 2 2006.257.06:41:50.01#ibcon#about to write, iclass 25, count 2 2006.257.06:41:50.01#ibcon#wrote, iclass 25, count 2 2006.257.06:41:50.01#ibcon#about to read 3, iclass 25, count 2 2006.257.06:41:50.03#ibcon#read 3, iclass 25, count 2 2006.257.06:41:50.03#ibcon#about to read 4, iclass 25, count 2 2006.257.06:41:50.03#ibcon#read 4, iclass 25, count 2 2006.257.06:41:50.03#ibcon#about to read 5, iclass 25, count 2 2006.257.06:41:50.03#ibcon#read 5, iclass 25, count 2 2006.257.06:41:50.03#ibcon#about to read 6, iclass 25, count 2 2006.257.06:41:50.03#ibcon#read 6, iclass 25, count 2 2006.257.06:41:50.03#ibcon#end of sib2, iclass 25, count 2 2006.257.06:41:50.03#ibcon#*mode == 0, iclass 25, count 2 2006.257.06:41:50.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.06:41:50.03#ibcon#[27=AT04-05\r\n] 2006.257.06:41:50.03#ibcon#*before write, iclass 25, count 2 2006.257.06:41:50.03#ibcon#enter sib2, iclass 25, count 2 2006.257.06:41:50.03#ibcon#flushed, iclass 25, count 2 2006.257.06:41:50.03#ibcon#about to write, iclass 25, count 2 2006.257.06:41:50.03#ibcon#wrote, iclass 25, count 2 2006.257.06:41:50.03#ibcon#about to read 3, iclass 25, count 2 2006.257.06:41:50.06#ibcon#read 3, iclass 25, count 2 2006.257.06:41:50.06#ibcon#about to read 4, iclass 25, count 2 2006.257.06:41:50.06#ibcon#read 4, iclass 25, count 2 2006.257.06:41:50.06#ibcon#about to read 5, iclass 25, count 2 2006.257.06:41:50.06#ibcon#read 5, iclass 25, count 2 2006.257.06:41:50.06#ibcon#about to read 6, iclass 25, count 2 2006.257.06:41:50.06#ibcon#read 6, iclass 25, count 2 2006.257.06:41:50.06#ibcon#end of sib2, iclass 25, count 2 2006.257.06:41:50.06#ibcon#*after write, iclass 25, count 2 2006.257.06:41:50.06#ibcon#*before return 0, iclass 25, count 2 2006.257.06:41:50.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:50.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:41:50.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.06:41:50.06#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:50.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:50.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:50.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:50.18#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:41:50.18#ibcon#first serial, iclass 25, count 0 2006.257.06:41:50.18#ibcon#enter sib2, iclass 25, count 0 2006.257.06:41:50.18#ibcon#flushed, iclass 25, count 0 2006.257.06:41:50.18#ibcon#about to write, iclass 25, count 0 2006.257.06:41:50.18#ibcon#wrote, iclass 25, count 0 2006.257.06:41:50.18#ibcon#about to read 3, iclass 25, count 0 2006.257.06:41:50.20#ibcon#read 3, iclass 25, count 0 2006.257.06:41:50.20#ibcon#about to read 4, iclass 25, count 0 2006.257.06:41:50.20#ibcon#read 4, iclass 25, count 0 2006.257.06:41:50.20#ibcon#about to read 5, iclass 25, count 0 2006.257.06:41:50.20#ibcon#read 5, iclass 25, count 0 2006.257.06:41:50.20#ibcon#about to read 6, iclass 25, count 0 2006.257.06:41:50.20#ibcon#read 6, iclass 25, count 0 2006.257.06:41:50.20#ibcon#end of sib2, iclass 25, count 0 2006.257.06:41:50.20#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:41:50.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:41:50.20#ibcon#[27=USB\r\n] 2006.257.06:41:50.20#ibcon#*before write, iclass 25, count 0 2006.257.06:41:50.20#ibcon#enter sib2, iclass 25, count 0 2006.257.06:41:50.20#ibcon#flushed, iclass 25, count 0 2006.257.06:41:50.20#ibcon#about to write, iclass 25, count 0 2006.257.06:41:50.20#ibcon#wrote, iclass 25, count 0 2006.257.06:41:50.20#ibcon#about to read 3, iclass 25, count 0 2006.257.06:41:50.23#ibcon#read 3, iclass 25, count 0 2006.257.06:41:50.23#ibcon#about to read 4, iclass 25, count 0 2006.257.06:41:50.23#ibcon#read 4, iclass 25, count 0 2006.257.06:41:50.23#ibcon#about to read 5, iclass 25, count 0 2006.257.06:41:50.23#ibcon#read 5, iclass 25, count 0 2006.257.06:41:50.23#ibcon#about to read 6, iclass 25, count 0 2006.257.06:41:50.23#ibcon#read 6, iclass 25, count 0 2006.257.06:41:50.23#ibcon#end of sib2, iclass 25, count 0 2006.257.06:41:50.23#ibcon#*after write, iclass 25, count 0 2006.257.06:41:50.23#ibcon#*before return 0, iclass 25, count 0 2006.257.06:41:50.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:50.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:41:50.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:41:50.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:41:50.23$vck44/vblo=5,709.99 2006.257.06:41:50.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.06:41:50.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.06:41:50.23#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:50.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:50.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:50.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:50.23#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:41:50.23#ibcon#first serial, iclass 27, count 0 2006.257.06:41:50.23#ibcon#enter sib2, iclass 27, count 0 2006.257.06:41:50.23#ibcon#flushed, iclass 27, count 0 2006.257.06:41:50.23#ibcon#about to write, iclass 27, count 0 2006.257.06:41:50.23#ibcon#wrote, iclass 27, count 0 2006.257.06:41:50.23#ibcon#about to read 3, iclass 27, count 0 2006.257.06:41:50.25#ibcon#read 3, iclass 27, count 0 2006.257.06:41:50.25#ibcon#about to read 4, iclass 27, count 0 2006.257.06:41:50.25#ibcon#read 4, iclass 27, count 0 2006.257.06:41:50.25#ibcon#about to read 5, iclass 27, count 0 2006.257.06:41:50.25#ibcon#read 5, iclass 27, count 0 2006.257.06:41:50.25#ibcon#about to read 6, iclass 27, count 0 2006.257.06:41:50.25#ibcon#read 6, iclass 27, count 0 2006.257.06:41:50.25#ibcon#end of sib2, iclass 27, count 0 2006.257.06:41:50.25#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:41:50.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:41:50.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:41:50.25#ibcon#*before write, iclass 27, count 0 2006.257.06:41:50.25#ibcon#enter sib2, iclass 27, count 0 2006.257.06:41:50.25#ibcon#flushed, iclass 27, count 0 2006.257.06:41:50.25#ibcon#about to write, iclass 27, count 0 2006.257.06:41:50.25#ibcon#wrote, iclass 27, count 0 2006.257.06:41:50.25#ibcon#about to read 3, iclass 27, count 0 2006.257.06:41:50.29#ibcon#read 3, iclass 27, count 0 2006.257.06:41:50.29#ibcon#about to read 4, iclass 27, count 0 2006.257.06:41:50.29#ibcon#read 4, iclass 27, count 0 2006.257.06:41:50.29#ibcon#about to read 5, iclass 27, count 0 2006.257.06:41:50.29#ibcon#read 5, iclass 27, count 0 2006.257.06:41:50.29#ibcon#about to read 6, iclass 27, count 0 2006.257.06:41:50.29#ibcon#read 6, iclass 27, count 0 2006.257.06:41:50.29#ibcon#end of sib2, iclass 27, count 0 2006.257.06:41:50.29#ibcon#*after write, iclass 27, count 0 2006.257.06:41:50.29#ibcon#*before return 0, iclass 27, count 0 2006.257.06:41:50.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:50.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:41:50.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:41:50.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:41:50.29$vck44/vb=5,4 2006.257.06:41:50.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.06:41:50.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.06:41:50.29#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:50.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:50.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:50.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:50.35#ibcon#enter wrdev, iclass 29, count 2 2006.257.06:41:50.35#ibcon#first serial, iclass 29, count 2 2006.257.06:41:50.35#ibcon#enter sib2, iclass 29, count 2 2006.257.06:41:50.35#ibcon#flushed, iclass 29, count 2 2006.257.06:41:50.35#ibcon#about to write, iclass 29, count 2 2006.257.06:41:50.35#ibcon#wrote, iclass 29, count 2 2006.257.06:41:50.35#ibcon#about to read 3, iclass 29, count 2 2006.257.06:41:50.37#ibcon#read 3, iclass 29, count 2 2006.257.06:41:50.37#ibcon#about to read 4, iclass 29, count 2 2006.257.06:41:50.37#ibcon#read 4, iclass 29, count 2 2006.257.06:41:50.37#ibcon#about to read 5, iclass 29, count 2 2006.257.06:41:50.37#ibcon#read 5, iclass 29, count 2 2006.257.06:41:50.37#ibcon#about to read 6, iclass 29, count 2 2006.257.06:41:50.37#ibcon#read 6, iclass 29, count 2 2006.257.06:41:50.37#ibcon#end of sib2, iclass 29, count 2 2006.257.06:41:50.37#ibcon#*mode == 0, iclass 29, count 2 2006.257.06:41:50.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.06:41:50.37#ibcon#[27=AT05-04\r\n] 2006.257.06:41:50.37#ibcon#*before write, iclass 29, count 2 2006.257.06:41:50.37#ibcon#enter sib2, iclass 29, count 2 2006.257.06:41:50.37#ibcon#flushed, iclass 29, count 2 2006.257.06:41:50.37#ibcon#about to write, iclass 29, count 2 2006.257.06:41:50.37#ibcon#wrote, iclass 29, count 2 2006.257.06:41:50.37#ibcon#about to read 3, iclass 29, count 2 2006.257.06:41:50.40#ibcon#read 3, iclass 29, count 2 2006.257.06:41:50.40#ibcon#about to read 4, iclass 29, count 2 2006.257.06:41:50.40#ibcon#read 4, iclass 29, count 2 2006.257.06:41:50.40#ibcon#about to read 5, iclass 29, count 2 2006.257.06:41:50.40#ibcon#read 5, iclass 29, count 2 2006.257.06:41:50.40#ibcon#about to read 6, iclass 29, count 2 2006.257.06:41:50.40#ibcon#read 6, iclass 29, count 2 2006.257.06:41:50.40#ibcon#end of sib2, iclass 29, count 2 2006.257.06:41:50.40#ibcon#*after write, iclass 29, count 2 2006.257.06:41:50.40#ibcon#*before return 0, iclass 29, count 2 2006.257.06:41:50.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:50.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:41:50.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.06:41:50.40#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:50.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:50.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:50.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:50.52#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:41:50.52#ibcon#first serial, iclass 29, count 0 2006.257.06:41:50.52#ibcon#enter sib2, iclass 29, count 0 2006.257.06:41:50.52#ibcon#flushed, iclass 29, count 0 2006.257.06:41:50.52#ibcon#about to write, iclass 29, count 0 2006.257.06:41:50.52#ibcon#wrote, iclass 29, count 0 2006.257.06:41:50.52#ibcon#about to read 3, iclass 29, count 0 2006.257.06:41:50.54#ibcon#read 3, iclass 29, count 0 2006.257.06:41:50.54#ibcon#about to read 4, iclass 29, count 0 2006.257.06:41:50.54#ibcon#read 4, iclass 29, count 0 2006.257.06:41:50.54#ibcon#about to read 5, iclass 29, count 0 2006.257.06:41:50.54#ibcon#read 5, iclass 29, count 0 2006.257.06:41:50.54#ibcon#about to read 6, iclass 29, count 0 2006.257.06:41:50.54#ibcon#read 6, iclass 29, count 0 2006.257.06:41:50.54#ibcon#end of sib2, iclass 29, count 0 2006.257.06:41:50.54#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:41:50.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:41:50.54#ibcon#[27=USB\r\n] 2006.257.06:41:50.54#ibcon#*before write, iclass 29, count 0 2006.257.06:41:50.54#ibcon#enter sib2, iclass 29, count 0 2006.257.06:41:50.54#ibcon#flushed, iclass 29, count 0 2006.257.06:41:50.54#ibcon#about to write, iclass 29, count 0 2006.257.06:41:50.54#ibcon#wrote, iclass 29, count 0 2006.257.06:41:50.54#ibcon#about to read 3, iclass 29, count 0 2006.257.06:41:50.57#ibcon#read 3, iclass 29, count 0 2006.257.06:41:50.57#ibcon#about to read 4, iclass 29, count 0 2006.257.06:41:50.57#ibcon#read 4, iclass 29, count 0 2006.257.06:41:50.57#ibcon#about to read 5, iclass 29, count 0 2006.257.06:41:50.57#ibcon#read 5, iclass 29, count 0 2006.257.06:41:50.57#ibcon#about to read 6, iclass 29, count 0 2006.257.06:41:50.57#ibcon#read 6, iclass 29, count 0 2006.257.06:41:50.57#ibcon#end of sib2, iclass 29, count 0 2006.257.06:41:50.57#ibcon#*after write, iclass 29, count 0 2006.257.06:41:50.57#ibcon#*before return 0, iclass 29, count 0 2006.257.06:41:50.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:50.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:41:50.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:41:50.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:41:50.57$vck44/vblo=6,719.99 2006.257.06:41:50.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.06:41:50.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.06:41:50.57#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:50.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:50.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:50.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:50.57#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:41:50.57#ibcon#first serial, iclass 31, count 0 2006.257.06:41:50.57#ibcon#enter sib2, iclass 31, count 0 2006.257.06:41:50.57#ibcon#flushed, iclass 31, count 0 2006.257.06:41:50.57#ibcon#about to write, iclass 31, count 0 2006.257.06:41:50.57#ibcon#wrote, iclass 31, count 0 2006.257.06:41:50.57#ibcon#about to read 3, iclass 31, count 0 2006.257.06:41:50.59#ibcon#read 3, iclass 31, count 0 2006.257.06:41:50.59#ibcon#about to read 4, iclass 31, count 0 2006.257.06:41:50.59#ibcon#read 4, iclass 31, count 0 2006.257.06:41:50.59#ibcon#about to read 5, iclass 31, count 0 2006.257.06:41:50.59#ibcon#read 5, iclass 31, count 0 2006.257.06:41:50.59#ibcon#about to read 6, iclass 31, count 0 2006.257.06:41:50.59#ibcon#read 6, iclass 31, count 0 2006.257.06:41:50.59#ibcon#end of sib2, iclass 31, count 0 2006.257.06:41:50.59#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:41:50.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:41:50.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:41:50.59#ibcon#*before write, iclass 31, count 0 2006.257.06:41:50.59#ibcon#enter sib2, iclass 31, count 0 2006.257.06:41:50.59#ibcon#flushed, iclass 31, count 0 2006.257.06:41:50.59#ibcon#about to write, iclass 31, count 0 2006.257.06:41:50.59#ibcon#wrote, iclass 31, count 0 2006.257.06:41:50.59#ibcon#about to read 3, iclass 31, count 0 2006.257.06:41:50.63#ibcon#read 3, iclass 31, count 0 2006.257.06:41:50.63#ibcon#about to read 4, iclass 31, count 0 2006.257.06:41:50.63#ibcon#read 4, iclass 31, count 0 2006.257.06:41:50.63#ibcon#about to read 5, iclass 31, count 0 2006.257.06:41:50.63#ibcon#read 5, iclass 31, count 0 2006.257.06:41:50.63#ibcon#about to read 6, iclass 31, count 0 2006.257.06:41:50.63#ibcon#read 6, iclass 31, count 0 2006.257.06:41:50.63#ibcon#end of sib2, iclass 31, count 0 2006.257.06:41:50.63#ibcon#*after write, iclass 31, count 0 2006.257.06:41:50.63#ibcon#*before return 0, iclass 31, count 0 2006.257.06:41:50.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:50.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:41:50.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:41:50.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:41:50.63$vck44/vb=6,4 2006.257.06:41:50.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.06:41:50.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.06:41:50.63#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:50.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:50.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:50.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:50.69#ibcon#enter wrdev, iclass 33, count 2 2006.257.06:41:50.69#ibcon#first serial, iclass 33, count 2 2006.257.06:41:50.69#ibcon#enter sib2, iclass 33, count 2 2006.257.06:41:50.69#ibcon#flushed, iclass 33, count 2 2006.257.06:41:50.69#ibcon#about to write, iclass 33, count 2 2006.257.06:41:50.69#ibcon#wrote, iclass 33, count 2 2006.257.06:41:50.69#ibcon#about to read 3, iclass 33, count 2 2006.257.06:41:50.71#ibcon#read 3, iclass 33, count 2 2006.257.06:41:50.71#ibcon#about to read 4, iclass 33, count 2 2006.257.06:41:50.71#ibcon#read 4, iclass 33, count 2 2006.257.06:41:50.71#ibcon#about to read 5, iclass 33, count 2 2006.257.06:41:50.71#ibcon#read 5, iclass 33, count 2 2006.257.06:41:50.71#ibcon#about to read 6, iclass 33, count 2 2006.257.06:41:50.71#ibcon#read 6, iclass 33, count 2 2006.257.06:41:50.71#ibcon#end of sib2, iclass 33, count 2 2006.257.06:41:50.71#ibcon#*mode == 0, iclass 33, count 2 2006.257.06:41:50.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.06:41:50.71#ibcon#[27=AT06-04\r\n] 2006.257.06:41:50.71#ibcon#*before write, iclass 33, count 2 2006.257.06:41:50.71#ibcon#enter sib2, iclass 33, count 2 2006.257.06:41:50.71#ibcon#flushed, iclass 33, count 2 2006.257.06:41:50.71#ibcon#about to write, iclass 33, count 2 2006.257.06:41:50.71#ibcon#wrote, iclass 33, count 2 2006.257.06:41:50.71#ibcon#about to read 3, iclass 33, count 2 2006.257.06:41:50.74#ibcon#read 3, iclass 33, count 2 2006.257.06:41:50.74#ibcon#about to read 4, iclass 33, count 2 2006.257.06:41:50.74#ibcon#read 4, iclass 33, count 2 2006.257.06:41:50.74#ibcon#about to read 5, iclass 33, count 2 2006.257.06:41:50.74#ibcon#read 5, iclass 33, count 2 2006.257.06:41:50.74#ibcon#about to read 6, iclass 33, count 2 2006.257.06:41:50.74#ibcon#read 6, iclass 33, count 2 2006.257.06:41:50.74#ibcon#end of sib2, iclass 33, count 2 2006.257.06:41:50.74#ibcon#*after write, iclass 33, count 2 2006.257.06:41:50.74#ibcon#*before return 0, iclass 33, count 2 2006.257.06:41:50.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:50.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:41:50.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.06:41:50.74#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:50.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:50.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:50.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:50.86#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:41:50.86#ibcon#first serial, iclass 33, count 0 2006.257.06:41:50.86#ibcon#enter sib2, iclass 33, count 0 2006.257.06:41:50.86#ibcon#flushed, iclass 33, count 0 2006.257.06:41:50.86#ibcon#about to write, iclass 33, count 0 2006.257.06:41:50.86#ibcon#wrote, iclass 33, count 0 2006.257.06:41:50.86#ibcon#about to read 3, iclass 33, count 0 2006.257.06:41:50.88#ibcon#read 3, iclass 33, count 0 2006.257.06:41:50.88#ibcon#about to read 4, iclass 33, count 0 2006.257.06:41:50.88#ibcon#read 4, iclass 33, count 0 2006.257.06:41:50.88#ibcon#about to read 5, iclass 33, count 0 2006.257.06:41:50.88#ibcon#read 5, iclass 33, count 0 2006.257.06:41:50.88#ibcon#about to read 6, iclass 33, count 0 2006.257.06:41:50.88#ibcon#read 6, iclass 33, count 0 2006.257.06:41:50.88#ibcon#end of sib2, iclass 33, count 0 2006.257.06:41:50.88#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:41:50.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:41:50.88#ibcon#[27=USB\r\n] 2006.257.06:41:50.88#ibcon#*before write, iclass 33, count 0 2006.257.06:41:50.88#ibcon#enter sib2, iclass 33, count 0 2006.257.06:41:50.88#ibcon#flushed, iclass 33, count 0 2006.257.06:41:50.88#ibcon#about to write, iclass 33, count 0 2006.257.06:41:50.88#ibcon#wrote, iclass 33, count 0 2006.257.06:41:50.88#ibcon#about to read 3, iclass 33, count 0 2006.257.06:41:50.91#ibcon#read 3, iclass 33, count 0 2006.257.06:41:50.91#ibcon#about to read 4, iclass 33, count 0 2006.257.06:41:50.91#ibcon#read 4, iclass 33, count 0 2006.257.06:41:50.91#ibcon#about to read 5, iclass 33, count 0 2006.257.06:41:50.91#ibcon#read 5, iclass 33, count 0 2006.257.06:41:50.91#ibcon#about to read 6, iclass 33, count 0 2006.257.06:41:50.91#ibcon#read 6, iclass 33, count 0 2006.257.06:41:50.91#ibcon#end of sib2, iclass 33, count 0 2006.257.06:41:50.91#ibcon#*after write, iclass 33, count 0 2006.257.06:41:50.91#ibcon#*before return 0, iclass 33, count 0 2006.257.06:41:50.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:50.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:41:50.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:41:50.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:41:50.91$vck44/vblo=7,734.99 2006.257.06:41:50.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:41:50.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:41:50.91#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:50.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:50.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:50.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:50.91#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:41:50.91#ibcon#first serial, iclass 35, count 0 2006.257.06:41:50.91#ibcon#enter sib2, iclass 35, count 0 2006.257.06:41:50.91#ibcon#flushed, iclass 35, count 0 2006.257.06:41:50.91#ibcon#about to write, iclass 35, count 0 2006.257.06:41:50.91#ibcon#wrote, iclass 35, count 0 2006.257.06:41:50.91#ibcon#about to read 3, iclass 35, count 0 2006.257.06:41:50.93#ibcon#read 3, iclass 35, count 0 2006.257.06:41:50.93#ibcon#about to read 4, iclass 35, count 0 2006.257.06:41:50.93#ibcon#read 4, iclass 35, count 0 2006.257.06:41:50.93#ibcon#about to read 5, iclass 35, count 0 2006.257.06:41:50.93#ibcon#read 5, iclass 35, count 0 2006.257.06:41:50.93#ibcon#about to read 6, iclass 35, count 0 2006.257.06:41:50.93#ibcon#read 6, iclass 35, count 0 2006.257.06:41:50.93#ibcon#end of sib2, iclass 35, count 0 2006.257.06:41:50.93#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:41:50.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:41:50.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:41:50.93#ibcon#*before write, iclass 35, count 0 2006.257.06:41:50.93#ibcon#enter sib2, iclass 35, count 0 2006.257.06:41:50.93#ibcon#flushed, iclass 35, count 0 2006.257.06:41:50.93#ibcon#about to write, iclass 35, count 0 2006.257.06:41:50.93#ibcon#wrote, iclass 35, count 0 2006.257.06:41:50.93#ibcon#about to read 3, iclass 35, count 0 2006.257.06:41:50.97#ibcon#read 3, iclass 35, count 0 2006.257.06:41:50.97#ibcon#about to read 4, iclass 35, count 0 2006.257.06:41:50.97#ibcon#read 4, iclass 35, count 0 2006.257.06:41:50.97#ibcon#about to read 5, iclass 35, count 0 2006.257.06:41:50.97#ibcon#read 5, iclass 35, count 0 2006.257.06:41:50.97#ibcon#about to read 6, iclass 35, count 0 2006.257.06:41:50.97#ibcon#read 6, iclass 35, count 0 2006.257.06:41:50.97#ibcon#end of sib2, iclass 35, count 0 2006.257.06:41:50.97#ibcon#*after write, iclass 35, count 0 2006.257.06:41:50.97#ibcon#*before return 0, iclass 35, count 0 2006.257.06:41:50.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:50.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:41:50.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:41:50.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:41:50.97$vck44/vb=7,4 2006.257.06:41:50.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.06:41:50.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.06:41:50.97#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:50.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:51.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:51.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:51.03#ibcon#enter wrdev, iclass 37, count 2 2006.257.06:41:51.03#ibcon#first serial, iclass 37, count 2 2006.257.06:41:51.03#ibcon#enter sib2, iclass 37, count 2 2006.257.06:41:51.03#ibcon#flushed, iclass 37, count 2 2006.257.06:41:51.03#ibcon#about to write, iclass 37, count 2 2006.257.06:41:51.03#ibcon#wrote, iclass 37, count 2 2006.257.06:41:51.03#ibcon#about to read 3, iclass 37, count 2 2006.257.06:41:51.05#ibcon#read 3, iclass 37, count 2 2006.257.06:41:51.05#ibcon#about to read 4, iclass 37, count 2 2006.257.06:41:51.05#ibcon#read 4, iclass 37, count 2 2006.257.06:41:51.05#ibcon#about to read 5, iclass 37, count 2 2006.257.06:41:51.05#ibcon#read 5, iclass 37, count 2 2006.257.06:41:51.05#ibcon#about to read 6, iclass 37, count 2 2006.257.06:41:51.05#ibcon#read 6, iclass 37, count 2 2006.257.06:41:51.05#ibcon#end of sib2, iclass 37, count 2 2006.257.06:41:51.05#ibcon#*mode == 0, iclass 37, count 2 2006.257.06:41:51.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.06:41:51.05#ibcon#[27=AT07-04\r\n] 2006.257.06:41:51.05#ibcon#*before write, iclass 37, count 2 2006.257.06:41:51.05#ibcon#enter sib2, iclass 37, count 2 2006.257.06:41:51.05#ibcon#flushed, iclass 37, count 2 2006.257.06:41:51.05#ibcon#about to write, iclass 37, count 2 2006.257.06:41:51.05#ibcon#wrote, iclass 37, count 2 2006.257.06:41:51.05#ibcon#about to read 3, iclass 37, count 2 2006.257.06:41:51.08#ibcon#read 3, iclass 37, count 2 2006.257.06:41:51.08#ibcon#about to read 4, iclass 37, count 2 2006.257.06:41:51.08#ibcon#read 4, iclass 37, count 2 2006.257.06:41:51.08#ibcon#about to read 5, iclass 37, count 2 2006.257.06:41:51.08#ibcon#read 5, iclass 37, count 2 2006.257.06:41:51.08#ibcon#about to read 6, iclass 37, count 2 2006.257.06:41:51.08#ibcon#read 6, iclass 37, count 2 2006.257.06:41:51.08#ibcon#end of sib2, iclass 37, count 2 2006.257.06:41:51.08#ibcon#*after write, iclass 37, count 2 2006.257.06:41:51.08#ibcon#*before return 0, iclass 37, count 2 2006.257.06:41:51.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:51.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:41:51.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.06:41:51.08#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:51.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:51.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:51.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:51.20#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:41:51.20#ibcon#first serial, iclass 37, count 0 2006.257.06:41:51.20#ibcon#enter sib2, iclass 37, count 0 2006.257.06:41:51.20#ibcon#flushed, iclass 37, count 0 2006.257.06:41:51.20#ibcon#about to write, iclass 37, count 0 2006.257.06:41:51.20#ibcon#wrote, iclass 37, count 0 2006.257.06:41:51.20#ibcon#about to read 3, iclass 37, count 0 2006.257.06:41:51.22#ibcon#read 3, iclass 37, count 0 2006.257.06:41:51.22#ibcon#about to read 4, iclass 37, count 0 2006.257.06:41:51.22#ibcon#read 4, iclass 37, count 0 2006.257.06:41:51.22#ibcon#about to read 5, iclass 37, count 0 2006.257.06:41:51.22#ibcon#read 5, iclass 37, count 0 2006.257.06:41:51.22#ibcon#about to read 6, iclass 37, count 0 2006.257.06:41:51.22#ibcon#read 6, iclass 37, count 0 2006.257.06:41:51.22#ibcon#end of sib2, iclass 37, count 0 2006.257.06:41:51.22#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:41:51.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:41:51.22#ibcon#[27=USB\r\n] 2006.257.06:41:51.22#ibcon#*before write, iclass 37, count 0 2006.257.06:41:51.22#ibcon#enter sib2, iclass 37, count 0 2006.257.06:41:51.22#ibcon#flushed, iclass 37, count 0 2006.257.06:41:51.22#ibcon#about to write, iclass 37, count 0 2006.257.06:41:51.22#ibcon#wrote, iclass 37, count 0 2006.257.06:41:51.22#ibcon#about to read 3, iclass 37, count 0 2006.257.06:41:51.25#ibcon#read 3, iclass 37, count 0 2006.257.06:41:51.25#ibcon#about to read 4, iclass 37, count 0 2006.257.06:41:51.25#ibcon#read 4, iclass 37, count 0 2006.257.06:41:51.25#ibcon#about to read 5, iclass 37, count 0 2006.257.06:41:51.25#ibcon#read 5, iclass 37, count 0 2006.257.06:41:51.25#ibcon#about to read 6, iclass 37, count 0 2006.257.06:41:51.25#ibcon#read 6, iclass 37, count 0 2006.257.06:41:51.25#ibcon#end of sib2, iclass 37, count 0 2006.257.06:41:51.25#ibcon#*after write, iclass 37, count 0 2006.257.06:41:51.25#ibcon#*before return 0, iclass 37, count 0 2006.257.06:41:51.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:51.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:41:51.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:41:51.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:41:51.25$vck44/vblo=8,744.99 2006.257.06:41:51.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.06:41:51.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.06:41:51.25#ibcon#ireg 17 cls_cnt 0 2006.257.06:41:51.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:51.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:51.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:51.25#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:41:51.25#ibcon#first serial, iclass 39, count 0 2006.257.06:41:51.25#ibcon#enter sib2, iclass 39, count 0 2006.257.06:41:51.25#ibcon#flushed, iclass 39, count 0 2006.257.06:41:51.25#ibcon#about to write, iclass 39, count 0 2006.257.06:41:51.25#ibcon#wrote, iclass 39, count 0 2006.257.06:41:51.25#ibcon#about to read 3, iclass 39, count 0 2006.257.06:41:51.27#ibcon#read 3, iclass 39, count 0 2006.257.06:41:51.27#ibcon#about to read 4, iclass 39, count 0 2006.257.06:41:51.27#ibcon#read 4, iclass 39, count 0 2006.257.06:41:51.27#ibcon#about to read 5, iclass 39, count 0 2006.257.06:41:51.27#ibcon#read 5, iclass 39, count 0 2006.257.06:41:51.27#ibcon#about to read 6, iclass 39, count 0 2006.257.06:41:51.27#ibcon#read 6, iclass 39, count 0 2006.257.06:41:51.27#ibcon#end of sib2, iclass 39, count 0 2006.257.06:41:51.27#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:41:51.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:41:51.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:41:51.27#ibcon#*before write, iclass 39, count 0 2006.257.06:41:51.27#ibcon#enter sib2, iclass 39, count 0 2006.257.06:41:51.27#ibcon#flushed, iclass 39, count 0 2006.257.06:41:51.27#ibcon#about to write, iclass 39, count 0 2006.257.06:41:51.27#ibcon#wrote, iclass 39, count 0 2006.257.06:41:51.27#ibcon#about to read 3, iclass 39, count 0 2006.257.06:41:51.31#ibcon#read 3, iclass 39, count 0 2006.257.06:41:51.31#ibcon#about to read 4, iclass 39, count 0 2006.257.06:41:51.31#ibcon#read 4, iclass 39, count 0 2006.257.06:41:51.31#ibcon#about to read 5, iclass 39, count 0 2006.257.06:41:51.31#ibcon#read 5, iclass 39, count 0 2006.257.06:41:51.31#ibcon#about to read 6, iclass 39, count 0 2006.257.06:41:51.31#ibcon#read 6, iclass 39, count 0 2006.257.06:41:51.31#ibcon#end of sib2, iclass 39, count 0 2006.257.06:41:51.31#ibcon#*after write, iclass 39, count 0 2006.257.06:41:51.31#ibcon#*before return 0, iclass 39, count 0 2006.257.06:41:51.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:51.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:41:51.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:41:51.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:41:51.31$vck44/vb=8,4 2006.257.06:41:51.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.06:41:51.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.06:41:51.31#ibcon#ireg 11 cls_cnt 2 2006.257.06:41:51.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:51.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:51.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:51.37#ibcon#enter wrdev, iclass 3, count 2 2006.257.06:41:51.37#ibcon#first serial, iclass 3, count 2 2006.257.06:41:51.37#ibcon#enter sib2, iclass 3, count 2 2006.257.06:41:51.37#ibcon#flushed, iclass 3, count 2 2006.257.06:41:51.37#ibcon#about to write, iclass 3, count 2 2006.257.06:41:51.37#ibcon#wrote, iclass 3, count 2 2006.257.06:41:51.37#ibcon#about to read 3, iclass 3, count 2 2006.257.06:41:51.39#ibcon#read 3, iclass 3, count 2 2006.257.06:41:51.39#ibcon#about to read 4, iclass 3, count 2 2006.257.06:41:51.39#ibcon#read 4, iclass 3, count 2 2006.257.06:41:51.39#ibcon#about to read 5, iclass 3, count 2 2006.257.06:41:51.39#ibcon#read 5, iclass 3, count 2 2006.257.06:41:51.39#ibcon#about to read 6, iclass 3, count 2 2006.257.06:41:51.39#ibcon#read 6, iclass 3, count 2 2006.257.06:41:51.39#ibcon#end of sib2, iclass 3, count 2 2006.257.06:41:51.39#ibcon#*mode == 0, iclass 3, count 2 2006.257.06:41:51.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.06:41:51.39#ibcon#[27=AT08-04\r\n] 2006.257.06:41:51.39#ibcon#*before write, iclass 3, count 2 2006.257.06:41:51.39#ibcon#enter sib2, iclass 3, count 2 2006.257.06:41:51.39#ibcon#flushed, iclass 3, count 2 2006.257.06:41:51.39#ibcon#about to write, iclass 3, count 2 2006.257.06:41:51.39#ibcon#wrote, iclass 3, count 2 2006.257.06:41:51.39#ibcon#about to read 3, iclass 3, count 2 2006.257.06:41:51.42#ibcon#read 3, iclass 3, count 2 2006.257.06:41:51.42#ibcon#about to read 4, iclass 3, count 2 2006.257.06:41:51.42#ibcon#read 4, iclass 3, count 2 2006.257.06:41:51.42#ibcon#about to read 5, iclass 3, count 2 2006.257.06:41:51.42#ibcon#read 5, iclass 3, count 2 2006.257.06:41:51.42#ibcon#about to read 6, iclass 3, count 2 2006.257.06:41:51.42#ibcon#read 6, iclass 3, count 2 2006.257.06:41:51.42#ibcon#end of sib2, iclass 3, count 2 2006.257.06:41:51.42#ibcon#*after write, iclass 3, count 2 2006.257.06:41:51.42#ibcon#*before return 0, iclass 3, count 2 2006.257.06:41:51.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:51.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:41:51.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.06:41:51.42#ibcon#ireg 7 cls_cnt 0 2006.257.06:41:51.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:51.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:51.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:51.54#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:41:51.54#ibcon#first serial, iclass 3, count 0 2006.257.06:41:51.54#ibcon#enter sib2, iclass 3, count 0 2006.257.06:41:51.54#ibcon#flushed, iclass 3, count 0 2006.257.06:41:51.54#ibcon#about to write, iclass 3, count 0 2006.257.06:41:51.54#ibcon#wrote, iclass 3, count 0 2006.257.06:41:51.54#ibcon#about to read 3, iclass 3, count 0 2006.257.06:41:51.56#ibcon#read 3, iclass 3, count 0 2006.257.06:41:51.56#ibcon#about to read 4, iclass 3, count 0 2006.257.06:41:51.56#ibcon#read 4, iclass 3, count 0 2006.257.06:41:51.56#ibcon#about to read 5, iclass 3, count 0 2006.257.06:41:51.56#ibcon#read 5, iclass 3, count 0 2006.257.06:41:51.56#ibcon#about to read 6, iclass 3, count 0 2006.257.06:41:51.56#ibcon#read 6, iclass 3, count 0 2006.257.06:41:51.56#ibcon#end of sib2, iclass 3, count 0 2006.257.06:41:51.56#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:41:51.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:41:51.56#ibcon#[27=USB\r\n] 2006.257.06:41:51.56#ibcon#*before write, iclass 3, count 0 2006.257.06:41:51.56#ibcon#enter sib2, iclass 3, count 0 2006.257.06:41:51.56#ibcon#flushed, iclass 3, count 0 2006.257.06:41:51.56#ibcon#about to write, iclass 3, count 0 2006.257.06:41:51.56#ibcon#wrote, iclass 3, count 0 2006.257.06:41:51.56#ibcon#about to read 3, iclass 3, count 0 2006.257.06:41:51.59#ibcon#read 3, iclass 3, count 0 2006.257.06:41:51.59#ibcon#about to read 4, iclass 3, count 0 2006.257.06:41:51.59#ibcon#read 4, iclass 3, count 0 2006.257.06:41:51.59#ibcon#about to read 5, iclass 3, count 0 2006.257.06:41:51.59#ibcon#read 5, iclass 3, count 0 2006.257.06:41:51.59#ibcon#about to read 6, iclass 3, count 0 2006.257.06:41:51.59#ibcon#read 6, iclass 3, count 0 2006.257.06:41:51.59#ibcon#end of sib2, iclass 3, count 0 2006.257.06:41:51.59#ibcon#*after write, iclass 3, count 0 2006.257.06:41:51.59#ibcon#*before return 0, iclass 3, count 0 2006.257.06:41:51.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:51.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:41:51.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:41:51.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:41:51.59$vck44/vabw=wide 2006.257.06:41:51.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.06:41:51.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.06:41:51.59#ibcon#ireg 8 cls_cnt 0 2006.257.06:41:51.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:51.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:51.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:51.59#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:41:51.59#ibcon#first serial, iclass 5, count 0 2006.257.06:41:51.59#ibcon#enter sib2, iclass 5, count 0 2006.257.06:41:51.59#ibcon#flushed, iclass 5, count 0 2006.257.06:41:51.59#ibcon#about to write, iclass 5, count 0 2006.257.06:41:51.59#ibcon#wrote, iclass 5, count 0 2006.257.06:41:51.59#ibcon#about to read 3, iclass 5, count 0 2006.257.06:41:51.61#ibcon#read 3, iclass 5, count 0 2006.257.06:41:51.61#ibcon#about to read 4, iclass 5, count 0 2006.257.06:41:51.61#ibcon#read 4, iclass 5, count 0 2006.257.06:41:51.61#ibcon#about to read 5, iclass 5, count 0 2006.257.06:41:51.61#ibcon#read 5, iclass 5, count 0 2006.257.06:41:51.61#ibcon#about to read 6, iclass 5, count 0 2006.257.06:41:51.61#ibcon#read 6, iclass 5, count 0 2006.257.06:41:51.61#ibcon#end of sib2, iclass 5, count 0 2006.257.06:41:51.61#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:41:51.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:41:51.61#ibcon#[25=BW32\r\n] 2006.257.06:41:51.61#ibcon#*before write, iclass 5, count 0 2006.257.06:41:51.61#ibcon#enter sib2, iclass 5, count 0 2006.257.06:41:51.61#ibcon#flushed, iclass 5, count 0 2006.257.06:41:51.61#ibcon#about to write, iclass 5, count 0 2006.257.06:41:51.61#ibcon#wrote, iclass 5, count 0 2006.257.06:41:51.61#ibcon#about to read 3, iclass 5, count 0 2006.257.06:41:51.64#ibcon#read 3, iclass 5, count 0 2006.257.06:41:51.64#ibcon#about to read 4, iclass 5, count 0 2006.257.06:41:51.64#ibcon#read 4, iclass 5, count 0 2006.257.06:41:51.64#ibcon#about to read 5, iclass 5, count 0 2006.257.06:41:51.64#ibcon#read 5, iclass 5, count 0 2006.257.06:41:51.64#ibcon#about to read 6, iclass 5, count 0 2006.257.06:41:51.64#ibcon#read 6, iclass 5, count 0 2006.257.06:41:51.64#ibcon#end of sib2, iclass 5, count 0 2006.257.06:41:51.64#ibcon#*after write, iclass 5, count 0 2006.257.06:41:51.64#ibcon#*before return 0, iclass 5, count 0 2006.257.06:41:51.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:51.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:41:51.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:41:51.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:41:51.64$vck44/vbbw=wide 2006.257.06:41:51.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.06:41:51.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.06:41:51.64#ibcon#ireg 8 cls_cnt 0 2006.257.06:41:51.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:41:51.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:41:51.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:41:51.71#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:41:51.71#ibcon#first serial, iclass 7, count 0 2006.257.06:41:51.71#ibcon#enter sib2, iclass 7, count 0 2006.257.06:41:51.71#ibcon#flushed, iclass 7, count 0 2006.257.06:41:51.71#ibcon#about to write, iclass 7, count 0 2006.257.06:41:51.71#ibcon#wrote, iclass 7, count 0 2006.257.06:41:51.71#ibcon#about to read 3, iclass 7, count 0 2006.257.06:41:51.73#ibcon#read 3, iclass 7, count 0 2006.257.06:41:51.73#ibcon#about to read 4, iclass 7, count 0 2006.257.06:41:51.73#ibcon#read 4, iclass 7, count 0 2006.257.06:41:51.73#ibcon#about to read 5, iclass 7, count 0 2006.257.06:41:51.73#ibcon#read 5, iclass 7, count 0 2006.257.06:41:51.73#ibcon#about to read 6, iclass 7, count 0 2006.257.06:41:51.73#ibcon#read 6, iclass 7, count 0 2006.257.06:41:51.73#ibcon#end of sib2, iclass 7, count 0 2006.257.06:41:51.73#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:41:51.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:41:51.73#ibcon#[27=BW32\r\n] 2006.257.06:41:51.73#ibcon#*before write, iclass 7, count 0 2006.257.06:41:51.73#ibcon#enter sib2, iclass 7, count 0 2006.257.06:41:51.73#ibcon#flushed, iclass 7, count 0 2006.257.06:41:51.73#ibcon#about to write, iclass 7, count 0 2006.257.06:41:51.73#ibcon#wrote, iclass 7, count 0 2006.257.06:41:51.73#ibcon#about to read 3, iclass 7, count 0 2006.257.06:41:51.76#ibcon#read 3, iclass 7, count 0 2006.257.06:41:51.76#ibcon#about to read 4, iclass 7, count 0 2006.257.06:41:51.76#ibcon#read 4, iclass 7, count 0 2006.257.06:41:51.76#ibcon#about to read 5, iclass 7, count 0 2006.257.06:41:51.76#ibcon#read 5, iclass 7, count 0 2006.257.06:41:51.76#ibcon#about to read 6, iclass 7, count 0 2006.257.06:41:51.76#ibcon#read 6, iclass 7, count 0 2006.257.06:41:51.76#ibcon#end of sib2, iclass 7, count 0 2006.257.06:41:51.76#ibcon#*after write, iclass 7, count 0 2006.257.06:41:51.76#ibcon#*before return 0, iclass 7, count 0 2006.257.06:41:51.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:41:51.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:41:51.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:41:51.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:41:51.76$setupk4/ifdk4 2006.257.06:41:51.76$ifdk4/lo= 2006.257.06:41:51.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:41:51.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:41:51.77$ifdk4/patch= 2006.257.06:41:51.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:41:51.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:41:51.77$setupk4/!*+20s 2006.257.06:41:54.50#abcon#<5=/15 0.7 2.1 20.66 881012.3\r\n> 2006.257.06:41:54.52#abcon#{5=INTERFACE CLEAR} 2006.257.06:41:54.58#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:41:59.13#trakl#Source acquired 2006.257.06:42:00.13#flagr#flagr/antenna,acquired 2006.257.06:42:04.67#abcon#<5=/15 0.7 3.3 20.66 881012.3\r\n> 2006.257.06:42:04.69#abcon#{5=INTERFACE CLEAR} 2006.257.06:42:04.75#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:42:06.28$setupk4/"tpicd 2006.257.06:42:06.28$setupk4/echo=off 2006.257.06:42:06.28$setupk4/xlog=off 2006.257.06:42:06.28:!2006.257.06:42:34 2006.257.06:42:34.00:preob 2006.257.06:42:34.13/onsource/TRACKING 2006.257.06:42:34.13:!2006.257.06:42:44 2006.257.06:42:44.00:"tape 2006.257.06:42:44.00:"st=record 2006.257.06:42:44.00:data_valid=on 2006.257.06:42:44.00:midob 2006.257.06:42:45.13/onsource/TRACKING 2006.257.06:42:45.14/wx/20.66,1012.3,89 2006.257.06:42:45.18/cable/+6.4794E-03 2006.257.06:42:46.27/va/01,08,usb,yes,31,33 2006.257.06:42:46.27/va/02,07,usb,yes,33,34 2006.257.06:42:46.27/va/03,08,usb,yes,30,32 2006.257.06:42:46.27/va/04,07,usb,yes,34,36 2006.257.06:42:46.27/va/05,04,usb,yes,31,31 2006.257.06:42:46.27/va/06,04,usb,yes,34,34 2006.257.06:42:46.27/va/07,04,usb,yes,35,36 2006.257.06:42:46.27/va/08,04,usb,yes,29,36 2006.257.06:42:46.50/valo/01,524.99,yes,locked 2006.257.06:42:46.50/valo/02,534.99,yes,locked 2006.257.06:42:46.50/valo/03,564.99,yes,locked 2006.257.06:42:46.50/valo/04,624.99,yes,locked 2006.257.06:42:46.50/valo/05,734.99,yes,locked 2006.257.06:42:46.50/valo/06,814.99,yes,locked 2006.257.06:42:46.50/valo/07,864.99,yes,locked 2006.257.06:42:46.50/valo/08,884.99,yes,locked 2006.257.06:42:47.59/vb/01,04,usb,yes,30,28 2006.257.06:42:47.59/vb/02,05,usb,yes,29,28 2006.257.06:42:47.59/vb/03,04,usb,yes,29,32 2006.257.06:42:47.59/vb/04,05,usb,yes,30,29 2006.257.06:42:47.59/vb/05,04,usb,yes,26,29 2006.257.06:42:47.59/vb/06,04,usb,yes,31,27 2006.257.06:42:47.59/vb/07,04,usb,yes,30,30 2006.257.06:42:47.59/vb/08,04,usb,yes,28,31 2006.257.06:42:47.82/vblo/01,629.99,yes,locked 2006.257.06:42:47.82/vblo/02,634.99,yes,locked 2006.257.06:42:47.82/vblo/03,649.99,yes,locked 2006.257.06:42:47.82/vblo/04,679.99,yes,locked 2006.257.06:42:47.82/vblo/05,709.99,yes,locked 2006.257.06:42:47.82/vblo/06,719.99,yes,locked 2006.257.06:42:47.82/vblo/07,734.99,yes,locked 2006.257.06:42:47.82/vblo/08,744.99,yes,locked 2006.257.06:42:47.97/vabw/8 2006.257.06:42:48.12/vbbw/8 2006.257.06:42:48.21/xfe/off,on,16.7 2006.257.06:42:48.58/ifatt/23,28,28,28 2006.257.06:42:49.07/fmout-gps/S +4.48E-07 2006.257.06:42:49.11:!2006.257.06:43:34 2006.257.06:43:34.01:data_valid=off 2006.257.06:43:34.02:"et 2006.257.06:43:34.02:!+3s 2006.257.06:43:37.04:"tape 2006.257.06:43:37.05:postob 2006.257.06:43:37.15/cable/+6.4781E-03 2006.257.06:43:37.16/wx/20.66,1012.3,89 2006.257.06:43:37.21/fmout-gps/S +4.48E-07 2006.257.06:43:37.22:scan_name=257-0648,jd0609,40 2006.257.06:43:37.22:source=2121+053,212344.52,053522.1,2000.0,cw 2006.257.06:43:38.14#flagr#flagr/antenna,new-source 2006.257.06:43:38.15:checkk5 2006.257.06:43:38.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:43:38.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:43:39.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:43:39.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:43:40.13/chk_obsdata//k5ts1/T2570642??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.06:43:40.51/chk_obsdata//k5ts2/T2570642??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.06:43:40.93/chk_obsdata//k5ts3/T2570642??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.06:43:41.34/chk_obsdata//k5ts4/T2570642??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.06:43:42.08/k5log//k5ts1_log_newline 2006.257.06:43:42.79/k5log//k5ts2_log_newline 2006.257.06:43:43.53/k5log//k5ts3_log_newline 2006.257.06:43:44.24/k5log//k5ts4_log_newline 2006.257.06:43:44.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:43:44.26:setupk4=1 2006.257.06:43:44.26$setupk4/echo=on 2006.257.06:43:44.26$setupk4/pcalon 2006.257.06:43:44.26$pcalon/"no phase cal control is implemented here 2006.257.06:43:44.26$setupk4/"tpicd=stop 2006.257.06:43:44.26$setupk4/"rec=synch_on 2006.257.06:43:44.26$setupk4/"rec_mode=128 2006.257.06:43:44.26$setupk4/!* 2006.257.06:43:44.26$setupk4/recpk4 2006.257.06:43:44.26$recpk4/recpatch= 2006.257.06:43:44.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:43:44.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:43:44.27$setupk4/vck44 2006.257.06:43:44.27$vck44/valo=1,524.99 2006.257.06:43:44.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.06:43:44.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.06:43:44.27#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:44.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:44.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:44.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:44.27#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:43:44.27#ibcon#first serial, iclass 22, count 0 2006.257.06:43:44.27#ibcon#enter sib2, iclass 22, count 0 2006.257.06:43:44.27#ibcon#flushed, iclass 22, count 0 2006.257.06:43:44.27#ibcon#about to write, iclass 22, count 0 2006.257.06:43:44.27#ibcon#wrote, iclass 22, count 0 2006.257.06:43:44.27#ibcon#about to read 3, iclass 22, count 0 2006.257.06:43:44.28#ibcon#read 3, iclass 22, count 0 2006.257.06:43:44.28#ibcon#about to read 4, iclass 22, count 0 2006.257.06:43:44.28#ibcon#read 4, iclass 22, count 0 2006.257.06:43:44.28#ibcon#about to read 5, iclass 22, count 0 2006.257.06:43:44.28#ibcon#read 5, iclass 22, count 0 2006.257.06:43:44.28#ibcon#about to read 6, iclass 22, count 0 2006.257.06:43:44.28#ibcon#read 6, iclass 22, count 0 2006.257.06:43:44.28#ibcon#end of sib2, iclass 22, count 0 2006.257.06:43:44.28#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:43:44.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:43:44.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:43:44.28#ibcon#*before write, iclass 22, count 0 2006.257.06:43:44.28#ibcon#enter sib2, iclass 22, count 0 2006.257.06:43:44.28#ibcon#flushed, iclass 22, count 0 2006.257.06:43:44.28#ibcon#about to write, iclass 22, count 0 2006.257.06:43:44.28#ibcon#wrote, iclass 22, count 0 2006.257.06:43:44.28#ibcon#about to read 3, iclass 22, count 0 2006.257.06:43:44.33#ibcon#read 3, iclass 22, count 0 2006.257.06:43:44.33#ibcon#about to read 4, iclass 22, count 0 2006.257.06:43:44.33#ibcon#read 4, iclass 22, count 0 2006.257.06:43:44.33#ibcon#about to read 5, iclass 22, count 0 2006.257.06:43:44.33#ibcon#read 5, iclass 22, count 0 2006.257.06:43:44.33#ibcon#about to read 6, iclass 22, count 0 2006.257.06:43:44.33#ibcon#read 6, iclass 22, count 0 2006.257.06:43:44.33#ibcon#end of sib2, iclass 22, count 0 2006.257.06:43:44.33#ibcon#*after write, iclass 22, count 0 2006.257.06:43:44.33#ibcon#*before return 0, iclass 22, count 0 2006.257.06:43:44.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:44.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:44.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:43:44.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:43:44.33$vck44/va=1,8 2006.257.06:43:44.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.06:43:44.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.06:43:44.33#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:44.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:44.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:44.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:44.33#ibcon#enter wrdev, iclass 24, count 2 2006.257.06:43:44.33#ibcon#first serial, iclass 24, count 2 2006.257.06:43:44.33#ibcon#enter sib2, iclass 24, count 2 2006.257.06:43:44.33#ibcon#flushed, iclass 24, count 2 2006.257.06:43:44.33#ibcon#about to write, iclass 24, count 2 2006.257.06:43:44.33#ibcon#wrote, iclass 24, count 2 2006.257.06:43:44.33#ibcon#about to read 3, iclass 24, count 2 2006.257.06:43:44.35#ibcon#read 3, iclass 24, count 2 2006.257.06:43:44.35#ibcon#about to read 4, iclass 24, count 2 2006.257.06:43:44.35#ibcon#read 4, iclass 24, count 2 2006.257.06:43:44.35#ibcon#about to read 5, iclass 24, count 2 2006.257.06:43:44.35#ibcon#read 5, iclass 24, count 2 2006.257.06:43:44.35#ibcon#about to read 6, iclass 24, count 2 2006.257.06:43:44.35#ibcon#read 6, iclass 24, count 2 2006.257.06:43:44.35#ibcon#end of sib2, iclass 24, count 2 2006.257.06:43:44.35#ibcon#*mode == 0, iclass 24, count 2 2006.257.06:43:44.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.06:43:44.35#ibcon#[25=AT01-08\r\n] 2006.257.06:43:44.35#ibcon#*before write, iclass 24, count 2 2006.257.06:43:44.35#ibcon#enter sib2, iclass 24, count 2 2006.257.06:43:44.35#ibcon#flushed, iclass 24, count 2 2006.257.06:43:44.35#ibcon#about to write, iclass 24, count 2 2006.257.06:43:44.35#ibcon#wrote, iclass 24, count 2 2006.257.06:43:44.35#ibcon#about to read 3, iclass 24, count 2 2006.257.06:43:44.38#ibcon#read 3, iclass 24, count 2 2006.257.06:43:44.38#ibcon#about to read 4, iclass 24, count 2 2006.257.06:43:44.38#ibcon#read 4, iclass 24, count 2 2006.257.06:43:44.38#ibcon#about to read 5, iclass 24, count 2 2006.257.06:43:44.38#ibcon#read 5, iclass 24, count 2 2006.257.06:43:44.38#ibcon#about to read 6, iclass 24, count 2 2006.257.06:43:44.38#ibcon#read 6, iclass 24, count 2 2006.257.06:43:44.38#ibcon#end of sib2, iclass 24, count 2 2006.257.06:43:44.38#ibcon#*after write, iclass 24, count 2 2006.257.06:43:44.38#ibcon#*before return 0, iclass 24, count 2 2006.257.06:43:44.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:44.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:44.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.06:43:44.38#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:44.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:44.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:44.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:44.50#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:43:44.50#ibcon#first serial, iclass 24, count 0 2006.257.06:43:44.50#ibcon#enter sib2, iclass 24, count 0 2006.257.06:43:44.50#ibcon#flushed, iclass 24, count 0 2006.257.06:43:44.50#ibcon#about to write, iclass 24, count 0 2006.257.06:43:44.50#ibcon#wrote, iclass 24, count 0 2006.257.06:43:44.50#ibcon#about to read 3, iclass 24, count 0 2006.257.06:43:44.52#ibcon#read 3, iclass 24, count 0 2006.257.06:43:44.52#ibcon#about to read 4, iclass 24, count 0 2006.257.06:43:44.52#ibcon#read 4, iclass 24, count 0 2006.257.06:43:44.52#ibcon#about to read 5, iclass 24, count 0 2006.257.06:43:44.52#ibcon#read 5, iclass 24, count 0 2006.257.06:43:44.52#ibcon#about to read 6, iclass 24, count 0 2006.257.06:43:44.52#ibcon#read 6, iclass 24, count 0 2006.257.06:43:44.52#ibcon#end of sib2, iclass 24, count 0 2006.257.06:43:44.52#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:43:44.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:43:44.52#ibcon#[25=USB\r\n] 2006.257.06:43:44.52#ibcon#*before write, iclass 24, count 0 2006.257.06:43:44.52#ibcon#enter sib2, iclass 24, count 0 2006.257.06:43:44.52#ibcon#flushed, iclass 24, count 0 2006.257.06:43:44.52#ibcon#about to write, iclass 24, count 0 2006.257.06:43:44.52#ibcon#wrote, iclass 24, count 0 2006.257.06:43:44.52#ibcon#about to read 3, iclass 24, count 0 2006.257.06:43:44.55#ibcon#read 3, iclass 24, count 0 2006.257.06:43:44.55#ibcon#about to read 4, iclass 24, count 0 2006.257.06:43:44.55#ibcon#read 4, iclass 24, count 0 2006.257.06:43:44.55#ibcon#about to read 5, iclass 24, count 0 2006.257.06:43:44.55#ibcon#read 5, iclass 24, count 0 2006.257.06:43:44.55#ibcon#about to read 6, iclass 24, count 0 2006.257.06:43:44.55#ibcon#read 6, iclass 24, count 0 2006.257.06:43:44.55#ibcon#end of sib2, iclass 24, count 0 2006.257.06:43:44.55#ibcon#*after write, iclass 24, count 0 2006.257.06:43:44.55#ibcon#*before return 0, iclass 24, count 0 2006.257.06:43:44.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:44.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:44.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:43:44.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:43:44.55$vck44/valo=2,534.99 2006.257.06:43:44.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.06:43:44.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.06:43:44.55#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:44.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:44.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:44.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:44.55#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:43:44.55#ibcon#first serial, iclass 26, count 0 2006.257.06:43:44.55#ibcon#enter sib2, iclass 26, count 0 2006.257.06:43:44.55#ibcon#flushed, iclass 26, count 0 2006.257.06:43:44.55#ibcon#about to write, iclass 26, count 0 2006.257.06:43:44.55#ibcon#wrote, iclass 26, count 0 2006.257.06:43:44.55#ibcon#about to read 3, iclass 26, count 0 2006.257.06:43:44.57#ibcon#read 3, iclass 26, count 0 2006.257.06:43:44.57#ibcon#about to read 4, iclass 26, count 0 2006.257.06:43:44.57#ibcon#read 4, iclass 26, count 0 2006.257.06:43:44.57#ibcon#about to read 5, iclass 26, count 0 2006.257.06:43:44.57#ibcon#read 5, iclass 26, count 0 2006.257.06:43:44.57#ibcon#about to read 6, iclass 26, count 0 2006.257.06:43:44.57#ibcon#read 6, iclass 26, count 0 2006.257.06:43:44.57#ibcon#end of sib2, iclass 26, count 0 2006.257.06:43:44.57#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:43:44.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:43:44.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:43:44.57#ibcon#*before write, iclass 26, count 0 2006.257.06:43:44.57#ibcon#enter sib2, iclass 26, count 0 2006.257.06:43:44.57#ibcon#flushed, iclass 26, count 0 2006.257.06:43:44.57#ibcon#about to write, iclass 26, count 0 2006.257.06:43:44.57#ibcon#wrote, iclass 26, count 0 2006.257.06:43:44.57#ibcon#about to read 3, iclass 26, count 0 2006.257.06:43:44.61#ibcon#read 3, iclass 26, count 0 2006.257.06:43:44.61#ibcon#about to read 4, iclass 26, count 0 2006.257.06:43:44.61#ibcon#read 4, iclass 26, count 0 2006.257.06:43:44.61#ibcon#about to read 5, iclass 26, count 0 2006.257.06:43:44.61#ibcon#read 5, iclass 26, count 0 2006.257.06:43:44.61#ibcon#about to read 6, iclass 26, count 0 2006.257.06:43:44.61#ibcon#read 6, iclass 26, count 0 2006.257.06:43:44.61#ibcon#end of sib2, iclass 26, count 0 2006.257.06:43:44.61#ibcon#*after write, iclass 26, count 0 2006.257.06:43:44.61#ibcon#*before return 0, iclass 26, count 0 2006.257.06:43:44.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:44.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:44.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:43:44.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:43:44.61$vck44/va=2,7 2006.257.06:43:44.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.06:43:44.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.06:43:44.61#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:44.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:44.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:44.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:44.67#ibcon#enter wrdev, iclass 28, count 2 2006.257.06:43:44.67#ibcon#first serial, iclass 28, count 2 2006.257.06:43:44.67#ibcon#enter sib2, iclass 28, count 2 2006.257.06:43:44.67#ibcon#flushed, iclass 28, count 2 2006.257.06:43:44.67#ibcon#about to write, iclass 28, count 2 2006.257.06:43:44.67#ibcon#wrote, iclass 28, count 2 2006.257.06:43:44.67#ibcon#about to read 3, iclass 28, count 2 2006.257.06:43:44.69#ibcon#read 3, iclass 28, count 2 2006.257.06:43:44.69#ibcon#about to read 4, iclass 28, count 2 2006.257.06:43:44.69#ibcon#read 4, iclass 28, count 2 2006.257.06:43:44.69#ibcon#about to read 5, iclass 28, count 2 2006.257.06:43:44.69#ibcon#read 5, iclass 28, count 2 2006.257.06:43:44.69#ibcon#about to read 6, iclass 28, count 2 2006.257.06:43:44.69#ibcon#read 6, iclass 28, count 2 2006.257.06:43:44.69#ibcon#end of sib2, iclass 28, count 2 2006.257.06:43:44.69#ibcon#*mode == 0, iclass 28, count 2 2006.257.06:43:44.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.06:43:44.69#ibcon#[25=AT02-07\r\n] 2006.257.06:43:44.69#ibcon#*before write, iclass 28, count 2 2006.257.06:43:44.69#ibcon#enter sib2, iclass 28, count 2 2006.257.06:43:44.69#ibcon#flushed, iclass 28, count 2 2006.257.06:43:44.69#ibcon#about to write, iclass 28, count 2 2006.257.06:43:44.69#ibcon#wrote, iclass 28, count 2 2006.257.06:43:44.69#ibcon#about to read 3, iclass 28, count 2 2006.257.06:43:44.72#ibcon#read 3, iclass 28, count 2 2006.257.06:43:44.72#ibcon#about to read 4, iclass 28, count 2 2006.257.06:43:44.72#ibcon#read 4, iclass 28, count 2 2006.257.06:43:44.72#ibcon#about to read 5, iclass 28, count 2 2006.257.06:43:44.72#ibcon#read 5, iclass 28, count 2 2006.257.06:43:44.72#ibcon#about to read 6, iclass 28, count 2 2006.257.06:43:44.72#ibcon#read 6, iclass 28, count 2 2006.257.06:43:44.72#ibcon#end of sib2, iclass 28, count 2 2006.257.06:43:44.72#ibcon#*after write, iclass 28, count 2 2006.257.06:43:44.72#ibcon#*before return 0, iclass 28, count 2 2006.257.06:43:44.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:44.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:44.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.06:43:44.72#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:44.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:44.84#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:44.84#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:44.84#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:43:44.84#ibcon#first serial, iclass 28, count 0 2006.257.06:43:44.84#ibcon#enter sib2, iclass 28, count 0 2006.257.06:43:44.84#ibcon#flushed, iclass 28, count 0 2006.257.06:43:44.84#ibcon#about to write, iclass 28, count 0 2006.257.06:43:44.84#ibcon#wrote, iclass 28, count 0 2006.257.06:43:44.84#ibcon#about to read 3, iclass 28, count 0 2006.257.06:43:44.86#ibcon#read 3, iclass 28, count 0 2006.257.06:43:44.86#ibcon#about to read 4, iclass 28, count 0 2006.257.06:43:44.86#ibcon#read 4, iclass 28, count 0 2006.257.06:43:44.86#ibcon#about to read 5, iclass 28, count 0 2006.257.06:43:44.86#ibcon#read 5, iclass 28, count 0 2006.257.06:43:44.86#ibcon#about to read 6, iclass 28, count 0 2006.257.06:43:44.86#ibcon#read 6, iclass 28, count 0 2006.257.06:43:44.86#ibcon#end of sib2, iclass 28, count 0 2006.257.06:43:44.86#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:43:44.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:43:44.86#ibcon#[25=USB\r\n] 2006.257.06:43:44.86#ibcon#*before write, iclass 28, count 0 2006.257.06:43:44.86#ibcon#enter sib2, iclass 28, count 0 2006.257.06:43:44.86#ibcon#flushed, iclass 28, count 0 2006.257.06:43:44.86#ibcon#about to write, iclass 28, count 0 2006.257.06:43:44.86#ibcon#wrote, iclass 28, count 0 2006.257.06:43:44.86#ibcon#about to read 3, iclass 28, count 0 2006.257.06:43:44.89#ibcon#read 3, iclass 28, count 0 2006.257.06:43:44.89#ibcon#about to read 4, iclass 28, count 0 2006.257.06:43:44.89#ibcon#read 4, iclass 28, count 0 2006.257.06:43:44.89#ibcon#about to read 5, iclass 28, count 0 2006.257.06:43:44.89#ibcon#read 5, iclass 28, count 0 2006.257.06:43:44.89#ibcon#about to read 6, iclass 28, count 0 2006.257.06:43:44.89#ibcon#read 6, iclass 28, count 0 2006.257.06:43:44.89#ibcon#end of sib2, iclass 28, count 0 2006.257.06:43:44.89#ibcon#*after write, iclass 28, count 0 2006.257.06:43:44.89#ibcon#*before return 0, iclass 28, count 0 2006.257.06:43:44.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:44.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:44.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:43:44.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:43:44.89$vck44/valo=3,564.99 2006.257.06:43:44.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.06:43:44.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.06:43:44.89#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:44.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:44.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:44.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:44.89#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:43:44.89#ibcon#first serial, iclass 30, count 0 2006.257.06:43:44.89#ibcon#enter sib2, iclass 30, count 0 2006.257.06:43:44.89#ibcon#flushed, iclass 30, count 0 2006.257.06:43:44.89#ibcon#about to write, iclass 30, count 0 2006.257.06:43:44.89#ibcon#wrote, iclass 30, count 0 2006.257.06:43:44.89#ibcon#about to read 3, iclass 30, count 0 2006.257.06:43:44.91#ibcon#read 3, iclass 30, count 0 2006.257.06:43:44.91#ibcon#about to read 4, iclass 30, count 0 2006.257.06:43:44.91#ibcon#read 4, iclass 30, count 0 2006.257.06:43:44.91#ibcon#about to read 5, iclass 30, count 0 2006.257.06:43:44.91#ibcon#read 5, iclass 30, count 0 2006.257.06:43:44.91#ibcon#about to read 6, iclass 30, count 0 2006.257.06:43:44.91#ibcon#read 6, iclass 30, count 0 2006.257.06:43:44.91#ibcon#end of sib2, iclass 30, count 0 2006.257.06:43:44.91#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:43:44.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:43:44.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:43:44.91#ibcon#*before write, iclass 30, count 0 2006.257.06:43:44.91#ibcon#enter sib2, iclass 30, count 0 2006.257.06:43:44.91#ibcon#flushed, iclass 30, count 0 2006.257.06:43:44.91#ibcon#about to write, iclass 30, count 0 2006.257.06:43:44.91#ibcon#wrote, iclass 30, count 0 2006.257.06:43:44.91#ibcon#about to read 3, iclass 30, count 0 2006.257.06:43:44.95#ibcon#read 3, iclass 30, count 0 2006.257.06:43:44.95#ibcon#about to read 4, iclass 30, count 0 2006.257.06:43:44.95#ibcon#read 4, iclass 30, count 0 2006.257.06:43:44.95#ibcon#about to read 5, iclass 30, count 0 2006.257.06:43:44.95#ibcon#read 5, iclass 30, count 0 2006.257.06:43:44.95#ibcon#about to read 6, iclass 30, count 0 2006.257.06:43:44.95#ibcon#read 6, iclass 30, count 0 2006.257.06:43:44.95#ibcon#end of sib2, iclass 30, count 0 2006.257.06:43:44.95#ibcon#*after write, iclass 30, count 0 2006.257.06:43:44.95#ibcon#*before return 0, iclass 30, count 0 2006.257.06:43:44.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:44.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:44.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:43:44.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:43:44.95$vck44/va=3,8 2006.257.06:43:44.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.06:43:44.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.06:43:44.95#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:44.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:45.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:45.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:45.01#ibcon#enter wrdev, iclass 32, count 2 2006.257.06:43:45.01#ibcon#first serial, iclass 32, count 2 2006.257.06:43:45.01#ibcon#enter sib2, iclass 32, count 2 2006.257.06:43:45.01#ibcon#flushed, iclass 32, count 2 2006.257.06:43:45.01#ibcon#about to write, iclass 32, count 2 2006.257.06:43:45.01#ibcon#wrote, iclass 32, count 2 2006.257.06:43:45.01#ibcon#about to read 3, iclass 32, count 2 2006.257.06:43:45.03#ibcon#read 3, iclass 32, count 2 2006.257.06:43:45.03#ibcon#about to read 4, iclass 32, count 2 2006.257.06:43:45.03#ibcon#read 4, iclass 32, count 2 2006.257.06:43:45.03#ibcon#about to read 5, iclass 32, count 2 2006.257.06:43:45.03#ibcon#read 5, iclass 32, count 2 2006.257.06:43:45.03#ibcon#about to read 6, iclass 32, count 2 2006.257.06:43:45.03#ibcon#read 6, iclass 32, count 2 2006.257.06:43:45.03#ibcon#end of sib2, iclass 32, count 2 2006.257.06:43:45.03#ibcon#*mode == 0, iclass 32, count 2 2006.257.06:43:45.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.06:43:45.03#ibcon#[25=AT03-08\r\n] 2006.257.06:43:45.03#ibcon#*before write, iclass 32, count 2 2006.257.06:43:45.03#ibcon#enter sib2, iclass 32, count 2 2006.257.06:43:45.03#ibcon#flushed, iclass 32, count 2 2006.257.06:43:45.03#ibcon#about to write, iclass 32, count 2 2006.257.06:43:45.03#ibcon#wrote, iclass 32, count 2 2006.257.06:43:45.03#ibcon#about to read 3, iclass 32, count 2 2006.257.06:43:45.06#ibcon#read 3, iclass 32, count 2 2006.257.06:43:45.06#ibcon#about to read 4, iclass 32, count 2 2006.257.06:43:45.06#ibcon#read 4, iclass 32, count 2 2006.257.06:43:45.06#ibcon#about to read 5, iclass 32, count 2 2006.257.06:43:45.06#ibcon#read 5, iclass 32, count 2 2006.257.06:43:45.06#ibcon#about to read 6, iclass 32, count 2 2006.257.06:43:45.06#ibcon#read 6, iclass 32, count 2 2006.257.06:43:45.06#ibcon#end of sib2, iclass 32, count 2 2006.257.06:43:45.06#ibcon#*after write, iclass 32, count 2 2006.257.06:43:45.06#ibcon#*before return 0, iclass 32, count 2 2006.257.06:43:45.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:45.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:45.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.06:43:45.06#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:45.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:45.18#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:45.18#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:45.18#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:43:45.18#ibcon#first serial, iclass 32, count 0 2006.257.06:43:45.18#ibcon#enter sib2, iclass 32, count 0 2006.257.06:43:45.18#ibcon#flushed, iclass 32, count 0 2006.257.06:43:45.18#ibcon#about to write, iclass 32, count 0 2006.257.06:43:45.18#ibcon#wrote, iclass 32, count 0 2006.257.06:43:45.18#ibcon#about to read 3, iclass 32, count 0 2006.257.06:43:45.20#ibcon#read 3, iclass 32, count 0 2006.257.06:43:45.20#ibcon#about to read 4, iclass 32, count 0 2006.257.06:43:45.20#ibcon#read 4, iclass 32, count 0 2006.257.06:43:45.20#ibcon#about to read 5, iclass 32, count 0 2006.257.06:43:45.20#ibcon#read 5, iclass 32, count 0 2006.257.06:43:45.20#ibcon#about to read 6, iclass 32, count 0 2006.257.06:43:45.20#ibcon#read 6, iclass 32, count 0 2006.257.06:43:45.20#ibcon#end of sib2, iclass 32, count 0 2006.257.06:43:45.20#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:43:45.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:43:45.20#ibcon#[25=USB\r\n] 2006.257.06:43:45.20#ibcon#*before write, iclass 32, count 0 2006.257.06:43:45.20#ibcon#enter sib2, iclass 32, count 0 2006.257.06:43:45.20#ibcon#flushed, iclass 32, count 0 2006.257.06:43:45.20#ibcon#about to write, iclass 32, count 0 2006.257.06:43:45.20#ibcon#wrote, iclass 32, count 0 2006.257.06:43:45.20#ibcon#about to read 3, iclass 32, count 0 2006.257.06:43:45.23#ibcon#read 3, iclass 32, count 0 2006.257.06:43:45.23#ibcon#about to read 4, iclass 32, count 0 2006.257.06:43:45.23#ibcon#read 4, iclass 32, count 0 2006.257.06:43:45.23#ibcon#about to read 5, iclass 32, count 0 2006.257.06:43:45.23#ibcon#read 5, iclass 32, count 0 2006.257.06:43:45.23#ibcon#about to read 6, iclass 32, count 0 2006.257.06:43:45.23#ibcon#read 6, iclass 32, count 0 2006.257.06:43:45.23#ibcon#end of sib2, iclass 32, count 0 2006.257.06:43:45.23#ibcon#*after write, iclass 32, count 0 2006.257.06:43:45.23#ibcon#*before return 0, iclass 32, count 0 2006.257.06:43:45.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:45.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:45.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:43:45.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:43:45.23$vck44/valo=4,624.99 2006.257.06:43:45.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.06:43:45.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.06:43:45.23#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:45.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:45.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:45.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:45.23#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:43:45.23#ibcon#first serial, iclass 34, count 0 2006.257.06:43:45.23#ibcon#enter sib2, iclass 34, count 0 2006.257.06:43:45.23#ibcon#flushed, iclass 34, count 0 2006.257.06:43:45.23#ibcon#about to write, iclass 34, count 0 2006.257.06:43:45.23#ibcon#wrote, iclass 34, count 0 2006.257.06:43:45.23#ibcon#about to read 3, iclass 34, count 0 2006.257.06:43:45.25#ibcon#read 3, iclass 34, count 0 2006.257.06:43:45.25#ibcon#about to read 4, iclass 34, count 0 2006.257.06:43:45.25#ibcon#read 4, iclass 34, count 0 2006.257.06:43:45.25#ibcon#about to read 5, iclass 34, count 0 2006.257.06:43:45.25#ibcon#read 5, iclass 34, count 0 2006.257.06:43:45.25#ibcon#about to read 6, iclass 34, count 0 2006.257.06:43:45.25#ibcon#read 6, iclass 34, count 0 2006.257.06:43:45.25#ibcon#end of sib2, iclass 34, count 0 2006.257.06:43:45.25#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:43:45.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:43:45.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:43:45.25#ibcon#*before write, iclass 34, count 0 2006.257.06:43:45.25#ibcon#enter sib2, iclass 34, count 0 2006.257.06:43:45.25#ibcon#flushed, iclass 34, count 0 2006.257.06:43:45.25#ibcon#about to write, iclass 34, count 0 2006.257.06:43:45.25#ibcon#wrote, iclass 34, count 0 2006.257.06:43:45.25#ibcon#about to read 3, iclass 34, count 0 2006.257.06:43:45.29#ibcon#read 3, iclass 34, count 0 2006.257.06:43:45.29#ibcon#about to read 4, iclass 34, count 0 2006.257.06:43:45.29#ibcon#read 4, iclass 34, count 0 2006.257.06:43:45.29#ibcon#about to read 5, iclass 34, count 0 2006.257.06:43:45.29#ibcon#read 5, iclass 34, count 0 2006.257.06:43:45.29#ibcon#about to read 6, iclass 34, count 0 2006.257.06:43:45.29#ibcon#read 6, iclass 34, count 0 2006.257.06:43:45.29#ibcon#end of sib2, iclass 34, count 0 2006.257.06:43:45.29#ibcon#*after write, iclass 34, count 0 2006.257.06:43:45.29#ibcon#*before return 0, iclass 34, count 0 2006.257.06:43:45.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:45.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:45.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:43:45.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:43:45.29$vck44/va=4,7 2006.257.06:43:45.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.06:43:45.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.06:43:45.29#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:45.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:45.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:45.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:45.35#ibcon#enter wrdev, iclass 36, count 2 2006.257.06:43:45.35#ibcon#first serial, iclass 36, count 2 2006.257.06:43:45.35#ibcon#enter sib2, iclass 36, count 2 2006.257.06:43:45.35#ibcon#flushed, iclass 36, count 2 2006.257.06:43:45.35#ibcon#about to write, iclass 36, count 2 2006.257.06:43:45.35#ibcon#wrote, iclass 36, count 2 2006.257.06:43:45.35#ibcon#about to read 3, iclass 36, count 2 2006.257.06:43:45.37#ibcon#read 3, iclass 36, count 2 2006.257.06:43:45.37#ibcon#about to read 4, iclass 36, count 2 2006.257.06:43:45.37#ibcon#read 4, iclass 36, count 2 2006.257.06:43:45.37#ibcon#about to read 5, iclass 36, count 2 2006.257.06:43:45.37#ibcon#read 5, iclass 36, count 2 2006.257.06:43:45.37#ibcon#about to read 6, iclass 36, count 2 2006.257.06:43:45.37#ibcon#read 6, iclass 36, count 2 2006.257.06:43:45.37#ibcon#end of sib2, iclass 36, count 2 2006.257.06:43:45.37#ibcon#*mode == 0, iclass 36, count 2 2006.257.06:43:45.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.06:43:45.37#ibcon#[25=AT04-07\r\n] 2006.257.06:43:45.37#ibcon#*before write, iclass 36, count 2 2006.257.06:43:45.37#ibcon#enter sib2, iclass 36, count 2 2006.257.06:43:45.37#ibcon#flushed, iclass 36, count 2 2006.257.06:43:45.37#ibcon#about to write, iclass 36, count 2 2006.257.06:43:45.37#ibcon#wrote, iclass 36, count 2 2006.257.06:43:45.37#ibcon#about to read 3, iclass 36, count 2 2006.257.06:43:45.40#ibcon#read 3, iclass 36, count 2 2006.257.06:43:45.40#ibcon#about to read 4, iclass 36, count 2 2006.257.06:43:45.40#ibcon#read 4, iclass 36, count 2 2006.257.06:43:45.40#ibcon#about to read 5, iclass 36, count 2 2006.257.06:43:45.40#ibcon#read 5, iclass 36, count 2 2006.257.06:43:45.40#ibcon#about to read 6, iclass 36, count 2 2006.257.06:43:45.40#ibcon#read 6, iclass 36, count 2 2006.257.06:43:45.40#ibcon#end of sib2, iclass 36, count 2 2006.257.06:43:45.40#ibcon#*after write, iclass 36, count 2 2006.257.06:43:45.40#ibcon#*before return 0, iclass 36, count 2 2006.257.06:43:45.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:45.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:45.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.06:43:45.40#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:45.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:45.52#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:45.52#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:45.52#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:43:45.52#ibcon#first serial, iclass 36, count 0 2006.257.06:43:45.52#ibcon#enter sib2, iclass 36, count 0 2006.257.06:43:45.52#ibcon#flushed, iclass 36, count 0 2006.257.06:43:45.52#ibcon#about to write, iclass 36, count 0 2006.257.06:43:45.52#ibcon#wrote, iclass 36, count 0 2006.257.06:43:45.52#ibcon#about to read 3, iclass 36, count 0 2006.257.06:43:45.54#ibcon#read 3, iclass 36, count 0 2006.257.06:43:45.54#ibcon#about to read 4, iclass 36, count 0 2006.257.06:43:45.54#ibcon#read 4, iclass 36, count 0 2006.257.06:43:45.54#ibcon#about to read 5, iclass 36, count 0 2006.257.06:43:45.54#ibcon#read 5, iclass 36, count 0 2006.257.06:43:45.54#ibcon#about to read 6, iclass 36, count 0 2006.257.06:43:45.54#ibcon#read 6, iclass 36, count 0 2006.257.06:43:45.54#ibcon#end of sib2, iclass 36, count 0 2006.257.06:43:45.54#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:43:45.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:43:45.54#ibcon#[25=USB\r\n] 2006.257.06:43:45.54#ibcon#*before write, iclass 36, count 0 2006.257.06:43:45.54#ibcon#enter sib2, iclass 36, count 0 2006.257.06:43:45.54#ibcon#flushed, iclass 36, count 0 2006.257.06:43:45.54#ibcon#about to write, iclass 36, count 0 2006.257.06:43:45.54#ibcon#wrote, iclass 36, count 0 2006.257.06:43:45.54#ibcon#about to read 3, iclass 36, count 0 2006.257.06:43:45.57#ibcon#read 3, iclass 36, count 0 2006.257.06:43:45.57#ibcon#about to read 4, iclass 36, count 0 2006.257.06:43:45.57#ibcon#read 4, iclass 36, count 0 2006.257.06:43:45.57#ibcon#about to read 5, iclass 36, count 0 2006.257.06:43:45.57#ibcon#read 5, iclass 36, count 0 2006.257.06:43:45.57#ibcon#about to read 6, iclass 36, count 0 2006.257.06:43:45.57#ibcon#read 6, iclass 36, count 0 2006.257.06:43:45.57#ibcon#end of sib2, iclass 36, count 0 2006.257.06:43:45.57#ibcon#*after write, iclass 36, count 0 2006.257.06:43:45.57#ibcon#*before return 0, iclass 36, count 0 2006.257.06:43:45.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:45.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:45.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:43:45.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:43:45.57$vck44/valo=5,734.99 2006.257.06:43:45.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.06:43:45.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.06:43:45.57#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:45.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:45.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:45.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:45.57#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:43:45.57#ibcon#first serial, iclass 38, count 0 2006.257.06:43:45.57#ibcon#enter sib2, iclass 38, count 0 2006.257.06:43:45.57#ibcon#flushed, iclass 38, count 0 2006.257.06:43:45.57#ibcon#about to write, iclass 38, count 0 2006.257.06:43:45.57#ibcon#wrote, iclass 38, count 0 2006.257.06:43:45.57#ibcon#about to read 3, iclass 38, count 0 2006.257.06:43:45.59#ibcon#read 3, iclass 38, count 0 2006.257.06:43:45.59#ibcon#about to read 4, iclass 38, count 0 2006.257.06:43:45.59#ibcon#read 4, iclass 38, count 0 2006.257.06:43:45.59#ibcon#about to read 5, iclass 38, count 0 2006.257.06:43:45.59#ibcon#read 5, iclass 38, count 0 2006.257.06:43:45.59#ibcon#about to read 6, iclass 38, count 0 2006.257.06:43:45.59#ibcon#read 6, iclass 38, count 0 2006.257.06:43:45.59#ibcon#end of sib2, iclass 38, count 0 2006.257.06:43:45.59#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:43:45.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:43:45.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:43:45.59#ibcon#*before write, iclass 38, count 0 2006.257.06:43:45.59#ibcon#enter sib2, iclass 38, count 0 2006.257.06:43:45.59#ibcon#flushed, iclass 38, count 0 2006.257.06:43:45.59#ibcon#about to write, iclass 38, count 0 2006.257.06:43:45.59#ibcon#wrote, iclass 38, count 0 2006.257.06:43:45.59#ibcon#about to read 3, iclass 38, count 0 2006.257.06:43:45.63#ibcon#read 3, iclass 38, count 0 2006.257.06:43:45.63#ibcon#about to read 4, iclass 38, count 0 2006.257.06:43:45.63#ibcon#read 4, iclass 38, count 0 2006.257.06:43:45.63#ibcon#about to read 5, iclass 38, count 0 2006.257.06:43:45.63#ibcon#read 5, iclass 38, count 0 2006.257.06:43:45.63#ibcon#about to read 6, iclass 38, count 0 2006.257.06:43:45.63#ibcon#read 6, iclass 38, count 0 2006.257.06:43:45.63#ibcon#end of sib2, iclass 38, count 0 2006.257.06:43:45.63#ibcon#*after write, iclass 38, count 0 2006.257.06:43:45.63#ibcon#*before return 0, iclass 38, count 0 2006.257.06:43:45.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:45.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:45.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:43:45.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:43:45.63$vck44/va=5,4 2006.257.06:43:45.63#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.06:43:45.63#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.06:43:45.63#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:45.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:45.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:45.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:45.69#ibcon#enter wrdev, iclass 40, count 2 2006.257.06:43:45.69#ibcon#first serial, iclass 40, count 2 2006.257.06:43:45.69#ibcon#enter sib2, iclass 40, count 2 2006.257.06:43:45.69#ibcon#flushed, iclass 40, count 2 2006.257.06:43:45.69#ibcon#about to write, iclass 40, count 2 2006.257.06:43:45.69#ibcon#wrote, iclass 40, count 2 2006.257.06:43:45.69#ibcon#about to read 3, iclass 40, count 2 2006.257.06:43:45.71#ibcon#read 3, iclass 40, count 2 2006.257.06:43:45.71#ibcon#about to read 4, iclass 40, count 2 2006.257.06:43:45.71#ibcon#read 4, iclass 40, count 2 2006.257.06:43:45.71#ibcon#about to read 5, iclass 40, count 2 2006.257.06:43:45.71#ibcon#read 5, iclass 40, count 2 2006.257.06:43:45.71#ibcon#about to read 6, iclass 40, count 2 2006.257.06:43:45.71#ibcon#read 6, iclass 40, count 2 2006.257.06:43:45.71#ibcon#end of sib2, iclass 40, count 2 2006.257.06:43:45.71#ibcon#*mode == 0, iclass 40, count 2 2006.257.06:43:45.71#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.06:43:45.71#ibcon#[25=AT05-04\r\n] 2006.257.06:43:45.71#ibcon#*before write, iclass 40, count 2 2006.257.06:43:45.71#ibcon#enter sib2, iclass 40, count 2 2006.257.06:43:45.71#ibcon#flushed, iclass 40, count 2 2006.257.06:43:45.71#ibcon#about to write, iclass 40, count 2 2006.257.06:43:45.71#ibcon#wrote, iclass 40, count 2 2006.257.06:43:45.71#ibcon#about to read 3, iclass 40, count 2 2006.257.06:43:45.74#ibcon#read 3, iclass 40, count 2 2006.257.06:43:45.74#ibcon#about to read 4, iclass 40, count 2 2006.257.06:43:45.74#ibcon#read 4, iclass 40, count 2 2006.257.06:43:45.74#ibcon#about to read 5, iclass 40, count 2 2006.257.06:43:45.74#ibcon#read 5, iclass 40, count 2 2006.257.06:43:45.74#ibcon#about to read 6, iclass 40, count 2 2006.257.06:43:45.74#ibcon#read 6, iclass 40, count 2 2006.257.06:43:45.74#ibcon#end of sib2, iclass 40, count 2 2006.257.06:43:45.74#ibcon#*after write, iclass 40, count 2 2006.257.06:43:45.74#ibcon#*before return 0, iclass 40, count 2 2006.257.06:43:45.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:45.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:45.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.06:43:45.74#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:45.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:45.86#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:45.86#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:45.86#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:43:45.86#ibcon#first serial, iclass 40, count 0 2006.257.06:43:45.86#ibcon#enter sib2, iclass 40, count 0 2006.257.06:43:45.86#ibcon#flushed, iclass 40, count 0 2006.257.06:43:45.86#ibcon#about to write, iclass 40, count 0 2006.257.06:43:45.86#ibcon#wrote, iclass 40, count 0 2006.257.06:43:45.86#ibcon#about to read 3, iclass 40, count 0 2006.257.06:43:45.88#ibcon#read 3, iclass 40, count 0 2006.257.06:43:45.88#ibcon#about to read 4, iclass 40, count 0 2006.257.06:43:45.88#ibcon#read 4, iclass 40, count 0 2006.257.06:43:45.88#ibcon#about to read 5, iclass 40, count 0 2006.257.06:43:45.88#ibcon#read 5, iclass 40, count 0 2006.257.06:43:45.88#ibcon#about to read 6, iclass 40, count 0 2006.257.06:43:45.88#ibcon#read 6, iclass 40, count 0 2006.257.06:43:45.88#ibcon#end of sib2, iclass 40, count 0 2006.257.06:43:45.88#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:43:45.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:43:45.88#ibcon#[25=USB\r\n] 2006.257.06:43:45.88#ibcon#*before write, iclass 40, count 0 2006.257.06:43:45.88#ibcon#enter sib2, iclass 40, count 0 2006.257.06:43:45.88#ibcon#flushed, iclass 40, count 0 2006.257.06:43:45.88#ibcon#about to write, iclass 40, count 0 2006.257.06:43:45.88#ibcon#wrote, iclass 40, count 0 2006.257.06:43:45.88#ibcon#about to read 3, iclass 40, count 0 2006.257.06:43:45.91#ibcon#read 3, iclass 40, count 0 2006.257.06:43:45.91#ibcon#about to read 4, iclass 40, count 0 2006.257.06:43:45.91#ibcon#read 4, iclass 40, count 0 2006.257.06:43:45.91#ibcon#about to read 5, iclass 40, count 0 2006.257.06:43:45.91#ibcon#read 5, iclass 40, count 0 2006.257.06:43:45.91#ibcon#about to read 6, iclass 40, count 0 2006.257.06:43:45.91#ibcon#read 6, iclass 40, count 0 2006.257.06:43:45.91#ibcon#end of sib2, iclass 40, count 0 2006.257.06:43:45.91#ibcon#*after write, iclass 40, count 0 2006.257.06:43:45.91#ibcon#*before return 0, iclass 40, count 0 2006.257.06:43:45.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:45.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:45.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:43:45.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:43:45.91$vck44/valo=6,814.99 2006.257.06:43:45.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.06:43:45.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.06:43:45.91#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:45.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:45.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:45.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:45.91#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:43:45.91#ibcon#first serial, iclass 4, count 0 2006.257.06:43:45.91#ibcon#enter sib2, iclass 4, count 0 2006.257.06:43:45.91#ibcon#flushed, iclass 4, count 0 2006.257.06:43:45.91#ibcon#about to write, iclass 4, count 0 2006.257.06:43:45.91#ibcon#wrote, iclass 4, count 0 2006.257.06:43:45.91#ibcon#about to read 3, iclass 4, count 0 2006.257.06:43:45.93#ibcon#read 3, iclass 4, count 0 2006.257.06:43:45.93#ibcon#about to read 4, iclass 4, count 0 2006.257.06:43:45.93#ibcon#read 4, iclass 4, count 0 2006.257.06:43:45.93#ibcon#about to read 5, iclass 4, count 0 2006.257.06:43:45.93#ibcon#read 5, iclass 4, count 0 2006.257.06:43:45.93#ibcon#about to read 6, iclass 4, count 0 2006.257.06:43:45.93#ibcon#read 6, iclass 4, count 0 2006.257.06:43:45.93#ibcon#end of sib2, iclass 4, count 0 2006.257.06:43:45.93#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:43:45.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:43:45.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:43:45.93#ibcon#*before write, iclass 4, count 0 2006.257.06:43:45.93#ibcon#enter sib2, iclass 4, count 0 2006.257.06:43:45.93#ibcon#flushed, iclass 4, count 0 2006.257.06:43:45.93#ibcon#about to write, iclass 4, count 0 2006.257.06:43:45.93#ibcon#wrote, iclass 4, count 0 2006.257.06:43:45.93#ibcon#about to read 3, iclass 4, count 0 2006.257.06:43:45.97#ibcon#read 3, iclass 4, count 0 2006.257.06:43:45.97#ibcon#about to read 4, iclass 4, count 0 2006.257.06:43:45.97#ibcon#read 4, iclass 4, count 0 2006.257.06:43:45.97#ibcon#about to read 5, iclass 4, count 0 2006.257.06:43:45.97#ibcon#read 5, iclass 4, count 0 2006.257.06:43:45.97#ibcon#about to read 6, iclass 4, count 0 2006.257.06:43:45.97#ibcon#read 6, iclass 4, count 0 2006.257.06:43:45.97#ibcon#end of sib2, iclass 4, count 0 2006.257.06:43:45.97#ibcon#*after write, iclass 4, count 0 2006.257.06:43:45.97#ibcon#*before return 0, iclass 4, count 0 2006.257.06:43:45.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:45.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:45.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:43:45.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:43:45.97$vck44/va=6,4 2006.257.06:43:45.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.06:43:45.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.06:43:45.97#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:45.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:46.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:46.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:46.03#ibcon#enter wrdev, iclass 6, count 2 2006.257.06:43:46.03#ibcon#first serial, iclass 6, count 2 2006.257.06:43:46.03#ibcon#enter sib2, iclass 6, count 2 2006.257.06:43:46.03#ibcon#flushed, iclass 6, count 2 2006.257.06:43:46.03#ibcon#about to write, iclass 6, count 2 2006.257.06:43:46.03#ibcon#wrote, iclass 6, count 2 2006.257.06:43:46.03#ibcon#about to read 3, iclass 6, count 2 2006.257.06:43:46.05#ibcon#read 3, iclass 6, count 2 2006.257.06:43:46.05#ibcon#about to read 4, iclass 6, count 2 2006.257.06:43:46.05#ibcon#read 4, iclass 6, count 2 2006.257.06:43:46.05#ibcon#about to read 5, iclass 6, count 2 2006.257.06:43:46.05#ibcon#read 5, iclass 6, count 2 2006.257.06:43:46.05#ibcon#about to read 6, iclass 6, count 2 2006.257.06:43:46.05#ibcon#read 6, iclass 6, count 2 2006.257.06:43:46.05#ibcon#end of sib2, iclass 6, count 2 2006.257.06:43:46.05#ibcon#*mode == 0, iclass 6, count 2 2006.257.06:43:46.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.06:43:46.05#ibcon#[25=AT06-04\r\n] 2006.257.06:43:46.05#ibcon#*before write, iclass 6, count 2 2006.257.06:43:46.05#ibcon#enter sib2, iclass 6, count 2 2006.257.06:43:46.05#ibcon#flushed, iclass 6, count 2 2006.257.06:43:46.05#ibcon#about to write, iclass 6, count 2 2006.257.06:43:46.05#ibcon#wrote, iclass 6, count 2 2006.257.06:43:46.05#ibcon#about to read 3, iclass 6, count 2 2006.257.06:43:46.08#ibcon#read 3, iclass 6, count 2 2006.257.06:43:46.08#ibcon#about to read 4, iclass 6, count 2 2006.257.06:43:46.08#ibcon#read 4, iclass 6, count 2 2006.257.06:43:46.08#ibcon#about to read 5, iclass 6, count 2 2006.257.06:43:46.08#ibcon#read 5, iclass 6, count 2 2006.257.06:43:46.08#ibcon#about to read 6, iclass 6, count 2 2006.257.06:43:46.08#ibcon#read 6, iclass 6, count 2 2006.257.06:43:46.08#ibcon#end of sib2, iclass 6, count 2 2006.257.06:43:46.08#ibcon#*after write, iclass 6, count 2 2006.257.06:43:46.08#ibcon#*before return 0, iclass 6, count 2 2006.257.06:43:46.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:46.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:46.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.06:43:46.08#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:46.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:46.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:46.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:46.20#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:43:46.20#ibcon#first serial, iclass 6, count 0 2006.257.06:43:46.20#ibcon#enter sib2, iclass 6, count 0 2006.257.06:43:46.20#ibcon#flushed, iclass 6, count 0 2006.257.06:43:46.20#ibcon#about to write, iclass 6, count 0 2006.257.06:43:46.20#ibcon#wrote, iclass 6, count 0 2006.257.06:43:46.20#ibcon#about to read 3, iclass 6, count 0 2006.257.06:43:46.22#ibcon#read 3, iclass 6, count 0 2006.257.06:43:46.22#ibcon#about to read 4, iclass 6, count 0 2006.257.06:43:46.22#ibcon#read 4, iclass 6, count 0 2006.257.06:43:46.22#ibcon#about to read 5, iclass 6, count 0 2006.257.06:43:46.22#ibcon#read 5, iclass 6, count 0 2006.257.06:43:46.22#ibcon#about to read 6, iclass 6, count 0 2006.257.06:43:46.22#ibcon#read 6, iclass 6, count 0 2006.257.06:43:46.22#ibcon#end of sib2, iclass 6, count 0 2006.257.06:43:46.22#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:43:46.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:43:46.22#ibcon#[25=USB\r\n] 2006.257.06:43:46.22#ibcon#*before write, iclass 6, count 0 2006.257.06:43:46.22#ibcon#enter sib2, iclass 6, count 0 2006.257.06:43:46.22#ibcon#flushed, iclass 6, count 0 2006.257.06:43:46.22#ibcon#about to write, iclass 6, count 0 2006.257.06:43:46.22#ibcon#wrote, iclass 6, count 0 2006.257.06:43:46.22#ibcon#about to read 3, iclass 6, count 0 2006.257.06:43:46.25#ibcon#read 3, iclass 6, count 0 2006.257.06:43:46.25#ibcon#about to read 4, iclass 6, count 0 2006.257.06:43:46.25#ibcon#read 4, iclass 6, count 0 2006.257.06:43:46.25#ibcon#about to read 5, iclass 6, count 0 2006.257.06:43:46.25#ibcon#read 5, iclass 6, count 0 2006.257.06:43:46.25#ibcon#about to read 6, iclass 6, count 0 2006.257.06:43:46.25#ibcon#read 6, iclass 6, count 0 2006.257.06:43:46.25#ibcon#end of sib2, iclass 6, count 0 2006.257.06:43:46.25#ibcon#*after write, iclass 6, count 0 2006.257.06:43:46.25#ibcon#*before return 0, iclass 6, count 0 2006.257.06:43:46.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:46.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:46.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:43:46.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:43:46.25$vck44/valo=7,864.99 2006.257.06:43:46.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.06:43:46.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.06:43:46.25#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:46.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:46.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:46.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:46.25#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:43:46.25#ibcon#first serial, iclass 10, count 0 2006.257.06:43:46.25#ibcon#enter sib2, iclass 10, count 0 2006.257.06:43:46.25#ibcon#flushed, iclass 10, count 0 2006.257.06:43:46.25#ibcon#about to write, iclass 10, count 0 2006.257.06:43:46.25#ibcon#wrote, iclass 10, count 0 2006.257.06:43:46.25#ibcon#about to read 3, iclass 10, count 0 2006.257.06:43:46.27#ibcon#read 3, iclass 10, count 0 2006.257.06:43:46.27#ibcon#about to read 4, iclass 10, count 0 2006.257.06:43:46.27#ibcon#read 4, iclass 10, count 0 2006.257.06:43:46.27#ibcon#about to read 5, iclass 10, count 0 2006.257.06:43:46.27#ibcon#read 5, iclass 10, count 0 2006.257.06:43:46.27#ibcon#about to read 6, iclass 10, count 0 2006.257.06:43:46.27#ibcon#read 6, iclass 10, count 0 2006.257.06:43:46.27#ibcon#end of sib2, iclass 10, count 0 2006.257.06:43:46.27#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:43:46.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:43:46.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:43:46.27#ibcon#*before write, iclass 10, count 0 2006.257.06:43:46.27#ibcon#enter sib2, iclass 10, count 0 2006.257.06:43:46.27#ibcon#flushed, iclass 10, count 0 2006.257.06:43:46.27#ibcon#about to write, iclass 10, count 0 2006.257.06:43:46.27#ibcon#wrote, iclass 10, count 0 2006.257.06:43:46.27#ibcon#about to read 3, iclass 10, count 0 2006.257.06:43:46.31#ibcon#read 3, iclass 10, count 0 2006.257.06:43:46.31#ibcon#about to read 4, iclass 10, count 0 2006.257.06:43:46.31#ibcon#read 4, iclass 10, count 0 2006.257.06:43:46.31#ibcon#about to read 5, iclass 10, count 0 2006.257.06:43:46.31#ibcon#read 5, iclass 10, count 0 2006.257.06:43:46.31#ibcon#about to read 6, iclass 10, count 0 2006.257.06:43:46.31#ibcon#read 6, iclass 10, count 0 2006.257.06:43:46.31#ibcon#end of sib2, iclass 10, count 0 2006.257.06:43:46.31#ibcon#*after write, iclass 10, count 0 2006.257.06:43:46.31#ibcon#*before return 0, iclass 10, count 0 2006.257.06:43:46.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:46.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:46.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:43:46.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:43:46.31$vck44/va=7,4 2006.257.06:43:46.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.06:43:46.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.06:43:46.31#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:46.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:46.37#abcon#<5=/16 0.8 3.8 20.66 891012.3\r\n> 2006.257.06:43:46.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:46.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:46.37#ibcon#enter wrdev, iclass 12, count 2 2006.257.06:43:46.37#ibcon#first serial, iclass 12, count 2 2006.257.06:43:46.37#ibcon#enter sib2, iclass 12, count 2 2006.257.06:43:46.37#ibcon#flushed, iclass 12, count 2 2006.257.06:43:46.37#ibcon#about to write, iclass 12, count 2 2006.257.06:43:46.37#ibcon#wrote, iclass 12, count 2 2006.257.06:43:46.37#ibcon#about to read 3, iclass 12, count 2 2006.257.06:43:46.39#ibcon#read 3, iclass 12, count 2 2006.257.06:43:46.39#ibcon#about to read 4, iclass 12, count 2 2006.257.06:43:46.39#ibcon#read 4, iclass 12, count 2 2006.257.06:43:46.39#ibcon#about to read 5, iclass 12, count 2 2006.257.06:43:46.39#ibcon#read 5, iclass 12, count 2 2006.257.06:43:46.39#ibcon#about to read 6, iclass 12, count 2 2006.257.06:43:46.39#ibcon#read 6, iclass 12, count 2 2006.257.06:43:46.39#ibcon#end of sib2, iclass 12, count 2 2006.257.06:43:46.39#ibcon#*mode == 0, iclass 12, count 2 2006.257.06:43:46.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.06:43:46.39#ibcon#[25=AT07-04\r\n] 2006.257.06:43:46.39#ibcon#*before write, iclass 12, count 2 2006.257.06:43:46.39#ibcon#enter sib2, iclass 12, count 2 2006.257.06:43:46.39#ibcon#flushed, iclass 12, count 2 2006.257.06:43:46.39#ibcon#about to write, iclass 12, count 2 2006.257.06:43:46.39#ibcon#wrote, iclass 12, count 2 2006.257.06:43:46.39#ibcon#about to read 3, iclass 12, count 2 2006.257.06:43:46.39#abcon#{5=INTERFACE CLEAR} 2006.257.06:43:46.42#ibcon#read 3, iclass 12, count 2 2006.257.06:43:46.42#ibcon#about to read 4, iclass 12, count 2 2006.257.06:43:46.42#ibcon#read 4, iclass 12, count 2 2006.257.06:43:46.42#ibcon#about to read 5, iclass 12, count 2 2006.257.06:43:46.42#ibcon#read 5, iclass 12, count 2 2006.257.06:43:46.42#ibcon#about to read 6, iclass 12, count 2 2006.257.06:43:46.42#ibcon#read 6, iclass 12, count 2 2006.257.06:43:46.42#ibcon#end of sib2, iclass 12, count 2 2006.257.06:43:46.42#ibcon#*after write, iclass 12, count 2 2006.257.06:43:46.42#ibcon#*before return 0, iclass 12, count 2 2006.257.06:43:46.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:46.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:46.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.06:43:46.42#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:46.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:46.45#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:43:46.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:46.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:46.54#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:43:46.54#ibcon#first serial, iclass 12, count 0 2006.257.06:43:46.54#ibcon#enter sib2, iclass 12, count 0 2006.257.06:43:46.54#ibcon#flushed, iclass 12, count 0 2006.257.06:43:46.54#ibcon#about to write, iclass 12, count 0 2006.257.06:43:46.54#ibcon#wrote, iclass 12, count 0 2006.257.06:43:46.54#ibcon#about to read 3, iclass 12, count 0 2006.257.06:43:46.56#ibcon#read 3, iclass 12, count 0 2006.257.06:43:46.56#ibcon#about to read 4, iclass 12, count 0 2006.257.06:43:46.56#ibcon#read 4, iclass 12, count 0 2006.257.06:43:46.56#ibcon#about to read 5, iclass 12, count 0 2006.257.06:43:46.56#ibcon#read 5, iclass 12, count 0 2006.257.06:43:46.56#ibcon#about to read 6, iclass 12, count 0 2006.257.06:43:46.56#ibcon#read 6, iclass 12, count 0 2006.257.06:43:46.56#ibcon#end of sib2, iclass 12, count 0 2006.257.06:43:46.56#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:43:46.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:43:46.56#ibcon#[25=USB\r\n] 2006.257.06:43:46.56#ibcon#*before write, iclass 12, count 0 2006.257.06:43:46.56#ibcon#enter sib2, iclass 12, count 0 2006.257.06:43:46.56#ibcon#flushed, iclass 12, count 0 2006.257.06:43:46.56#ibcon#about to write, iclass 12, count 0 2006.257.06:43:46.56#ibcon#wrote, iclass 12, count 0 2006.257.06:43:46.56#ibcon#about to read 3, iclass 12, count 0 2006.257.06:43:46.59#ibcon#read 3, iclass 12, count 0 2006.257.06:43:46.59#ibcon#about to read 4, iclass 12, count 0 2006.257.06:43:46.59#ibcon#read 4, iclass 12, count 0 2006.257.06:43:46.59#ibcon#about to read 5, iclass 12, count 0 2006.257.06:43:46.59#ibcon#read 5, iclass 12, count 0 2006.257.06:43:46.59#ibcon#about to read 6, iclass 12, count 0 2006.257.06:43:46.59#ibcon#read 6, iclass 12, count 0 2006.257.06:43:46.59#ibcon#end of sib2, iclass 12, count 0 2006.257.06:43:46.59#ibcon#*after write, iclass 12, count 0 2006.257.06:43:46.59#ibcon#*before return 0, iclass 12, count 0 2006.257.06:43:46.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:46.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:46.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:43:46.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:43:46.59$vck44/valo=8,884.99 2006.257.06:43:46.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.06:43:46.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.06:43:46.59#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:46.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:46.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:46.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:46.59#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:43:46.59#ibcon#first serial, iclass 18, count 0 2006.257.06:43:46.59#ibcon#enter sib2, iclass 18, count 0 2006.257.06:43:46.59#ibcon#flushed, iclass 18, count 0 2006.257.06:43:46.59#ibcon#about to write, iclass 18, count 0 2006.257.06:43:46.59#ibcon#wrote, iclass 18, count 0 2006.257.06:43:46.59#ibcon#about to read 3, iclass 18, count 0 2006.257.06:43:46.61#ibcon#read 3, iclass 18, count 0 2006.257.06:43:46.61#ibcon#about to read 4, iclass 18, count 0 2006.257.06:43:46.61#ibcon#read 4, iclass 18, count 0 2006.257.06:43:46.61#ibcon#about to read 5, iclass 18, count 0 2006.257.06:43:46.61#ibcon#read 5, iclass 18, count 0 2006.257.06:43:46.61#ibcon#about to read 6, iclass 18, count 0 2006.257.06:43:46.61#ibcon#read 6, iclass 18, count 0 2006.257.06:43:46.61#ibcon#end of sib2, iclass 18, count 0 2006.257.06:43:46.61#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:43:46.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:43:46.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:43:46.61#ibcon#*before write, iclass 18, count 0 2006.257.06:43:46.61#ibcon#enter sib2, iclass 18, count 0 2006.257.06:43:46.61#ibcon#flushed, iclass 18, count 0 2006.257.06:43:46.61#ibcon#about to write, iclass 18, count 0 2006.257.06:43:46.61#ibcon#wrote, iclass 18, count 0 2006.257.06:43:46.61#ibcon#about to read 3, iclass 18, count 0 2006.257.06:43:46.65#ibcon#read 3, iclass 18, count 0 2006.257.06:43:46.65#ibcon#about to read 4, iclass 18, count 0 2006.257.06:43:46.65#ibcon#read 4, iclass 18, count 0 2006.257.06:43:46.65#ibcon#about to read 5, iclass 18, count 0 2006.257.06:43:46.65#ibcon#read 5, iclass 18, count 0 2006.257.06:43:46.65#ibcon#about to read 6, iclass 18, count 0 2006.257.06:43:46.65#ibcon#read 6, iclass 18, count 0 2006.257.06:43:46.65#ibcon#end of sib2, iclass 18, count 0 2006.257.06:43:46.65#ibcon#*after write, iclass 18, count 0 2006.257.06:43:46.65#ibcon#*before return 0, iclass 18, count 0 2006.257.06:43:46.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:46.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:46.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:43:46.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:43:46.65$vck44/va=8,4 2006.257.06:43:46.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.06:43:46.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.06:43:46.65#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:46.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:43:46.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:43:46.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:43:46.71#ibcon#enter wrdev, iclass 20, count 2 2006.257.06:43:46.71#ibcon#first serial, iclass 20, count 2 2006.257.06:43:46.71#ibcon#enter sib2, iclass 20, count 2 2006.257.06:43:46.71#ibcon#flushed, iclass 20, count 2 2006.257.06:43:46.71#ibcon#about to write, iclass 20, count 2 2006.257.06:43:46.71#ibcon#wrote, iclass 20, count 2 2006.257.06:43:46.71#ibcon#about to read 3, iclass 20, count 2 2006.257.06:43:46.73#ibcon#read 3, iclass 20, count 2 2006.257.06:43:46.73#ibcon#about to read 4, iclass 20, count 2 2006.257.06:43:46.73#ibcon#read 4, iclass 20, count 2 2006.257.06:43:46.73#ibcon#about to read 5, iclass 20, count 2 2006.257.06:43:46.73#ibcon#read 5, iclass 20, count 2 2006.257.06:43:46.73#ibcon#about to read 6, iclass 20, count 2 2006.257.06:43:46.73#ibcon#read 6, iclass 20, count 2 2006.257.06:43:46.73#ibcon#end of sib2, iclass 20, count 2 2006.257.06:43:46.73#ibcon#*mode == 0, iclass 20, count 2 2006.257.06:43:46.73#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.06:43:46.73#ibcon#[25=AT08-04\r\n] 2006.257.06:43:46.73#ibcon#*before write, iclass 20, count 2 2006.257.06:43:46.73#ibcon#enter sib2, iclass 20, count 2 2006.257.06:43:46.73#ibcon#flushed, iclass 20, count 2 2006.257.06:43:46.73#ibcon#about to write, iclass 20, count 2 2006.257.06:43:46.73#ibcon#wrote, iclass 20, count 2 2006.257.06:43:46.73#ibcon#about to read 3, iclass 20, count 2 2006.257.06:43:46.76#ibcon#read 3, iclass 20, count 2 2006.257.06:43:46.76#ibcon#about to read 4, iclass 20, count 2 2006.257.06:43:46.76#ibcon#read 4, iclass 20, count 2 2006.257.06:43:46.76#ibcon#about to read 5, iclass 20, count 2 2006.257.06:43:46.76#ibcon#read 5, iclass 20, count 2 2006.257.06:43:46.76#ibcon#about to read 6, iclass 20, count 2 2006.257.06:43:46.76#ibcon#read 6, iclass 20, count 2 2006.257.06:43:46.76#ibcon#end of sib2, iclass 20, count 2 2006.257.06:43:46.76#ibcon#*after write, iclass 20, count 2 2006.257.06:43:46.76#ibcon#*before return 0, iclass 20, count 2 2006.257.06:43:46.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:43:46.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:43:46.76#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.06:43:46.76#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:46.76#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:43:46.88#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:43:46.88#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:43:46.88#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:43:46.88#ibcon#first serial, iclass 20, count 0 2006.257.06:43:46.88#ibcon#enter sib2, iclass 20, count 0 2006.257.06:43:46.88#ibcon#flushed, iclass 20, count 0 2006.257.06:43:46.88#ibcon#about to write, iclass 20, count 0 2006.257.06:43:46.88#ibcon#wrote, iclass 20, count 0 2006.257.06:43:46.88#ibcon#about to read 3, iclass 20, count 0 2006.257.06:43:46.90#ibcon#read 3, iclass 20, count 0 2006.257.06:43:46.90#ibcon#about to read 4, iclass 20, count 0 2006.257.06:43:46.90#ibcon#read 4, iclass 20, count 0 2006.257.06:43:46.90#ibcon#about to read 5, iclass 20, count 0 2006.257.06:43:46.90#ibcon#read 5, iclass 20, count 0 2006.257.06:43:46.90#ibcon#about to read 6, iclass 20, count 0 2006.257.06:43:46.90#ibcon#read 6, iclass 20, count 0 2006.257.06:43:46.90#ibcon#end of sib2, iclass 20, count 0 2006.257.06:43:46.90#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:43:46.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:43:46.90#ibcon#[25=USB\r\n] 2006.257.06:43:46.90#ibcon#*before write, iclass 20, count 0 2006.257.06:43:46.90#ibcon#enter sib2, iclass 20, count 0 2006.257.06:43:46.90#ibcon#flushed, iclass 20, count 0 2006.257.06:43:46.90#ibcon#about to write, iclass 20, count 0 2006.257.06:43:46.90#ibcon#wrote, iclass 20, count 0 2006.257.06:43:46.90#ibcon#about to read 3, iclass 20, count 0 2006.257.06:43:46.93#ibcon#read 3, iclass 20, count 0 2006.257.06:43:46.93#ibcon#about to read 4, iclass 20, count 0 2006.257.06:43:46.93#ibcon#read 4, iclass 20, count 0 2006.257.06:43:46.93#ibcon#about to read 5, iclass 20, count 0 2006.257.06:43:46.93#ibcon#read 5, iclass 20, count 0 2006.257.06:43:46.93#ibcon#about to read 6, iclass 20, count 0 2006.257.06:43:46.93#ibcon#read 6, iclass 20, count 0 2006.257.06:43:46.93#ibcon#end of sib2, iclass 20, count 0 2006.257.06:43:46.93#ibcon#*after write, iclass 20, count 0 2006.257.06:43:46.93#ibcon#*before return 0, iclass 20, count 0 2006.257.06:43:46.93#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:43:46.93#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:43:46.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:43:46.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:43:46.93$vck44/vblo=1,629.99 2006.257.06:43:46.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.06:43:46.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.06:43:46.93#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:46.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:46.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:46.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:46.93#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:43:46.93#ibcon#first serial, iclass 22, count 0 2006.257.06:43:46.93#ibcon#enter sib2, iclass 22, count 0 2006.257.06:43:46.93#ibcon#flushed, iclass 22, count 0 2006.257.06:43:46.93#ibcon#about to write, iclass 22, count 0 2006.257.06:43:46.93#ibcon#wrote, iclass 22, count 0 2006.257.06:43:46.93#ibcon#about to read 3, iclass 22, count 0 2006.257.06:43:46.95#ibcon#read 3, iclass 22, count 0 2006.257.06:43:46.95#ibcon#about to read 4, iclass 22, count 0 2006.257.06:43:46.95#ibcon#read 4, iclass 22, count 0 2006.257.06:43:46.95#ibcon#about to read 5, iclass 22, count 0 2006.257.06:43:46.95#ibcon#read 5, iclass 22, count 0 2006.257.06:43:46.95#ibcon#about to read 6, iclass 22, count 0 2006.257.06:43:46.95#ibcon#read 6, iclass 22, count 0 2006.257.06:43:46.95#ibcon#end of sib2, iclass 22, count 0 2006.257.06:43:46.95#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:43:46.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:43:46.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:43:46.95#ibcon#*before write, iclass 22, count 0 2006.257.06:43:46.95#ibcon#enter sib2, iclass 22, count 0 2006.257.06:43:46.95#ibcon#flushed, iclass 22, count 0 2006.257.06:43:46.95#ibcon#about to write, iclass 22, count 0 2006.257.06:43:46.95#ibcon#wrote, iclass 22, count 0 2006.257.06:43:46.95#ibcon#about to read 3, iclass 22, count 0 2006.257.06:43:46.99#ibcon#read 3, iclass 22, count 0 2006.257.06:43:46.99#ibcon#about to read 4, iclass 22, count 0 2006.257.06:43:46.99#ibcon#read 4, iclass 22, count 0 2006.257.06:43:46.99#ibcon#about to read 5, iclass 22, count 0 2006.257.06:43:46.99#ibcon#read 5, iclass 22, count 0 2006.257.06:43:46.99#ibcon#about to read 6, iclass 22, count 0 2006.257.06:43:46.99#ibcon#read 6, iclass 22, count 0 2006.257.06:43:46.99#ibcon#end of sib2, iclass 22, count 0 2006.257.06:43:46.99#ibcon#*after write, iclass 22, count 0 2006.257.06:43:46.99#ibcon#*before return 0, iclass 22, count 0 2006.257.06:43:46.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:46.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:43:46.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:43:46.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:43:46.99$vck44/vb=1,4 2006.257.06:43:46.99#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.06:43:46.99#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.06:43:46.99#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:46.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:46.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:46.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:46.99#ibcon#enter wrdev, iclass 24, count 2 2006.257.06:43:46.99#ibcon#first serial, iclass 24, count 2 2006.257.06:43:46.99#ibcon#enter sib2, iclass 24, count 2 2006.257.06:43:46.99#ibcon#flushed, iclass 24, count 2 2006.257.06:43:46.99#ibcon#about to write, iclass 24, count 2 2006.257.06:43:46.99#ibcon#wrote, iclass 24, count 2 2006.257.06:43:46.99#ibcon#about to read 3, iclass 24, count 2 2006.257.06:43:47.01#ibcon#read 3, iclass 24, count 2 2006.257.06:43:47.01#ibcon#about to read 4, iclass 24, count 2 2006.257.06:43:47.01#ibcon#read 4, iclass 24, count 2 2006.257.06:43:47.01#ibcon#about to read 5, iclass 24, count 2 2006.257.06:43:47.01#ibcon#read 5, iclass 24, count 2 2006.257.06:43:47.01#ibcon#about to read 6, iclass 24, count 2 2006.257.06:43:47.01#ibcon#read 6, iclass 24, count 2 2006.257.06:43:47.01#ibcon#end of sib2, iclass 24, count 2 2006.257.06:43:47.01#ibcon#*mode == 0, iclass 24, count 2 2006.257.06:43:47.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.06:43:47.01#ibcon#[27=AT01-04\r\n] 2006.257.06:43:47.01#ibcon#*before write, iclass 24, count 2 2006.257.06:43:47.01#ibcon#enter sib2, iclass 24, count 2 2006.257.06:43:47.01#ibcon#flushed, iclass 24, count 2 2006.257.06:43:47.01#ibcon#about to write, iclass 24, count 2 2006.257.06:43:47.01#ibcon#wrote, iclass 24, count 2 2006.257.06:43:47.01#ibcon#about to read 3, iclass 24, count 2 2006.257.06:43:47.04#ibcon#read 3, iclass 24, count 2 2006.257.06:43:47.04#ibcon#about to read 4, iclass 24, count 2 2006.257.06:43:47.04#ibcon#read 4, iclass 24, count 2 2006.257.06:43:47.04#ibcon#about to read 5, iclass 24, count 2 2006.257.06:43:47.04#ibcon#read 5, iclass 24, count 2 2006.257.06:43:47.04#ibcon#about to read 6, iclass 24, count 2 2006.257.06:43:47.04#ibcon#read 6, iclass 24, count 2 2006.257.06:43:47.04#ibcon#end of sib2, iclass 24, count 2 2006.257.06:43:47.04#ibcon#*after write, iclass 24, count 2 2006.257.06:43:47.04#ibcon#*before return 0, iclass 24, count 2 2006.257.06:43:47.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:47.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:43:47.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.06:43:47.04#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:47.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:47.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:47.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:47.16#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:43:47.16#ibcon#first serial, iclass 24, count 0 2006.257.06:43:47.16#ibcon#enter sib2, iclass 24, count 0 2006.257.06:43:47.16#ibcon#flushed, iclass 24, count 0 2006.257.06:43:47.16#ibcon#about to write, iclass 24, count 0 2006.257.06:43:47.16#ibcon#wrote, iclass 24, count 0 2006.257.06:43:47.16#ibcon#about to read 3, iclass 24, count 0 2006.257.06:43:47.18#ibcon#read 3, iclass 24, count 0 2006.257.06:43:47.18#ibcon#about to read 4, iclass 24, count 0 2006.257.06:43:47.18#ibcon#read 4, iclass 24, count 0 2006.257.06:43:47.18#ibcon#about to read 5, iclass 24, count 0 2006.257.06:43:47.18#ibcon#read 5, iclass 24, count 0 2006.257.06:43:47.18#ibcon#about to read 6, iclass 24, count 0 2006.257.06:43:47.18#ibcon#read 6, iclass 24, count 0 2006.257.06:43:47.18#ibcon#end of sib2, iclass 24, count 0 2006.257.06:43:47.18#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:43:47.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:43:47.18#ibcon#[27=USB\r\n] 2006.257.06:43:47.18#ibcon#*before write, iclass 24, count 0 2006.257.06:43:47.18#ibcon#enter sib2, iclass 24, count 0 2006.257.06:43:47.18#ibcon#flushed, iclass 24, count 0 2006.257.06:43:47.18#ibcon#about to write, iclass 24, count 0 2006.257.06:43:47.18#ibcon#wrote, iclass 24, count 0 2006.257.06:43:47.18#ibcon#about to read 3, iclass 24, count 0 2006.257.06:43:47.21#ibcon#read 3, iclass 24, count 0 2006.257.06:43:47.21#ibcon#about to read 4, iclass 24, count 0 2006.257.06:43:47.21#ibcon#read 4, iclass 24, count 0 2006.257.06:43:47.21#ibcon#about to read 5, iclass 24, count 0 2006.257.06:43:47.21#ibcon#read 5, iclass 24, count 0 2006.257.06:43:47.21#ibcon#about to read 6, iclass 24, count 0 2006.257.06:43:47.21#ibcon#read 6, iclass 24, count 0 2006.257.06:43:47.21#ibcon#end of sib2, iclass 24, count 0 2006.257.06:43:47.21#ibcon#*after write, iclass 24, count 0 2006.257.06:43:47.21#ibcon#*before return 0, iclass 24, count 0 2006.257.06:43:47.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:47.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:43:47.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:43:47.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:43:47.21$vck44/vblo=2,634.99 2006.257.06:43:47.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.06:43:47.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.06:43:47.21#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:47.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:47.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:47.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:47.21#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:43:47.21#ibcon#first serial, iclass 26, count 0 2006.257.06:43:47.21#ibcon#enter sib2, iclass 26, count 0 2006.257.06:43:47.21#ibcon#flushed, iclass 26, count 0 2006.257.06:43:47.21#ibcon#about to write, iclass 26, count 0 2006.257.06:43:47.21#ibcon#wrote, iclass 26, count 0 2006.257.06:43:47.21#ibcon#about to read 3, iclass 26, count 0 2006.257.06:43:47.23#ibcon#read 3, iclass 26, count 0 2006.257.06:43:47.23#ibcon#about to read 4, iclass 26, count 0 2006.257.06:43:47.23#ibcon#read 4, iclass 26, count 0 2006.257.06:43:47.23#ibcon#about to read 5, iclass 26, count 0 2006.257.06:43:47.23#ibcon#read 5, iclass 26, count 0 2006.257.06:43:47.23#ibcon#about to read 6, iclass 26, count 0 2006.257.06:43:47.23#ibcon#read 6, iclass 26, count 0 2006.257.06:43:47.23#ibcon#end of sib2, iclass 26, count 0 2006.257.06:43:47.23#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:43:47.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:43:47.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:43:47.23#ibcon#*before write, iclass 26, count 0 2006.257.06:43:47.23#ibcon#enter sib2, iclass 26, count 0 2006.257.06:43:47.23#ibcon#flushed, iclass 26, count 0 2006.257.06:43:47.23#ibcon#about to write, iclass 26, count 0 2006.257.06:43:47.23#ibcon#wrote, iclass 26, count 0 2006.257.06:43:47.23#ibcon#about to read 3, iclass 26, count 0 2006.257.06:43:47.27#ibcon#read 3, iclass 26, count 0 2006.257.06:43:47.27#ibcon#about to read 4, iclass 26, count 0 2006.257.06:43:47.27#ibcon#read 4, iclass 26, count 0 2006.257.06:43:47.27#ibcon#about to read 5, iclass 26, count 0 2006.257.06:43:47.27#ibcon#read 5, iclass 26, count 0 2006.257.06:43:47.27#ibcon#about to read 6, iclass 26, count 0 2006.257.06:43:47.27#ibcon#read 6, iclass 26, count 0 2006.257.06:43:47.27#ibcon#end of sib2, iclass 26, count 0 2006.257.06:43:47.27#ibcon#*after write, iclass 26, count 0 2006.257.06:43:47.27#ibcon#*before return 0, iclass 26, count 0 2006.257.06:43:47.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:47.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:43:47.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:43:47.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:43:47.27$vck44/vb=2,5 2006.257.06:43:47.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.06:43:47.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.06:43:47.27#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:47.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:47.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:47.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:47.33#ibcon#enter wrdev, iclass 28, count 2 2006.257.06:43:47.33#ibcon#first serial, iclass 28, count 2 2006.257.06:43:47.33#ibcon#enter sib2, iclass 28, count 2 2006.257.06:43:47.33#ibcon#flushed, iclass 28, count 2 2006.257.06:43:47.33#ibcon#about to write, iclass 28, count 2 2006.257.06:43:47.33#ibcon#wrote, iclass 28, count 2 2006.257.06:43:47.33#ibcon#about to read 3, iclass 28, count 2 2006.257.06:43:47.35#ibcon#read 3, iclass 28, count 2 2006.257.06:43:47.35#ibcon#about to read 4, iclass 28, count 2 2006.257.06:43:47.35#ibcon#read 4, iclass 28, count 2 2006.257.06:43:47.35#ibcon#about to read 5, iclass 28, count 2 2006.257.06:43:47.35#ibcon#read 5, iclass 28, count 2 2006.257.06:43:47.35#ibcon#about to read 6, iclass 28, count 2 2006.257.06:43:47.35#ibcon#read 6, iclass 28, count 2 2006.257.06:43:47.35#ibcon#end of sib2, iclass 28, count 2 2006.257.06:43:47.35#ibcon#*mode == 0, iclass 28, count 2 2006.257.06:43:47.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.06:43:47.35#ibcon#[27=AT02-05\r\n] 2006.257.06:43:47.35#ibcon#*before write, iclass 28, count 2 2006.257.06:43:47.35#ibcon#enter sib2, iclass 28, count 2 2006.257.06:43:47.35#ibcon#flushed, iclass 28, count 2 2006.257.06:43:47.35#ibcon#about to write, iclass 28, count 2 2006.257.06:43:47.35#ibcon#wrote, iclass 28, count 2 2006.257.06:43:47.35#ibcon#about to read 3, iclass 28, count 2 2006.257.06:43:47.38#ibcon#read 3, iclass 28, count 2 2006.257.06:43:47.38#ibcon#about to read 4, iclass 28, count 2 2006.257.06:43:47.38#ibcon#read 4, iclass 28, count 2 2006.257.06:43:47.38#ibcon#about to read 5, iclass 28, count 2 2006.257.06:43:47.38#ibcon#read 5, iclass 28, count 2 2006.257.06:43:47.38#ibcon#about to read 6, iclass 28, count 2 2006.257.06:43:47.38#ibcon#read 6, iclass 28, count 2 2006.257.06:43:47.38#ibcon#end of sib2, iclass 28, count 2 2006.257.06:43:47.38#ibcon#*after write, iclass 28, count 2 2006.257.06:43:47.38#ibcon#*before return 0, iclass 28, count 2 2006.257.06:43:47.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:47.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:43:47.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.06:43:47.38#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:47.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:47.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:47.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:47.50#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:43:47.50#ibcon#first serial, iclass 28, count 0 2006.257.06:43:47.50#ibcon#enter sib2, iclass 28, count 0 2006.257.06:43:47.50#ibcon#flushed, iclass 28, count 0 2006.257.06:43:47.50#ibcon#about to write, iclass 28, count 0 2006.257.06:43:47.50#ibcon#wrote, iclass 28, count 0 2006.257.06:43:47.50#ibcon#about to read 3, iclass 28, count 0 2006.257.06:43:47.52#ibcon#read 3, iclass 28, count 0 2006.257.06:43:47.52#ibcon#about to read 4, iclass 28, count 0 2006.257.06:43:47.52#ibcon#read 4, iclass 28, count 0 2006.257.06:43:47.52#ibcon#about to read 5, iclass 28, count 0 2006.257.06:43:47.52#ibcon#read 5, iclass 28, count 0 2006.257.06:43:47.52#ibcon#about to read 6, iclass 28, count 0 2006.257.06:43:47.52#ibcon#read 6, iclass 28, count 0 2006.257.06:43:47.52#ibcon#end of sib2, iclass 28, count 0 2006.257.06:43:47.52#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:43:47.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:43:47.52#ibcon#[27=USB\r\n] 2006.257.06:43:47.52#ibcon#*before write, iclass 28, count 0 2006.257.06:43:47.52#ibcon#enter sib2, iclass 28, count 0 2006.257.06:43:47.52#ibcon#flushed, iclass 28, count 0 2006.257.06:43:47.52#ibcon#about to write, iclass 28, count 0 2006.257.06:43:47.52#ibcon#wrote, iclass 28, count 0 2006.257.06:43:47.52#ibcon#about to read 3, iclass 28, count 0 2006.257.06:43:47.55#ibcon#read 3, iclass 28, count 0 2006.257.06:43:47.55#ibcon#about to read 4, iclass 28, count 0 2006.257.06:43:47.55#ibcon#read 4, iclass 28, count 0 2006.257.06:43:47.55#ibcon#about to read 5, iclass 28, count 0 2006.257.06:43:47.55#ibcon#read 5, iclass 28, count 0 2006.257.06:43:47.55#ibcon#about to read 6, iclass 28, count 0 2006.257.06:43:47.55#ibcon#read 6, iclass 28, count 0 2006.257.06:43:47.55#ibcon#end of sib2, iclass 28, count 0 2006.257.06:43:47.55#ibcon#*after write, iclass 28, count 0 2006.257.06:43:47.55#ibcon#*before return 0, iclass 28, count 0 2006.257.06:43:47.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:47.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:43:47.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:43:47.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:43:47.55$vck44/vblo=3,649.99 2006.257.06:43:47.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.06:43:47.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.06:43:47.55#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:47.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:47.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:47.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:47.55#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:43:47.55#ibcon#first serial, iclass 30, count 0 2006.257.06:43:47.55#ibcon#enter sib2, iclass 30, count 0 2006.257.06:43:47.55#ibcon#flushed, iclass 30, count 0 2006.257.06:43:47.55#ibcon#about to write, iclass 30, count 0 2006.257.06:43:47.55#ibcon#wrote, iclass 30, count 0 2006.257.06:43:47.55#ibcon#about to read 3, iclass 30, count 0 2006.257.06:43:47.57#ibcon#read 3, iclass 30, count 0 2006.257.06:43:47.57#ibcon#about to read 4, iclass 30, count 0 2006.257.06:43:47.57#ibcon#read 4, iclass 30, count 0 2006.257.06:43:47.57#ibcon#about to read 5, iclass 30, count 0 2006.257.06:43:47.57#ibcon#read 5, iclass 30, count 0 2006.257.06:43:47.57#ibcon#about to read 6, iclass 30, count 0 2006.257.06:43:47.57#ibcon#read 6, iclass 30, count 0 2006.257.06:43:47.57#ibcon#end of sib2, iclass 30, count 0 2006.257.06:43:47.57#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:43:47.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:43:47.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:43:47.57#ibcon#*before write, iclass 30, count 0 2006.257.06:43:47.57#ibcon#enter sib2, iclass 30, count 0 2006.257.06:43:47.57#ibcon#flushed, iclass 30, count 0 2006.257.06:43:47.57#ibcon#about to write, iclass 30, count 0 2006.257.06:43:47.57#ibcon#wrote, iclass 30, count 0 2006.257.06:43:47.57#ibcon#about to read 3, iclass 30, count 0 2006.257.06:43:47.61#ibcon#read 3, iclass 30, count 0 2006.257.06:43:47.61#ibcon#about to read 4, iclass 30, count 0 2006.257.06:43:47.61#ibcon#read 4, iclass 30, count 0 2006.257.06:43:47.61#ibcon#about to read 5, iclass 30, count 0 2006.257.06:43:47.61#ibcon#read 5, iclass 30, count 0 2006.257.06:43:47.61#ibcon#about to read 6, iclass 30, count 0 2006.257.06:43:47.61#ibcon#read 6, iclass 30, count 0 2006.257.06:43:47.61#ibcon#end of sib2, iclass 30, count 0 2006.257.06:43:47.61#ibcon#*after write, iclass 30, count 0 2006.257.06:43:47.61#ibcon#*before return 0, iclass 30, count 0 2006.257.06:43:47.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:47.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:43:47.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:43:47.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:43:47.61$vck44/vb=3,4 2006.257.06:43:47.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.06:43:47.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.06:43:47.61#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:47.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:47.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:47.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:47.67#ibcon#enter wrdev, iclass 32, count 2 2006.257.06:43:47.67#ibcon#first serial, iclass 32, count 2 2006.257.06:43:47.67#ibcon#enter sib2, iclass 32, count 2 2006.257.06:43:47.67#ibcon#flushed, iclass 32, count 2 2006.257.06:43:47.67#ibcon#about to write, iclass 32, count 2 2006.257.06:43:47.67#ibcon#wrote, iclass 32, count 2 2006.257.06:43:47.67#ibcon#about to read 3, iclass 32, count 2 2006.257.06:43:47.69#ibcon#read 3, iclass 32, count 2 2006.257.06:43:47.69#ibcon#about to read 4, iclass 32, count 2 2006.257.06:43:47.69#ibcon#read 4, iclass 32, count 2 2006.257.06:43:47.69#ibcon#about to read 5, iclass 32, count 2 2006.257.06:43:47.69#ibcon#read 5, iclass 32, count 2 2006.257.06:43:47.69#ibcon#about to read 6, iclass 32, count 2 2006.257.06:43:47.69#ibcon#read 6, iclass 32, count 2 2006.257.06:43:47.69#ibcon#end of sib2, iclass 32, count 2 2006.257.06:43:47.69#ibcon#*mode == 0, iclass 32, count 2 2006.257.06:43:47.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.06:43:47.69#ibcon#[27=AT03-04\r\n] 2006.257.06:43:47.69#ibcon#*before write, iclass 32, count 2 2006.257.06:43:47.69#ibcon#enter sib2, iclass 32, count 2 2006.257.06:43:47.69#ibcon#flushed, iclass 32, count 2 2006.257.06:43:47.69#ibcon#about to write, iclass 32, count 2 2006.257.06:43:47.69#ibcon#wrote, iclass 32, count 2 2006.257.06:43:47.69#ibcon#about to read 3, iclass 32, count 2 2006.257.06:43:47.72#ibcon#read 3, iclass 32, count 2 2006.257.06:43:47.72#ibcon#about to read 4, iclass 32, count 2 2006.257.06:43:47.72#ibcon#read 4, iclass 32, count 2 2006.257.06:43:47.72#ibcon#about to read 5, iclass 32, count 2 2006.257.06:43:47.72#ibcon#read 5, iclass 32, count 2 2006.257.06:43:47.72#ibcon#about to read 6, iclass 32, count 2 2006.257.06:43:47.72#ibcon#read 6, iclass 32, count 2 2006.257.06:43:47.72#ibcon#end of sib2, iclass 32, count 2 2006.257.06:43:47.72#ibcon#*after write, iclass 32, count 2 2006.257.06:43:47.72#ibcon#*before return 0, iclass 32, count 2 2006.257.06:43:47.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:47.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:43:47.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.06:43:47.72#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:47.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:47.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:47.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:47.84#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:43:47.84#ibcon#first serial, iclass 32, count 0 2006.257.06:43:47.84#ibcon#enter sib2, iclass 32, count 0 2006.257.06:43:47.84#ibcon#flushed, iclass 32, count 0 2006.257.06:43:47.84#ibcon#about to write, iclass 32, count 0 2006.257.06:43:47.84#ibcon#wrote, iclass 32, count 0 2006.257.06:43:47.84#ibcon#about to read 3, iclass 32, count 0 2006.257.06:43:47.86#ibcon#read 3, iclass 32, count 0 2006.257.06:43:47.86#ibcon#about to read 4, iclass 32, count 0 2006.257.06:43:47.86#ibcon#read 4, iclass 32, count 0 2006.257.06:43:47.86#ibcon#about to read 5, iclass 32, count 0 2006.257.06:43:47.86#ibcon#read 5, iclass 32, count 0 2006.257.06:43:47.86#ibcon#about to read 6, iclass 32, count 0 2006.257.06:43:47.86#ibcon#read 6, iclass 32, count 0 2006.257.06:43:47.86#ibcon#end of sib2, iclass 32, count 0 2006.257.06:43:47.86#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:43:47.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:43:47.86#ibcon#[27=USB\r\n] 2006.257.06:43:47.86#ibcon#*before write, iclass 32, count 0 2006.257.06:43:47.86#ibcon#enter sib2, iclass 32, count 0 2006.257.06:43:47.86#ibcon#flushed, iclass 32, count 0 2006.257.06:43:47.86#ibcon#about to write, iclass 32, count 0 2006.257.06:43:47.86#ibcon#wrote, iclass 32, count 0 2006.257.06:43:47.86#ibcon#about to read 3, iclass 32, count 0 2006.257.06:43:47.89#ibcon#read 3, iclass 32, count 0 2006.257.06:43:47.89#ibcon#about to read 4, iclass 32, count 0 2006.257.06:43:47.89#ibcon#read 4, iclass 32, count 0 2006.257.06:43:47.89#ibcon#about to read 5, iclass 32, count 0 2006.257.06:43:47.89#ibcon#read 5, iclass 32, count 0 2006.257.06:43:47.89#ibcon#about to read 6, iclass 32, count 0 2006.257.06:43:47.89#ibcon#read 6, iclass 32, count 0 2006.257.06:43:47.89#ibcon#end of sib2, iclass 32, count 0 2006.257.06:43:47.89#ibcon#*after write, iclass 32, count 0 2006.257.06:43:47.89#ibcon#*before return 0, iclass 32, count 0 2006.257.06:43:47.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:47.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:43:47.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:43:47.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:43:47.89$vck44/vblo=4,679.99 2006.257.06:43:47.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.06:43:47.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.06:43:47.89#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:47.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:47.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:47.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:47.89#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:43:47.89#ibcon#first serial, iclass 34, count 0 2006.257.06:43:47.89#ibcon#enter sib2, iclass 34, count 0 2006.257.06:43:47.89#ibcon#flushed, iclass 34, count 0 2006.257.06:43:47.89#ibcon#about to write, iclass 34, count 0 2006.257.06:43:47.89#ibcon#wrote, iclass 34, count 0 2006.257.06:43:47.89#ibcon#about to read 3, iclass 34, count 0 2006.257.06:43:47.91#ibcon#read 3, iclass 34, count 0 2006.257.06:43:47.91#ibcon#about to read 4, iclass 34, count 0 2006.257.06:43:47.91#ibcon#read 4, iclass 34, count 0 2006.257.06:43:47.91#ibcon#about to read 5, iclass 34, count 0 2006.257.06:43:47.91#ibcon#read 5, iclass 34, count 0 2006.257.06:43:47.91#ibcon#about to read 6, iclass 34, count 0 2006.257.06:43:47.91#ibcon#read 6, iclass 34, count 0 2006.257.06:43:47.91#ibcon#end of sib2, iclass 34, count 0 2006.257.06:43:47.91#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:43:47.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:43:47.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:43:47.91#ibcon#*before write, iclass 34, count 0 2006.257.06:43:47.91#ibcon#enter sib2, iclass 34, count 0 2006.257.06:43:47.91#ibcon#flushed, iclass 34, count 0 2006.257.06:43:47.91#ibcon#about to write, iclass 34, count 0 2006.257.06:43:47.91#ibcon#wrote, iclass 34, count 0 2006.257.06:43:47.91#ibcon#about to read 3, iclass 34, count 0 2006.257.06:43:47.95#ibcon#read 3, iclass 34, count 0 2006.257.06:43:47.95#ibcon#about to read 4, iclass 34, count 0 2006.257.06:43:47.95#ibcon#read 4, iclass 34, count 0 2006.257.06:43:47.95#ibcon#about to read 5, iclass 34, count 0 2006.257.06:43:47.95#ibcon#read 5, iclass 34, count 0 2006.257.06:43:47.95#ibcon#about to read 6, iclass 34, count 0 2006.257.06:43:47.95#ibcon#read 6, iclass 34, count 0 2006.257.06:43:47.95#ibcon#end of sib2, iclass 34, count 0 2006.257.06:43:47.95#ibcon#*after write, iclass 34, count 0 2006.257.06:43:47.95#ibcon#*before return 0, iclass 34, count 0 2006.257.06:43:47.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:47.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:43:47.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:43:47.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:43:47.95$vck44/vb=4,5 2006.257.06:43:47.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.06:43:47.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.06:43:47.95#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:47.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:48.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:48.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:48.01#ibcon#enter wrdev, iclass 36, count 2 2006.257.06:43:48.01#ibcon#first serial, iclass 36, count 2 2006.257.06:43:48.01#ibcon#enter sib2, iclass 36, count 2 2006.257.06:43:48.01#ibcon#flushed, iclass 36, count 2 2006.257.06:43:48.01#ibcon#about to write, iclass 36, count 2 2006.257.06:43:48.01#ibcon#wrote, iclass 36, count 2 2006.257.06:43:48.01#ibcon#about to read 3, iclass 36, count 2 2006.257.06:43:48.03#ibcon#read 3, iclass 36, count 2 2006.257.06:43:48.03#ibcon#about to read 4, iclass 36, count 2 2006.257.06:43:48.03#ibcon#read 4, iclass 36, count 2 2006.257.06:43:48.03#ibcon#about to read 5, iclass 36, count 2 2006.257.06:43:48.03#ibcon#read 5, iclass 36, count 2 2006.257.06:43:48.03#ibcon#about to read 6, iclass 36, count 2 2006.257.06:43:48.03#ibcon#read 6, iclass 36, count 2 2006.257.06:43:48.03#ibcon#end of sib2, iclass 36, count 2 2006.257.06:43:48.03#ibcon#*mode == 0, iclass 36, count 2 2006.257.06:43:48.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.06:43:48.03#ibcon#[27=AT04-05\r\n] 2006.257.06:43:48.03#ibcon#*before write, iclass 36, count 2 2006.257.06:43:48.03#ibcon#enter sib2, iclass 36, count 2 2006.257.06:43:48.03#ibcon#flushed, iclass 36, count 2 2006.257.06:43:48.03#ibcon#about to write, iclass 36, count 2 2006.257.06:43:48.03#ibcon#wrote, iclass 36, count 2 2006.257.06:43:48.03#ibcon#about to read 3, iclass 36, count 2 2006.257.06:43:48.06#ibcon#read 3, iclass 36, count 2 2006.257.06:43:48.06#ibcon#about to read 4, iclass 36, count 2 2006.257.06:43:48.06#ibcon#read 4, iclass 36, count 2 2006.257.06:43:48.06#ibcon#about to read 5, iclass 36, count 2 2006.257.06:43:48.06#ibcon#read 5, iclass 36, count 2 2006.257.06:43:48.06#ibcon#about to read 6, iclass 36, count 2 2006.257.06:43:48.06#ibcon#read 6, iclass 36, count 2 2006.257.06:43:48.06#ibcon#end of sib2, iclass 36, count 2 2006.257.06:43:48.06#ibcon#*after write, iclass 36, count 2 2006.257.06:43:48.06#ibcon#*before return 0, iclass 36, count 2 2006.257.06:43:48.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:48.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:43:48.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.06:43:48.06#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:48.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:48.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:48.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:48.18#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:43:48.18#ibcon#first serial, iclass 36, count 0 2006.257.06:43:48.18#ibcon#enter sib2, iclass 36, count 0 2006.257.06:43:48.18#ibcon#flushed, iclass 36, count 0 2006.257.06:43:48.18#ibcon#about to write, iclass 36, count 0 2006.257.06:43:48.18#ibcon#wrote, iclass 36, count 0 2006.257.06:43:48.18#ibcon#about to read 3, iclass 36, count 0 2006.257.06:43:48.20#ibcon#read 3, iclass 36, count 0 2006.257.06:43:48.20#ibcon#about to read 4, iclass 36, count 0 2006.257.06:43:48.20#ibcon#read 4, iclass 36, count 0 2006.257.06:43:48.20#ibcon#about to read 5, iclass 36, count 0 2006.257.06:43:48.20#ibcon#read 5, iclass 36, count 0 2006.257.06:43:48.20#ibcon#about to read 6, iclass 36, count 0 2006.257.06:43:48.20#ibcon#read 6, iclass 36, count 0 2006.257.06:43:48.20#ibcon#end of sib2, iclass 36, count 0 2006.257.06:43:48.20#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:43:48.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:43:48.20#ibcon#[27=USB\r\n] 2006.257.06:43:48.20#ibcon#*before write, iclass 36, count 0 2006.257.06:43:48.20#ibcon#enter sib2, iclass 36, count 0 2006.257.06:43:48.20#ibcon#flushed, iclass 36, count 0 2006.257.06:43:48.20#ibcon#about to write, iclass 36, count 0 2006.257.06:43:48.20#ibcon#wrote, iclass 36, count 0 2006.257.06:43:48.20#ibcon#about to read 3, iclass 36, count 0 2006.257.06:43:48.23#ibcon#read 3, iclass 36, count 0 2006.257.06:43:48.23#ibcon#about to read 4, iclass 36, count 0 2006.257.06:43:48.23#ibcon#read 4, iclass 36, count 0 2006.257.06:43:48.23#ibcon#about to read 5, iclass 36, count 0 2006.257.06:43:48.23#ibcon#read 5, iclass 36, count 0 2006.257.06:43:48.23#ibcon#about to read 6, iclass 36, count 0 2006.257.06:43:48.23#ibcon#read 6, iclass 36, count 0 2006.257.06:43:48.23#ibcon#end of sib2, iclass 36, count 0 2006.257.06:43:48.23#ibcon#*after write, iclass 36, count 0 2006.257.06:43:48.23#ibcon#*before return 0, iclass 36, count 0 2006.257.06:43:48.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:48.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:43:48.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:43:48.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:43:48.23$vck44/vblo=5,709.99 2006.257.06:43:48.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.06:43:48.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.06:43:48.23#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:48.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:48.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:48.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:48.23#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:43:48.23#ibcon#first serial, iclass 38, count 0 2006.257.06:43:48.23#ibcon#enter sib2, iclass 38, count 0 2006.257.06:43:48.23#ibcon#flushed, iclass 38, count 0 2006.257.06:43:48.23#ibcon#about to write, iclass 38, count 0 2006.257.06:43:48.23#ibcon#wrote, iclass 38, count 0 2006.257.06:43:48.23#ibcon#about to read 3, iclass 38, count 0 2006.257.06:43:48.25#ibcon#read 3, iclass 38, count 0 2006.257.06:43:48.25#ibcon#about to read 4, iclass 38, count 0 2006.257.06:43:48.25#ibcon#read 4, iclass 38, count 0 2006.257.06:43:48.25#ibcon#about to read 5, iclass 38, count 0 2006.257.06:43:48.25#ibcon#read 5, iclass 38, count 0 2006.257.06:43:48.25#ibcon#about to read 6, iclass 38, count 0 2006.257.06:43:48.25#ibcon#read 6, iclass 38, count 0 2006.257.06:43:48.25#ibcon#end of sib2, iclass 38, count 0 2006.257.06:43:48.25#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:43:48.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:43:48.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:43:48.25#ibcon#*before write, iclass 38, count 0 2006.257.06:43:48.25#ibcon#enter sib2, iclass 38, count 0 2006.257.06:43:48.25#ibcon#flushed, iclass 38, count 0 2006.257.06:43:48.25#ibcon#about to write, iclass 38, count 0 2006.257.06:43:48.25#ibcon#wrote, iclass 38, count 0 2006.257.06:43:48.25#ibcon#about to read 3, iclass 38, count 0 2006.257.06:43:48.29#ibcon#read 3, iclass 38, count 0 2006.257.06:43:48.29#ibcon#about to read 4, iclass 38, count 0 2006.257.06:43:48.29#ibcon#read 4, iclass 38, count 0 2006.257.06:43:48.29#ibcon#about to read 5, iclass 38, count 0 2006.257.06:43:48.29#ibcon#read 5, iclass 38, count 0 2006.257.06:43:48.29#ibcon#about to read 6, iclass 38, count 0 2006.257.06:43:48.29#ibcon#read 6, iclass 38, count 0 2006.257.06:43:48.29#ibcon#end of sib2, iclass 38, count 0 2006.257.06:43:48.29#ibcon#*after write, iclass 38, count 0 2006.257.06:43:48.29#ibcon#*before return 0, iclass 38, count 0 2006.257.06:43:48.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:48.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:43:48.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:43:48.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:43:48.29$vck44/vb=5,4 2006.257.06:43:48.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.06:43:48.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.06:43:48.29#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:48.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:48.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:48.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:48.35#ibcon#enter wrdev, iclass 40, count 2 2006.257.06:43:48.35#ibcon#first serial, iclass 40, count 2 2006.257.06:43:48.35#ibcon#enter sib2, iclass 40, count 2 2006.257.06:43:48.35#ibcon#flushed, iclass 40, count 2 2006.257.06:43:48.35#ibcon#about to write, iclass 40, count 2 2006.257.06:43:48.35#ibcon#wrote, iclass 40, count 2 2006.257.06:43:48.35#ibcon#about to read 3, iclass 40, count 2 2006.257.06:43:48.37#ibcon#read 3, iclass 40, count 2 2006.257.06:43:48.37#ibcon#about to read 4, iclass 40, count 2 2006.257.06:43:48.37#ibcon#read 4, iclass 40, count 2 2006.257.06:43:48.37#ibcon#about to read 5, iclass 40, count 2 2006.257.06:43:48.37#ibcon#read 5, iclass 40, count 2 2006.257.06:43:48.37#ibcon#about to read 6, iclass 40, count 2 2006.257.06:43:48.37#ibcon#read 6, iclass 40, count 2 2006.257.06:43:48.37#ibcon#end of sib2, iclass 40, count 2 2006.257.06:43:48.37#ibcon#*mode == 0, iclass 40, count 2 2006.257.06:43:48.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.06:43:48.37#ibcon#[27=AT05-04\r\n] 2006.257.06:43:48.37#ibcon#*before write, iclass 40, count 2 2006.257.06:43:48.37#ibcon#enter sib2, iclass 40, count 2 2006.257.06:43:48.37#ibcon#flushed, iclass 40, count 2 2006.257.06:43:48.37#ibcon#about to write, iclass 40, count 2 2006.257.06:43:48.37#ibcon#wrote, iclass 40, count 2 2006.257.06:43:48.37#ibcon#about to read 3, iclass 40, count 2 2006.257.06:43:48.40#ibcon#read 3, iclass 40, count 2 2006.257.06:43:48.40#ibcon#about to read 4, iclass 40, count 2 2006.257.06:43:48.40#ibcon#read 4, iclass 40, count 2 2006.257.06:43:48.40#ibcon#about to read 5, iclass 40, count 2 2006.257.06:43:48.40#ibcon#read 5, iclass 40, count 2 2006.257.06:43:48.40#ibcon#about to read 6, iclass 40, count 2 2006.257.06:43:48.40#ibcon#read 6, iclass 40, count 2 2006.257.06:43:48.40#ibcon#end of sib2, iclass 40, count 2 2006.257.06:43:48.40#ibcon#*after write, iclass 40, count 2 2006.257.06:43:48.40#ibcon#*before return 0, iclass 40, count 2 2006.257.06:43:48.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:48.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:43:48.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.06:43:48.40#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:48.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:48.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:48.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:48.52#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:43:48.52#ibcon#first serial, iclass 40, count 0 2006.257.06:43:48.52#ibcon#enter sib2, iclass 40, count 0 2006.257.06:43:48.52#ibcon#flushed, iclass 40, count 0 2006.257.06:43:48.52#ibcon#about to write, iclass 40, count 0 2006.257.06:43:48.52#ibcon#wrote, iclass 40, count 0 2006.257.06:43:48.52#ibcon#about to read 3, iclass 40, count 0 2006.257.06:43:48.54#ibcon#read 3, iclass 40, count 0 2006.257.06:43:48.54#ibcon#about to read 4, iclass 40, count 0 2006.257.06:43:48.54#ibcon#read 4, iclass 40, count 0 2006.257.06:43:48.54#ibcon#about to read 5, iclass 40, count 0 2006.257.06:43:48.54#ibcon#read 5, iclass 40, count 0 2006.257.06:43:48.54#ibcon#about to read 6, iclass 40, count 0 2006.257.06:43:48.54#ibcon#read 6, iclass 40, count 0 2006.257.06:43:48.54#ibcon#end of sib2, iclass 40, count 0 2006.257.06:43:48.54#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:43:48.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:43:48.54#ibcon#[27=USB\r\n] 2006.257.06:43:48.54#ibcon#*before write, iclass 40, count 0 2006.257.06:43:48.54#ibcon#enter sib2, iclass 40, count 0 2006.257.06:43:48.54#ibcon#flushed, iclass 40, count 0 2006.257.06:43:48.54#ibcon#about to write, iclass 40, count 0 2006.257.06:43:48.54#ibcon#wrote, iclass 40, count 0 2006.257.06:43:48.54#ibcon#about to read 3, iclass 40, count 0 2006.257.06:43:48.57#ibcon#read 3, iclass 40, count 0 2006.257.06:43:48.57#ibcon#about to read 4, iclass 40, count 0 2006.257.06:43:48.57#ibcon#read 4, iclass 40, count 0 2006.257.06:43:48.57#ibcon#about to read 5, iclass 40, count 0 2006.257.06:43:48.57#ibcon#read 5, iclass 40, count 0 2006.257.06:43:48.57#ibcon#about to read 6, iclass 40, count 0 2006.257.06:43:48.57#ibcon#read 6, iclass 40, count 0 2006.257.06:43:48.57#ibcon#end of sib2, iclass 40, count 0 2006.257.06:43:48.57#ibcon#*after write, iclass 40, count 0 2006.257.06:43:48.57#ibcon#*before return 0, iclass 40, count 0 2006.257.06:43:48.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:48.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:43:48.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:43:48.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:43:48.57$vck44/vblo=6,719.99 2006.257.06:43:48.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.06:43:48.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.06:43:48.57#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:48.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:48.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:48.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:48.57#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:43:48.57#ibcon#first serial, iclass 4, count 0 2006.257.06:43:48.57#ibcon#enter sib2, iclass 4, count 0 2006.257.06:43:48.57#ibcon#flushed, iclass 4, count 0 2006.257.06:43:48.57#ibcon#about to write, iclass 4, count 0 2006.257.06:43:48.57#ibcon#wrote, iclass 4, count 0 2006.257.06:43:48.57#ibcon#about to read 3, iclass 4, count 0 2006.257.06:43:48.59#ibcon#read 3, iclass 4, count 0 2006.257.06:43:48.59#ibcon#about to read 4, iclass 4, count 0 2006.257.06:43:48.59#ibcon#read 4, iclass 4, count 0 2006.257.06:43:48.59#ibcon#about to read 5, iclass 4, count 0 2006.257.06:43:48.59#ibcon#read 5, iclass 4, count 0 2006.257.06:43:48.59#ibcon#about to read 6, iclass 4, count 0 2006.257.06:43:48.59#ibcon#read 6, iclass 4, count 0 2006.257.06:43:48.59#ibcon#end of sib2, iclass 4, count 0 2006.257.06:43:48.59#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:43:48.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:43:48.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:43:48.59#ibcon#*before write, iclass 4, count 0 2006.257.06:43:48.59#ibcon#enter sib2, iclass 4, count 0 2006.257.06:43:48.59#ibcon#flushed, iclass 4, count 0 2006.257.06:43:48.59#ibcon#about to write, iclass 4, count 0 2006.257.06:43:48.59#ibcon#wrote, iclass 4, count 0 2006.257.06:43:48.59#ibcon#about to read 3, iclass 4, count 0 2006.257.06:43:48.63#ibcon#read 3, iclass 4, count 0 2006.257.06:43:48.63#ibcon#about to read 4, iclass 4, count 0 2006.257.06:43:48.63#ibcon#read 4, iclass 4, count 0 2006.257.06:43:48.63#ibcon#about to read 5, iclass 4, count 0 2006.257.06:43:48.63#ibcon#read 5, iclass 4, count 0 2006.257.06:43:48.63#ibcon#about to read 6, iclass 4, count 0 2006.257.06:43:48.63#ibcon#read 6, iclass 4, count 0 2006.257.06:43:48.63#ibcon#end of sib2, iclass 4, count 0 2006.257.06:43:48.63#ibcon#*after write, iclass 4, count 0 2006.257.06:43:48.63#ibcon#*before return 0, iclass 4, count 0 2006.257.06:43:48.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:48.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:43:48.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:43:48.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:43:48.63$vck44/vb=6,4 2006.257.06:43:48.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.06:43:48.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.06:43:48.63#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:48.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:48.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:48.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:48.69#ibcon#enter wrdev, iclass 6, count 2 2006.257.06:43:48.69#ibcon#first serial, iclass 6, count 2 2006.257.06:43:48.69#ibcon#enter sib2, iclass 6, count 2 2006.257.06:43:48.69#ibcon#flushed, iclass 6, count 2 2006.257.06:43:48.69#ibcon#about to write, iclass 6, count 2 2006.257.06:43:48.69#ibcon#wrote, iclass 6, count 2 2006.257.06:43:48.69#ibcon#about to read 3, iclass 6, count 2 2006.257.06:43:48.71#ibcon#read 3, iclass 6, count 2 2006.257.06:43:48.71#ibcon#about to read 4, iclass 6, count 2 2006.257.06:43:48.71#ibcon#read 4, iclass 6, count 2 2006.257.06:43:48.71#ibcon#about to read 5, iclass 6, count 2 2006.257.06:43:48.71#ibcon#read 5, iclass 6, count 2 2006.257.06:43:48.71#ibcon#about to read 6, iclass 6, count 2 2006.257.06:43:48.71#ibcon#read 6, iclass 6, count 2 2006.257.06:43:48.71#ibcon#end of sib2, iclass 6, count 2 2006.257.06:43:48.71#ibcon#*mode == 0, iclass 6, count 2 2006.257.06:43:48.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.06:43:48.71#ibcon#[27=AT06-04\r\n] 2006.257.06:43:48.71#ibcon#*before write, iclass 6, count 2 2006.257.06:43:48.71#ibcon#enter sib2, iclass 6, count 2 2006.257.06:43:48.71#ibcon#flushed, iclass 6, count 2 2006.257.06:43:48.71#ibcon#about to write, iclass 6, count 2 2006.257.06:43:48.71#ibcon#wrote, iclass 6, count 2 2006.257.06:43:48.71#ibcon#about to read 3, iclass 6, count 2 2006.257.06:43:48.74#ibcon#read 3, iclass 6, count 2 2006.257.06:43:48.74#ibcon#about to read 4, iclass 6, count 2 2006.257.06:43:48.74#ibcon#read 4, iclass 6, count 2 2006.257.06:43:48.74#ibcon#about to read 5, iclass 6, count 2 2006.257.06:43:48.74#ibcon#read 5, iclass 6, count 2 2006.257.06:43:48.74#ibcon#about to read 6, iclass 6, count 2 2006.257.06:43:48.74#ibcon#read 6, iclass 6, count 2 2006.257.06:43:48.74#ibcon#end of sib2, iclass 6, count 2 2006.257.06:43:48.74#ibcon#*after write, iclass 6, count 2 2006.257.06:43:48.74#ibcon#*before return 0, iclass 6, count 2 2006.257.06:43:48.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:48.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:43:48.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.06:43:48.74#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:48.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:48.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:48.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:48.86#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:43:48.86#ibcon#first serial, iclass 6, count 0 2006.257.06:43:48.86#ibcon#enter sib2, iclass 6, count 0 2006.257.06:43:48.86#ibcon#flushed, iclass 6, count 0 2006.257.06:43:48.86#ibcon#about to write, iclass 6, count 0 2006.257.06:43:48.86#ibcon#wrote, iclass 6, count 0 2006.257.06:43:48.86#ibcon#about to read 3, iclass 6, count 0 2006.257.06:43:48.88#ibcon#read 3, iclass 6, count 0 2006.257.06:43:48.88#ibcon#about to read 4, iclass 6, count 0 2006.257.06:43:48.88#ibcon#read 4, iclass 6, count 0 2006.257.06:43:48.88#ibcon#about to read 5, iclass 6, count 0 2006.257.06:43:48.88#ibcon#read 5, iclass 6, count 0 2006.257.06:43:48.88#ibcon#about to read 6, iclass 6, count 0 2006.257.06:43:48.88#ibcon#read 6, iclass 6, count 0 2006.257.06:43:48.88#ibcon#end of sib2, iclass 6, count 0 2006.257.06:43:48.88#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:43:48.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:43:48.88#ibcon#[27=USB\r\n] 2006.257.06:43:48.88#ibcon#*before write, iclass 6, count 0 2006.257.06:43:48.88#ibcon#enter sib2, iclass 6, count 0 2006.257.06:43:48.88#ibcon#flushed, iclass 6, count 0 2006.257.06:43:48.88#ibcon#about to write, iclass 6, count 0 2006.257.06:43:48.88#ibcon#wrote, iclass 6, count 0 2006.257.06:43:48.88#ibcon#about to read 3, iclass 6, count 0 2006.257.06:43:48.91#ibcon#read 3, iclass 6, count 0 2006.257.06:43:48.91#ibcon#about to read 4, iclass 6, count 0 2006.257.06:43:48.91#ibcon#read 4, iclass 6, count 0 2006.257.06:43:48.91#ibcon#about to read 5, iclass 6, count 0 2006.257.06:43:48.91#ibcon#read 5, iclass 6, count 0 2006.257.06:43:48.91#ibcon#about to read 6, iclass 6, count 0 2006.257.06:43:48.91#ibcon#read 6, iclass 6, count 0 2006.257.06:43:48.91#ibcon#end of sib2, iclass 6, count 0 2006.257.06:43:48.91#ibcon#*after write, iclass 6, count 0 2006.257.06:43:48.91#ibcon#*before return 0, iclass 6, count 0 2006.257.06:43:48.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:48.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:43:48.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:43:48.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:43:48.91$vck44/vblo=7,734.99 2006.257.06:43:48.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.06:43:48.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.06:43:48.91#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:48.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:48.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:48.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:48.91#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:43:48.91#ibcon#first serial, iclass 10, count 0 2006.257.06:43:48.91#ibcon#enter sib2, iclass 10, count 0 2006.257.06:43:48.91#ibcon#flushed, iclass 10, count 0 2006.257.06:43:48.91#ibcon#about to write, iclass 10, count 0 2006.257.06:43:48.91#ibcon#wrote, iclass 10, count 0 2006.257.06:43:48.91#ibcon#about to read 3, iclass 10, count 0 2006.257.06:43:48.93#ibcon#read 3, iclass 10, count 0 2006.257.06:43:48.93#ibcon#about to read 4, iclass 10, count 0 2006.257.06:43:48.93#ibcon#read 4, iclass 10, count 0 2006.257.06:43:48.93#ibcon#about to read 5, iclass 10, count 0 2006.257.06:43:48.93#ibcon#read 5, iclass 10, count 0 2006.257.06:43:48.93#ibcon#about to read 6, iclass 10, count 0 2006.257.06:43:48.93#ibcon#read 6, iclass 10, count 0 2006.257.06:43:48.93#ibcon#end of sib2, iclass 10, count 0 2006.257.06:43:48.93#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:43:48.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:43:48.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:43:48.93#ibcon#*before write, iclass 10, count 0 2006.257.06:43:48.93#ibcon#enter sib2, iclass 10, count 0 2006.257.06:43:48.93#ibcon#flushed, iclass 10, count 0 2006.257.06:43:48.93#ibcon#about to write, iclass 10, count 0 2006.257.06:43:48.93#ibcon#wrote, iclass 10, count 0 2006.257.06:43:48.93#ibcon#about to read 3, iclass 10, count 0 2006.257.06:43:48.97#ibcon#read 3, iclass 10, count 0 2006.257.06:43:48.97#ibcon#about to read 4, iclass 10, count 0 2006.257.06:43:48.97#ibcon#read 4, iclass 10, count 0 2006.257.06:43:48.97#ibcon#about to read 5, iclass 10, count 0 2006.257.06:43:48.97#ibcon#read 5, iclass 10, count 0 2006.257.06:43:48.97#ibcon#about to read 6, iclass 10, count 0 2006.257.06:43:48.97#ibcon#read 6, iclass 10, count 0 2006.257.06:43:48.97#ibcon#end of sib2, iclass 10, count 0 2006.257.06:43:48.97#ibcon#*after write, iclass 10, count 0 2006.257.06:43:48.97#ibcon#*before return 0, iclass 10, count 0 2006.257.06:43:48.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:48.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:43:48.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:43:48.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:43:48.97$vck44/vb=7,4 2006.257.06:43:48.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.06:43:48.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.06:43:48.97#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:48.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:49.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:49.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:49.03#ibcon#enter wrdev, iclass 12, count 2 2006.257.06:43:49.03#ibcon#first serial, iclass 12, count 2 2006.257.06:43:49.03#ibcon#enter sib2, iclass 12, count 2 2006.257.06:43:49.03#ibcon#flushed, iclass 12, count 2 2006.257.06:43:49.03#ibcon#about to write, iclass 12, count 2 2006.257.06:43:49.03#ibcon#wrote, iclass 12, count 2 2006.257.06:43:49.03#ibcon#about to read 3, iclass 12, count 2 2006.257.06:43:49.05#ibcon#read 3, iclass 12, count 2 2006.257.06:43:49.05#ibcon#about to read 4, iclass 12, count 2 2006.257.06:43:49.05#ibcon#read 4, iclass 12, count 2 2006.257.06:43:49.05#ibcon#about to read 5, iclass 12, count 2 2006.257.06:43:49.05#ibcon#read 5, iclass 12, count 2 2006.257.06:43:49.05#ibcon#about to read 6, iclass 12, count 2 2006.257.06:43:49.05#ibcon#read 6, iclass 12, count 2 2006.257.06:43:49.05#ibcon#end of sib2, iclass 12, count 2 2006.257.06:43:49.05#ibcon#*mode == 0, iclass 12, count 2 2006.257.06:43:49.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.06:43:49.05#ibcon#[27=AT07-04\r\n] 2006.257.06:43:49.05#ibcon#*before write, iclass 12, count 2 2006.257.06:43:49.05#ibcon#enter sib2, iclass 12, count 2 2006.257.06:43:49.05#ibcon#flushed, iclass 12, count 2 2006.257.06:43:49.05#ibcon#about to write, iclass 12, count 2 2006.257.06:43:49.05#ibcon#wrote, iclass 12, count 2 2006.257.06:43:49.05#ibcon#about to read 3, iclass 12, count 2 2006.257.06:43:49.08#ibcon#read 3, iclass 12, count 2 2006.257.06:43:49.08#ibcon#about to read 4, iclass 12, count 2 2006.257.06:43:49.08#ibcon#read 4, iclass 12, count 2 2006.257.06:43:49.08#ibcon#about to read 5, iclass 12, count 2 2006.257.06:43:49.08#ibcon#read 5, iclass 12, count 2 2006.257.06:43:49.08#ibcon#about to read 6, iclass 12, count 2 2006.257.06:43:49.08#ibcon#read 6, iclass 12, count 2 2006.257.06:43:49.08#ibcon#end of sib2, iclass 12, count 2 2006.257.06:43:49.08#ibcon#*after write, iclass 12, count 2 2006.257.06:43:49.08#ibcon#*before return 0, iclass 12, count 2 2006.257.06:43:49.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:49.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:43:49.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.06:43:49.08#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:49.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:49.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:49.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:49.20#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:43:49.20#ibcon#first serial, iclass 12, count 0 2006.257.06:43:49.20#ibcon#enter sib2, iclass 12, count 0 2006.257.06:43:49.20#ibcon#flushed, iclass 12, count 0 2006.257.06:43:49.20#ibcon#about to write, iclass 12, count 0 2006.257.06:43:49.20#ibcon#wrote, iclass 12, count 0 2006.257.06:43:49.20#ibcon#about to read 3, iclass 12, count 0 2006.257.06:43:49.22#ibcon#read 3, iclass 12, count 0 2006.257.06:43:49.22#ibcon#about to read 4, iclass 12, count 0 2006.257.06:43:49.22#ibcon#read 4, iclass 12, count 0 2006.257.06:43:49.22#ibcon#about to read 5, iclass 12, count 0 2006.257.06:43:49.22#ibcon#read 5, iclass 12, count 0 2006.257.06:43:49.22#ibcon#about to read 6, iclass 12, count 0 2006.257.06:43:49.22#ibcon#read 6, iclass 12, count 0 2006.257.06:43:49.22#ibcon#end of sib2, iclass 12, count 0 2006.257.06:43:49.22#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:43:49.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:43:49.22#ibcon#[27=USB\r\n] 2006.257.06:43:49.22#ibcon#*before write, iclass 12, count 0 2006.257.06:43:49.22#ibcon#enter sib2, iclass 12, count 0 2006.257.06:43:49.22#ibcon#flushed, iclass 12, count 0 2006.257.06:43:49.22#ibcon#about to write, iclass 12, count 0 2006.257.06:43:49.22#ibcon#wrote, iclass 12, count 0 2006.257.06:43:49.22#ibcon#about to read 3, iclass 12, count 0 2006.257.06:43:49.25#ibcon#read 3, iclass 12, count 0 2006.257.06:43:49.25#ibcon#about to read 4, iclass 12, count 0 2006.257.06:43:49.25#ibcon#read 4, iclass 12, count 0 2006.257.06:43:49.25#ibcon#about to read 5, iclass 12, count 0 2006.257.06:43:49.25#ibcon#read 5, iclass 12, count 0 2006.257.06:43:49.25#ibcon#about to read 6, iclass 12, count 0 2006.257.06:43:49.25#ibcon#read 6, iclass 12, count 0 2006.257.06:43:49.25#ibcon#end of sib2, iclass 12, count 0 2006.257.06:43:49.25#ibcon#*after write, iclass 12, count 0 2006.257.06:43:49.25#ibcon#*before return 0, iclass 12, count 0 2006.257.06:43:49.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:49.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:43:49.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:43:49.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:43:49.25$vck44/vblo=8,744.99 2006.257.06:43:49.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.06:43:49.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.06:43:49.25#ibcon#ireg 17 cls_cnt 0 2006.257.06:43:49.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:43:49.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:43:49.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:43:49.25#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:43:49.25#ibcon#first serial, iclass 14, count 0 2006.257.06:43:49.25#ibcon#enter sib2, iclass 14, count 0 2006.257.06:43:49.25#ibcon#flushed, iclass 14, count 0 2006.257.06:43:49.25#ibcon#about to write, iclass 14, count 0 2006.257.06:43:49.25#ibcon#wrote, iclass 14, count 0 2006.257.06:43:49.25#ibcon#about to read 3, iclass 14, count 0 2006.257.06:43:49.27#ibcon#read 3, iclass 14, count 0 2006.257.06:43:49.27#ibcon#about to read 4, iclass 14, count 0 2006.257.06:43:49.27#ibcon#read 4, iclass 14, count 0 2006.257.06:43:49.27#ibcon#about to read 5, iclass 14, count 0 2006.257.06:43:49.27#ibcon#read 5, iclass 14, count 0 2006.257.06:43:49.27#ibcon#about to read 6, iclass 14, count 0 2006.257.06:43:49.27#ibcon#read 6, iclass 14, count 0 2006.257.06:43:49.27#ibcon#end of sib2, iclass 14, count 0 2006.257.06:43:49.27#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:43:49.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:43:49.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:43:49.27#ibcon#*before write, iclass 14, count 0 2006.257.06:43:49.27#ibcon#enter sib2, iclass 14, count 0 2006.257.06:43:49.27#ibcon#flushed, iclass 14, count 0 2006.257.06:43:49.27#ibcon#about to write, iclass 14, count 0 2006.257.06:43:49.27#ibcon#wrote, iclass 14, count 0 2006.257.06:43:49.27#ibcon#about to read 3, iclass 14, count 0 2006.257.06:43:49.31#ibcon#read 3, iclass 14, count 0 2006.257.06:43:49.31#ibcon#about to read 4, iclass 14, count 0 2006.257.06:43:49.31#ibcon#read 4, iclass 14, count 0 2006.257.06:43:49.31#ibcon#about to read 5, iclass 14, count 0 2006.257.06:43:49.31#ibcon#read 5, iclass 14, count 0 2006.257.06:43:49.31#ibcon#about to read 6, iclass 14, count 0 2006.257.06:43:49.31#ibcon#read 6, iclass 14, count 0 2006.257.06:43:49.31#ibcon#end of sib2, iclass 14, count 0 2006.257.06:43:49.31#ibcon#*after write, iclass 14, count 0 2006.257.06:43:49.31#ibcon#*before return 0, iclass 14, count 0 2006.257.06:43:49.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:43:49.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:43:49.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:43:49.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:43:49.31$vck44/vb=8,4 2006.257.06:43:49.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.06:43:49.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.06:43:49.31#ibcon#ireg 11 cls_cnt 2 2006.257.06:43:49.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:43:49.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:43:49.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:43:49.37#ibcon#enter wrdev, iclass 16, count 2 2006.257.06:43:49.37#ibcon#first serial, iclass 16, count 2 2006.257.06:43:49.37#ibcon#enter sib2, iclass 16, count 2 2006.257.06:43:49.37#ibcon#flushed, iclass 16, count 2 2006.257.06:43:49.37#ibcon#about to write, iclass 16, count 2 2006.257.06:43:49.37#ibcon#wrote, iclass 16, count 2 2006.257.06:43:49.37#ibcon#about to read 3, iclass 16, count 2 2006.257.06:43:49.39#ibcon#read 3, iclass 16, count 2 2006.257.06:43:49.39#ibcon#about to read 4, iclass 16, count 2 2006.257.06:43:49.39#ibcon#read 4, iclass 16, count 2 2006.257.06:43:49.39#ibcon#about to read 5, iclass 16, count 2 2006.257.06:43:49.39#ibcon#read 5, iclass 16, count 2 2006.257.06:43:49.39#ibcon#about to read 6, iclass 16, count 2 2006.257.06:43:49.39#ibcon#read 6, iclass 16, count 2 2006.257.06:43:49.39#ibcon#end of sib2, iclass 16, count 2 2006.257.06:43:49.39#ibcon#*mode == 0, iclass 16, count 2 2006.257.06:43:49.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.06:43:49.39#ibcon#[27=AT08-04\r\n] 2006.257.06:43:49.39#ibcon#*before write, iclass 16, count 2 2006.257.06:43:49.39#ibcon#enter sib2, iclass 16, count 2 2006.257.06:43:49.39#ibcon#flushed, iclass 16, count 2 2006.257.06:43:49.39#ibcon#about to write, iclass 16, count 2 2006.257.06:43:49.39#ibcon#wrote, iclass 16, count 2 2006.257.06:43:49.39#ibcon#about to read 3, iclass 16, count 2 2006.257.06:43:49.42#ibcon#read 3, iclass 16, count 2 2006.257.06:43:49.42#ibcon#about to read 4, iclass 16, count 2 2006.257.06:43:49.42#ibcon#read 4, iclass 16, count 2 2006.257.06:43:49.42#ibcon#about to read 5, iclass 16, count 2 2006.257.06:43:49.42#ibcon#read 5, iclass 16, count 2 2006.257.06:43:49.42#ibcon#about to read 6, iclass 16, count 2 2006.257.06:43:49.42#ibcon#read 6, iclass 16, count 2 2006.257.06:43:49.42#ibcon#end of sib2, iclass 16, count 2 2006.257.06:43:49.42#ibcon#*after write, iclass 16, count 2 2006.257.06:43:49.42#ibcon#*before return 0, iclass 16, count 2 2006.257.06:43:49.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:43:49.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:43:49.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.06:43:49.42#ibcon#ireg 7 cls_cnt 0 2006.257.06:43:49.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:43:49.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:43:49.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:43:49.54#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:43:49.54#ibcon#first serial, iclass 16, count 0 2006.257.06:43:49.54#ibcon#enter sib2, iclass 16, count 0 2006.257.06:43:49.54#ibcon#flushed, iclass 16, count 0 2006.257.06:43:49.54#ibcon#about to write, iclass 16, count 0 2006.257.06:43:49.54#ibcon#wrote, iclass 16, count 0 2006.257.06:43:49.54#ibcon#about to read 3, iclass 16, count 0 2006.257.06:43:49.56#ibcon#read 3, iclass 16, count 0 2006.257.06:43:49.56#ibcon#about to read 4, iclass 16, count 0 2006.257.06:43:49.56#ibcon#read 4, iclass 16, count 0 2006.257.06:43:49.56#ibcon#about to read 5, iclass 16, count 0 2006.257.06:43:49.56#ibcon#read 5, iclass 16, count 0 2006.257.06:43:49.56#ibcon#about to read 6, iclass 16, count 0 2006.257.06:43:49.56#ibcon#read 6, iclass 16, count 0 2006.257.06:43:49.56#ibcon#end of sib2, iclass 16, count 0 2006.257.06:43:49.56#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:43:49.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:43:49.56#ibcon#[27=USB\r\n] 2006.257.06:43:49.56#ibcon#*before write, iclass 16, count 0 2006.257.06:43:49.56#ibcon#enter sib2, iclass 16, count 0 2006.257.06:43:49.56#ibcon#flushed, iclass 16, count 0 2006.257.06:43:49.56#ibcon#about to write, iclass 16, count 0 2006.257.06:43:49.56#ibcon#wrote, iclass 16, count 0 2006.257.06:43:49.56#ibcon#about to read 3, iclass 16, count 0 2006.257.06:43:49.59#ibcon#read 3, iclass 16, count 0 2006.257.06:43:49.59#ibcon#about to read 4, iclass 16, count 0 2006.257.06:43:49.59#ibcon#read 4, iclass 16, count 0 2006.257.06:43:49.59#ibcon#about to read 5, iclass 16, count 0 2006.257.06:43:49.59#ibcon#read 5, iclass 16, count 0 2006.257.06:43:49.59#ibcon#about to read 6, iclass 16, count 0 2006.257.06:43:49.59#ibcon#read 6, iclass 16, count 0 2006.257.06:43:49.59#ibcon#end of sib2, iclass 16, count 0 2006.257.06:43:49.59#ibcon#*after write, iclass 16, count 0 2006.257.06:43:49.59#ibcon#*before return 0, iclass 16, count 0 2006.257.06:43:49.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:43:49.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:43:49.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:43:49.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:43:49.59$vck44/vabw=wide 2006.257.06:43:49.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.06:43:49.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.06:43:49.59#ibcon#ireg 8 cls_cnt 0 2006.257.06:43:49.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:49.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:49.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:49.59#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:43:49.59#ibcon#first serial, iclass 18, count 0 2006.257.06:43:49.59#ibcon#enter sib2, iclass 18, count 0 2006.257.06:43:49.59#ibcon#flushed, iclass 18, count 0 2006.257.06:43:49.59#ibcon#about to write, iclass 18, count 0 2006.257.06:43:49.59#ibcon#wrote, iclass 18, count 0 2006.257.06:43:49.59#ibcon#about to read 3, iclass 18, count 0 2006.257.06:43:49.61#ibcon#read 3, iclass 18, count 0 2006.257.06:43:49.61#ibcon#about to read 4, iclass 18, count 0 2006.257.06:43:49.61#ibcon#read 4, iclass 18, count 0 2006.257.06:43:49.61#ibcon#about to read 5, iclass 18, count 0 2006.257.06:43:49.61#ibcon#read 5, iclass 18, count 0 2006.257.06:43:49.61#ibcon#about to read 6, iclass 18, count 0 2006.257.06:43:49.61#ibcon#read 6, iclass 18, count 0 2006.257.06:43:49.61#ibcon#end of sib2, iclass 18, count 0 2006.257.06:43:49.61#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:43:49.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:43:49.61#ibcon#[25=BW32\r\n] 2006.257.06:43:49.61#ibcon#*before write, iclass 18, count 0 2006.257.06:43:49.61#ibcon#enter sib2, iclass 18, count 0 2006.257.06:43:49.61#ibcon#flushed, iclass 18, count 0 2006.257.06:43:49.61#ibcon#about to write, iclass 18, count 0 2006.257.06:43:49.61#ibcon#wrote, iclass 18, count 0 2006.257.06:43:49.61#ibcon#about to read 3, iclass 18, count 0 2006.257.06:43:49.64#ibcon#read 3, iclass 18, count 0 2006.257.06:43:49.64#ibcon#about to read 4, iclass 18, count 0 2006.257.06:43:49.64#ibcon#read 4, iclass 18, count 0 2006.257.06:43:49.64#ibcon#about to read 5, iclass 18, count 0 2006.257.06:43:49.64#ibcon#read 5, iclass 18, count 0 2006.257.06:43:49.64#ibcon#about to read 6, iclass 18, count 0 2006.257.06:43:49.64#ibcon#read 6, iclass 18, count 0 2006.257.06:43:49.64#ibcon#end of sib2, iclass 18, count 0 2006.257.06:43:49.64#ibcon#*after write, iclass 18, count 0 2006.257.06:43:49.64#ibcon#*before return 0, iclass 18, count 0 2006.257.06:43:49.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:49.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:43:49.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:43:49.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:43:49.64$vck44/vbbw=wide 2006.257.06:43:49.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.06:43:49.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.06:43:49.64#ibcon#ireg 8 cls_cnt 0 2006.257.06:43:49.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:43:49.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:43:49.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:43:49.71#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:43:49.71#ibcon#first serial, iclass 20, count 0 2006.257.06:43:49.71#ibcon#enter sib2, iclass 20, count 0 2006.257.06:43:49.71#ibcon#flushed, iclass 20, count 0 2006.257.06:43:49.71#ibcon#about to write, iclass 20, count 0 2006.257.06:43:49.71#ibcon#wrote, iclass 20, count 0 2006.257.06:43:49.71#ibcon#about to read 3, iclass 20, count 0 2006.257.06:43:49.73#ibcon#read 3, iclass 20, count 0 2006.257.06:43:49.73#ibcon#about to read 4, iclass 20, count 0 2006.257.06:43:49.73#ibcon#read 4, iclass 20, count 0 2006.257.06:43:49.73#ibcon#about to read 5, iclass 20, count 0 2006.257.06:43:49.73#ibcon#read 5, iclass 20, count 0 2006.257.06:43:49.73#ibcon#about to read 6, iclass 20, count 0 2006.257.06:43:49.73#ibcon#read 6, iclass 20, count 0 2006.257.06:43:49.73#ibcon#end of sib2, iclass 20, count 0 2006.257.06:43:49.73#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:43:49.73#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:43:49.73#ibcon#[27=BW32\r\n] 2006.257.06:43:49.73#ibcon#*before write, iclass 20, count 0 2006.257.06:43:49.73#ibcon#enter sib2, iclass 20, count 0 2006.257.06:43:49.73#ibcon#flushed, iclass 20, count 0 2006.257.06:43:49.73#ibcon#about to write, iclass 20, count 0 2006.257.06:43:49.73#ibcon#wrote, iclass 20, count 0 2006.257.06:43:49.73#ibcon#about to read 3, iclass 20, count 0 2006.257.06:43:49.76#ibcon#read 3, iclass 20, count 0 2006.257.06:43:49.76#ibcon#about to read 4, iclass 20, count 0 2006.257.06:43:49.76#ibcon#read 4, iclass 20, count 0 2006.257.06:43:49.76#ibcon#about to read 5, iclass 20, count 0 2006.257.06:43:49.76#ibcon#read 5, iclass 20, count 0 2006.257.06:43:49.76#ibcon#about to read 6, iclass 20, count 0 2006.257.06:43:49.76#ibcon#read 6, iclass 20, count 0 2006.257.06:43:49.76#ibcon#end of sib2, iclass 20, count 0 2006.257.06:43:49.76#ibcon#*after write, iclass 20, count 0 2006.257.06:43:49.76#ibcon#*before return 0, iclass 20, count 0 2006.257.06:43:49.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:43:49.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:43:49.76#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:43:49.76#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:43:49.76$setupk4/ifdk4 2006.257.06:43:49.76$ifdk4/lo= 2006.257.06:43:49.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:43:49.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:43:49.76$ifdk4/patch= 2006.257.06:43:49.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:43:49.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:43:49.77$setupk4/!*+20s 2006.257.06:43:56.54#abcon#<5=/16 0.9 3.8 20.66 891012.3\r\n> 2006.257.06:43:56.56#abcon#{5=INTERFACE CLEAR} 2006.257.06:43:56.62#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:44:04.28$setupk4/"tpicd 2006.257.06:44:04.28$setupk4/echo=off 2006.257.06:44:04.28$setupk4/xlog=off 2006.257.06:44:04.28:!2006.257.06:48:05 2006.257.06:44:14.14#trakl#Source acquired 2006.257.06:44:15.14#flagr#flagr/antenna,acquired 2006.257.06:48:05.00:preob 2006.257.06:48:05.14/onsource/TRACKING 2006.257.06:48:05.14:!2006.257.06:48:15 2006.257.06:48:15.00:"tape 2006.257.06:48:15.00:"st=record 2006.257.06:48:15.00:data_valid=on 2006.257.06:48:15.00:midob 2006.257.06:48:15.14/onsource/TRACKING 2006.257.06:48:15.14/wx/20.66,1012.3,89 2006.257.06:48:15.23/cable/+6.4780E-03 2006.257.06:48:16.32/va/01,08,usb,yes,38,41 2006.257.06:48:16.32/va/02,07,usb,yes,41,42 2006.257.06:48:16.32/va/03,08,usb,yes,37,39 2006.257.06:48:16.32/va/04,07,usb,yes,42,45 2006.257.06:48:16.32/va/05,04,usb,yes,38,39 2006.257.06:48:16.32/va/06,04,usb,yes,42,42 2006.257.06:48:16.32/va/07,04,usb,yes,43,44 2006.257.06:48:16.32/va/08,04,usb,yes,36,44 2006.257.06:48:16.55/valo/01,524.99,yes,locked 2006.257.06:48:16.55/valo/02,534.99,yes,locked 2006.257.06:48:16.55/valo/03,564.99,yes,locked 2006.257.06:48:16.55/valo/04,624.99,yes,locked 2006.257.06:48:16.55/valo/05,734.99,yes,locked 2006.257.06:48:16.55/valo/06,814.99,yes,locked 2006.257.06:48:16.55/valo/07,864.99,yes,locked 2006.257.06:48:16.55/valo/08,884.99,yes,locked 2006.257.06:48:17.64/vb/01,04,usb,yes,35,33 2006.257.06:48:17.64/vb/02,05,usb,yes,33,33 2006.257.06:48:17.64/vb/03,04,usb,yes,34,38 2006.257.06:48:17.64/vb/04,05,usb,yes,35,34 2006.257.06:48:17.64/vb/05,04,usb,yes,31,34 2006.257.06:48:17.64/vb/06,04,usb,yes,36,32 2006.257.06:48:17.64/vb/07,04,usb,yes,36,36 2006.257.06:48:17.64/vb/08,04,usb,yes,33,37 2006.257.06:48:17.87/vblo/01,629.99,yes,locked 2006.257.06:48:17.87/vblo/02,634.99,yes,locked 2006.257.06:48:17.87/vblo/03,649.99,yes,locked 2006.257.06:48:17.87/vblo/04,679.99,yes,locked 2006.257.06:48:17.87/vblo/05,709.99,yes,locked 2006.257.06:48:17.87/vblo/06,719.99,yes,locked 2006.257.06:48:17.87/vblo/07,734.99,yes,locked 2006.257.06:48:17.87/vblo/08,744.99,yes,locked 2006.257.06:48:18.02/vabw/8 2006.257.06:48:18.17/vbbw/8 2006.257.06:48:18.26/xfe/off,on,16.7 2006.257.06:48:18.63/ifatt/23,28,28,28 2006.257.06:48:19.07/fmout-gps/S +4.47E-07 2006.257.06:48:19.11:!2006.257.06:48:55 2006.257.06:48:55.01:data_valid=off 2006.257.06:48:55.02:"et 2006.257.06:48:55.02:!+3s 2006.257.06:48:58.04:"tape 2006.257.06:48:58.04:postob 2006.257.06:48:58.27/cable/+6.4775E-03 2006.257.06:48:58.27/wx/20.67,1012.3,89 2006.257.06:48:58.33/fmout-gps/S +4.46E-07 2006.257.06:48:58.33:scan_name=257-0649,jd0609,160 2006.257.06:48:58.34:source=2136+141,213901.31,142336.0,2000.0,cw 2006.257.06:49:00.14#flagr#flagr/antenna,new-source 2006.257.06:49:00.15:checkk5 2006.257.06:49:00.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:49:00.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:49:01.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:49:01.80/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:49:02.18/chk_obsdata//k5ts1/T2570648??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:49:02.58/chk_obsdata//k5ts2/T2570648??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:49:03.00/chk_obsdata//k5ts3/T2570648??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:49:03.41/chk_obsdata//k5ts4/T2570648??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:49:04.15/k5log//k5ts1_log_newline 2006.257.06:49:04.85/k5log//k5ts2_log_newline 2006.257.06:49:05.60/k5log//k5ts3_log_newline 2006.257.06:49:06.32/k5log//k5ts4_log_newline 2006.257.06:49:06.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:49:06.34:setupk4=1 2006.257.06:49:06.34$setupk4/echo=on 2006.257.06:49:06.34$setupk4/pcalon 2006.257.06:49:06.34$pcalon/"no phase cal control is implemented here 2006.257.06:49:06.34$setupk4/"tpicd=stop 2006.257.06:49:06.34$setupk4/"rec=synch_on 2006.257.06:49:06.34$setupk4/"rec_mode=128 2006.257.06:49:06.34$setupk4/!* 2006.257.06:49:06.34$setupk4/recpk4 2006.257.06:49:06.34$recpk4/recpatch= 2006.257.06:49:06.35$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:49:06.35$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:49:06.35$setupk4/vck44 2006.257.06:49:06.35$vck44/valo=1,524.99 2006.257.06:49:06.35#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.06:49:06.35#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.06:49:06.35#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:06.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:06.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:06.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:06.35#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:49:06.35#ibcon#first serial, iclass 3, count 0 2006.257.06:49:06.35#ibcon#enter sib2, iclass 3, count 0 2006.257.06:49:06.35#ibcon#flushed, iclass 3, count 0 2006.257.06:49:06.35#ibcon#about to write, iclass 3, count 0 2006.257.06:49:06.35#ibcon#wrote, iclass 3, count 0 2006.257.06:49:06.35#ibcon#about to read 3, iclass 3, count 0 2006.257.06:49:06.36#ibcon#read 3, iclass 3, count 0 2006.257.06:49:06.36#ibcon#about to read 4, iclass 3, count 0 2006.257.06:49:06.36#ibcon#read 4, iclass 3, count 0 2006.257.06:49:06.36#ibcon#about to read 5, iclass 3, count 0 2006.257.06:49:06.36#ibcon#read 5, iclass 3, count 0 2006.257.06:49:06.36#ibcon#about to read 6, iclass 3, count 0 2006.257.06:49:06.36#ibcon#read 6, iclass 3, count 0 2006.257.06:49:06.36#ibcon#end of sib2, iclass 3, count 0 2006.257.06:49:06.36#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:49:06.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:49:06.36#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:49:06.36#ibcon#*before write, iclass 3, count 0 2006.257.06:49:06.36#ibcon#enter sib2, iclass 3, count 0 2006.257.06:49:06.36#ibcon#flushed, iclass 3, count 0 2006.257.06:49:06.36#ibcon#about to write, iclass 3, count 0 2006.257.06:49:06.36#ibcon#wrote, iclass 3, count 0 2006.257.06:49:06.36#ibcon#about to read 3, iclass 3, count 0 2006.257.06:49:06.41#ibcon#read 3, iclass 3, count 0 2006.257.06:49:06.41#ibcon#about to read 4, iclass 3, count 0 2006.257.06:49:06.41#ibcon#read 4, iclass 3, count 0 2006.257.06:49:06.41#ibcon#about to read 5, iclass 3, count 0 2006.257.06:49:06.41#ibcon#read 5, iclass 3, count 0 2006.257.06:49:06.41#ibcon#about to read 6, iclass 3, count 0 2006.257.06:49:06.41#ibcon#read 6, iclass 3, count 0 2006.257.06:49:06.41#ibcon#end of sib2, iclass 3, count 0 2006.257.06:49:06.41#ibcon#*after write, iclass 3, count 0 2006.257.06:49:06.41#ibcon#*before return 0, iclass 3, count 0 2006.257.06:49:06.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:06.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:06.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:49:06.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:49:06.41$vck44/va=1,8 2006.257.06:49:06.41#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.06:49:06.41#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.06:49:06.41#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:06.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:06.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:06.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:06.41#ibcon#enter wrdev, iclass 5, count 2 2006.257.06:49:06.41#ibcon#first serial, iclass 5, count 2 2006.257.06:49:06.41#ibcon#enter sib2, iclass 5, count 2 2006.257.06:49:06.41#ibcon#flushed, iclass 5, count 2 2006.257.06:49:06.41#ibcon#about to write, iclass 5, count 2 2006.257.06:49:06.41#ibcon#wrote, iclass 5, count 2 2006.257.06:49:06.41#ibcon#about to read 3, iclass 5, count 2 2006.257.06:49:06.43#ibcon#read 3, iclass 5, count 2 2006.257.06:49:06.43#ibcon#about to read 4, iclass 5, count 2 2006.257.06:49:06.43#ibcon#read 4, iclass 5, count 2 2006.257.06:49:06.43#ibcon#about to read 5, iclass 5, count 2 2006.257.06:49:06.43#ibcon#read 5, iclass 5, count 2 2006.257.06:49:06.43#ibcon#about to read 6, iclass 5, count 2 2006.257.06:49:06.43#ibcon#read 6, iclass 5, count 2 2006.257.06:49:06.43#ibcon#end of sib2, iclass 5, count 2 2006.257.06:49:06.43#ibcon#*mode == 0, iclass 5, count 2 2006.257.06:49:06.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.06:49:06.43#ibcon#[25=AT01-08\r\n] 2006.257.06:49:06.43#ibcon#*before write, iclass 5, count 2 2006.257.06:49:06.43#ibcon#enter sib2, iclass 5, count 2 2006.257.06:49:06.43#ibcon#flushed, iclass 5, count 2 2006.257.06:49:06.43#ibcon#about to write, iclass 5, count 2 2006.257.06:49:06.43#ibcon#wrote, iclass 5, count 2 2006.257.06:49:06.43#ibcon#about to read 3, iclass 5, count 2 2006.257.06:49:06.46#ibcon#read 3, iclass 5, count 2 2006.257.06:49:06.46#ibcon#about to read 4, iclass 5, count 2 2006.257.06:49:06.46#ibcon#read 4, iclass 5, count 2 2006.257.06:49:06.46#ibcon#about to read 5, iclass 5, count 2 2006.257.06:49:06.46#ibcon#read 5, iclass 5, count 2 2006.257.06:49:06.46#ibcon#about to read 6, iclass 5, count 2 2006.257.06:49:06.46#ibcon#read 6, iclass 5, count 2 2006.257.06:49:06.46#ibcon#end of sib2, iclass 5, count 2 2006.257.06:49:06.46#ibcon#*after write, iclass 5, count 2 2006.257.06:49:06.46#ibcon#*before return 0, iclass 5, count 2 2006.257.06:49:06.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:06.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:06.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.06:49:06.46#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:06.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:06.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:06.58#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:06.58#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:49:06.58#ibcon#first serial, iclass 5, count 0 2006.257.06:49:06.58#ibcon#enter sib2, iclass 5, count 0 2006.257.06:49:06.58#ibcon#flushed, iclass 5, count 0 2006.257.06:49:06.58#ibcon#about to write, iclass 5, count 0 2006.257.06:49:06.58#ibcon#wrote, iclass 5, count 0 2006.257.06:49:06.58#ibcon#about to read 3, iclass 5, count 0 2006.257.06:49:06.60#ibcon#read 3, iclass 5, count 0 2006.257.06:49:06.60#ibcon#about to read 4, iclass 5, count 0 2006.257.06:49:06.60#ibcon#read 4, iclass 5, count 0 2006.257.06:49:06.60#ibcon#about to read 5, iclass 5, count 0 2006.257.06:49:06.60#ibcon#read 5, iclass 5, count 0 2006.257.06:49:06.60#ibcon#about to read 6, iclass 5, count 0 2006.257.06:49:06.60#ibcon#read 6, iclass 5, count 0 2006.257.06:49:06.60#ibcon#end of sib2, iclass 5, count 0 2006.257.06:49:06.60#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:49:06.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:49:06.60#ibcon#[25=USB\r\n] 2006.257.06:49:06.60#ibcon#*before write, iclass 5, count 0 2006.257.06:49:06.60#ibcon#enter sib2, iclass 5, count 0 2006.257.06:49:06.60#ibcon#flushed, iclass 5, count 0 2006.257.06:49:06.60#ibcon#about to write, iclass 5, count 0 2006.257.06:49:06.60#ibcon#wrote, iclass 5, count 0 2006.257.06:49:06.60#ibcon#about to read 3, iclass 5, count 0 2006.257.06:49:06.63#ibcon#read 3, iclass 5, count 0 2006.257.06:49:06.63#ibcon#about to read 4, iclass 5, count 0 2006.257.06:49:06.63#ibcon#read 4, iclass 5, count 0 2006.257.06:49:06.63#ibcon#about to read 5, iclass 5, count 0 2006.257.06:49:06.63#ibcon#read 5, iclass 5, count 0 2006.257.06:49:06.63#ibcon#about to read 6, iclass 5, count 0 2006.257.06:49:06.63#ibcon#read 6, iclass 5, count 0 2006.257.06:49:06.63#ibcon#end of sib2, iclass 5, count 0 2006.257.06:49:06.63#ibcon#*after write, iclass 5, count 0 2006.257.06:49:06.63#ibcon#*before return 0, iclass 5, count 0 2006.257.06:49:06.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:06.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:06.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:49:06.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:49:06.63$vck44/valo=2,534.99 2006.257.06:49:06.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.06:49:06.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.06:49:06.63#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:06.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:06.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:06.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:06.63#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:49:06.63#ibcon#first serial, iclass 7, count 0 2006.257.06:49:06.63#ibcon#enter sib2, iclass 7, count 0 2006.257.06:49:06.63#ibcon#flushed, iclass 7, count 0 2006.257.06:49:06.63#ibcon#about to write, iclass 7, count 0 2006.257.06:49:06.63#ibcon#wrote, iclass 7, count 0 2006.257.06:49:06.63#ibcon#about to read 3, iclass 7, count 0 2006.257.06:49:06.65#ibcon#read 3, iclass 7, count 0 2006.257.06:49:06.65#ibcon#about to read 4, iclass 7, count 0 2006.257.06:49:06.65#ibcon#read 4, iclass 7, count 0 2006.257.06:49:06.65#ibcon#about to read 5, iclass 7, count 0 2006.257.06:49:06.65#ibcon#read 5, iclass 7, count 0 2006.257.06:49:06.65#ibcon#about to read 6, iclass 7, count 0 2006.257.06:49:06.65#ibcon#read 6, iclass 7, count 0 2006.257.06:49:06.65#ibcon#end of sib2, iclass 7, count 0 2006.257.06:49:06.65#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:49:06.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:49:06.65#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:49:06.65#ibcon#*before write, iclass 7, count 0 2006.257.06:49:06.65#ibcon#enter sib2, iclass 7, count 0 2006.257.06:49:06.65#ibcon#flushed, iclass 7, count 0 2006.257.06:49:06.65#ibcon#about to write, iclass 7, count 0 2006.257.06:49:06.65#ibcon#wrote, iclass 7, count 0 2006.257.06:49:06.65#ibcon#about to read 3, iclass 7, count 0 2006.257.06:49:06.69#ibcon#read 3, iclass 7, count 0 2006.257.06:49:06.69#ibcon#about to read 4, iclass 7, count 0 2006.257.06:49:06.69#ibcon#read 4, iclass 7, count 0 2006.257.06:49:06.69#ibcon#about to read 5, iclass 7, count 0 2006.257.06:49:06.69#ibcon#read 5, iclass 7, count 0 2006.257.06:49:06.69#ibcon#about to read 6, iclass 7, count 0 2006.257.06:49:06.69#ibcon#read 6, iclass 7, count 0 2006.257.06:49:06.69#ibcon#end of sib2, iclass 7, count 0 2006.257.06:49:06.69#ibcon#*after write, iclass 7, count 0 2006.257.06:49:06.69#ibcon#*before return 0, iclass 7, count 0 2006.257.06:49:06.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:06.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:06.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:49:06.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:49:06.69$vck44/va=2,7 2006.257.06:49:06.69#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.06:49:06.69#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.06:49:06.69#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:06.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:06.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:06.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:06.75#ibcon#enter wrdev, iclass 11, count 2 2006.257.06:49:06.75#ibcon#first serial, iclass 11, count 2 2006.257.06:49:06.75#ibcon#enter sib2, iclass 11, count 2 2006.257.06:49:06.75#ibcon#flushed, iclass 11, count 2 2006.257.06:49:06.75#ibcon#about to write, iclass 11, count 2 2006.257.06:49:06.75#ibcon#wrote, iclass 11, count 2 2006.257.06:49:06.75#ibcon#about to read 3, iclass 11, count 2 2006.257.06:49:06.77#ibcon#read 3, iclass 11, count 2 2006.257.06:49:06.77#ibcon#about to read 4, iclass 11, count 2 2006.257.06:49:06.77#ibcon#read 4, iclass 11, count 2 2006.257.06:49:06.77#ibcon#about to read 5, iclass 11, count 2 2006.257.06:49:06.77#ibcon#read 5, iclass 11, count 2 2006.257.06:49:06.77#ibcon#about to read 6, iclass 11, count 2 2006.257.06:49:06.77#ibcon#read 6, iclass 11, count 2 2006.257.06:49:06.77#ibcon#end of sib2, iclass 11, count 2 2006.257.06:49:06.77#ibcon#*mode == 0, iclass 11, count 2 2006.257.06:49:06.77#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.06:49:06.77#ibcon#[25=AT02-07\r\n] 2006.257.06:49:06.77#ibcon#*before write, iclass 11, count 2 2006.257.06:49:06.77#ibcon#enter sib2, iclass 11, count 2 2006.257.06:49:06.77#ibcon#flushed, iclass 11, count 2 2006.257.06:49:06.77#ibcon#about to write, iclass 11, count 2 2006.257.06:49:06.77#ibcon#wrote, iclass 11, count 2 2006.257.06:49:06.77#ibcon#about to read 3, iclass 11, count 2 2006.257.06:49:06.80#ibcon#read 3, iclass 11, count 2 2006.257.06:49:06.80#ibcon#about to read 4, iclass 11, count 2 2006.257.06:49:06.80#ibcon#read 4, iclass 11, count 2 2006.257.06:49:06.80#ibcon#about to read 5, iclass 11, count 2 2006.257.06:49:06.80#ibcon#read 5, iclass 11, count 2 2006.257.06:49:06.80#ibcon#about to read 6, iclass 11, count 2 2006.257.06:49:06.80#ibcon#read 6, iclass 11, count 2 2006.257.06:49:06.80#ibcon#end of sib2, iclass 11, count 2 2006.257.06:49:06.80#ibcon#*after write, iclass 11, count 2 2006.257.06:49:06.80#ibcon#*before return 0, iclass 11, count 2 2006.257.06:49:06.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:06.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:06.80#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.06:49:06.80#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:06.80#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:06.92#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:06.92#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:06.92#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:49:06.92#ibcon#first serial, iclass 11, count 0 2006.257.06:49:06.92#ibcon#enter sib2, iclass 11, count 0 2006.257.06:49:06.92#ibcon#flushed, iclass 11, count 0 2006.257.06:49:06.92#ibcon#about to write, iclass 11, count 0 2006.257.06:49:06.92#ibcon#wrote, iclass 11, count 0 2006.257.06:49:06.92#ibcon#about to read 3, iclass 11, count 0 2006.257.06:49:06.94#ibcon#read 3, iclass 11, count 0 2006.257.06:49:06.94#ibcon#about to read 4, iclass 11, count 0 2006.257.06:49:06.94#ibcon#read 4, iclass 11, count 0 2006.257.06:49:06.94#ibcon#about to read 5, iclass 11, count 0 2006.257.06:49:06.94#ibcon#read 5, iclass 11, count 0 2006.257.06:49:06.94#ibcon#about to read 6, iclass 11, count 0 2006.257.06:49:06.94#ibcon#read 6, iclass 11, count 0 2006.257.06:49:06.94#ibcon#end of sib2, iclass 11, count 0 2006.257.06:49:06.94#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:49:06.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:49:06.94#ibcon#[25=USB\r\n] 2006.257.06:49:06.94#ibcon#*before write, iclass 11, count 0 2006.257.06:49:06.94#ibcon#enter sib2, iclass 11, count 0 2006.257.06:49:06.94#ibcon#flushed, iclass 11, count 0 2006.257.06:49:06.94#ibcon#about to write, iclass 11, count 0 2006.257.06:49:06.94#ibcon#wrote, iclass 11, count 0 2006.257.06:49:06.94#ibcon#about to read 3, iclass 11, count 0 2006.257.06:49:06.97#ibcon#read 3, iclass 11, count 0 2006.257.06:49:06.97#ibcon#about to read 4, iclass 11, count 0 2006.257.06:49:06.97#ibcon#read 4, iclass 11, count 0 2006.257.06:49:06.97#ibcon#about to read 5, iclass 11, count 0 2006.257.06:49:06.97#ibcon#read 5, iclass 11, count 0 2006.257.06:49:06.97#ibcon#about to read 6, iclass 11, count 0 2006.257.06:49:06.97#ibcon#read 6, iclass 11, count 0 2006.257.06:49:06.97#ibcon#end of sib2, iclass 11, count 0 2006.257.06:49:06.97#ibcon#*after write, iclass 11, count 0 2006.257.06:49:06.97#ibcon#*before return 0, iclass 11, count 0 2006.257.06:49:06.97#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:06.97#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:06.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:49:06.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:49:06.97$vck44/valo=3,564.99 2006.257.06:49:06.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.06:49:06.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.06:49:06.97#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:06.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:06.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:06.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:06.97#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:49:06.97#ibcon#first serial, iclass 13, count 0 2006.257.06:49:06.97#ibcon#enter sib2, iclass 13, count 0 2006.257.06:49:06.97#ibcon#flushed, iclass 13, count 0 2006.257.06:49:06.97#ibcon#about to write, iclass 13, count 0 2006.257.06:49:06.97#ibcon#wrote, iclass 13, count 0 2006.257.06:49:06.97#ibcon#about to read 3, iclass 13, count 0 2006.257.06:49:06.99#ibcon#read 3, iclass 13, count 0 2006.257.06:49:06.99#ibcon#about to read 4, iclass 13, count 0 2006.257.06:49:06.99#ibcon#read 4, iclass 13, count 0 2006.257.06:49:06.99#ibcon#about to read 5, iclass 13, count 0 2006.257.06:49:06.99#ibcon#read 5, iclass 13, count 0 2006.257.06:49:06.99#ibcon#about to read 6, iclass 13, count 0 2006.257.06:49:06.99#ibcon#read 6, iclass 13, count 0 2006.257.06:49:06.99#ibcon#end of sib2, iclass 13, count 0 2006.257.06:49:06.99#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:49:06.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:49:06.99#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:49:06.99#ibcon#*before write, iclass 13, count 0 2006.257.06:49:06.99#ibcon#enter sib2, iclass 13, count 0 2006.257.06:49:06.99#ibcon#flushed, iclass 13, count 0 2006.257.06:49:06.99#ibcon#about to write, iclass 13, count 0 2006.257.06:49:06.99#ibcon#wrote, iclass 13, count 0 2006.257.06:49:06.99#ibcon#about to read 3, iclass 13, count 0 2006.257.06:49:07.03#ibcon#read 3, iclass 13, count 0 2006.257.06:49:07.03#ibcon#about to read 4, iclass 13, count 0 2006.257.06:49:07.03#ibcon#read 4, iclass 13, count 0 2006.257.06:49:07.03#ibcon#about to read 5, iclass 13, count 0 2006.257.06:49:07.03#ibcon#read 5, iclass 13, count 0 2006.257.06:49:07.03#ibcon#about to read 6, iclass 13, count 0 2006.257.06:49:07.03#ibcon#read 6, iclass 13, count 0 2006.257.06:49:07.03#ibcon#end of sib2, iclass 13, count 0 2006.257.06:49:07.03#ibcon#*after write, iclass 13, count 0 2006.257.06:49:07.03#ibcon#*before return 0, iclass 13, count 0 2006.257.06:49:07.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:07.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:07.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:49:07.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:49:07.03$vck44/va=3,8 2006.257.06:49:07.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.06:49:07.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.06:49:07.03#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:07.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:07.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:07.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:07.09#ibcon#enter wrdev, iclass 15, count 2 2006.257.06:49:07.09#ibcon#first serial, iclass 15, count 2 2006.257.06:49:07.09#ibcon#enter sib2, iclass 15, count 2 2006.257.06:49:07.09#ibcon#flushed, iclass 15, count 2 2006.257.06:49:07.09#ibcon#about to write, iclass 15, count 2 2006.257.06:49:07.09#ibcon#wrote, iclass 15, count 2 2006.257.06:49:07.09#ibcon#about to read 3, iclass 15, count 2 2006.257.06:49:07.11#ibcon#read 3, iclass 15, count 2 2006.257.06:49:07.11#ibcon#about to read 4, iclass 15, count 2 2006.257.06:49:07.11#ibcon#read 4, iclass 15, count 2 2006.257.06:49:07.11#ibcon#about to read 5, iclass 15, count 2 2006.257.06:49:07.11#ibcon#read 5, iclass 15, count 2 2006.257.06:49:07.11#ibcon#about to read 6, iclass 15, count 2 2006.257.06:49:07.11#ibcon#read 6, iclass 15, count 2 2006.257.06:49:07.11#ibcon#end of sib2, iclass 15, count 2 2006.257.06:49:07.11#ibcon#*mode == 0, iclass 15, count 2 2006.257.06:49:07.11#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.06:49:07.11#ibcon#[25=AT03-08\r\n] 2006.257.06:49:07.11#ibcon#*before write, iclass 15, count 2 2006.257.06:49:07.11#ibcon#enter sib2, iclass 15, count 2 2006.257.06:49:07.11#ibcon#flushed, iclass 15, count 2 2006.257.06:49:07.11#ibcon#about to write, iclass 15, count 2 2006.257.06:49:07.11#ibcon#wrote, iclass 15, count 2 2006.257.06:49:07.11#ibcon#about to read 3, iclass 15, count 2 2006.257.06:49:07.14#ibcon#read 3, iclass 15, count 2 2006.257.06:49:07.14#ibcon#about to read 4, iclass 15, count 2 2006.257.06:49:07.14#ibcon#read 4, iclass 15, count 2 2006.257.06:49:07.14#ibcon#about to read 5, iclass 15, count 2 2006.257.06:49:07.14#ibcon#read 5, iclass 15, count 2 2006.257.06:49:07.14#ibcon#about to read 6, iclass 15, count 2 2006.257.06:49:07.14#ibcon#read 6, iclass 15, count 2 2006.257.06:49:07.14#ibcon#end of sib2, iclass 15, count 2 2006.257.06:49:07.14#ibcon#*after write, iclass 15, count 2 2006.257.06:49:07.14#ibcon#*before return 0, iclass 15, count 2 2006.257.06:49:07.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:07.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:07.14#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.06:49:07.14#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:07.14#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:07.26#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:07.26#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:07.26#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:49:07.26#ibcon#first serial, iclass 15, count 0 2006.257.06:49:07.26#ibcon#enter sib2, iclass 15, count 0 2006.257.06:49:07.26#ibcon#flushed, iclass 15, count 0 2006.257.06:49:07.26#ibcon#about to write, iclass 15, count 0 2006.257.06:49:07.26#ibcon#wrote, iclass 15, count 0 2006.257.06:49:07.26#ibcon#about to read 3, iclass 15, count 0 2006.257.06:49:07.28#ibcon#read 3, iclass 15, count 0 2006.257.06:49:07.28#ibcon#about to read 4, iclass 15, count 0 2006.257.06:49:07.28#ibcon#read 4, iclass 15, count 0 2006.257.06:49:07.28#ibcon#about to read 5, iclass 15, count 0 2006.257.06:49:07.28#ibcon#read 5, iclass 15, count 0 2006.257.06:49:07.28#ibcon#about to read 6, iclass 15, count 0 2006.257.06:49:07.28#ibcon#read 6, iclass 15, count 0 2006.257.06:49:07.28#ibcon#end of sib2, iclass 15, count 0 2006.257.06:49:07.28#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:49:07.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:49:07.28#ibcon#[25=USB\r\n] 2006.257.06:49:07.28#ibcon#*before write, iclass 15, count 0 2006.257.06:49:07.28#ibcon#enter sib2, iclass 15, count 0 2006.257.06:49:07.28#ibcon#flushed, iclass 15, count 0 2006.257.06:49:07.28#ibcon#about to write, iclass 15, count 0 2006.257.06:49:07.28#ibcon#wrote, iclass 15, count 0 2006.257.06:49:07.28#ibcon#about to read 3, iclass 15, count 0 2006.257.06:49:07.31#ibcon#read 3, iclass 15, count 0 2006.257.06:49:07.31#ibcon#about to read 4, iclass 15, count 0 2006.257.06:49:07.31#ibcon#read 4, iclass 15, count 0 2006.257.06:49:07.31#ibcon#about to read 5, iclass 15, count 0 2006.257.06:49:07.31#ibcon#read 5, iclass 15, count 0 2006.257.06:49:07.31#ibcon#about to read 6, iclass 15, count 0 2006.257.06:49:07.31#ibcon#read 6, iclass 15, count 0 2006.257.06:49:07.31#ibcon#end of sib2, iclass 15, count 0 2006.257.06:49:07.31#ibcon#*after write, iclass 15, count 0 2006.257.06:49:07.31#ibcon#*before return 0, iclass 15, count 0 2006.257.06:49:07.31#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:07.31#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:07.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:49:07.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:49:07.31$vck44/valo=4,624.99 2006.257.06:49:07.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.06:49:07.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.06:49:07.31#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:07.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:07.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:07.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:07.31#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:49:07.31#ibcon#first serial, iclass 17, count 0 2006.257.06:49:07.31#ibcon#enter sib2, iclass 17, count 0 2006.257.06:49:07.31#ibcon#flushed, iclass 17, count 0 2006.257.06:49:07.31#ibcon#about to write, iclass 17, count 0 2006.257.06:49:07.31#ibcon#wrote, iclass 17, count 0 2006.257.06:49:07.31#ibcon#about to read 3, iclass 17, count 0 2006.257.06:49:07.33#ibcon#read 3, iclass 17, count 0 2006.257.06:49:07.33#ibcon#about to read 4, iclass 17, count 0 2006.257.06:49:07.33#ibcon#read 4, iclass 17, count 0 2006.257.06:49:07.33#ibcon#about to read 5, iclass 17, count 0 2006.257.06:49:07.33#ibcon#read 5, iclass 17, count 0 2006.257.06:49:07.33#ibcon#about to read 6, iclass 17, count 0 2006.257.06:49:07.33#ibcon#read 6, iclass 17, count 0 2006.257.06:49:07.33#ibcon#end of sib2, iclass 17, count 0 2006.257.06:49:07.33#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:49:07.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:49:07.33#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:49:07.33#ibcon#*before write, iclass 17, count 0 2006.257.06:49:07.33#ibcon#enter sib2, iclass 17, count 0 2006.257.06:49:07.33#ibcon#flushed, iclass 17, count 0 2006.257.06:49:07.33#ibcon#about to write, iclass 17, count 0 2006.257.06:49:07.33#ibcon#wrote, iclass 17, count 0 2006.257.06:49:07.33#ibcon#about to read 3, iclass 17, count 0 2006.257.06:49:07.37#ibcon#read 3, iclass 17, count 0 2006.257.06:49:07.37#ibcon#about to read 4, iclass 17, count 0 2006.257.06:49:07.37#ibcon#read 4, iclass 17, count 0 2006.257.06:49:07.37#ibcon#about to read 5, iclass 17, count 0 2006.257.06:49:07.37#ibcon#read 5, iclass 17, count 0 2006.257.06:49:07.37#ibcon#about to read 6, iclass 17, count 0 2006.257.06:49:07.37#ibcon#read 6, iclass 17, count 0 2006.257.06:49:07.37#ibcon#end of sib2, iclass 17, count 0 2006.257.06:49:07.37#ibcon#*after write, iclass 17, count 0 2006.257.06:49:07.37#ibcon#*before return 0, iclass 17, count 0 2006.257.06:49:07.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:07.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:07.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:49:07.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:49:07.37$vck44/va=4,7 2006.257.06:49:07.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.06:49:07.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.06:49:07.37#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:07.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:07.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:07.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:07.43#ibcon#enter wrdev, iclass 19, count 2 2006.257.06:49:07.43#ibcon#first serial, iclass 19, count 2 2006.257.06:49:07.43#ibcon#enter sib2, iclass 19, count 2 2006.257.06:49:07.43#ibcon#flushed, iclass 19, count 2 2006.257.06:49:07.43#ibcon#about to write, iclass 19, count 2 2006.257.06:49:07.43#ibcon#wrote, iclass 19, count 2 2006.257.06:49:07.43#ibcon#about to read 3, iclass 19, count 2 2006.257.06:49:07.45#ibcon#read 3, iclass 19, count 2 2006.257.06:49:07.45#ibcon#about to read 4, iclass 19, count 2 2006.257.06:49:07.45#ibcon#read 4, iclass 19, count 2 2006.257.06:49:07.45#ibcon#about to read 5, iclass 19, count 2 2006.257.06:49:07.45#ibcon#read 5, iclass 19, count 2 2006.257.06:49:07.45#ibcon#about to read 6, iclass 19, count 2 2006.257.06:49:07.45#ibcon#read 6, iclass 19, count 2 2006.257.06:49:07.45#ibcon#end of sib2, iclass 19, count 2 2006.257.06:49:07.45#ibcon#*mode == 0, iclass 19, count 2 2006.257.06:49:07.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.06:49:07.45#ibcon#[25=AT04-07\r\n] 2006.257.06:49:07.45#ibcon#*before write, iclass 19, count 2 2006.257.06:49:07.45#ibcon#enter sib2, iclass 19, count 2 2006.257.06:49:07.45#ibcon#flushed, iclass 19, count 2 2006.257.06:49:07.45#ibcon#about to write, iclass 19, count 2 2006.257.06:49:07.45#ibcon#wrote, iclass 19, count 2 2006.257.06:49:07.45#ibcon#about to read 3, iclass 19, count 2 2006.257.06:49:07.48#ibcon#read 3, iclass 19, count 2 2006.257.06:49:07.48#ibcon#about to read 4, iclass 19, count 2 2006.257.06:49:07.48#ibcon#read 4, iclass 19, count 2 2006.257.06:49:07.48#ibcon#about to read 5, iclass 19, count 2 2006.257.06:49:07.48#ibcon#read 5, iclass 19, count 2 2006.257.06:49:07.48#ibcon#about to read 6, iclass 19, count 2 2006.257.06:49:07.48#ibcon#read 6, iclass 19, count 2 2006.257.06:49:07.48#ibcon#end of sib2, iclass 19, count 2 2006.257.06:49:07.48#ibcon#*after write, iclass 19, count 2 2006.257.06:49:07.48#ibcon#*before return 0, iclass 19, count 2 2006.257.06:49:07.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:07.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:07.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.06:49:07.48#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:07.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:07.60#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:07.60#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:07.60#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:49:07.60#ibcon#first serial, iclass 19, count 0 2006.257.06:49:07.60#ibcon#enter sib2, iclass 19, count 0 2006.257.06:49:07.60#ibcon#flushed, iclass 19, count 0 2006.257.06:49:07.60#ibcon#about to write, iclass 19, count 0 2006.257.06:49:07.60#ibcon#wrote, iclass 19, count 0 2006.257.06:49:07.60#ibcon#about to read 3, iclass 19, count 0 2006.257.06:49:07.62#ibcon#read 3, iclass 19, count 0 2006.257.06:49:07.62#ibcon#about to read 4, iclass 19, count 0 2006.257.06:49:07.62#ibcon#read 4, iclass 19, count 0 2006.257.06:49:07.62#ibcon#about to read 5, iclass 19, count 0 2006.257.06:49:07.62#ibcon#read 5, iclass 19, count 0 2006.257.06:49:07.62#ibcon#about to read 6, iclass 19, count 0 2006.257.06:49:07.62#ibcon#read 6, iclass 19, count 0 2006.257.06:49:07.62#ibcon#end of sib2, iclass 19, count 0 2006.257.06:49:07.62#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:49:07.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:49:07.62#ibcon#[25=USB\r\n] 2006.257.06:49:07.62#ibcon#*before write, iclass 19, count 0 2006.257.06:49:07.62#ibcon#enter sib2, iclass 19, count 0 2006.257.06:49:07.62#ibcon#flushed, iclass 19, count 0 2006.257.06:49:07.62#ibcon#about to write, iclass 19, count 0 2006.257.06:49:07.62#ibcon#wrote, iclass 19, count 0 2006.257.06:49:07.62#ibcon#about to read 3, iclass 19, count 0 2006.257.06:49:07.65#ibcon#read 3, iclass 19, count 0 2006.257.06:49:07.65#ibcon#about to read 4, iclass 19, count 0 2006.257.06:49:07.65#ibcon#read 4, iclass 19, count 0 2006.257.06:49:07.65#ibcon#about to read 5, iclass 19, count 0 2006.257.06:49:07.65#ibcon#read 5, iclass 19, count 0 2006.257.06:49:07.65#ibcon#about to read 6, iclass 19, count 0 2006.257.06:49:07.65#ibcon#read 6, iclass 19, count 0 2006.257.06:49:07.65#ibcon#end of sib2, iclass 19, count 0 2006.257.06:49:07.65#ibcon#*after write, iclass 19, count 0 2006.257.06:49:07.65#ibcon#*before return 0, iclass 19, count 0 2006.257.06:49:07.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:07.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:07.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:49:07.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:49:07.65$vck44/valo=5,734.99 2006.257.06:49:07.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.06:49:07.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.06:49:07.65#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:07.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:07.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:07.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:07.65#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:49:07.65#ibcon#first serial, iclass 21, count 0 2006.257.06:49:07.65#ibcon#enter sib2, iclass 21, count 0 2006.257.06:49:07.65#ibcon#flushed, iclass 21, count 0 2006.257.06:49:07.65#ibcon#about to write, iclass 21, count 0 2006.257.06:49:07.65#ibcon#wrote, iclass 21, count 0 2006.257.06:49:07.65#ibcon#about to read 3, iclass 21, count 0 2006.257.06:49:07.67#ibcon#read 3, iclass 21, count 0 2006.257.06:49:07.67#ibcon#about to read 4, iclass 21, count 0 2006.257.06:49:07.67#ibcon#read 4, iclass 21, count 0 2006.257.06:49:07.67#ibcon#about to read 5, iclass 21, count 0 2006.257.06:49:07.67#ibcon#read 5, iclass 21, count 0 2006.257.06:49:07.67#ibcon#about to read 6, iclass 21, count 0 2006.257.06:49:07.67#ibcon#read 6, iclass 21, count 0 2006.257.06:49:07.67#ibcon#end of sib2, iclass 21, count 0 2006.257.06:49:07.67#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:49:07.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:49:07.67#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:49:07.67#ibcon#*before write, iclass 21, count 0 2006.257.06:49:07.67#ibcon#enter sib2, iclass 21, count 0 2006.257.06:49:07.67#ibcon#flushed, iclass 21, count 0 2006.257.06:49:07.67#ibcon#about to write, iclass 21, count 0 2006.257.06:49:07.67#ibcon#wrote, iclass 21, count 0 2006.257.06:49:07.67#ibcon#about to read 3, iclass 21, count 0 2006.257.06:49:07.71#ibcon#read 3, iclass 21, count 0 2006.257.06:49:07.71#ibcon#about to read 4, iclass 21, count 0 2006.257.06:49:07.71#ibcon#read 4, iclass 21, count 0 2006.257.06:49:07.71#ibcon#about to read 5, iclass 21, count 0 2006.257.06:49:07.71#ibcon#read 5, iclass 21, count 0 2006.257.06:49:07.71#ibcon#about to read 6, iclass 21, count 0 2006.257.06:49:07.71#ibcon#read 6, iclass 21, count 0 2006.257.06:49:07.71#ibcon#end of sib2, iclass 21, count 0 2006.257.06:49:07.71#ibcon#*after write, iclass 21, count 0 2006.257.06:49:07.71#ibcon#*before return 0, iclass 21, count 0 2006.257.06:49:07.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:07.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:07.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:49:07.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:49:07.71$vck44/va=5,4 2006.257.06:49:07.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.06:49:07.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.06:49:07.71#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:07.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:07.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:07.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:07.77#ibcon#enter wrdev, iclass 23, count 2 2006.257.06:49:07.77#ibcon#first serial, iclass 23, count 2 2006.257.06:49:07.77#ibcon#enter sib2, iclass 23, count 2 2006.257.06:49:07.77#ibcon#flushed, iclass 23, count 2 2006.257.06:49:07.77#ibcon#about to write, iclass 23, count 2 2006.257.06:49:07.77#ibcon#wrote, iclass 23, count 2 2006.257.06:49:07.77#ibcon#about to read 3, iclass 23, count 2 2006.257.06:49:07.79#ibcon#read 3, iclass 23, count 2 2006.257.06:49:07.79#ibcon#about to read 4, iclass 23, count 2 2006.257.06:49:07.79#ibcon#read 4, iclass 23, count 2 2006.257.06:49:07.79#ibcon#about to read 5, iclass 23, count 2 2006.257.06:49:07.79#ibcon#read 5, iclass 23, count 2 2006.257.06:49:07.79#ibcon#about to read 6, iclass 23, count 2 2006.257.06:49:07.79#ibcon#read 6, iclass 23, count 2 2006.257.06:49:07.79#ibcon#end of sib2, iclass 23, count 2 2006.257.06:49:07.79#ibcon#*mode == 0, iclass 23, count 2 2006.257.06:49:07.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.06:49:07.79#ibcon#[25=AT05-04\r\n] 2006.257.06:49:07.79#ibcon#*before write, iclass 23, count 2 2006.257.06:49:07.79#ibcon#enter sib2, iclass 23, count 2 2006.257.06:49:07.79#ibcon#flushed, iclass 23, count 2 2006.257.06:49:07.79#ibcon#about to write, iclass 23, count 2 2006.257.06:49:07.79#ibcon#wrote, iclass 23, count 2 2006.257.06:49:07.79#ibcon#about to read 3, iclass 23, count 2 2006.257.06:49:07.82#ibcon#read 3, iclass 23, count 2 2006.257.06:49:07.82#ibcon#about to read 4, iclass 23, count 2 2006.257.06:49:07.82#ibcon#read 4, iclass 23, count 2 2006.257.06:49:07.82#ibcon#about to read 5, iclass 23, count 2 2006.257.06:49:07.82#ibcon#read 5, iclass 23, count 2 2006.257.06:49:07.82#ibcon#about to read 6, iclass 23, count 2 2006.257.06:49:07.82#ibcon#read 6, iclass 23, count 2 2006.257.06:49:07.82#ibcon#end of sib2, iclass 23, count 2 2006.257.06:49:07.82#ibcon#*after write, iclass 23, count 2 2006.257.06:49:07.82#ibcon#*before return 0, iclass 23, count 2 2006.257.06:49:07.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:07.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:07.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.06:49:07.82#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:07.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:07.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:07.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:07.94#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:49:07.94#ibcon#first serial, iclass 23, count 0 2006.257.06:49:07.94#ibcon#enter sib2, iclass 23, count 0 2006.257.06:49:07.94#ibcon#flushed, iclass 23, count 0 2006.257.06:49:07.94#ibcon#about to write, iclass 23, count 0 2006.257.06:49:07.94#ibcon#wrote, iclass 23, count 0 2006.257.06:49:07.94#ibcon#about to read 3, iclass 23, count 0 2006.257.06:49:07.96#ibcon#read 3, iclass 23, count 0 2006.257.06:49:07.96#ibcon#about to read 4, iclass 23, count 0 2006.257.06:49:07.96#ibcon#read 4, iclass 23, count 0 2006.257.06:49:07.96#ibcon#about to read 5, iclass 23, count 0 2006.257.06:49:07.96#ibcon#read 5, iclass 23, count 0 2006.257.06:49:07.96#ibcon#about to read 6, iclass 23, count 0 2006.257.06:49:07.96#ibcon#read 6, iclass 23, count 0 2006.257.06:49:07.96#ibcon#end of sib2, iclass 23, count 0 2006.257.06:49:07.96#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:49:07.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:49:07.96#ibcon#[25=USB\r\n] 2006.257.06:49:07.96#ibcon#*before write, iclass 23, count 0 2006.257.06:49:07.96#ibcon#enter sib2, iclass 23, count 0 2006.257.06:49:07.96#ibcon#flushed, iclass 23, count 0 2006.257.06:49:07.96#ibcon#about to write, iclass 23, count 0 2006.257.06:49:07.96#ibcon#wrote, iclass 23, count 0 2006.257.06:49:07.96#ibcon#about to read 3, iclass 23, count 0 2006.257.06:49:07.99#ibcon#read 3, iclass 23, count 0 2006.257.06:49:07.99#ibcon#about to read 4, iclass 23, count 0 2006.257.06:49:07.99#ibcon#read 4, iclass 23, count 0 2006.257.06:49:07.99#ibcon#about to read 5, iclass 23, count 0 2006.257.06:49:07.99#ibcon#read 5, iclass 23, count 0 2006.257.06:49:07.99#ibcon#about to read 6, iclass 23, count 0 2006.257.06:49:07.99#ibcon#read 6, iclass 23, count 0 2006.257.06:49:07.99#ibcon#end of sib2, iclass 23, count 0 2006.257.06:49:07.99#ibcon#*after write, iclass 23, count 0 2006.257.06:49:07.99#ibcon#*before return 0, iclass 23, count 0 2006.257.06:49:07.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:07.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:07.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:49:07.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:49:07.99$vck44/valo=6,814.99 2006.257.06:49:07.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.06:49:07.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.06:49:07.99#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:07.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:07.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:07.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:07.99#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:49:07.99#ibcon#first serial, iclass 25, count 0 2006.257.06:49:07.99#ibcon#enter sib2, iclass 25, count 0 2006.257.06:49:07.99#ibcon#flushed, iclass 25, count 0 2006.257.06:49:07.99#ibcon#about to write, iclass 25, count 0 2006.257.06:49:07.99#ibcon#wrote, iclass 25, count 0 2006.257.06:49:07.99#ibcon#about to read 3, iclass 25, count 0 2006.257.06:49:08.01#ibcon#read 3, iclass 25, count 0 2006.257.06:49:08.01#ibcon#about to read 4, iclass 25, count 0 2006.257.06:49:08.01#ibcon#read 4, iclass 25, count 0 2006.257.06:49:08.01#ibcon#about to read 5, iclass 25, count 0 2006.257.06:49:08.01#ibcon#read 5, iclass 25, count 0 2006.257.06:49:08.01#ibcon#about to read 6, iclass 25, count 0 2006.257.06:49:08.01#ibcon#read 6, iclass 25, count 0 2006.257.06:49:08.01#ibcon#end of sib2, iclass 25, count 0 2006.257.06:49:08.01#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:49:08.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:49:08.01#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:49:08.01#ibcon#*before write, iclass 25, count 0 2006.257.06:49:08.01#ibcon#enter sib2, iclass 25, count 0 2006.257.06:49:08.01#ibcon#flushed, iclass 25, count 0 2006.257.06:49:08.01#ibcon#about to write, iclass 25, count 0 2006.257.06:49:08.01#ibcon#wrote, iclass 25, count 0 2006.257.06:49:08.01#ibcon#about to read 3, iclass 25, count 0 2006.257.06:49:08.05#ibcon#read 3, iclass 25, count 0 2006.257.06:49:08.05#ibcon#about to read 4, iclass 25, count 0 2006.257.06:49:08.05#ibcon#read 4, iclass 25, count 0 2006.257.06:49:08.05#ibcon#about to read 5, iclass 25, count 0 2006.257.06:49:08.05#ibcon#read 5, iclass 25, count 0 2006.257.06:49:08.05#ibcon#about to read 6, iclass 25, count 0 2006.257.06:49:08.05#ibcon#read 6, iclass 25, count 0 2006.257.06:49:08.05#ibcon#end of sib2, iclass 25, count 0 2006.257.06:49:08.05#ibcon#*after write, iclass 25, count 0 2006.257.06:49:08.05#ibcon#*before return 0, iclass 25, count 0 2006.257.06:49:08.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:08.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:08.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:49:08.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:49:08.05$vck44/va=6,4 2006.257.06:49:08.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.06:49:08.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.06:49:08.05#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:08.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:08.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:08.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:08.11#ibcon#enter wrdev, iclass 27, count 2 2006.257.06:49:08.11#ibcon#first serial, iclass 27, count 2 2006.257.06:49:08.11#ibcon#enter sib2, iclass 27, count 2 2006.257.06:49:08.11#ibcon#flushed, iclass 27, count 2 2006.257.06:49:08.11#ibcon#about to write, iclass 27, count 2 2006.257.06:49:08.11#ibcon#wrote, iclass 27, count 2 2006.257.06:49:08.11#ibcon#about to read 3, iclass 27, count 2 2006.257.06:49:08.13#ibcon#read 3, iclass 27, count 2 2006.257.06:49:08.13#ibcon#about to read 4, iclass 27, count 2 2006.257.06:49:08.13#ibcon#read 4, iclass 27, count 2 2006.257.06:49:08.13#ibcon#about to read 5, iclass 27, count 2 2006.257.06:49:08.13#ibcon#read 5, iclass 27, count 2 2006.257.06:49:08.13#ibcon#about to read 6, iclass 27, count 2 2006.257.06:49:08.13#ibcon#read 6, iclass 27, count 2 2006.257.06:49:08.13#ibcon#end of sib2, iclass 27, count 2 2006.257.06:49:08.13#ibcon#*mode == 0, iclass 27, count 2 2006.257.06:49:08.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.06:49:08.13#ibcon#[25=AT06-04\r\n] 2006.257.06:49:08.13#ibcon#*before write, iclass 27, count 2 2006.257.06:49:08.13#ibcon#enter sib2, iclass 27, count 2 2006.257.06:49:08.13#ibcon#flushed, iclass 27, count 2 2006.257.06:49:08.13#ibcon#about to write, iclass 27, count 2 2006.257.06:49:08.13#ibcon#wrote, iclass 27, count 2 2006.257.06:49:08.13#ibcon#about to read 3, iclass 27, count 2 2006.257.06:49:08.16#ibcon#read 3, iclass 27, count 2 2006.257.06:49:08.16#ibcon#about to read 4, iclass 27, count 2 2006.257.06:49:08.16#ibcon#read 4, iclass 27, count 2 2006.257.06:49:08.16#ibcon#about to read 5, iclass 27, count 2 2006.257.06:49:08.16#ibcon#read 5, iclass 27, count 2 2006.257.06:49:08.16#ibcon#about to read 6, iclass 27, count 2 2006.257.06:49:08.16#ibcon#read 6, iclass 27, count 2 2006.257.06:49:08.16#ibcon#end of sib2, iclass 27, count 2 2006.257.06:49:08.16#ibcon#*after write, iclass 27, count 2 2006.257.06:49:08.16#ibcon#*before return 0, iclass 27, count 2 2006.257.06:49:08.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:08.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:08.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.06:49:08.16#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:08.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:08.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:08.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:08.28#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:49:08.28#ibcon#first serial, iclass 27, count 0 2006.257.06:49:08.28#ibcon#enter sib2, iclass 27, count 0 2006.257.06:49:08.28#ibcon#flushed, iclass 27, count 0 2006.257.06:49:08.28#ibcon#about to write, iclass 27, count 0 2006.257.06:49:08.28#ibcon#wrote, iclass 27, count 0 2006.257.06:49:08.28#ibcon#about to read 3, iclass 27, count 0 2006.257.06:49:08.30#ibcon#read 3, iclass 27, count 0 2006.257.06:49:08.30#ibcon#about to read 4, iclass 27, count 0 2006.257.06:49:08.30#ibcon#read 4, iclass 27, count 0 2006.257.06:49:08.30#ibcon#about to read 5, iclass 27, count 0 2006.257.06:49:08.30#ibcon#read 5, iclass 27, count 0 2006.257.06:49:08.30#ibcon#about to read 6, iclass 27, count 0 2006.257.06:49:08.30#ibcon#read 6, iclass 27, count 0 2006.257.06:49:08.30#ibcon#end of sib2, iclass 27, count 0 2006.257.06:49:08.30#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:49:08.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:49:08.30#ibcon#[25=USB\r\n] 2006.257.06:49:08.30#ibcon#*before write, iclass 27, count 0 2006.257.06:49:08.30#ibcon#enter sib2, iclass 27, count 0 2006.257.06:49:08.30#ibcon#flushed, iclass 27, count 0 2006.257.06:49:08.30#ibcon#about to write, iclass 27, count 0 2006.257.06:49:08.30#ibcon#wrote, iclass 27, count 0 2006.257.06:49:08.30#ibcon#about to read 3, iclass 27, count 0 2006.257.06:49:08.33#ibcon#read 3, iclass 27, count 0 2006.257.06:49:08.33#ibcon#about to read 4, iclass 27, count 0 2006.257.06:49:08.33#ibcon#read 4, iclass 27, count 0 2006.257.06:49:08.33#ibcon#about to read 5, iclass 27, count 0 2006.257.06:49:08.33#ibcon#read 5, iclass 27, count 0 2006.257.06:49:08.33#ibcon#about to read 6, iclass 27, count 0 2006.257.06:49:08.33#ibcon#read 6, iclass 27, count 0 2006.257.06:49:08.33#ibcon#end of sib2, iclass 27, count 0 2006.257.06:49:08.33#ibcon#*after write, iclass 27, count 0 2006.257.06:49:08.33#ibcon#*before return 0, iclass 27, count 0 2006.257.06:49:08.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:08.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:08.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:49:08.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:49:08.33$vck44/valo=7,864.99 2006.257.06:49:08.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.06:49:08.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.06:49:08.33#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:08.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:08.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:08.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:08.33#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:49:08.33#ibcon#first serial, iclass 29, count 0 2006.257.06:49:08.33#ibcon#enter sib2, iclass 29, count 0 2006.257.06:49:08.33#ibcon#flushed, iclass 29, count 0 2006.257.06:49:08.33#ibcon#about to write, iclass 29, count 0 2006.257.06:49:08.33#ibcon#wrote, iclass 29, count 0 2006.257.06:49:08.33#ibcon#about to read 3, iclass 29, count 0 2006.257.06:49:08.35#ibcon#read 3, iclass 29, count 0 2006.257.06:49:08.35#ibcon#about to read 4, iclass 29, count 0 2006.257.06:49:08.35#ibcon#read 4, iclass 29, count 0 2006.257.06:49:08.35#ibcon#about to read 5, iclass 29, count 0 2006.257.06:49:08.35#ibcon#read 5, iclass 29, count 0 2006.257.06:49:08.35#ibcon#about to read 6, iclass 29, count 0 2006.257.06:49:08.35#ibcon#read 6, iclass 29, count 0 2006.257.06:49:08.35#ibcon#end of sib2, iclass 29, count 0 2006.257.06:49:08.35#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:49:08.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:49:08.35#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:49:08.35#ibcon#*before write, iclass 29, count 0 2006.257.06:49:08.35#ibcon#enter sib2, iclass 29, count 0 2006.257.06:49:08.35#ibcon#flushed, iclass 29, count 0 2006.257.06:49:08.35#ibcon#about to write, iclass 29, count 0 2006.257.06:49:08.35#ibcon#wrote, iclass 29, count 0 2006.257.06:49:08.35#ibcon#about to read 3, iclass 29, count 0 2006.257.06:49:08.39#ibcon#read 3, iclass 29, count 0 2006.257.06:49:08.39#ibcon#about to read 4, iclass 29, count 0 2006.257.06:49:08.39#ibcon#read 4, iclass 29, count 0 2006.257.06:49:08.39#ibcon#about to read 5, iclass 29, count 0 2006.257.06:49:08.39#ibcon#read 5, iclass 29, count 0 2006.257.06:49:08.39#ibcon#about to read 6, iclass 29, count 0 2006.257.06:49:08.39#ibcon#read 6, iclass 29, count 0 2006.257.06:49:08.39#ibcon#end of sib2, iclass 29, count 0 2006.257.06:49:08.39#ibcon#*after write, iclass 29, count 0 2006.257.06:49:08.39#ibcon#*before return 0, iclass 29, count 0 2006.257.06:49:08.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:08.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:08.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:49:08.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:49:08.39$vck44/va=7,4 2006.257.06:49:08.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.06:49:08.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.06:49:08.39#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:08.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:08.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:08.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:08.45#ibcon#enter wrdev, iclass 31, count 2 2006.257.06:49:08.45#ibcon#first serial, iclass 31, count 2 2006.257.06:49:08.45#ibcon#enter sib2, iclass 31, count 2 2006.257.06:49:08.45#ibcon#flushed, iclass 31, count 2 2006.257.06:49:08.45#ibcon#about to write, iclass 31, count 2 2006.257.06:49:08.45#ibcon#wrote, iclass 31, count 2 2006.257.06:49:08.45#ibcon#about to read 3, iclass 31, count 2 2006.257.06:49:08.47#ibcon#read 3, iclass 31, count 2 2006.257.06:49:08.47#ibcon#about to read 4, iclass 31, count 2 2006.257.06:49:08.47#ibcon#read 4, iclass 31, count 2 2006.257.06:49:08.47#ibcon#about to read 5, iclass 31, count 2 2006.257.06:49:08.47#ibcon#read 5, iclass 31, count 2 2006.257.06:49:08.47#ibcon#about to read 6, iclass 31, count 2 2006.257.06:49:08.47#ibcon#read 6, iclass 31, count 2 2006.257.06:49:08.47#ibcon#end of sib2, iclass 31, count 2 2006.257.06:49:08.47#ibcon#*mode == 0, iclass 31, count 2 2006.257.06:49:08.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.06:49:08.47#ibcon#[25=AT07-04\r\n] 2006.257.06:49:08.47#ibcon#*before write, iclass 31, count 2 2006.257.06:49:08.47#ibcon#enter sib2, iclass 31, count 2 2006.257.06:49:08.47#ibcon#flushed, iclass 31, count 2 2006.257.06:49:08.47#ibcon#about to write, iclass 31, count 2 2006.257.06:49:08.47#ibcon#wrote, iclass 31, count 2 2006.257.06:49:08.47#ibcon#about to read 3, iclass 31, count 2 2006.257.06:49:08.50#ibcon#read 3, iclass 31, count 2 2006.257.06:49:08.50#ibcon#about to read 4, iclass 31, count 2 2006.257.06:49:08.50#ibcon#read 4, iclass 31, count 2 2006.257.06:49:08.50#ibcon#about to read 5, iclass 31, count 2 2006.257.06:49:08.50#ibcon#read 5, iclass 31, count 2 2006.257.06:49:08.50#ibcon#about to read 6, iclass 31, count 2 2006.257.06:49:08.50#ibcon#read 6, iclass 31, count 2 2006.257.06:49:08.50#ibcon#end of sib2, iclass 31, count 2 2006.257.06:49:08.50#ibcon#*after write, iclass 31, count 2 2006.257.06:49:08.50#ibcon#*before return 0, iclass 31, count 2 2006.257.06:49:08.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:08.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:08.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.06:49:08.50#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:08.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:08.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:08.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:08.62#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:49:08.62#ibcon#first serial, iclass 31, count 0 2006.257.06:49:08.62#ibcon#enter sib2, iclass 31, count 0 2006.257.06:49:08.62#ibcon#flushed, iclass 31, count 0 2006.257.06:49:08.62#ibcon#about to write, iclass 31, count 0 2006.257.06:49:08.62#ibcon#wrote, iclass 31, count 0 2006.257.06:49:08.62#ibcon#about to read 3, iclass 31, count 0 2006.257.06:49:08.64#ibcon#read 3, iclass 31, count 0 2006.257.06:49:08.64#ibcon#about to read 4, iclass 31, count 0 2006.257.06:49:08.64#ibcon#read 4, iclass 31, count 0 2006.257.06:49:08.64#ibcon#about to read 5, iclass 31, count 0 2006.257.06:49:08.64#ibcon#read 5, iclass 31, count 0 2006.257.06:49:08.64#ibcon#about to read 6, iclass 31, count 0 2006.257.06:49:08.64#ibcon#read 6, iclass 31, count 0 2006.257.06:49:08.64#ibcon#end of sib2, iclass 31, count 0 2006.257.06:49:08.64#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:49:08.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:49:08.64#ibcon#[25=USB\r\n] 2006.257.06:49:08.64#ibcon#*before write, iclass 31, count 0 2006.257.06:49:08.64#ibcon#enter sib2, iclass 31, count 0 2006.257.06:49:08.64#ibcon#flushed, iclass 31, count 0 2006.257.06:49:08.64#ibcon#about to write, iclass 31, count 0 2006.257.06:49:08.64#ibcon#wrote, iclass 31, count 0 2006.257.06:49:08.64#ibcon#about to read 3, iclass 31, count 0 2006.257.06:49:08.67#ibcon#read 3, iclass 31, count 0 2006.257.06:49:08.67#ibcon#about to read 4, iclass 31, count 0 2006.257.06:49:08.67#ibcon#read 4, iclass 31, count 0 2006.257.06:49:08.67#ibcon#about to read 5, iclass 31, count 0 2006.257.06:49:08.67#ibcon#read 5, iclass 31, count 0 2006.257.06:49:08.67#ibcon#about to read 6, iclass 31, count 0 2006.257.06:49:08.67#ibcon#read 6, iclass 31, count 0 2006.257.06:49:08.67#ibcon#end of sib2, iclass 31, count 0 2006.257.06:49:08.67#ibcon#*after write, iclass 31, count 0 2006.257.06:49:08.67#ibcon#*before return 0, iclass 31, count 0 2006.257.06:49:08.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:08.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:08.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:49:08.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:49:08.67$vck44/valo=8,884.99 2006.257.06:49:08.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.06:49:08.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.06:49:08.67#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:08.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:08.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:08.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:08.67#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:49:08.67#ibcon#first serial, iclass 33, count 0 2006.257.06:49:08.67#ibcon#enter sib2, iclass 33, count 0 2006.257.06:49:08.67#ibcon#flushed, iclass 33, count 0 2006.257.06:49:08.67#ibcon#about to write, iclass 33, count 0 2006.257.06:49:08.67#ibcon#wrote, iclass 33, count 0 2006.257.06:49:08.67#ibcon#about to read 3, iclass 33, count 0 2006.257.06:49:08.69#ibcon#read 3, iclass 33, count 0 2006.257.06:49:08.69#ibcon#about to read 4, iclass 33, count 0 2006.257.06:49:08.69#ibcon#read 4, iclass 33, count 0 2006.257.06:49:08.69#ibcon#about to read 5, iclass 33, count 0 2006.257.06:49:08.69#ibcon#read 5, iclass 33, count 0 2006.257.06:49:08.69#ibcon#about to read 6, iclass 33, count 0 2006.257.06:49:08.69#ibcon#read 6, iclass 33, count 0 2006.257.06:49:08.69#ibcon#end of sib2, iclass 33, count 0 2006.257.06:49:08.69#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:49:08.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:49:08.69#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:49:08.69#ibcon#*before write, iclass 33, count 0 2006.257.06:49:08.69#ibcon#enter sib2, iclass 33, count 0 2006.257.06:49:08.69#ibcon#flushed, iclass 33, count 0 2006.257.06:49:08.69#ibcon#about to write, iclass 33, count 0 2006.257.06:49:08.69#ibcon#wrote, iclass 33, count 0 2006.257.06:49:08.69#ibcon#about to read 3, iclass 33, count 0 2006.257.06:49:08.73#ibcon#read 3, iclass 33, count 0 2006.257.06:49:08.73#ibcon#about to read 4, iclass 33, count 0 2006.257.06:49:08.73#ibcon#read 4, iclass 33, count 0 2006.257.06:49:08.73#ibcon#about to read 5, iclass 33, count 0 2006.257.06:49:08.73#ibcon#read 5, iclass 33, count 0 2006.257.06:49:08.73#ibcon#about to read 6, iclass 33, count 0 2006.257.06:49:08.73#ibcon#read 6, iclass 33, count 0 2006.257.06:49:08.73#ibcon#end of sib2, iclass 33, count 0 2006.257.06:49:08.73#ibcon#*after write, iclass 33, count 0 2006.257.06:49:08.73#ibcon#*before return 0, iclass 33, count 0 2006.257.06:49:08.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:08.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:08.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:49:08.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:49:08.73$vck44/va=8,4 2006.257.06:49:08.73#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.06:49:08.73#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.06:49:08.73#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:08.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:49:08.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:49:08.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:49:08.79#ibcon#enter wrdev, iclass 35, count 2 2006.257.06:49:08.79#ibcon#first serial, iclass 35, count 2 2006.257.06:49:08.79#ibcon#enter sib2, iclass 35, count 2 2006.257.06:49:08.79#ibcon#flushed, iclass 35, count 2 2006.257.06:49:08.79#ibcon#about to write, iclass 35, count 2 2006.257.06:49:08.79#ibcon#wrote, iclass 35, count 2 2006.257.06:49:08.79#ibcon#about to read 3, iclass 35, count 2 2006.257.06:49:08.81#ibcon#read 3, iclass 35, count 2 2006.257.06:49:08.81#ibcon#about to read 4, iclass 35, count 2 2006.257.06:49:08.81#ibcon#read 4, iclass 35, count 2 2006.257.06:49:08.81#ibcon#about to read 5, iclass 35, count 2 2006.257.06:49:08.81#ibcon#read 5, iclass 35, count 2 2006.257.06:49:08.81#ibcon#about to read 6, iclass 35, count 2 2006.257.06:49:08.81#ibcon#read 6, iclass 35, count 2 2006.257.06:49:08.81#ibcon#end of sib2, iclass 35, count 2 2006.257.06:49:08.81#ibcon#*mode == 0, iclass 35, count 2 2006.257.06:49:08.81#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.06:49:08.81#ibcon#[25=AT08-04\r\n] 2006.257.06:49:08.81#ibcon#*before write, iclass 35, count 2 2006.257.06:49:08.81#ibcon#enter sib2, iclass 35, count 2 2006.257.06:49:08.81#ibcon#flushed, iclass 35, count 2 2006.257.06:49:08.81#ibcon#about to write, iclass 35, count 2 2006.257.06:49:08.81#ibcon#wrote, iclass 35, count 2 2006.257.06:49:08.81#ibcon#about to read 3, iclass 35, count 2 2006.257.06:49:08.84#ibcon#read 3, iclass 35, count 2 2006.257.06:49:08.84#ibcon#about to read 4, iclass 35, count 2 2006.257.06:49:08.84#ibcon#read 4, iclass 35, count 2 2006.257.06:49:08.84#ibcon#about to read 5, iclass 35, count 2 2006.257.06:49:08.84#ibcon#read 5, iclass 35, count 2 2006.257.06:49:08.84#ibcon#about to read 6, iclass 35, count 2 2006.257.06:49:08.84#ibcon#read 6, iclass 35, count 2 2006.257.06:49:08.84#ibcon#end of sib2, iclass 35, count 2 2006.257.06:49:08.84#ibcon#*after write, iclass 35, count 2 2006.257.06:49:08.84#ibcon#*before return 0, iclass 35, count 2 2006.257.06:49:08.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:49:08.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.06:49:08.84#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.06:49:08.84#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:08.84#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:49:08.96#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:49:08.96#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:49:08.96#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:49:08.96#ibcon#first serial, iclass 35, count 0 2006.257.06:49:08.96#ibcon#enter sib2, iclass 35, count 0 2006.257.06:49:08.96#ibcon#flushed, iclass 35, count 0 2006.257.06:49:08.96#ibcon#about to write, iclass 35, count 0 2006.257.06:49:08.96#ibcon#wrote, iclass 35, count 0 2006.257.06:49:08.96#ibcon#about to read 3, iclass 35, count 0 2006.257.06:49:08.98#ibcon#read 3, iclass 35, count 0 2006.257.06:49:08.98#ibcon#about to read 4, iclass 35, count 0 2006.257.06:49:08.98#ibcon#read 4, iclass 35, count 0 2006.257.06:49:08.98#ibcon#about to read 5, iclass 35, count 0 2006.257.06:49:08.98#ibcon#read 5, iclass 35, count 0 2006.257.06:49:08.98#ibcon#about to read 6, iclass 35, count 0 2006.257.06:49:08.98#ibcon#read 6, iclass 35, count 0 2006.257.06:49:08.98#ibcon#end of sib2, iclass 35, count 0 2006.257.06:49:08.98#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:49:08.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:49:08.98#ibcon#[25=USB\r\n] 2006.257.06:49:08.98#ibcon#*before write, iclass 35, count 0 2006.257.06:49:08.98#ibcon#enter sib2, iclass 35, count 0 2006.257.06:49:08.98#ibcon#flushed, iclass 35, count 0 2006.257.06:49:08.98#ibcon#about to write, iclass 35, count 0 2006.257.06:49:08.98#ibcon#wrote, iclass 35, count 0 2006.257.06:49:08.98#ibcon#about to read 3, iclass 35, count 0 2006.257.06:49:09.01#ibcon#read 3, iclass 35, count 0 2006.257.06:49:09.01#ibcon#about to read 4, iclass 35, count 0 2006.257.06:49:09.01#ibcon#read 4, iclass 35, count 0 2006.257.06:49:09.01#ibcon#about to read 5, iclass 35, count 0 2006.257.06:49:09.01#ibcon#read 5, iclass 35, count 0 2006.257.06:49:09.01#ibcon#about to read 6, iclass 35, count 0 2006.257.06:49:09.01#ibcon#read 6, iclass 35, count 0 2006.257.06:49:09.01#ibcon#end of sib2, iclass 35, count 0 2006.257.06:49:09.01#ibcon#*after write, iclass 35, count 0 2006.257.06:49:09.01#ibcon#*before return 0, iclass 35, count 0 2006.257.06:49:09.01#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:49:09.01#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.06:49:09.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:49:09.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:49:09.01$vck44/vblo=1,629.99 2006.257.06:49:09.01#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.06:49:09.01#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.06:49:09.01#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:09.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:49:09.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:49:09.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:49:09.01#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:49:09.01#ibcon#first serial, iclass 37, count 0 2006.257.06:49:09.01#ibcon#enter sib2, iclass 37, count 0 2006.257.06:49:09.01#ibcon#flushed, iclass 37, count 0 2006.257.06:49:09.01#ibcon#about to write, iclass 37, count 0 2006.257.06:49:09.01#ibcon#wrote, iclass 37, count 0 2006.257.06:49:09.01#ibcon#about to read 3, iclass 37, count 0 2006.257.06:49:09.03#ibcon#read 3, iclass 37, count 0 2006.257.06:49:09.03#ibcon#about to read 4, iclass 37, count 0 2006.257.06:49:09.03#ibcon#read 4, iclass 37, count 0 2006.257.06:49:09.03#ibcon#about to read 5, iclass 37, count 0 2006.257.06:49:09.03#ibcon#read 5, iclass 37, count 0 2006.257.06:49:09.03#ibcon#about to read 6, iclass 37, count 0 2006.257.06:49:09.03#ibcon#read 6, iclass 37, count 0 2006.257.06:49:09.03#ibcon#end of sib2, iclass 37, count 0 2006.257.06:49:09.03#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:49:09.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:49:09.03#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:49:09.03#ibcon#*before write, iclass 37, count 0 2006.257.06:49:09.03#ibcon#enter sib2, iclass 37, count 0 2006.257.06:49:09.03#ibcon#flushed, iclass 37, count 0 2006.257.06:49:09.03#ibcon#about to write, iclass 37, count 0 2006.257.06:49:09.03#ibcon#wrote, iclass 37, count 0 2006.257.06:49:09.03#ibcon#about to read 3, iclass 37, count 0 2006.257.06:49:09.07#ibcon#read 3, iclass 37, count 0 2006.257.06:49:09.07#ibcon#about to read 4, iclass 37, count 0 2006.257.06:49:09.07#ibcon#read 4, iclass 37, count 0 2006.257.06:49:09.07#ibcon#about to read 5, iclass 37, count 0 2006.257.06:49:09.07#ibcon#read 5, iclass 37, count 0 2006.257.06:49:09.07#ibcon#about to read 6, iclass 37, count 0 2006.257.06:49:09.07#ibcon#read 6, iclass 37, count 0 2006.257.06:49:09.07#ibcon#end of sib2, iclass 37, count 0 2006.257.06:49:09.07#ibcon#*after write, iclass 37, count 0 2006.257.06:49:09.07#ibcon#*before return 0, iclass 37, count 0 2006.257.06:49:09.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:49:09.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.06:49:09.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:49:09.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:49:09.07$vck44/vb=1,4 2006.257.06:49:09.07#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.06:49:09.07#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.06:49:09.07#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:09.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:49:09.07#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:49:09.07#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:49:09.07#ibcon#enter wrdev, iclass 39, count 2 2006.257.06:49:09.07#ibcon#first serial, iclass 39, count 2 2006.257.06:49:09.07#ibcon#enter sib2, iclass 39, count 2 2006.257.06:49:09.07#ibcon#flushed, iclass 39, count 2 2006.257.06:49:09.07#ibcon#about to write, iclass 39, count 2 2006.257.06:49:09.07#ibcon#wrote, iclass 39, count 2 2006.257.06:49:09.07#ibcon#about to read 3, iclass 39, count 2 2006.257.06:49:09.09#ibcon#read 3, iclass 39, count 2 2006.257.06:49:09.09#ibcon#about to read 4, iclass 39, count 2 2006.257.06:49:09.09#ibcon#read 4, iclass 39, count 2 2006.257.06:49:09.09#ibcon#about to read 5, iclass 39, count 2 2006.257.06:49:09.09#ibcon#read 5, iclass 39, count 2 2006.257.06:49:09.09#ibcon#about to read 6, iclass 39, count 2 2006.257.06:49:09.09#ibcon#read 6, iclass 39, count 2 2006.257.06:49:09.09#ibcon#end of sib2, iclass 39, count 2 2006.257.06:49:09.09#ibcon#*mode == 0, iclass 39, count 2 2006.257.06:49:09.09#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.06:49:09.09#ibcon#[27=AT01-04\r\n] 2006.257.06:49:09.09#ibcon#*before write, iclass 39, count 2 2006.257.06:49:09.09#ibcon#enter sib2, iclass 39, count 2 2006.257.06:49:09.09#ibcon#flushed, iclass 39, count 2 2006.257.06:49:09.09#ibcon#about to write, iclass 39, count 2 2006.257.06:49:09.09#ibcon#wrote, iclass 39, count 2 2006.257.06:49:09.09#ibcon#about to read 3, iclass 39, count 2 2006.257.06:49:09.12#ibcon#read 3, iclass 39, count 2 2006.257.06:49:09.12#ibcon#about to read 4, iclass 39, count 2 2006.257.06:49:09.12#ibcon#read 4, iclass 39, count 2 2006.257.06:49:09.12#ibcon#about to read 5, iclass 39, count 2 2006.257.06:49:09.12#ibcon#read 5, iclass 39, count 2 2006.257.06:49:09.12#ibcon#about to read 6, iclass 39, count 2 2006.257.06:49:09.12#ibcon#read 6, iclass 39, count 2 2006.257.06:49:09.12#ibcon#end of sib2, iclass 39, count 2 2006.257.06:49:09.12#ibcon#*after write, iclass 39, count 2 2006.257.06:49:09.12#ibcon#*before return 0, iclass 39, count 2 2006.257.06:49:09.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:49:09.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.06:49:09.12#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.06:49:09.12#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:09.12#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:49:09.24#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:49:09.24#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:49:09.24#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:49:09.24#ibcon#first serial, iclass 39, count 0 2006.257.06:49:09.24#ibcon#enter sib2, iclass 39, count 0 2006.257.06:49:09.24#ibcon#flushed, iclass 39, count 0 2006.257.06:49:09.24#ibcon#about to write, iclass 39, count 0 2006.257.06:49:09.24#ibcon#wrote, iclass 39, count 0 2006.257.06:49:09.24#ibcon#about to read 3, iclass 39, count 0 2006.257.06:49:09.26#ibcon#read 3, iclass 39, count 0 2006.257.06:49:09.26#ibcon#about to read 4, iclass 39, count 0 2006.257.06:49:09.26#ibcon#read 4, iclass 39, count 0 2006.257.06:49:09.26#ibcon#about to read 5, iclass 39, count 0 2006.257.06:49:09.26#ibcon#read 5, iclass 39, count 0 2006.257.06:49:09.26#ibcon#about to read 6, iclass 39, count 0 2006.257.06:49:09.26#ibcon#read 6, iclass 39, count 0 2006.257.06:49:09.26#ibcon#end of sib2, iclass 39, count 0 2006.257.06:49:09.26#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:49:09.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:49:09.26#ibcon#[27=USB\r\n] 2006.257.06:49:09.26#ibcon#*before write, iclass 39, count 0 2006.257.06:49:09.26#ibcon#enter sib2, iclass 39, count 0 2006.257.06:49:09.26#ibcon#flushed, iclass 39, count 0 2006.257.06:49:09.26#ibcon#about to write, iclass 39, count 0 2006.257.06:49:09.26#ibcon#wrote, iclass 39, count 0 2006.257.06:49:09.26#ibcon#about to read 3, iclass 39, count 0 2006.257.06:49:09.29#ibcon#read 3, iclass 39, count 0 2006.257.06:49:09.29#ibcon#about to read 4, iclass 39, count 0 2006.257.06:49:09.29#ibcon#read 4, iclass 39, count 0 2006.257.06:49:09.29#ibcon#about to read 5, iclass 39, count 0 2006.257.06:49:09.29#ibcon#read 5, iclass 39, count 0 2006.257.06:49:09.29#ibcon#about to read 6, iclass 39, count 0 2006.257.06:49:09.29#ibcon#read 6, iclass 39, count 0 2006.257.06:49:09.29#ibcon#end of sib2, iclass 39, count 0 2006.257.06:49:09.29#ibcon#*after write, iclass 39, count 0 2006.257.06:49:09.29#ibcon#*before return 0, iclass 39, count 0 2006.257.06:49:09.29#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:49:09.29#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.06:49:09.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:49:09.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:49:09.29$vck44/vblo=2,634.99 2006.257.06:49:09.29#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.06:49:09.29#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.06:49:09.29#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:09.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:09.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:09.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:09.29#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:49:09.29#ibcon#first serial, iclass 3, count 0 2006.257.06:49:09.29#ibcon#enter sib2, iclass 3, count 0 2006.257.06:49:09.29#ibcon#flushed, iclass 3, count 0 2006.257.06:49:09.29#ibcon#about to write, iclass 3, count 0 2006.257.06:49:09.29#ibcon#wrote, iclass 3, count 0 2006.257.06:49:09.29#ibcon#about to read 3, iclass 3, count 0 2006.257.06:49:09.31#ibcon#read 3, iclass 3, count 0 2006.257.06:49:09.31#ibcon#about to read 4, iclass 3, count 0 2006.257.06:49:09.31#ibcon#read 4, iclass 3, count 0 2006.257.06:49:09.31#ibcon#about to read 5, iclass 3, count 0 2006.257.06:49:09.31#ibcon#read 5, iclass 3, count 0 2006.257.06:49:09.31#ibcon#about to read 6, iclass 3, count 0 2006.257.06:49:09.31#ibcon#read 6, iclass 3, count 0 2006.257.06:49:09.31#ibcon#end of sib2, iclass 3, count 0 2006.257.06:49:09.31#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:49:09.31#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:49:09.31#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:49:09.31#ibcon#*before write, iclass 3, count 0 2006.257.06:49:09.31#ibcon#enter sib2, iclass 3, count 0 2006.257.06:49:09.31#ibcon#flushed, iclass 3, count 0 2006.257.06:49:09.31#ibcon#about to write, iclass 3, count 0 2006.257.06:49:09.31#ibcon#wrote, iclass 3, count 0 2006.257.06:49:09.31#ibcon#about to read 3, iclass 3, count 0 2006.257.06:49:09.35#ibcon#read 3, iclass 3, count 0 2006.257.06:49:09.35#ibcon#about to read 4, iclass 3, count 0 2006.257.06:49:09.35#ibcon#read 4, iclass 3, count 0 2006.257.06:49:09.35#ibcon#about to read 5, iclass 3, count 0 2006.257.06:49:09.35#ibcon#read 5, iclass 3, count 0 2006.257.06:49:09.35#ibcon#about to read 6, iclass 3, count 0 2006.257.06:49:09.35#ibcon#read 6, iclass 3, count 0 2006.257.06:49:09.35#ibcon#end of sib2, iclass 3, count 0 2006.257.06:49:09.35#ibcon#*after write, iclass 3, count 0 2006.257.06:49:09.35#ibcon#*before return 0, iclass 3, count 0 2006.257.06:49:09.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:09.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.06:49:09.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:49:09.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:49:09.35$vck44/vb=2,5 2006.257.06:49:09.35#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.06:49:09.35#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.06:49:09.35#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:09.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:09.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:09.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:09.41#ibcon#enter wrdev, iclass 5, count 2 2006.257.06:49:09.41#ibcon#first serial, iclass 5, count 2 2006.257.06:49:09.41#ibcon#enter sib2, iclass 5, count 2 2006.257.06:49:09.41#ibcon#flushed, iclass 5, count 2 2006.257.06:49:09.41#ibcon#about to write, iclass 5, count 2 2006.257.06:49:09.41#ibcon#wrote, iclass 5, count 2 2006.257.06:49:09.41#ibcon#about to read 3, iclass 5, count 2 2006.257.06:49:09.43#ibcon#read 3, iclass 5, count 2 2006.257.06:49:09.43#ibcon#about to read 4, iclass 5, count 2 2006.257.06:49:09.43#ibcon#read 4, iclass 5, count 2 2006.257.06:49:09.43#ibcon#about to read 5, iclass 5, count 2 2006.257.06:49:09.43#ibcon#read 5, iclass 5, count 2 2006.257.06:49:09.43#ibcon#about to read 6, iclass 5, count 2 2006.257.06:49:09.43#ibcon#read 6, iclass 5, count 2 2006.257.06:49:09.43#ibcon#end of sib2, iclass 5, count 2 2006.257.06:49:09.43#ibcon#*mode == 0, iclass 5, count 2 2006.257.06:49:09.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.06:49:09.43#ibcon#[27=AT02-05\r\n] 2006.257.06:49:09.43#ibcon#*before write, iclass 5, count 2 2006.257.06:49:09.43#ibcon#enter sib2, iclass 5, count 2 2006.257.06:49:09.43#ibcon#flushed, iclass 5, count 2 2006.257.06:49:09.43#ibcon#about to write, iclass 5, count 2 2006.257.06:49:09.43#ibcon#wrote, iclass 5, count 2 2006.257.06:49:09.43#ibcon#about to read 3, iclass 5, count 2 2006.257.06:49:09.46#ibcon#read 3, iclass 5, count 2 2006.257.06:49:09.46#ibcon#about to read 4, iclass 5, count 2 2006.257.06:49:09.46#ibcon#read 4, iclass 5, count 2 2006.257.06:49:09.46#ibcon#about to read 5, iclass 5, count 2 2006.257.06:49:09.46#ibcon#read 5, iclass 5, count 2 2006.257.06:49:09.46#ibcon#about to read 6, iclass 5, count 2 2006.257.06:49:09.46#ibcon#read 6, iclass 5, count 2 2006.257.06:49:09.46#ibcon#end of sib2, iclass 5, count 2 2006.257.06:49:09.46#ibcon#*after write, iclass 5, count 2 2006.257.06:49:09.46#ibcon#*before return 0, iclass 5, count 2 2006.257.06:49:09.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:09.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.06:49:09.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.06:49:09.46#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:09.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:09.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:09.58#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:09.58#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:49:09.58#ibcon#first serial, iclass 5, count 0 2006.257.06:49:09.58#ibcon#enter sib2, iclass 5, count 0 2006.257.06:49:09.58#ibcon#flushed, iclass 5, count 0 2006.257.06:49:09.58#ibcon#about to write, iclass 5, count 0 2006.257.06:49:09.58#ibcon#wrote, iclass 5, count 0 2006.257.06:49:09.58#ibcon#about to read 3, iclass 5, count 0 2006.257.06:49:09.60#ibcon#read 3, iclass 5, count 0 2006.257.06:49:09.60#ibcon#about to read 4, iclass 5, count 0 2006.257.06:49:09.60#ibcon#read 4, iclass 5, count 0 2006.257.06:49:09.60#ibcon#about to read 5, iclass 5, count 0 2006.257.06:49:09.60#ibcon#read 5, iclass 5, count 0 2006.257.06:49:09.60#ibcon#about to read 6, iclass 5, count 0 2006.257.06:49:09.60#ibcon#read 6, iclass 5, count 0 2006.257.06:49:09.60#ibcon#end of sib2, iclass 5, count 0 2006.257.06:49:09.60#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:49:09.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:49:09.60#ibcon#[27=USB\r\n] 2006.257.06:49:09.60#ibcon#*before write, iclass 5, count 0 2006.257.06:49:09.60#ibcon#enter sib2, iclass 5, count 0 2006.257.06:49:09.60#ibcon#flushed, iclass 5, count 0 2006.257.06:49:09.60#ibcon#about to write, iclass 5, count 0 2006.257.06:49:09.60#ibcon#wrote, iclass 5, count 0 2006.257.06:49:09.60#ibcon#about to read 3, iclass 5, count 0 2006.257.06:49:09.63#ibcon#read 3, iclass 5, count 0 2006.257.06:49:09.63#ibcon#about to read 4, iclass 5, count 0 2006.257.06:49:09.63#ibcon#read 4, iclass 5, count 0 2006.257.06:49:09.63#ibcon#about to read 5, iclass 5, count 0 2006.257.06:49:09.63#ibcon#read 5, iclass 5, count 0 2006.257.06:49:09.63#ibcon#about to read 6, iclass 5, count 0 2006.257.06:49:09.63#ibcon#read 6, iclass 5, count 0 2006.257.06:49:09.63#ibcon#end of sib2, iclass 5, count 0 2006.257.06:49:09.63#ibcon#*after write, iclass 5, count 0 2006.257.06:49:09.63#ibcon#*before return 0, iclass 5, count 0 2006.257.06:49:09.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:09.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.06:49:09.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:49:09.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:49:09.63$vck44/vblo=3,649.99 2006.257.06:49:09.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.06:49:09.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.06:49:09.63#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:09.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:09.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:09.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:09.63#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:49:09.63#ibcon#first serial, iclass 7, count 0 2006.257.06:49:09.63#ibcon#enter sib2, iclass 7, count 0 2006.257.06:49:09.63#ibcon#flushed, iclass 7, count 0 2006.257.06:49:09.63#ibcon#about to write, iclass 7, count 0 2006.257.06:49:09.63#ibcon#wrote, iclass 7, count 0 2006.257.06:49:09.63#ibcon#about to read 3, iclass 7, count 0 2006.257.06:49:09.65#ibcon#read 3, iclass 7, count 0 2006.257.06:49:09.65#ibcon#about to read 4, iclass 7, count 0 2006.257.06:49:09.65#ibcon#read 4, iclass 7, count 0 2006.257.06:49:09.65#ibcon#about to read 5, iclass 7, count 0 2006.257.06:49:09.65#ibcon#read 5, iclass 7, count 0 2006.257.06:49:09.65#ibcon#about to read 6, iclass 7, count 0 2006.257.06:49:09.65#ibcon#read 6, iclass 7, count 0 2006.257.06:49:09.65#ibcon#end of sib2, iclass 7, count 0 2006.257.06:49:09.65#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:49:09.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:49:09.65#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:49:09.65#ibcon#*before write, iclass 7, count 0 2006.257.06:49:09.65#ibcon#enter sib2, iclass 7, count 0 2006.257.06:49:09.65#ibcon#flushed, iclass 7, count 0 2006.257.06:49:09.65#ibcon#about to write, iclass 7, count 0 2006.257.06:49:09.65#ibcon#wrote, iclass 7, count 0 2006.257.06:49:09.65#ibcon#about to read 3, iclass 7, count 0 2006.257.06:49:09.69#ibcon#read 3, iclass 7, count 0 2006.257.06:49:09.69#ibcon#about to read 4, iclass 7, count 0 2006.257.06:49:09.69#ibcon#read 4, iclass 7, count 0 2006.257.06:49:09.69#ibcon#about to read 5, iclass 7, count 0 2006.257.06:49:09.69#ibcon#read 5, iclass 7, count 0 2006.257.06:49:09.69#ibcon#about to read 6, iclass 7, count 0 2006.257.06:49:09.69#ibcon#read 6, iclass 7, count 0 2006.257.06:49:09.69#ibcon#end of sib2, iclass 7, count 0 2006.257.06:49:09.69#ibcon#*after write, iclass 7, count 0 2006.257.06:49:09.69#ibcon#*before return 0, iclass 7, count 0 2006.257.06:49:09.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:09.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.06:49:09.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:49:09.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:49:09.69$vck44/vb=3,4 2006.257.06:49:09.69#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.06:49:09.69#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.06:49:09.69#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:09.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:09.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:09.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:09.75#ibcon#enter wrdev, iclass 11, count 2 2006.257.06:49:09.75#ibcon#first serial, iclass 11, count 2 2006.257.06:49:09.75#ibcon#enter sib2, iclass 11, count 2 2006.257.06:49:09.75#ibcon#flushed, iclass 11, count 2 2006.257.06:49:09.75#ibcon#about to write, iclass 11, count 2 2006.257.06:49:09.75#ibcon#wrote, iclass 11, count 2 2006.257.06:49:09.75#ibcon#about to read 3, iclass 11, count 2 2006.257.06:49:09.77#ibcon#read 3, iclass 11, count 2 2006.257.06:49:09.77#ibcon#about to read 4, iclass 11, count 2 2006.257.06:49:09.77#ibcon#read 4, iclass 11, count 2 2006.257.06:49:09.77#ibcon#about to read 5, iclass 11, count 2 2006.257.06:49:09.77#ibcon#read 5, iclass 11, count 2 2006.257.06:49:09.77#ibcon#about to read 6, iclass 11, count 2 2006.257.06:49:09.77#ibcon#read 6, iclass 11, count 2 2006.257.06:49:09.77#ibcon#end of sib2, iclass 11, count 2 2006.257.06:49:09.77#ibcon#*mode == 0, iclass 11, count 2 2006.257.06:49:09.77#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.06:49:09.77#ibcon#[27=AT03-04\r\n] 2006.257.06:49:09.77#ibcon#*before write, iclass 11, count 2 2006.257.06:49:09.77#ibcon#enter sib2, iclass 11, count 2 2006.257.06:49:09.77#ibcon#flushed, iclass 11, count 2 2006.257.06:49:09.77#ibcon#about to write, iclass 11, count 2 2006.257.06:49:09.77#ibcon#wrote, iclass 11, count 2 2006.257.06:49:09.77#ibcon#about to read 3, iclass 11, count 2 2006.257.06:49:09.80#ibcon#read 3, iclass 11, count 2 2006.257.06:49:09.80#ibcon#about to read 4, iclass 11, count 2 2006.257.06:49:09.80#ibcon#read 4, iclass 11, count 2 2006.257.06:49:09.80#ibcon#about to read 5, iclass 11, count 2 2006.257.06:49:09.80#ibcon#read 5, iclass 11, count 2 2006.257.06:49:09.80#ibcon#about to read 6, iclass 11, count 2 2006.257.06:49:09.80#ibcon#read 6, iclass 11, count 2 2006.257.06:49:09.80#ibcon#end of sib2, iclass 11, count 2 2006.257.06:49:09.80#ibcon#*after write, iclass 11, count 2 2006.257.06:49:09.80#ibcon#*before return 0, iclass 11, count 2 2006.257.06:49:09.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:09.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.06:49:09.80#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.06:49:09.80#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:09.80#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:09.92#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:09.92#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:09.92#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:49:09.92#ibcon#first serial, iclass 11, count 0 2006.257.06:49:09.92#ibcon#enter sib2, iclass 11, count 0 2006.257.06:49:09.92#ibcon#flushed, iclass 11, count 0 2006.257.06:49:09.92#ibcon#about to write, iclass 11, count 0 2006.257.06:49:09.92#ibcon#wrote, iclass 11, count 0 2006.257.06:49:09.92#ibcon#about to read 3, iclass 11, count 0 2006.257.06:49:09.94#ibcon#read 3, iclass 11, count 0 2006.257.06:49:09.94#ibcon#about to read 4, iclass 11, count 0 2006.257.06:49:09.94#ibcon#read 4, iclass 11, count 0 2006.257.06:49:09.94#ibcon#about to read 5, iclass 11, count 0 2006.257.06:49:09.94#ibcon#read 5, iclass 11, count 0 2006.257.06:49:09.94#ibcon#about to read 6, iclass 11, count 0 2006.257.06:49:09.94#ibcon#read 6, iclass 11, count 0 2006.257.06:49:09.94#ibcon#end of sib2, iclass 11, count 0 2006.257.06:49:09.94#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:49:09.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:49:09.94#ibcon#[27=USB\r\n] 2006.257.06:49:09.94#ibcon#*before write, iclass 11, count 0 2006.257.06:49:09.94#ibcon#enter sib2, iclass 11, count 0 2006.257.06:49:09.94#ibcon#flushed, iclass 11, count 0 2006.257.06:49:09.94#ibcon#about to write, iclass 11, count 0 2006.257.06:49:09.94#ibcon#wrote, iclass 11, count 0 2006.257.06:49:09.94#ibcon#about to read 3, iclass 11, count 0 2006.257.06:49:09.97#ibcon#read 3, iclass 11, count 0 2006.257.06:49:09.97#ibcon#about to read 4, iclass 11, count 0 2006.257.06:49:09.97#ibcon#read 4, iclass 11, count 0 2006.257.06:49:09.97#ibcon#about to read 5, iclass 11, count 0 2006.257.06:49:09.97#ibcon#read 5, iclass 11, count 0 2006.257.06:49:09.97#ibcon#about to read 6, iclass 11, count 0 2006.257.06:49:09.97#ibcon#read 6, iclass 11, count 0 2006.257.06:49:09.97#ibcon#end of sib2, iclass 11, count 0 2006.257.06:49:09.97#ibcon#*after write, iclass 11, count 0 2006.257.06:49:09.97#ibcon#*before return 0, iclass 11, count 0 2006.257.06:49:09.97#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:09.97#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.06:49:09.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:49:09.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:49:09.97$vck44/vblo=4,679.99 2006.257.06:49:09.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.06:49:09.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.06:49:09.97#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:09.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:09.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:09.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:09.97#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:49:09.97#ibcon#first serial, iclass 13, count 0 2006.257.06:49:09.97#ibcon#enter sib2, iclass 13, count 0 2006.257.06:49:09.97#ibcon#flushed, iclass 13, count 0 2006.257.06:49:09.97#ibcon#about to write, iclass 13, count 0 2006.257.06:49:09.97#ibcon#wrote, iclass 13, count 0 2006.257.06:49:09.97#ibcon#about to read 3, iclass 13, count 0 2006.257.06:49:09.99#ibcon#read 3, iclass 13, count 0 2006.257.06:49:09.99#ibcon#about to read 4, iclass 13, count 0 2006.257.06:49:09.99#ibcon#read 4, iclass 13, count 0 2006.257.06:49:09.99#ibcon#about to read 5, iclass 13, count 0 2006.257.06:49:09.99#ibcon#read 5, iclass 13, count 0 2006.257.06:49:09.99#ibcon#about to read 6, iclass 13, count 0 2006.257.06:49:09.99#ibcon#read 6, iclass 13, count 0 2006.257.06:49:09.99#ibcon#end of sib2, iclass 13, count 0 2006.257.06:49:09.99#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:49:09.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:49:09.99#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:49:09.99#ibcon#*before write, iclass 13, count 0 2006.257.06:49:09.99#ibcon#enter sib2, iclass 13, count 0 2006.257.06:49:09.99#ibcon#flushed, iclass 13, count 0 2006.257.06:49:09.99#ibcon#about to write, iclass 13, count 0 2006.257.06:49:09.99#ibcon#wrote, iclass 13, count 0 2006.257.06:49:09.99#ibcon#about to read 3, iclass 13, count 0 2006.257.06:49:10.03#ibcon#read 3, iclass 13, count 0 2006.257.06:49:10.03#ibcon#about to read 4, iclass 13, count 0 2006.257.06:49:10.03#ibcon#read 4, iclass 13, count 0 2006.257.06:49:10.03#ibcon#about to read 5, iclass 13, count 0 2006.257.06:49:10.03#ibcon#read 5, iclass 13, count 0 2006.257.06:49:10.03#ibcon#about to read 6, iclass 13, count 0 2006.257.06:49:10.03#ibcon#read 6, iclass 13, count 0 2006.257.06:49:10.03#ibcon#end of sib2, iclass 13, count 0 2006.257.06:49:10.03#ibcon#*after write, iclass 13, count 0 2006.257.06:49:10.03#ibcon#*before return 0, iclass 13, count 0 2006.257.06:49:10.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:10.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.06:49:10.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:49:10.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:49:10.03$vck44/vb=4,5 2006.257.06:49:10.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.06:49:10.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.06:49:10.03#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:10.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:10.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:10.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:10.09#ibcon#enter wrdev, iclass 15, count 2 2006.257.06:49:10.09#ibcon#first serial, iclass 15, count 2 2006.257.06:49:10.09#ibcon#enter sib2, iclass 15, count 2 2006.257.06:49:10.09#ibcon#flushed, iclass 15, count 2 2006.257.06:49:10.09#ibcon#about to write, iclass 15, count 2 2006.257.06:49:10.09#ibcon#wrote, iclass 15, count 2 2006.257.06:49:10.09#ibcon#about to read 3, iclass 15, count 2 2006.257.06:49:10.11#ibcon#read 3, iclass 15, count 2 2006.257.06:49:10.11#ibcon#about to read 4, iclass 15, count 2 2006.257.06:49:10.11#ibcon#read 4, iclass 15, count 2 2006.257.06:49:10.11#ibcon#about to read 5, iclass 15, count 2 2006.257.06:49:10.11#ibcon#read 5, iclass 15, count 2 2006.257.06:49:10.11#ibcon#about to read 6, iclass 15, count 2 2006.257.06:49:10.11#ibcon#read 6, iclass 15, count 2 2006.257.06:49:10.11#ibcon#end of sib2, iclass 15, count 2 2006.257.06:49:10.11#ibcon#*mode == 0, iclass 15, count 2 2006.257.06:49:10.11#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.06:49:10.11#ibcon#[27=AT04-05\r\n] 2006.257.06:49:10.11#ibcon#*before write, iclass 15, count 2 2006.257.06:49:10.11#ibcon#enter sib2, iclass 15, count 2 2006.257.06:49:10.11#ibcon#flushed, iclass 15, count 2 2006.257.06:49:10.11#ibcon#about to write, iclass 15, count 2 2006.257.06:49:10.11#ibcon#wrote, iclass 15, count 2 2006.257.06:49:10.11#ibcon#about to read 3, iclass 15, count 2 2006.257.06:49:10.14#ibcon#read 3, iclass 15, count 2 2006.257.06:49:10.14#ibcon#about to read 4, iclass 15, count 2 2006.257.06:49:10.14#ibcon#read 4, iclass 15, count 2 2006.257.06:49:10.14#ibcon#about to read 5, iclass 15, count 2 2006.257.06:49:10.14#ibcon#read 5, iclass 15, count 2 2006.257.06:49:10.14#ibcon#about to read 6, iclass 15, count 2 2006.257.06:49:10.14#ibcon#read 6, iclass 15, count 2 2006.257.06:49:10.14#ibcon#end of sib2, iclass 15, count 2 2006.257.06:49:10.14#ibcon#*after write, iclass 15, count 2 2006.257.06:49:10.14#ibcon#*before return 0, iclass 15, count 2 2006.257.06:49:10.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:10.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.06:49:10.14#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.06:49:10.14#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:10.14#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:10.26#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:10.26#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:10.26#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:49:10.26#ibcon#first serial, iclass 15, count 0 2006.257.06:49:10.26#ibcon#enter sib2, iclass 15, count 0 2006.257.06:49:10.26#ibcon#flushed, iclass 15, count 0 2006.257.06:49:10.26#ibcon#about to write, iclass 15, count 0 2006.257.06:49:10.26#ibcon#wrote, iclass 15, count 0 2006.257.06:49:10.26#ibcon#about to read 3, iclass 15, count 0 2006.257.06:49:10.28#ibcon#read 3, iclass 15, count 0 2006.257.06:49:10.28#ibcon#about to read 4, iclass 15, count 0 2006.257.06:49:10.28#ibcon#read 4, iclass 15, count 0 2006.257.06:49:10.28#ibcon#about to read 5, iclass 15, count 0 2006.257.06:49:10.28#ibcon#read 5, iclass 15, count 0 2006.257.06:49:10.28#ibcon#about to read 6, iclass 15, count 0 2006.257.06:49:10.28#ibcon#read 6, iclass 15, count 0 2006.257.06:49:10.28#ibcon#end of sib2, iclass 15, count 0 2006.257.06:49:10.28#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:49:10.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:49:10.28#ibcon#[27=USB\r\n] 2006.257.06:49:10.28#ibcon#*before write, iclass 15, count 0 2006.257.06:49:10.28#ibcon#enter sib2, iclass 15, count 0 2006.257.06:49:10.28#ibcon#flushed, iclass 15, count 0 2006.257.06:49:10.28#ibcon#about to write, iclass 15, count 0 2006.257.06:49:10.28#ibcon#wrote, iclass 15, count 0 2006.257.06:49:10.28#ibcon#about to read 3, iclass 15, count 0 2006.257.06:49:10.31#ibcon#read 3, iclass 15, count 0 2006.257.06:49:10.31#ibcon#about to read 4, iclass 15, count 0 2006.257.06:49:10.31#ibcon#read 4, iclass 15, count 0 2006.257.06:49:10.31#ibcon#about to read 5, iclass 15, count 0 2006.257.06:49:10.31#ibcon#read 5, iclass 15, count 0 2006.257.06:49:10.31#ibcon#about to read 6, iclass 15, count 0 2006.257.06:49:10.31#ibcon#read 6, iclass 15, count 0 2006.257.06:49:10.31#ibcon#end of sib2, iclass 15, count 0 2006.257.06:49:10.31#ibcon#*after write, iclass 15, count 0 2006.257.06:49:10.31#ibcon#*before return 0, iclass 15, count 0 2006.257.06:49:10.31#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:10.31#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.06:49:10.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:49:10.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:49:10.31$vck44/vblo=5,709.99 2006.257.06:49:10.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.06:49:10.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.06:49:10.31#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:10.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:10.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:10.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:10.31#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:49:10.31#ibcon#first serial, iclass 17, count 0 2006.257.06:49:10.31#ibcon#enter sib2, iclass 17, count 0 2006.257.06:49:10.31#ibcon#flushed, iclass 17, count 0 2006.257.06:49:10.31#ibcon#about to write, iclass 17, count 0 2006.257.06:49:10.31#ibcon#wrote, iclass 17, count 0 2006.257.06:49:10.31#ibcon#about to read 3, iclass 17, count 0 2006.257.06:49:10.33#ibcon#read 3, iclass 17, count 0 2006.257.06:49:10.33#ibcon#about to read 4, iclass 17, count 0 2006.257.06:49:10.33#ibcon#read 4, iclass 17, count 0 2006.257.06:49:10.33#ibcon#about to read 5, iclass 17, count 0 2006.257.06:49:10.33#ibcon#read 5, iclass 17, count 0 2006.257.06:49:10.33#ibcon#about to read 6, iclass 17, count 0 2006.257.06:49:10.33#ibcon#read 6, iclass 17, count 0 2006.257.06:49:10.33#ibcon#end of sib2, iclass 17, count 0 2006.257.06:49:10.33#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:49:10.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:49:10.33#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:49:10.33#ibcon#*before write, iclass 17, count 0 2006.257.06:49:10.33#ibcon#enter sib2, iclass 17, count 0 2006.257.06:49:10.33#ibcon#flushed, iclass 17, count 0 2006.257.06:49:10.33#ibcon#about to write, iclass 17, count 0 2006.257.06:49:10.33#ibcon#wrote, iclass 17, count 0 2006.257.06:49:10.33#ibcon#about to read 3, iclass 17, count 0 2006.257.06:49:10.37#ibcon#read 3, iclass 17, count 0 2006.257.06:49:10.37#ibcon#about to read 4, iclass 17, count 0 2006.257.06:49:10.37#ibcon#read 4, iclass 17, count 0 2006.257.06:49:10.37#ibcon#about to read 5, iclass 17, count 0 2006.257.06:49:10.37#ibcon#read 5, iclass 17, count 0 2006.257.06:49:10.37#ibcon#about to read 6, iclass 17, count 0 2006.257.06:49:10.37#ibcon#read 6, iclass 17, count 0 2006.257.06:49:10.37#ibcon#end of sib2, iclass 17, count 0 2006.257.06:49:10.37#ibcon#*after write, iclass 17, count 0 2006.257.06:49:10.37#ibcon#*before return 0, iclass 17, count 0 2006.257.06:49:10.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:10.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.06:49:10.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:49:10.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:49:10.37$vck44/vb=5,4 2006.257.06:49:10.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.06:49:10.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.06:49:10.37#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:10.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:10.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:10.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:10.43#ibcon#enter wrdev, iclass 19, count 2 2006.257.06:49:10.43#ibcon#first serial, iclass 19, count 2 2006.257.06:49:10.43#ibcon#enter sib2, iclass 19, count 2 2006.257.06:49:10.43#ibcon#flushed, iclass 19, count 2 2006.257.06:49:10.43#ibcon#about to write, iclass 19, count 2 2006.257.06:49:10.43#ibcon#wrote, iclass 19, count 2 2006.257.06:49:10.43#ibcon#about to read 3, iclass 19, count 2 2006.257.06:49:10.45#ibcon#read 3, iclass 19, count 2 2006.257.06:49:10.45#ibcon#about to read 4, iclass 19, count 2 2006.257.06:49:10.45#ibcon#read 4, iclass 19, count 2 2006.257.06:49:10.45#ibcon#about to read 5, iclass 19, count 2 2006.257.06:49:10.45#ibcon#read 5, iclass 19, count 2 2006.257.06:49:10.45#ibcon#about to read 6, iclass 19, count 2 2006.257.06:49:10.45#ibcon#read 6, iclass 19, count 2 2006.257.06:49:10.45#ibcon#end of sib2, iclass 19, count 2 2006.257.06:49:10.45#ibcon#*mode == 0, iclass 19, count 2 2006.257.06:49:10.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.06:49:10.45#ibcon#[27=AT05-04\r\n] 2006.257.06:49:10.45#ibcon#*before write, iclass 19, count 2 2006.257.06:49:10.45#ibcon#enter sib2, iclass 19, count 2 2006.257.06:49:10.45#ibcon#flushed, iclass 19, count 2 2006.257.06:49:10.45#ibcon#about to write, iclass 19, count 2 2006.257.06:49:10.45#ibcon#wrote, iclass 19, count 2 2006.257.06:49:10.45#ibcon#about to read 3, iclass 19, count 2 2006.257.06:49:10.48#ibcon#read 3, iclass 19, count 2 2006.257.06:49:10.48#ibcon#about to read 4, iclass 19, count 2 2006.257.06:49:10.48#ibcon#read 4, iclass 19, count 2 2006.257.06:49:10.48#ibcon#about to read 5, iclass 19, count 2 2006.257.06:49:10.48#ibcon#read 5, iclass 19, count 2 2006.257.06:49:10.48#ibcon#about to read 6, iclass 19, count 2 2006.257.06:49:10.48#ibcon#read 6, iclass 19, count 2 2006.257.06:49:10.48#ibcon#end of sib2, iclass 19, count 2 2006.257.06:49:10.48#ibcon#*after write, iclass 19, count 2 2006.257.06:49:10.48#ibcon#*before return 0, iclass 19, count 2 2006.257.06:49:10.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:10.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.06:49:10.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.06:49:10.48#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:10.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:10.60#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:10.60#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:10.60#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:49:10.60#ibcon#first serial, iclass 19, count 0 2006.257.06:49:10.60#ibcon#enter sib2, iclass 19, count 0 2006.257.06:49:10.60#ibcon#flushed, iclass 19, count 0 2006.257.06:49:10.60#ibcon#about to write, iclass 19, count 0 2006.257.06:49:10.60#ibcon#wrote, iclass 19, count 0 2006.257.06:49:10.60#ibcon#about to read 3, iclass 19, count 0 2006.257.06:49:10.62#ibcon#read 3, iclass 19, count 0 2006.257.06:49:10.62#ibcon#about to read 4, iclass 19, count 0 2006.257.06:49:10.62#ibcon#read 4, iclass 19, count 0 2006.257.06:49:10.62#ibcon#about to read 5, iclass 19, count 0 2006.257.06:49:10.62#ibcon#read 5, iclass 19, count 0 2006.257.06:49:10.62#ibcon#about to read 6, iclass 19, count 0 2006.257.06:49:10.62#ibcon#read 6, iclass 19, count 0 2006.257.06:49:10.62#ibcon#end of sib2, iclass 19, count 0 2006.257.06:49:10.62#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:49:10.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:49:10.62#ibcon#[27=USB\r\n] 2006.257.06:49:10.62#ibcon#*before write, iclass 19, count 0 2006.257.06:49:10.62#ibcon#enter sib2, iclass 19, count 0 2006.257.06:49:10.62#ibcon#flushed, iclass 19, count 0 2006.257.06:49:10.62#ibcon#about to write, iclass 19, count 0 2006.257.06:49:10.62#ibcon#wrote, iclass 19, count 0 2006.257.06:49:10.62#ibcon#about to read 3, iclass 19, count 0 2006.257.06:49:10.65#ibcon#read 3, iclass 19, count 0 2006.257.06:49:10.65#ibcon#about to read 4, iclass 19, count 0 2006.257.06:49:10.65#ibcon#read 4, iclass 19, count 0 2006.257.06:49:10.65#ibcon#about to read 5, iclass 19, count 0 2006.257.06:49:10.65#ibcon#read 5, iclass 19, count 0 2006.257.06:49:10.65#ibcon#about to read 6, iclass 19, count 0 2006.257.06:49:10.65#ibcon#read 6, iclass 19, count 0 2006.257.06:49:10.65#ibcon#end of sib2, iclass 19, count 0 2006.257.06:49:10.65#ibcon#*after write, iclass 19, count 0 2006.257.06:49:10.65#ibcon#*before return 0, iclass 19, count 0 2006.257.06:49:10.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:10.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.06:49:10.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:49:10.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:49:10.65$vck44/vblo=6,719.99 2006.257.06:49:10.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.06:49:10.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.06:49:10.65#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:10.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:10.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:10.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:10.65#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:49:10.65#ibcon#first serial, iclass 21, count 0 2006.257.06:49:10.65#ibcon#enter sib2, iclass 21, count 0 2006.257.06:49:10.65#ibcon#flushed, iclass 21, count 0 2006.257.06:49:10.65#ibcon#about to write, iclass 21, count 0 2006.257.06:49:10.65#ibcon#wrote, iclass 21, count 0 2006.257.06:49:10.65#ibcon#about to read 3, iclass 21, count 0 2006.257.06:49:10.67#ibcon#read 3, iclass 21, count 0 2006.257.06:49:10.67#ibcon#about to read 4, iclass 21, count 0 2006.257.06:49:10.67#ibcon#read 4, iclass 21, count 0 2006.257.06:49:10.67#ibcon#about to read 5, iclass 21, count 0 2006.257.06:49:10.67#ibcon#read 5, iclass 21, count 0 2006.257.06:49:10.67#ibcon#about to read 6, iclass 21, count 0 2006.257.06:49:10.67#ibcon#read 6, iclass 21, count 0 2006.257.06:49:10.67#ibcon#end of sib2, iclass 21, count 0 2006.257.06:49:10.67#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:49:10.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:49:10.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:49:10.67#ibcon#*before write, iclass 21, count 0 2006.257.06:49:10.67#ibcon#enter sib2, iclass 21, count 0 2006.257.06:49:10.67#ibcon#flushed, iclass 21, count 0 2006.257.06:49:10.67#ibcon#about to write, iclass 21, count 0 2006.257.06:49:10.67#ibcon#wrote, iclass 21, count 0 2006.257.06:49:10.67#ibcon#about to read 3, iclass 21, count 0 2006.257.06:49:10.71#ibcon#read 3, iclass 21, count 0 2006.257.06:49:10.71#ibcon#about to read 4, iclass 21, count 0 2006.257.06:49:10.71#ibcon#read 4, iclass 21, count 0 2006.257.06:49:10.71#ibcon#about to read 5, iclass 21, count 0 2006.257.06:49:10.71#ibcon#read 5, iclass 21, count 0 2006.257.06:49:10.71#ibcon#about to read 6, iclass 21, count 0 2006.257.06:49:10.71#ibcon#read 6, iclass 21, count 0 2006.257.06:49:10.71#ibcon#end of sib2, iclass 21, count 0 2006.257.06:49:10.71#ibcon#*after write, iclass 21, count 0 2006.257.06:49:10.71#ibcon#*before return 0, iclass 21, count 0 2006.257.06:49:10.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:10.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.06:49:10.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:49:10.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:49:10.71$vck44/vb=6,4 2006.257.06:49:10.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.06:49:10.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.06:49:10.71#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:10.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:10.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:10.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:10.77#ibcon#enter wrdev, iclass 23, count 2 2006.257.06:49:10.77#ibcon#first serial, iclass 23, count 2 2006.257.06:49:10.77#ibcon#enter sib2, iclass 23, count 2 2006.257.06:49:10.77#ibcon#flushed, iclass 23, count 2 2006.257.06:49:10.77#ibcon#about to write, iclass 23, count 2 2006.257.06:49:10.77#ibcon#wrote, iclass 23, count 2 2006.257.06:49:10.77#ibcon#about to read 3, iclass 23, count 2 2006.257.06:49:10.79#ibcon#read 3, iclass 23, count 2 2006.257.06:49:10.79#ibcon#about to read 4, iclass 23, count 2 2006.257.06:49:10.79#ibcon#read 4, iclass 23, count 2 2006.257.06:49:10.79#ibcon#about to read 5, iclass 23, count 2 2006.257.06:49:10.79#ibcon#read 5, iclass 23, count 2 2006.257.06:49:10.79#ibcon#about to read 6, iclass 23, count 2 2006.257.06:49:10.79#ibcon#read 6, iclass 23, count 2 2006.257.06:49:10.79#ibcon#end of sib2, iclass 23, count 2 2006.257.06:49:10.79#ibcon#*mode == 0, iclass 23, count 2 2006.257.06:49:10.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.06:49:10.79#ibcon#[27=AT06-04\r\n] 2006.257.06:49:10.79#ibcon#*before write, iclass 23, count 2 2006.257.06:49:10.79#ibcon#enter sib2, iclass 23, count 2 2006.257.06:49:10.79#ibcon#flushed, iclass 23, count 2 2006.257.06:49:10.79#ibcon#about to write, iclass 23, count 2 2006.257.06:49:10.79#ibcon#wrote, iclass 23, count 2 2006.257.06:49:10.79#ibcon#about to read 3, iclass 23, count 2 2006.257.06:49:10.82#ibcon#read 3, iclass 23, count 2 2006.257.06:49:10.82#ibcon#about to read 4, iclass 23, count 2 2006.257.06:49:10.82#ibcon#read 4, iclass 23, count 2 2006.257.06:49:10.82#ibcon#about to read 5, iclass 23, count 2 2006.257.06:49:10.82#ibcon#read 5, iclass 23, count 2 2006.257.06:49:10.82#ibcon#about to read 6, iclass 23, count 2 2006.257.06:49:10.82#ibcon#read 6, iclass 23, count 2 2006.257.06:49:10.82#ibcon#end of sib2, iclass 23, count 2 2006.257.06:49:10.82#ibcon#*after write, iclass 23, count 2 2006.257.06:49:10.82#ibcon#*before return 0, iclass 23, count 2 2006.257.06:49:10.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:10.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.06:49:10.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.06:49:10.82#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:10.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:10.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:10.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:10.94#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:49:10.94#ibcon#first serial, iclass 23, count 0 2006.257.06:49:10.94#ibcon#enter sib2, iclass 23, count 0 2006.257.06:49:10.94#ibcon#flushed, iclass 23, count 0 2006.257.06:49:10.94#ibcon#about to write, iclass 23, count 0 2006.257.06:49:10.94#ibcon#wrote, iclass 23, count 0 2006.257.06:49:10.94#ibcon#about to read 3, iclass 23, count 0 2006.257.06:49:10.96#ibcon#read 3, iclass 23, count 0 2006.257.06:49:10.96#ibcon#about to read 4, iclass 23, count 0 2006.257.06:49:10.96#ibcon#read 4, iclass 23, count 0 2006.257.06:49:10.96#ibcon#about to read 5, iclass 23, count 0 2006.257.06:49:10.96#ibcon#read 5, iclass 23, count 0 2006.257.06:49:10.96#ibcon#about to read 6, iclass 23, count 0 2006.257.06:49:10.96#ibcon#read 6, iclass 23, count 0 2006.257.06:49:10.96#ibcon#end of sib2, iclass 23, count 0 2006.257.06:49:10.96#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:49:10.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:49:10.96#ibcon#[27=USB\r\n] 2006.257.06:49:10.96#ibcon#*before write, iclass 23, count 0 2006.257.06:49:10.96#ibcon#enter sib2, iclass 23, count 0 2006.257.06:49:10.96#ibcon#flushed, iclass 23, count 0 2006.257.06:49:10.96#ibcon#about to write, iclass 23, count 0 2006.257.06:49:10.96#ibcon#wrote, iclass 23, count 0 2006.257.06:49:10.96#ibcon#about to read 3, iclass 23, count 0 2006.257.06:49:10.99#ibcon#read 3, iclass 23, count 0 2006.257.06:49:10.99#ibcon#about to read 4, iclass 23, count 0 2006.257.06:49:10.99#ibcon#read 4, iclass 23, count 0 2006.257.06:49:10.99#ibcon#about to read 5, iclass 23, count 0 2006.257.06:49:10.99#ibcon#read 5, iclass 23, count 0 2006.257.06:49:10.99#ibcon#about to read 6, iclass 23, count 0 2006.257.06:49:10.99#ibcon#read 6, iclass 23, count 0 2006.257.06:49:10.99#ibcon#end of sib2, iclass 23, count 0 2006.257.06:49:10.99#ibcon#*after write, iclass 23, count 0 2006.257.06:49:10.99#ibcon#*before return 0, iclass 23, count 0 2006.257.06:49:10.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:10.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.06:49:10.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:49:10.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:49:10.99$vck44/vblo=7,734.99 2006.257.06:49:10.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.06:49:10.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.06:49:10.99#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:10.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:10.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:10.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:10.99#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:49:10.99#ibcon#first serial, iclass 25, count 0 2006.257.06:49:10.99#ibcon#enter sib2, iclass 25, count 0 2006.257.06:49:10.99#ibcon#flushed, iclass 25, count 0 2006.257.06:49:10.99#ibcon#about to write, iclass 25, count 0 2006.257.06:49:10.99#ibcon#wrote, iclass 25, count 0 2006.257.06:49:10.99#ibcon#about to read 3, iclass 25, count 0 2006.257.06:49:11.01#ibcon#read 3, iclass 25, count 0 2006.257.06:49:11.01#ibcon#about to read 4, iclass 25, count 0 2006.257.06:49:11.01#ibcon#read 4, iclass 25, count 0 2006.257.06:49:11.01#ibcon#about to read 5, iclass 25, count 0 2006.257.06:49:11.01#ibcon#read 5, iclass 25, count 0 2006.257.06:49:11.01#ibcon#about to read 6, iclass 25, count 0 2006.257.06:49:11.01#ibcon#read 6, iclass 25, count 0 2006.257.06:49:11.01#ibcon#end of sib2, iclass 25, count 0 2006.257.06:49:11.01#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:49:11.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:49:11.01#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:49:11.01#ibcon#*before write, iclass 25, count 0 2006.257.06:49:11.01#ibcon#enter sib2, iclass 25, count 0 2006.257.06:49:11.01#ibcon#flushed, iclass 25, count 0 2006.257.06:49:11.01#ibcon#about to write, iclass 25, count 0 2006.257.06:49:11.01#ibcon#wrote, iclass 25, count 0 2006.257.06:49:11.01#ibcon#about to read 3, iclass 25, count 0 2006.257.06:49:11.05#ibcon#read 3, iclass 25, count 0 2006.257.06:49:11.05#ibcon#about to read 4, iclass 25, count 0 2006.257.06:49:11.05#ibcon#read 4, iclass 25, count 0 2006.257.06:49:11.05#ibcon#about to read 5, iclass 25, count 0 2006.257.06:49:11.05#ibcon#read 5, iclass 25, count 0 2006.257.06:49:11.05#ibcon#about to read 6, iclass 25, count 0 2006.257.06:49:11.05#ibcon#read 6, iclass 25, count 0 2006.257.06:49:11.05#ibcon#end of sib2, iclass 25, count 0 2006.257.06:49:11.05#ibcon#*after write, iclass 25, count 0 2006.257.06:49:11.05#ibcon#*before return 0, iclass 25, count 0 2006.257.06:49:11.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:11.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.06:49:11.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:49:11.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:49:11.05$vck44/vb=7,4 2006.257.06:49:11.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.06:49:11.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.06:49:11.05#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:11.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:11.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:11.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:11.11#ibcon#enter wrdev, iclass 27, count 2 2006.257.06:49:11.11#ibcon#first serial, iclass 27, count 2 2006.257.06:49:11.11#ibcon#enter sib2, iclass 27, count 2 2006.257.06:49:11.11#ibcon#flushed, iclass 27, count 2 2006.257.06:49:11.11#ibcon#about to write, iclass 27, count 2 2006.257.06:49:11.11#ibcon#wrote, iclass 27, count 2 2006.257.06:49:11.11#ibcon#about to read 3, iclass 27, count 2 2006.257.06:49:11.13#ibcon#read 3, iclass 27, count 2 2006.257.06:49:11.13#ibcon#about to read 4, iclass 27, count 2 2006.257.06:49:11.13#ibcon#read 4, iclass 27, count 2 2006.257.06:49:11.13#ibcon#about to read 5, iclass 27, count 2 2006.257.06:49:11.13#ibcon#read 5, iclass 27, count 2 2006.257.06:49:11.13#ibcon#about to read 6, iclass 27, count 2 2006.257.06:49:11.13#ibcon#read 6, iclass 27, count 2 2006.257.06:49:11.13#ibcon#end of sib2, iclass 27, count 2 2006.257.06:49:11.13#ibcon#*mode == 0, iclass 27, count 2 2006.257.06:49:11.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.06:49:11.13#ibcon#[27=AT07-04\r\n] 2006.257.06:49:11.13#ibcon#*before write, iclass 27, count 2 2006.257.06:49:11.13#ibcon#enter sib2, iclass 27, count 2 2006.257.06:49:11.13#ibcon#flushed, iclass 27, count 2 2006.257.06:49:11.13#ibcon#about to write, iclass 27, count 2 2006.257.06:49:11.13#ibcon#wrote, iclass 27, count 2 2006.257.06:49:11.13#ibcon#about to read 3, iclass 27, count 2 2006.257.06:49:11.16#ibcon#read 3, iclass 27, count 2 2006.257.06:49:11.16#ibcon#about to read 4, iclass 27, count 2 2006.257.06:49:11.16#ibcon#read 4, iclass 27, count 2 2006.257.06:49:11.16#ibcon#about to read 5, iclass 27, count 2 2006.257.06:49:11.16#ibcon#read 5, iclass 27, count 2 2006.257.06:49:11.16#ibcon#about to read 6, iclass 27, count 2 2006.257.06:49:11.16#ibcon#read 6, iclass 27, count 2 2006.257.06:49:11.16#ibcon#end of sib2, iclass 27, count 2 2006.257.06:49:11.16#ibcon#*after write, iclass 27, count 2 2006.257.06:49:11.16#ibcon#*before return 0, iclass 27, count 2 2006.257.06:49:11.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:11.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.06:49:11.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.06:49:11.16#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:11.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:11.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:11.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:11.28#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:49:11.28#ibcon#first serial, iclass 27, count 0 2006.257.06:49:11.28#ibcon#enter sib2, iclass 27, count 0 2006.257.06:49:11.28#ibcon#flushed, iclass 27, count 0 2006.257.06:49:11.28#ibcon#about to write, iclass 27, count 0 2006.257.06:49:11.28#ibcon#wrote, iclass 27, count 0 2006.257.06:49:11.28#ibcon#about to read 3, iclass 27, count 0 2006.257.06:49:11.30#ibcon#read 3, iclass 27, count 0 2006.257.06:49:11.30#ibcon#about to read 4, iclass 27, count 0 2006.257.06:49:11.30#ibcon#read 4, iclass 27, count 0 2006.257.06:49:11.30#ibcon#about to read 5, iclass 27, count 0 2006.257.06:49:11.30#ibcon#read 5, iclass 27, count 0 2006.257.06:49:11.30#ibcon#about to read 6, iclass 27, count 0 2006.257.06:49:11.30#ibcon#read 6, iclass 27, count 0 2006.257.06:49:11.30#ibcon#end of sib2, iclass 27, count 0 2006.257.06:49:11.30#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:49:11.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:49:11.30#ibcon#[27=USB\r\n] 2006.257.06:49:11.30#ibcon#*before write, iclass 27, count 0 2006.257.06:49:11.30#ibcon#enter sib2, iclass 27, count 0 2006.257.06:49:11.30#ibcon#flushed, iclass 27, count 0 2006.257.06:49:11.30#ibcon#about to write, iclass 27, count 0 2006.257.06:49:11.30#ibcon#wrote, iclass 27, count 0 2006.257.06:49:11.30#ibcon#about to read 3, iclass 27, count 0 2006.257.06:49:11.33#ibcon#read 3, iclass 27, count 0 2006.257.06:49:11.33#ibcon#about to read 4, iclass 27, count 0 2006.257.06:49:11.33#ibcon#read 4, iclass 27, count 0 2006.257.06:49:11.33#ibcon#about to read 5, iclass 27, count 0 2006.257.06:49:11.33#ibcon#read 5, iclass 27, count 0 2006.257.06:49:11.33#ibcon#about to read 6, iclass 27, count 0 2006.257.06:49:11.33#ibcon#read 6, iclass 27, count 0 2006.257.06:49:11.33#ibcon#end of sib2, iclass 27, count 0 2006.257.06:49:11.33#ibcon#*after write, iclass 27, count 0 2006.257.06:49:11.33#ibcon#*before return 0, iclass 27, count 0 2006.257.06:49:11.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:11.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.06:49:11.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:49:11.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:49:11.33$vck44/vblo=8,744.99 2006.257.06:49:11.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.06:49:11.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.06:49:11.33#ibcon#ireg 17 cls_cnt 0 2006.257.06:49:11.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:11.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:11.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:11.33#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:49:11.33#ibcon#first serial, iclass 29, count 0 2006.257.06:49:11.33#ibcon#enter sib2, iclass 29, count 0 2006.257.06:49:11.33#ibcon#flushed, iclass 29, count 0 2006.257.06:49:11.33#ibcon#about to write, iclass 29, count 0 2006.257.06:49:11.33#ibcon#wrote, iclass 29, count 0 2006.257.06:49:11.33#ibcon#about to read 3, iclass 29, count 0 2006.257.06:49:11.35#ibcon#read 3, iclass 29, count 0 2006.257.06:49:11.35#ibcon#about to read 4, iclass 29, count 0 2006.257.06:49:11.35#ibcon#read 4, iclass 29, count 0 2006.257.06:49:11.35#ibcon#about to read 5, iclass 29, count 0 2006.257.06:49:11.35#ibcon#read 5, iclass 29, count 0 2006.257.06:49:11.35#ibcon#about to read 6, iclass 29, count 0 2006.257.06:49:11.35#ibcon#read 6, iclass 29, count 0 2006.257.06:49:11.35#ibcon#end of sib2, iclass 29, count 0 2006.257.06:49:11.35#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:49:11.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:49:11.35#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:49:11.35#ibcon#*before write, iclass 29, count 0 2006.257.06:49:11.35#ibcon#enter sib2, iclass 29, count 0 2006.257.06:49:11.35#ibcon#flushed, iclass 29, count 0 2006.257.06:49:11.35#ibcon#about to write, iclass 29, count 0 2006.257.06:49:11.35#ibcon#wrote, iclass 29, count 0 2006.257.06:49:11.35#ibcon#about to read 3, iclass 29, count 0 2006.257.06:49:11.39#ibcon#read 3, iclass 29, count 0 2006.257.06:49:11.39#ibcon#about to read 4, iclass 29, count 0 2006.257.06:49:11.39#ibcon#read 4, iclass 29, count 0 2006.257.06:49:11.39#ibcon#about to read 5, iclass 29, count 0 2006.257.06:49:11.39#ibcon#read 5, iclass 29, count 0 2006.257.06:49:11.39#ibcon#about to read 6, iclass 29, count 0 2006.257.06:49:11.39#ibcon#read 6, iclass 29, count 0 2006.257.06:49:11.39#ibcon#end of sib2, iclass 29, count 0 2006.257.06:49:11.39#ibcon#*after write, iclass 29, count 0 2006.257.06:49:11.39#ibcon#*before return 0, iclass 29, count 0 2006.257.06:49:11.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:11.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.06:49:11.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:49:11.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:49:11.39$vck44/vb=8,4 2006.257.06:49:11.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.06:49:11.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.06:49:11.39#ibcon#ireg 11 cls_cnt 2 2006.257.06:49:11.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:11.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:11.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:11.45#ibcon#enter wrdev, iclass 31, count 2 2006.257.06:49:11.45#ibcon#first serial, iclass 31, count 2 2006.257.06:49:11.45#ibcon#enter sib2, iclass 31, count 2 2006.257.06:49:11.45#ibcon#flushed, iclass 31, count 2 2006.257.06:49:11.45#ibcon#about to write, iclass 31, count 2 2006.257.06:49:11.45#ibcon#wrote, iclass 31, count 2 2006.257.06:49:11.45#ibcon#about to read 3, iclass 31, count 2 2006.257.06:49:11.47#ibcon#read 3, iclass 31, count 2 2006.257.06:49:11.47#ibcon#about to read 4, iclass 31, count 2 2006.257.06:49:11.47#ibcon#read 4, iclass 31, count 2 2006.257.06:49:11.47#ibcon#about to read 5, iclass 31, count 2 2006.257.06:49:11.47#ibcon#read 5, iclass 31, count 2 2006.257.06:49:11.47#ibcon#about to read 6, iclass 31, count 2 2006.257.06:49:11.47#ibcon#read 6, iclass 31, count 2 2006.257.06:49:11.47#ibcon#end of sib2, iclass 31, count 2 2006.257.06:49:11.47#ibcon#*mode == 0, iclass 31, count 2 2006.257.06:49:11.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.06:49:11.47#ibcon#[27=AT08-04\r\n] 2006.257.06:49:11.47#ibcon#*before write, iclass 31, count 2 2006.257.06:49:11.47#ibcon#enter sib2, iclass 31, count 2 2006.257.06:49:11.47#ibcon#flushed, iclass 31, count 2 2006.257.06:49:11.47#ibcon#about to write, iclass 31, count 2 2006.257.06:49:11.47#ibcon#wrote, iclass 31, count 2 2006.257.06:49:11.47#ibcon#about to read 3, iclass 31, count 2 2006.257.06:49:11.50#ibcon#read 3, iclass 31, count 2 2006.257.06:49:11.50#ibcon#about to read 4, iclass 31, count 2 2006.257.06:49:11.50#ibcon#read 4, iclass 31, count 2 2006.257.06:49:11.50#ibcon#about to read 5, iclass 31, count 2 2006.257.06:49:11.50#ibcon#read 5, iclass 31, count 2 2006.257.06:49:11.50#ibcon#about to read 6, iclass 31, count 2 2006.257.06:49:11.50#ibcon#read 6, iclass 31, count 2 2006.257.06:49:11.50#ibcon#end of sib2, iclass 31, count 2 2006.257.06:49:11.50#ibcon#*after write, iclass 31, count 2 2006.257.06:49:11.50#ibcon#*before return 0, iclass 31, count 2 2006.257.06:49:11.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:11.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.06:49:11.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.06:49:11.50#ibcon#ireg 7 cls_cnt 0 2006.257.06:49:11.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:11.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:11.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:11.62#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:49:11.62#ibcon#first serial, iclass 31, count 0 2006.257.06:49:11.62#ibcon#enter sib2, iclass 31, count 0 2006.257.06:49:11.62#ibcon#flushed, iclass 31, count 0 2006.257.06:49:11.62#ibcon#about to write, iclass 31, count 0 2006.257.06:49:11.62#ibcon#wrote, iclass 31, count 0 2006.257.06:49:11.62#ibcon#about to read 3, iclass 31, count 0 2006.257.06:49:11.64#ibcon#read 3, iclass 31, count 0 2006.257.06:49:11.64#ibcon#about to read 4, iclass 31, count 0 2006.257.06:49:11.64#ibcon#read 4, iclass 31, count 0 2006.257.06:49:11.64#ibcon#about to read 5, iclass 31, count 0 2006.257.06:49:11.64#ibcon#read 5, iclass 31, count 0 2006.257.06:49:11.64#ibcon#about to read 6, iclass 31, count 0 2006.257.06:49:11.64#ibcon#read 6, iclass 31, count 0 2006.257.06:49:11.64#ibcon#end of sib2, iclass 31, count 0 2006.257.06:49:11.64#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:49:11.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:49:11.64#ibcon#[27=USB\r\n] 2006.257.06:49:11.64#ibcon#*before write, iclass 31, count 0 2006.257.06:49:11.64#ibcon#enter sib2, iclass 31, count 0 2006.257.06:49:11.64#ibcon#flushed, iclass 31, count 0 2006.257.06:49:11.64#ibcon#about to write, iclass 31, count 0 2006.257.06:49:11.64#ibcon#wrote, iclass 31, count 0 2006.257.06:49:11.64#ibcon#about to read 3, iclass 31, count 0 2006.257.06:49:11.67#ibcon#read 3, iclass 31, count 0 2006.257.06:49:11.67#ibcon#about to read 4, iclass 31, count 0 2006.257.06:49:11.67#ibcon#read 4, iclass 31, count 0 2006.257.06:49:11.67#ibcon#about to read 5, iclass 31, count 0 2006.257.06:49:11.67#ibcon#read 5, iclass 31, count 0 2006.257.06:49:11.67#ibcon#about to read 6, iclass 31, count 0 2006.257.06:49:11.67#ibcon#read 6, iclass 31, count 0 2006.257.06:49:11.67#ibcon#end of sib2, iclass 31, count 0 2006.257.06:49:11.67#ibcon#*after write, iclass 31, count 0 2006.257.06:49:11.67#ibcon#*before return 0, iclass 31, count 0 2006.257.06:49:11.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:11.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.06:49:11.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:49:11.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:49:11.67$vck44/vabw=wide 2006.257.06:49:11.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.06:49:11.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.06:49:11.67#ibcon#ireg 8 cls_cnt 0 2006.257.06:49:11.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:11.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:11.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:11.67#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:49:11.67#ibcon#first serial, iclass 33, count 0 2006.257.06:49:11.67#ibcon#enter sib2, iclass 33, count 0 2006.257.06:49:11.67#ibcon#flushed, iclass 33, count 0 2006.257.06:49:11.67#ibcon#about to write, iclass 33, count 0 2006.257.06:49:11.67#ibcon#wrote, iclass 33, count 0 2006.257.06:49:11.67#ibcon#about to read 3, iclass 33, count 0 2006.257.06:49:11.69#ibcon#read 3, iclass 33, count 0 2006.257.06:49:11.69#ibcon#about to read 4, iclass 33, count 0 2006.257.06:49:11.69#ibcon#read 4, iclass 33, count 0 2006.257.06:49:11.69#ibcon#about to read 5, iclass 33, count 0 2006.257.06:49:11.69#ibcon#read 5, iclass 33, count 0 2006.257.06:49:11.69#ibcon#about to read 6, iclass 33, count 0 2006.257.06:49:11.69#ibcon#read 6, iclass 33, count 0 2006.257.06:49:11.69#ibcon#end of sib2, iclass 33, count 0 2006.257.06:49:11.69#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:49:11.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:49:11.69#ibcon#[25=BW32\r\n] 2006.257.06:49:11.69#ibcon#*before write, iclass 33, count 0 2006.257.06:49:11.69#ibcon#enter sib2, iclass 33, count 0 2006.257.06:49:11.69#ibcon#flushed, iclass 33, count 0 2006.257.06:49:11.69#ibcon#about to write, iclass 33, count 0 2006.257.06:49:11.69#ibcon#wrote, iclass 33, count 0 2006.257.06:49:11.69#ibcon#about to read 3, iclass 33, count 0 2006.257.06:49:11.72#ibcon#read 3, iclass 33, count 0 2006.257.06:49:11.72#ibcon#about to read 4, iclass 33, count 0 2006.257.06:49:11.72#ibcon#read 4, iclass 33, count 0 2006.257.06:49:11.72#ibcon#about to read 5, iclass 33, count 0 2006.257.06:49:11.72#ibcon#read 5, iclass 33, count 0 2006.257.06:49:11.72#ibcon#about to read 6, iclass 33, count 0 2006.257.06:49:11.72#ibcon#read 6, iclass 33, count 0 2006.257.06:49:11.72#ibcon#end of sib2, iclass 33, count 0 2006.257.06:49:11.72#ibcon#*after write, iclass 33, count 0 2006.257.06:49:11.72#ibcon#*before return 0, iclass 33, count 0 2006.257.06:49:11.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:11.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:49:11.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:49:11.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:49:11.72$vck44/vbbw=wide 2006.257.06:49:11.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:49:11.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:49:11.72#ibcon#ireg 8 cls_cnt 0 2006.257.06:49:11.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:49:11.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:49:11.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:49:11.79#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:49:11.79#ibcon#first serial, iclass 35, count 0 2006.257.06:49:11.79#ibcon#enter sib2, iclass 35, count 0 2006.257.06:49:11.79#ibcon#flushed, iclass 35, count 0 2006.257.06:49:11.79#ibcon#about to write, iclass 35, count 0 2006.257.06:49:11.79#ibcon#wrote, iclass 35, count 0 2006.257.06:49:11.79#ibcon#about to read 3, iclass 35, count 0 2006.257.06:49:11.81#ibcon#read 3, iclass 35, count 0 2006.257.06:49:11.81#ibcon#about to read 4, iclass 35, count 0 2006.257.06:49:11.81#ibcon#read 4, iclass 35, count 0 2006.257.06:49:11.81#ibcon#about to read 5, iclass 35, count 0 2006.257.06:49:11.81#ibcon#read 5, iclass 35, count 0 2006.257.06:49:11.81#ibcon#about to read 6, iclass 35, count 0 2006.257.06:49:11.81#ibcon#read 6, iclass 35, count 0 2006.257.06:49:11.81#ibcon#end of sib2, iclass 35, count 0 2006.257.06:49:11.81#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:49:11.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:49:11.81#ibcon#[27=BW32\r\n] 2006.257.06:49:11.81#ibcon#*before write, iclass 35, count 0 2006.257.06:49:11.81#ibcon#enter sib2, iclass 35, count 0 2006.257.06:49:11.81#ibcon#flushed, iclass 35, count 0 2006.257.06:49:11.81#ibcon#about to write, iclass 35, count 0 2006.257.06:49:11.81#ibcon#wrote, iclass 35, count 0 2006.257.06:49:11.81#ibcon#about to read 3, iclass 35, count 0 2006.257.06:49:11.84#ibcon#read 3, iclass 35, count 0 2006.257.06:49:11.84#ibcon#about to read 4, iclass 35, count 0 2006.257.06:49:11.84#ibcon#read 4, iclass 35, count 0 2006.257.06:49:11.84#ibcon#about to read 5, iclass 35, count 0 2006.257.06:49:11.84#ibcon#read 5, iclass 35, count 0 2006.257.06:49:11.84#ibcon#about to read 6, iclass 35, count 0 2006.257.06:49:11.84#ibcon#read 6, iclass 35, count 0 2006.257.06:49:11.84#ibcon#end of sib2, iclass 35, count 0 2006.257.06:49:11.84#ibcon#*after write, iclass 35, count 0 2006.257.06:49:11.84#ibcon#*before return 0, iclass 35, count 0 2006.257.06:49:11.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:49:11.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:49:11.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:49:11.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:49:11.84$setupk4/ifdk4 2006.257.06:49:11.84$ifdk4/lo= 2006.257.06:49:11.84$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:49:11.84$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:49:11.84$ifdk4/patch= 2006.257.06:49:11.84$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:49:11.84$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:49:11.84$setupk4/!*+20s 2006.257.06:49:11.96#abcon#<5=/01 1.3 4.3 20.68 891012.3\r\n> 2006.257.06:49:11.98#abcon#{5=INTERFACE CLEAR} 2006.257.06:49:12.04#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:49:15.14#trakl#Source acquired 2006.257.06:49:16.14#flagr#flagr/antenna,acquired 2006.257.06:49:22.13#abcon#<5=/01 1.3 4.3 20.68 891012.3\r\n> 2006.257.06:49:22.15#abcon#{5=INTERFACE CLEAR} 2006.257.06:49:22.21#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:49:26.35$setupk4/"tpicd 2006.257.06:49:26.35$setupk4/echo=off 2006.257.06:49:26.35$setupk4/xlog=off 2006.257.06:49:26.35:!2006.257.06:49:32 2006.257.06:49:32.00:preob 2006.257.06:49:32.14/onsource/TRACKING 2006.257.06:49:32.14:!2006.257.06:49:42 2006.257.06:49:42.00:"tape 2006.257.06:49:42.00:"st=record 2006.257.06:49:42.00:data_valid=on 2006.257.06:49:42.00:midob 2006.257.06:49:43.14/onsource/TRACKING 2006.257.06:49:43.14/wx/20.68,1012.3,89 2006.257.06:49:43.24/cable/+6.4774E-03 2006.257.06:49:44.33/va/01,08,usb,yes,36,39 2006.257.06:49:44.33/va/02,07,usb,yes,39,40 2006.257.06:49:44.33/va/03,08,usb,yes,35,37 2006.257.06:49:44.33/va/04,07,usb,yes,40,42 2006.257.06:49:44.33/va/05,04,usb,yes,36,37 2006.257.06:49:44.33/va/06,04,usb,yes,40,40 2006.257.06:49:44.33/va/07,04,usb,yes,41,42 2006.257.06:49:44.33/va/08,04,usb,yes,34,42 2006.257.06:49:44.56/valo/01,524.99,yes,locked 2006.257.06:49:44.56/valo/02,534.99,yes,locked 2006.257.06:49:44.56/valo/03,564.99,yes,locked 2006.257.06:49:44.56/valo/04,624.99,yes,locked 2006.257.06:49:44.56/valo/05,734.99,yes,locked 2006.257.06:49:44.56/valo/06,814.99,yes,locked 2006.257.06:49:44.56/valo/07,864.99,yes,locked 2006.257.06:49:44.56/valo/08,884.99,yes,locked 2006.257.06:49:45.65/vb/01,04,usb,yes,34,31 2006.257.06:49:45.65/vb/02,05,usb,yes,32,32 2006.257.06:49:45.65/vb/03,04,usb,yes,33,37 2006.257.06:49:45.65/vb/04,05,usb,yes,33,32 2006.257.06:49:45.65/vb/05,04,usb,yes,30,33 2006.257.06:49:45.65/vb/06,04,usb,yes,35,31 2006.257.06:49:45.65/vb/07,04,usb,yes,35,35 2006.257.06:49:45.65/vb/08,04,usb,yes,32,35 2006.257.06:49:45.89/vblo/01,629.99,yes,locked 2006.257.06:49:45.89/vblo/02,634.99,yes,locked 2006.257.06:49:45.89/vblo/03,649.99,yes,locked 2006.257.06:49:45.89/vblo/04,679.99,yes,locked 2006.257.06:49:45.89/vblo/05,709.99,yes,locked 2006.257.06:49:45.89/vblo/06,719.99,yes,locked 2006.257.06:49:45.89/vblo/07,734.99,yes,locked 2006.257.06:49:45.89/vblo/08,744.99,yes,locked 2006.257.06:49:46.04/vabw/8 2006.257.06:49:46.19/vbbw/8 2006.257.06:49:46.28/xfe/off,on,16.7 2006.257.06:49:46.66/ifatt/23,28,28,28 2006.257.06:49:47.07/fmout-gps/S +4.46E-07 2006.257.06:49:47.11:!2006.257.06:52:22 2006.257.06:52:22.01:data_valid=off 2006.257.06:52:22.01:"et 2006.257.06:52:22.02:!+3s 2006.257.06:52:25.04:"tape 2006.257.06:52:25.04:postob 2006.257.06:52:25.10/cable/+6.4782E-03 2006.257.06:52:25.10/wx/20.71,1012.3,89 2006.257.06:52:25.16/fmout-gps/S +4.46E-07 2006.257.06:52:25.16:scan_name=257-0653,jd0609,200 2006.257.06:52:25.16:source=2201+315,220314.98,314538.3,2000.0,cw 2006.257.06:52:27.14#flagr#flagr/antenna,new-source 2006.257.06:52:27.14:checkk5 2006.257.06:52:27.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:52:27.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:52:28.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:52:28.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:52:29.16/chk_obsdata//k5ts1/T2570649??a.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.06:52:29.57/chk_obsdata//k5ts2/T2570649??b.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.06:52:29.97/chk_obsdata//k5ts3/T2570649??c.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.06:52:30.37/chk_obsdata//k5ts4/T2570649??d.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.06:52:31.10/k5log//k5ts1_log_newline 2006.257.06:52:31.80/k5log//k5ts2_log_newline 2006.257.06:52:32.54/k5log//k5ts3_log_newline 2006.257.06:52:33.24/k5log//k5ts4_log_newline 2006.257.06:52:33.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:52:33.26:setupk4=1 2006.257.06:52:33.26$setupk4/echo=on 2006.257.06:52:33.26$setupk4/pcalon 2006.257.06:52:33.26$pcalon/"no phase cal control is implemented here 2006.257.06:52:33.26$setupk4/"tpicd=stop 2006.257.06:52:33.26$setupk4/"rec=synch_on 2006.257.06:52:33.26$setupk4/"rec_mode=128 2006.257.06:52:33.26$setupk4/!* 2006.257.06:52:33.26$setupk4/recpk4 2006.257.06:52:33.26$recpk4/recpatch= 2006.257.06:52:33.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:52:33.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:52:33.26$setupk4/vck44 2006.257.06:52:33.27$vck44/valo=1,524.99 2006.257.06:52:33.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.06:52:33.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.06:52:33.27#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:33.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:33.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:33.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:33.27#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:52:33.27#ibcon#first serial, iclass 12, count 0 2006.257.06:52:33.27#ibcon#enter sib2, iclass 12, count 0 2006.257.06:52:33.27#ibcon#flushed, iclass 12, count 0 2006.257.06:52:33.27#ibcon#about to write, iclass 12, count 0 2006.257.06:52:33.27#ibcon#wrote, iclass 12, count 0 2006.257.06:52:33.27#ibcon#about to read 3, iclass 12, count 0 2006.257.06:52:33.28#ibcon#read 3, iclass 12, count 0 2006.257.06:52:33.28#ibcon#about to read 4, iclass 12, count 0 2006.257.06:52:33.28#ibcon#read 4, iclass 12, count 0 2006.257.06:52:33.28#ibcon#about to read 5, iclass 12, count 0 2006.257.06:52:33.28#ibcon#read 5, iclass 12, count 0 2006.257.06:52:33.28#ibcon#about to read 6, iclass 12, count 0 2006.257.06:52:33.28#ibcon#read 6, iclass 12, count 0 2006.257.06:52:33.28#ibcon#end of sib2, iclass 12, count 0 2006.257.06:52:33.28#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:52:33.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:52:33.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:52:33.28#ibcon#*before write, iclass 12, count 0 2006.257.06:52:33.28#ibcon#enter sib2, iclass 12, count 0 2006.257.06:52:33.28#ibcon#flushed, iclass 12, count 0 2006.257.06:52:33.28#ibcon#about to write, iclass 12, count 0 2006.257.06:52:33.28#ibcon#wrote, iclass 12, count 0 2006.257.06:52:33.28#ibcon#about to read 3, iclass 12, count 0 2006.257.06:52:33.33#ibcon#read 3, iclass 12, count 0 2006.257.06:52:33.33#ibcon#about to read 4, iclass 12, count 0 2006.257.06:52:33.33#ibcon#read 4, iclass 12, count 0 2006.257.06:52:33.33#ibcon#about to read 5, iclass 12, count 0 2006.257.06:52:33.33#ibcon#read 5, iclass 12, count 0 2006.257.06:52:33.33#ibcon#about to read 6, iclass 12, count 0 2006.257.06:52:33.33#ibcon#read 6, iclass 12, count 0 2006.257.06:52:33.33#ibcon#end of sib2, iclass 12, count 0 2006.257.06:52:33.33#ibcon#*after write, iclass 12, count 0 2006.257.06:52:33.33#ibcon#*before return 0, iclass 12, count 0 2006.257.06:52:33.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:33.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:33.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:52:33.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:52:33.33$vck44/va=1,8 2006.257.06:52:33.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.06:52:33.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.06:52:33.33#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:33.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:33.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:33.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:33.33#ibcon#enter wrdev, iclass 14, count 2 2006.257.06:52:33.33#ibcon#first serial, iclass 14, count 2 2006.257.06:52:33.33#ibcon#enter sib2, iclass 14, count 2 2006.257.06:52:33.33#ibcon#flushed, iclass 14, count 2 2006.257.06:52:33.33#ibcon#about to write, iclass 14, count 2 2006.257.06:52:33.33#ibcon#wrote, iclass 14, count 2 2006.257.06:52:33.33#ibcon#about to read 3, iclass 14, count 2 2006.257.06:52:33.35#ibcon#read 3, iclass 14, count 2 2006.257.06:52:33.35#ibcon#about to read 4, iclass 14, count 2 2006.257.06:52:33.35#ibcon#read 4, iclass 14, count 2 2006.257.06:52:33.35#ibcon#about to read 5, iclass 14, count 2 2006.257.06:52:33.35#ibcon#read 5, iclass 14, count 2 2006.257.06:52:33.35#ibcon#about to read 6, iclass 14, count 2 2006.257.06:52:33.35#ibcon#read 6, iclass 14, count 2 2006.257.06:52:33.35#ibcon#end of sib2, iclass 14, count 2 2006.257.06:52:33.35#ibcon#*mode == 0, iclass 14, count 2 2006.257.06:52:33.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.06:52:33.35#ibcon#[25=AT01-08\r\n] 2006.257.06:52:33.35#ibcon#*before write, iclass 14, count 2 2006.257.06:52:33.35#ibcon#enter sib2, iclass 14, count 2 2006.257.06:52:33.35#ibcon#flushed, iclass 14, count 2 2006.257.06:52:33.35#ibcon#about to write, iclass 14, count 2 2006.257.06:52:33.35#ibcon#wrote, iclass 14, count 2 2006.257.06:52:33.35#ibcon#about to read 3, iclass 14, count 2 2006.257.06:52:33.38#ibcon#read 3, iclass 14, count 2 2006.257.06:52:33.38#ibcon#about to read 4, iclass 14, count 2 2006.257.06:52:33.38#ibcon#read 4, iclass 14, count 2 2006.257.06:52:33.38#ibcon#about to read 5, iclass 14, count 2 2006.257.06:52:33.38#ibcon#read 5, iclass 14, count 2 2006.257.06:52:33.38#ibcon#about to read 6, iclass 14, count 2 2006.257.06:52:33.38#ibcon#read 6, iclass 14, count 2 2006.257.06:52:33.38#ibcon#end of sib2, iclass 14, count 2 2006.257.06:52:33.38#ibcon#*after write, iclass 14, count 2 2006.257.06:52:33.38#ibcon#*before return 0, iclass 14, count 2 2006.257.06:52:33.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:33.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:33.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.06:52:33.38#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:33.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:33.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:33.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:33.50#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:52:33.50#ibcon#first serial, iclass 14, count 0 2006.257.06:52:33.50#ibcon#enter sib2, iclass 14, count 0 2006.257.06:52:33.50#ibcon#flushed, iclass 14, count 0 2006.257.06:52:33.50#ibcon#about to write, iclass 14, count 0 2006.257.06:52:33.50#ibcon#wrote, iclass 14, count 0 2006.257.06:52:33.50#ibcon#about to read 3, iclass 14, count 0 2006.257.06:52:33.52#ibcon#read 3, iclass 14, count 0 2006.257.06:52:33.52#ibcon#about to read 4, iclass 14, count 0 2006.257.06:52:33.52#ibcon#read 4, iclass 14, count 0 2006.257.06:52:33.52#ibcon#about to read 5, iclass 14, count 0 2006.257.06:52:33.52#ibcon#read 5, iclass 14, count 0 2006.257.06:52:33.52#ibcon#about to read 6, iclass 14, count 0 2006.257.06:52:33.52#ibcon#read 6, iclass 14, count 0 2006.257.06:52:33.52#ibcon#end of sib2, iclass 14, count 0 2006.257.06:52:33.52#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:52:33.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:52:33.52#ibcon#[25=USB\r\n] 2006.257.06:52:33.52#ibcon#*before write, iclass 14, count 0 2006.257.06:52:33.52#ibcon#enter sib2, iclass 14, count 0 2006.257.06:52:33.52#ibcon#flushed, iclass 14, count 0 2006.257.06:52:33.52#ibcon#about to write, iclass 14, count 0 2006.257.06:52:33.52#ibcon#wrote, iclass 14, count 0 2006.257.06:52:33.52#ibcon#about to read 3, iclass 14, count 0 2006.257.06:52:33.55#ibcon#read 3, iclass 14, count 0 2006.257.06:52:33.55#ibcon#about to read 4, iclass 14, count 0 2006.257.06:52:33.55#ibcon#read 4, iclass 14, count 0 2006.257.06:52:33.55#ibcon#about to read 5, iclass 14, count 0 2006.257.06:52:33.55#ibcon#read 5, iclass 14, count 0 2006.257.06:52:33.55#ibcon#about to read 6, iclass 14, count 0 2006.257.06:52:33.55#ibcon#read 6, iclass 14, count 0 2006.257.06:52:33.55#ibcon#end of sib2, iclass 14, count 0 2006.257.06:52:33.55#ibcon#*after write, iclass 14, count 0 2006.257.06:52:33.55#ibcon#*before return 0, iclass 14, count 0 2006.257.06:52:33.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:33.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:33.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:52:33.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:52:33.55$vck44/valo=2,534.99 2006.257.06:52:33.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.06:52:33.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.06:52:33.55#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:33.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:33.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:33.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:33.55#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:52:33.55#ibcon#first serial, iclass 16, count 0 2006.257.06:52:33.55#ibcon#enter sib2, iclass 16, count 0 2006.257.06:52:33.55#ibcon#flushed, iclass 16, count 0 2006.257.06:52:33.55#ibcon#about to write, iclass 16, count 0 2006.257.06:52:33.55#ibcon#wrote, iclass 16, count 0 2006.257.06:52:33.55#ibcon#about to read 3, iclass 16, count 0 2006.257.06:52:33.57#ibcon#read 3, iclass 16, count 0 2006.257.06:52:33.57#ibcon#about to read 4, iclass 16, count 0 2006.257.06:52:33.57#ibcon#read 4, iclass 16, count 0 2006.257.06:52:33.57#ibcon#about to read 5, iclass 16, count 0 2006.257.06:52:33.57#ibcon#read 5, iclass 16, count 0 2006.257.06:52:33.57#ibcon#about to read 6, iclass 16, count 0 2006.257.06:52:33.57#ibcon#read 6, iclass 16, count 0 2006.257.06:52:33.57#ibcon#end of sib2, iclass 16, count 0 2006.257.06:52:33.57#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:52:33.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:52:33.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:52:33.57#ibcon#*before write, iclass 16, count 0 2006.257.06:52:33.57#ibcon#enter sib2, iclass 16, count 0 2006.257.06:52:33.57#ibcon#flushed, iclass 16, count 0 2006.257.06:52:33.57#ibcon#about to write, iclass 16, count 0 2006.257.06:52:33.57#ibcon#wrote, iclass 16, count 0 2006.257.06:52:33.57#ibcon#about to read 3, iclass 16, count 0 2006.257.06:52:33.61#ibcon#read 3, iclass 16, count 0 2006.257.06:52:33.61#ibcon#about to read 4, iclass 16, count 0 2006.257.06:52:33.61#ibcon#read 4, iclass 16, count 0 2006.257.06:52:33.61#ibcon#about to read 5, iclass 16, count 0 2006.257.06:52:33.61#ibcon#read 5, iclass 16, count 0 2006.257.06:52:33.61#ibcon#about to read 6, iclass 16, count 0 2006.257.06:52:33.61#ibcon#read 6, iclass 16, count 0 2006.257.06:52:33.61#ibcon#end of sib2, iclass 16, count 0 2006.257.06:52:33.61#ibcon#*after write, iclass 16, count 0 2006.257.06:52:33.61#ibcon#*before return 0, iclass 16, count 0 2006.257.06:52:33.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:33.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:33.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:52:33.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:52:33.61$vck44/va=2,7 2006.257.06:52:33.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.06:52:33.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.06:52:33.61#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:33.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:33.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:33.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:33.67#ibcon#enter wrdev, iclass 18, count 2 2006.257.06:52:33.67#ibcon#first serial, iclass 18, count 2 2006.257.06:52:33.67#ibcon#enter sib2, iclass 18, count 2 2006.257.06:52:33.67#ibcon#flushed, iclass 18, count 2 2006.257.06:52:33.67#ibcon#about to write, iclass 18, count 2 2006.257.06:52:33.67#ibcon#wrote, iclass 18, count 2 2006.257.06:52:33.67#ibcon#about to read 3, iclass 18, count 2 2006.257.06:52:33.69#ibcon#read 3, iclass 18, count 2 2006.257.06:52:33.69#ibcon#about to read 4, iclass 18, count 2 2006.257.06:52:33.69#ibcon#read 4, iclass 18, count 2 2006.257.06:52:33.69#ibcon#about to read 5, iclass 18, count 2 2006.257.06:52:33.69#ibcon#read 5, iclass 18, count 2 2006.257.06:52:33.69#ibcon#about to read 6, iclass 18, count 2 2006.257.06:52:33.69#ibcon#read 6, iclass 18, count 2 2006.257.06:52:33.69#ibcon#end of sib2, iclass 18, count 2 2006.257.06:52:33.69#ibcon#*mode == 0, iclass 18, count 2 2006.257.06:52:33.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.06:52:33.69#ibcon#[25=AT02-07\r\n] 2006.257.06:52:33.69#ibcon#*before write, iclass 18, count 2 2006.257.06:52:33.69#ibcon#enter sib2, iclass 18, count 2 2006.257.06:52:33.69#ibcon#flushed, iclass 18, count 2 2006.257.06:52:33.69#ibcon#about to write, iclass 18, count 2 2006.257.06:52:33.69#ibcon#wrote, iclass 18, count 2 2006.257.06:52:33.69#ibcon#about to read 3, iclass 18, count 2 2006.257.06:52:33.72#ibcon#read 3, iclass 18, count 2 2006.257.06:52:33.72#ibcon#about to read 4, iclass 18, count 2 2006.257.06:52:33.72#ibcon#read 4, iclass 18, count 2 2006.257.06:52:33.72#ibcon#about to read 5, iclass 18, count 2 2006.257.06:52:33.72#ibcon#read 5, iclass 18, count 2 2006.257.06:52:33.72#ibcon#about to read 6, iclass 18, count 2 2006.257.06:52:33.72#ibcon#read 6, iclass 18, count 2 2006.257.06:52:33.72#ibcon#end of sib2, iclass 18, count 2 2006.257.06:52:33.72#ibcon#*after write, iclass 18, count 2 2006.257.06:52:33.72#ibcon#*before return 0, iclass 18, count 2 2006.257.06:52:33.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:33.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:33.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.06:52:33.72#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:33.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:33.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:33.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:33.84#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:52:33.84#ibcon#first serial, iclass 18, count 0 2006.257.06:52:33.84#ibcon#enter sib2, iclass 18, count 0 2006.257.06:52:33.84#ibcon#flushed, iclass 18, count 0 2006.257.06:52:33.84#ibcon#about to write, iclass 18, count 0 2006.257.06:52:33.84#ibcon#wrote, iclass 18, count 0 2006.257.06:52:33.84#ibcon#about to read 3, iclass 18, count 0 2006.257.06:52:33.86#ibcon#read 3, iclass 18, count 0 2006.257.06:52:33.86#ibcon#about to read 4, iclass 18, count 0 2006.257.06:52:33.86#ibcon#read 4, iclass 18, count 0 2006.257.06:52:33.86#ibcon#about to read 5, iclass 18, count 0 2006.257.06:52:33.86#ibcon#read 5, iclass 18, count 0 2006.257.06:52:33.86#ibcon#about to read 6, iclass 18, count 0 2006.257.06:52:33.86#ibcon#read 6, iclass 18, count 0 2006.257.06:52:33.86#ibcon#end of sib2, iclass 18, count 0 2006.257.06:52:33.86#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:52:33.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:52:33.86#ibcon#[25=USB\r\n] 2006.257.06:52:33.86#ibcon#*before write, iclass 18, count 0 2006.257.06:52:33.86#ibcon#enter sib2, iclass 18, count 0 2006.257.06:52:33.86#ibcon#flushed, iclass 18, count 0 2006.257.06:52:33.86#ibcon#about to write, iclass 18, count 0 2006.257.06:52:33.86#ibcon#wrote, iclass 18, count 0 2006.257.06:52:33.86#ibcon#about to read 3, iclass 18, count 0 2006.257.06:52:33.89#ibcon#read 3, iclass 18, count 0 2006.257.06:52:33.89#ibcon#about to read 4, iclass 18, count 0 2006.257.06:52:33.89#ibcon#read 4, iclass 18, count 0 2006.257.06:52:33.89#ibcon#about to read 5, iclass 18, count 0 2006.257.06:52:33.89#ibcon#read 5, iclass 18, count 0 2006.257.06:52:33.89#ibcon#about to read 6, iclass 18, count 0 2006.257.06:52:33.89#ibcon#read 6, iclass 18, count 0 2006.257.06:52:33.89#ibcon#end of sib2, iclass 18, count 0 2006.257.06:52:33.89#ibcon#*after write, iclass 18, count 0 2006.257.06:52:33.89#ibcon#*before return 0, iclass 18, count 0 2006.257.06:52:33.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:33.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:33.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:52:33.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:52:33.89$vck44/valo=3,564.99 2006.257.06:52:33.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.06:52:33.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.06:52:33.89#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:33.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:33.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:33.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:33.89#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:52:33.89#ibcon#first serial, iclass 20, count 0 2006.257.06:52:33.89#ibcon#enter sib2, iclass 20, count 0 2006.257.06:52:33.89#ibcon#flushed, iclass 20, count 0 2006.257.06:52:33.89#ibcon#about to write, iclass 20, count 0 2006.257.06:52:33.89#ibcon#wrote, iclass 20, count 0 2006.257.06:52:33.89#ibcon#about to read 3, iclass 20, count 0 2006.257.06:52:33.91#ibcon#read 3, iclass 20, count 0 2006.257.06:52:33.91#ibcon#about to read 4, iclass 20, count 0 2006.257.06:52:33.91#ibcon#read 4, iclass 20, count 0 2006.257.06:52:33.91#ibcon#about to read 5, iclass 20, count 0 2006.257.06:52:33.91#ibcon#read 5, iclass 20, count 0 2006.257.06:52:33.91#ibcon#about to read 6, iclass 20, count 0 2006.257.06:52:33.91#ibcon#read 6, iclass 20, count 0 2006.257.06:52:33.91#ibcon#end of sib2, iclass 20, count 0 2006.257.06:52:33.91#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:52:33.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:52:33.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:52:33.91#ibcon#*before write, iclass 20, count 0 2006.257.06:52:33.91#ibcon#enter sib2, iclass 20, count 0 2006.257.06:52:33.91#ibcon#flushed, iclass 20, count 0 2006.257.06:52:33.91#ibcon#about to write, iclass 20, count 0 2006.257.06:52:33.91#ibcon#wrote, iclass 20, count 0 2006.257.06:52:33.91#ibcon#about to read 3, iclass 20, count 0 2006.257.06:52:33.95#ibcon#read 3, iclass 20, count 0 2006.257.06:52:33.95#ibcon#about to read 4, iclass 20, count 0 2006.257.06:52:33.95#ibcon#read 4, iclass 20, count 0 2006.257.06:52:33.95#ibcon#about to read 5, iclass 20, count 0 2006.257.06:52:33.95#ibcon#read 5, iclass 20, count 0 2006.257.06:52:33.95#ibcon#about to read 6, iclass 20, count 0 2006.257.06:52:33.95#ibcon#read 6, iclass 20, count 0 2006.257.06:52:33.95#ibcon#end of sib2, iclass 20, count 0 2006.257.06:52:33.95#ibcon#*after write, iclass 20, count 0 2006.257.06:52:33.95#ibcon#*before return 0, iclass 20, count 0 2006.257.06:52:33.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:33.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:33.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:52:33.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:52:33.95$vck44/va=3,8 2006.257.06:52:33.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.06:52:33.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.06:52:33.95#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:33.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:34.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:34.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:34.01#ibcon#enter wrdev, iclass 22, count 2 2006.257.06:52:34.01#ibcon#first serial, iclass 22, count 2 2006.257.06:52:34.01#ibcon#enter sib2, iclass 22, count 2 2006.257.06:52:34.01#ibcon#flushed, iclass 22, count 2 2006.257.06:52:34.01#ibcon#about to write, iclass 22, count 2 2006.257.06:52:34.01#ibcon#wrote, iclass 22, count 2 2006.257.06:52:34.01#ibcon#about to read 3, iclass 22, count 2 2006.257.06:52:34.03#ibcon#read 3, iclass 22, count 2 2006.257.06:52:34.03#ibcon#about to read 4, iclass 22, count 2 2006.257.06:52:34.03#ibcon#read 4, iclass 22, count 2 2006.257.06:52:34.03#ibcon#about to read 5, iclass 22, count 2 2006.257.06:52:34.03#ibcon#read 5, iclass 22, count 2 2006.257.06:52:34.03#ibcon#about to read 6, iclass 22, count 2 2006.257.06:52:34.03#ibcon#read 6, iclass 22, count 2 2006.257.06:52:34.03#ibcon#end of sib2, iclass 22, count 2 2006.257.06:52:34.03#ibcon#*mode == 0, iclass 22, count 2 2006.257.06:52:34.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.06:52:34.03#ibcon#[25=AT03-08\r\n] 2006.257.06:52:34.03#ibcon#*before write, iclass 22, count 2 2006.257.06:52:34.03#ibcon#enter sib2, iclass 22, count 2 2006.257.06:52:34.03#ibcon#flushed, iclass 22, count 2 2006.257.06:52:34.03#ibcon#about to write, iclass 22, count 2 2006.257.06:52:34.03#ibcon#wrote, iclass 22, count 2 2006.257.06:52:34.03#ibcon#about to read 3, iclass 22, count 2 2006.257.06:52:34.06#ibcon#read 3, iclass 22, count 2 2006.257.06:52:34.06#ibcon#about to read 4, iclass 22, count 2 2006.257.06:52:34.06#ibcon#read 4, iclass 22, count 2 2006.257.06:52:34.06#ibcon#about to read 5, iclass 22, count 2 2006.257.06:52:34.06#ibcon#read 5, iclass 22, count 2 2006.257.06:52:34.06#ibcon#about to read 6, iclass 22, count 2 2006.257.06:52:34.06#ibcon#read 6, iclass 22, count 2 2006.257.06:52:34.06#ibcon#end of sib2, iclass 22, count 2 2006.257.06:52:34.06#ibcon#*after write, iclass 22, count 2 2006.257.06:52:34.06#ibcon#*before return 0, iclass 22, count 2 2006.257.06:52:34.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:34.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:34.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.06:52:34.06#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:34.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:34.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:34.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:34.18#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:52:34.18#ibcon#first serial, iclass 22, count 0 2006.257.06:52:34.18#ibcon#enter sib2, iclass 22, count 0 2006.257.06:52:34.18#ibcon#flushed, iclass 22, count 0 2006.257.06:52:34.18#ibcon#about to write, iclass 22, count 0 2006.257.06:52:34.18#ibcon#wrote, iclass 22, count 0 2006.257.06:52:34.18#ibcon#about to read 3, iclass 22, count 0 2006.257.06:52:34.20#ibcon#read 3, iclass 22, count 0 2006.257.06:52:34.20#ibcon#about to read 4, iclass 22, count 0 2006.257.06:52:34.20#ibcon#read 4, iclass 22, count 0 2006.257.06:52:34.20#ibcon#about to read 5, iclass 22, count 0 2006.257.06:52:34.20#ibcon#read 5, iclass 22, count 0 2006.257.06:52:34.20#ibcon#about to read 6, iclass 22, count 0 2006.257.06:52:34.20#ibcon#read 6, iclass 22, count 0 2006.257.06:52:34.20#ibcon#end of sib2, iclass 22, count 0 2006.257.06:52:34.20#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:52:34.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:52:34.20#ibcon#[25=USB\r\n] 2006.257.06:52:34.20#ibcon#*before write, iclass 22, count 0 2006.257.06:52:34.20#ibcon#enter sib2, iclass 22, count 0 2006.257.06:52:34.20#ibcon#flushed, iclass 22, count 0 2006.257.06:52:34.20#ibcon#about to write, iclass 22, count 0 2006.257.06:52:34.20#ibcon#wrote, iclass 22, count 0 2006.257.06:52:34.20#ibcon#about to read 3, iclass 22, count 0 2006.257.06:52:34.23#ibcon#read 3, iclass 22, count 0 2006.257.06:52:34.23#ibcon#about to read 4, iclass 22, count 0 2006.257.06:52:34.23#ibcon#read 4, iclass 22, count 0 2006.257.06:52:34.23#ibcon#about to read 5, iclass 22, count 0 2006.257.06:52:34.23#ibcon#read 5, iclass 22, count 0 2006.257.06:52:34.23#ibcon#about to read 6, iclass 22, count 0 2006.257.06:52:34.23#ibcon#read 6, iclass 22, count 0 2006.257.06:52:34.23#ibcon#end of sib2, iclass 22, count 0 2006.257.06:52:34.23#ibcon#*after write, iclass 22, count 0 2006.257.06:52:34.23#ibcon#*before return 0, iclass 22, count 0 2006.257.06:52:34.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:34.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:34.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:52:34.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:52:34.23$vck44/valo=4,624.99 2006.257.06:52:34.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.06:52:34.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.06:52:34.23#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:34.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:34.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:34.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:34.23#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:52:34.23#ibcon#first serial, iclass 24, count 0 2006.257.06:52:34.23#ibcon#enter sib2, iclass 24, count 0 2006.257.06:52:34.23#ibcon#flushed, iclass 24, count 0 2006.257.06:52:34.23#ibcon#about to write, iclass 24, count 0 2006.257.06:52:34.23#ibcon#wrote, iclass 24, count 0 2006.257.06:52:34.23#ibcon#about to read 3, iclass 24, count 0 2006.257.06:52:34.25#ibcon#read 3, iclass 24, count 0 2006.257.06:52:34.25#ibcon#about to read 4, iclass 24, count 0 2006.257.06:52:34.25#ibcon#read 4, iclass 24, count 0 2006.257.06:52:34.25#ibcon#about to read 5, iclass 24, count 0 2006.257.06:52:34.25#ibcon#read 5, iclass 24, count 0 2006.257.06:52:34.25#ibcon#about to read 6, iclass 24, count 0 2006.257.06:52:34.25#ibcon#read 6, iclass 24, count 0 2006.257.06:52:34.25#ibcon#end of sib2, iclass 24, count 0 2006.257.06:52:34.25#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:52:34.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:52:34.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:52:34.25#ibcon#*before write, iclass 24, count 0 2006.257.06:52:34.25#ibcon#enter sib2, iclass 24, count 0 2006.257.06:52:34.25#ibcon#flushed, iclass 24, count 0 2006.257.06:52:34.25#ibcon#about to write, iclass 24, count 0 2006.257.06:52:34.25#ibcon#wrote, iclass 24, count 0 2006.257.06:52:34.25#ibcon#about to read 3, iclass 24, count 0 2006.257.06:52:34.29#ibcon#read 3, iclass 24, count 0 2006.257.06:52:34.29#ibcon#about to read 4, iclass 24, count 0 2006.257.06:52:34.29#ibcon#read 4, iclass 24, count 0 2006.257.06:52:34.29#ibcon#about to read 5, iclass 24, count 0 2006.257.06:52:34.29#ibcon#read 5, iclass 24, count 0 2006.257.06:52:34.29#ibcon#about to read 6, iclass 24, count 0 2006.257.06:52:34.29#ibcon#read 6, iclass 24, count 0 2006.257.06:52:34.29#ibcon#end of sib2, iclass 24, count 0 2006.257.06:52:34.29#ibcon#*after write, iclass 24, count 0 2006.257.06:52:34.29#ibcon#*before return 0, iclass 24, count 0 2006.257.06:52:34.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:34.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:34.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:52:34.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:52:34.29$vck44/va=4,7 2006.257.06:52:34.29#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.06:52:34.29#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.06:52:34.29#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:34.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:34.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:34.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:34.35#ibcon#enter wrdev, iclass 26, count 2 2006.257.06:52:34.35#ibcon#first serial, iclass 26, count 2 2006.257.06:52:34.35#ibcon#enter sib2, iclass 26, count 2 2006.257.06:52:34.35#ibcon#flushed, iclass 26, count 2 2006.257.06:52:34.35#ibcon#about to write, iclass 26, count 2 2006.257.06:52:34.35#ibcon#wrote, iclass 26, count 2 2006.257.06:52:34.35#ibcon#about to read 3, iclass 26, count 2 2006.257.06:52:34.37#ibcon#read 3, iclass 26, count 2 2006.257.06:52:34.37#ibcon#about to read 4, iclass 26, count 2 2006.257.06:52:34.37#ibcon#read 4, iclass 26, count 2 2006.257.06:52:34.37#ibcon#about to read 5, iclass 26, count 2 2006.257.06:52:34.37#ibcon#read 5, iclass 26, count 2 2006.257.06:52:34.37#ibcon#about to read 6, iclass 26, count 2 2006.257.06:52:34.37#ibcon#read 6, iclass 26, count 2 2006.257.06:52:34.37#ibcon#end of sib2, iclass 26, count 2 2006.257.06:52:34.37#ibcon#*mode == 0, iclass 26, count 2 2006.257.06:52:34.37#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.06:52:34.37#ibcon#[25=AT04-07\r\n] 2006.257.06:52:34.37#ibcon#*before write, iclass 26, count 2 2006.257.06:52:34.37#ibcon#enter sib2, iclass 26, count 2 2006.257.06:52:34.37#ibcon#flushed, iclass 26, count 2 2006.257.06:52:34.37#ibcon#about to write, iclass 26, count 2 2006.257.06:52:34.37#ibcon#wrote, iclass 26, count 2 2006.257.06:52:34.37#ibcon#about to read 3, iclass 26, count 2 2006.257.06:52:34.40#ibcon#read 3, iclass 26, count 2 2006.257.06:52:34.40#ibcon#about to read 4, iclass 26, count 2 2006.257.06:52:34.40#ibcon#read 4, iclass 26, count 2 2006.257.06:52:34.40#ibcon#about to read 5, iclass 26, count 2 2006.257.06:52:34.40#ibcon#read 5, iclass 26, count 2 2006.257.06:52:34.40#ibcon#about to read 6, iclass 26, count 2 2006.257.06:52:34.40#ibcon#read 6, iclass 26, count 2 2006.257.06:52:34.40#ibcon#end of sib2, iclass 26, count 2 2006.257.06:52:34.40#ibcon#*after write, iclass 26, count 2 2006.257.06:52:34.40#ibcon#*before return 0, iclass 26, count 2 2006.257.06:52:34.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:34.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:34.40#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.06:52:34.40#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:34.40#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:34.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:34.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:34.52#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:52:34.52#ibcon#first serial, iclass 26, count 0 2006.257.06:52:34.52#ibcon#enter sib2, iclass 26, count 0 2006.257.06:52:34.52#ibcon#flushed, iclass 26, count 0 2006.257.06:52:34.52#ibcon#about to write, iclass 26, count 0 2006.257.06:52:34.52#ibcon#wrote, iclass 26, count 0 2006.257.06:52:34.52#ibcon#about to read 3, iclass 26, count 0 2006.257.06:52:34.54#ibcon#read 3, iclass 26, count 0 2006.257.06:52:34.54#ibcon#about to read 4, iclass 26, count 0 2006.257.06:52:34.54#ibcon#read 4, iclass 26, count 0 2006.257.06:52:34.54#ibcon#about to read 5, iclass 26, count 0 2006.257.06:52:34.54#ibcon#read 5, iclass 26, count 0 2006.257.06:52:34.54#ibcon#about to read 6, iclass 26, count 0 2006.257.06:52:34.54#ibcon#read 6, iclass 26, count 0 2006.257.06:52:34.54#ibcon#end of sib2, iclass 26, count 0 2006.257.06:52:34.54#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:52:34.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:52:34.54#ibcon#[25=USB\r\n] 2006.257.06:52:34.54#ibcon#*before write, iclass 26, count 0 2006.257.06:52:34.54#ibcon#enter sib2, iclass 26, count 0 2006.257.06:52:34.54#ibcon#flushed, iclass 26, count 0 2006.257.06:52:34.54#ibcon#about to write, iclass 26, count 0 2006.257.06:52:34.54#ibcon#wrote, iclass 26, count 0 2006.257.06:52:34.54#ibcon#about to read 3, iclass 26, count 0 2006.257.06:52:34.57#ibcon#read 3, iclass 26, count 0 2006.257.06:52:34.57#ibcon#about to read 4, iclass 26, count 0 2006.257.06:52:34.57#ibcon#read 4, iclass 26, count 0 2006.257.06:52:34.57#ibcon#about to read 5, iclass 26, count 0 2006.257.06:52:34.57#ibcon#read 5, iclass 26, count 0 2006.257.06:52:34.57#ibcon#about to read 6, iclass 26, count 0 2006.257.06:52:34.57#ibcon#read 6, iclass 26, count 0 2006.257.06:52:34.57#ibcon#end of sib2, iclass 26, count 0 2006.257.06:52:34.57#ibcon#*after write, iclass 26, count 0 2006.257.06:52:34.57#ibcon#*before return 0, iclass 26, count 0 2006.257.06:52:34.57#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:34.57#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:34.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:52:34.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:52:34.57$vck44/valo=5,734.99 2006.257.06:52:34.57#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.06:52:34.57#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.06:52:34.57#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:34.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:34.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:34.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:34.57#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:52:34.57#ibcon#first serial, iclass 28, count 0 2006.257.06:52:34.57#ibcon#enter sib2, iclass 28, count 0 2006.257.06:52:34.57#ibcon#flushed, iclass 28, count 0 2006.257.06:52:34.57#ibcon#about to write, iclass 28, count 0 2006.257.06:52:34.57#ibcon#wrote, iclass 28, count 0 2006.257.06:52:34.57#ibcon#about to read 3, iclass 28, count 0 2006.257.06:52:34.59#ibcon#read 3, iclass 28, count 0 2006.257.06:52:34.59#ibcon#about to read 4, iclass 28, count 0 2006.257.06:52:34.59#ibcon#read 4, iclass 28, count 0 2006.257.06:52:34.59#ibcon#about to read 5, iclass 28, count 0 2006.257.06:52:34.59#ibcon#read 5, iclass 28, count 0 2006.257.06:52:34.59#ibcon#about to read 6, iclass 28, count 0 2006.257.06:52:34.59#ibcon#read 6, iclass 28, count 0 2006.257.06:52:34.59#ibcon#end of sib2, iclass 28, count 0 2006.257.06:52:34.59#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:52:34.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:52:34.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:52:34.59#ibcon#*before write, iclass 28, count 0 2006.257.06:52:34.59#ibcon#enter sib2, iclass 28, count 0 2006.257.06:52:34.59#ibcon#flushed, iclass 28, count 0 2006.257.06:52:34.59#ibcon#about to write, iclass 28, count 0 2006.257.06:52:34.59#ibcon#wrote, iclass 28, count 0 2006.257.06:52:34.59#ibcon#about to read 3, iclass 28, count 0 2006.257.06:52:34.63#ibcon#read 3, iclass 28, count 0 2006.257.06:52:34.63#ibcon#about to read 4, iclass 28, count 0 2006.257.06:52:34.63#ibcon#read 4, iclass 28, count 0 2006.257.06:52:34.63#ibcon#about to read 5, iclass 28, count 0 2006.257.06:52:34.63#ibcon#read 5, iclass 28, count 0 2006.257.06:52:34.63#ibcon#about to read 6, iclass 28, count 0 2006.257.06:52:34.63#ibcon#read 6, iclass 28, count 0 2006.257.06:52:34.63#ibcon#end of sib2, iclass 28, count 0 2006.257.06:52:34.63#ibcon#*after write, iclass 28, count 0 2006.257.06:52:34.63#ibcon#*before return 0, iclass 28, count 0 2006.257.06:52:34.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:34.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:34.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:52:34.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:52:34.63$vck44/va=5,4 2006.257.06:52:34.63#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.06:52:34.63#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.06:52:34.63#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:34.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:34.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:34.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:34.69#ibcon#enter wrdev, iclass 30, count 2 2006.257.06:52:34.69#ibcon#first serial, iclass 30, count 2 2006.257.06:52:34.69#ibcon#enter sib2, iclass 30, count 2 2006.257.06:52:34.69#ibcon#flushed, iclass 30, count 2 2006.257.06:52:34.69#ibcon#about to write, iclass 30, count 2 2006.257.06:52:34.69#ibcon#wrote, iclass 30, count 2 2006.257.06:52:34.69#ibcon#about to read 3, iclass 30, count 2 2006.257.06:52:34.71#ibcon#read 3, iclass 30, count 2 2006.257.06:52:34.71#ibcon#about to read 4, iclass 30, count 2 2006.257.06:52:34.71#ibcon#read 4, iclass 30, count 2 2006.257.06:52:34.71#ibcon#about to read 5, iclass 30, count 2 2006.257.06:52:34.71#ibcon#read 5, iclass 30, count 2 2006.257.06:52:34.71#ibcon#about to read 6, iclass 30, count 2 2006.257.06:52:34.71#ibcon#read 6, iclass 30, count 2 2006.257.06:52:34.71#ibcon#end of sib2, iclass 30, count 2 2006.257.06:52:34.71#ibcon#*mode == 0, iclass 30, count 2 2006.257.06:52:34.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.06:52:34.71#ibcon#[25=AT05-04\r\n] 2006.257.06:52:34.71#ibcon#*before write, iclass 30, count 2 2006.257.06:52:34.71#ibcon#enter sib2, iclass 30, count 2 2006.257.06:52:34.71#ibcon#flushed, iclass 30, count 2 2006.257.06:52:34.71#ibcon#about to write, iclass 30, count 2 2006.257.06:52:34.71#ibcon#wrote, iclass 30, count 2 2006.257.06:52:34.71#ibcon#about to read 3, iclass 30, count 2 2006.257.06:52:34.74#ibcon#read 3, iclass 30, count 2 2006.257.06:52:34.74#ibcon#about to read 4, iclass 30, count 2 2006.257.06:52:34.74#ibcon#read 4, iclass 30, count 2 2006.257.06:52:34.74#ibcon#about to read 5, iclass 30, count 2 2006.257.06:52:34.74#ibcon#read 5, iclass 30, count 2 2006.257.06:52:34.74#ibcon#about to read 6, iclass 30, count 2 2006.257.06:52:34.74#ibcon#read 6, iclass 30, count 2 2006.257.06:52:34.74#ibcon#end of sib2, iclass 30, count 2 2006.257.06:52:34.74#ibcon#*after write, iclass 30, count 2 2006.257.06:52:34.74#ibcon#*before return 0, iclass 30, count 2 2006.257.06:52:34.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:34.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:34.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.06:52:34.74#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:34.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:34.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:34.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:34.86#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:52:34.86#ibcon#first serial, iclass 30, count 0 2006.257.06:52:34.86#ibcon#enter sib2, iclass 30, count 0 2006.257.06:52:34.86#ibcon#flushed, iclass 30, count 0 2006.257.06:52:34.86#ibcon#about to write, iclass 30, count 0 2006.257.06:52:34.86#ibcon#wrote, iclass 30, count 0 2006.257.06:52:34.86#ibcon#about to read 3, iclass 30, count 0 2006.257.06:52:34.88#ibcon#read 3, iclass 30, count 0 2006.257.06:52:34.88#ibcon#about to read 4, iclass 30, count 0 2006.257.06:52:34.88#ibcon#read 4, iclass 30, count 0 2006.257.06:52:34.88#ibcon#about to read 5, iclass 30, count 0 2006.257.06:52:34.88#ibcon#read 5, iclass 30, count 0 2006.257.06:52:34.88#ibcon#about to read 6, iclass 30, count 0 2006.257.06:52:34.88#ibcon#read 6, iclass 30, count 0 2006.257.06:52:34.88#ibcon#end of sib2, iclass 30, count 0 2006.257.06:52:34.88#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:52:34.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:52:34.88#ibcon#[25=USB\r\n] 2006.257.06:52:34.88#ibcon#*before write, iclass 30, count 0 2006.257.06:52:34.88#ibcon#enter sib2, iclass 30, count 0 2006.257.06:52:34.88#ibcon#flushed, iclass 30, count 0 2006.257.06:52:34.88#ibcon#about to write, iclass 30, count 0 2006.257.06:52:34.88#ibcon#wrote, iclass 30, count 0 2006.257.06:52:34.88#ibcon#about to read 3, iclass 30, count 0 2006.257.06:52:34.91#ibcon#read 3, iclass 30, count 0 2006.257.06:52:34.91#ibcon#about to read 4, iclass 30, count 0 2006.257.06:52:34.91#ibcon#read 4, iclass 30, count 0 2006.257.06:52:34.91#ibcon#about to read 5, iclass 30, count 0 2006.257.06:52:34.91#ibcon#read 5, iclass 30, count 0 2006.257.06:52:34.91#ibcon#about to read 6, iclass 30, count 0 2006.257.06:52:34.91#ibcon#read 6, iclass 30, count 0 2006.257.06:52:34.91#ibcon#end of sib2, iclass 30, count 0 2006.257.06:52:34.91#ibcon#*after write, iclass 30, count 0 2006.257.06:52:34.91#ibcon#*before return 0, iclass 30, count 0 2006.257.06:52:34.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:34.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:34.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:52:34.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:52:34.91$vck44/valo=6,814.99 2006.257.06:52:34.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.06:52:34.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.06:52:34.91#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:34.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:34.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:34.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:34.91#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:52:34.91#ibcon#first serial, iclass 32, count 0 2006.257.06:52:34.91#ibcon#enter sib2, iclass 32, count 0 2006.257.06:52:34.91#ibcon#flushed, iclass 32, count 0 2006.257.06:52:34.91#ibcon#about to write, iclass 32, count 0 2006.257.06:52:34.91#ibcon#wrote, iclass 32, count 0 2006.257.06:52:34.91#ibcon#about to read 3, iclass 32, count 0 2006.257.06:52:34.93#ibcon#read 3, iclass 32, count 0 2006.257.06:52:34.93#ibcon#about to read 4, iclass 32, count 0 2006.257.06:52:34.93#ibcon#read 4, iclass 32, count 0 2006.257.06:52:34.93#ibcon#about to read 5, iclass 32, count 0 2006.257.06:52:34.93#ibcon#read 5, iclass 32, count 0 2006.257.06:52:34.93#ibcon#about to read 6, iclass 32, count 0 2006.257.06:52:34.93#ibcon#read 6, iclass 32, count 0 2006.257.06:52:34.93#ibcon#end of sib2, iclass 32, count 0 2006.257.06:52:34.93#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:52:34.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:52:34.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:52:34.93#ibcon#*before write, iclass 32, count 0 2006.257.06:52:34.93#ibcon#enter sib2, iclass 32, count 0 2006.257.06:52:34.93#ibcon#flushed, iclass 32, count 0 2006.257.06:52:34.93#ibcon#about to write, iclass 32, count 0 2006.257.06:52:34.93#ibcon#wrote, iclass 32, count 0 2006.257.06:52:34.93#ibcon#about to read 3, iclass 32, count 0 2006.257.06:52:34.97#ibcon#read 3, iclass 32, count 0 2006.257.06:52:34.97#ibcon#about to read 4, iclass 32, count 0 2006.257.06:52:34.97#ibcon#read 4, iclass 32, count 0 2006.257.06:52:34.97#ibcon#about to read 5, iclass 32, count 0 2006.257.06:52:34.97#ibcon#read 5, iclass 32, count 0 2006.257.06:52:34.97#ibcon#about to read 6, iclass 32, count 0 2006.257.06:52:34.97#ibcon#read 6, iclass 32, count 0 2006.257.06:52:34.97#ibcon#end of sib2, iclass 32, count 0 2006.257.06:52:34.97#ibcon#*after write, iclass 32, count 0 2006.257.06:52:34.97#ibcon#*before return 0, iclass 32, count 0 2006.257.06:52:34.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:34.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:34.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:52:34.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:52:34.97$vck44/va=6,4 2006.257.06:52:34.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.06:52:34.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.06:52:34.97#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:34.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:35.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:35.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:35.03#ibcon#enter wrdev, iclass 34, count 2 2006.257.06:52:35.03#ibcon#first serial, iclass 34, count 2 2006.257.06:52:35.03#ibcon#enter sib2, iclass 34, count 2 2006.257.06:52:35.03#ibcon#flushed, iclass 34, count 2 2006.257.06:52:35.03#ibcon#about to write, iclass 34, count 2 2006.257.06:52:35.03#ibcon#wrote, iclass 34, count 2 2006.257.06:52:35.03#ibcon#about to read 3, iclass 34, count 2 2006.257.06:52:35.05#ibcon#read 3, iclass 34, count 2 2006.257.06:52:35.05#ibcon#about to read 4, iclass 34, count 2 2006.257.06:52:35.05#ibcon#read 4, iclass 34, count 2 2006.257.06:52:35.05#ibcon#about to read 5, iclass 34, count 2 2006.257.06:52:35.05#ibcon#read 5, iclass 34, count 2 2006.257.06:52:35.05#ibcon#about to read 6, iclass 34, count 2 2006.257.06:52:35.05#ibcon#read 6, iclass 34, count 2 2006.257.06:52:35.05#ibcon#end of sib2, iclass 34, count 2 2006.257.06:52:35.05#ibcon#*mode == 0, iclass 34, count 2 2006.257.06:52:35.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.06:52:35.05#ibcon#[25=AT06-04\r\n] 2006.257.06:52:35.05#ibcon#*before write, iclass 34, count 2 2006.257.06:52:35.05#ibcon#enter sib2, iclass 34, count 2 2006.257.06:52:35.05#ibcon#flushed, iclass 34, count 2 2006.257.06:52:35.05#ibcon#about to write, iclass 34, count 2 2006.257.06:52:35.05#ibcon#wrote, iclass 34, count 2 2006.257.06:52:35.05#ibcon#about to read 3, iclass 34, count 2 2006.257.06:52:35.08#ibcon#read 3, iclass 34, count 2 2006.257.06:52:35.08#ibcon#about to read 4, iclass 34, count 2 2006.257.06:52:35.08#ibcon#read 4, iclass 34, count 2 2006.257.06:52:35.08#ibcon#about to read 5, iclass 34, count 2 2006.257.06:52:35.08#ibcon#read 5, iclass 34, count 2 2006.257.06:52:35.08#ibcon#about to read 6, iclass 34, count 2 2006.257.06:52:35.08#ibcon#read 6, iclass 34, count 2 2006.257.06:52:35.08#ibcon#end of sib2, iclass 34, count 2 2006.257.06:52:35.08#ibcon#*after write, iclass 34, count 2 2006.257.06:52:35.08#ibcon#*before return 0, iclass 34, count 2 2006.257.06:52:35.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:35.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:35.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.06:52:35.08#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:35.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:35.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:35.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:35.20#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:52:35.20#ibcon#first serial, iclass 34, count 0 2006.257.06:52:35.20#ibcon#enter sib2, iclass 34, count 0 2006.257.06:52:35.20#ibcon#flushed, iclass 34, count 0 2006.257.06:52:35.20#ibcon#about to write, iclass 34, count 0 2006.257.06:52:35.20#ibcon#wrote, iclass 34, count 0 2006.257.06:52:35.20#ibcon#about to read 3, iclass 34, count 0 2006.257.06:52:35.22#ibcon#read 3, iclass 34, count 0 2006.257.06:52:35.22#ibcon#about to read 4, iclass 34, count 0 2006.257.06:52:35.22#ibcon#read 4, iclass 34, count 0 2006.257.06:52:35.22#ibcon#about to read 5, iclass 34, count 0 2006.257.06:52:35.22#ibcon#read 5, iclass 34, count 0 2006.257.06:52:35.22#ibcon#about to read 6, iclass 34, count 0 2006.257.06:52:35.22#ibcon#read 6, iclass 34, count 0 2006.257.06:52:35.22#ibcon#end of sib2, iclass 34, count 0 2006.257.06:52:35.22#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:52:35.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:52:35.22#ibcon#[25=USB\r\n] 2006.257.06:52:35.22#ibcon#*before write, iclass 34, count 0 2006.257.06:52:35.22#ibcon#enter sib2, iclass 34, count 0 2006.257.06:52:35.22#ibcon#flushed, iclass 34, count 0 2006.257.06:52:35.22#ibcon#about to write, iclass 34, count 0 2006.257.06:52:35.22#ibcon#wrote, iclass 34, count 0 2006.257.06:52:35.22#ibcon#about to read 3, iclass 34, count 0 2006.257.06:52:35.25#ibcon#read 3, iclass 34, count 0 2006.257.06:52:35.25#ibcon#about to read 4, iclass 34, count 0 2006.257.06:52:35.25#ibcon#read 4, iclass 34, count 0 2006.257.06:52:35.25#ibcon#about to read 5, iclass 34, count 0 2006.257.06:52:35.25#ibcon#read 5, iclass 34, count 0 2006.257.06:52:35.25#ibcon#about to read 6, iclass 34, count 0 2006.257.06:52:35.25#ibcon#read 6, iclass 34, count 0 2006.257.06:52:35.25#ibcon#end of sib2, iclass 34, count 0 2006.257.06:52:35.25#ibcon#*after write, iclass 34, count 0 2006.257.06:52:35.25#ibcon#*before return 0, iclass 34, count 0 2006.257.06:52:35.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:35.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:35.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:52:35.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:52:35.25$vck44/valo=7,864.99 2006.257.06:52:35.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.06:52:35.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.06:52:35.25#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:35.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:35.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:35.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:35.25#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:52:35.25#ibcon#first serial, iclass 36, count 0 2006.257.06:52:35.25#ibcon#enter sib2, iclass 36, count 0 2006.257.06:52:35.25#ibcon#flushed, iclass 36, count 0 2006.257.06:52:35.25#ibcon#about to write, iclass 36, count 0 2006.257.06:52:35.25#ibcon#wrote, iclass 36, count 0 2006.257.06:52:35.25#ibcon#about to read 3, iclass 36, count 0 2006.257.06:52:35.27#ibcon#read 3, iclass 36, count 0 2006.257.06:52:35.27#ibcon#about to read 4, iclass 36, count 0 2006.257.06:52:35.27#ibcon#read 4, iclass 36, count 0 2006.257.06:52:35.27#ibcon#about to read 5, iclass 36, count 0 2006.257.06:52:35.27#ibcon#read 5, iclass 36, count 0 2006.257.06:52:35.27#ibcon#about to read 6, iclass 36, count 0 2006.257.06:52:35.27#ibcon#read 6, iclass 36, count 0 2006.257.06:52:35.27#ibcon#end of sib2, iclass 36, count 0 2006.257.06:52:35.27#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:52:35.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:52:35.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:52:35.27#ibcon#*before write, iclass 36, count 0 2006.257.06:52:35.27#ibcon#enter sib2, iclass 36, count 0 2006.257.06:52:35.27#ibcon#flushed, iclass 36, count 0 2006.257.06:52:35.27#ibcon#about to write, iclass 36, count 0 2006.257.06:52:35.27#ibcon#wrote, iclass 36, count 0 2006.257.06:52:35.27#ibcon#about to read 3, iclass 36, count 0 2006.257.06:52:35.31#ibcon#read 3, iclass 36, count 0 2006.257.06:52:35.31#ibcon#about to read 4, iclass 36, count 0 2006.257.06:52:35.31#ibcon#read 4, iclass 36, count 0 2006.257.06:52:35.31#ibcon#about to read 5, iclass 36, count 0 2006.257.06:52:35.31#ibcon#read 5, iclass 36, count 0 2006.257.06:52:35.31#ibcon#about to read 6, iclass 36, count 0 2006.257.06:52:35.31#ibcon#read 6, iclass 36, count 0 2006.257.06:52:35.31#ibcon#end of sib2, iclass 36, count 0 2006.257.06:52:35.31#ibcon#*after write, iclass 36, count 0 2006.257.06:52:35.31#ibcon#*before return 0, iclass 36, count 0 2006.257.06:52:35.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:35.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:35.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:52:35.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:52:35.31$vck44/va=7,4 2006.257.06:52:35.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.06:52:35.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.06:52:35.31#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:35.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:35.36#abcon#<5=/01 1.4 4.3 20.71 891012.3\r\n> 2006.257.06:52:35.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:35.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:35.37#ibcon#enter wrdev, iclass 38, count 2 2006.257.06:52:35.37#ibcon#first serial, iclass 38, count 2 2006.257.06:52:35.37#ibcon#enter sib2, iclass 38, count 2 2006.257.06:52:35.37#ibcon#flushed, iclass 38, count 2 2006.257.06:52:35.37#ibcon#about to write, iclass 38, count 2 2006.257.06:52:35.37#ibcon#wrote, iclass 38, count 2 2006.257.06:52:35.37#ibcon#about to read 3, iclass 38, count 2 2006.257.06:52:35.38#abcon#{5=INTERFACE CLEAR} 2006.257.06:52:35.39#ibcon#read 3, iclass 38, count 2 2006.257.06:52:35.39#ibcon#about to read 4, iclass 38, count 2 2006.257.06:52:35.39#ibcon#read 4, iclass 38, count 2 2006.257.06:52:35.39#ibcon#about to read 5, iclass 38, count 2 2006.257.06:52:35.39#ibcon#read 5, iclass 38, count 2 2006.257.06:52:35.39#ibcon#about to read 6, iclass 38, count 2 2006.257.06:52:35.39#ibcon#read 6, iclass 38, count 2 2006.257.06:52:35.39#ibcon#end of sib2, iclass 38, count 2 2006.257.06:52:35.39#ibcon#*mode == 0, iclass 38, count 2 2006.257.06:52:35.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.06:52:35.39#ibcon#[25=AT07-04\r\n] 2006.257.06:52:35.39#ibcon#*before write, iclass 38, count 2 2006.257.06:52:35.39#ibcon#enter sib2, iclass 38, count 2 2006.257.06:52:35.39#ibcon#flushed, iclass 38, count 2 2006.257.06:52:35.39#ibcon#about to write, iclass 38, count 2 2006.257.06:52:35.39#ibcon#wrote, iclass 38, count 2 2006.257.06:52:35.39#ibcon#about to read 3, iclass 38, count 2 2006.257.06:52:35.42#ibcon#read 3, iclass 38, count 2 2006.257.06:52:35.42#ibcon#about to read 4, iclass 38, count 2 2006.257.06:52:35.42#ibcon#read 4, iclass 38, count 2 2006.257.06:52:35.42#ibcon#about to read 5, iclass 38, count 2 2006.257.06:52:35.42#ibcon#read 5, iclass 38, count 2 2006.257.06:52:35.42#ibcon#about to read 6, iclass 38, count 2 2006.257.06:52:35.42#ibcon#read 6, iclass 38, count 2 2006.257.06:52:35.42#ibcon#end of sib2, iclass 38, count 2 2006.257.06:52:35.42#ibcon#*after write, iclass 38, count 2 2006.257.06:52:35.42#ibcon#*before return 0, iclass 38, count 2 2006.257.06:52:35.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:35.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:35.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.06:52:35.42#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:35.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:35.44#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:52:35.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:35.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:35.54#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:52:35.54#ibcon#first serial, iclass 38, count 0 2006.257.06:52:35.54#ibcon#enter sib2, iclass 38, count 0 2006.257.06:52:35.54#ibcon#flushed, iclass 38, count 0 2006.257.06:52:35.54#ibcon#about to write, iclass 38, count 0 2006.257.06:52:35.54#ibcon#wrote, iclass 38, count 0 2006.257.06:52:35.54#ibcon#about to read 3, iclass 38, count 0 2006.257.06:52:35.56#ibcon#read 3, iclass 38, count 0 2006.257.06:52:35.56#ibcon#about to read 4, iclass 38, count 0 2006.257.06:52:35.56#ibcon#read 4, iclass 38, count 0 2006.257.06:52:35.56#ibcon#about to read 5, iclass 38, count 0 2006.257.06:52:35.56#ibcon#read 5, iclass 38, count 0 2006.257.06:52:35.56#ibcon#about to read 6, iclass 38, count 0 2006.257.06:52:35.56#ibcon#read 6, iclass 38, count 0 2006.257.06:52:35.56#ibcon#end of sib2, iclass 38, count 0 2006.257.06:52:35.56#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:52:35.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:52:35.56#ibcon#[25=USB\r\n] 2006.257.06:52:35.56#ibcon#*before write, iclass 38, count 0 2006.257.06:52:35.56#ibcon#enter sib2, iclass 38, count 0 2006.257.06:52:35.56#ibcon#flushed, iclass 38, count 0 2006.257.06:52:35.56#ibcon#about to write, iclass 38, count 0 2006.257.06:52:35.56#ibcon#wrote, iclass 38, count 0 2006.257.06:52:35.56#ibcon#about to read 3, iclass 38, count 0 2006.257.06:52:35.59#ibcon#read 3, iclass 38, count 0 2006.257.06:52:35.59#ibcon#about to read 4, iclass 38, count 0 2006.257.06:52:35.59#ibcon#read 4, iclass 38, count 0 2006.257.06:52:35.59#ibcon#about to read 5, iclass 38, count 0 2006.257.06:52:35.59#ibcon#read 5, iclass 38, count 0 2006.257.06:52:35.59#ibcon#about to read 6, iclass 38, count 0 2006.257.06:52:35.59#ibcon#read 6, iclass 38, count 0 2006.257.06:52:35.59#ibcon#end of sib2, iclass 38, count 0 2006.257.06:52:35.59#ibcon#*after write, iclass 38, count 0 2006.257.06:52:35.59#ibcon#*before return 0, iclass 38, count 0 2006.257.06:52:35.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:35.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:35.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:52:35.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:52:35.59$vck44/valo=8,884.99 2006.257.06:52:35.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.06:52:35.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.06:52:35.59#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:35.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:35.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:35.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:35.59#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:52:35.59#ibcon#first serial, iclass 6, count 0 2006.257.06:52:35.59#ibcon#enter sib2, iclass 6, count 0 2006.257.06:52:35.59#ibcon#flushed, iclass 6, count 0 2006.257.06:52:35.59#ibcon#about to write, iclass 6, count 0 2006.257.06:52:35.59#ibcon#wrote, iclass 6, count 0 2006.257.06:52:35.59#ibcon#about to read 3, iclass 6, count 0 2006.257.06:52:35.61#ibcon#read 3, iclass 6, count 0 2006.257.06:52:35.61#ibcon#about to read 4, iclass 6, count 0 2006.257.06:52:35.61#ibcon#read 4, iclass 6, count 0 2006.257.06:52:35.61#ibcon#about to read 5, iclass 6, count 0 2006.257.06:52:35.61#ibcon#read 5, iclass 6, count 0 2006.257.06:52:35.61#ibcon#about to read 6, iclass 6, count 0 2006.257.06:52:35.61#ibcon#read 6, iclass 6, count 0 2006.257.06:52:35.61#ibcon#end of sib2, iclass 6, count 0 2006.257.06:52:35.61#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:52:35.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:52:35.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:52:35.61#ibcon#*before write, iclass 6, count 0 2006.257.06:52:35.61#ibcon#enter sib2, iclass 6, count 0 2006.257.06:52:35.61#ibcon#flushed, iclass 6, count 0 2006.257.06:52:35.61#ibcon#about to write, iclass 6, count 0 2006.257.06:52:35.61#ibcon#wrote, iclass 6, count 0 2006.257.06:52:35.61#ibcon#about to read 3, iclass 6, count 0 2006.257.06:52:35.65#ibcon#read 3, iclass 6, count 0 2006.257.06:52:35.65#ibcon#about to read 4, iclass 6, count 0 2006.257.06:52:35.65#ibcon#read 4, iclass 6, count 0 2006.257.06:52:35.65#ibcon#about to read 5, iclass 6, count 0 2006.257.06:52:35.65#ibcon#read 5, iclass 6, count 0 2006.257.06:52:35.65#ibcon#about to read 6, iclass 6, count 0 2006.257.06:52:35.65#ibcon#read 6, iclass 6, count 0 2006.257.06:52:35.65#ibcon#end of sib2, iclass 6, count 0 2006.257.06:52:35.65#ibcon#*after write, iclass 6, count 0 2006.257.06:52:35.65#ibcon#*before return 0, iclass 6, count 0 2006.257.06:52:35.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:35.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:35.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:52:35.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:52:35.65$vck44/va=8,4 2006.257.06:52:35.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.06:52:35.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.06:52:35.65#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:35.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:52:35.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:52:35.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:52:35.71#ibcon#enter wrdev, iclass 10, count 2 2006.257.06:52:35.71#ibcon#first serial, iclass 10, count 2 2006.257.06:52:35.71#ibcon#enter sib2, iclass 10, count 2 2006.257.06:52:35.71#ibcon#flushed, iclass 10, count 2 2006.257.06:52:35.71#ibcon#about to write, iclass 10, count 2 2006.257.06:52:35.71#ibcon#wrote, iclass 10, count 2 2006.257.06:52:35.71#ibcon#about to read 3, iclass 10, count 2 2006.257.06:52:35.73#ibcon#read 3, iclass 10, count 2 2006.257.06:52:35.73#ibcon#about to read 4, iclass 10, count 2 2006.257.06:52:35.73#ibcon#read 4, iclass 10, count 2 2006.257.06:52:35.73#ibcon#about to read 5, iclass 10, count 2 2006.257.06:52:35.73#ibcon#read 5, iclass 10, count 2 2006.257.06:52:35.73#ibcon#about to read 6, iclass 10, count 2 2006.257.06:52:35.73#ibcon#read 6, iclass 10, count 2 2006.257.06:52:35.73#ibcon#end of sib2, iclass 10, count 2 2006.257.06:52:35.73#ibcon#*mode == 0, iclass 10, count 2 2006.257.06:52:35.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.06:52:35.73#ibcon#[25=AT08-04\r\n] 2006.257.06:52:35.73#ibcon#*before write, iclass 10, count 2 2006.257.06:52:35.73#ibcon#enter sib2, iclass 10, count 2 2006.257.06:52:35.73#ibcon#flushed, iclass 10, count 2 2006.257.06:52:35.73#ibcon#about to write, iclass 10, count 2 2006.257.06:52:35.73#ibcon#wrote, iclass 10, count 2 2006.257.06:52:35.73#ibcon#about to read 3, iclass 10, count 2 2006.257.06:52:35.76#ibcon#read 3, iclass 10, count 2 2006.257.06:52:35.76#ibcon#about to read 4, iclass 10, count 2 2006.257.06:52:35.76#ibcon#read 4, iclass 10, count 2 2006.257.06:52:35.76#ibcon#about to read 5, iclass 10, count 2 2006.257.06:52:35.76#ibcon#read 5, iclass 10, count 2 2006.257.06:52:35.76#ibcon#about to read 6, iclass 10, count 2 2006.257.06:52:35.76#ibcon#read 6, iclass 10, count 2 2006.257.06:52:35.76#ibcon#end of sib2, iclass 10, count 2 2006.257.06:52:35.76#ibcon#*after write, iclass 10, count 2 2006.257.06:52:35.76#ibcon#*before return 0, iclass 10, count 2 2006.257.06:52:35.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:52:35.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.06:52:35.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.06:52:35.76#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:35.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:52:35.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:52:35.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:52:35.88#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:52:35.88#ibcon#first serial, iclass 10, count 0 2006.257.06:52:35.88#ibcon#enter sib2, iclass 10, count 0 2006.257.06:52:35.88#ibcon#flushed, iclass 10, count 0 2006.257.06:52:35.88#ibcon#about to write, iclass 10, count 0 2006.257.06:52:35.88#ibcon#wrote, iclass 10, count 0 2006.257.06:52:35.88#ibcon#about to read 3, iclass 10, count 0 2006.257.06:52:35.90#ibcon#read 3, iclass 10, count 0 2006.257.06:52:35.90#ibcon#about to read 4, iclass 10, count 0 2006.257.06:52:35.90#ibcon#read 4, iclass 10, count 0 2006.257.06:52:35.90#ibcon#about to read 5, iclass 10, count 0 2006.257.06:52:35.90#ibcon#read 5, iclass 10, count 0 2006.257.06:52:35.90#ibcon#about to read 6, iclass 10, count 0 2006.257.06:52:35.90#ibcon#read 6, iclass 10, count 0 2006.257.06:52:35.90#ibcon#end of sib2, iclass 10, count 0 2006.257.06:52:35.90#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:52:35.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:52:35.90#ibcon#[25=USB\r\n] 2006.257.06:52:35.90#ibcon#*before write, iclass 10, count 0 2006.257.06:52:35.90#ibcon#enter sib2, iclass 10, count 0 2006.257.06:52:35.90#ibcon#flushed, iclass 10, count 0 2006.257.06:52:35.90#ibcon#about to write, iclass 10, count 0 2006.257.06:52:35.90#ibcon#wrote, iclass 10, count 0 2006.257.06:52:35.90#ibcon#about to read 3, iclass 10, count 0 2006.257.06:52:35.93#ibcon#read 3, iclass 10, count 0 2006.257.06:52:35.93#ibcon#about to read 4, iclass 10, count 0 2006.257.06:52:35.93#ibcon#read 4, iclass 10, count 0 2006.257.06:52:35.93#ibcon#about to read 5, iclass 10, count 0 2006.257.06:52:35.93#ibcon#read 5, iclass 10, count 0 2006.257.06:52:35.93#ibcon#about to read 6, iclass 10, count 0 2006.257.06:52:35.93#ibcon#read 6, iclass 10, count 0 2006.257.06:52:35.93#ibcon#end of sib2, iclass 10, count 0 2006.257.06:52:35.93#ibcon#*after write, iclass 10, count 0 2006.257.06:52:35.93#ibcon#*before return 0, iclass 10, count 0 2006.257.06:52:35.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:52:35.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.06:52:35.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:52:35.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:52:35.93$vck44/vblo=1,629.99 2006.257.06:52:35.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.06:52:35.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.06:52:35.93#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:35.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:35.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:35.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:35.93#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:52:35.93#ibcon#first serial, iclass 12, count 0 2006.257.06:52:35.93#ibcon#enter sib2, iclass 12, count 0 2006.257.06:52:35.93#ibcon#flushed, iclass 12, count 0 2006.257.06:52:35.93#ibcon#about to write, iclass 12, count 0 2006.257.06:52:35.93#ibcon#wrote, iclass 12, count 0 2006.257.06:52:35.93#ibcon#about to read 3, iclass 12, count 0 2006.257.06:52:35.95#ibcon#read 3, iclass 12, count 0 2006.257.06:52:35.95#ibcon#about to read 4, iclass 12, count 0 2006.257.06:52:35.95#ibcon#read 4, iclass 12, count 0 2006.257.06:52:35.95#ibcon#about to read 5, iclass 12, count 0 2006.257.06:52:35.95#ibcon#read 5, iclass 12, count 0 2006.257.06:52:35.95#ibcon#about to read 6, iclass 12, count 0 2006.257.06:52:35.95#ibcon#read 6, iclass 12, count 0 2006.257.06:52:35.95#ibcon#end of sib2, iclass 12, count 0 2006.257.06:52:35.95#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:52:35.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:52:35.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:52:35.95#ibcon#*before write, iclass 12, count 0 2006.257.06:52:35.95#ibcon#enter sib2, iclass 12, count 0 2006.257.06:52:35.95#ibcon#flushed, iclass 12, count 0 2006.257.06:52:35.95#ibcon#about to write, iclass 12, count 0 2006.257.06:52:35.95#ibcon#wrote, iclass 12, count 0 2006.257.06:52:35.95#ibcon#about to read 3, iclass 12, count 0 2006.257.06:52:35.99#ibcon#read 3, iclass 12, count 0 2006.257.06:52:35.99#ibcon#about to read 4, iclass 12, count 0 2006.257.06:52:35.99#ibcon#read 4, iclass 12, count 0 2006.257.06:52:35.99#ibcon#about to read 5, iclass 12, count 0 2006.257.06:52:35.99#ibcon#read 5, iclass 12, count 0 2006.257.06:52:35.99#ibcon#about to read 6, iclass 12, count 0 2006.257.06:52:35.99#ibcon#read 6, iclass 12, count 0 2006.257.06:52:35.99#ibcon#end of sib2, iclass 12, count 0 2006.257.06:52:35.99#ibcon#*after write, iclass 12, count 0 2006.257.06:52:35.99#ibcon#*before return 0, iclass 12, count 0 2006.257.06:52:35.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:35.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.06:52:35.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:52:35.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:52:35.99$vck44/vb=1,4 2006.257.06:52:35.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.06:52:35.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.06:52:35.99#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:35.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:35.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:35.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:35.99#ibcon#enter wrdev, iclass 14, count 2 2006.257.06:52:35.99#ibcon#first serial, iclass 14, count 2 2006.257.06:52:35.99#ibcon#enter sib2, iclass 14, count 2 2006.257.06:52:35.99#ibcon#flushed, iclass 14, count 2 2006.257.06:52:35.99#ibcon#about to write, iclass 14, count 2 2006.257.06:52:35.99#ibcon#wrote, iclass 14, count 2 2006.257.06:52:35.99#ibcon#about to read 3, iclass 14, count 2 2006.257.06:52:36.01#ibcon#read 3, iclass 14, count 2 2006.257.06:52:36.01#ibcon#about to read 4, iclass 14, count 2 2006.257.06:52:36.01#ibcon#read 4, iclass 14, count 2 2006.257.06:52:36.01#ibcon#about to read 5, iclass 14, count 2 2006.257.06:52:36.01#ibcon#read 5, iclass 14, count 2 2006.257.06:52:36.01#ibcon#about to read 6, iclass 14, count 2 2006.257.06:52:36.01#ibcon#read 6, iclass 14, count 2 2006.257.06:52:36.01#ibcon#end of sib2, iclass 14, count 2 2006.257.06:52:36.01#ibcon#*mode == 0, iclass 14, count 2 2006.257.06:52:36.01#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.06:52:36.01#ibcon#[27=AT01-04\r\n] 2006.257.06:52:36.01#ibcon#*before write, iclass 14, count 2 2006.257.06:52:36.01#ibcon#enter sib2, iclass 14, count 2 2006.257.06:52:36.01#ibcon#flushed, iclass 14, count 2 2006.257.06:52:36.01#ibcon#about to write, iclass 14, count 2 2006.257.06:52:36.01#ibcon#wrote, iclass 14, count 2 2006.257.06:52:36.01#ibcon#about to read 3, iclass 14, count 2 2006.257.06:52:36.04#ibcon#read 3, iclass 14, count 2 2006.257.06:52:36.04#ibcon#about to read 4, iclass 14, count 2 2006.257.06:52:36.04#ibcon#read 4, iclass 14, count 2 2006.257.06:52:36.04#ibcon#about to read 5, iclass 14, count 2 2006.257.06:52:36.04#ibcon#read 5, iclass 14, count 2 2006.257.06:52:36.04#ibcon#about to read 6, iclass 14, count 2 2006.257.06:52:36.04#ibcon#read 6, iclass 14, count 2 2006.257.06:52:36.04#ibcon#end of sib2, iclass 14, count 2 2006.257.06:52:36.04#ibcon#*after write, iclass 14, count 2 2006.257.06:52:36.04#ibcon#*before return 0, iclass 14, count 2 2006.257.06:52:36.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:36.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.06:52:36.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.06:52:36.04#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:36.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:36.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:36.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:36.16#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:52:36.16#ibcon#first serial, iclass 14, count 0 2006.257.06:52:36.16#ibcon#enter sib2, iclass 14, count 0 2006.257.06:52:36.16#ibcon#flushed, iclass 14, count 0 2006.257.06:52:36.16#ibcon#about to write, iclass 14, count 0 2006.257.06:52:36.16#ibcon#wrote, iclass 14, count 0 2006.257.06:52:36.16#ibcon#about to read 3, iclass 14, count 0 2006.257.06:52:36.18#ibcon#read 3, iclass 14, count 0 2006.257.06:52:36.18#ibcon#about to read 4, iclass 14, count 0 2006.257.06:52:36.18#ibcon#read 4, iclass 14, count 0 2006.257.06:52:36.18#ibcon#about to read 5, iclass 14, count 0 2006.257.06:52:36.18#ibcon#read 5, iclass 14, count 0 2006.257.06:52:36.18#ibcon#about to read 6, iclass 14, count 0 2006.257.06:52:36.18#ibcon#read 6, iclass 14, count 0 2006.257.06:52:36.18#ibcon#end of sib2, iclass 14, count 0 2006.257.06:52:36.18#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:52:36.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:52:36.18#ibcon#[27=USB\r\n] 2006.257.06:52:36.18#ibcon#*before write, iclass 14, count 0 2006.257.06:52:36.18#ibcon#enter sib2, iclass 14, count 0 2006.257.06:52:36.18#ibcon#flushed, iclass 14, count 0 2006.257.06:52:36.18#ibcon#about to write, iclass 14, count 0 2006.257.06:52:36.18#ibcon#wrote, iclass 14, count 0 2006.257.06:52:36.18#ibcon#about to read 3, iclass 14, count 0 2006.257.06:52:36.21#ibcon#read 3, iclass 14, count 0 2006.257.06:52:36.21#ibcon#about to read 4, iclass 14, count 0 2006.257.06:52:36.21#ibcon#read 4, iclass 14, count 0 2006.257.06:52:36.21#ibcon#about to read 5, iclass 14, count 0 2006.257.06:52:36.21#ibcon#read 5, iclass 14, count 0 2006.257.06:52:36.21#ibcon#about to read 6, iclass 14, count 0 2006.257.06:52:36.21#ibcon#read 6, iclass 14, count 0 2006.257.06:52:36.21#ibcon#end of sib2, iclass 14, count 0 2006.257.06:52:36.21#ibcon#*after write, iclass 14, count 0 2006.257.06:52:36.21#ibcon#*before return 0, iclass 14, count 0 2006.257.06:52:36.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:36.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.06:52:36.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:52:36.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:52:36.21$vck44/vblo=2,634.99 2006.257.06:52:36.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.06:52:36.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.06:52:36.21#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:36.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:36.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:36.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:36.21#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:52:36.21#ibcon#first serial, iclass 16, count 0 2006.257.06:52:36.21#ibcon#enter sib2, iclass 16, count 0 2006.257.06:52:36.21#ibcon#flushed, iclass 16, count 0 2006.257.06:52:36.21#ibcon#about to write, iclass 16, count 0 2006.257.06:52:36.21#ibcon#wrote, iclass 16, count 0 2006.257.06:52:36.21#ibcon#about to read 3, iclass 16, count 0 2006.257.06:52:36.23#ibcon#read 3, iclass 16, count 0 2006.257.06:52:36.23#ibcon#about to read 4, iclass 16, count 0 2006.257.06:52:36.23#ibcon#read 4, iclass 16, count 0 2006.257.06:52:36.23#ibcon#about to read 5, iclass 16, count 0 2006.257.06:52:36.23#ibcon#read 5, iclass 16, count 0 2006.257.06:52:36.23#ibcon#about to read 6, iclass 16, count 0 2006.257.06:52:36.23#ibcon#read 6, iclass 16, count 0 2006.257.06:52:36.23#ibcon#end of sib2, iclass 16, count 0 2006.257.06:52:36.23#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:52:36.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:52:36.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:52:36.23#ibcon#*before write, iclass 16, count 0 2006.257.06:52:36.23#ibcon#enter sib2, iclass 16, count 0 2006.257.06:52:36.23#ibcon#flushed, iclass 16, count 0 2006.257.06:52:36.23#ibcon#about to write, iclass 16, count 0 2006.257.06:52:36.23#ibcon#wrote, iclass 16, count 0 2006.257.06:52:36.23#ibcon#about to read 3, iclass 16, count 0 2006.257.06:52:36.27#ibcon#read 3, iclass 16, count 0 2006.257.06:52:36.27#ibcon#about to read 4, iclass 16, count 0 2006.257.06:52:36.27#ibcon#read 4, iclass 16, count 0 2006.257.06:52:36.27#ibcon#about to read 5, iclass 16, count 0 2006.257.06:52:36.27#ibcon#read 5, iclass 16, count 0 2006.257.06:52:36.27#ibcon#about to read 6, iclass 16, count 0 2006.257.06:52:36.27#ibcon#read 6, iclass 16, count 0 2006.257.06:52:36.27#ibcon#end of sib2, iclass 16, count 0 2006.257.06:52:36.27#ibcon#*after write, iclass 16, count 0 2006.257.06:52:36.27#ibcon#*before return 0, iclass 16, count 0 2006.257.06:52:36.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:36.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.06:52:36.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:52:36.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:52:36.27$vck44/vb=2,5 2006.257.06:52:36.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.06:52:36.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.06:52:36.27#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:36.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:36.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:36.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:36.33#ibcon#enter wrdev, iclass 18, count 2 2006.257.06:52:36.33#ibcon#first serial, iclass 18, count 2 2006.257.06:52:36.33#ibcon#enter sib2, iclass 18, count 2 2006.257.06:52:36.33#ibcon#flushed, iclass 18, count 2 2006.257.06:52:36.33#ibcon#about to write, iclass 18, count 2 2006.257.06:52:36.33#ibcon#wrote, iclass 18, count 2 2006.257.06:52:36.33#ibcon#about to read 3, iclass 18, count 2 2006.257.06:52:36.35#ibcon#read 3, iclass 18, count 2 2006.257.06:52:36.35#ibcon#about to read 4, iclass 18, count 2 2006.257.06:52:36.35#ibcon#read 4, iclass 18, count 2 2006.257.06:52:36.35#ibcon#about to read 5, iclass 18, count 2 2006.257.06:52:36.35#ibcon#read 5, iclass 18, count 2 2006.257.06:52:36.35#ibcon#about to read 6, iclass 18, count 2 2006.257.06:52:36.35#ibcon#read 6, iclass 18, count 2 2006.257.06:52:36.35#ibcon#end of sib2, iclass 18, count 2 2006.257.06:52:36.35#ibcon#*mode == 0, iclass 18, count 2 2006.257.06:52:36.35#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.06:52:36.35#ibcon#[27=AT02-05\r\n] 2006.257.06:52:36.35#ibcon#*before write, iclass 18, count 2 2006.257.06:52:36.35#ibcon#enter sib2, iclass 18, count 2 2006.257.06:52:36.35#ibcon#flushed, iclass 18, count 2 2006.257.06:52:36.35#ibcon#about to write, iclass 18, count 2 2006.257.06:52:36.35#ibcon#wrote, iclass 18, count 2 2006.257.06:52:36.35#ibcon#about to read 3, iclass 18, count 2 2006.257.06:52:36.38#ibcon#read 3, iclass 18, count 2 2006.257.06:52:36.38#ibcon#about to read 4, iclass 18, count 2 2006.257.06:52:36.38#ibcon#read 4, iclass 18, count 2 2006.257.06:52:36.38#ibcon#about to read 5, iclass 18, count 2 2006.257.06:52:36.38#ibcon#read 5, iclass 18, count 2 2006.257.06:52:36.38#ibcon#about to read 6, iclass 18, count 2 2006.257.06:52:36.38#ibcon#read 6, iclass 18, count 2 2006.257.06:52:36.38#ibcon#end of sib2, iclass 18, count 2 2006.257.06:52:36.38#ibcon#*after write, iclass 18, count 2 2006.257.06:52:36.38#ibcon#*before return 0, iclass 18, count 2 2006.257.06:52:36.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:36.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.06:52:36.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.06:52:36.38#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:36.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:36.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:36.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:36.50#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:52:36.50#ibcon#first serial, iclass 18, count 0 2006.257.06:52:36.50#ibcon#enter sib2, iclass 18, count 0 2006.257.06:52:36.50#ibcon#flushed, iclass 18, count 0 2006.257.06:52:36.50#ibcon#about to write, iclass 18, count 0 2006.257.06:52:36.50#ibcon#wrote, iclass 18, count 0 2006.257.06:52:36.50#ibcon#about to read 3, iclass 18, count 0 2006.257.06:52:36.52#ibcon#read 3, iclass 18, count 0 2006.257.06:52:36.52#ibcon#about to read 4, iclass 18, count 0 2006.257.06:52:36.52#ibcon#read 4, iclass 18, count 0 2006.257.06:52:36.52#ibcon#about to read 5, iclass 18, count 0 2006.257.06:52:36.52#ibcon#read 5, iclass 18, count 0 2006.257.06:52:36.52#ibcon#about to read 6, iclass 18, count 0 2006.257.06:52:36.52#ibcon#read 6, iclass 18, count 0 2006.257.06:52:36.52#ibcon#end of sib2, iclass 18, count 0 2006.257.06:52:36.52#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:52:36.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:52:36.52#ibcon#[27=USB\r\n] 2006.257.06:52:36.52#ibcon#*before write, iclass 18, count 0 2006.257.06:52:36.52#ibcon#enter sib2, iclass 18, count 0 2006.257.06:52:36.52#ibcon#flushed, iclass 18, count 0 2006.257.06:52:36.52#ibcon#about to write, iclass 18, count 0 2006.257.06:52:36.52#ibcon#wrote, iclass 18, count 0 2006.257.06:52:36.52#ibcon#about to read 3, iclass 18, count 0 2006.257.06:52:36.55#ibcon#read 3, iclass 18, count 0 2006.257.06:52:36.55#ibcon#about to read 4, iclass 18, count 0 2006.257.06:52:36.55#ibcon#read 4, iclass 18, count 0 2006.257.06:52:36.55#ibcon#about to read 5, iclass 18, count 0 2006.257.06:52:36.55#ibcon#read 5, iclass 18, count 0 2006.257.06:52:36.55#ibcon#about to read 6, iclass 18, count 0 2006.257.06:52:36.55#ibcon#read 6, iclass 18, count 0 2006.257.06:52:36.55#ibcon#end of sib2, iclass 18, count 0 2006.257.06:52:36.55#ibcon#*after write, iclass 18, count 0 2006.257.06:52:36.55#ibcon#*before return 0, iclass 18, count 0 2006.257.06:52:36.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:36.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.06:52:36.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:52:36.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:52:36.55$vck44/vblo=3,649.99 2006.257.06:52:36.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.06:52:36.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.06:52:36.55#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:36.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:36.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:36.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:36.55#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:52:36.55#ibcon#first serial, iclass 20, count 0 2006.257.06:52:36.55#ibcon#enter sib2, iclass 20, count 0 2006.257.06:52:36.55#ibcon#flushed, iclass 20, count 0 2006.257.06:52:36.55#ibcon#about to write, iclass 20, count 0 2006.257.06:52:36.55#ibcon#wrote, iclass 20, count 0 2006.257.06:52:36.55#ibcon#about to read 3, iclass 20, count 0 2006.257.06:52:36.57#ibcon#read 3, iclass 20, count 0 2006.257.06:52:36.57#ibcon#about to read 4, iclass 20, count 0 2006.257.06:52:36.57#ibcon#read 4, iclass 20, count 0 2006.257.06:52:36.57#ibcon#about to read 5, iclass 20, count 0 2006.257.06:52:36.57#ibcon#read 5, iclass 20, count 0 2006.257.06:52:36.57#ibcon#about to read 6, iclass 20, count 0 2006.257.06:52:36.57#ibcon#read 6, iclass 20, count 0 2006.257.06:52:36.57#ibcon#end of sib2, iclass 20, count 0 2006.257.06:52:36.57#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:52:36.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:52:36.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:52:36.57#ibcon#*before write, iclass 20, count 0 2006.257.06:52:36.57#ibcon#enter sib2, iclass 20, count 0 2006.257.06:52:36.57#ibcon#flushed, iclass 20, count 0 2006.257.06:52:36.57#ibcon#about to write, iclass 20, count 0 2006.257.06:52:36.57#ibcon#wrote, iclass 20, count 0 2006.257.06:52:36.57#ibcon#about to read 3, iclass 20, count 0 2006.257.06:52:36.61#ibcon#read 3, iclass 20, count 0 2006.257.06:52:36.61#ibcon#about to read 4, iclass 20, count 0 2006.257.06:52:36.61#ibcon#read 4, iclass 20, count 0 2006.257.06:52:36.61#ibcon#about to read 5, iclass 20, count 0 2006.257.06:52:36.61#ibcon#read 5, iclass 20, count 0 2006.257.06:52:36.61#ibcon#about to read 6, iclass 20, count 0 2006.257.06:52:36.61#ibcon#read 6, iclass 20, count 0 2006.257.06:52:36.61#ibcon#end of sib2, iclass 20, count 0 2006.257.06:52:36.61#ibcon#*after write, iclass 20, count 0 2006.257.06:52:36.61#ibcon#*before return 0, iclass 20, count 0 2006.257.06:52:36.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:36.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.06:52:36.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:52:36.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:52:36.61$vck44/vb=3,4 2006.257.06:52:36.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.06:52:36.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.06:52:36.61#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:36.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:36.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:36.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:36.67#ibcon#enter wrdev, iclass 22, count 2 2006.257.06:52:36.67#ibcon#first serial, iclass 22, count 2 2006.257.06:52:36.67#ibcon#enter sib2, iclass 22, count 2 2006.257.06:52:36.67#ibcon#flushed, iclass 22, count 2 2006.257.06:52:36.67#ibcon#about to write, iclass 22, count 2 2006.257.06:52:36.67#ibcon#wrote, iclass 22, count 2 2006.257.06:52:36.67#ibcon#about to read 3, iclass 22, count 2 2006.257.06:52:36.69#ibcon#read 3, iclass 22, count 2 2006.257.06:52:36.69#ibcon#about to read 4, iclass 22, count 2 2006.257.06:52:36.69#ibcon#read 4, iclass 22, count 2 2006.257.06:52:36.69#ibcon#about to read 5, iclass 22, count 2 2006.257.06:52:36.69#ibcon#read 5, iclass 22, count 2 2006.257.06:52:36.69#ibcon#about to read 6, iclass 22, count 2 2006.257.06:52:36.69#ibcon#read 6, iclass 22, count 2 2006.257.06:52:36.69#ibcon#end of sib2, iclass 22, count 2 2006.257.06:52:36.69#ibcon#*mode == 0, iclass 22, count 2 2006.257.06:52:36.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.06:52:36.69#ibcon#[27=AT03-04\r\n] 2006.257.06:52:36.69#ibcon#*before write, iclass 22, count 2 2006.257.06:52:36.69#ibcon#enter sib2, iclass 22, count 2 2006.257.06:52:36.69#ibcon#flushed, iclass 22, count 2 2006.257.06:52:36.69#ibcon#about to write, iclass 22, count 2 2006.257.06:52:36.69#ibcon#wrote, iclass 22, count 2 2006.257.06:52:36.69#ibcon#about to read 3, iclass 22, count 2 2006.257.06:52:36.72#ibcon#read 3, iclass 22, count 2 2006.257.06:52:36.72#ibcon#about to read 4, iclass 22, count 2 2006.257.06:52:36.72#ibcon#read 4, iclass 22, count 2 2006.257.06:52:36.72#ibcon#about to read 5, iclass 22, count 2 2006.257.06:52:36.72#ibcon#read 5, iclass 22, count 2 2006.257.06:52:36.72#ibcon#about to read 6, iclass 22, count 2 2006.257.06:52:36.72#ibcon#read 6, iclass 22, count 2 2006.257.06:52:36.72#ibcon#end of sib2, iclass 22, count 2 2006.257.06:52:36.72#ibcon#*after write, iclass 22, count 2 2006.257.06:52:36.72#ibcon#*before return 0, iclass 22, count 2 2006.257.06:52:36.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:36.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.06:52:36.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.06:52:36.72#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:36.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:36.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:36.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:36.84#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:52:36.84#ibcon#first serial, iclass 22, count 0 2006.257.06:52:36.84#ibcon#enter sib2, iclass 22, count 0 2006.257.06:52:36.84#ibcon#flushed, iclass 22, count 0 2006.257.06:52:36.84#ibcon#about to write, iclass 22, count 0 2006.257.06:52:36.84#ibcon#wrote, iclass 22, count 0 2006.257.06:52:36.84#ibcon#about to read 3, iclass 22, count 0 2006.257.06:52:36.86#ibcon#read 3, iclass 22, count 0 2006.257.06:52:36.86#ibcon#about to read 4, iclass 22, count 0 2006.257.06:52:36.86#ibcon#read 4, iclass 22, count 0 2006.257.06:52:36.86#ibcon#about to read 5, iclass 22, count 0 2006.257.06:52:36.86#ibcon#read 5, iclass 22, count 0 2006.257.06:52:36.86#ibcon#about to read 6, iclass 22, count 0 2006.257.06:52:36.86#ibcon#read 6, iclass 22, count 0 2006.257.06:52:36.86#ibcon#end of sib2, iclass 22, count 0 2006.257.06:52:36.86#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:52:36.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:52:36.86#ibcon#[27=USB\r\n] 2006.257.06:52:36.86#ibcon#*before write, iclass 22, count 0 2006.257.06:52:36.86#ibcon#enter sib2, iclass 22, count 0 2006.257.06:52:36.86#ibcon#flushed, iclass 22, count 0 2006.257.06:52:36.86#ibcon#about to write, iclass 22, count 0 2006.257.06:52:36.86#ibcon#wrote, iclass 22, count 0 2006.257.06:52:36.86#ibcon#about to read 3, iclass 22, count 0 2006.257.06:52:36.89#ibcon#read 3, iclass 22, count 0 2006.257.06:52:36.89#ibcon#about to read 4, iclass 22, count 0 2006.257.06:52:36.89#ibcon#read 4, iclass 22, count 0 2006.257.06:52:36.89#ibcon#about to read 5, iclass 22, count 0 2006.257.06:52:36.89#ibcon#read 5, iclass 22, count 0 2006.257.06:52:36.89#ibcon#about to read 6, iclass 22, count 0 2006.257.06:52:36.89#ibcon#read 6, iclass 22, count 0 2006.257.06:52:36.89#ibcon#end of sib2, iclass 22, count 0 2006.257.06:52:36.89#ibcon#*after write, iclass 22, count 0 2006.257.06:52:36.89#ibcon#*before return 0, iclass 22, count 0 2006.257.06:52:36.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:36.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.06:52:36.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:52:36.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:52:36.89$vck44/vblo=4,679.99 2006.257.06:52:36.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.06:52:36.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.06:52:36.89#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:36.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:36.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:36.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:36.89#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:52:36.89#ibcon#first serial, iclass 24, count 0 2006.257.06:52:36.89#ibcon#enter sib2, iclass 24, count 0 2006.257.06:52:36.89#ibcon#flushed, iclass 24, count 0 2006.257.06:52:36.89#ibcon#about to write, iclass 24, count 0 2006.257.06:52:36.89#ibcon#wrote, iclass 24, count 0 2006.257.06:52:36.89#ibcon#about to read 3, iclass 24, count 0 2006.257.06:52:36.91#ibcon#read 3, iclass 24, count 0 2006.257.06:52:36.91#ibcon#about to read 4, iclass 24, count 0 2006.257.06:52:36.91#ibcon#read 4, iclass 24, count 0 2006.257.06:52:36.91#ibcon#about to read 5, iclass 24, count 0 2006.257.06:52:36.91#ibcon#read 5, iclass 24, count 0 2006.257.06:52:36.91#ibcon#about to read 6, iclass 24, count 0 2006.257.06:52:36.91#ibcon#read 6, iclass 24, count 0 2006.257.06:52:36.91#ibcon#end of sib2, iclass 24, count 0 2006.257.06:52:36.91#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:52:36.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:52:36.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:52:36.91#ibcon#*before write, iclass 24, count 0 2006.257.06:52:36.91#ibcon#enter sib2, iclass 24, count 0 2006.257.06:52:36.91#ibcon#flushed, iclass 24, count 0 2006.257.06:52:36.91#ibcon#about to write, iclass 24, count 0 2006.257.06:52:36.91#ibcon#wrote, iclass 24, count 0 2006.257.06:52:36.91#ibcon#about to read 3, iclass 24, count 0 2006.257.06:52:36.95#ibcon#read 3, iclass 24, count 0 2006.257.06:52:36.95#ibcon#about to read 4, iclass 24, count 0 2006.257.06:52:36.95#ibcon#read 4, iclass 24, count 0 2006.257.06:52:36.95#ibcon#about to read 5, iclass 24, count 0 2006.257.06:52:36.95#ibcon#read 5, iclass 24, count 0 2006.257.06:52:36.95#ibcon#about to read 6, iclass 24, count 0 2006.257.06:52:36.95#ibcon#read 6, iclass 24, count 0 2006.257.06:52:36.95#ibcon#end of sib2, iclass 24, count 0 2006.257.06:52:36.95#ibcon#*after write, iclass 24, count 0 2006.257.06:52:36.95#ibcon#*before return 0, iclass 24, count 0 2006.257.06:52:36.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:36.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.06:52:36.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:52:36.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:52:36.95$vck44/vb=4,5 2006.257.06:52:36.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.06:52:36.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.06:52:36.95#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:36.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:37.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:37.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:37.01#ibcon#enter wrdev, iclass 26, count 2 2006.257.06:52:37.01#ibcon#first serial, iclass 26, count 2 2006.257.06:52:37.01#ibcon#enter sib2, iclass 26, count 2 2006.257.06:52:37.01#ibcon#flushed, iclass 26, count 2 2006.257.06:52:37.01#ibcon#about to write, iclass 26, count 2 2006.257.06:52:37.01#ibcon#wrote, iclass 26, count 2 2006.257.06:52:37.01#ibcon#about to read 3, iclass 26, count 2 2006.257.06:52:37.03#ibcon#read 3, iclass 26, count 2 2006.257.06:52:37.03#ibcon#about to read 4, iclass 26, count 2 2006.257.06:52:37.03#ibcon#read 4, iclass 26, count 2 2006.257.06:52:37.03#ibcon#about to read 5, iclass 26, count 2 2006.257.06:52:37.03#ibcon#read 5, iclass 26, count 2 2006.257.06:52:37.03#ibcon#about to read 6, iclass 26, count 2 2006.257.06:52:37.03#ibcon#read 6, iclass 26, count 2 2006.257.06:52:37.03#ibcon#end of sib2, iclass 26, count 2 2006.257.06:52:37.03#ibcon#*mode == 0, iclass 26, count 2 2006.257.06:52:37.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.06:52:37.03#ibcon#[27=AT04-05\r\n] 2006.257.06:52:37.03#ibcon#*before write, iclass 26, count 2 2006.257.06:52:37.03#ibcon#enter sib2, iclass 26, count 2 2006.257.06:52:37.03#ibcon#flushed, iclass 26, count 2 2006.257.06:52:37.03#ibcon#about to write, iclass 26, count 2 2006.257.06:52:37.03#ibcon#wrote, iclass 26, count 2 2006.257.06:52:37.03#ibcon#about to read 3, iclass 26, count 2 2006.257.06:52:37.06#ibcon#read 3, iclass 26, count 2 2006.257.06:52:37.06#ibcon#about to read 4, iclass 26, count 2 2006.257.06:52:37.06#ibcon#read 4, iclass 26, count 2 2006.257.06:52:37.06#ibcon#about to read 5, iclass 26, count 2 2006.257.06:52:37.06#ibcon#read 5, iclass 26, count 2 2006.257.06:52:37.06#ibcon#about to read 6, iclass 26, count 2 2006.257.06:52:37.06#ibcon#read 6, iclass 26, count 2 2006.257.06:52:37.06#ibcon#end of sib2, iclass 26, count 2 2006.257.06:52:37.06#ibcon#*after write, iclass 26, count 2 2006.257.06:52:37.06#ibcon#*before return 0, iclass 26, count 2 2006.257.06:52:37.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:37.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.06:52:37.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.06:52:37.06#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:37.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:37.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:37.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:37.18#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:52:37.18#ibcon#first serial, iclass 26, count 0 2006.257.06:52:37.18#ibcon#enter sib2, iclass 26, count 0 2006.257.06:52:37.18#ibcon#flushed, iclass 26, count 0 2006.257.06:52:37.18#ibcon#about to write, iclass 26, count 0 2006.257.06:52:37.18#ibcon#wrote, iclass 26, count 0 2006.257.06:52:37.18#ibcon#about to read 3, iclass 26, count 0 2006.257.06:52:37.20#ibcon#read 3, iclass 26, count 0 2006.257.06:52:37.20#ibcon#about to read 4, iclass 26, count 0 2006.257.06:52:37.20#ibcon#read 4, iclass 26, count 0 2006.257.06:52:37.20#ibcon#about to read 5, iclass 26, count 0 2006.257.06:52:37.20#ibcon#read 5, iclass 26, count 0 2006.257.06:52:37.20#ibcon#about to read 6, iclass 26, count 0 2006.257.06:52:37.20#ibcon#read 6, iclass 26, count 0 2006.257.06:52:37.20#ibcon#end of sib2, iclass 26, count 0 2006.257.06:52:37.20#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:52:37.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:52:37.20#ibcon#[27=USB\r\n] 2006.257.06:52:37.20#ibcon#*before write, iclass 26, count 0 2006.257.06:52:37.20#ibcon#enter sib2, iclass 26, count 0 2006.257.06:52:37.20#ibcon#flushed, iclass 26, count 0 2006.257.06:52:37.20#ibcon#about to write, iclass 26, count 0 2006.257.06:52:37.20#ibcon#wrote, iclass 26, count 0 2006.257.06:52:37.20#ibcon#about to read 3, iclass 26, count 0 2006.257.06:52:37.23#ibcon#read 3, iclass 26, count 0 2006.257.06:52:37.23#ibcon#about to read 4, iclass 26, count 0 2006.257.06:52:37.23#ibcon#read 4, iclass 26, count 0 2006.257.06:52:37.23#ibcon#about to read 5, iclass 26, count 0 2006.257.06:52:37.23#ibcon#read 5, iclass 26, count 0 2006.257.06:52:37.23#ibcon#about to read 6, iclass 26, count 0 2006.257.06:52:37.23#ibcon#read 6, iclass 26, count 0 2006.257.06:52:37.23#ibcon#end of sib2, iclass 26, count 0 2006.257.06:52:37.23#ibcon#*after write, iclass 26, count 0 2006.257.06:52:37.23#ibcon#*before return 0, iclass 26, count 0 2006.257.06:52:37.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:37.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.06:52:37.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:52:37.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:52:37.23$vck44/vblo=5,709.99 2006.257.06:52:37.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.06:52:37.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.06:52:37.23#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:37.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:37.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:37.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:37.23#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:52:37.23#ibcon#first serial, iclass 28, count 0 2006.257.06:52:37.23#ibcon#enter sib2, iclass 28, count 0 2006.257.06:52:37.23#ibcon#flushed, iclass 28, count 0 2006.257.06:52:37.23#ibcon#about to write, iclass 28, count 0 2006.257.06:52:37.23#ibcon#wrote, iclass 28, count 0 2006.257.06:52:37.23#ibcon#about to read 3, iclass 28, count 0 2006.257.06:52:37.25#ibcon#read 3, iclass 28, count 0 2006.257.06:52:37.25#ibcon#about to read 4, iclass 28, count 0 2006.257.06:52:37.25#ibcon#read 4, iclass 28, count 0 2006.257.06:52:37.25#ibcon#about to read 5, iclass 28, count 0 2006.257.06:52:37.25#ibcon#read 5, iclass 28, count 0 2006.257.06:52:37.25#ibcon#about to read 6, iclass 28, count 0 2006.257.06:52:37.25#ibcon#read 6, iclass 28, count 0 2006.257.06:52:37.25#ibcon#end of sib2, iclass 28, count 0 2006.257.06:52:37.25#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:52:37.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:52:37.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:52:37.25#ibcon#*before write, iclass 28, count 0 2006.257.06:52:37.25#ibcon#enter sib2, iclass 28, count 0 2006.257.06:52:37.25#ibcon#flushed, iclass 28, count 0 2006.257.06:52:37.25#ibcon#about to write, iclass 28, count 0 2006.257.06:52:37.25#ibcon#wrote, iclass 28, count 0 2006.257.06:52:37.25#ibcon#about to read 3, iclass 28, count 0 2006.257.06:52:37.29#ibcon#read 3, iclass 28, count 0 2006.257.06:52:37.29#ibcon#about to read 4, iclass 28, count 0 2006.257.06:52:37.29#ibcon#read 4, iclass 28, count 0 2006.257.06:52:37.29#ibcon#about to read 5, iclass 28, count 0 2006.257.06:52:37.29#ibcon#read 5, iclass 28, count 0 2006.257.06:52:37.29#ibcon#about to read 6, iclass 28, count 0 2006.257.06:52:37.29#ibcon#read 6, iclass 28, count 0 2006.257.06:52:37.29#ibcon#end of sib2, iclass 28, count 0 2006.257.06:52:37.29#ibcon#*after write, iclass 28, count 0 2006.257.06:52:37.29#ibcon#*before return 0, iclass 28, count 0 2006.257.06:52:37.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:37.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.06:52:37.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:52:37.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:52:37.29$vck44/vb=5,4 2006.257.06:52:37.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.06:52:37.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.06:52:37.29#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:37.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:37.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:37.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:37.35#ibcon#enter wrdev, iclass 30, count 2 2006.257.06:52:37.35#ibcon#first serial, iclass 30, count 2 2006.257.06:52:37.35#ibcon#enter sib2, iclass 30, count 2 2006.257.06:52:37.35#ibcon#flushed, iclass 30, count 2 2006.257.06:52:37.35#ibcon#about to write, iclass 30, count 2 2006.257.06:52:37.35#ibcon#wrote, iclass 30, count 2 2006.257.06:52:37.35#ibcon#about to read 3, iclass 30, count 2 2006.257.06:52:37.37#ibcon#read 3, iclass 30, count 2 2006.257.06:52:37.37#ibcon#about to read 4, iclass 30, count 2 2006.257.06:52:37.37#ibcon#read 4, iclass 30, count 2 2006.257.06:52:37.37#ibcon#about to read 5, iclass 30, count 2 2006.257.06:52:37.37#ibcon#read 5, iclass 30, count 2 2006.257.06:52:37.37#ibcon#about to read 6, iclass 30, count 2 2006.257.06:52:37.37#ibcon#read 6, iclass 30, count 2 2006.257.06:52:37.37#ibcon#end of sib2, iclass 30, count 2 2006.257.06:52:37.37#ibcon#*mode == 0, iclass 30, count 2 2006.257.06:52:37.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.06:52:37.37#ibcon#[27=AT05-04\r\n] 2006.257.06:52:37.37#ibcon#*before write, iclass 30, count 2 2006.257.06:52:37.37#ibcon#enter sib2, iclass 30, count 2 2006.257.06:52:37.37#ibcon#flushed, iclass 30, count 2 2006.257.06:52:37.37#ibcon#about to write, iclass 30, count 2 2006.257.06:52:37.37#ibcon#wrote, iclass 30, count 2 2006.257.06:52:37.37#ibcon#about to read 3, iclass 30, count 2 2006.257.06:52:37.40#ibcon#read 3, iclass 30, count 2 2006.257.06:52:37.40#ibcon#about to read 4, iclass 30, count 2 2006.257.06:52:37.40#ibcon#read 4, iclass 30, count 2 2006.257.06:52:37.40#ibcon#about to read 5, iclass 30, count 2 2006.257.06:52:37.40#ibcon#read 5, iclass 30, count 2 2006.257.06:52:37.40#ibcon#about to read 6, iclass 30, count 2 2006.257.06:52:37.40#ibcon#read 6, iclass 30, count 2 2006.257.06:52:37.40#ibcon#end of sib2, iclass 30, count 2 2006.257.06:52:37.40#ibcon#*after write, iclass 30, count 2 2006.257.06:52:37.40#ibcon#*before return 0, iclass 30, count 2 2006.257.06:52:37.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:37.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.06:52:37.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.06:52:37.40#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:37.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:37.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:37.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:37.52#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:52:37.52#ibcon#first serial, iclass 30, count 0 2006.257.06:52:37.52#ibcon#enter sib2, iclass 30, count 0 2006.257.06:52:37.52#ibcon#flushed, iclass 30, count 0 2006.257.06:52:37.52#ibcon#about to write, iclass 30, count 0 2006.257.06:52:37.52#ibcon#wrote, iclass 30, count 0 2006.257.06:52:37.52#ibcon#about to read 3, iclass 30, count 0 2006.257.06:52:37.54#ibcon#read 3, iclass 30, count 0 2006.257.06:52:37.54#ibcon#about to read 4, iclass 30, count 0 2006.257.06:52:37.54#ibcon#read 4, iclass 30, count 0 2006.257.06:52:37.54#ibcon#about to read 5, iclass 30, count 0 2006.257.06:52:37.54#ibcon#read 5, iclass 30, count 0 2006.257.06:52:37.54#ibcon#about to read 6, iclass 30, count 0 2006.257.06:52:37.54#ibcon#read 6, iclass 30, count 0 2006.257.06:52:37.54#ibcon#end of sib2, iclass 30, count 0 2006.257.06:52:37.54#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:52:37.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:52:37.54#ibcon#[27=USB\r\n] 2006.257.06:52:37.54#ibcon#*before write, iclass 30, count 0 2006.257.06:52:37.54#ibcon#enter sib2, iclass 30, count 0 2006.257.06:52:37.54#ibcon#flushed, iclass 30, count 0 2006.257.06:52:37.54#ibcon#about to write, iclass 30, count 0 2006.257.06:52:37.54#ibcon#wrote, iclass 30, count 0 2006.257.06:52:37.54#ibcon#about to read 3, iclass 30, count 0 2006.257.06:52:37.57#ibcon#read 3, iclass 30, count 0 2006.257.06:52:37.57#ibcon#about to read 4, iclass 30, count 0 2006.257.06:52:37.57#ibcon#read 4, iclass 30, count 0 2006.257.06:52:37.57#ibcon#about to read 5, iclass 30, count 0 2006.257.06:52:37.57#ibcon#read 5, iclass 30, count 0 2006.257.06:52:37.57#ibcon#about to read 6, iclass 30, count 0 2006.257.06:52:37.57#ibcon#read 6, iclass 30, count 0 2006.257.06:52:37.57#ibcon#end of sib2, iclass 30, count 0 2006.257.06:52:37.57#ibcon#*after write, iclass 30, count 0 2006.257.06:52:37.57#ibcon#*before return 0, iclass 30, count 0 2006.257.06:52:37.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:37.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.06:52:37.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:52:37.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:52:37.57$vck44/vblo=6,719.99 2006.257.06:52:37.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.06:52:37.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.06:52:37.57#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:37.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:37.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:37.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:37.57#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:52:37.57#ibcon#first serial, iclass 32, count 0 2006.257.06:52:37.57#ibcon#enter sib2, iclass 32, count 0 2006.257.06:52:37.57#ibcon#flushed, iclass 32, count 0 2006.257.06:52:37.57#ibcon#about to write, iclass 32, count 0 2006.257.06:52:37.57#ibcon#wrote, iclass 32, count 0 2006.257.06:52:37.57#ibcon#about to read 3, iclass 32, count 0 2006.257.06:52:37.59#ibcon#read 3, iclass 32, count 0 2006.257.06:52:37.59#ibcon#about to read 4, iclass 32, count 0 2006.257.06:52:37.59#ibcon#read 4, iclass 32, count 0 2006.257.06:52:37.59#ibcon#about to read 5, iclass 32, count 0 2006.257.06:52:37.59#ibcon#read 5, iclass 32, count 0 2006.257.06:52:37.59#ibcon#about to read 6, iclass 32, count 0 2006.257.06:52:37.59#ibcon#read 6, iclass 32, count 0 2006.257.06:52:37.59#ibcon#end of sib2, iclass 32, count 0 2006.257.06:52:37.59#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:52:37.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:52:37.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:52:37.59#ibcon#*before write, iclass 32, count 0 2006.257.06:52:37.59#ibcon#enter sib2, iclass 32, count 0 2006.257.06:52:37.59#ibcon#flushed, iclass 32, count 0 2006.257.06:52:37.59#ibcon#about to write, iclass 32, count 0 2006.257.06:52:37.59#ibcon#wrote, iclass 32, count 0 2006.257.06:52:37.59#ibcon#about to read 3, iclass 32, count 0 2006.257.06:52:37.63#ibcon#read 3, iclass 32, count 0 2006.257.06:52:37.63#ibcon#about to read 4, iclass 32, count 0 2006.257.06:52:37.63#ibcon#read 4, iclass 32, count 0 2006.257.06:52:37.63#ibcon#about to read 5, iclass 32, count 0 2006.257.06:52:37.63#ibcon#read 5, iclass 32, count 0 2006.257.06:52:37.63#ibcon#about to read 6, iclass 32, count 0 2006.257.06:52:37.63#ibcon#read 6, iclass 32, count 0 2006.257.06:52:37.63#ibcon#end of sib2, iclass 32, count 0 2006.257.06:52:37.63#ibcon#*after write, iclass 32, count 0 2006.257.06:52:37.63#ibcon#*before return 0, iclass 32, count 0 2006.257.06:52:37.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:37.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.06:52:37.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:52:37.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:52:37.63$vck44/vb=6,4 2006.257.06:52:37.63#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.06:52:37.63#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.06:52:37.63#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:37.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:37.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:37.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:37.69#ibcon#enter wrdev, iclass 34, count 2 2006.257.06:52:37.69#ibcon#first serial, iclass 34, count 2 2006.257.06:52:37.69#ibcon#enter sib2, iclass 34, count 2 2006.257.06:52:37.69#ibcon#flushed, iclass 34, count 2 2006.257.06:52:37.69#ibcon#about to write, iclass 34, count 2 2006.257.06:52:37.69#ibcon#wrote, iclass 34, count 2 2006.257.06:52:37.69#ibcon#about to read 3, iclass 34, count 2 2006.257.06:52:37.71#ibcon#read 3, iclass 34, count 2 2006.257.06:52:37.71#ibcon#about to read 4, iclass 34, count 2 2006.257.06:52:37.71#ibcon#read 4, iclass 34, count 2 2006.257.06:52:37.71#ibcon#about to read 5, iclass 34, count 2 2006.257.06:52:37.71#ibcon#read 5, iclass 34, count 2 2006.257.06:52:37.71#ibcon#about to read 6, iclass 34, count 2 2006.257.06:52:37.71#ibcon#read 6, iclass 34, count 2 2006.257.06:52:37.71#ibcon#end of sib2, iclass 34, count 2 2006.257.06:52:37.71#ibcon#*mode == 0, iclass 34, count 2 2006.257.06:52:37.71#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.06:52:37.71#ibcon#[27=AT06-04\r\n] 2006.257.06:52:37.71#ibcon#*before write, iclass 34, count 2 2006.257.06:52:37.71#ibcon#enter sib2, iclass 34, count 2 2006.257.06:52:37.71#ibcon#flushed, iclass 34, count 2 2006.257.06:52:37.71#ibcon#about to write, iclass 34, count 2 2006.257.06:52:37.71#ibcon#wrote, iclass 34, count 2 2006.257.06:52:37.71#ibcon#about to read 3, iclass 34, count 2 2006.257.06:52:37.74#ibcon#read 3, iclass 34, count 2 2006.257.06:52:37.74#ibcon#about to read 4, iclass 34, count 2 2006.257.06:52:37.74#ibcon#read 4, iclass 34, count 2 2006.257.06:52:37.74#ibcon#about to read 5, iclass 34, count 2 2006.257.06:52:37.74#ibcon#read 5, iclass 34, count 2 2006.257.06:52:37.74#ibcon#about to read 6, iclass 34, count 2 2006.257.06:52:37.74#ibcon#read 6, iclass 34, count 2 2006.257.06:52:37.74#ibcon#end of sib2, iclass 34, count 2 2006.257.06:52:37.74#ibcon#*after write, iclass 34, count 2 2006.257.06:52:37.74#ibcon#*before return 0, iclass 34, count 2 2006.257.06:52:37.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:37.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.06:52:37.74#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.06:52:37.74#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:37.74#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:37.86#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:37.86#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:37.86#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:52:37.86#ibcon#first serial, iclass 34, count 0 2006.257.06:52:37.86#ibcon#enter sib2, iclass 34, count 0 2006.257.06:52:37.86#ibcon#flushed, iclass 34, count 0 2006.257.06:52:37.86#ibcon#about to write, iclass 34, count 0 2006.257.06:52:37.86#ibcon#wrote, iclass 34, count 0 2006.257.06:52:37.86#ibcon#about to read 3, iclass 34, count 0 2006.257.06:52:37.88#ibcon#read 3, iclass 34, count 0 2006.257.06:52:37.88#ibcon#about to read 4, iclass 34, count 0 2006.257.06:52:37.88#ibcon#read 4, iclass 34, count 0 2006.257.06:52:37.88#ibcon#about to read 5, iclass 34, count 0 2006.257.06:52:37.88#ibcon#read 5, iclass 34, count 0 2006.257.06:52:37.88#ibcon#about to read 6, iclass 34, count 0 2006.257.06:52:37.88#ibcon#read 6, iclass 34, count 0 2006.257.06:52:37.88#ibcon#end of sib2, iclass 34, count 0 2006.257.06:52:37.88#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:52:37.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:52:37.88#ibcon#[27=USB\r\n] 2006.257.06:52:37.88#ibcon#*before write, iclass 34, count 0 2006.257.06:52:37.88#ibcon#enter sib2, iclass 34, count 0 2006.257.06:52:37.88#ibcon#flushed, iclass 34, count 0 2006.257.06:52:37.88#ibcon#about to write, iclass 34, count 0 2006.257.06:52:37.88#ibcon#wrote, iclass 34, count 0 2006.257.06:52:37.88#ibcon#about to read 3, iclass 34, count 0 2006.257.06:52:37.91#ibcon#read 3, iclass 34, count 0 2006.257.06:52:37.91#ibcon#about to read 4, iclass 34, count 0 2006.257.06:52:37.91#ibcon#read 4, iclass 34, count 0 2006.257.06:52:37.91#ibcon#about to read 5, iclass 34, count 0 2006.257.06:52:37.91#ibcon#read 5, iclass 34, count 0 2006.257.06:52:37.91#ibcon#about to read 6, iclass 34, count 0 2006.257.06:52:37.91#ibcon#read 6, iclass 34, count 0 2006.257.06:52:37.91#ibcon#end of sib2, iclass 34, count 0 2006.257.06:52:37.91#ibcon#*after write, iclass 34, count 0 2006.257.06:52:37.91#ibcon#*before return 0, iclass 34, count 0 2006.257.06:52:37.91#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:37.91#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.06:52:37.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:52:37.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:52:37.91$vck44/vblo=7,734.99 2006.257.06:52:37.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.06:52:37.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.06:52:37.91#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:37.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:37.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:37.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:37.91#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:52:37.91#ibcon#first serial, iclass 36, count 0 2006.257.06:52:37.91#ibcon#enter sib2, iclass 36, count 0 2006.257.06:52:37.91#ibcon#flushed, iclass 36, count 0 2006.257.06:52:37.91#ibcon#about to write, iclass 36, count 0 2006.257.06:52:37.91#ibcon#wrote, iclass 36, count 0 2006.257.06:52:37.91#ibcon#about to read 3, iclass 36, count 0 2006.257.06:52:37.93#ibcon#read 3, iclass 36, count 0 2006.257.06:52:37.93#ibcon#about to read 4, iclass 36, count 0 2006.257.06:52:37.93#ibcon#read 4, iclass 36, count 0 2006.257.06:52:37.93#ibcon#about to read 5, iclass 36, count 0 2006.257.06:52:37.93#ibcon#read 5, iclass 36, count 0 2006.257.06:52:37.93#ibcon#about to read 6, iclass 36, count 0 2006.257.06:52:37.93#ibcon#read 6, iclass 36, count 0 2006.257.06:52:37.93#ibcon#end of sib2, iclass 36, count 0 2006.257.06:52:37.93#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:52:37.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:52:37.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:52:37.93#ibcon#*before write, iclass 36, count 0 2006.257.06:52:37.93#ibcon#enter sib2, iclass 36, count 0 2006.257.06:52:37.93#ibcon#flushed, iclass 36, count 0 2006.257.06:52:37.93#ibcon#about to write, iclass 36, count 0 2006.257.06:52:37.93#ibcon#wrote, iclass 36, count 0 2006.257.06:52:37.93#ibcon#about to read 3, iclass 36, count 0 2006.257.06:52:37.97#ibcon#read 3, iclass 36, count 0 2006.257.06:52:37.97#ibcon#about to read 4, iclass 36, count 0 2006.257.06:52:37.97#ibcon#read 4, iclass 36, count 0 2006.257.06:52:37.97#ibcon#about to read 5, iclass 36, count 0 2006.257.06:52:37.97#ibcon#read 5, iclass 36, count 0 2006.257.06:52:37.97#ibcon#about to read 6, iclass 36, count 0 2006.257.06:52:37.97#ibcon#read 6, iclass 36, count 0 2006.257.06:52:37.97#ibcon#end of sib2, iclass 36, count 0 2006.257.06:52:37.97#ibcon#*after write, iclass 36, count 0 2006.257.06:52:37.97#ibcon#*before return 0, iclass 36, count 0 2006.257.06:52:37.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:37.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.06:52:37.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:52:37.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:52:37.97$vck44/vb=7,4 2006.257.06:52:37.97#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.06:52:37.97#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.06:52:37.97#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:37.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:38.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:38.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:38.03#ibcon#enter wrdev, iclass 38, count 2 2006.257.06:52:38.03#ibcon#first serial, iclass 38, count 2 2006.257.06:52:38.03#ibcon#enter sib2, iclass 38, count 2 2006.257.06:52:38.03#ibcon#flushed, iclass 38, count 2 2006.257.06:52:38.03#ibcon#about to write, iclass 38, count 2 2006.257.06:52:38.03#ibcon#wrote, iclass 38, count 2 2006.257.06:52:38.03#ibcon#about to read 3, iclass 38, count 2 2006.257.06:52:38.05#ibcon#read 3, iclass 38, count 2 2006.257.06:52:38.05#ibcon#about to read 4, iclass 38, count 2 2006.257.06:52:38.05#ibcon#read 4, iclass 38, count 2 2006.257.06:52:38.05#ibcon#about to read 5, iclass 38, count 2 2006.257.06:52:38.05#ibcon#read 5, iclass 38, count 2 2006.257.06:52:38.05#ibcon#about to read 6, iclass 38, count 2 2006.257.06:52:38.05#ibcon#read 6, iclass 38, count 2 2006.257.06:52:38.05#ibcon#end of sib2, iclass 38, count 2 2006.257.06:52:38.05#ibcon#*mode == 0, iclass 38, count 2 2006.257.06:52:38.05#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.06:52:38.05#ibcon#[27=AT07-04\r\n] 2006.257.06:52:38.05#ibcon#*before write, iclass 38, count 2 2006.257.06:52:38.05#ibcon#enter sib2, iclass 38, count 2 2006.257.06:52:38.05#ibcon#flushed, iclass 38, count 2 2006.257.06:52:38.05#ibcon#about to write, iclass 38, count 2 2006.257.06:52:38.05#ibcon#wrote, iclass 38, count 2 2006.257.06:52:38.05#ibcon#about to read 3, iclass 38, count 2 2006.257.06:52:38.08#ibcon#read 3, iclass 38, count 2 2006.257.06:52:38.08#ibcon#about to read 4, iclass 38, count 2 2006.257.06:52:38.08#ibcon#read 4, iclass 38, count 2 2006.257.06:52:38.08#ibcon#about to read 5, iclass 38, count 2 2006.257.06:52:38.08#ibcon#read 5, iclass 38, count 2 2006.257.06:52:38.08#ibcon#about to read 6, iclass 38, count 2 2006.257.06:52:38.08#ibcon#read 6, iclass 38, count 2 2006.257.06:52:38.08#ibcon#end of sib2, iclass 38, count 2 2006.257.06:52:38.08#ibcon#*after write, iclass 38, count 2 2006.257.06:52:38.08#ibcon#*before return 0, iclass 38, count 2 2006.257.06:52:38.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:38.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.06:52:38.08#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.06:52:38.08#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:38.08#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:38.20#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:38.20#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:38.20#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:52:38.20#ibcon#first serial, iclass 38, count 0 2006.257.06:52:38.20#ibcon#enter sib2, iclass 38, count 0 2006.257.06:52:38.20#ibcon#flushed, iclass 38, count 0 2006.257.06:52:38.20#ibcon#about to write, iclass 38, count 0 2006.257.06:52:38.20#ibcon#wrote, iclass 38, count 0 2006.257.06:52:38.20#ibcon#about to read 3, iclass 38, count 0 2006.257.06:52:38.22#ibcon#read 3, iclass 38, count 0 2006.257.06:52:38.22#ibcon#about to read 4, iclass 38, count 0 2006.257.06:52:38.22#ibcon#read 4, iclass 38, count 0 2006.257.06:52:38.22#ibcon#about to read 5, iclass 38, count 0 2006.257.06:52:38.22#ibcon#read 5, iclass 38, count 0 2006.257.06:52:38.22#ibcon#about to read 6, iclass 38, count 0 2006.257.06:52:38.22#ibcon#read 6, iclass 38, count 0 2006.257.06:52:38.22#ibcon#end of sib2, iclass 38, count 0 2006.257.06:52:38.22#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:52:38.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:52:38.22#ibcon#[27=USB\r\n] 2006.257.06:52:38.22#ibcon#*before write, iclass 38, count 0 2006.257.06:52:38.22#ibcon#enter sib2, iclass 38, count 0 2006.257.06:52:38.22#ibcon#flushed, iclass 38, count 0 2006.257.06:52:38.22#ibcon#about to write, iclass 38, count 0 2006.257.06:52:38.22#ibcon#wrote, iclass 38, count 0 2006.257.06:52:38.22#ibcon#about to read 3, iclass 38, count 0 2006.257.06:52:38.25#ibcon#read 3, iclass 38, count 0 2006.257.06:52:38.25#ibcon#about to read 4, iclass 38, count 0 2006.257.06:52:38.25#ibcon#read 4, iclass 38, count 0 2006.257.06:52:38.25#ibcon#about to read 5, iclass 38, count 0 2006.257.06:52:38.25#ibcon#read 5, iclass 38, count 0 2006.257.06:52:38.25#ibcon#about to read 6, iclass 38, count 0 2006.257.06:52:38.25#ibcon#read 6, iclass 38, count 0 2006.257.06:52:38.25#ibcon#end of sib2, iclass 38, count 0 2006.257.06:52:38.25#ibcon#*after write, iclass 38, count 0 2006.257.06:52:38.25#ibcon#*before return 0, iclass 38, count 0 2006.257.06:52:38.25#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:38.25#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.06:52:38.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:52:38.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:52:38.25$vck44/vblo=8,744.99 2006.257.06:52:38.25#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.06:52:38.25#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.06:52:38.25#ibcon#ireg 17 cls_cnt 0 2006.257.06:52:38.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:52:38.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:52:38.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:52:38.25#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:52:38.25#ibcon#first serial, iclass 40, count 0 2006.257.06:52:38.25#ibcon#enter sib2, iclass 40, count 0 2006.257.06:52:38.25#ibcon#flushed, iclass 40, count 0 2006.257.06:52:38.25#ibcon#about to write, iclass 40, count 0 2006.257.06:52:38.25#ibcon#wrote, iclass 40, count 0 2006.257.06:52:38.25#ibcon#about to read 3, iclass 40, count 0 2006.257.06:52:38.27#ibcon#read 3, iclass 40, count 0 2006.257.06:52:38.27#ibcon#about to read 4, iclass 40, count 0 2006.257.06:52:38.27#ibcon#read 4, iclass 40, count 0 2006.257.06:52:38.27#ibcon#about to read 5, iclass 40, count 0 2006.257.06:52:38.27#ibcon#read 5, iclass 40, count 0 2006.257.06:52:38.27#ibcon#about to read 6, iclass 40, count 0 2006.257.06:52:38.27#ibcon#read 6, iclass 40, count 0 2006.257.06:52:38.27#ibcon#end of sib2, iclass 40, count 0 2006.257.06:52:38.27#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:52:38.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:52:38.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:52:38.27#ibcon#*before write, iclass 40, count 0 2006.257.06:52:38.27#ibcon#enter sib2, iclass 40, count 0 2006.257.06:52:38.27#ibcon#flushed, iclass 40, count 0 2006.257.06:52:38.27#ibcon#about to write, iclass 40, count 0 2006.257.06:52:38.27#ibcon#wrote, iclass 40, count 0 2006.257.06:52:38.27#ibcon#about to read 3, iclass 40, count 0 2006.257.06:52:38.31#ibcon#read 3, iclass 40, count 0 2006.257.06:52:38.31#ibcon#about to read 4, iclass 40, count 0 2006.257.06:52:38.31#ibcon#read 4, iclass 40, count 0 2006.257.06:52:38.31#ibcon#about to read 5, iclass 40, count 0 2006.257.06:52:38.31#ibcon#read 5, iclass 40, count 0 2006.257.06:52:38.31#ibcon#about to read 6, iclass 40, count 0 2006.257.06:52:38.31#ibcon#read 6, iclass 40, count 0 2006.257.06:52:38.31#ibcon#end of sib2, iclass 40, count 0 2006.257.06:52:38.31#ibcon#*after write, iclass 40, count 0 2006.257.06:52:38.31#ibcon#*before return 0, iclass 40, count 0 2006.257.06:52:38.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:52:38.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:52:38.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:52:38.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:52:38.31$vck44/vb=8,4 2006.257.06:52:38.31#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.06:52:38.31#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.06:52:38.31#ibcon#ireg 11 cls_cnt 2 2006.257.06:52:38.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:52:38.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:52:38.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:52:38.37#ibcon#enter wrdev, iclass 4, count 2 2006.257.06:52:38.37#ibcon#first serial, iclass 4, count 2 2006.257.06:52:38.37#ibcon#enter sib2, iclass 4, count 2 2006.257.06:52:38.37#ibcon#flushed, iclass 4, count 2 2006.257.06:52:38.37#ibcon#about to write, iclass 4, count 2 2006.257.06:52:38.37#ibcon#wrote, iclass 4, count 2 2006.257.06:52:38.37#ibcon#about to read 3, iclass 4, count 2 2006.257.06:52:38.39#ibcon#read 3, iclass 4, count 2 2006.257.06:52:38.39#ibcon#about to read 4, iclass 4, count 2 2006.257.06:52:38.39#ibcon#read 4, iclass 4, count 2 2006.257.06:52:38.39#ibcon#about to read 5, iclass 4, count 2 2006.257.06:52:38.39#ibcon#read 5, iclass 4, count 2 2006.257.06:52:38.39#ibcon#about to read 6, iclass 4, count 2 2006.257.06:52:38.39#ibcon#read 6, iclass 4, count 2 2006.257.06:52:38.39#ibcon#end of sib2, iclass 4, count 2 2006.257.06:52:38.39#ibcon#*mode == 0, iclass 4, count 2 2006.257.06:52:38.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.06:52:38.39#ibcon#[27=AT08-04\r\n] 2006.257.06:52:38.39#ibcon#*before write, iclass 4, count 2 2006.257.06:52:38.39#ibcon#enter sib2, iclass 4, count 2 2006.257.06:52:38.39#ibcon#flushed, iclass 4, count 2 2006.257.06:52:38.39#ibcon#about to write, iclass 4, count 2 2006.257.06:52:38.39#ibcon#wrote, iclass 4, count 2 2006.257.06:52:38.39#ibcon#about to read 3, iclass 4, count 2 2006.257.06:52:38.42#ibcon#read 3, iclass 4, count 2 2006.257.06:52:38.42#ibcon#about to read 4, iclass 4, count 2 2006.257.06:52:38.42#ibcon#read 4, iclass 4, count 2 2006.257.06:52:38.42#ibcon#about to read 5, iclass 4, count 2 2006.257.06:52:38.42#ibcon#read 5, iclass 4, count 2 2006.257.06:52:38.42#ibcon#about to read 6, iclass 4, count 2 2006.257.06:52:38.42#ibcon#read 6, iclass 4, count 2 2006.257.06:52:38.42#ibcon#end of sib2, iclass 4, count 2 2006.257.06:52:38.42#ibcon#*after write, iclass 4, count 2 2006.257.06:52:38.42#ibcon#*before return 0, iclass 4, count 2 2006.257.06:52:38.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:52:38.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.06:52:38.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.06:52:38.42#ibcon#ireg 7 cls_cnt 0 2006.257.06:52:38.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:52:38.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:52:38.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:52:38.54#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:52:38.54#ibcon#first serial, iclass 4, count 0 2006.257.06:52:38.54#ibcon#enter sib2, iclass 4, count 0 2006.257.06:52:38.54#ibcon#flushed, iclass 4, count 0 2006.257.06:52:38.54#ibcon#about to write, iclass 4, count 0 2006.257.06:52:38.54#ibcon#wrote, iclass 4, count 0 2006.257.06:52:38.54#ibcon#about to read 3, iclass 4, count 0 2006.257.06:52:38.56#ibcon#read 3, iclass 4, count 0 2006.257.06:52:38.56#ibcon#about to read 4, iclass 4, count 0 2006.257.06:52:38.56#ibcon#read 4, iclass 4, count 0 2006.257.06:52:38.56#ibcon#about to read 5, iclass 4, count 0 2006.257.06:52:38.56#ibcon#read 5, iclass 4, count 0 2006.257.06:52:38.56#ibcon#about to read 6, iclass 4, count 0 2006.257.06:52:38.56#ibcon#read 6, iclass 4, count 0 2006.257.06:52:38.56#ibcon#end of sib2, iclass 4, count 0 2006.257.06:52:38.56#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:52:38.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:52:38.56#ibcon#[27=USB\r\n] 2006.257.06:52:38.56#ibcon#*before write, iclass 4, count 0 2006.257.06:52:38.56#ibcon#enter sib2, iclass 4, count 0 2006.257.06:52:38.56#ibcon#flushed, iclass 4, count 0 2006.257.06:52:38.56#ibcon#about to write, iclass 4, count 0 2006.257.06:52:38.56#ibcon#wrote, iclass 4, count 0 2006.257.06:52:38.56#ibcon#about to read 3, iclass 4, count 0 2006.257.06:52:38.59#ibcon#read 3, iclass 4, count 0 2006.257.06:52:38.59#ibcon#about to read 4, iclass 4, count 0 2006.257.06:52:38.59#ibcon#read 4, iclass 4, count 0 2006.257.06:52:38.59#ibcon#about to read 5, iclass 4, count 0 2006.257.06:52:38.59#ibcon#read 5, iclass 4, count 0 2006.257.06:52:38.59#ibcon#about to read 6, iclass 4, count 0 2006.257.06:52:38.59#ibcon#read 6, iclass 4, count 0 2006.257.06:52:38.59#ibcon#end of sib2, iclass 4, count 0 2006.257.06:52:38.59#ibcon#*after write, iclass 4, count 0 2006.257.06:52:38.59#ibcon#*before return 0, iclass 4, count 0 2006.257.06:52:38.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:52:38.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.06:52:38.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:52:38.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:52:38.59$vck44/vabw=wide 2006.257.06:52:38.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.06:52:38.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.06:52:38.59#ibcon#ireg 8 cls_cnt 0 2006.257.06:52:38.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:38.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:38.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:38.59#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:52:38.59#ibcon#first serial, iclass 6, count 0 2006.257.06:52:38.59#ibcon#enter sib2, iclass 6, count 0 2006.257.06:52:38.59#ibcon#flushed, iclass 6, count 0 2006.257.06:52:38.59#ibcon#about to write, iclass 6, count 0 2006.257.06:52:38.59#ibcon#wrote, iclass 6, count 0 2006.257.06:52:38.59#ibcon#about to read 3, iclass 6, count 0 2006.257.06:52:38.61#ibcon#read 3, iclass 6, count 0 2006.257.06:52:38.61#ibcon#about to read 4, iclass 6, count 0 2006.257.06:52:38.61#ibcon#read 4, iclass 6, count 0 2006.257.06:52:38.61#ibcon#about to read 5, iclass 6, count 0 2006.257.06:52:38.61#ibcon#read 5, iclass 6, count 0 2006.257.06:52:38.61#ibcon#about to read 6, iclass 6, count 0 2006.257.06:52:38.61#ibcon#read 6, iclass 6, count 0 2006.257.06:52:38.61#ibcon#end of sib2, iclass 6, count 0 2006.257.06:52:38.61#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:52:38.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:52:38.61#ibcon#[25=BW32\r\n] 2006.257.06:52:38.61#ibcon#*before write, iclass 6, count 0 2006.257.06:52:38.61#ibcon#enter sib2, iclass 6, count 0 2006.257.06:52:38.61#ibcon#flushed, iclass 6, count 0 2006.257.06:52:38.61#ibcon#about to write, iclass 6, count 0 2006.257.06:52:38.61#ibcon#wrote, iclass 6, count 0 2006.257.06:52:38.61#ibcon#about to read 3, iclass 6, count 0 2006.257.06:52:38.64#ibcon#read 3, iclass 6, count 0 2006.257.06:52:38.64#ibcon#about to read 4, iclass 6, count 0 2006.257.06:52:38.64#ibcon#read 4, iclass 6, count 0 2006.257.06:52:38.64#ibcon#about to read 5, iclass 6, count 0 2006.257.06:52:38.64#ibcon#read 5, iclass 6, count 0 2006.257.06:52:38.64#ibcon#about to read 6, iclass 6, count 0 2006.257.06:52:38.64#ibcon#read 6, iclass 6, count 0 2006.257.06:52:38.64#ibcon#end of sib2, iclass 6, count 0 2006.257.06:52:38.64#ibcon#*after write, iclass 6, count 0 2006.257.06:52:38.64#ibcon#*before return 0, iclass 6, count 0 2006.257.06:52:38.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:38.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:52:38.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:52:38.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:52:38.64$vck44/vbbw=wide 2006.257.06:52:38.64#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.06:52:38.64#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.06:52:38.64#ibcon#ireg 8 cls_cnt 0 2006.257.06:52:38.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:52:38.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:52:38.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:52:38.71#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:52:38.71#ibcon#first serial, iclass 10, count 0 2006.257.06:52:38.71#ibcon#enter sib2, iclass 10, count 0 2006.257.06:52:38.71#ibcon#flushed, iclass 10, count 0 2006.257.06:52:38.71#ibcon#about to write, iclass 10, count 0 2006.257.06:52:38.71#ibcon#wrote, iclass 10, count 0 2006.257.06:52:38.71#ibcon#about to read 3, iclass 10, count 0 2006.257.06:52:38.73#ibcon#read 3, iclass 10, count 0 2006.257.06:52:38.73#ibcon#about to read 4, iclass 10, count 0 2006.257.06:52:38.73#ibcon#read 4, iclass 10, count 0 2006.257.06:52:38.73#ibcon#about to read 5, iclass 10, count 0 2006.257.06:52:38.73#ibcon#read 5, iclass 10, count 0 2006.257.06:52:38.73#ibcon#about to read 6, iclass 10, count 0 2006.257.06:52:38.73#ibcon#read 6, iclass 10, count 0 2006.257.06:52:38.73#ibcon#end of sib2, iclass 10, count 0 2006.257.06:52:38.73#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:52:38.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:52:38.73#ibcon#[27=BW32\r\n] 2006.257.06:52:38.73#ibcon#*before write, iclass 10, count 0 2006.257.06:52:38.73#ibcon#enter sib2, iclass 10, count 0 2006.257.06:52:38.73#ibcon#flushed, iclass 10, count 0 2006.257.06:52:38.73#ibcon#about to write, iclass 10, count 0 2006.257.06:52:38.73#ibcon#wrote, iclass 10, count 0 2006.257.06:52:38.73#ibcon#about to read 3, iclass 10, count 0 2006.257.06:52:38.76#ibcon#read 3, iclass 10, count 0 2006.257.06:52:38.76#ibcon#about to read 4, iclass 10, count 0 2006.257.06:52:38.76#ibcon#read 4, iclass 10, count 0 2006.257.06:52:38.76#ibcon#about to read 5, iclass 10, count 0 2006.257.06:52:38.76#ibcon#read 5, iclass 10, count 0 2006.257.06:52:38.76#ibcon#about to read 6, iclass 10, count 0 2006.257.06:52:38.76#ibcon#read 6, iclass 10, count 0 2006.257.06:52:38.76#ibcon#end of sib2, iclass 10, count 0 2006.257.06:52:38.76#ibcon#*after write, iclass 10, count 0 2006.257.06:52:38.76#ibcon#*before return 0, iclass 10, count 0 2006.257.06:52:38.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:52:38.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:52:38.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:52:38.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:52:38.76$setupk4/ifdk4 2006.257.06:52:38.76$ifdk4/lo= 2006.257.06:52:38.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:52:38.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:52:38.76$ifdk4/patch= 2006.257.06:52:38.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:52:38.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:52:38.76$setupk4/!*+20s 2006.257.06:52:42.14#trakl#Source acquired 2006.257.06:52:43.14#flagr#flagr/antenna,acquired 2006.257.06:52:45.53#abcon#<5=/01 1.4 4.3 20.72 891012.3\r\n> 2006.257.06:52:45.55#abcon#{5=INTERFACE CLEAR} 2006.257.06:52:45.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:52:53.27$setupk4/"tpicd 2006.257.06:52:53.27$setupk4/echo=off 2006.257.06:52:53.27$setupk4/xlog=off 2006.257.06:52:53.27:!2006.257.06:52:59 2006.257.06:52:59.00:preob 2006.257.06:52:59.14/onsource/TRACKING 2006.257.06:52:59.14:!2006.257.06:53:09 2006.257.06:53:09.00:"tape 2006.257.06:53:09.00:"st=record 2006.257.06:53:09.00:data_valid=on 2006.257.06:53:09.00:midob 2006.257.06:53:10.14/onsource/TRACKING 2006.257.06:53:10.14/wx/20.72,1012.3,89 2006.257.06:53:10.31/cable/+6.4779E-03 2006.257.06:53:11.40/va/01,08,usb,yes,34,36 2006.257.06:53:11.40/va/02,07,usb,yes,36,37 2006.257.06:53:11.40/va/03,08,usb,yes,33,35 2006.257.06:53:11.40/va/04,07,usb,yes,38,39 2006.257.06:53:11.40/va/05,04,usb,yes,34,34 2006.257.06:53:11.40/va/06,04,usb,yes,38,37 2006.257.06:53:11.40/va/07,04,usb,yes,38,39 2006.257.06:53:11.40/va/08,04,usb,yes,32,39 2006.257.06:53:11.63/valo/01,524.99,yes,locked 2006.257.06:53:11.63/valo/02,534.99,yes,locked 2006.257.06:53:11.63/valo/03,564.99,yes,locked 2006.257.06:53:11.63/valo/04,624.99,yes,locked 2006.257.06:53:11.63/valo/05,734.99,yes,locked 2006.257.06:53:11.63/valo/06,814.99,yes,locked 2006.257.06:53:11.63/valo/07,864.99,yes,locked 2006.257.06:53:11.63/valo/08,884.99,yes,locked 2006.257.06:53:12.72/vb/01,04,usb,yes,33,30 2006.257.06:53:12.72/vb/02,05,usb,yes,31,31 2006.257.06:53:12.72/vb/03,04,usb,yes,32,35 2006.257.06:53:12.72/vb/04,05,usb,yes,32,31 2006.257.06:53:12.72/vb/05,04,usb,yes,29,31 2006.257.06:53:12.72/vb/06,04,usb,yes,34,29 2006.257.06:53:12.72/vb/07,04,usb,yes,33,33 2006.257.06:53:12.72/vb/08,04,usb,yes,30,34 2006.257.06:53:12.96/vblo/01,629.99,yes,locked 2006.257.06:53:12.96/vblo/02,634.99,yes,locked 2006.257.06:53:12.96/vblo/03,649.99,yes,locked 2006.257.06:53:12.96/vblo/04,679.99,yes,locked 2006.257.06:53:12.96/vblo/05,709.99,yes,locked 2006.257.06:53:12.96/vblo/06,719.99,yes,locked 2006.257.06:53:12.96/vblo/07,734.99,yes,locked 2006.257.06:53:12.96/vblo/08,744.99,yes,locked 2006.257.06:53:13.11/vabw/8 2006.257.06:53:13.26/vbbw/8 2006.257.06:53:13.35/xfe/off,on,16.7 2006.257.06:53:13.73/ifatt/23,28,28,28 2006.257.06:53:14.07/fmout-gps/S +4.47E-07 2006.257.06:53:14.11:!2006.257.06:56:29 2006.257.06:56:29.01:data_valid=off 2006.257.06:56:29.01:"et 2006.257.06:56:29.01:!+3s 2006.257.06:56:32.04:"tape 2006.257.06:56:32.04:postob 2006.257.06:56:32.23/cable/+6.4778E-03 2006.257.06:56:32.23/wx/20.77,1012.3,89 2006.257.06:56:32.29/fmout-gps/S +4.48E-07 2006.257.06:56:32.29:scan_name=257-0657,jd0609,40 2006.257.06:56:32.29:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.257.06:56:33.14#flagr#flagr/antenna,new-source 2006.257.06:56:33.14:checkk5 2006.257.06:56:33.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:56:33.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:56:34.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:56:34.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:56:35.14/chk_obsdata//k5ts1/T2570653??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.06:56:35.53/chk_obsdata//k5ts2/T2570653??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.06:56:35.95/chk_obsdata//k5ts3/T2570653??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.06:56:36.35/chk_obsdata//k5ts4/T2570653??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.06:56:37.08/k5log//k5ts1_log_newline 2006.257.06:56:37.80/k5log//k5ts2_log_newline 2006.257.06:56:38.53/k5log//k5ts3_log_newline 2006.257.06:56:39.25/k5log//k5ts4_log_newline 2006.257.06:56:39.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:56:39.27:setupk4=1 2006.257.06:56:39.27$setupk4/echo=on 2006.257.06:56:39.27$setupk4/pcalon 2006.257.06:56:39.27$pcalon/"no phase cal control is implemented here 2006.257.06:56:39.27$setupk4/"tpicd=stop 2006.257.06:56:39.27$setupk4/"rec=synch_on 2006.257.06:56:39.27$setupk4/"rec_mode=128 2006.257.06:56:39.27$setupk4/!* 2006.257.06:56:39.27$setupk4/recpk4 2006.257.06:56:39.27$recpk4/recpatch= 2006.257.06:56:39.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:56:39.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:56:39.27$setupk4/vck44 2006.257.06:56:39.27$vck44/valo=1,524.99 2006.257.06:56:39.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:56:39.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:56:39.27#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:39.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:39.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:39.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:39.27#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:56:39.27#ibcon#first serial, iclass 35, count 0 2006.257.06:56:39.27#ibcon#enter sib2, iclass 35, count 0 2006.257.06:56:39.27#ibcon#flushed, iclass 35, count 0 2006.257.06:56:39.27#ibcon#about to write, iclass 35, count 0 2006.257.06:56:39.27#ibcon#wrote, iclass 35, count 0 2006.257.06:56:39.27#ibcon#about to read 3, iclass 35, count 0 2006.257.06:56:39.29#ibcon#read 3, iclass 35, count 0 2006.257.06:56:39.29#ibcon#about to read 4, iclass 35, count 0 2006.257.06:56:39.29#ibcon#read 4, iclass 35, count 0 2006.257.06:56:39.29#ibcon#about to read 5, iclass 35, count 0 2006.257.06:56:39.29#ibcon#read 5, iclass 35, count 0 2006.257.06:56:39.29#ibcon#about to read 6, iclass 35, count 0 2006.257.06:56:39.29#ibcon#read 6, iclass 35, count 0 2006.257.06:56:39.29#ibcon#end of sib2, iclass 35, count 0 2006.257.06:56:39.29#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:56:39.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:56:39.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:56:39.29#ibcon#*before write, iclass 35, count 0 2006.257.06:56:39.29#ibcon#enter sib2, iclass 35, count 0 2006.257.06:56:39.29#ibcon#flushed, iclass 35, count 0 2006.257.06:56:39.29#ibcon#about to write, iclass 35, count 0 2006.257.06:56:39.29#ibcon#wrote, iclass 35, count 0 2006.257.06:56:39.29#ibcon#about to read 3, iclass 35, count 0 2006.257.06:56:39.34#ibcon#read 3, iclass 35, count 0 2006.257.06:56:39.34#ibcon#about to read 4, iclass 35, count 0 2006.257.06:56:39.34#ibcon#read 4, iclass 35, count 0 2006.257.06:56:39.34#ibcon#about to read 5, iclass 35, count 0 2006.257.06:56:39.34#ibcon#read 5, iclass 35, count 0 2006.257.06:56:39.34#ibcon#about to read 6, iclass 35, count 0 2006.257.06:56:39.34#ibcon#read 6, iclass 35, count 0 2006.257.06:56:39.34#ibcon#end of sib2, iclass 35, count 0 2006.257.06:56:39.34#ibcon#*after write, iclass 35, count 0 2006.257.06:56:39.34#ibcon#*before return 0, iclass 35, count 0 2006.257.06:56:39.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:39.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:39.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:56:39.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:56:39.34$vck44/va=1,8 2006.257.06:56:39.34#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.06:56:39.34#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.06:56:39.34#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:39.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:39.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:39.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:39.34#ibcon#enter wrdev, iclass 37, count 2 2006.257.06:56:39.34#ibcon#first serial, iclass 37, count 2 2006.257.06:56:39.34#ibcon#enter sib2, iclass 37, count 2 2006.257.06:56:39.34#ibcon#flushed, iclass 37, count 2 2006.257.06:56:39.34#ibcon#about to write, iclass 37, count 2 2006.257.06:56:39.34#ibcon#wrote, iclass 37, count 2 2006.257.06:56:39.34#ibcon#about to read 3, iclass 37, count 2 2006.257.06:56:39.36#ibcon#read 3, iclass 37, count 2 2006.257.06:56:39.36#ibcon#about to read 4, iclass 37, count 2 2006.257.06:56:39.36#ibcon#read 4, iclass 37, count 2 2006.257.06:56:39.36#ibcon#about to read 5, iclass 37, count 2 2006.257.06:56:39.36#ibcon#read 5, iclass 37, count 2 2006.257.06:56:39.36#ibcon#about to read 6, iclass 37, count 2 2006.257.06:56:39.36#ibcon#read 6, iclass 37, count 2 2006.257.06:56:39.36#ibcon#end of sib2, iclass 37, count 2 2006.257.06:56:39.36#ibcon#*mode == 0, iclass 37, count 2 2006.257.06:56:39.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.06:56:39.36#ibcon#[25=AT01-08\r\n] 2006.257.06:56:39.36#ibcon#*before write, iclass 37, count 2 2006.257.06:56:39.36#ibcon#enter sib2, iclass 37, count 2 2006.257.06:56:39.36#ibcon#flushed, iclass 37, count 2 2006.257.06:56:39.36#ibcon#about to write, iclass 37, count 2 2006.257.06:56:39.36#ibcon#wrote, iclass 37, count 2 2006.257.06:56:39.36#ibcon#about to read 3, iclass 37, count 2 2006.257.06:56:39.39#ibcon#read 3, iclass 37, count 2 2006.257.06:56:39.39#ibcon#about to read 4, iclass 37, count 2 2006.257.06:56:39.39#ibcon#read 4, iclass 37, count 2 2006.257.06:56:39.39#ibcon#about to read 5, iclass 37, count 2 2006.257.06:56:39.39#ibcon#read 5, iclass 37, count 2 2006.257.06:56:39.39#ibcon#about to read 6, iclass 37, count 2 2006.257.06:56:39.39#ibcon#read 6, iclass 37, count 2 2006.257.06:56:39.39#ibcon#end of sib2, iclass 37, count 2 2006.257.06:56:39.39#ibcon#*after write, iclass 37, count 2 2006.257.06:56:39.39#ibcon#*before return 0, iclass 37, count 2 2006.257.06:56:39.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:39.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:39.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.06:56:39.39#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:39.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:39.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:39.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:39.51#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:56:39.51#ibcon#first serial, iclass 37, count 0 2006.257.06:56:39.51#ibcon#enter sib2, iclass 37, count 0 2006.257.06:56:39.51#ibcon#flushed, iclass 37, count 0 2006.257.06:56:39.51#ibcon#about to write, iclass 37, count 0 2006.257.06:56:39.51#ibcon#wrote, iclass 37, count 0 2006.257.06:56:39.51#ibcon#about to read 3, iclass 37, count 0 2006.257.06:56:39.53#ibcon#read 3, iclass 37, count 0 2006.257.06:56:39.53#ibcon#about to read 4, iclass 37, count 0 2006.257.06:56:39.53#ibcon#read 4, iclass 37, count 0 2006.257.06:56:39.53#ibcon#about to read 5, iclass 37, count 0 2006.257.06:56:39.53#ibcon#read 5, iclass 37, count 0 2006.257.06:56:39.53#ibcon#about to read 6, iclass 37, count 0 2006.257.06:56:39.53#ibcon#read 6, iclass 37, count 0 2006.257.06:56:39.53#ibcon#end of sib2, iclass 37, count 0 2006.257.06:56:39.53#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:56:39.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:56:39.53#ibcon#[25=USB\r\n] 2006.257.06:56:39.53#ibcon#*before write, iclass 37, count 0 2006.257.06:56:39.53#ibcon#enter sib2, iclass 37, count 0 2006.257.06:56:39.53#ibcon#flushed, iclass 37, count 0 2006.257.06:56:39.53#ibcon#about to write, iclass 37, count 0 2006.257.06:56:39.53#ibcon#wrote, iclass 37, count 0 2006.257.06:56:39.53#ibcon#about to read 3, iclass 37, count 0 2006.257.06:56:39.56#ibcon#read 3, iclass 37, count 0 2006.257.06:56:39.56#ibcon#about to read 4, iclass 37, count 0 2006.257.06:56:39.56#ibcon#read 4, iclass 37, count 0 2006.257.06:56:39.56#ibcon#about to read 5, iclass 37, count 0 2006.257.06:56:39.56#ibcon#read 5, iclass 37, count 0 2006.257.06:56:39.56#ibcon#about to read 6, iclass 37, count 0 2006.257.06:56:39.56#ibcon#read 6, iclass 37, count 0 2006.257.06:56:39.56#ibcon#end of sib2, iclass 37, count 0 2006.257.06:56:39.56#ibcon#*after write, iclass 37, count 0 2006.257.06:56:39.56#ibcon#*before return 0, iclass 37, count 0 2006.257.06:56:39.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:39.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:39.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:56:39.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:56:39.56$vck44/valo=2,534.99 2006.257.06:56:39.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.06:56:39.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.06:56:39.56#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:39.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:56:39.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:56:39.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:56:39.56#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:56:39.56#ibcon#first serial, iclass 40, count 0 2006.257.06:56:39.56#ibcon#enter sib2, iclass 40, count 0 2006.257.06:56:39.56#ibcon#flushed, iclass 40, count 0 2006.257.06:56:39.56#ibcon#about to write, iclass 40, count 0 2006.257.06:56:39.56#ibcon#wrote, iclass 40, count 0 2006.257.06:56:39.56#ibcon#about to read 3, iclass 40, count 0 2006.257.06:56:39.58#ibcon#read 3, iclass 40, count 0 2006.257.06:56:39.58#ibcon#about to read 4, iclass 40, count 0 2006.257.06:56:39.58#ibcon#read 4, iclass 40, count 0 2006.257.06:56:39.58#ibcon#about to read 5, iclass 40, count 0 2006.257.06:56:39.58#ibcon#read 5, iclass 40, count 0 2006.257.06:56:39.58#ibcon#about to read 6, iclass 40, count 0 2006.257.06:56:39.58#ibcon#read 6, iclass 40, count 0 2006.257.06:56:39.58#ibcon#end of sib2, iclass 40, count 0 2006.257.06:56:39.58#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:56:39.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:56:39.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:56:39.58#ibcon#*before write, iclass 40, count 0 2006.257.06:56:39.58#ibcon#enter sib2, iclass 40, count 0 2006.257.06:56:39.58#ibcon#flushed, iclass 40, count 0 2006.257.06:56:39.58#ibcon#about to write, iclass 40, count 0 2006.257.06:56:39.58#ibcon#wrote, iclass 40, count 0 2006.257.06:56:39.58#ibcon#about to read 3, iclass 40, count 0 2006.257.06:56:39.58#abcon#<5=/16 1.3 3.8 20.77 891012.3\r\n> 2006.257.06:56:39.60#abcon#{5=INTERFACE CLEAR} 2006.257.06:56:39.62#ibcon#read 3, iclass 40, count 0 2006.257.06:56:39.62#ibcon#about to read 4, iclass 40, count 0 2006.257.06:56:39.62#ibcon#read 4, iclass 40, count 0 2006.257.06:56:39.62#ibcon#about to read 5, iclass 40, count 0 2006.257.06:56:39.62#ibcon#read 5, iclass 40, count 0 2006.257.06:56:39.62#ibcon#about to read 6, iclass 40, count 0 2006.257.06:56:39.62#ibcon#read 6, iclass 40, count 0 2006.257.06:56:39.62#ibcon#end of sib2, iclass 40, count 0 2006.257.06:56:39.62#ibcon#*after write, iclass 40, count 0 2006.257.06:56:39.62#ibcon#*before return 0, iclass 40, count 0 2006.257.06:56:39.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:56:39.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.06:56:39.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:56:39.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:56:39.62$vck44/va=2,7 2006.257.06:56:39.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.06:56:39.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.06:56:39.62#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:39.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:56:39.66#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:56:39.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:56:39.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:56:39.68#ibcon#enter wrdev, iclass 6, count 2 2006.257.06:56:39.68#ibcon#first serial, iclass 6, count 2 2006.257.06:56:39.68#ibcon#enter sib2, iclass 6, count 2 2006.257.06:56:39.68#ibcon#flushed, iclass 6, count 2 2006.257.06:56:39.68#ibcon#about to write, iclass 6, count 2 2006.257.06:56:39.68#ibcon#wrote, iclass 6, count 2 2006.257.06:56:39.68#ibcon#about to read 3, iclass 6, count 2 2006.257.06:56:39.70#ibcon#read 3, iclass 6, count 2 2006.257.06:56:39.70#ibcon#about to read 4, iclass 6, count 2 2006.257.06:56:39.70#ibcon#read 4, iclass 6, count 2 2006.257.06:56:39.70#ibcon#about to read 5, iclass 6, count 2 2006.257.06:56:39.70#ibcon#read 5, iclass 6, count 2 2006.257.06:56:39.70#ibcon#about to read 6, iclass 6, count 2 2006.257.06:56:39.70#ibcon#read 6, iclass 6, count 2 2006.257.06:56:39.70#ibcon#end of sib2, iclass 6, count 2 2006.257.06:56:39.70#ibcon#*mode == 0, iclass 6, count 2 2006.257.06:56:39.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.06:56:39.70#ibcon#[25=AT02-07\r\n] 2006.257.06:56:39.70#ibcon#*before write, iclass 6, count 2 2006.257.06:56:39.70#ibcon#enter sib2, iclass 6, count 2 2006.257.06:56:39.70#ibcon#flushed, iclass 6, count 2 2006.257.06:56:39.70#ibcon#about to write, iclass 6, count 2 2006.257.06:56:39.70#ibcon#wrote, iclass 6, count 2 2006.257.06:56:39.70#ibcon#about to read 3, iclass 6, count 2 2006.257.06:56:39.73#ibcon#read 3, iclass 6, count 2 2006.257.06:56:39.73#ibcon#about to read 4, iclass 6, count 2 2006.257.06:56:39.73#ibcon#read 4, iclass 6, count 2 2006.257.06:56:39.73#ibcon#about to read 5, iclass 6, count 2 2006.257.06:56:39.73#ibcon#read 5, iclass 6, count 2 2006.257.06:56:39.73#ibcon#about to read 6, iclass 6, count 2 2006.257.06:56:39.73#ibcon#read 6, iclass 6, count 2 2006.257.06:56:39.73#ibcon#end of sib2, iclass 6, count 2 2006.257.06:56:39.73#ibcon#*after write, iclass 6, count 2 2006.257.06:56:39.73#ibcon#*before return 0, iclass 6, count 2 2006.257.06:56:39.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:56:39.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:56:39.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.06:56:39.73#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:39.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:56:39.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:56:39.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:56:39.85#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:56:39.85#ibcon#first serial, iclass 6, count 0 2006.257.06:56:39.85#ibcon#enter sib2, iclass 6, count 0 2006.257.06:56:39.85#ibcon#flushed, iclass 6, count 0 2006.257.06:56:39.85#ibcon#about to write, iclass 6, count 0 2006.257.06:56:39.85#ibcon#wrote, iclass 6, count 0 2006.257.06:56:39.85#ibcon#about to read 3, iclass 6, count 0 2006.257.06:56:39.87#ibcon#read 3, iclass 6, count 0 2006.257.06:56:39.87#ibcon#about to read 4, iclass 6, count 0 2006.257.06:56:39.87#ibcon#read 4, iclass 6, count 0 2006.257.06:56:39.87#ibcon#about to read 5, iclass 6, count 0 2006.257.06:56:39.87#ibcon#read 5, iclass 6, count 0 2006.257.06:56:39.87#ibcon#about to read 6, iclass 6, count 0 2006.257.06:56:39.87#ibcon#read 6, iclass 6, count 0 2006.257.06:56:39.87#ibcon#end of sib2, iclass 6, count 0 2006.257.06:56:39.87#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:56:39.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:56:39.87#ibcon#[25=USB\r\n] 2006.257.06:56:39.87#ibcon#*before write, iclass 6, count 0 2006.257.06:56:39.87#ibcon#enter sib2, iclass 6, count 0 2006.257.06:56:39.87#ibcon#flushed, iclass 6, count 0 2006.257.06:56:39.87#ibcon#about to write, iclass 6, count 0 2006.257.06:56:39.87#ibcon#wrote, iclass 6, count 0 2006.257.06:56:39.87#ibcon#about to read 3, iclass 6, count 0 2006.257.06:56:39.90#ibcon#read 3, iclass 6, count 0 2006.257.06:56:39.90#ibcon#about to read 4, iclass 6, count 0 2006.257.06:56:39.90#ibcon#read 4, iclass 6, count 0 2006.257.06:56:39.90#ibcon#about to read 5, iclass 6, count 0 2006.257.06:56:39.90#ibcon#read 5, iclass 6, count 0 2006.257.06:56:39.90#ibcon#about to read 6, iclass 6, count 0 2006.257.06:56:39.90#ibcon#read 6, iclass 6, count 0 2006.257.06:56:39.90#ibcon#end of sib2, iclass 6, count 0 2006.257.06:56:39.90#ibcon#*after write, iclass 6, count 0 2006.257.06:56:39.90#ibcon#*before return 0, iclass 6, count 0 2006.257.06:56:39.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:56:39.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:56:39.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:56:39.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:56:39.90$vck44/valo=3,564.99 2006.257.06:56:39.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.06:56:39.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.06:56:39.90#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:39.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:39.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:39.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:39.90#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:56:39.90#ibcon#first serial, iclass 11, count 0 2006.257.06:56:39.90#ibcon#enter sib2, iclass 11, count 0 2006.257.06:56:39.90#ibcon#flushed, iclass 11, count 0 2006.257.06:56:39.90#ibcon#about to write, iclass 11, count 0 2006.257.06:56:39.90#ibcon#wrote, iclass 11, count 0 2006.257.06:56:39.90#ibcon#about to read 3, iclass 11, count 0 2006.257.06:56:39.92#ibcon#read 3, iclass 11, count 0 2006.257.06:56:39.92#ibcon#about to read 4, iclass 11, count 0 2006.257.06:56:39.92#ibcon#read 4, iclass 11, count 0 2006.257.06:56:39.92#ibcon#about to read 5, iclass 11, count 0 2006.257.06:56:39.92#ibcon#read 5, iclass 11, count 0 2006.257.06:56:39.92#ibcon#about to read 6, iclass 11, count 0 2006.257.06:56:39.92#ibcon#read 6, iclass 11, count 0 2006.257.06:56:39.92#ibcon#end of sib2, iclass 11, count 0 2006.257.06:56:39.92#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:56:39.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:56:39.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:56:39.92#ibcon#*before write, iclass 11, count 0 2006.257.06:56:39.92#ibcon#enter sib2, iclass 11, count 0 2006.257.06:56:39.92#ibcon#flushed, iclass 11, count 0 2006.257.06:56:39.92#ibcon#about to write, iclass 11, count 0 2006.257.06:56:39.92#ibcon#wrote, iclass 11, count 0 2006.257.06:56:39.92#ibcon#about to read 3, iclass 11, count 0 2006.257.06:56:39.96#ibcon#read 3, iclass 11, count 0 2006.257.06:56:39.96#ibcon#about to read 4, iclass 11, count 0 2006.257.06:56:39.96#ibcon#read 4, iclass 11, count 0 2006.257.06:56:39.96#ibcon#about to read 5, iclass 11, count 0 2006.257.06:56:39.96#ibcon#read 5, iclass 11, count 0 2006.257.06:56:39.96#ibcon#about to read 6, iclass 11, count 0 2006.257.06:56:39.96#ibcon#read 6, iclass 11, count 0 2006.257.06:56:39.96#ibcon#end of sib2, iclass 11, count 0 2006.257.06:56:39.96#ibcon#*after write, iclass 11, count 0 2006.257.06:56:39.96#ibcon#*before return 0, iclass 11, count 0 2006.257.06:56:39.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:39.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:39.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:56:39.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:56:39.96$vck44/va=3,8 2006.257.06:56:39.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.06:56:39.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.06:56:39.96#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:39.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:40.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:40.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:40.02#ibcon#enter wrdev, iclass 13, count 2 2006.257.06:56:40.02#ibcon#first serial, iclass 13, count 2 2006.257.06:56:40.02#ibcon#enter sib2, iclass 13, count 2 2006.257.06:56:40.02#ibcon#flushed, iclass 13, count 2 2006.257.06:56:40.02#ibcon#about to write, iclass 13, count 2 2006.257.06:56:40.02#ibcon#wrote, iclass 13, count 2 2006.257.06:56:40.02#ibcon#about to read 3, iclass 13, count 2 2006.257.06:56:40.04#ibcon#read 3, iclass 13, count 2 2006.257.06:56:40.04#ibcon#about to read 4, iclass 13, count 2 2006.257.06:56:40.04#ibcon#read 4, iclass 13, count 2 2006.257.06:56:40.04#ibcon#about to read 5, iclass 13, count 2 2006.257.06:56:40.04#ibcon#read 5, iclass 13, count 2 2006.257.06:56:40.04#ibcon#about to read 6, iclass 13, count 2 2006.257.06:56:40.04#ibcon#read 6, iclass 13, count 2 2006.257.06:56:40.04#ibcon#end of sib2, iclass 13, count 2 2006.257.06:56:40.04#ibcon#*mode == 0, iclass 13, count 2 2006.257.06:56:40.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.06:56:40.04#ibcon#[25=AT03-08\r\n] 2006.257.06:56:40.04#ibcon#*before write, iclass 13, count 2 2006.257.06:56:40.04#ibcon#enter sib2, iclass 13, count 2 2006.257.06:56:40.04#ibcon#flushed, iclass 13, count 2 2006.257.06:56:40.04#ibcon#about to write, iclass 13, count 2 2006.257.06:56:40.04#ibcon#wrote, iclass 13, count 2 2006.257.06:56:40.04#ibcon#about to read 3, iclass 13, count 2 2006.257.06:56:40.07#ibcon#read 3, iclass 13, count 2 2006.257.06:56:40.07#ibcon#about to read 4, iclass 13, count 2 2006.257.06:56:40.07#ibcon#read 4, iclass 13, count 2 2006.257.06:56:40.07#ibcon#about to read 5, iclass 13, count 2 2006.257.06:56:40.07#ibcon#read 5, iclass 13, count 2 2006.257.06:56:40.07#ibcon#about to read 6, iclass 13, count 2 2006.257.06:56:40.07#ibcon#read 6, iclass 13, count 2 2006.257.06:56:40.07#ibcon#end of sib2, iclass 13, count 2 2006.257.06:56:40.07#ibcon#*after write, iclass 13, count 2 2006.257.06:56:40.07#ibcon#*before return 0, iclass 13, count 2 2006.257.06:56:40.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:40.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:40.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.06:56:40.07#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:40.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:40.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:40.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:40.19#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:56:40.19#ibcon#first serial, iclass 13, count 0 2006.257.06:56:40.19#ibcon#enter sib2, iclass 13, count 0 2006.257.06:56:40.19#ibcon#flushed, iclass 13, count 0 2006.257.06:56:40.19#ibcon#about to write, iclass 13, count 0 2006.257.06:56:40.19#ibcon#wrote, iclass 13, count 0 2006.257.06:56:40.19#ibcon#about to read 3, iclass 13, count 0 2006.257.06:56:40.21#ibcon#read 3, iclass 13, count 0 2006.257.06:56:40.21#ibcon#about to read 4, iclass 13, count 0 2006.257.06:56:40.21#ibcon#read 4, iclass 13, count 0 2006.257.06:56:40.21#ibcon#about to read 5, iclass 13, count 0 2006.257.06:56:40.21#ibcon#read 5, iclass 13, count 0 2006.257.06:56:40.21#ibcon#about to read 6, iclass 13, count 0 2006.257.06:56:40.21#ibcon#read 6, iclass 13, count 0 2006.257.06:56:40.21#ibcon#end of sib2, iclass 13, count 0 2006.257.06:56:40.21#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:56:40.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:56:40.21#ibcon#[25=USB\r\n] 2006.257.06:56:40.21#ibcon#*before write, iclass 13, count 0 2006.257.06:56:40.21#ibcon#enter sib2, iclass 13, count 0 2006.257.06:56:40.21#ibcon#flushed, iclass 13, count 0 2006.257.06:56:40.21#ibcon#about to write, iclass 13, count 0 2006.257.06:56:40.21#ibcon#wrote, iclass 13, count 0 2006.257.06:56:40.21#ibcon#about to read 3, iclass 13, count 0 2006.257.06:56:40.24#ibcon#read 3, iclass 13, count 0 2006.257.06:56:40.24#ibcon#about to read 4, iclass 13, count 0 2006.257.06:56:40.24#ibcon#read 4, iclass 13, count 0 2006.257.06:56:40.24#ibcon#about to read 5, iclass 13, count 0 2006.257.06:56:40.24#ibcon#read 5, iclass 13, count 0 2006.257.06:56:40.24#ibcon#about to read 6, iclass 13, count 0 2006.257.06:56:40.24#ibcon#read 6, iclass 13, count 0 2006.257.06:56:40.24#ibcon#end of sib2, iclass 13, count 0 2006.257.06:56:40.24#ibcon#*after write, iclass 13, count 0 2006.257.06:56:40.24#ibcon#*before return 0, iclass 13, count 0 2006.257.06:56:40.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:40.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:40.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:56:40.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:56:40.24$vck44/valo=4,624.99 2006.257.06:56:40.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.06:56:40.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.06:56:40.24#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:40.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:40.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:40.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:40.24#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:56:40.24#ibcon#first serial, iclass 15, count 0 2006.257.06:56:40.24#ibcon#enter sib2, iclass 15, count 0 2006.257.06:56:40.24#ibcon#flushed, iclass 15, count 0 2006.257.06:56:40.24#ibcon#about to write, iclass 15, count 0 2006.257.06:56:40.24#ibcon#wrote, iclass 15, count 0 2006.257.06:56:40.24#ibcon#about to read 3, iclass 15, count 0 2006.257.06:56:40.26#ibcon#read 3, iclass 15, count 0 2006.257.06:56:40.26#ibcon#about to read 4, iclass 15, count 0 2006.257.06:56:40.26#ibcon#read 4, iclass 15, count 0 2006.257.06:56:40.26#ibcon#about to read 5, iclass 15, count 0 2006.257.06:56:40.26#ibcon#read 5, iclass 15, count 0 2006.257.06:56:40.26#ibcon#about to read 6, iclass 15, count 0 2006.257.06:56:40.26#ibcon#read 6, iclass 15, count 0 2006.257.06:56:40.26#ibcon#end of sib2, iclass 15, count 0 2006.257.06:56:40.26#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:56:40.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:56:40.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:56:40.26#ibcon#*before write, iclass 15, count 0 2006.257.06:56:40.26#ibcon#enter sib2, iclass 15, count 0 2006.257.06:56:40.26#ibcon#flushed, iclass 15, count 0 2006.257.06:56:40.26#ibcon#about to write, iclass 15, count 0 2006.257.06:56:40.26#ibcon#wrote, iclass 15, count 0 2006.257.06:56:40.26#ibcon#about to read 3, iclass 15, count 0 2006.257.06:56:40.30#ibcon#read 3, iclass 15, count 0 2006.257.06:56:40.30#ibcon#about to read 4, iclass 15, count 0 2006.257.06:56:40.30#ibcon#read 4, iclass 15, count 0 2006.257.06:56:40.30#ibcon#about to read 5, iclass 15, count 0 2006.257.06:56:40.30#ibcon#read 5, iclass 15, count 0 2006.257.06:56:40.30#ibcon#about to read 6, iclass 15, count 0 2006.257.06:56:40.30#ibcon#read 6, iclass 15, count 0 2006.257.06:56:40.30#ibcon#end of sib2, iclass 15, count 0 2006.257.06:56:40.30#ibcon#*after write, iclass 15, count 0 2006.257.06:56:40.30#ibcon#*before return 0, iclass 15, count 0 2006.257.06:56:40.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:40.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:40.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:56:40.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:56:40.30$vck44/va=4,7 2006.257.06:56:40.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.06:56:40.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.06:56:40.30#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:40.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:40.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:40.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:40.36#ibcon#enter wrdev, iclass 17, count 2 2006.257.06:56:40.36#ibcon#first serial, iclass 17, count 2 2006.257.06:56:40.36#ibcon#enter sib2, iclass 17, count 2 2006.257.06:56:40.36#ibcon#flushed, iclass 17, count 2 2006.257.06:56:40.36#ibcon#about to write, iclass 17, count 2 2006.257.06:56:40.36#ibcon#wrote, iclass 17, count 2 2006.257.06:56:40.36#ibcon#about to read 3, iclass 17, count 2 2006.257.06:56:40.38#ibcon#read 3, iclass 17, count 2 2006.257.06:56:40.38#ibcon#about to read 4, iclass 17, count 2 2006.257.06:56:40.38#ibcon#read 4, iclass 17, count 2 2006.257.06:56:40.38#ibcon#about to read 5, iclass 17, count 2 2006.257.06:56:40.38#ibcon#read 5, iclass 17, count 2 2006.257.06:56:40.38#ibcon#about to read 6, iclass 17, count 2 2006.257.06:56:40.38#ibcon#read 6, iclass 17, count 2 2006.257.06:56:40.38#ibcon#end of sib2, iclass 17, count 2 2006.257.06:56:40.38#ibcon#*mode == 0, iclass 17, count 2 2006.257.06:56:40.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.06:56:40.38#ibcon#[25=AT04-07\r\n] 2006.257.06:56:40.38#ibcon#*before write, iclass 17, count 2 2006.257.06:56:40.38#ibcon#enter sib2, iclass 17, count 2 2006.257.06:56:40.38#ibcon#flushed, iclass 17, count 2 2006.257.06:56:40.38#ibcon#about to write, iclass 17, count 2 2006.257.06:56:40.38#ibcon#wrote, iclass 17, count 2 2006.257.06:56:40.38#ibcon#about to read 3, iclass 17, count 2 2006.257.06:56:40.41#ibcon#read 3, iclass 17, count 2 2006.257.06:56:40.41#ibcon#about to read 4, iclass 17, count 2 2006.257.06:56:40.41#ibcon#read 4, iclass 17, count 2 2006.257.06:56:40.41#ibcon#about to read 5, iclass 17, count 2 2006.257.06:56:40.41#ibcon#read 5, iclass 17, count 2 2006.257.06:56:40.41#ibcon#about to read 6, iclass 17, count 2 2006.257.06:56:40.41#ibcon#read 6, iclass 17, count 2 2006.257.06:56:40.41#ibcon#end of sib2, iclass 17, count 2 2006.257.06:56:40.41#ibcon#*after write, iclass 17, count 2 2006.257.06:56:40.41#ibcon#*before return 0, iclass 17, count 2 2006.257.06:56:40.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:40.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:40.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.06:56:40.41#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:40.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:40.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:40.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:40.53#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:56:40.53#ibcon#first serial, iclass 17, count 0 2006.257.06:56:40.53#ibcon#enter sib2, iclass 17, count 0 2006.257.06:56:40.53#ibcon#flushed, iclass 17, count 0 2006.257.06:56:40.53#ibcon#about to write, iclass 17, count 0 2006.257.06:56:40.53#ibcon#wrote, iclass 17, count 0 2006.257.06:56:40.53#ibcon#about to read 3, iclass 17, count 0 2006.257.06:56:40.55#ibcon#read 3, iclass 17, count 0 2006.257.06:56:40.55#ibcon#about to read 4, iclass 17, count 0 2006.257.06:56:40.55#ibcon#read 4, iclass 17, count 0 2006.257.06:56:40.55#ibcon#about to read 5, iclass 17, count 0 2006.257.06:56:40.55#ibcon#read 5, iclass 17, count 0 2006.257.06:56:40.55#ibcon#about to read 6, iclass 17, count 0 2006.257.06:56:40.55#ibcon#read 6, iclass 17, count 0 2006.257.06:56:40.55#ibcon#end of sib2, iclass 17, count 0 2006.257.06:56:40.55#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:56:40.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:56:40.55#ibcon#[25=USB\r\n] 2006.257.06:56:40.55#ibcon#*before write, iclass 17, count 0 2006.257.06:56:40.55#ibcon#enter sib2, iclass 17, count 0 2006.257.06:56:40.55#ibcon#flushed, iclass 17, count 0 2006.257.06:56:40.55#ibcon#about to write, iclass 17, count 0 2006.257.06:56:40.55#ibcon#wrote, iclass 17, count 0 2006.257.06:56:40.55#ibcon#about to read 3, iclass 17, count 0 2006.257.06:56:40.58#ibcon#read 3, iclass 17, count 0 2006.257.06:56:40.58#ibcon#about to read 4, iclass 17, count 0 2006.257.06:56:40.58#ibcon#read 4, iclass 17, count 0 2006.257.06:56:40.58#ibcon#about to read 5, iclass 17, count 0 2006.257.06:56:40.58#ibcon#read 5, iclass 17, count 0 2006.257.06:56:40.58#ibcon#about to read 6, iclass 17, count 0 2006.257.06:56:40.58#ibcon#read 6, iclass 17, count 0 2006.257.06:56:40.58#ibcon#end of sib2, iclass 17, count 0 2006.257.06:56:40.58#ibcon#*after write, iclass 17, count 0 2006.257.06:56:40.58#ibcon#*before return 0, iclass 17, count 0 2006.257.06:56:40.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:40.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:40.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:56:40.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:56:40.58$vck44/valo=5,734.99 2006.257.06:56:40.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.06:56:40.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.06:56:40.58#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:40.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:40.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:40.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:40.58#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:56:40.58#ibcon#first serial, iclass 19, count 0 2006.257.06:56:40.58#ibcon#enter sib2, iclass 19, count 0 2006.257.06:56:40.58#ibcon#flushed, iclass 19, count 0 2006.257.06:56:40.58#ibcon#about to write, iclass 19, count 0 2006.257.06:56:40.58#ibcon#wrote, iclass 19, count 0 2006.257.06:56:40.58#ibcon#about to read 3, iclass 19, count 0 2006.257.06:56:40.60#ibcon#read 3, iclass 19, count 0 2006.257.06:56:40.60#ibcon#about to read 4, iclass 19, count 0 2006.257.06:56:40.60#ibcon#read 4, iclass 19, count 0 2006.257.06:56:40.60#ibcon#about to read 5, iclass 19, count 0 2006.257.06:56:40.60#ibcon#read 5, iclass 19, count 0 2006.257.06:56:40.60#ibcon#about to read 6, iclass 19, count 0 2006.257.06:56:40.60#ibcon#read 6, iclass 19, count 0 2006.257.06:56:40.60#ibcon#end of sib2, iclass 19, count 0 2006.257.06:56:40.60#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:56:40.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:56:40.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:56:40.60#ibcon#*before write, iclass 19, count 0 2006.257.06:56:40.60#ibcon#enter sib2, iclass 19, count 0 2006.257.06:56:40.60#ibcon#flushed, iclass 19, count 0 2006.257.06:56:40.60#ibcon#about to write, iclass 19, count 0 2006.257.06:56:40.60#ibcon#wrote, iclass 19, count 0 2006.257.06:56:40.60#ibcon#about to read 3, iclass 19, count 0 2006.257.06:56:40.64#ibcon#read 3, iclass 19, count 0 2006.257.06:56:40.64#ibcon#about to read 4, iclass 19, count 0 2006.257.06:56:40.64#ibcon#read 4, iclass 19, count 0 2006.257.06:56:40.64#ibcon#about to read 5, iclass 19, count 0 2006.257.06:56:40.64#ibcon#read 5, iclass 19, count 0 2006.257.06:56:40.64#ibcon#about to read 6, iclass 19, count 0 2006.257.06:56:40.64#ibcon#read 6, iclass 19, count 0 2006.257.06:56:40.64#ibcon#end of sib2, iclass 19, count 0 2006.257.06:56:40.64#ibcon#*after write, iclass 19, count 0 2006.257.06:56:40.64#ibcon#*before return 0, iclass 19, count 0 2006.257.06:56:40.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:40.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:40.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:56:40.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:56:40.64$vck44/va=5,4 2006.257.06:56:40.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.06:56:40.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.06:56:40.64#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:40.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:40.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:40.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:40.70#ibcon#enter wrdev, iclass 21, count 2 2006.257.06:56:40.70#ibcon#first serial, iclass 21, count 2 2006.257.06:56:40.70#ibcon#enter sib2, iclass 21, count 2 2006.257.06:56:40.70#ibcon#flushed, iclass 21, count 2 2006.257.06:56:40.70#ibcon#about to write, iclass 21, count 2 2006.257.06:56:40.70#ibcon#wrote, iclass 21, count 2 2006.257.06:56:40.70#ibcon#about to read 3, iclass 21, count 2 2006.257.06:56:40.72#ibcon#read 3, iclass 21, count 2 2006.257.06:56:40.72#ibcon#about to read 4, iclass 21, count 2 2006.257.06:56:40.72#ibcon#read 4, iclass 21, count 2 2006.257.06:56:40.72#ibcon#about to read 5, iclass 21, count 2 2006.257.06:56:40.72#ibcon#read 5, iclass 21, count 2 2006.257.06:56:40.72#ibcon#about to read 6, iclass 21, count 2 2006.257.06:56:40.72#ibcon#read 6, iclass 21, count 2 2006.257.06:56:40.72#ibcon#end of sib2, iclass 21, count 2 2006.257.06:56:40.72#ibcon#*mode == 0, iclass 21, count 2 2006.257.06:56:40.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.06:56:40.72#ibcon#[25=AT05-04\r\n] 2006.257.06:56:40.72#ibcon#*before write, iclass 21, count 2 2006.257.06:56:40.72#ibcon#enter sib2, iclass 21, count 2 2006.257.06:56:40.72#ibcon#flushed, iclass 21, count 2 2006.257.06:56:40.72#ibcon#about to write, iclass 21, count 2 2006.257.06:56:40.72#ibcon#wrote, iclass 21, count 2 2006.257.06:56:40.72#ibcon#about to read 3, iclass 21, count 2 2006.257.06:56:40.75#ibcon#read 3, iclass 21, count 2 2006.257.06:56:40.75#ibcon#about to read 4, iclass 21, count 2 2006.257.06:56:40.75#ibcon#read 4, iclass 21, count 2 2006.257.06:56:40.75#ibcon#about to read 5, iclass 21, count 2 2006.257.06:56:40.75#ibcon#read 5, iclass 21, count 2 2006.257.06:56:40.75#ibcon#about to read 6, iclass 21, count 2 2006.257.06:56:40.75#ibcon#read 6, iclass 21, count 2 2006.257.06:56:40.75#ibcon#end of sib2, iclass 21, count 2 2006.257.06:56:40.75#ibcon#*after write, iclass 21, count 2 2006.257.06:56:40.75#ibcon#*before return 0, iclass 21, count 2 2006.257.06:56:40.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:40.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:40.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.06:56:40.75#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:40.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:40.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:40.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:40.87#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:56:40.87#ibcon#first serial, iclass 21, count 0 2006.257.06:56:40.87#ibcon#enter sib2, iclass 21, count 0 2006.257.06:56:40.87#ibcon#flushed, iclass 21, count 0 2006.257.06:56:40.87#ibcon#about to write, iclass 21, count 0 2006.257.06:56:40.87#ibcon#wrote, iclass 21, count 0 2006.257.06:56:40.87#ibcon#about to read 3, iclass 21, count 0 2006.257.06:56:40.89#ibcon#read 3, iclass 21, count 0 2006.257.06:56:40.89#ibcon#about to read 4, iclass 21, count 0 2006.257.06:56:40.89#ibcon#read 4, iclass 21, count 0 2006.257.06:56:40.89#ibcon#about to read 5, iclass 21, count 0 2006.257.06:56:40.89#ibcon#read 5, iclass 21, count 0 2006.257.06:56:40.89#ibcon#about to read 6, iclass 21, count 0 2006.257.06:56:40.89#ibcon#read 6, iclass 21, count 0 2006.257.06:56:40.89#ibcon#end of sib2, iclass 21, count 0 2006.257.06:56:40.89#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:56:40.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:56:40.89#ibcon#[25=USB\r\n] 2006.257.06:56:40.89#ibcon#*before write, iclass 21, count 0 2006.257.06:56:40.89#ibcon#enter sib2, iclass 21, count 0 2006.257.06:56:40.89#ibcon#flushed, iclass 21, count 0 2006.257.06:56:40.89#ibcon#about to write, iclass 21, count 0 2006.257.06:56:40.89#ibcon#wrote, iclass 21, count 0 2006.257.06:56:40.89#ibcon#about to read 3, iclass 21, count 0 2006.257.06:56:40.92#ibcon#read 3, iclass 21, count 0 2006.257.06:56:40.92#ibcon#about to read 4, iclass 21, count 0 2006.257.06:56:40.92#ibcon#read 4, iclass 21, count 0 2006.257.06:56:40.92#ibcon#about to read 5, iclass 21, count 0 2006.257.06:56:40.92#ibcon#read 5, iclass 21, count 0 2006.257.06:56:40.92#ibcon#about to read 6, iclass 21, count 0 2006.257.06:56:40.92#ibcon#read 6, iclass 21, count 0 2006.257.06:56:40.92#ibcon#end of sib2, iclass 21, count 0 2006.257.06:56:40.92#ibcon#*after write, iclass 21, count 0 2006.257.06:56:40.92#ibcon#*before return 0, iclass 21, count 0 2006.257.06:56:40.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:40.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:40.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:56:40.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:56:40.92$vck44/valo=6,814.99 2006.257.06:56:40.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.06:56:40.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.06:56:40.92#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:40.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:40.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:40.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:40.92#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:56:40.92#ibcon#first serial, iclass 23, count 0 2006.257.06:56:40.92#ibcon#enter sib2, iclass 23, count 0 2006.257.06:56:40.92#ibcon#flushed, iclass 23, count 0 2006.257.06:56:40.92#ibcon#about to write, iclass 23, count 0 2006.257.06:56:40.92#ibcon#wrote, iclass 23, count 0 2006.257.06:56:40.92#ibcon#about to read 3, iclass 23, count 0 2006.257.06:56:40.94#ibcon#read 3, iclass 23, count 0 2006.257.06:56:40.94#ibcon#about to read 4, iclass 23, count 0 2006.257.06:56:40.94#ibcon#read 4, iclass 23, count 0 2006.257.06:56:40.94#ibcon#about to read 5, iclass 23, count 0 2006.257.06:56:40.94#ibcon#read 5, iclass 23, count 0 2006.257.06:56:40.94#ibcon#about to read 6, iclass 23, count 0 2006.257.06:56:40.94#ibcon#read 6, iclass 23, count 0 2006.257.06:56:40.94#ibcon#end of sib2, iclass 23, count 0 2006.257.06:56:40.94#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:56:40.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:56:40.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:56:40.94#ibcon#*before write, iclass 23, count 0 2006.257.06:56:40.94#ibcon#enter sib2, iclass 23, count 0 2006.257.06:56:40.94#ibcon#flushed, iclass 23, count 0 2006.257.06:56:40.94#ibcon#about to write, iclass 23, count 0 2006.257.06:56:40.94#ibcon#wrote, iclass 23, count 0 2006.257.06:56:40.94#ibcon#about to read 3, iclass 23, count 0 2006.257.06:56:40.98#ibcon#read 3, iclass 23, count 0 2006.257.06:56:40.98#ibcon#about to read 4, iclass 23, count 0 2006.257.06:56:40.98#ibcon#read 4, iclass 23, count 0 2006.257.06:56:40.98#ibcon#about to read 5, iclass 23, count 0 2006.257.06:56:40.98#ibcon#read 5, iclass 23, count 0 2006.257.06:56:40.98#ibcon#about to read 6, iclass 23, count 0 2006.257.06:56:40.98#ibcon#read 6, iclass 23, count 0 2006.257.06:56:40.98#ibcon#end of sib2, iclass 23, count 0 2006.257.06:56:40.98#ibcon#*after write, iclass 23, count 0 2006.257.06:56:40.98#ibcon#*before return 0, iclass 23, count 0 2006.257.06:56:40.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:40.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:40.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:56:40.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:56:40.98$vck44/va=6,4 2006.257.06:56:40.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.06:56:40.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.06:56:40.98#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:40.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:41.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:41.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:41.04#ibcon#enter wrdev, iclass 25, count 2 2006.257.06:56:41.04#ibcon#first serial, iclass 25, count 2 2006.257.06:56:41.04#ibcon#enter sib2, iclass 25, count 2 2006.257.06:56:41.04#ibcon#flushed, iclass 25, count 2 2006.257.06:56:41.04#ibcon#about to write, iclass 25, count 2 2006.257.06:56:41.04#ibcon#wrote, iclass 25, count 2 2006.257.06:56:41.04#ibcon#about to read 3, iclass 25, count 2 2006.257.06:56:41.06#ibcon#read 3, iclass 25, count 2 2006.257.06:56:41.06#ibcon#about to read 4, iclass 25, count 2 2006.257.06:56:41.06#ibcon#read 4, iclass 25, count 2 2006.257.06:56:41.06#ibcon#about to read 5, iclass 25, count 2 2006.257.06:56:41.06#ibcon#read 5, iclass 25, count 2 2006.257.06:56:41.06#ibcon#about to read 6, iclass 25, count 2 2006.257.06:56:41.06#ibcon#read 6, iclass 25, count 2 2006.257.06:56:41.06#ibcon#end of sib2, iclass 25, count 2 2006.257.06:56:41.06#ibcon#*mode == 0, iclass 25, count 2 2006.257.06:56:41.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.06:56:41.06#ibcon#[25=AT06-04\r\n] 2006.257.06:56:41.06#ibcon#*before write, iclass 25, count 2 2006.257.06:56:41.06#ibcon#enter sib2, iclass 25, count 2 2006.257.06:56:41.06#ibcon#flushed, iclass 25, count 2 2006.257.06:56:41.06#ibcon#about to write, iclass 25, count 2 2006.257.06:56:41.06#ibcon#wrote, iclass 25, count 2 2006.257.06:56:41.06#ibcon#about to read 3, iclass 25, count 2 2006.257.06:56:41.09#ibcon#read 3, iclass 25, count 2 2006.257.06:56:41.09#ibcon#about to read 4, iclass 25, count 2 2006.257.06:56:41.09#ibcon#read 4, iclass 25, count 2 2006.257.06:56:41.09#ibcon#about to read 5, iclass 25, count 2 2006.257.06:56:41.09#ibcon#read 5, iclass 25, count 2 2006.257.06:56:41.09#ibcon#about to read 6, iclass 25, count 2 2006.257.06:56:41.09#ibcon#read 6, iclass 25, count 2 2006.257.06:56:41.09#ibcon#end of sib2, iclass 25, count 2 2006.257.06:56:41.09#ibcon#*after write, iclass 25, count 2 2006.257.06:56:41.09#ibcon#*before return 0, iclass 25, count 2 2006.257.06:56:41.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:41.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:41.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.06:56:41.09#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:41.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:41.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:41.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:41.21#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:56:41.21#ibcon#first serial, iclass 25, count 0 2006.257.06:56:41.21#ibcon#enter sib2, iclass 25, count 0 2006.257.06:56:41.21#ibcon#flushed, iclass 25, count 0 2006.257.06:56:41.21#ibcon#about to write, iclass 25, count 0 2006.257.06:56:41.21#ibcon#wrote, iclass 25, count 0 2006.257.06:56:41.21#ibcon#about to read 3, iclass 25, count 0 2006.257.06:56:41.23#ibcon#read 3, iclass 25, count 0 2006.257.06:56:41.23#ibcon#about to read 4, iclass 25, count 0 2006.257.06:56:41.23#ibcon#read 4, iclass 25, count 0 2006.257.06:56:41.23#ibcon#about to read 5, iclass 25, count 0 2006.257.06:56:41.23#ibcon#read 5, iclass 25, count 0 2006.257.06:56:41.23#ibcon#about to read 6, iclass 25, count 0 2006.257.06:56:41.23#ibcon#read 6, iclass 25, count 0 2006.257.06:56:41.23#ibcon#end of sib2, iclass 25, count 0 2006.257.06:56:41.23#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:56:41.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:56:41.23#ibcon#[25=USB\r\n] 2006.257.06:56:41.23#ibcon#*before write, iclass 25, count 0 2006.257.06:56:41.23#ibcon#enter sib2, iclass 25, count 0 2006.257.06:56:41.23#ibcon#flushed, iclass 25, count 0 2006.257.06:56:41.23#ibcon#about to write, iclass 25, count 0 2006.257.06:56:41.23#ibcon#wrote, iclass 25, count 0 2006.257.06:56:41.23#ibcon#about to read 3, iclass 25, count 0 2006.257.06:56:41.26#ibcon#read 3, iclass 25, count 0 2006.257.06:56:41.26#ibcon#about to read 4, iclass 25, count 0 2006.257.06:56:41.26#ibcon#read 4, iclass 25, count 0 2006.257.06:56:41.26#ibcon#about to read 5, iclass 25, count 0 2006.257.06:56:41.26#ibcon#read 5, iclass 25, count 0 2006.257.06:56:41.26#ibcon#about to read 6, iclass 25, count 0 2006.257.06:56:41.26#ibcon#read 6, iclass 25, count 0 2006.257.06:56:41.26#ibcon#end of sib2, iclass 25, count 0 2006.257.06:56:41.26#ibcon#*after write, iclass 25, count 0 2006.257.06:56:41.26#ibcon#*before return 0, iclass 25, count 0 2006.257.06:56:41.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:41.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:41.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:56:41.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:56:41.26$vck44/valo=7,864.99 2006.257.06:56:41.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.06:56:41.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.06:56:41.26#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:41.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:41.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:41.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:41.26#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:56:41.26#ibcon#first serial, iclass 27, count 0 2006.257.06:56:41.26#ibcon#enter sib2, iclass 27, count 0 2006.257.06:56:41.26#ibcon#flushed, iclass 27, count 0 2006.257.06:56:41.26#ibcon#about to write, iclass 27, count 0 2006.257.06:56:41.26#ibcon#wrote, iclass 27, count 0 2006.257.06:56:41.26#ibcon#about to read 3, iclass 27, count 0 2006.257.06:56:41.28#ibcon#read 3, iclass 27, count 0 2006.257.06:56:41.28#ibcon#about to read 4, iclass 27, count 0 2006.257.06:56:41.28#ibcon#read 4, iclass 27, count 0 2006.257.06:56:41.28#ibcon#about to read 5, iclass 27, count 0 2006.257.06:56:41.28#ibcon#read 5, iclass 27, count 0 2006.257.06:56:41.28#ibcon#about to read 6, iclass 27, count 0 2006.257.06:56:41.28#ibcon#read 6, iclass 27, count 0 2006.257.06:56:41.28#ibcon#end of sib2, iclass 27, count 0 2006.257.06:56:41.28#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:56:41.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:56:41.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:56:41.28#ibcon#*before write, iclass 27, count 0 2006.257.06:56:41.28#ibcon#enter sib2, iclass 27, count 0 2006.257.06:56:41.28#ibcon#flushed, iclass 27, count 0 2006.257.06:56:41.28#ibcon#about to write, iclass 27, count 0 2006.257.06:56:41.28#ibcon#wrote, iclass 27, count 0 2006.257.06:56:41.28#ibcon#about to read 3, iclass 27, count 0 2006.257.06:56:41.32#ibcon#read 3, iclass 27, count 0 2006.257.06:56:41.32#ibcon#about to read 4, iclass 27, count 0 2006.257.06:56:41.32#ibcon#read 4, iclass 27, count 0 2006.257.06:56:41.32#ibcon#about to read 5, iclass 27, count 0 2006.257.06:56:41.32#ibcon#read 5, iclass 27, count 0 2006.257.06:56:41.32#ibcon#about to read 6, iclass 27, count 0 2006.257.06:56:41.32#ibcon#read 6, iclass 27, count 0 2006.257.06:56:41.32#ibcon#end of sib2, iclass 27, count 0 2006.257.06:56:41.32#ibcon#*after write, iclass 27, count 0 2006.257.06:56:41.32#ibcon#*before return 0, iclass 27, count 0 2006.257.06:56:41.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:41.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:41.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:56:41.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:56:41.32$vck44/va=7,4 2006.257.06:56:41.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.06:56:41.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.06:56:41.32#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:41.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:41.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:41.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:41.38#ibcon#enter wrdev, iclass 29, count 2 2006.257.06:56:41.38#ibcon#first serial, iclass 29, count 2 2006.257.06:56:41.38#ibcon#enter sib2, iclass 29, count 2 2006.257.06:56:41.38#ibcon#flushed, iclass 29, count 2 2006.257.06:56:41.38#ibcon#about to write, iclass 29, count 2 2006.257.06:56:41.38#ibcon#wrote, iclass 29, count 2 2006.257.06:56:41.38#ibcon#about to read 3, iclass 29, count 2 2006.257.06:56:41.40#ibcon#read 3, iclass 29, count 2 2006.257.06:56:41.40#ibcon#about to read 4, iclass 29, count 2 2006.257.06:56:41.40#ibcon#read 4, iclass 29, count 2 2006.257.06:56:41.40#ibcon#about to read 5, iclass 29, count 2 2006.257.06:56:41.40#ibcon#read 5, iclass 29, count 2 2006.257.06:56:41.40#ibcon#about to read 6, iclass 29, count 2 2006.257.06:56:41.40#ibcon#read 6, iclass 29, count 2 2006.257.06:56:41.40#ibcon#end of sib2, iclass 29, count 2 2006.257.06:56:41.40#ibcon#*mode == 0, iclass 29, count 2 2006.257.06:56:41.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.06:56:41.40#ibcon#[25=AT07-04\r\n] 2006.257.06:56:41.40#ibcon#*before write, iclass 29, count 2 2006.257.06:56:41.40#ibcon#enter sib2, iclass 29, count 2 2006.257.06:56:41.40#ibcon#flushed, iclass 29, count 2 2006.257.06:56:41.40#ibcon#about to write, iclass 29, count 2 2006.257.06:56:41.40#ibcon#wrote, iclass 29, count 2 2006.257.06:56:41.40#ibcon#about to read 3, iclass 29, count 2 2006.257.06:56:41.43#ibcon#read 3, iclass 29, count 2 2006.257.06:56:41.43#ibcon#about to read 4, iclass 29, count 2 2006.257.06:56:41.43#ibcon#read 4, iclass 29, count 2 2006.257.06:56:41.43#ibcon#about to read 5, iclass 29, count 2 2006.257.06:56:41.43#ibcon#read 5, iclass 29, count 2 2006.257.06:56:41.43#ibcon#about to read 6, iclass 29, count 2 2006.257.06:56:41.43#ibcon#read 6, iclass 29, count 2 2006.257.06:56:41.43#ibcon#end of sib2, iclass 29, count 2 2006.257.06:56:41.43#ibcon#*after write, iclass 29, count 2 2006.257.06:56:41.43#ibcon#*before return 0, iclass 29, count 2 2006.257.06:56:41.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:41.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:41.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.06:56:41.43#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:41.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:41.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:41.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:41.55#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:56:41.55#ibcon#first serial, iclass 29, count 0 2006.257.06:56:41.55#ibcon#enter sib2, iclass 29, count 0 2006.257.06:56:41.55#ibcon#flushed, iclass 29, count 0 2006.257.06:56:41.55#ibcon#about to write, iclass 29, count 0 2006.257.06:56:41.55#ibcon#wrote, iclass 29, count 0 2006.257.06:56:41.55#ibcon#about to read 3, iclass 29, count 0 2006.257.06:56:41.57#ibcon#read 3, iclass 29, count 0 2006.257.06:56:41.57#ibcon#about to read 4, iclass 29, count 0 2006.257.06:56:41.57#ibcon#read 4, iclass 29, count 0 2006.257.06:56:41.57#ibcon#about to read 5, iclass 29, count 0 2006.257.06:56:41.57#ibcon#read 5, iclass 29, count 0 2006.257.06:56:41.57#ibcon#about to read 6, iclass 29, count 0 2006.257.06:56:41.57#ibcon#read 6, iclass 29, count 0 2006.257.06:56:41.57#ibcon#end of sib2, iclass 29, count 0 2006.257.06:56:41.57#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:56:41.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:56:41.57#ibcon#[25=USB\r\n] 2006.257.06:56:41.57#ibcon#*before write, iclass 29, count 0 2006.257.06:56:41.57#ibcon#enter sib2, iclass 29, count 0 2006.257.06:56:41.57#ibcon#flushed, iclass 29, count 0 2006.257.06:56:41.57#ibcon#about to write, iclass 29, count 0 2006.257.06:56:41.57#ibcon#wrote, iclass 29, count 0 2006.257.06:56:41.57#ibcon#about to read 3, iclass 29, count 0 2006.257.06:56:41.60#ibcon#read 3, iclass 29, count 0 2006.257.06:56:41.60#ibcon#about to read 4, iclass 29, count 0 2006.257.06:56:41.60#ibcon#read 4, iclass 29, count 0 2006.257.06:56:41.60#ibcon#about to read 5, iclass 29, count 0 2006.257.06:56:41.60#ibcon#read 5, iclass 29, count 0 2006.257.06:56:41.60#ibcon#about to read 6, iclass 29, count 0 2006.257.06:56:41.60#ibcon#read 6, iclass 29, count 0 2006.257.06:56:41.60#ibcon#end of sib2, iclass 29, count 0 2006.257.06:56:41.60#ibcon#*after write, iclass 29, count 0 2006.257.06:56:41.60#ibcon#*before return 0, iclass 29, count 0 2006.257.06:56:41.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:41.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:41.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:56:41.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:56:41.60$vck44/valo=8,884.99 2006.257.06:56:41.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.06:56:41.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.06:56:41.60#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:41.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:41.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:41.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:41.60#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:56:41.60#ibcon#first serial, iclass 31, count 0 2006.257.06:56:41.60#ibcon#enter sib2, iclass 31, count 0 2006.257.06:56:41.60#ibcon#flushed, iclass 31, count 0 2006.257.06:56:41.60#ibcon#about to write, iclass 31, count 0 2006.257.06:56:41.60#ibcon#wrote, iclass 31, count 0 2006.257.06:56:41.60#ibcon#about to read 3, iclass 31, count 0 2006.257.06:56:41.62#ibcon#read 3, iclass 31, count 0 2006.257.06:56:41.62#ibcon#about to read 4, iclass 31, count 0 2006.257.06:56:41.62#ibcon#read 4, iclass 31, count 0 2006.257.06:56:41.62#ibcon#about to read 5, iclass 31, count 0 2006.257.06:56:41.62#ibcon#read 5, iclass 31, count 0 2006.257.06:56:41.62#ibcon#about to read 6, iclass 31, count 0 2006.257.06:56:41.62#ibcon#read 6, iclass 31, count 0 2006.257.06:56:41.62#ibcon#end of sib2, iclass 31, count 0 2006.257.06:56:41.62#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:56:41.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:56:41.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:56:41.62#ibcon#*before write, iclass 31, count 0 2006.257.06:56:41.62#ibcon#enter sib2, iclass 31, count 0 2006.257.06:56:41.62#ibcon#flushed, iclass 31, count 0 2006.257.06:56:41.62#ibcon#about to write, iclass 31, count 0 2006.257.06:56:41.62#ibcon#wrote, iclass 31, count 0 2006.257.06:56:41.62#ibcon#about to read 3, iclass 31, count 0 2006.257.06:56:41.66#ibcon#read 3, iclass 31, count 0 2006.257.06:56:41.66#ibcon#about to read 4, iclass 31, count 0 2006.257.06:56:41.66#ibcon#read 4, iclass 31, count 0 2006.257.06:56:41.66#ibcon#about to read 5, iclass 31, count 0 2006.257.06:56:41.66#ibcon#read 5, iclass 31, count 0 2006.257.06:56:41.66#ibcon#about to read 6, iclass 31, count 0 2006.257.06:56:41.66#ibcon#read 6, iclass 31, count 0 2006.257.06:56:41.66#ibcon#end of sib2, iclass 31, count 0 2006.257.06:56:41.66#ibcon#*after write, iclass 31, count 0 2006.257.06:56:41.66#ibcon#*before return 0, iclass 31, count 0 2006.257.06:56:41.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:41.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:41.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:56:41.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:56:41.66$vck44/va=8,4 2006.257.06:56:41.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.06:56:41.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.06:56:41.66#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:41.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:56:41.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:56:41.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:56:41.72#ibcon#enter wrdev, iclass 33, count 2 2006.257.06:56:41.72#ibcon#first serial, iclass 33, count 2 2006.257.06:56:41.72#ibcon#enter sib2, iclass 33, count 2 2006.257.06:56:41.72#ibcon#flushed, iclass 33, count 2 2006.257.06:56:41.72#ibcon#about to write, iclass 33, count 2 2006.257.06:56:41.72#ibcon#wrote, iclass 33, count 2 2006.257.06:56:41.72#ibcon#about to read 3, iclass 33, count 2 2006.257.06:56:41.74#ibcon#read 3, iclass 33, count 2 2006.257.06:56:41.74#ibcon#about to read 4, iclass 33, count 2 2006.257.06:56:41.74#ibcon#read 4, iclass 33, count 2 2006.257.06:56:41.74#ibcon#about to read 5, iclass 33, count 2 2006.257.06:56:41.74#ibcon#read 5, iclass 33, count 2 2006.257.06:56:41.74#ibcon#about to read 6, iclass 33, count 2 2006.257.06:56:41.74#ibcon#read 6, iclass 33, count 2 2006.257.06:56:41.74#ibcon#end of sib2, iclass 33, count 2 2006.257.06:56:41.74#ibcon#*mode == 0, iclass 33, count 2 2006.257.06:56:41.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.06:56:41.74#ibcon#[25=AT08-04\r\n] 2006.257.06:56:41.74#ibcon#*before write, iclass 33, count 2 2006.257.06:56:41.74#ibcon#enter sib2, iclass 33, count 2 2006.257.06:56:41.74#ibcon#flushed, iclass 33, count 2 2006.257.06:56:41.74#ibcon#about to write, iclass 33, count 2 2006.257.06:56:41.74#ibcon#wrote, iclass 33, count 2 2006.257.06:56:41.74#ibcon#about to read 3, iclass 33, count 2 2006.257.06:56:41.77#ibcon#read 3, iclass 33, count 2 2006.257.06:56:41.77#ibcon#about to read 4, iclass 33, count 2 2006.257.06:56:41.77#ibcon#read 4, iclass 33, count 2 2006.257.06:56:41.77#ibcon#about to read 5, iclass 33, count 2 2006.257.06:56:41.77#ibcon#read 5, iclass 33, count 2 2006.257.06:56:41.77#ibcon#about to read 6, iclass 33, count 2 2006.257.06:56:41.77#ibcon#read 6, iclass 33, count 2 2006.257.06:56:41.77#ibcon#end of sib2, iclass 33, count 2 2006.257.06:56:41.77#ibcon#*after write, iclass 33, count 2 2006.257.06:56:41.77#ibcon#*before return 0, iclass 33, count 2 2006.257.06:56:41.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:56:41.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.06:56:41.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.06:56:41.77#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:41.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:56:41.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:56:41.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:56:41.89#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:56:41.89#ibcon#first serial, iclass 33, count 0 2006.257.06:56:41.89#ibcon#enter sib2, iclass 33, count 0 2006.257.06:56:41.89#ibcon#flushed, iclass 33, count 0 2006.257.06:56:41.89#ibcon#about to write, iclass 33, count 0 2006.257.06:56:41.89#ibcon#wrote, iclass 33, count 0 2006.257.06:56:41.89#ibcon#about to read 3, iclass 33, count 0 2006.257.06:56:41.91#ibcon#read 3, iclass 33, count 0 2006.257.06:56:41.91#ibcon#about to read 4, iclass 33, count 0 2006.257.06:56:41.91#ibcon#read 4, iclass 33, count 0 2006.257.06:56:41.91#ibcon#about to read 5, iclass 33, count 0 2006.257.06:56:41.91#ibcon#read 5, iclass 33, count 0 2006.257.06:56:41.91#ibcon#about to read 6, iclass 33, count 0 2006.257.06:56:41.91#ibcon#read 6, iclass 33, count 0 2006.257.06:56:41.91#ibcon#end of sib2, iclass 33, count 0 2006.257.06:56:41.91#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:56:41.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:56:41.91#ibcon#[25=USB\r\n] 2006.257.06:56:41.91#ibcon#*before write, iclass 33, count 0 2006.257.06:56:41.91#ibcon#enter sib2, iclass 33, count 0 2006.257.06:56:41.91#ibcon#flushed, iclass 33, count 0 2006.257.06:56:41.91#ibcon#about to write, iclass 33, count 0 2006.257.06:56:41.91#ibcon#wrote, iclass 33, count 0 2006.257.06:56:41.91#ibcon#about to read 3, iclass 33, count 0 2006.257.06:56:41.94#ibcon#read 3, iclass 33, count 0 2006.257.06:56:41.94#ibcon#about to read 4, iclass 33, count 0 2006.257.06:56:41.94#ibcon#read 4, iclass 33, count 0 2006.257.06:56:41.94#ibcon#about to read 5, iclass 33, count 0 2006.257.06:56:41.94#ibcon#read 5, iclass 33, count 0 2006.257.06:56:41.94#ibcon#about to read 6, iclass 33, count 0 2006.257.06:56:41.94#ibcon#read 6, iclass 33, count 0 2006.257.06:56:41.94#ibcon#end of sib2, iclass 33, count 0 2006.257.06:56:41.94#ibcon#*after write, iclass 33, count 0 2006.257.06:56:41.94#ibcon#*before return 0, iclass 33, count 0 2006.257.06:56:41.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:56:41.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.06:56:41.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:56:41.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:56:41.94$vck44/vblo=1,629.99 2006.257.06:56:41.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.06:56:41.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.06:56:41.94#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:41.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:41.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:41.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:41.94#ibcon#enter wrdev, iclass 35, count 0 2006.257.06:56:41.94#ibcon#first serial, iclass 35, count 0 2006.257.06:56:41.94#ibcon#enter sib2, iclass 35, count 0 2006.257.06:56:41.94#ibcon#flushed, iclass 35, count 0 2006.257.06:56:41.94#ibcon#about to write, iclass 35, count 0 2006.257.06:56:41.94#ibcon#wrote, iclass 35, count 0 2006.257.06:56:41.94#ibcon#about to read 3, iclass 35, count 0 2006.257.06:56:41.96#ibcon#read 3, iclass 35, count 0 2006.257.06:56:41.96#ibcon#about to read 4, iclass 35, count 0 2006.257.06:56:41.96#ibcon#read 4, iclass 35, count 0 2006.257.06:56:41.96#ibcon#about to read 5, iclass 35, count 0 2006.257.06:56:41.96#ibcon#read 5, iclass 35, count 0 2006.257.06:56:41.96#ibcon#about to read 6, iclass 35, count 0 2006.257.06:56:41.96#ibcon#read 6, iclass 35, count 0 2006.257.06:56:41.96#ibcon#end of sib2, iclass 35, count 0 2006.257.06:56:41.96#ibcon#*mode == 0, iclass 35, count 0 2006.257.06:56:41.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.06:56:41.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:56:41.96#ibcon#*before write, iclass 35, count 0 2006.257.06:56:41.96#ibcon#enter sib2, iclass 35, count 0 2006.257.06:56:41.96#ibcon#flushed, iclass 35, count 0 2006.257.06:56:41.96#ibcon#about to write, iclass 35, count 0 2006.257.06:56:41.96#ibcon#wrote, iclass 35, count 0 2006.257.06:56:41.96#ibcon#about to read 3, iclass 35, count 0 2006.257.06:56:42.00#ibcon#read 3, iclass 35, count 0 2006.257.06:56:42.00#ibcon#about to read 4, iclass 35, count 0 2006.257.06:56:42.00#ibcon#read 4, iclass 35, count 0 2006.257.06:56:42.00#ibcon#about to read 5, iclass 35, count 0 2006.257.06:56:42.00#ibcon#read 5, iclass 35, count 0 2006.257.06:56:42.00#ibcon#about to read 6, iclass 35, count 0 2006.257.06:56:42.00#ibcon#read 6, iclass 35, count 0 2006.257.06:56:42.00#ibcon#end of sib2, iclass 35, count 0 2006.257.06:56:42.00#ibcon#*after write, iclass 35, count 0 2006.257.06:56:42.00#ibcon#*before return 0, iclass 35, count 0 2006.257.06:56:42.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:42.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.06:56:42.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.06:56:42.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.06:56:42.00$vck44/vb=1,4 2006.257.06:56:42.00#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.06:56:42.00#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.06:56:42.00#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:42.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:42.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:42.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:42.00#ibcon#enter wrdev, iclass 37, count 2 2006.257.06:56:42.00#ibcon#first serial, iclass 37, count 2 2006.257.06:56:42.00#ibcon#enter sib2, iclass 37, count 2 2006.257.06:56:42.00#ibcon#flushed, iclass 37, count 2 2006.257.06:56:42.00#ibcon#about to write, iclass 37, count 2 2006.257.06:56:42.00#ibcon#wrote, iclass 37, count 2 2006.257.06:56:42.00#ibcon#about to read 3, iclass 37, count 2 2006.257.06:56:42.02#ibcon#read 3, iclass 37, count 2 2006.257.06:56:42.02#ibcon#about to read 4, iclass 37, count 2 2006.257.06:56:42.02#ibcon#read 4, iclass 37, count 2 2006.257.06:56:42.02#ibcon#about to read 5, iclass 37, count 2 2006.257.06:56:42.02#ibcon#read 5, iclass 37, count 2 2006.257.06:56:42.02#ibcon#about to read 6, iclass 37, count 2 2006.257.06:56:42.02#ibcon#read 6, iclass 37, count 2 2006.257.06:56:42.02#ibcon#end of sib2, iclass 37, count 2 2006.257.06:56:42.02#ibcon#*mode == 0, iclass 37, count 2 2006.257.06:56:42.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.06:56:42.02#ibcon#[27=AT01-04\r\n] 2006.257.06:56:42.02#ibcon#*before write, iclass 37, count 2 2006.257.06:56:42.02#ibcon#enter sib2, iclass 37, count 2 2006.257.06:56:42.02#ibcon#flushed, iclass 37, count 2 2006.257.06:56:42.02#ibcon#about to write, iclass 37, count 2 2006.257.06:56:42.02#ibcon#wrote, iclass 37, count 2 2006.257.06:56:42.02#ibcon#about to read 3, iclass 37, count 2 2006.257.06:56:42.05#ibcon#read 3, iclass 37, count 2 2006.257.06:56:42.05#ibcon#about to read 4, iclass 37, count 2 2006.257.06:56:42.05#ibcon#read 4, iclass 37, count 2 2006.257.06:56:42.05#ibcon#about to read 5, iclass 37, count 2 2006.257.06:56:42.05#ibcon#read 5, iclass 37, count 2 2006.257.06:56:42.05#ibcon#about to read 6, iclass 37, count 2 2006.257.06:56:42.05#ibcon#read 6, iclass 37, count 2 2006.257.06:56:42.05#ibcon#end of sib2, iclass 37, count 2 2006.257.06:56:42.05#ibcon#*after write, iclass 37, count 2 2006.257.06:56:42.05#ibcon#*before return 0, iclass 37, count 2 2006.257.06:56:42.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:42.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.06:56:42.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.06:56:42.05#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:42.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:42.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:42.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:42.17#ibcon#enter wrdev, iclass 37, count 0 2006.257.06:56:42.17#ibcon#first serial, iclass 37, count 0 2006.257.06:56:42.17#ibcon#enter sib2, iclass 37, count 0 2006.257.06:56:42.17#ibcon#flushed, iclass 37, count 0 2006.257.06:56:42.17#ibcon#about to write, iclass 37, count 0 2006.257.06:56:42.17#ibcon#wrote, iclass 37, count 0 2006.257.06:56:42.17#ibcon#about to read 3, iclass 37, count 0 2006.257.06:56:42.19#ibcon#read 3, iclass 37, count 0 2006.257.06:56:42.19#ibcon#about to read 4, iclass 37, count 0 2006.257.06:56:42.19#ibcon#read 4, iclass 37, count 0 2006.257.06:56:42.19#ibcon#about to read 5, iclass 37, count 0 2006.257.06:56:42.19#ibcon#read 5, iclass 37, count 0 2006.257.06:56:42.19#ibcon#about to read 6, iclass 37, count 0 2006.257.06:56:42.19#ibcon#read 6, iclass 37, count 0 2006.257.06:56:42.19#ibcon#end of sib2, iclass 37, count 0 2006.257.06:56:42.19#ibcon#*mode == 0, iclass 37, count 0 2006.257.06:56:42.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.06:56:42.19#ibcon#[27=USB\r\n] 2006.257.06:56:42.19#ibcon#*before write, iclass 37, count 0 2006.257.06:56:42.19#ibcon#enter sib2, iclass 37, count 0 2006.257.06:56:42.19#ibcon#flushed, iclass 37, count 0 2006.257.06:56:42.19#ibcon#about to write, iclass 37, count 0 2006.257.06:56:42.19#ibcon#wrote, iclass 37, count 0 2006.257.06:56:42.19#ibcon#about to read 3, iclass 37, count 0 2006.257.06:56:42.22#ibcon#read 3, iclass 37, count 0 2006.257.06:56:42.22#ibcon#about to read 4, iclass 37, count 0 2006.257.06:56:42.22#ibcon#read 4, iclass 37, count 0 2006.257.06:56:42.22#ibcon#about to read 5, iclass 37, count 0 2006.257.06:56:42.22#ibcon#read 5, iclass 37, count 0 2006.257.06:56:42.22#ibcon#about to read 6, iclass 37, count 0 2006.257.06:56:42.22#ibcon#read 6, iclass 37, count 0 2006.257.06:56:42.22#ibcon#end of sib2, iclass 37, count 0 2006.257.06:56:42.22#ibcon#*after write, iclass 37, count 0 2006.257.06:56:42.22#ibcon#*before return 0, iclass 37, count 0 2006.257.06:56:42.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:42.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.06:56:42.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.06:56:42.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.06:56:42.22$vck44/vblo=2,634.99 2006.257.06:56:42.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.06:56:42.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.06:56:42.22#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:42.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:56:42.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:56:42.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:56:42.22#ibcon#enter wrdev, iclass 39, count 0 2006.257.06:56:42.22#ibcon#first serial, iclass 39, count 0 2006.257.06:56:42.22#ibcon#enter sib2, iclass 39, count 0 2006.257.06:56:42.22#ibcon#flushed, iclass 39, count 0 2006.257.06:56:42.22#ibcon#about to write, iclass 39, count 0 2006.257.06:56:42.22#ibcon#wrote, iclass 39, count 0 2006.257.06:56:42.22#ibcon#about to read 3, iclass 39, count 0 2006.257.06:56:42.24#ibcon#read 3, iclass 39, count 0 2006.257.06:56:42.24#ibcon#about to read 4, iclass 39, count 0 2006.257.06:56:42.24#ibcon#read 4, iclass 39, count 0 2006.257.06:56:42.24#ibcon#about to read 5, iclass 39, count 0 2006.257.06:56:42.24#ibcon#read 5, iclass 39, count 0 2006.257.06:56:42.24#ibcon#about to read 6, iclass 39, count 0 2006.257.06:56:42.24#ibcon#read 6, iclass 39, count 0 2006.257.06:56:42.24#ibcon#end of sib2, iclass 39, count 0 2006.257.06:56:42.24#ibcon#*mode == 0, iclass 39, count 0 2006.257.06:56:42.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.06:56:42.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:56:42.24#ibcon#*before write, iclass 39, count 0 2006.257.06:56:42.24#ibcon#enter sib2, iclass 39, count 0 2006.257.06:56:42.24#ibcon#flushed, iclass 39, count 0 2006.257.06:56:42.24#ibcon#about to write, iclass 39, count 0 2006.257.06:56:42.24#ibcon#wrote, iclass 39, count 0 2006.257.06:56:42.24#ibcon#about to read 3, iclass 39, count 0 2006.257.06:56:42.28#ibcon#read 3, iclass 39, count 0 2006.257.06:56:42.28#ibcon#about to read 4, iclass 39, count 0 2006.257.06:56:42.28#ibcon#read 4, iclass 39, count 0 2006.257.06:56:42.28#ibcon#about to read 5, iclass 39, count 0 2006.257.06:56:42.28#ibcon#read 5, iclass 39, count 0 2006.257.06:56:42.28#ibcon#about to read 6, iclass 39, count 0 2006.257.06:56:42.28#ibcon#read 6, iclass 39, count 0 2006.257.06:56:42.28#ibcon#end of sib2, iclass 39, count 0 2006.257.06:56:42.28#ibcon#*after write, iclass 39, count 0 2006.257.06:56:42.28#ibcon#*before return 0, iclass 39, count 0 2006.257.06:56:42.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:56:42.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.06:56:42.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.06:56:42.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.06:56:42.28$vck44/vb=2,5 2006.257.06:56:42.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.06:56:42.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.06:56:42.28#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:42.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:56:42.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:56:42.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:56:42.34#ibcon#enter wrdev, iclass 3, count 2 2006.257.06:56:42.34#ibcon#first serial, iclass 3, count 2 2006.257.06:56:42.34#ibcon#enter sib2, iclass 3, count 2 2006.257.06:56:42.34#ibcon#flushed, iclass 3, count 2 2006.257.06:56:42.34#ibcon#about to write, iclass 3, count 2 2006.257.06:56:42.34#ibcon#wrote, iclass 3, count 2 2006.257.06:56:42.34#ibcon#about to read 3, iclass 3, count 2 2006.257.06:56:42.36#ibcon#read 3, iclass 3, count 2 2006.257.06:56:42.36#ibcon#about to read 4, iclass 3, count 2 2006.257.06:56:42.36#ibcon#read 4, iclass 3, count 2 2006.257.06:56:42.36#ibcon#about to read 5, iclass 3, count 2 2006.257.06:56:42.36#ibcon#read 5, iclass 3, count 2 2006.257.06:56:42.36#ibcon#about to read 6, iclass 3, count 2 2006.257.06:56:42.36#ibcon#read 6, iclass 3, count 2 2006.257.06:56:42.36#ibcon#end of sib2, iclass 3, count 2 2006.257.06:56:42.36#ibcon#*mode == 0, iclass 3, count 2 2006.257.06:56:42.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.06:56:42.36#ibcon#[27=AT02-05\r\n] 2006.257.06:56:42.36#ibcon#*before write, iclass 3, count 2 2006.257.06:56:42.36#ibcon#enter sib2, iclass 3, count 2 2006.257.06:56:42.36#ibcon#flushed, iclass 3, count 2 2006.257.06:56:42.36#ibcon#about to write, iclass 3, count 2 2006.257.06:56:42.36#ibcon#wrote, iclass 3, count 2 2006.257.06:56:42.36#ibcon#about to read 3, iclass 3, count 2 2006.257.06:56:42.39#ibcon#read 3, iclass 3, count 2 2006.257.06:56:42.39#ibcon#about to read 4, iclass 3, count 2 2006.257.06:56:42.39#ibcon#read 4, iclass 3, count 2 2006.257.06:56:42.39#ibcon#about to read 5, iclass 3, count 2 2006.257.06:56:42.39#ibcon#read 5, iclass 3, count 2 2006.257.06:56:42.39#ibcon#about to read 6, iclass 3, count 2 2006.257.06:56:42.39#ibcon#read 6, iclass 3, count 2 2006.257.06:56:42.39#ibcon#end of sib2, iclass 3, count 2 2006.257.06:56:42.39#ibcon#*after write, iclass 3, count 2 2006.257.06:56:42.39#ibcon#*before return 0, iclass 3, count 2 2006.257.06:56:42.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:56:42.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.06:56:42.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.06:56:42.39#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:42.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:56:42.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:56:42.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:56:42.51#ibcon#enter wrdev, iclass 3, count 0 2006.257.06:56:42.51#ibcon#first serial, iclass 3, count 0 2006.257.06:56:42.51#ibcon#enter sib2, iclass 3, count 0 2006.257.06:56:42.51#ibcon#flushed, iclass 3, count 0 2006.257.06:56:42.51#ibcon#about to write, iclass 3, count 0 2006.257.06:56:42.51#ibcon#wrote, iclass 3, count 0 2006.257.06:56:42.51#ibcon#about to read 3, iclass 3, count 0 2006.257.06:56:42.53#ibcon#read 3, iclass 3, count 0 2006.257.06:56:42.53#ibcon#about to read 4, iclass 3, count 0 2006.257.06:56:42.53#ibcon#read 4, iclass 3, count 0 2006.257.06:56:42.53#ibcon#about to read 5, iclass 3, count 0 2006.257.06:56:42.53#ibcon#read 5, iclass 3, count 0 2006.257.06:56:42.53#ibcon#about to read 6, iclass 3, count 0 2006.257.06:56:42.53#ibcon#read 6, iclass 3, count 0 2006.257.06:56:42.53#ibcon#end of sib2, iclass 3, count 0 2006.257.06:56:42.53#ibcon#*mode == 0, iclass 3, count 0 2006.257.06:56:42.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.06:56:42.53#ibcon#[27=USB\r\n] 2006.257.06:56:42.53#ibcon#*before write, iclass 3, count 0 2006.257.06:56:42.53#ibcon#enter sib2, iclass 3, count 0 2006.257.06:56:42.53#ibcon#flushed, iclass 3, count 0 2006.257.06:56:42.53#ibcon#about to write, iclass 3, count 0 2006.257.06:56:42.53#ibcon#wrote, iclass 3, count 0 2006.257.06:56:42.53#ibcon#about to read 3, iclass 3, count 0 2006.257.06:56:42.56#ibcon#read 3, iclass 3, count 0 2006.257.06:56:42.56#ibcon#about to read 4, iclass 3, count 0 2006.257.06:56:42.56#ibcon#read 4, iclass 3, count 0 2006.257.06:56:42.56#ibcon#about to read 5, iclass 3, count 0 2006.257.06:56:42.56#ibcon#read 5, iclass 3, count 0 2006.257.06:56:42.56#ibcon#about to read 6, iclass 3, count 0 2006.257.06:56:42.56#ibcon#read 6, iclass 3, count 0 2006.257.06:56:42.56#ibcon#end of sib2, iclass 3, count 0 2006.257.06:56:42.56#ibcon#*after write, iclass 3, count 0 2006.257.06:56:42.56#ibcon#*before return 0, iclass 3, count 0 2006.257.06:56:42.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:56:42.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.06:56:42.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.06:56:42.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.06:56:42.56$vck44/vblo=3,649.99 2006.257.06:56:42.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.06:56:42.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.06:56:42.56#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:42.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:56:42.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:56:42.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:56:42.56#ibcon#enter wrdev, iclass 5, count 0 2006.257.06:56:42.56#ibcon#first serial, iclass 5, count 0 2006.257.06:56:42.56#ibcon#enter sib2, iclass 5, count 0 2006.257.06:56:42.56#ibcon#flushed, iclass 5, count 0 2006.257.06:56:42.56#ibcon#about to write, iclass 5, count 0 2006.257.06:56:42.56#ibcon#wrote, iclass 5, count 0 2006.257.06:56:42.56#ibcon#about to read 3, iclass 5, count 0 2006.257.06:56:42.58#ibcon#read 3, iclass 5, count 0 2006.257.06:56:42.58#ibcon#about to read 4, iclass 5, count 0 2006.257.06:56:42.58#ibcon#read 4, iclass 5, count 0 2006.257.06:56:42.58#ibcon#about to read 5, iclass 5, count 0 2006.257.06:56:42.58#ibcon#read 5, iclass 5, count 0 2006.257.06:56:42.58#ibcon#about to read 6, iclass 5, count 0 2006.257.06:56:42.58#ibcon#read 6, iclass 5, count 0 2006.257.06:56:42.58#ibcon#end of sib2, iclass 5, count 0 2006.257.06:56:42.58#ibcon#*mode == 0, iclass 5, count 0 2006.257.06:56:42.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.06:56:42.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:56:42.58#ibcon#*before write, iclass 5, count 0 2006.257.06:56:42.58#ibcon#enter sib2, iclass 5, count 0 2006.257.06:56:42.58#ibcon#flushed, iclass 5, count 0 2006.257.06:56:42.58#ibcon#about to write, iclass 5, count 0 2006.257.06:56:42.58#ibcon#wrote, iclass 5, count 0 2006.257.06:56:42.58#ibcon#about to read 3, iclass 5, count 0 2006.257.06:56:42.62#ibcon#read 3, iclass 5, count 0 2006.257.06:56:42.62#ibcon#about to read 4, iclass 5, count 0 2006.257.06:56:42.62#ibcon#read 4, iclass 5, count 0 2006.257.06:56:42.62#ibcon#about to read 5, iclass 5, count 0 2006.257.06:56:42.62#ibcon#read 5, iclass 5, count 0 2006.257.06:56:42.62#ibcon#about to read 6, iclass 5, count 0 2006.257.06:56:42.62#ibcon#read 6, iclass 5, count 0 2006.257.06:56:42.62#ibcon#end of sib2, iclass 5, count 0 2006.257.06:56:42.62#ibcon#*after write, iclass 5, count 0 2006.257.06:56:42.62#ibcon#*before return 0, iclass 5, count 0 2006.257.06:56:42.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:56:42.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.06:56:42.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.06:56:42.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.06:56:42.62$vck44/vb=3,4 2006.257.06:56:42.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.06:56:42.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.06:56:42.62#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:42.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:56:42.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:56:42.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:56:42.68#ibcon#enter wrdev, iclass 7, count 2 2006.257.06:56:42.68#ibcon#first serial, iclass 7, count 2 2006.257.06:56:42.68#ibcon#enter sib2, iclass 7, count 2 2006.257.06:56:42.68#ibcon#flushed, iclass 7, count 2 2006.257.06:56:42.68#ibcon#about to write, iclass 7, count 2 2006.257.06:56:42.68#ibcon#wrote, iclass 7, count 2 2006.257.06:56:42.68#ibcon#about to read 3, iclass 7, count 2 2006.257.06:56:42.70#ibcon#read 3, iclass 7, count 2 2006.257.06:56:42.70#ibcon#about to read 4, iclass 7, count 2 2006.257.06:56:42.70#ibcon#read 4, iclass 7, count 2 2006.257.06:56:42.70#ibcon#about to read 5, iclass 7, count 2 2006.257.06:56:42.70#ibcon#read 5, iclass 7, count 2 2006.257.06:56:42.70#ibcon#about to read 6, iclass 7, count 2 2006.257.06:56:42.70#ibcon#read 6, iclass 7, count 2 2006.257.06:56:42.70#ibcon#end of sib2, iclass 7, count 2 2006.257.06:56:42.70#ibcon#*mode == 0, iclass 7, count 2 2006.257.06:56:42.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.06:56:42.70#ibcon#[27=AT03-04\r\n] 2006.257.06:56:42.70#ibcon#*before write, iclass 7, count 2 2006.257.06:56:42.70#ibcon#enter sib2, iclass 7, count 2 2006.257.06:56:42.70#ibcon#flushed, iclass 7, count 2 2006.257.06:56:42.70#ibcon#about to write, iclass 7, count 2 2006.257.06:56:42.70#ibcon#wrote, iclass 7, count 2 2006.257.06:56:42.70#ibcon#about to read 3, iclass 7, count 2 2006.257.06:56:42.73#ibcon#read 3, iclass 7, count 2 2006.257.06:56:42.73#ibcon#about to read 4, iclass 7, count 2 2006.257.06:56:42.73#ibcon#read 4, iclass 7, count 2 2006.257.06:56:42.73#ibcon#about to read 5, iclass 7, count 2 2006.257.06:56:42.73#ibcon#read 5, iclass 7, count 2 2006.257.06:56:42.73#ibcon#about to read 6, iclass 7, count 2 2006.257.06:56:42.73#ibcon#read 6, iclass 7, count 2 2006.257.06:56:42.73#ibcon#end of sib2, iclass 7, count 2 2006.257.06:56:42.73#ibcon#*after write, iclass 7, count 2 2006.257.06:56:42.73#ibcon#*before return 0, iclass 7, count 2 2006.257.06:56:42.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:56:42.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.06:56:42.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.06:56:42.73#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:42.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:56:42.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:56:42.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:56:42.85#ibcon#enter wrdev, iclass 7, count 0 2006.257.06:56:42.85#ibcon#first serial, iclass 7, count 0 2006.257.06:56:42.85#ibcon#enter sib2, iclass 7, count 0 2006.257.06:56:42.85#ibcon#flushed, iclass 7, count 0 2006.257.06:56:42.85#ibcon#about to write, iclass 7, count 0 2006.257.06:56:42.85#ibcon#wrote, iclass 7, count 0 2006.257.06:56:42.85#ibcon#about to read 3, iclass 7, count 0 2006.257.06:56:42.87#ibcon#read 3, iclass 7, count 0 2006.257.06:56:42.87#ibcon#about to read 4, iclass 7, count 0 2006.257.06:56:42.87#ibcon#read 4, iclass 7, count 0 2006.257.06:56:42.87#ibcon#about to read 5, iclass 7, count 0 2006.257.06:56:42.87#ibcon#read 5, iclass 7, count 0 2006.257.06:56:42.87#ibcon#about to read 6, iclass 7, count 0 2006.257.06:56:42.87#ibcon#read 6, iclass 7, count 0 2006.257.06:56:42.87#ibcon#end of sib2, iclass 7, count 0 2006.257.06:56:42.87#ibcon#*mode == 0, iclass 7, count 0 2006.257.06:56:42.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.06:56:42.87#ibcon#[27=USB\r\n] 2006.257.06:56:42.87#ibcon#*before write, iclass 7, count 0 2006.257.06:56:42.87#ibcon#enter sib2, iclass 7, count 0 2006.257.06:56:42.87#ibcon#flushed, iclass 7, count 0 2006.257.06:56:42.87#ibcon#about to write, iclass 7, count 0 2006.257.06:56:42.87#ibcon#wrote, iclass 7, count 0 2006.257.06:56:42.87#ibcon#about to read 3, iclass 7, count 0 2006.257.06:56:42.90#ibcon#read 3, iclass 7, count 0 2006.257.06:56:42.90#ibcon#about to read 4, iclass 7, count 0 2006.257.06:56:42.90#ibcon#read 4, iclass 7, count 0 2006.257.06:56:42.90#ibcon#about to read 5, iclass 7, count 0 2006.257.06:56:42.90#ibcon#read 5, iclass 7, count 0 2006.257.06:56:42.90#ibcon#about to read 6, iclass 7, count 0 2006.257.06:56:42.90#ibcon#read 6, iclass 7, count 0 2006.257.06:56:42.90#ibcon#end of sib2, iclass 7, count 0 2006.257.06:56:42.90#ibcon#*after write, iclass 7, count 0 2006.257.06:56:42.90#ibcon#*before return 0, iclass 7, count 0 2006.257.06:56:42.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:56:42.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.06:56:42.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.06:56:42.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.06:56:42.90$vck44/vblo=4,679.99 2006.257.06:56:42.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.06:56:42.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.06:56:42.90#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:42.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:42.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:42.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:42.90#ibcon#enter wrdev, iclass 11, count 0 2006.257.06:56:42.90#ibcon#first serial, iclass 11, count 0 2006.257.06:56:42.90#ibcon#enter sib2, iclass 11, count 0 2006.257.06:56:42.90#ibcon#flushed, iclass 11, count 0 2006.257.06:56:42.90#ibcon#about to write, iclass 11, count 0 2006.257.06:56:42.90#ibcon#wrote, iclass 11, count 0 2006.257.06:56:42.90#ibcon#about to read 3, iclass 11, count 0 2006.257.06:56:42.92#ibcon#read 3, iclass 11, count 0 2006.257.06:56:42.92#ibcon#about to read 4, iclass 11, count 0 2006.257.06:56:42.92#ibcon#read 4, iclass 11, count 0 2006.257.06:56:42.92#ibcon#about to read 5, iclass 11, count 0 2006.257.06:56:42.92#ibcon#read 5, iclass 11, count 0 2006.257.06:56:42.92#ibcon#about to read 6, iclass 11, count 0 2006.257.06:56:42.92#ibcon#read 6, iclass 11, count 0 2006.257.06:56:42.92#ibcon#end of sib2, iclass 11, count 0 2006.257.06:56:42.92#ibcon#*mode == 0, iclass 11, count 0 2006.257.06:56:42.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.06:56:42.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:56:42.92#ibcon#*before write, iclass 11, count 0 2006.257.06:56:42.92#ibcon#enter sib2, iclass 11, count 0 2006.257.06:56:42.92#ibcon#flushed, iclass 11, count 0 2006.257.06:56:42.92#ibcon#about to write, iclass 11, count 0 2006.257.06:56:42.92#ibcon#wrote, iclass 11, count 0 2006.257.06:56:42.92#ibcon#about to read 3, iclass 11, count 0 2006.257.06:56:42.96#ibcon#read 3, iclass 11, count 0 2006.257.06:56:42.96#ibcon#about to read 4, iclass 11, count 0 2006.257.06:56:42.96#ibcon#read 4, iclass 11, count 0 2006.257.06:56:42.96#ibcon#about to read 5, iclass 11, count 0 2006.257.06:56:42.96#ibcon#read 5, iclass 11, count 0 2006.257.06:56:42.96#ibcon#about to read 6, iclass 11, count 0 2006.257.06:56:42.96#ibcon#read 6, iclass 11, count 0 2006.257.06:56:42.96#ibcon#end of sib2, iclass 11, count 0 2006.257.06:56:42.96#ibcon#*after write, iclass 11, count 0 2006.257.06:56:42.96#ibcon#*before return 0, iclass 11, count 0 2006.257.06:56:42.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:42.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.06:56:42.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.06:56:42.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.06:56:42.96$vck44/vb=4,5 2006.257.06:56:42.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.06:56:42.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.06:56:42.96#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:42.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:43.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:43.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:43.02#ibcon#enter wrdev, iclass 13, count 2 2006.257.06:56:43.02#ibcon#first serial, iclass 13, count 2 2006.257.06:56:43.02#ibcon#enter sib2, iclass 13, count 2 2006.257.06:56:43.02#ibcon#flushed, iclass 13, count 2 2006.257.06:56:43.02#ibcon#about to write, iclass 13, count 2 2006.257.06:56:43.02#ibcon#wrote, iclass 13, count 2 2006.257.06:56:43.02#ibcon#about to read 3, iclass 13, count 2 2006.257.06:56:43.04#ibcon#read 3, iclass 13, count 2 2006.257.06:56:43.04#ibcon#about to read 4, iclass 13, count 2 2006.257.06:56:43.04#ibcon#read 4, iclass 13, count 2 2006.257.06:56:43.04#ibcon#about to read 5, iclass 13, count 2 2006.257.06:56:43.04#ibcon#read 5, iclass 13, count 2 2006.257.06:56:43.04#ibcon#about to read 6, iclass 13, count 2 2006.257.06:56:43.04#ibcon#read 6, iclass 13, count 2 2006.257.06:56:43.04#ibcon#end of sib2, iclass 13, count 2 2006.257.06:56:43.04#ibcon#*mode == 0, iclass 13, count 2 2006.257.06:56:43.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.06:56:43.04#ibcon#[27=AT04-05\r\n] 2006.257.06:56:43.04#ibcon#*before write, iclass 13, count 2 2006.257.06:56:43.04#ibcon#enter sib2, iclass 13, count 2 2006.257.06:56:43.04#ibcon#flushed, iclass 13, count 2 2006.257.06:56:43.04#ibcon#about to write, iclass 13, count 2 2006.257.06:56:43.04#ibcon#wrote, iclass 13, count 2 2006.257.06:56:43.04#ibcon#about to read 3, iclass 13, count 2 2006.257.06:56:43.07#ibcon#read 3, iclass 13, count 2 2006.257.06:56:43.07#ibcon#about to read 4, iclass 13, count 2 2006.257.06:56:43.07#ibcon#read 4, iclass 13, count 2 2006.257.06:56:43.07#ibcon#about to read 5, iclass 13, count 2 2006.257.06:56:43.07#ibcon#read 5, iclass 13, count 2 2006.257.06:56:43.07#ibcon#about to read 6, iclass 13, count 2 2006.257.06:56:43.07#ibcon#read 6, iclass 13, count 2 2006.257.06:56:43.07#ibcon#end of sib2, iclass 13, count 2 2006.257.06:56:43.07#ibcon#*after write, iclass 13, count 2 2006.257.06:56:43.07#ibcon#*before return 0, iclass 13, count 2 2006.257.06:56:43.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:43.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.06:56:43.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.06:56:43.07#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:43.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:43.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:43.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:43.19#ibcon#enter wrdev, iclass 13, count 0 2006.257.06:56:43.19#ibcon#first serial, iclass 13, count 0 2006.257.06:56:43.19#ibcon#enter sib2, iclass 13, count 0 2006.257.06:56:43.19#ibcon#flushed, iclass 13, count 0 2006.257.06:56:43.19#ibcon#about to write, iclass 13, count 0 2006.257.06:56:43.19#ibcon#wrote, iclass 13, count 0 2006.257.06:56:43.19#ibcon#about to read 3, iclass 13, count 0 2006.257.06:56:43.21#ibcon#read 3, iclass 13, count 0 2006.257.06:56:43.21#ibcon#about to read 4, iclass 13, count 0 2006.257.06:56:43.21#ibcon#read 4, iclass 13, count 0 2006.257.06:56:43.21#ibcon#about to read 5, iclass 13, count 0 2006.257.06:56:43.21#ibcon#read 5, iclass 13, count 0 2006.257.06:56:43.21#ibcon#about to read 6, iclass 13, count 0 2006.257.06:56:43.21#ibcon#read 6, iclass 13, count 0 2006.257.06:56:43.21#ibcon#end of sib2, iclass 13, count 0 2006.257.06:56:43.21#ibcon#*mode == 0, iclass 13, count 0 2006.257.06:56:43.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.06:56:43.21#ibcon#[27=USB\r\n] 2006.257.06:56:43.21#ibcon#*before write, iclass 13, count 0 2006.257.06:56:43.21#ibcon#enter sib2, iclass 13, count 0 2006.257.06:56:43.21#ibcon#flushed, iclass 13, count 0 2006.257.06:56:43.21#ibcon#about to write, iclass 13, count 0 2006.257.06:56:43.21#ibcon#wrote, iclass 13, count 0 2006.257.06:56:43.21#ibcon#about to read 3, iclass 13, count 0 2006.257.06:56:43.24#ibcon#read 3, iclass 13, count 0 2006.257.06:56:43.24#ibcon#about to read 4, iclass 13, count 0 2006.257.06:56:43.24#ibcon#read 4, iclass 13, count 0 2006.257.06:56:43.24#ibcon#about to read 5, iclass 13, count 0 2006.257.06:56:43.24#ibcon#read 5, iclass 13, count 0 2006.257.06:56:43.24#ibcon#about to read 6, iclass 13, count 0 2006.257.06:56:43.24#ibcon#read 6, iclass 13, count 0 2006.257.06:56:43.24#ibcon#end of sib2, iclass 13, count 0 2006.257.06:56:43.24#ibcon#*after write, iclass 13, count 0 2006.257.06:56:43.24#ibcon#*before return 0, iclass 13, count 0 2006.257.06:56:43.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:43.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.06:56:43.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.06:56:43.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.06:56:43.24$vck44/vblo=5,709.99 2006.257.06:56:43.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.06:56:43.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.06:56:43.24#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:43.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:43.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:43.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:43.24#ibcon#enter wrdev, iclass 15, count 0 2006.257.06:56:43.24#ibcon#first serial, iclass 15, count 0 2006.257.06:56:43.24#ibcon#enter sib2, iclass 15, count 0 2006.257.06:56:43.24#ibcon#flushed, iclass 15, count 0 2006.257.06:56:43.24#ibcon#about to write, iclass 15, count 0 2006.257.06:56:43.24#ibcon#wrote, iclass 15, count 0 2006.257.06:56:43.24#ibcon#about to read 3, iclass 15, count 0 2006.257.06:56:43.26#ibcon#read 3, iclass 15, count 0 2006.257.06:56:43.26#ibcon#about to read 4, iclass 15, count 0 2006.257.06:56:43.26#ibcon#read 4, iclass 15, count 0 2006.257.06:56:43.26#ibcon#about to read 5, iclass 15, count 0 2006.257.06:56:43.26#ibcon#read 5, iclass 15, count 0 2006.257.06:56:43.26#ibcon#about to read 6, iclass 15, count 0 2006.257.06:56:43.26#ibcon#read 6, iclass 15, count 0 2006.257.06:56:43.26#ibcon#end of sib2, iclass 15, count 0 2006.257.06:56:43.26#ibcon#*mode == 0, iclass 15, count 0 2006.257.06:56:43.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.06:56:43.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:56:43.26#ibcon#*before write, iclass 15, count 0 2006.257.06:56:43.26#ibcon#enter sib2, iclass 15, count 0 2006.257.06:56:43.26#ibcon#flushed, iclass 15, count 0 2006.257.06:56:43.26#ibcon#about to write, iclass 15, count 0 2006.257.06:56:43.26#ibcon#wrote, iclass 15, count 0 2006.257.06:56:43.26#ibcon#about to read 3, iclass 15, count 0 2006.257.06:56:43.30#ibcon#read 3, iclass 15, count 0 2006.257.06:56:43.30#ibcon#about to read 4, iclass 15, count 0 2006.257.06:56:43.30#ibcon#read 4, iclass 15, count 0 2006.257.06:56:43.30#ibcon#about to read 5, iclass 15, count 0 2006.257.06:56:43.30#ibcon#read 5, iclass 15, count 0 2006.257.06:56:43.30#ibcon#about to read 6, iclass 15, count 0 2006.257.06:56:43.30#ibcon#read 6, iclass 15, count 0 2006.257.06:56:43.30#ibcon#end of sib2, iclass 15, count 0 2006.257.06:56:43.30#ibcon#*after write, iclass 15, count 0 2006.257.06:56:43.30#ibcon#*before return 0, iclass 15, count 0 2006.257.06:56:43.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:43.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.06:56:43.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.06:56:43.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.06:56:43.30$vck44/vb=5,4 2006.257.06:56:43.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.06:56:43.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.06:56:43.30#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:43.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:43.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:43.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:43.36#ibcon#enter wrdev, iclass 17, count 2 2006.257.06:56:43.36#ibcon#first serial, iclass 17, count 2 2006.257.06:56:43.36#ibcon#enter sib2, iclass 17, count 2 2006.257.06:56:43.36#ibcon#flushed, iclass 17, count 2 2006.257.06:56:43.36#ibcon#about to write, iclass 17, count 2 2006.257.06:56:43.36#ibcon#wrote, iclass 17, count 2 2006.257.06:56:43.36#ibcon#about to read 3, iclass 17, count 2 2006.257.06:56:43.38#ibcon#read 3, iclass 17, count 2 2006.257.06:56:43.38#ibcon#about to read 4, iclass 17, count 2 2006.257.06:56:43.38#ibcon#read 4, iclass 17, count 2 2006.257.06:56:43.38#ibcon#about to read 5, iclass 17, count 2 2006.257.06:56:43.38#ibcon#read 5, iclass 17, count 2 2006.257.06:56:43.38#ibcon#about to read 6, iclass 17, count 2 2006.257.06:56:43.38#ibcon#read 6, iclass 17, count 2 2006.257.06:56:43.38#ibcon#end of sib2, iclass 17, count 2 2006.257.06:56:43.38#ibcon#*mode == 0, iclass 17, count 2 2006.257.06:56:43.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.06:56:43.38#ibcon#[27=AT05-04\r\n] 2006.257.06:56:43.38#ibcon#*before write, iclass 17, count 2 2006.257.06:56:43.38#ibcon#enter sib2, iclass 17, count 2 2006.257.06:56:43.38#ibcon#flushed, iclass 17, count 2 2006.257.06:56:43.38#ibcon#about to write, iclass 17, count 2 2006.257.06:56:43.38#ibcon#wrote, iclass 17, count 2 2006.257.06:56:43.38#ibcon#about to read 3, iclass 17, count 2 2006.257.06:56:43.41#ibcon#read 3, iclass 17, count 2 2006.257.06:56:43.41#ibcon#about to read 4, iclass 17, count 2 2006.257.06:56:43.41#ibcon#read 4, iclass 17, count 2 2006.257.06:56:43.41#ibcon#about to read 5, iclass 17, count 2 2006.257.06:56:43.41#ibcon#read 5, iclass 17, count 2 2006.257.06:56:43.41#ibcon#about to read 6, iclass 17, count 2 2006.257.06:56:43.41#ibcon#read 6, iclass 17, count 2 2006.257.06:56:43.41#ibcon#end of sib2, iclass 17, count 2 2006.257.06:56:43.41#ibcon#*after write, iclass 17, count 2 2006.257.06:56:43.41#ibcon#*before return 0, iclass 17, count 2 2006.257.06:56:43.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:43.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.06:56:43.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.06:56:43.41#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:43.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:43.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:43.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:43.53#ibcon#enter wrdev, iclass 17, count 0 2006.257.06:56:43.53#ibcon#first serial, iclass 17, count 0 2006.257.06:56:43.53#ibcon#enter sib2, iclass 17, count 0 2006.257.06:56:43.53#ibcon#flushed, iclass 17, count 0 2006.257.06:56:43.53#ibcon#about to write, iclass 17, count 0 2006.257.06:56:43.53#ibcon#wrote, iclass 17, count 0 2006.257.06:56:43.53#ibcon#about to read 3, iclass 17, count 0 2006.257.06:56:43.55#ibcon#read 3, iclass 17, count 0 2006.257.06:56:43.55#ibcon#about to read 4, iclass 17, count 0 2006.257.06:56:43.55#ibcon#read 4, iclass 17, count 0 2006.257.06:56:43.55#ibcon#about to read 5, iclass 17, count 0 2006.257.06:56:43.55#ibcon#read 5, iclass 17, count 0 2006.257.06:56:43.55#ibcon#about to read 6, iclass 17, count 0 2006.257.06:56:43.55#ibcon#read 6, iclass 17, count 0 2006.257.06:56:43.55#ibcon#end of sib2, iclass 17, count 0 2006.257.06:56:43.55#ibcon#*mode == 0, iclass 17, count 0 2006.257.06:56:43.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.06:56:43.55#ibcon#[27=USB\r\n] 2006.257.06:56:43.55#ibcon#*before write, iclass 17, count 0 2006.257.06:56:43.55#ibcon#enter sib2, iclass 17, count 0 2006.257.06:56:43.55#ibcon#flushed, iclass 17, count 0 2006.257.06:56:43.55#ibcon#about to write, iclass 17, count 0 2006.257.06:56:43.55#ibcon#wrote, iclass 17, count 0 2006.257.06:56:43.55#ibcon#about to read 3, iclass 17, count 0 2006.257.06:56:43.58#ibcon#read 3, iclass 17, count 0 2006.257.06:56:43.58#ibcon#about to read 4, iclass 17, count 0 2006.257.06:56:43.58#ibcon#read 4, iclass 17, count 0 2006.257.06:56:43.58#ibcon#about to read 5, iclass 17, count 0 2006.257.06:56:43.58#ibcon#read 5, iclass 17, count 0 2006.257.06:56:43.58#ibcon#about to read 6, iclass 17, count 0 2006.257.06:56:43.58#ibcon#read 6, iclass 17, count 0 2006.257.06:56:43.58#ibcon#end of sib2, iclass 17, count 0 2006.257.06:56:43.58#ibcon#*after write, iclass 17, count 0 2006.257.06:56:43.58#ibcon#*before return 0, iclass 17, count 0 2006.257.06:56:43.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:43.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.06:56:43.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.06:56:43.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.06:56:43.58$vck44/vblo=6,719.99 2006.257.06:56:43.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.06:56:43.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.06:56:43.58#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:43.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:43.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:43.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:43.58#ibcon#enter wrdev, iclass 19, count 0 2006.257.06:56:43.58#ibcon#first serial, iclass 19, count 0 2006.257.06:56:43.58#ibcon#enter sib2, iclass 19, count 0 2006.257.06:56:43.58#ibcon#flushed, iclass 19, count 0 2006.257.06:56:43.58#ibcon#about to write, iclass 19, count 0 2006.257.06:56:43.58#ibcon#wrote, iclass 19, count 0 2006.257.06:56:43.58#ibcon#about to read 3, iclass 19, count 0 2006.257.06:56:43.60#ibcon#read 3, iclass 19, count 0 2006.257.06:56:43.60#ibcon#about to read 4, iclass 19, count 0 2006.257.06:56:43.60#ibcon#read 4, iclass 19, count 0 2006.257.06:56:43.60#ibcon#about to read 5, iclass 19, count 0 2006.257.06:56:43.60#ibcon#read 5, iclass 19, count 0 2006.257.06:56:43.60#ibcon#about to read 6, iclass 19, count 0 2006.257.06:56:43.60#ibcon#read 6, iclass 19, count 0 2006.257.06:56:43.60#ibcon#end of sib2, iclass 19, count 0 2006.257.06:56:43.60#ibcon#*mode == 0, iclass 19, count 0 2006.257.06:56:43.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.06:56:43.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:56:43.60#ibcon#*before write, iclass 19, count 0 2006.257.06:56:43.60#ibcon#enter sib2, iclass 19, count 0 2006.257.06:56:43.60#ibcon#flushed, iclass 19, count 0 2006.257.06:56:43.60#ibcon#about to write, iclass 19, count 0 2006.257.06:56:43.60#ibcon#wrote, iclass 19, count 0 2006.257.06:56:43.60#ibcon#about to read 3, iclass 19, count 0 2006.257.06:56:43.64#ibcon#read 3, iclass 19, count 0 2006.257.06:56:43.64#ibcon#about to read 4, iclass 19, count 0 2006.257.06:56:43.64#ibcon#read 4, iclass 19, count 0 2006.257.06:56:43.64#ibcon#about to read 5, iclass 19, count 0 2006.257.06:56:43.64#ibcon#read 5, iclass 19, count 0 2006.257.06:56:43.64#ibcon#about to read 6, iclass 19, count 0 2006.257.06:56:43.64#ibcon#read 6, iclass 19, count 0 2006.257.06:56:43.64#ibcon#end of sib2, iclass 19, count 0 2006.257.06:56:43.64#ibcon#*after write, iclass 19, count 0 2006.257.06:56:43.64#ibcon#*before return 0, iclass 19, count 0 2006.257.06:56:43.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:43.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.06:56:43.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.06:56:43.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.06:56:43.64$vck44/vb=6,4 2006.257.06:56:43.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.06:56:43.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.06:56:43.64#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:43.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:43.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:43.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:43.70#ibcon#enter wrdev, iclass 21, count 2 2006.257.06:56:43.70#ibcon#first serial, iclass 21, count 2 2006.257.06:56:43.70#ibcon#enter sib2, iclass 21, count 2 2006.257.06:56:43.70#ibcon#flushed, iclass 21, count 2 2006.257.06:56:43.70#ibcon#about to write, iclass 21, count 2 2006.257.06:56:43.70#ibcon#wrote, iclass 21, count 2 2006.257.06:56:43.70#ibcon#about to read 3, iclass 21, count 2 2006.257.06:56:43.72#ibcon#read 3, iclass 21, count 2 2006.257.06:56:43.72#ibcon#about to read 4, iclass 21, count 2 2006.257.06:56:43.72#ibcon#read 4, iclass 21, count 2 2006.257.06:56:43.72#ibcon#about to read 5, iclass 21, count 2 2006.257.06:56:43.72#ibcon#read 5, iclass 21, count 2 2006.257.06:56:43.72#ibcon#about to read 6, iclass 21, count 2 2006.257.06:56:43.72#ibcon#read 6, iclass 21, count 2 2006.257.06:56:43.72#ibcon#end of sib2, iclass 21, count 2 2006.257.06:56:43.72#ibcon#*mode == 0, iclass 21, count 2 2006.257.06:56:43.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.06:56:43.72#ibcon#[27=AT06-04\r\n] 2006.257.06:56:43.72#ibcon#*before write, iclass 21, count 2 2006.257.06:56:43.72#ibcon#enter sib2, iclass 21, count 2 2006.257.06:56:43.72#ibcon#flushed, iclass 21, count 2 2006.257.06:56:43.72#ibcon#about to write, iclass 21, count 2 2006.257.06:56:43.72#ibcon#wrote, iclass 21, count 2 2006.257.06:56:43.72#ibcon#about to read 3, iclass 21, count 2 2006.257.06:56:43.75#ibcon#read 3, iclass 21, count 2 2006.257.06:56:43.75#ibcon#about to read 4, iclass 21, count 2 2006.257.06:56:43.75#ibcon#read 4, iclass 21, count 2 2006.257.06:56:43.75#ibcon#about to read 5, iclass 21, count 2 2006.257.06:56:43.75#ibcon#read 5, iclass 21, count 2 2006.257.06:56:43.75#ibcon#about to read 6, iclass 21, count 2 2006.257.06:56:43.75#ibcon#read 6, iclass 21, count 2 2006.257.06:56:43.75#ibcon#end of sib2, iclass 21, count 2 2006.257.06:56:43.75#ibcon#*after write, iclass 21, count 2 2006.257.06:56:43.75#ibcon#*before return 0, iclass 21, count 2 2006.257.06:56:43.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:43.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.06:56:43.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.06:56:43.75#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:43.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:43.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:43.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:43.87#ibcon#enter wrdev, iclass 21, count 0 2006.257.06:56:43.87#ibcon#first serial, iclass 21, count 0 2006.257.06:56:43.87#ibcon#enter sib2, iclass 21, count 0 2006.257.06:56:43.87#ibcon#flushed, iclass 21, count 0 2006.257.06:56:43.87#ibcon#about to write, iclass 21, count 0 2006.257.06:56:43.87#ibcon#wrote, iclass 21, count 0 2006.257.06:56:43.87#ibcon#about to read 3, iclass 21, count 0 2006.257.06:56:43.89#ibcon#read 3, iclass 21, count 0 2006.257.06:56:43.89#ibcon#about to read 4, iclass 21, count 0 2006.257.06:56:43.89#ibcon#read 4, iclass 21, count 0 2006.257.06:56:43.89#ibcon#about to read 5, iclass 21, count 0 2006.257.06:56:43.89#ibcon#read 5, iclass 21, count 0 2006.257.06:56:43.89#ibcon#about to read 6, iclass 21, count 0 2006.257.06:56:43.89#ibcon#read 6, iclass 21, count 0 2006.257.06:56:43.89#ibcon#end of sib2, iclass 21, count 0 2006.257.06:56:43.89#ibcon#*mode == 0, iclass 21, count 0 2006.257.06:56:43.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.06:56:43.89#ibcon#[27=USB\r\n] 2006.257.06:56:43.89#ibcon#*before write, iclass 21, count 0 2006.257.06:56:43.89#ibcon#enter sib2, iclass 21, count 0 2006.257.06:56:43.89#ibcon#flushed, iclass 21, count 0 2006.257.06:56:43.89#ibcon#about to write, iclass 21, count 0 2006.257.06:56:43.89#ibcon#wrote, iclass 21, count 0 2006.257.06:56:43.89#ibcon#about to read 3, iclass 21, count 0 2006.257.06:56:43.92#ibcon#read 3, iclass 21, count 0 2006.257.06:56:43.92#ibcon#about to read 4, iclass 21, count 0 2006.257.06:56:43.92#ibcon#read 4, iclass 21, count 0 2006.257.06:56:43.92#ibcon#about to read 5, iclass 21, count 0 2006.257.06:56:43.92#ibcon#read 5, iclass 21, count 0 2006.257.06:56:43.92#ibcon#about to read 6, iclass 21, count 0 2006.257.06:56:43.92#ibcon#read 6, iclass 21, count 0 2006.257.06:56:43.92#ibcon#end of sib2, iclass 21, count 0 2006.257.06:56:43.92#ibcon#*after write, iclass 21, count 0 2006.257.06:56:43.92#ibcon#*before return 0, iclass 21, count 0 2006.257.06:56:43.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:43.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.06:56:43.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.06:56:43.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.06:56:43.92$vck44/vblo=7,734.99 2006.257.06:56:43.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.06:56:43.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.06:56:43.92#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:43.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:43.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:43.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:43.92#ibcon#enter wrdev, iclass 23, count 0 2006.257.06:56:43.92#ibcon#first serial, iclass 23, count 0 2006.257.06:56:43.92#ibcon#enter sib2, iclass 23, count 0 2006.257.06:56:43.92#ibcon#flushed, iclass 23, count 0 2006.257.06:56:43.92#ibcon#about to write, iclass 23, count 0 2006.257.06:56:43.92#ibcon#wrote, iclass 23, count 0 2006.257.06:56:43.92#ibcon#about to read 3, iclass 23, count 0 2006.257.06:56:43.94#ibcon#read 3, iclass 23, count 0 2006.257.06:56:43.94#ibcon#about to read 4, iclass 23, count 0 2006.257.06:56:43.94#ibcon#read 4, iclass 23, count 0 2006.257.06:56:43.94#ibcon#about to read 5, iclass 23, count 0 2006.257.06:56:43.94#ibcon#read 5, iclass 23, count 0 2006.257.06:56:43.94#ibcon#about to read 6, iclass 23, count 0 2006.257.06:56:43.94#ibcon#read 6, iclass 23, count 0 2006.257.06:56:43.94#ibcon#end of sib2, iclass 23, count 0 2006.257.06:56:43.94#ibcon#*mode == 0, iclass 23, count 0 2006.257.06:56:43.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.06:56:43.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:56:43.94#ibcon#*before write, iclass 23, count 0 2006.257.06:56:43.94#ibcon#enter sib2, iclass 23, count 0 2006.257.06:56:43.94#ibcon#flushed, iclass 23, count 0 2006.257.06:56:43.94#ibcon#about to write, iclass 23, count 0 2006.257.06:56:43.94#ibcon#wrote, iclass 23, count 0 2006.257.06:56:43.94#ibcon#about to read 3, iclass 23, count 0 2006.257.06:56:43.98#ibcon#read 3, iclass 23, count 0 2006.257.06:56:43.98#ibcon#about to read 4, iclass 23, count 0 2006.257.06:56:43.98#ibcon#read 4, iclass 23, count 0 2006.257.06:56:43.98#ibcon#about to read 5, iclass 23, count 0 2006.257.06:56:43.98#ibcon#read 5, iclass 23, count 0 2006.257.06:56:43.98#ibcon#about to read 6, iclass 23, count 0 2006.257.06:56:43.98#ibcon#read 6, iclass 23, count 0 2006.257.06:56:43.98#ibcon#end of sib2, iclass 23, count 0 2006.257.06:56:43.98#ibcon#*after write, iclass 23, count 0 2006.257.06:56:43.98#ibcon#*before return 0, iclass 23, count 0 2006.257.06:56:43.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:43.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.06:56:43.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.06:56:43.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.06:56:43.98$vck44/vb=7,4 2006.257.06:56:43.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.06:56:43.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.06:56:43.98#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:43.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:44.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:44.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:44.04#ibcon#enter wrdev, iclass 25, count 2 2006.257.06:56:44.04#ibcon#first serial, iclass 25, count 2 2006.257.06:56:44.04#ibcon#enter sib2, iclass 25, count 2 2006.257.06:56:44.04#ibcon#flushed, iclass 25, count 2 2006.257.06:56:44.04#ibcon#about to write, iclass 25, count 2 2006.257.06:56:44.04#ibcon#wrote, iclass 25, count 2 2006.257.06:56:44.04#ibcon#about to read 3, iclass 25, count 2 2006.257.06:56:44.06#ibcon#read 3, iclass 25, count 2 2006.257.06:56:44.06#ibcon#about to read 4, iclass 25, count 2 2006.257.06:56:44.06#ibcon#read 4, iclass 25, count 2 2006.257.06:56:44.06#ibcon#about to read 5, iclass 25, count 2 2006.257.06:56:44.06#ibcon#read 5, iclass 25, count 2 2006.257.06:56:44.06#ibcon#about to read 6, iclass 25, count 2 2006.257.06:56:44.06#ibcon#read 6, iclass 25, count 2 2006.257.06:56:44.06#ibcon#end of sib2, iclass 25, count 2 2006.257.06:56:44.06#ibcon#*mode == 0, iclass 25, count 2 2006.257.06:56:44.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.06:56:44.06#ibcon#[27=AT07-04\r\n] 2006.257.06:56:44.06#ibcon#*before write, iclass 25, count 2 2006.257.06:56:44.06#ibcon#enter sib2, iclass 25, count 2 2006.257.06:56:44.06#ibcon#flushed, iclass 25, count 2 2006.257.06:56:44.06#ibcon#about to write, iclass 25, count 2 2006.257.06:56:44.06#ibcon#wrote, iclass 25, count 2 2006.257.06:56:44.06#ibcon#about to read 3, iclass 25, count 2 2006.257.06:56:44.09#ibcon#read 3, iclass 25, count 2 2006.257.06:56:44.09#ibcon#about to read 4, iclass 25, count 2 2006.257.06:56:44.09#ibcon#read 4, iclass 25, count 2 2006.257.06:56:44.09#ibcon#about to read 5, iclass 25, count 2 2006.257.06:56:44.09#ibcon#read 5, iclass 25, count 2 2006.257.06:56:44.09#ibcon#about to read 6, iclass 25, count 2 2006.257.06:56:44.09#ibcon#read 6, iclass 25, count 2 2006.257.06:56:44.09#ibcon#end of sib2, iclass 25, count 2 2006.257.06:56:44.09#ibcon#*after write, iclass 25, count 2 2006.257.06:56:44.09#ibcon#*before return 0, iclass 25, count 2 2006.257.06:56:44.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:44.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.06:56:44.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.06:56:44.09#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:44.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:44.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:44.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:44.21#ibcon#enter wrdev, iclass 25, count 0 2006.257.06:56:44.21#ibcon#first serial, iclass 25, count 0 2006.257.06:56:44.21#ibcon#enter sib2, iclass 25, count 0 2006.257.06:56:44.21#ibcon#flushed, iclass 25, count 0 2006.257.06:56:44.21#ibcon#about to write, iclass 25, count 0 2006.257.06:56:44.21#ibcon#wrote, iclass 25, count 0 2006.257.06:56:44.21#ibcon#about to read 3, iclass 25, count 0 2006.257.06:56:44.23#ibcon#read 3, iclass 25, count 0 2006.257.06:56:44.23#ibcon#about to read 4, iclass 25, count 0 2006.257.06:56:44.23#ibcon#read 4, iclass 25, count 0 2006.257.06:56:44.23#ibcon#about to read 5, iclass 25, count 0 2006.257.06:56:44.23#ibcon#read 5, iclass 25, count 0 2006.257.06:56:44.23#ibcon#about to read 6, iclass 25, count 0 2006.257.06:56:44.23#ibcon#read 6, iclass 25, count 0 2006.257.06:56:44.23#ibcon#end of sib2, iclass 25, count 0 2006.257.06:56:44.23#ibcon#*mode == 0, iclass 25, count 0 2006.257.06:56:44.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.06:56:44.23#ibcon#[27=USB\r\n] 2006.257.06:56:44.23#ibcon#*before write, iclass 25, count 0 2006.257.06:56:44.23#ibcon#enter sib2, iclass 25, count 0 2006.257.06:56:44.23#ibcon#flushed, iclass 25, count 0 2006.257.06:56:44.23#ibcon#about to write, iclass 25, count 0 2006.257.06:56:44.23#ibcon#wrote, iclass 25, count 0 2006.257.06:56:44.23#ibcon#about to read 3, iclass 25, count 0 2006.257.06:56:44.26#ibcon#read 3, iclass 25, count 0 2006.257.06:56:44.26#ibcon#about to read 4, iclass 25, count 0 2006.257.06:56:44.26#ibcon#read 4, iclass 25, count 0 2006.257.06:56:44.26#ibcon#about to read 5, iclass 25, count 0 2006.257.06:56:44.26#ibcon#read 5, iclass 25, count 0 2006.257.06:56:44.26#ibcon#about to read 6, iclass 25, count 0 2006.257.06:56:44.26#ibcon#read 6, iclass 25, count 0 2006.257.06:56:44.26#ibcon#end of sib2, iclass 25, count 0 2006.257.06:56:44.26#ibcon#*after write, iclass 25, count 0 2006.257.06:56:44.26#ibcon#*before return 0, iclass 25, count 0 2006.257.06:56:44.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:44.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.06:56:44.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.06:56:44.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.06:56:44.26$vck44/vblo=8,744.99 2006.257.06:56:44.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.06:56:44.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.06:56:44.26#ibcon#ireg 17 cls_cnt 0 2006.257.06:56:44.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:44.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:44.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:44.26#ibcon#enter wrdev, iclass 27, count 0 2006.257.06:56:44.26#ibcon#first serial, iclass 27, count 0 2006.257.06:56:44.26#ibcon#enter sib2, iclass 27, count 0 2006.257.06:56:44.26#ibcon#flushed, iclass 27, count 0 2006.257.06:56:44.26#ibcon#about to write, iclass 27, count 0 2006.257.06:56:44.26#ibcon#wrote, iclass 27, count 0 2006.257.06:56:44.26#ibcon#about to read 3, iclass 27, count 0 2006.257.06:56:44.28#ibcon#read 3, iclass 27, count 0 2006.257.06:56:44.28#ibcon#about to read 4, iclass 27, count 0 2006.257.06:56:44.28#ibcon#read 4, iclass 27, count 0 2006.257.06:56:44.28#ibcon#about to read 5, iclass 27, count 0 2006.257.06:56:44.28#ibcon#read 5, iclass 27, count 0 2006.257.06:56:44.28#ibcon#about to read 6, iclass 27, count 0 2006.257.06:56:44.28#ibcon#read 6, iclass 27, count 0 2006.257.06:56:44.28#ibcon#end of sib2, iclass 27, count 0 2006.257.06:56:44.28#ibcon#*mode == 0, iclass 27, count 0 2006.257.06:56:44.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.06:56:44.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:56:44.28#ibcon#*before write, iclass 27, count 0 2006.257.06:56:44.28#ibcon#enter sib2, iclass 27, count 0 2006.257.06:56:44.28#ibcon#flushed, iclass 27, count 0 2006.257.06:56:44.28#ibcon#about to write, iclass 27, count 0 2006.257.06:56:44.28#ibcon#wrote, iclass 27, count 0 2006.257.06:56:44.28#ibcon#about to read 3, iclass 27, count 0 2006.257.06:56:44.32#ibcon#read 3, iclass 27, count 0 2006.257.06:56:44.32#ibcon#about to read 4, iclass 27, count 0 2006.257.06:56:44.32#ibcon#read 4, iclass 27, count 0 2006.257.06:56:44.32#ibcon#about to read 5, iclass 27, count 0 2006.257.06:56:44.32#ibcon#read 5, iclass 27, count 0 2006.257.06:56:44.32#ibcon#about to read 6, iclass 27, count 0 2006.257.06:56:44.32#ibcon#read 6, iclass 27, count 0 2006.257.06:56:44.32#ibcon#end of sib2, iclass 27, count 0 2006.257.06:56:44.32#ibcon#*after write, iclass 27, count 0 2006.257.06:56:44.32#ibcon#*before return 0, iclass 27, count 0 2006.257.06:56:44.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:44.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.06:56:44.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.06:56:44.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.06:56:44.32$vck44/vb=8,4 2006.257.06:56:44.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.06:56:44.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.06:56:44.32#ibcon#ireg 11 cls_cnt 2 2006.257.06:56:44.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:44.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:44.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:44.38#ibcon#enter wrdev, iclass 29, count 2 2006.257.06:56:44.38#ibcon#first serial, iclass 29, count 2 2006.257.06:56:44.38#ibcon#enter sib2, iclass 29, count 2 2006.257.06:56:44.38#ibcon#flushed, iclass 29, count 2 2006.257.06:56:44.38#ibcon#about to write, iclass 29, count 2 2006.257.06:56:44.38#ibcon#wrote, iclass 29, count 2 2006.257.06:56:44.38#ibcon#about to read 3, iclass 29, count 2 2006.257.06:56:44.40#ibcon#read 3, iclass 29, count 2 2006.257.06:56:44.40#ibcon#about to read 4, iclass 29, count 2 2006.257.06:56:44.40#ibcon#read 4, iclass 29, count 2 2006.257.06:56:44.40#ibcon#about to read 5, iclass 29, count 2 2006.257.06:56:44.40#ibcon#read 5, iclass 29, count 2 2006.257.06:56:44.40#ibcon#about to read 6, iclass 29, count 2 2006.257.06:56:44.40#ibcon#read 6, iclass 29, count 2 2006.257.06:56:44.40#ibcon#end of sib2, iclass 29, count 2 2006.257.06:56:44.40#ibcon#*mode == 0, iclass 29, count 2 2006.257.06:56:44.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.06:56:44.40#ibcon#[27=AT08-04\r\n] 2006.257.06:56:44.40#ibcon#*before write, iclass 29, count 2 2006.257.06:56:44.40#ibcon#enter sib2, iclass 29, count 2 2006.257.06:56:44.40#ibcon#flushed, iclass 29, count 2 2006.257.06:56:44.40#ibcon#about to write, iclass 29, count 2 2006.257.06:56:44.40#ibcon#wrote, iclass 29, count 2 2006.257.06:56:44.40#ibcon#about to read 3, iclass 29, count 2 2006.257.06:56:44.43#ibcon#read 3, iclass 29, count 2 2006.257.06:56:44.43#ibcon#about to read 4, iclass 29, count 2 2006.257.06:56:44.43#ibcon#read 4, iclass 29, count 2 2006.257.06:56:44.43#ibcon#about to read 5, iclass 29, count 2 2006.257.06:56:44.43#ibcon#read 5, iclass 29, count 2 2006.257.06:56:44.43#ibcon#about to read 6, iclass 29, count 2 2006.257.06:56:44.43#ibcon#read 6, iclass 29, count 2 2006.257.06:56:44.43#ibcon#end of sib2, iclass 29, count 2 2006.257.06:56:44.43#ibcon#*after write, iclass 29, count 2 2006.257.06:56:44.43#ibcon#*before return 0, iclass 29, count 2 2006.257.06:56:44.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:44.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.06:56:44.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.06:56:44.43#ibcon#ireg 7 cls_cnt 0 2006.257.06:56:44.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:44.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:44.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:44.55#ibcon#enter wrdev, iclass 29, count 0 2006.257.06:56:44.55#ibcon#first serial, iclass 29, count 0 2006.257.06:56:44.55#ibcon#enter sib2, iclass 29, count 0 2006.257.06:56:44.55#ibcon#flushed, iclass 29, count 0 2006.257.06:56:44.55#ibcon#about to write, iclass 29, count 0 2006.257.06:56:44.55#ibcon#wrote, iclass 29, count 0 2006.257.06:56:44.55#ibcon#about to read 3, iclass 29, count 0 2006.257.06:56:44.57#ibcon#read 3, iclass 29, count 0 2006.257.06:56:44.57#ibcon#about to read 4, iclass 29, count 0 2006.257.06:56:44.57#ibcon#read 4, iclass 29, count 0 2006.257.06:56:44.57#ibcon#about to read 5, iclass 29, count 0 2006.257.06:56:44.57#ibcon#read 5, iclass 29, count 0 2006.257.06:56:44.57#ibcon#about to read 6, iclass 29, count 0 2006.257.06:56:44.57#ibcon#read 6, iclass 29, count 0 2006.257.06:56:44.57#ibcon#end of sib2, iclass 29, count 0 2006.257.06:56:44.57#ibcon#*mode == 0, iclass 29, count 0 2006.257.06:56:44.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.06:56:44.57#ibcon#[27=USB\r\n] 2006.257.06:56:44.57#ibcon#*before write, iclass 29, count 0 2006.257.06:56:44.57#ibcon#enter sib2, iclass 29, count 0 2006.257.06:56:44.57#ibcon#flushed, iclass 29, count 0 2006.257.06:56:44.57#ibcon#about to write, iclass 29, count 0 2006.257.06:56:44.57#ibcon#wrote, iclass 29, count 0 2006.257.06:56:44.57#ibcon#about to read 3, iclass 29, count 0 2006.257.06:56:44.60#ibcon#read 3, iclass 29, count 0 2006.257.06:56:44.60#ibcon#about to read 4, iclass 29, count 0 2006.257.06:56:44.60#ibcon#read 4, iclass 29, count 0 2006.257.06:56:44.60#ibcon#about to read 5, iclass 29, count 0 2006.257.06:56:44.60#ibcon#read 5, iclass 29, count 0 2006.257.06:56:44.60#ibcon#about to read 6, iclass 29, count 0 2006.257.06:56:44.60#ibcon#read 6, iclass 29, count 0 2006.257.06:56:44.60#ibcon#end of sib2, iclass 29, count 0 2006.257.06:56:44.60#ibcon#*after write, iclass 29, count 0 2006.257.06:56:44.60#ibcon#*before return 0, iclass 29, count 0 2006.257.06:56:44.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:44.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.06:56:44.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.06:56:44.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.06:56:44.60$vck44/vabw=wide 2006.257.06:56:44.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.06:56:44.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.06:56:44.60#ibcon#ireg 8 cls_cnt 0 2006.257.06:56:44.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:44.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:44.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:44.60#ibcon#enter wrdev, iclass 31, count 0 2006.257.06:56:44.60#ibcon#first serial, iclass 31, count 0 2006.257.06:56:44.60#ibcon#enter sib2, iclass 31, count 0 2006.257.06:56:44.60#ibcon#flushed, iclass 31, count 0 2006.257.06:56:44.60#ibcon#about to write, iclass 31, count 0 2006.257.06:56:44.60#ibcon#wrote, iclass 31, count 0 2006.257.06:56:44.60#ibcon#about to read 3, iclass 31, count 0 2006.257.06:56:44.62#ibcon#read 3, iclass 31, count 0 2006.257.06:56:44.62#ibcon#about to read 4, iclass 31, count 0 2006.257.06:56:44.62#ibcon#read 4, iclass 31, count 0 2006.257.06:56:44.62#ibcon#about to read 5, iclass 31, count 0 2006.257.06:56:44.62#ibcon#read 5, iclass 31, count 0 2006.257.06:56:44.62#ibcon#about to read 6, iclass 31, count 0 2006.257.06:56:44.62#ibcon#read 6, iclass 31, count 0 2006.257.06:56:44.62#ibcon#end of sib2, iclass 31, count 0 2006.257.06:56:44.62#ibcon#*mode == 0, iclass 31, count 0 2006.257.06:56:44.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.06:56:44.62#ibcon#[25=BW32\r\n] 2006.257.06:56:44.62#ibcon#*before write, iclass 31, count 0 2006.257.06:56:44.62#ibcon#enter sib2, iclass 31, count 0 2006.257.06:56:44.62#ibcon#flushed, iclass 31, count 0 2006.257.06:56:44.62#ibcon#about to write, iclass 31, count 0 2006.257.06:56:44.62#ibcon#wrote, iclass 31, count 0 2006.257.06:56:44.62#ibcon#about to read 3, iclass 31, count 0 2006.257.06:56:44.65#ibcon#read 3, iclass 31, count 0 2006.257.06:56:44.65#ibcon#about to read 4, iclass 31, count 0 2006.257.06:56:44.65#ibcon#read 4, iclass 31, count 0 2006.257.06:56:44.65#ibcon#about to read 5, iclass 31, count 0 2006.257.06:56:44.65#ibcon#read 5, iclass 31, count 0 2006.257.06:56:44.65#ibcon#about to read 6, iclass 31, count 0 2006.257.06:56:44.65#ibcon#read 6, iclass 31, count 0 2006.257.06:56:44.65#ibcon#end of sib2, iclass 31, count 0 2006.257.06:56:44.65#ibcon#*after write, iclass 31, count 0 2006.257.06:56:44.65#ibcon#*before return 0, iclass 31, count 0 2006.257.06:56:44.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:44.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.06:56:44.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.06:56:44.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.06:56:44.65$vck44/vbbw=wide 2006.257.06:56:44.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.06:56:44.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.06:56:44.65#ibcon#ireg 8 cls_cnt 0 2006.257.06:56:44.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:56:44.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:56:44.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:56:44.72#ibcon#enter wrdev, iclass 33, count 0 2006.257.06:56:44.72#ibcon#first serial, iclass 33, count 0 2006.257.06:56:44.72#ibcon#enter sib2, iclass 33, count 0 2006.257.06:56:44.72#ibcon#flushed, iclass 33, count 0 2006.257.06:56:44.72#ibcon#about to write, iclass 33, count 0 2006.257.06:56:44.72#ibcon#wrote, iclass 33, count 0 2006.257.06:56:44.72#ibcon#about to read 3, iclass 33, count 0 2006.257.06:56:44.74#ibcon#read 3, iclass 33, count 0 2006.257.06:56:44.74#ibcon#about to read 4, iclass 33, count 0 2006.257.06:56:44.74#ibcon#read 4, iclass 33, count 0 2006.257.06:56:44.74#ibcon#about to read 5, iclass 33, count 0 2006.257.06:56:44.74#ibcon#read 5, iclass 33, count 0 2006.257.06:56:44.74#ibcon#about to read 6, iclass 33, count 0 2006.257.06:56:44.74#ibcon#read 6, iclass 33, count 0 2006.257.06:56:44.74#ibcon#end of sib2, iclass 33, count 0 2006.257.06:56:44.74#ibcon#*mode == 0, iclass 33, count 0 2006.257.06:56:44.74#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.06:56:44.74#ibcon#[27=BW32\r\n] 2006.257.06:56:44.74#ibcon#*before write, iclass 33, count 0 2006.257.06:56:44.74#ibcon#enter sib2, iclass 33, count 0 2006.257.06:56:44.74#ibcon#flushed, iclass 33, count 0 2006.257.06:56:44.74#ibcon#about to write, iclass 33, count 0 2006.257.06:56:44.74#ibcon#wrote, iclass 33, count 0 2006.257.06:56:44.74#ibcon#about to read 3, iclass 33, count 0 2006.257.06:56:44.77#ibcon#read 3, iclass 33, count 0 2006.257.06:56:44.77#ibcon#about to read 4, iclass 33, count 0 2006.257.06:56:44.77#ibcon#read 4, iclass 33, count 0 2006.257.06:56:44.77#ibcon#about to read 5, iclass 33, count 0 2006.257.06:56:44.77#ibcon#read 5, iclass 33, count 0 2006.257.06:56:44.77#ibcon#about to read 6, iclass 33, count 0 2006.257.06:56:44.77#ibcon#read 6, iclass 33, count 0 2006.257.06:56:44.77#ibcon#end of sib2, iclass 33, count 0 2006.257.06:56:44.77#ibcon#*after write, iclass 33, count 0 2006.257.06:56:44.77#ibcon#*before return 0, iclass 33, count 0 2006.257.06:56:44.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:56:44.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.06:56:44.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.06:56:44.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.06:56:44.77$setupk4/ifdk4 2006.257.06:56:44.77$ifdk4/lo= 2006.257.06:56:44.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:56:44.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:56:44.77$ifdk4/patch= 2006.257.06:56:44.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:56:44.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:56:44.77$setupk4/!*+20s 2006.257.06:56:49.75#abcon#<5=/16 1.3 3.9 20.78 891012.3\r\n> 2006.257.06:56:49.77#abcon#{5=INTERFACE CLEAR} 2006.257.06:56:49.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:56:59.28$setupk4/"tpicd 2006.257.06:56:59.28$setupk4/echo=off 2006.257.06:56:59.28$setupk4/xlog=off 2006.257.06:56:59.28:!2006.257.06:57:44 2006.257.06:57:27.14#trakl#Source acquired 2006.257.06:57:28.14#flagr#flagr/antenna,acquired 2006.257.06:57:44.00:preob 2006.257.06:57:44.14/onsource/TRACKING 2006.257.06:57:44.14:!2006.257.06:57:54 2006.257.06:57:54.00:"tape 2006.257.06:57:54.00:"st=record 2006.257.06:57:54.00:data_valid=on 2006.257.06:57:54.00:midob 2006.257.06:57:55.14/onsource/TRACKING 2006.257.06:57:55.14/wx/20.79,1012.3,89 2006.257.06:57:55.32/cable/+6.4776E-03 2006.257.06:57:56.41/va/01,08,usb,yes,36,39 2006.257.06:57:56.41/va/02,07,usb,yes,39,40 2006.257.06:57:56.41/va/03,08,usb,yes,35,37 2006.257.06:57:56.41/va/04,07,usb,yes,40,43 2006.257.06:57:56.41/va/05,04,usb,yes,36,37 2006.257.06:57:56.41/va/06,04,usb,yes,40,40 2006.257.06:57:56.41/va/07,04,usb,yes,41,42 2006.257.06:57:56.41/va/08,04,usb,yes,35,42 2006.257.06:57:56.64/valo/01,524.99,yes,locked 2006.257.06:57:56.64/valo/02,534.99,yes,locked 2006.257.06:57:56.64/valo/03,564.99,yes,locked 2006.257.06:57:56.64/valo/04,624.99,yes,locked 2006.257.06:57:56.64/valo/05,734.99,yes,locked 2006.257.06:57:56.64/valo/06,814.99,yes,locked 2006.257.06:57:56.64/valo/07,864.99,yes,locked 2006.257.06:57:56.64/valo/08,884.99,yes,locked 2006.257.06:57:57.73/vb/01,04,usb,yes,34,31 2006.257.06:57:57.73/vb/02,05,usb,yes,32,32 2006.257.06:57:57.73/vb/03,04,usb,yes,33,36 2006.257.06:57:57.73/vb/04,05,usb,yes,33,32 2006.257.06:57:57.73/vb/05,04,usb,yes,30,32 2006.257.06:57:57.73/vb/06,04,usb,yes,35,31 2006.257.06:57:57.73/vb/07,04,usb,yes,34,34 2006.257.06:57:57.73/vb/08,04,usb,yes,32,35 2006.257.06:57:57.96/vblo/01,629.99,yes,locked 2006.257.06:57:57.96/vblo/02,634.99,yes,locked 2006.257.06:57:57.96/vblo/03,649.99,yes,locked 2006.257.06:57:57.96/vblo/04,679.99,yes,locked 2006.257.06:57:57.96/vblo/05,709.99,yes,locked 2006.257.06:57:57.96/vblo/06,719.99,yes,locked 2006.257.06:57:57.96/vblo/07,734.99,yes,locked 2006.257.06:57:57.96/vblo/08,744.99,yes,locked 2006.257.06:57:58.11/vabw/8 2006.257.06:57:58.26/vbbw/8 2006.257.06:57:58.35/xfe/off,on,16.7 2006.257.06:57:58.72/ifatt/23,28,28,28 2006.257.06:57:59.07/fmout-gps/S +4.50E-07 2006.257.06:57:59.11:!2006.257.06:58:34 2006.257.06:58:34.00:data_valid=off 2006.257.06:58:34.00:"et 2006.257.06:58:34.00:!+3s 2006.257.06:58:37.03:"tape 2006.257.06:58:37.03:postob 2006.257.06:58:37.24/cable/+6.4777E-03 2006.257.06:58:37.24/wx/20.80,1012.3,89 2006.257.06:58:37.30/fmout-gps/S +4.49E-07 2006.257.06:58:37.30:scan_name=257-0703,jd0609,90 2006.257.06:58:37.30:source=3c274,123049.42,122328.0,2000.0,cw 2006.257.06:58:39.13#flagr#flagr/antenna,new-source 2006.257.06:58:39.13:checkk5 2006.257.06:58:39.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.06:58:39.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.06:58:40.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.06:58:40.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.06:58:41.15/chk_obsdata//k5ts1/T2570657??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:58:41.56/chk_obsdata//k5ts2/T2570657??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:58:41.99/chk_obsdata//k5ts3/T2570657??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:58:42.37/chk_obsdata//k5ts4/T2570657??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.06:58:43.09/k5log//k5ts1_log_newline 2006.257.06:58:43.81/k5log//k5ts2_log_newline 2006.257.06:58:44.56/k5log//k5ts3_log_newline 2006.257.06:58:45.30/k5log//k5ts4_log_newline 2006.257.06:58:45.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.06:58:45.32:setupk4=1 2006.257.06:58:45.32$setupk4/echo=on 2006.257.06:58:45.32$setupk4/pcalon 2006.257.06:58:45.32$pcalon/"no phase cal control is implemented here 2006.257.06:58:45.32$setupk4/"tpicd=stop 2006.257.06:58:45.32$setupk4/"rec=synch_on 2006.257.06:58:45.32$setupk4/"rec_mode=128 2006.257.06:58:45.32$setupk4/!* 2006.257.06:58:45.32$setupk4/recpk4 2006.257.06:58:45.32$recpk4/recpatch= 2006.257.06:58:45.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.06:58:45.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.06:58:45.32$setupk4/vck44 2006.257.06:58:45.32$vck44/valo=1,524.99 2006.257.06:58:45.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.06:58:45.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.06:58:45.32#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:45.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:45.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:45.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:45.32#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:58:45.32#ibcon#first serial, iclass 14, count 0 2006.257.06:58:45.32#ibcon#enter sib2, iclass 14, count 0 2006.257.06:58:45.32#ibcon#flushed, iclass 14, count 0 2006.257.06:58:45.32#ibcon#about to write, iclass 14, count 0 2006.257.06:58:45.32#ibcon#wrote, iclass 14, count 0 2006.257.06:58:45.32#ibcon#about to read 3, iclass 14, count 0 2006.257.06:58:45.34#ibcon#read 3, iclass 14, count 0 2006.257.06:58:45.34#ibcon#about to read 4, iclass 14, count 0 2006.257.06:58:45.34#ibcon#read 4, iclass 14, count 0 2006.257.06:58:45.34#ibcon#about to read 5, iclass 14, count 0 2006.257.06:58:45.34#ibcon#read 5, iclass 14, count 0 2006.257.06:58:45.34#ibcon#about to read 6, iclass 14, count 0 2006.257.06:58:45.34#ibcon#read 6, iclass 14, count 0 2006.257.06:58:45.34#ibcon#end of sib2, iclass 14, count 0 2006.257.06:58:45.34#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:58:45.34#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:58:45.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.06:58:45.34#ibcon#*before write, iclass 14, count 0 2006.257.06:58:45.34#ibcon#enter sib2, iclass 14, count 0 2006.257.06:58:45.34#ibcon#flushed, iclass 14, count 0 2006.257.06:58:45.34#ibcon#about to write, iclass 14, count 0 2006.257.06:58:45.34#ibcon#wrote, iclass 14, count 0 2006.257.06:58:45.34#ibcon#about to read 3, iclass 14, count 0 2006.257.06:58:45.39#ibcon#read 3, iclass 14, count 0 2006.257.06:58:45.39#ibcon#about to read 4, iclass 14, count 0 2006.257.06:58:45.39#ibcon#read 4, iclass 14, count 0 2006.257.06:58:45.39#ibcon#about to read 5, iclass 14, count 0 2006.257.06:58:45.39#ibcon#read 5, iclass 14, count 0 2006.257.06:58:45.39#ibcon#about to read 6, iclass 14, count 0 2006.257.06:58:45.39#ibcon#read 6, iclass 14, count 0 2006.257.06:58:45.39#ibcon#end of sib2, iclass 14, count 0 2006.257.06:58:45.39#ibcon#*after write, iclass 14, count 0 2006.257.06:58:45.39#ibcon#*before return 0, iclass 14, count 0 2006.257.06:58:45.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:45.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:45.39#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:58:45.39#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:58:45.39$vck44/va=1,8 2006.257.06:58:45.39#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.06:58:45.39#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.06:58:45.39#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:45.39#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:45.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:45.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:45.39#ibcon#enter wrdev, iclass 16, count 2 2006.257.06:58:45.39#ibcon#first serial, iclass 16, count 2 2006.257.06:58:45.39#ibcon#enter sib2, iclass 16, count 2 2006.257.06:58:45.39#ibcon#flushed, iclass 16, count 2 2006.257.06:58:45.39#ibcon#about to write, iclass 16, count 2 2006.257.06:58:45.39#ibcon#wrote, iclass 16, count 2 2006.257.06:58:45.39#ibcon#about to read 3, iclass 16, count 2 2006.257.06:58:45.41#ibcon#read 3, iclass 16, count 2 2006.257.06:58:45.41#ibcon#about to read 4, iclass 16, count 2 2006.257.06:58:45.41#ibcon#read 4, iclass 16, count 2 2006.257.06:58:45.41#ibcon#about to read 5, iclass 16, count 2 2006.257.06:58:45.41#ibcon#read 5, iclass 16, count 2 2006.257.06:58:45.41#ibcon#about to read 6, iclass 16, count 2 2006.257.06:58:45.41#ibcon#read 6, iclass 16, count 2 2006.257.06:58:45.41#ibcon#end of sib2, iclass 16, count 2 2006.257.06:58:45.41#ibcon#*mode == 0, iclass 16, count 2 2006.257.06:58:45.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.06:58:45.41#ibcon#[25=AT01-08\r\n] 2006.257.06:58:45.41#ibcon#*before write, iclass 16, count 2 2006.257.06:58:45.41#ibcon#enter sib2, iclass 16, count 2 2006.257.06:58:45.41#ibcon#flushed, iclass 16, count 2 2006.257.06:58:45.41#ibcon#about to write, iclass 16, count 2 2006.257.06:58:45.41#ibcon#wrote, iclass 16, count 2 2006.257.06:58:45.41#ibcon#about to read 3, iclass 16, count 2 2006.257.06:58:45.44#ibcon#read 3, iclass 16, count 2 2006.257.06:58:45.44#ibcon#about to read 4, iclass 16, count 2 2006.257.06:58:45.44#ibcon#read 4, iclass 16, count 2 2006.257.06:58:45.44#ibcon#about to read 5, iclass 16, count 2 2006.257.06:58:45.44#ibcon#read 5, iclass 16, count 2 2006.257.06:58:45.44#ibcon#about to read 6, iclass 16, count 2 2006.257.06:58:45.44#ibcon#read 6, iclass 16, count 2 2006.257.06:58:45.44#ibcon#end of sib2, iclass 16, count 2 2006.257.06:58:45.44#ibcon#*after write, iclass 16, count 2 2006.257.06:58:45.44#ibcon#*before return 0, iclass 16, count 2 2006.257.06:58:45.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:45.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:45.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.06:58:45.44#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:45.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:45.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:45.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:45.56#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:58:45.56#ibcon#first serial, iclass 16, count 0 2006.257.06:58:45.56#ibcon#enter sib2, iclass 16, count 0 2006.257.06:58:45.56#ibcon#flushed, iclass 16, count 0 2006.257.06:58:45.56#ibcon#about to write, iclass 16, count 0 2006.257.06:58:45.56#ibcon#wrote, iclass 16, count 0 2006.257.06:58:45.56#ibcon#about to read 3, iclass 16, count 0 2006.257.06:58:45.58#ibcon#read 3, iclass 16, count 0 2006.257.06:58:45.58#ibcon#about to read 4, iclass 16, count 0 2006.257.06:58:45.58#ibcon#read 4, iclass 16, count 0 2006.257.06:58:45.58#ibcon#about to read 5, iclass 16, count 0 2006.257.06:58:45.58#ibcon#read 5, iclass 16, count 0 2006.257.06:58:45.58#ibcon#about to read 6, iclass 16, count 0 2006.257.06:58:45.58#ibcon#read 6, iclass 16, count 0 2006.257.06:58:45.58#ibcon#end of sib2, iclass 16, count 0 2006.257.06:58:45.58#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:58:45.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:58:45.58#ibcon#[25=USB\r\n] 2006.257.06:58:45.58#ibcon#*before write, iclass 16, count 0 2006.257.06:58:45.58#ibcon#enter sib2, iclass 16, count 0 2006.257.06:58:45.58#ibcon#flushed, iclass 16, count 0 2006.257.06:58:45.58#ibcon#about to write, iclass 16, count 0 2006.257.06:58:45.58#ibcon#wrote, iclass 16, count 0 2006.257.06:58:45.58#ibcon#about to read 3, iclass 16, count 0 2006.257.06:58:45.61#ibcon#read 3, iclass 16, count 0 2006.257.06:58:45.61#ibcon#about to read 4, iclass 16, count 0 2006.257.06:58:45.61#ibcon#read 4, iclass 16, count 0 2006.257.06:58:45.61#ibcon#about to read 5, iclass 16, count 0 2006.257.06:58:45.61#ibcon#read 5, iclass 16, count 0 2006.257.06:58:45.61#ibcon#about to read 6, iclass 16, count 0 2006.257.06:58:45.61#ibcon#read 6, iclass 16, count 0 2006.257.06:58:45.61#ibcon#end of sib2, iclass 16, count 0 2006.257.06:58:45.61#ibcon#*after write, iclass 16, count 0 2006.257.06:58:45.61#ibcon#*before return 0, iclass 16, count 0 2006.257.06:58:45.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:45.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:45.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:58:45.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:58:45.61$vck44/valo=2,534.99 2006.257.06:58:45.61#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.06:58:45.61#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.06:58:45.61#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:45.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:45.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:45.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:45.61#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:58:45.61#ibcon#first serial, iclass 18, count 0 2006.257.06:58:45.61#ibcon#enter sib2, iclass 18, count 0 2006.257.06:58:45.61#ibcon#flushed, iclass 18, count 0 2006.257.06:58:45.61#ibcon#about to write, iclass 18, count 0 2006.257.06:58:45.61#ibcon#wrote, iclass 18, count 0 2006.257.06:58:45.61#ibcon#about to read 3, iclass 18, count 0 2006.257.06:58:45.63#ibcon#read 3, iclass 18, count 0 2006.257.06:58:45.63#ibcon#about to read 4, iclass 18, count 0 2006.257.06:58:45.63#ibcon#read 4, iclass 18, count 0 2006.257.06:58:45.63#ibcon#about to read 5, iclass 18, count 0 2006.257.06:58:45.63#ibcon#read 5, iclass 18, count 0 2006.257.06:58:45.63#ibcon#about to read 6, iclass 18, count 0 2006.257.06:58:45.63#ibcon#read 6, iclass 18, count 0 2006.257.06:58:45.63#ibcon#end of sib2, iclass 18, count 0 2006.257.06:58:45.63#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:58:45.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:58:45.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.06:58:45.63#ibcon#*before write, iclass 18, count 0 2006.257.06:58:45.63#ibcon#enter sib2, iclass 18, count 0 2006.257.06:58:45.63#ibcon#flushed, iclass 18, count 0 2006.257.06:58:45.63#ibcon#about to write, iclass 18, count 0 2006.257.06:58:45.63#ibcon#wrote, iclass 18, count 0 2006.257.06:58:45.63#ibcon#about to read 3, iclass 18, count 0 2006.257.06:58:45.67#ibcon#read 3, iclass 18, count 0 2006.257.06:58:45.67#ibcon#about to read 4, iclass 18, count 0 2006.257.06:58:45.67#ibcon#read 4, iclass 18, count 0 2006.257.06:58:45.67#ibcon#about to read 5, iclass 18, count 0 2006.257.06:58:45.67#ibcon#read 5, iclass 18, count 0 2006.257.06:58:45.67#ibcon#about to read 6, iclass 18, count 0 2006.257.06:58:45.67#ibcon#read 6, iclass 18, count 0 2006.257.06:58:45.67#ibcon#end of sib2, iclass 18, count 0 2006.257.06:58:45.67#ibcon#*after write, iclass 18, count 0 2006.257.06:58:45.67#ibcon#*before return 0, iclass 18, count 0 2006.257.06:58:45.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:45.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:45.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:58:45.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:58:45.67$vck44/va=2,7 2006.257.06:58:45.67#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.06:58:45.67#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.06:58:45.67#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:45.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:45.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:45.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:45.73#ibcon#enter wrdev, iclass 20, count 2 2006.257.06:58:45.73#ibcon#first serial, iclass 20, count 2 2006.257.06:58:45.73#ibcon#enter sib2, iclass 20, count 2 2006.257.06:58:45.73#ibcon#flushed, iclass 20, count 2 2006.257.06:58:45.73#ibcon#about to write, iclass 20, count 2 2006.257.06:58:45.73#ibcon#wrote, iclass 20, count 2 2006.257.06:58:45.73#ibcon#about to read 3, iclass 20, count 2 2006.257.06:58:45.75#ibcon#read 3, iclass 20, count 2 2006.257.06:58:45.75#ibcon#about to read 4, iclass 20, count 2 2006.257.06:58:45.75#ibcon#read 4, iclass 20, count 2 2006.257.06:58:45.75#ibcon#about to read 5, iclass 20, count 2 2006.257.06:58:45.75#ibcon#read 5, iclass 20, count 2 2006.257.06:58:45.75#ibcon#about to read 6, iclass 20, count 2 2006.257.06:58:45.75#ibcon#read 6, iclass 20, count 2 2006.257.06:58:45.75#ibcon#end of sib2, iclass 20, count 2 2006.257.06:58:45.75#ibcon#*mode == 0, iclass 20, count 2 2006.257.06:58:45.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.06:58:45.75#ibcon#[25=AT02-07\r\n] 2006.257.06:58:45.75#ibcon#*before write, iclass 20, count 2 2006.257.06:58:45.75#ibcon#enter sib2, iclass 20, count 2 2006.257.06:58:45.75#ibcon#flushed, iclass 20, count 2 2006.257.06:58:45.75#ibcon#about to write, iclass 20, count 2 2006.257.06:58:45.75#ibcon#wrote, iclass 20, count 2 2006.257.06:58:45.75#ibcon#about to read 3, iclass 20, count 2 2006.257.06:58:45.78#ibcon#read 3, iclass 20, count 2 2006.257.06:58:45.78#ibcon#about to read 4, iclass 20, count 2 2006.257.06:58:45.78#ibcon#read 4, iclass 20, count 2 2006.257.06:58:45.78#ibcon#about to read 5, iclass 20, count 2 2006.257.06:58:45.78#ibcon#read 5, iclass 20, count 2 2006.257.06:58:45.78#ibcon#about to read 6, iclass 20, count 2 2006.257.06:58:45.78#ibcon#read 6, iclass 20, count 2 2006.257.06:58:45.78#ibcon#end of sib2, iclass 20, count 2 2006.257.06:58:45.78#ibcon#*after write, iclass 20, count 2 2006.257.06:58:45.78#ibcon#*before return 0, iclass 20, count 2 2006.257.06:58:45.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:45.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:45.78#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.06:58:45.78#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:45.78#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:45.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:45.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:45.90#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:58:45.90#ibcon#first serial, iclass 20, count 0 2006.257.06:58:45.90#ibcon#enter sib2, iclass 20, count 0 2006.257.06:58:45.90#ibcon#flushed, iclass 20, count 0 2006.257.06:58:45.90#ibcon#about to write, iclass 20, count 0 2006.257.06:58:45.90#ibcon#wrote, iclass 20, count 0 2006.257.06:58:45.90#ibcon#about to read 3, iclass 20, count 0 2006.257.06:58:45.92#ibcon#read 3, iclass 20, count 0 2006.257.06:58:45.92#ibcon#about to read 4, iclass 20, count 0 2006.257.06:58:45.92#ibcon#read 4, iclass 20, count 0 2006.257.06:58:45.92#ibcon#about to read 5, iclass 20, count 0 2006.257.06:58:45.92#ibcon#read 5, iclass 20, count 0 2006.257.06:58:45.92#ibcon#about to read 6, iclass 20, count 0 2006.257.06:58:45.92#ibcon#read 6, iclass 20, count 0 2006.257.06:58:45.92#ibcon#end of sib2, iclass 20, count 0 2006.257.06:58:45.92#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:58:45.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:58:45.92#ibcon#[25=USB\r\n] 2006.257.06:58:45.92#ibcon#*before write, iclass 20, count 0 2006.257.06:58:45.92#ibcon#enter sib2, iclass 20, count 0 2006.257.06:58:45.92#ibcon#flushed, iclass 20, count 0 2006.257.06:58:45.92#ibcon#about to write, iclass 20, count 0 2006.257.06:58:45.92#ibcon#wrote, iclass 20, count 0 2006.257.06:58:45.92#ibcon#about to read 3, iclass 20, count 0 2006.257.06:58:45.95#ibcon#read 3, iclass 20, count 0 2006.257.06:58:45.95#ibcon#about to read 4, iclass 20, count 0 2006.257.06:58:45.95#ibcon#read 4, iclass 20, count 0 2006.257.06:58:45.95#ibcon#about to read 5, iclass 20, count 0 2006.257.06:58:45.95#ibcon#read 5, iclass 20, count 0 2006.257.06:58:45.95#ibcon#about to read 6, iclass 20, count 0 2006.257.06:58:45.95#ibcon#read 6, iclass 20, count 0 2006.257.06:58:45.95#ibcon#end of sib2, iclass 20, count 0 2006.257.06:58:45.95#ibcon#*after write, iclass 20, count 0 2006.257.06:58:45.95#ibcon#*before return 0, iclass 20, count 0 2006.257.06:58:45.95#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:45.95#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:45.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:58:45.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:58:45.95$vck44/valo=3,564.99 2006.257.06:58:45.95#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.06:58:45.95#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.06:58:45.95#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:45.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:45.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:45.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:45.95#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:58:45.95#ibcon#first serial, iclass 22, count 0 2006.257.06:58:45.95#ibcon#enter sib2, iclass 22, count 0 2006.257.06:58:45.95#ibcon#flushed, iclass 22, count 0 2006.257.06:58:45.95#ibcon#about to write, iclass 22, count 0 2006.257.06:58:45.95#ibcon#wrote, iclass 22, count 0 2006.257.06:58:45.95#ibcon#about to read 3, iclass 22, count 0 2006.257.06:58:45.97#ibcon#read 3, iclass 22, count 0 2006.257.06:58:45.97#ibcon#about to read 4, iclass 22, count 0 2006.257.06:58:45.97#ibcon#read 4, iclass 22, count 0 2006.257.06:58:45.97#ibcon#about to read 5, iclass 22, count 0 2006.257.06:58:45.97#ibcon#read 5, iclass 22, count 0 2006.257.06:58:45.97#ibcon#about to read 6, iclass 22, count 0 2006.257.06:58:45.97#ibcon#read 6, iclass 22, count 0 2006.257.06:58:45.97#ibcon#end of sib2, iclass 22, count 0 2006.257.06:58:45.97#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:58:45.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:58:45.97#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.06:58:45.97#ibcon#*before write, iclass 22, count 0 2006.257.06:58:45.97#ibcon#enter sib2, iclass 22, count 0 2006.257.06:58:45.97#ibcon#flushed, iclass 22, count 0 2006.257.06:58:45.97#ibcon#about to write, iclass 22, count 0 2006.257.06:58:45.97#ibcon#wrote, iclass 22, count 0 2006.257.06:58:45.97#ibcon#about to read 3, iclass 22, count 0 2006.257.06:58:46.01#ibcon#read 3, iclass 22, count 0 2006.257.06:58:46.01#ibcon#about to read 4, iclass 22, count 0 2006.257.06:58:46.01#ibcon#read 4, iclass 22, count 0 2006.257.06:58:46.01#ibcon#about to read 5, iclass 22, count 0 2006.257.06:58:46.01#ibcon#read 5, iclass 22, count 0 2006.257.06:58:46.01#ibcon#about to read 6, iclass 22, count 0 2006.257.06:58:46.01#ibcon#read 6, iclass 22, count 0 2006.257.06:58:46.01#ibcon#end of sib2, iclass 22, count 0 2006.257.06:58:46.01#ibcon#*after write, iclass 22, count 0 2006.257.06:58:46.01#ibcon#*before return 0, iclass 22, count 0 2006.257.06:58:46.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:46.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:46.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:58:46.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:58:46.01$vck44/va=3,8 2006.257.06:58:46.01#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.06:58:46.01#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.06:58:46.01#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:46.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:46.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:46.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:46.07#ibcon#enter wrdev, iclass 24, count 2 2006.257.06:58:46.07#ibcon#first serial, iclass 24, count 2 2006.257.06:58:46.07#ibcon#enter sib2, iclass 24, count 2 2006.257.06:58:46.07#ibcon#flushed, iclass 24, count 2 2006.257.06:58:46.07#ibcon#about to write, iclass 24, count 2 2006.257.06:58:46.07#ibcon#wrote, iclass 24, count 2 2006.257.06:58:46.07#ibcon#about to read 3, iclass 24, count 2 2006.257.06:58:46.09#ibcon#read 3, iclass 24, count 2 2006.257.06:58:46.09#ibcon#about to read 4, iclass 24, count 2 2006.257.06:58:46.09#ibcon#read 4, iclass 24, count 2 2006.257.06:58:46.09#ibcon#about to read 5, iclass 24, count 2 2006.257.06:58:46.09#ibcon#read 5, iclass 24, count 2 2006.257.06:58:46.09#ibcon#about to read 6, iclass 24, count 2 2006.257.06:58:46.09#ibcon#read 6, iclass 24, count 2 2006.257.06:58:46.09#ibcon#end of sib2, iclass 24, count 2 2006.257.06:58:46.09#ibcon#*mode == 0, iclass 24, count 2 2006.257.06:58:46.09#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.06:58:46.09#ibcon#[25=AT03-08\r\n] 2006.257.06:58:46.09#ibcon#*before write, iclass 24, count 2 2006.257.06:58:46.09#ibcon#enter sib2, iclass 24, count 2 2006.257.06:58:46.09#ibcon#flushed, iclass 24, count 2 2006.257.06:58:46.09#ibcon#about to write, iclass 24, count 2 2006.257.06:58:46.09#ibcon#wrote, iclass 24, count 2 2006.257.06:58:46.09#ibcon#about to read 3, iclass 24, count 2 2006.257.06:58:46.12#ibcon#read 3, iclass 24, count 2 2006.257.06:58:46.12#ibcon#about to read 4, iclass 24, count 2 2006.257.06:58:46.12#ibcon#read 4, iclass 24, count 2 2006.257.06:58:46.12#ibcon#about to read 5, iclass 24, count 2 2006.257.06:58:46.12#ibcon#read 5, iclass 24, count 2 2006.257.06:58:46.12#ibcon#about to read 6, iclass 24, count 2 2006.257.06:58:46.12#ibcon#read 6, iclass 24, count 2 2006.257.06:58:46.12#ibcon#end of sib2, iclass 24, count 2 2006.257.06:58:46.12#ibcon#*after write, iclass 24, count 2 2006.257.06:58:46.12#ibcon#*before return 0, iclass 24, count 2 2006.257.06:58:46.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:46.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:46.12#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.06:58:46.12#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:46.12#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:46.24#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:46.24#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:46.24#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:58:46.24#ibcon#first serial, iclass 24, count 0 2006.257.06:58:46.24#ibcon#enter sib2, iclass 24, count 0 2006.257.06:58:46.24#ibcon#flushed, iclass 24, count 0 2006.257.06:58:46.24#ibcon#about to write, iclass 24, count 0 2006.257.06:58:46.24#ibcon#wrote, iclass 24, count 0 2006.257.06:58:46.24#ibcon#about to read 3, iclass 24, count 0 2006.257.06:58:46.26#ibcon#read 3, iclass 24, count 0 2006.257.06:58:46.26#ibcon#about to read 4, iclass 24, count 0 2006.257.06:58:46.26#ibcon#read 4, iclass 24, count 0 2006.257.06:58:46.26#ibcon#about to read 5, iclass 24, count 0 2006.257.06:58:46.26#ibcon#read 5, iclass 24, count 0 2006.257.06:58:46.26#ibcon#about to read 6, iclass 24, count 0 2006.257.06:58:46.26#ibcon#read 6, iclass 24, count 0 2006.257.06:58:46.26#ibcon#end of sib2, iclass 24, count 0 2006.257.06:58:46.26#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:58:46.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:58:46.26#ibcon#[25=USB\r\n] 2006.257.06:58:46.26#ibcon#*before write, iclass 24, count 0 2006.257.06:58:46.26#ibcon#enter sib2, iclass 24, count 0 2006.257.06:58:46.26#ibcon#flushed, iclass 24, count 0 2006.257.06:58:46.26#ibcon#about to write, iclass 24, count 0 2006.257.06:58:46.26#ibcon#wrote, iclass 24, count 0 2006.257.06:58:46.26#ibcon#about to read 3, iclass 24, count 0 2006.257.06:58:46.29#ibcon#read 3, iclass 24, count 0 2006.257.06:58:46.29#ibcon#about to read 4, iclass 24, count 0 2006.257.06:58:46.29#ibcon#read 4, iclass 24, count 0 2006.257.06:58:46.29#ibcon#about to read 5, iclass 24, count 0 2006.257.06:58:46.29#ibcon#read 5, iclass 24, count 0 2006.257.06:58:46.29#ibcon#about to read 6, iclass 24, count 0 2006.257.06:58:46.29#ibcon#read 6, iclass 24, count 0 2006.257.06:58:46.29#ibcon#end of sib2, iclass 24, count 0 2006.257.06:58:46.29#ibcon#*after write, iclass 24, count 0 2006.257.06:58:46.29#ibcon#*before return 0, iclass 24, count 0 2006.257.06:58:46.29#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:46.29#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:46.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:58:46.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:58:46.29$vck44/valo=4,624.99 2006.257.06:58:46.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.06:58:46.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.06:58:46.29#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:46.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:46.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:46.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:46.29#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:58:46.29#ibcon#first serial, iclass 26, count 0 2006.257.06:58:46.29#ibcon#enter sib2, iclass 26, count 0 2006.257.06:58:46.29#ibcon#flushed, iclass 26, count 0 2006.257.06:58:46.29#ibcon#about to write, iclass 26, count 0 2006.257.06:58:46.29#ibcon#wrote, iclass 26, count 0 2006.257.06:58:46.29#ibcon#about to read 3, iclass 26, count 0 2006.257.06:58:46.31#ibcon#read 3, iclass 26, count 0 2006.257.06:58:46.31#ibcon#about to read 4, iclass 26, count 0 2006.257.06:58:46.31#ibcon#read 4, iclass 26, count 0 2006.257.06:58:46.31#ibcon#about to read 5, iclass 26, count 0 2006.257.06:58:46.31#ibcon#read 5, iclass 26, count 0 2006.257.06:58:46.31#ibcon#about to read 6, iclass 26, count 0 2006.257.06:58:46.31#ibcon#read 6, iclass 26, count 0 2006.257.06:58:46.31#ibcon#end of sib2, iclass 26, count 0 2006.257.06:58:46.31#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:58:46.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:58:46.31#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.06:58:46.31#ibcon#*before write, iclass 26, count 0 2006.257.06:58:46.31#ibcon#enter sib2, iclass 26, count 0 2006.257.06:58:46.31#ibcon#flushed, iclass 26, count 0 2006.257.06:58:46.31#ibcon#about to write, iclass 26, count 0 2006.257.06:58:46.31#ibcon#wrote, iclass 26, count 0 2006.257.06:58:46.31#ibcon#about to read 3, iclass 26, count 0 2006.257.06:58:46.35#ibcon#read 3, iclass 26, count 0 2006.257.06:58:46.35#ibcon#about to read 4, iclass 26, count 0 2006.257.06:58:46.35#ibcon#read 4, iclass 26, count 0 2006.257.06:58:46.35#ibcon#about to read 5, iclass 26, count 0 2006.257.06:58:46.35#ibcon#read 5, iclass 26, count 0 2006.257.06:58:46.35#ibcon#about to read 6, iclass 26, count 0 2006.257.06:58:46.35#ibcon#read 6, iclass 26, count 0 2006.257.06:58:46.35#ibcon#end of sib2, iclass 26, count 0 2006.257.06:58:46.35#ibcon#*after write, iclass 26, count 0 2006.257.06:58:46.35#ibcon#*before return 0, iclass 26, count 0 2006.257.06:58:46.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:46.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:46.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:58:46.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:58:46.35$vck44/va=4,7 2006.257.06:58:46.35#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.06:58:46.35#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.06:58:46.35#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:46.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:46.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:46.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:46.41#ibcon#enter wrdev, iclass 28, count 2 2006.257.06:58:46.41#ibcon#first serial, iclass 28, count 2 2006.257.06:58:46.41#ibcon#enter sib2, iclass 28, count 2 2006.257.06:58:46.41#ibcon#flushed, iclass 28, count 2 2006.257.06:58:46.41#ibcon#about to write, iclass 28, count 2 2006.257.06:58:46.41#ibcon#wrote, iclass 28, count 2 2006.257.06:58:46.41#ibcon#about to read 3, iclass 28, count 2 2006.257.06:58:46.43#ibcon#read 3, iclass 28, count 2 2006.257.06:58:46.43#ibcon#about to read 4, iclass 28, count 2 2006.257.06:58:46.43#ibcon#read 4, iclass 28, count 2 2006.257.06:58:46.43#ibcon#about to read 5, iclass 28, count 2 2006.257.06:58:46.43#ibcon#read 5, iclass 28, count 2 2006.257.06:58:46.43#ibcon#about to read 6, iclass 28, count 2 2006.257.06:58:46.43#ibcon#read 6, iclass 28, count 2 2006.257.06:58:46.43#ibcon#end of sib2, iclass 28, count 2 2006.257.06:58:46.43#ibcon#*mode == 0, iclass 28, count 2 2006.257.06:58:46.43#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.06:58:46.43#ibcon#[25=AT04-07\r\n] 2006.257.06:58:46.43#ibcon#*before write, iclass 28, count 2 2006.257.06:58:46.43#ibcon#enter sib2, iclass 28, count 2 2006.257.06:58:46.43#ibcon#flushed, iclass 28, count 2 2006.257.06:58:46.43#ibcon#about to write, iclass 28, count 2 2006.257.06:58:46.43#ibcon#wrote, iclass 28, count 2 2006.257.06:58:46.43#ibcon#about to read 3, iclass 28, count 2 2006.257.06:58:46.46#ibcon#read 3, iclass 28, count 2 2006.257.06:58:46.46#ibcon#about to read 4, iclass 28, count 2 2006.257.06:58:46.46#ibcon#read 4, iclass 28, count 2 2006.257.06:58:46.46#ibcon#about to read 5, iclass 28, count 2 2006.257.06:58:46.46#ibcon#read 5, iclass 28, count 2 2006.257.06:58:46.46#ibcon#about to read 6, iclass 28, count 2 2006.257.06:58:46.46#ibcon#read 6, iclass 28, count 2 2006.257.06:58:46.46#ibcon#end of sib2, iclass 28, count 2 2006.257.06:58:46.46#ibcon#*after write, iclass 28, count 2 2006.257.06:58:46.46#ibcon#*before return 0, iclass 28, count 2 2006.257.06:58:46.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:46.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:46.46#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.06:58:46.46#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:46.46#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:46.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:46.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:46.58#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:58:46.58#ibcon#first serial, iclass 28, count 0 2006.257.06:58:46.58#ibcon#enter sib2, iclass 28, count 0 2006.257.06:58:46.58#ibcon#flushed, iclass 28, count 0 2006.257.06:58:46.58#ibcon#about to write, iclass 28, count 0 2006.257.06:58:46.58#ibcon#wrote, iclass 28, count 0 2006.257.06:58:46.58#ibcon#about to read 3, iclass 28, count 0 2006.257.06:58:46.60#ibcon#read 3, iclass 28, count 0 2006.257.06:58:46.60#ibcon#about to read 4, iclass 28, count 0 2006.257.06:58:46.60#ibcon#read 4, iclass 28, count 0 2006.257.06:58:46.60#ibcon#about to read 5, iclass 28, count 0 2006.257.06:58:46.60#ibcon#read 5, iclass 28, count 0 2006.257.06:58:46.60#ibcon#about to read 6, iclass 28, count 0 2006.257.06:58:46.60#ibcon#read 6, iclass 28, count 0 2006.257.06:58:46.60#ibcon#end of sib2, iclass 28, count 0 2006.257.06:58:46.60#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:58:46.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:58:46.60#ibcon#[25=USB\r\n] 2006.257.06:58:46.60#ibcon#*before write, iclass 28, count 0 2006.257.06:58:46.60#ibcon#enter sib2, iclass 28, count 0 2006.257.06:58:46.60#ibcon#flushed, iclass 28, count 0 2006.257.06:58:46.60#ibcon#about to write, iclass 28, count 0 2006.257.06:58:46.60#ibcon#wrote, iclass 28, count 0 2006.257.06:58:46.60#ibcon#about to read 3, iclass 28, count 0 2006.257.06:58:46.63#ibcon#read 3, iclass 28, count 0 2006.257.06:58:46.63#ibcon#about to read 4, iclass 28, count 0 2006.257.06:58:46.63#ibcon#read 4, iclass 28, count 0 2006.257.06:58:46.63#ibcon#about to read 5, iclass 28, count 0 2006.257.06:58:46.63#ibcon#read 5, iclass 28, count 0 2006.257.06:58:46.63#ibcon#about to read 6, iclass 28, count 0 2006.257.06:58:46.63#ibcon#read 6, iclass 28, count 0 2006.257.06:58:46.63#ibcon#end of sib2, iclass 28, count 0 2006.257.06:58:46.63#ibcon#*after write, iclass 28, count 0 2006.257.06:58:46.63#ibcon#*before return 0, iclass 28, count 0 2006.257.06:58:46.63#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:46.63#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:46.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:58:46.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:58:46.63$vck44/valo=5,734.99 2006.257.06:58:46.63#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.06:58:46.63#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.06:58:46.63#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:46.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:46.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:46.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:46.63#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:58:46.63#ibcon#first serial, iclass 30, count 0 2006.257.06:58:46.63#ibcon#enter sib2, iclass 30, count 0 2006.257.06:58:46.63#ibcon#flushed, iclass 30, count 0 2006.257.06:58:46.63#ibcon#about to write, iclass 30, count 0 2006.257.06:58:46.63#ibcon#wrote, iclass 30, count 0 2006.257.06:58:46.63#ibcon#about to read 3, iclass 30, count 0 2006.257.06:58:46.65#ibcon#read 3, iclass 30, count 0 2006.257.06:58:46.65#ibcon#about to read 4, iclass 30, count 0 2006.257.06:58:46.65#ibcon#read 4, iclass 30, count 0 2006.257.06:58:46.65#ibcon#about to read 5, iclass 30, count 0 2006.257.06:58:46.65#ibcon#read 5, iclass 30, count 0 2006.257.06:58:46.65#ibcon#about to read 6, iclass 30, count 0 2006.257.06:58:46.65#ibcon#read 6, iclass 30, count 0 2006.257.06:58:46.65#ibcon#end of sib2, iclass 30, count 0 2006.257.06:58:46.65#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:58:46.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:58:46.65#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.06:58:46.65#ibcon#*before write, iclass 30, count 0 2006.257.06:58:46.65#ibcon#enter sib2, iclass 30, count 0 2006.257.06:58:46.65#ibcon#flushed, iclass 30, count 0 2006.257.06:58:46.65#ibcon#about to write, iclass 30, count 0 2006.257.06:58:46.65#ibcon#wrote, iclass 30, count 0 2006.257.06:58:46.65#ibcon#about to read 3, iclass 30, count 0 2006.257.06:58:46.69#ibcon#read 3, iclass 30, count 0 2006.257.06:58:46.69#ibcon#about to read 4, iclass 30, count 0 2006.257.06:58:46.69#ibcon#read 4, iclass 30, count 0 2006.257.06:58:46.69#ibcon#about to read 5, iclass 30, count 0 2006.257.06:58:46.69#ibcon#read 5, iclass 30, count 0 2006.257.06:58:46.69#ibcon#about to read 6, iclass 30, count 0 2006.257.06:58:46.69#ibcon#read 6, iclass 30, count 0 2006.257.06:58:46.69#ibcon#end of sib2, iclass 30, count 0 2006.257.06:58:46.69#ibcon#*after write, iclass 30, count 0 2006.257.06:58:46.69#ibcon#*before return 0, iclass 30, count 0 2006.257.06:58:46.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:46.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:46.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:58:46.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:58:46.69$vck44/va=5,4 2006.257.06:58:46.69#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.06:58:46.69#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.06:58:46.69#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:46.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:46.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:46.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:46.75#ibcon#enter wrdev, iclass 32, count 2 2006.257.06:58:46.75#ibcon#first serial, iclass 32, count 2 2006.257.06:58:46.75#ibcon#enter sib2, iclass 32, count 2 2006.257.06:58:46.75#ibcon#flushed, iclass 32, count 2 2006.257.06:58:46.75#ibcon#about to write, iclass 32, count 2 2006.257.06:58:46.75#ibcon#wrote, iclass 32, count 2 2006.257.06:58:46.75#ibcon#about to read 3, iclass 32, count 2 2006.257.06:58:46.77#ibcon#read 3, iclass 32, count 2 2006.257.06:58:46.77#ibcon#about to read 4, iclass 32, count 2 2006.257.06:58:46.77#ibcon#read 4, iclass 32, count 2 2006.257.06:58:46.77#ibcon#about to read 5, iclass 32, count 2 2006.257.06:58:46.77#ibcon#read 5, iclass 32, count 2 2006.257.06:58:46.77#ibcon#about to read 6, iclass 32, count 2 2006.257.06:58:46.77#ibcon#read 6, iclass 32, count 2 2006.257.06:58:46.77#ibcon#end of sib2, iclass 32, count 2 2006.257.06:58:46.77#ibcon#*mode == 0, iclass 32, count 2 2006.257.06:58:46.77#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.06:58:46.77#ibcon#[25=AT05-04\r\n] 2006.257.06:58:46.77#ibcon#*before write, iclass 32, count 2 2006.257.06:58:46.77#ibcon#enter sib2, iclass 32, count 2 2006.257.06:58:46.77#ibcon#flushed, iclass 32, count 2 2006.257.06:58:46.77#ibcon#about to write, iclass 32, count 2 2006.257.06:58:46.77#ibcon#wrote, iclass 32, count 2 2006.257.06:58:46.77#ibcon#about to read 3, iclass 32, count 2 2006.257.06:58:46.80#ibcon#read 3, iclass 32, count 2 2006.257.06:58:46.80#ibcon#about to read 4, iclass 32, count 2 2006.257.06:58:46.80#ibcon#read 4, iclass 32, count 2 2006.257.06:58:46.80#ibcon#about to read 5, iclass 32, count 2 2006.257.06:58:46.80#ibcon#read 5, iclass 32, count 2 2006.257.06:58:46.80#ibcon#about to read 6, iclass 32, count 2 2006.257.06:58:46.80#ibcon#read 6, iclass 32, count 2 2006.257.06:58:46.80#ibcon#end of sib2, iclass 32, count 2 2006.257.06:58:46.80#ibcon#*after write, iclass 32, count 2 2006.257.06:58:46.80#ibcon#*before return 0, iclass 32, count 2 2006.257.06:58:46.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:46.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:46.80#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.06:58:46.80#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:46.80#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:46.92#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:46.92#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:46.92#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:58:46.92#ibcon#first serial, iclass 32, count 0 2006.257.06:58:46.92#ibcon#enter sib2, iclass 32, count 0 2006.257.06:58:46.92#ibcon#flushed, iclass 32, count 0 2006.257.06:58:46.92#ibcon#about to write, iclass 32, count 0 2006.257.06:58:46.92#ibcon#wrote, iclass 32, count 0 2006.257.06:58:46.92#ibcon#about to read 3, iclass 32, count 0 2006.257.06:58:46.94#ibcon#read 3, iclass 32, count 0 2006.257.06:58:46.94#ibcon#about to read 4, iclass 32, count 0 2006.257.06:58:46.94#ibcon#read 4, iclass 32, count 0 2006.257.06:58:46.94#ibcon#about to read 5, iclass 32, count 0 2006.257.06:58:46.94#ibcon#read 5, iclass 32, count 0 2006.257.06:58:46.94#ibcon#about to read 6, iclass 32, count 0 2006.257.06:58:46.94#ibcon#read 6, iclass 32, count 0 2006.257.06:58:46.94#ibcon#end of sib2, iclass 32, count 0 2006.257.06:58:46.94#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:58:46.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:58:46.94#ibcon#[25=USB\r\n] 2006.257.06:58:46.94#ibcon#*before write, iclass 32, count 0 2006.257.06:58:46.94#ibcon#enter sib2, iclass 32, count 0 2006.257.06:58:46.94#ibcon#flushed, iclass 32, count 0 2006.257.06:58:46.94#ibcon#about to write, iclass 32, count 0 2006.257.06:58:46.94#ibcon#wrote, iclass 32, count 0 2006.257.06:58:46.94#ibcon#about to read 3, iclass 32, count 0 2006.257.06:58:46.97#ibcon#read 3, iclass 32, count 0 2006.257.06:58:46.97#ibcon#about to read 4, iclass 32, count 0 2006.257.06:58:46.97#ibcon#read 4, iclass 32, count 0 2006.257.06:58:46.97#ibcon#about to read 5, iclass 32, count 0 2006.257.06:58:46.97#ibcon#read 5, iclass 32, count 0 2006.257.06:58:46.97#ibcon#about to read 6, iclass 32, count 0 2006.257.06:58:46.97#ibcon#read 6, iclass 32, count 0 2006.257.06:58:46.97#ibcon#end of sib2, iclass 32, count 0 2006.257.06:58:46.97#ibcon#*after write, iclass 32, count 0 2006.257.06:58:46.97#ibcon#*before return 0, iclass 32, count 0 2006.257.06:58:46.97#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:46.97#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:46.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:58:46.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:58:46.97$vck44/valo=6,814.99 2006.257.06:58:46.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.06:58:46.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.06:58:46.97#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:46.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:46.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:46.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:46.97#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:58:46.97#ibcon#first serial, iclass 34, count 0 2006.257.06:58:46.97#ibcon#enter sib2, iclass 34, count 0 2006.257.06:58:46.97#ibcon#flushed, iclass 34, count 0 2006.257.06:58:46.97#ibcon#about to write, iclass 34, count 0 2006.257.06:58:46.97#ibcon#wrote, iclass 34, count 0 2006.257.06:58:46.97#ibcon#about to read 3, iclass 34, count 0 2006.257.06:58:46.99#ibcon#read 3, iclass 34, count 0 2006.257.06:58:46.99#ibcon#about to read 4, iclass 34, count 0 2006.257.06:58:46.99#ibcon#read 4, iclass 34, count 0 2006.257.06:58:46.99#ibcon#about to read 5, iclass 34, count 0 2006.257.06:58:46.99#ibcon#read 5, iclass 34, count 0 2006.257.06:58:46.99#ibcon#about to read 6, iclass 34, count 0 2006.257.06:58:46.99#ibcon#read 6, iclass 34, count 0 2006.257.06:58:46.99#ibcon#end of sib2, iclass 34, count 0 2006.257.06:58:46.99#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:58:46.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:58:46.99#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.06:58:46.99#ibcon#*before write, iclass 34, count 0 2006.257.06:58:46.99#ibcon#enter sib2, iclass 34, count 0 2006.257.06:58:46.99#ibcon#flushed, iclass 34, count 0 2006.257.06:58:46.99#ibcon#about to write, iclass 34, count 0 2006.257.06:58:46.99#ibcon#wrote, iclass 34, count 0 2006.257.06:58:46.99#ibcon#about to read 3, iclass 34, count 0 2006.257.06:58:47.03#ibcon#read 3, iclass 34, count 0 2006.257.06:58:47.03#ibcon#about to read 4, iclass 34, count 0 2006.257.06:58:47.03#ibcon#read 4, iclass 34, count 0 2006.257.06:58:47.03#ibcon#about to read 5, iclass 34, count 0 2006.257.06:58:47.03#ibcon#read 5, iclass 34, count 0 2006.257.06:58:47.03#ibcon#about to read 6, iclass 34, count 0 2006.257.06:58:47.03#ibcon#read 6, iclass 34, count 0 2006.257.06:58:47.03#ibcon#end of sib2, iclass 34, count 0 2006.257.06:58:47.03#ibcon#*after write, iclass 34, count 0 2006.257.06:58:47.03#ibcon#*before return 0, iclass 34, count 0 2006.257.06:58:47.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:47.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:47.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:58:47.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:58:47.03$vck44/va=6,4 2006.257.06:58:47.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.06:58:47.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.06:58:47.03#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:47.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:47.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:47.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:47.09#ibcon#enter wrdev, iclass 36, count 2 2006.257.06:58:47.09#ibcon#first serial, iclass 36, count 2 2006.257.06:58:47.09#ibcon#enter sib2, iclass 36, count 2 2006.257.06:58:47.09#ibcon#flushed, iclass 36, count 2 2006.257.06:58:47.09#ibcon#about to write, iclass 36, count 2 2006.257.06:58:47.09#ibcon#wrote, iclass 36, count 2 2006.257.06:58:47.09#ibcon#about to read 3, iclass 36, count 2 2006.257.06:58:47.11#ibcon#read 3, iclass 36, count 2 2006.257.06:58:47.11#ibcon#about to read 4, iclass 36, count 2 2006.257.06:58:47.11#ibcon#read 4, iclass 36, count 2 2006.257.06:58:47.11#ibcon#about to read 5, iclass 36, count 2 2006.257.06:58:47.11#ibcon#read 5, iclass 36, count 2 2006.257.06:58:47.11#ibcon#about to read 6, iclass 36, count 2 2006.257.06:58:47.11#ibcon#read 6, iclass 36, count 2 2006.257.06:58:47.11#ibcon#end of sib2, iclass 36, count 2 2006.257.06:58:47.11#ibcon#*mode == 0, iclass 36, count 2 2006.257.06:58:47.11#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.06:58:47.11#ibcon#[25=AT06-04\r\n] 2006.257.06:58:47.11#ibcon#*before write, iclass 36, count 2 2006.257.06:58:47.11#ibcon#enter sib2, iclass 36, count 2 2006.257.06:58:47.11#ibcon#flushed, iclass 36, count 2 2006.257.06:58:47.11#ibcon#about to write, iclass 36, count 2 2006.257.06:58:47.11#ibcon#wrote, iclass 36, count 2 2006.257.06:58:47.11#ibcon#about to read 3, iclass 36, count 2 2006.257.06:58:47.14#ibcon#read 3, iclass 36, count 2 2006.257.06:58:47.14#ibcon#about to read 4, iclass 36, count 2 2006.257.06:58:47.14#ibcon#read 4, iclass 36, count 2 2006.257.06:58:47.14#ibcon#about to read 5, iclass 36, count 2 2006.257.06:58:47.14#ibcon#read 5, iclass 36, count 2 2006.257.06:58:47.14#ibcon#about to read 6, iclass 36, count 2 2006.257.06:58:47.14#ibcon#read 6, iclass 36, count 2 2006.257.06:58:47.14#ibcon#end of sib2, iclass 36, count 2 2006.257.06:58:47.14#ibcon#*after write, iclass 36, count 2 2006.257.06:58:47.14#ibcon#*before return 0, iclass 36, count 2 2006.257.06:58:47.14#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:47.14#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:47.14#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.06:58:47.14#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:47.14#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:47.26#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:47.26#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:47.26#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:58:47.26#ibcon#first serial, iclass 36, count 0 2006.257.06:58:47.26#ibcon#enter sib2, iclass 36, count 0 2006.257.06:58:47.26#ibcon#flushed, iclass 36, count 0 2006.257.06:58:47.26#ibcon#about to write, iclass 36, count 0 2006.257.06:58:47.26#ibcon#wrote, iclass 36, count 0 2006.257.06:58:47.26#ibcon#about to read 3, iclass 36, count 0 2006.257.06:58:47.28#ibcon#read 3, iclass 36, count 0 2006.257.06:58:47.28#ibcon#about to read 4, iclass 36, count 0 2006.257.06:58:47.28#ibcon#read 4, iclass 36, count 0 2006.257.06:58:47.28#ibcon#about to read 5, iclass 36, count 0 2006.257.06:58:47.28#ibcon#read 5, iclass 36, count 0 2006.257.06:58:47.28#ibcon#about to read 6, iclass 36, count 0 2006.257.06:58:47.28#ibcon#read 6, iclass 36, count 0 2006.257.06:58:47.28#ibcon#end of sib2, iclass 36, count 0 2006.257.06:58:47.28#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:58:47.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:58:47.28#ibcon#[25=USB\r\n] 2006.257.06:58:47.28#ibcon#*before write, iclass 36, count 0 2006.257.06:58:47.28#ibcon#enter sib2, iclass 36, count 0 2006.257.06:58:47.28#ibcon#flushed, iclass 36, count 0 2006.257.06:58:47.28#ibcon#about to write, iclass 36, count 0 2006.257.06:58:47.28#ibcon#wrote, iclass 36, count 0 2006.257.06:58:47.28#ibcon#about to read 3, iclass 36, count 0 2006.257.06:58:47.31#ibcon#read 3, iclass 36, count 0 2006.257.06:58:47.31#ibcon#about to read 4, iclass 36, count 0 2006.257.06:58:47.31#ibcon#read 4, iclass 36, count 0 2006.257.06:58:47.31#ibcon#about to read 5, iclass 36, count 0 2006.257.06:58:47.31#ibcon#read 5, iclass 36, count 0 2006.257.06:58:47.31#ibcon#about to read 6, iclass 36, count 0 2006.257.06:58:47.31#ibcon#read 6, iclass 36, count 0 2006.257.06:58:47.31#ibcon#end of sib2, iclass 36, count 0 2006.257.06:58:47.31#ibcon#*after write, iclass 36, count 0 2006.257.06:58:47.31#ibcon#*before return 0, iclass 36, count 0 2006.257.06:58:47.31#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:47.31#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:47.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:58:47.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:58:47.31$vck44/valo=7,864.99 2006.257.06:58:47.31#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.06:58:47.31#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.06:58:47.31#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:47.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:47.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:47.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:47.31#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:58:47.31#ibcon#first serial, iclass 38, count 0 2006.257.06:58:47.31#ibcon#enter sib2, iclass 38, count 0 2006.257.06:58:47.31#ibcon#flushed, iclass 38, count 0 2006.257.06:58:47.31#ibcon#about to write, iclass 38, count 0 2006.257.06:58:47.31#ibcon#wrote, iclass 38, count 0 2006.257.06:58:47.31#ibcon#about to read 3, iclass 38, count 0 2006.257.06:58:47.33#ibcon#read 3, iclass 38, count 0 2006.257.06:58:47.33#ibcon#about to read 4, iclass 38, count 0 2006.257.06:58:47.33#ibcon#read 4, iclass 38, count 0 2006.257.06:58:47.33#ibcon#about to read 5, iclass 38, count 0 2006.257.06:58:47.33#ibcon#read 5, iclass 38, count 0 2006.257.06:58:47.33#ibcon#about to read 6, iclass 38, count 0 2006.257.06:58:47.33#ibcon#read 6, iclass 38, count 0 2006.257.06:58:47.33#ibcon#end of sib2, iclass 38, count 0 2006.257.06:58:47.33#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:58:47.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:58:47.33#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.06:58:47.33#ibcon#*before write, iclass 38, count 0 2006.257.06:58:47.33#ibcon#enter sib2, iclass 38, count 0 2006.257.06:58:47.33#ibcon#flushed, iclass 38, count 0 2006.257.06:58:47.33#ibcon#about to write, iclass 38, count 0 2006.257.06:58:47.33#ibcon#wrote, iclass 38, count 0 2006.257.06:58:47.33#ibcon#about to read 3, iclass 38, count 0 2006.257.06:58:47.37#ibcon#read 3, iclass 38, count 0 2006.257.06:58:47.37#ibcon#about to read 4, iclass 38, count 0 2006.257.06:58:47.37#ibcon#read 4, iclass 38, count 0 2006.257.06:58:47.37#ibcon#about to read 5, iclass 38, count 0 2006.257.06:58:47.37#ibcon#read 5, iclass 38, count 0 2006.257.06:58:47.37#ibcon#about to read 6, iclass 38, count 0 2006.257.06:58:47.37#ibcon#read 6, iclass 38, count 0 2006.257.06:58:47.37#ibcon#end of sib2, iclass 38, count 0 2006.257.06:58:47.37#ibcon#*after write, iclass 38, count 0 2006.257.06:58:47.37#ibcon#*before return 0, iclass 38, count 0 2006.257.06:58:47.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:47.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:47.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:58:47.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:58:47.37$vck44/va=7,4 2006.257.06:58:47.37#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.06:58:47.37#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.06:58:47.37#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:47.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:47.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:47.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:47.43#ibcon#enter wrdev, iclass 40, count 2 2006.257.06:58:47.43#ibcon#first serial, iclass 40, count 2 2006.257.06:58:47.43#ibcon#enter sib2, iclass 40, count 2 2006.257.06:58:47.43#ibcon#flushed, iclass 40, count 2 2006.257.06:58:47.43#ibcon#about to write, iclass 40, count 2 2006.257.06:58:47.43#ibcon#wrote, iclass 40, count 2 2006.257.06:58:47.43#ibcon#about to read 3, iclass 40, count 2 2006.257.06:58:47.45#ibcon#read 3, iclass 40, count 2 2006.257.06:58:47.45#ibcon#about to read 4, iclass 40, count 2 2006.257.06:58:47.45#ibcon#read 4, iclass 40, count 2 2006.257.06:58:47.45#ibcon#about to read 5, iclass 40, count 2 2006.257.06:58:47.45#ibcon#read 5, iclass 40, count 2 2006.257.06:58:47.45#ibcon#about to read 6, iclass 40, count 2 2006.257.06:58:47.45#ibcon#read 6, iclass 40, count 2 2006.257.06:58:47.45#ibcon#end of sib2, iclass 40, count 2 2006.257.06:58:47.45#ibcon#*mode == 0, iclass 40, count 2 2006.257.06:58:47.45#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.06:58:47.45#ibcon#[25=AT07-04\r\n] 2006.257.06:58:47.45#ibcon#*before write, iclass 40, count 2 2006.257.06:58:47.45#ibcon#enter sib2, iclass 40, count 2 2006.257.06:58:47.45#ibcon#flushed, iclass 40, count 2 2006.257.06:58:47.45#ibcon#about to write, iclass 40, count 2 2006.257.06:58:47.45#ibcon#wrote, iclass 40, count 2 2006.257.06:58:47.45#ibcon#about to read 3, iclass 40, count 2 2006.257.06:58:47.48#ibcon#read 3, iclass 40, count 2 2006.257.06:58:47.48#ibcon#about to read 4, iclass 40, count 2 2006.257.06:58:47.48#ibcon#read 4, iclass 40, count 2 2006.257.06:58:47.48#ibcon#about to read 5, iclass 40, count 2 2006.257.06:58:47.48#ibcon#read 5, iclass 40, count 2 2006.257.06:58:47.48#ibcon#about to read 6, iclass 40, count 2 2006.257.06:58:47.48#ibcon#read 6, iclass 40, count 2 2006.257.06:58:47.48#ibcon#end of sib2, iclass 40, count 2 2006.257.06:58:47.48#ibcon#*after write, iclass 40, count 2 2006.257.06:58:47.48#ibcon#*before return 0, iclass 40, count 2 2006.257.06:58:47.48#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:47.48#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:47.48#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.06:58:47.48#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:47.48#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:47.60#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:47.60#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:47.60#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:58:47.60#ibcon#first serial, iclass 40, count 0 2006.257.06:58:47.60#ibcon#enter sib2, iclass 40, count 0 2006.257.06:58:47.60#ibcon#flushed, iclass 40, count 0 2006.257.06:58:47.60#ibcon#about to write, iclass 40, count 0 2006.257.06:58:47.60#ibcon#wrote, iclass 40, count 0 2006.257.06:58:47.60#ibcon#about to read 3, iclass 40, count 0 2006.257.06:58:47.62#ibcon#read 3, iclass 40, count 0 2006.257.06:58:47.62#ibcon#about to read 4, iclass 40, count 0 2006.257.06:58:47.62#ibcon#read 4, iclass 40, count 0 2006.257.06:58:47.62#ibcon#about to read 5, iclass 40, count 0 2006.257.06:58:47.62#ibcon#read 5, iclass 40, count 0 2006.257.06:58:47.62#ibcon#about to read 6, iclass 40, count 0 2006.257.06:58:47.62#ibcon#read 6, iclass 40, count 0 2006.257.06:58:47.62#ibcon#end of sib2, iclass 40, count 0 2006.257.06:58:47.62#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:58:47.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:58:47.62#ibcon#[25=USB\r\n] 2006.257.06:58:47.62#ibcon#*before write, iclass 40, count 0 2006.257.06:58:47.62#ibcon#enter sib2, iclass 40, count 0 2006.257.06:58:47.62#ibcon#flushed, iclass 40, count 0 2006.257.06:58:47.62#ibcon#about to write, iclass 40, count 0 2006.257.06:58:47.62#ibcon#wrote, iclass 40, count 0 2006.257.06:58:47.62#ibcon#about to read 3, iclass 40, count 0 2006.257.06:58:47.65#ibcon#read 3, iclass 40, count 0 2006.257.06:58:47.65#ibcon#about to read 4, iclass 40, count 0 2006.257.06:58:47.65#ibcon#read 4, iclass 40, count 0 2006.257.06:58:47.65#ibcon#about to read 5, iclass 40, count 0 2006.257.06:58:47.65#ibcon#read 5, iclass 40, count 0 2006.257.06:58:47.65#ibcon#about to read 6, iclass 40, count 0 2006.257.06:58:47.65#ibcon#read 6, iclass 40, count 0 2006.257.06:58:47.65#ibcon#end of sib2, iclass 40, count 0 2006.257.06:58:47.65#ibcon#*after write, iclass 40, count 0 2006.257.06:58:47.65#ibcon#*before return 0, iclass 40, count 0 2006.257.06:58:47.65#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:47.65#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:47.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:58:47.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:58:47.65$vck44/valo=8,884.99 2006.257.06:58:47.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.06:58:47.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.06:58:47.65#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:47.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:47.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:47.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:47.65#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:58:47.65#ibcon#first serial, iclass 4, count 0 2006.257.06:58:47.65#ibcon#enter sib2, iclass 4, count 0 2006.257.06:58:47.65#ibcon#flushed, iclass 4, count 0 2006.257.06:58:47.65#ibcon#about to write, iclass 4, count 0 2006.257.06:58:47.65#ibcon#wrote, iclass 4, count 0 2006.257.06:58:47.65#ibcon#about to read 3, iclass 4, count 0 2006.257.06:58:47.67#ibcon#read 3, iclass 4, count 0 2006.257.06:58:47.67#ibcon#about to read 4, iclass 4, count 0 2006.257.06:58:47.67#ibcon#read 4, iclass 4, count 0 2006.257.06:58:47.67#ibcon#about to read 5, iclass 4, count 0 2006.257.06:58:47.67#ibcon#read 5, iclass 4, count 0 2006.257.06:58:47.67#ibcon#about to read 6, iclass 4, count 0 2006.257.06:58:47.67#ibcon#read 6, iclass 4, count 0 2006.257.06:58:47.67#ibcon#end of sib2, iclass 4, count 0 2006.257.06:58:47.67#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:58:47.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:58:47.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.06:58:47.67#ibcon#*before write, iclass 4, count 0 2006.257.06:58:47.67#ibcon#enter sib2, iclass 4, count 0 2006.257.06:58:47.67#ibcon#flushed, iclass 4, count 0 2006.257.06:58:47.67#ibcon#about to write, iclass 4, count 0 2006.257.06:58:47.67#ibcon#wrote, iclass 4, count 0 2006.257.06:58:47.67#ibcon#about to read 3, iclass 4, count 0 2006.257.06:58:47.71#ibcon#read 3, iclass 4, count 0 2006.257.06:58:47.71#ibcon#about to read 4, iclass 4, count 0 2006.257.06:58:47.71#ibcon#read 4, iclass 4, count 0 2006.257.06:58:47.71#ibcon#about to read 5, iclass 4, count 0 2006.257.06:58:47.71#ibcon#read 5, iclass 4, count 0 2006.257.06:58:47.71#ibcon#about to read 6, iclass 4, count 0 2006.257.06:58:47.71#ibcon#read 6, iclass 4, count 0 2006.257.06:58:47.71#ibcon#end of sib2, iclass 4, count 0 2006.257.06:58:47.71#ibcon#*after write, iclass 4, count 0 2006.257.06:58:47.71#ibcon#*before return 0, iclass 4, count 0 2006.257.06:58:47.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:47.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:47.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:58:47.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:58:47.71$vck44/va=8,4 2006.257.06:58:47.71#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.06:58:47.71#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.06:58:47.71#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:47.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:58:47.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:58:47.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:58:47.77#ibcon#enter wrdev, iclass 6, count 2 2006.257.06:58:47.77#ibcon#first serial, iclass 6, count 2 2006.257.06:58:47.77#ibcon#enter sib2, iclass 6, count 2 2006.257.06:58:47.77#ibcon#flushed, iclass 6, count 2 2006.257.06:58:47.77#ibcon#about to write, iclass 6, count 2 2006.257.06:58:47.77#ibcon#wrote, iclass 6, count 2 2006.257.06:58:47.77#ibcon#about to read 3, iclass 6, count 2 2006.257.06:58:47.79#ibcon#read 3, iclass 6, count 2 2006.257.06:58:47.79#ibcon#about to read 4, iclass 6, count 2 2006.257.06:58:47.79#ibcon#read 4, iclass 6, count 2 2006.257.06:58:47.79#ibcon#about to read 5, iclass 6, count 2 2006.257.06:58:47.79#ibcon#read 5, iclass 6, count 2 2006.257.06:58:47.79#ibcon#about to read 6, iclass 6, count 2 2006.257.06:58:47.79#ibcon#read 6, iclass 6, count 2 2006.257.06:58:47.79#ibcon#end of sib2, iclass 6, count 2 2006.257.06:58:47.79#ibcon#*mode == 0, iclass 6, count 2 2006.257.06:58:47.79#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.06:58:47.79#ibcon#[25=AT08-04\r\n] 2006.257.06:58:47.79#ibcon#*before write, iclass 6, count 2 2006.257.06:58:47.79#ibcon#enter sib2, iclass 6, count 2 2006.257.06:58:47.79#ibcon#flushed, iclass 6, count 2 2006.257.06:58:47.79#ibcon#about to write, iclass 6, count 2 2006.257.06:58:47.79#ibcon#wrote, iclass 6, count 2 2006.257.06:58:47.79#ibcon#about to read 3, iclass 6, count 2 2006.257.06:58:47.82#ibcon#read 3, iclass 6, count 2 2006.257.06:58:47.82#ibcon#about to read 4, iclass 6, count 2 2006.257.06:58:47.82#ibcon#read 4, iclass 6, count 2 2006.257.06:58:47.82#ibcon#about to read 5, iclass 6, count 2 2006.257.06:58:47.82#ibcon#read 5, iclass 6, count 2 2006.257.06:58:47.82#ibcon#about to read 6, iclass 6, count 2 2006.257.06:58:47.82#ibcon#read 6, iclass 6, count 2 2006.257.06:58:47.82#ibcon#end of sib2, iclass 6, count 2 2006.257.06:58:47.82#ibcon#*after write, iclass 6, count 2 2006.257.06:58:47.82#ibcon#*before return 0, iclass 6, count 2 2006.257.06:58:47.82#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:58:47.82#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.06:58:47.82#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.06:58:47.82#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:47.82#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:58:47.94#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:58:47.94#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:58:47.94#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:58:47.94#ibcon#first serial, iclass 6, count 0 2006.257.06:58:47.94#ibcon#enter sib2, iclass 6, count 0 2006.257.06:58:47.94#ibcon#flushed, iclass 6, count 0 2006.257.06:58:47.94#ibcon#about to write, iclass 6, count 0 2006.257.06:58:47.94#ibcon#wrote, iclass 6, count 0 2006.257.06:58:47.94#ibcon#about to read 3, iclass 6, count 0 2006.257.06:58:47.96#ibcon#read 3, iclass 6, count 0 2006.257.06:58:47.96#ibcon#about to read 4, iclass 6, count 0 2006.257.06:58:47.96#ibcon#read 4, iclass 6, count 0 2006.257.06:58:47.96#ibcon#about to read 5, iclass 6, count 0 2006.257.06:58:47.96#ibcon#read 5, iclass 6, count 0 2006.257.06:58:47.96#ibcon#about to read 6, iclass 6, count 0 2006.257.06:58:47.96#ibcon#read 6, iclass 6, count 0 2006.257.06:58:47.96#ibcon#end of sib2, iclass 6, count 0 2006.257.06:58:47.96#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:58:47.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:58:47.96#ibcon#[25=USB\r\n] 2006.257.06:58:47.96#ibcon#*before write, iclass 6, count 0 2006.257.06:58:47.96#ibcon#enter sib2, iclass 6, count 0 2006.257.06:58:47.96#ibcon#flushed, iclass 6, count 0 2006.257.06:58:47.96#ibcon#about to write, iclass 6, count 0 2006.257.06:58:47.96#ibcon#wrote, iclass 6, count 0 2006.257.06:58:47.96#ibcon#about to read 3, iclass 6, count 0 2006.257.06:58:47.99#ibcon#read 3, iclass 6, count 0 2006.257.06:58:47.99#ibcon#about to read 4, iclass 6, count 0 2006.257.06:58:47.99#ibcon#read 4, iclass 6, count 0 2006.257.06:58:47.99#ibcon#about to read 5, iclass 6, count 0 2006.257.06:58:47.99#ibcon#read 5, iclass 6, count 0 2006.257.06:58:47.99#ibcon#about to read 6, iclass 6, count 0 2006.257.06:58:47.99#ibcon#read 6, iclass 6, count 0 2006.257.06:58:47.99#ibcon#end of sib2, iclass 6, count 0 2006.257.06:58:47.99#ibcon#*after write, iclass 6, count 0 2006.257.06:58:47.99#ibcon#*before return 0, iclass 6, count 0 2006.257.06:58:47.99#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:58:47.99#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.06:58:47.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:58:47.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:58:47.99$vck44/vblo=1,629.99 2006.257.06:58:47.99#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.06:58:47.99#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.06:58:47.99#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:47.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:58:47.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:58:47.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:58:47.99#ibcon#enter wrdev, iclass 10, count 0 2006.257.06:58:47.99#ibcon#first serial, iclass 10, count 0 2006.257.06:58:47.99#ibcon#enter sib2, iclass 10, count 0 2006.257.06:58:47.99#ibcon#flushed, iclass 10, count 0 2006.257.06:58:47.99#ibcon#about to write, iclass 10, count 0 2006.257.06:58:47.99#ibcon#wrote, iclass 10, count 0 2006.257.06:58:47.99#ibcon#about to read 3, iclass 10, count 0 2006.257.06:58:48.01#ibcon#read 3, iclass 10, count 0 2006.257.06:58:48.01#ibcon#about to read 4, iclass 10, count 0 2006.257.06:58:48.01#ibcon#read 4, iclass 10, count 0 2006.257.06:58:48.01#ibcon#about to read 5, iclass 10, count 0 2006.257.06:58:48.01#ibcon#read 5, iclass 10, count 0 2006.257.06:58:48.01#ibcon#about to read 6, iclass 10, count 0 2006.257.06:58:48.01#ibcon#read 6, iclass 10, count 0 2006.257.06:58:48.01#ibcon#end of sib2, iclass 10, count 0 2006.257.06:58:48.01#ibcon#*mode == 0, iclass 10, count 0 2006.257.06:58:48.01#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.06:58:48.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.06:58:48.01#ibcon#*before write, iclass 10, count 0 2006.257.06:58:48.01#ibcon#enter sib2, iclass 10, count 0 2006.257.06:58:48.01#ibcon#flushed, iclass 10, count 0 2006.257.06:58:48.01#ibcon#about to write, iclass 10, count 0 2006.257.06:58:48.01#ibcon#wrote, iclass 10, count 0 2006.257.06:58:48.01#ibcon#about to read 3, iclass 10, count 0 2006.257.06:58:48.05#ibcon#read 3, iclass 10, count 0 2006.257.06:58:48.05#ibcon#about to read 4, iclass 10, count 0 2006.257.06:58:48.05#ibcon#read 4, iclass 10, count 0 2006.257.06:58:48.05#ibcon#about to read 5, iclass 10, count 0 2006.257.06:58:48.05#ibcon#read 5, iclass 10, count 0 2006.257.06:58:48.05#ibcon#about to read 6, iclass 10, count 0 2006.257.06:58:48.05#ibcon#read 6, iclass 10, count 0 2006.257.06:58:48.05#ibcon#end of sib2, iclass 10, count 0 2006.257.06:58:48.05#ibcon#*after write, iclass 10, count 0 2006.257.06:58:48.05#ibcon#*before return 0, iclass 10, count 0 2006.257.06:58:48.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:58:48.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.06:58:48.05#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.06:58:48.05#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.06:58:48.05$vck44/vb=1,4 2006.257.06:58:48.05#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.06:58:48.05#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.06:58:48.05#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:48.05#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:58:48.05#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:58:48.05#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:58:48.05#ibcon#enter wrdev, iclass 12, count 2 2006.257.06:58:48.05#ibcon#first serial, iclass 12, count 2 2006.257.06:58:48.05#ibcon#enter sib2, iclass 12, count 2 2006.257.06:58:48.05#ibcon#flushed, iclass 12, count 2 2006.257.06:58:48.05#ibcon#about to write, iclass 12, count 2 2006.257.06:58:48.05#ibcon#wrote, iclass 12, count 2 2006.257.06:58:48.05#ibcon#about to read 3, iclass 12, count 2 2006.257.06:58:48.07#ibcon#read 3, iclass 12, count 2 2006.257.06:58:48.07#ibcon#about to read 4, iclass 12, count 2 2006.257.06:58:48.07#ibcon#read 4, iclass 12, count 2 2006.257.06:58:48.07#ibcon#about to read 5, iclass 12, count 2 2006.257.06:58:48.07#ibcon#read 5, iclass 12, count 2 2006.257.06:58:48.07#ibcon#about to read 6, iclass 12, count 2 2006.257.06:58:48.07#ibcon#read 6, iclass 12, count 2 2006.257.06:58:48.07#ibcon#end of sib2, iclass 12, count 2 2006.257.06:58:48.07#ibcon#*mode == 0, iclass 12, count 2 2006.257.06:58:48.07#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.06:58:48.07#ibcon#[27=AT01-04\r\n] 2006.257.06:58:48.07#ibcon#*before write, iclass 12, count 2 2006.257.06:58:48.07#ibcon#enter sib2, iclass 12, count 2 2006.257.06:58:48.07#ibcon#flushed, iclass 12, count 2 2006.257.06:58:48.07#ibcon#about to write, iclass 12, count 2 2006.257.06:58:48.07#ibcon#wrote, iclass 12, count 2 2006.257.06:58:48.07#ibcon#about to read 3, iclass 12, count 2 2006.257.06:58:48.10#ibcon#read 3, iclass 12, count 2 2006.257.06:58:48.10#ibcon#about to read 4, iclass 12, count 2 2006.257.06:58:48.10#ibcon#read 4, iclass 12, count 2 2006.257.06:58:48.10#ibcon#about to read 5, iclass 12, count 2 2006.257.06:58:48.10#ibcon#read 5, iclass 12, count 2 2006.257.06:58:48.10#ibcon#about to read 6, iclass 12, count 2 2006.257.06:58:48.10#ibcon#read 6, iclass 12, count 2 2006.257.06:58:48.10#ibcon#end of sib2, iclass 12, count 2 2006.257.06:58:48.10#ibcon#*after write, iclass 12, count 2 2006.257.06:58:48.10#ibcon#*before return 0, iclass 12, count 2 2006.257.06:58:48.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:58:48.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.06:58:48.10#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.06:58:48.10#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:48.10#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:58:48.22#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:58:48.22#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:58:48.22#ibcon#enter wrdev, iclass 12, count 0 2006.257.06:58:48.22#ibcon#first serial, iclass 12, count 0 2006.257.06:58:48.22#ibcon#enter sib2, iclass 12, count 0 2006.257.06:58:48.22#ibcon#flushed, iclass 12, count 0 2006.257.06:58:48.22#ibcon#about to write, iclass 12, count 0 2006.257.06:58:48.22#ibcon#wrote, iclass 12, count 0 2006.257.06:58:48.22#ibcon#about to read 3, iclass 12, count 0 2006.257.06:58:48.24#ibcon#read 3, iclass 12, count 0 2006.257.06:58:48.24#ibcon#about to read 4, iclass 12, count 0 2006.257.06:58:48.24#ibcon#read 4, iclass 12, count 0 2006.257.06:58:48.24#ibcon#about to read 5, iclass 12, count 0 2006.257.06:58:48.24#ibcon#read 5, iclass 12, count 0 2006.257.06:58:48.24#ibcon#about to read 6, iclass 12, count 0 2006.257.06:58:48.24#ibcon#read 6, iclass 12, count 0 2006.257.06:58:48.24#ibcon#end of sib2, iclass 12, count 0 2006.257.06:58:48.24#ibcon#*mode == 0, iclass 12, count 0 2006.257.06:58:48.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.06:58:48.24#ibcon#[27=USB\r\n] 2006.257.06:58:48.24#ibcon#*before write, iclass 12, count 0 2006.257.06:58:48.24#ibcon#enter sib2, iclass 12, count 0 2006.257.06:58:48.24#ibcon#flushed, iclass 12, count 0 2006.257.06:58:48.24#ibcon#about to write, iclass 12, count 0 2006.257.06:58:48.24#ibcon#wrote, iclass 12, count 0 2006.257.06:58:48.24#ibcon#about to read 3, iclass 12, count 0 2006.257.06:58:48.27#ibcon#read 3, iclass 12, count 0 2006.257.06:58:48.27#ibcon#about to read 4, iclass 12, count 0 2006.257.06:58:48.27#ibcon#read 4, iclass 12, count 0 2006.257.06:58:48.27#ibcon#about to read 5, iclass 12, count 0 2006.257.06:58:48.27#ibcon#read 5, iclass 12, count 0 2006.257.06:58:48.27#ibcon#about to read 6, iclass 12, count 0 2006.257.06:58:48.27#ibcon#read 6, iclass 12, count 0 2006.257.06:58:48.27#ibcon#end of sib2, iclass 12, count 0 2006.257.06:58:48.27#ibcon#*after write, iclass 12, count 0 2006.257.06:58:48.27#ibcon#*before return 0, iclass 12, count 0 2006.257.06:58:48.27#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:58:48.27#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.06:58:48.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.06:58:48.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.06:58:48.27$vck44/vblo=2,634.99 2006.257.06:58:48.27#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.06:58:48.27#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.06:58:48.27#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:48.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:48.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:48.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:48.27#ibcon#enter wrdev, iclass 14, count 0 2006.257.06:58:48.27#ibcon#first serial, iclass 14, count 0 2006.257.06:58:48.27#ibcon#enter sib2, iclass 14, count 0 2006.257.06:58:48.27#ibcon#flushed, iclass 14, count 0 2006.257.06:58:48.27#ibcon#about to write, iclass 14, count 0 2006.257.06:58:48.27#ibcon#wrote, iclass 14, count 0 2006.257.06:58:48.27#ibcon#about to read 3, iclass 14, count 0 2006.257.06:58:48.29#ibcon#read 3, iclass 14, count 0 2006.257.06:58:48.29#ibcon#about to read 4, iclass 14, count 0 2006.257.06:58:48.29#ibcon#read 4, iclass 14, count 0 2006.257.06:58:48.29#ibcon#about to read 5, iclass 14, count 0 2006.257.06:58:48.29#ibcon#read 5, iclass 14, count 0 2006.257.06:58:48.29#ibcon#about to read 6, iclass 14, count 0 2006.257.06:58:48.29#ibcon#read 6, iclass 14, count 0 2006.257.06:58:48.29#ibcon#end of sib2, iclass 14, count 0 2006.257.06:58:48.29#ibcon#*mode == 0, iclass 14, count 0 2006.257.06:58:48.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.06:58:48.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.06:58:48.29#ibcon#*before write, iclass 14, count 0 2006.257.06:58:48.29#ibcon#enter sib2, iclass 14, count 0 2006.257.06:58:48.29#ibcon#flushed, iclass 14, count 0 2006.257.06:58:48.29#ibcon#about to write, iclass 14, count 0 2006.257.06:58:48.29#ibcon#wrote, iclass 14, count 0 2006.257.06:58:48.29#ibcon#about to read 3, iclass 14, count 0 2006.257.06:58:48.33#ibcon#read 3, iclass 14, count 0 2006.257.06:58:48.33#ibcon#about to read 4, iclass 14, count 0 2006.257.06:58:48.33#ibcon#read 4, iclass 14, count 0 2006.257.06:58:48.33#ibcon#about to read 5, iclass 14, count 0 2006.257.06:58:48.33#ibcon#read 5, iclass 14, count 0 2006.257.06:58:48.33#ibcon#about to read 6, iclass 14, count 0 2006.257.06:58:48.33#ibcon#read 6, iclass 14, count 0 2006.257.06:58:48.33#ibcon#end of sib2, iclass 14, count 0 2006.257.06:58:48.33#ibcon#*after write, iclass 14, count 0 2006.257.06:58:48.33#ibcon#*before return 0, iclass 14, count 0 2006.257.06:58:48.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:48.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.06:58:48.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.06:58:48.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.06:58:48.33$vck44/vb=2,5 2006.257.06:58:48.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.06:58:48.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.06:58:48.33#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:48.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:48.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:48.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:48.39#ibcon#enter wrdev, iclass 16, count 2 2006.257.06:58:48.39#ibcon#first serial, iclass 16, count 2 2006.257.06:58:48.39#ibcon#enter sib2, iclass 16, count 2 2006.257.06:58:48.39#ibcon#flushed, iclass 16, count 2 2006.257.06:58:48.39#ibcon#about to write, iclass 16, count 2 2006.257.06:58:48.39#ibcon#wrote, iclass 16, count 2 2006.257.06:58:48.39#ibcon#about to read 3, iclass 16, count 2 2006.257.06:58:48.41#ibcon#read 3, iclass 16, count 2 2006.257.06:58:48.41#ibcon#about to read 4, iclass 16, count 2 2006.257.06:58:48.41#ibcon#read 4, iclass 16, count 2 2006.257.06:58:48.41#ibcon#about to read 5, iclass 16, count 2 2006.257.06:58:48.41#ibcon#read 5, iclass 16, count 2 2006.257.06:58:48.41#ibcon#about to read 6, iclass 16, count 2 2006.257.06:58:48.41#ibcon#read 6, iclass 16, count 2 2006.257.06:58:48.41#ibcon#end of sib2, iclass 16, count 2 2006.257.06:58:48.41#ibcon#*mode == 0, iclass 16, count 2 2006.257.06:58:48.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.06:58:48.41#ibcon#[27=AT02-05\r\n] 2006.257.06:58:48.41#ibcon#*before write, iclass 16, count 2 2006.257.06:58:48.41#ibcon#enter sib2, iclass 16, count 2 2006.257.06:58:48.41#ibcon#flushed, iclass 16, count 2 2006.257.06:58:48.41#ibcon#about to write, iclass 16, count 2 2006.257.06:58:48.41#ibcon#wrote, iclass 16, count 2 2006.257.06:58:48.41#ibcon#about to read 3, iclass 16, count 2 2006.257.06:58:48.44#ibcon#read 3, iclass 16, count 2 2006.257.06:58:48.44#ibcon#about to read 4, iclass 16, count 2 2006.257.06:58:48.44#ibcon#read 4, iclass 16, count 2 2006.257.06:58:48.44#ibcon#about to read 5, iclass 16, count 2 2006.257.06:58:48.44#ibcon#read 5, iclass 16, count 2 2006.257.06:58:48.44#ibcon#about to read 6, iclass 16, count 2 2006.257.06:58:48.44#ibcon#read 6, iclass 16, count 2 2006.257.06:58:48.44#ibcon#end of sib2, iclass 16, count 2 2006.257.06:58:48.44#ibcon#*after write, iclass 16, count 2 2006.257.06:58:48.44#ibcon#*before return 0, iclass 16, count 2 2006.257.06:58:48.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:48.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.06:58:48.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.06:58:48.44#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:48.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:48.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:48.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:48.56#ibcon#enter wrdev, iclass 16, count 0 2006.257.06:58:48.56#ibcon#first serial, iclass 16, count 0 2006.257.06:58:48.56#ibcon#enter sib2, iclass 16, count 0 2006.257.06:58:48.56#ibcon#flushed, iclass 16, count 0 2006.257.06:58:48.56#ibcon#about to write, iclass 16, count 0 2006.257.06:58:48.56#ibcon#wrote, iclass 16, count 0 2006.257.06:58:48.56#ibcon#about to read 3, iclass 16, count 0 2006.257.06:58:48.58#ibcon#read 3, iclass 16, count 0 2006.257.06:58:48.58#ibcon#about to read 4, iclass 16, count 0 2006.257.06:58:48.58#ibcon#read 4, iclass 16, count 0 2006.257.06:58:48.58#ibcon#about to read 5, iclass 16, count 0 2006.257.06:58:48.58#ibcon#read 5, iclass 16, count 0 2006.257.06:58:48.58#ibcon#about to read 6, iclass 16, count 0 2006.257.06:58:48.58#ibcon#read 6, iclass 16, count 0 2006.257.06:58:48.58#ibcon#end of sib2, iclass 16, count 0 2006.257.06:58:48.58#ibcon#*mode == 0, iclass 16, count 0 2006.257.06:58:48.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.06:58:48.58#ibcon#[27=USB\r\n] 2006.257.06:58:48.58#ibcon#*before write, iclass 16, count 0 2006.257.06:58:48.58#ibcon#enter sib2, iclass 16, count 0 2006.257.06:58:48.58#ibcon#flushed, iclass 16, count 0 2006.257.06:58:48.58#ibcon#about to write, iclass 16, count 0 2006.257.06:58:48.58#ibcon#wrote, iclass 16, count 0 2006.257.06:58:48.58#ibcon#about to read 3, iclass 16, count 0 2006.257.06:58:48.61#ibcon#read 3, iclass 16, count 0 2006.257.06:58:48.61#ibcon#about to read 4, iclass 16, count 0 2006.257.06:58:48.61#ibcon#read 4, iclass 16, count 0 2006.257.06:58:48.61#ibcon#about to read 5, iclass 16, count 0 2006.257.06:58:48.61#ibcon#read 5, iclass 16, count 0 2006.257.06:58:48.61#ibcon#about to read 6, iclass 16, count 0 2006.257.06:58:48.61#ibcon#read 6, iclass 16, count 0 2006.257.06:58:48.61#ibcon#end of sib2, iclass 16, count 0 2006.257.06:58:48.61#ibcon#*after write, iclass 16, count 0 2006.257.06:58:48.61#ibcon#*before return 0, iclass 16, count 0 2006.257.06:58:48.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:48.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.06:58:48.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.06:58:48.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.06:58:48.61$vck44/vblo=3,649.99 2006.257.06:58:48.61#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.06:58:48.61#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.06:58:48.61#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:48.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:48.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:48.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:48.61#ibcon#enter wrdev, iclass 18, count 0 2006.257.06:58:48.61#ibcon#first serial, iclass 18, count 0 2006.257.06:58:48.61#ibcon#enter sib2, iclass 18, count 0 2006.257.06:58:48.61#ibcon#flushed, iclass 18, count 0 2006.257.06:58:48.61#ibcon#about to write, iclass 18, count 0 2006.257.06:58:48.61#ibcon#wrote, iclass 18, count 0 2006.257.06:58:48.61#ibcon#about to read 3, iclass 18, count 0 2006.257.06:58:48.63#ibcon#read 3, iclass 18, count 0 2006.257.06:58:48.63#ibcon#about to read 4, iclass 18, count 0 2006.257.06:58:48.63#ibcon#read 4, iclass 18, count 0 2006.257.06:58:48.63#ibcon#about to read 5, iclass 18, count 0 2006.257.06:58:48.63#ibcon#read 5, iclass 18, count 0 2006.257.06:58:48.63#ibcon#about to read 6, iclass 18, count 0 2006.257.06:58:48.63#ibcon#read 6, iclass 18, count 0 2006.257.06:58:48.63#ibcon#end of sib2, iclass 18, count 0 2006.257.06:58:48.63#ibcon#*mode == 0, iclass 18, count 0 2006.257.06:58:48.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.06:58:48.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.06:58:48.63#ibcon#*before write, iclass 18, count 0 2006.257.06:58:48.63#ibcon#enter sib2, iclass 18, count 0 2006.257.06:58:48.63#ibcon#flushed, iclass 18, count 0 2006.257.06:58:48.63#ibcon#about to write, iclass 18, count 0 2006.257.06:58:48.63#ibcon#wrote, iclass 18, count 0 2006.257.06:58:48.63#ibcon#about to read 3, iclass 18, count 0 2006.257.06:58:48.67#ibcon#read 3, iclass 18, count 0 2006.257.06:58:48.67#ibcon#about to read 4, iclass 18, count 0 2006.257.06:58:48.67#ibcon#read 4, iclass 18, count 0 2006.257.06:58:48.67#ibcon#about to read 5, iclass 18, count 0 2006.257.06:58:48.67#ibcon#read 5, iclass 18, count 0 2006.257.06:58:48.67#ibcon#about to read 6, iclass 18, count 0 2006.257.06:58:48.67#ibcon#read 6, iclass 18, count 0 2006.257.06:58:48.67#ibcon#end of sib2, iclass 18, count 0 2006.257.06:58:48.67#ibcon#*after write, iclass 18, count 0 2006.257.06:58:48.67#ibcon#*before return 0, iclass 18, count 0 2006.257.06:58:48.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:48.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.06:58:48.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.06:58:48.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.06:58:48.67$vck44/vb=3,4 2006.257.06:58:48.67#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.06:58:48.67#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.06:58:48.67#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:48.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:48.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:48.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:48.73#ibcon#enter wrdev, iclass 20, count 2 2006.257.06:58:48.73#ibcon#first serial, iclass 20, count 2 2006.257.06:58:48.73#ibcon#enter sib2, iclass 20, count 2 2006.257.06:58:48.73#ibcon#flushed, iclass 20, count 2 2006.257.06:58:48.73#ibcon#about to write, iclass 20, count 2 2006.257.06:58:48.73#ibcon#wrote, iclass 20, count 2 2006.257.06:58:48.73#ibcon#about to read 3, iclass 20, count 2 2006.257.06:58:48.75#ibcon#read 3, iclass 20, count 2 2006.257.06:58:48.75#ibcon#about to read 4, iclass 20, count 2 2006.257.06:58:48.75#ibcon#read 4, iclass 20, count 2 2006.257.06:58:48.75#ibcon#about to read 5, iclass 20, count 2 2006.257.06:58:48.75#ibcon#read 5, iclass 20, count 2 2006.257.06:58:48.75#ibcon#about to read 6, iclass 20, count 2 2006.257.06:58:48.75#ibcon#read 6, iclass 20, count 2 2006.257.06:58:48.75#ibcon#end of sib2, iclass 20, count 2 2006.257.06:58:48.75#ibcon#*mode == 0, iclass 20, count 2 2006.257.06:58:48.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.06:58:48.75#ibcon#[27=AT03-04\r\n] 2006.257.06:58:48.75#ibcon#*before write, iclass 20, count 2 2006.257.06:58:48.75#ibcon#enter sib2, iclass 20, count 2 2006.257.06:58:48.75#ibcon#flushed, iclass 20, count 2 2006.257.06:58:48.75#ibcon#about to write, iclass 20, count 2 2006.257.06:58:48.75#ibcon#wrote, iclass 20, count 2 2006.257.06:58:48.75#ibcon#about to read 3, iclass 20, count 2 2006.257.06:58:48.78#ibcon#read 3, iclass 20, count 2 2006.257.06:58:48.78#ibcon#about to read 4, iclass 20, count 2 2006.257.06:58:48.78#ibcon#read 4, iclass 20, count 2 2006.257.06:58:48.78#ibcon#about to read 5, iclass 20, count 2 2006.257.06:58:48.78#ibcon#read 5, iclass 20, count 2 2006.257.06:58:48.78#ibcon#about to read 6, iclass 20, count 2 2006.257.06:58:48.78#ibcon#read 6, iclass 20, count 2 2006.257.06:58:48.78#ibcon#end of sib2, iclass 20, count 2 2006.257.06:58:48.78#ibcon#*after write, iclass 20, count 2 2006.257.06:58:48.78#ibcon#*before return 0, iclass 20, count 2 2006.257.06:58:48.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:48.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.06:58:48.78#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.06:58:48.78#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:48.78#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:48.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:48.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:48.90#ibcon#enter wrdev, iclass 20, count 0 2006.257.06:58:48.90#ibcon#first serial, iclass 20, count 0 2006.257.06:58:48.90#ibcon#enter sib2, iclass 20, count 0 2006.257.06:58:48.90#ibcon#flushed, iclass 20, count 0 2006.257.06:58:48.90#ibcon#about to write, iclass 20, count 0 2006.257.06:58:48.90#ibcon#wrote, iclass 20, count 0 2006.257.06:58:48.90#ibcon#about to read 3, iclass 20, count 0 2006.257.06:58:48.92#ibcon#read 3, iclass 20, count 0 2006.257.06:58:48.92#ibcon#about to read 4, iclass 20, count 0 2006.257.06:58:48.92#ibcon#read 4, iclass 20, count 0 2006.257.06:58:48.92#ibcon#about to read 5, iclass 20, count 0 2006.257.06:58:48.92#ibcon#read 5, iclass 20, count 0 2006.257.06:58:48.92#ibcon#about to read 6, iclass 20, count 0 2006.257.06:58:48.92#ibcon#read 6, iclass 20, count 0 2006.257.06:58:48.92#ibcon#end of sib2, iclass 20, count 0 2006.257.06:58:48.92#ibcon#*mode == 0, iclass 20, count 0 2006.257.06:58:48.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.06:58:48.92#ibcon#[27=USB\r\n] 2006.257.06:58:48.92#ibcon#*before write, iclass 20, count 0 2006.257.06:58:48.92#ibcon#enter sib2, iclass 20, count 0 2006.257.06:58:48.92#ibcon#flushed, iclass 20, count 0 2006.257.06:58:48.92#ibcon#about to write, iclass 20, count 0 2006.257.06:58:48.92#ibcon#wrote, iclass 20, count 0 2006.257.06:58:48.92#ibcon#about to read 3, iclass 20, count 0 2006.257.06:58:48.95#ibcon#read 3, iclass 20, count 0 2006.257.06:58:48.95#ibcon#about to read 4, iclass 20, count 0 2006.257.06:58:48.95#ibcon#read 4, iclass 20, count 0 2006.257.06:58:48.95#ibcon#about to read 5, iclass 20, count 0 2006.257.06:58:48.95#ibcon#read 5, iclass 20, count 0 2006.257.06:58:48.95#ibcon#about to read 6, iclass 20, count 0 2006.257.06:58:48.95#ibcon#read 6, iclass 20, count 0 2006.257.06:58:48.95#ibcon#end of sib2, iclass 20, count 0 2006.257.06:58:48.95#ibcon#*after write, iclass 20, count 0 2006.257.06:58:48.95#ibcon#*before return 0, iclass 20, count 0 2006.257.06:58:48.95#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:48.95#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.06:58:48.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.06:58:48.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.06:58:48.95$vck44/vblo=4,679.99 2006.257.06:58:48.95#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.06:58:48.95#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.06:58:48.95#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:48.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:48.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:48.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:48.95#ibcon#enter wrdev, iclass 22, count 0 2006.257.06:58:48.95#ibcon#first serial, iclass 22, count 0 2006.257.06:58:48.95#ibcon#enter sib2, iclass 22, count 0 2006.257.06:58:48.95#ibcon#flushed, iclass 22, count 0 2006.257.06:58:48.95#ibcon#about to write, iclass 22, count 0 2006.257.06:58:48.95#ibcon#wrote, iclass 22, count 0 2006.257.06:58:48.95#ibcon#about to read 3, iclass 22, count 0 2006.257.06:58:48.97#ibcon#read 3, iclass 22, count 0 2006.257.06:58:48.97#ibcon#about to read 4, iclass 22, count 0 2006.257.06:58:48.97#ibcon#read 4, iclass 22, count 0 2006.257.06:58:48.97#ibcon#about to read 5, iclass 22, count 0 2006.257.06:58:48.97#ibcon#read 5, iclass 22, count 0 2006.257.06:58:48.97#ibcon#about to read 6, iclass 22, count 0 2006.257.06:58:48.97#ibcon#read 6, iclass 22, count 0 2006.257.06:58:48.97#ibcon#end of sib2, iclass 22, count 0 2006.257.06:58:48.97#ibcon#*mode == 0, iclass 22, count 0 2006.257.06:58:48.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.06:58:48.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.06:58:48.97#ibcon#*before write, iclass 22, count 0 2006.257.06:58:48.97#ibcon#enter sib2, iclass 22, count 0 2006.257.06:58:48.97#ibcon#flushed, iclass 22, count 0 2006.257.06:58:48.97#ibcon#about to write, iclass 22, count 0 2006.257.06:58:48.97#ibcon#wrote, iclass 22, count 0 2006.257.06:58:48.97#ibcon#about to read 3, iclass 22, count 0 2006.257.06:58:49.01#ibcon#read 3, iclass 22, count 0 2006.257.06:58:49.01#ibcon#about to read 4, iclass 22, count 0 2006.257.06:58:49.01#ibcon#read 4, iclass 22, count 0 2006.257.06:58:49.01#ibcon#about to read 5, iclass 22, count 0 2006.257.06:58:49.01#ibcon#read 5, iclass 22, count 0 2006.257.06:58:49.01#ibcon#about to read 6, iclass 22, count 0 2006.257.06:58:49.01#ibcon#read 6, iclass 22, count 0 2006.257.06:58:49.01#ibcon#end of sib2, iclass 22, count 0 2006.257.06:58:49.01#ibcon#*after write, iclass 22, count 0 2006.257.06:58:49.01#ibcon#*before return 0, iclass 22, count 0 2006.257.06:58:49.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:49.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.06:58:49.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.06:58:49.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.06:58:49.01$vck44/vb=4,5 2006.257.06:58:49.01#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.06:58:49.01#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.06:58:49.01#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:49.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:49.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:49.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:49.07#ibcon#enter wrdev, iclass 24, count 2 2006.257.06:58:49.07#ibcon#first serial, iclass 24, count 2 2006.257.06:58:49.07#ibcon#enter sib2, iclass 24, count 2 2006.257.06:58:49.07#ibcon#flushed, iclass 24, count 2 2006.257.06:58:49.07#ibcon#about to write, iclass 24, count 2 2006.257.06:58:49.07#ibcon#wrote, iclass 24, count 2 2006.257.06:58:49.07#ibcon#about to read 3, iclass 24, count 2 2006.257.06:58:49.09#ibcon#read 3, iclass 24, count 2 2006.257.06:58:49.09#ibcon#about to read 4, iclass 24, count 2 2006.257.06:58:49.09#ibcon#read 4, iclass 24, count 2 2006.257.06:58:49.09#ibcon#about to read 5, iclass 24, count 2 2006.257.06:58:49.09#ibcon#read 5, iclass 24, count 2 2006.257.06:58:49.09#ibcon#about to read 6, iclass 24, count 2 2006.257.06:58:49.09#ibcon#read 6, iclass 24, count 2 2006.257.06:58:49.09#ibcon#end of sib2, iclass 24, count 2 2006.257.06:58:49.09#ibcon#*mode == 0, iclass 24, count 2 2006.257.06:58:49.09#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.06:58:49.09#ibcon#[27=AT04-05\r\n] 2006.257.06:58:49.09#ibcon#*before write, iclass 24, count 2 2006.257.06:58:49.09#ibcon#enter sib2, iclass 24, count 2 2006.257.06:58:49.09#ibcon#flushed, iclass 24, count 2 2006.257.06:58:49.09#ibcon#about to write, iclass 24, count 2 2006.257.06:58:49.09#ibcon#wrote, iclass 24, count 2 2006.257.06:58:49.09#ibcon#about to read 3, iclass 24, count 2 2006.257.06:58:49.12#ibcon#read 3, iclass 24, count 2 2006.257.06:58:49.12#ibcon#about to read 4, iclass 24, count 2 2006.257.06:58:49.12#ibcon#read 4, iclass 24, count 2 2006.257.06:58:49.12#ibcon#about to read 5, iclass 24, count 2 2006.257.06:58:49.12#ibcon#read 5, iclass 24, count 2 2006.257.06:58:49.12#ibcon#about to read 6, iclass 24, count 2 2006.257.06:58:49.12#ibcon#read 6, iclass 24, count 2 2006.257.06:58:49.12#ibcon#end of sib2, iclass 24, count 2 2006.257.06:58:49.12#ibcon#*after write, iclass 24, count 2 2006.257.06:58:49.12#ibcon#*before return 0, iclass 24, count 2 2006.257.06:58:49.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:49.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.06:58:49.12#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.06:58:49.12#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:49.12#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:49.24#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:49.24#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:49.24#ibcon#enter wrdev, iclass 24, count 0 2006.257.06:58:49.24#ibcon#first serial, iclass 24, count 0 2006.257.06:58:49.24#ibcon#enter sib2, iclass 24, count 0 2006.257.06:58:49.24#ibcon#flushed, iclass 24, count 0 2006.257.06:58:49.24#ibcon#about to write, iclass 24, count 0 2006.257.06:58:49.24#ibcon#wrote, iclass 24, count 0 2006.257.06:58:49.24#ibcon#about to read 3, iclass 24, count 0 2006.257.06:58:49.26#ibcon#read 3, iclass 24, count 0 2006.257.06:58:49.26#ibcon#about to read 4, iclass 24, count 0 2006.257.06:58:49.26#ibcon#read 4, iclass 24, count 0 2006.257.06:58:49.26#ibcon#about to read 5, iclass 24, count 0 2006.257.06:58:49.26#ibcon#read 5, iclass 24, count 0 2006.257.06:58:49.26#ibcon#about to read 6, iclass 24, count 0 2006.257.06:58:49.26#ibcon#read 6, iclass 24, count 0 2006.257.06:58:49.26#ibcon#end of sib2, iclass 24, count 0 2006.257.06:58:49.26#ibcon#*mode == 0, iclass 24, count 0 2006.257.06:58:49.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.06:58:49.26#ibcon#[27=USB\r\n] 2006.257.06:58:49.26#ibcon#*before write, iclass 24, count 0 2006.257.06:58:49.26#ibcon#enter sib2, iclass 24, count 0 2006.257.06:58:49.26#ibcon#flushed, iclass 24, count 0 2006.257.06:58:49.26#ibcon#about to write, iclass 24, count 0 2006.257.06:58:49.26#ibcon#wrote, iclass 24, count 0 2006.257.06:58:49.26#ibcon#about to read 3, iclass 24, count 0 2006.257.06:58:49.29#ibcon#read 3, iclass 24, count 0 2006.257.06:58:49.29#ibcon#about to read 4, iclass 24, count 0 2006.257.06:58:49.29#ibcon#read 4, iclass 24, count 0 2006.257.06:58:49.29#ibcon#about to read 5, iclass 24, count 0 2006.257.06:58:49.29#ibcon#read 5, iclass 24, count 0 2006.257.06:58:49.29#ibcon#about to read 6, iclass 24, count 0 2006.257.06:58:49.29#ibcon#read 6, iclass 24, count 0 2006.257.06:58:49.29#ibcon#end of sib2, iclass 24, count 0 2006.257.06:58:49.29#ibcon#*after write, iclass 24, count 0 2006.257.06:58:49.29#ibcon#*before return 0, iclass 24, count 0 2006.257.06:58:49.29#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:49.29#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.06:58:49.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.06:58:49.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.06:58:49.29$vck44/vblo=5,709.99 2006.257.06:58:49.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.06:58:49.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.06:58:49.29#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:49.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:49.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:49.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:49.29#ibcon#enter wrdev, iclass 26, count 0 2006.257.06:58:49.29#ibcon#first serial, iclass 26, count 0 2006.257.06:58:49.29#ibcon#enter sib2, iclass 26, count 0 2006.257.06:58:49.29#ibcon#flushed, iclass 26, count 0 2006.257.06:58:49.29#ibcon#about to write, iclass 26, count 0 2006.257.06:58:49.29#ibcon#wrote, iclass 26, count 0 2006.257.06:58:49.29#ibcon#about to read 3, iclass 26, count 0 2006.257.06:58:49.31#ibcon#read 3, iclass 26, count 0 2006.257.06:58:49.31#ibcon#about to read 4, iclass 26, count 0 2006.257.06:58:49.31#ibcon#read 4, iclass 26, count 0 2006.257.06:58:49.31#ibcon#about to read 5, iclass 26, count 0 2006.257.06:58:49.31#ibcon#read 5, iclass 26, count 0 2006.257.06:58:49.31#ibcon#about to read 6, iclass 26, count 0 2006.257.06:58:49.31#ibcon#read 6, iclass 26, count 0 2006.257.06:58:49.31#ibcon#end of sib2, iclass 26, count 0 2006.257.06:58:49.31#ibcon#*mode == 0, iclass 26, count 0 2006.257.06:58:49.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.06:58:49.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.06:58:49.31#ibcon#*before write, iclass 26, count 0 2006.257.06:58:49.31#ibcon#enter sib2, iclass 26, count 0 2006.257.06:58:49.31#ibcon#flushed, iclass 26, count 0 2006.257.06:58:49.31#ibcon#about to write, iclass 26, count 0 2006.257.06:58:49.31#ibcon#wrote, iclass 26, count 0 2006.257.06:58:49.31#ibcon#about to read 3, iclass 26, count 0 2006.257.06:58:49.35#ibcon#read 3, iclass 26, count 0 2006.257.06:58:49.35#ibcon#about to read 4, iclass 26, count 0 2006.257.06:58:49.35#ibcon#read 4, iclass 26, count 0 2006.257.06:58:49.35#ibcon#about to read 5, iclass 26, count 0 2006.257.06:58:49.35#ibcon#read 5, iclass 26, count 0 2006.257.06:58:49.35#ibcon#about to read 6, iclass 26, count 0 2006.257.06:58:49.35#ibcon#read 6, iclass 26, count 0 2006.257.06:58:49.35#ibcon#end of sib2, iclass 26, count 0 2006.257.06:58:49.35#ibcon#*after write, iclass 26, count 0 2006.257.06:58:49.35#ibcon#*before return 0, iclass 26, count 0 2006.257.06:58:49.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:49.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.06:58:49.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.06:58:49.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.06:58:49.35$vck44/vb=5,4 2006.257.06:58:49.35#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.06:58:49.35#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.06:58:49.35#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:49.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:49.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:49.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:49.41#ibcon#enter wrdev, iclass 28, count 2 2006.257.06:58:49.41#ibcon#first serial, iclass 28, count 2 2006.257.06:58:49.41#ibcon#enter sib2, iclass 28, count 2 2006.257.06:58:49.41#ibcon#flushed, iclass 28, count 2 2006.257.06:58:49.41#ibcon#about to write, iclass 28, count 2 2006.257.06:58:49.41#ibcon#wrote, iclass 28, count 2 2006.257.06:58:49.41#ibcon#about to read 3, iclass 28, count 2 2006.257.06:58:49.43#ibcon#read 3, iclass 28, count 2 2006.257.06:58:49.43#ibcon#about to read 4, iclass 28, count 2 2006.257.06:58:49.43#ibcon#read 4, iclass 28, count 2 2006.257.06:58:49.43#ibcon#about to read 5, iclass 28, count 2 2006.257.06:58:49.43#ibcon#read 5, iclass 28, count 2 2006.257.06:58:49.43#ibcon#about to read 6, iclass 28, count 2 2006.257.06:58:49.43#ibcon#read 6, iclass 28, count 2 2006.257.06:58:49.43#ibcon#end of sib2, iclass 28, count 2 2006.257.06:58:49.43#ibcon#*mode == 0, iclass 28, count 2 2006.257.06:58:49.43#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.06:58:49.43#ibcon#[27=AT05-04\r\n] 2006.257.06:58:49.43#ibcon#*before write, iclass 28, count 2 2006.257.06:58:49.43#ibcon#enter sib2, iclass 28, count 2 2006.257.06:58:49.43#ibcon#flushed, iclass 28, count 2 2006.257.06:58:49.43#ibcon#about to write, iclass 28, count 2 2006.257.06:58:49.43#ibcon#wrote, iclass 28, count 2 2006.257.06:58:49.43#ibcon#about to read 3, iclass 28, count 2 2006.257.06:58:49.46#ibcon#read 3, iclass 28, count 2 2006.257.06:58:49.46#ibcon#about to read 4, iclass 28, count 2 2006.257.06:58:49.46#ibcon#read 4, iclass 28, count 2 2006.257.06:58:49.46#ibcon#about to read 5, iclass 28, count 2 2006.257.06:58:49.46#ibcon#read 5, iclass 28, count 2 2006.257.06:58:49.46#ibcon#about to read 6, iclass 28, count 2 2006.257.06:58:49.46#ibcon#read 6, iclass 28, count 2 2006.257.06:58:49.46#ibcon#end of sib2, iclass 28, count 2 2006.257.06:58:49.46#ibcon#*after write, iclass 28, count 2 2006.257.06:58:49.46#ibcon#*before return 0, iclass 28, count 2 2006.257.06:58:49.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:49.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.06:58:49.46#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.06:58:49.46#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:49.46#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:49.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:49.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:49.58#ibcon#enter wrdev, iclass 28, count 0 2006.257.06:58:49.58#ibcon#first serial, iclass 28, count 0 2006.257.06:58:49.58#ibcon#enter sib2, iclass 28, count 0 2006.257.06:58:49.58#ibcon#flushed, iclass 28, count 0 2006.257.06:58:49.58#ibcon#about to write, iclass 28, count 0 2006.257.06:58:49.58#ibcon#wrote, iclass 28, count 0 2006.257.06:58:49.58#ibcon#about to read 3, iclass 28, count 0 2006.257.06:58:49.60#ibcon#read 3, iclass 28, count 0 2006.257.06:58:49.60#ibcon#about to read 4, iclass 28, count 0 2006.257.06:58:49.60#ibcon#read 4, iclass 28, count 0 2006.257.06:58:49.60#ibcon#about to read 5, iclass 28, count 0 2006.257.06:58:49.60#ibcon#read 5, iclass 28, count 0 2006.257.06:58:49.60#ibcon#about to read 6, iclass 28, count 0 2006.257.06:58:49.60#ibcon#read 6, iclass 28, count 0 2006.257.06:58:49.60#ibcon#end of sib2, iclass 28, count 0 2006.257.06:58:49.60#ibcon#*mode == 0, iclass 28, count 0 2006.257.06:58:49.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.06:58:49.60#ibcon#[27=USB\r\n] 2006.257.06:58:49.60#ibcon#*before write, iclass 28, count 0 2006.257.06:58:49.60#ibcon#enter sib2, iclass 28, count 0 2006.257.06:58:49.60#ibcon#flushed, iclass 28, count 0 2006.257.06:58:49.60#ibcon#about to write, iclass 28, count 0 2006.257.06:58:49.60#ibcon#wrote, iclass 28, count 0 2006.257.06:58:49.60#ibcon#about to read 3, iclass 28, count 0 2006.257.06:58:49.63#ibcon#read 3, iclass 28, count 0 2006.257.06:58:49.63#ibcon#about to read 4, iclass 28, count 0 2006.257.06:58:49.63#ibcon#read 4, iclass 28, count 0 2006.257.06:58:49.63#ibcon#about to read 5, iclass 28, count 0 2006.257.06:58:49.63#ibcon#read 5, iclass 28, count 0 2006.257.06:58:49.63#ibcon#about to read 6, iclass 28, count 0 2006.257.06:58:49.63#ibcon#read 6, iclass 28, count 0 2006.257.06:58:49.63#ibcon#end of sib2, iclass 28, count 0 2006.257.06:58:49.63#ibcon#*after write, iclass 28, count 0 2006.257.06:58:49.63#ibcon#*before return 0, iclass 28, count 0 2006.257.06:58:49.63#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:49.63#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.06:58:49.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.06:58:49.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.06:58:49.63$vck44/vblo=6,719.99 2006.257.06:58:49.63#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.06:58:49.63#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.06:58:49.63#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:49.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:49.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:49.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:49.63#ibcon#enter wrdev, iclass 30, count 0 2006.257.06:58:49.63#ibcon#first serial, iclass 30, count 0 2006.257.06:58:49.63#ibcon#enter sib2, iclass 30, count 0 2006.257.06:58:49.63#ibcon#flushed, iclass 30, count 0 2006.257.06:58:49.63#ibcon#about to write, iclass 30, count 0 2006.257.06:58:49.63#ibcon#wrote, iclass 30, count 0 2006.257.06:58:49.63#ibcon#about to read 3, iclass 30, count 0 2006.257.06:58:49.65#ibcon#read 3, iclass 30, count 0 2006.257.06:58:49.65#ibcon#about to read 4, iclass 30, count 0 2006.257.06:58:49.65#ibcon#read 4, iclass 30, count 0 2006.257.06:58:49.65#ibcon#about to read 5, iclass 30, count 0 2006.257.06:58:49.65#ibcon#read 5, iclass 30, count 0 2006.257.06:58:49.65#ibcon#about to read 6, iclass 30, count 0 2006.257.06:58:49.65#ibcon#read 6, iclass 30, count 0 2006.257.06:58:49.65#ibcon#end of sib2, iclass 30, count 0 2006.257.06:58:49.65#ibcon#*mode == 0, iclass 30, count 0 2006.257.06:58:49.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.06:58:49.65#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.06:58:49.65#ibcon#*before write, iclass 30, count 0 2006.257.06:58:49.65#ibcon#enter sib2, iclass 30, count 0 2006.257.06:58:49.65#ibcon#flushed, iclass 30, count 0 2006.257.06:58:49.65#ibcon#about to write, iclass 30, count 0 2006.257.06:58:49.65#ibcon#wrote, iclass 30, count 0 2006.257.06:58:49.65#ibcon#about to read 3, iclass 30, count 0 2006.257.06:58:49.69#ibcon#read 3, iclass 30, count 0 2006.257.06:58:49.69#ibcon#about to read 4, iclass 30, count 0 2006.257.06:58:49.69#ibcon#read 4, iclass 30, count 0 2006.257.06:58:49.69#ibcon#about to read 5, iclass 30, count 0 2006.257.06:58:49.69#ibcon#read 5, iclass 30, count 0 2006.257.06:58:49.69#ibcon#about to read 6, iclass 30, count 0 2006.257.06:58:49.69#ibcon#read 6, iclass 30, count 0 2006.257.06:58:49.69#ibcon#end of sib2, iclass 30, count 0 2006.257.06:58:49.69#ibcon#*after write, iclass 30, count 0 2006.257.06:58:49.69#ibcon#*before return 0, iclass 30, count 0 2006.257.06:58:49.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:49.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.06:58:49.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.06:58:49.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.06:58:49.69$vck44/vb=6,4 2006.257.06:58:49.69#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.06:58:49.69#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.06:58:49.69#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:49.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:49.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:49.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:49.75#ibcon#enter wrdev, iclass 32, count 2 2006.257.06:58:49.75#ibcon#first serial, iclass 32, count 2 2006.257.06:58:49.75#ibcon#enter sib2, iclass 32, count 2 2006.257.06:58:49.75#ibcon#flushed, iclass 32, count 2 2006.257.06:58:49.75#ibcon#about to write, iclass 32, count 2 2006.257.06:58:49.75#ibcon#wrote, iclass 32, count 2 2006.257.06:58:49.75#ibcon#about to read 3, iclass 32, count 2 2006.257.06:58:49.77#ibcon#read 3, iclass 32, count 2 2006.257.06:58:49.77#ibcon#about to read 4, iclass 32, count 2 2006.257.06:58:49.77#ibcon#read 4, iclass 32, count 2 2006.257.06:58:49.77#ibcon#about to read 5, iclass 32, count 2 2006.257.06:58:49.77#ibcon#read 5, iclass 32, count 2 2006.257.06:58:49.77#ibcon#about to read 6, iclass 32, count 2 2006.257.06:58:49.77#ibcon#read 6, iclass 32, count 2 2006.257.06:58:49.77#ibcon#end of sib2, iclass 32, count 2 2006.257.06:58:49.77#ibcon#*mode == 0, iclass 32, count 2 2006.257.06:58:49.77#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.06:58:49.77#ibcon#[27=AT06-04\r\n] 2006.257.06:58:49.77#ibcon#*before write, iclass 32, count 2 2006.257.06:58:49.77#ibcon#enter sib2, iclass 32, count 2 2006.257.06:58:49.77#ibcon#flushed, iclass 32, count 2 2006.257.06:58:49.77#ibcon#about to write, iclass 32, count 2 2006.257.06:58:49.77#ibcon#wrote, iclass 32, count 2 2006.257.06:58:49.77#ibcon#about to read 3, iclass 32, count 2 2006.257.06:58:49.80#ibcon#read 3, iclass 32, count 2 2006.257.06:58:49.80#ibcon#about to read 4, iclass 32, count 2 2006.257.06:58:49.80#ibcon#read 4, iclass 32, count 2 2006.257.06:58:49.80#ibcon#about to read 5, iclass 32, count 2 2006.257.06:58:49.80#ibcon#read 5, iclass 32, count 2 2006.257.06:58:49.80#ibcon#about to read 6, iclass 32, count 2 2006.257.06:58:49.80#ibcon#read 6, iclass 32, count 2 2006.257.06:58:49.80#ibcon#end of sib2, iclass 32, count 2 2006.257.06:58:49.80#ibcon#*after write, iclass 32, count 2 2006.257.06:58:49.80#ibcon#*before return 0, iclass 32, count 2 2006.257.06:58:49.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:49.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.06:58:49.80#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.06:58:49.80#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:49.80#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:49.92#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:49.92#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:49.92#ibcon#enter wrdev, iclass 32, count 0 2006.257.06:58:49.92#ibcon#first serial, iclass 32, count 0 2006.257.06:58:49.92#ibcon#enter sib2, iclass 32, count 0 2006.257.06:58:49.92#ibcon#flushed, iclass 32, count 0 2006.257.06:58:49.92#ibcon#about to write, iclass 32, count 0 2006.257.06:58:49.92#ibcon#wrote, iclass 32, count 0 2006.257.06:58:49.92#ibcon#about to read 3, iclass 32, count 0 2006.257.06:58:49.94#ibcon#read 3, iclass 32, count 0 2006.257.06:58:49.94#ibcon#about to read 4, iclass 32, count 0 2006.257.06:58:49.94#ibcon#read 4, iclass 32, count 0 2006.257.06:58:49.94#ibcon#about to read 5, iclass 32, count 0 2006.257.06:58:49.94#ibcon#read 5, iclass 32, count 0 2006.257.06:58:49.94#ibcon#about to read 6, iclass 32, count 0 2006.257.06:58:49.94#ibcon#read 6, iclass 32, count 0 2006.257.06:58:49.94#ibcon#end of sib2, iclass 32, count 0 2006.257.06:58:49.94#ibcon#*mode == 0, iclass 32, count 0 2006.257.06:58:49.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.06:58:49.94#ibcon#[27=USB\r\n] 2006.257.06:58:49.94#ibcon#*before write, iclass 32, count 0 2006.257.06:58:49.94#ibcon#enter sib2, iclass 32, count 0 2006.257.06:58:49.94#ibcon#flushed, iclass 32, count 0 2006.257.06:58:49.94#ibcon#about to write, iclass 32, count 0 2006.257.06:58:49.94#ibcon#wrote, iclass 32, count 0 2006.257.06:58:49.94#ibcon#about to read 3, iclass 32, count 0 2006.257.06:58:49.97#ibcon#read 3, iclass 32, count 0 2006.257.06:58:49.97#ibcon#about to read 4, iclass 32, count 0 2006.257.06:58:49.97#ibcon#read 4, iclass 32, count 0 2006.257.06:58:49.97#ibcon#about to read 5, iclass 32, count 0 2006.257.06:58:49.97#ibcon#read 5, iclass 32, count 0 2006.257.06:58:49.97#ibcon#about to read 6, iclass 32, count 0 2006.257.06:58:49.97#ibcon#read 6, iclass 32, count 0 2006.257.06:58:49.97#ibcon#end of sib2, iclass 32, count 0 2006.257.06:58:49.97#ibcon#*after write, iclass 32, count 0 2006.257.06:58:49.97#ibcon#*before return 0, iclass 32, count 0 2006.257.06:58:49.97#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:49.97#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.06:58:49.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.06:58:49.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.06:58:49.97$vck44/vblo=7,734.99 2006.257.06:58:49.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.06:58:49.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.06:58:49.97#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:49.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:49.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:49.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:49.97#ibcon#enter wrdev, iclass 34, count 0 2006.257.06:58:49.97#ibcon#first serial, iclass 34, count 0 2006.257.06:58:49.97#ibcon#enter sib2, iclass 34, count 0 2006.257.06:58:49.97#ibcon#flushed, iclass 34, count 0 2006.257.06:58:49.97#ibcon#about to write, iclass 34, count 0 2006.257.06:58:49.97#ibcon#wrote, iclass 34, count 0 2006.257.06:58:49.97#ibcon#about to read 3, iclass 34, count 0 2006.257.06:58:49.99#ibcon#read 3, iclass 34, count 0 2006.257.06:58:49.99#ibcon#about to read 4, iclass 34, count 0 2006.257.06:58:49.99#ibcon#read 4, iclass 34, count 0 2006.257.06:58:49.99#ibcon#about to read 5, iclass 34, count 0 2006.257.06:58:49.99#ibcon#read 5, iclass 34, count 0 2006.257.06:58:49.99#ibcon#about to read 6, iclass 34, count 0 2006.257.06:58:49.99#ibcon#read 6, iclass 34, count 0 2006.257.06:58:49.99#ibcon#end of sib2, iclass 34, count 0 2006.257.06:58:49.99#ibcon#*mode == 0, iclass 34, count 0 2006.257.06:58:49.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.06:58:49.99#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.06:58:49.99#ibcon#*before write, iclass 34, count 0 2006.257.06:58:49.99#ibcon#enter sib2, iclass 34, count 0 2006.257.06:58:49.99#ibcon#flushed, iclass 34, count 0 2006.257.06:58:49.99#ibcon#about to write, iclass 34, count 0 2006.257.06:58:49.99#ibcon#wrote, iclass 34, count 0 2006.257.06:58:49.99#ibcon#about to read 3, iclass 34, count 0 2006.257.06:58:50.03#ibcon#read 3, iclass 34, count 0 2006.257.06:58:50.03#ibcon#about to read 4, iclass 34, count 0 2006.257.06:58:50.03#ibcon#read 4, iclass 34, count 0 2006.257.06:58:50.03#ibcon#about to read 5, iclass 34, count 0 2006.257.06:58:50.03#ibcon#read 5, iclass 34, count 0 2006.257.06:58:50.03#ibcon#about to read 6, iclass 34, count 0 2006.257.06:58:50.03#ibcon#read 6, iclass 34, count 0 2006.257.06:58:50.03#ibcon#end of sib2, iclass 34, count 0 2006.257.06:58:50.03#ibcon#*after write, iclass 34, count 0 2006.257.06:58:50.03#ibcon#*before return 0, iclass 34, count 0 2006.257.06:58:50.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:50.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.06:58:50.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.06:58:50.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.06:58:50.03$vck44/vb=7,4 2006.257.06:58:50.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.06:58:50.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.06:58:50.03#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:50.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:50.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:50.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:50.09#ibcon#enter wrdev, iclass 36, count 2 2006.257.06:58:50.09#ibcon#first serial, iclass 36, count 2 2006.257.06:58:50.09#ibcon#enter sib2, iclass 36, count 2 2006.257.06:58:50.09#ibcon#flushed, iclass 36, count 2 2006.257.06:58:50.09#ibcon#about to write, iclass 36, count 2 2006.257.06:58:50.09#ibcon#wrote, iclass 36, count 2 2006.257.06:58:50.09#ibcon#about to read 3, iclass 36, count 2 2006.257.06:58:50.11#ibcon#read 3, iclass 36, count 2 2006.257.06:58:50.11#ibcon#about to read 4, iclass 36, count 2 2006.257.06:58:50.11#ibcon#read 4, iclass 36, count 2 2006.257.06:58:50.11#ibcon#about to read 5, iclass 36, count 2 2006.257.06:58:50.11#ibcon#read 5, iclass 36, count 2 2006.257.06:58:50.11#ibcon#about to read 6, iclass 36, count 2 2006.257.06:58:50.11#ibcon#read 6, iclass 36, count 2 2006.257.06:58:50.11#ibcon#end of sib2, iclass 36, count 2 2006.257.06:58:50.11#ibcon#*mode == 0, iclass 36, count 2 2006.257.06:58:50.11#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.06:58:50.11#ibcon#[27=AT07-04\r\n] 2006.257.06:58:50.11#ibcon#*before write, iclass 36, count 2 2006.257.06:58:50.11#ibcon#enter sib2, iclass 36, count 2 2006.257.06:58:50.11#ibcon#flushed, iclass 36, count 2 2006.257.06:58:50.11#ibcon#about to write, iclass 36, count 2 2006.257.06:58:50.11#ibcon#wrote, iclass 36, count 2 2006.257.06:58:50.11#ibcon#about to read 3, iclass 36, count 2 2006.257.06:58:50.14#ibcon#read 3, iclass 36, count 2 2006.257.06:58:50.14#ibcon#about to read 4, iclass 36, count 2 2006.257.06:58:50.14#ibcon#read 4, iclass 36, count 2 2006.257.06:58:50.14#ibcon#about to read 5, iclass 36, count 2 2006.257.06:58:50.14#ibcon#read 5, iclass 36, count 2 2006.257.06:58:50.14#ibcon#about to read 6, iclass 36, count 2 2006.257.06:58:50.14#ibcon#read 6, iclass 36, count 2 2006.257.06:58:50.14#ibcon#end of sib2, iclass 36, count 2 2006.257.06:58:50.14#ibcon#*after write, iclass 36, count 2 2006.257.06:58:50.14#ibcon#*before return 0, iclass 36, count 2 2006.257.06:58:50.14#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:50.14#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.06:58:50.14#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.06:58:50.14#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:50.14#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:50.26#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:50.26#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:50.26#ibcon#enter wrdev, iclass 36, count 0 2006.257.06:58:50.26#ibcon#first serial, iclass 36, count 0 2006.257.06:58:50.26#ibcon#enter sib2, iclass 36, count 0 2006.257.06:58:50.26#ibcon#flushed, iclass 36, count 0 2006.257.06:58:50.26#ibcon#about to write, iclass 36, count 0 2006.257.06:58:50.26#ibcon#wrote, iclass 36, count 0 2006.257.06:58:50.26#ibcon#about to read 3, iclass 36, count 0 2006.257.06:58:50.28#ibcon#read 3, iclass 36, count 0 2006.257.06:58:50.28#ibcon#about to read 4, iclass 36, count 0 2006.257.06:58:50.28#ibcon#read 4, iclass 36, count 0 2006.257.06:58:50.28#ibcon#about to read 5, iclass 36, count 0 2006.257.06:58:50.28#ibcon#read 5, iclass 36, count 0 2006.257.06:58:50.28#ibcon#about to read 6, iclass 36, count 0 2006.257.06:58:50.28#ibcon#read 6, iclass 36, count 0 2006.257.06:58:50.28#ibcon#end of sib2, iclass 36, count 0 2006.257.06:58:50.28#ibcon#*mode == 0, iclass 36, count 0 2006.257.06:58:50.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.06:58:50.28#ibcon#[27=USB\r\n] 2006.257.06:58:50.28#ibcon#*before write, iclass 36, count 0 2006.257.06:58:50.28#ibcon#enter sib2, iclass 36, count 0 2006.257.06:58:50.28#ibcon#flushed, iclass 36, count 0 2006.257.06:58:50.28#ibcon#about to write, iclass 36, count 0 2006.257.06:58:50.28#ibcon#wrote, iclass 36, count 0 2006.257.06:58:50.28#ibcon#about to read 3, iclass 36, count 0 2006.257.06:58:50.31#ibcon#read 3, iclass 36, count 0 2006.257.06:58:50.31#ibcon#about to read 4, iclass 36, count 0 2006.257.06:58:50.31#ibcon#read 4, iclass 36, count 0 2006.257.06:58:50.31#ibcon#about to read 5, iclass 36, count 0 2006.257.06:58:50.31#ibcon#read 5, iclass 36, count 0 2006.257.06:58:50.31#ibcon#about to read 6, iclass 36, count 0 2006.257.06:58:50.31#ibcon#read 6, iclass 36, count 0 2006.257.06:58:50.31#ibcon#end of sib2, iclass 36, count 0 2006.257.06:58:50.31#ibcon#*after write, iclass 36, count 0 2006.257.06:58:50.31#ibcon#*before return 0, iclass 36, count 0 2006.257.06:58:50.31#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:50.31#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.06:58:50.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.06:58:50.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.06:58:50.31$vck44/vblo=8,744.99 2006.257.06:58:50.31#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.06:58:50.31#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.06:58:50.31#ibcon#ireg 17 cls_cnt 0 2006.257.06:58:50.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:50.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:50.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:50.31#ibcon#enter wrdev, iclass 38, count 0 2006.257.06:58:50.31#ibcon#first serial, iclass 38, count 0 2006.257.06:58:50.31#ibcon#enter sib2, iclass 38, count 0 2006.257.06:58:50.31#ibcon#flushed, iclass 38, count 0 2006.257.06:58:50.31#ibcon#about to write, iclass 38, count 0 2006.257.06:58:50.31#ibcon#wrote, iclass 38, count 0 2006.257.06:58:50.31#ibcon#about to read 3, iclass 38, count 0 2006.257.06:58:50.33#ibcon#read 3, iclass 38, count 0 2006.257.06:58:50.33#ibcon#about to read 4, iclass 38, count 0 2006.257.06:58:50.33#ibcon#read 4, iclass 38, count 0 2006.257.06:58:50.33#ibcon#about to read 5, iclass 38, count 0 2006.257.06:58:50.33#ibcon#read 5, iclass 38, count 0 2006.257.06:58:50.33#ibcon#about to read 6, iclass 38, count 0 2006.257.06:58:50.33#ibcon#read 6, iclass 38, count 0 2006.257.06:58:50.33#ibcon#end of sib2, iclass 38, count 0 2006.257.06:58:50.33#ibcon#*mode == 0, iclass 38, count 0 2006.257.06:58:50.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.06:58:50.33#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.06:58:50.33#ibcon#*before write, iclass 38, count 0 2006.257.06:58:50.33#ibcon#enter sib2, iclass 38, count 0 2006.257.06:58:50.33#ibcon#flushed, iclass 38, count 0 2006.257.06:58:50.33#ibcon#about to write, iclass 38, count 0 2006.257.06:58:50.33#ibcon#wrote, iclass 38, count 0 2006.257.06:58:50.33#ibcon#about to read 3, iclass 38, count 0 2006.257.06:58:50.37#ibcon#read 3, iclass 38, count 0 2006.257.06:58:50.37#ibcon#about to read 4, iclass 38, count 0 2006.257.06:58:50.37#ibcon#read 4, iclass 38, count 0 2006.257.06:58:50.37#ibcon#about to read 5, iclass 38, count 0 2006.257.06:58:50.37#ibcon#read 5, iclass 38, count 0 2006.257.06:58:50.37#ibcon#about to read 6, iclass 38, count 0 2006.257.06:58:50.37#ibcon#read 6, iclass 38, count 0 2006.257.06:58:50.37#ibcon#end of sib2, iclass 38, count 0 2006.257.06:58:50.37#ibcon#*after write, iclass 38, count 0 2006.257.06:58:50.37#ibcon#*before return 0, iclass 38, count 0 2006.257.06:58:50.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:50.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.06:58:50.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.06:58:50.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.06:58:50.37$vck44/vb=8,4 2006.257.06:58:50.37#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.06:58:50.37#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.06:58:50.37#ibcon#ireg 11 cls_cnt 2 2006.257.06:58:50.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:50.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:50.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:50.43#ibcon#enter wrdev, iclass 40, count 2 2006.257.06:58:50.43#ibcon#first serial, iclass 40, count 2 2006.257.06:58:50.43#ibcon#enter sib2, iclass 40, count 2 2006.257.06:58:50.43#ibcon#flushed, iclass 40, count 2 2006.257.06:58:50.43#ibcon#about to write, iclass 40, count 2 2006.257.06:58:50.43#ibcon#wrote, iclass 40, count 2 2006.257.06:58:50.43#ibcon#about to read 3, iclass 40, count 2 2006.257.06:58:50.45#ibcon#read 3, iclass 40, count 2 2006.257.06:58:50.45#ibcon#about to read 4, iclass 40, count 2 2006.257.06:58:50.45#ibcon#read 4, iclass 40, count 2 2006.257.06:58:50.45#ibcon#about to read 5, iclass 40, count 2 2006.257.06:58:50.45#ibcon#read 5, iclass 40, count 2 2006.257.06:58:50.45#ibcon#about to read 6, iclass 40, count 2 2006.257.06:58:50.45#ibcon#read 6, iclass 40, count 2 2006.257.06:58:50.45#ibcon#end of sib2, iclass 40, count 2 2006.257.06:58:50.45#ibcon#*mode == 0, iclass 40, count 2 2006.257.06:58:50.45#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.06:58:50.45#ibcon#[27=AT08-04\r\n] 2006.257.06:58:50.45#ibcon#*before write, iclass 40, count 2 2006.257.06:58:50.45#ibcon#enter sib2, iclass 40, count 2 2006.257.06:58:50.45#ibcon#flushed, iclass 40, count 2 2006.257.06:58:50.45#ibcon#about to write, iclass 40, count 2 2006.257.06:58:50.45#ibcon#wrote, iclass 40, count 2 2006.257.06:58:50.45#ibcon#about to read 3, iclass 40, count 2 2006.257.06:58:50.48#ibcon#read 3, iclass 40, count 2 2006.257.06:58:50.48#ibcon#about to read 4, iclass 40, count 2 2006.257.06:58:50.48#ibcon#read 4, iclass 40, count 2 2006.257.06:58:50.48#ibcon#about to read 5, iclass 40, count 2 2006.257.06:58:50.48#ibcon#read 5, iclass 40, count 2 2006.257.06:58:50.48#ibcon#about to read 6, iclass 40, count 2 2006.257.06:58:50.48#ibcon#read 6, iclass 40, count 2 2006.257.06:58:50.48#ibcon#end of sib2, iclass 40, count 2 2006.257.06:58:50.48#ibcon#*after write, iclass 40, count 2 2006.257.06:58:50.48#ibcon#*before return 0, iclass 40, count 2 2006.257.06:58:50.48#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:50.48#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.06:58:50.48#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.06:58:50.48#ibcon#ireg 7 cls_cnt 0 2006.257.06:58:50.48#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:50.60#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:50.60#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:50.60#ibcon#enter wrdev, iclass 40, count 0 2006.257.06:58:50.60#ibcon#first serial, iclass 40, count 0 2006.257.06:58:50.60#ibcon#enter sib2, iclass 40, count 0 2006.257.06:58:50.60#ibcon#flushed, iclass 40, count 0 2006.257.06:58:50.60#ibcon#about to write, iclass 40, count 0 2006.257.06:58:50.60#ibcon#wrote, iclass 40, count 0 2006.257.06:58:50.60#ibcon#about to read 3, iclass 40, count 0 2006.257.06:58:50.62#ibcon#read 3, iclass 40, count 0 2006.257.06:58:50.62#ibcon#about to read 4, iclass 40, count 0 2006.257.06:58:50.62#ibcon#read 4, iclass 40, count 0 2006.257.06:58:50.62#ibcon#about to read 5, iclass 40, count 0 2006.257.06:58:50.62#ibcon#read 5, iclass 40, count 0 2006.257.06:58:50.62#ibcon#about to read 6, iclass 40, count 0 2006.257.06:58:50.62#ibcon#read 6, iclass 40, count 0 2006.257.06:58:50.62#ibcon#end of sib2, iclass 40, count 0 2006.257.06:58:50.62#ibcon#*mode == 0, iclass 40, count 0 2006.257.06:58:50.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.06:58:50.62#ibcon#[27=USB\r\n] 2006.257.06:58:50.62#ibcon#*before write, iclass 40, count 0 2006.257.06:58:50.62#ibcon#enter sib2, iclass 40, count 0 2006.257.06:58:50.62#ibcon#flushed, iclass 40, count 0 2006.257.06:58:50.62#ibcon#about to write, iclass 40, count 0 2006.257.06:58:50.62#ibcon#wrote, iclass 40, count 0 2006.257.06:58:50.62#ibcon#about to read 3, iclass 40, count 0 2006.257.06:58:50.65#ibcon#read 3, iclass 40, count 0 2006.257.06:58:50.65#ibcon#about to read 4, iclass 40, count 0 2006.257.06:58:50.65#ibcon#read 4, iclass 40, count 0 2006.257.06:58:50.65#ibcon#about to read 5, iclass 40, count 0 2006.257.06:58:50.65#ibcon#read 5, iclass 40, count 0 2006.257.06:58:50.65#ibcon#about to read 6, iclass 40, count 0 2006.257.06:58:50.65#ibcon#read 6, iclass 40, count 0 2006.257.06:58:50.65#ibcon#end of sib2, iclass 40, count 0 2006.257.06:58:50.65#ibcon#*after write, iclass 40, count 0 2006.257.06:58:50.65#ibcon#*before return 0, iclass 40, count 0 2006.257.06:58:50.65#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:50.65#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.06:58:50.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.06:58:50.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.06:58:50.65$vck44/vabw=wide 2006.257.06:58:50.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.06:58:50.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.06:58:50.65#ibcon#ireg 8 cls_cnt 0 2006.257.06:58:50.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:50.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:50.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:50.65#ibcon#enter wrdev, iclass 4, count 0 2006.257.06:58:50.65#ibcon#first serial, iclass 4, count 0 2006.257.06:58:50.65#ibcon#enter sib2, iclass 4, count 0 2006.257.06:58:50.65#ibcon#flushed, iclass 4, count 0 2006.257.06:58:50.65#ibcon#about to write, iclass 4, count 0 2006.257.06:58:50.65#ibcon#wrote, iclass 4, count 0 2006.257.06:58:50.65#ibcon#about to read 3, iclass 4, count 0 2006.257.06:58:50.67#ibcon#read 3, iclass 4, count 0 2006.257.06:58:50.67#ibcon#about to read 4, iclass 4, count 0 2006.257.06:58:50.67#ibcon#read 4, iclass 4, count 0 2006.257.06:58:50.67#ibcon#about to read 5, iclass 4, count 0 2006.257.06:58:50.67#ibcon#read 5, iclass 4, count 0 2006.257.06:58:50.67#ibcon#about to read 6, iclass 4, count 0 2006.257.06:58:50.67#ibcon#read 6, iclass 4, count 0 2006.257.06:58:50.67#ibcon#end of sib2, iclass 4, count 0 2006.257.06:58:50.67#ibcon#*mode == 0, iclass 4, count 0 2006.257.06:58:50.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.06:58:50.67#ibcon#[25=BW32\r\n] 2006.257.06:58:50.67#ibcon#*before write, iclass 4, count 0 2006.257.06:58:50.67#ibcon#enter sib2, iclass 4, count 0 2006.257.06:58:50.67#ibcon#flushed, iclass 4, count 0 2006.257.06:58:50.67#ibcon#about to write, iclass 4, count 0 2006.257.06:58:50.67#ibcon#wrote, iclass 4, count 0 2006.257.06:58:50.67#ibcon#about to read 3, iclass 4, count 0 2006.257.06:58:50.70#ibcon#read 3, iclass 4, count 0 2006.257.06:58:50.70#ibcon#about to read 4, iclass 4, count 0 2006.257.06:58:50.70#ibcon#read 4, iclass 4, count 0 2006.257.06:58:50.70#ibcon#about to read 5, iclass 4, count 0 2006.257.06:58:50.70#ibcon#read 5, iclass 4, count 0 2006.257.06:58:50.70#ibcon#about to read 6, iclass 4, count 0 2006.257.06:58:50.70#ibcon#read 6, iclass 4, count 0 2006.257.06:58:50.70#ibcon#end of sib2, iclass 4, count 0 2006.257.06:58:50.70#ibcon#*after write, iclass 4, count 0 2006.257.06:58:50.70#ibcon#*before return 0, iclass 4, count 0 2006.257.06:58:50.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:50.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.06:58:50.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.06:58:50.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.06:58:50.70$vck44/vbbw=wide 2006.257.06:58:50.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.06:58:50.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.06:58:50.70#ibcon#ireg 8 cls_cnt 0 2006.257.06:58:50.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:58:50.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:58:50.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:58:50.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.06:58:50.77#ibcon#first serial, iclass 6, count 0 2006.257.06:58:50.77#ibcon#enter sib2, iclass 6, count 0 2006.257.06:58:50.77#ibcon#flushed, iclass 6, count 0 2006.257.06:58:50.77#ibcon#about to write, iclass 6, count 0 2006.257.06:58:50.77#ibcon#wrote, iclass 6, count 0 2006.257.06:58:50.77#ibcon#about to read 3, iclass 6, count 0 2006.257.06:58:50.79#ibcon#read 3, iclass 6, count 0 2006.257.06:58:50.79#ibcon#about to read 4, iclass 6, count 0 2006.257.06:58:50.79#ibcon#read 4, iclass 6, count 0 2006.257.06:58:50.79#ibcon#about to read 5, iclass 6, count 0 2006.257.06:58:50.79#ibcon#read 5, iclass 6, count 0 2006.257.06:58:50.79#ibcon#about to read 6, iclass 6, count 0 2006.257.06:58:50.79#ibcon#read 6, iclass 6, count 0 2006.257.06:58:50.79#ibcon#end of sib2, iclass 6, count 0 2006.257.06:58:50.79#ibcon#*mode == 0, iclass 6, count 0 2006.257.06:58:50.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.06:58:50.79#ibcon#[27=BW32\r\n] 2006.257.06:58:50.79#ibcon#*before write, iclass 6, count 0 2006.257.06:58:50.79#ibcon#enter sib2, iclass 6, count 0 2006.257.06:58:50.79#ibcon#flushed, iclass 6, count 0 2006.257.06:58:50.79#ibcon#about to write, iclass 6, count 0 2006.257.06:58:50.79#ibcon#wrote, iclass 6, count 0 2006.257.06:58:50.79#ibcon#about to read 3, iclass 6, count 0 2006.257.06:58:50.82#ibcon#read 3, iclass 6, count 0 2006.257.06:58:50.82#ibcon#about to read 4, iclass 6, count 0 2006.257.06:58:50.82#ibcon#read 4, iclass 6, count 0 2006.257.06:58:50.82#ibcon#about to read 5, iclass 6, count 0 2006.257.06:58:50.82#ibcon#read 5, iclass 6, count 0 2006.257.06:58:50.82#ibcon#about to read 6, iclass 6, count 0 2006.257.06:58:50.82#ibcon#read 6, iclass 6, count 0 2006.257.06:58:50.82#ibcon#end of sib2, iclass 6, count 0 2006.257.06:58:50.82#ibcon#*after write, iclass 6, count 0 2006.257.06:58:50.82#ibcon#*before return 0, iclass 6, count 0 2006.257.06:58:50.82#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:58:50.82#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.06:58:50.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.06:58:50.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.06:58:50.82$setupk4/ifdk4 2006.257.06:58:50.82$ifdk4/lo= 2006.257.06:58:50.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.06:58:50.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.06:58:50.82$ifdk4/patch= 2006.257.06:58:50.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.06:58:50.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.06:58:50.82$setupk4/!*+20s 2006.257.06:58:51.80#abcon#<5=/16 1.3 3.9 20.81 891012.3\r\n> 2006.257.06:58:51.82#abcon#{5=INTERFACE CLEAR} 2006.257.06:58:51.88#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:59:01.97#abcon#<5=/16 1.3 3.9 20.81 891012.3\r\n> 2006.257.06:59:01.99#abcon#{5=INTERFACE CLEAR} 2006.257.06:59:02.05#abcon#[5=S1D000X0/0*\r\n] 2006.257.06:59:05.33$setupk4/"tpicd 2006.257.06:59:05.33$setupk4/echo=off 2006.257.06:59:05.33$setupk4/xlog=off 2006.257.06:59:05.33:!2006.257.07:02:53 2006.257.06:59:07.13#trakl#Source acquired 2006.257.06:59:07.13#flagr#flagr/antenna,acquired 2006.257.07:02:53.00:preob 2006.257.07:02:53.14/onsource/TRACKING 2006.257.07:02:53.14:!2006.257.07:03:03 2006.257.07:03:03.00:"tape 2006.257.07:03:03.00:"st=record 2006.257.07:03:03.00:data_valid=on 2006.257.07:03:03.00:midob 2006.257.07:03:04.14/onsource/TRACKING 2006.257.07:03:04.14/wx/20.90,1012.2,88 2006.257.07:03:04.23/cable/+6.4787E-03 2006.257.07:03:05.32/va/01,08,usb,yes,33,36 2006.257.07:03:05.32/va/02,07,usb,yes,36,36 2006.257.07:03:05.32/va/03,08,usb,yes,32,34 2006.257.07:03:05.32/va/04,07,usb,yes,37,39 2006.257.07:03:05.32/va/05,04,usb,yes,33,34 2006.257.07:03:05.32/va/06,04,usb,yes,37,36 2006.257.07:03:05.32/va/07,04,usb,yes,38,38 2006.257.07:03:05.32/va/08,04,usb,yes,31,39 2006.257.07:03:05.55/valo/01,524.99,yes,locked 2006.257.07:03:05.55/valo/02,534.99,yes,locked 2006.257.07:03:05.55/valo/03,564.99,yes,locked 2006.257.07:03:05.55/valo/04,624.99,yes,locked 2006.257.07:03:05.55/valo/05,734.99,yes,locked 2006.257.07:03:05.55/valo/06,814.99,yes,locked 2006.257.07:03:05.55/valo/07,864.99,yes,locked 2006.257.07:03:05.55/valo/08,884.99,yes,locked 2006.257.07:03:06.64/vb/01,04,usb,yes,39,36 2006.257.07:03:06.64/vb/02,05,usb,yes,37,36 2006.257.07:03:06.64/vb/03,04,usb,yes,38,42 2006.257.07:03:06.64/vb/04,05,usb,yes,38,37 2006.257.07:03:06.64/vb/05,04,usb,yes,34,37 2006.257.07:03:06.64/vb/06,04,usb,yes,39,35 2006.257.07:03:06.64/vb/07,04,usb,yes,39,39 2006.257.07:03:06.64/vb/08,04,usb,yes,35,39 2006.257.07:03:06.87/vblo/01,629.99,yes,locked 2006.257.07:03:06.87/vblo/02,634.99,yes,locked 2006.257.07:03:06.87/vblo/03,649.99,yes,locked 2006.257.07:03:06.87/vblo/04,679.99,yes,locked 2006.257.07:03:06.87/vblo/05,709.99,yes,locked 2006.257.07:03:06.87/vblo/06,719.99,yes,locked 2006.257.07:03:06.87/vblo/07,734.99,yes,locked 2006.257.07:03:06.87/vblo/08,744.99,yes,locked 2006.257.07:03:07.02/vabw/8 2006.257.07:03:07.17/vbbw/8 2006.257.07:03:07.38/xfe/off,on,16.7 2006.257.07:03:07.75/ifatt/23,28,28,28 2006.257.07:03:08.07/fmout-gps/S +4.50E-07 2006.257.07:03:08.11:!2006.257.07:04:33 2006.257.07:04:33.00:data_valid=off 2006.257.07:04:33.00:"et 2006.257.07:04:33.00:!+3s 2006.257.07:04:36.01:"tape 2006.257.07:04:36.01:postob 2006.257.07:04:36.21/cable/+6.4788E-03 2006.257.07:04:36.21/wx/20.92,1012.2,88 2006.257.07:04:37.07/fmout-gps/S +4.51E-07 2006.257.07:04:37.07:scan_name=257-0708,jd0609,210 2006.257.07:04:37.07:source=1044+719,104827.62,714335.9,2000.0,cw 2006.257.07:04:37.14#flagr#flagr/antenna,new-source 2006.257.07:04:38.14:checkk5 2006.257.07:04:38.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.07:04:38.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.07:04:40.59/chk_autoobs//k5ts3/ autoobs is running! 2006.257.07:04:40.98/chk_autoobs//k5ts4/ autoobs is running! 2006.257.07:04:41.38/chk_obsdata//k5ts1/T2570703??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.07:04:41.77/chk_obsdata//k5ts2/T2570703??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.07:04:42.20/chk_obsdata//k5ts3/T2570703??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.07:04:42.62/chk_obsdata//k5ts4/T2570703??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.257.07:04:43.34/k5log//k5ts1_log_newline 2006.257.07:04:44.06/k5log//k5ts2_log_newline 2006.257.07:04:44.81/k5log//k5ts3_log_newline 2006.257.07:04:45.50/k5log//k5ts4_log_newline 2006.257.07:04:45.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.07:04:45.52:setupk4=1 2006.257.07:04:45.52$setupk4/echo=on 2006.257.07:04:45.52$setupk4/pcalon 2006.257.07:04:45.52$pcalon/"no phase cal control is implemented here 2006.257.07:04:45.52$setupk4/"tpicd=stop 2006.257.07:04:45.52$setupk4/"rec=synch_on 2006.257.07:04:45.52$setupk4/"rec_mode=128 2006.257.07:04:45.52$setupk4/!* 2006.257.07:04:45.52$setupk4/recpk4 2006.257.07:04:45.52$recpk4/recpatch= 2006.257.07:04:45.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.07:04:45.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.07:04:45.53$setupk4/vck44 2006.257.07:04:45.53$vck44/valo=1,524.99 2006.257.07:04:45.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.07:04:45.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.07:04:45.53#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:45.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:45.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:45.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:45.53#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:04:45.53#ibcon#first serial, iclass 7, count 0 2006.257.07:04:45.53#ibcon#enter sib2, iclass 7, count 0 2006.257.07:04:45.53#ibcon#flushed, iclass 7, count 0 2006.257.07:04:45.53#ibcon#about to write, iclass 7, count 0 2006.257.07:04:45.53#ibcon#wrote, iclass 7, count 0 2006.257.07:04:45.53#ibcon#about to read 3, iclass 7, count 0 2006.257.07:04:45.55#ibcon#read 3, iclass 7, count 0 2006.257.07:04:45.55#ibcon#about to read 4, iclass 7, count 0 2006.257.07:04:45.55#ibcon#read 4, iclass 7, count 0 2006.257.07:04:45.55#ibcon#about to read 5, iclass 7, count 0 2006.257.07:04:45.55#ibcon#read 5, iclass 7, count 0 2006.257.07:04:45.55#ibcon#about to read 6, iclass 7, count 0 2006.257.07:04:45.55#ibcon#read 6, iclass 7, count 0 2006.257.07:04:45.55#ibcon#end of sib2, iclass 7, count 0 2006.257.07:04:45.55#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:04:45.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:04:45.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.07:04:45.55#ibcon#*before write, iclass 7, count 0 2006.257.07:04:45.55#ibcon#enter sib2, iclass 7, count 0 2006.257.07:04:45.55#ibcon#flushed, iclass 7, count 0 2006.257.07:04:45.55#ibcon#about to write, iclass 7, count 0 2006.257.07:04:45.55#ibcon#wrote, iclass 7, count 0 2006.257.07:04:45.55#ibcon#about to read 3, iclass 7, count 0 2006.257.07:04:45.60#ibcon#read 3, iclass 7, count 0 2006.257.07:04:45.60#ibcon#about to read 4, iclass 7, count 0 2006.257.07:04:45.60#ibcon#read 4, iclass 7, count 0 2006.257.07:04:45.60#ibcon#about to read 5, iclass 7, count 0 2006.257.07:04:45.60#ibcon#read 5, iclass 7, count 0 2006.257.07:04:45.60#ibcon#about to read 6, iclass 7, count 0 2006.257.07:04:45.60#ibcon#read 6, iclass 7, count 0 2006.257.07:04:45.60#ibcon#end of sib2, iclass 7, count 0 2006.257.07:04:45.60#ibcon#*after write, iclass 7, count 0 2006.257.07:04:45.60#ibcon#*before return 0, iclass 7, count 0 2006.257.07:04:45.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:45.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:45.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:04:45.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:04:45.60$vck44/va=1,8 2006.257.07:04:45.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.07:04:45.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.07:04:45.60#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:45.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:45.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:45.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:45.60#ibcon#enter wrdev, iclass 11, count 2 2006.257.07:04:45.60#ibcon#first serial, iclass 11, count 2 2006.257.07:04:45.60#ibcon#enter sib2, iclass 11, count 2 2006.257.07:04:45.60#ibcon#flushed, iclass 11, count 2 2006.257.07:04:45.60#ibcon#about to write, iclass 11, count 2 2006.257.07:04:45.60#ibcon#wrote, iclass 11, count 2 2006.257.07:04:45.60#ibcon#about to read 3, iclass 11, count 2 2006.257.07:04:45.62#ibcon#read 3, iclass 11, count 2 2006.257.07:04:45.62#ibcon#about to read 4, iclass 11, count 2 2006.257.07:04:45.62#ibcon#read 4, iclass 11, count 2 2006.257.07:04:45.62#ibcon#about to read 5, iclass 11, count 2 2006.257.07:04:45.62#ibcon#read 5, iclass 11, count 2 2006.257.07:04:45.62#ibcon#about to read 6, iclass 11, count 2 2006.257.07:04:45.62#ibcon#read 6, iclass 11, count 2 2006.257.07:04:45.62#ibcon#end of sib2, iclass 11, count 2 2006.257.07:04:45.62#ibcon#*mode == 0, iclass 11, count 2 2006.257.07:04:45.62#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.07:04:45.62#ibcon#[25=AT01-08\r\n] 2006.257.07:04:45.62#ibcon#*before write, iclass 11, count 2 2006.257.07:04:45.62#ibcon#enter sib2, iclass 11, count 2 2006.257.07:04:45.62#ibcon#flushed, iclass 11, count 2 2006.257.07:04:45.62#ibcon#about to write, iclass 11, count 2 2006.257.07:04:45.62#ibcon#wrote, iclass 11, count 2 2006.257.07:04:45.62#ibcon#about to read 3, iclass 11, count 2 2006.257.07:04:45.65#ibcon#read 3, iclass 11, count 2 2006.257.07:04:45.65#ibcon#about to read 4, iclass 11, count 2 2006.257.07:04:45.65#ibcon#read 4, iclass 11, count 2 2006.257.07:04:45.65#ibcon#about to read 5, iclass 11, count 2 2006.257.07:04:45.65#ibcon#read 5, iclass 11, count 2 2006.257.07:04:45.65#ibcon#about to read 6, iclass 11, count 2 2006.257.07:04:45.65#ibcon#read 6, iclass 11, count 2 2006.257.07:04:45.65#ibcon#end of sib2, iclass 11, count 2 2006.257.07:04:45.65#ibcon#*after write, iclass 11, count 2 2006.257.07:04:45.65#ibcon#*before return 0, iclass 11, count 2 2006.257.07:04:45.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:45.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:45.65#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.07:04:45.65#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:45.65#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:45.77#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:45.77#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:45.77#ibcon#enter wrdev, iclass 11, count 0 2006.257.07:04:45.77#ibcon#first serial, iclass 11, count 0 2006.257.07:04:45.77#ibcon#enter sib2, iclass 11, count 0 2006.257.07:04:45.77#ibcon#flushed, iclass 11, count 0 2006.257.07:04:45.77#ibcon#about to write, iclass 11, count 0 2006.257.07:04:45.77#ibcon#wrote, iclass 11, count 0 2006.257.07:04:45.77#ibcon#about to read 3, iclass 11, count 0 2006.257.07:04:45.79#ibcon#read 3, iclass 11, count 0 2006.257.07:04:45.79#ibcon#about to read 4, iclass 11, count 0 2006.257.07:04:45.79#ibcon#read 4, iclass 11, count 0 2006.257.07:04:45.79#ibcon#about to read 5, iclass 11, count 0 2006.257.07:04:45.79#ibcon#read 5, iclass 11, count 0 2006.257.07:04:45.79#ibcon#about to read 6, iclass 11, count 0 2006.257.07:04:45.79#ibcon#read 6, iclass 11, count 0 2006.257.07:04:45.79#ibcon#end of sib2, iclass 11, count 0 2006.257.07:04:45.79#ibcon#*mode == 0, iclass 11, count 0 2006.257.07:04:45.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.07:04:45.79#ibcon#[25=USB\r\n] 2006.257.07:04:45.79#ibcon#*before write, iclass 11, count 0 2006.257.07:04:45.79#ibcon#enter sib2, iclass 11, count 0 2006.257.07:04:45.79#ibcon#flushed, iclass 11, count 0 2006.257.07:04:45.79#ibcon#about to write, iclass 11, count 0 2006.257.07:04:45.79#ibcon#wrote, iclass 11, count 0 2006.257.07:04:45.79#ibcon#about to read 3, iclass 11, count 0 2006.257.07:04:45.82#ibcon#read 3, iclass 11, count 0 2006.257.07:04:45.82#ibcon#about to read 4, iclass 11, count 0 2006.257.07:04:45.82#ibcon#read 4, iclass 11, count 0 2006.257.07:04:45.82#ibcon#about to read 5, iclass 11, count 0 2006.257.07:04:45.82#ibcon#read 5, iclass 11, count 0 2006.257.07:04:45.82#ibcon#about to read 6, iclass 11, count 0 2006.257.07:04:45.82#ibcon#read 6, iclass 11, count 0 2006.257.07:04:45.82#ibcon#end of sib2, iclass 11, count 0 2006.257.07:04:45.82#ibcon#*after write, iclass 11, count 0 2006.257.07:04:45.82#ibcon#*before return 0, iclass 11, count 0 2006.257.07:04:45.82#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:45.82#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:45.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.07:04:45.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.07:04:45.82$vck44/valo=2,534.99 2006.257.07:04:45.82#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.07:04:45.82#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.07:04:45.82#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:45.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:45.82#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:45.82#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:45.82#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:04:45.82#ibcon#first serial, iclass 13, count 0 2006.257.07:04:45.82#ibcon#enter sib2, iclass 13, count 0 2006.257.07:04:45.82#ibcon#flushed, iclass 13, count 0 2006.257.07:04:45.82#ibcon#about to write, iclass 13, count 0 2006.257.07:04:45.82#ibcon#wrote, iclass 13, count 0 2006.257.07:04:45.82#ibcon#about to read 3, iclass 13, count 0 2006.257.07:04:45.84#ibcon#read 3, iclass 13, count 0 2006.257.07:04:45.84#ibcon#about to read 4, iclass 13, count 0 2006.257.07:04:45.84#ibcon#read 4, iclass 13, count 0 2006.257.07:04:45.84#ibcon#about to read 5, iclass 13, count 0 2006.257.07:04:45.84#ibcon#read 5, iclass 13, count 0 2006.257.07:04:45.84#ibcon#about to read 6, iclass 13, count 0 2006.257.07:04:45.84#ibcon#read 6, iclass 13, count 0 2006.257.07:04:45.84#ibcon#end of sib2, iclass 13, count 0 2006.257.07:04:45.84#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:04:45.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:04:45.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.07:04:45.84#ibcon#*before write, iclass 13, count 0 2006.257.07:04:45.84#ibcon#enter sib2, iclass 13, count 0 2006.257.07:04:45.84#ibcon#flushed, iclass 13, count 0 2006.257.07:04:45.84#ibcon#about to write, iclass 13, count 0 2006.257.07:04:45.84#ibcon#wrote, iclass 13, count 0 2006.257.07:04:45.84#ibcon#about to read 3, iclass 13, count 0 2006.257.07:04:45.88#ibcon#read 3, iclass 13, count 0 2006.257.07:04:45.88#ibcon#about to read 4, iclass 13, count 0 2006.257.07:04:45.88#ibcon#read 4, iclass 13, count 0 2006.257.07:04:45.88#ibcon#about to read 5, iclass 13, count 0 2006.257.07:04:45.88#ibcon#read 5, iclass 13, count 0 2006.257.07:04:45.88#ibcon#about to read 6, iclass 13, count 0 2006.257.07:04:45.88#ibcon#read 6, iclass 13, count 0 2006.257.07:04:45.88#ibcon#end of sib2, iclass 13, count 0 2006.257.07:04:45.88#ibcon#*after write, iclass 13, count 0 2006.257.07:04:45.88#ibcon#*before return 0, iclass 13, count 0 2006.257.07:04:45.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:45.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:45.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:04:45.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:04:45.88$vck44/va=2,7 2006.257.07:04:45.88#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.07:04:45.88#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.07:04:45.88#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:45.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:45.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:45.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:45.94#ibcon#enter wrdev, iclass 15, count 2 2006.257.07:04:45.94#ibcon#first serial, iclass 15, count 2 2006.257.07:04:45.94#ibcon#enter sib2, iclass 15, count 2 2006.257.07:04:45.94#ibcon#flushed, iclass 15, count 2 2006.257.07:04:45.94#ibcon#about to write, iclass 15, count 2 2006.257.07:04:45.94#ibcon#wrote, iclass 15, count 2 2006.257.07:04:45.94#ibcon#about to read 3, iclass 15, count 2 2006.257.07:04:45.96#ibcon#read 3, iclass 15, count 2 2006.257.07:04:45.96#ibcon#about to read 4, iclass 15, count 2 2006.257.07:04:45.96#ibcon#read 4, iclass 15, count 2 2006.257.07:04:45.96#ibcon#about to read 5, iclass 15, count 2 2006.257.07:04:45.96#ibcon#read 5, iclass 15, count 2 2006.257.07:04:45.96#ibcon#about to read 6, iclass 15, count 2 2006.257.07:04:45.96#ibcon#read 6, iclass 15, count 2 2006.257.07:04:45.96#ibcon#end of sib2, iclass 15, count 2 2006.257.07:04:45.96#ibcon#*mode == 0, iclass 15, count 2 2006.257.07:04:45.96#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.07:04:45.96#ibcon#[25=AT02-07\r\n] 2006.257.07:04:45.96#ibcon#*before write, iclass 15, count 2 2006.257.07:04:45.96#ibcon#enter sib2, iclass 15, count 2 2006.257.07:04:45.96#ibcon#flushed, iclass 15, count 2 2006.257.07:04:45.96#ibcon#about to write, iclass 15, count 2 2006.257.07:04:45.96#ibcon#wrote, iclass 15, count 2 2006.257.07:04:45.96#ibcon#about to read 3, iclass 15, count 2 2006.257.07:04:45.99#ibcon#read 3, iclass 15, count 2 2006.257.07:04:45.99#ibcon#about to read 4, iclass 15, count 2 2006.257.07:04:45.99#ibcon#read 4, iclass 15, count 2 2006.257.07:04:45.99#ibcon#about to read 5, iclass 15, count 2 2006.257.07:04:45.99#ibcon#read 5, iclass 15, count 2 2006.257.07:04:45.99#ibcon#about to read 6, iclass 15, count 2 2006.257.07:04:45.99#ibcon#read 6, iclass 15, count 2 2006.257.07:04:45.99#ibcon#end of sib2, iclass 15, count 2 2006.257.07:04:45.99#ibcon#*after write, iclass 15, count 2 2006.257.07:04:45.99#ibcon#*before return 0, iclass 15, count 2 2006.257.07:04:45.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:45.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:45.99#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.07:04:45.99#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:45.99#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:46.11#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:46.11#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:46.11#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:04:46.11#ibcon#first serial, iclass 15, count 0 2006.257.07:04:46.11#ibcon#enter sib2, iclass 15, count 0 2006.257.07:04:46.11#ibcon#flushed, iclass 15, count 0 2006.257.07:04:46.11#ibcon#about to write, iclass 15, count 0 2006.257.07:04:46.11#ibcon#wrote, iclass 15, count 0 2006.257.07:04:46.11#ibcon#about to read 3, iclass 15, count 0 2006.257.07:04:46.13#ibcon#read 3, iclass 15, count 0 2006.257.07:04:46.13#ibcon#about to read 4, iclass 15, count 0 2006.257.07:04:46.13#ibcon#read 4, iclass 15, count 0 2006.257.07:04:46.13#ibcon#about to read 5, iclass 15, count 0 2006.257.07:04:46.13#ibcon#read 5, iclass 15, count 0 2006.257.07:04:46.13#ibcon#about to read 6, iclass 15, count 0 2006.257.07:04:46.13#ibcon#read 6, iclass 15, count 0 2006.257.07:04:46.13#ibcon#end of sib2, iclass 15, count 0 2006.257.07:04:46.13#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:04:46.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:04:46.13#ibcon#[25=USB\r\n] 2006.257.07:04:46.13#ibcon#*before write, iclass 15, count 0 2006.257.07:04:46.13#ibcon#enter sib2, iclass 15, count 0 2006.257.07:04:46.13#ibcon#flushed, iclass 15, count 0 2006.257.07:04:46.13#ibcon#about to write, iclass 15, count 0 2006.257.07:04:46.13#ibcon#wrote, iclass 15, count 0 2006.257.07:04:46.13#ibcon#about to read 3, iclass 15, count 0 2006.257.07:04:46.16#ibcon#read 3, iclass 15, count 0 2006.257.07:04:46.16#ibcon#about to read 4, iclass 15, count 0 2006.257.07:04:46.16#ibcon#read 4, iclass 15, count 0 2006.257.07:04:46.16#ibcon#about to read 5, iclass 15, count 0 2006.257.07:04:46.16#ibcon#read 5, iclass 15, count 0 2006.257.07:04:46.16#ibcon#about to read 6, iclass 15, count 0 2006.257.07:04:46.16#ibcon#read 6, iclass 15, count 0 2006.257.07:04:46.16#ibcon#end of sib2, iclass 15, count 0 2006.257.07:04:46.16#ibcon#*after write, iclass 15, count 0 2006.257.07:04:46.16#ibcon#*before return 0, iclass 15, count 0 2006.257.07:04:46.16#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:46.16#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:46.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:04:46.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:04:46.16$vck44/valo=3,564.99 2006.257.07:04:46.16#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.07:04:46.16#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.07:04:46.16#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:46.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:46.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:46.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:46.16#ibcon#enter wrdev, iclass 17, count 0 2006.257.07:04:46.16#ibcon#first serial, iclass 17, count 0 2006.257.07:04:46.16#ibcon#enter sib2, iclass 17, count 0 2006.257.07:04:46.16#ibcon#flushed, iclass 17, count 0 2006.257.07:04:46.16#ibcon#about to write, iclass 17, count 0 2006.257.07:04:46.16#ibcon#wrote, iclass 17, count 0 2006.257.07:04:46.16#ibcon#about to read 3, iclass 17, count 0 2006.257.07:04:46.18#ibcon#read 3, iclass 17, count 0 2006.257.07:04:46.18#ibcon#about to read 4, iclass 17, count 0 2006.257.07:04:46.18#ibcon#read 4, iclass 17, count 0 2006.257.07:04:46.18#ibcon#about to read 5, iclass 17, count 0 2006.257.07:04:46.18#ibcon#read 5, iclass 17, count 0 2006.257.07:04:46.18#ibcon#about to read 6, iclass 17, count 0 2006.257.07:04:46.18#ibcon#read 6, iclass 17, count 0 2006.257.07:04:46.18#ibcon#end of sib2, iclass 17, count 0 2006.257.07:04:46.18#ibcon#*mode == 0, iclass 17, count 0 2006.257.07:04:46.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.07:04:46.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.07:04:46.18#ibcon#*before write, iclass 17, count 0 2006.257.07:04:46.18#ibcon#enter sib2, iclass 17, count 0 2006.257.07:04:46.18#ibcon#flushed, iclass 17, count 0 2006.257.07:04:46.18#ibcon#about to write, iclass 17, count 0 2006.257.07:04:46.18#ibcon#wrote, iclass 17, count 0 2006.257.07:04:46.18#ibcon#about to read 3, iclass 17, count 0 2006.257.07:04:46.22#ibcon#read 3, iclass 17, count 0 2006.257.07:04:46.22#ibcon#about to read 4, iclass 17, count 0 2006.257.07:04:46.22#ibcon#read 4, iclass 17, count 0 2006.257.07:04:46.22#ibcon#about to read 5, iclass 17, count 0 2006.257.07:04:46.22#ibcon#read 5, iclass 17, count 0 2006.257.07:04:46.22#ibcon#about to read 6, iclass 17, count 0 2006.257.07:04:46.22#ibcon#read 6, iclass 17, count 0 2006.257.07:04:46.22#ibcon#end of sib2, iclass 17, count 0 2006.257.07:04:46.22#ibcon#*after write, iclass 17, count 0 2006.257.07:04:46.22#ibcon#*before return 0, iclass 17, count 0 2006.257.07:04:46.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:46.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:46.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.07:04:46.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.07:04:46.22$vck44/va=3,8 2006.257.07:04:46.22#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.07:04:46.22#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.07:04:46.22#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:46.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:46.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:46.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:46.28#ibcon#enter wrdev, iclass 19, count 2 2006.257.07:04:46.28#ibcon#first serial, iclass 19, count 2 2006.257.07:04:46.28#ibcon#enter sib2, iclass 19, count 2 2006.257.07:04:46.28#ibcon#flushed, iclass 19, count 2 2006.257.07:04:46.28#ibcon#about to write, iclass 19, count 2 2006.257.07:04:46.28#ibcon#wrote, iclass 19, count 2 2006.257.07:04:46.28#ibcon#about to read 3, iclass 19, count 2 2006.257.07:04:46.30#ibcon#read 3, iclass 19, count 2 2006.257.07:04:46.30#ibcon#about to read 4, iclass 19, count 2 2006.257.07:04:46.30#ibcon#read 4, iclass 19, count 2 2006.257.07:04:46.30#ibcon#about to read 5, iclass 19, count 2 2006.257.07:04:46.30#ibcon#read 5, iclass 19, count 2 2006.257.07:04:46.30#ibcon#about to read 6, iclass 19, count 2 2006.257.07:04:46.30#ibcon#read 6, iclass 19, count 2 2006.257.07:04:46.30#ibcon#end of sib2, iclass 19, count 2 2006.257.07:04:46.30#ibcon#*mode == 0, iclass 19, count 2 2006.257.07:04:46.30#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.07:04:46.30#ibcon#[25=AT03-08\r\n] 2006.257.07:04:46.30#ibcon#*before write, iclass 19, count 2 2006.257.07:04:46.30#ibcon#enter sib2, iclass 19, count 2 2006.257.07:04:46.30#ibcon#flushed, iclass 19, count 2 2006.257.07:04:46.30#ibcon#about to write, iclass 19, count 2 2006.257.07:04:46.30#ibcon#wrote, iclass 19, count 2 2006.257.07:04:46.30#ibcon#about to read 3, iclass 19, count 2 2006.257.07:04:46.33#ibcon#read 3, iclass 19, count 2 2006.257.07:04:46.33#ibcon#about to read 4, iclass 19, count 2 2006.257.07:04:46.33#ibcon#read 4, iclass 19, count 2 2006.257.07:04:46.33#ibcon#about to read 5, iclass 19, count 2 2006.257.07:04:46.33#ibcon#read 5, iclass 19, count 2 2006.257.07:04:46.33#ibcon#about to read 6, iclass 19, count 2 2006.257.07:04:46.33#ibcon#read 6, iclass 19, count 2 2006.257.07:04:46.33#ibcon#end of sib2, iclass 19, count 2 2006.257.07:04:46.33#ibcon#*after write, iclass 19, count 2 2006.257.07:04:46.33#ibcon#*before return 0, iclass 19, count 2 2006.257.07:04:46.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:46.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:46.33#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.07:04:46.33#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:46.33#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:46.45#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:46.45#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:46.45#ibcon#enter wrdev, iclass 19, count 0 2006.257.07:04:46.45#ibcon#first serial, iclass 19, count 0 2006.257.07:04:46.45#ibcon#enter sib2, iclass 19, count 0 2006.257.07:04:46.45#ibcon#flushed, iclass 19, count 0 2006.257.07:04:46.45#ibcon#about to write, iclass 19, count 0 2006.257.07:04:46.45#ibcon#wrote, iclass 19, count 0 2006.257.07:04:46.45#ibcon#about to read 3, iclass 19, count 0 2006.257.07:04:46.47#ibcon#read 3, iclass 19, count 0 2006.257.07:04:46.47#ibcon#about to read 4, iclass 19, count 0 2006.257.07:04:46.47#ibcon#read 4, iclass 19, count 0 2006.257.07:04:46.47#ibcon#about to read 5, iclass 19, count 0 2006.257.07:04:46.47#ibcon#read 5, iclass 19, count 0 2006.257.07:04:46.47#ibcon#about to read 6, iclass 19, count 0 2006.257.07:04:46.47#ibcon#read 6, iclass 19, count 0 2006.257.07:04:46.47#ibcon#end of sib2, iclass 19, count 0 2006.257.07:04:46.47#ibcon#*mode == 0, iclass 19, count 0 2006.257.07:04:46.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.07:04:46.47#ibcon#[25=USB\r\n] 2006.257.07:04:46.47#ibcon#*before write, iclass 19, count 0 2006.257.07:04:46.47#ibcon#enter sib2, iclass 19, count 0 2006.257.07:04:46.47#ibcon#flushed, iclass 19, count 0 2006.257.07:04:46.47#ibcon#about to write, iclass 19, count 0 2006.257.07:04:46.47#ibcon#wrote, iclass 19, count 0 2006.257.07:04:46.47#ibcon#about to read 3, iclass 19, count 0 2006.257.07:04:46.50#ibcon#read 3, iclass 19, count 0 2006.257.07:04:46.50#ibcon#about to read 4, iclass 19, count 0 2006.257.07:04:46.50#ibcon#read 4, iclass 19, count 0 2006.257.07:04:46.50#ibcon#about to read 5, iclass 19, count 0 2006.257.07:04:46.50#ibcon#read 5, iclass 19, count 0 2006.257.07:04:46.50#ibcon#about to read 6, iclass 19, count 0 2006.257.07:04:46.50#ibcon#read 6, iclass 19, count 0 2006.257.07:04:46.50#ibcon#end of sib2, iclass 19, count 0 2006.257.07:04:46.50#ibcon#*after write, iclass 19, count 0 2006.257.07:04:46.50#ibcon#*before return 0, iclass 19, count 0 2006.257.07:04:46.50#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:46.50#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:46.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.07:04:46.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.07:04:46.50$vck44/valo=4,624.99 2006.257.07:04:46.50#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.07:04:46.50#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.07:04:46.50#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:46.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:46.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:46.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:46.50#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:04:46.50#ibcon#first serial, iclass 21, count 0 2006.257.07:04:46.50#ibcon#enter sib2, iclass 21, count 0 2006.257.07:04:46.50#ibcon#flushed, iclass 21, count 0 2006.257.07:04:46.50#ibcon#about to write, iclass 21, count 0 2006.257.07:04:46.50#ibcon#wrote, iclass 21, count 0 2006.257.07:04:46.50#ibcon#about to read 3, iclass 21, count 0 2006.257.07:04:46.52#ibcon#read 3, iclass 21, count 0 2006.257.07:04:46.52#ibcon#about to read 4, iclass 21, count 0 2006.257.07:04:46.52#ibcon#read 4, iclass 21, count 0 2006.257.07:04:46.52#ibcon#about to read 5, iclass 21, count 0 2006.257.07:04:46.52#ibcon#read 5, iclass 21, count 0 2006.257.07:04:46.52#ibcon#about to read 6, iclass 21, count 0 2006.257.07:04:46.52#ibcon#read 6, iclass 21, count 0 2006.257.07:04:46.52#ibcon#end of sib2, iclass 21, count 0 2006.257.07:04:46.52#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:04:46.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:04:46.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.07:04:46.52#ibcon#*before write, iclass 21, count 0 2006.257.07:04:46.52#ibcon#enter sib2, iclass 21, count 0 2006.257.07:04:46.52#ibcon#flushed, iclass 21, count 0 2006.257.07:04:46.52#ibcon#about to write, iclass 21, count 0 2006.257.07:04:46.52#ibcon#wrote, iclass 21, count 0 2006.257.07:04:46.52#ibcon#about to read 3, iclass 21, count 0 2006.257.07:04:46.56#ibcon#read 3, iclass 21, count 0 2006.257.07:04:46.56#ibcon#about to read 4, iclass 21, count 0 2006.257.07:04:46.56#ibcon#read 4, iclass 21, count 0 2006.257.07:04:46.56#ibcon#about to read 5, iclass 21, count 0 2006.257.07:04:46.56#ibcon#read 5, iclass 21, count 0 2006.257.07:04:46.56#ibcon#about to read 6, iclass 21, count 0 2006.257.07:04:46.56#ibcon#read 6, iclass 21, count 0 2006.257.07:04:46.56#ibcon#end of sib2, iclass 21, count 0 2006.257.07:04:46.56#ibcon#*after write, iclass 21, count 0 2006.257.07:04:46.56#ibcon#*before return 0, iclass 21, count 0 2006.257.07:04:46.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:46.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:46.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:04:46.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:04:46.56$vck44/va=4,7 2006.257.07:04:46.56#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.07:04:46.56#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.07:04:46.56#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:46.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:46.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:46.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:46.62#ibcon#enter wrdev, iclass 23, count 2 2006.257.07:04:46.62#ibcon#first serial, iclass 23, count 2 2006.257.07:04:46.62#ibcon#enter sib2, iclass 23, count 2 2006.257.07:04:46.62#ibcon#flushed, iclass 23, count 2 2006.257.07:04:46.62#ibcon#about to write, iclass 23, count 2 2006.257.07:04:46.62#ibcon#wrote, iclass 23, count 2 2006.257.07:04:46.62#ibcon#about to read 3, iclass 23, count 2 2006.257.07:04:46.64#ibcon#read 3, iclass 23, count 2 2006.257.07:04:46.64#ibcon#about to read 4, iclass 23, count 2 2006.257.07:04:46.64#ibcon#read 4, iclass 23, count 2 2006.257.07:04:46.64#ibcon#about to read 5, iclass 23, count 2 2006.257.07:04:46.64#ibcon#read 5, iclass 23, count 2 2006.257.07:04:46.64#ibcon#about to read 6, iclass 23, count 2 2006.257.07:04:46.64#ibcon#read 6, iclass 23, count 2 2006.257.07:04:46.64#ibcon#end of sib2, iclass 23, count 2 2006.257.07:04:46.64#ibcon#*mode == 0, iclass 23, count 2 2006.257.07:04:46.64#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.07:04:46.64#ibcon#[25=AT04-07\r\n] 2006.257.07:04:46.64#ibcon#*before write, iclass 23, count 2 2006.257.07:04:46.64#ibcon#enter sib2, iclass 23, count 2 2006.257.07:04:46.64#ibcon#flushed, iclass 23, count 2 2006.257.07:04:46.64#ibcon#about to write, iclass 23, count 2 2006.257.07:04:46.64#ibcon#wrote, iclass 23, count 2 2006.257.07:04:46.64#ibcon#about to read 3, iclass 23, count 2 2006.257.07:04:46.67#ibcon#read 3, iclass 23, count 2 2006.257.07:04:46.67#ibcon#about to read 4, iclass 23, count 2 2006.257.07:04:46.67#ibcon#read 4, iclass 23, count 2 2006.257.07:04:46.67#ibcon#about to read 5, iclass 23, count 2 2006.257.07:04:46.67#ibcon#read 5, iclass 23, count 2 2006.257.07:04:46.67#ibcon#about to read 6, iclass 23, count 2 2006.257.07:04:46.67#ibcon#read 6, iclass 23, count 2 2006.257.07:04:46.67#ibcon#end of sib2, iclass 23, count 2 2006.257.07:04:46.67#ibcon#*after write, iclass 23, count 2 2006.257.07:04:46.67#ibcon#*before return 0, iclass 23, count 2 2006.257.07:04:46.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:46.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:46.67#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.07:04:46.67#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:46.67#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:46.79#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:46.79#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:46.79#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:04:46.79#ibcon#first serial, iclass 23, count 0 2006.257.07:04:46.79#ibcon#enter sib2, iclass 23, count 0 2006.257.07:04:46.79#ibcon#flushed, iclass 23, count 0 2006.257.07:04:46.79#ibcon#about to write, iclass 23, count 0 2006.257.07:04:46.79#ibcon#wrote, iclass 23, count 0 2006.257.07:04:46.79#ibcon#about to read 3, iclass 23, count 0 2006.257.07:04:46.81#ibcon#read 3, iclass 23, count 0 2006.257.07:04:46.81#ibcon#about to read 4, iclass 23, count 0 2006.257.07:04:46.81#ibcon#read 4, iclass 23, count 0 2006.257.07:04:46.81#ibcon#about to read 5, iclass 23, count 0 2006.257.07:04:46.81#ibcon#read 5, iclass 23, count 0 2006.257.07:04:46.81#ibcon#about to read 6, iclass 23, count 0 2006.257.07:04:46.81#ibcon#read 6, iclass 23, count 0 2006.257.07:04:46.81#ibcon#end of sib2, iclass 23, count 0 2006.257.07:04:46.81#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:04:46.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:04:46.81#ibcon#[25=USB\r\n] 2006.257.07:04:46.81#ibcon#*before write, iclass 23, count 0 2006.257.07:04:46.81#ibcon#enter sib2, iclass 23, count 0 2006.257.07:04:46.81#ibcon#flushed, iclass 23, count 0 2006.257.07:04:46.81#ibcon#about to write, iclass 23, count 0 2006.257.07:04:46.81#ibcon#wrote, iclass 23, count 0 2006.257.07:04:46.81#ibcon#about to read 3, iclass 23, count 0 2006.257.07:04:46.84#ibcon#read 3, iclass 23, count 0 2006.257.07:04:46.84#ibcon#about to read 4, iclass 23, count 0 2006.257.07:04:46.84#ibcon#read 4, iclass 23, count 0 2006.257.07:04:46.84#ibcon#about to read 5, iclass 23, count 0 2006.257.07:04:46.84#ibcon#read 5, iclass 23, count 0 2006.257.07:04:46.84#ibcon#about to read 6, iclass 23, count 0 2006.257.07:04:46.84#ibcon#read 6, iclass 23, count 0 2006.257.07:04:46.84#ibcon#end of sib2, iclass 23, count 0 2006.257.07:04:46.84#ibcon#*after write, iclass 23, count 0 2006.257.07:04:46.84#ibcon#*before return 0, iclass 23, count 0 2006.257.07:04:46.84#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:46.84#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:46.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:04:46.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:04:46.84$vck44/valo=5,734.99 2006.257.07:04:46.84#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.07:04:46.84#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.07:04:46.84#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:46.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:46.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:46.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:46.84#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:04:46.84#ibcon#first serial, iclass 25, count 0 2006.257.07:04:46.84#ibcon#enter sib2, iclass 25, count 0 2006.257.07:04:46.84#ibcon#flushed, iclass 25, count 0 2006.257.07:04:46.84#ibcon#about to write, iclass 25, count 0 2006.257.07:04:46.84#ibcon#wrote, iclass 25, count 0 2006.257.07:04:46.84#ibcon#about to read 3, iclass 25, count 0 2006.257.07:04:46.86#ibcon#read 3, iclass 25, count 0 2006.257.07:04:46.86#ibcon#about to read 4, iclass 25, count 0 2006.257.07:04:46.86#ibcon#read 4, iclass 25, count 0 2006.257.07:04:46.86#ibcon#about to read 5, iclass 25, count 0 2006.257.07:04:46.86#ibcon#read 5, iclass 25, count 0 2006.257.07:04:46.86#ibcon#about to read 6, iclass 25, count 0 2006.257.07:04:46.86#ibcon#read 6, iclass 25, count 0 2006.257.07:04:46.86#ibcon#end of sib2, iclass 25, count 0 2006.257.07:04:46.86#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:04:46.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:04:46.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.07:04:46.86#ibcon#*before write, iclass 25, count 0 2006.257.07:04:46.86#ibcon#enter sib2, iclass 25, count 0 2006.257.07:04:46.86#ibcon#flushed, iclass 25, count 0 2006.257.07:04:46.86#ibcon#about to write, iclass 25, count 0 2006.257.07:04:46.86#ibcon#wrote, iclass 25, count 0 2006.257.07:04:46.86#ibcon#about to read 3, iclass 25, count 0 2006.257.07:04:46.90#ibcon#read 3, iclass 25, count 0 2006.257.07:04:46.90#ibcon#about to read 4, iclass 25, count 0 2006.257.07:04:46.90#ibcon#read 4, iclass 25, count 0 2006.257.07:04:46.90#ibcon#about to read 5, iclass 25, count 0 2006.257.07:04:46.90#ibcon#read 5, iclass 25, count 0 2006.257.07:04:46.90#ibcon#about to read 6, iclass 25, count 0 2006.257.07:04:46.90#ibcon#read 6, iclass 25, count 0 2006.257.07:04:46.90#ibcon#end of sib2, iclass 25, count 0 2006.257.07:04:46.90#ibcon#*after write, iclass 25, count 0 2006.257.07:04:46.90#ibcon#*before return 0, iclass 25, count 0 2006.257.07:04:46.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:46.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:46.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:04:46.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:04:46.90$vck44/va=5,4 2006.257.07:04:46.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.07:04:46.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.07:04:46.90#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:46.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:46.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:46.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:46.96#ibcon#enter wrdev, iclass 27, count 2 2006.257.07:04:46.96#ibcon#first serial, iclass 27, count 2 2006.257.07:04:46.96#ibcon#enter sib2, iclass 27, count 2 2006.257.07:04:46.96#ibcon#flushed, iclass 27, count 2 2006.257.07:04:46.96#ibcon#about to write, iclass 27, count 2 2006.257.07:04:46.96#ibcon#wrote, iclass 27, count 2 2006.257.07:04:46.96#ibcon#about to read 3, iclass 27, count 2 2006.257.07:04:46.98#ibcon#read 3, iclass 27, count 2 2006.257.07:04:46.98#ibcon#about to read 4, iclass 27, count 2 2006.257.07:04:46.98#ibcon#read 4, iclass 27, count 2 2006.257.07:04:46.98#ibcon#about to read 5, iclass 27, count 2 2006.257.07:04:46.98#ibcon#read 5, iclass 27, count 2 2006.257.07:04:46.98#ibcon#about to read 6, iclass 27, count 2 2006.257.07:04:46.98#ibcon#read 6, iclass 27, count 2 2006.257.07:04:46.98#ibcon#end of sib2, iclass 27, count 2 2006.257.07:04:46.98#ibcon#*mode == 0, iclass 27, count 2 2006.257.07:04:46.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.07:04:46.98#ibcon#[25=AT05-04\r\n] 2006.257.07:04:46.98#ibcon#*before write, iclass 27, count 2 2006.257.07:04:46.98#ibcon#enter sib2, iclass 27, count 2 2006.257.07:04:46.98#ibcon#flushed, iclass 27, count 2 2006.257.07:04:46.98#ibcon#about to write, iclass 27, count 2 2006.257.07:04:46.98#ibcon#wrote, iclass 27, count 2 2006.257.07:04:46.98#ibcon#about to read 3, iclass 27, count 2 2006.257.07:04:47.01#ibcon#read 3, iclass 27, count 2 2006.257.07:04:47.01#ibcon#about to read 4, iclass 27, count 2 2006.257.07:04:47.01#ibcon#read 4, iclass 27, count 2 2006.257.07:04:47.01#ibcon#about to read 5, iclass 27, count 2 2006.257.07:04:47.01#ibcon#read 5, iclass 27, count 2 2006.257.07:04:47.01#ibcon#about to read 6, iclass 27, count 2 2006.257.07:04:47.01#ibcon#read 6, iclass 27, count 2 2006.257.07:04:47.01#ibcon#end of sib2, iclass 27, count 2 2006.257.07:04:47.01#ibcon#*after write, iclass 27, count 2 2006.257.07:04:47.01#ibcon#*before return 0, iclass 27, count 2 2006.257.07:04:47.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:47.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:47.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.07:04:47.01#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:47.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:47.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:47.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:47.13#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:04:47.13#ibcon#first serial, iclass 27, count 0 2006.257.07:04:47.13#ibcon#enter sib2, iclass 27, count 0 2006.257.07:04:47.13#ibcon#flushed, iclass 27, count 0 2006.257.07:04:47.13#ibcon#about to write, iclass 27, count 0 2006.257.07:04:47.13#ibcon#wrote, iclass 27, count 0 2006.257.07:04:47.13#ibcon#about to read 3, iclass 27, count 0 2006.257.07:04:47.15#ibcon#read 3, iclass 27, count 0 2006.257.07:04:47.15#ibcon#about to read 4, iclass 27, count 0 2006.257.07:04:47.15#ibcon#read 4, iclass 27, count 0 2006.257.07:04:47.15#ibcon#about to read 5, iclass 27, count 0 2006.257.07:04:47.15#ibcon#read 5, iclass 27, count 0 2006.257.07:04:47.15#ibcon#about to read 6, iclass 27, count 0 2006.257.07:04:47.15#ibcon#read 6, iclass 27, count 0 2006.257.07:04:47.15#ibcon#end of sib2, iclass 27, count 0 2006.257.07:04:47.15#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:04:47.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:04:47.15#ibcon#[25=USB\r\n] 2006.257.07:04:47.15#ibcon#*before write, iclass 27, count 0 2006.257.07:04:47.15#ibcon#enter sib2, iclass 27, count 0 2006.257.07:04:47.15#ibcon#flushed, iclass 27, count 0 2006.257.07:04:47.15#ibcon#about to write, iclass 27, count 0 2006.257.07:04:47.15#ibcon#wrote, iclass 27, count 0 2006.257.07:04:47.15#ibcon#about to read 3, iclass 27, count 0 2006.257.07:04:47.18#ibcon#read 3, iclass 27, count 0 2006.257.07:04:47.18#ibcon#about to read 4, iclass 27, count 0 2006.257.07:04:47.18#ibcon#read 4, iclass 27, count 0 2006.257.07:04:47.18#ibcon#about to read 5, iclass 27, count 0 2006.257.07:04:47.18#ibcon#read 5, iclass 27, count 0 2006.257.07:04:47.18#ibcon#about to read 6, iclass 27, count 0 2006.257.07:04:47.18#ibcon#read 6, iclass 27, count 0 2006.257.07:04:47.18#ibcon#end of sib2, iclass 27, count 0 2006.257.07:04:47.18#ibcon#*after write, iclass 27, count 0 2006.257.07:04:47.18#ibcon#*before return 0, iclass 27, count 0 2006.257.07:04:47.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:47.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:47.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:04:47.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:04:47.18$vck44/valo=6,814.99 2006.257.07:04:47.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.07:04:47.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.07:04:47.18#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:47.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:47.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:47.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:47.18#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:04:47.18#ibcon#first serial, iclass 29, count 0 2006.257.07:04:47.18#ibcon#enter sib2, iclass 29, count 0 2006.257.07:04:47.18#ibcon#flushed, iclass 29, count 0 2006.257.07:04:47.18#ibcon#about to write, iclass 29, count 0 2006.257.07:04:47.18#ibcon#wrote, iclass 29, count 0 2006.257.07:04:47.18#ibcon#about to read 3, iclass 29, count 0 2006.257.07:04:47.20#ibcon#read 3, iclass 29, count 0 2006.257.07:04:47.20#ibcon#about to read 4, iclass 29, count 0 2006.257.07:04:47.20#ibcon#read 4, iclass 29, count 0 2006.257.07:04:47.20#ibcon#about to read 5, iclass 29, count 0 2006.257.07:04:47.20#ibcon#read 5, iclass 29, count 0 2006.257.07:04:47.20#ibcon#about to read 6, iclass 29, count 0 2006.257.07:04:47.20#ibcon#read 6, iclass 29, count 0 2006.257.07:04:47.20#ibcon#end of sib2, iclass 29, count 0 2006.257.07:04:47.20#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:04:47.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:04:47.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.07:04:47.20#ibcon#*before write, iclass 29, count 0 2006.257.07:04:47.20#ibcon#enter sib2, iclass 29, count 0 2006.257.07:04:47.20#ibcon#flushed, iclass 29, count 0 2006.257.07:04:47.20#ibcon#about to write, iclass 29, count 0 2006.257.07:04:47.20#ibcon#wrote, iclass 29, count 0 2006.257.07:04:47.20#ibcon#about to read 3, iclass 29, count 0 2006.257.07:04:47.24#ibcon#read 3, iclass 29, count 0 2006.257.07:04:47.24#ibcon#about to read 4, iclass 29, count 0 2006.257.07:04:47.24#ibcon#read 4, iclass 29, count 0 2006.257.07:04:47.24#ibcon#about to read 5, iclass 29, count 0 2006.257.07:04:47.24#ibcon#read 5, iclass 29, count 0 2006.257.07:04:47.24#ibcon#about to read 6, iclass 29, count 0 2006.257.07:04:47.24#ibcon#read 6, iclass 29, count 0 2006.257.07:04:47.24#ibcon#end of sib2, iclass 29, count 0 2006.257.07:04:47.24#ibcon#*after write, iclass 29, count 0 2006.257.07:04:47.24#ibcon#*before return 0, iclass 29, count 0 2006.257.07:04:47.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:47.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:47.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:04:47.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:04:47.24$vck44/va=6,4 2006.257.07:04:47.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.07:04:47.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.07:04:47.24#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:47.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:47.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:47.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:47.30#ibcon#enter wrdev, iclass 31, count 2 2006.257.07:04:47.30#ibcon#first serial, iclass 31, count 2 2006.257.07:04:47.30#ibcon#enter sib2, iclass 31, count 2 2006.257.07:04:47.30#ibcon#flushed, iclass 31, count 2 2006.257.07:04:47.30#ibcon#about to write, iclass 31, count 2 2006.257.07:04:47.30#ibcon#wrote, iclass 31, count 2 2006.257.07:04:47.30#ibcon#about to read 3, iclass 31, count 2 2006.257.07:04:47.32#ibcon#read 3, iclass 31, count 2 2006.257.07:04:47.32#ibcon#about to read 4, iclass 31, count 2 2006.257.07:04:47.32#ibcon#read 4, iclass 31, count 2 2006.257.07:04:47.32#ibcon#about to read 5, iclass 31, count 2 2006.257.07:04:47.32#ibcon#read 5, iclass 31, count 2 2006.257.07:04:47.32#ibcon#about to read 6, iclass 31, count 2 2006.257.07:04:47.32#ibcon#read 6, iclass 31, count 2 2006.257.07:04:47.32#ibcon#end of sib2, iclass 31, count 2 2006.257.07:04:47.32#ibcon#*mode == 0, iclass 31, count 2 2006.257.07:04:47.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.07:04:47.32#ibcon#[25=AT06-04\r\n] 2006.257.07:04:47.32#ibcon#*before write, iclass 31, count 2 2006.257.07:04:47.32#ibcon#enter sib2, iclass 31, count 2 2006.257.07:04:47.32#ibcon#flushed, iclass 31, count 2 2006.257.07:04:47.32#ibcon#about to write, iclass 31, count 2 2006.257.07:04:47.32#ibcon#wrote, iclass 31, count 2 2006.257.07:04:47.32#ibcon#about to read 3, iclass 31, count 2 2006.257.07:04:47.35#ibcon#read 3, iclass 31, count 2 2006.257.07:04:47.35#ibcon#about to read 4, iclass 31, count 2 2006.257.07:04:47.35#ibcon#read 4, iclass 31, count 2 2006.257.07:04:47.35#ibcon#about to read 5, iclass 31, count 2 2006.257.07:04:47.35#ibcon#read 5, iclass 31, count 2 2006.257.07:04:47.35#ibcon#about to read 6, iclass 31, count 2 2006.257.07:04:47.35#ibcon#read 6, iclass 31, count 2 2006.257.07:04:47.35#ibcon#end of sib2, iclass 31, count 2 2006.257.07:04:47.35#ibcon#*after write, iclass 31, count 2 2006.257.07:04:47.35#ibcon#*before return 0, iclass 31, count 2 2006.257.07:04:47.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:47.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:47.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.07:04:47.35#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:47.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:47.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:47.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:47.47#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:04:47.47#ibcon#first serial, iclass 31, count 0 2006.257.07:04:47.47#ibcon#enter sib2, iclass 31, count 0 2006.257.07:04:47.47#ibcon#flushed, iclass 31, count 0 2006.257.07:04:47.47#ibcon#about to write, iclass 31, count 0 2006.257.07:04:47.47#ibcon#wrote, iclass 31, count 0 2006.257.07:04:47.47#ibcon#about to read 3, iclass 31, count 0 2006.257.07:04:47.49#ibcon#read 3, iclass 31, count 0 2006.257.07:04:47.49#ibcon#about to read 4, iclass 31, count 0 2006.257.07:04:47.49#ibcon#read 4, iclass 31, count 0 2006.257.07:04:47.49#ibcon#about to read 5, iclass 31, count 0 2006.257.07:04:47.49#ibcon#read 5, iclass 31, count 0 2006.257.07:04:47.49#ibcon#about to read 6, iclass 31, count 0 2006.257.07:04:47.49#ibcon#read 6, iclass 31, count 0 2006.257.07:04:47.49#ibcon#end of sib2, iclass 31, count 0 2006.257.07:04:47.49#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:04:47.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:04:47.49#ibcon#[25=USB\r\n] 2006.257.07:04:47.49#ibcon#*before write, iclass 31, count 0 2006.257.07:04:47.49#ibcon#enter sib2, iclass 31, count 0 2006.257.07:04:47.49#ibcon#flushed, iclass 31, count 0 2006.257.07:04:47.49#ibcon#about to write, iclass 31, count 0 2006.257.07:04:47.49#ibcon#wrote, iclass 31, count 0 2006.257.07:04:47.49#ibcon#about to read 3, iclass 31, count 0 2006.257.07:04:47.52#ibcon#read 3, iclass 31, count 0 2006.257.07:04:47.52#ibcon#about to read 4, iclass 31, count 0 2006.257.07:04:47.52#ibcon#read 4, iclass 31, count 0 2006.257.07:04:47.52#ibcon#about to read 5, iclass 31, count 0 2006.257.07:04:47.52#ibcon#read 5, iclass 31, count 0 2006.257.07:04:47.52#ibcon#about to read 6, iclass 31, count 0 2006.257.07:04:47.52#ibcon#read 6, iclass 31, count 0 2006.257.07:04:47.52#ibcon#end of sib2, iclass 31, count 0 2006.257.07:04:47.52#ibcon#*after write, iclass 31, count 0 2006.257.07:04:47.52#ibcon#*before return 0, iclass 31, count 0 2006.257.07:04:47.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:47.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:47.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:04:47.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:04:47.52$vck44/valo=7,864.99 2006.257.07:04:47.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.07:04:47.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.07:04:47.52#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:47.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:47.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:47.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:47.52#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:04:47.52#ibcon#first serial, iclass 33, count 0 2006.257.07:04:47.52#ibcon#enter sib2, iclass 33, count 0 2006.257.07:04:47.52#ibcon#flushed, iclass 33, count 0 2006.257.07:04:47.52#ibcon#about to write, iclass 33, count 0 2006.257.07:04:47.52#ibcon#wrote, iclass 33, count 0 2006.257.07:04:47.52#ibcon#about to read 3, iclass 33, count 0 2006.257.07:04:47.54#ibcon#read 3, iclass 33, count 0 2006.257.07:04:47.54#ibcon#about to read 4, iclass 33, count 0 2006.257.07:04:47.54#ibcon#read 4, iclass 33, count 0 2006.257.07:04:47.54#ibcon#about to read 5, iclass 33, count 0 2006.257.07:04:47.54#ibcon#read 5, iclass 33, count 0 2006.257.07:04:47.54#ibcon#about to read 6, iclass 33, count 0 2006.257.07:04:47.54#ibcon#read 6, iclass 33, count 0 2006.257.07:04:47.54#ibcon#end of sib2, iclass 33, count 0 2006.257.07:04:47.54#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:04:47.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:04:47.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.07:04:47.54#ibcon#*before write, iclass 33, count 0 2006.257.07:04:47.54#ibcon#enter sib2, iclass 33, count 0 2006.257.07:04:47.54#ibcon#flushed, iclass 33, count 0 2006.257.07:04:47.54#ibcon#about to write, iclass 33, count 0 2006.257.07:04:47.54#ibcon#wrote, iclass 33, count 0 2006.257.07:04:47.54#ibcon#about to read 3, iclass 33, count 0 2006.257.07:04:47.58#ibcon#read 3, iclass 33, count 0 2006.257.07:04:47.58#ibcon#about to read 4, iclass 33, count 0 2006.257.07:04:47.58#ibcon#read 4, iclass 33, count 0 2006.257.07:04:47.58#ibcon#about to read 5, iclass 33, count 0 2006.257.07:04:47.58#ibcon#read 5, iclass 33, count 0 2006.257.07:04:47.58#ibcon#about to read 6, iclass 33, count 0 2006.257.07:04:47.58#ibcon#read 6, iclass 33, count 0 2006.257.07:04:47.58#ibcon#end of sib2, iclass 33, count 0 2006.257.07:04:47.58#ibcon#*after write, iclass 33, count 0 2006.257.07:04:47.58#ibcon#*before return 0, iclass 33, count 0 2006.257.07:04:47.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:47.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:47.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:04:47.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:04:47.58$vck44/va=7,4 2006.257.07:04:47.58#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.07:04:47.58#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.07:04:47.58#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:47.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:47.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:47.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:47.64#ibcon#enter wrdev, iclass 35, count 2 2006.257.07:04:47.64#ibcon#first serial, iclass 35, count 2 2006.257.07:04:47.64#ibcon#enter sib2, iclass 35, count 2 2006.257.07:04:47.64#ibcon#flushed, iclass 35, count 2 2006.257.07:04:47.64#ibcon#about to write, iclass 35, count 2 2006.257.07:04:47.64#ibcon#wrote, iclass 35, count 2 2006.257.07:04:47.64#ibcon#about to read 3, iclass 35, count 2 2006.257.07:04:47.66#ibcon#read 3, iclass 35, count 2 2006.257.07:04:47.66#ibcon#about to read 4, iclass 35, count 2 2006.257.07:04:47.66#ibcon#read 4, iclass 35, count 2 2006.257.07:04:47.66#ibcon#about to read 5, iclass 35, count 2 2006.257.07:04:47.66#ibcon#read 5, iclass 35, count 2 2006.257.07:04:47.66#ibcon#about to read 6, iclass 35, count 2 2006.257.07:04:47.66#ibcon#read 6, iclass 35, count 2 2006.257.07:04:47.66#ibcon#end of sib2, iclass 35, count 2 2006.257.07:04:47.66#ibcon#*mode == 0, iclass 35, count 2 2006.257.07:04:47.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.07:04:47.66#ibcon#[25=AT07-04\r\n] 2006.257.07:04:47.66#ibcon#*before write, iclass 35, count 2 2006.257.07:04:47.66#ibcon#enter sib2, iclass 35, count 2 2006.257.07:04:47.66#ibcon#flushed, iclass 35, count 2 2006.257.07:04:47.66#ibcon#about to write, iclass 35, count 2 2006.257.07:04:47.66#ibcon#wrote, iclass 35, count 2 2006.257.07:04:47.66#ibcon#about to read 3, iclass 35, count 2 2006.257.07:04:47.69#ibcon#read 3, iclass 35, count 2 2006.257.07:04:47.69#ibcon#about to read 4, iclass 35, count 2 2006.257.07:04:47.69#ibcon#read 4, iclass 35, count 2 2006.257.07:04:47.69#ibcon#about to read 5, iclass 35, count 2 2006.257.07:04:47.69#ibcon#read 5, iclass 35, count 2 2006.257.07:04:47.69#ibcon#about to read 6, iclass 35, count 2 2006.257.07:04:47.69#ibcon#read 6, iclass 35, count 2 2006.257.07:04:47.69#ibcon#end of sib2, iclass 35, count 2 2006.257.07:04:47.69#ibcon#*after write, iclass 35, count 2 2006.257.07:04:47.69#ibcon#*before return 0, iclass 35, count 2 2006.257.07:04:47.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:47.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:47.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.07:04:47.69#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:47.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:47.75#abcon#<5=/16 1.5 3.9 20.93 881012.2\r\n> 2006.257.07:04:47.77#abcon#{5=INTERFACE CLEAR} 2006.257.07:04:47.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:47.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:47.81#ibcon#enter wrdev, iclass 35, count 0 2006.257.07:04:47.81#ibcon#first serial, iclass 35, count 0 2006.257.07:04:47.81#ibcon#enter sib2, iclass 35, count 0 2006.257.07:04:47.81#ibcon#flushed, iclass 35, count 0 2006.257.07:04:47.81#ibcon#about to write, iclass 35, count 0 2006.257.07:04:47.81#ibcon#wrote, iclass 35, count 0 2006.257.07:04:47.81#ibcon#about to read 3, iclass 35, count 0 2006.257.07:04:47.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:04:47.83#ibcon#read 3, iclass 35, count 0 2006.257.07:04:47.83#ibcon#about to read 4, iclass 35, count 0 2006.257.07:04:47.83#ibcon#read 4, iclass 35, count 0 2006.257.07:04:47.83#ibcon#about to read 5, iclass 35, count 0 2006.257.07:04:47.83#ibcon#read 5, iclass 35, count 0 2006.257.07:04:47.83#ibcon#about to read 6, iclass 35, count 0 2006.257.07:04:47.83#ibcon#read 6, iclass 35, count 0 2006.257.07:04:47.83#ibcon#end of sib2, iclass 35, count 0 2006.257.07:04:47.83#ibcon#*mode == 0, iclass 35, count 0 2006.257.07:04:47.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.07:04:47.83#ibcon#[25=USB\r\n] 2006.257.07:04:47.83#ibcon#*before write, iclass 35, count 0 2006.257.07:04:47.83#ibcon#enter sib2, iclass 35, count 0 2006.257.07:04:47.83#ibcon#flushed, iclass 35, count 0 2006.257.07:04:47.83#ibcon#about to write, iclass 35, count 0 2006.257.07:04:47.83#ibcon#wrote, iclass 35, count 0 2006.257.07:04:47.83#ibcon#about to read 3, iclass 35, count 0 2006.257.07:04:47.86#ibcon#read 3, iclass 35, count 0 2006.257.07:04:47.86#ibcon#about to read 4, iclass 35, count 0 2006.257.07:04:47.86#ibcon#read 4, iclass 35, count 0 2006.257.07:04:47.86#ibcon#about to read 5, iclass 35, count 0 2006.257.07:04:47.86#ibcon#read 5, iclass 35, count 0 2006.257.07:04:47.86#ibcon#about to read 6, iclass 35, count 0 2006.257.07:04:47.86#ibcon#read 6, iclass 35, count 0 2006.257.07:04:47.86#ibcon#end of sib2, iclass 35, count 0 2006.257.07:04:47.86#ibcon#*after write, iclass 35, count 0 2006.257.07:04:47.86#ibcon#*before return 0, iclass 35, count 0 2006.257.07:04:47.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:47.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:47.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.07:04:47.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.07:04:47.86$vck44/valo=8,884.99 2006.257.07:04:47.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.07:04:47.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.07:04:47.86#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:47.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:47.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:47.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:47.86#ibcon#enter wrdev, iclass 3, count 0 2006.257.07:04:47.86#ibcon#first serial, iclass 3, count 0 2006.257.07:04:47.86#ibcon#enter sib2, iclass 3, count 0 2006.257.07:04:47.86#ibcon#flushed, iclass 3, count 0 2006.257.07:04:47.86#ibcon#about to write, iclass 3, count 0 2006.257.07:04:47.86#ibcon#wrote, iclass 3, count 0 2006.257.07:04:47.86#ibcon#about to read 3, iclass 3, count 0 2006.257.07:04:47.88#ibcon#read 3, iclass 3, count 0 2006.257.07:04:47.88#ibcon#about to read 4, iclass 3, count 0 2006.257.07:04:47.88#ibcon#read 4, iclass 3, count 0 2006.257.07:04:47.88#ibcon#about to read 5, iclass 3, count 0 2006.257.07:04:47.88#ibcon#read 5, iclass 3, count 0 2006.257.07:04:47.88#ibcon#about to read 6, iclass 3, count 0 2006.257.07:04:47.88#ibcon#read 6, iclass 3, count 0 2006.257.07:04:47.88#ibcon#end of sib2, iclass 3, count 0 2006.257.07:04:47.88#ibcon#*mode == 0, iclass 3, count 0 2006.257.07:04:47.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.07:04:47.88#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.07:04:47.88#ibcon#*before write, iclass 3, count 0 2006.257.07:04:47.88#ibcon#enter sib2, iclass 3, count 0 2006.257.07:04:47.88#ibcon#flushed, iclass 3, count 0 2006.257.07:04:47.88#ibcon#about to write, iclass 3, count 0 2006.257.07:04:47.88#ibcon#wrote, iclass 3, count 0 2006.257.07:04:47.88#ibcon#about to read 3, iclass 3, count 0 2006.257.07:04:47.92#ibcon#read 3, iclass 3, count 0 2006.257.07:04:47.92#ibcon#about to read 4, iclass 3, count 0 2006.257.07:04:47.92#ibcon#read 4, iclass 3, count 0 2006.257.07:04:47.92#ibcon#about to read 5, iclass 3, count 0 2006.257.07:04:47.92#ibcon#read 5, iclass 3, count 0 2006.257.07:04:47.92#ibcon#about to read 6, iclass 3, count 0 2006.257.07:04:47.92#ibcon#read 6, iclass 3, count 0 2006.257.07:04:47.92#ibcon#end of sib2, iclass 3, count 0 2006.257.07:04:47.92#ibcon#*after write, iclass 3, count 0 2006.257.07:04:47.92#ibcon#*before return 0, iclass 3, count 0 2006.257.07:04:47.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:47.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:47.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.07:04:47.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.07:04:47.92$vck44/va=8,4 2006.257.07:04:47.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.07:04:47.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.07:04:47.92#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:47.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:04:47.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:04:47.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:04:47.98#ibcon#enter wrdev, iclass 5, count 2 2006.257.07:04:47.98#ibcon#first serial, iclass 5, count 2 2006.257.07:04:47.98#ibcon#enter sib2, iclass 5, count 2 2006.257.07:04:47.98#ibcon#flushed, iclass 5, count 2 2006.257.07:04:47.98#ibcon#about to write, iclass 5, count 2 2006.257.07:04:47.98#ibcon#wrote, iclass 5, count 2 2006.257.07:04:47.98#ibcon#about to read 3, iclass 5, count 2 2006.257.07:04:48.00#ibcon#read 3, iclass 5, count 2 2006.257.07:04:48.00#ibcon#about to read 4, iclass 5, count 2 2006.257.07:04:48.00#ibcon#read 4, iclass 5, count 2 2006.257.07:04:48.00#ibcon#about to read 5, iclass 5, count 2 2006.257.07:04:48.00#ibcon#read 5, iclass 5, count 2 2006.257.07:04:48.00#ibcon#about to read 6, iclass 5, count 2 2006.257.07:04:48.00#ibcon#read 6, iclass 5, count 2 2006.257.07:04:48.00#ibcon#end of sib2, iclass 5, count 2 2006.257.07:04:48.00#ibcon#*mode == 0, iclass 5, count 2 2006.257.07:04:48.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.07:04:48.00#ibcon#[25=AT08-04\r\n] 2006.257.07:04:48.00#ibcon#*before write, iclass 5, count 2 2006.257.07:04:48.00#ibcon#enter sib2, iclass 5, count 2 2006.257.07:04:48.00#ibcon#flushed, iclass 5, count 2 2006.257.07:04:48.00#ibcon#about to write, iclass 5, count 2 2006.257.07:04:48.00#ibcon#wrote, iclass 5, count 2 2006.257.07:04:48.00#ibcon#about to read 3, iclass 5, count 2 2006.257.07:04:48.03#ibcon#read 3, iclass 5, count 2 2006.257.07:04:48.03#ibcon#about to read 4, iclass 5, count 2 2006.257.07:04:48.03#ibcon#read 4, iclass 5, count 2 2006.257.07:04:48.03#ibcon#about to read 5, iclass 5, count 2 2006.257.07:04:48.03#ibcon#read 5, iclass 5, count 2 2006.257.07:04:48.03#ibcon#about to read 6, iclass 5, count 2 2006.257.07:04:48.03#ibcon#read 6, iclass 5, count 2 2006.257.07:04:48.03#ibcon#end of sib2, iclass 5, count 2 2006.257.07:04:48.03#ibcon#*after write, iclass 5, count 2 2006.257.07:04:48.03#ibcon#*before return 0, iclass 5, count 2 2006.257.07:04:48.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:04:48.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:04:48.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.07:04:48.03#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:48.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:04:48.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:04:48.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:04:48.15#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:04:48.15#ibcon#first serial, iclass 5, count 0 2006.257.07:04:48.15#ibcon#enter sib2, iclass 5, count 0 2006.257.07:04:48.15#ibcon#flushed, iclass 5, count 0 2006.257.07:04:48.15#ibcon#about to write, iclass 5, count 0 2006.257.07:04:48.15#ibcon#wrote, iclass 5, count 0 2006.257.07:04:48.15#ibcon#about to read 3, iclass 5, count 0 2006.257.07:04:48.17#ibcon#read 3, iclass 5, count 0 2006.257.07:04:48.17#ibcon#about to read 4, iclass 5, count 0 2006.257.07:04:48.17#ibcon#read 4, iclass 5, count 0 2006.257.07:04:48.17#ibcon#about to read 5, iclass 5, count 0 2006.257.07:04:48.17#ibcon#read 5, iclass 5, count 0 2006.257.07:04:48.17#ibcon#about to read 6, iclass 5, count 0 2006.257.07:04:48.17#ibcon#read 6, iclass 5, count 0 2006.257.07:04:48.17#ibcon#end of sib2, iclass 5, count 0 2006.257.07:04:48.17#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:04:48.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:04:48.17#ibcon#[25=USB\r\n] 2006.257.07:04:48.17#ibcon#*before write, iclass 5, count 0 2006.257.07:04:48.17#ibcon#enter sib2, iclass 5, count 0 2006.257.07:04:48.17#ibcon#flushed, iclass 5, count 0 2006.257.07:04:48.17#ibcon#about to write, iclass 5, count 0 2006.257.07:04:48.17#ibcon#wrote, iclass 5, count 0 2006.257.07:04:48.17#ibcon#about to read 3, iclass 5, count 0 2006.257.07:04:48.20#ibcon#read 3, iclass 5, count 0 2006.257.07:04:48.20#ibcon#about to read 4, iclass 5, count 0 2006.257.07:04:48.20#ibcon#read 4, iclass 5, count 0 2006.257.07:04:48.20#ibcon#about to read 5, iclass 5, count 0 2006.257.07:04:48.20#ibcon#read 5, iclass 5, count 0 2006.257.07:04:48.20#ibcon#about to read 6, iclass 5, count 0 2006.257.07:04:48.20#ibcon#read 6, iclass 5, count 0 2006.257.07:04:48.20#ibcon#end of sib2, iclass 5, count 0 2006.257.07:04:48.20#ibcon#*after write, iclass 5, count 0 2006.257.07:04:48.20#ibcon#*before return 0, iclass 5, count 0 2006.257.07:04:48.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:04:48.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:04:48.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:04:48.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:04:48.20$vck44/vblo=1,629.99 2006.257.07:04:48.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.07:04:48.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.07:04:48.20#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:48.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:48.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:48.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:48.20#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:04:48.20#ibcon#first serial, iclass 7, count 0 2006.257.07:04:48.20#ibcon#enter sib2, iclass 7, count 0 2006.257.07:04:48.20#ibcon#flushed, iclass 7, count 0 2006.257.07:04:48.20#ibcon#about to write, iclass 7, count 0 2006.257.07:04:48.20#ibcon#wrote, iclass 7, count 0 2006.257.07:04:48.20#ibcon#about to read 3, iclass 7, count 0 2006.257.07:04:48.22#ibcon#read 3, iclass 7, count 0 2006.257.07:04:48.22#ibcon#about to read 4, iclass 7, count 0 2006.257.07:04:48.22#ibcon#read 4, iclass 7, count 0 2006.257.07:04:48.22#ibcon#about to read 5, iclass 7, count 0 2006.257.07:04:48.22#ibcon#read 5, iclass 7, count 0 2006.257.07:04:48.22#ibcon#about to read 6, iclass 7, count 0 2006.257.07:04:48.22#ibcon#read 6, iclass 7, count 0 2006.257.07:04:48.22#ibcon#end of sib2, iclass 7, count 0 2006.257.07:04:48.22#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:04:48.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:04:48.22#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.07:04:48.22#ibcon#*before write, iclass 7, count 0 2006.257.07:04:48.22#ibcon#enter sib2, iclass 7, count 0 2006.257.07:04:48.22#ibcon#flushed, iclass 7, count 0 2006.257.07:04:48.22#ibcon#about to write, iclass 7, count 0 2006.257.07:04:48.22#ibcon#wrote, iclass 7, count 0 2006.257.07:04:48.22#ibcon#about to read 3, iclass 7, count 0 2006.257.07:04:48.26#ibcon#read 3, iclass 7, count 0 2006.257.07:04:48.26#ibcon#about to read 4, iclass 7, count 0 2006.257.07:04:48.26#ibcon#read 4, iclass 7, count 0 2006.257.07:04:48.26#ibcon#about to read 5, iclass 7, count 0 2006.257.07:04:48.26#ibcon#read 5, iclass 7, count 0 2006.257.07:04:48.26#ibcon#about to read 6, iclass 7, count 0 2006.257.07:04:48.26#ibcon#read 6, iclass 7, count 0 2006.257.07:04:48.26#ibcon#end of sib2, iclass 7, count 0 2006.257.07:04:48.26#ibcon#*after write, iclass 7, count 0 2006.257.07:04:48.26#ibcon#*before return 0, iclass 7, count 0 2006.257.07:04:48.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:48.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:04:48.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:04:48.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:04:48.26$vck44/vb=1,4 2006.257.07:04:48.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.07:04:48.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.07:04:48.26#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:48.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:48.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:48.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:48.26#ibcon#enter wrdev, iclass 11, count 2 2006.257.07:04:48.26#ibcon#first serial, iclass 11, count 2 2006.257.07:04:48.26#ibcon#enter sib2, iclass 11, count 2 2006.257.07:04:48.26#ibcon#flushed, iclass 11, count 2 2006.257.07:04:48.26#ibcon#about to write, iclass 11, count 2 2006.257.07:04:48.26#ibcon#wrote, iclass 11, count 2 2006.257.07:04:48.26#ibcon#about to read 3, iclass 11, count 2 2006.257.07:04:48.28#ibcon#read 3, iclass 11, count 2 2006.257.07:04:48.28#ibcon#about to read 4, iclass 11, count 2 2006.257.07:04:48.28#ibcon#read 4, iclass 11, count 2 2006.257.07:04:48.28#ibcon#about to read 5, iclass 11, count 2 2006.257.07:04:48.28#ibcon#read 5, iclass 11, count 2 2006.257.07:04:48.28#ibcon#about to read 6, iclass 11, count 2 2006.257.07:04:48.28#ibcon#read 6, iclass 11, count 2 2006.257.07:04:48.28#ibcon#end of sib2, iclass 11, count 2 2006.257.07:04:48.28#ibcon#*mode == 0, iclass 11, count 2 2006.257.07:04:48.28#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.07:04:48.28#ibcon#[27=AT01-04\r\n] 2006.257.07:04:48.28#ibcon#*before write, iclass 11, count 2 2006.257.07:04:48.28#ibcon#enter sib2, iclass 11, count 2 2006.257.07:04:48.28#ibcon#flushed, iclass 11, count 2 2006.257.07:04:48.28#ibcon#about to write, iclass 11, count 2 2006.257.07:04:48.28#ibcon#wrote, iclass 11, count 2 2006.257.07:04:48.28#ibcon#about to read 3, iclass 11, count 2 2006.257.07:04:48.31#ibcon#read 3, iclass 11, count 2 2006.257.07:04:48.31#ibcon#about to read 4, iclass 11, count 2 2006.257.07:04:48.31#ibcon#read 4, iclass 11, count 2 2006.257.07:04:48.31#ibcon#about to read 5, iclass 11, count 2 2006.257.07:04:48.31#ibcon#read 5, iclass 11, count 2 2006.257.07:04:48.31#ibcon#about to read 6, iclass 11, count 2 2006.257.07:04:48.31#ibcon#read 6, iclass 11, count 2 2006.257.07:04:48.31#ibcon#end of sib2, iclass 11, count 2 2006.257.07:04:48.31#ibcon#*after write, iclass 11, count 2 2006.257.07:04:48.31#ibcon#*before return 0, iclass 11, count 2 2006.257.07:04:48.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:48.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:04:48.31#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.07:04:48.31#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:48.31#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:48.43#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:48.43#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:48.43#ibcon#enter wrdev, iclass 11, count 0 2006.257.07:04:48.43#ibcon#first serial, iclass 11, count 0 2006.257.07:04:48.43#ibcon#enter sib2, iclass 11, count 0 2006.257.07:04:48.43#ibcon#flushed, iclass 11, count 0 2006.257.07:04:48.43#ibcon#about to write, iclass 11, count 0 2006.257.07:04:48.43#ibcon#wrote, iclass 11, count 0 2006.257.07:04:48.43#ibcon#about to read 3, iclass 11, count 0 2006.257.07:04:48.45#ibcon#read 3, iclass 11, count 0 2006.257.07:04:48.45#ibcon#about to read 4, iclass 11, count 0 2006.257.07:04:48.45#ibcon#read 4, iclass 11, count 0 2006.257.07:04:48.45#ibcon#about to read 5, iclass 11, count 0 2006.257.07:04:48.45#ibcon#read 5, iclass 11, count 0 2006.257.07:04:48.45#ibcon#about to read 6, iclass 11, count 0 2006.257.07:04:48.45#ibcon#read 6, iclass 11, count 0 2006.257.07:04:48.45#ibcon#end of sib2, iclass 11, count 0 2006.257.07:04:48.45#ibcon#*mode == 0, iclass 11, count 0 2006.257.07:04:48.45#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.07:04:48.45#ibcon#[27=USB\r\n] 2006.257.07:04:48.45#ibcon#*before write, iclass 11, count 0 2006.257.07:04:48.45#ibcon#enter sib2, iclass 11, count 0 2006.257.07:04:48.45#ibcon#flushed, iclass 11, count 0 2006.257.07:04:48.45#ibcon#about to write, iclass 11, count 0 2006.257.07:04:48.45#ibcon#wrote, iclass 11, count 0 2006.257.07:04:48.45#ibcon#about to read 3, iclass 11, count 0 2006.257.07:04:48.48#ibcon#read 3, iclass 11, count 0 2006.257.07:04:48.48#ibcon#about to read 4, iclass 11, count 0 2006.257.07:04:48.48#ibcon#read 4, iclass 11, count 0 2006.257.07:04:48.48#ibcon#about to read 5, iclass 11, count 0 2006.257.07:04:48.48#ibcon#read 5, iclass 11, count 0 2006.257.07:04:48.48#ibcon#about to read 6, iclass 11, count 0 2006.257.07:04:48.48#ibcon#read 6, iclass 11, count 0 2006.257.07:04:48.48#ibcon#end of sib2, iclass 11, count 0 2006.257.07:04:48.48#ibcon#*after write, iclass 11, count 0 2006.257.07:04:48.48#ibcon#*before return 0, iclass 11, count 0 2006.257.07:04:48.48#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:48.48#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:04:48.48#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.07:04:48.48#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.07:04:48.48$vck44/vblo=2,634.99 2006.257.07:04:48.48#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.07:04:48.48#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.07:04:48.48#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:48.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:48.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:48.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:48.48#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:04:48.48#ibcon#first serial, iclass 13, count 0 2006.257.07:04:48.48#ibcon#enter sib2, iclass 13, count 0 2006.257.07:04:48.48#ibcon#flushed, iclass 13, count 0 2006.257.07:04:48.48#ibcon#about to write, iclass 13, count 0 2006.257.07:04:48.48#ibcon#wrote, iclass 13, count 0 2006.257.07:04:48.48#ibcon#about to read 3, iclass 13, count 0 2006.257.07:04:48.50#ibcon#read 3, iclass 13, count 0 2006.257.07:04:48.50#ibcon#about to read 4, iclass 13, count 0 2006.257.07:04:48.50#ibcon#read 4, iclass 13, count 0 2006.257.07:04:48.50#ibcon#about to read 5, iclass 13, count 0 2006.257.07:04:48.50#ibcon#read 5, iclass 13, count 0 2006.257.07:04:48.50#ibcon#about to read 6, iclass 13, count 0 2006.257.07:04:48.50#ibcon#read 6, iclass 13, count 0 2006.257.07:04:48.50#ibcon#end of sib2, iclass 13, count 0 2006.257.07:04:48.50#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:04:48.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:04:48.50#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.07:04:48.50#ibcon#*before write, iclass 13, count 0 2006.257.07:04:48.50#ibcon#enter sib2, iclass 13, count 0 2006.257.07:04:48.50#ibcon#flushed, iclass 13, count 0 2006.257.07:04:48.50#ibcon#about to write, iclass 13, count 0 2006.257.07:04:48.50#ibcon#wrote, iclass 13, count 0 2006.257.07:04:48.50#ibcon#about to read 3, iclass 13, count 0 2006.257.07:04:48.54#ibcon#read 3, iclass 13, count 0 2006.257.07:04:48.54#ibcon#about to read 4, iclass 13, count 0 2006.257.07:04:48.54#ibcon#read 4, iclass 13, count 0 2006.257.07:04:48.54#ibcon#about to read 5, iclass 13, count 0 2006.257.07:04:48.54#ibcon#read 5, iclass 13, count 0 2006.257.07:04:48.54#ibcon#about to read 6, iclass 13, count 0 2006.257.07:04:48.54#ibcon#read 6, iclass 13, count 0 2006.257.07:04:48.54#ibcon#end of sib2, iclass 13, count 0 2006.257.07:04:48.54#ibcon#*after write, iclass 13, count 0 2006.257.07:04:48.54#ibcon#*before return 0, iclass 13, count 0 2006.257.07:04:48.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:48.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:04:48.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:04:48.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:04:48.54$vck44/vb=2,5 2006.257.07:04:48.54#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.07:04:48.54#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.07:04:48.54#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:48.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:48.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:48.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:48.60#ibcon#enter wrdev, iclass 15, count 2 2006.257.07:04:48.60#ibcon#first serial, iclass 15, count 2 2006.257.07:04:48.60#ibcon#enter sib2, iclass 15, count 2 2006.257.07:04:48.60#ibcon#flushed, iclass 15, count 2 2006.257.07:04:48.60#ibcon#about to write, iclass 15, count 2 2006.257.07:04:48.60#ibcon#wrote, iclass 15, count 2 2006.257.07:04:48.60#ibcon#about to read 3, iclass 15, count 2 2006.257.07:04:48.62#ibcon#read 3, iclass 15, count 2 2006.257.07:04:48.62#ibcon#about to read 4, iclass 15, count 2 2006.257.07:04:48.62#ibcon#read 4, iclass 15, count 2 2006.257.07:04:48.62#ibcon#about to read 5, iclass 15, count 2 2006.257.07:04:48.62#ibcon#read 5, iclass 15, count 2 2006.257.07:04:48.62#ibcon#about to read 6, iclass 15, count 2 2006.257.07:04:48.62#ibcon#read 6, iclass 15, count 2 2006.257.07:04:48.62#ibcon#end of sib2, iclass 15, count 2 2006.257.07:04:48.62#ibcon#*mode == 0, iclass 15, count 2 2006.257.07:04:48.62#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.07:04:48.62#ibcon#[27=AT02-05\r\n] 2006.257.07:04:48.62#ibcon#*before write, iclass 15, count 2 2006.257.07:04:48.62#ibcon#enter sib2, iclass 15, count 2 2006.257.07:04:48.62#ibcon#flushed, iclass 15, count 2 2006.257.07:04:48.62#ibcon#about to write, iclass 15, count 2 2006.257.07:04:48.62#ibcon#wrote, iclass 15, count 2 2006.257.07:04:48.62#ibcon#about to read 3, iclass 15, count 2 2006.257.07:04:48.65#ibcon#read 3, iclass 15, count 2 2006.257.07:04:48.65#ibcon#about to read 4, iclass 15, count 2 2006.257.07:04:48.65#ibcon#read 4, iclass 15, count 2 2006.257.07:04:48.65#ibcon#about to read 5, iclass 15, count 2 2006.257.07:04:48.65#ibcon#read 5, iclass 15, count 2 2006.257.07:04:48.65#ibcon#about to read 6, iclass 15, count 2 2006.257.07:04:48.65#ibcon#read 6, iclass 15, count 2 2006.257.07:04:48.65#ibcon#end of sib2, iclass 15, count 2 2006.257.07:04:48.65#ibcon#*after write, iclass 15, count 2 2006.257.07:04:48.65#ibcon#*before return 0, iclass 15, count 2 2006.257.07:04:48.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:48.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:04:48.65#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.07:04:48.65#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:48.65#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:48.77#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:48.77#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:48.77#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:04:48.77#ibcon#first serial, iclass 15, count 0 2006.257.07:04:48.77#ibcon#enter sib2, iclass 15, count 0 2006.257.07:04:48.77#ibcon#flushed, iclass 15, count 0 2006.257.07:04:48.77#ibcon#about to write, iclass 15, count 0 2006.257.07:04:48.77#ibcon#wrote, iclass 15, count 0 2006.257.07:04:48.77#ibcon#about to read 3, iclass 15, count 0 2006.257.07:04:48.79#ibcon#read 3, iclass 15, count 0 2006.257.07:04:48.79#ibcon#about to read 4, iclass 15, count 0 2006.257.07:04:48.79#ibcon#read 4, iclass 15, count 0 2006.257.07:04:48.79#ibcon#about to read 5, iclass 15, count 0 2006.257.07:04:48.79#ibcon#read 5, iclass 15, count 0 2006.257.07:04:48.79#ibcon#about to read 6, iclass 15, count 0 2006.257.07:04:48.79#ibcon#read 6, iclass 15, count 0 2006.257.07:04:48.79#ibcon#end of sib2, iclass 15, count 0 2006.257.07:04:48.79#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:04:48.79#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:04:48.79#ibcon#[27=USB\r\n] 2006.257.07:04:48.79#ibcon#*before write, iclass 15, count 0 2006.257.07:04:48.79#ibcon#enter sib2, iclass 15, count 0 2006.257.07:04:48.79#ibcon#flushed, iclass 15, count 0 2006.257.07:04:48.79#ibcon#about to write, iclass 15, count 0 2006.257.07:04:48.79#ibcon#wrote, iclass 15, count 0 2006.257.07:04:48.79#ibcon#about to read 3, iclass 15, count 0 2006.257.07:04:48.82#ibcon#read 3, iclass 15, count 0 2006.257.07:04:48.82#ibcon#about to read 4, iclass 15, count 0 2006.257.07:04:48.82#ibcon#read 4, iclass 15, count 0 2006.257.07:04:48.82#ibcon#about to read 5, iclass 15, count 0 2006.257.07:04:48.82#ibcon#read 5, iclass 15, count 0 2006.257.07:04:48.82#ibcon#about to read 6, iclass 15, count 0 2006.257.07:04:48.82#ibcon#read 6, iclass 15, count 0 2006.257.07:04:48.82#ibcon#end of sib2, iclass 15, count 0 2006.257.07:04:48.82#ibcon#*after write, iclass 15, count 0 2006.257.07:04:48.82#ibcon#*before return 0, iclass 15, count 0 2006.257.07:04:48.82#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:48.82#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:04:48.82#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:04:48.82#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:04:48.82$vck44/vblo=3,649.99 2006.257.07:04:48.82#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.07:04:48.82#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.07:04:48.82#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:48.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:48.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:48.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:48.82#ibcon#enter wrdev, iclass 17, count 0 2006.257.07:04:48.82#ibcon#first serial, iclass 17, count 0 2006.257.07:04:48.82#ibcon#enter sib2, iclass 17, count 0 2006.257.07:04:48.82#ibcon#flushed, iclass 17, count 0 2006.257.07:04:48.82#ibcon#about to write, iclass 17, count 0 2006.257.07:04:48.82#ibcon#wrote, iclass 17, count 0 2006.257.07:04:48.82#ibcon#about to read 3, iclass 17, count 0 2006.257.07:04:48.84#ibcon#read 3, iclass 17, count 0 2006.257.07:04:48.84#ibcon#about to read 4, iclass 17, count 0 2006.257.07:04:48.84#ibcon#read 4, iclass 17, count 0 2006.257.07:04:48.84#ibcon#about to read 5, iclass 17, count 0 2006.257.07:04:48.84#ibcon#read 5, iclass 17, count 0 2006.257.07:04:48.84#ibcon#about to read 6, iclass 17, count 0 2006.257.07:04:48.84#ibcon#read 6, iclass 17, count 0 2006.257.07:04:48.84#ibcon#end of sib2, iclass 17, count 0 2006.257.07:04:48.84#ibcon#*mode == 0, iclass 17, count 0 2006.257.07:04:48.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.07:04:48.84#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.07:04:48.84#ibcon#*before write, iclass 17, count 0 2006.257.07:04:48.84#ibcon#enter sib2, iclass 17, count 0 2006.257.07:04:48.84#ibcon#flushed, iclass 17, count 0 2006.257.07:04:48.84#ibcon#about to write, iclass 17, count 0 2006.257.07:04:48.84#ibcon#wrote, iclass 17, count 0 2006.257.07:04:48.84#ibcon#about to read 3, iclass 17, count 0 2006.257.07:04:48.88#ibcon#read 3, iclass 17, count 0 2006.257.07:04:48.88#ibcon#about to read 4, iclass 17, count 0 2006.257.07:04:48.88#ibcon#read 4, iclass 17, count 0 2006.257.07:04:48.88#ibcon#about to read 5, iclass 17, count 0 2006.257.07:04:48.88#ibcon#read 5, iclass 17, count 0 2006.257.07:04:48.88#ibcon#about to read 6, iclass 17, count 0 2006.257.07:04:48.88#ibcon#read 6, iclass 17, count 0 2006.257.07:04:48.88#ibcon#end of sib2, iclass 17, count 0 2006.257.07:04:48.88#ibcon#*after write, iclass 17, count 0 2006.257.07:04:48.88#ibcon#*before return 0, iclass 17, count 0 2006.257.07:04:48.88#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:48.88#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:04:48.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.07:04:48.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.07:04:48.88$vck44/vb=3,4 2006.257.07:04:48.88#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.07:04:48.88#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.07:04:48.88#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:48.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:48.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:48.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:48.94#ibcon#enter wrdev, iclass 19, count 2 2006.257.07:04:48.94#ibcon#first serial, iclass 19, count 2 2006.257.07:04:48.94#ibcon#enter sib2, iclass 19, count 2 2006.257.07:04:48.94#ibcon#flushed, iclass 19, count 2 2006.257.07:04:48.94#ibcon#about to write, iclass 19, count 2 2006.257.07:04:48.94#ibcon#wrote, iclass 19, count 2 2006.257.07:04:48.94#ibcon#about to read 3, iclass 19, count 2 2006.257.07:04:48.96#ibcon#read 3, iclass 19, count 2 2006.257.07:04:48.96#ibcon#about to read 4, iclass 19, count 2 2006.257.07:04:48.96#ibcon#read 4, iclass 19, count 2 2006.257.07:04:48.96#ibcon#about to read 5, iclass 19, count 2 2006.257.07:04:48.96#ibcon#read 5, iclass 19, count 2 2006.257.07:04:48.96#ibcon#about to read 6, iclass 19, count 2 2006.257.07:04:48.96#ibcon#read 6, iclass 19, count 2 2006.257.07:04:48.96#ibcon#end of sib2, iclass 19, count 2 2006.257.07:04:48.96#ibcon#*mode == 0, iclass 19, count 2 2006.257.07:04:48.96#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.07:04:48.96#ibcon#[27=AT03-04\r\n] 2006.257.07:04:48.96#ibcon#*before write, iclass 19, count 2 2006.257.07:04:48.96#ibcon#enter sib2, iclass 19, count 2 2006.257.07:04:48.96#ibcon#flushed, iclass 19, count 2 2006.257.07:04:48.96#ibcon#about to write, iclass 19, count 2 2006.257.07:04:48.96#ibcon#wrote, iclass 19, count 2 2006.257.07:04:48.96#ibcon#about to read 3, iclass 19, count 2 2006.257.07:04:48.99#ibcon#read 3, iclass 19, count 2 2006.257.07:04:48.99#ibcon#about to read 4, iclass 19, count 2 2006.257.07:04:48.99#ibcon#read 4, iclass 19, count 2 2006.257.07:04:48.99#ibcon#about to read 5, iclass 19, count 2 2006.257.07:04:48.99#ibcon#read 5, iclass 19, count 2 2006.257.07:04:48.99#ibcon#about to read 6, iclass 19, count 2 2006.257.07:04:48.99#ibcon#read 6, iclass 19, count 2 2006.257.07:04:48.99#ibcon#end of sib2, iclass 19, count 2 2006.257.07:04:48.99#ibcon#*after write, iclass 19, count 2 2006.257.07:04:48.99#ibcon#*before return 0, iclass 19, count 2 2006.257.07:04:48.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:48.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:04:48.99#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.07:04:48.99#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:48.99#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:49.11#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:49.11#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:49.11#ibcon#enter wrdev, iclass 19, count 0 2006.257.07:04:49.11#ibcon#first serial, iclass 19, count 0 2006.257.07:04:49.11#ibcon#enter sib2, iclass 19, count 0 2006.257.07:04:49.11#ibcon#flushed, iclass 19, count 0 2006.257.07:04:49.11#ibcon#about to write, iclass 19, count 0 2006.257.07:04:49.11#ibcon#wrote, iclass 19, count 0 2006.257.07:04:49.11#ibcon#about to read 3, iclass 19, count 0 2006.257.07:04:49.13#ibcon#read 3, iclass 19, count 0 2006.257.07:04:49.13#ibcon#about to read 4, iclass 19, count 0 2006.257.07:04:49.13#ibcon#read 4, iclass 19, count 0 2006.257.07:04:49.13#ibcon#about to read 5, iclass 19, count 0 2006.257.07:04:49.13#ibcon#read 5, iclass 19, count 0 2006.257.07:04:49.13#ibcon#about to read 6, iclass 19, count 0 2006.257.07:04:49.13#ibcon#read 6, iclass 19, count 0 2006.257.07:04:49.13#ibcon#end of sib2, iclass 19, count 0 2006.257.07:04:49.13#ibcon#*mode == 0, iclass 19, count 0 2006.257.07:04:49.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.07:04:49.13#ibcon#[27=USB\r\n] 2006.257.07:04:49.13#ibcon#*before write, iclass 19, count 0 2006.257.07:04:49.13#ibcon#enter sib2, iclass 19, count 0 2006.257.07:04:49.13#ibcon#flushed, iclass 19, count 0 2006.257.07:04:49.13#ibcon#about to write, iclass 19, count 0 2006.257.07:04:49.13#ibcon#wrote, iclass 19, count 0 2006.257.07:04:49.13#ibcon#about to read 3, iclass 19, count 0 2006.257.07:04:49.16#ibcon#read 3, iclass 19, count 0 2006.257.07:04:49.16#ibcon#about to read 4, iclass 19, count 0 2006.257.07:04:49.16#ibcon#read 4, iclass 19, count 0 2006.257.07:04:49.16#ibcon#about to read 5, iclass 19, count 0 2006.257.07:04:49.16#ibcon#read 5, iclass 19, count 0 2006.257.07:04:49.16#ibcon#about to read 6, iclass 19, count 0 2006.257.07:04:49.16#ibcon#read 6, iclass 19, count 0 2006.257.07:04:49.16#ibcon#end of sib2, iclass 19, count 0 2006.257.07:04:49.16#ibcon#*after write, iclass 19, count 0 2006.257.07:04:49.16#ibcon#*before return 0, iclass 19, count 0 2006.257.07:04:49.16#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:49.16#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:04:49.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.07:04:49.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.07:04:49.16$vck44/vblo=4,679.99 2006.257.07:04:49.16#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.07:04:49.16#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.07:04:49.16#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:49.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:49.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:49.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:49.16#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:04:49.16#ibcon#first serial, iclass 21, count 0 2006.257.07:04:49.16#ibcon#enter sib2, iclass 21, count 0 2006.257.07:04:49.16#ibcon#flushed, iclass 21, count 0 2006.257.07:04:49.16#ibcon#about to write, iclass 21, count 0 2006.257.07:04:49.16#ibcon#wrote, iclass 21, count 0 2006.257.07:04:49.16#ibcon#about to read 3, iclass 21, count 0 2006.257.07:04:49.18#ibcon#read 3, iclass 21, count 0 2006.257.07:04:49.18#ibcon#about to read 4, iclass 21, count 0 2006.257.07:04:49.18#ibcon#read 4, iclass 21, count 0 2006.257.07:04:49.18#ibcon#about to read 5, iclass 21, count 0 2006.257.07:04:49.18#ibcon#read 5, iclass 21, count 0 2006.257.07:04:49.18#ibcon#about to read 6, iclass 21, count 0 2006.257.07:04:49.18#ibcon#read 6, iclass 21, count 0 2006.257.07:04:49.18#ibcon#end of sib2, iclass 21, count 0 2006.257.07:04:49.18#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:04:49.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:04:49.18#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.07:04:49.18#ibcon#*before write, iclass 21, count 0 2006.257.07:04:49.18#ibcon#enter sib2, iclass 21, count 0 2006.257.07:04:49.18#ibcon#flushed, iclass 21, count 0 2006.257.07:04:49.18#ibcon#about to write, iclass 21, count 0 2006.257.07:04:49.18#ibcon#wrote, iclass 21, count 0 2006.257.07:04:49.18#ibcon#about to read 3, iclass 21, count 0 2006.257.07:04:49.22#ibcon#read 3, iclass 21, count 0 2006.257.07:04:49.22#ibcon#about to read 4, iclass 21, count 0 2006.257.07:04:49.22#ibcon#read 4, iclass 21, count 0 2006.257.07:04:49.22#ibcon#about to read 5, iclass 21, count 0 2006.257.07:04:49.22#ibcon#read 5, iclass 21, count 0 2006.257.07:04:49.22#ibcon#about to read 6, iclass 21, count 0 2006.257.07:04:49.22#ibcon#read 6, iclass 21, count 0 2006.257.07:04:49.22#ibcon#end of sib2, iclass 21, count 0 2006.257.07:04:49.22#ibcon#*after write, iclass 21, count 0 2006.257.07:04:49.22#ibcon#*before return 0, iclass 21, count 0 2006.257.07:04:49.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:49.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:04:49.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:04:49.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:04:49.22$vck44/vb=4,5 2006.257.07:04:49.22#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.07:04:49.22#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.07:04:49.22#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:49.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:49.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:49.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:49.28#ibcon#enter wrdev, iclass 23, count 2 2006.257.07:04:49.28#ibcon#first serial, iclass 23, count 2 2006.257.07:04:49.28#ibcon#enter sib2, iclass 23, count 2 2006.257.07:04:49.28#ibcon#flushed, iclass 23, count 2 2006.257.07:04:49.28#ibcon#about to write, iclass 23, count 2 2006.257.07:04:49.28#ibcon#wrote, iclass 23, count 2 2006.257.07:04:49.28#ibcon#about to read 3, iclass 23, count 2 2006.257.07:04:49.30#ibcon#read 3, iclass 23, count 2 2006.257.07:04:49.30#ibcon#about to read 4, iclass 23, count 2 2006.257.07:04:49.30#ibcon#read 4, iclass 23, count 2 2006.257.07:04:49.30#ibcon#about to read 5, iclass 23, count 2 2006.257.07:04:49.30#ibcon#read 5, iclass 23, count 2 2006.257.07:04:49.30#ibcon#about to read 6, iclass 23, count 2 2006.257.07:04:49.30#ibcon#read 6, iclass 23, count 2 2006.257.07:04:49.30#ibcon#end of sib2, iclass 23, count 2 2006.257.07:04:49.30#ibcon#*mode == 0, iclass 23, count 2 2006.257.07:04:49.30#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.07:04:49.30#ibcon#[27=AT04-05\r\n] 2006.257.07:04:49.30#ibcon#*before write, iclass 23, count 2 2006.257.07:04:49.30#ibcon#enter sib2, iclass 23, count 2 2006.257.07:04:49.30#ibcon#flushed, iclass 23, count 2 2006.257.07:04:49.30#ibcon#about to write, iclass 23, count 2 2006.257.07:04:49.30#ibcon#wrote, iclass 23, count 2 2006.257.07:04:49.30#ibcon#about to read 3, iclass 23, count 2 2006.257.07:04:49.33#ibcon#read 3, iclass 23, count 2 2006.257.07:04:49.33#ibcon#about to read 4, iclass 23, count 2 2006.257.07:04:49.33#ibcon#read 4, iclass 23, count 2 2006.257.07:04:49.33#ibcon#about to read 5, iclass 23, count 2 2006.257.07:04:49.33#ibcon#read 5, iclass 23, count 2 2006.257.07:04:49.33#ibcon#about to read 6, iclass 23, count 2 2006.257.07:04:49.33#ibcon#read 6, iclass 23, count 2 2006.257.07:04:49.33#ibcon#end of sib2, iclass 23, count 2 2006.257.07:04:49.33#ibcon#*after write, iclass 23, count 2 2006.257.07:04:49.33#ibcon#*before return 0, iclass 23, count 2 2006.257.07:04:49.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:49.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:04:49.33#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.07:04:49.33#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:49.33#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:49.45#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:49.45#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:49.45#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:04:49.45#ibcon#first serial, iclass 23, count 0 2006.257.07:04:49.45#ibcon#enter sib2, iclass 23, count 0 2006.257.07:04:49.45#ibcon#flushed, iclass 23, count 0 2006.257.07:04:49.45#ibcon#about to write, iclass 23, count 0 2006.257.07:04:49.45#ibcon#wrote, iclass 23, count 0 2006.257.07:04:49.45#ibcon#about to read 3, iclass 23, count 0 2006.257.07:04:49.47#ibcon#read 3, iclass 23, count 0 2006.257.07:04:49.47#ibcon#about to read 4, iclass 23, count 0 2006.257.07:04:49.47#ibcon#read 4, iclass 23, count 0 2006.257.07:04:49.47#ibcon#about to read 5, iclass 23, count 0 2006.257.07:04:49.47#ibcon#read 5, iclass 23, count 0 2006.257.07:04:49.47#ibcon#about to read 6, iclass 23, count 0 2006.257.07:04:49.47#ibcon#read 6, iclass 23, count 0 2006.257.07:04:49.47#ibcon#end of sib2, iclass 23, count 0 2006.257.07:04:49.47#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:04:49.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:04:49.47#ibcon#[27=USB\r\n] 2006.257.07:04:49.47#ibcon#*before write, iclass 23, count 0 2006.257.07:04:49.47#ibcon#enter sib2, iclass 23, count 0 2006.257.07:04:49.47#ibcon#flushed, iclass 23, count 0 2006.257.07:04:49.47#ibcon#about to write, iclass 23, count 0 2006.257.07:04:49.47#ibcon#wrote, iclass 23, count 0 2006.257.07:04:49.47#ibcon#about to read 3, iclass 23, count 0 2006.257.07:04:49.50#ibcon#read 3, iclass 23, count 0 2006.257.07:04:49.50#ibcon#about to read 4, iclass 23, count 0 2006.257.07:04:49.50#ibcon#read 4, iclass 23, count 0 2006.257.07:04:49.50#ibcon#about to read 5, iclass 23, count 0 2006.257.07:04:49.50#ibcon#read 5, iclass 23, count 0 2006.257.07:04:49.50#ibcon#about to read 6, iclass 23, count 0 2006.257.07:04:49.50#ibcon#read 6, iclass 23, count 0 2006.257.07:04:49.50#ibcon#end of sib2, iclass 23, count 0 2006.257.07:04:49.50#ibcon#*after write, iclass 23, count 0 2006.257.07:04:49.50#ibcon#*before return 0, iclass 23, count 0 2006.257.07:04:49.50#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:49.50#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:04:49.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:04:49.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:04:49.50$vck44/vblo=5,709.99 2006.257.07:04:49.50#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.07:04:49.50#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.07:04:49.50#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:49.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:49.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:49.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:49.50#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:04:49.50#ibcon#first serial, iclass 25, count 0 2006.257.07:04:49.50#ibcon#enter sib2, iclass 25, count 0 2006.257.07:04:49.50#ibcon#flushed, iclass 25, count 0 2006.257.07:04:49.50#ibcon#about to write, iclass 25, count 0 2006.257.07:04:49.50#ibcon#wrote, iclass 25, count 0 2006.257.07:04:49.50#ibcon#about to read 3, iclass 25, count 0 2006.257.07:04:49.52#ibcon#read 3, iclass 25, count 0 2006.257.07:04:49.52#ibcon#about to read 4, iclass 25, count 0 2006.257.07:04:49.52#ibcon#read 4, iclass 25, count 0 2006.257.07:04:49.52#ibcon#about to read 5, iclass 25, count 0 2006.257.07:04:49.52#ibcon#read 5, iclass 25, count 0 2006.257.07:04:49.52#ibcon#about to read 6, iclass 25, count 0 2006.257.07:04:49.52#ibcon#read 6, iclass 25, count 0 2006.257.07:04:49.52#ibcon#end of sib2, iclass 25, count 0 2006.257.07:04:49.52#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:04:49.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:04:49.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.07:04:49.52#ibcon#*before write, iclass 25, count 0 2006.257.07:04:49.52#ibcon#enter sib2, iclass 25, count 0 2006.257.07:04:49.52#ibcon#flushed, iclass 25, count 0 2006.257.07:04:49.52#ibcon#about to write, iclass 25, count 0 2006.257.07:04:49.52#ibcon#wrote, iclass 25, count 0 2006.257.07:04:49.52#ibcon#about to read 3, iclass 25, count 0 2006.257.07:04:49.56#ibcon#read 3, iclass 25, count 0 2006.257.07:04:49.56#ibcon#about to read 4, iclass 25, count 0 2006.257.07:04:49.56#ibcon#read 4, iclass 25, count 0 2006.257.07:04:49.56#ibcon#about to read 5, iclass 25, count 0 2006.257.07:04:49.56#ibcon#read 5, iclass 25, count 0 2006.257.07:04:49.56#ibcon#about to read 6, iclass 25, count 0 2006.257.07:04:49.56#ibcon#read 6, iclass 25, count 0 2006.257.07:04:49.56#ibcon#end of sib2, iclass 25, count 0 2006.257.07:04:49.56#ibcon#*after write, iclass 25, count 0 2006.257.07:04:49.56#ibcon#*before return 0, iclass 25, count 0 2006.257.07:04:49.56#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:49.56#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:04:49.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:04:49.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:04:49.56$vck44/vb=5,4 2006.257.07:04:49.56#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.07:04:49.56#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.07:04:49.56#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:49.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:49.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:49.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:49.62#ibcon#enter wrdev, iclass 27, count 2 2006.257.07:04:49.62#ibcon#first serial, iclass 27, count 2 2006.257.07:04:49.62#ibcon#enter sib2, iclass 27, count 2 2006.257.07:04:49.62#ibcon#flushed, iclass 27, count 2 2006.257.07:04:49.62#ibcon#about to write, iclass 27, count 2 2006.257.07:04:49.62#ibcon#wrote, iclass 27, count 2 2006.257.07:04:49.62#ibcon#about to read 3, iclass 27, count 2 2006.257.07:04:49.64#ibcon#read 3, iclass 27, count 2 2006.257.07:04:49.64#ibcon#about to read 4, iclass 27, count 2 2006.257.07:04:49.64#ibcon#read 4, iclass 27, count 2 2006.257.07:04:49.64#ibcon#about to read 5, iclass 27, count 2 2006.257.07:04:49.64#ibcon#read 5, iclass 27, count 2 2006.257.07:04:49.64#ibcon#about to read 6, iclass 27, count 2 2006.257.07:04:49.64#ibcon#read 6, iclass 27, count 2 2006.257.07:04:49.64#ibcon#end of sib2, iclass 27, count 2 2006.257.07:04:49.64#ibcon#*mode == 0, iclass 27, count 2 2006.257.07:04:49.64#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.07:04:49.64#ibcon#[27=AT05-04\r\n] 2006.257.07:04:49.64#ibcon#*before write, iclass 27, count 2 2006.257.07:04:49.64#ibcon#enter sib2, iclass 27, count 2 2006.257.07:04:49.64#ibcon#flushed, iclass 27, count 2 2006.257.07:04:49.64#ibcon#about to write, iclass 27, count 2 2006.257.07:04:49.64#ibcon#wrote, iclass 27, count 2 2006.257.07:04:49.64#ibcon#about to read 3, iclass 27, count 2 2006.257.07:04:49.67#ibcon#read 3, iclass 27, count 2 2006.257.07:04:49.67#ibcon#about to read 4, iclass 27, count 2 2006.257.07:04:49.67#ibcon#read 4, iclass 27, count 2 2006.257.07:04:49.67#ibcon#about to read 5, iclass 27, count 2 2006.257.07:04:49.67#ibcon#read 5, iclass 27, count 2 2006.257.07:04:49.67#ibcon#about to read 6, iclass 27, count 2 2006.257.07:04:49.67#ibcon#read 6, iclass 27, count 2 2006.257.07:04:49.67#ibcon#end of sib2, iclass 27, count 2 2006.257.07:04:49.67#ibcon#*after write, iclass 27, count 2 2006.257.07:04:49.67#ibcon#*before return 0, iclass 27, count 2 2006.257.07:04:49.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:49.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:04:49.67#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.07:04:49.67#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:49.67#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:49.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:49.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:49.79#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:04:49.79#ibcon#first serial, iclass 27, count 0 2006.257.07:04:49.79#ibcon#enter sib2, iclass 27, count 0 2006.257.07:04:49.79#ibcon#flushed, iclass 27, count 0 2006.257.07:04:49.79#ibcon#about to write, iclass 27, count 0 2006.257.07:04:49.79#ibcon#wrote, iclass 27, count 0 2006.257.07:04:49.79#ibcon#about to read 3, iclass 27, count 0 2006.257.07:04:49.81#ibcon#read 3, iclass 27, count 0 2006.257.07:04:49.81#ibcon#about to read 4, iclass 27, count 0 2006.257.07:04:49.81#ibcon#read 4, iclass 27, count 0 2006.257.07:04:49.81#ibcon#about to read 5, iclass 27, count 0 2006.257.07:04:49.81#ibcon#read 5, iclass 27, count 0 2006.257.07:04:49.81#ibcon#about to read 6, iclass 27, count 0 2006.257.07:04:49.81#ibcon#read 6, iclass 27, count 0 2006.257.07:04:49.81#ibcon#end of sib2, iclass 27, count 0 2006.257.07:04:49.81#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:04:49.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:04:49.81#ibcon#[27=USB\r\n] 2006.257.07:04:49.81#ibcon#*before write, iclass 27, count 0 2006.257.07:04:49.81#ibcon#enter sib2, iclass 27, count 0 2006.257.07:04:49.81#ibcon#flushed, iclass 27, count 0 2006.257.07:04:49.81#ibcon#about to write, iclass 27, count 0 2006.257.07:04:49.81#ibcon#wrote, iclass 27, count 0 2006.257.07:04:49.81#ibcon#about to read 3, iclass 27, count 0 2006.257.07:04:49.84#ibcon#read 3, iclass 27, count 0 2006.257.07:04:49.84#ibcon#about to read 4, iclass 27, count 0 2006.257.07:04:49.84#ibcon#read 4, iclass 27, count 0 2006.257.07:04:49.84#ibcon#about to read 5, iclass 27, count 0 2006.257.07:04:49.84#ibcon#read 5, iclass 27, count 0 2006.257.07:04:49.84#ibcon#about to read 6, iclass 27, count 0 2006.257.07:04:49.84#ibcon#read 6, iclass 27, count 0 2006.257.07:04:49.84#ibcon#end of sib2, iclass 27, count 0 2006.257.07:04:49.84#ibcon#*after write, iclass 27, count 0 2006.257.07:04:49.84#ibcon#*before return 0, iclass 27, count 0 2006.257.07:04:49.84#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:49.84#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:04:49.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:04:49.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:04:49.84$vck44/vblo=6,719.99 2006.257.07:04:49.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.07:04:49.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.07:04:49.84#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:49.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:49.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:49.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:49.84#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:04:49.84#ibcon#first serial, iclass 29, count 0 2006.257.07:04:49.84#ibcon#enter sib2, iclass 29, count 0 2006.257.07:04:49.84#ibcon#flushed, iclass 29, count 0 2006.257.07:04:49.84#ibcon#about to write, iclass 29, count 0 2006.257.07:04:49.84#ibcon#wrote, iclass 29, count 0 2006.257.07:04:49.84#ibcon#about to read 3, iclass 29, count 0 2006.257.07:04:49.86#ibcon#read 3, iclass 29, count 0 2006.257.07:04:49.86#ibcon#about to read 4, iclass 29, count 0 2006.257.07:04:49.86#ibcon#read 4, iclass 29, count 0 2006.257.07:04:49.86#ibcon#about to read 5, iclass 29, count 0 2006.257.07:04:49.86#ibcon#read 5, iclass 29, count 0 2006.257.07:04:49.86#ibcon#about to read 6, iclass 29, count 0 2006.257.07:04:49.86#ibcon#read 6, iclass 29, count 0 2006.257.07:04:49.86#ibcon#end of sib2, iclass 29, count 0 2006.257.07:04:49.86#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:04:49.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:04:49.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.07:04:49.86#ibcon#*before write, iclass 29, count 0 2006.257.07:04:49.86#ibcon#enter sib2, iclass 29, count 0 2006.257.07:04:49.86#ibcon#flushed, iclass 29, count 0 2006.257.07:04:49.86#ibcon#about to write, iclass 29, count 0 2006.257.07:04:49.86#ibcon#wrote, iclass 29, count 0 2006.257.07:04:49.86#ibcon#about to read 3, iclass 29, count 0 2006.257.07:04:49.90#ibcon#read 3, iclass 29, count 0 2006.257.07:04:49.90#ibcon#about to read 4, iclass 29, count 0 2006.257.07:04:49.90#ibcon#read 4, iclass 29, count 0 2006.257.07:04:49.90#ibcon#about to read 5, iclass 29, count 0 2006.257.07:04:49.90#ibcon#read 5, iclass 29, count 0 2006.257.07:04:49.90#ibcon#about to read 6, iclass 29, count 0 2006.257.07:04:49.90#ibcon#read 6, iclass 29, count 0 2006.257.07:04:49.90#ibcon#end of sib2, iclass 29, count 0 2006.257.07:04:49.90#ibcon#*after write, iclass 29, count 0 2006.257.07:04:49.90#ibcon#*before return 0, iclass 29, count 0 2006.257.07:04:49.90#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:49.90#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:04:49.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:04:49.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:04:49.90$vck44/vb=6,4 2006.257.07:04:49.90#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.07:04:49.90#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.07:04:49.90#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:49.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:49.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:49.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:49.96#ibcon#enter wrdev, iclass 31, count 2 2006.257.07:04:49.96#ibcon#first serial, iclass 31, count 2 2006.257.07:04:49.96#ibcon#enter sib2, iclass 31, count 2 2006.257.07:04:49.96#ibcon#flushed, iclass 31, count 2 2006.257.07:04:49.96#ibcon#about to write, iclass 31, count 2 2006.257.07:04:49.96#ibcon#wrote, iclass 31, count 2 2006.257.07:04:49.96#ibcon#about to read 3, iclass 31, count 2 2006.257.07:04:49.98#ibcon#read 3, iclass 31, count 2 2006.257.07:04:49.98#ibcon#about to read 4, iclass 31, count 2 2006.257.07:04:49.98#ibcon#read 4, iclass 31, count 2 2006.257.07:04:49.98#ibcon#about to read 5, iclass 31, count 2 2006.257.07:04:49.98#ibcon#read 5, iclass 31, count 2 2006.257.07:04:49.98#ibcon#about to read 6, iclass 31, count 2 2006.257.07:04:49.98#ibcon#read 6, iclass 31, count 2 2006.257.07:04:49.98#ibcon#end of sib2, iclass 31, count 2 2006.257.07:04:49.98#ibcon#*mode == 0, iclass 31, count 2 2006.257.07:04:49.98#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.07:04:49.98#ibcon#[27=AT06-04\r\n] 2006.257.07:04:49.98#ibcon#*before write, iclass 31, count 2 2006.257.07:04:49.98#ibcon#enter sib2, iclass 31, count 2 2006.257.07:04:49.98#ibcon#flushed, iclass 31, count 2 2006.257.07:04:49.98#ibcon#about to write, iclass 31, count 2 2006.257.07:04:49.98#ibcon#wrote, iclass 31, count 2 2006.257.07:04:49.98#ibcon#about to read 3, iclass 31, count 2 2006.257.07:04:50.01#ibcon#read 3, iclass 31, count 2 2006.257.07:04:50.01#ibcon#about to read 4, iclass 31, count 2 2006.257.07:04:50.01#ibcon#read 4, iclass 31, count 2 2006.257.07:04:50.01#ibcon#about to read 5, iclass 31, count 2 2006.257.07:04:50.01#ibcon#read 5, iclass 31, count 2 2006.257.07:04:50.01#ibcon#about to read 6, iclass 31, count 2 2006.257.07:04:50.01#ibcon#read 6, iclass 31, count 2 2006.257.07:04:50.01#ibcon#end of sib2, iclass 31, count 2 2006.257.07:04:50.01#ibcon#*after write, iclass 31, count 2 2006.257.07:04:50.01#ibcon#*before return 0, iclass 31, count 2 2006.257.07:04:50.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:50.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:04:50.01#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.07:04:50.01#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:50.01#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:50.13#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:50.13#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:50.13#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:04:50.13#ibcon#first serial, iclass 31, count 0 2006.257.07:04:50.13#ibcon#enter sib2, iclass 31, count 0 2006.257.07:04:50.13#ibcon#flushed, iclass 31, count 0 2006.257.07:04:50.13#ibcon#about to write, iclass 31, count 0 2006.257.07:04:50.13#ibcon#wrote, iclass 31, count 0 2006.257.07:04:50.13#ibcon#about to read 3, iclass 31, count 0 2006.257.07:04:50.15#ibcon#read 3, iclass 31, count 0 2006.257.07:04:50.15#ibcon#about to read 4, iclass 31, count 0 2006.257.07:04:50.15#ibcon#read 4, iclass 31, count 0 2006.257.07:04:50.15#ibcon#about to read 5, iclass 31, count 0 2006.257.07:04:50.15#ibcon#read 5, iclass 31, count 0 2006.257.07:04:50.15#ibcon#about to read 6, iclass 31, count 0 2006.257.07:04:50.15#ibcon#read 6, iclass 31, count 0 2006.257.07:04:50.15#ibcon#end of sib2, iclass 31, count 0 2006.257.07:04:50.15#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:04:50.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:04:50.15#ibcon#[27=USB\r\n] 2006.257.07:04:50.15#ibcon#*before write, iclass 31, count 0 2006.257.07:04:50.15#ibcon#enter sib2, iclass 31, count 0 2006.257.07:04:50.15#ibcon#flushed, iclass 31, count 0 2006.257.07:04:50.15#ibcon#about to write, iclass 31, count 0 2006.257.07:04:50.15#ibcon#wrote, iclass 31, count 0 2006.257.07:04:50.15#ibcon#about to read 3, iclass 31, count 0 2006.257.07:04:50.18#ibcon#read 3, iclass 31, count 0 2006.257.07:04:50.18#ibcon#about to read 4, iclass 31, count 0 2006.257.07:04:50.18#ibcon#read 4, iclass 31, count 0 2006.257.07:04:50.18#ibcon#about to read 5, iclass 31, count 0 2006.257.07:04:50.18#ibcon#read 5, iclass 31, count 0 2006.257.07:04:50.18#ibcon#about to read 6, iclass 31, count 0 2006.257.07:04:50.18#ibcon#read 6, iclass 31, count 0 2006.257.07:04:50.18#ibcon#end of sib2, iclass 31, count 0 2006.257.07:04:50.18#ibcon#*after write, iclass 31, count 0 2006.257.07:04:50.18#ibcon#*before return 0, iclass 31, count 0 2006.257.07:04:50.18#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:50.18#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:04:50.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:04:50.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:04:50.18$vck44/vblo=7,734.99 2006.257.07:04:50.18#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.07:04:50.18#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.07:04:50.18#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:50.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:50.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:50.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:50.18#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:04:50.18#ibcon#first serial, iclass 33, count 0 2006.257.07:04:50.18#ibcon#enter sib2, iclass 33, count 0 2006.257.07:04:50.18#ibcon#flushed, iclass 33, count 0 2006.257.07:04:50.18#ibcon#about to write, iclass 33, count 0 2006.257.07:04:50.18#ibcon#wrote, iclass 33, count 0 2006.257.07:04:50.18#ibcon#about to read 3, iclass 33, count 0 2006.257.07:04:50.20#ibcon#read 3, iclass 33, count 0 2006.257.07:04:50.20#ibcon#about to read 4, iclass 33, count 0 2006.257.07:04:50.20#ibcon#read 4, iclass 33, count 0 2006.257.07:04:50.20#ibcon#about to read 5, iclass 33, count 0 2006.257.07:04:50.20#ibcon#read 5, iclass 33, count 0 2006.257.07:04:50.20#ibcon#about to read 6, iclass 33, count 0 2006.257.07:04:50.20#ibcon#read 6, iclass 33, count 0 2006.257.07:04:50.20#ibcon#end of sib2, iclass 33, count 0 2006.257.07:04:50.20#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:04:50.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:04:50.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.07:04:50.20#ibcon#*before write, iclass 33, count 0 2006.257.07:04:50.20#ibcon#enter sib2, iclass 33, count 0 2006.257.07:04:50.20#ibcon#flushed, iclass 33, count 0 2006.257.07:04:50.20#ibcon#about to write, iclass 33, count 0 2006.257.07:04:50.20#ibcon#wrote, iclass 33, count 0 2006.257.07:04:50.20#ibcon#about to read 3, iclass 33, count 0 2006.257.07:04:50.24#ibcon#read 3, iclass 33, count 0 2006.257.07:04:50.24#ibcon#about to read 4, iclass 33, count 0 2006.257.07:04:50.24#ibcon#read 4, iclass 33, count 0 2006.257.07:04:50.24#ibcon#about to read 5, iclass 33, count 0 2006.257.07:04:50.24#ibcon#read 5, iclass 33, count 0 2006.257.07:04:50.24#ibcon#about to read 6, iclass 33, count 0 2006.257.07:04:50.24#ibcon#read 6, iclass 33, count 0 2006.257.07:04:50.24#ibcon#end of sib2, iclass 33, count 0 2006.257.07:04:50.24#ibcon#*after write, iclass 33, count 0 2006.257.07:04:50.24#ibcon#*before return 0, iclass 33, count 0 2006.257.07:04:50.24#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:50.24#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:04:50.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:04:50.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:04:50.24$vck44/vb=7,4 2006.257.07:04:50.24#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.07:04:50.24#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.07:04:50.24#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:50.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:50.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:50.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:50.30#ibcon#enter wrdev, iclass 35, count 2 2006.257.07:04:50.30#ibcon#first serial, iclass 35, count 2 2006.257.07:04:50.30#ibcon#enter sib2, iclass 35, count 2 2006.257.07:04:50.30#ibcon#flushed, iclass 35, count 2 2006.257.07:04:50.30#ibcon#about to write, iclass 35, count 2 2006.257.07:04:50.30#ibcon#wrote, iclass 35, count 2 2006.257.07:04:50.30#ibcon#about to read 3, iclass 35, count 2 2006.257.07:04:50.32#ibcon#read 3, iclass 35, count 2 2006.257.07:04:50.32#ibcon#about to read 4, iclass 35, count 2 2006.257.07:04:50.32#ibcon#read 4, iclass 35, count 2 2006.257.07:04:50.32#ibcon#about to read 5, iclass 35, count 2 2006.257.07:04:50.32#ibcon#read 5, iclass 35, count 2 2006.257.07:04:50.32#ibcon#about to read 6, iclass 35, count 2 2006.257.07:04:50.32#ibcon#read 6, iclass 35, count 2 2006.257.07:04:50.32#ibcon#end of sib2, iclass 35, count 2 2006.257.07:04:50.32#ibcon#*mode == 0, iclass 35, count 2 2006.257.07:04:50.32#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.07:04:50.32#ibcon#[27=AT07-04\r\n] 2006.257.07:04:50.32#ibcon#*before write, iclass 35, count 2 2006.257.07:04:50.32#ibcon#enter sib2, iclass 35, count 2 2006.257.07:04:50.32#ibcon#flushed, iclass 35, count 2 2006.257.07:04:50.32#ibcon#about to write, iclass 35, count 2 2006.257.07:04:50.32#ibcon#wrote, iclass 35, count 2 2006.257.07:04:50.32#ibcon#about to read 3, iclass 35, count 2 2006.257.07:04:50.35#ibcon#read 3, iclass 35, count 2 2006.257.07:04:50.35#ibcon#about to read 4, iclass 35, count 2 2006.257.07:04:50.35#ibcon#read 4, iclass 35, count 2 2006.257.07:04:50.35#ibcon#about to read 5, iclass 35, count 2 2006.257.07:04:50.35#ibcon#read 5, iclass 35, count 2 2006.257.07:04:50.35#ibcon#about to read 6, iclass 35, count 2 2006.257.07:04:50.35#ibcon#read 6, iclass 35, count 2 2006.257.07:04:50.35#ibcon#end of sib2, iclass 35, count 2 2006.257.07:04:50.35#ibcon#*after write, iclass 35, count 2 2006.257.07:04:50.35#ibcon#*before return 0, iclass 35, count 2 2006.257.07:04:50.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:50.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:04:50.35#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.07:04:50.35#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:50.35#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:50.47#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:50.47#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:50.47#ibcon#enter wrdev, iclass 35, count 0 2006.257.07:04:50.47#ibcon#first serial, iclass 35, count 0 2006.257.07:04:50.47#ibcon#enter sib2, iclass 35, count 0 2006.257.07:04:50.47#ibcon#flushed, iclass 35, count 0 2006.257.07:04:50.47#ibcon#about to write, iclass 35, count 0 2006.257.07:04:50.47#ibcon#wrote, iclass 35, count 0 2006.257.07:04:50.47#ibcon#about to read 3, iclass 35, count 0 2006.257.07:04:50.49#ibcon#read 3, iclass 35, count 0 2006.257.07:04:50.49#ibcon#about to read 4, iclass 35, count 0 2006.257.07:04:50.49#ibcon#read 4, iclass 35, count 0 2006.257.07:04:50.49#ibcon#about to read 5, iclass 35, count 0 2006.257.07:04:50.49#ibcon#read 5, iclass 35, count 0 2006.257.07:04:50.49#ibcon#about to read 6, iclass 35, count 0 2006.257.07:04:50.49#ibcon#read 6, iclass 35, count 0 2006.257.07:04:50.49#ibcon#end of sib2, iclass 35, count 0 2006.257.07:04:50.49#ibcon#*mode == 0, iclass 35, count 0 2006.257.07:04:50.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.07:04:50.49#ibcon#[27=USB\r\n] 2006.257.07:04:50.49#ibcon#*before write, iclass 35, count 0 2006.257.07:04:50.49#ibcon#enter sib2, iclass 35, count 0 2006.257.07:04:50.49#ibcon#flushed, iclass 35, count 0 2006.257.07:04:50.49#ibcon#about to write, iclass 35, count 0 2006.257.07:04:50.49#ibcon#wrote, iclass 35, count 0 2006.257.07:04:50.49#ibcon#about to read 3, iclass 35, count 0 2006.257.07:04:50.52#ibcon#read 3, iclass 35, count 0 2006.257.07:04:50.52#ibcon#about to read 4, iclass 35, count 0 2006.257.07:04:50.52#ibcon#read 4, iclass 35, count 0 2006.257.07:04:50.52#ibcon#about to read 5, iclass 35, count 0 2006.257.07:04:50.52#ibcon#read 5, iclass 35, count 0 2006.257.07:04:50.52#ibcon#about to read 6, iclass 35, count 0 2006.257.07:04:50.52#ibcon#read 6, iclass 35, count 0 2006.257.07:04:50.52#ibcon#end of sib2, iclass 35, count 0 2006.257.07:04:50.52#ibcon#*after write, iclass 35, count 0 2006.257.07:04:50.52#ibcon#*before return 0, iclass 35, count 0 2006.257.07:04:50.52#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:50.52#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:04:50.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.07:04:50.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.07:04:50.52$vck44/vblo=8,744.99 2006.257.07:04:50.52#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.07:04:50.52#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.07:04:50.52#ibcon#ireg 17 cls_cnt 0 2006.257.07:04:50.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:04:50.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:04:50.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:04:50.52#ibcon#enter wrdev, iclass 37, count 0 2006.257.07:04:50.52#ibcon#first serial, iclass 37, count 0 2006.257.07:04:50.52#ibcon#enter sib2, iclass 37, count 0 2006.257.07:04:50.52#ibcon#flushed, iclass 37, count 0 2006.257.07:04:50.52#ibcon#about to write, iclass 37, count 0 2006.257.07:04:50.52#ibcon#wrote, iclass 37, count 0 2006.257.07:04:50.52#ibcon#about to read 3, iclass 37, count 0 2006.257.07:04:50.54#ibcon#read 3, iclass 37, count 0 2006.257.07:04:50.54#ibcon#about to read 4, iclass 37, count 0 2006.257.07:04:50.54#ibcon#read 4, iclass 37, count 0 2006.257.07:04:50.54#ibcon#about to read 5, iclass 37, count 0 2006.257.07:04:50.54#ibcon#read 5, iclass 37, count 0 2006.257.07:04:50.54#ibcon#about to read 6, iclass 37, count 0 2006.257.07:04:50.54#ibcon#read 6, iclass 37, count 0 2006.257.07:04:50.54#ibcon#end of sib2, iclass 37, count 0 2006.257.07:04:50.54#ibcon#*mode == 0, iclass 37, count 0 2006.257.07:04:50.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.07:04:50.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.07:04:50.54#ibcon#*before write, iclass 37, count 0 2006.257.07:04:50.54#ibcon#enter sib2, iclass 37, count 0 2006.257.07:04:50.54#ibcon#flushed, iclass 37, count 0 2006.257.07:04:50.54#ibcon#about to write, iclass 37, count 0 2006.257.07:04:50.54#ibcon#wrote, iclass 37, count 0 2006.257.07:04:50.54#ibcon#about to read 3, iclass 37, count 0 2006.257.07:04:50.58#ibcon#read 3, iclass 37, count 0 2006.257.07:04:50.58#ibcon#about to read 4, iclass 37, count 0 2006.257.07:04:50.58#ibcon#read 4, iclass 37, count 0 2006.257.07:04:50.58#ibcon#about to read 5, iclass 37, count 0 2006.257.07:04:50.58#ibcon#read 5, iclass 37, count 0 2006.257.07:04:50.58#ibcon#about to read 6, iclass 37, count 0 2006.257.07:04:50.58#ibcon#read 6, iclass 37, count 0 2006.257.07:04:50.58#ibcon#end of sib2, iclass 37, count 0 2006.257.07:04:50.58#ibcon#*after write, iclass 37, count 0 2006.257.07:04:50.58#ibcon#*before return 0, iclass 37, count 0 2006.257.07:04:50.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:04:50.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:04:50.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.07:04:50.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.07:04:50.58$vck44/vb=8,4 2006.257.07:04:50.58#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.07:04:50.58#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.07:04:50.58#ibcon#ireg 11 cls_cnt 2 2006.257.07:04:50.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:04:50.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:04:50.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:04:50.64#ibcon#enter wrdev, iclass 39, count 2 2006.257.07:04:50.64#ibcon#first serial, iclass 39, count 2 2006.257.07:04:50.64#ibcon#enter sib2, iclass 39, count 2 2006.257.07:04:50.64#ibcon#flushed, iclass 39, count 2 2006.257.07:04:50.64#ibcon#about to write, iclass 39, count 2 2006.257.07:04:50.64#ibcon#wrote, iclass 39, count 2 2006.257.07:04:50.64#ibcon#about to read 3, iclass 39, count 2 2006.257.07:04:50.66#ibcon#read 3, iclass 39, count 2 2006.257.07:04:50.66#ibcon#about to read 4, iclass 39, count 2 2006.257.07:04:50.66#ibcon#read 4, iclass 39, count 2 2006.257.07:04:50.66#ibcon#about to read 5, iclass 39, count 2 2006.257.07:04:50.66#ibcon#read 5, iclass 39, count 2 2006.257.07:04:50.66#ibcon#about to read 6, iclass 39, count 2 2006.257.07:04:50.66#ibcon#read 6, iclass 39, count 2 2006.257.07:04:50.66#ibcon#end of sib2, iclass 39, count 2 2006.257.07:04:50.66#ibcon#*mode == 0, iclass 39, count 2 2006.257.07:04:50.66#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.07:04:50.66#ibcon#[27=AT08-04\r\n] 2006.257.07:04:50.66#ibcon#*before write, iclass 39, count 2 2006.257.07:04:50.66#ibcon#enter sib2, iclass 39, count 2 2006.257.07:04:50.66#ibcon#flushed, iclass 39, count 2 2006.257.07:04:50.66#ibcon#about to write, iclass 39, count 2 2006.257.07:04:50.66#ibcon#wrote, iclass 39, count 2 2006.257.07:04:50.66#ibcon#about to read 3, iclass 39, count 2 2006.257.07:04:50.69#ibcon#read 3, iclass 39, count 2 2006.257.07:04:50.69#ibcon#about to read 4, iclass 39, count 2 2006.257.07:04:50.69#ibcon#read 4, iclass 39, count 2 2006.257.07:04:50.69#ibcon#about to read 5, iclass 39, count 2 2006.257.07:04:50.69#ibcon#read 5, iclass 39, count 2 2006.257.07:04:50.69#ibcon#about to read 6, iclass 39, count 2 2006.257.07:04:50.69#ibcon#read 6, iclass 39, count 2 2006.257.07:04:50.69#ibcon#end of sib2, iclass 39, count 2 2006.257.07:04:50.69#ibcon#*after write, iclass 39, count 2 2006.257.07:04:50.69#ibcon#*before return 0, iclass 39, count 2 2006.257.07:04:50.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:04:50.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:04:50.69#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.07:04:50.69#ibcon#ireg 7 cls_cnt 0 2006.257.07:04:50.69#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:04:50.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:04:50.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:04:50.81#ibcon#enter wrdev, iclass 39, count 0 2006.257.07:04:50.81#ibcon#first serial, iclass 39, count 0 2006.257.07:04:50.81#ibcon#enter sib2, iclass 39, count 0 2006.257.07:04:50.81#ibcon#flushed, iclass 39, count 0 2006.257.07:04:50.81#ibcon#about to write, iclass 39, count 0 2006.257.07:04:50.81#ibcon#wrote, iclass 39, count 0 2006.257.07:04:50.81#ibcon#about to read 3, iclass 39, count 0 2006.257.07:04:50.83#ibcon#read 3, iclass 39, count 0 2006.257.07:04:50.83#ibcon#about to read 4, iclass 39, count 0 2006.257.07:04:50.83#ibcon#read 4, iclass 39, count 0 2006.257.07:04:50.83#ibcon#about to read 5, iclass 39, count 0 2006.257.07:04:50.83#ibcon#read 5, iclass 39, count 0 2006.257.07:04:50.83#ibcon#about to read 6, iclass 39, count 0 2006.257.07:04:50.83#ibcon#read 6, iclass 39, count 0 2006.257.07:04:50.83#ibcon#end of sib2, iclass 39, count 0 2006.257.07:04:50.83#ibcon#*mode == 0, iclass 39, count 0 2006.257.07:04:50.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.07:04:50.83#ibcon#[27=USB\r\n] 2006.257.07:04:50.83#ibcon#*before write, iclass 39, count 0 2006.257.07:04:50.83#ibcon#enter sib2, iclass 39, count 0 2006.257.07:04:50.83#ibcon#flushed, iclass 39, count 0 2006.257.07:04:50.83#ibcon#about to write, iclass 39, count 0 2006.257.07:04:50.83#ibcon#wrote, iclass 39, count 0 2006.257.07:04:50.83#ibcon#about to read 3, iclass 39, count 0 2006.257.07:04:50.86#ibcon#read 3, iclass 39, count 0 2006.257.07:04:50.86#ibcon#about to read 4, iclass 39, count 0 2006.257.07:04:50.86#ibcon#read 4, iclass 39, count 0 2006.257.07:04:50.86#ibcon#about to read 5, iclass 39, count 0 2006.257.07:04:50.86#ibcon#read 5, iclass 39, count 0 2006.257.07:04:50.86#ibcon#about to read 6, iclass 39, count 0 2006.257.07:04:50.86#ibcon#read 6, iclass 39, count 0 2006.257.07:04:50.86#ibcon#end of sib2, iclass 39, count 0 2006.257.07:04:50.86#ibcon#*after write, iclass 39, count 0 2006.257.07:04:50.86#ibcon#*before return 0, iclass 39, count 0 2006.257.07:04:50.86#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:04:50.86#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:04:50.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.07:04:50.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.07:04:50.86$vck44/vabw=wide 2006.257.07:04:50.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.07:04:50.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.07:04:50.86#ibcon#ireg 8 cls_cnt 0 2006.257.07:04:50.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:50.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:50.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:50.86#ibcon#enter wrdev, iclass 3, count 0 2006.257.07:04:50.86#ibcon#first serial, iclass 3, count 0 2006.257.07:04:50.86#ibcon#enter sib2, iclass 3, count 0 2006.257.07:04:50.86#ibcon#flushed, iclass 3, count 0 2006.257.07:04:50.86#ibcon#about to write, iclass 3, count 0 2006.257.07:04:50.86#ibcon#wrote, iclass 3, count 0 2006.257.07:04:50.86#ibcon#about to read 3, iclass 3, count 0 2006.257.07:04:50.88#ibcon#read 3, iclass 3, count 0 2006.257.07:04:50.88#ibcon#about to read 4, iclass 3, count 0 2006.257.07:04:50.88#ibcon#read 4, iclass 3, count 0 2006.257.07:04:50.88#ibcon#about to read 5, iclass 3, count 0 2006.257.07:04:50.88#ibcon#read 5, iclass 3, count 0 2006.257.07:04:50.88#ibcon#about to read 6, iclass 3, count 0 2006.257.07:04:50.88#ibcon#read 6, iclass 3, count 0 2006.257.07:04:50.88#ibcon#end of sib2, iclass 3, count 0 2006.257.07:04:50.88#ibcon#*mode == 0, iclass 3, count 0 2006.257.07:04:50.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.07:04:50.88#ibcon#[25=BW32\r\n] 2006.257.07:04:50.88#ibcon#*before write, iclass 3, count 0 2006.257.07:04:50.88#ibcon#enter sib2, iclass 3, count 0 2006.257.07:04:50.88#ibcon#flushed, iclass 3, count 0 2006.257.07:04:50.88#ibcon#about to write, iclass 3, count 0 2006.257.07:04:50.88#ibcon#wrote, iclass 3, count 0 2006.257.07:04:50.88#ibcon#about to read 3, iclass 3, count 0 2006.257.07:04:50.91#ibcon#read 3, iclass 3, count 0 2006.257.07:04:50.91#ibcon#about to read 4, iclass 3, count 0 2006.257.07:04:50.91#ibcon#read 4, iclass 3, count 0 2006.257.07:04:50.91#ibcon#about to read 5, iclass 3, count 0 2006.257.07:04:50.91#ibcon#read 5, iclass 3, count 0 2006.257.07:04:50.91#ibcon#about to read 6, iclass 3, count 0 2006.257.07:04:50.91#ibcon#read 6, iclass 3, count 0 2006.257.07:04:50.91#ibcon#end of sib2, iclass 3, count 0 2006.257.07:04:50.91#ibcon#*after write, iclass 3, count 0 2006.257.07:04:50.91#ibcon#*before return 0, iclass 3, count 0 2006.257.07:04:50.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:50.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:04:50.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.07:04:50.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.07:04:50.91$vck44/vbbw=wide 2006.257.07:04:50.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.07:04:50.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.07:04:50.91#ibcon#ireg 8 cls_cnt 0 2006.257.07:04:50.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:04:50.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:04:50.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:04:50.98#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:04:50.98#ibcon#first serial, iclass 5, count 0 2006.257.07:04:50.98#ibcon#enter sib2, iclass 5, count 0 2006.257.07:04:50.98#ibcon#flushed, iclass 5, count 0 2006.257.07:04:50.98#ibcon#about to write, iclass 5, count 0 2006.257.07:04:50.98#ibcon#wrote, iclass 5, count 0 2006.257.07:04:50.98#ibcon#about to read 3, iclass 5, count 0 2006.257.07:04:51.00#ibcon#read 3, iclass 5, count 0 2006.257.07:04:51.00#ibcon#about to read 4, iclass 5, count 0 2006.257.07:04:51.00#ibcon#read 4, iclass 5, count 0 2006.257.07:04:51.00#ibcon#about to read 5, iclass 5, count 0 2006.257.07:04:51.00#ibcon#read 5, iclass 5, count 0 2006.257.07:04:51.00#ibcon#about to read 6, iclass 5, count 0 2006.257.07:04:51.00#ibcon#read 6, iclass 5, count 0 2006.257.07:04:51.00#ibcon#end of sib2, iclass 5, count 0 2006.257.07:04:51.00#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:04:51.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:04:51.00#ibcon#[27=BW32\r\n] 2006.257.07:04:51.00#ibcon#*before write, iclass 5, count 0 2006.257.07:04:51.00#ibcon#enter sib2, iclass 5, count 0 2006.257.07:04:51.00#ibcon#flushed, iclass 5, count 0 2006.257.07:04:51.00#ibcon#about to write, iclass 5, count 0 2006.257.07:04:51.00#ibcon#wrote, iclass 5, count 0 2006.257.07:04:51.00#ibcon#about to read 3, iclass 5, count 0 2006.257.07:04:51.03#ibcon#read 3, iclass 5, count 0 2006.257.07:04:51.03#ibcon#about to read 4, iclass 5, count 0 2006.257.07:04:51.03#ibcon#read 4, iclass 5, count 0 2006.257.07:04:51.03#ibcon#about to read 5, iclass 5, count 0 2006.257.07:04:51.03#ibcon#read 5, iclass 5, count 0 2006.257.07:04:51.03#ibcon#about to read 6, iclass 5, count 0 2006.257.07:04:51.03#ibcon#read 6, iclass 5, count 0 2006.257.07:04:51.03#ibcon#end of sib2, iclass 5, count 0 2006.257.07:04:51.03#ibcon#*after write, iclass 5, count 0 2006.257.07:04:51.03#ibcon#*before return 0, iclass 5, count 0 2006.257.07:04:51.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:04:51.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:04:51.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:04:51.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:04:51.03$setupk4/ifdk4 2006.257.07:04:51.03$ifdk4/lo= 2006.257.07:04:51.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.07:04:51.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.07:04:51.03$ifdk4/patch= 2006.257.07:04:51.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.07:04:51.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.07:04:51.03$setupk4/!*+20s 2006.257.07:04:57.92#abcon#<5=/16 1.5 3.9 20.93 881012.2\r\n> 2006.257.07:04:57.94#abcon#{5=INTERFACE CLEAR} 2006.257.07:04:58.00#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:05:05.53$setupk4/"tpicd 2006.257.07:05:05.53$setupk4/echo=off 2006.257.07:05:05.53$setupk4/xlog=off 2006.257.07:05:05.53:!2006.257.07:08:18 2006.257.07:05:13.14#trakl#Source acquired 2006.257.07:05:13.14#flagr#flagr/antenna,acquired 2006.257.07:08:18.00:preob 2006.257.07:08:18.13/onsource/TRACKING 2006.257.07:08:18.13:!2006.257.07:08:28 2006.257.07:08:28.00:"tape 2006.257.07:08:28.00:"st=record 2006.257.07:08:28.00:data_valid=on 2006.257.07:08:28.00:midob 2006.257.07:08:28.13/onsource/TRACKING 2006.257.07:08:28.13/wx/21.04,1012.2,87 2006.257.07:08:28.19/cable/+6.4789E-03 2006.257.07:08:29.28/va/01,08,usb,yes,31,33 2006.257.07:08:29.28/va/02,07,usb,yes,34,34 2006.257.07:08:29.28/va/03,08,usb,yes,30,32 2006.257.07:08:29.28/va/04,07,usb,yes,35,36 2006.257.07:08:29.28/va/05,04,usb,yes,31,31 2006.257.07:08:29.28/va/06,04,usb,yes,35,34 2006.257.07:08:29.28/va/07,04,usb,yes,36,36 2006.257.07:08:29.28/va/08,04,usb,yes,29,36 2006.257.07:08:29.51/valo/01,524.99,yes,locked 2006.257.07:08:29.51/valo/02,534.99,yes,locked 2006.257.07:08:29.51/valo/03,564.99,yes,locked 2006.257.07:08:29.51/valo/04,624.99,yes,locked 2006.257.07:08:29.51/valo/05,734.99,yes,locked 2006.257.07:08:29.51/valo/06,814.99,yes,locked 2006.257.07:08:29.51/valo/07,864.99,yes,locked 2006.257.07:08:29.51/valo/08,884.99,yes,locked 2006.257.07:08:30.60/vb/01,04,usb,yes,31,28 2006.257.07:08:30.60/vb/02,05,usb,yes,29,29 2006.257.07:08:30.60/vb/03,04,usb,yes,30,33 2006.257.07:08:30.60/vb/04,05,usb,yes,30,29 2006.257.07:08:30.60/vb/05,04,usb,yes,27,29 2006.257.07:08:30.60/vb/06,04,usb,yes,31,27 2006.257.07:08:30.60/vb/07,04,usb,yes,31,31 2006.257.07:08:30.60/vb/08,04,usb,yes,28,32 2006.257.07:08:30.84/vblo/01,629.99,yes,locked 2006.257.07:08:30.84/vblo/02,634.99,yes,locked 2006.257.07:08:30.84/vblo/03,649.99,yes,locked 2006.257.07:08:30.84/vblo/04,679.99,yes,locked 2006.257.07:08:30.84/vblo/05,709.99,yes,locked 2006.257.07:08:30.84/vblo/06,719.99,yes,locked 2006.257.07:08:30.84/vblo/07,734.99,yes,locked 2006.257.07:08:30.84/vblo/08,744.99,yes,locked 2006.257.07:08:30.99/vabw/8 2006.257.07:08:31.14/vbbw/8 2006.257.07:08:31.28/xfe/off,on,16.7 2006.257.07:08:31.65/ifatt/23,28,28,28 2006.257.07:08:32.07/fmout-gps/S +4.53E-07 2006.257.07:08:32.11:!2006.257.07:11:58 2006.257.07:11:58.00:data_valid=off 2006.257.07:11:58.00:"et 2006.257.07:11:58.00:!+3s 2006.257.07:12:01.01:"tape 2006.257.07:12:01.01:postob 2006.257.07:12:01.07/cable/+6.4761E-03 2006.257.07:12:01.07/wx/21.20,1012.2,87 2006.257.07:12:02.08/fmout-gps/S +4.54E-07 2006.257.07:12:02.08:scan_name=257-0715,jd0609,230 2006.257.07:12:02.08:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.257.07:12:02.14#flagr#flagr/antenna,new-source 2006.257.07:12:03.14:checkk5 2006.257.07:12:03.53/chk_autoobs//k5ts1/ autoobs is running! 2006.257.07:12:03.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.07:12:04.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.07:12:04.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.07:12:05.14/chk_obsdata//k5ts1/T2570708??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.07:12:05.54/chk_obsdata//k5ts2/T2570708??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.07:12:05.97/chk_obsdata//k5ts3/T2570708??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.07:12:06.36/chk_obsdata//k5ts4/T2570708??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.07:12:07.09/k5log//k5ts1_log_newline 2006.257.07:12:07.81/k5log//k5ts2_log_newline 2006.257.07:12:08.54/k5log//k5ts3_log_newline 2006.257.07:12:09.24/k5log//k5ts4_log_newline 2006.257.07:12:09.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.07:12:09.26:setupk4=1 2006.257.07:12:09.27$setupk4/echo=on 2006.257.07:12:09.27$setupk4/pcalon 2006.257.07:12:09.27$pcalon/"no phase cal control is implemented here 2006.257.07:12:09.27$setupk4/"tpicd=stop 2006.257.07:12:09.27$setupk4/"rec=synch_on 2006.257.07:12:09.27$setupk4/"rec_mode=128 2006.257.07:12:09.27$setupk4/!* 2006.257.07:12:09.27$setupk4/recpk4 2006.257.07:12:09.27$recpk4/recpatch= 2006.257.07:12:09.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.07:12:09.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.07:12:09.27$setupk4/vck44 2006.257.07:12:09.27$vck44/valo=1,524.99 2006.257.07:12:09.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.07:12:09.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.07:12:09.27#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:09.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:09.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:09.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:09.27#ibcon#enter wrdev, iclass 40, count 0 2006.257.07:12:09.27#ibcon#first serial, iclass 40, count 0 2006.257.07:12:09.27#ibcon#enter sib2, iclass 40, count 0 2006.257.07:12:09.27#ibcon#flushed, iclass 40, count 0 2006.257.07:12:09.27#ibcon#about to write, iclass 40, count 0 2006.257.07:12:09.27#ibcon#wrote, iclass 40, count 0 2006.257.07:12:09.27#ibcon#about to read 3, iclass 40, count 0 2006.257.07:12:09.29#ibcon#read 3, iclass 40, count 0 2006.257.07:12:09.29#ibcon#about to read 4, iclass 40, count 0 2006.257.07:12:09.29#ibcon#read 4, iclass 40, count 0 2006.257.07:12:09.29#ibcon#about to read 5, iclass 40, count 0 2006.257.07:12:09.29#ibcon#read 5, iclass 40, count 0 2006.257.07:12:09.29#ibcon#about to read 6, iclass 40, count 0 2006.257.07:12:09.29#ibcon#read 6, iclass 40, count 0 2006.257.07:12:09.29#ibcon#end of sib2, iclass 40, count 0 2006.257.07:12:09.29#ibcon#*mode == 0, iclass 40, count 0 2006.257.07:12:09.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.07:12:09.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.07:12:09.29#ibcon#*before write, iclass 40, count 0 2006.257.07:12:09.29#ibcon#enter sib2, iclass 40, count 0 2006.257.07:12:09.29#ibcon#flushed, iclass 40, count 0 2006.257.07:12:09.29#ibcon#about to write, iclass 40, count 0 2006.257.07:12:09.29#ibcon#wrote, iclass 40, count 0 2006.257.07:12:09.29#ibcon#about to read 3, iclass 40, count 0 2006.257.07:12:09.34#ibcon#read 3, iclass 40, count 0 2006.257.07:12:09.34#ibcon#about to read 4, iclass 40, count 0 2006.257.07:12:09.34#ibcon#read 4, iclass 40, count 0 2006.257.07:12:09.34#ibcon#about to read 5, iclass 40, count 0 2006.257.07:12:09.34#ibcon#read 5, iclass 40, count 0 2006.257.07:12:09.34#ibcon#about to read 6, iclass 40, count 0 2006.257.07:12:09.34#ibcon#read 6, iclass 40, count 0 2006.257.07:12:09.34#ibcon#end of sib2, iclass 40, count 0 2006.257.07:12:09.34#ibcon#*after write, iclass 40, count 0 2006.257.07:12:09.34#ibcon#*before return 0, iclass 40, count 0 2006.257.07:12:09.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:09.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:09.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.07:12:09.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.07:12:09.34$vck44/va=1,8 2006.257.07:12:09.34#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.07:12:09.34#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.07:12:09.34#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:09.34#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:09.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:09.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:09.34#ibcon#enter wrdev, iclass 4, count 2 2006.257.07:12:09.34#ibcon#first serial, iclass 4, count 2 2006.257.07:12:09.34#ibcon#enter sib2, iclass 4, count 2 2006.257.07:12:09.34#ibcon#flushed, iclass 4, count 2 2006.257.07:12:09.34#ibcon#about to write, iclass 4, count 2 2006.257.07:12:09.34#ibcon#wrote, iclass 4, count 2 2006.257.07:12:09.34#ibcon#about to read 3, iclass 4, count 2 2006.257.07:12:09.36#ibcon#read 3, iclass 4, count 2 2006.257.07:12:09.36#ibcon#about to read 4, iclass 4, count 2 2006.257.07:12:09.36#ibcon#read 4, iclass 4, count 2 2006.257.07:12:09.36#ibcon#about to read 5, iclass 4, count 2 2006.257.07:12:09.36#ibcon#read 5, iclass 4, count 2 2006.257.07:12:09.36#ibcon#about to read 6, iclass 4, count 2 2006.257.07:12:09.36#ibcon#read 6, iclass 4, count 2 2006.257.07:12:09.36#ibcon#end of sib2, iclass 4, count 2 2006.257.07:12:09.36#ibcon#*mode == 0, iclass 4, count 2 2006.257.07:12:09.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.07:12:09.36#ibcon#[25=AT01-08\r\n] 2006.257.07:12:09.36#ibcon#*before write, iclass 4, count 2 2006.257.07:12:09.36#ibcon#enter sib2, iclass 4, count 2 2006.257.07:12:09.36#ibcon#flushed, iclass 4, count 2 2006.257.07:12:09.36#ibcon#about to write, iclass 4, count 2 2006.257.07:12:09.36#ibcon#wrote, iclass 4, count 2 2006.257.07:12:09.36#ibcon#about to read 3, iclass 4, count 2 2006.257.07:12:09.39#ibcon#read 3, iclass 4, count 2 2006.257.07:12:09.39#ibcon#about to read 4, iclass 4, count 2 2006.257.07:12:09.39#ibcon#read 4, iclass 4, count 2 2006.257.07:12:09.39#ibcon#about to read 5, iclass 4, count 2 2006.257.07:12:09.39#ibcon#read 5, iclass 4, count 2 2006.257.07:12:09.39#ibcon#about to read 6, iclass 4, count 2 2006.257.07:12:09.39#ibcon#read 6, iclass 4, count 2 2006.257.07:12:09.39#ibcon#end of sib2, iclass 4, count 2 2006.257.07:12:09.39#ibcon#*after write, iclass 4, count 2 2006.257.07:12:09.39#ibcon#*before return 0, iclass 4, count 2 2006.257.07:12:09.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:09.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:09.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.07:12:09.39#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:09.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:09.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:09.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:09.51#ibcon#enter wrdev, iclass 4, count 0 2006.257.07:12:09.51#ibcon#first serial, iclass 4, count 0 2006.257.07:12:09.51#ibcon#enter sib2, iclass 4, count 0 2006.257.07:12:09.51#ibcon#flushed, iclass 4, count 0 2006.257.07:12:09.51#ibcon#about to write, iclass 4, count 0 2006.257.07:12:09.51#ibcon#wrote, iclass 4, count 0 2006.257.07:12:09.51#ibcon#about to read 3, iclass 4, count 0 2006.257.07:12:09.53#ibcon#read 3, iclass 4, count 0 2006.257.07:12:09.53#ibcon#about to read 4, iclass 4, count 0 2006.257.07:12:09.53#ibcon#read 4, iclass 4, count 0 2006.257.07:12:09.53#ibcon#about to read 5, iclass 4, count 0 2006.257.07:12:09.53#ibcon#read 5, iclass 4, count 0 2006.257.07:12:09.53#ibcon#about to read 6, iclass 4, count 0 2006.257.07:12:09.53#ibcon#read 6, iclass 4, count 0 2006.257.07:12:09.53#ibcon#end of sib2, iclass 4, count 0 2006.257.07:12:09.53#ibcon#*mode == 0, iclass 4, count 0 2006.257.07:12:09.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.07:12:09.53#ibcon#[25=USB\r\n] 2006.257.07:12:09.53#ibcon#*before write, iclass 4, count 0 2006.257.07:12:09.53#ibcon#enter sib2, iclass 4, count 0 2006.257.07:12:09.53#ibcon#flushed, iclass 4, count 0 2006.257.07:12:09.53#ibcon#about to write, iclass 4, count 0 2006.257.07:12:09.53#ibcon#wrote, iclass 4, count 0 2006.257.07:12:09.53#ibcon#about to read 3, iclass 4, count 0 2006.257.07:12:09.56#ibcon#read 3, iclass 4, count 0 2006.257.07:12:09.56#ibcon#about to read 4, iclass 4, count 0 2006.257.07:12:09.56#ibcon#read 4, iclass 4, count 0 2006.257.07:12:09.56#ibcon#about to read 5, iclass 4, count 0 2006.257.07:12:09.56#ibcon#read 5, iclass 4, count 0 2006.257.07:12:09.56#ibcon#about to read 6, iclass 4, count 0 2006.257.07:12:09.56#ibcon#read 6, iclass 4, count 0 2006.257.07:12:09.56#ibcon#end of sib2, iclass 4, count 0 2006.257.07:12:09.56#ibcon#*after write, iclass 4, count 0 2006.257.07:12:09.56#ibcon#*before return 0, iclass 4, count 0 2006.257.07:12:09.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:09.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:09.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.07:12:09.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.07:12:09.56$vck44/valo=2,534.99 2006.257.07:12:09.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.07:12:09.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.07:12:09.56#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:09.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:09.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:09.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:09.56#ibcon#enter wrdev, iclass 6, count 0 2006.257.07:12:09.56#ibcon#first serial, iclass 6, count 0 2006.257.07:12:09.56#ibcon#enter sib2, iclass 6, count 0 2006.257.07:12:09.56#ibcon#flushed, iclass 6, count 0 2006.257.07:12:09.56#ibcon#about to write, iclass 6, count 0 2006.257.07:12:09.56#ibcon#wrote, iclass 6, count 0 2006.257.07:12:09.56#ibcon#about to read 3, iclass 6, count 0 2006.257.07:12:09.58#ibcon#read 3, iclass 6, count 0 2006.257.07:12:09.58#ibcon#about to read 4, iclass 6, count 0 2006.257.07:12:09.58#ibcon#read 4, iclass 6, count 0 2006.257.07:12:09.58#ibcon#about to read 5, iclass 6, count 0 2006.257.07:12:09.58#ibcon#read 5, iclass 6, count 0 2006.257.07:12:09.58#ibcon#about to read 6, iclass 6, count 0 2006.257.07:12:09.58#ibcon#read 6, iclass 6, count 0 2006.257.07:12:09.58#ibcon#end of sib2, iclass 6, count 0 2006.257.07:12:09.58#ibcon#*mode == 0, iclass 6, count 0 2006.257.07:12:09.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.07:12:09.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.07:12:09.58#ibcon#*before write, iclass 6, count 0 2006.257.07:12:09.58#ibcon#enter sib2, iclass 6, count 0 2006.257.07:12:09.58#ibcon#flushed, iclass 6, count 0 2006.257.07:12:09.58#ibcon#about to write, iclass 6, count 0 2006.257.07:12:09.58#ibcon#wrote, iclass 6, count 0 2006.257.07:12:09.58#ibcon#about to read 3, iclass 6, count 0 2006.257.07:12:09.62#ibcon#read 3, iclass 6, count 0 2006.257.07:12:09.62#ibcon#about to read 4, iclass 6, count 0 2006.257.07:12:09.62#ibcon#read 4, iclass 6, count 0 2006.257.07:12:09.62#ibcon#about to read 5, iclass 6, count 0 2006.257.07:12:09.62#ibcon#read 5, iclass 6, count 0 2006.257.07:12:09.62#ibcon#about to read 6, iclass 6, count 0 2006.257.07:12:09.62#ibcon#read 6, iclass 6, count 0 2006.257.07:12:09.62#ibcon#end of sib2, iclass 6, count 0 2006.257.07:12:09.62#ibcon#*after write, iclass 6, count 0 2006.257.07:12:09.62#ibcon#*before return 0, iclass 6, count 0 2006.257.07:12:09.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:09.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:09.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.07:12:09.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.07:12:09.62$vck44/va=2,7 2006.257.07:12:09.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.07:12:09.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.07:12:09.62#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:09.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:09.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:09.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:09.68#ibcon#enter wrdev, iclass 10, count 2 2006.257.07:12:09.68#ibcon#first serial, iclass 10, count 2 2006.257.07:12:09.68#ibcon#enter sib2, iclass 10, count 2 2006.257.07:12:09.68#ibcon#flushed, iclass 10, count 2 2006.257.07:12:09.68#ibcon#about to write, iclass 10, count 2 2006.257.07:12:09.68#ibcon#wrote, iclass 10, count 2 2006.257.07:12:09.68#ibcon#about to read 3, iclass 10, count 2 2006.257.07:12:09.70#ibcon#read 3, iclass 10, count 2 2006.257.07:12:09.70#ibcon#about to read 4, iclass 10, count 2 2006.257.07:12:09.70#ibcon#read 4, iclass 10, count 2 2006.257.07:12:09.70#ibcon#about to read 5, iclass 10, count 2 2006.257.07:12:09.70#ibcon#read 5, iclass 10, count 2 2006.257.07:12:09.70#ibcon#about to read 6, iclass 10, count 2 2006.257.07:12:09.70#ibcon#read 6, iclass 10, count 2 2006.257.07:12:09.70#ibcon#end of sib2, iclass 10, count 2 2006.257.07:12:09.70#ibcon#*mode == 0, iclass 10, count 2 2006.257.07:12:09.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.07:12:09.70#ibcon#[25=AT02-07\r\n] 2006.257.07:12:09.70#ibcon#*before write, iclass 10, count 2 2006.257.07:12:09.70#ibcon#enter sib2, iclass 10, count 2 2006.257.07:12:09.70#ibcon#flushed, iclass 10, count 2 2006.257.07:12:09.70#ibcon#about to write, iclass 10, count 2 2006.257.07:12:09.70#ibcon#wrote, iclass 10, count 2 2006.257.07:12:09.70#ibcon#about to read 3, iclass 10, count 2 2006.257.07:12:09.73#ibcon#read 3, iclass 10, count 2 2006.257.07:12:09.73#ibcon#about to read 4, iclass 10, count 2 2006.257.07:12:09.73#ibcon#read 4, iclass 10, count 2 2006.257.07:12:09.73#ibcon#about to read 5, iclass 10, count 2 2006.257.07:12:09.73#ibcon#read 5, iclass 10, count 2 2006.257.07:12:09.73#ibcon#about to read 6, iclass 10, count 2 2006.257.07:12:09.73#ibcon#read 6, iclass 10, count 2 2006.257.07:12:09.73#ibcon#end of sib2, iclass 10, count 2 2006.257.07:12:09.73#ibcon#*after write, iclass 10, count 2 2006.257.07:12:09.73#ibcon#*before return 0, iclass 10, count 2 2006.257.07:12:09.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:09.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:09.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.07:12:09.73#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:09.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:09.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:09.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:09.85#ibcon#enter wrdev, iclass 10, count 0 2006.257.07:12:09.85#ibcon#first serial, iclass 10, count 0 2006.257.07:12:09.85#ibcon#enter sib2, iclass 10, count 0 2006.257.07:12:09.85#ibcon#flushed, iclass 10, count 0 2006.257.07:12:09.85#ibcon#about to write, iclass 10, count 0 2006.257.07:12:09.85#ibcon#wrote, iclass 10, count 0 2006.257.07:12:09.85#ibcon#about to read 3, iclass 10, count 0 2006.257.07:12:09.87#ibcon#read 3, iclass 10, count 0 2006.257.07:12:09.87#ibcon#about to read 4, iclass 10, count 0 2006.257.07:12:09.87#ibcon#read 4, iclass 10, count 0 2006.257.07:12:09.87#ibcon#about to read 5, iclass 10, count 0 2006.257.07:12:09.87#ibcon#read 5, iclass 10, count 0 2006.257.07:12:09.87#ibcon#about to read 6, iclass 10, count 0 2006.257.07:12:09.87#ibcon#read 6, iclass 10, count 0 2006.257.07:12:09.87#ibcon#end of sib2, iclass 10, count 0 2006.257.07:12:09.87#ibcon#*mode == 0, iclass 10, count 0 2006.257.07:12:09.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.07:12:09.87#ibcon#[25=USB\r\n] 2006.257.07:12:09.87#ibcon#*before write, iclass 10, count 0 2006.257.07:12:09.87#ibcon#enter sib2, iclass 10, count 0 2006.257.07:12:09.87#ibcon#flushed, iclass 10, count 0 2006.257.07:12:09.87#ibcon#about to write, iclass 10, count 0 2006.257.07:12:09.87#ibcon#wrote, iclass 10, count 0 2006.257.07:12:09.87#ibcon#about to read 3, iclass 10, count 0 2006.257.07:12:09.90#ibcon#read 3, iclass 10, count 0 2006.257.07:12:09.90#ibcon#about to read 4, iclass 10, count 0 2006.257.07:12:09.90#ibcon#read 4, iclass 10, count 0 2006.257.07:12:09.90#ibcon#about to read 5, iclass 10, count 0 2006.257.07:12:09.90#ibcon#read 5, iclass 10, count 0 2006.257.07:12:09.90#ibcon#about to read 6, iclass 10, count 0 2006.257.07:12:09.90#ibcon#read 6, iclass 10, count 0 2006.257.07:12:09.90#ibcon#end of sib2, iclass 10, count 0 2006.257.07:12:09.90#ibcon#*after write, iclass 10, count 0 2006.257.07:12:09.90#ibcon#*before return 0, iclass 10, count 0 2006.257.07:12:09.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:09.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:09.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.07:12:09.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.07:12:09.90$vck44/valo=3,564.99 2006.257.07:12:09.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.07:12:09.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.07:12:09.90#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:09.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:09.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:09.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:09.90#ibcon#enter wrdev, iclass 12, count 0 2006.257.07:12:09.90#ibcon#first serial, iclass 12, count 0 2006.257.07:12:09.90#ibcon#enter sib2, iclass 12, count 0 2006.257.07:12:09.90#ibcon#flushed, iclass 12, count 0 2006.257.07:12:09.90#ibcon#about to write, iclass 12, count 0 2006.257.07:12:09.90#ibcon#wrote, iclass 12, count 0 2006.257.07:12:09.90#ibcon#about to read 3, iclass 12, count 0 2006.257.07:12:09.92#ibcon#read 3, iclass 12, count 0 2006.257.07:12:09.92#ibcon#about to read 4, iclass 12, count 0 2006.257.07:12:09.92#ibcon#read 4, iclass 12, count 0 2006.257.07:12:09.92#ibcon#about to read 5, iclass 12, count 0 2006.257.07:12:09.92#ibcon#read 5, iclass 12, count 0 2006.257.07:12:09.92#ibcon#about to read 6, iclass 12, count 0 2006.257.07:12:09.92#ibcon#read 6, iclass 12, count 0 2006.257.07:12:09.92#ibcon#end of sib2, iclass 12, count 0 2006.257.07:12:09.92#ibcon#*mode == 0, iclass 12, count 0 2006.257.07:12:09.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.07:12:09.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.07:12:09.92#ibcon#*before write, iclass 12, count 0 2006.257.07:12:09.92#ibcon#enter sib2, iclass 12, count 0 2006.257.07:12:09.92#ibcon#flushed, iclass 12, count 0 2006.257.07:12:09.92#ibcon#about to write, iclass 12, count 0 2006.257.07:12:09.92#ibcon#wrote, iclass 12, count 0 2006.257.07:12:09.92#ibcon#about to read 3, iclass 12, count 0 2006.257.07:12:09.96#ibcon#read 3, iclass 12, count 0 2006.257.07:12:09.96#ibcon#about to read 4, iclass 12, count 0 2006.257.07:12:09.96#ibcon#read 4, iclass 12, count 0 2006.257.07:12:09.96#ibcon#about to read 5, iclass 12, count 0 2006.257.07:12:09.96#ibcon#read 5, iclass 12, count 0 2006.257.07:12:09.96#ibcon#about to read 6, iclass 12, count 0 2006.257.07:12:09.96#ibcon#read 6, iclass 12, count 0 2006.257.07:12:09.96#ibcon#end of sib2, iclass 12, count 0 2006.257.07:12:09.96#ibcon#*after write, iclass 12, count 0 2006.257.07:12:09.96#ibcon#*before return 0, iclass 12, count 0 2006.257.07:12:09.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:09.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:09.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.07:12:09.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.07:12:09.96$vck44/va=3,8 2006.257.07:12:09.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.07:12:09.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.07:12:09.96#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:09.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:10.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:10.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:10.02#ibcon#enter wrdev, iclass 14, count 2 2006.257.07:12:10.02#ibcon#first serial, iclass 14, count 2 2006.257.07:12:10.02#ibcon#enter sib2, iclass 14, count 2 2006.257.07:12:10.02#ibcon#flushed, iclass 14, count 2 2006.257.07:12:10.02#ibcon#about to write, iclass 14, count 2 2006.257.07:12:10.02#ibcon#wrote, iclass 14, count 2 2006.257.07:12:10.02#ibcon#about to read 3, iclass 14, count 2 2006.257.07:12:10.04#ibcon#read 3, iclass 14, count 2 2006.257.07:12:10.04#ibcon#about to read 4, iclass 14, count 2 2006.257.07:12:10.04#ibcon#read 4, iclass 14, count 2 2006.257.07:12:10.04#ibcon#about to read 5, iclass 14, count 2 2006.257.07:12:10.04#ibcon#read 5, iclass 14, count 2 2006.257.07:12:10.04#ibcon#about to read 6, iclass 14, count 2 2006.257.07:12:10.04#ibcon#read 6, iclass 14, count 2 2006.257.07:12:10.04#ibcon#end of sib2, iclass 14, count 2 2006.257.07:12:10.04#ibcon#*mode == 0, iclass 14, count 2 2006.257.07:12:10.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.07:12:10.04#ibcon#[25=AT03-08\r\n] 2006.257.07:12:10.04#ibcon#*before write, iclass 14, count 2 2006.257.07:12:10.04#ibcon#enter sib2, iclass 14, count 2 2006.257.07:12:10.04#ibcon#flushed, iclass 14, count 2 2006.257.07:12:10.04#ibcon#about to write, iclass 14, count 2 2006.257.07:12:10.04#ibcon#wrote, iclass 14, count 2 2006.257.07:12:10.04#ibcon#about to read 3, iclass 14, count 2 2006.257.07:12:10.07#ibcon#read 3, iclass 14, count 2 2006.257.07:12:10.07#ibcon#about to read 4, iclass 14, count 2 2006.257.07:12:10.07#ibcon#read 4, iclass 14, count 2 2006.257.07:12:10.07#ibcon#about to read 5, iclass 14, count 2 2006.257.07:12:10.07#ibcon#read 5, iclass 14, count 2 2006.257.07:12:10.07#ibcon#about to read 6, iclass 14, count 2 2006.257.07:12:10.07#ibcon#read 6, iclass 14, count 2 2006.257.07:12:10.07#ibcon#end of sib2, iclass 14, count 2 2006.257.07:12:10.07#ibcon#*after write, iclass 14, count 2 2006.257.07:12:10.07#ibcon#*before return 0, iclass 14, count 2 2006.257.07:12:10.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:10.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:10.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.07:12:10.07#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:10.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:10.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:10.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:10.19#ibcon#enter wrdev, iclass 14, count 0 2006.257.07:12:10.19#ibcon#first serial, iclass 14, count 0 2006.257.07:12:10.19#ibcon#enter sib2, iclass 14, count 0 2006.257.07:12:10.19#ibcon#flushed, iclass 14, count 0 2006.257.07:12:10.19#ibcon#about to write, iclass 14, count 0 2006.257.07:12:10.19#ibcon#wrote, iclass 14, count 0 2006.257.07:12:10.19#ibcon#about to read 3, iclass 14, count 0 2006.257.07:12:10.21#ibcon#read 3, iclass 14, count 0 2006.257.07:12:10.21#ibcon#about to read 4, iclass 14, count 0 2006.257.07:12:10.21#ibcon#read 4, iclass 14, count 0 2006.257.07:12:10.21#ibcon#about to read 5, iclass 14, count 0 2006.257.07:12:10.21#ibcon#read 5, iclass 14, count 0 2006.257.07:12:10.21#ibcon#about to read 6, iclass 14, count 0 2006.257.07:12:10.21#ibcon#read 6, iclass 14, count 0 2006.257.07:12:10.21#ibcon#end of sib2, iclass 14, count 0 2006.257.07:12:10.21#ibcon#*mode == 0, iclass 14, count 0 2006.257.07:12:10.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.07:12:10.21#ibcon#[25=USB\r\n] 2006.257.07:12:10.21#ibcon#*before write, iclass 14, count 0 2006.257.07:12:10.21#ibcon#enter sib2, iclass 14, count 0 2006.257.07:12:10.21#ibcon#flushed, iclass 14, count 0 2006.257.07:12:10.21#ibcon#about to write, iclass 14, count 0 2006.257.07:12:10.21#ibcon#wrote, iclass 14, count 0 2006.257.07:12:10.21#ibcon#about to read 3, iclass 14, count 0 2006.257.07:12:10.24#ibcon#read 3, iclass 14, count 0 2006.257.07:12:10.24#ibcon#about to read 4, iclass 14, count 0 2006.257.07:12:10.24#ibcon#read 4, iclass 14, count 0 2006.257.07:12:10.24#ibcon#about to read 5, iclass 14, count 0 2006.257.07:12:10.24#ibcon#read 5, iclass 14, count 0 2006.257.07:12:10.24#ibcon#about to read 6, iclass 14, count 0 2006.257.07:12:10.24#ibcon#read 6, iclass 14, count 0 2006.257.07:12:10.24#ibcon#end of sib2, iclass 14, count 0 2006.257.07:12:10.24#ibcon#*after write, iclass 14, count 0 2006.257.07:12:10.24#ibcon#*before return 0, iclass 14, count 0 2006.257.07:12:10.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:10.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:10.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.07:12:10.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.07:12:10.24$vck44/valo=4,624.99 2006.257.07:12:10.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.07:12:10.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.07:12:10.24#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:10.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:10.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:10.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:10.24#ibcon#enter wrdev, iclass 16, count 0 2006.257.07:12:10.24#ibcon#first serial, iclass 16, count 0 2006.257.07:12:10.24#ibcon#enter sib2, iclass 16, count 0 2006.257.07:12:10.24#ibcon#flushed, iclass 16, count 0 2006.257.07:12:10.24#ibcon#about to write, iclass 16, count 0 2006.257.07:12:10.24#ibcon#wrote, iclass 16, count 0 2006.257.07:12:10.24#ibcon#about to read 3, iclass 16, count 0 2006.257.07:12:10.26#ibcon#read 3, iclass 16, count 0 2006.257.07:12:10.26#ibcon#about to read 4, iclass 16, count 0 2006.257.07:12:10.26#ibcon#read 4, iclass 16, count 0 2006.257.07:12:10.26#ibcon#about to read 5, iclass 16, count 0 2006.257.07:12:10.26#ibcon#read 5, iclass 16, count 0 2006.257.07:12:10.26#ibcon#about to read 6, iclass 16, count 0 2006.257.07:12:10.26#ibcon#read 6, iclass 16, count 0 2006.257.07:12:10.26#ibcon#end of sib2, iclass 16, count 0 2006.257.07:12:10.26#ibcon#*mode == 0, iclass 16, count 0 2006.257.07:12:10.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.07:12:10.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.07:12:10.26#ibcon#*before write, iclass 16, count 0 2006.257.07:12:10.26#ibcon#enter sib2, iclass 16, count 0 2006.257.07:12:10.26#ibcon#flushed, iclass 16, count 0 2006.257.07:12:10.26#ibcon#about to write, iclass 16, count 0 2006.257.07:12:10.26#ibcon#wrote, iclass 16, count 0 2006.257.07:12:10.26#ibcon#about to read 3, iclass 16, count 0 2006.257.07:12:10.30#ibcon#read 3, iclass 16, count 0 2006.257.07:12:10.30#ibcon#about to read 4, iclass 16, count 0 2006.257.07:12:10.30#ibcon#read 4, iclass 16, count 0 2006.257.07:12:10.30#ibcon#about to read 5, iclass 16, count 0 2006.257.07:12:10.30#ibcon#read 5, iclass 16, count 0 2006.257.07:12:10.30#ibcon#about to read 6, iclass 16, count 0 2006.257.07:12:10.30#ibcon#read 6, iclass 16, count 0 2006.257.07:12:10.30#ibcon#end of sib2, iclass 16, count 0 2006.257.07:12:10.30#ibcon#*after write, iclass 16, count 0 2006.257.07:12:10.30#ibcon#*before return 0, iclass 16, count 0 2006.257.07:12:10.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:10.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:10.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.07:12:10.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.07:12:10.30$vck44/va=4,7 2006.257.07:12:10.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.07:12:10.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.07:12:10.30#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:10.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:10.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:10.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:10.36#ibcon#enter wrdev, iclass 18, count 2 2006.257.07:12:10.36#ibcon#first serial, iclass 18, count 2 2006.257.07:12:10.36#ibcon#enter sib2, iclass 18, count 2 2006.257.07:12:10.36#ibcon#flushed, iclass 18, count 2 2006.257.07:12:10.36#ibcon#about to write, iclass 18, count 2 2006.257.07:12:10.36#ibcon#wrote, iclass 18, count 2 2006.257.07:12:10.36#ibcon#about to read 3, iclass 18, count 2 2006.257.07:12:10.38#ibcon#read 3, iclass 18, count 2 2006.257.07:12:10.38#ibcon#about to read 4, iclass 18, count 2 2006.257.07:12:10.38#ibcon#read 4, iclass 18, count 2 2006.257.07:12:10.38#ibcon#about to read 5, iclass 18, count 2 2006.257.07:12:10.38#ibcon#read 5, iclass 18, count 2 2006.257.07:12:10.38#ibcon#about to read 6, iclass 18, count 2 2006.257.07:12:10.38#ibcon#read 6, iclass 18, count 2 2006.257.07:12:10.38#ibcon#end of sib2, iclass 18, count 2 2006.257.07:12:10.38#ibcon#*mode == 0, iclass 18, count 2 2006.257.07:12:10.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.07:12:10.38#ibcon#[25=AT04-07\r\n] 2006.257.07:12:10.38#ibcon#*before write, iclass 18, count 2 2006.257.07:12:10.38#ibcon#enter sib2, iclass 18, count 2 2006.257.07:12:10.38#ibcon#flushed, iclass 18, count 2 2006.257.07:12:10.38#ibcon#about to write, iclass 18, count 2 2006.257.07:12:10.38#ibcon#wrote, iclass 18, count 2 2006.257.07:12:10.38#ibcon#about to read 3, iclass 18, count 2 2006.257.07:12:10.41#ibcon#read 3, iclass 18, count 2 2006.257.07:12:10.41#ibcon#about to read 4, iclass 18, count 2 2006.257.07:12:10.41#ibcon#read 4, iclass 18, count 2 2006.257.07:12:10.41#ibcon#about to read 5, iclass 18, count 2 2006.257.07:12:10.41#ibcon#read 5, iclass 18, count 2 2006.257.07:12:10.41#ibcon#about to read 6, iclass 18, count 2 2006.257.07:12:10.41#ibcon#read 6, iclass 18, count 2 2006.257.07:12:10.41#ibcon#end of sib2, iclass 18, count 2 2006.257.07:12:10.41#ibcon#*after write, iclass 18, count 2 2006.257.07:12:10.41#ibcon#*before return 0, iclass 18, count 2 2006.257.07:12:10.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:10.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:10.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.07:12:10.41#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:10.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:10.53#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:10.53#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:10.53#ibcon#enter wrdev, iclass 18, count 0 2006.257.07:12:10.53#ibcon#first serial, iclass 18, count 0 2006.257.07:12:10.53#ibcon#enter sib2, iclass 18, count 0 2006.257.07:12:10.53#ibcon#flushed, iclass 18, count 0 2006.257.07:12:10.53#ibcon#about to write, iclass 18, count 0 2006.257.07:12:10.53#ibcon#wrote, iclass 18, count 0 2006.257.07:12:10.53#ibcon#about to read 3, iclass 18, count 0 2006.257.07:12:10.55#ibcon#read 3, iclass 18, count 0 2006.257.07:12:10.55#ibcon#about to read 4, iclass 18, count 0 2006.257.07:12:10.55#ibcon#read 4, iclass 18, count 0 2006.257.07:12:10.55#ibcon#about to read 5, iclass 18, count 0 2006.257.07:12:10.55#ibcon#read 5, iclass 18, count 0 2006.257.07:12:10.55#ibcon#about to read 6, iclass 18, count 0 2006.257.07:12:10.55#ibcon#read 6, iclass 18, count 0 2006.257.07:12:10.55#ibcon#end of sib2, iclass 18, count 0 2006.257.07:12:10.55#ibcon#*mode == 0, iclass 18, count 0 2006.257.07:12:10.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.07:12:10.55#ibcon#[25=USB\r\n] 2006.257.07:12:10.55#ibcon#*before write, iclass 18, count 0 2006.257.07:12:10.55#ibcon#enter sib2, iclass 18, count 0 2006.257.07:12:10.55#ibcon#flushed, iclass 18, count 0 2006.257.07:12:10.55#ibcon#about to write, iclass 18, count 0 2006.257.07:12:10.55#ibcon#wrote, iclass 18, count 0 2006.257.07:12:10.55#ibcon#about to read 3, iclass 18, count 0 2006.257.07:12:10.58#ibcon#read 3, iclass 18, count 0 2006.257.07:12:10.58#ibcon#about to read 4, iclass 18, count 0 2006.257.07:12:10.58#ibcon#read 4, iclass 18, count 0 2006.257.07:12:10.58#ibcon#about to read 5, iclass 18, count 0 2006.257.07:12:10.58#ibcon#read 5, iclass 18, count 0 2006.257.07:12:10.58#ibcon#about to read 6, iclass 18, count 0 2006.257.07:12:10.58#ibcon#read 6, iclass 18, count 0 2006.257.07:12:10.58#ibcon#end of sib2, iclass 18, count 0 2006.257.07:12:10.58#ibcon#*after write, iclass 18, count 0 2006.257.07:12:10.58#ibcon#*before return 0, iclass 18, count 0 2006.257.07:12:10.58#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:10.58#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:10.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.07:12:10.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.07:12:10.58$vck44/valo=5,734.99 2006.257.07:12:10.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.07:12:10.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.07:12:10.58#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:10.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:10.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:10.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:10.58#ibcon#enter wrdev, iclass 20, count 0 2006.257.07:12:10.58#ibcon#first serial, iclass 20, count 0 2006.257.07:12:10.58#ibcon#enter sib2, iclass 20, count 0 2006.257.07:12:10.58#ibcon#flushed, iclass 20, count 0 2006.257.07:12:10.58#ibcon#about to write, iclass 20, count 0 2006.257.07:12:10.58#ibcon#wrote, iclass 20, count 0 2006.257.07:12:10.58#ibcon#about to read 3, iclass 20, count 0 2006.257.07:12:10.60#ibcon#read 3, iclass 20, count 0 2006.257.07:12:10.60#ibcon#about to read 4, iclass 20, count 0 2006.257.07:12:10.60#ibcon#read 4, iclass 20, count 0 2006.257.07:12:10.60#ibcon#about to read 5, iclass 20, count 0 2006.257.07:12:10.60#ibcon#read 5, iclass 20, count 0 2006.257.07:12:10.60#ibcon#about to read 6, iclass 20, count 0 2006.257.07:12:10.60#ibcon#read 6, iclass 20, count 0 2006.257.07:12:10.60#ibcon#end of sib2, iclass 20, count 0 2006.257.07:12:10.60#ibcon#*mode == 0, iclass 20, count 0 2006.257.07:12:10.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.07:12:10.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.07:12:10.60#ibcon#*before write, iclass 20, count 0 2006.257.07:12:10.60#ibcon#enter sib2, iclass 20, count 0 2006.257.07:12:10.60#ibcon#flushed, iclass 20, count 0 2006.257.07:12:10.60#ibcon#about to write, iclass 20, count 0 2006.257.07:12:10.60#ibcon#wrote, iclass 20, count 0 2006.257.07:12:10.60#ibcon#about to read 3, iclass 20, count 0 2006.257.07:12:10.64#ibcon#read 3, iclass 20, count 0 2006.257.07:12:10.64#ibcon#about to read 4, iclass 20, count 0 2006.257.07:12:10.64#ibcon#read 4, iclass 20, count 0 2006.257.07:12:10.64#ibcon#about to read 5, iclass 20, count 0 2006.257.07:12:10.64#ibcon#read 5, iclass 20, count 0 2006.257.07:12:10.64#ibcon#about to read 6, iclass 20, count 0 2006.257.07:12:10.64#ibcon#read 6, iclass 20, count 0 2006.257.07:12:10.64#ibcon#end of sib2, iclass 20, count 0 2006.257.07:12:10.64#ibcon#*after write, iclass 20, count 0 2006.257.07:12:10.64#ibcon#*before return 0, iclass 20, count 0 2006.257.07:12:10.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:10.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:10.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.07:12:10.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.07:12:10.64$vck44/va=5,4 2006.257.07:12:10.64#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.07:12:10.64#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.07:12:10.64#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:10.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:10.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:10.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:10.70#ibcon#enter wrdev, iclass 22, count 2 2006.257.07:12:10.70#ibcon#first serial, iclass 22, count 2 2006.257.07:12:10.70#ibcon#enter sib2, iclass 22, count 2 2006.257.07:12:10.70#ibcon#flushed, iclass 22, count 2 2006.257.07:12:10.70#ibcon#about to write, iclass 22, count 2 2006.257.07:12:10.70#ibcon#wrote, iclass 22, count 2 2006.257.07:12:10.70#ibcon#about to read 3, iclass 22, count 2 2006.257.07:12:10.72#ibcon#read 3, iclass 22, count 2 2006.257.07:12:10.72#ibcon#about to read 4, iclass 22, count 2 2006.257.07:12:10.72#ibcon#read 4, iclass 22, count 2 2006.257.07:12:10.72#ibcon#about to read 5, iclass 22, count 2 2006.257.07:12:10.72#ibcon#read 5, iclass 22, count 2 2006.257.07:12:10.72#ibcon#about to read 6, iclass 22, count 2 2006.257.07:12:10.72#ibcon#read 6, iclass 22, count 2 2006.257.07:12:10.72#ibcon#end of sib2, iclass 22, count 2 2006.257.07:12:10.72#ibcon#*mode == 0, iclass 22, count 2 2006.257.07:12:10.72#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.07:12:10.72#ibcon#[25=AT05-04\r\n] 2006.257.07:12:10.72#ibcon#*before write, iclass 22, count 2 2006.257.07:12:10.72#ibcon#enter sib2, iclass 22, count 2 2006.257.07:12:10.72#ibcon#flushed, iclass 22, count 2 2006.257.07:12:10.72#ibcon#about to write, iclass 22, count 2 2006.257.07:12:10.72#ibcon#wrote, iclass 22, count 2 2006.257.07:12:10.72#ibcon#about to read 3, iclass 22, count 2 2006.257.07:12:10.75#ibcon#read 3, iclass 22, count 2 2006.257.07:12:10.75#ibcon#about to read 4, iclass 22, count 2 2006.257.07:12:10.75#ibcon#read 4, iclass 22, count 2 2006.257.07:12:10.75#ibcon#about to read 5, iclass 22, count 2 2006.257.07:12:10.75#ibcon#read 5, iclass 22, count 2 2006.257.07:12:10.75#ibcon#about to read 6, iclass 22, count 2 2006.257.07:12:10.75#ibcon#read 6, iclass 22, count 2 2006.257.07:12:10.75#ibcon#end of sib2, iclass 22, count 2 2006.257.07:12:10.75#ibcon#*after write, iclass 22, count 2 2006.257.07:12:10.75#ibcon#*before return 0, iclass 22, count 2 2006.257.07:12:10.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:10.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:10.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.07:12:10.75#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:10.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:10.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:10.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:10.87#ibcon#enter wrdev, iclass 22, count 0 2006.257.07:12:10.87#ibcon#first serial, iclass 22, count 0 2006.257.07:12:10.87#ibcon#enter sib2, iclass 22, count 0 2006.257.07:12:10.87#ibcon#flushed, iclass 22, count 0 2006.257.07:12:10.87#ibcon#about to write, iclass 22, count 0 2006.257.07:12:10.87#ibcon#wrote, iclass 22, count 0 2006.257.07:12:10.87#ibcon#about to read 3, iclass 22, count 0 2006.257.07:12:10.89#ibcon#read 3, iclass 22, count 0 2006.257.07:12:10.89#ibcon#about to read 4, iclass 22, count 0 2006.257.07:12:10.89#ibcon#read 4, iclass 22, count 0 2006.257.07:12:10.89#ibcon#about to read 5, iclass 22, count 0 2006.257.07:12:10.89#ibcon#read 5, iclass 22, count 0 2006.257.07:12:10.89#ibcon#about to read 6, iclass 22, count 0 2006.257.07:12:10.89#ibcon#read 6, iclass 22, count 0 2006.257.07:12:10.89#ibcon#end of sib2, iclass 22, count 0 2006.257.07:12:10.89#ibcon#*mode == 0, iclass 22, count 0 2006.257.07:12:10.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.07:12:10.89#ibcon#[25=USB\r\n] 2006.257.07:12:10.89#ibcon#*before write, iclass 22, count 0 2006.257.07:12:10.89#ibcon#enter sib2, iclass 22, count 0 2006.257.07:12:10.89#ibcon#flushed, iclass 22, count 0 2006.257.07:12:10.89#ibcon#about to write, iclass 22, count 0 2006.257.07:12:10.89#ibcon#wrote, iclass 22, count 0 2006.257.07:12:10.89#ibcon#about to read 3, iclass 22, count 0 2006.257.07:12:10.92#ibcon#read 3, iclass 22, count 0 2006.257.07:12:10.92#ibcon#about to read 4, iclass 22, count 0 2006.257.07:12:10.92#ibcon#read 4, iclass 22, count 0 2006.257.07:12:10.92#ibcon#about to read 5, iclass 22, count 0 2006.257.07:12:10.92#ibcon#read 5, iclass 22, count 0 2006.257.07:12:10.92#ibcon#about to read 6, iclass 22, count 0 2006.257.07:12:10.92#ibcon#read 6, iclass 22, count 0 2006.257.07:12:10.92#ibcon#end of sib2, iclass 22, count 0 2006.257.07:12:10.92#ibcon#*after write, iclass 22, count 0 2006.257.07:12:10.92#ibcon#*before return 0, iclass 22, count 0 2006.257.07:12:10.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:10.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:10.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.07:12:10.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.07:12:10.92$vck44/valo=6,814.99 2006.257.07:12:10.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.07:12:10.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.07:12:10.92#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:10.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:10.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:10.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:10.92#ibcon#enter wrdev, iclass 24, count 0 2006.257.07:12:10.92#ibcon#first serial, iclass 24, count 0 2006.257.07:12:10.92#ibcon#enter sib2, iclass 24, count 0 2006.257.07:12:10.92#ibcon#flushed, iclass 24, count 0 2006.257.07:12:10.92#ibcon#about to write, iclass 24, count 0 2006.257.07:12:10.92#ibcon#wrote, iclass 24, count 0 2006.257.07:12:10.92#ibcon#about to read 3, iclass 24, count 0 2006.257.07:12:10.94#ibcon#read 3, iclass 24, count 0 2006.257.07:12:10.94#ibcon#about to read 4, iclass 24, count 0 2006.257.07:12:10.94#ibcon#read 4, iclass 24, count 0 2006.257.07:12:10.94#ibcon#about to read 5, iclass 24, count 0 2006.257.07:12:10.94#ibcon#read 5, iclass 24, count 0 2006.257.07:12:10.94#ibcon#about to read 6, iclass 24, count 0 2006.257.07:12:10.94#ibcon#read 6, iclass 24, count 0 2006.257.07:12:10.94#ibcon#end of sib2, iclass 24, count 0 2006.257.07:12:10.94#ibcon#*mode == 0, iclass 24, count 0 2006.257.07:12:10.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.07:12:10.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.07:12:10.94#ibcon#*before write, iclass 24, count 0 2006.257.07:12:10.94#ibcon#enter sib2, iclass 24, count 0 2006.257.07:12:10.94#ibcon#flushed, iclass 24, count 0 2006.257.07:12:10.94#ibcon#about to write, iclass 24, count 0 2006.257.07:12:10.94#ibcon#wrote, iclass 24, count 0 2006.257.07:12:10.94#ibcon#about to read 3, iclass 24, count 0 2006.257.07:12:10.98#ibcon#read 3, iclass 24, count 0 2006.257.07:12:10.98#ibcon#about to read 4, iclass 24, count 0 2006.257.07:12:10.98#ibcon#read 4, iclass 24, count 0 2006.257.07:12:10.98#ibcon#about to read 5, iclass 24, count 0 2006.257.07:12:10.98#ibcon#read 5, iclass 24, count 0 2006.257.07:12:10.98#ibcon#about to read 6, iclass 24, count 0 2006.257.07:12:10.98#ibcon#read 6, iclass 24, count 0 2006.257.07:12:10.98#ibcon#end of sib2, iclass 24, count 0 2006.257.07:12:10.98#ibcon#*after write, iclass 24, count 0 2006.257.07:12:10.98#ibcon#*before return 0, iclass 24, count 0 2006.257.07:12:10.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:10.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:10.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.07:12:10.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.07:12:10.98$vck44/va=6,4 2006.257.07:12:10.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.07:12:10.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.07:12:10.98#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:10.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:11.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:11.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:11.04#ibcon#enter wrdev, iclass 26, count 2 2006.257.07:12:11.04#ibcon#first serial, iclass 26, count 2 2006.257.07:12:11.04#ibcon#enter sib2, iclass 26, count 2 2006.257.07:12:11.04#ibcon#flushed, iclass 26, count 2 2006.257.07:12:11.04#ibcon#about to write, iclass 26, count 2 2006.257.07:12:11.04#ibcon#wrote, iclass 26, count 2 2006.257.07:12:11.04#ibcon#about to read 3, iclass 26, count 2 2006.257.07:12:11.06#ibcon#read 3, iclass 26, count 2 2006.257.07:12:11.06#ibcon#about to read 4, iclass 26, count 2 2006.257.07:12:11.06#ibcon#read 4, iclass 26, count 2 2006.257.07:12:11.06#ibcon#about to read 5, iclass 26, count 2 2006.257.07:12:11.06#ibcon#read 5, iclass 26, count 2 2006.257.07:12:11.06#ibcon#about to read 6, iclass 26, count 2 2006.257.07:12:11.06#ibcon#read 6, iclass 26, count 2 2006.257.07:12:11.06#ibcon#end of sib2, iclass 26, count 2 2006.257.07:12:11.06#ibcon#*mode == 0, iclass 26, count 2 2006.257.07:12:11.06#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.07:12:11.06#ibcon#[25=AT06-04\r\n] 2006.257.07:12:11.06#ibcon#*before write, iclass 26, count 2 2006.257.07:12:11.06#ibcon#enter sib2, iclass 26, count 2 2006.257.07:12:11.06#ibcon#flushed, iclass 26, count 2 2006.257.07:12:11.06#ibcon#about to write, iclass 26, count 2 2006.257.07:12:11.06#ibcon#wrote, iclass 26, count 2 2006.257.07:12:11.06#ibcon#about to read 3, iclass 26, count 2 2006.257.07:12:11.09#ibcon#read 3, iclass 26, count 2 2006.257.07:12:11.09#ibcon#about to read 4, iclass 26, count 2 2006.257.07:12:11.09#ibcon#read 4, iclass 26, count 2 2006.257.07:12:11.09#ibcon#about to read 5, iclass 26, count 2 2006.257.07:12:11.09#ibcon#read 5, iclass 26, count 2 2006.257.07:12:11.09#ibcon#about to read 6, iclass 26, count 2 2006.257.07:12:11.09#ibcon#read 6, iclass 26, count 2 2006.257.07:12:11.09#ibcon#end of sib2, iclass 26, count 2 2006.257.07:12:11.09#ibcon#*after write, iclass 26, count 2 2006.257.07:12:11.09#ibcon#*before return 0, iclass 26, count 2 2006.257.07:12:11.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:11.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:11.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.07:12:11.09#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:11.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:11.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:11.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:11.21#ibcon#enter wrdev, iclass 26, count 0 2006.257.07:12:11.21#ibcon#first serial, iclass 26, count 0 2006.257.07:12:11.21#ibcon#enter sib2, iclass 26, count 0 2006.257.07:12:11.21#ibcon#flushed, iclass 26, count 0 2006.257.07:12:11.21#ibcon#about to write, iclass 26, count 0 2006.257.07:12:11.21#ibcon#wrote, iclass 26, count 0 2006.257.07:12:11.21#ibcon#about to read 3, iclass 26, count 0 2006.257.07:12:11.23#ibcon#read 3, iclass 26, count 0 2006.257.07:12:11.23#ibcon#about to read 4, iclass 26, count 0 2006.257.07:12:11.23#ibcon#read 4, iclass 26, count 0 2006.257.07:12:11.23#ibcon#about to read 5, iclass 26, count 0 2006.257.07:12:11.23#ibcon#read 5, iclass 26, count 0 2006.257.07:12:11.23#ibcon#about to read 6, iclass 26, count 0 2006.257.07:12:11.23#ibcon#read 6, iclass 26, count 0 2006.257.07:12:11.23#ibcon#end of sib2, iclass 26, count 0 2006.257.07:12:11.23#ibcon#*mode == 0, iclass 26, count 0 2006.257.07:12:11.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.07:12:11.23#ibcon#[25=USB\r\n] 2006.257.07:12:11.23#ibcon#*before write, iclass 26, count 0 2006.257.07:12:11.23#ibcon#enter sib2, iclass 26, count 0 2006.257.07:12:11.23#ibcon#flushed, iclass 26, count 0 2006.257.07:12:11.23#ibcon#about to write, iclass 26, count 0 2006.257.07:12:11.23#ibcon#wrote, iclass 26, count 0 2006.257.07:12:11.23#ibcon#about to read 3, iclass 26, count 0 2006.257.07:12:11.26#ibcon#read 3, iclass 26, count 0 2006.257.07:12:11.26#ibcon#about to read 4, iclass 26, count 0 2006.257.07:12:11.26#ibcon#read 4, iclass 26, count 0 2006.257.07:12:11.26#ibcon#about to read 5, iclass 26, count 0 2006.257.07:12:11.26#ibcon#read 5, iclass 26, count 0 2006.257.07:12:11.26#ibcon#about to read 6, iclass 26, count 0 2006.257.07:12:11.26#ibcon#read 6, iclass 26, count 0 2006.257.07:12:11.26#ibcon#end of sib2, iclass 26, count 0 2006.257.07:12:11.26#ibcon#*after write, iclass 26, count 0 2006.257.07:12:11.26#ibcon#*before return 0, iclass 26, count 0 2006.257.07:12:11.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:11.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:11.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.07:12:11.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.07:12:11.26$vck44/valo=7,864.99 2006.257.07:12:11.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.07:12:11.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.07:12:11.26#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:11.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:11.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:11.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:11.26#ibcon#enter wrdev, iclass 28, count 0 2006.257.07:12:11.26#ibcon#first serial, iclass 28, count 0 2006.257.07:12:11.26#ibcon#enter sib2, iclass 28, count 0 2006.257.07:12:11.26#ibcon#flushed, iclass 28, count 0 2006.257.07:12:11.26#ibcon#about to write, iclass 28, count 0 2006.257.07:12:11.26#ibcon#wrote, iclass 28, count 0 2006.257.07:12:11.26#ibcon#about to read 3, iclass 28, count 0 2006.257.07:12:11.28#ibcon#read 3, iclass 28, count 0 2006.257.07:12:11.28#ibcon#about to read 4, iclass 28, count 0 2006.257.07:12:11.28#ibcon#read 4, iclass 28, count 0 2006.257.07:12:11.28#ibcon#about to read 5, iclass 28, count 0 2006.257.07:12:11.28#ibcon#read 5, iclass 28, count 0 2006.257.07:12:11.28#ibcon#about to read 6, iclass 28, count 0 2006.257.07:12:11.28#ibcon#read 6, iclass 28, count 0 2006.257.07:12:11.28#ibcon#end of sib2, iclass 28, count 0 2006.257.07:12:11.28#ibcon#*mode == 0, iclass 28, count 0 2006.257.07:12:11.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.07:12:11.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.07:12:11.28#ibcon#*before write, iclass 28, count 0 2006.257.07:12:11.28#ibcon#enter sib2, iclass 28, count 0 2006.257.07:12:11.28#ibcon#flushed, iclass 28, count 0 2006.257.07:12:11.28#ibcon#about to write, iclass 28, count 0 2006.257.07:12:11.28#ibcon#wrote, iclass 28, count 0 2006.257.07:12:11.28#ibcon#about to read 3, iclass 28, count 0 2006.257.07:12:11.32#ibcon#read 3, iclass 28, count 0 2006.257.07:12:11.32#ibcon#about to read 4, iclass 28, count 0 2006.257.07:12:11.32#ibcon#read 4, iclass 28, count 0 2006.257.07:12:11.32#ibcon#about to read 5, iclass 28, count 0 2006.257.07:12:11.32#ibcon#read 5, iclass 28, count 0 2006.257.07:12:11.32#ibcon#about to read 6, iclass 28, count 0 2006.257.07:12:11.32#ibcon#read 6, iclass 28, count 0 2006.257.07:12:11.32#ibcon#end of sib2, iclass 28, count 0 2006.257.07:12:11.32#ibcon#*after write, iclass 28, count 0 2006.257.07:12:11.32#ibcon#*before return 0, iclass 28, count 0 2006.257.07:12:11.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:11.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:11.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.07:12:11.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.07:12:11.32$vck44/va=7,4 2006.257.07:12:11.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.07:12:11.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.07:12:11.32#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:11.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:11.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:11.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:11.38#ibcon#enter wrdev, iclass 30, count 2 2006.257.07:12:11.38#ibcon#first serial, iclass 30, count 2 2006.257.07:12:11.38#ibcon#enter sib2, iclass 30, count 2 2006.257.07:12:11.38#ibcon#flushed, iclass 30, count 2 2006.257.07:12:11.38#ibcon#about to write, iclass 30, count 2 2006.257.07:12:11.38#ibcon#wrote, iclass 30, count 2 2006.257.07:12:11.38#ibcon#about to read 3, iclass 30, count 2 2006.257.07:12:11.40#ibcon#read 3, iclass 30, count 2 2006.257.07:12:11.40#ibcon#about to read 4, iclass 30, count 2 2006.257.07:12:11.40#ibcon#read 4, iclass 30, count 2 2006.257.07:12:11.40#ibcon#about to read 5, iclass 30, count 2 2006.257.07:12:11.40#ibcon#read 5, iclass 30, count 2 2006.257.07:12:11.40#ibcon#about to read 6, iclass 30, count 2 2006.257.07:12:11.40#ibcon#read 6, iclass 30, count 2 2006.257.07:12:11.40#ibcon#end of sib2, iclass 30, count 2 2006.257.07:12:11.40#ibcon#*mode == 0, iclass 30, count 2 2006.257.07:12:11.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.07:12:11.40#ibcon#[25=AT07-04\r\n] 2006.257.07:12:11.40#ibcon#*before write, iclass 30, count 2 2006.257.07:12:11.40#ibcon#enter sib2, iclass 30, count 2 2006.257.07:12:11.40#ibcon#flushed, iclass 30, count 2 2006.257.07:12:11.40#ibcon#about to write, iclass 30, count 2 2006.257.07:12:11.40#ibcon#wrote, iclass 30, count 2 2006.257.07:12:11.40#ibcon#about to read 3, iclass 30, count 2 2006.257.07:12:11.43#ibcon#read 3, iclass 30, count 2 2006.257.07:12:11.43#ibcon#about to read 4, iclass 30, count 2 2006.257.07:12:11.43#ibcon#read 4, iclass 30, count 2 2006.257.07:12:11.43#ibcon#about to read 5, iclass 30, count 2 2006.257.07:12:11.43#ibcon#read 5, iclass 30, count 2 2006.257.07:12:11.43#ibcon#about to read 6, iclass 30, count 2 2006.257.07:12:11.43#ibcon#read 6, iclass 30, count 2 2006.257.07:12:11.43#ibcon#end of sib2, iclass 30, count 2 2006.257.07:12:11.43#ibcon#*after write, iclass 30, count 2 2006.257.07:12:11.43#ibcon#*before return 0, iclass 30, count 2 2006.257.07:12:11.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:11.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:11.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.07:12:11.43#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:11.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:11.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:11.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:11.55#ibcon#enter wrdev, iclass 30, count 0 2006.257.07:12:11.55#ibcon#first serial, iclass 30, count 0 2006.257.07:12:11.55#ibcon#enter sib2, iclass 30, count 0 2006.257.07:12:11.55#ibcon#flushed, iclass 30, count 0 2006.257.07:12:11.55#ibcon#about to write, iclass 30, count 0 2006.257.07:12:11.55#ibcon#wrote, iclass 30, count 0 2006.257.07:12:11.55#ibcon#about to read 3, iclass 30, count 0 2006.257.07:12:11.57#ibcon#read 3, iclass 30, count 0 2006.257.07:12:11.57#ibcon#about to read 4, iclass 30, count 0 2006.257.07:12:11.57#ibcon#read 4, iclass 30, count 0 2006.257.07:12:11.57#ibcon#about to read 5, iclass 30, count 0 2006.257.07:12:11.57#ibcon#read 5, iclass 30, count 0 2006.257.07:12:11.57#ibcon#about to read 6, iclass 30, count 0 2006.257.07:12:11.57#ibcon#read 6, iclass 30, count 0 2006.257.07:12:11.57#ibcon#end of sib2, iclass 30, count 0 2006.257.07:12:11.57#ibcon#*mode == 0, iclass 30, count 0 2006.257.07:12:11.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.07:12:11.57#ibcon#[25=USB\r\n] 2006.257.07:12:11.57#ibcon#*before write, iclass 30, count 0 2006.257.07:12:11.57#ibcon#enter sib2, iclass 30, count 0 2006.257.07:12:11.57#ibcon#flushed, iclass 30, count 0 2006.257.07:12:11.57#ibcon#about to write, iclass 30, count 0 2006.257.07:12:11.57#ibcon#wrote, iclass 30, count 0 2006.257.07:12:11.57#ibcon#about to read 3, iclass 30, count 0 2006.257.07:12:11.60#ibcon#read 3, iclass 30, count 0 2006.257.07:12:11.60#ibcon#about to read 4, iclass 30, count 0 2006.257.07:12:11.60#ibcon#read 4, iclass 30, count 0 2006.257.07:12:11.60#ibcon#about to read 5, iclass 30, count 0 2006.257.07:12:11.60#ibcon#read 5, iclass 30, count 0 2006.257.07:12:11.60#ibcon#about to read 6, iclass 30, count 0 2006.257.07:12:11.60#ibcon#read 6, iclass 30, count 0 2006.257.07:12:11.60#ibcon#end of sib2, iclass 30, count 0 2006.257.07:12:11.60#ibcon#*after write, iclass 30, count 0 2006.257.07:12:11.60#ibcon#*before return 0, iclass 30, count 0 2006.257.07:12:11.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:11.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:11.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.07:12:11.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.07:12:11.60$vck44/valo=8,884.99 2006.257.07:12:11.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.07:12:11.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.07:12:11.60#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:11.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:11.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:11.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:11.60#ibcon#enter wrdev, iclass 32, count 0 2006.257.07:12:11.60#ibcon#first serial, iclass 32, count 0 2006.257.07:12:11.60#ibcon#enter sib2, iclass 32, count 0 2006.257.07:12:11.60#ibcon#flushed, iclass 32, count 0 2006.257.07:12:11.60#ibcon#about to write, iclass 32, count 0 2006.257.07:12:11.60#ibcon#wrote, iclass 32, count 0 2006.257.07:12:11.60#ibcon#about to read 3, iclass 32, count 0 2006.257.07:12:11.62#ibcon#read 3, iclass 32, count 0 2006.257.07:12:11.62#ibcon#about to read 4, iclass 32, count 0 2006.257.07:12:11.62#ibcon#read 4, iclass 32, count 0 2006.257.07:12:11.62#ibcon#about to read 5, iclass 32, count 0 2006.257.07:12:11.62#ibcon#read 5, iclass 32, count 0 2006.257.07:12:11.62#ibcon#about to read 6, iclass 32, count 0 2006.257.07:12:11.62#ibcon#read 6, iclass 32, count 0 2006.257.07:12:11.62#ibcon#end of sib2, iclass 32, count 0 2006.257.07:12:11.62#ibcon#*mode == 0, iclass 32, count 0 2006.257.07:12:11.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.07:12:11.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.07:12:11.62#ibcon#*before write, iclass 32, count 0 2006.257.07:12:11.62#ibcon#enter sib2, iclass 32, count 0 2006.257.07:12:11.62#ibcon#flushed, iclass 32, count 0 2006.257.07:12:11.62#ibcon#about to write, iclass 32, count 0 2006.257.07:12:11.62#ibcon#wrote, iclass 32, count 0 2006.257.07:12:11.62#ibcon#about to read 3, iclass 32, count 0 2006.257.07:12:11.66#ibcon#read 3, iclass 32, count 0 2006.257.07:12:11.66#ibcon#about to read 4, iclass 32, count 0 2006.257.07:12:11.66#ibcon#read 4, iclass 32, count 0 2006.257.07:12:11.66#ibcon#about to read 5, iclass 32, count 0 2006.257.07:12:11.66#ibcon#read 5, iclass 32, count 0 2006.257.07:12:11.66#ibcon#about to read 6, iclass 32, count 0 2006.257.07:12:11.66#ibcon#read 6, iclass 32, count 0 2006.257.07:12:11.66#ibcon#end of sib2, iclass 32, count 0 2006.257.07:12:11.66#ibcon#*after write, iclass 32, count 0 2006.257.07:12:11.66#ibcon#*before return 0, iclass 32, count 0 2006.257.07:12:11.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:11.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:11.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.07:12:11.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.07:12:11.66$vck44/va=8,4 2006.257.07:12:11.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.07:12:11.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.07:12:11.66#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:11.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:12:11.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:12:11.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:12:11.72#ibcon#enter wrdev, iclass 34, count 2 2006.257.07:12:11.72#ibcon#first serial, iclass 34, count 2 2006.257.07:12:11.72#ibcon#enter sib2, iclass 34, count 2 2006.257.07:12:11.72#ibcon#flushed, iclass 34, count 2 2006.257.07:12:11.72#ibcon#about to write, iclass 34, count 2 2006.257.07:12:11.72#ibcon#wrote, iclass 34, count 2 2006.257.07:12:11.72#ibcon#about to read 3, iclass 34, count 2 2006.257.07:12:11.74#ibcon#read 3, iclass 34, count 2 2006.257.07:12:11.74#ibcon#about to read 4, iclass 34, count 2 2006.257.07:12:11.74#ibcon#read 4, iclass 34, count 2 2006.257.07:12:11.74#ibcon#about to read 5, iclass 34, count 2 2006.257.07:12:11.74#ibcon#read 5, iclass 34, count 2 2006.257.07:12:11.74#ibcon#about to read 6, iclass 34, count 2 2006.257.07:12:11.74#ibcon#read 6, iclass 34, count 2 2006.257.07:12:11.74#ibcon#end of sib2, iclass 34, count 2 2006.257.07:12:11.74#ibcon#*mode == 0, iclass 34, count 2 2006.257.07:12:11.74#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.07:12:11.74#ibcon#[25=AT08-04\r\n] 2006.257.07:12:11.74#ibcon#*before write, iclass 34, count 2 2006.257.07:12:11.74#ibcon#enter sib2, iclass 34, count 2 2006.257.07:12:11.74#ibcon#flushed, iclass 34, count 2 2006.257.07:12:11.74#ibcon#about to write, iclass 34, count 2 2006.257.07:12:11.74#ibcon#wrote, iclass 34, count 2 2006.257.07:12:11.74#ibcon#about to read 3, iclass 34, count 2 2006.257.07:12:11.77#ibcon#read 3, iclass 34, count 2 2006.257.07:12:11.77#ibcon#about to read 4, iclass 34, count 2 2006.257.07:12:11.77#ibcon#read 4, iclass 34, count 2 2006.257.07:12:11.77#ibcon#about to read 5, iclass 34, count 2 2006.257.07:12:11.77#ibcon#read 5, iclass 34, count 2 2006.257.07:12:11.77#ibcon#about to read 6, iclass 34, count 2 2006.257.07:12:11.77#ibcon#read 6, iclass 34, count 2 2006.257.07:12:11.77#ibcon#end of sib2, iclass 34, count 2 2006.257.07:12:11.77#ibcon#*after write, iclass 34, count 2 2006.257.07:12:11.77#ibcon#*before return 0, iclass 34, count 2 2006.257.07:12:11.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:12:11.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:12:11.77#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.07:12:11.77#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:11.77#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:12:11.89#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:12:11.89#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:12:11.89#ibcon#enter wrdev, iclass 34, count 0 2006.257.07:12:11.89#ibcon#first serial, iclass 34, count 0 2006.257.07:12:11.89#ibcon#enter sib2, iclass 34, count 0 2006.257.07:12:11.89#ibcon#flushed, iclass 34, count 0 2006.257.07:12:11.89#ibcon#about to write, iclass 34, count 0 2006.257.07:12:11.89#ibcon#wrote, iclass 34, count 0 2006.257.07:12:11.89#ibcon#about to read 3, iclass 34, count 0 2006.257.07:12:11.91#ibcon#read 3, iclass 34, count 0 2006.257.07:12:11.91#ibcon#about to read 4, iclass 34, count 0 2006.257.07:12:11.91#ibcon#read 4, iclass 34, count 0 2006.257.07:12:11.91#ibcon#about to read 5, iclass 34, count 0 2006.257.07:12:11.91#ibcon#read 5, iclass 34, count 0 2006.257.07:12:11.91#ibcon#about to read 6, iclass 34, count 0 2006.257.07:12:11.91#ibcon#read 6, iclass 34, count 0 2006.257.07:12:11.91#ibcon#end of sib2, iclass 34, count 0 2006.257.07:12:11.91#ibcon#*mode == 0, iclass 34, count 0 2006.257.07:12:11.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.07:12:11.91#ibcon#[25=USB\r\n] 2006.257.07:12:11.91#ibcon#*before write, iclass 34, count 0 2006.257.07:12:11.91#ibcon#enter sib2, iclass 34, count 0 2006.257.07:12:11.91#ibcon#flushed, iclass 34, count 0 2006.257.07:12:11.91#ibcon#about to write, iclass 34, count 0 2006.257.07:12:11.91#ibcon#wrote, iclass 34, count 0 2006.257.07:12:11.91#ibcon#about to read 3, iclass 34, count 0 2006.257.07:12:11.94#ibcon#read 3, iclass 34, count 0 2006.257.07:12:11.94#ibcon#about to read 4, iclass 34, count 0 2006.257.07:12:11.94#ibcon#read 4, iclass 34, count 0 2006.257.07:12:11.94#ibcon#about to read 5, iclass 34, count 0 2006.257.07:12:11.94#ibcon#read 5, iclass 34, count 0 2006.257.07:12:11.94#ibcon#about to read 6, iclass 34, count 0 2006.257.07:12:11.94#ibcon#read 6, iclass 34, count 0 2006.257.07:12:11.94#ibcon#end of sib2, iclass 34, count 0 2006.257.07:12:11.94#ibcon#*after write, iclass 34, count 0 2006.257.07:12:11.94#ibcon#*before return 0, iclass 34, count 0 2006.257.07:12:11.94#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:12:11.94#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:12:11.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.07:12:11.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.07:12:11.94$vck44/vblo=1,629.99 2006.257.07:12:11.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.07:12:11.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.07:12:11.94#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:11.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:12:11.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:12:11.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:12:11.94#ibcon#enter wrdev, iclass 36, count 0 2006.257.07:12:11.94#ibcon#first serial, iclass 36, count 0 2006.257.07:12:11.94#ibcon#enter sib2, iclass 36, count 0 2006.257.07:12:11.94#ibcon#flushed, iclass 36, count 0 2006.257.07:12:11.94#ibcon#about to write, iclass 36, count 0 2006.257.07:12:11.94#ibcon#wrote, iclass 36, count 0 2006.257.07:12:11.94#ibcon#about to read 3, iclass 36, count 0 2006.257.07:12:11.96#ibcon#read 3, iclass 36, count 0 2006.257.07:12:11.96#ibcon#about to read 4, iclass 36, count 0 2006.257.07:12:11.96#ibcon#read 4, iclass 36, count 0 2006.257.07:12:11.96#ibcon#about to read 5, iclass 36, count 0 2006.257.07:12:11.96#ibcon#read 5, iclass 36, count 0 2006.257.07:12:11.96#ibcon#about to read 6, iclass 36, count 0 2006.257.07:12:11.96#ibcon#read 6, iclass 36, count 0 2006.257.07:12:11.96#ibcon#end of sib2, iclass 36, count 0 2006.257.07:12:11.96#ibcon#*mode == 0, iclass 36, count 0 2006.257.07:12:11.96#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.07:12:11.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.07:12:11.96#ibcon#*before write, iclass 36, count 0 2006.257.07:12:11.96#ibcon#enter sib2, iclass 36, count 0 2006.257.07:12:11.96#ibcon#flushed, iclass 36, count 0 2006.257.07:12:11.96#ibcon#about to write, iclass 36, count 0 2006.257.07:12:11.96#ibcon#wrote, iclass 36, count 0 2006.257.07:12:11.96#ibcon#about to read 3, iclass 36, count 0 2006.257.07:12:12.00#ibcon#read 3, iclass 36, count 0 2006.257.07:12:12.00#ibcon#about to read 4, iclass 36, count 0 2006.257.07:12:12.00#ibcon#read 4, iclass 36, count 0 2006.257.07:12:12.00#ibcon#about to read 5, iclass 36, count 0 2006.257.07:12:12.00#ibcon#read 5, iclass 36, count 0 2006.257.07:12:12.00#ibcon#about to read 6, iclass 36, count 0 2006.257.07:12:12.00#ibcon#read 6, iclass 36, count 0 2006.257.07:12:12.00#ibcon#end of sib2, iclass 36, count 0 2006.257.07:12:12.00#ibcon#*after write, iclass 36, count 0 2006.257.07:12:12.00#ibcon#*before return 0, iclass 36, count 0 2006.257.07:12:12.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:12:12.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:12:12.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.07:12:12.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.07:12:12.00$vck44/vb=1,4 2006.257.07:12:12.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.07:12:12.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.07:12:12.00#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:12.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:12:12.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:12:12.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:12:12.00#ibcon#enter wrdev, iclass 38, count 2 2006.257.07:12:12.00#ibcon#first serial, iclass 38, count 2 2006.257.07:12:12.00#ibcon#enter sib2, iclass 38, count 2 2006.257.07:12:12.00#ibcon#flushed, iclass 38, count 2 2006.257.07:12:12.00#ibcon#about to write, iclass 38, count 2 2006.257.07:12:12.00#ibcon#wrote, iclass 38, count 2 2006.257.07:12:12.00#ibcon#about to read 3, iclass 38, count 2 2006.257.07:12:12.02#ibcon#read 3, iclass 38, count 2 2006.257.07:12:12.02#ibcon#about to read 4, iclass 38, count 2 2006.257.07:12:12.02#ibcon#read 4, iclass 38, count 2 2006.257.07:12:12.02#ibcon#about to read 5, iclass 38, count 2 2006.257.07:12:12.02#ibcon#read 5, iclass 38, count 2 2006.257.07:12:12.02#ibcon#about to read 6, iclass 38, count 2 2006.257.07:12:12.02#ibcon#read 6, iclass 38, count 2 2006.257.07:12:12.02#ibcon#end of sib2, iclass 38, count 2 2006.257.07:12:12.02#ibcon#*mode == 0, iclass 38, count 2 2006.257.07:12:12.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.07:12:12.02#ibcon#[27=AT01-04\r\n] 2006.257.07:12:12.02#ibcon#*before write, iclass 38, count 2 2006.257.07:12:12.02#ibcon#enter sib2, iclass 38, count 2 2006.257.07:12:12.02#ibcon#flushed, iclass 38, count 2 2006.257.07:12:12.02#ibcon#about to write, iclass 38, count 2 2006.257.07:12:12.02#ibcon#wrote, iclass 38, count 2 2006.257.07:12:12.02#ibcon#about to read 3, iclass 38, count 2 2006.257.07:12:12.05#ibcon#read 3, iclass 38, count 2 2006.257.07:12:12.05#ibcon#about to read 4, iclass 38, count 2 2006.257.07:12:12.05#ibcon#read 4, iclass 38, count 2 2006.257.07:12:12.05#ibcon#about to read 5, iclass 38, count 2 2006.257.07:12:12.05#ibcon#read 5, iclass 38, count 2 2006.257.07:12:12.05#ibcon#about to read 6, iclass 38, count 2 2006.257.07:12:12.05#ibcon#read 6, iclass 38, count 2 2006.257.07:12:12.05#ibcon#end of sib2, iclass 38, count 2 2006.257.07:12:12.05#ibcon#*after write, iclass 38, count 2 2006.257.07:12:12.05#ibcon#*before return 0, iclass 38, count 2 2006.257.07:12:12.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:12:12.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:12:12.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.07:12:12.05#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:12.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:12:12.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:12:12.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:12:12.17#ibcon#enter wrdev, iclass 38, count 0 2006.257.07:12:12.17#ibcon#first serial, iclass 38, count 0 2006.257.07:12:12.17#ibcon#enter sib2, iclass 38, count 0 2006.257.07:12:12.17#ibcon#flushed, iclass 38, count 0 2006.257.07:12:12.17#ibcon#about to write, iclass 38, count 0 2006.257.07:12:12.17#ibcon#wrote, iclass 38, count 0 2006.257.07:12:12.17#ibcon#about to read 3, iclass 38, count 0 2006.257.07:12:12.19#ibcon#read 3, iclass 38, count 0 2006.257.07:12:12.19#ibcon#about to read 4, iclass 38, count 0 2006.257.07:12:12.19#ibcon#read 4, iclass 38, count 0 2006.257.07:12:12.19#ibcon#about to read 5, iclass 38, count 0 2006.257.07:12:12.19#ibcon#read 5, iclass 38, count 0 2006.257.07:12:12.19#ibcon#about to read 6, iclass 38, count 0 2006.257.07:12:12.19#ibcon#read 6, iclass 38, count 0 2006.257.07:12:12.19#ibcon#end of sib2, iclass 38, count 0 2006.257.07:12:12.19#ibcon#*mode == 0, iclass 38, count 0 2006.257.07:12:12.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.07:12:12.19#ibcon#[27=USB\r\n] 2006.257.07:12:12.19#ibcon#*before write, iclass 38, count 0 2006.257.07:12:12.19#ibcon#enter sib2, iclass 38, count 0 2006.257.07:12:12.19#ibcon#flushed, iclass 38, count 0 2006.257.07:12:12.19#ibcon#about to write, iclass 38, count 0 2006.257.07:12:12.19#ibcon#wrote, iclass 38, count 0 2006.257.07:12:12.19#ibcon#about to read 3, iclass 38, count 0 2006.257.07:12:12.22#ibcon#read 3, iclass 38, count 0 2006.257.07:12:12.22#ibcon#about to read 4, iclass 38, count 0 2006.257.07:12:12.22#ibcon#read 4, iclass 38, count 0 2006.257.07:12:12.22#ibcon#about to read 5, iclass 38, count 0 2006.257.07:12:12.22#ibcon#read 5, iclass 38, count 0 2006.257.07:12:12.22#ibcon#about to read 6, iclass 38, count 0 2006.257.07:12:12.22#ibcon#read 6, iclass 38, count 0 2006.257.07:12:12.22#ibcon#end of sib2, iclass 38, count 0 2006.257.07:12:12.22#ibcon#*after write, iclass 38, count 0 2006.257.07:12:12.22#ibcon#*before return 0, iclass 38, count 0 2006.257.07:12:12.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:12:12.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:12:12.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.07:12:12.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.07:12:12.22$vck44/vblo=2,634.99 2006.257.07:12:12.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.07:12:12.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.07:12:12.22#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:12.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:12.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:12.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:12.22#ibcon#enter wrdev, iclass 40, count 0 2006.257.07:12:12.22#ibcon#first serial, iclass 40, count 0 2006.257.07:12:12.22#ibcon#enter sib2, iclass 40, count 0 2006.257.07:12:12.22#ibcon#flushed, iclass 40, count 0 2006.257.07:12:12.22#ibcon#about to write, iclass 40, count 0 2006.257.07:12:12.22#ibcon#wrote, iclass 40, count 0 2006.257.07:12:12.22#ibcon#about to read 3, iclass 40, count 0 2006.257.07:12:12.24#ibcon#read 3, iclass 40, count 0 2006.257.07:12:12.24#ibcon#about to read 4, iclass 40, count 0 2006.257.07:12:12.24#ibcon#read 4, iclass 40, count 0 2006.257.07:12:12.24#ibcon#about to read 5, iclass 40, count 0 2006.257.07:12:12.24#ibcon#read 5, iclass 40, count 0 2006.257.07:12:12.24#ibcon#about to read 6, iclass 40, count 0 2006.257.07:12:12.24#ibcon#read 6, iclass 40, count 0 2006.257.07:12:12.24#ibcon#end of sib2, iclass 40, count 0 2006.257.07:12:12.24#ibcon#*mode == 0, iclass 40, count 0 2006.257.07:12:12.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.07:12:12.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.07:12:12.24#ibcon#*before write, iclass 40, count 0 2006.257.07:12:12.24#ibcon#enter sib2, iclass 40, count 0 2006.257.07:12:12.24#ibcon#flushed, iclass 40, count 0 2006.257.07:12:12.24#ibcon#about to write, iclass 40, count 0 2006.257.07:12:12.24#ibcon#wrote, iclass 40, count 0 2006.257.07:12:12.24#ibcon#about to read 3, iclass 40, count 0 2006.257.07:12:12.28#ibcon#read 3, iclass 40, count 0 2006.257.07:12:12.28#ibcon#about to read 4, iclass 40, count 0 2006.257.07:12:12.28#ibcon#read 4, iclass 40, count 0 2006.257.07:12:12.28#ibcon#about to read 5, iclass 40, count 0 2006.257.07:12:12.28#ibcon#read 5, iclass 40, count 0 2006.257.07:12:12.28#ibcon#about to read 6, iclass 40, count 0 2006.257.07:12:12.28#ibcon#read 6, iclass 40, count 0 2006.257.07:12:12.28#ibcon#end of sib2, iclass 40, count 0 2006.257.07:12:12.28#ibcon#*after write, iclass 40, count 0 2006.257.07:12:12.28#ibcon#*before return 0, iclass 40, count 0 2006.257.07:12:12.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:12.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:12:12.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.07:12:12.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.07:12:12.28$vck44/vb=2,5 2006.257.07:12:12.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.07:12:12.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.07:12:12.28#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:12.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:12.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:12.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:12.34#ibcon#enter wrdev, iclass 4, count 2 2006.257.07:12:12.34#ibcon#first serial, iclass 4, count 2 2006.257.07:12:12.34#ibcon#enter sib2, iclass 4, count 2 2006.257.07:12:12.34#ibcon#flushed, iclass 4, count 2 2006.257.07:12:12.34#ibcon#about to write, iclass 4, count 2 2006.257.07:12:12.34#ibcon#wrote, iclass 4, count 2 2006.257.07:12:12.34#ibcon#about to read 3, iclass 4, count 2 2006.257.07:12:12.36#ibcon#read 3, iclass 4, count 2 2006.257.07:12:12.36#ibcon#about to read 4, iclass 4, count 2 2006.257.07:12:12.36#ibcon#read 4, iclass 4, count 2 2006.257.07:12:12.36#ibcon#about to read 5, iclass 4, count 2 2006.257.07:12:12.36#ibcon#read 5, iclass 4, count 2 2006.257.07:12:12.36#ibcon#about to read 6, iclass 4, count 2 2006.257.07:12:12.36#ibcon#read 6, iclass 4, count 2 2006.257.07:12:12.36#ibcon#end of sib2, iclass 4, count 2 2006.257.07:12:12.36#ibcon#*mode == 0, iclass 4, count 2 2006.257.07:12:12.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.07:12:12.36#ibcon#[27=AT02-05\r\n] 2006.257.07:12:12.36#ibcon#*before write, iclass 4, count 2 2006.257.07:12:12.36#ibcon#enter sib2, iclass 4, count 2 2006.257.07:12:12.36#ibcon#flushed, iclass 4, count 2 2006.257.07:12:12.36#ibcon#about to write, iclass 4, count 2 2006.257.07:12:12.36#ibcon#wrote, iclass 4, count 2 2006.257.07:12:12.36#ibcon#about to read 3, iclass 4, count 2 2006.257.07:12:12.39#ibcon#read 3, iclass 4, count 2 2006.257.07:12:12.39#ibcon#about to read 4, iclass 4, count 2 2006.257.07:12:12.39#ibcon#read 4, iclass 4, count 2 2006.257.07:12:12.39#ibcon#about to read 5, iclass 4, count 2 2006.257.07:12:12.39#ibcon#read 5, iclass 4, count 2 2006.257.07:12:12.39#ibcon#about to read 6, iclass 4, count 2 2006.257.07:12:12.39#ibcon#read 6, iclass 4, count 2 2006.257.07:12:12.39#ibcon#end of sib2, iclass 4, count 2 2006.257.07:12:12.39#ibcon#*after write, iclass 4, count 2 2006.257.07:12:12.39#ibcon#*before return 0, iclass 4, count 2 2006.257.07:12:12.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:12.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:12:12.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.07:12:12.39#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:12.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:12.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:12.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:12.51#ibcon#enter wrdev, iclass 4, count 0 2006.257.07:12:12.51#ibcon#first serial, iclass 4, count 0 2006.257.07:12:12.51#ibcon#enter sib2, iclass 4, count 0 2006.257.07:12:12.51#ibcon#flushed, iclass 4, count 0 2006.257.07:12:12.51#ibcon#about to write, iclass 4, count 0 2006.257.07:12:12.51#ibcon#wrote, iclass 4, count 0 2006.257.07:12:12.51#ibcon#about to read 3, iclass 4, count 0 2006.257.07:12:12.53#ibcon#read 3, iclass 4, count 0 2006.257.07:12:12.53#ibcon#about to read 4, iclass 4, count 0 2006.257.07:12:12.53#ibcon#read 4, iclass 4, count 0 2006.257.07:12:12.53#ibcon#about to read 5, iclass 4, count 0 2006.257.07:12:12.53#ibcon#read 5, iclass 4, count 0 2006.257.07:12:12.53#ibcon#about to read 6, iclass 4, count 0 2006.257.07:12:12.53#ibcon#read 6, iclass 4, count 0 2006.257.07:12:12.53#ibcon#end of sib2, iclass 4, count 0 2006.257.07:12:12.53#ibcon#*mode == 0, iclass 4, count 0 2006.257.07:12:12.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.07:12:12.53#ibcon#[27=USB\r\n] 2006.257.07:12:12.53#ibcon#*before write, iclass 4, count 0 2006.257.07:12:12.53#ibcon#enter sib2, iclass 4, count 0 2006.257.07:12:12.53#ibcon#flushed, iclass 4, count 0 2006.257.07:12:12.53#ibcon#about to write, iclass 4, count 0 2006.257.07:12:12.53#ibcon#wrote, iclass 4, count 0 2006.257.07:12:12.53#ibcon#about to read 3, iclass 4, count 0 2006.257.07:12:12.56#ibcon#read 3, iclass 4, count 0 2006.257.07:12:12.56#ibcon#about to read 4, iclass 4, count 0 2006.257.07:12:12.56#ibcon#read 4, iclass 4, count 0 2006.257.07:12:12.56#ibcon#about to read 5, iclass 4, count 0 2006.257.07:12:12.56#ibcon#read 5, iclass 4, count 0 2006.257.07:12:12.56#ibcon#about to read 6, iclass 4, count 0 2006.257.07:12:12.56#ibcon#read 6, iclass 4, count 0 2006.257.07:12:12.56#ibcon#end of sib2, iclass 4, count 0 2006.257.07:12:12.56#ibcon#*after write, iclass 4, count 0 2006.257.07:12:12.56#ibcon#*before return 0, iclass 4, count 0 2006.257.07:12:12.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:12.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:12:12.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.07:12:12.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.07:12:12.56$vck44/vblo=3,649.99 2006.257.07:12:12.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.07:12:12.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.07:12:12.56#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:12.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:12.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:12.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:12.56#ibcon#enter wrdev, iclass 6, count 0 2006.257.07:12:12.56#ibcon#first serial, iclass 6, count 0 2006.257.07:12:12.56#ibcon#enter sib2, iclass 6, count 0 2006.257.07:12:12.56#ibcon#flushed, iclass 6, count 0 2006.257.07:12:12.56#ibcon#about to write, iclass 6, count 0 2006.257.07:12:12.56#ibcon#wrote, iclass 6, count 0 2006.257.07:12:12.56#ibcon#about to read 3, iclass 6, count 0 2006.257.07:12:12.58#ibcon#read 3, iclass 6, count 0 2006.257.07:12:12.58#ibcon#about to read 4, iclass 6, count 0 2006.257.07:12:12.58#ibcon#read 4, iclass 6, count 0 2006.257.07:12:12.58#ibcon#about to read 5, iclass 6, count 0 2006.257.07:12:12.58#ibcon#read 5, iclass 6, count 0 2006.257.07:12:12.58#ibcon#about to read 6, iclass 6, count 0 2006.257.07:12:12.58#ibcon#read 6, iclass 6, count 0 2006.257.07:12:12.58#ibcon#end of sib2, iclass 6, count 0 2006.257.07:12:12.58#ibcon#*mode == 0, iclass 6, count 0 2006.257.07:12:12.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.07:12:12.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.07:12:12.58#ibcon#*before write, iclass 6, count 0 2006.257.07:12:12.58#ibcon#enter sib2, iclass 6, count 0 2006.257.07:12:12.58#ibcon#flushed, iclass 6, count 0 2006.257.07:12:12.58#ibcon#about to write, iclass 6, count 0 2006.257.07:12:12.58#ibcon#wrote, iclass 6, count 0 2006.257.07:12:12.58#ibcon#about to read 3, iclass 6, count 0 2006.257.07:12:12.62#ibcon#read 3, iclass 6, count 0 2006.257.07:12:12.62#ibcon#about to read 4, iclass 6, count 0 2006.257.07:12:12.62#ibcon#read 4, iclass 6, count 0 2006.257.07:12:12.62#ibcon#about to read 5, iclass 6, count 0 2006.257.07:12:12.62#ibcon#read 5, iclass 6, count 0 2006.257.07:12:12.62#ibcon#about to read 6, iclass 6, count 0 2006.257.07:12:12.62#ibcon#read 6, iclass 6, count 0 2006.257.07:12:12.62#ibcon#end of sib2, iclass 6, count 0 2006.257.07:12:12.62#ibcon#*after write, iclass 6, count 0 2006.257.07:12:12.62#ibcon#*before return 0, iclass 6, count 0 2006.257.07:12:12.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:12.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:12:12.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.07:12:12.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.07:12:12.62$vck44/vb=3,4 2006.257.07:12:12.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.07:12:12.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.07:12:12.62#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:12.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:12.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:12.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:12.68#ibcon#enter wrdev, iclass 10, count 2 2006.257.07:12:12.68#ibcon#first serial, iclass 10, count 2 2006.257.07:12:12.68#ibcon#enter sib2, iclass 10, count 2 2006.257.07:12:12.68#ibcon#flushed, iclass 10, count 2 2006.257.07:12:12.68#ibcon#about to write, iclass 10, count 2 2006.257.07:12:12.68#ibcon#wrote, iclass 10, count 2 2006.257.07:12:12.68#ibcon#about to read 3, iclass 10, count 2 2006.257.07:12:12.70#ibcon#read 3, iclass 10, count 2 2006.257.07:12:12.70#ibcon#about to read 4, iclass 10, count 2 2006.257.07:12:12.70#ibcon#read 4, iclass 10, count 2 2006.257.07:12:12.70#ibcon#about to read 5, iclass 10, count 2 2006.257.07:12:12.70#ibcon#read 5, iclass 10, count 2 2006.257.07:12:12.70#ibcon#about to read 6, iclass 10, count 2 2006.257.07:12:12.70#ibcon#read 6, iclass 10, count 2 2006.257.07:12:12.70#ibcon#end of sib2, iclass 10, count 2 2006.257.07:12:12.70#ibcon#*mode == 0, iclass 10, count 2 2006.257.07:12:12.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.07:12:12.70#ibcon#[27=AT03-04\r\n] 2006.257.07:12:12.70#ibcon#*before write, iclass 10, count 2 2006.257.07:12:12.70#ibcon#enter sib2, iclass 10, count 2 2006.257.07:12:12.70#ibcon#flushed, iclass 10, count 2 2006.257.07:12:12.70#ibcon#about to write, iclass 10, count 2 2006.257.07:12:12.70#ibcon#wrote, iclass 10, count 2 2006.257.07:12:12.70#ibcon#about to read 3, iclass 10, count 2 2006.257.07:12:12.73#ibcon#read 3, iclass 10, count 2 2006.257.07:12:12.73#ibcon#about to read 4, iclass 10, count 2 2006.257.07:12:12.73#ibcon#read 4, iclass 10, count 2 2006.257.07:12:12.73#ibcon#about to read 5, iclass 10, count 2 2006.257.07:12:12.73#ibcon#read 5, iclass 10, count 2 2006.257.07:12:12.73#ibcon#about to read 6, iclass 10, count 2 2006.257.07:12:12.73#ibcon#read 6, iclass 10, count 2 2006.257.07:12:12.73#ibcon#end of sib2, iclass 10, count 2 2006.257.07:12:12.73#ibcon#*after write, iclass 10, count 2 2006.257.07:12:12.73#ibcon#*before return 0, iclass 10, count 2 2006.257.07:12:12.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:12.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:12:12.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.07:12:12.73#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:12.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:12.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:12.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:12.85#ibcon#enter wrdev, iclass 10, count 0 2006.257.07:12:12.85#ibcon#first serial, iclass 10, count 0 2006.257.07:12:12.85#ibcon#enter sib2, iclass 10, count 0 2006.257.07:12:12.85#ibcon#flushed, iclass 10, count 0 2006.257.07:12:12.85#ibcon#about to write, iclass 10, count 0 2006.257.07:12:12.85#ibcon#wrote, iclass 10, count 0 2006.257.07:12:12.85#ibcon#about to read 3, iclass 10, count 0 2006.257.07:12:12.87#ibcon#read 3, iclass 10, count 0 2006.257.07:12:12.87#ibcon#about to read 4, iclass 10, count 0 2006.257.07:12:12.87#ibcon#read 4, iclass 10, count 0 2006.257.07:12:12.87#ibcon#about to read 5, iclass 10, count 0 2006.257.07:12:12.87#ibcon#read 5, iclass 10, count 0 2006.257.07:12:12.87#ibcon#about to read 6, iclass 10, count 0 2006.257.07:12:12.87#ibcon#read 6, iclass 10, count 0 2006.257.07:12:12.87#ibcon#end of sib2, iclass 10, count 0 2006.257.07:12:12.87#ibcon#*mode == 0, iclass 10, count 0 2006.257.07:12:12.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.07:12:12.87#ibcon#[27=USB\r\n] 2006.257.07:12:12.87#ibcon#*before write, iclass 10, count 0 2006.257.07:12:12.87#ibcon#enter sib2, iclass 10, count 0 2006.257.07:12:12.87#ibcon#flushed, iclass 10, count 0 2006.257.07:12:12.87#ibcon#about to write, iclass 10, count 0 2006.257.07:12:12.87#ibcon#wrote, iclass 10, count 0 2006.257.07:12:12.87#ibcon#about to read 3, iclass 10, count 0 2006.257.07:12:12.90#ibcon#read 3, iclass 10, count 0 2006.257.07:12:12.90#ibcon#about to read 4, iclass 10, count 0 2006.257.07:12:12.90#ibcon#read 4, iclass 10, count 0 2006.257.07:12:12.90#ibcon#about to read 5, iclass 10, count 0 2006.257.07:12:12.90#ibcon#read 5, iclass 10, count 0 2006.257.07:12:12.90#ibcon#about to read 6, iclass 10, count 0 2006.257.07:12:12.90#ibcon#read 6, iclass 10, count 0 2006.257.07:12:12.90#ibcon#end of sib2, iclass 10, count 0 2006.257.07:12:12.90#ibcon#*after write, iclass 10, count 0 2006.257.07:12:12.90#ibcon#*before return 0, iclass 10, count 0 2006.257.07:12:12.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:12.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:12:12.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.07:12:12.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.07:12:12.90$vck44/vblo=4,679.99 2006.257.07:12:12.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.07:12:12.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.07:12:12.90#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:12.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:12.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:12.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:12.90#ibcon#enter wrdev, iclass 12, count 0 2006.257.07:12:12.90#ibcon#first serial, iclass 12, count 0 2006.257.07:12:12.90#ibcon#enter sib2, iclass 12, count 0 2006.257.07:12:12.90#ibcon#flushed, iclass 12, count 0 2006.257.07:12:12.90#ibcon#about to write, iclass 12, count 0 2006.257.07:12:12.90#ibcon#wrote, iclass 12, count 0 2006.257.07:12:12.90#ibcon#about to read 3, iclass 12, count 0 2006.257.07:12:12.92#ibcon#read 3, iclass 12, count 0 2006.257.07:12:12.92#ibcon#about to read 4, iclass 12, count 0 2006.257.07:12:12.92#ibcon#read 4, iclass 12, count 0 2006.257.07:12:12.92#ibcon#about to read 5, iclass 12, count 0 2006.257.07:12:12.92#ibcon#read 5, iclass 12, count 0 2006.257.07:12:12.92#ibcon#about to read 6, iclass 12, count 0 2006.257.07:12:12.92#ibcon#read 6, iclass 12, count 0 2006.257.07:12:12.92#ibcon#end of sib2, iclass 12, count 0 2006.257.07:12:12.92#ibcon#*mode == 0, iclass 12, count 0 2006.257.07:12:12.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.07:12:12.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.07:12:12.92#ibcon#*before write, iclass 12, count 0 2006.257.07:12:12.92#ibcon#enter sib2, iclass 12, count 0 2006.257.07:12:12.92#ibcon#flushed, iclass 12, count 0 2006.257.07:12:12.92#ibcon#about to write, iclass 12, count 0 2006.257.07:12:12.92#ibcon#wrote, iclass 12, count 0 2006.257.07:12:12.92#ibcon#about to read 3, iclass 12, count 0 2006.257.07:12:12.96#ibcon#read 3, iclass 12, count 0 2006.257.07:12:12.96#ibcon#about to read 4, iclass 12, count 0 2006.257.07:12:12.96#ibcon#read 4, iclass 12, count 0 2006.257.07:12:12.96#ibcon#about to read 5, iclass 12, count 0 2006.257.07:12:12.96#ibcon#read 5, iclass 12, count 0 2006.257.07:12:12.96#ibcon#about to read 6, iclass 12, count 0 2006.257.07:12:12.96#ibcon#read 6, iclass 12, count 0 2006.257.07:12:12.96#ibcon#end of sib2, iclass 12, count 0 2006.257.07:12:12.96#ibcon#*after write, iclass 12, count 0 2006.257.07:12:12.96#ibcon#*before return 0, iclass 12, count 0 2006.257.07:12:12.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:12.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:12:12.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.07:12:12.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.07:12:12.96$vck44/vb=4,5 2006.257.07:12:12.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.07:12:12.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.07:12:12.96#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:12.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:13.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:13.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:13.02#ibcon#enter wrdev, iclass 14, count 2 2006.257.07:12:13.02#ibcon#first serial, iclass 14, count 2 2006.257.07:12:13.02#ibcon#enter sib2, iclass 14, count 2 2006.257.07:12:13.02#ibcon#flushed, iclass 14, count 2 2006.257.07:12:13.02#ibcon#about to write, iclass 14, count 2 2006.257.07:12:13.02#ibcon#wrote, iclass 14, count 2 2006.257.07:12:13.02#ibcon#about to read 3, iclass 14, count 2 2006.257.07:12:13.04#ibcon#read 3, iclass 14, count 2 2006.257.07:12:13.04#ibcon#about to read 4, iclass 14, count 2 2006.257.07:12:13.04#ibcon#read 4, iclass 14, count 2 2006.257.07:12:13.04#ibcon#about to read 5, iclass 14, count 2 2006.257.07:12:13.04#ibcon#read 5, iclass 14, count 2 2006.257.07:12:13.04#ibcon#about to read 6, iclass 14, count 2 2006.257.07:12:13.04#ibcon#read 6, iclass 14, count 2 2006.257.07:12:13.04#ibcon#end of sib2, iclass 14, count 2 2006.257.07:12:13.04#ibcon#*mode == 0, iclass 14, count 2 2006.257.07:12:13.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.07:12:13.04#ibcon#[27=AT04-05\r\n] 2006.257.07:12:13.04#ibcon#*before write, iclass 14, count 2 2006.257.07:12:13.04#ibcon#enter sib2, iclass 14, count 2 2006.257.07:12:13.04#ibcon#flushed, iclass 14, count 2 2006.257.07:12:13.04#ibcon#about to write, iclass 14, count 2 2006.257.07:12:13.04#ibcon#wrote, iclass 14, count 2 2006.257.07:12:13.04#ibcon#about to read 3, iclass 14, count 2 2006.257.07:12:13.07#ibcon#read 3, iclass 14, count 2 2006.257.07:12:13.07#ibcon#about to read 4, iclass 14, count 2 2006.257.07:12:13.07#ibcon#read 4, iclass 14, count 2 2006.257.07:12:13.07#ibcon#about to read 5, iclass 14, count 2 2006.257.07:12:13.07#ibcon#read 5, iclass 14, count 2 2006.257.07:12:13.07#ibcon#about to read 6, iclass 14, count 2 2006.257.07:12:13.07#ibcon#read 6, iclass 14, count 2 2006.257.07:12:13.07#ibcon#end of sib2, iclass 14, count 2 2006.257.07:12:13.07#ibcon#*after write, iclass 14, count 2 2006.257.07:12:13.07#ibcon#*before return 0, iclass 14, count 2 2006.257.07:12:13.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:13.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:12:13.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.07:12:13.07#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:13.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:13.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:13.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:13.19#ibcon#enter wrdev, iclass 14, count 0 2006.257.07:12:13.19#ibcon#first serial, iclass 14, count 0 2006.257.07:12:13.19#ibcon#enter sib2, iclass 14, count 0 2006.257.07:12:13.19#ibcon#flushed, iclass 14, count 0 2006.257.07:12:13.19#ibcon#about to write, iclass 14, count 0 2006.257.07:12:13.19#ibcon#wrote, iclass 14, count 0 2006.257.07:12:13.19#ibcon#about to read 3, iclass 14, count 0 2006.257.07:12:13.21#ibcon#read 3, iclass 14, count 0 2006.257.07:12:13.21#ibcon#about to read 4, iclass 14, count 0 2006.257.07:12:13.21#ibcon#read 4, iclass 14, count 0 2006.257.07:12:13.21#ibcon#about to read 5, iclass 14, count 0 2006.257.07:12:13.21#ibcon#read 5, iclass 14, count 0 2006.257.07:12:13.21#ibcon#about to read 6, iclass 14, count 0 2006.257.07:12:13.21#ibcon#read 6, iclass 14, count 0 2006.257.07:12:13.21#ibcon#end of sib2, iclass 14, count 0 2006.257.07:12:13.21#ibcon#*mode == 0, iclass 14, count 0 2006.257.07:12:13.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.07:12:13.21#ibcon#[27=USB\r\n] 2006.257.07:12:13.21#ibcon#*before write, iclass 14, count 0 2006.257.07:12:13.21#ibcon#enter sib2, iclass 14, count 0 2006.257.07:12:13.21#ibcon#flushed, iclass 14, count 0 2006.257.07:12:13.21#ibcon#about to write, iclass 14, count 0 2006.257.07:12:13.21#ibcon#wrote, iclass 14, count 0 2006.257.07:12:13.21#ibcon#about to read 3, iclass 14, count 0 2006.257.07:12:13.24#ibcon#read 3, iclass 14, count 0 2006.257.07:12:13.24#ibcon#about to read 4, iclass 14, count 0 2006.257.07:12:13.24#ibcon#read 4, iclass 14, count 0 2006.257.07:12:13.24#ibcon#about to read 5, iclass 14, count 0 2006.257.07:12:13.24#ibcon#read 5, iclass 14, count 0 2006.257.07:12:13.24#ibcon#about to read 6, iclass 14, count 0 2006.257.07:12:13.24#ibcon#read 6, iclass 14, count 0 2006.257.07:12:13.24#ibcon#end of sib2, iclass 14, count 0 2006.257.07:12:13.24#ibcon#*after write, iclass 14, count 0 2006.257.07:12:13.24#ibcon#*before return 0, iclass 14, count 0 2006.257.07:12:13.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:13.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:12:13.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.07:12:13.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.07:12:13.24$vck44/vblo=5,709.99 2006.257.07:12:13.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.07:12:13.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.07:12:13.24#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:13.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:13.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:13.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:13.24#ibcon#enter wrdev, iclass 16, count 0 2006.257.07:12:13.24#ibcon#first serial, iclass 16, count 0 2006.257.07:12:13.24#ibcon#enter sib2, iclass 16, count 0 2006.257.07:12:13.24#ibcon#flushed, iclass 16, count 0 2006.257.07:12:13.24#ibcon#about to write, iclass 16, count 0 2006.257.07:12:13.24#ibcon#wrote, iclass 16, count 0 2006.257.07:12:13.24#ibcon#about to read 3, iclass 16, count 0 2006.257.07:12:13.26#ibcon#read 3, iclass 16, count 0 2006.257.07:12:13.26#ibcon#about to read 4, iclass 16, count 0 2006.257.07:12:13.26#ibcon#read 4, iclass 16, count 0 2006.257.07:12:13.26#ibcon#about to read 5, iclass 16, count 0 2006.257.07:12:13.26#ibcon#read 5, iclass 16, count 0 2006.257.07:12:13.26#ibcon#about to read 6, iclass 16, count 0 2006.257.07:12:13.26#ibcon#read 6, iclass 16, count 0 2006.257.07:12:13.26#ibcon#end of sib2, iclass 16, count 0 2006.257.07:12:13.26#ibcon#*mode == 0, iclass 16, count 0 2006.257.07:12:13.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.07:12:13.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.07:12:13.26#ibcon#*before write, iclass 16, count 0 2006.257.07:12:13.26#ibcon#enter sib2, iclass 16, count 0 2006.257.07:12:13.26#ibcon#flushed, iclass 16, count 0 2006.257.07:12:13.26#ibcon#about to write, iclass 16, count 0 2006.257.07:12:13.26#ibcon#wrote, iclass 16, count 0 2006.257.07:12:13.26#ibcon#about to read 3, iclass 16, count 0 2006.257.07:12:13.30#ibcon#read 3, iclass 16, count 0 2006.257.07:12:13.30#ibcon#about to read 4, iclass 16, count 0 2006.257.07:12:13.30#ibcon#read 4, iclass 16, count 0 2006.257.07:12:13.30#ibcon#about to read 5, iclass 16, count 0 2006.257.07:12:13.30#ibcon#read 5, iclass 16, count 0 2006.257.07:12:13.30#ibcon#about to read 6, iclass 16, count 0 2006.257.07:12:13.30#ibcon#read 6, iclass 16, count 0 2006.257.07:12:13.30#ibcon#end of sib2, iclass 16, count 0 2006.257.07:12:13.30#ibcon#*after write, iclass 16, count 0 2006.257.07:12:13.30#ibcon#*before return 0, iclass 16, count 0 2006.257.07:12:13.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:13.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:12:13.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.07:12:13.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.07:12:13.30$vck44/vb=5,4 2006.257.07:12:13.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.07:12:13.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.07:12:13.30#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:13.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:13.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:13.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:13.36#ibcon#enter wrdev, iclass 18, count 2 2006.257.07:12:13.36#ibcon#first serial, iclass 18, count 2 2006.257.07:12:13.36#ibcon#enter sib2, iclass 18, count 2 2006.257.07:12:13.36#ibcon#flushed, iclass 18, count 2 2006.257.07:12:13.36#ibcon#about to write, iclass 18, count 2 2006.257.07:12:13.36#ibcon#wrote, iclass 18, count 2 2006.257.07:12:13.36#ibcon#about to read 3, iclass 18, count 2 2006.257.07:12:13.38#ibcon#read 3, iclass 18, count 2 2006.257.07:12:13.38#ibcon#about to read 4, iclass 18, count 2 2006.257.07:12:13.38#ibcon#read 4, iclass 18, count 2 2006.257.07:12:13.38#ibcon#about to read 5, iclass 18, count 2 2006.257.07:12:13.38#ibcon#read 5, iclass 18, count 2 2006.257.07:12:13.38#ibcon#about to read 6, iclass 18, count 2 2006.257.07:12:13.38#ibcon#read 6, iclass 18, count 2 2006.257.07:12:13.38#ibcon#end of sib2, iclass 18, count 2 2006.257.07:12:13.38#ibcon#*mode == 0, iclass 18, count 2 2006.257.07:12:13.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.07:12:13.38#ibcon#[27=AT05-04\r\n] 2006.257.07:12:13.38#ibcon#*before write, iclass 18, count 2 2006.257.07:12:13.38#ibcon#enter sib2, iclass 18, count 2 2006.257.07:12:13.38#ibcon#flushed, iclass 18, count 2 2006.257.07:12:13.38#ibcon#about to write, iclass 18, count 2 2006.257.07:12:13.38#ibcon#wrote, iclass 18, count 2 2006.257.07:12:13.38#ibcon#about to read 3, iclass 18, count 2 2006.257.07:12:13.41#ibcon#read 3, iclass 18, count 2 2006.257.07:12:13.41#ibcon#about to read 4, iclass 18, count 2 2006.257.07:12:13.41#ibcon#read 4, iclass 18, count 2 2006.257.07:12:13.41#ibcon#about to read 5, iclass 18, count 2 2006.257.07:12:13.41#ibcon#read 5, iclass 18, count 2 2006.257.07:12:13.41#ibcon#about to read 6, iclass 18, count 2 2006.257.07:12:13.41#ibcon#read 6, iclass 18, count 2 2006.257.07:12:13.41#ibcon#end of sib2, iclass 18, count 2 2006.257.07:12:13.41#ibcon#*after write, iclass 18, count 2 2006.257.07:12:13.41#ibcon#*before return 0, iclass 18, count 2 2006.257.07:12:13.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:13.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:12:13.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.07:12:13.41#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:13.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:13.53#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:13.53#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:13.53#ibcon#enter wrdev, iclass 18, count 0 2006.257.07:12:13.53#ibcon#first serial, iclass 18, count 0 2006.257.07:12:13.53#ibcon#enter sib2, iclass 18, count 0 2006.257.07:12:13.53#ibcon#flushed, iclass 18, count 0 2006.257.07:12:13.53#ibcon#about to write, iclass 18, count 0 2006.257.07:12:13.53#ibcon#wrote, iclass 18, count 0 2006.257.07:12:13.53#ibcon#about to read 3, iclass 18, count 0 2006.257.07:12:13.55#ibcon#read 3, iclass 18, count 0 2006.257.07:12:13.55#ibcon#about to read 4, iclass 18, count 0 2006.257.07:12:13.55#ibcon#read 4, iclass 18, count 0 2006.257.07:12:13.55#ibcon#about to read 5, iclass 18, count 0 2006.257.07:12:13.55#ibcon#read 5, iclass 18, count 0 2006.257.07:12:13.55#ibcon#about to read 6, iclass 18, count 0 2006.257.07:12:13.55#ibcon#read 6, iclass 18, count 0 2006.257.07:12:13.55#ibcon#end of sib2, iclass 18, count 0 2006.257.07:12:13.55#ibcon#*mode == 0, iclass 18, count 0 2006.257.07:12:13.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.07:12:13.55#ibcon#[27=USB\r\n] 2006.257.07:12:13.55#ibcon#*before write, iclass 18, count 0 2006.257.07:12:13.55#ibcon#enter sib2, iclass 18, count 0 2006.257.07:12:13.55#ibcon#flushed, iclass 18, count 0 2006.257.07:12:13.55#ibcon#about to write, iclass 18, count 0 2006.257.07:12:13.55#ibcon#wrote, iclass 18, count 0 2006.257.07:12:13.55#ibcon#about to read 3, iclass 18, count 0 2006.257.07:12:13.58#ibcon#read 3, iclass 18, count 0 2006.257.07:12:13.58#ibcon#about to read 4, iclass 18, count 0 2006.257.07:12:13.58#ibcon#read 4, iclass 18, count 0 2006.257.07:12:13.58#ibcon#about to read 5, iclass 18, count 0 2006.257.07:12:13.58#ibcon#read 5, iclass 18, count 0 2006.257.07:12:13.58#ibcon#about to read 6, iclass 18, count 0 2006.257.07:12:13.58#ibcon#read 6, iclass 18, count 0 2006.257.07:12:13.58#ibcon#end of sib2, iclass 18, count 0 2006.257.07:12:13.58#ibcon#*after write, iclass 18, count 0 2006.257.07:12:13.58#ibcon#*before return 0, iclass 18, count 0 2006.257.07:12:13.58#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:13.58#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:12:13.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.07:12:13.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.07:12:13.58$vck44/vblo=6,719.99 2006.257.07:12:13.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.07:12:13.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.07:12:13.58#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:13.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:13.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:13.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:13.58#ibcon#enter wrdev, iclass 20, count 0 2006.257.07:12:13.58#ibcon#first serial, iclass 20, count 0 2006.257.07:12:13.58#ibcon#enter sib2, iclass 20, count 0 2006.257.07:12:13.58#ibcon#flushed, iclass 20, count 0 2006.257.07:12:13.58#ibcon#about to write, iclass 20, count 0 2006.257.07:12:13.58#ibcon#wrote, iclass 20, count 0 2006.257.07:12:13.58#ibcon#about to read 3, iclass 20, count 0 2006.257.07:12:13.60#ibcon#read 3, iclass 20, count 0 2006.257.07:12:13.60#ibcon#about to read 4, iclass 20, count 0 2006.257.07:12:13.60#ibcon#read 4, iclass 20, count 0 2006.257.07:12:13.60#ibcon#about to read 5, iclass 20, count 0 2006.257.07:12:13.60#ibcon#read 5, iclass 20, count 0 2006.257.07:12:13.60#ibcon#about to read 6, iclass 20, count 0 2006.257.07:12:13.60#ibcon#read 6, iclass 20, count 0 2006.257.07:12:13.60#ibcon#end of sib2, iclass 20, count 0 2006.257.07:12:13.60#ibcon#*mode == 0, iclass 20, count 0 2006.257.07:12:13.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.07:12:13.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.07:12:13.60#ibcon#*before write, iclass 20, count 0 2006.257.07:12:13.60#ibcon#enter sib2, iclass 20, count 0 2006.257.07:12:13.60#ibcon#flushed, iclass 20, count 0 2006.257.07:12:13.60#ibcon#about to write, iclass 20, count 0 2006.257.07:12:13.60#ibcon#wrote, iclass 20, count 0 2006.257.07:12:13.60#ibcon#about to read 3, iclass 20, count 0 2006.257.07:12:13.64#ibcon#read 3, iclass 20, count 0 2006.257.07:12:13.64#ibcon#about to read 4, iclass 20, count 0 2006.257.07:12:13.64#ibcon#read 4, iclass 20, count 0 2006.257.07:12:13.64#ibcon#about to read 5, iclass 20, count 0 2006.257.07:12:13.64#ibcon#read 5, iclass 20, count 0 2006.257.07:12:13.64#ibcon#about to read 6, iclass 20, count 0 2006.257.07:12:13.64#ibcon#read 6, iclass 20, count 0 2006.257.07:12:13.64#ibcon#end of sib2, iclass 20, count 0 2006.257.07:12:13.64#ibcon#*after write, iclass 20, count 0 2006.257.07:12:13.64#ibcon#*before return 0, iclass 20, count 0 2006.257.07:12:13.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:13.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:12:13.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.07:12:13.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.07:12:13.64$vck44/vb=6,4 2006.257.07:12:13.64#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.07:12:13.64#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.07:12:13.64#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:13.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:13.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:13.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:13.70#ibcon#enter wrdev, iclass 22, count 2 2006.257.07:12:13.70#ibcon#first serial, iclass 22, count 2 2006.257.07:12:13.70#ibcon#enter sib2, iclass 22, count 2 2006.257.07:12:13.70#ibcon#flushed, iclass 22, count 2 2006.257.07:12:13.70#ibcon#about to write, iclass 22, count 2 2006.257.07:12:13.70#ibcon#wrote, iclass 22, count 2 2006.257.07:12:13.70#ibcon#about to read 3, iclass 22, count 2 2006.257.07:12:13.72#ibcon#read 3, iclass 22, count 2 2006.257.07:12:13.72#ibcon#about to read 4, iclass 22, count 2 2006.257.07:12:13.72#ibcon#read 4, iclass 22, count 2 2006.257.07:12:13.72#ibcon#about to read 5, iclass 22, count 2 2006.257.07:12:13.72#ibcon#read 5, iclass 22, count 2 2006.257.07:12:13.72#ibcon#about to read 6, iclass 22, count 2 2006.257.07:12:13.72#ibcon#read 6, iclass 22, count 2 2006.257.07:12:13.72#ibcon#end of sib2, iclass 22, count 2 2006.257.07:12:13.72#ibcon#*mode == 0, iclass 22, count 2 2006.257.07:12:13.72#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.07:12:13.72#ibcon#[27=AT06-04\r\n] 2006.257.07:12:13.72#ibcon#*before write, iclass 22, count 2 2006.257.07:12:13.72#ibcon#enter sib2, iclass 22, count 2 2006.257.07:12:13.72#ibcon#flushed, iclass 22, count 2 2006.257.07:12:13.72#ibcon#about to write, iclass 22, count 2 2006.257.07:12:13.72#ibcon#wrote, iclass 22, count 2 2006.257.07:12:13.72#ibcon#about to read 3, iclass 22, count 2 2006.257.07:12:13.75#ibcon#read 3, iclass 22, count 2 2006.257.07:12:13.75#ibcon#about to read 4, iclass 22, count 2 2006.257.07:12:13.75#ibcon#read 4, iclass 22, count 2 2006.257.07:12:13.75#ibcon#about to read 5, iclass 22, count 2 2006.257.07:12:13.75#ibcon#read 5, iclass 22, count 2 2006.257.07:12:13.75#ibcon#about to read 6, iclass 22, count 2 2006.257.07:12:13.75#ibcon#read 6, iclass 22, count 2 2006.257.07:12:13.75#ibcon#end of sib2, iclass 22, count 2 2006.257.07:12:13.75#ibcon#*after write, iclass 22, count 2 2006.257.07:12:13.75#ibcon#*before return 0, iclass 22, count 2 2006.257.07:12:13.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:13.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:12:13.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.07:12:13.75#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:13.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:13.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:13.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:13.87#ibcon#enter wrdev, iclass 22, count 0 2006.257.07:12:13.87#ibcon#first serial, iclass 22, count 0 2006.257.07:12:13.87#ibcon#enter sib2, iclass 22, count 0 2006.257.07:12:13.87#ibcon#flushed, iclass 22, count 0 2006.257.07:12:13.87#ibcon#about to write, iclass 22, count 0 2006.257.07:12:13.87#ibcon#wrote, iclass 22, count 0 2006.257.07:12:13.87#ibcon#about to read 3, iclass 22, count 0 2006.257.07:12:13.89#ibcon#read 3, iclass 22, count 0 2006.257.07:12:13.89#ibcon#about to read 4, iclass 22, count 0 2006.257.07:12:13.89#ibcon#read 4, iclass 22, count 0 2006.257.07:12:13.89#ibcon#about to read 5, iclass 22, count 0 2006.257.07:12:13.89#ibcon#read 5, iclass 22, count 0 2006.257.07:12:13.89#ibcon#about to read 6, iclass 22, count 0 2006.257.07:12:13.89#ibcon#read 6, iclass 22, count 0 2006.257.07:12:13.89#ibcon#end of sib2, iclass 22, count 0 2006.257.07:12:13.89#ibcon#*mode == 0, iclass 22, count 0 2006.257.07:12:13.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.07:12:13.89#ibcon#[27=USB\r\n] 2006.257.07:12:13.89#ibcon#*before write, iclass 22, count 0 2006.257.07:12:13.89#ibcon#enter sib2, iclass 22, count 0 2006.257.07:12:13.89#ibcon#flushed, iclass 22, count 0 2006.257.07:12:13.89#ibcon#about to write, iclass 22, count 0 2006.257.07:12:13.89#ibcon#wrote, iclass 22, count 0 2006.257.07:12:13.89#ibcon#about to read 3, iclass 22, count 0 2006.257.07:12:13.92#ibcon#read 3, iclass 22, count 0 2006.257.07:12:13.92#ibcon#about to read 4, iclass 22, count 0 2006.257.07:12:13.92#ibcon#read 4, iclass 22, count 0 2006.257.07:12:13.92#ibcon#about to read 5, iclass 22, count 0 2006.257.07:12:13.92#ibcon#read 5, iclass 22, count 0 2006.257.07:12:13.92#ibcon#about to read 6, iclass 22, count 0 2006.257.07:12:13.92#ibcon#read 6, iclass 22, count 0 2006.257.07:12:13.92#ibcon#end of sib2, iclass 22, count 0 2006.257.07:12:13.92#ibcon#*after write, iclass 22, count 0 2006.257.07:12:13.92#ibcon#*before return 0, iclass 22, count 0 2006.257.07:12:13.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:13.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:12:13.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.07:12:13.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.07:12:13.92$vck44/vblo=7,734.99 2006.257.07:12:13.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.07:12:13.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.07:12:13.92#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:13.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:13.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:13.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:13.92#ibcon#enter wrdev, iclass 24, count 0 2006.257.07:12:13.92#ibcon#first serial, iclass 24, count 0 2006.257.07:12:13.92#ibcon#enter sib2, iclass 24, count 0 2006.257.07:12:13.92#ibcon#flushed, iclass 24, count 0 2006.257.07:12:13.92#ibcon#about to write, iclass 24, count 0 2006.257.07:12:13.92#ibcon#wrote, iclass 24, count 0 2006.257.07:12:13.92#ibcon#about to read 3, iclass 24, count 0 2006.257.07:12:13.94#ibcon#read 3, iclass 24, count 0 2006.257.07:12:13.94#ibcon#about to read 4, iclass 24, count 0 2006.257.07:12:13.94#ibcon#read 4, iclass 24, count 0 2006.257.07:12:13.94#ibcon#about to read 5, iclass 24, count 0 2006.257.07:12:13.94#ibcon#read 5, iclass 24, count 0 2006.257.07:12:13.94#ibcon#about to read 6, iclass 24, count 0 2006.257.07:12:13.94#ibcon#read 6, iclass 24, count 0 2006.257.07:12:13.94#ibcon#end of sib2, iclass 24, count 0 2006.257.07:12:13.94#ibcon#*mode == 0, iclass 24, count 0 2006.257.07:12:13.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.07:12:13.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.07:12:13.94#ibcon#*before write, iclass 24, count 0 2006.257.07:12:13.94#ibcon#enter sib2, iclass 24, count 0 2006.257.07:12:13.94#ibcon#flushed, iclass 24, count 0 2006.257.07:12:13.94#ibcon#about to write, iclass 24, count 0 2006.257.07:12:13.94#ibcon#wrote, iclass 24, count 0 2006.257.07:12:13.94#ibcon#about to read 3, iclass 24, count 0 2006.257.07:12:13.98#ibcon#read 3, iclass 24, count 0 2006.257.07:12:13.98#ibcon#about to read 4, iclass 24, count 0 2006.257.07:12:13.98#ibcon#read 4, iclass 24, count 0 2006.257.07:12:13.98#ibcon#about to read 5, iclass 24, count 0 2006.257.07:12:13.98#ibcon#read 5, iclass 24, count 0 2006.257.07:12:13.98#ibcon#about to read 6, iclass 24, count 0 2006.257.07:12:13.98#ibcon#read 6, iclass 24, count 0 2006.257.07:12:13.98#ibcon#end of sib2, iclass 24, count 0 2006.257.07:12:13.98#ibcon#*after write, iclass 24, count 0 2006.257.07:12:13.98#ibcon#*before return 0, iclass 24, count 0 2006.257.07:12:13.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:13.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:12:13.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.07:12:13.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.07:12:13.98$vck44/vb=7,4 2006.257.07:12:13.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.07:12:13.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.07:12:13.98#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:13.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:14.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:14.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:14.04#ibcon#enter wrdev, iclass 26, count 2 2006.257.07:12:14.04#ibcon#first serial, iclass 26, count 2 2006.257.07:12:14.04#ibcon#enter sib2, iclass 26, count 2 2006.257.07:12:14.04#ibcon#flushed, iclass 26, count 2 2006.257.07:12:14.04#ibcon#about to write, iclass 26, count 2 2006.257.07:12:14.04#ibcon#wrote, iclass 26, count 2 2006.257.07:12:14.04#ibcon#about to read 3, iclass 26, count 2 2006.257.07:12:14.06#ibcon#read 3, iclass 26, count 2 2006.257.07:12:14.06#ibcon#about to read 4, iclass 26, count 2 2006.257.07:12:14.06#ibcon#read 4, iclass 26, count 2 2006.257.07:12:14.06#ibcon#about to read 5, iclass 26, count 2 2006.257.07:12:14.06#ibcon#read 5, iclass 26, count 2 2006.257.07:12:14.06#ibcon#about to read 6, iclass 26, count 2 2006.257.07:12:14.06#ibcon#read 6, iclass 26, count 2 2006.257.07:12:14.06#ibcon#end of sib2, iclass 26, count 2 2006.257.07:12:14.06#ibcon#*mode == 0, iclass 26, count 2 2006.257.07:12:14.06#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.07:12:14.06#ibcon#[27=AT07-04\r\n] 2006.257.07:12:14.06#ibcon#*before write, iclass 26, count 2 2006.257.07:12:14.06#ibcon#enter sib2, iclass 26, count 2 2006.257.07:12:14.06#ibcon#flushed, iclass 26, count 2 2006.257.07:12:14.06#ibcon#about to write, iclass 26, count 2 2006.257.07:12:14.06#ibcon#wrote, iclass 26, count 2 2006.257.07:12:14.06#ibcon#about to read 3, iclass 26, count 2 2006.257.07:12:14.09#ibcon#read 3, iclass 26, count 2 2006.257.07:12:14.09#ibcon#about to read 4, iclass 26, count 2 2006.257.07:12:14.09#ibcon#read 4, iclass 26, count 2 2006.257.07:12:14.09#ibcon#about to read 5, iclass 26, count 2 2006.257.07:12:14.09#ibcon#read 5, iclass 26, count 2 2006.257.07:12:14.09#ibcon#about to read 6, iclass 26, count 2 2006.257.07:12:14.09#ibcon#read 6, iclass 26, count 2 2006.257.07:12:14.09#ibcon#end of sib2, iclass 26, count 2 2006.257.07:12:14.09#ibcon#*after write, iclass 26, count 2 2006.257.07:12:14.09#ibcon#*before return 0, iclass 26, count 2 2006.257.07:12:14.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:14.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:12:14.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.07:12:14.09#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:14.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:14.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:14.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:14.21#ibcon#enter wrdev, iclass 26, count 0 2006.257.07:12:14.21#ibcon#first serial, iclass 26, count 0 2006.257.07:12:14.21#ibcon#enter sib2, iclass 26, count 0 2006.257.07:12:14.21#ibcon#flushed, iclass 26, count 0 2006.257.07:12:14.21#ibcon#about to write, iclass 26, count 0 2006.257.07:12:14.21#ibcon#wrote, iclass 26, count 0 2006.257.07:12:14.21#ibcon#about to read 3, iclass 26, count 0 2006.257.07:12:14.23#ibcon#read 3, iclass 26, count 0 2006.257.07:12:14.23#ibcon#about to read 4, iclass 26, count 0 2006.257.07:12:14.23#ibcon#read 4, iclass 26, count 0 2006.257.07:12:14.23#ibcon#about to read 5, iclass 26, count 0 2006.257.07:12:14.23#ibcon#read 5, iclass 26, count 0 2006.257.07:12:14.23#ibcon#about to read 6, iclass 26, count 0 2006.257.07:12:14.23#ibcon#read 6, iclass 26, count 0 2006.257.07:12:14.23#ibcon#end of sib2, iclass 26, count 0 2006.257.07:12:14.23#ibcon#*mode == 0, iclass 26, count 0 2006.257.07:12:14.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.07:12:14.23#ibcon#[27=USB\r\n] 2006.257.07:12:14.23#ibcon#*before write, iclass 26, count 0 2006.257.07:12:14.23#ibcon#enter sib2, iclass 26, count 0 2006.257.07:12:14.23#ibcon#flushed, iclass 26, count 0 2006.257.07:12:14.23#ibcon#about to write, iclass 26, count 0 2006.257.07:12:14.23#ibcon#wrote, iclass 26, count 0 2006.257.07:12:14.23#ibcon#about to read 3, iclass 26, count 0 2006.257.07:12:14.26#ibcon#read 3, iclass 26, count 0 2006.257.07:12:14.26#ibcon#about to read 4, iclass 26, count 0 2006.257.07:12:14.26#ibcon#read 4, iclass 26, count 0 2006.257.07:12:14.26#ibcon#about to read 5, iclass 26, count 0 2006.257.07:12:14.26#ibcon#read 5, iclass 26, count 0 2006.257.07:12:14.26#ibcon#about to read 6, iclass 26, count 0 2006.257.07:12:14.26#ibcon#read 6, iclass 26, count 0 2006.257.07:12:14.26#ibcon#end of sib2, iclass 26, count 0 2006.257.07:12:14.26#ibcon#*after write, iclass 26, count 0 2006.257.07:12:14.26#ibcon#*before return 0, iclass 26, count 0 2006.257.07:12:14.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:14.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:12:14.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.07:12:14.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.07:12:14.26$vck44/vblo=8,744.99 2006.257.07:12:14.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.07:12:14.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.07:12:14.26#ibcon#ireg 17 cls_cnt 0 2006.257.07:12:14.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:14.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:14.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:14.26#ibcon#enter wrdev, iclass 28, count 0 2006.257.07:12:14.26#ibcon#first serial, iclass 28, count 0 2006.257.07:12:14.26#ibcon#enter sib2, iclass 28, count 0 2006.257.07:12:14.26#ibcon#flushed, iclass 28, count 0 2006.257.07:12:14.26#ibcon#about to write, iclass 28, count 0 2006.257.07:12:14.26#ibcon#wrote, iclass 28, count 0 2006.257.07:12:14.26#ibcon#about to read 3, iclass 28, count 0 2006.257.07:12:14.28#ibcon#read 3, iclass 28, count 0 2006.257.07:12:14.28#ibcon#about to read 4, iclass 28, count 0 2006.257.07:12:14.28#ibcon#read 4, iclass 28, count 0 2006.257.07:12:14.28#ibcon#about to read 5, iclass 28, count 0 2006.257.07:12:14.28#ibcon#read 5, iclass 28, count 0 2006.257.07:12:14.28#ibcon#about to read 6, iclass 28, count 0 2006.257.07:12:14.28#ibcon#read 6, iclass 28, count 0 2006.257.07:12:14.28#ibcon#end of sib2, iclass 28, count 0 2006.257.07:12:14.28#ibcon#*mode == 0, iclass 28, count 0 2006.257.07:12:14.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.07:12:14.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.07:12:14.28#ibcon#*before write, iclass 28, count 0 2006.257.07:12:14.28#ibcon#enter sib2, iclass 28, count 0 2006.257.07:12:14.28#ibcon#flushed, iclass 28, count 0 2006.257.07:12:14.28#ibcon#about to write, iclass 28, count 0 2006.257.07:12:14.28#ibcon#wrote, iclass 28, count 0 2006.257.07:12:14.28#ibcon#about to read 3, iclass 28, count 0 2006.257.07:12:14.32#ibcon#read 3, iclass 28, count 0 2006.257.07:12:14.32#ibcon#about to read 4, iclass 28, count 0 2006.257.07:12:14.32#ibcon#read 4, iclass 28, count 0 2006.257.07:12:14.32#ibcon#about to read 5, iclass 28, count 0 2006.257.07:12:14.32#ibcon#read 5, iclass 28, count 0 2006.257.07:12:14.32#ibcon#about to read 6, iclass 28, count 0 2006.257.07:12:14.32#ibcon#read 6, iclass 28, count 0 2006.257.07:12:14.32#ibcon#end of sib2, iclass 28, count 0 2006.257.07:12:14.32#ibcon#*after write, iclass 28, count 0 2006.257.07:12:14.32#ibcon#*before return 0, iclass 28, count 0 2006.257.07:12:14.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:14.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:12:14.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.07:12:14.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.07:12:14.32$vck44/vb=8,4 2006.257.07:12:14.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.07:12:14.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.07:12:14.32#ibcon#ireg 11 cls_cnt 2 2006.257.07:12:14.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:14.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:14.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:14.38#ibcon#enter wrdev, iclass 30, count 2 2006.257.07:12:14.38#ibcon#first serial, iclass 30, count 2 2006.257.07:12:14.38#ibcon#enter sib2, iclass 30, count 2 2006.257.07:12:14.38#ibcon#flushed, iclass 30, count 2 2006.257.07:12:14.38#ibcon#about to write, iclass 30, count 2 2006.257.07:12:14.38#ibcon#wrote, iclass 30, count 2 2006.257.07:12:14.38#ibcon#about to read 3, iclass 30, count 2 2006.257.07:12:14.40#ibcon#read 3, iclass 30, count 2 2006.257.07:12:14.40#ibcon#about to read 4, iclass 30, count 2 2006.257.07:12:14.40#ibcon#read 4, iclass 30, count 2 2006.257.07:12:14.40#ibcon#about to read 5, iclass 30, count 2 2006.257.07:12:14.40#ibcon#read 5, iclass 30, count 2 2006.257.07:12:14.40#ibcon#about to read 6, iclass 30, count 2 2006.257.07:12:14.40#ibcon#read 6, iclass 30, count 2 2006.257.07:12:14.40#ibcon#end of sib2, iclass 30, count 2 2006.257.07:12:14.40#ibcon#*mode == 0, iclass 30, count 2 2006.257.07:12:14.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.07:12:14.40#ibcon#[27=AT08-04\r\n] 2006.257.07:12:14.40#ibcon#*before write, iclass 30, count 2 2006.257.07:12:14.40#ibcon#enter sib2, iclass 30, count 2 2006.257.07:12:14.40#ibcon#flushed, iclass 30, count 2 2006.257.07:12:14.40#ibcon#about to write, iclass 30, count 2 2006.257.07:12:14.40#ibcon#wrote, iclass 30, count 2 2006.257.07:12:14.40#ibcon#about to read 3, iclass 30, count 2 2006.257.07:12:14.43#ibcon#read 3, iclass 30, count 2 2006.257.07:12:14.43#ibcon#about to read 4, iclass 30, count 2 2006.257.07:12:14.43#ibcon#read 4, iclass 30, count 2 2006.257.07:12:14.43#ibcon#about to read 5, iclass 30, count 2 2006.257.07:12:14.43#ibcon#read 5, iclass 30, count 2 2006.257.07:12:14.43#ibcon#about to read 6, iclass 30, count 2 2006.257.07:12:14.43#ibcon#read 6, iclass 30, count 2 2006.257.07:12:14.43#ibcon#end of sib2, iclass 30, count 2 2006.257.07:12:14.43#ibcon#*after write, iclass 30, count 2 2006.257.07:12:14.43#ibcon#*before return 0, iclass 30, count 2 2006.257.07:12:14.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:14.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:12:14.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.07:12:14.43#ibcon#ireg 7 cls_cnt 0 2006.257.07:12:14.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:14.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:14.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:14.55#ibcon#enter wrdev, iclass 30, count 0 2006.257.07:12:14.55#ibcon#first serial, iclass 30, count 0 2006.257.07:12:14.55#ibcon#enter sib2, iclass 30, count 0 2006.257.07:12:14.55#ibcon#flushed, iclass 30, count 0 2006.257.07:12:14.55#ibcon#about to write, iclass 30, count 0 2006.257.07:12:14.55#ibcon#wrote, iclass 30, count 0 2006.257.07:12:14.55#ibcon#about to read 3, iclass 30, count 0 2006.257.07:12:14.57#ibcon#read 3, iclass 30, count 0 2006.257.07:12:14.57#ibcon#about to read 4, iclass 30, count 0 2006.257.07:12:14.57#ibcon#read 4, iclass 30, count 0 2006.257.07:12:14.57#ibcon#about to read 5, iclass 30, count 0 2006.257.07:12:14.57#ibcon#read 5, iclass 30, count 0 2006.257.07:12:14.57#ibcon#about to read 6, iclass 30, count 0 2006.257.07:12:14.57#ibcon#read 6, iclass 30, count 0 2006.257.07:12:14.57#ibcon#end of sib2, iclass 30, count 0 2006.257.07:12:14.57#ibcon#*mode == 0, iclass 30, count 0 2006.257.07:12:14.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.07:12:14.57#ibcon#[27=USB\r\n] 2006.257.07:12:14.57#ibcon#*before write, iclass 30, count 0 2006.257.07:12:14.57#ibcon#enter sib2, iclass 30, count 0 2006.257.07:12:14.57#ibcon#flushed, iclass 30, count 0 2006.257.07:12:14.57#ibcon#about to write, iclass 30, count 0 2006.257.07:12:14.57#ibcon#wrote, iclass 30, count 0 2006.257.07:12:14.57#ibcon#about to read 3, iclass 30, count 0 2006.257.07:12:14.60#ibcon#read 3, iclass 30, count 0 2006.257.07:12:14.60#ibcon#about to read 4, iclass 30, count 0 2006.257.07:12:14.60#ibcon#read 4, iclass 30, count 0 2006.257.07:12:14.60#ibcon#about to read 5, iclass 30, count 0 2006.257.07:12:14.60#ibcon#read 5, iclass 30, count 0 2006.257.07:12:14.60#ibcon#about to read 6, iclass 30, count 0 2006.257.07:12:14.60#ibcon#read 6, iclass 30, count 0 2006.257.07:12:14.60#ibcon#end of sib2, iclass 30, count 0 2006.257.07:12:14.60#ibcon#*after write, iclass 30, count 0 2006.257.07:12:14.60#ibcon#*before return 0, iclass 30, count 0 2006.257.07:12:14.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:14.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:12:14.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.07:12:14.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.07:12:14.60$vck44/vabw=wide 2006.257.07:12:14.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.07:12:14.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.07:12:14.60#ibcon#ireg 8 cls_cnt 0 2006.257.07:12:14.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:14.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:14.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:14.60#ibcon#enter wrdev, iclass 32, count 0 2006.257.07:12:14.60#ibcon#first serial, iclass 32, count 0 2006.257.07:12:14.60#ibcon#enter sib2, iclass 32, count 0 2006.257.07:12:14.60#ibcon#flushed, iclass 32, count 0 2006.257.07:12:14.60#ibcon#about to write, iclass 32, count 0 2006.257.07:12:14.60#ibcon#wrote, iclass 32, count 0 2006.257.07:12:14.60#ibcon#about to read 3, iclass 32, count 0 2006.257.07:12:14.62#ibcon#read 3, iclass 32, count 0 2006.257.07:12:14.62#ibcon#about to read 4, iclass 32, count 0 2006.257.07:12:14.62#ibcon#read 4, iclass 32, count 0 2006.257.07:12:14.62#ibcon#about to read 5, iclass 32, count 0 2006.257.07:12:14.62#ibcon#read 5, iclass 32, count 0 2006.257.07:12:14.62#ibcon#about to read 6, iclass 32, count 0 2006.257.07:12:14.62#ibcon#read 6, iclass 32, count 0 2006.257.07:12:14.62#ibcon#end of sib2, iclass 32, count 0 2006.257.07:12:14.62#ibcon#*mode == 0, iclass 32, count 0 2006.257.07:12:14.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.07:12:14.62#ibcon#[25=BW32\r\n] 2006.257.07:12:14.62#ibcon#*before write, iclass 32, count 0 2006.257.07:12:14.62#ibcon#enter sib2, iclass 32, count 0 2006.257.07:12:14.62#ibcon#flushed, iclass 32, count 0 2006.257.07:12:14.62#ibcon#about to write, iclass 32, count 0 2006.257.07:12:14.62#ibcon#wrote, iclass 32, count 0 2006.257.07:12:14.62#ibcon#about to read 3, iclass 32, count 0 2006.257.07:12:14.65#ibcon#read 3, iclass 32, count 0 2006.257.07:12:14.65#ibcon#about to read 4, iclass 32, count 0 2006.257.07:12:14.65#ibcon#read 4, iclass 32, count 0 2006.257.07:12:14.65#ibcon#about to read 5, iclass 32, count 0 2006.257.07:12:14.65#ibcon#read 5, iclass 32, count 0 2006.257.07:12:14.65#ibcon#about to read 6, iclass 32, count 0 2006.257.07:12:14.65#ibcon#read 6, iclass 32, count 0 2006.257.07:12:14.65#ibcon#end of sib2, iclass 32, count 0 2006.257.07:12:14.65#ibcon#*after write, iclass 32, count 0 2006.257.07:12:14.65#ibcon#*before return 0, iclass 32, count 0 2006.257.07:12:14.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:14.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:12:14.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.07:12:14.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.07:12:14.65$vck44/vbbw=wide 2006.257.07:12:14.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.07:12:14.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.07:12:14.65#ibcon#ireg 8 cls_cnt 0 2006.257.07:12:14.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:12:14.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:12:14.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:12:14.72#ibcon#enter wrdev, iclass 34, count 0 2006.257.07:12:14.72#ibcon#first serial, iclass 34, count 0 2006.257.07:12:14.72#ibcon#enter sib2, iclass 34, count 0 2006.257.07:12:14.72#ibcon#flushed, iclass 34, count 0 2006.257.07:12:14.72#ibcon#about to write, iclass 34, count 0 2006.257.07:12:14.72#ibcon#wrote, iclass 34, count 0 2006.257.07:12:14.72#ibcon#about to read 3, iclass 34, count 0 2006.257.07:12:14.74#ibcon#read 3, iclass 34, count 0 2006.257.07:12:14.74#ibcon#about to read 4, iclass 34, count 0 2006.257.07:12:14.74#ibcon#read 4, iclass 34, count 0 2006.257.07:12:14.74#ibcon#about to read 5, iclass 34, count 0 2006.257.07:12:14.74#ibcon#read 5, iclass 34, count 0 2006.257.07:12:14.74#ibcon#about to read 6, iclass 34, count 0 2006.257.07:12:14.74#ibcon#read 6, iclass 34, count 0 2006.257.07:12:14.74#ibcon#end of sib2, iclass 34, count 0 2006.257.07:12:14.74#ibcon#*mode == 0, iclass 34, count 0 2006.257.07:12:14.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.07:12:14.74#ibcon#[27=BW32\r\n] 2006.257.07:12:14.74#ibcon#*before write, iclass 34, count 0 2006.257.07:12:14.74#ibcon#enter sib2, iclass 34, count 0 2006.257.07:12:14.74#ibcon#flushed, iclass 34, count 0 2006.257.07:12:14.74#ibcon#about to write, iclass 34, count 0 2006.257.07:12:14.74#ibcon#wrote, iclass 34, count 0 2006.257.07:12:14.74#ibcon#about to read 3, iclass 34, count 0 2006.257.07:12:14.77#ibcon#read 3, iclass 34, count 0 2006.257.07:12:14.77#ibcon#about to read 4, iclass 34, count 0 2006.257.07:12:14.77#ibcon#read 4, iclass 34, count 0 2006.257.07:12:14.77#ibcon#about to read 5, iclass 34, count 0 2006.257.07:12:14.77#ibcon#read 5, iclass 34, count 0 2006.257.07:12:14.77#ibcon#about to read 6, iclass 34, count 0 2006.257.07:12:14.77#ibcon#read 6, iclass 34, count 0 2006.257.07:12:14.77#ibcon#end of sib2, iclass 34, count 0 2006.257.07:12:14.77#ibcon#*after write, iclass 34, count 0 2006.257.07:12:14.77#ibcon#*before return 0, iclass 34, count 0 2006.257.07:12:14.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:12:14.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:12:14.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.07:12:14.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.07:12:14.77$setupk4/ifdk4 2006.257.07:12:14.77$ifdk4/lo= 2006.257.07:12:14.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.07:12:14.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.07:12:14.77$ifdk4/patch= 2006.257.07:12:14.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.07:12:14.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.07:12:14.77$setupk4/!*+20s 2006.257.07:12:15.54#abcon#<5=/16 1.2 3.3 21.21 871012.2\r\n> 2006.257.07:12:15.56#abcon#{5=INTERFACE CLEAR} 2006.257.07:12:15.62#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:12:25.71#abcon#<5=/16 1.2 3.3 21.22 871012.2\r\n> 2006.257.07:12:25.73#abcon#{5=INTERFACE CLEAR} 2006.257.07:12:25.79#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:12:29.28$setupk4/"tpicd 2006.257.07:12:29.28$setupk4/echo=off 2006.257.07:12:29.28$setupk4/xlog=off 2006.257.07:12:29.28:!2006.257.07:15:36 2006.257.07:12:50.14#trakl#Source acquired 2006.257.07:12:50.14#flagr#flagr/antenna,acquired 2006.257.07:15:36.02:preob 2006.257.07:15:37.14/onsource/TRACKING 2006.257.07:15:37.14:!2006.257.07:15:46 2006.257.07:15:46.02:"tape 2006.257.07:15:46.02:"st=record 2006.257.07:15:46.02:data_valid=on 2006.257.07:15:46.02:midob 2006.257.07:15:47.14/onsource/TRACKING 2006.257.07:15:47.14/wx/21.30,1012.2,85 2006.257.07:15:47.18/cable/+6.4781E-03 2006.257.07:15:48.27/va/01,08,usb,yes,31,34 2006.257.07:15:48.27/va/02,07,usb,yes,34,34 2006.257.07:15:48.27/va/03,08,usb,yes,31,32 2006.257.07:15:48.27/va/04,07,usb,yes,35,37 2006.257.07:15:48.27/va/05,04,usb,yes,32,32 2006.257.07:15:48.27/va/06,04,usb,yes,35,35 2006.257.07:15:48.27/va/07,04,usb,yes,36,36 2006.257.07:15:48.27/va/08,04,usb,yes,30,37 2006.257.07:15:48.50/valo/01,524.99,yes,locked 2006.257.07:15:48.50/valo/02,534.99,yes,locked 2006.257.07:15:48.50/valo/03,564.99,yes,locked 2006.257.07:15:48.50/valo/04,624.99,yes,locked 2006.257.07:15:48.50/valo/05,734.99,yes,locked 2006.257.07:15:48.50/valo/06,814.99,yes,locked 2006.257.07:15:48.50/valo/07,864.99,yes,locked 2006.257.07:15:48.50/valo/08,884.99,yes,locked 2006.257.07:15:49.59/vb/01,04,usb,yes,31,29 2006.257.07:15:49.59/vb/02,05,usb,yes,29,29 2006.257.07:15:49.59/vb/03,04,usb,yes,30,33 2006.257.07:15:49.59/vb/04,05,usb,yes,31,30 2006.257.07:15:49.59/vb/05,04,usb,yes,27,30 2006.257.07:15:49.59/vb/06,04,usb,yes,32,28 2006.257.07:15:49.59/vb/07,04,usb,yes,31,31 2006.257.07:15:49.59/vb/08,04,usb,yes,29,32 2006.257.07:15:49.82/vblo/01,629.99,yes,locked 2006.257.07:15:49.82/vblo/02,634.99,yes,locked 2006.257.07:15:49.82/vblo/03,649.99,yes,locked 2006.257.07:15:49.82/vblo/04,679.99,yes,locked 2006.257.07:15:49.82/vblo/05,709.99,yes,locked 2006.257.07:15:49.82/vblo/06,719.99,yes,locked 2006.257.07:15:49.82/vblo/07,734.99,yes,locked 2006.257.07:15:49.82/vblo/08,744.99,yes,locked 2006.257.07:15:49.97/vabw/8 2006.257.07:15:50.12/vbbw/8 2006.257.07:15:50.28/xfe/off,on,16.7 2006.257.07:15:50.65/ifatt/23,28,28,28 2006.257.07:15:51.07/fmout-gps/S +4.53E-07 2006.257.07:15:51.11:!2006.257.07:19:36 2006.257.07:19:36.01:data_valid=off 2006.257.07:19:36.02:"et 2006.257.07:19:36.02:!+3s 2006.257.07:19:39.04:"tape 2006.257.07:19:39.05:postob 2006.257.07:19:39.12/cable/+6.4781E-03 2006.257.07:19:39.13/wx/21.37,1012.2,85 2006.257.07:19:39.18/fmout-gps/S +4.52E-07 2006.257.07:19:39.18:scan_name=257-0722,jd0609,280 2006.257.07:19:39.18:source=1622-253,162546.89,-252738.3,2000.0,cw 2006.257.07:19:41.14#flagr#flagr/antenna,new-source 2006.257.07:19:41.15:checkk5 2006.257.07:19:41.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.07:19:41.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.07:19:42.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.07:19:42.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.07:19:43.17/chk_obsdata//k5ts1/T2570715??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.257.07:19:43.56/chk_obsdata//k5ts2/T2570715??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.257.07:19:43.97/chk_obsdata//k5ts3/T2570715??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.257.07:19:44.36/chk_obsdata//k5ts4/T2570715??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.257.07:19:45.09/k5log//k5ts1_log_newline 2006.257.07:19:45.82/k5log//k5ts2_log_newline 2006.257.07:19:46.55/k5log//k5ts3_log_newline 2006.257.07:19:47.27/k5log//k5ts4_log_newline 2006.257.07:19:47.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.07:19:47.29:setupk4=1 2006.257.07:19:47.29$setupk4/echo=on 2006.257.07:19:47.29$setupk4/pcalon 2006.257.07:19:47.29$pcalon/"no phase cal control is implemented here 2006.257.07:19:47.29$setupk4/"tpicd=stop 2006.257.07:19:47.29$setupk4/"rec=synch_on 2006.257.07:19:47.29$setupk4/"rec_mode=128 2006.257.07:19:47.29$setupk4/!* 2006.257.07:19:47.29$setupk4/recpk4 2006.257.07:19:47.29$recpk4/recpatch= 2006.257.07:19:47.30$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.07:19:47.30$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.07:19:47.30$setupk4/vck44 2006.257.07:19:47.30$vck44/valo=1,524.99 2006.257.07:19:47.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.07:19:47.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.07:19:47.30#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:47.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:47.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:47.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:47.30#ibcon#enter wrdev, iclass 39, count 0 2006.257.07:19:47.30#ibcon#first serial, iclass 39, count 0 2006.257.07:19:47.30#ibcon#enter sib2, iclass 39, count 0 2006.257.07:19:47.30#ibcon#flushed, iclass 39, count 0 2006.257.07:19:47.30#ibcon#about to write, iclass 39, count 0 2006.257.07:19:47.30#ibcon#wrote, iclass 39, count 0 2006.257.07:19:47.30#ibcon#about to read 3, iclass 39, count 0 2006.257.07:19:47.31#ibcon#read 3, iclass 39, count 0 2006.257.07:19:47.31#ibcon#about to read 4, iclass 39, count 0 2006.257.07:19:47.31#ibcon#read 4, iclass 39, count 0 2006.257.07:19:47.31#ibcon#about to read 5, iclass 39, count 0 2006.257.07:19:47.31#ibcon#read 5, iclass 39, count 0 2006.257.07:19:47.31#ibcon#about to read 6, iclass 39, count 0 2006.257.07:19:47.31#ibcon#read 6, iclass 39, count 0 2006.257.07:19:47.31#ibcon#end of sib2, iclass 39, count 0 2006.257.07:19:47.31#ibcon#*mode == 0, iclass 39, count 0 2006.257.07:19:47.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.07:19:47.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.07:19:47.31#ibcon#*before write, iclass 39, count 0 2006.257.07:19:47.31#ibcon#enter sib2, iclass 39, count 0 2006.257.07:19:47.31#ibcon#flushed, iclass 39, count 0 2006.257.07:19:47.31#ibcon#about to write, iclass 39, count 0 2006.257.07:19:47.31#ibcon#wrote, iclass 39, count 0 2006.257.07:19:47.31#ibcon#about to read 3, iclass 39, count 0 2006.257.07:19:47.36#ibcon#read 3, iclass 39, count 0 2006.257.07:19:47.36#ibcon#about to read 4, iclass 39, count 0 2006.257.07:19:47.36#ibcon#read 4, iclass 39, count 0 2006.257.07:19:47.36#ibcon#about to read 5, iclass 39, count 0 2006.257.07:19:47.36#ibcon#read 5, iclass 39, count 0 2006.257.07:19:47.36#ibcon#about to read 6, iclass 39, count 0 2006.257.07:19:47.36#ibcon#read 6, iclass 39, count 0 2006.257.07:19:47.36#ibcon#end of sib2, iclass 39, count 0 2006.257.07:19:47.36#ibcon#*after write, iclass 39, count 0 2006.257.07:19:47.36#ibcon#*before return 0, iclass 39, count 0 2006.257.07:19:47.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:47.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:47.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.07:19:47.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.07:19:47.36$vck44/va=1,8 2006.257.07:19:47.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.07:19:47.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.07:19:47.36#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:47.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:47.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:47.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:47.36#ibcon#enter wrdev, iclass 3, count 2 2006.257.07:19:47.36#ibcon#first serial, iclass 3, count 2 2006.257.07:19:47.36#ibcon#enter sib2, iclass 3, count 2 2006.257.07:19:47.36#ibcon#flushed, iclass 3, count 2 2006.257.07:19:47.36#ibcon#about to write, iclass 3, count 2 2006.257.07:19:47.36#ibcon#wrote, iclass 3, count 2 2006.257.07:19:47.36#ibcon#about to read 3, iclass 3, count 2 2006.257.07:19:47.38#ibcon#read 3, iclass 3, count 2 2006.257.07:19:47.38#ibcon#about to read 4, iclass 3, count 2 2006.257.07:19:47.38#ibcon#read 4, iclass 3, count 2 2006.257.07:19:47.38#ibcon#about to read 5, iclass 3, count 2 2006.257.07:19:47.38#ibcon#read 5, iclass 3, count 2 2006.257.07:19:47.38#ibcon#about to read 6, iclass 3, count 2 2006.257.07:19:47.38#ibcon#read 6, iclass 3, count 2 2006.257.07:19:47.38#ibcon#end of sib2, iclass 3, count 2 2006.257.07:19:47.38#ibcon#*mode == 0, iclass 3, count 2 2006.257.07:19:47.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.07:19:47.38#ibcon#[25=AT01-08\r\n] 2006.257.07:19:47.38#ibcon#*before write, iclass 3, count 2 2006.257.07:19:47.38#ibcon#enter sib2, iclass 3, count 2 2006.257.07:19:47.38#ibcon#flushed, iclass 3, count 2 2006.257.07:19:47.38#ibcon#about to write, iclass 3, count 2 2006.257.07:19:47.38#ibcon#wrote, iclass 3, count 2 2006.257.07:19:47.38#ibcon#about to read 3, iclass 3, count 2 2006.257.07:19:47.41#ibcon#read 3, iclass 3, count 2 2006.257.07:19:47.41#ibcon#about to read 4, iclass 3, count 2 2006.257.07:19:47.41#ibcon#read 4, iclass 3, count 2 2006.257.07:19:47.41#ibcon#about to read 5, iclass 3, count 2 2006.257.07:19:47.41#ibcon#read 5, iclass 3, count 2 2006.257.07:19:47.41#ibcon#about to read 6, iclass 3, count 2 2006.257.07:19:47.41#ibcon#read 6, iclass 3, count 2 2006.257.07:19:47.41#ibcon#end of sib2, iclass 3, count 2 2006.257.07:19:47.41#ibcon#*after write, iclass 3, count 2 2006.257.07:19:47.41#ibcon#*before return 0, iclass 3, count 2 2006.257.07:19:47.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:47.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:47.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.07:19:47.41#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:47.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:47.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:47.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:47.53#ibcon#enter wrdev, iclass 3, count 0 2006.257.07:19:47.53#ibcon#first serial, iclass 3, count 0 2006.257.07:19:47.53#ibcon#enter sib2, iclass 3, count 0 2006.257.07:19:47.53#ibcon#flushed, iclass 3, count 0 2006.257.07:19:47.53#ibcon#about to write, iclass 3, count 0 2006.257.07:19:47.53#ibcon#wrote, iclass 3, count 0 2006.257.07:19:47.53#ibcon#about to read 3, iclass 3, count 0 2006.257.07:19:47.55#ibcon#read 3, iclass 3, count 0 2006.257.07:19:47.55#ibcon#about to read 4, iclass 3, count 0 2006.257.07:19:47.55#ibcon#read 4, iclass 3, count 0 2006.257.07:19:47.55#ibcon#about to read 5, iclass 3, count 0 2006.257.07:19:47.55#ibcon#read 5, iclass 3, count 0 2006.257.07:19:47.55#ibcon#about to read 6, iclass 3, count 0 2006.257.07:19:47.55#ibcon#read 6, iclass 3, count 0 2006.257.07:19:47.55#ibcon#end of sib2, iclass 3, count 0 2006.257.07:19:47.55#ibcon#*mode == 0, iclass 3, count 0 2006.257.07:19:47.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.07:19:47.55#ibcon#[25=USB\r\n] 2006.257.07:19:47.55#ibcon#*before write, iclass 3, count 0 2006.257.07:19:47.55#ibcon#enter sib2, iclass 3, count 0 2006.257.07:19:47.55#ibcon#flushed, iclass 3, count 0 2006.257.07:19:47.55#ibcon#about to write, iclass 3, count 0 2006.257.07:19:47.55#ibcon#wrote, iclass 3, count 0 2006.257.07:19:47.55#ibcon#about to read 3, iclass 3, count 0 2006.257.07:19:47.58#ibcon#read 3, iclass 3, count 0 2006.257.07:19:47.58#ibcon#about to read 4, iclass 3, count 0 2006.257.07:19:47.58#ibcon#read 4, iclass 3, count 0 2006.257.07:19:47.58#ibcon#about to read 5, iclass 3, count 0 2006.257.07:19:47.58#ibcon#read 5, iclass 3, count 0 2006.257.07:19:47.58#ibcon#about to read 6, iclass 3, count 0 2006.257.07:19:47.58#ibcon#read 6, iclass 3, count 0 2006.257.07:19:47.58#ibcon#end of sib2, iclass 3, count 0 2006.257.07:19:47.58#ibcon#*after write, iclass 3, count 0 2006.257.07:19:47.58#ibcon#*before return 0, iclass 3, count 0 2006.257.07:19:47.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:47.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:47.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.07:19:47.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.07:19:47.58$vck44/valo=2,534.99 2006.257.07:19:47.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.07:19:47.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.07:19:47.58#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:47.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:47.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:47.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:47.58#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:19:47.58#ibcon#first serial, iclass 5, count 0 2006.257.07:19:47.58#ibcon#enter sib2, iclass 5, count 0 2006.257.07:19:47.58#ibcon#flushed, iclass 5, count 0 2006.257.07:19:47.58#ibcon#about to write, iclass 5, count 0 2006.257.07:19:47.58#ibcon#wrote, iclass 5, count 0 2006.257.07:19:47.58#ibcon#about to read 3, iclass 5, count 0 2006.257.07:19:47.60#ibcon#read 3, iclass 5, count 0 2006.257.07:19:47.60#ibcon#about to read 4, iclass 5, count 0 2006.257.07:19:47.60#ibcon#read 4, iclass 5, count 0 2006.257.07:19:47.60#ibcon#about to read 5, iclass 5, count 0 2006.257.07:19:47.60#ibcon#read 5, iclass 5, count 0 2006.257.07:19:47.60#ibcon#about to read 6, iclass 5, count 0 2006.257.07:19:47.60#ibcon#read 6, iclass 5, count 0 2006.257.07:19:47.60#ibcon#end of sib2, iclass 5, count 0 2006.257.07:19:47.60#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:19:47.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:19:47.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.07:19:47.60#ibcon#*before write, iclass 5, count 0 2006.257.07:19:47.60#ibcon#enter sib2, iclass 5, count 0 2006.257.07:19:47.60#ibcon#flushed, iclass 5, count 0 2006.257.07:19:47.60#ibcon#about to write, iclass 5, count 0 2006.257.07:19:47.60#ibcon#wrote, iclass 5, count 0 2006.257.07:19:47.60#ibcon#about to read 3, iclass 5, count 0 2006.257.07:19:47.64#ibcon#read 3, iclass 5, count 0 2006.257.07:19:47.64#ibcon#about to read 4, iclass 5, count 0 2006.257.07:19:47.64#ibcon#read 4, iclass 5, count 0 2006.257.07:19:47.64#ibcon#about to read 5, iclass 5, count 0 2006.257.07:19:47.64#ibcon#read 5, iclass 5, count 0 2006.257.07:19:47.64#ibcon#about to read 6, iclass 5, count 0 2006.257.07:19:47.64#ibcon#read 6, iclass 5, count 0 2006.257.07:19:47.64#ibcon#end of sib2, iclass 5, count 0 2006.257.07:19:47.64#ibcon#*after write, iclass 5, count 0 2006.257.07:19:47.64#ibcon#*before return 0, iclass 5, count 0 2006.257.07:19:47.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:47.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:47.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:19:47.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:19:47.64$vck44/va=2,7 2006.257.07:19:47.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.07:19:47.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.07:19:47.64#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:47.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:47.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:47.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:47.70#ibcon#enter wrdev, iclass 7, count 2 2006.257.07:19:47.70#ibcon#first serial, iclass 7, count 2 2006.257.07:19:47.70#ibcon#enter sib2, iclass 7, count 2 2006.257.07:19:47.70#ibcon#flushed, iclass 7, count 2 2006.257.07:19:47.70#ibcon#about to write, iclass 7, count 2 2006.257.07:19:47.70#ibcon#wrote, iclass 7, count 2 2006.257.07:19:47.70#ibcon#about to read 3, iclass 7, count 2 2006.257.07:19:47.72#ibcon#read 3, iclass 7, count 2 2006.257.07:19:47.72#ibcon#about to read 4, iclass 7, count 2 2006.257.07:19:47.72#ibcon#read 4, iclass 7, count 2 2006.257.07:19:47.72#ibcon#about to read 5, iclass 7, count 2 2006.257.07:19:47.72#ibcon#read 5, iclass 7, count 2 2006.257.07:19:47.72#ibcon#about to read 6, iclass 7, count 2 2006.257.07:19:47.72#ibcon#read 6, iclass 7, count 2 2006.257.07:19:47.72#ibcon#end of sib2, iclass 7, count 2 2006.257.07:19:47.72#ibcon#*mode == 0, iclass 7, count 2 2006.257.07:19:47.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.07:19:47.72#ibcon#[25=AT02-07\r\n] 2006.257.07:19:47.72#ibcon#*before write, iclass 7, count 2 2006.257.07:19:47.72#ibcon#enter sib2, iclass 7, count 2 2006.257.07:19:47.72#ibcon#flushed, iclass 7, count 2 2006.257.07:19:47.72#ibcon#about to write, iclass 7, count 2 2006.257.07:19:47.72#ibcon#wrote, iclass 7, count 2 2006.257.07:19:47.72#ibcon#about to read 3, iclass 7, count 2 2006.257.07:19:47.75#ibcon#read 3, iclass 7, count 2 2006.257.07:19:47.75#ibcon#about to read 4, iclass 7, count 2 2006.257.07:19:47.75#ibcon#read 4, iclass 7, count 2 2006.257.07:19:47.75#ibcon#about to read 5, iclass 7, count 2 2006.257.07:19:47.75#ibcon#read 5, iclass 7, count 2 2006.257.07:19:47.75#ibcon#about to read 6, iclass 7, count 2 2006.257.07:19:47.75#ibcon#read 6, iclass 7, count 2 2006.257.07:19:47.75#ibcon#end of sib2, iclass 7, count 2 2006.257.07:19:47.75#ibcon#*after write, iclass 7, count 2 2006.257.07:19:47.75#ibcon#*before return 0, iclass 7, count 2 2006.257.07:19:47.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:47.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:47.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.07:19:47.75#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:47.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:47.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:47.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:47.87#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:19:47.87#ibcon#first serial, iclass 7, count 0 2006.257.07:19:47.87#ibcon#enter sib2, iclass 7, count 0 2006.257.07:19:47.87#ibcon#flushed, iclass 7, count 0 2006.257.07:19:47.87#ibcon#about to write, iclass 7, count 0 2006.257.07:19:47.87#ibcon#wrote, iclass 7, count 0 2006.257.07:19:47.87#ibcon#about to read 3, iclass 7, count 0 2006.257.07:19:47.89#ibcon#read 3, iclass 7, count 0 2006.257.07:19:47.89#ibcon#about to read 4, iclass 7, count 0 2006.257.07:19:47.89#ibcon#read 4, iclass 7, count 0 2006.257.07:19:47.89#ibcon#about to read 5, iclass 7, count 0 2006.257.07:19:47.89#ibcon#read 5, iclass 7, count 0 2006.257.07:19:47.89#ibcon#about to read 6, iclass 7, count 0 2006.257.07:19:47.89#ibcon#read 6, iclass 7, count 0 2006.257.07:19:47.89#ibcon#end of sib2, iclass 7, count 0 2006.257.07:19:47.89#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:19:47.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:19:47.89#ibcon#[25=USB\r\n] 2006.257.07:19:47.89#ibcon#*before write, iclass 7, count 0 2006.257.07:19:47.89#ibcon#enter sib2, iclass 7, count 0 2006.257.07:19:47.89#ibcon#flushed, iclass 7, count 0 2006.257.07:19:47.89#ibcon#about to write, iclass 7, count 0 2006.257.07:19:47.89#ibcon#wrote, iclass 7, count 0 2006.257.07:19:47.89#ibcon#about to read 3, iclass 7, count 0 2006.257.07:19:47.92#ibcon#read 3, iclass 7, count 0 2006.257.07:19:47.92#ibcon#about to read 4, iclass 7, count 0 2006.257.07:19:47.92#ibcon#read 4, iclass 7, count 0 2006.257.07:19:47.92#ibcon#about to read 5, iclass 7, count 0 2006.257.07:19:47.92#ibcon#read 5, iclass 7, count 0 2006.257.07:19:47.92#ibcon#about to read 6, iclass 7, count 0 2006.257.07:19:47.92#ibcon#read 6, iclass 7, count 0 2006.257.07:19:47.92#ibcon#end of sib2, iclass 7, count 0 2006.257.07:19:47.92#ibcon#*after write, iclass 7, count 0 2006.257.07:19:47.92#ibcon#*before return 0, iclass 7, count 0 2006.257.07:19:47.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:47.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:47.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:19:47.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:19:47.92$vck44/valo=3,564.99 2006.257.07:19:47.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.07:19:47.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.07:19:47.92#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:47.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:47.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:47.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:47.92#ibcon#enter wrdev, iclass 11, count 0 2006.257.07:19:47.92#ibcon#first serial, iclass 11, count 0 2006.257.07:19:47.92#ibcon#enter sib2, iclass 11, count 0 2006.257.07:19:47.92#ibcon#flushed, iclass 11, count 0 2006.257.07:19:47.92#ibcon#about to write, iclass 11, count 0 2006.257.07:19:47.92#ibcon#wrote, iclass 11, count 0 2006.257.07:19:47.92#ibcon#about to read 3, iclass 11, count 0 2006.257.07:19:47.94#ibcon#read 3, iclass 11, count 0 2006.257.07:19:47.94#ibcon#about to read 4, iclass 11, count 0 2006.257.07:19:47.94#ibcon#read 4, iclass 11, count 0 2006.257.07:19:47.94#ibcon#about to read 5, iclass 11, count 0 2006.257.07:19:47.94#ibcon#read 5, iclass 11, count 0 2006.257.07:19:47.94#ibcon#about to read 6, iclass 11, count 0 2006.257.07:19:47.94#ibcon#read 6, iclass 11, count 0 2006.257.07:19:47.94#ibcon#end of sib2, iclass 11, count 0 2006.257.07:19:47.94#ibcon#*mode == 0, iclass 11, count 0 2006.257.07:19:47.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.07:19:47.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.07:19:47.94#ibcon#*before write, iclass 11, count 0 2006.257.07:19:47.94#ibcon#enter sib2, iclass 11, count 0 2006.257.07:19:47.94#ibcon#flushed, iclass 11, count 0 2006.257.07:19:47.94#ibcon#about to write, iclass 11, count 0 2006.257.07:19:47.94#ibcon#wrote, iclass 11, count 0 2006.257.07:19:47.94#ibcon#about to read 3, iclass 11, count 0 2006.257.07:19:47.98#ibcon#read 3, iclass 11, count 0 2006.257.07:19:47.98#ibcon#about to read 4, iclass 11, count 0 2006.257.07:19:47.98#ibcon#read 4, iclass 11, count 0 2006.257.07:19:47.98#ibcon#about to read 5, iclass 11, count 0 2006.257.07:19:47.98#ibcon#read 5, iclass 11, count 0 2006.257.07:19:47.98#ibcon#about to read 6, iclass 11, count 0 2006.257.07:19:47.98#ibcon#read 6, iclass 11, count 0 2006.257.07:19:47.98#ibcon#end of sib2, iclass 11, count 0 2006.257.07:19:47.98#ibcon#*after write, iclass 11, count 0 2006.257.07:19:47.98#ibcon#*before return 0, iclass 11, count 0 2006.257.07:19:47.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:47.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:47.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.07:19:47.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.07:19:47.98$vck44/va=3,8 2006.257.07:19:47.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.07:19:47.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.07:19:47.98#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:47.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:48.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:48.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:48.04#ibcon#enter wrdev, iclass 13, count 2 2006.257.07:19:48.04#ibcon#first serial, iclass 13, count 2 2006.257.07:19:48.04#ibcon#enter sib2, iclass 13, count 2 2006.257.07:19:48.04#ibcon#flushed, iclass 13, count 2 2006.257.07:19:48.04#ibcon#about to write, iclass 13, count 2 2006.257.07:19:48.04#ibcon#wrote, iclass 13, count 2 2006.257.07:19:48.04#ibcon#about to read 3, iclass 13, count 2 2006.257.07:19:48.06#ibcon#read 3, iclass 13, count 2 2006.257.07:19:48.06#ibcon#about to read 4, iclass 13, count 2 2006.257.07:19:48.06#ibcon#read 4, iclass 13, count 2 2006.257.07:19:48.06#ibcon#about to read 5, iclass 13, count 2 2006.257.07:19:48.06#ibcon#read 5, iclass 13, count 2 2006.257.07:19:48.06#ibcon#about to read 6, iclass 13, count 2 2006.257.07:19:48.06#ibcon#read 6, iclass 13, count 2 2006.257.07:19:48.06#ibcon#end of sib2, iclass 13, count 2 2006.257.07:19:48.06#ibcon#*mode == 0, iclass 13, count 2 2006.257.07:19:48.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.07:19:48.06#ibcon#[25=AT03-08\r\n] 2006.257.07:19:48.06#ibcon#*before write, iclass 13, count 2 2006.257.07:19:48.06#ibcon#enter sib2, iclass 13, count 2 2006.257.07:19:48.06#ibcon#flushed, iclass 13, count 2 2006.257.07:19:48.06#ibcon#about to write, iclass 13, count 2 2006.257.07:19:48.06#ibcon#wrote, iclass 13, count 2 2006.257.07:19:48.06#ibcon#about to read 3, iclass 13, count 2 2006.257.07:19:48.09#ibcon#read 3, iclass 13, count 2 2006.257.07:19:48.09#ibcon#about to read 4, iclass 13, count 2 2006.257.07:19:48.09#ibcon#read 4, iclass 13, count 2 2006.257.07:19:48.09#ibcon#about to read 5, iclass 13, count 2 2006.257.07:19:48.09#ibcon#read 5, iclass 13, count 2 2006.257.07:19:48.09#ibcon#about to read 6, iclass 13, count 2 2006.257.07:19:48.09#ibcon#read 6, iclass 13, count 2 2006.257.07:19:48.09#ibcon#end of sib2, iclass 13, count 2 2006.257.07:19:48.09#ibcon#*after write, iclass 13, count 2 2006.257.07:19:48.09#ibcon#*before return 0, iclass 13, count 2 2006.257.07:19:48.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:48.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:48.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.07:19:48.09#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:48.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:48.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:48.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:48.21#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:19:48.21#ibcon#first serial, iclass 13, count 0 2006.257.07:19:48.21#ibcon#enter sib2, iclass 13, count 0 2006.257.07:19:48.21#ibcon#flushed, iclass 13, count 0 2006.257.07:19:48.21#ibcon#about to write, iclass 13, count 0 2006.257.07:19:48.21#ibcon#wrote, iclass 13, count 0 2006.257.07:19:48.21#ibcon#about to read 3, iclass 13, count 0 2006.257.07:19:48.23#ibcon#read 3, iclass 13, count 0 2006.257.07:19:48.23#ibcon#about to read 4, iclass 13, count 0 2006.257.07:19:48.23#ibcon#read 4, iclass 13, count 0 2006.257.07:19:48.23#ibcon#about to read 5, iclass 13, count 0 2006.257.07:19:48.23#ibcon#read 5, iclass 13, count 0 2006.257.07:19:48.23#ibcon#about to read 6, iclass 13, count 0 2006.257.07:19:48.23#ibcon#read 6, iclass 13, count 0 2006.257.07:19:48.23#ibcon#end of sib2, iclass 13, count 0 2006.257.07:19:48.23#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:19:48.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:19:48.23#ibcon#[25=USB\r\n] 2006.257.07:19:48.23#ibcon#*before write, iclass 13, count 0 2006.257.07:19:48.23#ibcon#enter sib2, iclass 13, count 0 2006.257.07:19:48.23#ibcon#flushed, iclass 13, count 0 2006.257.07:19:48.23#ibcon#about to write, iclass 13, count 0 2006.257.07:19:48.23#ibcon#wrote, iclass 13, count 0 2006.257.07:19:48.23#ibcon#about to read 3, iclass 13, count 0 2006.257.07:19:48.26#ibcon#read 3, iclass 13, count 0 2006.257.07:19:48.26#ibcon#about to read 4, iclass 13, count 0 2006.257.07:19:48.26#ibcon#read 4, iclass 13, count 0 2006.257.07:19:48.26#ibcon#about to read 5, iclass 13, count 0 2006.257.07:19:48.26#ibcon#read 5, iclass 13, count 0 2006.257.07:19:48.26#ibcon#about to read 6, iclass 13, count 0 2006.257.07:19:48.26#ibcon#read 6, iclass 13, count 0 2006.257.07:19:48.26#ibcon#end of sib2, iclass 13, count 0 2006.257.07:19:48.26#ibcon#*after write, iclass 13, count 0 2006.257.07:19:48.26#ibcon#*before return 0, iclass 13, count 0 2006.257.07:19:48.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:48.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:48.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:19:48.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:19:48.26$vck44/valo=4,624.99 2006.257.07:19:48.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.07:19:48.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.07:19:48.26#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:48.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:48.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:48.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:48.26#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:19:48.26#ibcon#first serial, iclass 15, count 0 2006.257.07:19:48.26#ibcon#enter sib2, iclass 15, count 0 2006.257.07:19:48.26#ibcon#flushed, iclass 15, count 0 2006.257.07:19:48.26#ibcon#about to write, iclass 15, count 0 2006.257.07:19:48.26#ibcon#wrote, iclass 15, count 0 2006.257.07:19:48.26#ibcon#about to read 3, iclass 15, count 0 2006.257.07:19:48.28#ibcon#read 3, iclass 15, count 0 2006.257.07:19:48.28#ibcon#about to read 4, iclass 15, count 0 2006.257.07:19:48.28#ibcon#read 4, iclass 15, count 0 2006.257.07:19:48.28#ibcon#about to read 5, iclass 15, count 0 2006.257.07:19:48.28#ibcon#read 5, iclass 15, count 0 2006.257.07:19:48.28#ibcon#about to read 6, iclass 15, count 0 2006.257.07:19:48.28#ibcon#read 6, iclass 15, count 0 2006.257.07:19:48.28#ibcon#end of sib2, iclass 15, count 0 2006.257.07:19:48.28#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:19:48.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:19:48.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.07:19:48.28#ibcon#*before write, iclass 15, count 0 2006.257.07:19:48.28#ibcon#enter sib2, iclass 15, count 0 2006.257.07:19:48.28#ibcon#flushed, iclass 15, count 0 2006.257.07:19:48.28#ibcon#about to write, iclass 15, count 0 2006.257.07:19:48.28#ibcon#wrote, iclass 15, count 0 2006.257.07:19:48.28#ibcon#about to read 3, iclass 15, count 0 2006.257.07:19:48.32#ibcon#read 3, iclass 15, count 0 2006.257.07:19:48.32#ibcon#about to read 4, iclass 15, count 0 2006.257.07:19:48.32#ibcon#read 4, iclass 15, count 0 2006.257.07:19:48.32#ibcon#about to read 5, iclass 15, count 0 2006.257.07:19:48.32#ibcon#read 5, iclass 15, count 0 2006.257.07:19:48.32#ibcon#about to read 6, iclass 15, count 0 2006.257.07:19:48.32#ibcon#read 6, iclass 15, count 0 2006.257.07:19:48.32#ibcon#end of sib2, iclass 15, count 0 2006.257.07:19:48.32#ibcon#*after write, iclass 15, count 0 2006.257.07:19:48.32#ibcon#*before return 0, iclass 15, count 0 2006.257.07:19:48.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:48.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:48.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:19:48.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:19:48.32$vck44/va=4,7 2006.257.07:19:48.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.07:19:48.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.07:19:48.32#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:48.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:48.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:48.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:48.38#ibcon#enter wrdev, iclass 17, count 2 2006.257.07:19:48.38#ibcon#first serial, iclass 17, count 2 2006.257.07:19:48.38#ibcon#enter sib2, iclass 17, count 2 2006.257.07:19:48.38#ibcon#flushed, iclass 17, count 2 2006.257.07:19:48.38#ibcon#about to write, iclass 17, count 2 2006.257.07:19:48.38#ibcon#wrote, iclass 17, count 2 2006.257.07:19:48.38#ibcon#about to read 3, iclass 17, count 2 2006.257.07:19:48.40#ibcon#read 3, iclass 17, count 2 2006.257.07:19:48.40#ibcon#about to read 4, iclass 17, count 2 2006.257.07:19:48.40#ibcon#read 4, iclass 17, count 2 2006.257.07:19:48.40#ibcon#about to read 5, iclass 17, count 2 2006.257.07:19:48.40#ibcon#read 5, iclass 17, count 2 2006.257.07:19:48.40#ibcon#about to read 6, iclass 17, count 2 2006.257.07:19:48.40#ibcon#read 6, iclass 17, count 2 2006.257.07:19:48.40#ibcon#end of sib2, iclass 17, count 2 2006.257.07:19:48.40#ibcon#*mode == 0, iclass 17, count 2 2006.257.07:19:48.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.07:19:48.40#ibcon#[25=AT04-07\r\n] 2006.257.07:19:48.40#ibcon#*before write, iclass 17, count 2 2006.257.07:19:48.40#ibcon#enter sib2, iclass 17, count 2 2006.257.07:19:48.40#ibcon#flushed, iclass 17, count 2 2006.257.07:19:48.40#ibcon#about to write, iclass 17, count 2 2006.257.07:19:48.40#ibcon#wrote, iclass 17, count 2 2006.257.07:19:48.40#ibcon#about to read 3, iclass 17, count 2 2006.257.07:19:48.43#ibcon#read 3, iclass 17, count 2 2006.257.07:19:48.43#ibcon#about to read 4, iclass 17, count 2 2006.257.07:19:48.43#ibcon#read 4, iclass 17, count 2 2006.257.07:19:48.43#ibcon#about to read 5, iclass 17, count 2 2006.257.07:19:48.43#ibcon#read 5, iclass 17, count 2 2006.257.07:19:48.43#ibcon#about to read 6, iclass 17, count 2 2006.257.07:19:48.43#ibcon#read 6, iclass 17, count 2 2006.257.07:19:48.43#ibcon#end of sib2, iclass 17, count 2 2006.257.07:19:48.43#ibcon#*after write, iclass 17, count 2 2006.257.07:19:48.43#ibcon#*before return 0, iclass 17, count 2 2006.257.07:19:48.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:48.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:48.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.07:19:48.43#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:48.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:48.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:48.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:48.55#ibcon#enter wrdev, iclass 17, count 0 2006.257.07:19:48.55#ibcon#first serial, iclass 17, count 0 2006.257.07:19:48.55#ibcon#enter sib2, iclass 17, count 0 2006.257.07:19:48.55#ibcon#flushed, iclass 17, count 0 2006.257.07:19:48.55#ibcon#about to write, iclass 17, count 0 2006.257.07:19:48.55#ibcon#wrote, iclass 17, count 0 2006.257.07:19:48.55#ibcon#about to read 3, iclass 17, count 0 2006.257.07:19:48.57#ibcon#read 3, iclass 17, count 0 2006.257.07:19:48.57#ibcon#about to read 4, iclass 17, count 0 2006.257.07:19:48.57#ibcon#read 4, iclass 17, count 0 2006.257.07:19:48.57#ibcon#about to read 5, iclass 17, count 0 2006.257.07:19:48.57#ibcon#read 5, iclass 17, count 0 2006.257.07:19:48.57#ibcon#about to read 6, iclass 17, count 0 2006.257.07:19:48.57#ibcon#read 6, iclass 17, count 0 2006.257.07:19:48.57#ibcon#end of sib2, iclass 17, count 0 2006.257.07:19:48.57#ibcon#*mode == 0, iclass 17, count 0 2006.257.07:19:48.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.07:19:48.57#ibcon#[25=USB\r\n] 2006.257.07:19:48.57#ibcon#*before write, iclass 17, count 0 2006.257.07:19:48.57#ibcon#enter sib2, iclass 17, count 0 2006.257.07:19:48.57#ibcon#flushed, iclass 17, count 0 2006.257.07:19:48.57#ibcon#about to write, iclass 17, count 0 2006.257.07:19:48.57#ibcon#wrote, iclass 17, count 0 2006.257.07:19:48.57#ibcon#about to read 3, iclass 17, count 0 2006.257.07:19:48.60#ibcon#read 3, iclass 17, count 0 2006.257.07:19:48.60#ibcon#about to read 4, iclass 17, count 0 2006.257.07:19:48.60#ibcon#read 4, iclass 17, count 0 2006.257.07:19:48.60#ibcon#about to read 5, iclass 17, count 0 2006.257.07:19:48.60#ibcon#read 5, iclass 17, count 0 2006.257.07:19:48.60#ibcon#about to read 6, iclass 17, count 0 2006.257.07:19:48.60#ibcon#read 6, iclass 17, count 0 2006.257.07:19:48.60#ibcon#end of sib2, iclass 17, count 0 2006.257.07:19:48.60#ibcon#*after write, iclass 17, count 0 2006.257.07:19:48.60#ibcon#*before return 0, iclass 17, count 0 2006.257.07:19:48.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:48.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:48.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.07:19:48.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.07:19:48.60$vck44/valo=5,734.99 2006.257.07:19:48.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.07:19:48.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.07:19:48.60#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:48.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:48.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:48.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:48.60#ibcon#enter wrdev, iclass 19, count 0 2006.257.07:19:48.60#ibcon#first serial, iclass 19, count 0 2006.257.07:19:48.60#ibcon#enter sib2, iclass 19, count 0 2006.257.07:19:48.60#ibcon#flushed, iclass 19, count 0 2006.257.07:19:48.60#ibcon#about to write, iclass 19, count 0 2006.257.07:19:48.60#ibcon#wrote, iclass 19, count 0 2006.257.07:19:48.60#ibcon#about to read 3, iclass 19, count 0 2006.257.07:19:48.62#ibcon#read 3, iclass 19, count 0 2006.257.07:19:48.62#ibcon#about to read 4, iclass 19, count 0 2006.257.07:19:48.62#ibcon#read 4, iclass 19, count 0 2006.257.07:19:48.62#ibcon#about to read 5, iclass 19, count 0 2006.257.07:19:48.62#ibcon#read 5, iclass 19, count 0 2006.257.07:19:48.62#ibcon#about to read 6, iclass 19, count 0 2006.257.07:19:48.62#ibcon#read 6, iclass 19, count 0 2006.257.07:19:48.62#ibcon#end of sib2, iclass 19, count 0 2006.257.07:19:48.62#ibcon#*mode == 0, iclass 19, count 0 2006.257.07:19:48.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.07:19:48.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.07:19:48.62#ibcon#*before write, iclass 19, count 0 2006.257.07:19:48.62#ibcon#enter sib2, iclass 19, count 0 2006.257.07:19:48.62#ibcon#flushed, iclass 19, count 0 2006.257.07:19:48.62#ibcon#about to write, iclass 19, count 0 2006.257.07:19:48.62#ibcon#wrote, iclass 19, count 0 2006.257.07:19:48.62#ibcon#about to read 3, iclass 19, count 0 2006.257.07:19:48.66#ibcon#read 3, iclass 19, count 0 2006.257.07:19:48.66#ibcon#about to read 4, iclass 19, count 0 2006.257.07:19:48.66#ibcon#read 4, iclass 19, count 0 2006.257.07:19:48.66#ibcon#about to read 5, iclass 19, count 0 2006.257.07:19:48.66#ibcon#read 5, iclass 19, count 0 2006.257.07:19:48.66#ibcon#about to read 6, iclass 19, count 0 2006.257.07:19:48.66#ibcon#read 6, iclass 19, count 0 2006.257.07:19:48.66#ibcon#end of sib2, iclass 19, count 0 2006.257.07:19:48.66#ibcon#*after write, iclass 19, count 0 2006.257.07:19:48.66#ibcon#*before return 0, iclass 19, count 0 2006.257.07:19:48.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:48.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:48.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.07:19:48.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.07:19:48.66$vck44/va=5,4 2006.257.07:19:48.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.07:19:48.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.07:19:48.66#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:48.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:48.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:48.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:48.72#ibcon#enter wrdev, iclass 21, count 2 2006.257.07:19:48.72#ibcon#first serial, iclass 21, count 2 2006.257.07:19:48.72#ibcon#enter sib2, iclass 21, count 2 2006.257.07:19:48.72#ibcon#flushed, iclass 21, count 2 2006.257.07:19:48.72#ibcon#about to write, iclass 21, count 2 2006.257.07:19:48.72#ibcon#wrote, iclass 21, count 2 2006.257.07:19:48.72#ibcon#about to read 3, iclass 21, count 2 2006.257.07:19:48.74#ibcon#read 3, iclass 21, count 2 2006.257.07:19:48.74#ibcon#about to read 4, iclass 21, count 2 2006.257.07:19:48.74#ibcon#read 4, iclass 21, count 2 2006.257.07:19:48.74#ibcon#about to read 5, iclass 21, count 2 2006.257.07:19:48.74#ibcon#read 5, iclass 21, count 2 2006.257.07:19:48.74#ibcon#about to read 6, iclass 21, count 2 2006.257.07:19:48.74#ibcon#read 6, iclass 21, count 2 2006.257.07:19:48.74#ibcon#end of sib2, iclass 21, count 2 2006.257.07:19:48.74#ibcon#*mode == 0, iclass 21, count 2 2006.257.07:19:48.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.07:19:48.74#ibcon#[25=AT05-04\r\n] 2006.257.07:19:48.74#ibcon#*before write, iclass 21, count 2 2006.257.07:19:48.74#ibcon#enter sib2, iclass 21, count 2 2006.257.07:19:48.74#ibcon#flushed, iclass 21, count 2 2006.257.07:19:48.74#ibcon#about to write, iclass 21, count 2 2006.257.07:19:48.74#ibcon#wrote, iclass 21, count 2 2006.257.07:19:48.74#ibcon#about to read 3, iclass 21, count 2 2006.257.07:19:48.77#ibcon#read 3, iclass 21, count 2 2006.257.07:19:48.77#ibcon#about to read 4, iclass 21, count 2 2006.257.07:19:48.77#ibcon#read 4, iclass 21, count 2 2006.257.07:19:48.77#ibcon#about to read 5, iclass 21, count 2 2006.257.07:19:48.77#ibcon#read 5, iclass 21, count 2 2006.257.07:19:48.77#ibcon#about to read 6, iclass 21, count 2 2006.257.07:19:48.77#ibcon#read 6, iclass 21, count 2 2006.257.07:19:48.77#ibcon#end of sib2, iclass 21, count 2 2006.257.07:19:48.77#ibcon#*after write, iclass 21, count 2 2006.257.07:19:48.77#ibcon#*before return 0, iclass 21, count 2 2006.257.07:19:48.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:48.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:48.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.07:19:48.77#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:48.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:48.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:48.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:48.89#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:19:48.89#ibcon#first serial, iclass 21, count 0 2006.257.07:19:48.89#ibcon#enter sib2, iclass 21, count 0 2006.257.07:19:48.89#ibcon#flushed, iclass 21, count 0 2006.257.07:19:48.89#ibcon#about to write, iclass 21, count 0 2006.257.07:19:48.89#ibcon#wrote, iclass 21, count 0 2006.257.07:19:48.89#ibcon#about to read 3, iclass 21, count 0 2006.257.07:19:48.91#ibcon#read 3, iclass 21, count 0 2006.257.07:19:48.91#ibcon#about to read 4, iclass 21, count 0 2006.257.07:19:48.91#ibcon#read 4, iclass 21, count 0 2006.257.07:19:48.91#ibcon#about to read 5, iclass 21, count 0 2006.257.07:19:48.91#ibcon#read 5, iclass 21, count 0 2006.257.07:19:48.91#ibcon#about to read 6, iclass 21, count 0 2006.257.07:19:48.91#ibcon#read 6, iclass 21, count 0 2006.257.07:19:48.91#ibcon#end of sib2, iclass 21, count 0 2006.257.07:19:48.91#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:19:48.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:19:48.91#ibcon#[25=USB\r\n] 2006.257.07:19:48.91#ibcon#*before write, iclass 21, count 0 2006.257.07:19:48.91#ibcon#enter sib2, iclass 21, count 0 2006.257.07:19:48.91#ibcon#flushed, iclass 21, count 0 2006.257.07:19:48.91#ibcon#about to write, iclass 21, count 0 2006.257.07:19:48.91#ibcon#wrote, iclass 21, count 0 2006.257.07:19:48.91#ibcon#about to read 3, iclass 21, count 0 2006.257.07:19:48.94#ibcon#read 3, iclass 21, count 0 2006.257.07:19:48.94#ibcon#about to read 4, iclass 21, count 0 2006.257.07:19:48.94#ibcon#read 4, iclass 21, count 0 2006.257.07:19:48.94#ibcon#about to read 5, iclass 21, count 0 2006.257.07:19:48.94#ibcon#read 5, iclass 21, count 0 2006.257.07:19:48.94#ibcon#about to read 6, iclass 21, count 0 2006.257.07:19:48.94#ibcon#read 6, iclass 21, count 0 2006.257.07:19:48.94#ibcon#end of sib2, iclass 21, count 0 2006.257.07:19:48.94#ibcon#*after write, iclass 21, count 0 2006.257.07:19:48.94#ibcon#*before return 0, iclass 21, count 0 2006.257.07:19:48.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:48.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:48.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:19:48.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:19:48.94$vck44/valo=6,814.99 2006.257.07:19:48.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.07:19:48.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.07:19:48.94#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:48.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:48.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:48.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:48.94#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:19:48.94#ibcon#first serial, iclass 23, count 0 2006.257.07:19:48.94#ibcon#enter sib2, iclass 23, count 0 2006.257.07:19:48.94#ibcon#flushed, iclass 23, count 0 2006.257.07:19:48.94#ibcon#about to write, iclass 23, count 0 2006.257.07:19:48.94#ibcon#wrote, iclass 23, count 0 2006.257.07:19:48.94#ibcon#about to read 3, iclass 23, count 0 2006.257.07:19:48.96#ibcon#read 3, iclass 23, count 0 2006.257.07:19:48.96#ibcon#about to read 4, iclass 23, count 0 2006.257.07:19:48.96#ibcon#read 4, iclass 23, count 0 2006.257.07:19:48.96#ibcon#about to read 5, iclass 23, count 0 2006.257.07:19:48.96#ibcon#read 5, iclass 23, count 0 2006.257.07:19:48.96#ibcon#about to read 6, iclass 23, count 0 2006.257.07:19:48.96#ibcon#read 6, iclass 23, count 0 2006.257.07:19:48.96#ibcon#end of sib2, iclass 23, count 0 2006.257.07:19:48.96#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:19:48.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:19:48.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.07:19:48.96#ibcon#*before write, iclass 23, count 0 2006.257.07:19:48.96#ibcon#enter sib2, iclass 23, count 0 2006.257.07:19:48.96#ibcon#flushed, iclass 23, count 0 2006.257.07:19:48.96#ibcon#about to write, iclass 23, count 0 2006.257.07:19:48.96#ibcon#wrote, iclass 23, count 0 2006.257.07:19:48.96#ibcon#about to read 3, iclass 23, count 0 2006.257.07:19:49.00#ibcon#read 3, iclass 23, count 0 2006.257.07:19:49.00#ibcon#about to read 4, iclass 23, count 0 2006.257.07:19:49.00#ibcon#read 4, iclass 23, count 0 2006.257.07:19:49.00#ibcon#about to read 5, iclass 23, count 0 2006.257.07:19:49.00#ibcon#read 5, iclass 23, count 0 2006.257.07:19:49.00#ibcon#about to read 6, iclass 23, count 0 2006.257.07:19:49.00#ibcon#read 6, iclass 23, count 0 2006.257.07:19:49.00#ibcon#end of sib2, iclass 23, count 0 2006.257.07:19:49.00#ibcon#*after write, iclass 23, count 0 2006.257.07:19:49.00#ibcon#*before return 0, iclass 23, count 0 2006.257.07:19:49.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:49.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:49.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:19:49.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:19:49.00$vck44/va=6,4 2006.257.07:19:49.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.07:19:49.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.07:19:49.00#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:49.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:49.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:49.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:49.06#ibcon#enter wrdev, iclass 25, count 2 2006.257.07:19:49.06#ibcon#first serial, iclass 25, count 2 2006.257.07:19:49.06#ibcon#enter sib2, iclass 25, count 2 2006.257.07:19:49.06#ibcon#flushed, iclass 25, count 2 2006.257.07:19:49.06#ibcon#about to write, iclass 25, count 2 2006.257.07:19:49.06#ibcon#wrote, iclass 25, count 2 2006.257.07:19:49.06#ibcon#about to read 3, iclass 25, count 2 2006.257.07:19:49.08#ibcon#read 3, iclass 25, count 2 2006.257.07:19:49.08#ibcon#about to read 4, iclass 25, count 2 2006.257.07:19:49.08#ibcon#read 4, iclass 25, count 2 2006.257.07:19:49.08#ibcon#about to read 5, iclass 25, count 2 2006.257.07:19:49.08#ibcon#read 5, iclass 25, count 2 2006.257.07:19:49.08#ibcon#about to read 6, iclass 25, count 2 2006.257.07:19:49.08#ibcon#read 6, iclass 25, count 2 2006.257.07:19:49.08#ibcon#end of sib2, iclass 25, count 2 2006.257.07:19:49.08#ibcon#*mode == 0, iclass 25, count 2 2006.257.07:19:49.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.07:19:49.08#ibcon#[25=AT06-04\r\n] 2006.257.07:19:49.08#ibcon#*before write, iclass 25, count 2 2006.257.07:19:49.08#ibcon#enter sib2, iclass 25, count 2 2006.257.07:19:49.08#ibcon#flushed, iclass 25, count 2 2006.257.07:19:49.08#ibcon#about to write, iclass 25, count 2 2006.257.07:19:49.08#ibcon#wrote, iclass 25, count 2 2006.257.07:19:49.08#ibcon#about to read 3, iclass 25, count 2 2006.257.07:19:49.11#ibcon#read 3, iclass 25, count 2 2006.257.07:19:49.11#ibcon#about to read 4, iclass 25, count 2 2006.257.07:19:49.11#ibcon#read 4, iclass 25, count 2 2006.257.07:19:49.11#ibcon#about to read 5, iclass 25, count 2 2006.257.07:19:49.11#ibcon#read 5, iclass 25, count 2 2006.257.07:19:49.11#ibcon#about to read 6, iclass 25, count 2 2006.257.07:19:49.11#ibcon#read 6, iclass 25, count 2 2006.257.07:19:49.11#ibcon#end of sib2, iclass 25, count 2 2006.257.07:19:49.11#ibcon#*after write, iclass 25, count 2 2006.257.07:19:49.11#ibcon#*before return 0, iclass 25, count 2 2006.257.07:19:49.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:49.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:49.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.07:19:49.11#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:49.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:49.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:49.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:49.23#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:19:49.23#ibcon#first serial, iclass 25, count 0 2006.257.07:19:49.23#ibcon#enter sib2, iclass 25, count 0 2006.257.07:19:49.23#ibcon#flushed, iclass 25, count 0 2006.257.07:19:49.23#ibcon#about to write, iclass 25, count 0 2006.257.07:19:49.23#ibcon#wrote, iclass 25, count 0 2006.257.07:19:49.23#ibcon#about to read 3, iclass 25, count 0 2006.257.07:19:49.25#ibcon#read 3, iclass 25, count 0 2006.257.07:19:49.25#ibcon#about to read 4, iclass 25, count 0 2006.257.07:19:49.25#ibcon#read 4, iclass 25, count 0 2006.257.07:19:49.25#ibcon#about to read 5, iclass 25, count 0 2006.257.07:19:49.25#ibcon#read 5, iclass 25, count 0 2006.257.07:19:49.25#ibcon#about to read 6, iclass 25, count 0 2006.257.07:19:49.25#ibcon#read 6, iclass 25, count 0 2006.257.07:19:49.25#ibcon#end of sib2, iclass 25, count 0 2006.257.07:19:49.25#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:19:49.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:19:49.25#ibcon#[25=USB\r\n] 2006.257.07:19:49.25#ibcon#*before write, iclass 25, count 0 2006.257.07:19:49.25#ibcon#enter sib2, iclass 25, count 0 2006.257.07:19:49.25#ibcon#flushed, iclass 25, count 0 2006.257.07:19:49.25#ibcon#about to write, iclass 25, count 0 2006.257.07:19:49.25#ibcon#wrote, iclass 25, count 0 2006.257.07:19:49.25#ibcon#about to read 3, iclass 25, count 0 2006.257.07:19:49.28#ibcon#read 3, iclass 25, count 0 2006.257.07:19:49.28#ibcon#about to read 4, iclass 25, count 0 2006.257.07:19:49.28#ibcon#read 4, iclass 25, count 0 2006.257.07:19:49.28#ibcon#about to read 5, iclass 25, count 0 2006.257.07:19:49.28#ibcon#read 5, iclass 25, count 0 2006.257.07:19:49.28#ibcon#about to read 6, iclass 25, count 0 2006.257.07:19:49.28#ibcon#read 6, iclass 25, count 0 2006.257.07:19:49.28#ibcon#end of sib2, iclass 25, count 0 2006.257.07:19:49.28#ibcon#*after write, iclass 25, count 0 2006.257.07:19:49.28#ibcon#*before return 0, iclass 25, count 0 2006.257.07:19:49.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:49.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:49.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:19:49.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:19:49.28$vck44/valo=7,864.99 2006.257.07:19:49.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.07:19:49.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.07:19:49.28#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:49.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:49.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:49.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:49.28#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:19:49.28#ibcon#first serial, iclass 27, count 0 2006.257.07:19:49.28#ibcon#enter sib2, iclass 27, count 0 2006.257.07:19:49.28#ibcon#flushed, iclass 27, count 0 2006.257.07:19:49.28#ibcon#about to write, iclass 27, count 0 2006.257.07:19:49.28#ibcon#wrote, iclass 27, count 0 2006.257.07:19:49.28#ibcon#about to read 3, iclass 27, count 0 2006.257.07:19:49.30#ibcon#read 3, iclass 27, count 0 2006.257.07:19:49.30#ibcon#about to read 4, iclass 27, count 0 2006.257.07:19:49.30#ibcon#read 4, iclass 27, count 0 2006.257.07:19:49.30#ibcon#about to read 5, iclass 27, count 0 2006.257.07:19:49.30#ibcon#read 5, iclass 27, count 0 2006.257.07:19:49.30#ibcon#about to read 6, iclass 27, count 0 2006.257.07:19:49.30#ibcon#read 6, iclass 27, count 0 2006.257.07:19:49.30#ibcon#end of sib2, iclass 27, count 0 2006.257.07:19:49.30#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:19:49.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:19:49.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.07:19:49.30#ibcon#*before write, iclass 27, count 0 2006.257.07:19:49.30#ibcon#enter sib2, iclass 27, count 0 2006.257.07:19:49.30#ibcon#flushed, iclass 27, count 0 2006.257.07:19:49.30#ibcon#about to write, iclass 27, count 0 2006.257.07:19:49.30#ibcon#wrote, iclass 27, count 0 2006.257.07:19:49.30#ibcon#about to read 3, iclass 27, count 0 2006.257.07:19:49.34#ibcon#read 3, iclass 27, count 0 2006.257.07:19:49.34#ibcon#about to read 4, iclass 27, count 0 2006.257.07:19:49.34#ibcon#read 4, iclass 27, count 0 2006.257.07:19:49.34#ibcon#about to read 5, iclass 27, count 0 2006.257.07:19:49.34#ibcon#read 5, iclass 27, count 0 2006.257.07:19:49.34#ibcon#about to read 6, iclass 27, count 0 2006.257.07:19:49.34#ibcon#read 6, iclass 27, count 0 2006.257.07:19:49.34#ibcon#end of sib2, iclass 27, count 0 2006.257.07:19:49.34#ibcon#*after write, iclass 27, count 0 2006.257.07:19:49.34#ibcon#*before return 0, iclass 27, count 0 2006.257.07:19:49.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:49.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:49.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:19:49.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:19:49.34$vck44/va=7,4 2006.257.07:19:49.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.07:19:49.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.07:19:49.34#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:49.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:49.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:49.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:49.40#ibcon#enter wrdev, iclass 29, count 2 2006.257.07:19:49.40#ibcon#first serial, iclass 29, count 2 2006.257.07:19:49.40#ibcon#enter sib2, iclass 29, count 2 2006.257.07:19:49.40#ibcon#flushed, iclass 29, count 2 2006.257.07:19:49.40#ibcon#about to write, iclass 29, count 2 2006.257.07:19:49.40#ibcon#wrote, iclass 29, count 2 2006.257.07:19:49.40#ibcon#about to read 3, iclass 29, count 2 2006.257.07:19:49.42#ibcon#read 3, iclass 29, count 2 2006.257.07:19:49.42#ibcon#about to read 4, iclass 29, count 2 2006.257.07:19:49.42#ibcon#read 4, iclass 29, count 2 2006.257.07:19:49.42#ibcon#about to read 5, iclass 29, count 2 2006.257.07:19:49.42#ibcon#read 5, iclass 29, count 2 2006.257.07:19:49.42#ibcon#about to read 6, iclass 29, count 2 2006.257.07:19:49.42#ibcon#read 6, iclass 29, count 2 2006.257.07:19:49.42#ibcon#end of sib2, iclass 29, count 2 2006.257.07:19:49.42#ibcon#*mode == 0, iclass 29, count 2 2006.257.07:19:49.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.07:19:49.42#ibcon#[25=AT07-04\r\n] 2006.257.07:19:49.42#ibcon#*before write, iclass 29, count 2 2006.257.07:19:49.42#ibcon#enter sib2, iclass 29, count 2 2006.257.07:19:49.42#ibcon#flushed, iclass 29, count 2 2006.257.07:19:49.42#ibcon#about to write, iclass 29, count 2 2006.257.07:19:49.42#ibcon#wrote, iclass 29, count 2 2006.257.07:19:49.42#ibcon#about to read 3, iclass 29, count 2 2006.257.07:19:49.45#ibcon#read 3, iclass 29, count 2 2006.257.07:19:49.45#ibcon#about to read 4, iclass 29, count 2 2006.257.07:19:49.45#ibcon#read 4, iclass 29, count 2 2006.257.07:19:49.45#ibcon#about to read 5, iclass 29, count 2 2006.257.07:19:49.45#ibcon#read 5, iclass 29, count 2 2006.257.07:19:49.45#ibcon#about to read 6, iclass 29, count 2 2006.257.07:19:49.45#ibcon#read 6, iclass 29, count 2 2006.257.07:19:49.45#ibcon#end of sib2, iclass 29, count 2 2006.257.07:19:49.45#ibcon#*after write, iclass 29, count 2 2006.257.07:19:49.45#ibcon#*before return 0, iclass 29, count 2 2006.257.07:19:49.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:49.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:49.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.07:19:49.45#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:49.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:49.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:49.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:49.57#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:19:49.57#ibcon#first serial, iclass 29, count 0 2006.257.07:19:49.57#ibcon#enter sib2, iclass 29, count 0 2006.257.07:19:49.57#ibcon#flushed, iclass 29, count 0 2006.257.07:19:49.57#ibcon#about to write, iclass 29, count 0 2006.257.07:19:49.57#ibcon#wrote, iclass 29, count 0 2006.257.07:19:49.57#ibcon#about to read 3, iclass 29, count 0 2006.257.07:19:49.59#ibcon#read 3, iclass 29, count 0 2006.257.07:19:49.59#ibcon#about to read 4, iclass 29, count 0 2006.257.07:19:49.59#ibcon#read 4, iclass 29, count 0 2006.257.07:19:49.59#ibcon#about to read 5, iclass 29, count 0 2006.257.07:19:49.59#ibcon#read 5, iclass 29, count 0 2006.257.07:19:49.59#ibcon#about to read 6, iclass 29, count 0 2006.257.07:19:49.59#ibcon#read 6, iclass 29, count 0 2006.257.07:19:49.59#ibcon#end of sib2, iclass 29, count 0 2006.257.07:19:49.59#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:19:49.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:19:49.59#ibcon#[25=USB\r\n] 2006.257.07:19:49.59#ibcon#*before write, iclass 29, count 0 2006.257.07:19:49.59#ibcon#enter sib2, iclass 29, count 0 2006.257.07:19:49.59#ibcon#flushed, iclass 29, count 0 2006.257.07:19:49.59#ibcon#about to write, iclass 29, count 0 2006.257.07:19:49.59#ibcon#wrote, iclass 29, count 0 2006.257.07:19:49.59#ibcon#about to read 3, iclass 29, count 0 2006.257.07:19:49.62#ibcon#read 3, iclass 29, count 0 2006.257.07:19:49.62#ibcon#about to read 4, iclass 29, count 0 2006.257.07:19:49.62#ibcon#read 4, iclass 29, count 0 2006.257.07:19:49.62#ibcon#about to read 5, iclass 29, count 0 2006.257.07:19:49.62#ibcon#read 5, iclass 29, count 0 2006.257.07:19:49.62#ibcon#about to read 6, iclass 29, count 0 2006.257.07:19:49.62#ibcon#read 6, iclass 29, count 0 2006.257.07:19:49.62#ibcon#end of sib2, iclass 29, count 0 2006.257.07:19:49.62#ibcon#*after write, iclass 29, count 0 2006.257.07:19:49.62#ibcon#*before return 0, iclass 29, count 0 2006.257.07:19:49.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:49.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:49.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:19:49.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:19:49.62$vck44/valo=8,884.99 2006.257.07:19:49.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.07:19:49.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.07:19:49.62#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:49.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:49.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:49.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:49.62#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:19:49.62#ibcon#first serial, iclass 31, count 0 2006.257.07:19:49.62#ibcon#enter sib2, iclass 31, count 0 2006.257.07:19:49.62#ibcon#flushed, iclass 31, count 0 2006.257.07:19:49.62#ibcon#about to write, iclass 31, count 0 2006.257.07:19:49.62#ibcon#wrote, iclass 31, count 0 2006.257.07:19:49.62#ibcon#about to read 3, iclass 31, count 0 2006.257.07:19:49.64#ibcon#read 3, iclass 31, count 0 2006.257.07:19:49.64#ibcon#about to read 4, iclass 31, count 0 2006.257.07:19:49.64#ibcon#read 4, iclass 31, count 0 2006.257.07:19:49.64#ibcon#about to read 5, iclass 31, count 0 2006.257.07:19:49.64#ibcon#read 5, iclass 31, count 0 2006.257.07:19:49.64#ibcon#about to read 6, iclass 31, count 0 2006.257.07:19:49.64#ibcon#read 6, iclass 31, count 0 2006.257.07:19:49.64#ibcon#end of sib2, iclass 31, count 0 2006.257.07:19:49.64#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:19:49.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:19:49.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.07:19:49.64#ibcon#*before write, iclass 31, count 0 2006.257.07:19:49.64#ibcon#enter sib2, iclass 31, count 0 2006.257.07:19:49.64#ibcon#flushed, iclass 31, count 0 2006.257.07:19:49.64#ibcon#about to write, iclass 31, count 0 2006.257.07:19:49.64#ibcon#wrote, iclass 31, count 0 2006.257.07:19:49.64#ibcon#about to read 3, iclass 31, count 0 2006.257.07:19:49.68#ibcon#read 3, iclass 31, count 0 2006.257.07:19:49.68#ibcon#about to read 4, iclass 31, count 0 2006.257.07:19:49.68#ibcon#read 4, iclass 31, count 0 2006.257.07:19:49.68#ibcon#about to read 5, iclass 31, count 0 2006.257.07:19:49.68#ibcon#read 5, iclass 31, count 0 2006.257.07:19:49.68#ibcon#about to read 6, iclass 31, count 0 2006.257.07:19:49.68#ibcon#read 6, iclass 31, count 0 2006.257.07:19:49.68#ibcon#end of sib2, iclass 31, count 0 2006.257.07:19:49.68#ibcon#*after write, iclass 31, count 0 2006.257.07:19:49.68#ibcon#*before return 0, iclass 31, count 0 2006.257.07:19:49.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:49.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:49.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:19:49.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:19:49.68$vck44/va=8,4 2006.257.07:19:49.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.07:19:49.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.07:19:49.68#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:49.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:19:49.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:19:49.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:19:49.74#ibcon#enter wrdev, iclass 33, count 2 2006.257.07:19:49.74#ibcon#first serial, iclass 33, count 2 2006.257.07:19:49.74#ibcon#enter sib2, iclass 33, count 2 2006.257.07:19:49.74#ibcon#flushed, iclass 33, count 2 2006.257.07:19:49.74#ibcon#about to write, iclass 33, count 2 2006.257.07:19:49.74#ibcon#wrote, iclass 33, count 2 2006.257.07:19:49.74#ibcon#about to read 3, iclass 33, count 2 2006.257.07:19:49.76#ibcon#read 3, iclass 33, count 2 2006.257.07:19:49.76#ibcon#about to read 4, iclass 33, count 2 2006.257.07:19:49.76#ibcon#read 4, iclass 33, count 2 2006.257.07:19:49.76#ibcon#about to read 5, iclass 33, count 2 2006.257.07:19:49.76#ibcon#read 5, iclass 33, count 2 2006.257.07:19:49.76#ibcon#about to read 6, iclass 33, count 2 2006.257.07:19:49.76#ibcon#read 6, iclass 33, count 2 2006.257.07:19:49.76#ibcon#end of sib2, iclass 33, count 2 2006.257.07:19:49.76#ibcon#*mode == 0, iclass 33, count 2 2006.257.07:19:49.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.07:19:49.76#ibcon#[25=AT08-04\r\n] 2006.257.07:19:49.76#ibcon#*before write, iclass 33, count 2 2006.257.07:19:49.76#ibcon#enter sib2, iclass 33, count 2 2006.257.07:19:49.76#ibcon#flushed, iclass 33, count 2 2006.257.07:19:49.76#ibcon#about to write, iclass 33, count 2 2006.257.07:19:49.76#ibcon#wrote, iclass 33, count 2 2006.257.07:19:49.76#ibcon#about to read 3, iclass 33, count 2 2006.257.07:19:49.79#ibcon#read 3, iclass 33, count 2 2006.257.07:19:49.79#ibcon#about to read 4, iclass 33, count 2 2006.257.07:19:49.79#ibcon#read 4, iclass 33, count 2 2006.257.07:19:49.79#ibcon#about to read 5, iclass 33, count 2 2006.257.07:19:49.79#ibcon#read 5, iclass 33, count 2 2006.257.07:19:49.79#ibcon#about to read 6, iclass 33, count 2 2006.257.07:19:49.79#ibcon#read 6, iclass 33, count 2 2006.257.07:19:49.79#ibcon#end of sib2, iclass 33, count 2 2006.257.07:19:49.79#ibcon#*after write, iclass 33, count 2 2006.257.07:19:49.79#ibcon#*before return 0, iclass 33, count 2 2006.257.07:19:49.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:19:49.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:19:49.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.07:19:49.79#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:49.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:19:49.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:19:49.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:19:49.91#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:19:49.91#ibcon#first serial, iclass 33, count 0 2006.257.07:19:49.91#ibcon#enter sib2, iclass 33, count 0 2006.257.07:19:49.91#ibcon#flushed, iclass 33, count 0 2006.257.07:19:49.91#ibcon#about to write, iclass 33, count 0 2006.257.07:19:49.91#ibcon#wrote, iclass 33, count 0 2006.257.07:19:49.91#ibcon#about to read 3, iclass 33, count 0 2006.257.07:19:49.93#ibcon#read 3, iclass 33, count 0 2006.257.07:19:49.93#ibcon#about to read 4, iclass 33, count 0 2006.257.07:19:49.93#ibcon#read 4, iclass 33, count 0 2006.257.07:19:49.93#ibcon#about to read 5, iclass 33, count 0 2006.257.07:19:49.93#ibcon#read 5, iclass 33, count 0 2006.257.07:19:49.93#ibcon#about to read 6, iclass 33, count 0 2006.257.07:19:49.93#ibcon#read 6, iclass 33, count 0 2006.257.07:19:49.93#ibcon#end of sib2, iclass 33, count 0 2006.257.07:19:49.93#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:19:49.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:19:49.93#ibcon#[25=USB\r\n] 2006.257.07:19:49.93#ibcon#*before write, iclass 33, count 0 2006.257.07:19:49.93#ibcon#enter sib2, iclass 33, count 0 2006.257.07:19:49.93#ibcon#flushed, iclass 33, count 0 2006.257.07:19:49.93#ibcon#about to write, iclass 33, count 0 2006.257.07:19:49.93#ibcon#wrote, iclass 33, count 0 2006.257.07:19:49.93#ibcon#about to read 3, iclass 33, count 0 2006.257.07:19:49.96#ibcon#read 3, iclass 33, count 0 2006.257.07:19:49.96#ibcon#about to read 4, iclass 33, count 0 2006.257.07:19:49.96#ibcon#read 4, iclass 33, count 0 2006.257.07:19:49.96#ibcon#about to read 5, iclass 33, count 0 2006.257.07:19:49.96#ibcon#read 5, iclass 33, count 0 2006.257.07:19:49.96#ibcon#about to read 6, iclass 33, count 0 2006.257.07:19:49.96#ibcon#read 6, iclass 33, count 0 2006.257.07:19:49.96#ibcon#end of sib2, iclass 33, count 0 2006.257.07:19:49.96#ibcon#*after write, iclass 33, count 0 2006.257.07:19:49.96#ibcon#*before return 0, iclass 33, count 0 2006.257.07:19:49.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:19:49.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:19:49.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:19:49.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:19:49.96$vck44/vblo=1,629.99 2006.257.07:19:49.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.07:19:49.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.07:19:49.96#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:49.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:19:49.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:19:49.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:19:49.96#ibcon#enter wrdev, iclass 35, count 0 2006.257.07:19:49.96#ibcon#first serial, iclass 35, count 0 2006.257.07:19:49.96#ibcon#enter sib2, iclass 35, count 0 2006.257.07:19:49.96#ibcon#flushed, iclass 35, count 0 2006.257.07:19:49.96#ibcon#about to write, iclass 35, count 0 2006.257.07:19:49.96#ibcon#wrote, iclass 35, count 0 2006.257.07:19:49.96#ibcon#about to read 3, iclass 35, count 0 2006.257.07:19:49.98#ibcon#read 3, iclass 35, count 0 2006.257.07:19:49.98#ibcon#about to read 4, iclass 35, count 0 2006.257.07:19:49.98#ibcon#read 4, iclass 35, count 0 2006.257.07:19:49.98#ibcon#about to read 5, iclass 35, count 0 2006.257.07:19:49.98#ibcon#read 5, iclass 35, count 0 2006.257.07:19:49.98#ibcon#about to read 6, iclass 35, count 0 2006.257.07:19:49.98#ibcon#read 6, iclass 35, count 0 2006.257.07:19:49.98#ibcon#end of sib2, iclass 35, count 0 2006.257.07:19:49.98#ibcon#*mode == 0, iclass 35, count 0 2006.257.07:19:49.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.07:19:49.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.07:19:49.98#ibcon#*before write, iclass 35, count 0 2006.257.07:19:49.98#ibcon#enter sib2, iclass 35, count 0 2006.257.07:19:49.98#ibcon#flushed, iclass 35, count 0 2006.257.07:19:49.98#ibcon#about to write, iclass 35, count 0 2006.257.07:19:49.98#ibcon#wrote, iclass 35, count 0 2006.257.07:19:49.98#ibcon#about to read 3, iclass 35, count 0 2006.257.07:19:50.02#ibcon#read 3, iclass 35, count 0 2006.257.07:19:50.02#ibcon#about to read 4, iclass 35, count 0 2006.257.07:19:50.02#ibcon#read 4, iclass 35, count 0 2006.257.07:19:50.02#ibcon#about to read 5, iclass 35, count 0 2006.257.07:19:50.02#ibcon#read 5, iclass 35, count 0 2006.257.07:19:50.02#ibcon#about to read 6, iclass 35, count 0 2006.257.07:19:50.02#ibcon#read 6, iclass 35, count 0 2006.257.07:19:50.02#ibcon#end of sib2, iclass 35, count 0 2006.257.07:19:50.02#ibcon#*after write, iclass 35, count 0 2006.257.07:19:50.02#ibcon#*before return 0, iclass 35, count 0 2006.257.07:19:50.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:19:50.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:19:50.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.07:19:50.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.07:19:50.02$vck44/vb=1,4 2006.257.07:19:50.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.07:19:50.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.07:19:50.02#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:50.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:19:50.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:19:50.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:19:50.02#ibcon#enter wrdev, iclass 37, count 2 2006.257.07:19:50.02#ibcon#first serial, iclass 37, count 2 2006.257.07:19:50.02#ibcon#enter sib2, iclass 37, count 2 2006.257.07:19:50.02#ibcon#flushed, iclass 37, count 2 2006.257.07:19:50.02#ibcon#about to write, iclass 37, count 2 2006.257.07:19:50.02#ibcon#wrote, iclass 37, count 2 2006.257.07:19:50.02#ibcon#about to read 3, iclass 37, count 2 2006.257.07:19:50.04#ibcon#read 3, iclass 37, count 2 2006.257.07:19:50.04#ibcon#about to read 4, iclass 37, count 2 2006.257.07:19:50.04#ibcon#read 4, iclass 37, count 2 2006.257.07:19:50.04#ibcon#about to read 5, iclass 37, count 2 2006.257.07:19:50.04#ibcon#read 5, iclass 37, count 2 2006.257.07:19:50.04#ibcon#about to read 6, iclass 37, count 2 2006.257.07:19:50.04#ibcon#read 6, iclass 37, count 2 2006.257.07:19:50.04#ibcon#end of sib2, iclass 37, count 2 2006.257.07:19:50.04#ibcon#*mode == 0, iclass 37, count 2 2006.257.07:19:50.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.07:19:50.04#ibcon#[27=AT01-04\r\n] 2006.257.07:19:50.04#ibcon#*before write, iclass 37, count 2 2006.257.07:19:50.04#ibcon#enter sib2, iclass 37, count 2 2006.257.07:19:50.04#ibcon#flushed, iclass 37, count 2 2006.257.07:19:50.04#ibcon#about to write, iclass 37, count 2 2006.257.07:19:50.04#ibcon#wrote, iclass 37, count 2 2006.257.07:19:50.04#ibcon#about to read 3, iclass 37, count 2 2006.257.07:19:50.07#ibcon#read 3, iclass 37, count 2 2006.257.07:19:50.07#ibcon#about to read 4, iclass 37, count 2 2006.257.07:19:50.07#ibcon#read 4, iclass 37, count 2 2006.257.07:19:50.07#ibcon#about to read 5, iclass 37, count 2 2006.257.07:19:50.07#ibcon#read 5, iclass 37, count 2 2006.257.07:19:50.07#ibcon#about to read 6, iclass 37, count 2 2006.257.07:19:50.07#ibcon#read 6, iclass 37, count 2 2006.257.07:19:50.07#ibcon#end of sib2, iclass 37, count 2 2006.257.07:19:50.07#ibcon#*after write, iclass 37, count 2 2006.257.07:19:50.07#ibcon#*before return 0, iclass 37, count 2 2006.257.07:19:50.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:19:50.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:19:50.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.07:19:50.07#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:50.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:19:50.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:19:50.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:19:50.19#ibcon#enter wrdev, iclass 37, count 0 2006.257.07:19:50.19#ibcon#first serial, iclass 37, count 0 2006.257.07:19:50.19#ibcon#enter sib2, iclass 37, count 0 2006.257.07:19:50.19#ibcon#flushed, iclass 37, count 0 2006.257.07:19:50.19#ibcon#about to write, iclass 37, count 0 2006.257.07:19:50.19#ibcon#wrote, iclass 37, count 0 2006.257.07:19:50.19#ibcon#about to read 3, iclass 37, count 0 2006.257.07:19:50.21#ibcon#read 3, iclass 37, count 0 2006.257.07:19:50.21#ibcon#about to read 4, iclass 37, count 0 2006.257.07:19:50.21#ibcon#read 4, iclass 37, count 0 2006.257.07:19:50.21#ibcon#about to read 5, iclass 37, count 0 2006.257.07:19:50.21#ibcon#read 5, iclass 37, count 0 2006.257.07:19:50.21#ibcon#about to read 6, iclass 37, count 0 2006.257.07:19:50.21#ibcon#read 6, iclass 37, count 0 2006.257.07:19:50.21#ibcon#end of sib2, iclass 37, count 0 2006.257.07:19:50.21#ibcon#*mode == 0, iclass 37, count 0 2006.257.07:19:50.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.07:19:50.21#ibcon#[27=USB\r\n] 2006.257.07:19:50.21#ibcon#*before write, iclass 37, count 0 2006.257.07:19:50.21#ibcon#enter sib2, iclass 37, count 0 2006.257.07:19:50.21#ibcon#flushed, iclass 37, count 0 2006.257.07:19:50.21#ibcon#about to write, iclass 37, count 0 2006.257.07:19:50.21#ibcon#wrote, iclass 37, count 0 2006.257.07:19:50.21#ibcon#about to read 3, iclass 37, count 0 2006.257.07:19:50.24#ibcon#read 3, iclass 37, count 0 2006.257.07:19:50.24#ibcon#about to read 4, iclass 37, count 0 2006.257.07:19:50.24#ibcon#read 4, iclass 37, count 0 2006.257.07:19:50.24#ibcon#about to read 5, iclass 37, count 0 2006.257.07:19:50.24#ibcon#read 5, iclass 37, count 0 2006.257.07:19:50.24#ibcon#about to read 6, iclass 37, count 0 2006.257.07:19:50.24#ibcon#read 6, iclass 37, count 0 2006.257.07:19:50.24#ibcon#end of sib2, iclass 37, count 0 2006.257.07:19:50.24#ibcon#*after write, iclass 37, count 0 2006.257.07:19:50.24#ibcon#*before return 0, iclass 37, count 0 2006.257.07:19:50.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:19:50.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:19:50.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.07:19:50.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.07:19:50.24$vck44/vblo=2,634.99 2006.257.07:19:50.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.07:19:50.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.07:19:50.24#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:50.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:50.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:50.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:50.24#ibcon#enter wrdev, iclass 39, count 0 2006.257.07:19:50.24#ibcon#first serial, iclass 39, count 0 2006.257.07:19:50.24#ibcon#enter sib2, iclass 39, count 0 2006.257.07:19:50.24#ibcon#flushed, iclass 39, count 0 2006.257.07:19:50.24#ibcon#about to write, iclass 39, count 0 2006.257.07:19:50.24#ibcon#wrote, iclass 39, count 0 2006.257.07:19:50.24#ibcon#about to read 3, iclass 39, count 0 2006.257.07:19:50.26#ibcon#read 3, iclass 39, count 0 2006.257.07:19:50.26#ibcon#about to read 4, iclass 39, count 0 2006.257.07:19:50.26#ibcon#read 4, iclass 39, count 0 2006.257.07:19:50.26#ibcon#about to read 5, iclass 39, count 0 2006.257.07:19:50.26#ibcon#read 5, iclass 39, count 0 2006.257.07:19:50.26#ibcon#about to read 6, iclass 39, count 0 2006.257.07:19:50.26#ibcon#read 6, iclass 39, count 0 2006.257.07:19:50.26#ibcon#end of sib2, iclass 39, count 0 2006.257.07:19:50.26#ibcon#*mode == 0, iclass 39, count 0 2006.257.07:19:50.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.07:19:50.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.07:19:50.26#ibcon#*before write, iclass 39, count 0 2006.257.07:19:50.26#ibcon#enter sib2, iclass 39, count 0 2006.257.07:19:50.26#ibcon#flushed, iclass 39, count 0 2006.257.07:19:50.26#ibcon#about to write, iclass 39, count 0 2006.257.07:19:50.26#ibcon#wrote, iclass 39, count 0 2006.257.07:19:50.26#ibcon#about to read 3, iclass 39, count 0 2006.257.07:19:50.30#ibcon#read 3, iclass 39, count 0 2006.257.07:19:50.30#ibcon#about to read 4, iclass 39, count 0 2006.257.07:19:50.30#ibcon#read 4, iclass 39, count 0 2006.257.07:19:50.30#ibcon#about to read 5, iclass 39, count 0 2006.257.07:19:50.30#ibcon#read 5, iclass 39, count 0 2006.257.07:19:50.30#ibcon#about to read 6, iclass 39, count 0 2006.257.07:19:50.30#ibcon#read 6, iclass 39, count 0 2006.257.07:19:50.30#ibcon#end of sib2, iclass 39, count 0 2006.257.07:19:50.30#ibcon#*after write, iclass 39, count 0 2006.257.07:19:50.30#ibcon#*before return 0, iclass 39, count 0 2006.257.07:19:50.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:50.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:19:50.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.07:19:50.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.07:19:50.30$vck44/vb=2,5 2006.257.07:19:50.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.07:19:50.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.07:19:50.30#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:50.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:50.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:50.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:50.36#ibcon#enter wrdev, iclass 3, count 2 2006.257.07:19:50.36#ibcon#first serial, iclass 3, count 2 2006.257.07:19:50.36#ibcon#enter sib2, iclass 3, count 2 2006.257.07:19:50.36#ibcon#flushed, iclass 3, count 2 2006.257.07:19:50.36#ibcon#about to write, iclass 3, count 2 2006.257.07:19:50.36#ibcon#wrote, iclass 3, count 2 2006.257.07:19:50.36#ibcon#about to read 3, iclass 3, count 2 2006.257.07:19:50.38#ibcon#read 3, iclass 3, count 2 2006.257.07:19:50.38#ibcon#about to read 4, iclass 3, count 2 2006.257.07:19:50.38#ibcon#read 4, iclass 3, count 2 2006.257.07:19:50.38#ibcon#about to read 5, iclass 3, count 2 2006.257.07:19:50.38#ibcon#read 5, iclass 3, count 2 2006.257.07:19:50.38#ibcon#about to read 6, iclass 3, count 2 2006.257.07:19:50.38#ibcon#read 6, iclass 3, count 2 2006.257.07:19:50.38#ibcon#end of sib2, iclass 3, count 2 2006.257.07:19:50.38#ibcon#*mode == 0, iclass 3, count 2 2006.257.07:19:50.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.07:19:50.38#ibcon#[27=AT02-05\r\n] 2006.257.07:19:50.38#ibcon#*before write, iclass 3, count 2 2006.257.07:19:50.38#ibcon#enter sib2, iclass 3, count 2 2006.257.07:19:50.38#ibcon#flushed, iclass 3, count 2 2006.257.07:19:50.38#ibcon#about to write, iclass 3, count 2 2006.257.07:19:50.38#ibcon#wrote, iclass 3, count 2 2006.257.07:19:50.38#ibcon#about to read 3, iclass 3, count 2 2006.257.07:19:50.41#ibcon#read 3, iclass 3, count 2 2006.257.07:19:50.41#ibcon#about to read 4, iclass 3, count 2 2006.257.07:19:50.41#ibcon#read 4, iclass 3, count 2 2006.257.07:19:50.41#ibcon#about to read 5, iclass 3, count 2 2006.257.07:19:50.41#ibcon#read 5, iclass 3, count 2 2006.257.07:19:50.41#ibcon#about to read 6, iclass 3, count 2 2006.257.07:19:50.41#ibcon#read 6, iclass 3, count 2 2006.257.07:19:50.41#ibcon#end of sib2, iclass 3, count 2 2006.257.07:19:50.41#ibcon#*after write, iclass 3, count 2 2006.257.07:19:50.41#ibcon#*before return 0, iclass 3, count 2 2006.257.07:19:50.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:50.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:19:50.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.07:19:50.41#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:50.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:50.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:50.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:50.53#ibcon#enter wrdev, iclass 3, count 0 2006.257.07:19:50.53#ibcon#first serial, iclass 3, count 0 2006.257.07:19:50.53#ibcon#enter sib2, iclass 3, count 0 2006.257.07:19:50.53#ibcon#flushed, iclass 3, count 0 2006.257.07:19:50.53#ibcon#about to write, iclass 3, count 0 2006.257.07:19:50.53#ibcon#wrote, iclass 3, count 0 2006.257.07:19:50.53#ibcon#about to read 3, iclass 3, count 0 2006.257.07:19:50.55#ibcon#read 3, iclass 3, count 0 2006.257.07:19:50.55#ibcon#about to read 4, iclass 3, count 0 2006.257.07:19:50.55#ibcon#read 4, iclass 3, count 0 2006.257.07:19:50.55#ibcon#about to read 5, iclass 3, count 0 2006.257.07:19:50.55#ibcon#read 5, iclass 3, count 0 2006.257.07:19:50.55#ibcon#about to read 6, iclass 3, count 0 2006.257.07:19:50.55#ibcon#read 6, iclass 3, count 0 2006.257.07:19:50.55#ibcon#end of sib2, iclass 3, count 0 2006.257.07:19:50.55#ibcon#*mode == 0, iclass 3, count 0 2006.257.07:19:50.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.07:19:50.55#ibcon#[27=USB\r\n] 2006.257.07:19:50.55#ibcon#*before write, iclass 3, count 0 2006.257.07:19:50.55#ibcon#enter sib2, iclass 3, count 0 2006.257.07:19:50.55#ibcon#flushed, iclass 3, count 0 2006.257.07:19:50.55#ibcon#about to write, iclass 3, count 0 2006.257.07:19:50.55#ibcon#wrote, iclass 3, count 0 2006.257.07:19:50.55#ibcon#about to read 3, iclass 3, count 0 2006.257.07:19:50.58#ibcon#read 3, iclass 3, count 0 2006.257.07:19:50.58#ibcon#about to read 4, iclass 3, count 0 2006.257.07:19:50.58#ibcon#read 4, iclass 3, count 0 2006.257.07:19:50.58#ibcon#about to read 5, iclass 3, count 0 2006.257.07:19:50.58#ibcon#read 5, iclass 3, count 0 2006.257.07:19:50.58#ibcon#about to read 6, iclass 3, count 0 2006.257.07:19:50.58#ibcon#read 6, iclass 3, count 0 2006.257.07:19:50.58#ibcon#end of sib2, iclass 3, count 0 2006.257.07:19:50.58#ibcon#*after write, iclass 3, count 0 2006.257.07:19:50.58#ibcon#*before return 0, iclass 3, count 0 2006.257.07:19:50.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:50.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:19:50.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.07:19:50.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.07:19:50.58$vck44/vblo=3,649.99 2006.257.07:19:50.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.07:19:50.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.07:19:50.58#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:50.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:50.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:50.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:50.58#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:19:50.58#ibcon#first serial, iclass 5, count 0 2006.257.07:19:50.58#ibcon#enter sib2, iclass 5, count 0 2006.257.07:19:50.58#ibcon#flushed, iclass 5, count 0 2006.257.07:19:50.58#ibcon#about to write, iclass 5, count 0 2006.257.07:19:50.58#ibcon#wrote, iclass 5, count 0 2006.257.07:19:50.58#ibcon#about to read 3, iclass 5, count 0 2006.257.07:19:50.60#ibcon#read 3, iclass 5, count 0 2006.257.07:19:50.60#ibcon#about to read 4, iclass 5, count 0 2006.257.07:19:50.60#ibcon#read 4, iclass 5, count 0 2006.257.07:19:50.60#ibcon#about to read 5, iclass 5, count 0 2006.257.07:19:50.60#ibcon#read 5, iclass 5, count 0 2006.257.07:19:50.60#ibcon#about to read 6, iclass 5, count 0 2006.257.07:19:50.60#ibcon#read 6, iclass 5, count 0 2006.257.07:19:50.60#ibcon#end of sib2, iclass 5, count 0 2006.257.07:19:50.60#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:19:50.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:19:50.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.07:19:50.60#ibcon#*before write, iclass 5, count 0 2006.257.07:19:50.60#ibcon#enter sib2, iclass 5, count 0 2006.257.07:19:50.60#ibcon#flushed, iclass 5, count 0 2006.257.07:19:50.60#ibcon#about to write, iclass 5, count 0 2006.257.07:19:50.60#ibcon#wrote, iclass 5, count 0 2006.257.07:19:50.60#ibcon#about to read 3, iclass 5, count 0 2006.257.07:19:50.64#ibcon#read 3, iclass 5, count 0 2006.257.07:19:50.64#ibcon#about to read 4, iclass 5, count 0 2006.257.07:19:50.64#ibcon#read 4, iclass 5, count 0 2006.257.07:19:50.64#ibcon#about to read 5, iclass 5, count 0 2006.257.07:19:50.64#ibcon#read 5, iclass 5, count 0 2006.257.07:19:50.64#ibcon#about to read 6, iclass 5, count 0 2006.257.07:19:50.64#ibcon#read 6, iclass 5, count 0 2006.257.07:19:50.64#ibcon#end of sib2, iclass 5, count 0 2006.257.07:19:50.64#ibcon#*after write, iclass 5, count 0 2006.257.07:19:50.64#ibcon#*before return 0, iclass 5, count 0 2006.257.07:19:50.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:50.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:19:50.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:19:50.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:19:50.64$vck44/vb=3,4 2006.257.07:19:50.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.07:19:50.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.07:19:50.64#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:50.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:50.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:50.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:50.70#ibcon#enter wrdev, iclass 7, count 2 2006.257.07:19:50.70#ibcon#first serial, iclass 7, count 2 2006.257.07:19:50.70#ibcon#enter sib2, iclass 7, count 2 2006.257.07:19:50.70#ibcon#flushed, iclass 7, count 2 2006.257.07:19:50.70#ibcon#about to write, iclass 7, count 2 2006.257.07:19:50.70#ibcon#wrote, iclass 7, count 2 2006.257.07:19:50.70#ibcon#about to read 3, iclass 7, count 2 2006.257.07:19:50.72#ibcon#read 3, iclass 7, count 2 2006.257.07:19:50.72#ibcon#about to read 4, iclass 7, count 2 2006.257.07:19:50.72#ibcon#read 4, iclass 7, count 2 2006.257.07:19:50.72#ibcon#about to read 5, iclass 7, count 2 2006.257.07:19:50.72#ibcon#read 5, iclass 7, count 2 2006.257.07:19:50.72#ibcon#about to read 6, iclass 7, count 2 2006.257.07:19:50.72#ibcon#read 6, iclass 7, count 2 2006.257.07:19:50.72#ibcon#end of sib2, iclass 7, count 2 2006.257.07:19:50.72#ibcon#*mode == 0, iclass 7, count 2 2006.257.07:19:50.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.07:19:50.72#ibcon#[27=AT03-04\r\n] 2006.257.07:19:50.72#ibcon#*before write, iclass 7, count 2 2006.257.07:19:50.72#ibcon#enter sib2, iclass 7, count 2 2006.257.07:19:50.72#ibcon#flushed, iclass 7, count 2 2006.257.07:19:50.72#ibcon#about to write, iclass 7, count 2 2006.257.07:19:50.72#ibcon#wrote, iclass 7, count 2 2006.257.07:19:50.72#ibcon#about to read 3, iclass 7, count 2 2006.257.07:19:50.75#ibcon#read 3, iclass 7, count 2 2006.257.07:19:50.75#ibcon#about to read 4, iclass 7, count 2 2006.257.07:19:50.75#ibcon#read 4, iclass 7, count 2 2006.257.07:19:50.75#ibcon#about to read 5, iclass 7, count 2 2006.257.07:19:50.75#ibcon#read 5, iclass 7, count 2 2006.257.07:19:50.75#ibcon#about to read 6, iclass 7, count 2 2006.257.07:19:50.75#ibcon#read 6, iclass 7, count 2 2006.257.07:19:50.75#ibcon#end of sib2, iclass 7, count 2 2006.257.07:19:50.75#ibcon#*after write, iclass 7, count 2 2006.257.07:19:50.75#ibcon#*before return 0, iclass 7, count 2 2006.257.07:19:50.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:50.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:19:50.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.07:19:50.75#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:50.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:50.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:50.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:50.87#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:19:50.87#ibcon#first serial, iclass 7, count 0 2006.257.07:19:50.87#ibcon#enter sib2, iclass 7, count 0 2006.257.07:19:50.87#ibcon#flushed, iclass 7, count 0 2006.257.07:19:50.87#ibcon#about to write, iclass 7, count 0 2006.257.07:19:50.87#ibcon#wrote, iclass 7, count 0 2006.257.07:19:50.87#ibcon#about to read 3, iclass 7, count 0 2006.257.07:19:50.89#ibcon#read 3, iclass 7, count 0 2006.257.07:19:50.89#ibcon#about to read 4, iclass 7, count 0 2006.257.07:19:50.89#ibcon#read 4, iclass 7, count 0 2006.257.07:19:50.89#ibcon#about to read 5, iclass 7, count 0 2006.257.07:19:50.89#ibcon#read 5, iclass 7, count 0 2006.257.07:19:50.89#ibcon#about to read 6, iclass 7, count 0 2006.257.07:19:50.89#ibcon#read 6, iclass 7, count 0 2006.257.07:19:50.89#ibcon#end of sib2, iclass 7, count 0 2006.257.07:19:50.89#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:19:50.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:19:50.89#ibcon#[27=USB\r\n] 2006.257.07:19:50.89#ibcon#*before write, iclass 7, count 0 2006.257.07:19:50.89#ibcon#enter sib2, iclass 7, count 0 2006.257.07:19:50.89#ibcon#flushed, iclass 7, count 0 2006.257.07:19:50.89#ibcon#about to write, iclass 7, count 0 2006.257.07:19:50.89#ibcon#wrote, iclass 7, count 0 2006.257.07:19:50.89#ibcon#about to read 3, iclass 7, count 0 2006.257.07:19:50.92#ibcon#read 3, iclass 7, count 0 2006.257.07:19:50.92#ibcon#about to read 4, iclass 7, count 0 2006.257.07:19:50.92#ibcon#read 4, iclass 7, count 0 2006.257.07:19:50.92#ibcon#about to read 5, iclass 7, count 0 2006.257.07:19:50.92#ibcon#read 5, iclass 7, count 0 2006.257.07:19:50.92#ibcon#about to read 6, iclass 7, count 0 2006.257.07:19:50.92#ibcon#read 6, iclass 7, count 0 2006.257.07:19:50.92#ibcon#end of sib2, iclass 7, count 0 2006.257.07:19:50.92#ibcon#*after write, iclass 7, count 0 2006.257.07:19:50.92#ibcon#*before return 0, iclass 7, count 0 2006.257.07:19:50.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:50.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:19:50.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:19:50.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:19:50.92$vck44/vblo=4,679.99 2006.257.07:19:50.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.07:19:50.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.07:19:50.92#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:50.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:50.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:50.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:50.92#ibcon#enter wrdev, iclass 11, count 0 2006.257.07:19:50.92#ibcon#first serial, iclass 11, count 0 2006.257.07:19:50.92#ibcon#enter sib2, iclass 11, count 0 2006.257.07:19:50.92#ibcon#flushed, iclass 11, count 0 2006.257.07:19:50.92#ibcon#about to write, iclass 11, count 0 2006.257.07:19:50.92#ibcon#wrote, iclass 11, count 0 2006.257.07:19:50.92#ibcon#about to read 3, iclass 11, count 0 2006.257.07:19:50.94#ibcon#read 3, iclass 11, count 0 2006.257.07:19:50.94#ibcon#about to read 4, iclass 11, count 0 2006.257.07:19:50.94#ibcon#read 4, iclass 11, count 0 2006.257.07:19:50.94#ibcon#about to read 5, iclass 11, count 0 2006.257.07:19:50.94#ibcon#read 5, iclass 11, count 0 2006.257.07:19:50.94#ibcon#about to read 6, iclass 11, count 0 2006.257.07:19:50.94#ibcon#read 6, iclass 11, count 0 2006.257.07:19:50.94#ibcon#end of sib2, iclass 11, count 0 2006.257.07:19:50.94#ibcon#*mode == 0, iclass 11, count 0 2006.257.07:19:50.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.07:19:50.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.07:19:50.94#ibcon#*before write, iclass 11, count 0 2006.257.07:19:50.94#ibcon#enter sib2, iclass 11, count 0 2006.257.07:19:50.94#ibcon#flushed, iclass 11, count 0 2006.257.07:19:50.94#ibcon#about to write, iclass 11, count 0 2006.257.07:19:50.94#ibcon#wrote, iclass 11, count 0 2006.257.07:19:50.94#ibcon#about to read 3, iclass 11, count 0 2006.257.07:19:50.98#ibcon#read 3, iclass 11, count 0 2006.257.07:19:50.98#ibcon#about to read 4, iclass 11, count 0 2006.257.07:19:50.98#ibcon#read 4, iclass 11, count 0 2006.257.07:19:50.98#ibcon#about to read 5, iclass 11, count 0 2006.257.07:19:50.98#ibcon#read 5, iclass 11, count 0 2006.257.07:19:50.98#ibcon#about to read 6, iclass 11, count 0 2006.257.07:19:50.98#ibcon#read 6, iclass 11, count 0 2006.257.07:19:50.98#ibcon#end of sib2, iclass 11, count 0 2006.257.07:19:50.98#ibcon#*after write, iclass 11, count 0 2006.257.07:19:50.98#ibcon#*before return 0, iclass 11, count 0 2006.257.07:19:50.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:50.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:19:50.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.07:19:50.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.07:19:50.98$vck44/vb=4,5 2006.257.07:19:50.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.07:19:50.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.07:19:50.98#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:50.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:51.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:51.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:51.04#ibcon#enter wrdev, iclass 13, count 2 2006.257.07:19:51.04#ibcon#first serial, iclass 13, count 2 2006.257.07:19:51.04#ibcon#enter sib2, iclass 13, count 2 2006.257.07:19:51.04#ibcon#flushed, iclass 13, count 2 2006.257.07:19:51.04#ibcon#about to write, iclass 13, count 2 2006.257.07:19:51.04#ibcon#wrote, iclass 13, count 2 2006.257.07:19:51.04#ibcon#about to read 3, iclass 13, count 2 2006.257.07:19:51.06#ibcon#read 3, iclass 13, count 2 2006.257.07:19:51.06#ibcon#about to read 4, iclass 13, count 2 2006.257.07:19:51.06#ibcon#read 4, iclass 13, count 2 2006.257.07:19:51.06#ibcon#about to read 5, iclass 13, count 2 2006.257.07:19:51.06#ibcon#read 5, iclass 13, count 2 2006.257.07:19:51.06#ibcon#about to read 6, iclass 13, count 2 2006.257.07:19:51.06#ibcon#read 6, iclass 13, count 2 2006.257.07:19:51.06#ibcon#end of sib2, iclass 13, count 2 2006.257.07:19:51.06#ibcon#*mode == 0, iclass 13, count 2 2006.257.07:19:51.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.07:19:51.06#ibcon#[27=AT04-05\r\n] 2006.257.07:19:51.06#ibcon#*before write, iclass 13, count 2 2006.257.07:19:51.06#ibcon#enter sib2, iclass 13, count 2 2006.257.07:19:51.06#ibcon#flushed, iclass 13, count 2 2006.257.07:19:51.06#ibcon#about to write, iclass 13, count 2 2006.257.07:19:51.06#ibcon#wrote, iclass 13, count 2 2006.257.07:19:51.06#ibcon#about to read 3, iclass 13, count 2 2006.257.07:19:51.09#ibcon#read 3, iclass 13, count 2 2006.257.07:19:51.09#ibcon#about to read 4, iclass 13, count 2 2006.257.07:19:51.09#ibcon#read 4, iclass 13, count 2 2006.257.07:19:51.09#ibcon#about to read 5, iclass 13, count 2 2006.257.07:19:51.09#ibcon#read 5, iclass 13, count 2 2006.257.07:19:51.09#ibcon#about to read 6, iclass 13, count 2 2006.257.07:19:51.09#ibcon#read 6, iclass 13, count 2 2006.257.07:19:51.09#ibcon#end of sib2, iclass 13, count 2 2006.257.07:19:51.09#ibcon#*after write, iclass 13, count 2 2006.257.07:19:51.09#ibcon#*before return 0, iclass 13, count 2 2006.257.07:19:51.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:51.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:19:51.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.07:19:51.09#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:51.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:51.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:51.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:51.21#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:19:51.21#ibcon#first serial, iclass 13, count 0 2006.257.07:19:51.21#ibcon#enter sib2, iclass 13, count 0 2006.257.07:19:51.21#ibcon#flushed, iclass 13, count 0 2006.257.07:19:51.21#ibcon#about to write, iclass 13, count 0 2006.257.07:19:51.21#ibcon#wrote, iclass 13, count 0 2006.257.07:19:51.21#ibcon#about to read 3, iclass 13, count 0 2006.257.07:19:51.23#ibcon#read 3, iclass 13, count 0 2006.257.07:19:51.23#ibcon#about to read 4, iclass 13, count 0 2006.257.07:19:51.23#ibcon#read 4, iclass 13, count 0 2006.257.07:19:51.23#ibcon#about to read 5, iclass 13, count 0 2006.257.07:19:51.23#ibcon#read 5, iclass 13, count 0 2006.257.07:19:51.23#ibcon#about to read 6, iclass 13, count 0 2006.257.07:19:51.23#ibcon#read 6, iclass 13, count 0 2006.257.07:19:51.23#ibcon#end of sib2, iclass 13, count 0 2006.257.07:19:51.23#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:19:51.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:19:51.23#ibcon#[27=USB\r\n] 2006.257.07:19:51.23#ibcon#*before write, iclass 13, count 0 2006.257.07:19:51.23#ibcon#enter sib2, iclass 13, count 0 2006.257.07:19:51.23#ibcon#flushed, iclass 13, count 0 2006.257.07:19:51.23#ibcon#about to write, iclass 13, count 0 2006.257.07:19:51.23#ibcon#wrote, iclass 13, count 0 2006.257.07:19:51.23#ibcon#about to read 3, iclass 13, count 0 2006.257.07:19:51.26#ibcon#read 3, iclass 13, count 0 2006.257.07:19:51.26#ibcon#about to read 4, iclass 13, count 0 2006.257.07:19:51.26#ibcon#read 4, iclass 13, count 0 2006.257.07:19:51.26#ibcon#about to read 5, iclass 13, count 0 2006.257.07:19:51.26#ibcon#read 5, iclass 13, count 0 2006.257.07:19:51.26#ibcon#about to read 6, iclass 13, count 0 2006.257.07:19:51.26#ibcon#read 6, iclass 13, count 0 2006.257.07:19:51.26#ibcon#end of sib2, iclass 13, count 0 2006.257.07:19:51.26#ibcon#*after write, iclass 13, count 0 2006.257.07:19:51.26#ibcon#*before return 0, iclass 13, count 0 2006.257.07:19:51.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:51.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:19:51.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:19:51.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:19:51.26$vck44/vblo=5,709.99 2006.257.07:19:51.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.07:19:51.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.07:19:51.26#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:51.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:51.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:51.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:51.26#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:19:51.26#ibcon#first serial, iclass 15, count 0 2006.257.07:19:51.26#ibcon#enter sib2, iclass 15, count 0 2006.257.07:19:51.26#ibcon#flushed, iclass 15, count 0 2006.257.07:19:51.26#ibcon#about to write, iclass 15, count 0 2006.257.07:19:51.26#ibcon#wrote, iclass 15, count 0 2006.257.07:19:51.26#ibcon#about to read 3, iclass 15, count 0 2006.257.07:19:51.28#ibcon#read 3, iclass 15, count 0 2006.257.07:19:51.28#ibcon#about to read 4, iclass 15, count 0 2006.257.07:19:51.28#ibcon#read 4, iclass 15, count 0 2006.257.07:19:51.28#ibcon#about to read 5, iclass 15, count 0 2006.257.07:19:51.28#ibcon#read 5, iclass 15, count 0 2006.257.07:19:51.28#ibcon#about to read 6, iclass 15, count 0 2006.257.07:19:51.28#ibcon#read 6, iclass 15, count 0 2006.257.07:19:51.28#ibcon#end of sib2, iclass 15, count 0 2006.257.07:19:51.28#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:19:51.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:19:51.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.07:19:51.28#ibcon#*before write, iclass 15, count 0 2006.257.07:19:51.28#ibcon#enter sib2, iclass 15, count 0 2006.257.07:19:51.28#ibcon#flushed, iclass 15, count 0 2006.257.07:19:51.28#ibcon#about to write, iclass 15, count 0 2006.257.07:19:51.28#ibcon#wrote, iclass 15, count 0 2006.257.07:19:51.28#ibcon#about to read 3, iclass 15, count 0 2006.257.07:19:51.32#ibcon#read 3, iclass 15, count 0 2006.257.07:19:51.32#ibcon#about to read 4, iclass 15, count 0 2006.257.07:19:51.32#ibcon#read 4, iclass 15, count 0 2006.257.07:19:51.32#ibcon#about to read 5, iclass 15, count 0 2006.257.07:19:51.32#ibcon#read 5, iclass 15, count 0 2006.257.07:19:51.32#ibcon#about to read 6, iclass 15, count 0 2006.257.07:19:51.32#ibcon#read 6, iclass 15, count 0 2006.257.07:19:51.32#ibcon#end of sib2, iclass 15, count 0 2006.257.07:19:51.32#ibcon#*after write, iclass 15, count 0 2006.257.07:19:51.32#ibcon#*before return 0, iclass 15, count 0 2006.257.07:19:51.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:51.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:19:51.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:19:51.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:19:51.32$vck44/vb=5,4 2006.257.07:19:51.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.07:19:51.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.07:19:51.32#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:51.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:51.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:51.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:51.38#ibcon#enter wrdev, iclass 17, count 2 2006.257.07:19:51.38#ibcon#first serial, iclass 17, count 2 2006.257.07:19:51.38#ibcon#enter sib2, iclass 17, count 2 2006.257.07:19:51.38#ibcon#flushed, iclass 17, count 2 2006.257.07:19:51.38#ibcon#about to write, iclass 17, count 2 2006.257.07:19:51.38#ibcon#wrote, iclass 17, count 2 2006.257.07:19:51.38#ibcon#about to read 3, iclass 17, count 2 2006.257.07:19:51.40#ibcon#read 3, iclass 17, count 2 2006.257.07:19:51.40#ibcon#about to read 4, iclass 17, count 2 2006.257.07:19:51.40#ibcon#read 4, iclass 17, count 2 2006.257.07:19:51.40#ibcon#about to read 5, iclass 17, count 2 2006.257.07:19:51.40#ibcon#read 5, iclass 17, count 2 2006.257.07:19:51.40#ibcon#about to read 6, iclass 17, count 2 2006.257.07:19:51.40#ibcon#read 6, iclass 17, count 2 2006.257.07:19:51.40#ibcon#end of sib2, iclass 17, count 2 2006.257.07:19:51.40#ibcon#*mode == 0, iclass 17, count 2 2006.257.07:19:51.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.07:19:51.40#ibcon#[27=AT05-04\r\n] 2006.257.07:19:51.40#ibcon#*before write, iclass 17, count 2 2006.257.07:19:51.40#ibcon#enter sib2, iclass 17, count 2 2006.257.07:19:51.40#ibcon#flushed, iclass 17, count 2 2006.257.07:19:51.40#ibcon#about to write, iclass 17, count 2 2006.257.07:19:51.40#ibcon#wrote, iclass 17, count 2 2006.257.07:19:51.40#ibcon#about to read 3, iclass 17, count 2 2006.257.07:19:51.43#ibcon#read 3, iclass 17, count 2 2006.257.07:19:51.43#ibcon#about to read 4, iclass 17, count 2 2006.257.07:19:51.43#ibcon#read 4, iclass 17, count 2 2006.257.07:19:51.43#ibcon#about to read 5, iclass 17, count 2 2006.257.07:19:51.43#ibcon#read 5, iclass 17, count 2 2006.257.07:19:51.43#ibcon#about to read 6, iclass 17, count 2 2006.257.07:19:51.43#ibcon#read 6, iclass 17, count 2 2006.257.07:19:51.43#ibcon#end of sib2, iclass 17, count 2 2006.257.07:19:51.43#ibcon#*after write, iclass 17, count 2 2006.257.07:19:51.43#ibcon#*before return 0, iclass 17, count 2 2006.257.07:19:51.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:51.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:19:51.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.07:19:51.43#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:51.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:51.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:51.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:51.55#ibcon#enter wrdev, iclass 17, count 0 2006.257.07:19:51.55#ibcon#first serial, iclass 17, count 0 2006.257.07:19:51.55#ibcon#enter sib2, iclass 17, count 0 2006.257.07:19:51.55#ibcon#flushed, iclass 17, count 0 2006.257.07:19:51.55#ibcon#about to write, iclass 17, count 0 2006.257.07:19:51.55#ibcon#wrote, iclass 17, count 0 2006.257.07:19:51.55#ibcon#about to read 3, iclass 17, count 0 2006.257.07:19:51.57#ibcon#read 3, iclass 17, count 0 2006.257.07:19:51.57#ibcon#about to read 4, iclass 17, count 0 2006.257.07:19:51.57#ibcon#read 4, iclass 17, count 0 2006.257.07:19:51.57#ibcon#about to read 5, iclass 17, count 0 2006.257.07:19:51.57#ibcon#read 5, iclass 17, count 0 2006.257.07:19:51.57#ibcon#about to read 6, iclass 17, count 0 2006.257.07:19:51.57#ibcon#read 6, iclass 17, count 0 2006.257.07:19:51.57#ibcon#end of sib2, iclass 17, count 0 2006.257.07:19:51.57#ibcon#*mode == 0, iclass 17, count 0 2006.257.07:19:51.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.07:19:51.57#ibcon#[27=USB\r\n] 2006.257.07:19:51.57#ibcon#*before write, iclass 17, count 0 2006.257.07:19:51.57#ibcon#enter sib2, iclass 17, count 0 2006.257.07:19:51.57#ibcon#flushed, iclass 17, count 0 2006.257.07:19:51.57#ibcon#about to write, iclass 17, count 0 2006.257.07:19:51.57#ibcon#wrote, iclass 17, count 0 2006.257.07:19:51.57#ibcon#about to read 3, iclass 17, count 0 2006.257.07:19:51.60#ibcon#read 3, iclass 17, count 0 2006.257.07:19:51.60#ibcon#about to read 4, iclass 17, count 0 2006.257.07:19:51.60#ibcon#read 4, iclass 17, count 0 2006.257.07:19:51.60#ibcon#about to read 5, iclass 17, count 0 2006.257.07:19:51.60#ibcon#read 5, iclass 17, count 0 2006.257.07:19:51.60#ibcon#about to read 6, iclass 17, count 0 2006.257.07:19:51.60#ibcon#read 6, iclass 17, count 0 2006.257.07:19:51.60#ibcon#end of sib2, iclass 17, count 0 2006.257.07:19:51.60#ibcon#*after write, iclass 17, count 0 2006.257.07:19:51.60#ibcon#*before return 0, iclass 17, count 0 2006.257.07:19:51.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:51.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:19:51.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.07:19:51.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.07:19:51.60$vck44/vblo=6,719.99 2006.257.07:19:51.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.07:19:51.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.07:19:51.60#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:51.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:51.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:51.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:51.60#ibcon#enter wrdev, iclass 19, count 0 2006.257.07:19:51.60#ibcon#first serial, iclass 19, count 0 2006.257.07:19:51.60#ibcon#enter sib2, iclass 19, count 0 2006.257.07:19:51.60#ibcon#flushed, iclass 19, count 0 2006.257.07:19:51.60#ibcon#about to write, iclass 19, count 0 2006.257.07:19:51.60#ibcon#wrote, iclass 19, count 0 2006.257.07:19:51.60#ibcon#about to read 3, iclass 19, count 0 2006.257.07:19:51.62#ibcon#read 3, iclass 19, count 0 2006.257.07:19:51.62#ibcon#about to read 4, iclass 19, count 0 2006.257.07:19:51.62#ibcon#read 4, iclass 19, count 0 2006.257.07:19:51.62#ibcon#about to read 5, iclass 19, count 0 2006.257.07:19:51.62#ibcon#read 5, iclass 19, count 0 2006.257.07:19:51.62#ibcon#about to read 6, iclass 19, count 0 2006.257.07:19:51.62#ibcon#read 6, iclass 19, count 0 2006.257.07:19:51.62#ibcon#end of sib2, iclass 19, count 0 2006.257.07:19:51.62#ibcon#*mode == 0, iclass 19, count 0 2006.257.07:19:51.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.07:19:51.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.07:19:51.62#ibcon#*before write, iclass 19, count 0 2006.257.07:19:51.62#ibcon#enter sib2, iclass 19, count 0 2006.257.07:19:51.62#ibcon#flushed, iclass 19, count 0 2006.257.07:19:51.62#ibcon#about to write, iclass 19, count 0 2006.257.07:19:51.62#ibcon#wrote, iclass 19, count 0 2006.257.07:19:51.62#ibcon#about to read 3, iclass 19, count 0 2006.257.07:19:51.66#ibcon#read 3, iclass 19, count 0 2006.257.07:19:51.66#ibcon#about to read 4, iclass 19, count 0 2006.257.07:19:51.66#ibcon#read 4, iclass 19, count 0 2006.257.07:19:51.66#ibcon#about to read 5, iclass 19, count 0 2006.257.07:19:51.66#ibcon#read 5, iclass 19, count 0 2006.257.07:19:51.66#ibcon#about to read 6, iclass 19, count 0 2006.257.07:19:51.66#ibcon#read 6, iclass 19, count 0 2006.257.07:19:51.66#ibcon#end of sib2, iclass 19, count 0 2006.257.07:19:51.66#ibcon#*after write, iclass 19, count 0 2006.257.07:19:51.66#ibcon#*before return 0, iclass 19, count 0 2006.257.07:19:51.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:51.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:19:51.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.07:19:51.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.07:19:51.66$vck44/vb=6,4 2006.257.07:19:51.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.07:19:51.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.07:19:51.66#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:51.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:51.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:51.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:51.72#ibcon#enter wrdev, iclass 21, count 2 2006.257.07:19:51.72#ibcon#first serial, iclass 21, count 2 2006.257.07:19:51.72#ibcon#enter sib2, iclass 21, count 2 2006.257.07:19:51.72#ibcon#flushed, iclass 21, count 2 2006.257.07:19:51.72#ibcon#about to write, iclass 21, count 2 2006.257.07:19:51.72#ibcon#wrote, iclass 21, count 2 2006.257.07:19:51.72#ibcon#about to read 3, iclass 21, count 2 2006.257.07:19:51.74#ibcon#read 3, iclass 21, count 2 2006.257.07:19:51.74#ibcon#about to read 4, iclass 21, count 2 2006.257.07:19:51.74#ibcon#read 4, iclass 21, count 2 2006.257.07:19:51.74#ibcon#about to read 5, iclass 21, count 2 2006.257.07:19:51.74#ibcon#read 5, iclass 21, count 2 2006.257.07:19:51.74#ibcon#about to read 6, iclass 21, count 2 2006.257.07:19:51.74#ibcon#read 6, iclass 21, count 2 2006.257.07:19:51.74#ibcon#end of sib2, iclass 21, count 2 2006.257.07:19:51.74#ibcon#*mode == 0, iclass 21, count 2 2006.257.07:19:51.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.07:19:51.74#ibcon#[27=AT06-04\r\n] 2006.257.07:19:51.74#ibcon#*before write, iclass 21, count 2 2006.257.07:19:51.74#ibcon#enter sib2, iclass 21, count 2 2006.257.07:19:51.74#ibcon#flushed, iclass 21, count 2 2006.257.07:19:51.74#ibcon#about to write, iclass 21, count 2 2006.257.07:19:51.74#ibcon#wrote, iclass 21, count 2 2006.257.07:19:51.74#ibcon#about to read 3, iclass 21, count 2 2006.257.07:19:51.77#ibcon#read 3, iclass 21, count 2 2006.257.07:19:51.77#ibcon#about to read 4, iclass 21, count 2 2006.257.07:19:51.77#ibcon#read 4, iclass 21, count 2 2006.257.07:19:51.77#ibcon#about to read 5, iclass 21, count 2 2006.257.07:19:51.77#ibcon#read 5, iclass 21, count 2 2006.257.07:19:51.77#ibcon#about to read 6, iclass 21, count 2 2006.257.07:19:51.77#ibcon#read 6, iclass 21, count 2 2006.257.07:19:51.77#ibcon#end of sib2, iclass 21, count 2 2006.257.07:19:51.77#ibcon#*after write, iclass 21, count 2 2006.257.07:19:51.77#ibcon#*before return 0, iclass 21, count 2 2006.257.07:19:51.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:51.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:19:51.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.07:19:51.77#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:51.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:51.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:51.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:51.89#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:19:51.89#ibcon#first serial, iclass 21, count 0 2006.257.07:19:51.89#ibcon#enter sib2, iclass 21, count 0 2006.257.07:19:51.89#ibcon#flushed, iclass 21, count 0 2006.257.07:19:51.89#ibcon#about to write, iclass 21, count 0 2006.257.07:19:51.89#ibcon#wrote, iclass 21, count 0 2006.257.07:19:51.89#ibcon#about to read 3, iclass 21, count 0 2006.257.07:19:51.91#ibcon#read 3, iclass 21, count 0 2006.257.07:19:51.91#ibcon#about to read 4, iclass 21, count 0 2006.257.07:19:51.91#ibcon#read 4, iclass 21, count 0 2006.257.07:19:51.91#ibcon#about to read 5, iclass 21, count 0 2006.257.07:19:51.91#ibcon#read 5, iclass 21, count 0 2006.257.07:19:51.91#ibcon#about to read 6, iclass 21, count 0 2006.257.07:19:51.91#ibcon#read 6, iclass 21, count 0 2006.257.07:19:51.91#ibcon#end of sib2, iclass 21, count 0 2006.257.07:19:51.91#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:19:51.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:19:51.91#ibcon#[27=USB\r\n] 2006.257.07:19:51.91#ibcon#*before write, iclass 21, count 0 2006.257.07:19:51.91#ibcon#enter sib2, iclass 21, count 0 2006.257.07:19:51.91#ibcon#flushed, iclass 21, count 0 2006.257.07:19:51.91#ibcon#about to write, iclass 21, count 0 2006.257.07:19:51.91#ibcon#wrote, iclass 21, count 0 2006.257.07:19:51.91#ibcon#about to read 3, iclass 21, count 0 2006.257.07:19:51.94#ibcon#read 3, iclass 21, count 0 2006.257.07:19:51.94#ibcon#about to read 4, iclass 21, count 0 2006.257.07:19:51.94#ibcon#read 4, iclass 21, count 0 2006.257.07:19:51.94#ibcon#about to read 5, iclass 21, count 0 2006.257.07:19:51.94#ibcon#read 5, iclass 21, count 0 2006.257.07:19:51.94#ibcon#about to read 6, iclass 21, count 0 2006.257.07:19:51.94#ibcon#read 6, iclass 21, count 0 2006.257.07:19:51.94#ibcon#end of sib2, iclass 21, count 0 2006.257.07:19:51.94#ibcon#*after write, iclass 21, count 0 2006.257.07:19:51.94#ibcon#*before return 0, iclass 21, count 0 2006.257.07:19:51.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:51.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:19:51.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:19:51.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:19:51.94$vck44/vblo=7,734.99 2006.257.07:19:51.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.07:19:51.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.07:19:51.94#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:51.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:51.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:51.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:51.94#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:19:51.94#ibcon#first serial, iclass 23, count 0 2006.257.07:19:51.94#ibcon#enter sib2, iclass 23, count 0 2006.257.07:19:51.94#ibcon#flushed, iclass 23, count 0 2006.257.07:19:51.94#ibcon#about to write, iclass 23, count 0 2006.257.07:19:51.94#ibcon#wrote, iclass 23, count 0 2006.257.07:19:51.94#ibcon#about to read 3, iclass 23, count 0 2006.257.07:19:51.96#ibcon#read 3, iclass 23, count 0 2006.257.07:19:51.96#ibcon#about to read 4, iclass 23, count 0 2006.257.07:19:51.96#ibcon#read 4, iclass 23, count 0 2006.257.07:19:51.96#ibcon#about to read 5, iclass 23, count 0 2006.257.07:19:51.96#ibcon#read 5, iclass 23, count 0 2006.257.07:19:51.96#ibcon#about to read 6, iclass 23, count 0 2006.257.07:19:51.96#ibcon#read 6, iclass 23, count 0 2006.257.07:19:51.96#ibcon#end of sib2, iclass 23, count 0 2006.257.07:19:51.96#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:19:51.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:19:51.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.07:19:51.96#ibcon#*before write, iclass 23, count 0 2006.257.07:19:51.96#ibcon#enter sib2, iclass 23, count 0 2006.257.07:19:51.96#ibcon#flushed, iclass 23, count 0 2006.257.07:19:51.96#ibcon#about to write, iclass 23, count 0 2006.257.07:19:51.96#ibcon#wrote, iclass 23, count 0 2006.257.07:19:51.96#ibcon#about to read 3, iclass 23, count 0 2006.257.07:19:52.00#ibcon#read 3, iclass 23, count 0 2006.257.07:19:52.00#ibcon#about to read 4, iclass 23, count 0 2006.257.07:19:52.00#ibcon#read 4, iclass 23, count 0 2006.257.07:19:52.00#ibcon#about to read 5, iclass 23, count 0 2006.257.07:19:52.00#ibcon#read 5, iclass 23, count 0 2006.257.07:19:52.00#ibcon#about to read 6, iclass 23, count 0 2006.257.07:19:52.00#ibcon#read 6, iclass 23, count 0 2006.257.07:19:52.00#ibcon#end of sib2, iclass 23, count 0 2006.257.07:19:52.00#ibcon#*after write, iclass 23, count 0 2006.257.07:19:52.00#ibcon#*before return 0, iclass 23, count 0 2006.257.07:19:52.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:52.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:19:52.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:19:52.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:19:52.00$vck44/vb=7,4 2006.257.07:19:52.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.07:19:52.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.07:19:52.00#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:52.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:52.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:52.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:52.06#ibcon#enter wrdev, iclass 25, count 2 2006.257.07:19:52.06#ibcon#first serial, iclass 25, count 2 2006.257.07:19:52.06#ibcon#enter sib2, iclass 25, count 2 2006.257.07:19:52.06#ibcon#flushed, iclass 25, count 2 2006.257.07:19:52.06#ibcon#about to write, iclass 25, count 2 2006.257.07:19:52.06#ibcon#wrote, iclass 25, count 2 2006.257.07:19:52.06#ibcon#about to read 3, iclass 25, count 2 2006.257.07:19:52.08#ibcon#read 3, iclass 25, count 2 2006.257.07:19:52.08#ibcon#about to read 4, iclass 25, count 2 2006.257.07:19:52.08#ibcon#read 4, iclass 25, count 2 2006.257.07:19:52.08#ibcon#about to read 5, iclass 25, count 2 2006.257.07:19:52.08#ibcon#read 5, iclass 25, count 2 2006.257.07:19:52.08#ibcon#about to read 6, iclass 25, count 2 2006.257.07:19:52.08#ibcon#read 6, iclass 25, count 2 2006.257.07:19:52.08#ibcon#end of sib2, iclass 25, count 2 2006.257.07:19:52.08#ibcon#*mode == 0, iclass 25, count 2 2006.257.07:19:52.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.07:19:52.08#ibcon#[27=AT07-04\r\n] 2006.257.07:19:52.08#ibcon#*before write, iclass 25, count 2 2006.257.07:19:52.08#ibcon#enter sib2, iclass 25, count 2 2006.257.07:19:52.08#ibcon#flushed, iclass 25, count 2 2006.257.07:19:52.08#ibcon#about to write, iclass 25, count 2 2006.257.07:19:52.08#ibcon#wrote, iclass 25, count 2 2006.257.07:19:52.08#ibcon#about to read 3, iclass 25, count 2 2006.257.07:19:52.11#ibcon#read 3, iclass 25, count 2 2006.257.07:19:52.11#ibcon#about to read 4, iclass 25, count 2 2006.257.07:19:52.11#ibcon#read 4, iclass 25, count 2 2006.257.07:19:52.11#ibcon#about to read 5, iclass 25, count 2 2006.257.07:19:52.11#ibcon#read 5, iclass 25, count 2 2006.257.07:19:52.11#ibcon#about to read 6, iclass 25, count 2 2006.257.07:19:52.11#ibcon#read 6, iclass 25, count 2 2006.257.07:19:52.11#ibcon#end of sib2, iclass 25, count 2 2006.257.07:19:52.11#ibcon#*after write, iclass 25, count 2 2006.257.07:19:52.11#ibcon#*before return 0, iclass 25, count 2 2006.257.07:19:52.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:52.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:19:52.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.07:19:52.11#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:52.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:52.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:52.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:52.23#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:19:52.23#ibcon#first serial, iclass 25, count 0 2006.257.07:19:52.23#ibcon#enter sib2, iclass 25, count 0 2006.257.07:19:52.23#ibcon#flushed, iclass 25, count 0 2006.257.07:19:52.23#ibcon#about to write, iclass 25, count 0 2006.257.07:19:52.23#ibcon#wrote, iclass 25, count 0 2006.257.07:19:52.23#ibcon#about to read 3, iclass 25, count 0 2006.257.07:19:52.25#ibcon#read 3, iclass 25, count 0 2006.257.07:19:52.25#ibcon#about to read 4, iclass 25, count 0 2006.257.07:19:52.25#ibcon#read 4, iclass 25, count 0 2006.257.07:19:52.25#ibcon#about to read 5, iclass 25, count 0 2006.257.07:19:52.25#ibcon#read 5, iclass 25, count 0 2006.257.07:19:52.25#ibcon#about to read 6, iclass 25, count 0 2006.257.07:19:52.25#ibcon#read 6, iclass 25, count 0 2006.257.07:19:52.25#ibcon#end of sib2, iclass 25, count 0 2006.257.07:19:52.25#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:19:52.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:19:52.25#ibcon#[27=USB\r\n] 2006.257.07:19:52.25#ibcon#*before write, iclass 25, count 0 2006.257.07:19:52.25#ibcon#enter sib2, iclass 25, count 0 2006.257.07:19:52.25#ibcon#flushed, iclass 25, count 0 2006.257.07:19:52.25#ibcon#about to write, iclass 25, count 0 2006.257.07:19:52.25#ibcon#wrote, iclass 25, count 0 2006.257.07:19:52.25#ibcon#about to read 3, iclass 25, count 0 2006.257.07:19:52.28#ibcon#read 3, iclass 25, count 0 2006.257.07:19:52.28#ibcon#about to read 4, iclass 25, count 0 2006.257.07:19:52.28#ibcon#read 4, iclass 25, count 0 2006.257.07:19:52.28#ibcon#about to read 5, iclass 25, count 0 2006.257.07:19:52.28#ibcon#read 5, iclass 25, count 0 2006.257.07:19:52.28#ibcon#about to read 6, iclass 25, count 0 2006.257.07:19:52.28#ibcon#read 6, iclass 25, count 0 2006.257.07:19:52.28#ibcon#end of sib2, iclass 25, count 0 2006.257.07:19:52.28#ibcon#*after write, iclass 25, count 0 2006.257.07:19:52.28#ibcon#*before return 0, iclass 25, count 0 2006.257.07:19:52.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:52.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:19:52.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:19:52.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:19:52.28$vck44/vblo=8,744.99 2006.257.07:19:52.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.07:19:52.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.07:19:52.28#ibcon#ireg 17 cls_cnt 0 2006.257.07:19:52.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:52.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:52.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:52.28#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:19:52.28#ibcon#first serial, iclass 27, count 0 2006.257.07:19:52.28#ibcon#enter sib2, iclass 27, count 0 2006.257.07:19:52.28#ibcon#flushed, iclass 27, count 0 2006.257.07:19:52.28#ibcon#about to write, iclass 27, count 0 2006.257.07:19:52.28#ibcon#wrote, iclass 27, count 0 2006.257.07:19:52.28#ibcon#about to read 3, iclass 27, count 0 2006.257.07:19:52.30#ibcon#read 3, iclass 27, count 0 2006.257.07:19:52.30#ibcon#about to read 4, iclass 27, count 0 2006.257.07:19:52.30#ibcon#read 4, iclass 27, count 0 2006.257.07:19:52.30#ibcon#about to read 5, iclass 27, count 0 2006.257.07:19:52.30#ibcon#read 5, iclass 27, count 0 2006.257.07:19:52.30#ibcon#about to read 6, iclass 27, count 0 2006.257.07:19:52.30#ibcon#read 6, iclass 27, count 0 2006.257.07:19:52.30#ibcon#end of sib2, iclass 27, count 0 2006.257.07:19:52.30#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:19:52.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:19:52.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.07:19:52.30#ibcon#*before write, iclass 27, count 0 2006.257.07:19:52.30#ibcon#enter sib2, iclass 27, count 0 2006.257.07:19:52.30#ibcon#flushed, iclass 27, count 0 2006.257.07:19:52.30#ibcon#about to write, iclass 27, count 0 2006.257.07:19:52.30#ibcon#wrote, iclass 27, count 0 2006.257.07:19:52.30#ibcon#about to read 3, iclass 27, count 0 2006.257.07:19:52.34#ibcon#read 3, iclass 27, count 0 2006.257.07:19:52.34#ibcon#about to read 4, iclass 27, count 0 2006.257.07:19:52.34#ibcon#read 4, iclass 27, count 0 2006.257.07:19:52.34#ibcon#about to read 5, iclass 27, count 0 2006.257.07:19:52.34#ibcon#read 5, iclass 27, count 0 2006.257.07:19:52.34#ibcon#about to read 6, iclass 27, count 0 2006.257.07:19:52.34#ibcon#read 6, iclass 27, count 0 2006.257.07:19:52.34#ibcon#end of sib2, iclass 27, count 0 2006.257.07:19:52.34#ibcon#*after write, iclass 27, count 0 2006.257.07:19:52.34#ibcon#*before return 0, iclass 27, count 0 2006.257.07:19:52.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:52.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:19:52.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:19:52.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:19:52.34$vck44/vb=8,4 2006.257.07:19:52.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.07:19:52.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.07:19:52.34#ibcon#ireg 11 cls_cnt 2 2006.257.07:19:52.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:52.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:52.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:52.40#ibcon#enter wrdev, iclass 29, count 2 2006.257.07:19:52.40#ibcon#first serial, iclass 29, count 2 2006.257.07:19:52.40#ibcon#enter sib2, iclass 29, count 2 2006.257.07:19:52.40#ibcon#flushed, iclass 29, count 2 2006.257.07:19:52.40#ibcon#about to write, iclass 29, count 2 2006.257.07:19:52.40#ibcon#wrote, iclass 29, count 2 2006.257.07:19:52.40#ibcon#about to read 3, iclass 29, count 2 2006.257.07:19:52.42#ibcon#read 3, iclass 29, count 2 2006.257.07:19:52.42#ibcon#about to read 4, iclass 29, count 2 2006.257.07:19:52.42#ibcon#read 4, iclass 29, count 2 2006.257.07:19:52.42#ibcon#about to read 5, iclass 29, count 2 2006.257.07:19:52.42#ibcon#read 5, iclass 29, count 2 2006.257.07:19:52.42#ibcon#about to read 6, iclass 29, count 2 2006.257.07:19:52.42#ibcon#read 6, iclass 29, count 2 2006.257.07:19:52.42#ibcon#end of sib2, iclass 29, count 2 2006.257.07:19:52.42#ibcon#*mode == 0, iclass 29, count 2 2006.257.07:19:52.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.07:19:52.42#ibcon#[27=AT08-04\r\n] 2006.257.07:19:52.42#ibcon#*before write, iclass 29, count 2 2006.257.07:19:52.42#ibcon#enter sib2, iclass 29, count 2 2006.257.07:19:52.42#ibcon#flushed, iclass 29, count 2 2006.257.07:19:52.42#ibcon#about to write, iclass 29, count 2 2006.257.07:19:52.42#ibcon#wrote, iclass 29, count 2 2006.257.07:19:52.42#ibcon#about to read 3, iclass 29, count 2 2006.257.07:19:52.45#ibcon#read 3, iclass 29, count 2 2006.257.07:19:52.45#ibcon#about to read 4, iclass 29, count 2 2006.257.07:19:52.45#ibcon#read 4, iclass 29, count 2 2006.257.07:19:52.45#ibcon#about to read 5, iclass 29, count 2 2006.257.07:19:52.45#ibcon#read 5, iclass 29, count 2 2006.257.07:19:52.45#ibcon#about to read 6, iclass 29, count 2 2006.257.07:19:52.45#ibcon#read 6, iclass 29, count 2 2006.257.07:19:52.45#ibcon#end of sib2, iclass 29, count 2 2006.257.07:19:52.45#ibcon#*after write, iclass 29, count 2 2006.257.07:19:52.45#ibcon#*before return 0, iclass 29, count 2 2006.257.07:19:52.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:52.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:19:52.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.07:19:52.45#ibcon#ireg 7 cls_cnt 0 2006.257.07:19:52.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:52.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:52.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:52.57#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:19:52.57#ibcon#first serial, iclass 29, count 0 2006.257.07:19:52.57#ibcon#enter sib2, iclass 29, count 0 2006.257.07:19:52.57#ibcon#flushed, iclass 29, count 0 2006.257.07:19:52.57#ibcon#about to write, iclass 29, count 0 2006.257.07:19:52.57#ibcon#wrote, iclass 29, count 0 2006.257.07:19:52.57#ibcon#about to read 3, iclass 29, count 0 2006.257.07:19:52.59#ibcon#read 3, iclass 29, count 0 2006.257.07:19:52.59#ibcon#about to read 4, iclass 29, count 0 2006.257.07:19:52.59#ibcon#read 4, iclass 29, count 0 2006.257.07:19:52.59#ibcon#about to read 5, iclass 29, count 0 2006.257.07:19:52.59#ibcon#read 5, iclass 29, count 0 2006.257.07:19:52.59#ibcon#about to read 6, iclass 29, count 0 2006.257.07:19:52.59#ibcon#read 6, iclass 29, count 0 2006.257.07:19:52.59#ibcon#end of sib2, iclass 29, count 0 2006.257.07:19:52.59#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:19:52.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:19:52.59#ibcon#[27=USB\r\n] 2006.257.07:19:52.59#ibcon#*before write, iclass 29, count 0 2006.257.07:19:52.59#ibcon#enter sib2, iclass 29, count 0 2006.257.07:19:52.59#ibcon#flushed, iclass 29, count 0 2006.257.07:19:52.59#ibcon#about to write, iclass 29, count 0 2006.257.07:19:52.59#ibcon#wrote, iclass 29, count 0 2006.257.07:19:52.59#ibcon#about to read 3, iclass 29, count 0 2006.257.07:19:52.62#ibcon#read 3, iclass 29, count 0 2006.257.07:19:52.62#ibcon#about to read 4, iclass 29, count 0 2006.257.07:19:52.62#ibcon#read 4, iclass 29, count 0 2006.257.07:19:52.62#ibcon#about to read 5, iclass 29, count 0 2006.257.07:19:52.62#ibcon#read 5, iclass 29, count 0 2006.257.07:19:52.62#ibcon#about to read 6, iclass 29, count 0 2006.257.07:19:52.62#ibcon#read 6, iclass 29, count 0 2006.257.07:19:52.62#ibcon#end of sib2, iclass 29, count 0 2006.257.07:19:52.62#ibcon#*after write, iclass 29, count 0 2006.257.07:19:52.62#ibcon#*before return 0, iclass 29, count 0 2006.257.07:19:52.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:52.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:19:52.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:19:52.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:19:52.62$vck44/vabw=wide 2006.257.07:19:52.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.07:19:52.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.07:19:52.62#ibcon#ireg 8 cls_cnt 0 2006.257.07:19:52.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:52.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:52.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:52.62#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:19:52.62#ibcon#first serial, iclass 31, count 0 2006.257.07:19:52.62#ibcon#enter sib2, iclass 31, count 0 2006.257.07:19:52.62#ibcon#flushed, iclass 31, count 0 2006.257.07:19:52.62#ibcon#about to write, iclass 31, count 0 2006.257.07:19:52.62#ibcon#wrote, iclass 31, count 0 2006.257.07:19:52.62#ibcon#about to read 3, iclass 31, count 0 2006.257.07:19:52.64#ibcon#read 3, iclass 31, count 0 2006.257.07:19:52.64#ibcon#about to read 4, iclass 31, count 0 2006.257.07:19:52.64#ibcon#read 4, iclass 31, count 0 2006.257.07:19:52.64#ibcon#about to read 5, iclass 31, count 0 2006.257.07:19:52.64#ibcon#read 5, iclass 31, count 0 2006.257.07:19:52.64#ibcon#about to read 6, iclass 31, count 0 2006.257.07:19:52.64#ibcon#read 6, iclass 31, count 0 2006.257.07:19:52.64#ibcon#end of sib2, iclass 31, count 0 2006.257.07:19:52.64#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:19:52.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:19:52.64#ibcon#[25=BW32\r\n] 2006.257.07:19:52.64#ibcon#*before write, iclass 31, count 0 2006.257.07:19:52.64#ibcon#enter sib2, iclass 31, count 0 2006.257.07:19:52.64#ibcon#flushed, iclass 31, count 0 2006.257.07:19:52.64#ibcon#about to write, iclass 31, count 0 2006.257.07:19:52.64#ibcon#wrote, iclass 31, count 0 2006.257.07:19:52.64#ibcon#about to read 3, iclass 31, count 0 2006.257.07:19:52.67#ibcon#read 3, iclass 31, count 0 2006.257.07:19:52.67#ibcon#about to read 4, iclass 31, count 0 2006.257.07:19:52.67#ibcon#read 4, iclass 31, count 0 2006.257.07:19:52.67#ibcon#about to read 5, iclass 31, count 0 2006.257.07:19:52.67#ibcon#read 5, iclass 31, count 0 2006.257.07:19:52.67#ibcon#about to read 6, iclass 31, count 0 2006.257.07:19:52.67#ibcon#read 6, iclass 31, count 0 2006.257.07:19:52.67#ibcon#end of sib2, iclass 31, count 0 2006.257.07:19:52.67#ibcon#*after write, iclass 31, count 0 2006.257.07:19:52.67#ibcon#*before return 0, iclass 31, count 0 2006.257.07:19:52.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:52.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:19:52.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:19:52.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:19:52.67$vck44/vbbw=wide 2006.257.07:19:52.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.07:19:52.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.07:19:52.67#ibcon#ireg 8 cls_cnt 0 2006.257.07:19:52.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:19:52.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:19:52.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:19:52.74#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:19:52.74#ibcon#first serial, iclass 33, count 0 2006.257.07:19:52.74#ibcon#enter sib2, iclass 33, count 0 2006.257.07:19:52.74#ibcon#flushed, iclass 33, count 0 2006.257.07:19:52.74#ibcon#about to write, iclass 33, count 0 2006.257.07:19:52.74#ibcon#wrote, iclass 33, count 0 2006.257.07:19:52.74#ibcon#about to read 3, iclass 33, count 0 2006.257.07:19:52.76#ibcon#read 3, iclass 33, count 0 2006.257.07:19:52.76#ibcon#about to read 4, iclass 33, count 0 2006.257.07:19:52.76#ibcon#read 4, iclass 33, count 0 2006.257.07:19:52.76#ibcon#about to read 5, iclass 33, count 0 2006.257.07:19:52.76#ibcon#read 5, iclass 33, count 0 2006.257.07:19:52.76#ibcon#about to read 6, iclass 33, count 0 2006.257.07:19:52.76#ibcon#read 6, iclass 33, count 0 2006.257.07:19:52.76#ibcon#end of sib2, iclass 33, count 0 2006.257.07:19:52.76#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:19:52.76#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:19:52.76#ibcon#[27=BW32\r\n] 2006.257.07:19:52.76#ibcon#*before write, iclass 33, count 0 2006.257.07:19:52.76#ibcon#enter sib2, iclass 33, count 0 2006.257.07:19:52.76#ibcon#flushed, iclass 33, count 0 2006.257.07:19:52.76#ibcon#about to write, iclass 33, count 0 2006.257.07:19:52.76#ibcon#wrote, iclass 33, count 0 2006.257.07:19:52.76#ibcon#about to read 3, iclass 33, count 0 2006.257.07:19:52.79#ibcon#read 3, iclass 33, count 0 2006.257.07:19:52.79#ibcon#about to read 4, iclass 33, count 0 2006.257.07:19:52.79#ibcon#read 4, iclass 33, count 0 2006.257.07:19:52.79#ibcon#about to read 5, iclass 33, count 0 2006.257.07:19:52.79#ibcon#read 5, iclass 33, count 0 2006.257.07:19:52.79#ibcon#about to read 6, iclass 33, count 0 2006.257.07:19:52.79#ibcon#read 6, iclass 33, count 0 2006.257.07:19:52.79#ibcon#end of sib2, iclass 33, count 0 2006.257.07:19:52.79#ibcon#*after write, iclass 33, count 0 2006.257.07:19:52.79#ibcon#*before return 0, iclass 33, count 0 2006.257.07:19:52.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:19:52.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:19:52.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:19:52.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:19:52.79$setupk4/ifdk4 2006.257.07:19:52.79$ifdk4/lo= 2006.257.07:19:52.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.07:19:52.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.07:19:52.79$ifdk4/patch= 2006.257.07:19:52.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.07:19:52.80$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.07:19:52.80$setupk4/!*+20s 2006.257.07:19:53.48#abcon#<5=/16 1.0 3.1 21.37 841012.2\r\n> 2006.257.07:19:53.50#abcon#{5=INTERFACE CLEAR} 2006.257.07:19:53.56#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:20:03.65#abcon#<5=/16 1.0 3.1 21.36 841012.2\r\n> 2006.257.07:20:03.67#abcon#{5=INTERFACE CLEAR} 2006.257.07:20:03.73#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:20:05.14#trakl#Source acquired 2006.257.07:20:06.14#flagr#flagr/antenna,acquired 2006.257.07:20:07.31$setupk4/"tpicd 2006.257.07:20:07.31$setupk4/echo=off 2006.257.07:20:07.31$setupk4/xlog=off 2006.257.07:20:07.31:!2006.257.07:22:33 2006.257.07:22:33.00:preob 2006.257.07:22:34.14/onsource/TRACKING 2006.257.07:22:34.14:!2006.257.07:22:43 2006.257.07:22:43.00:"tape 2006.257.07:22:43.00:"st=record 2006.257.07:22:43.00:data_valid=on 2006.257.07:22:43.00:midob 2006.257.07:22:43.14/onsource/TRACKING 2006.257.07:22:43.14/wx/21.32,1012.4,85 2006.257.07:22:43.35/cable/+6.4765E-03 2006.257.07:22:44.44/va/01,08,usb,yes,31,34 2006.257.07:22:44.44/va/02,07,usb,yes,34,35 2006.257.07:22:44.44/va/03,08,usb,yes,31,32 2006.257.07:22:44.44/va/04,07,usb,yes,35,37 2006.257.07:22:44.44/va/05,04,usb,yes,32,32 2006.257.07:22:44.44/va/06,04,usb,yes,35,35 2006.257.07:22:44.44/va/07,04,usb,yes,36,36 2006.257.07:22:44.44/va/08,04,usb,yes,30,37 2006.257.07:22:44.67/valo/01,524.99,yes,locked 2006.257.07:22:44.67/valo/02,534.99,yes,locked 2006.257.07:22:44.67/valo/03,564.99,yes,locked 2006.257.07:22:44.67/valo/04,624.99,yes,locked 2006.257.07:22:44.67/valo/05,734.99,yes,locked 2006.257.07:22:44.67/valo/06,814.99,yes,locked 2006.257.07:22:44.67/valo/07,864.99,yes,locked 2006.257.07:22:44.67/valo/08,884.99,yes,locked 2006.257.07:22:45.76/vb/01,04,usb,yes,30,28 2006.257.07:22:45.76/vb/02,05,usb,yes,29,29 2006.257.07:22:45.76/vb/03,04,usb,yes,30,33 2006.257.07:22:45.76/vb/04,05,usb,yes,30,29 2006.257.07:22:45.76/vb/05,04,usb,yes,26,29 2006.257.07:22:45.76/vb/06,04,usb,yes,31,27 2006.257.07:22:45.76/vb/07,04,usb,yes,31,31 2006.257.07:22:45.76/vb/08,04,usb,yes,28,32 2006.257.07:22:45.99/vblo/01,629.99,yes,locked 2006.257.07:22:45.99/vblo/02,634.99,yes,locked 2006.257.07:22:45.99/vblo/03,649.99,yes,locked 2006.257.07:22:45.99/vblo/04,679.99,yes,locked 2006.257.07:22:45.99/vblo/05,709.99,yes,locked 2006.257.07:22:45.99/vblo/06,719.99,yes,locked 2006.257.07:22:45.99/vblo/07,734.99,yes,locked 2006.257.07:22:45.99/vblo/08,744.99,yes,locked 2006.257.07:22:46.14/vabw/8 2006.257.07:22:46.29/vbbw/8 2006.257.07:22:46.38/xfe/off,on,16.7 2006.257.07:22:46.80/ifatt/23,28,28,28 2006.257.07:22:47.07/fmout-gps/S +4.53E-07 2006.257.07:22:47.11:!2006.257.07:27:23 2006.257.07:27:23.00:data_valid=off 2006.257.07:27:23.00:"et 2006.257.07:27:23.00:!+3s 2006.257.07:27:26.01:"tape 2006.257.07:27:26.01:postob 2006.257.07:27:26.07/cable/+6.4762E-03 2006.257.07:27:26.07/wx/21.26,1012.5,86 2006.257.07:27:27.07/fmout-gps/S +4.53E-07 2006.257.07:27:27.07:scan_name=257-0730,jd0609,40 2006.257.07:27:27.07:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.257.07:27:28.14#flagr#flagr/antenna,new-source 2006.257.07:27:28.14:checkk5 2006.257.07:27:28.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.07:27:28.98/chk_autoobs//k5ts2/ autoobs is running! 2006.257.07:27:29.40/chk_autoobs//k5ts3/ autoobs is running! 2006.257.07:27:29.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.07:27:30.18/chk_obsdata//k5ts1/T2570722??a.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.257.07:27:30.59/chk_obsdata//k5ts2/T2570722??b.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.257.07:27:31.01/chk_obsdata//k5ts3/T2570722??c.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.257.07:27:31.40/chk_obsdata//k5ts4/T2570722??d.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.257.07:27:32.14/k5log//k5ts1_log_newline 2006.257.07:27:32.87/k5log//k5ts2_log_newline 2006.257.07:27:33.62/k5log//k5ts3_log_newline 2006.257.07:27:34.35/k5log//k5ts4_log_newline 2006.257.07:27:34.37/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.07:27:34.37:setupk4=1 2006.257.07:27:34.37$setupk4/echo=on 2006.257.07:27:34.37$setupk4/pcalon 2006.257.07:27:34.37$pcalon/"no phase cal control is implemented here 2006.257.07:27:34.37$setupk4/"tpicd=stop 2006.257.07:27:34.37$setupk4/"rec=synch_on 2006.257.07:27:34.37$setupk4/"rec_mode=128 2006.257.07:27:34.37$setupk4/!* 2006.257.07:27:34.37$setupk4/recpk4 2006.257.07:27:34.37$recpk4/recpatch= 2006.257.07:27:34.37$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.07:27:34.37$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.07:27:34.37$setupk4/vck44 2006.257.07:27:34.37$vck44/valo=1,524.99 2006.257.07:27:34.38#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.07:27:34.38#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.07:27:34.38#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:34.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:34.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:34.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:34.38#ibcon#enter wrdev, iclass 4, count 0 2006.257.07:27:34.38#ibcon#first serial, iclass 4, count 0 2006.257.07:27:34.38#ibcon#enter sib2, iclass 4, count 0 2006.257.07:27:34.38#ibcon#flushed, iclass 4, count 0 2006.257.07:27:34.38#ibcon#about to write, iclass 4, count 0 2006.257.07:27:34.38#ibcon#wrote, iclass 4, count 0 2006.257.07:27:34.38#ibcon#about to read 3, iclass 4, count 0 2006.257.07:27:34.39#ibcon#read 3, iclass 4, count 0 2006.257.07:27:34.39#ibcon#about to read 4, iclass 4, count 0 2006.257.07:27:34.39#ibcon#read 4, iclass 4, count 0 2006.257.07:27:34.39#ibcon#about to read 5, iclass 4, count 0 2006.257.07:27:34.39#ibcon#read 5, iclass 4, count 0 2006.257.07:27:34.39#ibcon#about to read 6, iclass 4, count 0 2006.257.07:27:34.39#ibcon#read 6, iclass 4, count 0 2006.257.07:27:34.39#ibcon#end of sib2, iclass 4, count 0 2006.257.07:27:34.39#ibcon#*mode == 0, iclass 4, count 0 2006.257.07:27:34.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.07:27:34.39#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.07:27:34.39#ibcon#*before write, iclass 4, count 0 2006.257.07:27:34.39#ibcon#enter sib2, iclass 4, count 0 2006.257.07:27:34.39#ibcon#flushed, iclass 4, count 0 2006.257.07:27:34.39#ibcon#about to write, iclass 4, count 0 2006.257.07:27:34.39#ibcon#wrote, iclass 4, count 0 2006.257.07:27:34.39#ibcon#about to read 3, iclass 4, count 0 2006.257.07:27:34.44#ibcon#read 3, iclass 4, count 0 2006.257.07:27:34.44#ibcon#about to read 4, iclass 4, count 0 2006.257.07:27:34.44#ibcon#read 4, iclass 4, count 0 2006.257.07:27:34.44#ibcon#about to read 5, iclass 4, count 0 2006.257.07:27:34.44#ibcon#read 5, iclass 4, count 0 2006.257.07:27:34.44#ibcon#about to read 6, iclass 4, count 0 2006.257.07:27:34.44#ibcon#read 6, iclass 4, count 0 2006.257.07:27:34.44#ibcon#end of sib2, iclass 4, count 0 2006.257.07:27:34.44#ibcon#*after write, iclass 4, count 0 2006.257.07:27:34.44#ibcon#*before return 0, iclass 4, count 0 2006.257.07:27:34.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:34.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:34.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.07:27:34.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.07:27:34.44$vck44/va=1,8 2006.257.07:27:34.44#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.07:27:34.44#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.07:27:34.44#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:34.44#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:34.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:34.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:34.44#ibcon#enter wrdev, iclass 6, count 2 2006.257.07:27:34.44#ibcon#first serial, iclass 6, count 2 2006.257.07:27:34.44#ibcon#enter sib2, iclass 6, count 2 2006.257.07:27:34.44#ibcon#flushed, iclass 6, count 2 2006.257.07:27:34.44#ibcon#about to write, iclass 6, count 2 2006.257.07:27:34.44#ibcon#wrote, iclass 6, count 2 2006.257.07:27:34.44#ibcon#about to read 3, iclass 6, count 2 2006.257.07:27:34.46#ibcon#read 3, iclass 6, count 2 2006.257.07:27:34.46#ibcon#about to read 4, iclass 6, count 2 2006.257.07:27:34.46#ibcon#read 4, iclass 6, count 2 2006.257.07:27:34.46#ibcon#about to read 5, iclass 6, count 2 2006.257.07:27:34.46#ibcon#read 5, iclass 6, count 2 2006.257.07:27:34.46#ibcon#about to read 6, iclass 6, count 2 2006.257.07:27:34.46#ibcon#read 6, iclass 6, count 2 2006.257.07:27:34.46#ibcon#end of sib2, iclass 6, count 2 2006.257.07:27:34.46#ibcon#*mode == 0, iclass 6, count 2 2006.257.07:27:34.46#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.07:27:34.46#ibcon#[25=AT01-08\r\n] 2006.257.07:27:34.46#ibcon#*before write, iclass 6, count 2 2006.257.07:27:34.46#ibcon#enter sib2, iclass 6, count 2 2006.257.07:27:34.46#ibcon#flushed, iclass 6, count 2 2006.257.07:27:34.46#ibcon#about to write, iclass 6, count 2 2006.257.07:27:34.46#ibcon#wrote, iclass 6, count 2 2006.257.07:27:34.46#ibcon#about to read 3, iclass 6, count 2 2006.257.07:27:34.49#ibcon#read 3, iclass 6, count 2 2006.257.07:27:34.49#ibcon#about to read 4, iclass 6, count 2 2006.257.07:27:34.49#ibcon#read 4, iclass 6, count 2 2006.257.07:27:34.49#ibcon#about to read 5, iclass 6, count 2 2006.257.07:27:34.49#ibcon#read 5, iclass 6, count 2 2006.257.07:27:34.49#ibcon#about to read 6, iclass 6, count 2 2006.257.07:27:34.49#ibcon#read 6, iclass 6, count 2 2006.257.07:27:34.49#ibcon#end of sib2, iclass 6, count 2 2006.257.07:27:34.49#ibcon#*after write, iclass 6, count 2 2006.257.07:27:34.49#ibcon#*before return 0, iclass 6, count 2 2006.257.07:27:34.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:34.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:34.49#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.07:27:34.49#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:34.49#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:34.61#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:34.61#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:34.61#ibcon#enter wrdev, iclass 6, count 0 2006.257.07:27:34.61#ibcon#first serial, iclass 6, count 0 2006.257.07:27:34.61#ibcon#enter sib2, iclass 6, count 0 2006.257.07:27:34.61#ibcon#flushed, iclass 6, count 0 2006.257.07:27:34.61#ibcon#about to write, iclass 6, count 0 2006.257.07:27:34.61#ibcon#wrote, iclass 6, count 0 2006.257.07:27:34.61#ibcon#about to read 3, iclass 6, count 0 2006.257.07:27:34.63#ibcon#read 3, iclass 6, count 0 2006.257.07:27:34.63#ibcon#about to read 4, iclass 6, count 0 2006.257.07:27:34.63#ibcon#read 4, iclass 6, count 0 2006.257.07:27:34.63#ibcon#about to read 5, iclass 6, count 0 2006.257.07:27:34.63#ibcon#read 5, iclass 6, count 0 2006.257.07:27:34.63#ibcon#about to read 6, iclass 6, count 0 2006.257.07:27:34.63#ibcon#read 6, iclass 6, count 0 2006.257.07:27:34.63#ibcon#end of sib2, iclass 6, count 0 2006.257.07:27:34.63#ibcon#*mode == 0, iclass 6, count 0 2006.257.07:27:34.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.07:27:34.63#ibcon#[25=USB\r\n] 2006.257.07:27:34.63#ibcon#*before write, iclass 6, count 0 2006.257.07:27:34.63#ibcon#enter sib2, iclass 6, count 0 2006.257.07:27:34.63#ibcon#flushed, iclass 6, count 0 2006.257.07:27:34.63#ibcon#about to write, iclass 6, count 0 2006.257.07:27:34.63#ibcon#wrote, iclass 6, count 0 2006.257.07:27:34.63#ibcon#about to read 3, iclass 6, count 0 2006.257.07:27:34.66#ibcon#read 3, iclass 6, count 0 2006.257.07:27:34.66#ibcon#about to read 4, iclass 6, count 0 2006.257.07:27:34.66#ibcon#read 4, iclass 6, count 0 2006.257.07:27:34.66#ibcon#about to read 5, iclass 6, count 0 2006.257.07:27:34.66#ibcon#read 5, iclass 6, count 0 2006.257.07:27:34.66#ibcon#about to read 6, iclass 6, count 0 2006.257.07:27:34.66#ibcon#read 6, iclass 6, count 0 2006.257.07:27:34.66#ibcon#end of sib2, iclass 6, count 0 2006.257.07:27:34.66#ibcon#*after write, iclass 6, count 0 2006.257.07:27:34.66#ibcon#*before return 0, iclass 6, count 0 2006.257.07:27:34.66#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:34.66#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:34.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.07:27:34.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.07:27:34.66$vck44/valo=2,534.99 2006.257.07:27:34.66#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.07:27:34.66#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.07:27:34.66#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:34.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:34.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:34.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:34.66#ibcon#enter wrdev, iclass 10, count 0 2006.257.07:27:34.66#ibcon#first serial, iclass 10, count 0 2006.257.07:27:34.66#ibcon#enter sib2, iclass 10, count 0 2006.257.07:27:34.66#ibcon#flushed, iclass 10, count 0 2006.257.07:27:34.66#ibcon#about to write, iclass 10, count 0 2006.257.07:27:34.66#ibcon#wrote, iclass 10, count 0 2006.257.07:27:34.66#ibcon#about to read 3, iclass 10, count 0 2006.257.07:27:34.68#ibcon#read 3, iclass 10, count 0 2006.257.07:27:34.68#ibcon#about to read 4, iclass 10, count 0 2006.257.07:27:34.68#ibcon#read 4, iclass 10, count 0 2006.257.07:27:34.68#ibcon#about to read 5, iclass 10, count 0 2006.257.07:27:34.68#ibcon#read 5, iclass 10, count 0 2006.257.07:27:34.68#ibcon#about to read 6, iclass 10, count 0 2006.257.07:27:34.68#ibcon#read 6, iclass 10, count 0 2006.257.07:27:34.68#ibcon#end of sib2, iclass 10, count 0 2006.257.07:27:34.68#ibcon#*mode == 0, iclass 10, count 0 2006.257.07:27:34.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.07:27:34.68#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.07:27:34.68#ibcon#*before write, iclass 10, count 0 2006.257.07:27:34.68#ibcon#enter sib2, iclass 10, count 0 2006.257.07:27:34.68#ibcon#flushed, iclass 10, count 0 2006.257.07:27:34.68#ibcon#about to write, iclass 10, count 0 2006.257.07:27:34.68#ibcon#wrote, iclass 10, count 0 2006.257.07:27:34.68#ibcon#about to read 3, iclass 10, count 0 2006.257.07:27:34.72#ibcon#read 3, iclass 10, count 0 2006.257.07:27:34.72#ibcon#about to read 4, iclass 10, count 0 2006.257.07:27:34.72#ibcon#read 4, iclass 10, count 0 2006.257.07:27:34.72#ibcon#about to read 5, iclass 10, count 0 2006.257.07:27:34.72#ibcon#read 5, iclass 10, count 0 2006.257.07:27:34.72#ibcon#about to read 6, iclass 10, count 0 2006.257.07:27:34.72#ibcon#read 6, iclass 10, count 0 2006.257.07:27:34.72#ibcon#end of sib2, iclass 10, count 0 2006.257.07:27:34.72#ibcon#*after write, iclass 10, count 0 2006.257.07:27:34.72#ibcon#*before return 0, iclass 10, count 0 2006.257.07:27:34.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:34.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:34.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.07:27:34.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.07:27:34.72$vck44/va=2,7 2006.257.07:27:34.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.07:27:34.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.07:27:34.72#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:34.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:34.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:34.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:34.78#ibcon#enter wrdev, iclass 12, count 2 2006.257.07:27:34.78#ibcon#first serial, iclass 12, count 2 2006.257.07:27:34.78#ibcon#enter sib2, iclass 12, count 2 2006.257.07:27:34.78#ibcon#flushed, iclass 12, count 2 2006.257.07:27:34.78#ibcon#about to write, iclass 12, count 2 2006.257.07:27:34.78#ibcon#wrote, iclass 12, count 2 2006.257.07:27:34.78#ibcon#about to read 3, iclass 12, count 2 2006.257.07:27:34.80#ibcon#read 3, iclass 12, count 2 2006.257.07:27:34.80#ibcon#about to read 4, iclass 12, count 2 2006.257.07:27:34.80#ibcon#read 4, iclass 12, count 2 2006.257.07:27:34.80#ibcon#about to read 5, iclass 12, count 2 2006.257.07:27:34.80#ibcon#read 5, iclass 12, count 2 2006.257.07:27:34.80#ibcon#about to read 6, iclass 12, count 2 2006.257.07:27:34.80#ibcon#read 6, iclass 12, count 2 2006.257.07:27:34.80#ibcon#end of sib2, iclass 12, count 2 2006.257.07:27:34.80#ibcon#*mode == 0, iclass 12, count 2 2006.257.07:27:34.80#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.07:27:34.80#ibcon#[25=AT02-07\r\n] 2006.257.07:27:34.80#ibcon#*before write, iclass 12, count 2 2006.257.07:27:34.80#ibcon#enter sib2, iclass 12, count 2 2006.257.07:27:34.80#ibcon#flushed, iclass 12, count 2 2006.257.07:27:34.80#ibcon#about to write, iclass 12, count 2 2006.257.07:27:34.80#ibcon#wrote, iclass 12, count 2 2006.257.07:27:34.80#ibcon#about to read 3, iclass 12, count 2 2006.257.07:27:34.83#ibcon#read 3, iclass 12, count 2 2006.257.07:27:34.83#ibcon#about to read 4, iclass 12, count 2 2006.257.07:27:34.83#ibcon#read 4, iclass 12, count 2 2006.257.07:27:34.83#ibcon#about to read 5, iclass 12, count 2 2006.257.07:27:34.83#ibcon#read 5, iclass 12, count 2 2006.257.07:27:34.83#ibcon#about to read 6, iclass 12, count 2 2006.257.07:27:34.83#ibcon#read 6, iclass 12, count 2 2006.257.07:27:34.83#ibcon#end of sib2, iclass 12, count 2 2006.257.07:27:34.83#ibcon#*after write, iclass 12, count 2 2006.257.07:27:34.83#ibcon#*before return 0, iclass 12, count 2 2006.257.07:27:34.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:34.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:34.83#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.07:27:34.83#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:34.83#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:34.95#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:34.95#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:34.95#ibcon#enter wrdev, iclass 12, count 0 2006.257.07:27:34.95#ibcon#first serial, iclass 12, count 0 2006.257.07:27:34.95#ibcon#enter sib2, iclass 12, count 0 2006.257.07:27:34.95#ibcon#flushed, iclass 12, count 0 2006.257.07:27:34.95#ibcon#about to write, iclass 12, count 0 2006.257.07:27:34.95#ibcon#wrote, iclass 12, count 0 2006.257.07:27:34.95#ibcon#about to read 3, iclass 12, count 0 2006.257.07:27:34.97#ibcon#read 3, iclass 12, count 0 2006.257.07:27:34.97#ibcon#about to read 4, iclass 12, count 0 2006.257.07:27:34.97#ibcon#read 4, iclass 12, count 0 2006.257.07:27:34.97#ibcon#about to read 5, iclass 12, count 0 2006.257.07:27:34.97#ibcon#read 5, iclass 12, count 0 2006.257.07:27:34.97#ibcon#about to read 6, iclass 12, count 0 2006.257.07:27:34.97#ibcon#read 6, iclass 12, count 0 2006.257.07:27:34.97#ibcon#end of sib2, iclass 12, count 0 2006.257.07:27:34.97#ibcon#*mode == 0, iclass 12, count 0 2006.257.07:27:34.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.07:27:34.97#ibcon#[25=USB\r\n] 2006.257.07:27:34.97#ibcon#*before write, iclass 12, count 0 2006.257.07:27:34.97#ibcon#enter sib2, iclass 12, count 0 2006.257.07:27:34.97#ibcon#flushed, iclass 12, count 0 2006.257.07:27:34.97#ibcon#about to write, iclass 12, count 0 2006.257.07:27:34.97#ibcon#wrote, iclass 12, count 0 2006.257.07:27:34.97#ibcon#about to read 3, iclass 12, count 0 2006.257.07:27:35.00#ibcon#read 3, iclass 12, count 0 2006.257.07:27:35.00#ibcon#about to read 4, iclass 12, count 0 2006.257.07:27:35.00#ibcon#read 4, iclass 12, count 0 2006.257.07:27:35.00#ibcon#about to read 5, iclass 12, count 0 2006.257.07:27:35.00#ibcon#read 5, iclass 12, count 0 2006.257.07:27:35.00#ibcon#about to read 6, iclass 12, count 0 2006.257.07:27:35.00#ibcon#read 6, iclass 12, count 0 2006.257.07:27:35.00#ibcon#end of sib2, iclass 12, count 0 2006.257.07:27:35.00#ibcon#*after write, iclass 12, count 0 2006.257.07:27:35.00#ibcon#*before return 0, iclass 12, count 0 2006.257.07:27:35.00#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:35.00#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:35.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.07:27:35.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.07:27:35.00$vck44/valo=3,564.99 2006.257.07:27:35.00#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.07:27:35.00#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.07:27:35.00#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:35.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:35.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:35.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:35.00#ibcon#enter wrdev, iclass 14, count 0 2006.257.07:27:35.00#ibcon#first serial, iclass 14, count 0 2006.257.07:27:35.00#ibcon#enter sib2, iclass 14, count 0 2006.257.07:27:35.00#ibcon#flushed, iclass 14, count 0 2006.257.07:27:35.00#ibcon#about to write, iclass 14, count 0 2006.257.07:27:35.00#ibcon#wrote, iclass 14, count 0 2006.257.07:27:35.00#ibcon#about to read 3, iclass 14, count 0 2006.257.07:27:35.02#ibcon#read 3, iclass 14, count 0 2006.257.07:27:35.02#ibcon#about to read 4, iclass 14, count 0 2006.257.07:27:35.02#ibcon#read 4, iclass 14, count 0 2006.257.07:27:35.02#ibcon#about to read 5, iclass 14, count 0 2006.257.07:27:35.02#ibcon#read 5, iclass 14, count 0 2006.257.07:27:35.02#ibcon#about to read 6, iclass 14, count 0 2006.257.07:27:35.02#ibcon#read 6, iclass 14, count 0 2006.257.07:27:35.02#ibcon#end of sib2, iclass 14, count 0 2006.257.07:27:35.02#ibcon#*mode == 0, iclass 14, count 0 2006.257.07:27:35.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.07:27:35.02#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.07:27:35.02#ibcon#*before write, iclass 14, count 0 2006.257.07:27:35.02#ibcon#enter sib2, iclass 14, count 0 2006.257.07:27:35.02#ibcon#flushed, iclass 14, count 0 2006.257.07:27:35.02#ibcon#about to write, iclass 14, count 0 2006.257.07:27:35.02#ibcon#wrote, iclass 14, count 0 2006.257.07:27:35.02#ibcon#about to read 3, iclass 14, count 0 2006.257.07:27:35.06#ibcon#read 3, iclass 14, count 0 2006.257.07:27:35.06#ibcon#about to read 4, iclass 14, count 0 2006.257.07:27:35.06#ibcon#read 4, iclass 14, count 0 2006.257.07:27:35.06#ibcon#about to read 5, iclass 14, count 0 2006.257.07:27:35.06#ibcon#read 5, iclass 14, count 0 2006.257.07:27:35.06#ibcon#about to read 6, iclass 14, count 0 2006.257.07:27:35.06#ibcon#read 6, iclass 14, count 0 2006.257.07:27:35.06#ibcon#end of sib2, iclass 14, count 0 2006.257.07:27:35.06#ibcon#*after write, iclass 14, count 0 2006.257.07:27:35.06#ibcon#*before return 0, iclass 14, count 0 2006.257.07:27:35.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:35.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:35.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.07:27:35.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.07:27:35.06$vck44/va=3,8 2006.257.07:27:35.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.07:27:35.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.07:27:35.06#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:35.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:35.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:35.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:35.12#ibcon#enter wrdev, iclass 16, count 2 2006.257.07:27:35.12#ibcon#first serial, iclass 16, count 2 2006.257.07:27:35.12#ibcon#enter sib2, iclass 16, count 2 2006.257.07:27:35.12#ibcon#flushed, iclass 16, count 2 2006.257.07:27:35.12#ibcon#about to write, iclass 16, count 2 2006.257.07:27:35.12#ibcon#wrote, iclass 16, count 2 2006.257.07:27:35.12#ibcon#about to read 3, iclass 16, count 2 2006.257.07:27:35.14#ibcon#read 3, iclass 16, count 2 2006.257.07:27:35.14#ibcon#about to read 4, iclass 16, count 2 2006.257.07:27:35.14#ibcon#read 4, iclass 16, count 2 2006.257.07:27:35.14#ibcon#about to read 5, iclass 16, count 2 2006.257.07:27:35.14#ibcon#read 5, iclass 16, count 2 2006.257.07:27:35.14#ibcon#about to read 6, iclass 16, count 2 2006.257.07:27:35.14#ibcon#read 6, iclass 16, count 2 2006.257.07:27:35.14#ibcon#end of sib2, iclass 16, count 2 2006.257.07:27:35.14#ibcon#*mode == 0, iclass 16, count 2 2006.257.07:27:35.14#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.07:27:35.14#ibcon#[25=AT03-08\r\n] 2006.257.07:27:35.14#ibcon#*before write, iclass 16, count 2 2006.257.07:27:35.14#ibcon#enter sib2, iclass 16, count 2 2006.257.07:27:35.14#ibcon#flushed, iclass 16, count 2 2006.257.07:27:35.14#ibcon#about to write, iclass 16, count 2 2006.257.07:27:35.14#ibcon#wrote, iclass 16, count 2 2006.257.07:27:35.14#ibcon#about to read 3, iclass 16, count 2 2006.257.07:27:35.17#ibcon#read 3, iclass 16, count 2 2006.257.07:27:35.17#ibcon#about to read 4, iclass 16, count 2 2006.257.07:27:35.17#ibcon#read 4, iclass 16, count 2 2006.257.07:27:35.17#ibcon#about to read 5, iclass 16, count 2 2006.257.07:27:35.17#ibcon#read 5, iclass 16, count 2 2006.257.07:27:35.17#ibcon#about to read 6, iclass 16, count 2 2006.257.07:27:35.17#ibcon#read 6, iclass 16, count 2 2006.257.07:27:35.17#ibcon#end of sib2, iclass 16, count 2 2006.257.07:27:35.17#ibcon#*after write, iclass 16, count 2 2006.257.07:27:35.17#ibcon#*before return 0, iclass 16, count 2 2006.257.07:27:35.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:35.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:35.17#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.07:27:35.17#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:35.17#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:35.29#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:35.29#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:35.29#ibcon#enter wrdev, iclass 16, count 0 2006.257.07:27:35.29#ibcon#first serial, iclass 16, count 0 2006.257.07:27:35.29#ibcon#enter sib2, iclass 16, count 0 2006.257.07:27:35.29#ibcon#flushed, iclass 16, count 0 2006.257.07:27:35.29#ibcon#about to write, iclass 16, count 0 2006.257.07:27:35.29#ibcon#wrote, iclass 16, count 0 2006.257.07:27:35.29#ibcon#about to read 3, iclass 16, count 0 2006.257.07:27:35.31#ibcon#read 3, iclass 16, count 0 2006.257.07:27:35.31#ibcon#about to read 4, iclass 16, count 0 2006.257.07:27:35.31#ibcon#read 4, iclass 16, count 0 2006.257.07:27:35.31#ibcon#about to read 5, iclass 16, count 0 2006.257.07:27:35.31#ibcon#read 5, iclass 16, count 0 2006.257.07:27:35.31#ibcon#about to read 6, iclass 16, count 0 2006.257.07:27:35.31#ibcon#read 6, iclass 16, count 0 2006.257.07:27:35.31#ibcon#end of sib2, iclass 16, count 0 2006.257.07:27:35.31#ibcon#*mode == 0, iclass 16, count 0 2006.257.07:27:35.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.07:27:35.31#ibcon#[25=USB\r\n] 2006.257.07:27:35.31#ibcon#*before write, iclass 16, count 0 2006.257.07:27:35.31#ibcon#enter sib2, iclass 16, count 0 2006.257.07:27:35.31#ibcon#flushed, iclass 16, count 0 2006.257.07:27:35.31#ibcon#about to write, iclass 16, count 0 2006.257.07:27:35.31#ibcon#wrote, iclass 16, count 0 2006.257.07:27:35.31#ibcon#about to read 3, iclass 16, count 0 2006.257.07:27:35.34#ibcon#read 3, iclass 16, count 0 2006.257.07:27:35.34#ibcon#about to read 4, iclass 16, count 0 2006.257.07:27:35.34#ibcon#read 4, iclass 16, count 0 2006.257.07:27:35.34#ibcon#about to read 5, iclass 16, count 0 2006.257.07:27:35.34#ibcon#read 5, iclass 16, count 0 2006.257.07:27:35.34#ibcon#about to read 6, iclass 16, count 0 2006.257.07:27:35.34#ibcon#read 6, iclass 16, count 0 2006.257.07:27:35.34#ibcon#end of sib2, iclass 16, count 0 2006.257.07:27:35.34#ibcon#*after write, iclass 16, count 0 2006.257.07:27:35.34#ibcon#*before return 0, iclass 16, count 0 2006.257.07:27:35.34#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:35.34#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:35.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.07:27:35.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.07:27:35.34$vck44/valo=4,624.99 2006.257.07:27:35.34#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.07:27:35.34#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.07:27:35.34#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:35.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:35.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:35.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:35.34#ibcon#enter wrdev, iclass 18, count 0 2006.257.07:27:35.34#ibcon#first serial, iclass 18, count 0 2006.257.07:27:35.34#ibcon#enter sib2, iclass 18, count 0 2006.257.07:27:35.34#ibcon#flushed, iclass 18, count 0 2006.257.07:27:35.34#ibcon#about to write, iclass 18, count 0 2006.257.07:27:35.34#ibcon#wrote, iclass 18, count 0 2006.257.07:27:35.34#ibcon#about to read 3, iclass 18, count 0 2006.257.07:27:35.36#ibcon#read 3, iclass 18, count 0 2006.257.07:27:35.36#ibcon#about to read 4, iclass 18, count 0 2006.257.07:27:35.36#ibcon#read 4, iclass 18, count 0 2006.257.07:27:35.36#ibcon#about to read 5, iclass 18, count 0 2006.257.07:27:35.36#ibcon#read 5, iclass 18, count 0 2006.257.07:27:35.36#ibcon#about to read 6, iclass 18, count 0 2006.257.07:27:35.36#ibcon#read 6, iclass 18, count 0 2006.257.07:27:35.36#ibcon#end of sib2, iclass 18, count 0 2006.257.07:27:35.36#ibcon#*mode == 0, iclass 18, count 0 2006.257.07:27:35.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.07:27:35.36#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.07:27:35.36#ibcon#*before write, iclass 18, count 0 2006.257.07:27:35.36#ibcon#enter sib2, iclass 18, count 0 2006.257.07:27:35.36#ibcon#flushed, iclass 18, count 0 2006.257.07:27:35.36#ibcon#about to write, iclass 18, count 0 2006.257.07:27:35.36#ibcon#wrote, iclass 18, count 0 2006.257.07:27:35.36#ibcon#about to read 3, iclass 18, count 0 2006.257.07:27:35.40#ibcon#read 3, iclass 18, count 0 2006.257.07:27:35.40#ibcon#about to read 4, iclass 18, count 0 2006.257.07:27:35.40#ibcon#read 4, iclass 18, count 0 2006.257.07:27:35.40#ibcon#about to read 5, iclass 18, count 0 2006.257.07:27:35.40#ibcon#read 5, iclass 18, count 0 2006.257.07:27:35.40#ibcon#about to read 6, iclass 18, count 0 2006.257.07:27:35.40#ibcon#read 6, iclass 18, count 0 2006.257.07:27:35.40#ibcon#end of sib2, iclass 18, count 0 2006.257.07:27:35.40#ibcon#*after write, iclass 18, count 0 2006.257.07:27:35.40#ibcon#*before return 0, iclass 18, count 0 2006.257.07:27:35.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:35.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:35.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.07:27:35.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.07:27:35.40$vck44/va=4,7 2006.257.07:27:35.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.07:27:35.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.07:27:35.40#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:35.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:35.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:35.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:35.46#ibcon#enter wrdev, iclass 20, count 2 2006.257.07:27:35.46#ibcon#first serial, iclass 20, count 2 2006.257.07:27:35.46#ibcon#enter sib2, iclass 20, count 2 2006.257.07:27:35.46#ibcon#flushed, iclass 20, count 2 2006.257.07:27:35.46#ibcon#about to write, iclass 20, count 2 2006.257.07:27:35.46#ibcon#wrote, iclass 20, count 2 2006.257.07:27:35.46#ibcon#about to read 3, iclass 20, count 2 2006.257.07:27:35.48#ibcon#read 3, iclass 20, count 2 2006.257.07:27:35.48#ibcon#about to read 4, iclass 20, count 2 2006.257.07:27:35.48#ibcon#read 4, iclass 20, count 2 2006.257.07:27:35.48#ibcon#about to read 5, iclass 20, count 2 2006.257.07:27:35.48#ibcon#read 5, iclass 20, count 2 2006.257.07:27:35.48#ibcon#about to read 6, iclass 20, count 2 2006.257.07:27:35.48#ibcon#read 6, iclass 20, count 2 2006.257.07:27:35.48#ibcon#end of sib2, iclass 20, count 2 2006.257.07:27:35.48#ibcon#*mode == 0, iclass 20, count 2 2006.257.07:27:35.48#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.07:27:35.48#ibcon#[25=AT04-07\r\n] 2006.257.07:27:35.48#ibcon#*before write, iclass 20, count 2 2006.257.07:27:35.48#ibcon#enter sib2, iclass 20, count 2 2006.257.07:27:35.48#ibcon#flushed, iclass 20, count 2 2006.257.07:27:35.48#ibcon#about to write, iclass 20, count 2 2006.257.07:27:35.48#ibcon#wrote, iclass 20, count 2 2006.257.07:27:35.48#ibcon#about to read 3, iclass 20, count 2 2006.257.07:27:35.51#ibcon#read 3, iclass 20, count 2 2006.257.07:27:35.51#ibcon#about to read 4, iclass 20, count 2 2006.257.07:27:35.51#ibcon#read 4, iclass 20, count 2 2006.257.07:27:35.51#ibcon#about to read 5, iclass 20, count 2 2006.257.07:27:35.51#ibcon#read 5, iclass 20, count 2 2006.257.07:27:35.51#ibcon#about to read 6, iclass 20, count 2 2006.257.07:27:35.51#ibcon#read 6, iclass 20, count 2 2006.257.07:27:35.51#ibcon#end of sib2, iclass 20, count 2 2006.257.07:27:35.51#ibcon#*after write, iclass 20, count 2 2006.257.07:27:35.51#ibcon#*before return 0, iclass 20, count 2 2006.257.07:27:35.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:35.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:35.51#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.07:27:35.51#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:35.51#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:35.63#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:35.63#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:35.63#ibcon#enter wrdev, iclass 20, count 0 2006.257.07:27:35.63#ibcon#first serial, iclass 20, count 0 2006.257.07:27:35.63#ibcon#enter sib2, iclass 20, count 0 2006.257.07:27:35.63#ibcon#flushed, iclass 20, count 0 2006.257.07:27:35.63#ibcon#about to write, iclass 20, count 0 2006.257.07:27:35.63#ibcon#wrote, iclass 20, count 0 2006.257.07:27:35.63#ibcon#about to read 3, iclass 20, count 0 2006.257.07:27:35.65#ibcon#read 3, iclass 20, count 0 2006.257.07:27:35.65#ibcon#about to read 4, iclass 20, count 0 2006.257.07:27:35.65#ibcon#read 4, iclass 20, count 0 2006.257.07:27:35.65#ibcon#about to read 5, iclass 20, count 0 2006.257.07:27:35.65#ibcon#read 5, iclass 20, count 0 2006.257.07:27:35.65#ibcon#about to read 6, iclass 20, count 0 2006.257.07:27:35.65#ibcon#read 6, iclass 20, count 0 2006.257.07:27:35.65#ibcon#end of sib2, iclass 20, count 0 2006.257.07:27:35.65#ibcon#*mode == 0, iclass 20, count 0 2006.257.07:27:35.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.07:27:35.65#ibcon#[25=USB\r\n] 2006.257.07:27:35.65#ibcon#*before write, iclass 20, count 0 2006.257.07:27:35.65#ibcon#enter sib2, iclass 20, count 0 2006.257.07:27:35.65#ibcon#flushed, iclass 20, count 0 2006.257.07:27:35.65#ibcon#about to write, iclass 20, count 0 2006.257.07:27:35.65#ibcon#wrote, iclass 20, count 0 2006.257.07:27:35.65#ibcon#about to read 3, iclass 20, count 0 2006.257.07:27:35.68#ibcon#read 3, iclass 20, count 0 2006.257.07:27:35.68#ibcon#about to read 4, iclass 20, count 0 2006.257.07:27:35.68#ibcon#read 4, iclass 20, count 0 2006.257.07:27:35.68#ibcon#about to read 5, iclass 20, count 0 2006.257.07:27:35.68#ibcon#read 5, iclass 20, count 0 2006.257.07:27:35.68#ibcon#about to read 6, iclass 20, count 0 2006.257.07:27:35.68#ibcon#read 6, iclass 20, count 0 2006.257.07:27:35.68#ibcon#end of sib2, iclass 20, count 0 2006.257.07:27:35.68#ibcon#*after write, iclass 20, count 0 2006.257.07:27:35.68#ibcon#*before return 0, iclass 20, count 0 2006.257.07:27:35.68#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:35.68#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:35.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.07:27:35.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.07:27:35.68$vck44/valo=5,734.99 2006.257.07:27:35.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.07:27:35.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.07:27:35.68#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:35.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:35.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:35.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:35.68#ibcon#enter wrdev, iclass 22, count 0 2006.257.07:27:35.68#ibcon#first serial, iclass 22, count 0 2006.257.07:27:35.68#ibcon#enter sib2, iclass 22, count 0 2006.257.07:27:35.68#ibcon#flushed, iclass 22, count 0 2006.257.07:27:35.68#ibcon#about to write, iclass 22, count 0 2006.257.07:27:35.68#ibcon#wrote, iclass 22, count 0 2006.257.07:27:35.68#ibcon#about to read 3, iclass 22, count 0 2006.257.07:27:35.70#ibcon#read 3, iclass 22, count 0 2006.257.07:27:35.70#ibcon#about to read 4, iclass 22, count 0 2006.257.07:27:35.70#ibcon#read 4, iclass 22, count 0 2006.257.07:27:35.70#ibcon#about to read 5, iclass 22, count 0 2006.257.07:27:35.70#ibcon#read 5, iclass 22, count 0 2006.257.07:27:35.70#ibcon#about to read 6, iclass 22, count 0 2006.257.07:27:35.70#ibcon#read 6, iclass 22, count 0 2006.257.07:27:35.70#ibcon#end of sib2, iclass 22, count 0 2006.257.07:27:35.70#ibcon#*mode == 0, iclass 22, count 0 2006.257.07:27:35.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.07:27:35.70#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.07:27:35.70#ibcon#*before write, iclass 22, count 0 2006.257.07:27:35.70#ibcon#enter sib2, iclass 22, count 0 2006.257.07:27:35.70#ibcon#flushed, iclass 22, count 0 2006.257.07:27:35.70#ibcon#about to write, iclass 22, count 0 2006.257.07:27:35.70#ibcon#wrote, iclass 22, count 0 2006.257.07:27:35.70#ibcon#about to read 3, iclass 22, count 0 2006.257.07:27:35.74#ibcon#read 3, iclass 22, count 0 2006.257.07:27:35.74#ibcon#about to read 4, iclass 22, count 0 2006.257.07:27:35.74#ibcon#read 4, iclass 22, count 0 2006.257.07:27:35.74#ibcon#about to read 5, iclass 22, count 0 2006.257.07:27:35.74#ibcon#read 5, iclass 22, count 0 2006.257.07:27:35.74#ibcon#about to read 6, iclass 22, count 0 2006.257.07:27:35.74#ibcon#read 6, iclass 22, count 0 2006.257.07:27:35.74#ibcon#end of sib2, iclass 22, count 0 2006.257.07:27:35.74#ibcon#*after write, iclass 22, count 0 2006.257.07:27:35.74#ibcon#*before return 0, iclass 22, count 0 2006.257.07:27:35.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:35.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:35.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.07:27:35.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.07:27:35.74$vck44/va=5,4 2006.257.07:27:35.74#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.07:27:35.74#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.07:27:35.74#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:35.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:35.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:35.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:35.80#ibcon#enter wrdev, iclass 24, count 2 2006.257.07:27:35.80#ibcon#first serial, iclass 24, count 2 2006.257.07:27:35.80#ibcon#enter sib2, iclass 24, count 2 2006.257.07:27:35.80#ibcon#flushed, iclass 24, count 2 2006.257.07:27:35.80#ibcon#about to write, iclass 24, count 2 2006.257.07:27:35.80#ibcon#wrote, iclass 24, count 2 2006.257.07:27:35.80#ibcon#about to read 3, iclass 24, count 2 2006.257.07:27:35.82#ibcon#read 3, iclass 24, count 2 2006.257.07:27:35.82#ibcon#about to read 4, iclass 24, count 2 2006.257.07:27:35.82#ibcon#read 4, iclass 24, count 2 2006.257.07:27:35.82#ibcon#about to read 5, iclass 24, count 2 2006.257.07:27:35.82#ibcon#read 5, iclass 24, count 2 2006.257.07:27:35.82#ibcon#about to read 6, iclass 24, count 2 2006.257.07:27:35.82#ibcon#read 6, iclass 24, count 2 2006.257.07:27:35.82#ibcon#end of sib2, iclass 24, count 2 2006.257.07:27:35.82#ibcon#*mode == 0, iclass 24, count 2 2006.257.07:27:35.82#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.07:27:35.82#ibcon#[25=AT05-04\r\n] 2006.257.07:27:35.82#ibcon#*before write, iclass 24, count 2 2006.257.07:27:35.82#ibcon#enter sib2, iclass 24, count 2 2006.257.07:27:35.82#ibcon#flushed, iclass 24, count 2 2006.257.07:27:35.82#ibcon#about to write, iclass 24, count 2 2006.257.07:27:35.82#ibcon#wrote, iclass 24, count 2 2006.257.07:27:35.82#ibcon#about to read 3, iclass 24, count 2 2006.257.07:27:35.85#ibcon#read 3, iclass 24, count 2 2006.257.07:27:35.85#ibcon#about to read 4, iclass 24, count 2 2006.257.07:27:35.85#ibcon#read 4, iclass 24, count 2 2006.257.07:27:35.85#ibcon#about to read 5, iclass 24, count 2 2006.257.07:27:35.85#ibcon#read 5, iclass 24, count 2 2006.257.07:27:35.85#ibcon#about to read 6, iclass 24, count 2 2006.257.07:27:35.85#ibcon#read 6, iclass 24, count 2 2006.257.07:27:35.85#ibcon#end of sib2, iclass 24, count 2 2006.257.07:27:35.85#ibcon#*after write, iclass 24, count 2 2006.257.07:27:35.85#ibcon#*before return 0, iclass 24, count 2 2006.257.07:27:35.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:35.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:35.85#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.07:27:35.85#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:35.85#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:35.97#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:35.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:35.97#ibcon#enter wrdev, iclass 24, count 0 2006.257.07:27:35.97#ibcon#first serial, iclass 24, count 0 2006.257.07:27:35.97#ibcon#enter sib2, iclass 24, count 0 2006.257.07:27:35.97#ibcon#flushed, iclass 24, count 0 2006.257.07:27:35.97#ibcon#about to write, iclass 24, count 0 2006.257.07:27:35.97#ibcon#wrote, iclass 24, count 0 2006.257.07:27:35.97#ibcon#about to read 3, iclass 24, count 0 2006.257.07:27:35.99#ibcon#read 3, iclass 24, count 0 2006.257.07:27:35.99#ibcon#about to read 4, iclass 24, count 0 2006.257.07:27:35.99#ibcon#read 4, iclass 24, count 0 2006.257.07:27:35.99#ibcon#about to read 5, iclass 24, count 0 2006.257.07:27:35.99#ibcon#read 5, iclass 24, count 0 2006.257.07:27:35.99#ibcon#about to read 6, iclass 24, count 0 2006.257.07:27:35.99#ibcon#read 6, iclass 24, count 0 2006.257.07:27:35.99#ibcon#end of sib2, iclass 24, count 0 2006.257.07:27:35.99#ibcon#*mode == 0, iclass 24, count 0 2006.257.07:27:35.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.07:27:35.99#ibcon#[25=USB\r\n] 2006.257.07:27:35.99#ibcon#*before write, iclass 24, count 0 2006.257.07:27:35.99#ibcon#enter sib2, iclass 24, count 0 2006.257.07:27:35.99#ibcon#flushed, iclass 24, count 0 2006.257.07:27:35.99#ibcon#about to write, iclass 24, count 0 2006.257.07:27:35.99#ibcon#wrote, iclass 24, count 0 2006.257.07:27:35.99#ibcon#about to read 3, iclass 24, count 0 2006.257.07:27:36.02#ibcon#read 3, iclass 24, count 0 2006.257.07:27:36.02#ibcon#about to read 4, iclass 24, count 0 2006.257.07:27:36.02#ibcon#read 4, iclass 24, count 0 2006.257.07:27:36.02#ibcon#about to read 5, iclass 24, count 0 2006.257.07:27:36.02#ibcon#read 5, iclass 24, count 0 2006.257.07:27:36.02#ibcon#about to read 6, iclass 24, count 0 2006.257.07:27:36.02#ibcon#read 6, iclass 24, count 0 2006.257.07:27:36.02#ibcon#end of sib2, iclass 24, count 0 2006.257.07:27:36.02#ibcon#*after write, iclass 24, count 0 2006.257.07:27:36.02#ibcon#*before return 0, iclass 24, count 0 2006.257.07:27:36.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:36.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:36.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.07:27:36.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.07:27:36.02$vck44/valo=6,814.99 2006.257.07:27:36.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.07:27:36.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.07:27:36.02#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:36.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:36.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:36.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:36.02#ibcon#enter wrdev, iclass 26, count 0 2006.257.07:27:36.02#ibcon#first serial, iclass 26, count 0 2006.257.07:27:36.02#ibcon#enter sib2, iclass 26, count 0 2006.257.07:27:36.02#ibcon#flushed, iclass 26, count 0 2006.257.07:27:36.02#ibcon#about to write, iclass 26, count 0 2006.257.07:27:36.02#ibcon#wrote, iclass 26, count 0 2006.257.07:27:36.02#ibcon#about to read 3, iclass 26, count 0 2006.257.07:27:36.04#ibcon#read 3, iclass 26, count 0 2006.257.07:27:36.04#ibcon#about to read 4, iclass 26, count 0 2006.257.07:27:36.04#ibcon#read 4, iclass 26, count 0 2006.257.07:27:36.04#ibcon#about to read 5, iclass 26, count 0 2006.257.07:27:36.04#ibcon#read 5, iclass 26, count 0 2006.257.07:27:36.04#ibcon#about to read 6, iclass 26, count 0 2006.257.07:27:36.04#ibcon#read 6, iclass 26, count 0 2006.257.07:27:36.04#ibcon#end of sib2, iclass 26, count 0 2006.257.07:27:36.04#ibcon#*mode == 0, iclass 26, count 0 2006.257.07:27:36.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.07:27:36.04#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.07:27:36.04#ibcon#*before write, iclass 26, count 0 2006.257.07:27:36.04#ibcon#enter sib2, iclass 26, count 0 2006.257.07:27:36.04#ibcon#flushed, iclass 26, count 0 2006.257.07:27:36.04#ibcon#about to write, iclass 26, count 0 2006.257.07:27:36.04#ibcon#wrote, iclass 26, count 0 2006.257.07:27:36.04#ibcon#about to read 3, iclass 26, count 0 2006.257.07:27:36.08#ibcon#read 3, iclass 26, count 0 2006.257.07:27:36.08#ibcon#about to read 4, iclass 26, count 0 2006.257.07:27:36.08#ibcon#read 4, iclass 26, count 0 2006.257.07:27:36.08#ibcon#about to read 5, iclass 26, count 0 2006.257.07:27:36.08#ibcon#read 5, iclass 26, count 0 2006.257.07:27:36.08#ibcon#about to read 6, iclass 26, count 0 2006.257.07:27:36.08#ibcon#read 6, iclass 26, count 0 2006.257.07:27:36.08#ibcon#end of sib2, iclass 26, count 0 2006.257.07:27:36.08#ibcon#*after write, iclass 26, count 0 2006.257.07:27:36.08#ibcon#*before return 0, iclass 26, count 0 2006.257.07:27:36.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:36.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:36.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.07:27:36.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.07:27:36.08$vck44/va=6,4 2006.257.07:27:36.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.07:27:36.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.07:27:36.08#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:36.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:36.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:36.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:36.14#ibcon#enter wrdev, iclass 28, count 2 2006.257.07:27:36.14#ibcon#first serial, iclass 28, count 2 2006.257.07:27:36.14#ibcon#enter sib2, iclass 28, count 2 2006.257.07:27:36.14#ibcon#flushed, iclass 28, count 2 2006.257.07:27:36.14#ibcon#about to write, iclass 28, count 2 2006.257.07:27:36.14#ibcon#wrote, iclass 28, count 2 2006.257.07:27:36.14#ibcon#about to read 3, iclass 28, count 2 2006.257.07:27:36.16#ibcon#read 3, iclass 28, count 2 2006.257.07:27:36.16#ibcon#about to read 4, iclass 28, count 2 2006.257.07:27:36.16#ibcon#read 4, iclass 28, count 2 2006.257.07:27:36.16#ibcon#about to read 5, iclass 28, count 2 2006.257.07:27:36.16#ibcon#read 5, iclass 28, count 2 2006.257.07:27:36.16#ibcon#about to read 6, iclass 28, count 2 2006.257.07:27:36.16#ibcon#read 6, iclass 28, count 2 2006.257.07:27:36.16#ibcon#end of sib2, iclass 28, count 2 2006.257.07:27:36.16#ibcon#*mode == 0, iclass 28, count 2 2006.257.07:27:36.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.07:27:36.16#ibcon#[25=AT06-04\r\n] 2006.257.07:27:36.16#ibcon#*before write, iclass 28, count 2 2006.257.07:27:36.16#ibcon#enter sib2, iclass 28, count 2 2006.257.07:27:36.16#ibcon#flushed, iclass 28, count 2 2006.257.07:27:36.16#ibcon#about to write, iclass 28, count 2 2006.257.07:27:36.16#ibcon#wrote, iclass 28, count 2 2006.257.07:27:36.16#ibcon#about to read 3, iclass 28, count 2 2006.257.07:27:36.19#ibcon#read 3, iclass 28, count 2 2006.257.07:27:36.19#ibcon#about to read 4, iclass 28, count 2 2006.257.07:27:36.19#ibcon#read 4, iclass 28, count 2 2006.257.07:27:36.19#ibcon#about to read 5, iclass 28, count 2 2006.257.07:27:36.19#ibcon#read 5, iclass 28, count 2 2006.257.07:27:36.19#ibcon#about to read 6, iclass 28, count 2 2006.257.07:27:36.19#ibcon#read 6, iclass 28, count 2 2006.257.07:27:36.19#ibcon#end of sib2, iclass 28, count 2 2006.257.07:27:36.19#ibcon#*after write, iclass 28, count 2 2006.257.07:27:36.19#ibcon#*before return 0, iclass 28, count 2 2006.257.07:27:36.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:36.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:36.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.07:27:36.19#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:36.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:36.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:36.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:36.31#ibcon#enter wrdev, iclass 28, count 0 2006.257.07:27:36.31#ibcon#first serial, iclass 28, count 0 2006.257.07:27:36.31#ibcon#enter sib2, iclass 28, count 0 2006.257.07:27:36.31#ibcon#flushed, iclass 28, count 0 2006.257.07:27:36.31#ibcon#about to write, iclass 28, count 0 2006.257.07:27:36.31#ibcon#wrote, iclass 28, count 0 2006.257.07:27:36.31#ibcon#about to read 3, iclass 28, count 0 2006.257.07:27:36.33#ibcon#read 3, iclass 28, count 0 2006.257.07:27:36.33#ibcon#about to read 4, iclass 28, count 0 2006.257.07:27:36.33#ibcon#read 4, iclass 28, count 0 2006.257.07:27:36.33#ibcon#about to read 5, iclass 28, count 0 2006.257.07:27:36.33#ibcon#read 5, iclass 28, count 0 2006.257.07:27:36.33#ibcon#about to read 6, iclass 28, count 0 2006.257.07:27:36.33#ibcon#read 6, iclass 28, count 0 2006.257.07:27:36.33#ibcon#end of sib2, iclass 28, count 0 2006.257.07:27:36.33#ibcon#*mode == 0, iclass 28, count 0 2006.257.07:27:36.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.07:27:36.33#ibcon#[25=USB\r\n] 2006.257.07:27:36.33#ibcon#*before write, iclass 28, count 0 2006.257.07:27:36.33#ibcon#enter sib2, iclass 28, count 0 2006.257.07:27:36.33#ibcon#flushed, iclass 28, count 0 2006.257.07:27:36.33#ibcon#about to write, iclass 28, count 0 2006.257.07:27:36.33#ibcon#wrote, iclass 28, count 0 2006.257.07:27:36.33#ibcon#about to read 3, iclass 28, count 0 2006.257.07:27:36.36#ibcon#read 3, iclass 28, count 0 2006.257.07:27:36.36#ibcon#about to read 4, iclass 28, count 0 2006.257.07:27:36.36#ibcon#read 4, iclass 28, count 0 2006.257.07:27:36.36#ibcon#about to read 5, iclass 28, count 0 2006.257.07:27:36.36#ibcon#read 5, iclass 28, count 0 2006.257.07:27:36.36#ibcon#about to read 6, iclass 28, count 0 2006.257.07:27:36.36#ibcon#read 6, iclass 28, count 0 2006.257.07:27:36.36#ibcon#end of sib2, iclass 28, count 0 2006.257.07:27:36.36#ibcon#*after write, iclass 28, count 0 2006.257.07:27:36.36#ibcon#*before return 0, iclass 28, count 0 2006.257.07:27:36.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:36.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:36.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.07:27:36.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.07:27:36.36$vck44/valo=7,864.99 2006.257.07:27:36.36#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.07:27:36.36#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.07:27:36.36#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:36.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:36.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:36.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:36.36#ibcon#enter wrdev, iclass 30, count 0 2006.257.07:27:36.36#ibcon#first serial, iclass 30, count 0 2006.257.07:27:36.36#ibcon#enter sib2, iclass 30, count 0 2006.257.07:27:36.36#ibcon#flushed, iclass 30, count 0 2006.257.07:27:36.36#ibcon#about to write, iclass 30, count 0 2006.257.07:27:36.36#ibcon#wrote, iclass 30, count 0 2006.257.07:27:36.36#ibcon#about to read 3, iclass 30, count 0 2006.257.07:27:36.38#ibcon#read 3, iclass 30, count 0 2006.257.07:27:36.38#ibcon#about to read 4, iclass 30, count 0 2006.257.07:27:36.38#ibcon#read 4, iclass 30, count 0 2006.257.07:27:36.38#ibcon#about to read 5, iclass 30, count 0 2006.257.07:27:36.38#ibcon#read 5, iclass 30, count 0 2006.257.07:27:36.38#ibcon#about to read 6, iclass 30, count 0 2006.257.07:27:36.38#ibcon#read 6, iclass 30, count 0 2006.257.07:27:36.38#ibcon#end of sib2, iclass 30, count 0 2006.257.07:27:36.38#ibcon#*mode == 0, iclass 30, count 0 2006.257.07:27:36.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.07:27:36.38#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.07:27:36.38#ibcon#*before write, iclass 30, count 0 2006.257.07:27:36.38#ibcon#enter sib2, iclass 30, count 0 2006.257.07:27:36.38#ibcon#flushed, iclass 30, count 0 2006.257.07:27:36.38#ibcon#about to write, iclass 30, count 0 2006.257.07:27:36.38#ibcon#wrote, iclass 30, count 0 2006.257.07:27:36.38#ibcon#about to read 3, iclass 30, count 0 2006.257.07:27:36.42#ibcon#read 3, iclass 30, count 0 2006.257.07:27:36.42#ibcon#about to read 4, iclass 30, count 0 2006.257.07:27:36.42#ibcon#read 4, iclass 30, count 0 2006.257.07:27:36.42#ibcon#about to read 5, iclass 30, count 0 2006.257.07:27:36.42#ibcon#read 5, iclass 30, count 0 2006.257.07:27:36.42#ibcon#about to read 6, iclass 30, count 0 2006.257.07:27:36.42#ibcon#read 6, iclass 30, count 0 2006.257.07:27:36.42#ibcon#end of sib2, iclass 30, count 0 2006.257.07:27:36.42#ibcon#*after write, iclass 30, count 0 2006.257.07:27:36.42#ibcon#*before return 0, iclass 30, count 0 2006.257.07:27:36.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:36.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:36.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.07:27:36.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.07:27:36.42$vck44/va=7,4 2006.257.07:27:36.42#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.07:27:36.42#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.07:27:36.42#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:36.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:36.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:36.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:36.48#ibcon#enter wrdev, iclass 32, count 2 2006.257.07:27:36.48#ibcon#first serial, iclass 32, count 2 2006.257.07:27:36.48#ibcon#enter sib2, iclass 32, count 2 2006.257.07:27:36.48#ibcon#flushed, iclass 32, count 2 2006.257.07:27:36.48#ibcon#about to write, iclass 32, count 2 2006.257.07:27:36.48#ibcon#wrote, iclass 32, count 2 2006.257.07:27:36.48#ibcon#about to read 3, iclass 32, count 2 2006.257.07:27:36.50#ibcon#read 3, iclass 32, count 2 2006.257.07:27:36.50#ibcon#about to read 4, iclass 32, count 2 2006.257.07:27:36.50#ibcon#read 4, iclass 32, count 2 2006.257.07:27:36.50#ibcon#about to read 5, iclass 32, count 2 2006.257.07:27:36.50#ibcon#read 5, iclass 32, count 2 2006.257.07:27:36.50#ibcon#about to read 6, iclass 32, count 2 2006.257.07:27:36.50#ibcon#read 6, iclass 32, count 2 2006.257.07:27:36.50#ibcon#end of sib2, iclass 32, count 2 2006.257.07:27:36.50#ibcon#*mode == 0, iclass 32, count 2 2006.257.07:27:36.50#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.07:27:36.50#ibcon#[25=AT07-04\r\n] 2006.257.07:27:36.50#ibcon#*before write, iclass 32, count 2 2006.257.07:27:36.50#ibcon#enter sib2, iclass 32, count 2 2006.257.07:27:36.50#ibcon#flushed, iclass 32, count 2 2006.257.07:27:36.50#ibcon#about to write, iclass 32, count 2 2006.257.07:27:36.50#ibcon#wrote, iclass 32, count 2 2006.257.07:27:36.50#ibcon#about to read 3, iclass 32, count 2 2006.257.07:27:36.53#ibcon#read 3, iclass 32, count 2 2006.257.07:27:36.53#ibcon#about to read 4, iclass 32, count 2 2006.257.07:27:36.53#ibcon#read 4, iclass 32, count 2 2006.257.07:27:36.53#ibcon#about to read 5, iclass 32, count 2 2006.257.07:27:36.53#ibcon#read 5, iclass 32, count 2 2006.257.07:27:36.53#ibcon#about to read 6, iclass 32, count 2 2006.257.07:27:36.53#ibcon#read 6, iclass 32, count 2 2006.257.07:27:36.53#ibcon#end of sib2, iclass 32, count 2 2006.257.07:27:36.53#ibcon#*after write, iclass 32, count 2 2006.257.07:27:36.53#ibcon#*before return 0, iclass 32, count 2 2006.257.07:27:36.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:36.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:36.53#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.07:27:36.53#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:36.53#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:36.65#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:36.65#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:36.65#ibcon#enter wrdev, iclass 32, count 0 2006.257.07:27:36.65#ibcon#first serial, iclass 32, count 0 2006.257.07:27:36.65#ibcon#enter sib2, iclass 32, count 0 2006.257.07:27:36.65#ibcon#flushed, iclass 32, count 0 2006.257.07:27:36.65#ibcon#about to write, iclass 32, count 0 2006.257.07:27:36.65#ibcon#wrote, iclass 32, count 0 2006.257.07:27:36.65#ibcon#about to read 3, iclass 32, count 0 2006.257.07:27:36.67#ibcon#read 3, iclass 32, count 0 2006.257.07:27:36.67#ibcon#about to read 4, iclass 32, count 0 2006.257.07:27:36.67#ibcon#read 4, iclass 32, count 0 2006.257.07:27:36.67#ibcon#about to read 5, iclass 32, count 0 2006.257.07:27:36.67#ibcon#read 5, iclass 32, count 0 2006.257.07:27:36.67#ibcon#about to read 6, iclass 32, count 0 2006.257.07:27:36.67#ibcon#read 6, iclass 32, count 0 2006.257.07:27:36.67#ibcon#end of sib2, iclass 32, count 0 2006.257.07:27:36.67#ibcon#*mode == 0, iclass 32, count 0 2006.257.07:27:36.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.07:27:36.67#ibcon#[25=USB\r\n] 2006.257.07:27:36.67#ibcon#*before write, iclass 32, count 0 2006.257.07:27:36.67#ibcon#enter sib2, iclass 32, count 0 2006.257.07:27:36.67#ibcon#flushed, iclass 32, count 0 2006.257.07:27:36.67#ibcon#about to write, iclass 32, count 0 2006.257.07:27:36.67#ibcon#wrote, iclass 32, count 0 2006.257.07:27:36.67#ibcon#about to read 3, iclass 32, count 0 2006.257.07:27:36.70#ibcon#read 3, iclass 32, count 0 2006.257.07:27:36.70#ibcon#about to read 4, iclass 32, count 0 2006.257.07:27:36.70#ibcon#read 4, iclass 32, count 0 2006.257.07:27:36.70#ibcon#about to read 5, iclass 32, count 0 2006.257.07:27:36.70#ibcon#read 5, iclass 32, count 0 2006.257.07:27:36.70#ibcon#about to read 6, iclass 32, count 0 2006.257.07:27:36.70#ibcon#read 6, iclass 32, count 0 2006.257.07:27:36.70#ibcon#end of sib2, iclass 32, count 0 2006.257.07:27:36.70#ibcon#*after write, iclass 32, count 0 2006.257.07:27:36.70#ibcon#*before return 0, iclass 32, count 0 2006.257.07:27:36.70#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:36.70#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:36.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.07:27:36.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.07:27:36.70$vck44/valo=8,884.99 2006.257.07:27:36.70#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.07:27:36.70#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.07:27:36.70#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:36.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:36.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:36.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:36.70#ibcon#enter wrdev, iclass 34, count 0 2006.257.07:27:36.70#ibcon#first serial, iclass 34, count 0 2006.257.07:27:36.70#ibcon#enter sib2, iclass 34, count 0 2006.257.07:27:36.70#ibcon#flushed, iclass 34, count 0 2006.257.07:27:36.70#ibcon#about to write, iclass 34, count 0 2006.257.07:27:36.70#ibcon#wrote, iclass 34, count 0 2006.257.07:27:36.70#ibcon#about to read 3, iclass 34, count 0 2006.257.07:27:36.72#ibcon#read 3, iclass 34, count 0 2006.257.07:27:36.72#ibcon#about to read 4, iclass 34, count 0 2006.257.07:27:36.72#ibcon#read 4, iclass 34, count 0 2006.257.07:27:36.72#ibcon#about to read 5, iclass 34, count 0 2006.257.07:27:36.72#ibcon#read 5, iclass 34, count 0 2006.257.07:27:36.72#ibcon#about to read 6, iclass 34, count 0 2006.257.07:27:36.72#ibcon#read 6, iclass 34, count 0 2006.257.07:27:36.72#ibcon#end of sib2, iclass 34, count 0 2006.257.07:27:36.72#ibcon#*mode == 0, iclass 34, count 0 2006.257.07:27:36.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.07:27:36.72#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.07:27:36.72#ibcon#*before write, iclass 34, count 0 2006.257.07:27:36.72#ibcon#enter sib2, iclass 34, count 0 2006.257.07:27:36.72#ibcon#flushed, iclass 34, count 0 2006.257.07:27:36.72#ibcon#about to write, iclass 34, count 0 2006.257.07:27:36.72#ibcon#wrote, iclass 34, count 0 2006.257.07:27:36.72#ibcon#about to read 3, iclass 34, count 0 2006.257.07:27:36.76#ibcon#read 3, iclass 34, count 0 2006.257.07:27:36.76#ibcon#about to read 4, iclass 34, count 0 2006.257.07:27:36.76#ibcon#read 4, iclass 34, count 0 2006.257.07:27:36.76#ibcon#about to read 5, iclass 34, count 0 2006.257.07:27:36.76#ibcon#read 5, iclass 34, count 0 2006.257.07:27:36.76#ibcon#about to read 6, iclass 34, count 0 2006.257.07:27:36.76#ibcon#read 6, iclass 34, count 0 2006.257.07:27:36.76#ibcon#end of sib2, iclass 34, count 0 2006.257.07:27:36.76#ibcon#*after write, iclass 34, count 0 2006.257.07:27:36.76#ibcon#*before return 0, iclass 34, count 0 2006.257.07:27:36.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:36.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:36.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.07:27:36.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.07:27:36.76$vck44/va=8,4 2006.257.07:27:36.76#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.07:27:36.76#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.07:27:36.76#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:36.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:27:36.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:27:36.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:27:36.82#ibcon#enter wrdev, iclass 36, count 2 2006.257.07:27:36.82#ibcon#first serial, iclass 36, count 2 2006.257.07:27:36.82#ibcon#enter sib2, iclass 36, count 2 2006.257.07:27:36.82#ibcon#flushed, iclass 36, count 2 2006.257.07:27:36.82#ibcon#about to write, iclass 36, count 2 2006.257.07:27:36.82#ibcon#wrote, iclass 36, count 2 2006.257.07:27:36.82#ibcon#about to read 3, iclass 36, count 2 2006.257.07:27:36.84#ibcon#read 3, iclass 36, count 2 2006.257.07:27:36.84#ibcon#about to read 4, iclass 36, count 2 2006.257.07:27:36.84#ibcon#read 4, iclass 36, count 2 2006.257.07:27:36.84#ibcon#about to read 5, iclass 36, count 2 2006.257.07:27:36.84#ibcon#read 5, iclass 36, count 2 2006.257.07:27:36.84#ibcon#about to read 6, iclass 36, count 2 2006.257.07:27:36.84#ibcon#read 6, iclass 36, count 2 2006.257.07:27:36.84#ibcon#end of sib2, iclass 36, count 2 2006.257.07:27:36.84#ibcon#*mode == 0, iclass 36, count 2 2006.257.07:27:36.84#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.07:27:36.84#ibcon#[25=AT08-04\r\n] 2006.257.07:27:36.84#ibcon#*before write, iclass 36, count 2 2006.257.07:27:36.84#ibcon#enter sib2, iclass 36, count 2 2006.257.07:27:36.84#ibcon#flushed, iclass 36, count 2 2006.257.07:27:36.84#ibcon#about to write, iclass 36, count 2 2006.257.07:27:36.84#ibcon#wrote, iclass 36, count 2 2006.257.07:27:36.84#ibcon#about to read 3, iclass 36, count 2 2006.257.07:27:36.87#ibcon#read 3, iclass 36, count 2 2006.257.07:27:36.87#ibcon#about to read 4, iclass 36, count 2 2006.257.07:27:36.87#ibcon#read 4, iclass 36, count 2 2006.257.07:27:36.87#ibcon#about to read 5, iclass 36, count 2 2006.257.07:27:36.87#ibcon#read 5, iclass 36, count 2 2006.257.07:27:36.87#ibcon#about to read 6, iclass 36, count 2 2006.257.07:27:36.87#ibcon#read 6, iclass 36, count 2 2006.257.07:27:36.87#ibcon#end of sib2, iclass 36, count 2 2006.257.07:27:36.87#ibcon#*after write, iclass 36, count 2 2006.257.07:27:36.87#ibcon#*before return 0, iclass 36, count 2 2006.257.07:27:36.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:27:36.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:27:36.87#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.07:27:36.87#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:36.87#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:27:36.99#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:27:36.99#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:27:36.99#ibcon#enter wrdev, iclass 36, count 0 2006.257.07:27:36.99#ibcon#first serial, iclass 36, count 0 2006.257.07:27:36.99#ibcon#enter sib2, iclass 36, count 0 2006.257.07:27:36.99#ibcon#flushed, iclass 36, count 0 2006.257.07:27:36.99#ibcon#about to write, iclass 36, count 0 2006.257.07:27:36.99#ibcon#wrote, iclass 36, count 0 2006.257.07:27:36.99#ibcon#about to read 3, iclass 36, count 0 2006.257.07:27:37.01#ibcon#read 3, iclass 36, count 0 2006.257.07:27:37.01#ibcon#about to read 4, iclass 36, count 0 2006.257.07:27:37.01#ibcon#read 4, iclass 36, count 0 2006.257.07:27:37.01#ibcon#about to read 5, iclass 36, count 0 2006.257.07:27:37.01#ibcon#read 5, iclass 36, count 0 2006.257.07:27:37.01#ibcon#about to read 6, iclass 36, count 0 2006.257.07:27:37.01#ibcon#read 6, iclass 36, count 0 2006.257.07:27:37.01#ibcon#end of sib2, iclass 36, count 0 2006.257.07:27:37.01#ibcon#*mode == 0, iclass 36, count 0 2006.257.07:27:37.01#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.07:27:37.01#ibcon#[25=USB\r\n] 2006.257.07:27:37.01#ibcon#*before write, iclass 36, count 0 2006.257.07:27:37.01#ibcon#enter sib2, iclass 36, count 0 2006.257.07:27:37.01#ibcon#flushed, iclass 36, count 0 2006.257.07:27:37.01#ibcon#about to write, iclass 36, count 0 2006.257.07:27:37.01#ibcon#wrote, iclass 36, count 0 2006.257.07:27:37.01#ibcon#about to read 3, iclass 36, count 0 2006.257.07:27:37.04#ibcon#read 3, iclass 36, count 0 2006.257.07:27:37.04#ibcon#about to read 4, iclass 36, count 0 2006.257.07:27:37.04#ibcon#read 4, iclass 36, count 0 2006.257.07:27:37.04#ibcon#about to read 5, iclass 36, count 0 2006.257.07:27:37.04#ibcon#read 5, iclass 36, count 0 2006.257.07:27:37.04#ibcon#about to read 6, iclass 36, count 0 2006.257.07:27:37.04#ibcon#read 6, iclass 36, count 0 2006.257.07:27:37.04#ibcon#end of sib2, iclass 36, count 0 2006.257.07:27:37.04#ibcon#*after write, iclass 36, count 0 2006.257.07:27:37.04#ibcon#*before return 0, iclass 36, count 0 2006.257.07:27:37.04#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:27:37.04#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:27:37.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.07:27:37.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.07:27:37.04$vck44/vblo=1,629.99 2006.257.07:27:37.04#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.07:27:37.04#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.07:27:37.04#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:37.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:27:37.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:27:37.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:27:37.04#ibcon#enter wrdev, iclass 38, count 0 2006.257.07:27:37.04#ibcon#first serial, iclass 38, count 0 2006.257.07:27:37.04#ibcon#enter sib2, iclass 38, count 0 2006.257.07:27:37.04#ibcon#flushed, iclass 38, count 0 2006.257.07:27:37.04#ibcon#about to write, iclass 38, count 0 2006.257.07:27:37.04#ibcon#wrote, iclass 38, count 0 2006.257.07:27:37.04#ibcon#about to read 3, iclass 38, count 0 2006.257.07:27:37.06#ibcon#read 3, iclass 38, count 0 2006.257.07:27:37.06#ibcon#about to read 4, iclass 38, count 0 2006.257.07:27:37.06#ibcon#read 4, iclass 38, count 0 2006.257.07:27:37.06#ibcon#about to read 5, iclass 38, count 0 2006.257.07:27:37.06#ibcon#read 5, iclass 38, count 0 2006.257.07:27:37.06#ibcon#about to read 6, iclass 38, count 0 2006.257.07:27:37.06#ibcon#read 6, iclass 38, count 0 2006.257.07:27:37.06#ibcon#end of sib2, iclass 38, count 0 2006.257.07:27:37.06#ibcon#*mode == 0, iclass 38, count 0 2006.257.07:27:37.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.07:27:37.06#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.07:27:37.06#ibcon#*before write, iclass 38, count 0 2006.257.07:27:37.06#ibcon#enter sib2, iclass 38, count 0 2006.257.07:27:37.06#ibcon#flushed, iclass 38, count 0 2006.257.07:27:37.06#ibcon#about to write, iclass 38, count 0 2006.257.07:27:37.06#ibcon#wrote, iclass 38, count 0 2006.257.07:27:37.06#ibcon#about to read 3, iclass 38, count 0 2006.257.07:27:37.10#ibcon#read 3, iclass 38, count 0 2006.257.07:27:37.10#ibcon#about to read 4, iclass 38, count 0 2006.257.07:27:37.10#ibcon#read 4, iclass 38, count 0 2006.257.07:27:37.10#ibcon#about to read 5, iclass 38, count 0 2006.257.07:27:37.10#ibcon#read 5, iclass 38, count 0 2006.257.07:27:37.10#ibcon#about to read 6, iclass 38, count 0 2006.257.07:27:37.10#ibcon#read 6, iclass 38, count 0 2006.257.07:27:37.10#ibcon#end of sib2, iclass 38, count 0 2006.257.07:27:37.10#ibcon#*after write, iclass 38, count 0 2006.257.07:27:37.10#ibcon#*before return 0, iclass 38, count 0 2006.257.07:27:37.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:27:37.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:27:37.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.07:27:37.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.07:27:37.10$vck44/vb=1,4 2006.257.07:27:37.10#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.07:27:37.10#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.07:27:37.10#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:37.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:27:37.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:27:37.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:27:37.10#ibcon#enter wrdev, iclass 40, count 2 2006.257.07:27:37.10#ibcon#first serial, iclass 40, count 2 2006.257.07:27:37.10#ibcon#enter sib2, iclass 40, count 2 2006.257.07:27:37.10#ibcon#flushed, iclass 40, count 2 2006.257.07:27:37.10#ibcon#about to write, iclass 40, count 2 2006.257.07:27:37.10#ibcon#wrote, iclass 40, count 2 2006.257.07:27:37.10#ibcon#about to read 3, iclass 40, count 2 2006.257.07:27:37.12#ibcon#read 3, iclass 40, count 2 2006.257.07:27:37.12#ibcon#about to read 4, iclass 40, count 2 2006.257.07:27:37.12#ibcon#read 4, iclass 40, count 2 2006.257.07:27:37.12#ibcon#about to read 5, iclass 40, count 2 2006.257.07:27:37.12#ibcon#read 5, iclass 40, count 2 2006.257.07:27:37.12#ibcon#about to read 6, iclass 40, count 2 2006.257.07:27:37.12#ibcon#read 6, iclass 40, count 2 2006.257.07:27:37.12#ibcon#end of sib2, iclass 40, count 2 2006.257.07:27:37.12#ibcon#*mode == 0, iclass 40, count 2 2006.257.07:27:37.12#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.07:27:37.12#ibcon#[27=AT01-04\r\n] 2006.257.07:27:37.12#ibcon#*before write, iclass 40, count 2 2006.257.07:27:37.12#ibcon#enter sib2, iclass 40, count 2 2006.257.07:27:37.12#ibcon#flushed, iclass 40, count 2 2006.257.07:27:37.12#ibcon#about to write, iclass 40, count 2 2006.257.07:27:37.12#ibcon#wrote, iclass 40, count 2 2006.257.07:27:37.12#ibcon#about to read 3, iclass 40, count 2 2006.257.07:27:37.15#ibcon#read 3, iclass 40, count 2 2006.257.07:27:37.15#ibcon#about to read 4, iclass 40, count 2 2006.257.07:27:37.15#ibcon#read 4, iclass 40, count 2 2006.257.07:27:37.15#ibcon#about to read 5, iclass 40, count 2 2006.257.07:27:37.15#ibcon#read 5, iclass 40, count 2 2006.257.07:27:37.15#ibcon#about to read 6, iclass 40, count 2 2006.257.07:27:37.15#ibcon#read 6, iclass 40, count 2 2006.257.07:27:37.15#ibcon#end of sib2, iclass 40, count 2 2006.257.07:27:37.15#ibcon#*after write, iclass 40, count 2 2006.257.07:27:37.15#ibcon#*before return 0, iclass 40, count 2 2006.257.07:27:37.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:27:37.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:27:37.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.07:27:37.15#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:37.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:27:37.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:27:37.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:27:37.27#ibcon#enter wrdev, iclass 40, count 0 2006.257.07:27:37.27#ibcon#first serial, iclass 40, count 0 2006.257.07:27:37.27#ibcon#enter sib2, iclass 40, count 0 2006.257.07:27:37.27#ibcon#flushed, iclass 40, count 0 2006.257.07:27:37.27#ibcon#about to write, iclass 40, count 0 2006.257.07:27:37.27#ibcon#wrote, iclass 40, count 0 2006.257.07:27:37.27#ibcon#about to read 3, iclass 40, count 0 2006.257.07:27:37.29#ibcon#read 3, iclass 40, count 0 2006.257.07:27:37.29#ibcon#about to read 4, iclass 40, count 0 2006.257.07:27:37.29#ibcon#read 4, iclass 40, count 0 2006.257.07:27:37.29#ibcon#about to read 5, iclass 40, count 0 2006.257.07:27:37.29#ibcon#read 5, iclass 40, count 0 2006.257.07:27:37.29#ibcon#about to read 6, iclass 40, count 0 2006.257.07:27:37.29#ibcon#read 6, iclass 40, count 0 2006.257.07:27:37.29#ibcon#end of sib2, iclass 40, count 0 2006.257.07:27:37.29#ibcon#*mode == 0, iclass 40, count 0 2006.257.07:27:37.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.07:27:37.29#ibcon#[27=USB\r\n] 2006.257.07:27:37.29#ibcon#*before write, iclass 40, count 0 2006.257.07:27:37.29#ibcon#enter sib2, iclass 40, count 0 2006.257.07:27:37.29#ibcon#flushed, iclass 40, count 0 2006.257.07:27:37.29#ibcon#about to write, iclass 40, count 0 2006.257.07:27:37.29#ibcon#wrote, iclass 40, count 0 2006.257.07:27:37.29#ibcon#about to read 3, iclass 40, count 0 2006.257.07:27:37.32#ibcon#read 3, iclass 40, count 0 2006.257.07:27:37.32#ibcon#about to read 4, iclass 40, count 0 2006.257.07:27:37.32#ibcon#read 4, iclass 40, count 0 2006.257.07:27:37.32#ibcon#about to read 5, iclass 40, count 0 2006.257.07:27:37.32#ibcon#read 5, iclass 40, count 0 2006.257.07:27:37.32#ibcon#about to read 6, iclass 40, count 0 2006.257.07:27:37.32#ibcon#read 6, iclass 40, count 0 2006.257.07:27:37.32#ibcon#end of sib2, iclass 40, count 0 2006.257.07:27:37.32#ibcon#*after write, iclass 40, count 0 2006.257.07:27:37.32#ibcon#*before return 0, iclass 40, count 0 2006.257.07:27:37.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:27:37.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:27:37.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.07:27:37.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.07:27:37.32$vck44/vblo=2,634.99 2006.257.07:27:37.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.07:27:37.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.07:27:37.32#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:37.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:37.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:37.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:37.32#ibcon#enter wrdev, iclass 4, count 0 2006.257.07:27:37.32#ibcon#first serial, iclass 4, count 0 2006.257.07:27:37.32#ibcon#enter sib2, iclass 4, count 0 2006.257.07:27:37.32#ibcon#flushed, iclass 4, count 0 2006.257.07:27:37.32#ibcon#about to write, iclass 4, count 0 2006.257.07:27:37.32#ibcon#wrote, iclass 4, count 0 2006.257.07:27:37.32#ibcon#about to read 3, iclass 4, count 0 2006.257.07:27:37.34#ibcon#read 3, iclass 4, count 0 2006.257.07:27:37.34#ibcon#about to read 4, iclass 4, count 0 2006.257.07:27:37.34#ibcon#read 4, iclass 4, count 0 2006.257.07:27:37.34#ibcon#about to read 5, iclass 4, count 0 2006.257.07:27:37.34#ibcon#read 5, iclass 4, count 0 2006.257.07:27:37.34#ibcon#about to read 6, iclass 4, count 0 2006.257.07:27:37.34#ibcon#read 6, iclass 4, count 0 2006.257.07:27:37.34#ibcon#end of sib2, iclass 4, count 0 2006.257.07:27:37.34#ibcon#*mode == 0, iclass 4, count 0 2006.257.07:27:37.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.07:27:37.34#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.07:27:37.34#ibcon#*before write, iclass 4, count 0 2006.257.07:27:37.34#ibcon#enter sib2, iclass 4, count 0 2006.257.07:27:37.34#ibcon#flushed, iclass 4, count 0 2006.257.07:27:37.34#ibcon#about to write, iclass 4, count 0 2006.257.07:27:37.34#ibcon#wrote, iclass 4, count 0 2006.257.07:27:37.34#ibcon#about to read 3, iclass 4, count 0 2006.257.07:27:37.38#ibcon#read 3, iclass 4, count 0 2006.257.07:27:37.38#ibcon#about to read 4, iclass 4, count 0 2006.257.07:27:37.38#ibcon#read 4, iclass 4, count 0 2006.257.07:27:37.38#ibcon#about to read 5, iclass 4, count 0 2006.257.07:27:37.38#ibcon#read 5, iclass 4, count 0 2006.257.07:27:37.38#ibcon#about to read 6, iclass 4, count 0 2006.257.07:27:37.38#ibcon#read 6, iclass 4, count 0 2006.257.07:27:37.38#ibcon#end of sib2, iclass 4, count 0 2006.257.07:27:37.38#ibcon#*after write, iclass 4, count 0 2006.257.07:27:37.38#ibcon#*before return 0, iclass 4, count 0 2006.257.07:27:37.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:37.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:27:37.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.07:27:37.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.07:27:37.38$vck44/vb=2,5 2006.257.07:27:37.38#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.07:27:37.38#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.07:27:37.38#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:37.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:37.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:37.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:37.44#ibcon#enter wrdev, iclass 6, count 2 2006.257.07:27:37.44#ibcon#first serial, iclass 6, count 2 2006.257.07:27:37.44#ibcon#enter sib2, iclass 6, count 2 2006.257.07:27:37.44#ibcon#flushed, iclass 6, count 2 2006.257.07:27:37.44#ibcon#about to write, iclass 6, count 2 2006.257.07:27:37.44#ibcon#wrote, iclass 6, count 2 2006.257.07:27:37.44#ibcon#about to read 3, iclass 6, count 2 2006.257.07:27:37.46#ibcon#read 3, iclass 6, count 2 2006.257.07:27:37.46#ibcon#about to read 4, iclass 6, count 2 2006.257.07:27:37.46#ibcon#read 4, iclass 6, count 2 2006.257.07:27:37.46#ibcon#about to read 5, iclass 6, count 2 2006.257.07:27:37.46#ibcon#read 5, iclass 6, count 2 2006.257.07:27:37.46#ibcon#about to read 6, iclass 6, count 2 2006.257.07:27:37.46#ibcon#read 6, iclass 6, count 2 2006.257.07:27:37.46#ibcon#end of sib2, iclass 6, count 2 2006.257.07:27:37.46#ibcon#*mode == 0, iclass 6, count 2 2006.257.07:27:37.46#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.07:27:37.46#ibcon#[27=AT02-05\r\n] 2006.257.07:27:37.46#ibcon#*before write, iclass 6, count 2 2006.257.07:27:37.46#ibcon#enter sib2, iclass 6, count 2 2006.257.07:27:37.46#ibcon#flushed, iclass 6, count 2 2006.257.07:27:37.46#ibcon#about to write, iclass 6, count 2 2006.257.07:27:37.46#ibcon#wrote, iclass 6, count 2 2006.257.07:27:37.46#ibcon#about to read 3, iclass 6, count 2 2006.257.07:27:37.49#ibcon#read 3, iclass 6, count 2 2006.257.07:27:37.49#ibcon#about to read 4, iclass 6, count 2 2006.257.07:27:37.49#ibcon#read 4, iclass 6, count 2 2006.257.07:27:37.49#ibcon#about to read 5, iclass 6, count 2 2006.257.07:27:37.49#ibcon#read 5, iclass 6, count 2 2006.257.07:27:37.49#ibcon#about to read 6, iclass 6, count 2 2006.257.07:27:37.49#ibcon#read 6, iclass 6, count 2 2006.257.07:27:37.49#ibcon#end of sib2, iclass 6, count 2 2006.257.07:27:37.49#ibcon#*after write, iclass 6, count 2 2006.257.07:27:37.49#ibcon#*before return 0, iclass 6, count 2 2006.257.07:27:37.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:37.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:27:37.49#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.07:27:37.49#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:37.49#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:37.61#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:37.61#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:37.61#ibcon#enter wrdev, iclass 6, count 0 2006.257.07:27:37.61#ibcon#first serial, iclass 6, count 0 2006.257.07:27:37.61#ibcon#enter sib2, iclass 6, count 0 2006.257.07:27:37.61#ibcon#flushed, iclass 6, count 0 2006.257.07:27:37.61#ibcon#about to write, iclass 6, count 0 2006.257.07:27:37.61#ibcon#wrote, iclass 6, count 0 2006.257.07:27:37.61#ibcon#about to read 3, iclass 6, count 0 2006.257.07:27:37.63#ibcon#read 3, iclass 6, count 0 2006.257.07:27:37.63#ibcon#about to read 4, iclass 6, count 0 2006.257.07:27:37.63#ibcon#read 4, iclass 6, count 0 2006.257.07:27:37.63#ibcon#about to read 5, iclass 6, count 0 2006.257.07:27:37.63#ibcon#read 5, iclass 6, count 0 2006.257.07:27:37.63#ibcon#about to read 6, iclass 6, count 0 2006.257.07:27:37.63#ibcon#read 6, iclass 6, count 0 2006.257.07:27:37.63#ibcon#end of sib2, iclass 6, count 0 2006.257.07:27:37.63#ibcon#*mode == 0, iclass 6, count 0 2006.257.07:27:37.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.07:27:37.63#ibcon#[27=USB\r\n] 2006.257.07:27:37.63#ibcon#*before write, iclass 6, count 0 2006.257.07:27:37.63#ibcon#enter sib2, iclass 6, count 0 2006.257.07:27:37.63#ibcon#flushed, iclass 6, count 0 2006.257.07:27:37.63#ibcon#about to write, iclass 6, count 0 2006.257.07:27:37.63#ibcon#wrote, iclass 6, count 0 2006.257.07:27:37.63#ibcon#about to read 3, iclass 6, count 0 2006.257.07:27:37.66#ibcon#read 3, iclass 6, count 0 2006.257.07:27:37.66#ibcon#about to read 4, iclass 6, count 0 2006.257.07:27:37.66#ibcon#read 4, iclass 6, count 0 2006.257.07:27:37.66#ibcon#about to read 5, iclass 6, count 0 2006.257.07:27:37.66#ibcon#read 5, iclass 6, count 0 2006.257.07:27:37.66#ibcon#about to read 6, iclass 6, count 0 2006.257.07:27:37.66#ibcon#read 6, iclass 6, count 0 2006.257.07:27:37.66#ibcon#end of sib2, iclass 6, count 0 2006.257.07:27:37.66#ibcon#*after write, iclass 6, count 0 2006.257.07:27:37.66#ibcon#*before return 0, iclass 6, count 0 2006.257.07:27:37.66#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:37.66#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:27:37.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.07:27:37.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.07:27:37.66$vck44/vblo=3,649.99 2006.257.07:27:37.66#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.07:27:37.66#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.07:27:37.66#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:37.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:37.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:37.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:37.66#ibcon#enter wrdev, iclass 10, count 0 2006.257.07:27:37.66#ibcon#first serial, iclass 10, count 0 2006.257.07:27:37.66#ibcon#enter sib2, iclass 10, count 0 2006.257.07:27:37.66#ibcon#flushed, iclass 10, count 0 2006.257.07:27:37.66#ibcon#about to write, iclass 10, count 0 2006.257.07:27:37.66#ibcon#wrote, iclass 10, count 0 2006.257.07:27:37.66#ibcon#about to read 3, iclass 10, count 0 2006.257.07:27:37.68#ibcon#read 3, iclass 10, count 0 2006.257.07:27:37.68#ibcon#about to read 4, iclass 10, count 0 2006.257.07:27:37.68#ibcon#read 4, iclass 10, count 0 2006.257.07:27:37.68#ibcon#about to read 5, iclass 10, count 0 2006.257.07:27:37.68#ibcon#read 5, iclass 10, count 0 2006.257.07:27:37.68#ibcon#about to read 6, iclass 10, count 0 2006.257.07:27:37.68#ibcon#read 6, iclass 10, count 0 2006.257.07:27:37.68#ibcon#end of sib2, iclass 10, count 0 2006.257.07:27:37.68#ibcon#*mode == 0, iclass 10, count 0 2006.257.07:27:37.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.07:27:37.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.07:27:37.68#ibcon#*before write, iclass 10, count 0 2006.257.07:27:37.68#ibcon#enter sib2, iclass 10, count 0 2006.257.07:27:37.68#ibcon#flushed, iclass 10, count 0 2006.257.07:27:37.68#ibcon#about to write, iclass 10, count 0 2006.257.07:27:37.68#ibcon#wrote, iclass 10, count 0 2006.257.07:27:37.68#ibcon#about to read 3, iclass 10, count 0 2006.257.07:27:37.72#ibcon#read 3, iclass 10, count 0 2006.257.07:27:37.72#ibcon#about to read 4, iclass 10, count 0 2006.257.07:27:37.72#ibcon#read 4, iclass 10, count 0 2006.257.07:27:37.72#ibcon#about to read 5, iclass 10, count 0 2006.257.07:27:37.72#ibcon#read 5, iclass 10, count 0 2006.257.07:27:37.72#ibcon#about to read 6, iclass 10, count 0 2006.257.07:27:37.72#ibcon#read 6, iclass 10, count 0 2006.257.07:27:37.72#ibcon#end of sib2, iclass 10, count 0 2006.257.07:27:37.72#ibcon#*after write, iclass 10, count 0 2006.257.07:27:37.72#ibcon#*before return 0, iclass 10, count 0 2006.257.07:27:37.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:37.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:27:37.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.07:27:37.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.07:27:37.72$vck44/vb=3,4 2006.257.07:27:37.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.07:27:37.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.07:27:37.72#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:37.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:37.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:37.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:37.78#ibcon#enter wrdev, iclass 12, count 2 2006.257.07:27:37.78#ibcon#first serial, iclass 12, count 2 2006.257.07:27:37.78#ibcon#enter sib2, iclass 12, count 2 2006.257.07:27:37.78#ibcon#flushed, iclass 12, count 2 2006.257.07:27:37.78#ibcon#about to write, iclass 12, count 2 2006.257.07:27:37.78#ibcon#wrote, iclass 12, count 2 2006.257.07:27:37.78#ibcon#about to read 3, iclass 12, count 2 2006.257.07:27:37.80#ibcon#read 3, iclass 12, count 2 2006.257.07:27:37.80#ibcon#about to read 4, iclass 12, count 2 2006.257.07:27:37.80#ibcon#read 4, iclass 12, count 2 2006.257.07:27:37.80#ibcon#about to read 5, iclass 12, count 2 2006.257.07:27:37.80#ibcon#read 5, iclass 12, count 2 2006.257.07:27:37.80#ibcon#about to read 6, iclass 12, count 2 2006.257.07:27:37.80#ibcon#read 6, iclass 12, count 2 2006.257.07:27:37.80#ibcon#end of sib2, iclass 12, count 2 2006.257.07:27:37.80#ibcon#*mode == 0, iclass 12, count 2 2006.257.07:27:37.80#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.07:27:37.80#ibcon#[27=AT03-04\r\n] 2006.257.07:27:37.80#ibcon#*before write, iclass 12, count 2 2006.257.07:27:37.80#ibcon#enter sib2, iclass 12, count 2 2006.257.07:27:37.80#ibcon#flushed, iclass 12, count 2 2006.257.07:27:37.80#ibcon#about to write, iclass 12, count 2 2006.257.07:27:37.80#ibcon#wrote, iclass 12, count 2 2006.257.07:27:37.80#ibcon#about to read 3, iclass 12, count 2 2006.257.07:27:37.83#ibcon#read 3, iclass 12, count 2 2006.257.07:27:37.83#ibcon#about to read 4, iclass 12, count 2 2006.257.07:27:37.83#ibcon#read 4, iclass 12, count 2 2006.257.07:27:37.83#ibcon#about to read 5, iclass 12, count 2 2006.257.07:27:37.83#ibcon#read 5, iclass 12, count 2 2006.257.07:27:37.83#ibcon#about to read 6, iclass 12, count 2 2006.257.07:27:37.83#ibcon#read 6, iclass 12, count 2 2006.257.07:27:37.83#ibcon#end of sib2, iclass 12, count 2 2006.257.07:27:37.83#ibcon#*after write, iclass 12, count 2 2006.257.07:27:37.83#ibcon#*before return 0, iclass 12, count 2 2006.257.07:27:37.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:37.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:27:37.83#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.07:27:37.83#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:37.83#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:37.95#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:37.95#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:37.95#ibcon#enter wrdev, iclass 12, count 0 2006.257.07:27:37.95#ibcon#first serial, iclass 12, count 0 2006.257.07:27:37.95#ibcon#enter sib2, iclass 12, count 0 2006.257.07:27:37.95#ibcon#flushed, iclass 12, count 0 2006.257.07:27:37.95#ibcon#about to write, iclass 12, count 0 2006.257.07:27:37.95#ibcon#wrote, iclass 12, count 0 2006.257.07:27:37.95#ibcon#about to read 3, iclass 12, count 0 2006.257.07:27:37.97#ibcon#read 3, iclass 12, count 0 2006.257.07:27:37.97#ibcon#about to read 4, iclass 12, count 0 2006.257.07:27:37.97#ibcon#read 4, iclass 12, count 0 2006.257.07:27:37.97#ibcon#about to read 5, iclass 12, count 0 2006.257.07:27:37.97#ibcon#read 5, iclass 12, count 0 2006.257.07:27:37.97#ibcon#about to read 6, iclass 12, count 0 2006.257.07:27:37.97#ibcon#read 6, iclass 12, count 0 2006.257.07:27:37.97#ibcon#end of sib2, iclass 12, count 0 2006.257.07:27:37.97#ibcon#*mode == 0, iclass 12, count 0 2006.257.07:27:37.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.07:27:37.97#ibcon#[27=USB\r\n] 2006.257.07:27:37.97#ibcon#*before write, iclass 12, count 0 2006.257.07:27:37.97#ibcon#enter sib2, iclass 12, count 0 2006.257.07:27:37.97#ibcon#flushed, iclass 12, count 0 2006.257.07:27:37.97#ibcon#about to write, iclass 12, count 0 2006.257.07:27:37.97#ibcon#wrote, iclass 12, count 0 2006.257.07:27:37.97#ibcon#about to read 3, iclass 12, count 0 2006.257.07:27:38.00#ibcon#read 3, iclass 12, count 0 2006.257.07:27:38.00#ibcon#about to read 4, iclass 12, count 0 2006.257.07:27:38.00#ibcon#read 4, iclass 12, count 0 2006.257.07:27:38.00#ibcon#about to read 5, iclass 12, count 0 2006.257.07:27:38.00#ibcon#read 5, iclass 12, count 0 2006.257.07:27:38.00#ibcon#about to read 6, iclass 12, count 0 2006.257.07:27:38.00#ibcon#read 6, iclass 12, count 0 2006.257.07:27:38.00#ibcon#end of sib2, iclass 12, count 0 2006.257.07:27:38.00#ibcon#*after write, iclass 12, count 0 2006.257.07:27:38.00#ibcon#*before return 0, iclass 12, count 0 2006.257.07:27:38.00#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:38.00#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:27:38.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.07:27:38.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.07:27:38.00$vck44/vblo=4,679.99 2006.257.07:27:38.00#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.07:27:38.00#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.07:27:38.00#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:38.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:38.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:38.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:38.00#ibcon#enter wrdev, iclass 14, count 0 2006.257.07:27:38.00#ibcon#first serial, iclass 14, count 0 2006.257.07:27:38.00#ibcon#enter sib2, iclass 14, count 0 2006.257.07:27:38.00#ibcon#flushed, iclass 14, count 0 2006.257.07:27:38.00#ibcon#about to write, iclass 14, count 0 2006.257.07:27:38.00#ibcon#wrote, iclass 14, count 0 2006.257.07:27:38.00#ibcon#about to read 3, iclass 14, count 0 2006.257.07:27:38.02#ibcon#read 3, iclass 14, count 0 2006.257.07:27:38.02#ibcon#about to read 4, iclass 14, count 0 2006.257.07:27:38.02#ibcon#read 4, iclass 14, count 0 2006.257.07:27:38.02#ibcon#about to read 5, iclass 14, count 0 2006.257.07:27:38.02#ibcon#read 5, iclass 14, count 0 2006.257.07:27:38.02#ibcon#about to read 6, iclass 14, count 0 2006.257.07:27:38.02#ibcon#read 6, iclass 14, count 0 2006.257.07:27:38.02#ibcon#end of sib2, iclass 14, count 0 2006.257.07:27:38.02#ibcon#*mode == 0, iclass 14, count 0 2006.257.07:27:38.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.07:27:38.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.07:27:38.02#ibcon#*before write, iclass 14, count 0 2006.257.07:27:38.02#ibcon#enter sib2, iclass 14, count 0 2006.257.07:27:38.02#ibcon#flushed, iclass 14, count 0 2006.257.07:27:38.02#ibcon#about to write, iclass 14, count 0 2006.257.07:27:38.02#ibcon#wrote, iclass 14, count 0 2006.257.07:27:38.02#ibcon#about to read 3, iclass 14, count 0 2006.257.07:27:38.06#ibcon#read 3, iclass 14, count 0 2006.257.07:27:38.06#ibcon#about to read 4, iclass 14, count 0 2006.257.07:27:38.06#ibcon#read 4, iclass 14, count 0 2006.257.07:27:38.06#ibcon#about to read 5, iclass 14, count 0 2006.257.07:27:38.06#ibcon#read 5, iclass 14, count 0 2006.257.07:27:38.06#ibcon#about to read 6, iclass 14, count 0 2006.257.07:27:38.06#ibcon#read 6, iclass 14, count 0 2006.257.07:27:38.06#ibcon#end of sib2, iclass 14, count 0 2006.257.07:27:38.06#ibcon#*after write, iclass 14, count 0 2006.257.07:27:38.06#ibcon#*before return 0, iclass 14, count 0 2006.257.07:27:38.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:38.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:27:38.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.07:27:38.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.07:27:38.06$vck44/vb=4,5 2006.257.07:27:38.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.07:27:38.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.07:27:38.06#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:38.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:38.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:38.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:38.12#ibcon#enter wrdev, iclass 16, count 2 2006.257.07:27:38.12#ibcon#first serial, iclass 16, count 2 2006.257.07:27:38.12#ibcon#enter sib2, iclass 16, count 2 2006.257.07:27:38.12#ibcon#flushed, iclass 16, count 2 2006.257.07:27:38.12#ibcon#about to write, iclass 16, count 2 2006.257.07:27:38.12#ibcon#wrote, iclass 16, count 2 2006.257.07:27:38.12#ibcon#about to read 3, iclass 16, count 2 2006.257.07:27:38.14#ibcon#read 3, iclass 16, count 2 2006.257.07:27:38.14#ibcon#about to read 4, iclass 16, count 2 2006.257.07:27:38.14#ibcon#read 4, iclass 16, count 2 2006.257.07:27:38.14#ibcon#about to read 5, iclass 16, count 2 2006.257.07:27:38.14#ibcon#read 5, iclass 16, count 2 2006.257.07:27:38.14#ibcon#about to read 6, iclass 16, count 2 2006.257.07:27:38.14#ibcon#read 6, iclass 16, count 2 2006.257.07:27:38.14#ibcon#end of sib2, iclass 16, count 2 2006.257.07:27:38.14#ibcon#*mode == 0, iclass 16, count 2 2006.257.07:27:38.14#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.07:27:38.14#ibcon#[27=AT04-05\r\n] 2006.257.07:27:38.14#ibcon#*before write, iclass 16, count 2 2006.257.07:27:38.14#ibcon#enter sib2, iclass 16, count 2 2006.257.07:27:38.14#ibcon#flushed, iclass 16, count 2 2006.257.07:27:38.14#ibcon#about to write, iclass 16, count 2 2006.257.07:27:38.14#ibcon#wrote, iclass 16, count 2 2006.257.07:27:38.14#ibcon#about to read 3, iclass 16, count 2 2006.257.07:27:38.17#ibcon#read 3, iclass 16, count 2 2006.257.07:27:38.17#ibcon#about to read 4, iclass 16, count 2 2006.257.07:27:38.17#ibcon#read 4, iclass 16, count 2 2006.257.07:27:38.17#ibcon#about to read 5, iclass 16, count 2 2006.257.07:27:38.17#ibcon#read 5, iclass 16, count 2 2006.257.07:27:38.17#ibcon#about to read 6, iclass 16, count 2 2006.257.07:27:38.17#ibcon#read 6, iclass 16, count 2 2006.257.07:27:38.17#ibcon#end of sib2, iclass 16, count 2 2006.257.07:27:38.17#ibcon#*after write, iclass 16, count 2 2006.257.07:27:38.17#ibcon#*before return 0, iclass 16, count 2 2006.257.07:27:38.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:38.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:27:38.17#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.07:27:38.17#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:38.17#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:38.29#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:38.29#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:38.29#ibcon#enter wrdev, iclass 16, count 0 2006.257.07:27:38.29#ibcon#first serial, iclass 16, count 0 2006.257.07:27:38.29#ibcon#enter sib2, iclass 16, count 0 2006.257.07:27:38.29#ibcon#flushed, iclass 16, count 0 2006.257.07:27:38.29#ibcon#about to write, iclass 16, count 0 2006.257.07:27:38.29#ibcon#wrote, iclass 16, count 0 2006.257.07:27:38.29#ibcon#about to read 3, iclass 16, count 0 2006.257.07:27:38.31#ibcon#read 3, iclass 16, count 0 2006.257.07:27:38.31#ibcon#about to read 4, iclass 16, count 0 2006.257.07:27:38.31#ibcon#read 4, iclass 16, count 0 2006.257.07:27:38.31#ibcon#about to read 5, iclass 16, count 0 2006.257.07:27:38.31#ibcon#read 5, iclass 16, count 0 2006.257.07:27:38.31#ibcon#about to read 6, iclass 16, count 0 2006.257.07:27:38.31#ibcon#read 6, iclass 16, count 0 2006.257.07:27:38.31#ibcon#end of sib2, iclass 16, count 0 2006.257.07:27:38.31#ibcon#*mode == 0, iclass 16, count 0 2006.257.07:27:38.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.07:27:38.31#ibcon#[27=USB\r\n] 2006.257.07:27:38.31#ibcon#*before write, iclass 16, count 0 2006.257.07:27:38.31#ibcon#enter sib2, iclass 16, count 0 2006.257.07:27:38.31#ibcon#flushed, iclass 16, count 0 2006.257.07:27:38.31#ibcon#about to write, iclass 16, count 0 2006.257.07:27:38.31#ibcon#wrote, iclass 16, count 0 2006.257.07:27:38.31#ibcon#about to read 3, iclass 16, count 0 2006.257.07:27:38.34#ibcon#read 3, iclass 16, count 0 2006.257.07:27:38.34#ibcon#about to read 4, iclass 16, count 0 2006.257.07:27:38.34#ibcon#read 4, iclass 16, count 0 2006.257.07:27:38.34#ibcon#about to read 5, iclass 16, count 0 2006.257.07:27:38.34#ibcon#read 5, iclass 16, count 0 2006.257.07:27:38.34#ibcon#about to read 6, iclass 16, count 0 2006.257.07:27:38.34#ibcon#read 6, iclass 16, count 0 2006.257.07:27:38.34#ibcon#end of sib2, iclass 16, count 0 2006.257.07:27:38.34#ibcon#*after write, iclass 16, count 0 2006.257.07:27:38.34#ibcon#*before return 0, iclass 16, count 0 2006.257.07:27:38.34#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:38.34#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:27:38.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.07:27:38.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.07:27:38.34$vck44/vblo=5,709.99 2006.257.07:27:38.34#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.07:27:38.34#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.07:27:38.34#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:38.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:38.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:38.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:38.34#ibcon#enter wrdev, iclass 18, count 0 2006.257.07:27:38.34#ibcon#first serial, iclass 18, count 0 2006.257.07:27:38.34#ibcon#enter sib2, iclass 18, count 0 2006.257.07:27:38.34#ibcon#flushed, iclass 18, count 0 2006.257.07:27:38.34#ibcon#about to write, iclass 18, count 0 2006.257.07:27:38.34#ibcon#wrote, iclass 18, count 0 2006.257.07:27:38.34#ibcon#about to read 3, iclass 18, count 0 2006.257.07:27:38.36#ibcon#read 3, iclass 18, count 0 2006.257.07:27:38.36#ibcon#about to read 4, iclass 18, count 0 2006.257.07:27:38.36#ibcon#read 4, iclass 18, count 0 2006.257.07:27:38.36#ibcon#about to read 5, iclass 18, count 0 2006.257.07:27:38.36#ibcon#read 5, iclass 18, count 0 2006.257.07:27:38.36#ibcon#about to read 6, iclass 18, count 0 2006.257.07:27:38.36#ibcon#read 6, iclass 18, count 0 2006.257.07:27:38.36#ibcon#end of sib2, iclass 18, count 0 2006.257.07:27:38.36#ibcon#*mode == 0, iclass 18, count 0 2006.257.07:27:38.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.07:27:38.36#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.07:27:38.36#ibcon#*before write, iclass 18, count 0 2006.257.07:27:38.36#ibcon#enter sib2, iclass 18, count 0 2006.257.07:27:38.36#ibcon#flushed, iclass 18, count 0 2006.257.07:27:38.36#ibcon#about to write, iclass 18, count 0 2006.257.07:27:38.36#ibcon#wrote, iclass 18, count 0 2006.257.07:27:38.36#ibcon#about to read 3, iclass 18, count 0 2006.257.07:27:38.40#ibcon#read 3, iclass 18, count 0 2006.257.07:27:38.40#ibcon#about to read 4, iclass 18, count 0 2006.257.07:27:38.40#ibcon#read 4, iclass 18, count 0 2006.257.07:27:38.40#ibcon#about to read 5, iclass 18, count 0 2006.257.07:27:38.40#ibcon#read 5, iclass 18, count 0 2006.257.07:27:38.40#ibcon#about to read 6, iclass 18, count 0 2006.257.07:27:38.40#ibcon#read 6, iclass 18, count 0 2006.257.07:27:38.40#ibcon#end of sib2, iclass 18, count 0 2006.257.07:27:38.40#ibcon#*after write, iclass 18, count 0 2006.257.07:27:38.40#ibcon#*before return 0, iclass 18, count 0 2006.257.07:27:38.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:38.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:27:38.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.07:27:38.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.07:27:38.40$vck44/vb=5,4 2006.257.07:27:38.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.07:27:38.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.07:27:38.40#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:38.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:38.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:38.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:38.46#ibcon#enter wrdev, iclass 20, count 2 2006.257.07:27:38.46#ibcon#first serial, iclass 20, count 2 2006.257.07:27:38.46#ibcon#enter sib2, iclass 20, count 2 2006.257.07:27:38.46#ibcon#flushed, iclass 20, count 2 2006.257.07:27:38.46#ibcon#about to write, iclass 20, count 2 2006.257.07:27:38.46#ibcon#wrote, iclass 20, count 2 2006.257.07:27:38.46#ibcon#about to read 3, iclass 20, count 2 2006.257.07:27:38.48#ibcon#read 3, iclass 20, count 2 2006.257.07:27:38.48#ibcon#about to read 4, iclass 20, count 2 2006.257.07:27:38.48#ibcon#read 4, iclass 20, count 2 2006.257.07:27:38.48#ibcon#about to read 5, iclass 20, count 2 2006.257.07:27:38.48#ibcon#read 5, iclass 20, count 2 2006.257.07:27:38.48#ibcon#about to read 6, iclass 20, count 2 2006.257.07:27:38.48#ibcon#read 6, iclass 20, count 2 2006.257.07:27:38.48#ibcon#end of sib2, iclass 20, count 2 2006.257.07:27:38.48#ibcon#*mode == 0, iclass 20, count 2 2006.257.07:27:38.48#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.07:27:38.48#ibcon#[27=AT05-04\r\n] 2006.257.07:27:38.48#ibcon#*before write, iclass 20, count 2 2006.257.07:27:38.48#ibcon#enter sib2, iclass 20, count 2 2006.257.07:27:38.48#ibcon#flushed, iclass 20, count 2 2006.257.07:27:38.48#ibcon#about to write, iclass 20, count 2 2006.257.07:27:38.48#ibcon#wrote, iclass 20, count 2 2006.257.07:27:38.48#ibcon#about to read 3, iclass 20, count 2 2006.257.07:27:38.51#ibcon#read 3, iclass 20, count 2 2006.257.07:27:38.51#ibcon#about to read 4, iclass 20, count 2 2006.257.07:27:38.51#ibcon#read 4, iclass 20, count 2 2006.257.07:27:38.51#ibcon#about to read 5, iclass 20, count 2 2006.257.07:27:38.51#ibcon#read 5, iclass 20, count 2 2006.257.07:27:38.51#ibcon#about to read 6, iclass 20, count 2 2006.257.07:27:38.51#ibcon#read 6, iclass 20, count 2 2006.257.07:27:38.51#ibcon#end of sib2, iclass 20, count 2 2006.257.07:27:38.51#ibcon#*after write, iclass 20, count 2 2006.257.07:27:38.51#ibcon#*before return 0, iclass 20, count 2 2006.257.07:27:38.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:38.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:27:38.51#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.07:27:38.51#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:38.51#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:38.63#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:38.63#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:38.63#ibcon#enter wrdev, iclass 20, count 0 2006.257.07:27:38.63#ibcon#first serial, iclass 20, count 0 2006.257.07:27:38.63#ibcon#enter sib2, iclass 20, count 0 2006.257.07:27:38.63#ibcon#flushed, iclass 20, count 0 2006.257.07:27:38.63#ibcon#about to write, iclass 20, count 0 2006.257.07:27:38.63#ibcon#wrote, iclass 20, count 0 2006.257.07:27:38.63#ibcon#about to read 3, iclass 20, count 0 2006.257.07:27:38.65#ibcon#read 3, iclass 20, count 0 2006.257.07:27:38.65#ibcon#about to read 4, iclass 20, count 0 2006.257.07:27:38.65#ibcon#read 4, iclass 20, count 0 2006.257.07:27:38.65#ibcon#about to read 5, iclass 20, count 0 2006.257.07:27:38.65#ibcon#read 5, iclass 20, count 0 2006.257.07:27:38.65#ibcon#about to read 6, iclass 20, count 0 2006.257.07:27:38.65#ibcon#read 6, iclass 20, count 0 2006.257.07:27:38.65#ibcon#end of sib2, iclass 20, count 0 2006.257.07:27:38.65#ibcon#*mode == 0, iclass 20, count 0 2006.257.07:27:38.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.07:27:38.65#ibcon#[27=USB\r\n] 2006.257.07:27:38.65#ibcon#*before write, iclass 20, count 0 2006.257.07:27:38.65#ibcon#enter sib2, iclass 20, count 0 2006.257.07:27:38.65#ibcon#flushed, iclass 20, count 0 2006.257.07:27:38.65#ibcon#about to write, iclass 20, count 0 2006.257.07:27:38.65#ibcon#wrote, iclass 20, count 0 2006.257.07:27:38.65#ibcon#about to read 3, iclass 20, count 0 2006.257.07:27:38.68#ibcon#read 3, iclass 20, count 0 2006.257.07:27:38.68#ibcon#about to read 4, iclass 20, count 0 2006.257.07:27:38.68#ibcon#read 4, iclass 20, count 0 2006.257.07:27:38.68#ibcon#about to read 5, iclass 20, count 0 2006.257.07:27:38.68#ibcon#read 5, iclass 20, count 0 2006.257.07:27:38.68#ibcon#about to read 6, iclass 20, count 0 2006.257.07:27:38.68#ibcon#read 6, iclass 20, count 0 2006.257.07:27:38.68#ibcon#end of sib2, iclass 20, count 0 2006.257.07:27:38.68#ibcon#*after write, iclass 20, count 0 2006.257.07:27:38.68#ibcon#*before return 0, iclass 20, count 0 2006.257.07:27:38.68#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:38.68#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:27:38.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.07:27:38.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.07:27:38.68$vck44/vblo=6,719.99 2006.257.07:27:38.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.07:27:38.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.07:27:38.68#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:38.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:38.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:38.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:38.68#ibcon#enter wrdev, iclass 22, count 0 2006.257.07:27:38.68#ibcon#first serial, iclass 22, count 0 2006.257.07:27:38.68#ibcon#enter sib2, iclass 22, count 0 2006.257.07:27:38.68#ibcon#flushed, iclass 22, count 0 2006.257.07:27:38.68#ibcon#about to write, iclass 22, count 0 2006.257.07:27:38.68#ibcon#wrote, iclass 22, count 0 2006.257.07:27:38.68#ibcon#about to read 3, iclass 22, count 0 2006.257.07:27:38.70#ibcon#read 3, iclass 22, count 0 2006.257.07:27:38.70#ibcon#about to read 4, iclass 22, count 0 2006.257.07:27:38.70#ibcon#read 4, iclass 22, count 0 2006.257.07:27:38.70#ibcon#about to read 5, iclass 22, count 0 2006.257.07:27:38.70#ibcon#read 5, iclass 22, count 0 2006.257.07:27:38.70#ibcon#about to read 6, iclass 22, count 0 2006.257.07:27:38.70#ibcon#read 6, iclass 22, count 0 2006.257.07:27:38.70#ibcon#end of sib2, iclass 22, count 0 2006.257.07:27:38.70#ibcon#*mode == 0, iclass 22, count 0 2006.257.07:27:38.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.07:27:38.70#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.07:27:38.70#ibcon#*before write, iclass 22, count 0 2006.257.07:27:38.70#ibcon#enter sib2, iclass 22, count 0 2006.257.07:27:38.70#ibcon#flushed, iclass 22, count 0 2006.257.07:27:38.70#ibcon#about to write, iclass 22, count 0 2006.257.07:27:38.70#ibcon#wrote, iclass 22, count 0 2006.257.07:27:38.70#ibcon#about to read 3, iclass 22, count 0 2006.257.07:27:38.74#ibcon#read 3, iclass 22, count 0 2006.257.07:27:38.74#ibcon#about to read 4, iclass 22, count 0 2006.257.07:27:38.74#ibcon#read 4, iclass 22, count 0 2006.257.07:27:38.74#ibcon#about to read 5, iclass 22, count 0 2006.257.07:27:38.74#ibcon#read 5, iclass 22, count 0 2006.257.07:27:38.74#ibcon#about to read 6, iclass 22, count 0 2006.257.07:27:38.74#ibcon#read 6, iclass 22, count 0 2006.257.07:27:38.74#ibcon#end of sib2, iclass 22, count 0 2006.257.07:27:38.74#ibcon#*after write, iclass 22, count 0 2006.257.07:27:38.74#ibcon#*before return 0, iclass 22, count 0 2006.257.07:27:38.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:38.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:27:38.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.07:27:38.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.07:27:38.74$vck44/vb=6,4 2006.257.07:27:38.74#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.07:27:38.74#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.07:27:38.74#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:38.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:38.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:38.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:38.80#ibcon#enter wrdev, iclass 24, count 2 2006.257.07:27:38.80#ibcon#first serial, iclass 24, count 2 2006.257.07:27:38.80#ibcon#enter sib2, iclass 24, count 2 2006.257.07:27:38.80#ibcon#flushed, iclass 24, count 2 2006.257.07:27:38.80#ibcon#about to write, iclass 24, count 2 2006.257.07:27:38.80#ibcon#wrote, iclass 24, count 2 2006.257.07:27:38.80#ibcon#about to read 3, iclass 24, count 2 2006.257.07:27:38.82#ibcon#read 3, iclass 24, count 2 2006.257.07:27:38.82#ibcon#about to read 4, iclass 24, count 2 2006.257.07:27:38.82#ibcon#read 4, iclass 24, count 2 2006.257.07:27:38.82#ibcon#about to read 5, iclass 24, count 2 2006.257.07:27:38.82#ibcon#read 5, iclass 24, count 2 2006.257.07:27:38.82#ibcon#about to read 6, iclass 24, count 2 2006.257.07:27:38.82#ibcon#read 6, iclass 24, count 2 2006.257.07:27:38.82#ibcon#end of sib2, iclass 24, count 2 2006.257.07:27:38.82#ibcon#*mode == 0, iclass 24, count 2 2006.257.07:27:38.82#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.07:27:38.82#ibcon#[27=AT06-04\r\n] 2006.257.07:27:38.82#ibcon#*before write, iclass 24, count 2 2006.257.07:27:38.82#ibcon#enter sib2, iclass 24, count 2 2006.257.07:27:38.82#ibcon#flushed, iclass 24, count 2 2006.257.07:27:38.82#ibcon#about to write, iclass 24, count 2 2006.257.07:27:38.82#ibcon#wrote, iclass 24, count 2 2006.257.07:27:38.82#ibcon#about to read 3, iclass 24, count 2 2006.257.07:27:38.85#ibcon#read 3, iclass 24, count 2 2006.257.07:27:38.85#ibcon#about to read 4, iclass 24, count 2 2006.257.07:27:38.85#ibcon#read 4, iclass 24, count 2 2006.257.07:27:38.85#ibcon#about to read 5, iclass 24, count 2 2006.257.07:27:38.85#ibcon#read 5, iclass 24, count 2 2006.257.07:27:38.85#ibcon#about to read 6, iclass 24, count 2 2006.257.07:27:38.85#ibcon#read 6, iclass 24, count 2 2006.257.07:27:38.85#ibcon#end of sib2, iclass 24, count 2 2006.257.07:27:38.85#ibcon#*after write, iclass 24, count 2 2006.257.07:27:38.85#ibcon#*before return 0, iclass 24, count 2 2006.257.07:27:38.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:38.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:27:38.85#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.07:27:38.85#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:38.85#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:38.97#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:38.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:38.97#ibcon#enter wrdev, iclass 24, count 0 2006.257.07:27:38.97#ibcon#first serial, iclass 24, count 0 2006.257.07:27:38.97#ibcon#enter sib2, iclass 24, count 0 2006.257.07:27:38.97#ibcon#flushed, iclass 24, count 0 2006.257.07:27:38.97#ibcon#about to write, iclass 24, count 0 2006.257.07:27:38.97#ibcon#wrote, iclass 24, count 0 2006.257.07:27:38.97#ibcon#about to read 3, iclass 24, count 0 2006.257.07:27:38.99#ibcon#read 3, iclass 24, count 0 2006.257.07:27:38.99#ibcon#about to read 4, iclass 24, count 0 2006.257.07:27:38.99#ibcon#read 4, iclass 24, count 0 2006.257.07:27:38.99#ibcon#about to read 5, iclass 24, count 0 2006.257.07:27:38.99#ibcon#read 5, iclass 24, count 0 2006.257.07:27:38.99#ibcon#about to read 6, iclass 24, count 0 2006.257.07:27:38.99#ibcon#read 6, iclass 24, count 0 2006.257.07:27:38.99#ibcon#end of sib2, iclass 24, count 0 2006.257.07:27:38.99#ibcon#*mode == 0, iclass 24, count 0 2006.257.07:27:38.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.07:27:38.99#ibcon#[27=USB\r\n] 2006.257.07:27:38.99#ibcon#*before write, iclass 24, count 0 2006.257.07:27:38.99#ibcon#enter sib2, iclass 24, count 0 2006.257.07:27:38.99#ibcon#flushed, iclass 24, count 0 2006.257.07:27:38.99#ibcon#about to write, iclass 24, count 0 2006.257.07:27:38.99#ibcon#wrote, iclass 24, count 0 2006.257.07:27:38.99#ibcon#about to read 3, iclass 24, count 0 2006.257.07:27:39.02#ibcon#read 3, iclass 24, count 0 2006.257.07:27:39.02#ibcon#about to read 4, iclass 24, count 0 2006.257.07:27:39.02#ibcon#read 4, iclass 24, count 0 2006.257.07:27:39.02#ibcon#about to read 5, iclass 24, count 0 2006.257.07:27:39.02#ibcon#read 5, iclass 24, count 0 2006.257.07:27:39.02#ibcon#about to read 6, iclass 24, count 0 2006.257.07:27:39.02#ibcon#read 6, iclass 24, count 0 2006.257.07:27:39.02#ibcon#end of sib2, iclass 24, count 0 2006.257.07:27:39.02#ibcon#*after write, iclass 24, count 0 2006.257.07:27:39.02#ibcon#*before return 0, iclass 24, count 0 2006.257.07:27:39.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:39.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:27:39.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.07:27:39.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.07:27:39.02$vck44/vblo=7,734.99 2006.257.07:27:39.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.07:27:39.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.07:27:39.02#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:39.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:39.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:39.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:39.02#ibcon#enter wrdev, iclass 26, count 0 2006.257.07:27:39.02#ibcon#first serial, iclass 26, count 0 2006.257.07:27:39.02#ibcon#enter sib2, iclass 26, count 0 2006.257.07:27:39.02#ibcon#flushed, iclass 26, count 0 2006.257.07:27:39.02#ibcon#about to write, iclass 26, count 0 2006.257.07:27:39.02#ibcon#wrote, iclass 26, count 0 2006.257.07:27:39.02#ibcon#about to read 3, iclass 26, count 0 2006.257.07:27:39.04#ibcon#read 3, iclass 26, count 0 2006.257.07:27:39.04#ibcon#about to read 4, iclass 26, count 0 2006.257.07:27:39.04#ibcon#read 4, iclass 26, count 0 2006.257.07:27:39.04#ibcon#about to read 5, iclass 26, count 0 2006.257.07:27:39.04#ibcon#read 5, iclass 26, count 0 2006.257.07:27:39.04#ibcon#about to read 6, iclass 26, count 0 2006.257.07:27:39.04#ibcon#read 6, iclass 26, count 0 2006.257.07:27:39.04#ibcon#end of sib2, iclass 26, count 0 2006.257.07:27:39.04#ibcon#*mode == 0, iclass 26, count 0 2006.257.07:27:39.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.07:27:39.04#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.07:27:39.04#ibcon#*before write, iclass 26, count 0 2006.257.07:27:39.04#ibcon#enter sib2, iclass 26, count 0 2006.257.07:27:39.04#ibcon#flushed, iclass 26, count 0 2006.257.07:27:39.04#ibcon#about to write, iclass 26, count 0 2006.257.07:27:39.04#ibcon#wrote, iclass 26, count 0 2006.257.07:27:39.04#ibcon#about to read 3, iclass 26, count 0 2006.257.07:27:39.08#ibcon#read 3, iclass 26, count 0 2006.257.07:27:39.08#ibcon#about to read 4, iclass 26, count 0 2006.257.07:27:39.08#ibcon#read 4, iclass 26, count 0 2006.257.07:27:39.08#ibcon#about to read 5, iclass 26, count 0 2006.257.07:27:39.08#ibcon#read 5, iclass 26, count 0 2006.257.07:27:39.08#ibcon#about to read 6, iclass 26, count 0 2006.257.07:27:39.08#ibcon#read 6, iclass 26, count 0 2006.257.07:27:39.08#ibcon#end of sib2, iclass 26, count 0 2006.257.07:27:39.08#ibcon#*after write, iclass 26, count 0 2006.257.07:27:39.08#ibcon#*before return 0, iclass 26, count 0 2006.257.07:27:39.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:39.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:27:39.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.07:27:39.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.07:27:39.08$vck44/vb=7,4 2006.257.07:27:39.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.07:27:39.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.07:27:39.08#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:39.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:39.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:39.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:39.14#ibcon#enter wrdev, iclass 28, count 2 2006.257.07:27:39.14#ibcon#first serial, iclass 28, count 2 2006.257.07:27:39.14#ibcon#enter sib2, iclass 28, count 2 2006.257.07:27:39.14#ibcon#flushed, iclass 28, count 2 2006.257.07:27:39.14#ibcon#about to write, iclass 28, count 2 2006.257.07:27:39.14#ibcon#wrote, iclass 28, count 2 2006.257.07:27:39.14#ibcon#about to read 3, iclass 28, count 2 2006.257.07:27:39.16#ibcon#read 3, iclass 28, count 2 2006.257.07:27:39.16#ibcon#about to read 4, iclass 28, count 2 2006.257.07:27:39.16#ibcon#read 4, iclass 28, count 2 2006.257.07:27:39.16#ibcon#about to read 5, iclass 28, count 2 2006.257.07:27:39.16#ibcon#read 5, iclass 28, count 2 2006.257.07:27:39.16#ibcon#about to read 6, iclass 28, count 2 2006.257.07:27:39.16#ibcon#read 6, iclass 28, count 2 2006.257.07:27:39.16#ibcon#end of sib2, iclass 28, count 2 2006.257.07:27:39.16#ibcon#*mode == 0, iclass 28, count 2 2006.257.07:27:39.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.07:27:39.16#ibcon#[27=AT07-04\r\n] 2006.257.07:27:39.16#ibcon#*before write, iclass 28, count 2 2006.257.07:27:39.16#ibcon#enter sib2, iclass 28, count 2 2006.257.07:27:39.16#ibcon#flushed, iclass 28, count 2 2006.257.07:27:39.16#ibcon#about to write, iclass 28, count 2 2006.257.07:27:39.16#ibcon#wrote, iclass 28, count 2 2006.257.07:27:39.16#ibcon#about to read 3, iclass 28, count 2 2006.257.07:27:39.19#ibcon#read 3, iclass 28, count 2 2006.257.07:27:39.19#ibcon#about to read 4, iclass 28, count 2 2006.257.07:27:39.19#ibcon#read 4, iclass 28, count 2 2006.257.07:27:39.19#ibcon#about to read 5, iclass 28, count 2 2006.257.07:27:39.19#ibcon#read 5, iclass 28, count 2 2006.257.07:27:39.19#ibcon#about to read 6, iclass 28, count 2 2006.257.07:27:39.19#ibcon#read 6, iclass 28, count 2 2006.257.07:27:39.19#ibcon#end of sib2, iclass 28, count 2 2006.257.07:27:39.19#ibcon#*after write, iclass 28, count 2 2006.257.07:27:39.19#ibcon#*before return 0, iclass 28, count 2 2006.257.07:27:39.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:39.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:27:39.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.07:27:39.19#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:39.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:39.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:39.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:39.31#ibcon#enter wrdev, iclass 28, count 0 2006.257.07:27:39.31#ibcon#first serial, iclass 28, count 0 2006.257.07:27:39.31#ibcon#enter sib2, iclass 28, count 0 2006.257.07:27:39.31#ibcon#flushed, iclass 28, count 0 2006.257.07:27:39.31#ibcon#about to write, iclass 28, count 0 2006.257.07:27:39.31#ibcon#wrote, iclass 28, count 0 2006.257.07:27:39.31#ibcon#about to read 3, iclass 28, count 0 2006.257.07:27:39.33#ibcon#read 3, iclass 28, count 0 2006.257.07:27:39.33#ibcon#about to read 4, iclass 28, count 0 2006.257.07:27:39.33#ibcon#read 4, iclass 28, count 0 2006.257.07:27:39.33#ibcon#about to read 5, iclass 28, count 0 2006.257.07:27:39.33#ibcon#read 5, iclass 28, count 0 2006.257.07:27:39.33#ibcon#about to read 6, iclass 28, count 0 2006.257.07:27:39.33#ibcon#read 6, iclass 28, count 0 2006.257.07:27:39.33#ibcon#end of sib2, iclass 28, count 0 2006.257.07:27:39.33#ibcon#*mode == 0, iclass 28, count 0 2006.257.07:27:39.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.07:27:39.33#ibcon#[27=USB\r\n] 2006.257.07:27:39.33#ibcon#*before write, iclass 28, count 0 2006.257.07:27:39.33#ibcon#enter sib2, iclass 28, count 0 2006.257.07:27:39.33#ibcon#flushed, iclass 28, count 0 2006.257.07:27:39.33#ibcon#about to write, iclass 28, count 0 2006.257.07:27:39.33#ibcon#wrote, iclass 28, count 0 2006.257.07:27:39.33#ibcon#about to read 3, iclass 28, count 0 2006.257.07:27:39.36#ibcon#read 3, iclass 28, count 0 2006.257.07:27:39.36#ibcon#about to read 4, iclass 28, count 0 2006.257.07:27:39.36#ibcon#read 4, iclass 28, count 0 2006.257.07:27:39.36#ibcon#about to read 5, iclass 28, count 0 2006.257.07:27:39.36#ibcon#read 5, iclass 28, count 0 2006.257.07:27:39.36#ibcon#about to read 6, iclass 28, count 0 2006.257.07:27:39.36#ibcon#read 6, iclass 28, count 0 2006.257.07:27:39.36#ibcon#end of sib2, iclass 28, count 0 2006.257.07:27:39.36#ibcon#*after write, iclass 28, count 0 2006.257.07:27:39.36#ibcon#*before return 0, iclass 28, count 0 2006.257.07:27:39.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:39.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:27:39.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.07:27:39.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.07:27:39.36$vck44/vblo=8,744.99 2006.257.07:27:39.36#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.07:27:39.36#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.07:27:39.36#ibcon#ireg 17 cls_cnt 0 2006.257.07:27:39.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:39.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:39.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:39.36#ibcon#enter wrdev, iclass 30, count 0 2006.257.07:27:39.36#ibcon#first serial, iclass 30, count 0 2006.257.07:27:39.36#ibcon#enter sib2, iclass 30, count 0 2006.257.07:27:39.36#ibcon#flushed, iclass 30, count 0 2006.257.07:27:39.36#ibcon#about to write, iclass 30, count 0 2006.257.07:27:39.36#ibcon#wrote, iclass 30, count 0 2006.257.07:27:39.36#ibcon#about to read 3, iclass 30, count 0 2006.257.07:27:39.38#ibcon#read 3, iclass 30, count 0 2006.257.07:27:39.38#ibcon#about to read 4, iclass 30, count 0 2006.257.07:27:39.38#ibcon#read 4, iclass 30, count 0 2006.257.07:27:39.38#ibcon#about to read 5, iclass 30, count 0 2006.257.07:27:39.38#ibcon#read 5, iclass 30, count 0 2006.257.07:27:39.38#ibcon#about to read 6, iclass 30, count 0 2006.257.07:27:39.38#ibcon#read 6, iclass 30, count 0 2006.257.07:27:39.38#ibcon#end of sib2, iclass 30, count 0 2006.257.07:27:39.38#ibcon#*mode == 0, iclass 30, count 0 2006.257.07:27:39.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.07:27:39.38#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.07:27:39.38#ibcon#*before write, iclass 30, count 0 2006.257.07:27:39.38#ibcon#enter sib2, iclass 30, count 0 2006.257.07:27:39.38#ibcon#flushed, iclass 30, count 0 2006.257.07:27:39.38#ibcon#about to write, iclass 30, count 0 2006.257.07:27:39.38#ibcon#wrote, iclass 30, count 0 2006.257.07:27:39.38#ibcon#about to read 3, iclass 30, count 0 2006.257.07:27:39.42#ibcon#read 3, iclass 30, count 0 2006.257.07:27:39.42#ibcon#about to read 4, iclass 30, count 0 2006.257.07:27:39.42#ibcon#read 4, iclass 30, count 0 2006.257.07:27:39.42#ibcon#about to read 5, iclass 30, count 0 2006.257.07:27:39.42#ibcon#read 5, iclass 30, count 0 2006.257.07:27:39.42#ibcon#about to read 6, iclass 30, count 0 2006.257.07:27:39.42#ibcon#read 6, iclass 30, count 0 2006.257.07:27:39.42#ibcon#end of sib2, iclass 30, count 0 2006.257.07:27:39.42#ibcon#*after write, iclass 30, count 0 2006.257.07:27:39.42#ibcon#*before return 0, iclass 30, count 0 2006.257.07:27:39.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:39.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:27:39.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.07:27:39.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.07:27:39.42$vck44/vb=8,4 2006.257.07:27:39.42#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.07:27:39.42#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.07:27:39.42#ibcon#ireg 11 cls_cnt 2 2006.257.07:27:39.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:39.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:39.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:39.48#ibcon#enter wrdev, iclass 32, count 2 2006.257.07:27:39.48#ibcon#first serial, iclass 32, count 2 2006.257.07:27:39.48#ibcon#enter sib2, iclass 32, count 2 2006.257.07:27:39.48#ibcon#flushed, iclass 32, count 2 2006.257.07:27:39.48#ibcon#about to write, iclass 32, count 2 2006.257.07:27:39.48#ibcon#wrote, iclass 32, count 2 2006.257.07:27:39.48#ibcon#about to read 3, iclass 32, count 2 2006.257.07:27:39.50#ibcon#read 3, iclass 32, count 2 2006.257.07:27:39.50#ibcon#about to read 4, iclass 32, count 2 2006.257.07:27:39.50#ibcon#read 4, iclass 32, count 2 2006.257.07:27:39.50#ibcon#about to read 5, iclass 32, count 2 2006.257.07:27:39.50#ibcon#read 5, iclass 32, count 2 2006.257.07:27:39.50#ibcon#about to read 6, iclass 32, count 2 2006.257.07:27:39.50#ibcon#read 6, iclass 32, count 2 2006.257.07:27:39.50#ibcon#end of sib2, iclass 32, count 2 2006.257.07:27:39.50#ibcon#*mode == 0, iclass 32, count 2 2006.257.07:27:39.50#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.07:27:39.50#ibcon#[27=AT08-04\r\n] 2006.257.07:27:39.50#ibcon#*before write, iclass 32, count 2 2006.257.07:27:39.50#ibcon#enter sib2, iclass 32, count 2 2006.257.07:27:39.50#ibcon#flushed, iclass 32, count 2 2006.257.07:27:39.50#ibcon#about to write, iclass 32, count 2 2006.257.07:27:39.50#ibcon#wrote, iclass 32, count 2 2006.257.07:27:39.50#ibcon#about to read 3, iclass 32, count 2 2006.257.07:27:39.53#ibcon#read 3, iclass 32, count 2 2006.257.07:27:39.53#ibcon#about to read 4, iclass 32, count 2 2006.257.07:27:39.53#ibcon#read 4, iclass 32, count 2 2006.257.07:27:39.53#ibcon#about to read 5, iclass 32, count 2 2006.257.07:27:39.53#ibcon#read 5, iclass 32, count 2 2006.257.07:27:39.53#ibcon#about to read 6, iclass 32, count 2 2006.257.07:27:39.53#ibcon#read 6, iclass 32, count 2 2006.257.07:27:39.53#ibcon#end of sib2, iclass 32, count 2 2006.257.07:27:39.53#ibcon#*after write, iclass 32, count 2 2006.257.07:27:39.53#ibcon#*before return 0, iclass 32, count 2 2006.257.07:27:39.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:39.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:27:39.53#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.07:27:39.53#ibcon#ireg 7 cls_cnt 0 2006.257.07:27:39.53#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:39.65#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:39.65#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:39.65#ibcon#enter wrdev, iclass 32, count 0 2006.257.07:27:39.65#ibcon#first serial, iclass 32, count 0 2006.257.07:27:39.65#ibcon#enter sib2, iclass 32, count 0 2006.257.07:27:39.65#ibcon#flushed, iclass 32, count 0 2006.257.07:27:39.65#ibcon#about to write, iclass 32, count 0 2006.257.07:27:39.65#ibcon#wrote, iclass 32, count 0 2006.257.07:27:39.65#ibcon#about to read 3, iclass 32, count 0 2006.257.07:27:39.67#ibcon#read 3, iclass 32, count 0 2006.257.07:27:39.67#ibcon#about to read 4, iclass 32, count 0 2006.257.07:27:39.67#ibcon#read 4, iclass 32, count 0 2006.257.07:27:39.67#ibcon#about to read 5, iclass 32, count 0 2006.257.07:27:39.67#ibcon#read 5, iclass 32, count 0 2006.257.07:27:39.67#ibcon#about to read 6, iclass 32, count 0 2006.257.07:27:39.67#ibcon#read 6, iclass 32, count 0 2006.257.07:27:39.67#ibcon#end of sib2, iclass 32, count 0 2006.257.07:27:39.67#ibcon#*mode == 0, iclass 32, count 0 2006.257.07:27:39.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.07:27:39.67#ibcon#[27=USB\r\n] 2006.257.07:27:39.67#ibcon#*before write, iclass 32, count 0 2006.257.07:27:39.67#ibcon#enter sib2, iclass 32, count 0 2006.257.07:27:39.67#ibcon#flushed, iclass 32, count 0 2006.257.07:27:39.67#ibcon#about to write, iclass 32, count 0 2006.257.07:27:39.67#ibcon#wrote, iclass 32, count 0 2006.257.07:27:39.67#ibcon#about to read 3, iclass 32, count 0 2006.257.07:27:39.70#ibcon#read 3, iclass 32, count 0 2006.257.07:27:39.70#ibcon#about to read 4, iclass 32, count 0 2006.257.07:27:39.70#ibcon#read 4, iclass 32, count 0 2006.257.07:27:39.70#ibcon#about to read 5, iclass 32, count 0 2006.257.07:27:39.70#ibcon#read 5, iclass 32, count 0 2006.257.07:27:39.70#ibcon#about to read 6, iclass 32, count 0 2006.257.07:27:39.70#ibcon#read 6, iclass 32, count 0 2006.257.07:27:39.70#ibcon#end of sib2, iclass 32, count 0 2006.257.07:27:39.70#ibcon#*after write, iclass 32, count 0 2006.257.07:27:39.70#ibcon#*before return 0, iclass 32, count 0 2006.257.07:27:39.70#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:39.70#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:27:39.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.07:27:39.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.07:27:39.70$vck44/vabw=wide 2006.257.07:27:39.70#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.07:27:39.70#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.07:27:39.70#ibcon#ireg 8 cls_cnt 0 2006.257.07:27:39.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:39.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:39.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:39.70#ibcon#enter wrdev, iclass 34, count 0 2006.257.07:27:39.70#ibcon#first serial, iclass 34, count 0 2006.257.07:27:39.70#ibcon#enter sib2, iclass 34, count 0 2006.257.07:27:39.70#ibcon#flushed, iclass 34, count 0 2006.257.07:27:39.70#ibcon#about to write, iclass 34, count 0 2006.257.07:27:39.70#ibcon#wrote, iclass 34, count 0 2006.257.07:27:39.70#ibcon#about to read 3, iclass 34, count 0 2006.257.07:27:39.72#ibcon#read 3, iclass 34, count 0 2006.257.07:27:39.72#ibcon#about to read 4, iclass 34, count 0 2006.257.07:27:39.72#ibcon#read 4, iclass 34, count 0 2006.257.07:27:39.72#ibcon#about to read 5, iclass 34, count 0 2006.257.07:27:39.72#ibcon#read 5, iclass 34, count 0 2006.257.07:27:39.72#ibcon#about to read 6, iclass 34, count 0 2006.257.07:27:39.72#ibcon#read 6, iclass 34, count 0 2006.257.07:27:39.72#ibcon#end of sib2, iclass 34, count 0 2006.257.07:27:39.72#ibcon#*mode == 0, iclass 34, count 0 2006.257.07:27:39.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.07:27:39.72#ibcon#[25=BW32\r\n] 2006.257.07:27:39.72#ibcon#*before write, iclass 34, count 0 2006.257.07:27:39.72#ibcon#enter sib2, iclass 34, count 0 2006.257.07:27:39.72#ibcon#flushed, iclass 34, count 0 2006.257.07:27:39.72#ibcon#about to write, iclass 34, count 0 2006.257.07:27:39.72#ibcon#wrote, iclass 34, count 0 2006.257.07:27:39.72#ibcon#about to read 3, iclass 34, count 0 2006.257.07:27:39.75#ibcon#read 3, iclass 34, count 0 2006.257.07:27:39.75#ibcon#about to read 4, iclass 34, count 0 2006.257.07:27:39.75#ibcon#read 4, iclass 34, count 0 2006.257.07:27:39.75#ibcon#about to read 5, iclass 34, count 0 2006.257.07:27:39.75#ibcon#read 5, iclass 34, count 0 2006.257.07:27:39.75#ibcon#about to read 6, iclass 34, count 0 2006.257.07:27:39.75#ibcon#read 6, iclass 34, count 0 2006.257.07:27:39.75#ibcon#end of sib2, iclass 34, count 0 2006.257.07:27:39.75#ibcon#*after write, iclass 34, count 0 2006.257.07:27:39.75#ibcon#*before return 0, iclass 34, count 0 2006.257.07:27:39.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:39.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:27:39.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.07:27:39.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.07:27:39.75$vck44/vbbw=wide 2006.257.07:27:39.75#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.07:27:39.75#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.07:27:39.75#ibcon#ireg 8 cls_cnt 0 2006.257.07:27:39.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:27:39.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:27:39.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:27:39.82#ibcon#enter wrdev, iclass 36, count 0 2006.257.07:27:39.82#ibcon#first serial, iclass 36, count 0 2006.257.07:27:39.82#ibcon#enter sib2, iclass 36, count 0 2006.257.07:27:39.82#ibcon#flushed, iclass 36, count 0 2006.257.07:27:39.82#ibcon#about to write, iclass 36, count 0 2006.257.07:27:39.82#ibcon#wrote, iclass 36, count 0 2006.257.07:27:39.82#ibcon#about to read 3, iclass 36, count 0 2006.257.07:27:39.84#ibcon#read 3, iclass 36, count 0 2006.257.07:27:39.84#ibcon#about to read 4, iclass 36, count 0 2006.257.07:27:39.84#ibcon#read 4, iclass 36, count 0 2006.257.07:27:39.84#ibcon#about to read 5, iclass 36, count 0 2006.257.07:27:39.84#ibcon#read 5, iclass 36, count 0 2006.257.07:27:39.84#ibcon#about to read 6, iclass 36, count 0 2006.257.07:27:39.84#ibcon#read 6, iclass 36, count 0 2006.257.07:27:39.84#ibcon#end of sib2, iclass 36, count 0 2006.257.07:27:39.84#ibcon#*mode == 0, iclass 36, count 0 2006.257.07:27:39.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.07:27:39.84#ibcon#[27=BW32\r\n] 2006.257.07:27:39.84#ibcon#*before write, iclass 36, count 0 2006.257.07:27:39.84#ibcon#enter sib2, iclass 36, count 0 2006.257.07:27:39.84#ibcon#flushed, iclass 36, count 0 2006.257.07:27:39.84#ibcon#about to write, iclass 36, count 0 2006.257.07:27:39.84#ibcon#wrote, iclass 36, count 0 2006.257.07:27:39.84#ibcon#about to read 3, iclass 36, count 0 2006.257.07:27:39.87#ibcon#read 3, iclass 36, count 0 2006.257.07:27:39.87#ibcon#about to read 4, iclass 36, count 0 2006.257.07:27:39.87#ibcon#read 4, iclass 36, count 0 2006.257.07:27:39.87#ibcon#about to read 5, iclass 36, count 0 2006.257.07:27:39.87#ibcon#read 5, iclass 36, count 0 2006.257.07:27:39.87#ibcon#about to read 6, iclass 36, count 0 2006.257.07:27:39.87#ibcon#read 6, iclass 36, count 0 2006.257.07:27:39.87#ibcon#end of sib2, iclass 36, count 0 2006.257.07:27:39.87#ibcon#*after write, iclass 36, count 0 2006.257.07:27:39.87#ibcon#*before return 0, iclass 36, count 0 2006.257.07:27:39.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:27:39.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:27:39.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.07:27:39.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.07:27:39.87$setupk4/ifdk4 2006.257.07:27:39.87$ifdk4/lo= 2006.257.07:27:39.87$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.07:27:39.87$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.07:27:39.87$ifdk4/patch= 2006.257.07:27:39.87$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.07:27:39.87$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.07:27:39.87$setupk4/!*+20s 2006.257.07:27:41.95#abcon#<5=/15 1.7 4.1 21.26 861012.5\r\n> 2006.257.07:27:41.97#abcon#{5=INTERFACE CLEAR} 2006.257.07:27:42.03#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:27:47.14#trakl#Source acquired 2006.257.07:27:47.14#flagr#flagr/antenna,acquired 2006.257.07:27:52.12#abcon#<5=/15 1.7 4.1 21.26 861012.5\r\n> 2006.257.07:27:52.14#abcon#{5=INTERFACE CLEAR} 2006.257.07:27:52.20#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:27:54.38$setupk4/"tpicd 2006.257.07:27:54.38$setupk4/echo=off 2006.257.07:27:54.38$setupk4/xlog=off 2006.257.07:27:54.38:!2006.257.07:30:40 2006.257.07:30:40.00:preob 2006.257.07:30:40.14/onsource/TRACKING 2006.257.07:30:40.14:!2006.257.07:30:50 2006.257.07:30:50.00:"tape 2006.257.07:30:50.00:"st=record 2006.257.07:30:50.00:data_valid=on 2006.257.07:30:50.00:midob 2006.257.07:30:50.14/onsource/TRACKING 2006.257.07:30:50.14/wx/21.23,1012.5,86 2006.257.07:30:50.35/cable/+6.4751E-03 2006.257.07:30:51.44/va/01,08,usb,yes,31,33 2006.257.07:30:51.44/va/02,07,usb,yes,33,34 2006.257.07:30:51.44/va/03,08,usb,yes,30,32 2006.257.07:30:51.44/va/04,07,usb,yes,34,36 2006.257.07:30:51.44/va/05,04,usb,yes,31,31 2006.257.07:30:51.44/va/06,04,usb,yes,34,34 2006.257.07:30:51.44/va/07,04,usb,yes,35,36 2006.257.07:30:51.44/va/08,04,usb,yes,29,36 2006.257.07:30:51.67/valo/01,524.99,yes,locked 2006.257.07:30:51.67/valo/02,534.99,yes,locked 2006.257.07:30:51.67/valo/03,564.99,yes,locked 2006.257.07:30:51.67/valo/04,624.99,yes,locked 2006.257.07:30:51.67/valo/05,734.99,yes,locked 2006.257.07:30:51.67/valo/06,814.99,yes,locked 2006.257.07:30:51.67/valo/07,864.99,yes,locked 2006.257.07:30:51.67/valo/08,884.99,yes,locked 2006.257.07:30:52.76/vb/01,04,usb,yes,31,28 2006.257.07:30:52.76/vb/02,05,usb,yes,29,29 2006.257.07:30:52.76/vb/03,04,usb,yes,30,33 2006.257.07:30:52.76/vb/04,05,usb,yes,30,29 2006.257.07:30:52.76/vb/05,04,usb,yes,27,29 2006.257.07:30:52.76/vb/06,04,usb,yes,31,27 2006.257.07:30:52.76/vb/07,04,usb,yes,31,31 2006.257.07:30:52.76/vb/08,04,usb,yes,28,32 2006.257.07:30:52.99/vblo/01,629.99,yes,locked 2006.257.07:30:52.99/vblo/02,634.99,yes,locked 2006.257.07:30:52.99/vblo/03,649.99,yes,locked 2006.257.07:30:52.99/vblo/04,679.99,yes,locked 2006.257.07:30:52.99/vblo/05,709.99,yes,locked 2006.257.07:30:52.99/vblo/06,719.99,yes,locked 2006.257.07:30:52.99/vblo/07,734.99,yes,locked 2006.257.07:30:52.99/vblo/08,744.99,yes,locked 2006.257.07:30:53.14/vabw/8 2006.257.07:30:53.29/vbbw/8 2006.257.07:30:53.38/xfe/off,on,15.5 2006.257.07:30:53.75/ifatt/23,28,28,28 2006.257.07:30:54.07/fmout-gps/S +4.54E-07 2006.257.07:30:54.11:!2006.257.07:31:30 2006.257.07:31:30.00:data_valid=off 2006.257.07:31:30.00:"et 2006.257.07:31:30.00:!+3s 2006.257.07:31:33.01:"tape 2006.257.07:31:33.01:postob 2006.257.07:31:33.12/cable/+6.4759E-03 2006.257.07:31:33.12/wx/21.22,1012.5,86 2006.257.07:31:34.07/fmout-gps/S +4.54E-07 2006.257.07:31:34.07:scan_name=257-0732,jd0609,100 2006.257.07:31:34.07:source=2121+053,212344.52,053522.1,2000.0,cw 2006.257.07:31:35.14#flagr#flagr/antenna,new-source 2006.257.07:31:35.14:checkk5 2006.257.07:31:35.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.07:31:35.88/chk_autoobs//k5ts2/ autoobs is running! 2006.257.07:31:36.29/chk_autoobs//k5ts3/ autoobs is running! 2006.257.07:31:36.68/chk_autoobs//k5ts4/ autoobs is running! 2006.257.07:31:37.07/chk_obsdata//k5ts1/T2570730??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.07:31:37.48/chk_obsdata//k5ts2/T2570730??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.07:31:37.89/chk_obsdata//k5ts3/T2570730??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.07:31:38.32/chk_obsdata//k5ts4/T2570730??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.07:31:39.05/k5log//k5ts1_log_newline 2006.257.07:31:39.76/k5log//k5ts2_log_newline 2006.257.07:31:40.51/k5log//k5ts3_log_newline 2006.257.07:31:41.23/k5log//k5ts4_log_newline 2006.257.07:31:41.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.07:31:41.25:setupk4=1 2006.257.07:31:41.25$setupk4/echo=on 2006.257.07:31:41.25$setupk4/pcalon 2006.257.07:31:41.25$pcalon/"no phase cal control is implemented here 2006.257.07:31:41.25$setupk4/"tpicd=stop 2006.257.07:31:41.25$setupk4/"rec=synch_on 2006.257.07:31:41.25$setupk4/"rec_mode=128 2006.257.07:31:41.25$setupk4/!* 2006.257.07:31:41.25$setupk4/recpk4 2006.257.07:31:41.25$recpk4/recpatch= 2006.257.07:31:41.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.07:31:41.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.07:31:41.25$setupk4/vck44 2006.257.07:31:41.25$vck44/valo=1,524.99 2006.257.07:31:41.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.07:31:41.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.07:31:41.25#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:41.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:41.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:41.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:41.25#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:31:41.25#ibcon#first serial, iclass 29, count 0 2006.257.07:31:41.25#ibcon#enter sib2, iclass 29, count 0 2006.257.07:31:41.25#ibcon#flushed, iclass 29, count 0 2006.257.07:31:41.25#ibcon#about to write, iclass 29, count 0 2006.257.07:31:41.25#ibcon#wrote, iclass 29, count 0 2006.257.07:31:41.25#ibcon#about to read 3, iclass 29, count 0 2006.257.07:31:41.27#ibcon#read 3, iclass 29, count 0 2006.257.07:31:41.27#ibcon#about to read 4, iclass 29, count 0 2006.257.07:31:41.27#ibcon#read 4, iclass 29, count 0 2006.257.07:31:41.27#ibcon#about to read 5, iclass 29, count 0 2006.257.07:31:41.27#ibcon#read 5, iclass 29, count 0 2006.257.07:31:41.27#ibcon#about to read 6, iclass 29, count 0 2006.257.07:31:41.27#ibcon#read 6, iclass 29, count 0 2006.257.07:31:41.27#ibcon#end of sib2, iclass 29, count 0 2006.257.07:31:41.27#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:31:41.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:31:41.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.07:31:41.27#ibcon#*before write, iclass 29, count 0 2006.257.07:31:41.27#ibcon#enter sib2, iclass 29, count 0 2006.257.07:31:41.27#ibcon#flushed, iclass 29, count 0 2006.257.07:31:41.27#ibcon#about to write, iclass 29, count 0 2006.257.07:31:41.27#ibcon#wrote, iclass 29, count 0 2006.257.07:31:41.27#ibcon#about to read 3, iclass 29, count 0 2006.257.07:31:41.32#ibcon#read 3, iclass 29, count 0 2006.257.07:31:41.32#ibcon#about to read 4, iclass 29, count 0 2006.257.07:31:41.32#ibcon#read 4, iclass 29, count 0 2006.257.07:31:41.32#ibcon#about to read 5, iclass 29, count 0 2006.257.07:31:41.32#ibcon#read 5, iclass 29, count 0 2006.257.07:31:41.32#ibcon#about to read 6, iclass 29, count 0 2006.257.07:31:41.32#ibcon#read 6, iclass 29, count 0 2006.257.07:31:41.32#ibcon#end of sib2, iclass 29, count 0 2006.257.07:31:41.32#ibcon#*after write, iclass 29, count 0 2006.257.07:31:41.32#ibcon#*before return 0, iclass 29, count 0 2006.257.07:31:41.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:41.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:41.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:31:41.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:31:41.32$vck44/va=1,8 2006.257.07:31:41.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.07:31:41.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.07:31:41.32#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:41.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:41.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:41.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:41.32#ibcon#enter wrdev, iclass 31, count 2 2006.257.07:31:41.32#ibcon#first serial, iclass 31, count 2 2006.257.07:31:41.32#ibcon#enter sib2, iclass 31, count 2 2006.257.07:31:41.32#ibcon#flushed, iclass 31, count 2 2006.257.07:31:41.32#ibcon#about to write, iclass 31, count 2 2006.257.07:31:41.32#ibcon#wrote, iclass 31, count 2 2006.257.07:31:41.32#ibcon#about to read 3, iclass 31, count 2 2006.257.07:31:41.34#ibcon#read 3, iclass 31, count 2 2006.257.07:31:41.34#ibcon#about to read 4, iclass 31, count 2 2006.257.07:31:41.34#ibcon#read 4, iclass 31, count 2 2006.257.07:31:41.34#ibcon#about to read 5, iclass 31, count 2 2006.257.07:31:41.34#ibcon#read 5, iclass 31, count 2 2006.257.07:31:41.34#ibcon#about to read 6, iclass 31, count 2 2006.257.07:31:41.34#ibcon#read 6, iclass 31, count 2 2006.257.07:31:41.34#ibcon#end of sib2, iclass 31, count 2 2006.257.07:31:41.34#ibcon#*mode == 0, iclass 31, count 2 2006.257.07:31:41.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.07:31:41.34#ibcon#[25=AT01-08\r\n] 2006.257.07:31:41.34#ibcon#*before write, iclass 31, count 2 2006.257.07:31:41.34#ibcon#enter sib2, iclass 31, count 2 2006.257.07:31:41.34#ibcon#flushed, iclass 31, count 2 2006.257.07:31:41.34#ibcon#about to write, iclass 31, count 2 2006.257.07:31:41.34#ibcon#wrote, iclass 31, count 2 2006.257.07:31:41.34#ibcon#about to read 3, iclass 31, count 2 2006.257.07:31:41.37#ibcon#read 3, iclass 31, count 2 2006.257.07:31:41.37#ibcon#about to read 4, iclass 31, count 2 2006.257.07:31:41.37#ibcon#read 4, iclass 31, count 2 2006.257.07:31:41.37#ibcon#about to read 5, iclass 31, count 2 2006.257.07:31:41.37#ibcon#read 5, iclass 31, count 2 2006.257.07:31:41.37#ibcon#about to read 6, iclass 31, count 2 2006.257.07:31:41.37#ibcon#read 6, iclass 31, count 2 2006.257.07:31:41.37#ibcon#end of sib2, iclass 31, count 2 2006.257.07:31:41.37#ibcon#*after write, iclass 31, count 2 2006.257.07:31:41.37#ibcon#*before return 0, iclass 31, count 2 2006.257.07:31:41.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:41.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:41.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.07:31:41.37#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:41.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:41.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:41.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:41.49#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:31:41.49#ibcon#first serial, iclass 31, count 0 2006.257.07:31:41.49#ibcon#enter sib2, iclass 31, count 0 2006.257.07:31:41.49#ibcon#flushed, iclass 31, count 0 2006.257.07:31:41.49#ibcon#about to write, iclass 31, count 0 2006.257.07:31:41.49#ibcon#wrote, iclass 31, count 0 2006.257.07:31:41.49#ibcon#about to read 3, iclass 31, count 0 2006.257.07:31:41.51#ibcon#read 3, iclass 31, count 0 2006.257.07:31:41.51#ibcon#about to read 4, iclass 31, count 0 2006.257.07:31:41.51#ibcon#read 4, iclass 31, count 0 2006.257.07:31:41.51#ibcon#about to read 5, iclass 31, count 0 2006.257.07:31:41.51#ibcon#read 5, iclass 31, count 0 2006.257.07:31:41.51#ibcon#about to read 6, iclass 31, count 0 2006.257.07:31:41.51#ibcon#read 6, iclass 31, count 0 2006.257.07:31:41.51#ibcon#end of sib2, iclass 31, count 0 2006.257.07:31:41.51#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:31:41.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:31:41.51#ibcon#[25=USB\r\n] 2006.257.07:31:41.51#ibcon#*before write, iclass 31, count 0 2006.257.07:31:41.51#ibcon#enter sib2, iclass 31, count 0 2006.257.07:31:41.51#ibcon#flushed, iclass 31, count 0 2006.257.07:31:41.51#ibcon#about to write, iclass 31, count 0 2006.257.07:31:41.51#ibcon#wrote, iclass 31, count 0 2006.257.07:31:41.51#ibcon#about to read 3, iclass 31, count 0 2006.257.07:31:41.54#ibcon#read 3, iclass 31, count 0 2006.257.07:31:41.54#ibcon#about to read 4, iclass 31, count 0 2006.257.07:31:41.54#ibcon#read 4, iclass 31, count 0 2006.257.07:31:41.54#ibcon#about to read 5, iclass 31, count 0 2006.257.07:31:41.54#ibcon#read 5, iclass 31, count 0 2006.257.07:31:41.54#ibcon#about to read 6, iclass 31, count 0 2006.257.07:31:41.54#ibcon#read 6, iclass 31, count 0 2006.257.07:31:41.54#ibcon#end of sib2, iclass 31, count 0 2006.257.07:31:41.54#ibcon#*after write, iclass 31, count 0 2006.257.07:31:41.54#ibcon#*before return 0, iclass 31, count 0 2006.257.07:31:41.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:41.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:41.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:31:41.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:31:41.54$vck44/valo=2,534.99 2006.257.07:31:41.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.07:31:41.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.07:31:41.54#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:41.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:41.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:41.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:41.54#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:31:41.54#ibcon#first serial, iclass 33, count 0 2006.257.07:31:41.54#ibcon#enter sib2, iclass 33, count 0 2006.257.07:31:41.54#ibcon#flushed, iclass 33, count 0 2006.257.07:31:41.54#ibcon#about to write, iclass 33, count 0 2006.257.07:31:41.54#ibcon#wrote, iclass 33, count 0 2006.257.07:31:41.54#ibcon#about to read 3, iclass 33, count 0 2006.257.07:31:41.56#ibcon#read 3, iclass 33, count 0 2006.257.07:31:41.56#ibcon#about to read 4, iclass 33, count 0 2006.257.07:31:41.56#ibcon#read 4, iclass 33, count 0 2006.257.07:31:41.56#ibcon#about to read 5, iclass 33, count 0 2006.257.07:31:41.56#ibcon#read 5, iclass 33, count 0 2006.257.07:31:41.56#ibcon#about to read 6, iclass 33, count 0 2006.257.07:31:41.56#ibcon#read 6, iclass 33, count 0 2006.257.07:31:41.56#ibcon#end of sib2, iclass 33, count 0 2006.257.07:31:41.56#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:31:41.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:31:41.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.07:31:41.56#ibcon#*before write, iclass 33, count 0 2006.257.07:31:41.56#ibcon#enter sib2, iclass 33, count 0 2006.257.07:31:41.56#ibcon#flushed, iclass 33, count 0 2006.257.07:31:41.56#ibcon#about to write, iclass 33, count 0 2006.257.07:31:41.56#ibcon#wrote, iclass 33, count 0 2006.257.07:31:41.56#ibcon#about to read 3, iclass 33, count 0 2006.257.07:31:41.60#ibcon#read 3, iclass 33, count 0 2006.257.07:31:41.60#ibcon#about to read 4, iclass 33, count 0 2006.257.07:31:41.60#ibcon#read 4, iclass 33, count 0 2006.257.07:31:41.60#ibcon#about to read 5, iclass 33, count 0 2006.257.07:31:41.60#ibcon#read 5, iclass 33, count 0 2006.257.07:31:41.60#ibcon#about to read 6, iclass 33, count 0 2006.257.07:31:41.60#ibcon#read 6, iclass 33, count 0 2006.257.07:31:41.60#ibcon#end of sib2, iclass 33, count 0 2006.257.07:31:41.60#ibcon#*after write, iclass 33, count 0 2006.257.07:31:41.60#ibcon#*before return 0, iclass 33, count 0 2006.257.07:31:41.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:41.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:41.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:31:41.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:31:41.60$vck44/va=2,7 2006.257.07:31:41.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.07:31:41.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.07:31:41.60#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:41.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:41.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:41.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:41.66#ibcon#enter wrdev, iclass 35, count 2 2006.257.07:31:41.66#ibcon#first serial, iclass 35, count 2 2006.257.07:31:41.66#ibcon#enter sib2, iclass 35, count 2 2006.257.07:31:41.66#ibcon#flushed, iclass 35, count 2 2006.257.07:31:41.66#ibcon#about to write, iclass 35, count 2 2006.257.07:31:41.66#ibcon#wrote, iclass 35, count 2 2006.257.07:31:41.66#ibcon#about to read 3, iclass 35, count 2 2006.257.07:31:41.68#ibcon#read 3, iclass 35, count 2 2006.257.07:31:41.68#ibcon#about to read 4, iclass 35, count 2 2006.257.07:31:41.68#ibcon#read 4, iclass 35, count 2 2006.257.07:31:41.68#ibcon#about to read 5, iclass 35, count 2 2006.257.07:31:41.68#ibcon#read 5, iclass 35, count 2 2006.257.07:31:41.68#ibcon#about to read 6, iclass 35, count 2 2006.257.07:31:41.68#ibcon#read 6, iclass 35, count 2 2006.257.07:31:41.68#ibcon#end of sib2, iclass 35, count 2 2006.257.07:31:41.68#ibcon#*mode == 0, iclass 35, count 2 2006.257.07:31:41.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.07:31:41.68#ibcon#[25=AT02-07\r\n] 2006.257.07:31:41.68#ibcon#*before write, iclass 35, count 2 2006.257.07:31:41.68#ibcon#enter sib2, iclass 35, count 2 2006.257.07:31:41.68#ibcon#flushed, iclass 35, count 2 2006.257.07:31:41.68#ibcon#about to write, iclass 35, count 2 2006.257.07:31:41.68#ibcon#wrote, iclass 35, count 2 2006.257.07:31:41.68#ibcon#about to read 3, iclass 35, count 2 2006.257.07:31:41.71#ibcon#read 3, iclass 35, count 2 2006.257.07:31:41.71#ibcon#about to read 4, iclass 35, count 2 2006.257.07:31:41.71#ibcon#read 4, iclass 35, count 2 2006.257.07:31:41.71#ibcon#about to read 5, iclass 35, count 2 2006.257.07:31:41.71#ibcon#read 5, iclass 35, count 2 2006.257.07:31:41.71#ibcon#about to read 6, iclass 35, count 2 2006.257.07:31:41.71#ibcon#read 6, iclass 35, count 2 2006.257.07:31:41.71#ibcon#end of sib2, iclass 35, count 2 2006.257.07:31:41.71#ibcon#*after write, iclass 35, count 2 2006.257.07:31:41.71#ibcon#*before return 0, iclass 35, count 2 2006.257.07:31:41.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:41.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:41.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.07:31:41.71#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:41.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:41.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:41.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:41.83#ibcon#enter wrdev, iclass 35, count 0 2006.257.07:31:41.83#ibcon#first serial, iclass 35, count 0 2006.257.07:31:41.83#ibcon#enter sib2, iclass 35, count 0 2006.257.07:31:41.83#ibcon#flushed, iclass 35, count 0 2006.257.07:31:41.83#ibcon#about to write, iclass 35, count 0 2006.257.07:31:41.83#ibcon#wrote, iclass 35, count 0 2006.257.07:31:41.83#ibcon#about to read 3, iclass 35, count 0 2006.257.07:31:41.85#ibcon#read 3, iclass 35, count 0 2006.257.07:31:41.85#ibcon#about to read 4, iclass 35, count 0 2006.257.07:31:41.85#ibcon#read 4, iclass 35, count 0 2006.257.07:31:41.85#ibcon#about to read 5, iclass 35, count 0 2006.257.07:31:41.85#ibcon#read 5, iclass 35, count 0 2006.257.07:31:41.85#ibcon#about to read 6, iclass 35, count 0 2006.257.07:31:41.85#ibcon#read 6, iclass 35, count 0 2006.257.07:31:41.85#ibcon#end of sib2, iclass 35, count 0 2006.257.07:31:41.85#ibcon#*mode == 0, iclass 35, count 0 2006.257.07:31:41.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.07:31:41.85#ibcon#[25=USB\r\n] 2006.257.07:31:41.85#ibcon#*before write, iclass 35, count 0 2006.257.07:31:41.85#ibcon#enter sib2, iclass 35, count 0 2006.257.07:31:41.85#ibcon#flushed, iclass 35, count 0 2006.257.07:31:41.85#ibcon#about to write, iclass 35, count 0 2006.257.07:31:41.85#ibcon#wrote, iclass 35, count 0 2006.257.07:31:41.85#ibcon#about to read 3, iclass 35, count 0 2006.257.07:31:41.88#ibcon#read 3, iclass 35, count 0 2006.257.07:31:41.88#ibcon#about to read 4, iclass 35, count 0 2006.257.07:31:41.88#ibcon#read 4, iclass 35, count 0 2006.257.07:31:41.88#ibcon#about to read 5, iclass 35, count 0 2006.257.07:31:41.88#ibcon#read 5, iclass 35, count 0 2006.257.07:31:41.88#ibcon#about to read 6, iclass 35, count 0 2006.257.07:31:41.88#ibcon#read 6, iclass 35, count 0 2006.257.07:31:41.88#ibcon#end of sib2, iclass 35, count 0 2006.257.07:31:41.88#ibcon#*after write, iclass 35, count 0 2006.257.07:31:41.88#ibcon#*before return 0, iclass 35, count 0 2006.257.07:31:41.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:41.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:41.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.07:31:41.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.07:31:41.88$vck44/valo=3,564.99 2006.257.07:31:41.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.07:31:41.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.07:31:41.88#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:41.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:41.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:41.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:41.88#ibcon#enter wrdev, iclass 37, count 0 2006.257.07:31:41.88#ibcon#first serial, iclass 37, count 0 2006.257.07:31:41.88#ibcon#enter sib2, iclass 37, count 0 2006.257.07:31:41.88#ibcon#flushed, iclass 37, count 0 2006.257.07:31:41.88#ibcon#about to write, iclass 37, count 0 2006.257.07:31:41.88#ibcon#wrote, iclass 37, count 0 2006.257.07:31:41.88#ibcon#about to read 3, iclass 37, count 0 2006.257.07:31:41.90#ibcon#read 3, iclass 37, count 0 2006.257.07:31:41.90#ibcon#about to read 4, iclass 37, count 0 2006.257.07:31:41.90#ibcon#read 4, iclass 37, count 0 2006.257.07:31:41.90#ibcon#about to read 5, iclass 37, count 0 2006.257.07:31:41.90#ibcon#read 5, iclass 37, count 0 2006.257.07:31:41.90#ibcon#about to read 6, iclass 37, count 0 2006.257.07:31:41.90#ibcon#read 6, iclass 37, count 0 2006.257.07:31:41.90#ibcon#end of sib2, iclass 37, count 0 2006.257.07:31:41.90#ibcon#*mode == 0, iclass 37, count 0 2006.257.07:31:41.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.07:31:41.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.07:31:41.90#ibcon#*before write, iclass 37, count 0 2006.257.07:31:41.90#ibcon#enter sib2, iclass 37, count 0 2006.257.07:31:41.90#ibcon#flushed, iclass 37, count 0 2006.257.07:31:41.90#ibcon#about to write, iclass 37, count 0 2006.257.07:31:41.90#ibcon#wrote, iclass 37, count 0 2006.257.07:31:41.90#ibcon#about to read 3, iclass 37, count 0 2006.257.07:31:41.94#ibcon#read 3, iclass 37, count 0 2006.257.07:31:41.94#ibcon#about to read 4, iclass 37, count 0 2006.257.07:31:41.94#ibcon#read 4, iclass 37, count 0 2006.257.07:31:41.94#ibcon#about to read 5, iclass 37, count 0 2006.257.07:31:41.94#ibcon#read 5, iclass 37, count 0 2006.257.07:31:41.94#ibcon#about to read 6, iclass 37, count 0 2006.257.07:31:41.94#ibcon#read 6, iclass 37, count 0 2006.257.07:31:41.94#ibcon#end of sib2, iclass 37, count 0 2006.257.07:31:41.94#ibcon#*after write, iclass 37, count 0 2006.257.07:31:41.94#ibcon#*before return 0, iclass 37, count 0 2006.257.07:31:41.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:41.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:41.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.07:31:41.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.07:31:41.94$vck44/va=3,8 2006.257.07:31:41.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.07:31:41.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.07:31:41.94#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:41.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:42.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:42.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:42.00#ibcon#enter wrdev, iclass 39, count 2 2006.257.07:31:42.00#ibcon#first serial, iclass 39, count 2 2006.257.07:31:42.00#ibcon#enter sib2, iclass 39, count 2 2006.257.07:31:42.00#ibcon#flushed, iclass 39, count 2 2006.257.07:31:42.00#ibcon#about to write, iclass 39, count 2 2006.257.07:31:42.00#ibcon#wrote, iclass 39, count 2 2006.257.07:31:42.00#ibcon#about to read 3, iclass 39, count 2 2006.257.07:31:42.02#ibcon#read 3, iclass 39, count 2 2006.257.07:31:42.02#ibcon#about to read 4, iclass 39, count 2 2006.257.07:31:42.02#ibcon#read 4, iclass 39, count 2 2006.257.07:31:42.02#ibcon#about to read 5, iclass 39, count 2 2006.257.07:31:42.02#ibcon#read 5, iclass 39, count 2 2006.257.07:31:42.02#ibcon#about to read 6, iclass 39, count 2 2006.257.07:31:42.02#ibcon#read 6, iclass 39, count 2 2006.257.07:31:42.02#ibcon#end of sib2, iclass 39, count 2 2006.257.07:31:42.02#ibcon#*mode == 0, iclass 39, count 2 2006.257.07:31:42.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.07:31:42.02#ibcon#[25=AT03-08\r\n] 2006.257.07:31:42.02#ibcon#*before write, iclass 39, count 2 2006.257.07:31:42.02#ibcon#enter sib2, iclass 39, count 2 2006.257.07:31:42.02#ibcon#flushed, iclass 39, count 2 2006.257.07:31:42.02#ibcon#about to write, iclass 39, count 2 2006.257.07:31:42.02#ibcon#wrote, iclass 39, count 2 2006.257.07:31:42.02#ibcon#about to read 3, iclass 39, count 2 2006.257.07:31:42.05#ibcon#read 3, iclass 39, count 2 2006.257.07:31:42.05#ibcon#about to read 4, iclass 39, count 2 2006.257.07:31:42.05#ibcon#read 4, iclass 39, count 2 2006.257.07:31:42.05#ibcon#about to read 5, iclass 39, count 2 2006.257.07:31:42.05#ibcon#read 5, iclass 39, count 2 2006.257.07:31:42.05#ibcon#about to read 6, iclass 39, count 2 2006.257.07:31:42.05#ibcon#read 6, iclass 39, count 2 2006.257.07:31:42.05#ibcon#end of sib2, iclass 39, count 2 2006.257.07:31:42.05#ibcon#*after write, iclass 39, count 2 2006.257.07:31:42.05#ibcon#*before return 0, iclass 39, count 2 2006.257.07:31:42.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:42.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:42.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.07:31:42.05#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:42.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:42.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:42.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:42.17#ibcon#enter wrdev, iclass 39, count 0 2006.257.07:31:42.17#ibcon#first serial, iclass 39, count 0 2006.257.07:31:42.17#ibcon#enter sib2, iclass 39, count 0 2006.257.07:31:42.17#ibcon#flushed, iclass 39, count 0 2006.257.07:31:42.17#ibcon#about to write, iclass 39, count 0 2006.257.07:31:42.17#ibcon#wrote, iclass 39, count 0 2006.257.07:31:42.17#ibcon#about to read 3, iclass 39, count 0 2006.257.07:31:42.19#ibcon#read 3, iclass 39, count 0 2006.257.07:31:42.19#ibcon#about to read 4, iclass 39, count 0 2006.257.07:31:42.19#ibcon#read 4, iclass 39, count 0 2006.257.07:31:42.19#ibcon#about to read 5, iclass 39, count 0 2006.257.07:31:42.19#ibcon#read 5, iclass 39, count 0 2006.257.07:31:42.19#ibcon#about to read 6, iclass 39, count 0 2006.257.07:31:42.19#ibcon#read 6, iclass 39, count 0 2006.257.07:31:42.19#ibcon#end of sib2, iclass 39, count 0 2006.257.07:31:42.19#ibcon#*mode == 0, iclass 39, count 0 2006.257.07:31:42.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.07:31:42.19#ibcon#[25=USB\r\n] 2006.257.07:31:42.19#ibcon#*before write, iclass 39, count 0 2006.257.07:31:42.19#ibcon#enter sib2, iclass 39, count 0 2006.257.07:31:42.19#ibcon#flushed, iclass 39, count 0 2006.257.07:31:42.19#ibcon#about to write, iclass 39, count 0 2006.257.07:31:42.19#ibcon#wrote, iclass 39, count 0 2006.257.07:31:42.19#ibcon#about to read 3, iclass 39, count 0 2006.257.07:31:42.22#ibcon#read 3, iclass 39, count 0 2006.257.07:31:42.22#ibcon#about to read 4, iclass 39, count 0 2006.257.07:31:42.22#ibcon#read 4, iclass 39, count 0 2006.257.07:31:42.22#ibcon#about to read 5, iclass 39, count 0 2006.257.07:31:42.22#ibcon#read 5, iclass 39, count 0 2006.257.07:31:42.22#ibcon#about to read 6, iclass 39, count 0 2006.257.07:31:42.22#ibcon#read 6, iclass 39, count 0 2006.257.07:31:42.22#ibcon#end of sib2, iclass 39, count 0 2006.257.07:31:42.22#ibcon#*after write, iclass 39, count 0 2006.257.07:31:42.22#ibcon#*before return 0, iclass 39, count 0 2006.257.07:31:42.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:42.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:42.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.07:31:42.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.07:31:42.22$vck44/valo=4,624.99 2006.257.07:31:42.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.07:31:42.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.07:31:42.22#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:42.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:42.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:42.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:42.22#ibcon#enter wrdev, iclass 3, count 0 2006.257.07:31:42.22#ibcon#first serial, iclass 3, count 0 2006.257.07:31:42.22#ibcon#enter sib2, iclass 3, count 0 2006.257.07:31:42.22#ibcon#flushed, iclass 3, count 0 2006.257.07:31:42.22#ibcon#about to write, iclass 3, count 0 2006.257.07:31:42.22#ibcon#wrote, iclass 3, count 0 2006.257.07:31:42.22#ibcon#about to read 3, iclass 3, count 0 2006.257.07:31:42.24#ibcon#read 3, iclass 3, count 0 2006.257.07:31:42.24#ibcon#about to read 4, iclass 3, count 0 2006.257.07:31:42.24#ibcon#read 4, iclass 3, count 0 2006.257.07:31:42.24#ibcon#about to read 5, iclass 3, count 0 2006.257.07:31:42.24#ibcon#read 5, iclass 3, count 0 2006.257.07:31:42.24#ibcon#about to read 6, iclass 3, count 0 2006.257.07:31:42.24#ibcon#read 6, iclass 3, count 0 2006.257.07:31:42.24#ibcon#end of sib2, iclass 3, count 0 2006.257.07:31:42.24#ibcon#*mode == 0, iclass 3, count 0 2006.257.07:31:42.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.07:31:42.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.07:31:42.24#ibcon#*before write, iclass 3, count 0 2006.257.07:31:42.24#ibcon#enter sib2, iclass 3, count 0 2006.257.07:31:42.24#ibcon#flushed, iclass 3, count 0 2006.257.07:31:42.24#ibcon#about to write, iclass 3, count 0 2006.257.07:31:42.24#ibcon#wrote, iclass 3, count 0 2006.257.07:31:42.24#ibcon#about to read 3, iclass 3, count 0 2006.257.07:31:42.28#ibcon#read 3, iclass 3, count 0 2006.257.07:31:42.28#ibcon#about to read 4, iclass 3, count 0 2006.257.07:31:42.28#ibcon#read 4, iclass 3, count 0 2006.257.07:31:42.28#ibcon#about to read 5, iclass 3, count 0 2006.257.07:31:42.28#ibcon#read 5, iclass 3, count 0 2006.257.07:31:42.28#ibcon#about to read 6, iclass 3, count 0 2006.257.07:31:42.28#ibcon#read 6, iclass 3, count 0 2006.257.07:31:42.28#ibcon#end of sib2, iclass 3, count 0 2006.257.07:31:42.28#ibcon#*after write, iclass 3, count 0 2006.257.07:31:42.28#ibcon#*before return 0, iclass 3, count 0 2006.257.07:31:42.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:42.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:42.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.07:31:42.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.07:31:42.28$vck44/va=4,7 2006.257.07:31:42.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.07:31:42.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.07:31:42.28#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:42.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:42.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:42.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:42.34#ibcon#enter wrdev, iclass 5, count 2 2006.257.07:31:42.34#ibcon#first serial, iclass 5, count 2 2006.257.07:31:42.34#ibcon#enter sib2, iclass 5, count 2 2006.257.07:31:42.34#ibcon#flushed, iclass 5, count 2 2006.257.07:31:42.34#ibcon#about to write, iclass 5, count 2 2006.257.07:31:42.34#ibcon#wrote, iclass 5, count 2 2006.257.07:31:42.34#ibcon#about to read 3, iclass 5, count 2 2006.257.07:31:42.36#ibcon#read 3, iclass 5, count 2 2006.257.07:31:42.36#ibcon#about to read 4, iclass 5, count 2 2006.257.07:31:42.36#ibcon#read 4, iclass 5, count 2 2006.257.07:31:42.36#ibcon#about to read 5, iclass 5, count 2 2006.257.07:31:42.36#ibcon#read 5, iclass 5, count 2 2006.257.07:31:42.36#ibcon#about to read 6, iclass 5, count 2 2006.257.07:31:42.36#ibcon#read 6, iclass 5, count 2 2006.257.07:31:42.36#ibcon#end of sib2, iclass 5, count 2 2006.257.07:31:42.36#ibcon#*mode == 0, iclass 5, count 2 2006.257.07:31:42.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.07:31:42.36#ibcon#[25=AT04-07\r\n] 2006.257.07:31:42.36#ibcon#*before write, iclass 5, count 2 2006.257.07:31:42.36#ibcon#enter sib2, iclass 5, count 2 2006.257.07:31:42.36#ibcon#flushed, iclass 5, count 2 2006.257.07:31:42.36#ibcon#about to write, iclass 5, count 2 2006.257.07:31:42.36#ibcon#wrote, iclass 5, count 2 2006.257.07:31:42.36#ibcon#about to read 3, iclass 5, count 2 2006.257.07:31:42.39#ibcon#read 3, iclass 5, count 2 2006.257.07:31:42.39#ibcon#about to read 4, iclass 5, count 2 2006.257.07:31:42.39#ibcon#read 4, iclass 5, count 2 2006.257.07:31:42.39#ibcon#about to read 5, iclass 5, count 2 2006.257.07:31:42.39#ibcon#read 5, iclass 5, count 2 2006.257.07:31:42.39#ibcon#about to read 6, iclass 5, count 2 2006.257.07:31:42.39#ibcon#read 6, iclass 5, count 2 2006.257.07:31:42.39#ibcon#end of sib2, iclass 5, count 2 2006.257.07:31:42.39#ibcon#*after write, iclass 5, count 2 2006.257.07:31:42.39#ibcon#*before return 0, iclass 5, count 2 2006.257.07:31:42.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:42.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:42.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.07:31:42.39#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:42.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:42.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:42.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:42.51#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:31:42.51#ibcon#first serial, iclass 5, count 0 2006.257.07:31:42.51#ibcon#enter sib2, iclass 5, count 0 2006.257.07:31:42.51#ibcon#flushed, iclass 5, count 0 2006.257.07:31:42.51#ibcon#about to write, iclass 5, count 0 2006.257.07:31:42.51#ibcon#wrote, iclass 5, count 0 2006.257.07:31:42.51#ibcon#about to read 3, iclass 5, count 0 2006.257.07:31:42.53#ibcon#read 3, iclass 5, count 0 2006.257.07:31:42.53#ibcon#about to read 4, iclass 5, count 0 2006.257.07:31:42.53#ibcon#read 4, iclass 5, count 0 2006.257.07:31:42.53#ibcon#about to read 5, iclass 5, count 0 2006.257.07:31:42.53#ibcon#read 5, iclass 5, count 0 2006.257.07:31:42.53#ibcon#about to read 6, iclass 5, count 0 2006.257.07:31:42.53#ibcon#read 6, iclass 5, count 0 2006.257.07:31:42.53#ibcon#end of sib2, iclass 5, count 0 2006.257.07:31:42.53#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:31:42.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:31:42.53#ibcon#[25=USB\r\n] 2006.257.07:31:42.53#ibcon#*before write, iclass 5, count 0 2006.257.07:31:42.53#ibcon#enter sib2, iclass 5, count 0 2006.257.07:31:42.53#ibcon#flushed, iclass 5, count 0 2006.257.07:31:42.53#ibcon#about to write, iclass 5, count 0 2006.257.07:31:42.53#ibcon#wrote, iclass 5, count 0 2006.257.07:31:42.53#ibcon#about to read 3, iclass 5, count 0 2006.257.07:31:42.56#ibcon#read 3, iclass 5, count 0 2006.257.07:31:42.56#ibcon#about to read 4, iclass 5, count 0 2006.257.07:31:42.56#ibcon#read 4, iclass 5, count 0 2006.257.07:31:42.56#ibcon#about to read 5, iclass 5, count 0 2006.257.07:31:42.56#ibcon#read 5, iclass 5, count 0 2006.257.07:31:42.56#ibcon#about to read 6, iclass 5, count 0 2006.257.07:31:42.56#ibcon#read 6, iclass 5, count 0 2006.257.07:31:42.56#ibcon#end of sib2, iclass 5, count 0 2006.257.07:31:42.56#ibcon#*after write, iclass 5, count 0 2006.257.07:31:42.56#ibcon#*before return 0, iclass 5, count 0 2006.257.07:31:42.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:42.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:42.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:31:42.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:31:42.56$vck44/valo=5,734.99 2006.257.07:31:42.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.07:31:42.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.07:31:42.56#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:42.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:42.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:42.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:42.56#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:31:42.56#ibcon#first serial, iclass 7, count 0 2006.257.07:31:42.56#ibcon#enter sib2, iclass 7, count 0 2006.257.07:31:42.56#ibcon#flushed, iclass 7, count 0 2006.257.07:31:42.56#ibcon#about to write, iclass 7, count 0 2006.257.07:31:42.56#ibcon#wrote, iclass 7, count 0 2006.257.07:31:42.56#ibcon#about to read 3, iclass 7, count 0 2006.257.07:31:42.58#ibcon#read 3, iclass 7, count 0 2006.257.07:31:42.58#ibcon#about to read 4, iclass 7, count 0 2006.257.07:31:42.58#ibcon#read 4, iclass 7, count 0 2006.257.07:31:42.58#ibcon#about to read 5, iclass 7, count 0 2006.257.07:31:42.58#ibcon#read 5, iclass 7, count 0 2006.257.07:31:42.58#ibcon#about to read 6, iclass 7, count 0 2006.257.07:31:42.58#ibcon#read 6, iclass 7, count 0 2006.257.07:31:42.58#ibcon#end of sib2, iclass 7, count 0 2006.257.07:31:42.58#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:31:42.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:31:42.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.07:31:42.58#ibcon#*before write, iclass 7, count 0 2006.257.07:31:42.58#ibcon#enter sib2, iclass 7, count 0 2006.257.07:31:42.58#ibcon#flushed, iclass 7, count 0 2006.257.07:31:42.58#ibcon#about to write, iclass 7, count 0 2006.257.07:31:42.58#ibcon#wrote, iclass 7, count 0 2006.257.07:31:42.58#ibcon#about to read 3, iclass 7, count 0 2006.257.07:31:42.62#ibcon#read 3, iclass 7, count 0 2006.257.07:31:42.62#ibcon#about to read 4, iclass 7, count 0 2006.257.07:31:42.62#ibcon#read 4, iclass 7, count 0 2006.257.07:31:42.62#ibcon#about to read 5, iclass 7, count 0 2006.257.07:31:42.62#ibcon#read 5, iclass 7, count 0 2006.257.07:31:42.62#ibcon#about to read 6, iclass 7, count 0 2006.257.07:31:42.62#ibcon#read 6, iclass 7, count 0 2006.257.07:31:42.62#ibcon#end of sib2, iclass 7, count 0 2006.257.07:31:42.62#ibcon#*after write, iclass 7, count 0 2006.257.07:31:42.62#ibcon#*before return 0, iclass 7, count 0 2006.257.07:31:42.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:42.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:42.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:31:42.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:31:42.62$vck44/va=5,4 2006.257.07:31:42.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.07:31:42.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.07:31:42.62#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:42.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:42.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:42.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:42.68#ibcon#enter wrdev, iclass 11, count 2 2006.257.07:31:42.68#ibcon#first serial, iclass 11, count 2 2006.257.07:31:42.68#ibcon#enter sib2, iclass 11, count 2 2006.257.07:31:42.68#ibcon#flushed, iclass 11, count 2 2006.257.07:31:42.68#ibcon#about to write, iclass 11, count 2 2006.257.07:31:42.68#ibcon#wrote, iclass 11, count 2 2006.257.07:31:42.68#ibcon#about to read 3, iclass 11, count 2 2006.257.07:31:42.70#ibcon#read 3, iclass 11, count 2 2006.257.07:31:42.70#ibcon#about to read 4, iclass 11, count 2 2006.257.07:31:42.70#ibcon#read 4, iclass 11, count 2 2006.257.07:31:42.70#ibcon#about to read 5, iclass 11, count 2 2006.257.07:31:42.70#ibcon#read 5, iclass 11, count 2 2006.257.07:31:42.70#ibcon#about to read 6, iclass 11, count 2 2006.257.07:31:42.70#ibcon#read 6, iclass 11, count 2 2006.257.07:31:42.70#ibcon#end of sib2, iclass 11, count 2 2006.257.07:31:42.70#ibcon#*mode == 0, iclass 11, count 2 2006.257.07:31:42.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.07:31:42.70#ibcon#[25=AT05-04\r\n] 2006.257.07:31:42.70#ibcon#*before write, iclass 11, count 2 2006.257.07:31:42.70#ibcon#enter sib2, iclass 11, count 2 2006.257.07:31:42.70#ibcon#flushed, iclass 11, count 2 2006.257.07:31:42.70#ibcon#about to write, iclass 11, count 2 2006.257.07:31:42.70#ibcon#wrote, iclass 11, count 2 2006.257.07:31:42.70#ibcon#about to read 3, iclass 11, count 2 2006.257.07:31:42.73#ibcon#read 3, iclass 11, count 2 2006.257.07:31:42.73#ibcon#about to read 4, iclass 11, count 2 2006.257.07:31:42.73#ibcon#read 4, iclass 11, count 2 2006.257.07:31:42.73#ibcon#about to read 5, iclass 11, count 2 2006.257.07:31:42.73#ibcon#read 5, iclass 11, count 2 2006.257.07:31:42.73#ibcon#about to read 6, iclass 11, count 2 2006.257.07:31:42.73#ibcon#read 6, iclass 11, count 2 2006.257.07:31:42.73#ibcon#end of sib2, iclass 11, count 2 2006.257.07:31:42.73#ibcon#*after write, iclass 11, count 2 2006.257.07:31:42.73#ibcon#*before return 0, iclass 11, count 2 2006.257.07:31:42.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:42.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:42.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.07:31:42.73#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:42.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:42.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:42.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:42.85#ibcon#enter wrdev, iclass 11, count 0 2006.257.07:31:42.85#ibcon#first serial, iclass 11, count 0 2006.257.07:31:42.85#ibcon#enter sib2, iclass 11, count 0 2006.257.07:31:42.85#ibcon#flushed, iclass 11, count 0 2006.257.07:31:42.85#ibcon#about to write, iclass 11, count 0 2006.257.07:31:42.85#ibcon#wrote, iclass 11, count 0 2006.257.07:31:42.85#ibcon#about to read 3, iclass 11, count 0 2006.257.07:31:42.87#ibcon#read 3, iclass 11, count 0 2006.257.07:31:42.87#ibcon#about to read 4, iclass 11, count 0 2006.257.07:31:42.87#ibcon#read 4, iclass 11, count 0 2006.257.07:31:42.87#ibcon#about to read 5, iclass 11, count 0 2006.257.07:31:42.87#ibcon#read 5, iclass 11, count 0 2006.257.07:31:42.87#ibcon#about to read 6, iclass 11, count 0 2006.257.07:31:42.87#ibcon#read 6, iclass 11, count 0 2006.257.07:31:42.87#ibcon#end of sib2, iclass 11, count 0 2006.257.07:31:42.87#ibcon#*mode == 0, iclass 11, count 0 2006.257.07:31:42.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.07:31:42.87#ibcon#[25=USB\r\n] 2006.257.07:31:42.87#ibcon#*before write, iclass 11, count 0 2006.257.07:31:42.87#ibcon#enter sib2, iclass 11, count 0 2006.257.07:31:42.87#ibcon#flushed, iclass 11, count 0 2006.257.07:31:42.87#ibcon#about to write, iclass 11, count 0 2006.257.07:31:42.87#ibcon#wrote, iclass 11, count 0 2006.257.07:31:42.87#ibcon#about to read 3, iclass 11, count 0 2006.257.07:31:42.90#ibcon#read 3, iclass 11, count 0 2006.257.07:31:42.90#ibcon#about to read 4, iclass 11, count 0 2006.257.07:31:42.90#ibcon#read 4, iclass 11, count 0 2006.257.07:31:42.90#ibcon#about to read 5, iclass 11, count 0 2006.257.07:31:42.90#ibcon#read 5, iclass 11, count 0 2006.257.07:31:42.90#ibcon#about to read 6, iclass 11, count 0 2006.257.07:31:42.90#ibcon#read 6, iclass 11, count 0 2006.257.07:31:42.90#ibcon#end of sib2, iclass 11, count 0 2006.257.07:31:42.90#ibcon#*after write, iclass 11, count 0 2006.257.07:31:42.90#ibcon#*before return 0, iclass 11, count 0 2006.257.07:31:42.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:42.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:42.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.07:31:42.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.07:31:42.90$vck44/valo=6,814.99 2006.257.07:31:42.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.07:31:42.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.07:31:42.90#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:42.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:42.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:42.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:42.90#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:31:42.90#ibcon#first serial, iclass 13, count 0 2006.257.07:31:42.90#ibcon#enter sib2, iclass 13, count 0 2006.257.07:31:42.90#ibcon#flushed, iclass 13, count 0 2006.257.07:31:42.90#ibcon#about to write, iclass 13, count 0 2006.257.07:31:42.90#ibcon#wrote, iclass 13, count 0 2006.257.07:31:42.90#ibcon#about to read 3, iclass 13, count 0 2006.257.07:31:42.92#ibcon#read 3, iclass 13, count 0 2006.257.07:31:42.92#ibcon#about to read 4, iclass 13, count 0 2006.257.07:31:42.92#ibcon#read 4, iclass 13, count 0 2006.257.07:31:42.92#ibcon#about to read 5, iclass 13, count 0 2006.257.07:31:42.92#ibcon#read 5, iclass 13, count 0 2006.257.07:31:42.92#ibcon#about to read 6, iclass 13, count 0 2006.257.07:31:42.92#ibcon#read 6, iclass 13, count 0 2006.257.07:31:42.92#ibcon#end of sib2, iclass 13, count 0 2006.257.07:31:42.92#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:31:42.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:31:42.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.07:31:42.92#ibcon#*before write, iclass 13, count 0 2006.257.07:31:42.92#ibcon#enter sib2, iclass 13, count 0 2006.257.07:31:42.92#ibcon#flushed, iclass 13, count 0 2006.257.07:31:42.92#ibcon#about to write, iclass 13, count 0 2006.257.07:31:42.92#ibcon#wrote, iclass 13, count 0 2006.257.07:31:42.92#ibcon#about to read 3, iclass 13, count 0 2006.257.07:31:42.96#ibcon#read 3, iclass 13, count 0 2006.257.07:31:42.96#ibcon#about to read 4, iclass 13, count 0 2006.257.07:31:42.96#ibcon#read 4, iclass 13, count 0 2006.257.07:31:42.96#ibcon#about to read 5, iclass 13, count 0 2006.257.07:31:42.96#ibcon#read 5, iclass 13, count 0 2006.257.07:31:42.96#ibcon#about to read 6, iclass 13, count 0 2006.257.07:31:42.96#ibcon#read 6, iclass 13, count 0 2006.257.07:31:42.96#ibcon#end of sib2, iclass 13, count 0 2006.257.07:31:42.96#ibcon#*after write, iclass 13, count 0 2006.257.07:31:42.96#ibcon#*before return 0, iclass 13, count 0 2006.257.07:31:42.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:42.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:42.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:31:42.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:31:42.96$vck44/va=6,4 2006.257.07:31:42.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.07:31:42.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.07:31:42.96#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:42.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:43.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:43.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:43.02#ibcon#enter wrdev, iclass 15, count 2 2006.257.07:31:43.02#ibcon#first serial, iclass 15, count 2 2006.257.07:31:43.02#ibcon#enter sib2, iclass 15, count 2 2006.257.07:31:43.02#ibcon#flushed, iclass 15, count 2 2006.257.07:31:43.02#ibcon#about to write, iclass 15, count 2 2006.257.07:31:43.02#ibcon#wrote, iclass 15, count 2 2006.257.07:31:43.02#ibcon#about to read 3, iclass 15, count 2 2006.257.07:31:43.04#ibcon#read 3, iclass 15, count 2 2006.257.07:31:43.04#ibcon#about to read 4, iclass 15, count 2 2006.257.07:31:43.04#ibcon#read 4, iclass 15, count 2 2006.257.07:31:43.04#ibcon#about to read 5, iclass 15, count 2 2006.257.07:31:43.04#ibcon#read 5, iclass 15, count 2 2006.257.07:31:43.04#ibcon#about to read 6, iclass 15, count 2 2006.257.07:31:43.04#ibcon#read 6, iclass 15, count 2 2006.257.07:31:43.04#ibcon#end of sib2, iclass 15, count 2 2006.257.07:31:43.04#ibcon#*mode == 0, iclass 15, count 2 2006.257.07:31:43.04#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.07:31:43.04#ibcon#[25=AT06-04\r\n] 2006.257.07:31:43.04#ibcon#*before write, iclass 15, count 2 2006.257.07:31:43.04#ibcon#enter sib2, iclass 15, count 2 2006.257.07:31:43.04#ibcon#flushed, iclass 15, count 2 2006.257.07:31:43.04#ibcon#about to write, iclass 15, count 2 2006.257.07:31:43.04#ibcon#wrote, iclass 15, count 2 2006.257.07:31:43.04#ibcon#about to read 3, iclass 15, count 2 2006.257.07:31:43.07#ibcon#read 3, iclass 15, count 2 2006.257.07:31:43.07#ibcon#about to read 4, iclass 15, count 2 2006.257.07:31:43.07#ibcon#read 4, iclass 15, count 2 2006.257.07:31:43.07#ibcon#about to read 5, iclass 15, count 2 2006.257.07:31:43.07#ibcon#read 5, iclass 15, count 2 2006.257.07:31:43.07#ibcon#about to read 6, iclass 15, count 2 2006.257.07:31:43.07#ibcon#read 6, iclass 15, count 2 2006.257.07:31:43.07#ibcon#end of sib2, iclass 15, count 2 2006.257.07:31:43.07#ibcon#*after write, iclass 15, count 2 2006.257.07:31:43.07#ibcon#*before return 0, iclass 15, count 2 2006.257.07:31:43.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:43.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:43.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.07:31:43.07#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:43.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:43.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:43.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:43.19#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:31:43.19#ibcon#first serial, iclass 15, count 0 2006.257.07:31:43.19#ibcon#enter sib2, iclass 15, count 0 2006.257.07:31:43.19#ibcon#flushed, iclass 15, count 0 2006.257.07:31:43.19#ibcon#about to write, iclass 15, count 0 2006.257.07:31:43.19#ibcon#wrote, iclass 15, count 0 2006.257.07:31:43.19#ibcon#about to read 3, iclass 15, count 0 2006.257.07:31:43.21#ibcon#read 3, iclass 15, count 0 2006.257.07:31:43.21#ibcon#about to read 4, iclass 15, count 0 2006.257.07:31:43.21#ibcon#read 4, iclass 15, count 0 2006.257.07:31:43.21#ibcon#about to read 5, iclass 15, count 0 2006.257.07:31:43.21#ibcon#read 5, iclass 15, count 0 2006.257.07:31:43.21#ibcon#about to read 6, iclass 15, count 0 2006.257.07:31:43.21#ibcon#read 6, iclass 15, count 0 2006.257.07:31:43.21#ibcon#end of sib2, iclass 15, count 0 2006.257.07:31:43.21#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:31:43.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:31:43.21#ibcon#[25=USB\r\n] 2006.257.07:31:43.21#ibcon#*before write, iclass 15, count 0 2006.257.07:31:43.21#ibcon#enter sib2, iclass 15, count 0 2006.257.07:31:43.21#ibcon#flushed, iclass 15, count 0 2006.257.07:31:43.21#ibcon#about to write, iclass 15, count 0 2006.257.07:31:43.21#ibcon#wrote, iclass 15, count 0 2006.257.07:31:43.21#ibcon#about to read 3, iclass 15, count 0 2006.257.07:31:43.24#ibcon#read 3, iclass 15, count 0 2006.257.07:31:43.24#ibcon#about to read 4, iclass 15, count 0 2006.257.07:31:43.24#ibcon#read 4, iclass 15, count 0 2006.257.07:31:43.24#ibcon#about to read 5, iclass 15, count 0 2006.257.07:31:43.24#ibcon#read 5, iclass 15, count 0 2006.257.07:31:43.24#ibcon#about to read 6, iclass 15, count 0 2006.257.07:31:43.24#ibcon#read 6, iclass 15, count 0 2006.257.07:31:43.24#ibcon#end of sib2, iclass 15, count 0 2006.257.07:31:43.24#ibcon#*after write, iclass 15, count 0 2006.257.07:31:43.24#ibcon#*before return 0, iclass 15, count 0 2006.257.07:31:43.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:43.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:43.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:31:43.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:31:43.24$vck44/valo=7,864.99 2006.257.07:31:43.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.07:31:43.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.07:31:43.24#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:43.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:31:43.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:31:43.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:31:43.24#ibcon#enter wrdev, iclass 17, count 0 2006.257.07:31:43.24#ibcon#first serial, iclass 17, count 0 2006.257.07:31:43.24#ibcon#enter sib2, iclass 17, count 0 2006.257.07:31:43.24#ibcon#flushed, iclass 17, count 0 2006.257.07:31:43.24#ibcon#about to write, iclass 17, count 0 2006.257.07:31:43.24#ibcon#wrote, iclass 17, count 0 2006.257.07:31:43.24#ibcon#about to read 3, iclass 17, count 0 2006.257.07:31:43.26#ibcon#read 3, iclass 17, count 0 2006.257.07:31:43.26#ibcon#about to read 4, iclass 17, count 0 2006.257.07:31:43.26#ibcon#read 4, iclass 17, count 0 2006.257.07:31:43.26#ibcon#about to read 5, iclass 17, count 0 2006.257.07:31:43.26#ibcon#read 5, iclass 17, count 0 2006.257.07:31:43.26#ibcon#about to read 6, iclass 17, count 0 2006.257.07:31:43.26#ibcon#read 6, iclass 17, count 0 2006.257.07:31:43.26#ibcon#end of sib2, iclass 17, count 0 2006.257.07:31:43.26#ibcon#*mode == 0, iclass 17, count 0 2006.257.07:31:43.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.07:31:43.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.07:31:43.26#ibcon#*before write, iclass 17, count 0 2006.257.07:31:43.26#ibcon#enter sib2, iclass 17, count 0 2006.257.07:31:43.26#ibcon#flushed, iclass 17, count 0 2006.257.07:31:43.26#ibcon#about to write, iclass 17, count 0 2006.257.07:31:43.26#ibcon#wrote, iclass 17, count 0 2006.257.07:31:43.26#ibcon#about to read 3, iclass 17, count 0 2006.257.07:31:43.30#ibcon#read 3, iclass 17, count 0 2006.257.07:31:43.30#ibcon#about to read 4, iclass 17, count 0 2006.257.07:31:43.30#ibcon#read 4, iclass 17, count 0 2006.257.07:31:43.30#ibcon#about to read 5, iclass 17, count 0 2006.257.07:31:43.30#ibcon#read 5, iclass 17, count 0 2006.257.07:31:43.30#ibcon#about to read 6, iclass 17, count 0 2006.257.07:31:43.30#ibcon#read 6, iclass 17, count 0 2006.257.07:31:43.30#ibcon#end of sib2, iclass 17, count 0 2006.257.07:31:43.30#ibcon#*after write, iclass 17, count 0 2006.257.07:31:43.30#ibcon#*before return 0, iclass 17, count 0 2006.257.07:31:43.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:31:43.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:31:43.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.07:31:43.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.07:31:43.30$vck44/va=7,4 2006.257.07:31:43.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.07:31:43.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.07:31:43.30#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:43.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:31:43.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:31:43.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:31:43.36#ibcon#enter wrdev, iclass 19, count 2 2006.257.07:31:43.36#ibcon#first serial, iclass 19, count 2 2006.257.07:31:43.36#ibcon#enter sib2, iclass 19, count 2 2006.257.07:31:43.36#ibcon#flushed, iclass 19, count 2 2006.257.07:31:43.36#ibcon#about to write, iclass 19, count 2 2006.257.07:31:43.36#ibcon#wrote, iclass 19, count 2 2006.257.07:31:43.36#ibcon#about to read 3, iclass 19, count 2 2006.257.07:31:43.38#ibcon#read 3, iclass 19, count 2 2006.257.07:31:43.38#ibcon#about to read 4, iclass 19, count 2 2006.257.07:31:43.38#ibcon#read 4, iclass 19, count 2 2006.257.07:31:43.38#ibcon#about to read 5, iclass 19, count 2 2006.257.07:31:43.38#ibcon#read 5, iclass 19, count 2 2006.257.07:31:43.38#ibcon#about to read 6, iclass 19, count 2 2006.257.07:31:43.38#ibcon#read 6, iclass 19, count 2 2006.257.07:31:43.38#ibcon#end of sib2, iclass 19, count 2 2006.257.07:31:43.38#ibcon#*mode == 0, iclass 19, count 2 2006.257.07:31:43.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.07:31:43.38#ibcon#[25=AT07-04\r\n] 2006.257.07:31:43.38#ibcon#*before write, iclass 19, count 2 2006.257.07:31:43.38#ibcon#enter sib2, iclass 19, count 2 2006.257.07:31:43.38#ibcon#flushed, iclass 19, count 2 2006.257.07:31:43.38#ibcon#about to write, iclass 19, count 2 2006.257.07:31:43.38#ibcon#wrote, iclass 19, count 2 2006.257.07:31:43.38#ibcon#about to read 3, iclass 19, count 2 2006.257.07:31:43.41#ibcon#read 3, iclass 19, count 2 2006.257.07:31:43.41#ibcon#about to read 4, iclass 19, count 2 2006.257.07:31:43.41#ibcon#read 4, iclass 19, count 2 2006.257.07:31:43.41#ibcon#about to read 5, iclass 19, count 2 2006.257.07:31:43.41#ibcon#read 5, iclass 19, count 2 2006.257.07:31:43.41#ibcon#about to read 6, iclass 19, count 2 2006.257.07:31:43.41#ibcon#read 6, iclass 19, count 2 2006.257.07:31:43.41#ibcon#end of sib2, iclass 19, count 2 2006.257.07:31:43.41#ibcon#*after write, iclass 19, count 2 2006.257.07:31:43.41#ibcon#*before return 0, iclass 19, count 2 2006.257.07:31:43.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:31:43.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:31:43.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.07:31:43.41#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:43.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:31:43.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:31:43.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:31:43.53#ibcon#enter wrdev, iclass 19, count 0 2006.257.07:31:43.53#ibcon#first serial, iclass 19, count 0 2006.257.07:31:43.53#ibcon#enter sib2, iclass 19, count 0 2006.257.07:31:43.53#ibcon#flushed, iclass 19, count 0 2006.257.07:31:43.53#ibcon#about to write, iclass 19, count 0 2006.257.07:31:43.53#ibcon#wrote, iclass 19, count 0 2006.257.07:31:43.53#ibcon#about to read 3, iclass 19, count 0 2006.257.07:31:43.55#ibcon#read 3, iclass 19, count 0 2006.257.07:31:43.55#ibcon#about to read 4, iclass 19, count 0 2006.257.07:31:43.55#ibcon#read 4, iclass 19, count 0 2006.257.07:31:43.55#ibcon#about to read 5, iclass 19, count 0 2006.257.07:31:43.55#ibcon#read 5, iclass 19, count 0 2006.257.07:31:43.55#ibcon#about to read 6, iclass 19, count 0 2006.257.07:31:43.55#ibcon#read 6, iclass 19, count 0 2006.257.07:31:43.55#ibcon#end of sib2, iclass 19, count 0 2006.257.07:31:43.55#ibcon#*mode == 0, iclass 19, count 0 2006.257.07:31:43.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.07:31:43.55#ibcon#[25=USB\r\n] 2006.257.07:31:43.55#ibcon#*before write, iclass 19, count 0 2006.257.07:31:43.55#ibcon#enter sib2, iclass 19, count 0 2006.257.07:31:43.55#ibcon#flushed, iclass 19, count 0 2006.257.07:31:43.55#ibcon#about to write, iclass 19, count 0 2006.257.07:31:43.55#ibcon#wrote, iclass 19, count 0 2006.257.07:31:43.55#ibcon#about to read 3, iclass 19, count 0 2006.257.07:31:43.58#ibcon#read 3, iclass 19, count 0 2006.257.07:31:43.58#ibcon#about to read 4, iclass 19, count 0 2006.257.07:31:43.58#ibcon#read 4, iclass 19, count 0 2006.257.07:31:43.58#ibcon#about to read 5, iclass 19, count 0 2006.257.07:31:43.58#ibcon#read 5, iclass 19, count 0 2006.257.07:31:43.58#ibcon#about to read 6, iclass 19, count 0 2006.257.07:31:43.58#ibcon#read 6, iclass 19, count 0 2006.257.07:31:43.58#ibcon#end of sib2, iclass 19, count 0 2006.257.07:31:43.58#ibcon#*after write, iclass 19, count 0 2006.257.07:31:43.58#ibcon#*before return 0, iclass 19, count 0 2006.257.07:31:43.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:31:43.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:31:43.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.07:31:43.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.07:31:43.58$vck44/valo=8,884.99 2006.257.07:31:43.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.07:31:43.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.07:31:43.58#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:43.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:43.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:43.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:43.58#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:31:43.58#ibcon#first serial, iclass 21, count 0 2006.257.07:31:43.58#ibcon#enter sib2, iclass 21, count 0 2006.257.07:31:43.58#ibcon#flushed, iclass 21, count 0 2006.257.07:31:43.58#ibcon#about to write, iclass 21, count 0 2006.257.07:31:43.58#ibcon#wrote, iclass 21, count 0 2006.257.07:31:43.58#ibcon#about to read 3, iclass 21, count 0 2006.257.07:31:43.60#ibcon#read 3, iclass 21, count 0 2006.257.07:31:43.60#ibcon#about to read 4, iclass 21, count 0 2006.257.07:31:43.60#ibcon#read 4, iclass 21, count 0 2006.257.07:31:43.60#ibcon#about to read 5, iclass 21, count 0 2006.257.07:31:43.60#ibcon#read 5, iclass 21, count 0 2006.257.07:31:43.60#ibcon#about to read 6, iclass 21, count 0 2006.257.07:31:43.60#ibcon#read 6, iclass 21, count 0 2006.257.07:31:43.60#ibcon#end of sib2, iclass 21, count 0 2006.257.07:31:43.60#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:31:43.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:31:43.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.07:31:43.60#ibcon#*before write, iclass 21, count 0 2006.257.07:31:43.60#ibcon#enter sib2, iclass 21, count 0 2006.257.07:31:43.60#ibcon#flushed, iclass 21, count 0 2006.257.07:31:43.60#ibcon#about to write, iclass 21, count 0 2006.257.07:31:43.60#ibcon#wrote, iclass 21, count 0 2006.257.07:31:43.60#ibcon#about to read 3, iclass 21, count 0 2006.257.07:31:43.64#ibcon#read 3, iclass 21, count 0 2006.257.07:31:43.64#ibcon#about to read 4, iclass 21, count 0 2006.257.07:31:43.64#ibcon#read 4, iclass 21, count 0 2006.257.07:31:43.64#ibcon#about to read 5, iclass 21, count 0 2006.257.07:31:43.64#ibcon#read 5, iclass 21, count 0 2006.257.07:31:43.64#ibcon#about to read 6, iclass 21, count 0 2006.257.07:31:43.64#ibcon#read 6, iclass 21, count 0 2006.257.07:31:43.64#ibcon#end of sib2, iclass 21, count 0 2006.257.07:31:43.64#ibcon#*after write, iclass 21, count 0 2006.257.07:31:43.64#ibcon#*before return 0, iclass 21, count 0 2006.257.07:31:43.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:43.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:43.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:31:43.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:31:43.64$vck44/va=8,4 2006.257.07:31:43.64#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.07:31:43.64#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.07:31:43.64#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:43.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:43.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:43.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:43.70#ibcon#enter wrdev, iclass 23, count 2 2006.257.07:31:43.70#ibcon#first serial, iclass 23, count 2 2006.257.07:31:43.70#ibcon#enter sib2, iclass 23, count 2 2006.257.07:31:43.70#ibcon#flushed, iclass 23, count 2 2006.257.07:31:43.70#ibcon#about to write, iclass 23, count 2 2006.257.07:31:43.70#ibcon#wrote, iclass 23, count 2 2006.257.07:31:43.70#ibcon#about to read 3, iclass 23, count 2 2006.257.07:31:43.72#ibcon#read 3, iclass 23, count 2 2006.257.07:31:43.72#ibcon#about to read 4, iclass 23, count 2 2006.257.07:31:43.72#ibcon#read 4, iclass 23, count 2 2006.257.07:31:43.72#ibcon#about to read 5, iclass 23, count 2 2006.257.07:31:43.72#ibcon#read 5, iclass 23, count 2 2006.257.07:31:43.72#ibcon#about to read 6, iclass 23, count 2 2006.257.07:31:43.72#ibcon#read 6, iclass 23, count 2 2006.257.07:31:43.72#ibcon#end of sib2, iclass 23, count 2 2006.257.07:31:43.72#ibcon#*mode == 0, iclass 23, count 2 2006.257.07:31:43.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.07:31:43.72#ibcon#[25=AT08-04\r\n] 2006.257.07:31:43.72#ibcon#*before write, iclass 23, count 2 2006.257.07:31:43.72#ibcon#enter sib2, iclass 23, count 2 2006.257.07:31:43.72#ibcon#flushed, iclass 23, count 2 2006.257.07:31:43.72#ibcon#about to write, iclass 23, count 2 2006.257.07:31:43.72#ibcon#wrote, iclass 23, count 2 2006.257.07:31:43.72#ibcon#about to read 3, iclass 23, count 2 2006.257.07:31:43.75#ibcon#read 3, iclass 23, count 2 2006.257.07:31:43.75#ibcon#about to read 4, iclass 23, count 2 2006.257.07:31:43.75#ibcon#read 4, iclass 23, count 2 2006.257.07:31:43.75#ibcon#about to read 5, iclass 23, count 2 2006.257.07:31:43.75#ibcon#read 5, iclass 23, count 2 2006.257.07:31:43.75#ibcon#about to read 6, iclass 23, count 2 2006.257.07:31:43.75#ibcon#read 6, iclass 23, count 2 2006.257.07:31:43.75#ibcon#end of sib2, iclass 23, count 2 2006.257.07:31:43.75#ibcon#*after write, iclass 23, count 2 2006.257.07:31:43.75#ibcon#*before return 0, iclass 23, count 2 2006.257.07:31:43.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:43.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:43.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.07:31:43.75#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:43.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:43.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:43.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:43.87#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:31:43.87#ibcon#first serial, iclass 23, count 0 2006.257.07:31:43.87#ibcon#enter sib2, iclass 23, count 0 2006.257.07:31:43.87#ibcon#flushed, iclass 23, count 0 2006.257.07:31:43.87#ibcon#about to write, iclass 23, count 0 2006.257.07:31:43.87#ibcon#wrote, iclass 23, count 0 2006.257.07:31:43.87#ibcon#about to read 3, iclass 23, count 0 2006.257.07:31:43.89#ibcon#read 3, iclass 23, count 0 2006.257.07:31:43.89#ibcon#about to read 4, iclass 23, count 0 2006.257.07:31:43.89#ibcon#read 4, iclass 23, count 0 2006.257.07:31:43.89#ibcon#about to read 5, iclass 23, count 0 2006.257.07:31:43.89#ibcon#read 5, iclass 23, count 0 2006.257.07:31:43.89#ibcon#about to read 6, iclass 23, count 0 2006.257.07:31:43.89#ibcon#read 6, iclass 23, count 0 2006.257.07:31:43.89#ibcon#end of sib2, iclass 23, count 0 2006.257.07:31:43.89#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:31:43.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:31:43.89#ibcon#[25=USB\r\n] 2006.257.07:31:43.89#ibcon#*before write, iclass 23, count 0 2006.257.07:31:43.89#ibcon#enter sib2, iclass 23, count 0 2006.257.07:31:43.89#ibcon#flushed, iclass 23, count 0 2006.257.07:31:43.89#ibcon#about to write, iclass 23, count 0 2006.257.07:31:43.89#ibcon#wrote, iclass 23, count 0 2006.257.07:31:43.89#ibcon#about to read 3, iclass 23, count 0 2006.257.07:31:43.92#ibcon#read 3, iclass 23, count 0 2006.257.07:31:43.92#ibcon#about to read 4, iclass 23, count 0 2006.257.07:31:43.92#ibcon#read 4, iclass 23, count 0 2006.257.07:31:43.92#ibcon#about to read 5, iclass 23, count 0 2006.257.07:31:43.92#ibcon#read 5, iclass 23, count 0 2006.257.07:31:43.92#ibcon#about to read 6, iclass 23, count 0 2006.257.07:31:43.92#ibcon#read 6, iclass 23, count 0 2006.257.07:31:43.92#ibcon#end of sib2, iclass 23, count 0 2006.257.07:31:43.92#ibcon#*after write, iclass 23, count 0 2006.257.07:31:43.92#ibcon#*before return 0, iclass 23, count 0 2006.257.07:31:43.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:43.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:43.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:31:43.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:31:43.92$vck44/vblo=1,629.99 2006.257.07:31:43.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.07:31:43.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.07:31:43.92#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:43.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:43.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:43.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:43.92#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:31:43.92#ibcon#first serial, iclass 25, count 0 2006.257.07:31:43.92#ibcon#enter sib2, iclass 25, count 0 2006.257.07:31:43.92#ibcon#flushed, iclass 25, count 0 2006.257.07:31:43.92#ibcon#about to write, iclass 25, count 0 2006.257.07:31:43.92#ibcon#wrote, iclass 25, count 0 2006.257.07:31:43.92#ibcon#about to read 3, iclass 25, count 0 2006.257.07:31:43.94#ibcon#read 3, iclass 25, count 0 2006.257.07:31:43.94#ibcon#about to read 4, iclass 25, count 0 2006.257.07:31:43.94#ibcon#read 4, iclass 25, count 0 2006.257.07:31:43.94#ibcon#about to read 5, iclass 25, count 0 2006.257.07:31:43.94#ibcon#read 5, iclass 25, count 0 2006.257.07:31:43.94#ibcon#about to read 6, iclass 25, count 0 2006.257.07:31:43.94#ibcon#read 6, iclass 25, count 0 2006.257.07:31:43.94#ibcon#end of sib2, iclass 25, count 0 2006.257.07:31:43.94#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:31:43.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:31:43.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.07:31:43.94#ibcon#*before write, iclass 25, count 0 2006.257.07:31:43.94#ibcon#enter sib2, iclass 25, count 0 2006.257.07:31:43.94#ibcon#flushed, iclass 25, count 0 2006.257.07:31:43.94#ibcon#about to write, iclass 25, count 0 2006.257.07:31:43.94#ibcon#wrote, iclass 25, count 0 2006.257.07:31:43.94#ibcon#about to read 3, iclass 25, count 0 2006.257.07:31:43.98#ibcon#read 3, iclass 25, count 0 2006.257.07:31:43.98#ibcon#about to read 4, iclass 25, count 0 2006.257.07:31:43.98#ibcon#read 4, iclass 25, count 0 2006.257.07:31:43.98#ibcon#about to read 5, iclass 25, count 0 2006.257.07:31:43.98#ibcon#read 5, iclass 25, count 0 2006.257.07:31:43.98#ibcon#about to read 6, iclass 25, count 0 2006.257.07:31:43.98#ibcon#read 6, iclass 25, count 0 2006.257.07:31:43.98#ibcon#end of sib2, iclass 25, count 0 2006.257.07:31:43.98#ibcon#*after write, iclass 25, count 0 2006.257.07:31:43.98#ibcon#*before return 0, iclass 25, count 0 2006.257.07:31:43.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:43.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:43.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:31:43.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:31:43.98$vck44/vb=1,4 2006.257.07:31:43.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.07:31:43.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.07:31:43.98#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:43.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:31:43.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:31:43.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:31:43.98#ibcon#enter wrdev, iclass 27, count 2 2006.257.07:31:43.98#ibcon#first serial, iclass 27, count 2 2006.257.07:31:43.98#ibcon#enter sib2, iclass 27, count 2 2006.257.07:31:43.98#ibcon#flushed, iclass 27, count 2 2006.257.07:31:43.98#ibcon#about to write, iclass 27, count 2 2006.257.07:31:43.98#ibcon#wrote, iclass 27, count 2 2006.257.07:31:43.98#ibcon#about to read 3, iclass 27, count 2 2006.257.07:31:44.00#ibcon#read 3, iclass 27, count 2 2006.257.07:31:44.00#ibcon#about to read 4, iclass 27, count 2 2006.257.07:31:44.00#ibcon#read 4, iclass 27, count 2 2006.257.07:31:44.00#ibcon#about to read 5, iclass 27, count 2 2006.257.07:31:44.00#ibcon#read 5, iclass 27, count 2 2006.257.07:31:44.00#ibcon#about to read 6, iclass 27, count 2 2006.257.07:31:44.00#ibcon#read 6, iclass 27, count 2 2006.257.07:31:44.00#ibcon#end of sib2, iclass 27, count 2 2006.257.07:31:44.00#ibcon#*mode == 0, iclass 27, count 2 2006.257.07:31:44.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.07:31:44.00#ibcon#[27=AT01-04\r\n] 2006.257.07:31:44.00#ibcon#*before write, iclass 27, count 2 2006.257.07:31:44.00#ibcon#enter sib2, iclass 27, count 2 2006.257.07:31:44.00#ibcon#flushed, iclass 27, count 2 2006.257.07:31:44.00#ibcon#about to write, iclass 27, count 2 2006.257.07:31:44.00#ibcon#wrote, iclass 27, count 2 2006.257.07:31:44.00#ibcon#about to read 3, iclass 27, count 2 2006.257.07:31:44.03#ibcon#read 3, iclass 27, count 2 2006.257.07:31:44.03#ibcon#about to read 4, iclass 27, count 2 2006.257.07:31:44.03#ibcon#read 4, iclass 27, count 2 2006.257.07:31:44.03#ibcon#about to read 5, iclass 27, count 2 2006.257.07:31:44.03#ibcon#read 5, iclass 27, count 2 2006.257.07:31:44.03#ibcon#about to read 6, iclass 27, count 2 2006.257.07:31:44.03#ibcon#read 6, iclass 27, count 2 2006.257.07:31:44.03#ibcon#end of sib2, iclass 27, count 2 2006.257.07:31:44.03#ibcon#*after write, iclass 27, count 2 2006.257.07:31:44.03#ibcon#*before return 0, iclass 27, count 2 2006.257.07:31:44.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:31:44.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:31:44.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.07:31:44.03#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:44.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:31:44.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:31:44.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:31:44.15#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:31:44.15#ibcon#first serial, iclass 27, count 0 2006.257.07:31:44.15#ibcon#enter sib2, iclass 27, count 0 2006.257.07:31:44.15#ibcon#flushed, iclass 27, count 0 2006.257.07:31:44.15#ibcon#about to write, iclass 27, count 0 2006.257.07:31:44.15#ibcon#wrote, iclass 27, count 0 2006.257.07:31:44.15#ibcon#about to read 3, iclass 27, count 0 2006.257.07:31:44.17#ibcon#read 3, iclass 27, count 0 2006.257.07:31:44.17#ibcon#about to read 4, iclass 27, count 0 2006.257.07:31:44.17#ibcon#read 4, iclass 27, count 0 2006.257.07:31:44.17#ibcon#about to read 5, iclass 27, count 0 2006.257.07:31:44.17#ibcon#read 5, iclass 27, count 0 2006.257.07:31:44.17#ibcon#about to read 6, iclass 27, count 0 2006.257.07:31:44.17#ibcon#read 6, iclass 27, count 0 2006.257.07:31:44.17#ibcon#end of sib2, iclass 27, count 0 2006.257.07:31:44.17#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:31:44.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:31:44.17#ibcon#[27=USB\r\n] 2006.257.07:31:44.17#ibcon#*before write, iclass 27, count 0 2006.257.07:31:44.17#ibcon#enter sib2, iclass 27, count 0 2006.257.07:31:44.17#ibcon#flushed, iclass 27, count 0 2006.257.07:31:44.17#ibcon#about to write, iclass 27, count 0 2006.257.07:31:44.17#ibcon#wrote, iclass 27, count 0 2006.257.07:31:44.17#ibcon#about to read 3, iclass 27, count 0 2006.257.07:31:44.20#ibcon#read 3, iclass 27, count 0 2006.257.07:31:44.20#ibcon#about to read 4, iclass 27, count 0 2006.257.07:31:44.20#ibcon#read 4, iclass 27, count 0 2006.257.07:31:44.20#ibcon#about to read 5, iclass 27, count 0 2006.257.07:31:44.20#ibcon#read 5, iclass 27, count 0 2006.257.07:31:44.20#ibcon#about to read 6, iclass 27, count 0 2006.257.07:31:44.20#ibcon#read 6, iclass 27, count 0 2006.257.07:31:44.20#ibcon#end of sib2, iclass 27, count 0 2006.257.07:31:44.20#ibcon#*after write, iclass 27, count 0 2006.257.07:31:44.20#ibcon#*before return 0, iclass 27, count 0 2006.257.07:31:44.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:31:44.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:31:44.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:31:44.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:31:44.20$vck44/vblo=2,634.99 2006.257.07:31:44.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.07:31:44.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.07:31:44.20#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:44.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:44.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:44.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:44.20#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:31:44.20#ibcon#first serial, iclass 29, count 0 2006.257.07:31:44.20#ibcon#enter sib2, iclass 29, count 0 2006.257.07:31:44.20#ibcon#flushed, iclass 29, count 0 2006.257.07:31:44.20#ibcon#about to write, iclass 29, count 0 2006.257.07:31:44.20#ibcon#wrote, iclass 29, count 0 2006.257.07:31:44.20#ibcon#about to read 3, iclass 29, count 0 2006.257.07:31:44.22#ibcon#read 3, iclass 29, count 0 2006.257.07:31:44.22#ibcon#about to read 4, iclass 29, count 0 2006.257.07:31:44.22#ibcon#read 4, iclass 29, count 0 2006.257.07:31:44.22#ibcon#about to read 5, iclass 29, count 0 2006.257.07:31:44.22#ibcon#read 5, iclass 29, count 0 2006.257.07:31:44.22#ibcon#about to read 6, iclass 29, count 0 2006.257.07:31:44.22#ibcon#read 6, iclass 29, count 0 2006.257.07:31:44.22#ibcon#end of sib2, iclass 29, count 0 2006.257.07:31:44.22#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:31:44.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:31:44.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.07:31:44.22#ibcon#*before write, iclass 29, count 0 2006.257.07:31:44.22#ibcon#enter sib2, iclass 29, count 0 2006.257.07:31:44.22#ibcon#flushed, iclass 29, count 0 2006.257.07:31:44.22#ibcon#about to write, iclass 29, count 0 2006.257.07:31:44.22#ibcon#wrote, iclass 29, count 0 2006.257.07:31:44.22#ibcon#about to read 3, iclass 29, count 0 2006.257.07:31:44.26#ibcon#read 3, iclass 29, count 0 2006.257.07:31:44.26#ibcon#about to read 4, iclass 29, count 0 2006.257.07:31:44.26#ibcon#read 4, iclass 29, count 0 2006.257.07:31:44.26#ibcon#about to read 5, iclass 29, count 0 2006.257.07:31:44.26#ibcon#read 5, iclass 29, count 0 2006.257.07:31:44.26#ibcon#about to read 6, iclass 29, count 0 2006.257.07:31:44.26#ibcon#read 6, iclass 29, count 0 2006.257.07:31:44.26#ibcon#end of sib2, iclass 29, count 0 2006.257.07:31:44.26#ibcon#*after write, iclass 29, count 0 2006.257.07:31:44.26#ibcon#*before return 0, iclass 29, count 0 2006.257.07:31:44.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:44.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:31:44.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:31:44.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:31:44.26$vck44/vb=2,5 2006.257.07:31:44.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.07:31:44.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.07:31:44.26#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:44.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:44.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:44.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:44.32#ibcon#enter wrdev, iclass 31, count 2 2006.257.07:31:44.32#ibcon#first serial, iclass 31, count 2 2006.257.07:31:44.32#ibcon#enter sib2, iclass 31, count 2 2006.257.07:31:44.32#ibcon#flushed, iclass 31, count 2 2006.257.07:31:44.32#ibcon#about to write, iclass 31, count 2 2006.257.07:31:44.32#ibcon#wrote, iclass 31, count 2 2006.257.07:31:44.32#ibcon#about to read 3, iclass 31, count 2 2006.257.07:31:44.34#ibcon#read 3, iclass 31, count 2 2006.257.07:31:44.34#ibcon#about to read 4, iclass 31, count 2 2006.257.07:31:44.34#ibcon#read 4, iclass 31, count 2 2006.257.07:31:44.34#ibcon#about to read 5, iclass 31, count 2 2006.257.07:31:44.34#ibcon#read 5, iclass 31, count 2 2006.257.07:31:44.34#ibcon#about to read 6, iclass 31, count 2 2006.257.07:31:44.34#ibcon#read 6, iclass 31, count 2 2006.257.07:31:44.34#ibcon#end of sib2, iclass 31, count 2 2006.257.07:31:44.34#ibcon#*mode == 0, iclass 31, count 2 2006.257.07:31:44.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.07:31:44.34#ibcon#[27=AT02-05\r\n] 2006.257.07:31:44.34#ibcon#*before write, iclass 31, count 2 2006.257.07:31:44.34#ibcon#enter sib2, iclass 31, count 2 2006.257.07:31:44.34#ibcon#flushed, iclass 31, count 2 2006.257.07:31:44.34#ibcon#about to write, iclass 31, count 2 2006.257.07:31:44.34#ibcon#wrote, iclass 31, count 2 2006.257.07:31:44.34#ibcon#about to read 3, iclass 31, count 2 2006.257.07:31:44.37#ibcon#read 3, iclass 31, count 2 2006.257.07:31:44.37#ibcon#about to read 4, iclass 31, count 2 2006.257.07:31:44.37#ibcon#read 4, iclass 31, count 2 2006.257.07:31:44.37#ibcon#about to read 5, iclass 31, count 2 2006.257.07:31:44.37#ibcon#read 5, iclass 31, count 2 2006.257.07:31:44.37#ibcon#about to read 6, iclass 31, count 2 2006.257.07:31:44.37#ibcon#read 6, iclass 31, count 2 2006.257.07:31:44.37#ibcon#end of sib2, iclass 31, count 2 2006.257.07:31:44.37#ibcon#*after write, iclass 31, count 2 2006.257.07:31:44.37#ibcon#*before return 0, iclass 31, count 2 2006.257.07:31:44.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:44.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:31:44.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.07:31:44.37#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:44.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:44.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:44.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:44.49#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:31:44.49#ibcon#first serial, iclass 31, count 0 2006.257.07:31:44.49#ibcon#enter sib2, iclass 31, count 0 2006.257.07:31:44.49#ibcon#flushed, iclass 31, count 0 2006.257.07:31:44.49#ibcon#about to write, iclass 31, count 0 2006.257.07:31:44.49#ibcon#wrote, iclass 31, count 0 2006.257.07:31:44.49#ibcon#about to read 3, iclass 31, count 0 2006.257.07:31:44.51#ibcon#read 3, iclass 31, count 0 2006.257.07:31:44.51#ibcon#about to read 4, iclass 31, count 0 2006.257.07:31:44.51#ibcon#read 4, iclass 31, count 0 2006.257.07:31:44.51#ibcon#about to read 5, iclass 31, count 0 2006.257.07:31:44.51#ibcon#read 5, iclass 31, count 0 2006.257.07:31:44.51#ibcon#about to read 6, iclass 31, count 0 2006.257.07:31:44.51#ibcon#read 6, iclass 31, count 0 2006.257.07:31:44.51#ibcon#end of sib2, iclass 31, count 0 2006.257.07:31:44.51#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:31:44.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:31:44.51#ibcon#[27=USB\r\n] 2006.257.07:31:44.51#ibcon#*before write, iclass 31, count 0 2006.257.07:31:44.51#ibcon#enter sib2, iclass 31, count 0 2006.257.07:31:44.51#ibcon#flushed, iclass 31, count 0 2006.257.07:31:44.51#ibcon#about to write, iclass 31, count 0 2006.257.07:31:44.51#ibcon#wrote, iclass 31, count 0 2006.257.07:31:44.51#ibcon#about to read 3, iclass 31, count 0 2006.257.07:31:44.54#ibcon#read 3, iclass 31, count 0 2006.257.07:31:44.54#ibcon#about to read 4, iclass 31, count 0 2006.257.07:31:44.54#ibcon#read 4, iclass 31, count 0 2006.257.07:31:44.54#ibcon#about to read 5, iclass 31, count 0 2006.257.07:31:44.54#ibcon#read 5, iclass 31, count 0 2006.257.07:31:44.54#ibcon#about to read 6, iclass 31, count 0 2006.257.07:31:44.54#ibcon#read 6, iclass 31, count 0 2006.257.07:31:44.54#ibcon#end of sib2, iclass 31, count 0 2006.257.07:31:44.54#ibcon#*after write, iclass 31, count 0 2006.257.07:31:44.54#ibcon#*before return 0, iclass 31, count 0 2006.257.07:31:44.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:44.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:31:44.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:31:44.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:31:44.54$vck44/vblo=3,649.99 2006.257.07:31:44.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.07:31:44.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.07:31:44.54#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:44.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:44.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:44.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:44.54#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:31:44.54#ibcon#first serial, iclass 33, count 0 2006.257.07:31:44.54#ibcon#enter sib2, iclass 33, count 0 2006.257.07:31:44.54#ibcon#flushed, iclass 33, count 0 2006.257.07:31:44.54#ibcon#about to write, iclass 33, count 0 2006.257.07:31:44.54#ibcon#wrote, iclass 33, count 0 2006.257.07:31:44.54#ibcon#about to read 3, iclass 33, count 0 2006.257.07:31:44.56#ibcon#read 3, iclass 33, count 0 2006.257.07:31:44.56#ibcon#about to read 4, iclass 33, count 0 2006.257.07:31:44.56#ibcon#read 4, iclass 33, count 0 2006.257.07:31:44.56#ibcon#about to read 5, iclass 33, count 0 2006.257.07:31:44.56#ibcon#read 5, iclass 33, count 0 2006.257.07:31:44.56#ibcon#about to read 6, iclass 33, count 0 2006.257.07:31:44.56#ibcon#read 6, iclass 33, count 0 2006.257.07:31:44.56#ibcon#end of sib2, iclass 33, count 0 2006.257.07:31:44.56#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:31:44.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:31:44.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.07:31:44.56#ibcon#*before write, iclass 33, count 0 2006.257.07:31:44.56#ibcon#enter sib2, iclass 33, count 0 2006.257.07:31:44.56#ibcon#flushed, iclass 33, count 0 2006.257.07:31:44.56#ibcon#about to write, iclass 33, count 0 2006.257.07:31:44.56#ibcon#wrote, iclass 33, count 0 2006.257.07:31:44.56#ibcon#about to read 3, iclass 33, count 0 2006.257.07:31:44.60#ibcon#read 3, iclass 33, count 0 2006.257.07:31:44.60#ibcon#about to read 4, iclass 33, count 0 2006.257.07:31:44.60#ibcon#read 4, iclass 33, count 0 2006.257.07:31:44.60#ibcon#about to read 5, iclass 33, count 0 2006.257.07:31:44.60#ibcon#read 5, iclass 33, count 0 2006.257.07:31:44.60#ibcon#about to read 6, iclass 33, count 0 2006.257.07:31:44.60#ibcon#read 6, iclass 33, count 0 2006.257.07:31:44.60#ibcon#end of sib2, iclass 33, count 0 2006.257.07:31:44.60#ibcon#*after write, iclass 33, count 0 2006.257.07:31:44.60#ibcon#*before return 0, iclass 33, count 0 2006.257.07:31:44.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:44.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:31:44.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:31:44.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:31:44.60$vck44/vb=3,4 2006.257.07:31:44.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.07:31:44.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.07:31:44.60#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:44.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:44.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:44.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:44.66#ibcon#enter wrdev, iclass 35, count 2 2006.257.07:31:44.66#ibcon#first serial, iclass 35, count 2 2006.257.07:31:44.66#ibcon#enter sib2, iclass 35, count 2 2006.257.07:31:44.66#ibcon#flushed, iclass 35, count 2 2006.257.07:31:44.66#ibcon#about to write, iclass 35, count 2 2006.257.07:31:44.66#ibcon#wrote, iclass 35, count 2 2006.257.07:31:44.66#ibcon#about to read 3, iclass 35, count 2 2006.257.07:31:44.68#ibcon#read 3, iclass 35, count 2 2006.257.07:31:44.68#ibcon#about to read 4, iclass 35, count 2 2006.257.07:31:44.68#ibcon#read 4, iclass 35, count 2 2006.257.07:31:44.68#ibcon#about to read 5, iclass 35, count 2 2006.257.07:31:44.68#ibcon#read 5, iclass 35, count 2 2006.257.07:31:44.68#ibcon#about to read 6, iclass 35, count 2 2006.257.07:31:44.68#ibcon#read 6, iclass 35, count 2 2006.257.07:31:44.68#ibcon#end of sib2, iclass 35, count 2 2006.257.07:31:44.68#ibcon#*mode == 0, iclass 35, count 2 2006.257.07:31:44.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.07:31:44.68#ibcon#[27=AT03-04\r\n] 2006.257.07:31:44.68#ibcon#*before write, iclass 35, count 2 2006.257.07:31:44.68#ibcon#enter sib2, iclass 35, count 2 2006.257.07:31:44.68#ibcon#flushed, iclass 35, count 2 2006.257.07:31:44.68#ibcon#about to write, iclass 35, count 2 2006.257.07:31:44.68#ibcon#wrote, iclass 35, count 2 2006.257.07:31:44.68#ibcon#about to read 3, iclass 35, count 2 2006.257.07:31:44.71#ibcon#read 3, iclass 35, count 2 2006.257.07:31:44.71#ibcon#about to read 4, iclass 35, count 2 2006.257.07:31:44.71#ibcon#read 4, iclass 35, count 2 2006.257.07:31:44.71#ibcon#about to read 5, iclass 35, count 2 2006.257.07:31:44.71#ibcon#read 5, iclass 35, count 2 2006.257.07:31:44.71#ibcon#about to read 6, iclass 35, count 2 2006.257.07:31:44.71#ibcon#read 6, iclass 35, count 2 2006.257.07:31:44.71#ibcon#end of sib2, iclass 35, count 2 2006.257.07:31:44.71#ibcon#*after write, iclass 35, count 2 2006.257.07:31:44.71#ibcon#*before return 0, iclass 35, count 2 2006.257.07:31:44.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:44.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:31:44.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.07:31:44.71#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:44.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:44.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:44.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:44.83#ibcon#enter wrdev, iclass 35, count 0 2006.257.07:31:44.83#ibcon#first serial, iclass 35, count 0 2006.257.07:31:44.83#ibcon#enter sib2, iclass 35, count 0 2006.257.07:31:44.83#ibcon#flushed, iclass 35, count 0 2006.257.07:31:44.83#ibcon#about to write, iclass 35, count 0 2006.257.07:31:44.83#ibcon#wrote, iclass 35, count 0 2006.257.07:31:44.83#ibcon#about to read 3, iclass 35, count 0 2006.257.07:31:44.85#ibcon#read 3, iclass 35, count 0 2006.257.07:31:44.85#ibcon#about to read 4, iclass 35, count 0 2006.257.07:31:44.85#ibcon#read 4, iclass 35, count 0 2006.257.07:31:44.85#ibcon#about to read 5, iclass 35, count 0 2006.257.07:31:44.85#ibcon#read 5, iclass 35, count 0 2006.257.07:31:44.85#ibcon#about to read 6, iclass 35, count 0 2006.257.07:31:44.85#ibcon#read 6, iclass 35, count 0 2006.257.07:31:44.85#ibcon#end of sib2, iclass 35, count 0 2006.257.07:31:44.85#ibcon#*mode == 0, iclass 35, count 0 2006.257.07:31:44.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.07:31:44.85#ibcon#[27=USB\r\n] 2006.257.07:31:44.85#ibcon#*before write, iclass 35, count 0 2006.257.07:31:44.85#ibcon#enter sib2, iclass 35, count 0 2006.257.07:31:44.85#ibcon#flushed, iclass 35, count 0 2006.257.07:31:44.85#ibcon#about to write, iclass 35, count 0 2006.257.07:31:44.85#ibcon#wrote, iclass 35, count 0 2006.257.07:31:44.85#ibcon#about to read 3, iclass 35, count 0 2006.257.07:31:44.88#ibcon#read 3, iclass 35, count 0 2006.257.07:31:44.88#ibcon#about to read 4, iclass 35, count 0 2006.257.07:31:44.88#ibcon#read 4, iclass 35, count 0 2006.257.07:31:44.88#ibcon#about to read 5, iclass 35, count 0 2006.257.07:31:44.88#ibcon#read 5, iclass 35, count 0 2006.257.07:31:44.88#ibcon#about to read 6, iclass 35, count 0 2006.257.07:31:44.88#ibcon#read 6, iclass 35, count 0 2006.257.07:31:44.88#ibcon#end of sib2, iclass 35, count 0 2006.257.07:31:44.88#ibcon#*after write, iclass 35, count 0 2006.257.07:31:44.88#ibcon#*before return 0, iclass 35, count 0 2006.257.07:31:44.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:44.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:31:44.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.07:31:44.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.07:31:44.88$vck44/vblo=4,679.99 2006.257.07:31:44.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.07:31:44.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.07:31:44.88#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:44.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:44.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:44.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:44.88#ibcon#enter wrdev, iclass 37, count 0 2006.257.07:31:44.88#ibcon#first serial, iclass 37, count 0 2006.257.07:31:44.88#ibcon#enter sib2, iclass 37, count 0 2006.257.07:31:44.88#ibcon#flushed, iclass 37, count 0 2006.257.07:31:44.88#ibcon#about to write, iclass 37, count 0 2006.257.07:31:44.88#ibcon#wrote, iclass 37, count 0 2006.257.07:31:44.88#ibcon#about to read 3, iclass 37, count 0 2006.257.07:31:44.90#ibcon#read 3, iclass 37, count 0 2006.257.07:31:44.90#ibcon#about to read 4, iclass 37, count 0 2006.257.07:31:44.90#ibcon#read 4, iclass 37, count 0 2006.257.07:31:44.90#ibcon#about to read 5, iclass 37, count 0 2006.257.07:31:44.90#ibcon#read 5, iclass 37, count 0 2006.257.07:31:44.90#ibcon#about to read 6, iclass 37, count 0 2006.257.07:31:44.90#ibcon#read 6, iclass 37, count 0 2006.257.07:31:44.90#ibcon#end of sib2, iclass 37, count 0 2006.257.07:31:44.90#ibcon#*mode == 0, iclass 37, count 0 2006.257.07:31:44.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.07:31:44.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.07:31:44.90#ibcon#*before write, iclass 37, count 0 2006.257.07:31:44.90#ibcon#enter sib2, iclass 37, count 0 2006.257.07:31:44.90#ibcon#flushed, iclass 37, count 0 2006.257.07:31:44.90#ibcon#about to write, iclass 37, count 0 2006.257.07:31:44.90#ibcon#wrote, iclass 37, count 0 2006.257.07:31:44.90#ibcon#about to read 3, iclass 37, count 0 2006.257.07:31:44.94#ibcon#read 3, iclass 37, count 0 2006.257.07:31:44.94#ibcon#about to read 4, iclass 37, count 0 2006.257.07:31:44.94#ibcon#read 4, iclass 37, count 0 2006.257.07:31:44.94#ibcon#about to read 5, iclass 37, count 0 2006.257.07:31:44.94#ibcon#read 5, iclass 37, count 0 2006.257.07:31:44.94#ibcon#about to read 6, iclass 37, count 0 2006.257.07:31:44.94#ibcon#read 6, iclass 37, count 0 2006.257.07:31:44.94#ibcon#end of sib2, iclass 37, count 0 2006.257.07:31:44.94#ibcon#*after write, iclass 37, count 0 2006.257.07:31:44.94#ibcon#*before return 0, iclass 37, count 0 2006.257.07:31:44.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:44.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:31:44.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.07:31:44.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.07:31:44.94$vck44/vb=4,5 2006.257.07:31:44.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.07:31:44.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.07:31:44.94#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:44.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:45.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:45.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:45.00#ibcon#enter wrdev, iclass 39, count 2 2006.257.07:31:45.00#ibcon#first serial, iclass 39, count 2 2006.257.07:31:45.00#ibcon#enter sib2, iclass 39, count 2 2006.257.07:31:45.00#ibcon#flushed, iclass 39, count 2 2006.257.07:31:45.00#ibcon#about to write, iclass 39, count 2 2006.257.07:31:45.00#ibcon#wrote, iclass 39, count 2 2006.257.07:31:45.00#ibcon#about to read 3, iclass 39, count 2 2006.257.07:31:45.02#ibcon#read 3, iclass 39, count 2 2006.257.07:31:45.02#ibcon#about to read 4, iclass 39, count 2 2006.257.07:31:45.02#ibcon#read 4, iclass 39, count 2 2006.257.07:31:45.02#ibcon#about to read 5, iclass 39, count 2 2006.257.07:31:45.02#ibcon#read 5, iclass 39, count 2 2006.257.07:31:45.02#ibcon#about to read 6, iclass 39, count 2 2006.257.07:31:45.02#ibcon#read 6, iclass 39, count 2 2006.257.07:31:45.02#ibcon#end of sib2, iclass 39, count 2 2006.257.07:31:45.02#ibcon#*mode == 0, iclass 39, count 2 2006.257.07:31:45.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.07:31:45.02#ibcon#[27=AT04-05\r\n] 2006.257.07:31:45.02#ibcon#*before write, iclass 39, count 2 2006.257.07:31:45.02#ibcon#enter sib2, iclass 39, count 2 2006.257.07:31:45.02#ibcon#flushed, iclass 39, count 2 2006.257.07:31:45.02#ibcon#about to write, iclass 39, count 2 2006.257.07:31:45.02#ibcon#wrote, iclass 39, count 2 2006.257.07:31:45.02#ibcon#about to read 3, iclass 39, count 2 2006.257.07:31:45.05#ibcon#read 3, iclass 39, count 2 2006.257.07:31:45.05#ibcon#about to read 4, iclass 39, count 2 2006.257.07:31:45.05#ibcon#read 4, iclass 39, count 2 2006.257.07:31:45.05#ibcon#about to read 5, iclass 39, count 2 2006.257.07:31:45.05#ibcon#read 5, iclass 39, count 2 2006.257.07:31:45.05#ibcon#about to read 6, iclass 39, count 2 2006.257.07:31:45.05#ibcon#read 6, iclass 39, count 2 2006.257.07:31:45.05#ibcon#end of sib2, iclass 39, count 2 2006.257.07:31:45.05#ibcon#*after write, iclass 39, count 2 2006.257.07:31:45.05#ibcon#*before return 0, iclass 39, count 2 2006.257.07:31:45.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:45.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:31:45.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.07:31:45.05#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:45.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:45.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:45.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:45.17#ibcon#enter wrdev, iclass 39, count 0 2006.257.07:31:45.17#ibcon#first serial, iclass 39, count 0 2006.257.07:31:45.17#ibcon#enter sib2, iclass 39, count 0 2006.257.07:31:45.17#ibcon#flushed, iclass 39, count 0 2006.257.07:31:45.17#ibcon#about to write, iclass 39, count 0 2006.257.07:31:45.17#ibcon#wrote, iclass 39, count 0 2006.257.07:31:45.17#ibcon#about to read 3, iclass 39, count 0 2006.257.07:31:45.19#ibcon#read 3, iclass 39, count 0 2006.257.07:31:45.19#ibcon#about to read 4, iclass 39, count 0 2006.257.07:31:45.19#ibcon#read 4, iclass 39, count 0 2006.257.07:31:45.19#ibcon#about to read 5, iclass 39, count 0 2006.257.07:31:45.19#ibcon#read 5, iclass 39, count 0 2006.257.07:31:45.19#ibcon#about to read 6, iclass 39, count 0 2006.257.07:31:45.19#ibcon#read 6, iclass 39, count 0 2006.257.07:31:45.19#ibcon#end of sib2, iclass 39, count 0 2006.257.07:31:45.19#ibcon#*mode == 0, iclass 39, count 0 2006.257.07:31:45.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.07:31:45.19#ibcon#[27=USB\r\n] 2006.257.07:31:45.19#ibcon#*before write, iclass 39, count 0 2006.257.07:31:45.19#ibcon#enter sib2, iclass 39, count 0 2006.257.07:31:45.19#ibcon#flushed, iclass 39, count 0 2006.257.07:31:45.19#ibcon#about to write, iclass 39, count 0 2006.257.07:31:45.19#ibcon#wrote, iclass 39, count 0 2006.257.07:31:45.19#ibcon#about to read 3, iclass 39, count 0 2006.257.07:31:45.22#ibcon#read 3, iclass 39, count 0 2006.257.07:31:45.22#ibcon#about to read 4, iclass 39, count 0 2006.257.07:31:45.22#ibcon#read 4, iclass 39, count 0 2006.257.07:31:45.22#ibcon#about to read 5, iclass 39, count 0 2006.257.07:31:45.22#ibcon#read 5, iclass 39, count 0 2006.257.07:31:45.22#ibcon#about to read 6, iclass 39, count 0 2006.257.07:31:45.22#ibcon#read 6, iclass 39, count 0 2006.257.07:31:45.22#ibcon#end of sib2, iclass 39, count 0 2006.257.07:31:45.22#ibcon#*after write, iclass 39, count 0 2006.257.07:31:45.22#ibcon#*before return 0, iclass 39, count 0 2006.257.07:31:45.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:45.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:31:45.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.07:31:45.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.07:31:45.22$vck44/vblo=5,709.99 2006.257.07:31:45.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.07:31:45.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.07:31:45.22#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:45.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:45.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:45.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:45.22#ibcon#enter wrdev, iclass 3, count 0 2006.257.07:31:45.22#ibcon#first serial, iclass 3, count 0 2006.257.07:31:45.22#ibcon#enter sib2, iclass 3, count 0 2006.257.07:31:45.22#ibcon#flushed, iclass 3, count 0 2006.257.07:31:45.22#ibcon#about to write, iclass 3, count 0 2006.257.07:31:45.22#ibcon#wrote, iclass 3, count 0 2006.257.07:31:45.22#ibcon#about to read 3, iclass 3, count 0 2006.257.07:31:45.24#ibcon#read 3, iclass 3, count 0 2006.257.07:31:45.24#ibcon#about to read 4, iclass 3, count 0 2006.257.07:31:45.24#ibcon#read 4, iclass 3, count 0 2006.257.07:31:45.24#ibcon#about to read 5, iclass 3, count 0 2006.257.07:31:45.24#ibcon#read 5, iclass 3, count 0 2006.257.07:31:45.24#ibcon#about to read 6, iclass 3, count 0 2006.257.07:31:45.24#ibcon#read 6, iclass 3, count 0 2006.257.07:31:45.24#ibcon#end of sib2, iclass 3, count 0 2006.257.07:31:45.24#ibcon#*mode == 0, iclass 3, count 0 2006.257.07:31:45.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.07:31:45.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.07:31:45.24#ibcon#*before write, iclass 3, count 0 2006.257.07:31:45.24#ibcon#enter sib2, iclass 3, count 0 2006.257.07:31:45.24#ibcon#flushed, iclass 3, count 0 2006.257.07:31:45.24#ibcon#about to write, iclass 3, count 0 2006.257.07:31:45.24#ibcon#wrote, iclass 3, count 0 2006.257.07:31:45.24#ibcon#about to read 3, iclass 3, count 0 2006.257.07:31:45.28#ibcon#read 3, iclass 3, count 0 2006.257.07:31:45.28#ibcon#about to read 4, iclass 3, count 0 2006.257.07:31:45.28#ibcon#read 4, iclass 3, count 0 2006.257.07:31:45.28#ibcon#about to read 5, iclass 3, count 0 2006.257.07:31:45.28#ibcon#read 5, iclass 3, count 0 2006.257.07:31:45.28#ibcon#about to read 6, iclass 3, count 0 2006.257.07:31:45.28#ibcon#read 6, iclass 3, count 0 2006.257.07:31:45.28#ibcon#end of sib2, iclass 3, count 0 2006.257.07:31:45.28#ibcon#*after write, iclass 3, count 0 2006.257.07:31:45.28#ibcon#*before return 0, iclass 3, count 0 2006.257.07:31:45.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:45.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:31:45.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.07:31:45.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.07:31:45.28$vck44/vb=5,4 2006.257.07:31:45.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.07:31:45.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.07:31:45.28#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:45.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:45.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:45.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:45.34#ibcon#enter wrdev, iclass 5, count 2 2006.257.07:31:45.34#ibcon#first serial, iclass 5, count 2 2006.257.07:31:45.34#ibcon#enter sib2, iclass 5, count 2 2006.257.07:31:45.34#ibcon#flushed, iclass 5, count 2 2006.257.07:31:45.34#ibcon#about to write, iclass 5, count 2 2006.257.07:31:45.34#ibcon#wrote, iclass 5, count 2 2006.257.07:31:45.34#ibcon#about to read 3, iclass 5, count 2 2006.257.07:31:45.36#ibcon#read 3, iclass 5, count 2 2006.257.07:31:45.36#ibcon#about to read 4, iclass 5, count 2 2006.257.07:31:45.36#ibcon#read 4, iclass 5, count 2 2006.257.07:31:45.36#ibcon#about to read 5, iclass 5, count 2 2006.257.07:31:45.36#ibcon#read 5, iclass 5, count 2 2006.257.07:31:45.36#ibcon#about to read 6, iclass 5, count 2 2006.257.07:31:45.36#ibcon#read 6, iclass 5, count 2 2006.257.07:31:45.36#ibcon#end of sib2, iclass 5, count 2 2006.257.07:31:45.36#ibcon#*mode == 0, iclass 5, count 2 2006.257.07:31:45.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.07:31:45.36#ibcon#[27=AT05-04\r\n] 2006.257.07:31:45.36#ibcon#*before write, iclass 5, count 2 2006.257.07:31:45.36#ibcon#enter sib2, iclass 5, count 2 2006.257.07:31:45.36#ibcon#flushed, iclass 5, count 2 2006.257.07:31:45.36#ibcon#about to write, iclass 5, count 2 2006.257.07:31:45.36#ibcon#wrote, iclass 5, count 2 2006.257.07:31:45.36#ibcon#about to read 3, iclass 5, count 2 2006.257.07:31:45.39#ibcon#read 3, iclass 5, count 2 2006.257.07:31:45.39#ibcon#about to read 4, iclass 5, count 2 2006.257.07:31:45.39#ibcon#read 4, iclass 5, count 2 2006.257.07:31:45.39#ibcon#about to read 5, iclass 5, count 2 2006.257.07:31:45.39#ibcon#read 5, iclass 5, count 2 2006.257.07:31:45.39#ibcon#about to read 6, iclass 5, count 2 2006.257.07:31:45.39#ibcon#read 6, iclass 5, count 2 2006.257.07:31:45.39#ibcon#end of sib2, iclass 5, count 2 2006.257.07:31:45.39#ibcon#*after write, iclass 5, count 2 2006.257.07:31:45.39#ibcon#*before return 0, iclass 5, count 2 2006.257.07:31:45.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:45.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:31:45.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.07:31:45.39#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:45.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:45.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:45.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:45.51#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:31:45.51#ibcon#first serial, iclass 5, count 0 2006.257.07:31:45.51#ibcon#enter sib2, iclass 5, count 0 2006.257.07:31:45.51#ibcon#flushed, iclass 5, count 0 2006.257.07:31:45.51#ibcon#about to write, iclass 5, count 0 2006.257.07:31:45.51#ibcon#wrote, iclass 5, count 0 2006.257.07:31:45.51#ibcon#about to read 3, iclass 5, count 0 2006.257.07:31:45.53#ibcon#read 3, iclass 5, count 0 2006.257.07:31:45.53#ibcon#about to read 4, iclass 5, count 0 2006.257.07:31:45.53#ibcon#read 4, iclass 5, count 0 2006.257.07:31:45.53#ibcon#about to read 5, iclass 5, count 0 2006.257.07:31:45.53#ibcon#read 5, iclass 5, count 0 2006.257.07:31:45.53#ibcon#about to read 6, iclass 5, count 0 2006.257.07:31:45.53#ibcon#read 6, iclass 5, count 0 2006.257.07:31:45.53#ibcon#end of sib2, iclass 5, count 0 2006.257.07:31:45.53#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:31:45.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:31:45.53#ibcon#[27=USB\r\n] 2006.257.07:31:45.53#ibcon#*before write, iclass 5, count 0 2006.257.07:31:45.53#ibcon#enter sib2, iclass 5, count 0 2006.257.07:31:45.53#ibcon#flushed, iclass 5, count 0 2006.257.07:31:45.53#ibcon#about to write, iclass 5, count 0 2006.257.07:31:45.53#ibcon#wrote, iclass 5, count 0 2006.257.07:31:45.53#ibcon#about to read 3, iclass 5, count 0 2006.257.07:31:45.56#ibcon#read 3, iclass 5, count 0 2006.257.07:31:45.56#ibcon#about to read 4, iclass 5, count 0 2006.257.07:31:45.56#ibcon#read 4, iclass 5, count 0 2006.257.07:31:45.56#ibcon#about to read 5, iclass 5, count 0 2006.257.07:31:45.56#ibcon#read 5, iclass 5, count 0 2006.257.07:31:45.56#ibcon#about to read 6, iclass 5, count 0 2006.257.07:31:45.56#ibcon#read 6, iclass 5, count 0 2006.257.07:31:45.56#ibcon#end of sib2, iclass 5, count 0 2006.257.07:31:45.56#ibcon#*after write, iclass 5, count 0 2006.257.07:31:45.56#ibcon#*before return 0, iclass 5, count 0 2006.257.07:31:45.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:45.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:31:45.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:31:45.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:31:45.56$vck44/vblo=6,719.99 2006.257.07:31:45.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.07:31:45.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.07:31:45.56#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:45.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:45.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:45.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:45.56#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:31:45.56#ibcon#first serial, iclass 7, count 0 2006.257.07:31:45.56#ibcon#enter sib2, iclass 7, count 0 2006.257.07:31:45.56#ibcon#flushed, iclass 7, count 0 2006.257.07:31:45.56#ibcon#about to write, iclass 7, count 0 2006.257.07:31:45.56#ibcon#wrote, iclass 7, count 0 2006.257.07:31:45.56#ibcon#about to read 3, iclass 7, count 0 2006.257.07:31:45.58#ibcon#read 3, iclass 7, count 0 2006.257.07:31:45.58#ibcon#about to read 4, iclass 7, count 0 2006.257.07:31:45.58#ibcon#read 4, iclass 7, count 0 2006.257.07:31:45.58#ibcon#about to read 5, iclass 7, count 0 2006.257.07:31:45.58#ibcon#read 5, iclass 7, count 0 2006.257.07:31:45.58#ibcon#about to read 6, iclass 7, count 0 2006.257.07:31:45.58#ibcon#read 6, iclass 7, count 0 2006.257.07:31:45.58#ibcon#end of sib2, iclass 7, count 0 2006.257.07:31:45.58#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:31:45.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:31:45.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.07:31:45.58#ibcon#*before write, iclass 7, count 0 2006.257.07:31:45.58#ibcon#enter sib2, iclass 7, count 0 2006.257.07:31:45.58#ibcon#flushed, iclass 7, count 0 2006.257.07:31:45.58#ibcon#about to write, iclass 7, count 0 2006.257.07:31:45.58#ibcon#wrote, iclass 7, count 0 2006.257.07:31:45.58#ibcon#about to read 3, iclass 7, count 0 2006.257.07:31:45.62#ibcon#read 3, iclass 7, count 0 2006.257.07:31:45.62#ibcon#about to read 4, iclass 7, count 0 2006.257.07:31:45.62#ibcon#read 4, iclass 7, count 0 2006.257.07:31:45.62#ibcon#about to read 5, iclass 7, count 0 2006.257.07:31:45.62#ibcon#read 5, iclass 7, count 0 2006.257.07:31:45.62#ibcon#about to read 6, iclass 7, count 0 2006.257.07:31:45.62#ibcon#read 6, iclass 7, count 0 2006.257.07:31:45.62#ibcon#end of sib2, iclass 7, count 0 2006.257.07:31:45.62#ibcon#*after write, iclass 7, count 0 2006.257.07:31:45.62#ibcon#*before return 0, iclass 7, count 0 2006.257.07:31:45.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:45.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:31:45.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:31:45.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:31:45.62$vck44/vb=6,4 2006.257.07:31:45.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.07:31:45.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.07:31:45.62#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:45.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:45.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:45.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:45.68#ibcon#enter wrdev, iclass 11, count 2 2006.257.07:31:45.68#ibcon#first serial, iclass 11, count 2 2006.257.07:31:45.68#ibcon#enter sib2, iclass 11, count 2 2006.257.07:31:45.68#ibcon#flushed, iclass 11, count 2 2006.257.07:31:45.68#ibcon#about to write, iclass 11, count 2 2006.257.07:31:45.68#ibcon#wrote, iclass 11, count 2 2006.257.07:31:45.68#ibcon#about to read 3, iclass 11, count 2 2006.257.07:31:45.70#ibcon#read 3, iclass 11, count 2 2006.257.07:31:45.70#ibcon#about to read 4, iclass 11, count 2 2006.257.07:31:45.70#ibcon#read 4, iclass 11, count 2 2006.257.07:31:45.70#ibcon#about to read 5, iclass 11, count 2 2006.257.07:31:45.70#ibcon#read 5, iclass 11, count 2 2006.257.07:31:45.70#ibcon#about to read 6, iclass 11, count 2 2006.257.07:31:45.70#ibcon#read 6, iclass 11, count 2 2006.257.07:31:45.70#ibcon#end of sib2, iclass 11, count 2 2006.257.07:31:45.70#ibcon#*mode == 0, iclass 11, count 2 2006.257.07:31:45.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.07:31:45.70#ibcon#[27=AT06-04\r\n] 2006.257.07:31:45.70#ibcon#*before write, iclass 11, count 2 2006.257.07:31:45.70#ibcon#enter sib2, iclass 11, count 2 2006.257.07:31:45.70#ibcon#flushed, iclass 11, count 2 2006.257.07:31:45.70#ibcon#about to write, iclass 11, count 2 2006.257.07:31:45.70#ibcon#wrote, iclass 11, count 2 2006.257.07:31:45.70#ibcon#about to read 3, iclass 11, count 2 2006.257.07:31:45.73#ibcon#read 3, iclass 11, count 2 2006.257.07:31:45.73#ibcon#about to read 4, iclass 11, count 2 2006.257.07:31:45.73#ibcon#read 4, iclass 11, count 2 2006.257.07:31:45.73#ibcon#about to read 5, iclass 11, count 2 2006.257.07:31:45.73#ibcon#read 5, iclass 11, count 2 2006.257.07:31:45.73#ibcon#about to read 6, iclass 11, count 2 2006.257.07:31:45.73#ibcon#read 6, iclass 11, count 2 2006.257.07:31:45.73#ibcon#end of sib2, iclass 11, count 2 2006.257.07:31:45.73#ibcon#*after write, iclass 11, count 2 2006.257.07:31:45.73#ibcon#*before return 0, iclass 11, count 2 2006.257.07:31:45.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:45.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:31:45.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.07:31:45.73#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:45.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:45.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:45.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:45.85#ibcon#enter wrdev, iclass 11, count 0 2006.257.07:31:45.85#ibcon#first serial, iclass 11, count 0 2006.257.07:31:45.85#ibcon#enter sib2, iclass 11, count 0 2006.257.07:31:45.85#ibcon#flushed, iclass 11, count 0 2006.257.07:31:45.85#ibcon#about to write, iclass 11, count 0 2006.257.07:31:45.85#ibcon#wrote, iclass 11, count 0 2006.257.07:31:45.85#ibcon#about to read 3, iclass 11, count 0 2006.257.07:31:45.87#ibcon#read 3, iclass 11, count 0 2006.257.07:31:45.87#ibcon#about to read 4, iclass 11, count 0 2006.257.07:31:45.87#ibcon#read 4, iclass 11, count 0 2006.257.07:31:45.87#ibcon#about to read 5, iclass 11, count 0 2006.257.07:31:45.87#ibcon#read 5, iclass 11, count 0 2006.257.07:31:45.87#ibcon#about to read 6, iclass 11, count 0 2006.257.07:31:45.87#ibcon#read 6, iclass 11, count 0 2006.257.07:31:45.87#ibcon#end of sib2, iclass 11, count 0 2006.257.07:31:45.87#ibcon#*mode == 0, iclass 11, count 0 2006.257.07:31:45.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.07:31:45.87#ibcon#[27=USB\r\n] 2006.257.07:31:45.87#ibcon#*before write, iclass 11, count 0 2006.257.07:31:45.87#ibcon#enter sib2, iclass 11, count 0 2006.257.07:31:45.87#ibcon#flushed, iclass 11, count 0 2006.257.07:31:45.87#ibcon#about to write, iclass 11, count 0 2006.257.07:31:45.87#ibcon#wrote, iclass 11, count 0 2006.257.07:31:45.87#ibcon#about to read 3, iclass 11, count 0 2006.257.07:31:45.90#ibcon#read 3, iclass 11, count 0 2006.257.07:31:45.90#ibcon#about to read 4, iclass 11, count 0 2006.257.07:31:45.90#ibcon#read 4, iclass 11, count 0 2006.257.07:31:45.90#ibcon#about to read 5, iclass 11, count 0 2006.257.07:31:45.90#ibcon#read 5, iclass 11, count 0 2006.257.07:31:45.90#ibcon#about to read 6, iclass 11, count 0 2006.257.07:31:45.90#ibcon#read 6, iclass 11, count 0 2006.257.07:31:45.90#ibcon#end of sib2, iclass 11, count 0 2006.257.07:31:45.90#ibcon#*after write, iclass 11, count 0 2006.257.07:31:45.90#ibcon#*before return 0, iclass 11, count 0 2006.257.07:31:45.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:45.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:31:45.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.07:31:45.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.07:31:45.90$vck44/vblo=7,734.99 2006.257.07:31:45.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.07:31:45.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.07:31:45.90#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:45.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:45.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:45.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:45.90#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:31:45.90#ibcon#first serial, iclass 13, count 0 2006.257.07:31:45.90#ibcon#enter sib2, iclass 13, count 0 2006.257.07:31:45.90#ibcon#flushed, iclass 13, count 0 2006.257.07:31:45.90#ibcon#about to write, iclass 13, count 0 2006.257.07:31:45.90#ibcon#wrote, iclass 13, count 0 2006.257.07:31:45.90#ibcon#about to read 3, iclass 13, count 0 2006.257.07:31:45.92#ibcon#read 3, iclass 13, count 0 2006.257.07:31:45.92#ibcon#about to read 4, iclass 13, count 0 2006.257.07:31:45.92#ibcon#read 4, iclass 13, count 0 2006.257.07:31:45.92#ibcon#about to read 5, iclass 13, count 0 2006.257.07:31:45.92#ibcon#read 5, iclass 13, count 0 2006.257.07:31:45.92#ibcon#about to read 6, iclass 13, count 0 2006.257.07:31:45.92#ibcon#read 6, iclass 13, count 0 2006.257.07:31:45.92#ibcon#end of sib2, iclass 13, count 0 2006.257.07:31:45.92#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:31:45.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:31:45.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.07:31:45.92#ibcon#*before write, iclass 13, count 0 2006.257.07:31:45.92#ibcon#enter sib2, iclass 13, count 0 2006.257.07:31:45.92#ibcon#flushed, iclass 13, count 0 2006.257.07:31:45.92#ibcon#about to write, iclass 13, count 0 2006.257.07:31:45.92#ibcon#wrote, iclass 13, count 0 2006.257.07:31:45.92#ibcon#about to read 3, iclass 13, count 0 2006.257.07:31:45.96#ibcon#read 3, iclass 13, count 0 2006.257.07:31:45.96#ibcon#about to read 4, iclass 13, count 0 2006.257.07:31:45.96#ibcon#read 4, iclass 13, count 0 2006.257.07:31:45.96#ibcon#about to read 5, iclass 13, count 0 2006.257.07:31:45.96#ibcon#read 5, iclass 13, count 0 2006.257.07:31:45.96#ibcon#about to read 6, iclass 13, count 0 2006.257.07:31:45.96#ibcon#read 6, iclass 13, count 0 2006.257.07:31:45.96#ibcon#end of sib2, iclass 13, count 0 2006.257.07:31:45.96#ibcon#*after write, iclass 13, count 0 2006.257.07:31:45.96#ibcon#*before return 0, iclass 13, count 0 2006.257.07:31:45.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:45.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:31:45.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:31:45.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:31:45.96$vck44/vb=7,4 2006.257.07:31:45.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.07:31:45.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.07:31:45.96#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:45.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:46.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:46.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:46.02#ibcon#enter wrdev, iclass 15, count 2 2006.257.07:31:46.02#ibcon#first serial, iclass 15, count 2 2006.257.07:31:46.02#ibcon#enter sib2, iclass 15, count 2 2006.257.07:31:46.02#ibcon#flushed, iclass 15, count 2 2006.257.07:31:46.02#ibcon#about to write, iclass 15, count 2 2006.257.07:31:46.02#ibcon#wrote, iclass 15, count 2 2006.257.07:31:46.02#ibcon#about to read 3, iclass 15, count 2 2006.257.07:31:46.03#abcon#<5=/15 1.6 3.6 21.22 861012.5\r\n> 2006.257.07:31:46.04#ibcon#read 3, iclass 15, count 2 2006.257.07:31:46.04#ibcon#about to read 4, iclass 15, count 2 2006.257.07:31:46.04#ibcon#read 4, iclass 15, count 2 2006.257.07:31:46.04#ibcon#about to read 5, iclass 15, count 2 2006.257.07:31:46.04#ibcon#read 5, iclass 15, count 2 2006.257.07:31:46.04#ibcon#about to read 6, iclass 15, count 2 2006.257.07:31:46.04#ibcon#read 6, iclass 15, count 2 2006.257.07:31:46.04#ibcon#end of sib2, iclass 15, count 2 2006.257.07:31:46.04#ibcon#*mode == 0, iclass 15, count 2 2006.257.07:31:46.04#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.07:31:46.04#ibcon#[27=AT07-04\r\n] 2006.257.07:31:46.04#ibcon#*before write, iclass 15, count 2 2006.257.07:31:46.04#ibcon#enter sib2, iclass 15, count 2 2006.257.07:31:46.04#ibcon#flushed, iclass 15, count 2 2006.257.07:31:46.04#ibcon#about to write, iclass 15, count 2 2006.257.07:31:46.04#ibcon#wrote, iclass 15, count 2 2006.257.07:31:46.04#ibcon#about to read 3, iclass 15, count 2 2006.257.07:31:46.05#abcon#{5=INTERFACE CLEAR} 2006.257.07:31:46.07#ibcon#read 3, iclass 15, count 2 2006.257.07:31:46.07#ibcon#about to read 4, iclass 15, count 2 2006.257.07:31:46.07#ibcon#read 4, iclass 15, count 2 2006.257.07:31:46.07#ibcon#about to read 5, iclass 15, count 2 2006.257.07:31:46.07#ibcon#read 5, iclass 15, count 2 2006.257.07:31:46.07#ibcon#about to read 6, iclass 15, count 2 2006.257.07:31:46.07#ibcon#read 6, iclass 15, count 2 2006.257.07:31:46.07#ibcon#end of sib2, iclass 15, count 2 2006.257.07:31:46.07#ibcon#*after write, iclass 15, count 2 2006.257.07:31:46.07#ibcon#*before return 0, iclass 15, count 2 2006.257.07:31:46.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:46.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:31:46.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.07:31:46.07#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:46.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:46.11#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:31:46.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:46.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:46.19#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:31:46.19#ibcon#first serial, iclass 15, count 0 2006.257.07:31:46.19#ibcon#enter sib2, iclass 15, count 0 2006.257.07:31:46.19#ibcon#flushed, iclass 15, count 0 2006.257.07:31:46.19#ibcon#about to write, iclass 15, count 0 2006.257.07:31:46.19#ibcon#wrote, iclass 15, count 0 2006.257.07:31:46.19#ibcon#about to read 3, iclass 15, count 0 2006.257.07:31:46.21#ibcon#read 3, iclass 15, count 0 2006.257.07:31:46.21#ibcon#about to read 4, iclass 15, count 0 2006.257.07:31:46.21#ibcon#read 4, iclass 15, count 0 2006.257.07:31:46.21#ibcon#about to read 5, iclass 15, count 0 2006.257.07:31:46.21#ibcon#read 5, iclass 15, count 0 2006.257.07:31:46.21#ibcon#about to read 6, iclass 15, count 0 2006.257.07:31:46.21#ibcon#read 6, iclass 15, count 0 2006.257.07:31:46.21#ibcon#end of sib2, iclass 15, count 0 2006.257.07:31:46.21#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:31:46.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:31:46.21#ibcon#[27=USB\r\n] 2006.257.07:31:46.21#ibcon#*before write, iclass 15, count 0 2006.257.07:31:46.21#ibcon#enter sib2, iclass 15, count 0 2006.257.07:31:46.21#ibcon#flushed, iclass 15, count 0 2006.257.07:31:46.21#ibcon#about to write, iclass 15, count 0 2006.257.07:31:46.21#ibcon#wrote, iclass 15, count 0 2006.257.07:31:46.21#ibcon#about to read 3, iclass 15, count 0 2006.257.07:31:46.24#ibcon#read 3, iclass 15, count 0 2006.257.07:31:46.24#ibcon#about to read 4, iclass 15, count 0 2006.257.07:31:46.24#ibcon#read 4, iclass 15, count 0 2006.257.07:31:46.24#ibcon#about to read 5, iclass 15, count 0 2006.257.07:31:46.24#ibcon#read 5, iclass 15, count 0 2006.257.07:31:46.24#ibcon#about to read 6, iclass 15, count 0 2006.257.07:31:46.24#ibcon#read 6, iclass 15, count 0 2006.257.07:31:46.24#ibcon#end of sib2, iclass 15, count 0 2006.257.07:31:46.24#ibcon#*after write, iclass 15, count 0 2006.257.07:31:46.24#ibcon#*before return 0, iclass 15, count 0 2006.257.07:31:46.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:46.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:31:46.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:31:46.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:31:46.24$vck44/vblo=8,744.99 2006.257.07:31:46.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.07:31:46.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.07:31:46.24#ibcon#ireg 17 cls_cnt 0 2006.257.07:31:46.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:46.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:46.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:46.24#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:31:46.24#ibcon#first serial, iclass 21, count 0 2006.257.07:31:46.24#ibcon#enter sib2, iclass 21, count 0 2006.257.07:31:46.24#ibcon#flushed, iclass 21, count 0 2006.257.07:31:46.24#ibcon#about to write, iclass 21, count 0 2006.257.07:31:46.24#ibcon#wrote, iclass 21, count 0 2006.257.07:31:46.24#ibcon#about to read 3, iclass 21, count 0 2006.257.07:31:46.26#ibcon#read 3, iclass 21, count 0 2006.257.07:31:46.26#ibcon#about to read 4, iclass 21, count 0 2006.257.07:31:46.26#ibcon#read 4, iclass 21, count 0 2006.257.07:31:46.26#ibcon#about to read 5, iclass 21, count 0 2006.257.07:31:46.26#ibcon#read 5, iclass 21, count 0 2006.257.07:31:46.26#ibcon#about to read 6, iclass 21, count 0 2006.257.07:31:46.26#ibcon#read 6, iclass 21, count 0 2006.257.07:31:46.26#ibcon#end of sib2, iclass 21, count 0 2006.257.07:31:46.26#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:31:46.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:31:46.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.07:31:46.26#ibcon#*before write, iclass 21, count 0 2006.257.07:31:46.26#ibcon#enter sib2, iclass 21, count 0 2006.257.07:31:46.26#ibcon#flushed, iclass 21, count 0 2006.257.07:31:46.26#ibcon#about to write, iclass 21, count 0 2006.257.07:31:46.26#ibcon#wrote, iclass 21, count 0 2006.257.07:31:46.26#ibcon#about to read 3, iclass 21, count 0 2006.257.07:31:46.30#ibcon#read 3, iclass 21, count 0 2006.257.07:31:46.30#ibcon#about to read 4, iclass 21, count 0 2006.257.07:31:46.30#ibcon#read 4, iclass 21, count 0 2006.257.07:31:46.30#ibcon#about to read 5, iclass 21, count 0 2006.257.07:31:46.30#ibcon#read 5, iclass 21, count 0 2006.257.07:31:46.30#ibcon#about to read 6, iclass 21, count 0 2006.257.07:31:46.30#ibcon#read 6, iclass 21, count 0 2006.257.07:31:46.30#ibcon#end of sib2, iclass 21, count 0 2006.257.07:31:46.30#ibcon#*after write, iclass 21, count 0 2006.257.07:31:46.30#ibcon#*before return 0, iclass 21, count 0 2006.257.07:31:46.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:46.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:31:46.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:31:46.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:31:46.30$vck44/vb=8,4 2006.257.07:31:46.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.07:31:46.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.07:31:46.30#ibcon#ireg 11 cls_cnt 2 2006.257.07:31:46.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:46.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:46.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:46.36#ibcon#enter wrdev, iclass 23, count 2 2006.257.07:31:46.36#ibcon#first serial, iclass 23, count 2 2006.257.07:31:46.36#ibcon#enter sib2, iclass 23, count 2 2006.257.07:31:46.36#ibcon#flushed, iclass 23, count 2 2006.257.07:31:46.36#ibcon#about to write, iclass 23, count 2 2006.257.07:31:46.36#ibcon#wrote, iclass 23, count 2 2006.257.07:31:46.36#ibcon#about to read 3, iclass 23, count 2 2006.257.07:31:46.38#ibcon#read 3, iclass 23, count 2 2006.257.07:31:46.38#ibcon#about to read 4, iclass 23, count 2 2006.257.07:31:46.38#ibcon#read 4, iclass 23, count 2 2006.257.07:31:46.38#ibcon#about to read 5, iclass 23, count 2 2006.257.07:31:46.38#ibcon#read 5, iclass 23, count 2 2006.257.07:31:46.38#ibcon#about to read 6, iclass 23, count 2 2006.257.07:31:46.38#ibcon#read 6, iclass 23, count 2 2006.257.07:31:46.38#ibcon#end of sib2, iclass 23, count 2 2006.257.07:31:46.38#ibcon#*mode == 0, iclass 23, count 2 2006.257.07:31:46.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.07:31:46.38#ibcon#[27=AT08-04\r\n] 2006.257.07:31:46.38#ibcon#*before write, iclass 23, count 2 2006.257.07:31:46.38#ibcon#enter sib2, iclass 23, count 2 2006.257.07:31:46.38#ibcon#flushed, iclass 23, count 2 2006.257.07:31:46.38#ibcon#about to write, iclass 23, count 2 2006.257.07:31:46.38#ibcon#wrote, iclass 23, count 2 2006.257.07:31:46.38#ibcon#about to read 3, iclass 23, count 2 2006.257.07:31:46.41#ibcon#read 3, iclass 23, count 2 2006.257.07:31:46.41#ibcon#about to read 4, iclass 23, count 2 2006.257.07:31:46.41#ibcon#read 4, iclass 23, count 2 2006.257.07:31:46.41#ibcon#about to read 5, iclass 23, count 2 2006.257.07:31:46.41#ibcon#read 5, iclass 23, count 2 2006.257.07:31:46.41#ibcon#about to read 6, iclass 23, count 2 2006.257.07:31:46.41#ibcon#read 6, iclass 23, count 2 2006.257.07:31:46.41#ibcon#end of sib2, iclass 23, count 2 2006.257.07:31:46.41#ibcon#*after write, iclass 23, count 2 2006.257.07:31:46.41#ibcon#*before return 0, iclass 23, count 2 2006.257.07:31:46.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:46.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:31:46.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.07:31:46.41#ibcon#ireg 7 cls_cnt 0 2006.257.07:31:46.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:46.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:46.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:46.53#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:31:46.53#ibcon#first serial, iclass 23, count 0 2006.257.07:31:46.53#ibcon#enter sib2, iclass 23, count 0 2006.257.07:31:46.53#ibcon#flushed, iclass 23, count 0 2006.257.07:31:46.53#ibcon#about to write, iclass 23, count 0 2006.257.07:31:46.53#ibcon#wrote, iclass 23, count 0 2006.257.07:31:46.53#ibcon#about to read 3, iclass 23, count 0 2006.257.07:31:46.55#ibcon#read 3, iclass 23, count 0 2006.257.07:31:46.55#ibcon#about to read 4, iclass 23, count 0 2006.257.07:31:46.55#ibcon#read 4, iclass 23, count 0 2006.257.07:31:46.55#ibcon#about to read 5, iclass 23, count 0 2006.257.07:31:46.55#ibcon#read 5, iclass 23, count 0 2006.257.07:31:46.55#ibcon#about to read 6, iclass 23, count 0 2006.257.07:31:46.55#ibcon#read 6, iclass 23, count 0 2006.257.07:31:46.55#ibcon#end of sib2, iclass 23, count 0 2006.257.07:31:46.55#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:31:46.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:31:46.55#ibcon#[27=USB\r\n] 2006.257.07:31:46.55#ibcon#*before write, iclass 23, count 0 2006.257.07:31:46.55#ibcon#enter sib2, iclass 23, count 0 2006.257.07:31:46.55#ibcon#flushed, iclass 23, count 0 2006.257.07:31:46.55#ibcon#about to write, iclass 23, count 0 2006.257.07:31:46.55#ibcon#wrote, iclass 23, count 0 2006.257.07:31:46.55#ibcon#about to read 3, iclass 23, count 0 2006.257.07:31:46.58#ibcon#read 3, iclass 23, count 0 2006.257.07:31:46.58#ibcon#about to read 4, iclass 23, count 0 2006.257.07:31:46.58#ibcon#read 4, iclass 23, count 0 2006.257.07:31:46.58#ibcon#about to read 5, iclass 23, count 0 2006.257.07:31:46.58#ibcon#read 5, iclass 23, count 0 2006.257.07:31:46.58#ibcon#about to read 6, iclass 23, count 0 2006.257.07:31:46.58#ibcon#read 6, iclass 23, count 0 2006.257.07:31:46.58#ibcon#end of sib2, iclass 23, count 0 2006.257.07:31:46.58#ibcon#*after write, iclass 23, count 0 2006.257.07:31:46.58#ibcon#*before return 0, iclass 23, count 0 2006.257.07:31:46.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:46.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:31:46.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:31:46.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:31:46.58$vck44/vabw=wide 2006.257.07:31:46.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.07:31:46.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.07:31:46.58#ibcon#ireg 8 cls_cnt 0 2006.257.07:31:46.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:46.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:46.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:46.58#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:31:46.58#ibcon#first serial, iclass 25, count 0 2006.257.07:31:46.58#ibcon#enter sib2, iclass 25, count 0 2006.257.07:31:46.58#ibcon#flushed, iclass 25, count 0 2006.257.07:31:46.58#ibcon#about to write, iclass 25, count 0 2006.257.07:31:46.58#ibcon#wrote, iclass 25, count 0 2006.257.07:31:46.58#ibcon#about to read 3, iclass 25, count 0 2006.257.07:31:46.60#ibcon#read 3, iclass 25, count 0 2006.257.07:31:46.60#ibcon#about to read 4, iclass 25, count 0 2006.257.07:31:46.60#ibcon#read 4, iclass 25, count 0 2006.257.07:31:46.60#ibcon#about to read 5, iclass 25, count 0 2006.257.07:31:46.60#ibcon#read 5, iclass 25, count 0 2006.257.07:31:46.60#ibcon#about to read 6, iclass 25, count 0 2006.257.07:31:46.60#ibcon#read 6, iclass 25, count 0 2006.257.07:31:46.60#ibcon#end of sib2, iclass 25, count 0 2006.257.07:31:46.60#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:31:46.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:31:46.60#ibcon#[25=BW32\r\n] 2006.257.07:31:46.60#ibcon#*before write, iclass 25, count 0 2006.257.07:31:46.60#ibcon#enter sib2, iclass 25, count 0 2006.257.07:31:46.60#ibcon#flushed, iclass 25, count 0 2006.257.07:31:46.60#ibcon#about to write, iclass 25, count 0 2006.257.07:31:46.60#ibcon#wrote, iclass 25, count 0 2006.257.07:31:46.60#ibcon#about to read 3, iclass 25, count 0 2006.257.07:31:46.63#ibcon#read 3, iclass 25, count 0 2006.257.07:31:46.63#ibcon#about to read 4, iclass 25, count 0 2006.257.07:31:46.63#ibcon#read 4, iclass 25, count 0 2006.257.07:31:46.63#ibcon#about to read 5, iclass 25, count 0 2006.257.07:31:46.63#ibcon#read 5, iclass 25, count 0 2006.257.07:31:46.63#ibcon#about to read 6, iclass 25, count 0 2006.257.07:31:46.63#ibcon#read 6, iclass 25, count 0 2006.257.07:31:46.63#ibcon#end of sib2, iclass 25, count 0 2006.257.07:31:46.63#ibcon#*after write, iclass 25, count 0 2006.257.07:31:46.63#ibcon#*before return 0, iclass 25, count 0 2006.257.07:31:46.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:46.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:31:46.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:31:46.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:31:46.63$vck44/vbbw=wide 2006.257.07:31:46.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.07:31:46.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.07:31:46.63#ibcon#ireg 8 cls_cnt 0 2006.257.07:31:46.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:31:46.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:31:46.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:31:46.70#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:31:46.70#ibcon#first serial, iclass 27, count 0 2006.257.07:31:46.70#ibcon#enter sib2, iclass 27, count 0 2006.257.07:31:46.70#ibcon#flushed, iclass 27, count 0 2006.257.07:31:46.70#ibcon#about to write, iclass 27, count 0 2006.257.07:31:46.70#ibcon#wrote, iclass 27, count 0 2006.257.07:31:46.70#ibcon#about to read 3, iclass 27, count 0 2006.257.07:31:46.72#ibcon#read 3, iclass 27, count 0 2006.257.07:31:46.72#ibcon#about to read 4, iclass 27, count 0 2006.257.07:31:46.72#ibcon#read 4, iclass 27, count 0 2006.257.07:31:46.72#ibcon#about to read 5, iclass 27, count 0 2006.257.07:31:46.72#ibcon#read 5, iclass 27, count 0 2006.257.07:31:46.72#ibcon#about to read 6, iclass 27, count 0 2006.257.07:31:46.72#ibcon#read 6, iclass 27, count 0 2006.257.07:31:46.72#ibcon#end of sib2, iclass 27, count 0 2006.257.07:31:46.72#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:31:46.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:31:46.72#ibcon#[27=BW32\r\n] 2006.257.07:31:46.72#ibcon#*before write, iclass 27, count 0 2006.257.07:31:46.72#ibcon#enter sib2, iclass 27, count 0 2006.257.07:31:46.72#ibcon#flushed, iclass 27, count 0 2006.257.07:31:46.72#ibcon#about to write, iclass 27, count 0 2006.257.07:31:46.72#ibcon#wrote, iclass 27, count 0 2006.257.07:31:46.72#ibcon#about to read 3, iclass 27, count 0 2006.257.07:31:46.75#ibcon#read 3, iclass 27, count 0 2006.257.07:31:46.75#ibcon#about to read 4, iclass 27, count 0 2006.257.07:31:46.75#ibcon#read 4, iclass 27, count 0 2006.257.07:31:46.75#ibcon#about to read 5, iclass 27, count 0 2006.257.07:31:46.75#ibcon#read 5, iclass 27, count 0 2006.257.07:31:46.75#ibcon#about to read 6, iclass 27, count 0 2006.257.07:31:46.75#ibcon#read 6, iclass 27, count 0 2006.257.07:31:46.75#ibcon#end of sib2, iclass 27, count 0 2006.257.07:31:46.75#ibcon#*after write, iclass 27, count 0 2006.257.07:31:46.75#ibcon#*before return 0, iclass 27, count 0 2006.257.07:31:46.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:31:46.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:31:46.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:31:46.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:31:46.75$setupk4/ifdk4 2006.257.07:31:46.75$ifdk4/lo= 2006.257.07:31:46.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.07:31:46.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.07:31:46.75$ifdk4/patch= 2006.257.07:31:46.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.07:31:46.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.07:31:46.75$setupk4/!*+20s 2006.257.07:31:56.20#abcon#<5=/15 1.6 3.6 21.22 861012.5\r\n> 2006.257.07:31:56.22#abcon#{5=INTERFACE CLEAR} 2006.257.07:31:56.28#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:32:01.26$setupk4/"tpicd 2006.257.07:32:01.26$setupk4/echo=off 2006.257.07:32:01.26$setupk4/xlog=off 2006.257.07:32:01.26:!2006.257.07:32:47 2006.257.07:32:02.14#trakl#Source acquired 2006.257.07:32:03.14#flagr#flagr/antenna,acquired 2006.257.07:32:47.00:preob 2006.257.07:32:47.13/onsource/TRACKING 2006.257.07:32:47.13:!2006.257.07:32:57 2006.257.07:32:57.00:"tape 2006.257.07:32:57.00:"st=record 2006.257.07:32:57.00:data_valid=on 2006.257.07:32:57.00:midob 2006.257.07:32:57.13/onsource/TRACKING 2006.257.07:32:57.13/wx/21.20,1012.5,86 2006.257.07:32:57.23/cable/+6.4768E-03 2006.257.07:32:58.32/va/01,08,usb,yes,33,36 2006.257.07:32:58.32/va/02,07,usb,yes,36,36 2006.257.07:32:58.32/va/03,08,usb,yes,32,34 2006.257.07:32:58.32/va/04,07,usb,yes,37,39 2006.257.07:32:58.32/va/05,04,usb,yes,33,34 2006.257.07:32:58.32/va/06,04,usb,yes,37,36 2006.257.07:32:58.32/va/07,04,usb,yes,38,38 2006.257.07:32:58.32/va/08,04,usb,yes,32,39 2006.257.07:32:58.55/valo/01,524.99,yes,locked 2006.257.07:32:58.55/valo/02,534.99,yes,locked 2006.257.07:32:58.55/valo/03,564.99,yes,locked 2006.257.07:32:58.55/valo/04,624.99,yes,locked 2006.257.07:32:58.55/valo/05,734.99,yes,locked 2006.257.07:32:58.55/valo/06,814.99,yes,locked 2006.257.07:32:58.55/valo/07,864.99,yes,locked 2006.257.07:32:58.55/valo/08,884.99,yes,locked 2006.257.07:32:59.64/vb/01,04,usb,yes,33,30 2006.257.07:32:59.64/vb/02,05,usb,yes,31,31 2006.257.07:32:59.64/vb/03,04,usb,yes,31,35 2006.257.07:32:59.64/vb/04,05,usb,yes,32,31 2006.257.07:32:59.64/vb/05,04,usb,yes,28,31 2006.257.07:32:59.64/vb/06,04,usb,yes,33,29 2006.257.07:32:59.64/vb/07,04,usb,yes,33,33 2006.257.07:32:59.64/vb/08,04,usb,yes,30,34 2006.257.07:32:59.87/vblo/01,629.99,yes,locked 2006.257.07:32:59.87/vblo/02,634.99,yes,locked 2006.257.07:32:59.87/vblo/03,649.99,yes,locked 2006.257.07:32:59.87/vblo/04,679.99,yes,locked 2006.257.07:32:59.87/vblo/05,709.99,yes,locked 2006.257.07:32:59.87/vblo/06,719.99,yes,locked 2006.257.07:32:59.87/vblo/07,734.99,yes,locked 2006.257.07:32:59.87/vblo/08,744.99,yes,locked 2006.257.07:33:00.02/vabw/8 2006.257.07:33:00.17/vbbw/8 2006.257.07:33:00.26/xfe/off,on,15.0 2006.257.07:33:00.64/ifatt/23,28,28,28 2006.257.07:33:01.08/fmout-gps/S +4.55E-07 2006.257.07:33:01.12:!2006.257.07:34:37 2006.257.07:34:37.00:data_valid=off 2006.257.07:34:37.00:"et 2006.257.07:34:37.00:!+3s 2006.257.07:34:40.01:"tape 2006.257.07:34:40.01:postob 2006.257.07:34:40.19/cable/+6.4767E-03 2006.257.07:34:40.19/wx/21.18,1012.5,87 2006.257.07:34:41.08/fmout-gps/S +4.56E-07 2006.257.07:34:41.08:scan_name=257-0738,jd0609,170 2006.257.07:34:41.08:source=1958-179,200057.09,-174857.7,2000.0,cw 2006.257.07:34:42.14#flagr#flagr/antenna,new-source 2006.257.07:34:42.14:checkk5 2006.257.07:34:42.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.07:34:42.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.07:34:43.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.07:34:43.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.07:34:44.14/chk_obsdata//k5ts1/T2570732??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.07:34:44.53/chk_obsdata//k5ts2/T2570732??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.07:34:44.97/chk_obsdata//k5ts3/T2570732??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.07:34:45.35/chk_obsdata//k5ts4/T2570732??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.07:34:46.08/k5log//k5ts1_log_newline 2006.257.07:34:46.80/k5log//k5ts2_log_newline 2006.257.07:34:47.53/k5log//k5ts3_log_newline 2006.257.07:34:48.24/k5log//k5ts4_log_newline 2006.257.07:34:48.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.07:34:48.26:setupk4=1 2006.257.07:34:48.26$setupk4/echo=on 2006.257.07:34:48.26$setupk4/pcalon 2006.257.07:34:48.26$pcalon/"no phase cal control is implemented here 2006.257.07:34:48.26$setupk4/"tpicd=stop 2006.257.07:34:48.26$setupk4/"rec=synch_on 2006.257.07:34:48.26$setupk4/"rec_mode=128 2006.257.07:34:48.26$setupk4/!* 2006.257.07:34:48.26$setupk4/recpk4 2006.257.07:34:48.26$recpk4/recpatch= 2006.257.07:34:48.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.07:34:48.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.07:34:48.26$setupk4/vck44 2006.257.07:34:48.26$vck44/valo=1,524.99 2006.257.07:34:48.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.07:34:48.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.07:34:48.26#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:48.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:48.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:48.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:48.26#ibcon#enter wrdev, iclass 28, count 0 2006.257.07:34:48.26#ibcon#first serial, iclass 28, count 0 2006.257.07:34:48.26#ibcon#enter sib2, iclass 28, count 0 2006.257.07:34:48.26#ibcon#flushed, iclass 28, count 0 2006.257.07:34:48.26#ibcon#about to write, iclass 28, count 0 2006.257.07:34:48.26#ibcon#wrote, iclass 28, count 0 2006.257.07:34:48.26#ibcon#about to read 3, iclass 28, count 0 2006.257.07:34:48.28#ibcon#read 3, iclass 28, count 0 2006.257.07:34:48.28#ibcon#about to read 4, iclass 28, count 0 2006.257.07:34:48.28#ibcon#read 4, iclass 28, count 0 2006.257.07:34:48.28#ibcon#about to read 5, iclass 28, count 0 2006.257.07:34:48.28#ibcon#read 5, iclass 28, count 0 2006.257.07:34:48.28#ibcon#about to read 6, iclass 28, count 0 2006.257.07:34:48.28#ibcon#read 6, iclass 28, count 0 2006.257.07:34:48.28#ibcon#end of sib2, iclass 28, count 0 2006.257.07:34:48.28#ibcon#*mode == 0, iclass 28, count 0 2006.257.07:34:48.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.07:34:48.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.07:34:48.28#ibcon#*before write, iclass 28, count 0 2006.257.07:34:48.28#ibcon#enter sib2, iclass 28, count 0 2006.257.07:34:48.28#ibcon#flushed, iclass 28, count 0 2006.257.07:34:48.28#ibcon#about to write, iclass 28, count 0 2006.257.07:34:48.28#ibcon#wrote, iclass 28, count 0 2006.257.07:34:48.28#ibcon#about to read 3, iclass 28, count 0 2006.257.07:34:48.33#ibcon#read 3, iclass 28, count 0 2006.257.07:34:48.33#ibcon#about to read 4, iclass 28, count 0 2006.257.07:34:48.33#ibcon#read 4, iclass 28, count 0 2006.257.07:34:48.33#ibcon#about to read 5, iclass 28, count 0 2006.257.07:34:48.33#ibcon#read 5, iclass 28, count 0 2006.257.07:34:48.33#ibcon#about to read 6, iclass 28, count 0 2006.257.07:34:48.33#ibcon#read 6, iclass 28, count 0 2006.257.07:34:48.33#ibcon#end of sib2, iclass 28, count 0 2006.257.07:34:48.33#ibcon#*after write, iclass 28, count 0 2006.257.07:34:48.33#ibcon#*before return 0, iclass 28, count 0 2006.257.07:34:48.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:48.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:48.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.07:34:48.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.07:34:48.33$vck44/va=1,8 2006.257.07:34:48.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.07:34:48.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.07:34:48.33#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:48.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:48.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:48.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:48.33#ibcon#enter wrdev, iclass 30, count 2 2006.257.07:34:48.33#ibcon#first serial, iclass 30, count 2 2006.257.07:34:48.33#ibcon#enter sib2, iclass 30, count 2 2006.257.07:34:48.33#ibcon#flushed, iclass 30, count 2 2006.257.07:34:48.33#ibcon#about to write, iclass 30, count 2 2006.257.07:34:48.33#ibcon#wrote, iclass 30, count 2 2006.257.07:34:48.33#ibcon#about to read 3, iclass 30, count 2 2006.257.07:34:48.35#ibcon#read 3, iclass 30, count 2 2006.257.07:34:48.35#ibcon#about to read 4, iclass 30, count 2 2006.257.07:34:48.35#ibcon#read 4, iclass 30, count 2 2006.257.07:34:48.35#ibcon#about to read 5, iclass 30, count 2 2006.257.07:34:48.35#ibcon#read 5, iclass 30, count 2 2006.257.07:34:48.35#ibcon#about to read 6, iclass 30, count 2 2006.257.07:34:48.35#ibcon#read 6, iclass 30, count 2 2006.257.07:34:48.35#ibcon#end of sib2, iclass 30, count 2 2006.257.07:34:48.35#ibcon#*mode == 0, iclass 30, count 2 2006.257.07:34:48.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.07:34:48.35#ibcon#[25=AT01-08\r\n] 2006.257.07:34:48.35#ibcon#*before write, iclass 30, count 2 2006.257.07:34:48.35#ibcon#enter sib2, iclass 30, count 2 2006.257.07:34:48.35#ibcon#flushed, iclass 30, count 2 2006.257.07:34:48.35#ibcon#about to write, iclass 30, count 2 2006.257.07:34:48.35#ibcon#wrote, iclass 30, count 2 2006.257.07:34:48.35#ibcon#about to read 3, iclass 30, count 2 2006.257.07:34:48.38#ibcon#read 3, iclass 30, count 2 2006.257.07:34:48.38#ibcon#about to read 4, iclass 30, count 2 2006.257.07:34:48.38#ibcon#read 4, iclass 30, count 2 2006.257.07:34:48.38#ibcon#about to read 5, iclass 30, count 2 2006.257.07:34:48.38#ibcon#read 5, iclass 30, count 2 2006.257.07:34:48.38#ibcon#about to read 6, iclass 30, count 2 2006.257.07:34:48.38#ibcon#read 6, iclass 30, count 2 2006.257.07:34:48.38#ibcon#end of sib2, iclass 30, count 2 2006.257.07:34:48.38#ibcon#*after write, iclass 30, count 2 2006.257.07:34:48.38#ibcon#*before return 0, iclass 30, count 2 2006.257.07:34:48.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:48.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:48.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.07:34:48.38#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:48.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:48.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:48.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:48.50#ibcon#enter wrdev, iclass 30, count 0 2006.257.07:34:48.50#ibcon#first serial, iclass 30, count 0 2006.257.07:34:48.50#ibcon#enter sib2, iclass 30, count 0 2006.257.07:34:48.50#ibcon#flushed, iclass 30, count 0 2006.257.07:34:48.50#ibcon#about to write, iclass 30, count 0 2006.257.07:34:48.50#ibcon#wrote, iclass 30, count 0 2006.257.07:34:48.50#ibcon#about to read 3, iclass 30, count 0 2006.257.07:34:48.52#ibcon#read 3, iclass 30, count 0 2006.257.07:34:48.52#ibcon#about to read 4, iclass 30, count 0 2006.257.07:34:48.52#ibcon#read 4, iclass 30, count 0 2006.257.07:34:48.52#ibcon#about to read 5, iclass 30, count 0 2006.257.07:34:48.52#ibcon#read 5, iclass 30, count 0 2006.257.07:34:48.52#ibcon#about to read 6, iclass 30, count 0 2006.257.07:34:48.52#ibcon#read 6, iclass 30, count 0 2006.257.07:34:48.52#ibcon#end of sib2, iclass 30, count 0 2006.257.07:34:48.52#ibcon#*mode == 0, iclass 30, count 0 2006.257.07:34:48.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.07:34:48.52#ibcon#[25=USB\r\n] 2006.257.07:34:48.52#ibcon#*before write, iclass 30, count 0 2006.257.07:34:48.52#ibcon#enter sib2, iclass 30, count 0 2006.257.07:34:48.52#ibcon#flushed, iclass 30, count 0 2006.257.07:34:48.52#ibcon#about to write, iclass 30, count 0 2006.257.07:34:48.52#ibcon#wrote, iclass 30, count 0 2006.257.07:34:48.52#ibcon#about to read 3, iclass 30, count 0 2006.257.07:34:48.55#ibcon#read 3, iclass 30, count 0 2006.257.07:34:48.55#ibcon#about to read 4, iclass 30, count 0 2006.257.07:34:48.55#ibcon#read 4, iclass 30, count 0 2006.257.07:34:48.55#ibcon#about to read 5, iclass 30, count 0 2006.257.07:34:48.55#ibcon#read 5, iclass 30, count 0 2006.257.07:34:48.55#ibcon#about to read 6, iclass 30, count 0 2006.257.07:34:48.55#ibcon#read 6, iclass 30, count 0 2006.257.07:34:48.55#ibcon#end of sib2, iclass 30, count 0 2006.257.07:34:48.55#ibcon#*after write, iclass 30, count 0 2006.257.07:34:48.55#ibcon#*before return 0, iclass 30, count 0 2006.257.07:34:48.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:48.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:48.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.07:34:48.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.07:34:48.55$vck44/valo=2,534.99 2006.257.07:34:48.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.07:34:48.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.07:34:48.55#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:48.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:48.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:48.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:48.55#ibcon#enter wrdev, iclass 32, count 0 2006.257.07:34:48.55#ibcon#first serial, iclass 32, count 0 2006.257.07:34:48.55#ibcon#enter sib2, iclass 32, count 0 2006.257.07:34:48.55#ibcon#flushed, iclass 32, count 0 2006.257.07:34:48.55#ibcon#about to write, iclass 32, count 0 2006.257.07:34:48.55#ibcon#wrote, iclass 32, count 0 2006.257.07:34:48.55#ibcon#about to read 3, iclass 32, count 0 2006.257.07:34:48.57#ibcon#read 3, iclass 32, count 0 2006.257.07:34:48.57#ibcon#about to read 4, iclass 32, count 0 2006.257.07:34:48.57#ibcon#read 4, iclass 32, count 0 2006.257.07:34:48.57#ibcon#about to read 5, iclass 32, count 0 2006.257.07:34:48.57#ibcon#read 5, iclass 32, count 0 2006.257.07:34:48.57#ibcon#about to read 6, iclass 32, count 0 2006.257.07:34:48.57#ibcon#read 6, iclass 32, count 0 2006.257.07:34:48.57#ibcon#end of sib2, iclass 32, count 0 2006.257.07:34:48.57#ibcon#*mode == 0, iclass 32, count 0 2006.257.07:34:48.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.07:34:48.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.07:34:48.57#ibcon#*before write, iclass 32, count 0 2006.257.07:34:48.57#ibcon#enter sib2, iclass 32, count 0 2006.257.07:34:48.57#ibcon#flushed, iclass 32, count 0 2006.257.07:34:48.57#ibcon#about to write, iclass 32, count 0 2006.257.07:34:48.57#ibcon#wrote, iclass 32, count 0 2006.257.07:34:48.57#ibcon#about to read 3, iclass 32, count 0 2006.257.07:34:48.61#ibcon#read 3, iclass 32, count 0 2006.257.07:34:48.61#ibcon#about to read 4, iclass 32, count 0 2006.257.07:34:48.61#ibcon#read 4, iclass 32, count 0 2006.257.07:34:48.61#ibcon#about to read 5, iclass 32, count 0 2006.257.07:34:48.61#ibcon#read 5, iclass 32, count 0 2006.257.07:34:48.61#ibcon#about to read 6, iclass 32, count 0 2006.257.07:34:48.61#ibcon#read 6, iclass 32, count 0 2006.257.07:34:48.61#ibcon#end of sib2, iclass 32, count 0 2006.257.07:34:48.61#ibcon#*after write, iclass 32, count 0 2006.257.07:34:48.61#ibcon#*before return 0, iclass 32, count 0 2006.257.07:34:48.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:48.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:48.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.07:34:48.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.07:34:48.61$vck44/va=2,7 2006.257.07:34:48.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.07:34:48.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.07:34:48.61#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:48.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:48.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:48.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:48.67#ibcon#enter wrdev, iclass 34, count 2 2006.257.07:34:48.67#ibcon#first serial, iclass 34, count 2 2006.257.07:34:48.67#ibcon#enter sib2, iclass 34, count 2 2006.257.07:34:48.67#ibcon#flushed, iclass 34, count 2 2006.257.07:34:48.67#ibcon#about to write, iclass 34, count 2 2006.257.07:34:48.67#ibcon#wrote, iclass 34, count 2 2006.257.07:34:48.67#ibcon#about to read 3, iclass 34, count 2 2006.257.07:34:48.69#ibcon#read 3, iclass 34, count 2 2006.257.07:34:48.69#ibcon#about to read 4, iclass 34, count 2 2006.257.07:34:48.69#ibcon#read 4, iclass 34, count 2 2006.257.07:34:48.69#ibcon#about to read 5, iclass 34, count 2 2006.257.07:34:48.69#ibcon#read 5, iclass 34, count 2 2006.257.07:34:48.69#ibcon#about to read 6, iclass 34, count 2 2006.257.07:34:48.69#ibcon#read 6, iclass 34, count 2 2006.257.07:34:48.69#ibcon#end of sib2, iclass 34, count 2 2006.257.07:34:48.69#ibcon#*mode == 0, iclass 34, count 2 2006.257.07:34:48.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.07:34:48.69#ibcon#[25=AT02-07\r\n] 2006.257.07:34:48.69#ibcon#*before write, iclass 34, count 2 2006.257.07:34:48.69#ibcon#enter sib2, iclass 34, count 2 2006.257.07:34:48.69#ibcon#flushed, iclass 34, count 2 2006.257.07:34:48.69#ibcon#about to write, iclass 34, count 2 2006.257.07:34:48.69#ibcon#wrote, iclass 34, count 2 2006.257.07:34:48.69#ibcon#about to read 3, iclass 34, count 2 2006.257.07:34:48.72#ibcon#read 3, iclass 34, count 2 2006.257.07:34:48.72#ibcon#about to read 4, iclass 34, count 2 2006.257.07:34:48.72#ibcon#read 4, iclass 34, count 2 2006.257.07:34:48.72#ibcon#about to read 5, iclass 34, count 2 2006.257.07:34:48.72#ibcon#read 5, iclass 34, count 2 2006.257.07:34:48.72#ibcon#about to read 6, iclass 34, count 2 2006.257.07:34:48.72#ibcon#read 6, iclass 34, count 2 2006.257.07:34:48.72#ibcon#end of sib2, iclass 34, count 2 2006.257.07:34:48.72#ibcon#*after write, iclass 34, count 2 2006.257.07:34:48.72#ibcon#*before return 0, iclass 34, count 2 2006.257.07:34:48.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:48.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:48.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.07:34:48.72#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:48.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:48.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:48.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:48.84#ibcon#enter wrdev, iclass 34, count 0 2006.257.07:34:48.84#ibcon#first serial, iclass 34, count 0 2006.257.07:34:48.84#ibcon#enter sib2, iclass 34, count 0 2006.257.07:34:48.84#ibcon#flushed, iclass 34, count 0 2006.257.07:34:48.84#ibcon#about to write, iclass 34, count 0 2006.257.07:34:48.84#ibcon#wrote, iclass 34, count 0 2006.257.07:34:48.84#ibcon#about to read 3, iclass 34, count 0 2006.257.07:34:48.86#ibcon#read 3, iclass 34, count 0 2006.257.07:34:48.86#ibcon#about to read 4, iclass 34, count 0 2006.257.07:34:48.86#ibcon#read 4, iclass 34, count 0 2006.257.07:34:48.86#ibcon#about to read 5, iclass 34, count 0 2006.257.07:34:48.86#ibcon#read 5, iclass 34, count 0 2006.257.07:34:48.86#ibcon#about to read 6, iclass 34, count 0 2006.257.07:34:48.86#ibcon#read 6, iclass 34, count 0 2006.257.07:34:48.86#ibcon#end of sib2, iclass 34, count 0 2006.257.07:34:48.86#ibcon#*mode == 0, iclass 34, count 0 2006.257.07:34:48.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.07:34:48.86#ibcon#[25=USB\r\n] 2006.257.07:34:48.86#ibcon#*before write, iclass 34, count 0 2006.257.07:34:48.86#ibcon#enter sib2, iclass 34, count 0 2006.257.07:34:48.86#ibcon#flushed, iclass 34, count 0 2006.257.07:34:48.86#ibcon#about to write, iclass 34, count 0 2006.257.07:34:48.86#ibcon#wrote, iclass 34, count 0 2006.257.07:34:48.86#ibcon#about to read 3, iclass 34, count 0 2006.257.07:34:48.89#ibcon#read 3, iclass 34, count 0 2006.257.07:34:48.89#ibcon#about to read 4, iclass 34, count 0 2006.257.07:34:48.89#ibcon#read 4, iclass 34, count 0 2006.257.07:34:48.89#ibcon#about to read 5, iclass 34, count 0 2006.257.07:34:48.89#ibcon#read 5, iclass 34, count 0 2006.257.07:34:48.89#ibcon#about to read 6, iclass 34, count 0 2006.257.07:34:48.89#ibcon#read 6, iclass 34, count 0 2006.257.07:34:48.89#ibcon#end of sib2, iclass 34, count 0 2006.257.07:34:48.89#ibcon#*after write, iclass 34, count 0 2006.257.07:34:48.89#ibcon#*before return 0, iclass 34, count 0 2006.257.07:34:48.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:48.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:48.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.07:34:48.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.07:34:48.89$vck44/valo=3,564.99 2006.257.07:34:48.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.07:34:48.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.07:34:48.89#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:48.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:48.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:48.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:48.89#ibcon#enter wrdev, iclass 36, count 0 2006.257.07:34:48.89#ibcon#first serial, iclass 36, count 0 2006.257.07:34:48.89#ibcon#enter sib2, iclass 36, count 0 2006.257.07:34:48.89#ibcon#flushed, iclass 36, count 0 2006.257.07:34:48.89#ibcon#about to write, iclass 36, count 0 2006.257.07:34:48.89#ibcon#wrote, iclass 36, count 0 2006.257.07:34:48.89#ibcon#about to read 3, iclass 36, count 0 2006.257.07:34:48.91#ibcon#read 3, iclass 36, count 0 2006.257.07:34:48.91#ibcon#about to read 4, iclass 36, count 0 2006.257.07:34:48.91#ibcon#read 4, iclass 36, count 0 2006.257.07:34:48.91#ibcon#about to read 5, iclass 36, count 0 2006.257.07:34:48.91#ibcon#read 5, iclass 36, count 0 2006.257.07:34:48.91#ibcon#about to read 6, iclass 36, count 0 2006.257.07:34:48.91#ibcon#read 6, iclass 36, count 0 2006.257.07:34:48.91#ibcon#end of sib2, iclass 36, count 0 2006.257.07:34:48.91#ibcon#*mode == 0, iclass 36, count 0 2006.257.07:34:48.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.07:34:48.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.07:34:48.91#ibcon#*before write, iclass 36, count 0 2006.257.07:34:48.91#ibcon#enter sib2, iclass 36, count 0 2006.257.07:34:48.91#ibcon#flushed, iclass 36, count 0 2006.257.07:34:48.91#ibcon#about to write, iclass 36, count 0 2006.257.07:34:48.91#ibcon#wrote, iclass 36, count 0 2006.257.07:34:48.91#ibcon#about to read 3, iclass 36, count 0 2006.257.07:34:48.95#ibcon#read 3, iclass 36, count 0 2006.257.07:34:48.95#ibcon#about to read 4, iclass 36, count 0 2006.257.07:34:48.95#ibcon#read 4, iclass 36, count 0 2006.257.07:34:48.95#ibcon#about to read 5, iclass 36, count 0 2006.257.07:34:48.95#ibcon#read 5, iclass 36, count 0 2006.257.07:34:48.95#ibcon#about to read 6, iclass 36, count 0 2006.257.07:34:48.95#ibcon#read 6, iclass 36, count 0 2006.257.07:34:48.95#ibcon#end of sib2, iclass 36, count 0 2006.257.07:34:48.95#ibcon#*after write, iclass 36, count 0 2006.257.07:34:48.95#ibcon#*before return 0, iclass 36, count 0 2006.257.07:34:48.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:48.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:48.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.07:34:48.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.07:34:48.95$vck44/va=3,8 2006.257.07:34:48.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.07:34:48.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.07:34:48.95#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:48.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:49.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:49.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:49.01#ibcon#enter wrdev, iclass 38, count 2 2006.257.07:34:49.01#ibcon#first serial, iclass 38, count 2 2006.257.07:34:49.01#ibcon#enter sib2, iclass 38, count 2 2006.257.07:34:49.01#ibcon#flushed, iclass 38, count 2 2006.257.07:34:49.01#ibcon#about to write, iclass 38, count 2 2006.257.07:34:49.01#ibcon#wrote, iclass 38, count 2 2006.257.07:34:49.01#ibcon#about to read 3, iclass 38, count 2 2006.257.07:34:49.03#ibcon#read 3, iclass 38, count 2 2006.257.07:34:49.03#ibcon#about to read 4, iclass 38, count 2 2006.257.07:34:49.03#ibcon#read 4, iclass 38, count 2 2006.257.07:34:49.03#ibcon#about to read 5, iclass 38, count 2 2006.257.07:34:49.03#ibcon#read 5, iclass 38, count 2 2006.257.07:34:49.03#ibcon#about to read 6, iclass 38, count 2 2006.257.07:34:49.03#ibcon#read 6, iclass 38, count 2 2006.257.07:34:49.03#ibcon#end of sib2, iclass 38, count 2 2006.257.07:34:49.03#ibcon#*mode == 0, iclass 38, count 2 2006.257.07:34:49.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.07:34:49.03#ibcon#[25=AT03-08\r\n] 2006.257.07:34:49.03#ibcon#*before write, iclass 38, count 2 2006.257.07:34:49.03#ibcon#enter sib2, iclass 38, count 2 2006.257.07:34:49.03#ibcon#flushed, iclass 38, count 2 2006.257.07:34:49.03#ibcon#about to write, iclass 38, count 2 2006.257.07:34:49.03#ibcon#wrote, iclass 38, count 2 2006.257.07:34:49.03#ibcon#about to read 3, iclass 38, count 2 2006.257.07:34:49.06#ibcon#read 3, iclass 38, count 2 2006.257.07:34:49.06#ibcon#about to read 4, iclass 38, count 2 2006.257.07:34:49.06#ibcon#read 4, iclass 38, count 2 2006.257.07:34:49.06#ibcon#about to read 5, iclass 38, count 2 2006.257.07:34:49.06#ibcon#read 5, iclass 38, count 2 2006.257.07:34:49.06#ibcon#about to read 6, iclass 38, count 2 2006.257.07:34:49.06#ibcon#read 6, iclass 38, count 2 2006.257.07:34:49.06#ibcon#end of sib2, iclass 38, count 2 2006.257.07:34:49.06#ibcon#*after write, iclass 38, count 2 2006.257.07:34:49.06#ibcon#*before return 0, iclass 38, count 2 2006.257.07:34:49.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:49.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:49.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.07:34:49.06#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:49.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:49.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:49.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:49.18#ibcon#enter wrdev, iclass 38, count 0 2006.257.07:34:49.18#ibcon#first serial, iclass 38, count 0 2006.257.07:34:49.18#ibcon#enter sib2, iclass 38, count 0 2006.257.07:34:49.18#ibcon#flushed, iclass 38, count 0 2006.257.07:34:49.18#ibcon#about to write, iclass 38, count 0 2006.257.07:34:49.18#ibcon#wrote, iclass 38, count 0 2006.257.07:34:49.18#ibcon#about to read 3, iclass 38, count 0 2006.257.07:34:49.20#ibcon#read 3, iclass 38, count 0 2006.257.07:34:49.20#ibcon#about to read 4, iclass 38, count 0 2006.257.07:34:49.20#ibcon#read 4, iclass 38, count 0 2006.257.07:34:49.20#ibcon#about to read 5, iclass 38, count 0 2006.257.07:34:49.20#ibcon#read 5, iclass 38, count 0 2006.257.07:34:49.20#ibcon#about to read 6, iclass 38, count 0 2006.257.07:34:49.20#ibcon#read 6, iclass 38, count 0 2006.257.07:34:49.20#ibcon#end of sib2, iclass 38, count 0 2006.257.07:34:49.20#ibcon#*mode == 0, iclass 38, count 0 2006.257.07:34:49.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.07:34:49.20#ibcon#[25=USB\r\n] 2006.257.07:34:49.20#ibcon#*before write, iclass 38, count 0 2006.257.07:34:49.20#ibcon#enter sib2, iclass 38, count 0 2006.257.07:34:49.20#ibcon#flushed, iclass 38, count 0 2006.257.07:34:49.20#ibcon#about to write, iclass 38, count 0 2006.257.07:34:49.20#ibcon#wrote, iclass 38, count 0 2006.257.07:34:49.20#ibcon#about to read 3, iclass 38, count 0 2006.257.07:34:49.23#abcon#<5=/15 1.4 3.6 21.18 861012.5\r\n> 2006.257.07:34:49.23#ibcon#read 3, iclass 38, count 0 2006.257.07:34:49.23#ibcon#about to read 4, iclass 38, count 0 2006.257.07:34:49.23#ibcon#read 4, iclass 38, count 0 2006.257.07:34:49.23#ibcon#about to read 5, iclass 38, count 0 2006.257.07:34:49.23#ibcon#read 5, iclass 38, count 0 2006.257.07:34:49.23#ibcon#about to read 6, iclass 38, count 0 2006.257.07:34:49.23#ibcon#read 6, iclass 38, count 0 2006.257.07:34:49.23#ibcon#end of sib2, iclass 38, count 0 2006.257.07:34:49.23#ibcon#*after write, iclass 38, count 0 2006.257.07:34:49.23#ibcon#*before return 0, iclass 38, count 0 2006.257.07:34:49.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:49.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:49.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.07:34:49.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.07:34:49.23$vck44/valo=4,624.99 2006.257.07:34:49.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.07:34:49.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.07:34:49.23#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:49.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:34:49.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:34:49.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:34:49.23#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:34:49.23#ibcon#first serial, iclass 5, count 0 2006.257.07:34:49.23#ibcon#enter sib2, iclass 5, count 0 2006.257.07:34:49.23#ibcon#flushed, iclass 5, count 0 2006.257.07:34:49.23#ibcon#about to write, iclass 5, count 0 2006.257.07:34:49.23#ibcon#wrote, iclass 5, count 0 2006.257.07:34:49.23#ibcon#about to read 3, iclass 5, count 0 2006.257.07:34:49.25#abcon#{5=INTERFACE CLEAR} 2006.257.07:34:49.25#ibcon#read 3, iclass 5, count 0 2006.257.07:34:49.25#ibcon#about to read 4, iclass 5, count 0 2006.257.07:34:49.25#ibcon#read 4, iclass 5, count 0 2006.257.07:34:49.25#ibcon#about to read 5, iclass 5, count 0 2006.257.07:34:49.25#ibcon#read 5, iclass 5, count 0 2006.257.07:34:49.25#ibcon#about to read 6, iclass 5, count 0 2006.257.07:34:49.25#ibcon#read 6, iclass 5, count 0 2006.257.07:34:49.25#ibcon#end of sib2, iclass 5, count 0 2006.257.07:34:49.25#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:34:49.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:34:49.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.07:34:49.25#ibcon#*before write, iclass 5, count 0 2006.257.07:34:49.25#ibcon#enter sib2, iclass 5, count 0 2006.257.07:34:49.25#ibcon#flushed, iclass 5, count 0 2006.257.07:34:49.25#ibcon#about to write, iclass 5, count 0 2006.257.07:34:49.25#ibcon#wrote, iclass 5, count 0 2006.257.07:34:49.25#ibcon#about to read 3, iclass 5, count 0 2006.257.07:34:49.29#ibcon#read 3, iclass 5, count 0 2006.257.07:34:49.29#ibcon#about to read 4, iclass 5, count 0 2006.257.07:34:49.29#ibcon#read 4, iclass 5, count 0 2006.257.07:34:49.29#ibcon#about to read 5, iclass 5, count 0 2006.257.07:34:49.29#ibcon#read 5, iclass 5, count 0 2006.257.07:34:49.29#ibcon#about to read 6, iclass 5, count 0 2006.257.07:34:49.29#ibcon#read 6, iclass 5, count 0 2006.257.07:34:49.29#ibcon#end of sib2, iclass 5, count 0 2006.257.07:34:49.29#ibcon#*after write, iclass 5, count 0 2006.257.07:34:49.29#ibcon#*before return 0, iclass 5, count 0 2006.257.07:34:49.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:34:49.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:34:49.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:34:49.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:34:49.29$vck44/va=4,7 2006.257.07:34:49.29#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.07:34:49.29#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.07:34:49.29#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:49.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:34:49.31#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:34:49.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:34:49.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:34:49.35#ibcon#enter wrdev, iclass 7, count 2 2006.257.07:34:49.35#ibcon#first serial, iclass 7, count 2 2006.257.07:34:49.35#ibcon#enter sib2, iclass 7, count 2 2006.257.07:34:49.35#ibcon#flushed, iclass 7, count 2 2006.257.07:34:49.35#ibcon#about to write, iclass 7, count 2 2006.257.07:34:49.35#ibcon#wrote, iclass 7, count 2 2006.257.07:34:49.35#ibcon#about to read 3, iclass 7, count 2 2006.257.07:34:49.37#ibcon#read 3, iclass 7, count 2 2006.257.07:34:49.37#ibcon#about to read 4, iclass 7, count 2 2006.257.07:34:49.37#ibcon#read 4, iclass 7, count 2 2006.257.07:34:49.37#ibcon#about to read 5, iclass 7, count 2 2006.257.07:34:49.37#ibcon#read 5, iclass 7, count 2 2006.257.07:34:49.37#ibcon#about to read 6, iclass 7, count 2 2006.257.07:34:49.37#ibcon#read 6, iclass 7, count 2 2006.257.07:34:49.37#ibcon#end of sib2, iclass 7, count 2 2006.257.07:34:49.37#ibcon#*mode == 0, iclass 7, count 2 2006.257.07:34:49.37#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.07:34:49.37#ibcon#[25=AT04-07\r\n] 2006.257.07:34:49.37#ibcon#*before write, iclass 7, count 2 2006.257.07:34:49.37#ibcon#enter sib2, iclass 7, count 2 2006.257.07:34:49.37#ibcon#flushed, iclass 7, count 2 2006.257.07:34:49.37#ibcon#about to write, iclass 7, count 2 2006.257.07:34:49.37#ibcon#wrote, iclass 7, count 2 2006.257.07:34:49.37#ibcon#about to read 3, iclass 7, count 2 2006.257.07:34:49.40#ibcon#read 3, iclass 7, count 2 2006.257.07:34:49.40#ibcon#about to read 4, iclass 7, count 2 2006.257.07:34:49.40#ibcon#read 4, iclass 7, count 2 2006.257.07:34:49.40#ibcon#about to read 5, iclass 7, count 2 2006.257.07:34:49.40#ibcon#read 5, iclass 7, count 2 2006.257.07:34:49.40#ibcon#about to read 6, iclass 7, count 2 2006.257.07:34:49.40#ibcon#read 6, iclass 7, count 2 2006.257.07:34:49.40#ibcon#end of sib2, iclass 7, count 2 2006.257.07:34:49.40#ibcon#*after write, iclass 7, count 2 2006.257.07:34:49.40#ibcon#*before return 0, iclass 7, count 2 2006.257.07:34:49.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:34:49.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:34:49.40#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.07:34:49.40#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:49.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:34:49.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:34:49.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:34:49.52#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:34:49.52#ibcon#first serial, iclass 7, count 0 2006.257.07:34:49.52#ibcon#enter sib2, iclass 7, count 0 2006.257.07:34:49.52#ibcon#flushed, iclass 7, count 0 2006.257.07:34:49.52#ibcon#about to write, iclass 7, count 0 2006.257.07:34:49.52#ibcon#wrote, iclass 7, count 0 2006.257.07:34:49.52#ibcon#about to read 3, iclass 7, count 0 2006.257.07:34:49.54#ibcon#read 3, iclass 7, count 0 2006.257.07:34:49.54#ibcon#about to read 4, iclass 7, count 0 2006.257.07:34:49.54#ibcon#read 4, iclass 7, count 0 2006.257.07:34:49.54#ibcon#about to read 5, iclass 7, count 0 2006.257.07:34:49.54#ibcon#read 5, iclass 7, count 0 2006.257.07:34:49.54#ibcon#about to read 6, iclass 7, count 0 2006.257.07:34:49.54#ibcon#read 6, iclass 7, count 0 2006.257.07:34:49.54#ibcon#end of sib2, iclass 7, count 0 2006.257.07:34:49.54#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:34:49.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:34:49.54#ibcon#[25=USB\r\n] 2006.257.07:34:49.54#ibcon#*before write, iclass 7, count 0 2006.257.07:34:49.54#ibcon#enter sib2, iclass 7, count 0 2006.257.07:34:49.54#ibcon#flushed, iclass 7, count 0 2006.257.07:34:49.54#ibcon#about to write, iclass 7, count 0 2006.257.07:34:49.54#ibcon#wrote, iclass 7, count 0 2006.257.07:34:49.54#ibcon#about to read 3, iclass 7, count 0 2006.257.07:34:49.57#ibcon#read 3, iclass 7, count 0 2006.257.07:34:49.57#ibcon#about to read 4, iclass 7, count 0 2006.257.07:34:49.57#ibcon#read 4, iclass 7, count 0 2006.257.07:34:49.57#ibcon#about to read 5, iclass 7, count 0 2006.257.07:34:49.57#ibcon#read 5, iclass 7, count 0 2006.257.07:34:49.57#ibcon#about to read 6, iclass 7, count 0 2006.257.07:34:49.57#ibcon#read 6, iclass 7, count 0 2006.257.07:34:49.57#ibcon#end of sib2, iclass 7, count 0 2006.257.07:34:49.57#ibcon#*after write, iclass 7, count 0 2006.257.07:34:49.57#ibcon#*before return 0, iclass 7, count 0 2006.257.07:34:49.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:34:49.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:34:49.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:34:49.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:34:49.57$vck44/valo=5,734.99 2006.257.07:34:49.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.07:34:49.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.07:34:49.57#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:49.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:49.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:49.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:49.57#ibcon#enter wrdev, iclass 12, count 0 2006.257.07:34:49.57#ibcon#first serial, iclass 12, count 0 2006.257.07:34:49.57#ibcon#enter sib2, iclass 12, count 0 2006.257.07:34:49.57#ibcon#flushed, iclass 12, count 0 2006.257.07:34:49.57#ibcon#about to write, iclass 12, count 0 2006.257.07:34:49.57#ibcon#wrote, iclass 12, count 0 2006.257.07:34:49.57#ibcon#about to read 3, iclass 12, count 0 2006.257.07:34:49.59#ibcon#read 3, iclass 12, count 0 2006.257.07:34:49.59#ibcon#about to read 4, iclass 12, count 0 2006.257.07:34:49.59#ibcon#read 4, iclass 12, count 0 2006.257.07:34:49.59#ibcon#about to read 5, iclass 12, count 0 2006.257.07:34:49.59#ibcon#read 5, iclass 12, count 0 2006.257.07:34:49.59#ibcon#about to read 6, iclass 12, count 0 2006.257.07:34:49.59#ibcon#read 6, iclass 12, count 0 2006.257.07:34:49.59#ibcon#end of sib2, iclass 12, count 0 2006.257.07:34:49.59#ibcon#*mode == 0, iclass 12, count 0 2006.257.07:34:49.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.07:34:49.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.07:34:49.59#ibcon#*before write, iclass 12, count 0 2006.257.07:34:49.59#ibcon#enter sib2, iclass 12, count 0 2006.257.07:34:49.59#ibcon#flushed, iclass 12, count 0 2006.257.07:34:49.59#ibcon#about to write, iclass 12, count 0 2006.257.07:34:49.59#ibcon#wrote, iclass 12, count 0 2006.257.07:34:49.59#ibcon#about to read 3, iclass 12, count 0 2006.257.07:34:49.63#ibcon#read 3, iclass 12, count 0 2006.257.07:34:49.63#ibcon#about to read 4, iclass 12, count 0 2006.257.07:34:49.63#ibcon#read 4, iclass 12, count 0 2006.257.07:34:49.63#ibcon#about to read 5, iclass 12, count 0 2006.257.07:34:49.63#ibcon#read 5, iclass 12, count 0 2006.257.07:34:49.63#ibcon#about to read 6, iclass 12, count 0 2006.257.07:34:49.63#ibcon#read 6, iclass 12, count 0 2006.257.07:34:49.63#ibcon#end of sib2, iclass 12, count 0 2006.257.07:34:49.63#ibcon#*after write, iclass 12, count 0 2006.257.07:34:49.63#ibcon#*before return 0, iclass 12, count 0 2006.257.07:34:49.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:49.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:49.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.07:34:49.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.07:34:49.63$vck44/va=5,4 2006.257.07:34:49.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.07:34:49.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.07:34:49.63#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:49.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:49.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:49.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:49.69#ibcon#enter wrdev, iclass 14, count 2 2006.257.07:34:49.69#ibcon#first serial, iclass 14, count 2 2006.257.07:34:49.69#ibcon#enter sib2, iclass 14, count 2 2006.257.07:34:49.69#ibcon#flushed, iclass 14, count 2 2006.257.07:34:49.69#ibcon#about to write, iclass 14, count 2 2006.257.07:34:49.69#ibcon#wrote, iclass 14, count 2 2006.257.07:34:49.69#ibcon#about to read 3, iclass 14, count 2 2006.257.07:34:49.71#ibcon#read 3, iclass 14, count 2 2006.257.07:34:49.71#ibcon#about to read 4, iclass 14, count 2 2006.257.07:34:49.71#ibcon#read 4, iclass 14, count 2 2006.257.07:34:49.71#ibcon#about to read 5, iclass 14, count 2 2006.257.07:34:49.71#ibcon#read 5, iclass 14, count 2 2006.257.07:34:49.71#ibcon#about to read 6, iclass 14, count 2 2006.257.07:34:49.71#ibcon#read 6, iclass 14, count 2 2006.257.07:34:49.71#ibcon#end of sib2, iclass 14, count 2 2006.257.07:34:49.71#ibcon#*mode == 0, iclass 14, count 2 2006.257.07:34:49.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.07:34:49.71#ibcon#[25=AT05-04\r\n] 2006.257.07:34:49.71#ibcon#*before write, iclass 14, count 2 2006.257.07:34:49.71#ibcon#enter sib2, iclass 14, count 2 2006.257.07:34:49.71#ibcon#flushed, iclass 14, count 2 2006.257.07:34:49.71#ibcon#about to write, iclass 14, count 2 2006.257.07:34:49.71#ibcon#wrote, iclass 14, count 2 2006.257.07:34:49.71#ibcon#about to read 3, iclass 14, count 2 2006.257.07:34:49.74#ibcon#read 3, iclass 14, count 2 2006.257.07:34:49.74#ibcon#about to read 4, iclass 14, count 2 2006.257.07:34:49.74#ibcon#read 4, iclass 14, count 2 2006.257.07:34:49.74#ibcon#about to read 5, iclass 14, count 2 2006.257.07:34:49.74#ibcon#read 5, iclass 14, count 2 2006.257.07:34:49.74#ibcon#about to read 6, iclass 14, count 2 2006.257.07:34:49.74#ibcon#read 6, iclass 14, count 2 2006.257.07:34:49.74#ibcon#end of sib2, iclass 14, count 2 2006.257.07:34:49.74#ibcon#*after write, iclass 14, count 2 2006.257.07:34:49.74#ibcon#*before return 0, iclass 14, count 2 2006.257.07:34:49.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:49.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:49.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.07:34:49.74#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:49.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:49.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:49.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:49.86#ibcon#enter wrdev, iclass 14, count 0 2006.257.07:34:49.86#ibcon#first serial, iclass 14, count 0 2006.257.07:34:49.86#ibcon#enter sib2, iclass 14, count 0 2006.257.07:34:49.86#ibcon#flushed, iclass 14, count 0 2006.257.07:34:49.86#ibcon#about to write, iclass 14, count 0 2006.257.07:34:49.86#ibcon#wrote, iclass 14, count 0 2006.257.07:34:49.86#ibcon#about to read 3, iclass 14, count 0 2006.257.07:34:49.88#ibcon#read 3, iclass 14, count 0 2006.257.07:34:49.88#ibcon#about to read 4, iclass 14, count 0 2006.257.07:34:49.88#ibcon#read 4, iclass 14, count 0 2006.257.07:34:49.88#ibcon#about to read 5, iclass 14, count 0 2006.257.07:34:49.88#ibcon#read 5, iclass 14, count 0 2006.257.07:34:49.88#ibcon#about to read 6, iclass 14, count 0 2006.257.07:34:49.88#ibcon#read 6, iclass 14, count 0 2006.257.07:34:49.88#ibcon#end of sib2, iclass 14, count 0 2006.257.07:34:49.88#ibcon#*mode == 0, iclass 14, count 0 2006.257.07:34:49.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.07:34:49.88#ibcon#[25=USB\r\n] 2006.257.07:34:49.88#ibcon#*before write, iclass 14, count 0 2006.257.07:34:49.88#ibcon#enter sib2, iclass 14, count 0 2006.257.07:34:49.88#ibcon#flushed, iclass 14, count 0 2006.257.07:34:49.88#ibcon#about to write, iclass 14, count 0 2006.257.07:34:49.88#ibcon#wrote, iclass 14, count 0 2006.257.07:34:49.88#ibcon#about to read 3, iclass 14, count 0 2006.257.07:34:49.91#ibcon#read 3, iclass 14, count 0 2006.257.07:34:49.91#ibcon#about to read 4, iclass 14, count 0 2006.257.07:34:49.91#ibcon#read 4, iclass 14, count 0 2006.257.07:34:49.91#ibcon#about to read 5, iclass 14, count 0 2006.257.07:34:49.91#ibcon#read 5, iclass 14, count 0 2006.257.07:34:49.91#ibcon#about to read 6, iclass 14, count 0 2006.257.07:34:49.91#ibcon#read 6, iclass 14, count 0 2006.257.07:34:49.91#ibcon#end of sib2, iclass 14, count 0 2006.257.07:34:49.91#ibcon#*after write, iclass 14, count 0 2006.257.07:34:49.91#ibcon#*before return 0, iclass 14, count 0 2006.257.07:34:49.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:49.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:49.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.07:34:49.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.07:34:49.91$vck44/valo=6,814.99 2006.257.07:34:49.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.07:34:49.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.07:34:49.91#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:49.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:49.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:49.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:49.91#ibcon#enter wrdev, iclass 16, count 0 2006.257.07:34:49.91#ibcon#first serial, iclass 16, count 0 2006.257.07:34:49.91#ibcon#enter sib2, iclass 16, count 0 2006.257.07:34:49.91#ibcon#flushed, iclass 16, count 0 2006.257.07:34:49.91#ibcon#about to write, iclass 16, count 0 2006.257.07:34:49.91#ibcon#wrote, iclass 16, count 0 2006.257.07:34:49.91#ibcon#about to read 3, iclass 16, count 0 2006.257.07:34:49.93#ibcon#read 3, iclass 16, count 0 2006.257.07:34:49.93#ibcon#about to read 4, iclass 16, count 0 2006.257.07:34:49.93#ibcon#read 4, iclass 16, count 0 2006.257.07:34:49.93#ibcon#about to read 5, iclass 16, count 0 2006.257.07:34:49.93#ibcon#read 5, iclass 16, count 0 2006.257.07:34:49.93#ibcon#about to read 6, iclass 16, count 0 2006.257.07:34:49.93#ibcon#read 6, iclass 16, count 0 2006.257.07:34:49.93#ibcon#end of sib2, iclass 16, count 0 2006.257.07:34:49.93#ibcon#*mode == 0, iclass 16, count 0 2006.257.07:34:49.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.07:34:49.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.07:34:49.93#ibcon#*before write, iclass 16, count 0 2006.257.07:34:49.93#ibcon#enter sib2, iclass 16, count 0 2006.257.07:34:49.93#ibcon#flushed, iclass 16, count 0 2006.257.07:34:49.93#ibcon#about to write, iclass 16, count 0 2006.257.07:34:49.93#ibcon#wrote, iclass 16, count 0 2006.257.07:34:49.93#ibcon#about to read 3, iclass 16, count 0 2006.257.07:34:49.97#ibcon#read 3, iclass 16, count 0 2006.257.07:34:49.97#ibcon#about to read 4, iclass 16, count 0 2006.257.07:34:49.97#ibcon#read 4, iclass 16, count 0 2006.257.07:34:49.97#ibcon#about to read 5, iclass 16, count 0 2006.257.07:34:49.97#ibcon#read 5, iclass 16, count 0 2006.257.07:34:49.97#ibcon#about to read 6, iclass 16, count 0 2006.257.07:34:49.97#ibcon#read 6, iclass 16, count 0 2006.257.07:34:49.97#ibcon#end of sib2, iclass 16, count 0 2006.257.07:34:49.97#ibcon#*after write, iclass 16, count 0 2006.257.07:34:49.97#ibcon#*before return 0, iclass 16, count 0 2006.257.07:34:49.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:49.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:49.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.07:34:49.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.07:34:49.97$vck44/va=6,4 2006.257.07:34:49.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.07:34:49.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.07:34:49.97#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:49.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:50.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:50.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:50.03#ibcon#enter wrdev, iclass 18, count 2 2006.257.07:34:50.03#ibcon#first serial, iclass 18, count 2 2006.257.07:34:50.03#ibcon#enter sib2, iclass 18, count 2 2006.257.07:34:50.03#ibcon#flushed, iclass 18, count 2 2006.257.07:34:50.03#ibcon#about to write, iclass 18, count 2 2006.257.07:34:50.03#ibcon#wrote, iclass 18, count 2 2006.257.07:34:50.03#ibcon#about to read 3, iclass 18, count 2 2006.257.07:34:50.05#ibcon#read 3, iclass 18, count 2 2006.257.07:34:50.05#ibcon#about to read 4, iclass 18, count 2 2006.257.07:34:50.05#ibcon#read 4, iclass 18, count 2 2006.257.07:34:50.05#ibcon#about to read 5, iclass 18, count 2 2006.257.07:34:50.05#ibcon#read 5, iclass 18, count 2 2006.257.07:34:50.05#ibcon#about to read 6, iclass 18, count 2 2006.257.07:34:50.05#ibcon#read 6, iclass 18, count 2 2006.257.07:34:50.05#ibcon#end of sib2, iclass 18, count 2 2006.257.07:34:50.05#ibcon#*mode == 0, iclass 18, count 2 2006.257.07:34:50.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.07:34:50.05#ibcon#[25=AT06-04\r\n] 2006.257.07:34:50.05#ibcon#*before write, iclass 18, count 2 2006.257.07:34:50.05#ibcon#enter sib2, iclass 18, count 2 2006.257.07:34:50.05#ibcon#flushed, iclass 18, count 2 2006.257.07:34:50.05#ibcon#about to write, iclass 18, count 2 2006.257.07:34:50.05#ibcon#wrote, iclass 18, count 2 2006.257.07:34:50.05#ibcon#about to read 3, iclass 18, count 2 2006.257.07:34:50.08#ibcon#read 3, iclass 18, count 2 2006.257.07:34:50.08#ibcon#about to read 4, iclass 18, count 2 2006.257.07:34:50.08#ibcon#read 4, iclass 18, count 2 2006.257.07:34:50.08#ibcon#about to read 5, iclass 18, count 2 2006.257.07:34:50.08#ibcon#read 5, iclass 18, count 2 2006.257.07:34:50.08#ibcon#about to read 6, iclass 18, count 2 2006.257.07:34:50.08#ibcon#read 6, iclass 18, count 2 2006.257.07:34:50.08#ibcon#end of sib2, iclass 18, count 2 2006.257.07:34:50.08#ibcon#*after write, iclass 18, count 2 2006.257.07:34:50.08#ibcon#*before return 0, iclass 18, count 2 2006.257.07:34:50.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:50.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:50.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.07:34:50.08#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:50.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:50.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:50.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:50.20#ibcon#enter wrdev, iclass 18, count 0 2006.257.07:34:50.20#ibcon#first serial, iclass 18, count 0 2006.257.07:34:50.20#ibcon#enter sib2, iclass 18, count 0 2006.257.07:34:50.20#ibcon#flushed, iclass 18, count 0 2006.257.07:34:50.20#ibcon#about to write, iclass 18, count 0 2006.257.07:34:50.20#ibcon#wrote, iclass 18, count 0 2006.257.07:34:50.20#ibcon#about to read 3, iclass 18, count 0 2006.257.07:34:50.22#ibcon#read 3, iclass 18, count 0 2006.257.07:34:50.22#ibcon#about to read 4, iclass 18, count 0 2006.257.07:34:50.22#ibcon#read 4, iclass 18, count 0 2006.257.07:34:50.22#ibcon#about to read 5, iclass 18, count 0 2006.257.07:34:50.22#ibcon#read 5, iclass 18, count 0 2006.257.07:34:50.22#ibcon#about to read 6, iclass 18, count 0 2006.257.07:34:50.22#ibcon#read 6, iclass 18, count 0 2006.257.07:34:50.22#ibcon#end of sib2, iclass 18, count 0 2006.257.07:34:50.22#ibcon#*mode == 0, iclass 18, count 0 2006.257.07:34:50.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.07:34:50.22#ibcon#[25=USB\r\n] 2006.257.07:34:50.22#ibcon#*before write, iclass 18, count 0 2006.257.07:34:50.22#ibcon#enter sib2, iclass 18, count 0 2006.257.07:34:50.22#ibcon#flushed, iclass 18, count 0 2006.257.07:34:50.22#ibcon#about to write, iclass 18, count 0 2006.257.07:34:50.22#ibcon#wrote, iclass 18, count 0 2006.257.07:34:50.22#ibcon#about to read 3, iclass 18, count 0 2006.257.07:34:50.25#ibcon#read 3, iclass 18, count 0 2006.257.07:34:50.25#ibcon#about to read 4, iclass 18, count 0 2006.257.07:34:50.25#ibcon#read 4, iclass 18, count 0 2006.257.07:34:50.25#ibcon#about to read 5, iclass 18, count 0 2006.257.07:34:50.25#ibcon#read 5, iclass 18, count 0 2006.257.07:34:50.25#ibcon#about to read 6, iclass 18, count 0 2006.257.07:34:50.25#ibcon#read 6, iclass 18, count 0 2006.257.07:34:50.25#ibcon#end of sib2, iclass 18, count 0 2006.257.07:34:50.25#ibcon#*after write, iclass 18, count 0 2006.257.07:34:50.25#ibcon#*before return 0, iclass 18, count 0 2006.257.07:34:50.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:50.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:50.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.07:34:50.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.07:34:50.25$vck44/valo=7,864.99 2006.257.07:34:50.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.07:34:50.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.07:34:50.25#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:50.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:50.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:50.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:50.25#ibcon#enter wrdev, iclass 20, count 0 2006.257.07:34:50.25#ibcon#first serial, iclass 20, count 0 2006.257.07:34:50.25#ibcon#enter sib2, iclass 20, count 0 2006.257.07:34:50.25#ibcon#flushed, iclass 20, count 0 2006.257.07:34:50.25#ibcon#about to write, iclass 20, count 0 2006.257.07:34:50.25#ibcon#wrote, iclass 20, count 0 2006.257.07:34:50.25#ibcon#about to read 3, iclass 20, count 0 2006.257.07:34:50.27#ibcon#read 3, iclass 20, count 0 2006.257.07:34:50.27#ibcon#about to read 4, iclass 20, count 0 2006.257.07:34:50.27#ibcon#read 4, iclass 20, count 0 2006.257.07:34:50.27#ibcon#about to read 5, iclass 20, count 0 2006.257.07:34:50.27#ibcon#read 5, iclass 20, count 0 2006.257.07:34:50.27#ibcon#about to read 6, iclass 20, count 0 2006.257.07:34:50.27#ibcon#read 6, iclass 20, count 0 2006.257.07:34:50.27#ibcon#end of sib2, iclass 20, count 0 2006.257.07:34:50.27#ibcon#*mode == 0, iclass 20, count 0 2006.257.07:34:50.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.07:34:50.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.07:34:50.27#ibcon#*before write, iclass 20, count 0 2006.257.07:34:50.27#ibcon#enter sib2, iclass 20, count 0 2006.257.07:34:50.27#ibcon#flushed, iclass 20, count 0 2006.257.07:34:50.27#ibcon#about to write, iclass 20, count 0 2006.257.07:34:50.27#ibcon#wrote, iclass 20, count 0 2006.257.07:34:50.27#ibcon#about to read 3, iclass 20, count 0 2006.257.07:34:50.31#ibcon#read 3, iclass 20, count 0 2006.257.07:34:50.31#ibcon#about to read 4, iclass 20, count 0 2006.257.07:34:50.31#ibcon#read 4, iclass 20, count 0 2006.257.07:34:50.31#ibcon#about to read 5, iclass 20, count 0 2006.257.07:34:50.31#ibcon#read 5, iclass 20, count 0 2006.257.07:34:50.31#ibcon#about to read 6, iclass 20, count 0 2006.257.07:34:50.31#ibcon#read 6, iclass 20, count 0 2006.257.07:34:50.31#ibcon#end of sib2, iclass 20, count 0 2006.257.07:34:50.31#ibcon#*after write, iclass 20, count 0 2006.257.07:34:50.31#ibcon#*before return 0, iclass 20, count 0 2006.257.07:34:50.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:50.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:50.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.07:34:50.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.07:34:50.31$vck44/va=7,4 2006.257.07:34:50.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.07:34:50.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.07:34:50.31#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:50.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:50.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:50.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:50.37#ibcon#enter wrdev, iclass 22, count 2 2006.257.07:34:50.37#ibcon#first serial, iclass 22, count 2 2006.257.07:34:50.37#ibcon#enter sib2, iclass 22, count 2 2006.257.07:34:50.37#ibcon#flushed, iclass 22, count 2 2006.257.07:34:50.37#ibcon#about to write, iclass 22, count 2 2006.257.07:34:50.37#ibcon#wrote, iclass 22, count 2 2006.257.07:34:50.37#ibcon#about to read 3, iclass 22, count 2 2006.257.07:34:50.39#ibcon#read 3, iclass 22, count 2 2006.257.07:34:50.39#ibcon#about to read 4, iclass 22, count 2 2006.257.07:34:50.39#ibcon#read 4, iclass 22, count 2 2006.257.07:34:50.39#ibcon#about to read 5, iclass 22, count 2 2006.257.07:34:50.39#ibcon#read 5, iclass 22, count 2 2006.257.07:34:50.39#ibcon#about to read 6, iclass 22, count 2 2006.257.07:34:50.39#ibcon#read 6, iclass 22, count 2 2006.257.07:34:50.39#ibcon#end of sib2, iclass 22, count 2 2006.257.07:34:50.39#ibcon#*mode == 0, iclass 22, count 2 2006.257.07:34:50.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.07:34:50.39#ibcon#[25=AT07-04\r\n] 2006.257.07:34:50.39#ibcon#*before write, iclass 22, count 2 2006.257.07:34:50.39#ibcon#enter sib2, iclass 22, count 2 2006.257.07:34:50.39#ibcon#flushed, iclass 22, count 2 2006.257.07:34:50.39#ibcon#about to write, iclass 22, count 2 2006.257.07:34:50.39#ibcon#wrote, iclass 22, count 2 2006.257.07:34:50.39#ibcon#about to read 3, iclass 22, count 2 2006.257.07:34:50.42#ibcon#read 3, iclass 22, count 2 2006.257.07:34:50.42#ibcon#about to read 4, iclass 22, count 2 2006.257.07:34:50.42#ibcon#read 4, iclass 22, count 2 2006.257.07:34:50.42#ibcon#about to read 5, iclass 22, count 2 2006.257.07:34:50.42#ibcon#read 5, iclass 22, count 2 2006.257.07:34:50.42#ibcon#about to read 6, iclass 22, count 2 2006.257.07:34:50.42#ibcon#read 6, iclass 22, count 2 2006.257.07:34:50.42#ibcon#end of sib2, iclass 22, count 2 2006.257.07:34:50.42#ibcon#*after write, iclass 22, count 2 2006.257.07:34:50.42#ibcon#*before return 0, iclass 22, count 2 2006.257.07:34:50.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:50.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:50.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.07:34:50.42#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:50.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:50.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:50.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:50.54#ibcon#enter wrdev, iclass 22, count 0 2006.257.07:34:50.54#ibcon#first serial, iclass 22, count 0 2006.257.07:34:50.54#ibcon#enter sib2, iclass 22, count 0 2006.257.07:34:50.54#ibcon#flushed, iclass 22, count 0 2006.257.07:34:50.54#ibcon#about to write, iclass 22, count 0 2006.257.07:34:50.54#ibcon#wrote, iclass 22, count 0 2006.257.07:34:50.54#ibcon#about to read 3, iclass 22, count 0 2006.257.07:34:50.56#ibcon#read 3, iclass 22, count 0 2006.257.07:34:50.56#ibcon#about to read 4, iclass 22, count 0 2006.257.07:34:50.56#ibcon#read 4, iclass 22, count 0 2006.257.07:34:50.56#ibcon#about to read 5, iclass 22, count 0 2006.257.07:34:50.56#ibcon#read 5, iclass 22, count 0 2006.257.07:34:50.56#ibcon#about to read 6, iclass 22, count 0 2006.257.07:34:50.56#ibcon#read 6, iclass 22, count 0 2006.257.07:34:50.56#ibcon#end of sib2, iclass 22, count 0 2006.257.07:34:50.56#ibcon#*mode == 0, iclass 22, count 0 2006.257.07:34:50.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.07:34:50.56#ibcon#[25=USB\r\n] 2006.257.07:34:50.56#ibcon#*before write, iclass 22, count 0 2006.257.07:34:50.56#ibcon#enter sib2, iclass 22, count 0 2006.257.07:34:50.56#ibcon#flushed, iclass 22, count 0 2006.257.07:34:50.56#ibcon#about to write, iclass 22, count 0 2006.257.07:34:50.56#ibcon#wrote, iclass 22, count 0 2006.257.07:34:50.56#ibcon#about to read 3, iclass 22, count 0 2006.257.07:34:50.59#ibcon#read 3, iclass 22, count 0 2006.257.07:34:50.59#ibcon#about to read 4, iclass 22, count 0 2006.257.07:34:50.59#ibcon#read 4, iclass 22, count 0 2006.257.07:34:50.59#ibcon#about to read 5, iclass 22, count 0 2006.257.07:34:50.59#ibcon#read 5, iclass 22, count 0 2006.257.07:34:50.59#ibcon#about to read 6, iclass 22, count 0 2006.257.07:34:50.59#ibcon#read 6, iclass 22, count 0 2006.257.07:34:50.59#ibcon#end of sib2, iclass 22, count 0 2006.257.07:34:50.59#ibcon#*after write, iclass 22, count 0 2006.257.07:34:50.59#ibcon#*before return 0, iclass 22, count 0 2006.257.07:34:50.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:50.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:50.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.07:34:50.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.07:34:50.59$vck44/valo=8,884.99 2006.257.07:34:50.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.07:34:50.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.07:34:50.59#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:50.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:50.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:50.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:50.59#ibcon#enter wrdev, iclass 24, count 0 2006.257.07:34:50.59#ibcon#first serial, iclass 24, count 0 2006.257.07:34:50.59#ibcon#enter sib2, iclass 24, count 0 2006.257.07:34:50.59#ibcon#flushed, iclass 24, count 0 2006.257.07:34:50.59#ibcon#about to write, iclass 24, count 0 2006.257.07:34:50.59#ibcon#wrote, iclass 24, count 0 2006.257.07:34:50.59#ibcon#about to read 3, iclass 24, count 0 2006.257.07:34:50.61#ibcon#read 3, iclass 24, count 0 2006.257.07:34:50.61#ibcon#about to read 4, iclass 24, count 0 2006.257.07:34:50.61#ibcon#read 4, iclass 24, count 0 2006.257.07:34:50.61#ibcon#about to read 5, iclass 24, count 0 2006.257.07:34:50.61#ibcon#read 5, iclass 24, count 0 2006.257.07:34:50.61#ibcon#about to read 6, iclass 24, count 0 2006.257.07:34:50.61#ibcon#read 6, iclass 24, count 0 2006.257.07:34:50.61#ibcon#end of sib2, iclass 24, count 0 2006.257.07:34:50.61#ibcon#*mode == 0, iclass 24, count 0 2006.257.07:34:50.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.07:34:50.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.07:34:50.61#ibcon#*before write, iclass 24, count 0 2006.257.07:34:50.61#ibcon#enter sib2, iclass 24, count 0 2006.257.07:34:50.61#ibcon#flushed, iclass 24, count 0 2006.257.07:34:50.61#ibcon#about to write, iclass 24, count 0 2006.257.07:34:50.61#ibcon#wrote, iclass 24, count 0 2006.257.07:34:50.61#ibcon#about to read 3, iclass 24, count 0 2006.257.07:34:50.65#ibcon#read 3, iclass 24, count 0 2006.257.07:34:50.65#ibcon#about to read 4, iclass 24, count 0 2006.257.07:34:50.65#ibcon#read 4, iclass 24, count 0 2006.257.07:34:50.65#ibcon#about to read 5, iclass 24, count 0 2006.257.07:34:50.65#ibcon#read 5, iclass 24, count 0 2006.257.07:34:50.65#ibcon#about to read 6, iclass 24, count 0 2006.257.07:34:50.65#ibcon#read 6, iclass 24, count 0 2006.257.07:34:50.65#ibcon#end of sib2, iclass 24, count 0 2006.257.07:34:50.65#ibcon#*after write, iclass 24, count 0 2006.257.07:34:50.65#ibcon#*before return 0, iclass 24, count 0 2006.257.07:34:50.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:50.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:50.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.07:34:50.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.07:34:50.65$vck44/va=8,4 2006.257.07:34:50.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.07:34:50.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.07:34:50.65#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:50.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:34:50.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:34:50.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:34:50.71#ibcon#enter wrdev, iclass 26, count 2 2006.257.07:34:50.71#ibcon#first serial, iclass 26, count 2 2006.257.07:34:50.71#ibcon#enter sib2, iclass 26, count 2 2006.257.07:34:50.71#ibcon#flushed, iclass 26, count 2 2006.257.07:34:50.71#ibcon#about to write, iclass 26, count 2 2006.257.07:34:50.71#ibcon#wrote, iclass 26, count 2 2006.257.07:34:50.71#ibcon#about to read 3, iclass 26, count 2 2006.257.07:34:50.73#ibcon#read 3, iclass 26, count 2 2006.257.07:34:50.73#ibcon#about to read 4, iclass 26, count 2 2006.257.07:34:50.73#ibcon#read 4, iclass 26, count 2 2006.257.07:34:50.73#ibcon#about to read 5, iclass 26, count 2 2006.257.07:34:50.73#ibcon#read 5, iclass 26, count 2 2006.257.07:34:50.73#ibcon#about to read 6, iclass 26, count 2 2006.257.07:34:50.73#ibcon#read 6, iclass 26, count 2 2006.257.07:34:50.73#ibcon#end of sib2, iclass 26, count 2 2006.257.07:34:50.73#ibcon#*mode == 0, iclass 26, count 2 2006.257.07:34:50.73#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.07:34:50.73#ibcon#[25=AT08-04\r\n] 2006.257.07:34:50.73#ibcon#*before write, iclass 26, count 2 2006.257.07:34:50.73#ibcon#enter sib2, iclass 26, count 2 2006.257.07:34:50.73#ibcon#flushed, iclass 26, count 2 2006.257.07:34:50.73#ibcon#about to write, iclass 26, count 2 2006.257.07:34:50.73#ibcon#wrote, iclass 26, count 2 2006.257.07:34:50.73#ibcon#about to read 3, iclass 26, count 2 2006.257.07:34:50.76#ibcon#read 3, iclass 26, count 2 2006.257.07:34:50.76#ibcon#about to read 4, iclass 26, count 2 2006.257.07:34:50.76#ibcon#read 4, iclass 26, count 2 2006.257.07:34:50.76#ibcon#about to read 5, iclass 26, count 2 2006.257.07:34:50.76#ibcon#read 5, iclass 26, count 2 2006.257.07:34:50.76#ibcon#about to read 6, iclass 26, count 2 2006.257.07:34:50.76#ibcon#read 6, iclass 26, count 2 2006.257.07:34:50.76#ibcon#end of sib2, iclass 26, count 2 2006.257.07:34:50.76#ibcon#*after write, iclass 26, count 2 2006.257.07:34:50.76#ibcon#*before return 0, iclass 26, count 2 2006.257.07:34:50.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:34:50.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.07:34:50.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.07:34:50.76#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:50.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:34:50.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:34:50.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:34:50.88#ibcon#enter wrdev, iclass 26, count 0 2006.257.07:34:50.88#ibcon#first serial, iclass 26, count 0 2006.257.07:34:50.88#ibcon#enter sib2, iclass 26, count 0 2006.257.07:34:50.88#ibcon#flushed, iclass 26, count 0 2006.257.07:34:50.88#ibcon#about to write, iclass 26, count 0 2006.257.07:34:50.88#ibcon#wrote, iclass 26, count 0 2006.257.07:34:50.88#ibcon#about to read 3, iclass 26, count 0 2006.257.07:34:50.90#ibcon#read 3, iclass 26, count 0 2006.257.07:34:50.90#ibcon#about to read 4, iclass 26, count 0 2006.257.07:34:50.90#ibcon#read 4, iclass 26, count 0 2006.257.07:34:50.90#ibcon#about to read 5, iclass 26, count 0 2006.257.07:34:50.90#ibcon#read 5, iclass 26, count 0 2006.257.07:34:50.90#ibcon#about to read 6, iclass 26, count 0 2006.257.07:34:50.90#ibcon#read 6, iclass 26, count 0 2006.257.07:34:50.90#ibcon#end of sib2, iclass 26, count 0 2006.257.07:34:50.90#ibcon#*mode == 0, iclass 26, count 0 2006.257.07:34:50.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.07:34:50.90#ibcon#[25=USB\r\n] 2006.257.07:34:50.90#ibcon#*before write, iclass 26, count 0 2006.257.07:34:50.90#ibcon#enter sib2, iclass 26, count 0 2006.257.07:34:50.90#ibcon#flushed, iclass 26, count 0 2006.257.07:34:50.90#ibcon#about to write, iclass 26, count 0 2006.257.07:34:50.90#ibcon#wrote, iclass 26, count 0 2006.257.07:34:50.90#ibcon#about to read 3, iclass 26, count 0 2006.257.07:34:50.93#ibcon#read 3, iclass 26, count 0 2006.257.07:34:50.93#ibcon#about to read 4, iclass 26, count 0 2006.257.07:34:50.93#ibcon#read 4, iclass 26, count 0 2006.257.07:34:50.93#ibcon#about to read 5, iclass 26, count 0 2006.257.07:34:50.93#ibcon#read 5, iclass 26, count 0 2006.257.07:34:50.93#ibcon#about to read 6, iclass 26, count 0 2006.257.07:34:50.93#ibcon#read 6, iclass 26, count 0 2006.257.07:34:50.93#ibcon#end of sib2, iclass 26, count 0 2006.257.07:34:50.93#ibcon#*after write, iclass 26, count 0 2006.257.07:34:50.93#ibcon#*before return 0, iclass 26, count 0 2006.257.07:34:50.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:34:50.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.07:34:50.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.07:34:50.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.07:34:50.93$vck44/vblo=1,629.99 2006.257.07:34:50.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.07:34:50.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.07:34:50.93#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:50.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:50.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:50.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:50.93#ibcon#enter wrdev, iclass 28, count 0 2006.257.07:34:50.93#ibcon#first serial, iclass 28, count 0 2006.257.07:34:50.93#ibcon#enter sib2, iclass 28, count 0 2006.257.07:34:50.93#ibcon#flushed, iclass 28, count 0 2006.257.07:34:50.93#ibcon#about to write, iclass 28, count 0 2006.257.07:34:50.93#ibcon#wrote, iclass 28, count 0 2006.257.07:34:50.93#ibcon#about to read 3, iclass 28, count 0 2006.257.07:34:50.95#ibcon#read 3, iclass 28, count 0 2006.257.07:34:50.95#ibcon#about to read 4, iclass 28, count 0 2006.257.07:34:50.95#ibcon#read 4, iclass 28, count 0 2006.257.07:34:50.95#ibcon#about to read 5, iclass 28, count 0 2006.257.07:34:50.95#ibcon#read 5, iclass 28, count 0 2006.257.07:34:50.95#ibcon#about to read 6, iclass 28, count 0 2006.257.07:34:50.95#ibcon#read 6, iclass 28, count 0 2006.257.07:34:50.95#ibcon#end of sib2, iclass 28, count 0 2006.257.07:34:50.95#ibcon#*mode == 0, iclass 28, count 0 2006.257.07:34:50.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.07:34:50.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.07:34:50.95#ibcon#*before write, iclass 28, count 0 2006.257.07:34:50.95#ibcon#enter sib2, iclass 28, count 0 2006.257.07:34:50.95#ibcon#flushed, iclass 28, count 0 2006.257.07:34:50.95#ibcon#about to write, iclass 28, count 0 2006.257.07:34:50.95#ibcon#wrote, iclass 28, count 0 2006.257.07:34:50.95#ibcon#about to read 3, iclass 28, count 0 2006.257.07:34:50.99#ibcon#read 3, iclass 28, count 0 2006.257.07:34:50.99#ibcon#about to read 4, iclass 28, count 0 2006.257.07:34:50.99#ibcon#read 4, iclass 28, count 0 2006.257.07:34:50.99#ibcon#about to read 5, iclass 28, count 0 2006.257.07:34:50.99#ibcon#read 5, iclass 28, count 0 2006.257.07:34:50.99#ibcon#about to read 6, iclass 28, count 0 2006.257.07:34:50.99#ibcon#read 6, iclass 28, count 0 2006.257.07:34:50.99#ibcon#end of sib2, iclass 28, count 0 2006.257.07:34:50.99#ibcon#*after write, iclass 28, count 0 2006.257.07:34:50.99#ibcon#*before return 0, iclass 28, count 0 2006.257.07:34:50.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:50.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.07:34:50.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.07:34:50.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.07:34:50.99$vck44/vb=1,4 2006.257.07:34:50.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.07:34:50.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.07:34:50.99#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:50.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:50.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:50.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:50.99#ibcon#enter wrdev, iclass 30, count 2 2006.257.07:34:50.99#ibcon#first serial, iclass 30, count 2 2006.257.07:34:50.99#ibcon#enter sib2, iclass 30, count 2 2006.257.07:34:50.99#ibcon#flushed, iclass 30, count 2 2006.257.07:34:50.99#ibcon#about to write, iclass 30, count 2 2006.257.07:34:50.99#ibcon#wrote, iclass 30, count 2 2006.257.07:34:50.99#ibcon#about to read 3, iclass 30, count 2 2006.257.07:34:51.01#ibcon#read 3, iclass 30, count 2 2006.257.07:34:51.01#ibcon#about to read 4, iclass 30, count 2 2006.257.07:34:51.01#ibcon#read 4, iclass 30, count 2 2006.257.07:34:51.01#ibcon#about to read 5, iclass 30, count 2 2006.257.07:34:51.01#ibcon#read 5, iclass 30, count 2 2006.257.07:34:51.01#ibcon#about to read 6, iclass 30, count 2 2006.257.07:34:51.01#ibcon#read 6, iclass 30, count 2 2006.257.07:34:51.01#ibcon#end of sib2, iclass 30, count 2 2006.257.07:34:51.01#ibcon#*mode == 0, iclass 30, count 2 2006.257.07:34:51.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.07:34:51.01#ibcon#[27=AT01-04\r\n] 2006.257.07:34:51.01#ibcon#*before write, iclass 30, count 2 2006.257.07:34:51.01#ibcon#enter sib2, iclass 30, count 2 2006.257.07:34:51.01#ibcon#flushed, iclass 30, count 2 2006.257.07:34:51.01#ibcon#about to write, iclass 30, count 2 2006.257.07:34:51.01#ibcon#wrote, iclass 30, count 2 2006.257.07:34:51.01#ibcon#about to read 3, iclass 30, count 2 2006.257.07:34:51.04#ibcon#read 3, iclass 30, count 2 2006.257.07:34:51.04#ibcon#about to read 4, iclass 30, count 2 2006.257.07:34:51.04#ibcon#read 4, iclass 30, count 2 2006.257.07:34:51.04#ibcon#about to read 5, iclass 30, count 2 2006.257.07:34:51.04#ibcon#read 5, iclass 30, count 2 2006.257.07:34:51.04#ibcon#about to read 6, iclass 30, count 2 2006.257.07:34:51.04#ibcon#read 6, iclass 30, count 2 2006.257.07:34:51.04#ibcon#end of sib2, iclass 30, count 2 2006.257.07:34:51.04#ibcon#*after write, iclass 30, count 2 2006.257.07:34:51.04#ibcon#*before return 0, iclass 30, count 2 2006.257.07:34:51.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:51.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.07:34:51.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.07:34:51.04#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:51.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:51.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:51.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:51.16#ibcon#enter wrdev, iclass 30, count 0 2006.257.07:34:51.16#ibcon#first serial, iclass 30, count 0 2006.257.07:34:51.16#ibcon#enter sib2, iclass 30, count 0 2006.257.07:34:51.16#ibcon#flushed, iclass 30, count 0 2006.257.07:34:51.16#ibcon#about to write, iclass 30, count 0 2006.257.07:34:51.16#ibcon#wrote, iclass 30, count 0 2006.257.07:34:51.16#ibcon#about to read 3, iclass 30, count 0 2006.257.07:34:51.18#ibcon#read 3, iclass 30, count 0 2006.257.07:34:51.18#ibcon#about to read 4, iclass 30, count 0 2006.257.07:34:51.18#ibcon#read 4, iclass 30, count 0 2006.257.07:34:51.18#ibcon#about to read 5, iclass 30, count 0 2006.257.07:34:51.18#ibcon#read 5, iclass 30, count 0 2006.257.07:34:51.18#ibcon#about to read 6, iclass 30, count 0 2006.257.07:34:51.18#ibcon#read 6, iclass 30, count 0 2006.257.07:34:51.18#ibcon#end of sib2, iclass 30, count 0 2006.257.07:34:51.18#ibcon#*mode == 0, iclass 30, count 0 2006.257.07:34:51.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.07:34:51.18#ibcon#[27=USB\r\n] 2006.257.07:34:51.18#ibcon#*before write, iclass 30, count 0 2006.257.07:34:51.18#ibcon#enter sib2, iclass 30, count 0 2006.257.07:34:51.18#ibcon#flushed, iclass 30, count 0 2006.257.07:34:51.18#ibcon#about to write, iclass 30, count 0 2006.257.07:34:51.18#ibcon#wrote, iclass 30, count 0 2006.257.07:34:51.18#ibcon#about to read 3, iclass 30, count 0 2006.257.07:34:51.21#ibcon#read 3, iclass 30, count 0 2006.257.07:34:51.21#ibcon#about to read 4, iclass 30, count 0 2006.257.07:34:51.21#ibcon#read 4, iclass 30, count 0 2006.257.07:34:51.21#ibcon#about to read 5, iclass 30, count 0 2006.257.07:34:51.21#ibcon#read 5, iclass 30, count 0 2006.257.07:34:51.21#ibcon#about to read 6, iclass 30, count 0 2006.257.07:34:51.21#ibcon#read 6, iclass 30, count 0 2006.257.07:34:51.21#ibcon#end of sib2, iclass 30, count 0 2006.257.07:34:51.21#ibcon#*after write, iclass 30, count 0 2006.257.07:34:51.21#ibcon#*before return 0, iclass 30, count 0 2006.257.07:34:51.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:51.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.07:34:51.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.07:34:51.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.07:34:51.21$vck44/vblo=2,634.99 2006.257.07:34:51.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.07:34:51.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.07:34:51.21#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:51.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:51.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:51.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:51.21#ibcon#enter wrdev, iclass 32, count 0 2006.257.07:34:51.21#ibcon#first serial, iclass 32, count 0 2006.257.07:34:51.21#ibcon#enter sib2, iclass 32, count 0 2006.257.07:34:51.21#ibcon#flushed, iclass 32, count 0 2006.257.07:34:51.21#ibcon#about to write, iclass 32, count 0 2006.257.07:34:51.21#ibcon#wrote, iclass 32, count 0 2006.257.07:34:51.21#ibcon#about to read 3, iclass 32, count 0 2006.257.07:34:51.23#ibcon#read 3, iclass 32, count 0 2006.257.07:34:51.23#ibcon#about to read 4, iclass 32, count 0 2006.257.07:34:51.23#ibcon#read 4, iclass 32, count 0 2006.257.07:34:51.23#ibcon#about to read 5, iclass 32, count 0 2006.257.07:34:51.23#ibcon#read 5, iclass 32, count 0 2006.257.07:34:51.23#ibcon#about to read 6, iclass 32, count 0 2006.257.07:34:51.23#ibcon#read 6, iclass 32, count 0 2006.257.07:34:51.23#ibcon#end of sib2, iclass 32, count 0 2006.257.07:34:51.23#ibcon#*mode == 0, iclass 32, count 0 2006.257.07:34:51.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.07:34:51.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.07:34:51.23#ibcon#*before write, iclass 32, count 0 2006.257.07:34:51.23#ibcon#enter sib2, iclass 32, count 0 2006.257.07:34:51.23#ibcon#flushed, iclass 32, count 0 2006.257.07:34:51.23#ibcon#about to write, iclass 32, count 0 2006.257.07:34:51.23#ibcon#wrote, iclass 32, count 0 2006.257.07:34:51.23#ibcon#about to read 3, iclass 32, count 0 2006.257.07:34:51.27#ibcon#read 3, iclass 32, count 0 2006.257.07:34:51.27#ibcon#about to read 4, iclass 32, count 0 2006.257.07:34:51.27#ibcon#read 4, iclass 32, count 0 2006.257.07:34:51.27#ibcon#about to read 5, iclass 32, count 0 2006.257.07:34:51.27#ibcon#read 5, iclass 32, count 0 2006.257.07:34:51.27#ibcon#about to read 6, iclass 32, count 0 2006.257.07:34:51.27#ibcon#read 6, iclass 32, count 0 2006.257.07:34:51.27#ibcon#end of sib2, iclass 32, count 0 2006.257.07:34:51.27#ibcon#*after write, iclass 32, count 0 2006.257.07:34:51.27#ibcon#*before return 0, iclass 32, count 0 2006.257.07:34:51.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:51.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.07:34:51.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.07:34:51.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.07:34:51.27$vck44/vb=2,5 2006.257.07:34:51.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.07:34:51.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.07:34:51.27#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:51.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:51.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:51.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:51.33#ibcon#enter wrdev, iclass 34, count 2 2006.257.07:34:51.33#ibcon#first serial, iclass 34, count 2 2006.257.07:34:51.33#ibcon#enter sib2, iclass 34, count 2 2006.257.07:34:51.33#ibcon#flushed, iclass 34, count 2 2006.257.07:34:51.33#ibcon#about to write, iclass 34, count 2 2006.257.07:34:51.33#ibcon#wrote, iclass 34, count 2 2006.257.07:34:51.33#ibcon#about to read 3, iclass 34, count 2 2006.257.07:34:51.35#ibcon#read 3, iclass 34, count 2 2006.257.07:34:51.35#ibcon#about to read 4, iclass 34, count 2 2006.257.07:34:51.35#ibcon#read 4, iclass 34, count 2 2006.257.07:34:51.35#ibcon#about to read 5, iclass 34, count 2 2006.257.07:34:51.35#ibcon#read 5, iclass 34, count 2 2006.257.07:34:51.35#ibcon#about to read 6, iclass 34, count 2 2006.257.07:34:51.35#ibcon#read 6, iclass 34, count 2 2006.257.07:34:51.35#ibcon#end of sib2, iclass 34, count 2 2006.257.07:34:51.35#ibcon#*mode == 0, iclass 34, count 2 2006.257.07:34:51.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.07:34:51.35#ibcon#[27=AT02-05\r\n] 2006.257.07:34:51.35#ibcon#*before write, iclass 34, count 2 2006.257.07:34:51.35#ibcon#enter sib2, iclass 34, count 2 2006.257.07:34:51.35#ibcon#flushed, iclass 34, count 2 2006.257.07:34:51.35#ibcon#about to write, iclass 34, count 2 2006.257.07:34:51.35#ibcon#wrote, iclass 34, count 2 2006.257.07:34:51.35#ibcon#about to read 3, iclass 34, count 2 2006.257.07:34:51.38#ibcon#read 3, iclass 34, count 2 2006.257.07:34:51.38#ibcon#about to read 4, iclass 34, count 2 2006.257.07:34:51.38#ibcon#read 4, iclass 34, count 2 2006.257.07:34:51.38#ibcon#about to read 5, iclass 34, count 2 2006.257.07:34:51.38#ibcon#read 5, iclass 34, count 2 2006.257.07:34:51.38#ibcon#about to read 6, iclass 34, count 2 2006.257.07:34:51.38#ibcon#read 6, iclass 34, count 2 2006.257.07:34:51.38#ibcon#end of sib2, iclass 34, count 2 2006.257.07:34:51.38#ibcon#*after write, iclass 34, count 2 2006.257.07:34:51.38#ibcon#*before return 0, iclass 34, count 2 2006.257.07:34:51.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:51.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.07:34:51.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.07:34:51.38#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:51.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:51.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:51.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:51.50#ibcon#enter wrdev, iclass 34, count 0 2006.257.07:34:51.50#ibcon#first serial, iclass 34, count 0 2006.257.07:34:51.50#ibcon#enter sib2, iclass 34, count 0 2006.257.07:34:51.50#ibcon#flushed, iclass 34, count 0 2006.257.07:34:51.50#ibcon#about to write, iclass 34, count 0 2006.257.07:34:51.50#ibcon#wrote, iclass 34, count 0 2006.257.07:34:51.50#ibcon#about to read 3, iclass 34, count 0 2006.257.07:34:51.52#ibcon#read 3, iclass 34, count 0 2006.257.07:34:51.52#ibcon#about to read 4, iclass 34, count 0 2006.257.07:34:51.52#ibcon#read 4, iclass 34, count 0 2006.257.07:34:51.52#ibcon#about to read 5, iclass 34, count 0 2006.257.07:34:51.52#ibcon#read 5, iclass 34, count 0 2006.257.07:34:51.52#ibcon#about to read 6, iclass 34, count 0 2006.257.07:34:51.52#ibcon#read 6, iclass 34, count 0 2006.257.07:34:51.52#ibcon#end of sib2, iclass 34, count 0 2006.257.07:34:51.52#ibcon#*mode == 0, iclass 34, count 0 2006.257.07:34:51.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.07:34:51.52#ibcon#[27=USB\r\n] 2006.257.07:34:51.52#ibcon#*before write, iclass 34, count 0 2006.257.07:34:51.52#ibcon#enter sib2, iclass 34, count 0 2006.257.07:34:51.52#ibcon#flushed, iclass 34, count 0 2006.257.07:34:51.52#ibcon#about to write, iclass 34, count 0 2006.257.07:34:51.52#ibcon#wrote, iclass 34, count 0 2006.257.07:34:51.52#ibcon#about to read 3, iclass 34, count 0 2006.257.07:34:51.55#ibcon#read 3, iclass 34, count 0 2006.257.07:34:51.55#ibcon#about to read 4, iclass 34, count 0 2006.257.07:34:51.55#ibcon#read 4, iclass 34, count 0 2006.257.07:34:51.55#ibcon#about to read 5, iclass 34, count 0 2006.257.07:34:51.55#ibcon#read 5, iclass 34, count 0 2006.257.07:34:51.55#ibcon#about to read 6, iclass 34, count 0 2006.257.07:34:51.55#ibcon#read 6, iclass 34, count 0 2006.257.07:34:51.55#ibcon#end of sib2, iclass 34, count 0 2006.257.07:34:51.55#ibcon#*after write, iclass 34, count 0 2006.257.07:34:51.55#ibcon#*before return 0, iclass 34, count 0 2006.257.07:34:51.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:51.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.07:34:51.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.07:34:51.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.07:34:51.55$vck44/vblo=3,649.99 2006.257.07:34:51.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.07:34:51.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.07:34:51.55#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:51.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:51.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:51.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:51.55#ibcon#enter wrdev, iclass 36, count 0 2006.257.07:34:51.55#ibcon#first serial, iclass 36, count 0 2006.257.07:34:51.55#ibcon#enter sib2, iclass 36, count 0 2006.257.07:34:51.55#ibcon#flushed, iclass 36, count 0 2006.257.07:34:51.55#ibcon#about to write, iclass 36, count 0 2006.257.07:34:51.55#ibcon#wrote, iclass 36, count 0 2006.257.07:34:51.55#ibcon#about to read 3, iclass 36, count 0 2006.257.07:34:51.57#ibcon#read 3, iclass 36, count 0 2006.257.07:34:51.57#ibcon#about to read 4, iclass 36, count 0 2006.257.07:34:51.57#ibcon#read 4, iclass 36, count 0 2006.257.07:34:51.57#ibcon#about to read 5, iclass 36, count 0 2006.257.07:34:51.57#ibcon#read 5, iclass 36, count 0 2006.257.07:34:51.57#ibcon#about to read 6, iclass 36, count 0 2006.257.07:34:51.57#ibcon#read 6, iclass 36, count 0 2006.257.07:34:51.57#ibcon#end of sib2, iclass 36, count 0 2006.257.07:34:51.57#ibcon#*mode == 0, iclass 36, count 0 2006.257.07:34:51.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.07:34:51.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.07:34:51.57#ibcon#*before write, iclass 36, count 0 2006.257.07:34:51.57#ibcon#enter sib2, iclass 36, count 0 2006.257.07:34:51.57#ibcon#flushed, iclass 36, count 0 2006.257.07:34:51.57#ibcon#about to write, iclass 36, count 0 2006.257.07:34:51.57#ibcon#wrote, iclass 36, count 0 2006.257.07:34:51.57#ibcon#about to read 3, iclass 36, count 0 2006.257.07:34:51.61#ibcon#read 3, iclass 36, count 0 2006.257.07:34:51.61#ibcon#about to read 4, iclass 36, count 0 2006.257.07:34:51.61#ibcon#read 4, iclass 36, count 0 2006.257.07:34:51.61#ibcon#about to read 5, iclass 36, count 0 2006.257.07:34:51.61#ibcon#read 5, iclass 36, count 0 2006.257.07:34:51.61#ibcon#about to read 6, iclass 36, count 0 2006.257.07:34:51.61#ibcon#read 6, iclass 36, count 0 2006.257.07:34:51.61#ibcon#end of sib2, iclass 36, count 0 2006.257.07:34:51.61#ibcon#*after write, iclass 36, count 0 2006.257.07:34:51.61#ibcon#*before return 0, iclass 36, count 0 2006.257.07:34:51.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:51.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:34:51.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.07:34:51.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.07:34:51.61$vck44/vb=3,4 2006.257.07:34:51.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.07:34:51.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.07:34:51.61#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:51.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:51.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:51.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:51.67#ibcon#enter wrdev, iclass 38, count 2 2006.257.07:34:51.67#ibcon#first serial, iclass 38, count 2 2006.257.07:34:51.67#ibcon#enter sib2, iclass 38, count 2 2006.257.07:34:51.67#ibcon#flushed, iclass 38, count 2 2006.257.07:34:51.67#ibcon#about to write, iclass 38, count 2 2006.257.07:34:51.67#ibcon#wrote, iclass 38, count 2 2006.257.07:34:51.67#ibcon#about to read 3, iclass 38, count 2 2006.257.07:34:51.69#ibcon#read 3, iclass 38, count 2 2006.257.07:34:51.69#ibcon#about to read 4, iclass 38, count 2 2006.257.07:34:51.69#ibcon#read 4, iclass 38, count 2 2006.257.07:34:51.69#ibcon#about to read 5, iclass 38, count 2 2006.257.07:34:51.69#ibcon#read 5, iclass 38, count 2 2006.257.07:34:51.69#ibcon#about to read 6, iclass 38, count 2 2006.257.07:34:51.69#ibcon#read 6, iclass 38, count 2 2006.257.07:34:51.69#ibcon#end of sib2, iclass 38, count 2 2006.257.07:34:51.69#ibcon#*mode == 0, iclass 38, count 2 2006.257.07:34:51.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.07:34:51.69#ibcon#[27=AT03-04\r\n] 2006.257.07:34:51.69#ibcon#*before write, iclass 38, count 2 2006.257.07:34:51.69#ibcon#enter sib2, iclass 38, count 2 2006.257.07:34:51.69#ibcon#flushed, iclass 38, count 2 2006.257.07:34:51.69#ibcon#about to write, iclass 38, count 2 2006.257.07:34:51.69#ibcon#wrote, iclass 38, count 2 2006.257.07:34:51.69#ibcon#about to read 3, iclass 38, count 2 2006.257.07:34:51.72#ibcon#read 3, iclass 38, count 2 2006.257.07:34:51.72#ibcon#about to read 4, iclass 38, count 2 2006.257.07:34:51.72#ibcon#read 4, iclass 38, count 2 2006.257.07:34:51.72#ibcon#about to read 5, iclass 38, count 2 2006.257.07:34:51.72#ibcon#read 5, iclass 38, count 2 2006.257.07:34:51.72#ibcon#about to read 6, iclass 38, count 2 2006.257.07:34:51.72#ibcon#read 6, iclass 38, count 2 2006.257.07:34:51.72#ibcon#end of sib2, iclass 38, count 2 2006.257.07:34:51.72#ibcon#*after write, iclass 38, count 2 2006.257.07:34:51.72#ibcon#*before return 0, iclass 38, count 2 2006.257.07:34:51.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:51.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.07:34:51.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.07:34:51.72#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:51.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:51.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:51.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:51.84#ibcon#enter wrdev, iclass 38, count 0 2006.257.07:34:51.84#ibcon#first serial, iclass 38, count 0 2006.257.07:34:51.84#ibcon#enter sib2, iclass 38, count 0 2006.257.07:34:51.84#ibcon#flushed, iclass 38, count 0 2006.257.07:34:51.84#ibcon#about to write, iclass 38, count 0 2006.257.07:34:51.84#ibcon#wrote, iclass 38, count 0 2006.257.07:34:51.84#ibcon#about to read 3, iclass 38, count 0 2006.257.07:34:51.86#ibcon#read 3, iclass 38, count 0 2006.257.07:34:51.86#ibcon#about to read 4, iclass 38, count 0 2006.257.07:34:51.86#ibcon#read 4, iclass 38, count 0 2006.257.07:34:51.86#ibcon#about to read 5, iclass 38, count 0 2006.257.07:34:51.86#ibcon#read 5, iclass 38, count 0 2006.257.07:34:51.86#ibcon#about to read 6, iclass 38, count 0 2006.257.07:34:51.86#ibcon#read 6, iclass 38, count 0 2006.257.07:34:51.86#ibcon#end of sib2, iclass 38, count 0 2006.257.07:34:51.86#ibcon#*mode == 0, iclass 38, count 0 2006.257.07:34:51.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.07:34:51.86#ibcon#[27=USB\r\n] 2006.257.07:34:51.86#ibcon#*before write, iclass 38, count 0 2006.257.07:34:51.86#ibcon#enter sib2, iclass 38, count 0 2006.257.07:34:51.86#ibcon#flushed, iclass 38, count 0 2006.257.07:34:51.86#ibcon#about to write, iclass 38, count 0 2006.257.07:34:51.86#ibcon#wrote, iclass 38, count 0 2006.257.07:34:51.86#ibcon#about to read 3, iclass 38, count 0 2006.257.07:34:51.89#ibcon#read 3, iclass 38, count 0 2006.257.07:34:51.89#ibcon#about to read 4, iclass 38, count 0 2006.257.07:34:51.89#ibcon#read 4, iclass 38, count 0 2006.257.07:34:51.89#ibcon#about to read 5, iclass 38, count 0 2006.257.07:34:51.89#ibcon#read 5, iclass 38, count 0 2006.257.07:34:51.89#ibcon#about to read 6, iclass 38, count 0 2006.257.07:34:51.89#ibcon#read 6, iclass 38, count 0 2006.257.07:34:51.89#ibcon#end of sib2, iclass 38, count 0 2006.257.07:34:51.89#ibcon#*after write, iclass 38, count 0 2006.257.07:34:51.89#ibcon#*before return 0, iclass 38, count 0 2006.257.07:34:51.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:51.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.07:34:51.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.07:34:51.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.07:34:51.89$vck44/vblo=4,679.99 2006.257.07:34:51.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.07:34:51.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.07:34:51.89#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:51.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:34:51.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:34:51.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:34:51.89#ibcon#enter wrdev, iclass 40, count 0 2006.257.07:34:51.89#ibcon#first serial, iclass 40, count 0 2006.257.07:34:51.89#ibcon#enter sib2, iclass 40, count 0 2006.257.07:34:51.89#ibcon#flushed, iclass 40, count 0 2006.257.07:34:51.89#ibcon#about to write, iclass 40, count 0 2006.257.07:34:51.89#ibcon#wrote, iclass 40, count 0 2006.257.07:34:51.89#ibcon#about to read 3, iclass 40, count 0 2006.257.07:34:51.91#ibcon#read 3, iclass 40, count 0 2006.257.07:34:51.91#ibcon#about to read 4, iclass 40, count 0 2006.257.07:34:51.91#ibcon#read 4, iclass 40, count 0 2006.257.07:34:51.91#ibcon#about to read 5, iclass 40, count 0 2006.257.07:34:51.91#ibcon#read 5, iclass 40, count 0 2006.257.07:34:51.91#ibcon#about to read 6, iclass 40, count 0 2006.257.07:34:51.91#ibcon#read 6, iclass 40, count 0 2006.257.07:34:51.91#ibcon#end of sib2, iclass 40, count 0 2006.257.07:34:51.91#ibcon#*mode == 0, iclass 40, count 0 2006.257.07:34:51.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.07:34:51.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.07:34:51.91#ibcon#*before write, iclass 40, count 0 2006.257.07:34:51.91#ibcon#enter sib2, iclass 40, count 0 2006.257.07:34:51.91#ibcon#flushed, iclass 40, count 0 2006.257.07:34:51.91#ibcon#about to write, iclass 40, count 0 2006.257.07:34:51.91#ibcon#wrote, iclass 40, count 0 2006.257.07:34:51.91#ibcon#about to read 3, iclass 40, count 0 2006.257.07:34:51.95#ibcon#read 3, iclass 40, count 0 2006.257.07:34:51.95#ibcon#about to read 4, iclass 40, count 0 2006.257.07:34:51.95#ibcon#read 4, iclass 40, count 0 2006.257.07:34:51.95#ibcon#about to read 5, iclass 40, count 0 2006.257.07:34:51.95#ibcon#read 5, iclass 40, count 0 2006.257.07:34:51.95#ibcon#about to read 6, iclass 40, count 0 2006.257.07:34:51.95#ibcon#read 6, iclass 40, count 0 2006.257.07:34:51.95#ibcon#end of sib2, iclass 40, count 0 2006.257.07:34:51.95#ibcon#*after write, iclass 40, count 0 2006.257.07:34:51.95#ibcon#*before return 0, iclass 40, count 0 2006.257.07:34:51.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:34:51.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.07:34:51.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.07:34:51.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.07:34:51.95$vck44/vb=4,5 2006.257.07:34:51.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.07:34:51.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.07:34:51.95#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:51.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:34:52.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:34:52.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:34:52.01#ibcon#enter wrdev, iclass 4, count 2 2006.257.07:34:52.01#ibcon#first serial, iclass 4, count 2 2006.257.07:34:52.01#ibcon#enter sib2, iclass 4, count 2 2006.257.07:34:52.01#ibcon#flushed, iclass 4, count 2 2006.257.07:34:52.01#ibcon#about to write, iclass 4, count 2 2006.257.07:34:52.01#ibcon#wrote, iclass 4, count 2 2006.257.07:34:52.01#ibcon#about to read 3, iclass 4, count 2 2006.257.07:34:52.03#ibcon#read 3, iclass 4, count 2 2006.257.07:34:52.03#ibcon#about to read 4, iclass 4, count 2 2006.257.07:34:52.03#ibcon#read 4, iclass 4, count 2 2006.257.07:34:52.03#ibcon#about to read 5, iclass 4, count 2 2006.257.07:34:52.03#ibcon#read 5, iclass 4, count 2 2006.257.07:34:52.03#ibcon#about to read 6, iclass 4, count 2 2006.257.07:34:52.03#ibcon#read 6, iclass 4, count 2 2006.257.07:34:52.03#ibcon#end of sib2, iclass 4, count 2 2006.257.07:34:52.03#ibcon#*mode == 0, iclass 4, count 2 2006.257.07:34:52.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.07:34:52.03#ibcon#[27=AT04-05\r\n] 2006.257.07:34:52.03#ibcon#*before write, iclass 4, count 2 2006.257.07:34:52.03#ibcon#enter sib2, iclass 4, count 2 2006.257.07:34:52.03#ibcon#flushed, iclass 4, count 2 2006.257.07:34:52.03#ibcon#about to write, iclass 4, count 2 2006.257.07:34:52.03#ibcon#wrote, iclass 4, count 2 2006.257.07:34:52.03#ibcon#about to read 3, iclass 4, count 2 2006.257.07:34:52.06#ibcon#read 3, iclass 4, count 2 2006.257.07:34:52.06#ibcon#about to read 4, iclass 4, count 2 2006.257.07:34:52.06#ibcon#read 4, iclass 4, count 2 2006.257.07:34:52.06#ibcon#about to read 5, iclass 4, count 2 2006.257.07:34:52.06#ibcon#read 5, iclass 4, count 2 2006.257.07:34:52.06#ibcon#about to read 6, iclass 4, count 2 2006.257.07:34:52.06#ibcon#read 6, iclass 4, count 2 2006.257.07:34:52.06#ibcon#end of sib2, iclass 4, count 2 2006.257.07:34:52.06#ibcon#*after write, iclass 4, count 2 2006.257.07:34:52.06#ibcon#*before return 0, iclass 4, count 2 2006.257.07:34:52.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:34:52.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.07:34:52.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.07:34:52.06#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:52.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:34:52.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:34:52.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:34:52.18#ibcon#enter wrdev, iclass 4, count 0 2006.257.07:34:52.18#ibcon#first serial, iclass 4, count 0 2006.257.07:34:52.18#ibcon#enter sib2, iclass 4, count 0 2006.257.07:34:52.18#ibcon#flushed, iclass 4, count 0 2006.257.07:34:52.18#ibcon#about to write, iclass 4, count 0 2006.257.07:34:52.18#ibcon#wrote, iclass 4, count 0 2006.257.07:34:52.18#ibcon#about to read 3, iclass 4, count 0 2006.257.07:34:52.20#ibcon#read 3, iclass 4, count 0 2006.257.07:34:52.20#ibcon#about to read 4, iclass 4, count 0 2006.257.07:34:52.20#ibcon#read 4, iclass 4, count 0 2006.257.07:34:52.20#ibcon#about to read 5, iclass 4, count 0 2006.257.07:34:52.20#ibcon#read 5, iclass 4, count 0 2006.257.07:34:52.20#ibcon#about to read 6, iclass 4, count 0 2006.257.07:34:52.20#ibcon#read 6, iclass 4, count 0 2006.257.07:34:52.20#ibcon#end of sib2, iclass 4, count 0 2006.257.07:34:52.20#ibcon#*mode == 0, iclass 4, count 0 2006.257.07:34:52.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.07:34:52.20#ibcon#[27=USB\r\n] 2006.257.07:34:52.20#ibcon#*before write, iclass 4, count 0 2006.257.07:34:52.20#ibcon#enter sib2, iclass 4, count 0 2006.257.07:34:52.20#ibcon#flushed, iclass 4, count 0 2006.257.07:34:52.20#ibcon#about to write, iclass 4, count 0 2006.257.07:34:52.20#ibcon#wrote, iclass 4, count 0 2006.257.07:34:52.20#ibcon#about to read 3, iclass 4, count 0 2006.257.07:34:52.23#ibcon#read 3, iclass 4, count 0 2006.257.07:34:52.23#ibcon#about to read 4, iclass 4, count 0 2006.257.07:34:52.23#ibcon#read 4, iclass 4, count 0 2006.257.07:34:52.23#ibcon#about to read 5, iclass 4, count 0 2006.257.07:34:52.23#ibcon#read 5, iclass 4, count 0 2006.257.07:34:52.23#ibcon#about to read 6, iclass 4, count 0 2006.257.07:34:52.23#ibcon#read 6, iclass 4, count 0 2006.257.07:34:52.23#ibcon#end of sib2, iclass 4, count 0 2006.257.07:34:52.23#ibcon#*after write, iclass 4, count 0 2006.257.07:34:52.23#ibcon#*before return 0, iclass 4, count 0 2006.257.07:34:52.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:34:52.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.07:34:52.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.07:34:52.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.07:34:52.23$vck44/vblo=5,709.99 2006.257.07:34:52.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.07:34:52.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.07:34:52.23#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:52.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:34:52.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:34:52.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:34:52.23#ibcon#enter wrdev, iclass 6, count 0 2006.257.07:34:52.23#ibcon#first serial, iclass 6, count 0 2006.257.07:34:52.23#ibcon#enter sib2, iclass 6, count 0 2006.257.07:34:52.23#ibcon#flushed, iclass 6, count 0 2006.257.07:34:52.23#ibcon#about to write, iclass 6, count 0 2006.257.07:34:52.23#ibcon#wrote, iclass 6, count 0 2006.257.07:34:52.23#ibcon#about to read 3, iclass 6, count 0 2006.257.07:34:52.25#ibcon#read 3, iclass 6, count 0 2006.257.07:34:52.25#ibcon#about to read 4, iclass 6, count 0 2006.257.07:34:52.25#ibcon#read 4, iclass 6, count 0 2006.257.07:34:52.25#ibcon#about to read 5, iclass 6, count 0 2006.257.07:34:52.25#ibcon#read 5, iclass 6, count 0 2006.257.07:34:52.25#ibcon#about to read 6, iclass 6, count 0 2006.257.07:34:52.25#ibcon#read 6, iclass 6, count 0 2006.257.07:34:52.25#ibcon#end of sib2, iclass 6, count 0 2006.257.07:34:52.25#ibcon#*mode == 0, iclass 6, count 0 2006.257.07:34:52.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.07:34:52.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.07:34:52.25#ibcon#*before write, iclass 6, count 0 2006.257.07:34:52.25#ibcon#enter sib2, iclass 6, count 0 2006.257.07:34:52.25#ibcon#flushed, iclass 6, count 0 2006.257.07:34:52.25#ibcon#about to write, iclass 6, count 0 2006.257.07:34:52.25#ibcon#wrote, iclass 6, count 0 2006.257.07:34:52.25#ibcon#about to read 3, iclass 6, count 0 2006.257.07:34:52.29#ibcon#read 3, iclass 6, count 0 2006.257.07:34:52.29#ibcon#about to read 4, iclass 6, count 0 2006.257.07:34:52.29#ibcon#read 4, iclass 6, count 0 2006.257.07:34:52.29#ibcon#about to read 5, iclass 6, count 0 2006.257.07:34:52.29#ibcon#read 5, iclass 6, count 0 2006.257.07:34:52.29#ibcon#about to read 6, iclass 6, count 0 2006.257.07:34:52.29#ibcon#read 6, iclass 6, count 0 2006.257.07:34:52.29#ibcon#end of sib2, iclass 6, count 0 2006.257.07:34:52.29#ibcon#*after write, iclass 6, count 0 2006.257.07:34:52.29#ibcon#*before return 0, iclass 6, count 0 2006.257.07:34:52.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:34:52.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.07:34:52.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.07:34:52.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.07:34:52.29$vck44/vb=5,4 2006.257.07:34:52.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.07:34:52.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.07:34:52.29#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:52.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:34:52.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:34:52.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:34:52.35#ibcon#enter wrdev, iclass 10, count 2 2006.257.07:34:52.35#ibcon#first serial, iclass 10, count 2 2006.257.07:34:52.35#ibcon#enter sib2, iclass 10, count 2 2006.257.07:34:52.35#ibcon#flushed, iclass 10, count 2 2006.257.07:34:52.35#ibcon#about to write, iclass 10, count 2 2006.257.07:34:52.35#ibcon#wrote, iclass 10, count 2 2006.257.07:34:52.35#ibcon#about to read 3, iclass 10, count 2 2006.257.07:34:52.37#ibcon#read 3, iclass 10, count 2 2006.257.07:34:52.37#ibcon#about to read 4, iclass 10, count 2 2006.257.07:34:52.37#ibcon#read 4, iclass 10, count 2 2006.257.07:34:52.37#ibcon#about to read 5, iclass 10, count 2 2006.257.07:34:52.37#ibcon#read 5, iclass 10, count 2 2006.257.07:34:52.37#ibcon#about to read 6, iclass 10, count 2 2006.257.07:34:52.37#ibcon#read 6, iclass 10, count 2 2006.257.07:34:52.37#ibcon#end of sib2, iclass 10, count 2 2006.257.07:34:52.37#ibcon#*mode == 0, iclass 10, count 2 2006.257.07:34:52.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.07:34:52.37#ibcon#[27=AT05-04\r\n] 2006.257.07:34:52.37#ibcon#*before write, iclass 10, count 2 2006.257.07:34:52.37#ibcon#enter sib2, iclass 10, count 2 2006.257.07:34:52.37#ibcon#flushed, iclass 10, count 2 2006.257.07:34:52.37#ibcon#about to write, iclass 10, count 2 2006.257.07:34:52.37#ibcon#wrote, iclass 10, count 2 2006.257.07:34:52.37#ibcon#about to read 3, iclass 10, count 2 2006.257.07:34:52.40#ibcon#read 3, iclass 10, count 2 2006.257.07:34:52.40#ibcon#about to read 4, iclass 10, count 2 2006.257.07:34:52.40#ibcon#read 4, iclass 10, count 2 2006.257.07:34:52.40#ibcon#about to read 5, iclass 10, count 2 2006.257.07:34:52.40#ibcon#read 5, iclass 10, count 2 2006.257.07:34:52.40#ibcon#about to read 6, iclass 10, count 2 2006.257.07:34:52.40#ibcon#read 6, iclass 10, count 2 2006.257.07:34:52.40#ibcon#end of sib2, iclass 10, count 2 2006.257.07:34:52.40#ibcon#*after write, iclass 10, count 2 2006.257.07:34:52.40#ibcon#*before return 0, iclass 10, count 2 2006.257.07:34:52.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:34:52.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:34:52.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.07:34:52.40#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:52.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:34:52.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:34:52.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:34:52.52#ibcon#enter wrdev, iclass 10, count 0 2006.257.07:34:52.52#ibcon#first serial, iclass 10, count 0 2006.257.07:34:52.52#ibcon#enter sib2, iclass 10, count 0 2006.257.07:34:52.52#ibcon#flushed, iclass 10, count 0 2006.257.07:34:52.52#ibcon#about to write, iclass 10, count 0 2006.257.07:34:52.52#ibcon#wrote, iclass 10, count 0 2006.257.07:34:52.52#ibcon#about to read 3, iclass 10, count 0 2006.257.07:34:52.54#ibcon#read 3, iclass 10, count 0 2006.257.07:34:52.54#ibcon#about to read 4, iclass 10, count 0 2006.257.07:34:52.54#ibcon#read 4, iclass 10, count 0 2006.257.07:34:52.54#ibcon#about to read 5, iclass 10, count 0 2006.257.07:34:52.54#ibcon#read 5, iclass 10, count 0 2006.257.07:34:52.54#ibcon#about to read 6, iclass 10, count 0 2006.257.07:34:52.54#ibcon#read 6, iclass 10, count 0 2006.257.07:34:52.54#ibcon#end of sib2, iclass 10, count 0 2006.257.07:34:52.54#ibcon#*mode == 0, iclass 10, count 0 2006.257.07:34:52.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.07:34:52.54#ibcon#[27=USB\r\n] 2006.257.07:34:52.54#ibcon#*before write, iclass 10, count 0 2006.257.07:34:52.54#ibcon#enter sib2, iclass 10, count 0 2006.257.07:34:52.54#ibcon#flushed, iclass 10, count 0 2006.257.07:34:52.54#ibcon#about to write, iclass 10, count 0 2006.257.07:34:52.54#ibcon#wrote, iclass 10, count 0 2006.257.07:34:52.54#ibcon#about to read 3, iclass 10, count 0 2006.257.07:34:52.57#ibcon#read 3, iclass 10, count 0 2006.257.07:34:52.57#ibcon#about to read 4, iclass 10, count 0 2006.257.07:34:52.57#ibcon#read 4, iclass 10, count 0 2006.257.07:34:52.57#ibcon#about to read 5, iclass 10, count 0 2006.257.07:34:52.57#ibcon#read 5, iclass 10, count 0 2006.257.07:34:52.57#ibcon#about to read 6, iclass 10, count 0 2006.257.07:34:52.57#ibcon#read 6, iclass 10, count 0 2006.257.07:34:52.57#ibcon#end of sib2, iclass 10, count 0 2006.257.07:34:52.57#ibcon#*after write, iclass 10, count 0 2006.257.07:34:52.57#ibcon#*before return 0, iclass 10, count 0 2006.257.07:34:52.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:34:52.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:34:52.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.07:34:52.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.07:34:52.57$vck44/vblo=6,719.99 2006.257.07:34:52.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.07:34:52.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.07:34:52.57#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:52.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:52.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:52.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:52.57#ibcon#enter wrdev, iclass 12, count 0 2006.257.07:34:52.57#ibcon#first serial, iclass 12, count 0 2006.257.07:34:52.57#ibcon#enter sib2, iclass 12, count 0 2006.257.07:34:52.57#ibcon#flushed, iclass 12, count 0 2006.257.07:34:52.57#ibcon#about to write, iclass 12, count 0 2006.257.07:34:52.57#ibcon#wrote, iclass 12, count 0 2006.257.07:34:52.57#ibcon#about to read 3, iclass 12, count 0 2006.257.07:34:52.59#ibcon#read 3, iclass 12, count 0 2006.257.07:34:52.59#ibcon#about to read 4, iclass 12, count 0 2006.257.07:34:52.59#ibcon#read 4, iclass 12, count 0 2006.257.07:34:52.59#ibcon#about to read 5, iclass 12, count 0 2006.257.07:34:52.59#ibcon#read 5, iclass 12, count 0 2006.257.07:34:52.59#ibcon#about to read 6, iclass 12, count 0 2006.257.07:34:52.59#ibcon#read 6, iclass 12, count 0 2006.257.07:34:52.59#ibcon#end of sib2, iclass 12, count 0 2006.257.07:34:52.59#ibcon#*mode == 0, iclass 12, count 0 2006.257.07:34:52.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.07:34:52.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.07:34:52.59#ibcon#*before write, iclass 12, count 0 2006.257.07:34:52.59#ibcon#enter sib2, iclass 12, count 0 2006.257.07:34:52.59#ibcon#flushed, iclass 12, count 0 2006.257.07:34:52.59#ibcon#about to write, iclass 12, count 0 2006.257.07:34:52.59#ibcon#wrote, iclass 12, count 0 2006.257.07:34:52.59#ibcon#about to read 3, iclass 12, count 0 2006.257.07:34:52.63#ibcon#read 3, iclass 12, count 0 2006.257.07:34:52.63#ibcon#about to read 4, iclass 12, count 0 2006.257.07:34:52.63#ibcon#read 4, iclass 12, count 0 2006.257.07:34:52.63#ibcon#about to read 5, iclass 12, count 0 2006.257.07:34:52.63#ibcon#read 5, iclass 12, count 0 2006.257.07:34:52.63#ibcon#about to read 6, iclass 12, count 0 2006.257.07:34:52.63#ibcon#read 6, iclass 12, count 0 2006.257.07:34:52.63#ibcon#end of sib2, iclass 12, count 0 2006.257.07:34:52.63#ibcon#*after write, iclass 12, count 0 2006.257.07:34:52.63#ibcon#*before return 0, iclass 12, count 0 2006.257.07:34:52.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:52.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.07:34:52.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.07:34:52.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.07:34:52.63$vck44/vb=6,4 2006.257.07:34:52.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.07:34:52.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.07:34:52.63#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:52.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:52.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:52.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:52.69#ibcon#enter wrdev, iclass 14, count 2 2006.257.07:34:52.69#ibcon#first serial, iclass 14, count 2 2006.257.07:34:52.69#ibcon#enter sib2, iclass 14, count 2 2006.257.07:34:52.69#ibcon#flushed, iclass 14, count 2 2006.257.07:34:52.69#ibcon#about to write, iclass 14, count 2 2006.257.07:34:52.69#ibcon#wrote, iclass 14, count 2 2006.257.07:34:52.69#ibcon#about to read 3, iclass 14, count 2 2006.257.07:34:52.71#ibcon#read 3, iclass 14, count 2 2006.257.07:34:52.71#ibcon#about to read 4, iclass 14, count 2 2006.257.07:34:52.71#ibcon#read 4, iclass 14, count 2 2006.257.07:34:52.71#ibcon#about to read 5, iclass 14, count 2 2006.257.07:34:52.71#ibcon#read 5, iclass 14, count 2 2006.257.07:34:52.71#ibcon#about to read 6, iclass 14, count 2 2006.257.07:34:52.71#ibcon#read 6, iclass 14, count 2 2006.257.07:34:52.71#ibcon#end of sib2, iclass 14, count 2 2006.257.07:34:52.71#ibcon#*mode == 0, iclass 14, count 2 2006.257.07:34:52.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.07:34:52.71#ibcon#[27=AT06-04\r\n] 2006.257.07:34:52.71#ibcon#*before write, iclass 14, count 2 2006.257.07:34:52.71#ibcon#enter sib2, iclass 14, count 2 2006.257.07:34:52.71#ibcon#flushed, iclass 14, count 2 2006.257.07:34:52.71#ibcon#about to write, iclass 14, count 2 2006.257.07:34:52.71#ibcon#wrote, iclass 14, count 2 2006.257.07:34:52.71#ibcon#about to read 3, iclass 14, count 2 2006.257.07:34:52.74#ibcon#read 3, iclass 14, count 2 2006.257.07:34:52.74#ibcon#about to read 4, iclass 14, count 2 2006.257.07:34:52.74#ibcon#read 4, iclass 14, count 2 2006.257.07:34:52.74#ibcon#about to read 5, iclass 14, count 2 2006.257.07:34:52.74#ibcon#read 5, iclass 14, count 2 2006.257.07:34:52.74#ibcon#about to read 6, iclass 14, count 2 2006.257.07:34:52.74#ibcon#read 6, iclass 14, count 2 2006.257.07:34:52.74#ibcon#end of sib2, iclass 14, count 2 2006.257.07:34:52.74#ibcon#*after write, iclass 14, count 2 2006.257.07:34:52.74#ibcon#*before return 0, iclass 14, count 2 2006.257.07:34:52.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:52.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.07:34:52.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.07:34:52.74#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:52.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:52.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:52.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:52.86#ibcon#enter wrdev, iclass 14, count 0 2006.257.07:34:52.86#ibcon#first serial, iclass 14, count 0 2006.257.07:34:52.86#ibcon#enter sib2, iclass 14, count 0 2006.257.07:34:52.86#ibcon#flushed, iclass 14, count 0 2006.257.07:34:52.86#ibcon#about to write, iclass 14, count 0 2006.257.07:34:52.86#ibcon#wrote, iclass 14, count 0 2006.257.07:34:52.86#ibcon#about to read 3, iclass 14, count 0 2006.257.07:34:52.88#ibcon#read 3, iclass 14, count 0 2006.257.07:34:52.88#ibcon#about to read 4, iclass 14, count 0 2006.257.07:34:52.88#ibcon#read 4, iclass 14, count 0 2006.257.07:34:52.88#ibcon#about to read 5, iclass 14, count 0 2006.257.07:34:52.88#ibcon#read 5, iclass 14, count 0 2006.257.07:34:52.88#ibcon#about to read 6, iclass 14, count 0 2006.257.07:34:52.88#ibcon#read 6, iclass 14, count 0 2006.257.07:34:52.88#ibcon#end of sib2, iclass 14, count 0 2006.257.07:34:52.88#ibcon#*mode == 0, iclass 14, count 0 2006.257.07:34:52.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.07:34:52.88#ibcon#[27=USB\r\n] 2006.257.07:34:52.88#ibcon#*before write, iclass 14, count 0 2006.257.07:34:52.88#ibcon#enter sib2, iclass 14, count 0 2006.257.07:34:52.88#ibcon#flushed, iclass 14, count 0 2006.257.07:34:52.88#ibcon#about to write, iclass 14, count 0 2006.257.07:34:52.88#ibcon#wrote, iclass 14, count 0 2006.257.07:34:52.88#ibcon#about to read 3, iclass 14, count 0 2006.257.07:34:52.91#ibcon#read 3, iclass 14, count 0 2006.257.07:34:52.91#ibcon#about to read 4, iclass 14, count 0 2006.257.07:34:52.91#ibcon#read 4, iclass 14, count 0 2006.257.07:34:52.91#ibcon#about to read 5, iclass 14, count 0 2006.257.07:34:52.91#ibcon#read 5, iclass 14, count 0 2006.257.07:34:52.91#ibcon#about to read 6, iclass 14, count 0 2006.257.07:34:52.91#ibcon#read 6, iclass 14, count 0 2006.257.07:34:52.91#ibcon#end of sib2, iclass 14, count 0 2006.257.07:34:52.91#ibcon#*after write, iclass 14, count 0 2006.257.07:34:52.91#ibcon#*before return 0, iclass 14, count 0 2006.257.07:34:52.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:52.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.07:34:52.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.07:34:52.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.07:34:52.91$vck44/vblo=7,734.99 2006.257.07:34:52.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.07:34:52.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.07:34:52.91#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:52.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:52.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:52.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:52.91#ibcon#enter wrdev, iclass 16, count 0 2006.257.07:34:52.91#ibcon#first serial, iclass 16, count 0 2006.257.07:34:52.91#ibcon#enter sib2, iclass 16, count 0 2006.257.07:34:52.91#ibcon#flushed, iclass 16, count 0 2006.257.07:34:52.91#ibcon#about to write, iclass 16, count 0 2006.257.07:34:52.91#ibcon#wrote, iclass 16, count 0 2006.257.07:34:52.91#ibcon#about to read 3, iclass 16, count 0 2006.257.07:34:52.93#ibcon#read 3, iclass 16, count 0 2006.257.07:34:52.93#ibcon#about to read 4, iclass 16, count 0 2006.257.07:34:52.93#ibcon#read 4, iclass 16, count 0 2006.257.07:34:52.93#ibcon#about to read 5, iclass 16, count 0 2006.257.07:34:52.93#ibcon#read 5, iclass 16, count 0 2006.257.07:34:52.93#ibcon#about to read 6, iclass 16, count 0 2006.257.07:34:52.93#ibcon#read 6, iclass 16, count 0 2006.257.07:34:52.93#ibcon#end of sib2, iclass 16, count 0 2006.257.07:34:52.93#ibcon#*mode == 0, iclass 16, count 0 2006.257.07:34:52.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.07:34:52.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.07:34:52.93#ibcon#*before write, iclass 16, count 0 2006.257.07:34:52.93#ibcon#enter sib2, iclass 16, count 0 2006.257.07:34:52.93#ibcon#flushed, iclass 16, count 0 2006.257.07:34:52.93#ibcon#about to write, iclass 16, count 0 2006.257.07:34:52.93#ibcon#wrote, iclass 16, count 0 2006.257.07:34:52.93#ibcon#about to read 3, iclass 16, count 0 2006.257.07:34:52.97#ibcon#read 3, iclass 16, count 0 2006.257.07:34:52.97#ibcon#about to read 4, iclass 16, count 0 2006.257.07:34:52.97#ibcon#read 4, iclass 16, count 0 2006.257.07:34:52.97#ibcon#about to read 5, iclass 16, count 0 2006.257.07:34:52.97#ibcon#read 5, iclass 16, count 0 2006.257.07:34:52.97#ibcon#about to read 6, iclass 16, count 0 2006.257.07:34:52.97#ibcon#read 6, iclass 16, count 0 2006.257.07:34:52.97#ibcon#end of sib2, iclass 16, count 0 2006.257.07:34:52.97#ibcon#*after write, iclass 16, count 0 2006.257.07:34:52.97#ibcon#*before return 0, iclass 16, count 0 2006.257.07:34:52.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:52.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.07:34:52.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.07:34:52.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.07:34:52.97$vck44/vb=7,4 2006.257.07:34:52.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.07:34:52.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.07:34:52.97#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:52.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:53.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:53.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:53.03#ibcon#enter wrdev, iclass 18, count 2 2006.257.07:34:53.03#ibcon#first serial, iclass 18, count 2 2006.257.07:34:53.03#ibcon#enter sib2, iclass 18, count 2 2006.257.07:34:53.03#ibcon#flushed, iclass 18, count 2 2006.257.07:34:53.03#ibcon#about to write, iclass 18, count 2 2006.257.07:34:53.03#ibcon#wrote, iclass 18, count 2 2006.257.07:34:53.03#ibcon#about to read 3, iclass 18, count 2 2006.257.07:34:53.05#ibcon#read 3, iclass 18, count 2 2006.257.07:34:53.05#ibcon#about to read 4, iclass 18, count 2 2006.257.07:34:53.05#ibcon#read 4, iclass 18, count 2 2006.257.07:34:53.05#ibcon#about to read 5, iclass 18, count 2 2006.257.07:34:53.05#ibcon#read 5, iclass 18, count 2 2006.257.07:34:53.05#ibcon#about to read 6, iclass 18, count 2 2006.257.07:34:53.05#ibcon#read 6, iclass 18, count 2 2006.257.07:34:53.05#ibcon#end of sib2, iclass 18, count 2 2006.257.07:34:53.05#ibcon#*mode == 0, iclass 18, count 2 2006.257.07:34:53.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.07:34:53.05#ibcon#[27=AT07-04\r\n] 2006.257.07:34:53.05#ibcon#*before write, iclass 18, count 2 2006.257.07:34:53.05#ibcon#enter sib2, iclass 18, count 2 2006.257.07:34:53.05#ibcon#flushed, iclass 18, count 2 2006.257.07:34:53.05#ibcon#about to write, iclass 18, count 2 2006.257.07:34:53.05#ibcon#wrote, iclass 18, count 2 2006.257.07:34:53.05#ibcon#about to read 3, iclass 18, count 2 2006.257.07:34:53.08#ibcon#read 3, iclass 18, count 2 2006.257.07:34:53.08#ibcon#about to read 4, iclass 18, count 2 2006.257.07:34:53.08#ibcon#read 4, iclass 18, count 2 2006.257.07:34:53.08#ibcon#about to read 5, iclass 18, count 2 2006.257.07:34:53.08#ibcon#read 5, iclass 18, count 2 2006.257.07:34:53.08#ibcon#about to read 6, iclass 18, count 2 2006.257.07:34:53.08#ibcon#read 6, iclass 18, count 2 2006.257.07:34:53.08#ibcon#end of sib2, iclass 18, count 2 2006.257.07:34:53.08#ibcon#*after write, iclass 18, count 2 2006.257.07:34:53.08#ibcon#*before return 0, iclass 18, count 2 2006.257.07:34:53.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:53.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.07:34:53.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.07:34:53.08#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:53.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:53.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:53.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:53.20#ibcon#enter wrdev, iclass 18, count 0 2006.257.07:34:53.20#ibcon#first serial, iclass 18, count 0 2006.257.07:34:53.20#ibcon#enter sib2, iclass 18, count 0 2006.257.07:34:53.20#ibcon#flushed, iclass 18, count 0 2006.257.07:34:53.20#ibcon#about to write, iclass 18, count 0 2006.257.07:34:53.20#ibcon#wrote, iclass 18, count 0 2006.257.07:34:53.20#ibcon#about to read 3, iclass 18, count 0 2006.257.07:34:53.22#ibcon#read 3, iclass 18, count 0 2006.257.07:34:53.22#ibcon#about to read 4, iclass 18, count 0 2006.257.07:34:53.22#ibcon#read 4, iclass 18, count 0 2006.257.07:34:53.22#ibcon#about to read 5, iclass 18, count 0 2006.257.07:34:53.22#ibcon#read 5, iclass 18, count 0 2006.257.07:34:53.22#ibcon#about to read 6, iclass 18, count 0 2006.257.07:34:53.22#ibcon#read 6, iclass 18, count 0 2006.257.07:34:53.22#ibcon#end of sib2, iclass 18, count 0 2006.257.07:34:53.22#ibcon#*mode == 0, iclass 18, count 0 2006.257.07:34:53.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.07:34:53.22#ibcon#[27=USB\r\n] 2006.257.07:34:53.22#ibcon#*before write, iclass 18, count 0 2006.257.07:34:53.22#ibcon#enter sib2, iclass 18, count 0 2006.257.07:34:53.22#ibcon#flushed, iclass 18, count 0 2006.257.07:34:53.22#ibcon#about to write, iclass 18, count 0 2006.257.07:34:53.22#ibcon#wrote, iclass 18, count 0 2006.257.07:34:53.22#ibcon#about to read 3, iclass 18, count 0 2006.257.07:34:53.25#ibcon#read 3, iclass 18, count 0 2006.257.07:34:53.25#ibcon#about to read 4, iclass 18, count 0 2006.257.07:34:53.25#ibcon#read 4, iclass 18, count 0 2006.257.07:34:53.25#ibcon#about to read 5, iclass 18, count 0 2006.257.07:34:53.25#ibcon#read 5, iclass 18, count 0 2006.257.07:34:53.25#ibcon#about to read 6, iclass 18, count 0 2006.257.07:34:53.25#ibcon#read 6, iclass 18, count 0 2006.257.07:34:53.25#ibcon#end of sib2, iclass 18, count 0 2006.257.07:34:53.25#ibcon#*after write, iclass 18, count 0 2006.257.07:34:53.25#ibcon#*before return 0, iclass 18, count 0 2006.257.07:34:53.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:53.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.07:34:53.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.07:34:53.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.07:34:53.25$vck44/vblo=8,744.99 2006.257.07:34:53.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.07:34:53.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.07:34:53.25#ibcon#ireg 17 cls_cnt 0 2006.257.07:34:53.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:53.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:53.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:53.25#ibcon#enter wrdev, iclass 20, count 0 2006.257.07:34:53.25#ibcon#first serial, iclass 20, count 0 2006.257.07:34:53.25#ibcon#enter sib2, iclass 20, count 0 2006.257.07:34:53.25#ibcon#flushed, iclass 20, count 0 2006.257.07:34:53.25#ibcon#about to write, iclass 20, count 0 2006.257.07:34:53.25#ibcon#wrote, iclass 20, count 0 2006.257.07:34:53.25#ibcon#about to read 3, iclass 20, count 0 2006.257.07:34:53.27#ibcon#read 3, iclass 20, count 0 2006.257.07:34:53.27#ibcon#about to read 4, iclass 20, count 0 2006.257.07:34:53.27#ibcon#read 4, iclass 20, count 0 2006.257.07:34:53.27#ibcon#about to read 5, iclass 20, count 0 2006.257.07:34:53.27#ibcon#read 5, iclass 20, count 0 2006.257.07:34:53.27#ibcon#about to read 6, iclass 20, count 0 2006.257.07:34:53.27#ibcon#read 6, iclass 20, count 0 2006.257.07:34:53.27#ibcon#end of sib2, iclass 20, count 0 2006.257.07:34:53.27#ibcon#*mode == 0, iclass 20, count 0 2006.257.07:34:53.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.07:34:53.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.07:34:53.27#ibcon#*before write, iclass 20, count 0 2006.257.07:34:53.27#ibcon#enter sib2, iclass 20, count 0 2006.257.07:34:53.27#ibcon#flushed, iclass 20, count 0 2006.257.07:34:53.27#ibcon#about to write, iclass 20, count 0 2006.257.07:34:53.27#ibcon#wrote, iclass 20, count 0 2006.257.07:34:53.27#ibcon#about to read 3, iclass 20, count 0 2006.257.07:34:53.31#ibcon#read 3, iclass 20, count 0 2006.257.07:34:53.31#ibcon#about to read 4, iclass 20, count 0 2006.257.07:34:53.31#ibcon#read 4, iclass 20, count 0 2006.257.07:34:53.31#ibcon#about to read 5, iclass 20, count 0 2006.257.07:34:53.31#ibcon#read 5, iclass 20, count 0 2006.257.07:34:53.31#ibcon#about to read 6, iclass 20, count 0 2006.257.07:34:53.31#ibcon#read 6, iclass 20, count 0 2006.257.07:34:53.31#ibcon#end of sib2, iclass 20, count 0 2006.257.07:34:53.31#ibcon#*after write, iclass 20, count 0 2006.257.07:34:53.31#ibcon#*before return 0, iclass 20, count 0 2006.257.07:34:53.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:53.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.07:34:53.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.07:34:53.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.07:34:53.31$vck44/vb=8,4 2006.257.07:34:53.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.07:34:53.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.07:34:53.31#ibcon#ireg 11 cls_cnt 2 2006.257.07:34:53.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:53.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:53.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:53.37#ibcon#enter wrdev, iclass 22, count 2 2006.257.07:34:53.37#ibcon#first serial, iclass 22, count 2 2006.257.07:34:53.37#ibcon#enter sib2, iclass 22, count 2 2006.257.07:34:53.37#ibcon#flushed, iclass 22, count 2 2006.257.07:34:53.37#ibcon#about to write, iclass 22, count 2 2006.257.07:34:53.37#ibcon#wrote, iclass 22, count 2 2006.257.07:34:53.37#ibcon#about to read 3, iclass 22, count 2 2006.257.07:34:53.39#ibcon#read 3, iclass 22, count 2 2006.257.07:34:53.39#ibcon#about to read 4, iclass 22, count 2 2006.257.07:34:53.39#ibcon#read 4, iclass 22, count 2 2006.257.07:34:53.39#ibcon#about to read 5, iclass 22, count 2 2006.257.07:34:53.39#ibcon#read 5, iclass 22, count 2 2006.257.07:34:53.39#ibcon#about to read 6, iclass 22, count 2 2006.257.07:34:53.39#ibcon#read 6, iclass 22, count 2 2006.257.07:34:53.39#ibcon#end of sib2, iclass 22, count 2 2006.257.07:34:53.39#ibcon#*mode == 0, iclass 22, count 2 2006.257.07:34:53.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.07:34:53.39#ibcon#[27=AT08-04\r\n] 2006.257.07:34:53.39#ibcon#*before write, iclass 22, count 2 2006.257.07:34:53.39#ibcon#enter sib2, iclass 22, count 2 2006.257.07:34:53.39#ibcon#flushed, iclass 22, count 2 2006.257.07:34:53.39#ibcon#about to write, iclass 22, count 2 2006.257.07:34:53.39#ibcon#wrote, iclass 22, count 2 2006.257.07:34:53.39#ibcon#about to read 3, iclass 22, count 2 2006.257.07:34:53.42#ibcon#read 3, iclass 22, count 2 2006.257.07:34:53.42#ibcon#about to read 4, iclass 22, count 2 2006.257.07:34:53.42#ibcon#read 4, iclass 22, count 2 2006.257.07:34:53.42#ibcon#about to read 5, iclass 22, count 2 2006.257.07:34:53.42#ibcon#read 5, iclass 22, count 2 2006.257.07:34:53.42#ibcon#about to read 6, iclass 22, count 2 2006.257.07:34:53.42#ibcon#read 6, iclass 22, count 2 2006.257.07:34:53.42#ibcon#end of sib2, iclass 22, count 2 2006.257.07:34:53.42#ibcon#*after write, iclass 22, count 2 2006.257.07:34:53.42#ibcon#*before return 0, iclass 22, count 2 2006.257.07:34:53.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:53.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.07:34:53.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.07:34:53.42#ibcon#ireg 7 cls_cnt 0 2006.257.07:34:53.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:53.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:53.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:53.54#ibcon#enter wrdev, iclass 22, count 0 2006.257.07:34:53.54#ibcon#first serial, iclass 22, count 0 2006.257.07:34:53.54#ibcon#enter sib2, iclass 22, count 0 2006.257.07:34:53.54#ibcon#flushed, iclass 22, count 0 2006.257.07:34:53.54#ibcon#about to write, iclass 22, count 0 2006.257.07:34:53.54#ibcon#wrote, iclass 22, count 0 2006.257.07:34:53.54#ibcon#about to read 3, iclass 22, count 0 2006.257.07:34:53.56#ibcon#read 3, iclass 22, count 0 2006.257.07:34:53.56#ibcon#about to read 4, iclass 22, count 0 2006.257.07:34:53.56#ibcon#read 4, iclass 22, count 0 2006.257.07:34:53.56#ibcon#about to read 5, iclass 22, count 0 2006.257.07:34:53.56#ibcon#read 5, iclass 22, count 0 2006.257.07:34:53.56#ibcon#about to read 6, iclass 22, count 0 2006.257.07:34:53.56#ibcon#read 6, iclass 22, count 0 2006.257.07:34:53.56#ibcon#end of sib2, iclass 22, count 0 2006.257.07:34:53.56#ibcon#*mode == 0, iclass 22, count 0 2006.257.07:34:53.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.07:34:53.56#ibcon#[27=USB\r\n] 2006.257.07:34:53.56#ibcon#*before write, iclass 22, count 0 2006.257.07:34:53.56#ibcon#enter sib2, iclass 22, count 0 2006.257.07:34:53.56#ibcon#flushed, iclass 22, count 0 2006.257.07:34:53.56#ibcon#about to write, iclass 22, count 0 2006.257.07:34:53.56#ibcon#wrote, iclass 22, count 0 2006.257.07:34:53.56#ibcon#about to read 3, iclass 22, count 0 2006.257.07:34:53.59#ibcon#read 3, iclass 22, count 0 2006.257.07:34:53.59#ibcon#about to read 4, iclass 22, count 0 2006.257.07:34:53.59#ibcon#read 4, iclass 22, count 0 2006.257.07:34:53.59#ibcon#about to read 5, iclass 22, count 0 2006.257.07:34:53.59#ibcon#read 5, iclass 22, count 0 2006.257.07:34:53.59#ibcon#about to read 6, iclass 22, count 0 2006.257.07:34:53.59#ibcon#read 6, iclass 22, count 0 2006.257.07:34:53.59#ibcon#end of sib2, iclass 22, count 0 2006.257.07:34:53.59#ibcon#*after write, iclass 22, count 0 2006.257.07:34:53.59#ibcon#*before return 0, iclass 22, count 0 2006.257.07:34:53.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:53.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.07:34:53.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.07:34:53.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.07:34:53.59$vck44/vabw=wide 2006.257.07:34:53.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.07:34:53.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.07:34:53.59#ibcon#ireg 8 cls_cnt 0 2006.257.07:34:53.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:53.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:53.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:53.59#ibcon#enter wrdev, iclass 24, count 0 2006.257.07:34:53.59#ibcon#first serial, iclass 24, count 0 2006.257.07:34:53.59#ibcon#enter sib2, iclass 24, count 0 2006.257.07:34:53.59#ibcon#flushed, iclass 24, count 0 2006.257.07:34:53.59#ibcon#about to write, iclass 24, count 0 2006.257.07:34:53.59#ibcon#wrote, iclass 24, count 0 2006.257.07:34:53.59#ibcon#about to read 3, iclass 24, count 0 2006.257.07:34:53.61#ibcon#read 3, iclass 24, count 0 2006.257.07:34:53.61#ibcon#about to read 4, iclass 24, count 0 2006.257.07:34:53.61#ibcon#read 4, iclass 24, count 0 2006.257.07:34:53.61#ibcon#about to read 5, iclass 24, count 0 2006.257.07:34:53.61#ibcon#read 5, iclass 24, count 0 2006.257.07:34:53.61#ibcon#about to read 6, iclass 24, count 0 2006.257.07:34:53.61#ibcon#read 6, iclass 24, count 0 2006.257.07:34:53.61#ibcon#end of sib2, iclass 24, count 0 2006.257.07:34:53.61#ibcon#*mode == 0, iclass 24, count 0 2006.257.07:34:53.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.07:34:53.61#ibcon#[25=BW32\r\n] 2006.257.07:34:53.61#ibcon#*before write, iclass 24, count 0 2006.257.07:34:53.61#ibcon#enter sib2, iclass 24, count 0 2006.257.07:34:53.61#ibcon#flushed, iclass 24, count 0 2006.257.07:34:53.61#ibcon#about to write, iclass 24, count 0 2006.257.07:34:53.61#ibcon#wrote, iclass 24, count 0 2006.257.07:34:53.61#ibcon#about to read 3, iclass 24, count 0 2006.257.07:34:53.64#ibcon#read 3, iclass 24, count 0 2006.257.07:34:53.64#ibcon#about to read 4, iclass 24, count 0 2006.257.07:34:53.64#ibcon#read 4, iclass 24, count 0 2006.257.07:34:53.64#ibcon#about to read 5, iclass 24, count 0 2006.257.07:34:53.64#ibcon#read 5, iclass 24, count 0 2006.257.07:34:53.64#ibcon#about to read 6, iclass 24, count 0 2006.257.07:34:53.64#ibcon#read 6, iclass 24, count 0 2006.257.07:34:53.64#ibcon#end of sib2, iclass 24, count 0 2006.257.07:34:53.64#ibcon#*after write, iclass 24, count 0 2006.257.07:34:53.64#ibcon#*before return 0, iclass 24, count 0 2006.257.07:34:53.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:53.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.07:34:53.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.07:34:53.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.07:34:53.64$vck44/vbbw=wide 2006.257.07:34:53.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.07:34:53.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.07:34:53.64#ibcon#ireg 8 cls_cnt 0 2006.257.07:34:53.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:34:53.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:34:53.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:34:53.71#ibcon#enter wrdev, iclass 26, count 0 2006.257.07:34:53.71#ibcon#first serial, iclass 26, count 0 2006.257.07:34:53.71#ibcon#enter sib2, iclass 26, count 0 2006.257.07:34:53.71#ibcon#flushed, iclass 26, count 0 2006.257.07:34:53.71#ibcon#about to write, iclass 26, count 0 2006.257.07:34:53.71#ibcon#wrote, iclass 26, count 0 2006.257.07:34:53.71#ibcon#about to read 3, iclass 26, count 0 2006.257.07:34:53.73#ibcon#read 3, iclass 26, count 0 2006.257.07:34:53.73#ibcon#about to read 4, iclass 26, count 0 2006.257.07:34:53.73#ibcon#read 4, iclass 26, count 0 2006.257.07:34:53.73#ibcon#about to read 5, iclass 26, count 0 2006.257.07:34:53.73#ibcon#read 5, iclass 26, count 0 2006.257.07:34:53.73#ibcon#about to read 6, iclass 26, count 0 2006.257.07:34:53.73#ibcon#read 6, iclass 26, count 0 2006.257.07:34:53.73#ibcon#end of sib2, iclass 26, count 0 2006.257.07:34:53.73#ibcon#*mode == 0, iclass 26, count 0 2006.257.07:34:53.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.07:34:53.73#ibcon#[27=BW32\r\n] 2006.257.07:34:53.73#ibcon#*before write, iclass 26, count 0 2006.257.07:34:53.73#ibcon#enter sib2, iclass 26, count 0 2006.257.07:34:53.73#ibcon#flushed, iclass 26, count 0 2006.257.07:34:53.73#ibcon#about to write, iclass 26, count 0 2006.257.07:34:53.73#ibcon#wrote, iclass 26, count 0 2006.257.07:34:53.73#ibcon#about to read 3, iclass 26, count 0 2006.257.07:34:53.76#ibcon#read 3, iclass 26, count 0 2006.257.07:34:53.76#ibcon#about to read 4, iclass 26, count 0 2006.257.07:34:53.76#ibcon#read 4, iclass 26, count 0 2006.257.07:34:53.76#ibcon#about to read 5, iclass 26, count 0 2006.257.07:34:53.76#ibcon#read 5, iclass 26, count 0 2006.257.07:34:53.76#ibcon#about to read 6, iclass 26, count 0 2006.257.07:34:53.76#ibcon#read 6, iclass 26, count 0 2006.257.07:34:53.76#ibcon#end of sib2, iclass 26, count 0 2006.257.07:34:53.76#ibcon#*after write, iclass 26, count 0 2006.257.07:34:53.76#ibcon#*before return 0, iclass 26, count 0 2006.257.07:34:53.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:34:53.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:34:53.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.07:34:53.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.07:34:53.76$setupk4/ifdk4 2006.257.07:34:53.76$ifdk4/lo= 2006.257.07:34:53.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.07:34:53.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.07:34:53.76$ifdk4/patch= 2006.257.07:34:53.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.07:34:53.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.07:34:53.76$setupk4/!*+20s 2006.257.07:34:59.40#abcon#<5=/15 1.4 3.5 21.18 871012.5\r\n> 2006.257.07:34:59.42#abcon#{5=INTERFACE CLEAR} 2006.257.07:34:59.48#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:35:02.14#trakl#Source acquired 2006.257.07:35:04.14#flagr#flagr/antenna,acquired 2006.257.07:35:08.27$setupk4/"tpicd 2006.257.07:35:08.27$setupk4/echo=off 2006.257.07:35:08.27$setupk4/xlog=off 2006.257.07:35:08.27:!2006.257.07:37:54 2006.257.07:37:54.00:preob 2006.257.07:37:54.14/onsource/TRACKING 2006.257.07:37:54.14:!2006.257.07:38:04 2006.257.07:38:04.00:"tape 2006.257.07:38:04.00:"st=record 2006.257.07:38:04.00:data_valid=on 2006.257.07:38:04.00:midob 2006.257.07:38:04.14/onsource/TRACKING 2006.257.07:38:04.14/wx/21.17,1012.5,87 2006.257.07:38:04.28/cable/+6.4751E-03 2006.257.07:38:05.37/va/01,08,usb,yes,33,35 2006.257.07:38:05.37/va/02,07,usb,yes,36,36 2006.257.07:38:05.37/va/03,08,usb,yes,32,34 2006.257.07:38:05.37/va/04,07,usb,yes,37,39 2006.257.07:38:05.37/va/05,04,usb,yes,33,33 2006.257.07:38:05.37/va/06,04,usb,yes,37,36 2006.257.07:38:05.37/va/07,04,usb,yes,38,38 2006.257.07:38:05.37/va/08,04,usb,yes,31,38 2006.257.07:38:05.60/valo/01,524.99,yes,locked 2006.257.07:38:05.60/valo/02,534.99,yes,locked 2006.257.07:38:05.60/valo/03,564.99,yes,locked 2006.257.07:38:05.60/valo/04,624.99,yes,locked 2006.257.07:38:05.60/valo/05,734.99,yes,locked 2006.257.07:38:05.60/valo/06,814.99,yes,locked 2006.257.07:38:05.60/valo/07,864.99,yes,locked 2006.257.07:38:05.60/valo/08,884.99,yes,locked 2006.257.07:38:06.69/vb/01,04,usb,yes,31,28 2006.257.07:38:06.69/vb/02,05,usb,yes,29,29 2006.257.07:38:06.69/vb/03,04,usb,yes,30,33 2006.257.07:38:06.69/vb/04,05,usb,yes,30,29 2006.257.07:38:06.69/vb/05,04,usb,yes,27,29 2006.257.07:38:06.69/vb/06,04,usb,yes,31,27 2006.257.07:38:06.69/vb/07,04,usb,yes,31,31 2006.257.07:38:06.69/vb/08,04,usb,yes,28,32 2006.257.07:38:06.92/vblo/01,629.99,yes,locked 2006.257.07:38:06.92/vblo/02,634.99,yes,locked 2006.257.07:38:06.92/vblo/03,649.99,yes,locked 2006.257.07:38:06.92/vblo/04,679.99,yes,locked 2006.257.07:38:06.92/vblo/05,709.99,yes,locked 2006.257.07:38:06.92/vblo/06,719.99,yes,locked 2006.257.07:38:06.92/vblo/07,734.99,yes,locked 2006.257.07:38:06.92/vblo/08,744.99,yes,locked 2006.257.07:38:07.07/vabw/8 2006.257.07:38:07.22/vbbw/8 2006.257.07:38:07.42/xfe/off,on,15.2 2006.257.07:38:07.80/ifatt/23,28,28,28 2006.257.07:38:08.08/fmout-gps/S +4.55E-07 2006.257.07:38:08.12:!2006.257.07:40:54 2006.257.07:40:54.00:data_valid=off 2006.257.07:40:54.00:"et 2006.257.07:40:54.00:!+3s 2006.257.07:40:57.01:"tape 2006.257.07:40:57.01:postob 2006.257.07:40:57.19/cable/+6.4759E-03 2006.257.07:40:57.19/wx/21.17,1012.6,87 2006.257.07:40:58.08/fmout-gps/S +4.53E-07 2006.257.07:40:58.08:scan_name=257-0745,jd0609,140 2006.257.07:40:58.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.257.07:40:59.14#flagr#flagr/antenna,new-source 2006.257.07:40:59.14:checkk5 2006.257.07:40:59.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.07:40:59.91/chk_autoobs//k5ts2/ autoobs is running! 2006.257.07:41:00.41/chk_autoobs//k5ts3/ autoobs is running! 2006.257.07:41:00.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.07:41:01.18/chk_obsdata//k5ts1/T2570738??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.07:41:01.59/chk_obsdata//k5ts2/T2570738??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.07:41:01.98/chk_obsdata//k5ts3/T2570738??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.07:41:02.38/chk_obsdata//k5ts4/T2570738??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.07:41:03.12/k5log//k5ts1_log_newline 2006.257.07:41:03.84/k5log//k5ts2_log_newline 2006.257.07:41:04.60/k5log//k5ts3_log_newline 2006.257.07:41:05.34/k5log//k5ts4_log_newline 2006.257.07:41:05.37/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.07:41:05.37:setupk4=1 2006.257.07:41:05.37$setupk4/echo=on 2006.257.07:41:05.37$setupk4/pcalon 2006.257.07:41:05.37$pcalon/"no phase cal control is implemented here 2006.257.07:41:05.37$setupk4/"tpicd=stop 2006.257.07:41:05.37$setupk4/"rec=synch_on 2006.257.07:41:05.37$setupk4/"rec_mode=128 2006.257.07:41:05.37$setupk4/!* 2006.257.07:41:05.37$setupk4/recpk4 2006.257.07:41:05.37$recpk4/recpatch= 2006.257.07:41:05.37$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.07:41:05.37$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.07:41:05.37$setupk4/vck44 2006.257.07:41:05.37$vck44/valo=1,524.99 2006.257.07:41:05.37#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.07:41:05.37#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.07:41:05.37#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:05.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:05.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:05.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:05.37#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:41:05.37#ibcon#first serial, iclass 31, count 0 2006.257.07:41:05.37#ibcon#enter sib2, iclass 31, count 0 2006.257.07:41:05.37#ibcon#flushed, iclass 31, count 0 2006.257.07:41:05.37#ibcon#about to write, iclass 31, count 0 2006.257.07:41:05.37#ibcon#wrote, iclass 31, count 0 2006.257.07:41:05.37#ibcon#about to read 3, iclass 31, count 0 2006.257.07:41:05.39#ibcon#read 3, iclass 31, count 0 2006.257.07:41:05.39#ibcon#about to read 4, iclass 31, count 0 2006.257.07:41:05.39#ibcon#read 4, iclass 31, count 0 2006.257.07:41:05.39#ibcon#about to read 5, iclass 31, count 0 2006.257.07:41:05.39#ibcon#read 5, iclass 31, count 0 2006.257.07:41:05.39#ibcon#about to read 6, iclass 31, count 0 2006.257.07:41:05.39#ibcon#read 6, iclass 31, count 0 2006.257.07:41:05.39#ibcon#end of sib2, iclass 31, count 0 2006.257.07:41:05.39#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:41:05.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:41:05.39#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.07:41:05.39#ibcon#*before write, iclass 31, count 0 2006.257.07:41:05.39#ibcon#enter sib2, iclass 31, count 0 2006.257.07:41:05.39#ibcon#flushed, iclass 31, count 0 2006.257.07:41:05.39#ibcon#about to write, iclass 31, count 0 2006.257.07:41:05.39#ibcon#wrote, iclass 31, count 0 2006.257.07:41:05.39#ibcon#about to read 3, iclass 31, count 0 2006.257.07:41:05.44#ibcon#read 3, iclass 31, count 0 2006.257.07:41:05.44#ibcon#about to read 4, iclass 31, count 0 2006.257.07:41:05.44#ibcon#read 4, iclass 31, count 0 2006.257.07:41:05.44#ibcon#about to read 5, iclass 31, count 0 2006.257.07:41:05.44#ibcon#read 5, iclass 31, count 0 2006.257.07:41:05.44#ibcon#about to read 6, iclass 31, count 0 2006.257.07:41:05.44#ibcon#read 6, iclass 31, count 0 2006.257.07:41:05.44#ibcon#end of sib2, iclass 31, count 0 2006.257.07:41:05.44#ibcon#*after write, iclass 31, count 0 2006.257.07:41:05.44#ibcon#*before return 0, iclass 31, count 0 2006.257.07:41:05.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:05.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:05.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:41:05.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:41:05.44$vck44/va=1,8 2006.257.07:41:05.44#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.07:41:05.44#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.07:41:05.44#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:05.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:05.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:05.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:05.44#ibcon#enter wrdev, iclass 33, count 2 2006.257.07:41:05.44#ibcon#first serial, iclass 33, count 2 2006.257.07:41:05.44#ibcon#enter sib2, iclass 33, count 2 2006.257.07:41:05.44#ibcon#flushed, iclass 33, count 2 2006.257.07:41:05.44#ibcon#about to write, iclass 33, count 2 2006.257.07:41:05.44#ibcon#wrote, iclass 33, count 2 2006.257.07:41:05.44#ibcon#about to read 3, iclass 33, count 2 2006.257.07:41:05.46#ibcon#read 3, iclass 33, count 2 2006.257.07:41:05.46#ibcon#about to read 4, iclass 33, count 2 2006.257.07:41:05.46#ibcon#read 4, iclass 33, count 2 2006.257.07:41:05.46#ibcon#about to read 5, iclass 33, count 2 2006.257.07:41:05.46#ibcon#read 5, iclass 33, count 2 2006.257.07:41:05.46#ibcon#about to read 6, iclass 33, count 2 2006.257.07:41:05.46#ibcon#read 6, iclass 33, count 2 2006.257.07:41:05.46#ibcon#end of sib2, iclass 33, count 2 2006.257.07:41:05.46#ibcon#*mode == 0, iclass 33, count 2 2006.257.07:41:05.46#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.07:41:05.46#ibcon#[25=AT01-08\r\n] 2006.257.07:41:05.46#ibcon#*before write, iclass 33, count 2 2006.257.07:41:05.46#ibcon#enter sib2, iclass 33, count 2 2006.257.07:41:05.46#ibcon#flushed, iclass 33, count 2 2006.257.07:41:05.46#ibcon#about to write, iclass 33, count 2 2006.257.07:41:05.46#ibcon#wrote, iclass 33, count 2 2006.257.07:41:05.46#ibcon#about to read 3, iclass 33, count 2 2006.257.07:41:05.49#ibcon#read 3, iclass 33, count 2 2006.257.07:41:05.49#ibcon#about to read 4, iclass 33, count 2 2006.257.07:41:05.49#ibcon#read 4, iclass 33, count 2 2006.257.07:41:05.49#ibcon#about to read 5, iclass 33, count 2 2006.257.07:41:05.49#ibcon#read 5, iclass 33, count 2 2006.257.07:41:05.49#ibcon#about to read 6, iclass 33, count 2 2006.257.07:41:05.49#ibcon#read 6, iclass 33, count 2 2006.257.07:41:05.49#ibcon#end of sib2, iclass 33, count 2 2006.257.07:41:05.49#ibcon#*after write, iclass 33, count 2 2006.257.07:41:05.49#ibcon#*before return 0, iclass 33, count 2 2006.257.07:41:05.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:05.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:05.49#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.07:41:05.49#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:05.49#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:05.52#abcon#<5=/16 1.1 2.6 21.17 871012.6\r\n> 2006.257.07:41:05.54#abcon#{5=INTERFACE CLEAR} 2006.257.07:41:05.60#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:41:05.61#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:05.61#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:05.61#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:41:05.61#ibcon#first serial, iclass 33, count 0 2006.257.07:41:05.61#ibcon#enter sib2, iclass 33, count 0 2006.257.07:41:05.61#ibcon#flushed, iclass 33, count 0 2006.257.07:41:05.61#ibcon#about to write, iclass 33, count 0 2006.257.07:41:05.61#ibcon#wrote, iclass 33, count 0 2006.257.07:41:05.61#ibcon#about to read 3, iclass 33, count 0 2006.257.07:41:05.63#ibcon#read 3, iclass 33, count 0 2006.257.07:41:05.63#ibcon#about to read 4, iclass 33, count 0 2006.257.07:41:05.63#ibcon#read 4, iclass 33, count 0 2006.257.07:41:05.63#ibcon#about to read 5, iclass 33, count 0 2006.257.07:41:05.63#ibcon#read 5, iclass 33, count 0 2006.257.07:41:05.63#ibcon#about to read 6, iclass 33, count 0 2006.257.07:41:05.63#ibcon#read 6, iclass 33, count 0 2006.257.07:41:05.63#ibcon#end of sib2, iclass 33, count 0 2006.257.07:41:05.63#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:41:05.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:41:05.63#ibcon#[25=USB\r\n] 2006.257.07:41:05.63#ibcon#*before write, iclass 33, count 0 2006.257.07:41:05.63#ibcon#enter sib2, iclass 33, count 0 2006.257.07:41:05.63#ibcon#flushed, iclass 33, count 0 2006.257.07:41:05.63#ibcon#about to write, iclass 33, count 0 2006.257.07:41:05.63#ibcon#wrote, iclass 33, count 0 2006.257.07:41:05.63#ibcon#about to read 3, iclass 33, count 0 2006.257.07:41:05.66#ibcon#read 3, iclass 33, count 0 2006.257.07:41:05.66#ibcon#about to read 4, iclass 33, count 0 2006.257.07:41:05.66#ibcon#read 4, iclass 33, count 0 2006.257.07:41:05.66#ibcon#about to read 5, iclass 33, count 0 2006.257.07:41:05.66#ibcon#read 5, iclass 33, count 0 2006.257.07:41:05.66#ibcon#about to read 6, iclass 33, count 0 2006.257.07:41:05.66#ibcon#read 6, iclass 33, count 0 2006.257.07:41:05.66#ibcon#end of sib2, iclass 33, count 0 2006.257.07:41:05.66#ibcon#*after write, iclass 33, count 0 2006.257.07:41:05.66#ibcon#*before return 0, iclass 33, count 0 2006.257.07:41:05.66#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:05.66#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:05.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:41:05.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:41:05.66$vck44/valo=2,534.99 2006.257.07:41:05.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.07:41:05.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.07:41:05.66#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:05.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:05.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:05.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:05.66#ibcon#enter wrdev, iclass 39, count 0 2006.257.07:41:05.66#ibcon#first serial, iclass 39, count 0 2006.257.07:41:05.66#ibcon#enter sib2, iclass 39, count 0 2006.257.07:41:05.66#ibcon#flushed, iclass 39, count 0 2006.257.07:41:05.66#ibcon#about to write, iclass 39, count 0 2006.257.07:41:05.66#ibcon#wrote, iclass 39, count 0 2006.257.07:41:05.66#ibcon#about to read 3, iclass 39, count 0 2006.257.07:41:05.68#ibcon#read 3, iclass 39, count 0 2006.257.07:41:05.68#ibcon#about to read 4, iclass 39, count 0 2006.257.07:41:05.68#ibcon#read 4, iclass 39, count 0 2006.257.07:41:05.68#ibcon#about to read 5, iclass 39, count 0 2006.257.07:41:05.68#ibcon#read 5, iclass 39, count 0 2006.257.07:41:05.68#ibcon#about to read 6, iclass 39, count 0 2006.257.07:41:05.68#ibcon#read 6, iclass 39, count 0 2006.257.07:41:05.68#ibcon#end of sib2, iclass 39, count 0 2006.257.07:41:05.68#ibcon#*mode == 0, iclass 39, count 0 2006.257.07:41:05.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.07:41:05.68#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.07:41:05.68#ibcon#*before write, iclass 39, count 0 2006.257.07:41:05.68#ibcon#enter sib2, iclass 39, count 0 2006.257.07:41:05.68#ibcon#flushed, iclass 39, count 0 2006.257.07:41:05.68#ibcon#about to write, iclass 39, count 0 2006.257.07:41:05.68#ibcon#wrote, iclass 39, count 0 2006.257.07:41:05.68#ibcon#about to read 3, iclass 39, count 0 2006.257.07:41:05.72#ibcon#read 3, iclass 39, count 0 2006.257.07:41:05.72#ibcon#about to read 4, iclass 39, count 0 2006.257.07:41:05.72#ibcon#read 4, iclass 39, count 0 2006.257.07:41:05.72#ibcon#about to read 5, iclass 39, count 0 2006.257.07:41:05.72#ibcon#read 5, iclass 39, count 0 2006.257.07:41:05.72#ibcon#about to read 6, iclass 39, count 0 2006.257.07:41:05.72#ibcon#read 6, iclass 39, count 0 2006.257.07:41:05.72#ibcon#end of sib2, iclass 39, count 0 2006.257.07:41:05.72#ibcon#*after write, iclass 39, count 0 2006.257.07:41:05.72#ibcon#*before return 0, iclass 39, count 0 2006.257.07:41:05.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:05.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:05.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.07:41:05.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.07:41:05.72$vck44/va=2,7 2006.257.07:41:05.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.07:41:05.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.07:41:05.72#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:05.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:05.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:05.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:05.78#ibcon#enter wrdev, iclass 3, count 2 2006.257.07:41:05.78#ibcon#first serial, iclass 3, count 2 2006.257.07:41:05.78#ibcon#enter sib2, iclass 3, count 2 2006.257.07:41:05.78#ibcon#flushed, iclass 3, count 2 2006.257.07:41:05.78#ibcon#about to write, iclass 3, count 2 2006.257.07:41:05.78#ibcon#wrote, iclass 3, count 2 2006.257.07:41:05.78#ibcon#about to read 3, iclass 3, count 2 2006.257.07:41:05.80#ibcon#read 3, iclass 3, count 2 2006.257.07:41:05.80#ibcon#about to read 4, iclass 3, count 2 2006.257.07:41:05.80#ibcon#read 4, iclass 3, count 2 2006.257.07:41:05.80#ibcon#about to read 5, iclass 3, count 2 2006.257.07:41:05.80#ibcon#read 5, iclass 3, count 2 2006.257.07:41:05.80#ibcon#about to read 6, iclass 3, count 2 2006.257.07:41:05.80#ibcon#read 6, iclass 3, count 2 2006.257.07:41:05.80#ibcon#end of sib2, iclass 3, count 2 2006.257.07:41:05.80#ibcon#*mode == 0, iclass 3, count 2 2006.257.07:41:05.80#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.07:41:05.80#ibcon#[25=AT02-07\r\n] 2006.257.07:41:05.80#ibcon#*before write, iclass 3, count 2 2006.257.07:41:05.80#ibcon#enter sib2, iclass 3, count 2 2006.257.07:41:05.80#ibcon#flushed, iclass 3, count 2 2006.257.07:41:05.80#ibcon#about to write, iclass 3, count 2 2006.257.07:41:05.80#ibcon#wrote, iclass 3, count 2 2006.257.07:41:05.80#ibcon#about to read 3, iclass 3, count 2 2006.257.07:41:05.83#ibcon#read 3, iclass 3, count 2 2006.257.07:41:05.83#ibcon#about to read 4, iclass 3, count 2 2006.257.07:41:05.83#ibcon#read 4, iclass 3, count 2 2006.257.07:41:05.83#ibcon#about to read 5, iclass 3, count 2 2006.257.07:41:05.83#ibcon#read 5, iclass 3, count 2 2006.257.07:41:05.83#ibcon#about to read 6, iclass 3, count 2 2006.257.07:41:05.83#ibcon#read 6, iclass 3, count 2 2006.257.07:41:05.83#ibcon#end of sib2, iclass 3, count 2 2006.257.07:41:05.83#ibcon#*after write, iclass 3, count 2 2006.257.07:41:05.83#ibcon#*before return 0, iclass 3, count 2 2006.257.07:41:05.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:05.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:05.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.07:41:05.83#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:05.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:05.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:05.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:05.95#ibcon#enter wrdev, iclass 3, count 0 2006.257.07:41:05.95#ibcon#first serial, iclass 3, count 0 2006.257.07:41:05.95#ibcon#enter sib2, iclass 3, count 0 2006.257.07:41:05.95#ibcon#flushed, iclass 3, count 0 2006.257.07:41:05.95#ibcon#about to write, iclass 3, count 0 2006.257.07:41:05.95#ibcon#wrote, iclass 3, count 0 2006.257.07:41:05.95#ibcon#about to read 3, iclass 3, count 0 2006.257.07:41:05.97#ibcon#read 3, iclass 3, count 0 2006.257.07:41:05.97#ibcon#about to read 4, iclass 3, count 0 2006.257.07:41:05.97#ibcon#read 4, iclass 3, count 0 2006.257.07:41:05.97#ibcon#about to read 5, iclass 3, count 0 2006.257.07:41:05.97#ibcon#read 5, iclass 3, count 0 2006.257.07:41:05.97#ibcon#about to read 6, iclass 3, count 0 2006.257.07:41:05.97#ibcon#read 6, iclass 3, count 0 2006.257.07:41:05.97#ibcon#end of sib2, iclass 3, count 0 2006.257.07:41:05.97#ibcon#*mode == 0, iclass 3, count 0 2006.257.07:41:05.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.07:41:05.97#ibcon#[25=USB\r\n] 2006.257.07:41:05.97#ibcon#*before write, iclass 3, count 0 2006.257.07:41:05.97#ibcon#enter sib2, iclass 3, count 0 2006.257.07:41:05.97#ibcon#flushed, iclass 3, count 0 2006.257.07:41:05.97#ibcon#about to write, iclass 3, count 0 2006.257.07:41:05.97#ibcon#wrote, iclass 3, count 0 2006.257.07:41:05.97#ibcon#about to read 3, iclass 3, count 0 2006.257.07:41:06.00#ibcon#read 3, iclass 3, count 0 2006.257.07:41:06.00#ibcon#about to read 4, iclass 3, count 0 2006.257.07:41:06.00#ibcon#read 4, iclass 3, count 0 2006.257.07:41:06.00#ibcon#about to read 5, iclass 3, count 0 2006.257.07:41:06.00#ibcon#read 5, iclass 3, count 0 2006.257.07:41:06.00#ibcon#about to read 6, iclass 3, count 0 2006.257.07:41:06.00#ibcon#read 6, iclass 3, count 0 2006.257.07:41:06.00#ibcon#end of sib2, iclass 3, count 0 2006.257.07:41:06.00#ibcon#*after write, iclass 3, count 0 2006.257.07:41:06.00#ibcon#*before return 0, iclass 3, count 0 2006.257.07:41:06.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:06.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:06.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.07:41:06.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.07:41:06.00$vck44/valo=3,564.99 2006.257.07:41:06.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.07:41:06.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.07:41:06.00#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:06.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:06.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:06.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:06.00#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:41:06.00#ibcon#first serial, iclass 5, count 0 2006.257.07:41:06.00#ibcon#enter sib2, iclass 5, count 0 2006.257.07:41:06.00#ibcon#flushed, iclass 5, count 0 2006.257.07:41:06.00#ibcon#about to write, iclass 5, count 0 2006.257.07:41:06.00#ibcon#wrote, iclass 5, count 0 2006.257.07:41:06.00#ibcon#about to read 3, iclass 5, count 0 2006.257.07:41:06.02#ibcon#read 3, iclass 5, count 0 2006.257.07:41:06.02#ibcon#about to read 4, iclass 5, count 0 2006.257.07:41:06.02#ibcon#read 4, iclass 5, count 0 2006.257.07:41:06.02#ibcon#about to read 5, iclass 5, count 0 2006.257.07:41:06.02#ibcon#read 5, iclass 5, count 0 2006.257.07:41:06.02#ibcon#about to read 6, iclass 5, count 0 2006.257.07:41:06.02#ibcon#read 6, iclass 5, count 0 2006.257.07:41:06.02#ibcon#end of sib2, iclass 5, count 0 2006.257.07:41:06.02#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:41:06.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:41:06.02#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.07:41:06.02#ibcon#*before write, iclass 5, count 0 2006.257.07:41:06.02#ibcon#enter sib2, iclass 5, count 0 2006.257.07:41:06.02#ibcon#flushed, iclass 5, count 0 2006.257.07:41:06.02#ibcon#about to write, iclass 5, count 0 2006.257.07:41:06.02#ibcon#wrote, iclass 5, count 0 2006.257.07:41:06.02#ibcon#about to read 3, iclass 5, count 0 2006.257.07:41:06.06#ibcon#read 3, iclass 5, count 0 2006.257.07:41:06.06#ibcon#about to read 4, iclass 5, count 0 2006.257.07:41:06.06#ibcon#read 4, iclass 5, count 0 2006.257.07:41:06.06#ibcon#about to read 5, iclass 5, count 0 2006.257.07:41:06.06#ibcon#read 5, iclass 5, count 0 2006.257.07:41:06.06#ibcon#about to read 6, iclass 5, count 0 2006.257.07:41:06.06#ibcon#read 6, iclass 5, count 0 2006.257.07:41:06.06#ibcon#end of sib2, iclass 5, count 0 2006.257.07:41:06.06#ibcon#*after write, iclass 5, count 0 2006.257.07:41:06.06#ibcon#*before return 0, iclass 5, count 0 2006.257.07:41:06.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:06.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:06.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:41:06.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:41:06.06$vck44/va=3,8 2006.257.07:41:06.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.07:41:06.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.07:41:06.06#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:06.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:06.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:06.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:06.12#ibcon#enter wrdev, iclass 7, count 2 2006.257.07:41:06.12#ibcon#first serial, iclass 7, count 2 2006.257.07:41:06.12#ibcon#enter sib2, iclass 7, count 2 2006.257.07:41:06.12#ibcon#flushed, iclass 7, count 2 2006.257.07:41:06.12#ibcon#about to write, iclass 7, count 2 2006.257.07:41:06.12#ibcon#wrote, iclass 7, count 2 2006.257.07:41:06.12#ibcon#about to read 3, iclass 7, count 2 2006.257.07:41:06.14#ibcon#read 3, iclass 7, count 2 2006.257.07:41:06.14#ibcon#about to read 4, iclass 7, count 2 2006.257.07:41:06.14#ibcon#read 4, iclass 7, count 2 2006.257.07:41:06.14#ibcon#about to read 5, iclass 7, count 2 2006.257.07:41:06.14#ibcon#read 5, iclass 7, count 2 2006.257.07:41:06.14#ibcon#about to read 6, iclass 7, count 2 2006.257.07:41:06.14#ibcon#read 6, iclass 7, count 2 2006.257.07:41:06.14#ibcon#end of sib2, iclass 7, count 2 2006.257.07:41:06.14#ibcon#*mode == 0, iclass 7, count 2 2006.257.07:41:06.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.07:41:06.14#ibcon#[25=AT03-08\r\n] 2006.257.07:41:06.14#ibcon#*before write, iclass 7, count 2 2006.257.07:41:06.14#ibcon#enter sib2, iclass 7, count 2 2006.257.07:41:06.14#ibcon#flushed, iclass 7, count 2 2006.257.07:41:06.14#ibcon#about to write, iclass 7, count 2 2006.257.07:41:06.14#ibcon#wrote, iclass 7, count 2 2006.257.07:41:06.14#ibcon#about to read 3, iclass 7, count 2 2006.257.07:41:06.17#ibcon#read 3, iclass 7, count 2 2006.257.07:41:06.17#ibcon#about to read 4, iclass 7, count 2 2006.257.07:41:06.17#ibcon#read 4, iclass 7, count 2 2006.257.07:41:06.17#ibcon#about to read 5, iclass 7, count 2 2006.257.07:41:06.17#ibcon#read 5, iclass 7, count 2 2006.257.07:41:06.17#ibcon#about to read 6, iclass 7, count 2 2006.257.07:41:06.17#ibcon#read 6, iclass 7, count 2 2006.257.07:41:06.17#ibcon#end of sib2, iclass 7, count 2 2006.257.07:41:06.17#ibcon#*after write, iclass 7, count 2 2006.257.07:41:06.17#ibcon#*before return 0, iclass 7, count 2 2006.257.07:41:06.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:06.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:06.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.07:41:06.17#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:06.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:06.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:06.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:06.29#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:41:06.29#ibcon#first serial, iclass 7, count 0 2006.257.07:41:06.29#ibcon#enter sib2, iclass 7, count 0 2006.257.07:41:06.29#ibcon#flushed, iclass 7, count 0 2006.257.07:41:06.29#ibcon#about to write, iclass 7, count 0 2006.257.07:41:06.29#ibcon#wrote, iclass 7, count 0 2006.257.07:41:06.29#ibcon#about to read 3, iclass 7, count 0 2006.257.07:41:06.31#ibcon#read 3, iclass 7, count 0 2006.257.07:41:06.31#ibcon#about to read 4, iclass 7, count 0 2006.257.07:41:06.31#ibcon#read 4, iclass 7, count 0 2006.257.07:41:06.31#ibcon#about to read 5, iclass 7, count 0 2006.257.07:41:06.31#ibcon#read 5, iclass 7, count 0 2006.257.07:41:06.31#ibcon#about to read 6, iclass 7, count 0 2006.257.07:41:06.31#ibcon#read 6, iclass 7, count 0 2006.257.07:41:06.31#ibcon#end of sib2, iclass 7, count 0 2006.257.07:41:06.31#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:41:06.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:41:06.31#ibcon#[25=USB\r\n] 2006.257.07:41:06.31#ibcon#*before write, iclass 7, count 0 2006.257.07:41:06.31#ibcon#enter sib2, iclass 7, count 0 2006.257.07:41:06.31#ibcon#flushed, iclass 7, count 0 2006.257.07:41:06.31#ibcon#about to write, iclass 7, count 0 2006.257.07:41:06.31#ibcon#wrote, iclass 7, count 0 2006.257.07:41:06.31#ibcon#about to read 3, iclass 7, count 0 2006.257.07:41:06.34#ibcon#read 3, iclass 7, count 0 2006.257.07:41:06.34#ibcon#about to read 4, iclass 7, count 0 2006.257.07:41:06.34#ibcon#read 4, iclass 7, count 0 2006.257.07:41:06.34#ibcon#about to read 5, iclass 7, count 0 2006.257.07:41:06.34#ibcon#read 5, iclass 7, count 0 2006.257.07:41:06.34#ibcon#about to read 6, iclass 7, count 0 2006.257.07:41:06.34#ibcon#read 6, iclass 7, count 0 2006.257.07:41:06.34#ibcon#end of sib2, iclass 7, count 0 2006.257.07:41:06.34#ibcon#*after write, iclass 7, count 0 2006.257.07:41:06.34#ibcon#*before return 0, iclass 7, count 0 2006.257.07:41:06.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:06.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:06.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:41:06.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:41:06.34$vck44/valo=4,624.99 2006.257.07:41:06.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.07:41:06.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.07:41:06.34#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:06.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:06.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:06.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:06.34#ibcon#enter wrdev, iclass 11, count 0 2006.257.07:41:06.34#ibcon#first serial, iclass 11, count 0 2006.257.07:41:06.34#ibcon#enter sib2, iclass 11, count 0 2006.257.07:41:06.34#ibcon#flushed, iclass 11, count 0 2006.257.07:41:06.34#ibcon#about to write, iclass 11, count 0 2006.257.07:41:06.34#ibcon#wrote, iclass 11, count 0 2006.257.07:41:06.34#ibcon#about to read 3, iclass 11, count 0 2006.257.07:41:06.36#ibcon#read 3, iclass 11, count 0 2006.257.07:41:06.36#ibcon#about to read 4, iclass 11, count 0 2006.257.07:41:06.36#ibcon#read 4, iclass 11, count 0 2006.257.07:41:06.36#ibcon#about to read 5, iclass 11, count 0 2006.257.07:41:06.36#ibcon#read 5, iclass 11, count 0 2006.257.07:41:06.36#ibcon#about to read 6, iclass 11, count 0 2006.257.07:41:06.36#ibcon#read 6, iclass 11, count 0 2006.257.07:41:06.36#ibcon#end of sib2, iclass 11, count 0 2006.257.07:41:06.36#ibcon#*mode == 0, iclass 11, count 0 2006.257.07:41:06.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.07:41:06.36#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.07:41:06.36#ibcon#*before write, iclass 11, count 0 2006.257.07:41:06.36#ibcon#enter sib2, iclass 11, count 0 2006.257.07:41:06.36#ibcon#flushed, iclass 11, count 0 2006.257.07:41:06.36#ibcon#about to write, iclass 11, count 0 2006.257.07:41:06.36#ibcon#wrote, iclass 11, count 0 2006.257.07:41:06.36#ibcon#about to read 3, iclass 11, count 0 2006.257.07:41:06.40#ibcon#read 3, iclass 11, count 0 2006.257.07:41:06.40#ibcon#about to read 4, iclass 11, count 0 2006.257.07:41:06.40#ibcon#read 4, iclass 11, count 0 2006.257.07:41:06.40#ibcon#about to read 5, iclass 11, count 0 2006.257.07:41:06.40#ibcon#read 5, iclass 11, count 0 2006.257.07:41:06.40#ibcon#about to read 6, iclass 11, count 0 2006.257.07:41:06.40#ibcon#read 6, iclass 11, count 0 2006.257.07:41:06.40#ibcon#end of sib2, iclass 11, count 0 2006.257.07:41:06.40#ibcon#*after write, iclass 11, count 0 2006.257.07:41:06.40#ibcon#*before return 0, iclass 11, count 0 2006.257.07:41:06.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:06.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:06.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.07:41:06.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.07:41:06.40$vck44/va=4,7 2006.257.07:41:06.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.07:41:06.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.07:41:06.40#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:06.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:06.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:06.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:06.46#ibcon#enter wrdev, iclass 13, count 2 2006.257.07:41:06.46#ibcon#first serial, iclass 13, count 2 2006.257.07:41:06.46#ibcon#enter sib2, iclass 13, count 2 2006.257.07:41:06.46#ibcon#flushed, iclass 13, count 2 2006.257.07:41:06.46#ibcon#about to write, iclass 13, count 2 2006.257.07:41:06.46#ibcon#wrote, iclass 13, count 2 2006.257.07:41:06.46#ibcon#about to read 3, iclass 13, count 2 2006.257.07:41:06.48#ibcon#read 3, iclass 13, count 2 2006.257.07:41:06.48#ibcon#about to read 4, iclass 13, count 2 2006.257.07:41:06.48#ibcon#read 4, iclass 13, count 2 2006.257.07:41:06.48#ibcon#about to read 5, iclass 13, count 2 2006.257.07:41:06.48#ibcon#read 5, iclass 13, count 2 2006.257.07:41:06.48#ibcon#about to read 6, iclass 13, count 2 2006.257.07:41:06.48#ibcon#read 6, iclass 13, count 2 2006.257.07:41:06.48#ibcon#end of sib2, iclass 13, count 2 2006.257.07:41:06.48#ibcon#*mode == 0, iclass 13, count 2 2006.257.07:41:06.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.07:41:06.48#ibcon#[25=AT04-07\r\n] 2006.257.07:41:06.48#ibcon#*before write, iclass 13, count 2 2006.257.07:41:06.48#ibcon#enter sib2, iclass 13, count 2 2006.257.07:41:06.48#ibcon#flushed, iclass 13, count 2 2006.257.07:41:06.48#ibcon#about to write, iclass 13, count 2 2006.257.07:41:06.48#ibcon#wrote, iclass 13, count 2 2006.257.07:41:06.48#ibcon#about to read 3, iclass 13, count 2 2006.257.07:41:06.51#ibcon#read 3, iclass 13, count 2 2006.257.07:41:06.51#ibcon#about to read 4, iclass 13, count 2 2006.257.07:41:06.51#ibcon#read 4, iclass 13, count 2 2006.257.07:41:06.51#ibcon#about to read 5, iclass 13, count 2 2006.257.07:41:06.51#ibcon#read 5, iclass 13, count 2 2006.257.07:41:06.51#ibcon#about to read 6, iclass 13, count 2 2006.257.07:41:06.51#ibcon#read 6, iclass 13, count 2 2006.257.07:41:06.51#ibcon#end of sib2, iclass 13, count 2 2006.257.07:41:06.51#ibcon#*after write, iclass 13, count 2 2006.257.07:41:06.51#ibcon#*before return 0, iclass 13, count 2 2006.257.07:41:06.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:06.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:06.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.07:41:06.51#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:06.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:06.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:06.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:06.63#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:41:06.63#ibcon#first serial, iclass 13, count 0 2006.257.07:41:06.63#ibcon#enter sib2, iclass 13, count 0 2006.257.07:41:06.63#ibcon#flushed, iclass 13, count 0 2006.257.07:41:06.63#ibcon#about to write, iclass 13, count 0 2006.257.07:41:06.63#ibcon#wrote, iclass 13, count 0 2006.257.07:41:06.63#ibcon#about to read 3, iclass 13, count 0 2006.257.07:41:06.65#ibcon#read 3, iclass 13, count 0 2006.257.07:41:06.65#ibcon#about to read 4, iclass 13, count 0 2006.257.07:41:06.65#ibcon#read 4, iclass 13, count 0 2006.257.07:41:06.65#ibcon#about to read 5, iclass 13, count 0 2006.257.07:41:06.65#ibcon#read 5, iclass 13, count 0 2006.257.07:41:06.65#ibcon#about to read 6, iclass 13, count 0 2006.257.07:41:06.65#ibcon#read 6, iclass 13, count 0 2006.257.07:41:06.65#ibcon#end of sib2, iclass 13, count 0 2006.257.07:41:06.65#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:41:06.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:41:06.65#ibcon#[25=USB\r\n] 2006.257.07:41:06.65#ibcon#*before write, iclass 13, count 0 2006.257.07:41:06.65#ibcon#enter sib2, iclass 13, count 0 2006.257.07:41:06.65#ibcon#flushed, iclass 13, count 0 2006.257.07:41:06.65#ibcon#about to write, iclass 13, count 0 2006.257.07:41:06.65#ibcon#wrote, iclass 13, count 0 2006.257.07:41:06.65#ibcon#about to read 3, iclass 13, count 0 2006.257.07:41:06.68#ibcon#read 3, iclass 13, count 0 2006.257.07:41:06.68#ibcon#about to read 4, iclass 13, count 0 2006.257.07:41:06.68#ibcon#read 4, iclass 13, count 0 2006.257.07:41:06.68#ibcon#about to read 5, iclass 13, count 0 2006.257.07:41:06.68#ibcon#read 5, iclass 13, count 0 2006.257.07:41:06.68#ibcon#about to read 6, iclass 13, count 0 2006.257.07:41:06.68#ibcon#read 6, iclass 13, count 0 2006.257.07:41:06.68#ibcon#end of sib2, iclass 13, count 0 2006.257.07:41:06.68#ibcon#*after write, iclass 13, count 0 2006.257.07:41:06.68#ibcon#*before return 0, iclass 13, count 0 2006.257.07:41:06.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:06.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:06.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:41:06.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:41:06.68$vck44/valo=5,734.99 2006.257.07:41:06.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.07:41:06.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.07:41:06.68#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:06.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:06.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:06.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:06.68#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:41:06.68#ibcon#first serial, iclass 15, count 0 2006.257.07:41:06.68#ibcon#enter sib2, iclass 15, count 0 2006.257.07:41:06.68#ibcon#flushed, iclass 15, count 0 2006.257.07:41:06.68#ibcon#about to write, iclass 15, count 0 2006.257.07:41:06.68#ibcon#wrote, iclass 15, count 0 2006.257.07:41:06.68#ibcon#about to read 3, iclass 15, count 0 2006.257.07:41:06.70#ibcon#read 3, iclass 15, count 0 2006.257.07:41:06.70#ibcon#about to read 4, iclass 15, count 0 2006.257.07:41:06.70#ibcon#read 4, iclass 15, count 0 2006.257.07:41:06.70#ibcon#about to read 5, iclass 15, count 0 2006.257.07:41:06.70#ibcon#read 5, iclass 15, count 0 2006.257.07:41:06.70#ibcon#about to read 6, iclass 15, count 0 2006.257.07:41:06.70#ibcon#read 6, iclass 15, count 0 2006.257.07:41:06.70#ibcon#end of sib2, iclass 15, count 0 2006.257.07:41:06.70#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:41:06.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:41:06.70#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.07:41:06.70#ibcon#*before write, iclass 15, count 0 2006.257.07:41:06.70#ibcon#enter sib2, iclass 15, count 0 2006.257.07:41:06.70#ibcon#flushed, iclass 15, count 0 2006.257.07:41:06.70#ibcon#about to write, iclass 15, count 0 2006.257.07:41:06.70#ibcon#wrote, iclass 15, count 0 2006.257.07:41:06.70#ibcon#about to read 3, iclass 15, count 0 2006.257.07:41:06.74#ibcon#read 3, iclass 15, count 0 2006.257.07:41:06.74#ibcon#about to read 4, iclass 15, count 0 2006.257.07:41:06.74#ibcon#read 4, iclass 15, count 0 2006.257.07:41:06.74#ibcon#about to read 5, iclass 15, count 0 2006.257.07:41:06.74#ibcon#read 5, iclass 15, count 0 2006.257.07:41:06.74#ibcon#about to read 6, iclass 15, count 0 2006.257.07:41:06.74#ibcon#read 6, iclass 15, count 0 2006.257.07:41:06.74#ibcon#end of sib2, iclass 15, count 0 2006.257.07:41:06.74#ibcon#*after write, iclass 15, count 0 2006.257.07:41:06.74#ibcon#*before return 0, iclass 15, count 0 2006.257.07:41:06.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:06.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:06.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:41:06.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:41:06.74$vck44/va=5,4 2006.257.07:41:06.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.07:41:06.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.07:41:06.74#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:06.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:06.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:06.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:06.80#ibcon#enter wrdev, iclass 17, count 2 2006.257.07:41:06.80#ibcon#first serial, iclass 17, count 2 2006.257.07:41:06.80#ibcon#enter sib2, iclass 17, count 2 2006.257.07:41:06.80#ibcon#flushed, iclass 17, count 2 2006.257.07:41:06.80#ibcon#about to write, iclass 17, count 2 2006.257.07:41:06.80#ibcon#wrote, iclass 17, count 2 2006.257.07:41:06.80#ibcon#about to read 3, iclass 17, count 2 2006.257.07:41:06.82#ibcon#read 3, iclass 17, count 2 2006.257.07:41:06.82#ibcon#about to read 4, iclass 17, count 2 2006.257.07:41:06.82#ibcon#read 4, iclass 17, count 2 2006.257.07:41:06.82#ibcon#about to read 5, iclass 17, count 2 2006.257.07:41:06.82#ibcon#read 5, iclass 17, count 2 2006.257.07:41:06.82#ibcon#about to read 6, iclass 17, count 2 2006.257.07:41:06.82#ibcon#read 6, iclass 17, count 2 2006.257.07:41:06.82#ibcon#end of sib2, iclass 17, count 2 2006.257.07:41:06.82#ibcon#*mode == 0, iclass 17, count 2 2006.257.07:41:06.82#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.07:41:06.82#ibcon#[25=AT05-04\r\n] 2006.257.07:41:06.82#ibcon#*before write, iclass 17, count 2 2006.257.07:41:06.82#ibcon#enter sib2, iclass 17, count 2 2006.257.07:41:06.82#ibcon#flushed, iclass 17, count 2 2006.257.07:41:06.82#ibcon#about to write, iclass 17, count 2 2006.257.07:41:06.82#ibcon#wrote, iclass 17, count 2 2006.257.07:41:06.82#ibcon#about to read 3, iclass 17, count 2 2006.257.07:41:06.85#ibcon#read 3, iclass 17, count 2 2006.257.07:41:06.85#ibcon#about to read 4, iclass 17, count 2 2006.257.07:41:06.85#ibcon#read 4, iclass 17, count 2 2006.257.07:41:06.85#ibcon#about to read 5, iclass 17, count 2 2006.257.07:41:06.85#ibcon#read 5, iclass 17, count 2 2006.257.07:41:06.85#ibcon#about to read 6, iclass 17, count 2 2006.257.07:41:06.85#ibcon#read 6, iclass 17, count 2 2006.257.07:41:06.85#ibcon#end of sib2, iclass 17, count 2 2006.257.07:41:06.85#ibcon#*after write, iclass 17, count 2 2006.257.07:41:06.85#ibcon#*before return 0, iclass 17, count 2 2006.257.07:41:06.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:06.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:06.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.07:41:06.85#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:06.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:06.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:06.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:06.97#ibcon#enter wrdev, iclass 17, count 0 2006.257.07:41:06.97#ibcon#first serial, iclass 17, count 0 2006.257.07:41:06.97#ibcon#enter sib2, iclass 17, count 0 2006.257.07:41:06.97#ibcon#flushed, iclass 17, count 0 2006.257.07:41:06.97#ibcon#about to write, iclass 17, count 0 2006.257.07:41:06.97#ibcon#wrote, iclass 17, count 0 2006.257.07:41:06.97#ibcon#about to read 3, iclass 17, count 0 2006.257.07:41:06.99#ibcon#read 3, iclass 17, count 0 2006.257.07:41:06.99#ibcon#about to read 4, iclass 17, count 0 2006.257.07:41:06.99#ibcon#read 4, iclass 17, count 0 2006.257.07:41:06.99#ibcon#about to read 5, iclass 17, count 0 2006.257.07:41:06.99#ibcon#read 5, iclass 17, count 0 2006.257.07:41:06.99#ibcon#about to read 6, iclass 17, count 0 2006.257.07:41:06.99#ibcon#read 6, iclass 17, count 0 2006.257.07:41:06.99#ibcon#end of sib2, iclass 17, count 0 2006.257.07:41:06.99#ibcon#*mode == 0, iclass 17, count 0 2006.257.07:41:06.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.07:41:06.99#ibcon#[25=USB\r\n] 2006.257.07:41:06.99#ibcon#*before write, iclass 17, count 0 2006.257.07:41:06.99#ibcon#enter sib2, iclass 17, count 0 2006.257.07:41:06.99#ibcon#flushed, iclass 17, count 0 2006.257.07:41:06.99#ibcon#about to write, iclass 17, count 0 2006.257.07:41:06.99#ibcon#wrote, iclass 17, count 0 2006.257.07:41:06.99#ibcon#about to read 3, iclass 17, count 0 2006.257.07:41:07.02#ibcon#read 3, iclass 17, count 0 2006.257.07:41:07.02#ibcon#about to read 4, iclass 17, count 0 2006.257.07:41:07.02#ibcon#read 4, iclass 17, count 0 2006.257.07:41:07.02#ibcon#about to read 5, iclass 17, count 0 2006.257.07:41:07.02#ibcon#read 5, iclass 17, count 0 2006.257.07:41:07.02#ibcon#about to read 6, iclass 17, count 0 2006.257.07:41:07.02#ibcon#read 6, iclass 17, count 0 2006.257.07:41:07.02#ibcon#end of sib2, iclass 17, count 0 2006.257.07:41:07.02#ibcon#*after write, iclass 17, count 0 2006.257.07:41:07.02#ibcon#*before return 0, iclass 17, count 0 2006.257.07:41:07.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:07.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:07.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.07:41:07.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.07:41:07.02$vck44/valo=6,814.99 2006.257.07:41:07.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.07:41:07.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.07:41:07.02#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:07.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:07.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:07.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:07.02#ibcon#enter wrdev, iclass 19, count 0 2006.257.07:41:07.02#ibcon#first serial, iclass 19, count 0 2006.257.07:41:07.02#ibcon#enter sib2, iclass 19, count 0 2006.257.07:41:07.02#ibcon#flushed, iclass 19, count 0 2006.257.07:41:07.02#ibcon#about to write, iclass 19, count 0 2006.257.07:41:07.02#ibcon#wrote, iclass 19, count 0 2006.257.07:41:07.02#ibcon#about to read 3, iclass 19, count 0 2006.257.07:41:07.04#ibcon#read 3, iclass 19, count 0 2006.257.07:41:07.04#ibcon#about to read 4, iclass 19, count 0 2006.257.07:41:07.04#ibcon#read 4, iclass 19, count 0 2006.257.07:41:07.04#ibcon#about to read 5, iclass 19, count 0 2006.257.07:41:07.04#ibcon#read 5, iclass 19, count 0 2006.257.07:41:07.04#ibcon#about to read 6, iclass 19, count 0 2006.257.07:41:07.04#ibcon#read 6, iclass 19, count 0 2006.257.07:41:07.04#ibcon#end of sib2, iclass 19, count 0 2006.257.07:41:07.04#ibcon#*mode == 0, iclass 19, count 0 2006.257.07:41:07.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.07:41:07.04#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.07:41:07.04#ibcon#*before write, iclass 19, count 0 2006.257.07:41:07.04#ibcon#enter sib2, iclass 19, count 0 2006.257.07:41:07.04#ibcon#flushed, iclass 19, count 0 2006.257.07:41:07.04#ibcon#about to write, iclass 19, count 0 2006.257.07:41:07.04#ibcon#wrote, iclass 19, count 0 2006.257.07:41:07.04#ibcon#about to read 3, iclass 19, count 0 2006.257.07:41:07.08#ibcon#read 3, iclass 19, count 0 2006.257.07:41:07.08#ibcon#about to read 4, iclass 19, count 0 2006.257.07:41:07.08#ibcon#read 4, iclass 19, count 0 2006.257.07:41:07.08#ibcon#about to read 5, iclass 19, count 0 2006.257.07:41:07.08#ibcon#read 5, iclass 19, count 0 2006.257.07:41:07.08#ibcon#about to read 6, iclass 19, count 0 2006.257.07:41:07.08#ibcon#read 6, iclass 19, count 0 2006.257.07:41:07.08#ibcon#end of sib2, iclass 19, count 0 2006.257.07:41:07.08#ibcon#*after write, iclass 19, count 0 2006.257.07:41:07.08#ibcon#*before return 0, iclass 19, count 0 2006.257.07:41:07.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:07.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:07.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.07:41:07.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.07:41:07.08$vck44/va=6,4 2006.257.07:41:07.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.07:41:07.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.07:41:07.08#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:07.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:07.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:07.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:07.14#ibcon#enter wrdev, iclass 21, count 2 2006.257.07:41:07.14#ibcon#first serial, iclass 21, count 2 2006.257.07:41:07.14#ibcon#enter sib2, iclass 21, count 2 2006.257.07:41:07.14#ibcon#flushed, iclass 21, count 2 2006.257.07:41:07.14#ibcon#about to write, iclass 21, count 2 2006.257.07:41:07.14#ibcon#wrote, iclass 21, count 2 2006.257.07:41:07.14#ibcon#about to read 3, iclass 21, count 2 2006.257.07:41:07.16#ibcon#read 3, iclass 21, count 2 2006.257.07:41:07.16#ibcon#about to read 4, iclass 21, count 2 2006.257.07:41:07.16#ibcon#read 4, iclass 21, count 2 2006.257.07:41:07.16#ibcon#about to read 5, iclass 21, count 2 2006.257.07:41:07.16#ibcon#read 5, iclass 21, count 2 2006.257.07:41:07.16#ibcon#about to read 6, iclass 21, count 2 2006.257.07:41:07.16#ibcon#read 6, iclass 21, count 2 2006.257.07:41:07.16#ibcon#end of sib2, iclass 21, count 2 2006.257.07:41:07.16#ibcon#*mode == 0, iclass 21, count 2 2006.257.07:41:07.16#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.07:41:07.16#ibcon#[25=AT06-04\r\n] 2006.257.07:41:07.16#ibcon#*before write, iclass 21, count 2 2006.257.07:41:07.16#ibcon#enter sib2, iclass 21, count 2 2006.257.07:41:07.16#ibcon#flushed, iclass 21, count 2 2006.257.07:41:07.16#ibcon#about to write, iclass 21, count 2 2006.257.07:41:07.16#ibcon#wrote, iclass 21, count 2 2006.257.07:41:07.16#ibcon#about to read 3, iclass 21, count 2 2006.257.07:41:07.19#ibcon#read 3, iclass 21, count 2 2006.257.07:41:07.19#ibcon#about to read 4, iclass 21, count 2 2006.257.07:41:07.19#ibcon#read 4, iclass 21, count 2 2006.257.07:41:07.19#ibcon#about to read 5, iclass 21, count 2 2006.257.07:41:07.19#ibcon#read 5, iclass 21, count 2 2006.257.07:41:07.19#ibcon#about to read 6, iclass 21, count 2 2006.257.07:41:07.19#ibcon#read 6, iclass 21, count 2 2006.257.07:41:07.19#ibcon#end of sib2, iclass 21, count 2 2006.257.07:41:07.19#ibcon#*after write, iclass 21, count 2 2006.257.07:41:07.19#ibcon#*before return 0, iclass 21, count 2 2006.257.07:41:07.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:07.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:07.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.07:41:07.19#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:07.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:07.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:07.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:07.31#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:41:07.31#ibcon#first serial, iclass 21, count 0 2006.257.07:41:07.31#ibcon#enter sib2, iclass 21, count 0 2006.257.07:41:07.31#ibcon#flushed, iclass 21, count 0 2006.257.07:41:07.31#ibcon#about to write, iclass 21, count 0 2006.257.07:41:07.31#ibcon#wrote, iclass 21, count 0 2006.257.07:41:07.31#ibcon#about to read 3, iclass 21, count 0 2006.257.07:41:07.33#ibcon#read 3, iclass 21, count 0 2006.257.07:41:07.33#ibcon#about to read 4, iclass 21, count 0 2006.257.07:41:07.33#ibcon#read 4, iclass 21, count 0 2006.257.07:41:07.33#ibcon#about to read 5, iclass 21, count 0 2006.257.07:41:07.33#ibcon#read 5, iclass 21, count 0 2006.257.07:41:07.33#ibcon#about to read 6, iclass 21, count 0 2006.257.07:41:07.33#ibcon#read 6, iclass 21, count 0 2006.257.07:41:07.33#ibcon#end of sib2, iclass 21, count 0 2006.257.07:41:07.33#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:41:07.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:41:07.33#ibcon#[25=USB\r\n] 2006.257.07:41:07.33#ibcon#*before write, iclass 21, count 0 2006.257.07:41:07.33#ibcon#enter sib2, iclass 21, count 0 2006.257.07:41:07.33#ibcon#flushed, iclass 21, count 0 2006.257.07:41:07.33#ibcon#about to write, iclass 21, count 0 2006.257.07:41:07.33#ibcon#wrote, iclass 21, count 0 2006.257.07:41:07.33#ibcon#about to read 3, iclass 21, count 0 2006.257.07:41:07.36#ibcon#read 3, iclass 21, count 0 2006.257.07:41:07.36#ibcon#about to read 4, iclass 21, count 0 2006.257.07:41:07.36#ibcon#read 4, iclass 21, count 0 2006.257.07:41:07.36#ibcon#about to read 5, iclass 21, count 0 2006.257.07:41:07.36#ibcon#read 5, iclass 21, count 0 2006.257.07:41:07.36#ibcon#about to read 6, iclass 21, count 0 2006.257.07:41:07.36#ibcon#read 6, iclass 21, count 0 2006.257.07:41:07.36#ibcon#end of sib2, iclass 21, count 0 2006.257.07:41:07.36#ibcon#*after write, iclass 21, count 0 2006.257.07:41:07.36#ibcon#*before return 0, iclass 21, count 0 2006.257.07:41:07.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:07.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:07.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:41:07.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:41:07.36$vck44/valo=7,864.99 2006.257.07:41:07.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.07:41:07.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.07:41:07.36#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:07.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:07.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:07.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:07.36#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:41:07.36#ibcon#first serial, iclass 23, count 0 2006.257.07:41:07.36#ibcon#enter sib2, iclass 23, count 0 2006.257.07:41:07.36#ibcon#flushed, iclass 23, count 0 2006.257.07:41:07.36#ibcon#about to write, iclass 23, count 0 2006.257.07:41:07.36#ibcon#wrote, iclass 23, count 0 2006.257.07:41:07.36#ibcon#about to read 3, iclass 23, count 0 2006.257.07:41:07.38#ibcon#read 3, iclass 23, count 0 2006.257.07:41:07.38#ibcon#about to read 4, iclass 23, count 0 2006.257.07:41:07.38#ibcon#read 4, iclass 23, count 0 2006.257.07:41:07.38#ibcon#about to read 5, iclass 23, count 0 2006.257.07:41:07.38#ibcon#read 5, iclass 23, count 0 2006.257.07:41:07.38#ibcon#about to read 6, iclass 23, count 0 2006.257.07:41:07.38#ibcon#read 6, iclass 23, count 0 2006.257.07:41:07.38#ibcon#end of sib2, iclass 23, count 0 2006.257.07:41:07.38#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:41:07.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:41:07.38#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.07:41:07.38#ibcon#*before write, iclass 23, count 0 2006.257.07:41:07.38#ibcon#enter sib2, iclass 23, count 0 2006.257.07:41:07.38#ibcon#flushed, iclass 23, count 0 2006.257.07:41:07.38#ibcon#about to write, iclass 23, count 0 2006.257.07:41:07.38#ibcon#wrote, iclass 23, count 0 2006.257.07:41:07.38#ibcon#about to read 3, iclass 23, count 0 2006.257.07:41:07.42#ibcon#read 3, iclass 23, count 0 2006.257.07:41:07.42#ibcon#about to read 4, iclass 23, count 0 2006.257.07:41:07.42#ibcon#read 4, iclass 23, count 0 2006.257.07:41:07.42#ibcon#about to read 5, iclass 23, count 0 2006.257.07:41:07.42#ibcon#read 5, iclass 23, count 0 2006.257.07:41:07.42#ibcon#about to read 6, iclass 23, count 0 2006.257.07:41:07.42#ibcon#read 6, iclass 23, count 0 2006.257.07:41:07.42#ibcon#end of sib2, iclass 23, count 0 2006.257.07:41:07.42#ibcon#*after write, iclass 23, count 0 2006.257.07:41:07.42#ibcon#*before return 0, iclass 23, count 0 2006.257.07:41:07.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:07.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:07.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:41:07.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:41:07.42$vck44/va=7,4 2006.257.07:41:07.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.07:41:07.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.07:41:07.42#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:07.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:07.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:07.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:07.48#ibcon#enter wrdev, iclass 25, count 2 2006.257.07:41:07.48#ibcon#first serial, iclass 25, count 2 2006.257.07:41:07.48#ibcon#enter sib2, iclass 25, count 2 2006.257.07:41:07.48#ibcon#flushed, iclass 25, count 2 2006.257.07:41:07.48#ibcon#about to write, iclass 25, count 2 2006.257.07:41:07.48#ibcon#wrote, iclass 25, count 2 2006.257.07:41:07.48#ibcon#about to read 3, iclass 25, count 2 2006.257.07:41:07.50#ibcon#read 3, iclass 25, count 2 2006.257.07:41:07.50#ibcon#about to read 4, iclass 25, count 2 2006.257.07:41:07.50#ibcon#read 4, iclass 25, count 2 2006.257.07:41:07.50#ibcon#about to read 5, iclass 25, count 2 2006.257.07:41:07.50#ibcon#read 5, iclass 25, count 2 2006.257.07:41:07.50#ibcon#about to read 6, iclass 25, count 2 2006.257.07:41:07.50#ibcon#read 6, iclass 25, count 2 2006.257.07:41:07.50#ibcon#end of sib2, iclass 25, count 2 2006.257.07:41:07.50#ibcon#*mode == 0, iclass 25, count 2 2006.257.07:41:07.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.07:41:07.50#ibcon#[25=AT07-04\r\n] 2006.257.07:41:07.50#ibcon#*before write, iclass 25, count 2 2006.257.07:41:07.50#ibcon#enter sib2, iclass 25, count 2 2006.257.07:41:07.50#ibcon#flushed, iclass 25, count 2 2006.257.07:41:07.50#ibcon#about to write, iclass 25, count 2 2006.257.07:41:07.50#ibcon#wrote, iclass 25, count 2 2006.257.07:41:07.50#ibcon#about to read 3, iclass 25, count 2 2006.257.07:41:07.53#ibcon#read 3, iclass 25, count 2 2006.257.07:41:07.53#ibcon#about to read 4, iclass 25, count 2 2006.257.07:41:07.53#ibcon#read 4, iclass 25, count 2 2006.257.07:41:07.53#ibcon#about to read 5, iclass 25, count 2 2006.257.07:41:07.53#ibcon#read 5, iclass 25, count 2 2006.257.07:41:07.53#ibcon#about to read 6, iclass 25, count 2 2006.257.07:41:07.53#ibcon#read 6, iclass 25, count 2 2006.257.07:41:07.53#ibcon#end of sib2, iclass 25, count 2 2006.257.07:41:07.53#ibcon#*after write, iclass 25, count 2 2006.257.07:41:07.53#ibcon#*before return 0, iclass 25, count 2 2006.257.07:41:07.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:07.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:07.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.07:41:07.53#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:07.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:07.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:07.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:07.65#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:41:07.65#ibcon#first serial, iclass 25, count 0 2006.257.07:41:07.65#ibcon#enter sib2, iclass 25, count 0 2006.257.07:41:07.65#ibcon#flushed, iclass 25, count 0 2006.257.07:41:07.65#ibcon#about to write, iclass 25, count 0 2006.257.07:41:07.65#ibcon#wrote, iclass 25, count 0 2006.257.07:41:07.65#ibcon#about to read 3, iclass 25, count 0 2006.257.07:41:07.67#ibcon#read 3, iclass 25, count 0 2006.257.07:41:07.67#ibcon#about to read 4, iclass 25, count 0 2006.257.07:41:07.67#ibcon#read 4, iclass 25, count 0 2006.257.07:41:07.67#ibcon#about to read 5, iclass 25, count 0 2006.257.07:41:07.67#ibcon#read 5, iclass 25, count 0 2006.257.07:41:07.67#ibcon#about to read 6, iclass 25, count 0 2006.257.07:41:07.67#ibcon#read 6, iclass 25, count 0 2006.257.07:41:07.67#ibcon#end of sib2, iclass 25, count 0 2006.257.07:41:07.67#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:41:07.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:41:07.67#ibcon#[25=USB\r\n] 2006.257.07:41:07.67#ibcon#*before write, iclass 25, count 0 2006.257.07:41:07.67#ibcon#enter sib2, iclass 25, count 0 2006.257.07:41:07.67#ibcon#flushed, iclass 25, count 0 2006.257.07:41:07.67#ibcon#about to write, iclass 25, count 0 2006.257.07:41:07.67#ibcon#wrote, iclass 25, count 0 2006.257.07:41:07.67#ibcon#about to read 3, iclass 25, count 0 2006.257.07:41:07.70#ibcon#read 3, iclass 25, count 0 2006.257.07:41:07.70#ibcon#about to read 4, iclass 25, count 0 2006.257.07:41:07.70#ibcon#read 4, iclass 25, count 0 2006.257.07:41:07.70#ibcon#about to read 5, iclass 25, count 0 2006.257.07:41:07.70#ibcon#read 5, iclass 25, count 0 2006.257.07:41:07.70#ibcon#about to read 6, iclass 25, count 0 2006.257.07:41:07.70#ibcon#read 6, iclass 25, count 0 2006.257.07:41:07.70#ibcon#end of sib2, iclass 25, count 0 2006.257.07:41:07.70#ibcon#*after write, iclass 25, count 0 2006.257.07:41:07.70#ibcon#*before return 0, iclass 25, count 0 2006.257.07:41:07.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:07.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:07.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:41:07.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:41:07.70$vck44/valo=8,884.99 2006.257.07:41:07.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.07:41:07.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.07:41:07.70#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:07.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:07.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:07.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:07.70#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:41:07.70#ibcon#first serial, iclass 27, count 0 2006.257.07:41:07.70#ibcon#enter sib2, iclass 27, count 0 2006.257.07:41:07.70#ibcon#flushed, iclass 27, count 0 2006.257.07:41:07.70#ibcon#about to write, iclass 27, count 0 2006.257.07:41:07.70#ibcon#wrote, iclass 27, count 0 2006.257.07:41:07.70#ibcon#about to read 3, iclass 27, count 0 2006.257.07:41:07.72#ibcon#read 3, iclass 27, count 0 2006.257.07:41:07.72#ibcon#about to read 4, iclass 27, count 0 2006.257.07:41:07.72#ibcon#read 4, iclass 27, count 0 2006.257.07:41:07.72#ibcon#about to read 5, iclass 27, count 0 2006.257.07:41:07.72#ibcon#read 5, iclass 27, count 0 2006.257.07:41:07.72#ibcon#about to read 6, iclass 27, count 0 2006.257.07:41:07.72#ibcon#read 6, iclass 27, count 0 2006.257.07:41:07.72#ibcon#end of sib2, iclass 27, count 0 2006.257.07:41:07.72#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:41:07.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:41:07.72#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.07:41:07.72#ibcon#*before write, iclass 27, count 0 2006.257.07:41:07.72#ibcon#enter sib2, iclass 27, count 0 2006.257.07:41:07.72#ibcon#flushed, iclass 27, count 0 2006.257.07:41:07.72#ibcon#about to write, iclass 27, count 0 2006.257.07:41:07.72#ibcon#wrote, iclass 27, count 0 2006.257.07:41:07.72#ibcon#about to read 3, iclass 27, count 0 2006.257.07:41:07.76#ibcon#read 3, iclass 27, count 0 2006.257.07:41:07.76#ibcon#about to read 4, iclass 27, count 0 2006.257.07:41:07.76#ibcon#read 4, iclass 27, count 0 2006.257.07:41:07.76#ibcon#about to read 5, iclass 27, count 0 2006.257.07:41:07.76#ibcon#read 5, iclass 27, count 0 2006.257.07:41:07.76#ibcon#about to read 6, iclass 27, count 0 2006.257.07:41:07.76#ibcon#read 6, iclass 27, count 0 2006.257.07:41:07.76#ibcon#end of sib2, iclass 27, count 0 2006.257.07:41:07.76#ibcon#*after write, iclass 27, count 0 2006.257.07:41:07.76#ibcon#*before return 0, iclass 27, count 0 2006.257.07:41:07.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:07.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:07.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:41:07.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:41:07.76$vck44/va=8,4 2006.257.07:41:07.76#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.07:41:07.76#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.07:41:07.76#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:07.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:41:07.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:41:07.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:41:07.82#ibcon#enter wrdev, iclass 29, count 2 2006.257.07:41:07.82#ibcon#first serial, iclass 29, count 2 2006.257.07:41:07.82#ibcon#enter sib2, iclass 29, count 2 2006.257.07:41:07.82#ibcon#flushed, iclass 29, count 2 2006.257.07:41:07.82#ibcon#about to write, iclass 29, count 2 2006.257.07:41:07.82#ibcon#wrote, iclass 29, count 2 2006.257.07:41:07.82#ibcon#about to read 3, iclass 29, count 2 2006.257.07:41:07.84#ibcon#read 3, iclass 29, count 2 2006.257.07:41:07.84#ibcon#about to read 4, iclass 29, count 2 2006.257.07:41:07.84#ibcon#read 4, iclass 29, count 2 2006.257.07:41:07.84#ibcon#about to read 5, iclass 29, count 2 2006.257.07:41:07.84#ibcon#read 5, iclass 29, count 2 2006.257.07:41:07.84#ibcon#about to read 6, iclass 29, count 2 2006.257.07:41:07.84#ibcon#read 6, iclass 29, count 2 2006.257.07:41:07.84#ibcon#end of sib2, iclass 29, count 2 2006.257.07:41:07.84#ibcon#*mode == 0, iclass 29, count 2 2006.257.07:41:07.84#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.07:41:07.84#ibcon#[25=AT08-04\r\n] 2006.257.07:41:07.84#ibcon#*before write, iclass 29, count 2 2006.257.07:41:07.84#ibcon#enter sib2, iclass 29, count 2 2006.257.07:41:07.84#ibcon#flushed, iclass 29, count 2 2006.257.07:41:07.84#ibcon#about to write, iclass 29, count 2 2006.257.07:41:07.84#ibcon#wrote, iclass 29, count 2 2006.257.07:41:07.84#ibcon#about to read 3, iclass 29, count 2 2006.257.07:41:07.87#ibcon#read 3, iclass 29, count 2 2006.257.07:41:07.87#ibcon#about to read 4, iclass 29, count 2 2006.257.07:41:07.87#ibcon#read 4, iclass 29, count 2 2006.257.07:41:07.87#ibcon#about to read 5, iclass 29, count 2 2006.257.07:41:07.87#ibcon#read 5, iclass 29, count 2 2006.257.07:41:07.87#ibcon#about to read 6, iclass 29, count 2 2006.257.07:41:07.87#ibcon#read 6, iclass 29, count 2 2006.257.07:41:07.87#ibcon#end of sib2, iclass 29, count 2 2006.257.07:41:07.87#ibcon#*after write, iclass 29, count 2 2006.257.07:41:07.87#ibcon#*before return 0, iclass 29, count 2 2006.257.07:41:07.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:41:07.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.07:41:07.87#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.07:41:07.87#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:07.87#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:41:07.99#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:41:07.99#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:41:07.99#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:41:07.99#ibcon#first serial, iclass 29, count 0 2006.257.07:41:07.99#ibcon#enter sib2, iclass 29, count 0 2006.257.07:41:07.99#ibcon#flushed, iclass 29, count 0 2006.257.07:41:07.99#ibcon#about to write, iclass 29, count 0 2006.257.07:41:07.99#ibcon#wrote, iclass 29, count 0 2006.257.07:41:07.99#ibcon#about to read 3, iclass 29, count 0 2006.257.07:41:08.01#ibcon#read 3, iclass 29, count 0 2006.257.07:41:08.01#ibcon#about to read 4, iclass 29, count 0 2006.257.07:41:08.01#ibcon#read 4, iclass 29, count 0 2006.257.07:41:08.01#ibcon#about to read 5, iclass 29, count 0 2006.257.07:41:08.01#ibcon#read 5, iclass 29, count 0 2006.257.07:41:08.01#ibcon#about to read 6, iclass 29, count 0 2006.257.07:41:08.01#ibcon#read 6, iclass 29, count 0 2006.257.07:41:08.01#ibcon#end of sib2, iclass 29, count 0 2006.257.07:41:08.01#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:41:08.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:41:08.01#ibcon#[25=USB\r\n] 2006.257.07:41:08.01#ibcon#*before write, iclass 29, count 0 2006.257.07:41:08.01#ibcon#enter sib2, iclass 29, count 0 2006.257.07:41:08.01#ibcon#flushed, iclass 29, count 0 2006.257.07:41:08.01#ibcon#about to write, iclass 29, count 0 2006.257.07:41:08.01#ibcon#wrote, iclass 29, count 0 2006.257.07:41:08.01#ibcon#about to read 3, iclass 29, count 0 2006.257.07:41:08.04#ibcon#read 3, iclass 29, count 0 2006.257.07:41:08.04#ibcon#about to read 4, iclass 29, count 0 2006.257.07:41:08.04#ibcon#read 4, iclass 29, count 0 2006.257.07:41:08.04#ibcon#about to read 5, iclass 29, count 0 2006.257.07:41:08.04#ibcon#read 5, iclass 29, count 0 2006.257.07:41:08.04#ibcon#about to read 6, iclass 29, count 0 2006.257.07:41:08.04#ibcon#read 6, iclass 29, count 0 2006.257.07:41:08.04#ibcon#end of sib2, iclass 29, count 0 2006.257.07:41:08.04#ibcon#*after write, iclass 29, count 0 2006.257.07:41:08.04#ibcon#*before return 0, iclass 29, count 0 2006.257.07:41:08.04#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:41:08.04#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.07:41:08.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:41:08.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:41:08.04$vck44/vblo=1,629.99 2006.257.07:41:08.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.07:41:08.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.07:41:08.04#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:08.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:08.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:08.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:08.04#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:41:08.04#ibcon#first serial, iclass 31, count 0 2006.257.07:41:08.04#ibcon#enter sib2, iclass 31, count 0 2006.257.07:41:08.04#ibcon#flushed, iclass 31, count 0 2006.257.07:41:08.04#ibcon#about to write, iclass 31, count 0 2006.257.07:41:08.04#ibcon#wrote, iclass 31, count 0 2006.257.07:41:08.04#ibcon#about to read 3, iclass 31, count 0 2006.257.07:41:08.06#ibcon#read 3, iclass 31, count 0 2006.257.07:41:08.06#ibcon#about to read 4, iclass 31, count 0 2006.257.07:41:08.06#ibcon#read 4, iclass 31, count 0 2006.257.07:41:08.06#ibcon#about to read 5, iclass 31, count 0 2006.257.07:41:08.06#ibcon#read 5, iclass 31, count 0 2006.257.07:41:08.06#ibcon#about to read 6, iclass 31, count 0 2006.257.07:41:08.06#ibcon#read 6, iclass 31, count 0 2006.257.07:41:08.06#ibcon#end of sib2, iclass 31, count 0 2006.257.07:41:08.06#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:41:08.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:41:08.06#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.07:41:08.06#ibcon#*before write, iclass 31, count 0 2006.257.07:41:08.06#ibcon#enter sib2, iclass 31, count 0 2006.257.07:41:08.06#ibcon#flushed, iclass 31, count 0 2006.257.07:41:08.06#ibcon#about to write, iclass 31, count 0 2006.257.07:41:08.06#ibcon#wrote, iclass 31, count 0 2006.257.07:41:08.06#ibcon#about to read 3, iclass 31, count 0 2006.257.07:41:08.10#ibcon#read 3, iclass 31, count 0 2006.257.07:41:08.10#ibcon#about to read 4, iclass 31, count 0 2006.257.07:41:08.10#ibcon#read 4, iclass 31, count 0 2006.257.07:41:08.10#ibcon#about to read 5, iclass 31, count 0 2006.257.07:41:08.10#ibcon#read 5, iclass 31, count 0 2006.257.07:41:08.10#ibcon#about to read 6, iclass 31, count 0 2006.257.07:41:08.10#ibcon#read 6, iclass 31, count 0 2006.257.07:41:08.10#ibcon#end of sib2, iclass 31, count 0 2006.257.07:41:08.10#ibcon#*after write, iclass 31, count 0 2006.257.07:41:08.10#ibcon#*before return 0, iclass 31, count 0 2006.257.07:41:08.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:08.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.07:41:08.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:41:08.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:41:08.10$vck44/vb=1,4 2006.257.07:41:08.10#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.07:41:08.10#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.07:41:08.10#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:08.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:08.10#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:08.10#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:08.10#ibcon#enter wrdev, iclass 33, count 2 2006.257.07:41:08.10#ibcon#first serial, iclass 33, count 2 2006.257.07:41:08.10#ibcon#enter sib2, iclass 33, count 2 2006.257.07:41:08.10#ibcon#flushed, iclass 33, count 2 2006.257.07:41:08.10#ibcon#about to write, iclass 33, count 2 2006.257.07:41:08.10#ibcon#wrote, iclass 33, count 2 2006.257.07:41:08.10#ibcon#about to read 3, iclass 33, count 2 2006.257.07:41:08.12#ibcon#read 3, iclass 33, count 2 2006.257.07:41:08.12#ibcon#about to read 4, iclass 33, count 2 2006.257.07:41:08.12#ibcon#read 4, iclass 33, count 2 2006.257.07:41:08.12#ibcon#about to read 5, iclass 33, count 2 2006.257.07:41:08.12#ibcon#read 5, iclass 33, count 2 2006.257.07:41:08.12#ibcon#about to read 6, iclass 33, count 2 2006.257.07:41:08.12#ibcon#read 6, iclass 33, count 2 2006.257.07:41:08.12#ibcon#end of sib2, iclass 33, count 2 2006.257.07:41:08.12#ibcon#*mode == 0, iclass 33, count 2 2006.257.07:41:08.12#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.07:41:08.12#ibcon#[27=AT01-04\r\n] 2006.257.07:41:08.12#ibcon#*before write, iclass 33, count 2 2006.257.07:41:08.12#ibcon#enter sib2, iclass 33, count 2 2006.257.07:41:08.12#ibcon#flushed, iclass 33, count 2 2006.257.07:41:08.12#ibcon#about to write, iclass 33, count 2 2006.257.07:41:08.12#ibcon#wrote, iclass 33, count 2 2006.257.07:41:08.12#ibcon#about to read 3, iclass 33, count 2 2006.257.07:41:08.15#ibcon#read 3, iclass 33, count 2 2006.257.07:41:08.15#ibcon#about to read 4, iclass 33, count 2 2006.257.07:41:08.15#ibcon#read 4, iclass 33, count 2 2006.257.07:41:08.15#ibcon#about to read 5, iclass 33, count 2 2006.257.07:41:08.15#ibcon#read 5, iclass 33, count 2 2006.257.07:41:08.15#ibcon#about to read 6, iclass 33, count 2 2006.257.07:41:08.15#ibcon#read 6, iclass 33, count 2 2006.257.07:41:08.15#ibcon#end of sib2, iclass 33, count 2 2006.257.07:41:08.15#ibcon#*after write, iclass 33, count 2 2006.257.07:41:08.15#ibcon#*before return 0, iclass 33, count 2 2006.257.07:41:08.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:08.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.07:41:08.15#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.07:41:08.15#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:08.15#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:08.27#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:08.27#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:08.27#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:41:08.27#ibcon#first serial, iclass 33, count 0 2006.257.07:41:08.27#ibcon#enter sib2, iclass 33, count 0 2006.257.07:41:08.27#ibcon#flushed, iclass 33, count 0 2006.257.07:41:08.27#ibcon#about to write, iclass 33, count 0 2006.257.07:41:08.27#ibcon#wrote, iclass 33, count 0 2006.257.07:41:08.27#ibcon#about to read 3, iclass 33, count 0 2006.257.07:41:08.29#ibcon#read 3, iclass 33, count 0 2006.257.07:41:08.29#ibcon#about to read 4, iclass 33, count 0 2006.257.07:41:08.29#ibcon#read 4, iclass 33, count 0 2006.257.07:41:08.29#ibcon#about to read 5, iclass 33, count 0 2006.257.07:41:08.29#ibcon#read 5, iclass 33, count 0 2006.257.07:41:08.29#ibcon#about to read 6, iclass 33, count 0 2006.257.07:41:08.29#ibcon#read 6, iclass 33, count 0 2006.257.07:41:08.29#ibcon#end of sib2, iclass 33, count 0 2006.257.07:41:08.29#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:41:08.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:41:08.29#ibcon#[27=USB\r\n] 2006.257.07:41:08.29#ibcon#*before write, iclass 33, count 0 2006.257.07:41:08.29#ibcon#enter sib2, iclass 33, count 0 2006.257.07:41:08.29#ibcon#flushed, iclass 33, count 0 2006.257.07:41:08.29#ibcon#about to write, iclass 33, count 0 2006.257.07:41:08.29#ibcon#wrote, iclass 33, count 0 2006.257.07:41:08.29#ibcon#about to read 3, iclass 33, count 0 2006.257.07:41:08.32#ibcon#read 3, iclass 33, count 0 2006.257.07:41:08.32#ibcon#about to read 4, iclass 33, count 0 2006.257.07:41:08.32#ibcon#read 4, iclass 33, count 0 2006.257.07:41:08.32#ibcon#about to read 5, iclass 33, count 0 2006.257.07:41:08.32#ibcon#read 5, iclass 33, count 0 2006.257.07:41:08.32#ibcon#about to read 6, iclass 33, count 0 2006.257.07:41:08.32#ibcon#read 6, iclass 33, count 0 2006.257.07:41:08.32#ibcon#end of sib2, iclass 33, count 0 2006.257.07:41:08.32#ibcon#*after write, iclass 33, count 0 2006.257.07:41:08.32#ibcon#*before return 0, iclass 33, count 0 2006.257.07:41:08.32#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:08.32#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.07:41:08.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:41:08.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:41:08.32$vck44/vblo=2,634.99 2006.257.07:41:08.32#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.07:41:08.32#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.07:41:08.32#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:08.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:41:08.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:41:08.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:41:08.32#ibcon#enter wrdev, iclass 35, count 0 2006.257.07:41:08.32#ibcon#first serial, iclass 35, count 0 2006.257.07:41:08.32#ibcon#enter sib2, iclass 35, count 0 2006.257.07:41:08.32#ibcon#flushed, iclass 35, count 0 2006.257.07:41:08.32#ibcon#about to write, iclass 35, count 0 2006.257.07:41:08.32#ibcon#wrote, iclass 35, count 0 2006.257.07:41:08.32#ibcon#about to read 3, iclass 35, count 0 2006.257.07:41:08.34#ibcon#read 3, iclass 35, count 0 2006.257.07:41:08.34#ibcon#about to read 4, iclass 35, count 0 2006.257.07:41:08.34#ibcon#read 4, iclass 35, count 0 2006.257.07:41:08.34#ibcon#about to read 5, iclass 35, count 0 2006.257.07:41:08.34#ibcon#read 5, iclass 35, count 0 2006.257.07:41:08.34#ibcon#about to read 6, iclass 35, count 0 2006.257.07:41:08.34#ibcon#read 6, iclass 35, count 0 2006.257.07:41:08.34#ibcon#end of sib2, iclass 35, count 0 2006.257.07:41:08.34#ibcon#*mode == 0, iclass 35, count 0 2006.257.07:41:08.34#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.07:41:08.34#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.07:41:08.34#ibcon#*before write, iclass 35, count 0 2006.257.07:41:08.34#ibcon#enter sib2, iclass 35, count 0 2006.257.07:41:08.34#ibcon#flushed, iclass 35, count 0 2006.257.07:41:08.34#ibcon#about to write, iclass 35, count 0 2006.257.07:41:08.34#ibcon#wrote, iclass 35, count 0 2006.257.07:41:08.34#ibcon#about to read 3, iclass 35, count 0 2006.257.07:41:08.38#ibcon#read 3, iclass 35, count 0 2006.257.07:41:08.38#ibcon#about to read 4, iclass 35, count 0 2006.257.07:41:08.38#ibcon#read 4, iclass 35, count 0 2006.257.07:41:08.38#ibcon#about to read 5, iclass 35, count 0 2006.257.07:41:08.38#ibcon#read 5, iclass 35, count 0 2006.257.07:41:08.38#ibcon#about to read 6, iclass 35, count 0 2006.257.07:41:08.38#ibcon#read 6, iclass 35, count 0 2006.257.07:41:08.38#ibcon#end of sib2, iclass 35, count 0 2006.257.07:41:08.38#ibcon#*after write, iclass 35, count 0 2006.257.07:41:08.38#ibcon#*before return 0, iclass 35, count 0 2006.257.07:41:08.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:41:08.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.07:41:08.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.07:41:08.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.07:41:08.38$vck44/vb=2,5 2006.257.07:41:08.38#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.07:41:08.38#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.07:41:08.38#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:08.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:41:08.44#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:41:08.44#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:41:08.44#ibcon#enter wrdev, iclass 37, count 2 2006.257.07:41:08.44#ibcon#first serial, iclass 37, count 2 2006.257.07:41:08.44#ibcon#enter sib2, iclass 37, count 2 2006.257.07:41:08.44#ibcon#flushed, iclass 37, count 2 2006.257.07:41:08.44#ibcon#about to write, iclass 37, count 2 2006.257.07:41:08.44#ibcon#wrote, iclass 37, count 2 2006.257.07:41:08.44#ibcon#about to read 3, iclass 37, count 2 2006.257.07:41:08.46#ibcon#read 3, iclass 37, count 2 2006.257.07:41:08.46#ibcon#about to read 4, iclass 37, count 2 2006.257.07:41:08.46#ibcon#read 4, iclass 37, count 2 2006.257.07:41:08.46#ibcon#about to read 5, iclass 37, count 2 2006.257.07:41:08.46#ibcon#read 5, iclass 37, count 2 2006.257.07:41:08.46#ibcon#about to read 6, iclass 37, count 2 2006.257.07:41:08.46#ibcon#read 6, iclass 37, count 2 2006.257.07:41:08.46#ibcon#end of sib2, iclass 37, count 2 2006.257.07:41:08.46#ibcon#*mode == 0, iclass 37, count 2 2006.257.07:41:08.46#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.07:41:08.46#ibcon#[27=AT02-05\r\n] 2006.257.07:41:08.46#ibcon#*before write, iclass 37, count 2 2006.257.07:41:08.46#ibcon#enter sib2, iclass 37, count 2 2006.257.07:41:08.46#ibcon#flushed, iclass 37, count 2 2006.257.07:41:08.46#ibcon#about to write, iclass 37, count 2 2006.257.07:41:08.46#ibcon#wrote, iclass 37, count 2 2006.257.07:41:08.46#ibcon#about to read 3, iclass 37, count 2 2006.257.07:41:08.49#ibcon#read 3, iclass 37, count 2 2006.257.07:41:08.49#ibcon#about to read 4, iclass 37, count 2 2006.257.07:41:08.49#ibcon#read 4, iclass 37, count 2 2006.257.07:41:08.49#ibcon#about to read 5, iclass 37, count 2 2006.257.07:41:08.49#ibcon#read 5, iclass 37, count 2 2006.257.07:41:08.49#ibcon#about to read 6, iclass 37, count 2 2006.257.07:41:08.49#ibcon#read 6, iclass 37, count 2 2006.257.07:41:08.49#ibcon#end of sib2, iclass 37, count 2 2006.257.07:41:08.49#ibcon#*after write, iclass 37, count 2 2006.257.07:41:08.49#ibcon#*before return 0, iclass 37, count 2 2006.257.07:41:08.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:41:08.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.07:41:08.49#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.07:41:08.49#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:08.49#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:41:08.61#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:41:08.61#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:41:08.61#ibcon#enter wrdev, iclass 37, count 0 2006.257.07:41:08.61#ibcon#first serial, iclass 37, count 0 2006.257.07:41:08.61#ibcon#enter sib2, iclass 37, count 0 2006.257.07:41:08.61#ibcon#flushed, iclass 37, count 0 2006.257.07:41:08.61#ibcon#about to write, iclass 37, count 0 2006.257.07:41:08.61#ibcon#wrote, iclass 37, count 0 2006.257.07:41:08.61#ibcon#about to read 3, iclass 37, count 0 2006.257.07:41:08.63#ibcon#read 3, iclass 37, count 0 2006.257.07:41:08.63#ibcon#about to read 4, iclass 37, count 0 2006.257.07:41:08.63#ibcon#read 4, iclass 37, count 0 2006.257.07:41:08.63#ibcon#about to read 5, iclass 37, count 0 2006.257.07:41:08.63#ibcon#read 5, iclass 37, count 0 2006.257.07:41:08.63#ibcon#about to read 6, iclass 37, count 0 2006.257.07:41:08.63#ibcon#read 6, iclass 37, count 0 2006.257.07:41:08.63#ibcon#end of sib2, iclass 37, count 0 2006.257.07:41:08.63#ibcon#*mode == 0, iclass 37, count 0 2006.257.07:41:08.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.07:41:08.63#ibcon#[27=USB\r\n] 2006.257.07:41:08.63#ibcon#*before write, iclass 37, count 0 2006.257.07:41:08.63#ibcon#enter sib2, iclass 37, count 0 2006.257.07:41:08.63#ibcon#flushed, iclass 37, count 0 2006.257.07:41:08.63#ibcon#about to write, iclass 37, count 0 2006.257.07:41:08.63#ibcon#wrote, iclass 37, count 0 2006.257.07:41:08.63#ibcon#about to read 3, iclass 37, count 0 2006.257.07:41:08.66#ibcon#read 3, iclass 37, count 0 2006.257.07:41:08.66#ibcon#about to read 4, iclass 37, count 0 2006.257.07:41:08.66#ibcon#read 4, iclass 37, count 0 2006.257.07:41:08.66#ibcon#about to read 5, iclass 37, count 0 2006.257.07:41:08.66#ibcon#read 5, iclass 37, count 0 2006.257.07:41:08.66#ibcon#about to read 6, iclass 37, count 0 2006.257.07:41:08.66#ibcon#read 6, iclass 37, count 0 2006.257.07:41:08.66#ibcon#end of sib2, iclass 37, count 0 2006.257.07:41:08.66#ibcon#*after write, iclass 37, count 0 2006.257.07:41:08.66#ibcon#*before return 0, iclass 37, count 0 2006.257.07:41:08.66#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:41:08.66#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.07:41:08.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.07:41:08.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.07:41:08.66$vck44/vblo=3,649.99 2006.257.07:41:08.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.07:41:08.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.07:41:08.66#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:08.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:08.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:08.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:08.66#ibcon#enter wrdev, iclass 39, count 0 2006.257.07:41:08.66#ibcon#first serial, iclass 39, count 0 2006.257.07:41:08.66#ibcon#enter sib2, iclass 39, count 0 2006.257.07:41:08.66#ibcon#flushed, iclass 39, count 0 2006.257.07:41:08.66#ibcon#about to write, iclass 39, count 0 2006.257.07:41:08.66#ibcon#wrote, iclass 39, count 0 2006.257.07:41:08.66#ibcon#about to read 3, iclass 39, count 0 2006.257.07:41:08.68#ibcon#read 3, iclass 39, count 0 2006.257.07:41:08.68#ibcon#about to read 4, iclass 39, count 0 2006.257.07:41:08.68#ibcon#read 4, iclass 39, count 0 2006.257.07:41:08.68#ibcon#about to read 5, iclass 39, count 0 2006.257.07:41:08.68#ibcon#read 5, iclass 39, count 0 2006.257.07:41:08.68#ibcon#about to read 6, iclass 39, count 0 2006.257.07:41:08.68#ibcon#read 6, iclass 39, count 0 2006.257.07:41:08.68#ibcon#end of sib2, iclass 39, count 0 2006.257.07:41:08.68#ibcon#*mode == 0, iclass 39, count 0 2006.257.07:41:08.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.07:41:08.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.07:41:08.68#ibcon#*before write, iclass 39, count 0 2006.257.07:41:08.68#ibcon#enter sib2, iclass 39, count 0 2006.257.07:41:08.68#ibcon#flushed, iclass 39, count 0 2006.257.07:41:08.68#ibcon#about to write, iclass 39, count 0 2006.257.07:41:08.68#ibcon#wrote, iclass 39, count 0 2006.257.07:41:08.68#ibcon#about to read 3, iclass 39, count 0 2006.257.07:41:08.72#ibcon#read 3, iclass 39, count 0 2006.257.07:41:08.72#ibcon#about to read 4, iclass 39, count 0 2006.257.07:41:08.72#ibcon#read 4, iclass 39, count 0 2006.257.07:41:08.72#ibcon#about to read 5, iclass 39, count 0 2006.257.07:41:08.72#ibcon#read 5, iclass 39, count 0 2006.257.07:41:08.72#ibcon#about to read 6, iclass 39, count 0 2006.257.07:41:08.72#ibcon#read 6, iclass 39, count 0 2006.257.07:41:08.72#ibcon#end of sib2, iclass 39, count 0 2006.257.07:41:08.72#ibcon#*after write, iclass 39, count 0 2006.257.07:41:08.72#ibcon#*before return 0, iclass 39, count 0 2006.257.07:41:08.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:08.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.07:41:08.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.07:41:08.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.07:41:08.72$vck44/vb=3,4 2006.257.07:41:08.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.07:41:08.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.07:41:08.72#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:08.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:08.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:08.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:08.78#ibcon#enter wrdev, iclass 3, count 2 2006.257.07:41:08.78#ibcon#first serial, iclass 3, count 2 2006.257.07:41:08.78#ibcon#enter sib2, iclass 3, count 2 2006.257.07:41:08.78#ibcon#flushed, iclass 3, count 2 2006.257.07:41:08.78#ibcon#about to write, iclass 3, count 2 2006.257.07:41:08.78#ibcon#wrote, iclass 3, count 2 2006.257.07:41:08.78#ibcon#about to read 3, iclass 3, count 2 2006.257.07:41:08.80#ibcon#read 3, iclass 3, count 2 2006.257.07:41:08.80#ibcon#about to read 4, iclass 3, count 2 2006.257.07:41:08.80#ibcon#read 4, iclass 3, count 2 2006.257.07:41:08.80#ibcon#about to read 5, iclass 3, count 2 2006.257.07:41:08.80#ibcon#read 5, iclass 3, count 2 2006.257.07:41:08.80#ibcon#about to read 6, iclass 3, count 2 2006.257.07:41:08.80#ibcon#read 6, iclass 3, count 2 2006.257.07:41:08.80#ibcon#end of sib2, iclass 3, count 2 2006.257.07:41:08.80#ibcon#*mode == 0, iclass 3, count 2 2006.257.07:41:08.80#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.07:41:08.80#ibcon#[27=AT03-04\r\n] 2006.257.07:41:08.80#ibcon#*before write, iclass 3, count 2 2006.257.07:41:08.80#ibcon#enter sib2, iclass 3, count 2 2006.257.07:41:08.80#ibcon#flushed, iclass 3, count 2 2006.257.07:41:08.80#ibcon#about to write, iclass 3, count 2 2006.257.07:41:08.80#ibcon#wrote, iclass 3, count 2 2006.257.07:41:08.80#ibcon#about to read 3, iclass 3, count 2 2006.257.07:41:08.83#ibcon#read 3, iclass 3, count 2 2006.257.07:41:08.83#ibcon#about to read 4, iclass 3, count 2 2006.257.07:41:08.83#ibcon#read 4, iclass 3, count 2 2006.257.07:41:08.83#ibcon#about to read 5, iclass 3, count 2 2006.257.07:41:08.83#ibcon#read 5, iclass 3, count 2 2006.257.07:41:08.83#ibcon#about to read 6, iclass 3, count 2 2006.257.07:41:08.83#ibcon#read 6, iclass 3, count 2 2006.257.07:41:08.83#ibcon#end of sib2, iclass 3, count 2 2006.257.07:41:08.83#ibcon#*after write, iclass 3, count 2 2006.257.07:41:08.83#ibcon#*before return 0, iclass 3, count 2 2006.257.07:41:08.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:08.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.07:41:08.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.07:41:08.83#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:08.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:08.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:08.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:08.95#ibcon#enter wrdev, iclass 3, count 0 2006.257.07:41:08.95#ibcon#first serial, iclass 3, count 0 2006.257.07:41:08.95#ibcon#enter sib2, iclass 3, count 0 2006.257.07:41:08.95#ibcon#flushed, iclass 3, count 0 2006.257.07:41:08.95#ibcon#about to write, iclass 3, count 0 2006.257.07:41:08.95#ibcon#wrote, iclass 3, count 0 2006.257.07:41:08.95#ibcon#about to read 3, iclass 3, count 0 2006.257.07:41:08.97#ibcon#read 3, iclass 3, count 0 2006.257.07:41:08.97#ibcon#about to read 4, iclass 3, count 0 2006.257.07:41:08.97#ibcon#read 4, iclass 3, count 0 2006.257.07:41:08.97#ibcon#about to read 5, iclass 3, count 0 2006.257.07:41:08.97#ibcon#read 5, iclass 3, count 0 2006.257.07:41:08.97#ibcon#about to read 6, iclass 3, count 0 2006.257.07:41:08.97#ibcon#read 6, iclass 3, count 0 2006.257.07:41:08.97#ibcon#end of sib2, iclass 3, count 0 2006.257.07:41:08.97#ibcon#*mode == 0, iclass 3, count 0 2006.257.07:41:08.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.07:41:08.97#ibcon#[27=USB\r\n] 2006.257.07:41:08.97#ibcon#*before write, iclass 3, count 0 2006.257.07:41:08.97#ibcon#enter sib2, iclass 3, count 0 2006.257.07:41:08.97#ibcon#flushed, iclass 3, count 0 2006.257.07:41:08.97#ibcon#about to write, iclass 3, count 0 2006.257.07:41:08.97#ibcon#wrote, iclass 3, count 0 2006.257.07:41:08.97#ibcon#about to read 3, iclass 3, count 0 2006.257.07:41:09.00#ibcon#read 3, iclass 3, count 0 2006.257.07:41:09.00#ibcon#about to read 4, iclass 3, count 0 2006.257.07:41:09.00#ibcon#read 4, iclass 3, count 0 2006.257.07:41:09.00#ibcon#about to read 5, iclass 3, count 0 2006.257.07:41:09.00#ibcon#read 5, iclass 3, count 0 2006.257.07:41:09.00#ibcon#about to read 6, iclass 3, count 0 2006.257.07:41:09.00#ibcon#read 6, iclass 3, count 0 2006.257.07:41:09.00#ibcon#end of sib2, iclass 3, count 0 2006.257.07:41:09.00#ibcon#*after write, iclass 3, count 0 2006.257.07:41:09.00#ibcon#*before return 0, iclass 3, count 0 2006.257.07:41:09.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:09.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.07:41:09.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.07:41:09.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.07:41:09.00$vck44/vblo=4,679.99 2006.257.07:41:09.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.07:41:09.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.07:41:09.00#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:09.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:09.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:09.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:09.00#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:41:09.00#ibcon#first serial, iclass 5, count 0 2006.257.07:41:09.00#ibcon#enter sib2, iclass 5, count 0 2006.257.07:41:09.00#ibcon#flushed, iclass 5, count 0 2006.257.07:41:09.00#ibcon#about to write, iclass 5, count 0 2006.257.07:41:09.00#ibcon#wrote, iclass 5, count 0 2006.257.07:41:09.00#ibcon#about to read 3, iclass 5, count 0 2006.257.07:41:09.02#ibcon#read 3, iclass 5, count 0 2006.257.07:41:09.02#ibcon#about to read 4, iclass 5, count 0 2006.257.07:41:09.02#ibcon#read 4, iclass 5, count 0 2006.257.07:41:09.02#ibcon#about to read 5, iclass 5, count 0 2006.257.07:41:09.02#ibcon#read 5, iclass 5, count 0 2006.257.07:41:09.02#ibcon#about to read 6, iclass 5, count 0 2006.257.07:41:09.02#ibcon#read 6, iclass 5, count 0 2006.257.07:41:09.02#ibcon#end of sib2, iclass 5, count 0 2006.257.07:41:09.02#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:41:09.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:41:09.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.07:41:09.02#ibcon#*before write, iclass 5, count 0 2006.257.07:41:09.02#ibcon#enter sib2, iclass 5, count 0 2006.257.07:41:09.02#ibcon#flushed, iclass 5, count 0 2006.257.07:41:09.02#ibcon#about to write, iclass 5, count 0 2006.257.07:41:09.02#ibcon#wrote, iclass 5, count 0 2006.257.07:41:09.02#ibcon#about to read 3, iclass 5, count 0 2006.257.07:41:09.06#ibcon#read 3, iclass 5, count 0 2006.257.07:41:09.06#ibcon#about to read 4, iclass 5, count 0 2006.257.07:41:09.06#ibcon#read 4, iclass 5, count 0 2006.257.07:41:09.06#ibcon#about to read 5, iclass 5, count 0 2006.257.07:41:09.06#ibcon#read 5, iclass 5, count 0 2006.257.07:41:09.06#ibcon#about to read 6, iclass 5, count 0 2006.257.07:41:09.06#ibcon#read 6, iclass 5, count 0 2006.257.07:41:09.06#ibcon#end of sib2, iclass 5, count 0 2006.257.07:41:09.06#ibcon#*after write, iclass 5, count 0 2006.257.07:41:09.06#ibcon#*before return 0, iclass 5, count 0 2006.257.07:41:09.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:09.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.07:41:09.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:41:09.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:41:09.06$vck44/vb=4,5 2006.257.07:41:09.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.07:41:09.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.07:41:09.06#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:09.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:09.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:09.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:09.12#ibcon#enter wrdev, iclass 7, count 2 2006.257.07:41:09.12#ibcon#first serial, iclass 7, count 2 2006.257.07:41:09.12#ibcon#enter sib2, iclass 7, count 2 2006.257.07:41:09.12#ibcon#flushed, iclass 7, count 2 2006.257.07:41:09.12#ibcon#about to write, iclass 7, count 2 2006.257.07:41:09.12#ibcon#wrote, iclass 7, count 2 2006.257.07:41:09.12#ibcon#about to read 3, iclass 7, count 2 2006.257.07:41:09.14#ibcon#read 3, iclass 7, count 2 2006.257.07:41:09.14#ibcon#about to read 4, iclass 7, count 2 2006.257.07:41:09.14#ibcon#read 4, iclass 7, count 2 2006.257.07:41:09.14#ibcon#about to read 5, iclass 7, count 2 2006.257.07:41:09.14#ibcon#read 5, iclass 7, count 2 2006.257.07:41:09.14#ibcon#about to read 6, iclass 7, count 2 2006.257.07:41:09.14#ibcon#read 6, iclass 7, count 2 2006.257.07:41:09.14#ibcon#end of sib2, iclass 7, count 2 2006.257.07:41:09.14#ibcon#*mode == 0, iclass 7, count 2 2006.257.07:41:09.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.07:41:09.14#ibcon#[27=AT04-05\r\n] 2006.257.07:41:09.14#ibcon#*before write, iclass 7, count 2 2006.257.07:41:09.14#ibcon#enter sib2, iclass 7, count 2 2006.257.07:41:09.14#ibcon#flushed, iclass 7, count 2 2006.257.07:41:09.14#ibcon#about to write, iclass 7, count 2 2006.257.07:41:09.14#ibcon#wrote, iclass 7, count 2 2006.257.07:41:09.14#ibcon#about to read 3, iclass 7, count 2 2006.257.07:41:09.17#ibcon#read 3, iclass 7, count 2 2006.257.07:41:09.17#ibcon#about to read 4, iclass 7, count 2 2006.257.07:41:09.17#ibcon#read 4, iclass 7, count 2 2006.257.07:41:09.17#ibcon#about to read 5, iclass 7, count 2 2006.257.07:41:09.17#ibcon#read 5, iclass 7, count 2 2006.257.07:41:09.17#ibcon#about to read 6, iclass 7, count 2 2006.257.07:41:09.17#ibcon#read 6, iclass 7, count 2 2006.257.07:41:09.17#ibcon#end of sib2, iclass 7, count 2 2006.257.07:41:09.17#ibcon#*after write, iclass 7, count 2 2006.257.07:41:09.17#ibcon#*before return 0, iclass 7, count 2 2006.257.07:41:09.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:09.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.07:41:09.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.07:41:09.17#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:09.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:09.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:09.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:09.29#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:41:09.29#ibcon#first serial, iclass 7, count 0 2006.257.07:41:09.29#ibcon#enter sib2, iclass 7, count 0 2006.257.07:41:09.29#ibcon#flushed, iclass 7, count 0 2006.257.07:41:09.29#ibcon#about to write, iclass 7, count 0 2006.257.07:41:09.29#ibcon#wrote, iclass 7, count 0 2006.257.07:41:09.29#ibcon#about to read 3, iclass 7, count 0 2006.257.07:41:09.31#ibcon#read 3, iclass 7, count 0 2006.257.07:41:09.31#ibcon#about to read 4, iclass 7, count 0 2006.257.07:41:09.31#ibcon#read 4, iclass 7, count 0 2006.257.07:41:09.31#ibcon#about to read 5, iclass 7, count 0 2006.257.07:41:09.31#ibcon#read 5, iclass 7, count 0 2006.257.07:41:09.31#ibcon#about to read 6, iclass 7, count 0 2006.257.07:41:09.31#ibcon#read 6, iclass 7, count 0 2006.257.07:41:09.31#ibcon#end of sib2, iclass 7, count 0 2006.257.07:41:09.31#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:41:09.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:41:09.31#ibcon#[27=USB\r\n] 2006.257.07:41:09.31#ibcon#*before write, iclass 7, count 0 2006.257.07:41:09.31#ibcon#enter sib2, iclass 7, count 0 2006.257.07:41:09.31#ibcon#flushed, iclass 7, count 0 2006.257.07:41:09.31#ibcon#about to write, iclass 7, count 0 2006.257.07:41:09.31#ibcon#wrote, iclass 7, count 0 2006.257.07:41:09.31#ibcon#about to read 3, iclass 7, count 0 2006.257.07:41:09.34#ibcon#read 3, iclass 7, count 0 2006.257.07:41:09.34#ibcon#about to read 4, iclass 7, count 0 2006.257.07:41:09.34#ibcon#read 4, iclass 7, count 0 2006.257.07:41:09.34#ibcon#about to read 5, iclass 7, count 0 2006.257.07:41:09.34#ibcon#read 5, iclass 7, count 0 2006.257.07:41:09.34#ibcon#about to read 6, iclass 7, count 0 2006.257.07:41:09.34#ibcon#read 6, iclass 7, count 0 2006.257.07:41:09.34#ibcon#end of sib2, iclass 7, count 0 2006.257.07:41:09.34#ibcon#*after write, iclass 7, count 0 2006.257.07:41:09.34#ibcon#*before return 0, iclass 7, count 0 2006.257.07:41:09.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:09.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.07:41:09.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:41:09.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:41:09.34$vck44/vblo=5,709.99 2006.257.07:41:09.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.07:41:09.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.07:41:09.34#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:09.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:09.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:09.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:09.34#ibcon#enter wrdev, iclass 11, count 0 2006.257.07:41:09.34#ibcon#first serial, iclass 11, count 0 2006.257.07:41:09.34#ibcon#enter sib2, iclass 11, count 0 2006.257.07:41:09.34#ibcon#flushed, iclass 11, count 0 2006.257.07:41:09.34#ibcon#about to write, iclass 11, count 0 2006.257.07:41:09.34#ibcon#wrote, iclass 11, count 0 2006.257.07:41:09.34#ibcon#about to read 3, iclass 11, count 0 2006.257.07:41:09.36#ibcon#read 3, iclass 11, count 0 2006.257.07:41:09.36#ibcon#about to read 4, iclass 11, count 0 2006.257.07:41:09.36#ibcon#read 4, iclass 11, count 0 2006.257.07:41:09.36#ibcon#about to read 5, iclass 11, count 0 2006.257.07:41:09.36#ibcon#read 5, iclass 11, count 0 2006.257.07:41:09.36#ibcon#about to read 6, iclass 11, count 0 2006.257.07:41:09.36#ibcon#read 6, iclass 11, count 0 2006.257.07:41:09.36#ibcon#end of sib2, iclass 11, count 0 2006.257.07:41:09.36#ibcon#*mode == 0, iclass 11, count 0 2006.257.07:41:09.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.07:41:09.36#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.07:41:09.36#ibcon#*before write, iclass 11, count 0 2006.257.07:41:09.36#ibcon#enter sib2, iclass 11, count 0 2006.257.07:41:09.36#ibcon#flushed, iclass 11, count 0 2006.257.07:41:09.36#ibcon#about to write, iclass 11, count 0 2006.257.07:41:09.36#ibcon#wrote, iclass 11, count 0 2006.257.07:41:09.36#ibcon#about to read 3, iclass 11, count 0 2006.257.07:41:09.40#ibcon#read 3, iclass 11, count 0 2006.257.07:41:09.40#ibcon#about to read 4, iclass 11, count 0 2006.257.07:41:09.40#ibcon#read 4, iclass 11, count 0 2006.257.07:41:09.40#ibcon#about to read 5, iclass 11, count 0 2006.257.07:41:09.40#ibcon#read 5, iclass 11, count 0 2006.257.07:41:09.40#ibcon#about to read 6, iclass 11, count 0 2006.257.07:41:09.40#ibcon#read 6, iclass 11, count 0 2006.257.07:41:09.40#ibcon#end of sib2, iclass 11, count 0 2006.257.07:41:09.40#ibcon#*after write, iclass 11, count 0 2006.257.07:41:09.40#ibcon#*before return 0, iclass 11, count 0 2006.257.07:41:09.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:09.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.07:41:09.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.07:41:09.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.07:41:09.40$vck44/vb=5,4 2006.257.07:41:09.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.07:41:09.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.07:41:09.40#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:09.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:09.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:09.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:09.46#ibcon#enter wrdev, iclass 13, count 2 2006.257.07:41:09.46#ibcon#first serial, iclass 13, count 2 2006.257.07:41:09.46#ibcon#enter sib2, iclass 13, count 2 2006.257.07:41:09.46#ibcon#flushed, iclass 13, count 2 2006.257.07:41:09.46#ibcon#about to write, iclass 13, count 2 2006.257.07:41:09.46#ibcon#wrote, iclass 13, count 2 2006.257.07:41:09.46#ibcon#about to read 3, iclass 13, count 2 2006.257.07:41:09.48#ibcon#read 3, iclass 13, count 2 2006.257.07:41:09.48#ibcon#about to read 4, iclass 13, count 2 2006.257.07:41:09.48#ibcon#read 4, iclass 13, count 2 2006.257.07:41:09.48#ibcon#about to read 5, iclass 13, count 2 2006.257.07:41:09.48#ibcon#read 5, iclass 13, count 2 2006.257.07:41:09.48#ibcon#about to read 6, iclass 13, count 2 2006.257.07:41:09.48#ibcon#read 6, iclass 13, count 2 2006.257.07:41:09.48#ibcon#end of sib2, iclass 13, count 2 2006.257.07:41:09.48#ibcon#*mode == 0, iclass 13, count 2 2006.257.07:41:09.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.07:41:09.48#ibcon#[27=AT05-04\r\n] 2006.257.07:41:09.48#ibcon#*before write, iclass 13, count 2 2006.257.07:41:09.48#ibcon#enter sib2, iclass 13, count 2 2006.257.07:41:09.48#ibcon#flushed, iclass 13, count 2 2006.257.07:41:09.48#ibcon#about to write, iclass 13, count 2 2006.257.07:41:09.48#ibcon#wrote, iclass 13, count 2 2006.257.07:41:09.48#ibcon#about to read 3, iclass 13, count 2 2006.257.07:41:09.51#ibcon#read 3, iclass 13, count 2 2006.257.07:41:09.51#ibcon#about to read 4, iclass 13, count 2 2006.257.07:41:09.51#ibcon#read 4, iclass 13, count 2 2006.257.07:41:09.51#ibcon#about to read 5, iclass 13, count 2 2006.257.07:41:09.51#ibcon#read 5, iclass 13, count 2 2006.257.07:41:09.51#ibcon#about to read 6, iclass 13, count 2 2006.257.07:41:09.51#ibcon#read 6, iclass 13, count 2 2006.257.07:41:09.51#ibcon#end of sib2, iclass 13, count 2 2006.257.07:41:09.51#ibcon#*after write, iclass 13, count 2 2006.257.07:41:09.51#ibcon#*before return 0, iclass 13, count 2 2006.257.07:41:09.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:09.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.07:41:09.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.07:41:09.51#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:09.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:09.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:09.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:09.63#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:41:09.63#ibcon#first serial, iclass 13, count 0 2006.257.07:41:09.63#ibcon#enter sib2, iclass 13, count 0 2006.257.07:41:09.63#ibcon#flushed, iclass 13, count 0 2006.257.07:41:09.63#ibcon#about to write, iclass 13, count 0 2006.257.07:41:09.63#ibcon#wrote, iclass 13, count 0 2006.257.07:41:09.63#ibcon#about to read 3, iclass 13, count 0 2006.257.07:41:09.65#ibcon#read 3, iclass 13, count 0 2006.257.07:41:09.65#ibcon#about to read 4, iclass 13, count 0 2006.257.07:41:09.65#ibcon#read 4, iclass 13, count 0 2006.257.07:41:09.65#ibcon#about to read 5, iclass 13, count 0 2006.257.07:41:09.65#ibcon#read 5, iclass 13, count 0 2006.257.07:41:09.65#ibcon#about to read 6, iclass 13, count 0 2006.257.07:41:09.65#ibcon#read 6, iclass 13, count 0 2006.257.07:41:09.65#ibcon#end of sib2, iclass 13, count 0 2006.257.07:41:09.65#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:41:09.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:41:09.65#ibcon#[27=USB\r\n] 2006.257.07:41:09.65#ibcon#*before write, iclass 13, count 0 2006.257.07:41:09.65#ibcon#enter sib2, iclass 13, count 0 2006.257.07:41:09.65#ibcon#flushed, iclass 13, count 0 2006.257.07:41:09.65#ibcon#about to write, iclass 13, count 0 2006.257.07:41:09.65#ibcon#wrote, iclass 13, count 0 2006.257.07:41:09.65#ibcon#about to read 3, iclass 13, count 0 2006.257.07:41:09.68#ibcon#read 3, iclass 13, count 0 2006.257.07:41:09.68#ibcon#about to read 4, iclass 13, count 0 2006.257.07:41:09.68#ibcon#read 4, iclass 13, count 0 2006.257.07:41:09.68#ibcon#about to read 5, iclass 13, count 0 2006.257.07:41:09.68#ibcon#read 5, iclass 13, count 0 2006.257.07:41:09.68#ibcon#about to read 6, iclass 13, count 0 2006.257.07:41:09.68#ibcon#read 6, iclass 13, count 0 2006.257.07:41:09.68#ibcon#end of sib2, iclass 13, count 0 2006.257.07:41:09.68#ibcon#*after write, iclass 13, count 0 2006.257.07:41:09.68#ibcon#*before return 0, iclass 13, count 0 2006.257.07:41:09.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:09.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.07:41:09.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:41:09.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:41:09.68$vck44/vblo=6,719.99 2006.257.07:41:09.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.07:41:09.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.07:41:09.68#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:09.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:09.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:09.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:09.68#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:41:09.68#ibcon#first serial, iclass 15, count 0 2006.257.07:41:09.68#ibcon#enter sib2, iclass 15, count 0 2006.257.07:41:09.68#ibcon#flushed, iclass 15, count 0 2006.257.07:41:09.68#ibcon#about to write, iclass 15, count 0 2006.257.07:41:09.68#ibcon#wrote, iclass 15, count 0 2006.257.07:41:09.68#ibcon#about to read 3, iclass 15, count 0 2006.257.07:41:09.70#ibcon#read 3, iclass 15, count 0 2006.257.07:41:09.70#ibcon#about to read 4, iclass 15, count 0 2006.257.07:41:09.70#ibcon#read 4, iclass 15, count 0 2006.257.07:41:09.70#ibcon#about to read 5, iclass 15, count 0 2006.257.07:41:09.70#ibcon#read 5, iclass 15, count 0 2006.257.07:41:09.70#ibcon#about to read 6, iclass 15, count 0 2006.257.07:41:09.70#ibcon#read 6, iclass 15, count 0 2006.257.07:41:09.70#ibcon#end of sib2, iclass 15, count 0 2006.257.07:41:09.70#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:41:09.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:41:09.70#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.07:41:09.70#ibcon#*before write, iclass 15, count 0 2006.257.07:41:09.70#ibcon#enter sib2, iclass 15, count 0 2006.257.07:41:09.70#ibcon#flushed, iclass 15, count 0 2006.257.07:41:09.70#ibcon#about to write, iclass 15, count 0 2006.257.07:41:09.70#ibcon#wrote, iclass 15, count 0 2006.257.07:41:09.70#ibcon#about to read 3, iclass 15, count 0 2006.257.07:41:09.74#ibcon#read 3, iclass 15, count 0 2006.257.07:41:09.74#ibcon#about to read 4, iclass 15, count 0 2006.257.07:41:09.74#ibcon#read 4, iclass 15, count 0 2006.257.07:41:09.74#ibcon#about to read 5, iclass 15, count 0 2006.257.07:41:09.74#ibcon#read 5, iclass 15, count 0 2006.257.07:41:09.74#ibcon#about to read 6, iclass 15, count 0 2006.257.07:41:09.74#ibcon#read 6, iclass 15, count 0 2006.257.07:41:09.74#ibcon#end of sib2, iclass 15, count 0 2006.257.07:41:09.74#ibcon#*after write, iclass 15, count 0 2006.257.07:41:09.74#ibcon#*before return 0, iclass 15, count 0 2006.257.07:41:09.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:09.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.07:41:09.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:41:09.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:41:09.74$vck44/vb=6,4 2006.257.07:41:09.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.07:41:09.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.07:41:09.74#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:09.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:09.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:09.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:09.80#ibcon#enter wrdev, iclass 17, count 2 2006.257.07:41:09.80#ibcon#first serial, iclass 17, count 2 2006.257.07:41:09.80#ibcon#enter sib2, iclass 17, count 2 2006.257.07:41:09.80#ibcon#flushed, iclass 17, count 2 2006.257.07:41:09.80#ibcon#about to write, iclass 17, count 2 2006.257.07:41:09.80#ibcon#wrote, iclass 17, count 2 2006.257.07:41:09.80#ibcon#about to read 3, iclass 17, count 2 2006.257.07:41:09.82#ibcon#read 3, iclass 17, count 2 2006.257.07:41:09.82#ibcon#about to read 4, iclass 17, count 2 2006.257.07:41:09.82#ibcon#read 4, iclass 17, count 2 2006.257.07:41:09.82#ibcon#about to read 5, iclass 17, count 2 2006.257.07:41:09.82#ibcon#read 5, iclass 17, count 2 2006.257.07:41:09.82#ibcon#about to read 6, iclass 17, count 2 2006.257.07:41:09.82#ibcon#read 6, iclass 17, count 2 2006.257.07:41:09.82#ibcon#end of sib2, iclass 17, count 2 2006.257.07:41:09.82#ibcon#*mode == 0, iclass 17, count 2 2006.257.07:41:09.82#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.07:41:09.82#ibcon#[27=AT06-04\r\n] 2006.257.07:41:09.82#ibcon#*before write, iclass 17, count 2 2006.257.07:41:09.82#ibcon#enter sib2, iclass 17, count 2 2006.257.07:41:09.82#ibcon#flushed, iclass 17, count 2 2006.257.07:41:09.82#ibcon#about to write, iclass 17, count 2 2006.257.07:41:09.82#ibcon#wrote, iclass 17, count 2 2006.257.07:41:09.82#ibcon#about to read 3, iclass 17, count 2 2006.257.07:41:09.85#ibcon#read 3, iclass 17, count 2 2006.257.07:41:09.85#ibcon#about to read 4, iclass 17, count 2 2006.257.07:41:09.85#ibcon#read 4, iclass 17, count 2 2006.257.07:41:09.85#ibcon#about to read 5, iclass 17, count 2 2006.257.07:41:09.85#ibcon#read 5, iclass 17, count 2 2006.257.07:41:09.85#ibcon#about to read 6, iclass 17, count 2 2006.257.07:41:09.85#ibcon#read 6, iclass 17, count 2 2006.257.07:41:09.85#ibcon#end of sib2, iclass 17, count 2 2006.257.07:41:09.85#ibcon#*after write, iclass 17, count 2 2006.257.07:41:09.85#ibcon#*before return 0, iclass 17, count 2 2006.257.07:41:09.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:09.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.07:41:09.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.07:41:09.85#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:09.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:09.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:09.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:09.97#ibcon#enter wrdev, iclass 17, count 0 2006.257.07:41:09.97#ibcon#first serial, iclass 17, count 0 2006.257.07:41:09.97#ibcon#enter sib2, iclass 17, count 0 2006.257.07:41:09.97#ibcon#flushed, iclass 17, count 0 2006.257.07:41:09.97#ibcon#about to write, iclass 17, count 0 2006.257.07:41:09.97#ibcon#wrote, iclass 17, count 0 2006.257.07:41:09.97#ibcon#about to read 3, iclass 17, count 0 2006.257.07:41:09.99#ibcon#read 3, iclass 17, count 0 2006.257.07:41:09.99#ibcon#about to read 4, iclass 17, count 0 2006.257.07:41:09.99#ibcon#read 4, iclass 17, count 0 2006.257.07:41:09.99#ibcon#about to read 5, iclass 17, count 0 2006.257.07:41:09.99#ibcon#read 5, iclass 17, count 0 2006.257.07:41:09.99#ibcon#about to read 6, iclass 17, count 0 2006.257.07:41:09.99#ibcon#read 6, iclass 17, count 0 2006.257.07:41:09.99#ibcon#end of sib2, iclass 17, count 0 2006.257.07:41:09.99#ibcon#*mode == 0, iclass 17, count 0 2006.257.07:41:09.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.07:41:09.99#ibcon#[27=USB\r\n] 2006.257.07:41:09.99#ibcon#*before write, iclass 17, count 0 2006.257.07:41:09.99#ibcon#enter sib2, iclass 17, count 0 2006.257.07:41:09.99#ibcon#flushed, iclass 17, count 0 2006.257.07:41:09.99#ibcon#about to write, iclass 17, count 0 2006.257.07:41:09.99#ibcon#wrote, iclass 17, count 0 2006.257.07:41:09.99#ibcon#about to read 3, iclass 17, count 0 2006.257.07:41:10.02#ibcon#read 3, iclass 17, count 0 2006.257.07:41:10.02#ibcon#about to read 4, iclass 17, count 0 2006.257.07:41:10.02#ibcon#read 4, iclass 17, count 0 2006.257.07:41:10.02#ibcon#about to read 5, iclass 17, count 0 2006.257.07:41:10.02#ibcon#read 5, iclass 17, count 0 2006.257.07:41:10.02#ibcon#about to read 6, iclass 17, count 0 2006.257.07:41:10.02#ibcon#read 6, iclass 17, count 0 2006.257.07:41:10.02#ibcon#end of sib2, iclass 17, count 0 2006.257.07:41:10.02#ibcon#*after write, iclass 17, count 0 2006.257.07:41:10.02#ibcon#*before return 0, iclass 17, count 0 2006.257.07:41:10.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:10.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.07:41:10.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.07:41:10.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.07:41:10.02$vck44/vblo=7,734.99 2006.257.07:41:10.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.07:41:10.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.07:41:10.02#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:10.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:10.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:10.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:10.02#ibcon#enter wrdev, iclass 19, count 0 2006.257.07:41:10.02#ibcon#first serial, iclass 19, count 0 2006.257.07:41:10.02#ibcon#enter sib2, iclass 19, count 0 2006.257.07:41:10.02#ibcon#flushed, iclass 19, count 0 2006.257.07:41:10.02#ibcon#about to write, iclass 19, count 0 2006.257.07:41:10.02#ibcon#wrote, iclass 19, count 0 2006.257.07:41:10.02#ibcon#about to read 3, iclass 19, count 0 2006.257.07:41:10.04#ibcon#read 3, iclass 19, count 0 2006.257.07:41:10.04#ibcon#about to read 4, iclass 19, count 0 2006.257.07:41:10.04#ibcon#read 4, iclass 19, count 0 2006.257.07:41:10.04#ibcon#about to read 5, iclass 19, count 0 2006.257.07:41:10.04#ibcon#read 5, iclass 19, count 0 2006.257.07:41:10.04#ibcon#about to read 6, iclass 19, count 0 2006.257.07:41:10.04#ibcon#read 6, iclass 19, count 0 2006.257.07:41:10.04#ibcon#end of sib2, iclass 19, count 0 2006.257.07:41:10.04#ibcon#*mode == 0, iclass 19, count 0 2006.257.07:41:10.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.07:41:10.04#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.07:41:10.04#ibcon#*before write, iclass 19, count 0 2006.257.07:41:10.04#ibcon#enter sib2, iclass 19, count 0 2006.257.07:41:10.04#ibcon#flushed, iclass 19, count 0 2006.257.07:41:10.04#ibcon#about to write, iclass 19, count 0 2006.257.07:41:10.04#ibcon#wrote, iclass 19, count 0 2006.257.07:41:10.04#ibcon#about to read 3, iclass 19, count 0 2006.257.07:41:10.08#ibcon#read 3, iclass 19, count 0 2006.257.07:41:10.08#ibcon#about to read 4, iclass 19, count 0 2006.257.07:41:10.08#ibcon#read 4, iclass 19, count 0 2006.257.07:41:10.08#ibcon#about to read 5, iclass 19, count 0 2006.257.07:41:10.08#ibcon#read 5, iclass 19, count 0 2006.257.07:41:10.08#ibcon#about to read 6, iclass 19, count 0 2006.257.07:41:10.08#ibcon#read 6, iclass 19, count 0 2006.257.07:41:10.08#ibcon#end of sib2, iclass 19, count 0 2006.257.07:41:10.08#ibcon#*after write, iclass 19, count 0 2006.257.07:41:10.08#ibcon#*before return 0, iclass 19, count 0 2006.257.07:41:10.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:10.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.07:41:10.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.07:41:10.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.07:41:10.08$vck44/vb=7,4 2006.257.07:41:10.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.07:41:10.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.07:41:10.08#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:10.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:10.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:10.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:10.14#ibcon#enter wrdev, iclass 21, count 2 2006.257.07:41:10.14#ibcon#first serial, iclass 21, count 2 2006.257.07:41:10.14#ibcon#enter sib2, iclass 21, count 2 2006.257.07:41:10.14#ibcon#flushed, iclass 21, count 2 2006.257.07:41:10.14#ibcon#about to write, iclass 21, count 2 2006.257.07:41:10.14#ibcon#wrote, iclass 21, count 2 2006.257.07:41:10.14#ibcon#about to read 3, iclass 21, count 2 2006.257.07:41:10.16#ibcon#read 3, iclass 21, count 2 2006.257.07:41:10.16#ibcon#about to read 4, iclass 21, count 2 2006.257.07:41:10.16#ibcon#read 4, iclass 21, count 2 2006.257.07:41:10.16#ibcon#about to read 5, iclass 21, count 2 2006.257.07:41:10.16#ibcon#read 5, iclass 21, count 2 2006.257.07:41:10.16#ibcon#about to read 6, iclass 21, count 2 2006.257.07:41:10.16#ibcon#read 6, iclass 21, count 2 2006.257.07:41:10.16#ibcon#end of sib2, iclass 21, count 2 2006.257.07:41:10.16#ibcon#*mode == 0, iclass 21, count 2 2006.257.07:41:10.16#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.07:41:10.16#ibcon#[27=AT07-04\r\n] 2006.257.07:41:10.16#ibcon#*before write, iclass 21, count 2 2006.257.07:41:10.16#ibcon#enter sib2, iclass 21, count 2 2006.257.07:41:10.16#ibcon#flushed, iclass 21, count 2 2006.257.07:41:10.16#ibcon#about to write, iclass 21, count 2 2006.257.07:41:10.16#ibcon#wrote, iclass 21, count 2 2006.257.07:41:10.16#ibcon#about to read 3, iclass 21, count 2 2006.257.07:41:10.19#ibcon#read 3, iclass 21, count 2 2006.257.07:41:10.19#ibcon#about to read 4, iclass 21, count 2 2006.257.07:41:10.19#ibcon#read 4, iclass 21, count 2 2006.257.07:41:10.19#ibcon#about to read 5, iclass 21, count 2 2006.257.07:41:10.19#ibcon#read 5, iclass 21, count 2 2006.257.07:41:10.19#ibcon#about to read 6, iclass 21, count 2 2006.257.07:41:10.19#ibcon#read 6, iclass 21, count 2 2006.257.07:41:10.19#ibcon#end of sib2, iclass 21, count 2 2006.257.07:41:10.19#ibcon#*after write, iclass 21, count 2 2006.257.07:41:10.19#ibcon#*before return 0, iclass 21, count 2 2006.257.07:41:10.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:10.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.07:41:10.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.07:41:10.19#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:10.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:10.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:10.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:10.31#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:41:10.31#ibcon#first serial, iclass 21, count 0 2006.257.07:41:10.31#ibcon#enter sib2, iclass 21, count 0 2006.257.07:41:10.31#ibcon#flushed, iclass 21, count 0 2006.257.07:41:10.31#ibcon#about to write, iclass 21, count 0 2006.257.07:41:10.31#ibcon#wrote, iclass 21, count 0 2006.257.07:41:10.31#ibcon#about to read 3, iclass 21, count 0 2006.257.07:41:10.33#ibcon#read 3, iclass 21, count 0 2006.257.07:41:10.33#ibcon#about to read 4, iclass 21, count 0 2006.257.07:41:10.33#ibcon#read 4, iclass 21, count 0 2006.257.07:41:10.33#ibcon#about to read 5, iclass 21, count 0 2006.257.07:41:10.33#ibcon#read 5, iclass 21, count 0 2006.257.07:41:10.33#ibcon#about to read 6, iclass 21, count 0 2006.257.07:41:10.33#ibcon#read 6, iclass 21, count 0 2006.257.07:41:10.33#ibcon#end of sib2, iclass 21, count 0 2006.257.07:41:10.33#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:41:10.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:41:10.33#ibcon#[27=USB\r\n] 2006.257.07:41:10.33#ibcon#*before write, iclass 21, count 0 2006.257.07:41:10.33#ibcon#enter sib2, iclass 21, count 0 2006.257.07:41:10.33#ibcon#flushed, iclass 21, count 0 2006.257.07:41:10.33#ibcon#about to write, iclass 21, count 0 2006.257.07:41:10.33#ibcon#wrote, iclass 21, count 0 2006.257.07:41:10.33#ibcon#about to read 3, iclass 21, count 0 2006.257.07:41:10.36#ibcon#read 3, iclass 21, count 0 2006.257.07:41:10.36#ibcon#about to read 4, iclass 21, count 0 2006.257.07:41:10.36#ibcon#read 4, iclass 21, count 0 2006.257.07:41:10.36#ibcon#about to read 5, iclass 21, count 0 2006.257.07:41:10.36#ibcon#read 5, iclass 21, count 0 2006.257.07:41:10.36#ibcon#about to read 6, iclass 21, count 0 2006.257.07:41:10.36#ibcon#read 6, iclass 21, count 0 2006.257.07:41:10.36#ibcon#end of sib2, iclass 21, count 0 2006.257.07:41:10.36#ibcon#*after write, iclass 21, count 0 2006.257.07:41:10.36#ibcon#*before return 0, iclass 21, count 0 2006.257.07:41:10.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:10.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.07:41:10.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:41:10.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:41:10.36$vck44/vblo=8,744.99 2006.257.07:41:10.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.07:41:10.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.07:41:10.36#ibcon#ireg 17 cls_cnt 0 2006.257.07:41:10.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:10.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:10.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:10.36#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:41:10.36#ibcon#first serial, iclass 23, count 0 2006.257.07:41:10.36#ibcon#enter sib2, iclass 23, count 0 2006.257.07:41:10.36#ibcon#flushed, iclass 23, count 0 2006.257.07:41:10.36#ibcon#about to write, iclass 23, count 0 2006.257.07:41:10.36#ibcon#wrote, iclass 23, count 0 2006.257.07:41:10.36#ibcon#about to read 3, iclass 23, count 0 2006.257.07:41:10.38#ibcon#read 3, iclass 23, count 0 2006.257.07:41:10.38#ibcon#about to read 4, iclass 23, count 0 2006.257.07:41:10.38#ibcon#read 4, iclass 23, count 0 2006.257.07:41:10.38#ibcon#about to read 5, iclass 23, count 0 2006.257.07:41:10.38#ibcon#read 5, iclass 23, count 0 2006.257.07:41:10.38#ibcon#about to read 6, iclass 23, count 0 2006.257.07:41:10.38#ibcon#read 6, iclass 23, count 0 2006.257.07:41:10.38#ibcon#end of sib2, iclass 23, count 0 2006.257.07:41:10.38#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:41:10.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:41:10.38#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.07:41:10.38#ibcon#*before write, iclass 23, count 0 2006.257.07:41:10.38#ibcon#enter sib2, iclass 23, count 0 2006.257.07:41:10.38#ibcon#flushed, iclass 23, count 0 2006.257.07:41:10.38#ibcon#about to write, iclass 23, count 0 2006.257.07:41:10.38#ibcon#wrote, iclass 23, count 0 2006.257.07:41:10.38#ibcon#about to read 3, iclass 23, count 0 2006.257.07:41:10.42#ibcon#read 3, iclass 23, count 0 2006.257.07:41:10.42#ibcon#about to read 4, iclass 23, count 0 2006.257.07:41:10.42#ibcon#read 4, iclass 23, count 0 2006.257.07:41:10.42#ibcon#about to read 5, iclass 23, count 0 2006.257.07:41:10.42#ibcon#read 5, iclass 23, count 0 2006.257.07:41:10.42#ibcon#about to read 6, iclass 23, count 0 2006.257.07:41:10.42#ibcon#read 6, iclass 23, count 0 2006.257.07:41:10.42#ibcon#end of sib2, iclass 23, count 0 2006.257.07:41:10.42#ibcon#*after write, iclass 23, count 0 2006.257.07:41:10.42#ibcon#*before return 0, iclass 23, count 0 2006.257.07:41:10.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:10.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.07:41:10.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:41:10.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:41:10.42$vck44/vb=8,4 2006.257.07:41:10.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.07:41:10.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.07:41:10.42#ibcon#ireg 11 cls_cnt 2 2006.257.07:41:10.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:10.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:10.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:10.48#ibcon#enter wrdev, iclass 25, count 2 2006.257.07:41:10.48#ibcon#first serial, iclass 25, count 2 2006.257.07:41:10.48#ibcon#enter sib2, iclass 25, count 2 2006.257.07:41:10.48#ibcon#flushed, iclass 25, count 2 2006.257.07:41:10.48#ibcon#about to write, iclass 25, count 2 2006.257.07:41:10.48#ibcon#wrote, iclass 25, count 2 2006.257.07:41:10.48#ibcon#about to read 3, iclass 25, count 2 2006.257.07:41:10.50#ibcon#read 3, iclass 25, count 2 2006.257.07:41:10.50#ibcon#about to read 4, iclass 25, count 2 2006.257.07:41:10.50#ibcon#read 4, iclass 25, count 2 2006.257.07:41:10.50#ibcon#about to read 5, iclass 25, count 2 2006.257.07:41:10.50#ibcon#read 5, iclass 25, count 2 2006.257.07:41:10.50#ibcon#about to read 6, iclass 25, count 2 2006.257.07:41:10.50#ibcon#read 6, iclass 25, count 2 2006.257.07:41:10.50#ibcon#end of sib2, iclass 25, count 2 2006.257.07:41:10.50#ibcon#*mode == 0, iclass 25, count 2 2006.257.07:41:10.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.07:41:10.50#ibcon#[27=AT08-04\r\n] 2006.257.07:41:10.50#ibcon#*before write, iclass 25, count 2 2006.257.07:41:10.50#ibcon#enter sib2, iclass 25, count 2 2006.257.07:41:10.50#ibcon#flushed, iclass 25, count 2 2006.257.07:41:10.50#ibcon#about to write, iclass 25, count 2 2006.257.07:41:10.50#ibcon#wrote, iclass 25, count 2 2006.257.07:41:10.50#ibcon#about to read 3, iclass 25, count 2 2006.257.07:41:10.53#ibcon#read 3, iclass 25, count 2 2006.257.07:41:10.53#ibcon#about to read 4, iclass 25, count 2 2006.257.07:41:10.53#ibcon#read 4, iclass 25, count 2 2006.257.07:41:10.53#ibcon#about to read 5, iclass 25, count 2 2006.257.07:41:10.53#ibcon#read 5, iclass 25, count 2 2006.257.07:41:10.53#ibcon#about to read 6, iclass 25, count 2 2006.257.07:41:10.53#ibcon#read 6, iclass 25, count 2 2006.257.07:41:10.53#ibcon#end of sib2, iclass 25, count 2 2006.257.07:41:10.53#ibcon#*after write, iclass 25, count 2 2006.257.07:41:10.53#ibcon#*before return 0, iclass 25, count 2 2006.257.07:41:10.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:10.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.07:41:10.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.07:41:10.53#ibcon#ireg 7 cls_cnt 0 2006.257.07:41:10.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:10.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:10.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:10.65#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:41:10.65#ibcon#first serial, iclass 25, count 0 2006.257.07:41:10.65#ibcon#enter sib2, iclass 25, count 0 2006.257.07:41:10.65#ibcon#flushed, iclass 25, count 0 2006.257.07:41:10.65#ibcon#about to write, iclass 25, count 0 2006.257.07:41:10.65#ibcon#wrote, iclass 25, count 0 2006.257.07:41:10.65#ibcon#about to read 3, iclass 25, count 0 2006.257.07:41:10.67#ibcon#read 3, iclass 25, count 0 2006.257.07:41:10.67#ibcon#about to read 4, iclass 25, count 0 2006.257.07:41:10.67#ibcon#read 4, iclass 25, count 0 2006.257.07:41:10.67#ibcon#about to read 5, iclass 25, count 0 2006.257.07:41:10.67#ibcon#read 5, iclass 25, count 0 2006.257.07:41:10.67#ibcon#about to read 6, iclass 25, count 0 2006.257.07:41:10.67#ibcon#read 6, iclass 25, count 0 2006.257.07:41:10.67#ibcon#end of sib2, iclass 25, count 0 2006.257.07:41:10.67#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:41:10.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:41:10.67#ibcon#[27=USB\r\n] 2006.257.07:41:10.67#ibcon#*before write, iclass 25, count 0 2006.257.07:41:10.67#ibcon#enter sib2, iclass 25, count 0 2006.257.07:41:10.67#ibcon#flushed, iclass 25, count 0 2006.257.07:41:10.67#ibcon#about to write, iclass 25, count 0 2006.257.07:41:10.67#ibcon#wrote, iclass 25, count 0 2006.257.07:41:10.67#ibcon#about to read 3, iclass 25, count 0 2006.257.07:41:10.70#ibcon#read 3, iclass 25, count 0 2006.257.07:41:10.70#ibcon#about to read 4, iclass 25, count 0 2006.257.07:41:10.70#ibcon#read 4, iclass 25, count 0 2006.257.07:41:10.70#ibcon#about to read 5, iclass 25, count 0 2006.257.07:41:10.70#ibcon#read 5, iclass 25, count 0 2006.257.07:41:10.70#ibcon#about to read 6, iclass 25, count 0 2006.257.07:41:10.70#ibcon#read 6, iclass 25, count 0 2006.257.07:41:10.70#ibcon#end of sib2, iclass 25, count 0 2006.257.07:41:10.70#ibcon#*after write, iclass 25, count 0 2006.257.07:41:10.70#ibcon#*before return 0, iclass 25, count 0 2006.257.07:41:10.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:10.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.07:41:10.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:41:10.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:41:10.70$vck44/vabw=wide 2006.257.07:41:10.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.07:41:10.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.07:41:10.70#ibcon#ireg 8 cls_cnt 0 2006.257.07:41:10.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:10.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:10.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:10.70#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:41:10.70#ibcon#first serial, iclass 27, count 0 2006.257.07:41:10.70#ibcon#enter sib2, iclass 27, count 0 2006.257.07:41:10.70#ibcon#flushed, iclass 27, count 0 2006.257.07:41:10.70#ibcon#about to write, iclass 27, count 0 2006.257.07:41:10.70#ibcon#wrote, iclass 27, count 0 2006.257.07:41:10.70#ibcon#about to read 3, iclass 27, count 0 2006.257.07:41:10.72#ibcon#read 3, iclass 27, count 0 2006.257.07:41:10.72#ibcon#about to read 4, iclass 27, count 0 2006.257.07:41:10.72#ibcon#read 4, iclass 27, count 0 2006.257.07:41:10.72#ibcon#about to read 5, iclass 27, count 0 2006.257.07:41:10.72#ibcon#read 5, iclass 27, count 0 2006.257.07:41:10.72#ibcon#about to read 6, iclass 27, count 0 2006.257.07:41:10.72#ibcon#read 6, iclass 27, count 0 2006.257.07:41:10.72#ibcon#end of sib2, iclass 27, count 0 2006.257.07:41:10.72#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:41:10.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:41:10.72#ibcon#[25=BW32\r\n] 2006.257.07:41:10.72#ibcon#*before write, iclass 27, count 0 2006.257.07:41:10.72#ibcon#enter sib2, iclass 27, count 0 2006.257.07:41:10.72#ibcon#flushed, iclass 27, count 0 2006.257.07:41:10.72#ibcon#about to write, iclass 27, count 0 2006.257.07:41:10.72#ibcon#wrote, iclass 27, count 0 2006.257.07:41:10.72#ibcon#about to read 3, iclass 27, count 0 2006.257.07:41:10.75#ibcon#read 3, iclass 27, count 0 2006.257.07:41:10.75#ibcon#about to read 4, iclass 27, count 0 2006.257.07:41:10.75#ibcon#read 4, iclass 27, count 0 2006.257.07:41:10.75#ibcon#about to read 5, iclass 27, count 0 2006.257.07:41:10.75#ibcon#read 5, iclass 27, count 0 2006.257.07:41:10.75#ibcon#about to read 6, iclass 27, count 0 2006.257.07:41:10.75#ibcon#read 6, iclass 27, count 0 2006.257.07:41:10.75#ibcon#end of sib2, iclass 27, count 0 2006.257.07:41:10.75#ibcon#*after write, iclass 27, count 0 2006.257.07:41:10.75#ibcon#*before return 0, iclass 27, count 0 2006.257.07:41:10.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:10.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:41:10.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:41:10.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:41:10.75$vck44/vbbw=wide 2006.257.07:41:10.75#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.07:41:10.75#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.07:41:10.75#ibcon#ireg 8 cls_cnt 0 2006.257.07:41:10.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:41:10.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:41:10.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:41:10.82#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:41:10.82#ibcon#first serial, iclass 29, count 0 2006.257.07:41:10.82#ibcon#enter sib2, iclass 29, count 0 2006.257.07:41:10.82#ibcon#flushed, iclass 29, count 0 2006.257.07:41:10.82#ibcon#about to write, iclass 29, count 0 2006.257.07:41:10.82#ibcon#wrote, iclass 29, count 0 2006.257.07:41:10.82#ibcon#about to read 3, iclass 29, count 0 2006.257.07:41:10.84#ibcon#read 3, iclass 29, count 0 2006.257.07:41:10.84#ibcon#about to read 4, iclass 29, count 0 2006.257.07:41:10.84#ibcon#read 4, iclass 29, count 0 2006.257.07:41:10.84#ibcon#about to read 5, iclass 29, count 0 2006.257.07:41:10.84#ibcon#read 5, iclass 29, count 0 2006.257.07:41:10.84#ibcon#about to read 6, iclass 29, count 0 2006.257.07:41:10.84#ibcon#read 6, iclass 29, count 0 2006.257.07:41:10.84#ibcon#end of sib2, iclass 29, count 0 2006.257.07:41:10.84#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:41:10.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:41:10.84#ibcon#[27=BW32\r\n] 2006.257.07:41:10.84#ibcon#*before write, iclass 29, count 0 2006.257.07:41:10.84#ibcon#enter sib2, iclass 29, count 0 2006.257.07:41:10.84#ibcon#flushed, iclass 29, count 0 2006.257.07:41:10.84#ibcon#about to write, iclass 29, count 0 2006.257.07:41:10.84#ibcon#wrote, iclass 29, count 0 2006.257.07:41:10.84#ibcon#about to read 3, iclass 29, count 0 2006.257.07:41:10.87#ibcon#read 3, iclass 29, count 0 2006.257.07:41:10.87#ibcon#about to read 4, iclass 29, count 0 2006.257.07:41:10.87#ibcon#read 4, iclass 29, count 0 2006.257.07:41:10.87#ibcon#about to read 5, iclass 29, count 0 2006.257.07:41:10.87#ibcon#read 5, iclass 29, count 0 2006.257.07:41:10.87#ibcon#about to read 6, iclass 29, count 0 2006.257.07:41:10.87#ibcon#read 6, iclass 29, count 0 2006.257.07:41:10.87#ibcon#end of sib2, iclass 29, count 0 2006.257.07:41:10.87#ibcon#*after write, iclass 29, count 0 2006.257.07:41:10.87#ibcon#*before return 0, iclass 29, count 0 2006.257.07:41:10.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:41:10.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:41:10.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:41:10.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:41:10.87$setupk4/ifdk4 2006.257.07:41:10.87$ifdk4/lo= 2006.257.07:41:10.87$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.07:41:10.87$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.07:41:10.87$ifdk4/patch= 2006.257.07:41:10.87$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.07:41:10.87$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.07:41:10.87$setupk4/!*+20s 2006.257.07:41:15.69#abcon#<5=/16 1.1 2.5 21.17 871012.6\r\n> 2006.257.07:41:15.71#abcon#{5=INTERFACE CLEAR} 2006.257.07:41:15.77#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:41:25.38$setupk4/"tpicd 2006.257.07:41:25.38$setupk4/echo=off 2006.257.07:41:25.38$setupk4/xlog=off 2006.257.07:41:25.38:!2006.257.07:44:54 2006.257.07:41:43.13#trakl#Source acquired 2006.257.07:41:43.13#flagr#flagr/antenna,acquired 2006.257.07:44:54.00:preob 2006.257.07:44:54.14/onsource/TRACKING 2006.257.07:44:54.14:!2006.257.07:45:04 2006.257.07:45:04.00:"tape 2006.257.07:45:04.00:"st=record 2006.257.07:45:04.00:data_valid=on 2006.257.07:45:04.00:midob 2006.257.07:45:04.14/onsource/TRACKING 2006.257.07:45:04.14/wx/21.15,1012.7,87 2006.257.07:45:04.24/cable/+6.4755E-03 2006.257.07:45:05.33/va/01,08,usb,yes,33,36 2006.257.07:45:05.33/va/02,07,usb,yes,36,37 2006.257.07:45:05.33/va/03,08,usb,yes,32,34 2006.257.07:45:05.33/va/04,07,usb,yes,37,39 2006.257.07:45:05.33/va/05,04,usb,yes,33,34 2006.257.07:45:05.33/va/06,04,usb,yes,37,37 2006.257.07:45:05.33/va/07,04,usb,yes,38,39 2006.257.07:45:05.33/va/08,04,usb,yes,32,39 2006.257.07:45:05.56/valo/01,524.99,yes,locked 2006.257.07:45:05.56/valo/02,534.99,yes,locked 2006.257.07:45:05.56/valo/03,564.99,yes,locked 2006.257.07:45:05.56/valo/04,624.99,yes,locked 2006.257.07:45:05.56/valo/05,734.99,yes,locked 2006.257.07:45:05.56/valo/06,814.99,yes,locked 2006.257.07:45:05.56/valo/07,864.99,yes,locked 2006.257.07:45:05.56/valo/08,884.99,yes,locked 2006.257.07:45:06.65/vb/01,04,usb,yes,32,30 2006.257.07:45:06.65/vb/02,05,usb,yes,31,31 2006.257.07:45:06.65/vb/03,04,usb,yes,32,35 2006.257.07:45:06.65/vb/04,05,usb,yes,32,31 2006.257.07:45:06.65/vb/05,04,usb,yes,30,31 2006.257.07:45:06.65/vb/06,04,usb,yes,35,30 2006.257.07:45:06.65/vb/07,04,usb,yes,33,34 2006.257.07:45:06.65/vb/08,04,usb,yes,30,34 2006.257.07:45:06.89/vblo/01,629.99,yes,locked 2006.257.07:45:06.89/vblo/02,634.99,yes,locked 2006.257.07:45:06.89/vblo/03,649.99,yes,locked 2006.257.07:45:06.89/vblo/04,679.99,yes,locked 2006.257.07:45:06.89/vblo/05,709.99,yes,locked 2006.257.07:45:06.89/vblo/06,719.99,yes,locked 2006.257.07:45:06.89/vblo/07,734.99,yes,locked 2006.257.07:45:06.89/vblo/08,744.99,yes,locked 2006.257.07:45:07.04/vabw/8 2006.257.07:45:07.19/vbbw/8 2006.257.07:45:07.28/xfe/off,on,14.5 2006.257.07:45:07.66/ifatt/23,28,28,28 2006.257.07:45:08.08/fmout-gps/S +4.52E-07 2006.257.07:45:08.12:!2006.257.07:47:24 2006.257.07:47:24.00:data_valid=off 2006.257.07:47:24.00:"et 2006.257.07:47:24.00:!+3s 2006.257.07:47:27.01:"tape 2006.257.07:47:27.01:postob 2006.257.07:47:27.07/cable/+6.4754E-03 2006.257.07:47:27.07/wx/21.13,1012.8,87 2006.257.07:47:28.08/fmout-gps/S +4.51E-07 2006.257.07:47:28.08:scan_name=257-0748,jd0609,180 2006.257.07:47:28.08:source=2201+315,220314.98,314538.3,2000.0,cw 2006.257.07:47:29.14#flagr#flagr/antenna,new-source 2006.257.07:47:29.14:checkk5 2006.257.07:47:29.53/chk_autoobs//k5ts1/ autoobs is running! 2006.257.07:47:29.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.07:47:30.41/chk_autoobs//k5ts3/ autoobs is running! 2006.257.07:47:30.80/chk_autoobs//k5ts4/ autoobs is running! 2006.257.07:47:31.20/chk_obsdata//k5ts1/T2570745??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.07:47:31.62/chk_obsdata//k5ts2/T2570745??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.07:47:32.03/chk_obsdata//k5ts3/T2570745??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.07:47:32.42/chk_obsdata//k5ts4/T2570745??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.07:47:33.17/k5log//k5ts1_log_newline 2006.257.07:47:33.88/k5log//k5ts2_log_newline 2006.257.07:47:34.63/k5log//k5ts3_log_newline 2006.257.07:47:35.34/k5log//k5ts4_log_newline 2006.257.07:47:35.36/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.07:47:35.36:setupk4=1 2006.257.07:47:35.36$setupk4/echo=on 2006.257.07:47:35.36$setupk4/pcalon 2006.257.07:47:35.36$pcalon/"no phase cal control is implemented here 2006.257.07:47:35.36$setupk4/"tpicd=stop 2006.257.07:47:35.36$setupk4/"rec=synch_on 2006.257.07:47:35.36$setupk4/"rec_mode=128 2006.257.07:47:35.36$setupk4/!* 2006.257.07:47:35.36$setupk4/recpk4 2006.257.07:47:35.36$recpk4/recpatch= 2006.257.07:47:35.37$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.07:47:35.37$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.07:47:35.37$setupk4/vck44 2006.257.07:47:35.37$vck44/valo=1,524.99 2006.257.07:47:35.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.07:47:35.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.07:47:35.37#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:35.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:35.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:35.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:35.37#ibcon#enter wrdev, iclass 4, count 0 2006.257.07:47:35.37#ibcon#first serial, iclass 4, count 0 2006.257.07:47:35.37#ibcon#enter sib2, iclass 4, count 0 2006.257.07:47:35.37#ibcon#flushed, iclass 4, count 0 2006.257.07:47:35.37#ibcon#about to write, iclass 4, count 0 2006.257.07:47:35.37#ibcon#wrote, iclass 4, count 0 2006.257.07:47:35.37#ibcon#about to read 3, iclass 4, count 0 2006.257.07:47:35.39#ibcon#read 3, iclass 4, count 0 2006.257.07:47:35.39#ibcon#about to read 4, iclass 4, count 0 2006.257.07:47:35.39#ibcon#read 4, iclass 4, count 0 2006.257.07:47:35.39#ibcon#about to read 5, iclass 4, count 0 2006.257.07:47:35.39#ibcon#read 5, iclass 4, count 0 2006.257.07:47:35.39#ibcon#about to read 6, iclass 4, count 0 2006.257.07:47:35.39#ibcon#read 6, iclass 4, count 0 2006.257.07:47:35.39#ibcon#end of sib2, iclass 4, count 0 2006.257.07:47:35.39#ibcon#*mode == 0, iclass 4, count 0 2006.257.07:47:35.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.07:47:35.39#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.07:47:35.39#ibcon#*before write, iclass 4, count 0 2006.257.07:47:35.39#ibcon#enter sib2, iclass 4, count 0 2006.257.07:47:35.39#ibcon#flushed, iclass 4, count 0 2006.257.07:47:35.39#ibcon#about to write, iclass 4, count 0 2006.257.07:47:35.39#ibcon#wrote, iclass 4, count 0 2006.257.07:47:35.39#ibcon#about to read 3, iclass 4, count 0 2006.257.07:47:35.44#ibcon#read 3, iclass 4, count 0 2006.257.07:47:35.44#ibcon#about to read 4, iclass 4, count 0 2006.257.07:47:35.44#ibcon#read 4, iclass 4, count 0 2006.257.07:47:35.44#ibcon#about to read 5, iclass 4, count 0 2006.257.07:47:35.44#ibcon#read 5, iclass 4, count 0 2006.257.07:47:35.44#ibcon#about to read 6, iclass 4, count 0 2006.257.07:47:35.44#ibcon#read 6, iclass 4, count 0 2006.257.07:47:35.44#ibcon#end of sib2, iclass 4, count 0 2006.257.07:47:35.44#ibcon#*after write, iclass 4, count 0 2006.257.07:47:35.44#ibcon#*before return 0, iclass 4, count 0 2006.257.07:47:35.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:35.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:35.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.07:47:35.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.07:47:35.44$vck44/va=1,8 2006.257.07:47:35.44#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.07:47:35.44#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.07:47:35.44#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:35.44#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:35.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:35.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:35.44#ibcon#enter wrdev, iclass 6, count 2 2006.257.07:47:35.44#ibcon#first serial, iclass 6, count 2 2006.257.07:47:35.44#ibcon#enter sib2, iclass 6, count 2 2006.257.07:47:35.44#ibcon#flushed, iclass 6, count 2 2006.257.07:47:35.44#ibcon#about to write, iclass 6, count 2 2006.257.07:47:35.44#ibcon#wrote, iclass 6, count 2 2006.257.07:47:35.44#ibcon#about to read 3, iclass 6, count 2 2006.257.07:47:35.46#ibcon#read 3, iclass 6, count 2 2006.257.07:47:35.46#ibcon#about to read 4, iclass 6, count 2 2006.257.07:47:35.46#ibcon#read 4, iclass 6, count 2 2006.257.07:47:35.46#ibcon#about to read 5, iclass 6, count 2 2006.257.07:47:35.46#ibcon#read 5, iclass 6, count 2 2006.257.07:47:35.46#ibcon#about to read 6, iclass 6, count 2 2006.257.07:47:35.46#ibcon#read 6, iclass 6, count 2 2006.257.07:47:35.46#ibcon#end of sib2, iclass 6, count 2 2006.257.07:47:35.46#ibcon#*mode == 0, iclass 6, count 2 2006.257.07:47:35.46#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.07:47:35.46#ibcon#[25=AT01-08\r\n] 2006.257.07:47:35.46#ibcon#*before write, iclass 6, count 2 2006.257.07:47:35.46#ibcon#enter sib2, iclass 6, count 2 2006.257.07:47:35.46#ibcon#flushed, iclass 6, count 2 2006.257.07:47:35.46#ibcon#about to write, iclass 6, count 2 2006.257.07:47:35.46#ibcon#wrote, iclass 6, count 2 2006.257.07:47:35.46#ibcon#about to read 3, iclass 6, count 2 2006.257.07:47:35.49#ibcon#read 3, iclass 6, count 2 2006.257.07:47:35.49#ibcon#about to read 4, iclass 6, count 2 2006.257.07:47:35.49#ibcon#read 4, iclass 6, count 2 2006.257.07:47:35.49#ibcon#about to read 5, iclass 6, count 2 2006.257.07:47:35.49#ibcon#read 5, iclass 6, count 2 2006.257.07:47:35.49#ibcon#about to read 6, iclass 6, count 2 2006.257.07:47:35.49#ibcon#read 6, iclass 6, count 2 2006.257.07:47:35.49#ibcon#end of sib2, iclass 6, count 2 2006.257.07:47:35.49#ibcon#*after write, iclass 6, count 2 2006.257.07:47:35.49#ibcon#*before return 0, iclass 6, count 2 2006.257.07:47:35.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:35.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:35.49#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.07:47:35.49#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:35.49#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:35.61#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:35.61#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:35.61#ibcon#enter wrdev, iclass 6, count 0 2006.257.07:47:35.61#ibcon#first serial, iclass 6, count 0 2006.257.07:47:35.61#ibcon#enter sib2, iclass 6, count 0 2006.257.07:47:35.61#ibcon#flushed, iclass 6, count 0 2006.257.07:47:35.61#ibcon#about to write, iclass 6, count 0 2006.257.07:47:35.61#ibcon#wrote, iclass 6, count 0 2006.257.07:47:35.61#ibcon#about to read 3, iclass 6, count 0 2006.257.07:47:35.63#ibcon#read 3, iclass 6, count 0 2006.257.07:47:35.63#ibcon#about to read 4, iclass 6, count 0 2006.257.07:47:35.63#ibcon#read 4, iclass 6, count 0 2006.257.07:47:35.63#ibcon#about to read 5, iclass 6, count 0 2006.257.07:47:35.63#ibcon#read 5, iclass 6, count 0 2006.257.07:47:35.63#ibcon#about to read 6, iclass 6, count 0 2006.257.07:47:35.63#ibcon#read 6, iclass 6, count 0 2006.257.07:47:35.63#ibcon#end of sib2, iclass 6, count 0 2006.257.07:47:35.63#ibcon#*mode == 0, iclass 6, count 0 2006.257.07:47:35.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.07:47:35.63#ibcon#[25=USB\r\n] 2006.257.07:47:35.63#ibcon#*before write, iclass 6, count 0 2006.257.07:47:35.63#ibcon#enter sib2, iclass 6, count 0 2006.257.07:47:35.63#ibcon#flushed, iclass 6, count 0 2006.257.07:47:35.63#ibcon#about to write, iclass 6, count 0 2006.257.07:47:35.63#ibcon#wrote, iclass 6, count 0 2006.257.07:47:35.63#ibcon#about to read 3, iclass 6, count 0 2006.257.07:47:35.66#ibcon#read 3, iclass 6, count 0 2006.257.07:47:35.66#ibcon#about to read 4, iclass 6, count 0 2006.257.07:47:35.66#ibcon#read 4, iclass 6, count 0 2006.257.07:47:35.66#ibcon#about to read 5, iclass 6, count 0 2006.257.07:47:35.66#ibcon#read 5, iclass 6, count 0 2006.257.07:47:35.66#ibcon#about to read 6, iclass 6, count 0 2006.257.07:47:35.66#ibcon#read 6, iclass 6, count 0 2006.257.07:47:35.66#ibcon#end of sib2, iclass 6, count 0 2006.257.07:47:35.66#ibcon#*after write, iclass 6, count 0 2006.257.07:47:35.66#ibcon#*before return 0, iclass 6, count 0 2006.257.07:47:35.66#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:35.66#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:35.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.07:47:35.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.07:47:35.66$vck44/valo=2,534.99 2006.257.07:47:35.66#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.07:47:35.66#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.07:47:35.66#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:35.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:35.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:35.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:35.66#ibcon#enter wrdev, iclass 10, count 0 2006.257.07:47:35.66#ibcon#first serial, iclass 10, count 0 2006.257.07:47:35.66#ibcon#enter sib2, iclass 10, count 0 2006.257.07:47:35.66#ibcon#flushed, iclass 10, count 0 2006.257.07:47:35.66#ibcon#about to write, iclass 10, count 0 2006.257.07:47:35.66#ibcon#wrote, iclass 10, count 0 2006.257.07:47:35.66#ibcon#about to read 3, iclass 10, count 0 2006.257.07:47:35.68#ibcon#read 3, iclass 10, count 0 2006.257.07:47:35.68#ibcon#about to read 4, iclass 10, count 0 2006.257.07:47:35.68#ibcon#read 4, iclass 10, count 0 2006.257.07:47:35.68#ibcon#about to read 5, iclass 10, count 0 2006.257.07:47:35.68#ibcon#read 5, iclass 10, count 0 2006.257.07:47:35.68#ibcon#about to read 6, iclass 10, count 0 2006.257.07:47:35.68#ibcon#read 6, iclass 10, count 0 2006.257.07:47:35.68#ibcon#end of sib2, iclass 10, count 0 2006.257.07:47:35.68#ibcon#*mode == 0, iclass 10, count 0 2006.257.07:47:35.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.07:47:35.68#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.07:47:35.68#ibcon#*before write, iclass 10, count 0 2006.257.07:47:35.68#ibcon#enter sib2, iclass 10, count 0 2006.257.07:47:35.68#ibcon#flushed, iclass 10, count 0 2006.257.07:47:35.68#ibcon#about to write, iclass 10, count 0 2006.257.07:47:35.68#ibcon#wrote, iclass 10, count 0 2006.257.07:47:35.68#ibcon#about to read 3, iclass 10, count 0 2006.257.07:47:35.72#ibcon#read 3, iclass 10, count 0 2006.257.07:47:35.72#ibcon#about to read 4, iclass 10, count 0 2006.257.07:47:35.72#ibcon#read 4, iclass 10, count 0 2006.257.07:47:35.72#ibcon#about to read 5, iclass 10, count 0 2006.257.07:47:35.72#ibcon#read 5, iclass 10, count 0 2006.257.07:47:35.72#ibcon#about to read 6, iclass 10, count 0 2006.257.07:47:35.72#ibcon#read 6, iclass 10, count 0 2006.257.07:47:35.72#ibcon#end of sib2, iclass 10, count 0 2006.257.07:47:35.72#ibcon#*after write, iclass 10, count 0 2006.257.07:47:35.72#ibcon#*before return 0, iclass 10, count 0 2006.257.07:47:35.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:35.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:35.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.07:47:35.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.07:47:35.72$vck44/va=2,7 2006.257.07:47:35.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.07:47:35.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.07:47:35.72#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:35.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:35.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:35.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:35.78#ibcon#enter wrdev, iclass 12, count 2 2006.257.07:47:35.78#ibcon#first serial, iclass 12, count 2 2006.257.07:47:35.78#ibcon#enter sib2, iclass 12, count 2 2006.257.07:47:35.78#ibcon#flushed, iclass 12, count 2 2006.257.07:47:35.78#ibcon#about to write, iclass 12, count 2 2006.257.07:47:35.78#ibcon#wrote, iclass 12, count 2 2006.257.07:47:35.78#ibcon#about to read 3, iclass 12, count 2 2006.257.07:47:35.80#ibcon#read 3, iclass 12, count 2 2006.257.07:47:35.80#ibcon#about to read 4, iclass 12, count 2 2006.257.07:47:35.80#ibcon#read 4, iclass 12, count 2 2006.257.07:47:35.80#ibcon#about to read 5, iclass 12, count 2 2006.257.07:47:35.80#ibcon#read 5, iclass 12, count 2 2006.257.07:47:35.80#ibcon#about to read 6, iclass 12, count 2 2006.257.07:47:35.80#ibcon#read 6, iclass 12, count 2 2006.257.07:47:35.80#ibcon#end of sib2, iclass 12, count 2 2006.257.07:47:35.80#ibcon#*mode == 0, iclass 12, count 2 2006.257.07:47:35.80#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.07:47:35.80#ibcon#[25=AT02-07\r\n] 2006.257.07:47:35.80#ibcon#*before write, iclass 12, count 2 2006.257.07:47:35.80#ibcon#enter sib2, iclass 12, count 2 2006.257.07:47:35.80#ibcon#flushed, iclass 12, count 2 2006.257.07:47:35.80#ibcon#about to write, iclass 12, count 2 2006.257.07:47:35.80#ibcon#wrote, iclass 12, count 2 2006.257.07:47:35.80#ibcon#about to read 3, iclass 12, count 2 2006.257.07:47:35.83#ibcon#read 3, iclass 12, count 2 2006.257.07:47:35.83#ibcon#about to read 4, iclass 12, count 2 2006.257.07:47:35.83#ibcon#read 4, iclass 12, count 2 2006.257.07:47:35.83#ibcon#about to read 5, iclass 12, count 2 2006.257.07:47:35.83#ibcon#read 5, iclass 12, count 2 2006.257.07:47:35.83#ibcon#about to read 6, iclass 12, count 2 2006.257.07:47:35.83#ibcon#read 6, iclass 12, count 2 2006.257.07:47:35.83#ibcon#end of sib2, iclass 12, count 2 2006.257.07:47:35.83#ibcon#*after write, iclass 12, count 2 2006.257.07:47:35.83#ibcon#*before return 0, iclass 12, count 2 2006.257.07:47:35.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:35.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:35.83#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.07:47:35.83#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:35.83#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:35.95#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:35.95#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:35.95#ibcon#enter wrdev, iclass 12, count 0 2006.257.07:47:35.95#ibcon#first serial, iclass 12, count 0 2006.257.07:47:35.95#ibcon#enter sib2, iclass 12, count 0 2006.257.07:47:35.95#ibcon#flushed, iclass 12, count 0 2006.257.07:47:35.95#ibcon#about to write, iclass 12, count 0 2006.257.07:47:35.95#ibcon#wrote, iclass 12, count 0 2006.257.07:47:35.95#ibcon#about to read 3, iclass 12, count 0 2006.257.07:47:35.97#ibcon#read 3, iclass 12, count 0 2006.257.07:47:35.97#ibcon#about to read 4, iclass 12, count 0 2006.257.07:47:35.97#ibcon#read 4, iclass 12, count 0 2006.257.07:47:35.97#ibcon#about to read 5, iclass 12, count 0 2006.257.07:47:35.97#ibcon#read 5, iclass 12, count 0 2006.257.07:47:35.97#ibcon#about to read 6, iclass 12, count 0 2006.257.07:47:35.97#ibcon#read 6, iclass 12, count 0 2006.257.07:47:35.97#ibcon#end of sib2, iclass 12, count 0 2006.257.07:47:35.97#ibcon#*mode == 0, iclass 12, count 0 2006.257.07:47:35.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.07:47:35.97#ibcon#[25=USB\r\n] 2006.257.07:47:35.97#ibcon#*before write, iclass 12, count 0 2006.257.07:47:35.97#ibcon#enter sib2, iclass 12, count 0 2006.257.07:47:35.97#ibcon#flushed, iclass 12, count 0 2006.257.07:47:35.97#ibcon#about to write, iclass 12, count 0 2006.257.07:47:35.97#ibcon#wrote, iclass 12, count 0 2006.257.07:47:35.97#ibcon#about to read 3, iclass 12, count 0 2006.257.07:47:36.00#ibcon#read 3, iclass 12, count 0 2006.257.07:47:36.00#ibcon#about to read 4, iclass 12, count 0 2006.257.07:47:36.00#ibcon#read 4, iclass 12, count 0 2006.257.07:47:36.00#ibcon#about to read 5, iclass 12, count 0 2006.257.07:47:36.00#ibcon#read 5, iclass 12, count 0 2006.257.07:47:36.00#ibcon#about to read 6, iclass 12, count 0 2006.257.07:47:36.00#ibcon#read 6, iclass 12, count 0 2006.257.07:47:36.00#ibcon#end of sib2, iclass 12, count 0 2006.257.07:47:36.00#ibcon#*after write, iclass 12, count 0 2006.257.07:47:36.00#ibcon#*before return 0, iclass 12, count 0 2006.257.07:47:36.00#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:36.00#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:36.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.07:47:36.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.07:47:36.00$vck44/valo=3,564.99 2006.257.07:47:36.00#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.07:47:36.00#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.07:47:36.00#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:36.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:36.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:36.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:36.00#ibcon#enter wrdev, iclass 14, count 0 2006.257.07:47:36.00#ibcon#first serial, iclass 14, count 0 2006.257.07:47:36.00#ibcon#enter sib2, iclass 14, count 0 2006.257.07:47:36.00#ibcon#flushed, iclass 14, count 0 2006.257.07:47:36.00#ibcon#about to write, iclass 14, count 0 2006.257.07:47:36.00#ibcon#wrote, iclass 14, count 0 2006.257.07:47:36.00#ibcon#about to read 3, iclass 14, count 0 2006.257.07:47:36.02#ibcon#read 3, iclass 14, count 0 2006.257.07:47:36.02#ibcon#about to read 4, iclass 14, count 0 2006.257.07:47:36.02#ibcon#read 4, iclass 14, count 0 2006.257.07:47:36.02#ibcon#about to read 5, iclass 14, count 0 2006.257.07:47:36.02#ibcon#read 5, iclass 14, count 0 2006.257.07:47:36.02#ibcon#about to read 6, iclass 14, count 0 2006.257.07:47:36.02#ibcon#read 6, iclass 14, count 0 2006.257.07:47:36.02#ibcon#end of sib2, iclass 14, count 0 2006.257.07:47:36.02#ibcon#*mode == 0, iclass 14, count 0 2006.257.07:47:36.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.07:47:36.02#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.07:47:36.02#ibcon#*before write, iclass 14, count 0 2006.257.07:47:36.02#ibcon#enter sib2, iclass 14, count 0 2006.257.07:47:36.02#ibcon#flushed, iclass 14, count 0 2006.257.07:47:36.02#ibcon#about to write, iclass 14, count 0 2006.257.07:47:36.02#ibcon#wrote, iclass 14, count 0 2006.257.07:47:36.02#ibcon#about to read 3, iclass 14, count 0 2006.257.07:47:36.06#ibcon#read 3, iclass 14, count 0 2006.257.07:47:36.06#ibcon#about to read 4, iclass 14, count 0 2006.257.07:47:36.06#ibcon#read 4, iclass 14, count 0 2006.257.07:47:36.06#ibcon#about to read 5, iclass 14, count 0 2006.257.07:47:36.06#ibcon#read 5, iclass 14, count 0 2006.257.07:47:36.06#ibcon#about to read 6, iclass 14, count 0 2006.257.07:47:36.06#ibcon#read 6, iclass 14, count 0 2006.257.07:47:36.06#ibcon#end of sib2, iclass 14, count 0 2006.257.07:47:36.06#ibcon#*after write, iclass 14, count 0 2006.257.07:47:36.06#ibcon#*before return 0, iclass 14, count 0 2006.257.07:47:36.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:36.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:36.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.07:47:36.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.07:47:36.06$vck44/va=3,8 2006.257.07:47:36.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.07:47:36.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.07:47:36.06#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:36.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:36.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:36.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:36.12#ibcon#enter wrdev, iclass 16, count 2 2006.257.07:47:36.12#ibcon#first serial, iclass 16, count 2 2006.257.07:47:36.12#ibcon#enter sib2, iclass 16, count 2 2006.257.07:47:36.12#ibcon#flushed, iclass 16, count 2 2006.257.07:47:36.12#ibcon#about to write, iclass 16, count 2 2006.257.07:47:36.12#ibcon#wrote, iclass 16, count 2 2006.257.07:47:36.12#ibcon#about to read 3, iclass 16, count 2 2006.257.07:47:36.14#ibcon#read 3, iclass 16, count 2 2006.257.07:47:36.14#ibcon#about to read 4, iclass 16, count 2 2006.257.07:47:36.14#ibcon#read 4, iclass 16, count 2 2006.257.07:47:36.14#ibcon#about to read 5, iclass 16, count 2 2006.257.07:47:36.14#ibcon#read 5, iclass 16, count 2 2006.257.07:47:36.14#ibcon#about to read 6, iclass 16, count 2 2006.257.07:47:36.14#ibcon#read 6, iclass 16, count 2 2006.257.07:47:36.14#ibcon#end of sib2, iclass 16, count 2 2006.257.07:47:36.14#ibcon#*mode == 0, iclass 16, count 2 2006.257.07:47:36.14#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.07:47:36.14#ibcon#[25=AT03-08\r\n] 2006.257.07:47:36.14#ibcon#*before write, iclass 16, count 2 2006.257.07:47:36.14#ibcon#enter sib2, iclass 16, count 2 2006.257.07:47:36.14#ibcon#flushed, iclass 16, count 2 2006.257.07:47:36.14#ibcon#about to write, iclass 16, count 2 2006.257.07:47:36.14#ibcon#wrote, iclass 16, count 2 2006.257.07:47:36.14#ibcon#about to read 3, iclass 16, count 2 2006.257.07:47:36.17#ibcon#read 3, iclass 16, count 2 2006.257.07:47:36.17#ibcon#about to read 4, iclass 16, count 2 2006.257.07:47:36.17#ibcon#read 4, iclass 16, count 2 2006.257.07:47:36.17#ibcon#about to read 5, iclass 16, count 2 2006.257.07:47:36.17#ibcon#read 5, iclass 16, count 2 2006.257.07:47:36.17#ibcon#about to read 6, iclass 16, count 2 2006.257.07:47:36.17#ibcon#read 6, iclass 16, count 2 2006.257.07:47:36.17#ibcon#end of sib2, iclass 16, count 2 2006.257.07:47:36.17#ibcon#*after write, iclass 16, count 2 2006.257.07:47:36.17#ibcon#*before return 0, iclass 16, count 2 2006.257.07:47:36.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:36.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:36.17#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.07:47:36.17#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:36.17#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:36.29#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:36.29#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:36.29#ibcon#enter wrdev, iclass 16, count 0 2006.257.07:47:36.29#ibcon#first serial, iclass 16, count 0 2006.257.07:47:36.29#ibcon#enter sib2, iclass 16, count 0 2006.257.07:47:36.29#ibcon#flushed, iclass 16, count 0 2006.257.07:47:36.29#ibcon#about to write, iclass 16, count 0 2006.257.07:47:36.29#ibcon#wrote, iclass 16, count 0 2006.257.07:47:36.29#ibcon#about to read 3, iclass 16, count 0 2006.257.07:47:36.31#ibcon#read 3, iclass 16, count 0 2006.257.07:47:36.31#ibcon#about to read 4, iclass 16, count 0 2006.257.07:47:36.31#ibcon#read 4, iclass 16, count 0 2006.257.07:47:36.31#ibcon#about to read 5, iclass 16, count 0 2006.257.07:47:36.31#ibcon#read 5, iclass 16, count 0 2006.257.07:47:36.31#ibcon#about to read 6, iclass 16, count 0 2006.257.07:47:36.31#ibcon#read 6, iclass 16, count 0 2006.257.07:47:36.31#ibcon#end of sib2, iclass 16, count 0 2006.257.07:47:36.31#ibcon#*mode == 0, iclass 16, count 0 2006.257.07:47:36.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.07:47:36.31#ibcon#[25=USB\r\n] 2006.257.07:47:36.31#ibcon#*before write, iclass 16, count 0 2006.257.07:47:36.31#ibcon#enter sib2, iclass 16, count 0 2006.257.07:47:36.31#ibcon#flushed, iclass 16, count 0 2006.257.07:47:36.31#ibcon#about to write, iclass 16, count 0 2006.257.07:47:36.31#ibcon#wrote, iclass 16, count 0 2006.257.07:47:36.31#ibcon#about to read 3, iclass 16, count 0 2006.257.07:47:36.34#ibcon#read 3, iclass 16, count 0 2006.257.07:47:36.34#ibcon#about to read 4, iclass 16, count 0 2006.257.07:47:36.34#ibcon#read 4, iclass 16, count 0 2006.257.07:47:36.34#ibcon#about to read 5, iclass 16, count 0 2006.257.07:47:36.34#ibcon#read 5, iclass 16, count 0 2006.257.07:47:36.34#ibcon#about to read 6, iclass 16, count 0 2006.257.07:47:36.34#ibcon#read 6, iclass 16, count 0 2006.257.07:47:36.34#ibcon#end of sib2, iclass 16, count 0 2006.257.07:47:36.34#ibcon#*after write, iclass 16, count 0 2006.257.07:47:36.34#ibcon#*before return 0, iclass 16, count 0 2006.257.07:47:36.34#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:36.34#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:36.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.07:47:36.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.07:47:36.34$vck44/valo=4,624.99 2006.257.07:47:36.34#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.07:47:36.34#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.07:47:36.34#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:36.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:36.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:36.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:36.34#ibcon#enter wrdev, iclass 18, count 0 2006.257.07:47:36.34#ibcon#first serial, iclass 18, count 0 2006.257.07:47:36.34#ibcon#enter sib2, iclass 18, count 0 2006.257.07:47:36.34#ibcon#flushed, iclass 18, count 0 2006.257.07:47:36.34#ibcon#about to write, iclass 18, count 0 2006.257.07:47:36.34#ibcon#wrote, iclass 18, count 0 2006.257.07:47:36.34#ibcon#about to read 3, iclass 18, count 0 2006.257.07:47:36.36#ibcon#read 3, iclass 18, count 0 2006.257.07:47:36.36#ibcon#about to read 4, iclass 18, count 0 2006.257.07:47:36.36#ibcon#read 4, iclass 18, count 0 2006.257.07:47:36.36#ibcon#about to read 5, iclass 18, count 0 2006.257.07:47:36.36#ibcon#read 5, iclass 18, count 0 2006.257.07:47:36.36#ibcon#about to read 6, iclass 18, count 0 2006.257.07:47:36.36#ibcon#read 6, iclass 18, count 0 2006.257.07:47:36.36#ibcon#end of sib2, iclass 18, count 0 2006.257.07:47:36.36#ibcon#*mode == 0, iclass 18, count 0 2006.257.07:47:36.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.07:47:36.36#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.07:47:36.36#ibcon#*before write, iclass 18, count 0 2006.257.07:47:36.36#ibcon#enter sib2, iclass 18, count 0 2006.257.07:47:36.36#ibcon#flushed, iclass 18, count 0 2006.257.07:47:36.36#ibcon#about to write, iclass 18, count 0 2006.257.07:47:36.36#ibcon#wrote, iclass 18, count 0 2006.257.07:47:36.36#ibcon#about to read 3, iclass 18, count 0 2006.257.07:47:36.40#ibcon#read 3, iclass 18, count 0 2006.257.07:47:36.40#ibcon#about to read 4, iclass 18, count 0 2006.257.07:47:36.40#ibcon#read 4, iclass 18, count 0 2006.257.07:47:36.40#ibcon#about to read 5, iclass 18, count 0 2006.257.07:47:36.40#ibcon#read 5, iclass 18, count 0 2006.257.07:47:36.40#ibcon#about to read 6, iclass 18, count 0 2006.257.07:47:36.40#ibcon#read 6, iclass 18, count 0 2006.257.07:47:36.40#ibcon#end of sib2, iclass 18, count 0 2006.257.07:47:36.40#ibcon#*after write, iclass 18, count 0 2006.257.07:47:36.40#ibcon#*before return 0, iclass 18, count 0 2006.257.07:47:36.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:36.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:36.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.07:47:36.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.07:47:36.40$vck44/va=4,7 2006.257.07:47:36.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.07:47:36.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.07:47:36.40#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:36.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:36.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:36.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:36.46#ibcon#enter wrdev, iclass 20, count 2 2006.257.07:47:36.46#ibcon#first serial, iclass 20, count 2 2006.257.07:47:36.46#ibcon#enter sib2, iclass 20, count 2 2006.257.07:47:36.46#ibcon#flushed, iclass 20, count 2 2006.257.07:47:36.46#ibcon#about to write, iclass 20, count 2 2006.257.07:47:36.46#ibcon#wrote, iclass 20, count 2 2006.257.07:47:36.46#ibcon#about to read 3, iclass 20, count 2 2006.257.07:47:36.48#ibcon#read 3, iclass 20, count 2 2006.257.07:47:36.48#ibcon#about to read 4, iclass 20, count 2 2006.257.07:47:36.48#ibcon#read 4, iclass 20, count 2 2006.257.07:47:36.48#ibcon#about to read 5, iclass 20, count 2 2006.257.07:47:36.48#ibcon#read 5, iclass 20, count 2 2006.257.07:47:36.48#ibcon#about to read 6, iclass 20, count 2 2006.257.07:47:36.48#ibcon#read 6, iclass 20, count 2 2006.257.07:47:36.48#ibcon#end of sib2, iclass 20, count 2 2006.257.07:47:36.48#ibcon#*mode == 0, iclass 20, count 2 2006.257.07:47:36.48#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.07:47:36.48#ibcon#[25=AT04-07\r\n] 2006.257.07:47:36.48#ibcon#*before write, iclass 20, count 2 2006.257.07:47:36.48#ibcon#enter sib2, iclass 20, count 2 2006.257.07:47:36.48#ibcon#flushed, iclass 20, count 2 2006.257.07:47:36.48#ibcon#about to write, iclass 20, count 2 2006.257.07:47:36.48#ibcon#wrote, iclass 20, count 2 2006.257.07:47:36.48#ibcon#about to read 3, iclass 20, count 2 2006.257.07:47:36.51#ibcon#read 3, iclass 20, count 2 2006.257.07:47:36.51#ibcon#about to read 4, iclass 20, count 2 2006.257.07:47:36.51#ibcon#read 4, iclass 20, count 2 2006.257.07:47:36.51#ibcon#about to read 5, iclass 20, count 2 2006.257.07:47:36.51#ibcon#read 5, iclass 20, count 2 2006.257.07:47:36.51#ibcon#about to read 6, iclass 20, count 2 2006.257.07:47:36.51#ibcon#read 6, iclass 20, count 2 2006.257.07:47:36.51#ibcon#end of sib2, iclass 20, count 2 2006.257.07:47:36.51#ibcon#*after write, iclass 20, count 2 2006.257.07:47:36.51#ibcon#*before return 0, iclass 20, count 2 2006.257.07:47:36.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:36.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:36.51#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.07:47:36.51#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:36.51#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:36.63#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:36.63#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:36.63#ibcon#enter wrdev, iclass 20, count 0 2006.257.07:47:36.63#ibcon#first serial, iclass 20, count 0 2006.257.07:47:36.63#ibcon#enter sib2, iclass 20, count 0 2006.257.07:47:36.63#ibcon#flushed, iclass 20, count 0 2006.257.07:47:36.63#ibcon#about to write, iclass 20, count 0 2006.257.07:47:36.63#ibcon#wrote, iclass 20, count 0 2006.257.07:47:36.63#ibcon#about to read 3, iclass 20, count 0 2006.257.07:47:36.65#ibcon#read 3, iclass 20, count 0 2006.257.07:47:36.65#ibcon#about to read 4, iclass 20, count 0 2006.257.07:47:36.65#ibcon#read 4, iclass 20, count 0 2006.257.07:47:36.65#ibcon#about to read 5, iclass 20, count 0 2006.257.07:47:36.65#ibcon#read 5, iclass 20, count 0 2006.257.07:47:36.65#ibcon#about to read 6, iclass 20, count 0 2006.257.07:47:36.65#ibcon#read 6, iclass 20, count 0 2006.257.07:47:36.65#ibcon#end of sib2, iclass 20, count 0 2006.257.07:47:36.65#ibcon#*mode == 0, iclass 20, count 0 2006.257.07:47:36.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.07:47:36.65#ibcon#[25=USB\r\n] 2006.257.07:47:36.65#ibcon#*before write, iclass 20, count 0 2006.257.07:47:36.65#ibcon#enter sib2, iclass 20, count 0 2006.257.07:47:36.65#ibcon#flushed, iclass 20, count 0 2006.257.07:47:36.65#ibcon#about to write, iclass 20, count 0 2006.257.07:47:36.65#ibcon#wrote, iclass 20, count 0 2006.257.07:47:36.65#ibcon#about to read 3, iclass 20, count 0 2006.257.07:47:36.68#ibcon#read 3, iclass 20, count 0 2006.257.07:47:36.68#ibcon#about to read 4, iclass 20, count 0 2006.257.07:47:36.68#ibcon#read 4, iclass 20, count 0 2006.257.07:47:36.68#ibcon#about to read 5, iclass 20, count 0 2006.257.07:47:36.68#ibcon#read 5, iclass 20, count 0 2006.257.07:47:36.68#ibcon#about to read 6, iclass 20, count 0 2006.257.07:47:36.68#ibcon#read 6, iclass 20, count 0 2006.257.07:47:36.68#ibcon#end of sib2, iclass 20, count 0 2006.257.07:47:36.68#ibcon#*after write, iclass 20, count 0 2006.257.07:47:36.68#ibcon#*before return 0, iclass 20, count 0 2006.257.07:47:36.68#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:36.68#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:36.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.07:47:36.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.07:47:36.68$vck44/valo=5,734.99 2006.257.07:47:36.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.07:47:36.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.07:47:36.68#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:36.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:36.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:36.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:36.68#ibcon#enter wrdev, iclass 22, count 0 2006.257.07:47:36.68#ibcon#first serial, iclass 22, count 0 2006.257.07:47:36.68#ibcon#enter sib2, iclass 22, count 0 2006.257.07:47:36.68#ibcon#flushed, iclass 22, count 0 2006.257.07:47:36.68#ibcon#about to write, iclass 22, count 0 2006.257.07:47:36.68#ibcon#wrote, iclass 22, count 0 2006.257.07:47:36.68#ibcon#about to read 3, iclass 22, count 0 2006.257.07:47:36.70#ibcon#read 3, iclass 22, count 0 2006.257.07:47:36.70#ibcon#about to read 4, iclass 22, count 0 2006.257.07:47:36.70#ibcon#read 4, iclass 22, count 0 2006.257.07:47:36.70#ibcon#about to read 5, iclass 22, count 0 2006.257.07:47:36.70#ibcon#read 5, iclass 22, count 0 2006.257.07:47:36.70#ibcon#about to read 6, iclass 22, count 0 2006.257.07:47:36.70#ibcon#read 6, iclass 22, count 0 2006.257.07:47:36.70#ibcon#end of sib2, iclass 22, count 0 2006.257.07:47:36.70#ibcon#*mode == 0, iclass 22, count 0 2006.257.07:47:36.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.07:47:36.70#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.07:47:36.70#ibcon#*before write, iclass 22, count 0 2006.257.07:47:36.70#ibcon#enter sib2, iclass 22, count 0 2006.257.07:47:36.70#ibcon#flushed, iclass 22, count 0 2006.257.07:47:36.70#ibcon#about to write, iclass 22, count 0 2006.257.07:47:36.70#ibcon#wrote, iclass 22, count 0 2006.257.07:47:36.70#ibcon#about to read 3, iclass 22, count 0 2006.257.07:47:36.74#ibcon#read 3, iclass 22, count 0 2006.257.07:47:36.74#ibcon#about to read 4, iclass 22, count 0 2006.257.07:47:36.74#ibcon#read 4, iclass 22, count 0 2006.257.07:47:36.74#ibcon#about to read 5, iclass 22, count 0 2006.257.07:47:36.74#ibcon#read 5, iclass 22, count 0 2006.257.07:47:36.74#ibcon#about to read 6, iclass 22, count 0 2006.257.07:47:36.74#ibcon#read 6, iclass 22, count 0 2006.257.07:47:36.74#ibcon#end of sib2, iclass 22, count 0 2006.257.07:47:36.74#ibcon#*after write, iclass 22, count 0 2006.257.07:47:36.74#ibcon#*before return 0, iclass 22, count 0 2006.257.07:47:36.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:36.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:36.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.07:47:36.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.07:47:36.74$vck44/va=5,4 2006.257.07:47:36.74#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.07:47:36.74#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.07:47:36.74#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:36.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:36.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:36.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:36.80#ibcon#enter wrdev, iclass 24, count 2 2006.257.07:47:36.80#ibcon#first serial, iclass 24, count 2 2006.257.07:47:36.80#ibcon#enter sib2, iclass 24, count 2 2006.257.07:47:36.80#ibcon#flushed, iclass 24, count 2 2006.257.07:47:36.80#ibcon#about to write, iclass 24, count 2 2006.257.07:47:36.80#ibcon#wrote, iclass 24, count 2 2006.257.07:47:36.80#ibcon#about to read 3, iclass 24, count 2 2006.257.07:47:36.82#ibcon#read 3, iclass 24, count 2 2006.257.07:47:36.82#ibcon#about to read 4, iclass 24, count 2 2006.257.07:47:36.82#ibcon#read 4, iclass 24, count 2 2006.257.07:47:36.82#ibcon#about to read 5, iclass 24, count 2 2006.257.07:47:36.82#ibcon#read 5, iclass 24, count 2 2006.257.07:47:36.82#ibcon#about to read 6, iclass 24, count 2 2006.257.07:47:36.82#ibcon#read 6, iclass 24, count 2 2006.257.07:47:36.82#ibcon#end of sib2, iclass 24, count 2 2006.257.07:47:36.82#ibcon#*mode == 0, iclass 24, count 2 2006.257.07:47:36.82#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.07:47:36.82#ibcon#[25=AT05-04\r\n] 2006.257.07:47:36.82#ibcon#*before write, iclass 24, count 2 2006.257.07:47:36.82#ibcon#enter sib2, iclass 24, count 2 2006.257.07:47:36.82#ibcon#flushed, iclass 24, count 2 2006.257.07:47:36.82#ibcon#about to write, iclass 24, count 2 2006.257.07:47:36.82#ibcon#wrote, iclass 24, count 2 2006.257.07:47:36.82#ibcon#about to read 3, iclass 24, count 2 2006.257.07:47:36.85#ibcon#read 3, iclass 24, count 2 2006.257.07:47:36.85#ibcon#about to read 4, iclass 24, count 2 2006.257.07:47:36.85#ibcon#read 4, iclass 24, count 2 2006.257.07:47:36.85#ibcon#about to read 5, iclass 24, count 2 2006.257.07:47:36.85#ibcon#read 5, iclass 24, count 2 2006.257.07:47:36.85#ibcon#about to read 6, iclass 24, count 2 2006.257.07:47:36.85#ibcon#read 6, iclass 24, count 2 2006.257.07:47:36.85#ibcon#end of sib2, iclass 24, count 2 2006.257.07:47:36.85#ibcon#*after write, iclass 24, count 2 2006.257.07:47:36.85#ibcon#*before return 0, iclass 24, count 2 2006.257.07:47:36.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:36.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:36.85#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.07:47:36.85#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:36.85#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:36.97#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:36.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:36.97#ibcon#enter wrdev, iclass 24, count 0 2006.257.07:47:36.97#ibcon#first serial, iclass 24, count 0 2006.257.07:47:36.97#ibcon#enter sib2, iclass 24, count 0 2006.257.07:47:36.97#ibcon#flushed, iclass 24, count 0 2006.257.07:47:36.97#ibcon#about to write, iclass 24, count 0 2006.257.07:47:36.97#ibcon#wrote, iclass 24, count 0 2006.257.07:47:36.97#ibcon#about to read 3, iclass 24, count 0 2006.257.07:47:36.99#ibcon#read 3, iclass 24, count 0 2006.257.07:47:36.99#ibcon#about to read 4, iclass 24, count 0 2006.257.07:47:36.99#ibcon#read 4, iclass 24, count 0 2006.257.07:47:36.99#ibcon#about to read 5, iclass 24, count 0 2006.257.07:47:36.99#ibcon#read 5, iclass 24, count 0 2006.257.07:47:36.99#ibcon#about to read 6, iclass 24, count 0 2006.257.07:47:36.99#ibcon#read 6, iclass 24, count 0 2006.257.07:47:36.99#ibcon#end of sib2, iclass 24, count 0 2006.257.07:47:36.99#ibcon#*mode == 0, iclass 24, count 0 2006.257.07:47:36.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.07:47:36.99#ibcon#[25=USB\r\n] 2006.257.07:47:36.99#ibcon#*before write, iclass 24, count 0 2006.257.07:47:36.99#ibcon#enter sib2, iclass 24, count 0 2006.257.07:47:36.99#ibcon#flushed, iclass 24, count 0 2006.257.07:47:36.99#ibcon#about to write, iclass 24, count 0 2006.257.07:47:36.99#ibcon#wrote, iclass 24, count 0 2006.257.07:47:36.99#ibcon#about to read 3, iclass 24, count 0 2006.257.07:47:37.02#ibcon#read 3, iclass 24, count 0 2006.257.07:47:37.02#ibcon#about to read 4, iclass 24, count 0 2006.257.07:47:37.02#ibcon#read 4, iclass 24, count 0 2006.257.07:47:37.02#ibcon#about to read 5, iclass 24, count 0 2006.257.07:47:37.02#ibcon#read 5, iclass 24, count 0 2006.257.07:47:37.02#ibcon#about to read 6, iclass 24, count 0 2006.257.07:47:37.02#ibcon#read 6, iclass 24, count 0 2006.257.07:47:37.02#ibcon#end of sib2, iclass 24, count 0 2006.257.07:47:37.02#ibcon#*after write, iclass 24, count 0 2006.257.07:47:37.02#ibcon#*before return 0, iclass 24, count 0 2006.257.07:47:37.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:37.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:37.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.07:47:37.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.07:47:37.02$vck44/valo=6,814.99 2006.257.07:47:37.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.07:47:37.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.07:47:37.02#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:37.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:37.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:37.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:37.02#ibcon#enter wrdev, iclass 26, count 0 2006.257.07:47:37.02#ibcon#first serial, iclass 26, count 0 2006.257.07:47:37.02#ibcon#enter sib2, iclass 26, count 0 2006.257.07:47:37.02#ibcon#flushed, iclass 26, count 0 2006.257.07:47:37.02#ibcon#about to write, iclass 26, count 0 2006.257.07:47:37.02#ibcon#wrote, iclass 26, count 0 2006.257.07:47:37.02#ibcon#about to read 3, iclass 26, count 0 2006.257.07:47:37.04#ibcon#read 3, iclass 26, count 0 2006.257.07:47:37.04#ibcon#about to read 4, iclass 26, count 0 2006.257.07:47:37.04#ibcon#read 4, iclass 26, count 0 2006.257.07:47:37.04#ibcon#about to read 5, iclass 26, count 0 2006.257.07:47:37.04#ibcon#read 5, iclass 26, count 0 2006.257.07:47:37.04#ibcon#about to read 6, iclass 26, count 0 2006.257.07:47:37.04#ibcon#read 6, iclass 26, count 0 2006.257.07:47:37.04#ibcon#end of sib2, iclass 26, count 0 2006.257.07:47:37.04#ibcon#*mode == 0, iclass 26, count 0 2006.257.07:47:37.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.07:47:37.04#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.07:47:37.04#ibcon#*before write, iclass 26, count 0 2006.257.07:47:37.04#ibcon#enter sib2, iclass 26, count 0 2006.257.07:47:37.04#ibcon#flushed, iclass 26, count 0 2006.257.07:47:37.04#ibcon#about to write, iclass 26, count 0 2006.257.07:47:37.04#ibcon#wrote, iclass 26, count 0 2006.257.07:47:37.04#ibcon#about to read 3, iclass 26, count 0 2006.257.07:47:37.08#ibcon#read 3, iclass 26, count 0 2006.257.07:47:37.08#ibcon#about to read 4, iclass 26, count 0 2006.257.07:47:37.08#ibcon#read 4, iclass 26, count 0 2006.257.07:47:37.08#ibcon#about to read 5, iclass 26, count 0 2006.257.07:47:37.08#ibcon#read 5, iclass 26, count 0 2006.257.07:47:37.08#ibcon#about to read 6, iclass 26, count 0 2006.257.07:47:37.08#ibcon#read 6, iclass 26, count 0 2006.257.07:47:37.08#ibcon#end of sib2, iclass 26, count 0 2006.257.07:47:37.08#ibcon#*after write, iclass 26, count 0 2006.257.07:47:37.08#ibcon#*before return 0, iclass 26, count 0 2006.257.07:47:37.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:37.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:37.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.07:47:37.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.07:47:37.08$vck44/va=6,4 2006.257.07:47:37.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.07:47:37.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.07:47:37.08#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:37.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:37.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:37.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:37.14#ibcon#enter wrdev, iclass 28, count 2 2006.257.07:47:37.14#ibcon#first serial, iclass 28, count 2 2006.257.07:47:37.14#ibcon#enter sib2, iclass 28, count 2 2006.257.07:47:37.14#ibcon#flushed, iclass 28, count 2 2006.257.07:47:37.14#ibcon#about to write, iclass 28, count 2 2006.257.07:47:37.14#ibcon#wrote, iclass 28, count 2 2006.257.07:47:37.14#ibcon#about to read 3, iclass 28, count 2 2006.257.07:47:37.16#ibcon#read 3, iclass 28, count 2 2006.257.07:47:37.16#ibcon#about to read 4, iclass 28, count 2 2006.257.07:47:37.16#ibcon#read 4, iclass 28, count 2 2006.257.07:47:37.16#ibcon#about to read 5, iclass 28, count 2 2006.257.07:47:37.16#ibcon#read 5, iclass 28, count 2 2006.257.07:47:37.16#ibcon#about to read 6, iclass 28, count 2 2006.257.07:47:37.16#ibcon#read 6, iclass 28, count 2 2006.257.07:47:37.16#ibcon#end of sib2, iclass 28, count 2 2006.257.07:47:37.16#ibcon#*mode == 0, iclass 28, count 2 2006.257.07:47:37.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.07:47:37.16#ibcon#[25=AT06-04\r\n] 2006.257.07:47:37.16#ibcon#*before write, iclass 28, count 2 2006.257.07:47:37.16#ibcon#enter sib2, iclass 28, count 2 2006.257.07:47:37.16#ibcon#flushed, iclass 28, count 2 2006.257.07:47:37.16#ibcon#about to write, iclass 28, count 2 2006.257.07:47:37.16#ibcon#wrote, iclass 28, count 2 2006.257.07:47:37.16#ibcon#about to read 3, iclass 28, count 2 2006.257.07:47:37.19#ibcon#read 3, iclass 28, count 2 2006.257.07:47:37.19#ibcon#about to read 4, iclass 28, count 2 2006.257.07:47:37.19#ibcon#read 4, iclass 28, count 2 2006.257.07:47:37.19#ibcon#about to read 5, iclass 28, count 2 2006.257.07:47:37.19#ibcon#read 5, iclass 28, count 2 2006.257.07:47:37.19#ibcon#about to read 6, iclass 28, count 2 2006.257.07:47:37.19#ibcon#read 6, iclass 28, count 2 2006.257.07:47:37.19#ibcon#end of sib2, iclass 28, count 2 2006.257.07:47:37.19#ibcon#*after write, iclass 28, count 2 2006.257.07:47:37.19#ibcon#*before return 0, iclass 28, count 2 2006.257.07:47:37.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:37.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:37.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.07:47:37.19#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:37.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:37.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:37.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:37.31#ibcon#enter wrdev, iclass 28, count 0 2006.257.07:47:37.31#ibcon#first serial, iclass 28, count 0 2006.257.07:47:37.31#ibcon#enter sib2, iclass 28, count 0 2006.257.07:47:37.31#ibcon#flushed, iclass 28, count 0 2006.257.07:47:37.31#ibcon#about to write, iclass 28, count 0 2006.257.07:47:37.31#ibcon#wrote, iclass 28, count 0 2006.257.07:47:37.31#ibcon#about to read 3, iclass 28, count 0 2006.257.07:47:37.33#ibcon#read 3, iclass 28, count 0 2006.257.07:47:37.33#ibcon#about to read 4, iclass 28, count 0 2006.257.07:47:37.33#ibcon#read 4, iclass 28, count 0 2006.257.07:47:37.33#ibcon#about to read 5, iclass 28, count 0 2006.257.07:47:37.33#ibcon#read 5, iclass 28, count 0 2006.257.07:47:37.33#ibcon#about to read 6, iclass 28, count 0 2006.257.07:47:37.33#ibcon#read 6, iclass 28, count 0 2006.257.07:47:37.33#ibcon#end of sib2, iclass 28, count 0 2006.257.07:47:37.33#ibcon#*mode == 0, iclass 28, count 0 2006.257.07:47:37.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.07:47:37.33#ibcon#[25=USB\r\n] 2006.257.07:47:37.33#ibcon#*before write, iclass 28, count 0 2006.257.07:47:37.33#ibcon#enter sib2, iclass 28, count 0 2006.257.07:47:37.33#ibcon#flushed, iclass 28, count 0 2006.257.07:47:37.33#ibcon#about to write, iclass 28, count 0 2006.257.07:47:37.33#ibcon#wrote, iclass 28, count 0 2006.257.07:47:37.33#ibcon#about to read 3, iclass 28, count 0 2006.257.07:47:37.36#ibcon#read 3, iclass 28, count 0 2006.257.07:47:37.36#ibcon#about to read 4, iclass 28, count 0 2006.257.07:47:37.36#ibcon#read 4, iclass 28, count 0 2006.257.07:47:37.36#ibcon#about to read 5, iclass 28, count 0 2006.257.07:47:37.36#ibcon#read 5, iclass 28, count 0 2006.257.07:47:37.36#ibcon#about to read 6, iclass 28, count 0 2006.257.07:47:37.36#ibcon#read 6, iclass 28, count 0 2006.257.07:47:37.36#ibcon#end of sib2, iclass 28, count 0 2006.257.07:47:37.36#ibcon#*after write, iclass 28, count 0 2006.257.07:47:37.36#ibcon#*before return 0, iclass 28, count 0 2006.257.07:47:37.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:37.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:37.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.07:47:37.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.07:47:37.36$vck44/valo=7,864.99 2006.257.07:47:37.36#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.07:47:37.36#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.07:47:37.36#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:37.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:37.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:37.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:37.36#ibcon#enter wrdev, iclass 30, count 0 2006.257.07:47:37.36#ibcon#first serial, iclass 30, count 0 2006.257.07:47:37.36#ibcon#enter sib2, iclass 30, count 0 2006.257.07:47:37.36#ibcon#flushed, iclass 30, count 0 2006.257.07:47:37.36#ibcon#about to write, iclass 30, count 0 2006.257.07:47:37.36#ibcon#wrote, iclass 30, count 0 2006.257.07:47:37.36#ibcon#about to read 3, iclass 30, count 0 2006.257.07:47:37.38#ibcon#read 3, iclass 30, count 0 2006.257.07:47:37.38#ibcon#about to read 4, iclass 30, count 0 2006.257.07:47:37.38#ibcon#read 4, iclass 30, count 0 2006.257.07:47:37.38#ibcon#about to read 5, iclass 30, count 0 2006.257.07:47:37.38#ibcon#read 5, iclass 30, count 0 2006.257.07:47:37.38#ibcon#about to read 6, iclass 30, count 0 2006.257.07:47:37.38#ibcon#read 6, iclass 30, count 0 2006.257.07:47:37.38#ibcon#end of sib2, iclass 30, count 0 2006.257.07:47:37.38#ibcon#*mode == 0, iclass 30, count 0 2006.257.07:47:37.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.07:47:37.38#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.07:47:37.38#ibcon#*before write, iclass 30, count 0 2006.257.07:47:37.38#ibcon#enter sib2, iclass 30, count 0 2006.257.07:47:37.38#ibcon#flushed, iclass 30, count 0 2006.257.07:47:37.38#ibcon#about to write, iclass 30, count 0 2006.257.07:47:37.38#ibcon#wrote, iclass 30, count 0 2006.257.07:47:37.38#ibcon#about to read 3, iclass 30, count 0 2006.257.07:47:37.42#ibcon#read 3, iclass 30, count 0 2006.257.07:47:37.42#ibcon#about to read 4, iclass 30, count 0 2006.257.07:47:37.42#ibcon#read 4, iclass 30, count 0 2006.257.07:47:37.42#ibcon#about to read 5, iclass 30, count 0 2006.257.07:47:37.42#ibcon#read 5, iclass 30, count 0 2006.257.07:47:37.42#ibcon#about to read 6, iclass 30, count 0 2006.257.07:47:37.42#ibcon#read 6, iclass 30, count 0 2006.257.07:47:37.42#ibcon#end of sib2, iclass 30, count 0 2006.257.07:47:37.42#ibcon#*after write, iclass 30, count 0 2006.257.07:47:37.42#ibcon#*before return 0, iclass 30, count 0 2006.257.07:47:37.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:37.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:37.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.07:47:37.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.07:47:37.42$vck44/va=7,4 2006.257.07:47:37.42#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.07:47:37.42#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.07:47:37.42#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:37.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:37.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:37.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:37.48#ibcon#enter wrdev, iclass 32, count 2 2006.257.07:47:37.48#ibcon#first serial, iclass 32, count 2 2006.257.07:47:37.48#ibcon#enter sib2, iclass 32, count 2 2006.257.07:47:37.48#ibcon#flushed, iclass 32, count 2 2006.257.07:47:37.48#ibcon#about to write, iclass 32, count 2 2006.257.07:47:37.48#ibcon#wrote, iclass 32, count 2 2006.257.07:47:37.48#ibcon#about to read 3, iclass 32, count 2 2006.257.07:47:37.50#ibcon#read 3, iclass 32, count 2 2006.257.07:47:37.50#ibcon#about to read 4, iclass 32, count 2 2006.257.07:47:37.50#ibcon#read 4, iclass 32, count 2 2006.257.07:47:37.50#ibcon#about to read 5, iclass 32, count 2 2006.257.07:47:37.50#ibcon#read 5, iclass 32, count 2 2006.257.07:47:37.50#ibcon#about to read 6, iclass 32, count 2 2006.257.07:47:37.50#ibcon#read 6, iclass 32, count 2 2006.257.07:47:37.50#ibcon#end of sib2, iclass 32, count 2 2006.257.07:47:37.50#ibcon#*mode == 0, iclass 32, count 2 2006.257.07:47:37.50#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.07:47:37.50#ibcon#[25=AT07-04\r\n] 2006.257.07:47:37.50#ibcon#*before write, iclass 32, count 2 2006.257.07:47:37.50#ibcon#enter sib2, iclass 32, count 2 2006.257.07:47:37.50#ibcon#flushed, iclass 32, count 2 2006.257.07:47:37.50#ibcon#about to write, iclass 32, count 2 2006.257.07:47:37.50#ibcon#wrote, iclass 32, count 2 2006.257.07:47:37.50#ibcon#about to read 3, iclass 32, count 2 2006.257.07:47:37.53#ibcon#read 3, iclass 32, count 2 2006.257.07:47:37.53#ibcon#about to read 4, iclass 32, count 2 2006.257.07:47:37.53#ibcon#read 4, iclass 32, count 2 2006.257.07:47:37.53#ibcon#about to read 5, iclass 32, count 2 2006.257.07:47:37.53#ibcon#read 5, iclass 32, count 2 2006.257.07:47:37.53#ibcon#about to read 6, iclass 32, count 2 2006.257.07:47:37.53#ibcon#read 6, iclass 32, count 2 2006.257.07:47:37.53#ibcon#end of sib2, iclass 32, count 2 2006.257.07:47:37.53#ibcon#*after write, iclass 32, count 2 2006.257.07:47:37.53#ibcon#*before return 0, iclass 32, count 2 2006.257.07:47:37.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:37.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:37.53#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.07:47:37.53#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:37.53#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:37.65#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:37.65#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:37.65#ibcon#enter wrdev, iclass 32, count 0 2006.257.07:47:37.65#ibcon#first serial, iclass 32, count 0 2006.257.07:47:37.65#ibcon#enter sib2, iclass 32, count 0 2006.257.07:47:37.65#ibcon#flushed, iclass 32, count 0 2006.257.07:47:37.65#ibcon#about to write, iclass 32, count 0 2006.257.07:47:37.65#ibcon#wrote, iclass 32, count 0 2006.257.07:47:37.65#ibcon#about to read 3, iclass 32, count 0 2006.257.07:47:37.67#ibcon#read 3, iclass 32, count 0 2006.257.07:47:37.67#ibcon#about to read 4, iclass 32, count 0 2006.257.07:47:37.67#ibcon#read 4, iclass 32, count 0 2006.257.07:47:37.67#ibcon#about to read 5, iclass 32, count 0 2006.257.07:47:37.67#ibcon#read 5, iclass 32, count 0 2006.257.07:47:37.67#ibcon#about to read 6, iclass 32, count 0 2006.257.07:47:37.67#ibcon#read 6, iclass 32, count 0 2006.257.07:47:37.67#ibcon#end of sib2, iclass 32, count 0 2006.257.07:47:37.67#ibcon#*mode == 0, iclass 32, count 0 2006.257.07:47:37.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.07:47:37.67#ibcon#[25=USB\r\n] 2006.257.07:47:37.67#ibcon#*before write, iclass 32, count 0 2006.257.07:47:37.67#ibcon#enter sib2, iclass 32, count 0 2006.257.07:47:37.67#ibcon#flushed, iclass 32, count 0 2006.257.07:47:37.67#ibcon#about to write, iclass 32, count 0 2006.257.07:47:37.67#ibcon#wrote, iclass 32, count 0 2006.257.07:47:37.67#ibcon#about to read 3, iclass 32, count 0 2006.257.07:47:37.70#ibcon#read 3, iclass 32, count 0 2006.257.07:47:37.70#ibcon#about to read 4, iclass 32, count 0 2006.257.07:47:37.70#ibcon#read 4, iclass 32, count 0 2006.257.07:47:37.70#ibcon#about to read 5, iclass 32, count 0 2006.257.07:47:37.70#ibcon#read 5, iclass 32, count 0 2006.257.07:47:37.70#ibcon#about to read 6, iclass 32, count 0 2006.257.07:47:37.70#ibcon#read 6, iclass 32, count 0 2006.257.07:47:37.70#ibcon#end of sib2, iclass 32, count 0 2006.257.07:47:37.70#ibcon#*after write, iclass 32, count 0 2006.257.07:47:37.70#ibcon#*before return 0, iclass 32, count 0 2006.257.07:47:37.70#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:37.70#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:37.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.07:47:37.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.07:47:37.70$vck44/valo=8,884.99 2006.257.07:47:37.70#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.07:47:37.70#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.07:47:37.70#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:37.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:37.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:37.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:37.70#ibcon#enter wrdev, iclass 34, count 0 2006.257.07:47:37.70#ibcon#first serial, iclass 34, count 0 2006.257.07:47:37.70#ibcon#enter sib2, iclass 34, count 0 2006.257.07:47:37.70#ibcon#flushed, iclass 34, count 0 2006.257.07:47:37.70#ibcon#about to write, iclass 34, count 0 2006.257.07:47:37.70#ibcon#wrote, iclass 34, count 0 2006.257.07:47:37.70#ibcon#about to read 3, iclass 34, count 0 2006.257.07:47:37.72#ibcon#read 3, iclass 34, count 0 2006.257.07:47:37.72#ibcon#about to read 4, iclass 34, count 0 2006.257.07:47:37.72#ibcon#read 4, iclass 34, count 0 2006.257.07:47:37.72#ibcon#about to read 5, iclass 34, count 0 2006.257.07:47:37.72#ibcon#read 5, iclass 34, count 0 2006.257.07:47:37.72#ibcon#about to read 6, iclass 34, count 0 2006.257.07:47:37.72#ibcon#read 6, iclass 34, count 0 2006.257.07:47:37.72#ibcon#end of sib2, iclass 34, count 0 2006.257.07:47:37.72#ibcon#*mode == 0, iclass 34, count 0 2006.257.07:47:37.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.07:47:37.72#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.07:47:37.72#ibcon#*before write, iclass 34, count 0 2006.257.07:47:37.72#ibcon#enter sib2, iclass 34, count 0 2006.257.07:47:37.72#ibcon#flushed, iclass 34, count 0 2006.257.07:47:37.72#ibcon#about to write, iclass 34, count 0 2006.257.07:47:37.72#ibcon#wrote, iclass 34, count 0 2006.257.07:47:37.72#ibcon#about to read 3, iclass 34, count 0 2006.257.07:47:37.76#ibcon#read 3, iclass 34, count 0 2006.257.07:47:37.76#ibcon#about to read 4, iclass 34, count 0 2006.257.07:47:37.76#ibcon#read 4, iclass 34, count 0 2006.257.07:47:37.76#ibcon#about to read 5, iclass 34, count 0 2006.257.07:47:37.76#ibcon#read 5, iclass 34, count 0 2006.257.07:47:37.76#ibcon#about to read 6, iclass 34, count 0 2006.257.07:47:37.76#ibcon#read 6, iclass 34, count 0 2006.257.07:47:37.76#ibcon#end of sib2, iclass 34, count 0 2006.257.07:47:37.76#ibcon#*after write, iclass 34, count 0 2006.257.07:47:37.76#ibcon#*before return 0, iclass 34, count 0 2006.257.07:47:37.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:37.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:37.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.07:47:37.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.07:47:37.76$vck44/va=8,4 2006.257.07:47:37.76#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.07:47:37.76#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.07:47:37.76#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:37.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:47:37.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:47:37.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:47:37.82#ibcon#enter wrdev, iclass 36, count 2 2006.257.07:47:37.82#ibcon#first serial, iclass 36, count 2 2006.257.07:47:37.82#ibcon#enter sib2, iclass 36, count 2 2006.257.07:47:37.82#ibcon#flushed, iclass 36, count 2 2006.257.07:47:37.82#ibcon#about to write, iclass 36, count 2 2006.257.07:47:37.82#ibcon#wrote, iclass 36, count 2 2006.257.07:47:37.82#ibcon#about to read 3, iclass 36, count 2 2006.257.07:47:37.84#ibcon#read 3, iclass 36, count 2 2006.257.07:47:37.84#ibcon#about to read 4, iclass 36, count 2 2006.257.07:47:37.84#ibcon#read 4, iclass 36, count 2 2006.257.07:47:37.84#ibcon#about to read 5, iclass 36, count 2 2006.257.07:47:37.84#ibcon#read 5, iclass 36, count 2 2006.257.07:47:37.84#ibcon#about to read 6, iclass 36, count 2 2006.257.07:47:37.84#ibcon#read 6, iclass 36, count 2 2006.257.07:47:37.84#ibcon#end of sib2, iclass 36, count 2 2006.257.07:47:37.84#ibcon#*mode == 0, iclass 36, count 2 2006.257.07:47:37.84#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.07:47:37.84#ibcon#[25=AT08-04\r\n] 2006.257.07:47:37.84#ibcon#*before write, iclass 36, count 2 2006.257.07:47:37.84#ibcon#enter sib2, iclass 36, count 2 2006.257.07:47:37.84#ibcon#flushed, iclass 36, count 2 2006.257.07:47:37.84#ibcon#about to write, iclass 36, count 2 2006.257.07:47:37.84#ibcon#wrote, iclass 36, count 2 2006.257.07:47:37.84#ibcon#about to read 3, iclass 36, count 2 2006.257.07:47:37.87#ibcon#read 3, iclass 36, count 2 2006.257.07:47:37.87#ibcon#about to read 4, iclass 36, count 2 2006.257.07:47:37.87#ibcon#read 4, iclass 36, count 2 2006.257.07:47:37.87#ibcon#about to read 5, iclass 36, count 2 2006.257.07:47:37.87#ibcon#read 5, iclass 36, count 2 2006.257.07:47:37.87#ibcon#about to read 6, iclass 36, count 2 2006.257.07:47:37.87#ibcon#read 6, iclass 36, count 2 2006.257.07:47:37.87#ibcon#end of sib2, iclass 36, count 2 2006.257.07:47:37.87#ibcon#*after write, iclass 36, count 2 2006.257.07:47:37.87#ibcon#*before return 0, iclass 36, count 2 2006.257.07:47:37.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:47:37.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.07:47:37.87#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.07:47:37.87#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:37.87#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:47:37.99#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:47:37.99#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:47:37.99#ibcon#enter wrdev, iclass 36, count 0 2006.257.07:47:37.99#ibcon#first serial, iclass 36, count 0 2006.257.07:47:37.99#ibcon#enter sib2, iclass 36, count 0 2006.257.07:47:37.99#ibcon#flushed, iclass 36, count 0 2006.257.07:47:37.99#ibcon#about to write, iclass 36, count 0 2006.257.07:47:37.99#ibcon#wrote, iclass 36, count 0 2006.257.07:47:37.99#ibcon#about to read 3, iclass 36, count 0 2006.257.07:47:38.01#ibcon#read 3, iclass 36, count 0 2006.257.07:47:38.01#ibcon#about to read 4, iclass 36, count 0 2006.257.07:47:38.01#ibcon#read 4, iclass 36, count 0 2006.257.07:47:38.01#ibcon#about to read 5, iclass 36, count 0 2006.257.07:47:38.01#ibcon#read 5, iclass 36, count 0 2006.257.07:47:38.01#ibcon#about to read 6, iclass 36, count 0 2006.257.07:47:38.01#ibcon#read 6, iclass 36, count 0 2006.257.07:47:38.01#ibcon#end of sib2, iclass 36, count 0 2006.257.07:47:38.01#ibcon#*mode == 0, iclass 36, count 0 2006.257.07:47:38.01#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.07:47:38.01#ibcon#[25=USB\r\n] 2006.257.07:47:38.01#ibcon#*before write, iclass 36, count 0 2006.257.07:47:38.01#ibcon#enter sib2, iclass 36, count 0 2006.257.07:47:38.01#ibcon#flushed, iclass 36, count 0 2006.257.07:47:38.01#ibcon#about to write, iclass 36, count 0 2006.257.07:47:38.01#ibcon#wrote, iclass 36, count 0 2006.257.07:47:38.01#ibcon#about to read 3, iclass 36, count 0 2006.257.07:47:38.04#ibcon#read 3, iclass 36, count 0 2006.257.07:47:38.04#ibcon#about to read 4, iclass 36, count 0 2006.257.07:47:38.04#ibcon#read 4, iclass 36, count 0 2006.257.07:47:38.04#ibcon#about to read 5, iclass 36, count 0 2006.257.07:47:38.04#ibcon#read 5, iclass 36, count 0 2006.257.07:47:38.04#ibcon#about to read 6, iclass 36, count 0 2006.257.07:47:38.04#ibcon#read 6, iclass 36, count 0 2006.257.07:47:38.04#ibcon#end of sib2, iclass 36, count 0 2006.257.07:47:38.04#ibcon#*after write, iclass 36, count 0 2006.257.07:47:38.04#ibcon#*before return 0, iclass 36, count 0 2006.257.07:47:38.04#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:47:38.04#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.07:47:38.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.07:47:38.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.07:47:38.04$vck44/vblo=1,629.99 2006.257.07:47:38.04#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.07:47:38.04#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.07:47:38.04#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:38.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:47:38.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:47:38.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:47:38.04#ibcon#enter wrdev, iclass 38, count 0 2006.257.07:47:38.04#ibcon#first serial, iclass 38, count 0 2006.257.07:47:38.04#ibcon#enter sib2, iclass 38, count 0 2006.257.07:47:38.04#ibcon#flushed, iclass 38, count 0 2006.257.07:47:38.04#ibcon#about to write, iclass 38, count 0 2006.257.07:47:38.04#ibcon#wrote, iclass 38, count 0 2006.257.07:47:38.04#ibcon#about to read 3, iclass 38, count 0 2006.257.07:47:38.06#ibcon#read 3, iclass 38, count 0 2006.257.07:47:38.06#ibcon#about to read 4, iclass 38, count 0 2006.257.07:47:38.06#ibcon#read 4, iclass 38, count 0 2006.257.07:47:38.06#ibcon#about to read 5, iclass 38, count 0 2006.257.07:47:38.06#ibcon#read 5, iclass 38, count 0 2006.257.07:47:38.06#ibcon#about to read 6, iclass 38, count 0 2006.257.07:47:38.06#ibcon#read 6, iclass 38, count 0 2006.257.07:47:38.06#ibcon#end of sib2, iclass 38, count 0 2006.257.07:47:38.06#ibcon#*mode == 0, iclass 38, count 0 2006.257.07:47:38.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.07:47:38.06#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.07:47:38.06#ibcon#*before write, iclass 38, count 0 2006.257.07:47:38.06#ibcon#enter sib2, iclass 38, count 0 2006.257.07:47:38.06#ibcon#flushed, iclass 38, count 0 2006.257.07:47:38.06#ibcon#about to write, iclass 38, count 0 2006.257.07:47:38.06#ibcon#wrote, iclass 38, count 0 2006.257.07:47:38.06#ibcon#about to read 3, iclass 38, count 0 2006.257.07:47:38.10#ibcon#read 3, iclass 38, count 0 2006.257.07:47:38.10#ibcon#about to read 4, iclass 38, count 0 2006.257.07:47:38.10#ibcon#read 4, iclass 38, count 0 2006.257.07:47:38.10#ibcon#about to read 5, iclass 38, count 0 2006.257.07:47:38.10#ibcon#read 5, iclass 38, count 0 2006.257.07:47:38.10#ibcon#about to read 6, iclass 38, count 0 2006.257.07:47:38.10#ibcon#read 6, iclass 38, count 0 2006.257.07:47:38.10#ibcon#end of sib2, iclass 38, count 0 2006.257.07:47:38.10#ibcon#*after write, iclass 38, count 0 2006.257.07:47:38.10#ibcon#*before return 0, iclass 38, count 0 2006.257.07:47:38.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:47:38.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.07:47:38.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.07:47:38.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.07:47:38.10$vck44/vb=1,4 2006.257.07:47:38.10#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.07:47:38.10#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.07:47:38.10#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:38.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:47:38.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:47:38.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:47:38.10#ibcon#enter wrdev, iclass 40, count 2 2006.257.07:47:38.10#ibcon#first serial, iclass 40, count 2 2006.257.07:47:38.10#ibcon#enter sib2, iclass 40, count 2 2006.257.07:47:38.10#ibcon#flushed, iclass 40, count 2 2006.257.07:47:38.10#ibcon#about to write, iclass 40, count 2 2006.257.07:47:38.10#ibcon#wrote, iclass 40, count 2 2006.257.07:47:38.10#ibcon#about to read 3, iclass 40, count 2 2006.257.07:47:38.12#ibcon#read 3, iclass 40, count 2 2006.257.07:47:38.12#ibcon#about to read 4, iclass 40, count 2 2006.257.07:47:38.12#ibcon#read 4, iclass 40, count 2 2006.257.07:47:38.12#ibcon#about to read 5, iclass 40, count 2 2006.257.07:47:38.12#ibcon#read 5, iclass 40, count 2 2006.257.07:47:38.12#ibcon#about to read 6, iclass 40, count 2 2006.257.07:47:38.12#ibcon#read 6, iclass 40, count 2 2006.257.07:47:38.12#ibcon#end of sib2, iclass 40, count 2 2006.257.07:47:38.12#ibcon#*mode == 0, iclass 40, count 2 2006.257.07:47:38.12#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.07:47:38.12#ibcon#[27=AT01-04\r\n] 2006.257.07:47:38.12#ibcon#*before write, iclass 40, count 2 2006.257.07:47:38.12#ibcon#enter sib2, iclass 40, count 2 2006.257.07:47:38.12#ibcon#flushed, iclass 40, count 2 2006.257.07:47:38.12#ibcon#about to write, iclass 40, count 2 2006.257.07:47:38.12#ibcon#wrote, iclass 40, count 2 2006.257.07:47:38.12#ibcon#about to read 3, iclass 40, count 2 2006.257.07:47:38.15#ibcon#read 3, iclass 40, count 2 2006.257.07:47:38.15#ibcon#about to read 4, iclass 40, count 2 2006.257.07:47:38.15#ibcon#read 4, iclass 40, count 2 2006.257.07:47:38.15#ibcon#about to read 5, iclass 40, count 2 2006.257.07:47:38.15#ibcon#read 5, iclass 40, count 2 2006.257.07:47:38.15#ibcon#about to read 6, iclass 40, count 2 2006.257.07:47:38.15#ibcon#read 6, iclass 40, count 2 2006.257.07:47:38.15#ibcon#end of sib2, iclass 40, count 2 2006.257.07:47:38.15#ibcon#*after write, iclass 40, count 2 2006.257.07:47:38.15#ibcon#*before return 0, iclass 40, count 2 2006.257.07:47:38.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:47:38.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.07:47:38.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.07:47:38.15#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:38.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:47:38.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:47:38.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:47:38.27#ibcon#enter wrdev, iclass 40, count 0 2006.257.07:47:38.27#ibcon#first serial, iclass 40, count 0 2006.257.07:47:38.27#ibcon#enter sib2, iclass 40, count 0 2006.257.07:47:38.27#ibcon#flushed, iclass 40, count 0 2006.257.07:47:38.27#ibcon#about to write, iclass 40, count 0 2006.257.07:47:38.27#ibcon#wrote, iclass 40, count 0 2006.257.07:47:38.27#ibcon#about to read 3, iclass 40, count 0 2006.257.07:47:38.29#ibcon#read 3, iclass 40, count 0 2006.257.07:47:38.29#ibcon#about to read 4, iclass 40, count 0 2006.257.07:47:38.29#ibcon#read 4, iclass 40, count 0 2006.257.07:47:38.29#ibcon#about to read 5, iclass 40, count 0 2006.257.07:47:38.29#ibcon#read 5, iclass 40, count 0 2006.257.07:47:38.29#ibcon#about to read 6, iclass 40, count 0 2006.257.07:47:38.29#ibcon#read 6, iclass 40, count 0 2006.257.07:47:38.29#ibcon#end of sib2, iclass 40, count 0 2006.257.07:47:38.29#ibcon#*mode == 0, iclass 40, count 0 2006.257.07:47:38.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.07:47:38.29#ibcon#[27=USB\r\n] 2006.257.07:47:38.29#ibcon#*before write, iclass 40, count 0 2006.257.07:47:38.29#ibcon#enter sib2, iclass 40, count 0 2006.257.07:47:38.29#ibcon#flushed, iclass 40, count 0 2006.257.07:47:38.29#ibcon#about to write, iclass 40, count 0 2006.257.07:47:38.29#ibcon#wrote, iclass 40, count 0 2006.257.07:47:38.29#ibcon#about to read 3, iclass 40, count 0 2006.257.07:47:38.32#ibcon#read 3, iclass 40, count 0 2006.257.07:47:38.32#ibcon#about to read 4, iclass 40, count 0 2006.257.07:47:38.32#ibcon#read 4, iclass 40, count 0 2006.257.07:47:38.32#ibcon#about to read 5, iclass 40, count 0 2006.257.07:47:38.32#ibcon#read 5, iclass 40, count 0 2006.257.07:47:38.32#ibcon#about to read 6, iclass 40, count 0 2006.257.07:47:38.32#ibcon#read 6, iclass 40, count 0 2006.257.07:47:38.32#ibcon#end of sib2, iclass 40, count 0 2006.257.07:47:38.32#ibcon#*after write, iclass 40, count 0 2006.257.07:47:38.32#ibcon#*before return 0, iclass 40, count 0 2006.257.07:47:38.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:47:38.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.07:47:38.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.07:47:38.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.07:47:38.32$vck44/vblo=2,634.99 2006.257.07:47:38.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.07:47:38.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.07:47:38.32#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:38.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:38.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:38.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:38.32#ibcon#enter wrdev, iclass 4, count 0 2006.257.07:47:38.32#ibcon#first serial, iclass 4, count 0 2006.257.07:47:38.32#ibcon#enter sib2, iclass 4, count 0 2006.257.07:47:38.32#ibcon#flushed, iclass 4, count 0 2006.257.07:47:38.32#ibcon#about to write, iclass 4, count 0 2006.257.07:47:38.32#ibcon#wrote, iclass 4, count 0 2006.257.07:47:38.32#ibcon#about to read 3, iclass 4, count 0 2006.257.07:47:38.34#ibcon#read 3, iclass 4, count 0 2006.257.07:47:38.34#ibcon#about to read 4, iclass 4, count 0 2006.257.07:47:38.34#ibcon#read 4, iclass 4, count 0 2006.257.07:47:38.34#ibcon#about to read 5, iclass 4, count 0 2006.257.07:47:38.34#ibcon#read 5, iclass 4, count 0 2006.257.07:47:38.34#ibcon#about to read 6, iclass 4, count 0 2006.257.07:47:38.34#ibcon#read 6, iclass 4, count 0 2006.257.07:47:38.34#ibcon#end of sib2, iclass 4, count 0 2006.257.07:47:38.34#ibcon#*mode == 0, iclass 4, count 0 2006.257.07:47:38.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.07:47:38.34#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.07:47:38.34#ibcon#*before write, iclass 4, count 0 2006.257.07:47:38.34#ibcon#enter sib2, iclass 4, count 0 2006.257.07:47:38.34#ibcon#flushed, iclass 4, count 0 2006.257.07:47:38.34#ibcon#about to write, iclass 4, count 0 2006.257.07:47:38.34#ibcon#wrote, iclass 4, count 0 2006.257.07:47:38.34#ibcon#about to read 3, iclass 4, count 0 2006.257.07:47:38.38#ibcon#read 3, iclass 4, count 0 2006.257.07:47:38.38#ibcon#about to read 4, iclass 4, count 0 2006.257.07:47:38.38#ibcon#read 4, iclass 4, count 0 2006.257.07:47:38.38#ibcon#about to read 5, iclass 4, count 0 2006.257.07:47:38.38#ibcon#read 5, iclass 4, count 0 2006.257.07:47:38.38#ibcon#about to read 6, iclass 4, count 0 2006.257.07:47:38.38#ibcon#read 6, iclass 4, count 0 2006.257.07:47:38.38#ibcon#end of sib2, iclass 4, count 0 2006.257.07:47:38.38#ibcon#*after write, iclass 4, count 0 2006.257.07:47:38.38#ibcon#*before return 0, iclass 4, count 0 2006.257.07:47:38.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:38.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:47:38.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.07:47:38.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.07:47:38.38$vck44/vb=2,5 2006.257.07:47:38.38#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.07:47:38.38#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.07:47:38.38#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:38.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:38.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:38.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:38.44#ibcon#enter wrdev, iclass 6, count 2 2006.257.07:47:38.44#ibcon#first serial, iclass 6, count 2 2006.257.07:47:38.44#ibcon#enter sib2, iclass 6, count 2 2006.257.07:47:38.44#ibcon#flushed, iclass 6, count 2 2006.257.07:47:38.44#ibcon#about to write, iclass 6, count 2 2006.257.07:47:38.44#ibcon#wrote, iclass 6, count 2 2006.257.07:47:38.44#ibcon#about to read 3, iclass 6, count 2 2006.257.07:47:38.46#ibcon#read 3, iclass 6, count 2 2006.257.07:47:38.46#ibcon#about to read 4, iclass 6, count 2 2006.257.07:47:38.46#ibcon#read 4, iclass 6, count 2 2006.257.07:47:38.46#ibcon#about to read 5, iclass 6, count 2 2006.257.07:47:38.46#ibcon#read 5, iclass 6, count 2 2006.257.07:47:38.46#ibcon#about to read 6, iclass 6, count 2 2006.257.07:47:38.46#ibcon#read 6, iclass 6, count 2 2006.257.07:47:38.46#ibcon#end of sib2, iclass 6, count 2 2006.257.07:47:38.46#ibcon#*mode == 0, iclass 6, count 2 2006.257.07:47:38.46#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.07:47:38.46#ibcon#[27=AT02-05\r\n] 2006.257.07:47:38.46#ibcon#*before write, iclass 6, count 2 2006.257.07:47:38.46#ibcon#enter sib2, iclass 6, count 2 2006.257.07:47:38.46#ibcon#flushed, iclass 6, count 2 2006.257.07:47:38.46#ibcon#about to write, iclass 6, count 2 2006.257.07:47:38.46#ibcon#wrote, iclass 6, count 2 2006.257.07:47:38.46#ibcon#about to read 3, iclass 6, count 2 2006.257.07:47:38.49#ibcon#read 3, iclass 6, count 2 2006.257.07:47:38.49#ibcon#about to read 4, iclass 6, count 2 2006.257.07:47:38.49#ibcon#read 4, iclass 6, count 2 2006.257.07:47:38.49#ibcon#about to read 5, iclass 6, count 2 2006.257.07:47:38.49#ibcon#read 5, iclass 6, count 2 2006.257.07:47:38.49#ibcon#about to read 6, iclass 6, count 2 2006.257.07:47:38.49#ibcon#read 6, iclass 6, count 2 2006.257.07:47:38.49#ibcon#end of sib2, iclass 6, count 2 2006.257.07:47:38.49#ibcon#*after write, iclass 6, count 2 2006.257.07:47:38.49#ibcon#*before return 0, iclass 6, count 2 2006.257.07:47:38.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:38.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.07:47:38.49#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.07:47:38.49#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:38.49#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:38.61#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:38.61#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:38.61#ibcon#enter wrdev, iclass 6, count 0 2006.257.07:47:38.61#ibcon#first serial, iclass 6, count 0 2006.257.07:47:38.61#ibcon#enter sib2, iclass 6, count 0 2006.257.07:47:38.61#ibcon#flushed, iclass 6, count 0 2006.257.07:47:38.61#ibcon#about to write, iclass 6, count 0 2006.257.07:47:38.61#ibcon#wrote, iclass 6, count 0 2006.257.07:47:38.61#ibcon#about to read 3, iclass 6, count 0 2006.257.07:47:38.63#ibcon#read 3, iclass 6, count 0 2006.257.07:47:38.63#ibcon#about to read 4, iclass 6, count 0 2006.257.07:47:38.63#ibcon#read 4, iclass 6, count 0 2006.257.07:47:38.63#ibcon#about to read 5, iclass 6, count 0 2006.257.07:47:38.63#ibcon#read 5, iclass 6, count 0 2006.257.07:47:38.63#ibcon#about to read 6, iclass 6, count 0 2006.257.07:47:38.63#ibcon#read 6, iclass 6, count 0 2006.257.07:47:38.63#ibcon#end of sib2, iclass 6, count 0 2006.257.07:47:38.63#ibcon#*mode == 0, iclass 6, count 0 2006.257.07:47:38.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.07:47:38.63#ibcon#[27=USB\r\n] 2006.257.07:47:38.63#ibcon#*before write, iclass 6, count 0 2006.257.07:47:38.63#ibcon#enter sib2, iclass 6, count 0 2006.257.07:47:38.63#ibcon#flushed, iclass 6, count 0 2006.257.07:47:38.63#ibcon#about to write, iclass 6, count 0 2006.257.07:47:38.63#ibcon#wrote, iclass 6, count 0 2006.257.07:47:38.63#ibcon#about to read 3, iclass 6, count 0 2006.257.07:47:38.66#ibcon#read 3, iclass 6, count 0 2006.257.07:47:38.66#ibcon#about to read 4, iclass 6, count 0 2006.257.07:47:38.66#ibcon#read 4, iclass 6, count 0 2006.257.07:47:38.66#ibcon#about to read 5, iclass 6, count 0 2006.257.07:47:38.66#ibcon#read 5, iclass 6, count 0 2006.257.07:47:38.66#ibcon#about to read 6, iclass 6, count 0 2006.257.07:47:38.66#ibcon#read 6, iclass 6, count 0 2006.257.07:47:38.66#ibcon#end of sib2, iclass 6, count 0 2006.257.07:47:38.66#ibcon#*after write, iclass 6, count 0 2006.257.07:47:38.66#ibcon#*before return 0, iclass 6, count 0 2006.257.07:47:38.66#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:38.66#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.07:47:38.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.07:47:38.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.07:47:38.66$vck44/vblo=3,649.99 2006.257.07:47:38.66#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.07:47:38.66#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.07:47:38.66#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:38.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:38.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:38.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:38.66#ibcon#enter wrdev, iclass 10, count 0 2006.257.07:47:38.66#ibcon#first serial, iclass 10, count 0 2006.257.07:47:38.66#ibcon#enter sib2, iclass 10, count 0 2006.257.07:47:38.66#ibcon#flushed, iclass 10, count 0 2006.257.07:47:38.66#ibcon#about to write, iclass 10, count 0 2006.257.07:47:38.66#ibcon#wrote, iclass 10, count 0 2006.257.07:47:38.66#ibcon#about to read 3, iclass 10, count 0 2006.257.07:47:38.68#ibcon#read 3, iclass 10, count 0 2006.257.07:47:38.68#ibcon#about to read 4, iclass 10, count 0 2006.257.07:47:38.68#ibcon#read 4, iclass 10, count 0 2006.257.07:47:38.68#ibcon#about to read 5, iclass 10, count 0 2006.257.07:47:38.68#ibcon#read 5, iclass 10, count 0 2006.257.07:47:38.68#ibcon#about to read 6, iclass 10, count 0 2006.257.07:47:38.68#ibcon#read 6, iclass 10, count 0 2006.257.07:47:38.68#ibcon#end of sib2, iclass 10, count 0 2006.257.07:47:38.68#ibcon#*mode == 0, iclass 10, count 0 2006.257.07:47:38.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.07:47:38.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.07:47:38.68#ibcon#*before write, iclass 10, count 0 2006.257.07:47:38.68#ibcon#enter sib2, iclass 10, count 0 2006.257.07:47:38.68#ibcon#flushed, iclass 10, count 0 2006.257.07:47:38.68#ibcon#about to write, iclass 10, count 0 2006.257.07:47:38.68#ibcon#wrote, iclass 10, count 0 2006.257.07:47:38.68#ibcon#about to read 3, iclass 10, count 0 2006.257.07:47:38.72#ibcon#read 3, iclass 10, count 0 2006.257.07:47:38.72#ibcon#about to read 4, iclass 10, count 0 2006.257.07:47:38.72#ibcon#read 4, iclass 10, count 0 2006.257.07:47:38.72#ibcon#about to read 5, iclass 10, count 0 2006.257.07:47:38.72#ibcon#read 5, iclass 10, count 0 2006.257.07:47:38.72#ibcon#about to read 6, iclass 10, count 0 2006.257.07:47:38.72#ibcon#read 6, iclass 10, count 0 2006.257.07:47:38.72#ibcon#end of sib2, iclass 10, count 0 2006.257.07:47:38.72#ibcon#*after write, iclass 10, count 0 2006.257.07:47:38.72#ibcon#*before return 0, iclass 10, count 0 2006.257.07:47:38.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:38.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.07:47:38.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.07:47:38.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.07:47:38.72$vck44/vb=3,4 2006.257.07:47:38.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.07:47:38.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.07:47:38.72#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:38.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:38.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:38.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:38.78#ibcon#enter wrdev, iclass 12, count 2 2006.257.07:47:38.78#ibcon#first serial, iclass 12, count 2 2006.257.07:47:38.78#ibcon#enter sib2, iclass 12, count 2 2006.257.07:47:38.78#ibcon#flushed, iclass 12, count 2 2006.257.07:47:38.78#ibcon#about to write, iclass 12, count 2 2006.257.07:47:38.78#ibcon#wrote, iclass 12, count 2 2006.257.07:47:38.78#ibcon#about to read 3, iclass 12, count 2 2006.257.07:47:38.80#ibcon#read 3, iclass 12, count 2 2006.257.07:47:38.80#ibcon#about to read 4, iclass 12, count 2 2006.257.07:47:38.80#ibcon#read 4, iclass 12, count 2 2006.257.07:47:38.80#ibcon#about to read 5, iclass 12, count 2 2006.257.07:47:38.80#ibcon#read 5, iclass 12, count 2 2006.257.07:47:38.80#ibcon#about to read 6, iclass 12, count 2 2006.257.07:47:38.80#ibcon#read 6, iclass 12, count 2 2006.257.07:47:38.80#ibcon#end of sib2, iclass 12, count 2 2006.257.07:47:38.80#ibcon#*mode == 0, iclass 12, count 2 2006.257.07:47:38.80#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.07:47:38.80#ibcon#[27=AT03-04\r\n] 2006.257.07:47:38.80#ibcon#*before write, iclass 12, count 2 2006.257.07:47:38.80#ibcon#enter sib2, iclass 12, count 2 2006.257.07:47:38.80#ibcon#flushed, iclass 12, count 2 2006.257.07:47:38.80#ibcon#about to write, iclass 12, count 2 2006.257.07:47:38.80#ibcon#wrote, iclass 12, count 2 2006.257.07:47:38.80#ibcon#about to read 3, iclass 12, count 2 2006.257.07:47:38.83#ibcon#read 3, iclass 12, count 2 2006.257.07:47:38.83#ibcon#about to read 4, iclass 12, count 2 2006.257.07:47:38.83#ibcon#read 4, iclass 12, count 2 2006.257.07:47:38.83#ibcon#about to read 5, iclass 12, count 2 2006.257.07:47:38.83#ibcon#read 5, iclass 12, count 2 2006.257.07:47:38.83#ibcon#about to read 6, iclass 12, count 2 2006.257.07:47:38.83#ibcon#read 6, iclass 12, count 2 2006.257.07:47:38.83#ibcon#end of sib2, iclass 12, count 2 2006.257.07:47:38.83#ibcon#*after write, iclass 12, count 2 2006.257.07:47:38.83#ibcon#*before return 0, iclass 12, count 2 2006.257.07:47:38.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:38.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.07:47:38.83#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.07:47:38.83#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:38.83#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:38.95#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:38.95#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:38.95#ibcon#enter wrdev, iclass 12, count 0 2006.257.07:47:38.95#ibcon#first serial, iclass 12, count 0 2006.257.07:47:38.95#ibcon#enter sib2, iclass 12, count 0 2006.257.07:47:38.95#ibcon#flushed, iclass 12, count 0 2006.257.07:47:38.95#ibcon#about to write, iclass 12, count 0 2006.257.07:47:38.95#ibcon#wrote, iclass 12, count 0 2006.257.07:47:38.95#ibcon#about to read 3, iclass 12, count 0 2006.257.07:47:38.97#ibcon#read 3, iclass 12, count 0 2006.257.07:47:38.97#ibcon#about to read 4, iclass 12, count 0 2006.257.07:47:38.97#ibcon#read 4, iclass 12, count 0 2006.257.07:47:38.97#ibcon#about to read 5, iclass 12, count 0 2006.257.07:47:38.97#ibcon#read 5, iclass 12, count 0 2006.257.07:47:38.97#ibcon#about to read 6, iclass 12, count 0 2006.257.07:47:38.97#ibcon#read 6, iclass 12, count 0 2006.257.07:47:38.97#ibcon#end of sib2, iclass 12, count 0 2006.257.07:47:38.97#ibcon#*mode == 0, iclass 12, count 0 2006.257.07:47:38.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.07:47:38.97#ibcon#[27=USB\r\n] 2006.257.07:47:38.97#ibcon#*before write, iclass 12, count 0 2006.257.07:47:38.97#ibcon#enter sib2, iclass 12, count 0 2006.257.07:47:38.97#ibcon#flushed, iclass 12, count 0 2006.257.07:47:38.97#ibcon#about to write, iclass 12, count 0 2006.257.07:47:38.97#ibcon#wrote, iclass 12, count 0 2006.257.07:47:38.97#ibcon#about to read 3, iclass 12, count 0 2006.257.07:47:39.00#ibcon#read 3, iclass 12, count 0 2006.257.07:47:39.00#ibcon#about to read 4, iclass 12, count 0 2006.257.07:47:39.00#ibcon#read 4, iclass 12, count 0 2006.257.07:47:39.00#ibcon#about to read 5, iclass 12, count 0 2006.257.07:47:39.00#ibcon#read 5, iclass 12, count 0 2006.257.07:47:39.00#ibcon#about to read 6, iclass 12, count 0 2006.257.07:47:39.00#ibcon#read 6, iclass 12, count 0 2006.257.07:47:39.00#ibcon#end of sib2, iclass 12, count 0 2006.257.07:47:39.00#ibcon#*after write, iclass 12, count 0 2006.257.07:47:39.00#ibcon#*before return 0, iclass 12, count 0 2006.257.07:47:39.00#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:39.00#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.07:47:39.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.07:47:39.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.07:47:39.00$vck44/vblo=4,679.99 2006.257.07:47:39.00#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.07:47:39.00#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.07:47:39.00#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:39.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:39.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:39.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:39.00#ibcon#enter wrdev, iclass 14, count 0 2006.257.07:47:39.00#ibcon#first serial, iclass 14, count 0 2006.257.07:47:39.00#ibcon#enter sib2, iclass 14, count 0 2006.257.07:47:39.00#ibcon#flushed, iclass 14, count 0 2006.257.07:47:39.00#ibcon#about to write, iclass 14, count 0 2006.257.07:47:39.00#ibcon#wrote, iclass 14, count 0 2006.257.07:47:39.00#ibcon#about to read 3, iclass 14, count 0 2006.257.07:47:39.02#ibcon#read 3, iclass 14, count 0 2006.257.07:47:39.02#ibcon#about to read 4, iclass 14, count 0 2006.257.07:47:39.02#ibcon#read 4, iclass 14, count 0 2006.257.07:47:39.02#ibcon#about to read 5, iclass 14, count 0 2006.257.07:47:39.02#ibcon#read 5, iclass 14, count 0 2006.257.07:47:39.02#ibcon#about to read 6, iclass 14, count 0 2006.257.07:47:39.02#ibcon#read 6, iclass 14, count 0 2006.257.07:47:39.02#ibcon#end of sib2, iclass 14, count 0 2006.257.07:47:39.02#ibcon#*mode == 0, iclass 14, count 0 2006.257.07:47:39.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.07:47:39.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.07:47:39.02#ibcon#*before write, iclass 14, count 0 2006.257.07:47:39.02#ibcon#enter sib2, iclass 14, count 0 2006.257.07:47:39.02#ibcon#flushed, iclass 14, count 0 2006.257.07:47:39.02#ibcon#about to write, iclass 14, count 0 2006.257.07:47:39.02#ibcon#wrote, iclass 14, count 0 2006.257.07:47:39.02#ibcon#about to read 3, iclass 14, count 0 2006.257.07:47:39.06#ibcon#read 3, iclass 14, count 0 2006.257.07:47:39.06#ibcon#about to read 4, iclass 14, count 0 2006.257.07:47:39.06#ibcon#read 4, iclass 14, count 0 2006.257.07:47:39.06#ibcon#about to read 5, iclass 14, count 0 2006.257.07:47:39.06#ibcon#read 5, iclass 14, count 0 2006.257.07:47:39.06#ibcon#about to read 6, iclass 14, count 0 2006.257.07:47:39.06#ibcon#read 6, iclass 14, count 0 2006.257.07:47:39.06#ibcon#end of sib2, iclass 14, count 0 2006.257.07:47:39.06#ibcon#*after write, iclass 14, count 0 2006.257.07:47:39.06#ibcon#*before return 0, iclass 14, count 0 2006.257.07:47:39.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:39.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.07:47:39.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.07:47:39.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.07:47:39.06$vck44/vb=4,5 2006.257.07:47:39.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.07:47:39.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.07:47:39.06#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:39.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:39.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:39.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:39.12#ibcon#enter wrdev, iclass 16, count 2 2006.257.07:47:39.12#ibcon#first serial, iclass 16, count 2 2006.257.07:47:39.12#ibcon#enter sib2, iclass 16, count 2 2006.257.07:47:39.12#ibcon#flushed, iclass 16, count 2 2006.257.07:47:39.12#ibcon#about to write, iclass 16, count 2 2006.257.07:47:39.12#ibcon#wrote, iclass 16, count 2 2006.257.07:47:39.12#ibcon#about to read 3, iclass 16, count 2 2006.257.07:47:39.14#ibcon#read 3, iclass 16, count 2 2006.257.07:47:39.14#ibcon#about to read 4, iclass 16, count 2 2006.257.07:47:39.14#ibcon#read 4, iclass 16, count 2 2006.257.07:47:39.14#ibcon#about to read 5, iclass 16, count 2 2006.257.07:47:39.14#ibcon#read 5, iclass 16, count 2 2006.257.07:47:39.14#ibcon#about to read 6, iclass 16, count 2 2006.257.07:47:39.14#ibcon#read 6, iclass 16, count 2 2006.257.07:47:39.14#ibcon#end of sib2, iclass 16, count 2 2006.257.07:47:39.14#ibcon#*mode == 0, iclass 16, count 2 2006.257.07:47:39.14#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.07:47:39.14#ibcon#[27=AT04-05\r\n] 2006.257.07:47:39.14#ibcon#*before write, iclass 16, count 2 2006.257.07:47:39.14#ibcon#enter sib2, iclass 16, count 2 2006.257.07:47:39.14#ibcon#flushed, iclass 16, count 2 2006.257.07:47:39.14#ibcon#about to write, iclass 16, count 2 2006.257.07:47:39.14#ibcon#wrote, iclass 16, count 2 2006.257.07:47:39.14#ibcon#about to read 3, iclass 16, count 2 2006.257.07:47:39.17#ibcon#read 3, iclass 16, count 2 2006.257.07:47:39.17#ibcon#about to read 4, iclass 16, count 2 2006.257.07:47:39.17#ibcon#read 4, iclass 16, count 2 2006.257.07:47:39.17#ibcon#about to read 5, iclass 16, count 2 2006.257.07:47:39.17#ibcon#read 5, iclass 16, count 2 2006.257.07:47:39.17#ibcon#about to read 6, iclass 16, count 2 2006.257.07:47:39.17#ibcon#read 6, iclass 16, count 2 2006.257.07:47:39.17#ibcon#end of sib2, iclass 16, count 2 2006.257.07:47:39.17#ibcon#*after write, iclass 16, count 2 2006.257.07:47:39.17#ibcon#*before return 0, iclass 16, count 2 2006.257.07:47:39.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:39.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.07:47:39.17#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.07:47:39.17#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:39.17#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:39.29#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:39.29#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:39.29#ibcon#enter wrdev, iclass 16, count 0 2006.257.07:47:39.29#ibcon#first serial, iclass 16, count 0 2006.257.07:47:39.29#ibcon#enter sib2, iclass 16, count 0 2006.257.07:47:39.29#ibcon#flushed, iclass 16, count 0 2006.257.07:47:39.29#ibcon#about to write, iclass 16, count 0 2006.257.07:47:39.29#ibcon#wrote, iclass 16, count 0 2006.257.07:47:39.29#ibcon#about to read 3, iclass 16, count 0 2006.257.07:47:39.31#ibcon#read 3, iclass 16, count 0 2006.257.07:47:39.31#ibcon#about to read 4, iclass 16, count 0 2006.257.07:47:39.31#ibcon#read 4, iclass 16, count 0 2006.257.07:47:39.31#ibcon#about to read 5, iclass 16, count 0 2006.257.07:47:39.31#ibcon#read 5, iclass 16, count 0 2006.257.07:47:39.31#ibcon#about to read 6, iclass 16, count 0 2006.257.07:47:39.31#ibcon#read 6, iclass 16, count 0 2006.257.07:47:39.31#ibcon#end of sib2, iclass 16, count 0 2006.257.07:47:39.31#ibcon#*mode == 0, iclass 16, count 0 2006.257.07:47:39.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.07:47:39.31#ibcon#[27=USB\r\n] 2006.257.07:47:39.31#ibcon#*before write, iclass 16, count 0 2006.257.07:47:39.31#ibcon#enter sib2, iclass 16, count 0 2006.257.07:47:39.31#ibcon#flushed, iclass 16, count 0 2006.257.07:47:39.31#ibcon#about to write, iclass 16, count 0 2006.257.07:47:39.31#ibcon#wrote, iclass 16, count 0 2006.257.07:47:39.31#ibcon#about to read 3, iclass 16, count 0 2006.257.07:47:39.34#ibcon#read 3, iclass 16, count 0 2006.257.07:47:39.34#ibcon#about to read 4, iclass 16, count 0 2006.257.07:47:39.34#ibcon#read 4, iclass 16, count 0 2006.257.07:47:39.34#ibcon#about to read 5, iclass 16, count 0 2006.257.07:47:39.34#ibcon#read 5, iclass 16, count 0 2006.257.07:47:39.34#ibcon#about to read 6, iclass 16, count 0 2006.257.07:47:39.34#ibcon#read 6, iclass 16, count 0 2006.257.07:47:39.34#ibcon#end of sib2, iclass 16, count 0 2006.257.07:47:39.34#ibcon#*after write, iclass 16, count 0 2006.257.07:47:39.34#ibcon#*before return 0, iclass 16, count 0 2006.257.07:47:39.34#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:39.34#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.07:47:39.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.07:47:39.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.07:47:39.34$vck44/vblo=5,709.99 2006.257.07:47:39.34#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.07:47:39.34#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.07:47:39.34#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:39.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:39.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:39.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:39.34#ibcon#enter wrdev, iclass 18, count 0 2006.257.07:47:39.34#ibcon#first serial, iclass 18, count 0 2006.257.07:47:39.34#ibcon#enter sib2, iclass 18, count 0 2006.257.07:47:39.34#ibcon#flushed, iclass 18, count 0 2006.257.07:47:39.34#ibcon#about to write, iclass 18, count 0 2006.257.07:47:39.34#ibcon#wrote, iclass 18, count 0 2006.257.07:47:39.34#ibcon#about to read 3, iclass 18, count 0 2006.257.07:47:39.36#ibcon#read 3, iclass 18, count 0 2006.257.07:47:39.36#ibcon#about to read 4, iclass 18, count 0 2006.257.07:47:39.36#ibcon#read 4, iclass 18, count 0 2006.257.07:47:39.36#ibcon#about to read 5, iclass 18, count 0 2006.257.07:47:39.36#ibcon#read 5, iclass 18, count 0 2006.257.07:47:39.36#ibcon#about to read 6, iclass 18, count 0 2006.257.07:47:39.36#ibcon#read 6, iclass 18, count 0 2006.257.07:47:39.36#ibcon#end of sib2, iclass 18, count 0 2006.257.07:47:39.36#ibcon#*mode == 0, iclass 18, count 0 2006.257.07:47:39.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.07:47:39.36#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.07:47:39.36#ibcon#*before write, iclass 18, count 0 2006.257.07:47:39.36#ibcon#enter sib2, iclass 18, count 0 2006.257.07:47:39.36#ibcon#flushed, iclass 18, count 0 2006.257.07:47:39.36#ibcon#about to write, iclass 18, count 0 2006.257.07:47:39.36#ibcon#wrote, iclass 18, count 0 2006.257.07:47:39.36#ibcon#about to read 3, iclass 18, count 0 2006.257.07:47:39.40#ibcon#read 3, iclass 18, count 0 2006.257.07:47:39.40#ibcon#about to read 4, iclass 18, count 0 2006.257.07:47:39.40#ibcon#read 4, iclass 18, count 0 2006.257.07:47:39.40#ibcon#about to read 5, iclass 18, count 0 2006.257.07:47:39.40#ibcon#read 5, iclass 18, count 0 2006.257.07:47:39.40#ibcon#about to read 6, iclass 18, count 0 2006.257.07:47:39.40#ibcon#read 6, iclass 18, count 0 2006.257.07:47:39.40#ibcon#end of sib2, iclass 18, count 0 2006.257.07:47:39.40#ibcon#*after write, iclass 18, count 0 2006.257.07:47:39.40#ibcon#*before return 0, iclass 18, count 0 2006.257.07:47:39.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:39.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.07:47:39.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.07:47:39.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.07:47:39.40$vck44/vb=5,4 2006.257.07:47:39.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.07:47:39.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.07:47:39.40#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:39.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:39.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:39.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:39.46#ibcon#enter wrdev, iclass 20, count 2 2006.257.07:47:39.46#ibcon#first serial, iclass 20, count 2 2006.257.07:47:39.46#ibcon#enter sib2, iclass 20, count 2 2006.257.07:47:39.46#ibcon#flushed, iclass 20, count 2 2006.257.07:47:39.46#ibcon#about to write, iclass 20, count 2 2006.257.07:47:39.46#ibcon#wrote, iclass 20, count 2 2006.257.07:47:39.46#ibcon#about to read 3, iclass 20, count 2 2006.257.07:47:39.48#ibcon#read 3, iclass 20, count 2 2006.257.07:47:39.48#ibcon#about to read 4, iclass 20, count 2 2006.257.07:47:39.48#ibcon#read 4, iclass 20, count 2 2006.257.07:47:39.48#ibcon#about to read 5, iclass 20, count 2 2006.257.07:47:39.48#ibcon#read 5, iclass 20, count 2 2006.257.07:47:39.48#ibcon#about to read 6, iclass 20, count 2 2006.257.07:47:39.48#ibcon#read 6, iclass 20, count 2 2006.257.07:47:39.48#ibcon#end of sib2, iclass 20, count 2 2006.257.07:47:39.48#ibcon#*mode == 0, iclass 20, count 2 2006.257.07:47:39.48#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.07:47:39.48#ibcon#[27=AT05-04\r\n] 2006.257.07:47:39.48#ibcon#*before write, iclass 20, count 2 2006.257.07:47:39.48#ibcon#enter sib2, iclass 20, count 2 2006.257.07:47:39.48#ibcon#flushed, iclass 20, count 2 2006.257.07:47:39.48#ibcon#about to write, iclass 20, count 2 2006.257.07:47:39.48#ibcon#wrote, iclass 20, count 2 2006.257.07:47:39.48#ibcon#about to read 3, iclass 20, count 2 2006.257.07:47:39.51#ibcon#read 3, iclass 20, count 2 2006.257.07:47:39.51#ibcon#about to read 4, iclass 20, count 2 2006.257.07:47:39.51#ibcon#read 4, iclass 20, count 2 2006.257.07:47:39.51#ibcon#about to read 5, iclass 20, count 2 2006.257.07:47:39.51#ibcon#read 5, iclass 20, count 2 2006.257.07:47:39.51#ibcon#about to read 6, iclass 20, count 2 2006.257.07:47:39.51#ibcon#read 6, iclass 20, count 2 2006.257.07:47:39.51#ibcon#end of sib2, iclass 20, count 2 2006.257.07:47:39.51#ibcon#*after write, iclass 20, count 2 2006.257.07:47:39.51#ibcon#*before return 0, iclass 20, count 2 2006.257.07:47:39.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:39.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.07:47:39.51#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.07:47:39.51#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:39.51#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:39.63#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:39.63#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:39.63#ibcon#enter wrdev, iclass 20, count 0 2006.257.07:47:39.63#ibcon#first serial, iclass 20, count 0 2006.257.07:47:39.63#ibcon#enter sib2, iclass 20, count 0 2006.257.07:47:39.63#ibcon#flushed, iclass 20, count 0 2006.257.07:47:39.63#ibcon#about to write, iclass 20, count 0 2006.257.07:47:39.63#ibcon#wrote, iclass 20, count 0 2006.257.07:47:39.63#ibcon#about to read 3, iclass 20, count 0 2006.257.07:47:39.65#ibcon#read 3, iclass 20, count 0 2006.257.07:47:39.65#ibcon#about to read 4, iclass 20, count 0 2006.257.07:47:39.65#ibcon#read 4, iclass 20, count 0 2006.257.07:47:39.65#ibcon#about to read 5, iclass 20, count 0 2006.257.07:47:39.65#ibcon#read 5, iclass 20, count 0 2006.257.07:47:39.65#ibcon#about to read 6, iclass 20, count 0 2006.257.07:47:39.65#ibcon#read 6, iclass 20, count 0 2006.257.07:47:39.65#ibcon#end of sib2, iclass 20, count 0 2006.257.07:47:39.65#ibcon#*mode == 0, iclass 20, count 0 2006.257.07:47:39.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.07:47:39.65#ibcon#[27=USB\r\n] 2006.257.07:47:39.65#ibcon#*before write, iclass 20, count 0 2006.257.07:47:39.65#ibcon#enter sib2, iclass 20, count 0 2006.257.07:47:39.65#ibcon#flushed, iclass 20, count 0 2006.257.07:47:39.65#ibcon#about to write, iclass 20, count 0 2006.257.07:47:39.65#ibcon#wrote, iclass 20, count 0 2006.257.07:47:39.65#ibcon#about to read 3, iclass 20, count 0 2006.257.07:47:39.68#ibcon#read 3, iclass 20, count 0 2006.257.07:47:39.68#ibcon#about to read 4, iclass 20, count 0 2006.257.07:47:39.68#ibcon#read 4, iclass 20, count 0 2006.257.07:47:39.68#ibcon#about to read 5, iclass 20, count 0 2006.257.07:47:39.68#ibcon#read 5, iclass 20, count 0 2006.257.07:47:39.68#ibcon#about to read 6, iclass 20, count 0 2006.257.07:47:39.68#ibcon#read 6, iclass 20, count 0 2006.257.07:47:39.68#ibcon#end of sib2, iclass 20, count 0 2006.257.07:47:39.68#ibcon#*after write, iclass 20, count 0 2006.257.07:47:39.68#ibcon#*before return 0, iclass 20, count 0 2006.257.07:47:39.68#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:39.68#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.07:47:39.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.07:47:39.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.07:47:39.68$vck44/vblo=6,719.99 2006.257.07:47:39.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.07:47:39.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.07:47:39.68#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:39.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:39.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:39.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:39.68#ibcon#enter wrdev, iclass 22, count 0 2006.257.07:47:39.68#ibcon#first serial, iclass 22, count 0 2006.257.07:47:39.68#ibcon#enter sib2, iclass 22, count 0 2006.257.07:47:39.68#ibcon#flushed, iclass 22, count 0 2006.257.07:47:39.68#ibcon#about to write, iclass 22, count 0 2006.257.07:47:39.68#ibcon#wrote, iclass 22, count 0 2006.257.07:47:39.68#ibcon#about to read 3, iclass 22, count 0 2006.257.07:47:39.70#ibcon#read 3, iclass 22, count 0 2006.257.07:47:39.70#ibcon#about to read 4, iclass 22, count 0 2006.257.07:47:39.70#ibcon#read 4, iclass 22, count 0 2006.257.07:47:39.70#ibcon#about to read 5, iclass 22, count 0 2006.257.07:47:39.70#ibcon#read 5, iclass 22, count 0 2006.257.07:47:39.70#ibcon#about to read 6, iclass 22, count 0 2006.257.07:47:39.70#ibcon#read 6, iclass 22, count 0 2006.257.07:47:39.70#ibcon#end of sib2, iclass 22, count 0 2006.257.07:47:39.70#ibcon#*mode == 0, iclass 22, count 0 2006.257.07:47:39.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.07:47:39.70#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.07:47:39.70#ibcon#*before write, iclass 22, count 0 2006.257.07:47:39.70#ibcon#enter sib2, iclass 22, count 0 2006.257.07:47:39.70#ibcon#flushed, iclass 22, count 0 2006.257.07:47:39.70#ibcon#about to write, iclass 22, count 0 2006.257.07:47:39.70#ibcon#wrote, iclass 22, count 0 2006.257.07:47:39.70#ibcon#about to read 3, iclass 22, count 0 2006.257.07:47:39.74#ibcon#read 3, iclass 22, count 0 2006.257.07:47:39.74#ibcon#about to read 4, iclass 22, count 0 2006.257.07:47:39.74#ibcon#read 4, iclass 22, count 0 2006.257.07:47:39.74#ibcon#about to read 5, iclass 22, count 0 2006.257.07:47:39.74#ibcon#read 5, iclass 22, count 0 2006.257.07:47:39.74#ibcon#about to read 6, iclass 22, count 0 2006.257.07:47:39.74#ibcon#read 6, iclass 22, count 0 2006.257.07:47:39.74#ibcon#end of sib2, iclass 22, count 0 2006.257.07:47:39.74#ibcon#*after write, iclass 22, count 0 2006.257.07:47:39.74#ibcon#*before return 0, iclass 22, count 0 2006.257.07:47:39.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:39.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.07:47:39.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.07:47:39.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.07:47:39.74$vck44/vb=6,4 2006.257.07:47:39.74#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.07:47:39.74#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.07:47:39.74#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:39.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:39.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:39.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:39.80#ibcon#enter wrdev, iclass 24, count 2 2006.257.07:47:39.80#ibcon#first serial, iclass 24, count 2 2006.257.07:47:39.80#ibcon#enter sib2, iclass 24, count 2 2006.257.07:47:39.80#ibcon#flushed, iclass 24, count 2 2006.257.07:47:39.80#ibcon#about to write, iclass 24, count 2 2006.257.07:47:39.80#ibcon#wrote, iclass 24, count 2 2006.257.07:47:39.80#ibcon#about to read 3, iclass 24, count 2 2006.257.07:47:39.82#ibcon#read 3, iclass 24, count 2 2006.257.07:47:39.82#ibcon#about to read 4, iclass 24, count 2 2006.257.07:47:39.82#ibcon#read 4, iclass 24, count 2 2006.257.07:47:39.82#ibcon#about to read 5, iclass 24, count 2 2006.257.07:47:39.82#ibcon#read 5, iclass 24, count 2 2006.257.07:47:39.82#ibcon#about to read 6, iclass 24, count 2 2006.257.07:47:39.82#ibcon#read 6, iclass 24, count 2 2006.257.07:47:39.82#ibcon#end of sib2, iclass 24, count 2 2006.257.07:47:39.82#ibcon#*mode == 0, iclass 24, count 2 2006.257.07:47:39.82#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.07:47:39.82#ibcon#[27=AT06-04\r\n] 2006.257.07:47:39.82#ibcon#*before write, iclass 24, count 2 2006.257.07:47:39.82#ibcon#enter sib2, iclass 24, count 2 2006.257.07:47:39.82#ibcon#flushed, iclass 24, count 2 2006.257.07:47:39.82#ibcon#about to write, iclass 24, count 2 2006.257.07:47:39.82#ibcon#wrote, iclass 24, count 2 2006.257.07:47:39.82#ibcon#about to read 3, iclass 24, count 2 2006.257.07:47:39.85#ibcon#read 3, iclass 24, count 2 2006.257.07:47:39.85#ibcon#about to read 4, iclass 24, count 2 2006.257.07:47:39.85#ibcon#read 4, iclass 24, count 2 2006.257.07:47:39.85#ibcon#about to read 5, iclass 24, count 2 2006.257.07:47:39.85#ibcon#read 5, iclass 24, count 2 2006.257.07:47:39.85#ibcon#about to read 6, iclass 24, count 2 2006.257.07:47:39.85#ibcon#read 6, iclass 24, count 2 2006.257.07:47:39.85#ibcon#end of sib2, iclass 24, count 2 2006.257.07:47:39.85#ibcon#*after write, iclass 24, count 2 2006.257.07:47:39.85#ibcon#*before return 0, iclass 24, count 2 2006.257.07:47:39.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:39.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.07:47:39.85#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.07:47:39.85#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:39.85#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:39.97#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:39.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:39.97#ibcon#enter wrdev, iclass 24, count 0 2006.257.07:47:39.97#ibcon#first serial, iclass 24, count 0 2006.257.07:47:39.97#ibcon#enter sib2, iclass 24, count 0 2006.257.07:47:39.97#ibcon#flushed, iclass 24, count 0 2006.257.07:47:39.97#ibcon#about to write, iclass 24, count 0 2006.257.07:47:39.97#ibcon#wrote, iclass 24, count 0 2006.257.07:47:39.97#ibcon#about to read 3, iclass 24, count 0 2006.257.07:47:39.99#ibcon#read 3, iclass 24, count 0 2006.257.07:47:39.99#ibcon#about to read 4, iclass 24, count 0 2006.257.07:47:39.99#ibcon#read 4, iclass 24, count 0 2006.257.07:47:39.99#ibcon#about to read 5, iclass 24, count 0 2006.257.07:47:39.99#ibcon#read 5, iclass 24, count 0 2006.257.07:47:39.99#ibcon#about to read 6, iclass 24, count 0 2006.257.07:47:39.99#ibcon#read 6, iclass 24, count 0 2006.257.07:47:39.99#ibcon#end of sib2, iclass 24, count 0 2006.257.07:47:39.99#ibcon#*mode == 0, iclass 24, count 0 2006.257.07:47:39.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.07:47:39.99#ibcon#[27=USB\r\n] 2006.257.07:47:39.99#ibcon#*before write, iclass 24, count 0 2006.257.07:47:39.99#ibcon#enter sib2, iclass 24, count 0 2006.257.07:47:39.99#ibcon#flushed, iclass 24, count 0 2006.257.07:47:39.99#ibcon#about to write, iclass 24, count 0 2006.257.07:47:39.99#ibcon#wrote, iclass 24, count 0 2006.257.07:47:39.99#ibcon#about to read 3, iclass 24, count 0 2006.257.07:47:40.02#ibcon#read 3, iclass 24, count 0 2006.257.07:47:40.02#ibcon#about to read 4, iclass 24, count 0 2006.257.07:47:40.02#ibcon#read 4, iclass 24, count 0 2006.257.07:47:40.02#ibcon#about to read 5, iclass 24, count 0 2006.257.07:47:40.02#ibcon#read 5, iclass 24, count 0 2006.257.07:47:40.02#ibcon#about to read 6, iclass 24, count 0 2006.257.07:47:40.02#ibcon#read 6, iclass 24, count 0 2006.257.07:47:40.02#ibcon#end of sib2, iclass 24, count 0 2006.257.07:47:40.02#ibcon#*after write, iclass 24, count 0 2006.257.07:47:40.02#ibcon#*before return 0, iclass 24, count 0 2006.257.07:47:40.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:40.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.07:47:40.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.07:47:40.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.07:47:40.02$vck44/vblo=7,734.99 2006.257.07:47:40.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.07:47:40.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.07:47:40.02#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:40.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:40.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:40.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:40.02#ibcon#enter wrdev, iclass 26, count 0 2006.257.07:47:40.02#ibcon#first serial, iclass 26, count 0 2006.257.07:47:40.02#ibcon#enter sib2, iclass 26, count 0 2006.257.07:47:40.02#ibcon#flushed, iclass 26, count 0 2006.257.07:47:40.02#ibcon#about to write, iclass 26, count 0 2006.257.07:47:40.02#ibcon#wrote, iclass 26, count 0 2006.257.07:47:40.02#ibcon#about to read 3, iclass 26, count 0 2006.257.07:47:40.04#ibcon#read 3, iclass 26, count 0 2006.257.07:47:40.04#ibcon#about to read 4, iclass 26, count 0 2006.257.07:47:40.04#ibcon#read 4, iclass 26, count 0 2006.257.07:47:40.04#ibcon#about to read 5, iclass 26, count 0 2006.257.07:47:40.04#ibcon#read 5, iclass 26, count 0 2006.257.07:47:40.04#ibcon#about to read 6, iclass 26, count 0 2006.257.07:47:40.04#ibcon#read 6, iclass 26, count 0 2006.257.07:47:40.04#ibcon#end of sib2, iclass 26, count 0 2006.257.07:47:40.04#ibcon#*mode == 0, iclass 26, count 0 2006.257.07:47:40.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.07:47:40.04#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.07:47:40.04#ibcon#*before write, iclass 26, count 0 2006.257.07:47:40.04#ibcon#enter sib2, iclass 26, count 0 2006.257.07:47:40.04#ibcon#flushed, iclass 26, count 0 2006.257.07:47:40.04#ibcon#about to write, iclass 26, count 0 2006.257.07:47:40.04#ibcon#wrote, iclass 26, count 0 2006.257.07:47:40.04#ibcon#about to read 3, iclass 26, count 0 2006.257.07:47:40.08#ibcon#read 3, iclass 26, count 0 2006.257.07:47:40.08#ibcon#about to read 4, iclass 26, count 0 2006.257.07:47:40.08#ibcon#read 4, iclass 26, count 0 2006.257.07:47:40.08#ibcon#about to read 5, iclass 26, count 0 2006.257.07:47:40.08#ibcon#read 5, iclass 26, count 0 2006.257.07:47:40.08#ibcon#about to read 6, iclass 26, count 0 2006.257.07:47:40.08#ibcon#read 6, iclass 26, count 0 2006.257.07:47:40.08#ibcon#end of sib2, iclass 26, count 0 2006.257.07:47:40.08#ibcon#*after write, iclass 26, count 0 2006.257.07:47:40.08#ibcon#*before return 0, iclass 26, count 0 2006.257.07:47:40.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:40.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.07:47:40.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.07:47:40.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.07:47:40.08$vck44/vb=7,4 2006.257.07:47:40.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.07:47:40.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.07:47:40.08#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:40.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:40.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:40.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:40.14#ibcon#enter wrdev, iclass 28, count 2 2006.257.07:47:40.14#ibcon#first serial, iclass 28, count 2 2006.257.07:47:40.14#ibcon#enter sib2, iclass 28, count 2 2006.257.07:47:40.14#ibcon#flushed, iclass 28, count 2 2006.257.07:47:40.14#ibcon#about to write, iclass 28, count 2 2006.257.07:47:40.14#ibcon#wrote, iclass 28, count 2 2006.257.07:47:40.14#ibcon#about to read 3, iclass 28, count 2 2006.257.07:47:40.16#ibcon#read 3, iclass 28, count 2 2006.257.07:47:40.16#ibcon#about to read 4, iclass 28, count 2 2006.257.07:47:40.16#ibcon#read 4, iclass 28, count 2 2006.257.07:47:40.16#ibcon#about to read 5, iclass 28, count 2 2006.257.07:47:40.16#ibcon#read 5, iclass 28, count 2 2006.257.07:47:40.16#ibcon#about to read 6, iclass 28, count 2 2006.257.07:47:40.16#ibcon#read 6, iclass 28, count 2 2006.257.07:47:40.16#ibcon#end of sib2, iclass 28, count 2 2006.257.07:47:40.16#ibcon#*mode == 0, iclass 28, count 2 2006.257.07:47:40.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.07:47:40.16#ibcon#[27=AT07-04\r\n] 2006.257.07:47:40.16#ibcon#*before write, iclass 28, count 2 2006.257.07:47:40.16#ibcon#enter sib2, iclass 28, count 2 2006.257.07:47:40.16#ibcon#flushed, iclass 28, count 2 2006.257.07:47:40.16#ibcon#about to write, iclass 28, count 2 2006.257.07:47:40.16#ibcon#wrote, iclass 28, count 2 2006.257.07:47:40.16#ibcon#about to read 3, iclass 28, count 2 2006.257.07:47:40.19#ibcon#read 3, iclass 28, count 2 2006.257.07:47:40.19#ibcon#about to read 4, iclass 28, count 2 2006.257.07:47:40.19#ibcon#read 4, iclass 28, count 2 2006.257.07:47:40.19#ibcon#about to read 5, iclass 28, count 2 2006.257.07:47:40.19#ibcon#read 5, iclass 28, count 2 2006.257.07:47:40.19#ibcon#about to read 6, iclass 28, count 2 2006.257.07:47:40.19#ibcon#read 6, iclass 28, count 2 2006.257.07:47:40.19#ibcon#end of sib2, iclass 28, count 2 2006.257.07:47:40.19#ibcon#*after write, iclass 28, count 2 2006.257.07:47:40.19#ibcon#*before return 0, iclass 28, count 2 2006.257.07:47:40.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:40.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.07:47:40.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.07:47:40.19#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:40.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:40.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:40.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:40.31#ibcon#enter wrdev, iclass 28, count 0 2006.257.07:47:40.31#ibcon#first serial, iclass 28, count 0 2006.257.07:47:40.31#ibcon#enter sib2, iclass 28, count 0 2006.257.07:47:40.31#ibcon#flushed, iclass 28, count 0 2006.257.07:47:40.31#ibcon#about to write, iclass 28, count 0 2006.257.07:47:40.31#ibcon#wrote, iclass 28, count 0 2006.257.07:47:40.31#ibcon#about to read 3, iclass 28, count 0 2006.257.07:47:40.33#ibcon#read 3, iclass 28, count 0 2006.257.07:47:40.33#ibcon#about to read 4, iclass 28, count 0 2006.257.07:47:40.33#ibcon#read 4, iclass 28, count 0 2006.257.07:47:40.33#ibcon#about to read 5, iclass 28, count 0 2006.257.07:47:40.33#ibcon#read 5, iclass 28, count 0 2006.257.07:47:40.33#ibcon#about to read 6, iclass 28, count 0 2006.257.07:47:40.33#ibcon#read 6, iclass 28, count 0 2006.257.07:47:40.33#ibcon#end of sib2, iclass 28, count 0 2006.257.07:47:40.33#ibcon#*mode == 0, iclass 28, count 0 2006.257.07:47:40.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.07:47:40.33#ibcon#[27=USB\r\n] 2006.257.07:47:40.33#ibcon#*before write, iclass 28, count 0 2006.257.07:47:40.33#ibcon#enter sib2, iclass 28, count 0 2006.257.07:47:40.33#ibcon#flushed, iclass 28, count 0 2006.257.07:47:40.33#ibcon#about to write, iclass 28, count 0 2006.257.07:47:40.33#ibcon#wrote, iclass 28, count 0 2006.257.07:47:40.33#ibcon#about to read 3, iclass 28, count 0 2006.257.07:47:40.36#ibcon#read 3, iclass 28, count 0 2006.257.07:47:40.36#ibcon#about to read 4, iclass 28, count 0 2006.257.07:47:40.36#ibcon#read 4, iclass 28, count 0 2006.257.07:47:40.36#ibcon#about to read 5, iclass 28, count 0 2006.257.07:47:40.36#ibcon#read 5, iclass 28, count 0 2006.257.07:47:40.36#ibcon#about to read 6, iclass 28, count 0 2006.257.07:47:40.36#ibcon#read 6, iclass 28, count 0 2006.257.07:47:40.36#ibcon#end of sib2, iclass 28, count 0 2006.257.07:47:40.36#ibcon#*after write, iclass 28, count 0 2006.257.07:47:40.36#ibcon#*before return 0, iclass 28, count 0 2006.257.07:47:40.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:40.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.07:47:40.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.07:47:40.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.07:47:40.36$vck44/vblo=8,744.99 2006.257.07:47:40.36#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.07:47:40.36#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.07:47:40.36#ibcon#ireg 17 cls_cnt 0 2006.257.07:47:40.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:40.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:40.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:40.36#ibcon#enter wrdev, iclass 30, count 0 2006.257.07:47:40.36#ibcon#first serial, iclass 30, count 0 2006.257.07:47:40.36#ibcon#enter sib2, iclass 30, count 0 2006.257.07:47:40.36#ibcon#flushed, iclass 30, count 0 2006.257.07:47:40.36#ibcon#about to write, iclass 30, count 0 2006.257.07:47:40.36#ibcon#wrote, iclass 30, count 0 2006.257.07:47:40.36#ibcon#about to read 3, iclass 30, count 0 2006.257.07:47:40.38#ibcon#read 3, iclass 30, count 0 2006.257.07:47:40.38#ibcon#about to read 4, iclass 30, count 0 2006.257.07:47:40.38#ibcon#read 4, iclass 30, count 0 2006.257.07:47:40.38#ibcon#about to read 5, iclass 30, count 0 2006.257.07:47:40.38#ibcon#read 5, iclass 30, count 0 2006.257.07:47:40.38#ibcon#about to read 6, iclass 30, count 0 2006.257.07:47:40.38#ibcon#read 6, iclass 30, count 0 2006.257.07:47:40.38#ibcon#end of sib2, iclass 30, count 0 2006.257.07:47:40.38#ibcon#*mode == 0, iclass 30, count 0 2006.257.07:47:40.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.07:47:40.38#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.07:47:40.38#ibcon#*before write, iclass 30, count 0 2006.257.07:47:40.38#ibcon#enter sib2, iclass 30, count 0 2006.257.07:47:40.38#ibcon#flushed, iclass 30, count 0 2006.257.07:47:40.38#ibcon#about to write, iclass 30, count 0 2006.257.07:47:40.38#ibcon#wrote, iclass 30, count 0 2006.257.07:47:40.38#ibcon#about to read 3, iclass 30, count 0 2006.257.07:47:40.42#ibcon#read 3, iclass 30, count 0 2006.257.07:47:40.42#ibcon#about to read 4, iclass 30, count 0 2006.257.07:47:40.42#ibcon#read 4, iclass 30, count 0 2006.257.07:47:40.42#ibcon#about to read 5, iclass 30, count 0 2006.257.07:47:40.42#ibcon#read 5, iclass 30, count 0 2006.257.07:47:40.42#ibcon#about to read 6, iclass 30, count 0 2006.257.07:47:40.42#ibcon#read 6, iclass 30, count 0 2006.257.07:47:40.42#ibcon#end of sib2, iclass 30, count 0 2006.257.07:47:40.42#ibcon#*after write, iclass 30, count 0 2006.257.07:47:40.42#ibcon#*before return 0, iclass 30, count 0 2006.257.07:47:40.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:40.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.07:47:40.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.07:47:40.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.07:47:40.42$vck44/vb=8,4 2006.257.07:47:40.42#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.07:47:40.42#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.07:47:40.42#ibcon#ireg 11 cls_cnt 2 2006.257.07:47:40.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:40.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:40.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:40.48#ibcon#enter wrdev, iclass 32, count 2 2006.257.07:47:40.48#ibcon#first serial, iclass 32, count 2 2006.257.07:47:40.48#ibcon#enter sib2, iclass 32, count 2 2006.257.07:47:40.48#ibcon#flushed, iclass 32, count 2 2006.257.07:47:40.48#ibcon#about to write, iclass 32, count 2 2006.257.07:47:40.48#ibcon#wrote, iclass 32, count 2 2006.257.07:47:40.48#ibcon#about to read 3, iclass 32, count 2 2006.257.07:47:40.50#ibcon#read 3, iclass 32, count 2 2006.257.07:47:40.50#ibcon#about to read 4, iclass 32, count 2 2006.257.07:47:40.50#ibcon#read 4, iclass 32, count 2 2006.257.07:47:40.50#ibcon#about to read 5, iclass 32, count 2 2006.257.07:47:40.50#ibcon#read 5, iclass 32, count 2 2006.257.07:47:40.50#ibcon#about to read 6, iclass 32, count 2 2006.257.07:47:40.50#ibcon#read 6, iclass 32, count 2 2006.257.07:47:40.50#ibcon#end of sib2, iclass 32, count 2 2006.257.07:47:40.50#ibcon#*mode == 0, iclass 32, count 2 2006.257.07:47:40.50#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.07:47:40.50#ibcon#[27=AT08-04\r\n] 2006.257.07:47:40.50#ibcon#*before write, iclass 32, count 2 2006.257.07:47:40.50#ibcon#enter sib2, iclass 32, count 2 2006.257.07:47:40.50#ibcon#flushed, iclass 32, count 2 2006.257.07:47:40.50#ibcon#about to write, iclass 32, count 2 2006.257.07:47:40.50#ibcon#wrote, iclass 32, count 2 2006.257.07:47:40.50#ibcon#about to read 3, iclass 32, count 2 2006.257.07:47:40.53#ibcon#read 3, iclass 32, count 2 2006.257.07:47:40.53#ibcon#about to read 4, iclass 32, count 2 2006.257.07:47:40.53#ibcon#read 4, iclass 32, count 2 2006.257.07:47:40.53#ibcon#about to read 5, iclass 32, count 2 2006.257.07:47:40.53#ibcon#read 5, iclass 32, count 2 2006.257.07:47:40.53#ibcon#about to read 6, iclass 32, count 2 2006.257.07:47:40.53#ibcon#read 6, iclass 32, count 2 2006.257.07:47:40.53#ibcon#end of sib2, iclass 32, count 2 2006.257.07:47:40.53#ibcon#*after write, iclass 32, count 2 2006.257.07:47:40.53#ibcon#*before return 0, iclass 32, count 2 2006.257.07:47:40.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:40.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.07:47:40.53#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.07:47:40.53#ibcon#ireg 7 cls_cnt 0 2006.257.07:47:40.53#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:40.65#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:40.65#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:40.65#ibcon#enter wrdev, iclass 32, count 0 2006.257.07:47:40.65#ibcon#first serial, iclass 32, count 0 2006.257.07:47:40.65#ibcon#enter sib2, iclass 32, count 0 2006.257.07:47:40.65#ibcon#flushed, iclass 32, count 0 2006.257.07:47:40.65#ibcon#about to write, iclass 32, count 0 2006.257.07:47:40.65#ibcon#wrote, iclass 32, count 0 2006.257.07:47:40.65#ibcon#about to read 3, iclass 32, count 0 2006.257.07:47:40.67#ibcon#read 3, iclass 32, count 0 2006.257.07:47:40.67#ibcon#about to read 4, iclass 32, count 0 2006.257.07:47:40.67#ibcon#read 4, iclass 32, count 0 2006.257.07:47:40.67#ibcon#about to read 5, iclass 32, count 0 2006.257.07:47:40.67#ibcon#read 5, iclass 32, count 0 2006.257.07:47:40.67#ibcon#about to read 6, iclass 32, count 0 2006.257.07:47:40.67#ibcon#read 6, iclass 32, count 0 2006.257.07:47:40.67#ibcon#end of sib2, iclass 32, count 0 2006.257.07:47:40.67#ibcon#*mode == 0, iclass 32, count 0 2006.257.07:47:40.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.07:47:40.67#ibcon#[27=USB\r\n] 2006.257.07:47:40.67#ibcon#*before write, iclass 32, count 0 2006.257.07:47:40.67#ibcon#enter sib2, iclass 32, count 0 2006.257.07:47:40.67#ibcon#flushed, iclass 32, count 0 2006.257.07:47:40.67#ibcon#about to write, iclass 32, count 0 2006.257.07:47:40.67#ibcon#wrote, iclass 32, count 0 2006.257.07:47:40.67#ibcon#about to read 3, iclass 32, count 0 2006.257.07:47:40.70#ibcon#read 3, iclass 32, count 0 2006.257.07:47:40.70#ibcon#about to read 4, iclass 32, count 0 2006.257.07:47:40.70#ibcon#read 4, iclass 32, count 0 2006.257.07:47:40.70#ibcon#about to read 5, iclass 32, count 0 2006.257.07:47:40.70#ibcon#read 5, iclass 32, count 0 2006.257.07:47:40.70#ibcon#about to read 6, iclass 32, count 0 2006.257.07:47:40.70#ibcon#read 6, iclass 32, count 0 2006.257.07:47:40.70#ibcon#end of sib2, iclass 32, count 0 2006.257.07:47:40.70#ibcon#*after write, iclass 32, count 0 2006.257.07:47:40.70#ibcon#*before return 0, iclass 32, count 0 2006.257.07:47:40.70#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:40.70#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.07:47:40.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.07:47:40.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.07:47:40.70$vck44/vabw=wide 2006.257.07:47:40.70#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.07:47:40.70#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.07:47:40.70#ibcon#ireg 8 cls_cnt 0 2006.257.07:47:40.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:40.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:40.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:40.70#ibcon#enter wrdev, iclass 34, count 0 2006.257.07:47:40.70#ibcon#first serial, iclass 34, count 0 2006.257.07:47:40.70#ibcon#enter sib2, iclass 34, count 0 2006.257.07:47:40.70#ibcon#flushed, iclass 34, count 0 2006.257.07:47:40.70#ibcon#about to write, iclass 34, count 0 2006.257.07:47:40.70#ibcon#wrote, iclass 34, count 0 2006.257.07:47:40.70#ibcon#about to read 3, iclass 34, count 0 2006.257.07:47:40.72#ibcon#read 3, iclass 34, count 0 2006.257.07:47:40.72#ibcon#about to read 4, iclass 34, count 0 2006.257.07:47:40.72#ibcon#read 4, iclass 34, count 0 2006.257.07:47:40.72#ibcon#about to read 5, iclass 34, count 0 2006.257.07:47:40.72#ibcon#read 5, iclass 34, count 0 2006.257.07:47:40.72#ibcon#about to read 6, iclass 34, count 0 2006.257.07:47:40.72#ibcon#read 6, iclass 34, count 0 2006.257.07:47:40.72#ibcon#end of sib2, iclass 34, count 0 2006.257.07:47:40.72#ibcon#*mode == 0, iclass 34, count 0 2006.257.07:47:40.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.07:47:40.72#ibcon#[25=BW32\r\n] 2006.257.07:47:40.72#ibcon#*before write, iclass 34, count 0 2006.257.07:47:40.72#ibcon#enter sib2, iclass 34, count 0 2006.257.07:47:40.72#ibcon#flushed, iclass 34, count 0 2006.257.07:47:40.72#ibcon#about to write, iclass 34, count 0 2006.257.07:47:40.72#ibcon#wrote, iclass 34, count 0 2006.257.07:47:40.72#ibcon#about to read 3, iclass 34, count 0 2006.257.07:47:40.75#ibcon#read 3, iclass 34, count 0 2006.257.07:47:40.75#ibcon#about to read 4, iclass 34, count 0 2006.257.07:47:40.75#ibcon#read 4, iclass 34, count 0 2006.257.07:47:40.75#ibcon#about to read 5, iclass 34, count 0 2006.257.07:47:40.75#ibcon#read 5, iclass 34, count 0 2006.257.07:47:40.75#ibcon#about to read 6, iclass 34, count 0 2006.257.07:47:40.75#ibcon#read 6, iclass 34, count 0 2006.257.07:47:40.75#ibcon#end of sib2, iclass 34, count 0 2006.257.07:47:40.75#ibcon#*after write, iclass 34, count 0 2006.257.07:47:40.75#ibcon#*before return 0, iclass 34, count 0 2006.257.07:47:40.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:40.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.07:47:40.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.07:47:40.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.07:47:40.75$vck44/vbbw=wide 2006.257.07:47:40.75#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.07:47:40.75#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.07:47:40.75#ibcon#ireg 8 cls_cnt 0 2006.257.07:47:40.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:47:40.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:47:40.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:47:40.82#ibcon#enter wrdev, iclass 36, count 0 2006.257.07:47:40.82#ibcon#first serial, iclass 36, count 0 2006.257.07:47:40.82#ibcon#enter sib2, iclass 36, count 0 2006.257.07:47:40.82#ibcon#flushed, iclass 36, count 0 2006.257.07:47:40.82#ibcon#about to write, iclass 36, count 0 2006.257.07:47:40.82#ibcon#wrote, iclass 36, count 0 2006.257.07:47:40.82#ibcon#about to read 3, iclass 36, count 0 2006.257.07:47:40.84#ibcon#read 3, iclass 36, count 0 2006.257.07:47:40.84#ibcon#about to read 4, iclass 36, count 0 2006.257.07:47:40.84#ibcon#read 4, iclass 36, count 0 2006.257.07:47:40.84#ibcon#about to read 5, iclass 36, count 0 2006.257.07:47:40.84#ibcon#read 5, iclass 36, count 0 2006.257.07:47:40.84#ibcon#about to read 6, iclass 36, count 0 2006.257.07:47:40.84#ibcon#read 6, iclass 36, count 0 2006.257.07:47:40.84#ibcon#end of sib2, iclass 36, count 0 2006.257.07:47:40.84#ibcon#*mode == 0, iclass 36, count 0 2006.257.07:47:40.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.07:47:40.84#ibcon#[27=BW32\r\n] 2006.257.07:47:40.84#ibcon#*before write, iclass 36, count 0 2006.257.07:47:40.84#ibcon#enter sib2, iclass 36, count 0 2006.257.07:47:40.84#ibcon#flushed, iclass 36, count 0 2006.257.07:47:40.84#ibcon#about to write, iclass 36, count 0 2006.257.07:47:40.84#ibcon#wrote, iclass 36, count 0 2006.257.07:47:40.84#ibcon#about to read 3, iclass 36, count 0 2006.257.07:47:40.87#ibcon#read 3, iclass 36, count 0 2006.257.07:47:40.87#ibcon#about to read 4, iclass 36, count 0 2006.257.07:47:40.87#ibcon#read 4, iclass 36, count 0 2006.257.07:47:40.87#ibcon#about to read 5, iclass 36, count 0 2006.257.07:47:40.87#ibcon#read 5, iclass 36, count 0 2006.257.07:47:40.87#ibcon#about to read 6, iclass 36, count 0 2006.257.07:47:40.87#ibcon#read 6, iclass 36, count 0 2006.257.07:47:40.87#ibcon#end of sib2, iclass 36, count 0 2006.257.07:47:40.87#ibcon#*after write, iclass 36, count 0 2006.257.07:47:40.87#ibcon#*before return 0, iclass 36, count 0 2006.257.07:47:40.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:47:40.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.07:47:40.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.07:47:40.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.07:47:40.87$setupk4/ifdk4 2006.257.07:47:40.87$ifdk4/lo= 2006.257.07:47:40.87$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.07:47:40.87$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.07:47:40.87$ifdk4/patch= 2006.257.07:47:40.87$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.07:47:40.87$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.07:47:40.87$setupk4/!*+20s 2006.257.07:47:42.30#abcon#<5=/16 1.0 2.5 21.12 871012.8\r\n> 2006.257.07:47:42.32#abcon#{5=INTERFACE CLEAR} 2006.257.07:47:42.38#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:47:52.14#trakl#Source acquired 2006.257.07:47:52.14#flagr#flagr/antenna,acquired 2006.257.07:47:52.47#abcon#<5=/16 1.0 2.5 21.12 871012.8\r\n> 2006.257.07:47:52.49#abcon#{5=INTERFACE CLEAR} 2006.257.07:47:52.55#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:47:55.37$setupk4/"tpicd 2006.257.07:47:55.37$setupk4/echo=off 2006.257.07:47:55.37$setupk4/xlog=off 2006.257.07:47:55.37:!2006.257.07:48:25 2006.257.07:48:25.00:preob 2006.257.07:48:26.14/onsource/TRACKING 2006.257.07:48:26.14:!2006.257.07:48:35 2006.257.07:48:35.00:"tape 2006.257.07:48:35.00:"st=record 2006.257.07:48:35.00:data_valid=on 2006.257.07:48:35.00:midob 2006.257.07:48:35.14/onsource/TRACKING 2006.257.07:48:35.14/wx/21.12,1012.8,87 2006.257.07:48:35.21/cable/+6.4751E-03 2006.257.07:48:36.30/va/01,08,usb,yes,32,34 2006.257.07:48:36.30/va/02,07,usb,yes,34,35 2006.257.07:48:36.30/va/03,08,usb,yes,31,33 2006.257.07:48:36.30/va/04,07,usb,yes,35,37 2006.257.07:48:36.30/va/05,04,usb,yes,32,32 2006.257.07:48:36.30/va/06,04,usb,yes,35,35 2006.257.07:48:36.30/va/07,04,usb,yes,36,37 2006.257.07:48:36.30/va/08,04,usb,yes,30,37 2006.257.07:48:36.53/valo/01,524.99,yes,locked 2006.257.07:48:36.53/valo/02,534.99,yes,locked 2006.257.07:48:36.53/valo/03,564.99,yes,locked 2006.257.07:48:36.53/valo/04,624.99,yes,locked 2006.257.07:48:36.53/valo/05,734.99,yes,locked 2006.257.07:48:36.53/valo/06,814.99,yes,locked 2006.257.07:48:36.53/valo/07,864.99,yes,locked 2006.257.07:48:36.53/valo/08,884.99,yes,locked 2006.257.07:48:37.62/vb/01,04,usb,yes,31,29 2006.257.07:48:37.62/vb/02,05,usb,yes,30,29 2006.257.07:48:37.62/vb/03,04,usb,yes,31,34 2006.257.07:48:37.62/vb/04,05,usb,yes,31,30 2006.257.07:48:37.62/vb/05,04,usb,yes,27,30 2006.257.07:48:37.62/vb/06,04,usb,yes,32,28 2006.257.07:48:37.62/vb/07,04,usb,yes,32,32 2006.257.07:48:37.62/vb/08,04,usb,yes,29,33 2006.257.07:48:37.86/vblo/01,629.99,yes,locked 2006.257.07:48:37.86/vblo/02,634.99,yes,locked 2006.257.07:48:37.86/vblo/03,649.99,yes,locked 2006.257.07:48:37.86/vblo/04,679.99,yes,locked 2006.257.07:48:37.86/vblo/05,709.99,yes,locked 2006.257.07:48:37.86/vblo/06,719.99,yes,locked 2006.257.07:48:37.86/vblo/07,734.99,yes,locked 2006.257.07:48:37.86/vblo/08,744.99,yes,locked 2006.257.07:48:38.01/vabw/8 2006.257.07:48:38.16/vbbw/8 2006.257.07:48:38.25/xfe/off,on,14.7 2006.257.07:48:38.63/ifatt/23,28,28,28 2006.257.07:48:39.08/fmout-gps/S +4.51E-07 2006.257.07:48:39.12:!2006.257.07:51:35 2006.257.07:51:35.02:data_valid=off 2006.257.07:51:35.02:"et 2006.257.07:51:35.02:!+3s 2006.257.07:51:38.04:"tape 2006.257.07:51:38.04:postob 2006.257.07:51:38.19/cable/+6.4747E-03 2006.257.07:51:38.20/wx/21.11,1012.8,87 2006.257.07:51:38.25/fmout-gps/S +4.51E-07 2006.257.07:51:38.26:scan_name=257-0801,jd0609,40 2006.257.07:51:38.26:source=3c345,164258.81,394837.0,2000.0,neutral 2006.257.07:51:39.13#flagr#flagr/antenna,new-source 2006.257.07:51:39.15:checkk5 2006.257.07:51:39.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.07:51:39.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.07:51:40.45/chk_autoobs//k5ts3/ autoobs is running! 2006.257.07:51:40.90/chk_autoobs//k5ts4/ autoobs is running! 2006.257.07:51:41.30/chk_obsdata//k5ts1/T2570748??a.dat file size is correct (nominal:720MB, actual:720MB). 2006.257.07:51:41.71/chk_obsdata//k5ts2/T2570748??b.dat file size is correct (nominal:720MB, actual:720MB). 2006.257.07:51:42.13/chk_obsdata//k5ts3/T2570748??c.dat file size is correct (nominal:720MB, actual:720MB). 2006.257.07:51:42.49/chk_obsdata//k5ts4/T2570748??d.dat file size is correct (nominal:720MB, actual:720MB). 2006.257.07:51:43.22/k5log//k5ts1_log_newline 2006.257.07:51:43.92/k5log//k5ts2_log_newline 2006.257.07:51:44.66/k5log//k5ts3_log_newline 2006.257.07:51:45.38/k5log//k5ts4_log_newline 2006.257.07:51:45.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.07:51:45.40:setupk4=1 2006.257.07:51:45.40$setupk4/echo=on 2006.257.07:51:45.40$setupk4/pcalon 2006.257.07:51:45.40$pcalon/"no phase cal control is implemented here 2006.257.07:51:45.40$setupk4/"tpicd=stop 2006.257.07:51:45.40$setupk4/"rec=synch_on 2006.257.07:51:45.40$setupk4/"rec_mode=128 2006.257.07:51:45.40$setupk4/!* 2006.257.07:51:45.40$setupk4/recpk4 2006.257.07:51:45.40$recpk4/recpatch= 2006.257.07:51:45.41$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.07:51:45.41$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.07:51:45.41$setupk4/vck44 2006.257.07:51:45.41$vck44/valo=1,524.99 2006.257.07:51:45.41#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.07:51:45.41#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.07:51:45.41#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:45.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:45.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:45.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:45.41#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:51:45.41#ibcon#first serial, iclass 29, count 0 2006.257.07:51:45.41#ibcon#enter sib2, iclass 29, count 0 2006.257.07:51:45.41#ibcon#flushed, iclass 29, count 0 2006.257.07:51:45.41#ibcon#about to write, iclass 29, count 0 2006.257.07:51:45.41#ibcon#wrote, iclass 29, count 0 2006.257.07:51:45.41#ibcon#about to read 3, iclass 29, count 0 2006.257.07:51:45.42#ibcon#read 3, iclass 29, count 0 2006.257.07:51:45.42#ibcon#about to read 4, iclass 29, count 0 2006.257.07:51:45.42#ibcon#read 4, iclass 29, count 0 2006.257.07:51:45.42#ibcon#about to read 5, iclass 29, count 0 2006.257.07:51:45.42#ibcon#read 5, iclass 29, count 0 2006.257.07:51:45.42#ibcon#about to read 6, iclass 29, count 0 2006.257.07:51:45.42#ibcon#read 6, iclass 29, count 0 2006.257.07:51:45.42#ibcon#end of sib2, iclass 29, count 0 2006.257.07:51:45.42#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:51:45.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:51:45.42#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.07:51:45.42#ibcon#*before write, iclass 29, count 0 2006.257.07:51:45.42#ibcon#enter sib2, iclass 29, count 0 2006.257.07:51:45.42#ibcon#flushed, iclass 29, count 0 2006.257.07:51:45.42#ibcon#about to write, iclass 29, count 0 2006.257.07:51:45.42#ibcon#wrote, iclass 29, count 0 2006.257.07:51:45.42#ibcon#about to read 3, iclass 29, count 0 2006.257.07:51:45.47#ibcon#read 3, iclass 29, count 0 2006.257.07:51:45.47#ibcon#about to read 4, iclass 29, count 0 2006.257.07:51:45.47#ibcon#read 4, iclass 29, count 0 2006.257.07:51:45.47#ibcon#about to read 5, iclass 29, count 0 2006.257.07:51:45.47#ibcon#read 5, iclass 29, count 0 2006.257.07:51:45.47#ibcon#about to read 6, iclass 29, count 0 2006.257.07:51:45.47#ibcon#read 6, iclass 29, count 0 2006.257.07:51:45.47#ibcon#end of sib2, iclass 29, count 0 2006.257.07:51:45.47#ibcon#*after write, iclass 29, count 0 2006.257.07:51:45.47#ibcon#*before return 0, iclass 29, count 0 2006.257.07:51:45.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:45.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:45.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:51:45.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:51:45.48$vck44/va=1,8 2006.257.07:51:45.48#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.07:51:45.48#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.07:51:45.48#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:45.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:45.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:45.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:45.48#ibcon#enter wrdev, iclass 31, count 2 2006.257.07:51:45.48#ibcon#first serial, iclass 31, count 2 2006.257.07:51:45.48#ibcon#enter sib2, iclass 31, count 2 2006.257.07:51:45.48#ibcon#flushed, iclass 31, count 2 2006.257.07:51:45.48#ibcon#about to write, iclass 31, count 2 2006.257.07:51:45.48#ibcon#wrote, iclass 31, count 2 2006.257.07:51:45.48#ibcon#about to read 3, iclass 31, count 2 2006.257.07:51:45.49#ibcon#read 3, iclass 31, count 2 2006.257.07:51:45.49#ibcon#about to read 4, iclass 31, count 2 2006.257.07:51:45.49#ibcon#read 4, iclass 31, count 2 2006.257.07:51:45.49#ibcon#about to read 5, iclass 31, count 2 2006.257.07:51:45.49#ibcon#read 5, iclass 31, count 2 2006.257.07:51:45.49#ibcon#about to read 6, iclass 31, count 2 2006.257.07:51:45.49#ibcon#read 6, iclass 31, count 2 2006.257.07:51:45.49#ibcon#end of sib2, iclass 31, count 2 2006.257.07:51:45.49#ibcon#*mode == 0, iclass 31, count 2 2006.257.07:51:45.49#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.07:51:45.49#ibcon#[25=AT01-08\r\n] 2006.257.07:51:45.49#ibcon#*before write, iclass 31, count 2 2006.257.07:51:45.49#ibcon#enter sib2, iclass 31, count 2 2006.257.07:51:45.49#ibcon#flushed, iclass 31, count 2 2006.257.07:51:45.49#ibcon#about to write, iclass 31, count 2 2006.257.07:51:45.49#ibcon#wrote, iclass 31, count 2 2006.257.07:51:45.49#ibcon#about to read 3, iclass 31, count 2 2006.257.07:51:45.52#ibcon#read 3, iclass 31, count 2 2006.257.07:51:45.52#ibcon#about to read 4, iclass 31, count 2 2006.257.07:51:45.52#ibcon#read 4, iclass 31, count 2 2006.257.07:51:45.52#ibcon#about to read 5, iclass 31, count 2 2006.257.07:51:45.52#ibcon#read 5, iclass 31, count 2 2006.257.07:51:45.52#ibcon#about to read 6, iclass 31, count 2 2006.257.07:51:45.52#ibcon#read 6, iclass 31, count 2 2006.257.07:51:45.52#ibcon#end of sib2, iclass 31, count 2 2006.257.07:51:45.52#ibcon#*after write, iclass 31, count 2 2006.257.07:51:45.52#ibcon#*before return 0, iclass 31, count 2 2006.257.07:51:45.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:45.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:45.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.07:51:45.52#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:45.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:45.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:45.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:45.64#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:51:45.64#ibcon#first serial, iclass 31, count 0 2006.257.07:51:45.64#ibcon#enter sib2, iclass 31, count 0 2006.257.07:51:45.64#ibcon#flushed, iclass 31, count 0 2006.257.07:51:45.64#ibcon#about to write, iclass 31, count 0 2006.257.07:51:45.64#ibcon#wrote, iclass 31, count 0 2006.257.07:51:45.64#ibcon#about to read 3, iclass 31, count 0 2006.257.07:51:45.66#ibcon#read 3, iclass 31, count 0 2006.257.07:51:45.66#ibcon#about to read 4, iclass 31, count 0 2006.257.07:51:45.66#ibcon#read 4, iclass 31, count 0 2006.257.07:51:45.66#ibcon#about to read 5, iclass 31, count 0 2006.257.07:51:45.66#ibcon#read 5, iclass 31, count 0 2006.257.07:51:45.66#ibcon#about to read 6, iclass 31, count 0 2006.257.07:51:45.66#ibcon#read 6, iclass 31, count 0 2006.257.07:51:45.66#ibcon#end of sib2, iclass 31, count 0 2006.257.07:51:45.66#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:51:45.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:51:45.66#ibcon#[25=USB\r\n] 2006.257.07:51:45.66#ibcon#*before write, iclass 31, count 0 2006.257.07:51:45.66#ibcon#enter sib2, iclass 31, count 0 2006.257.07:51:45.66#ibcon#flushed, iclass 31, count 0 2006.257.07:51:45.66#ibcon#about to write, iclass 31, count 0 2006.257.07:51:45.66#ibcon#wrote, iclass 31, count 0 2006.257.07:51:45.66#ibcon#about to read 3, iclass 31, count 0 2006.257.07:51:45.69#ibcon#read 3, iclass 31, count 0 2006.257.07:51:45.69#ibcon#about to read 4, iclass 31, count 0 2006.257.07:51:45.69#ibcon#read 4, iclass 31, count 0 2006.257.07:51:45.69#ibcon#about to read 5, iclass 31, count 0 2006.257.07:51:45.69#ibcon#read 5, iclass 31, count 0 2006.257.07:51:45.69#ibcon#about to read 6, iclass 31, count 0 2006.257.07:51:45.69#ibcon#read 6, iclass 31, count 0 2006.257.07:51:45.69#ibcon#end of sib2, iclass 31, count 0 2006.257.07:51:45.69#ibcon#*after write, iclass 31, count 0 2006.257.07:51:45.69#ibcon#*before return 0, iclass 31, count 0 2006.257.07:51:45.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:45.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:45.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:51:45.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:51:45.70$vck44/valo=2,534.99 2006.257.07:51:45.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.07:51:45.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.07:51:45.70#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:45.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:45.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:45.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:45.70#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:51:45.70#ibcon#first serial, iclass 33, count 0 2006.257.07:51:45.70#ibcon#enter sib2, iclass 33, count 0 2006.257.07:51:45.70#ibcon#flushed, iclass 33, count 0 2006.257.07:51:45.70#ibcon#about to write, iclass 33, count 0 2006.257.07:51:45.70#ibcon#wrote, iclass 33, count 0 2006.257.07:51:45.70#ibcon#about to read 3, iclass 33, count 0 2006.257.07:51:45.71#ibcon#read 3, iclass 33, count 0 2006.257.07:51:45.71#ibcon#about to read 4, iclass 33, count 0 2006.257.07:51:45.71#ibcon#read 4, iclass 33, count 0 2006.257.07:51:45.71#ibcon#about to read 5, iclass 33, count 0 2006.257.07:51:45.71#ibcon#read 5, iclass 33, count 0 2006.257.07:51:45.71#ibcon#about to read 6, iclass 33, count 0 2006.257.07:51:45.71#ibcon#read 6, iclass 33, count 0 2006.257.07:51:45.71#ibcon#end of sib2, iclass 33, count 0 2006.257.07:51:45.71#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:51:45.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:51:45.71#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.07:51:45.71#ibcon#*before write, iclass 33, count 0 2006.257.07:51:45.71#ibcon#enter sib2, iclass 33, count 0 2006.257.07:51:45.71#ibcon#flushed, iclass 33, count 0 2006.257.07:51:45.71#ibcon#about to write, iclass 33, count 0 2006.257.07:51:45.71#ibcon#wrote, iclass 33, count 0 2006.257.07:51:45.71#ibcon#about to read 3, iclass 33, count 0 2006.257.07:51:45.75#ibcon#read 3, iclass 33, count 0 2006.257.07:51:45.75#ibcon#about to read 4, iclass 33, count 0 2006.257.07:51:45.75#ibcon#read 4, iclass 33, count 0 2006.257.07:51:45.75#ibcon#about to read 5, iclass 33, count 0 2006.257.07:51:45.75#ibcon#read 5, iclass 33, count 0 2006.257.07:51:45.75#ibcon#about to read 6, iclass 33, count 0 2006.257.07:51:45.75#ibcon#read 6, iclass 33, count 0 2006.257.07:51:45.75#ibcon#end of sib2, iclass 33, count 0 2006.257.07:51:45.75#ibcon#*after write, iclass 33, count 0 2006.257.07:51:45.75#ibcon#*before return 0, iclass 33, count 0 2006.257.07:51:45.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:45.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:45.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:51:45.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:51:45.76$vck44/va=2,7 2006.257.07:51:45.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.07:51:45.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.07:51:45.76#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:45.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:45.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:45.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:45.80#ibcon#enter wrdev, iclass 35, count 2 2006.257.07:51:45.80#ibcon#first serial, iclass 35, count 2 2006.257.07:51:45.80#ibcon#enter sib2, iclass 35, count 2 2006.257.07:51:45.80#ibcon#flushed, iclass 35, count 2 2006.257.07:51:45.80#ibcon#about to write, iclass 35, count 2 2006.257.07:51:45.80#ibcon#wrote, iclass 35, count 2 2006.257.07:51:45.80#ibcon#about to read 3, iclass 35, count 2 2006.257.07:51:45.82#ibcon#read 3, iclass 35, count 2 2006.257.07:51:45.82#ibcon#about to read 4, iclass 35, count 2 2006.257.07:51:45.82#ibcon#read 4, iclass 35, count 2 2006.257.07:51:45.82#ibcon#about to read 5, iclass 35, count 2 2006.257.07:51:45.82#ibcon#read 5, iclass 35, count 2 2006.257.07:51:45.82#ibcon#about to read 6, iclass 35, count 2 2006.257.07:51:45.82#ibcon#read 6, iclass 35, count 2 2006.257.07:51:45.82#ibcon#end of sib2, iclass 35, count 2 2006.257.07:51:45.82#ibcon#*mode == 0, iclass 35, count 2 2006.257.07:51:45.82#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.07:51:45.82#ibcon#[25=AT02-07\r\n] 2006.257.07:51:45.82#ibcon#*before write, iclass 35, count 2 2006.257.07:51:45.82#ibcon#enter sib2, iclass 35, count 2 2006.257.07:51:45.82#ibcon#flushed, iclass 35, count 2 2006.257.07:51:45.82#ibcon#about to write, iclass 35, count 2 2006.257.07:51:45.82#ibcon#wrote, iclass 35, count 2 2006.257.07:51:45.82#ibcon#about to read 3, iclass 35, count 2 2006.257.07:51:45.85#ibcon#read 3, iclass 35, count 2 2006.257.07:51:45.85#ibcon#about to read 4, iclass 35, count 2 2006.257.07:51:45.85#ibcon#read 4, iclass 35, count 2 2006.257.07:51:45.85#ibcon#about to read 5, iclass 35, count 2 2006.257.07:51:45.85#ibcon#read 5, iclass 35, count 2 2006.257.07:51:45.85#ibcon#about to read 6, iclass 35, count 2 2006.257.07:51:45.85#ibcon#read 6, iclass 35, count 2 2006.257.07:51:45.85#ibcon#end of sib2, iclass 35, count 2 2006.257.07:51:45.85#ibcon#*after write, iclass 35, count 2 2006.257.07:51:45.85#ibcon#*before return 0, iclass 35, count 2 2006.257.07:51:45.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:45.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:45.85#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.07:51:45.85#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:45.85#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:45.97#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:45.97#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:45.97#ibcon#enter wrdev, iclass 35, count 0 2006.257.07:51:45.97#ibcon#first serial, iclass 35, count 0 2006.257.07:51:45.97#ibcon#enter sib2, iclass 35, count 0 2006.257.07:51:45.97#ibcon#flushed, iclass 35, count 0 2006.257.07:51:45.97#ibcon#about to write, iclass 35, count 0 2006.257.07:51:45.97#ibcon#wrote, iclass 35, count 0 2006.257.07:51:45.97#ibcon#about to read 3, iclass 35, count 0 2006.257.07:51:45.99#ibcon#read 3, iclass 35, count 0 2006.257.07:51:45.99#ibcon#about to read 4, iclass 35, count 0 2006.257.07:51:45.99#ibcon#read 4, iclass 35, count 0 2006.257.07:51:45.99#ibcon#about to read 5, iclass 35, count 0 2006.257.07:51:45.99#ibcon#read 5, iclass 35, count 0 2006.257.07:51:45.99#ibcon#about to read 6, iclass 35, count 0 2006.257.07:51:45.99#ibcon#read 6, iclass 35, count 0 2006.257.07:51:45.99#ibcon#end of sib2, iclass 35, count 0 2006.257.07:51:45.99#ibcon#*mode == 0, iclass 35, count 0 2006.257.07:51:45.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.07:51:45.99#ibcon#[25=USB\r\n] 2006.257.07:51:45.99#ibcon#*before write, iclass 35, count 0 2006.257.07:51:45.99#ibcon#enter sib2, iclass 35, count 0 2006.257.07:51:45.99#ibcon#flushed, iclass 35, count 0 2006.257.07:51:45.99#ibcon#about to write, iclass 35, count 0 2006.257.07:51:45.99#ibcon#wrote, iclass 35, count 0 2006.257.07:51:45.99#ibcon#about to read 3, iclass 35, count 0 2006.257.07:51:46.02#ibcon#read 3, iclass 35, count 0 2006.257.07:51:46.02#ibcon#about to read 4, iclass 35, count 0 2006.257.07:51:46.02#ibcon#read 4, iclass 35, count 0 2006.257.07:51:46.02#ibcon#about to read 5, iclass 35, count 0 2006.257.07:51:46.02#ibcon#read 5, iclass 35, count 0 2006.257.07:51:46.02#ibcon#about to read 6, iclass 35, count 0 2006.257.07:51:46.02#ibcon#read 6, iclass 35, count 0 2006.257.07:51:46.02#ibcon#end of sib2, iclass 35, count 0 2006.257.07:51:46.02#ibcon#*after write, iclass 35, count 0 2006.257.07:51:46.02#ibcon#*before return 0, iclass 35, count 0 2006.257.07:51:46.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:46.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:46.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.07:51:46.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.07:51:46.03$vck44/valo=3,564.99 2006.257.07:51:46.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.07:51:46.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.07:51:46.03#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:46.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:46.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:46.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:46.03#ibcon#enter wrdev, iclass 37, count 0 2006.257.07:51:46.03#ibcon#first serial, iclass 37, count 0 2006.257.07:51:46.03#ibcon#enter sib2, iclass 37, count 0 2006.257.07:51:46.03#ibcon#flushed, iclass 37, count 0 2006.257.07:51:46.03#ibcon#about to write, iclass 37, count 0 2006.257.07:51:46.03#ibcon#wrote, iclass 37, count 0 2006.257.07:51:46.03#ibcon#about to read 3, iclass 37, count 0 2006.257.07:51:46.04#ibcon#read 3, iclass 37, count 0 2006.257.07:51:46.04#ibcon#about to read 4, iclass 37, count 0 2006.257.07:51:46.04#ibcon#read 4, iclass 37, count 0 2006.257.07:51:46.04#ibcon#about to read 5, iclass 37, count 0 2006.257.07:51:46.04#ibcon#read 5, iclass 37, count 0 2006.257.07:51:46.04#ibcon#about to read 6, iclass 37, count 0 2006.257.07:51:46.04#ibcon#read 6, iclass 37, count 0 2006.257.07:51:46.04#ibcon#end of sib2, iclass 37, count 0 2006.257.07:51:46.04#ibcon#*mode == 0, iclass 37, count 0 2006.257.07:51:46.04#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.07:51:46.04#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.07:51:46.04#ibcon#*before write, iclass 37, count 0 2006.257.07:51:46.04#ibcon#enter sib2, iclass 37, count 0 2006.257.07:51:46.04#ibcon#flushed, iclass 37, count 0 2006.257.07:51:46.04#ibcon#about to write, iclass 37, count 0 2006.257.07:51:46.04#ibcon#wrote, iclass 37, count 0 2006.257.07:51:46.04#ibcon#about to read 3, iclass 37, count 0 2006.257.07:51:46.08#ibcon#read 3, iclass 37, count 0 2006.257.07:51:46.08#ibcon#about to read 4, iclass 37, count 0 2006.257.07:51:46.08#ibcon#read 4, iclass 37, count 0 2006.257.07:51:46.08#ibcon#about to read 5, iclass 37, count 0 2006.257.07:51:46.08#ibcon#read 5, iclass 37, count 0 2006.257.07:51:46.08#ibcon#about to read 6, iclass 37, count 0 2006.257.07:51:46.08#ibcon#read 6, iclass 37, count 0 2006.257.07:51:46.08#ibcon#end of sib2, iclass 37, count 0 2006.257.07:51:46.08#ibcon#*after write, iclass 37, count 0 2006.257.07:51:46.08#ibcon#*before return 0, iclass 37, count 0 2006.257.07:51:46.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:46.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:46.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.07:51:46.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.07:51:46.09$vck44/va=3,8 2006.257.07:51:46.09#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.07:51:46.09#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.07:51:46.09#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:46.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:46.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:46.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:46.14#ibcon#enter wrdev, iclass 39, count 2 2006.257.07:51:46.14#ibcon#first serial, iclass 39, count 2 2006.257.07:51:46.14#ibcon#enter sib2, iclass 39, count 2 2006.257.07:51:46.14#ibcon#flushed, iclass 39, count 2 2006.257.07:51:46.14#ibcon#about to write, iclass 39, count 2 2006.257.07:51:46.14#ibcon#wrote, iclass 39, count 2 2006.257.07:51:46.14#ibcon#about to read 3, iclass 39, count 2 2006.257.07:51:46.15#ibcon#read 3, iclass 39, count 2 2006.257.07:51:46.15#ibcon#about to read 4, iclass 39, count 2 2006.257.07:51:46.15#ibcon#read 4, iclass 39, count 2 2006.257.07:51:46.15#ibcon#about to read 5, iclass 39, count 2 2006.257.07:51:46.15#ibcon#read 5, iclass 39, count 2 2006.257.07:51:46.15#ibcon#about to read 6, iclass 39, count 2 2006.257.07:51:46.15#ibcon#read 6, iclass 39, count 2 2006.257.07:51:46.15#ibcon#end of sib2, iclass 39, count 2 2006.257.07:51:46.15#ibcon#*mode == 0, iclass 39, count 2 2006.257.07:51:46.15#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.07:51:46.15#ibcon#[25=AT03-08\r\n] 2006.257.07:51:46.15#ibcon#*before write, iclass 39, count 2 2006.257.07:51:46.15#ibcon#enter sib2, iclass 39, count 2 2006.257.07:51:46.15#ibcon#flushed, iclass 39, count 2 2006.257.07:51:46.15#ibcon#about to write, iclass 39, count 2 2006.257.07:51:46.15#ibcon#wrote, iclass 39, count 2 2006.257.07:51:46.15#ibcon#about to read 3, iclass 39, count 2 2006.257.07:51:46.18#ibcon#read 3, iclass 39, count 2 2006.257.07:51:46.18#ibcon#about to read 4, iclass 39, count 2 2006.257.07:51:46.18#ibcon#read 4, iclass 39, count 2 2006.257.07:51:46.18#ibcon#about to read 5, iclass 39, count 2 2006.257.07:51:46.18#ibcon#read 5, iclass 39, count 2 2006.257.07:51:46.18#ibcon#about to read 6, iclass 39, count 2 2006.257.07:51:46.18#ibcon#read 6, iclass 39, count 2 2006.257.07:51:46.18#ibcon#end of sib2, iclass 39, count 2 2006.257.07:51:46.18#ibcon#*after write, iclass 39, count 2 2006.257.07:51:46.18#ibcon#*before return 0, iclass 39, count 2 2006.257.07:51:46.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:46.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:46.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.07:51:46.18#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:46.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:46.30#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:46.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:46.30#ibcon#enter wrdev, iclass 39, count 0 2006.257.07:51:46.30#ibcon#first serial, iclass 39, count 0 2006.257.07:51:46.30#ibcon#enter sib2, iclass 39, count 0 2006.257.07:51:46.30#ibcon#flushed, iclass 39, count 0 2006.257.07:51:46.30#ibcon#about to write, iclass 39, count 0 2006.257.07:51:46.30#ibcon#wrote, iclass 39, count 0 2006.257.07:51:46.30#ibcon#about to read 3, iclass 39, count 0 2006.257.07:51:46.32#ibcon#read 3, iclass 39, count 0 2006.257.07:51:46.32#ibcon#about to read 4, iclass 39, count 0 2006.257.07:51:46.32#ibcon#read 4, iclass 39, count 0 2006.257.07:51:46.32#ibcon#about to read 5, iclass 39, count 0 2006.257.07:51:46.32#ibcon#read 5, iclass 39, count 0 2006.257.07:51:46.32#ibcon#about to read 6, iclass 39, count 0 2006.257.07:51:46.32#ibcon#read 6, iclass 39, count 0 2006.257.07:51:46.32#ibcon#end of sib2, iclass 39, count 0 2006.257.07:51:46.32#ibcon#*mode == 0, iclass 39, count 0 2006.257.07:51:46.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.07:51:46.32#ibcon#[25=USB\r\n] 2006.257.07:51:46.32#ibcon#*before write, iclass 39, count 0 2006.257.07:51:46.32#ibcon#enter sib2, iclass 39, count 0 2006.257.07:51:46.32#ibcon#flushed, iclass 39, count 0 2006.257.07:51:46.32#ibcon#about to write, iclass 39, count 0 2006.257.07:51:46.32#ibcon#wrote, iclass 39, count 0 2006.257.07:51:46.32#ibcon#about to read 3, iclass 39, count 0 2006.257.07:51:46.35#ibcon#read 3, iclass 39, count 0 2006.257.07:51:46.35#ibcon#about to read 4, iclass 39, count 0 2006.257.07:51:46.35#ibcon#read 4, iclass 39, count 0 2006.257.07:51:46.35#ibcon#about to read 5, iclass 39, count 0 2006.257.07:51:46.35#ibcon#read 5, iclass 39, count 0 2006.257.07:51:46.35#ibcon#about to read 6, iclass 39, count 0 2006.257.07:51:46.35#ibcon#read 6, iclass 39, count 0 2006.257.07:51:46.35#ibcon#end of sib2, iclass 39, count 0 2006.257.07:51:46.35#ibcon#*after write, iclass 39, count 0 2006.257.07:51:46.35#ibcon#*before return 0, iclass 39, count 0 2006.257.07:51:46.35#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:46.35#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:46.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.07:51:46.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.07:51:46.36$vck44/valo=4,624.99 2006.257.07:51:46.36#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.07:51:46.36#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.07:51:46.36#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:46.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:51:46.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:51:46.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:51:46.36#ibcon#enter wrdev, iclass 4, count 0 2006.257.07:51:46.36#ibcon#first serial, iclass 4, count 0 2006.257.07:51:46.36#ibcon#enter sib2, iclass 4, count 0 2006.257.07:51:46.36#ibcon#flushed, iclass 4, count 0 2006.257.07:51:46.36#ibcon#about to write, iclass 4, count 0 2006.257.07:51:46.36#ibcon#wrote, iclass 4, count 0 2006.257.07:51:46.36#ibcon#about to read 3, iclass 4, count 0 2006.257.07:51:46.37#ibcon#read 3, iclass 4, count 0 2006.257.07:51:46.37#ibcon#about to read 4, iclass 4, count 0 2006.257.07:51:46.37#ibcon#read 4, iclass 4, count 0 2006.257.07:51:46.37#ibcon#about to read 5, iclass 4, count 0 2006.257.07:51:46.37#ibcon#read 5, iclass 4, count 0 2006.257.07:51:46.37#ibcon#about to read 6, iclass 4, count 0 2006.257.07:51:46.37#ibcon#read 6, iclass 4, count 0 2006.257.07:51:46.37#ibcon#end of sib2, iclass 4, count 0 2006.257.07:51:46.37#ibcon#*mode == 0, iclass 4, count 0 2006.257.07:51:46.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.07:51:46.37#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.07:51:46.37#ibcon#*before write, iclass 4, count 0 2006.257.07:51:46.37#ibcon#enter sib2, iclass 4, count 0 2006.257.07:51:46.37#ibcon#flushed, iclass 4, count 0 2006.257.07:51:46.37#ibcon#about to write, iclass 4, count 0 2006.257.07:51:46.37#ibcon#wrote, iclass 4, count 0 2006.257.07:51:46.37#ibcon#about to read 3, iclass 4, count 0 2006.257.07:51:46.37#abcon#<5=/15 0.8 2.1 21.11 871012.8\r\n> 2006.257.07:51:46.39#abcon#{5=INTERFACE CLEAR} 2006.257.07:51:46.41#ibcon#read 3, iclass 4, count 0 2006.257.07:51:46.41#ibcon#about to read 4, iclass 4, count 0 2006.257.07:51:46.41#ibcon#read 4, iclass 4, count 0 2006.257.07:51:46.41#ibcon#about to read 5, iclass 4, count 0 2006.257.07:51:46.41#ibcon#read 5, iclass 4, count 0 2006.257.07:51:46.41#ibcon#about to read 6, iclass 4, count 0 2006.257.07:51:46.41#ibcon#read 6, iclass 4, count 0 2006.257.07:51:46.41#ibcon#end of sib2, iclass 4, count 0 2006.257.07:51:46.41#ibcon#*after write, iclass 4, count 0 2006.257.07:51:46.41#ibcon#*before return 0, iclass 4, count 0 2006.257.07:51:46.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:51:46.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.07:51:46.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.07:51:46.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.07:51:46.42$vck44/va=4,7 2006.257.07:51:46.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.07:51:46.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.07:51:46.42#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:46.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:51:46.45#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:51:46.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:51:46.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:51:46.46#ibcon#enter wrdev, iclass 10, count 2 2006.257.07:51:46.46#ibcon#first serial, iclass 10, count 2 2006.257.07:51:46.46#ibcon#enter sib2, iclass 10, count 2 2006.257.07:51:46.46#ibcon#flushed, iclass 10, count 2 2006.257.07:51:46.46#ibcon#about to write, iclass 10, count 2 2006.257.07:51:46.46#ibcon#wrote, iclass 10, count 2 2006.257.07:51:46.46#ibcon#about to read 3, iclass 10, count 2 2006.257.07:51:46.48#ibcon#read 3, iclass 10, count 2 2006.257.07:51:46.48#ibcon#about to read 4, iclass 10, count 2 2006.257.07:51:46.48#ibcon#read 4, iclass 10, count 2 2006.257.07:51:46.48#ibcon#about to read 5, iclass 10, count 2 2006.257.07:51:46.48#ibcon#read 5, iclass 10, count 2 2006.257.07:51:46.48#ibcon#about to read 6, iclass 10, count 2 2006.257.07:51:46.48#ibcon#read 6, iclass 10, count 2 2006.257.07:51:46.48#ibcon#end of sib2, iclass 10, count 2 2006.257.07:51:46.48#ibcon#*mode == 0, iclass 10, count 2 2006.257.07:51:46.48#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.07:51:46.48#ibcon#[25=AT04-07\r\n] 2006.257.07:51:46.48#ibcon#*before write, iclass 10, count 2 2006.257.07:51:46.48#ibcon#enter sib2, iclass 10, count 2 2006.257.07:51:46.48#ibcon#flushed, iclass 10, count 2 2006.257.07:51:46.48#ibcon#about to write, iclass 10, count 2 2006.257.07:51:46.48#ibcon#wrote, iclass 10, count 2 2006.257.07:51:46.48#ibcon#about to read 3, iclass 10, count 2 2006.257.07:51:46.51#ibcon#read 3, iclass 10, count 2 2006.257.07:51:46.51#ibcon#about to read 4, iclass 10, count 2 2006.257.07:51:46.51#ibcon#read 4, iclass 10, count 2 2006.257.07:51:46.51#ibcon#about to read 5, iclass 10, count 2 2006.257.07:51:46.51#ibcon#read 5, iclass 10, count 2 2006.257.07:51:46.51#ibcon#about to read 6, iclass 10, count 2 2006.257.07:51:46.51#ibcon#read 6, iclass 10, count 2 2006.257.07:51:46.51#ibcon#end of sib2, iclass 10, count 2 2006.257.07:51:46.51#ibcon#*after write, iclass 10, count 2 2006.257.07:51:46.51#ibcon#*before return 0, iclass 10, count 2 2006.257.07:51:46.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:51:46.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.07:51:46.51#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.07:51:46.51#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:46.51#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:51:46.63#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:51:46.63#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:51:46.63#ibcon#enter wrdev, iclass 10, count 0 2006.257.07:51:46.63#ibcon#first serial, iclass 10, count 0 2006.257.07:51:46.63#ibcon#enter sib2, iclass 10, count 0 2006.257.07:51:46.63#ibcon#flushed, iclass 10, count 0 2006.257.07:51:46.63#ibcon#about to write, iclass 10, count 0 2006.257.07:51:46.63#ibcon#wrote, iclass 10, count 0 2006.257.07:51:46.63#ibcon#about to read 3, iclass 10, count 0 2006.257.07:51:46.65#ibcon#read 3, iclass 10, count 0 2006.257.07:51:46.65#ibcon#about to read 4, iclass 10, count 0 2006.257.07:51:46.65#ibcon#read 4, iclass 10, count 0 2006.257.07:51:46.65#ibcon#about to read 5, iclass 10, count 0 2006.257.07:51:46.65#ibcon#read 5, iclass 10, count 0 2006.257.07:51:46.65#ibcon#about to read 6, iclass 10, count 0 2006.257.07:51:46.65#ibcon#read 6, iclass 10, count 0 2006.257.07:51:46.65#ibcon#end of sib2, iclass 10, count 0 2006.257.07:51:46.65#ibcon#*mode == 0, iclass 10, count 0 2006.257.07:51:46.65#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.07:51:46.65#ibcon#[25=USB\r\n] 2006.257.07:51:46.65#ibcon#*before write, iclass 10, count 0 2006.257.07:51:46.65#ibcon#enter sib2, iclass 10, count 0 2006.257.07:51:46.65#ibcon#flushed, iclass 10, count 0 2006.257.07:51:46.65#ibcon#about to write, iclass 10, count 0 2006.257.07:51:46.65#ibcon#wrote, iclass 10, count 0 2006.257.07:51:46.65#ibcon#about to read 3, iclass 10, count 0 2006.257.07:51:46.68#ibcon#read 3, iclass 10, count 0 2006.257.07:51:46.68#ibcon#about to read 4, iclass 10, count 0 2006.257.07:51:46.68#ibcon#read 4, iclass 10, count 0 2006.257.07:51:46.68#ibcon#about to read 5, iclass 10, count 0 2006.257.07:51:46.68#ibcon#read 5, iclass 10, count 0 2006.257.07:51:46.68#ibcon#about to read 6, iclass 10, count 0 2006.257.07:51:46.68#ibcon#read 6, iclass 10, count 0 2006.257.07:51:46.68#ibcon#end of sib2, iclass 10, count 0 2006.257.07:51:46.68#ibcon#*after write, iclass 10, count 0 2006.257.07:51:46.68#ibcon#*before return 0, iclass 10, count 0 2006.257.07:51:46.68#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:51:46.68#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.07:51:46.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.07:51:46.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.07:51:46.69$vck44/valo=5,734.99 2006.257.07:51:46.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.07:51:46.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.07:51:46.69#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:46.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:46.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:46.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:46.69#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:51:46.69#ibcon#first serial, iclass 13, count 0 2006.257.07:51:46.69#ibcon#enter sib2, iclass 13, count 0 2006.257.07:51:46.69#ibcon#flushed, iclass 13, count 0 2006.257.07:51:46.69#ibcon#about to write, iclass 13, count 0 2006.257.07:51:46.69#ibcon#wrote, iclass 13, count 0 2006.257.07:51:46.69#ibcon#about to read 3, iclass 13, count 0 2006.257.07:51:46.70#ibcon#read 3, iclass 13, count 0 2006.257.07:51:46.70#ibcon#about to read 4, iclass 13, count 0 2006.257.07:51:46.70#ibcon#read 4, iclass 13, count 0 2006.257.07:51:46.70#ibcon#about to read 5, iclass 13, count 0 2006.257.07:51:46.70#ibcon#read 5, iclass 13, count 0 2006.257.07:51:46.70#ibcon#about to read 6, iclass 13, count 0 2006.257.07:51:46.70#ibcon#read 6, iclass 13, count 0 2006.257.07:51:46.70#ibcon#end of sib2, iclass 13, count 0 2006.257.07:51:46.70#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:51:46.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:51:46.70#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.07:51:46.70#ibcon#*before write, iclass 13, count 0 2006.257.07:51:46.70#ibcon#enter sib2, iclass 13, count 0 2006.257.07:51:46.70#ibcon#flushed, iclass 13, count 0 2006.257.07:51:46.70#ibcon#about to write, iclass 13, count 0 2006.257.07:51:46.70#ibcon#wrote, iclass 13, count 0 2006.257.07:51:46.70#ibcon#about to read 3, iclass 13, count 0 2006.257.07:51:46.74#ibcon#read 3, iclass 13, count 0 2006.257.07:51:46.74#ibcon#about to read 4, iclass 13, count 0 2006.257.07:51:46.74#ibcon#read 4, iclass 13, count 0 2006.257.07:51:46.74#ibcon#about to read 5, iclass 13, count 0 2006.257.07:51:46.74#ibcon#read 5, iclass 13, count 0 2006.257.07:51:46.74#ibcon#about to read 6, iclass 13, count 0 2006.257.07:51:46.74#ibcon#read 6, iclass 13, count 0 2006.257.07:51:46.74#ibcon#end of sib2, iclass 13, count 0 2006.257.07:51:46.74#ibcon#*after write, iclass 13, count 0 2006.257.07:51:46.74#ibcon#*before return 0, iclass 13, count 0 2006.257.07:51:46.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:46.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:46.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:51:46.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:51:46.75$vck44/va=5,4 2006.257.07:51:46.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.07:51:46.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.07:51:46.75#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:46.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:46.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:46.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:46.79#ibcon#enter wrdev, iclass 15, count 2 2006.257.07:51:46.79#ibcon#first serial, iclass 15, count 2 2006.257.07:51:46.79#ibcon#enter sib2, iclass 15, count 2 2006.257.07:51:46.79#ibcon#flushed, iclass 15, count 2 2006.257.07:51:46.79#ibcon#about to write, iclass 15, count 2 2006.257.07:51:46.79#ibcon#wrote, iclass 15, count 2 2006.257.07:51:46.79#ibcon#about to read 3, iclass 15, count 2 2006.257.07:51:46.81#ibcon#read 3, iclass 15, count 2 2006.257.07:51:46.81#ibcon#about to read 4, iclass 15, count 2 2006.257.07:51:46.81#ibcon#read 4, iclass 15, count 2 2006.257.07:51:46.81#ibcon#about to read 5, iclass 15, count 2 2006.257.07:51:46.81#ibcon#read 5, iclass 15, count 2 2006.257.07:51:46.81#ibcon#about to read 6, iclass 15, count 2 2006.257.07:51:46.81#ibcon#read 6, iclass 15, count 2 2006.257.07:51:46.81#ibcon#end of sib2, iclass 15, count 2 2006.257.07:51:46.81#ibcon#*mode == 0, iclass 15, count 2 2006.257.07:51:46.81#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.07:51:46.81#ibcon#[25=AT05-04\r\n] 2006.257.07:51:46.81#ibcon#*before write, iclass 15, count 2 2006.257.07:51:46.81#ibcon#enter sib2, iclass 15, count 2 2006.257.07:51:46.81#ibcon#flushed, iclass 15, count 2 2006.257.07:51:46.81#ibcon#about to write, iclass 15, count 2 2006.257.07:51:46.81#ibcon#wrote, iclass 15, count 2 2006.257.07:51:46.81#ibcon#about to read 3, iclass 15, count 2 2006.257.07:51:46.84#ibcon#read 3, iclass 15, count 2 2006.257.07:51:46.84#ibcon#about to read 4, iclass 15, count 2 2006.257.07:51:46.84#ibcon#read 4, iclass 15, count 2 2006.257.07:51:46.84#ibcon#about to read 5, iclass 15, count 2 2006.257.07:51:46.84#ibcon#read 5, iclass 15, count 2 2006.257.07:51:46.84#ibcon#about to read 6, iclass 15, count 2 2006.257.07:51:46.84#ibcon#read 6, iclass 15, count 2 2006.257.07:51:46.84#ibcon#end of sib2, iclass 15, count 2 2006.257.07:51:46.84#ibcon#*after write, iclass 15, count 2 2006.257.07:51:46.84#ibcon#*before return 0, iclass 15, count 2 2006.257.07:51:46.84#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:46.84#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:46.84#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.07:51:46.84#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:46.84#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:46.96#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:46.96#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:46.96#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:51:46.96#ibcon#first serial, iclass 15, count 0 2006.257.07:51:46.96#ibcon#enter sib2, iclass 15, count 0 2006.257.07:51:46.96#ibcon#flushed, iclass 15, count 0 2006.257.07:51:46.96#ibcon#about to write, iclass 15, count 0 2006.257.07:51:46.96#ibcon#wrote, iclass 15, count 0 2006.257.07:51:46.96#ibcon#about to read 3, iclass 15, count 0 2006.257.07:51:46.98#ibcon#read 3, iclass 15, count 0 2006.257.07:51:46.98#ibcon#about to read 4, iclass 15, count 0 2006.257.07:51:46.98#ibcon#read 4, iclass 15, count 0 2006.257.07:51:46.98#ibcon#about to read 5, iclass 15, count 0 2006.257.07:51:46.98#ibcon#read 5, iclass 15, count 0 2006.257.07:51:46.98#ibcon#about to read 6, iclass 15, count 0 2006.257.07:51:46.98#ibcon#read 6, iclass 15, count 0 2006.257.07:51:46.98#ibcon#end of sib2, iclass 15, count 0 2006.257.07:51:46.98#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:51:46.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:51:46.98#ibcon#[25=USB\r\n] 2006.257.07:51:46.98#ibcon#*before write, iclass 15, count 0 2006.257.07:51:46.98#ibcon#enter sib2, iclass 15, count 0 2006.257.07:51:46.98#ibcon#flushed, iclass 15, count 0 2006.257.07:51:46.98#ibcon#about to write, iclass 15, count 0 2006.257.07:51:46.98#ibcon#wrote, iclass 15, count 0 2006.257.07:51:46.98#ibcon#about to read 3, iclass 15, count 0 2006.257.07:51:47.01#ibcon#read 3, iclass 15, count 0 2006.257.07:51:47.01#ibcon#about to read 4, iclass 15, count 0 2006.257.07:51:47.01#ibcon#read 4, iclass 15, count 0 2006.257.07:51:47.01#ibcon#about to read 5, iclass 15, count 0 2006.257.07:51:47.01#ibcon#read 5, iclass 15, count 0 2006.257.07:51:47.01#ibcon#about to read 6, iclass 15, count 0 2006.257.07:51:47.01#ibcon#read 6, iclass 15, count 0 2006.257.07:51:47.01#ibcon#end of sib2, iclass 15, count 0 2006.257.07:51:47.01#ibcon#*after write, iclass 15, count 0 2006.257.07:51:47.01#ibcon#*before return 0, iclass 15, count 0 2006.257.07:51:47.01#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:47.01#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:47.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:51:47.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:51:47.02$vck44/valo=6,814.99 2006.257.07:51:47.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.07:51:47.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.07:51:47.02#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:47.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:47.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:47.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:47.02#ibcon#enter wrdev, iclass 17, count 0 2006.257.07:51:47.02#ibcon#first serial, iclass 17, count 0 2006.257.07:51:47.02#ibcon#enter sib2, iclass 17, count 0 2006.257.07:51:47.02#ibcon#flushed, iclass 17, count 0 2006.257.07:51:47.02#ibcon#about to write, iclass 17, count 0 2006.257.07:51:47.02#ibcon#wrote, iclass 17, count 0 2006.257.07:51:47.02#ibcon#about to read 3, iclass 17, count 0 2006.257.07:51:47.03#ibcon#read 3, iclass 17, count 0 2006.257.07:51:47.03#ibcon#about to read 4, iclass 17, count 0 2006.257.07:51:47.03#ibcon#read 4, iclass 17, count 0 2006.257.07:51:47.03#ibcon#about to read 5, iclass 17, count 0 2006.257.07:51:47.03#ibcon#read 5, iclass 17, count 0 2006.257.07:51:47.03#ibcon#about to read 6, iclass 17, count 0 2006.257.07:51:47.03#ibcon#read 6, iclass 17, count 0 2006.257.07:51:47.03#ibcon#end of sib2, iclass 17, count 0 2006.257.07:51:47.03#ibcon#*mode == 0, iclass 17, count 0 2006.257.07:51:47.03#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.07:51:47.03#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.07:51:47.03#ibcon#*before write, iclass 17, count 0 2006.257.07:51:47.03#ibcon#enter sib2, iclass 17, count 0 2006.257.07:51:47.03#ibcon#flushed, iclass 17, count 0 2006.257.07:51:47.03#ibcon#about to write, iclass 17, count 0 2006.257.07:51:47.03#ibcon#wrote, iclass 17, count 0 2006.257.07:51:47.03#ibcon#about to read 3, iclass 17, count 0 2006.257.07:51:47.07#ibcon#read 3, iclass 17, count 0 2006.257.07:51:47.07#ibcon#about to read 4, iclass 17, count 0 2006.257.07:51:47.07#ibcon#read 4, iclass 17, count 0 2006.257.07:51:47.07#ibcon#about to read 5, iclass 17, count 0 2006.257.07:51:47.07#ibcon#read 5, iclass 17, count 0 2006.257.07:51:47.07#ibcon#about to read 6, iclass 17, count 0 2006.257.07:51:47.07#ibcon#read 6, iclass 17, count 0 2006.257.07:51:47.07#ibcon#end of sib2, iclass 17, count 0 2006.257.07:51:47.07#ibcon#*after write, iclass 17, count 0 2006.257.07:51:47.07#ibcon#*before return 0, iclass 17, count 0 2006.257.07:51:47.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:47.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:47.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.07:51:47.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.07:51:47.08$vck44/va=6,4 2006.257.07:51:47.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.07:51:47.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.07:51:47.08#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:47.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:47.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:47.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:47.12#ibcon#enter wrdev, iclass 19, count 2 2006.257.07:51:47.12#ibcon#first serial, iclass 19, count 2 2006.257.07:51:47.12#ibcon#enter sib2, iclass 19, count 2 2006.257.07:51:47.12#ibcon#flushed, iclass 19, count 2 2006.257.07:51:47.12#ibcon#about to write, iclass 19, count 2 2006.257.07:51:47.12#ibcon#wrote, iclass 19, count 2 2006.257.07:51:47.12#ibcon#about to read 3, iclass 19, count 2 2006.257.07:51:47.14#ibcon#read 3, iclass 19, count 2 2006.257.07:51:47.14#ibcon#about to read 4, iclass 19, count 2 2006.257.07:51:47.14#ibcon#read 4, iclass 19, count 2 2006.257.07:51:47.14#ibcon#about to read 5, iclass 19, count 2 2006.257.07:51:47.14#ibcon#read 5, iclass 19, count 2 2006.257.07:51:47.14#ibcon#about to read 6, iclass 19, count 2 2006.257.07:51:47.14#ibcon#read 6, iclass 19, count 2 2006.257.07:51:47.14#ibcon#end of sib2, iclass 19, count 2 2006.257.07:51:47.14#ibcon#*mode == 0, iclass 19, count 2 2006.257.07:51:47.14#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.07:51:47.14#ibcon#[25=AT06-04\r\n] 2006.257.07:51:47.14#ibcon#*before write, iclass 19, count 2 2006.257.07:51:47.14#ibcon#enter sib2, iclass 19, count 2 2006.257.07:51:47.14#ibcon#flushed, iclass 19, count 2 2006.257.07:51:47.14#ibcon#about to write, iclass 19, count 2 2006.257.07:51:47.14#ibcon#wrote, iclass 19, count 2 2006.257.07:51:47.14#ibcon#about to read 3, iclass 19, count 2 2006.257.07:51:47.17#ibcon#read 3, iclass 19, count 2 2006.257.07:51:47.17#ibcon#about to read 4, iclass 19, count 2 2006.257.07:51:47.17#ibcon#read 4, iclass 19, count 2 2006.257.07:51:47.17#ibcon#about to read 5, iclass 19, count 2 2006.257.07:51:47.17#ibcon#read 5, iclass 19, count 2 2006.257.07:51:47.17#ibcon#about to read 6, iclass 19, count 2 2006.257.07:51:47.17#ibcon#read 6, iclass 19, count 2 2006.257.07:51:47.17#ibcon#end of sib2, iclass 19, count 2 2006.257.07:51:47.17#ibcon#*after write, iclass 19, count 2 2006.257.07:51:47.17#ibcon#*before return 0, iclass 19, count 2 2006.257.07:51:47.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:47.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:47.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.07:51:47.17#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:47.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:47.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:47.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:47.29#ibcon#enter wrdev, iclass 19, count 0 2006.257.07:51:47.29#ibcon#first serial, iclass 19, count 0 2006.257.07:51:47.29#ibcon#enter sib2, iclass 19, count 0 2006.257.07:51:47.29#ibcon#flushed, iclass 19, count 0 2006.257.07:51:47.29#ibcon#about to write, iclass 19, count 0 2006.257.07:51:47.29#ibcon#wrote, iclass 19, count 0 2006.257.07:51:47.29#ibcon#about to read 3, iclass 19, count 0 2006.257.07:51:47.31#ibcon#read 3, iclass 19, count 0 2006.257.07:51:47.31#ibcon#about to read 4, iclass 19, count 0 2006.257.07:51:47.31#ibcon#read 4, iclass 19, count 0 2006.257.07:51:47.31#ibcon#about to read 5, iclass 19, count 0 2006.257.07:51:47.31#ibcon#read 5, iclass 19, count 0 2006.257.07:51:47.31#ibcon#about to read 6, iclass 19, count 0 2006.257.07:51:47.31#ibcon#read 6, iclass 19, count 0 2006.257.07:51:47.31#ibcon#end of sib2, iclass 19, count 0 2006.257.07:51:47.31#ibcon#*mode == 0, iclass 19, count 0 2006.257.07:51:47.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.07:51:47.31#ibcon#[25=USB\r\n] 2006.257.07:51:47.31#ibcon#*before write, iclass 19, count 0 2006.257.07:51:47.31#ibcon#enter sib2, iclass 19, count 0 2006.257.07:51:47.31#ibcon#flushed, iclass 19, count 0 2006.257.07:51:47.31#ibcon#about to write, iclass 19, count 0 2006.257.07:51:47.31#ibcon#wrote, iclass 19, count 0 2006.257.07:51:47.31#ibcon#about to read 3, iclass 19, count 0 2006.257.07:51:47.34#ibcon#read 3, iclass 19, count 0 2006.257.07:51:47.34#ibcon#about to read 4, iclass 19, count 0 2006.257.07:51:47.34#ibcon#read 4, iclass 19, count 0 2006.257.07:51:47.34#ibcon#about to read 5, iclass 19, count 0 2006.257.07:51:47.34#ibcon#read 5, iclass 19, count 0 2006.257.07:51:47.34#ibcon#about to read 6, iclass 19, count 0 2006.257.07:51:47.34#ibcon#read 6, iclass 19, count 0 2006.257.07:51:47.34#ibcon#end of sib2, iclass 19, count 0 2006.257.07:51:47.34#ibcon#*after write, iclass 19, count 0 2006.257.07:51:47.34#ibcon#*before return 0, iclass 19, count 0 2006.257.07:51:47.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:47.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:47.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.07:51:47.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.07:51:47.35$vck44/valo=7,864.99 2006.257.07:51:47.35#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.07:51:47.35#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.07:51:47.35#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:47.35#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:47.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:47.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:47.35#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:51:47.35#ibcon#first serial, iclass 21, count 0 2006.257.07:51:47.35#ibcon#enter sib2, iclass 21, count 0 2006.257.07:51:47.35#ibcon#flushed, iclass 21, count 0 2006.257.07:51:47.35#ibcon#about to write, iclass 21, count 0 2006.257.07:51:47.35#ibcon#wrote, iclass 21, count 0 2006.257.07:51:47.35#ibcon#about to read 3, iclass 21, count 0 2006.257.07:51:47.36#ibcon#read 3, iclass 21, count 0 2006.257.07:51:47.36#ibcon#about to read 4, iclass 21, count 0 2006.257.07:51:47.36#ibcon#read 4, iclass 21, count 0 2006.257.07:51:47.36#ibcon#about to read 5, iclass 21, count 0 2006.257.07:51:47.36#ibcon#read 5, iclass 21, count 0 2006.257.07:51:47.36#ibcon#about to read 6, iclass 21, count 0 2006.257.07:51:47.36#ibcon#read 6, iclass 21, count 0 2006.257.07:51:47.36#ibcon#end of sib2, iclass 21, count 0 2006.257.07:51:47.36#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:51:47.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:51:47.36#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.07:51:47.36#ibcon#*before write, iclass 21, count 0 2006.257.07:51:47.36#ibcon#enter sib2, iclass 21, count 0 2006.257.07:51:47.36#ibcon#flushed, iclass 21, count 0 2006.257.07:51:47.36#ibcon#about to write, iclass 21, count 0 2006.257.07:51:47.36#ibcon#wrote, iclass 21, count 0 2006.257.07:51:47.36#ibcon#about to read 3, iclass 21, count 0 2006.257.07:51:47.40#ibcon#read 3, iclass 21, count 0 2006.257.07:51:47.40#ibcon#about to read 4, iclass 21, count 0 2006.257.07:51:47.40#ibcon#read 4, iclass 21, count 0 2006.257.07:51:47.40#ibcon#about to read 5, iclass 21, count 0 2006.257.07:51:47.40#ibcon#read 5, iclass 21, count 0 2006.257.07:51:47.40#ibcon#about to read 6, iclass 21, count 0 2006.257.07:51:47.40#ibcon#read 6, iclass 21, count 0 2006.257.07:51:47.40#ibcon#end of sib2, iclass 21, count 0 2006.257.07:51:47.40#ibcon#*after write, iclass 21, count 0 2006.257.07:51:47.40#ibcon#*before return 0, iclass 21, count 0 2006.257.07:51:47.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:47.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:47.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:51:47.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:51:47.41$vck44/va=7,4 2006.257.07:51:47.41#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.07:51:47.41#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.07:51:47.41#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:47.41#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:47.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:47.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:47.45#ibcon#enter wrdev, iclass 23, count 2 2006.257.07:51:47.45#ibcon#first serial, iclass 23, count 2 2006.257.07:51:47.45#ibcon#enter sib2, iclass 23, count 2 2006.257.07:51:47.45#ibcon#flushed, iclass 23, count 2 2006.257.07:51:47.45#ibcon#about to write, iclass 23, count 2 2006.257.07:51:47.45#ibcon#wrote, iclass 23, count 2 2006.257.07:51:47.45#ibcon#about to read 3, iclass 23, count 2 2006.257.07:51:47.47#ibcon#read 3, iclass 23, count 2 2006.257.07:51:47.47#ibcon#about to read 4, iclass 23, count 2 2006.257.07:51:47.47#ibcon#read 4, iclass 23, count 2 2006.257.07:51:47.47#ibcon#about to read 5, iclass 23, count 2 2006.257.07:51:47.47#ibcon#read 5, iclass 23, count 2 2006.257.07:51:47.47#ibcon#about to read 6, iclass 23, count 2 2006.257.07:51:47.47#ibcon#read 6, iclass 23, count 2 2006.257.07:51:47.47#ibcon#end of sib2, iclass 23, count 2 2006.257.07:51:47.47#ibcon#*mode == 0, iclass 23, count 2 2006.257.07:51:47.47#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.07:51:47.47#ibcon#[25=AT07-04\r\n] 2006.257.07:51:47.47#ibcon#*before write, iclass 23, count 2 2006.257.07:51:47.47#ibcon#enter sib2, iclass 23, count 2 2006.257.07:51:47.47#ibcon#flushed, iclass 23, count 2 2006.257.07:51:47.47#ibcon#about to write, iclass 23, count 2 2006.257.07:51:47.47#ibcon#wrote, iclass 23, count 2 2006.257.07:51:47.47#ibcon#about to read 3, iclass 23, count 2 2006.257.07:51:47.50#ibcon#read 3, iclass 23, count 2 2006.257.07:51:47.50#ibcon#about to read 4, iclass 23, count 2 2006.257.07:51:47.50#ibcon#read 4, iclass 23, count 2 2006.257.07:51:47.50#ibcon#about to read 5, iclass 23, count 2 2006.257.07:51:47.50#ibcon#read 5, iclass 23, count 2 2006.257.07:51:47.50#ibcon#about to read 6, iclass 23, count 2 2006.257.07:51:47.50#ibcon#read 6, iclass 23, count 2 2006.257.07:51:47.50#ibcon#end of sib2, iclass 23, count 2 2006.257.07:51:47.50#ibcon#*after write, iclass 23, count 2 2006.257.07:51:47.50#ibcon#*before return 0, iclass 23, count 2 2006.257.07:51:47.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:47.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:47.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.07:51:47.50#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:47.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:47.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:47.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:47.62#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:51:47.62#ibcon#first serial, iclass 23, count 0 2006.257.07:51:47.62#ibcon#enter sib2, iclass 23, count 0 2006.257.07:51:47.62#ibcon#flushed, iclass 23, count 0 2006.257.07:51:47.62#ibcon#about to write, iclass 23, count 0 2006.257.07:51:47.62#ibcon#wrote, iclass 23, count 0 2006.257.07:51:47.62#ibcon#about to read 3, iclass 23, count 0 2006.257.07:51:47.64#ibcon#read 3, iclass 23, count 0 2006.257.07:51:47.64#ibcon#about to read 4, iclass 23, count 0 2006.257.07:51:47.64#ibcon#read 4, iclass 23, count 0 2006.257.07:51:47.64#ibcon#about to read 5, iclass 23, count 0 2006.257.07:51:47.64#ibcon#read 5, iclass 23, count 0 2006.257.07:51:47.64#ibcon#about to read 6, iclass 23, count 0 2006.257.07:51:47.64#ibcon#read 6, iclass 23, count 0 2006.257.07:51:47.64#ibcon#end of sib2, iclass 23, count 0 2006.257.07:51:47.64#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:51:47.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:51:47.64#ibcon#[25=USB\r\n] 2006.257.07:51:47.64#ibcon#*before write, iclass 23, count 0 2006.257.07:51:47.64#ibcon#enter sib2, iclass 23, count 0 2006.257.07:51:47.64#ibcon#flushed, iclass 23, count 0 2006.257.07:51:47.64#ibcon#about to write, iclass 23, count 0 2006.257.07:51:47.64#ibcon#wrote, iclass 23, count 0 2006.257.07:51:47.64#ibcon#about to read 3, iclass 23, count 0 2006.257.07:51:47.67#ibcon#read 3, iclass 23, count 0 2006.257.07:51:47.67#ibcon#about to read 4, iclass 23, count 0 2006.257.07:51:47.67#ibcon#read 4, iclass 23, count 0 2006.257.07:51:47.67#ibcon#about to read 5, iclass 23, count 0 2006.257.07:51:47.67#ibcon#read 5, iclass 23, count 0 2006.257.07:51:47.67#ibcon#about to read 6, iclass 23, count 0 2006.257.07:51:47.67#ibcon#read 6, iclass 23, count 0 2006.257.07:51:47.67#ibcon#end of sib2, iclass 23, count 0 2006.257.07:51:47.67#ibcon#*after write, iclass 23, count 0 2006.257.07:51:47.67#ibcon#*before return 0, iclass 23, count 0 2006.257.07:51:47.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:47.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:47.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:51:47.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:51:47.68$vck44/valo=8,884.99 2006.257.07:51:47.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.07:51:47.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.07:51:47.68#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:47.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:47.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:47.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:47.68#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:51:47.68#ibcon#first serial, iclass 25, count 0 2006.257.07:51:47.68#ibcon#enter sib2, iclass 25, count 0 2006.257.07:51:47.68#ibcon#flushed, iclass 25, count 0 2006.257.07:51:47.68#ibcon#about to write, iclass 25, count 0 2006.257.07:51:47.68#ibcon#wrote, iclass 25, count 0 2006.257.07:51:47.68#ibcon#about to read 3, iclass 25, count 0 2006.257.07:51:47.69#ibcon#read 3, iclass 25, count 0 2006.257.07:51:47.69#ibcon#about to read 4, iclass 25, count 0 2006.257.07:51:47.69#ibcon#read 4, iclass 25, count 0 2006.257.07:51:47.69#ibcon#about to read 5, iclass 25, count 0 2006.257.07:51:47.69#ibcon#read 5, iclass 25, count 0 2006.257.07:51:47.69#ibcon#about to read 6, iclass 25, count 0 2006.257.07:51:47.69#ibcon#read 6, iclass 25, count 0 2006.257.07:51:47.69#ibcon#end of sib2, iclass 25, count 0 2006.257.07:51:47.69#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:51:47.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:51:47.69#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.07:51:47.69#ibcon#*before write, iclass 25, count 0 2006.257.07:51:47.69#ibcon#enter sib2, iclass 25, count 0 2006.257.07:51:47.69#ibcon#flushed, iclass 25, count 0 2006.257.07:51:47.69#ibcon#about to write, iclass 25, count 0 2006.257.07:51:47.69#ibcon#wrote, iclass 25, count 0 2006.257.07:51:47.69#ibcon#about to read 3, iclass 25, count 0 2006.257.07:51:47.73#ibcon#read 3, iclass 25, count 0 2006.257.07:51:47.73#ibcon#about to read 4, iclass 25, count 0 2006.257.07:51:47.73#ibcon#read 4, iclass 25, count 0 2006.257.07:51:47.73#ibcon#about to read 5, iclass 25, count 0 2006.257.07:51:47.73#ibcon#read 5, iclass 25, count 0 2006.257.07:51:47.73#ibcon#about to read 6, iclass 25, count 0 2006.257.07:51:47.73#ibcon#read 6, iclass 25, count 0 2006.257.07:51:47.73#ibcon#end of sib2, iclass 25, count 0 2006.257.07:51:47.73#ibcon#*after write, iclass 25, count 0 2006.257.07:51:47.73#ibcon#*before return 0, iclass 25, count 0 2006.257.07:51:47.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:47.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:47.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:51:47.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:51:47.74$vck44/va=8,4 2006.257.07:51:47.74#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.07:51:47.74#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.07:51:47.74#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:47.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:51:47.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:51:47.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:51:47.78#ibcon#enter wrdev, iclass 27, count 2 2006.257.07:51:47.78#ibcon#first serial, iclass 27, count 2 2006.257.07:51:47.78#ibcon#enter sib2, iclass 27, count 2 2006.257.07:51:47.78#ibcon#flushed, iclass 27, count 2 2006.257.07:51:47.78#ibcon#about to write, iclass 27, count 2 2006.257.07:51:47.78#ibcon#wrote, iclass 27, count 2 2006.257.07:51:47.78#ibcon#about to read 3, iclass 27, count 2 2006.257.07:51:47.80#ibcon#read 3, iclass 27, count 2 2006.257.07:51:47.80#ibcon#about to read 4, iclass 27, count 2 2006.257.07:51:47.80#ibcon#read 4, iclass 27, count 2 2006.257.07:51:47.80#ibcon#about to read 5, iclass 27, count 2 2006.257.07:51:47.80#ibcon#read 5, iclass 27, count 2 2006.257.07:51:47.80#ibcon#about to read 6, iclass 27, count 2 2006.257.07:51:47.80#ibcon#read 6, iclass 27, count 2 2006.257.07:51:47.80#ibcon#end of sib2, iclass 27, count 2 2006.257.07:51:47.80#ibcon#*mode == 0, iclass 27, count 2 2006.257.07:51:47.80#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.07:51:47.80#ibcon#[25=AT08-04\r\n] 2006.257.07:51:47.80#ibcon#*before write, iclass 27, count 2 2006.257.07:51:47.80#ibcon#enter sib2, iclass 27, count 2 2006.257.07:51:47.80#ibcon#flushed, iclass 27, count 2 2006.257.07:51:47.80#ibcon#about to write, iclass 27, count 2 2006.257.07:51:47.80#ibcon#wrote, iclass 27, count 2 2006.257.07:51:47.80#ibcon#about to read 3, iclass 27, count 2 2006.257.07:51:47.83#ibcon#read 3, iclass 27, count 2 2006.257.07:51:47.83#ibcon#about to read 4, iclass 27, count 2 2006.257.07:51:47.83#ibcon#read 4, iclass 27, count 2 2006.257.07:51:47.83#ibcon#about to read 5, iclass 27, count 2 2006.257.07:51:47.83#ibcon#read 5, iclass 27, count 2 2006.257.07:51:47.83#ibcon#about to read 6, iclass 27, count 2 2006.257.07:51:47.83#ibcon#read 6, iclass 27, count 2 2006.257.07:51:47.83#ibcon#end of sib2, iclass 27, count 2 2006.257.07:51:47.83#ibcon#*after write, iclass 27, count 2 2006.257.07:51:47.83#ibcon#*before return 0, iclass 27, count 2 2006.257.07:51:47.83#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:51:47.83#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.07:51:47.83#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.07:51:47.83#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:47.83#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:51:47.95#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:51:47.95#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:51:47.95#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:51:47.95#ibcon#first serial, iclass 27, count 0 2006.257.07:51:47.95#ibcon#enter sib2, iclass 27, count 0 2006.257.07:51:47.95#ibcon#flushed, iclass 27, count 0 2006.257.07:51:47.95#ibcon#about to write, iclass 27, count 0 2006.257.07:51:47.95#ibcon#wrote, iclass 27, count 0 2006.257.07:51:47.95#ibcon#about to read 3, iclass 27, count 0 2006.257.07:51:47.97#ibcon#read 3, iclass 27, count 0 2006.257.07:51:47.97#ibcon#about to read 4, iclass 27, count 0 2006.257.07:51:47.97#ibcon#read 4, iclass 27, count 0 2006.257.07:51:47.97#ibcon#about to read 5, iclass 27, count 0 2006.257.07:51:47.97#ibcon#read 5, iclass 27, count 0 2006.257.07:51:47.97#ibcon#about to read 6, iclass 27, count 0 2006.257.07:51:47.97#ibcon#read 6, iclass 27, count 0 2006.257.07:51:47.97#ibcon#end of sib2, iclass 27, count 0 2006.257.07:51:47.97#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:51:47.97#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:51:47.97#ibcon#[25=USB\r\n] 2006.257.07:51:47.97#ibcon#*before write, iclass 27, count 0 2006.257.07:51:47.97#ibcon#enter sib2, iclass 27, count 0 2006.257.07:51:47.97#ibcon#flushed, iclass 27, count 0 2006.257.07:51:47.97#ibcon#about to write, iclass 27, count 0 2006.257.07:51:47.97#ibcon#wrote, iclass 27, count 0 2006.257.07:51:47.97#ibcon#about to read 3, iclass 27, count 0 2006.257.07:51:48.00#ibcon#read 3, iclass 27, count 0 2006.257.07:51:48.00#ibcon#about to read 4, iclass 27, count 0 2006.257.07:51:48.00#ibcon#read 4, iclass 27, count 0 2006.257.07:51:48.00#ibcon#about to read 5, iclass 27, count 0 2006.257.07:51:48.00#ibcon#read 5, iclass 27, count 0 2006.257.07:51:48.00#ibcon#about to read 6, iclass 27, count 0 2006.257.07:51:48.00#ibcon#read 6, iclass 27, count 0 2006.257.07:51:48.00#ibcon#end of sib2, iclass 27, count 0 2006.257.07:51:48.00#ibcon#*after write, iclass 27, count 0 2006.257.07:51:48.00#ibcon#*before return 0, iclass 27, count 0 2006.257.07:51:48.00#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:51:48.00#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.07:51:48.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:51:48.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:51:48.01$vck44/vblo=1,629.99 2006.257.07:51:48.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.07:51:48.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.07:51:48.01#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:48.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:48.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:48.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:48.01#ibcon#enter wrdev, iclass 29, count 0 2006.257.07:51:48.01#ibcon#first serial, iclass 29, count 0 2006.257.07:51:48.01#ibcon#enter sib2, iclass 29, count 0 2006.257.07:51:48.01#ibcon#flushed, iclass 29, count 0 2006.257.07:51:48.01#ibcon#about to write, iclass 29, count 0 2006.257.07:51:48.01#ibcon#wrote, iclass 29, count 0 2006.257.07:51:48.01#ibcon#about to read 3, iclass 29, count 0 2006.257.07:51:48.02#ibcon#read 3, iclass 29, count 0 2006.257.07:51:48.02#ibcon#about to read 4, iclass 29, count 0 2006.257.07:51:48.02#ibcon#read 4, iclass 29, count 0 2006.257.07:51:48.02#ibcon#about to read 5, iclass 29, count 0 2006.257.07:51:48.02#ibcon#read 5, iclass 29, count 0 2006.257.07:51:48.02#ibcon#about to read 6, iclass 29, count 0 2006.257.07:51:48.02#ibcon#read 6, iclass 29, count 0 2006.257.07:51:48.02#ibcon#end of sib2, iclass 29, count 0 2006.257.07:51:48.02#ibcon#*mode == 0, iclass 29, count 0 2006.257.07:51:48.02#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.07:51:48.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.07:51:48.02#ibcon#*before write, iclass 29, count 0 2006.257.07:51:48.02#ibcon#enter sib2, iclass 29, count 0 2006.257.07:51:48.02#ibcon#flushed, iclass 29, count 0 2006.257.07:51:48.02#ibcon#about to write, iclass 29, count 0 2006.257.07:51:48.02#ibcon#wrote, iclass 29, count 0 2006.257.07:51:48.02#ibcon#about to read 3, iclass 29, count 0 2006.257.07:51:48.06#ibcon#read 3, iclass 29, count 0 2006.257.07:51:48.06#ibcon#about to read 4, iclass 29, count 0 2006.257.07:51:48.06#ibcon#read 4, iclass 29, count 0 2006.257.07:51:48.06#ibcon#about to read 5, iclass 29, count 0 2006.257.07:51:48.06#ibcon#read 5, iclass 29, count 0 2006.257.07:51:48.06#ibcon#about to read 6, iclass 29, count 0 2006.257.07:51:48.06#ibcon#read 6, iclass 29, count 0 2006.257.07:51:48.06#ibcon#end of sib2, iclass 29, count 0 2006.257.07:51:48.06#ibcon#*after write, iclass 29, count 0 2006.257.07:51:48.06#ibcon#*before return 0, iclass 29, count 0 2006.257.07:51:48.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:48.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.07:51:48.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.07:51:48.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.07:51:48.07$vck44/vb=1,4 2006.257.07:51:48.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.07:51:48.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.07:51:48.07#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:48.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:48.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:48.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:48.07#ibcon#enter wrdev, iclass 31, count 2 2006.257.07:51:48.07#ibcon#first serial, iclass 31, count 2 2006.257.07:51:48.07#ibcon#enter sib2, iclass 31, count 2 2006.257.07:51:48.07#ibcon#flushed, iclass 31, count 2 2006.257.07:51:48.07#ibcon#about to write, iclass 31, count 2 2006.257.07:51:48.07#ibcon#wrote, iclass 31, count 2 2006.257.07:51:48.07#ibcon#about to read 3, iclass 31, count 2 2006.257.07:51:48.08#ibcon#read 3, iclass 31, count 2 2006.257.07:51:48.08#ibcon#about to read 4, iclass 31, count 2 2006.257.07:51:48.08#ibcon#read 4, iclass 31, count 2 2006.257.07:51:48.08#ibcon#about to read 5, iclass 31, count 2 2006.257.07:51:48.08#ibcon#read 5, iclass 31, count 2 2006.257.07:51:48.08#ibcon#about to read 6, iclass 31, count 2 2006.257.07:51:48.08#ibcon#read 6, iclass 31, count 2 2006.257.07:51:48.08#ibcon#end of sib2, iclass 31, count 2 2006.257.07:51:48.08#ibcon#*mode == 0, iclass 31, count 2 2006.257.07:51:48.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.07:51:48.08#ibcon#[27=AT01-04\r\n] 2006.257.07:51:48.08#ibcon#*before write, iclass 31, count 2 2006.257.07:51:48.08#ibcon#enter sib2, iclass 31, count 2 2006.257.07:51:48.08#ibcon#flushed, iclass 31, count 2 2006.257.07:51:48.08#ibcon#about to write, iclass 31, count 2 2006.257.07:51:48.08#ibcon#wrote, iclass 31, count 2 2006.257.07:51:48.08#ibcon#about to read 3, iclass 31, count 2 2006.257.07:51:48.11#ibcon#read 3, iclass 31, count 2 2006.257.07:51:48.11#ibcon#about to read 4, iclass 31, count 2 2006.257.07:51:48.11#ibcon#read 4, iclass 31, count 2 2006.257.07:51:48.11#ibcon#about to read 5, iclass 31, count 2 2006.257.07:51:48.11#ibcon#read 5, iclass 31, count 2 2006.257.07:51:48.11#ibcon#about to read 6, iclass 31, count 2 2006.257.07:51:48.11#ibcon#read 6, iclass 31, count 2 2006.257.07:51:48.11#ibcon#end of sib2, iclass 31, count 2 2006.257.07:51:48.11#ibcon#*after write, iclass 31, count 2 2006.257.07:51:48.11#ibcon#*before return 0, iclass 31, count 2 2006.257.07:51:48.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:48.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.07:51:48.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.07:51:48.11#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:48.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:48.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:48.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:48.23#ibcon#enter wrdev, iclass 31, count 0 2006.257.07:51:48.23#ibcon#first serial, iclass 31, count 0 2006.257.07:51:48.23#ibcon#enter sib2, iclass 31, count 0 2006.257.07:51:48.23#ibcon#flushed, iclass 31, count 0 2006.257.07:51:48.23#ibcon#about to write, iclass 31, count 0 2006.257.07:51:48.23#ibcon#wrote, iclass 31, count 0 2006.257.07:51:48.23#ibcon#about to read 3, iclass 31, count 0 2006.257.07:51:48.25#ibcon#read 3, iclass 31, count 0 2006.257.07:51:48.25#ibcon#about to read 4, iclass 31, count 0 2006.257.07:51:48.25#ibcon#read 4, iclass 31, count 0 2006.257.07:51:48.25#ibcon#about to read 5, iclass 31, count 0 2006.257.07:51:48.25#ibcon#read 5, iclass 31, count 0 2006.257.07:51:48.25#ibcon#about to read 6, iclass 31, count 0 2006.257.07:51:48.25#ibcon#read 6, iclass 31, count 0 2006.257.07:51:48.25#ibcon#end of sib2, iclass 31, count 0 2006.257.07:51:48.25#ibcon#*mode == 0, iclass 31, count 0 2006.257.07:51:48.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.07:51:48.25#ibcon#[27=USB\r\n] 2006.257.07:51:48.25#ibcon#*before write, iclass 31, count 0 2006.257.07:51:48.25#ibcon#enter sib2, iclass 31, count 0 2006.257.07:51:48.25#ibcon#flushed, iclass 31, count 0 2006.257.07:51:48.25#ibcon#about to write, iclass 31, count 0 2006.257.07:51:48.25#ibcon#wrote, iclass 31, count 0 2006.257.07:51:48.25#ibcon#about to read 3, iclass 31, count 0 2006.257.07:51:48.28#ibcon#read 3, iclass 31, count 0 2006.257.07:51:48.28#ibcon#about to read 4, iclass 31, count 0 2006.257.07:51:48.28#ibcon#read 4, iclass 31, count 0 2006.257.07:51:48.28#ibcon#about to read 5, iclass 31, count 0 2006.257.07:51:48.28#ibcon#read 5, iclass 31, count 0 2006.257.07:51:48.28#ibcon#about to read 6, iclass 31, count 0 2006.257.07:51:48.28#ibcon#read 6, iclass 31, count 0 2006.257.07:51:48.28#ibcon#end of sib2, iclass 31, count 0 2006.257.07:51:48.28#ibcon#*after write, iclass 31, count 0 2006.257.07:51:48.28#ibcon#*before return 0, iclass 31, count 0 2006.257.07:51:48.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:48.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.07:51:48.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.07:51:48.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.07:51:48.29$vck44/vblo=2,634.99 2006.257.07:51:48.29#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.07:51:48.29#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.07:51:48.29#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:48.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:48.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:48.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:48.29#ibcon#enter wrdev, iclass 33, count 0 2006.257.07:51:48.29#ibcon#first serial, iclass 33, count 0 2006.257.07:51:48.29#ibcon#enter sib2, iclass 33, count 0 2006.257.07:51:48.29#ibcon#flushed, iclass 33, count 0 2006.257.07:51:48.29#ibcon#about to write, iclass 33, count 0 2006.257.07:51:48.29#ibcon#wrote, iclass 33, count 0 2006.257.07:51:48.29#ibcon#about to read 3, iclass 33, count 0 2006.257.07:51:48.30#ibcon#read 3, iclass 33, count 0 2006.257.07:51:48.30#ibcon#about to read 4, iclass 33, count 0 2006.257.07:51:48.30#ibcon#read 4, iclass 33, count 0 2006.257.07:51:48.30#ibcon#about to read 5, iclass 33, count 0 2006.257.07:51:48.30#ibcon#read 5, iclass 33, count 0 2006.257.07:51:48.30#ibcon#about to read 6, iclass 33, count 0 2006.257.07:51:48.30#ibcon#read 6, iclass 33, count 0 2006.257.07:51:48.30#ibcon#end of sib2, iclass 33, count 0 2006.257.07:51:48.30#ibcon#*mode == 0, iclass 33, count 0 2006.257.07:51:48.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.07:51:48.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.07:51:48.30#ibcon#*before write, iclass 33, count 0 2006.257.07:51:48.30#ibcon#enter sib2, iclass 33, count 0 2006.257.07:51:48.30#ibcon#flushed, iclass 33, count 0 2006.257.07:51:48.30#ibcon#about to write, iclass 33, count 0 2006.257.07:51:48.30#ibcon#wrote, iclass 33, count 0 2006.257.07:51:48.30#ibcon#about to read 3, iclass 33, count 0 2006.257.07:51:48.34#ibcon#read 3, iclass 33, count 0 2006.257.07:51:48.34#ibcon#about to read 4, iclass 33, count 0 2006.257.07:51:48.34#ibcon#read 4, iclass 33, count 0 2006.257.07:51:48.34#ibcon#about to read 5, iclass 33, count 0 2006.257.07:51:48.34#ibcon#read 5, iclass 33, count 0 2006.257.07:51:48.34#ibcon#about to read 6, iclass 33, count 0 2006.257.07:51:48.34#ibcon#read 6, iclass 33, count 0 2006.257.07:51:48.34#ibcon#end of sib2, iclass 33, count 0 2006.257.07:51:48.34#ibcon#*after write, iclass 33, count 0 2006.257.07:51:48.34#ibcon#*before return 0, iclass 33, count 0 2006.257.07:51:48.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:48.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.07:51:48.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.07:51:48.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.07:51:48.35$vck44/vb=2,5 2006.257.07:51:48.35#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.07:51:48.35#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.07:51:48.35#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:48.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:48.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:48.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:48.39#ibcon#enter wrdev, iclass 35, count 2 2006.257.07:51:48.39#ibcon#first serial, iclass 35, count 2 2006.257.07:51:48.39#ibcon#enter sib2, iclass 35, count 2 2006.257.07:51:48.39#ibcon#flushed, iclass 35, count 2 2006.257.07:51:48.39#ibcon#about to write, iclass 35, count 2 2006.257.07:51:48.39#ibcon#wrote, iclass 35, count 2 2006.257.07:51:48.39#ibcon#about to read 3, iclass 35, count 2 2006.257.07:51:48.41#ibcon#read 3, iclass 35, count 2 2006.257.07:51:48.41#ibcon#about to read 4, iclass 35, count 2 2006.257.07:51:48.41#ibcon#read 4, iclass 35, count 2 2006.257.07:51:48.41#ibcon#about to read 5, iclass 35, count 2 2006.257.07:51:48.41#ibcon#read 5, iclass 35, count 2 2006.257.07:51:48.41#ibcon#about to read 6, iclass 35, count 2 2006.257.07:51:48.41#ibcon#read 6, iclass 35, count 2 2006.257.07:51:48.41#ibcon#end of sib2, iclass 35, count 2 2006.257.07:51:48.41#ibcon#*mode == 0, iclass 35, count 2 2006.257.07:51:48.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.07:51:48.41#ibcon#[27=AT02-05\r\n] 2006.257.07:51:48.41#ibcon#*before write, iclass 35, count 2 2006.257.07:51:48.41#ibcon#enter sib2, iclass 35, count 2 2006.257.07:51:48.41#ibcon#flushed, iclass 35, count 2 2006.257.07:51:48.41#ibcon#about to write, iclass 35, count 2 2006.257.07:51:48.41#ibcon#wrote, iclass 35, count 2 2006.257.07:51:48.41#ibcon#about to read 3, iclass 35, count 2 2006.257.07:51:48.44#ibcon#read 3, iclass 35, count 2 2006.257.07:51:48.44#ibcon#about to read 4, iclass 35, count 2 2006.257.07:51:48.44#ibcon#read 4, iclass 35, count 2 2006.257.07:51:48.44#ibcon#about to read 5, iclass 35, count 2 2006.257.07:51:48.44#ibcon#read 5, iclass 35, count 2 2006.257.07:51:48.44#ibcon#about to read 6, iclass 35, count 2 2006.257.07:51:48.44#ibcon#read 6, iclass 35, count 2 2006.257.07:51:48.44#ibcon#end of sib2, iclass 35, count 2 2006.257.07:51:48.44#ibcon#*after write, iclass 35, count 2 2006.257.07:51:48.44#ibcon#*before return 0, iclass 35, count 2 2006.257.07:51:48.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:48.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.07:51:48.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.07:51:48.44#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:48.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:48.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:48.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:48.56#ibcon#enter wrdev, iclass 35, count 0 2006.257.07:51:48.56#ibcon#first serial, iclass 35, count 0 2006.257.07:51:48.56#ibcon#enter sib2, iclass 35, count 0 2006.257.07:51:48.56#ibcon#flushed, iclass 35, count 0 2006.257.07:51:48.56#ibcon#about to write, iclass 35, count 0 2006.257.07:51:48.56#ibcon#wrote, iclass 35, count 0 2006.257.07:51:48.56#ibcon#about to read 3, iclass 35, count 0 2006.257.07:51:48.58#ibcon#read 3, iclass 35, count 0 2006.257.07:51:48.58#ibcon#about to read 4, iclass 35, count 0 2006.257.07:51:48.58#ibcon#read 4, iclass 35, count 0 2006.257.07:51:48.58#ibcon#about to read 5, iclass 35, count 0 2006.257.07:51:48.58#ibcon#read 5, iclass 35, count 0 2006.257.07:51:48.58#ibcon#about to read 6, iclass 35, count 0 2006.257.07:51:48.58#ibcon#read 6, iclass 35, count 0 2006.257.07:51:48.58#ibcon#end of sib2, iclass 35, count 0 2006.257.07:51:48.58#ibcon#*mode == 0, iclass 35, count 0 2006.257.07:51:48.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.07:51:48.58#ibcon#[27=USB\r\n] 2006.257.07:51:48.58#ibcon#*before write, iclass 35, count 0 2006.257.07:51:48.58#ibcon#enter sib2, iclass 35, count 0 2006.257.07:51:48.58#ibcon#flushed, iclass 35, count 0 2006.257.07:51:48.58#ibcon#about to write, iclass 35, count 0 2006.257.07:51:48.58#ibcon#wrote, iclass 35, count 0 2006.257.07:51:48.58#ibcon#about to read 3, iclass 35, count 0 2006.257.07:51:48.61#ibcon#read 3, iclass 35, count 0 2006.257.07:51:48.61#ibcon#about to read 4, iclass 35, count 0 2006.257.07:51:48.61#ibcon#read 4, iclass 35, count 0 2006.257.07:51:48.61#ibcon#about to read 5, iclass 35, count 0 2006.257.07:51:48.61#ibcon#read 5, iclass 35, count 0 2006.257.07:51:48.61#ibcon#about to read 6, iclass 35, count 0 2006.257.07:51:48.61#ibcon#read 6, iclass 35, count 0 2006.257.07:51:48.61#ibcon#end of sib2, iclass 35, count 0 2006.257.07:51:48.61#ibcon#*after write, iclass 35, count 0 2006.257.07:51:48.61#ibcon#*before return 0, iclass 35, count 0 2006.257.07:51:48.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:48.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.07:51:48.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.07:51:48.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.07:51:48.62$vck44/vblo=3,649.99 2006.257.07:51:48.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.07:51:48.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.07:51:48.62#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:48.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:48.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:48.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:48.62#ibcon#enter wrdev, iclass 37, count 0 2006.257.07:51:48.62#ibcon#first serial, iclass 37, count 0 2006.257.07:51:48.62#ibcon#enter sib2, iclass 37, count 0 2006.257.07:51:48.62#ibcon#flushed, iclass 37, count 0 2006.257.07:51:48.62#ibcon#about to write, iclass 37, count 0 2006.257.07:51:48.62#ibcon#wrote, iclass 37, count 0 2006.257.07:51:48.62#ibcon#about to read 3, iclass 37, count 0 2006.257.07:51:48.63#ibcon#read 3, iclass 37, count 0 2006.257.07:51:48.63#ibcon#about to read 4, iclass 37, count 0 2006.257.07:51:48.63#ibcon#read 4, iclass 37, count 0 2006.257.07:51:48.63#ibcon#about to read 5, iclass 37, count 0 2006.257.07:51:48.63#ibcon#read 5, iclass 37, count 0 2006.257.07:51:48.63#ibcon#about to read 6, iclass 37, count 0 2006.257.07:51:48.63#ibcon#read 6, iclass 37, count 0 2006.257.07:51:48.63#ibcon#end of sib2, iclass 37, count 0 2006.257.07:51:48.63#ibcon#*mode == 0, iclass 37, count 0 2006.257.07:51:48.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.07:51:48.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.07:51:48.63#ibcon#*before write, iclass 37, count 0 2006.257.07:51:48.63#ibcon#enter sib2, iclass 37, count 0 2006.257.07:51:48.63#ibcon#flushed, iclass 37, count 0 2006.257.07:51:48.63#ibcon#about to write, iclass 37, count 0 2006.257.07:51:48.63#ibcon#wrote, iclass 37, count 0 2006.257.07:51:48.63#ibcon#about to read 3, iclass 37, count 0 2006.257.07:51:48.67#ibcon#read 3, iclass 37, count 0 2006.257.07:51:48.67#ibcon#about to read 4, iclass 37, count 0 2006.257.07:51:48.67#ibcon#read 4, iclass 37, count 0 2006.257.07:51:48.67#ibcon#about to read 5, iclass 37, count 0 2006.257.07:51:48.67#ibcon#read 5, iclass 37, count 0 2006.257.07:51:48.67#ibcon#about to read 6, iclass 37, count 0 2006.257.07:51:48.67#ibcon#read 6, iclass 37, count 0 2006.257.07:51:48.67#ibcon#end of sib2, iclass 37, count 0 2006.257.07:51:48.67#ibcon#*after write, iclass 37, count 0 2006.257.07:51:48.67#ibcon#*before return 0, iclass 37, count 0 2006.257.07:51:48.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:48.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.07:51:48.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.07:51:48.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.07:51:48.68$vck44/vb=3,4 2006.257.07:51:48.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.07:51:48.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.07:51:48.68#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:48.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:48.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:48.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:48.72#ibcon#enter wrdev, iclass 39, count 2 2006.257.07:51:48.72#ibcon#first serial, iclass 39, count 2 2006.257.07:51:48.72#ibcon#enter sib2, iclass 39, count 2 2006.257.07:51:48.72#ibcon#flushed, iclass 39, count 2 2006.257.07:51:48.72#ibcon#about to write, iclass 39, count 2 2006.257.07:51:48.72#ibcon#wrote, iclass 39, count 2 2006.257.07:51:48.72#ibcon#about to read 3, iclass 39, count 2 2006.257.07:51:48.74#ibcon#read 3, iclass 39, count 2 2006.257.07:51:48.74#ibcon#about to read 4, iclass 39, count 2 2006.257.07:51:48.74#ibcon#read 4, iclass 39, count 2 2006.257.07:51:48.74#ibcon#about to read 5, iclass 39, count 2 2006.257.07:51:48.74#ibcon#read 5, iclass 39, count 2 2006.257.07:51:48.74#ibcon#about to read 6, iclass 39, count 2 2006.257.07:51:48.74#ibcon#read 6, iclass 39, count 2 2006.257.07:51:48.74#ibcon#end of sib2, iclass 39, count 2 2006.257.07:51:48.74#ibcon#*mode == 0, iclass 39, count 2 2006.257.07:51:48.74#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.07:51:48.74#ibcon#[27=AT03-04\r\n] 2006.257.07:51:48.74#ibcon#*before write, iclass 39, count 2 2006.257.07:51:48.74#ibcon#enter sib2, iclass 39, count 2 2006.257.07:51:48.74#ibcon#flushed, iclass 39, count 2 2006.257.07:51:48.74#ibcon#about to write, iclass 39, count 2 2006.257.07:51:48.74#ibcon#wrote, iclass 39, count 2 2006.257.07:51:48.74#ibcon#about to read 3, iclass 39, count 2 2006.257.07:51:48.77#ibcon#read 3, iclass 39, count 2 2006.257.07:51:48.77#ibcon#about to read 4, iclass 39, count 2 2006.257.07:51:48.77#ibcon#read 4, iclass 39, count 2 2006.257.07:51:48.77#ibcon#about to read 5, iclass 39, count 2 2006.257.07:51:48.77#ibcon#read 5, iclass 39, count 2 2006.257.07:51:48.77#ibcon#about to read 6, iclass 39, count 2 2006.257.07:51:48.77#ibcon#read 6, iclass 39, count 2 2006.257.07:51:48.77#ibcon#end of sib2, iclass 39, count 2 2006.257.07:51:48.77#ibcon#*after write, iclass 39, count 2 2006.257.07:51:48.77#ibcon#*before return 0, iclass 39, count 2 2006.257.07:51:48.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:48.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.07:51:48.77#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.07:51:48.77#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:48.77#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:48.89#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:48.89#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:48.89#ibcon#enter wrdev, iclass 39, count 0 2006.257.07:51:48.89#ibcon#first serial, iclass 39, count 0 2006.257.07:51:48.89#ibcon#enter sib2, iclass 39, count 0 2006.257.07:51:48.89#ibcon#flushed, iclass 39, count 0 2006.257.07:51:48.89#ibcon#about to write, iclass 39, count 0 2006.257.07:51:48.89#ibcon#wrote, iclass 39, count 0 2006.257.07:51:48.89#ibcon#about to read 3, iclass 39, count 0 2006.257.07:51:48.91#ibcon#read 3, iclass 39, count 0 2006.257.07:51:48.91#ibcon#about to read 4, iclass 39, count 0 2006.257.07:51:48.91#ibcon#read 4, iclass 39, count 0 2006.257.07:51:48.91#ibcon#about to read 5, iclass 39, count 0 2006.257.07:51:48.91#ibcon#read 5, iclass 39, count 0 2006.257.07:51:48.91#ibcon#about to read 6, iclass 39, count 0 2006.257.07:51:48.91#ibcon#read 6, iclass 39, count 0 2006.257.07:51:48.91#ibcon#end of sib2, iclass 39, count 0 2006.257.07:51:48.91#ibcon#*mode == 0, iclass 39, count 0 2006.257.07:51:48.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.07:51:48.91#ibcon#[27=USB\r\n] 2006.257.07:51:48.91#ibcon#*before write, iclass 39, count 0 2006.257.07:51:48.91#ibcon#enter sib2, iclass 39, count 0 2006.257.07:51:48.91#ibcon#flushed, iclass 39, count 0 2006.257.07:51:48.91#ibcon#about to write, iclass 39, count 0 2006.257.07:51:48.91#ibcon#wrote, iclass 39, count 0 2006.257.07:51:48.91#ibcon#about to read 3, iclass 39, count 0 2006.257.07:51:48.94#ibcon#read 3, iclass 39, count 0 2006.257.07:51:48.94#ibcon#about to read 4, iclass 39, count 0 2006.257.07:51:48.94#ibcon#read 4, iclass 39, count 0 2006.257.07:51:48.94#ibcon#about to read 5, iclass 39, count 0 2006.257.07:51:48.94#ibcon#read 5, iclass 39, count 0 2006.257.07:51:48.94#ibcon#about to read 6, iclass 39, count 0 2006.257.07:51:48.94#ibcon#read 6, iclass 39, count 0 2006.257.07:51:48.94#ibcon#end of sib2, iclass 39, count 0 2006.257.07:51:48.94#ibcon#*after write, iclass 39, count 0 2006.257.07:51:48.94#ibcon#*before return 0, iclass 39, count 0 2006.257.07:51:48.94#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:48.94#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.07:51:48.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.07:51:48.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.07:51:48.95$vck44/vblo=4,679.99 2006.257.07:51:48.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.07:51:48.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.07:51:48.95#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:48.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:51:48.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:51:48.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:51:48.95#ibcon#enter wrdev, iclass 3, count 0 2006.257.07:51:48.95#ibcon#first serial, iclass 3, count 0 2006.257.07:51:48.95#ibcon#enter sib2, iclass 3, count 0 2006.257.07:51:48.95#ibcon#flushed, iclass 3, count 0 2006.257.07:51:48.95#ibcon#about to write, iclass 3, count 0 2006.257.07:51:48.95#ibcon#wrote, iclass 3, count 0 2006.257.07:51:48.95#ibcon#about to read 3, iclass 3, count 0 2006.257.07:51:48.96#ibcon#read 3, iclass 3, count 0 2006.257.07:51:48.96#ibcon#about to read 4, iclass 3, count 0 2006.257.07:51:48.96#ibcon#read 4, iclass 3, count 0 2006.257.07:51:48.96#ibcon#about to read 5, iclass 3, count 0 2006.257.07:51:48.96#ibcon#read 5, iclass 3, count 0 2006.257.07:51:48.96#ibcon#about to read 6, iclass 3, count 0 2006.257.07:51:48.96#ibcon#read 6, iclass 3, count 0 2006.257.07:51:48.96#ibcon#end of sib2, iclass 3, count 0 2006.257.07:51:48.96#ibcon#*mode == 0, iclass 3, count 0 2006.257.07:51:48.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.07:51:48.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.07:51:48.96#ibcon#*before write, iclass 3, count 0 2006.257.07:51:48.96#ibcon#enter sib2, iclass 3, count 0 2006.257.07:51:48.96#ibcon#flushed, iclass 3, count 0 2006.257.07:51:48.96#ibcon#about to write, iclass 3, count 0 2006.257.07:51:48.96#ibcon#wrote, iclass 3, count 0 2006.257.07:51:48.96#ibcon#about to read 3, iclass 3, count 0 2006.257.07:51:49.00#ibcon#read 3, iclass 3, count 0 2006.257.07:51:49.00#ibcon#about to read 4, iclass 3, count 0 2006.257.07:51:49.00#ibcon#read 4, iclass 3, count 0 2006.257.07:51:49.00#ibcon#about to read 5, iclass 3, count 0 2006.257.07:51:49.00#ibcon#read 5, iclass 3, count 0 2006.257.07:51:49.00#ibcon#about to read 6, iclass 3, count 0 2006.257.07:51:49.00#ibcon#read 6, iclass 3, count 0 2006.257.07:51:49.00#ibcon#end of sib2, iclass 3, count 0 2006.257.07:51:49.00#ibcon#*after write, iclass 3, count 0 2006.257.07:51:49.00#ibcon#*before return 0, iclass 3, count 0 2006.257.07:51:49.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:51:49.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.07:51:49.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.07:51:49.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.07:51:49.01$vck44/vb=4,5 2006.257.07:51:49.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.07:51:49.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.07:51:49.01#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:49.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:51:49.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:51:49.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:51:49.05#ibcon#enter wrdev, iclass 5, count 2 2006.257.07:51:49.05#ibcon#first serial, iclass 5, count 2 2006.257.07:51:49.05#ibcon#enter sib2, iclass 5, count 2 2006.257.07:51:49.05#ibcon#flushed, iclass 5, count 2 2006.257.07:51:49.05#ibcon#about to write, iclass 5, count 2 2006.257.07:51:49.05#ibcon#wrote, iclass 5, count 2 2006.257.07:51:49.05#ibcon#about to read 3, iclass 5, count 2 2006.257.07:51:49.07#ibcon#read 3, iclass 5, count 2 2006.257.07:51:49.07#ibcon#about to read 4, iclass 5, count 2 2006.257.07:51:49.07#ibcon#read 4, iclass 5, count 2 2006.257.07:51:49.07#ibcon#about to read 5, iclass 5, count 2 2006.257.07:51:49.07#ibcon#read 5, iclass 5, count 2 2006.257.07:51:49.07#ibcon#about to read 6, iclass 5, count 2 2006.257.07:51:49.07#ibcon#read 6, iclass 5, count 2 2006.257.07:51:49.07#ibcon#end of sib2, iclass 5, count 2 2006.257.07:51:49.07#ibcon#*mode == 0, iclass 5, count 2 2006.257.07:51:49.07#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.07:51:49.07#ibcon#[27=AT04-05\r\n] 2006.257.07:51:49.07#ibcon#*before write, iclass 5, count 2 2006.257.07:51:49.07#ibcon#enter sib2, iclass 5, count 2 2006.257.07:51:49.07#ibcon#flushed, iclass 5, count 2 2006.257.07:51:49.07#ibcon#about to write, iclass 5, count 2 2006.257.07:51:49.07#ibcon#wrote, iclass 5, count 2 2006.257.07:51:49.07#ibcon#about to read 3, iclass 5, count 2 2006.257.07:51:49.10#ibcon#read 3, iclass 5, count 2 2006.257.07:51:49.10#ibcon#about to read 4, iclass 5, count 2 2006.257.07:51:49.10#ibcon#read 4, iclass 5, count 2 2006.257.07:51:49.10#ibcon#about to read 5, iclass 5, count 2 2006.257.07:51:49.10#ibcon#read 5, iclass 5, count 2 2006.257.07:51:49.10#ibcon#about to read 6, iclass 5, count 2 2006.257.07:51:49.10#ibcon#read 6, iclass 5, count 2 2006.257.07:51:49.10#ibcon#end of sib2, iclass 5, count 2 2006.257.07:51:49.10#ibcon#*after write, iclass 5, count 2 2006.257.07:51:49.10#ibcon#*before return 0, iclass 5, count 2 2006.257.07:51:49.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:51:49.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.07:51:49.10#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.07:51:49.10#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:49.10#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:51:49.22#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:51:49.22#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:51:49.22#ibcon#enter wrdev, iclass 5, count 0 2006.257.07:51:49.22#ibcon#first serial, iclass 5, count 0 2006.257.07:51:49.22#ibcon#enter sib2, iclass 5, count 0 2006.257.07:51:49.22#ibcon#flushed, iclass 5, count 0 2006.257.07:51:49.22#ibcon#about to write, iclass 5, count 0 2006.257.07:51:49.22#ibcon#wrote, iclass 5, count 0 2006.257.07:51:49.22#ibcon#about to read 3, iclass 5, count 0 2006.257.07:51:49.24#ibcon#read 3, iclass 5, count 0 2006.257.07:51:49.24#ibcon#about to read 4, iclass 5, count 0 2006.257.07:51:49.24#ibcon#read 4, iclass 5, count 0 2006.257.07:51:49.24#ibcon#about to read 5, iclass 5, count 0 2006.257.07:51:49.24#ibcon#read 5, iclass 5, count 0 2006.257.07:51:49.24#ibcon#about to read 6, iclass 5, count 0 2006.257.07:51:49.24#ibcon#read 6, iclass 5, count 0 2006.257.07:51:49.24#ibcon#end of sib2, iclass 5, count 0 2006.257.07:51:49.24#ibcon#*mode == 0, iclass 5, count 0 2006.257.07:51:49.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.07:51:49.24#ibcon#[27=USB\r\n] 2006.257.07:51:49.24#ibcon#*before write, iclass 5, count 0 2006.257.07:51:49.24#ibcon#enter sib2, iclass 5, count 0 2006.257.07:51:49.24#ibcon#flushed, iclass 5, count 0 2006.257.07:51:49.24#ibcon#about to write, iclass 5, count 0 2006.257.07:51:49.24#ibcon#wrote, iclass 5, count 0 2006.257.07:51:49.24#ibcon#about to read 3, iclass 5, count 0 2006.257.07:51:49.27#ibcon#read 3, iclass 5, count 0 2006.257.07:51:49.27#ibcon#about to read 4, iclass 5, count 0 2006.257.07:51:49.27#ibcon#read 4, iclass 5, count 0 2006.257.07:51:49.27#ibcon#about to read 5, iclass 5, count 0 2006.257.07:51:49.27#ibcon#read 5, iclass 5, count 0 2006.257.07:51:49.27#ibcon#about to read 6, iclass 5, count 0 2006.257.07:51:49.27#ibcon#read 6, iclass 5, count 0 2006.257.07:51:49.27#ibcon#end of sib2, iclass 5, count 0 2006.257.07:51:49.27#ibcon#*after write, iclass 5, count 0 2006.257.07:51:49.27#ibcon#*before return 0, iclass 5, count 0 2006.257.07:51:49.27#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:51:49.27#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.07:51:49.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.07:51:49.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.07:51:49.28$vck44/vblo=5,709.99 2006.257.07:51:49.28#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.07:51:49.28#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.07:51:49.28#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:49.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:51:49.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:51:49.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:51:49.28#ibcon#enter wrdev, iclass 7, count 0 2006.257.07:51:49.28#ibcon#first serial, iclass 7, count 0 2006.257.07:51:49.28#ibcon#enter sib2, iclass 7, count 0 2006.257.07:51:49.28#ibcon#flushed, iclass 7, count 0 2006.257.07:51:49.28#ibcon#about to write, iclass 7, count 0 2006.257.07:51:49.28#ibcon#wrote, iclass 7, count 0 2006.257.07:51:49.28#ibcon#about to read 3, iclass 7, count 0 2006.257.07:51:49.29#ibcon#read 3, iclass 7, count 0 2006.257.07:51:49.29#ibcon#about to read 4, iclass 7, count 0 2006.257.07:51:49.29#ibcon#read 4, iclass 7, count 0 2006.257.07:51:49.29#ibcon#about to read 5, iclass 7, count 0 2006.257.07:51:49.29#ibcon#read 5, iclass 7, count 0 2006.257.07:51:49.29#ibcon#about to read 6, iclass 7, count 0 2006.257.07:51:49.29#ibcon#read 6, iclass 7, count 0 2006.257.07:51:49.29#ibcon#end of sib2, iclass 7, count 0 2006.257.07:51:49.29#ibcon#*mode == 0, iclass 7, count 0 2006.257.07:51:49.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.07:51:49.29#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.07:51:49.29#ibcon#*before write, iclass 7, count 0 2006.257.07:51:49.29#ibcon#enter sib2, iclass 7, count 0 2006.257.07:51:49.29#ibcon#flushed, iclass 7, count 0 2006.257.07:51:49.29#ibcon#about to write, iclass 7, count 0 2006.257.07:51:49.29#ibcon#wrote, iclass 7, count 0 2006.257.07:51:49.29#ibcon#about to read 3, iclass 7, count 0 2006.257.07:51:49.33#ibcon#read 3, iclass 7, count 0 2006.257.07:51:49.33#ibcon#about to read 4, iclass 7, count 0 2006.257.07:51:49.33#ibcon#read 4, iclass 7, count 0 2006.257.07:51:49.33#ibcon#about to read 5, iclass 7, count 0 2006.257.07:51:49.33#ibcon#read 5, iclass 7, count 0 2006.257.07:51:49.33#ibcon#about to read 6, iclass 7, count 0 2006.257.07:51:49.33#ibcon#read 6, iclass 7, count 0 2006.257.07:51:49.33#ibcon#end of sib2, iclass 7, count 0 2006.257.07:51:49.33#ibcon#*after write, iclass 7, count 0 2006.257.07:51:49.33#ibcon#*before return 0, iclass 7, count 0 2006.257.07:51:49.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:51:49.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.07:51:49.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.07:51:49.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.07:51:49.33$vck44/vb=5,4 2006.257.07:51:49.34#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.07:51:49.34#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.07:51:49.34#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:49.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:51:49.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:51:49.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:51:49.38#ibcon#enter wrdev, iclass 11, count 2 2006.257.07:51:49.38#ibcon#first serial, iclass 11, count 2 2006.257.07:51:49.38#ibcon#enter sib2, iclass 11, count 2 2006.257.07:51:49.38#ibcon#flushed, iclass 11, count 2 2006.257.07:51:49.38#ibcon#about to write, iclass 11, count 2 2006.257.07:51:49.38#ibcon#wrote, iclass 11, count 2 2006.257.07:51:49.38#ibcon#about to read 3, iclass 11, count 2 2006.257.07:51:49.40#ibcon#read 3, iclass 11, count 2 2006.257.07:51:49.40#ibcon#about to read 4, iclass 11, count 2 2006.257.07:51:49.40#ibcon#read 4, iclass 11, count 2 2006.257.07:51:49.40#ibcon#about to read 5, iclass 11, count 2 2006.257.07:51:49.40#ibcon#read 5, iclass 11, count 2 2006.257.07:51:49.40#ibcon#about to read 6, iclass 11, count 2 2006.257.07:51:49.40#ibcon#read 6, iclass 11, count 2 2006.257.07:51:49.40#ibcon#end of sib2, iclass 11, count 2 2006.257.07:51:49.40#ibcon#*mode == 0, iclass 11, count 2 2006.257.07:51:49.40#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.07:51:49.40#ibcon#[27=AT05-04\r\n] 2006.257.07:51:49.40#ibcon#*before write, iclass 11, count 2 2006.257.07:51:49.40#ibcon#enter sib2, iclass 11, count 2 2006.257.07:51:49.40#ibcon#flushed, iclass 11, count 2 2006.257.07:51:49.40#ibcon#about to write, iclass 11, count 2 2006.257.07:51:49.40#ibcon#wrote, iclass 11, count 2 2006.257.07:51:49.40#ibcon#about to read 3, iclass 11, count 2 2006.257.07:51:49.43#ibcon#read 3, iclass 11, count 2 2006.257.07:51:49.43#ibcon#about to read 4, iclass 11, count 2 2006.257.07:51:49.43#ibcon#read 4, iclass 11, count 2 2006.257.07:51:49.43#ibcon#about to read 5, iclass 11, count 2 2006.257.07:51:49.43#ibcon#read 5, iclass 11, count 2 2006.257.07:51:49.43#ibcon#about to read 6, iclass 11, count 2 2006.257.07:51:49.43#ibcon#read 6, iclass 11, count 2 2006.257.07:51:49.43#ibcon#end of sib2, iclass 11, count 2 2006.257.07:51:49.43#ibcon#*after write, iclass 11, count 2 2006.257.07:51:49.43#ibcon#*before return 0, iclass 11, count 2 2006.257.07:51:49.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:51:49.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.07:51:49.43#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.07:51:49.43#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:49.43#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:51:49.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:51:49.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:51:49.55#ibcon#enter wrdev, iclass 11, count 0 2006.257.07:51:49.55#ibcon#first serial, iclass 11, count 0 2006.257.07:51:49.55#ibcon#enter sib2, iclass 11, count 0 2006.257.07:51:49.55#ibcon#flushed, iclass 11, count 0 2006.257.07:51:49.55#ibcon#about to write, iclass 11, count 0 2006.257.07:51:49.55#ibcon#wrote, iclass 11, count 0 2006.257.07:51:49.55#ibcon#about to read 3, iclass 11, count 0 2006.257.07:51:49.57#ibcon#read 3, iclass 11, count 0 2006.257.07:51:49.57#ibcon#about to read 4, iclass 11, count 0 2006.257.07:51:49.57#ibcon#read 4, iclass 11, count 0 2006.257.07:51:49.57#ibcon#about to read 5, iclass 11, count 0 2006.257.07:51:49.57#ibcon#read 5, iclass 11, count 0 2006.257.07:51:49.57#ibcon#about to read 6, iclass 11, count 0 2006.257.07:51:49.57#ibcon#read 6, iclass 11, count 0 2006.257.07:51:49.57#ibcon#end of sib2, iclass 11, count 0 2006.257.07:51:49.57#ibcon#*mode == 0, iclass 11, count 0 2006.257.07:51:49.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.07:51:49.57#ibcon#[27=USB\r\n] 2006.257.07:51:49.57#ibcon#*before write, iclass 11, count 0 2006.257.07:51:49.57#ibcon#enter sib2, iclass 11, count 0 2006.257.07:51:49.57#ibcon#flushed, iclass 11, count 0 2006.257.07:51:49.57#ibcon#about to write, iclass 11, count 0 2006.257.07:51:49.57#ibcon#wrote, iclass 11, count 0 2006.257.07:51:49.57#ibcon#about to read 3, iclass 11, count 0 2006.257.07:51:49.60#ibcon#read 3, iclass 11, count 0 2006.257.07:51:49.60#ibcon#about to read 4, iclass 11, count 0 2006.257.07:51:49.60#ibcon#read 4, iclass 11, count 0 2006.257.07:51:49.60#ibcon#about to read 5, iclass 11, count 0 2006.257.07:51:49.60#ibcon#read 5, iclass 11, count 0 2006.257.07:51:49.60#ibcon#about to read 6, iclass 11, count 0 2006.257.07:51:49.60#ibcon#read 6, iclass 11, count 0 2006.257.07:51:49.60#ibcon#end of sib2, iclass 11, count 0 2006.257.07:51:49.60#ibcon#*after write, iclass 11, count 0 2006.257.07:51:49.60#ibcon#*before return 0, iclass 11, count 0 2006.257.07:51:49.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:51:49.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.07:51:49.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.07:51:49.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.07:51:49.61$vck44/vblo=6,719.99 2006.257.07:51:49.61#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.07:51:49.61#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.07:51:49.61#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:49.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:49.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:49.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:49.61#ibcon#enter wrdev, iclass 13, count 0 2006.257.07:51:49.61#ibcon#first serial, iclass 13, count 0 2006.257.07:51:49.61#ibcon#enter sib2, iclass 13, count 0 2006.257.07:51:49.61#ibcon#flushed, iclass 13, count 0 2006.257.07:51:49.61#ibcon#about to write, iclass 13, count 0 2006.257.07:51:49.61#ibcon#wrote, iclass 13, count 0 2006.257.07:51:49.61#ibcon#about to read 3, iclass 13, count 0 2006.257.07:51:49.62#ibcon#read 3, iclass 13, count 0 2006.257.07:51:49.62#ibcon#about to read 4, iclass 13, count 0 2006.257.07:51:49.62#ibcon#read 4, iclass 13, count 0 2006.257.07:51:49.62#ibcon#about to read 5, iclass 13, count 0 2006.257.07:51:49.62#ibcon#read 5, iclass 13, count 0 2006.257.07:51:49.62#ibcon#about to read 6, iclass 13, count 0 2006.257.07:51:49.62#ibcon#read 6, iclass 13, count 0 2006.257.07:51:49.62#ibcon#end of sib2, iclass 13, count 0 2006.257.07:51:49.62#ibcon#*mode == 0, iclass 13, count 0 2006.257.07:51:49.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.07:51:49.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.07:51:49.62#ibcon#*before write, iclass 13, count 0 2006.257.07:51:49.62#ibcon#enter sib2, iclass 13, count 0 2006.257.07:51:49.62#ibcon#flushed, iclass 13, count 0 2006.257.07:51:49.62#ibcon#about to write, iclass 13, count 0 2006.257.07:51:49.62#ibcon#wrote, iclass 13, count 0 2006.257.07:51:49.62#ibcon#about to read 3, iclass 13, count 0 2006.257.07:51:49.66#ibcon#read 3, iclass 13, count 0 2006.257.07:51:49.66#ibcon#about to read 4, iclass 13, count 0 2006.257.07:51:49.66#ibcon#read 4, iclass 13, count 0 2006.257.07:51:49.66#ibcon#about to read 5, iclass 13, count 0 2006.257.07:51:49.66#ibcon#read 5, iclass 13, count 0 2006.257.07:51:49.66#ibcon#about to read 6, iclass 13, count 0 2006.257.07:51:49.66#ibcon#read 6, iclass 13, count 0 2006.257.07:51:49.66#ibcon#end of sib2, iclass 13, count 0 2006.257.07:51:49.66#ibcon#*after write, iclass 13, count 0 2006.257.07:51:49.66#ibcon#*before return 0, iclass 13, count 0 2006.257.07:51:49.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:49.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.07:51:49.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.07:51:49.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.07:51:49.67$vck44/vb=6,4 2006.257.07:51:49.67#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.07:51:49.67#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.07:51:49.67#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:49.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:49.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:49.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:49.71#ibcon#enter wrdev, iclass 15, count 2 2006.257.07:51:49.71#ibcon#first serial, iclass 15, count 2 2006.257.07:51:49.71#ibcon#enter sib2, iclass 15, count 2 2006.257.07:51:49.71#ibcon#flushed, iclass 15, count 2 2006.257.07:51:49.71#ibcon#about to write, iclass 15, count 2 2006.257.07:51:49.71#ibcon#wrote, iclass 15, count 2 2006.257.07:51:49.71#ibcon#about to read 3, iclass 15, count 2 2006.257.07:51:49.73#ibcon#read 3, iclass 15, count 2 2006.257.07:51:49.73#ibcon#about to read 4, iclass 15, count 2 2006.257.07:51:49.73#ibcon#read 4, iclass 15, count 2 2006.257.07:51:49.73#ibcon#about to read 5, iclass 15, count 2 2006.257.07:51:49.73#ibcon#read 5, iclass 15, count 2 2006.257.07:51:49.73#ibcon#about to read 6, iclass 15, count 2 2006.257.07:51:49.73#ibcon#read 6, iclass 15, count 2 2006.257.07:51:49.73#ibcon#end of sib2, iclass 15, count 2 2006.257.07:51:49.73#ibcon#*mode == 0, iclass 15, count 2 2006.257.07:51:49.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.07:51:49.73#ibcon#[27=AT06-04\r\n] 2006.257.07:51:49.73#ibcon#*before write, iclass 15, count 2 2006.257.07:51:49.73#ibcon#enter sib2, iclass 15, count 2 2006.257.07:51:49.73#ibcon#flushed, iclass 15, count 2 2006.257.07:51:49.73#ibcon#about to write, iclass 15, count 2 2006.257.07:51:49.73#ibcon#wrote, iclass 15, count 2 2006.257.07:51:49.73#ibcon#about to read 3, iclass 15, count 2 2006.257.07:51:49.76#ibcon#read 3, iclass 15, count 2 2006.257.07:51:49.76#ibcon#about to read 4, iclass 15, count 2 2006.257.07:51:49.76#ibcon#read 4, iclass 15, count 2 2006.257.07:51:49.76#ibcon#about to read 5, iclass 15, count 2 2006.257.07:51:49.76#ibcon#read 5, iclass 15, count 2 2006.257.07:51:49.76#ibcon#about to read 6, iclass 15, count 2 2006.257.07:51:49.76#ibcon#read 6, iclass 15, count 2 2006.257.07:51:49.76#ibcon#end of sib2, iclass 15, count 2 2006.257.07:51:49.76#ibcon#*after write, iclass 15, count 2 2006.257.07:51:49.76#ibcon#*before return 0, iclass 15, count 2 2006.257.07:51:49.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:49.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.07:51:49.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.07:51:49.76#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:49.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:49.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:49.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:49.88#ibcon#enter wrdev, iclass 15, count 0 2006.257.07:51:49.88#ibcon#first serial, iclass 15, count 0 2006.257.07:51:49.88#ibcon#enter sib2, iclass 15, count 0 2006.257.07:51:49.88#ibcon#flushed, iclass 15, count 0 2006.257.07:51:49.88#ibcon#about to write, iclass 15, count 0 2006.257.07:51:49.88#ibcon#wrote, iclass 15, count 0 2006.257.07:51:49.88#ibcon#about to read 3, iclass 15, count 0 2006.257.07:51:49.90#ibcon#read 3, iclass 15, count 0 2006.257.07:51:49.90#ibcon#about to read 4, iclass 15, count 0 2006.257.07:51:49.90#ibcon#read 4, iclass 15, count 0 2006.257.07:51:49.90#ibcon#about to read 5, iclass 15, count 0 2006.257.07:51:49.90#ibcon#read 5, iclass 15, count 0 2006.257.07:51:49.90#ibcon#about to read 6, iclass 15, count 0 2006.257.07:51:49.90#ibcon#read 6, iclass 15, count 0 2006.257.07:51:49.90#ibcon#end of sib2, iclass 15, count 0 2006.257.07:51:49.90#ibcon#*mode == 0, iclass 15, count 0 2006.257.07:51:49.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.07:51:49.90#ibcon#[27=USB\r\n] 2006.257.07:51:49.90#ibcon#*before write, iclass 15, count 0 2006.257.07:51:49.90#ibcon#enter sib2, iclass 15, count 0 2006.257.07:51:49.90#ibcon#flushed, iclass 15, count 0 2006.257.07:51:49.90#ibcon#about to write, iclass 15, count 0 2006.257.07:51:49.90#ibcon#wrote, iclass 15, count 0 2006.257.07:51:49.90#ibcon#about to read 3, iclass 15, count 0 2006.257.07:51:49.93#ibcon#read 3, iclass 15, count 0 2006.257.07:51:49.93#ibcon#about to read 4, iclass 15, count 0 2006.257.07:51:49.93#ibcon#read 4, iclass 15, count 0 2006.257.07:51:49.93#ibcon#about to read 5, iclass 15, count 0 2006.257.07:51:49.93#ibcon#read 5, iclass 15, count 0 2006.257.07:51:49.93#ibcon#about to read 6, iclass 15, count 0 2006.257.07:51:49.93#ibcon#read 6, iclass 15, count 0 2006.257.07:51:49.93#ibcon#end of sib2, iclass 15, count 0 2006.257.07:51:49.93#ibcon#*after write, iclass 15, count 0 2006.257.07:51:49.93#ibcon#*before return 0, iclass 15, count 0 2006.257.07:51:49.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:49.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.07:51:49.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.07:51:49.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.07:51:49.93$vck44/vblo=7,734.99 2006.257.07:51:49.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.07:51:49.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.07:51:49.94#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:49.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:49.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:49.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:49.94#ibcon#enter wrdev, iclass 17, count 0 2006.257.07:51:49.94#ibcon#first serial, iclass 17, count 0 2006.257.07:51:49.94#ibcon#enter sib2, iclass 17, count 0 2006.257.07:51:49.94#ibcon#flushed, iclass 17, count 0 2006.257.07:51:49.94#ibcon#about to write, iclass 17, count 0 2006.257.07:51:49.94#ibcon#wrote, iclass 17, count 0 2006.257.07:51:49.94#ibcon#about to read 3, iclass 17, count 0 2006.257.07:51:49.95#ibcon#read 3, iclass 17, count 0 2006.257.07:51:49.95#ibcon#about to read 4, iclass 17, count 0 2006.257.07:51:49.95#ibcon#read 4, iclass 17, count 0 2006.257.07:51:49.95#ibcon#about to read 5, iclass 17, count 0 2006.257.07:51:49.95#ibcon#read 5, iclass 17, count 0 2006.257.07:51:49.95#ibcon#about to read 6, iclass 17, count 0 2006.257.07:51:49.95#ibcon#read 6, iclass 17, count 0 2006.257.07:51:49.95#ibcon#end of sib2, iclass 17, count 0 2006.257.07:51:49.95#ibcon#*mode == 0, iclass 17, count 0 2006.257.07:51:49.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.07:51:49.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.07:51:49.95#ibcon#*before write, iclass 17, count 0 2006.257.07:51:49.95#ibcon#enter sib2, iclass 17, count 0 2006.257.07:51:49.95#ibcon#flushed, iclass 17, count 0 2006.257.07:51:49.95#ibcon#about to write, iclass 17, count 0 2006.257.07:51:49.95#ibcon#wrote, iclass 17, count 0 2006.257.07:51:49.95#ibcon#about to read 3, iclass 17, count 0 2006.257.07:51:49.99#ibcon#read 3, iclass 17, count 0 2006.257.07:51:49.99#ibcon#about to read 4, iclass 17, count 0 2006.257.07:51:49.99#ibcon#read 4, iclass 17, count 0 2006.257.07:51:49.99#ibcon#about to read 5, iclass 17, count 0 2006.257.07:51:49.99#ibcon#read 5, iclass 17, count 0 2006.257.07:51:49.99#ibcon#about to read 6, iclass 17, count 0 2006.257.07:51:49.99#ibcon#read 6, iclass 17, count 0 2006.257.07:51:49.99#ibcon#end of sib2, iclass 17, count 0 2006.257.07:51:49.99#ibcon#*after write, iclass 17, count 0 2006.257.07:51:49.99#ibcon#*before return 0, iclass 17, count 0 2006.257.07:51:49.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:49.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.07:51:49.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.07:51:49.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.07:51:50.00$vck44/vb=7,4 2006.257.07:51:50.00#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.07:51:50.00#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.07:51:50.00#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:50.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:50.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:50.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:50.04#ibcon#enter wrdev, iclass 19, count 2 2006.257.07:51:50.04#ibcon#first serial, iclass 19, count 2 2006.257.07:51:50.04#ibcon#enter sib2, iclass 19, count 2 2006.257.07:51:50.04#ibcon#flushed, iclass 19, count 2 2006.257.07:51:50.04#ibcon#about to write, iclass 19, count 2 2006.257.07:51:50.04#ibcon#wrote, iclass 19, count 2 2006.257.07:51:50.04#ibcon#about to read 3, iclass 19, count 2 2006.257.07:51:50.06#ibcon#read 3, iclass 19, count 2 2006.257.07:51:50.06#ibcon#about to read 4, iclass 19, count 2 2006.257.07:51:50.06#ibcon#read 4, iclass 19, count 2 2006.257.07:51:50.06#ibcon#about to read 5, iclass 19, count 2 2006.257.07:51:50.06#ibcon#read 5, iclass 19, count 2 2006.257.07:51:50.06#ibcon#about to read 6, iclass 19, count 2 2006.257.07:51:50.06#ibcon#read 6, iclass 19, count 2 2006.257.07:51:50.06#ibcon#end of sib2, iclass 19, count 2 2006.257.07:51:50.06#ibcon#*mode == 0, iclass 19, count 2 2006.257.07:51:50.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.07:51:50.06#ibcon#[27=AT07-04\r\n] 2006.257.07:51:50.06#ibcon#*before write, iclass 19, count 2 2006.257.07:51:50.06#ibcon#enter sib2, iclass 19, count 2 2006.257.07:51:50.06#ibcon#flushed, iclass 19, count 2 2006.257.07:51:50.06#ibcon#about to write, iclass 19, count 2 2006.257.07:51:50.06#ibcon#wrote, iclass 19, count 2 2006.257.07:51:50.06#ibcon#about to read 3, iclass 19, count 2 2006.257.07:51:50.09#ibcon#read 3, iclass 19, count 2 2006.257.07:51:50.09#ibcon#about to read 4, iclass 19, count 2 2006.257.07:51:50.09#ibcon#read 4, iclass 19, count 2 2006.257.07:51:50.09#ibcon#about to read 5, iclass 19, count 2 2006.257.07:51:50.09#ibcon#read 5, iclass 19, count 2 2006.257.07:51:50.09#ibcon#about to read 6, iclass 19, count 2 2006.257.07:51:50.09#ibcon#read 6, iclass 19, count 2 2006.257.07:51:50.09#ibcon#end of sib2, iclass 19, count 2 2006.257.07:51:50.09#ibcon#*after write, iclass 19, count 2 2006.257.07:51:50.09#ibcon#*before return 0, iclass 19, count 2 2006.257.07:51:50.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:50.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.07:51:50.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.07:51:50.09#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:50.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:50.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:50.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:50.21#ibcon#enter wrdev, iclass 19, count 0 2006.257.07:51:50.21#ibcon#first serial, iclass 19, count 0 2006.257.07:51:50.21#ibcon#enter sib2, iclass 19, count 0 2006.257.07:51:50.21#ibcon#flushed, iclass 19, count 0 2006.257.07:51:50.21#ibcon#about to write, iclass 19, count 0 2006.257.07:51:50.21#ibcon#wrote, iclass 19, count 0 2006.257.07:51:50.21#ibcon#about to read 3, iclass 19, count 0 2006.257.07:51:50.23#ibcon#read 3, iclass 19, count 0 2006.257.07:51:50.23#ibcon#about to read 4, iclass 19, count 0 2006.257.07:51:50.23#ibcon#read 4, iclass 19, count 0 2006.257.07:51:50.23#ibcon#about to read 5, iclass 19, count 0 2006.257.07:51:50.23#ibcon#read 5, iclass 19, count 0 2006.257.07:51:50.23#ibcon#about to read 6, iclass 19, count 0 2006.257.07:51:50.23#ibcon#read 6, iclass 19, count 0 2006.257.07:51:50.23#ibcon#end of sib2, iclass 19, count 0 2006.257.07:51:50.23#ibcon#*mode == 0, iclass 19, count 0 2006.257.07:51:50.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.07:51:50.23#ibcon#[27=USB\r\n] 2006.257.07:51:50.23#ibcon#*before write, iclass 19, count 0 2006.257.07:51:50.23#ibcon#enter sib2, iclass 19, count 0 2006.257.07:51:50.23#ibcon#flushed, iclass 19, count 0 2006.257.07:51:50.23#ibcon#about to write, iclass 19, count 0 2006.257.07:51:50.23#ibcon#wrote, iclass 19, count 0 2006.257.07:51:50.23#ibcon#about to read 3, iclass 19, count 0 2006.257.07:51:50.26#ibcon#read 3, iclass 19, count 0 2006.257.07:51:50.26#ibcon#about to read 4, iclass 19, count 0 2006.257.07:51:50.26#ibcon#read 4, iclass 19, count 0 2006.257.07:51:50.26#ibcon#about to read 5, iclass 19, count 0 2006.257.07:51:50.26#ibcon#read 5, iclass 19, count 0 2006.257.07:51:50.26#ibcon#about to read 6, iclass 19, count 0 2006.257.07:51:50.26#ibcon#read 6, iclass 19, count 0 2006.257.07:51:50.26#ibcon#end of sib2, iclass 19, count 0 2006.257.07:51:50.26#ibcon#*after write, iclass 19, count 0 2006.257.07:51:50.26#ibcon#*before return 0, iclass 19, count 0 2006.257.07:51:50.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:50.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.07:51:50.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.07:51:50.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.07:51:50.26$vck44/vblo=8,744.99 2006.257.07:51:50.27#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.07:51:50.27#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.07:51:50.27#ibcon#ireg 17 cls_cnt 0 2006.257.07:51:50.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:50.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:50.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:50.27#ibcon#enter wrdev, iclass 21, count 0 2006.257.07:51:50.27#ibcon#first serial, iclass 21, count 0 2006.257.07:51:50.27#ibcon#enter sib2, iclass 21, count 0 2006.257.07:51:50.27#ibcon#flushed, iclass 21, count 0 2006.257.07:51:50.27#ibcon#about to write, iclass 21, count 0 2006.257.07:51:50.27#ibcon#wrote, iclass 21, count 0 2006.257.07:51:50.27#ibcon#about to read 3, iclass 21, count 0 2006.257.07:51:50.28#ibcon#read 3, iclass 21, count 0 2006.257.07:51:50.28#ibcon#about to read 4, iclass 21, count 0 2006.257.07:51:50.28#ibcon#read 4, iclass 21, count 0 2006.257.07:51:50.28#ibcon#about to read 5, iclass 21, count 0 2006.257.07:51:50.28#ibcon#read 5, iclass 21, count 0 2006.257.07:51:50.28#ibcon#about to read 6, iclass 21, count 0 2006.257.07:51:50.28#ibcon#read 6, iclass 21, count 0 2006.257.07:51:50.28#ibcon#end of sib2, iclass 21, count 0 2006.257.07:51:50.28#ibcon#*mode == 0, iclass 21, count 0 2006.257.07:51:50.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.07:51:50.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.07:51:50.28#ibcon#*before write, iclass 21, count 0 2006.257.07:51:50.28#ibcon#enter sib2, iclass 21, count 0 2006.257.07:51:50.28#ibcon#flushed, iclass 21, count 0 2006.257.07:51:50.28#ibcon#about to write, iclass 21, count 0 2006.257.07:51:50.28#ibcon#wrote, iclass 21, count 0 2006.257.07:51:50.28#ibcon#about to read 3, iclass 21, count 0 2006.257.07:51:50.32#ibcon#read 3, iclass 21, count 0 2006.257.07:51:50.32#ibcon#about to read 4, iclass 21, count 0 2006.257.07:51:50.32#ibcon#read 4, iclass 21, count 0 2006.257.07:51:50.32#ibcon#about to read 5, iclass 21, count 0 2006.257.07:51:50.32#ibcon#read 5, iclass 21, count 0 2006.257.07:51:50.32#ibcon#about to read 6, iclass 21, count 0 2006.257.07:51:50.32#ibcon#read 6, iclass 21, count 0 2006.257.07:51:50.32#ibcon#end of sib2, iclass 21, count 0 2006.257.07:51:50.32#ibcon#*after write, iclass 21, count 0 2006.257.07:51:50.32#ibcon#*before return 0, iclass 21, count 0 2006.257.07:51:50.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:50.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.07:51:50.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.07:51:50.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.07:51:50.33$vck44/vb=8,4 2006.257.07:51:50.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.07:51:50.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.07:51:50.33#ibcon#ireg 11 cls_cnt 2 2006.257.07:51:50.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:50.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:50.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:50.37#ibcon#enter wrdev, iclass 23, count 2 2006.257.07:51:50.37#ibcon#first serial, iclass 23, count 2 2006.257.07:51:50.37#ibcon#enter sib2, iclass 23, count 2 2006.257.07:51:50.37#ibcon#flushed, iclass 23, count 2 2006.257.07:51:50.37#ibcon#about to write, iclass 23, count 2 2006.257.07:51:50.37#ibcon#wrote, iclass 23, count 2 2006.257.07:51:50.37#ibcon#about to read 3, iclass 23, count 2 2006.257.07:51:50.39#ibcon#read 3, iclass 23, count 2 2006.257.07:51:50.39#ibcon#about to read 4, iclass 23, count 2 2006.257.07:51:50.39#ibcon#read 4, iclass 23, count 2 2006.257.07:51:50.39#ibcon#about to read 5, iclass 23, count 2 2006.257.07:51:50.39#ibcon#read 5, iclass 23, count 2 2006.257.07:51:50.39#ibcon#about to read 6, iclass 23, count 2 2006.257.07:51:50.39#ibcon#read 6, iclass 23, count 2 2006.257.07:51:50.39#ibcon#end of sib2, iclass 23, count 2 2006.257.07:51:50.39#ibcon#*mode == 0, iclass 23, count 2 2006.257.07:51:50.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.07:51:50.39#ibcon#[27=AT08-04\r\n] 2006.257.07:51:50.39#ibcon#*before write, iclass 23, count 2 2006.257.07:51:50.39#ibcon#enter sib2, iclass 23, count 2 2006.257.07:51:50.39#ibcon#flushed, iclass 23, count 2 2006.257.07:51:50.39#ibcon#about to write, iclass 23, count 2 2006.257.07:51:50.39#ibcon#wrote, iclass 23, count 2 2006.257.07:51:50.39#ibcon#about to read 3, iclass 23, count 2 2006.257.07:51:50.42#ibcon#read 3, iclass 23, count 2 2006.257.07:51:50.42#ibcon#about to read 4, iclass 23, count 2 2006.257.07:51:50.42#ibcon#read 4, iclass 23, count 2 2006.257.07:51:50.42#ibcon#about to read 5, iclass 23, count 2 2006.257.07:51:50.42#ibcon#read 5, iclass 23, count 2 2006.257.07:51:50.42#ibcon#about to read 6, iclass 23, count 2 2006.257.07:51:50.42#ibcon#read 6, iclass 23, count 2 2006.257.07:51:50.42#ibcon#end of sib2, iclass 23, count 2 2006.257.07:51:50.42#ibcon#*after write, iclass 23, count 2 2006.257.07:51:50.42#ibcon#*before return 0, iclass 23, count 2 2006.257.07:51:50.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:50.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.07:51:50.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.07:51:50.42#ibcon#ireg 7 cls_cnt 0 2006.257.07:51:50.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:50.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:50.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:50.54#ibcon#enter wrdev, iclass 23, count 0 2006.257.07:51:50.54#ibcon#first serial, iclass 23, count 0 2006.257.07:51:50.54#ibcon#enter sib2, iclass 23, count 0 2006.257.07:51:50.54#ibcon#flushed, iclass 23, count 0 2006.257.07:51:50.54#ibcon#about to write, iclass 23, count 0 2006.257.07:51:50.54#ibcon#wrote, iclass 23, count 0 2006.257.07:51:50.54#ibcon#about to read 3, iclass 23, count 0 2006.257.07:51:50.56#ibcon#read 3, iclass 23, count 0 2006.257.07:51:50.56#ibcon#about to read 4, iclass 23, count 0 2006.257.07:51:50.56#ibcon#read 4, iclass 23, count 0 2006.257.07:51:50.56#ibcon#about to read 5, iclass 23, count 0 2006.257.07:51:50.56#ibcon#read 5, iclass 23, count 0 2006.257.07:51:50.56#ibcon#about to read 6, iclass 23, count 0 2006.257.07:51:50.56#ibcon#read 6, iclass 23, count 0 2006.257.07:51:50.56#ibcon#end of sib2, iclass 23, count 0 2006.257.07:51:50.56#ibcon#*mode == 0, iclass 23, count 0 2006.257.07:51:50.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.07:51:50.56#ibcon#[27=USB\r\n] 2006.257.07:51:50.56#ibcon#*before write, iclass 23, count 0 2006.257.07:51:50.56#ibcon#enter sib2, iclass 23, count 0 2006.257.07:51:50.56#ibcon#flushed, iclass 23, count 0 2006.257.07:51:50.56#ibcon#about to write, iclass 23, count 0 2006.257.07:51:50.56#ibcon#wrote, iclass 23, count 0 2006.257.07:51:50.56#ibcon#about to read 3, iclass 23, count 0 2006.257.07:51:50.59#ibcon#read 3, iclass 23, count 0 2006.257.07:51:50.59#ibcon#about to read 4, iclass 23, count 0 2006.257.07:51:50.59#ibcon#read 4, iclass 23, count 0 2006.257.07:51:50.59#ibcon#about to read 5, iclass 23, count 0 2006.257.07:51:50.59#ibcon#read 5, iclass 23, count 0 2006.257.07:51:50.59#ibcon#about to read 6, iclass 23, count 0 2006.257.07:51:50.59#ibcon#read 6, iclass 23, count 0 2006.257.07:51:50.59#ibcon#end of sib2, iclass 23, count 0 2006.257.07:51:50.59#ibcon#*after write, iclass 23, count 0 2006.257.07:51:50.59#ibcon#*before return 0, iclass 23, count 0 2006.257.07:51:50.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:50.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.07:51:50.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.07:51:50.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.07:51:50.60$vck44/vabw=wide 2006.257.07:51:50.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.07:51:50.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.07:51:50.60#ibcon#ireg 8 cls_cnt 0 2006.257.07:51:50.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:50.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:50.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:50.60#ibcon#enter wrdev, iclass 25, count 0 2006.257.07:51:50.60#ibcon#first serial, iclass 25, count 0 2006.257.07:51:50.60#ibcon#enter sib2, iclass 25, count 0 2006.257.07:51:50.60#ibcon#flushed, iclass 25, count 0 2006.257.07:51:50.60#ibcon#about to write, iclass 25, count 0 2006.257.07:51:50.60#ibcon#wrote, iclass 25, count 0 2006.257.07:51:50.60#ibcon#about to read 3, iclass 25, count 0 2006.257.07:51:50.61#ibcon#read 3, iclass 25, count 0 2006.257.07:51:50.61#ibcon#about to read 4, iclass 25, count 0 2006.257.07:51:50.61#ibcon#read 4, iclass 25, count 0 2006.257.07:51:50.61#ibcon#about to read 5, iclass 25, count 0 2006.257.07:51:50.61#ibcon#read 5, iclass 25, count 0 2006.257.07:51:50.61#ibcon#about to read 6, iclass 25, count 0 2006.257.07:51:50.61#ibcon#read 6, iclass 25, count 0 2006.257.07:51:50.61#ibcon#end of sib2, iclass 25, count 0 2006.257.07:51:50.61#ibcon#*mode == 0, iclass 25, count 0 2006.257.07:51:50.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.07:51:50.61#ibcon#[25=BW32\r\n] 2006.257.07:51:50.61#ibcon#*before write, iclass 25, count 0 2006.257.07:51:50.61#ibcon#enter sib2, iclass 25, count 0 2006.257.07:51:50.61#ibcon#flushed, iclass 25, count 0 2006.257.07:51:50.61#ibcon#about to write, iclass 25, count 0 2006.257.07:51:50.61#ibcon#wrote, iclass 25, count 0 2006.257.07:51:50.61#ibcon#about to read 3, iclass 25, count 0 2006.257.07:51:50.64#ibcon#read 3, iclass 25, count 0 2006.257.07:51:50.64#ibcon#about to read 4, iclass 25, count 0 2006.257.07:51:50.64#ibcon#read 4, iclass 25, count 0 2006.257.07:51:50.64#ibcon#about to read 5, iclass 25, count 0 2006.257.07:51:50.64#ibcon#read 5, iclass 25, count 0 2006.257.07:51:50.64#ibcon#about to read 6, iclass 25, count 0 2006.257.07:51:50.64#ibcon#read 6, iclass 25, count 0 2006.257.07:51:50.64#ibcon#end of sib2, iclass 25, count 0 2006.257.07:51:50.64#ibcon#*after write, iclass 25, count 0 2006.257.07:51:50.64#ibcon#*before return 0, iclass 25, count 0 2006.257.07:51:50.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:50.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.07:51:50.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.07:51:50.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.07:51:50.65$vck44/vbbw=wide 2006.257.07:51:50.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.07:51:50.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.07:51:50.65#ibcon#ireg 8 cls_cnt 0 2006.257.07:51:50.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:51:50.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:51:50.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:51:50.70#ibcon#enter wrdev, iclass 27, count 0 2006.257.07:51:50.70#ibcon#first serial, iclass 27, count 0 2006.257.07:51:50.70#ibcon#enter sib2, iclass 27, count 0 2006.257.07:51:50.70#ibcon#flushed, iclass 27, count 0 2006.257.07:51:50.70#ibcon#about to write, iclass 27, count 0 2006.257.07:51:50.70#ibcon#wrote, iclass 27, count 0 2006.257.07:51:50.70#ibcon#about to read 3, iclass 27, count 0 2006.257.07:51:50.72#ibcon#read 3, iclass 27, count 0 2006.257.07:51:50.72#ibcon#about to read 4, iclass 27, count 0 2006.257.07:51:50.72#ibcon#read 4, iclass 27, count 0 2006.257.07:51:50.72#ibcon#about to read 5, iclass 27, count 0 2006.257.07:51:50.72#ibcon#read 5, iclass 27, count 0 2006.257.07:51:50.72#ibcon#about to read 6, iclass 27, count 0 2006.257.07:51:50.72#ibcon#read 6, iclass 27, count 0 2006.257.07:51:50.72#ibcon#end of sib2, iclass 27, count 0 2006.257.07:51:50.72#ibcon#*mode == 0, iclass 27, count 0 2006.257.07:51:50.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.07:51:50.72#ibcon#[27=BW32\r\n] 2006.257.07:51:50.72#ibcon#*before write, iclass 27, count 0 2006.257.07:51:50.72#ibcon#enter sib2, iclass 27, count 0 2006.257.07:51:50.72#ibcon#flushed, iclass 27, count 0 2006.257.07:51:50.72#ibcon#about to write, iclass 27, count 0 2006.257.07:51:50.72#ibcon#wrote, iclass 27, count 0 2006.257.07:51:50.72#ibcon#about to read 3, iclass 27, count 0 2006.257.07:51:50.75#ibcon#read 3, iclass 27, count 0 2006.257.07:51:50.75#ibcon#about to read 4, iclass 27, count 0 2006.257.07:51:50.75#ibcon#read 4, iclass 27, count 0 2006.257.07:51:50.75#ibcon#about to read 5, iclass 27, count 0 2006.257.07:51:50.75#ibcon#read 5, iclass 27, count 0 2006.257.07:51:50.75#ibcon#about to read 6, iclass 27, count 0 2006.257.07:51:50.75#ibcon#read 6, iclass 27, count 0 2006.257.07:51:50.75#ibcon#end of sib2, iclass 27, count 0 2006.257.07:51:50.75#ibcon#*after write, iclass 27, count 0 2006.257.07:51:50.75#ibcon#*before return 0, iclass 27, count 0 2006.257.07:51:50.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:51:50.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.07:51:50.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.07:51:50.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.07:51:50.76$setupk4/ifdk4 2006.257.07:51:50.76$ifdk4/lo= 2006.257.07:51:50.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.07:51:50.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.07:51:50.76$ifdk4/patch= 2006.257.07:51:50.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.07:51:50.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.07:51:50.76$setupk4/!*+20s 2006.257.07:51:56.54#abcon#<5=/15 0.8 2.1 21.11 871012.8\r\n> 2006.257.07:51:56.56#abcon#{5=INTERFACE CLEAR} 2006.257.07:51:56.62#abcon#[5=S1D000X0/0*\r\n] 2006.257.07:52:05.42$setupk4/"tpicd 2006.257.07:52:05.42$setupk4/echo=off 2006.257.07:52:05.42$setupk4/xlog=off 2006.257.07:52:05.42:!2006.257.08:01:49 2006.257.07:52:11.14#trakl#Source acquired 2006.257.07:52:11.15#flagr#flagr/antenna,acquired 2006.257.08:01:49.00:preob 2006.257.08:01:49.14/onsource/TRACKING 2006.257.08:01:49.14:!2006.257.08:01:59 2006.257.08:01:59.00:"tape 2006.257.08:01:59.00:"st=record 2006.257.08:01:59.00:data_valid=on 2006.257.08:01:59.00:midob 2006.257.08:01:59.14/onsource/TRACKING 2006.257.08:01:59.14/wx/20.98,1012.8,88 2006.257.08:01:59.26/cable/+6.4742E-03 2006.257.08:02:00.35/va/01,08,usb,yes,43,46 2006.257.08:02:00.35/va/02,07,usb,yes,46,47 2006.257.08:02:00.35/va/03,08,usb,yes,42,44 2006.257.08:02:00.35/va/04,07,usb,yes,47,50 2006.257.08:02:00.35/va/05,04,usb,yes,42,43 2006.257.08:02:00.35/va/06,04,usb,yes,47,47 2006.257.08:02:00.35/va/07,04,usb,yes,49,49 2006.257.08:02:00.35/va/08,04,usb,yes,41,49 2006.257.08:02:00.58/valo/01,524.99,yes,locked 2006.257.08:02:00.58/valo/02,534.99,yes,locked 2006.257.08:02:00.58/valo/03,564.99,yes,locked 2006.257.08:02:00.58/valo/04,624.99,yes,locked 2006.257.08:02:00.58/valo/05,734.99,yes,locked 2006.257.08:02:00.58/valo/06,814.99,yes,locked 2006.257.08:02:00.58/valo/07,864.99,yes,locked 2006.257.08:02:00.58/valo/08,884.99,yes,locked 2006.257.08:02:01.67/vb/01,04,usb,yes,32,30 2006.257.08:02:01.67/vb/02,05,usb,yes,30,30 2006.257.08:02:01.67/vb/03,04,usb,yes,31,34 2006.257.08:02:01.67/vb/04,05,usb,yes,32,31 2006.257.08:02:01.67/vb/05,04,usb,yes,28,31 2006.257.08:02:01.67/vb/06,04,usb,yes,33,29 2006.257.08:02:01.67/vb/07,04,usb,yes,32,32 2006.257.08:02:01.67/vb/08,04,usb,yes,30,33 2006.257.08:02:01.90/vblo/01,629.99,yes,locked 2006.257.08:02:01.90/vblo/02,634.99,yes,locked 2006.257.08:02:01.90/vblo/03,649.99,yes,locked 2006.257.08:02:01.90/vblo/04,679.99,yes,locked 2006.257.08:02:01.90/vblo/05,709.99,yes,locked 2006.257.08:02:01.90/vblo/06,719.99,yes,locked 2006.257.08:02:01.90/vblo/07,734.99,yes,locked 2006.257.08:02:01.90/vblo/08,744.99,yes,locked 2006.257.08:02:02.05/vabw/8 2006.257.08:02:02.20/vbbw/8 2006.257.08:02:02.29/xfe/off,on,15.2 2006.257.08:02:02.67/ifatt/23,28,28,28 2006.257.08:02:03.07/fmout-gps/S +4.49E-07 2006.257.08:02:03.11:!2006.257.08:02:39 2006.257.08:02:39.00:data_valid=off 2006.257.08:02:39.00:"et 2006.257.08:02:39.00:!+3s 2006.257.08:02:42.01:"tape 2006.257.08:02:42.01:postob 2006.257.08:02:42.16/cable/+6.4755E-03 2006.257.08:02:42.16/wx/20.97,1012.8,88 2006.257.08:02:43.07/fmout-gps/S +4.50E-07 2006.257.08:02:43.07:scan_name=257-0804,jd0609,250 2006.257.08:02:43.07:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.257.08:02:44.14#flagr#flagr/antenna,new-source 2006.257.08:02:44.14:checkk5 2006.257.08:02:44.53/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:02:44.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:02:45.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:02:45.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:02:46.12/chk_obsdata//k5ts1/T2570801??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.08:02:46.51/chk_obsdata//k5ts2/T2570801??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.08:02:46.90/chk_obsdata//k5ts3/T2570801??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.08:02:47.32/chk_obsdata//k5ts4/T2570801??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.08:02:48.04/k5log//k5ts1_log_newline 2006.257.08:02:48.75/k5log//k5ts2_log_newline 2006.257.08:02:49.45/k5log//k5ts3_log_newline 2006.257.08:02:50.17/k5log//k5ts4_log_newline 2006.257.08:02:50.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:02:50.20:setupk4=1 2006.257.08:02:50.20$setupk4/echo=on 2006.257.08:02:50.20$setupk4/pcalon 2006.257.08:02:50.20$pcalon/"no phase cal control is implemented here 2006.257.08:02:50.20$setupk4/"tpicd=stop 2006.257.08:02:50.20$setupk4/"rec=synch_on 2006.257.08:02:50.20$setupk4/"rec_mode=128 2006.257.08:02:50.20$setupk4/!* 2006.257.08:02:50.20$setupk4/recpk4 2006.257.08:02:50.20$recpk4/recpatch= 2006.257.08:02:50.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:02:50.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:02:50.20$setupk4/vck44 2006.257.08:02:50.20$vck44/valo=1,524.99 2006.257.08:02:50.20#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.08:02:50.20#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.08:02:50.20#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:50.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:50.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:50.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:50.20#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:02:50.20#ibcon#first serial, iclass 40, count 0 2006.257.08:02:50.20#ibcon#enter sib2, iclass 40, count 0 2006.257.08:02:50.20#ibcon#flushed, iclass 40, count 0 2006.257.08:02:50.20#ibcon#about to write, iclass 40, count 0 2006.257.08:02:50.20#ibcon#wrote, iclass 40, count 0 2006.257.08:02:50.20#ibcon#about to read 3, iclass 40, count 0 2006.257.08:02:50.21#ibcon#read 3, iclass 40, count 0 2006.257.08:02:50.21#ibcon#about to read 4, iclass 40, count 0 2006.257.08:02:50.21#ibcon#read 4, iclass 40, count 0 2006.257.08:02:50.21#ibcon#about to read 5, iclass 40, count 0 2006.257.08:02:50.21#ibcon#read 5, iclass 40, count 0 2006.257.08:02:50.21#ibcon#about to read 6, iclass 40, count 0 2006.257.08:02:50.21#ibcon#read 6, iclass 40, count 0 2006.257.08:02:50.21#ibcon#end of sib2, iclass 40, count 0 2006.257.08:02:50.21#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:02:50.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:02:50.21#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:02:50.21#ibcon#*before write, iclass 40, count 0 2006.257.08:02:50.21#ibcon#enter sib2, iclass 40, count 0 2006.257.08:02:50.21#ibcon#flushed, iclass 40, count 0 2006.257.08:02:50.21#ibcon#about to write, iclass 40, count 0 2006.257.08:02:50.21#ibcon#wrote, iclass 40, count 0 2006.257.08:02:50.21#ibcon#about to read 3, iclass 40, count 0 2006.257.08:02:50.26#ibcon#read 3, iclass 40, count 0 2006.257.08:02:50.26#ibcon#about to read 4, iclass 40, count 0 2006.257.08:02:50.26#ibcon#read 4, iclass 40, count 0 2006.257.08:02:50.26#ibcon#about to read 5, iclass 40, count 0 2006.257.08:02:50.26#ibcon#read 5, iclass 40, count 0 2006.257.08:02:50.26#ibcon#about to read 6, iclass 40, count 0 2006.257.08:02:50.26#ibcon#read 6, iclass 40, count 0 2006.257.08:02:50.26#ibcon#end of sib2, iclass 40, count 0 2006.257.08:02:50.26#ibcon#*after write, iclass 40, count 0 2006.257.08:02:50.26#ibcon#*before return 0, iclass 40, count 0 2006.257.08:02:50.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:50.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:50.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:02:50.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:02:50.26$vck44/va=1,8 2006.257.08:02:50.26#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.08:02:50.26#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.08:02:50.26#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:50.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:50.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:50.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:50.26#ibcon#enter wrdev, iclass 4, count 2 2006.257.08:02:50.26#ibcon#first serial, iclass 4, count 2 2006.257.08:02:50.26#ibcon#enter sib2, iclass 4, count 2 2006.257.08:02:50.26#ibcon#flushed, iclass 4, count 2 2006.257.08:02:50.26#ibcon#about to write, iclass 4, count 2 2006.257.08:02:50.26#ibcon#wrote, iclass 4, count 2 2006.257.08:02:50.26#ibcon#about to read 3, iclass 4, count 2 2006.257.08:02:50.28#ibcon#read 3, iclass 4, count 2 2006.257.08:02:50.28#ibcon#about to read 4, iclass 4, count 2 2006.257.08:02:50.28#ibcon#read 4, iclass 4, count 2 2006.257.08:02:50.28#ibcon#about to read 5, iclass 4, count 2 2006.257.08:02:50.28#ibcon#read 5, iclass 4, count 2 2006.257.08:02:50.28#ibcon#about to read 6, iclass 4, count 2 2006.257.08:02:50.28#ibcon#read 6, iclass 4, count 2 2006.257.08:02:50.28#ibcon#end of sib2, iclass 4, count 2 2006.257.08:02:50.28#ibcon#*mode == 0, iclass 4, count 2 2006.257.08:02:50.28#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.08:02:50.28#ibcon#[25=AT01-08\r\n] 2006.257.08:02:50.28#ibcon#*before write, iclass 4, count 2 2006.257.08:02:50.28#ibcon#enter sib2, iclass 4, count 2 2006.257.08:02:50.28#ibcon#flushed, iclass 4, count 2 2006.257.08:02:50.28#ibcon#about to write, iclass 4, count 2 2006.257.08:02:50.28#ibcon#wrote, iclass 4, count 2 2006.257.08:02:50.28#ibcon#about to read 3, iclass 4, count 2 2006.257.08:02:50.31#ibcon#read 3, iclass 4, count 2 2006.257.08:02:50.31#ibcon#about to read 4, iclass 4, count 2 2006.257.08:02:50.31#ibcon#read 4, iclass 4, count 2 2006.257.08:02:50.31#ibcon#about to read 5, iclass 4, count 2 2006.257.08:02:50.31#ibcon#read 5, iclass 4, count 2 2006.257.08:02:50.31#ibcon#about to read 6, iclass 4, count 2 2006.257.08:02:50.31#ibcon#read 6, iclass 4, count 2 2006.257.08:02:50.31#ibcon#end of sib2, iclass 4, count 2 2006.257.08:02:50.31#ibcon#*after write, iclass 4, count 2 2006.257.08:02:50.31#ibcon#*before return 0, iclass 4, count 2 2006.257.08:02:50.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:50.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:50.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.08:02:50.31#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:50.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:50.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:50.43#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:50.43#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:02:50.43#ibcon#first serial, iclass 4, count 0 2006.257.08:02:50.43#ibcon#enter sib2, iclass 4, count 0 2006.257.08:02:50.43#ibcon#flushed, iclass 4, count 0 2006.257.08:02:50.43#ibcon#about to write, iclass 4, count 0 2006.257.08:02:50.43#ibcon#wrote, iclass 4, count 0 2006.257.08:02:50.43#ibcon#about to read 3, iclass 4, count 0 2006.257.08:02:50.45#ibcon#read 3, iclass 4, count 0 2006.257.08:02:50.45#ibcon#about to read 4, iclass 4, count 0 2006.257.08:02:50.45#ibcon#read 4, iclass 4, count 0 2006.257.08:02:50.45#ibcon#about to read 5, iclass 4, count 0 2006.257.08:02:50.45#ibcon#read 5, iclass 4, count 0 2006.257.08:02:50.45#ibcon#about to read 6, iclass 4, count 0 2006.257.08:02:50.45#ibcon#read 6, iclass 4, count 0 2006.257.08:02:50.45#ibcon#end of sib2, iclass 4, count 0 2006.257.08:02:50.45#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:02:50.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:02:50.45#ibcon#[25=USB\r\n] 2006.257.08:02:50.45#ibcon#*before write, iclass 4, count 0 2006.257.08:02:50.45#ibcon#enter sib2, iclass 4, count 0 2006.257.08:02:50.45#ibcon#flushed, iclass 4, count 0 2006.257.08:02:50.45#ibcon#about to write, iclass 4, count 0 2006.257.08:02:50.45#ibcon#wrote, iclass 4, count 0 2006.257.08:02:50.45#ibcon#about to read 3, iclass 4, count 0 2006.257.08:02:50.48#ibcon#read 3, iclass 4, count 0 2006.257.08:02:50.48#ibcon#about to read 4, iclass 4, count 0 2006.257.08:02:50.48#ibcon#read 4, iclass 4, count 0 2006.257.08:02:50.48#ibcon#about to read 5, iclass 4, count 0 2006.257.08:02:50.48#ibcon#read 5, iclass 4, count 0 2006.257.08:02:50.48#ibcon#about to read 6, iclass 4, count 0 2006.257.08:02:50.48#ibcon#read 6, iclass 4, count 0 2006.257.08:02:50.48#ibcon#end of sib2, iclass 4, count 0 2006.257.08:02:50.48#ibcon#*after write, iclass 4, count 0 2006.257.08:02:50.48#ibcon#*before return 0, iclass 4, count 0 2006.257.08:02:50.48#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:50.48#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:50.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:02:50.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:02:50.48$vck44/valo=2,534.99 2006.257.08:02:50.48#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.08:02:50.48#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.08:02:50.48#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:50.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:50.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:50.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:50.48#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:02:50.48#ibcon#first serial, iclass 6, count 0 2006.257.08:02:50.48#ibcon#enter sib2, iclass 6, count 0 2006.257.08:02:50.48#ibcon#flushed, iclass 6, count 0 2006.257.08:02:50.48#ibcon#about to write, iclass 6, count 0 2006.257.08:02:50.48#ibcon#wrote, iclass 6, count 0 2006.257.08:02:50.48#ibcon#about to read 3, iclass 6, count 0 2006.257.08:02:50.50#ibcon#read 3, iclass 6, count 0 2006.257.08:02:50.50#ibcon#about to read 4, iclass 6, count 0 2006.257.08:02:50.50#ibcon#read 4, iclass 6, count 0 2006.257.08:02:50.50#ibcon#about to read 5, iclass 6, count 0 2006.257.08:02:50.50#ibcon#read 5, iclass 6, count 0 2006.257.08:02:50.50#ibcon#about to read 6, iclass 6, count 0 2006.257.08:02:50.50#ibcon#read 6, iclass 6, count 0 2006.257.08:02:50.50#ibcon#end of sib2, iclass 6, count 0 2006.257.08:02:50.50#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:02:50.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:02:50.50#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:02:50.50#ibcon#*before write, iclass 6, count 0 2006.257.08:02:50.50#ibcon#enter sib2, iclass 6, count 0 2006.257.08:02:50.50#ibcon#flushed, iclass 6, count 0 2006.257.08:02:50.50#ibcon#about to write, iclass 6, count 0 2006.257.08:02:50.50#ibcon#wrote, iclass 6, count 0 2006.257.08:02:50.50#ibcon#about to read 3, iclass 6, count 0 2006.257.08:02:50.54#ibcon#read 3, iclass 6, count 0 2006.257.08:02:50.54#ibcon#about to read 4, iclass 6, count 0 2006.257.08:02:50.54#ibcon#read 4, iclass 6, count 0 2006.257.08:02:50.54#ibcon#about to read 5, iclass 6, count 0 2006.257.08:02:50.54#ibcon#read 5, iclass 6, count 0 2006.257.08:02:50.54#ibcon#about to read 6, iclass 6, count 0 2006.257.08:02:50.54#ibcon#read 6, iclass 6, count 0 2006.257.08:02:50.54#ibcon#end of sib2, iclass 6, count 0 2006.257.08:02:50.54#ibcon#*after write, iclass 6, count 0 2006.257.08:02:50.54#ibcon#*before return 0, iclass 6, count 0 2006.257.08:02:50.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:50.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:50.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:02:50.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:02:50.54$vck44/va=2,7 2006.257.08:02:50.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.08:02:50.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.08:02:50.54#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:50.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:50.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:50.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:50.60#ibcon#enter wrdev, iclass 10, count 2 2006.257.08:02:50.60#ibcon#first serial, iclass 10, count 2 2006.257.08:02:50.60#ibcon#enter sib2, iclass 10, count 2 2006.257.08:02:50.60#ibcon#flushed, iclass 10, count 2 2006.257.08:02:50.60#ibcon#about to write, iclass 10, count 2 2006.257.08:02:50.60#ibcon#wrote, iclass 10, count 2 2006.257.08:02:50.60#ibcon#about to read 3, iclass 10, count 2 2006.257.08:02:50.62#ibcon#read 3, iclass 10, count 2 2006.257.08:02:50.62#ibcon#about to read 4, iclass 10, count 2 2006.257.08:02:50.62#ibcon#read 4, iclass 10, count 2 2006.257.08:02:50.62#ibcon#about to read 5, iclass 10, count 2 2006.257.08:02:50.62#ibcon#read 5, iclass 10, count 2 2006.257.08:02:50.62#ibcon#about to read 6, iclass 10, count 2 2006.257.08:02:50.62#ibcon#read 6, iclass 10, count 2 2006.257.08:02:50.62#ibcon#end of sib2, iclass 10, count 2 2006.257.08:02:50.62#ibcon#*mode == 0, iclass 10, count 2 2006.257.08:02:50.62#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.08:02:50.62#ibcon#[25=AT02-07\r\n] 2006.257.08:02:50.62#ibcon#*before write, iclass 10, count 2 2006.257.08:02:50.62#ibcon#enter sib2, iclass 10, count 2 2006.257.08:02:50.62#ibcon#flushed, iclass 10, count 2 2006.257.08:02:50.62#ibcon#about to write, iclass 10, count 2 2006.257.08:02:50.62#ibcon#wrote, iclass 10, count 2 2006.257.08:02:50.62#ibcon#about to read 3, iclass 10, count 2 2006.257.08:02:50.65#ibcon#read 3, iclass 10, count 2 2006.257.08:02:50.65#ibcon#about to read 4, iclass 10, count 2 2006.257.08:02:50.65#ibcon#read 4, iclass 10, count 2 2006.257.08:02:50.65#ibcon#about to read 5, iclass 10, count 2 2006.257.08:02:50.65#ibcon#read 5, iclass 10, count 2 2006.257.08:02:50.65#ibcon#about to read 6, iclass 10, count 2 2006.257.08:02:50.65#ibcon#read 6, iclass 10, count 2 2006.257.08:02:50.65#ibcon#end of sib2, iclass 10, count 2 2006.257.08:02:50.65#ibcon#*after write, iclass 10, count 2 2006.257.08:02:50.65#ibcon#*before return 0, iclass 10, count 2 2006.257.08:02:50.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:50.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:50.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.08:02:50.65#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:50.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:50.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:50.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:50.77#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:02:50.77#ibcon#first serial, iclass 10, count 0 2006.257.08:02:50.77#ibcon#enter sib2, iclass 10, count 0 2006.257.08:02:50.77#ibcon#flushed, iclass 10, count 0 2006.257.08:02:50.77#ibcon#about to write, iclass 10, count 0 2006.257.08:02:50.77#ibcon#wrote, iclass 10, count 0 2006.257.08:02:50.77#ibcon#about to read 3, iclass 10, count 0 2006.257.08:02:50.79#ibcon#read 3, iclass 10, count 0 2006.257.08:02:50.79#ibcon#about to read 4, iclass 10, count 0 2006.257.08:02:50.79#ibcon#read 4, iclass 10, count 0 2006.257.08:02:50.79#ibcon#about to read 5, iclass 10, count 0 2006.257.08:02:50.79#ibcon#read 5, iclass 10, count 0 2006.257.08:02:50.79#ibcon#about to read 6, iclass 10, count 0 2006.257.08:02:50.79#ibcon#read 6, iclass 10, count 0 2006.257.08:02:50.79#ibcon#end of sib2, iclass 10, count 0 2006.257.08:02:50.79#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:02:50.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:02:50.79#ibcon#[25=USB\r\n] 2006.257.08:02:50.79#ibcon#*before write, iclass 10, count 0 2006.257.08:02:50.79#ibcon#enter sib2, iclass 10, count 0 2006.257.08:02:50.79#ibcon#flushed, iclass 10, count 0 2006.257.08:02:50.79#ibcon#about to write, iclass 10, count 0 2006.257.08:02:50.79#ibcon#wrote, iclass 10, count 0 2006.257.08:02:50.79#ibcon#about to read 3, iclass 10, count 0 2006.257.08:02:50.82#ibcon#read 3, iclass 10, count 0 2006.257.08:02:50.82#ibcon#about to read 4, iclass 10, count 0 2006.257.08:02:50.82#ibcon#read 4, iclass 10, count 0 2006.257.08:02:50.82#ibcon#about to read 5, iclass 10, count 0 2006.257.08:02:50.82#ibcon#read 5, iclass 10, count 0 2006.257.08:02:50.82#ibcon#about to read 6, iclass 10, count 0 2006.257.08:02:50.82#ibcon#read 6, iclass 10, count 0 2006.257.08:02:50.82#ibcon#end of sib2, iclass 10, count 0 2006.257.08:02:50.82#ibcon#*after write, iclass 10, count 0 2006.257.08:02:50.82#ibcon#*before return 0, iclass 10, count 0 2006.257.08:02:50.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:50.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:50.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:02:50.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:02:50.82$vck44/valo=3,564.99 2006.257.08:02:50.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.08:02:50.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.08:02:50.82#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:50.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:50.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:50.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:50.82#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:02:50.82#ibcon#first serial, iclass 12, count 0 2006.257.08:02:50.82#ibcon#enter sib2, iclass 12, count 0 2006.257.08:02:50.82#ibcon#flushed, iclass 12, count 0 2006.257.08:02:50.82#ibcon#about to write, iclass 12, count 0 2006.257.08:02:50.82#ibcon#wrote, iclass 12, count 0 2006.257.08:02:50.82#ibcon#about to read 3, iclass 12, count 0 2006.257.08:02:50.84#ibcon#read 3, iclass 12, count 0 2006.257.08:02:50.84#ibcon#about to read 4, iclass 12, count 0 2006.257.08:02:50.84#ibcon#read 4, iclass 12, count 0 2006.257.08:02:50.84#ibcon#about to read 5, iclass 12, count 0 2006.257.08:02:50.84#ibcon#read 5, iclass 12, count 0 2006.257.08:02:50.84#ibcon#about to read 6, iclass 12, count 0 2006.257.08:02:50.84#ibcon#read 6, iclass 12, count 0 2006.257.08:02:50.84#ibcon#end of sib2, iclass 12, count 0 2006.257.08:02:50.84#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:02:50.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:02:50.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:02:50.84#ibcon#*before write, iclass 12, count 0 2006.257.08:02:50.84#ibcon#enter sib2, iclass 12, count 0 2006.257.08:02:50.84#ibcon#flushed, iclass 12, count 0 2006.257.08:02:50.84#ibcon#about to write, iclass 12, count 0 2006.257.08:02:50.84#ibcon#wrote, iclass 12, count 0 2006.257.08:02:50.84#ibcon#about to read 3, iclass 12, count 0 2006.257.08:02:50.88#ibcon#read 3, iclass 12, count 0 2006.257.08:02:50.88#ibcon#about to read 4, iclass 12, count 0 2006.257.08:02:50.88#ibcon#read 4, iclass 12, count 0 2006.257.08:02:50.88#ibcon#about to read 5, iclass 12, count 0 2006.257.08:02:50.88#ibcon#read 5, iclass 12, count 0 2006.257.08:02:50.88#ibcon#about to read 6, iclass 12, count 0 2006.257.08:02:50.88#ibcon#read 6, iclass 12, count 0 2006.257.08:02:50.88#ibcon#end of sib2, iclass 12, count 0 2006.257.08:02:50.88#ibcon#*after write, iclass 12, count 0 2006.257.08:02:50.88#ibcon#*before return 0, iclass 12, count 0 2006.257.08:02:50.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:50.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:50.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:02:50.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:02:50.88$vck44/va=3,8 2006.257.08:02:50.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.08:02:50.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.08:02:50.88#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:50.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:50.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:50.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:50.94#ibcon#enter wrdev, iclass 14, count 2 2006.257.08:02:50.94#ibcon#first serial, iclass 14, count 2 2006.257.08:02:50.94#ibcon#enter sib2, iclass 14, count 2 2006.257.08:02:50.94#ibcon#flushed, iclass 14, count 2 2006.257.08:02:50.94#ibcon#about to write, iclass 14, count 2 2006.257.08:02:50.94#ibcon#wrote, iclass 14, count 2 2006.257.08:02:50.94#ibcon#about to read 3, iclass 14, count 2 2006.257.08:02:50.96#ibcon#read 3, iclass 14, count 2 2006.257.08:02:50.96#ibcon#about to read 4, iclass 14, count 2 2006.257.08:02:50.96#ibcon#read 4, iclass 14, count 2 2006.257.08:02:50.96#ibcon#about to read 5, iclass 14, count 2 2006.257.08:02:50.96#ibcon#read 5, iclass 14, count 2 2006.257.08:02:50.96#ibcon#about to read 6, iclass 14, count 2 2006.257.08:02:50.96#ibcon#read 6, iclass 14, count 2 2006.257.08:02:50.96#ibcon#end of sib2, iclass 14, count 2 2006.257.08:02:50.96#ibcon#*mode == 0, iclass 14, count 2 2006.257.08:02:50.96#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.08:02:50.96#ibcon#[25=AT03-08\r\n] 2006.257.08:02:50.96#ibcon#*before write, iclass 14, count 2 2006.257.08:02:50.96#ibcon#enter sib2, iclass 14, count 2 2006.257.08:02:50.96#ibcon#flushed, iclass 14, count 2 2006.257.08:02:50.96#ibcon#about to write, iclass 14, count 2 2006.257.08:02:50.96#ibcon#wrote, iclass 14, count 2 2006.257.08:02:50.96#ibcon#about to read 3, iclass 14, count 2 2006.257.08:02:50.99#ibcon#read 3, iclass 14, count 2 2006.257.08:02:50.99#ibcon#about to read 4, iclass 14, count 2 2006.257.08:02:50.99#ibcon#read 4, iclass 14, count 2 2006.257.08:02:50.99#ibcon#about to read 5, iclass 14, count 2 2006.257.08:02:50.99#ibcon#read 5, iclass 14, count 2 2006.257.08:02:50.99#ibcon#about to read 6, iclass 14, count 2 2006.257.08:02:50.99#ibcon#read 6, iclass 14, count 2 2006.257.08:02:50.99#ibcon#end of sib2, iclass 14, count 2 2006.257.08:02:50.99#ibcon#*after write, iclass 14, count 2 2006.257.08:02:50.99#ibcon#*before return 0, iclass 14, count 2 2006.257.08:02:50.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:50.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:50.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.08:02:50.99#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:50.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:51.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:51.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:51.11#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:02:51.11#ibcon#first serial, iclass 14, count 0 2006.257.08:02:51.11#ibcon#enter sib2, iclass 14, count 0 2006.257.08:02:51.11#ibcon#flushed, iclass 14, count 0 2006.257.08:02:51.11#ibcon#about to write, iclass 14, count 0 2006.257.08:02:51.11#ibcon#wrote, iclass 14, count 0 2006.257.08:02:51.11#ibcon#about to read 3, iclass 14, count 0 2006.257.08:02:51.13#ibcon#read 3, iclass 14, count 0 2006.257.08:02:51.13#ibcon#about to read 4, iclass 14, count 0 2006.257.08:02:51.13#ibcon#read 4, iclass 14, count 0 2006.257.08:02:51.13#ibcon#about to read 5, iclass 14, count 0 2006.257.08:02:51.13#ibcon#read 5, iclass 14, count 0 2006.257.08:02:51.13#ibcon#about to read 6, iclass 14, count 0 2006.257.08:02:51.13#ibcon#read 6, iclass 14, count 0 2006.257.08:02:51.13#ibcon#end of sib2, iclass 14, count 0 2006.257.08:02:51.13#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:02:51.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:02:51.13#ibcon#[25=USB\r\n] 2006.257.08:02:51.13#ibcon#*before write, iclass 14, count 0 2006.257.08:02:51.13#ibcon#enter sib2, iclass 14, count 0 2006.257.08:02:51.13#ibcon#flushed, iclass 14, count 0 2006.257.08:02:51.13#ibcon#about to write, iclass 14, count 0 2006.257.08:02:51.13#ibcon#wrote, iclass 14, count 0 2006.257.08:02:51.13#ibcon#about to read 3, iclass 14, count 0 2006.257.08:02:51.16#ibcon#read 3, iclass 14, count 0 2006.257.08:02:51.16#ibcon#about to read 4, iclass 14, count 0 2006.257.08:02:51.16#ibcon#read 4, iclass 14, count 0 2006.257.08:02:51.16#ibcon#about to read 5, iclass 14, count 0 2006.257.08:02:51.16#ibcon#read 5, iclass 14, count 0 2006.257.08:02:51.16#ibcon#about to read 6, iclass 14, count 0 2006.257.08:02:51.16#ibcon#read 6, iclass 14, count 0 2006.257.08:02:51.16#ibcon#end of sib2, iclass 14, count 0 2006.257.08:02:51.16#ibcon#*after write, iclass 14, count 0 2006.257.08:02:51.16#ibcon#*before return 0, iclass 14, count 0 2006.257.08:02:51.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:51.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:51.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:02:51.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:02:51.16$vck44/valo=4,624.99 2006.257.08:02:51.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.08:02:51.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.08:02:51.16#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:51.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:51.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:51.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:51.16#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:02:51.16#ibcon#first serial, iclass 16, count 0 2006.257.08:02:51.16#ibcon#enter sib2, iclass 16, count 0 2006.257.08:02:51.16#ibcon#flushed, iclass 16, count 0 2006.257.08:02:51.16#ibcon#about to write, iclass 16, count 0 2006.257.08:02:51.16#ibcon#wrote, iclass 16, count 0 2006.257.08:02:51.16#ibcon#about to read 3, iclass 16, count 0 2006.257.08:02:51.18#ibcon#read 3, iclass 16, count 0 2006.257.08:02:51.18#ibcon#about to read 4, iclass 16, count 0 2006.257.08:02:51.18#ibcon#read 4, iclass 16, count 0 2006.257.08:02:51.18#ibcon#about to read 5, iclass 16, count 0 2006.257.08:02:51.18#ibcon#read 5, iclass 16, count 0 2006.257.08:02:51.18#ibcon#about to read 6, iclass 16, count 0 2006.257.08:02:51.18#ibcon#read 6, iclass 16, count 0 2006.257.08:02:51.18#ibcon#end of sib2, iclass 16, count 0 2006.257.08:02:51.18#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:02:51.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:02:51.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:02:51.18#ibcon#*before write, iclass 16, count 0 2006.257.08:02:51.18#ibcon#enter sib2, iclass 16, count 0 2006.257.08:02:51.18#ibcon#flushed, iclass 16, count 0 2006.257.08:02:51.18#ibcon#about to write, iclass 16, count 0 2006.257.08:02:51.18#ibcon#wrote, iclass 16, count 0 2006.257.08:02:51.18#ibcon#about to read 3, iclass 16, count 0 2006.257.08:02:51.22#ibcon#read 3, iclass 16, count 0 2006.257.08:02:51.22#ibcon#about to read 4, iclass 16, count 0 2006.257.08:02:51.22#ibcon#read 4, iclass 16, count 0 2006.257.08:02:51.22#ibcon#about to read 5, iclass 16, count 0 2006.257.08:02:51.22#ibcon#read 5, iclass 16, count 0 2006.257.08:02:51.22#ibcon#about to read 6, iclass 16, count 0 2006.257.08:02:51.22#ibcon#read 6, iclass 16, count 0 2006.257.08:02:51.22#ibcon#end of sib2, iclass 16, count 0 2006.257.08:02:51.22#ibcon#*after write, iclass 16, count 0 2006.257.08:02:51.22#ibcon#*before return 0, iclass 16, count 0 2006.257.08:02:51.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:51.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:51.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:02:51.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:02:51.22$vck44/va=4,7 2006.257.08:02:51.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.08:02:51.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.08:02:51.22#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:51.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:51.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:51.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:51.28#ibcon#enter wrdev, iclass 18, count 2 2006.257.08:02:51.28#ibcon#first serial, iclass 18, count 2 2006.257.08:02:51.28#ibcon#enter sib2, iclass 18, count 2 2006.257.08:02:51.28#ibcon#flushed, iclass 18, count 2 2006.257.08:02:51.28#ibcon#about to write, iclass 18, count 2 2006.257.08:02:51.28#ibcon#wrote, iclass 18, count 2 2006.257.08:02:51.28#ibcon#about to read 3, iclass 18, count 2 2006.257.08:02:51.30#ibcon#read 3, iclass 18, count 2 2006.257.08:02:51.30#ibcon#about to read 4, iclass 18, count 2 2006.257.08:02:51.30#ibcon#read 4, iclass 18, count 2 2006.257.08:02:51.30#ibcon#about to read 5, iclass 18, count 2 2006.257.08:02:51.30#ibcon#read 5, iclass 18, count 2 2006.257.08:02:51.30#ibcon#about to read 6, iclass 18, count 2 2006.257.08:02:51.30#ibcon#read 6, iclass 18, count 2 2006.257.08:02:51.30#ibcon#end of sib2, iclass 18, count 2 2006.257.08:02:51.30#ibcon#*mode == 0, iclass 18, count 2 2006.257.08:02:51.30#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.08:02:51.30#ibcon#[25=AT04-07\r\n] 2006.257.08:02:51.30#ibcon#*before write, iclass 18, count 2 2006.257.08:02:51.30#ibcon#enter sib2, iclass 18, count 2 2006.257.08:02:51.30#ibcon#flushed, iclass 18, count 2 2006.257.08:02:51.30#ibcon#about to write, iclass 18, count 2 2006.257.08:02:51.30#ibcon#wrote, iclass 18, count 2 2006.257.08:02:51.30#ibcon#about to read 3, iclass 18, count 2 2006.257.08:02:51.33#ibcon#read 3, iclass 18, count 2 2006.257.08:02:51.33#ibcon#about to read 4, iclass 18, count 2 2006.257.08:02:51.33#ibcon#read 4, iclass 18, count 2 2006.257.08:02:51.33#ibcon#about to read 5, iclass 18, count 2 2006.257.08:02:51.33#ibcon#read 5, iclass 18, count 2 2006.257.08:02:51.33#ibcon#about to read 6, iclass 18, count 2 2006.257.08:02:51.33#ibcon#read 6, iclass 18, count 2 2006.257.08:02:51.33#ibcon#end of sib2, iclass 18, count 2 2006.257.08:02:51.33#ibcon#*after write, iclass 18, count 2 2006.257.08:02:51.33#ibcon#*before return 0, iclass 18, count 2 2006.257.08:02:51.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:51.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:51.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.08:02:51.33#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:51.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:51.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:51.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:51.45#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:02:51.45#ibcon#first serial, iclass 18, count 0 2006.257.08:02:51.45#ibcon#enter sib2, iclass 18, count 0 2006.257.08:02:51.45#ibcon#flushed, iclass 18, count 0 2006.257.08:02:51.45#ibcon#about to write, iclass 18, count 0 2006.257.08:02:51.45#ibcon#wrote, iclass 18, count 0 2006.257.08:02:51.45#ibcon#about to read 3, iclass 18, count 0 2006.257.08:02:51.47#ibcon#read 3, iclass 18, count 0 2006.257.08:02:51.47#ibcon#about to read 4, iclass 18, count 0 2006.257.08:02:51.47#ibcon#read 4, iclass 18, count 0 2006.257.08:02:51.47#ibcon#about to read 5, iclass 18, count 0 2006.257.08:02:51.47#ibcon#read 5, iclass 18, count 0 2006.257.08:02:51.47#ibcon#about to read 6, iclass 18, count 0 2006.257.08:02:51.47#ibcon#read 6, iclass 18, count 0 2006.257.08:02:51.47#ibcon#end of sib2, iclass 18, count 0 2006.257.08:02:51.47#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:02:51.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:02:51.47#ibcon#[25=USB\r\n] 2006.257.08:02:51.47#ibcon#*before write, iclass 18, count 0 2006.257.08:02:51.47#ibcon#enter sib2, iclass 18, count 0 2006.257.08:02:51.47#ibcon#flushed, iclass 18, count 0 2006.257.08:02:51.47#ibcon#about to write, iclass 18, count 0 2006.257.08:02:51.47#ibcon#wrote, iclass 18, count 0 2006.257.08:02:51.47#ibcon#about to read 3, iclass 18, count 0 2006.257.08:02:51.50#ibcon#read 3, iclass 18, count 0 2006.257.08:02:51.50#ibcon#about to read 4, iclass 18, count 0 2006.257.08:02:51.50#ibcon#read 4, iclass 18, count 0 2006.257.08:02:51.50#ibcon#about to read 5, iclass 18, count 0 2006.257.08:02:51.50#ibcon#read 5, iclass 18, count 0 2006.257.08:02:51.50#ibcon#about to read 6, iclass 18, count 0 2006.257.08:02:51.50#ibcon#read 6, iclass 18, count 0 2006.257.08:02:51.50#ibcon#end of sib2, iclass 18, count 0 2006.257.08:02:51.50#ibcon#*after write, iclass 18, count 0 2006.257.08:02:51.50#ibcon#*before return 0, iclass 18, count 0 2006.257.08:02:51.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:51.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:51.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:02:51.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:02:51.50$vck44/valo=5,734.99 2006.257.08:02:51.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.08:02:51.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.08:02:51.50#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:51.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:51.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:51.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:51.50#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:02:51.50#ibcon#first serial, iclass 20, count 0 2006.257.08:02:51.50#ibcon#enter sib2, iclass 20, count 0 2006.257.08:02:51.50#ibcon#flushed, iclass 20, count 0 2006.257.08:02:51.50#ibcon#about to write, iclass 20, count 0 2006.257.08:02:51.50#ibcon#wrote, iclass 20, count 0 2006.257.08:02:51.50#ibcon#about to read 3, iclass 20, count 0 2006.257.08:02:51.52#ibcon#read 3, iclass 20, count 0 2006.257.08:02:51.52#ibcon#about to read 4, iclass 20, count 0 2006.257.08:02:51.52#ibcon#read 4, iclass 20, count 0 2006.257.08:02:51.52#ibcon#about to read 5, iclass 20, count 0 2006.257.08:02:51.52#ibcon#read 5, iclass 20, count 0 2006.257.08:02:51.52#ibcon#about to read 6, iclass 20, count 0 2006.257.08:02:51.52#ibcon#read 6, iclass 20, count 0 2006.257.08:02:51.52#ibcon#end of sib2, iclass 20, count 0 2006.257.08:02:51.52#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:02:51.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:02:51.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:02:51.52#ibcon#*before write, iclass 20, count 0 2006.257.08:02:51.52#ibcon#enter sib2, iclass 20, count 0 2006.257.08:02:51.52#ibcon#flushed, iclass 20, count 0 2006.257.08:02:51.52#ibcon#about to write, iclass 20, count 0 2006.257.08:02:51.52#ibcon#wrote, iclass 20, count 0 2006.257.08:02:51.52#ibcon#about to read 3, iclass 20, count 0 2006.257.08:02:51.56#ibcon#read 3, iclass 20, count 0 2006.257.08:02:51.56#ibcon#about to read 4, iclass 20, count 0 2006.257.08:02:51.56#ibcon#read 4, iclass 20, count 0 2006.257.08:02:51.56#ibcon#about to read 5, iclass 20, count 0 2006.257.08:02:51.56#ibcon#read 5, iclass 20, count 0 2006.257.08:02:51.56#ibcon#about to read 6, iclass 20, count 0 2006.257.08:02:51.56#ibcon#read 6, iclass 20, count 0 2006.257.08:02:51.56#ibcon#end of sib2, iclass 20, count 0 2006.257.08:02:51.56#ibcon#*after write, iclass 20, count 0 2006.257.08:02:51.56#ibcon#*before return 0, iclass 20, count 0 2006.257.08:02:51.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:51.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:51.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:02:51.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:02:51.56$vck44/va=5,4 2006.257.08:02:51.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.08:02:51.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.08:02:51.56#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:51.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:51.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:51.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:51.62#ibcon#enter wrdev, iclass 22, count 2 2006.257.08:02:51.62#ibcon#first serial, iclass 22, count 2 2006.257.08:02:51.62#ibcon#enter sib2, iclass 22, count 2 2006.257.08:02:51.62#ibcon#flushed, iclass 22, count 2 2006.257.08:02:51.62#ibcon#about to write, iclass 22, count 2 2006.257.08:02:51.62#ibcon#wrote, iclass 22, count 2 2006.257.08:02:51.62#ibcon#about to read 3, iclass 22, count 2 2006.257.08:02:51.64#ibcon#read 3, iclass 22, count 2 2006.257.08:02:51.64#ibcon#about to read 4, iclass 22, count 2 2006.257.08:02:51.64#ibcon#read 4, iclass 22, count 2 2006.257.08:02:51.64#ibcon#about to read 5, iclass 22, count 2 2006.257.08:02:51.64#ibcon#read 5, iclass 22, count 2 2006.257.08:02:51.64#ibcon#about to read 6, iclass 22, count 2 2006.257.08:02:51.64#ibcon#read 6, iclass 22, count 2 2006.257.08:02:51.64#ibcon#end of sib2, iclass 22, count 2 2006.257.08:02:51.64#ibcon#*mode == 0, iclass 22, count 2 2006.257.08:02:51.64#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.08:02:51.64#ibcon#[25=AT05-04\r\n] 2006.257.08:02:51.64#ibcon#*before write, iclass 22, count 2 2006.257.08:02:51.64#ibcon#enter sib2, iclass 22, count 2 2006.257.08:02:51.64#ibcon#flushed, iclass 22, count 2 2006.257.08:02:51.64#ibcon#about to write, iclass 22, count 2 2006.257.08:02:51.64#ibcon#wrote, iclass 22, count 2 2006.257.08:02:51.64#ibcon#about to read 3, iclass 22, count 2 2006.257.08:02:51.67#ibcon#read 3, iclass 22, count 2 2006.257.08:02:51.67#ibcon#about to read 4, iclass 22, count 2 2006.257.08:02:51.67#ibcon#read 4, iclass 22, count 2 2006.257.08:02:51.67#ibcon#about to read 5, iclass 22, count 2 2006.257.08:02:51.67#ibcon#read 5, iclass 22, count 2 2006.257.08:02:51.67#ibcon#about to read 6, iclass 22, count 2 2006.257.08:02:51.67#ibcon#read 6, iclass 22, count 2 2006.257.08:02:51.67#ibcon#end of sib2, iclass 22, count 2 2006.257.08:02:51.67#ibcon#*after write, iclass 22, count 2 2006.257.08:02:51.67#ibcon#*before return 0, iclass 22, count 2 2006.257.08:02:51.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:51.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:51.67#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.08:02:51.67#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:51.67#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:51.79#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:51.79#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:51.79#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:02:51.79#ibcon#first serial, iclass 22, count 0 2006.257.08:02:51.79#ibcon#enter sib2, iclass 22, count 0 2006.257.08:02:51.79#ibcon#flushed, iclass 22, count 0 2006.257.08:02:51.79#ibcon#about to write, iclass 22, count 0 2006.257.08:02:51.79#ibcon#wrote, iclass 22, count 0 2006.257.08:02:51.79#ibcon#about to read 3, iclass 22, count 0 2006.257.08:02:51.81#ibcon#read 3, iclass 22, count 0 2006.257.08:02:51.81#ibcon#about to read 4, iclass 22, count 0 2006.257.08:02:51.81#ibcon#read 4, iclass 22, count 0 2006.257.08:02:51.81#ibcon#about to read 5, iclass 22, count 0 2006.257.08:02:51.81#ibcon#read 5, iclass 22, count 0 2006.257.08:02:51.81#ibcon#about to read 6, iclass 22, count 0 2006.257.08:02:51.81#ibcon#read 6, iclass 22, count 0 2006.257.08:02:51.81#ibcon#end of sib2, iclass 22, count 0 2006.257.08:02:51.81#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:02:51.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:02:51.81#ibcon#[25=USB\r\n] 2006.257.08:02:51.81#ibcon#*before write, iclass 22, count 0 2006.257.08:02:51.81#ibcon#enter sib2, iclass 22, count 0 2006.257.08:02:51.81#ibcon#flushed, iclass 22, count 0 2006.257.08:02:51.81#ibcon#about to write, iclass 22, count 0 2006.257.08:02:51.81#ibcon#wrote, iclass 22, count 0 2006.257.08:02:51.81#ibcon#about to read 3, iclass 22, count 0 2006.257.08:02:51.84#ibcon#read 3, iclass 22, count 0 2006.257.08:02:51.84#ibcon#about to read 4, iclass 22, count 0 2006.257.08:02:51.84#ibcon#read 4, iclass 22, count 0 2006.257.08:02:51.84#ibcon#about to read 5, iclass 22, count 0 2006.257.08:02:51.84#ibcon#read 5, iclass 22, count 0 2006.257.08:02:51.84#ibcon#about to read 6, iclass 22, count 0 2006.257.08:02:51.84#ibcon#read 6, iclass 22, count 0 2006.257.08:02:51.84#ibcon#end of sib2, iclass 22, count 0 2006.257.08:02:51.84#ibcon#*after write, iclass 22, count 0 2006.257.08:02:51.84#ibcon#*before return 0, iclass 22, count 0 2006.257.08:02:51.84#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:51.84#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:51.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:02:51.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:02:51.84$vck44/valo=6,814.99 2006.257.08:02:51.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.08:02:51.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.08:02:51.84#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:51.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:51.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:51.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:51.84#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:02:51.84#ibcon#first serial, iclass 24, count 0 2006.257.08:02:51.84#ibcon#enter sib2, iclass 24, count 0 2006.257.08:02:51.84#ibcon#flushed, iclass 24, count 0 2006.257.08:02:51.84#ibcon#about to write, iclass 24, count 0 2006.257.08:02:51.84#ibcon#wrote, iclass 24, count 0 2006.257.08:02:51.84#ibcon#about to read 3, iclass 24, count 0 2006.257.08:02:51.86#ibcon#read 3, iclass 24, count 0 2006.257.08:02:51.86#ibcon#about to read 4, iclass 24, count 0 2006.257.08:02:51.86#ibcon#read 4, iclass 24, count 0 2006.257.08:02:51.86#ibcon#about to read 5, iclass 24, count 0 2006.257.08:02:51.86#ibcon#read 5, iclass 24, count 0 2006.257.08:02:51.86#ibcon#about to read 6, iclass 24, count 0 2006.257.08:02:51.86#ibcon#read 6, iclass 24, count 0 2006.257.08:02:51.86#ibcon#end of sib2, iclass 24, count 0 2006.257.08:02:51.86#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:02:51.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:02:51.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:02:51.86#ibcon#*before write, iclass 24, count 0 2006.257.08:02:51.86#ibcon#enter sib2, iclass 24, count 0 2006.257.08:02:51.86#ibcon#flushed, iclass 24, count 0 2006.257.08:02:51.86#ibcon#about to write, iclass 24, count 0 2006.257.08:02:51.86#ibcon#wrote, iclass 24, count 0 2006.257.08:02:51.86#ibcon#about to read 3, iclass 24, count 0 2006.257.08:02:51.90#ibcon#read 3, iclass 24, count 0 2006.257.08:02:51.90#ibcon#about to read 4, iclass 24, count 0 2006.257.08:02:51.90#ibcon#read 4, iclass 24, count 0 2006.257.08:02:51.90#ibcon#about to read 5, iclass 24, count 0 2006.257.08:02:51.90#ibcon#read 5, iclass 24, count 0 2006.257.08:02:51.90#ibcon#about to read 6, iclass 24, count 0 2006.257.08:02:51.90#ibcon#read 6, iclass 24, count 0 2006.257.08:02:51.90#ibcon#end of sib2, iclass 24, count 0 2006.257.08:02:51.90#ibcon#*after write, iclass 24, count 0 2006.257.08:02:51.90#ibcon#*before return 0, iclass 24, count 0 2006.257.08:02:51.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:51.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:51.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:02:51.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:02:51.90$vck44/va=6,4 2006.257.08:02:51.90#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.08:02:51.90#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.08:02:51.90#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:51.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:51.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:51.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:51.96#ibcon#enter wrdev, iclass 26, count 2 2006.257.08:02:51.96#ibcon#first serial, iclass 26, count 2 2006.257.08:02:51.96#ibcon#enter sib2, iclass 26, count 2 2006.257.08:02:51.96#ibcon#flushed, iclass 26, count 2 2006.257.08:02:51.96#ibcon#about to write, iclass 26, count 2 2006.257.08:02:51.96#ibcon#wrote, iclass 26, count 2 2006.257.08:02:51.96#ibcon#about to read 3, iclass 26, count 2 2006.257.08:02:51.98#ibcon#read 3, iclass 26, count 2 2006.257.08:02:51.98#ibcon#about to read 4, iclass 26, count 2 2006.257.08:02:51.98#ibcon#read 4, iclass 26, count 2 2006.257.08:02:51.98#ibcon#about to read 5, iclass 26, count 2 2006.257.08:02:51.98#ibcon#read 5, iclass 26, count 2 2006.257.08:02:51.98#ibcon#about to read 6, iclass 26, count 2 2006.257.08:02:51.98#ibcon#read 6, iclass 26, count 2 2006.257.08:02:51.98#ibcon#end of sib2, iclass 26, count 2 2006.257.08:02:51.98#ibcon#*mode == 0, iclass 26, count 2 2006.257.08:02:51.98#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.08:02:51.98#ibcon#[25=AT06-04\r\n] 2006.257.08:02:51.98#ibcon#*before write, iclass 26, count 2 2006.257.08:02:51.98#ibcon#enter sib2, iclass 26, count 2 2006.257.08:02:51.98#ibcon#flushed, iclass 26, count 2 2006.257.08:02:51.98#ibcon#about to write, iclass 26, count 2 2006.257.08:02:51.98#ibcon#wrote, iclass 26, count 2 2006.257.08:02:51.98#ibcon#about to read 3, iclass 26, count 2 2006.257.08:02:52.01#ibcon#read 3, iclass 26, count 2 2006.257.08:02:52.01#ibcon#about to read 4, iclass 26, count 2 2006.257.08:02:52.01#ibcon#read 4, iclass 26, count 2 2006.257.08:02:52.01#ibcon#about to read 5, iclass 26, count 2 2006.257.08:02:52.01#ibcon#read 5, iclass 26, count 2 2006.257.08:02:52.01#ibcon#about to read 6, iclass 26, count 2 2006.257.08:02:52.01#ibcon#read 6, iclass 26, count 2 2006.257.08:02:52.01#ibcon#end of sib2, iclass 26, count 2 2006.257.08:02:52.01#ibcon#*after write, iclass 26, count 2 2006.257.08:02:52.01#ibcon#*before return 0, iclass 26, count 2 2006.257.08:02:52.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:52.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:52.01#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.08:02:52.01#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:52.01#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:52.13#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:52.13#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:52.13#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:02:52.13#ibcon#first serial, iclass 26, count 0 2006.257.08:02:52.13#ibcon#enter sib2, iclass 26, count 0 2006.257.08:02:52.13#ibcon#flushed, iclass 26, count 0 2006.257.08:02:52.13#ibcon#about to write, iclass 26, count 0 2006.257.08:02:52.13#ibcon#wrote, iclass 26, count 0 2006.257.08:02:52.13#ibcon#about to read 3, iclass 26, count 0 2006.257.08:02:52.15#ibcon#read 3, iclass 26, count 0 2006.257.08:02:52.15#ibcon#about to read 4, iclass 26, count 0 2006.257.08:02:52.15#ibcon#read 4, iclass 26, count 0 2006.257.08:02:52.15#ibcon#about to read 5, iclass 26, count 0 2006.257.08:02:52.15#ibcon#read 5, iclass 26, count 0 2006.257.08:02:52.15#ibcon#about to read 6, iclass 26, count 0 2006.257.08:02:52.15#ibcon#read 6, iclass 26, count 0 2006.257.08:02:52.15#ibcon#end of sib2, iclass 26, count 0 2006.257.08:02:52.15#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:02:52.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:02:52.15#ibcon#[25=USB\r\n] 2006.257.08:02:52.15#ibcon#*before write, iclass 26, count 0 2006.257.08:02:52.15#ibcon#enter sib2, iclass 26, count 0 2006.257.08:02:52.15#ibcon#flushed, iclass 26, count 0 2006.257.08:02:52.15#ibcon#about to write, iclass 26, count 0 2006.257.08:02:52.15#ibcon#wrote, iclass 26, count 0 2006.257.08:02:52.15#ibcon#about to read 3, iclass 26, count 0 2006.257.08:02:52.18#ibcon#read 3, iclass 26, count 0 2006.257.08:02:52.18#ibcon#about to read 4, iclass 26, count 0 2006.257.08:02:52.18#ibcon#read 4, iclass 26, count 0 2006.257.08:02:52.18#ibcon#about to read 5, iclass 26, count 0 2006.257.08:02:52.18#ibcon#read 5, iclass 26, count 0 2006.257.08:02:52.18#ibcon#about to read 6, iclass 26, count 0 2006.257.08:02:52.18#ibcon#read 6, iclass 26, count 0 2006.257.08:02:52.18#ibcon#end of sib2, iclass 26, count 0 2006.257.08:02:52.18#ibcon#*after write, iclass 26, count 0 2006.257.08:02:52.18#ibcon#*before return 0, iclass 26, count 0 2006.257.08:02:52.18#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:52.18#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:52.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:02:52.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:02:52.18$vck44/valo=7,864.99 2006.257.08:02:52.18#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.08:02:52.18#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.08:02:52.18#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:52.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:52.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:52.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:52.18#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:02:52.18#ibcon#first serial, iclass 28, count 0 2006.257.08:02:52.18#ibcon#enter sib2, iclass 28, count 0 2006.257.08:02:52.18#ibcon#flushed, iclass 28, count 0 2006.257.08:02:52.18#ibcon#about to write, iclass 28, count 0 2006.257.08:02:52.18#ibcon#wrote, iclass 28, count 0 2006.257.08:02:52.18#ibcon#about to read 3, iclass 28, count 0 2006.257.08:02:52.20#ibcon#read 3, iclass 28, count 0 2006.257.08:02:52.20#ibcon#about to read 4, iclass 28, count 0 2006.257.08:02:52.20#ibcon#read 4, iclass 28, count 0 2006.257.08:02:52.20#ibcon#about to read 5, iclass 28, count 0 2006.257.08:02:52.20#ibcon#read 5, iclass 28, count 0 2006.257.08:02:52.20#ibcon#about to read 6, iclass 28, count 0 2006.257.08:02:52.20#ibcon#read 6, iclass 28, count 0 2006.257.08:02:52.20#ibcon#end of sib2, iclass 28, count 0 2006.257.08:02:52.20#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:02:52.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:02:52.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:02:52.20#ibcon#*before write, iclass 28, count 0 2006.257.08:02:52.20#ibcon#enter sib2, iclass 28, count 0 2006.257.08:02:52.20#ibcon#flushed, iclass 28, count 0 2006.257.08:02:52.20#ibcon#about to write, iclass 28, count 0 2006.257.08:02:52.20#ibcon#wrote, iclass 28, count 0 2006.257.08:02:52.20#ibcon#about to read 3, iclass 28, count 0 2006.257.08:02:52.24#ibcon#read 3, iclass 28, count 0 2006.257.08:02:52.24#ibcon#about to read 4, iclass 28, count 0 2006.257.08:02:52.24#ibcon#read 4, iclass 28, count 0 2006.257.08:02:52.24#ibcon#about to read 5, iclass 28, count 0 2006.257.08:02:52.24#ibcon#read 5, iclass 28, count 0 2006.257.08:02:52.24#ibcon#about to read 6, iclass 28, count 0 2006.257.08:02:52.24#ibcon#read 6, iclass 28, count 0 2006.257.08:02:52.24#ibcon#end of sib2, iclass 28, count 0 2006.257.08:02:52.24#ibcon#*after write, iclass 28, count 0 2006.257.08:02:52.24#ibcon#*before return 0, iclass 28, count 0 2006.257.08:02:52.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:52.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:52.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:02:52.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:02:52.24$vck44/va=7,4 2006.257.08:02:52.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.08:02:52.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.08:02:52.24#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:52.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:52.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:52.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:52.30#ibcon#enter wrdev, iclass 30, count 2 2006.257.08:02:52.30#ibcon#first serial, iclass 30, count 2 2006.257.08:02:52.30#ibcon#enter sib2, iclass 30, count 2 2006.257.08:02:52.30#ibcon#flushed, iclass 30, count 2 2006.257.08:02:52.30#ibcon#about to write, iclass 30, count 2 2006.257.08:02:52.30#ibcon#wrote, iclass 30, count 2 2006.257.08:02:52.30#ibcon#about to read 3, iclass 30, count 2 2006.257.08:02:52.32#ibcon#read 3, iclass 30, count 2 2006.257.08:02:52.32#ibcon#about to read 4, iclass 30, count 2 2006.257.08:02:52.32#ibcon#read 4, iclass 30, count 2 2006.257.08:02:52.32#ibcon#about to read 5, iclass 30, count 2 2006.257.08:02:52.32#ibcon#read 5, iclass 30, count 2 2006.257.08:02:52.32#ibcon#about to read 6, iclass 30, count 2 2006.257.08:02:52.32#ibcon#read 6, iclass 30, count 2 2006.257.08:02:52.32#ibcon#end of sib2, iclass 30, count 2 2006.257.08:02:52.32#ibcon#*mode == 0, iclass 30, count 2 2006.257.08:02:52.32#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.08:02:52.32#ibcon#[25=AT07-04\r\n] 2006.257.08:02:52.32#ibcon#*before write, iclass 30, count 2 2006.257.08:02:52.32#ibcon#enter sib2, iclass 30, count 2 2006.257.08:02:52.32#ibcon#flushed, iclass 30, count 2 2006.257.08:02:52.32#ibcon#about to write, iclass 30, count 2 2006.257.08:02:52.32#ibcon#wrote, iclass 30, count 2 2006.257.08:02:52.32#ibcon#about to read 3, iclass 30, count 2 2006.257.08:02:52.35#ibcon#read 3, iclass 30, count 2 2006.257.08:02:52.35#ibcon#about to read 4, iclass 30, count 2 2006.257.08:02:52.35#ibcon#read 4, iclass 30, count 2 2006.257.08:02:52.35#ibcon#about to read 5, iclass 30, count 2 2006.257.08:02:52.35#ibcon#read 5, iclass 30, count 2 2006.257.08:02:52.35#ibcon#about to read 6, iclass 30, count 2 2006.257.08:02:52.35#ibcon#read 6, iclass 30, count 2 2006.257.08:02:52.35#ibcon#end of sib2, iclass 30, count 2 2006.257.08:02:52.35#ibcon#*after write, iclass 30, count 2 2006.257.08:02:52.35#ibcon#*before return 0, iclass 30, count 2 2006.257.08:02:52.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:52.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:52.35#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.08:02:52.35#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:52.35#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:52.47#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:52.47#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:52.47#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:02:52.47#ibcon#first serial, iclass 30, count 0 2006.257.08:02:52.47#ibcon#enter sib2, iclass 30, count 0 2006.257.08:02:52.47#ibcon#flushed, iclass 30, count 0 2006.257.08:02:52.47#ibcon#about to write, iclass 30, count 0 2006.257.08:02:52.47#ibcon#wrote, iclass 30, count 0 2006.257.08:02:52.47#ibcon#about to read 3, iclass 30, count 0 2006.257.08:02:52.49#ibcon#read 3, iclass 30, count 0 2006.257.08:02:52.49#ibcon#about to read 4, iclass 30, count 0 2006.257.08:02:52.49#ibcon#read 4, iclass 30, count 0 2006.257.08:02:52.49#ibcon#about to read 5, iclass 30, count 0 2006.257.08:02:52.49#ibcon#read 5, iclass 30, count 0 2006.257.08:02:52.49#ibcon#about to read 6, iclass 30, count 0 2006.257.08:02:52.49#ibcon#read 6, iclass 30, count 0 2006.257.08:02:52.49#ibcon#end of sib2, iclass 30, count 0 2006.257.08:02:52.49#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:02:52.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:02:52.49#ibcon#[25=USB\r\n] 2006.257.08:02:52.49#ibcon#*before write, iclass 30, count 0 2006.257.08:02:52.49#ibcon#enter sib2, iclass 30, count 0 2006.257.08:02:52.49#ibcon#flushed, iclass 30, count 0 2006.257.08:02:52.49#ibcon#about to write, iclass 30, count 0 2006.257.08:02:52.49#ibcon#wrote, iclass 30, count 0 2006.257.08:02:52.49#ibcon#about to read 3, iclass 30, count 0 2006.257.08:02:52.52#ibcon#read 3, iclass 30, count 0 2006.257.08:02:52.52#ibcon#about to read 4, iclass 30, count 0 2006.257.08:02:52.52#ibcon#read 4, iclass 30, count 0 2006.257.08:02:52.52#ibcon#about to read 5, iclass 30, count 0 2006.257.08:02:52.52#ibcon#read 5, iclass 30, count 0 2006.257.08:02:52.52#ibcon#about to read 6, iclass 30, count 0 2006.257.08:02:52.52#ibcon#read 6, iclass 30, count 0 2006.257.08:02:52.52#ibcon#end of sib2, iclass 30, count 0 2006.257.08:02:52.52#ibcon#*after write, iclass 30, count 0 2006.257.08:02:52.52#ibcon#*before return 0, iclass 30, count 0 2006.257.08:02:52.52#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:52.52#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:52.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:02:52.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:02:52.52$vck44/valo=8,884.99 2006.257.08:02:52.52#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.08:02:52.52#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.08:02:52.52#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:52.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:52.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:52.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:52.52#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:02:52.52#ibcon#first serial, iclass 32, count 0 2006.257.08:02:52.52#ibcon#enter sib2, iclass 32, count 0 2006.257.08:02:52.52#ibcon#flushed, iclass 32, count 0 2006.257.08:02:52.52#ibcon#about to write, iclass 32, count 0 2006.257.08:02:52.52#ibcon#wrote, iclass 32, count 0 2006.257.08:02:52.52#ibcon#about to read 3, iclass 32, count 0 2006.257.08:02:52.54#ibcon#read 3, iclass 32, count 0 2006.257.08:02:52.54#ibcon#about to read 4, iclass 32, count 0 2006.257.08:02:52.54#ibcon#read 4, iclass 32, count 0 2006.257.08:02:52.54#ibcon#about to read 5, iclass 32, count 0 2006.257.08:02:52.54#ibcon#read 5, iclass 32, count 0 2006.257.08:02:52.54#ibcon#about to read 6, iclass 32, count 0 2006.257.08:02:52.54#ibcon#read 6, iclass 32, count 0 2006.257.08:02:52.54#ibcon#end of sib2, iclass 32, count 0 2006.257.08:02:52.54#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:02:52.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:02:52.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:02:52.54#ibcon#*before write, iclass 32, count 0 2006.257.08:02:52.54#ibcon#enter sib2, iclass 32, count 0 2006.257.08:02:52.54#ibcon#flushed, iclass 32, count 0 2006.257.08:02:52.54#ibcon#about to write, iclass 32, count 0 2006.257.08:02:52.54#ibcon#wrote, iclass 32, count 0 2006.257.08:02:52.54#ibcon#about to read 3, iclass 32, count 0 2006.257.08:02:52.58#ibcon#read 3, iclass 32, count 0 2006.257.08:02:52.58#ibcon#about to read 4, iclass 32, count 0 2006.257.08:02:52.58#ibcon#read 4, iclass 32, count 0 2006.257.08:02:52.58#ibcon#about to read 5, iclass 32, count 0 2006.257.08:02:52.58#ibcon#read 5, iclass 32, count 0 2006.257.08:02:52.58#ibcon#about to read 6, iclass 32, count 0 2006.257.08:02:52.58#ibcon#read 6, iclass 32, count 0 2006.257.08:02:52.58#ibcon#end of sib2, iclass 32, count 0 2006.257.08:02:52.58#ibcon#*after write, iclass 32, count 0 2006.257.08:02:52.58#ibcon#*before return 0, iclass 32, count 0 2006.257.08:02:52.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:52.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:52.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:02:52.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:02:52.58$vck44/va=8,4 2006.257.08:02:52.58#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.08:02:52.58#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.08:02:52.58#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:52.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:02:52.64#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:02:52.64#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:02:52.64#ibcon#enter wrdev, iclass 34, count 2 2006.257.08:02:52.64#ibcon#first serial, iclass 34, count 2 2006.257.08:02:52.64#ibcon#enter sib2, iclass 34, count 2 2006.257.08:02:52.64#ibcon#flushed, iclass 34, count 2 2006.257.08:02:52.64#ibcon#about to write, iclass 34, count 2 2006.257.08:02:52.64#ibcon#wrote, iclass 34, count 2 2006.257.08:02:52.64#ibcon#about to read 3, iclass 34, count 2 2006.257.08:02:52.66#ibcon#read 3, iclass 34, count 2 2006.257.08:02:52.66#ibcon#about to read 4, iclass 34, count 2 2006.257.08:02:52.66#ibcon#read 4, iclass 34, count 2 2006.257.08:02:52.66#ibcon#about to read 5, iclass 34, count 2 2006.257.08:02:52.66#ibcon#read 5, iclass 34, count 2 2006.257.08:02:52.66#ibcon#about to read 6, iclass 34, count 2 2006.257.08:02:52.66#ibcon#read 6, iclass 34, count 2 2006.257.08:02:52.66#ibcon#end of sib2, iclass 34, count 2 2006.257.08:02:52.66#ibcon#*mode == 0, iclass 34, count 2 2006.257.08:02:52.66#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.08:02:52.66#ibcon#[25=AT08-04\r\n] 2006.257.08:02:52.66#ibcon#*before write, iclass 34, count 2 2006.257.08:02:52.66#ibcon#enter sib2, iclass 34, count 2 2006.257.08:02:52.66#ibcon#flushed, iclass 34, count 2 2006.257.08:02:52.66#ibcon#about to write, iclass 34, count 2 2006.257.08:02:52.66#ibcon#wrote, iclass 34, count 2 2006.257.08:02:52.66#ibcon#about to read 3, iclass 34, count 2 2006.257.08:02:52.69#ibcon#read 3, iclass 34, count 2 2006.257.08:02:52.69#ibcon#about to read 4, iclass 34, count 2 2006.257.08:02:52.69#ibcon#read 4, iclass 34, count 2 2006.257.08:02:52.69#ibcon#about to read 5, iclass 34, count 2 2006.257.08:02:52.69#ibcon#read 5, iclass 34, count 2 2006.257.08:02:52.69#ibcon#about to read 6, iclass 34, count 2 2006.257.08:02:52.69#ibcon#read 6, iclass 34, count 2 2006.257.08:02:52.69#ibcon#end of sib2, iclass 34, count 2 2006.257.08:02:52.69#ibcon#*after write, iclass 34, count 2 2006.257.08:02:52.69#ibcon#*before return 0, iclass 34, count 2 2006.257.08:02:52.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:02:52.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:02:52.69#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.08:02:52.69#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:52.69#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:02:52.81#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:02:52.81#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:02:52.81#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:02:52.81#ibcon#first serial, iclass 34, count 0 2006.257.08:02:52.81#ibcon#enter sib2, iclass 34, count 0 2006.257.08:02:52.81#ibcon#flushed, iclass 34, count 0 2006.257.08:02:52.81#ibcon#about to write, iclass 34, count 0 2006.257.08:02:52.81#ibcon#wrote, iclass 34, count 0 2006.257.08:02:52.81#ibcon#about to read 3, iclass 34, count 0 2006.257.08:02:52.83#ibcon#read 3, iclass 34, count 0 2006.257.08:02:52.83#ibcon#about to read 4, iclass 34, count 0 2006.257.08:02:52.83#ibcon#read 4, iclass 34, count 0 2006.257.08:02:52.83#ibcon#about to read 5, iclass 34, count 0 2006.257.08:02:52.83#ibcon#read 5, iclass 34, count 0 2006.257.08:02:52.83#ibcon#about to read 6, iclass 34, count 0 2006.257.08:02:52.83#ibcon#read 6, iclass 34, count 0 2006.257.08:02:52.83#ibcon#end of sib2, iclass 34, count 0 2006.257.08:02:52.83#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:02:52.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:02:52.83#ibcon#[25=USB\r\n] 2006.257.08:02:52.83#ibcon#*before write, iclass 34, count 0 2006.257.08:02:52.83#ibcon#enter sib2, iclass 34, count 0 2006.257.08:02:52.83#ibcon#flushed, iclass 34, count 0 2006.257.08:02:52.83#ibcon#about to write, iclass 34, count 0 2006.257.08:02:52.83#ibcon#wrote, iclass 34, count 0 2006.257.08:02:52.83#ibcon#about to read 3, iclass 34, count 0 2006.257.08:02:52.86#ibcon#read 3, iclass 34, count 0 2006.257.08:02:52.86#ibcon#about to read 4, iclass 34, count 0 2006.257.08:02:52.86#ibcon#read 4, iclass 34, count 0 2006.257.08:02:52.86#ibcon#about to read 5, iclass 34, count 0 2006.257.08:02:52.86#ibcon#read 5, iclass 34, count 0 2006.257.08:02:52.86#ibcon#about to read 6, iclass 34, count 0 2006.257.08:02:52.86#ibcon#read 6, iclass 34, count 0 2006.257.08:02:52.86#ibcon#end of sib2, iclass 34, count 0 2006.257.08:02:52.86#ibcon#*after write, iclass 34, count 0 2006.257.08:02:52.86#ibcon#*before return 0, iclass 34, count 0 2006.257.08:02:52.86#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:02:52.86#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:02:52.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:02:52.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:02:52.86$vck44/vblo=1,629.99 2006.257.08:02:52.86#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.08:02:52.86#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.08:02:52.86#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:52.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:02:52.86#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:02:52.86#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:02:52.86#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:02:52.86#ibcon#first serial, iclass 36, count 0 2006.257.08:02:52.86#ibcon#enter sib2, iclass 36, count 0 2006.257.08:02:52.86#ibcon#flushed, iclass 36, count 0 2006.257.08:02:52.86#ibcon#about to write, iclass 36, count 0 2006.257.08:02:52.86#ibcon#wrote, iclass 36, count 0 2006.257.08:02:52.86#ibcon#about to read 3, iclass 36, count 0 2006.257.08:02:52.88#ibcon#read 3, iclass 36, count 0 2006.257.08:02:52.88#ibcon#about to read 4, iclass 36, count 0 2006.257.08:02:52.88#ibcon#read 4, iclass 36, count 0 2006.257.08:02:52.88#ibcon#about to read 5, iclass 36, count 0 2006.257.08:02:52.88#ibcon#read 5, iclass 36, count 0 2006.257.08:02:52.88#ibcon#about to read 6, iclass 36, count 0 2006.257.08:02:52.88#ibcon#read 6, iclass 36, count 0 2006.257.08:02:52.88#ibcon#end of sib2, iclass 36, count 0 2006.257.08:02:52.88#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:02:52.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:02:52.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:02:52.88#ibcon#*before write, iclass 36, count 0 2006.257.08:02:52.88#ibcon#enter sib2, iclass 36, count 0 2006.257.08:02:52.88#ibcon#flushed, iclass 36, count 0 2006.257.08:02:52.88#ibcon#about to write, iclass 36, count 0 2006.257.08:02:52.88#ibcon#wrote, iclass 36, count 0 2006.257.08:02:52.88#ibcon#about to read 3, iclass 36, count 0 2006.257.08:02:52.92#ibcon#read 3, iclass 36, count 0 2006.257.08:02:52.92#ibcon#about to read 4, iclass 36, count 0 2006.257.08:02:52.92#ibcon#read 4, iclass 36, count 0 2006.257.08:02:52.92#ibcon#about to read 5, iclass 36, count 0 2006.257.08:02:52.92#ibcon#read 5, iclass 36, count 0 2006.257.08:02:52.92#ibcon#about to read 6, iclass 36, count 0 2006.257.08:02:52.92#ibcon#read 6, iclass 36, count 0 2006.257.08:02:52.92#ibcon#end of sib2, iclass 36, count 0 2006.257.08:02:52.92#ibcon#*after write, iclass 36, count 0 2006.257.08:02:52.92#ibcon#*before return 0, iclass 36, count 0 2006.257.08:02:52.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:02:52.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:02:52.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:02:52.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:02:52.92$vck44/vb=1,4 2006.257.08:02:52.92#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.08:02:52.92#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.08:02:52.92#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:52.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:02:52.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:02:52.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:02:52.92#ibcon#enter wrdev, iclass 38, count 2 2006.257.08:02:52.92#ibcon#first serial, iclass 38, count 2 2006.257.08:02:52.92#ibcon#enter sib2, iclass 38, count 2 2006.257.08:02:52.92#ibcon#flushed, iclass 38, count 2 2006.257.08:02:52.92#ibcon#about to write, iclass 38, count 2 2006.257.08:02:52.92#ibcon#wrote, iclass 38, count 2 2006.257.08:02:52.92#ibcon#about to read 3, iclass 38, count 2 2006.257.08:02:52.94#ibcon#read 3, iclass 38, count 2 2006.257.08:02:52.94#ibcon#about to read 4, iclass 38, count 2 2006.257.08:02:52.94#ibcon#read 4, iclass 38, count 2 2006.257.08:02:52.94#ibcon#about to read 5, iclass 38, count 2 2006.257.08:02:52.94#ibcon#read 5, iclass 38, count 2 2006.257.08:02:52.94#ibcon#about to read 6, iclass 38, count 2 2006.257.08:02:52.94#ibcon#read 6, iclass 38, count 2 2006.257.08:02:52.94#ibcon#end of sib2, iclass 38, count 2 2006.257.08:02:52.94#ibcon#*mode == 0, iclass 38, count 2 2006.257.08:02:52.94#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.08:02:52.94#ibcon#[27=AT01-04\r\n] 2006.257.08:02:52.94#ibcon#*before write, iclass 38, count 2 2006.257.08:02:52.94#ibcon#enter sib2, iclass 38, count 2 2006.257.08:02:52.94#ibcon#flushed, iclass 38, count 2 2006.257.08:02:52.94#ibcon#about to write, iclass 38, count 2 2006.257.08:02:52.94#ibcon#wrote, iclass 38, count 2 2006.257.08:02:52.94#ibcon#about to read 3, iclass 38, count 2 2006.257.08:02:52.97#ibcon#read 3, iclass 38, count 2 2006.257.08:02:52.97#ibcon#about to read 4, iclass 38, count 2 2006.257.08:02:52.97#ibcon#read 4, iclass 38, count 2 2006.257.08:02:52.97#ibcon#about to read 5, iclass 38, count 2 2006.257.08:02:52.97#ibcon#read 5, iclass 38, count 2 2006.257.08:02:52.97#ibcon#about to read 6, iclass 38, count 2 2006.257.08:02:52.97#ibcon#read 6, iclass 38, count 2 2006.257.08:02:52.97#ibcon#end of sib2, iclass 38, count 2 2006.257.08:02:52.97#ibcon#*after write, iclass 38, count 2 2006.257.08:02:52.97#ibcon#*before return 0, iclass 38, count 2 2006.257.08:02:52.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:02:52.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:02:52.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.08:02:52.97#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:52.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:02:53.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:02:53.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:02:53.09#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:02:53.09#ibcon#first serial, iclass 38, count 0 2006.257.08:02:53.09#ibcon#enter sib2, iclass 38, count 0 2006.257.08:02:53.09#ibcon#flushed, iclass 38, count 0 2006.257.08:02:53.09#ibcon#about to write, iclass 38, count 0 2006.257.08:02:53.09#ibcon#wrote, iclass 38, count 0 2006.257.08:02:53.09#ibcon#about to read 3, iclass 38, count 0 2006.257.08:02:53.11#ibcon#read 3, iclass 38, count 0 2006.257.08:02:53.11#ibcon#about to read 4, iclass 38, count 0 2006.257.08:02:53.11#ibcon#read 4, iclass 38, count 0 2006.257.08:02:53.11#ibcon#about to read 5, iclass 38, count 0 2006.257.08:02:53.11#ibcon#read 5, iclass 38, count 0 2006.257.08:02:53.11#ibcon#about to read 6, iclass 38, count 0 2006.257.08:02:53.11#ibcon#read 6, iclass 38, count 0 2006.257.08:02:53.11#ibcon#end of sib2, iclass 38, count 0 2006.257.08:02:53.11#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:02:53.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:02:53.11#ibcon#[27=USB\r\n] 2006.257.08:02:53.11#ibcon#*before write, iclass 38, count 0 2006.257.08:02:53.11#ibcon#enter sib2, iclass 38, count 0 2006.257.08:02:53.11#ibcon#flushed, iclass 38, count 0 2006.257.08:02:53.11#ibcon#about to write, iclass 38, count 0 2006.257.08:02:53.11#ibcon#wrote, iclass 38, count 0 2006.257.08:02:53.11#ibcon#about to read 3, iclass 38, count 0 2006.257.08:02:53.14#ibcon#read 3, iclass 38, count 0 2006.257.08:02:53.14#ibcon#about to read 4, iclass 38, count 0 2006.257.08:02:53.14#ibcon#read 4, iclass 38, count 0 2006.257.08:02:53.14#ibcon#about to read 5, iclass 38, count 0 2006.257.08:02:53.14#ibcon#read 5, iclass 38, count 0 2006.257.08:02:53.14#ibcon#about to read 6, iclass 38, count 0 2006.257.08:02:53.14#ibcon#read 6, iclass 38, count 0 2006.257.08:02:53.14#ibcon#end of sib2, iclass 38, count 0 2006.257.08:02:53.14#ibcon#*after write, iclass 38, count 0 2006.257.08:02:53.14#ibcon#*before return 0, iclass 38, count 0 2006.257.08:02:53.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:02:53.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:02:53.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:02:53.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:02:53.14$vck44/vblo=2,634.99 2006.257.08:02:53.14#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.08:02:53.14#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.08:02:53.14#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:53.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:53.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:53.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:53.14#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:02:53.14#ibcon#first serial, iclass 40, count 0 2006.257.08:02:53.14#ibcon#enter sib2, iclass 40, count 0 2006.257.08:02:53.14#ibcon#flushed, iclass 40, count 0 2006.257.08:02:53.14#ibcon#about to write, iclass 40, count 0 2006.257.08:02:53.14#ibcon#wrote, iclass 40, count 0 2006.257.08:02:53.14#ibcon#about to read 3, iclass 40, count 0 2006.257.08:02:53.16#ibcon#read 3, iclass 40, count 0 2006.257.08:02:53.16#ibcon#about to read 4, iclass 40, count 0 2006.257.08:02:53.16#ibcon#read 4, iclass 40, count 0 2006.257.08:02:53.16#ibcon#about to read 5, iclass 40, count 0 2006.257.08:02:53.16#ibcon#read 5, iclass 40, count 0 2006.257.08:02:53.16#ibcon#about to read 6, iclass 40, count 0 2006.257.08:02:53.16#ibcon#read 6, iclass 40, count 0 2006.257.08:02:53.16#ibcon#end of sib2, iclass 40, count 0 2006.257.08:02:53.16#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:02:53.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:02:53.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:02:53.16#ibcon#*before write, iclass 40, count 0 2006.257.08:02:53.16#ibcon#enter sib2, iclass 40, count 0 2006.257.08:02:53.16#ibcon#flushed, iclass 40, count 0 2006.257.08:02:53.16#ibcon#about to write, iclass 40, count 0 2006.257.08:02:53.16#ibcon#wrote, iclass 40, count 0 2006.257.08:02:53.16#ibcon#about to read 3, iclass 40, count 0 2006.257.08:02:53.20#ibcon#read 3, iclass 40, count 0 2006.257.08:02:53.20#ibcon#about to read 4, iclass 40, count 0 2006.257.08:02:53.20#ibcon#read 4, iclass 40, count 0 2006.257.08:02:53.20#ibcon#about to read 5, iclass 40, count 0 2006.257.08:02:53.20#ibcon#read 5, iclass 40, count 0 2006.257.08:02:53.20#ibcon#about to read 6, iclass 40, count 0 2006.257.08:02:53.20#ibcon#read 6, iclass 40, count 0 2006.257.08:02:53.20#ibcon#end of sib2, iclass 40, count 0 2006.257.08:02:53.20#ibcon#*after write, iclass 40, count 0 2006.257.08:02:53.20#ibcon#*before return 0, iclass 40, count 0 2006.257.08:02:53.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:53.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:02:53.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:02:53.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:02:53.22$vck44/vb=2,5 2006.257.08:02:53.22#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.08:02:53.22#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.08:02:53.22#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:53.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:53.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:53.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:53.25#ibcon#enter wrdev, iclass 4, count 2 2006.257.08:02:53.25#ibcon#first serial, iclass 4, count 2 2006.257.08:02:53.25#ibcon#enter sib2, iclass 4, count 2 2006.257.08:02:53.25#ibcon#flushed, iclass 4, count 2 2006.257.08:02:53.25#ibcon#about to write, iclass 4, count 2 2006.257.08:02:53.25#ibcon#wrote, iclass 4, count 2 2006.257.08:02:53.25#ibcon#about to read 3, iclass 4, count 2 2006.257.08:02:53.27#ibcon#read 3, iclass 4, count 2 2006.257.08:02:53.27#ibcon#about to read 4, iclass 4, count 2 2006.257.08:02:53.27#ibcon#read 4, iclass 4, count 2 2006.257.08:02:53.27#ibcon#about to read 5, iclass 4, count 2 2006.257.08:02:53.27#ibcon#read 5, iclass 4, count 2 2006.257.08:02:53.27#ibcon#about to read 6, iclass 4, count 2 2006.257.08:02:53.27#ibcon#read 6, iclass 4, count 2 2006.257.08:02:53.27#ibcon#end of sib2, iclass 4, count 2 2006.257.08:02:53.27#ibcon#*mode == 0, iclass 4, count 2 2006.257.08:02:53.27#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.08:02:53.27#ibcon#[27=AT02-05\r\n] 2006.257.08:02:53.27#ibcon#*before write, iclass 4, count 2 2006.257.08:02:53.27#ibcon#enter sib2, iclass 4, count 2 2006.257.08:02:53.27#ibcon#flushed, iclass 4, count 2 2006.257.08:02:53.27#ibcon#about to write, iclass 4, count 2 2006.257.08:02:53.27#ibcon#wrote, iclass 4, count 2 2006.257.08:02:53.27#ibcon#about to read 3, iclass 4, count 2 2006.257.08:02:53.30#ibcon#read 3, iclass 4, count 2 2006.257.08:02:53.30#ibcon#about to read 4, iclass 4, count 2 2006.257.08:02:53.30#ibcon#read 4, iclass 4, count 2 2006.257.08:02:53.30#ibcon#about to read 5, iclass 4, count 2 2006.257.08:02:53.30#ibcon#read 5, iclass 4, count 2 2006.257.08:02:53.30#ibcon#about to read 6, iclass 4, count 2 2006.257.08:02:53.30#ibcon#read 6, iclass 4, count 2 2006.257.08:02:53.30#ibcon#end of sib2, iclass 4, count 2 2006.257.08:02:53.30#ibcon#*after write, iclass 4, count 2 2006.257.08:02:53.30#ibcon#*before return 0, iclass 4, count 2 2006.257.08:02:53.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:53.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:02:53.30#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.08:02:53.30#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:53.30#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:53.42#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:53.42#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:53.42#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:02:53.42#ibcon#first serial, iclass 4, count 0 2006.257.08:02:53.42#ibcon#enter sib2, iclass 4, count 0 2006.257.08:02:53.42#ibcon#flushed, iclass 4, count 0 2006.257.08:02:53.42#ibcon#about to write, iclass 4, count 0 2006.257.08:02:53.42#ibcon#wrote, iclass 4, count 0 2006.257.08:02:53.42#ibcon#about to read 3, iclass 4, count 0 2006.257.08:02:53.44#ibcon#read 3, iclass 4, count 0 2006.257.08:02:53.44#ibcon#about to read 4, iclass 4, count 0 2006.257.08:02:53.44#ibcon#read 4, iclass 4, count 0 2006.257.08:02:53.44#ibcon#about to read 5, iclass 4, count 0 2006.257.08:02:53.44#ibcon#read 5, iclass 4, count 0 2006.257.08:02:53.44#ibcon#about to read 6, iclass 4, count 0 2006.257.08:02:53.44#ibcon#read 6, iclass 4, count 0 2006.257.08:02:53.44#ibcon#end of sib2, iclass 4, count 0 2006.257.08:02:53.44#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:02:53.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:02:53.44#ibcon#[27=USB\r\n] 2006.257.08:02:53.44#ibcon#*before write, iclass 4, count 0 2006.257.08:02:53.44#ibcon#enter sib2, iclass 4, count 0 2006.257.08:02:53.44#ibcon#flushed, iclass 4, count 0 2006.257.08:02:53.44#ibcon#about to write, iclass 4, count 0 2006.257.08:02:53.44#ibcon#wrote, iclass 4, count 0 2006.257.08:02:53.44#ibcon#about to read 3, iclass 4, count 0 2006.257.08:02:53.47#ibcon#read 3, iclass 4, count 0 2006.257.08:02:53.47#ibcon#about to read 4, iclass 4, count 0 2006.257.08:02:53.47#ibcon#read 4, iclass 4, count 0 2006.257.08:02:53.47#ibcon#about to read 5, iclass 4, count 0 2006.257.08:02:53.47#ibcon#read 5, iclass 4, count 0 2006.257.08:02:53.47#ibcon#about to read 6, iclass 4, count 0 2006.257.08:02:53.47#ibcon#read 6, iclass 4, count 0 2006.257.08:02:53.47#ibcon#end of sib2, iclass 4, count 0 2006.257.08:02:53.47#ibcon#*after write, iclass 4, count 0 2006.257.08:02:53.47#ibcon#*before return 0, iclass 4, count 0 2006.257.08:02:53.47#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:53.47#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:02:53.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:02:53.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:02:53.47$vck44/vblo=3,649.99 2006.257.08:02:53.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.08:02:53.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.08:02:53.47#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:53.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:53.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:53.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:53.47#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:02:53.47#ibcon#first serial, iclass 6, count 0 2006.257.08:02:53.47#ibcon#enter sib2, iclass 6, count 0 2006.257.08:02:53.47#ibcon#flushed, iclass 6, count 0 2006.257.08:02:53.47#ibcon#about to write, iclass 6, count 0 2006.257.08:02:53.47#ibcon#wrote, iclass 6, count 0 2006.257.08:02:53.47#ibcon#about to read 3, iclass 6, count 0 2006.257.08:02:53.49#ibcon#read 3, iclass 6, count 0 2006.257.08:02:53.49#ibcon#about to read 4, iclass 6, count 0 2006.257.08:02:53.49#ibcon#read 4, iclass 6, count 0 2006.257.08:02:53.49#ibcon#about to read 5, iclass 6, count 0 2006.257.08:02:53.49#ibcon#read 5, iclass 6, count 0 2006.257.08:02:53.49#ibcon#about to read 6, iclass 6, count 0 2006.257.08:02:53.49#ibcon#read 6, iclass 6, count 0 2006.257.08:02:53.49#ibcon#end of sib2, iclass 6, count 0 2006.257.08:02:53.49#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:02:53.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:02:53.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:02:53.49#ibcon#*before write, iclass 6, count 0 2006.257.08:02:53.49#ibcon#enter sib2, iclass 6, count 0 2006.257.08:02:53.49#ibcon#flushed, iclass 6, count 0 2006.257.08:02:53.49#ibcon#about to write, iclass 6, count 0 2006.257.08:02:53.49#ibcon#wrote, iclass 6, count 0 2006.257.08:02:53.49#ibcon#about to read 3, iclass 6, count 0 2006.257.08:02:53.53#ibcon#read 3, iclass 6, count 0 2006.257.08:02:53.53#ibcon#about to read 4, iclass 6, count 0 2006.257.08:02:53.53#ibcon#read 4, iclass 6, count 0 2006.257.08:02:53.53#ibcon#about to read 5, iclass 6, count 0 2006.257.08:02:53.53#ibcon#read 5, iclass 6, count 0 2006.257.08:02:53.53#ibcon#about to read 6, iclass 6, count 0 2006.257.08:02:53.53#ibcon#read 6, iclass 6, count 0 2006.257.08:02:53.53#ibcon#end of sib2, iclass 6, count 0 2006.257.08:02:53.53#ibcon#*after write, iclass 6, count 0 2006.257.08:02:53.53#ibcon#*before return 0, iclass 6, count 0 2006.257.08:02:53.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:53.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:02:53.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:02:53.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:02:53.53$vck44/vb=3,4 2006.257.08:02:53.53#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.08:02:53.53#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.08:02:53.53#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:53.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:53.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:53.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:53.59#ibcon#enter wrdev, iclass 10, count 2 2006.257.08:02:53.59#ibcon#first serial, iclass 10, count 2 2006.257.08:02:53.59#ibcon#enter sib2, iclass 10, count 2 2006.257.08:02:53.59#ibcon#flushed, iclass 10, count 2 2006.257.08:02:53.59#ibcon#about to write, iclass 10, count 2 2006.257.08:02:53.59#ibcon#wrote, iclass 10, count 2 2006.257.08:02:53.59#ibcon#about to read 3, iclass 10, count 2 2006.257.08:02:53.61#ibcon#read 3, iclass 10, count 2 2006.257.08:02:53.61#ibcon#about to read 4, iclass 10, count 2 2006.257.08:02:53.61#ibcon#read 4, iclass 10, count 2 2006.257.08:02:53.61#ibcon#about to read 5, iclass 10, count 2 2006.257.08:02:53.61#ibcon#read 5, iclass 10, count 2 2006.257.08:02:53.61#ibcon#about to read 6, iclass 10, count 2 2006.257.08:02:53.61#ibcon#read 6, iclass 10, count 2 2006.257.08:02:53.61#ibcon#end of sib2, iclass 10, count 2 2006.257.08:02:53.61#ibcon#*mode == 0, iclass 10, count 2 2006.257.08:02:53.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.08:02:53.61#ibcon#[27=AT03-04\r\n] 2006.257.08:02:53.61#ibcon#*before write, iclass 10, count 2 2006.257.08:02:53.61#ibcon#enter sib2, iclass 10, count 2 2006.257.08:02:53.61#ibcon#flushed, iclass 10, count 2 2006.257.08:02:53.61#ibcon#about to write, iclass 10, count 2 2006.257.08:02:53.61#ibcon#wrote, iclass 10, count 2 2006.257.08:02:53.61#ibcon#about to read 3, iclass 10, count 2 2006.257.08:02:53.64#ibcon#read 3, iclass 10, count 2 2006.257.08:02:53.64#ibcon#about to read 4, iclass 10, count 2 2006.257.08:02:53.64#ibcon#read 4, iclass 10, count 2 2006.257.08:02:53.64#ibcon#about to read 5, iclass 10, count 2 2006.257.08:02:53.64#ibcon#read 5, iclass 10, count 2 2006.257.08:02:53.64#ibcon#about to read 6, iclass 10, count 2 2006.257.08:02:53.64#ibcon#read 6, iclass 10, count 2 2006.257.08:02:53.64#ibcon#end of sib2, iclass 10, count 2 2006.257.08:02:53.64#ibcon#*after write, iclass 10, count 2 2006.257.08:02:53.64#ibcon#*before return 0, iclass 10, count 2 2006.257.08:02:53.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:53.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:02:53.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.08:02:53.64#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:53.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:53.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:53.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:53.76#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:02:53.76#ibcon#first serial, iclass 10, count 0 2006.257.08:02:53.76#ibcon#enter sib2, iclass 10, count 0 2006.257.08:02:53.76#ibcon#flushed, iclass 10, count 0 2006.257.08:02:53.76#ibcon#about to write, iclass 10, count 0 2006.257.08:02:53.76#ibcon#wrote, iclass 10, count 0 2006.257.08:02:53.76#ibcon#about to read 3, iclass 10, count 0 2006.257.08:02:53.78#ibcon#read 3, iclass 10, count 0 2006.257.08:02:53.78#ibcon#about to read 4, iclass 10, count 0 2006.257.08:02:53.78#ibcon#read 4, iclass 10, count 0 2006.257.08:02:53.78#ibcon#about to read 5, iclass 10, count 0 2006.257.08:02:53.78#ibcon#read 5, iclass 10, count 0 2006.257.08:02:53.78#ibcon#about to read 6, iclass 10, count 0 2006.257.08:02:53.78#ibcon#read 6, iclass 10, count 0 2006.257.08:02:53.78#ibcon#end of sib2, iclass 10, count 0 2006.257.08:02:53.78#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:02:53.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:02:53.78#ibcon#[27=USB\r\n] 2006.257.08:02:53.78#ibcon#*before write, iclass 10, count 0 2006.257.08:02:53.78#ibcon#enter sib2, iclass 10, count 0 2006.257.08:02:53.78#ibcon#flushed, iclass 10, count 0 2006.257.08:02:53.78#ibcon#about to write, iclass 10, count 0 2006.257.08:02:53.78#ibcon#wrote, iclass 10, count 0 2006.257.08:02:53.78#ibcon#about to read 3, iclass 10, count 0 2006.257.08:02:53.81#ibcon#read 3, iclass 10, count 0 2006.257.08:02:53.81#ibcon#about to read 4, iclass 10, count 0 2006.257.08:02:53.81#ibcon#read 4, iclass 10, count 0 2006.257.08:02:53.81#ibcon#about to read 5, iclass 10, count 0 2006.257.08:02:53.81#ibcon#read 5, iclass 10, count 0 2006.257.08:02:53.81#ibcon#about to read 6, iclass 10, count 0 2006.257.08:02:53.81#ibcon#read 6, iclass 10, count 0 2006.257.08:02:53.81#ibcon#end of sib2, iclass 10, count 0 2006.257.08:02:53.81#ibcon#*after write, iclass 10, count 0 2006.257.08:02:53.81#ibcon#*before return 0, iclass 10, count 0 2006.257.08:02:53.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:53.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:02:53.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:02:53.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:02:53.81$vck44/vblo=4,679.99 2006.257.08:02:53.81#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.08:02:53.81#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.08:02:53.81#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:53.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:53.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:53.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:53.81#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:02:53.81#ibcon#first serial, iclass 12, count 0 2006.257.08:02:53.81#ibcon#enter sib2, iclass 12, count 0 2006.257.08:02:53.81#ibcon#flushed, iclass 12, count 0 2006.257.08:02:53.81#ibcon#about to write, iclass 12, count 0 2006.257.08:02:53.81#ibcon#wrote, iclass 12, count 0 2006.257.08:02:53.81#ibcon#about to read 3, iclass 12, count 0 2006.257.08:02:53.83#ibcon#read 3, iclass 12, count 0 2006.257.08:02:53.83#ibcon#about to read 4, iclass 12, count 0 2006.257.08:02:53.83#ibcon#read 4, iclass 12, count 0 2006.257.08:02:53.83#ibcon#about to read 5, iclass 12, count 0 2006.257.08:02:53.83#ibcon#read 5, iclass 12, count 0 2006.257.08:02:53.83#ibcon#about to read 6, iclass 12, count 0 2006.257.08:02:53.83#ibcon#read 6, iclass 12, count 0 2006.257.08:02:53.83#ibcon#end of sib2, iclass 12, count 0 2006.257.08:02:53.83#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:02:53.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:02:53.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:02:53.83#ibcon#*before write, iclass 12, count 0 2006.257.08:02:53.83#ibcon#enter sib2, iclass 12, count 0 2006.257.08:02:53.83#ibcon#flushed, iclass 12, count 0 2006.257.08:02:53.83#ibcon#about to write, iclass 12, count 0 2006.257.08:02:53.83#ibcon#wrote, iclass 12, count 0 2006.257.08:02:53.83#ibcon#about to read 3, iclass 12, count 0 2006.257.08:02:53.87#ibcon#read 3, iclass 12, count 0 2006.257.08:02:53.87#ibcon#about to read 4, iclass 12, count 0 2006.257.08:02:53.87#ibcon#read 4, iclass 12, count 0 2006.257.08:02:53.87#ibcon#about to read 5, iclass 12, count 0 2006.257.08:02:53.87#ibcon#read 5, iclass 12, count 0 2006.257.08:02:53.87#ibcon#about to read 6, iclass 12, count 0 2006.257.08:02:53.87#ibcon#read 6, iclass 12, count 0 2006.257.08:02:53.87#ibcon#end of sib2, iclass 12, count 0 2006.257.08:02:53.87#ibcon#*after write, iclass 12, count 0 2006.257.08:02:53.87#ibcon#*before return 0, iclass 12, count 0 2006.257.08:02:53.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:53.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:02:53.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:02:53.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:02:53.87$vck44/vb=4,5 2006.257.08:02:53.87#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.08:02:53.87#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.08:02:53.87#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:53.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:53.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:53.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:53.93#ibcon#enter wrdev, iclass 14, count 2 2006.257.08:02:53.93#ibcon#first serial, iclass 14, count 2 2006.257.08:02:53.93#ibcon#enter sib2, iclass 14, count 2 2006.257.08:02:53.93#ibcon#flushed, iclass 14, count 2 2006.257.08:02:53.93#ibcon#about to write, iclass 14, count 2 2006.257.08:02:53.93#ibcon#wrote, iclass 14, count 2 2006.257.08:02:53.93#ibcon#about to read 3, iclass 14, count 2 2006.257.08:02:53.95#ibcon#read 3, iclass 14, count 2 2006.257.08:02:53.95#ibcon#about to read 4, iclass 14, count 2 2006.257.08:02:53.95#ibcon#read 4, iclass 14, count 2 2006.257.08:02:53.95#ibcon#about to read 5, iclass 14, count 2 2006.257.08:02:53.95#ibcon#read 5, iclass 14, count 2 2006.257.08:02:53.95#ibcon#about to read 6, iclass 14, count 2 2006.257.08:02:53.95#ibcon#read 6, iclass 14, count 2 2006.257.08:02:53.95#ibcon#end of sib2, iclass 14, count 2 2006.257.08:02:53.95#ibcon#*mode == 0, iclass 14, count 2 2006.257.08:02:53.95#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.08:02:53.95#ibcon#[27=AT04-05\r\n] 2006.257.08:02:53.95#ibcon#*before write, iclass 14, count 2 2006.257.08:02:53.95#ibcon#enter sib2, iclass 14, count 2 2006.257.08:02:53.95#ibcon#flushed, iclass 14, count 2 2006.257.08:02:53.95#ibcon#about to write, iclass 14, count 2 2006.257.08:02:53.95#ibcon#wrote, iclass 14, count 2 2006.257.08:02:53.95#ibcon#about to read 3, iclass 14, count 2 2006.257.08:02:53.98#ibcon#read 3, iclass 14, count 2 2006.257.08:02:53.98#ibcon#about to read 4, iclass 14, count 2 2006.257.08:02:53.98#ibcon#read 4, iclass 14, count 2 2006.257.08:02:53.98#ibcon#about to read 5, iclass 14, count 2 2006.257.08:02:53.98#ibcon#read 5, iclass 14, count 2 2006.257.08:02:53.98#ibcon#about to read 6, iclass 14, count 2 2006.257.08:02:53.98#ibcon#read 6, iclass 14, count 2 2006.257.08:02:53.98#ibcon#end of sib2, iclass 14, count 2 2006.257.08:02:53.98#ibcon#*after write, iclass 14, count 2 2006.257.08:02:53.98#ibcon#*before return 0, iclass 14, count 2 2006.257.08:02:53.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:53.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:02:53.98#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.08:02:53.98#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:53.98#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:54.10#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:54.10#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:54.10#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:02:54.10#ibcon#first serial, iclass 14, count 0 2006.257.08:02:54.10#ibcon#enter sib2, iclass 14, count 0 2006.257.08:02:54.10#ibcon#flushed, iclass 14, count 0 2006.257.08:02:54.10#ibcon#about to write, iclass 14, count 0 2006.257.08:02:54.10#ibcon#wrote, iclass 14, count 0 2006.257.08:02:54.10#ibcon#about to read 3, iclass 14, count 0 2006.257.08:02:54.12#ibcon#read 3, iclass 14, count 0 2006.257.08:02:54.12#ibcon#about to read 4, iclass 14, count 0 2006.257.08:02:54.12#ibcon#read 4, iclass 14, count 0 2006.257.08:02:54.12#ibcon#about to read 5, iclass 14, count 0 2006.257.08:02:54.12#ibcon#read 5, iclass 14, count 0 2006.257.08:02:54.12#ibcon#about to read 6, iclass 14, count 0 2006.257.08:02:54.12#ibcon#read 6, iclass 14, count 0 2006.257.08:02:54.12#ibcon#end of sib2, iclass 14, count 0 2006.257.08:02:54.12#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:02:54.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:02:54.12#ibcon#[27=USB\r\n] 2006.257.08:02:54.12#ibcon#*before write, iclass 14, count 0 2006.257.08:02:54.12#ibcon#enter sib2, iclass 14, count 0 2006.257.08:02:54.12#ibcon#flushed, iclass 14, count 0 2006.257.08:02:54.12#ibcon#about to write, iclass 14, count 0 2006.257.08:02:54.12#ibcon#wrote, iclass 14, count 0 2006.257.08:02:54.12#ibcon#about to read 3, iclass 14, count 0 2006.257.08:02:54.15#ibcon#read 3, iclass 14, count 0 2006.257.08:02:54.15#ibcon#about to read 4, iclass 14, count 0 2006.257.08:02:54.15#ibcon#read 4, iclass 14, count 0 2006.257.08:02:54.15#ibcon#about to read 5, iclass 14, count 0 2006.257.08:02:54.15#ibcon#read 5, iclass 14, count 0 2006.257.08:02:54.15#ibcon#about to read 6, iclass 14, count 0 2006.257.08:02:54.15#ibcon#read 6, iclass 14, count 0 2006.257.08:02:54.15#ibcon#end of sib2, iclass 14, count 0 2006.257.08:02:54.15#ibcon#*after write, iclass 14, count 0 2006.257.08:02:54.15#ibcon#*before return 0, iclass 14, count 0 2006.257.08:02:54.15#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:54.15#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:02:54.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:02:54.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:02:54.15$vck44/vblo=5,709.99 2006.257.08:02:54.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.08:02:54.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.08:02:54.15#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:54.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:54.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:54.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:54.15#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:02:54.15#ibcon#first serial, iclass 16, count 0 2006.257.08:02:54.15#ibcon#enter sib2, iclass 16, count 0 2006.257.08:02:54.15#ibcon#flushed, iclass 16, count 0 2006.257.08:02:54.15#ibcon#about to write, iclass 16, count 0 2006.257.08:02:54.15#ibcon#wrote, iclass 16, count 0 2006.257.08:02:54.15#ibcon#about to read 3, iclass 16, count 0 2006.257.08:02:54.17#ibcon#read 3, iclass 16, count 0 2006.257.08:02:54.17#ibcon#about to read 4, iclass 16, count 0 2006.257.08:02:54.17#ibcon#read 4, iclass 16, count 0 2006.257.08:02:54.17#ibcon#about to read 5, iclass 16, count 0 2006.257.08:02:54.17#ibcon#read 5, iclass 16, count 0 2006.257.08:02:54.17#ibcon#about to read 6, iclass 16, count 0 2006.257.08:02:54.17#ibcon#read 6, iclass 16, count 0 2006.257.08:02:54.17#ibcon#end of sib2, iclass 16, count 0 2006.257.08:02:54.17#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:02:54.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:02:54.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:02:54.17#ibcon#*before write, iclass 16, count 0 2006.257.08:02:54.17#ibcon#enter sib2, iclass 16, count 0 2006.257.08:02:54.17#ibcon#flushed, iclass 16, count 0 2006.257.08:02:54.17#ibcon#about to write, iclass 16, count 0 2006.257.08:02:54.17#ibcon#wrote, iclass 16, count 0 2006.257.08:02:54.17#ibcon#about to read 3, iclass 16, count 0 2006.257.08:02:54.21#ibcon#read 3, iclass 16, count 0 2006.257.08:02:54.21#ibcon#about to read 4, iclass 16, count 0 2006.257.08:02:54.21#ibcon#read 4, iclass 16, count 0 2006.257.08:02:54.21#ibcon#about to read 5, iclass 16, count 0 2006.257.08:02:54.21#ibcon#read 5, iclass 16, count 0 2006.257.08:02:54.21#ibcon#about to read 6, iclass 16, count 0 2006.257.08:02:54.21#ibcon#read 6, iclass 16, count 0 2006.257.08:02:54.21#ibcon#end of sib2, iclass 16, count 0 2006.257.08:02:54.21#ibcon#*after write, iclass 16, count 0 2006.257.08:02:54.21#ibcon#*before return 0, iclass 16, count 0 2006.257.08:02:54.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:54.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:02:54.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:02:54.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:02:54.21$vck44/vb=5,4 2006.257.08:02:54.21#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.08:02:54.21#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.08:02:54.21#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:54.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:54.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:54.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:54.27#ibcon#enter wrdev, iclass 18, count 2 2006.257.08:02:54.27#ibcon#first serial, iclass 18, count 2 2006.257.08:02:54.27#ibcon#enter sib2, iclass 18, count 2 2006.257.08:02:54.27#ibcon#flushed, iclass 18, count 2 2006.257.08:02:54.27#ibcon#about to write, iclass 18, count 2 2006.257.08:02:54.27#ibcon#wrote, iclass 18, count 2 2006.257.08:02:54.27#ibcon#about to read 3, iclass 18, count 2 2006.257.08:02:54.29#ibcon#read 3, iclass 18, count 2 2006.257.08:02:54.29#ibcon#about to read 4, iclass 18, count 2 2006.257.08:02:54.29#ibcon#read 4, iclass 18, count 2 2006.257.08:02:54.29#ibcon#about to read 5, iclass 18, count 2 2006.257.08:02:54.29#ibcon#read 5, iclass 18, count 2 2006.257.08:02:54.29#ibcon#about to read 6, iclass 18, count 2 2006.257.08:02:54.29#ibcon#read 6, iclass 18, count 2 2006.257.08:02:54.29#ibcon#end of sib2, iclass 18, count 2 2006.257.08:02:54.29#ibcon#*mode == 0, iclass 18, count 2 2006.257.08:02:54.29#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.08:02:54.29#ibcon#[27=AT05-04\r\n] 2006.257.08:02:54.29#ibcon#*before write, iclass 18, count 2 2006.257.08:02:54.29#ibcon#enter sib2, iclass 18, count 2 2006.257.08:02:54.29#ibcon#flushed, iclass 18, count 2 2006.257.08:02:54.29#ibcon#about to write, iclass 18, count 2 2006.257.08:02:54.29#ibcon#wrote, iclass 18, count 2 2006.257.08:02:54.29#ibcon#about to read 3, iclass 18, count 2 2006.257.08:02:54.32#ibcon#read 3, iclass 18, count 2 2006.257.08:02:54.32#ibcon#about to read 4, iclass 18, count 2 2006.257.08:02:54.32#ibcon#read 4, iclass 18, count 2 2006.257.08:02:54.32#ibcon#about to read 5, iclass 18, count 2 2006.257.08:02:54.32#ibcon#read 5, iclass 18, count 2 2006.257.08:02:54.32#ibcon#about to read 6, iclass 18, count 2 2006.257.08:02:54.32#ibcon#read 6, iclass 18, count 2 2006.257.08:02:54.32#ibcon#end of sib2, iclass 18, count 2 2006.257.08:02:54.32#ibcon#*after write, iclass 18, count 2 2006.257.08:02:54.32#ibcon#*before return 0, iclass 18, count 2 2006.257.08:02:54.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:54.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:02:54.32#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.08:02:54.32#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:54.32#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:54.44#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:54.44#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:54.44#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:02:54.44#ibcon#first serial, iclass 18, count 0 2006.257.08:02:54.44#ibcon#enter sib2, iclass 18, count 0 2006.257.08:02:54.44#ibcon#flushed, iclass 18, count 0 2006.257.08:02:54.44#ibcon#about to write, iclass 18, count 0 2006.257.08:02:54.44#ibcon#wrote, iclass 18, count 0 2006.257.08:02:54.44#ibcon#about to read 3, iclass 18, count 0 2006.257.08:02:54.46#ibcon#read 3, iclass 18, count 0 2006.257.08:02:54.46#ibcon#about to read 4, iclass 18, count 0 2006.257.08:02:54.46#ibcon#read 4, iclass 18, count 0 2006.257.08:02:54.46#ibcon#about to read 5, iclass 18, count 0 2006.257.08:02:54.46#ibcon#read 5, iclass 18, count 0 2006.257.08:02:54.46#ibcon#about to read 6, iclass 18, count 0 2006.257.08:02:54.46#ibcon#read 6, iclass 18, count 0 2006.257.08:02:54.46#ibcon#end of sib2, iclass 18, count 0 2006.257.08:02:54.46#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:02:54.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:02:54.46#ibcon#[27=USB\r\n] 2006.257.08:02:54.46#ibcon#*before write, iclass 18, count 0 2006.257.08:02:54.46#ibcon#enter sib2, iclass 18, count 0 2006.257.08:02:54.46#ibcon#flushed, iclass 18, count 0 2006.257.08:02:54.46#ibcon#about to write, iclass 18, count 0 2006.257.08:02:54.46#ibcon#wrote, iclass 18, count 0 2006.257.08:02:54.46#ibcon#about to read 3, iclass 18, count 0 2006.257.08:02:54.49#ibcon#read 3, iclass 18, count 0 2006.257.08:02:54.49#ibcon#about to read 4, iclass 18, count 0 2006.257.08:02:54.49#ibcon#read 4, iclass 18, count 0 2006.257.08:02:54.49#ibcon#about to read 5, iclass 18, count 0 2006.257.08:02:54.49#ibcon#read 5, iclass 18, count 0 2006.257.08:02:54.49#ibcon#about to read 6, iclass 18, count 0 2006.257.08:02:54.49#ibcon#read 6, iclass 18, count 0 2006.257.08:02:54.49#ibcon#end of sib2, iclass 18, count 0 2006.257.08:02:54.49#ibcon#*after write, iclass 18, count 0 2006.257.08:02:54.49#ibcon#*before return 0, iclass 18, count 0 2006.257.08:02:54.49#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:54.49#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:02:54.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:02:54.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:02:54.49$vck44/vblo=6,719.99 2006.257.08:02:54.49#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.08:02:54.49#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.08:02:54.49#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:54.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:54.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:54.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:54.49#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:02:54.49#ibcon#first serial, iclass 20, count 0 2006.257.08:02:54.49#ibcon#enter sib2, iclass 20, count 0 2006.257.08:02:54.49#ibcon#flushed, iclass 20, count 0 2006.257.08:02:54.49#ibcon#about to write, iclass 20, count 0 2006.257.08:02:54.49#ibcon#wrote, iclass 20, count 0 2006.257.08:02:54.49#ibcon#about to read 3, iclass 20, count 0 2006.257.08:02:54.51#ibcon#read 3, iclass 20, count 0 2006.257.08:02:54.51#ibcon#about to read 4, iclass 20, count 0 2006.257.08:02:54.51#ibcon#read 4, iclass 20, count 0 2006.257.08:02:54.51#ibcon#about to read 5, iclass 20, count 0 2006.257.08:02:54.51#ibcon#read 5, iclass 20, count 0 2006.257.08:02:54.51#ibcon#about to read 6, iclass 20, count 0 2006.257.08:02:54.51#ibcon#read 6, iclass 20, count 0 2006.257.08:02:54.51#ibcon#end of sib2, iclass 20, count 0 2006.257.08:02:54.51#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:02:54.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:02:54.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:02:54.51#ibcon#*before write, iclass 20, count 0 2006.257.08:02:54.51#ibcon#enter sib2, iclass 20, count 0 2006.257.08:02:54.51#ibcon#flushed, iclass 20, count 0 2006.257.08:02:54.51#ibcon#about to write, iclass 20, count 0 2006.257.08:02:54.51#ibcon#wrote, iclass 20, count 0 2006.257.08:02:54.51#ibcon#about to read 3, iclass 20, count 0 2006.257.08:02:54.55#ibcon#read 3, iclass 20, count 0 2006.257.08:02:54.55#ibcon#about to read 4, iclass 20, count 0 2006.257.08:02:54.55#ibcon#read 4, iclass 20, count 0 2006.257.08:02:54.55#ibcon#about to read 5, iclass 20, count 0 2006.257.08:02:54.55#ibcon#read 5, iclass 20, count 0 2006.257.08:02:54.55#ibcon#about to read 6, iclass 20, count 0 2006.257.08:02:54.55#ibcon#read 6, iclass 20, count 0 2006.257.08:02:54.55#ibcon#end of sib2, iclass 20, count 0 2006.257.08:02:54.55#ibcon#*after write, iclass 20, count 0 2006.257.08:02:54.55#ibcon#*before return 0, iclass 20, count 0 2006.257.08:02:54.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:54.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:02:54.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:02:54.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:02:54.55$vck44/vb=6,4 2006.257.08:02:54.55#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.08:02:54.55#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.08:02:54.55#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:54.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:54.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:54.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:54.61#ibcon#enter wrdev, iclass 22, count 2 2006.257.08:02:54.61#ibcon#first serial, iclass 22, count 2 2006.257.08:02:54.61#ibcon#enter sib2, iclass 22, count 2 2006.257.08:02:54.61#ibcon#flushed, iclass 22, count 2 2006.257.08:02:54.61#ibcon#about to write, iclass 22, count 2 2006.257.08:02:54.61#ibcon#wrote, iclass 22, count 2 2006.257.08:02:54.61#ibcon#about to read 3, iclass 22, count 2 2006.257.08:02:54.63#ibcon#read 3, iclass 22, count 2 2006.257.08:02:54.63#ibcon#about to read 4, iclass 22, count 2 2006.257.08:02:54.63#ibcon#read 4, iclass 22, count 2 2006.257.08:02:54.63#ibcon#about to read 5, iclass 22, count 2 2006.257.08:02:54.63#ibcon#read 5, iclass 22, count 2 2006.257.08:02:54.63#ibcon#about to read 6, iclass 22, count 2 2006.257.08:02:54.63#ibcon#read 6, iclass 22, count 2 2006.257.08:02:54.63#ibcon#end of sib2, iclass 22, count 2 2006.257.08:02:54.63#ibcon#*mode == 0, iclass 22, count 2 2006.257.08:02:54.63#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.08:02:54.63#ibcon#[27=AT06-04\r\n] 2006.257.08:02:54.63#ibcon#*before write, iclass 22, count 2 2006.257.08:02:54.63#ibcon#enter sib2, iclass 22, count 2 2006.257.08:02:54.63#ibcon#flushed, iclass 22, count 2 2006.257.08:02:54.63#ibcon#about to write, iclass 22, count 2 2006.257.08:02:54.63#ibcon#wrote, iclass 22, count 2 2006.257.08:02:54.63#ibcon#about to read 3, iclass 22, count 2 2006.257.08:02:54.66#ibcon#read 3, iclass 22, count 2 2006.257.08:02:54.66#ibcon#about to read 4, iclass 22, count 2 2006.257.08:02:54.66#ibcon#read 4, iclass 22, count 2 2006.257.08:02:54.66#ibcon#about to read 5, iclass 22, count 2 2006.257.08:02:54.66#ibcon#read 5, iclass 22, count 2 2006.257.08:02:54.66#ibcon#about to read 6, iclass 22, count 2 2006.257.08:02:54.66#ibcon#read 6, iclass 22, count 2 2006.257.08:02:54.66#ibcon#end of sib2, iclass 22, count 2 2006.257.08:02:54.66#ibcon#*after write, iclass 22, count 2 2006.257.08:02:54.66#ibcon#*before return 0, iclass 22, count 2 2006.257.08:02:54.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:54.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:02:54.66#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.08:02:54.66#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:54.66#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:54.78#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:54.78#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:54.78#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:02:54.78#ibcon#first serial, iclass 22, count 0 2006.257.08:02:54.78#ibcon#enter sib2, iclass 22, count 0 2006.257.08:02:54.78#ibcon#flushed, iclass 22, count 0 2006.257.08:02:54.78#ibcon#about to write, iclass 22, count 0 2006.257.08:02:54.78#ibcon#wrote, iclass 22, count 0 2006.257.08:02:54.78#ibcon#about to read 3, iclass 22, count 0 2006.257.08:02:54.80#ibcon#read 3, iclass 22, count 0 2006.257.08:02:54.80#ibcon#about to read 4, iclass 22, count 0 2006.257.08:02:54.80#ibcon#read 4, iclass 22, count 0 2006.257.08:02:54.80#ibcon#about to read 5, iclass 22, count 0 2006.257.08:02:54.80#ibcon#read 5, iclass 22, count 0 2006.257.08:02:54.80#ibcon#about to read 6, iclass 22, count 0 2006.257.08:02:54.80#ibcon#read 6, iclass 22, count 0 2006.257.08:02:54.80#ibcon#end of sib2, iclass 22, count 0 2006.257.08:02:54.80#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:02:54.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:02:54.80#ibcon#[27=USB\r\n] 2006.257.08:02:54.80#ibcon#*before write, iclass 22, count 0 2006.257.08:02:54.80#ibcon#enter sib2, iclass 22, count 0 2006.257.08:02:54.80#ibcon#flushed, iclass 22, count 0 2006.257.08:02:54.80#ibcon#about to write, iclass 22, count 0 2006.257.08:02:54.80#ibcon#wrote, iclass 22, count 0 2006.257.08:02:54.80#ibcon#about to read 3, iclass 22, count 0 2006.257.08:02:54.83#ibcon#read 3, iclass 22, count 0 2006.257.08:02:54.83#ibcon#about to read 4, iclass 22, count 0 2006.257.08:02:54.83#ibcon#read 4, iclass 22, count 0 2006.257.08:02:54.83#ibcon#about to read 5, iclass 22, count 0 2006.257.08:02:54.83#ibcon#read 5, iclass 22, count 0 2006.257.08:02:54.83#ibcon#about to read 6, iclass 22, count 0 2006.257.08:02:54.83#ibcon#read 6, iclass 22, count 0 2006.257.08:02:54.83#ibcon#end of sib2, iclass 22, count 0 2006.257.08:02:54.83#ibcon#*after write, iclass 22, count 0 2006.257.08:02:54.83#ibcon#*before return 0, iclass 22, count 0 2006.257.08:02:54.83#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:54.83#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:02:54.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:02:54.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:02:54.83$vck44/vblo=7,734.99 2006.257.08:02:54.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.08:02:54.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.08:02:54.83#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:54.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:54.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:54.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:54.83#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:02:54.83#ibcon#first serial, iclass 24, count 0 2006.257.08:02:54.83#ibcon#enter sib2, iclass 24, count 0 2006.257.08:02:54.83#ibcon#flushed, iclass 24, count 0 2006.257.08:02:54.83#ibcon#about to write, iclass 24, count 0 2006.257.08:02:54.83#ibcon#wrote, iclass 24, count 0 2006.257.08:02:54.83#ibcon#about to read 3, iclass 24, count 0 2006.257.08:02:54.85#ibcon#read 3, iclass 24, count 0 2006.257.08:02:54.85#ibcon#about to read 4, iclass 24, count 0 2006.257.08:02:54.85#ibcon#read 4, iclass 24, count 0 2006.257.08:02:54.85#ibcon#about to read 5, iclass 24, count 0 2006.257.08:02:54.85#ibcon#read 5, iclass 24, count 0 2006.257.08:02:54.85#ibcon#about to read 6, iclass 24, count 0 2006.257.08:02:54.85#ibcon#read 6, iclass 24, count 0 2006.257.08:02:54.85#ibcon#end of sib2, iclass 24, count 0 2006.257.08:02:54.85#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:02:54.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:02:54.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:02:54.85#ibcon#*before write, iclass 24, count 0 2006.257.08:02:54.85#ibcon#enter sib2, iclass 24, count 0 2006.257.08:02:54.85#ibcon#flushed, iclass 24, count 0 2006.257.08:02:54.85#ibcon#about to write, iclass 24, count 0 2006.257.08:02:54.85#ibcon#wrote, iclass 24, count 0 2006.257.08:02:54.85#ibcon#about to read 3, iclass 24, count 0 2006.257.08:02:54.89#ibcon#read 3, iclass 24, count 0 2006.257.08:02:54.89#ibcon#about to read 4, iclass 24, count 0 2006.257.08:02:54.89#ibcon#read 4, iclass 24, count 0 2006.257.08:02:54.89#ibcon#about to read 5, iclass 24, count 0 2006.257.08:02:54.89#ibcon#read 5, iclass 24, count 0 2006.257.08:02:54.89#ibcon#about to read 6, iclass 24, count 0 2006.257.08:02:54.89#ibcon#read 6, iclass 24, count 0 2006.257.08:02:54.89#ibcon#end of sib2, iclass 24, count 0 2006.257.08:02:54.89#ibcon#*after write, iclass 24, count 0 2006.257.08:02:54.89#ibcon#*before return 0, iclass 24, count 0 2006.257.08:02:54.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:54.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:02:54.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:02:54.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:02:54.89$vck44/vb=7,4 2006.257.08:02:54.89#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.08:02:54.89#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.08:02:54.89#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:54.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:54.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:54.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:54.95#ibcon#enter wrdev, iclass 26, count 2 2006.257.08:02:54.95#ibcon#first serial, iclass 26, count 2 2006.257.08:02:54.95#ibcon#enter sib2, iclass 26, count 2 2006.257.08:02:54.95#ibcon#flushed, iclass 26, count 2 2006.257.08:02:54.95#ibcon#about to write, iclass 26, count 2 2006.257.08:02:54.95#ibcon#wrote, iclass 26, count 2 2006.257.08:02:54.95#ibcon#about to read 3, iclass 26, count 2 2006.257.08:02:54.97#ibcon#read 3, iclass 26, count 2 2006.257.08:02:54.97#ibcon#about to read 4, iclass 26, count 2 2006.257.08:02:54.97#ibcon#read 4, iclass 26, count 2 2006.257.08:02:54.97#ibcon#about to read 5, iclass 26, count 2 2006.257.08:02:54.97#ibcon#read 5, iclass 26, count 2 2006.257.08:02:54.97#ibcon#about to read 6, iclass 26, count 2 2006.257.08:02:54.97#ibcon#read 6, iclass 26, count 2 2006.257.08:02:54.97#ibcon#end of sib2, iclass 26, count 2 2006.257.08:02:54.97#ibcon#*mode == 0, iclass 26, count 2 2006.257.08:02:54.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.08:02:54.97#ibcon#[27=AT07-04\r\n] 2006.257.08:02:54.97#ibcon#*before write, iclass 26, count 2 2006.257.08:02:54.97#ibcon#enter sib2, iclass 26, count 2 2006.257.08:02:54.97#ibcon#flushed, iclass 26, count 2 2006.257.08:02:54.97#ibcon#about to write, iclass 26, count 2 2006.257.08:02:54.97#ibcon#wrote, iclass 26, count 2 2006.257.08:02:54.97#ibcon#about to read 3, iclass 26, count 2 2006.257.08:02:55.00#ibcon#read 3, iclass 26, count 2 2006.257.08:02:55.00#ibcon#about to read 4, iclass 26, count 2 2006.257.08:02:55.00#ibcon#read 4, iclass 26, count 2 2006.257.08:02:55.00#ibcon#about to read 5, iclass 26, count 2 2006.257.08:02:55.00#ibcon#read 5, iclass 26, count 2 2006.257.08:02:55.00#ibcon#about to read 6, iclass 26, count 2 2006.257.08:02:55.00#ibcon#read 6, iclass 26, count 2 2006.257.08:02:55.00#ibcon#end of sib2, iclass 26, count 2 2006.257.08:02:55.00#ibcon#*after write, iclass 26, count 2 2006.257.08:02:55.00#ibcon#*before return 0, iclass 26, count 2 2006.257.08:02:55.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:55.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:02:55.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.08:02:55.00#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:55.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:55.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:55.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:55.12#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:02:55.12#ibcon#first serial, iclass 26, count 0 2006.257.08:02:55.12#ibcon#enter sib2, iclass 26, count 0 2006.257.08:02:55.12#ibcon#flushed, iclass 26, count 0 2006.257.08:02:55.12#ibcon#about to write, iclass 26, count 0 2006.257.08:02:55.12#ibcon#wrote, iclass 26, count 0 2006.257.08:02:55.12#ibcon#about to read 3, iclass 26, count 0 2006.257.08:02:55.14#ibcon#read 3, iclass 26, count 0 2006.257.08:02:55.14#ibcon#about to read 4, iclass 26, count 0 2006.257.08:02:55.14#ibcon#read 4, iclass 26, count 0 2006.257.08:02:55.14#ibcon#about to read 5, iclass 26, count 0 2006.257.08:02:55.14#ibcon#read 5, iclass 26, count 0 2006.257.08:02:55.14#ibcon#about to read 6, iclass 26, count 0 2006.257.08:02:55.14#ibcon#read 6, iclass 26, count 0 2006.257.08:02:55.14#ibcon#end of sib2, iclass 26, count 0 2006.257.08:02:55.14#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:02:55.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:02:55.14#ibcon#[27=USB\r\n] 2006.257.08:02:55.14#ibcon#*before write, iclass 26, count 0 2006.257.08:02:55.14#ibcon#enter sib2, iclass 26, count 0 2006.257.08:02:55.14#ibcon#flushed, iclass 26, count 0 2006.257.08:02:55.14#ibcon#about to write, iclass 26, count 0 2006.257.08:02:55.14#ibcon#wrote, iclass 26, count 0 2006.257.08:02:55.14#ibcon#about to read 3, iclass 26, count 0 2006.257.08:02:55.17#ibcon#read 3, iclass 26, count 0 2006.257.08:02:55.17#ibcon#about to read 4, iclass 26, count 0 2006.257.08:02:55.17#ibcon#read 4, iclass 26, count 0 2006.257.08:02:55.17#ibcon#about to read 5, iclass 26, count 0 2006.257.08:02:55.17#ibcon#read 5, iclass 26, count 0 2006.257.08:02:55.17#ibcon#about to read 6, iclass 26, count 0 2006.257.08:02:55.17#ibcon#read 6, iclass 26, count 0 2006.257.08:02:55.17#ibcon#end of sib2, iclass 26, count 0 2006.257.08:02:55.17#ibcon#*after write, iclass 26, count 0 2006.257.08:02:55.17#ibcon#*before return 0, iclass 26, count 0 2006.257.08:02:55.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:55.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:02:55.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:02:55.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:02:55.17$vck44/vblo=8,744.99 2006.257.08:02:55.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.08:02:55.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.08:02:55.17#ibcon#ireg 17 cls_cnt 0 2006.257.08:02:55.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:55.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:55.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:55.17#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:02:55.17#ibcon#first serial, iclass 28, count 0 2006.257.08:02:55.17#ibcon#enter sib2, iclass 28, count 0 2006.257.08:02:55.17#ibcon#flushed, iclass 28, count 0 2006.257.08:02:55.17#ibcon#about to write, iclass 28, count 0 2006.257.08:02:55.17#ibcon#wrote, iclass 28, count 0 2006.257.08:02:55.17#ibcon#about to read 3, iclass 28, count 0 2006.257.08:02:55.19#ibcon#read 3, iclass 28, count 0 2006.257.08:02:55.19#ibcon#about to read 4, iclass 28, count 0 2006.257.08:02:55.19#ibcon#read 4, iclass 28, count 0 2006.257.08:02:55.19#ibcon#about to read 5, iclass 28, count 0 2006.257.08:02:55.19#ibcon#read 5, iclass 28, count 0 2006.257.08:02:55.19#ibcon#about to read 6, iclass 28, count 0 2006.257.08:02:55.19#ibcon#read 6, iclass 28, count 0 2006.257.08:02:55.19#ibcon#end of sib2, iclass 28, count 0 2006.257.08:02:55.19#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:02:55.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:02:55.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:02:55.19#ibcon#*before write, iclass 28, count 0 2006.257.08:02:55.19#ibcon#enter sib2, iclass 28, count 0 2006.257.08:02:55.19#ibcon#flushed, iclass 28, count 0 2006.257.08:02:55.19#ibcon#about to write, iclass 28, count 0 2006.257.08:02:55.19#ibcon#wrote, iclass 28, count 0 2006.257.08:02:55.19#ibcon#about to read 3, iclass 28, count 0 2006.257.08:02:55.23#ibcon#read 3, iclass 28, count 0 2006.257.08:02:55.23#ibcon#about to read 4, iclass 28, count 0 2006.257.08:02:55.23#ibcon#read 4, iclass 28, count 0 2006.257.08:02:55.23#ibcon#about to read 5, iclass 28, count 0 2006.257.08:02:55.23#ibcon#read 5, iclass 28, count 0 2006.257.08:02:55.23#ibcon#about to read 6, iclass 28, count 0 2006.257.08:02:55.23#ibcon#read 6, iclass 28, count 0 2006.257.08:02:55.23#ibcon#end of sib2, iclass 28, count 0 2006.257.08:02:55.23#ibcon#*after write, iclass 28, count 0 2006.257.08:02:55.23#ibcon#*before return 0, iclass 28, count 0 2006.257.08:02:55.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:55.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:02:55.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:02:55.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:02:55.23$vck44/vb=8,4 2006.257.08:02:55.23#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.08:02:55.23#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.08:02:55.23#ibcon#ireg 11 cls_cnt 2 2006.257.08:02:55.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:55.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:55.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:55.29#ibcon#enter wrdev, iclass 30, count 2 2006.257.08:02:55.29#ibcon#first serial, iclass 30, count 2 2006.257.08:02:55.29#ibcon#enter sib2, iclass 30, count 2 2006.257.08:02:55.29#ibcon#flushed, iclass 30, count 2 2006.257.08:02:55.29#ibcon#about to write, iclass 30, count 2 2006.257.08:02:55.29#ibcon#wrote, iclass 30, count 2 2006.257.08:02:55.29#ibcon#about to read 3, iclass 30, count 2 2006.257.08:02:55.31#ibcon#read 3, iclass 30, count 2 2006.257.08:02:55.31#ibcon#about to read 4, iclass 30, count 2 2006.257.08:02:55.31#ibcon#read 4, iclass 30, count 2 2006.257.08:02:55.31#ibcon#about to read 5, iclass 30, count 2 2006.257.08:02:55.31#ibcon#read 5, iclass 30, count 2 2006.257.08:02:55.31#ibcon#about to read 6, iclass 30, count 2 2006.257.08:02:55.31#ibcon#read 6, iclass 30, count 2 2006.257.08:02:55.31#ibcon#end of sib2, iclass 30, count 2 2006.257.08:02:55.31#ibcon#*mode == 0, iclass 30, count 2 2006.257.08:02:55.31#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.08:02:55.31#ibcon#[27=AT08-04\r\n] 2006.257.08:02:55.31#ibcon#*before write, iclass 30, count 2 2006.257.08:02:55.31#ibcon#enter sib2, iclass 30, count 2 2006.257.08:02:55.31#ibcon#flushed, iclass 30, count 2 2006.257.08:02:55.31#ibcon#about to write, iclass 30, count 2 2006.257.08:02:55.31#ibcon#wrote, iclass 30, count 2 2006.257.08:02:55.31#ibcon#about to read 3, iclass 30, count 2 2006.257.08:02:55.34#ibcon#read 3, iclass 30, count 2 2006.257.08:02:55.35#ibcon#about to read 4, iclass 30, count 2 2006.257.08:02:55.35#ibcon#read 4, iclass 30, count 2 2006.257.08:02:55.35#ibcon#about to read 5, iclass 30, count 2 2006.257.08:02:55.35#ibcon#read 5, iclass 30, count 2 2006.257.08:02:55.35#ibcon#about to read 6, iclass 30, count 2 2006.257.08:02:55.35#ibcon#read 6, iclass 30, count 2 2006.257.08:02:55.35#ibcon#end of sib2, iclass 30, count 2 2006.257.08:02:55.35#ibcon#*after write, iclass 30, count 2 2006.257.08:02:55.35#ibcon#*before return 0, iclass 30, count 2 2006.257.08:02:55.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:55.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:02:55.35#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.08:02:55.35#ibcon#ireg 7 cls_cnt 0 2006.257.08:02:55.35#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:55.46#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:55.46#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:55.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:02:55.46#ibcon#first serial, iclass 30, count 0 2006.257.08:02:55.46#ibcon#enter sib2, iclass 30, count 0 2006.257.08:02:55.46#ibcon#flushed, iclass 30, count 0 2006.257.08:02:55.46#ibcon#about to write, iclass 30, count 0 2006.257.08:02:55.46#ibcon#wrote, iclass 30, count 0 2006.257.08:02:55.46#ibcon#about to read 3, iclass 30, count 0 2006.257.08:02:55.48#ibcon#read 3, iclass 30, count 0 2006.257.08:02:55.48#ibcon#about to read 4, iclass 30, count 0 2006.257.08:02:55.48#ibcon#read 4, iclass 30, count 0 2006.257.08:02:55.48#ibcon#about to read 5, iclass 30, count 0 2006.257.08:02:55.48#ibcon#read 5, iclass 30, count 0 2006.257.08:02:55.48#ibcon#about to read 6, iclass 30, count 0 2006.257.08:02:55.48#ibcon#read 6, iclass 30, count 0 2006.257.08:02:55.48#ibcon#end of sib2, iclass 30, count 0 2006.257.08:02:55.48#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:02:55.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:02:55.48#ibcon#[27=USB\r\n] 2006.257.08:02:55.48#ibcon#*before write, iclass 30, count 0 2006.257.08:02:55.48#ibcon#enter sib2, iclass 30, count 0 2006.257.08:02:55.48#ibcon#flushed, iclass 30, count 0 2006.257.08:02:55.48#ibcon#about to write, iclass 30, count 0 2006.257.08:02:55.48#ibcon#wrote, iclass 30, count 0 2006.257.08:02:55.48#ibcon#about to read 3, iclass 30, count 0 2006.257.08:02:55.51#ibcon#read 3, iclass 30, count 0 2006.257.08:02:55.51#ibcon#about to read 4, iclass 30, count 0 2006.257.08:02:55.51#ibcon#read 4, iclass 30, count 0 2006.257.08:02:55.51#ibcon#about to read 5, iclass 30, count 0 2006.257.08:02:55.51#ibcon#read 5, iclass 30, count 0 2006.257.08:02:55.51#ibcon#about to read 6, iclass 30, count 0 2006.257.08:02:55.51#ibcon#read 6, iclass 30, count 0 2006.257.08:02:55.51#ibcon#end of sib2, iclass 30, count 0 2006.257.08:02:55.51#ibcon#*after write, iclass 30, count 0 2006.257.08:02:55.51#ibcon#*before return 0, iclass 30, count 0 2006.257.08:02:55.51#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:55.51#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:02:55.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:02:55.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:02:55.51$vck44/vabw=wide 2006.257.08:02:55.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.08:02:55.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.08:02:55.51#ibcon#ireg 8 cls_cnt 0 2006.257.08:02:55.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:55.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:55.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:55.51#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:02:55.51#ibcon#first serial, iclass 32, count 0 2006.257.08:02:55.51#ibcon#enter sib2, iclass 32, count 0 2006.257.08:02:55.51#ibcon#flushed, iclass 32, count 0 2006.257.08:02:55.51#ibcon#about to write, iclass 32, count 0 2006.257.08:02:55.51#ibcon#wrote, iclass 32, count 0 2006.257.08:02:55.51#ibcon#about to read 3, iclass 32, count 0 2006.257.08:02:55.53#ibcon#read 3, iclass 32, count 0 2006.257.08:02:55.53#ibcon#about to read 4, iclass 32, count 0 2006.257.08:02:55.53#ibcon#read 4, iclass 32, count 0 2006.257.08:02:55.53#ibcon#about to read 5, iclass 32, count 0 2006.257.08:02:55.53#ibcon#read 5, iclass 32, count 0 2006.257.08:02:55.53#ibcon#about to read 6, iclass 32, count 0 2006.257.08:02:55.53#ibcon#read 6, iclass 32, count 0 2006.257.08:02:55.53#ibcon#end of sib2, iclass 32, count 0 2006.257.08:02:55.53#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:02:55.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:02:55.53#ibcon#[25=BW32\r\n] 2006.257.08:02:55.53#ibcon#*before write, iclass 32, count 0 2006.257.08:02:55.53#ibcon#enter sib2, iclass 32, count 0 2006.257.08:02:55.53#ibcon#flushed, iclass 32, count 0 2006.257.08:02:55.53#ibcon#about to write, iclass 32, count 0 2006.257.08:02:55.53#ibcon#wrote, iclass 32, count 0 2006.257.08:02:55.53#ibcon#about to read 3, iclass 32, count 0 2006.257.08:02:55.56#ibcon#read 3, iclass 32, count 0 2006.257.08:02:55.56#ibcon#about to read 4, iclass 32, count 0 2006.257.08:02:55.56#ibcon#read 4, iclass 32, count 0 2006.257.08:02:55.56#ibcon#about to read 5, iclass 32, count 0 2006.257.08:02:55.56#ibcon#read 5, iclass 32, count 0 2006.257.08:02:55.56#ibcon#about to read 6, iclass 32, count 0 2006.257.08:02:55.56#ibcon#read 6, iclass 32, count 0 2006.257.08:02:55.56#ibcon#end of sib2, iclass 32, count 0 2006.257.08:02:55.56#ibcon#*after write, iclass 32, count 0 2006.257.08:02:55.56#ibcon#*before return 0, iclass 32, count 0 2006.257.08:02:55.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:55.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:02:55.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:02:55.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:02:55.56$vck44/vbbw=wide 2006.257.08:02:55.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.08:02:55.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.08:02:55.56#ibcon#ireg 8 cls_cnt 0 2006.257.08:02:55.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:02:55.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:02:55.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:02:55.63#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:02:55.63#ibcon#first serial, iclass 34, count 0 2006.257.08:02:55.63#ibcon#enter sib2, iclass 34, count 0 2006.257.08:02:55.63#ibcon#flushed, iclass 34, count 0 2006.257.08:02:55.63#ibcon#about to write, iclass 34, count 0 2006.257.08:02:55.63#ibcon#wrote, iclass 34, count 0 2006.257.08:02:55.63#ibcon#about to read 3, iclass 34, count 0 2006.257.08:02:55.65#ibcon#read 3, iclass 34, count 0 2006.257.08:02:55.65#ibcon#about to read 4, iclass 34, count 0 2006.257.08:02:55.65#ibcon#read 4, iclass 34, count 0 2006.257.08:02:55.65#ibcon#about to read 5, iclass 34, count 0 2006.257.08:02:55.65#ibcon#read 5, iclass 34, count 0 2006.257.08:02:55.65#ibcon#about to read 6, iclass 34, count 0 2006.257.08:02:55.65#ibcon#read 6, iclass 34, count 0 2006.257.08:02:55.65#ibcon#end of sib2, iclass 34, count 0 2006.257.08:02:55.65#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:02:55.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:02:55.65#ibcon#[27=BW32\r\n] 2006.257.08:02:55.65#ibcon#*before write, iclass 34, count 0 2006.257.08:02:55.65#ibcon#enter sib2, iclass 34, count 0 2006.257.08:02:55.65#ibcon#flushed, iclass 34, count 0 2006.257.08:02:55.65#ibcon#about to write, iclass 34, count 0 2006.257.08:02:55.65#ibcon#wrote, iclass 34, count 0 2006.257.08:02:55.65#ibcon#about to read 3, iclass 34, count 0 2006.257.08:02:55.68#ibcon#read 3, iclass 34, count 0 2006.257.08:02:55.68#ibcon#about to read 4, iclass 34, count 0 2006.257.08:02:55.68#ibcon#read 4, iclass 34, count 0 2006.257.08:02:55.68#ibcon#about to read 5, iclass 34, count 0 2006.257.08:02:55.68#ibcon#read 5, iclass 34, count 0 2006.257.08:02:55.68#ibcon#about to read 6, iclass 34, count 0 2006.257.08:02:55.68#ibcon#read 6, iclass 34, count 0 2006.257.08:02:55.68#ibcon#end of sib2, iclass 34, count 0 2006.257.08:02:55.68#ibcon#*after write, iclass 34, count 0 2006.257.08:02:55.68#ibcon#*before return 0, iclass 34, count 0 2006.257.08:02:55.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:02:55.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:02:55.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:02:55.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:02:55.68$setupk4/ifdk4 2006.257.08:02:55.68$ifdk4/lo= 2006.257.08:02:55.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:02:55.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:02:55.68$ifdk4/patch= 2006.257.08:02:55.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:02:55.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:02:55.68$setupk4/!*+20s 2006.257.08:02:57.72#abcon#<5=/16 1.3 4.1 20.96 881012.8\r\n> 2006.257.08:02:57.74#abcon#{5=INTERFACE CLEAR} 2006.257.08:02:57.80#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:03:07.89#abcon#<5=/16 1.3 4.1 20.96 881012.8\r\n> 2006.257.08:03:07.91#abcon#{5=INTERFACE CLEAR} 2006.257.08:03:07.97#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:03:10.21$setupk4/"tpicd 2006.257.08:03:10.21$setupk4/echo=off 2006.257.08:03:10.21$setupk4/xlog=off 2006.257.08:03:10.21:!2006.257.08:04:10 2006.257.08:03:25.14#trakl#Source acquired 2006.257.08:03:27.14#flagr#flagr/antenna,acquired 2006.257.08:04:10.00:preob 2006.257.08:04:10.14/onsource/TRACKING 2006.257.08:04:10.14:!2006.257.08:04:20 2006.257.08:04:20.00:"tape 2006.257.08:04:20.00:"st=record 2006.257.08:04:20.00:data_valid=on 2006.257.08:04:20.00:midob 2006.257.08:04:21.14/onsource/TRACKING 2006.257.08:04:21.14/wx/20.94,1012.8,87 2006.257.08:04:21.24/cable/+6.4762E-03 2006.257.08:04:22.33/va/01,08,usb,yes,39,42 2006.257.08:04:22.33/va/02,07,usb,yes,42,43 2006.257.08:04:22.33/va/03,08,usb,yes,38,40 2006.257.08:04:22.33/va/04,07,usb,yes,44,46 2006.257.08:04:22.33/va/05,04,usb,yes,39,40 2006.257.08:04:22.33/va/06,04,usb,yes,44,43 2006.257.08:04:22.33/va/07,04,usb,yes,45,45 2006.257.08:04:22.33/va/08,04,usb,yes,37,46 2006.257.08:04:22.56/valo/01,524.99,yes,locked 2006.257.08:04:22.56/valo/02,534.99,yes,locked 2006.257.08:04:22.56/valo/03,564.99,yes,locked 2006.257.08:04:22.56/valo/04,624.99,yes,locked 2006.257.08:04:22.56/valo/05,734.99,yes,locked 2006.257.08:04:22.56/valo/06,814.99,yes,locked 2006.257.08:04:22.56/valo/07,864.99,yes,locked 2006.257.08:04:22.56/valo/08,884.99,yes,locked 2006.257.08:04:23.65/vb/01,04,usb,yes,33,30 2006.257.08:04:23.65/vb/02,05,usb,yes,31,31 2006.257.08:04:23.65/vb/03,04,usb,yes,31,35 2006.257.08:04:23.65/vb/04,05,usb,yes,32,31 2006.257.08:04:23.65/vb/05,04,usb,yes,28,31 2006.257.08:04:23.65/vb/06,04,usb,yes,33,29 2006.257.08:04:23.65/vb/07,04,usb,yes,32,32 2006.257.08:04:23.65/vb/08,04,usb,yes,30,33 2006.257.08:04:23.88/vblo/01,629.99,yes,locked 2006.257.08:04:23.88/vblo/02,634.99,yes,locked 2006.257.08:04:23.88/vblo/03,649.99,yes,locked 2006.257.08:04:23.88/vblo/04,679.99,yes,locked 2006.257.08:04:23.88/vblo/05,709.99,yes,locked 2006.257.08:04:23.88/vblo/06,719.99,yes,locked 2006.257.08:04:23.88/vblo/07,734.99,yes,locked 2006.257.08:04:23.88/vblo/08,744.99,yes,locked 2006.257.08:04:24.03/vabw/8 2006.257.08:04:24.18/vbbw/8 2006.257.08:04:24.27/xfe/off,on,15.2 2006.257.08:04:24.65/ifatt/23,28,28,28 2006.257.08:04:25.07/fmout-gps/S +4.50E-07 2006.257.08:04:25.11:!2006.257.08:08:30 2006.257.08:08:30.00:data_valid=off 2006.257.08:08:30.00:"et 2006.257.08:08:30.00:!+3s 2006.257.08:08:33.01:"tape 2006.257.08:08:33.01:postob 2006.257.08:08:33.15/cable/+6.4770E-03 2006.257.08:08:33.15/wx/20.88,1012.9,87 2006.257.08:08:34.07/fmout-gps/S +4.53E-07 2006.257.08:08:34.07:scan_name=257-0811,jd0609,50 2006.257.08:08:34.07:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.08:08:35.14#flagr#flagr/antenna,new-source 2006.257.08:08:35.14:checkk5 2006.257.08:08:35.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:08:35.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:08:36.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:08:36.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:08:37.16/chk_obsdata//k5ts1/T2570804??a.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.257.08:08:37.55/chk_obsdata//k5ts2/T2570804??b.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.257.08:08:37.96/chk_obsdata//k5ts3/T2570804??c.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.257.08:08:38.36/chk_obsdata//k5ts4/T2570804??d.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.257.08:08:39.08/k5log//k5ts1_log_newline 2006.257.08:08:39.79/k5log//k5ts2_log_newline 2006.257.08:08:40.51/k5log//k5ts3_log_newline 2006.257.08:08:41.22/k5log//k5ts4_log_newline 2006.257.08:08:41.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:08:41.25:setupk4=1 2006.257.08:08:41.25$setupk4/echo=on 2006.257.08:08:41.25$setupk4/pcalon 2006.257.08:08:41.25$pcalon/"no phase cal control is implemented here 2006.257.08:08:41.25$setupk4/"tpicd=stop 2006.257.08:08:41.25$setupk4/"rec=synch_on 2006.257.08:08:41.25$setupk4/"rec_mode=128 2006.257.08:08:41.25$setupk4/!* 2006.257.08:08:41.25$setupk4/recpk4 2006.257.08:08:41.25$recpk4/recpatch= 2006.257.08:08:41.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:08:41.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:08:41.25$setupk4/vck44 2006.257.08:08:41.25$vck44/valo=1,524.99 2006.257.08:08:41.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.08:08:41.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.08:08:41.25#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:41.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:41.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:41.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:41.25#ibcon#enter wrdev, iclass 31, count 0 2006.257.08:08:41.25#ibcon#first serial, iclass 31, count 0 2006.257.08:08:41.25#ibcon#enter sib2, iclass 31, count 0 2006.257.08:08:41.25#ibcon#flushed, iclass 31, count 0 2006.257.08:08:41.25#ibcon#about to write, iclass 31, count 0 2006.257.08:08:41.25#ibcon#wrote, iclass 31, count 0 2006.257.08:08:41.25#ibcon#about to read 3, iclass 31, count 0 2006.257.08:08:41.27#ibcon#read 3, iclass 31, count 0 2006.257.08:08:41.27#ibcon#about to read 4, iclass 31, count 0 2006.257.08:08:41.27#ibcon#read 4, iclass 31, count 0 2006.257.08:08:41.27#ibcon#about to read 5, iclass 31, count 0 2006.257.08:08:41.27#ibcon#read 5, iclass 31, count 0 2006.257.08:08:41.27#ibcon#about to read 6, iclass 31, count 0 2006.257.08:08:41.27#ibcon#read 6, iclass 31, count 0 2006.257.08:08:41.27#ibcon#end of sib2, iclass 31, count 0 2006.257.08:08:41.27#ibcon#*mode == 0, iclass 31, count 0 2006.257.08:08:41.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.08:08:41.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:08:41.27#ibcon#*before write, iclass 31, count 0 2006.257.08:08:41.27#ibcon#enter sib2, iclass 31, count 0 2006.257.08:08:41.27#ibcon#flushed, iclass 31, count 0 2006.257.08:08:41.27#ibcon#about to write, iclass 31, count 0 2006.257.08:08:41.27#ibcon#wrote, iclass 31, count 0 2006.257.08:08:41.27#ibcon#about to read 3, iclass 31, count 0 2006.257.08:08:41.32#ibcon#read 3, iclass 31, count 0 2006.257.08:08:41.32#ibcon#about to read 4, iclass 31, count 0 2006.257.08:08:41.32#ibcon#read 4, iclass 31, count 0 2006.257.08:08:41.32#ibcon#about to read 5, iclass 31, count 0 2006.257.08:08:41.32#ibcon#read 5, iclass 31, count 0 2006.257.08:08:41.32#ibcon#about to read 6, iclass 31, count 0 2006.257.08:08:41.32#ibcon#read 6, iclass 31, count 0 2006.257.08:08:41.32#ibcon#end of sib2, iclass 31, count 0 2006.257.08:08:41.32#ibcon#*after write, iclass 31, count 0 2006.257.08:08:41.32#ibcon#*before return 0, iclass 31, count 0 2006.257.08:08:41.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:41.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:41.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.08:08:41.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.08:08:41.32$vck44/va=1,8 2006.257.08:08:41.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.08:08:41.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.08:08:41.32#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:41.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:41.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:41.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:41.32#ibcon#enter wrdev, iclass 33, count 2 2006.257.08:08:41.32#ibcon#first serial, iclass 33, count 2 2006.257.08:08:41.32#ibcon#enter sib2, iclass 33, count 2 2006.257.08:08:41.32#ibcon#flushed, iclass 33, count 2 2006.257.08:08:41.32#ibcon#about to write, iclass 33, count 2 2006.257.08:08:41.32#ibcon#wrote, iclass 33, count 2 2006.257.08:08:41.32#ibcon#about to read 3, iclass 33, count 2 2006.257.08:08:41.34#ibcon#read 3, iclass 33, count 2 2006.257.08:08:41.34#ibcon#about to read 4, iclass 33, count 2 2006.257.08:08:41.34#ibcon#read 4, iclass 33, count 2 2006.257.08:08:41.34#ibcon#about to read 5, iclass 33, count 2 2006.257.08:08:41.34#ibcon#read 5, iclass 33, count 2 2006.257.08:08:41.34#ibcon#about to read 6, iclass 33, count 2 2006.257.08:08:41.34#ibcon#read 6, iclass 33, count 2 2006.257.08:08:41.34#ibcon#end of sib2, iclass 33, count 2 2006.257.08:08:41.34#ibcon#*mode == 0, iclass 33, count 2 2006.257.08:08:41.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.08:08:41.34#ibcon#[25=AT01-08\r\n] 2006.257.08:08:41.34#ibcon#*before write, iclass 33, count 2 2006.257.08:08:41.34#ibcon#enter sib2, iclass 33, count 2 2006.257.08:08:41.34#ibcon#flushed, iclass 33, count 2 2006.257.08:08:41.34#ibcon#about to write, iclass 33, count 2 2006.257.08:08:41.34#ibcon#wrote, iclass 33, count 2 2006.257.08:08:41.34#ibcon#about to read 3, iclass 33, count 2 2006.257.08:08:41.37#ibcon#read 3, iclass 33, count 2 2006.257.08:08:41.37#ibcon#about to read 4, iclass 33, count 2 2006.257.08:08:41.37#ibcon#read 4, iclass 33, count 2 2006.257.08:08:41.37#ibcon#about to read 5, iclass 33, count 2 2006.257.08:08:41.37#ibcon#read 5, iclass 33, count 2 2006.257.08:08:41.37#ibcon#about to read 6, iclass 33, count 2 2006.257.08:08:41.37#ibcon#read 6, iclass 33, count 2 2006.257.08:08:41.37#ibcon#end of sib2, iclass 33, count 2 2006.257.08:08:41.37#ibcon#*after write, iclass 33, count 2 2006.257.08:08:41.37#ibcon#*before return 0, iclass 33, count 2 2006.257.08:08:41.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:41.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:41.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.08:08:41.37#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:41.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:41.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:41.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:41.49#ibcon#enter wrdev, iclass 33, count 0 2006.257.08:08:41.49#ibcon#first serial, iclass 33, count 0 2006.257.08:08:41.49#ibcon#enter sib2, iclass 33, count 0 2006.257.08:08:41.49#ibcon#flushed, iclass 33, count 0 2006.257.08:08:41.49#ibcon#about to write, iclass 33, count 0 2006.257.08:08:41.49#ibcon#wrote, iclass 33, count 0 2006.257.08:08:41.49#ibcon#about to read 3, iclass 33, count 0 2006.257.08:08:41.51#ibcon#read 3, iclass 33, count 0 2006.257.08:08:41.51#ibcon#about to read 4, iclass 33, count 0 2006.257.08:08:41.51#ibcon#read 4, iclass 33, count 0 2006.257.08:08:41.51#ibcon#about to read 5, iclass 33, count 0 2006.257.08:08:41.51#ibcon#read 5, iclass 33, count 0 2006.257.08:08:41.51#ibcon#about to read 6, iclass 33, count 0 2006.257.08:08:41.51#ibcon#read 6, iclass 33, count 0 2006.257.08:08:41.51#ibcon#end of sib2, iclass 33, count 0 2006.257.08:08:41.51#ibcon#*mode == 0, iclass 33, count 0 2006.257.08:08:41.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.08:08:41.51#ibcon#[25=USB\r\n] 2006.257.08:08:41.51#ibcon#*before write, iclass 33, count 0 2006.257.08:08:41.51#ibcon#enter sib2, iclass 33, count 0 2006.257.08:08:41.51#ibcon#flushed, iclass 33, count 0 2006.257.08:08:41.51#ibcon#about to write, iclass 33, count 0 2006.257.08:08:41.51#ibcon#wrote, iclass 33, count 0 2006.257.08:08:41.51#ibcon#about to read 3, iclass 33, count 0 2006.257.08:08:41.54#ibcon#read 3, iclass 33, count 0 2006.257.08:08:41.54#ibcon#about to read 4, iclass 33, count 0 2006.257.08:08:41.54#ibcon#read 4, iclass 33, count 0 2006.257.08:08:41.54#ibcon#about to read 5, iclass 33, count 0 2006.257.08:08:41.54#ibcon#read 5, iclass 33, count 0 2006.257.08:08:41.54#ibcon#about to read 6, iclass 33, count 0 2006.257.08:08:41.54#ibcon#read 6, iclass 33, count 0 2006.257.08:08:41.54#ibcon#end of sib2, iclass 33, count 0 2006.257.08:08:41.54#ibcon#*after write, iclass 33, count 0 2006.257.08:08:41.54#ibcon#*before return 0, iclass 33, count 0 2006.257.08:08:41.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:41.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:41.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.08:08:41.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.08:08:41.54$vck44/valo=2,534.99 2006.257.08:08:41.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.08:08:41.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.08:08:41.54#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:41.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:41.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:41.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:41.54#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:08:41.54#ibcon#first serial, iclass 35, count 0 2006.257.08:08:41.54#ibcon#enter sib2, iclass 35, count 0 2006.257.08:08:41.54#ibcon#flushed, iclass 35, count 0 2006.257.08:08:41.54#ibcon#about to write, iclass 35, count 0 2006.257.08:08:41.54#ibcon#wrote, iclass 35, count 0 2006.257.08:08:41.54#ibcon#about to read 3, iclass 35, count 0 2006.257.08:08:41.56#ibcon#read 3, iclass 35, count 0 2006.257.08:08:41.56#ibcon#about to read 4, iclass 35, count 0 2006.257.08:08:41.56#ibcon#read 4, iclass 35, count 0 2006.257.08:08:41.56#ibcon#about to read 5, iclass 35, count 0 2006.257.08:08:41.56#ibcon#read 5, iclass 35, count 0 2006.257.08:08:41.56#ibcon#about to read 6, iclass 35, count 0 2006.257.08:08:41.56#ibcon#read 6, iclass 35, count 0 2006.257.08:08:41.56#ibcon#end of sib2, iclass 35, count 0 2006.257.08:08:41.56#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:08:41.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:08:41.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:08:41.56#ibcon#*before write, iclass 35, count 0 2006.257.08:08:41.56#ibcon#enter sib2, iclass 35, count 0 2006.257.08:08:41.56#ibcon#flushed, iclass 35, count 0 2006.257.08:08:41.56#ibcon#about to write, iclass 35, count 0 2006.257.08:08:41.56#ibcon#wrote, iclass 35, count 0 2006.257.08:08:41.56#ibcon#about to read 3, iclass 35, count 0 2006.257.08:08:41.60#ibcon#read 3, iclass 35, count 0 2006.257.08:08:41.60#ibcon#about to read 4, iclass 35, count 0 2006.257.08:08:41.60#ibcon#read 4, iclass 35, count 0 2006.257.08:08:41.60#ibcon#about to read 5, iclass 35, count 0 2006.257.08:08:41.60#ibcon#read 5, iclass 35, count 0 2006.257.08:08:41.60#ibcon#about to read 6, iclass 35, count 0 2006.257.08:08:41.60#ibcon#read 6, iclass 35, count 0 2006.257.08:08:41.60#ibcon#end of sib2, iclass 35, count 0 2006.257.08:08:41.60#ibcon#*after write, iclass 35, count 0 2006.257.08:08:41.60#ibcon#*before return 0, iclass 35, count 0 2006.257.08:08:41.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:41.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:41.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:08:41.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:08:41.60$vck44/va=2,7 2006.257.08:08:41.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.08:08:41.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.08:08:41.60#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:41.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:41.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:41.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:41.66#ibcon#enter wrdev, iclass 37, count 2 2006.257.08:08:41.66#ibcon#first serial, iclass 37, count 2 2006.257.08:08:41.66#ibcon#enter sib2, iclass 37, count 2 2006.257.08:08:41.66#ibcon#flushed, iclass 37, count 2 2006.257.08:08:41.66#ibcon#about to write, iclass 37, count 2 2006.257.08:08:41.66#ibcon#wrote, iclass 37, count 2 2006.257.08:08:41.66#ibcon#about to read 3, iclass 37, count 2 2006.257.08:08:41.68#ibcon#read 3, iclass 37, count 2 2006.257.08:08:41.68#ibcon#about to read 4, iclass 37, count 2 2006.257.08:08:41.68#ibcon#read 4, iclass 37, count 2 2006.257.08:08:41.68#ibcon#about to read 5, iclass 37, count 2 2006.257.08:08:41.68#ibcon#read 5, iclass 37, count 2 2006.257.08:08:41.68#ibcon#about to read 6, iclass 37, count 2 2006.257.08:08:41.68#ibcon#read 6, iclass 37, count 2 2006.257.08:08:41.68#ibcon#end of sib2, iclass 37, count 2 2006.257.08:08:41.68#ibcon#*mode == 0, iclass 37, count 2 2006.257.08:08:41.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.08:08:41.68#ibcon#[25=AT02-07\r\n] 2006.257.08:08:41.68#ibcon#*before write, iclass 37, count 2 2006.257.08:08:41.68#ibcon#enter sib2, iclass 37, count 2 2006.257.08:08:41.68#ibcon#flushed, iclass 37, count 2 2006.257.08:08:41.68#ibcon#about to write, iclass 37, count 2 2006.257.08:08:41.68#ibcon#wrote, iclass 37, count 2 2006.257.08:08:41.68#ibcon#about to read 3, iclass 37, count 2 2006.257.08:08:41.71#ibcon#read 3, iclass 37, count 2 2006.257.08:08:41.71#ibcon#about to read 4, iclass 37, count 2 2006.257.08:08:41.71#ibcon#read 4, iclass 37, count 2 2006.257.08:08:41.71#ibcon#about to read 5, iclass 37, count 2 2006.257.08:08:41.71#ibcon#read 5, iclass 37, count 2 2006.257.08:08:41.71#ibcon#about to read 6, iclass 37, count 2 2006.257.08:08:41.71#ibcon#read 6, iclass 37, count 2 2006.257.08:08:41.71#ibcon#end of sib2, iclass 37, count 2 2006.257.08:08:41.71#ibcon#*after write, iclass 37, count 2 2006.257.08:08:41.71#ibcon#*before return 0, iclass 37, count 2 2006.257.08:08:41.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:41.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:41.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.08:08:41.71#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:41.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:41.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:41.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:41.83#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:08:41.83#ibcon#first serial, iclass 37, count 0 2006.257.08:08:41.83#ibcon#enter sib2, iclass 37, count 0 2006.257.08:08:41.83#ibcon#flushed, iclass 37, count 0 2006.257.08:08:41.83#ibcon#about to write, iclass 37, count 0 2006.257.08:08:41.83#ibcon#wrote, iclass 37, count 0 2006.257.08:08:41.83#ibcon#about to read 3, iclass 37, count 0 2006.257.08:08:41.85#ibcon#read 3, iclass 37, count 0 2006.257.08:08:41.85#ibcon#about to read 4, iclass 37, count 0 2006.257.08:08:41.85#ibcon#read 4, iclass 37, count 0 2006.257.08:08:41.85#ibcon#about to read 5, iclass 37, count 0 2006.257.08:08:41.85#ibcon#read 5, iclass 37, count 0 2006.257.08:08:41.85#ibcon#about to read 6, iclass 37, count 0 2006.257.08:08:41.85#ibcon#read 6, iclass 37, count 0 2006.257.08:08:41.85#ibcon#end of sib2, iclass 37, count 0 2006.257.08:08:41.85#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:08:41.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:08:41.85#ibcon#[25=USB\r\n] 2006.257.08:08:41.85#ibcon#*before write, iclass 37, count 0 2006.257.08:08:41.85#ibcon#enter sib2, iclass 37, count 0 2006.257.08:08:41.85#ibcon#flushed, iclass 37, count 0 2006.257.08:08:41.85#ibcon#about to write, iclass 37, count 0 2006.257.08:08:41.85#ibcon#wrote, iclass 37, count 0 2006.257.08:08:41.85#ibcon#about to read 3, iclass 37, count 0 2006.257.08:08:41.88#ibcon#read 3, iclass 37, count 0 2006.257.08:08:41.88#ibcon#about to read 4, iclass 37, count 0 2006.257.08:08:41.88#ibcon#read 4, iclass 37, count 0 2006.257.08:08:41.88#ibcon#about to read 5, iclass 37, count 0 2006.257.08:08:41.88#ibcon#read 5, iclass 37, count 0 2006.257.08:08:41.88#ibcon#about to read 6, iclass 37, count 0 2006.257.08:08:41.88#ibcon#read 6, iclass 37, count 0 2006.257.08:08:41.88#ibcon#end of sib2, iclass 37, count 0 2006.257.08:08:41.88#ibcon#*after write, iclass 37, count 0 2006.257.08:08:41.88#ibcon#*before return 0, iclass 37, count 0 2006.257.08:08:41.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:41.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:41.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:08:41.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:08:41.88$vck44/valo=3,564.99 2006.257.08:08:41.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.08:08:41.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.08:08:41.88#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:41.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:41.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:41.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:41.88#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:08:41.88#ibcon#first serial, iclass 39, count 0 2006.257.08:08:41.88#ibcon#enter sib2, iclass 39, count 0 2006.257.08:08:41.88#ibcon#flushed, iclass 39, count 0 2006.257.08:08:41.88#ibcon#about to write, iclass 39, count 0 2006.257.08:08:41.88#ibcon#wrote, iclass 39, count 0 2006.257.08:08:41.88#ibcon#about to read 3, iclass 39, count 0 2006.257.08:08:41.90#ibcon#read 3, iclass 39, count 0 2006.257.08:08:41.90#ibcon#about to read 4, iclass 39, count 0 2006.257.08:08:41.90#ibcon#read 4, iclass 39, count 0 2006.257.08:08:41.90#ibcon#about to read 5, iclass 39, count 0 2006.257.08:08:41.90#ibcon#read 5, iclass 39, count 0 2006.257.08:08:41.90#ibcon#about to read 6, iclass 39, count 0 2006.257.08:08:41.90#ibcon#read 6, iclass 39, count 0 2006.257.08:08:41.90#ibcon#end of sib2, iclass 39, count 0 2006.257.08:08:41.90#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:08:41.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:08:41.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:08:41.90#ibcon#*before write, iclass 39, count 0 2006.257.08:08:41.90#ibcon#enter sib2, iclass 39, count 0 2006.257.08:08:41.90#ibcon#flushed, iclass 39, count 0 2006.257.08:08:41.90#ibcon#about to write, iclass 39, count 0 2006.257.08:08:41.90#ibcon#wrote, iclass 39, count 0 2006.257.08:08:41.90#ibcon#about to read 3, iclass 39, count 0 2006.257.08:08:41.94#ibcon#read 3, iclass 39, count 0 2006.257.08:08:41.94#ibcon#about to read 4, iclass 39, count 0 2006.257.08:08:41.94#ibcon#read 4, iclass 39, count 0 2006.257.08:08:41.94#ibcon#about to read 5, iclass 39, count 0 2006.257.08:08:41.94#ibcon#read 5, iclass 39, count 0 2006.257.08:08:41.94#ibcon#about to read 6, iclass 39, count 0 2006.257.08:08:41.94#ibcon#read 6, iclass 39, count 0 2006.257.08:08:41.94#ibcon#end of sib2, iclass 39, count 0 2006.257.08:08:41.94#ibcon#*after write, iclass 39, count 0 2006.257.08:08:41.94#ibcon#*before return 0, iclass 39, count 0 2006.257.08:08:41.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:41.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:41.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:08:41.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:08:41.94$vck44/va=3,8 2006.257.08:08:41.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.08:08:41.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.08:08:41.94#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:41.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:42.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:42.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:42.00#ibcon#enter wrdev, iclass 3, count 2 2006.257.08:08:42.00#ibcon#first serial, iclass 3, count 2 2006.257.08:08:42.00#ibcon#enter sib2, iclass 3, count 2 2006.257.08:08:42.00#ibcon#flushed, iclass 3, count 2 2006.257.08:08:42.00#ibcon#about to write, iclass 3, count 2 2006.257.08:08:42.00#ibcon#wrote, iclass 3, count 2 2006.257.08:08:42.00#ibcon#about to read 3, iclass 3, count 2 2006.257.08:08:42.02#ibcon#read 3, iclass 3, count 2 2006.257.08:08:42.02#ibcon#about to read 4, iclass 3, count 2 2006.257.08:08:42.02#ibcon#read 4, iclass 3, count 2 2006.257.08:08:42.02#ibcon#about to read 5, iclass 3, count 2 2006.257.08:08:42.02#ibcon#read 5, iclass 3, count 2 2006.257.08:08:42.02#ibcon#about to read 6, iclass 3, count 2 2006.257.08:08:42.02#ibcon#read 6, iclass 3, count 2 2006.257.08:08:42.02#ibcon#end of sib2, iclass 3, count 2 2006.257.08:08:42.02#ibcon#*mode == 0, iclass 3, count 2 2006.257.08:08:42.02#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.08:08:42.02#ibcon#[25=AT03-08\r\n] 2006.257.08:08:42.02#ibcon#*before write, iclass 3, count 2 2006.257.08:08:42.02#ibcon#enter sib2, iclass 3, count 2 2006.257.08:08:42.02#ibcon#flushed, iclass 3, count 2 2006.257.08:08:42.02#ibcon#about to write, iclass 3, count 2 2006.257.08:08:42.02#ibcon#wrote, iclass 3, count 2 2006.257.08:08:42.02#ibcon#about to read 3, iclass 3, count 2 2006.257.08:08:42.05#ibcon#read 3, iclass 3, count 2 2006.257.08:08:42.05#ibcon#about to read 4, iclass 3, count 2 2006.257.08:08:42.05#ibcon#read 4, iclass 3, count 2 2006.257.08:08:42.05#ibcon#about to read 5, iclass 3, count 2 2006.257.08:08:42.05#ibcon#read 5, iclass 3, count 2 2006.257.08:08:42.05#ibcon#about to read 6, iclass 3, count 2 2006.257.08:08:42.05#ibcon#read 6, iclass 3, count 2 2006.257.08:08:42.05#ibcon#end of sib2, iclass 3, count 2 2006.257.08:08:42.05#ibcon#*after write, iclass 3, count 2 2006.257.08:08:42.05#ibcon#*before return 0, iclass 3, count 2 2006.257.08:08:42.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:42.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:42.05#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.08:08:42.05#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:42.05#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:42.17#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:42.17#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:42.17#ibcon#enter wrdev, iclass 3, count 0 2006.257.08:08:42.17#ibcon#first serial, iclass 3, count 0 2006.257.08:08:42.17#ibcon#enter sib2, iclass 3, count 0 2006.257.08:08:42.17#ibcon#flushed, iclass 3, count 0 2006.257.08:08:42.17#ibcon#about to write, iclass 3, count 0 2006.257.08:08:42.17#ibcon#wrote, iclass 3, count 0 2006.257.08:08:42.17#ibcon#about to read 3, iclass 3, count 0 2006.257.08:08:42.19#ibcon#read 3, iclass 3, count 0 2006.257.08:08:42.19#ibcon#about to read 4, iclass 3, count 0 2006.257.08:08:42.19#ibcon#read 4, iclass 3, count 0 2006.257.08:08:42.19#ibcon#about to read 5, iclass 3, count 0 2006.257.08:08:42.19#ibcon#read 5, iclass 3, count 0 2006.257.08:08:42.19#ibcon#about to read 6, iclass 3, count 0 2006.257.08:08:42.19#ibcon#read 6, iclass 3, count 0 2006.257.08:08:42.19#ibcon#end of sib2, iclass 3, count 0 2006.257.08:08:42.19#ibcon#*mode == 0, iclass 3, count 0 2006.257.08:08:42.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.08:08:42.19#ibcon#[25=USB\r\n] 2006.257.08:08:42.19#ibcon#*before write, iclass 3, count 0 2006.257.08:08:42.19#ibcon#enter sib2, iclass 3, count 0 2006.257.08:08:42.19#ibcon#flushed, iclass 3, count 0 2006.257.08:08:42.19#ibcon#about to write, iclass 3, count 0 2006.257.08:08:42.19#ibcon#wrote, iclass 3, count 0 2006.257.08:08:42.19#ibcon#about to read 3, iclass 3, count 0 2006.257.08:08:42.22#ibcon#read 3, iclass 3, count 0 2006.257.08:08:42.22#ibcon#about to read 4, iclass 3, count 0 2006.257.08:08:42.22#ibcon#read 4, iclass 3, count 0 2006.257.08:08:42.22#ibcon#about to read 5, iclass 3, count 0 2006.257.08:08:42.22#ibcon#read 5, iclass 3, count 0 2006.257.08:08:42.22#ibcon#about to read 6, iclass 3, count 0 2006.257.08:08:42.22#ibcon#read 6, iclass 3, count 0 2006.257.08:08:42.22#ibcon#end of sib2, iclass 3, count 0 2006.257.08:08:42.22#ibcon#*after write, iclass 3, count 0 2006.257.08:08:42.22#ibcon#*before return 0, iclass 3, count 0 2006.257.08:08:42.22#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:42.22#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:42.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.08:08:42.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.08:08:42.22$vck44/valo=4,624.99 2006.257.08:08:42.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.08:08:42.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.08:08:42.22#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:42.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:42.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:42.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:42.22#ibcon#enter wrdev, iclass 5, count 0 2006.257.08:08:42.22#ibcon#first serial, iclass 5, count 0 2006.257.08:08:42.22#ibcon#enter sib2, iclass 5, count 0 2006.257.08:08:42.22#ibcon#flushed, iclass 5, count 0 2006.257.08:08:42.22#ibcon#about to write, iclass 5, count 0 2006.257.08:08:42.22#ibcon#wrote, iclass 5, count 0 2006.257.08:08:42.22#ibcon#about to read 3, iclass 5, count 0 2006.257.08:08:42.24#ibcon#read 3, iclass 5, count 0 2006.257.08:08:42.24#ibcon#about to read 4, iclass 5, count 0 2006.257.08:08:42.24#ibcon#read 4, iclass 5, count 0 2006.257.08:08:42.24#ibcon#about to read 5, iclass 5, count 0 2006.257.08:08:42.24#ibcon#read 5, iclass 5, count 0 2006.257.08:08:42.24#ibcon#about to read 6, iclass 5, count 0 2006.257.08:08:42.24#ibcon#read 6, iclass 5, count 0 2006.257.08:08:42.24#ibcon#end of sib2, iclass 5, count 0 2006.257.08:08:42.24#ibcon#*mode == 0, iclass 5, count 0 2006.257.08:08:42.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.08:08:42.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:08:42.24#ibcon#*before write, iclass 5, count 0 2006.257.08:08:42.24#ibcon#enter sib2, iclass 5, count 0 2006.257.08:08:42.24#ibcon#flushed, iclass 5, count 0 2006.257.08:08:42.24#ibcon#about to write, iclass 5, count 0 2006.257.08:08:42.24#ibcon#wrote, iclass 5, count 0 2006.257.08:08:42.24#ibcon#about to read 3, iclass 5, count 0 2006.257.08:08:42.28#ibcon#read 3, iclass 5, count 0 2006.257.08:08:42.28#ibcon#about to read 4, iclass 5, count 0 2006.257.08:08:42.28#ibcon#read 4, iclass 5, count 0 2006.257.08:08:42.28#ibcon#about to read 5, iclass 5, count 0 2006.257.08:08:42.28#ibcon#read 5, iclass 5, count 0 2006.257.08:08:42.28#ibcon#about to read 6, iclass 5, count 0 2006.257.08:08:42.28#ibcon#read 6, iclass 5, count 0 2006.257.08:08:42.28#ibcon#end of sib2, iclass 5, count 0 2006.257.08:08:42.28#ibcon#*after write, iclass 5, count 0 2006.257.08:08:42.28#ibcon#*before return 0, iclass 5, count 0 2006.257.08:08:42.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:42.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:42.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.08:08:42.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.08:08:42.28$vck44/va=4,7 2006.257.08:08:42.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.08:08:42.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.08:08:42.28#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:42.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:42.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:42.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:42.34#ibcon#enter wrdev, iclass 7, count 2 2006.257.08:08:42.34#ibcon#first serial, iclass 7, count 2 2006.257.08:08:42.34#ibcon#enter sib2, iclass 7, count 2 2006.257.08:08:42.34#ibcon#flushed, iclass 7, count 2 2006.257.08:08:42.34#ibcon#about to write, iclass 7, count 2 2006.257.08:08:42.34#ibcon#wrote, iclass 7, count 2 2006.257.08:08:42.34#ibcon#about to read 3, iclass 7, count 2 2006.257.08:08:42.36#ibcon#read 3, iclass 7, count 2 2006.257.08:08:42.36#ibcon#about to read 4, iclass 7, count 2 2006.257.08:08:42.36#ibcon#read 4, iclass 7, count 2 2006.257.08:08:42.36#ibcon#about to read 5, iclass 7, count 2 2006.257.08:08:42.36#ibcon#read 5, iclass 7, count 2 2006.257.08:08:42.36#ibcon#about to read 6, iclass 7, count 2 2006.257.08:08:42.36#ibcon#read 6, iclass 7, count 2 2006.257.08:08:42.36#ibcon#end of sib2, iclass 7, count 2 2006.257.08:08:42.36#ibcon#*mode == 0, iclass 7, count 2 2006.257.08:08:42.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.08:08:42.36#ibcon#[25=AT04-07\r\n] 2006.257.08:08:42.36#ibcon#*before write, iclass 7, count 2 2006.257.08:08:42.36#ibcon#enter sib2, iclass 7, count 2 2006.257.08:08:42.36#ibcon#flushed, iclass 7, count 2 2006.257.08:08:42.36#ibcon#about to write, iclass 7, count 2 2006.257.08:08:42.36#ibcon#wrote, iclass 7, count 2 2006.257.08:08:42.36#ibcon#about to read 3, iclass 7, count 2 2006.257.08:08:42.39#ibcon#read 3, iclass 7, count 2 2006.257.08:08:42.39#ibcon#about to read 4, iclass 7, count 2 2006.257.08:08:42.39#ibcon#read 4, iclass 7, count 2 2006.257.08:08:42.39#ibcon#about to read 5, iclass 7, count 2 2006.257.08:08:42.39#ibcon#read 5, iclass 7, count 2 2006.257.08:08:42.39#ibcon#about to read 6, iclass 7, count 2 2006.257.08:08:42.39#ibcon#read 6, iclass 7, count 2 2006.257.08:08:42.39#ibcon#end of sib2, iclass 7, count 2 2006.257.08:08:42.39#ibcon#*after write, iclass 7, count 2 2006.257.08:08:42.39#ibcon#*before return 0, iclass 7, count 2 2006.257.08:08:42.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:42.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:42.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.08:08:42.39#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:42.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:42.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:42.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:42.51#ibcon#enter wrdev, iclass 7, count 0 2006.257.08:08:42.51#ibcon#first serial, iclass 7, count 0 2006.257.08:08:42.51#ibcon#enter sib2, iclass 7, count 0 2006.257.08:08:42.51#ibcon#flushed, iclass 7, count 0 2006.257.08:08:42.51#ibcon#about to write, iclass 7, count 0 2006.257.08:08:42.51#ibcon#wrote, iclass 7, count 0 2006.257.08:08:42.51#ibcon#about to read 3, iclass 7, count 0 2006.257.08:08:42.53#ibcon#read 3, iclass 7, count 0 2006.257.08:08:42.53#ibcon#about to read 4, iclass 7, count 0 2006.257.08:08:42.53#ibcon#read 4, iclass 7, count 0 2006.257.08:08:42.53#ibcon#about to read 5, iclass 7, count 0 2006.257.08:08:42.53#ibcon#read 5, iclass 7, count 0 2006.257.08:08:42.53#ibcon#about to read 6, iclass 7, count 0 2006.257.08:08:42.53#ibcon#read 6, iclass 7, count 0 2006.257.08:08:42.53#ibcon#end of sib2, iclass 7, count 0 2006.257.08:08:42.53#ibcon#*mode == 0, iclass 7, count 0 2006.257.08:08:42.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.08:08:42.53#ibcon#[25=USB\r\n] 2006.257.08:08:42.53#ibcon#*before write, iclass 7, count 0 2006.257.08:08:42.53#ibcon#enter sib2, iclass 7, count 0 2006.257.08:08:42.53#ibcon#flushed, iclass 7, count 0 2006.257.08:08:42.53#ibcon#about to write, iclass 7, count 0 2006.257.08:08:42.53#ibcon#wrote, iclass 7, count 0 2006.257.08:08:42.53#ibcon#about to read 3, iclass 7, count 0 2006.257.08:08:42.56#ibcon#read 3, iclass 7, count 0 2006.257.08:08:42.56#ibcon#about to read 4, iclass 7, count 0 2006.257.08:08:42.56#ibcon#read 4, iclass 7, count 0 2006.257.08:08:42.56#ibcon#about to read 5, iclass 7, count 0 2006.257.08:08:42.56#ibcon#read 5, iclass 7, count 0 2006.257.08:08:42.56#ibcon#about to read 6, iclass 7, count 0 2006.257.08:08:42.56#ibcon#read 6, iclass 7, count 0 2006.257.08:08:42.56#ibcon#end of sib2, iclass 7, count 0 2006.257.08:08:42.56#ibcon#*after write, iclass 7, count 0 2006.257.08:08:42.56#ibcon#*before return 0, iclass 7, count 0 2006.257.08:08:42.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:42.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:42.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.08:08:42.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.08:08:42.56$vck44/valo=5,734.99 2006.257.08:08:42.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.08:08:42.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.08:08:42.56#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:42.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:42.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:42.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:42.56#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:08:42.56#ibcon#first serial, iclass 11, count 0 2006.257.08:08:42.56#ibcon#enter sib2, iclass 11, count 0 2006.257.08:08:42.56#ibcon#flushed, iclass 11, count 0 2006.257.08:08:42.56#ibcon#about to write, iclass 11, count 0 2006.257.08:08:42.56#ibcon#wrote, iclass 11, count 0 2006.257.08:08:42.56#ibcon#about to read 3, iclass 11, count 0 2006.257.08:08:42.58#ibcon#read 3, iclass 11, count 0 2006.257.08:08:42.58#ibcon#about to read 4, iclass 11, count 0 2006.257.08:08:42.58#ibcon#read 4, iclass 11, count 0 2006.257.08:08:42.58#ibcon#about to read 5, iclass 11, count 0 2006.257.08:08:42.58#ibcon#read 5, iclass 11, count 0 2006.257.08:08:42.58#ibcon#about to read 6, iclass 11, count 0 2006.257.08:08:42.58#ibcon#read 6, iclass 11, count 0 2006.257.08:08:42.58#ibcon#end of sib2, iclass 11, count 0 2006.257.08:08:42.58#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:08:42.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:08:42.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:08:42.58#ibcon#*before write, iclass 11, count 0 2006.257.08:08:42.58#ibcon#enter sib2, iclass 11, count 0 2006.257.08:08:42.58#ibcon#flushed, iclass 11, count 0 2006.257.08:08:42.58#ibcon#about to write, iclass 11, count 0 2006.257.08:08:42.58#ibcon#wrote, iclass 11, count 0 2006.257.08:08:42.58#ibcon#about to read 3, iclass 11, count 0 2006.257.08:08:42.62#ibcon#read 3, iclass 11, count 0 2006.257.08:08:42.62#ibcon#about to read 4, iclass 11, count 0 2006.257.08:08:42.62#ibcon#read 4, iclass 11, count 0 2006.257.08:08:42.62#ibcon#about to read 5, iclass 11, count 0 2006.257.08:08:42.62#ibcon#read 5, iclass 11, count 0 2006.257.08:08:42.62#ibcon#about to read 6, iclass 11, count 0 2006.257.08:08:42.62#ibcon#read 6, iclass 11, count 0 2006.257.08:08:42.62#ibcon#end of sib2, iclass 11, count 0 2006.257.08:08:42.62#ibcon#*after write, iclass 11, count 0 2006.257.08:08:42.62#ibcon#*before return 0, iclass 11, count 0 2006.257.08:08:42.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:42.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:42.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:08:42.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:08:42.62$vck44/va=5,4 2006.257.08:08:42.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.08:08:42.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.08:08:42.62#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:42.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:42.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:42.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:42.68#ibcon#enter wrdev, iclass 13, count 2 2006.257.08:08:42.68#ibcon#first serial, iclass 13, count 2 2006.257.08:08:42.68#ibcon#enter sib2, iclass 13, count 2 2006.257.08:08:42.68#ibcon#flushed, iclass 13, count 2 2006.257.08:08:42.68#ibcon#about to write, iclass 13, count 2 2006.257.08:08:42.68#ibcon#wrote, iclass 13, count 2 2006.257.08:08:42.68#ibcon#about to read 3, iclass 13, count 2 2006.257.08:08:42.70#ibcon#read 3, iclass 13, count 2 2006.257.08:08:42.70#ibcon#about to read 4, iclass 13, count 2 2006.257.08:08:42.70#ibcon#read 4, iclass 13, count 2 2006.257.08:08:42.70#ibcon#about to read 5, iclass 13, count 2 2006.257.08:08:42.70#ibcon#read 5, iclass 13, count 2 2006.257.08:08:42.70#ibcon#about to read 6, iclass 13, count 2 2006.257.08:08:42.70#ibcon#read 6, iclass 13, count 2 2006.257.08:08:42.70#ibcon#end of sib2, iclass 13, count 2 2006.257.08:08:42.70#ibcon#*mode == 0, iclass 13, count 2 2006.257.08:08:42.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.08:08:42.70#ibcon#[25=AT05-04\r\n] 2006.257.08:08:42.70#ibcon#*before write, iclass 13, count 2 2006.257.08:08:42.70#ibcon#enter sib2, iclass 13, count 2 2006.257.08:08:42.70#ibcon#flushed, iclass 13, count 2 2006.257.08:08:42.70#ibcon#about to write, iclass 13, count 2 2006.257.08:08:42.70#ibcon#wrote, iclass 13, count 2 2006.257.08:08:42.70#ibcon#about to read 3, iclass 13, count 2 2006.257.08:08:42.73#ibcon#read 3, iclass 13, count 2 2006.257.08:08:42.73#ibcon#about to read 4, iclass 13, count 2 2006.257.08:08:42.73#ibcon#read 4, iclass 13, count 2 2006.257.08:08:42.73#ibcon#about to read 5, iclass 13, count 2 2006.257.08:08:42.73#ibcon#read 5, iclass 13, count 2 2006.257.08:08:42.73#ibcon#about to read 6, iclass 13, count 2 2006.257.08:08:42.73#ibcon#read 6, iclass 13, count 2 2006.257.08:08:42.73#ibcon#end of sib2, iclass 13, count 2 2006.257.08:08:42.73#ibcon#*after write, iclass 13, count 2 2006.257.08:08:42.73#ibcon#*before return 0, iclass 13, count 2 2006.257.08:08:42.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:42.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:42.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.08:08:42.73#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:42.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:42.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:42.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:42.85#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:08:42.85#ibcon#first serial, iclass 13, count 0 2006.257.08:08:42.85#ibcon#enter sib2, iclass 13, count 0 2006.257.08:08:42.85#ibcon#flushed, iclass 13, count 0 2006.257.08:08:42.85#ibcon#about to write, iclass 13, count 0 2006.257.08:08:42.85#ibcon#wrote, iclass 13, count 0 2006.257.08:08:42.85#ibcon#about to read 3, iclass 13, count 0 2006.257.08:08:42.87#ibcon#read 3, iclass 13, count 0 2006.257.08:08:42.87#ibcon#about to read 4, iclass 13, count 0 2006.257.08:08:42.87#ibcon#read 4, iclass 13, count 0 2006.257.08:08:42.87#ibcon#about to read 5, iclass 13, count 0 2006.257.08:08:42.87#ibcon#read 5, iclass 13, count 0 2006.257.08:08:42.87#ibcon#about to read 6, iclass 13, count 0 2006.257.08:08:42.87#ibcon#read 6, iclass 13, count 0 2006.257.08:08:42.87#ibcon#end of sib2, iclass 13, count 0 2006.257.08:08:42.87#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:08:42.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:08:42.87#ibcon#[25=USB\r\n] 2006.257.08:08:42.87#ibcon#*before write, iclass 13, count 0 2006.257.08:08:42.87#ibcon#enter sib2, iclass 13, count 0 2006.257.08:08:42.87#ibcon#flushed, iclass 13, count 0 2006.257.08:08:42.87#ibcon#about to write, iclass 13, count 0 2006.257.08:08:42.87#ibcon#wrote, iclass 13, count 0 2006.257.08:08:42.87#ibcon#about to read 3, iclass 13, count 0 2006.257.08:08:42.90#ibcon#read 3, iclass 13, count 0 2006.257.08:08:42.90#ibcon#about to read 4, iclass 13, count 0 2006.257.08:08:42.90#ibcon#read 4, iclass 13, count 0 2006.257.08:08:42.90#ibcon#about to read 5, iclass 13, count 0 2006.257.08:08:42.90#ibcon#read 5, iclass 13, count 0 2006.257.08:08:42.90#ibcon#about to read 6, iclass 13, count 0 2006.257.08:08:42.90#ibcon#read 6, iclass 13, count 0 2006.257.08:08:42.90#ibcon#end of sib2, iclass 13, count 0 2006.257.08:08:42.90#ibcon#*after write, iclass 13, count 0 2006.257.08:08:42.90#ibcon#*before return 0, iclass 13, count 0 2006.257.08:08:42.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:42.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:42.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:08:42.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:08:42.90$vck44/valo=6,814.99 2006.257.08:08:42.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.08:08:42.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.08:08:42.90#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:42.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:42.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:42.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:42.90#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:08:42.90#ibcon#first serial, iclass 15, count 0 2006.257.08:08:42.90#ibcon#enter sib2, iclass 15, count 0 2006.257.08:08:42.90#ibcon#flushed, iclass 15, count 0 2006.257.08:08:42.90#ibcon#about to write, iclass 15, count 0 2006.257.08:08:42.90#ibcon#wrote, iclass 15, count 0 2006.257.08:08:42.90#ibcon#about to read 3, iclass 15, count 0 2006.257.08:08:42.92#ibcon#read 3, iclass 15, count 0 2006.257.08:08:42.92#ibcon#about to read 4, iclass 15, count 0 2006.257.08:08:42.92#ibcon#read 4, iclass 15, count 0 2006.257.08:08:42.92#ibcon#about to read 5, iclass 15, count 0 2006.257.08:08:42.92#ibcon#read 5, iclass 15, count 0 2006.257.08:08:42.92#ibcon#about to read 6, iclass 15, count 0 2006.257.08:08:42.92#ibcon#read 6, iclass 15, count 0 2006.257.08:08:42.92#ibcon#end of sib2, iclass 15, count 0 2006.257.08:08:42.92#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:08:42.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:08:42.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:08:42.92#ibcon#*before write, iclass 15, count 0 2006.257.08:08:42.92#ibcon#enter sib2, iclass 15, count 0 2006.257.08:08:42.92#ibcon#flushed, iclass 15, count 0 2006.257.08:08:42.92#ibcon#about to write, iclass 15, count 0 2006.257.08:08:42.92#ibcon#wrote, iclass 15, count 0 2006.257.08:08:42.92#ibcon#about to read 3, iclass 15, count 0 2006.257.08:08:42.96#ibcon#read 3, iclass 15, count 0 2006.257.08:08:42.96#ibcon#about to read 4, iclass 15, count 0 2006.257.08:08:42.96#ibcon#read 4, iclass 15, count 0 2006.257.08:08:42.96#ibcon#about to read 5, iclass 15, count 0 2006.257.08:08:42.96#ibcon#read 5, iclass 15, count 0 2006.257.08:08:42.96#ibcon#about to read 6, iclass 15, count 0 2006.257.08:08:42.96#ibcon#read 6, iclass 15, count 0 2006.257.08:08:42.96#ibcon#end of sib2, iclass 15, count 0 2006.257.08:08:42.96#ibcon#*after write, iclass 15, count 0 2006.257.08:08:42.96#ibcon#*before return 0, iclass 15, count 0 2006.257.08:08:42.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:42.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:42.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:08:42.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:08:42.96$vck44/va=6,4 2006.257.08:08:42.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.08:08:42.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.08:08:42.96#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:42.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:43.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:43.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:43.02#ibcon#enter wrdev, iclass 17, count 2 2006.257.08:08:43.02#ibcon#first serial, iclass 17, count 2 2006.257.08:08:43.02#ibcon#enter sib2, iclass 17, count 2 2006.257.08:08:43.02#ibcon#flushed, iclass 17, count 2 2006.257.08:08:43.02#ibcon#about to write, iclass 17, count 2 2006.257.08:08:43.02#ibcon#wrote, iclass 17, count 2 2006.257.08:08:43.02#ibcon#about to read 3, iclass 17, count 2 2006.257.08:08:43.04#ibcon#read 3, iclass 17, count 2 2006.257.08:08:43.04#ibcon#about to read 4, iclass 17, count 2 2006.257.08:08:43.04#ibcon#read 4, iclass 17, count 2 2006.257.08:08:43.04#ibcon#about to read 5, iclass 17, count 2 2006.257.08:08:43.04#ibcon#read 5, iclass 17, count 2 2006.257.08:08:43.04#ibcon#about to read 6, iclass 17, count 2 2006.257.08:08:43.04#ibcon#read 6, iclass 17, count 2 2006.257.08:08:43.04#ibcon#end of sib2, iclass 17, count 2 2006.257.08:08:43.04#ibcon#*mode == 0, iclass 17, count 2 2006.257.08:08:43.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.08:08:43.04#ibcon#[25=AT06-04\r\n] 2006.257.08:08:43.04#ibcon#*before write, iclass 17, count 2 2006.257.08:08:43.04#ibcon#enter sib2, iclass 17, count 2 2006.257.08:08:43.04#ibcon#flushed, iclass 17, count 2 2006.257.08:08:43.04#ibcon#about to write, iclass 17, count 2 2006.257.08:08:43.04#ibcon#wrote, iclass 17, count 2 2006.257.08:08:43.04#ibcon#about to read 3, iclass 17, count 2 2006.257.08:08:43.07#ibcon#read 3, iclass 17, count 2 2006.257.08:08:43.07#ibcon#about to read 4, iclass 17, count 2 2006.257.08:08:43.07#ibcon#read 4, iclass 17, count 2 2006.257.08:08:43.07#ibcon#about to read 5, iclass 17, count 2 2006.257.08:08:43.07#ibcon#read 5, iclass 17, count 2 2006.257.08:08:43.07#ibcon#about to read 6, iclass 17, count 2 2006.257.08:08:43.07#ibcon#read 6, iclass 17, count 2 2006.257.08:08:43.07#ibcon#end of sib2, iclass 17, count 2 2006.257.08:08:43.07#ibcon#*after write, iclass 17, count 2 2006.257.08:08:43.07#ibcon#*before return 0, iclass 17, count 2 2006.257.08:08:43.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:43.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:43.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.08:08:43.07#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:43.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:43.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:43.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:43.19#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:08:43.19#ibcon#first serial, iclass 17, count 0 2006.257.08:08:43.19#ibcon#enter sib2, iclass 17, count 0 2006.257.08:08:43.19#ibcon#flushed, iclass 17, count 0 2006.257.08:08:43.19#ibcon#about to write, iclass 17, count 0 2006.257.08:08:43.19#ibcon#wrote, iclass 17, count 0 2006.257.08:08:43.19#ibcon#about to read 3, iclass 17, count 0 2006.257.08:08:43.21#ibcon#read 3, iclass 17, count 0 2006.257.08:08:43.21#ibcon#about to read 4, iclass 17, count 0 2006.257.08:08:43.21#ibcon#read 4, iclass 17, count 0 2006.257.08:08:43.21#ibcon#about to read 5, iclass 17, count 0 2006.257.08:08:43.21#ibcon#read 5, iclass 17, count 0 2006.257.08:08:43.21#ibcon#about to read 6, iclass 17, count 0 2006.257.08:08:43.21#ibcon#read 6, iclass 17, count 0 2006.257.08:08:43.21#ibcon#end of sib2, iclass 17, count 0 2006.257.08:08:43.21#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:08:43.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:08:43.21#ibcon#[25=USB\r\n] 2006.257.08:08:43.21#ibcon#*before write, iclass 17, count 0 2006.257.08:08:43.21#ibcon#enter sib2, iclass 17, count 0 2006.257.08:08:43.21#ibcon#flushed, iclass 17, count 0 2006.257.08:08:43.21#ibcon#about to write, iclass 17, count 0 2006.257.08:08:43.21#ibcon#wrote, iclass 17, count 0 2006.257.08:08:43.21#ibcon#about to read 3, iclass 17, count 0 2006.257.08:08:43.24#ibcon#read 3, iclass 17, count 0 2006.257.08:08:43.24#ibcon#about to read 4, iclass 17, count 0 2006.257.08:08:43.24#ibcon#read 4, iclass 17, count 0 2006.257.08:08:43.24#ibcon#about to read 5, iclass 17, count 0 2006.257.08:08:43.24#ibcon#read 5, iclass 17, count 0 2006.257.08:08:43.24#ibcon#about to read 6, iclass 17, count 0 2006.257.08:08:43.24#ibcon#read 6, iclass 17, count 0 2006.257.08:08:43.24#ibcon#end of sib2, iclass 17, count 0 2006.257.08:08:43.24#ibcon#*after write, iclass 17, count 0 2006.257.08:08:43.24#ibcon#*before return 0, iclass 17, count 0 2006.257.08:08:43.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:43.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:43.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:08:43.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:08:43.24$vck44/valo=7,864.99 2006.257.08:08:43.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.08:08:43.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.08:08:43.24#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:43.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:43.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:43.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:43.24#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:08:43.24#ibcon#first serial, iclass 19, count 0 2006.257.08:08:43.24#ibcon#enter sib2, iclass 19, count 0 2006.257.08:08:43.24#ibcon#flushed, iclass 19, count 0 2006.257.08:08:43.24#ibcon#about to write, iclass 19, count 0 2006.257.08:08:43.24#ibcon#wrote, iclass 19, count 0 2006.257.08:08:43.24#ibcon#about to read 3, iclass 19, count 0 2006.257.08:08:43.26#ibcon#read 3, iclass 19, count 0 2006.257.08:08:43.26#ibcon#about to read 4, iclass 19, count 0 2006.257.08:08:43.26#ibcon#read 4, iclass 19, count 0 2006.257.08:08:43.26#ibcon#about to read 5, iclass 19, count 0 2006.257.08:08:43.26#ibcon#read 5, iclass 19, count 0 2006.257.08:08:43.26#ibcon#about to read 6, iclass 19, count 0 2006.257.08:08:43.26#ibcon#read 6, iclass 19, count 0 2006.257.08:08:43.26#ibcon#end of sib2, iclass 19, count 0 2006.257.08:08:43.26#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:08:43.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:08:43.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:08:43.26#ibcon#*before write, iclass 19, count 0 2006.257.08:08:43.26#ibcon#enter sib2, iclass 19, count 0 2006.257.08:08:43.26#ibcon#flushed, iclass 19, count 0 2006.257.08:08:43.26#ibcon#about to write, iclass 19, count 0 2006.257.08:08:43.26#ibcon#wrote, iclass 19, count 0 2006.257.08:08:43.26#ibcon#about to read 3, iclass 19, count 0 2006.257.08:08:43.30#ibcon#read 3, iclass 19, count 0 2006.257.08:08:43.30#ibcon#about to read 4, iclass 19, count 0 2006.257.08:08:43.30#ibcon#read 4, iclass 19, count 0 2006.257.08:08:43.30#ibcon#about to read 5, iclass 19, count 0 2006.257.08:08:43.30#ibcon#read 5, iclass 19, count 0 2006.257.08:08:43.30#ibcon#about to read 6, iclass 19, count 0 2006.257.08:08:43.30#ibcon#read 6, iclass 19, count 0 2006.257.08:08:43.30#ibcon#end of sib2, iclass 19, count 0 2006.257.08:08:43.30#ibcon#*after write, iclass 19, count 0 2006.257.08:08:43.30#ibcon#*before return 0, iclass 19, count 0 2006.257.08:08:43.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:43.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:43.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:08:43.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:08:43.30$vck44/va=7,4 2006.257.08:08:43.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.08:08:43.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.08:08:43.30#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:43.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:43.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:43.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:43.36#ibcon#enter wrdev, iclass 21, count 2 2006.257.08:08:43.36#ibcon#first serial, iclass 21, count 2 2006.257.08:08:43.36#ibcon#enter sib2, iclass 21, count 2 2006.257.08:08:43.36#ibcon#flushed, iclass 21, count 2 2006.257.08:08:43.36#ibcon#about to write, iclass 21, count 2 2006.257.08:08:43.36#ibcon#wrote, iclass 21, count 2 2006.257.08:08:43.36#ibcon#about to read 3, iclass 21, count 2 2006.257.08:08:43.38#ibcon#read 3, iclass 21, count 2 2006.257.08:08:43.38#ibcon#about to read 4, iclass 21, count 2 2006.257.08:08:43.38#ibcon#read 4, iclass 21, count 2 2006.257.08:08:43.38#ibcon#about to read 5, iclass 21, count 2 2006.257.08:08:43.38#ibcon#read 5, iclass 21, count 2 2006.257.08:08:43.38#ibcon#about to read 6, iclass 21, count 2 2006.257.08:08:43.38#ibcon#read 6, iclass 21, count 2 2006.257.08:08:43.38#ibcon#end of sib2, iclass 21, count 2 2006.257.08:08:43.38#ibcon#*mode == 0, iclass 21, count 2 2006.257.08:08:43.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.08:08:43.38#ibcon#[25=AT07-04\r\n] 2006.257.08:08:43.38#ibcon#*before write, iclass 21, count 2 2006.257.08:08:43.38#ibcon#enter sib2, iclass 21, count 2 2006.257.08:08:43.38#ibcon#flushed, iclass 21, count 2 2006.257.08:08:43.38#ibcon#about to write, iclass 21, count 2 2006.257.08:08:43.38#ibcon#wrote, iclass 21, count 2 2006.257.08:08:43.38#ibcon#about to read 3, iclass 21, count 2 2006.257.08:08:43.41#ibcon#read 3, iclass 21, count 2 2006.257.08:08:43.41#ibcon#about to read 4, iclass 21, count 2 2006.257.08:08:43.41#ibcon#read 4, iclass 21, count 2 2006.257.08:08:43.41#ibcon#about to read 5, iclass 21, count 2 2006.257.08:08:43.41#ibcon#read 5, iclass 21, count 2 2006.257.08:08:43.41#ibcon#about to read 6, iclass 21, count 2 2006.257.08:08:43.41#ibcon#read 6, iclass 21, count 2 2006.257.08:08:43.41#ibcon#end of sib2, iclass 21, count 2 2006.257.08:08:43.41#ibcon#*after write, iclass 21, count 2 2006.257.08:08:43.41#ibcon#*before return 0, iclass 21, count 2 2006.257.08:08:43.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:43.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:43.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.08:08:43.41#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:43.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:43.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:43.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:43.53#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:08:43.53#ibcon#first serial, iclass 21, count 0 2006.257.08:08:43.53#ibcon#enter sib2, iclass 21, count 0 2006.257.08:08:43.53#ibcon#flushed, iclass 21, count 0 2006.257.08:08:43.53#ibcon#about to write, iclass 21, count 0 2006.257.08:08:43.53#ibcon#wrote, iclass 21, count 0 2006.257.08:08:43.53#ibcon#about to read 3, iclass 21, count 0 2006.257.08:08:43.55#ibcon#read 3, iclass 21, count 0 2006.257.08:08:43.55#ibcon#about to read 4, iclass 21, count 0 2006.257.08:08:43.55#ibcon#read 4, iclass 21, count 0 2006.257.08:08:43.55#ibcon#about to read 5, iclass 21, count 0 2006.257.08:08:43.55#ibcon#read 5, iclass 21, count 0 2006.257.08:08:43.55#ibcon#about to read 6, iclass 21, count 0 2006.257.08:08:43.55#ibcon#read 6, iclass 21, count 0 2006.257.08:08:43.55#ibcon#end of sib2, iclass 21, count 0 2006.257.08:08:43.55#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:08:43.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:08:43.55#ibcon#[25=USB\r\n] 2006.257.08:08:43.55#ibcon#*before write, iclass 21, count 0 2006.257.08:08:43.55#ibcon#enter sib2, iclass 21, count 0 2006.257.08:08:43.55#ibcon#flushed, iclass 21, count 0 2006.257.08:08:43.55#ibcon#about to write, iclass 21, count 0 2006.257.08:08:43.55#ibcon#wrote, iclass 21, count 0 2006.257.08:08:43.55#ibcon#about to read 3, iclass 21, count 0 2006.257.08:08:43.58#ibcon#read 3, iclass 21, count 0 2006.257.08:08:43.58#ibcon#about to read 4, iclass 21, count 0 2006.257.08:08:43.58#ibcon#read 4, iclass 21, count 0 2006.257.08:08:43.58#ibcon#about to read 5, iclass 21, count 0 2006.257.08:08:43.58#ibcon#read 5, iclass 21, count 0 2006.257.08:08:43.58#ibcon#about to read 6, iclass 21, count 0 2006.257.08:08:43.58#ibcon#read 6, iclass 21, count 0 2006.257.08:08:43.58#ibcon#end of sib2, iclass 21, count 0 2006.257.08:08:43.58#ibcon#*after write, iclass 21, count 0 2006.257.08:08:43.58#ibcon#*before return 0, iclass 21, count 0 2006.257.08:08:43.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:43.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:43.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:08:43.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:08:43.58$vck44/valo=8,884.99 2006.257.08:08:43.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.08:08:43.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.08:08:43.58#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:43.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:43.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:43.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:43.58#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:08:43.58#ibcon#first serial, iclass 23, count 0 2006.257.08:08:43.58#ibcon#enter sib2, iclass 23, count 0 2006.257.08:08:43.58#ibcon#flushed, iclass 23, count 0 2006.257.08:08:43.58#ibcon#about to write, iclass 23, count 0 2006.257.08:08:43.58#ibcon#wrote, iclass 23, count 0 2006.257.08:08:43.58#ibcon#about to read 3, iclass 23, count 0 2006.257.08:08:43.60#ibcon#read 3, iclass 23, count 0 2006.257.08:08:43.60#ibcon#about to read 4, iclass 23, count 0 2006.257.08:08:43.60#ibcon#read 4, iclass 23, count 0 2006.257.08:08:43.60#ibcon#about to read 5, iclass 23, count 0 2006.257.08:08:43.60#ibcon#read 5, iclass 23, count 0 2006.257.08:08:43.60#ibcon#about to read 6, iclass 23, count 0 2006.257.08:08:43.60#ibcon#read 6, iclass 23, count 0 2006.257.08:08:43.60#ibcon#end of sib2, iclass 23, count 0 2006.257.08:08:43.60#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:08:43.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:08:43.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:08:43.60#ibcon#*before write, iclass 23, count 0 2006.257.08:08:43.60#ibcon#enter sib2, iclass 23, count 0 2006.257.08:08:43.60#ibcon#flushed, iclass 23, count 0 2006.257.08:08:43.60#ibcon#about to write, iclass 23, count 0 2006.257.08:08:43.60#ibcon#wrote, iclass 23, count 0 2006.257.08:08:43.60#ibcon#about to read 3, iclass 23, count 0 2006.257.08:08:43.64#ibcon#read 3, iclass 23, count 0 2006.257.08:08:43.64#ibcon#about to read 4, iclass 23, count 0 2006.257.08:08:43.64#ibcon#read 4, iclass 23, count 0 2006.257.08:08:43.64#ibcon#about to read 5, iclass 23, count 0 2006.257.08:08:43.64#ibcon#read 5, iclass 23, count 0 2006.257.08:08:43.64#ibcon#about to read 6, iclass 23, count 0 2006.257.08:08:43.64#ibcon#read 6, iclass 23, count 0 2006.257.08:08:43.64#ibcon#end of sib2, iclass 23, count 0 2006.257.08:08:43.64#ibcon#*after write, iclass 23, count 0 2006.257.08:08:43.64#ibcon#*before return 0, iclass 23, count 0 2006.257.08:08:43.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:43.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:43.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:08:43.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:08:43.64$vck44/va=8,4 2006.257.08:08:43.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.08:08:43.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.08:08:43.64#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:43.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:43.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:43.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:43.70#ibcon#enter wrdev, iclass 25, count 2 2006.257.08:08:43.70#ibcon#first serial, iclass 25, count 2 2006.257.08:08:43.70#ibcon#enter sib2, iclass 25, count 2 2006.257.08:08:43.70#ibcon#flushed, iclass 25, count 2 2006.257.08:08:43.70#ibcon#about to write, iclass 25, count 2 2006.257.08:08:43.70#ibcon#wrote, iclass 25, count 2 2006.257.08:08:43.70#ibcon#about to read 3, iclass 25, count 2 2006.257.08:08:43.72#ibcon#read 3, iclass 25, count 2 2006.257.08:08:43.72#ibcon#about to read 4, iclass 25, count 2 2006.257.08:08:43.72#ibcon#read 4, iclass 25, count 2 2006.257.08:08:43.72#ibcon#about to read 5, iclass 25, count 2 2006.257.08:08:43.72#ibcon#read 5, iclass 25, count 2 2006.257.08:08:43.72#ibcon#about to read 6, iclass 25, count 2 2006.257.08:08:43.72#ibcon#read 6, iclass 25, count 2 2006.257.08:08:43.72#ibcon#end of sib2, iclass 25, count 2 2006.257.08:08:43.72#ibcon#*mode == 0, iclass 25, count 2 2006.257.08:08:43.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.08:08:43.72#ibcon#[25=AT08-04\r\n] 2006.257.08:08:43.72#ibcon#*before write, iclass 25, count 2 2006.257.08:08:43.72#ibcon#enter sib2, iclass 25, count 2 2006.257.08:08:43.72#ibcon#flushed, iclass 25, count 2 2006.257.08:08:43.72#ibcon#about to write, iclass 25, count 2 2006.257.08:08:43.72#ibcon#wrote, iclass 25, count 2 2006.257.08:08:43.72#ibcon#about to read 3, iclass 25, count 2 2006.257.08:08:43.73#abcon#<5=/16 1.4 6.2 20.87 871012.9\r\n> 2006.257.08:08:43.75#abcon#{5=INTERFACE CLEAR} 2006.257.08:08:43.75#ibcon#read 3, iclass 25, count 2 2006.257.08:08:43.75#ibcon#about to read 4, iclass 25, count 2 2006.257.08:08:43.75#ibcon#read 4, iclass 25, count 2 2006.257.08:08:43.75#ibcon#about to read 5, iclass 25, count 2 2006.257.08:08:43.75#ibcon#read 5, iclass 25, count 2 2006.257.08:08:43.75#ibcon#about to read 6, iclass 25, count 2 2006.257.08:08:43.75#ibcon#read 6, iclass 25, count 2 2006.257.08:08:43.75#ibcon#end of sib2, iclass 25, count 2 2006.257.08:08:43.75#ibcon#*after write, iclass 25, count 2 2006.257.08:08:43.75#ibcon#*before return 0, iclass 25, count 2 2006.257.08:08:43.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:43.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:43.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.08:08:43.75#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:43.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:43.81#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:08:43.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:43.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:43.87#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:08:43.87#ibcon#first serial, iclass 25, count 0 2006.257.08:08:43.87#ibcon#enter sib2, iclass 25, count 0 2006.257.08:08:43.87#ibcon#flushed, iclass 25, count 0 2006.257.08:08:43.87#ibcon#about to write, iclass 25, count 0 2006.257.08:08:43.87#ibcon#wrote, iclass 25, count 0 2006.257.08:08:43.87#ibcon#about to read 3, iclass 25, count 0 2006.257.08:08:43.89#ibcon#read 3, iclass 25, count 0 2006.257.08:08:43.89#ibcon#about to read 4, iclass 25, count 0 2006.257.08:08:43.89#ibcon#read 4, iclass 25, count 0 2006.257.08:08:43.89#ibcon#about to read 5, iclass 25, count 0 2006.257.08:08:43.89#ibcon#read 5, iclass 25, count 0 2006.257.08:08:43.89#ibcon#about to read 6, iclass 25, count 0 2006.257.08:08:43.89#ibcon#read 6, iclass 25, count 0 2006.257.08:08:43.89#ibcon#end of sib2, iclass 25, count 0 2006.257.08:08:43.89#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:08:43.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:08:43.89#ibcon#[25=USB\r\n] 2006.257.08:08:43.89#ibcon#*before write, iclass 25, count 0 2006.257.08:08:43.89#ibcon#enter sib2, iclass 25, count 0 2006.257.08:08:43.89#ibcon#flushed, iclass 25, count 0 2006.257.08:08:43.89#ibcon#about to write, iclass 25, count 0 2006.257.08:08:43.89#ibcon#wrote, iclass 25, count 0 2006.257.08:08:43.89#ibcon#about to read 3, iclass 25, count 0 2006.257.08:08:43.92#ibcon#read 3, iclass 25, count 0 2006.257.08:08:43.92#ibcon#about to read 4, iclass 25, count 0 2006.257.08:08:43.92#ibcon#read 4, iclass 25, count 0 2006.257.08:08:43.92#ibcon#about to read 5, iclass 25, count 0 2006.257.08:08:43.92#ibcon#read 5, iclass 25, count 0 2006.257.08:08:43.92#ibcon#about to read 6, iclass 25, count 0 2006.257.08:08:43.92#ibcon#read 6, iclass 25, count 0 2006.257.08:08:43.92#ibcon#end of sib2, iclass 25, count 0 2006.257.08:08:43.92#ibcon#*after write, iclass 25, count 0 2006.257.08:08:43.92#ibcon#*before return 0, iclass 25, count 0 2006.257.08:08:43.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:43.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:43.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:08:43.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:08:43.92$vck44/vblo=1,629.99 2006.257.08:08:43.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.08:08:43.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.08:08:43.92#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:43.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:43.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:43.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:43.92#ibcon#enter wrdev, iclass 31, count 0 2006.257.08:08:43.92#ibcon#first serial, iclass 31, count 0 2006.257.08:08:43.92#ibcon#enter sib2, iclass 31, count 0 2006.257.08:08:43.92#ibcon#flushed, iclass 31, count 0 2006.257.08:08:43.92#ibcon#about to write, iclass 31, count 0 2006.257.08:08:43.92#ibcon#wrote, iclass 31, count 0 2006.257.08:08:43.92#ibcon#about to read 3, iclass 31, count 0 2006.257.08:08:43.94#ibcon#read 3, iclass 31, count 0 2006.257.08:08:43.94#ibcon#about to read 4, iclass 31, count 0 2006.257.08:08:43.94#ibcon#read 4, iclass 31, count 0 2006.257.08:08:43.94#ibcon#about to read 5, iclass 31, count 0 2006.257.08:08:43.94#ibcon#read 5, iclass 31, count 0 2006.257.08:08:43.94#ibcon#about to read 6, iclass 31, count 0 2006.257.08:08:43.94#ibcon#read 6, iclass 31, count 0 2006.257.08:08:43.94#ibcon#end of sib2, iclass 31, count 0 2006.257.08:08:43.94#ibcon#*mode == 0, iclass 31, count 0 2006.257.08:08:43.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.08:08:43.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:08:43.94#ibcon#*before write, iclass 31, count 0 2006.257.08:08:43.94#ibcon#enter sib2, iclass 31, count 0 2006.257.08:08:43.94#ibcon#flushed, iclass 31, count 0 2006.257.08:08:43.94#ibcon#about to write, iclass 31, count 0 2006.257.08:08:43.94#ibcon#wrote, iclass 31, count 0 2006.257.08:08:43.94#ibcon#about to read 3, iclass 31, count 0 2006.257.08:08:43.98#ibcon#read 3, iclass 31, count 0 2006.257.08:08:43.98#ibcon#about to read 4, iclass 31, count 0 2006.257.08:08:43.98#ibcon#read 4, iclass 31, count 0 2006.257.08:08:43.98#ibcon#about to read 5, iclass 31, count 0 2006.257.08:08:43.98#ibcon#read 5, iclass 31, count 0 2006.257.08:08:43.98#ibcon#about to read 6, iclass 31, count 0 2006.257.08:08:43.98#ibcon#read 6, iclass 31, count 0 2006.257.08:08:43.98#ibcon#end of sib2, iclass 31, count 0 2006.257.08:08:43.98#ibcon#*after write, iclass 31, count 0 2006.257.08:08:43.98#ibcon#*before return 0, iclass 31, count 0 2006.257.08:08:43.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:43.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:08:43.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.08:08:43.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.08:08:43.98$vck44/vb=1,4 2006.257.08:08:43.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.08:08:43.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.08:08:43.98#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:43.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:43.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:43.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:43.98#ibcon#enter wrdev, iclass 33, count 2 2006.257.08:08:43.98#ibcon#first serial, iclass 33, count 2 2006.257.08:08:43.98#ibcon#enter sib2, iclass 33, count 2 2006.257.08:08:43.98#ibcon#flushed, iclass 33, count 2 2006.257.08:08:43.98#ibcon#about to write, iclass 33, count 2 2006.257.08:08:43.98#ibcon#wrote, iclass 33, count 2 2006.257.08:08:43.98#ibcon#about to read 3, iclass 33, count 2 2006.257.08:08:44.00#ibcon#read 3, iclass 33, count 2 2006.257.08:08:44.00#ibcon#about to read 4, iclass 33, count 2 2006.257.08:08:44.00#ibcon#read 4, iclass 33, count 2 2006.257.08:08:44.00#ibcon#about to read 5, iclass 33, count 2 2006.257.08:08:44.00#ibcon#read 5, iclass 33, count 2 2006.257.08:08:44.00#ibcon#about to read 6, iclass 33, count 2 2006.257.08:08:44.00#ibcon#read 6, iclass 33, count 2 2006.257.08:08:44.00#ibcon#end of sib2, iclass 33, count 2 2006.257.08:08:44.00#ibcon#*mode == 0, iclass 33, count 2 2006.257.08:08:44.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.08:08:44.00#ibcon#[27=AT01-04\r\n] 2006.257.08:08:44.00#ibcon#*before write, iclass 33, count 2 2006.257.08:08:44.00#ibcon#enter sib2, iclass 33, count 2 2006.257.08:08:44.00#ibcon#flushed, iclass 33, count 2 2006.257.08:08:44.00#ibcon#about to write, iclass 33, count 2 2006.257.08:08:44.00#ibcon#wrote, iclass 33, count 2 2006.257.08:08:44.00#ibcon#about to read 3, iclass 33, count 2 2006.257.08:08:44.03#ibcon#read 3, iclass 33, count 2 2006.257.08:08:44.03#ibcon#about to read 4, iclass 33, count 2 2006.257.08:08:44.03#ibcon#read 4, iclass 33, count 2 2006.257.08:08:44.03#ibcon#about to read 5, iclass 33, count 2 2006.257.08:08:44.03#ibcon#read 5, iclass 33, count 2 2006.257.08:08:44.03#ibcon#about to read 6, iclass 33, count 2 2006.257.08:08:44.03#ibcon#read 6, iclass 33, count 2 2006.257.08:08:44.03#ibcon#end of sib2, iclass 33, count 2 2006.257.08:08:44.03#ibcon#*after write, iclass 33, count 2 2006.257.08:08:44.03#ibcon#*before return 0, iclass 33, count 2 2006.257.08:08:44.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:44.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:08:44.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.08:08:44.03#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:44.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:44.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:44.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:44.15#ibcon#enter wrdev, iclass 33, count 0 2006.257.08:08:44.15#ibcon#first serial, iclass 33, count 0 2006.257.08:08:44.15#ibcon#enter sib2, iclass 33, count 0 2006.257.08:08:44.15#ibcon#flushed, iclass 33, count 0 2006.257.08:08:44.15#ibcon#about to write, iclass 33, count 0 2006.257.08:08:44.15#ibcon#wrote, iclass 33, count 0 2006.257.08:08:44.15#ibcon#about to read 3, iclass 33, count 0 2006.257.08:08:44.17#ibcon#read 3, iclass 33, count 0 2006.257.08:08:44.17#ibcon#about to read 4, iclass 33, count 0 2006.257.08:08:44.17#ibcon#read 4, iclass 33, count 0 2006.257.08:08:44.17#ibcon#about to read 5, iclass 33, count 0 2006.257.08:08:44.17#ibcon#read 5, iclass 33, count 0 2006.257.08:08:44.17#ibcon#about to read 6, iclass 33, count 0 2006.257.08:08:44.17#ibcon#read 6, iclass 33, count 0 2006.257.08:08:44.17#ibcon#end of sib2, iclass 33, count 0 2006.257.08:08:44.17#ibcon#*mode == 0, iclass 33, count 0 2006.257.08:08:44.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.08:08:44.17#ibcon#[27=USB\r\n] 2006.257.08:08:44.17#ibcon#*before write, iclass 33, count 0 2006.257.08:08:44.17#ibcon#enter sib2, iclass 33, count 0 2006.257.08:08:44.17#ibcon#flushed, iclass 33, count 0 2006.257.08:08:44.17#ibcon#about to write, iclass 33, count 0 2006.257.08:08:44.17#ibcon#wrote, iclass 33, count 0 2006.257.08:08:44.17#ibcon#about to read 3, iclass 33, count 0 2006.257.08:08:44.20#ibcon#read 3, iclass 33, count 0 2006.257.08:08:44.20#ibcon#about to read 4, iclass 33, count 0 2006.257.08:08:44.20#ibcon#read 4, iclass 33, count 0 2006.257.08:08:44.20#ibcon#about to read 5, iclass 33, count 0 2006.257.08:08:44.20#ibcon#read 5, iclass 33, count 0 2006.257.08:08:44.20#ibcon#about to read 6, iclass 33, count 0 2006.257.08:08:44.20#ibcon#read 6, iclass 33, count 0 2006.257.08:08:44.20#ibcon#end of sib2, iclass 33, count 0 2006.257.08:08:44.20#ibcon#*after write, iclass 33, count 0 2006.257.08:08:44.20#ibcon#*before return 0, iclass 33, count 0 2006.257.08:08:44.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:44.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:08:44.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.08:08:44.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.08:08:44.20$vck44/vblo=2,634.99 2006.257.08:08:44.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.08:08:44.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.08:08:44.20#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:44.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:44.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:44.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:44.20#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:08:44.20#ibcon#first serial, iclass 35, count 0 2006.257.08:08:44.20#ibcon#enter sib2, iclass 35, count 0 2006.257.08:08:44.20#ibcon#flushed, iclass 35, count 0 2006.257.08:08:44.20#ibcon#about to write, iclass 35, count 0 2006.257.08:08:44.20#ibcon#wrote, iclass 35, count 0 2006.257.08:08:44.20#ibcon#about to read 3, iclass 35, count 0 2006.257.08:08:44.22#ibcon#read 3, iclass 35, count 0 2006.257.08:08:44.22#ibcon#about to read 4, iclass 35, count 0 2006.257.08:08:44.22#ibcon#read 4, iclass 35, count 0 2006.257.08:08:44.22#ibcon#about to read 5, iclass 35, count 0 2006.257.08:08:44.22#ibcon#read 5, iclass 35, count 0 2006.257.08:08:44.22#ibcon#about to read 6, iclass 35, count 0 2006.257.08:08:44.22#ibcon#read 6, iclass 35, count 0 2006.257.08:08:44.22#ibcon#end of sib2, iclass 35, count 0 2006.257.08:08:44.22#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:08:44.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:08:44.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:08:44.22#ibcon#*before write, iclass 35, count 0 2006.257.08:08:44.22#ibcon#enter sib2, iclass 35, count 0 2006.257.08:08:44.22#ibcon#flushed, iclass 35, count 0 2006.257.08:08:44.22#ibcon#about to write, iclass 35, count 0 2006.257.08:08:44.22#ibcon#wrote, iclass 35, count 0 2006.257.08:08:44.22#ibcon#about to read 3, iclass 35, count 0 2006.257.08:08:44.26#ibcon#read 3, iclass 35, count 0 2006.257.08:08:44.26#ibcon#about to read 4, iclass 35, count 0 2006.257.08:08:44.26#ibcon#read 4, iclass 35, count 0 2006.257.08:08:44.26#ibcon#about to read 5, iclass 35, count 0 2006.257.08:08:44.26#ibcon#read 5, iclass 35, count 0 2006.257.08:08:44.26#ibcon#about to read 6, iclass 35, count 0 2006.257.08:08:44.26#ibcon#read 6, iclass 35, count 0 2006.257.08:08:44.26#ibcon#end of sib2, iclass 35, count 0 2006.257.08:08:44.26#ibcon#*after write, iclass 35, count 0 2006.257.08:08:44.26#ibcon#*before return 0, iclass 35, count 0 2006.257.08:08:44.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:44.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:08:44.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:08:44.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:08:44.26$vck44/vb=2,5 2006.257.08:08:44.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.08:08:44.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.08:08:44.26#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:44.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:44.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:44.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:44.32#ibcon#enter wrdev, iclass 37, count 2 2006.257.08:08:44.32#ibcon#first serial, iclass 37, count 2 2006.257.08:08:44.32#ibcon#enter sib2, iclass 37, count 2 2006.257.08:08:44.32#ibcon#flushed, iclass 37, count 2 2006.257.08:08:44.32#ibcon#about to write, iclass 37, count 2 2006.257.08:08:44.32#ibcon#wrote, iclass 37, count 2 2006.257.08:08:44.32#ibcon#about to read 3, iclass 37, count 2 2006.257.08:08:44.34#ibcon#read 3, iclass 37, count 2 2006.257.08:08:44.34#ibcon#about to read 4, iclass 37, count 2 2006.257.08:08:44.34#ibcon#read 4, iclass 37, count 2 2006.257.08:08:44.34#ibcon#about to read 5, iclass 37, count 2 2006.257.08:08:44.34#ibcon#read 5, iclass 37, count 2 2006.257.08:08:44.34#ibcon#about to read 6, iclass 37, count 2 2006.257.08:08:44.34#ibcon#read 6, iclass 37, count 2 2006.257.08:08:44.34#ibcon#end of sib2, iclass 37, count 2 2006.257.08:08:44.34#ibcon#*mode == 0, iclass 37, count 2 2006.257.08:08:44.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.08:08:44.34#ibcon#[27=AT02-05\r\n] 2006.257.08:08:44.34#ibcon#*before write, iclass 37, count 2 2006.257.08:08:44.34#ibcon#enter sib2, iclass 37, count 2 2006.257.08:08:44.34#ibcon#flushed, iclass 37, count 2 2006.257.08:08:44.34#ibcon#about to write, iclass 37, count 2 2006.257.08:08:44.34#ibcon#wrote, iclass 37, count 2 2006.257.08:08:44.34#ibcon#about to read 3, iclass 37, count 2 2006.257.08:08:44.37#ibcon#read 3, iclass 37, count 2 2006.257.08:08:44.37#ibcon#about to read 4, iclass 37, count 2 2006.257.08:08:44.37#ibcon#read 4, iclass 37, count 2 2006.257.08:08:44.37#ibcon#about to read 5, iclass 37, count 2 2006.257.08:08:44.37#ibcon#read 5, iclass 37, count 2 2006.257.08:08:44.37#ibcon#about to read 6, iclass 37, count 2 2006.257.08:08:44.37#ibcon#read 6, iclass 37, count 2 2006.257.08:08:44.37#ibcon#end of sib2, iclass 37, count 2 2006.257.08:08:44.37#ibcon#*after write, iclass 37, count 2 2006.257.08:08:44.37#ibcon#*before return 0, iclass 37, count 2 2006.257.08:08:44.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:44.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:08:44.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.08:08:44.37#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:44.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:44.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:44.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:44.49#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:08:44.49#ibcon#first serial, iclass 37, count 0 2006.257.08:08:44.49#ibcon#enter sib2, iclass 37, count 0 2006.257.08:08:44.49#ibcon#flushed, iclass 37, count 0 2006.257.08:08:44.49#ibcon#about to write, iclass 37, count 0 2006.257.08:08:44.49#ibcon#wrote, iclass 37, count 0 2006.257.08:08:44.49#ibcon#about to read 3, iclass 37, count 0 2006.257.08:08:44.51#ibcon#read 3, iclass 37, count 0 2006.257.08:08:44.51#ibcon#about to read 4, iclass 37, count 0 2006.257.08:08:44.51#ibcon#read 4, iclass 37, count 0 2006.257.08:08:44.51#ibcon#about to read 5, iclass 37, count 0 2006.257.08:08:44.51#ibcon#read 5, iclass 37, count 0 2006.257.08:08:44.51#ibcon#about to read 6, iclass 37, count 0 2006.257.08:08:44.51#ibcon#read 6, iclass 37, count 0 2006.257.08:08:44.51#ibcon#end of sib2, iclass 37, count 0 2006.257.08:08:44.51#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:08:44.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:08:44.51#ibcon#[27=USB\r\n] 2006.257.08:08:44.51#ibcon#*before write, iclass 37, count 0 2006.257.08:08:44.51#ibcon#enter sib2, iclass 37, count 0 2006.257.08:08:44.52#ibcon#flushed, iclass 37, count 0 2006.257.08:08:44.52#ibcon#about to write, iclass 37, count 0 2006.257.08:08:44.52#ibcon#wrote, iclass 37, count 0 2006.257.08:08:44.52#ibcon#about to read 3, iclass 37, count 0 2006.257.08:08:44.55#ibcon#read 3, iclass 37, count 0 2006.257.08:08:44.55#ibcon#about to read 4, iclass 37, count 0 2006.257.08:08:44.55#ibcon#read 4, iclass 37, count 0 2006.257.08:08:44.55#ibcon#about to read 5, iclass 37, count 0 2006.257.08:08:44.55#ibcon#read 5, iclass 37, count 0 2006.257.08:08:44.55#ibcon#about to read 6, iclass 37, count 0 2006.257.08:08:44.55#ibcon#read 6, iclass 37, count 0 2006.257.08:08:44.55#ibcon#end of sib2, iclass 37, count 0 2006.257.08:08:44.55#ibcon#*after write, iclass 37, count 0 2006.257.08:08:44.55#ibcon#*before return 0, iclass 37, count 0 2006.257.08:08:44.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:44.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:08:44.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:08:44.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:08:44.55$vck44/vblo=3,649.99 2006.257.08:08:44.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.08:08:44.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.08:08:44.55#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:44.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:44.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:44.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:44.55#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:08:44.55#ibcon#first serial, iclass 39, count 0 2006.257.08:08:44.55#ibcon#enter sib2, iclass 39, count 0 2006.257.08:08:44.55#ibcon#flushed, iclass 39, count 0 2006.257.08:08:44.55#ibcon#about to write, iclass 39, count 0 2006.257.08:08:44.55#ibcon#wrote, iclass 39, count 0 2006.257.08:08:44.55#ibcon#about to read 3, iclass 39, count 0 2006.257.08:08:44.57#ibcon#read 3, iclass 39, count 0 2006.257.08:08:44.57#ibcon#about to read 4, iclass 39, count 0 2006.257.08:08:44.57#ibcon#read 4, iclass 39, count 0 2006.257.08:08:44.57#ibcon#about to read 5, iclass 39, count 0 2006.257.08:08:44.57#ibcon#read 5, iclass 39, count 0 2006.257.08:08:44.57#ibcon#about to read 6, iclass 39, count 0 2006.257.08:08:44.57#ibcon#read 6, iclass 39, count 0 2006.257.08:08:44.57#ibcon#end of sib2, iclass 39, count 0 2006.257.08:08:44.57#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:08:44.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:08:44.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:08:44.57#ibcon#*before write, iclass 39, count 0 2006.257.08:08:44.57#ibcon#enter sib2, iclass 39, count 0 2006.257.08:08:44.57#ibcon#flushed, iclass 39, count 0 2006.257.08:08:44.57#ibcon#about to write, iclass 39, count 0 2006.257.08:08:44.57#ibcon#wrote, iclass 39, count 0 2006.257.08:08:44.57#ibcon#about to read 3, iclass 39, count 0 2006.257.08:08:44.61#ibcon#read 3, iclass 39, count 0 2006.257.08:08:44.61#ibcon#about to read 4, iclass 39, count 0 2006.257.08:08:44.61#ibcon#read 4, iclass 39, count 0 2006.257.08:08:44.61#ibcon#about to read 5, iclass 39, count 0 2006.257.08:08:44.61#ibcon#read 5, iclass 39, count 0 2006.257.08:08:44.61#ibcon#about to read 6, iclass 39, count 0 2006.257.08:08:44.61#ibcon#read 6, iclass 39, count 0 2006.257.08:08:44.61#ibcon#end of sib2, iclass 39, count 0 2006.257.08:08:44.61#ibcon#*after write, iclass 39, count 0 2006.257.08:08:44.61#ibcon#*before return 0, iclass 39, count 0 2006.257.08:08:44.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:44.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:08:44.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:08:44.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:08:44.61$vck44/vb=3,4 2006.257.08:08:44.61#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.08:08:44.61#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.08:08:44.61#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:44.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:44.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:44.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:44.67#ibcon#enter wrdev, iclass 3, count 2 2006.257.08:08:44.67#ibcon#first serial, iclass 3, count 2 2006.257.08:08:44.67#ibcon#enter sib2, iclass 3, count 2 2006.257.08:08:44.67#ibcon#flushed, iclass 3, count 2 2006.257.08:08:44.67#ibcon#about to write, iclass 3, count 2 2006.257.08:08:44.67#ibcon#wrote, iclass 3, count 2 2006.257.08:08:44.67#ibcon#about to read 3, iclass 3, count 2 2006.257.08:08:44.69#ibcon#read 3, iclass 3, count 2 2006.257.08:08:44.69#ibcon#about to read 4, iclass 3, count 2 2006.257.08:08:44.69#ibcon#read 4, iclass 3, count 2 2006.257.08:08:44.69#ibcon#about to read 5, iclass 3, count 2 2006.257.08:08:44.69#ibcon#read 5, iclass 3, count 2 2006.257.08:08:44.69#ibcon#about to read 6, iclass 3, count 2 2006.257.08:08:44.69#ibcon#read 6, iclass 3, count 2 2006.257.08:08:44.69#ibcon#end of sib2, iclass 3, count 2 2006.257.08:08:44.69#ibcon#*mode == 0, iclass 3, count 2 2006.257.08:08:44.69#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.08:08:44.69#ibcon#[27=AT03-04\r\n] 2006.257.08:08:44.69#ibcon#*before write, iclass 3, count 2 2006.257.08:08:44.69#ibcon#enter sib2, iclass 3, count 2 2006.257.08:08:44.69#ibcon#flushed, iclass 3, count 2 2006.257.08:08:44.69#ibcon#about to write, iclass 3, count 2 2006.257.08:08:44.69#ibcon#wrote, iclass 3, count 2 2006.257.08:08:44.69#ibcon#about to read 3, iclass 3, count 2 2006.257.08:08:44.72#ibcon#read 3, iclass 3, count 2 2006.257.08:08:44.72#ibcon#about to read 4, iclass 3, count 2 2006.257.08:08:44.72#ibcon#read 4, iclass 3, count 2 2006.257.08:08:44.72#ibcon#about to read 5, iclass 3, count 2 2006.257.08:08:44.72#ibcon#read 5, iclass 3, count 2 2006.257.08:08:44.72#ibcon#about to read 6, iclass 3, count 2 2006.257.08:08:44.72#ibcon#read 6, iclass 3, count 2 2006.257.08:08:44.72#ibcon#end of sib2, iclass 3, count 2 2006.257.08:08:44.72#ibcon#*after write, iclass 3, count 2 2006.257.08:08:44.72#ibcon#*before return 0, iclass 3, count 2 2006.257.08:08:44.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:44.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:08:44.72#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.08:08:44.72#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:44.72#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:44.84#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:44.84#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:44.84#ibcon#enter wrdev, iclass 3, count 0 2006.257.08:08:44.84#ibcon#first serial, iclass 3, count 0 2006.257.08:08:44.84#ibcon#enter sib2, iclass 3, count 0 2006.257.08:08:44.84#ibcon#flushed, iclass 3, count 0 2006.257.08:08:44.84#ibcon#about to write, iclass 3, count 0 2006.257.08:08:44.84#ibcon#wrote, iclass 3, count 0 2006.257.08:08:44.84#ibcon#about to read 3, iclass 3, count 0 2006.257.08:08:44.86#ibcon#read 3, iclass 3, count 0 2006.257.08:08:44.86#ibcon#about to read 4, iclass 3, count 0 2006.257.08:08:44.86#ibcon#read 4, iclass 3, count 0 2006.257.08:08:44.86#ibcon#about to read 5, iclass 3, count 0 2006.257.08:08:44.86#ibcon#read 5, iclass 3, count 0 2006.257.08:08:44.86#ibcon#about to read 6, iclass 3, count 0 2006.257.08:08:44.86#ibcon#read 6, iclass 3, count 0 2006.257.08:08:44.86#ibcon#end of sib2, iclass 3, count 0 2006.257.08:08:44.86#ibcon#*mode == 0, iclass 3, count 0 2006.257.08:08:44.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.08:08:44.86#ibcon#[27=USB\r\n] 2006.257.08:08:44.86#ibcon#*before write, iclass 3, count 0 2006.257.08:08:44.86#ibcon#enter sib2, iclass 3, count 0 2006.257.08:08:44.86#ibcon#flushed, iclass 3, count 0 2006.257.08:08:44.86#ibcon#about to write, iclass 3, count 0 2006.257.08:08:44.86#ibcon#wrote, iclass 3, count 0 2006.257.08:08:44.86#ibcon#about to read 3, iclass 3, count 0 2006.257.08:08:44.89#ibcon#read 3, iclass 3, count 0 2006.257.08:08:44.89#ibcon#about to read 4, iclass 3, count 0 2006.257.08:08:44.89#ibcon#read 4, iclass 3, count 0 2006.257.08:08:44.89#ibcon#about to read 5, iclass 3, count 0 2006.257.08:08:44.89#ibcon#read 5, iclass 3, count 0 2006.257.08:08:44.89#ibcon#about to read 6, iclass 3, count 0 2006.257.08:08:44.89#ibcon#read 6, iclass 3, count 0 2006.257.08:08:44.89#ibcon#end of sib2, iclass 3, count 0 2006.257.08:08:44.89#ibcon#*after write, iclass 3, count 0 2006.257.08:08:44.89#ibcon#*before return 0, iclass 3, count 0 2006.257.08:08:44.89#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:44.89#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:08:44.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.08:08:44.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.08:08:44.89$vck44/vblo=4,679.99 2006.257.08:08:44.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.08:08:44.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.08:08:44.89#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:44.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:44.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:44.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:44.89#ibcon#enter wrdev, iclass 5, count 0 2006.257.08:08:44.89#ibcon#first serial, iclass 5, count 0 2006.257.08:08:44.89#ibcon#enter sib2, iclass 5, count 0 2006.257.08:08:44.89#ibcon#flushed, iclass 5, count 0 2006.257.08:08:44.89#ibcon#about to write, iclass 5, count 0 2006.257.08:08:44.89#ibcon#wrote, iclass 5, count 0 2006.257.08:08:44.89#ibcon#about to read 3, iclass 5, count 0 2006.257.08:08:44.91#ibcon#read 3, iclass 5, count 0 2006.257.08:08:44.91#ibcon#about to read 4, iclass 5, count 0 2006.257.08:08:44.91#ibcon#read 4, iclass 5, count 0 2006.257.08:08:44.91#ibcon#about to read 5, iclass 5, count 0 2006.257.08:08:44.91#ibcon#read 5, iclass 5, count 0 2006.257.08:08:44.91#ibcon#about to read 6, iclass 5, count 0 2006.257.08:08:44.91#ibcon#read 6, iclass 5, count 0 2006.257.08:08:44.91#ibcon#end of sib2, iclass 5, count 0 2006.257.08:08:44.91#ibcon#*mode == 0, iclass 5, count 0 2006.257.08:08:44.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.08:08:44.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:08:44.91#ibcon#*before write, iclass 5, count 0 2006.257.08:08:44.91#ibcon#enter sib2, iclass 5, count 0 2006.257.08:08:44.91#ibcon#flushed, iclass 5, count 0 2006.257.08:08:44.91#ibcon#about to write, iclass 5, count 0 2006.257.08:08:44.91#ibcon#wrote, iclass 5, count 0 2006.257.08:08:44.91#ibcon#about to read 3, iclass 5, count 0 2006.257.08:08:44.95#ibcon#read 3, iclass 5, count 0 2006.257.08:08:44.95#ibcon#about to read 4, iclass 5, count 0 2006.257.08:08:44.95#ibcon#read 4, iclass 5, count 0 2006.257.08:08:44.95#ibcon#about to read 5, iclass 5, count 0 2006.257.08:08:44.95#ibcon#read 5, iclass 5, count 0 2006.257.08:08:44.95#ibcon#about to read 6, iclass 5, count 0 2006.257.08:08:44.95#ibcon#read 6, iclass 5, count 0 2006.257.08:08:44.95#ibcon#end of sib2, iclass 5, count 0 2006.257.08:08:44.95#ibcon#*after write, iclass 5, count 0 2006.257.08:08:44.95#ibcon#*before return 0, iclass 5, count 0 2006.257.08:08:44.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:44.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:08:44.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.08:08:44.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.08:08:44.95$vck44/vb=4,5 2006.257.08:08:44.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.08:08:44.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.08:08:44.95#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:44.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:45.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:45.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:45.01#ibcon#enter wrdev, iclass 7, count 2 2006.257.08:08:45.01#ibcon#first serial, iclass 7, count 2 2006.257.08:08:45.01#ibcon#enter sib2, iclass 7, count 2 2006.257.08:08:45.01#ibcon#flushed, iclass 7, count 2 2006.257.08:08:45.01#ibcon#about to write, iclass 7, count 2 2006.257.08:08:45.01#ibcon#wrote, iclass 7, count 2 2006.257.08:08:45.01#ibcon#about to read 3, iclass 7, count 2 2006.257.08:08:45.03#ibcon#read 3, iclass 7, count 2 2006.257.08:08:45.03#ibcon#about to read 4, iclass 7, count 2 2006.257.08:08:45.03#ibcon#read 4, iclass 7, count 2 2006.257.08:08:45.03#ibcon#about to read 5, iclass 7, count 2 2006.257.08:08:45.03#ibcon#read 5, iclass 7, count 2 2006.257.08:08:45.03#ibcon#about to read 6, iclass 7, count 2 2006.257.08:08:45.03#ibcon#read 6, iclass 7, count 2 2006.257.08:08:45.03#ibcon#end of sib2, iclass 7, count 2 2006.257.08:08:45.03#ibcon#*mode == 0, iclass 7, count 2 2006.257.08:08:45.03#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.08:08:45.03#ibcon#[27=AT04-05\r\n] 2006.257.08:08:45.03#ibcon#*before write, iclass 7, count 2 2006.257.08:08:45.03#ibcon#enter sib2, iclass 7, count 2 2006.257.08:08:45.03#ibcon#flushed, iclass 7, count 2 2006.257.08:08:45.03#ibcon#about to write, iclass 7, count 2 2006.257.08:08:45.03#ibcon#wrote, iclass 7, count 2 2006.257.08:08:45.03#ibcon#about to read 3, iclass 7, count 2 2006.257.08:08:45.06#ibcon#read 3, iclass 7, count 2 2006.257.08:08:45.06#ibcon#about to read 4, iclass 7, count 2 2006.257.08:08:45.06#ibcon#read 4, iclass 7, count 2 2006.257.08:08:45.06#ibcon#about to read 5, iclass 7, count 2 2006.257.08:08:45.06#ibcon#read 5, iclass 7, count 2 2006.257.08:08:45.06#ibcon#about to read 6, iclass 7, count 2 2006.257.08:08:45.06#ibcon#read 6, iclass 7, count 2 2006.257.08:08:45.06#ibcon#end of sib2, iclass 7, count 2 2006.257.08:08:45.06#ibcon#*after write, iclass 7, count 2 2006.257.08:08:45.06#ibcon#*before return 0, iclass 7, count 2 2006.257.08:08:45.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:45.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:08:45.06#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.08:08:45.06#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:45.06#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:45.18#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:45.18#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:45.18#ibcon#enter wrdev, iclass 7, count 0 2006.257.08:08:45.18#ibcon#first serial, iclass 7, count 0 2006.257.08:08:45.18#ibcon#enter sib2, iclass 7, count 0 2006.257.08:08:45.18#ibcon#flushed, iclass 7, count 0 2006.257.08:08:45.18#ibcon#about to write, iclass 7, count 0 2006.257.08:08:45.18#ibcon#wrote, iclass 7, count 0 2006.257.08:08:45.18#ibcon#about to read 3, iclass 7, count 0 2006.257.08:08:45.20#ibcon#read 3, iclass 7, count 0 2006.257.08:08:45.20#ibcon#about to read 4, iclass 7, count 0 2006.257.08:08:45.20#ibcon#read 4, iclass 7, count 0 2006.257.08:08:45.20#ibcon#about to read 5, iclass 7, count 0 2006.257.08:08:45.20#ibcon#read 5, iclass 7, count 0 2006.257.08:08:45.20#ibcon#about to read 6, iclass 7, count 0 2006.257.08:08:45.20#ibcon#read 6, iclass 7, count 0 2006.257.08:08:45.20#ibcon#end of sib2, iclass 7, count 0 2006.257.08:08:45.20#ibcon#*mode == 0, iclass 7, count 0 2006.257.08:08:45.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.08:08:45.20#ibcon#[27=USB\r\n] 2006.257.08:08:45.20#ibcon#*before write, iclass 7, count 0 2006.257.08:08:45.20#ibcon#enter sib2, iclass 7, count 0 2006.257.08:08:45.20#ibcon#flushed, iclass 7, count 0 2006.257.08:08:45.20#ibcon#about to write, iclass 7, count 0 2006.257.08:08:45.20#ibcon#wrote, iclass 7, count 0 2006.257.08:08:45.20#ibcon#about to read 3, iclass 7, count 0 2006.257.08:08:45.23#ibcon#read 3, iclass 7, count 0 2006.257.08:08:45.23#ibcon#about to read 4, iclass 7, count 0 2006.257.08:08:45.23#ibcon#read 4, iclass 7, count 0 2006.257.08:08:45.23#ibcon#about to read 5, iclass 7, count 0 2006.257.08:08:45.23#ibcon#read 5, iclass 7, count 0 2006.257.08:08:45.23#ibcon#about to read 6, iclass 7, count 0 2006.257.08:08:45.23#ibcon#read 6, iclass 7, count 0 2006.257.08:08:45.23#ibcon#end of sib2, iclass 7, count 0 2006.257.08:08:45.23#ibcon#*after write, iclass 7, count 0 2006.257.08:08:45.23#ibcon#*before return 0, iclass 7, count 0 2006.257.08:08:45.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:45.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:08:45.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.08:08:45.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.08:08:45.23$vck44/vblo=5,709.99 2006.257.08:08:45.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.08:08:45.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.08:08:45.23#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:45.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:45.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:45.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:45.23#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:08:45.23#ibcon#first serial, iclass 11, count 0 2006.257.08:08:45.23#ibcon#enter sib2, iclass 11, count 0 2006.257.08:08:45.23#ibcon#flushed, iclass 11, count 0 2006.257.08:08:45.23#ibcon#about to write, iclass 11, count 0 2006.257.08:08:45.23#ibcon#wrote, iclass 11, count 0 2006.257.08:08:45.23#ibcon#about to read 3, iclass 11, count 0 2006.257.08:08:45.25#ibcon#read 3, iclass 11, count 0 2006.257.08:08:45.25#ibcon#about to read 4, iclass 11, count 0 2006.257.08:08:45.25#ibcon#read 4, iclass 11, count 0 2006.257.08:08:45.25#ibcon#about to read 5, iclass 11, count 0 2006.257.08:08:45.25#ibcon#read 5, iclass 11, count 0 2006.257.08:08:45.25#ibcon#about to read 6, iclass 11, count 0 2006.257.08:08:45.25#ibcon#read 6, iclass 11, count 0 2006.257.08:08:45.25#ibcon#end of sib2, iclass 11, count 0 2006.257.08:08:45.25#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:08:45.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:08:45.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:08:45.25#ibcon#*before write, iclass 11, count 0 2006.257.08:08:45.25#ibcon#enter sib2, iclass 11, count 0 2006.257.08:08:45.25#ibcon#flushed, iclass 11, count 0 2006.257.08:08:45.25#ibcon#about to write, iclass 11, count 0 2006.257.08:08:45.25#ibcon#wrote, iclass 11, count 0 2006.257.08:08:45.25#ibcon#about to read 3, iclass 11, count 0 2006.257.08:08:45.29#ibcon#read 3, iclass 11, count 0 2006.257.08:08:45.29#ibcon#about to read 4, iclass 11, count 0 2006.257.08:08:45.29#ibcon#read 4, iclass 11, count 0 2006.257.08:08:45.29#ibcon#about to read 5, iclass 11, count 0 2006.257.08:08:45.29#ibcon#read 5, iclass 11, count 0 2006.257.08:08:45.29#ibcon#about to read 6, iclass 11, count 0 2006.257.08:08:45.29#ibcon#read 6, iclass 11, count 0 2006.257.08:08:45.29#ibcon#end of sib2, iclass 11, count 0 2006.257.08:08:45.29#ibcon#*after write, iclass 11, count 0 2006.257.08:08:45.29#ibcon#*before return 0, iclass 11, count 0 2006.257.08:08:45.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:45.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:08:45.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:08:45.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:08:45.29$vck44/vb=5,4 2006.257.08:08:45.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.08:08:45.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.08:08:45.29#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:45.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:45.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:45.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:45.35#ibcon#enter wrdev, iclass 13, count 2 2006.257.08:08:45.35#ibcon#first serial, iclass 13, count 2 2006.257.08:08:45.35#ibcon#enter sib2, iclass 13, count 2 2006.257.08:08:45.35#ibcon#flushed, iclass 13, count 2 2006.257.08:08:45.35#ibcon#about to write, iclass 13, count 2 2006.257.08:08:45.35#ibcon#wrote, iclass 13, count 2 2006.257.08:08:45.35#ibcon#about to read 3, iclass 13, count 2 2006.257.08:08:45.37#ibcon#read 3, iclass 13, count 2 2006.257.08:08:45.37#ibcon#about to read 4, iclass 13, count 2 2006.257.08:08:45.37#ibcon#read 4, iclass 13, count 2 2006.257.08:08:45.37#ibcon#about to read 5, iclass 13, count 2 2006.257.08:08:45.37#ibcon#read 5, iclass 13, count 2 2006.257.08:08:45.37#ibcon#about to read 6, iclass 13, count 2 2006.257.08:08:45.37#ibcon#read 6, iclass 13, count 2 2006.257.08:08:45.37#ibcon#end of sib2, iclass 13, count 2 2006.257.08:08:45.37#ibcon#*mode == 0, iclass 13, count 2 2006.257.08:08:45.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.08:08:45.37#ibcon#[27=AT05-04\r\n] 2006.257.08:08:45.37#ibcon#*before write, iclass 13, count 2 2006.257.08:08:45.37#ibcon#enter sib2, iclass 13, count 2 2006.257.08:08:45.37#ibcon#flushed, iclass 13, count 2 2006.257.08:08:45.37#ibcon#about to write, iclass 13, count 2 2006.257.08:08:45.37#ibcon#wrote, iclass 13, count 2 2006.257.08:08:45.37#ibcon#about to read 3, iclass 13, count 2 2006.257.08:08:45.40#ibcon#read 3, iclass 13, count 2 2006.257.08:08:45.40#ibcon#about to read 4, iclass 13, count 2 2006.257.08:08:45.40#ibcon#read 4, iclass 13, count 2 2006.257.08:08:45.40#ibcon#about to read 5, iclass 13, count 2 2006.257.08:08:45.40#ibcon#read 5, iclass 13, count 2 2006.257.08:08:45.40#ibcon#about to read 6, iclass 13, count 2 2006.257.08:08:45.40#ibcon#read 6, iclass 13, count 2 2006.257.08:08:45.40#ibcon#end of sib2, iclass 13, count 2 2006.257.08:08:45.40#ibcon#*after write, iclass 13, count 2 2006.257.08:08:45.40#ibcon#*before return 0, iclass 13, count 2 2006.257.08:08:45.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:45.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:08:45.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.08:08:45.40#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:45.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:45.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:45.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:45.52#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:08:45.52#ibcon#first serial, iclass 13, count 0 2006.257.08:08:45.52#ibcon#enter sib2, iclass 13, count 0 2006.257.08:08:45.52#ibcon#flushed, iclass 13, count 0 2006.257.08:08:45.52#ibcon#about to write, iclass 13, count 0 2006.257.08:08:45.52#ibcon#wrote, iclass 13, count 0 2006.257.08:08:45.52#ibcon#about to read 3, iclass 13, count 0 2006.257.08:08:45.54#ibcon#read 3, iclass 13, count 0 2006.257.08:08:45.54#ibcon#about to read 4, iclass 13, count 0 2006.257.08:08:45.54#ibcon#read 4, iclass 13, count 0 2006.257.08:08:45.54#ibcon#about to read 5, iclass 13, count 0 2006.257.08:08:45.54#ibcon#read 5, iclass 13, count 0 2006.257.08:08:45.54#ibcon#about to read 6, iclass 13, count 0 2006.257.08:08:45.54#ibcon#read 6, iclass 13, count 0 2006.257.08:08:45.54#ibcon#end of sib2, iclass 13, count 0 2006.257.08:08:45.54#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:08:45.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:08:45.54#ibcon#[27=USB\r\n] 2006.257.08:08:45.54#ibcon#*before write, iclass 13, count 0 2006.257.08:08:45.54#ibcon#enter sib2, iclass 13, count 0 2006.257.08:08:45.54#ibcon#flushed, iclass 13, count 0 2006.257.08:08:45.54#ibcon#about to write, iclass 13, count 0 2006.257.08:08:45.54#ibcon#wrote, iclass 13, count 0 2006.257.08:08:45.54#ibcon#about to read 3, iclass 13, count 0 2006.257.08:08:45.57#ibcon#read 3, iclass 13, count 0 2006.257.08:08:45.57#ibcon#about to read 4, iclass 13, count 0 2006.257.08:08:45.57#ibcon#read 4, iclass 13, count 0 2006.257.08:08:45.57#ibcon#about to read 5, iclass 13, count 0 2006.257.08:08:45.57#ibcon#read 5, iclass 13, count 0 2006.257.08:08:45.57#ibcon#about to read 6, iclass 13, count 0 2006.257.08:08:45.57#ibcon#read 6, iclass 13, count 0 2006.257.08:08:45.57#ibcon#end of sib2, iclass 13, count 0 2006.257.08:08:45.57#ibcon#*after write, iclass 13, count 0 2006.257.08:08:45.57#ibcon#*before return 0, iclass 13, count 0 2006.257.08:08:45.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:45.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:08:45.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:08:45.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:08:45.57$vck44/vblo=6,719.99 2006.257.08:08:45.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.08:08:45.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.08:08:45.57#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:45.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:45.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:45.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:45.57#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:08:45.57#ibcon#first serial, iclass 15, count 0 2006.257.08:08:45.57#ibcon#enter sib2, iclass 15, count 0 2006.257.08:08:45.57#ibcon#flushed, iclass 15, count 0 2006.257.08:08:45.57#ibcon#about to write, iclass 15, count 0 2006.257.08:08:45.57#ibcon#wrote, iclass 15, count 0 2006.257.08:08:45.57#ibcon#about to read 3, iclass 15, count 0 2006.257.08:08:45.59#ibcon#read 3, iclass 15, count 0 2006.257.08:08:45.59#ibcon#about to read 4, iclass 15, count 0 2006.257.08:08:45.59#ibcon#read 4, iclass 15, count 0 2006.257.08:08:45.59#ibcon#about to read 5, iclass 15, count 0 2006.257.08:08:45.59#ibcon#read 5, iclass 15, count 0 2006.257.08:08:45.59#ibcon#about to read 6, iclass 15, count 0 2006.257.08:08:45.59#ibcon#read 6, iclass 15, count 0 2006.257.08:08:45.59#ibcon#end of sib2, iclass 15, count 0 2006.257.08:08:45.59#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:08:45.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:08:45.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:08:45.59#ibcon#*before write, iclass 15, count 0 2006.257.08:08:45.59#ibcon#enter sib2, iclass 15, count 0 2006.257.08:08:45.59#ibcon#flushed, iclass 15, count 0 2006.257.08:08:45.59#ibcon#about to write, iclass 15, count 0 2006.257.08:08:45.59#ibcon#wrote, iclass 15, count 0 2006.257.08:08:45.59#ibcon#about to read 3, iclass 15, count 0 2006.257.08:08:45.63#ibcon#read 3, iclass 15, count 0 2006.257.08:08:45.63#ibcon#about to read 4, iclass 15, count 0 2006.257.08:08:45.63#ibcon#read 4, iclass 15, count 0 2006.257.08:08:45.63#ibcon#about to read 5, iclass 15, count 0 2006.257.08:08:45.63#ibcon#read 5, iclass 15, count 0 2006.257.08:08:45.63#ibcon#about to read 6, iclass 15, count 0 2006.257.08:08:45.63#ibcon#read 6, iclass 15, count 0 2006.257.08:08:45.63#ibcon#end of sib2, iclass 15, count 0 2006.257.08:08:45.63#ibcon#*after write, iclass 15, count 0 2006.257.08:08:45.63#ibcon#*before return 0, iclass 15, count 0 2006.257.08:08:45.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:45.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:08:45.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:08:45.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:08:45.63$vck44/vb=6,4 2006.257.08:08:45.63#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.08:08:45.63#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.08:08:45.63#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:45.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:45.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:45.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:45.69#ibcon#enter wrdev, iclass 17, count 2 2006.257.08:08:45.69#ibcon#first serial, iclass 17, count 2 2006.257.08:08:45.69#ibcon#enter sib2, iclass 17, count 2 2006.257.08:08:45.69#ibcon#flushed, iclass 17, count 2 2006.257.08:08:45.69#ibcon#about to write, iclass 17, count 2 2006.257.08:08:45.69#ibcon#wrote, iclass 17, count 2 2006.257.08:08:45.69#ibcon#about to read 3, iclass 17, count 2 2006.257.08:08:45.71#ibcon#read 3, iclass 17, count 2 2006.257.08:08:45.71#ibcon#about to read 4, iclass 17, count 2 2006.257.08:08:45.71#ibcon#read 4, iclass 17, count 2 2006.257.08:08:45.71#ibcon#about to read 5, iclass 17, count 2 2006.257.08:08:45.71#ibcon#read 5, iclass 17, count 2 2006.257.08:08:45.71#ibcon#about to read 6, iclass 17, count 2 2006.257.08:08:45.71#ibcon#read 6, iclass 17, count 2 2006.257.08:08:45.71#ibcon#end of sib2, iclass 17, count 2 2006.257.08:08:45.71#ibcon#*mode == 0, iclass 17, count 2 2006.257.08:08:45.71#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.08:08:45.71#ibcon#[27=AT06-04\r\n] 2006.257.08:08:45.71#ibcon#*before write, iclass 17, count 2 2006.257.08:08:45.71#ibcon#enter sib2, iclass 17, count 2 2006.257.08:08:45.71#ibcon#flushed, iclass 17, count 2 2006.257.08:08:45.71#ibcon#about to write, iclass 17, count 2 2006.257.08:08:45.71#ibcon#wrote, iclass 17, count 2 2006.257.08:08:45.71#ibcon#about to read 3, iclass 17, count 2 2006.257.08:08:45.74#ibcon#read 3, iclass 17, count 2 2006.257.08:08:45.74#ibcon#about to read 4, iclass 17, count 2 2006.257.08:08:45.74#ibcon#read 4, iclass 17, count 2 2006.257.08:08:45.74#ibcon#about to read 5, iclass 17, count 2 2006.257.08:08:45.74#ibcon#read 5, iclass 17, count 2 2006.257.08:08:45.74#ibcon#about to read 6, iclass 17, count 2 2006.257.08:08:45.74#ibcon#read 6, iclass 17, count 2 2006.257.08:08:45.74#ibcon#end of sib2, iclass 17, count 2 2006.257.08:08:45.74#ibcon#*after write, iclass 17, count 2 2006.257.08:08:45.74#ibcon#*before return 0, iclass 17, count 2 2006.257.08:08:45.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:45.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:08:45.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.08:08:45.74#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:45.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:45.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:45.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:45.86#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:08:45.86#ibcon#first serial, iclass 17, count 0 2006.257.08:08:45.86#ibcon#enter sib2, iclass 17, count 0 2006.257.08:08:45.86#ibcon#flushed, iclass 17, count 0 2006.257.08:08:45.86#ibcon#about to write, iclass 17, count 0 2006.257.08:08:45.86#ibcon#wrote, iclass 17, count 0 2006.257.08:08:45.86#ibcon#about to read 3, iclass 17, count 0 2006.257.08:08:45.88#ibcon#read 3, iclass 17, count 0 2006.257.08:08:45.88#ibcon#about to read 4, iclass 17, count 0 2006.257.08:08:45.88#ibcon#read 4, iclass 17, count 0 2006.257.08:08:45.88#ibcon#about to read 5, iclass 17, count 0 2006.257.08:08:45.88#ibcon#read 5, iclass 17, count 0 2006.257.08:08:45.88#ibcon#about to read 6, iclass 17, count 0 2006.257.08:08:45.88#ibcon#read 6, iclass 17, count 0 2006.257.08:08:45.88#ibcon#end of sib2, iclass 17, count 0 2006.257.08:08:45.88#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:08:45.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:08:45.88#ibcon#[27=USB\r\n] 2006.257.08:08:45.88#ibcon#*before write, iclass 17, count 0 2006.257.08:08:45.88#ibcon#enter sib2, iclass 17, count 0 2006.257.08:08:45.88#ibcon#flushed, iclass 17, count 0 2006.257.08:08:45.88#ibcon#about to write, iclass 17, count 0 2006.257.08:08:45.88#ibcon#wrote, iclass 17, count 0 2006.257.08:08:45.88#ibcon#about to read 3, iclass 17, count 0 2006.257.08:08:45.91#ibcon#read 3, iclass 17, count 0 2006.257.08:08:45.91#ibcon#about to read 4, iclass 17, count 0 2006.257.08:08:45.91#ibcon#read 4, iclass 17, count 0 2006.257.08:08:45.91#ibcon#about to read 5, iclass 17, count 0 2006.257.08:08:45.91#ibcon#read 5, iclass 17, count 0 2006.257.08:08:45.91#ibcon#about to read 6, iclass 17, count 0 2006.257.08:08:45.91#ibcon#read 6, iclass 17, count 0 2006.257.08:08:45.91#ibcon#end of sib2, iclass 17, count 0 2006.257.08:08:45.91#ibcon#*after write, iclass 17, count 0 2006.257.08:08:45.91#ibcon#*before return 0, iclass 17, count 0 2006.257.08:08:45.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:45.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:08:45.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:08:45.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:08:45.91$vck44/vblo=7,734.99 2006.257.08:08:45.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.08:08:45.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.08:08:45.91#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:45.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:45.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:45.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:45.91#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:08:45.91#ibcon#first serial, iclass 19, count 0 2006.257.08:08:45.91#ibcon#enter sib2, iclass 19, count 0 2006.257.08:08:45.91#ibcon#flushed, iclass 19, count 0 2006.257.08:08:45.91#ibcon#about to write, iclass 19, count 0 2006.257.08:08:45.91#ibcon#wrote, iclass 19, count 0 2006.257.08:08:45.91#ibcon#about to read 3, iclass 19, count 0 2006.257.08:08:45.93#ibcon#read 3, iclass 19, count 0 2006.257.08:08:45.93#ibcon#about to read 4, iclass 19, count 0 2006.257.08:08:45.93#ibcon#read 4, iclass 19, count 0 2006.257.08:08:45.93#ibcon#about to read 5, iclass 19, count 0 2006.257.08:08:45.93#ibcon#read 5, iclass 19, count 0 2006.257.08:08:45.93#ibcon#about to read 6, iclass 19, count 0 2006.257.08:08:45.93#ibcon#read 6, iclass 19, count 0 2006.257.08:08:45.93#ibcon#end of sib2, iclass 19, count 0 2006.257.08:08:45.93#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:08:45.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:08:45.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:08:45.93#ibcon#*before write, iclass 19, count 0 2006.257.08:08:45.93#ibcon#enter sib2, iclass 19, count 0 2006.257.08:08:45.93#ibcon#flushed, iclass 19, count 0 2006.257.08:08:45.93#ibcon#about to write, iclass 19, count 0 2006.257.08:08:45.93#ibcon#wrote, iclass 19, count 0 2006.257.08:08:45.93#ibcon#about to read 3, iclass 19, count 0 2006.257.08:08:45.97#ibcon#read 3, iclass 19, count 0 2006.257.08:08:45.97#ibcon#about to read 4, iclass 19, count 0 2006.257.08:08:45.97#ibcon#read 4, iclass 19, count 0 2006.257.08:08:45.97#ibcon#about to read 5, iclass 19, count 0 2006.257.08:08:45.97#ibcon#read 5, iclass 19, count 0 2006.257.08:08:45.97#ibcon#about to read 6, iclass 19, count 0 2006.257.08:08:45.97#ibcon#read 6, iclass 19, count 0 2006.257.08:08:45.97#ibcon#end of sib2, iclass 19, count 0 2006.257.08:08:45.97#ibcon#*after write, iclass 19, count 0 2006.257.08:08:45.97#ibcon#*before return 0, iclass 19, count 0 2006.257.08:08:45.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:45.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:08:45.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:08:45.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:08:45.97$vck44/vb=7,4 2006.257.08:08:45.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.08:08:45.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.08:08:45.97#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:45.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:46.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:46.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:46.03#ibcon#enter wrdev, iclass 21, count 2 2006.257.08:08:46.03#ibcon#first serial, iclass 21, count 2 2006.257.08:08:46.03#ibcon#enter sib2, iclass 21, count 2 2006.257.08:08:46.03#ibcon#flushed, iclass 21, count 2 2006.257.08:08:46.03#ibcon#about to write, iclass 21, count 2 2006.257.08:08:46.03#ibcon#wrote, iclass 21, count 2 2006.257.08:08:46.03#ibcon#about to read 3, iclass 21, count 2 2006.257.08:08:46.05#ibcon#read 3, iclass 21, count 2 2006.257.08:08:46.05#ibcon#about to read 4, iclass 21, count 2 2006.257.08:08:46.05#ibcon#read 4, iclass 21, count 2 2006.257.08:08:46.05#ibcon#about to read 5, iclass 21, count 2 2006.257.08:08:46.05#ibcon#read 5, iclass 21, count 2 2006.257.08:08:46.05#ibcon#about to read 6, iclass 21, count 2 2006.257.08:08:46.05#ibcon#read 6, iclass 21, count 2 2006.257.08:08:46.05#ibcon#end of sib2, iclass 21, count 2 2006.257.08:08:46.05#ibcon#*mode == 0, iclass 21, count 2 2006.257.08:08:46.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.08:08:46.05#ibcon#[27=AT07-04\r\n] 2006.257.08:08:46.05#ibcon#*before write, iclass 21, count 2 2006.257.08:08:46.05#ibcon#enter sib2, iclass 21, count 2 2006.257.08:08:46.05#ibcon#flushed, iclass 21, count 2 2006.257.08:08:46.05#ibcon#about to write, iclass 21, count 2 2006.257.08:08:46.05#ibcon#wrote, iclass 21, count 2 2006.257.08:08:46.05#ibcon#about to read 3, iclass 21, count 2 2006.257.08:08:46.08#ibcon#read 3, iclass 21, count 2 2006.257.08:08:46.08#ibcon#about to read 4, iclass 21, count 2 2006.257.08:08:46.08#ibcon#read 4, iclass 21, count 2 2006.257.08:08:46.08#ibcon#about to read 5, iclass 21, count 2 2006.257.08:08:46.08#ibcon#read 5, iclass 21, count 2 2006.257.08:08:46.08#ibcon#about to read 6, iclass 21, count 2 2006.257.08:08:46.08#ibcon#read 6, iclass 21, count 2 2006.257.08:08:46.08#ibcon#end of sib2, iclass 21, count 2 2006.257.08:08:46.08#ibcon#*after write, iclass 21, count 2 2006.257.08:08:46.08#ibcon#*before return 0, iclass 21, count 2 2006.257.08:08:46.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:46.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:08:46.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.08:08:46.08#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:46.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:46.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:46.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:46.20#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:08:46.20#ibcon#first serial, iclass 21, count 0 2006.257.08:08:46.20#ibcon#enter sib2, iclass 21, count 0 2006.257.08:08:46.20#ibcon#flushed, iclass 21, count 0 2006.257.08:08:46.20#ibcon#about to write, iclass 21, count 0 2006.257.08:08:46.20#ibcon#wrote, iclass 21, count 0 2006.257.08:08:46.20#ibcon#about to read 3, iclass 21, count 0 2006.257.08:08:46.22#ibcon#read 3, iclass 21, count 0 2006.257.08:08:46.22#ibcon#about to read 4, iclass 21, count 0 2006.257.08:08:46.22#ibcon#read 4, iclass 21, count 0 2006.257.08:08:46.22#ibcon#about to read 5, iclass 21, count 0 2006.257.08:08:46.22#ibcon#read 5, iclass 21, count 0 2006.257.08:08:46.22#ibcon#about to read 6, iclass 21, count 0 2006.257.08:08:46.22#ibcon#read 6, iclass 21, count 0 2006.257.08:08:46.22#ibcon#end of sib2, iclass 21, count 0 2006.257.08:08:46.22#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:08:46.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:08:46.22#ibcon#[27=USB\r\n] 2006.257.08:08:46.22#ibcon#*before write, iclass 21, count 0 2006.257.08:08:46.22#ibcon#enter sib2, iclass 21, count 0 2006.257.08:08:46.22#ibcon#flushed, iclass 21, count 0 2006.257.08:08:46.22#ibcon#about to write, iclass 21, count 0 2006.257.08:08:46.22#ibcon#wrote, iclass 21, count 0 2006.257.08:08:46.22#ibcon#about to read 3, iclass 21, count 0 2006.257.08:08:46.25#ibcon#read 3, iclass 21, count 0 2006.257.08:08:46.25#ibcon#about to read 4, iclass 21, count 0 2006.257.08:08:46.25#ibcon#read 4, iclass 21, count 0 2006.257.08:08:46.25#ibcon#about to read 5, iclass 21, count 0 2006.257.08:08:46.25#ibcon#read 5, iclass 21, count 0 2006.257.08:08:46.25#ibcon#about to read 6, iclass 21, count 0 2006.257.08:08:46.25#ibcon#read 6, iclass 21, count 0 2006.257.08:08:46.25#ibcon#end of sib2, iclass 21, count 0 2006.257.08:08:46.25#ibcon#*after write, iclass 21, count 0 2006.257.08:08:46.25#ibcon#*before return 0, iclass 21, count 0 2006.257.08:08:46.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:46.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:08:46.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:08:46.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:08:46.25$vck44/vblo=8,744.99 2006.257.08:08:46.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.08:08:46.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.08:08:46.25#ibcon#ireg 17 cls_cnt 0 2006.257.08:08:46.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:46.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:46.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:46.25#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:08:46.25#ibcon#first serial, iclass 23, count 0 2006.257.08:08:46.25#ibcon#enter sib2, iclass 23, count 0 2006.257.08:08:46.25#ibcon#flushed, iclass 23, count 0 2006.257.08:08:46.25#ibcon#about to write, iclass 23, count 0 2006.257.08:08:46.25#ibcon#wrote, iclass 23, count 0 2006.257.08:08:46.25#ibcon#about to read 3, iclass 23, count 0 2006.257.08:08:46.27#ibcon#read 3, iclass 23, count 0 2006.257.08:08:46.27#ibcon#about to read 4, iclass 23, count 0 2006.257.08:08:46.27#ibcon#read 4, iclass 23, count 0 2006.257.08:08:46.27#ibcon#about to read 5, iclass 23, count 0 2006.257.08:08:46.27#ibcon#read 5, iclass 23, count 0 2006.257.08:08:46.27#ibcon#about to read 6, iclass 23, count 0 2006.257.08:08:46.27#ibcon#read 6, iclass 23, count 0 2006.257.08:08:46.27#ibcon#end of sib2, iclass 23, count 0 2006.257.08:08:46.27#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:08:46.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:08:46.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:08:46.27#ibcon#*before write, iclass 23, count 0 2006.257.08:08:46.27#ibcon#enter sib2, iclass 23, count 0 2006.257.08:08:46.27#ibcon#flushed, iclass 23, count 0 2006.257.08:08:46.27#ibcon#about to write, iclass 23, count 0 2006.257.08:08:46.27#ibcon#wrote, iclass 23, count 0 2006.257.08:08:46.27#ibcon#about to read 3, iclass 23, count 0 2006.257.08:08:46.31#ibcon#read 3, iclass 23, count 0 2006.257.08:08:46.31#ibcon#about to read 4, iclass 23, count 0 2006.257.08:08:46.31#ibcon#read 4, iclass 23, count 0 2006.257.08:08:46.31#ibcon#about to read 5, iclass 23, count 0 2006.257.08:08:46.31#ibcon#read 5, iclass 23, count 0 2006.257.08:08:46.31#ibcon#about to read 6, iclass 23, count 0 2006.257.08:08:46.31#ibcon#read 6, iclass 23, count 0 2006.257.08:08:46.31#ibcon#end of sib2, iclass 23, count 0 2006.257.08:08:46.31#ibcon#*after write, iclass 23, count 0 2006.257.08:08:46.31#ibcon#*before return 0, iclass 23, count 0 2006.257.08:08:46.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:46.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:08:46.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:08:46.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:08:46.31$vck44/vb=8,4 2006.257.08:08:46.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.08:08:46.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.08:08:46.31#ibcon#ireg 11 cls_cnt 2 2006.257.08:08:46.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:46.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:46.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:46.37#ibcon#enter wrdev, iclass 25, count 2 2006.257.08:08:46.37#ibcon#first serial, iclass 25, count 2 2006.257.08:08:46.37#ibcon#enter sib2, iclass 25, count 2 2006.257.08:08:46.37#ibcon#flushed, iclass 25, count 2 2006.257.08:08:46.37#ibcon#about to write, iclass 25, count 2 2006.257.08:08:46.37#ibcon#wrote, iclass 25, count 2 2006.257.08:08:46.37#ibcon#about to read 3, iclass 25, count 2 2006.257.08:08:46.39#ibcon#read 3, iclass 25, count 2 2006.257.08:08:46.39#ibcon#about to read 4, iclass 25, count 2 2006.257.08:08:46.39#ibcon#read 4, iclass 25, count 2 2006.257.08:08:46.39#ibcon#about to read 5, iclass 25, count 2 2006.257.08:08:46.39#ibcon#read 5, iclass 25, count 2 2006.257.08:08:46.39#ibcon#about to read 6, iclass 25, count 2 2006.257.08:08:46.39#ibcon#read 6, iclass 25, count 2 2006.257.08:08:46.39#ibcon#end of sib2, iclass 25, count 2 2006.257.08:08:46.39#ibcon#*mode == 0, iclass 25, count 2 2006.257.08:08:46.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.08:08:46.39#ibcon#[27=AT08-04\r\n] 2006.257.08:08:46.39#ibcon#*before write, iclass 25, count 2 2006.257.08:08:46.39#ibcon#enter sib2, iclass 25, count 2 2006.257.08:08:46.39#ibcon#flushed, iclass 25, count 2 2006.257.08:08:46.39#ibcon#about to write, iclass 25, count 2 2006.257.08:08:46.39#ibcon#wrote, iclass 25, count 2 2006.257.08:08:46.39#ibcon#about to read 3, iclass 25, count 2 2006.257.08:08:46.42#ibcon#read 3, iclass 25, count 2 2006.257.08:08:46.42#ibcon#about to read 4, iclass 25, count 2 2006.257.08:08:46.42#ibcon#read 4, iclass 25, count 2 2006.257.08:08:46.42#ibcon#about to read 5, iclass 25, count 2 2006.257.08:08:46.42#ibcon#read 5, iclass 25, count 2 2006.257.08:08:46.42#ibcon#about to read 6, iclass 25, count 2 2006.257.08:08:46.42#ibcon#read 6, iclass 25, count 2 2006.257.08:08:46.42#ibcon#end of sib2, iclass 25, count 2 2006.257.08:08:46.42#ibcon#*after write, iclass 25, count 2 2006.257.08:08:46.42#ibcon#*before return 0, iclass 25, count 2 2006.257.08:08:46.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:46.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:08:46.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.08:08:46.42#ibcon#ireg 7 cls_cnt 0 2006.257.08:08:46.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:46.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:46.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:46.54#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:08:46.54#ibcon#first serial, iclass 25, count 0 2006.257.08:08:46.54#ibcon#enter sib2, iclass 25, count 0 2006.257.08:08:46.54#ibcon#flushed, iclass 25, count 0 2006.257.08:08:46.54#ibcon#about to write, iclass 25, count 0 2006.257.08:08:46.54#ibcon#wrote, iclass 25, count 0 2006.257.08:08:46.54#ibcon#about to read 3, iclass 25, count 0 2006.257.08:08:46.56#ibcon#read 3, iclass 25, count 0 2006.257.08:08:46.56#ibcon#about to read 4, iclass 25, count 0 2006.257.08:08:46.56#ibcon#read 4, iclass 25, count 0 2006.257.08:08:46.56#ibcon#about to read 5, iclass 25, count 0 2006.257.08:08:46.56#ibcon#read 5, iclass 25, count 0 2006.257.08:08:46.56#ibcon#about to read 6, iclass 25, count 0 2006.257.08:08:46.56#ibcon#read 6, iclass 25, count 0 2006.257.08:08:46.56#ibcon#end of sib2, iclass 25, count 0 2006.257.08:08:46.56#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:08:46.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:08:46.56#ibcon#[27=USB\r\n] 2006.257.08:08:46.56#ibcon#*before write, iclass 25, count 0 2006.257.08:08:46.56#ibcon#enter sib2, iclass 25, count 0 2006.257.08:08:46.56#ibcon#flushed, iclass 25, count 0 2006.257.08:08:46.56#ibcon#about to write, iclass 25, count 0 2006.257.08:08:46.56#ibcon#wrote, iclass 25, count 0 2006.257.08:08:46.56#ibcon#about to read 3, iclass 25, count 0 2006.257.08:08:46.59#ibcon#read 3, iclass 25, count 0 2006.257.08:08:46.59#ibcon#about to read 4, iclass 25, count 0 2006.257.08:08:46.59#ibcon#read 4, iclass 25, count 0 2006.257.08:08:46.59#ibcon#about to read 5, iclass 25, count 0 2006.257.08:08:46.59#ibcon#read 5, iclass 25, count 0 2006.257.08:08:46.59#ibcon#about to read 6, iclass 25, count 0 2006.257.08:08:46.59#ibcon#read 6, iclass 25, count 0 2006.257.08:08:46.59#ibcon#end of sib2, iclass 25, count 0 2006.257.08:08:46.59#ibcon#*after write, iclass 25, count 0 2006.257.08:08:46.59#ibcon#*before return 0, iclass 25, count 0 2006.257.08:08:46.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:46.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:08:46.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:08:46.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:08:46.59$vck44/vabw=wide 2006.257.08:08:46.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.08:08:46.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.08:08:46.59#ibcon#ireg 8 cls_cnt 0 2006.257.08:08:46.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:08:46.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:08:46.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:08:46.59#ibcon#enter wrdev, iclass 27, count 0 2006.257.08:08:46.59#ibcon#first serial, iclass 27, count 0 2006.257.08:08:46.59#ibcon#enter sib2, iclass 27, count 0 2006.257.08:08:46.59#ibcon#flushed, iclass 27, count 0 2006.257.08:08:46.59#ibcon#about to write, iclass 27, count 0 2006.257.08:08:46.59#ibcon#wrote, iclass 27, count 0 2006.257.08:08:46.59#ibcon#about to read 3, iclass 27, count 0 2006.257.08:08:46.61#ibcon#read 3, iclass 27, count 0 2006.257.08:08:46.61#ibcon#about to read 4, iclass 27, count 0 2006.257.08:08:46.61#ibcon#read 4, iclass 27, count 0 2006.257.08:08:46.61#ibcon#about to read 5, iclass 27, count 0 2006.257.08:08:46.61#ibcon#read 5, iclass 27, count 0 2006.257.08:08:46.61#ibcon#about to read 6, iclass 27, count 0 2006.257.08:08:46.61#ibcon#read 6, iclass 27, count 0 2006.257.08:08:46.61#ibcon#end of sib2, iclass 27, count 0 2006.257.08:08:46.61#ibcon#*mode == 0, iclass 27, count 0 2006.257.08:08:46.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.08:08:46.61#ibcon#[25=BW32\r\n] 2006.257.08:08:46.61#ibcon#*before write, iclass 27, count 0 2006.257.08:08:46.61#ibcon#enter sib2, iclass 27, count 0 2006.257.08:08:46.61#ibcon#flushed, iclass 27, count 0 2006.257.08:08:46.61#ibcon#about to write, iclass 27, count 0 2006.257.08:08:46.61#ibcon#wrote, iclass 27, count 0 2006.257.08:08:46.61#ibcon#about to read 3, iclass 27, count 0 2006.257.08:08:46.64#ibcon#read 3, iclass 27, count 0 2006.257.08:08:46.64#ibcon#about to read 4, iclass 27, count 0 2006.257.08:08:46.64#ibcon#read 4, iclass 27, count 0 2006.257.08:08:46.64#ibcon#about to read 5, iclass 27, count 0 2006.257.08:08:46.64#ibcon#read 5, iclass 27, count 0 2006.257.08:08:46.64#ibcon#about to read 6, iclass 27, count 0 2006.257.08:08:46.64#ibcon#read 6, iclass 27, count 0 2006.257.08:08:46.64#ibcon#end of sib2, iclass 27, count 0 2006.257.08:08:46.64#ibcon#*after write, iclass 27, count 0 2006.257.08:08:46.64#ibcon#*before return 0, iclass 27, count 0 2006.257.08:08:46.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:08:46.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:08:46.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.08:08:46.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.08:08:46.64$vck44/vbbw=wide 2006.257.08:08:46.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.08:08:46.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.08:08:46.64#ibcon#ireg 8 cls_cnt 0 2006.257.08:08:46.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:08:46.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:08:46.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:08:46.71#ibcon#enter wrdev, iclass 29, count 0 2006.257.08:08:46.71#ibcon#first serial, iclass 29, count 0 2006.257.08:08:46.71#ibcon#enter sib2, iclass 29, count 0 2006.257.08:08:46.71#ibcon#flushed, iclass 29, count 0 2006.257.08:08:46.71#ibcon#about to write, iclass 29, count 0 2006.257.08:08:46.71#ibcon#wrote, iclass 29, count 0 2006.257.08:08:46.71#ibcon#about to read 3, iclass 29, count 0 2006.257.08:08:46.73#ibcon#read 3, iclass 29, count 0 2006.257.08:08:46.73#ibcon#about to read 4, iclass 29, count 0 2006.257.08:08:46.73#ibcon#read 4, iclass 29, count 0 2006.257.08:08:46.73#ibcon#about to read 5, iclass 29, count 0 2006.257.08:08:46.73#ibcon#read 5, iclass 29, count 0 2006.257.08:08:46.73#ibcon#about to read 6, iclass 29, count 0 2006.257.08:08:46.73#ibcon#read 6, iclass 29, count 0 2006.257.08:08:46.73#ibcon#end of sib2, iclass 29, count 0 2006.257.08:08:46.73#ibcon#*mode == 0, iclass 29, count 0 2006.257.08:08:46.73#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.08:08:46.73#ibcon#[27=BW32\r\n] 2006.257.08:08:46.73#ibcon#*before write, iclass 29, count 0 2006.257.08:08:46.73#ibcon#enter sib2, iclass 29, count 0 2006.257.08:08:46.73#ibcon#flushed, iclass 29, count 0 2006.257.08:08:46.73#ibcon#about to write, iclass 29, count 0 2006.257.08:08:46.73#ibcon#wrote, iclass 29, count 0 2006.257.08:08:46.73#ibcon#about to read 3, iclass 29, count 0 2006.257.08:08:46.76#ibcon#read 3, iclass 29, count 0 2006.257.08:08:46.76#ibcon#about to read 4, iclass 29, count 0 2006.257.08:08:46.76#ibcon#read 4, iclass 29, count 0 2006.257.08:08:46.76#ibcon#about to read 5, iclass 29, count 0 2006.257.08:08:46.76#ibcon#read 5, iclass 29, count 0 2006.257.08:08:46.76#ibcon#about to read 6, iclass 29, count 0 2006.257.08:08:46.76#ibcon#read 6, iclass 29, count 0 2006.257.08:08:46.76#ibcon#end of sib2, iclass 29, count 0 2006.257.08:08:46.76#ibcon#*after write, iclass 29, count 0 2006.257.08:08:46.76#ibcon#*before return 0, iclass 29, count 0 2006.257.08:08:46.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:08:46.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:08:46.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.08:08:46.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.08:08:46.76$setupk4/ifdk4 2006.257.08:08:46.76$ifdk4/lo= 2006.257.08:08:46.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:08:46.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:08:46.76$ifdk4/patch= 2006.257.08:08:46.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:08:46.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:08:46.76$setupk4/!*+20s 2006.257.08:08:53.90#abcon#<5=/16 1.5 6.2 20.87 871012.9\r\n> 2006.257.08:08:53.92#abcon#{5=INTERFACE CLEAR} 2006.257.08:08:53.98#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:09:01.26$setupk4/"tpicd 2006.257.08:09:01.26$setupk4/echo=off 2006.257.08:09:01.26$setupk4/xlog=off 2006.257.08:09:01.26:!2006.257.08:11:25 2006.257.08:09:06.14#trakl#Source acquired 2006.257.08:09:06.14#flagr#flagr/antenna,acquired 2006.257.08:11:25.00:preob 2006.257.08:11:25.14/onsource/TRACKING 2006.257.08:11:25.14:!2006.257.08:11:35 2006.257.08:11:35.00:"tape 2006.257.08:11:35.00:"st=record 2006.257.08:11:35.00:data_valid=on 2006.257.08:11:35.00:midob 2006.257.08:11:36.14/onsource/TRACKING 2006.257.08:11:36.14/wx/20.84,1012.9,88 2006.257.08:11:36.25/cable/+6.4757E-03 2006.257.08:11:37.34/va/01,08,usb,yes,33,36 2006.257.08:11:37.34/va/02,07,usb,yes,36,37 2006.257.08:11:37.34/va/03,08,usb,yes,33,34 2006.257.08:11:37.34/va/04,07,usb,yes,37,39 2006.257.08:11:37.34/va/05,04,usb,yes,33,34 2006.257.08:11:37.34/va/06,04,usb,yes,37,37 2006.257.08:11:37.34/va/07,04,usb,yes,38,39 2006.257.08:11:37.34/va/08,04,usb,yes,32,39 2006.257.08:11:37.57/valo/01,524.99,yes,locked 2006.257.08:11:37.57/valo/02,534.99,yes,locked 2006.257.08:11:37.57/valo/03,564.99,yes,locked 2006.257.08:11:37.57/valo/04,624.99,yes,locked 2006.257.08:11:37.57/valo/05,734.99,yes,locked 2006.257.08:11:37.57/valo/06,814.99,yes,locked 2006.257.08:11:37.57/valo/07,864.99,yes,locked 2006.257.08:11:37.57/valo/08,884.99,yes,locked 2006.257.08:11:38.66/vb/01,04,usb,yes,31,29 2006.257.08:11:38.66/vb/02,05,usb,yes,29,29 2006.257.08:11:38.66/vb/03,04,usb,yes,30,33 2006.257.08:11:38.66/vb/04,05,usb,yes,30,29 2006.257.08:11:38.66/vb/05,04,usb,yes,27,29 2006.257.08:11:38.66/vb/06,04,usb,yes,31,27 2006.257.08:11:38.66/vb/07,04,usb,yes,31,31 2006.257.08:11:38.66/vb/08,04,usb,yes,28,32 2006.257.08:11:38.90/vblo/01,629.99,yes,locked 2006.257.08:11:38.90/vblo/02,634.99,yes,locked 2006.257.08:11:38.90/vblo/03,649.99,yes,locked 2006.257.08:11:38.90/vblo/04,679.99,yes,locked 2006.257.08:11:38.90/vblo/05,709.99,yes,locked 2006.257.08:11:38.90/vblo/06,719.99,yes,locked 2006.257.08:11:38.90/vblo/07,734.99,yes,locked 2006.257.08:11:38.90/vblo/08,744.99,yes,locked 2006.257.08:11:39.05/vabw/8 2006.257.08:11:39.20/vbbw/8 2006.257.08:11:39.29/xfe/off,on,15.2 2006.257.08:11:39.66/ifatt/23,28,28,28 2006.257.08:11:40.08/fmout-gps/S +4.52E-07 2006.257.08:11:40.12:!2006.257.08:12:25 2006.257.08:12:25.00:data_valid=off 2006.257.08:12:25.00:"et 2006.257.08:12:25.01:!+3s 2006.257.08:12:28.02:"tape 2006.257.08:12:28.02:postob 2006.257.08:12:28.15/cable/+6.4741E-03 2006.257.08:12:28.15/wx/20.83,1012.9,88 2006.257.08:12:28.21/fmout-gps/S +4.53E-07 2006.257.08:12:28.21:scan_name=257-0817,jd0609,40 2006.257.08:12:28.22:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.08:12:29.14#flagr#flagr/antenna,new-source 2006.257.08:12:29.14:checkk5 2006.257.08:12:29.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:12:29.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:12:30.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:12:30.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:12:31.16/chk_obsdata//k5ts1/T2570811??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.08:12:31.58/chk_obsdata//k5ts2/T2570811??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.08:12:31.98/chk_obsdata//k5ts3/T2570811??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.08:12:32.38/chk_obsdata//k5ts4/T2570811??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.08:12:33.10/k5log//k5ts1_log_newline 2006.257.08:12:33.80/k5log//k5ts2_log_newline 2006.257.08:12:34.52/k5log//k5ts3_log_newline 2006.257.08:12:35.21/k5log//k5ts4_log_newline 2006.257.08:12:35.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:12:35.24:setupk4=1 2006.257.08:12:35.24$setupk4/echo=on 2006.257.08:12:35.24$setupk4/pcalon 2006.257.08:12:35.24$pcalon/"no phase cal control is implemented here 2006.257.08:12:35.24$setupk4/"tpicd=stop 2006.257.08:12:35.24$setupk4/"rec=synch_on 2006.257.08:12:35.24$setupk4/"rec_mode=128 2006.257.08:12:35.24$setupk4/!* 2006.257.08:12:35.24$setupk4/recpk4 2006.257.08:12:35.24$recpk4/recpatch= 2006.257.08:12:35.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:12:35.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:12:35.25$setupk4/vck44 2006.257.08:12:35.25$vck44/valo=1,524.99 2006.257.08:12:35.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.08:12:35.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.08:12:35.25#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:35.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:35.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:35.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:35.25#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:12:35.25#ibcon#first serial, iclass 14, count 0 2006.257.08:12:35.25#ibcon#enter sib2, iclass 14, count 0 2006.257.08:12:35.25#ibcon#flushed, iclass 14, count 0 2006.257.08:12:35.25#ibcon#about to write, iclass 14, count 0 2006.257.08:12:35.25#ibcon#wrote, iclass 14, count 0 2006.257.08:12:35.25#ibcon#about to read 3, iclass 14, count 0 2006.257.08:12:35.26#ibcon#read 3, iclass 14, count 0 2006.257.08:12:35.26#ibcon#about to read 4, iclass 14, count 0 2006.257.08:12:35.26#ibcon#read 4, iclass 14, count 0 2006.257.08:12:35.26#ibcon#about to read 5, iclass 14, count 0 2006.257.08:12:35.26#ibcon#read 5, iclass 14, count 0 2006.257.08:12:35.26#ibcon#about to read 6, iclass 14, count 0 2006.257.08:12:35.26#ibcon#read 6, iclass 14, count 0 2006.257.08:12:35.26#ibcon#end of sib2, iclass 14, count 0 2006.257.08:12:35.26#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:12:35.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:12:35.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:12:35.26#ibcon#*before write, iclass 14, count 0 2006.257.08:12:35.26#ibcon#enter sib2, iclass 14, count 0 2006.257.08:12:35.26#ibcon#flushed, iclass 14, count 0 2006.257.08:12:35.26#ibcon#about to write, iclass 14, count 0 2006.257.08:12:35.26#ibcon#wrote, iclass 14, count 0 2006.257.08:12:35.26#ibcon#about to read 3, iclass 14, count 0 2006.257.08:12:35.31#ibcon#read 3, iclass 14, count 0 2006.257.08:12:35.31#ibcon#about to read 4, iclass 14, count 0 2006.257.08:12:35.31#ibcon#read 4, iclass 14, count 0 2006.257.08:12:35.31#ibcon#about to read 5, iclass 14, count 0 2006.257.08:12:35.31#ibcon#read 5, iclass 14, count 0 2006.257.08:12:35.31#ibcon#about to read 6, iclass 14, count 0 2006.257.08:12:35.31#ibcon#read 6, iclass 14, count 0 2006.257.08:12:35.31#ibcon#end of sib2, iclass 14, count 0 2006.257.08:12:35.31#ibcon#*after write, iclass 14, count 0 2006.257.08:12:35.31#ibcon#*before return 0, iclass 14, count 0 2006.257.08:12:35.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:35.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:35.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:12:35.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:12:35.31$vck44/va=1,8 2006.257.08:12:35.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.08:12:35.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.08:12:35.31#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:35.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:35.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:35.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:35.31#ibcon#enter wrdev, iclass 16, count 2 2006.257.08:12:35.31#ibcon#first serial, iclass 16, count 2 2006.257.08:12:35.31#ibcon#enter sib2, iclass 16, count 2 2006.257.08:12:35.31#ibcon#flushed, iclass 16, count 2 2006.257.08:12:35.31#ibcon#about to write, iclass 16, count 2 2006.257.08:12:35.31#ibcon#wrote, iclass 16, count 2 2006.257.08:12:35.31#ibcon#about to read 3, iclass 16, count 2 2006.257.08:12:35.33#ibcon#read 3, iclass 16, count 2 2006.257.08:12:35.33#ibcon#about to read 4, iclass 16, count 2 2006.257.08:12:35.33#ibcon#read 4, iclass 16, count 2 2006.257.08:12:35.33#ibcon#about to read 5, iclass 16, count 2 2006.257.08:12:35.33#ibcon#read 5, iclass 16, count 2 2006.257.08:12:35.33#ibcon#about to read 6, iclass 16, count 2 2006.257.08:12:35.33#ibcon#read 6, iclass 16, count 2 2006.257.08:12:35.33#ibcon#end of sib2, iclass 16, count 2 2006.257.08:12:35.33#ibcon#*mode == 0, iclass 16, count 2 2006.257.08:12:35.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.08:12:35.33#ibcon#[25=AT01-08\r\n] 2006.257.08:12:35.33#ibcon#*before write, iclass 16, count 2 2006.257.08:12:35.33#ibcon#enter sib2, iclass 16, count 2 2006.257.08:12:35.33#ibcon#flushed, iclass 16, count 2 2006.257.08:12:35.33#ibcon#about to write, iclass 16, count 2 2006.257.08:12:35.33#ibcon#wrote, iclass 16, count 2 2006.257.08:12:35.33#ibcon#about to read 3, iclass 16, count 2 2006.257.08:12:35.36#ibcon#read 3, iclass 16, count 2 2006.257.08:12:35.36#ibcon#about to read 4, iclass 16, count 2 2006.257.08:12:35.36#ibcon#read 4, iclass 16, count 2 2006.257.08:12:35.36#ibcon#about to read 5, iclass 16, count 2 2006.257.08:12:35.36#ibcon#read 5, iclass 16, count 2 2006.257.08:12:35.36#ibcon#about to read 6, iclass 16, count 2 2006.257.08:12:35.36#ibcon#read 6, iclass 16, count 2 2006.257.08:12:35.36#ibcon#end of sib2, iclass 16, count 2 2006.257.08:12:35.36#ibcon#*after write, iclass 16, count 2 2006.257.08:12:35.36#ibcon#*before return 0, iclass 16, count 2 2006.257.08:12:35.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:35.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:35.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.08:12:35.36#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:35.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:35.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:35.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:35.48#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:12:35.48#ibcon#first serial, iclass 16, count 0 2006.257.08:12:35.48#ibcon#enter sib2, iclass 16, count 0 2006.257.08:12:35.48#ibcon#flushed, iclass 16, count 0 2006.257.08:12:35.48#ibcon#about to write, iclass 16, count 0 2006.257.08:12:35.48#ibcon#wrote, iclass 16, count 0 2006.257.08:12:35.48#ibcon#about to read 3, iclass 16, count 0 2006.257.08:12:35.50#ibcon#read 3, iclass 16, count 0 2006.257.08:12:35.50#ibcon#about to read 4, iclass 16, count 0 2006.257.08:12:35.50#ibcon#read 4, iclass 16, count 0 2006.257.08:12:35.50#ibcon#about to read 5, iclass 16, count 0 2006.257.08:12:35.50#ibcon#read 5, iclass 16, count 0 2006.257.08:12:35.50#ibcon#about to read 6, iclass 16, count 0 2006.257.08:12:35.50#ibcon#read 6, iclass 16, count 0 2006.257.08:12:35.50#ibcon#end of sib2, iclass 16, count 0 2006.257.08:12:35.50#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:12:35.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:12:35.50#ibcon#[25=USB\r\n] 2006.257.08:12:35.50#ibcon#*before write, iclass 16, count 0 2006.257.08:12:35.50#ibcon#enter sib2, iclass 16, count 0 2006.257.08:12:35.50#ibcon#flushed, iclass 16, count 0 2006.257.08:12:35.50#ibcon#about to write, iclass 16, count 0 2006.257.08:12:35.50#ibcon#wrote, iclass 16, count 0 2006.257.08:12:35.50#ibcon#about to read 3, iclass 16, count 0 2006.257.08:12:35.53#ibcon#read 3, iclass 16, count 0 2006.257.08:12:35.53#ibcon#about to read 4, iclass 16, count 0 2006.257.08:12:35.53#ibcon#read 4, iclass 16, count 0 2006.257.08:12:35.53#ibcon#about to read 5, iclass 16, count 0 2006.257.08:12:35.53#ibcon#read 5, iclass 16, count 0 2006.257.08:12:35.53#ibcon#about to read 6, iclass 16, count 0 2006.257.08:12:35.53#ibcon#read 6, iclass 16, count 0 2006.257.08:12:35.53#ibcon#end of sib2, iclass 16, count 0 2006.257.08:12:35.53#ibcon#*after write, iclass 16, count 0 2006.257.08:12:35.53#ibcon#*before return 0, iclass 16, count 0 2006.257.08:12:35.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:35.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:35.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:12:35.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:12:35.53$vck44/valo=2,534.99 2006.257.08:12:35.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.08:12:35.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.08:12:35.53#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:35.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:35.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:35.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:35.53#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:12:35.53#ibcon#first serial, iclass 18, count 0 2006.257.08:12:35.53#ibcon#enter sib2, iclass 18, count 0 2006.257.08:12:35.53#ibcon#flushed, iclass 18, count 0 2006.257.08:12:35.53#ibcon#about to write, iclass 18, count 0 2006.257.08:12:35.53#ibcon#wrote, iclass 18, count 0 2006.257.08:12:35.53#ibcon#about to read 3, iclass 18, count 0 2006.257.08:12:35.55#ibcon#read 3, iclass 18, count 0 2006.257.08:12:35.55#ibcon#about to read 4, iclass 18, count 0 2006.257.08:12:35.55#ibcon#read 4, iclass 18, count 0 2006.257.08:12:35.55#ibcon#about to read 5, iclass 18, count 0 2006.257.08:12:35.55#ibcon#read 5, iclass 18, count 0 2006.257.08:12:35.55#ibcon#about to read 6, iclass 18, count 0 2006.257.08:12:35.55#ibcon#read 6, iclass 18, count 0 2006.257.08:12:35.55#ibcon#end of sib2, iclass 18, count 0 2006.257.08:12:35.55#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:12:35.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:12:35.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:12:35.55#ibcon#*before write, iclass 18, count 0 2006.257.08:12:35.55#ibcon#enter sib2, iclass 18, count 0 2006.257.08:12:35.55#ibcon#flushed, iclass 18, count 0 2006.257.08:12:35.55#ibcon#about to write, iclass 18, count 0 2006.257.08:12:35.55#ibcon#wrote, iclass 18, count 0 2006.257.08:12:35.55#ibcon#about to read 3, iclass 18, count 0 2006.257.08:12:35.59#ibcon#read 3, iclass 18, count 0 2006.257.08:12:35.59#ibcon#about to read 4, iclass 18, count 0 2006.257.08:12:35.59#ibcon#read 4, iclass 18, count 0 2006.257.08:12:35.59#ibcon#about to read 5, iclass 18, count 0 2006.257.08:12:35.59#ibcon#read 5, iclass 18, count 0 2006.257.08:12:35.59#ibcon#about to read 6, iclass 18, count 0 2006.257.08:12:35.59#ibcon#read 6, iclass 18, count 0 2006.257.08:12:35.59#ibcon#end of sib2, iclass 18, count 0 2006.257.08:12:35.59#ibcon#*after write, iclass 18, count 0 2006.257.08:12:35.59#ibcon#*before return 0, iclass 18, count 0 2006.257.08:12:35.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:35.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:35.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:12:35.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:12:35.59$vck44/va=2,7 2006.257.08:12:35.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.08:12:35.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.08:12:35.59#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:35.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:35.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:35.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:35.65#ibcon#enter wrdev, iclass 20, count 2 2006.257.08:12:35.65#ibcon#first serial, iclass 20, count 2 2006.257.08:12:35.65#ibcon#enter sib2, iclass 20, count 2 2006.257.08:12:35.65#ibcon#flushed, iclass 20, count 2 2006.257.08:12:35.65#ibcon#about to write, iclass 20, count 2 2006.257.08:12:35.65#ibcon#wrote, iclass 20, count 2 2006.257.08:12:35.65#ibcon#about to read 3, iclass 20, count 2 2006.257.08:12:35.67#ibcon#read 3, iclass 20, count 2 2006.257.08:12:35.67#ibcon#about to read 4, iclass 20, count 2 2006.257.08:12:35.67#ibcon#read 4, iclass 20, count 2 2006.257.08:12:35.67#ibcon#about to read 5, iclass 20, count 2 2006.257.08:12:35.67#ibcon#read 5, iclass 20, count 2 2006.257.08:12:35.67#ibcon#about to read 6, iclass 20, count 2 2006.257.08:12:35.67#ibcon#read 6, iclass 20, count 2 2006.257.08:12:35.67#ibcon#end of sib2, iclass 20, count 2 2006.257.08:12:35.67#ibcon#*mode == 0, iclass 20, count 2 2006.257.08:12:35.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.08:12:35.67#ibcon#[25=AT02-07\r\n] 2006.257.08:12:35.67#ibcon#*before write, iclass 20, count 2 2006.257.08:12:35.67#ibcon#enter sib2, iclass 20, count 2 2006.257.08:12:35.67#ibcon#flushed, iclass 20, count 2 2006.257.08:12:35.67#ibcon#about to write, iclass 20, count 2 2006.257.08:12:35.67#ibcon#wrote, iclass 20, count 2 2006.257.08:12:35.67#ibcon#about to read 3, iclass 20, count 2 2006.257.08:12:35.70#ibcon#read 3, iclass 20, count 2 2006.257.08:12:35.70#ibcon#about to read 4, iclass 20, count 2 2006.257.08:12:35.70#ibcon#read 4, iclass 20, count 2 2006.257.08:12:35.70#ibcon#about to read 5, iclass 20, count 2 2006.257.08:12:35.70#ibcon#read 5, iclass 20, count 2 2006.257.08:12:35.70#ibcon#about to read 6, iclass 20, count 2 2006.257.08:12:35.70#ibcon#read 6, iclass 20, count 2 2006.257.08:12:35.70#ibcon#end of sib2, iclass 20, count 2 2006.257.08:12:35.70#ibcon#*after write, iclass 20, count 2 2006.257.08:12:35.70#ibcon#*before return 0, iclass 20, count 2 2006.257.08:12:35.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:35.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:35.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.08:12:35.70#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:35.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:35.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:35.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:35.82#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:12:35.82#ibcon#first serial, iclass 20, count 0 2006.257.08:12:35.82#ibcon#enter sib2, iclass 20, count 0 2006.257.08:12:35.82#ibcon#flushed, iclass 20, count 0 2006.257.08:12:35.82#ibcon#about to write, iclass 20, count 0 2006.257.08:12:35.82#ibcon#wrote, iclass 20, count 0 2006.257.08:12:35.82#ibcon#about to read 3, iclass 20, count 0 2006.257.08:12:35.84#ibcon#read 3, iclass 20, count 0 2006.257.08:12:35.84#ibcon#about to read 4, iclass 20, count 0 2006.257.08:12:35.84#ibcon#read 4, iclass 20, count 0 2006.257.08:12:35.84#ibcon#about to read 5, iclass 20, count 0 2006.257.08:12:35.84#ibcon#read 5, iclass 20, count 0 2006.257.08:12:35.84#ibcon#about to read 6, iclass 20, count 0 2006.257.08:12:35.84#ibcon#read 6, iclass 20, count 0 2006.257.08:12:35.84#ibcon#end of sib2, iclass 20, count 0 2006.257.08:12:35.84#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:12:35.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:12:35.84#ibcon#[25=USB\r\n] 2006.257.08:12:35.84#ibcon#*before write, iclass 20, count 0 2006.257.08:12:35.84#ibcon#enter sib2, iclass 20, count 0 2006.257.08:12:35.84#ibcon#flushed, iclass 20, count 0 2006.257.08:12:35.84#ibcon#about to write, iclass 20, count 0 2006.257.08:12:35.84#ibcon#wrote, iclass 20, count 0 2006.257.08:12:35.84#ibcon#about to read 3, iclass 20, count 0 2006.257.08:12:35.87#ibcon#read 3, iclass 20, count 0 2006.257.08:12:35.87#ibcon#about to read 4, iclass 20, count 0 2006.257.08:12:35.87#ibcon#read 4, iclass 20, count 0 2006.257.08:12:35.87#ibcon#about to read 5, iclass 20, count 0 2006.257.08:12:35.87#ibcon#read 5, iclass 20, count 0 2006.257.08:12:35.87#ibcon#about to read 6, iclass 20, count 0 2006.257.08:12:35.87#ibcon#read 6, iclass 20, count 0 2006.257.08:12:35.87#ibcon#end of sib2, iclass 20, count 0 2006.257.08:12:35.87#ibcon#*after write, iclass 20, count 0 2006.257.08:12:35.87#ibcon#*before return 0, iclass 20, count 0 2006.257.08:12:35.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:35.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:35.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:12:35.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:12:35.87$vck44/valo=3,564.99 2006.257.08:12:35.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.08:12:35.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.08:12:35.87#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:35.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:35.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:35.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:35.87#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:12:35.87#ibcon#first serial, iclass 22, count 0 2006.257.08:12:35.87#ibcon#enter sib2, iclass 22, count 0 2006.257.08:12:35.87#ibcon#flushed, iclass 22, count 0 2006.257.08:12:35.87#ibcon#about to write, iclass 22, count 0 2006.257.08:12:35.87#ibcon#wrote, iclass 22, count 0 2006.257.08:12:35.87#ibcon#about to read 3, iclass 22, count 0 2006.257.08:12:35.89#ibcon#read 3, iclass 22, count 0 2006.257.08:12:35.89#ibcon#about to read 4, iclass 22, count 0 2006.257.08:12:35.89#ibcon#read 4, iclass 22, count 0 2006.257.08:12:35.89#ibcon#about to read 5, iclass 22, count 0 2006.257.08:12:35.89#ibcon#read 5, iclass 22, count 0 2006.257.08:12:35.89#ibcon#about to read 6, iclass 22, count 0 2006.257.08:12:35.89#ibcon#read 6, iclass 22, count 0 2006.257.08:12:35.89#ibcon#end of sib2, iclass 22, count 0 2006.257.08:12:35.89#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:12:35.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:12:35.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:12:35.89#ibcon#*before write, iclass 22, count 0 2006.257.08:12:35.89#ibcon#enter sib2, iclass 22, count 0 2006.257.08:12:35.89#ibcon#flushed, iclass 22, count 0 2006.257.08:12:35.89#ibcon#about to write, iclass 22, count 0 2006.257.08:12:35.89#ibcon#wrote, iclass 22, count 0 2006.257.08:12:35.89#ibcon#about to read 3, iclass 22, count 0 2006.257.08:12:35.93#ibcon#read 3, iclass 22, count 0 2006.257.08:12:35.93#ibcon#about to read 4, iclass 22, count 0 2006.257.08:12:35.93#ibcon#read 4, iclass 22, count 0 2006.257.08:12:35.93#ibcon#about to read 5, iclass 22, count 0 2006.257.08:12:35.93#ibcon#read 5, iclass 22, count 0 2006.257.08:12:35.93#ibcon#about to read 6, iclass 22, count 0 2006.257.08:12:35.93#ibcon#read 6, iclass 22, count 0 2006.257.08:12:35.93#ibcon#end of sib2, iclass 22, count 0 2006.257.08:12:35.93#ibcon#*after write, iclass 22, count 0 2006.257.08:12:35.93#ibcon#*before return 0, iclass 22, count 0 2006.257.08:12:35.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:35.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:35.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:12:35.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:12:35.93$vck44/va=3,8 2006.257.08:12:35.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.08:12:35.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.08:12:35.93#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:35.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:35.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:35.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:35.99#ibcon#enter wrdev, iclass 24, count 2 2006.257.08:12:35.99#ibcon#first serial, iclass 24, count 2 2006.257.08:12:35.99#ibcon#enter sib2, iclass 24, count 2 2006.257.08:12:35.99#ibcon#flushed, iclass 24, count 2 2006.257.08:12:35.99#ibcon#about to write, iclass 24, count 2 2006.257.08:12:35.99#ibcon#wrote, iclass 24, count 2 2006.257.08:12:35.99#ibcon#about to read 3, iclass 24, count 2 2006.257.08:12:36.01#ibcon#read 3, iclass 24, count 2 2006.257.08:12:36.01#ibcon#about to read 4, iclass 24, count 2 2006.257.08:12:36.01#ibcon#read 4, iclass 24, count 2 2006.257.08:12:36.01#ibcon#about to read 5, iclass 24, count 2 2006.257.08:12:36.01#ibcon#read 5, iclass 24, count 2 2006.257.08:12:36.01#ibcon#about to read 6, iclass 24, count 2 2006.257.08:12:36.01#ibcon#read 6, iclass 24, count 2 2006.257.08:12:36.01#ibcon#end of sib2, iclass 24, count 2 2006.257.08:12:36.01#ibcon#*mode == 0, iclass 24, count 2 2006.257.08:12:36.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.08:12:36.01#ibcon#[25=AT03-08\r\n] 2006.257.08:12:36.01#ibcon#*before write, iclass 24, count 2 2006.257.08:12:36.01#ibcon#enter sib2, iclass 24, count 2 2006.257.08:12:36.01#ibcon#flushed, iclass 24, count 2 2006.257.08:12:36.01#ibcon#about to write, iclass 24, count 2 2006.257.08:12:36.01#ibcon#wrote, iclass 24, count 2 2006.257.08:12:36.01#ibcon#about to read 3, iclass 24, count 2 2006.257.08:12:36.04#ibcon#read 3, iclass 24, count 2 2006.257.08:12:36.04#ibcon#about to read 4, iclass 24, count 2 2006.257.08:12:36.04#ibcon#read 4, iclass 24, count 2 2006.257.08:12:36.04#ibcon#about to read 5, iclass 24, count 2 2006.257.08:12:36.04#ibcon#read 5, iclass 24, count 2 2006.257.08:12:36.04#ibcon#about to read 6, iclass 24, count 2 2006.257.08:12:36.04#ibcon#read 6, iclass 24, count 2 2006.257.08:12:36.04#ibcon#end of sib2, iclass 24, count 2 2006.257.08:12:36.04#ibcon#*after write, iclass 24, count 2 2006.257.08:12:36.04#ibcon#*before return 0, iclass 24, count 2 2006.257.08:12:36.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:36.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:36.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.08:12:36.04#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:36.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:36.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:36.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:36.16#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:12:36.16#ibcon#first serial, iclass 24, count 0 2006.257.08:12:36.16#ibcon#enter sib2, iclass 24, count 0 2006.257.08:12:36.16#ibcon#flushed, iclass 24, count 0 2006.257.08:12:36.16#ibcon#about to write, iclass 24, count 0 2006.257.08:12:36.16#ibcon#wrote, iclass 24, count 0 2006.257.08:12:36.16#ibcon#about to read 3, iclass 24, count 0 2006.257.08:12:36.18#ibcon#read 3, iclass 24, count 0 2006.257.08:12:36.18#ibcon#about to read 4, iclass 24, count 0 2006.257.08:12:36.18#ibcon#read 4, iclass 24, count 0 2006.257.08:12:36.18#ibcon#about to read 5, iclass 24, count 0 2006.257.08:12:36.18#ibcon#read 5, iclass 24, count 0 2006.257.08:12:36.18#ibcon#about to read 6, iclass 24, count 0 2006.257.08:12:36.18#ibcon#read 6, iclass 24, count 0 2006.257.08:12:36.18#ibcon#end of sib2, iclass 24, count 0 2006.257.08:12:36.18#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:12:36.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:12:36.18#ibcon#[25=USB\r\n] 2006.257.08:12:36.18#ibcon#*before write, iclass 24, count 0 2006.257.08:12:36.18#ibcon#enter sib2, iclass 24, count 0 2006.257.08:12:36.18#ibcon#flushed, iclass 24, count 0 2006.257.08:12:36.18#ibcon#about to write, iclass 24, count 0 2006.257.08:12:36.18#ibcon#wrote, iclass 24, count 0 2006.257.08:12:36.18#ibcon#about to read 3, iclass 24, count 0 2006.257.08:12:36.21#ibcon#read 3, iclass 24, count 0 2006.257.08:12:36.21#ibcon#about to read 4, iclass 24, count 0 2006.257.08:12:36.21#ibcon#read 4, iclass 24, count 0 2006.257.08:12:36.21#ibcon#about to read 5, iclass 24, count 0 2006.257.08:12:36.21#ibcon#read 5, iclass 24, count 0 2006.257.08:12:36.21#ibcon#about to read 6, iclass 24, count 0 2006.257.08:12:36.21#ibcon#read 6, iclass 24, count 0 2006.257.08:12:36.21#ibcon#end of sib2, iclass 24, count 0 2006.257.08:12:36.21#ibcon#*after write, iclass 24, count 0 2006.257.08:12:36.21#ibcon#*before return 0, iclass 24, count 0 2006.257.08:12:36.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:36.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:36.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:12:36.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:12:36.21$vck44/valo=4,624.99 2006.257.08:12:36.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.08:12:36.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.08:12:36.21#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:36.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:36.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:36.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:36.21#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:12:36.21#ibcon#first serial, iclass 26, count 0 2006.257.08:12:36.21#ibcon#enter sib2, iclass 26, count 0 2006.257.08:12:36.21#ibcon#flushed, iclass 26, count 0 2006.257.08:12:36.21#ibcon#about to write, iclass 26, count 0 2006.257.08:12:36.21#ibcon#wrote, iclass 26, count 0 2006.257.08:12:36.21#ibcon#about to read 3, iclass 26, count 0 2006.257.08:12:36.23#ibcon#read 3, iclass 26, count 0 2006.257.08:12:36.23#ibcon#about to read 4, iclass 26, count 0 2006.257.08:12:36.23#ibcon#read 4, iclass 26, count 0 2006.257.08:12:36.23#ibcon#about to read 5, iclass 26, count 0 2006.257.08:12:36.23#ibcon#read 5, iclass 26, count 0 2006.257.08:12:36.23#ibcon#about to read 6, iclass 26, count 0 2006.257.08:12:36.23#ibcon#read 6, iclass 26, count 0 2006.257.08:12:36.23#ibcon#end of sib2, iclass 26, count 0 2006.257.08:12:36.23#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:12:36.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:12:36.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:12:36.23#ibcon#*before write, iclass 26, count 0 2006.257.08:12:36.23#ibcon#enter sib2, iclass 26, count 0 2006.257.08:12:36.23#ibcon#flushed, iclass 26, count 0 2006.257.08:12:36.23#ibcon#about to write, iclass 26, count 0 2006.257.08:12:36.23#ibcon#wrote, iclass 26, count 0 2006.257.08:12:36.23#ibcon#about to read 3, iclass 26, count 0 2006.257.08:12:36.27#ibcon#read 3, iclass 26, count 0 2006.257.08:12:36.27#ibcon#about to read 4, iclass 26, count 0 2006.257.08:12:36.27#ibcon#read 4, iclass 26, count 0 2006.257.08:12:36.27#ibcon#about to read 5, iclass 26, count 0 2006.257.08:12:36.27#ibcon#read 5, iclass 26, count 0 2006.257.08:12:36.27#ibcon#about to read 6, iclass 26, count 0 2006.257.08:12:36.27#ibcon#read 6, iclass 26, count 0 2006.257.08:12:36.27#ibcon#end of sib2, iclass 26, count 0 2006.257.08:12:36.27#ibcon#*after write, iclass 26, count 0 2006.257.08:12:36.27#ibcon#*before return 0, iclass 26, count 0 2006.257.08:12:36.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:36.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:36.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:12:36.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:12:36.27$vck44/va=4,7 2006.257.08:12:36.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.08:12:36.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.08:12:36.27#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:36.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:36.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:36.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:36.33#ibcon#enter wrdev, iclass 28, count 2 2006.257.08:12:36.33#ibcon#first serial, iclass 28, count 2 2006.257.08:12:36.33#ibcon#enter sib2, iclass 28, count 2 2006.257.08:12:36.33#ibcon#flushed, iclass 28, count 2 2006.257.08:12:36.33#ibcon#about to write, iclass 28, count 2 2006.257.08:12:36.33#ibcon#wrote, iclass 28, count 2 2006.257.08:12:36.33#ibcon#about to read 3, iclass 28, count 2 2006.257.08:12:36.35#ibcon#read 3, iclass 28, count 2 2006.257.08:12:36.35#ibcon#about to read 4, iclass 28, count 2 2006.257.08:12:36.35#ibcon#read 4, iclass 28, count 2 2006.257.08:12:36.35#ibcon#about to read 5, iclass 28, count 2 2006.257.08:12:36.35#ibcon#read 5, iclass 28, count 2 2006.257.08:12:36.35#ibcon#about to read 6, iclass 28, count 2 2006.257.08:12:36.35#ibcon#read 6, iclass 28, count 2 2006.257.08:12:36.35#ibcon#end of sib2, iclass 28, count 2 2006.257.08:12:36.35#ibcon#*mode == 0, iclass 28, count 2 2006.257.08:12:36.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.08:12:36.35#ibcon#[25=AT04-07\r\n] 2006.257.08:12:36.35#ibcon#*before write, iclass 28, count 2 2006.257.08:12:36.35#ibcon#enter sib2, iclass 28, count 2 2006.257.08:12:36.35#ibcon#flushed, iclass 28, count 2 2006.257.08:12:36.35#ibcon#about to write, iclass 28, count 2 2006.257.08:12:36.35#ibcon#wrote, iclass 28, count 2 2006.257.08:12:36.35#ibcon#about to read 3, iclass 28, count 2 2006.257.08:12:36.38#ibcon#read 3, iclass 28, count 2 2006.257.08:12:36.38#ibcon#about to read 4, iclass 28, count 2 2006.257.08:12:36.38#ibcon#read 4, iclass 28, count 2 2006.257.08:12:36.38#ibcon#about to read 5, iclass 28, count 2 2006.257.08:12:36.38#ibcon#read 5, iclass 28, count 2 2006.257.08:12:36.38#ibcon#about to read 6, iclass 28, count 2 2006.257.08:12:36.38#ibcon#read 6, iclass 28, count 2 2006.257.08:12:36.38#ibcon#end of sib2, iclass 28, count 2 2006.257.08:12:36.38#ibcon#*after write, iclass 28, count 2 2006.257.08:12:36.40#ibcon#*before return 0, iclass 28, count 2 2006.257.08:12:36.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:36.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:36.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.08:12:36.40#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:36.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:36.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:36.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:36.52#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:12:36.52#ibcon#first serial, iclass 28, count 0 2006.257.08:12:36.52#ibcon#enter sib2, iclass 28, count 0 2006.257.08:12:36.52#ibcon#flushed, iclass 28, count 0 2006.257.08:12:36.52#ibcon#about to write, iclass 28, count 0 2006.257.08:12:36.52#ibcon#wrote, iclass 28, count 0 2006.257.08:12:36.52#ibcon#about to read 3, iclass 28, count 0 2006.257.08:12:36.54#ibcon#read 3, iclass 28, count 0 2006.257.08:12:36.54#ibcon#about to read 4, iclass 28, count 0 2006.257.08:12:36.54#ibcon#read 4, iclass 28, count 0 2006.257.08:12:36.54#ibcon#about to read 5, iclass 28, count 0 2006.257.08:12:36.54#ibcon#read 5, iclass 28, count 0 2006.257.08:12:36.54#ibcon#about to read 6, iclass 28, count 0 2006.257.08:12:36.54#ibcon#read 6, iclass 28, count 0 2006.257.08:12:36.54#ibcon#end of sib2, iclass 28, count 0 2006.257.08:12:36.54#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:12:36.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:12:36.54#ibcon#[25=USB\r\n] 2006.257.08:12:36.54#ibcon#*before write, iclass 28, count 0 2006.257.08:12:36.54#ibcon#enter sib2, iclass 28, count 0 2006.257.08:12:36.54#ibcon#flushed, iclass 28, count 0 2006.257.08:12:36.54#ibcon#about to write, iclass 28, count 0 2006.257.08:12:36.54#ibcon#wrote, iclass 28, count 0 2006.257.08:12:36.54#ibcon#about to read 3, iclass 28, count 0 2006.257.08:12:36.57#ibcon#read 3, iclass 28, count 0 2006.257.08:12:36.57#ibcon#about to read 4, iclass 28, count 0 2006.257.08:12:36.57#ibcon#read 4, iclass 28, count 0 2006.257.08:12:36.57#ibcon#about to read 5, iclass 28, count 0 2006.257.08:12:36.57#ibcon#read 5, iclass 28, count 0 2006.257.08:12:36.57#ibcon#about to read 6, iclass 28, count 0 2006.257.08:12:36.57#ibcon#read 6, iclass 28, count 0 2006.257.08:12:36.57#ibcon#end of sib2, iclass 28, count 0 2006.257.08:12:36.57#ibcon#*after write, iclass 28, count 0 2006.257.08:12:36.57#ibcon#*before return 0, iclass 28, count 0 2006.257.08:12:36.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:36.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:36.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:12:36.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:12:36.57$vck44/valo=5,734.99 2006.257.08:12:36.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.08:12:36.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.08:12:36.57#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:36.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:36.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:36.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:36.57#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:12:36.57#ibcon#first serial, iclass 30, count 0 2006.257.08:12:36.57#ibcon#enter sib2, iclass 30, count 0 2006.257.08:12:36.57#ibcon#flushed, iclass 30, count 0 2006.257.08:12:36.57#ibcon#about to write, iclass 30, count 0 2006.257.08:12:36.57#ibcon#wrote, iclass 30, count 0 2006.257.08:12:36.57#ibcon#about to read 3, iclass 30, count 0 2006.257.08:12:36.59#ibcon#read 3, iclass 30, count 0 2006.257.08:12:36.59#ibcon#about to read 4, iclass 30, count 0 2006.257.08:12:36.59#ibcon#read 4, iclass 30, count 0 2006.257.08:12:36.59#ibcon#about to read 5, iclass 30, count 0 2006.257.08:12:36.59#ibcon#read 5, iclass 30, count 0 2006.257.08:12:36.59#ibcon#about to read 6, iclass 30, count 0 2006.257.08:12:36.59#ibcon#read 6, iclass 30, count 0 2006.257.08:12:36.59#ibcon#end of sib2, iclass 30, count 0 2006.257.08:12:36.59#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:12:36.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:12:36.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:12:36.59#ibcon#*before write, iclass 30, count 0 2006.257.08:12:36.59#ibcon#enter sib2, iclass 30, count 0 2006.257.08:12:36.59#ibcon#flushed, iclass 30, count 0 2006.257.08:12:36.59#ibcon#about to write, iclass 30, count 0 2006.257.08:12:36.59#ibcon#wrote, iclass 30, count 0 2006.257.08:12:36.59#ibcon#about to read 3, iclass 30, count 0 2006.257.08:12:36.63#ibcon#read 3, iclass 30, count 0 2006.257.08:12:36.63#ibcon#about to read 4, iclass 30, count 0 2006.257.08:12:36.63#ibcon#read 4, iclass 30, count 0 2006.257.08:12:36.63#ibcon#about to read 5, iclass 30, count 0 2006.257.08:12:36.63#ibcon#read 5, iclass 30, count 0 2006.257.08:12:36.63#ibcon#about to read 6, iclass 30, count 0 2006.257.08:12:36.63#ibcon#read 6, iclass 30, count 0 2006.257.08:12:36.63#ibcon#end of sib2, iclass 30, count 0 2006.257.08:12:36.63#ibcon#*after write, iclass 30, count 0 2006.257.08:12:36.63#ibcon#*before return 0, iclass 30, count 0 2006.257.08:12:36.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:36.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:36.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:12:36.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:12:36.63$vck44/va=5,4 2006.257.08:12:36.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.08:12:36.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.08:12:36.63#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:36.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:36.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:36.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:36.69#ibcon#enter wrdev, iclass 32, count 2 2006.257.08:12:36.69#ibcon#first serial, iclass 32, count 2 2006.257.08:12:36.69#ibcon#enter sib2, iclass 32, count 2 2006.257.08:12:36.69#ibcon#flushed, iclass 32, count 2 2006.257.08:12:36.69#ibcon#about to write, iclass 32, count 2 2006.257.08:12:36.69#ibcon#wrote, iclass 32, count 2 2006.257.08:12:36.69#ibcon#about to read 3, iclass 32, count 2 2006.257.08:12:36.71#ibcon#read 3, iclass 32, count 2 2006.257.08:12:36.71#ibcon#about to read 4, iclass 32, count 2 2006.257.08:12:36.71#ibcon#read 4, iclass 32, count 2 2006.257.08:12:36.71#ibcon#about to read 5, iclass 32, count 2 2006.257.08:12:36.71#ibcon#read 5, iclass 32, count 2 2006.257.08:12:36.71#ibcon#about to read 6, iclass 32, count 2 2006.257.08:12:36.71#ibcon#read 6, iclass 32, count 2 2006.257.08:12:36.71#ibcon#end of sib2, iclass 32, count 2 2006.257.08:12:36.71#ibcon#*mode == 0, iclass 32, count 2 2006.257.08:12:36.71#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.08:12:36.71#ibcon#[25=AT05-04\r\n] 2006.257.08:12:36.71#ibcon#*before write, iclass 32, count 2 2006.257.08:12:36.71#ibcon#enter sib2, iclass 32, count 2 2006.257.08:12:36.71#ibcon#flushed, iclass 32, count 2 2006.257.08:12:36.71#ibcon#about to write, iclass 32, count 2 2006.257.08:12:36.71#ibcon#wrote, iclass 32, count 2 2006.257.08:12:36.71#ibcon#about to read 3, iclass 32, count 2 2006.257.08:12:36.74#ibcon#read 3, iclass 32, count 2 2006.257.08:12:36.74#ibcon#about to read 4, iclass 32, count 2 2006.257.08:12:36.74#ibcon#read 4, iclass 32, count 2 2006.257.08:12:36.74#ibcon#about to read 5, iclass 32, count 2 2006.257.08:12:36.74#ibcon#read 5, iclass 32, count 2 2006.257.08:12:36.74#ibcon#about to read 6, iclass 32, count 2 2006.257.08:12:36.74#ibcon#read 6, iclass 32, count 2 2006.257.08:12:36.74#ibcon#end of sib2, iclass 32, count 2 2006.257.08:12:36.74#ibcon#*after write, iclass 32, count 2 2006.257.08:12:36.74#ibcon#*before return 0, iclass 32, count 2 2006.257.08:12:36.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:36.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:36.74#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.08:12:36.74#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:36.74#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:36.86#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:36.86#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:36.86#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:12:36.86#ibcon#first serial, iclass 32, count 0 2006.257.08:12:36.86#ibcon#enter sib2, iclass 32, count 0 2006.257.08:12:36.86#ibcon#flushed, iclass 32, count 0 2006.257.08:12:36.86#ibcon#about to write, iclass 32, count 0 2006.257.08:12:36.86#ibcon#wrote, iclass 32, count 0 2006.257.08:12:36.86#ibcon#about to read 3, iclass 32, count 0 2006.257.08:12:36.88#ibcon#read 3, iclass 32, count 0 2006.257.08:12:36.88#ibcon#about to read 4, iclass 32, count 0 2006.257.08:12:36.88#ibcon#read 4, iclass 32, count 0 2006.257.08:12:36.88#ibcon#about to read 5, iclass 32, count 0 2006.257.08:12:36.88#ibcon#read 5, iclass 32, count 0 2006.257.08:12:36.88#ibcon#about to read 6, iclass 32, count 0 2006.257.08:12:36.88#ibcon#read 6, iclass 32, count 0 2006.257.08:12:36.88#ibcon#end of sib2, iclass 32, count 0 2006.257.08:12:36.88#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:12:36.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:12:36.88#ibcon#[25=USB\r\n] 2006.257.08:12:36.88#ibcon#*before write, iclass 32, count 0 2006.257.08:12:36.88#ibcon#enter sib2, iclass 32, count 0 2006.257.08:12:36.88#ibcon#flushed, iclass 32, count 0 2006.257.08:12:36.88#ibcon#about to write, iclass 32, count 0 2006.257.08:12:36.88#ibcon#wrote, iclass 32, count 0 2006.257.08:12:36.88#ibcon#about to read 3, iclass 32, count 0 2006.257.08:12:36.91#ibcon#read 3, iclass 32, count 0 2006.257.08:12:36.91#ibcon#about to read 4, iclass 32, count 0 2006.257.08:12:36.91#ibcon#read 4, iclass 32, count 0 2006.257.08:12:36.91#ibcon#about to read 5, iclass 32, count 0 2006.257.08:12:36.91#ibcon#read 5, iclass 32, count 0 2006.257.08:12:36.91#ibcon#about to read 6, iclass 32, count 0 2006.257.08:12:36.91#ibcon#read 6, iclass 32, count 0 2006.257.08:12:36.91#ibcon#end of sib2, iclass 32, count 0 2006.257.08:12:36.91#ibcon#*after write, iclass 32, count 0 2006.257.08:12:36.91#ibcon#*before return 0, iclass 32, count 0 2006.257.08:12:36.91#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:36.91#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:36.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:12:36.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:12:36.91$vck44/valo=6,814.99 2006.257.08:12:36.91#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.08:12:36.91#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.08:12:36.91#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:36.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:36.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:36.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:36.91#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:12:36.91#ibcon#first serial, iclass 34, count 0 2006.257.08:12:36.91#ibcon#enter sib2, iclass 34, count 0 2006.257.08:12:36.91#ibcon#flushed, iclass 34, count 0 2006.257.08:12:36.91#ibcon#about to write, iclass 34, count 0 2006.257.08:12:36.91#ibcon#wrote, iclass 34, count 0 2006.257.08:12:36.91#ibcon#about to read 3, iclass 34, count 0 2006.257.08:12:36.93#ibcon#read 3, iclass 34, count 0 2006.257.08:12:36.93#ibcon#about to read 4, iclass 34, count 0 2006.257.08:12:36.93#ibcon#read 4, iclass 34, count 0 2006.257.08:12:36.93#ibcon#about to read 5, iclass 34, count 0 2006.257.08:12:36.93#ibcon#read 5, iclass 34, count 0 2006.257.08:12:36.93#ibcon#about to read 6, iclass 34, count 0 2006.257.08:12:36.93#ibcon#read 6, iclass 34, count 0 2006.257.08:12:36.93#ibcon#end of sib2, iclass 34, count 0 2006.257.08:12:36.93#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:12:36.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:12:36.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:12:36.93#ibcon#*before write, iclass 34, count 0 2006.257.08:12:36.93#ibcon#enter sib2, iclass 34, count 0 2006.257.08:12:36.93#ibcon#flushed, iclass 34, count 0 2006.257.08:12:36.93#ibcon#about to write, iclass 34, count 0 2006.257.08:12:36.93#ibcon#wrote, iclass 34, count 0 2006.257.08:12:36.93#ibcon#about to read 3, iclass 34, count 0 2006.257.08:12:36.97#ibcon#read 3, iclass 34, count 0 2006.257.08:12:36.97#ibcon#about to read 4, iclass 34, count 0 2006.257.08:12:36.97#ibcon#read 4, iclass 34, count 0 2006.257.08:12:36.97#ibcon#about to read 5, iclass 34, count 0 2006.257.08:12:36.97#ibcon#read 5, iclass 34, count 0 2006.257.08:12:36.97#ibcon#about to read 6, iclass 34, count 0 2006.257.08:12:36.97#ibcon#read 6, iclass 34, count 0 2006.257.08:12:36.97#ibcon#end of sib2, iclass 34, count 0 2006.257.08:12:36.97#ibcon#*after write, iclass 34, count 0 2006.257.08:12:36.97#ibcon#*before return 0, iclass 34, count 0 2006.257.08:12:36.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:36.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:36.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:12:36.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:12:36.97$vck44/va=6,4 2006.257.08:12:36.97#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.08:12:36.97#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.08:12:36.97#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:36.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:37.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:37.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:37.03#ibcon#enter wrdev, iclass 36, count 2 2006.257.08:12:37.03#ibcon#first serial, iclass 36, count 2 2006.257.08:12:37.03#ibcon#enter sib2, iclass 36, count 2 2006.257.08:12:37.03#ibcon#flushed, iclass 36, count 2 2006.257.08:12:37.03#ibcon#about to write, iclass 36, count 2 2006.257.08:12:37.03#ibcon#wrote, iclass 36, count 2 2006.257.08:12:37.03#ibcon#about to read 3, iclass 36, count 2 2006.257.08:12:37.05#ibcon#read 3, iclass 36, count 2 2006.257.08:12:37.05#ibcon#about to read 4, iclass 36, count 2 2006.257.08:12:37.05#ibcon#read 4, iclass 36, count 2 2006.257.08:12:37.05#ibcon#about to read 5, iclass 36, count 2 2006.257.08:12:37.05#ibcon#read 5, iclass 36, count 2 2006.257.08:12:37.05#ibcon#about to read 6, iclass 36, count 2 2006.257.08:12:37.05#ibcon#read 6, iclass 36, count 2 2006.257.08:12:37.05#ibcon#end of sib2, iclass 36, count 2 2006.257.08:12:37.05#ibcon#*mode == 0, iclass 36, count 2 2006.257.08:12:37.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.08:12:37.05#ibcon#[25=AT06-04\r\n] 2006.257.08:12:37.05#ibcon#*before write, iclass 36, count 2 2006.257.08:12:37.05#ibcon#enter sib2, iclass 36, count 2 2006.257.08:12:37.05#ibcon#flushed, iclass 36, count 2 2006.257.08:12:37.05#ibcon#about to write, iclass 36, count 2 2006.257.08:12:37.05#ibcon#wrote, iclass 36, count 2 2006.257.08:12:37.05#ibcon#about to read 3, iclass 36, count 2 2006.257.08:12:37.08#ibcon#read 3, iclass 36, count 2 2006.257.08:12:37.08#ibcon#about to read 4, iclass 36, count 2 2006.257.08:12:37.08#ibcon#read 4, iclass 36, count 2 2006.257.08:12:37.08#ibcon#about to read 5, iclass 36, count 2 2006.257.08:12:37.08#ibcon#read 5, iclass 36, count 2 2006.257.08:12:37.08#ibcon#about to read 6, iclass 36, count 2 2006.257.08:12:37.08#ibcon#read 6, iclass 36, count 2 2006.257.08:12:37.08#ibcon#end of sib2, iclass 36, count 2 2006.257.08:12:37.08#ibcon#*after write, iclass 36, count 2 2006.257.08:12:37.08#ibcon#*before return 0, iclass 36, count 2 2006.257.08:12:37.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:37.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:37.08#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.08:12:37.08#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:37.08#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:37.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:37.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:37.20#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:12:37.20#ibcon#first serial, iclass 36, count 0 2006.257.08:12:37.20#ibcon#enter sib2, iclass 36, count 0 2006.257.08:12:37.20#ibcon#flushed, iclass 36, count 0 2006.257.08:12:37.20#ibcon#about to write, iclass 36, count 0 2006.257.08:12:37.20#ibcon#wrote, iclass 36, count 0 2006.257.08:12:37.20#ibcon#about to read 3, iclass 36, count 0 2006.257.08:12:37.22#ibcon#read 3, iclass 36, count 0 2006.257.08:12:37.22#ibcon#about to read 4, iclass 36, count 0 2006.257.08:12:37.22#ibcon#read 4, iclass 36, count 0 2006.257.08:12:37.22#ibcon#about to read 5, iclass 36, count 0 2006.257.08:12:37.22#ibcon#read 5, iclass 36, count 0 2006.257.08:12:37.22#ibcon#about to read 6, iclass 36, count 0 2006.257.08:12:37.22#ibcon#read 6, iclass 36, count 0 2006.257.08:12:37.22#ibcon#end of sib2, iclass 36, count 0 2006.257.08:12:37.22#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:12:37.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:12:37.22#ibcon#[25=USB\r\n] 2006.257.08:12:37.22#ibcon#*before write, iclass 36, count 0 2006.257.08:12:37.22#ibcon#enter sib2, iclass 36, count 0 2006.257.08:12:37.22#ibcon#flushed, iclass 36, count 0 2006.257.08:12:37.22#ibcon#about to write, iclass 36, count 0 2006.257.08:12:37.22#ibcon#wrote, iclass 36, count 0 2006.257.08:12:37.22#ibcon#about to read 3, iclass 36, count 0 2006.257.08:12:37.25#ibcon#read 3, iclass 36, count 0 2006.257.08:12:37.25#ibcon#about to read 4, iclass 36, count 0 2006.257.08:12:37.25#ibcon#read 4, iclass 36, count 0 2006.257.08:12:37.25#ibcon#about to read 5, iclass 36, count 0 2006.257.08:12:37.25#ibcon#read 5, iclass 36, count 0 2006.257.08:12:37.25#ibcon#about to read 6, iclass 36, count 0 2006.257.08:12:37.25#ibcon#read 6, iclass 36, count 0 2006.257.08:12:37.25#ibcon#end of sib2, iclass 36, count 0 2006.257.08:12:37.25#ibcon#*after write, iclass 36, count 0 2006.257.08:12:37.25#ibcon#*before return 0, iclass 36, count 0 2006.257.08:12:37.25#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:37.25#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:37.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:12:37.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:12:37.25$vck44/valo=7,864.99 2006.257.08:12:37.25#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.08:12:37.25#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.08:12:37.25#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:37.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:37.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:37.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:37.25#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:12:37.25#ibcon#first serial, iclass 38, count 0 2006.257.08:12:37.25#ibcon#enter sib2, iclass 38, count 0 2006.257.08:12:37.25#ibcon#flushed, iclass 38, count 0 2006.257.08:12:37.25#ibcon#about to write, iclass 38, count 0 2006.257.08:12:37.25#ibcon#wrote, iclass 38, count 0 2006.257.08:12:37.25#ibcon#about to read 3, iclass 38, count 0 2006.257.08:12:37.27#ibcon#read 3, iclass 38, count 0 2006.257.08:12:37.27#ibcon#about to read 4, iclass 38, count 0 2006.257.08:12:37.27#ibcon#read 4, iclass 38, count 0 2006.257.08:12:37.27#ibcon#about to read 5, iclass 38, count 0 2006.257.08:12:37.27#ibcon#read 5, iclass 38, count 0 2006.257.08:12:37.27#ibcon#about to read 6, iclass 38, count 0 2006.257.08:12:37.27#ibcon#read 6, iclass 38, count 0 2006.257.08:12:37.27#ibcon#end of sib2, iclass 38, count 0 2006.257.08:12:37.27#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:12:37.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:12:37.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:12:37.27#ibcon#*before write, iclass 38, count 0 2006.257.08:12:37.27#ibcon#enter sib2, iclass 38, count 0 2006.257.08:12:37.27#ibcon#flushed, iclass 38, count 0 2006.257.08:12:37.27#ibcon#about to write, iclass 38, count 0 2006.257.08:12:37.27#ibcon#wrote, iclass 38, count 0 2006.257.08:12:37.27#ibcon#about to read 3, iclass 38, count 0 2006.257.08:12:37.31#ibcon#read 3, iclass 38, count 0 2006.257.08:12:37.31#ibcon#about to read 4, iclass 38, count 0 2006.257.08:12:37.31#ibcon#read 4, iclass 38, count 0 2006.257.08:12:37.31#ibcon#about to read 5, iclass 38, count 0 2006.257.08:12:37.31#ibcon#read 5, iclass 38, count 0 2006.257.08:12:37.31#ibcon#about to read 6, iclass 38, count 0 2006.257.08:12:37.31#ibcon#read 6, iclass 38, count 0 2006.257.08:12:37.31#ibcon#end of sib2, iclass 38, count 0 2006.257.08:12:37.31#ibcon#*after write, iclass 38, count 0 2006.257.08:12:37.31#ibcon#*before return 0, iclass 38, count 0 2006.257.08:12:37.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:37.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:37.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:12:37.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:12:37.31$vck44/va=7,4 2006.257.08:12:37.31#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.08:12:37.31#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.08:12:37.31#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:37.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:37.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:37.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:37.37#ibcon#enter wrdev, iclass 40, count 2 2006.257.08:12:37.37#ibcon#first serial, iclass 40, count 2 2006.257.08:12:37.37#ibcon#enter sib2, iclass 40, count 2 2006.257.08:12:37.37#ibcon#flushed, iclass 40, count 2 2006.257.08:12:37.37#ibcon#about to write, iclass 40, count 2 2006.257.08:12:37.37#ibcon#wrote, iclass 40, count 2 2006.257.08:12:37.37#ibcon#about to read 3, iclass 40, count 2 2006.257.08:12:37.39#ibcon#read 3, iclass 40, count 2 2006.257.08:12:37.39#ibcon#about to read 4, iclass 40, count 2 2006.257.08:12:37.39#ibcon#read 4, iclass 40, count 2 2006.257.08:12:37.39#ibcon#about to read 5, iclass 40, count 2 2006.257.08:12:37.39#ibcon#read 5, iclass 40, count 2 2006.257.08:12:37.39#ibcon#about to read 6, iclass 40, count 2 2006.257.08:12:37.39#ibcon#read 6, iclass 40, count 2 2006.257.08:12:37.39#ibcon#end of sib2, iclass 40, count 2 2006.257.08:12:37.39#ibcon#*mode == 0, iclass 40, count 2 2006.257.08:12:37.39#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.08:12:37.39#ibcon#[25=AT07-04\r\n] 2006.257.08:12:37.39#ibcon#*before write, iclass 40, count 2 2006.257.08:12:37.39#ibcon#enter sib2, iclass 40, count 2 2006.257.08:12:37.39#ibcon#flushed, iclass 40, count 2 2006.257.08:12:37.39#ibcon#about to write, iclass 40, count 2 2006.257.08:12:37.39#ibcon#wrote, iclass 40, count 2 2006.257.08:12:37.39#ibcon#about to read 3, iclass 40, count 2 2006.257.08:12:37.42#ibcon#read 3, iclass 40, count 2 2006.257.08:12:37.42#ibcon#about to read 4, iclass 40, count 2 2006.257.08:12:37.42#ibcon#read 4, iclass 40, count 2 2006.257.08:12:37.42#ibcon#about to read 5, iclass 40, count 2 2006.257.08:12:37.42#ibcon#read 5, iclass 40, count 2 2006.257.08:12:37.42#ibcon#about to read 6, iclass 40, count 2 2006.257.08:12:37.42#ibcon#read 6, iclass 40, count 2 2006.257.08:12:37.42#ibcon#end of sib2, iclass 40, count 2 2006.257.08:12:37.42#ibcon#*after write, iclass 40, count 2 2006.257.08:12:37.42#ibcon#*before return 0, iclass 40, count 2 2006.257.08:12:37.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:37.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:37.42#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.08:12:37.42#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:37.42#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:37.54#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:37.54#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:37.54#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:12:37.54#ibcon#first serial, iclass 40, count 0 2006.257.08:12:37.54#ibcon#enter sib2, iclass 40, count 0 2006.257.08:12:37.54#ibcon#flushed, iclass 40, count 0 2006.257.08:12:37.54#ibcon#about to write, iclass 40, count 0 2006.257.08:12:37.54#ibcon#wrote, iclass 40, count 0 2006.257.08:12:37.54#ibcon#about to read 3, iclass 40, count 0 2006.257.08:12:37.56#ibcon#read 3, iclass 40, count 0 2006.257.08:12:37.56#ibcon#about to read 4, iclass 40, count 0 2006.257.08:12:37.56#ibcon#read 4, iclass 40, count 0 2006.257.08:12:37.56#ibcon#about to read 5, iclass 40, count 0 2006.257.08:12:37.56#ibcon#read 5, iclass 40, count 0 2006.257.08:12:37.56#ibcon#about to read 6, iclass 40, count 0 2006.257.08:12:37.56#ibcon#read 6, iclass 40, count 0 2006.257.08:12:37.56#ibcon#end of sib2, iclass 40, count 0 2006.257.08:12:37.56#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:12:37.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:12:37.56#ibcon#[25=USB\r\n] 2006.257.08:12:37.56#ibcon#*before write, iclass 40, count 0 2006.257.08:12:37.56#ibcon#enter sib2, iclass 40, count 0 2006.257.08:12:37.56#ibcon#flushed, iclass 40, count 0 2006.257.08:12:37.56#ibcon#about to write, iclass 40, count 0 2006.257.08:12:37.56#ibcon#wrote, iclass 40, count 0 2006.257.08:12:37.56#ibcon#about to read 3, iclass 40, count 0 2006.257.08:12:37.59#ibcon#read 3, iclass 40, count 0 2006.257.08:12:37.59#ibcon#about to read 4, iclass 40, count 0 2006.257.08:12:37.59#ibcon#read 4, iclass 40, count 0 2006.257.08:12:37.59#ibcon#about to read 5, iclass 40, count 0 2006.257.08:12:37.59#ibcon#read 5, iclass 40, count 0 2006.257.08:12:37.59#ibcon#about to read 6, iclass 40, count 0 2006.257.08:12:37.59#ibcon#read 6, iclass 40, count 0 2006.257.08:12:37.59#ibcon#end of sib2, iclass 40, count 0 2006.257.08:12:37.59#ibcon#*after write, iclass 40, count 0 2006.257.08:12:37.59#ibcon#*before return 0, iclass 40, count 0 2006.257.08:12:37.59#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:37.59#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:37.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:12:37.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:12:37.59$vck44/valo=8,884.99 2006.257.08:12:37.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.08:12:37.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.08:12:37.59#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:37.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:12:37.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:12:37.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:12:37.59#ibcon#enter wrdev, iclass 5, count 0 2006.257.08:12:37.59#ibcon#first serial, iclass 5, count 0 2006.257.08:12:37.59#ibcon#enter sib2, iclass 5, count 0 2006.257.08:12:37.59#ibcon#flushed, iclass 5, count 0 2006.257.08:12:37.59#ibcon#about to write, iclass 5, count 0 2006.257.08:12:37.59#ibcon#wrote, iclass 5, count 0 2006.257.08:12:37.59#ibcon#about to read 3, iclass 5, count 0 2006.257.08:12:37.61#ibcon#read 3, iclass 5, count 0 2006.257.08:12:37.61#ibcon#about to read 4, iclass 5, count 0 2006.257.08:12:37.61#ibcon#read 4, iclass 5, count 0 2006.257.08:12:37.61#ibcon#about to read 5, iclass 5, count 0 2006.257.08:12:37.61#ibcon#read 5, iclass 5, count 0 2006.257.08:12:37.61#ibcon#about to read 6, iclass 5, count 0 2006.257.08:12:37.61#ibcon#read 6, iclass 5, count 0 2006.257.08:12:37.61#ibcon#end of sib2, iclass 5, count 0 2006.257.08:12:37.61#ibcon#*mode == 0, iclass 5, count 0 2006.257.08:12:37.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.08:12:37.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:12:37.61#ibcon#*before write, iclass 5, count 0 2006.257.08:12:37.61#ibcon#enter sib2, iclass 5, count 0 2006.257.08:12:37.61#ibcon#flushed, iclass 5, count 0 2006.257.08:12:37.61#ibcon#about to write, iclass 5, count 0 2006.257.08:12:37.61#ibcon#wrote, iclass 5, count 0 2006.257.08:12:37.61#ibcon#about to read 3, iclass 5, count 0 2006.257.08:12:37.64#abcon#<5=/16 1.5 6.2 20.83 881012.9\r\n> 2006.257.08:12:37.65#ibcon#read 3, iclass 5, count 0 2006.257.08:12:37.65#ibcon#about to read 4, iclass 5, count 0 2006.257.08:12:37.65#ibcon#read 4, iclass 5, count 0 2006.257.08:12:37.65#ibcon#about to read 5, iclass 5, count 0 2006.257.08:12:37.65#ibcon#read 5, iclass 5, count 0 2006.257.08:12:37.65#ibcon#about to read 6, iclass 5, count 0 2006.257.08:12:37.65#ibcon#read 6, iclass 5, count 0 2006.257.08:12:37.65#ibcon#end of sib2, iclass 5, count 0 2006.257.08:12:37.65#ibcon#*after write, iclass 5, count 0 2006.257.08:12:37.65#ibcon#*before return 0, iclass 5, count 0 2006.257.08:12:37.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:12:37.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:12:37.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.08:12:37.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.08:12:37.65$vck44/va=8,4 2006.257.08:12:37.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.08:12:37.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.08:12:37.65#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:37.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:12:37.66#abcon#{5=INTERFACE CLEAR} 2006.257.08:12:37.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:12:37.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:12:37.71#ibcon#enter wrdev, iclass 11, count 2 2006.257.08:12:37.71#ibcon#first serial, iclass 11, count 2 2006.257.08:12:37.71#ibcon#enter sib2, iclass 11, count 2 2006.257.08:12:37.71#ibcon#flushed, iclass 11, count 2 2006.257.08:12:37.71#ibcon#about to write, iclass 11, count 2 2006.257.08:12:37.71#ibcon#wrote, iclass 11, count 2 2006.257.08:12:37.71#ibcon#about to read 3, iclass 11, count 2 2006.257.08:12:37.72#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:12:37.73#ibcon#read 3, iclass 11, count 2 2006.257.08:12:37.73#ibcon#about to read 4, iclass 11, count 2 2006.257.08:12:37.73#ibcon#read 4, iclass 11, count 2 2006.257.08:12:37.73#ibcon#about to read 5, iclass 11, count 2 2006.257.08:12:37.73#ibcon#read 5, iclass 11, count 2 2006.257.08:12:37.73#ibcon#about to read 6, iclass 11, count 2 2006.257.08:12:37.73#ibcon#read 6, iclass 11, count 2 2006.257.08:12:37.73#ibcon#end of sib2, iclass 11, count 2 2006.257.08:12:37.73#ibcon#*mode == 0, iclass 11, count 2 2006.257.08:12:37.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.08:12:37.73#ibcon#[25=AT08-04\r\n] 2006.257.08:12:37.73#ibcon#*before write, iclass 11, count 2 2006.257.08:12:37.73#ibcon#enter sib2, iclass 11, count 2 2006.257.08:12:37.73#ibcon#flushed, iclass 11, count 2 2006.257.08:12:37.73#ibcon#about to write, iclass 11, count 2 2006.257.08:12:37.73#ibcon#wrote, iclass 11, count 2 2006.257.08:12:37.73#ibcon#about to read 3, iclass 11, count 2 2006.257.08:12:37.76#ibcon#read 3, iclass 11, count 2 2006.257.08:12:37.76#ibcon#about to read 4, iclass 11, count 2 2006.257.08:12:37.76#ibcon#read 4, iclass 11, count 2 2006.257.08:12:37.76#ibcon#about to read 5, iclass 11, count 2 2006.257.08:12:37.76#ibcon#read 5, iclass 11, count 2 2006.257.08:12:37.76#ibcon#about to read 6, iclass 11, count 2 2006.257.08:12:37.76#ibcon#read 6, iclass 11, count 2 2006.257.08:12:37.76#ibcon#end of sib2, iclass 11, count 2 2006.257.08:12:37.76#ibcon#*after write, iclass 11, count 2 2006.257.08:12:37.76#ibcon#*before return 0, iclass 11, count 2 2006.257.08:12:37.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:12:37.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:12:37.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.08:12:37.76#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:37.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:12:37.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:12:37.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:12:37.88#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:12:37.88#ibcon#first serial, iclass 11, count 0 2006.257.08:12:37.88#ibcon#enter sib2, iclass 11, count 0 2006.257.08:12:37.88#ibcon#flushed, iclass 11, count 0 2006.257.08:12:37.88#ibcon#about to write, iclass 11, count 0 2006.257.08:12:37.88#ibcon#wrote, iclass 11, count 0 2006.257.08:12:37.88#ibcon#about to read 3, iclass 11, count 0 2006.257.08:12:37.90#ibcon#read 3, iclass 11, count 0 2006.257.08:12:37.90#ibcon#about to read 4, iclass 11, count 0 2006.257.08:12:37.90#ibcon#read 4, iclass 11, count 0 2006.257.08:12:37.90#ibcon#about to read 5, iclass 11, count 0 2006.257.08:12:37.90#ibcon#read 5, iclass 11, count 0 2006.257.08:12:37.90#ibcon#about to read 6, iclass 11, count 0 2006.257.08:12:37.90#ibcon#read 6, iclass 11, count 0 2006.257.08:12:37.90#ibcon#end of sib2, iclass 11, count 0 2006.257.08:12:37.90#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:12:37.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:12:37.90#ibcon#[25=USB\r\n] 2006.257.08:12:37.90#ibcon#*before write, iclass 11, count 0 2006.257.08:12:37.90#ibcon#enter sib2, iclass 11, count 0 2006.257.08:12:37.90#ibcon#flushed, iclass 11, count 0 2006.257.08:12:37.90#ibcon#about to write, iclass 11, count 0 2006.257.08:12:37.90#ibcon#wrote, iclass 11, count 0 2006.257.08:12:37.90#ibcon#about to read 3, iclass 11, count 0 2006.257.08:12:37.93#ibcon#read 3, iclass 11, count 0 2006.257.08:12:37.93#ibcon#about to read 4, iclass 11, count 0 2006.257.08:12:37.93#ibcon#read 4, iclass 11, count 0 2006.257.08:12:37.93#ibcon#about to read 5, iclass 11, count 0 2006.257.08:12:37.93#ibcon#read 5, iclass 11, count 0 2006.257.08:12:37.93#ibcon#about to read 6, iclass 11, count 0 2006.257.08:12:37.93#ibcon#read 6, iclass 11, count 0 2006.257.08:12:37.93#ibcon#end of sib2, iclass 11, count 0 2006.257.08:12:37.93#ibcon#*after write, iclass 11, count 0 2006.257.08:12:37.93#ibcon#*before return 0, iclass 11, count 0 2006.257.08:12:37.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:12:37.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:12:37.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:12:37.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:12:37.93$vck44/vblo=1,629.99 2006.257.08:12:37.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.08:12:37.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.08:12:37.93#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:37.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:37.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:37.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:37.93#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:12:37.93#ibcon#first serial, iclass 14, count 0 2006.257.08:12:37.93#ibcon#enter sib2, iclass 14, count 0 2006.257.08:12:37.93#ibcon#flushed, iclass 14, count 0 2006.257.08:12:37.93#ibcon#about to write, iclass 14, count 0 2006.257.08:12:37.93#ibcon#wrote, iclass 14, count 0 2006.257.08:12:37.93#ibcon#about to read 3, iclass 14, count 0 2006.257.08:12:37.95#ibcon#read 3, iclass 14, count 0 2006.257.08:12:37.95#ibcon#about to read 4, iclass 14, count 0 2006.257.08:12:37.95#ibcon#read 4, iclass 14, count 0 2006.257.08:12:37.95#ibcon#about to read 5, iclass 14, count 0 2006.257.08:12:37.95#ibcon#read 5, iclass 14, count 0 2006.257.08:12:37.95#ibcon#about to read 6, iclass 14, count 0 2006.257.08:12:37.95#ibcon#read 6, iclass 14, count 0 2006.257.08:12:37.95#ibcon#end of sib2, iclass 14, count 0 2006.257.08:12:37.95#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:12:37.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:12:37.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:12:37.95#ibcon#*before write, iclass 14, count 0 2006.257.08:12:37.95#ibcon#enter sib2, iclass 14, count 0 2006.257.08:12:37.95#ibcon#flushed, iclass 14, count 0 2006.257.08:12:37.95#ibcon#about to write, iclass 14, count 0 2006.257.08:12:37.95#ibcon#wrote, iclass 14, count 0 2006.257.08:12:37.95#ibcon#about to read 3, iclass 14, count 0 2006.257.08:12:37.99#ibcon#read 3, iclass 14, count 0 2006.257.08:12:37.99#ibcon#about to read 4, iclass 14, count 0 2006.257.08:12:37.99#ibcon#read 4, iclass 14, count 0 2006.257.08:12:37.99#ibcon#about to read 5, iclass 14, count 0 2006.257.08:12:37.99#ibcon#read 5, iclass 14, count 0 2006.257.08:12:37.99#ibcon#about to read 6, iclass 14, count 0 2006.257.08:12:37.99#ibcon#read 6, iclass 14, count 0 2006.257.08:12:37.99#ibcon#end of sib2, iclass 14, count 0 2006.257.08:12:37.99#ibcon#*after write, iclass 14, count 0 2006.257.08:12:37.99#ibcon#*before return 0, iclass 14, count 0 2006.257.08:12:37.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:37.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:12:37.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:12:37.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:12:37.99$vck44/vb=1,4 2006.257.08:12:37.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.08:12:37.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.08:12:37.99#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:37.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:37.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:37.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:37.99#ibcon#enter wrdev, iclass 16, count 2 2006.257.08:12:37.99#ibcon#first serial, iclass 16, count 2 2006.257.08:12:37.99#ibcon#enter sib2, iclass 16, count 2 2006.257.08:12:37.99#ibcon#flushed, iclass 16, count 2 2006.257.08:12:37.99#ibcon#about to write, iclass 16, count 2 2006.257.08:12:37.99#ibcon#wrote, iclass 16, count 2 2006.257.08:12:37.99#ibcon#about to read 3, iclass 16, count 2 2006.257.08:12:38.01#ibcon#read 3, iclass 16, count 2 2006.257.08:12:38.01#ibcon#about to read 4, iclass 16, count 2 2006.257.08:12:38.01#ibcon#read 4, iclass 16, count 2 2006.257.08:12:38.01#ibcon#about to read 5, iclass 16, count 2 2006.257.08:12:38.01#ibcon#read 5, iclass 16, count 2 2006.257.08:12:38.01#ibcon#about to read 6, iclass 16, count 2 2006.257.08:12:38.01#ibcon#read 6, iclass 16, count 2 2006.257.08:12:38.01#ibcon#end of sib2, iclass 16, count 2 2006.257.08:12:38.01#ibcon#*mode == 0, iclass 16, count 2 2006.257.08:12:38.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.08:12:38.01#ibcon#[27=AT01-04\r\n] 2006.257.08:12:38.01#ibcon#*before write, iclass 16, count 2 2006.257.08:12:38.01#ibcon#enter sib2, iclass 16, count 2 2006.257.08:12:38.01#ibcon#flushed, iclass 16, count 2 2006.257.08:12:38.01#ibcon#about to write, iclass 16, count 2 2006.257.08:12:38.01#ibcon#wrote, iclass 16, count 2 2006.257.08:12:38.01#ibcon#about to read 3, iclass 16, count 2 2006.257.08:12:38.04#ibcon#read 3, iclass 16, count 2 2006.257.08:12:38.04#ibcon#about to read 4, iclass 16, count 2 2006.257.08:12:38.04#ibcon#read 4, iclass 16, count 2 2006.257.08:12:38.04#ibcon#about to read 5, iclass 16, count 2 2006.257.08:12:38.04#ibcon#read 5, iclass 16, count 2 2006.257.08:12:38.04#ibcon#about to read 6, iclass 16, count 2 2006.257.08:12:38.04#ibcon#read 6, iclass 16, count 2 2006.257.08:12:38.04#ibcon#end of sib2, iclass 16, count 2 2006.257.08:12:38.04#ibcon#*after write, iclass 16, count 2 2006.257.08:12:38.04#ibcon#*before return 0, iclass 16, count 2 2006.257.08:12:38.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:38.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:12:38.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.08:12:38.04#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:38.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:38.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:38.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:38.16#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:12:38.16#ibcon#first serial, iclass 16, count 0 2006.257.08:12:38.16#ibcon#enter sib2, iclass 16, count 0 2006.257.08:12:38.16#ibcon#flushed, iclass 16, count 0 2006.257.08:12:38.16#ibcon#about to write, iclass 16, count 0 2006.257.08:12:38.16#ibcon#wrote, iclass 16, count 0 2006.257.08:12:38.16#ibcon#about to read 3, iclass 16, count 0 2006.257.08:12:38.18#ibcon#read 3, iclass 16, count 0 2006.257.08:12:38.18#ibcon#about to read 4, iclass 16, count 0 2006.257.08:12:38.18#ibcon#read 4, iclass 16, count 0 2006.257.08:12:38.18#ibcon#about to read 5, iclass 16, count 0 2006.257.08:12:38.18#ibcon#read 5, iclass 16, count 0 2006.257.08:12:38.18#ibcon#about to read 6, iclass 16, count 0 2006.257.08:12:38.18#ibcon#read 6, iclass 16, count 0 2006.257.08:12:38.18#ibcon#end of sib2, iclass 16, count 0 2006.257.08:12:38.18#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:12:38.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:12:38.18#ibcon#[27=USB\r\n] 2006.257.08:12:38.18#ibcon#*before write, iclass 16, count 0 2006.257.08:12:38.18#ibcon#enter sib2, iclass 16, count 0 2006.257.08:12:38.18#ibcon#flushed, iclass 16, count 0 2006.257.08:12:38.18#ibcon#about to write, iclass 16, count 0 2006.257.08:12:38.18#ibcon#wrote, iclass 16, count 0 2006.257.08:12:38.18#ibcon#about to read 3, iclass 16, count 0 2006.257.08:12:38.21#ibcon#read 3, iclass 16, count 0 2006.257.08:12:38.21#ibcon#about to read 4, iclass 16, count 0 2006.257.08:12:38.21#ibcon#read 4, iclass 16, count 0 2006.257.08:12:38.21#ibcon#about to read 5, iclass 16, count 0 2006.257.08:12:38.21#ibcon#read 5, iclass 16, count 0 2006.257.08:12:38.21#ibcon#about to read 6, iclass 16, count 0 2006.257.08:12:38.21#ibcon#read 6, iclass 16, count 0 2006.257.08:12:38.21#ibcon#end of sib2, iclass 16, count 0 2006.257.08:12:38.21#ibcon#*after write, iclass 16, count 0 2006.257.08:12:38.21#ibcon#*before return 0, iclass 16, count 0 2006.257.08:12:38.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:38.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:12:38.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:12:38.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:12:38.21$vck44/vblo=2,634.99 2006.257.08:12:38.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.08:12:38.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.08:12:38.21#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:38.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:38.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:38.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:38.21#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:12:38.21#ibcon#first serial, iclass 18, count 0 2006.257.08:12:38.21#ibcon#enter sib2, iclass 18, count 0 2006.257.08:12:38.21#ibcon#flushed, iclass 18, count 0 2006.257.08:12:38.21#ibcon#about to write, iclass 18, count 0 2006.257.08:12:38.21#ibcon#wrote, iclass 18, count 0 2006.257.08:12:38.21#ibcon#about to read 3, iclass 18, count 0 2006.257.08:12:38.23#ibcon#read 3, iclass 18, count 0 2006.257.08:12:38.23#ibcon#about to read 4, iclass 18, count 0 2006.257.08:12:38.23#ibcon#read 4, iclass 18, count 0 2006.257.08:12:38.23#ibcon#about to read 5, iclass 18, count 0 2006.257.08:12:38.23#ibcon#read 5, iclass 18, count 0 2006.257.08:12:38.23#ibcon#about to read 6, iclass 18, count 0 2006.257.08:12:38.23#ibcon#read 6, iclass 18, count 0 2006.257.08:12:38.23#ibcon#end of sib2, iclass 18, count 0 2006.257.08:12:38.23#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:12:38.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:12:38.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:12:38.23#ibcon#*before write, iclass 18, count 0 2006.257.08:12:38.23#ibcon#enter sib2, iclass 18, count 0 2006.257.08:12:38.23#ibcon#flushed, iclass 18, count 0 2006.257.08:12:38.23#ibcon#about to write, iclass 18, count 0 2006.257.08:12:38.23#ibcon#wrote, iclass 18, count 0 2006.257.08:12:38.23#ibcon#about to read 3, iclass 18, count 0 2006.257.08:12:38.27#ibcon#read 3, iclass 18, count 0 2006.257.08:12:38.27#ibcon#about to read 4, iclass 18, count 0 2006.257.08:12:38.27#ibcon#read 4, iclass 18, count 0 2006.257.08:12:38.27#ibcon#about to read 5, iclass 18, count 0 2006.257.08:12:38.27#ibcon#read 5, iclass 18, count 0 2006.257.08:12:38.27#ibcon#about to read 6, iclass 18, count 0 2006.257.08:12:38.27#ibcon#read 6, iclass 18, count 0 2006.257.08:12:38.27#ibcon#end of sib2, iclass 18, count 0 2006.257.08:12:38.27#ibcon#*after write, iclass 18, count 0 2006.257.08:12:38.27#ibcon#*before return 0, iclass 18, count 0 2006.257.08:12:38.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:38.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:12:38.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:12:38.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:12:38.27$vck44/vb=2,5 2006.257.08:12:38.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.08:12:38.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.08:12:38.27#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:38.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:38.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:38.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:38.33#ibcon#enter wrdev, iclass 20, count 2 2006.257.08:12:38.33#ibcon#first serial, iclass 20, count 2 2006.257.08:12:38.33#ibcon#enter sib2, iclass 20, count 2 2006.257.08:12:38.33#ibcon#flushed, iclass 20, count 2 2006.257.08:12:38.33#ibcon#about to write, iclass 20, count 2 2006.257.08:12:38.33#ibcon#wrote, iclass 20, count 2 2006.257.08:12:38.33#ibcon#about to read 3, iclass 20, count 2 2006.257.08:12:38.35#ibcon#read 3, iclass 20, count 2 2006.257.08:12:38.35#ibcon#about to read 4, iclass 20, count 2 2006.257.08:12:38.35#ibcon#read 4, iclass 20, count 2 2006.257.08:12:38.35#ibcon#about to read 5, iclass 20, count 2 2006.257.08:12:38.35#ibcon#read 5, iclass 20, count 2 2006.257.08:12:38.35#ibcon#about to read 6, iclass 20, count 2 2006.257.08:12:38.35#ibcon#read 6, iclass 20, count 2 2006.257.08:12:38.35#ibcon#end of sib2, iclass 20, count 2 2006.257.08:12:38.35#ibcon#*mode == 0, iclass 20, count 2 2006.257.08:12:38.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.08:12:38.35#ibcon#[27=AT02-05\r\n] 2006.257.08:12:38.35#ibcon#*before write, iclass 20, count 2 2006.257.08:12:38.35#ibcon#enter sib2, iclass 20, count 2 2006.257.08:12:38.35#ibcon#flushed, iclass 20, count 2 2006.257.08:12:38.35#ibcon#about to write, iclass 20, count 2 2006.257.08:12:38.35#ibcon#wrote, iclass 20, count 2 2006.257.08:12:38.35#ibcon#about to read 3, iclass 20, count 2 2006.257.08:12:38.38#ibcon#read 3, iclass 20, count 2 2006.257.08:12:38.38#ibcon#about to read 4, iclass 20, count 2 2006.257.08:12:38.38#ibcon#read 4, iclass 20, count 2 2006.257.08:12:38.38#ibcon#about to read 5, iclass 20, count 2 2006.257.08:12:38.38#ibcon#read 5, iclass 20, count 2 2006.257.08:12:38.38#ibcon#about to read 6, iclass 20, count 2 2006.257.08:12:38.38#ibcon#read 6, iclass 20, count 2 2006.257.08:12:38.38#ibcon#end of sib2, iclass 20, count 2 2006.257.08:12:38.38#ibcon#*after write, iclass 20, count 2 2006.257.08:12:38.38#ibcon#*before return 0, iclass 20, count 2 2006.257.08:12:38.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:38.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:12:38.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.08:12:38.38#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:38.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:38.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:38.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:38.50#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:12:38.50#ibcon#first serial, iclass 20, count 0 2006.257.08:12:38.50#ibcon#enter sib2, iclass 20, count 0 2006.257.08:12:38.50#ibcon#flushed, iclass 20, count 0 2006.257.08:12:38.50#ibcon#about to write, iclass 20, count 0 2006.257.08:12:38.50#ibcon#wrote, iclass 20, count 0 2006.257.08:12:38.50#ibcon#about to read 3, iclass 20, count 0 2006.257.08:12:38.52#ibcon#read 3, iclass 20, count 0 2006.257.08:12:38.52#ibcon#about to read 4, iclass 20, count 0 2006.257.08:12:38.52#ibcon#read 4, iclass 20, count 0 2006.257.08:12:38.52#ibcon#about to read 5, iclass 20, count 0 2006.257.08:12:38.52#ibcon#read 5, iclass 20, count 0 2006.257.08:12:38.52#ibcon#about to read 6, iclass 20, count 0 2006.257.08:12:38.52#ibcon#read 6, iclass 20, count 0 2006.257.08:12:38.52#ibcon#end of sib2, iclass 20, count 0 2006.257.08:12:38.52#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:12:38.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:12:38.52#ibcon#[27=USB\r\n] 2006.257.08:12:38.52#ibcon#*before write, iclass 20, count 0 2006.257.08:12:38.52#ibcon#enter sib2, iclass 20, count 0 2006.257.08:12:38.52#ibcon#flushed, iclass 20, count 0 2006.257.08:12:38.52#ibcon#about to write, iclass 20, count 0 2006.257.08:12:38.52#ibcon#wrote, iclass 20, count 0 2006.257.08:12:38.52#ibcon#about to read 3, iclass 20, count 0 2006.257.08:12:38.55#ibcon#read 3, iclass 20, count 0 2006.257.08:12:38.55#ibcon#about to read 4, iclass 20, count 0 2006.257.08:12:38.55#ibcon#read 4, iclass 20, count 0 2006.257.08:12:38.55#ibcon#about to read 5, iclass 20, count 0 2006.257.08:12:38.55#ibcon#read 5, iclass 20, count 0 2006.257.08:12:38.55#ibcon#about to read 6, iclass 20, count 0 2006.257.08:12:38.55#ibcon#read 6, iclass 20, count 0 2006.257.08:12:38.55#ibcon#end of sib2, iclass 20, count 0 2006.257.08:12:38.55#ibcon#*after write, iclass 20, count 0 2006.257.08:12:38.55#ibcon#*before return 0, iclass 20, count 0 2006.257.08:12:38.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:38.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:12:38.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:12:38.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:12:38.55$vck44/vblo=3,649.99 2006.257.08:12:38.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.08:12:38.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.08:12:38.55#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:38.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:38.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:38.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:38.55#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:12:38.55#ibcon#first serial, iclass 22, count 0 2006.257.08:12:38.55#ibcon#enter sib2, iclass 22, count 0 2006.257.08:12:38.55#ibcon#flushed, iclass 22, count 0 2006.257.08:12:38.55#ibcon#about to write, iclass 22, count 0 2006.257.08:12:38.55#ibcon#wrote, iclass 22, count 0 2006.257.08:12:38.55#ibcon#about to read 3, iclass 22, count 0 2006.257.08:12:38.57#ibcon#read 3, iclass 22, count 0 2006.257.08:12:38.57#ibcon#about to read 4, iclass 22, count 0 2006.257.08:12:38.57#ibcon#read 4, iclass 22, count 0 2006.257.08:12:38.57#ibcon#about to read 5, iclass 22, count 0 2006.257.08:12:38.57#ibcon#read 5, iclass 22, count 0 2006.257.08:12:38.57#ibcon#about to read 6, iclass 22, count 0 2006.257.08:12:38.57#ibcon#read 6, iclass 22, count 0 2006.257.08:12:38.57#ibcon#end of sib2, iclass 22, count 0 2006.257.08:12:38.57#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:12:38.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:12:38.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:12:38.57#ibcon#*before write, iclass 22, count 0 2006.257.08:12:38.57#ibcon#enter sib2, iclass 22, count 0 2006.257.08:12:38.57#ibcon#flushed, iclass 22, count 0 2006.257.08:12:38.57#ibcon#about to write, iclass 22, count 0 2006.257.08:12:38.57#ibcon#wrote, iclass 22, count 0 2006.257.08:12:38.57#ibcon#about to read 3, iclass 22, count 0 2006.257.08:12:38.61#ibcon#read 3, iclass 22, count 0 2006.257.08:12:38.61#ibcon#about to read 4, iclass 22, count 0 2006.257.08:12:38.61#ibcon#read 4, iclass 22, count 0 2006.257.08:12:38.61#ibcon#about to read 5, iclass 22, count 0 2006.257.08:12:38.61#ibcon#read 5, iclass 22, count 0 2006.257.08:12:38.61#ibcon#about to read 6, iclass 22, count 0 2006.257.08:12:38.61#ibcon#read 6, iclass 22, count 0 2006.257.08:12:38.61#ibcon#end of sib2, iclass 22, count 0 2006.257.08:12:38.61#ibcon#*after write, iclass 22, count 0 2006.257.08:12:38.61#ibcon#*before return 0, iclass 22, count 0 2006.257.08:12:38.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:38.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:12:38.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:12:38.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:12:38.61$vck44/vb=3,4 2006.257.08:12:38.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.08:12:38.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.08:12:38.61#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:38.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:38.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:38.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:38.67#ibcon#enter wrdev, iclass 24, count 2 2006.257.08:12:38.67#ibcon#first serial, iclass 24, count 2 2006.257.08:12:38.67#ibcon#enter sib2, iclass 24, count 2 2006.257.08:12:38.67#ibcon#flushed, iclass 24, count 2 2006.257.08:12:38.67#ibcon#about to write, iclass 24, count 2 2006.257.08:12:38.67#ibcon#wrote, iclass 24, count 2 2006.257.08:12:38.67#ibcon#about to read 3, iclass 24, count 2 2006.257.08:12:38.69#ibcon#read 3, iclass 24, count 2 2006.257.08:12:38.69#ibcon#about to read 4, iclass 24, count 2 2006.257.08:12:38.69#ibcon#read 4, iclass 24, count 2 2006.257.08:12:38.69#ibcon#about to read 5, iclass 24, count 2 2006.257.08:12:38.69#ibcon#read 5, iclass 24, count 2 2006.257.08:12:38.69#ibcon#about to read 6, iclass 24, count 2 2006.257.08:12:38.69#ibcon#read 6, iclass 24, count 2 2006.257.08:12:38.69#ibcon#end of sib2, iclass 24, count 2 2006.257.08:12:38.69#ibcon#*mode == 0, iclass 24, count 2 2006.257.08:12:38.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.08:12:38.69#ibcon#[27=AT03-04\r\n] 2006.257.08:12:38.69#ibcon#*before write, iclass 24, count 2 2006.257.08:12:38.69#ibcon#enter sib2, iclass 24, count 2 2006.257.08:12:38.69#ibcon#flushed, iclass 24, count 2 2006.257.08:12:38.69#ibcon#about to write, iclass 24, count 2 2006.257.08:12:38.69#ibcon#wrote, iclass 24, count 2 2006.257.08:12:38.69#ibcon#about to read 3, iclass 24, count 2 2006.257.08:12:38.72#ibcon#read 3, iclass 24, count 2 2006.257.08:12:38.72#ibcon#about to read 4, iclass 24, count 2 2006.257.08:12:38.72#ibcon#read 4, iclass 24, count 2 2006.257.08:12:38.72#ibcon#about to read 5, iclass 24, count 2 2006.257.08:12:38.72#ibcon#read 5, iclass 24, count 2 2006.257.08:12:38.72#ibcon#about to read 6, iclass 24, count 2 2006.257.08:12:38.72#ibcon#read 6, iclass 24, count 2 2006.257.08:12:38.72#ibcon#end of sib2, iclass 24, count 2 2006.257.08:12:38.72#ibcon#*after write, iclass 24, count 2 2006.257.08:12:38.72#ibcon#*before return 0, iclass 24, count 2 2006.257.08:12:38.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:38.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:12:38.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.08:12:38.72#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:38.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:38.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:38.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:38.84#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:12:38.84#ibcon#first serial, iclass 24, count 0 2006.257.08:12:38.84#ibcon#enter sib2, iclass 24, count 0 2006.257.08:12:38.84#ibcon#flushed, iclass 24, count 0 2006.257.08:12:38.84#ibcon#about to write, iclass 24, count 0 2006.257.08:12:38.84#ibcon#wrote, iclass 24, count 0 2006.257.08:12:38.84#ibcon#about to read 3, iclass 24, count 0 2006.257.08:12:38.86#ibcon#read 3, iclass 24, count 0 2006.257.08:12:38.86#ibcon#about to read 4, iclass 24, count 0 2006.257.08:12:38.86#ibcon#read 4, iclass 24, count 0 2006.257.08:12:38.86#ibcon#about to read 5, iclass 24, count 0 2006.257.08:12:38.86#ibcon#read 5, iclass 24, count 0 2006.257.08:12:38.86#ibcon#about to read 6, iclass 24, count 0 2006.257.08:12:38.86#ibcon#read 6, iclass 24, count 0 2006.257.08:12:38.86#ibcon#end of sib2, iclass 24, count 0 2006.257.08:12:38.86#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:12:38.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:12:38.86#ibcon#[27=USB\r\n] 2006.257.08:12:38.86#ibcon#*before write, iclass 24, count 0 2006.257.08:12:38.86#ibcon#enter sib2, iclass 24, count 0 2006.257.08:12:38.86#ibcon#flushed, iclass 24, count 0 2006.257.08:12:38.86#ibcon#about to write, iclass 24, count 0 2006.257.08:12:38.86#ibcon#wrote, iclass 24, count 0 2006.257.08:12:38.86#ibcon#about to read 3, iclass 24, count 0 2006.257.08:12:38.89#ibcon#read 3, iclass 24, count 0 2006.257.08:12:38.89#ibcon#about to read 4, iclass 24, count 0 2006.257.08:12:38.89#ibcon#read 4, iclass 24, count 0 2006.257.08:12:38.89#ibcon#about to read 5, iclass 24, count 0 2006.257.08:12:38.89#ibcon#read 5, iclass 24, count 0 2006.257.08:12:38.89#ibcon#about to read 6, iclass 24, count 0 2006.257.08:12:38.89#ibcon#read 6, iclass 24, count 0 2006.257.08:12:38.89#ibcon#end of sib2, iclass 24, count 0 2006.257.08:12:38.89#ibcon#*after write, iclass 24, count 0 2006.257.08:12:38.89#ibcon#*before return 0, iclass 24, count 0 2006.257.08:12:38.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:38.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:12:38.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:12:38.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:12:38.89$vck44/vblo=4,679.99 2006.257.08:12:38.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.08:12:38.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.08:12:38.89#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:38.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:38.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:38.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:38.89#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:12:38.89#ibcon#first serial, iclass 26, count 0 2006.257.08:12:38.89#ibcon#enter sib2, iclass 26, count 0 2006.257.08:12:38.89#ibcon#flushed, iclass 26, count 0 2006.257.08:12:38.89#ibcon#about to write, iclass 26, count 0 2006.257.08:12:38.89#ibcon#wrote, iclass 26, count 0 2006.257.08:12:38.89#ibcon#about to read 3, iclass 26, count 0 2006.257.08:12:38.91#ibcon#read 3, iclass 26, count 0 2006.257.08:12:38.91#ibcon#about to read 4, iclass 26, count 0 2006.257.08:12:38.91#ibcon#read 4, iclass 26, count 0 2006.257.08:12:38.91#ibcon#about to read 5, iclass 26, count 0 2006.257.08:12:38.91#ibcon#read 5, iclass 26, count 0 2006.257.08:12:38.91#ibcon#about to read 6, iclass 26, count 0 2006.257.08:12:38.91#ibcon#read 6, iclass 26, count 0 2006.257.08:12:38.91#ibcon#end of sib2, iclass 26, count 0 2006.257.08:12:38.91#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:12:38.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:12:38.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:12:38.91#ibcon#*before write, iclass 26, count 0 2006.257.08:12:38.91#ibcon#enter sib2, iclass 26, count 0 2006.257.08:12:38.91#ibcon#flushed, iclass 26, count 0 2006.257.08:12:38.91#ibcon#about to write, iclass 26, count 0 2006.257.08:12:38.91#ibcon#wrote, iclass 26, count 0 2006.257.08:12:38.91#ibcon#about to read 3, iclass 26, count 0 2006.257.08:12:38.95#ibcon#read 3, iclass 26, count 0 2006.257.08:12:38.95#ibcon#about to read 4, iclass 26, count 0 2006.257.08:12:38.95#ibcon#read 4, iclass 26, count 0 2006.257.08:12:38.95#ibcon#about to read 5, iclass 26, count 0 2006.257.08:12:38.95#ibcon#read 5, iclass 26, count 0 2006.257.08:12:38.95#ibcon#about to read 6, iclass 26, count 0 2006.257.08:12:38.95#ibcon#read 6, iclass 26, count 0 2006.257.08:12:38.95#ibcon#end of sib2, iclass 26, count 0 2006.257.08:12:38.95#ibcon#*after write, iclass 26, count 0 2006.257.08:12:38.95#ibcon#*before return 0, iclass 26, count 0 2006.257.08:12:38.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:38.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:12:38.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:12:38.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:12:38.95$vck44/vb=4,5 2006.257.08:12:38.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.08:12:38.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.08:12:38.95#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:38.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:39.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:39.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:39.01#ibcon#enter wrdev, iclass 28, count 2 2006.257.08:12:39.01#ibcon#first serial, iclass 28, count 2 2006.257.08:12:39.01#ibcon#enter sib2, iclass 28, count 2 2006.257.08:12:39.01#ibcon#flushed, iclass 28, count 2 2006.257.08:12:39.01#ibcon#about to write, iclass 28, count 2 2006.257.08:12:39.01#ibcon#wrote, iclass 28, count 2 2006.257.08:12:39.01#ibcon#about to read 3, iclass 28, count 2 2006.257.08:12:39.03#ibcon#read 3, iclass 28, count 2 2006.257.08:12:39.03#ibcon#about to read 4, iclass 28, count 2 2006.257.08:12:39.03#ibcon#read 4, iclass 28, count 2 2006.257.08:12:39.03#ibcon#about to read 5, iclass 28, count 2 2006.257.08:12:39.03#ibcon#read 5, iclass 28, count 2 2006.257.08:12:39.03#ibcon#about to read 6, iclass 28, count 2 2006.257.08:12:39.03#ibcon#read 6, iclass 28, count 2 2006.257.08:12:39.03#ibcon#end of sib2, iclass 28, count 2 2006.257.08:12:39.03#ibcon#*mode == 0, iclass 28, count 2 2006.257.08:12:39.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.08:12:39.03#ibcon#[27=AT04-05\r\n] 2006.257.08:12:39.03#ibcon#*before write, iclass 28, count 2 2006.257.08:12:39.03#ibcon#enter sib2, iclass 28, count 2 2006.257.08:12:39.03#ibcon#flushed, iclass 28, count 2 2006.257.08:12:39.03#ibcon#about to write, iclass 28, count 2 2006.257.08:12:39.03#ibcon#wrote, iclass 28, count 2 2006.257.08:12:39.03#ibcon#about to read 3, iclass 28, count 2 2006.257.08:12:39.06#ibcon#read 3, iclass 28, count 2 2006.257.08:12:39.06#ibcon#about to read 4, iclass 28, count 2 2006.257.08:12:39.06#ibcon#read 4, iclass 28, count 2 2006.257.08:12:39.06#ibcon#about to read 5, iclass 28, count 2 2006.257.08:12:39.06#ibcon#read 5, iclass 28, count 2 2006.257.08:12:39.06#ibcon#about to read 6, iclass 28, count 2 2006.257.08:12:39.06#ibcon#read 6, iclass 28, count 2 2006.257.08:12:39.06#ibcon#end of sib2, iclass 28, count 2 2006.257.08:12:39.06#ibcon#*after write, iclass 28, count 2 2006.257.08:12:39.06#ibcon#*before return 0, iclass 28, count 2 2006.257.08:12:39.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:39.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:12:39.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.08:12:39.06#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:39.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:39.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:39.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:39.18#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:12:39.18#ibcon#first serial, iclass 28, count 0 2006.257.08:12:39.18#ibcon#enter sib2, iclass 28, count 0 2006.257.08:12:39.18#ibcon#flushed, iclass 28, count 0 2006.257.08:12:39.18#ibcon#about to write, iclass 28, count 0 2006.257.08:12:39.18#ibcon#wrote, iclass 28, count 0 2006.257.08:12:39.18#ibcon#about to read 3, iclass 28, count 0 2006.257.08:12:39.20#ibcon#read 3, iclass 28, count 0 2006.257.08:12:39.20#ibcon#about to read 4, iclass 28, count 0 2006.257.08:12:39.20#ibcon#read 4, iclass 28, count 0 2006.257.08:12:39.20#ibcon#about to read 5, iclass 28, count 0 2006.257.08:12:39.20#ibcon#read 5, iclass 28, count 0 2006.257.08:12:39.20#ibcon#about to read 6, iclass 28, count 0 2006.257.08:12:39.20#ibcon#read 6, iclass 28, count 0 2006.257.08:12:39.20#ibcon#end of sib2, iclass 28, count 0 2006.257.08:12:39.20#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:12:39.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:12:39.20#ibcon#[27=USB\r\n] 2006.257.08:12:39.20#ibcon#*before write, iclass 28, count 0 2006.257.08:12:39.20#ibcon#enter sib2, iclass 28, count 0 2006.257.08:12:39.20#ibcon#flushed, iclass 28, count 0 2006.257.08:12:39.20#ibcon#about to write, iclass 28, count 0 2006.257.08:12:39.20#ibcon#wrote, iclass 28, count 0 2006.257.08:12:39.20#ibcon#about to read 3, iclass 28, count 0 2006.257.08:12:39.23#ibcon#read 3, iclass 28, count 0 2006.257.08:12:39.23#ibcon#about to read 4, iclass 28, count 0 2006.257.08:12:39.23#ibcon#read 4, iclass 28, count 0 2006.257.08:12:39.23#ibcon#about to read 5, iclass 28, count 0 2006.257.08:12:39.23#ibcon#read 5, iclass 28, count 0 2006.257.08:12:39.23#ibcon#about to read 6, iclass 28, count 0 2006.257.08:12:39.23#ibcon#read 6, iclass 28, count 0 2006.257.08:12:39.23#ibcon#end of sib2, iclass 28, count 0 2006.257.08:12:39.23#ibcon#*after write, iclass 28, count 0 2006.257.08:12:39.23#ibcon#*before return 0, iclass 28, count 0 2006.257.08:12:39.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:39.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:12:39.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:12:39.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:12:39.23$vck44/vblo=5,709.99 2006.257.08:12:39.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.08:12:39.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.08:12:39.23#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:39.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:39.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:39.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:39.23#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:12:39.23#ibcon#first serial, iclass 30, count 0 2006.257.08:12:39.23#ibcon#enter sib2, iclass 30, count 0 2006.257.08:12:39.23#ibcon#flushed, iclass 30, count 0 2006.257.08:12:39.23#ibcon#about to write, iclass 30, count 0 2006.257.08:12:39.23#ibcon#wrote, iclass 30, count 0 2006.257.08:12:39.23#ibcon#about to read 3, iclass 30, count 0 2006.257.08:12:39.25#ibcon#read 3, iclass 30, count 0 2006.257.08:12:39.25#ibcon#about to read 4, iclass 30, count 0 2006.257.08:12:39.25#ibcon#read 4, iclass 30, count 0 2006.257.08:12:39.25#ibcon#about to read 5, iclass 30, count 0 2006.257.08:12:39.25#ibcon#read 5, iclass 30, count 0 2006.257.08:12:39.25#ibcon#about to read 6, iclass 30, count 0 2006.257.08:12:39.25#ibcon#read 6, iclass 30, count 0 2006.257.08:12:39.25#ibcon#end of sib2, iclass 30, count 0 2006.257.08:12:39.25#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:12:39.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:12:39.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:12:39.25#ibcon#*before write, iclass 30, count 0 2006.257.08:12:39.25#ibcon#enter sib2, iclass 30, count 0 2006.257.08:12:39.25#ibcon#flushed, iclass 30, count 0 2006.257.08:12:39.25#ibcon#about to write, iclass 30, count 0 2006.257.08:12:39.25#ibcon#wrote, iclass 30, count 0 2006.257.08:12:39.25#ibcon#about to read 3, iclass 30, count 0 2006.257.08:12:39.29#ibcon#read 3, iclass 30, count 0 2006.257.08:12:39.29#ibcon#about to read 4, iclass 30, count 0 2006.257.08:12:39.29#ibcon#read 4, iclass 30, count 0 2006.257.08:12:39.29#ibcon#about to read 5, iclass 30, count 0 2006.257.08:12:39.29#ibcon#read 5, iclass 30, count 0 2006.257.08:12:39.29#ibcon#about to read 6, iclass 30, count 0 2006.257.08:12:39.29#ibcon#read 6, iclass 30, count 0 2006.257.08:12:39.29#ibcon#end of sib2, iclass 30, count 0 2006.257.08:12:39.29#ibcon#*after write, iclass 30, count 0 2006.257.08:12:39.29#ibcon#*before return 0, iclass 30, count 0 2006.257.08:12:39.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:39.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:12:39.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:12:39.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:12:39.29$vck44/vb=5,4 2006.257.08:12:39.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.08:12:39.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.08:12:39.29#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:39.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:39.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:39.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:39.35#ibcon#enter wrdev, iclass 32, count 2 2006.257.08:12:39.35#ibcon#first serial, iclass 32, count 2 2006.257.08:12:39.35#ibcon#enter sib2, iclass 32, count 2 2006.257.08:12:39.35#ibcon#flushed, iclass 32, count 2 2006.257.08:12:39.35#ibcon#about to write, iclass 32, count 2 2006.257.08:12:39.35#ibcon#wrote, iclass 32, count 2 2006.257.08:12:39.35#ibcon#about to read 3, iclass 32, count 2 2006.257.08:12:39.37#ibcon#read 3, iclass 32, count 2 2006.257.08:12:39.37#ibcon#about to read 4, iclass 32, count 2 2006.257.08:12:39.37#ibcon#read 4, iclass 32, count 2 2006.257.08:12:39.37#ibcon#about to read 5, iclass 32, count 2 2006.257.08:12:39.37#ibcon#read 5, iclass 32, count 2 2006.257.08:12:39.37#ibcon#about to read 6, iclass 32, count 2 2006.257.08:12:39.37#ibcon#read 6, iclass 32, count 2 2006.257.08:12:39.37#ibcon#end of sib2, iclass 32, count 2 2006.257.08:12:39.37#ibcon#*mode == 0, iclass 32, count 2 2006.257.08:12:39.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.08:12:39.37#ibcon#[27=AT05-04\r\n] 2006.257.08:12:39.37#ibcon#*before write, iclass 32, count 2 2006.257.08:12:39.37#ibcon#enter sib2, iclass 32, count 2 2006.257.08:12:39.37#ibcon#flushed, iclass 32, count 2 2006.257.08:12:39.37#ibcon#about to write, iclass 32, count 2 2006.257.08:12:39.37#ibcon#wrote, iclass 32, count 2 2006.257.08:12:39.37#ibcon#about to read 3, iclass 32, count 2 2006.257.08:12:39.40#ibcon#read 3, iclass 32, count 2 2006.257.08:12:39.40#ibcon#about to read 4, iclass 32, count 2 2006.257.08:12:39.40#ibcon#read 4, iclass 32, count 2 2006.257.08:12:39.40#ibcon#about to read 5, iclass 32, count 2 2006.257.08:12:39.40#ibcon#read 5, iclass 32, count 2 2006.257.08:12:39.40#ibcon#about to read 6, iclass 32, count 2 2006.257.08:12:39.40#ibcon#read 6, iclass 32, count 2 2006.257.08:12:39.40#ibcon#end of sib2, iclass 32, count 2 2006.257.08:12:39.40#ibcon#*after write, iclass 32, count 2 2006.257.08:12:39.40#ibcon#*before return 0, iclass 32, count 2 2006.257.08:12:39.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:39.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:12:39.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.08:12:39.40#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:39.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:39.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:39.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:39.52#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:12:39.52#ibcon#first serial, iclass 32, count 0 2006.257.08:12:39.52#ibcon#enter sib2, iclass 32, count 0 2006.257.08:12:39.52#ibcon#flushed, iclass 32, count 0 2006.257.08:12:39.52#ibcon#about to write, iclass 32, count 0 2006.257.08:12:39.52#ibcon#wrote, iclass 32, count 0 2006.257.08:12:39.52#ibcon#about to read 3, iclass 32, count 0 2006.257.08:12:39.54#ibcon#read 3, iclass 32, count 0 2006.257.08:12:39.54#ibcon#about to read 4, iclass 32, count 0 2006.257.08:12:39.54#ibcon#read 4, iclass 32, count 0 2006.257.08:12:39.54#ibcon#about to read 5, iclass 32, count 0 2006.257.08:12:39.54#ibcon#read 5, iclass 32, count 0 2006.257.08:12:39.54#ibcon#about to read 6, iclass 32, count 0 2006.257.08:12:39.54#ibcon#read 6, iclass 32, count 0 2006.257.08:12:39.54#ibcon#end of sib2, iclass 32, count 0 2006.257.08:12:39.54#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:12:39.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:12:39.54#ibcon#[27=USB\r\n] 2006.257.08:12:39.54#ibcon#*before write, iclass 32, count 0 2006.257.08:12:39.54#ibcon#enter sib2, iclass 32, count 0 2006.257.08:12:39.54#ibcon#flushed, iclass 32, count 0 2006.257.08:12:39.54#ibcon#about to write, iclass 32, count 0 2006.257.08:12:39.54#ibcon#wrote, iclass 32, count 0 2006.257.08:12:39.54#ibcon#about to read 3, iclass 32, count 0 2006.257.08:12:39.57#ibcon#read 3, iclass 32, count 0 2006.257.08:12:39.57#ibcon#about to read 4, iclass 32, count 0 2006.257.08:12:39.57#ibcon#read 4, iclass 32, count 0 2006.257.08:12:39.57#ibcon#about to read 5, iclass 32, count 0 2006.257.08:12:39.57#ibcon#read 5, iclass 32, count 0 2006.257.08:12:39.57#ibcon#about to read 6, iclass 32, count 0 2006.257.08:12:39.57#ibcon#read 6, iclass 32, count 0 2006.257.08:12:39.57#ibcon#end of sib2, iclass 32, count 0 2006.257.08:12:39.57#ibcon#*after write, iclass 32, count 0 2006.257.08:12:39.57#ibcon#*before return 0, iclass 32, count 0 2006.257.08:12:39.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:39.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:12:39.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:12:39.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:12:39.57$vck44/vblo=6,719.99 2006.257.08:12:39.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.08:12:39.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.08:12:39.57#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:39.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:39.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:39.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:39.57#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:12:39.57#ibcon#first serial, iclass 34, count 0 2006.257.08:12:39.57#ibcon#enter sib2, iclass 34, count 0 2006.257.08:12:39.57#ibcon#flushed, iclass 34, count 0 2006.257.08:12:39.57#ibcon#about to write, iclass 34, count 0 2006.257.08:12:39.57#ibcon#wrote, iclass 34, count 0 2006.257.08:12:39.57#ibcon#about to read 3, iclass 34, count 0 2006.257.08:12:39.59#ibcon#read 3, iclass 34, count 0 2006.257.08:12:39.59#ibcon#about to read 4, iclass 34, count 0 2006.257.08:12:39.59#ibcon#read 4, iclass 34, count 0 2006.257.08:12:39.59#ibcon#about to read 5, iclass 34, count 0 2006.257.08:12:39.59#ibcon#read 5, iclass 34, count 0 2006.257.08:12:39.59#ibcon#about to read 6, iclass 34, count 0 2006.257.08:12:39.59#ibcon#read 6, iclass 34, count 0 2006.257.08:12:39.59#ibcon#end of sib2, iclass 34, count 0 2006.257.08:12:39.59#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:12:39.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:12:39.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:12:39.59#ibcon#*before write, iclass 34, count 0 2006.257.08:12:39.59#ibcon#enter sib2, iclass 34, count 0 2006.257.08:12:39.59#ibcon#flushed, iclass 34, count 0 2006.257.08:12:39.59#ibcon#about to write, iclass 34, count 0 2006.257.08:12:39.59#ibcon#wrote, iclass 34, count 0 2006.257.08:12:39.59#ibcon#about to read 3, iclass 34, count 0 2006.257.08:12:39.63#ibcon#read 3, iclass 34, count 0 2006.257.08:12:39.63#ibcon#about to read 4, iclass 34, count 0 2006.257.08:12:39.63#ibcon#read 4, iclass 34, count 0 2006.257.08:12:39.63#ibcon#about to read 5, iclass 34, count 0 2006.257.08:12:39.63#ibcon#read 5, iclass 34, count 0 2006.257.08:12:39.63#ibcon#about to read 6, iclass 34, count 0 2006.257.08:12:39.63#ibcon#read 6, iclass 34, count 0 2006.257.08:12:39.63#ibcon#end of sib2, iclass 34, count 0 2006.257.08:12:39.63#ibcon#*after write, iclass 34, count 0 2006.257.08:12:39.63#ibcon#*before return 0, iclass 34, count 0 2006.257.08:12:39.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:39.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:12:39.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:12:39.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:12:39.63$vck44/vb=6,4 2006.257.08:12:39.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.08:12:39.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.08:12:39.63#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:39.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:39.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:39.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:39.69#ibcon#enter wrdev, iclass 36, count 2 2006.257.08:12:39.69#ibcon#first serial, iclass 36, count 2 2006.257.08:12:39.69#ibcon#enter sib2, iclass 36, count 2 2006.257.08:12:39.69#ibcon#flushed, iclass 36, count 2 2006.257.08:12:39.69#ibcon#about to write, iclass 36, count 2 2006.257.08:12:39.69#ibcon#wrote, iclass 36, count 2 2006.257.08:12:39.69#ibcon#about to read 3, iclass 36, count 2 2006.257.08:12:39.71#ibcon#read 3, iclass 36, count 2 2006.257.08:12:39.71#ibcon#about to read 4, iclass 36, count 2 2006.257.08:12:39.71#ibcon#read 4, iclass 36, count 2 2006.257.08:12:39.71#ibcon#about to read 5, iclass 36, count 2 2006.257.08:12:39.71#ibcon#read 5, iclass 36, count 2 2006.257.08:12:39.71#ibcon#about to read 6, iclass 36, count 2 2006.257.08:12:39.71#ibcon#read 6, iclass 36, count 2 2006.257.08:12:39.71#ibcon#end of sib2, iclass 36, count 2 2006.257.08:12:39.71#ibcon#*mode == 0, iclass 36, count 2 2006.257.08:12:39.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.08:12:39.71#ibcon#[27=AT06-04\r\n] 2006.257.08:12:39.71#ibcon#*before write, iclass 36, count 2 2006.257.08:12:39.71#ibcon#enter sib2, iclass 36, count 2 2006.257.08:12:39.71#ibcon#flushed, iclass 36, count 2 2006.257.08:12:39.71#ibcon#about to write, iclass 36, count 2 2006.257.08:12:39.71#ibcon#wrote, iclass 36, count 2 2006.257.08:12:39.71#ibcon#about to read 3, iclass 36, count 2 2006.257.08:12:39.74#ibcon#read 3, iclass 36, count 2 2006.257.08:12:39.74#ibcon#about to read 4, iclass 36, count 2 2006.257.08:12:39.74#ibcon#read 4, iclass 36, count 2 2006.257.08:12:39.74#ibcon#about to read 5, iclass 36, count 2 2006.257.08:12:39.74#ibcon#read 5, iclass 36, count 2 2006.257.08:12:39.74#ibcon#about to read 6, iclass 36, count 2 2006.257.08:12:39.74#ibcon#read 6, iclass 36, count 2 2006.257.08:12:39.74#ibcon#end of sib2, iclass 36, count 2 2006.257.08:12:39.74#ibcon#*after write, iclass 36, count 2 2006.257.08:12:39.74#ibcon#*before return 0, iclass 36, count 2 2006.257.08:12:39.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:39.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:12:39.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.08:12:39.74#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:39.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:39.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:39.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:39.86#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:12:39.86#ibcon#first serial, iclass 36, count 0 2006.257.08:12:39.86#ibcon#enter sib2, iclass 36, count 0 2006.257.08:12:39.86#ibcon#flushed, iclass 36, count 0 2006.257.08:12:39.86#ibcon#about to write, iclass 36, count 0 2006.257.08:12:39.86#ibcon#wrote, iclass 36, count 0 2006.257.08:12:39.86#ibcon#about to read 3, iclass 36, count 0 2006.257.08:12:39.88#ibcon#read 3, iclass 36, count 0 2006.257.08:12:39.88#ibcon#about to read 4, iclass 36, count 0 2006.257.08:12:39.88#ibcon#read 4, iclass 36, count 0 2006.257.08:12:39.88#ibcon#about to read 5, iclass 36, count 0 2006.257.08:12:39.88#ibcon#read 5, iclass 36, count 0 2006.257.08:12:39.88#ibcon#about to read 6, iclass 36, count 0 2006.257.08:12:39.88#ibcon#read 6, iclass 36, count 0 2006.257.08:12:39.88#ibcon#end of sib2, iclass 36, count 0 2006.257.08:12:39.88#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:12:39.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:12:39.88#ibcon#[27=USB\r\n] 2006.257.08:12:39.88#ibcon#*before write, iclass 36, count 0 2006.257.08:12:39.88#ibcon#enter sib2, iclass 36, count 0 2006.257.08:12:39.88#ibcon#flushed, iclass 36, count 0 2006.257.08:12:39.88#ibcon#about to write, iclass 36, count 0 2006.257.08:12:39.88#ibcon#wrote, iclass 36, count 0 2006.257.08:12:39.88#ibcon#about to read 3, iclass 36, count 0 2006.257.08:12:39.91#ibcon#read 3, iclass 36, count 0 2006.257.08:12:39.91#ibcon#about to read 4, iclass 36, count 0 2006.257.08:12:39.91#ibcon#read 4, iclass 36, count 0 2006.257.08:12:39.91#ibcon#about to read 5, iclass 36, count 0 2006.257.08:12:39.91#ibcon#read 5, iclass 36, count 0 2006.257.08:12:39.91#ibcon#about to read 6, iclass 36, count 0 2006.257.08:12:39.91#ibcon#read 6, iclass 36, count 0 2006.257.08:12:39.91#ibcon#end of sib2, iclass 36, count 0 2006.257.08:12:39.91#ibcon#*after write, iclass 36, count 0 2006.257.08:12:39.91#ibcon#*before return 0, iclass 36, count 0 2006.257.08:12:39.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:39.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:12:39.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:12:39.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:12:39.91$vck44/vblo=7,734.99 2006.257.08:12:39.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.08:12:39.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.08:12:39.91#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:39.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:39.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:39.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:39.91#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:12:39.91#ibcon#first serial, iclass 38, count 0 2006.257.08:12:39.91#ibcon#enter sib2, iclass 38, count 0 2006.257.08:12:39.91#ibcon#flushed, iclass 38, count 0 2006.257.08:12:39.91#ibcon#about to write, iclass 38, count 0 2006.257.08:12:39.91#ibcon#wrote, iclass 38, count 0 2006.257.08:12:39.91#ibcon#about to read 3, iclass 38, count 0 2006.257.08:12:39.93#ibcon#read 3, iclass 38, count 0 2006.257.08:12:39.93#ibcon#about to read 4, iclass 38, count 0 2006.257.08:12:39.93#ibcon#read 4, iclass 38, count 0 2006.257.08:12:39.93#ibcon#about to read 5, iclass 38, count 0 2006.257.08:12:39.93#ibcon#read 5, iclass 38, count 0 2006.257.08:12:39.93#ibcon#about to read 6, iclass 38, count 0 2006.257.08:12:39.93#ibcon#read 6, iclass 38, count 0 2006.257.08:12:39.93#ibcon#end of sib2, iclass 38, count 0 2006.257.08:12:39.93#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:12:39.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:12:39.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:12:39.93#ibcon#*before write, iclass 38, count 0 2006.257.08:12:39.93#ibcon#enter sib2, iclass 38, count 0 2006.257.08:12:39.93#ibcon#flushed, iclass 38, count 0 2006.257.08:12:39.93#ibcon#about to write, iclass 38, count 0 2006.257.08:12:39.93#ibcon#wrote, iclass 38, count 0 2006.257.08:12:39.93#ibcon#about to read 3, iclass 38, count 0 2006.257.08:12:39.97#ibcon#read 3, iclass 38, count 0 2006.257.08:12:39.97#ibcon#about to read 4, iclass 38, count 0 2006.257.08:12:39.97#ibcon#read 4, iclass 38, count 0 2006.257.08:12:39.97#ibcon#about to read 5, iclass 38, count 0 2006.257.08:12:39.97#ibcon#read 5, iclass 38, count 0 2006.257.08:12:39.97#ibcon#about to read 6, iclass 38, count 0 2006.257.08:12:39.97#ibcon#read 6, iclass 38, count 0 2006.257.08:12:39.97#ibcon#end of sib2, iclass 38, count 0 2006.257.08:12:39.97#ibcon#*after write, iclass 38, count 0 2006.257.08:12:39.97#ibcon#*before return 0, iclass 38, count 0 2006.257.08:12:39.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:39.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:12:39.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:12:39.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:12:39.97$vck44/vb=7,4 2006.257.08:12:39.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.08:12:39.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.08:12:39.97#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:39.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:40.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:40.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:40.03#ibcon#enter wrdev, iclass 40, count 2 2006.257.08:12:40.03#ibcon#first serial, iclass 40, count 2 2006.257.08:12:40.03#ibcon#enter sib2, iclass 40, count 2 2006.257.08:12:40.03#ibcon#flushed, iclass 40, count 2 2006.257.08:12:40.03#ibcon#about to write, iclass 40, count 2 2006.257.08:12:40.03#ibcon#wrote, iclass 40, count 2 2006.257.08:12:40.03#ibcon#about to read 3, iclass 40, count 2 2006.257.08:12:40.05#ibcon#read 3, iclass 40, count 2 2006.257.08:12:40.05#ibcon#about to read 4, iclass 40, count 2 2006.257.08:12:40.05#ibcon#read 4, iclass 40, count 2 2006.257.08:12:40.05#ibcon#about to read 5, iclass 40, count 2 2006.257.08:12:40.05#ibcon#read 5, iclass 40, count 2 2006.257.08:12:40.05#ibcon#about to read 6, iclass 40, count 2 2006.257.08:12:40.05#ibcon#read 6, iclass 40, count 2 2006.257.08:12:40.05#ibcon#end of sib2, iclass 40, count 2 2006.257.08:12:40.05#ibcon#*mode == 0, iclass 40, count 2 2006.257.08:12:40.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.08:12:40.05#ibcon#[27=AT07-04\r\n] 2006.257.08:12:40.05#ibcon#*before write, iclass 40, count 2 2006.257.08:12:40.05#ibcon#enter sib2, iclass 40, count 2 2006.257.08:12:40.05#ibcon#flushed, iclass 40, count 2 2006.257.08:12:40.05#ibcon#about to write, iclass 40, count 2 2006.257.08:12:40.05#ibcon#wrote, iclass 40, count 2 2006.257.08:12:40.05#ibcon#about to read 3, iclass 40, count 2 2006.257.08:12:40.08#ibcon#read 3, iclass 40, count 2 2006.257.08:12:40.08#ibcon#about to read 4, iclass 40, count 2 2006.257.08:12:40.08#ibcon#read 4, iclass 40, count 2 2006.257.08:12:40.08#ibcon#about to read 5, iclass 40, count 2 2006.257.08:12:40.08#ibcon#read 5, iclass 40, count 2 2006.257.08:12:40.08#ibcon#about to read 6, iclass 40, count 2 2006.257.08:12:40.08#ibcon#read 6, iclass 40, count 2 2006.257.08:12:40.08#ibcon#end of sib2, iclass 40, count 2 2006.257.08:12:40.08#ibcon#*after write, iclass 40, count 2 2006.257.08:12:40.08#ibcon#*before return 0, iclass 40, count 2 2006.257.08:12:40.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:40.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:12:40.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.08:12:40.08#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:40.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:40.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:40.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:40.20#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:12:40.20#ibcon#first serial, iclass 40, count 0 2006.257.08:12:40.20#ibcon#enter sib2, iclass 40, count 0 2006.257.08:12:40.20#ibcon#flushed, iclass 40, count 0 2006.257.08:12:40.20#ibcon#about to write, iclass 40, count 0 2006.257.08:12:40.20#ibcon#wrote, iclass 40, count 0 2006.257.08:12:40.20#ibcon#about to read 3, iclass 40, count 0 2006.257.08:12:40.22#ibcon#read 3, iclass 40, count 0 2006.257.08:12:40.22#ibcon#about to read 4, iclass 40, count 0 2006.257.08:12:40.22#ibcon#read 4, iclass 40, count 0 2006.257.08:12:40.22#ibcon#about to read 5, iclass 40, count 0 2006.257.08:12:40.22#ibcon#read 5, iclass 40, count 0 2006.257.08:12:40.22#ibcon#about to read 6, iclass 40, count 0 2006.257.08:12:40.22#ibcon#read 6, iclass 40, count 0 2006.257.08:12:40.22#ibcon#end of sib2, iclass 40, count 0 2006.257.08:12:40.22#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:12:40.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:12:40.22#ibcon#[27=USB\r\n] 2006.257.08:12:40.22#ibcon#*before write, iclass 40, count 0 2006.257.08:12:40.22#ibcon#enter sib2, iclass 40, count 0 2006.257.08:12:40.22#ibcon#flushed, iclass 40, count 0 2006.257.08:12:40.22#ibcon#about to write, iclass 40, count 0 2006.257.08:12:40.22#ibcon#wrote, iclass 40, count 0 2006.257.08:12:40.22#ibcon#about to read 3, iclass 40, count 0 2006.257.08:12:40.25#ibcon#read 3, iclass 40, count 0 2006.257.08:12:40.25#ibcon#about to read 4, iclass 40, count 0 2006.257.08:12:40.25#ibcon#read 4, iclass 40, count 0 2006.257.08:12:40.25#ibcon#about to read 5, iclass 40, count 0 2006.257.08:12:40.25#ibcon#read 5, iclass 40, count 0 2006.257.08:12:40.25#ibcon#about to read 6, iclass 40, count 0 2006.257.08:12:40.25#ibcon#read 6, iclass 40, count 0 2006.257.08:12:40.25#ibcon#end of sib2, iclass 40, count 0 2006.257.08:12:40.25#ibcon#*after write, iclass 40, count 0 2006.257.08:12:40.25#ibcon#*before return 0, iclass 40, count 0 2006.257.08:12:40.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:40.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:12:40.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:12:40.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:12:40.25$vck44/vblo=8,744.99 2006.257.08:12:40.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.08:12:40.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.08:12:40.25#ibcon#ireg 17 cls_cnt 0 2006.257.08:12:40.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:12:40.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:12:40.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:12:40.25#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:12:40.25#ibcon#first serial, iclass 4, count 0 2006.257.08:12:40.25#ibcon#enter sib2, iclass 4, count 0 2006.257.08:12:40.25#ibcon#flushed, iclass 4, count 0 2006.257.08:12:40.25#ibcon#about to write, iclass 4, count 0 2006.257.08:12:40.25#ibcon#wrote, iclass 4, count 0 2006.257.08:12:40.25#ibcon#about to read 3, iclass 4, count 0 2006.257.08:12:40.27#ibcon#read 3, iclass 4, count 0 2006.257.08:12:40.27#ibcon#about to read 4, iclass 4, count 0 2006.257.08:12:40.27#ibcon#read 4, iclass 4, count 0 2006.257.08:12:40.27#ibcon#about to read 5, iclass 4, count 0 2006.257.08:12:40.27#ibcon#read 5, iclass 4, count 0 2006.257.08:12:40.27#ibcon#about to read 6, iclass 4, count 0 2006.257.08:12:40.27#ibcon#read 6, iclass 4, count 0 2006.257.08:12:40.27#ibcon#end of sib2, iclass 4, count 0 2006.257.08:12:40.27#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:12:40.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:12:40.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:12:40.27#ibcon#*before write, iclass 4, count 0 2006.257.08:12:40.27#ibcon#enter sib2, iclass 4, count 0 2006.257.08:12:40.27#ibcon#flushed, iclass 4, count 0 2006.257.08:12:40.27#ibcon#about to write, iclass 4, count 0 2006.257.08:12:40.27#ibcon#wrote, iclass 4, count 0 2006.257.08:12:40.27#ibcon#about to read 3, iclass 4, count 0 2006.257.08:12:40.31#ibcon#read 3, iclass 4, count 0 2006.257.08:12:40.31#ibcon#about to read 4, iclass 4, count 0 2006.257.08:12:40.31#ibcon#read 4, iclass 4, count 0 2006.257.08:12:40.31#ibcon#about to read 5, iclass 4, count 0 2006.257.08:12:40.31#ibcon#read 5, iclass 4, count 0 2006.257.08:12:40.31#ibcon#about to read 6, iclass 4, count 0 2006.257.08:12:40.31#ibcon#read 6, iclass 4, count 0 2006.257.08:12:40.31#ibcon#end of sib2, iclass 4, count 0 2006.257.08:12:40.31#ibcon#*after write, iclass 4, count 0 2006.257.08:12:40.31#ibcon#*before return 0, iclass 4, count 0 2006.257.08:12:40.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:12:40.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:12:40.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:12:40.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:12:40.31$vck44/vb=8,4 2006.257.08:12:40.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.08:12:40.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.08:12:40.31#ibcon#ireg 11 cls_cnt 2 2006.257.08:12:40.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:12:40.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:12:40.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:12:40.37#ibcon#enter wrdev, iclass 6, count 2 2006.257.08:12:40.37#ibcon#first serial, iclass 6, count 2 2006.257.08:12:40.37#ibcon#enter sib2, iclass 6, count 2 2006.257.08:12:40.37#ibcon#flushed, iclass 6, count 2 2006.257.08:12:40.37#ibcon#about to write, iclass 6, count 2 2006.257.08:12:40.37#ibcon#wrote, iclass 6, count 2 2006.257.08:12:40.37#ibcon#about to read 3, iclass 6, count 2 2006.257.08:12:40.39#ibcon#read 3, iclass 6, count 2 2006.257.08:12:40.39#ibcon#about to read 4, iclass 6, count 2 2006.257.08:12:40.39#ibcon#read 4, iclass 6, count 2 2006.257.08:12:40.39#ibcon#about to read 5, iclass 6, count 2 2006.257.08:12:40.39#ibcon#read 5, iclass 6, count 2 2006.257.08:12:40.39#ibcon#about to read 6, iclass 6, count 2 2006.257.08:12:40.39#ibcon#read 6, iclass 6, count 2 2006.257.08:12:40.39#ibcon#end of sib2, iclass 6, count 2 2006.257.08:12:40.39#ibcon#*mode == 0, iclass 6, count 2 2006.257.08:12:40.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.08:12:40.39#ibcon#[27=AT08-04\r\n] 2006.257.08:12:40.39#ibcon#*before write, iclass 6, count 2 2006.257.08:12:40.39#ibcon#enter sib2, iclass 6, count 2 2006.257.08:12:40.39#ibcon#flushed, iclass 6, count 2 2006.257.08:12:40.39#ibcon#about to write, iclass 6, count 2 2006.257.08:12:40.39#ibcon#wrote, iclass 6, count 2 2006.257.08:12:40.39#ibcon#about to read 3, iclass 6, count 2 2006.257.08:12:40.42#ibcon#read 3, iclass 6, count 2 2006.257.08:12:40.42#ibcon#about to read 4, iclass 6, count 2 2006.257.08:12:40.42#ibcon#read 4, iclass 6, count 2 2006.257.08:12:40.42#ibcon#about to read 5, iclass 6, count 2 2006.257.08:12:40.42#ibcon#read 5, iclass 6, count 2 2006.257.08:12:40.42#ibcon#about to read 6, iclass 6, count 2 2006.257.08:12:40.42#ibcon#read 6, iclass 6, count 2 2006.257.08:12:40.42#ibcon#end of sib2, iclass 6, count 2 2006.257.08:12:40.42#ibcon#*after write, iclass 6, count 2 2006.257.08:12:40.42#ibcon#*before return 0, iclass 6, count 2 2006.257.08:12:40.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:12:40.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:12:40.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.08:12:40.42#ibcon#ireg 7 cls_cnt 0 2006.257.08:12:40.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:12:40.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:12:40.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:12:40.54#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:12:40.54#ibcon#first serial, iclass 6, count 0 2006.257.08:12:40.54#ibcon#enter sib2, iclass 6, count 0 2006.257.08:12:40.54#ibcon#flushed, iclass 6, count 0 2006.257.08:12:40.54#ibcon#about to write, iclass 6, count 0 2006.257.08:12:40.54#ibcon#wrote, iclass 6, count 0 2006.257.08:12:40.54#ibcon#about to read 3, iclass 6, count 0 2006.257.08:12:40.56#ibcon#read 3, iclass 6, count 0 2006.257.08:12:40.56#ibcon#about to read 4, iclass 6, count 0 2006.257.08:12:40.56#ibcon#read 4, iclass 6, count 0 2006.257.08:12:40.56#ibcon#about to read 5, iclass 6, count 0 2006.257.08:12:40.56#ibcon#read 5, iclass 6, count 0 2006.257.08:12:40.56#ibcon#about to read 6, iclass 6, count 0 2006.257.08:12:40.56#ibcon#read 6, iclass 6, count 0 2006.257.08:12:40.56#ibcon#end of sib2, iclass 6, count 0 2006.257.08:12:40.56#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:12:40.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:12:40.56#ibcon#[27=USB\r\n] 2006.257.08:12:40.56#ibcon#*before write, iclass 6, count 0 2006.257.08:12:40.56#ibcon#enter sib2, iclass 6, count 0 2006.257.08:12:40.56#ibcon#flushed, iclass 6, count 0 2006.257.08:12:40.56#ibcon#about to write, iclass 6, count 0 2006.257.08:12:40.56#ibcon#wrote, iclass 6, count 0 2006.257.08:12:40.56#ibcon#about to read 3, iclass 6, count 0 2006.257.08:12:40.59#ibcon#read 3, iclass 6, count 0 2006.257.08:12:40.59#ibcon#about to read 4, iclass 6, count 0 2006.257.08:12:40.59#ibcon#read 4, iclass 6, count 0 2006.257.08:12:40.59#ibcon#about to read 5, iclass 6, count 0 2006.257.08:12:40.59#ibcon#read 5, iclass 6, count 0 2006.257.08:12:40.59#ibcon#about to read 6, iclass 6, count 0 2006.257.08:12:40.59#ibcon#read 6, iclass 6, count 0 2006.257.08:12:40.59#ibcon#end of sib2, iclass 6, count 0 2006.257.08:12:40.59#ibcon#*after write, iclass 6, count 0 2006.257.08:12:40.59#ibcon#*before return 0, iclass 6, count 0 2006.257.08:12:40.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:12:40.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:12:40.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:12:40.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:12:40.59$vck44/vabw=wide 2006.257.08:12:40.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.08:12:40.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.08:12:40.59#ibcon#ireg 8 cls_cnt 0 2006.257.08:12:40.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:12:40.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:12:40.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:12:40.59#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:12:40.59#ibcon#first serial, iclass 10, count 0 2006.257.08:12:40.59#ibcon#enter sib2, iclass 10, count 0 2006.257.08:12:40.59#ibcon#flushed, iclass 10, count 0 2006.257.08:12:40.59#ibcon#about to write, iclass 10, count 0 2006.257.08:12:40.59#ibcon#wrote, iclass 10, count 0 2006.257.08:12:40.59#ibcon#about to read 3, iclass 10, count 0 2006.257.08:12:40.61#ibcon#read 3, iclass 10, count 0 2006.257.08:12:40.61#ibcon#about to read 4, iclass 10, count 0 2006.257.08:12:40.61#ibcon#read 4, iclass 10, count 0 2006.257.08:12:40.61#ibcon#about to read 5, iclass 10, count 0 2006.257.08:12:40.61#ibcon#read 5, iclass 10, count 0 2006.257.08:12:40.61#ibcon#about to read 6, iclass 10, count 0 2006.257.08:12:40.61#ibcon#read 6, iclass 10, count 0 2006.257.08:12:40.61#ibcon#end of sib2, iclass 10, count 0 2006.257.08:12:40.61#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:12:40.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:12:40.61#ibcon#[25=BW32\r\n] 2006.257.08:12:40.61#ibcon#*before write, iclass 10, count 0 2006.257.08:12:40.61#ibcon#enter sib2, iclass 10, count 0 2006.257.08:12:40.61#ibcon#flushed, iclass 10, count 0 2006.257.08:12:40.61#ibcon#about to write, iclass 10, count 0 2006.257.08:12:40.61#ibcon#wrote, iclass 10, count 0 2006.257.08:12:40.61#ibcon#about to read 3, iclass 10, count 0 2006.257.08:12:40.64#ibcon#read 3, iclass 10, count 0 2006.257.08:12:40.64#ibcon#about to read 4, iclass 10, count 0 2006.257.08:12:40.64#ibcon#read 4, iclass 10, count 0 2006.257.08:12:40.64#ibcon#about to read 5, iclass 10, count 0 2006.257.08:12:40.64#ibcon#read 5, iclass 10, count 0 2006.257.08:12:40.64#ibcon#about to read 6, iclass 10, count 0 2006.257.08:12:40.64#ibcon#read 6, iclass 10, count 0 2006.257.08:12:40.64#ibcon#end of sib2, iclass 10, count 0 2006.257.08:12:40.64#ibcon#*after write, iclass 10, count 0 2006.257.08:12:40.64#ibcon#*before return 0, iclass 10, count 0 2006.257.08:12:40.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:12:40.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:12:40.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:12:40.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:12:40.64$vck44/vbbw=wide 2006.257.08:12:40.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.08:12:40.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.08:12:40.64#ibcon#ireg 8 cls_cnt 0 2006.257.08:12:40.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:12:40.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:12:40.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:12:40.71#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:12:40.71#ibcon#first serial, iclass 12, count 0 2006.257.08:12:40.71#ibcon#enter sib2, iclass 12, count 0 2006.257.08:12:40.71#ibcon#flushed, iclass 12, count 0 2006.257.08:12:40.71#ibcon#about to write, iclass 12, count 0 2006.257.08:12:40.71#ibcon#wrote, iclass 12, count 0 2006.257.08:12:40.71#ibcon#about to read 3, iclass 12, count 0 2006.257.08:12:40.73#ibcon#read 3, iclass 12, count 0 2006.257.08:12:40.73#ibcon#about to read 4, iclass 12, count 0 2006.257.08:12:40.73#ibcon#read 4, iclass 12, count 0 2006.257.08:12:40.73#ibcon#about to read 5, iclass 12, count 0 2006.257.08:12:40.73#ibcon#read 5, iclass 12, count 0 2006.257.08:12:40.73#ibcon#about to read 6, iclass 12, count 0 2006.257.08:12:40.73#ibcon#read 6, iclass 12, count 0 2006.257.08:12:40.73#ibcon#end of sib2, iclass 12, count 0 2006.257.08:12:40.73#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:12:40.73#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:12:40.73#ibcon#[27=BW32\r\n] 2006.257.08:12:40.73#ibcon#*before write, iclass 12, count 0 2006.257.08:12:40.73#ibcon#enter sib2, iclass 12, count 0 2006.257.08:12:40.73#ibcon#flushed, iclass 12, count 0 2006.257.08:12:40.73#ibcon#about to write, iclass 12, count 0 2006.257.08:12:40.73#ibcon#wrote, iclass 12, count 0 2006.257.08:12:40.73#ibcon#about to read 3, iclass 12, count 0 2006.257.08:12:40.76#ibcon#read 3, iclass 12, count 0 2006.257.08:12:40.76#ibcon#about to read 4, iclass 12, count 0 2006.257.08:12:40.76#ibcon#read 4, iclass 12, count 0 2006.257.08:12:40.76#ibcon#about to read 5, iclass 12, count 0 2006.257.08:12:40.76#ibcon#read 5, iclass 12, count 0 2006.257.08:12:40.76#ibcon#about to read 6, iclass 12, count 0 2006.257.08:12:40.76#ibcon#read 6, iclass 12, count 0 2006.257.08:12:40.76#ibcon#end of sib2, iclass 12, count 0 2006.257.08:12:40.76#ibcon#*after write, iclass 12, count 0 2006.257.08:12:40.76#ibcon#*before return 0, iclass 12, count 0 2006.257.08:12:40.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:12:40.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:12:40.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:12:40.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:12:40.76$setupk4/ifdk4 2006.257.08:12:40.76$ifdk4/lo= 2006.257.08:12:40.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:12:40.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:12:40.76$ifdk4/patch= 2006.257.08:12:40.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:12:40.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:12:40.76$setupk4/!*+20s 2006.257.08:12:47.81#abcon#<5=/16 1.5 6.2 20.82 881012.9\r\n> 2006.257.08:12:47.83#abcon#{5=INTERFACE CLEAR} 2006.257.08:12:47.89#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:12:55.25$setupk4/"tpicd 2006.257.08:12:55.25$setupk4/echo=off 2006.257.08:12:55.25$setupk4/xlog=off 2006.257.08:12:55.25:!2006.257.08:17:23 2006.257.08:13:09.14#trakl#Source acquired 2006.257.08:13:09.14#flagr#flagr/antenna,acquired 2006.257.08:17:23.00:preob 2006.257.08:17:23.14/onsource/TRACKING 2006.257.08:17:23.14:!2006.257.08:17:33 2006.257.08:17:33.00:"tape 2006.257.08:17:33.00:"st=record 2006.257.08:17:33.00:data_valid=on 2006.257.08:17:33.00:midob 2006.257.08:17:33.14/onsource/TRACKING 2006.257.08:17:33.14/wx/20.78,1012.9,88 2006.257.08:17:33.32/cable/+6.4755E-03 2006.257.08:17:34.41/va/01,08,usb,yes,32,34 2006.257.08:17:34.41/va/02,07,usb,yes,34,35 2006.257.08:17:34.41/va/03,08,usb,yes,31,33 2006.257.08:17:34.41/va/04,07,usb,yes,35,37 2006.257.08:17:34.41/va/05,04,usb,yes,32,32 2006.257.08:17:34.41/va/06,04,usb,yes,35,35 2006.257.08:17:34.41/va/07,04,usb,yes,36,37 2006.257.08:17:34.41/va/08,04,usb,yes,30,37 2006.257.08:17:34.64/valo/01,524.99,yes,locked 2006.257.08:17:34.64/valo/02,534.99,yes,locked 2006.257.08:17:34.64/valo/03,564.99,yes,locked 2006.257.08:17:34.64/valo/04,624.99,yes,locked 2006.257.08:17:34.64/valo/05,734.99,yes,locked 2006.257.08:17:34.64/valo/06,814.99,yes,locked 2006.257.08:17:34.64/valo/07,864.99,yes,locked 2006.257.08:17:34.64/valo/08,884.99,yes,locked 2006.257.08:17:35.73/vb/01,04,usb,yes,32,29 2006.257.08:17:35.73/vb/02,05,usb,yes,29,30 2006.257.08:17:35.73/vb/03,04,usb,yes,30,33 2006.257.08:17:35.73/vb/04,05,usb,yes,30,29 2006.257.08:17:35.73/vb/05,04,usb,yes,26,29 2006.257.08:17:35.73/vb/06,04,usb,yes,31,27 2006.257.08:17:35.73/vb/07,04,usb,yes,31,31 2006.257.08:17:35.73/vb/08,04,usb,yes,28,32 2006.257.08:17:35.97/vblo/01,629.99,yes,locked 2006.257.08:17:35.97/vblo/02,634.99,yes,locked 2006.257.08:17:35.97/vblo/03,649.99,yes,locked 2006.257.08:17:35.97/vblo/04,679.99,yes,locked 2006.257.08:17:35.97/vblo/05,709.99,yes,locked 2006.257.08:17:35.97/vblo/06,719.99,yes,locked 2006.257.08:17:35.97/vblo/07,734.99,yes,locked 2006.257.08:17:35.97/vblo/08,744.99,yes,locked 2006.257.08:17:36.12/vabw/8 2006.257.08:17:36.27/vbbw/8 2006.257.08:17:36.36/xfe/off,on,15.2 2006.257.08:17:36.73/ifatt/23,28,28,28 2006.257.08:17:37.07/fmout-gps/S +4.54E-07 2006.257.08:17:37.11:!2006.257.08:18:13 2006.257.08:18:13.00:data_valid=off 2006.257.08:18:13.00:"et 2006.257.08:18:13.00:!+3s 2006.257.08:18:16.02:"tape 2006.257.08:18:16.02:postob 2006.257.08:18:16.25/cable/+6.4738E-03 2006.257.08:18:16.25/wx/20.78,1012.9,89 2006.257.08:18:16.31/fmout-gps/S +4.53E-07 2006.257.08:18:16.31:scan_name=257-0819,jd0609,280 2006.257.08:18:16.31:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.257.08:18:18.14#flagr#flagr/antenna,new-source 2006.257.08:18:18.14:checkk5 2006.257.08:18:18.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:18:18.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:18:19.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:18:19.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:18:20.14/chk_obsdata//k5ts1/T2570817??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.08:18:20.56/chk_obsdata//k5ts2/T2570817??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.08:18:20.96/chk_obsdata//k5ts3/T2570817??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.08:18:21.37/chk_obsdata//k5ts4/T2570817??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.08:18:22.10/k5log//k5ts1_log_newline 2006.257.08:18:22.81/k5log//k5ts2_log_newline 2006.257.08:18:23.53/k5log//k5ts3_log_newline 2006.257.08:18:24.23/k5log//k5ts4_log_newline 2006.257.08:18:24.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:18:24.26:setupk4=1 2006.257.08:18:24.26$setupk4/echo=on 2006.257.08:18:24.26$setupk4/pcalon 2006.257.08:18:24.26$pcalon/"no phase cal control is implemented here 2006.257.08:18:24.26$setupk4/"tpicd=stop 2006.257.08:18:24.26$setupk4/"rec=synch_on 2006.257.08:18:24.26$setupk4/"rec_mode=128 2006.257.08:18:24.26$setupk4/!* 2006.257.08:18:24.26$setupk4/recpk4 2006.257.08:18:24.26$recpk4/recpatch= 2006.257.08:18:24.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:18:24.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:18:24.27$setupk4/vck44 2006.257.08:18:24.27$vck44/valo=1,524.99 2006.257.08:18:24.27#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.08:18:24.27#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.08:18:24.27#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:24.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:24.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:24.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:24.27#ibcon#enter wrdev, iclass 7, count 0 2006.257.08:18:24.27#ibcon#first serial, iclass 7, count 0 2006.257.08:18:24.27#ibcon#enter sib2, iclass 7, count 0 2006.257.08:18:24.27#ibcon#flushed, iclass 7, count 0 2006.257.08:18:24.27#ibcon#about to write, iclass 7, count 0 2006.257.08:18:24.27#ibcon#wrote, iclass 7, count 0 2006.257.08:18:24.27#ibcon#about to read 3, iclass 7, count 0 2006.257.08:18:24.29#ibcon#read 3, iclass 7, count 0 2006.257.08:18:24.29#ibcon#about to read 4, iclass 7, count 0 2006.257.08:18:24.29#ibcon#read 4, iclass 7, count 0 2006.257.08:18:24.29#ibcon#about to read 5, iclass 7, count 0 2006.257.08:18:24.29#ibcon#read 5, iclass 7, count 0 2006.257.08:18:24.29#ibcon#about to read 6, iclass 7, count 0 2006.257.08:18:24.29#ibcon#read 6, iclass 7, count 0 2006.257.08:18:24.29#ibcon#end of sib2, iclass 7, count 0 2006.257.08:18:24.29#ibcon#*mode == 0, iclass 7, count 0 2006.257.08:18:24.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.08:18:24.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:18:24.29#ibcon#*before write, iclass 7, count 0 2006.257.08:18:24.29#ibcon#enter sib2, iclass 7, count 0 2006.257.08:18:24.29#ibcon#flushed, iclass 7, count 0 2006.257.08:18:24.29#ibcon#about to write, iclass 7, count 0 2006.257.08:18:24.29#ibcon#wrote, iclass 7, count 0 2006.257.08:18:24.29#ibcon#about to read 3, iclass 7, count 0 2006.257.08:18:24.34#ibcon#read 3, iclass 7, count 0 2006.257.08:18:24.34#ibcon#about to read 4, iclass 7, count 0 2006.257.08:18:24.34#ibcon#read 4, iclass 7, count 0 2006.257.08:18:24.34#ibcon#about to read 5, iclass 7, count 0 2006.257.08:18:24.34#ibcon#read 5, iclass 7, count 0 2006.257.08:18:24.34#ibcon#about to read 6, iclass 7, count 0 2006.257.08:18:24.34#ibcon#read 6, iclass 7, count 0 2006.257.08:18:24.34#ibcon#end of sib2, iclass 7, count 0 2006.257.08:18:24.34#ibcon#*after write, iclass 7, count 0 2006.257.08:18:24.34#ibcon#*before return 0, iclass 7, count 0 2006.257.08:18:24.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:24.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:24.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.08:18:24.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.08:18:24.34$vck44/va=1,8 2006.257.08:18:24.34#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.08:18:24.34#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.08:18:24.34#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:24.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:24.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:24.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:24.34#ibcon#enter wrdev, iclass 11, count 2 2006.257.08:18:24.34#ibcon#first serial, iclass 11, count 2 2006.257.08:18:24.34#ibcon#enter sib2, iclass 11, count 2 2006.257.08:18:24.34#ibcon#flushed, iclass 11, count 2 2006.257.08:18:24.34#ibcon#about to write, iclass 11, count 2 2006.257.08:18:24.34#ibcon#wrote, iclass 11, count 2 2006.257.08:18:24.34#ibcon#about to read 3, iclass 11, count 2 2006.257.08:18:24.36#ibcon#read 3, iclass 11, count 2 2006.257.08:18:24.36#ibcon#about to read 4, iclass 11, count 2 2006.257.08:18:24.36#ibcon#read 4, iclass 11, count 2 2006.257.08:18:24.36#ibcon#about to read 5, iclass 11, count 2 2006.257.08:18:24.36#ibcon#read 5, iclass 11, count 2 2006.257.08:18:24.36#ibcon#about to read 6, iclass 11, count 2 2006.257.08:18:24.36#ibcon#read 6, iclass 11, count 2 2006.257.08:18:24.36#ibcon#end of sib2, iclass 11, count 2 2006.257.08:18:24.36#ibcon#*mode == 0, iclass 11, count 2 2006.257.08:18:24.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.08:18:24.36#ibcon#[25=AT01-08\r\n] 2006.257.08:18:24.36#ibcon#*before write, iclass 11, count 2 2006.257.08:18:24.36#ibcon#enter sib2, iclass 11, count 2 2006.257.08:18:24.36#ibcon#flushed, iclass 11, count 2 2006.257.08:18:24.36#ibcon#about to write, iclass 11, count 2 2006.257.08:18:24.36#ibcon#wrote, iclass 11, count 2 2006.257.08:18:24.36#ibcon#about to read 3, iclass 11, count 2 2006.257.08:18:24.39#ibcon#read 3, iclass 11, count 2 2006.257.08:18:24.39#ibcon#about to read 4, iclass 11, count 2 2006.257.08:18:24.39#ibcon#read 4, iclass 11, count 2 2006.257.08:18:24.39#ibcon#about to read 5, iclass 11, count 2 2006.257.08:18:24.39#ibcon#read 5, iclass 11, count 2 2006.257.08:18:24.39#ibcon#about to read 6, iclass 11, count 2 2006.257.08:18:24.39#ibcon#read 6, iclass 11, count 2 2006.257.08:18:24.39#ibcon#end of sib2, iclass 11, count 2 2006.257.08:18:24.39#ibcon#*after write, iclass 11, count 2 2006.257.08:18:24.39#ibcon#*before return 0, iclass 11, count 2 2006.257.08:18:24.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:24.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:24.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.08:18:24.39#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:24.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:24.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:24.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:24.51#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:18:24.51#ibcon#first serial, iclass 11, count 0 2006.257.08:18:24.51#ibcon#enter sib2, iclass 11, count 0 2006.257.08:18:24.51#ibcon#flushed, iclass 11, count 0 2006.257.08:18:24.51#ibcon#about to write, iclass 11, count 0 2006.257.08:18:24.51#ibcon#wrote, iclass 11, count 0 2006.257.08:18:24.51#ibcon#about to read 3, iclass 11, count 0 2006.257.08:18:24.53#ibcon#read 3, iclass 11, count 0 2006.257.08:18:24.53#ibcon#about to read 4, iclass 11, count 0 2006.257.08:18:24.53#ibcon#read 4, iclass 11, count 0 2006.257.08:18:24.53#ibcon#about to read 5, iclass 11, count 0 2006.257.08:18:24.53#ibcon#read 5, iclass 11, count 0 2006.257.08:18:24.53#ibcon#about to read 6, iclass 11, count 0 2006.257.08:18:24.53#ibcon#read 6, iclass 11, count 0 2006.257.08:18:24.53#ibcon#end of sib2, iclass 11, count 0 2006.257.08:18:24.53#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:18:24.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:18:24.53#ibcon#[25=USB\r\n] 2006.257.08:18:24.53#ibcon#*before write, iclass 11, count 0 2006.257.08:18:24.53#ibcon#enter sib2, iclass 11, count 0 2006.257.08:18:24.53#ibcon#flushed, iclass 11, count 0 2006.257.08:18:24.53#ibcon#about to write, iclass 11, count 0 2006.257.08:18:24.53#ibcon#wrote, iclass 11, count 0 2006.257.08:18:24.53#ibcon#about to read 3, iclass 11, count 0 2006.257.08:18:24.56#ibcon#read 3, iclass 11, count 0 2006.257.08:18:24.56#ibcon#about to read 4, iclass 11, count 0 2006.257.08:18:24.56#ibcon#read 4, iclass 11, count 0 2006.257.08:18:24.56#ibcon#about to read 5, iclass 11, count 0 2006.257.08:18:24.56#ibcon#read 5, iclass 11, count 0 2006.257.08:18:24.56#ibcon#about to read 6, iclass 11, count 0 2006.257.08:18:24.56#ibcon#read 6, iclass 11, count 0 2006.257.08:18:24.56#ibcon#end of sib2, iclass 11, count 0 2006.257.08:18:24.56#ibcon#*after write, iclass 11, count 0 2006.257.08:18:24.56#ibcon#*before return 0, iclass 11, count 0 2006.257.08:18:24.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:24.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:24.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:18:24.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:18:24.56$vck44/valo=2,534.99 2006.257.08:18:24.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.08:18:24.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.08:18:24.56#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:24.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:24.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:24.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:24.56#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:18:24.56#ibcon#first serial, iclass 13, count 0 2006.257.08:18:24.56#ibcon#enter sib2, iclass 13, count 0 2006.257.08:18:24.56#ibcon#flushed, iclass 13, count 0 2006.257.08:18:24.56#ibcon#about to write, iclass 13, count 0 2006.257.08:18:24.56#ibcon#wrote, iclass 13, count 0 2006.257.08:18:24.56#ibcon#about to read 3, iclass 13, count 0 2006.257.08:18:24.58#ibcon#read 3, iclass 13, count 0 2006.257.08:18:24.58#ibcon#about to read 4, iclass 13, count 0 2006.257.08:18:24.58#ibcon#read 4, iclass 13, count 0 2006.257.08:18:24.58#ibcon#about to read 5, iclass 13, count 0 2006.257.08:18:24.58#ibcon#read 5, iclass 13, count 0 2006.257.08:18:24.58#ibcon#about to read 6, iclass 13, count 0 2006.257.08:18:24.58#ibcon#read 6, iclass 13, count 0 2006.257.08:18:24.58#ibcon#end of sib2, iclass 13, count 0 2006.257.08:18:24.58#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:18:24.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:18:24.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:18:24.58#ibcon#*before write, iclass 13, count 0 2006.257.08:18:24.58#ibcon#enter sib2, iclass 13, count 0 2006.257.08:18:24.58#ibcon#flushed, iclass 13, count 0 2006.257.08:18:24.58#ibcon#about to write, iclass 13, count 0 2006.257.08:18:24.58#ibcon#wrote, iclass 13, count 0 2006.257.08:18:24.58#ibcon#about to read 3, iclass 13, count 0 2006.257.08:18:24.62#ibcon#read 3, iclass 13, count 0 2006.257.08:18:24.62#ibcon#about to read 4, iclass 13, count 0 2006.257.08:18:24.62#ibcon#read 4, iclass 13, count 0 2006.257.08:18:24.62#ibcon#about to read 5, iclass 13, count 0 2006.257.08:18:24.62#ibcon#read 5, iclass 13, count 0 2006.257.08:18:24.62#ibcon#about to read 6, iclass 13, count 0 2006.257.08:18:24.62#ibcon#read 6, iclass 13, count 0 2006.257.08:18:24.62#ibcon#end of sib2, iclass 13, count 0 2006.257.08:18:24.62#ibcon#*after write, iclass 13, count 0 2006.257.08:18:24.62#ibcon#*before return 0, iclass 13, count 0 2006.257.08:18:24.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:24.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:24.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:18:24.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:18:24.62$vck44/va=2,7 2006.257.08:18:24.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.08:18:24.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.08:18:24.62#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:24.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:24.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:24.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:24.68#ibcon#enter wrdev, iclass 15, count 2 2006.257.08:18:24.68#ibcon#first serial, iclass 15, count 2 2006.257.08:18:24.68#ibcon#enter sib2, iclass 15, count 2 2006.257.08:18:24.68#ibcon#flushed, iclass 15, count 2 2006.257.08:18:24.68#ibcon#about to write, iclass 15, count 2 2006.257.08:18:24.68#ibcon#wrote, iclass 15, count 2 2006.257.08:18:24.68#ibcon#about to read 3, iclass 15, count 2 2006.257.08:18:24.70#ibcon#read 3, iclass 15, count 2 2006.257.08:18:24.70#ibcon#about to read 4, iclass 15, count 2 2006.257.08:18:24.70#ibcon#read 4, iclass 15, count 2 2006.257.08:18:24.70#ibcon#about to read 5, iclass 15, count 2 2006.257.08:18:24.70#ibcon#read 5, iclass 15, count 2 2006.257.08:18:24.70#ibcon#about to read 6, iclass 15, count 2 2006.257.08:18:24.70#ibcon#read 6, iclass 15, count 2 2006.257.08:18:24.70#ibcon#end of sib2, iclass 15, count 2 2006.257.08:18:24.70#ibcon#*mode == 0, iclass 15, count 2 2006.257.08:18:24.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.08:18:24.70#ibcon#[25=AT02-07\r\n] 2006.257.08:18:24.70#ibcon#*before write, iclass 15, count 2 2006.257.08:18:24.70#ibcon#enter sib2, iclass 15, count 2 2006.257.08:18:24.70#ibcon#flushed, iclass 15, count 2 2006.257.08:18:24.70#ibcon#about to write, iclass 15, count 2 2006.257.08:18:24.70#ibcon#wrote, iclass 15, count 2 2006.257.08:18:24.70#ibcon#about to read 3, iclass 15, count 2 2006.257.08:18:24.73#ibcon#read 3, iclass 15, count 2 2006.257.08:18:24.73#ibcon#about to read 4, iclass 15, count 2 2006.257.08:18:24.73#ibcon#read 4, iclass 15, count 2 2006.257.08:18:24.73#ibcon#about to read 5, iclass 15, count 2 2006.257.08:18:24.73#ibcon#read 5, iclass 15, count 2 2006.257.08:18:24.73#ibcon#about to read 6, iclass 15, count 2 2006.257.08:18:24.73#ibcon#read 6, iclass 15, count 2 2006.257.08:18:24.73#ibcon#end of sib2, iclass 15, count 2 2006.257.08:18:24.73#ibcon#*after write, iclass 15, count 2 2006.257.08:18:24.73#ibcon#*before return 0, iclass 15, count 2 2006.257.08:18:24.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:24.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:24.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.08:18:24.73#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:24.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:24.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:24.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:24.85#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:18:24.85#ibcon#first serial, iclass 15, count 0 2006.257.08:18:24.85#ibcon#enter sib2, iclass 15, count 0 2006.257.08:18:24.85#ibcon#flushed, iclass 15, count 0 2006.257.08:18:24.85#ibcon#about to write, iclass 15, count 0 2006.257.08:18:24.85#ibcon#wrote, iclass 15, count 0 2006.257.08:18:24.85#ibcon#about to read 3, iclass 15, count 0 2006.257.08:18:24.87#ibcon#read 3, iclass 15, count 0 2006.257.08:18:24.87#ibcon#about to read 4, iclass 15, count 0 2006.257.08:18:24.87#ibcon#read 4, iclass 15, count 0 2006.257.08:18:24.87#ibcon#about to read 5, iclass 15, count 0 2006.257.08:18:24.87#ibcon#read 5, iclass 15, count 0 2006.257.08:18:24.87#ibcon#about to read 6, iclass 15, count 0 2006.257.08:18:24.87#ibcon#read 6, iclass 15, count 0 2006.257.08:18:24.87#ibcon#end of sib2, iclass 15, count 0 2006.257.08:18:24.87#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:18:24.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:18:24.87#ibcon#[25=USB\r\n] 2006.257.08:18:24.87#ibcon#*before write, iclass 15, count 0 2006.257.08:18:24.87#ibcon#enter sib2, iclass 15, count 0 2006.257.08:18:24.87#ibcon#flushed, iclass 15, count 0 2006.257.08:18:24.87#ibcon#about to write, iclass 15, count 0 2006.257.08:18:24.87#ibcon#wrote, iclass 15, count 0 2006.257.08:18:24.87#ibcon#about to read 3, iclass 15, count 0 2006.257.08:18:24.90#ibcon#read 3, iclass 15, count 0 2006.257.08:18:24.90#ibcon#about to read 4, iclass 15, count 0 2006.257.08:18:24.90#ibcon#read 4, iclass 15, count 0 2006.257.08:18:24.90#ibcon#about to read 5, iclass 15, count 0 2006.257.08:18:24.90#ibcon#read 5, iclass 15, count 0 2006.257.08:18:24.90#ibcon#about to read 6, iclass 15, count 0 2006.257.08:18:24.90#ibcon#read 6, iclass 15, count 0 2006.257.08:18:24.90#ibcon#end of sib2, iclass 15, count 0 2006.257.08:18:24.90#ibcon#*after write, iclass 15, count 0 2006.257.08:18:24.90#ibcon#*before return 0, iclass 15, count 0 2006.257.08:18:24.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:24.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:24.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:18:24.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:18:24.90$vck44/valo=3,564.99 2006.257.08:18:24.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.08:18:24.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.08:18:24.90#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:24.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:24.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:24.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:24.90#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:18:24.90#ibcon#first serial, iclass 17, count 0 2006.257.08:18:24.90#ibcon#enter sib2, iclass 17, count 0 2006.257.08:18:24.90#ibcon#flushed, iclass 17, count 0 2006.257.08:18:24.90#ibcon#about to write, iclass 17, count 0 2006.257.08:18:24.90#ibcon#wrote, iclass 17, count 0 2006.257.08:18:24.90#ibcon#about to read 3, iclass 17, count 0 2006.257.08:18:24.92#ibcon#read 3, iclass 17, count 0 2006.257.08:18:24.92#ibcon#about to read 4, iclass 17, count 0 2006.257.08:18:24.92#ibcon#read 4, iclass 17, count 0 2006.257.08:18:24.92#ibcon#about to read 5, iclass 17, count 0 2006.257.08:18:24.92#ibcon#read 5, iclass 17, count 0 2006.257.08:18:24.92#ibcon#about to read 6, iclass 17, count 0 2006.257.08:18:24.92#ibcon#read 6, iclass 17, count 0 2006.257.08:18:24.92#ibcon#end of sib2, iclass 17, count 0 2006.257.08:18:24.92#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:18:24.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:18:24.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:18:24.92#ibcon#*before write, iclass 17, count 0 2006.257.08:18:24.92#ibcon#enter sib2, iclass 17, count 0 2006.257.08:18:24.92#ibcon#flushed, iclass 17, count 0 2006.257.08:18:24.92#ibcon#about to write, iclass 17, count 0 2006.257.08:18:24.92#ibcon#wrote, iclass 17, count 0 2006.257.08:18:24.92#ibcon#about to read 3, iclass 17, count 0 2006.257.08:18:24.96#ibcon#read 3, iclass 17, count 0 2006.257.08:18:24.96#ibcon#about to read 4, iclass 17, count 0 2006.257.08:18:24.96#ibcon#read 4, iclass 17, count 0 2006.257.08:18:24.96#ibcon#about to read 5, iclass 17, count 0 2006.257.08:18:24.96#ibcon#read 5, iclass 17, count 0 2006.257.08:18:24.96#ibcon#about to read 6, iclass 17, count 0 2006.257.08:18:24.96#ibcon#read 6, iclass 17, count 0 2006.257.08:18:24.96#ibcon#end of sib2, iclass 17, count 0 2006.257.08:18:24.96#ibcon#*after write, iclass 17, count 0 2006.257.08:18:24.96#ibcon#*before return 0, iclass 17, count 0 2006.257.08:18:24.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:24.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:24.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:18:24.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:18:24.96$vck44/va=3,8 2006.257.08:18:24.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.08:18:24.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.08:18:24.96#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:24.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:25.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:25.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:25.02#ibcon#enter wrdev, iclass 19, count 2 2006.257.08:18:25.02#ibcon#first serial, iclass 19, count 2 2006.257.08:18:25.02#ibcon#enter sib2, iclass 19, count 2 2006.257.08:18:25.02#ibcon#flushed, iclass 19, count 2 2006.257.08:18:25.02#ibcon#about to write, iclass 19, count 2 2006.257.08:18:25.02#ibcon#wrote, iclass 19, count 2 2006.257.08:18:25.02#ibcon#about to read 3, iclass 19, count 2 2006.257.08:18:25.04#ibcon#read 3, iclass 19, count 2 2006.257.08:18:25.04#ibcon#about to read 4, iclass 19, count 2 2006.257.08:18:25.04#ibcon#read 4, iclass 19, count 2 2006.257.08:18:25.04#ibcon#about to read 5, iclass 19, count 2 2006.257.08:18:25.04#ibcon#read 5, iclass 19, count 2 2006.257.08:18:25.04#ibcon#about to read 6, iclass 19, count 2 2006.257.08:18:25.04#ibcon#read 6, iclass 19, count 2 2006.257.08:18:25.04#ibcon#end of sib2, iclass 19, count 2 2006.257.08:18:25.04#ibcon#*mode == 0, iclass 19, count 2 2006.257.08:18:25.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.08:18:25.04#ibcon#[25=AT03-08\r\n] 2006.257.08:18:25.04#ibcon#*before write, iclass 19, count 2 2006.257.08:18:25.04#ibcon#enter sib2, iclass 19, count 2 2006.257.08:18:25.04#ibcon#flushed, iclass 19, count 2 2006.257.08:18:25.04#ibcon#about to write, iclass 19, count 2 2006.257.08:18:25.04#ibcon#wrote, iclass 19, count 2 2006.257.08:18:25.04#ibcon#about to read 3, iclass 19, count 2 2006.257.08:18:25.07#ibcon#read 3, iclass 19, count 2 2006.257.08:18:25.07#ibcon#about to read 4, iclass 19, count 2 2006.257.08:18:25.07#ibcon#read 4, iclass 19, count 2 2006.257.08:18:25.07#ibcon#about to read 5, iclass 19, count 2 2006.257.08:18:25.07#ibcon#read 5, iclass 19, count 2 2006.257.08:18:25.07#ibcon#about to read 6, iclass 19, count 2 2006.257.08:18:25.07#ibcon#read 6, iclass 19, count 2 2006.257.08:18:25.07#ibcon#end of sib2, iclass 19, count 2 2006.257.08:18:25.07#ibcon#*after write, iclass 19, count 2 2006.257.08:18:25.07#ibcon#*before return 0, iclass 19, count 2 2006.257.08:18:25.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:25.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:25.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.08:18:25.07#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:25.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:25.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:25.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:25.19#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:18:25.19#ibcon#first serial, iclass 19, count 0 2006.257.08:18:25.19#ibcon#enter sib2, iclass 19, count 0 2006.257.08:18:25.19#ibcon#flushed, iclass 19, count 0 2006.257.08:18:25.19#ibcon#about to write, iclass 19, count 0 2006.257.08:18:25.19#ibcon#wrote, iclass 19, count 0 2006.257.08:18:25.19#ibcon#about to read 3, iclass 19, count 0 2006.257.08:18:25.21#ibcon#read 3, iclass 19, count 0 2006.257.08:18:25.21#ibcon#about to read 4, iclass 19, count 0 2006.257.08:18:25.21#ibcon#read 4, iclass 19, count 0 2006.257.08:18:25.21#ibcon#about to read 5, iclass 19, count 0 2006.257.08:18:25.21#ibcon#read 5, iclass 19, count 0 2006.257.08:18:25.21#ibcon#about to read 6, iclass 19, count 0 2006.257.08:18:25.21#ibcon#read 6, iclass 19, count 0 2006.257.08:18:25.21#ibcon#end of sib2, iclass 19, count 0 2006.257.08:18:25.21#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:18:25.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:18:25.21#ibcon#[25=USB\r\n] 2006.257.08:18:25.21#ibcon#*before write, iclass 19, count 0 2006.257.08:18:25.21#ibcon#enter sib2, iclass 19, count 0 2006.257.08:18:25.21#ibcon#flushed, iclass 19, count 0 2006.257.08:18:25.21#ibcon#about to write, iclass 19, count 0 2006.257.08:18:25.21#ibcon#wrote, iclass 19, count 0 2006.257.08:18:25.21#ibcon#about to read 3, iclass 19, count 0 2006.257.08:18:25.24#ibcon#read 3, iclass 19, count 0 2006.257.08:18:25.24#ibcon#about to read 4, iclass 19, count 0 2006.257.08:18:25.24#ibcon#read 4, iclass 19, count 0 2006.257.08:18:25.24#ibcon#about to read 5, iclass 19, count 0 2006.257.08:18:25.24#ibcon#read 5, iclass 19, count 0 2006.257.08:18:25.24#ibcon#about to read 6, iclass 19, count 0 2006.257.08:18:25.24#ibcon#read 6, iclass 19, count 0 2006.257.08:18:25.24#ibcon#end of sib2, iclass 19, count 0 2006.257.08:18:25.24#ibcon#*after write, iclass 19, count 0 2006.257.08:18:25.24#ibcon#*before return 0, iclass 19, count 0 2006.257.08:18:25.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:25.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:25.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:18:25.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:18:25.24$vck44/valo=4,624.99 2006.257.08:18:25.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.08:18:25.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.08:18:25.24#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:25.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:25.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:25.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:25.24#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:18:25.24#ibcon#first serial, iclass 21, count 0 2006.257.08:18:25.24#ibcon#enter sib2, iclass 21, count 0 2006.257.08:18:25.24#ibcon#flushed, iclass 21, count 0 2006.257.08:18:25.24#ibcon#about to write, iclass 21, count 0 2006.257.08:18:25.24#ibcon#wrote, iclass 21, count 0 2006.257.08:18:25.24#ibcon#about to read 3, iclass 21, count 0 2006.257.08:18:25.26#ibcon#read 3, iclass 21, count 0 2006.257.08:18:25.26#ibcon#about to read 4, iclass 21, count 0 2006.257.08:18:25.26#ibcon#read 4, iclass 21, count 0 2006.257.08:18:25.26#ibcon#about to read 5, iclass 21, count 0 2006.257.08:18:25.26#ibcon#read 5, iclass 21, count 0 2006.257.08:18:25.26#ibcon#about to read 6, iclass 21, count 0 2006.257.08:18:25.26#ibcon#read 6, iclass 21, count 0 2006.257.08:18:25.26#ibcon#end of sib2, iclass 21, count 0 2006.257.08:18:25.26#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:18:25.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:18:25.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:18:25.26#ibcon#*before write, iclass 21, count 0 2006.257.08:18:25.26#ibcon#enter sib2, iclass 21, count 0 2006.257.08:18:25.26#ibcon#flushed, iclass 21, count 0 2006.257.08:18:25.26#ibcon#about to write, iclass 21, count 0 2006.257.08:18:25.26#ibcon#wrote, iclass 21, count 0 2006.257.08:18:25.26#ibcon#about to read 3, iclass 21, count 0 2006.257.08:18:25.30#ibcon#read 3, iclass 21, count 0 2006.257.08:18:25.30#ibcon#about to read 4, iclass 21, count 0 2006.257.08:18:25.30#ibcon#read 4, iclass 21, count 0 2006.257.08:18:25.30#ibcon#about to read 5, iclass 21, count 0 2006.257.08:18:25.30#ibcon#read 5, iclass 21, count 0 2006.257.08:18:25.30#ibcon#about to read 6, iclass 21, count 0 2006.257.08:18:25.30#ibcon#read 6, iclass 21, count 0 2006.257.08:18:25.30#ibcon#end of sib2, iclass 21, count 0 2006.257.08:18:25.30#ibcon#*after write, iclass 21, count 0 2006.257.08:18:25.30#ibcon#*before return 0, iclass 21, count 0 2006.257.08:18:25.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:25.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:25.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:18:25.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:18:25.30$vck44/va=4,7 2006.257.08:18:25.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.08:18:25.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.08:18:25.30#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:25.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:25.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:25.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:25.36#ibcon#enter wrdev, iclass 23, count 2 2006.257.08:18:25.36#ibcon#first serial, iclass 23, count 2 2006.257.08:18:25.36#ibcon#enter sib2, iclass 23, count 2 2006.257.08:18:25.36#ibcon#flushed, iclass 23, count 2 2006.257.08:18:25.36#ibcon#about to write, iclass 23, count 2 2006.257.08:18:25.36#ibcon#wrote, iclass 23, count 2 2006.257.08:18:25.36#ibcon#about to read 3, iclass 23, count 2 2006.257.08:18:25.38#ibcon#read 3, iclass 23, count 2 2006.257.08:18:25.38#ibcon#about to read 4, iclass 23, count 2 2006.257.08:18:25.38#ibcon#read 4, iclass 23, count 2 2006.257.08:18:25.38#ibcon#about to read 5, iclass 23, count 2 2006.257.08:18:25.38#ibcon#read 5, iclass 23, count 2 2006.257.08:18:25.38#ibcon#about to read 6, iclass 23, count 2 2006.257.08:18:25.38#ibcon#read 6, iclass 23, count 2 2006.257.08:18:25.38#ibcon#end of sib2, iclass 23, count 2 2006.257.08:18:25.38#ibcon#*mode == 0, iclass 23, count 2 2006.257.08:18:25.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.08:18:25.38#ibcon#[25=AT04-07\r\n] 2006.257.08:18:25.38#ibcon#*before write, iclass 23, count 2 2006.257.08:18:25.38#ibcon#enter sib2, iclass 23, count 2 2006.257.08:18:25.38#ibcon#flushed, iclass 23, count 2 2006.257.08:18:25.38#ibcon#about to write, iclass 23, count 2 2006.257.08:18:25.38#ibcon#wrote, iclass 23, count 2 2006.257.08:18:25.38#ibcon#about to read 3, iclass 23, count 2 2006.257.08:18:25.41#ibcon#read 3, iclass 23, count 2 2006.257.08:18:25.41#ibcon#about to read 4, iclass 23, count 2 2006.257.08:18:25.41#ibcon#read 4, iclass 23, count 2 2006.257.08:18:25.41#ibcon#about to read 5, iclass 23, count 2 2006.257.08:18:25.41#ibcon#read 5, iclass 23, count 2 2006.257.08:18:25.41#ibcon#about to read 6, iclass 23, count 2 2006.257.08:18:25.41#ibcon#read 6, iclass 23, count 2 2006.257.08:18:25.41#ibcon#end of sib2, iclass 23, count 2 2006.257.08:18:25.41#ibcon#*after write, iclass 23, count 2 2006.257.08:18:25.41#ibcon#*before return 0, iclass 23, count 2 2006.257.08:18:25.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:25.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:25.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.08:18:25.41#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:25.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:25.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:25.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:25.53#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:18:25.53#ibcon#first serial, iclass 23, count 0 2006.257.08:18:25.53#ibcon#enter sib2, iclass 23, count 0 2006.257.08:18:25.53#ibcon#flushed, iclass 23, count 0 2006.257.08:18:25.53#ibcon#about to write, iclass 23, count 0 2006.257.08:18:25.53#ibcon#wrote, iclass 23, count 0 2006.257.08:18:25.53#ibcon#about to read 3, iclass 23, count 0 2006.257.08:18:25.55#ibcon#read 3, iclass 23, count 0 2006.257.08:18:25.55#ibcon#about to read 4, iclass 23, count 0 2006.257.08:18:25.55#ibcon#read 4, iclass 23, count 0 2006.257.08:18:25.55#ibcon#about to read 5, iclass 23, count 0 2006.257.08:18:25.55#ibcon#read 5, iclass 23, count 0 2006.257.08:18:25.55#ibcon#about to read 6, iclass 23, count 0 2006.257.08:18:25.55#ibcon#read 6, iclass 23, count 0 2006.257.08:18:25.55#ibcon#end of sib2, iclass 23, count 0 2006.257.08:18:25.55#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:18:25.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:18:25.55#ibcon#[25=USB\r\n] 2006.257.08:18:25.55#ibcon#*before write, iclass 23, count 0 2006.257.08:18:25.55#ibcon#enter sib2, iclass 23, count 0 2006.257.08:18:25.55#ibcon#flushed, iclass 23, count 0 2006.257.08:18:25.55#ibcon#about to write, iclass 23, count 0 2006.257.08:18:25.55#ibcon#wrote, iclass 23, count 0 2006.257.08:18:25.55#ibcon#about to read 3, iclass 23, count 0 2006.257.08:18:25.58#ibcon#read 3, iclass 23, count 0 2006.257.08:18:25.58#ibcon#about to read 4, iclass 23, count 0 2006.257.08:18:25.58#ibcon#read 4, iclass 23, count 0 2006.257.08:18:25.58#ibcon#about to read 5, iclass 23, count 0 2006.257.08:18:25.58#ibcon#read 5, iclass 23, count 0 2006.257.08:18:25.58#ibcon#about to read 6, iclass 23, count 0 2006.257.08:18:25.58#ibcon#read 6, iclass 23, count 0 2006.257.08:18:25.58#ibcon#end of sib2, iclass 23, count 0 2006.257.08:18:25.58#ibcon#*after write, iclass 23, count 0 2006.257.08:18:25.58#ibcon#*before return 0, iclass 23, count 0 2006.257.08:18:25.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:25.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:25.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:18:25.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:18:25.58$vck44/valo=5,734.99 2006.257.08:18:25.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.08:18:25.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.08:18:25.58#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:25.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:25.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:25.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:25.58#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:18:25.58#ibcon#first serial, iclass 25, count 0 2006.257.08:18:25.58#ibcon#enter sib2, iclass 25, count 0 2006.257.08:18:25.58#ibcon#flushed, iclass 25, count 0 2006.257.08:18:25.58#ibcon#about to write, iclass 25, count 0 2006.257.08:18:25.58#ibcon#wrote, iclass 25, count 0 2006.257.08:18:25.58#ibcon#about to read 3, iclass 25, count 0 2006.257.08:18:25.60#ibcon#read 3, iclass 25, count 0 2006.257.08:18:25.60#ibcon#about to read 4, iclass 25, count 0 2006.257.08:18:25.60#ibcon#read 4, iclass 25, count 0 2006.257.08:18:25.60#ibcon#about to read 5, iclass 25, count 0 2006.257.08:18:25.60#ibcon#read 5, iclass 25, count 0 2006.257.08:18:25.60#ibcon#about to read 6, iclass 25, count 0 2006.257.08:18:25.60#ibcon#read 6, iclass 25, count 0 2006.257.08:18:25.60#ibcon#end of sib2, iclass 25, count 0 2006.257.08:18:25.60#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:18:25.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:18:25.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:18:25.60#ibcon#*before write, iclass 25, count 0 2006.257.08:18:25.60#ibcon#enter sib2, iclass 25, count 0 2006.257.08:18:25.60#ibcon#flushed, iclass 25, count 0 2006.257.08:18:25.60#ibcon#about to write, iclass 25, count 0 2006.257.08:18:25.60#ibcon#wrote, iclass 25, count 0 2006.257.08:18:25.60#ibcon#about to read 3, iclass 25, count 0 2006.257.08:18:25.64#ibcon#read 3, iclass 25, count 0 2006.257.08:18:25.64#ibcon#about to read 4, iclass 25, count 0 2006.257.08:18:25.64#ibcon#read 4, iclass 25, count 0 2006.257.08:18:25.64#ibcon#about to read 5, iclass 25, count 0 2006.257.08:18:25.64#ibcon#read 5, iclass 25, count 0 2006.257.08:18:25.64#ibcon#about to read 6, iclass 25, count 0 2006.257.08:18:25.64#ibcon#read 6, iclass 25, count 0 2006.257.08:18:25.64#ibcon#end of sib2, iclass 25, count 0 2006.257.08:18:25.64#ibcon#*after write, iclass 25, count 0 2006.257.08:18:25.64#ibcon#*before return 0, iclass 25, count 0 2006.257.08:18:25.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:25.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:25.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:18:25.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:18:25.64$vck44/va=5,4 2006.257.08:18:25.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.08:18:25.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.08:18:25.64#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:25.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:25.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:25.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:25.70#ibcon#enter wrdev, iclass 27, count 2 2006.257.08:18:25.70#ibcon#first serial, iclass 27, count 2 2006.257.08:18:25.70#ibcon#enter sib2, iclass 27, count 2 2006.257.08:18:25.70#ibcon#flushed, iclass 27, count 2 2006.257.08:18:25.70#ibcon#about to write, iclass 27, count 2 2006.257.08:18:25.70#ibcon#wrote, iclass 27, count 2 2006.257.08:18:25.70#ibcon#about to read 3, iclass 27, count 2 2006.257.08:18:25.72#ibcon#read 3, iclass 27, count 2 2006.257.08:18:25.72#ibcon#about to read 4, iclass 27, count 2 2006.257.08:18:25.72#ibcon#read 4, iclass 27, count 2 2006.257.08:18:25.72#ibcon#about to read 5, iclass 27, count 2 2006.257.08:18:25.72#ibcon#read 5, iclass 27, count 2 2006.257.08:18:25.72#ibcon#about to read 6, iclass 27, count 2 2006.257.08:18:25.72#ibcon#read 6, iclass 27, count 2 2006.257.08:18:25.72#ibcon#end of sib2, iclass 27, count 2 2006.257.08:18:25.72#ibcon#*mode == 0, iclass 27, count 2 2006.257.08:18:25.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.08:18:25.72#ibcon#[25=AT05-04\r\n] 2006.257.08:18:25.72#ibcon#*before write, iclass 27, count 2 2006.257.08:18:25.72#ibcon#enter sib2, iclass 27, count 2 2006.257.08:18:25.72#ibcon#flushed, iclass 27, count 2 2006.257.08:18:25.72#ibcon#about to write, iclass 27, count 2 2006.257.08:18:25.72#ibcon#wrote, iclass 27, count 2 2006.257.08:18:25.72#ibcon#about to read 3, iclass 27, count 2 2006.257.08:18:25.75#ibcon#read 3, iclass 27, count 2 2006.257.08:18:25.75#ibcon#about to read 4, iclass 27, count 2 2006.257.08:18:25.75#ibcon#read 4, iclass 27, count 2 2006.257.08:18:25.75#ibcon#about to read 5, iclass 27, count 2 2006.257.08:18:25.75#ibcon#read 5, iclass 27, count 2 2006.257.08:18:25.75#ibcon#about to read 6, iclass 27, count 2 2006.257.08:18:25.75#ibcon#read 6, iclass 27, count 2 2006.257.08:18:25.75#ibcon#end of sib2, iclass 27, count 2 2006.257.08:18:25.75#ibcon#*after write, iclass 27, count 2 2006.257.08:18:25.75#ibcon#*before return 0, iclass 27, count 2 2006.257.08:18:25.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:25.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:25.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.08:18:25.75#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:25.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:25.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:25.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:25.87#ibcon#enter wrdev, iclass 27, count 0 2006.257.08:18:25.87#ibcon#first serial, iclass 27, count 0 2006.257.08:18:25.87#ibcon#enter sib2, iclass 27, count 0 2006.257.08:18:25.87#ibcon#flushed, iclass 27, count 0 2006.257.08:18:25.87#ibcon#about to write, iclass 27, count 0 2006.257.08:18:25.87#ibcon#wrote, iclass 27, count 0 2006.257.08:18:25.87#ibcon#about to read 3, iclass 27, count 0 2006.257.08:18:25.89#ibcon#read 3, iclass 27, count 0 2006.257.08:18:25.89#ibcon#about to read 4, iclass 27, count 0 2006.257.08:18:25.89#ibcon#read 4, iclass 27, count 0 2006.257.08:18:25.89#ibcon#about to read 5, iclass 27, count 0 2006.257.08:18:25.89#ibcon#read 5, iclass 27, count 0 2006.257.08:18:25.89#ibcon#about to read 6, iclass 27, count 0 2006.257.08:18:25.89#ibcon#read 6, iclass 27, count 0 2006.257.08:18:25.89#ibcon#end of sib2, iclass 27, count 0 2006.257.08:18:25.89#ibcon#*mode == 0, iclass 27, count 0 2006.257.08:18:25.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.08:18:25.89#ibcon#[25=USB\r\n] 2006.257.08:18:25.89#ibcon#*before write, iclass 27, count 0 2006.257.08:18:25.89#ibcon#enter sib2, iclass 27, count 0 2006.257.08:18:25.89#ibcon#flushed, iclass 27, count 0 2006.257.08:18:25.89#ibcon#about to write, iclass 27, count 0 2006.257.08:18:25.89#ibcon#wrote, iclass 27, count 0 2006.257.08:18:25.89#ibcon#about to read 3, iclass 27, count 0 2006.257.08:18:25.92#ibcon#read 3, iclass 27, count 0 2006.257.08:18:25.92#ibcon#about to read 4, iclass 27, count 0 2006.257.08:18:25.92#ibcon#read 4, iclass 27, count 0 2006.257.08:18:25.92#ibcon#about to read 5, iclass 27, count 0 2006.257.08:18:25.92#ibcon#read 5, iclass 27, count 0 2006.257.08:18:25.92#ibcon#about to read 6, iclass 27, count 0 2006.257.08:18:25.92#ibcon#read 6, iclass 27, count 0 2006.257.08:18:25.92#ibcon#end of sib2, iclass 27, count 0 2006.257.08:18:25.92#ibcon#*after write, iclass 27, count 0 2006.257.08:18:25.92#ibcon#*before return 0, iclass 27, count 0 2006.257.08:18:25.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:25.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:25.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.08:18:25.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.08:18:25.92$vck44/valo=6,814.99 2006.257.08:18:25.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.08:18:25.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.08:18:25.92#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:25.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:25.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:25.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:25.92#ibcon#enter wrdev, iclass 29, count 0 2006.257.08:18:25.92#ibcon#first serial, iclass 29, count 0 2006.257.08:18:25.92#ibcon#enter sib2, iclass 29, count 0 2006.257.08:18:25.92#ibcon#flushed, iclass 29, count 0 2006.257.08:18:25.92#ibcon#about to write, iclass 29, count 0 2006.257.08:18:25.92#ibcon#wrote, iclass 29, count 0 2006.257.08:18:25.92#ibcon#about to read 3, iclass 29, count 0 2006.257.08:18:25.94#ibcon#read 3, iclass 29, count 0 2006.257.08:18:25.94#ibcon#about to read 4, iclass 29, count 0 2006.257.08:18:25.94#ibcon#read 4, iclass 29, count 0 2006.257.08:18:25.94#ibcon#about to read 5, iclass 29, count 0 2006.257.08:18:25.94#ibcon#read 5, iclass 29, count 0 2006.257.08:18:25.94#ibcon#about to read 6, iclass 29, count 0 2006.257.08:18:25.94#ibcon#read 6, iclass 29, count 0 2006.257.08:18:25.94#ibcon#end of sib2, iclass 29, count 0 2006.257.08:18:25.94#ibcon#*mode == 0, iclass 29, count 0 2006.257.08:18:25.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.08:18:25.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:18:25.94#ibcon#*before write, iclass 29, count 0 2006.257.08:18:25.94#ibcon#enter sib2, iclass 29, count 0 2006.257.08:18:25.94#ibcon#flushed, iclass 29, count 0 2006.257.08:18:25.94#ibcon#about to write, iclass 29, count 0 2006.257.08:18:25.94#ibcon#wrote, iclass 29, count 0 2006.257.08:18:25.94#ibcon#about to read 3, iclass 29, count 0 2006.257.08:18:25.98#ibcon#read 3, iclass 29, count 0 2006.257.08:18:25.98#ibcon#about to read 4, iclass 29, count 0 2006.257.08:18:25.98#ibcon#read 4, iclass 29, count 0 2006.257.08:18:25.98#ibcon#about to read 5, iclass 29, count 0 2006.257.08:18:25.98#ibcon#read 5, iclass 29, count 0 2006.257.08:18:25.98#ibcon#about to read 6, iclass 29, count 0 2006.257.08:18:25.98#ibcon#read 6, iclass 29, count 0 2006.257.08:18:25.98#ibcon#end of sib2, iclass 29, count 0 2006.257.08:18:25.98#ibcon#*after write, iclass 29, count 0 2006.257.08:18:25.98#ibcon#*before return 0, iclass 29, count 0 2006.257.08:18:25.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:25.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:25.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.08:18:25.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.08:18:25.98$vck44/va=6,4 2006.257.08:18:25.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.08:18:25.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.08:18:25.98#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:25.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:26.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:26.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:26.04#ibcon#enter wrdev, iclass 31, count 2 2006.257.08:18:26.04#ibcon#first serial, iclass 31, count 2 2006.257.08:18:26.04#ibcon#enter sib2, iclass 31, count 2 2006.257.08:18:26.04#ibcon#flushed, iclass 31, count 2 2006.257.08:18:26.04#ibcon#about to write, iclass 31, count 2 2006.257.08:18:26.04#ibcon#wrote, iclass 31, count 2 2006.257.08:18:26.04#ibcon#about to read 3, iclass 31, count 2 2006.257.08:18:26.06#ibcon#read 3, iclass 31, count 2 2006.257.08:18:26.06#ibcon#about to read 4, iclass 31, count 2 2006.257.08:18:26.06#ibcon#read 4, iclass 31, count 2 2006.257.08:18:26.06#ibcon#about to read 5, iclass 31, count 2 2006.257.08:18:26.06#ibcon#read 5, iclass 31, count 2 2006.257.08:18:26.06#ibcon#about to read 6, iclass 31, count 2 2006.257.08:18:26.06#ibcon#read 6, iclass 31, count 2 2006.257.08:18:26.06#ibcon#end of sib2, iclass 31, count 2 2006.257.08:18:26.06#ibcon#*mode == 0, iclass 31, count 2 2006.257.08:18:26.06#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.08:18:26.06#ibcon#[25=AT06-04\r\n] 2006.257.08:18:26.06#ibcon#*before write, iclass 31, count 2 2006.257.08:18:26.06#ibcon#enter sib2, iclass 31, count 2 2006.257.08:18:26.06#ibcon#flushed, iclass 31, count 2 2006.257.08:18:26.06#ibcon#about to write, iclass 31, count 2 2006.257.08:18:26.06#ibcon#wrote, iclass 31, count 2 2006.257.08:18:26.06#ibcon#about to read 3, iclass 31, count 2 2006.257.08:18:26.09#ibcon#read 3, iclass 31, count 2 2006.257.08:18:26.09#ibcon#about to read 4, iclass 31, count 2 2006.257.08:18:26.09#ibcon#read 4, iclass 31, count 2 2006.257.08:18:26.09#ibcon#about to read 5, iclass 31, count 2 2006.257.08:18:26.09#ibcon#read 5, iclass 31, count 2 2006.257.08:18:26.09#ibcon#about to read 6, iclass 31, count 2 2006.257.08:18:26.09#ibcon#read 6, iclass 31, count 2 2006.257.08:18:26.09#ibcon#end of sib2, iclass 31, count 2 2006.257.08:18:26.09#ibcon#*after write, iclass 31, count 2 2006.257.08:18:26.09#ibcon#*before return 0, iclass 31, count 2 2006.257.08:18:26.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:26.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:26.09#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.08:18:26.09#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:26.09#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:26.21#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:26.21#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:26.21#ibcon#enter wrdev, iclass 31, count 0 2006.257.08:18:26.21#ibcon#first serial, iclass 31, count 0 2006.257.08:18:26.21#ibcon#enter sib2, iclass 31, count 0 2006.257.08:18:26.21#ibcon#flushed, iclass 31, count 0 2006.257.08:18:26.21#ibcon#about to write, iclass 31, count 0 2006.257.08:18:26.21#ibcon#wrote, iclass 31, count 0 2006.257.08:18:26.21#ibcon#about to read 3, iclass 31, count 0 2006.257.08:18:26.23#ibcon#read 3, iclass 31, count 0 2006.257.08:18:26.23#ibcon#about to read 4, iclass 31, count 0 2006.257.08:18:26.23#ibcon#read 4, iclass 31, count 0 2006.257.08:18:26.23#ibcon#about to read 5, iclass 31, count 0 2006.257.08:18:26.23#ibcon#read 5, iclass 31, count 0 2006.257.08:18:26.23#ibcon#about to read 6, iclass 31, count 0 2006.257.08:18:26.23#ibcon#read 6, iclass 31, count 0 2006.257.08:18:26.23#ibcon#end of sib2, iclass 31, count 0 2006.257.08:18:26.23#ibcon#*mode == 0, iclass 31, count 0 2006.257.08:18:26.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.08:18:26.23#ibcon#[25=USB\r\n] 2006.257.08:18:26.23#ibcon#*before write, iclass 31, count 0 2006.257.08:18:26.23#ibcon#enter sib2, iclass 31, count 0 2006.257.08:18:26.23#ibcon#flushed, iclass 31, count 0 2006.257.08:18:26.23#ibcon#about to write, iclass 31, count 0 2006.257.08:18:26.23#ibcon#wrote, iclass 31, count 0 2006.257.08:18:26.23#ibcon#about to read 3, iclass 31, count 0 2006.257.08:18:26.26#ibcon#read 3, iclass 31, count 0 2006.257.08:18:26.26#ibcon#about to read 4, iclass 31, count 0 2006.257.08:18:26.26#ibcon#read 4, iclass 31, count 0 2006.257.08:18:26.26#ibcon#about to read 5, iclass 31, count 0 2006.257.08:18:26.26#ibcon#read 5, iclass 31, count 0 2006.257.08:18:26.26#ibcon#about to read 6, iclass 31, count 0 2006.257.08:18:26.26#ibcon#read 6, iclass 31, count 0 2006.257.08:18:26.26#ibcon#end of sib2, iclass 31, count 0 2006.257.08:18:26.26#ibcon#*after write, iclass 31, count 0 2006.257.08:18:26.26#ibcon#*before return 0, iclass 31, count 0 2006.257.08:18:26.26#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:26.26#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:26.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.08:18:26.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.08:18:26.26$vck44/valo=7,864.99 2006.257.08:18:26.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.08:18:26.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.08:18:26.26#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:26.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:26.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:26.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:26.26#ibcon#enter wrdev, iclass 33, count 0 2006.257.08:18:26.26#ibcon#first serial, iclass 33, count 0 2006.257.08:18:26.26#ibcon#enter sib2, iclass 33, count 0 2006.257.08:18:26.26#ibcon#flushed, iclass 33, count 0 2006.257.08:18:26.26#ibcon#about to write, iclass 33, count 0 2006.257.08:18:26.26#ibcon#wrote, iclass 33, count 0 2006.257.08:18:26.26#ibcon#about to read 3, iclass 33, count 0 2006.257.08:18:26.28#ibcon#read 3, iclass 33, count 0 2006.257.08:18:26.28#ibcon#about to read 4, iclass 33, count 0 2006.257.08:18:26.28#ibcon#read 4, iclass 33, count 0 2006.257.08:18:26.28#ibcon#about to read 5, iclass 33, count 0 2006.257.08:18:26.28#ibcon#read 5, iclass 33, count 0 2006.257.08:18:26.28#ibcon#about to read 6, iclass 33, count 0 2006.257.08:18:26.28#ibcon#read 6, iclass 33, count 0 2006.257.08:18:26.28#ibcon#end of sib2, iclass 33, count 0 2006.257.08:18:26.28#ibcon#*mode == 0, iclass 33, count 0 2006.257.08:18:26.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.08:18:26.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:18:26.28#ibcon#*before write, iclass 33, count 0 2006.257.08:18:26.28#ibcon#enter sib2, iclass 33, count 0 2006.257.08:18:26.28#ibcon#flushed, iclass 33, count 0 2006.257.08:18:26.28#ibcon#about to write, iclass 33, count 0 2006.257.08:18:26.28#ibcon#wrote, iclass 33, count 0 2006.257.08:18:26.28#ibcon#about to read 3, iclass 33, count 0 2006.257.08:18:26.32#ibcon#read 3, iclass 33, count 0 2006.257.08:18:26.32#ibcon#about to read 4, iclass 33, count 0 2006.257.08:18:26.32#ibcon#read 4, iclass 33, count 0 2006.257.08:18:26.32#ibcon#about to read 5, iclass 33, count 0 2006.257.08:18:26.32#ibcon#read 5, iclass 33, count 0 2006.257.08:18:26.32#ibcon#about to read 6, iclass 33, count 0 2006.257.08:18:26.32#ibcon#read 6, iclass 33, count 0 2006.257.08:18:26.32#ibcon#end of sib2, iclass 33, count 0 2006.257.08:18:26.32#ibcon#*after write, iclass 33, count 0 2006.257.08:18:26.32#ibcon#*before return 0, iclass 33, count 0 2006.257.08:18:26.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:26.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:26.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.08:18:26.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.08:18:26.32$vck44/va=7,4 2006.257.08:18:26.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.08:18:26.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.08:18:26.32#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:26.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:26.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:26.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:26.38#ibcon#enter wrdev, iclass 35, count 2 2006.257.08:18:26.38#ibcon#first serial, iclass 35, count 2 2006.257.08:18:26.38#ibcon#enter sib2, iclass 35, count 2 2006.257.08:18:26.38#ibcon#flushed, iclass 35, count 2 2006.257.08:18:26.38#ibcon#about to write, iclass 35, count 2 2006.257.08:18:26.38#ibcon#wrote, iclass 35, count 2 2006.257.08:18:26.38#ibcon#about to read 3, iclass 35, count 2 2006.257.08:18:26.40#ibcon#read 3, iclass 35, count 2 2006.257.08:18:26.40#ibcon#about to read 4, iclass 35, count 2 2006.257.08:18:26.40#ibcon#read 4, iclass 35, count 2 2006.257.08:18:26.40#ibcon#about to read 5, iclass 35, count 2 2006.257.08:18:26.40#ibcon#read 5, iclass 35, count 2 2006.257.08:18:26.40#ibcon#about to read 6, iclass 35, count 2 2006.257.08:18:26.40#ibcon#read 6, iclass 35, count 2 2006.257.08:18:26.40#ibcon#end of sib2, iclass 35, count 2 2006.257.08:18:26.40#ibcon#*mode == 0, iclass 35, count 2 2006.257.08:18:26.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.08:18:26.40#ibcon#[25=AT07-04\r\n] 2006.257.08:18:26.40#ibcon#*before write, iclass 35, count 2 2006.257.08:18:26.40#ibcon#enter sib2, iclass 35, count 2 2006.257.08:18:26.40#ibcon#flushed, iclass 35, count 2 2006.257.08:18:26.40#ibcon#about to write, iclass 35, count 2 2006.257.08:18:26.40#ibcon#wrote, iclass 35, count 2 2006.257.08:18:26.40#ibcon#about to read 3, iclass 35, count 2 2006.257.08:18:26.47#ibcon#read 3, iclass 35, count 2 2006.257.08:18:26.47#ibcon#about to read 4, iclass 35, count 2 2006.257.08:18:26.47#ibcon#read 4, iclass 35, count 2 2006.257.08:18:26.47#ibcon#about to read 5, iclass 35, count 2 2006.257.08:18:26.47#ibcon#read 5, iclass 35, count 2 2006.257.08:18:26.47#ibcon#about to read 6, iclass 35, count 2 2006.257.08:18:26.47#ibcon#read 6, iclass 35, count 2 2006.257.08:18:26.47#ibcon#end of sib2, iclass 35, count 2 2006.257.08:18:26.47#ibcon#*after write, iclass 35, count 2 2006.257.08:18:26.47#ibcon#*before return 0, iclass 35, count 2 2006.257.08:18:26.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:26.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:26.47#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.08:18:26.47#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:26.47#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:26.59#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:26.59#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:26.59#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:18:26.59#ibcon#first serial, iclass 35, count 0 2006.257.08:18:26.59#ibcon#enter sib2, iclass 35, count 0 2006.257.08:18:26.59#ibcon#flushed, iclass 35, count 0 2006.257.08:18:26.59#ibcon#about to write, iclass 35, count 0 2006.257.08:18:26.59#ibcon#wrote, iclass 35, count 0 2006.257.08:18:26.59#ibcon#about to read 3, iclass 35, count 0 2006.257.08:18:26.61#ibcon#read 3, iclass 35, count 0 2006.257.08:18:26.61#ibcon#about to read 4, iclass 35, count 0 2006.257.08:18:26.61#ibcon#read 4, iclass 35, count 0 2006.257.08:18:26.61#ibcon#about to read 5, iclass 35, count 0 2006.257.08:18:26.61#ibcon#read 5, iclass 35, count 0 2006.257.08:18:26.61#ibcon#about to read 6, iclass 35, count 0 2006.257.08:18:26.61#ibcon#read 6, iclass 35, count 0 2006.257.08:18:26.61#ibcon#end of sib2, iclass 35, count 0 2006.257.08:18:26.61#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:18:26.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:18:26.61#ibcon#[25=USB\r\n] 2006.257.08:18:26.61#ibcon#*before write, iclass 35, count 0 2006.257.08:18:26.61#ibcon#enter sib2, iclass 35, count 0 2006.257.08:18:26.61#ibcon#flushed, iclass 35, count 0 2006.257.08:18:26.61#ibcon#about to write, iclass 35, count 0 2006.257.08:18:26.61#ibcon#wrote, iclass 35, count 0 2006.257.08:18:26.61#ibcon#about to read 3, iclass 35, count 0 2006.257.08:18:26.64#ibcon#read 3, iclass 35, count 0 2006.257.08:18:26.64#ibcon#about to read 4, iclass 35, count 0 2006.257.08:18:26.64#ibcon#read 4, iclass 35, count 0 2006.257.08:18:26.64#ibcon#about to read 5, iclass 35, count 0 2006.257.08:18:26.64#ibcon#read 5, iclass 35, count 0 2006.257.08:18:26.64#ibcon#about to read 6, iclass 35, count 0 2006.257.08:18:26.64#ibcon#read 6, iclass 35, count 0 2006.257.08:18:26.64#ibcon#end of sib2, iclass 35, count 0 2006.257.08:18:26.64#ibcon#*after write, iclass 35, count 0 2006.257.08:18:26.64#ibcon#*before return 0, iclass 35, count 0 2006.257.08:18:26.64#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:26.64#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:26.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:18:26.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:18:26.64$vck44/valo=8,884.99 2006.257.08:18:26.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.08:18:26.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.08:18:26.64#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:26.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:26.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:26.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:26.64#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:18:26.64#ibcon#first serial, iclass 37, count 0 2006.257.08:18:26.64#ibcon#enter sib2, iclass 37, count 0 2006.257.08:18:26.64#ibcon#flushed, iclass 37, count 0 2006.257.08:18:26.64#ibcon#about to write, iclass 37, count 0 2006.257.08:18:26.64#ibcon#wrote, iclass 37, count 0 2006.257.08:18:26.64#ibcon#about to read 3, iclass 37, count 0 2006.257.08:18:26.66#ibcon#read 3, iclass 37, count 0 2006.257.08:18:26.66#ibcon#about to read 4, iclass 37, count 0 2006.257.08:18:26.66#ibcon#read 4, iclass 37, count 0 2006.257.08:18:26.66#ibcon#about to read 5, iclass 37, count 0 2006.257.08:18:26.66#ibcon#read 5, iclass 37, count 0 2006.257.08:18:26.66#ibcon#about to read 6, iclass 37, count 0 2006.257.08:18:26.66#ibcon#read 6, iclass 37, count 0 2006.257.08:18:26.66#ibcon#end of sib2, iclass 37, count 0 2006.257.08:18:26.66#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:18:26.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:18:26.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:18:26.66#ibcon#*before write, iclass 37, count 0 2006.257.08:18:26.66#ibcon#enter sib2, iclass 37, count 0 2006.257.08:18:26.66#ibcon#flushed, iclass 37, count 0 2006.257.08:18:26.66#ibcon#about to write, iclass 37, count 0 2006.257.08:18:26.66#ibcon#wrote, iclass 37, count 0 2006.257.08:18:26.66#ibcon#about to read 3, iclass 37, count 0 2006.257.08:18:26.70#ibcon#read 3, iclass 37, count 0 2006.257.08:18:26.70#ibcon#about to read 4, iclass 37, count 0 2006.257.08:18:26.70#ibcon#read 4, iclass 37, count 0 2006.257.08:18:26.70#ibcon#about to read 5, iclass 37, count 0 2006.257.08:18:26.70#ibcon#read 5, iclass 37, count 0 2006.257.08:18:26.70#ibcon#about to read 6, iclass 37, count 0 2006.257.08:18:26.70#ibcon#read 6, iclass 37, count 0 2006.257.08:18:26.70#ibcon#end of sib2, iclass 37, count 0 2006.257.08:18:26.70#ibcon#*after write, iclass 37, count 0 2006.257.08:18:26.70#ibcon#*before return 0, iclass 37, count 0 2006.257.08:18:26.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:26.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:26.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:18:26.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:18:26.70$vck44/va=8,4 2006.257.08:18:26.70#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.08:18:26.70#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.08:18:26.70#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:26.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:18:26.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:18:26.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:18:26.76#ibcon#enter wrdev, iclass 39, count 2 2006.257.08:18:26.76#ibcon#first serial, iclass 39, count 2 2006.257.08:18:26.76#ibcon#enter sib2, iclass 39, count 2 2006.257.08:18:26.76#ibcon#flushed, iclass 39, count 2 2006.257.08:18:26.76#ibcon#about to write, iclass 39, count 2 2006.257.08:18:26.76#ibcon#wrote, iclass 39, count 2 2006.257.08:18:26.76#ibcon#about to read 3, iclass 39, count 2 2006.257.08:18:26.78#ibcon#read 3, iclass 39, count 2 2006.257.08:18:26.78#ibcon#about to read 4, iclass 39, count 2 2006.257.08:18:26.78#ibcon#read 4, iclass 39, count 2 2006.257.08:18:26.78#ibcon#about to read 5, iclass 39, count 2 2006.257.08:18:26.78#ibcon#read 5, iclass 39, count 2 2006.257.08:18:26.78#ibcon#about to read 6, iclass 39, count 2 2006.257.08:18:26.78#ibcon#read 6, iclass 39, count 2 2006.257.08:18:26.78#ibcon#end of sib2, iclass 39, count 2 2006.257.08:18:26.78#ibcon#*mode == 0, iclass 39, count 2 2006.257.08:18:26.78#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.08:18:26.78#ibcon#[25=AT08-04\r\n] 2006.257.08:18:26.78#ibcon#*before write, iclass 39, count 2 2006.257.08:18:26.78#ibcon#enter sib2, iclass 39, count 2 2006.257.08:18:26.78#ibcon#flushed, iclass 39, count 2 2006.257.08:18:26.78#ibcon#about to write, iclass 39, count 2 2006.257.08:18:26.78#ibcon#wrote, iclass 39, count 2 2006.257.08:18:26.78#ibcon#about to read 3, iclass 39, count 2 2006.257.08:18:26.81#ibcon#read 3, iclass 39, count 2 2006.257.08:18:26.81#ibcon#about to read 4, iclass 39, count 2 2006.257.08:18:26.81#ibcon#read 4, iclass 39, count 2 2006.257.08:18:26.81#ibcon#about to read 5, iclass 39, count 2 2006.257.08:18:26.81#ibcon#read 5, iclass 39, count 2 2006.257.08:18:26.81#ibcon#about to read 6, iclass 39, count 2 2006.257.08:18:26.81#ibcon#read 6, iclass 39, count 2 2006.257.08:18:26.81#ibcon#end of sib2, iclass 39, count 2 2006.257.08:18:26.81#ibcon#*after write, iclass 39, count 2 2006.257.08:18:26.81#ibcon#*before return 0, iclass 39, count 2 2006.257.08:18:26.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:18:26.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:18:26.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.08:18:26.81#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:26.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:18:26.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:18:26.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:18:26.93#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:18:26.93#ibcon#first serial, iclass 39, count 0 2006.257.08:18:26.93#ibcon#enter sib2, iclass 39, count 0 2006.257.08:18:26.93#ibcon#flushed, iclass 39, count 0 2006.257.08:18:26.93#ibcon#about to write, iclass 39, count 0 2006.257.08:18:26.93#ibcon#wrote, iclass 39, count 0 2006.257.08:18:26.93#ibcon#about to read 3, iclass 39, count 0 2006.257.08:18:26.95#ibcon#read 3, iclass 39, count 0 2006.257.08:18:26.95#ibcon#about to read 4, iclass 39, count 0 2006.257.08:18:26.95#ibcon#read 4, iclass 39, count 0 2006.257.08:18:26.95#ibcon#about to read 5, iclass 39, count 0 2006.257.08:18:26.95#ibcon#read 5, iclass 39, count 0 2006.257.08:18:26.95#ibcon#about to read 6, iclass 39, count 0 2006.257.08:18:26.95#ibcon#read 6, iclass 39, count 0 2006.257.08:18:26.95#ibcon#end of sib2, iclass 39, count 0 2006.257.08:18:26.95#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:18:26.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:18:26.95#ibcon#[25=USB\r\n] 2006.257.08:18:26.95#ibcon#*before write, iclass 39, count 0 2006.257.08:18:26.95#ibcon#enter sib2, iclass 39, count 0 2006.257.08:18:26.95#ibcon#flushed, iclass 39, count 0 2006.257.08:18:26.95#ibcon#about to write, iclass 39, count 0 2006.257.08:18:26.95#ibcon#wrote, iclass 39, count 0 2006.257.08:18:26.95#ibcon#about to read 3, iclass 39, count 0 2006.257.08:18:26.98#ibcon#read 3, iclass 39, count 0 2006.257.08:18:26.98#ibcon#about to read 4, iclass 39, count 0 2006.257.08:18:26.98#ibcon#read 4, iclass 39, count 0 2006.257.08:18:26.98#ibcon#about to read 5, iclass 39, count 0 2006.257.08:18:26.98#ibcon#read 5, iclass 39, count 0 2006.257.08:18:26.98#ibcon#about to read 6, iclass 39, count 0 2006.257.08:18:26.98#ibcon#read 6, iclass 39, count 0 2006.257.08:18:26.98#ibcon#end of sib2, iclass 39, count 0 2006.257.08:18:26.98#ibcon#*after write, iclass 39, count 0 2006.257.08:18:26.98#ibcon#*before return 0, iclass 39, count 0 2006.257.08:18:26.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:18:26.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:18:26.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:18:26.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:18:26.98$vck44/vblo=1,629.99 2006.257.08:18:26.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.08:18:26.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.08:18:26.98#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:26.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:18:26.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:18:26.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:18:26.98#ibcon#enter wrdev, iclass 3, count 0 2006.257.08:18:26.98#ibcon#first serial, iclass 3, count 0 2006.257.08:18:26.98#ibcon#enter sib2, iclass 3, count 0 2006.257.08:18:26.98#ibcon#flushed, iclass 3, count 0 2006.257.08:18:26.98#ibcon#about to write, iclass 3, count 0 2006.257.08:18:26.98#ibcon#wrote, iclass 3, count 0 2006.257.08:18:26.98#ibcon#about to read 3, iclass 3, count 0 2006.257.08:18:27.00#ibcon#read 3, iclass 3, count 0 2006.257.08:18:27.00#ibcon#about to read 4, iclass 3, count 0 2006.257.08:18:27.00#ibcon#read 4, iclass 3, count 0 2006.257.08:18:27.00#ibcon#about to read 5, iclass 3, count 0 2006.257.08:18:27.00#ibcon#read 5, iclass 3, count 0 2006.257.08:18:27.00#ibcon#about to read 6, iclass 3, count 0 2006.257.08:18:27.00#ibcon#read 6, iclass 3, count 0 2006.257.08:18:27.00#ibcon#end of sib2, iclass 3, count 0 2006.257.08:18:27.00#ibcon#*mode == 0, iclass 3, count 0 2006.257.08:18:27.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.08:18:27.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:18:27.00#ibcon#*before write, iclass 3, count 0 2006.257.08:18:27.00#ibcon#enter sib2, iclass 3, count 0 2006.257.08:18:27.00#ibcon#flushed, iclass 3, count 0 2006.257.08:18:27.00#ibcon#about to write, iclass 3, count 0 2006.257.08:18:27.00#ibcon#wrote, iclass 3, count 0 2006.257.08:18:27.00#ibcon#about to read 3, iclass 3, count 0 2006.257.08:18:27.04#ibcon#read 3, iclass 3, count 0 2006.257.08:18:27.04#ibcon#about to read 4, iclass 3, count 0 2006.257.08:18:27.04#ibcon#read 4, iclass 3, count 0 2006.257.08:18:27.04#ibcon#about to read 5, iclass 3, count 0 2006.257.08:18:27.04#ibcon#read 5, iclass 3, count 0 2006.257.08:18:27.04#ibcon#about to read 6, iclass 3, count 0 2006.257.08:18:27.04#ibcon#read 6, iclass 3, count 0 2006.257.08:18:27.04#ibcon#end of sib2, iclass 3, count 0 2006.257.08:18:27.04#ibcon#*after write, iclass 3, count 0 2006.257.08:18:27.04#ibcon#*before return 0, iclass 3, count 0 2006.257.08:18:27.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:18:27.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:18:27.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.08:18:27.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.08:18:27.04$vck44/vb=1,4 2006.257.08:18:27.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.08:18:27.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.08:18:27.04#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:27.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:18:27.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:18:27.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:18:27.04#ibcon#enter wrdev, iclass 5, count 2 2006.257.08:18:27.04#ibcon#first serial, iclass 5, count 2 2006.257.08:18:27.04#ibcon#enter sib2, iclass 5, count 2 2006.257.08:18:27.04#ibcon#flushed, iclass 5, count 2 2006.257.08:18:27.04#ibcon#about to write, iclass 5, count 2 2006.257.08:18:27.04#ibcon#wrote, iclass 5, count 2 2006.257.08:18:27.04#ibcon#about to read 3, iclass 5, count 2 2006.257.08:18:27.06#ibcon#read 3, iclass 5, count 2 2006.257.08:18:27.06#ibcon#about to read 4, iclass 5, count 2 2006.257.08:18:27.06#ibcon#read 4, iclass 5, count 2 2006.257.08:18:27.06#ibcon#about to read 5, iclass 5, count 2 2006.257.08:18:27.06#ibcon#read 5, iclass 5, count 2 2006.257.08:18:27.06#ibcon#about to read 6, iclass 5, count 2 2006.257.08:18:27.06#ibcon#read 6, iclass 5, count 2 2006.257.08:18:27.06#ibcon#end of sib2, iclass 5, count 2 2006.257.08:18:27.06#ibcon#*mode == 0, iclass 5, count 2 2006.257.08:18:27.06#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.08:18:27.06#ibcon#[27=AT01-04\r\n] 2006.257.08:18:27.06#ibcon#*before write, iclass 5, count 2 2006.257.08:18:27.06#ibcon#enter sib2, iclass 5, count 2 2006.257.08:18:27.06#ibcon#flushed, iclass 5, count 2 2006.257.08:18:27.06#ibcon#about to write, iclass 5, count 2 2006.257.08:18:27.06#ibcon#wrote, iclass 5, count 2 2006.257.08:18:27.06#ibcon#about to read 3, iclass 5, count 2 2006.257.08:18:27.09#ibcon#read 3, iclass 5, count 2 2006.257.08:18:27.09#ibcon#about to read 4, iclass 5, count 2 2006.257.08:18:27.09#ibcon#read 4, iclass 5, count 2 2006.257.08:18:27.09#ibcon#about to read 5, iclass 5, count 2 2006.257.08:18:27.09#ibcon#read 5, iclass 5, count 2 2006.257.08:18:27.09#ibcon#about to read 6, iclass 5, count 2 2006.257.08:18:27.09#ibcon#read 6, iclass 5, count 2 2006.257.08:18:27.09#ibcon#end of sib2, iclass 5, count 2 2006.257.08:18:27.09#ibcon#*after write, iclass 5, count 2 2006.257.08:18:27.09#ibcon#*before return 0, iclass 5, count 2 2006.257.08:18:27.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:18:27.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:18:27.09#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.08:18:27.09#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:27.09#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:18:27.21#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:18:27.21#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:18:27.21#ibcon#enter wrdev, iclass 5, count 0 2006.257.08:18:27.21#ibcon#first serial, iclass 5, count 0 2006.257.08:18:27.21#ibcon#enter sib2, iclass 5, count 0 2006.257.08:18:27.21#ibcon#flushed, iclass 5, count 0 2006.257.08:18:27.21#ibcon#about to write, iclass 5, count 0 2006.257.08:18:27.21#ibcon#wrote, iclass 5, count 0 2006.257.08:18:27.21#ibcon#about to read 3, iclass 5, count 0 2006.257.08:18:27.23#ibcon#read 3, iclass 5, count 0 2006.257.08:18:27.23#ibcon#about to read 4, iclass 5, count 0 2006.257.08:18:27.23#ibcon#read 4, iclass 5, count 0 2006.257.08:18:27.23#ibcon#about to read 5, iclass 5, count 0 2006.257.08:18:27.23#ibcon#read 5, iclass 5, count 0 2006.257.08:18:27.23#ibcon#about to read 6, iclass 5, count 0 2006.257.08:18:27.23#ibcon#read 6, iclass 5, count 0 2006.257.08:18:27.23#ibcon#end of sib2, iclass 5, count 0 2006.257.08:18:27.23#ibcon#*mode == 0, iclass 5, count 0 2006.257.08:18:27.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.08:18:27.23#ibcon#[27=USB\r\n] 2006.257.08:18:27.23#ibcon#*before write, iclass 5, count 0 2006.257.08:18:27.23#ibcon#enter sib2, iclass 5, count 0 2006.257.08:18:27.23#ibcon#flushed, iclass 5, count 0 2006.257.08:18:27.23#ibcon#about to write, iclass 5, count 0 2006.257.08:18:27.23#ibcon#wrote, iclass 5, count 0 2006.257.08:18:27.23#ibcon#about to read 3, iclass 5, count 0 2006.257.08:18:27.26#ibcon#read 3, iclass 5, count 0 2006.257.08:18:27.26#ibcon#about to read 4, iclass 5, count 0 2006.257.08:18:27.26#ibcon#read 4, iclass 5, count 0 2006.257.08:18:27.26#ibcon#about to read 5, iclass 5, count 0 2006.257.08:18:27.26#ibcon#read 5, iclass 5, count 0 2006.257.08:18:27.26#ibcon#about to read 6, iclass 5, count 0 2006.257.08:18:27.26#ibcon#read 6, iclass 5, count 0 2006.257.08:18:27.26#ibcon#end of sib2, iclass 5, count 0 2006.257.08:18:27.26#ibcon#*after write, iclass 5, count 0 2006.257.08:18:27.26#ibcon#*before return 0, iclass 5, count 0 2006.257.08:18:27.26#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:18:27.26#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:18:27.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.08:18:27.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.08:18:27.26$vck44/vblo=2,634.99 2006.257.08:18:27.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.08:18:27.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.08:18:27.26#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:27.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:27.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:27.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:27.26#ibcon#enter wrdev, iclass 7, count 0 2006.257.08:18:27.26#ibcon#first serial, iclass 7, count 0 2006.257.08:18:27.26#ibcon#enter sib2, iclass 7, count 0 2006.257.08:18:27.26#ibcon#flushed, iclass 7, count 0 2006.257.08:18:27.26#ibcon#about to write, iclass 7, count 0 2006.257.08:18:27.26#ibcon#wrote, iclass 7, count 0 2006.257.08:18:27.26#ibcon#about to read 3, iclass 7, count 0 2006.257.08:18:27.28#ibcon#read 3, iclass 7, count 0 2006.257.08:18:27.28#ibcon#about to read 4, iclass 7, count 0 2006.257.08:18:27.28#ibcon#read 4, iclass 7, count 0 2006.257.08:18:27.28#ibcon#about to read 5, iclass 7, count 0 2006.257.08:18:27.28#ibcon#read 5, iclass 7, count 0 2006.257.08:18:27.28#ibcon#about to read 6, iclass 7, count 0 2006.257.08:18:27.28#ibcon#read 6, iclass 7, count 0 2006.257.08:18:27.28#ibcon#end of sib2, iclass 7, count 0 2006.257.08:18:27.28#ibcon#*mode == 0, iclass 7, count 0 2006.257.08:18:27.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.08:18:27.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:18:27.28#ibcon#*before write, iclass 7, count 0 2006.257.08:18:27.28#ibcon#enter sib2, iclass 7, count 0 2006.257.08:18:27.28#ibcon#flushed, iclass 7, count 0 2006.257.08:18:27.28#ibcon#about to write, iclass 7, count 0 2006.257.08:18:27.28#ibcon#wrote, iclass 7, count 0 2006.257.08:18:27.28#ibcon#about to read 3, iclass 7, count 0 2006.257.08:18:27.32#ibcon#read 3, iclass 7, count 0 2006.257.08:18:27.32#ibcon#about to read 4, iclass 7, count 0 2006.257.08:18:27.32#ibcon#read 4, iclass 7, count 0 2006.257.08:18:27.32#ibcon#about to read 5, iclass 7, count 0 2006.257.08:18:27.32#ibcon#read 5, iclass 7, count 0 2006.257.08:18:27.32#ibcon#about to read 6, iclass 7, count 0 2006.257.08:18:27.32#ibcon#read 6, iclass 7, count 0 2006.257.08:18:27.32#ibcon#end of sib2, iclass 7, count 0 2006.257.08:18:27.32#ibcon#*after write, iclass 7, count 0 2006.257.08:18:27.32#ibcon#*before return 0, iclass 7, count 0 2006.257.08:18:27.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:27.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:18:27.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.08:18:27.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.08:18:27.32$vck44/vb=2,5 2006.257.08:18:27.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.08:18:27.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.08:18:27.32#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:27.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:27.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:27.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:27.38#ibcon#enter wrdev, iclass 11, count 2 2006.257.08:18:27.38#ibcon#first serial, iclass 11, count 2 2006.257.08:18:27.38#ibcon#enter sib2, iclass 11, count 2 2006.257.08:18:27.38#ibcon#flushed, iclass 11, count 2 2006.257.08:18:27.38#ibcon#about to write, iclass 11, count 2 2006.257.08:18:27.38#ibcon#wrote, iclass 11, count 2 2006.257.08:18:27.38#ibcon#about to read 3, iclass 11, count 2 2006.257.08:18:27.40#ibcon#read 3, iclass 11, count 2 2006.257.08:18:27.40#ibcon#about to read 4, iclass 11, count 2 2006.257.08:18:27.40#ibcon#read 4, iclass 11, count 2 2006.257.08:18:27.40#ibcon#about to read 5, iclass 11, count 2 2006.257.08:18:27.40#ibcon#read 5, iclass 11, count 2 2006.257.08:18:27.40#ibcon#about to read 6, iclass 11, count 2 2006.257.08:18:27.40#ibcon#read 6, iclass 11, count 2 2006.257.08:18:27.40#ibcon#end of sib2, iclass 11, count 2 2006.257.08:18:27.40#ibcon#*mode == 0, iclass 11, count 2 2006.257.08:18:27.40#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.08:18:27.40#ibcon#[27=AT02-05\r\n] 2006.257.08:18:27.40#ibcon#*before write, iclass 11, count 2 2006.257.08:18:27.40#ibcon#enter sib2, iclass 11, count 2 2006.257.08:18:27.40#ibcon#flushed, iclass 11, count 2 2006.257.08:18:27.40#ibcon#about to write, iclass 11, count 2 2006.257.08:18:27.40#ibcon#wrote, iclass 11, count 2 2006.257.08:18:27.40#ibcon#about to read 3, iclass 11, count 2 2006.257.08:18:27.43#ibcon#read 3, iclass 11, count 2 2006.257.08:18:27.43#ibcon#about to read 4, iclass 11, count 2 2006.257.08:18:27.43#ibcon#read 4, iclass 11, count 2 2006.257.08:18:27.52#ibcon#about to read 5, iclass 11, count 2 2006.257.08:18:27.52#ibcon#read 5, iclass 11, count 2 2006.257.08:18:27.52#ibcon#about to read 6, iclass 11, count 2 2006.257.08:18:27.52#ibcon#read 6, iclass 11, count 2 2006.257.08:18:27.52#ibcon#end of sib2, iclass 11, count 2 2006.257.08:18:27.52#ibcon#*after write, iclass 11, count 2 2006.257.08:18:27.52#ibcon#*before return 0, iclass 11, count 2 2006.257.08:18:27.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:27.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:18:27.53#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.08:18:27.53#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:27.53#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:27.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:27.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:27.63#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:18:27.63#ibcon#first serial, iclass 11, count 0 2006.257.08:18:27.63#ibcon#enter sib2, iclass 11, count 0 2006.257.08:18:27.63#ibcon#flushed, iclass 11, count 0 2006.257.08:18:27.63#ibcon#about to write, iclass 11, count 0 2006.257.08:18:27.63#ibcon#wrote, iclass 11, count 0 2006.257.08:18:27.63#ibcon#about to read 3, iclass 11, count 0 2006.257.08:18:27.65#ibcon#read 3, iclass 11, count 0 2006.257.08:18:27.65#ibcon#about to read 4, iclass 11, count 0 2006.257.08:18:27.65#ibcon#read 4, iclass 11, count 0 2006.257.08:18:27.65#ibcon#about to read 5, iclass 11, count 0 2006.257.08:18:27.65#ibcon#read 5, iclass 11, count 0 2006.257.08:18:27.65#ibcon#about to read 6, iclass 11, count 0 2006.257.08:18:27.65#ibcon#read 6, iclass 11, count 0 2006.257.08:18:27.65#ibcon#end of sib2, iclass 11, count 0 2006.257.08:18:27.65#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:18:27.65#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:18:27.65#ibcon#[27=USB\r\n] 2006.257.08:18:27.65#ibcon#*before write, iclass 11, count 0 2006.257.08:18:27.65#ibcon#enter sib2, iclass 11, count 0 2006.257.08:18:27.65#ibcon#flushed, iclass 11, count 0 2006.257.08:18:27.65#ibcon#about to write, iclass 11, count 0 2006.257.08:18:27.65#ibcon#wrote, iclass 11, count 0 2006.257.08:18:27.65#ibcon#about to read 3, iclass 11, count 0 2006.257.08:18:27.68#ibcon#read 3, iclass 11, count 0 2006.257.08:18:27.68#ibcon#about to read 4, iclass 11, count 0 2006.257.08:18:27.68#ibcon#read 4, iclass 11, count 0 2006.257.08:18:27.68#ibcon#about to read 5, iclass 11, count 0 2006.257.08:18:27.68#ibcon#read 5, iclass 11, count 0 2006.257.08:18:27.68#ibcon#about to read 6, iclass 11, count 0 2006.257.08:18:27.68#ibcon#read 6, iclass 11, count 0 2006.257.08:18:27.68#ibcon#end of sib2, iclass 11, count 0 2006.257.08:18:27.68#ibcon#*after write, iclass 11, count 0 2006.257.08:18:27.68#ibcon#*before return 0, iclass 11, count 0 2006.257.08:18:27.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:27.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:18:27.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:18:27.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:18:27.68$vck44/vblo=3,649.99 2006.257.08:18:27.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.08:18:27.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.08:18:27.68#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:27.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:27.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:27.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:27.68#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:18:27.68#ibcon#first serial, iclass 13, count 0 2006.257.08:18:27.68#ibcon#enter sib2, iclass 13, count 0 2006.257.08:18:27.68#ibcon#flushed, iclass 13, count 0 2006.257.08:18:27.68#ibcon#about to write, iclass 13, count 0 2006.257.08:18:27.68#ibcon#wrote, iclass 13, count 0 2006.257.08:18:27.68#ibcon#about to read 3, iclass 13, count 0 2006.257.08:18:27.70#ibcon#read 3, iclass 13, count 0 2006.257.08:18:27.70#ibcon#about to read 4, iclass 13, count 0 2006.257.08:18:27.70#ibcon#read 4, iclass 13, count 0 2006.257.08:18:27.70#ibcon#about to read 5, iclass 13, count 0 2006.257.08:18:27.70#ibcon#read 5, iclass 13, count 0 2006.257.08:18:27.70#ibcon#about to read 6, iclass 13, count 0 2006.257.08:18:27.70#ibcon#read 6, iclass 13, count 0 2006.257.08:18:27.70#ibcon#end of sib2, iclass 13, count 0 2006.257.08:18:27.70#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:18:27.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:18:27.70#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:18:27.70#ibcon#*before write, iclass 13, count 0 2006.257.08:18:27.70#ibcon#enter sib2, iclass 13, count 0 2006.257.08:18:27.70#ibcon#flushed, iclass 13, count 0 2006.257.08:18:27.70#ibcon#about to write, iclass 13, count 0 2006.257.08:18:27.70#ibcon#wrote, iclass 13, count 0 2006.257.08:18:27.70#ibcon#about to read 3, iclass 13, count 0 2006.257.08:18:27.74#ibcon#read 3, iclass 13, count 0 2006.257.08:18:27.74#ibcon#about to read 4, iclass 13, count 0 2006.257.08:18:27.74#ibcon#read 4, iclass 13, count 0 2006.257.08:18:27.74#ibcon#about to read 5, iclass 13, count 0 2006.257.08:18:27.74#ibcon#read 5, iclass 13, count 0 2006.257.08:18:27.74#ibcon#about to read 6, iclass 13, count 0 2006.257.08:18:27.74#ibcon#read 6, iclass 13, count 0 2006.257.08:18:27.74#ibcon#end of sib2, iclass 13, count 0 2006.257.08:18:27.74#ibcon#*after write, iclass 13, count 0 2006.257.08:18:27.74#ibcon#*before return 0, iclass 13, count 0 2006.257.08:18:27.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:27.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:18:27.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:18:27.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:18:27.74$vck44/vb=3,4 2006.257.08:18:27.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.08:18:27.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.08:18:27.74#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:27.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:27.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:27.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:27.80#ibcon#enter wrdev, iclass 15, count 2 2006.257.08:18:27.80#ibcon#first serial, iclass 15, count 2 2006.257.08:18:27.80#ibcon#enter sib2, iclass 15, count 2 2006.257.08:18:27.80#ibcon#flushed, iclass 15, count 2 2006.257.08:18:27.80#ibcon#about to write, iclass 15, count 2 2006.257.08:18:27.80#ibcon#wrote, iclass 15, count 2 2006.257.08:18:27.80#ibcon#about to read 3, iclass 15, count 2 2006.257.08:18:27.82#ibcon#read 3, iclass 15, count 2 2006.257.08:18:27.82#ibcon#about to read 4, iclass 15, count 2 2006.257.08:18:27.82#ibcon#read 4, iclass 15, count 2 2006.257.08:18:27.82#ibcon#about to read 5, iclass 15, count 2 2006.257.08:18:27.82#ibcon#read 5, iclass 15, count 2 2006.257.08:18:27.82#ibcon#about to read 6, iclass 15, count 2 2006.257.08:18:27.82#ibcon#read 6, iclass 15, count 2 2006.257.08:18:27.82#ibcon#end of sib2, iclass 15, count 2 2006.257.08:18:27.82#ibcon#*mode == 0, iclass 15, count 2 2006.257.08:18:27.82#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.08:18:27.82#ibcon#[27=AT03-04\r\n] 2006.257.08:18:27.82#ibcon#*before write, iclass 15, count 2 2006.257.08:18:27.82#ibcon#enter sib2, iclass 15, count 2 2006.257.08:18:27.82#ibcon#flushed, iclass 15, count 2 2006.257.08:18:27.82#ibcon#about to write, iclass 15, count 2 2006.257.08:18:27.82#ibcon#wrote, iclass 15, count 2 2006.257.08:18:27.82#ibcon#about to read 3, iclass 15, count 2 2006.257.08:18:27.85#ibcon#read 3, iclass 15, count 2 2006.257.08:18:27.85#ibcon#about to read 4, iclass 15, count 2 2006.257.08:18:27.85#ibcon#read 4, iclass 15, count 2 2006.257.08:18:27.85#ibcon#about to read 5, iclass 15, count 2 2006.257.08:18:27.85#ibcon#read 5, iclass 15, count 2 2006.257.08:18:27.85#ibcon#about to read 6, iclass 15, count 2 2006.257.08:18:27.85#ibcon#read 6, iclass 15, count 2 2006.257.08:18:27.85#ibcon#end of sib2, iclass 15, count 2 2006.257.08:18:27.85#ibcon#*after write, iclass 15, count 2 2006.257.08:18:27.85#ibcon#*before return 0, iclass 15, count 2 2006.257.08:18:27.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:27.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:18:27.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.08:18:27.85#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:27.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:27.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:27.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:27.97#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:18:27.97#ibcon#first serial, iclass 15, count 0 2006.257.08:18:27.97#ibcon#enter sib2, iclass 15, count 0 2006.257.08:18:27.97#ibcon#flushed, iclass 15, count 0 2006.257.08:18:27.97#ibcon#about to write, iclass 15, count 0 2006.257.08:18:27.97#ibcon#wrote, iclass 15, count 0 2006.257.08:18:27.97#ibcon#about to read 3, iclass 15, count 0 2006.257.08:18:27.99#ibcon#read 3, iclass 15, count 0 2006.257.08:18:27.99#ibcon#about to read 4, iclass 15, count 0 2006.257.08:18:27.99#ibcon#read 4, iclass 15, count 0 2006.257.08:18:27.99#ibcon#about to read 5, iclass 15, count 0 2006.257.08:18:27.99#ibcon#read 5, iclass 15, count 0 2006.257.08:18:27.99#ibcon#about to read 6, iclass 15, count 0 2006.257.08:18:27.99#ibcon#read 6, iclass 15, count 0 2006.257.08:18:27.99#ibcon#end of sib2, iclass 15, count 0 2006.257.08:18:27.99#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:18:27.99#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:18:27.99#ibcon#[27=USB\r\n] 2006.257.08:18:27.99#ibcon#*before write, iclass 15, count 0 2006.257.08:18:27.99#ibcon#enter sib2, iclass 15, count 0 2006.257.08:18:27.99#ibcon#flushed, iclass 15, count 0 2006.257.08:18:27.99#ibcon#about to write, iclass 15, count 0 2006.257.08:18:27.99#ibcon#wrote, iclass 15, count 0 2006.257.08:18:27.99#ibcon#about to read 3, iclass 15, count 0 2006.257.08:18:28.02#ibcon#read 3, iclass 15, count 0 2006.257.08:18:28.02#ibcon#about to read 4, iclass 15, count 0 2006.257.08:18:28.02#ibcon#read 4, iclass 15, count 0 2006.257.08:18:28.02#ibcon#about to read 5, iclass 15, count 0 2006.257.08:18:28.02#ibcon#read 5, iclass 15, count 0 2006.257.08:18:28.02#ibcon#about to read 6, iclass 15, count 0 2006.257.08:18:28.02#ibcon#read 6, iclass 15, count 0 2006.257.08:18:28.02#ibcon#end of sib2, iclass 15, count 0 2006.257.08:18:28.02#ibcon#*after write, iclass 15, count 0 2006.257.08:18:28.02#ibcon#*before return 0, iclass 15, count 0 2006.257.08:18:28.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:28.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:18:28.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:18:28.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:18:28.02$vck44/vblo=4,679.99 2006.257.08:18:28.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.08:18:28.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.08:18:28.02#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:28.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:28.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:28.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:28.02#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:18:28.02#ibcon#first serial, iclass 17, count 0 2006.257.08:18:28.02#ibcon#enter sib2, iclass 17, count 0 2006.257.08:18:28.02#ibcon#flushed, iclass 17, count 0 2006.257.08:18:28.02#ibcon#about to write, iclass 17, count 0 2006.257.08:18:28.02#ibcon#wrote, iclass 17, count 0 2006.257.08:18:28.02#ibcon#about to read 3, iclass 17, count 0 2006.257.08:18:28.04#ibcon#read 3, iclass 17, count 0 2006.257.08:18:28.04#ibcon#about to read 4, iclass 17, count 0 2006.257.08:18:28.04#ibcon#read 4, iclass 17, count 0 2006.257.08:18:28.04#ibcon#about to read 5, iclass 17, count 0 2006.257.08:18:28.04#ibcon#read 5, iclass 17, count 0 2006.257.08:18:28.04#ibcon#about to read 6, iclass 17, count 0 2006.257.08:18:28.04#ibcon#read 6, iclass 17, count 0 2006.257.08:18:28.04#ibcon#end of sib2, iclass 17, count 0 2006.257.08:18:28.04#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:18:28.04#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:18:28.04#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:18:28.04#ibcon#*before write, iclass 17, count 0 2006.257.08:18:28.04#ibcon#enter sib2, iclass 17, count 0 2006.257.08:18:28.04#ibcon#flushed, iclass 17, count 0 2006.257.08:18:28.04#ibcon#about to write, iclass 17, count 0 2006.257.08:18:28.04#ibcon#wrote, iclass 17, count 0 2006.257.08:18:28.04#ibcon#about to read 3, iclass 17, count 0 2006.257.08:18:28.08#ibcon#read 3, iclass 17, count 0 2006.257.08:18:28.08#ibcon#about to read 4, iclass 17, count 0 2006.257.08:18:28.08#ibcon#read 4, iclass 17, count 0 2006.257.08:18:28.08#ibcon#about to read 5, iclass 17, count 0 2006.257.08:18:28.08#ibcon#read 5, iclass 17, count 0 2006.257.08:18:28.08#ibcon#about to read 6, iclass 17, count 0 2006.257.08:18:28.08#ibcon#read 6, iclass 17, count 0 2006.257.08:18:28.08#ibcon#end of sib2, iclass 17, count 0 2006.257.08:18:28.08#ibcon#*after write, iclass 17, count 0 2006.257.08:18:28.08#ibcon#*before return 0, iclass 17, count 0 2006.257.08:18:28.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:28.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:18:28.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:18:28.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:18:28.08$vck44/vb=4,5 2006.257.08:18:28.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.08:18:28.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.08:18:28.08#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:28.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:28.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:28.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:28.14#ibcon#enter wrdev, iclass 19, count 2 2006.257.08:18:28.14#ibcon#first serial, iclass 19, count 2 2006.257.08:18:28.14#ibcon#enter sib2, iclass 19, count 2 2006.257.08:18:28.14#ibcon#flushed, iclass 19, count 2 2006.257.08:18:28.14#ibcon#about to write, iclass 19, count 2 2006.257.08:18:28.14#ibcon#wrote, iclass 19, count 2 2006.257.08:18:28.14#ibcon#about to read 3, iclass 19, count 2 2006.257.08:18:28.16#ibcon#read 3, iclass 19, count 2 2006.257.08:18:28.16#ibcon#about to read 4, iclass 19, count 2 2006.257.08:18:28.16#ibcon#read 4, iclass 19, count 2 2006.257.08:18:28.16#ibcon#about to read 5, iclass 19, count 2 2006.257.08:18:28.16#ibcon#read 5, iclass 19, count 2 2006.257.08:18:28.16#ibcon#about to read 6, iclass 19, count 2 2006.257.08:18:28.16#ibcon#read 6, iclass 19, count 2 2006.257.08:18:28.16#ibcon#end of sib2, iclass 19, count 2 2006.257.08:18:28.16#ibcon#*mode == 0, iclass 19, count 2 2006.257.08:18:28.16#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.08:18:28.16#ibcon#[27=AT04-05\r\n] 2006.257.08:18:28.16#ibcon#*before write, iclass 19, count 2 2006.257.08:18:28.16#ibcon#enter sib2, iclass 19, count 2 2006.257.08:18:28.16#ibcon#flushed, iclass 19, count 2 2006.257.08:18:28.16#ibcon#about to write, iclass 19, count 2 2006.257.08:18:28.16#ibcon#wrote, iclass 19, count 2 2006.257.08:18:28.16#ibcon#about to read 3, iclass 19, count 2 2006.257.08:18:28.19#ibcon#read 3, iclass 19, count 2 2006.257.08:18:28.19#ibcon#about to read 4, iclass 19, count 2 2006.257.08:18:28.19#ibcon#read 4, iclass 19, count 2 2006.257.08:18:28.19#ibcon#about to read 5, iclass 19, count 2 2006.257.08:18:28.19#ibcon#read 5, iclass 19, count 2 2006.257.08:18:28.19#ibcon#about to read 6, iclass 19, count 2 2006.257.08:18:28.19#ibcon#read 6, iclass 19, count 2 2006.257.08:18:28.19#ibcon#end of sib2, iclass 19, count 2 2006.257.08:18:28.19#ibcon#*after write, iclass 19, count 2 2006.257.08:18:28.19#ibcon#*before return 0, iclass 19, count 2 2006.257.08:18:28.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:28.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:18:28.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.08:18:28.19#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:28.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:28.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:28.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:28.31#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:18:28.31#ibcon#first serial, iclass 19, count 0 2006.257.08:18:28.31#ibcon#enter sib2, iclass 19, count 0 2006.257.08:18:28.31#ibcon#flushed, iclass 19, count 0 2006.257.08:18:28.31#ibcon#about to write, iclass 19, count 0 2006.257.08:18:28.31#ibcon#wrote, iclass 19, count 0 2006.257.08:18:28.31#ibcon#about to read 3, iclass 19, count 0 2006.257.08:18:28.33#ibcon#read 3, iclass 19, count 0 2006.257.08:18:28.33#ibcon#about to read 4, iclass 19, count 0 2006.257.08:18:28.33#ibcon#read 4, iclass 19, count 0 2006.257.08:18:28.33#ibcon#about to read 5, iclass 19, count 0 2006.257.08:18:28.33#ibcon#read 5, iclass 19, count 0 2006.257.08:18:28.33#ibcon#about to read 6, iclass 19, count 0 2006.257.08:18:28.33#ibcon#read 6, iclass 19, count 0 2006.257.08:18:28.33#ibcon#end of sib2, iclass 19, count 0 2006.257.08:18:28.33#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:18:28.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:18:28.33#ibcon#[27=USB\r\n] 2006.257.08:18:28.33#ibcon#*before write, iclass 19, count 0 2006.257.08:18:28.33#ibcon#enter sib2, iclass 19, count 0 2006.257.08:18:28.33#ibcon#flushed, iclass 19, count 0 2006.257.08:18:28.33#ibcon#about to write, iclass 19, count 0 2006.257.08:18:28.33#ibcon#wrote, iclass 19, count 0 2006.257.08:18:28.33#ibcon#about to read 3, iclass 19, count 0 2006.257.08:18:28.36#ibcon#read 3, iclass 19, count 0 2006.257.08:18:28.36#ibcon#about to read 4, iclass 19, count 0 2006.257.08:18:28.36#ibcon#read 4, iclass 19, count 0 2006.257.08:18:28.36#ibcon#about to read 5, iclass 19, count 0 2006.257.08:18:28.36#ibcon#read 5, iclass 19, count 0 2006.257.08:18:28.36#ibcon#about to read 6, iclass 19, count 0 2006.257.08:18:28.36#ibcon#read 6, iclass 19, count 0 2006.257.08:18:28.36#ibcon#end of sib2, iclass 19, count 0 2006.257.08:18:28.36#ibcon#*after write, iclass 19, count 0 2006.257.08:18:28.36#ibcon#*before return 0, iclass 19, count 0 2006.257.08:18:28.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:28.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:18:28.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:18:28.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:18:28.36$vck44/vblo=5,709.99 2006.257.08:18:28.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.08:18:28.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.08:18:28.36#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:28.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:28.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:28.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:28.36#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:18:28.36#ibcon#first serial, iclass 21, count 0 2006.257.08:18:28.36#ibcon#enter sib2, iclass 21, count 0 2006.257.08:18:28.36#ibcon#flushed, iclass 21, count 0 2006.257.08:18:28.36#ibcon#about to write, iclass 21, count 0 2006.257.08:18:28.36#ibcon#wrote, iclass 21, count 0 2006.257.08:18:28.36#ibcon#about to read 3, iclass 21, count 0 2006.257.08:18:28.38#ibcon#read 3, iclass 21, count 0 2006.257.08:18:28.38#ibcon#about to read 4, iclass 21, count 0 2006.257.08:18:28.38#ibcon#read 4, iclass 21, count 0 2006.257.08:18:28.38#ibcon#about to read 5, iclass 21, count 0 2006.257.08:18:28.38#ibcon#read 5, iclass 21, count 0 2006.257.08:18:28.38#ibcon#about to read 6, iclass 21, count 0 2006.257.08:18:28.38#ibcon#read 6, iclass 21, count 0 2006.257.08:18:28.38#ibcon#end of sib2, iclass 21, count 0 2006.257.08:18:28.38#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:18:28.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:18:28.38#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:18:28.38#ibcon#*before write, iclass 21, count 0 2006.257.08:18:28.38#ibcon#enter sib2, iclass 21, count 0 2006.257.08:18:28.38#ibcon#flushed, iclass 21, count 0 2006.257.08:18:28.38#ibcon#about to write, iclass 21, count 0 2006.257.08:18:28.38#ibcon#wrote, iclass 21, count 0 2006.257.08:18:28.38#ibcon#about to read 3, iclass 21, count 0 2006.257.08:18:28.42#ibcon#read 3, iclass 21, count 0 2006.257.08:18:28.42#ibcon#about to read 4, iclass 21, count 0 2006.257.08:18:28.42#ibcon#read 4, iclass 21, count 0 2006.257.08:18:28.42#ibcon#about to read 5, iclass 21, count 0 2006.257.08:18:28.42#ibcon#read 5, iclass 21, count 0 2006.257.08:18:28.42#ibcon#about to read 6, iclass 21, count 0 2006.257.08:18:28.42#ibcon#read 6, iclass 21, count 0 2006.257.08:18:28.42#ibcon#end of sib2, iclass 21, count 0 2006.257.08:18:28.42#ibcon#*after write, iclass 21, count 0 2006.257.08:18:28.42#ibcon#*before return 0, iclass 21, count 0 2006.257.08:18:28.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:28.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:18:28.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:18:28.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:18:28.42$vck44/vb=5,4 2006.257.08:18:28.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.08:18:28.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.08:18:28.42#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:28.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:28.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:28.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:28.48#ibcon#enter wrdev, iclass 23, count 2 2006.257.08:18:28.48#ibcon#first serial, iclass 23, count 2 2006.257.08:18:28.48#ibcon#enter sib2, iclass 23, count 2 2006.257.08:18:28.48#ibcon#flushed, iclass 23, count 2 2006.257.08:18:28.48#ibcon#about to write, iclass 23, count 2 2006.257.08:18:28.48#ibcon#wrote, iclass 23, count 2 2006.257.08:18:28.48#ibcon#about to read 3, iclass 23, count 2 2006.257.08:18:28.50#ibcon#read 3, iclass 23, count 2 2006.257.08:18:28.50#ibcon#about to read 4, iclass 23, count 2 2006.257.08:18:28.50#ibcon#read 4, iclass 23, count 2 2006.257.08:18:28.50#ibcon#about to read 5, iclass 23, count 2 2006.257.08:18:28.50#ibcon#read 5, iclass 23, count 2 2006.257.08:18:28.50#ibcon#about to read 6, iclass 23, count 2 2006.257.08:18:28.50#ibcon#read 6, iclass 23, count 2 2006.257.08:18:28.50#ibcon#end of sib2, iclass 23, count 2 2006.257.08:18:28.50#ibcon#*mode == 0, iclass 23, count 2 2006.257.08:18:28.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.08:18:28.50#ibcon#[27=AT05-04\r\n] 2006.257.08:18:28.50#ibcon#*before write, iclass 23, count 2 2006.257.08:18:28.50#ibcon#enter sib2, iclass 23, count 2 2006.257.08:18:28.50#ibcon#flushed, iclass 23, count 2 2006.257.08:18:28.50#ibcon#about to write, iclass 23, count 2 2006.257.08:18:28.50#ibcon#wrote, iclass 23, count 2 2006.257.08:18:28.50#ibcon#about to read 3, iclass 23, count 2 2006.257.08:18:28.53#ibcon#read 3, iclass 23, count 2 2006.257.08:18:28.53#ibcon#about to read 4, iclass 23, count 2 2006.257.08:18:28.53#ibcon#read 4, iclass 23, count 2 2006.257.08:18:28.53#ibcon#about to read 5, iclass 23, count 2 2006.257.08:18:28.53#ibcon#read 5, iclass 23, count 2 2006.257.08:18:28.53#ibcon#about to read 6, iclass 23, count 2 2006.257.08:18:28.53#ibcon#read 6, iclass 23, count 2 2006.257.08:18:28.53#ibcon#end of sib2, iclass 23, count 2 2006.257.08:18:28.53#ibcon#*after write, iclass 23, count 2 2006.257.08:18:28.53#ibcon#*before return 0, iclass 23, count 2 2006.257.08:18:28.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:28.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:18:28.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.08:18:28.53#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:28.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:28.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:28.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:28.65#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:18:28.65#ibcon#first serial, iclass 23, count 0 2006.257.08:18:28.65#ibcon#enter sib2, iclass 23, count 0 2006.257.08:18:28.65#ibcon#flushed, iclass 23, count 0 2006.257.08:18:28.65#ibcon#about to write, iclass 23, count 0 2006.257.08:18:28.65#ibcon#wrote, iclass 23, count 0 2006.257.08:18:28.65#ibcon#about to read 3, iclass 23, count 0 2006.257.08:18:28.67#ibcon#read 3, iclass 23, count 0 2006.257.08:18:28.67#ibcon#about to read 4, iclass 23, count 0 2006.257.08:18:28.67#ibcon#read 4, iclass 23, count 0 2006.257.08:18:28.67#ibcon#about to read 5, iclass 23, count 0 2006.257.08:18:28.67#ibcon#read 5, iclass 23, count 0 2006.257.08:18:28.67#ibcon#about to read 6, iclass 23, count 0 2006.257.08:18:28.67#ibcon#read 6, iclass 23, count 0 2006.257.08:18:28.67#ibcon#end of sib2, iclass 23, count 0 2006.257.08:18:28.67#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:18:28.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:18:28.67#ibcon#[27=USB\r\n] 2006.257.08:18:28.67#ibcon#*before write, iclass 23, count 0 2006.257.08:18:28.67#ibcon#enter sib2, iclass 23, count 0 2006.257.08:18:28.67#ibcon#flushed, iclass 23, count 0 2006.257.08:18:28.67#ibcon#about to write, iclass 23, count 0 2006.257.08:18:28.67#ibcon#wrote, iclass 23, count 0 2006.257.08:18:28.67#ibcon#about to read 3, iclass 23, count 0 2006.257.08:18:28.70#ibcon#read 3, iclass 23, count 0 2006.257.08:18:28.70#ibcon#about to read 4, iclass 23, count 0 2006.257.08:18:28.70#ibcon#read 4, iclass 23, count 0 2006.257.08:18:28.70#ibcon#about to read 5, iclass 23, count 0 2006.257.08:18:28.70#ibcon#read 5, iclass 23, count 0 2006.257.08:18:28.70#ibcon#about to read 6, iclass 23, count 0 2006.257.08:18:28.70#ibcon#read 6, iclass 23, count 0 2006.257.08:18:28.70#ibcon#end of sib2, iclass 23, count 0 2006.257.08:18:28.70#ibcon#*after write, iclass 23, count 0 2006.257.08:18:28.70#ibcon#*before return 0, iclass 23, count 0 2006.257.08:18:28.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:28.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:18:28.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:18:28.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:18:28.70$vck44/vblo=6,719.99 2006.257.08:18:28.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.08:18:28.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.08:18:28.70#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:28.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:28.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:28.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:28.70#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:18:28.70#ibcon#first serial, iclass 25, count 0 2006.257.08:18:28.70#ibcon#enter sib2, iclass 25, count 0 2006.257.08:18:28.70#ibcon#flushed, iclass 25, count 0 2006.257.08:18:28.70#ibcon#about to write, iclass 25, count 0 2006.257.08:18:28.70#ibcon#wrote, iclass 25, count 0 2006.257.08:18:28.70#ibcon#about to read 3, iclass 25, count 0 2006.257.08:18:28.72#ibcon#read 3, iclass 25, count 0 2006.257.08:18:28.72#ibcon#about to read 4, iclass 25, count 0 2006.257.08:18:28.72#ibcon#read 4, iclass 25, count 0 2006.257.08:18:28.72#ibcon#about to read 5, iclass 25, count 0 2006.257.08:18:28.72#ibcon#read 5, iclass 25, count 0 2006.257.08:18:28.72#ibcon#about to read 6, iclass 25, count 0 2006.257.08:18:28.72#ibcon#read 6, iclass 25, count 0 2006.257.08:18:28.72#ibcon#end of sib2, iclass 25, count 0 2006.257.08:18:28.72#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:18:28.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:18:28.72#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:18:28.72#ibcon#*before write, iclass 25, count 0 2006.257.08:18:28.72#ibcon#enter sib2, iclass 25, count 0 2006.257.08:18:28.72#ibcon#flushed, iclass 25, count 0 2006.257.08:18:28.72#ibcon#about to write, iclass 25, count 0 2006.257.08:18:28.72#ibcon#wrote, iclass 25, count 0 2006.257.08:18:28.72#ibcon#about to read 3, iclass 25, count 0 2006.257.08:18:28.76#ibcon#read 3, iclass 25, count 0 2006.257.08:18:28.76#ibcon#about to read 4, iclass 25, count 0 2006.257.08:18:28.76#ibcon#read 4, iclass 25, count 0 2006.257.08:18:28.76#ibcon#about to read 5, iclass 25, count 0 2006.257.08:18:28.76#ibcon#read 5, iclass 25, count 0 2006.257.08:18:28.76#ibcon#about to read 6, iclass 25, count 0 2006.257.08:18:28.76#ibcon#read 6, iclass 25, count 0 2006.257.08:18:28.76#ibcon#end of sib2, iclass 25, count 0 2006.257.08:18:28.76#ibcon#*after write, iclass 25, count 0 2006.257.08:18:28.76#ibcon#*before return 0, iclass 25, count 0 2006.257.08:18:28.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:28.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:18:28.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:18:28.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:18:28.76$vck44/vb=6,4 2006.257.08:18:28.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.08:18:28.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.08:18:28.76#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:28.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:28.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:28.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:28.82#ibcon#enter wrdev, iclass 27, count 2 2006.257.08:18:28.82#ibcon#first serial, iclass 27, count 2 2006.257.08:18:28.82#ibcon#enter sib2, iclass 27, count 2 2006.257.08:18:28.82#ibcon#flushed, iclass 27, count 2 2006.257.08:18:28.82#ibcon#about to write, iclass 27, count 2 2006.257.08:18:28.82#ibcon#wrote, iclass 27, count 2 2006.257.08:18:28.82#ibcon#about to read 3, iclass 27, count 2 2006.257.08:18:28.84#ibcon#read 3, iclass 27, count 2 2006.257.08:18:28.84#ibcon#about to read 4, iclass 27, count 2 2006.257.08:18:28.84#ibcon#read 4, iclass 27, count 2 2006.257.08:18:28.84#ibcon#about to read 5, iclass 27, count 2 2006.257.08:18:28.84#ibcon#read 5, iclass 27, count 2 2006.257.08:18:28.84#ibcon#about to read 6, iclass 27, count 2 2006.257.08:18:28.84#ibcon#read 6, iclass 27, count 2 2006.257.08:18:28.84#ibcon#end of sib2, iclass 27, count 2 2006.257.08:18:28.84#ibcon#*mode == 0, iclass 27, count 2 2006.257.08:18:28.84#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.08:18:28.84#ibcon#[27=AT06-04\r\n] 2006.257.08:18:28.84#ibcon#*before write, iclass 27, count 2 2006.257.08:18:28.84#ibcon#enter sib2, iclass 27, count 2 2006.257.08:18:28.84#ibcon#flushed, iclass 27, count 2 2006.257.08:18:28.84#ibcon#about to write, iclass 27, count 2 2006.257.08:18:28.84#ibcon#wrote, iclass 27, count 2 2006.257.08:18:28.84#ibcon#about to read 3, iclass 27, count 2 2006.257.08:18:28.87#ibcon#read 3, iclass 27, count 2 2006.257.08:18:28.87#ibcon#about to read 4, iclass 27, count 2 2006.257.08:18:28.87#ibcon#read 4, iclass 27, count 2 2006.257.08:18:28.87#ibcon#about to read 5, iclass 27, count 2 2006.257.08:18:28.87#ibcon#read 5, iclass 27, count 2 2006.257.08:18:28.87#ibcon#about to read 6, iclass 27, count 2 2006.257.08:18:28.87#ibcon#read 6, iclass 27, count 2 2006.257.08:18:28.87#ibcon#end of sib2, iclass 27, count 2 2006.257.08:18:28.87#ibcon#*after write, iclass 27, count 2 2006.257.08:18:28.87#ibcon#*before return 0, iclass 27, count 2 2006.257.08:18:28.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:28.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:18:28.87#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.08:18:28.87#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:28.87#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:28.99#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:28.99#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:28.99#ibcon#enter wrdev, iclass 27, count 0 2006.257.08:18:28.99#ibcon#first serial, iclass 27, count 0 2006.257.08:18:28.99#ibcon#enter sib2, iclass 27, count 0 2006.257.08:18:28.99#ibcon#flushed, iclass 27, count 0 2006.257.08:18:28.99#ibcon#about to write, iclass 27, count 0 2006.257.08:18:28.99#ibcon#wrote, iclass 27, count 0 2006.257.08:18:28.99#ibcon#about to read 3, iclass 27, count 0 2006.257.08:18:29.01#ibcon#read 3, iclass 27, count 0 2006.257.08:18:29.01#ibcon#about to read 4, iclass 27, count 0 2006.257.08:18:29.01#ibcon#read 4, iclass 27, count 0 2006.257.08:18:29.01#ibcon#about to read 5, iclass 27, count 0 2006.257.08:18:29.01#ibcon#read 5, iclass 27, count 0 2006.257.08:18:29.01#ibcon#about to read 6, iclass 27, count 0 2006.257.08:18:29.01#ibcon#read 6, iclass 27, count 0 2006.257.08:18:29.01#ibcon#end of sib2, iclass 27, count 0 2006.257.08:18:29.01#ibcon#*mode == 0, iclass 27, count 0 2006.257.08:18:29.01#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.08:18:29.01#ibcon#[27=USB\r\n] 2006.257.08:18:29.01#ibcon#*before write, iclass 27, count 0 2006.257.08:18:29.01#ibcon#enter sib2, iclass 27, count 0 2006.257.08:18:29.01#ibcon#flushed, iclass 27, count 0 2006.257.08:18:29.01#ibcon#about to write, iclass 27, count 0 2006.257.08:18:29.01#ibcon#wrote, iclass 27, count 0 2006.257.08:18:29.01#ibcon#about to read 3, iclass 27, count 0 2006.257.08:18:29.04#ibcon#read 3, iclass 27, count 0 2006.257.08:18:29.04#ibcon#about to read 4, iclass 27, count 0 2006.257.08:18:29.04#ibcon#read 4, iclass 27, count 0 2006.257.08:18:29.04#ibcon#about to read 5, iclass 27, count 0 2006.257.08:18:29.04#ibcon#read 5, iclass 27, count 0 2006.257.08:18:29.04#ibcon#about to read 6, iclass 27, count 0 2006.257.08:18:29.04#ibcon#read 6, iclass 27, count 0 2006.257.08:18:29.04#ibcon#end of sib2, iclass 27, count 0 2006.257.08:18:29.04#ibcon#*after write, iclass 27, count 0 2006.257.08:18:29.04#ibcon#*before return 0, iclass 27, count 0 2006.257.08:18:29.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:29.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:18:29.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.08:18:29.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.08:18:29.04$vck44/vblo=7,734.99 2006.257.08:18:29.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.08:18:29.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.08:18:29.04#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:29.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:29.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:29.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:29.04#ibcon#enter wrdev, iclass 29, count 0 2006.257.08:18:29.04#ibcon#first serial, iclass 29, count 0 2006.257.08:18:29.04#ibcon#enter sib2, iclass 29, count 0 2006.257.08:18:29.04#ibcon#flushed, iclass 29, count 0 2006.257.08:18:29.04#ibcon#about to write, iclass 29, count 0 2006.257.08:18:29.04#ibcon#wrote, iclass 29, count 0 2006.257.08:18:29.04#ibcon#about to read 3, iclass 29, count 0 2006.257.08:18:29.06#ibcon#read 3, iclass 29, count 0 2006.257.08:18:29.06#ibcon#about to read 4, iclass 29, count 0 2006.257.08:18:29.06#ibcon#read 4, iclass 29, count 0 2006.257.08:18:29.06#ibcon#about to read 5, iclass 29, count 0 2006.257.08:18:29.06#ibcon#read 5, iclass 29, count 0 2006.257.08:18:29.06#ibcon#about to read 6, iclass 29, count 0 2006.257.08:18:29.06#ibcon#read 6, iclass 29, count 0 2006.257.08:18:29.06#ibcon#end of sib2, iclass 29, count 0 2006.257.08:18:29.06#ibcon#*mode == 0, iclass 29, count 0 2006.257.08:18:29.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.08:18:29.06#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:18:29.06#ibcon#*before write, iclass 29, count 0 2006.257.08:18:29.06#ibcon#enter sib2, iclass 29, count 0 2006.257.08:18:29.06#ibcon#flushed, iclass 29, count 0 2006.257.08:18:29.06#ibcon#about to write, iclass 29, count 0 2006.257.08:18:29.06#ibcon#wrote, iclass 29, count 0 2006.257.08:18:29.06#ibcon#about to read 3, iclass 29, count 0 2006.257.08:18:29.10#ibcon#read 3, iclass 29, count 0 2006.257.08:18:29.10#ibcon#about to read 4, iclass 29, count 0 2006.257.08:18:29.10#ibcon#read 4, iclass 29, count 0 2006.257.08:18:29.10#ibcon#about to read 5, iclass 29, count 0 2006.257.08:18:29.10#ibcon#read 5, iclass 29, count 0 2006.257.08:18:29.10#ibcon#about to read 6, iclass 29, count 0 2006.257.08:18:29.10#ibcon#read 6, iclass 29, count 0 2006.257.08:18:29.10#ibcon#end of sib2, iclass 29, count 0 2006.257.08:18:29.10#ibcon#*after write, iclass 29, count 0 2006.257.08:18:29.10#ibcon#*before return 0, iclass 29, count 0 2006.257.08:18:29.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:29.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:18:29.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.08:18:29.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.08:18:29.10$vck44/vb=7,4 2006.257.08:18:29.10#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.08:18:29.10#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.08:18:29.10#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:29.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:29.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:29.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:29.16#ibcon#enter wrdev, iclass 31, count 2 2006.257.08:18:29.16#ibcon#first serial, iclass 31, count 2 2006.257.08:18:29.16#ibcon#enter sib2, iclass 31, count 2 2006.257.08:18:29.16#ibcon#flushed, iclass 31, count 2 2006.257.08:18:29.16#ibcon#about to write, iclass 31, count 2 2006.257.08:18:29.16#ibcon#wrote, iclass 31, count 2 2006.257.08:18:29.16#ibcon#about to read 3, iclass 31, count 2 2006.257.08:18:29.18#ibcon#read 3, iclass 31, count 2 2006.257.08:18:29.18#ibcon#about to read 4, iclass 31, count 2 2006.257.08:18:29.18#ibcon#read 4, iclass 31, count 2 2006.257.08:18:29.18#ibcon#about to read 5, iclass 31, count 2 2006.257.08:18:29.18#ibcon#read 5, iclass 31, count 2 2006.257.08:18:29.18#ibcon#about to read 6, iclass 31, count 2 2006.257.08:18:29.18#ibcon#read 6, iclass 31, count 2 2006.257.08:18:29.18#ibcon#end of sib2, iclass 31, count 2 2006.257.08:18:29.18#ibcon#*mode == 0, iclass 31, count 2 2006.257.08:18:29.18#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.08:18:29.18#ibcon#[27=AT07-04\r\n] 2006.257.08:18:29.18#ibcon#*before write, iclass 31, count 2 2006.257.08:18:29.18#ibcon#enter sib2, iclass 31, count 2 2006.257.08:18:29.18#ibcon#flushed, iclass 31, count 2 2006.257.08:18:29.18#ibcon#about to write, iclass 31, count 2 2006.257.08:18:29.18#ibcon#wrote, iclass 31, count 2 2006.257.08:18:29.18#ibcon#about to read 3, iclass 31, count 2 2006.257.08:18:29.21#ibcon#read 3, iclass 31, count 2 2006.257.08:18:29.21#ibcon#about to read 4, iclass 31, count 2 2006.257.08:18:29.21#ibcon#read 4, iclass 31, count 2 2006.257.08:18:29.21#ibcon#about to read 5, iclass 31, count 2 2006.257.08:18:29.21#ibcon#read 5, iclass 31, count 2 2006.257.08:18:29.21#ibcon#about to read 6, iclass 31, count 2 2006.257.08:18:29.21#ibcon#read 6, iclass 31, count 2 2006.257.08:18:29.21#ibcon#end of sib2, iclass 31, count 2 2006.257.08:18:29.21#ibcon#*after write, iclass 31, count 2 2006.257.08:18:29.21#ibcon#*before return 0, iclass 31, count 2 2006.257.08:18:29.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:29.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:18:29.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.08:18:29.21#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:29.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:29.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:29.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:29.33#ibcon#enter wrdev, iclass 31, count 0 2006.257.08:18:29.33#ibcon#first serial, iclass 31, count 0 2006.257.08:18:29.33#ibcon#enter sib2, iclass 31, count 0 2006.257.08:18:29.33#ibcon#flushed, iclass 31, count 0 2006.257.08:18:29.33#ibcon#about to write, iclass 31, count 0 2006.257.08:18:29.33#ibcon#wrote, iclass 31, count 0 2006.257.08:18:29.33#ibcon#about to read 3, iclass 31, count 0 2006.257.08:18:29.35#ibcon#read 3, iclass 31, count 0 2006.257.08:18:29.35#ibcon#about to read 4, iclass 31, count 0 2006.257.08:18:29.35#ibcon#read 4, iclass 31, count 0 2006.257.08:18:29.35#ibcon#about to read 5, iclass 31, count 0 2006.257.08:18:29.35#ibcon#read 5, iclass 31, count 0 2006.257.08:18:29.35#ibcon#about to read 6, iclass 31, count 0 2006.257.08:18:29.35#ibcon#read 6, iclass 31, count 0 2006.257.08:18:29.35#ibcon#end of sib2, iclass 31, count 0 2006.257.08:18:29.35#ibcon#*mode == 0, iclass 31, count 0 2006.257.08:18:29.35#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.08:18:29.35#ibcon#[27=USB\r\n] 2006.257.08:18:29.35#ibcon#*before write, iclass 31, count 0 2006.257.08:18:29.35#ibcon#enter sib2, iclass 31, count 0 2006.257.08:18:29.35#ibcon#flushed, iclass 31, count 0 2006.257.08:18:29.35#ibcon#about to write, iclass 31, count 0 2006.257.08:18:29.35#ibcon#wrote, iclass 31, count 0 2006.257.08:18:29.35#ibcon#about to read 3, iclass 31, count 0 2006.257.08:18:29.38#ibcon#read 3, iclass 31, count 0 2006.257.08:18:29.38#ibcon#about to read 4, iclass 31, count 0 2006.257.08:18:29.38#ibcon#read 4, iclass 31, count 0 2006.257.08:18:29.38#ibcon#about to read 5, iclass 31, count 0 2006.257.08:18:29.38#ibcon#read 5, iclass 31, count 0 2006.257.08:18:29.38#ibcon#about to read 6, iclass 31, count 0 2006.257.08:18:29.38#ibcon#read 6, iclass 31, count 0 2006.257.08:18:29.38#ibcon#end of sib2, iclass 31, count 0 2006.257.08:18:29.38#ibcon#*after write, iclass 31, count 0 2006.257.08:18:29.38#ibcon#*before return 0, iclass 31, count 0 2006.257.08:18:29.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:29.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:18:29.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.08:18:29.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.08:18:29.38$vck44/vblo=8,744.99 2006.257.08:18:29.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.08:18:29.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.08:18:29.38#ibcon#ireg 17 cls_cnt 0 2006.257.08:18:29.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:29.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:29.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:29.38#ibcon#enter wrdev, iclass 33, count 0 2006.257.08:18:29.38#ibcon#first serial, iclass 33, count 0 2006.257.08:18:29.38#ibcon#enter sib2, iclass 33, count 0 2006.257.08:18:29.38#ibcon#flushed, iclass 33, count 0 2006.257.08:18:29.38#ibcon#about to write, iclass 33, count 0 2006.257.08:18:29.38#ibcon#wrote, iclass 33, count 0 2006.257.08:18:29.38#ibcon#about to read 3, iclass 33, count 0 2006.257.08:18:29.40#ibcon#read 3, iclass 33, count 0 2006.257.08:18:29.40#ibcon#about to read 4, iclass 33, count 0 2006.257.08:18:29.40#ibcon#read 4, iclass 33, count 0 2006.257.08:18:29.40#ibcon#about to read 5, iclass 33, count 0 2006.257.08:18:29.40#ibcon#read 5, iclass 33, count 0 2006.257.08:18:29.40#ibcon#about to read 6, iclass 33, count 0 2006.257.08:18:29.40#ibcon#read 6, iclass 33, count 0 2006.257.08:18:29.40#ibcon#end of sib2, iclass 33, count 0 2006.257.08:18:29.40#ibcon#*mode == 0, iclass 33, count 0 2006.257.08:18:29.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.08:18:29.40#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:18:29.40#ibcon#*before write, iclass 33, count 0 2006.257.08:18:29.40#ibcon#enter sib2, iclass 33, count 0 2006.257.08:18:29.40#ibcon#flushed, iclass 33, count 0 2006.257.08:18:29.40#ibcon#about to write, iclass 33, count 0 2006.257.08:18:29.40#ibcon#wrote, iclass 33, count 0 2006.257.08:18:29.40#ibcon#about to read 3, iclass 33, count 0 2006.257.08:18:29.44#ibcon#read 3, iclass 33, count 0 2006.257.08:18:29.44#ibcon#about to read 4, iclass 33, count 0 2006.257.08:18:29.44#ibcon#read 4, iclass 33, count 0 2006.257.08:18:29.44#ibcon#about to read 5, iclass 33, count 0 2006.257.08:18:29.44#ibcon#read 5, iclass 33, count 0 2006.257.08:18:29.44#ibcon#about to read 6, iclass 33, count 0 2006.257.08:18:29.44#ibcon#read 6, iclass 33, count 0 2006.257.08:18:29.44#ibcon#end of sib2, iclass 33, count 0 2006.257.08:18:29.44#ibcon#*after write, iclass 33, count 0 2006.257.08:18:29.44#ibcon#*before return 0, iclass 33, count 0 2006.257.08:18:29.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:29.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:18:29.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.08:18:29.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.08:18:29.44$vck44/vb=8,4 2006.257.08:18:29.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.08:18:29.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.08:18:29.44#ibcon#ireg 11 cls_cnt 2 2006.257.08:18:29.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:29.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:29.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:29.50#ibcon#enter wrdev, iclass 35, count 2 2006.257.08:18:29.50#ibcon#first serial, iclass 35, count 2 2006.257.08:18:29.50#ibcon#enter sib2, iclass 35, count 2 2006.257.08:18:29.50#ibcon#flushed, iclass 35, count 2 2006.257.08:18:29.50#ibcon#about to write, iclass 35, count 2 2006.257.08:18:29.50#ibcon#wrote, iclass 35, count 2 2006.257.08:18:29.50#ibcon#about to read 3, iclass 35, count 2 2006.257.08:18:29.52#ibcon#read 3, iclass 35, count 2 2006.257.08:18:29.52#ibcon#about to read 4, iclass 35, count 2 2006.257.08:18:29.52#ibcon#read 4, iclass 35, count 2 2006.257.08:18:29.52#ibcon#about to read 5, iclass 35, count 2 2006.257.08:18:29.52#ibcon#read 5, iclass 35, count 2 2006.257.08:18:29.52#ibcon#about to read 6, iclass 35, count 2 2006.257.08:18:29.52#ibcon#read 6, iclass 35, count 2 2006.257.08:18:29.52#ibcon#end of sib2, iclass 35, count 2 2006.257.08:18:29.52#ibcon#*mode == 0, iclass 35, count 2 2006.257.08:18:29.52#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.08:18:29.52#ibcon#[27=AT08-04\r\n] 2006.257.08:18:29.52#ibcon#*before write, iclass 35, count 2 2006.257.08:18:29.52#ibcon#enter sib2, iclass 35, count 2 2006.257.08:18:29.52#ibcon#flushed, iclass 35, count 2 2006.257.08:18:29.52#ibcon#about to write, iclass 35, count 2 2006.257.08:18:29.52#ibcon#wrote, iclass 35, count 2 2006.257.08:18:29.52#ibcon#about to read 3, iclass 35, count 2 2006.257.08:18:29.55#ibcon#read 3, iclass 35, count 2 2006.257.08:18:29.55#ibcon#about to read 4, iclass 35, count 2 2006.257.08:18:29.55#ibcon#read 4, iclass 35, count 2 2006.257.08:18:29.55#ibcon#about to read 5, iclass 35, count 2 2006.257.08:18:29.55#ibcon#read 5, iclass 35, count 2 2006.257.08:18:29.55#ibcon#about to read 6, iclass 35, count 2 2006.257.08:18:29.55#ibcon#read 6, iclass 35, count 2 2006.257.08:18:29.55#ibcon#end of sib2, iclass 35, count 2 2006.257.08:18:29.55#ibcon#*after write, iclass 35, count 2 2006.257.08:18:29.57#ibcon#*before return 0, iclass 35, count 2 2006.257.08:18:29.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:29.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:18:29.58#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.08:18:29.58#ibcon#ireg 7 cls_cnt 0 2006.257.08:18:29.58#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:29.69#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:29.69#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:29.69#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:18:29.69#ibcon#first serial, iclass 35, count 0 2006.257.08:18:29.69#ibcon#enter sib2, iclass 35, count 0 2006.257.08:18:29.69#ibcon#flushed, iclass 35, count 0 2006.257.08:18:29.69#ibcon#about to write, iclass 35, count 0 2006.257.08:18:29.69#ibcon#wrote, iclass 35, count 0 2006.257.08:18:29.69#ibcon#about to read 3, iclass 35, count 0 2006.257.08:18:29.71#ibcon#read 3, iclass 35, count 0 2006.257.08:18:29.71#ibcon#about to read 4, iclass 35, count 0 2006.257.08:18:29.71#ibcon#read 4, iclass 35, count 0 2006.257.08:18:29.71#ibcon#about to read 5, iclass 35, count 0 2006.257.08:18:29.71#ibcon#read 5, iclass 35, count 0 2006.257.08:18:29.71#ibcon#about to read 6, iclass 35, count 0 2006.257.08:18:29.71#ibcon#read 6, iclass 35, count 0 2006.257.08:18:29.71#ibcon#end of sib2, iclass 35, count 0 2006.257.08:18:29.71#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:18:29.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:18:29.71#ibcon#[27=USB\r\n] 2006.257.08:18:29.71#ibcon#*before write, iclass 35, count 0 2006.257.08:18:29.71#ibcon#enter sib2, iclass 35, count 0 2006.257.08:18:29.71#ibcon#flushed, iclass 35, count 0 2006.257.08:18:29.71#ibcon#about to write, iclass 35, count 0 2006.257.08:18:29.71#ibcon#wrote, iclass 35, count 0 2006.257.08:18:29.71#ibcon#about to read 3, iclass 35, count 0 2006.257.08:18:29.74#ibcon#read 3, iclass 35, count 0 2006.257.08:18:29.74#ibcon#about to read 4, iclass 35, count 0 2006.257.08:18:29.74#ibcon#read 4, iclass 35, count 0 2006.257.08:18:29.74#ibcon#about to read 5, iclass 35, count 0 2006.257.08:18:29.74#ibcon#read 5, iclass 35, count 0 2006.257.08:18:29.74#ibcon#about to read 6, iclass 35, count 0 2006.257.08:18:29.74#ibcon#read 6, iclass 35, count 0 2006.257.08:18:29.74#ibcon#end of sib2, iclass 35, count 0 2006.257.08:18:29.74#ibcon#*after write, iclass 35, count 0 2006.257.08:18:29.74#ibcon#*before return 0, iclass 35, count 0 2006.257.08:18:29.74#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:29.74#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:18:29.74#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:18:29.74#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:18:29.74$vck44/vabw=wide 2006.257.08:18:29.74#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.08:18:29.74#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.08:18:29.74#ibcon#ireg 8 cls_cnt 0 2006.257.08:18:29.74#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:29.74#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:29.74#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:29.74#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:18:29.74#ibcon#first serial, iclass 37, count 0 2006.257.08:18:29.74#ibcon#enter sib2, iclass 37, count 0 2006.257.08:18:29.74#ibcon#flushed, iclass 37, count 0 2006.257.08:18:29.74#ibcon#about to write, iclass 37, count 0 2006.257.08:18:29.74#ibcon#wrote, iclass 37, count 0 2006.257.08:18:29.74#ibcon#about to read 3, iclass 37, count 0 2006.257.08:18:29.76#ibcon#read 3, iclass 37, count 0 2006.257.08:18:29.76#ibcon#about to read 4, iclass 37, count 0 2006.257.08:18:29.76#ibcon#read 4, iclass 37, count 0 2006.257.08:18:29.76#ibcon#about to read 5, iclass 37, count 0 2006.257.08:18:29.76#ibcon#read 5, iclass 37, count 0 2006.257.08:18:29.76#ibcon#about to read 6, iclass 37, count 0 2006.257.08:18:29.76#ibcon#read 6, iclass 37, count 0 2006.257.08:18:29.76#ibcon#end of sib2, iclass 37, count 0 2006.257.08:18:29.76#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:18:29.76#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:18:29.76#ibcon#[25=BW32\r\n] 2006.257.08:18:29.76#ibcon#*before write, iclass 37, count 0 2006.257.08:18:29.76#ibcon#enter sib2, iclass 37, count 0 2006.257.08:18:29.76#ibcon#flushed, iclass 37, count 0 2006.257.08:18:29.76#ibcon#about to write, iclass 37, count 0 2006.257.08:18:29.76#ibcon#wrote, iclass 37, count 0 2006.257.08:18:29.76#ibcon#about to read 3, iclass 37, count 0 2006.257.08:18:29.79#ibcon#read 3, iclass 37, count 0 2006.257.08:18:29.79#ibcon#about to read 4, iclass 37, count 0 2006.257.08:18:29.79#ibcon#read 4, iclass 37, count 0 2006.257.08:18:29.79#ibcon#about to read 5, iclass 37, count 0 2006.257.08:18:29.79#ibcon#read 5, iclass 37, count 0 2006.257.08:18:29.79#ibcon#about to read 6, iclass 37, count 0 2006.257.08:18:29.79#ibcon#read 6, iclass 37, count 0 2006.257.08:18:29.79#ibcon#end of sib2, iclass 37, count 0 2006.257.08:18:29.79#ibcon#*after write, iclass 37, count 0 2006.257.08:18:29.79#ibcon#*before return 0, iclass 37, count 0 2006.257.08:18:29.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:29.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:18:29.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:18:29.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:18:29.79$vck44/vbbw=wide 2006.257.08:18:29.79#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.08:18:29.79#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.08:18:29.79#ibcon#ireg 8 cls_cnt 0 2006.257.08:18:29.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:18:29.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:18:29.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:18:29.86#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:18:29.86#ibcon#first serial, iclass 39, count 0 2006.257.08:18:29.86#ibcon#enter sib2, iclass 39, count 0 2006.257.08:18:29.86#ibcon#flushed, iclass 39, count 0 2006.257.08:18:29.86#ibcon#about to write, iclass 39, count 0 2006.257.08:18:29.86#ibcon#wrote, iclass 39, count 0 2006.257.08:18:29.86#ibcon#about to read 3, iclass 39, count 0 2006.257.08:18:29.88#ibcon#read 3, iclass 39, count 0 2006.257.08:18:29.88#ibcon#about to read 4, iclass 39, count 0 2006.257.08:18:29.88#ibcon#read 4, iclass 39, count 0 2006.257.08:18:29.88#ibcon#about to read 5, iclass 39, count 0 2006.257.08:18:29.88#ibcon#read 5, iclass 39, count 0 2006.257.08:18:29.88#ibcon#about to read 6, iclass 39, count 0 2006.257.08:18:29.88#ibcon#read 6, iclass 39, count 0 2006.257.08:18:29.88#ibcon#end of sib2, iclass 39, count 0 2006.257.08:18:29.88#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:18:29.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:18:29.88#ibcon#[27=BW32\r\n] 2006.257.08:18:29.88#ibcon#*before write, iclass 39, count 0 2006.257.08:18:29.88#ibcon#enter sib2, iclass 39, count 0 2006.257.08:18:29.88#ibcon#flushed, iclass 39, count 0 2006.257.08:18:29.88#ibcon#about to write, iclass 39, count 0 2006.257.08:18:29.88#ibcon#wrote, iclass 39, count 0 2006.257.08:18:29.88#ibcon#about to read 3, iclass 39, count 0 2006.257.08:18:29.91#ibcon#read 3, iclass 39, count 0 2006.257.08:18:29.91#ibcon#about to read 4, iclass 39, count 0 2006.257.08:18:29.91#ibcon#read 4, iclass 39, count 0 2006.257.08:18:29.91#ibcon#about to read 5, iclass 39, count 0 2006.257.08:18:29.91#ibcon#read 5, iclass 39, count 0 2006.257.08:18:29.91#ibcon#about to read 6, iclass 39, count 0 2006.257.08:18:29.91#ibcon#read 6, iclass 39, count 0 2006.257.08:18:29.91#ibcon#end of sib2, iclass 39, count 0 2006.257.08:18:29.91#ibcon#*after write, iclass 39, count 0 2006.257.08:18:29.91#ibcon#*before return 0, iclass 39, count 0 2006.257.08:18:29.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:18:29.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:18:29.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:18:29.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:18:29.91$setupk4/ifdk4 2006.257.08:18:29.91$ifdk4/lo= 2006.257.08:18:29.91$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:18:29.91$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:18:29.91$ifdk4/patch= 2006.257.08:18:29.91$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:18:29.91$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:18:29.91$setupk4/!*+20s 2006.257.08:18:33.65#abcon#<5=/16 1.5 3.9 20.78 891012.9\r\n> 2006.257.08:18:33.67#abcon#{5=INTERFACE CLEAR} 2006.257.08:18:33.73#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:18:37.14#trakl#Source acquired 2006.257.08:18:37.14#flagr#flagr/antenna,acquired 2006.257.08:18:43.82#abcon#<5=/16 1.6 3.9 20.77 891012.9\r\n> 2006.257.08:18:43.84#abcon#{5=INTERFACE CLEAR} 2006.257.08:18:43.90#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:18:44.27$setupk4/"tpicd 2006.257.08:18:44.27$setupk4/echo=off 2006.257.08:18:44.27$setupk4/xlog=off 2006.257.08:18:44.27:!2006.257.08:19:30 2006.257.08:19:30.00:preob 2006.257.08:19:30.14/onsource/TRACKING 2006.257.08:19:30.14:!2006.257.08:19:40 2006.257.08:19:40.00:"tape 2006.257.08:19:40.00:"st=record 2006.257.08:19:40.00:data_valid=on 2006.257.08:19:40.00:midob 2006.257.08:19:40.14/onsource/TRACKING 2006.257.08:19:40.14/wx/20.77,1012.9,89 2006.257.08:19:40.27/cable/+6.4742E-03 2006.257.08:19:41.36/va/01,08,usb,yes,32,34 2006.257.08:19:41.36/va/02,07,usb,yes,35,35 2006.257.08:19:41.36/va/03,08,usb,yes,31,33 2006.257.08:19:41.36/va/04,07,usb,yes,35,37 2006.257.08:19:41.36/va/05,04,usb,yes,32,32 2006.257.08:19:41.36/va/06,04,usb,yes,36,35 2006.257.08:19:41.36/va/07,04,usb,yes,36,37 2006.257.08:19:41.36/va/08,04,usb,yes,30,37 2006.257.08:19:41.59/valo/01,524.99,yes,locked 2006.257.08:19:41.59/valo/02,534.99,yes,locked 2006.257.08:19:41.59/valo/03,564.99,yes,locked 2006.257.08:19:41.59/valo/04,624.99,yes,locked 2006.257.08:19:41.59/valo/05,734.99,yes,locked 2006.257.08:19:41.59/valo/06,814.99,yes,locked 2006.257.08:19:41.59/valo/07,864.99,yes,locked 2006.257.08:19:41.59/valo/08,884.99,yes,locked 2006.257.08:19:42.68/vb/01,04,usb,yes,31,29 2006.257.08:19:42.68/vb/02,05,usb,yes,30,29 2006.257.08:19:42.68/vb/03,04,usb,yes,31,33 2006.257.08:19:42.68/vb/04,05,usb,yes,31,30 2006.257.08:19:42.68/vb/05,04,usb,yes,27,29 2006.257.08:19:42.68/vb/06,04,usb,yes,32,28 2006.257.08:19:42.68/vb/07,04,usb,yes,31,31 2006.257.08:19:42.68/vb/08,04,usb,yes,29,32 2006.257.08:19:42.91/vblo/01,629.99,yes,locked 2006.257.08:19:42.91/vblo/02,634.99,yes,locked 2006.257.08:19:42.91/vblo/03,649.99,yes,locked 2006.257.08:19:42.91/vblo/04,679.99,yes,locked 2006.257.08:19:42.91/vblo/05,709.99,yes,locked 2006.257.08:19:42.91/vblo/06,719.99,yes,locked 2006.257.08:19:42.91/vblo/07,734.99,yes,locked 2006.257.08:19:42.91/vblo/08,744.99,yes,locked 2006.257.08:19:43.06/vabw/8 2006.257.08:19:43.21/vbbw/8 2006.257.08:19:43.30/xfe/off,on,15.2 2006.257.08:19:43.68/ifatt/23,28,28,28 2006.257.08:19:44.08/fmout-gps/S +4.54E-07 2006.257.08:19:44.12:!2006.257.08:24:20 2006.257.08:24:20.00:data_valid=off 2006.257.08:24:20.00:"et 2006.257.08:24:20.00:!+3s 2006.257.08:24:23.02:"tape 2006.257.08:24:23.02:postob 2006.257.08:24:23.12/cable/+6.4754E-03 2006.257.08:24:23.12/wx/20.74,1013.0,89 2006.257.08:24:23.18/fmout-gps/S +4.55E-07 2006.257.08:24:23.18:scan_name=257-0827,jd0609,80 2006.257.08:24:23.18:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.08:24:25.13#flagr#flagr/antenna,new-source 2006.257.08:24:25.13:checkk5 2006.257.08:24:25.62/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:24:26.02/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:24:26.42/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:24:26.82/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:24:27.20/chk_obsdata//k5ts1/T2570819??a.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.257.08:24:27.58/chk_obsdata//k5ts2/T2570819??b.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.257.08:24:27.96/chk_obsdata//k5ts3/T2570819??c.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.257.08:24:28.36/chk_obsdata//k5ts4/T2570819??d.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.257.08:24:29.10/k5log//k5ts1_log_newline 2006.257.08:24:29.82/k5log//k5ts2_log_newline 2006.257.08:24:30.52/k5log//k5ts3_log_newline 2006.257.08:24:31.22/k5log//k5ts4_log_newline 2006.257.08:24:31.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:24:31.25:setupk4=1 2006.257.08:24:31.25$setupk4/echo=on 2006.257.08:24:31.25$setupk4/pcalon 2006.257.08:24:31.25$pcalon/"no phase cal control is implemented here 2006.257.08:24:31.25$setupk4/"tpicd=stop 2006.257.08:24:31.25$setupk4/"rec=synch_on 2006.257.08:24:31.25$setupk4/"rec_mode=128 2006.257.08:24:31.25$setupk4/!* 2006.257.08:24:31.25$setupk4/recpk4 2006.257.08:24:31.25$recpk4/recpatch= 2006.257.08:24:31.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:24:31.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:24:31.25$setupk4/vck44 2006.257.08:24:31.25$vck44/valo=1,524.99 2006.257.08:24:31.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.08:24:31.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.08:24:31.25#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:31.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:31.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:31.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:31.25#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:24:31.25#ibcon#first serial, iclass 6, count 0 2006.257.08:24:31.25#ibcon#enter sib2, iclass 6, count 0 2006.257.08:24:31.25#ibcon#flushed, iclass 6, count 0 2006.257.08:24:31.25#ibcon#about to write, iclass 6, count 0 2006.257.08:24:31.25#ibcon#wrote, iclass 6, count 0 2006.257.08:24:31.25#ibcon#about to read 3, iclass 6, count 0 2006.257.08:24:31.27#ibcon#read 3, iclass 6, count 0 2006.257.08:24:31.27#ibcon#about to read 4, iclass 6, count 0 2006.257.08:24:31.27#ibcon#read 4, iclass 6, count 0 2006.257.08:24:31.27#ibcon#about to read 5, iclass 6, count 0 2006.257.08:24:31.27#ibcon#read 5, iclass 6, count 0 2006.257.08:24:31.27#ibcon#about to read 6, iclass 6, count 0 2006.257.08:24:31.27#ibcon#read 6, iclass 6, count 0 2006.257.08:24:31.27#ibcon#end of sib2, iclass 6, count 0 2006.257.08:24:31.27#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:24:31.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:24:31.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:24:31.27#ibcon#*before write, iclass 6, count 0 2006.257.08:24:31.27#ibcon#enter sib2, iclass 6, count 0 2006.257.08:24:31.27#ibcon#flushed, iclass 6, count 0 2006.257.08:24:31.27#ibcon#about to write, iclass 6, count 0 2006.257.08:24:31.27#ibcon#wrote, iclass 6, count 0 2006.257.08:24:31.27#ibcon#about to read 3, iclass 6, count 0 2006.257.08:24:31.32#ibcon#read 3, iclass 6, count 0 2006.257.08:24:31.32#ibcon#about to read 4, iclass 6, count 0 2006.257.08:24:31.32#ibcon#read 4, iclass 6, count 0 2006.257.08:24:31.32#ibcon#about to read 5, iclass 6, count 0 2006.257.08:24:31.32#ibcon#read 5, iclass 6, count 0 2006.257.08:24:31.32#ibcon#about to read 6, iclass 6, count 0 2006.257.08:24:31.32#ibcon#read 6, iclass 6, count 0 2006.257.08:24:31.32#ibcon#end of sib2, iclass 6, count 0 2006.257.08:24:31.32#ibcon#*after write, iclass 6, count 0 2006.257.08:24:31.32#ibcon#*before return 0, iclass 6, count 0 2006.257.08:24:31.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:31.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:31.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:24:31.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:24:31.32$vck44/va=1,8 2006.257.08:24:31.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.08:24:31.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.08:24:31.32#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:31.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:31.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:31.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:31.32#ibcon#enter wrdev, iclass 10, count 2 2006.257.08:24:31.32#ibcon#first serial, iclass 10, count 2 2006.257.08:24:31.32#ibcon#enter sib2, iclass 10, count 2 2006.257.08:24:31.32#ibcon#flushed, iclass 10, count 2 2006.257.08:24:31.32#ibcon#about to write, iclass 10, count 2 2006.257.08:24:31.32#ibcon#wrote, iclass 10, count 2 2006.257.08:24:31.32#ibcon#about to read 3, iclass 10, count 2 2006.257.08:24:31.34#ibcon#read 3, iclass 10, count 2 2006.257.08:24:31.34#ibcon#about to read 4, iclass 10, count 2 2006.257.08:24:31.34#ibcon#read 4, iclass 10, count 2 2006.257.08:24:31.34#ibcon#about to read 5, iclass 10, count 2 2006.257.08:24:31.34#ibcon#read 5, iclass 10, count 2 2006.257.08:24:31.34#ibcon#about to read 6, iclass 10, count 2 2006.257.08:24:31.34#ibcon#read 6, iclass 10, count 2 2006.257.08:24:31.34#ibcon#end of sib2, iclass 10, count 2 2006.257.08:24:31.34#ibcon#*mode == 0, iclass 10, count 2 2006.257.08:24:31.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.08:24:31.34#ibcon#[25=AT01-08\r\n] 2006.257.08:24:31.34#ibcon#*before write, iclass 10, count 2 2006.257.08:24:31.34#ibcon#enter sib2, iclass 10, count 2 2006.257.08:24:31.34#ibcon#flushed, iclass 10, count 2 2006.257.08:24:31.34#ibcon#about to write, iclass 10, count 2 2006.257.08:24:31.34#ibcon#wrote, iclass 10, count 2 2006.257.08:24:31.34#ibcon#about to read 3, iclass 10, count 2 2006.257.08:24:31.37#ibcon#read 3, iclass 10, count 2 2006.257.08:24:31.37#ibcon#about to read 4, iclass 10, count 2 2006.257.08:24:31.37#ibcon#read 4, iclass 10, count 2 2006.257.08:24:31.37#ibcon#about to read 5, iclass 10, count 2 2006.257.08:24:31.37#ibcon#read 5, iclass 10, count 2 2006.257.08:24:31.37#ibcon#about to read 6, iclass 10, count 2 2006.257.08:24:31.37#ibcon#read 6, iclass 10, count 2 2006.257.08:24:31.37#ibcon#end of sib2, iclass 10, count 2 2006.257.08:24:31.37#ibcon#*after write, iclass 10, count 2 2006.257.08:24:31.37#ibcon#*before return 0, iclass 10, count 2 2006.257.08:24:31.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:31.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:31.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.08:24:31.37#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:31.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:31.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:31.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:31.49#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:24:31.49#ibcon#first serial, iclass 10, count 0 2006.257.08:24:31.49#ibcon#enter sib2, iclass 10, count 0 2006.257.08:24:31.49#ibcon#flushed, iclass 10, count 0 2006.257.08:24:31.49#ibcon#about to write, iclass 10, count 0 2006.257.08:24:31.49#ibcon#wrote, iclass 10, count 0 2006.257.08:24:31.49#ibcon#about to read 3, iclass 10, count 0 2006.257.08:24:31.51#ibcon#read 3, iclass 10, count 0 2006.257.08:24:31.51#ibcon#about to read 4, iclass 10, count 0 2006.257.08:24:31.51#ibcon#read 4, iclass 10, count 0 2006.257.08:24:31.51#ibcon#about to read 5, iclass 10, count 0 2006.257.08:24:31.51#ibcon#read 5, iclass 10, count 0 2006.257.08:24:31.51#ibcon#about to read 6, iclass 10, count 0 2006.257.08:24:31.51#ibcon#read 6, iclass 10, count 0 2006.257.08:24:31.51#ibcon#end of sib2, iclass 10, count 0 2006.257.08:24:31.51#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:24:31.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:24:31.51#ibcon#[25=USB\r\n] 2006.257.08:24:31.51#ibcon#*before write, iclass 10, count 0 2006.257.08:24:31.51#ibcon#enter sib2, iclass 10, count 0 2006.257.08:24:31.51#ibcon#flushed, iclass 10, count 0 2006.257.08:24:31.51#ibcon#about to write, iclass 10, count 0 2006.257.08:24:31.51#ibcon#wrote, iclass 10, count 0 2006.257.08:24:31.51#ibcon#about to read 3, iclass 10, count 0 2006.257.08:24:31.54#ibcon#read 3, iclass 10, count 0 2006.257.08:24:31.54#ibcon#about to read 4, iclass 10, count 0 2006.257.08:24:31.54#ibcon#read 4, iclass 10, count 0 2006.257.08:24:31.54#ibcon#about to read 5, iclass 10, count 0 2006.257.08:24:31.54#ibcon#read 5, iclass 10, count 0 2006.257.08:24:31.54#ibcon#about to read 6, iclass 10, count 0 2006.257.08:24:31.54#ibcon#read 6, iclass 10, count 0 2006.257.08:24:31.54#ibcon#end of sib2, iclass 10, count 0 2006.257.08:24:31.54#ibcon#*after write, iclass 10, count 0 2006.257.08:24:31.54#ibcon#*before return 0, iclass 10, count 0 2006.257.08:24:31.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:31.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:31.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:24:31.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:24:31.54$vck44/valo=2,534.99 2006.257.08:24:31.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.08:24:31.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.08:24:31.54#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:31.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:31.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:31.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:31.54#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:24:31.54#ibcon#first serial, iclass 12, count 0 2006.257.08:24:31.54#ibcon#enter sib2, iclass 12, count 0 2006.257.08:24:31.54#ibcon#flushed, iclass 12, count 0 2006.257.08:24:31.54#ibcon#about to write, iclass 12, count 0 2006.257.08:24:31.54#ibcon#wrote, iclass 12, count 0 2006.257.08:24:31.54#ibcon#about to read 3, iclass 12, count 0 2006.257.08:24:31.56#ibcon#read 3, iclass 12, count 0 2006.257.08:24:31.56#ibcon#about to read 4, iclass 12, count 0 2006.257.08:24:31.56#ibcon#read 4, iclass 12, count 0 2006.257.08:24:31.56#ibcon#about to read 5, iclass 12, count 0 2006.257.08:24:31.56#ibcon#read 5, iclass 12, count 0 2006.257.08:24:31.56#ibcon#about to read 6, iclass 12, count 0 2006.257.08:24:31.56#ibcon#read 6, iclass 12, count 0 2006.257.08:24:31.56#ibcon#end of sib2, iclass 12, count 0 2006.257.08:24:31.56#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:24:31.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:24:31.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:24:31.56#ibcon#*before write, iclass 12, count 0 2006.257.08:24:31.56#ibcon#enter sib2, iclass 12, count 0 2006.257.08:24:31.56#ibcon#flushed, iclass 12, count 0 2006.257.08:24:31.56#ibcon#about to write, iclass 12, count 0 2006.257.08:24:31.56#ibcon#wrote, iclass 12, count 0 2006.257.08:24:31.56#ibcon#about to read 3, iclass 12, count 0 2006.257.08:24:31.60#ibcon#read 3, iclass 12, count 0 2006.257.08:24:31.60#ibcon#about to read 4, iclass 12, count 0 2006.257.08:24:31.60#ibcon#read 4, iclass 12, count 0 2006.257.08:24:31.60#ibcon#about to read 5, iclass 12, count 0 2006.257.08:24:31.60#ibcon#read 5, iclass 12, count 0 2006.257.08:24:31.60#ibcon#about to read 6, iclass 12, count 0 2006.257.08:24:31.60#ibcon#read 6, iclass 12, count 0 2006.257.08:24:31.60#ibcon#end of sib2, iclass 12, count 0 2006.257.08:24:31.60#ibcon#*after write, iclass 12, count 0 2006.257.08:24:31.60#ibcon#*before return 0, iclass 12, count 0 2006.257.08:24:31.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:31.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:31.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:24:31.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:24:31.60$vck44/va=2,7 2006.257.08:24:31.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.08:24:31.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.08:24:31.60#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:31.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:31.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:31.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:31.66#ibcon#enter wrdev, iclass 14, count 2 2006.257.08:24:31.66#ibcon#first serial, iclass 14, count 2 2006.257.08:24:31.66#ibcon#enter sib2, iclass 14, count 2 2006.257.08:24:31.66#ibcon#flushed, iclass 14, count 2 2006.257.08:24:31.66#ibcon#about to write, iclass 14, count 2 2006.257.08:24:31.66#ibcon#wrote, iclass 14, count 2 2006.257.08:24:31.66#ibcon#about to read 3, iclass 14, count 2 2006.257.08:24:31.68#ibcon#read 3, iclass 14, count 2 2006.257.08:24:31.68#ibcon#about to read 4, iclass 14, count 2 2006.257.08:24:31.68#ibcon#read 4, iclass 14, count 2 2006.257.08:24:31.68#ibcon#about to read 5, iclass 14, count 2 2006.257.08:24:31.68#ibcon#read 5, iclass 14, count 2 2006.257.08:24:31.68#ibcon#about to read 6, iclass 14, count 2 2006.257.08:24:31.68#ibcon#read 6, iclass 14, count 2 2006.257.08:24:31.68#ibcon#end of sib2, iclass 14, count 2 2006.257.08:24:31.68#ibcon#*mode == 0, iclass 14, count 2 2006.257.08:24:31.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.08:24:31.68#ibcon#[25=AT02-07\r\n] 2006.257.08:24:31.68#ibcon#*before write, iclass 14, count 2 2006.257.08:24:31.68#ibcon#enter sib2, iclass 14, count 2 2006.257.08:24:31.68#ibcon#flushed, iclass 14, count 2 2006.257.08:24:31.68#ibcon#about to write, iclass 14, count 2 2006.257.08:24:31.68#ibcon#wrote, iclass 14, count 2 2006.257.08:24:31.68#ibcon#about to read 3, iclass 14, count 2 2006.257.08:24:31.71#ibcon#read 3, iclass 14, count 2 2006.257.08:24:31.71#ibcon#about to read 4, iclass 14, count 2 2006.257.08:24:31.71#ibcon#read 4, iclass 14, count 2 2006.257.08:24:31.71#ibcon#about to read 5, iclass 14, count 2 2006.257.08:24:31.71#ibcon#read 5, iclass 14, count 2 2006.257.08:24:31.71#ibcon#about to read 6, iclass 14, count 2 2006.257.08:24:31.71#ibcon#read 6, iclass 14, count 2 2006.257.08:24:31.71#ibcon#end of sib2, iclass 14, count 2 2006.257.08:24:31.71#ibcon#*after write, iclass 14, count 2 2006.257.08:24:31.71#ibcon#*before return 0, iclass 14, count 2 2006.257.08:24:31.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:31.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:31.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.08:24:31.71#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:31.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:31.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:31.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:31.83#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:24:31.83#ibcon#first serial, iclass 14, count 0 2006.257.08:24:31.83#ibcon#enter sib2, iclass 14, count 0 2006.257.08:24:31.83#ibcon#flushed, iclass 14, count 0 2006.257.08:24:31.83#ibcon#about to write, iclass 14, count 0 2006.257.08:24:31.83#ibcon#wrote, iclass 14, count 0 2006.257.08:24:31.83#ibcon#about to read 3, iclass 14, count 0 2006.257.08:24:31.85#ibcon#read 3, iclass 14, count 0 2006.257.08:24:31.85#ibcon#about to read 4, iclass 14, count 0 2006.257.08:24:31.85#ibcon#read 4, iclass 14, count 0 2006.257.08:24:31.85#ibcon#about to read 5, iclass 14, count 0 2006.257.08:24:31.85#ibcon#read 5, iclass 14, count 0 2006.257.08:24:31.85#ibcon#about to read 6, iclass 14, count 0 2006.257.08:24:31.85#ibcon#read 6, iclass 14, count 0 2006.257.08:24:31.85#ibcon#end of sib2, iclass 14, count 0 2006.257.08:24:31.85#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:24:31.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:24:31.85#ibcon#[25=USB\r\n] 2006.257.08:24:31.85#ibcon#*before write, iclass 14, count 0 2006.257.08:24:31.85#ibcon#enter sib2, iclass 14, count 0 2006.257.08:24:31.85#ibcon#flushed, iclass 14, count 0 2006.257.08:24:31.85#ibcon#about to write, iclass 14, count 0 2006.257.08:24:31.85#ibcon#wrote, iclass 14, count 0 2006.257.08:24:31.85#ibcon#about to read 3, iclass 14, count 0 2006.257.08:24:31.88#ibcon#read 3, iclass 14, count 0 2006.257.08:24:31.88#ibcon#about to read 4, iclass 14, count 0 2006.257.08:24:31.88#ibcon#read 4, iclass 14, count 0 2006.257.08:24:31.88#ibcon#about to read 5, iclass 14, count 0 2006.257.08:24:31.88#ibcon#read 5, iclass 14, count 0 2006.257.08:24:31.88#ibcon#about to read 6, iclass 14, count 0 2006.257.08:24:31.88#ibcon#read 6, iclass 14, count 0 2006.257.08:24:31.88#ibcon#end of sib2, iclass 14, count 0 2006.257.08:24:31.88#ibcon#*after write, iclass 14, count 0 2006.257.08:24:31.88#ibcon#*before return 0, iclass 14, count 0 2006.257.08:24:31.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:31.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:31.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:24:31.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:24:31.88$vck44/valo=3,564.99 2006.257.08:24:31.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.08:24:31.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.08:24:31.88#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:31.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:31.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:31.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:31.88#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:24:31.88#ibcon#first serial, iclass 16, count 0 2006.257.08:24:31.88#ibcon#enter sib2, iclass 16, count 0 2006.257.08:24:31.88#ibcon#flushed, iclass 16, count 0 2006.257.08:24:31.88#ibcon#about to write, iclass 16, count 0 2006.257.08:24:31.88#ibcon#wrote, iclass 16, count 0 2006.257.08:24:31.88#ibcon#about to read 3, iclass 16, count 0 2006.257.08:24:31.90#ibcon#read 3, iclass 16, count 0 2006.257.08:24:31.90#ibcon#about to read 4, iclass 16, count 0 2006.257.08:24:31.90#ibcon#read 4, iclass 16, count 0 2006.257.08:24:31.90#ibcon#about to read 5, iclass 16, count 0 2006.257.08:24:31.90#ibcon#read 5, iclass 16, count 0 2006.257.08:24:31.90#ibcon#about to read 6, iclass 16, count 0 2006.257.08:24:31.90#ibcon#read 6, iclass 16, count 0 2006.257.08:24:31.90#ibcon#end of sib2, iclass 16, count 0 2006.257.08:24:31.90#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:24:31.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:24:31.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:24:31.90#ibcon#*before write, iclass 16, count 0 2006.257.08:24:31.90#ibcon#enter sib2, iclass 16, count 0 2006.257.08:24:31.90#ibcon#flushed, iclass 16, count 0 2006.257.08:24:31.90#ibcon#about to write, iclass 16, count 0 2006.257.08:24:31.90#ibcon#wrote, iclass 16, count 0 2006.257.08:24:31.90#ibcon#about to read 3, iclass 16, count 0 2006.257.08:24:31.94#ibcon#read 3, iclass 16, count 0 2006.257.08:24:31.94#ibcon#about to read 4, iclass 16, count 0 2006.257.08:24:31.94#ibcon#read 4, iclass 16, count 0 2006.257.08:24:31.94#ibcon#about to read 5, iclass 16, count 0 2006.257.08:24:31.94#ibcon#read 5, iclass 16, count 0 2006.257.08:24:31.94#ibcon#about to read 6, iclass 16, count 0 2006.257.08:24:31.94#ibcon#read 6, iclass 16, count 0 2006.257.08:24:31.94#ibcon#end of sib2, iclass 16, count 0 2006.257.08:24:31.94#ibcon#*after write, iclass 16, count 0 2006.257.08:24:31.94#ibcon#*before return 0, iclass 16, count 0 2006.257.08:24:31.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:31.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:31.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:24:31.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:24:31.94$vck44/va=3,8 2006.257.08:24:31.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.08:24:31.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.08:24:31.94#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:31.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:32.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:32.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:32.00#ibcon#enter wrdev, iclass 18, count 2 2006.257.08:24:32.00#ibcon#first serial, iclass 18, count 2 2006.257.08:24:32.00#ibcon#enter sib2, iclass 18, count 2 2006.257.08:24:32.00#ibcon#flushed, iclass 18, count 2 2006.257.08:24:32.00#ibcon#about to write, iclass 18, count 2 2006.257.08:24:32.00#ibcon#wrote, iclass 18, count 2 2006.257.08:24:32.00#ibcon#about to read 3, iclass 18, count 2 2006.257.08:24:32.02#ibcon#read 3, iclass 18, count 2 2006.257.08:24:32.02#ibcon#about to read 4, iclass 18, count 2 2006.257.08:24:32.02#ibcon#read 4, iclass 18, count 2 2006.257.08:24:32.02#ibcon#about to read 5, iclass 18, count 2 2006.257.08:24:32.02#ibcon#read 5, iclass 18, count 2 2006.257.08:24:32.02#ibcon#about to read 6, iclass 18, count 2 2006.257.08:24:32.02#ibcon#read 6, iclass 18, count 2 2006.257.08:24:32.02#ibcon#end of sib2, iclass 18, count 2 2006.257.08:24:32.02#ibcon#*mode == 0, iclass 18, count 2 2006.257.08:24:32.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.08:24:32.02#ibcon#[25=AT03-08\r\n] 2006.257.08:24:32.02#ibcon#*before write, iclass 18, count 2 2006.257.08:24:32.02#ibcon#enter sib2, iclass 18, count 2 2006.257.08:24:32.02#ibcon#flushed, iclass 18, count 2 2006.257.08:24:32.02#ibcon#about to write, iclass 18, count 2 2006.257.08:24:32.02#ibcon#wrote, iclass 18, count 2 2006.257.08:24:32.02#ibcon#about to read 3, iclass 18, count 2 2006.257.08:24:32.05#ibcon#read 3, iclass 18, count 2 2006.257.08:24:32.05#ibcon#about to read 4, iclass 18, count 2 2006.257.08:24:32.05#ibcon#read 4, iclass 18, count 2 2006.257.08:24:32.05#ibcon#about to read 5, iclass 18, count 2 2006.257.08:24:32.05#ibcon#read 5, iclass 18, count 2 2006.257.08:24:32.05#ibcon#about to read 6, iclass 18, count 2 2006.257.08:24:32.05#ibcon#read 6, iclass 18, count 2 2006.257.08:24:32.05#ibcon#end of sib2, iclass 18, count 2 2006.257.08:24:32.05#ibcon#*after write, iclass 18, count 2 2006.257.08:24:32.05#ibcon#*before return 0, iclass 18, count 2 2006.257.08:24:32.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:32.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:32.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.08:24:32.05#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:32.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:32.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:32.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:32.17#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:24:32.17#ibcon#first serial, iclass 18, count 0 2006.257.08:24:32.17#ibcon#enter sib2, iclass 18, count 0 2006.257.08:24:32.17#ibcon#flushed, iclass 18, count 0 2006.257.08:24:32.17#ibcon#about to write, iclass 18, count 0 2006.257.08:24:32.17#ibcon#wrote, iclass 18, count 0 2006.257.08:24:32.17#ibcon#about to read 3, iclass 18, count 0 2006.257.08:24:32.19#ibcon#read 3, iclass 18, count 0 2006.257.08:24:32.19#ibcon#about to read 4, iclass 18, count 0 2006.257.08:24:32.19#ibcon#read 4, iclass 18, count 0 2006.257.08:24:32.19#ibcon#about to read 5, iclass 18, count 0 2006.257.08:24:32.19#ibcon#read 5, iclass 18, count 0 2006.257.08:24:32.19#ibcon#about to read 6, iclass 18, count 0 2006.257.08:24:32.19#ibcon#read 6, iclass 18, count 0 2006.257.08:24:32.19#ibcon#end of sib2, iclass 18, count 0 2006.257.08:24:32.19#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:24:32.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:24:32.19#ibcon#[25=USB\r\n] 2006.257.08:24:32.19#ibcon#*before write, iclass 18, count 0 2006.257.08:24:32.19#ibcon#enter sib2, iclass 18, count 0 2006.257.08:24:32.19#ibcon#flushed, iclass 18, count 0 2006.257.08:24:32.19#ibcon#about to write, iclass 18, count 0 2006.257.08:24:32.19#ibcon#wrote, iclass 18, count 0 2006.257.08:24:32.19#ibcon#about to read 3, iclass 18, count 0 2006.257.08:24:32.22#ibcon#read 3, iclass 18, count 0 2006.257.08:24:32.22#ibcon#about to read 4, iclass 18, count 0 2006.257.08:24:32.22#ibcon#read 4, iclass 18, count 0 2006.257.08:24:32.22#ibcon#about to read 5, iclass 18, count 0 2006.257.08:24:32.22#ibcon#read 5, iclass 18, count 0 2006.257.08:24:32.22#ibcon#about to read 6, iclass 18, count 0 2006.257.08:24:32.22#ibcon#read 6, iclass 18, count 0 2006.257.08:24:32.22#ibcon#end of sib2, iclass 18, count 0 2006.257.08:24:32.22#ibcon#*after write, iclass 18, count 0 2006.257.08:24:32.22#ibcon#*before return 0, iclass 18, count 0 2006.257.08:24:32.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:32.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:32.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:24:32.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:24:32.22$vck44/valo=4,624.99 2006.257.08:24:32.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.08:24:32.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.08:24:32.22#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:32.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:32.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:32.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:32.22#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:24:32.22#ibcon#first serial, iclass 20, count 0 2006.257.08:24:32.22#ibcon#enter sib2, iclass 20, count 0 2006.257.08:24:32.22#ibcon#flushed, iclass 20, count 0 2006.257.08:24:32.22#ibcon#about to write, iclass 20, count 0 2006.257.08:24:32.22#ibcon#wrote, iclass 20, count 0 2006.257.08:24:32.22#ibcon#about to read 3, iclass 20, count 0 2006.257.08:24:32.24#ibcon#read 3, iclass 20, count 0 2006.257.08:24:32.24#ibcon#about to read 4, iclass 20, count 0 2006.257.08:24:32.24#ibcon#read 4, iclass 20, count 0 2006.257.08:24:32.24#ibcon#about to read 5, iclass 20, count 0 2006.257.08:24:32.24#ibcon#read 5, iclass 20, count 0 2006.257.08:24:32.24#ibcon#about to read 6, iclass 20, count 0 2006.257.08:24:32.24#ibcon#read 6, iclass 20, count 0 2006.257.08:24:32.24#ibcon#end of sib2, iclass 20, count 0 2006.257.08:24:32.24#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:24:32.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:24:32.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:24:32.24#ibcon#*before write, iclass 20, count 0 2006.257.08:24:32.24#ibcon#enter sib2, iclass 20, count 0 2006.257.08:24:32.24#ibcon#flushed, iclass 20, count 0 2006.257.08:24:32.24#ibcon#about to write, iclass 20, count 0 2006.257.08:24:32.24#ibcon#wrote, iclass 20, count 0 2006.257.08:24:32.24#ibcon#about to read 3, iclass 20, count 0 2006.257.08:24:32.28#ibcon#read 3, iclass 20, count 0 2006.257.08:24:32.28#ibcon#about to read 4, iclass 20, count 0 2006.257.08:24:32.28#ibcon#read 4, iclass 20, count 0 2006.257.08:24:32.28#ibcon#about to read 5, iclass 20, count 0 2006.257.08:24:32.28#ibcon#read 5, iclass 20, count 0 2006.257.08:24:32.28#ibcon#about to read 6, iclass 20, count 0 2006.257.08:24:32.28#ibcon#read 6, iclass 20, count 0 2006.257.08:24:32.28#ibcon#end of sib2, iclass 20, count 0 2006.257.08:24:32.28#ibcon#*after write, iclass 20, count 0 2006.257.08:24:32.28#ibcon#*before return 0, iclass 20, count 0 2006.257.08:24:32.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:32.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:32.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:24:32.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:24:32.28$vck44/va=4,7 2006.257.08:24:32.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.08:24:32.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.08:24:32.28#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:32.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:32.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:32.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:32.34#ibcon#enter wrdev, iclass 22, count 2 2006.257.08:24:32.34#ibcon#first serial, iclass 22, count 2 2006.257.08:24:32.34#ibcon#enter sib2, iclass 22, count 2 2006.257.08:24:32.34#ibcon#flushed, iclass 22, count 2 2006.257.08:24:32.34#ibcon#about to write, iclass 22, count 2 2006.257.08:24:32.34#ibcon#wrote, iclass 22, count 2 2006.257.08:24:32.34#ibcon#about to read 3, iclass 22, count 2 2006.257.08:24:32.36#ibcon#read 3, iclass 22, count 2 2006.257.08:24:32.36#ibcon#about to read 4, iclass 22, count 2 2006.257.08:24:32.36#ibcon#read 4, iclass 22, count 2 2006.257.08:24:32.36#ibcon#about to read 5, iclass 22, count 2 2006.257.08:24:32.36#ibcon#read 5, iclass 22, count 2 2006.257.08:24:32.36#ibcon#about to read 6, iclass 22, count 2 2006.257.08:24:32.36#ibcon#read 6, iclass 22, count 2 2006.257.08:24:32.36#ibcon#end of sib2, iclass 22, count 2 2006.257.08:24:32.36#ibcon#*mode == 0, iclass 22, count 2 2006.257.08:24:32.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.08:24:32.36#ibcon#[25=AT04-07\r\n] 2006.257.08:24:32.36#ibcon#*before write, iclass 22, count 2 2006.257.08:24:32.36#ibcon#enter sib2, iclass 22, count 2 2006.257.08:24:32.36#ibcon#flushed, iclass 22, count 2 2006.257.08:24:32.36#ibcon#about to write, iclass 22, count 2 2006.257.08:24:32.36#ibcon#wrote, iclass 22, count 2 2006.257.08:24:32.36#ibcon#about to read 3, iclass 22, count 2 2006.257.08:24:32.39#ibcon#read 3, iclass 22, count 2 2006.257.08:24:32.39#ibcon#about to read 4, iclass 22, count 2 2006.257.08:24:32.39#ibcon#read 4, iclass 22, count 2 2006.257.08:24:32.39#ibcon#about to read 5, iclass 22, count 2 2006.257.08:24:32.39#ibcon#read 5, iclass 22, count 2 2006.257.08:24:32.39#ibcon#about to read 6, iclass 22, count 2 2006.257.08:24:32.39#ibcon#read 6, iclass 22, count 2 2006.257.08:24:32.39#ibcon#end of sib2, iclass 22, count 2 2006.257.08:24:32.39#ibcon#*after write, iclass 22, count 2 2006.257.08:24:32.39#ibcon#*before return 0, iclass 22, count 2 2006.257.08:24:32.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:32.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:32.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.08:24:32.39#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:32.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:32.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:32.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:32.51#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:24:32.51#ibcon#first serial, iclass 22, count 0 2006.257.08:24:32.51#ibcon#enter sib2, iclass 22, count 0 2006.257.08:24:32.51#ibcon#flushed, iclass 22, count 0 2006.257.08:24:32.51#ibcon#about to write, iclass 22, count 0 2006.257.08:24:32.51#ibcon#wrote, iclass 22, count 0 2006.257.08:24:32.51#ibcon#about to read 3, iclass 22, count 0 2006.257.08:24:32.53#ibcon#read 3, iclass 22, count 0 2006.257.08:24:32.53#ibcon#about to read 4, iclass 22, count 0 2006.257.08:24:32.53#ibcon#read 4, iclass 22, count 0 2006.257.08:24:32.53#ibcon#about to read 5, iclass 22, count 0 2006.257.08:24:32.53#ibcon#read 5, iclass 22, count 0 2006.257.08:24:32.53#ibcon#about to read 6, iclass 22, count 0 2006.257.08:24:32.53#ibcon#read 6, iclass 22, count 0 2006.257.08:24:32.53#ibcon#end of sib2, iclass 22, count 0 2006.257.08:24:32.53#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:24:32.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:24:32.53#ibcon#[25=USB\r\n] 2006.257.08:24:32.53#ibcon#*before write, iclass 22, count 0 2006.257.08:24:32.53#ibcon#enter sib2, iclass 22, count 0 2006.257.08:24:32.53#ibcon#flushed, iclass 22, count 0 2006.257.08:24:32.53#ibcon#about to write, iclass 22, count 0 2006.257.08:24:32.53#ibcon#wrote, iclass 22, count 0 2006.257.08:24:32.53#ibcon#about to read 3, iclass 22, count 0 2006.257.08:24:32.56#ibcon#read 3, iclass 22, count 0 2006.257.08:24:32.56#ibcon#about to read 4, iclass 22, count 0 2006.257.08:24:32.56#ibcon#read 4, iclass 22, count 0 2006.257.08:24:32.56#ibcon#about to read 5, iclass 22, count 0 2006.257.08:24:32.56#ibcon#read 5, iclass 22, count 0 2006.257.08:24:32.56#ibcon#about to read 6, iclass 22, count 0 2006.257.08:24:32.56#ibcon#read 6, iclass 22, count 0 2006.257.08:24:32.56#ibcon#end of sib2, iclass 22, count 0 2006.257.08:24:32.56#ibcon#*after write, iclass 22, count 0 2006.257.08:24:32.56#ibcon#*before return 0, iclass 22, count 0 2006.257.08:24:32.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:32.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:32.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:24:32.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:24:32.56$vck44/valo=5,734.99 2006.257.08:24:32.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.08:24:32.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.08:24:32.56#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:32.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:32.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:32.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:32.56#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:24:32.56#ibcon#first serial, iclass 24, count 0 2006.257.08:24:32.56#ibcon#enter sib2, iclass 24, count 0 2006.257.08:24:32.56#ibcon#flushed, iclass 24, count 0 2006.257.08:24:32.56#ibcon#about to write, iclass 24, count 0 2006.257.08:24:32.56#ibcon#wrote, iclass 24, count 0 2006.257.08:24:32.56#ibcon#about to read 3, iclass 24, count 0 2006.257.08:24:32.58#ibcon#read 3, iclass 24, count 0 2006.257.08:24:32.58#ibcon#about to read 4, iclass 24, count 0 2006.257.08:24:32.58#ibcon#read 4, iclass 24, count 0 2006.257.08:24:32.58#ibcon#about to read 5, iclass 24, count 0 2006.257.08:24:32.58#ibcon#read 5, iclass 24, count 0 2006.257.08:24:32.58#ibcon#about to read 6, iclass 24, count 0 2006.257.08:24:32.58#ibcon#read 6, iclass 24, count 0 2006.257.08:24:32.58#ibcon#end of sib2, iclass 24, count 0 2006.257.08:24:32.58#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:24:32.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:24:32.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:24:32.58#ibcon#*before write, iclass 24, count 0 2006.257.08:24:32.58#ibcon#enter sib2, iclass 24, count 0 2006.257.08:24:32.58#ibcon#flushed, iclass 24, count 0 2006.257.08:24:32.58#ibcon#about to write, iclass 24, count 0 2006.257.08:24:32.58#ibcon#wrote, iclass 24, count 0 2006.257.08:24:32.58#ibcon#about to read 3, iclass 24, count 0 2006.257.08:24:32.62#ibcon#read 3, iclass 24, count 0 2006.257.08:24:32.62#ibcon#about to read 4, iclass 24, count 0 2006.257.08:24:32.62#ibcon#read 4, iclass 24, count 0 2006.257.08:24:32.62#ibcon#about to read 5, iclass 24, count 0 2006.257.08:24:32.62#ibcon#read 5, iclass 24, count 0 2006.257.08:24:32.62#ibcon#about to read 6, iclass 24, count 0 2006.257.08:24:32.62#ibcon#read 6, iclass 24, count 0 2006.257.08:24:32.62#ibcon#end of sib2, iclass 24, count 0 2006.257.08:24:32.62#ibcon#*after write, iclass 24, count 0 2006.257.08:24:32.62#ibcon#*before return 0, iclass 24, count 0 2006.257.08:24:32.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:32.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:32.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:24:32.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:24:32.62$vck44/va=5,4 2006.257.08:24:32.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.08:24:32.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.08:24:32.62#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:32.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:32.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:32.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:32.68#ibcon#enter wrdev, iclass 26, count 2 2006.257.08:24:32.68#ibcon#first serial, iclass 26, count 2 2006.257.08:24:32.68#ibcon#enter sib2, iclass 26, count 2 2006.257.08:24:32.68#ibcon#flushed, iclass 26, count 2 2006.257.08:24:32.68#ibcon#about to write, iclass 26, count 2 2006.257.08:24:32.68#ibcon#wrote, iclass 26, count 2 2006.257.08:24:32.68#ibcon#about to read 3, iclass 26, count 2 2006.257.08:24:32.70#ibcon#read 3, iclass 26, count 2 2006.257.08:24:32.70#ibcon#about to read 4, iclass 26, count 2 2006.257.08:24:32.70#ibcon#read 4, iclass 26, count 2 2006.257.08:24:32.70#ibcon#about to read 5, iclass 26, count 2 2006.257.08:24:32.70#ibcon#read 5, iclass 26, count 2 2006.257.08:24:32.70#ibcon#about to read 6, iclass 26, count 2 2006.257.08:24:32.70#ibcon#read 6, iclass 26, count 2 2006.257.08:24:32.70#ibcon#end of sib2, iclass 26, count 2 2006.257.08:24:32.70#ibcon#*mode == 0, iclass 26, count 2 2006.257.08:24:32.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.08:24:32.70#ibcon#[25=AT05-04\r\n] 2006.257.08:24:32.70#ibcon#*before write, iclass 26, count 2 2006.257.08:24:32.70#ibcon#enter sib2, iclass 26, count 2 2006.257.08:24:32.70#ibcon#flushed, iclass 26, count 2 2006.257.08:24:32.70#ibcon#about to write, iclass 26, count 2 2006.257.08:24:32.70#ibcon#wrote, iclass 26, count 2 2006.257.08:24:32.70#ibcon#about to read 3, iclass 26, count 2 2006.257.08:24:32.73#ibcon#read 3, iclass 26, count 2 2006.257.08:24:32.73#ibcon#about to read 4, iclass 26, count 2 2006.257.08:24:32.73#ibcon#read 4, iclass 26, count 2 2006.257.08:24:32.73#ibcon#about to read 5, iclass 26, count 2 2006.257.08:24:32.73#ibcon#read 5, iclass 26, count 2 2006.257.08:24:32.73#ibcon#about to read 6, iclass 26, count 2 2006.257.08:24:32.73#ibcon#read 6, iclass 26, count 2 2006.257.08:24:32.73#ibcon#end of sib2, iclass 26, count 2 2006.257.08:24:32.73#ibcon#*after write, iclass 26, count 2 2006.257.08:24:32.73#ibcon#*before return 0, iclass 26, count 2 2006.257.08:24:32.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:32.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:32.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.08:24:32.73#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:32.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:32.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:32.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:32.85#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:24:32.85#ibcon#first serial, iclass 26, count 0 2006.257.08:24:32.85#ibcon#enter sib2, iclass 26, count 0 2006.257.08:24:32.85#ibcon#flushed, iclass 26, count 0 2006.257.08:24:32.85#ibcon#about to write, iclass 26, count 0 2006.257.08:24:32.85#ibcon#wrote, iclass 26, count 0 2006.257.08:24:32.85#ibcon#about to read 3, iclass 26, count 0 2006.257.08:24:32.87#ibcon#read 3, iclass 26, count 0 2006.257.08:24:32.87#ibcon#about to read 4, iclass 26, count 0 2006.257.08:24:32.87#ibcon#read 4, iclass 26, count 0 2006.257.08:24:32.87#ibcon#about to read 5, iclass 26, count 0 2006.257.08:24:32.87#ibcon#read 5, iclass 26, count 0 2006.257.08:24:32.87#ibcon#about to read 6, iclass 26, count 0 2006.257.08:24:32.87#ibcon#read 6, iclass 26, count 0 2006.257.08:24:32.87#ibcon#end of sib2, iclass 26, count 0 2006.257.08:24:32.87#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:24:32.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:24:32.87#ibcon#[25=USB\r\n] 2006.257.08:24:32.87#ibcon#*before write, iclass 26, count 0 2006.257.08:24:32.87#ibcon#enter sib2, iclass 26, count 0 2006.257.08:24:32.87#ibcon#flushed, iclass 26, count 0 2006.257.08:24:32.87#ibcon#about to write, iclass 26, count 0 2006.257.08:24:32.87#ibcon#wrote, iclass 26, count 0 2006.257.08:24:32.87#ibcon#about to read 3, iclass 26, count 0 2006.257.08:24:32.90#ibcon#read 3, iclass 26, count 0 2006.257.08:24:32.90#ibcon#about to read 4, iclass 26, count 0 2006.257.08:24:32.90#ibcon#read 4, iclass 26, count 0 2006.257.08:24:32.90#ibcon#about to read 5, iclass 26, count 0 2006.257.08:24:32.90#ibcon#read 5, iclass 26, count 0 2006.257.08:24:32.90#ibcon#about to read 6, iclass 26, count 0 2006.257.08:24:32.90#ibcon#read 6, iclass 26, count 0 2006.257.08:24:32.90#ibcon#end of sib2, iclass 26, count 0 2006.257.08:24:32.90#ibcon#*after write, iclass 26, count 0 2006.257.08:24:32.90#ibcon#*before return 0, iclass 26, count 0 2006.257.08:24:32.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:32.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:32.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:24:32.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:24:32.90$vck44/valo=6,814.99 2006.257.08:24:32.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.08:24:32.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.08:24:32.90#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:32.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:32.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:32.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:32.90#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:24:32.90#ibcon#first serial, iclass 28, count 0 2006.257.08:24:32.90#ibcon#enter sib2, iclass 28, count 0 2006.257.08:24:32.90#ibcon#flushed, iclass 28, count 0 2006.257.08:24:32.90#ibcon#about to write, iclass 28, count 0 2006.257.08:24:32.90#ibcon#wrote, iclass 28, count 0 2006.257.08:24:32.90#ibcon#about to read 3, iclass 28, count 0 2006.257.08:24:32.92#ibcon#read 3, iclass 28, count 0 2006.257.08:24:32.92#ibcon#about to read 4, iclass 28, count 0 2006.257.08:24:32.92#ibcon#read 4, iclass 28, count 0 2006.257.08:24:32.92#ibcon#about to read 5, iclass 28, count 0 2006.257.08:24:32.92#ibcon#read 5, iclass 28, count 0 2006.257.08:24:32.92#ibcon#about to read 6, iclass 28, count 0 2006.257.08:24:32.92#ibcon#read 6, iclass 28, count 0 2006.257.08:24:32.92#ibcon#end of sib2, iclass 28, count 0 2006.257.08:24:32.92#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:24:32.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:24:32.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:24:32.92#ibcon#*before write, iclass 28, count 0 2006.257.08:24:32.92#ibcon#enter sib2, iclass 28, count 0 2006.257.08:24:32.92#ibcon#flushed, iclass 28, count 0 2006.257.08:24:32.92#ibcon#about to write, iclass 28, count 0 2006.257.08:24:32.92#ibcon#wrote, iclass 28, count 0 2006.257.08:24:32.92#ibcon#about to read 3, iclass 28, count 0 2006.257.08:24:32.96#ibcon#read 3, iclass 28, count 0 2006.257.08:24:32.96#ibcon#about to read 4, iclass 28, count 0 2006.257.08:24:32.96#ibcon#read 4, iclass 28, count 0 2006.257.08:24:32.96#ibcon#about to read 5, iclass 28, count 0 2006.257.08:24:32.96#ibcon#read 5, iclass 28, count 0 2006.257.08:24:32.96#ibcon#about to read 6, iclass 28, count 0 2006.257.08:24:32.96#ibcon#read 6, iclass 28, count 0 2006.257.08:24:32.96#ibcon#end of sib2, iclass 28, count 0 2006.257.08:24:32.96#ibcon#*after write, iclass 28, count 0 2006.257.08:24:32.96#ibcon#*before return 0, iclass 28, count 0 2006.257.08:24:32.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:32.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:32.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:24:32.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:24:32.96$vck44/va=6,4 2006.257.08:24:32.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.08:24:32.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.08:24:32.96#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:32.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:33.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:33.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:33.02#ibcon#enter wrdev, iclass 30, count 2 2006.257.08:24:33.02#ibcon#first serial, iclass 30, count 2 2006.257.08:24:33.02#ibcon#enter sib2, iclass 30, count 2 2006.257.08:24:33.02#ibcon#flushed, iclass 30, count 2 2006.257.08:24:33.02#ibcon#about to write, iclass 30, count 2 2006.257.08:24:33.02#ibcon#wrote, iclass 30, count 2 2006.257.08:24:33.02#ibcon#about to read 3, iclass 30, count 2 2006.257.08:24:33.04#ibcon#read 3, iclass 30, count 2 2006.257.08:24:33.04#ibcon#about to read 4, iclass 30, count 2 2006.257.08:24:33.04#ibcon#read 4, iclass 30, count 2 2006.257.08:24:33.04#ibcon#about to read 5, iclass 30, count 2 2006.257.08:24:33.04#ibcon#read 5, iclass 30, count 2 2006.257.08:24:33.04#ibcon#about to read 6, iclass 30, count 2 2006.257.08:24:33.04#ibcon#read 6, iclass 30, count 2 2006.257.08:24:33.04#ibcon#end of sib2, iclass 30, count 2 2006.257.08:24:33.04#ibcon#*mode == 0, iclass 30, count 2 2006.257.08:24:33.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.08:24:33.04#ibcon#[25=AT06-04\r\n] 2006.257.08:24:33.04#ibcon#*before write, iclass 30, count 2 2006.257.08:24:33.04#ibcon#enter sib2, iclass 30, count 2 2006.257.08:24:33.04#ibcon#flushed, iclass 30, count 2 2006.257.08:24:33.04#ibcon#about to write, iclass 30, count 2 2006.257.08:24:33.04#ibcon#wrote, iclass 30, count 2 2006.257.08:24:33.04#ibcon#about to read 3, iclass 30, count 2 2006.257.08:24:33.07#ibcon#read 3, iclass 30, count 2 2006.257.08:24:33.07#ibcon#about to read 4, iclass 30, count 2 2006.257.08:24:33.07#ibcon#read 4, iclass 30, count 2 2006.257.08:24:33.07#ibcon#about to read 5, iclass 30, count 2 2006.257.08:24:33.07#ibcon#read 5, iclass 30, count 2 2006.257.08:24:33.07#ibcon#about to read 6, iclass 30, count 2 2006.257.08:24:33.07#ibcon#read 6, iclass 30, count 2 2006.257.08:24:33.07#ibcon#end of sib2, iclass 30, count 2 2006.257.08:24:33.07#ibcon#*after write, iclass 30, count 2 2006.257.08:24:33.07#ibcon#*before return 0, iclass 30, count 2 2006.257.08:24:33.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:33.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:33.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.08:24:33.07#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:33.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:33.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:33.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:33.19#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:24:33.19#ibcon#first serial, iclass 30, count 0 2006.257.08:24:33.19#ibcon#enter sib2, iclass 30, count 0 2006.257.08:24:33.19#ibcon#flushed, iclass 30, count 0 2006.257.08:24:33.19#ibcon#about to write, iclass 30, count 0 2006.257.08:24:33.19#ibcon#wrote, iclass 30, count 0 2006.257.08:24:33.19#ibcon#about to read 3, iclass 30, count 0 2006.257.08:24:33.21#ibcon#read 3, iclass 30, count 0 2006.257.08:24:33.21#ibcon#about to read 4, iclass 30, count 0 2006.257.08:24:33.21#ibcon#read 4, iclass 30, count 0 2006.257.08:24:33.21#ibcon#about to read 5, iclass 30, count 0 2006.257.08:24:33.21#ibcon#read 5, iclass 30, count 0 2006.257.08:24:33.21#ibcon#about to read 6, iclass 30, count 0 2006.257.08:24:33.21#ibcon#read 6, iclass 30, count 0 2006.257.08:24:33.21#ibcon#end of sib2, iclass 30, count 0 2006.257.08:24:33.21#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:24:33.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:24:33.21#ibcon#[25=USB\r\n] 2006.257.08:24:33.21#ibcon#*before write, iclass 30, count 0 2006.257.08:24:33.21#ibcon#enter sib2, iclass 30, count 0 2006.257.08:24:33.21#ibcon#flushed, iclass 30, count 0 2006.257.08:24:33.21#ibcon#about to write, iclass 30, count 0 2006.257.08:24:33.21#ibcon#wrote, iclass 30, count 0 2006.257.08:24:33.21#ibcon#about to read 3, iclass 30, count 0 2006.257.08:24:33.24#ibcon#read 3, iclass 30, count 0 2006.257.08:24:33.24#ibcon#about to read 4, iclass 30, count 0 2006.257.08:24:33.24#ibcon#read 4, iclass 30, count 0 2006.257.08:24:33.24#ibcon#about to read 5, iclass 30, count 0 2006.257.08:24:33.24#ibcon#read 5, iclass 30, count 0 2006.257.08:24:33.24#ibcon#about to read 6, iclass 30, count 0 2006.257.08:24:33.24#ibcon#read 6, iclass 30, count 0 2006.257.08:24:33.24#ibcon#end of sib2, iclass 30, count 0 2006.257.08:24:33.24#ibcon#*after write, iclass 30, count 0 2006.257.08:24:33.24#ibcon#*before return 0, iclass 30, count 0 2006.257.08:24:33.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:33.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:33.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:24:33.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:24:33.24$vck44/valo=7,864.99 2006.257.08:24:33.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.08:24:33.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.08:24:33.24#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:33.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:33.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:33.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:33.24#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:24:33.24#ibcon#first serial, iclass 32, count 0 2006.257.08:24:33.24#ibcon#enter sib2, iclass 32, count 0 2006.257.08:24:33.24#ibcon#flushed, iclass 32, count 0 2006.257.08:24:33.24#ibcon#about to write, iclass 32, count 0 2006.257.08:24:33.24#ibcon#wrote, iclass 32, count 0 2006.257.08:24:33.24#ibcon#about to read 3, iclass 32, count 0 2006.257.08:24:33.26#ibcon#read 3, iclass 32, count 0 2006.257.08:24:33.26#ibcon#about to read 4, iclass 32, count 0 2006.257.08:24:33.26#ibcon#read 4, iclass 32, count 0 2006.257.08:24:33.26#ibcon#about to read 5, iclass 32, count 0 2006.257.08:24:33.26#ibcon#read 5, iclass 32, count 0 2006.257.08:24:33.26#ibcon#about to read 6, iclass 32, count 0 2006.257.08:24:33.26#ibcon#read 6, iclass 32, count 0 2006.257.08:24:33.26#ibcon#end of sib2, iclass 32, count 0 2006.257.08:24:33.26#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:24:33.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:24:33.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:24:33.26#ibcon#*before write, iclass 32, count 0 2006.257.08:24:33.26#ibcon#enter sib2, iclass 32, count 0 2006.257.08:24:33.26#ibcon#flushed, iclass 32, count 0 2006.257.08:24:33.26#ibcon#about to write, iclass 32, count 0 2006.257.08:24:33.26#ibcon#wrote, iclass 32, count 0 2006.257.08:24:33.26#ibcon#about to read 3, iclass 32, count 0 2006.257.08:24:33.30#ibcon#read 3, iclass 32, count 0 2006.257.08:24:33.30#ibcon#about to read 4, iclass 32, count 0 2006.257.08:24:33.30#ibcon#read 4, iclass 32, count 0 2006.257.08:24:33.30#ibcon#about to read 5, iclass 32, count 0 2006.257.08:24:33.30#ibcon#read 5, iclass 32, count 0 2006.257.08:24:33.30#ibcon#about to read 6, iclass 32, count 0 2006.257.08:24:33.30#ibcon#read 6, iclass 32, count 0 2006.257.08:24:33.30#ibcon#end of sib2, iclass 32, count 0 2006.257.08:24:33.30#ibcon#*after write, iclass 32, count 0 2006.257.08:24:33.30#ibcon#*before return 0, iclass 32, count 0 2006.257.08:24:33.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:33.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:33.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:24:33.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:24:33.30$vck44/va=7,4 2006.257.08:24:33.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.08:24:33.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.08:24:33.30#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:33.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:33.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:33.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:33.36#ibcon#enter wrdev, iclass 34, count 2 2006.257.08:24:33.36#ibcon#first serial, iclass 34, count 2 2006.257.08:24:33.36#ibcon#enter sib2, iclass 34, count 2 2006.257.08:24:33.36#ibcon#flushed, iclass 34, count 2 2006.257.08:24:33.36#ibcon#about to write, iclass 34, count 2 2006.257.08:24:33.36#ibcon#wrote, iclass 34, count 2 2006.257.08:24:33.36#ibcon#about to read 3, iclass 34, count 2 2006.257.08:24:33.38#ibcon#read 3, iclass 34, count 2 2006.257.08:24:33.38#ibcon#about to read 4, iclass 34, count 2 2006.257.08:24:33.38#ibcon#read 4, iclass 34, count 2 2006.257.08:24:33.38#ibcon#about to read 5, iclass 34, count 2 2006.257.08:24:33.38#ibcon#read 5, iclass 34, count 2 2006.257.08:24:33.38#ibcon#about to read 6, iclass 34, count 2 2006.257.08:24:33.38#ibcon#read 6, iclass 34, count 2 2006.257.08:24:33.38#ibcon#end of sib2, iclass 34, count 2 2006.257.08:24:33.38#ibcon#*mode == 0, iclass 34, count 2 2006.257.08:24:33.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.08:24:33.38#ibcon#[25=AT07-04\r\n] 2006.257.08:24:33.38#ibcon#*before write, iclass 34, count 2 2006.257.08:24:33.38#ibcon#enter sib2, iclass 34, count 2 2006.257.08:24:33.38#ibcon#flushed, iclass 34, count 2 2006.257.08:24:33.38#ibcon#about to write, iclass 34, count 2 2006.257.08:24:33.38#ibcon#wrote, iclass 34, count 2 2006.257.08:24:33.38#ibcon#about to read 3, iclass 34, count 2 2006.257.08:24:33.41#ibcon#read 3, iclass 34, count 2 2006.257.08:24:33.41#ibcon#about to read 4, iclass 34, count 2 2006.257.08:24:33.41#ibcon#read 4, iclass 34, count 2 2006.257.08:24:33.41#ibcon#about to read 5, iclass 34, count 2 2006.257.08:24:33.41#ibcon#read 5, iclass 34, count 2 2006.257.08:24:33.41#ibcon#about to read 6, iclass 34, count 2 2006.257.08:24:33.41#ibcon#read 6, iclass 34, count 2 2006.257.08:24:33.41#ibcon#end of sib2, iclass 34, count 2 2006.257.08:24:33.41#ibcon#*after write, iclass 34, count 2 2006.257.08:24:33.41#ibcon#*before return 0, iclass 34, count 2 2006.257.08:24:33.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:33.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:33.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.08:24:33.41#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:33.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:33.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:33.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:33.53#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:24:33.53#ibcon#first serial, iclass 34, count 0 2006.257.08:24:33.53#ibcon#enter sib2, iclass 34, count 0 2006.257.08:24:33.53#ibcon#flushed, iclass 34, count 0 2006.257.08:24:33.53#ibcon#about to write, iclass 34, count 0 2006.257.08:24:33.53#ibcon#wrote, iclass 34, count 0 2006.257.08:24:33.53#ibcon#about to read 3, iclass 34, count 0 2006.257.08:24:33.55#ibcon#read 3, iclass 34, count 0 2006.257.08:24:33.55#ibcon#about to read 4, iclass 34, count 0 2006.257.08:24:33.55#ibcon#read 4, iclass 34, count 0 2006.257.08:24:33.55#ibcon#about to read 5, iclass 34, count 0 2006.257.08:24:33.55#ibcon#read 5, iclass 34, count 0 2006.257.08:24:33.55#ibcon#about to read 6, iclass 34, count 0 2006.257.08:24:33.55#ibcon#read 6, iclass 34, count 0 2006.257.08:24:33.55#ibcon#end of sib2, iclass 34, count 0 2006.257.08:24:33.55#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:24:33.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:24:33.55#ibcon#[25=USB\r\n] 2006.257.08:24:33.55#ibcon#*before write, iclass 34, count 0 2006.257.08:24:33.55#ibcon#enter sib2, iclass 34, count 0 2006.257.08:24:33.55#ibcon#flushed, iclass 34, count 0 2006.257.08:24:33.55#ibcon#about to write, iclass 34, count 0 2006.257.08:24:33.55#ibcon#wrote, iclass 34, count 0 2006.257.08:24:33.55#ibcon#about to read 3, iclass 34, count 0 2006.257.08:24:33.58#ibcon#read 3, iclass 34, count 0 2006.257.08:24:33.58#ibcon#about to read 4, iclass 34, count 0 2006.257.08:24:33.58#ibcon#read 4, iclass 34, count 0 2006.257.08:24:33.58#ibcon#about to read 5, iclass 34, count 0 2006.257.08:24:33.58#ibcon#read 5, iclass 34, count 0 2006.257.08:24:33.58#ibcon#about to read 6, iclass 34, count 0 2006.257.08:24:33.58#ibcon#read 6, iclass 34, count 0 2006.257.08:24:33.58#ibcon#end of sib2, iclass 34, count 0 2006.257.08:24:33.58#ibcon#*after write, iclass 34, count 0 2006.257.08:24:33.58#ibcon#*before return 0, iclass 34, count 0 2006.257.08:24:33.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:33.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:33.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:24:33.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:24:33.58$vck44/valo=8,884.99 2006.257.08:24:33.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.08:24:33.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.08:24:33.58#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:33.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:33.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:33.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:33.58#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:24:33.58#ibcon#first serial, iclass 36, count 0 2006.257.08:24:33.58#ibcon#enter sib2, iclass 36, count 0 2006.257.08:24:33.58#ibcon#flushed, iclass 36, count 0 2006.257.08:24:33.58#ibcon#about to write, iclass 36, count 0 2006.257.08:24:33.58#ibcon#wrote, iclass 36, count 0 2006.257.08:24:33.58#ibcon#about to read 3, iclass 36, count 0 2006.257.08:24:33.60#ibcon#read 3, iclass 36, count 0 2006.257.08:24:33.60#ibcon#about to read 4, iclass 36, count 0 2006.257.08:24:33.60#ibcon#read 4, iclass 36, count 0 2006.257.08:24:33.60#ibcon#about to read 5, iclass 36, count 0 2006.257.08:24:33.60#ibcon#read 5, iclass 36, count 0 2006.257.08:24:33.60#ibcon#about to read 6, iclass 36, count 0 2006.257.08:24:33.60#ibcon#read 6, iclass 36, count 0 2006.257.08:24:33.60#ibcon#end of sib2, iclass 36, count 0 2006.257.08:24:33.60#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:24:33.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:24:33.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:24:33.60#ibcon#*before write, iclass 36, count 0 2006.257.08:24:33.60#ibcon#enter sib2, iclass 36, count 0 2006.257.08:24:33.60#ibcon#flushed, iclass 36, count 0 2006.257.08:24:33.60#ibcon#about to write, iclass 36, count 0 2006.257.08:24:33.60#ibcon#wrote, iclass 36, count 0 2006.257.08:24:33.60#ibcon#about to read 3, iclass 36, count 0 2006.257.08:24:33.64#ibcon#read 3, iclass 36, count 0 2006.257.08:24:33.64#ibcon#about to read 4, iclass 36, count 0 2006.257.08:24:33.64#ibcon#read 4, iclass 36, count 0 2006.257.08:24:33.64#ibcon#about to read 5, iclass 36, count 0 2006.257.08:24:33.64#ibcon#read 5, iclass 36, count 0 2006.257.08:24:33.64#ibcon#about to read 6, iclass 36, count 0 2006.257.08:24:33.64#ibcon#read 6, iclass 36, count 0 2006.257.08:24:33.64#ibcon#end of sib2, iclass 36, count 0 2006.257.08:24:33.64#ibcon#*after write, iclass 36, count 0 2006.257.08:24:33.64#ibcon#*before return 0, iclass 36, count 0 2006.257.08:24:33.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:33.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:33.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:24:33.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:24:33.64$vck44/va=8,4 2006.257.08:24:33.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.08:24:33.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.08:24:33.64#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:33.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:24:33.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:24:33.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:24:33.70#ibcon#enter wrdev, iclass 38, count 2 2006.257.08:24:33.70#ibcon#first serial, iclass 38, count 2 2006.257.08:24:33.70#ibcon#enter sib2, iclass 38, count 2 2006.257.08:24:33.70#ibcon#flushed, iclass 38, count 2 2006.257.08:24:33.70#ibcon#about to write, iclass 38, count 2 2006.257.08:24:33.70#ibcon#wrote, iclass 38, count 2 2006.257.08:24:33.70#ibcon#about to read 3, iclass 38, count 2 2006.257.08:24:33.72#ibcon#read 3, iclass 38, count 2 2006.257.08:24:33.72#ibcon#about to read 4, iclass 38, count 2 2006.257.08:24:33.72#ibcon#read 4, iclass 38, count 2 2006.257.08:24:33.72#ibcon#about to read 5, iclass 38, count 2 2006.257.08:24:33.72#ibcon#read 5, iclass 38, count 2 2006.257.08:24:33.72#ibcon#about to read 6, iclass 38, count 2 2006.257.08:24:33.72#ibcon#read 6, iclass 38, count 2 2006.257.08:24:33.72#ibcon#end of sib2, iclass 38, count 2 2006.257.08:24:33.72#ibcon#*mode == 0, iclass 38, count 2 2006.257.08:24:33.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.08:24:33.72#ibcon#[25=AT08-04\r\n] 2006.257.08:24:33.72#ibcon#*before write, iclass 38, count 2 2006.257.08:24:33.72#ibcon#enter sib2, iclass 38, count 2 2006.257.08:24:33.72#ibcon#flushed, iclass 38, count 2 2006.257.08:24:33.72#ibcon#about to write, iclass 38, count 2 2006.257.08:24:33.72#ibcon#wrote, iclass 38, count 2 2006.257.08:24:33.72#ibcon#about to read 3, iclass 38, count 2 2006.257.08:24:33.75#ibcon#read 3, iclass 38, count 2 2006.257.08:24:33.75#ibcon#about to read 4, iclass 38, count 2 2006.257.08:24:33.75#ibcon#read 4, iclass 38, count 2 2006.257.08:24:33.75#ibcon#about to read 5, iclass 38, count 2 2006.257.08:24:33.75#ibcon#read 5, iclass 38, count 2 2006.257.08:24:33.75#ibcon#about to read 6, iclass 38, count 2 2006.257.08:24:33.75#ibcon#read 6, iclass 38, count 2 2006.257.08:24:33.75#ibcon#end of sib2, iclass 38, count 2 2006.257.08:24:33.75#ibcon#*after write, iclass 38, count 2 2006.257.08:24:33.75#ibcon#*before return 0, iclass 38, count 2 2006.257.08:24:33.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:24:33.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:24:33.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.08:24:33.75#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:33.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:24:33.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:24:33.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:24:33.87#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:24:33.87#ibcon#first serial, iclass 38, count 0 2006.257.08:24:33.87#ibcon#enter sib2, iclass 38, count 0 2006.257.08:24:33.87#ibcon#flushed, iclass 38, count 0 2006.257.08:24:33.87#ibcon#about to write, iclass 38, count 0 2006.257.08:24:33.87#ibcon#wrote, iclass 38, count 0 2006.257.08:24:33.87#ibcon#about to read 3, iclass 38, count 0 2006.257.08:24:33.89#ibcon#read 3, iclass 38, count 0 2006.257.08:24:33.89#ibcon#about to read 4, iclass 38, count 0 2006.257.08:24:33.89#ibcon#read 4, iclass 38, count 0 2006.257.08:24:33.89#ibcon#about to read 5, iclass 38, count 0 2006.257.08:24:33.89#ibcon#read 5, iclass 38, count 0 2006.257.08:24:33.89#ibcon#about to read 6, iclass 38, count 0 2006.257.08:24:33.89#ibcon#read 6, iclass 38, count 0 2006.257.08:24:33.89#ibcon#end of sib2, iclass 38, count 0 2006.257.08:24:33.89#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:24:33.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:24:33.89#ibcon#[25=USB\r\n] 2006.257.08:24:33.89#ibcon#*before write, iclass 38, count 0 2006.257.08:24:33.89#ibcon#enter sib2, iclass 38, count 0 2006.257.08:24:33.89#ibcon#flushed, iclass 38, count 0 2006.257.08:24:33.89#ibcon#about to write, iclass 38, count 0 2006.257.08:24:33.89#ibcon#wrote, iclass 38, count 0 2006.257.08:24:33.89#ibcon#about to read 3, iclass 38, count 0 2006.257.08:24:33.92#ibcon#read 3, iclass 38, count 0 2006.257.08:24:33.92#ibcon#about to read 4, iclass 38, count 0 2006.257.08:24:33.92#ibcon#read 4, iclass 38, count 0 2006.257.08:24:33.92#ibcon#about to read 5, iclass 38, count 0 2006.257.08:24:33.92#ibcon#read 5, iclass 38, count 0 2006.257.08:24:33.92#ibcon#about to read 6, iclass 38, count 0 2006.257.08:24:33.92#ibcon#read 6, iclass 38, count 0 2006.257.08:24:33.92#ibcon#end of sib2, iclass 38, count 0 2006.257.08:24:33.92#ibcon#*after write, iclass 38, count 0 2006.257.08:24:33.92#ibcon#*before return 0, iclass 38, count 0 2006.257.08:24:33.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:24:33.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:24:33.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:24:33.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:24:33.92$vck44/vblo=1,629.99 2006.257.08:24:33.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.08:24:33.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.08:24:33.92#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:33.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:24:33.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:24:33.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:24:33.92#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:24:33.92#ibcon#first serial, iclass 40, count 0 2006.257.08:24:33.92#ibcon#enter sib2, iclass 40, count 0 2006.257.08:24:33.92#ibcon#flushed, iclass 40, count 0 2006.257.08:24:33.92#ibcon#about to write, iclass 40, count 0 2006.257.08:24:33.92#ibcon#wrote, iclass 40, count 0 2006.257.08:24:33.92#ibcon#about to read 3, iclass 40, count 0 2006.257.08:24:33.94#ibcon#read 3, iclass 40, count 0 2006.257.08:24:33.94#ibcon#about to read 4, iclass 40, count 0 2006.257.08:24:33.94#ibcon#read 4, iclass 40, count 0 2006.257.08:24:33.94#ibcon#about to read 5, iclass 40, count 0 2006.257.08:24:33.94#ibcon#read 5, iclass 40, count 0 2006.257.08:24:33.94#ibcon#about to read 6, iclass 40, count 0 2006.257.08:24:33.94#ibcon#read 6, iclass 40, count 0 2006.257.08:24:33.94#ibcon#end of sib2, iclass 40, count 0 2006.257.08:24:33.94#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:24:33.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:24:33.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:24:33.94#ibcon#*before write, iclass 40, count 0 2006.257.08:24:33.94#ibcon#enter sib2, iclass 40, count 0 2006.257.08:24:33.94#ibcon#flushed, iclass 40, count 0 2006.257.08:24:33.94#ibcon#about to write, iclass 40, count 0 2006.257.08:24:33.94#ibcon#wrote, iclass 40, count 0 2006.257.08:24:33.94#ibcon#about to read 3, iclass 40, count 0 2006.257.08:24:33.98#ibcon#read 3, iclass 40, count 0 2006.257.08:24:33.98#ibcon#about to read 4, iclass 40, count 0 2006.257.08:24:33.98#ibcon#read 4, iclass 40, count 0 2006.257.08:24:33.98#ibcon#about to read 5, iclass 40, count 0 2006.257.08:24:33.98#ibcon#read 5, iclass 40, count 0 2006.257.08:24:33.98#ibcon#about to read 6, iclass 40, count 0 2006.257.08:24:33.98#ibcon#read 6, iclass 40, count 0 2006.257.08:24:33.98#ibcon#end of sib2, iclass 40, count 0 2006.257.08:24:33.98#ibcon#*after write, iclass 40, count 0 2006.257.08:24:33.98#ibcon#*before return 0, iclass 40, count 0 2006.257.08:24:33.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:24:33.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:24:33.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:24:33.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:24:33.98$vck44/vb=1,4 2006.257.08:24:33.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.08:24:33.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.08:24:33.98#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:33.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:24:33.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:24:33.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:24:33.98#ibcon#enter wrdev, iclass 4, count 2 2006.257.08:24:33.98#ibcon#first serial, iclass 4, count 2 2006.257.08:24:33.98#ibcon#enter sib2, iclass 4, count 2 2006.257.08:24:33.98#ibcon#flushed, iclass 4, count 2 2006.257.08:24:33.98#ibcon#about to write, iclass 4, count 2 2006.257.08:24:33.98#ibcon#wrote, iclass 4, count 2 2006.257.08:24:33.98#ibcon#about to read 3, iclass 4, count 2 2006.257.08:24:34.00#ibcon#read 3, iclass 4, count 2 2006.257.08:24:34.00#ibcon#about to read 4, iclass 4, count 2 2006.257.08:24:34.00#ibcon#read 4, iclass 4, count 2 2006.257.08:24:34.00#ibcon#about to read 5, iclass 4, count 2 2006.257.08:24:34.00#ibcon#read 5, iclass 4, count 2 2006.257.08:24:34.00#ibcon#about to read 6, iclass 4, count 2 2006.257.08:24:34.00#ibcon#read 6, iclass 4, count 2 2006.257.08:24:34.00#ibcon#end of sib2, iclass 4, count 2 2006.257.08:24:34.00#ibcon#*mode == 0, iclass 4, count 2 2006.257.08:24:34.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.08:24:34.00#ibcon#[27=AT01-04\r\n] 2006.257.08:24:34.00#ibcon#*before write, iclass 4, count 2 2006.257.08:24:34.00#ibcon#enter sib2, iclass 4, count 2 2006.257.08:24:34.00#ibcon#flushed, iclass 4, count 2 2006.257.08:24:34.00#ibcon#about to write, iclass 4, count 2 2006.257.08:24:34.00#ibcon#wrote, iclass 4, count 2 2006.257.08:24:34.00#ibcon#about to read 3, iclass 4, count 2 2006.257.08:24:34.03#ibcon#read 3, iclass 4, count 2 2006.257.08:24:34.03#ibcon#about to read 4, iclass 4, count 2 2006.257.08:24:34.03#ibcon#read 4, iclass 4, count 2 2006.257.08:24:34.03#ibcon#about to read 5, iclass 4, count 2 2006.257.08:24:34.03#ibcon#read 5, iclass 4, count 2 2006.257.08:24:34.03#ibcon#about to read 6, iclass 4, count 2 2006.257.08:24:34.03#ibcon#read 6, iclass 4, count 2 2006.257.08:24:34.03#ibcon#end of sib2, iclass 4, count 2 2006.257.08:24:34.03#ibcon#*after write, iclass 4, count 2 2006.257.08:24:34.03#ibcon#*before return 0, iclass 4, count 2 2006.257.08:24:34.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:24:34.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:24:34.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.08:24:34.03#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:34.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:24:34.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:24:34.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:24:34.15#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:24:34.15#ibcon#first serial, iclass 4, count 0 2006.257.08:24:34.15#ibcon#enter sib2, iclass 4, count 0 2006.257.08:24:34.15#ibcon#flushed, iclass 4, count 0 2006.257.08:24:34.15#ibcon#about to write, iclass 4, count 0 2006.257.08:24:34.15#ibcon#wrote, iclass 4, count 0 2006.257.08:24:34.15#ibcon#about to read 3, iclass 4, count 0 2006.257.08:24:34.17#ibcon#read 3, iclass 4, count 0 2006.257.08:24:34.17#ibcon#about to read 4, iclass 4, count 0 2006.257.08:24:34.17#ibcon#read 4, iclass 4, count 0 2006.257.08:24:34.17#ibcon#about to read 5, iclass 4, count 0 2006.257.08:24:34.17#ibcon#read 5, iclass 4, count 0 2006.257.08:24:34.17#ibcon#about to read 6, iclass 4, count 0 2006.257.08:24:34.17#ibcon#read 6, iclass 4, count 0 2006.257.08:24:34.17#ibcon#end of sib2, iclass 4, count 0 2006.257.08:24:34.17#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:24:34.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:24:34.17#ibcon#[27=USB\r\n] 2006.257.08:24:34.17#ibcon#*before write, iclass 4, count 0 2006.257.08:24:34.17#ibcon#enter sib2, iclass 4, count 0 2006.257.08:24:34.17#ibcon#flushed, iclass 4, count 0 2006.257.08:24:34.17#ibcon#about to write, iclass 4, count 0 2006.257.08:24:34.17#ibcon#wrote, iclass 4, count 0 2006.257.08:24:34.17#ibcon#about to read 3, iclass 4, count 0 2006.257.08:24:34.20#ibcon#read 3, iclass 4, count 0 2006.257.08:24:34.20#ibcon#about to read 4, iclass 4, count 0 2006.257.08:24:34.20#ibcon#read 4, iclass 4, count 0 2006.257.08:24:34.20#ibcon#about to read 5, iclass 4, count 0 2006.257.08:24:34.20#ibcon#read 5, iclass 4, count 0 2006.257.08:24:34.20#ibcon#about to read 6, iclass 4, count 0 2006.257.08:24:34.20#ibcon#read 6, iclass 4, count 0 2006.257.08:24:34.20#ibcon#end of sib2, iclass 4, count 0 2006.257.08:24:34.20#ibcon#*after write, iclass 4, count 0 2006.257.08:24:34.20#ibcon#*before return 0, iclass 4, count 0 2006.257.08:24:34.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:24:34.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:24:34.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:24:34.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:24:34.20$vck44/vblo=2,634.99 2006.257.08:24:34.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.08:24:34.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.08:24:34.20#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:34.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:34.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:34.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:34.20#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:24:34.20#ibcon#first serial, iclass 6, count 0 2006.257.08:24:34.20#ibcon#enter sib2, iclass 6, count 0 2006.257.08:24:34.20#ibcon#flushed, iclass 6, count 0 2006.257.08:24:34.20#ibcon#about to write, iclass 6, count 0 2006.257.08:24:34.20#ibcon#wrote, iclass 6, count 0 2006.257.08:24:34.20#ibcon#about to read 3, iclass 6, count 0 2006.257.08:24:34.22#ibcon#read 3, iclass 6, count 0 2006.257.08:24:34.22#ibcon#about to read 4, iclass 6, count 0 2006.257.08:24:34.22#ibcon#read 4, iclass 6, count 0 2006.257.08:24:34.22#ibcon#about to read 5, iclass 6, count 0 2006.257.08:24:34.22#ibcon#read 5, iclass 6, count 0 2006.257.08:24:34.22#ibcon#about to read 6, iclass 6, count 0 2006.257.08:24:34.22#ibcon#read 6, iclass 6, count 0 2006.257.08:24:34.22#ibcon#end of sib2, iclass 6, count 0 2006.257.08:24:34.22#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:24:34.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:24:34.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:24:34.22#ibcon#*before write, iclass 6, count 0 2006.257.08:24:34.22#ibcon#enter sib2, iclass 6, count 0 2006.257.08:24:34.22#ibcon#flushed, iclass 6, count 0 2006.257.08:24:34.22#ibcon#about to write, iclass 6, count 0 2006.257.08:24:34.22#ibcon#wrote, iclass 6, count 0 2006.257.08:24:34.22#ibcon#about to read 3, iclass 6, count 0 2006.257.08:24:34.26#ibcon#read 3, iclass 6, count 0 2006.257.08:24:34.26#ibcon#about to read 4, iclass 6, count 0 2006.257.08:24:34.26#ibcon#read 4, iclass 6, count 0 2006.257.08:24:34.26#ibcon#about to read 5, iclass 6, count 0 2006.257.08:24:34.26#ibcon#read 5, iclass 6, count 0 2006.257.08:24:34.26#ibcon#about to read 6, iclass 6, count 0 2006.257.08:24:34.26#ibcon#read 6, iclass 6, count 0 2006.257.08:24:34.26#ibcon#end of sib2, iclass 6, count 0 2006.257.08:24:34.26#ibcon#*after write, iclass 6, count 0 2006.257.08:24:34.26#ibcon#*before return 0, iclass 6, count 0 2006.257.08:24:34.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:34.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:24:34.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:24:34.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:24:34.26$vck44/vb=2,5 2006.257.08:24:34.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.08:24:34.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.08:24:34.26#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:34.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:34.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:34.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:34.32#ibcon#enter wrdev, iclass 10, count 2 2006.257.08:24:34.32#ibcon#first serial, iclass 10, count 2 2006.257.08:24:34.32#ibcon#enter sib2, iclass 10, count 2 2006.257.08:24:34.32#ibcon#flushed, iclass 10, count 2 2006.257.08:24:34.32#ibcon#about to write, iclass 10, count 2 2006.257.08:24:34.32#ibcon#wrote, iclass 10, count 2 2006.257.08:24:34.32#ibcon#about to read 3, iclass 10, count 2 2006.257.08:24:34.34#ibcon#read 3, iclass 10, count 2 2006.257.08:24:34.34#ibcon#about to read 4, iclass 10, count 2 2006.257.08:24:34.34#ibcon#read 4, iclass 10, count 2 2006.257.08:24:34.34#ibcon#about to read 5, iclass 10, count 2 2006.257.08:24:34.34#ibcon#read 5, iclass 10, count 2 2006.257.08:24:34.34#ibcon#about to read 6, iclass 10, count 2 2006.257.08:24:34.34#ibcon#read 6, iclass 10, count 2 2006.257.08:24:34.34#ibcon#end of sib2, iclass 10, count 2 2006.257.08:24:34.34#ibcon#*mode == 0, iclass 10, count 2 2006.257.08:24:34.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.08:24:34.34#ibcon#[27=AT02-05\r\n] 2006.257.08:24:34.34#ibcon#*before write, iclass 10, count 2 2006.257.08:24:34.34#ibcon#enter sib2, iclass 10, count 2 2006.257.08:24:34.34#ibcon#flushed, iclass 10, count 2 2006.257.08:24:34.34#ibcon#about to write, iclass 10, count 2 2006.257.08:24:34.34#ibcon#wrote, iclass 10, count 2 2006.257.08:24:34.34#ibcon#about to read 3, iclass 10, count 2 2006.257.08:24:34.37#ibcon#read 3, iclass 10, count 2 2006.257.08:24:34.37#ibcon#about to read 4, iclass 10, count 2 2006.257.08:24:34.37#ibcon#read 4, iclass 10, count 2 2006.257.08:24:34.37#ibcon#about to read 5, iclass 10, count 2 2006.257.08:24:34.37#ibcon#read 5, iclass 10, count 2 2006.257.08:24:34.37#ibcon#about to read 6, iclass 10, count 2 2006.257.08:24:34.37#ibcon#read 6, iclass 10, count 2 2006.257.08:24:34.37#ibcon#end of sib2, iclass 10, count 2 2006.257.08:24:34.37#ibcon#*after write, iclass 10, count 2 2006.257.08:24:34.37#ibcon#*before return 0, iclass 10, count 2 2006.257.08:24:34.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:34.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:24:34.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.08:24:34.37#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:34.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:34.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:34.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:34.49#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:24:34.49#ibcon#first serial, iclass 10, count 0 2006.257.08:24:34.49#ibcon#enter sib2, iclass 10, count 0 2006.257.08:24:34.49#ibcon#flushed, iclass 10, count 0 2006.257.08:24:34.49#ibcon#about to write, iclass 10, count 0 2006.257.08:24:34.49#ibcon#wrote, iclass 10, count 0 2006.257.08:24:34.49#ibcon#about to read 3, iclass 10, count 0 2006.257.08:24:34.51#ibcon#read 3, iclass 10, count 0 2006.257.08:24:34.51#ibcon#about to read 4, iclass 10, count 0 2006.257.08:24:34.51#ibcon#read 4, iclass 10, count 0 2006.257.08:24:34.51#ibcon#about to read 5, iclass 10, count 0 2006.257.08:24:34.51#ibcon#read 5, iclass 10, count 0 2006.257.08:24:34.51#ibcon#about to read 6, iclass 10, count 0 2006.257.08:24:34.51#ibcon#read 6, iclass 10, count 0 2006.257.08:24:34.51#ibcon#end of sib2, iclass 10, count 0 2006.257.08:24:34.51#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:24:34.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:24:34.51#ibcon#[27=USB\r\n] 2006.257.08:24:34.51#ibcon#*before write, iclass 10, count 0 2006.257.08:24:34.51#ibcon#enter sib2, iclass 10, count 0 2006.257.08:24:34.51#ibcon#flushed, iclass 10, count 0 2006.257.08:24:34.51#ibcon#about to write, iclass 10, count 0 2006.257.08:24:34.51#ibcon#wrote, iclass 10, count 0 2006.257.08:24:34.51#ibcon#about to read 3, iclass 10, count 0 2006.257.08:24:34.54#ibcon#read 3, iclass 10, count 0 2006.257.08:24:34.54#ibcon#about to read 4, iclass 10, count 0 2006.257.08:24:34.54#ibcon#read 4, iclass 10, count 0 2006.257.08:24:34.54#ibcon#about to read 5, iclass 10, count 0 2006.257.08:24:34.54#ibcon#read 5, iclass 10, count 0 2006.257.08:24:34.54#ibcon#about to read 6, iclass 10, count 0 2006.257.08:24:34.54#ibcon#read 6, iclass 10, count 0 2006.257.08:24:34.54#ibcon#end of sib2, iclass 10, count 0 2006.257.08:24:34.54#ibcon#*after write, iclass 10, count 0 2006.257.08:24:34.54#ibcon#*before return 0, iclass 10, count 0 2006.257.08:24:34.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:34.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:24:34.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:24:34.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:24:34.54$vck44/vblo=3,649.99 2006.257.08:24:34.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.08:24:34.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.08:24:34.54#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:34.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:34.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:34.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:34.54#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:24:34.54#ibcon#first serial, iclass 12, count 0 2006.257.08:24:34.54#ibcon#enter sib2, iclass 12, count 0 2006.257.08:24:34.54#ibcon#flushed, iclass 12, count 0 2006.257.08:24:34.54#ibcon#about to write, iclass 12, count 0 2006.257.08:24:34.54#ibcon#wrote, iclass 12, count 0 2006.257.08:24:34.54#ibcon#about to read 3, iclass 12, count 0 2006.257.08:24:34.56#ibcon#read 3, iclass 12, count 0 2006.257.08:24:34.56#ibcon#about to read 4, iclass 12, count 0 2006.257.08:24:34.56#ibcon#read 4, iclass 12, count 0 2006.257.08:24:34.56#ibcon#about to read 5, iclass 12, count 0 2006.257.08:24:34.56#ibcon#read 5, iclass 12, count 0 2006.257.08:24:34.56#ibcon#about to read 6, iclass 12, count 0 2006.257.08:24:34.56#ibcon#read 6, iclass 12, count 0 2006.257.08:24:34.56#ibcon#end of sib2, iclass 12, count 0 2006.257.08:24:34.56#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:24:34.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:24:34.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:24:34.56#ibcon#*before write, iclass 12, count 0 2006.257.08:24:34.56#ibcon#enter sib2, iclass 12, count 0 2006.257.08:24:34.56#ibcon#flushed, iclass 12, count 0 2006.257.08:24:34.56#ibcon#about to write, iclass 12, count 0 2006.257.08:24:34.56#ibcon#wrote, iclass 12, count 0 2006.257.08:24:34.56#ibcon#about to read 3, iclass 12, count 0 2006.257.08:24:34.60#ibcon#read 3, iclass 12, count 0 2006.257.08:24:34.60#ibcon#about to read 4, iclass 12, count 0 2006.257.08:24:34.60#ibcon#read 4, iclass 12, count 0 2006.257.08:24:34.60#ibcon#about to read 5, iclass 12, count 0 2006.257.08:24:34.60#ibcon#read 5, iclass 12, count 0 2006.257.08:24:34.60#ibcon#about to read 6, iclass 12, count 0 2006.257.08:24:34.60#ibcon#read 6, iclass 12, count 0 2006.257.08:24:34.60#ibcon#end of sib2, iclass 12, count 0 2006.257.08:24:34.60#ibcon#*after write, iclass 12, count 0 2006.257.08:24:34.60#ibcon#*before return 0, iclass 12, count 0 2006.257.08:24:34.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:34.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:24:34.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:24:34.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:24:34.60$vck44/vb=3,4 2006.257.08:24:34.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.08:24:34.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.08:24:34.60#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:34.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:34.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:34.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:34.66#ibcon#enter wrdev, iclass 14, count 2 2006.257.08:24:34.66#ibcon#first serial, iclass 14, count 2 2006.257.08:24:34.66#ibcon#enter sib2, iclass 14, count 2 2006.257.08:24:34.66#ibcon#flushed, iclass 14, count 2 2006.257.08:24:34.66#ibcon#about to write, iclass 14, count 2 2006.257.08:24:34.66#ibcon#wrote, iclass 14, count 2 2006.257.08:24:34.66#ibcon#about to read 3, iclass 14, count 2 2006.257.08:24:34.68#ibcon#read 3, iclass 14, count 2 2006.257.08:24:34.68#ibcon#about to read 4, iclass 14, count 2 2006.257.08:24:34.68#ibcon#read 4, iclass 14, count 2 2006.257.08:24:34.68#ibcon#about to read 5, iclass 14, count 2 2006.257.08:24:34.68#ibcon#read 5, iclass 14, count 2 2006.257.08:24:34.68#ibcon#about to read 6, iclass 14, count 2 2006.257.08:24:34.68#ibcon#read 6, iclass 14, count 2 2006.257.08:24:34.68#ibcon#end of sib2, iclass 14, count 2 2006.257.08:24:34.68#ibcon#*mode == 0, iclass 14, count 2 2006.257.08:24:34.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.08:24:34.68#ibcon#[27=AT03-04\r\n] 2006.257.08:24:34.68#ibcon#*before write, iclass 14, count 2 2006.257.08:24:34.68#ibcon#enter sib2, iclass 14, count 2 2006.257.08:24:34.68#ibcon#flushed, iclass 14, count 2 2006.257.08:24:34.68#ibcon#about to write, iclass 14, count 2 2006.257.08:24:34.68#ibcon#wrote, iclass 14, count 2 2006.257.08:24:34.68#ibcon#about to read 3, iclass 14, count 2 2006.257.08:24:34.71#ibcon#read 3, iclass 14, count 2 2006.257.08:24:34.71#ibcon#about to read 4, iclass 14, count 2 2006.257.08:24:34.71#ibcon#read 4, iclass 14, count 2 2006.257.08:24:34.71#ibcon#about to read 5, iclass 14, count 2 2006.257.08:24:34.71#ibcon#read 5, iclass 14, count 2 2006.257.08:24:34.71#ibcon#about to read 6, iclass 14, count 2 2006.257.08:24:34.71#ibcon#read 6, iclass 14, count 2 2006.257.08:24:34.71#ibcon#end of sib2, iclass 14, count 2 2006.257.08:24:34.71#ibcon#*after write, iclass 14, count 2 2006.257.08:24:34.71#ibcon#*before return 0, iclass 14, count 2 2006.257.08:24:34.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:34.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:24:34.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.08:24:34.71#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:34.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:34.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:34.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:34.83#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:24:34.83#ibcon#first serial, iclass 14, count 0 2006.257.08:24:34.83#ibcon#enter sib2, iclass 14, count 0 2006.257.08:24:34.83#ibcon#flushed, iclass 14, count 0 2006.257.08:24:34.83#ibcon#about to write, iclass 14, count 0 2006.257.08:24:34.83#ibcon#wrote, iclass 14, count 0 2006.257.08:24:34.83#ibcon#about to read 3, iclass 14, count 0 2006.257.08:24:34.85#ibcon#read 3, iclass 14, count 0 2006.257.08:24:34.85#ibcon#about to read 4, iclass 14, count 0 2006.257.08:24:34.85#ibcon#read 4, iclass 14, count 0 2006.257.08:24:34.85#ibcon#about to read 5, iclass 14, count 0 2006.257.08:24:34.85#ibcon#read 5, iclass 14, count 0 2006.257.08:24:34.85#ibcon#about to read 6, iclass 14, count 0 2006.257.08:24:34.85#ibcon#read 6, iclass 14, count 0 2006.257.08:24:34.85#ibcon#end of sib2, iclass 14, count 0 2006.257.08:24:34.85#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:24:34.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:24:34.85#ibcon#[27=USB\r\n] 2006.257.08:24:34.85#ibcon#*before write, iclass 14, count 0 2006.257.08:24:34.85#ibcon#enter sib2, iclass 14, count 0 2006.257.08:24:34.85#ibcon#flushed, iclass 14, count 0 2006.257.08:24:34.85#ibcon#about to write, iclass 14, count 0 2006.257.08:24:34.85#ibcon#wrote, iclass 14, count 0 2006.257.08:24:34.85#ibcon#about to read 3, iclass 14, count 0 2006.257.08:24:34.88#ibcon#read 3, iclass 14, count 0 2006.257.08:24:34.88#ibcon#about to read 4, iclass 14, count 0 2006.257.08:24:34.88#ibcon#read 4, iclass 14, count 0 2006.257.08:24:34.88#ibcon#about to read 5, iclass 14, count 0 2006.257.08:24:34.88#ibcon#read 5, iclass 14, count 0 2006.257.08:24:34.88#ibcon#about to read 6, iclass 14, count 0 2006.257.08:24:34.88#ibcon#read 6, iclass 14, count 0 2006.257.08:24:34.88#ibcon#end of sib2, iclass 14, count 0 2006.257.08:24:34.88#ibcon#*after write, iclass 14, count 0 2006.257.08:24:34.88#ibcon#*before return 0, iclass 14, count 0 2006.257.08:24:34.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:34.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:24:34.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:24:34.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:24:34.88$vck44/vblo=4,679.99 2006.257.08:24:34.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.08:24:34.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.08:24:34.88#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:34.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:34.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:34.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:34.88#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:24:34.88#ibcon#first serial, iclass 16, count 0 2006.257.08:24:34.88#ibcon#enter sib2, iclass 16, count 0 2006.257.08:24:34.88#ibcon#flushed, iclass 16, count 0 2006.257.08:24:34.88#ibcon#about to write, iclass 16, count 0 2006.257.08:24:34.88#ibcon#wrote, iclass 16, count 0 2006.257.08:24:34.88#ibcon#about to read 3, iclass 16, count 0 2006.257.08:24:34.90#ibcon#read 3, iclass 16, count 0 2006.257.08:24:34.90#ibcon#about to read 4, iclass 16, count 0 2006.257.08:24:34.90#ibcon#read 4, iclass 16, count 0 2006.257.08:24:34.90#ibcon#about to read 5, iclass 16, count 0 2006.257.08:24:34.90#ibcon#read 5, iclass 16, count 0 2006.257.08:24:34.90#ibcon#about to read 6, iclass 16, count 0 2006.257.08:24:34.90#ibcon#read 6, iclass 16, count 0 2006.257.08:24:34.90#ibcon#end of sib2, iclass 16, count 0 2006.257.08:24:34.90#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:24:34.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:24:34.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:24:34.90#ibcon#*before write, iclass 16, count 0 2006.257.08:24:34.90#ibcon#enter sib2, iclass 16, count 0 2006.257.08:24:34.90#ibcon#flushed, iclass 16, count 0 2006.257.08:24:34.90#ibcon#about to write, iclass 16, count 0 2006.257.08:24:34.90#ibcon#wrote, iclass 16, count 0 2006.257.08:24:34.90#ibcon#about to read 3, iclass 16, count 0 2006.257.08:24:34.94#ibcon#read 3, iclass 16, count 0 2006.257.08:24:34.94#ibcon#about to read 4, iclass 16, count 0 2006.257.08:24:34.94#ibcon#read 4, iclass 16, count 0 2006.257.08:24:34.94#ibcon#about to read 5, iclass 16, count 0 2006.257.08:24:34.94#ibcon#read 5, iclass 16, count 0 2006.257.08:24:34.94#ibcon#about to read 6, iclass 16, count 0 2006.257.08:24:34.94#ibcon#read 6, iclass 16, count 0 2006.257.08:24:34.94#ibcon#end of sib2, iclass 16, count 0 2006.257.08:24:34.94#ibcon#*after write, iclass 16, count 0 2006.257.08:24:34.94#ibcon#*before return 0, iclass 16, count 0 2006.257.08:24:34.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:34.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:24:34.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:24:34.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:24:34.94$vck44/vb=4,5 2006.257.08:24:34.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.08:24:34.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.08:24:34.94#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:34.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:35.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:35.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:35.00#ibcon#enter wrdev, iclass 18, count 2 2006.257.08:24:35.00#ibcon#first serial, iclass 18, count 2 2006.257.08:24:35.00#ibcon#enter sib2, iclass 18, count 2 2006.257.08:24:35.00#ibcon#flushed, iclass 18, count 2 2006.257.08:24:35.00#ibcon#about to write, iclass 18, count 2 2006.257.08:24:35.00#ibcon#wrote, iclass 18, count 2 2006.257.08:24:35.00#ibcon#about to read 3, iclass 18, count 2 2006.257.08:24:35.02#ibcon#read 3, iclass 18, count 2 2006.257.08:24:35.02#ibcon#about to read 4, iclass 18, count 2 2006.257.08:24:35.02#ibcon#read 4, iclass 18, count 2 2006.257.08:24:35.02#ibcon#about to read 5, iclass 18, count 2 2006.257.08:24:35.02#ibcon#read 5, iclass 18, count 2 2006.257.08:24:35.02#ibcon#about to read 6, iclass 18, count 2 2006.257.08:24:35.02#ibcon#read 6, iclass 18, count 2 2006.257.08:24:35.02#ibcon#end of sib2, iclass 18, count 2 2006.257.08:24:35.02#ibcon#*mode == 0, iclass 18, count 2 2006.257.08:24:35.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.08:24:35.02#ibcon#[27=AT04-05\r\n] 2006.257.08:24:35.02#ibcon#*before write, iclass 18, count 2 2006.257.08:24:35.02#ibcon#enter sib2, iclass 18, count 2 2006.257.08:24:35.02#ibcon#flushed, iclass 18, count 2 2006.257.08:24:35.02#ibcon#about to write, iclass 18, count 2 2006.257.08:24:35.02#ibcon#wrote, iclass 18, count 2 2006.257.08:24:35.02#ibcon#about to read 3, iclass 18, count 2 2006.257.08:24:35.05#ibcon#read 3, iclass 18, count 2 2006.257.08:24:35.05#ibcon#about to read 4, iclass 18, count 2 2006.257.08:24:35.05#ibcon#read 4, iclass 18, count 2 2006.257.08:24:35.05#ibcon#about to read 5, iclass 18, count 2 2006.257.08:24:35.05#ibcon#read 5, iclass 18, count 2 2006.257.08:24:35.05#ibcon#about to read 6, iclass 18, count 2 2006.257.08:24:35.05#ibcon#read 6, iclass 18, count 2 2006.257.08:24:35.05#ibcon#end of sib2, iclass 18, count 2 2006.257.08:24:35.05#ibcon#*after write, iclass 18, count 2 2006.257.08:24:35.05#ibcon#*before return 0, iclass 18, count 2 2006.257.08:24:35.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:35.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:24:35.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.08:24:35.05#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:35.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:35.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:35.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:35.17#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:24:35.17#ibcon#first serial, iclass 18, count 0 2006.257.08:24:35.17#ibcon#enter sib2, iclass 18, count 0 2006.257.08:24:35.17#ibcon#flushed, iclass 18, count 0 2006.257.08:24:35.17#ibcon#about to write, iclass 18, count 0 2006.257.08:24:35.17#ibcon#wrote, iclass 18, count 0 2006.257.08:24:35.17#ibcon#about to read 3, iclass 18, count 0 2006.257.08:24:35.19#ibcon#read 3, iclass 18, count 0 2006.257.08:24:35.19#ibcon#about to read 4, iclass 18, count 0 2006.257.08:24:35.19#ibcon#read 4, iclass 18, count 0 2006.257.08:24:35.19#ibcon#about to read 5, iclass 18, count 0 2006.257.08:24:35.19#ibcon#read 5, iclass 18, count 0 2006.257.08:24:35.19#ibcon#about to read 6, iclass 18, count 0 2006.257.08:24:35.19#ibcon#read 6, iclass 18, count 0 2006.257.08:24:35.19#ibcon#end of sib2, iclass 18, count 0 2006.257.08:24:35.19#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:24:35.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:24:35.19#ibcon#[27=USB\r\n] 2006.257.08:24:35.19#ibcon#*before write, iclass 18, count 0 2006.257.08:24:35.19#ibcon#enter sib2, iclass 18, count 0 2006.257.08:24:35.19#ibcon#flushed, iclass 18, count 0 2006.257.08:24:35.19#ibcon#about to write, iclass 18, count 0 2006.257.08:24:35.19#ibcon#wrote, iclass 18, count 0 2006.257.08:24:35.19#ibcon#about to read 3, iclass 18, count 0 2006.257.08:24:35.22#ibcon#read 3, iclass 18, count 0 2006.257.08:24:35.22#ibcon#about to read 4, iclass 18, count 0 2006.257.08:24:35.22#ibcon#read 4, iclass 18, count 0 2006.257.08:24:35.22#ibcon#about to read 5, iclass 18, count 0 2006.257.08:24:35.22#ibcon#read 5, iclass 18, count 0 2006.257.08:24:35.22#ibcon#about to read 6, iclass 18, count 0 2006.257.08:24:35.22#ibcon#read 6, iclass 18, count 0 2006.257.08:24:35.22#ibcon#end of sib2, iclass 18, count 0 2006.257.08:24:35.22#ibcon#*after write, iclass 18, count 0 2006.257.08:24:35.22#ibcon#*before return 0, iclass 18, count 0 2006.257.08:24:35.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:35.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:24:35.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:24:35.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:24:35.22$vck44/vblo=5,709.99 2006.257.08:24:35.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.08:24:35.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.08:24:35.22#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:35.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:35.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:35.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:35.22#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:24:35.22#ibcon#first serial, iclass 20, count 0 2006.257.08:24:35.22#ibcon#enter sib2, iclass 20, count 0 2006.257.08:24:35.22#ibcon#flushed, iclass 20, count 0 2006.257.08:24:35.22#ibcon#about to write, iclass 20, count 0 2006.257.08:24:35.22#ibcon#wrote, iclass 20, count 0 2006.257.08:24:35.22#ibcon#about to read 3, iclass 20, count 0 2006.257.08:24:35.24#ibcon#read 3, iclass 20, count 0 2006.257.08:24:35.24#ibcon#about to read 4, iclass 20, count 0 2006.257.08:24:35.24#ibcon#read 4, iclass 20, count 0 2006.257.08:24:35.24#ibcon#about to read 5, iclass 20, count 0 2006.257.08:24:35.24#ibcon#read 5, iclass 20, count 0 2006.257.08:24:35.24#ibcon#about to read 6, iclass 20, count 0 2006.257.08:24:35.24#ibcon#read 6, iclass 20, count 0 2006.257.08:24:35.24#ibcon#end of sib2, iclass 20, count 0 2006.257.08:24:35.24#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:24:35.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:24:35.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:24:35.24#ibcon#*before write, iclass 20, count 0 2006.257.08:24:35.24#ibcon#enter sib2, iclass 20, count 0 2006.257.08:24:35.24#ibcon#flushed, iclass 20, count 0 2006.257.08:24:35.24#ibcon#about to write, iclass 20, count 0 2006.257.08:24:35.24#ibcon#wrote, iclass 20, count 0 2006.257.08:24:35.24#ibcon#about to read 3, iclass 20, count 0 2006.257.08:24:35.28#ibcon#read 3, iclass 20, count 0 2006.257.08:24:35.28#ibcon#about to read 4, iclass 20, count 0 2006.257.08:24:35.28#ibcon#read 4, iclass 20, count 0 2006.257.08:24:35.28#ibcon#about to read 5, iclass 20, count 0 2006.257.08:24:35.28#ibcon#read 5, iclass 20, count 0 2006.257.08:24:35.28#ibcon#about to read 6, iclass 20, count 0 2006.257.08:24:35.28#ibcon#read 6, iclass 20, count 0 2006.257.08:24:35.28#ibcon#end of sib2, iclass 20, count 0 2006.257.08:24:35.28#ibcon#*after write, iclass 20, count 0 2006.257.08:24:35.28#ibcon#*before return 0, iclass 20, count 0 2006.257.08:24:35.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:35.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:24:35.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:24:35.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:24:35.28$vck44/vb=5,4 2006.257.08:24:35.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.08:24:35.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.08:24:35.28#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:35.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:35.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:35.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:35.34#ibcon#enter wrdev, iclass 22, count 2 2006.257.08:24:35.34#ibcon#first serial, iclass 22, count 2 2006.257.08:24:35.34#ibcon#enter sib2, iclass 22, count 2 2006.257.08:24:35.34#ibcon#flushed, iclass 22, count 2 2006.257.08:24:35.34#ibcon#about to write, iclass 22, count 2 2006.257.08:24:35.34#ibcon#wrote, iclass 22, count 2 2006.257.08:24:35.34#ibcon#about to read 3, iclass 22, count 2 2006.257.08:24:35.36#ibcon#read 3, iclass 22, count 2 2006.257.08:24:35.36#ibcon#about to read 4, iclass 22, count 2 2006.257.08:24:35.36#ibcon#read 4, iclass 22, count 2 2006.257.08:24:35.36#ibcon#about to read 5, iclass 22, count 2 2006.257.08:24:35.36#ibcon#read 5, iclass 22, count 2 2006.257.08:24:35.36#ibcon#about to read 6, iclass 22, count 2 2006.257.08:24:35.36#ibcon#read 6, iclass 22, count 2 2006.257.08:24:35.36#ibcon#end of sib2, iclass 22, count 2 2006.257.08:24:35.36#ibcon#*mode == 0, iclass 22, count 2 2006.257.08:24:35.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.08:24:35.36#ibcon#[27=AT05-04\r\n] 2006.257.08:24:35.36#ibcon#*before write, iclass 22, count 2 2006.257.08:24:35.36#ibcon#enter sib2, iclass 22, count 2 2006.257.08:24:35.36#ibcon#flushed, iclass 22, count 2 2006.257.08:24:35.36#ibcon#about to write, iclass 22, count 2 2006.257.08:24:35.36#ibcon#wrote, iclass 22, count 2 2006.257.08:24:35.36#ibcon#about to read 3, iclass 22, count 2 2006.257.08:24:35.39#ibcon#read 3, iclass 22, count 2 2006.257.08:24:35.39#ibcon#about to read 4, iclass 22, count 2 2006.257.08:24:35.39#ibcon#read 4, iclass 22, count 2 2006.257.08:24:35.39#ibcon#about to read 5, iclass 22, count 2 2006.257.08:24:35.39#ibcon#read 5, iclass 22, count 2 2006.257.08:24:35.39#ibcon#about to read 6, iclass 22, count 2 2006.257.08:24:35.39#ibcon#read 6, iclass 22, count 2 2006.257.08:24:35.39#ibcon#end of sib2, iclass 22, count 2 2006.257.08:24:35.39#ibcon#*after write, iclass 22, count 2 2006.257.08:24:35.39#ibcon#*before return 0, iclass 22, count 2 2006.257.08:24:35.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:35.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:24:35.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.08:24:35.39#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:35.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:35.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:35.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:35.51#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:24:35.51#ibcon#first serial, iclass 22, count 0 2006.257.08:24:35.51#ibcon#enter sib2, iclass 22, count 0 2006.257.08:24:35.51#ibcon#flushed, iclass 22, count 0 2006.257.08:24:35.51#ibcon#about to write, iclass 22, count 0 2006.257.08:24:35.51#ibcon#wrote, iclass 22, count 0 2006.257.08:24:35.51#ibcon#about to read 3, iclass 22, count 0 2006.257.08:24:35.53#ibcon#read 3, iclass 22, count 0 2006.257.08:24:35.53#ibcon#about to read 4, iclass 22, count 0 2006.257.08:24:35.53#ibcon#read 4, iclass 22, count 0 2006.257.08:24:35.53#ibcon#about to read 5, iclass 22, count 0 2006.257.08:24:35.53#ibcon#read 5, iclass 22, count 0 2006.257.08:24:35.53#ibcon#about to read 6, iclass 22, count 0 2006.257.08:24:35.53#ibcon#read 6, iclass 22, count 0 2006.257.08:24:35.53#ibcon#end of sib2, iclass 22, count 0 2006.257.08:24:35.53#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:24:35.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:24:35.53#ibcon#[27=USB\r\n] 2006.257.08:24:35.53#ibcon#*before write, iclass 22, count 0 2006.257.08:24:35.53#ibcon#enter sib2, iclass 22, count 0 2006.257.08:24:35.53#ibcon#flushed, iclass 22, count 0 2006.257.08:24:35.53#ibcon#about to write, iclass 22, count 0 2006.257.08:24:35.53#ibcon#wrote, iclass 22, count 0 2006.257.08:24:35.53#ibcon#about to read 3, iclass 22, count 0 2006.257.08:24:35.56#ibcon#read 3, iclass 22, count 0 2006.257.08:24:35.56#ibcon#about to read 4, iclass 22, count 0 2006.257.08:24:35.56#ibcon#read 4, iclass 22, count 0 2006.257.08:24:35.56#ibcon#about to read 5, iclass 22, count 0 2006.257.08:24:35.56#ibcon#read 5, iclass 22, count 0 2006.257.08:24:35.56#ibcon#about to read 6, iclass 22, count 0 2006.257.08:24:35.56#ibcon#read 6, iclass 22, count 0 2006.257.08:24:35.56#ibcon#end of sib2, iclass 22, count 0 2006.257.08:24:35.56#ibcon#*after write, iclass 22, count 0 2006.257.08:24:35.56#ibcon#*before return 0, iclass 22, count 0 2006.257.08:24:35.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:35.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:24:35.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:24:35.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:24:35.56$vck44/vblo=6,719.99 2006.257.08:24:35.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.08:24:35.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.08:24:35.56#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:35.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:35.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:35.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:35.56#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:24:35.56#ibcon#first serial, iclass 24, count 0 2006.257.08:24:35.56#ibcon#enter sib2, iclass 24, count 0 2006.257.08:24:35.56#ibcon#flushed, iclass 24, count 0 2006.257.08:24:35.56#ibcon#about to write, iclass 24, count 0 2006.257.08:24:35.56#ibcon#wrote, iclass 24, count 0 2006.257.08:24:35.56#ibcon#about to read 3, iclass 24, count 0 2006.257.08:24:35.58#ibcon#read 3, iclass 24, count 0 2006.257.08:24:35.58#ibcon#about to read 4, iclass 24, count 0 2006.257.08:24:35.58#ibcon#read 4, iclass 24, count 0 2006.257.08:24:35.58#ibcon#about to read 5, iclass 24, count 0 2006.257.08:24:35.58#ibcon#read 5, iclass 24, count 0 2006.257.08:24:35.58#ibcon#about to read 6, iclass 24, count 0 2006.257.08:24:35.58#ibcon#read 6, iclass 24, count 0 2006.257.08:24:35.58#ibcon#end of sib2, iclass 24, count 0 2006.257.08:24:35.58#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:24:35.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:24:35.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:24:35.58#ibcon#*before write, iclass 24, count 0 2006.257.08:24:35.58#ibcon#enter sib2, iclass 24, count 0 2006.257.08:24:35.58#ibcon#flushed, iclass 24, count 0 2006.257.08:24:35.58#ibcon#about to write, iclass 24, count 0 2006.257.08:24:35.58#ibcon#wrote, iclass 24, count 0 2006.257.08:24:35.58#ibcon#about to read 3, iclass 24, count 0 2006.257.08:24:35.62#ibcon#read 3, iclass 24, count 0 2006.257.08:24:35.62#ibcon#about to read 4, iclass 24, count 0 2006.257.08:24:35.62#ibcon#read 4, iclass 24, count 0 2006.257.08:24:35.62#ibcon#about to read 5, iclass 24, count 0 2006.257.08:24:35.62#ibcon#read 5, iclass 24, count 0 2006.257.08:24:35.62#ibcon#about to read 6, iclass 24, count 0 2006.257.08:24:35.62#ibcon#read 6, iclass 24, count 0 2006.257.08:24:35.62#ibcon#end of sib2, iclass 24, count 0 2006.257.08:24:35.62#ibcon#*after write, iclass 24, count 0 2006.257.08:24:35.62#ibcon#*before return 0, iclass 24, count 0 2006.257.08:24:35.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:35.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:24:35.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:24:35.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:24:35.62$vck44/vb=6,4 2006.257.08:24:35.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.08:24:35.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.08:24:35.62#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:35.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:35.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:35.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:35.68#ibcon#enter wrdev, iclass 26, count 2 2006.257.08:24:35.68#ibcon#first serial, iclass 26, count 2 2006.257.08:24:35.68#ibcon#enter sib2, iclass 26, count 2 2006.257.08:24:35.68#ibcon#flushed, iclass 26, count 2 2006.257.08:24:35.68#ibcon#about to write, iclass 26, count 2 2006.257.08:24:35.68#ibcon#wrote, iclass 26, count 2 2006.257.08:24:35.68#ibcon#about to read 3, iclass 26, count 2 2006.257.08:24:35.70#ibcon#read 3, iclass 26, count 2 2006.257.08:24:35.70#ibcon#about to read 4, iclass 26, count 2 2006.257.08:24:35.70#ibcon#read 4, iclass 26, count 2 2006.257.08:24:35.70#ibcon#about to read 5, iclass 26, count 2 2006.257.08:24:35.70#ibcon#read 5, iclass 26, count 2 2006.257.08:24:35.70#ibcon#about to read 6, iclass 26, count 2 2006.257.08:24:35.70#ibcon#read 6, iclass 26, count 2 2006.257.08:24:35.70#ibcon#end of sib2, iclass 26, count 2 2006.257.08:24:35.70#ibcon#*mode == 0, iclass 26, count 2 2006.257.08:24:35.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.08:24:35.70#ibcon#[27=AT06-04\r\n] 2006.257.08:24:35.70#ibcon#*before write, iclass 26, count 2 2006.257.08:24:35.70#ibcon#enter sib2, iclass 26, count 2 2006.257.08:24:35.70#ibcon#flushed, iclass 26, count 2 2006.257.08:24:35.70#ibcon#about to write, iclass 26, count 2 2006.257.08:24:35.70#ibcon#wrote, iclass 26, count 2 2006.257.08:24:35.70#ibcon#about to read 3, iclass 26, count 2 2006.257.08:24:35.73#ibcon#read 3, iclass 26, count 2 2006.257.08:24:35.73#ibcon#about to read 4, iclass 26, count 2 2006.257.08:24:35.73#ibcon#read 4, iclass 26, count 2 2006.257.08:24:35.73#ibcon#about to read 5, iclass 26, count 2 2006.257.08:24:35.73#ibcon#read 5, iclass 26, count 2 2006.257.08:24:35.73#ibcon#about to read 6, iclass 26, count 2 2006.257.08:24:35.73#ibcon#read 6, iclass 26, count 2 2006.257.08:24:35.73#ibcon#end of sib2, iclass 26, count 2 2006.257.08:24:35.73#ibcon#*after write, iclass 26, count 2 2006.257.08:24:35.73#ibcon#*before return 0, iclass 26, count 2 2006.257.08:24:35.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:35.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:24:35.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.08:24:35.73#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:35.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:35.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:35.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:35.85#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:24:35.85#ibcon#first serial, iclass 26, count 0 2006.257.08:24:35.85#ibcon#enter sib2, iclass 26, count 0 2006.257.08:24:35.85#ibcon#flushed, iclass 26, count 0 2006.257.08:24:35.85#ibcon#about to write, iclass 26, count 0 2006.257.08:24:35.85#ibcon#wrote, iclass 26, count 0 2006.257.08:24:35.85#ibcon#about to read 3, iclass 26, count 0 2006.257.08:24:35.87#ibcon#read 3, iclass 26, count 0 2006.257.08:24:35.87#ibcon#about to read 4, iclass 26, count 0 2006.257.08:24:35.87#ibcon#read 4, iclass 26, count 0 2006.257.08:24:35.87#ibcon#about to read 5, iclass 26, count 0 2006.257.08:24:35.87#ibcon#read 5, iclass 26, count 0 2006.257.08:24:35.87#ibcon#about to read 6, iclass 26, count 0 2006.257.08:24:35.87#ibcon#read 6, iclass 26, count 0 2006.257.08:24:35.87#ibcon#end of sib2, iclass 26, count 0 2006.257.08:24:35.87#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:24:35.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:24:35.87#ibcon#[27=USB\r\n] 2006.257.08:24:35.87#ibcon#*before write, iclass 26, count 0 2006.257.08:24:35.87#ibcon#enter sib2, iclass 26, count 0 2006.257.08:24:35.87#ibcon#flushed, iclass 26, count 0 2006.257.08:24:35.87#ibcon#about to write, iclass 26, count 0 2006.257.08:24:35.87#ibcon#wrote, iclass 26, count 0 2006.257.08:24:35.87#ibcon#about to read 3, iclass 26, count 0 2006.257.08:24:35.90#ibcon#read 3, iclass 26, count 0 2006.257.08:24:35.90#ibcon#about to read 4, iclass 26, count 0 2006.257.08:24:35.90#ibcon#read 4, iclass 26, count 0 2006.257.08:24:35.90#ibcon#about to read 5, iclass 26, count 0 2006.257.08:24:35.90#ibcon#read 5, iclass 26, count 0 2006.257.08:24:35.90#ibcon#about to read 6, iclass 26, count 0 2006.257.08:24:35.90#ibcon#read 6, iclass 26, count 0 2006.257.08:24:35.90#ibcon#end of sib2, iclass 26, count 0 2006.257.08:24:35.90#ibcon#*after write, iclass 26, count 0 2006.257.08:24:35.90#ibcon#*before return 0, iclass 26, count 0 2006.257.08:24:35.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:35.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:24:35.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:24:35.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:24:35.90$vck44/vblo=7,734.99 2006.257.08:24:35.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.08:24:35.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.08:24:35.90#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:35.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:35.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:35.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:35.90#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:24:35.90#ibcon#first serial, iclass 28, count 0 2006.257.08:24:35.90#ibcon#enter sib2, iclass 28, count 0 2006.257.08:24:35.90#ibcon#flushed, iclass 28, count 0 2006.257.08:24:35.90#ibcon#about to write, iclass 28, count 0 2006.257.08:24:35.90#ibcon#wrote, iclass 28, count 0 2006.257.08:24:35.90#ibcon#about to read 3, iclass 28, count 0 2006.257.08:24:35.92#ibcon#read 3, iclass 28, count 0 2006.257.08:24:35.92#ibcon#about to read 4, iclass 28, count 0 2006.257.08:24:35.92#ibcon#read 4, iclass 28, count 0 2006.257.08:24:35.92#ibcon#about to read 5, iclass 28, count 0 2006.257.08:24:35.92#ibcon#read 5, iclass 28, count 0 2006.257.08:24:35.92#ibcon#about to read 6, iclass 28, count 0 2006.257.08:24:35.92#ibcon#read 6, iclass 28, count 0 2006.257.08:24:35.92#ibcon#end of sib2, iclass 28, count 0 2006.257.08:24:35.92#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:24:35.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:24:35.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:24:35.92#ibcon#*before write, iclass 28, count 0 2006.257.08:24:35.92#ibcon#enter sib2, iclass 28, count 0 2006.257.08:24:35.92#ibcon#flushed, iclass 28, count 0 2006.257.08:24:35.92#ibcon#about to write, iclass 28, count 0 2006.257.08:24:35.92#ibcon#wrote, iclass 28, count 0 2006.257.08:24:35.92#ibcon#about to read 3, iclass 28, count 0 2006.257.08:24:35.96#ibcon#read 3, iclass 28, count 0 2006.257.08:24:35.96#ibcon#about to read 4, iclass 28, count 0 2006.257.08:24:35.96#ibcon#read 4, iclass 28, count 0 2006.257.08:24:35.96#ibcon#about to read 5, iclass 28, count 0 2006.257.08:24:35.96#ibcon#read 5, iclass 28, count 0 2006.257.08:24:35.96#ibcon#about to read 6, iclass 28, count 0 2006.257.08:24:35.96#ibcon#read 6, iclass 28, count 0 2006.257.08:24:35.96#ibcon#end of sib2, iclass 28, count 0 2006.257.08:24:35.96#ibcon#*after write, iclass 28, count 0 2006.257.08:24:35.96#ibcon#*before return 0, iclass 28, count 0 2006.257.08:24:35.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:35.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:24:35.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:24:35.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:24:35.96$vck44/vb=7,4 2006.257.08:24:35.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.08:24:35.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.08:24:35.96#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:35.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:36.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:36.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:36.02#ibcon#enter wrdev, iclass 30, count 2 2006.257.08:24:36.02#ibcon#first serial, iclass 30, count 2 2006.257.08:24:36.02#ibcon#enter sib2, iclass 30, count 2 2006.257.08:24:36.02#ibcon#flushed, iclass 30, count 2 2006.257.08:24:36.02#ibcon#about to write, iclass 30, count 2 2006.257.08:24:36.02#ibcon#wrote, iclass 30, count 2 2006.257.08:24:36.02#ibcon#about to read 3, iclass 30, count 2 2006.257.08:24:36.04#ibcon#read 3, iclass 30, count 2 2006.257.08:24:36.04#ibcon#about to read 4, iclass 30, count 2 2006.257.08:24:36.04#ibcon#read 4, iclass 30, count 2 2006.257.08:24:36.04#ibcon#about to read 5, iclass 30, count 2 2006.257.08:24:36.04#ibcon#read 5, iclass 30, count 2 2006.257.08:24:36.04#ibcon#about to read 6, iclass 30, count 2 2006.257.08:24:36.04#ibcon#read 6, iclass 30, count 2 2006.257.08:24:36.04#ibcon#end of sib2, iclass 30, count 2 2006.257.08:24:36.04#ibcon#*mode == 0, iclass 30, count 2 2006.257.08:24:36.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.08:24:36.04#ibcon#[27=AT07-04\r\n] 2006.257.08:24:36.04#ibcon#*before write, iclass 30, count 2 2006.257.08:24:36.04#ibcon#enter sib2, iclass 30, count 2 2006.257.08:24:36.04#ibcon#flushed, iclass 30, count 2 2006.257.08:24:36.04#ibcon#about to write, iclass 30, count 2 2006.257.08:24:36.04#ibcon#wrote, iclass 30, count 2 2006.257.08:24:36.04#ibcon#about to read 3, iclass 30, count 2 2006.257.08:24:36.07#ibcon#read 3, iclass 30, count 2 2006.257.08:24:36.07#ibcon#about to read 4, iclass 30, count 2 2006.257.08:24:36.07#ibcon#read 4, iclass 30, count 2 2006.257.08:24:36.07#ibcon#about to read 5, iclass 30, count 2 2006.257.08:24:36.07#ibcon#read 5, iclass 30, count 2 2006.257.08:24:36.07#ibcon#about to read 6, iclass 30, count 2 2006.257.08:24:36.07#ibcon#read 6, iclass 30, count 2 2006.257.08:24:36.07#ibcon#end of sib2, iclass 30, count 2 2006.257.08:24:36.07#ibcon#*after write, iclass 30, count 2 2006.257.08:24:36.07#ibcon#*before return 0, iclass 30, count 2 2006.257.08:24:36.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:36.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:24:36.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.08:24:36.07#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:36.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:36.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:36.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:36.19#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:24:36.19#ibcon#first serial, iclass 30, count 0 2006.257.08:24:36.19#ibcon#enter sib2, iclass 30, count 0 2006.257.08:24:36.19#ibcon#flushed, iclass 30, count 0 2006.257.08:24:36.19#ibcon#about to write, iclass 30, count 0 2006.257.08:24:36.19#ibcon#wrote, iclass 30, count 0 2006.257.08:24:36.19#ibcon#about to read 3, iclass 30, count 0 2006.257.08:24:36.21#ibcon#read 3, iclass 30, count 0 2006.257.08:24:36.21#ibcon#about to read 4, iclass 30, count 0 2006.257.08:24:36.21#ibcon#read 4, iclass 30, count 0 2006.257.08:24:36.21#ibcon#about to read 5, iclass 30, count 0 2006.257.08:24:36.21#ibcon#read 5, iclass 30, count 0 2006.257.08:24:36.21#ibcon#about to read 6, iclass 30, count 0 2006.257.08:24:36.21#ibcon#read 6, iclass 30, count 0 2006.257.08:24:36.21#ibcon#end of sib2, iclass 30, count 0 2006.257.08:24:36.21#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:24:36.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:24:36.21#ibcon#[27=USB\r\n] 2006.257.08:24:36.21#ibcon#*before write, iclass 30, count 0 2006.257.08:24:36.21#ibcon#enter sib2, iclass 30, count 0 2006.257.08:24:36.21#ibcon#flushed, iclass 30, count 0 2006.257.08:24:36.21#ibcon#about to write, iclass 30, count 0 2006.257.08:24:36.21#ibcon#wrote, iclass 30, count 0 2006.257.08:24:36.21#ibcon#about to read 3, iclass 30, count 0 2006.257.08:24:36.24#ibcon#read 3, iclass 30, count 0 2006.257.08:24:36.24#ibcon#about to read 4, iclass 30, count 0 2006.257.08:24:36.24#ibcon#read 4, iclass 30, count 0 2006.257.08:24:36.24#ibcon#about to read 5, iclass 30, count 0 2006.257.08:24:36.24#ibcon#read 5, iclass 30, count 0 2006.257.08:24:36.24#ibcon#about to read 6, iclass 30, count 0 2006.257.08:24:36.24#ibcon#read 6, iclass 30, count 0 2006.257.08:24:36.24#ibcon#end of sib2, iclass 30, count 0 2006.257.08:24:36.24#ibcon#*after write, iclass 30, count 0 2006.257.08:24:36.24#ibcon#*before return 0, iclass 30, count 0 2006.257.08:24:36.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:36.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:24:36.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:24:36.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:24:36.24$vck44/vblo=8,744.99 2006.257.08:24:36.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.08:24:36.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.08:24:36.24#ibcon#ireg 17 cls_cnt 0 2006.257.08:24:36.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:36.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:36.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:36.24#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:24:36.24#ibcon#first serial, iclass 32, count 0 2006.257.08:24:36.24#ibcon#enter sib2, iclass 32, count 0 2006.257.08:24:36.24#ibcon#flushed, iclass 32, count 0 2006.257.08:24:36.24#ibcon#about to write, iclass 32, count 0 2006.257.08:24:36.24#ibcon#wrote, iclass 32, count 0 2006.257.08:24:36.24#ibcon#about to read 3, iclass 32, count 0 2006.257.08:24:36.26#ibcon#read 3, iclass 32, count 0 2006.257.08:24:36.26#ibcon#about to read 4, iclass 32, count 0 2006.257.08:24:36.26#ibcon#read 4, iclass 32, count 0 2006.257.08:24:36.26#ibcon#about to read 5, iclass 32, count 0 2006.257.08:24:36.26#ibcon#read 5, iclass 32, count 0 2006.257.08:24:36.26#ibcon#about to read 6, iclass 32, count 0 2006.257.08:24:36.26#ibcon#read 6, iclass 32, count 0 2006.257.08:24:36.26#ibcon#end of sib2, iclass 32, count 0 2006.257.08:24:36.26#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:24:36.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:24:36.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:24:36.26#ibcon#*before write, iclass 32, count 0 2006.257.08:24:36.26#ibcon#enter sib2, iclass 32, count 0 2006.257.08:24:36.26#ibcon#flushed, iclass 32, count 0 2006.257.08:24:36.26#ibcon#about to write, iclass 32, count 0 2006.257.08:24:36.26#ibcon#wrote, iclass 32, count 0 2006.257.08:24:36.26#ibcon#about to read 3, iclass 32, count 0 2006.257.08:24:36.30#ibcon#read 3, iclass 32, count 0 2006.257.08:24:36.30#ibcon#about to read 4, iclass 32, count 0 2006.257.08:24:36.30#ibcon#read 4, iclass 32, count 0 2006.257.08:24:36.30#ibcon#about to read 5, iclass 32, count 0 2006.257.08:24:36.30#ibcon#read 5, iclass 32, count 0 2006.257.08:24:36.30#ibcon#about to read 6, iclass 32, count 0 2006.257.08:24:36.30#ibcon#read 6, iclass 32, count 0 2006.257.08:24:36.30#ibcon#end of sib2, iclass 32, count 0 2006.257.08:24:36.30#ibcon#*after write, iclass 32, count 0 2006.257.08:24:36.30#ibcon#*before return 0, iclass 32, count 0 2006.257.08:24:36.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:36.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:24:36.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:24:36.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:24:36.30$vck44/vb=8,4 2006.257.08:24:36.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.08:24:36.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.08:24:36.30#ibcon#ireg 11 cls_cnt 2 2006.257.08:24:36.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:36.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:36.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:36.36#ibcon#enter wrdev, iclass 34, count 2 2006.257.08:24:36.36#ibcon#first serial, iclass 34, count 2 2006.257.08:24:36.36#ibcon#enter sib2, iclass 34, count 2 2006.257.08:24:36.36#ibcon#flushed, iclass 34, count 2 2006.257.08:24:36.36#ibcon#about to write, iclass 34, count 2 2006.257.08:24:36.36#ibcon#wrote, iclass 34, count 2 2006.257.08:24:36.36#ibcon#about to read 3, iclass 34, count 2 2006.257.08:24:36.38#ibcon#read 3, iclass 34, count 2 2006.257.08:24:36.38#ibcon#about to read 4, iclass 34, count 2 2006.257.08:24:36.38#ibcon#read 4, iclass 34, count 2 2006.257.08:24:36.38#ibcon#about to read 5, iclass 34, count 2 2006.257.08:24:36.38#ibcon#read 5, iclass 34, count 2 2006.257.08:24:36.38#ibcon#about to read 6, iclass 34, count 2 2006.257.08:24:36.38#ibcon#read 6, iclass 34, count 2 2006.257.08:24:36.38#ibcon#end of sib2, iclass 34, count 2 2006.257.08:24:36.38#ibcon#*mode == 0, iclass 34, count 2 2006.257.08:24:36.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.08:24:36.38#ibcon#[27=AT08-04\r\n] 2006.257.08:24:36.38#ibcon#*before write, iclass 34, count 2 2006.257.08:24:36.38#ibcon#enter sib2, iclass 34, count 2 2006.257.08:24:36.38#ibcon#flushed, iclass 34, count 2 2006.257.08:24:36.38#ibcon#about to write, iclass 34, count 2 2006.257.08:24:36.38#ibcon#wrote, iclass 34, count 2 2006.257.08:24:36.38#ibcon#about to read 3, iclass 34, count 2 2006.257.08:24:36.41#ibcon#read 3, iclass 34, count 2 2006.257.08:24:36.41#ibcon#about to read 4, iclass 34, count 2 2006.257.08:24:36.41#ibcon#read 4, iclass 34, count 2 2006.257.08:24:36.41#ibcon#about to read 5, iclass 34, count 2 2006.257.08:24:36.41#ibcon#read 5, iclass 34, count 2 2006.257.08:24:36.41#ibcon#about to read 6, iclass 34, count 2 2006.257.08:24:36.41#ibcon#read 6, iclass 34, count 2 2006.257.08:24:36.41#ibcon#end of sib2, iclass 34, count 2 2006.257.08:24:36.41#ibcon#*after write, iclass 34, count 2 2006.257.08:24:36.41#ibcon#*before return 0, iclass 34, count 2 2006.257.08:24:36.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:36.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:24:36.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.08:24:36.41#ibcon#ireg 7 cls_cnt 0 2006.257.08:24:36.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:36.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:36.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:36.53#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:24:36.53#ibcon#first serial, iclass 34, count 0 2006.257.08:24:36.53#ibcon#enter sib2, iclass 34, count 0 2006.257.08:24:36.53#ibcon#flushed, iclass 34, count 0 2006.257.08:24:36.53#ibcon#about to write, iclass 34, count 0 2006.257.08:24:36.53#ibcon#wrote, iclass 34, count 0 2006.257.08:24:36.53#ibcon#about to read 3, iclass 34, count 0 2006.257.08:24:36.55#ibcon#read 3, iclass 34, count 0 2006.257.08:24:36.55#ibcon#about to read 4, iclass 34, count 0 2006.257.08:24:36.55#ibcon#read 4, iclass 34, count 0 2006.257.08:24:36.55#ibcon#about to read 5, iclass 34, count 0 2006.257.08:24:36.55#ibcon#read 5, iclass 34, count 0 2006.257.08:24:36.55#ibcon#about to read 6, iclass 34, count 0 2006.257.08:24:36.55#ibcon#read 6, iclass 34, count 0 2006.257.08:24:36.55#ibcon#end of sib2, iclass 34, count 0 2006.257.08:24:36.55#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:24:36.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:24:36.55#ibcon#[27=USB\r\n] 2006.257.08:24:36.55#ibcon#*before write, iclass 34, count 0 2006.257.08:24:36.55#ibcon#enter sib2, iclass 34, count 0 2006.257.08:24:36.55#ibcon#flushed, iclass 34, count 0 2006.257.08:24:36.55#ibcon#about to write, iclass 34, count 0 2006.257.08:24:36.55#ibcon#wrote, iclass 34, count 0 2006.257.08:24:36.55#ibcon#about to read 3, iclass 34, count 0 2006.257.08:24:36.58#ibcon#read 3, iclass 34, count 0 2006.257.08:24:36.58#ibcon#about to read 4, iclass 34, count 0 2006.257.08:24:36.58#ibcon#read 4, iclass 34, count 0 2006.257.08:24:36.58#ibcon#about to read 5, iclass 34, count 0 2006.257.08:24:36.58#ibcon#read 5, iclass 34, count 0 2006.257.08:24:36.58#ibcon#about to read 6, iclass 34, count 0 2006.257.08:24:36.58#ibcon#read 6, iclass 34, count 0 2006.257.08:24:36.58#ibcon#end of sib2, iclass 34, count 0 2006.257.08:24:36.58#ibcon#*after write, iclass 34, count 0 2006.257.08:24:36.58#ibcon#*before return 0, iclass 34, count 0 2006.257.08:24:36.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:36.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:24:36.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:24:36.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:24:36.58$vck44/vabw=wide 2006.257.08:24:36.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.08:24:36.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.08:24:36.58#ibcon#ireg 8 cls_cnt 0 2006.257.08:24:36.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:36.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:36.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:36.58#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:24:36.58#ibcon#first serial, iclass 36, count 0 2006.257.08:24:36.58#ibcon#enter sib2, iclass 36, count 0 2006.257.08:24:36.58#ibcon#flushed, iclass 36, count 0 2006.257.08:24:36.58#ibcon#about to write, iclass 36, count 0 2006.257.08:24:36.58#ibcon#wrote, iclass 36, count 0 2006.257.08:24:36.58#ibcon#about to read 3, iclass 36, count 0 2006.257.08:24:36.60#ibcon#read 3, iclass 36, count 0 2006.257.08:24:36.60#ibcon#about to read 4, iclass 36, count 0 2006.257.08:24:36.60#ibcon#read 4, iclass 36, count 0 2006.257.08:24:36.60#ibcon#about to read 5, iclass 36, count 0 2006.257.08:24:36.60#ibcon#read 5, iclass 36, count 0 2006.257.08:24:36.60#ibcon#about to read 6, iclass 36, count 0 2006.257.08:24:36.60#ibcon#read 6, iclass 36, count 0 2006.257.08:24:36.60#ibcon#end of sib2, iclass 36, count 0 2006.257.08:24:36.60#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:24:36.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:24:36.60#ibcon#[25=BW32\r\n] 2006.257.08:24:36.60#ibcon#*before write, iclass 36, count 0 2006.257.08:24:36.60#ibcon#enter sib2, iclass 36, count 0 2006.257.08:24:36.60#ibcon#flushed, iclass 36, count 0 2006.257.08:24:36.60#ibcon#about to write, iclass 36, count 0 2006.257.08:24:36.60#ibcon#wrote, iclass 36, count 0 2006.257.08:24:36.60#ibcon#about to read 3, iclass 36, count 0 2006.257.08:24:36.63#ibcon#read 3, iclass 36, count 0 2006.257.08:24:36.63#ibcon#about to read 4, iclass 36, count 0 2006.257.08:24:36.63#ibcon#read 4, iclass 36, count 0 2006.257.08:24:36.63#ibcon#about to read 5, iclass 36, count 0 2006.257.08:24:36.63#ibcon#read 5, iclass 36, count 0 2006.257.08:24:36.63#ibcon#about to read 6, iclass 36, count 0 2006.257.08:24:36.63#ibcon#read 6, iclass 36, count 0 2006.257.08:24:36.63#ibcon#end of sib2, iclass 36, count 0 2006.257.08:24:36.63#ibcon#*after write, iclass 36, count 0 2006.257.08:24:36.63#ibcon#*before return 0, iclass 36, count 0 2006.257.08:24:36.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:36.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:24:36.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:24:36.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:24:36.63$vck44/vbbw=wide 2006.257.08:24:36.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.08:24:36.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.08:24:36.63#ibcon#ireg 8 cls_cnt 0 2006.257.08:24:36.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:24:36.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:24:36.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:24:36.70#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:24:36.70#ibcon#first serial, iclass 38, count 0 2006.257.08:24:36.70#ibcon#enter sib2, iclass 38, count 0 2006.257.08:24:36.70#ibcon#flushed, iclass 38, count 0 2006.257.08:24:36.70#ibcon#about to write, iclass 38, count 0 2006.257.08:24:36.70#ibcon#wrote, iclass 38, count 0 2006.257.08:24:36.70#ibcon#about to read 3, iclass 38, count 0 2006.257.08:24:36.72#ibcon#read 3, iclass 38, count 0 2006.257.08:24:36.72#ibcon#about to read 4, iclass 38, count 0 2006.257.08:24:36.72#ibcon#read 4, iclass 38, count 0 2006.257.08:24:36.72#ibcon#about to read 5, iclass 38, count 0 2006.257.08:24:36.72#ibcon#read 5, iclass 38, count 0 2006.257.08:24:36.72#ibcon#about to read 6, iclass 38, count 0 2006.257.08:24:36.72#ibcon#read 6, iclass 38, count 0 2006.257.08:24:36.72#ibcon#end of sib2, iclass 38, count 0 2006.257.08:24:36.72#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:24:36.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:24:36.72#ibcon#[27=BW32\r\n] 2006.257.08:24:36.72#ibcon#*before write, iclass 38, count 0 2006.257.08:24:36.72#ibcon#enter sib2, iclass 38, count 0 2006.257.08:24:36.72#ibcon#flushed, iclass 38, count 0 2006.257.08:24:36.72#ibcon#about to write, iclass 38, count 0 2006.257.08:24:36.72#ibcon#wrote, iclass 38, count 0 2006.257.08:24:36.72#ibcon#about to read 3, iclass 38, count 0 2006.257.08:24:36.75#ibcon#read 3, iclass 38, count 0 2006.257.08:24:36.75#ibcon#about to read 4, iclass 38, count 0 2006.257.08:24:36.75#ibcon#read 4, iclass 38, count 0 2006.257.08:24:36.75#ibcon#about to read 5, iclass 38, count 0 2006.257.08:24:36.75#ibcon#read 5, iclass 38, count 0 2006.257.08:24:36.75#ibcon#about to read 6, iclass 38, count 0 2006.257.08:24:36.75#ibcon#read 6, iclass 38, count 0 2006.257.08:24:36.75#ibcon#end of sib2, iclass 38, count 0 2006.257.08:24:36.75#ibcon#*after write, iclass 38, count 0 2006.257.08:24:36.75#ibcon#*before return 0, iclass 38, count 0 2006.257.08:24:36.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:24:36.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:24:36.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:24:36.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:24:36.75$setupk4/ifdk4 2006.257.08:24:36.75$ifdk4/lo= 2006.257.08:24:36.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:24:36.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:24:36.75$ifdk4/patch= 2006.257.08:24:36.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:24:36.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:24:36.75$setupk4/!*+20s 2006.257.08:24:39.91#abcon#<5=/15 1.4 3.9 20.74 901013.0\r\n> 2006.257.08:24:39.93#abcon#{5=INTERFACE CLEAR} 2006.257.08:24:39.99#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:24:50.08#abcon#<5=/15 1.4 3.9 20.74 901012.9\r\n> 2006.257.08:24:50.10#abcon#{5=INTERFACE CLEAR} 2006.257.08:24:50.16#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:24:51.26$setupk4/"tpicd 2006.257.08:24:51.26$setupk4/echo=off 2006.257.08:24:51.26$setupk4/xlog=off 2006.257.08:24:51.26:!2006.257.08:27:49 2006.257.08:25:03.13#trakl#Source acquired 2006.257.08:25:05.13#flagr#flagr/antenna,acquired 2006.257.08:27:49.02:preob 2006.257.08:27:50.15/onsource/TRACKING 2006.257.08:27:50.15:!2006.257.08:27:59 2006.257.08:27:59.02:"tape 2006.257.08:27:59.02:"st=record 2006.257.08:27:59.02:data_valid=on 2006.257.08:27:59.02:midob 2006.257.08:28:00.15/onsource/TRACKING 2006.257.08:28:00.15/wx/20.71,1012.8,90 2006.257.08:28:00.20/cable/+6.4757E-03 2006.257.08:28:01.29/va/01,08,usb,yes,32,34 2006.257.08:28:01.29/va/02,07,usb,yes,34,35 2006.257.08:28:01.29/va/03,08,usb,yes,31,33 2006.257.08:28:01.29/va/04,07,usb,yes,35,37 2006.257.08:28:01.29/va/05,04,usb,yes,32,32 2006.257.08:28:01.29/va/06,04,usb,yes,35,35 2006.257.08:28:01.29/va/07,04,usb,yes,36,37 2006.257.08:28:01.29/va/08,04,usb,yes,30,37 2006.257.08:28:01.52/valo/01,524.99,yes,locked 2006.257.08:28:01.52/valo/02,534.99,yes,locked 2006.257.08:28:01.52/valo/03,564.99,yes,locked 2006.257.08:28:01.52/valo/04,624.99,yes,locked 2006.257.08:28:01.52/valo/05,734.99,yes,locked 2006.257.08:28:01.52/valo/06,814.99,yes,locked 2006.257.08:28:01.52/valo/07,864.99,yes,locked 2006.257.08:28:01.52/valo/08,884.99,yes,locked 2006.257.08:28:02.61/vb/01,04,usb,yes,31,29 2006.257.08:28:02.61/vb/02,05,usb,yes,29,29 2006.257.08:28:02.61/vb/03,04,usb,yes,30,33 2006.257.08:28:02.61/vb/04,05,usb,yes,30,29 2006.257.08:28:02.61/vb/05,04,usb,yes,27,29 2006.257.08:28:02.61/vb/06,04,usb,yes,31,28 2006.257.08:28:02.61/vb/07,04,usb,yes,31,31 2006.257.08:28:02.61/vb/08,04,usb,yes,29,32 2006.257.08:28:02.85/vblo/01,629.99,yes,locked 2006.257.08:28:02.85/vblo/02,634.99,yes,locked 2006.257.08:28:02.85/vblo/03,649.99,yes,locked 2006.257.08:28:02.85/vblo/04,679.99,yes,locked 2006.257.08:28:02.85/vblo/05,709.99,yes,locked 2006.257.08:28:02.85/vblo/06,719.99,yes,locked 2006.257.08:28:02.85/vblo/07,734.99,yes,locked 2006.257.08:28:02.85/vblo/08,744.99,yes,locked 2006.257.08:28:03.00/vabw/8 2006.257.08:28:03.15/vbbw/8 2006.257.08:28:03.24/xfe/off,on,14.7 2006.257.08:28:03.62/ifatt/23,28,28,28 2006.257.08:28:04.07/fmout-gps/S +4.56E-07 2006.257.08:28:04.12:!2006.257.08:29:19 2006.257.08:29:19.01:data_valid=off 2006.257.08:29:19.02:"et 2006.257.08:29:19.02:!+3s 2006.257.08:29:22.03:"tape 2006.257.08:29:22.04:postob 2006.257.08:29:22.23/cable/+6.4754E-03 2006.257.08:29:22.24/wx/20.70,1012.8,90 2006.257.08:29:22.29/fmout-gps/S +4.57E-07 2006.257.08:29:22.30:scan_name=257-0831,jd0609,160 2006.257.08:29:22.30:source=2128-123,213135.26,-120704.8,2000.0,ccw 2006.257.08:29:24.14#flagr#flagr/antenna,new-source 2006.257.08:29:24.15:checkk5 2006.257.08:29:24.62/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:29:25.02/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:29:25.39/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:29:25.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:29:26.18/chk_obsdata//k5ts1/T2570827??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.08:29:26.58/chk_obsdata//k5ts2/T2570827??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.08:29:26.97/chk_obsdata//k5ts3/T2570827??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.08:29:27.36/chk_obsdata//k5ts4/T2570827??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.08:29:28.09/k5log//k5ts1_log_newline 2006.257.08:29:28.81/k5log//k5ts2_log_newline 2006.257.08:29:29.51/k5log//k5ts3_log_newline 2006.257.08:29:30.22/k5log//k5ts4_log_newline 2006.257.08:29:30.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:29:30.25:setupk4=1 2006.257.08:29:30.25$setupk4/echo=on 2006.257.08:29:30.25$setupk4/pcalon 2006.257.08:29:30.25$pcalon/"no phase cal control is implemented here 2006.257.08:29:30.25$setupk4/"tpicd=stop 2006.257.08:29:30.25$setupk4/"rec=synch_on 2006.257.08:29:30.25$setupk4/"rec_mode=128 2006.257.08:29:30.25$setupk4/!* 2006.257.08:29:30.25$setupk4/recpk4 2006.257.08:29:30.25$recpk4/recpatch= 2006.257.08:29:30.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:29:30.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:29:30.26$setupk4/vck44 2006.257.08:29:30.26$vck44/valo=1,524.99 2006.257.08:29:30.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.08:29:30.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.08:29:30.26#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:30.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:30.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:30.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:30.26#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:29:30.26#ibcon#first serial, iclass 15, count 0 2006.257.08:29:30.26#ibcon#enter sib2, iclass 15, count 0 2006.257.08:29:30.26#ibcon#flushed, iclass 15, count 0 2006.257.08:29:30.26#ibcon#about to write, iclass 15, count 0 2006.257.08:29:30.26#ibcon#wrote, iclass 15, count 0 2006.257.08:29:30.26#ibcon#about to read 3, iclass 15, count 0 2006.257.08:29:30.27#ibcon#read 3, iclass 15, count 0 2006.257.08:29:30.27#ibcon#about to read 4, iclass 15, count 0 2006.257.08:29:30.27#ibcon#read 4, iclass 15, count 0 2006.257.08:29:30.27#ibcon#about to read 5, iclass 15, count 0 2006.257.08:29:30.27#ibcon#read 5, iclass 15, count 0 2006.257.08:29:30.27#ibcon#about to read 6, iclass 15, count 0 2006.257.08:29:30.27#ibcon#read 6, iclass 15, count 0 2006.257.08:29:30.27#ibcon#end of sib2, iclass 15, count 0 2006.257.08:29:30.27#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:29:30.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:29:30.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:29:30.27#ibcon#*before write, iclass 15, count 0 2006.257.08:29:30.27#ibcon#enter sib2, iclass 15, count 0 2006.257.08:29:30.27#ibcon#flushed, iclass 15, count 0 2006.257.08:29:30.27#ibcon#about to write, iclass 15, count 0 2006.257.08:29:30.27#ibcon#wrote, iclass 15, count 0 2006.257.08:29:30.27#ibcon#about to read 3, iclass 15, count 0 2006.257.08:29:30.32#ibcon#read 3, iclass 15, count 0 2006.257.08:29:30.32#ibcon#about to read 4, iclass 15, count 0 2006.257.08:29:30.32#ibcon#read 4, iclass 15, count 0 2006.257.08:29:30.32#ibcon#about to read 5, iclass 15, count 0 2006.257.08:29:30.32#ibcon#read 5, iclass 15, count 0 2006.257.08:29:30.32#ibcon#about to read 6, iclass 15, count 0 2006.257.08:29:30.32#ibcon#read 6, iclass 15, count 0 2006.257.08:29:30.32#ibcon#end of sib2, iclass 15, count 0 2006.257.08:29:30.32#ibcon#*after write, iclass 15, count 0 2006.257.08:29:30.32#ibcon#*before return 0, iclass 15, count 0 2006.257.08:29:30.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:30.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:30.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:29:30.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:29:30.32$vck44/va=1,8 2006.257.08:29:30.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.08:29:30.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.08:29:30.32#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:30.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:30.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:30.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:30.32#ibcon#enter wrdev, iclass 17, count 2 2006.257.08:29:30.32#ibcon#first serial, iclass 17, count 2 2006.257.08:29:30.32#ibcon#enter sib2, iclass 17, count 2 2006.257.08:29:30.32#ibcon#flushed, iclass 17, count 2 2006.257.08:29:30.32#ibcon#about to write, iclass 17, count 2 2006.257.08:29:30.32#ibcon#wrote, iclass 17, count 2 2006.257.08:29:30.32#ibcon#about to read 3, iclass 17, count 2 2006.257.08:29:30.34#ibcon#read 3, iclass 17, count 2 2006.257.08:29:30.34#ibcon#about to read 4, iclass 17, count 2 2006.257.08:29:30.34#ibcon#read 4, iclass 17, count 2 2006.257.08:29:30.34#ibcon#about to read 5, iclass 17, count 2 2006.257.08:29:30.34#ibcon#read 5, iclass 17, count 2 2006.257.08:29:30.34#ibcon#about to read 6, iclass 17, count 2 2006.257.08:29:30.34#ibcon#read 6, iclass 17, count 2 2006.257.08:29:30.34#ibcon#end of sib2, iclass 17, count 2 2006.257.08:29:30.34#ibcon#*mode == 0, iclass 17, count 2 2006.257.08:29:30.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.08:29:30.34#ibcon#[25=AT01-08\r\n] 2006.257.08:29:30.34#ibcon#*before write, iclass 17, count 2 2006.257.08:29:30.34#ibcon#enter sib2, iclass 17, count 2 2006.257.08:29:30.34#ibcon#flushed, iclass 17, count 2 2006.257.08:29:30.34#ibcon#about to write, iclass 17, count 2 2006.257.08:29:30.34#ibcon#wrote, iclass 17, count 2 2006.257.08:29:30.34#ibcon#about to read 3, iclass 17, count 2 2006.257.08:29:30.37#ibcon#read 3, iclass 17, count 2 2006.257.08:29:30.37#ibcon#about to read 4, iclass 17, count 2 2006.257.08:29:30.37#ibcon#read 4, iclass 17, count 2 2006.257.08:29:30.37#ibcon#about to read 5, iclass 17, count 2 2006.257.08:29:30.37#ibcon#read 5, iclass 17, count 2 2006.257.08:29:30.37#ibcon#about to read 6, iclass 17, count 2 2006.257.08:29:30.37#ibcon#read 6, iclass 17, count 2 2006.257.08:29:30.37#ibcon#end of sib2, iclass 17, count 2 2006.257.08:29:30.37#ibcon#*after write, iclass 17, count 2 2006.257.08:29:30.37#ibcon#*before return 0, iclass 17, count 2 2006.257.08:29:30.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:30.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:30.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.08:29:30.37#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:30.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:30.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:30.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:30.49#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:29:30.49#ibcon#first serial, iclass 17, count 0 2006.257.08:29:30.49#ibcon#enter sib2, iclass 17, count 0 2006.257.08:29:30.49#ibcon#flushed, iclass 17, count 0 2006.257.08:29:30.49#ibcon#about to write, iclass 17, count 0 2006.257.08:29:30.49#ibcon#wrote, iclass 17, count 0 2006.257.08:29:30.49#ibcon#about to read 3, iclass 17, count 0 2006.257.08:29:30.51#ibcon#read 3, iclass 17, count 0 2006.257.08:29:30.51#ibcon#about to read 4, iclass 17, count 0 2006.257.08:29:30.51#ibcon#read 4, iclass 17, count 0 2006.257.08:29:30.51#ibcon#about to read 5, iclass 17, count 0 2006.257.08:29:30.51#ibcon#read 5, iclass 17, count 0 2006.257.08:29:30.51#ibcon#about to read 6, iclass 17, count 0 2006.257.08:29:30.51#ibcon#read 6, iclass 17, count 0 2006.257.08:29:30.51#ibcon#end of sib2, iclass 17, count 0 2006.257.08:29:30.51#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:29:30.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:29:30.51#ibcon#[25=USB\r\n] 2006.257.08:29:30.51#ibcon#*before write, iclass 17, count 0 2006.257.08:29:30.51#ibcon#enter sib2, iclass 17, count 0 2006.257.08:29:30.51#ibcon#flushed, iclass 17, count 0 2006.257.08:29:30.51#ibcon#about to write, iclass 17, count 0 2006.257.08:29:30.51#ibcon#wrote, iclass 17, count 0 2006.257.08:29:30.51#ibcon#about to read 3, iclass 17, count 0 2006.257.08:29:30.54#ibcon#read 3, iclass 17, count 0 2006.257.08:29:30.54#ibcon#about to read 4, iclass 17, count 0 2006.257.08:29:30.54#ibcon#read 4, iclass 17, count 0 2006.257.08:29:30.54#ibcon#about to read 5, iclass 17, count 0 2006.257.08:29:30.54#ibcon#read 5, iclass 17, count 0 2006.257.08:29:30.54#ibcon#about to read 6, iclass 17, count 0 2006.257.08:29:30.54#ibcon#read 6, iclass 17, count 0 2006.257.08:29:30.54#ibcon#end of sib2, iclass 17, count 0 2006.257.08:29:30.54#ibcon#*after write, iclass 17, count 0 2006.257.08:29:30.54#ibcon#*before return 0, iclass 17, count 0 2006.257.08:29:30.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:30.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:30.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:29:30.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:29:30.54$vck44/valo=2,534.99 2006.257.08:29:30.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.08:29:30.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.08:29:30.54#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:30.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:30.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:30.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:30.54#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:29:30.54#ibcon#first serial, iclass 19, count 0 2006.257.08:29:30.54#ibcon#enter sib2, iclass 19, count 0 2006.257.08:29:30.54#ibcon#flushed, iclass 19, count 0 2006.257.08:29:30.54#ibcon#about to write, iclass 19, count 0 2006.257.08:29:30.54#ibcon#wrote, iclass 19, count 0 2006.257.08:29:30.54#ibcon#about to read 3, iclass 19, count 0 2006.257.08:29:30.56#ibcon#read 3, iclass 19, count 0 2006.257.08:29:30.56#ibcon#about to read 4, iclass 19, count 0 2006.257.08:29:30.56#ibcon#read 4, iclass 19, count 0 2006.257.08:29:30.56#ibcon#about to read 5, iclass 19, count 0 2006.257.08:29:30.56#ibcon#read 5, iclass 19, count 0 2006.257.08:29:30.56#ibcon#about to read 6, iclass 19, count 0 2006.257.08:29:30.56#ibcon#read 6, iclass 19, count 0 2006.257.08:29:30.56#ibcon#end of sib2, iclass 19, count 0 2006.257.08:29:30.56#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:29:30.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:29:30.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:29:30.56#ibcon#*before write, iclass 19, count 0 2006.257.08:29:30.56#ibcon#enter sib2, iclass 19, count 0 2006.257.08:29:30.56#ibcon#flushed, iclass 19, count 0 2006.257.08:29:30.56#ibcon#about to write, iclass 19, count 0 2006.257.08:29:30.56#ibcon#wrote, iclass 19, count 0 2006.257.08:29:30.56#ibcon#about to read 3, iclass 19, count 0 2006.257.08:29:30.60#ibcon#read 3, iclass 19, count 0 2006.257.08:29:30.60#ibcon#about to read 4, iclass 19, count 0 2006.257.08:29:30.60#ibcon#read 4, iclass 19, count 0 2006.257.08:29:30.60#ibcon#about to read 5, iclass 19, count 0 2006.257.08:29:30.60#ibcon#read 5, iclass 19, count 0 2006.257.08:29:30.60#ibcon#about to read 6, iclass 19, count 0 2006.257.08:29:30.60#ibcon#read 6, iclass 19, count 0 2006.257.08:29:30.60#ibcon#end of sib2, iclass 19, count 0 2006.257.08:29:30.60#ibcon#*after write, iclass 19, count 0 2006.257.08:29:30.60#ibcon#*before return 0, iclass 19, count 0 2006.257.08:29:30.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:30.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:30.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:29:30.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:29:30.60$vck44/va=2,7 2006.257.08:29:30.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.08:29:30.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.08:29:30.60#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:30.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:30.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:30.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:30.66#ibcon#enter wrdev, iclass 21, count 2 2006.257.08:29:30.66#ibcon#first serial, iclass 21, count 2 2006.257.08:29:30.66#ibcon#enter sib2, iclass 21, count 2 2006.257.08:29:30.66#ibcon#flushed, iclass 21, count 2 2006.257.08:29:30.66#ibcon#about to write, iclass 21, count 2 2006.257.08:29:30.66#ibcon#wrote, iclass 21, count 2 2006.257.08:29:30.66#ibcon#about to read 3, iclass 21, count 2 2006.257.08:29:30.68#ibcon#read 3, iclass 21, count 2 2006.257.08:29:30.68#ibcon#about to read 4, iclass 21, count 2 2006.257.08:29:30.68#ibcon#read 4, iclass 21, count 2 2006.257.08:29:30.68#ibcon#about to read 5, iclass 21, count 2 2006.257.08:29:30.68#ibcon#read 5, iclass 21, count 2 2006.257.08:29:30.68#ibcon#about to read 6, iclass 21, count 2 2006.257.08:29:30.68#ibcon#read 6, iclass 21, count 2 2006.257.08:29:30.68#ibcon#end of sib2, iclass 21, count 2 2006.257.08:29:30.68#ibcon#*mode == 0, iclass 21, count 2 2006.257.08:29:30.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.08:29:30.68#ibcon#[25=AT02-07\r\n] 2006.257.08:29:30.68#ibcon#*before write, iclass 21, count 2 2006.257.08:29:30.68#ibcon#enter sib2, iclass 21, count 2 2006.257.08:29:30.68#ibcon#flushed, iclass 21, count 2 2006.257.08:29:30.68#ibcon#about to write, iclass 21, count 2 2006.257.08:29:30.68#ibcon#wrote, iclass 21, count 2 2006.257.08:29:30.68#ibcon#about to read 3, iclass 21, count 2 2006.257.08:29:30.71#ibcon#read 3, iclass 21, count 2 2006.257.08:29:30.71#ibcon#about to read 4, iclass 21, count 2 2006.257.08:29:30.71#ibcon#read 4, iclass 21, count 2 2006.257.08:29:30.71#ibcon#about to read 5, iclass 21, count 2 2006.257.08:29:30.71#ibcon#read 5, iclass 21, count 2 2006.257.08:29:30.71#ibcon#about to read 6, iclass 21, count 2 2006.257.08:29:30.71#ibcon#read 6, iclass 21, count 2 2006.257.08:29:30.71#ibcon#end of sib2, iclass 21, count 2 2006.257.08:29:30.71#ibcon#*after write, iclass 21, count 2 2006.257.08:29:30.71#ibcon#*before return 0, iclass 21, count 2 2006.257.08:29:30.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:30.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:30.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.08:29:30.71#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:30.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:30.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:30.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:30.83#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:29:30.83#ibcon#first serial, iclass 21, count 0 2006.257.08:29:30.83#ibcon#enter sib2, iclass 21, count 0 2006.257.08:29:30.83#ibcon#flushed, iclass 21, count 0 2006.257.08:29:30.83#ibcon#about to write, iclass 21, count 0 2006.257.08:29:30.83#ibcon#wrote, iclass 21, count 0 2006.257.08:29:30.83#ibcon#about to read 3, iclass 21, count 0 2006.257.08:29:30.85#ibcon#read 3, iclass 21, count 0 2006.257.08:29:30.85#ibcon#about to read 4, iclass 21, count 0 2006.257.08:29:30.85#ibcon#read 4, iclass 21, count 0 2006.257.08:29:30.85#ibcon#about to read 5, iclass 21, count 0 2006.257.08:29:30.85#ibcon#read 5, iclass 21, count 0 2006.257.08:29:30.85#ibcon#about to read 6, iclass 21, count 0 2006.257.08:29:30.85#ibcon#read 6, iclass 21, count 0 2006.257.08:29:30.85#ibcon#end of sib2, iclass 21, count 0 2006.257.08:29:30.85#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:29:30.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:29:30.85#ibcon#[25=USB\r\n] 2006.257.08:29:30.85#ibcon#*before write, iclass 21, count 0 2006.257.08:29:30.85#ibcon#enter sib2, iclass 21, count 0 2006.257.08:29:30.85#ibcon#flushed, iclass 21, count 0 2006.257.08:29:30.85#ibcon#about to write, iclass 21, count 0 2006.257.08:29:30.85#ibcon#wrote, iclass 21, count 0 2006.257.08:29:30.85#ibcon#about to read 3, iclass 21, count 0 2006.257.08:29:30.88#ibcon#read 3, iclass 21, count 0 2006.257.08:29:30.88#ibcon#about to read 4, iclass 21, count 0 2006.257.08:29:30.88#ibcon#read 4, iclass 21, count 0 2006.257.08:29:30.88#ibcon#about to read 5, iclass 21, count 0 2006.257.08:29:30.88#ibcon#read 5, iclass 21, count 0 2006.257.08:29:30.88#ibcon#about to read 6, iclass 21, count 0 2006.257.08:29:30.88#ibcon#read 6, iclass 21, count 0 2006.257.08:29:30.88#ibcon#end of sib2, iclass 21, count 0 2006.257.08:29:30.88#ibcon#*after write, iclass 21, count 0 2006.257.08:29:30.88#ibcon#*before return 0, iclass 21, count 0 2006.257.08:29:30.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:30.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:30.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:29:30.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:29:30.88$vck44/valo=3,564.99 2006.257.08:29:30.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.08:29:30.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.08:29:30.88#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:30.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:30.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:30.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:30.88#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:29:30.88#ibcon#first serial, iclass 23, count 0 2006.257.08:29:30.88#ibcon#enter sib2, iclass 23, count 0 2006.257.08:29:30.88#ibcon#flushed, iclass 23, count 0 2006.257.08:29:30.88#ibcon#about to write, iclass 23, count 0 2006.257.08:29:30.88#ibcon#wrote, iclass 23, count 0 2006.257.08:29:30.88#ibcon#about to read 3, iclass 23, count 0 2006.257.08:29:30.90#ibcon#read 3, iclass 23, count 0 2006.257.08:29:30.90#ibcon#about to read 4, iclass 23, count 0 2006.257.08:29:30.90#ibcon#read 4, iclass 23, count 0 2006.257.08:29:30.90#ibcon#about to read 5, iclass 23, count 0 2006.257.08:29:30.90#ibcon#read 5, iclass 23, count 0 2006.257.08:29:30.90#ibcon#about to read 6, iclass 23, count 0 2006.257.08:29:30.90#ibcon#read 6, iclass 23, count 0 2006.257.08:29:30.90#ibcon#end of sib2, iclass 23, count 0 2006.257.08:29:30.90#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:29:30.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:29:30.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:29:30.90#ibcon#*before write, iclass 23, count 0 2006.257.08:29:30.90#ibcon#enter sib2, iclass 23, count 0 2006.257.08:29:30.90#ibcon#flushed, iclass 23, count 0 2006.257.08:29:30.90#ibcon#about to write, iclass 23, count 0 2006.257.08:29:30.90#ibcon#wrote, iclass 23, count 0 2006.257.08:29:30.90#ibcon#about to read 3, iclass 23, count 0 2006.257.08:29:30.94#ibcon#read 3, iclass 23, count 0 2006.257.08:29:30.94#ibcon#about to read 4, iclass 23, count 0 2006.257.08:29:30.94#ibcon#read 4, iclass 23, count 0 2006.257.08:29:30.94#ibcon#about to read 5, iclass 23, count 0 2006.257.08:29:30.94#ibcon#read 5, iclass 23, count 0 2006.257.08:29:30.94#ibcon#about to read 6, iclass 23, count 0 2006.257.08:29:30.94#ibcon#read 6, iclass 23, count 0 2006.257.08:29:30.94#ibcon#end of sib2, iclass 23, count 0 2006.257.08:29:30.94#ibcon#*after write, iclass 23, count 0 2006.257.08:29:30.94#ibcon#*before return 0, iclass 23, count 0 2006.257.08:29:30.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:30.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:30.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:29:30.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:29:30.94$vck44/va=3,8 2006.257.08:29:30.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.08:29:30.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.08:29:30.94#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:30.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:31.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:31.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:31.00#ibcon#enter wrdev, iclass 25, count 2 2006.257.08:29:31.00#ibcon#first serial, iclass 25, count 2 2006.257.08:29:31.00#ibcon#enter sib2, iclass 25, count 2 2006.257.08:29:31.00#ibcon#flushed, iclass 25, count 2 2006.257.08:29:31.00#ibcon#about to write, iclass 25, count 2 2006.257.08:29:31.00#ibcon#wrote, iclass 25, count 2 2006.257.08:29:31.00#ibcon#about to read 3, iclass 25, count 2 2006.257.08:29:31.02#ibcon#read 3, iclass 25, count 2 2006.257.08:29:31.02#ibcon#about to read 4, iclass 25, count 2 2006.257.08:29:31.02#ibcon#read 4, iclass 25, count 2 2006.257.08:29:31.02#ibcon#about to read 5, iclass 25, count 2 2006.257.08:29:31.02#ibcon#read 5, iclass 25, count 2 2006.257.08:29:31.02#ibcon#about to read 6, iclass 25, count 2 2006.257.08:29:31.02#ibcon#read 6, iclass 25, count 2 2006.257.08:29:31.02#ibcon#end of sib2, iclass 25, count 2 2006.257.08:29:31.02#ibcon#*mode == 0, iclass 25, count 2 2006.257.08:29:31.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.08:29:31.02#ibcon#[25=AT03-08\r\n] 2006.257.08:29:31.02#ibcon#*before write, iclass 25, count 2 2006.257.08:29:31.02#ibcon#enter sib2, iclass 25, count 2 2006.257.08:29:31.02#ibcon#flushed, iclass 25, count 2 2006.257.08:29:31.02#ibcon#about to write, iclass 25, count 2 2006.257.08:29:31.02#ibcon#wrote, iclass 25, count 2 2006.257.08:29:31.02#ibcon#about to read 3, iclass 25, count 2 2006.257.08:29:31.05#ibcon#read 3, iclass 25, count 2 2006.257.08:29:31.05#ibcon#about to read 4, iclass 25, count 2 2006.257.08:29:31.05#ibcon#read 4, iclass 25, count 2 2006.257.08:29:31.05#ibcon#about to read 5, iclass 25, count 2 2006.257.08:29:31.05#ibcon#read 5, iclass 25, count 2 2006.257.08:29:31.05#ibcon#about to read 6, iclass 25, count 2 2006.257.08:29:31.05#ibcon#read 6, iclass 25, count 2 2006.257.08:29:31.05#ibcon#end of sib2, iclass 25, count 2 2006.257.08:29:31.05#ibcon#*after write, iclass 25, count 2 2006.257.08:29:31.05#ibcon#*before return 0, iclass 25, count 2 2006.257.08:29:31.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:31.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:31.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.08:29:31.05#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:31.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:31.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:31.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:31.17#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:29:31.17#ibcon#first serial, iclass 25, count 0 2006.257.08:29:31.17#ibcon#enter sib2, iclass 25, count 0 2006.257.08:29:31.17#ibcon#flushed, iclass 25, count 0 2006.257.08:29:31.17#ibcon#about to write, iclass 25, count 0 2006.257.08:29:31.17#ibcon#wrote, iclass 25, count 0 2006.257.08:29:31.17#ibcon#about to read 3, iclass 25, count 0 2006.257.08:29:31.19#ibcon#read 3, iclass 25, count 0 2006.257.08:29:31.19#ibcon#about to read 4, iclass 25, count 0 2006.257.08:29:31.19#ibcon#read 4, iclass 25, count 0 2006.257.08:29:31.19#ibcon#about to read 5, iclass 25, count 0 2006.257.08:29:31.19#ibcon#read 5, iclass 25, count 0 2006.257.08:29:31.19#ibcon#about to read 6, iclass 25, count 0 2006.257.08:29:31.19#ibcon#read 6, iclass 25, count 0 2006.257.08:29:31.19#ibcon#end of sib2, iclass 25, count 0 2006.257.08:29:31.19#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:29:31.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:29:31.19#ibcon#[25=USB\r\n] 2006.257.08:29:31.19#ibcon#*before write, iclass 25, count 0 2006.257.08:29:31.19#ibcon#enter sib2, iclass 25, count 0 2006.257.08:29:31.19#ibcon#flushed, iclass 25, count 0 2006.257.08:29:31.19#ibcon#about to write, iclass 25, count 0 2006.257.08:29:31.19#ibcon#wrote, iclass 25, count 0 2006.257.08:29:31.19#ibcon#about to read 3, iclass 25, count 0 2006.257.08:29:31.22#ibcon#read 3, iclass 25, count 0 2006.257.08:29:31.22#ibcon#about to read 4, iclass 25, count 0 2006.257.08:29:31.22#ibcon#read 4, iclass 25, count 0 2006.257.08:29:31.22#ibcon#about to read 5, iclass 25, count 0 2006.257.08:29:31.22#ibcon#read 5, iclass 25, count 0 2006.257.08:29:31.22#ibcon#about to read 6, iclass 25, count 0 2006.257.08:29:31.22#ibcon#read 6, iclass 25, count 0 2006.257.08:29:31.22#ibcon#end of sib2, iclass 25, count 0 2006.257.08:29:31.22#ibcon#*after write, iclass 25, count 0 2006.257.08:29:31.22#ibcon#*before return 0, iclass 25, count 0 2006.257.08:29:31.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:31.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:31.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:29:31.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:29:31.22$vck44/valo=4,624.99 2006.257.08:29:31.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.08:29:31.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.08:29:31.22#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:31.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:31.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:31.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:31.22#ibcon#enter wrdev, iclass 27, count 0 2006.257.08:29:31.22#ibcon#first serial, iclass 27, count 0 2006.257.08:29:31.22#ibcon#enter sib2, iclass 27, count 0 2006.257.08:29:31.22#ibcon#flushed, iclass 27, count 0 2006.257.08:29:31.22#ibcon#about to write, iclass 27, count 0 2006.257.08:29:31.22#ibcon#wrote, iclass 27, count 0 2006.257.08:29:31.22#ibcon#about to read 3, iclass 27, count 0 2006.257.08:29:31.24#ibcon#read 3, iclass 27, count 0 2006.257.08:29:31.24#ibcon#about to read 4, iclass 27, count 0 2006.257.08:29:31.24#ibcon#read 4, iclass 27, count 0 2006.257.08:29:31.24#ibcon#about to read 5, iclass 27, count 0 2006.257.08:29:31.24#ibcon#read 5, iclass 27, count 0 2006.257.08:29:31.24#ibcon#about to read 6, iclass 27, count 0 2006.257.08:29:31.24#ibcon#read 6, iclass 27, count 0 2006.257.08:29:31.24#ibcon#end of sib2, iclass 27, count 0 2006.257.08:29:31.24#ibcon#*mode == 0, iclass 27, count 0 2006.257.08:29:31.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.08:29:31.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:29:31.24#ibcon#*before write, iclass 27, count 0 2006.257.08:29:31.24#ibcon#enter sib2, iclass 27, count 0 2006.257.08:29:31.24#ibcon#flushed, iclass 27, count 0 2006.257.08:29:31.24#ibcon#about to write, iclass 27, count 0 2006.257.08:29:31.24#ibcon#wrote, iclass 27, count 0 2006.257.08:29:31.24#ibcon#about to read 3, iclass 27, count 0 2006.257.08:29:31.28#ibcon#read 3, iclass 27, count 0 2006.257.08:29:31.28#ibcon#about to read 4, iclass 27, count 0 2006.257.08:29:31.28#ibcon#read 4, iclass 27, count 0 2006.257.08:29:31.28#ibcon#about to read 5, iclass 27, count 0 2006.257.08:29:31.28#ibcon#read 5, iclass 27, count 0 2006.257.08:29:31.28#ibcon#about to read 6, iclass 27, count 0 2006.257.08:29:31.28#ibcon#read 6, iclass 27, count 0 2006.257.08:29:31.28#ibcon#end of sib2, iclass 27, count 0 2006.257.08:29:31.28#ibcon#*after write, iclass 27, count 0 2006.257.08:29:31.28#ibcon#*before return 0, iclass 27, count 0 2006.257.08:29:31.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:31.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:31.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.08:29:31.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.08:29:31.28$vck44/va=4,7 2006.257.08:29:31.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.08:29:31.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.08:29:31.28#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:31.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:31.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:31.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:31.34#ibcon#enter wrdev, iclass 29, count 2 2006.257.08:29:31.34#ibcon#first serial, iclass 29, count 2 2006.257.08:29:31.34#ibcon#enter sib2, iclass 29, count 2 2006.257.08:29:31.34#ibcon#flushed, iclass 29, count 2 2006.257.08:29:31.34#ibcon#about to write, iclass 29, count 2 2006.257.08:29:31.34#ibcon#wrote, iclass 29, count 2 2006.257.08:29:31.34#ibcon#about to read 3, iclass 29, count 2 2006.257.08:29:31.36#ibcon#read 3, iclass 29, count 2 2006.257.08:29:31.36#ibcon#about to read 4, iclass 29, count 2 2006.257.08:29:31.36#ibcon#read 4, iclass 29, count 2 2006.257.08:29:31.36#ibcon#about to read 5, iclass 29, count 2 2006.257.08:29:31.36#ibcon#read 5, iclass 29, count 2 2006.257.08:29:31.36#ibcon#about to read 6, iclass 29, count 2 2006.257.08:29:31.36#ibcon#read 6, iclass 29, count 2 2006.257.08:29:31.36#ibcon#end of sib2, iclass 29, count 2 2006.257.08:29:31.36#ibcon#*mode == 0, iclass 29, count 2 2006.257.08:29:31.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.08:29:31.36#ibcon#[25=AT04-07\r\n] 2006.257.08:29:31.36#ibcon#*before write, iclass 29, count 2 2006.257.08:29:31.36#ibcon#enter sib2, iclass 29, count 2 2006.257.08:29:31.36#ibcon#flushed, iclass 29, count 2 2006.257.08:29:31.36#ibcon#about to write, iclass 29, count 2 2006.257.08:29:31.36#ibcon#wrote, iclass 29, count 2 2006.257.08:29:31.36#ibcon#about to read 3, iclass 29, count 2 2006.257.08:29:31.39#ibcon#read 3, iclass 29, count 2 2006.257.08:29:31.39#ibcon#about to read 4, iclass 29, count 2 2006.257.08:29:31.39#ibcon#read 4, iclass 29, count 2 2006.257.08:29:31.39#ibcon#about to read 5, iclass 29, count 2 2006.257.08:29:31.39#ibcon#read 5, iclass 29, count 2 2006.257.08:29:31.39#ibcon#about to read 6, iclass 29, count 2 2006.257.08:29:31.39#ibcon#read 6, iclass 29, count 2 2006.257.08:29:31.39#ibcon#end of sib2, iclass 29, count 2 2006.257.08:29:31.39#ibcon#*after write, iclass 29, count 2 2006.257.08:29:31.40#ibcon#*before return 0, iclass 29, count 2 2006.257.08:29:31.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:31.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:31.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.08:29:31.40#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:31.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:31.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:31.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:31.51#ibcon#enter wrdev, iclass 29, count 0 2006.257.08:29:31.51#ibcon#first serial, iclass 29, count 0 2006.257.08:29:31.51#ibcon#enter sib2, iclass 29, count 0 2006.257.08:29:31.51#ibcon#flushed, iclass 29, count 0 2006.257.08:29:31.51#ibcon#about to write, iclass 29, count 0 2006.257.08:29:31.51#ibcon#wrote, iclass 29, count 0 2006.257.08:29:31.51#ibcon#about to read 3, iclass 29, count 0 2006.257.08:29:31.53#ibcon#read 3, iclass 29, count 0 2006.257.08:29:31.53#ibcon#about to read 4, iclass 29, count 0 2006.257.08:29:31.53#ibcon#read 4, iclass 29, count 0 2006.257.08:29:31.53#ibcon#about to read 5, iclass 29, count 0 2006.257.08:29:31.53#ibcon#read 5, iclass 29, count 0 2006.257.08:29:31.53#ibcon#about to read 6, iclass 29, count 0 2006.257.08:29:31.53#ibcon#read 6, iclass 29, count 0 2006.257.08:29:31.53#ibcon#end of sib2, iclass 29, count 0 2006.257.08:29:31.53#ibcon#*mode == 0, iclass 29, count 0 2006.257.08:29:31.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.08:29:31.53#ibcon#[25=USB\r\n] 2006.257.08:29:31.53#ibcon#*before write, iclass 29, count 0 2006.257.08:29:31.53#ibcon#enter sib2, iclass 29, count 0 2006.257.08:29:31.53#ibcon#flushed, iclass 29, count 0 2006.257.08:29:31.53#ibcon#about to write, iclass 29, count 0 2006.257.08:29:31.53#ibcon#wrote, iclass 29, count 0 2006.257.08:29:31.53#ibcon#about to read 3, iclass 29, count 0 2006.257.08:29:31.56#ibcon#read 3, iclass 29, count 0 2006.257.08:29:31.56#ibcon#about to read 4, iclass 29, count 0 2006.257.08:29:31.56#ibcon#read 4, iclass 29, count 0 2006.257.08:29:31.56#ibcon#about to read 5, iclass 29, count 0 2006.257.08:29:31.56#ibcon#read 5, iclass 29, count 0 2006.257.08:29:31.56#ibcon#about to read 6, iclass 29, count 0 2006.257.08:29:31.56#ibcon#read 6, iclass 29, count 0 2006.257.08:29:31.56#ibcon#end of sib2, iclass 29, count 0 2006.257.08:29:31.56#ibcon#*after write, iclass 29, count 0 2006.257.08:29:31.56#ibcon#*before return 0, iclass 29, count 0 2006.257.08:29:31.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:31.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:31.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.08:29:31.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.08:29:31.56$vck44/valo=5,734.99 2006.257.08:29:31.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.08:29:31.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.08:29:31.56#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:31.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:31.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:31.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:31.56#ibcon#enter wrdev, iclass 31, count 0 2006.257.08:29:31.56#ibcon#first serial, iclass 31, count 0 2006.257.08:29:31.56#ibcon#enter sib2, iclass 31, count 0 2006.257.08:29:31.56#ibcon#flushed, iclass 31, count 0 2006.257.08:29:31.56#ibcon#about to write, iclass 31, count 0 2006.257.08:29:31.56#ibcon#wrote, iclass 31, count 0 2006.257.08:29:31.56#ibcon#about to read 3, iclass 31, count 0 2006.257.08:29:31.58#ibcon#read 3, iclass 31, count 0 2006.257.08:29:31.58#ibcon#about to read 4, iclass 31, count 0 2006.257.08:29:31.58#ibcon#read 4, iclass 31, count 0 2006.257.08:29:31.58#ibcon#about to read 5, iclass 31, count 0 2006.257.08:29:31.58#ibcon#read 5, iclass 31, count 0 2006.257.08:29:31.58#ibcon#about to read 6, iclass 31, count 0 2006.257.08:29:31.58#ibcon#read 6, iclass 31, count 0 2006.257.08:29:31.58#ibcon#end of sib2, iclass 31, count 0 2006.257.08:29:31.58#ibcon#*mode == 0, iclass 31, count 0 2006.257.08:29:31.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.08:29:31.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:29:31.58#ibcon#*before write, iclass 31, count 0 2006.257.08:29:31.58#ibcon#enter sib2, iclass 31, count 0 2006.257.08:29:31.58#ibcon#flushed, iclass 31, count 0 2006.257.08:29:31.58#ibcon#about to write, iclass 31, count 0 2006.257.08:29:31.58#ibcon#wrote, iclass 31, count 0 2006.257.08:29:31.58#ibcon#about to read 3, iclass 31, count 0 2006.257.08:29:31.62#ibcon#read 3, iclass 31, count 0 2006.257.08:29:31.62#ibcon#about to read 4, iclass 31, count 0 2006.257.08:29:31.62#ibcon#read 4, iclass 31, count 0 2006.257.08:29:31.62#ibcon#about to read 5, iclass 31, count 0 2006.257.08:29:31.62#ibcon#read 5, iclass 31, count 0 2006.257.08:29:31.62#ibcon#about to read 6, iclass 31, count 0 2006.257.08:29:31.62#ibcon#read 6, iclass 31, count 0 2006.257.08:29:31.62#ibcon#end of sib2, iclass 31, count 0 2006.257.08:29:31.62#ibcon#*after write, iclass 31, count 0 2006.257.08:29:31.62#ibcon#*before return 0, iclass 31, count 0 2006.257.08:29:31.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:31.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:31.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.08:29:31.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.08:29:31.62$vck44/va=5,4 2006.257.08:29:31.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.08:29:31.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.08:29:31.62#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:31.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:31.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:31.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:31.68#ibcon#enter wrdev, iclass 33, count 2 2006.257.08:29:31.68#ibcon#first serial, iclass 33, count 2 2006.257.08:29:31.68#ibcon#enter sib2, iclass 33, count 2 2006.257.08:29:31.68#ibcon#flushed, iclass 33, count 2 2006.257.08:29:31.68#ibcon#about to write, iclass 33, count 2 2006.257.08:29:31.68#ibcon#wrote, iclass 33, count 2 2006.257.08:29:31.68#ibcon#about to read 3, iclass 33, count 2 2006.257.08:29:31.70#ibcon#read 3, iclass 33, count 2 2006.257.08:29:31.70#ibcon#about to read 4, iclass 33, count 2 2006.257.08:29:31.70#ibcon#read 4, iclass 33, count 2 2006.257.08:29:31.70#ibcon#about to read 5, iclass 33, count 2 2006.257.08:29:31.70#ibcon#read 5, iclass 33, count 2 2006.257.08:29:31.70#ibcon#about to read 6, iclass 33, count 2 2006.257.08:29:31.70#ibcon#read 6, iclass 33, count 2 2006.257.08:29:31.70#ibcon#end of sib2, iclass 33, count 2 2006.257.08:29:31.70#ibcon#*mode == 0, iclass 33, count 2 2006.257.08:29:31.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.08:29:31.70#ibcon#[25=AT05-04\r\n] 2006.257.08:29:31.70#ibcon#*before write, iclass 33, count 2 2006.257.08:29:31.70#ibcon#enter sib2, iclass 33, count 2 2006.257.08:29:31.70#ibcon#flushed, iclass 33, count 2 2006.257.08:29:31.70#ibcon#about to write, iclass 33, count 2 2006.257.08:29:31.70#ibcon#wrote, iclass 33, count 2 2006.257.08:29:31.70#ibcon#about to read 3, iclass 33, count 2 2006.257.08:29:31.73#ibcon#read 3, iclass 33, count 2 2006.257.08:29:31.73#ibcon#about to read 4, iclass 33, count 2 2006.257.08:29:31.73#ibcon#read 4, iclass 33, count 2 2006.257.08:29:31.73#ibcon#about to read 5, iclass 33, count 2 2006.257.08:29:31.73#ibcon#read 5, iclass 33, count 2 2006.257.08:29:31.73#ibcon#about to read 6, iclass 33, count 2 2006.257.08:29:31.73#ibcon#read 6, iclass 33, count 2 2006.257.08:29:31.73#ibcon#end of sib2, iclass 33, count 2 2006.257.08:29:31.73#ibcon#*after write, iclass 33, count 2 2006.257.08:29:31.73#ibcon#*before return 0, iclass 33, count 2 2006.257.08:29:31.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:31.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:31.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.08:29:31.73#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:31.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:31.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:31.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:31.85#ibcon#enter wrdev, iclass 33, count 0 2006.257.08:29:31.85#ibcon#first serial, iclass 33, count 0 2006.257.08:29:31.85#ibcon#enter sib2, iclass 33, count 0 2006.257.08:29:31.85#ibcon#flushed, iclass 33, count 0 2006.257.08:29:31.85#ibcon#about to write, iclass 33, count 0 2006.257.08:29:31.85#ibcon#wrote, iclass 33, count 0 2006.257.08:29:31.85#ibcon#about to read 3, iclass 33, count 0 2006.257.08:29:31.87#ibcon#read 3, iclass 33, count 0 2006.257.08:29:31.87#ibcon#about to read 4, iclass 33, count 0 2006.257.08:29:31.87#ibcon#read 4, iclass 33, count 0 2006.257.08:29:31.87#ibcon#about to read 5, iclass 33, count 0 2006.257.08:29:31.87#ibcon#read 5, iclass 33, count 0 2006.257.08:29:31.87#ibcon#about to read 6, iclass 33, count 0 2006.257.08:29:31.87#ibcon#read 6, iclass 33, count 0 2006.257.08:29:31.87#ibcon#end of sib2, iclass 33, count 0 2006.257.08:29:31.87#ibcon#*mode == 0, iclass 33, count 0 2006.257.08:29:31.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.08:29:31.87#ibcon#[25=USB\r\n] 2006.257.08:29:31.87#ibcon#*before write, iclass 33, count 0 2006.257.08:29:31.87#ibcon#enter sib2, iclass 33, count 0 2006.257.08:29:31.87#ibcon#flushed, iclass 33, count 0 2006.257.08:29:31.87#ibcon#about to write, iclass 33, count 0 2006.257.08:29:31.87#ibcon#wrote, iclass 33, count 0 2006.257.08:29:31.87#ibcon#about to read 3, iclass 33, count 0 2006.257.08:29:31.90#ibcon#read 3, iclass 33, count 0 2006.257.08:29:31.90#ibcon#about to read 4, iclass 33, count 0 2006.257.08:29:31.90#ibcon#read 4, iclass 33, count 0 2006.257.08:29:31.90#ibcon#about to read 5, iclass 33, count 0 2006.257.08:29:31.90#ibcon#read 5, iclass 33, count 0 2006.257.08:29:31.90#ibcon#about to read 6, iclass 33, count 0 2006.257.08:29:31.90#ibcon#read 6, iclass 33, count 0 2006.257.08:29:31.90#ibcon#end of sib2, iclass 33, count 0 2006.257.08:29:31.90#ibcon#*after write, iclass 33, count 0 2006.257.08:29:31.90#ibcon#*before return 0, iclass 33, count 0 2006.257.08:29:31.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:31.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:31.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.08:29:31.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.08:29:31.90$vck44/valo=6,814.99 2006.257.08:29:31.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.08:29:31.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.08:29:31.90#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:31.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:31.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:31.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:31.90#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:29:31.90#ibcon#first serial, iclass 35, count 0 2006.257.08:29:31.90#ibcon#enter sib2, iclass 35, count 0 2006.257.08:29:31.90#ibcon#flushed, iclass 35, count 0 2006.257.08:29:31.90#ibcon#about to write, iclass 35, count 0 2006.257.08:29:31.90#ibcon#wrote, iclass 35, count 0 2006.257.08:29:31.90#ibcon#about to read 3, iclass 35, count 0 2006.257.08:29:31.92#ibcon#read 3, iclass 35, count 0 2006.257.08:29:31.92#ibcon#about to read 4, iclass 35, count 0 2006.257.08:29:31.92#ibcon#read 4, iclass 35, count 0 2006.257.08:29:31.92#ibcon#about to read 5, iclass 35, count 0 2006.257.08:29:31.92#ibcon#read 5, iclass 35, count 0 2006.257.08:29:31.92#ibcon#about to read 6, iclass 35, count 0 2006.257.08:29:31.92#ibcon#read 6, iclass 35, count 0 2006.257.08:29:31.92#ibcon#end of sib2, iclass 35, count 0 2006.257.08:29:31.92#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:29:31.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:29:31.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:29:31.92#ibcon#*before write, iclass 35, count 0 2006.257.08:29:31.92#ibcon#enter sib2, iclass 35, count 0 2006.257.08:29:31.92#ibcon#flushed, iclass 35, count 0 2006.257.08:29:31.92#ibcon#about to write, iclass 35, count 0 2006.257.08:29:31.92#ibcon#wrote, iclass 35, count 0 2006.257.08:29:31.92#ibcon#about to read 3, iclass 35, count 0 2006.257.08:29:31.96#ibcon#read 3, iclass 35, count 0 2006.257.08:29:31.96#ibcon#about to read 4, iclass 35, count 0 2006.257.08:29:31.96#ibcon#read 4, iclass 35, count 0 2006.257.08:29:31.96#ibcon#about to read 5, iclass 35, count 0 2006.257.08:29:31.96#ibcon#read 5, iclass 35, count 0 2006.257.08:29:31.96#ibcon#about to read 6, iclass 35, count 0 2006.257.08:29:31.96#ibcon#read 6, iclass 35, count 0 2006.257.08:29:31.96#ibcon#end of sib2, iclass 35, count 0 2006.257.08:29:31.96#ibcon#*after write, iclass 35, count 0 2006.257.08:29:31.96#ibcon#*before return 0, iclass 35, count 0 2006.257.08:29:31.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:31.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:31.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:29:31.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:29:31.96$vck44/va=6,4 2006.257.08:29:31.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.08:29:31.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.08:29:31.96#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:31.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:32.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:32.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:32.02#ibcon#enter wrdev, iclass 37, count 2 2006.257.08:29:32.02#ibcon#first serial, iclass 37, count 2 2006.257.08:29:32.02#ibcon#enter sib2, iclass 37, count 2 2006.257.08:29:32.02#ibcon#flushed, iclass 37, count 2 2006.257.08:29:32.02#ibcon#about to write, iclass 37, count 2 2006.257.08:29:32.02#ibcon#wrote, iclass 37, count 2 2006.257.08:29:32.02#ibcon#about to read 3, iclass 37, count 2 2006.257.08:29:32.04#ibcon#read 3, iclass 37, count 2 2006.257.08:29:32.04#ibcon#about to read 4, iclass 37, count 2 2006.257.08:29:32.04#ibcon#read 4, iclass 37, count 2 2006.257.08:29:32.04#ibcon#about to read 5, iclass 37, count 2 2006.257.08:29:32.04#ibcon#read 5, iclass 37, count 2 2006.257.08:29:32.04#ibcon#about to read 6, iclass 37, count 2 2006.257.08:29:32.04#ibcon#read 6, iclass 37, count 2 2006.257.08:29:32.04#ibcon#end of sib2, iclass 37, count 2 2006.257.08:29:32.04#ibcon#*mode == 0, iclass 37, count 2 2006.257.08:29:32.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.08:29:32.04#ibcon#[25=AT06-04\r\n] 2006.257.08:29:32.04#ibcon#*before write, iclass 37, count 2 2006.257.08:29:32.04#ibcon#enter sib2, iclass 37, count 2 2006.257.08:29:32.04#ibcon#flushed, iclass 37, count 2 2006.257.08:29:32.04#ibcon#about to write, iclass 37, count 2 2006.257.08:29:32.04#ibcon#wrote, iclass 37, count 2 2006.257.08:29:32.04#ibcon#about to read 3, iclass 37, count 2 2006.257.08:29:32.07#ibcon#read 3, iclass 37, count 2 2006.257.08:29:32.07#ibcon#about to read 4, iclass 37, count 2 2006.257.08:29:32.07#ibcon#read 4, iclass 37, count 2 2006.257.08:29:32.07#ibcon#about to read 5, iclass 37, count 2 2006.257.08:29:32.07#ibcon#read 5, iclass 37, count 2 2006.257.08:29:32.07#ibcon#about to read 6, iclass 37, count 2 2006.257.08:29:32.07#ibcon#read 6, iclass 37, count 2 2006.257.08:29:32.07#ibcon#end of sib2, iclass 37, count 2 2006.257.08:29:32.07#ibcon#*after write, iclass 37, count 2 2006.257.08:29:32.07#ibcon#*before return 0, iclass 37, count 2 2006.257.08:29:32.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:32.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:32.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.08:29:32.07#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:32.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:32.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:32.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:32.19#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:29:32.19#ibcon#first serial, iclass 37, count 0 2006.257.08:29:32.19#ibcon#enter sib2, iclass 37, count 0 2006.257.08:29:32.19#ibcon#flushed, iclass 37, count 0 2006.257.08:29:32.19#ibcon#about to write, iclass 37, count 0 2006.257.08:29:32.19#ibcon#wrote, iclass 37, count 0 2006.257.08:29:32.19#ibcon#about to read 3, iclass 37, count 0 2006.257.08:29:32.21#ibcon#read 3, iclass 37, count 0 2006.257.08:29:32.21#ibcon#about to read 4, iclass 37, count 0 2006.257.08:29:32.21#ibcon#read 4, iclass 37, count 0 2006.257.08:29:32.21#ibcon#about to read 5, iclass 37, count 0 2006.257.08:29:32.21#ibcon#read 5, iclass 37, count 0 2006.257.08:29:32.21#ibcon#about to read 6, iclass 37, count 0 2006.257.08:29:32.21#ibcon#read 6, iclass 37, count 0 2006.257.08:29:32.21#ibcon#end of sib2, iclass 37, count 0 2006.257.08:29:32.21#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:29:32.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:29:32.21#ibcon#[25=USB\r\n] 2006.257.08:29:32.21#ibcon#*before write, iclass 37, count 0 2006.257.08:29:32.21#ibcon#enter sib2, iclass 37, count 0 2006.257.08:29:32.21#ibcon#flushed, iclass 37, count 0 2006.257.08:29:32.21#ibcon#about to write, iclass 37, count 0 2006.257.08:29:32.21#ibcon#wrote, iclass 37, count 0 2006.257.08:29:32.21#ibcon#about to read 3, iclass 37, count 0 2006.257.08:29:32.24#ibcon#read 3, iclass 37, count 0 2006.257.08:29:32.24#ibcon#about to read 4, iclass 37, count 0 2006.257.08:29:32.24#ibcon#read 4, iclass 37, count 0 2006.257.08:29:32.24#ibcon#about to read 5, iclass 37, count 0 2006.257.08:29:32.24#ibcon#read 5, iclass 37, count 0 2006.257.08:29:32.24#ibcon#about to read 6, iclass 37, count 0 2006.257.08:29:32.24#ibcon#read 6, iclass 37, count 0 2006.257.08:29:32.24#ibcon#end of sib2, iclass 37, count 0 2006.257.08:29:32.24#ibcon#*after write, iclass 37, count 0 2006.257.08:29:32.24#ibcon#*before return 0, iclass 37, count 0 2006.257.08:29:32.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:32.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:32.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:29:32.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:29:32.24$vck44/valo=7,864.99 2006.257.08:29:32.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.08:29:32.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.08:29:32.24#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:32.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:32.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:32.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:32.24#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:29:32.24#ibcon#first serial, iclass 39, count 0 2006.257.08:29:32.24#ibcon#enter sib2, iclass 39, count 0 2006.257.08:29:32.24#ibcon#flushed, iclass 39, count 0 2006.257.08:29:32.24#ibcon#about to write, iclass 39, count 0 2006.257.08:29:32.24#ibcon#wrote, iclass 39, count 0 2006.257.08:29:32.24#ibcon#about to read 3, iclass 39, count 0 2006.257.08:29:32.26#ibcon#read 3, iclass 39, count 0 2006.257.08:29:32.26#ibcon#about to read 4, iclass 39, count 0 2006.257.08:29:32.26#ibcon#read 4, iclass 39, count 0 2006.257.08:29:32.26#ibcon#about to read 5, iclass 39, count 0 2006.257.08:29:32.26#ibcon#read 5, iclass 39, count 0 2006.257.08:29:32.26#ibcon#about to read 6, iclass 39, count 0 2006.257.08:29:32.26#ibcon#read 6, iclass 39, count 0 2006.257.08:29:32.26#ibcon#end of sib2, iclass 39, count 0 2006.257.08:29:32.26#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:29:32.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:29:32.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:29:32.26#ibcon#*before write, iclass 39, count 0 2006.257.08:29:32.26#ibcon#enter sib2, iclass 39, count 0 2006.257.08:29:32.26#ibcon#flushed, iclass 39, count 0 2006.257.08:29:32.26#ibcon#about to write, iclass 39, count 0 2006.257.08:29:32.26#ibcon#wrote, iclass 39, count 0 2006.257.08:29:32.26#ibcon#about to read 3, iclass 39, count 0 2006.257.08:29:32.30#ibcon#read 3, iclass 39, count 0 2006.257.08:29:32.30#ibcon#about to read 4, iclass 39, count 0 2006.257.08:29:32.30#ibcon#read 4, iclass 39, count 0 2006.257.08:29:32.30#ibcon#about to read 5, iclass 39, count 0 2006.257.08:29:32.30#ibcon#read 5, iclass 39, count 0 2006.257.08:29:32.30#ibcon#about to read 6, iclass 39, count 0 2006.257.08:29:32.30#ibcon#read 6, iclass 39, count 0 2006.257.08:29:32.30#ibcon#end of sib2, iclass 39, count 0 2006.257.08:29:32.30#ibcon#*after write, iclass 39, count 0 2006.257.08:29:32.30#ibcon#*before return 0, iclass 39, count 0 2006.257.08:29:32.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:32.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:32.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:29:32.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:29:32.30$vck44/va=7,4 2006.257.08:29:32.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.08:29:32.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.08:29:32.30#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:32.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:29:32.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:29:32.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:29:32.36#ibcon#enter wrdev, iclass 3, count 2 2006.257.08:29:32.36#ibcon#first serial, iclass 3, count 2 2006.257.08:29:32.36#ibcon#enter sib2, iclass 3, count 2 2006.257.08:29:32.36#ibcon#flushed, iclass 3, count 2 2006.257.08:29:32.36#ibcon#about to write, iclass 3, count 2 2006.257.08:29:32.36#ibcon#wrote, iclass 3, count 2 2006.257.08:29:32.36#ibcon#about to read 3, iclass 3, count 2 2006.257.08:29:32.38#ibcon#read 3, iclass 3, count 2 2006.257.08:29:32.38#ibcon#about to read 4, iclass 3, count 2 2006.257.08:29:32.38#ibcon#read 4, iclass 3, count 2 2006.257.08:29:32.38#ibcon#about to read 5, iclass 3, count 2 2006.257.08:29:32.38#ibcon#read 5, iclass 3, count 2 2006.257.08:29:32.38#ibcon#about to read 6, iclass 3, count 2 2006.257.08:29:32.38#ibcon#read 6, iclass 3, count 2 2006.257.08:29:32.38#ibcon#end of sib2, iclass 3, count 2 2006.257.08:29:32.38#ibcon#*mode == 0, iclass 3, count 2 2006.257.08:29:32.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.08:29:32.38#ibcon#[25=AT07-04\r\n] 2006.257.08:29:32.38#ibcon#*before write, iclass 3, count 2 2006.257.08:29:32.38#ibcon#enter sib2, iclass 3, count 2 2006.257.08:29:32.38#ibcon#flushed, iclass 3, count 2 2006.257.08:29:32.38#ibcon#about to write, iclass 3, count 2 2006.257.08:29:32.38#ibcon#wrote, iclass 3, count 2 2006.257.08:29:32.38#ibcon#about to read 3, iclass 3, count 2 2006.257.08:29:32.41#ibcon#read 3, iclass 3, count 2 2006.257.08:29:32.41#ibcon#about to read 4, iclass 3, count 2 2006.257.08:29:32.41#ibcon#read 4, iclass 3, count 2 2006.257.08:29:32.41#ibcon#about to read 5, iclass 3, count 2 2006.257.08:29:32.41#ibcon#read 5, iclass 3, count 2 2006.257.08:29:32.41#ibcon#about to read 6, iclass 3, count 2 2006.257.08:29:32.41#ibcon#read 6, iclass 3, count 2 2006.257.08:29:32.41#ibcon#end of sib2, iclass 3, count 2 2006.257.08:29:32.41#ibcon#*after write, iclass 3, count 2 2006.257.08:29:32.41#ibcon#*before return 0, iclass 3, count 2 2006.257.08:29:32.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:29:32.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:29:32.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.08:29:32.41#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:32.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:29:32.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:29:32.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:29:32.53#ibcon#enter wrdev, iclass 3, count 0 2006.257.08:29:32.53#ibcon#first serial, iclass 3, count 0 2006.257.08:29:32.53#ibcon#enter sib2, iclass 3, count 0 2006.257.08:29:32.53#ibcon#flushed, iclass 3, count 0 2006.257.08:29:32.53#ibcon#about to write, iclass 3, count 0 2006.257.08:29:32.53#ibcon#wrote, iclass 3, count 0 2006.257.08:29:32.53#ibcon#about to read 3, iclass 3, count 0 2006.257.08:29:32.55#ibcon#read 3, iclass 3, count 0 2006.257.08:29:32.55#ibcon#about to read 4, iclass 3, count 0 2006.257.08:29:32.55#ibcon#read 4, iclass 3, count 0 2006.257.08:29:32.55#ibcon#about to read 5, iclass 3, count 0 2006.257.08:29:32.55#ibcon#read 5, iclass 3, count 0 2006.257.08:29:32.55#ibcon#about to read 6, iclass 3, count 0 2006.257.08:29:32.55#ibcon#read 6, iclass 3, count 0 2006.257.08:29:32.55#ibcon#end of sib2, iclass 3, count 0 2006.257.08:29:32.55#ibcon#*mode == 0, iclass 3, count 0 2006.257.08:29:32.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.08:29:32.55#ibcon#[25=USB\r\n] 2006.257.08:29:32.55#ibcon#*before write, iclass 3, count 0 2006.257.08:29:32.55#ibcon#enter sib2, iclass 3, count 0 2006.257.08:29:32.55#ibcon#flushed, iclass 3, count 0 2006.257.08:29:32.55#ibcon#about to write, iclass 3, count 0 2006.257.08:29:32.55#ibcon#wrote, iclass 3, count 0 2006.257.08:29:32.55#ibcon#about to read 3, iclass 3, count 0 2006.257.08:29:32.58#ibcon#read 3, iclass 3, count 0 2006.257.08:29:32.58#ibcon#about to read 4, iclass 3, count 0 2006.257.08:29:32.58#ibcon#read 4, iclass 3, count 0 2006.257.08:29:32.58#ibcon#about to read 5, iclass 3, count 0 2006.257.08:29:32.58#ibcon#read 5, iclass 3, count 0 2006.257.08:29:32.58#ibcon#about to read 6, iclass 3, count 0 2006.257.08:29:32.58#ibcon#read 6, iclass 3, count 0 2006.257.08:29:32.58#ibcon#end of sib2, iclass 3, count 0 2006.257.08:29:32.58#ibcon#*after write, iclass 3, count 0 2006.257.08:29:32.58#ibcon#*before return 0, iclass 3, count 0 2006.257.08:29:32.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:29:32.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:29:32.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.08:29:32.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.08:29:32.58$vck44/valo=8,884.99 2006.257.08:29:32.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.08:29:32.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.08:29:32.58#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:32.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:29:32.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:29:32.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:29:32.58#ibcon#enter wrdev, iclass 5, count 0 2006.257.08:29:32.58#ibcon#first serial, iclass 5, count 0 2006.257.08:29:32.58#ibcon#enter sib2, iclass 5, count 0 2006.257.08:29:32.58#ibcon#flushed, iclass 5, count 0 2006.257.08:29:32.58#ibcon#about to write, iclass 5, count 0 2006.257.08:29:32.58#ibcon#wrote, iclass 5, count 0 2006.257.08:29:32.58#ibcon#about to read 3, iclass 5, count 0 2006.257.08:29:32.60#ibcon#read 3, iclass 5, count 0 2006.257.08:29:32.60#ibcon#about to read 4, iclass 5, count 0 2006.257.08:29:32.60#ibcon#read 4, iclass 5, count 0 2006.257.08:29:32.60#ibcon#about to read 5, iclass 5, count 0 2006.257.08:29:32.60#ibcon#read 5, iclass 5, count 0 2006.257.08:29:32.60#ibcon#about to read 6, iclass 5, count 0 2006.257.08:29:32.60#ibcon#read 6, iclass 5, count 0 2006.257.08:29:32.60#ibcon#end of sib2, iclass 5, count 0 2006.257.08:29:32.60#ibcon#*mode == 0, iclass 5, count 0 2006.257.08:29:32.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.08:29:32.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:29:32.60#ibcon#*before write, iclass 5, count 0 2006.257.08:29:32.60#ibcon#enter sib2, iclass 5, count 0 2006.257.08:29:32.60#ibcon#flushed, iclass 5, count 0 2006.257.08:29:32.60#ibcon#about to write, iclass 5, count 0 2006.257.08:29:32.60#ibcon#wrote, iclass 5, count 0 2006.257.08:29:32.60#ibcon#about to read 3, iclass 5, count 0 2006.257.08:29:32.64#ibcon#read 3, iclass 5, count 0 2006.257.08:29:32.64#ibcon#about to read 4, iclass 5, count 0 2006.257.08:29:32.64#ibcon#read 4, iclass 5, count 0 2006.257.08:29:32.64#ibcon#about to read 5, iclass 5, count 0 2006.257.08:29:32.64#ibcon#read 5, iclass 5, count 0 2006.257.08:29:32.64#ibcon#about to read 6, iclass 5, count 0 2006.257.08:29:32.64#ibcon#read 6, iclass 5, count 0 2006.257.08:29:32.64#ibcon#end of sib2, iclass 5, count 0 2006.257.08:29:32.64#ibcon#*after write, iclass 5, count 0 2006.257.08:29:32.64#ibcon#*before return 0, iclass 5, count 0 2006.257.08:29:32.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:29:32.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:29:32.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.08:29:32.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.08:29:32.64$vck44/va=8,4 2006.257.08:29:32.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.08:29:32.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.08:29:32.64#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:32.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:29:32.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:29:32.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:29:32.70#ibcon#enter wrdev, iclass 7, count 2 2006.257.08:29:32.70#ibcon#first serial, iclass 7, count 2 2006.257.08:29:32.70#ibcon#enter sib2, iclass 7, count 2 2006.257.08:29:32.70#ibcon#flushed, iclass 7, count 2 2006.257.08:29:32.70#ibcon#about to write, iclass 7, count 2 2006.257.08:29:32.70#ibcon#wrote, iclass 7, count 2 2006.257.08:29:32.70#ibcon#about to read 3, iclass 7, count 2 2006.257.08:29:32.72#ibcon#read 3, iclass 7, count 2 2006.257.08:29:32.72#ibcon#about to read 4, iclass 7, count 2 2006.257.08:29:32.72#ibcon#read 4, iclass 7, count 2 2006.257.08:29:32.72#ibcon#about to read 5, iclass 7, count 2 2006.257.08:29:32.72#ibcon#read 5, iclass 7, count 2 2006.257.08:29:32.72#ibcon#about to read 6, iclass 7, count 2 2006.257.08:29:32.72#ibcon#read 6, iclass 7, count 2 2006.257.08:29:32.72#ibcon#end of sib2, iclass 7, count 2 2006.257.08:29:32.72#ibcon#*mode == 0, iclass 7, count 2 2006.257.08:29:32.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.08:29:32.72#ibcon#[25=AT08-04\r\n] 2006.257.08:29:32.72#ibcon#*before write, iclass 7, count 2 2006.257.08:29:32.72#ibcon#enter sib2, iclass 7, count 2 2006.257.08:29:32.72#ibcon#flushed, iclass 7, count 2 2006.257.08:29:32.72#ibcon#about to write, iclass 7, count 2 2006.257.08:29:32.72#ibcon#wrote, iclass 7, count 2 2006.257.08:29:32.72#ibcon#about to read 3, iclass 7, count 2 2006.257.08:29:32.75#ibcon#read 3, iclass 7, count 2 2006.257.08:29:32.75#ibcon#about to read 4, iclass 7, count 2 2006.257.08:29:32.75#ibcon#read 4, iclass 7, count 2 2006.257.08:29:32.75#ibcon#about to read 5, iclass 7, count 2 2006.257.08:29:32.75#ibcon#read 5, iclass 7, count 2 2006.257.08:29:32.75#ibcon#about to read 6, iclass 7, count 2 2006.257.08:29:32.75#ibcon#read 6, iclass 7, count 2 2006.257.08:29:32.75#ibcon#end of sib2, iclass 7, count 2 2006.257.08:29:32.75#ibcon#*after write, iclass 7, count 2 2006.257.08:29:32.75#ibcon#*before return 0, iclass 7, count 2 2006.257.08:29:32.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:29:32.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:29:32.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.08:29:32.75#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:32.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:29:32.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:29:32.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:29:32.87#ibcon#enter wrdev, iclass 7, count 0 2006.257.08:29:32.87#ibcon#first serial, iclass 7, count 0 2006.257.08:29:32.87#ibcon#enter sib2, iclass 7, count 0 2006.257.08:29:32.87#ibcon#flushed, iclass 7, count 0 2006.257.08:29:32.87#ibcon#about to write, iclass 7, count 0 2006.257.08:29:32.87#ibcon#wrote, iclass 7, count 0 2006.257.08:29:32.87#ibcon#about to read 3, iclass 7, count 0 2006.257.08:29:32.89#ibcon#read 3, iclass 7, count 0 2006.257.08:29:32.89#ibcon#about to read 4, iclass 7, count 0 2006.257.08:29:32.89#ibcon#read 4, iclass 7, count 0 2006.257.08:29:32.89#ibcon#about to read 5, iclass 7, count 0 2006.257.08:29:32.89#ibcon#read 5, iclass 7, count 0 2006.257.08:29:32.89#ibcon#about to read 6, iclass 7, count 0 2006.257.08:29:32.89#ibcon#read 6, iclass 7, count 0 2006.257.08:29:32.89#ibcon#end of sib2, iclass 7, count 0 2006.257.08:29:32.89#ibcon#*mode == 0, iclass 7, count 0 2006.257.08:29:32.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.08:29:32.89#ibcon#[25=USB\r\n] 2006.257.08:29:32.89#ibcon#*before write, iclass 7, count 0 2006.257.08:29:32.89#ibcon#enter sib2, iclass 7, count 0 2006.257.08:29:32.89#ibcon#flushed, iclass 7, count 0 2006.257.08:29:32.89#ibcon#about to write, iclass 7, count 0 2006.257.08:29:32.89#ibcon#wrote, iclass 7, count 0 2006.257.08:29:32.89#ibcon#about to read 3, iclass 7, count 0 2006.257.08:29:32.92#ibcon#read 3, iclass 7, count 0 2006.257.08:29:32.92#ibcon#about to read 4, iclass 7, count 0 2006.257.08:29:32.92#ibcon#read 4, iclass 7, count 0 2006.257.08:29:32.92#ibcon#about to read 5, iclass 7, count 0 2006.257.08:29:32.92#ibcon#read 5, iclass 7, count 0 2006.257.08:29:32.92#ibcon#about to read 6, iclass 7, count 0 2006.257.08:29:32.92#ibcon#read 6, iclass 7, count 0 2006.257.08:29:32.92#ibcon#end of sib2, iclass 7, count 0 2006.257.08:29:32.92#ibcon#*after write, iclass 7, count 0 2006.257.08:29:32.92#ibcon#*before return 0, iclass 7, count 0 2006.257.08:29:32.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:29:32.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:29:32.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.08:29:32.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.08:29:32.92$vck44/vblo=1,629.99 2006.257.08:29:32.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.08:29:32.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.08:29:32.92#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:32.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:32.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:32.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:32.92#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:29:32.92#ibcon#first serial, iclass 11, count 0 2006.257.08:29:32.92#ibcon#enter sib2, iclass 11, count 0 2006.257.08:29:32.92#ibcon#flushed, iclass 11, count 0 2006.257.08:29:32.92#ibcon#about to write, iclass 11, count 0 2006.257.08:29:32.92#ibcon#wrote, iclass 11, count 0 2006.257.08:29:32.92#ibcon#about to read 3, iclass 11, count 0 2006.257.08:29:32.94#ibcon#read 3, iclass 11, count 0 2006.257.08:29:32.94#ibcon#about to read 4, iclass 11, count 0 2006.257.08:29:32.94#ibcon#read 4, iclass 11, count 0 2006.257.08:29:32.94#ibcon#about to read 5, iclass 11, count 0 2006.257.08:29:32.94#ibcon#read 5, iclass 11, count 0 2006.257.08:29:32.94#ibcon#about to read 6, iclass 11, count 0 2006.257.08:29:32.94#ibcon#read 6, iclass 11, count 0 2006.257.08:29:32.94#ibcon#end of sib2, iclass 11, count 0 2006.257.08:29:32.94#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:29:32.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:29:32.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:29:32.94#ibcon#*before write, iclass 11, count 0 2006.257.08:29:32.94#ibcon#enter sib2, iclass 11, count 0 2006.257.08:29:32.94#ibcon#flushed, iclass 11, count 0 2006.257.08:29:32.94#ibcon#about to write, iclass 11, count 0 2006.257.08:29:32.94#ibcon#wrote, iclass 11, count 0 2006.257.08:29:32.94#ibcon#about to read 3, iclass 11, count 0 2006.257.08:29:32.98#ibcon#read 3, iclass 11, count 0 2006.257.08:29:32.98#ibcon#about to read 4, iclass 11, count 0 2006.257.08:29:32.98#ibcon#read 4, iclass 11, count 0 2006.257.08:29:32.98#ibcon#about to read 5, iclass 11, count 0 2006.257.08:29:32.98#ibcon#read 5, iclass 11, count 0 2006.257.08:29:32.98#ibcon#about to read 6, iclass 11, count 0 2006.257.08:29:32.98#ibcon#read 6, iclass 11, count 0 2006.257.08:29:32.98#ibcon#end of sib2, iclass 11, count 0 2006.257.08:29:32.98#ibcon#*after write, iclass 11, count 0 2006.257.08:29:32.98#ibcon#*before return 0, iclass 11, count 0 2006.257.08:29:32.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:32.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:32.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:29:32.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:29:32.98$vck44/vb=1,4 2006.257.08:29:32.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.08:29:32.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.08:29:32.98#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:32.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:29:32.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:29:32.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:29:32.98#ibcon#enter wrdev, iclass 13, count 2 2006.257.08:29:32.98#ibcon#first serial, iclass 13, count 2 2006.257.08:29:32.98#ibcon#enter sib2, iclass 13, count 2 2006.257.08:29:32.98#ibcon#flushed, iclass 13, count 2 2006.257.08:29:32.98#ibcon#about to write, iclass 13, count 2 2006.257.08:29:32.98#ibcon#wrote, iclass 13, count 2 2006.257.08:29:32.98#ibcon#about to read 3, iclass 13, count 2 2006.257.08:29:33.00#ibcon#read 3, iclass 13, count 2 2006.257.08:29:33.00#ibcon#about to read 4, iclass 13, count 2 2006.257.08:29:33.00#ibcon#read 4, iclass 13, count 2 2006.257.08:29:33.00#ibcon#about to read 5, iclass 13, count 2 2006.257.08:29:33.00#ibcon#read 5, iclass 13, count 2 2006.257.08:29:33.00#ibcon#about to read 6, iclass 13, count 2 2006.257.08:29:33.00#ibcon#read 6, iclass 13, count 2 2006.257.08:29:33.00#ibcon#end of sib2, iclass 13, count 2 2006.257.08:29:33.00#ibcon#*mode == 0, iclass 13, count 2 2006.257.08:29:33.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.08:29:33.00#ibcon#[27=AT01-04\r\n] 2006.257.08:29:33.00#ibcon#*before write, iclass 13, count 2 2006.257.08:29:33.00#ibcon#enter sib2, iclass 13, count 2 2006.257.08:29:33.00#ibcon#flushed, iclass 13, count 2 2006.257.08:29:33.00#ibcon#about to write, iclass 13, count 2 2006.257.08:29:33.00#ibcon#wrote, iclass 13, count 2 2006.257.08:29:33.00#ibcon#about to read 3, iclass 13, count 2 2006.257.08:29:33.03#ibcon#read 3, iclass 13, count 2 2006.257.08:29:33.03#ibcon#about to read 4, iclass 13, count 2 2006.257.08:29:33.03#ibcon#read 4, iclass 13, count 2 2006.257.08:29:33.03#ibcon#about to read 5, iclass 13, count 2 2006.257.08:29:33.03#ibcon#read 5, iclass 13, count 2 2006.257.08:29:33.03#ibcon#about to read 6, iclass 13, count 2 2006.257.08:29:33.03#ibcon#read 6, iclass 13, count 2 2006.257.08:29:33.03#ibcon#end of sib2, iclass 13, count 2 2006.257.08:29:33.03#ibcon#*after write, iclass 13, count 2 2006.257.08:29:33.03#ibcon#*before return 0, iclass 13, count 2 2006.257.08:29:33.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:29:33.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:29:33.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.08:29:33.03#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:33.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:29:33.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:29:33.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:29:33.15#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:29:33.15#ibcon#first serial, iclass 13, count 0 2006.257.08:29:33.15#ibcon#enter sib2, iclass 13, count 0 2006.257.08:29:33.15#ibcon#flushed, iclass 13, count 0 2006.257.08:29:33.15#ibcon#about to write, iclass 13, count 0 2006.257.08:29:33.15#ibcon#wrote, iclass 13, count 0 2006.257.08:29:33.15#ibcon#about to read 3, iclass 13, count 0 2006.257.08:29:33.17#ibcon#read 3, iclass 13, count 0 2006.257.08:29:33.17#ibcon#about to read 4, iclass 13, count 0 2006.257.08:29:33.17#ibcon#read 4, iclass 13, count 0 2006.257.08:29:33.17#ibcon#about to read 5, iclass 13, count 0 2006.257.08:29:33.17#ibcon#read 5, iclass 13, count 0 2006.257.08:29:33.17#ibcon#about to read 6, iclass 13, count 0 2006.257.08:29:33.17#ibcon#read 6, iclass 13, count 0 2006.257.08:29:33.17#ibcon#end of sib2, iclass 13, count 0 2006.257.08:29:33.17#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:29:33.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:29:33.17#ibcon#[27=USB\r\n] 2006.257.08:29:33.17#ibcon#*before write, iclass 13, count 0 2006.257.08:29:33.17#ibcon#enter sib2, iclass 13, count 0 2006.257.08:29:33.17#ibcon#flushed, iclass 13, count 0 2006.257.08:29:33.17#ibcon#about to write, iclass 13, count 0 2006.257.08:29:33.17#ibcon#wrote, iclass 13, count 0 2006.257.08:29:33.17#ibcon#about to read 3, iclass 13, count 0 2006.257.08:29:33.20#ibcon#read 3, iclass 13, count 0 2006.257.08:29:33.20#ibcon#about to read 4, iclass 13, count 0 2006.257.08:29:33.20#ibcon#read 4, iclass 13, count 0 2006.257.08:29:33.20#ibcon#about to read 5, iclass 13, count 0 2006.257.08:29:33.20#ibcon#read 5, iclass 13, count 0 2006.257.08:29:33.20#ibcon#about to read 6, iclass 13, count 0 2006.257.08:29:33.20#ibcon#read 6, iclass 13, count 0 2006.257.08:29:33.20#ibcon#end of sib2, iclass 13, count 0 2006.257.08:29:33.20#ibcon#*after write, iclass 13, count 0 2006.257.08:29:33.20#ibcon#*before return 0, iclass 13, count 0 2006.257.08:29:33.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:29:33.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:29:33.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:29:33.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:29:33.20$vck44/vblo=2,634.99 2006.257.08:29:33.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.08:29:33.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.08:29:33.20#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:33.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:33.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:33.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:33.20#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:29:33.20#ibcon#first serial, iclass 15, count 0 2006.257.08:29:33.20#ibcon#enter sib2, iclass 15, count 0 2006.257.08:29:33.20#ibcon#flushed, iclass 15, count 0 2006.257.08:29:33.20#ibcon#about to write, iclass 15, count 0 2006.257.08:29:33.20#ibcon#wrote, iclass 15, count 0 2006.257.08:29:33.20#ibcon#about to read 3, iclass 15, count 0 2006.257.08:29:33.22#ibcon#read 3, iclass 15, count 0 2006.257.08:29:33.22#ibcon#about to read 4, iclass 15, count 0 2006.257.08:29:33.22#ibcon#read 4, iclass 15, count 0 2006.257.08:29:33.22#ibcon#about to read 5, iclass 15, count 0 2006.257.08:29:33.22#ibcon#read 5, iclass 15, count 0 2006.257.08:29:33.22#ibcon#about to read 6, iclass 15, count 0 2006.257.08:29:33.22#ibcon#read 6, iclass 15, count 0 2006.257.08:29:33.22#ibcon#end of sib2, iclass 15, count 0 2006.257.08:29:33.22#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:29:33.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:29:33.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:29:33.22#ibcon#*before write, iclass 15, count 0 2006.257.08:29:33.22#ibcon#enter sib2, iclass 15, count 0 2006.257.08:29:33.22#ibcon#flushed, iclass 15, count 0 2006.257.08:29:33.22#ibcon#about to write, iclass 15, count 0 2006.257.08:29:33.22#ibcon#wrote, iclass 15, count 0 2006.257.08:29:33.22#ibcon#about to read 3, iclass 15, count 0 2006.257.08:29:33.26#ibcon#read 3, iclass 15, count 0 2006.257.08:29:33.26#ibcon#about to read 4, iclass 15, count 0 2006.257.08:29:33.26#ibcon#read 4, iclass 15, count 0 2006.257.08:29:33.26#ibcon#about to read 5, iclass 15, count 0 2006.257.08:29:33.26#ibcon#read 5, iclass 15, count 0 2006.257.08:29:33.26#ibcon#about to read 6, iclass 15, count 0 2006.257.08:29:33.26#ibcon#read 6, iclass 15, count 0 2006.257.08:29:33.26#ibcon#end of sib2, iclass 15, count 0 2006.257.08:29:33.26#ibcon#*after write, iclass 15, count 0 2006.257.08:29:33.26#ibcon#*before return 0, iclass 15, count 0 2006.257.08:29:33.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:33.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:29:33.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:29:33.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:29:33.26$vck44/vb=2,5 2006.257.08:29:33.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.08:29:33.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.08:29:33.26#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:33.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:33.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:33.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:33.32#ibcon#enter wrdev, iclass 17, count 2 2006.257.08:29:33.32#ibcon#first serial, iclass 17, count 2 2006.257.08:29:33.32#ibcon#enter sib2, iclass 17, count 2 2006.257.08:29:33.32#ibcon#flushed, iclass 17, count 2 2006.257.08:29:33.32#ibcon#about to write, iclass 17, count 2 2006.257.08:29:33.32#ibcon#wrote, iclass 17, count 2 2006.257.08:29:33.32#ibcon#about to read 3, iclass 17, count 2 2006.257.08:29:33.34#ibcon#read 3, iclass 17, count 2 2006.257.08:29:33.34#ibcon#about to read 4, iclass 17, count 2 2006.257.08:29:33.34#ibcon#read 4, iclass 17, count 2 2006.257.08:29:33.34#ibcon#about to read 5, iclass 17, count 2 2006.257.08:29:33.34#ibcon#read 5, iclass 17, count 2 2006.257.08:29:33.34#ibcon#about to read 6, iclass 17, count 2 2006.257.08:29:33.34#ibcon#read 6, iclass 17, count 2 2006.257.08:29:33.34#ibcon#end of sib2, iclass 17, count 2 2006.257.08:29:33.34#ibcon#*mode == 0, iclass 17, count 2 2006.257.08:29:33.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.08:29:33.34#ibcon#[27=AT02-05\r\n] 2006.257.08:29:33.34#ibcon#*before write, iclass 17, count 2 2006.257.08:29:33.34#ibcon#enter sib2, iclass 17, count 2 2006.257.08:29:33.34#ibcon#flushed, iclass 17, count 2 2006.257.08:29:33.34#ibcon#about to write, iclass 17, count 2 2006.257.08:29:33.34#ibcon#wrote, iclass 17, count 2 2006.257.08:29:33.34#ibcon#about to read 3, iclass 17, count 2 2006.257.08:29:33.37#ibcon#read 3, iclass 17, count 2 2006.257.08:29:33.37#ibcon#about to read 4, iclass 17, count 2 2006.257.08:29:33.37#ibcon#read 4, iclass 17, count 2 2006.257.08:29:33.37#ibcon#about to read 5, iclass 17, count 2 2006.257.08:29:33.37#ibcon#read 5, iclass 17, count 2 2006.257.08:29:33.37#ibcon#about to read 6, iclass 17, count 2 2006.257.08:29:33.37#ibcon#read 6, iclass 17, count 2 2006.257.08:29:33.37#ibcon#end of sib2, iclass 17, count 2 2006.257.08:29:33.37#ibcon#*after write, iclass 17, count 2 2006.257.08:29:33.37#ibcon#*before return 0, iclass 17, count 2 2006.257.08:29:33.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:33.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:29:33.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.08:29:33.37#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:33.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:33.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:33.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:33.49#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:29:33.49#ibcon#first serial, iclass 17, count 0 2006.257.08:29:33.49#ibcon#enter sib2, iclass 17, count 0 2006.257.08:29:33.49#ibcon#flushed, iclass 17, count 0 2006.257.08:29:33.49#ibcon#about to write, iclass 17, count 0 2006.257.08:29:33.49#ibcon#wrote, iclass 17, count 0 2006.257.08:29:33.49#ibcon#about to read 3, iclass 17, count 0 2006.257.08:29:33.51#ibcon#read 3, iclass 17, count 0 2006.257.08:29:33.51#ibcon#about to read 4, iclass 17, count 0 2006.257.08:29:33.51#ibcon#read 4, iclass 17, count 0 2006.257.08:29:33.51#ibcon#about to read 5, iclass 17, count 0 2006.257.08:29:33.51#ibcon#read 5, iclass 17, count 0 2006.257.08:29:33.51#ibcon#about to read 6, iclass 17, count 0 2006.257.08:29:33.51#ibcon#read 6, iclass 17, count 0 2006.257.08:29:33.51#ibcon#end of sib2, iclass 17, count 0 2006.257.08:29:33.51#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:29:33.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:29:33.51#ibcon#[27=USB\r\n] 2006.257.08:29:33.51#ibcon#*before write, iclass 17, count 0 2006.257.08:29:33.51#ibcon#enter sib2, iclass 17, count 0 2006.257.08:29:33.51#ibcon#flushed, iclass 17, count 0 2006.257.08:29:33.51#ibcon#about to write, iclass 17, count 0 2006.257.08:29:33.51#ibcon#wrote, iclass 17, count 0 2006.257.08:29:33.51#ibcon#about to read 3, iclass 17, count 0 2006.257.08:29:33.54#ibcon#read 3, iclass 17, count 0 2006.257.08:29:33.54#ibcon#about to read 4, iclass 17, count 0 2006.257.08:29:33.54#ibcon#read 4, iclass 17, count 0 2006.257.08:29:33.54#ibcon#about to read 5, iclass 17, count 0 2006.257.08:29:33.54#ibcon#read 5, iclass 17, count 0 2006.257.08:29:33.54#ibcon#about to read 6, iclass 17, count 0 2006.257.08:29:33.54#ibcon#read 6, iclass 17, count 0 2006.257.08:29:33.54#ibcon#end of sib2, iclass 17, count 0 2006.257.08:29:33.54#ibcon#*after write, iclass 17, count 0 2006.257.08:29:33.54#ibcon#*before return 0, iclass 17, count 0 2006.257.08:29:33.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:33.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:29:33.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:29:33.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:29:33.54$vck44/vblo=3,649.99 2006.257.08:29:33.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.08:29:33.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.08:29:33.54#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:33.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:33.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:33.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:33.54#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:29:33.54#ibcon#first serial, iclass 19, count 0 2006.257.08:29:33.54#ibcon#enter sib2, iclass 19, count 0 2006.257.08:29:33.54#ibcon#flushed, iclass 19, count 0 2006.257.08:29:33.54#ibcon#about to write, iclass 19, count 0 2006.257.08:29:33.54#ibcon#wrote, iclass 19, count 0 2006.257.08:29:33.54#ibcon#about to read 3, iclass 19, count 0 2006.257.08:29:33.56#ibcon#read 3, iclass 19, count 0 2006.257.08:29:33.56#ibcon#about to read 4, iclass 19, count 0 2006.257.08:29:33.56#ibcon#read 4, iclass 19, count 0 2006.257.08:29:33.56#ibcon#about to read 5, iclass 19, count 0 2006.257.08:29:33.56#ibcon#read 5, iclass 19, count 0 2006.257.08:29:33.56#ibcon#about to read 6, iclass 19, count 0 2006.257.08:29:33.56#ibcon#read 6, iclass 19, count 0 2006.257.08:29:33.56#ibcon#end of sib2, iclass 19, count 0 2006.257.08:29:33.56#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:29:33.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:29:33.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:29:33.56#ibcon#*before write, iclass 19, count 0 2006.257.08:29:33.56#ibcon#enter sib2, iclass 19, count 0 2006.257.08:29:33.56#ibcon#flushed, iclass 19, count 0 2006.257.08:29:33.56#ibcon#about to write, iclass 19, count 0 2006.257.08:29:33.56#ibcon#wrote, iclass 19, count 0 2006.257.08:29:33.56#ibcon#about to read 3, iclass 19, count 0 2006.257.08:29:33.60#ibcon#read 3, iclass 19, count 0 2006.257.08:29:33.60#ibcon#about to read 4, iclass 19, count 0 2006.257.08:29:33.60#ibcon#read 4, iclass 19, count 0 2006.257.08:29:33.60#ibcon#about to read 5, iclass 19, count 0 2006.257.08:29:33.60#ibcon#read 5, iclass 19, count 0 2006.257.08:29:33.60#ibcon#about to read 6, iclass 19, count 0 2006.257.08:29:33.60#ibcon#read 6, iclass 19, count 0 2006.257.08:29:33.60#ibcon#end of sib2, iclass 19, count 0 2006.257.08:29:33.60#ibcon#*after write, iclass 19, count 0 2006.257.08:29:33.60#ibcon#*before return 0, iclass 19, count 0 2006.257.08:29:33.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:33.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:29:33.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:29:33.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:29:33.60$vck44/vb=3,4 2006.257.08:29:33.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.08:29:33.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.08:29:33.60#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:33.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:33.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:33.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:33.66#ibcon#enter wrdev, iclass 21, count 2 2006.257.08:29:33.66#ibcon#first serial, iclass 21, count 2 2006.257.08:29:33.66#ibcon#enter sib2, iclass 21, count 2 2006.257.08:29:33.66#ibcon#flushed, iclass 21, count 2 2006.257.08:29:33.66#ibcon#about to write, iclass 21, count 2 2006.257.08:29:33.66#ibcon#wrote, iclass 21, count 2 2006.257.08:29:33.66#ibcon#about to read 3, iclass 21, count 2 2006.257.08:29:33.68#ibcon#read 3, iclass 21, count 2 2006.257.08:29:33.68#ibcon#about to read 4, iclass 21, count 2 2006.257.08:29:33.68#ibcon#read 4, iclass 21, count 2 2006.257.08:29:33.68#ibcon#about to read 5, iclass 21, count 2 2006.257.08:29:33.68#ibcon#read 5, iclass 21, count 2 2006.257.08:29:33.68#ibcon#about to read 6, iclass 21, count 2 2006.257.08:29:33.68#ibcon#read 6, iclass 21, count 2 2006.257.08:29:33.68#ibcon#end of sib2, iclass 21, count 2 2006.257.08:29:33.68#ibcon#*mode == 0, iclass 21, count 2 2006.257.08:29:33.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.08:29:33.68#ibcon#[27=AT03-04\r\n] 2006.257.08:29:33.68#ibcon#*before write, iclass 21, count 2 2006.257.08:29:33.68#ibcon#enter sib2, iclass 21, count 2 2006.257.08:29:33.68#ibcon#flushed, iclass 21, count 2 2006.257.08:29:33.68#ibcon#about to write, iclass 21, count 2 2006.257.08:29:33.68#ibcon#wrote, iclass 21, count 2 2006.257.08:29:33.68#ibcon#about to read 3, iclass 21, count 2 2006.257.08:29:33.71#ibcon#read 3, iclass 21, count 2 2006.257.08:29:33.71#ibcon#about to read 4, iclass 21, count 2 2006.257.08:29:33.71#ibcon#read 4, iclass 21, count 2 2006.257.08:29:33.71#ibcon#about to read 5, iclass 21, count 2 2006.257.08:29:33.71#ibcon#read 5, iclass 21, count 2 2006.257.08:29:33.71#ibcon#about to read 6, iclass 21, count 2 2006.257.08:29:33.71#ibcon#read 6, iclass 21, count 2 2006.257.08:29:33.71#ibcon#end of sib2, iclass 21, count 2 2006.257.08:29:33.71#ibcon#*after write, iclass 21, count 2 2006.257.08:29:33.71#ibcon#*before return 0, iclass 21, count 2 2006.257.08:29:33.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:33.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:29:33.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.08:29:33.71#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:33.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:33.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:33.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:33.83#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:29:33.83#ibcon#first serial, iclass 21, count 0 2006.257.08:29:33.83#ibcon#enter sib2, iclass 21, count 0 2006.257.08:29:33.83#ibcon#flushed, iclass 21, count 0 2006.257.08:29:33.83#ibcon#about to write, iclass 21, count 0 2006.257.08:29:33.83#ibcon#wrote, iclass 21, count 0 2006.257.08:29:33.83#ibcon#about to read 3, iclass 21, count 0 2006.257.08:29:33.85#ibcon#read 3, iclass 21, count 0 2006.257.08:29:33.85#ibcon#about to read 4, iclass 21, count 0 2006.257.08:29:33.85#ibcon#read 4, iclass 21, count 0 2006.257.08:29:33.85#ibcon#about to read 5, iclass 21, count 0 2006.257.08:29:33.85#ibcon#read 5, iclass 21, count 0 2006.257.08:29:33.85#ibcon#about to read 6, iclass 21, count 0 2006.257.08:29:33.85#ibcon#read 6, iclass 21, count 0 2006.257.08:29:33.85#ibcon#end of sib2, iclass 21, count 0 2006.257.08:29:33.85#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:29:33.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:29:33.85#ibcon#[27=USB\r\n] 2006.257.08:29:33.85#ibcon#*before write, iclass 21, count 0 2006.257.08:29:33.85#ibcon#enter sib2, iclass 21, count 0 2006.257.08:29:33.85#ibcon#flushed, iclass 21, count 0 2006.257.08:29:33.85#ibcon#about to write, iclass 21, count 0 2006.257.08:29:33.85#ibcon#wrote, iclass 21, count 0 2006.257.08:29:33.85#ibcon#about to read 3, iclass 21, count 0 2006.257.08:29:33.88#ibcon#read 3, iclass 21, count 0 2006.257.08:29:33.88#ibcon#about to read 4, iclass 21, count 0 2006.257.08:29:33.88#ibcon#read 4, iclass 21, count 0 2006.257.08:29:33.88#ibcon#about to read 5, iclass 21, count 0 2006.257.08:29:33.88#ibcon#read 5, iclass 21, count 0 2006.257.08:29:33.88#ibcon#about to read 6, iclass 21, count 0 2006.257.08:29:33.88#ibcon#read 6, iclass 21, count 0 2006.257.08:29:33.88#ibcon#end of sib2, iclass 21, count 0 2006.257.08:29:33.88#ibcon#*after write, iclass 21, count 0 2006.257.08:29:33.88#ibcon#*before return 0, iclass 21, count 0 2006.257.08:29:33.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:33.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:29:33.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:29:33.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:29:33.88$vck44/vblo=4,679.99 2006.257.08:29:33.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.08:29:33.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.08:29:33.88#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:33.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:33.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:33.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:33.88#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:29:33.88#ibcon#first serial, iclass 23, count 0 2006.257.08:29:33.88#ibcon#enter sib2, iclass 23, count 0 2006.257.08:29:33.88#ibcon#flushed, iclass 23, count 0 2006.257.08:29:33.88#ibcon#about to write, iclass 23, count 0 2006.257.08:29:33.88#ibcon#wrote, iclass 23, count 0 2006.257.08:29:33.88#ibcon#about to read 3, iclass 23, count 0 2006.257.08:29:33.90#ibcon#read 3, iclass 23, count 0 2006.257.08:29:33.90#ibcon#about to read 4, iclass 23, count 0 2006.257.08:29:33.90#ibcon#read 4, iclass 23, count 0 2006.257.08:29:33.90#ibcon#about to read 5, iclass 23, count 0 2006.257.08:29:33.90#ibcon#read 5, iclass 23, count 0 2006.257.08:29:33.90#ibcon#about to read 6, iclass 23, count 0 2006.257.08:29:33.90#ibcon#read 6, iclass 23, count 0 2006.257.08:29:33.90#ibcon#end of sib2, iclass 23, count 0 2006.257.08:29:33.90#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:29:33.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:29:33.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:29:33.90#ibcon#*before write, iclass 23, count 0 2006.257.08:29:33.90#ibcon#enter sib2, iclass 23, count 0 2006.257.08:29:33.90#ibcon#flushed, iclass 23, count 0 2006.257.08:29:33.90#ibcon#about to write, iclass 23, count 0 2006.257.08:29:33.90#ibcon#wrote, iclass 23, count 0 2006.257.08:29:33.90#ibcon#about to read 3, iclass 23, count 0 2006.257.08:29:33.94#ibcon#read 3, iclass 23, count 0 2006.257.08:29:33.94#ibcon#about to read 4, iclass 23, count 0 2006.257.08:29:33.94#ibcon#read 4, iclass 23, count 0 2006.257.08:29:33.94#ibcon#about to read 5, iclass 23, count 0 2006.257.08:29:33.94#ibcon#read 5, iclass 23, count 0 2006.257.08:29:33.94#ibcon#about to read 6, iclass 23, count 0 2006.257.08:29:33.94#ibcon#read 6, iclass 23, count 0 2006.257.08:29:33.94#ibcon#end of sib2, iclass 23, count 0 2006.257.08:29:33.94#ibcon#*after write, iclass 23, count 0 2006.257.08:29:33.94#ibcon#*before return 0, iclass 23, count 0 2006.257.08:29:33.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:33.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:29:33.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:29:33.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:29:33.94$vck44/vb=4,5 2006.257.08:29:33.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.08:29:33.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.08:29:33.94#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:33.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:34.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:34.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:34.00#ibcon#enter wrdev, iclass 25, count 2 2006.257.08:29:34.00#ibcon#first serial, iclass 25, count 2 2006.257.08:29:34.00#ibcon#enter sib2, iclass 25, count 2 2006.257.08:29:34.00#ibcon#flushed, iclass 25, count 2 2006.257.08:29:34.00#ibcon#about to write, iclass 25, count 2 2006.257.08:29:34.00#ibcon#wrote, iclass 25, count 2 2006.257.08:29:34.00#ibcon#about to read 3, iclass 25, count 2 2006.257.08:29:34.02#ibcon#read 3, iclass 25, count 2 2006.257.08:29:34.02#ibcon#about to read 4, iclass 25, count 2 2006.257.08:29:34.02#ibcon#read 4, iclass 25, count 2 2006.257.08:29:34.02#ibcon#about to read 5, iclass 25, count 2 2006.257.08:29:34.02#ibcon#read 5, iclass 25, count 2 2006.257.08:29:34.02#ibcon#about to read 6, iclass 25, count 2 2006.257.08:29:34.02#ibcon#read 6, iclass 25, count 2 2006.257.08:29:34.02#ibcon#end of sib2, iclass 25, count 2 2006.257.08:29:34.02#ibcon#*mode == 0, iclass 25, count 2 2006.257.08:29:34.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.08:29:34.02#ibcon#[27=AT04-05\r\n] 2006.257.08:29:34.02#ibcon#*before write, iclass 25, count 2 2006.257.08:29:34.02#ibcon#enter sib2, iclass 25, count 2 2006.257.08:29:34.02#ibcon#flushed, iclass 25, count 2 2006.257.08:29:34.02#ibcon#about to write, iclass 25, count 2 2006.257.08:29:34.02#ibcon#wrote, iclass 25, count 2 2006.257.08:29:34.02#ibcon#about to read 3, iclass 25, count 2 2006.257.08:29:34.05#ibcon#read 3, iclass 25, count 2 2006.257.08:29:34.05#ibcon#about to read 4, iclass 25, count 2 2006.257.08:29:34.05#ibcon#read 4, iclass 25, count 2 2006.257.08:29:34.05#ibcon#about to read 5, iclass 25, count 2 2006.257.08:29:34.05#ibcon#read 5, iclass 25, count 2 2006.257.08:29:34.05#ibcon#about to read 6, iclass 25, count 2 2006.257.08:29:34.05#ibcon#read 6, iclass 25, count 2 2006.257.08:29:34.05#ibcon#end of sib2, iclass 25, count 2 2006.257.08:29:34.05#ibcon#*after write, iclass 25, count 2 2006.257.08:29:34.05#ibcon#*before return 0, iclass 25, count 2 2006.257.08:29:34.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:34.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:29:34.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.08:29:34.05#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:34.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:34.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:34.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:34.17#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:29:34.17#ibcon#first serial, iclass 25, count 0 2006.257.08:29:34.17#ibcon#enter sib2, iclass 25, count 0 2006.257.08:29:34.17#ibcon#flushed, iclass 25, count 0 2006.257.08:29:34.17#ibcon#about to write, iclass 25, count 0 2006.257.08:29:34.17#ibcon#wrote, iclass 25, count 0 2006.257.08:29:34.17#ibcon#about to read 3, iclass 25, count 0 2006.257.08:29:34.19#ibcon#read 3, iclass 25, count 0 2006.257.08:29:34.19#ibcon#about to read 4, iclass 25, count 0 2006.257.08:29:34.19#ibcon#read 4, iclass 25, count 0 2006.257.08:29:34.19#ibcon#about to read 5, iclass 25, count 0 2006.257.08:29:34.19#ibcon#read 5, iclass 25, count 0 2006.257.08:29:34.19#ibcon#about to read 6, iclass 25, count 0 2006.257.08:29:34.19#ibcon#read 6, iclass 25, count 0 2006.257.08:29:34.19#ibcon#end of sib2, iclass 25, count 0 2006.257.08:29:34.19#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:29:34.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:29:34.19#ibcon#[27=USB\r\n] 2006.257.08:29:34.19#ibcon#*before write, iclass 25, count 0 2006.257.08:29:34.19#ibcon#enter sib2, iclass 25, count 0 2006.257.08:29:34.19#ibcon#flushed, iclass 25, count 0 2006.257.08:29:34.19#ibcon#about to write, iclass 25, count 0 2006.257.08:29:34.19#ibcon#wrote, iclass 25, count 0 2006.257.08:29:34.19#ibcon#about to read 3, iclass 25, count 0 2006.257.08:29:34.22#ibcon#read 3, iclass 25, count 0 2006.257.08:29:34.22#ibcon#about to read 4, iclass 25, count 0 2006.257.08:29:34.22#ibcon#read 4, iclass 25, count 0 2006.257.08:29:34.22#ibcon#about to read 5, iclass 25, count 0 2006.257.08:29:34.22#ibcon#read 5, iclass 25, count 0 2006.257.08:29:34.22#ibcon#about to read 6, iclass 25, count 0 2006.257.08:29:34.22#ibcon#read 6, iclass 25, count 0 2006.257.08:29:34.22#ibcon#end of sib2, iclass 25, count 0 2006.257.08:29:34.22#ibcon#*after write, iclass 25, count 0 2006.257.08:29:34.22#ibcon#*before return 0, iclass 25, count 0 2006.257.08:29:34.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:34.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:29:34.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:29:34.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:29:34.22$vck44/vblo=5,709.99 2006.257.08:29:34.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.08:29:34.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.08:29:34.22#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:34.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:34.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:34.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:34.22#ibcon#enter wrdev, iclass 27, count 0 2006.257.08:29:34.22#ibcon#first serial, iclass 27, count 0 2006.257.08:29:34.22#ibcon#enter sib2, iclass 27, count 0 2006.257.08:29:34.22#ibcon#flushed, iclass 27, count 0 2006.257.08:29:34.22#ibcon#about to write, iclass 27, count 0 2006.257.08:29:34.22#ibcon#wrote, iclass 27, count 0 2006.257.08:29:34.22#ibcon#about to read 3, iclass 27, count 0 2006.257.08:29:34.24#ibcon#read 3, iclass 27, count 0 2006.257.08:29:34.24#ibcon#about to read 4, iclass 27, count 0 2006.257.08:29:34.24#ibcon#read 4, iclass 27, count 0 2006.257.08:29:34.24#ibcon#about to read 5, iclass 27, count 0 2006.257.08:29:34.24#ibcon#read 5, iclass 27, count 0 2006.257.08:29:34.24#ibcon#about to read 6, iclass 27, count 0 2006.257.08:29:34.24#ibcon#read 6, iclass 27, count 0 2006.257.08:29:34.24#ibcon#end of sib2, iclass 27, count 0 2006.257.08:29:34.24#ibcon#*mode == 0, iclass 27, count 0 2006.257.08:29:34.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.08:29:34.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:29:34.24#ibcon#*before write, iclass 27, count 0 2006.257.08:29:34.24#ibcon#enter sib2, iclass 27, count 0 2006.257.08:29:34.24#ibcon#flushed, iclass 27, count 0 2006.257.08:29:34.24#ibcon#about to write, iclass 27, count 0 2006.257.08:29:34.24#ibcon#wrote, iclass 27, count 0 2006.257.08:29:34.24#ibcon#about to read 3, iclass 27, count 0 2006.257.08:29:34.28#ibcon#read 3, iclass 27, count 0 2006.257.08:29:34.28#ibcon#about to read 4, iclass 27, count 0 2006.257.08:29:34.28#ibcon#read 4, iclass 27, count 0 2006.257.08:29:34.28#ibcon#about to read 5, iclass 27, count 0 2006.257.08:29:34.28#ibcon#read 5, iclass 27, count 0 2006.257.08:29:34.28#ibcon#about to read 6, iclass 27, count 0 2006.257.08:29:34.28#ibcon#read 6, iclass 27, count 0 2006.257.08:29:34.28#ibcon#end of sib2, iclass 27, count 0 2006.257.08:29:34.28#ibcon#*after write, iclass 27, count 0 2006.257.08:29:34.28#ibcon#*before return 0, iclass 27, count 0 2006.257.08:29:34.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:34.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:29:34.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.08:29:34.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.08:29:34.28$vck44/vb=5,4 2006.257.08:29:34.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.08:29:34.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.08:29:34.28#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:34.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:34.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:34.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:34.34#ibcon#enter wrdev, iclass 29, count 2 2006.257.08:29:34.34#ibcon#first serial, iclass 29, count 2 2006.257.08:29:34.34#ibcon#enter sib2, iclass 29, count 2 2006.257.08:29:34.34#ibcon#flushed, iclass 29, count 2 2006.257.08:29:34.34#ibcon#about to write, iclass 29, count 2 2006.257.08:29:34.34#ibcon#wrote, iclass 29, count 2 2006.257.08:29:34.34#ibcon#about to read 3, iclass 29, count 2 2006.257.08:29:34.36#ibcon#read 3, iclass 29, count 2 2006.257.08:29:34.36#ibcon#about to read 4, iclass 29, count 2 2006.257.08:29:34.36#ibcon#read 4, iclass 29, count 2 2006.257.08:29:34.36#ibcon#about to read 5, iclass 29, count 2 2006.257.08:29:34.36#ibcon#read 5, iclass 29, count 2 2006.257.08:29:34.36#ibcon#about to read 6, iclass 29, count 2 2006.257.08:29:34.36#ibcon#read 6, iclass 29, count 2 2006.257.08:29:34.36#ibcon#end of sib2, iclass 29, count 2 2006.257.08:29:34.36#ibcon#*mode == 0, iclass 29, count 2 2006.257.08:29:34.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.08:29:34.36#ibcon#[27=AT05-04\r\n] 2006.257.08:29:34.36#ibcon#*before write, iclass 29, count 2 2006.257.08:29:34.36#ibcon#enter sib2, iclass 29, count 2 2006.257.08:29:34.36#ibcon#flushed, iclass 29, count 2 2006.257.08:29:34.36#ibcon#about to write, iclass 29, count 2 2006.257.08:29:34.36#ibcon#wrote, iclass 29, count 2 2006.257.08:29:34.36#ibcon#about to read 3, iclass 29, count 2 2006.257.08:29:34.39#ibcon#read 3, iclass 29, count 2 2006.257.08:29:34.39#ibcon#about to read 4, iclass 29, count 2 2006.257.08:29:34.39#ibcon#read 4, iclass 29, count 2 2006.257.08:29:34.39#ibcon#about to read 5, iclass 29, count 2 2006.257.08:29:34.39#ibcon#read 5, iclass 29, count 2 2006.257.08:29:34.39#ibcon#about to read 6, iclass 29, count 2 2006.257.08:29:34.39#ibcon#read 6, iclass 29, count 2 2006.257.08:29:34.39#ibcon#end of sib2, iclass 29, count 2 2006.257.08:29:34.39#ibcon#*after write, iclass 29, count 2 2006.257.08:29:34.39#ibcon#*before return 0, iclass 29, count 2 2006.257.08:29:34.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:34.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:29:34.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.08:29:34.39#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:34.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:34.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:34.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:34.51#ibcon#enter wrdev, iclass 29, count 0 2006.257.08:29:34.51#ibcon#first serial, iclass 29, count 0 2006.257.08:29:34.51#ibcon#enter sib2, iclass 29, count 0 2006.257.08:29:34.51#ibcon#flushed, iclass 29, count 0 2006.257.08:29:34.51#ibcon#about to write, iclass 29, count 0 2006.257.08:29:34.51#ibcon#wrote, iclass 29, count 0 2006.257.08:29:34.51#ibcon#about to read 3, iclass 29, count 0 2006.257.08:29:34.53#ibcon#read 3, iclass 29, count 0 2006.257.08:29:34.53#ibcon#about to read 4, iclass 29, count 0 2006.257.08:29:34.53#ibcon#read 4, iclass 29, count 0 2006.257.08:29:34.53#ibcon#about to read 5, iclass 29, count 0 2006.257.08:29:34.53#ibcon#read 5, iclass 29, count 0 2006.257.08:29:34.53#ibcon#about to read 6, iclass 29, count 0 2006.257.08:29:34.53#ibcon#read 6, iclass 29, count 0 2006.257.08:29:34.53#ibcon#end of sib2, iclass 29, count 0 2006.257.08:29:34.53#ibcon#*mode == 0, iclass 29, count 0 2006.257.08:29:34.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.08:29:34.53#ibcon#[27=USB\r\n] 2006.257.08:29:34.53#ibcon#*before write, iclass 29, count 0 2006.257.08:29:34.53#ibcon#enter sib2, iclass 29, count 0 2006.257.08:29:34.53#ibcon#flushed, iclass 29, count 0 2006.257.08:29:34.53#ibcon#about to write, iclass 29, count 0 2006.257.08:29:34.53#ibcon#wrote, iclass 29, count 0 2006.257.08:29:34.53#ibcon#about to read 3, iclass 29, count 0 2006.257.08:29:34.56#ibcon#read 3, iclass 29, count 0 2006.257.08:29:34.56#ibcon#about to read 4, iclass 29, count 0 2006.257.08:29:34.56#ibcon#read 4, iclass 29, count 0 2006.257.08:29:34.56#ibcon#about to read 5, iclass 29, count 0 2006.257.08:29:34.56#ibcon#read 5, iclass 29, count 0 2006.257.08:29:34.56#ibcon#about to read 6, iclass 29, count 0 2006.257.08:29:34.56#ibcon#read 6, iclass 29, count 0 2006.257.08:29:34.56#ibcon#end of sib2, iclass 29, count 0 2006.257.08:29:34.56#ibcon#*after write, iclass 29, count 0 2006.257.08:29:34.56#ibcon#*before return 0, iclass 29, count 0 2006.257.08:29:34.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:34.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:29:34.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.08:29:34.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.08:29:34.56$vck44/vblo=6,719.99 2006.257.08:29:34.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.08:29:34.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.08:29:34.56#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:34.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:34.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:34.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:34.56#ibcon#enter wrdev, iclass 31, count 0 2006.257.08:29:34.56#ibcon#first serial, iclass 31, count 0 2006.257.08:29:34.56#ibcon#enter sib2, iclass 31, count 0 2006.257.08:29:34.56#ibcon#flushed, iclass 31, count 0 2006.257.08:29:34.56#ibcon#about to write, iclass 31, count 0 2006.257.08:29:34.56#ibcon#wrote, iclass 31, count 0 2006.257.08:29:34.56#ibcon#about to read 3, iclass 31, count 0 2006.257.08:29:34.58#ibcon#read 3, iclass 31, count 0 2006.257.08:29:34.58#ibcon#about to read 4, iclass 31, count 0 2006.257.08:29:34.58#ibcon#read 4, iclass 31, count 0 2006.257.08:29:34.58#ibcon#about to read 5, iclass 31, count 0 2006.257.08:29:34.58#ibcon#read 5, iclass 31, count 0 2006.257.08:29:34.58#ibcon#about to read 6, iclass 31, count 0 2006.257.08:29:34.58#ibcon#read 6, iclass 31, count 0 2006.257.08:29:34.58#ibcon#end of sib2, iclass 31, count 0 2006.257.08:29:34.58#ibcon#*mode == 0, iclass 31, count 0 2006.257.08:29:34.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.08:29:34.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:29:34.58#ibcon#*before write, iclass 31, count 0 2006.257.08:29:34.58#ibcon#enter sib2, iclass 31, count 0 2006.257.08:29:34.58#ibcon#flushed, iclass 31, count 0 2006.257.08:29:34.58#ibcon#about to write, iclass 31, count 0 2006.257.08:29:34.58#ibcon#wrote, iclass 31, count 0 2006.257.08:29:34.58#ibcon#about to read 3, iclass 31, count 0 2006.257.08:29:34.62#ibcon#read 3, iclass 31, count 0 2006.257.08:29:34.62#ibcon#about to read 4, iclass 31, count 0 2006.257.08:29:34.62#ibcon#read 4, iclass 31, count 0 2006.257.08:29:34.62#ibcon#about to read 5, iclass 31, count 0 2006.257.08:29:34.62#ibcon#read 5, iclass 31, count 0 2006.257.08:29:34.62#ibcon#about to read 6, iclass 31, count 0 2006.257.08:29:34.62#ibcon#read 6, iclass 31, count 0 2006.257.08:29:34.62#ibcon#end of sib2, iclass 31, count 0 2006.257.08:29:34.62#ibcon#*after write, iclass 31, count 0 2006.257.08:29:34.62#ibcon#*before return 0, iclass 31, count 0 2006.257.08:29:34.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:34.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:29:34.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.08:29:34.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.08:29:34.62$vck44/vb=6,4 2006.257.08:29:34.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.08:29:34.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.08:29:34.62#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:34.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:34.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:34.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:34.68#ibcon#enter wrdev, iclass 33, count 2 2006.257.08:29:34.68#ibcon#first serial, iclass 33, count 2 2006.257.08:29:34.68#ibcon#enter sib2, iclass 33, count 2 2006.257.08:29:34.68#ibcon#flushed, iclass 33, count 2 2006.257.08:29:34.68#ibcon#about to write, iclass 33, count 2 2006.257.08:29:34.68#ibcon#wrote, iclass 33, count 2 2006.257.08:29:34.68#ibcon#about to read 3, iclass 33, count 2 2006.257.08:29:34.70#ibcon#read 3, iclass 33, count 2 2006.257.08:29:34.70#ibcon#about to read 4, iclass 33, count 2 2006.257.08:29:34.70#ibcon#read 4, iclass 33, count 2 2006.257.08:29:34.70#ibcon#about to read 5, iclass 33, count 2 2006.257.08:29:34.70#ibcon#read 5, iclass 33, count 2 2006.257.08:29:34.70#ibcon#about to read 6, iclass 33, count 2 2006.257.08:29:34.70#ibcon#read 6, iclass 33, count 2 2006.257.08:29:34.70#ibcon#end of sib2, iclass 33, count 2 2006.257.08:29:34.70#ibcon#*mode == 0, iclass 33, count 2 2006.257.08:29:34.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.08:29:34.70#ibcon#[27=AT06-04\r\n] 2006.257.08:29:34.70#ibcon#*before write, iclass 33, count 2 2006.257.08:29:34.70#ibcon#enter sib2, iclass 33, count 2 2006.257.08:29:34.70#ibcon#flushed, iclass 33, count 2 2006.257.08:29:34.70#ibcon#about to write, iclass 33, count 2 2006.257.08:29:34.70#ibcon#wrote, iclass 33, count 2 2006.257.08:29:34.70#ibcon#about to read 3, iclass 33, count 2 2006.257.08:29:34.73#ibcon#read 3, iclass 33, count 2 2006.257.08:29:34.73#ibcon#about to read 4, iclass 33, count 2 2006.257.08:29:34.73#ibcon#read 4, iclass 33, count 2 2006.257.08:29:34.73#ibcon#about to read 5, iclass 33, count 2 2006.257.08:29:34.73#ibcon#read 5, iclass 33, count 2 2006.257.08:29:34.73#ibcon#about to read 6, iclass 33, count 2 2006.257.08:29:34.73#ibcon#read 6, iclass 33, count 2 2006.257.08:29:34.73#ibcon#end of sib2, iclass 33, count 2 2006.257.08:29:34.73#ibcon#*after write, iclass 33, count 2 2006.257.08:29:34.73#ibcon#*before return 0, iclass 33, count 2 2006.257.08:29:34.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:34.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:29:34.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.08:29:34.73#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:34.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:34.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:34.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:34.85#ibcon#enter wrdev, iclass 33, count 0 2006.257.08:29:34.85#ibcon#first serial, iclass 33, count 0 2006.257.08:29:34.85#ibcon#enter sib2, iclass 33, count 0 2006.257.08:29:34.85#ibcon#flushed, iclass 33, count 0 2006.257.08:29:34.85#ibcon#about to write, iclass 33, count 0 2006.257.08:29:34.85#ibcon#wrote, iclass 33, count 0 2006.257.08:29:34.85#ibcon#about to read 3, iclass 33, count 0 2006.257.08:29:34.87#ibcon#read 3, iclass 33, count 0 2006.257.08:29:34.87#ibcon#about to read 4, iclass 33, count 0 2006.257.08:29:34.87#ibcon#read 4, iclass 33, count 0 2006.257.08:29:34.87#ibcon#about to read 5, iclass 33, count 0 2006.257.08:29:34.87#ibcon#read 5, iclass 33, count 0 2006.257.08:29:34.87#ibcon#about to read 6, iclass 33, count 0 2006.257.08:29:34.87#ibcon#read 6, iclass 33, count 0 2006.257.08:29:34.87#ibcon#end of sib2, iclass 33, count 0 2006.257.08:29:34.87#ibcon#*mode == 0, iclass 33, count 0 2006.257.08:29:34.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.08:29:34.87#ibcon#[27=USB\r\n] 2006.257.08:29:34.87#ibcon#*before write, iclass 33, count 0 2006.257.08:29:34.87#ibcon#enter sib2, iclass 33, count 0 2006.257.08:29:34.87#ibcon#flushed, iclass 33, count 0 2006.257.08:29:34.87#ibcon#about to write, iclass 33, count 0 2006.257.08:29:34.87#ibcon#wrote, iclass 33, count 0 2006.257.08:29:34.87#ibcon#about to read 3, iclass 33, count 0 2006.257.08:29:34.90#ibcon#read 3, iclass 33, count 0 2006.257.08:29:34.90#ibcon#about to read 4, iclass 33, count 0 2006.257.08:29:34.90#ibcon#read 4, iclass 33, count 0 2006.257.08:29:34.90#ibcon#about to read 5, iclass 33, count 0 2006.257.08:29:34.90#ibcon#read 5, iclass 33, count 0 2006.257.08:29:34.90#ibcon#about to read 6, iclass 33, count 0 2006.257.08:29:34.90#ibcon#read 6, iclass 33, count 0 2006.257.08:29:34.90#ibcon#end of sib2, iclass 33, count 0 2006.257.08:29:34.90#ibcon#*after write, iclass 33, count 0 2006.257.08:29:34.90#ibcon#*before return 0, iclass 33, count 0 2006.257.08:29:34.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:34.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:29:34.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.08:29:34.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.08:29:34.90$vck44/vblo=7,734.99 2006.257.08:29:34.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.08:29:34.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.08:29:34.90#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:34.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:34.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:34.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:34.90#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:29:34.90#ibcon#first serial, iclass 35, count 0 2006.257.08:29:34.90#ibcon#enter sib2, iclass 35, count 0 2006.257.08:29:34.90#ibcon#flushed, iclass 35, count 0 2006.257.08:29:34.90#ibcon#about to write, iclass 35, count 0 2006.257.08:29:34.90#ibcon#wrote, iclass 35, count 0 2006.257.08:29:34.90#ibcon#about to read 3, iclass 35, count 0 2006.257.08:29:34.92#ibcon#read 3, iclass 35, count 0 2006.257.08:29:34.92#ibcon#about to read 4, iclass 35, count 0 2006.257.08:29:34.92#ibcon#read 4, iclass 35, count 0 2006.257.08:29:34.92#ibcon#about to read 5, iclass 35, count 0 2006.257.08:29:34.92#ibcon#read 5, iclass 35, count 0 2006.257.08:29:34.92#ibcon#about to read 6, iclass 35, count 0 2006.257.08:29:34.92#ibcon#read 6, iclass 35, count 0 2006.257.08:29:34.92#ibcon#end of sib2, iclass 35, count 0 2006.257.08:29:34.92#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:29:34.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:29:34.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:29:34.92#ibcon#*before write, iclass 35, count 0 2006.257.08:29:34.92#ibcon#enter sib2, iclass 35, count 0 2006.257.08:29:34.92#ibcon#flushed, iclass 35, count 0 2006.257.08:29:34.92#ibcon#about to write, iclass 35, count 0 2006.257.08:29:34.92#ibcon#wrote, iclass 35, count 0 2006.257.08:29:34.92#ibcon#about to read 3, iclass 35, count 0 2006.257.08:29:34.96#ibcon#read 3, iclass 35, count 0 2006.257.08:29:34.96#ibcon#about to read 4, iclass 35, count 0 2006.257.08:29:34.96#ibcon#read 4, iclass 35, count 0 2006.257.08:29:34.96#ibcon#about to read 5, iclass 35, count 0 2006.257.08:29:34.96#ibcon#read 5, iclass 35, count 0 2006.257.08:29:34.96#ibcon#about to read 6, iclass 35, count 0 2006.257.08:29:34.96#ibcon#read 6, iclass 35, count 0 2006.257.08:29:34.96#ibcon#end of sib2, iclass 35, count 0 2006.257.08:29:34.96#ibcon#*after write, iclass 35, count 0 2006.257.08:29:34.96#ibcon#*before return 0, iclass 35, count 0 2006.257.08:29:34.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:34.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:29:34.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:29:34.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:29:34.96$vck44/vb=7,4 2006.257.08:29:34.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.08:29:34.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.08:29:34.96#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:34.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:35.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:35.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:35.02#ibcon#enter wrdev, iclass 37, count 2 2006.257.08:29:35.02#ibcon#first serial, iclass 37, count 2 2006.257.08:29:35.02#ibcon#enter sib2, iclass 37, count 2 2006.257.08:29:35.02#ibcon#flushed, iclass 37, count 2 2006.257.08:29:35.02#ibcon#about to write, iclass 37, count 2 2006.257.08:29:35.02#ibcon#wrote, iclass 37, count 2 2006.257.08:29:35.02#ibcon#about to read 3, iclass 37, count 2 2006.257.08:29:35.04#ibcon#read 3, iclass 37, count 2 2006.257.08:29:35.04#ibcon#about to read 4, iclass 37, count 2 2006.257.08:29:35.04#ibcon#read 4, iclass 37, count 2 2006.257.08:29:35.04#ibcon#about to read 5, iclass 37, count 2 2006.257.08:29:35.04#ibcon#read 5, iclass 37, count 2 2006.257.08:29:35.04#ibcon#about to read 6, iclass 37, count 2 2006.257.08:29:35.04#ibcon#read 6, iclass 37, count 2 2006.257.08:29:35.04#ibcon#end of sib2, iclass 37, count 2 2006.257.08:29:35.04#ibcon#*mode == 0, iclass 37, count 2 2006.257.08:29:35.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.08:29:35.04#ibcon#[27=AT07-04\r\n] 2006.257.08:29:35.04#ibcon#*before write, iclass 37, count 2 2006.257.08:29:35.04#ibcon#enter sib2, iclass 37, count 2 2006.257.08:29:35.04#ibcon#flushed, iclass 37, count 2 2006.257.08:29:35.04#ibcon#about to write, iclass 37, count 2 2006.257.08:29:35.04#ibcon#wrote, iclass 37, count 2 2006.257.08:29:35.04#ibcon#about to read 3, iclass 37, count 2 2006.257.08:29:35.07#ibcon#read 3, iclass 37, count 2 2006.257.08:29:35.07#ibcon#about to read 4, iclass 37, count 2 2006.257.08:29:35.07#ibcon#read 4, iclass 37, count 2 2006.257.08:29:35.07#ibcon#about to read 5, iclass 37, count 2 2006.257.08:29:35.07#ibcon#read 5, iclass 37, count 2 2006.257.08:29:35.07#ibcon#about to read 6, iclass 37, count 2 2006.257.08:29:35.07#ibcon#read 6, iclass 37, count 2 2006.257.08:29:35.07#ibcon#end of sib2, iclass 37, count 2 2006.257.08:29:35.07#ibcon#*after write, iclass 37, count 2 2006.257.08:29:35.07#ibcon#*before return 0, iclass 37, count 2 2006.257.08:29:35.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:35.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:29:35.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.08:29:35.07#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:35.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:35.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:35.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:35.19#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:29:35.19#ibcon#first serial, iclass 37, count 0 2006.257.08:29:35.19#ibcon#enter sib2, iclass 37, count 0 2006.257.08:29:35.19#ibcon#flushed, iclass 37, count 0 2006.257.08:29:35.19#ibcon#about to write, iclass 37, count 0 2006.257.08:29:35.19#ibcon#wrote, iclass 37, count 0 2006.257.08:29:35.19#ibcon#about to read 3, iclass 37, count 0 2006.257.08:29:35.21#ibcon#read 3, iclass 37, count 0 2006.257.08:29:35.21#ibcon#about to read 4, iclass 37, count 0 2006.257.08:29:35.21#ibcon#read 4, iclass 37, count 0 2006.257.08:29:35.21#ibcon#about to read 5, iclass 37, count 0 2006.257.08:29:35.21#ibcon#read 5, iclass 37, count 0 2006.257.08:29:35.21#ibcon#about to read 6, iclass 37, count 0 2006.257.08:29:35.21#ibcon#read 6, iclass 37, count 0 2006.257.08:29:35.21#ibcon#end of sib2, iclass 37, count 0 2006.257.08:29:35.21#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:29:35.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:29:35.21#ibcon#[27=USB\r\n] 2006.257.08:29:35.21#ibcon#*before write, iclass 37, count 0 2006.257.08:29:35.21#ibcon#enter sib2, iclass 37, count 0 2006.257.08:29:35.21#ibcon#flushed, iclass 37, count 0 2006.257.08:29:35.21#ibcon#about to write, iclass 37, count 0 2006.257.08:29:35.21#ibcon#wrote, iclass 37, count 0 2006.257.08:29:35.21#ibcon#about to read 3, iclass 37, count 0 2006.257.08:29:35.24#ibcon#read 3, iclass 37, count 0 2006.257.08:29:35.24#ibcon#about to read 4, iclass 37, count 0 2006.257.08:29:35.24#ibcon#read 4, iclass 37, count 0 2006.257.08:29:35.24#ibcon#about to read 5, iclass 37, count 0 2006.257.08:29:35.24#ibcon#read 5, iclass 37, count 0 2006.257.08:29:35.24#ibcon#about to read 6, iclass 37, count 0 2006.257.08:29:35.24#ibcon#read 6, iclass 37, count 0 2006.257.08:29:35.24#ibcon#end of sib2, iclass 37, count 0 2006.257.08:29:35.24#ibcon#*after write, iclass 37, count 0 2006.257.08:29:35.24#ibcon#*before return 0, iclass 37, count 0 2006.257.08:29:35.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:35.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:29:35.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:29:35.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:29:35.24$vck44/vblo=8,744.99 2006.257.08:29:35.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.08:29:35.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.08:29:35.24#ibcon#ireg 17 cls_cnt 0 2006.257.08:29:35.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:35.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:35.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:35.24#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:29:35.24#ibcon#first serial, iclass 39, count 0 2006.257.08:29:35.24#ibcon#enter sib2, iclass 39, count 0 2006.257.08:29:35.24#ibcon#flushed, iclass 39, count 0 2006.257.08:29:35.24#ibcon#about to write, iclass 39, count 0 2006.257.08:29:35.24#ibcon#wrote, iclass 39, count 0 2006.257.08:29:35.24#ibcon#about to read 3, iclass 39, count 0 2006.257.08:29:35.26#ibcon#read 3, iclass 39, count 0 2006.257.08:29:35.26#ibcon#about to read 4, iclass 39, count 0 2006.257.08:29:35.26#ibcon#read 4, iclass 39, count 0 2006.257.08:29:35.26#ibcon#about to read 5, iclass 39, count 0 2006.257.08:29:35.26#ibcon#read 5, iclass 39, count 0 2006.257.08:29:35.26#ibcon#about to read 6, iclass 39, count 0 2006.257.08:29:35.26#ibcon#read 6, iclass 39, count 0 2006.257.08:29:35.26#ibcon#end of sib2, iclass 39, count 0 2006.257.08:29:35.26#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:29:35.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:29:35.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:29:35.26#ibcon#*before write, iclass 39, count 0 2006.257.08:29:35.26#ibcon#enter sib2, iclass 39, count 0 2006.257.08:29:35.26#ibcon#flushed, iclass 39, count 0 2006.257.08:29:35.26#ibcon#about to write, iclass 39, count 0 2006.257.08:29:35.26#ibcon#wrote, iclass 39, count 0 2006.257.08:29:35.26#ibcon#about to read 3, iclass 39, count 0 2006.257.08:29:35.29#abcon#<5=/15 1.1 3.1 20.69 911012.8\r\n> 2006.257.08:29:35.30#ibcon#read 3, iclass 39, count 0 2006.257.08:29:35.30#ibcon#about to read 4, iclass 39, count 0 2006.257.08:29:35.30#ibcon#read 4, iclass 39, count 0 2006.257.08:29:35.30#ibcon#about to read 5, iclass 39, count 0 2006.257.08:29:35.30#ibcon#read 5, iclass 39, count 0 2006.257.08:29:35.30#ibcon#about to read 6, iclass 39, count 0 2006.257.08:29:35.30#ibcon#read 6, iclass 39, count 0 2006.257.08:29:35.30#ibcon#end of sib2, iclass 39, count 0 2006.257.08:29:35.30#ibcon#*after write, iclass 39, count 0 2006.257.08:29:35.30#ibcon#*before return 0, iclass 39, count 0 2006.257.08:29:35.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:35.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:29:35.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:29:35.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:29:35.30$vck44/vb=8,4 2006.257.08:29:35.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.08:29:35.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.08:29:35.30#ibcon#ireg 11 cls_cnt 2 2006.257.08:29:35.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:29:35.31#abcon#{5=INTERFACE CLEAR} 2006.257.08:29:35.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:29:35.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:29:35.36#ibcon#enter wrdev, iclass 6, count 2 2006.257.08:29:35.36#ibcon#first serial, iclass 6, count 2 2006.257.08:29:35.36#ibcon#enter sib2, iclass 6, count 2 2006.257.08:29:35.36#ibcon#flushed, iclass 6, count 2 2006.257.08:29:35.36#ibcon#about to write, iclass 6, count 2 2006.257.08:29:35.36#ibcon#wrote, iclass 6, count 2 2006.257.08:29:35.36#ibcon#about to read 3, iclass 6, count 2 2006.257.08:29:35.37#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:29:35.38#ibcon#read 3, iclass 6, count 2 2006.257.08:29:35.38#ibcon#about to read 4, iclass 6, count 2 2006.257.08:29:35.38#ibcon#read 4, iclass 6, count 2 2006.257.08:29:35.38#ibcon#about to read 5, iclass 6, count 2 2006.257.08:29:35.38#ibcon#read 5, iclass 6, count 2 2006.257.08:29:35.38#ibcon#about to read 6, iclass 6, count 2 2006.257.08:29:35.38#ibcon#read 6, iclass 6, count 2 2006.257.08:29:35.38#ibcon#end of sib2, iclass 6, count 2 2006.257.08:29:35.38#ibcon#*mode == 0, iclass 6, count 2 2006.257.08:29:35.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.08:29:35.38#ibcon#[27=AT08-04\r\n] 2006.257.08:29:35.38#ibcon#*before write, iclass 6, count 2 2006.257.08:29:35.38#ibcon#enter sib2, iclass 6, count 2 2006.257.08:29:35.38#ibcon#flushed, iclass 6, count 2 2006.257.08:29:35.38#ibcon#about to write, iclass 6, count 2 2006.257.08:29:35.38#ibcon#wrote, iclass 6, count 2 2006.257.08:29:35.38#ibcon#about to read 3, iclass 6, count 2 2006.257.08:29:35.41#ibcon#read 3, iclass 6, count 2 2006.257.08:29:35.41#ibcon#about to read 4, iclass 6, count 2 2006.257.08:29:35.41#ibcon#read 4, iclass 6, count 2 2006.257.08:29:35.41#ibcon#about to read 5, iclass 6, count 2 2006.257.08:29:35.41#ibcon#read 5, iclass 6, count 2 2006.257.08:29:35.41#ibcon#about to read 6, iclass 6, count 2 2006.257.08:29:35.41#ibcon#read 6, iclass 6, count 2 2006.257.08:29:35.41#ibcon#end of sib2, iclass 6, count 2 2006.257.08:29:35.41#ibcon#*after write, iclass 6, count 2 2006.257.08:29:35.41#ibcon#*before return 0, iclass 6, count 2 2006.257.08:29:35.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:29:35.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:29:35.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.08:29:35.41#ibcon#ireg 7 cls_cnt 0 2006.257.08:29:35.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:29:35.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:29:35.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:29:35.53#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:29:35.53#ibcon#first serial, iclass 6, count 0 2006.257.08:29:35.53#ibcon#enter sib2, iclass 6, count 0 2006.257.08:29:35.53#ibcon#flushed, iclass 6, count 0 2006.257.08:29:35.53#ibcon#about to write, iclass 6, count 0 2006.257.08:29:35.53#ibcon#wrote, iclass 6, count 0 2006.257.08:29:35.53#ibcon#about to read 3, iclass 6, count 0 2006.257.08:29:35.55#ibcon#read 3, iclass 6, count 0 2006.257.08:29:35.55#ibcon#about to read 4, iclass 6, count 0 2006.257.08:29:35.55#ibcon#read 4, iclass 6, count 0 2006.257.08:29:35.55#ibcon#about to read 5, iclass 6, count 0 2006.257.08:29:35.55#ibcon#read 5, iclass 6, count 0 2006.257.08:29:35.55#ibcon#about to read 6, iclass 6, count 0 2006.257.08:29:35.55#ibcon#read 6, iclass 6, count 0 2006.257.08:29:35.55#ibcon#end of sib2, iclass 6, count 0 2006.257.08:29:35.55#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:29:35.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:29:35.55#ibcon#[27=USB\r\n] 2006.257.08:29:35.55#ibcon#*before write, iclass 6, count 0 2006.257.08:29:35.55#ibcon#enter sib2, iclass 6, count 0 2006.257.08:29:35.55#ibcon#flushed, iclass 6, count 0 2006.257.08:29:35.55#ibcon#about to write, iclass 6, count 0 2006.257.08:29:35.55#ibcon#wrote, iclass 6, count 0 2006.257.08:29:35.55#ibcon#about to read 3, iclass 6, count 0 2006.257.08:29:35.58#ibcon#read 3, iclass 6, count 0 2006.257.08:29:35.58#ibcon#about to read 4, iclass 6, count 0 2006.257.08:29:35.58#ibcon#read 4, iclass 6, count 0 2006.257.08:29:35.58#ibcon#about to read 5, iclass 6, count 0 2006.257.08:29:35.58#ibcon#read 5, iclass 6, count 0 2006.257.08:29:35.58#ibcon#about to read 6, iclass 6, count 0 2006.257.08:29:35.58#ibcon#read 6, iclass 6, count 0 2006.257.08:29:35.58#ibcon#end of sib2, iclass 6, count 0 2006.257.08:29:35.58#ibcon#*after write, iclass 6, count 0 2006.257.08:29:35.58#ibcon#*before return 0, iclass 6, count 0 2006.257.08:29:35.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:29:35.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:29:35.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:29:35.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:29:35.58$vck44/vabw=wide 2006.257.08:29:35.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.08:29:35.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.08:29:35.58#ibcon#ireg 8 cls_cnt 0 2006.257.08:29:35.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:35.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:35.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:35.58#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:29:35.58#ibcon#first serial, iclass 11, count 0 2006.257.08:29:35.58#ibcon#enter sib2, iclass 11, count 0 2006.257.08:29:35.58#ibcon#flushed, iclass 11, count 0 2006.257.08:29:35.58#ibcon#about to write, iclass 11, count 0 2006.257.08:29:35.58#ibcon#wrote, iclass 11, count 0 2006.257.08:29:35.58#ibcon#about to read 3, iclass 11, count 0 2006.257.08:29:35.60#ibcon#read 3, iclass 11, count 0 2006.257.08:29:35.60#ibcon#about to read 4, iclass 11, count 0 2006.257.08:29:35.60#ibcon#read 4, iclass 11, count 0 2006.257.08:29:35.60#ibcon#about to read 5, iclass 11, count 0 2006.257.08:29:35.60#ibcon#read 5, iclass 11, count 0 2006.257.08:29:35.60#ibcon#about to read 6, iclass 11, count 0 2006.257.08:29:35.60#ibcon#read 6, iclass 11, count 0 2006.257.08:29:35.60#ibcon#end of sib2, iclass 11, count 0 2006.257.08:29:35.60#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:29:35.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:29:35.60#ibcon#[25=BW32\r\n] 2006.257.08:29:35.60#ibcon#*before write, iclass 11, count 0 2006.257.08:29:35.60#ibcon#enter sib2, iclass 11, count 0 2006.257.08:29:35.60#ibcon#flushed, iclass 11, count 0 2006.257.08:29:35.60#ibcon#about to write, iclass 11, count 0 2006.257.08:29:35.60#ibcon#wrote, iclass 11, count 0 2006.257.08:29:35.60#ibcon#about to read 3, iclass 11, count 0 2006.257.08:29:35.63#ibcon#read 3, iclass 11, count 0 2006.257.08:29:35.63#ibcon#about to read 4, iclass 11, count 0 2006.257.08:29:35.63#ibcon#read 4, iclass 11, count 0 2006.257.08:29:35.63#ibcon#about to read 5, iclass 11, count 0 2006.257.08:29:35.63#ibcon#read 5, iclass 11, count 0 2006.257.08:29:35.63#ibcon#about to read 6, iclass 11, count 0 2006.257.08:29:35.63#ibcon#read 6, iclass 11, count 0 2006.257.08:29:35.63#ibcon#end of sib2, iclass 11, count 0 2006.257.08:29:35.63#ibcon#*after write, iclass 11, count 0 2006.257.08:29:35.63#ibcon#*before return 0, iclass 11, count 0 2006.257.08:29:35.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:35.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:29:35.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:29:35.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:29:35.63$vck44/vbbw=wide 2006.257.08:29:35.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.08:29:35.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.08:29:35.63#ibcon#ireg 8 cls_cnt 0 2006.257.08:29:35.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:29:35.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:29:35.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:29:35.70#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:29:35.70#ibcon#first serial, iclass 13, count 0 2006.257.08:29:35.70#ibcon#enter sib2, iclass 13, count 0 2006.257.08:29:35.70#ibcon#flushed, iclass 13, count 0 2006.257.08:29:35.70#ibcon#about to write, iclass 13, count 0 2006.257.08:29:35.70#ibcon#wrote, iclass 13, count 0 2006.257.08:29:35.70#ibcon#about to read 3, iclass 13, count 0 2006.257.08:29:35.72#ibcon#read 3, iclass 13, count 0 2006.257.08:29:35.72#ibcon#about to read 4, iclass 13, count 0 2006.257.08:29:35.72#ibcon#read 4, iclass 13, count 0 2006.257.08:29:35.72#ibcon#about to read 5, iclass 13, count 0 2006.257.08:29:35.72#ibcon#read 5, iclass 13, count 0 2006.257.08:29:35.72#ibcon#about to read 6, iclass 13, count 0 2006.257.08:29:35.72#ibcon#read 6, iclass 13, count 0 2006.257.08:29:35.72#ibcon#end of sib2, iclass 13, count 0 2006.257.08:29:35.72#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:29:35.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:29:35.72#ibcon#[27=BW32\r\n] 2006.257.08:29:35.72#ibcon#*before write, iclass 13, count 0 2006.257.08:29:35.72#ibcon#enter sib2, iclass 13, count 0 2006.257.08:29:35.72#ibcon#flushed, iclass 13, count 0 2006.257.08:29:35.72#ibcon#about to write, iclass 13, count 0 2006.257.08:29:35.72#ibcon#wrote, iclass 13, count 0 2006.257.08:29:35.72#ibcon#about to read 3, iclass 13, count 0 2006.257.08:29:35.75#ibcon#read 3, iclass 13, count 0 2006.257.08:29:35.75#ibcon#about to read 4, iclass 13, count 0 2006.257.08:29:35.75#ibcon#read 4, iclass 13, count 0 2006.257.08:29:35.75#ibcon#about to read 5, iclass 13, count 0 2006.257.08:29:35.75#ibcon#read 5, iclass 13, count 0 2006.257.08:29:35.75#ibcon#about to read 6, iclass 13, count 0 2006.257.08:29:35.75#ibcon#read 6, iclass 13, count 0 2006.257.08:29:35.75#ibcon#end of sib2, iclass 13, count 0 2006.257.08:29:35.75#ibcon#*after write, iclass 13, count 0 2006.257.08:29:35.75#ibcon#*before return 0, iclass 13, count 0 2006.257.08:29:35.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:29:35.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:29:35.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:29:35.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:29:35.75$setupk4/ifdk4 2006.257.08:29:35.75$ifdk4/lo= 2006.257.08:29:35.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:29:35.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:29:35.76$ifdk4/patch= 2006.257.08:29:35.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:29:35.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:29:35.76$setupk4/!*+20s 2006.257.08:29:41.14#trakl#Source acquired 2006.257.08:29:43.14#flagr#flagr/antenna,acquired 2006.257.08:29:45.46#abcon#<5=/15 1.1 3.1 20.69 911012.9\r\n> 2006.257.08:29:45.48#abcon#{5=INTERFACE CLEAR} 2006.257.08:29:45.54#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:29:50.27$setupk4/"tpicd 2006.257.08:29:50.27$setupk4/echo=off 2006.257.08:29:50.27$setupk4/xlog=off 2006.257.08:29:50.27:!2006.257.08:31:16 2006.257.08:31:16.00:preob 2006.257.08:31:17.14/onsource/TRACKING 2006.257.08:31:17.14:!2006.257.08:31:26 2006.257.08:31:26.00:"tape 2006.257.08:31:26.00:"st=record 2006.257.08:31:26.00:data_valid=on 2006.257.08:31:26.00:midob 2006.257.08:31:26.14/onsource/TRACKING 2006.257.08:31:26.14/wx/20.68,1012.9,91 2006.257.08:31:26.31/cable/+6.4743E-03 2006.257.08:31:27.40/va/01,08,usb,yes,33,36 2006.257.08:31:27.40/va/02,07,usb,yes,36,37 2006.257.08:31:27.40/va/03,08,usb,yes,33,34 2006.257.08:31:27.40/va/04,07,usb,yes,37,39 2006.257.08:31:27.40/va/05,04,usb,yes,33,34 2006.257.08:31:27.40/va/06,04,usb,yes,37,37 2006.257.08:31:27.40/va/07,04,usb,yes,38,39 2006.257.08:31:27.40/va/08,04,usb,yes,32,39 2006.257.08:31:27.63/valo/01,524.99,yes,locked 2006.257.08:31:27.63/valo/02,534.99,yes,locked 2006.257.08:31:27.63/valo/03,564.99,yes,locked 2006.257.08:31:27.63/valo/04,624.99,yes,locked 2006.257.08:31:27.63/valo/05,734.99,yes,locked 2006.257.08:31:27.63/valo/06,814.99,yes,locked 2006.257.08:31:27.63/valo/07,864.99,yes,locked 2006.257.08:31:27.63/valo/08,884.99,yes,locked 2006.257.08:31:28.72/vb/01,04,usb,yes,57,33 2006.257.08:31:28.72/vb/02,05,usb,yes,33,50 2006.257.08:31:28.72/vb/03,04,usb,yes,32,44 2006.257.08:31:28.72/vb/04,05,usb,yes,31,30 2006.257.08:31:28.72/vb/05,04,usb,yes,27,30 2006.257.08:31:28.72/vb/06,04,usb,yes,32,28 2006.257.08:31:28.72/vb/07,04,usb,yes,32,32 2006.257.08:31:28.72/vb/08,04,usb,yes,29,33 2006.257.08:31:28.95/vblo/01,629.99,yes,locked 2006.257.08:31:28.95/vblo/02,634.99,yes,locked 2006.257.08:31:28.95/vblo/03,649.99,yes,locked 2006.257.08:31:28.95/vblo/04,679.99,yes,locked 2006.257.08:31:28.95/vblo/05,709.99,yes,locked 2006.257.08:31:28.95/vblo/06,719.99,yes,locked 2006.257.08:31:28.95/vblo/07,734.99,yes,locked 2006.257.08:31:28.95/vblo/08,744.99,yes,locked 2006.257.08:31:29.10/vabw/8 2006.257.08:31:29.25/vbbw/8 2006.257.08:31:29.34/xfe/off,on,14.7 2006.257.08:31:29.71/ifatt/23,28,28,28 2006.257.08:31:30.07/fmout-gps/S +4.57E-07 2006.257.08:31:30.11:!2006.257.08:34:06 2006.257.08:34:06.01:data_valid=off 2006.257.08:34:06.01:"et 2006.257.08:34:06.01:!+3s 2006.257.08:34:09.02:"tape 2006.257.08:34:09.02:postob 2006.257.08:34:09.12/cable/+6.4739E-03 2006.257.08:34:09.12/wx/20.66,1013.0,91 2006.257.08:34:09.18/fmout-gps/S +4.56E-07 2006.257.08:34:09.18:scan_name=257-0842,jd0609,40 2006.257.08:34:09.18:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.08:34:11.14#flagr#flagr/antenna,new-source 2006.257.08:34:11.14:checkk5 2006.257.08:34:11.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:34:11.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:34:12.30/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:34:12.71/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:34:13.10/chk_obsdata//k5ts1/T2570831??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.08:34:13.49/chk_obsdata//k5ts2/T2570831??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.08:34:13.88/chk_obsdata//k5ts3/T2570831??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.08:34:14.28/chk_obsdata//k5ts4/T2570831??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.08:34:15.00/k5log//k5ts1_log_newline 2006.257.08:34:15.70/k5log//k5ts2_log_newline 2006.257.08:34:16.42/k5log//k5ts3_log_newline 2006.257.08:34:17.11/k5log//k5ts4_log_newline 2006.257.08:34:17.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:34:17.14:setupk4=1 2006.257.08:34:17.14$setupk4/echo=on 2006.257.08:34:17.14$setupk4/pcalon 2006.257.08:34:17.14$pcalon/"no phase cal control is implemented here 2006.257.08:34:17.14$setupk4/"tpicd=stop 2006.257.08:34:17.14$setupk4/"rec=synch_on 2006.257.08:34:17.14$setupk4/"rec_mode=128 2006.257.08:34:17.14$setupk4/!* 2006.257.08:34:17.14$setupk4/recpk4 2006.257.08:34:17.14$recpk4/recpatch= 2006.257.08:34:17.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:34:17.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:34:17.15$setupk4/vck44 2006.257.08:34:17.15$vck44/valo=1,524.99 2006.257.08:34:17.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.08:34:17.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.08:34:17.15#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:17.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:17.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:17.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:17.15#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:34:17.15#ibcon#first serial, iclass 18, count 0 2006.257.08:34:17.15#ibcon#enter sib2, iclass 18, count 0 2006.257.08:34:17.15#ibcon#flushed, iclass 18, count 0 2006.257.08:34:17.15#ibcon#about to write, iclass 18, count 0 2006.257.08:34:17.15#ibcon#wrote, iclass 18, count 0 2006.257.08:34:17.15#ibcon#about to read 3, iclass 18, count 0 2006.257.08:34:17.16#ibcon#read 3, iclass 18, count 0 2006.257.08:34:17.16#ibcon#about to read 4, iclass 18, count 0 2006.257.08:34:17.16#ibcon#read 4, iclass 18, count 0 2006.257.08:34:17.16#ibcon#about to read 5, iclass 18, count 0 2006.257.08:34:17.16#ibcon#read 5, iclass 18, count 0 2006.257.08:34:17.16#ibcon#about to read 6, iclass 18, count 0 2006.257.08:34:17.16#ibcon#read 6, iclass 18, count 0 2006.257.08:34:17.16#ibcon#end of sib2, iclass 18, count 0 2006.257.08:34:17.16#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:34:17.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:34:17.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:34:17.16#ibcon#*before write, iclass 18, count 0 2006.257.08:34:17.16#ibcon#enter sib2, iclass 18, count 0 2006.257.08:34:17.16#ibcon#flushed, iclass 18, count 0 2006.257.08:34:17.16#ibcon#about to write, iclass 18, count 0 2006.257.08:34:17.16#ibcon#wrote, iclass 18, count 0 2006.257.08:34:17.16#ibcon#about to read 3, iclass 18, count 0 2006.257.08:34:17.21#ibcon#read 3, iclass 18, count 0 2006.257.08:34:17.21#ibcon#about to read 4, iclass 18, count 0 2006.257.08:34:17.21#ibcon#read 4, iclass 18, count 0 2006.257.08:34:17.21#ibcon#about to read 5, iclass 18, count 0 2006.257.08:34:17.21#ibcon#read 5, iclass 18, count 0 2006.257.08:34:17.21#ibcon#about to read 6, iclass 18, count 0 2006.257.08:34:17.21#ibcon#read 6, iclass 18, count 0 2006.257.08:34:17.21#ibcon#end of sib2, iclass 18, count 0 2006.257.08:34:17.21#ibcon#*after write, iclass 18, count 0 2006.257.08:34:17.21#ibcon#*before return 0, iclass 18, count 0 2006.257.08:34:17.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:17.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:17.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:34:17.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:34:17.21$vck44/va=1,8 2006.257.08:34:17.21#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.08:34:17.21#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.08:34:17.21#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:17.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:17.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:17.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:17.21#ibcon#enter wrdev, iclass 20, count 2 2006.257.08:34:17.21#ibcon#first serial, iclass 20, count 2 2006.257.08:34:17.21#ibcon#enter sib2, iclass 20, count 2 2006.257.08:34:17.21#ibcon#flushed, iclass 20, count 2 2006.257.08:34:17.21#ibcon#about to write, iclass 20, count 2 2006.257.08:34:17.21#ibcon#wrote, iclass 20, count 2 2006.257.08:34:17.21#ibcon#about to read 3, iclass 20, count 2 2006.257.08:34:17.23#ibcon#read 3, iclass 20, count 2 2006.257.08:34:17.23#ibcon#about to read 4, iclass 20, count 2 2006.257.08:34:17.23#ibcon#read 4, iclass 20, count 2 2006.257.08:34:17.23#ibcon#about to read 5, iclass 20, count 2 2006.257.08:34:17.23#ibcon#read 5, iclass 20, count 2 2006.257.08:34:17.23#ibcon#about to read 6, iclass 20, count 2 2006.257.08:34:17.23#ibcon#read 6, iclass 20, count 2 2006.257.08:34:17.23#ibcon#end of sib2, iclass 20, count 2 2006.257.08:34:17.23#ibcon#*mode == 0, iclass 20, count 2 2006.257.08:34:17.23#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.08:34:17.23#ibcon#[25=AT01-08\r\n] 2006.257.08:34:17.23#ibcon#*before write, iclass 20, count 2 2006.257.08:34:17.23#ibcon#enter sib2, iclass 20, count 2 2006.257.08:34:17.23#ibcon#flushed, iclass 20, count 2 2006.257.08:34:17.23#ibcon#about to write, iclass 20, count 2 2006.257.08:34:17.23#ibcon#wrote, iclass 20, count 2 2006.257.08:34:17.23#ibcon#about to read 3, iclass 20, count 2 2006.257.08:34:17.26#ibcon#read 3, iclass 20, count 2 2006.257.08:34:17.26#ibcon#about to read 4, iclass 20, count 2 2006.257.08:34:17.26#ibcon#read 4, iclass 20, count 2 2006.257.08:34:17.26#ibcon#about to read 5, iclass 20, count 2 2006.257.08:34:17.26#ibcon#read 5, iclass 20, count 2 2006.257.08:34:17.26#ibcon#about to read 6, iclass 20, count 2 2006.257.08:34:17.26#ibcon#read 6, iclass 20, count 2 2006.257.08:34:17.26#ibcon#end of sib2, iclass 20, count 2 2006.257.08:34:17.26#ibcon#*after write, iclass 20, count 2 2006.257.08:34:17.26#ibcon#*before return 0, iclass 20, count 2 2006.257.08:34:17.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:17.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:17.26#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.08:34:17.26#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:17.26#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:17.38#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:17.38#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:17.38#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:34:17.38#ibcon#first serial, iclass 20, count 0 2006.257.08:34:17.38#ibcon#enter sib2, iclass 20, count 0 2006.257.08:34:17.38#ibcon#flushed, iclass 20, count 0 2006.257.08:34:17.38#ibcon#about to write, iclass 20, count 0 2006.257.08:34:17.38#ibcon#wrote, iclass 20, count 0 2006.257.08:34:17.38#ibcon#about to read 3, iclass 20, count 0 2006.257.08:34:17.40#ibcon#read 3, iclass 20, count 0 2006.257.08:34:17.40#ibcon#about to read 4, iclass 20, count 0 2006.257.08:34:17.40#ibcon#read 4, iclass 20, count 0 2006.257.08:34:17.40#ibcon#about to read 5, iclass 20, count 0 2006.257.08:34:17.40#ibcon#read 5, iclass 20, count 0 2006.257.08:34:17.40#ibcon#about to read 6, iclass 20, count 0 2006.257.08:34:17.40#ibcon#read 6, iclass 20, count 0 2006.257.08:34:17.40#ibcon#end of sib2, iclass 20, count 0 2006.257.08:34:17.40#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:34:17.40#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:34:17.40#ibcon#[25=USB\r\n] 2006.257.08:34:17.40#ibcon#*before write, iclass 20, count 0 2006.257.08:34:17.40#ibcon#enter sib2, iclass 20, count 0 2006.257.08:34:17.40#ibcon#flushed, iclass 20, count 0 2006.257.08:34:17.40#ibcon#about to write, iclass 20, count 0 2006.257.08:34:17.40#ibcon#wrote, iclass 20, count 0 2006.257.08:34:17.40#ibcon#about to read 3, iclass 20, count 0 2006.257.08:34:17.43#ibcon#read 3, iclass 20, count 0 2006.257.08:34:17.43#ibcon#about to read 4, iclass 20, count 0 2006.257.08:34:17.43#ibcon#read 4, iclass 20, count 0 2006.257.08:34:17.43#ibcon#about to read 5, iclass 20, count 0 2006.257.08:34:17.43#ibcon#read 5, iclass 20, count 0 2006.257.08:34:17.43#ibcon#about to read 6, iclass 20, count 0 2006.257.08:34:17.43#ibcon#read 6, iclass 20, count 0 2006.257.08:34:17.43#ibcon#end of sib2, iclass 20, count 0 2006.257.08:34:17.43#ibcon#*after write, iclass 20, count 0 2006.257.08:34:17.43#ibcon#*before return 0, iclass 20, count 0 2006.257.08:34:17.43#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:17.43#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:17.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:34:17.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:34:17.43$vck44/valo=2,534.99 2006.257.08:34:17.43#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.08:34:17.43#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.08:34:17.43#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:17.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:34:17.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:34:17.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:34:17.43#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:34:17.43#ibcon#first serial, iclass 22, count 0 2006.257.08:34:17.43#ibcon#enter sib2, iclass 22, count 0 2006.257.08:34:17.43#ibcon#flushed, iclass 22, count 0 2006.257.08:34:17.43#ibcon#about to write, iclass 22, count 0 2006.257.08:34:17.43#ibcon#wrote, iclass 22, count 0 2006.257.08:34:17.43#ibcon#about to read 3, iclass 22, count 0 2006.257.08:34:17.45#ibcon#read 3, iclass 22, count 0 2006.257.08:34:17.45#ibcon#about to read 4, iclass 22, count 0 2006.257.08:34:17.45#ibcon#read 4, iclass 22, count 0 2006.257.08:34:17.45#ibcon#about to read 5, iclass 22, count 0 2006.257.08:34:17.45#ibcon#read 5, iclass 22, count 0 2006.257.08:34:17.45#ibcon#about to read 6, iclass 22, count 0 2006.257.08:34:17.45#ibcon#read 6, iclass 22, count 0 2006.257.08:34:17.45#ibcon#end of sib2, iclass 22, count 0 2006.257.08:34:17.45#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:34:17.45#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:34:17.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:34:17.45#ibcon#*before write, iclass 22, count 0 2006.257.08:34:17.45#ibcon#enter sib2, iclass 22, count 0 2006.257.08:34:17.45#ibcon#flushed, iclass 22, count 0 2006.257.08:34:17.45#ibcon#about to write, iclass 22, count 0 2006.257.08:34:17.45#ibcon#wrote, iclass 22, count 0 2006.257.08:34:17.45#ibcon#about to read 3, iclass 22, count 0 2006.257.08:34:17.49#ibcon#read 3, iclass 22, count 0 2006.257.08:34:17.49#ibcon#about to read 4, iclass 22, count 0 2006.257.08:34:17.49#ibcon#read 4, iclass 22, count 0 2006.257.08:34:17.49#ibcon#about to read 5, iclass 22, count 0 2006.257.08:34:17.49#ibcon#read 5, iclass 22, count 0 2006.257.08:34:17.49#ibcon#about to read 6, iclass 22, count 0 2006.257.08:34:17.49#ibcon#read 6, iclass 22, count 0 2006.257.08:34:17.49#ibcon#end of sib2, iclass 22, count 0 2006.257.08:34:17.49#ibcon#*after write, iclass 22, count 0 2006.257.08:34:17.49#ibcon#*before return 0, iclass 22, count 0 2006.257.08:34:17.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:34:17.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:34:17.49#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:34:17.49#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:34:17.49$vck44/va=2,7 2006.257.08:34:17.49#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.08:34:17.49#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.08:34:17.49#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:17.49#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:34:17.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:34:17.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:34:17.55#ibcon#enter wrdev, iclass 24, count 2 2006.257.08:34:17.55#ibcon#first serial, iclass 24, count 2 2006.257.08:34:17.55#ibcon#enter sib2, iclass 24, count 2 2006.257.08:34:17.55#ibcon#flushed, iclass 24, count 2 2006.257.08:34:17.55#ibcon#about to write, iclass 24, count 2 2006.257.08:34:17.55#ibcon#wrote, iclass 24, count 2 2006.257.08:34:17.55#ibcon#about to read 3, iclass 24, count 2 2006.257.08:34:17.57#ibcon#read 3, iclass 24, count 2 2006.257.08:34:17.57#ibcon#about to read 4, iclass 24, count 2 2006.257.08:34:17.57#ibcon#read 4, iclass 24, count 2 2006.257.08:34:17.57#ibcon#about to read 5, iclass 24, count 2 2006.257.08:34:17.57#ibcon#read 5, iclass 24, count 2 2006.257.08:34:17.57#ibcon#about to read 6, iclass 24, count 2 2006.257.08:34:17.57#ibcon#read 6, iclass 24, count 2 2006.257.08:34:17.57#ibcon#end of sib2, iclass 24, count 2 2006.257.08:34:17.57#ibcon#*mode == 0, iclass 24, count 2 2006.257.08:34:17.57#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.08:34:17.57#ibcon#[25=AT02-07\r\n] 2006.257.08:34:17.57#ibcon#*before write, iclass 24, count 2 2006.257.08:34:17.57#ibcon#enter sib2, iclass 24, count 2 2006.257.08:34:17.57#ibcon#flushed, iclass 24, count 2 2006.257.08:34:17.57#ibcon#about to write, iclass 24, count 2 2006.257.08:34:17.57#ibcon#wrote, iclass 24, count 2 2006.257.08:34:17.57#ibcon#about to read 3, iclass 24, count 2 2006.257.08:34:17.60#ibcon#read 3, iclass 24, count 2 2006.257.08:34:17.60#ibcon#about to read 4, iclass 24, count 2 2006.257.08:34:17.60#ibcon#read 4, iclass 24, count 2 2006.257.08:34:17.60#ibcon#about to read 5, iclass 24, count 2 2006.257.08:34:17.60#ibcon#read 5, iclass 24, count 2 2006.257.08:34:17.60#ibcon#about to read 6, iclass 24, count 2 2006.257.08:34:17.60#ibcon#read 6, iclass 24, count 2 2006.257.08:34:17.60#ibcon#end of sib2, iclass 24, count 2 2006.257.08:34:17.60#ibcon#*after write, iclass 24, count 2 2006.257.08:34:17.60#ibcon#*before return 0, iclass 24, count 2 2006.257.08:34:17.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:34:17.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:34:17.60#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.08:34:17.60#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:17.60#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:34:17.72#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:34:17.72#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:34:17.72#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:34:17.72#ibcon#first serial, iclass 24, count 0 2006.257.08:34:17.72#ibcon#enter sib2, iclass 24, count 0 2006.257.08:34:17.72#ibcon#flushed, iclass 24, count 0 2006.257.08:34:17.72#ibcon#about to write, iclass 24, count 0 2006.257.08:34:17.72#ibcon#wrote, iclass 24, count 0 2006.257.08:34:17.72#ibcon#about to read 3, iclass 24, count 0 2006.257.08:34:17.74#ibcon#read 3, iclass 24, count 0 2006.257.08:34:17.74#ibcon#about to read 4, iclass 24, count 0 2006.257.08:34:17.74#ibcon#read 4, iclass 24, count 0 2006.257.08:34:17.74#ibcon#about to read 5, iclass 24, count 0 2006.257.08:34:17.74#ibcon#read 5, iclass 24, count 0 2006.257.08:34:17.74#ibcon#about to read 6, iclass 24, count 0 2006.257.08:34:17.74#ibcon#read 6, iclass 24, count 0 2006.257.08:34:17.74#ibcon#end of sib2, iclass 24, count 0 2006.257.08:34:17.74#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:34:17.74#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:34:17.74#ibcon#[25=USB\r\n] 2006.257.08:34:17.74#ibcon#*before write, iclass 24, count 0 2006.257.08:34:17.74#ibcon#enter sib2, iclass 24, count 0 2006.257.08:34:17.74#ibcon#flushed, iclass 24, count 0 2006.257.08:34:17.74#ibcon#about to write, iclass 24, count 0 2006.257.08:34:17.74#ibcon#wrote, iclass 24, count 0 2006.257.08:34:17.74#ibcon#about to read 3, iclass 24, count 0 2006.257.08:34:17.77#ibcon#read 3, iclass 24, count 0 2006.257.08:34:17.77#ibcon#about to read 4, iclass 24, count 0 2006.257.08:34:17.77#ibcon#read 4, iclass 24, count 0 2006.257.08:34:17.77#ibcon#about to read 5, iclass 24, count 0 2006.257.08:34:17.77#ibcon#read 5, iclass 24, count 0 2006.257.08:34:17.77#ibcon#about to read 6, iclass 24, count 0 2006.257.08:34:17.77#ibcon#read 6, iclass 24, count 0 2006.257.08:34:17.77#ibcon#end of sib2, iclass 24, count 0 2006.257.08:34:17.77#ibcon#*after write, iclass 24, count 0 2006.257.08:34:17.77#ibcon#*before return 0, iclass 24, count 0 2006.257.08:34:17.77#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:34:17.77#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:34:17.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:34:17.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:34:17.77$vck44/valo=3,564.99 2006.257.08:34:17.77#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.08:34:17.77#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.08:34:17.77#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:17.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:17.77#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:17.77#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:17.77#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:34:17.77#ibcon#first serial, iclass 26, count 0 2006.257.08:34:17.77#ibcon#enter sib2, iclass 26, count 0 2006.257.08:34:17.77#ibcon#flushed, iclass 26, count 0 2006.257.08:34:17.77#ibcon#about to write, iclass 26, count 0 2006.257.08:34:17.77#ibcon#wrote, iclass 26, count 0 2006.257.08:34:17.77#ibcon#about to read 3, iclass 26, count 0 2006.257.08:34:17.79#ibcon#read 3, iclass 26, count 0 2006.257.08:34:17.79#ibcon#about to read 4, iclass 26, count 0 2006.257.08:34:17.79#ibcon#read 4, iclass 26, count 0 2006.257.08:34:17.79#ibcon#about to read 5, iclass 26, count 0 2006.257.08:34:17.79#ibcon#read 5, iclass 26, count 0 2006.257.08:34:17.79#ibcon#about to read 6, iclass 26, count 0 2006.257.08:34:17.79#ibcon#read 6, iclass 26, count 0 2006.257.08:34:17.79#ibcon#end of sib2, iclass 26, count 0 2006.257.08:34:17.79#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:34:17.79#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:34:17.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:34:17.79#ibcon#*before write, iclass 26, count 0 2006.257.08:34:17.79#ibcon#enter sib2, iclass 26, count 0 2006.257.08:34:17.79#ibcon#flushed, iclass 26, count 0 2006.257.08:34:17.79#ibcon#about to write, iclass 26, count 0 2006.257.08:34:17.79#ibcon#wrote, iclass 26, count 0 2006.257.08:34:17.79#ibcon#about to read 3, iclass 26, count 0 2006.257.08:34:17.83#ibcon#read 3, iclass 26, count 0 2006.257.08:34:17.83#ibcon#about to read 4, iclass 26, count 0 2006.257.08:34:17.83#ibcon#read 4, iclass 26, count 0 2006.257.08:34:17.83#ibcon#about to read 5, iclass 26, count 0 2006.257.08:34:17.83#ibcon#read 5, iclass 26, count 0 2006.257.08:34:17.83#ibcon#about to read 6, iclass 26, count 0 2006.257.08:34:17.83#ibcon#read 6, iclass 26, count 0 2006.257.08:34:17.83#ibcon#end of sib2, iclass 26, count 0 2006.257.08:34:17.83#ibcon#*after write, iclass 26, count 0 2006.257.08:34:17.83#ibcon#*before return 0, iclass 26, count 0 2006.257.08:34:17.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:17.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:17.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:34:17.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:34:17.83$vck44/va=3,8 2006.257.08:34:17.83#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.08:34:17.83#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.08:34:17.83#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:17.83#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:17.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:17.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:17.89#ibcon#enter wrdev, iclass 28, count 2 2006.257.08:34:17.89#ibcon#first serial, iclass 28, count 2 2006.257.08:34:17.89#ibcon#enter sib2, iclass 28, count 2 2006.257.08:34:17.89#ibcon#flushed, iclass 28, count 2 2006.257.08:34:17.89#ibcon#about to write, iclass 28, count 2 2006.257.08:34:17.89#ibcon#wrote, iclass 28, count 2 2006.257.08:34:17.89#ibcon#about to read 3, iclass 28, count 2 2006.257.08:34:17.91#ibcon#read 3, iclass 28, count 2 2006.257.08:34:17.91#ibcon#about to read 4, iclass 28, count 2 2006.257.08:34:17.91#ibcon#read 4, iclass 28, count 2 2006.257.08:34:17.91#ibcon#about to read 5, iclass 28, count 2 2006.257.08:34:17.91#ibcon#read 5, iclass 28, count 2 2006.257.08:34:17.91#ibcon#about to read 6, iclass 28, count 2 2006.257.08:34:17.91#ibcon#read 6, iclass 28, count 2 2006.257.08:34:17.91#ibcon#end of sib2, iclass 28, count 2 2006.257.08:34:17.91#ibcon#*mode == 0, iclass 28, count 2 2006.257.08:34:17.91#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.08:34:17.91#ibcon#[25=AT03-08\r\n] 2006.257.08:34:17.91#ibcon#*before write, iclass 28, count 2 2006.257.08:34:17.91#ibcon#enter sib2, iclass 28, count 2 2006.257.08:34:17.91#ibcon#flushed, iclass 28, count 2 2006.257.08:34:17.91#ibcon#about to write, iclass 28, count 2 2006.257.08:34:17.91#ibcon#wrote, iclass 28, count 2 2006.257.08:34:17.91#ibcon#about to read 3, iclass 28, count 2 2006.257.08:34:17.94#ibcon#read 3, iclass 28, count 2 2006.257.08:34:17.94#ibcon#about to read 4, iclass 28, count 2 2006.257.08:34:17.94#ibcon#read 4, iclass 28, count 2 2006.257.08:34:17.94#ibcon#about to read 5, iclass 28, count 2 2006.257.08:34:17.94#ibcon#read 5, iclass 28, count 2 2006.257.08:34:17.94#ibcon#about to read 6, iclass 28, count 2 2006.257.08:34:17.94#ibcon#read 6, iclass 28, count 2 2006.257.08:34:17.94#ibcon#end of sib2, iclass 28, count 2 2006.257.08:34:17.94#ibcon#*after write, iclass 28, count 2 2006.257.08:34:17.94#ibcon#*before return 0, iclass 28, count 2 2006.257.08:34:17.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:17.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:17.94#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.08:34:17.94#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:17.94#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:18.06#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:18.06#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:18.06#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:34:18.06#ibcon#first serial, iclass 28, count 0 2006.257.08:34:18.06#ibcon#enter sib2, iclass 28, count 0 2006.257.08:34:18.06#ibcon#flushed, iclass 28, count 0 2006.257.08:34:18.06#ibcon#about to write, iclass 28, count 0 2006.257.08:34:18.06#ibcon#wrote, iclass 28, count 0 2006.257.08:34:18.06#ibcon#about to read 3, iclass 28, count 0 2006.257.08:34:18.08#ibcon#read 3, iclass 28, count 0 2006.257.08:34:18.08#ibcon#about to read 4, iclass 28, count 0 2006.257.08:34:18.08#ibcon#read 4, iclass 28, count 0 2006.257.08:34:18.08#ibcon#about to read 5, iclass 28, count 0 2006.257.08:34:18.08#ibcon#read 5, iclass 28, count 0 2006.257.08:34:18.08#ibcon#about to read 6, iclass 28, count 0 2006.257.08:34:18.08#ibcon#read 6, iclass 28, count 0 2006.257.08:34:18.08#ibcon#end of sib2, iclass 28, count 0 2006.257.08:34:18.08#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:34:18.08#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:34:18.08#ibcon#[25=USB\r\n] 2006.257.08:34:18.08#ibcon#*before write, iclass 28, count 0 2006.257.08:34:18.08#ibcon#enter sib2, iclass 28, count 0 2006.257.08:34:18.08#ibcon#flushed, iclass 28, count 0 2006.257.08:34:18.08#ibcon#about to write, iclass 28, count 0 2006.257.08:34:18.08#ibcon#wrote, iclass 28, count 0 2006.257.08:34:18.08#ibcon#about to read 3, iclass 28, count 0 2006.257.08:34:18.11#ibcon#read 3, iclass 28, count 0 2006.257.08:34:18.11#ibcon#about to read 4, iclass 28, count 0 2006.257.08:34:18.11#ibcon#read 4, iclass 28, count 0 2006.257.08:34:18.11#ibcon#about to read 5, iclass 28, count 0 2006.257.08:34:18.11#ibcon#read 5, iclass 28, count 0 2006.257.08:34:18.11#ibcon#about to read 6, iclass 28, count 0 2006.257.08:34:18.11#ibcon#read 6, iclass 28, count 0 2006.257.08:34:18.11#ibcon#end of sib2, iclass 28, count 0 2006.257.08:34:18.11#ibcon#*after write, iclass 28, count 0 2006.257.08:34:18.11#ibcon#*before return 0, iclass 28, count 0 2006.257.08:34:18.11#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:18.11#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:18.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:34:18.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:34:18.11$vck44/valo=4,624.99 2006.257.08:34:18.11#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.08:34:18.11#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.08:34:18.11#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:18.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:18.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:18.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:18.11#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:34:18.11#ibcon#first serial, iclass 30, count 0 2006.257.08:34:18.11#ibcon#enter sib2, iclass 30, count 0 2006.257.08:34:18.11#ibcon#flushed, iclass 30, count 0 2006.257.08:34:18.11#ibcon#about to write, iclass 30, count 0 2006.257.08:34:18.11#ibcon#wrote, iclass 30, count 0 2006.257.08:34:18.11#ibcon#about to read 3, iclass 30, count 0 2006.257.08:34:18.13#ibcon#read 3, iclass 30, count 0 2006.257.08:34:18.13#ibcon#about to read 4, iclass 30, count 0 2006.257.08:34:18.13#ibcon#read 4, iclass 30, count 0 2006.257.08:34:18.13#ibcon#about to read 5, iclass 30, count 0 2006.257.08:34:18.13#ibcon#read 5, iclass 30, count 0 2006.257.08:34:18.13#ibcon#about to read 6, iclass 30, count 0 2006.257.08:34:18.13#ibcon#read 6, iclass 30, count 0 2006.257.08:34:18.13#ibcon#end of sib2, iclass 30, count 0 2006.257.08:34:18.13#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:34:18.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:34:18.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:34:18.13#ibcon#*before write, iclass 30, count 0 2006.257.08:34:18.13#ibcon#enter sib2, iclass 30, count 0 2006.257.08:34:18.13#ibcon#flushed, iclass 30, count 0 2006.257.08:34:18.13#ibcon#about to write, iclass 30, count 0 2006.257.08:34:18.13#ibcon#wrote, iclass 30, count 0 2006.257.08:34:18.13#ibcon#about to read 3, iclass 30, count 0 2006.257.08:34:18.17#ibcon#read 3, iclass 30, count 0 2006.257.08:34:18.17#ibcon#about to read 4, iclass 30, count 0 2006.257.08:34:18.17#ibcon#read 4, iclass 30, count 0 2006.257.08:34:18.17#ibcon#about to read 5, iclass 30, count 0 2006.257.08:34:18.17#ibcon#read 5, iclass 30, count 0 2006.257.08:34:18.17#ibcon#about to read 6, iclass 30, count 0 2006.257.08:34:18.17#ibcon#read 6, iclass 30, count 0 2006.257.08:34:18.17#ibcon#end of sib2, iclass 30, count 0 2006.257.08:34:18.17#ibcon#*after write, iclass 30, count 0 2006.257.08:34:18.17#ibcon#*before return 0, iclass 30, count 0 2006.257.08:34:18.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:18.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:18.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:34:18.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:34:18.17$vck44/va=4,7 2006.257.08:34:18.17#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.08:34:18.17#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.08:34:18.17#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:18.17#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:18.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:18.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:18.23#ibcon#enter wrdev, iclass 32, count 2 2006.257.08:34:18.23#ibcon#first serial, iclass 32, count 2 2006.257.08:34:18.23#ibcon#enter sib2, iclass 32, count 2 2006.257.08:34:18.23#ibcon#flushed, iclass 32, count 2 2006.257.08:34:18.23#ibcon#about to write, iclass 32, count 2 2006.257.08:34:18.23#ibcon#wrote, iclass 32, count 2 2006.257.08:34:18.23#ibcon#about to read 3, iclass 32, count 2 2006.257.08:34:18.25#ibcon#read 3, iclass 32, count 2 2006.257.08:34:18.25#ibcon#about to read 4, iclass 32, count 2 2006.257.08:34:18.25#ibcon#read 4, iclass 32, count 2 2006.257.08:34:18.25#ibcon#about to read 5, iclass 32, count 2 2006.257.08:34:18.25#ibcon#read 5, iclass 32, count 2 2006.257.08:34:18.25#ibcon#about to read 6, iclass 32, count 2 2006.257.08:34:18.25#ibcon#read 6, iclass 32, count 2 2006.257.08:34:18.25#ibcon#end of sib2, iclass 32, count 2 2006.257.08:34:18.25#ibcon#*mode == 0, iclass 32, count 2 2006.257.08:34:18.25#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.08:34:18.25#ibcon#[25=AT04-07\r\n] 2006.257.08:34:18.25#ibcon#*before write, iclass 32, count 2 2006.257.08:34:18.25#ibcon#enter sib2, iclass 32, count 2 2006.257.08:34:18.25#ibcon#flushed, iclass 32, count 2 2006.257.08:34:18.25#ibcon#about to write, iclass 32, count 2 2006.257.08:34:18.25#ibcon#wrote, iclass 32, count 2 2006.257.08:34:18.25#ibcon#about to read 3, iclass 32, count 2 2006.257.08:34:18.28#ibcon#read 3, iclass 32, count 2 2006.257.08:34:18.28#ibcon#about to read 4, iclass 32, count 2 2006.257.08:34:18.28#ibcon#read 4, iclass 32, count 2 2006.257.08:34:18.28#ibcon#about to read 5, iclass 32, count 2 2006.257.08:34:18.28#ibcon#read 5, iclass 32, count 2 2006.257.08:34:18.28#ibcon#about to read 6, iclass 32, count 2 2006.257.08:34:18.28#ibcon#read 6, iclass 32, count 2 2006.257.08:34:18.28#ibcon#end of sib2, iclass 32, count 2 2006.257.08:34:18.28#ibcon#*after write, iclass 32, count 2 2006.257.08:34:18.28#ibcon#*before return 0, iclass 32, count 2 2006.257.08:34:18.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:18.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:18.28#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.08:34:18.28#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:18.28#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:18.40#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:18.40#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:18.40#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:34:18.40#ibcon#first serial, iclass 32, count 0 2006.257.08:34:18.40#ibcon#enter sib2, iclass 32, count 0 2006.257.08:34:18.40#ibcon#flushed, iclass 32, count 0 2006.257.08:34:18.40#ibcon#about to write, iclass 32, count 0 2006.257.08:34:18.40#ibcon#wrote, iclass 32, count 0 2006.257.08:34:18.40#ibcon#about to read 3, iclass 32, count 0 2006.257.08:34:18.42#ibcon#read 3, iclass 32, count 0 2006.257.08:34:18.42#ibcon#about to read 4, iclass 32, count 0 2006.257.08:34:18.42#ibcon#read 4, iclass 32, count 0 2006.257.08:34:18.42#ibcon#about to read 5, iclass 32, count 0 2006.257.08:34:18.42#ibcon#read 5, iclass 32, count 0 2006.257.08:34:18.42#ibcon#about to read 6, iclass 32, count 0 2006.257.08:34:18.42#ibcon#read 6, iclass 32, count 0 2006.257.08:34:18.42#ibcon#end of sib2, iclass 32, count 0 2006.257.08:34:18.42#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:34:18.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:34:18.42#ibcon#[25=USB\r\n] 2006.257.08:34:18.42#ibcon#*before write, iclass 32, count 0 2006.257.08:34:18.42#ibcon#enter sib2, iclass 32, count 0 2006.257.08:34:18.42#ibcon#flushed, iclass 32, count 0 2006.257.08:34:18.42#ibcon#about to write, iclass 32, count 0 2006.257.08:34:18.42#ibcon#wrote, iclass 32, count 0 2006.257.08:34:18.42#ibcon#about to read 3, iclass 32, count 0 2006.257.08:34:18.45#ibcon#read 3, iclass 32, count 0 2006.257.08:34:18.45#ibcon#about to read 4, iclass 32, count 0 2006.257.08:34:18.45#ibcon#read 4, iclass 32, count 0 2006.257.08:34:18.45#ibcon#about to read 5, iclass 32, count 0 2006.257.08:34:18.45#ibcon#read 5, iclass 32, count 0 2006.257.08:34:18.45#ibcon#about to read 6, iclass 32, count 0 2006.257.08:34:18.45#ibcon#read 6, iclass 32, count 0 2006.257.08:34:18.45#ibcon#end of sib2, iclass 32, count 0 2006.257.08:34:18.45#ibcon#*after write, iclass 32, count 0 2006.257.08:34:18.45#ibcon#*before return 0, iclass 32, count 0 2006.257.08:34:18.45#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:18.45#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:18.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:34:18.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:34:18.45$vck44/valo=5,734.99 2006.257.08:34:18.45#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.08:34:18.45#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.08:34:18.45#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:18.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:18.45#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:18.45#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:18.45#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:34:18.45#ibcon#first serial, iclass 34, count 0 2006.257.08:34:18.45#ibcon#enter sib2, iclass 34, count 0 2006.257.08:34:18.45#ibcon#flushed, iclass 34, count 0 2006.257.08:34:18.45#ibcon#about to write, iclass 34, count 0 2006.257.08:34:18.45#ibcon#wrote, iclass 34, count 0 2006.257.08:34:18.45#ibcon#about to read 3, iclass 34, count 0 2006.257.08:34:18.47#ibcon#read 3, iclass 34, count 0 2006.257.08:34:18.47#ibcon#about to read 4, iclass 34, count 0 2006.257.08:34:18.47#ibcon#read 4, iclass 34, count 0 2006.257.08:34:18.47#ibcon#about to read 5, iclass 34, count 0 2006.257.08:34:18.47#ibcon#read 5, iclass 34, count 0 2006.257.08:34:18.47#ibcon#about to read 6, iclass 34, count 0 2006.257.08:34:18.47#ibcon#read 6, iclass 34, count 0 2006.257.08:34:18.47#ibcon#end of sib2, iclass 34, count 0 2006.257.08:34:18.47#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:34:18.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:34:18.47#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:34:18.47#ibcon#*before write, iclass 34, count 0 2006.257.08:34:18.47#ibcon#enter sib2, iclass 34, count 0 2006.257.08:34:18.47#ibcon#flushed, iclass 34, count 0 2006.257.08:34:18.47#ibcon#about to write, iclass 34, count 0 2006.257.08:34:18.47#ibcon#wrote, iclass 34, count 0 2006.257.08:34:18.47#ibcon#about to read 3, iclass 34, count 0 2006.257.08:34:18.51#ibcon#read 3, iclass 34, count 0 2006.257.08:34:18.51#ibcon#about to read 4, iclass 34, count 0 2006.257.08:34:18.51#ibcon#read 4, iclass 34, count 0 2006.257.08:34:18.51#ibcon#about to read 5, iclass 34, count 0 2006.257.08:34:18.51#ibcon#read 5, iclass 34, count 0 2006.257.08:34:18.51#ibcon#about to read 6, iclass 34, count 0 2006.257.08:34:18.51#ibcon#read 6, iclass 34, count 0 2006.257.08:34:18.51#ibcon#end of sib2, iclass 34, count 0 2006.257.08:34:18.51#ibcon#*after write, iclass 34, count 0 2006.257.08:34:18.51#ibcon#*before return 0, iclass 34, count 0 2006.257.08:34:18.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:18.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:18.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:34:18.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:34:18.51$vck44/va=5,4 2006.257.08:34:18.51#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.08:34:18.51#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.08:34:18.51#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:18.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:18.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:18.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:18.57#ibcon#enter wrdev, iclass 36, count 2 2006.257.08:34:18.57#ibcon#first serial, iclass 36, count 2 2006.257.08:34:18.57#ibcon#enter sib2, iclass 36, count 2 2006.257.08:34:18.57#ibcon#flushed, iclass 36, count 2 2006.257.08:34:18.57#ibcon#about to write, iclass 36, count 2 2006.257.08:34:18.57#ibcon#wrote, iclass 36, count 2 2006.257.08:34:18.57#ibcon#about to read 3, iclass 36, count 2 2006.257.08:34:18.59#ibcon#read 3, iclass 36, count 2 2006.257.08:34:18.59#ibcon#about to read 4, iclass 36, count 2 2006.257.08:34:18.59#ibcon#read 4, iclass 36, count 2 2006.257.08:34:18.59#ibcon#about to read 5, iclass 36, count 2 2006.257.08:34:18.59#ibcon#read 5, iclass 36, count 2 2006.257.08:34:18.59#ibcon#about to read 6, iclass 36, count 2 2006.257.08:34:18.59#ibcon#read 6, iclass 36, count 2 2006.257.08:34:18.59#ibcon#end of sib2, iclass 36, count 2 2006.257.08:34:18.59#ibcon#*mode == 0, iclass 36, count 2 2006.257.08:34:18.59#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.08:34:18.59#ibcon#[25=AT05-04\r\n] 2006.257.08:34:18.59#ibcon#*before write, iclass 36, count 2 2006.257.08:34:18.59#ibcon#enter sib2, iclass 36, count 2 2006.257.08:34:18.59#ibcon#flushed, iclass 36, count 2 2006.257.08:34:18.59#ibcon#about to write, iclass 36, count 2 2006.257.08:34:18.59#ibcon#wrote, iclass 36, count 2 2006.257.08:34:18.59#ibcon#about to read 3, iclass 36, count 2 2006.257.08:34:18.62#ibcon#read 3, iclass 36, count 2 2006.257.08:34:18.62#ibcon#about to read 4, iclass 36, count 2 2006.257.08:34:18.62#ibcon#read 4, iclass 36, count 2 2006.257.08:34:18.62#ibcon#about to read 5, iclass 36, count 2 2006.257.08:34:18.62#ibcon#read 5, iclass 36, count 2 2006.257.08:34:18.62#ibcon#about to read 6, iclass 36, count 2 2006.257.08:34:18.62#ibcon#read 6, iclass 36, count 2 2006.257.08:34:18.62#ibcon#end of sib2, iclass 36, count 2 2006.257.08:34:18.62#ibcon#*after write, iclass 36, count 2 2006.257.08:34:18.62#ibcon#*before return 0, iclass 36, count 2 2006.257.08:34:18.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:18.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:18.62#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.08:34:18.62#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:18.62#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:18.74#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:18.74#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:18.74#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:34:18.74#ibcon#first serial, iclass 36, count 0 2006.257.08:34:18.74#ibcon#enter sib2, iclass 36, count 0 2006.257.08:34:18.74#ibcon#flushed, iclass 36, count 0 2006.257.08:34:18.74#ibcon#about to write, iclass 36, count 0 2006.257.08:34:18.74#ibcon#wrote, iclass 36, count 0 2006.257.08:34:18.74#ibcon#about to read 3, iclass 36, count 0 2006.257.08:34:18.76#ibcon#read 3, iclass 36, count 0 2006.257.08:34:18.76#ibcon#about to read 4, iclass 36, count 0 2006.257.08:34:18.76#ibcon#read 4, iclass 36, count 0 2006.257.08:34:18.76#ibcon#about to read 5, iclass 36, count 0 2006.257.08:34:18.76#ibcon#read 5, iclass 36, count 0 2006.257.08:34:18.76#ibcon#about to read 6, iclass 36, count 0 2006.257.08:34:18.76#ibcon#read 6, iclass 36, count 0 2006.257.08:34:18.76#ibcon#end of sib2, iclass 36, count 0 2006.257.08:34:18.76#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:34:18.76#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:34:18.76#ibcon#[25=USB\r\n] 2006.257.08:34:18.76#ibcon#*before write, iclass 36, count 0 2006.257.08:34:18.76#ibcon#enter sib2, iclass 36, count 0 2006.257.08:34:18.76#ibcon#flushed, iclass 36, count 0 2006.257.08:34:18.76#ibcon#about to write, iclass 36, count 0 2006.257.08:34:18.76#ibcon#wrote, iclass 36, count 0 2006.257.08:34:18.76#ibcon#about to read 3, iclass 36, count 0 2006.257.08:34:18.79#ibcon#read 3, iclass 36, count 0 2006.257.08:34:18.79#ibcon#about to read 4, iclass 36, count 0 2006.257.08:34:18.79#ibcon#read 4, iclass 36, count 0 2006.257.08:34:18.79#ibcon#about to read 5, iclass 36, count 0 2006.257.08:34:18.79#ibcon#read 5, iclass 36, count 0 2006.257.08:34:18.79#ibcon#about to read 6, iclass 36, count 0 2006.257.08:34:18.79#ibcon#read 6, iclass 36, count 0 2006.257.08:34:18.79#ibcon#end of sib2, iclass 36, count 0 2006.257.08:34:18.79#ibcon#*after write, iclass 36, count 0 2006.257.08:34:18.79#ibcon#*before return 0, iclass 36, count 0 2006.257.08:34:18.79#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:18.79#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:18.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:34:18.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:34:18.79$vck44/valo=6,814.99 2006.257.08:34:18.79#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.08:34:18.79#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.08:34:18.79#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:18.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:18.79#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:18.79#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:18.79#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:34:18.79#ibcon#first serial, iclass 38, count 0 2006.257.08:34:18.79#ibcon#enter sib2, iclass 38, count 0 2006.257.08:34:18.79#ibcon#flushed, iclass 38, count 0 2006.257.08:34:18.79#ibcon#about to write, iclass 38, count 0 2006.257.08:34:18.79#ibcon#wrote, iclass 38, count 0 2006.257.08:34:18.79#ibcon#about to read 3, iclass 38, count 0 2006.257.08:34:18.81#ibcon#read 3, iclass 38, count 0 2006.257.08:34:18.81#ibcon#about to read 4, iclass 38, count 0 2006.257.08:34:18.81#ibcon#read 4, iclass 38, count 0 2006.257.08:34:18.81#ibcon#about to read 5, iclass 38, count 0 2006.257.08:34:18.81#ibcon#read 5, iclass 38, count 0 2006.257.08:34:18.81#ibcon#about to read 6, iclass 38, count 0 2006.257.08:34:18.81#ibcon#read 6, iclass 38, count 0 2006.257.08:34:18.81#ibcon#end of sib2, iclass 38, count 0 2006.257.08:34:18.81#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:34:18.81#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:34:18.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:34:18.81#ibcon#*before write, iclass 38, count 0 2006.257.08:34:18.81#ibcon#enter sib2, iclass 38, count 0 2006.257.08:34:18.81#ibcon#flushed, iclass 38, count 0 2006.257.08:34:18.81#ibcon#about to write, iclass 38, count 0 2006.257.08:34:18.81#ibcon#wrote, iclass 38, count 0 2006.257.08:34:18.81#ibcon#about to read 3, iclass 38, count 0 2006.257.08:34:18.85#ibcon#read 3, iclass 38, count 0 2006.257.08:34:18.85#ibcon#about to read 4, iclass 38, count 0 2006.257.08:34:18.85#ibcon#read 4, iclass 38, count 0 2006.257.08:34:18.85#ibcon#about to read 5, iclass 38, count 0 2006.257.08:34:18.85#ibcon#read 5, iclass 38, count 0 2006.257.08:34:18.85#ibcon#about to read 6, iclass 38, count 0 2006.257.08:34:18.85#ibcon#read 6, iclass 38, count 0 2006.257.08:34:18.85#ibcon#end of sib2, iclass 38, count 0 2006.257.08:34:18.85#ibcon#*after write, iclass 38, count 0 2006.257.08:34:18.85#ibcon#*before return 0, iclass 38, count 0 2006.257.08:34:18.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:18.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:18.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:34:18.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:34:18.85$vck44/va=6,4 2006.257.08:34:18.85#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.08:34:18.85#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.08:34:18.85#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:18.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:18.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:18.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:18.91#ibcon#enter wrdev, iclass 40, count 2 2006.257.08:34:18.91#ibcon#first serial, iclass 40, count 2 2006.257.08:34:18.91#ibcon#enter sib2, iclass 40, count 2 2006.257.08:34:18.91#ibcon#flushed, iclass 40, count 2 2006.257.08:34:18.91#ibcon#about to write, iclass 40, count 2 2006.257.08:34:18.91#ibcon#wrote, iclass 40, count 2 2006.257.08:34:18.91#ibcon#about to read 3, iclass 40, count 2 2006.257.08:34:18.93#ibcon#read 3, iclass 40, count 2 2006.257.08:34:18.93#ibcon#about to read 4, iclass 40, count 2 2006.257.08:34:18.93#ibcon#read 4, iclass 40, count 2 2006.257.08:34:18.93#ibcon#about to read 5, iclass 40, count 2 2006.257.08:34:18.93#ibcon#read 5, iclass 40, count 2 2006.257.08:34:18.93#ibcon#about to read 6, iclass 40, count 2 2006.257.08:34:18.93#ibcon#read 6, iclass 40, count 2 2006.257.08:34:18.93#ibcon#end of sib2, iclass 40, count 2 2006.257.08:34:18.93#ibcon#*mode == 0, iclass 40, count 2 2006.257.08:34:18.93#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.08:34:18.93#ibcon#[25=AT06-04\r\n] 2006.257.08:34:18.93#ibcon#*before write, iclass 40, count 2 2006.257.08:34:18.93#ibcon#enter sib2, iclass 40, count 2 2006.257.08:34:18.93#ibcon#flushed, iclass 40, count 2 2006.257.08:34:18.93#ibcon#about to write, iclass 40, count 2 2006.257.08:34:18.93#ibcon#wrote, iclass 40, count 2 2006.257.08:34:18.93#ibcon#about to read 3, iclass 40, count 2 2006.257.08:34:18.96#ibcon#read 3, iclass 40, count 2 2006.257.08:34:18.96#ibcon#about to read 4, iclass 40, count 2 2006.257.08:34:18.96#ibcon#read 4, iclass 40, count 2 2006.257.08:34:18.96#ibcon#about to read 5, iclass 40, count 2 2006.257.08:34:18.96#ibcon#read 5, iclass 40, count 2 2006.257.08:34:18.96#ibcon#about to read 6, iclass 40, count 2 2006.257.08:34:18.96#ibcon#read 6, iclass 40, count 2 2006.257.08:34:18.96#ibcon#end of sib2, iclass 40, count 2 2006.257.08:34:18.96#ibcon#*after write, iclass 40, count 2 2006.257.08:34:18.96#ibcon#*before return 0, iclass 40, count 2 2006.257.08:34:18.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:18.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:18.96#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.08:34:18.96#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:18.96#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:19.08#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:19.08#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:19.08#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:34:19.08#ibcon#first serial, iclass 40, count 0 2006.257.08:34:19.08#ibcon#enter sib2, iclass 40, count 0 2006.257.08:34:19.08#ibcon#flushed, iclass 40, count 0 2006.257.08:34:19.08#ibcon#about to write, iclass 40, count 0 2006.257.08:34:19.08#ibcon#wrote, iclass 40, count 0 2006.257.08:34:19.08#ibcon#about to read 3, iclass 40, count 0 2006.257.08:34:19.10#ibcon#read 3, iclass 40, count 0 2006.257.08:34:19.10#ibcon#about to read 4, iclass 40, count 0 2006.257.08:34:19.10#ibcon#read 4, iclass 40, count 0 2006.257.08:34:19.10#ibcon#about to read 5, iclass 40, count 0 2006.257.08:34:19.10#ibcon#read 5, iclass 40, count 0 2006.257.08:34:19.10#ibcon#about to read 6, iclass 40, count 0 2006.257.08:34:19.10#ibcon#read 6, iclass 40, count 0 2006.257.08:34:19.10#ibcon#end of sib2, iclass 40, count 0 2006.257.08:34:19.10#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:34:19.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:34:19.10#ibcon#[25=USB\r\n] 2006.257.08:34:19.10#ibcon#*before write, iclass 40, count 0 2006.257.08:34:19.10#ibcon#enter sib2, iclass 40, count 0 2006.257.08:34:19.10#ibcon#flushed, iclass 40, count 0 2006.257.08:34:19.10#ibcon#about to write, iclass 40, count 0 2006.257.08:34:19.10#ibcon#wrote, iclass 40, count 0 2006.257.08:34:19.10#ibcon#about to read 3, iclass 40, count 0 2006.257.08:34:19.13#ibcon#read 3, iclass 40, count 0 2006.257.08:34:19.13#ibcon#about to read 4, iclass 40, count 0 2006.257.08:34:19.13#ibcon#read 4, iclass 40, count 0 2006.257.08:34:19.13#ibcon#about to read 5, iclass 40, count 0 2006.257.08:34:19.13#ibcon#read 5, iclass 40, count 0 2006.257.08:34:19.13#ibcon#about to read 6, iclass 40, count 0 2006.257.08:34:19.13#ibcon#read 6, iclass 40, count 0 2006.257.08:34:19.13#ibcon#end of sib2, iclass 40, count 0 2006.257.08:34:19.13#ibcon#*after write, iclass 40, count 0 2006.257.08:34:19.13#ibcon#*before return 0, iclass 40, count 0 2006.257.08:34:19.13#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:19.13#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:19.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:34:19.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:34:19.13$vck44/valo=7,864.99 2006.257.08:34:19.13#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.08:34:19.13#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.08:34:19.13#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:19.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:19.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:19.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:19.13#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:34:19.13#ibcon#first serial, iclass 4, count 0 2006.257.08:34:19.13#ibcon#enter sib2, iclass 4, count 0 2006.257.08:34:19.13#ibcon#flushed, iclass 4, count 0 2006.257.08:34:19.13#ibcon#about to write, iclass 4, count 0 2006.257.08:34:19.13#ibcon#wrote, iclass 4, count 0 2006.257.08:34:19.13#ibcon#about to read 3, iclass 4, count 0 2006.257.08:34:19.15#ibcon#read 3, iclass 4, count 0 2006.257.08:34:19.15#ibcon#about to read 4, iclass 4, count 0 2006.257.08:34:19.15#ibcon#read 4, iclass 4, count 0 2006.257.08:34:19.15#ibcon#about to read 5, iclass 4, count 0 2006.257.08:34:19.15#ibcon#read 5, iclass 4, count 0 2006.257.08:34:19.15#ibcon#about to read 6, iclass 4, count 0 2006.257.08:34:19.15#ibcon#read 6, iclass 4, count 0 2006.257.08:34:19.15#ibcon#end of sib2, iclass 4, count 0 2006.257.08:34:19.15#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:34:19.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:34:19.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:34:19.15#ibcon#*before write, iclass 4, count 0 2006.257.08:34:19.15#ibcon#enter sib2, iclass 4, count 0 2006.257.08:34:19.15#ibcon#flushed, iclass 4, count 0 2006.257.08:34:19.15#ibcon#about to write, iclass 4, count 0 2006.257.08:34:19.15#ibcon#wrote, iclass 4, count 0 2006.257.08:34:19.15#ibcon#about to read 3, iclass 4, count 0 2006.257.08:34:19.19#ibcon#read 3, iclass 4, count 0 2006.257.08:34:19.19#ibcon#about to read 4, iclass 4, count 0 2006.257.08:34:19.19#ibcon#read 4, iclass 4, count 0 2006.257.08:34:19.19#ibcon#about to read 5, iclass 4, count 0 2006.257.08:34:19.19#ibcon#read 5, iclass 4, count 0 2006.257.08:34:19.19#ibcon#about to read 6, iclass 4, count 0 2006.257.08:34:19.19#ibcon#read 6, iclass 4, count 0 2006.257.08:34:19.19#ibcon#end of sib2, iclass 4, count 0 2006.257.08:34:19.19#ibcon#*after write, iclass 4, count 0 2006.257.08:34:19.19#ibcon#*before return 0, iclass 4, count 0 2006.257.08:34:19.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:19.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:19.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:34:19.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:34:19.19$vck44/va=7,4 2006.257.08:34:19.19#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.08:34:19.19#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.08:34:19.19#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:19.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:19.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:19.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:19.25#ibcon#enter wrdev, iclass 6, count 2 2006.257.08:34:19.25#ibcon#first serial, iclass 6, count 2 2006.257.08:34:19.25#ibcon#enter sib2, iclass 6, count 2 2006.257.08:34:19.25#ibcon#flushed, iclass 6, count 2 2006.257.08:34:19.25#ibcon#about to write, iclass 6, count 2 2006.257.08:34:19.25#ibcon#wrote, iclass 6, count 2 2006.257.08:34:19.25#ibcon#about to read 3, iclass 6, count 2 2006.257.08:34:19.27#ibcon#read 3, iclass 6, count 2 2006.257.08:34:19.27#ibcon#about to read 4, iclass 6, count 2 2006.257.08:34:19.27#ibcon#read 4, iclass 6, count 2 2006.257.08:34:19.27#ibcon#about to read 5, iclass 6, count 2 2006.257.08:34:19.27#ibcon#read 5, iclass 6, count 2 2006.257.08:34:19.27#ibcon#about to read 6, iclass 6, count 2 2006.257.08:34:19.27#ibcon#read 6, iclass 6, count 2 2006.257.08:34:19.27#ibcon#end of sib2, iclass 6, count 2 2006.257.08:34:19.27#ibcon#*mode == 0, iclass 6, count 2 2006.257.08:34:19.27#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.08:34:19.27#ibcon#[25=AT07-04\r\n] 2006.257.08:34:19.27#ibcon#*before write, iclass 6, count 2 2006.257.08:34:19.27#ibcon#enter sib2, iclass 6, count 2 2006.257.08:34:19.27#ibcon#flushed, iclass 6, count 2 2006.257.08:34:19.27#ibcon#about to write, iclass 6, count 2 2006.257.08:34:19.27#ibcon#wrote, iclass 6, count 2 2006.257.08:34:19.27#ibcon#about to read 3, iclass 6, count 2 2006.257.08:34:19.30#ibcon#read 3, iclass 6, count 2 2006.257.08:34:19.30#ibcon#about to read 4, iclass 6, count 2 2006.257.08:34:19.30#ibcon#read 4, iclass 6, count 2 2006.257.08:34:19.30#ibcon#about to read 5, iclass 6, count 2 2006.257.08:34:19.30#ibcon#read 5, iclass 6, count 2 2006.257.08:34:19.30#ibcon#about to read 6, iclass 6, count 2 2006.257.08:34:19.30#ibcon#read 6, iclass 6, count 2 2006.257.08:34:19.30#ibcon#end of sib2, iclass 6, count 2 2006.257.08:34:19.30#ibcon#*after write, iclass 6, count 2 2006.257.08:34:19.30#ibcon#*before return 0, iclass 6, count 2 2006.257.08:34:19.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:19.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:19.30#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.08:34:19.30#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:19.30#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:19.42#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:19.42#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:19.42#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:34:19.42#ibcon#first serial, iclass 6, count 0 2006.257.08:34:19.42#ibcon#enter sib2, iclass 6, count 0 2006.257.08:34:19.42#ibcon#flushed, iclass 6, count 0 2006.257.08:34:19.42#ibcon#about to write, iclass 6, count 0 2006.257.08:34:19.42#ibcon#wrote, iclass 6, count 0 2006.257.08:34:19.42#ibcon#about to read 3, iclass 6, count 0 2006.257.08:34:19.44#ibcon#read 3, iclass 6, count 0 2006.257.08:34:19.44#ibcon#about to read 4, iclass 6, count 0 2006.257.08:34:19.44#ibcon#read 4, iclass 6, count 0 2006.257.08:34:19.44#ibcon#about to read 5, iclass 6, count 0 2006.257.08:34:19.44#ibcon#read 5, iclass 6, count 0 2006.257.08:34:19.44#ibcon#about to read 6, iclass 6, count 0 2006.257.08:34:19.44#ibcon#read 6, iclass 6, count 0 2006.257.08:34:19.44#ibcon#end of sib2, iclass 6, count 0 2006.257.08:34:19.44#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:34:19.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:34:19.44#ibcon#[25=USB\r\n] 2006.257.08:34:19.44#ibcon#*before write, iclass 6, count 0 2006.257.08:34:19.44#ibcon#enter sib2, iclass 6, count 0 2006.257.08:34:19.44#ibcon#flushed, iclass 6, count 0 2006.257.08:34:19.44#ibcon#about to write, iclass 6, count 0 2006.257.08:34:19.44#ibcon#wrote, iclass 6, count 0 2006.257.08:34:19.44#ibcon#about to read 3, iclass 6, count 0 2006.257.08:34:19.47#ibcon#read 3, iclass 6, count 0 2006.257.08:34:19.47#ibcon#about to read 4, iclass 6, count 0 2006.257.08:34:19.47#ibcon#read 4, iclass 6, count 0 2006.257.08:34:19.47#ibcon#about to read 5, iclass 6, count 0 2006.257.08:34:19.47#ibcon#read 5, iclass 6, count 0 2006.257.08:34:19.47#ibcon#about to read 6, iclass 6, count 0 2006.257.08:34:19.47#ibcon#read 6, iclass 6, count 0 2006.257.08:34:19.47#ibcon#end of sib2, iclass 6, count 0 2006.257.08:34:19.47#ibcon#*after write, iclass 6, count 0 2006.257.08:34:19.47#ibcon#*before return 0, iclass 6, count 0 2006.257.08:34:19.47#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:19.47#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:19.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:34:19.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:34:19.47$vck44/valo=8,884.99 2006.257.08:34:19.47#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.08:34:19.47#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.08:34:19.47#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:19.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:19.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:19.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:19.47#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:34:19.47#ibcon#first serial, iclass 10, count 0 2006.257.08:34:19.47#ibcon#enter sib2, iclass 10, count 0 2006.257.08:34:19.47#ibcon#flushed, iclass 10, count 0 2006.257.08:34:19.47#ibcon#about to write, iclass 10, count 0 2006.257.08:34:19.47#ibcon#wrote, iclass 10, count 0 2006.257.08:34:19.47#ibcon#about to read 3, iclass 10, count 0 2006.257.08:34:19.49#ibcon#read 3, iclass 10, count 0 2006.257.08:34:19.49#ibcon#about to read 4, iclass 10, count 0 2006.257.08:34:19.49#ibcon#read 4, iclass 10, count 0 2006.257.08:34:19.49#ibcon#about to read 5, iclass 10, count 0 2006.257.08:34:19.49#ibcon#read 5, iclass 10, count 0 2006.257.08:34:19.49#ibcon#about to read 6, iclass 10, count 0 2006.257.08:34:19.49#ibcon#read 6, iclass 10, count 0 2006.257.08:34:19.49#ibcon#end of sib2, iclass 10, count 0 2006.257.08:34:19.49#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:34:19.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:34:19.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:34:19.49#ibcon#*before write, iclass 10, count 0 2006.257.08:34:19.49#ibcon#enter sib2, iclass 10, count 0 2006.257.08:34:19.49#ibcon#flushed, iclass 10, count 0 2006.257.08:34:19.49#ibcon#about to write, iclass 10, count 0 2006.257.08:34:19.49#ibcon#wrote, iclass 10, count 0 2006.257.08:34:19.49#ibcon#about to read 3, iclass 10, count 0 2006.257.08:34:19.53#ibcon#read 3, iclass 10, count 0 2006.257.08:34:19.53#ibcon#about to read 4, iclass 10, count 0 2006.257.08:34:19.53#ibcon#read 4, iclass 10, count 0 2006.257.08:34:19.53#ibcon#about to read 5, iclass 10, count 0 2006.257.08:34:19.53#ibcon#read 5, iclass 10, count 0 2006.257.08:34:19.53#ibcon#about to read 6, iclass 10, count 0 2006.257.08:34:19.53#ibcon#read 6, iclass 10, count 0 2006.257.08:34:19.53#ibcon#end of sib2, iclass 10, count 0 2006.257.08:34:19.53#ibcon#*after write, iclass 10, count 0 2006.257.08:34:19.53#ibcon#*before return 0, iclass 10, count 0 2006.257.08:34:19.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:19.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:19.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:34:19.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:34:19.53$vck44/va=8,4 2006.257.08:34:19.53#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.08:34:19.53#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.08:34:19.53#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:19.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:19.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:19.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:19.59#ibcon#enter wrdev, iclass 12, count 2 2006.257.08:34:19.59#ibcon#first serial, iclass 12, count 2 2006.257.08:34:19.59#ibcon#enter sib2, iclass 12, count 2 2006.257.08:34:19.59#ibcon#flushed, iclass 12, count 2 2006.257.08:34:19.59#ibcon#about to write, iclass 12, count 2 2006.257.08:34:19.59#ibcon#wrote, iclass 12, count 2 2006.257.08:34:19.59#ibcon#about to read 3, iclass 12, count 2 2006.257.08:34:19.61#ibcon#read 3, iclass 12, count 2 2006.257.08:34:19.61#ibcon#about to read 4, iclass 12, count 2 2006.257.08:34:19.61#ibcon#read 4, iclass 12, count 2 2006.257.08:34:19.61#ibcon#about to read 5, iclass 12, count 2 2006.257.08:34:19.61#ibcon#read 5, iclass 12, count 2 2006.257.08:34:19.61#ibcon#about to read 6, iclass 12, count 2 2006.257.08:34:19.61#ibcon#read 6, iclass 12, count 2 2006.257.08:34:19.61#ibcon#end of sib2, iclass 12, count 2 2006.257.08:34:19.61#ibcon#*mode == 0, iclass 12, count 2 2006.257.08:34:19.61#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.08:34:19.61#ibcon#[25=AT08-04\r\n] 2006.257.08:34:19.61#ibcon#*before write, iclass 12, count 2 2006.257.08:34:19.61#ibcon#enter sib2, iclass 12, count 2 2006.257.08:34:19.61#ibcon#flushed, iclass 12, count 2 2006.257.08:34:19.61#ibcon#about to write, iclass 12, count 2 2006.257.08:34:19.61#ibcon#wrote, iclass 12, count 2 2006.257.08:34:19.61#ibcon#about to read 3, iclass 12, count 2 2006.257.08:34:19.64#ibcon#read 3, iclass 12, count 2 2006.257.08:34:19.64#ibcon#about to read 4, iclass 12, count 2 2006.257.08:34:19.64#ibcon#read 4, iclass 12, count 2 2006.257.08:34:19.64#ibcon#about to read 5, iclass 12, count 2 2006.257.08:34:19.64#ibcon#read 5, iclass 12, count 2 2006.257.08:34:19.64#ibcon#about to read 6, iclass 12, count 2 2006.257.08:34:19.64#ibcon#read 6, iclass 12, count 2 2006.257.08:34:19.64#ibcon#end of sib2, iclass 12, count 2 2006.257.08:34:19.64#ibcon#*after write, iclass 12, count 2 2006.257.08:34:19.64#ibcon#*before return 0, iclass 12, count 2 2006.257.08:34:19.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:19.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:19.64#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.08:34:19.64#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:19.64#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:19.76#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:19.76#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:19.76#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:34:19.76#ibcon#first serial, iclass 12, count 0 2006.257.08:34:19.76#ibcon#enter sib2, iclass 12, count 0 2006.257.08:34:19.76#ibcon#flushed, iclass 12, count 0 2006.257.08:34:19.76#ibcon#about to write, iclass 12, count 0 2006.257.08:34:19.76#ibcon#wrote, iclass 12, count 0 2006.257.08:34:19.76#ibcon#about to read 3, iclass 12, count 0 2006.257.08:34:19.78#ibcon#read 3, iclass 12, count 0 2006.257.08:34:19.78#ibcon#about to read 4, iclass 12, count 0 2006.257.08:34:19.78#ibcon#read 4, iclass 12, count 0 2006.257.08:34:19.78#ibcon#about to read 5, iclass 12, count 0 2006.257.08:34:19.78#ibcon#read 5, iclass 12, count 0 2006.257.08:34:19.78#ibcon#about to read 6, iclass 12, count 0 2006.257.08:34:19.78#ibcon#read 6, iclass 12, count 0 2006.257.08:34:19.78#ibcon#end of sib2, iclass 12, count 0 2006.257.08:34:19.78#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:34:19.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:34:19.78#ibcon#[25=USB\r\n] 2006.257.08:34:19.78#ibcon#*before write, iclass 12, count 0 2006.257.08:34:19.78#ibcon#enter sib2, iclass 12, count 0 2006.257.08:34:19.78#ibcon#flushed, iclass 12, count 0 2006.257.08:34:19.78#ibcon#about to write, iclass 12, count 0 2006.257.08:34:19.78#ibcon#wrote, iclass 12, count 0 2006.257.08:34:19.78#ibcon#about to read 3, iclass 12, count 0 2006.257.08:34:19.81#ibcon#read 3, iclass 12, count 0 2006.257.08:34:19.81#ibcon#about to read 4, iclass 12, count 0 2006.257.08:34:19.81#ibcon#read 4, iclass 12, count 0 2006.257.08:34:19.81#ibcon#about to read 5, iclass 12, count 0 2006.257.08:34:19.81#ibcon#read 5, iclass 12, count 0 2006.257.08:34:19.81#ibcon#about to read 6, iclass 12, count 0 2006.257.08:34:19.81#ibcon#read 6, iclass 12, count 0 2006.257.08:34:19.81#ibcon#end of sib2, iclass 12, count 0 2006.257.08:34:19.81#ibcon#*after write, iclass 12, count 0 2006.257.08:34:19.81#ibcon#*before return 0, iclass 12, count 0 2006.257.08:34:19.81#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:19.81#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:19.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:34:19.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:34:19.81$vck44/vblo=1,629.99 2006.257.08:34:19.81#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.08:34:19.81#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.08:34:19.81#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:19.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:19.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:19.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:19.81#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:34:19.81#ibcon#first serial, iclass 14, count 0 2006.257.08:34:19.81#ibcon#enter sib2, iclass 14, count 0 2006.257.08:34:19.81#ibcon#flushed, iclass 14, count 0 2006.257.08:34:19.81#ibcon#about to write, iclass 14, count 0 2006.257.08:34:19.81#ibcon#wrote, iclass 14, count 0 2006.257.08:34:19.81#ibcon#about to read 3, iclass 14, count 0 2006.257.08:34:19.83#ibcon#read 3, iclass 14, count 0 2006.257.08:34:19.83#ibcon#about to read 4, iclass 14, count 0 2006.257.08:34:19.83#ibcon#read 4, iclass 14, count 0 2006.257.08:34:19.83#ibcon#about to read 5, iclass 14, count 0 2006.257.08:34:19.83#ibcon#read 5, iclass 14, count 0 2006.257.08:34:19.83#ibcon#about to read 6, iclass 14, count 0 2006.257.08:34:19.83#ibcon#read 6, iclass 14, count 0 2006.257.08:34:19.83#ibcon#end of sib2, iclass 14, count 0 2006.257.08:34:19.83#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:34:19.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:34:19.83#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:34:19.83#ibcon#*before write, iclass 14, count 0 2006.257.08:34:19.83#ibcon#enter sib2, iclass 14, count 0 2006.257.08:34:19.83#ibcon#flushed, iclass 14, count 0 2006.257.08:34:19.83#ibcon#about to write, iclass 14, count 0 2006.257.08:34:19.83#ibcon#wrote, iclass 14, count 0 2006.257.08:34:19.83#ibcon#about to read 3, iclass 14, count 0 2006.257.08:34:19.87#ibcon#read 3, iclass 14, count 0 2006.257.08:34:19.87#ibcon#about to read 4, iclass 14, count 0 2006.257.08:34:19.87#ibcon#read 4, iclass 14, count 0 2006.257.08:34:19.87#ibcon#about to read 5, iclass 14, count 0 2006.257.08:34:19.87#ibcon#read 5, iclass 14, count 0 2006.257.08:34:19.87#ibcon#about to read 6, iclass 14, count 0 2006.257.08:34:19.87#ibcon#read 6, iclass 14, count 0 2006.257.08:34:19.87#ibcon#end of sib2, iclass 14, count 0 2006.257.08:34:19.87#ibcon#*after write, iclass 14, count 0 2006.257.08:34:19.87#ibcon#*before return 0, iclass 14, count 0 2006.257.08:34:19.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:19.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:19.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:34:19.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:34:19.87$vck44/vb=1,4 2006.257.08:34:19.87#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.08:34:19.87#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.08:34:19.87#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:19.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:34:19.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:34:19.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:34:19.87#ibcon#enter wrdev, iclass 16, count 2 2006.257.08:34:19.87#ibcon#first serial, iclass 16, count 2 2006.257.08:34:19.87#ibcon#enter sib2, iclass 16, count 2 2006.257.08:34:19.87#ibcon#flushed, iclass 16, count 2 2006.257.08:34:19.87#ibcon#about to write, iclass 16, count 2 2006.257.08:34:19.87#ibcon#wrote, iclass 16, count 2 2006.257.08:34:19.87#ibcon#about to read 3, iclass 16, count 2 2006.257.08:34:19.89#ibcon#read 3, iclass 16, count 2 2006.257.08:34:19.89#ibcon#about to read 4, iclass 16, count 2 2006.257.08:34:19.89#ibcon#read 4, iclass 16, count 2 2006.257.08:34:19.89#ibcon#about to read 5, iclass 16, count 2 2006.257.08:34:19.89#ibcon#read 5, iclass 16, count 2 2006.257.08:34:19.89#ibcon#about to read 6, iclass 16, count 2 2006.257.08:34:19.89#ibcon#read 6, iclass 16, count 2 2006.257.08:34:19.89#ibcon#end of sib2, iclass 16, count 2 2006.257.08:34:19.89#ibcon#*mode == 0, iclass 16, count 2 2006.257.08:34:19.89#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.08:34:19.89#ibcon#[27=AT01-04\r\n] 2006.257.08:34:19.89#ibcon#*before write, iclass 16, count 2 2006.257.08:34:19.89#ibcon#enter sib2, iclass 16, count 2 2006.257.08:34:19.89#ibcon#flushed, iclass 16, count 2 2006.257.08:34:19.89#ibcon#about to write, iclass 16, count 2 2006.257.08:34:19.89#ibcon#wrote, iclass 16, count 2 2006.257.08:34:19.89#ibcon#about to read 3, iclass 16, count 2 2006.257.08:34:19.92#ibcon#read 3, iclass 16, count 2 2006.257.08:34:19.92#ibcon#about to read 4, iclass 16, count 2 2006.257.08:34:19.92#ibcon#read 4, iclass 16, count 2 2006.257.08:34:19.92#ibcon#about to read 5, iclass 16, count 2 2006.257.08:34:19.92#ibcon#read 5, iclass 16, count 2 2006.257.08:34:19.92#ibcon#about to read 6, iclass 16, count 2 2006.257.08:34:19.92#ibcon#read 6, iclass 16, count 2 2006.257.08:34:19.92#ibcon#end of sib2, iclass 16, count 2 2006.257.08:34:19.92#ibcon#*after write, iclass 16, count 2 2006.257.08:34:19.92#ibcon#*before return 0, iclass 16, count 2 2006.257.08:34:19.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:34:19.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:34:19.92#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.08:34:19.92#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:19.92#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:34:20.04#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:34:20.04#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:34:20.04#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:34:20.04#ibcon#first serial, iclass 16, count 0 2006.257.08:34:20.04#ibcon#enter sib2, iclass 16, count 0 2006.257.08:34:20.04#ibcon#flushed, iclass 16, count 0 2006.257.08:34:20.04#ibcon#about to write, iclass 16, count 0 2006.257.08:34:20.04#ibcon#wrote, iclass 16, count 0 2006.257.08:34:20.04#ibcon#about to read 3, iclass 16, count 0 2006.257.08:34:20.06#ibcon#read 3, iclass 16, count 0 2006.257.08:34:20.06#ibcon#about to read 4, iclass 16, count 0 2006.257.08:34:20.06#ibcon#read 4, iclass 16, count 0 2006.257.08:34:20.06#ibcon#about to read 5, iclass 16, count 0 2006.257.08:34:20.06#ibcon#read 5, iclass 16, count 0 2006.257.08:34:20.06#ibcon#about to read 6, iclass 16, count 0 2006.257.08:34:20.06#ibcon#read 6, iclass 16, count 0 2006.257.08:34:20.06#ibcon#end of sib2, iclass 16, count 0 2006.257.08:34:20.06#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:34:20.06#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:34:20.06#ibcon#[27=USB\r\n] 2006.257.08:34:20.06#ibcon#*before write, iclass 16, count 0 2006.257.08:34:20.06#ibcon#enter sib2, iclass 16, count 0 2006.257.08:34:20.06#ibcon#flushed, iclass 16, count 0 2006.257.08:34:20.06#ibcon#about to write, iclass 16, count 0 2006.257.08:34:20.06#ibcon#wrote, iclass 16, count 0 2006.257.08:34:20.06#ibcon#about to read 3, iclass 16, count 0 2006.257.08:34:20.09#ibcon#read 3, iclass 16, count 0 2006.257.08:34:20.09#ibcon#about to read 4, iclass 16, count 0 2006.257.08:34:20.09#ibcon#read 4, iclass 16, count 0 2006.257.08:34:20.09#ibcon#about to read 5, iclass 16, count 0 2006.257.08:34:20.09#ibcon#read 5, iclass 16, count 0 2006.257.08:34:20.09#ibcon#about to read 6, iclass 16, count 0 2006.257.08:34:20.09#ibcon#read 6, iclass 16, count 0 2006.257.08:34:20.09#ibcon#end of sib2, iclass 16, count 0 2006.257.08:34:20.09#ibcon#*after write, iclass 16, count 0 2006.257.08:34:20.09#ibcon#*before return 0, iclass 16, count 0 2006.257.08:34:20.09#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:34:20.09#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:34:20.09#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:34:20.09#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:34:20.09$vck44/vblo=2,634.99 2006.257.08:34:20.09#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.08:34:20.09#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.08:34:20.09#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:20.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:20.09#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:20.09#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:20.09#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:34:20.09#ibcon#first serial, iclass 18, count 0 2006.257.08:34:20.09#ibcon#enter sib2, iclass 18, count 0 2006.257.08:34:20.09#ibcon#flushed, iclass 18, count 0 2006.257.08:34:20.09#ibcon#about to write, iclass 18, count 0 2006.257.08:34:20.09#ibcon#wrote, iclass 18, count 0 2006.257.08:34:20.09#ibcon#about to read 3, iclass 18, count 0 2006.257.08:34:20.11#ibcon#read 3, iclass 18, count 0 2006.257.08:34:20.11#ibcon#about to read 4, iclass 18, count 0 2006.257.08:34:20.11#ibcon#read 4, iclass 18, count 0 2006.257.08:34:20.11#ibcon#about to read 5, iclass 18, count 0 2006.257.08:34:20.11#ibcon#read 5, iclass 18, count 0 2006.257.08:34:20.11#ibcon#about to read 6, iclass 18, count 0 2006.257.08:34:20.11#ibcon#read 6, iclass 18, count 0 2006.257.08:34:20.11#ibcon#end of sib2, iclass 18, count 0 2006.257.08:34:20.11#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:34:20.11#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:34:20.11#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:34:20.11#ibcon#*before write, iclass 18, count 0 2006.257.08:34:20.11#ibcon#enter sib2, iclass 18, count 0 2006.257.08:34:20.11#ibcon#flushed, iclass 18, count 0 2006.257.08:34:20.11#ibcon#about to write, iclass 18, count 0 2006.257.08:34:20.11#ibcon#wrote, iclass 18, count 0 2006.257.08:34:20.11#ibcon#about to read 3, iclass 18, count 0 2006.257.08:34:20.15#ibcon#read 3, iclass 18, count 0 2006.257.08:34:20.15#ibcon#about to read 4, iclass 18, count 0 2006.257.08:34:20.15#ibcon#read 4, iclass 18, count 0 2006.257.08:34:20.15#ibcon#about to read 5, iclass 18, count 0 2006.257.08:34:20.15#ibcon#read 5, iclass 18, count 0 2006.257.08:34:20.15#ibcon#about to read 6, iclass 18, count 0 2006.257.08:34:20.15#ibcon#read 6, iclass 18, count 0 2006.257.08:34:20.15#ibcon#end of sib2, iclass 18, count 0 2006.257.08:34:20.15#ibcon#*after write, iclass 18, count 0 2006.257.08:34:20.15#ibcon#*before return 0, iclass 18, count 0 2006.257.08:34:20.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:20.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:34:20.15#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:34:20.15#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:34:20.15$vck44/vb=2,5 2006.257.08:34:20.15#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.08:34:20.15#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.08:34:20.15#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:20.15#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:20.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:20.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:20.21#ibcon#enter wrdev, iclass 20, count 2 2006.257.08:34:20.21#ibcon#first serial, iclass 20, count 2 2006.257.08:34:20.21#ibcon#enter sib2, iclass 20, count 2 2006.257.08:34:20.21#ibcon#flushed, iclass 20, count 2 2006.257.08:34:20.21#ibcon#about to write, iclass 20, count 2 2006.257.08:34:20.21#ibcon#wrote, iclass 20, count 2 2006.257.08:34:20.21#ibcon#about to read 3, iclass 20, count 2 2006.257.08:34:20.23#ibcon#read 3, iclass 20, count 2 2006.257.08:34:20.23#ibcon#about to read 4, iclass 20, count 2 2006.257.08:34:20.23#ibcon#read 4, iclass 20, count 2 2006.257.08:34:20.23#ibcon#about to read 5, iclass 20, count 2 2006.257.08:34:20.23#ibcon#read 5, iclass 20, count 2 2006.257.08:34:20.23#ibcon#about to read 6, iclass 20, count 2 2006.257.08:34:20.23#ibcon#read 6, iclass 20, count 2 2006.257.08:34:20.23#ibcon#end of sib2, iclass 20, count 2 2006.257.08:34:20.23#ibcon#*mode == 0, iclass 20, count 2 2006.257.08:34:20.23#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.08:34:20.23#ibcon#[27=AT02-05\r\n] 2006.257.08:34:20.23#ibcon#*before write, iclass 20, count 2 2006.257.08:34:20.23#ibcon#enter sib2, iclass 20, count 2 2006.257.08:34:20.23#ibcon#flushed, iclass 20, count 2 2006.257.08:34:20.23#ibcon#about to write, iclass 20, count 2 2006.257.08:34:20.23#ibcon#wrote, iclass 20, count 2 2006.257.08:34:20.23#ibcon#about to read 3, iclass 20, count 2 2006.257.08:34:20.26#ibcon#read 3, iclass 20, count 2 2006.257.08:34:20.26#ibcon#about to read 4, iclass 20, count 2 2006.257.08:34:20.26#ibcon#read 4, iclass 20, count 2 2006.257.08:34:20.26#ibcon#about to read 5, iclass 20, count 2 2006.257.08:34:20.26#ibcon#read 5, iclass 20, count 2 2006.257.08:34:20.26#ibcon#about to read 6, iclass 20, count 2 2006.257.08:34:20.26#ibcon#read 6, iclass 20, count 2 2006.257.08:34:20.26#ibcon#end of sib2, iclass 20, count 2 2006.257.08:34:20.26#ibcon#*after write, iclass 20, count 2 2006.257.08:34:20.26#ibcon#*before return 0, iclass 20, count 2 2006.257.08:34:20.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:20.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:34:20.26#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.08:34:20.26#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:20.26#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:20.32#abcon#<5=/16 1.0 3.1 20.66 911013.0\r\n> 2006.257.08:34:20.34#abcon#{5=INTERFACE CLEAR} 2006.257.08:34:20.38#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:20.38#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:20.38#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:34:20.38#ibcon#first serial, iclass 20, count 0 2006.257.08:34:20.38#ibcon#enter sib2, iclass 20, count 0 2006.257.08:34:20.38#ibcon#flushed, iclass 20, count 0 2006.257.08:34:20.38#ibcon#about to write, iclass 20, count 0 2006.257.08:34:20.38#ibcon#wrote, iclass 20, count 0 2006.257.08:34:20.38#ibcon#about to read 3, iclass 20, count 0 2006.257.08:34:20.40#ibcon#read 3, iclass 20, count 0 2006.257.08:34:20.40#ibcon#about to read 4, iclass 20, count 0 2006.257.08:34:20.40#ibcon#read 4, iclass 20, count 0 2006.257.08:34:20.40#ibcon#about to read 5, iclass 20, count 0 2006.257.08:34:20.40#ibcon#read 5, iclass 20, count 0 2006.257.08:34:20.40#ibcon#about to read 6, iclass 20, count 0 2006.257.08:34:20.40#ibcon#read 6, iclass 20, count 0 2006.257.08:34:20.40#ibcon#end of sib2, iclass 20, count 0 2006.257.08:34:20.40#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:34:20.40#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:34:20.40#ibcon#[27=USB\r\n] 2006.257.08:34:20.40#ibcon#*before write, iclass 20, count 0 2006.257.08:34:20.40#ibcon#enter sib2, iclass 20, count 0 2006.257.08:34:20.40#ibcon#flushed, iclass 20, count 0 2006.257.08:34:20.40#ibcon#about to write, iclass 20, count 0 2006.257.08:34:20.40#ibcon#wrote, iclass 20, count 0 2006.257.08:34:20.40#ibcon#about to read 3, iclass 20, count 0 2006.257.08:34:20.40#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:34:20.43#ibcon#read 3, iclass 20, count 0 2006.257.08:34:20.43#ibcon#about to read 4, iclass 20, count 0 2006.257.08:34:20.43#ibcon#read 4, iclass 20, count 0 2006.257.08:34:20.43#ibcon#about to read 5, iclass 20, count 0 2006.257.08:34:20.43#ibcon#read 5, iclass 20, count 0 2006.257.08:34:20.43#ibcon#about to read 6, iclass 20, count 0 2006.257.08:34:20.43#ibcon#read 6, iclass 20, count 0 2006.257.08:34:20.43#ibcon#end of sib2, iclass 20, count 0 2006.257.08:34:20.43#ibcon#*after write, iclass 20, count 0 2006.257.08:34:20.43#ibcon#*before return 0, iclass 20, count 0 2006.257.08:34:20.43#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:20.43#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:34:20.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:34:20.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:34:20.43$vck44/vblo=3,649.99 2006.257.08:34:20.43#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.08:34:20.43#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.08:34:20.43#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:20.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:20.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:20.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:20.43#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:34:20.43#ibcon#first serial, iclass 26, count 0 2006.257.08:34:20.43#ibcon#enter sib2, iclass 26, count 0 2006.257.08:34:20.43#ibcon#flushed, iclass 26, count 0 2006.257.08:34:20.43#ibcon#about to write, iclass 26, count 0 2006.257.08:34:20.43#ibcon#wrote, iclass 26, count 0 2006.257.08:34:20.43#ibcon#about to read 3, iclass 26, count 0 2006.257.08:34:20.45#ibcon#read 3, iclass 26, count 0 2006.257.08:34:20.45#ibcon#about to read 4, iclass 26, count 0 2006.257.08:34:20.45#ibcon#read 4, iclass 26, count 0 2006.257.08:34:20.45#ibcon#about to read 5, iclass 26, count 0 2006.257.08:34:20.45#ibcon#read 5, iclass 26, count 0 2006.257.08:34:20.45#ibcon#about to read 6, iclass 26, count 0 2006.257.08:34:20.45#ibcon#read 6, iclass 26, count 0 2006.257.08:34:20.45#ibcon#end of sib2, iclass 26, count 0 2006.257.08:34:20.45#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:34:20.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:34:20.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:34:20.45#ibcon#*before write, iclass 26, count 0 2006.257.08:34:20.45#ibcon#enter sib2, iclass 26, count 0 2006.257.08:34:20.45#ibcon#flushed, iclass 26, count 0 2006.257.08:34:20.45#ibcon#about to write, iclass 26, count 0 2006.257.08:34:20.45#ibcon#wrote, iclass 26, count 0 2006.257.08:34:20.45#ibcon#about to read 3, iclass 26, count 0 2006.257.08:34:20.49#ibcon#read 3, iclass 26, count 0 2006.257.08:34:20.49#ibcon#about to read 4, iclass 26, count 0 2006.257.08:34:20.49#ibcon#read 4, iclass 26, count 0 2006.257.08:34:20.49#ibcon#about to read 5, iclass 26, count 0 2006.257.08:34:20.49#ibcon#read 5, iclass 26, count 0 2006.257.08:34:20.49#ibcon#about to read 6, iclass 26, count 0 2006.257.08:34:20.49#ibcon#read 6, iclass 26, count 0 2006.257.08:34:20.49#ibcon#end of sib2, iclass 26, count 0 2006.257.08:34:20.49#ibcon#*after write, iclass 26, count 0 2006.257.08:34:20.49#ibcon#*before return 0, iclass 26, count 0 2006.257.08:34:20.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:20.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:34:20.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:34:20.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:34:20.49$vck44/vb=3,4 2006.257.08:34:20.49#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.08:34:20.49#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.08:34:20.49#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:20.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:20.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:20.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:20.55#ibcon#enter wrdev, iclass 28, count 2 2006.257.08:34:20.55#ibcon#first serial, iclass 28, count 2 2006.257.08:34:20.55#ibcon#enter sib2, iclass 28, count 2 2006.257.08:34:20.55#ibcon#flushed, iclass 28, count 2 2006.257.08:34:20.55#ibcon#about to write, iclass 28, count 2 2006.257.08:34:20.55#ibcon#wrote, iclass 28, count 2 2006.257.08:34:20.55#ibcon#about to read 3, iclass 28, count 2 2006.257.08:34:20.57#ibcon#read 3, iclass 28, count 2 2006.257.08:34:20.57#ibcon#about to read 4, iclass 28, count 2 2006.257.08:34:20.57#ibcon#read 4, iclass 28, count 2 2006.257.08:34:20.57#ibcon#about to read 5, iclass 28, count 2 2006.257.08:34:20.57#ibcon#read 5, iclass 28, count 2 2006.257.08:34:20.57#ibcon#about to read 6, iclass 28, count 2 2006.257.08:34:20.57#ibcon#read 6, iclass 28, count 2 2006.257.08:34:20.57#ibcon#end of sib2, iclass 28, count 2 2006.257.08:34:20.57#ibcon#*mode == 0, iclass 28, count 2 2006.257.08:34:20.57#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.08:34:20.57#ibcon#[27=AT03-04\r\n] 2006.257.08:34:20.57#ibcon#*before write, iclass 28, count 2 2006.257.08:34:20.57#ibcon#enter sib2, iclass 28, count 2 2006.257.08:34:20.57#ibcon#flushed, iclass 28, count 2 2006.257.08:34:20.57#ibcon#about to write, iclass 28, count 2 2006.257.08:34:20.57#ibcon#wrote, iclass 28, count 2 2006.257.08:34:20.57#ibcon#about to read 3, iclass 28, count 2 2006.257.08:34:20.60#ibcon#read 3, iclass 28, count 2 2006.257.08:34:20.60#ibcon#about to read 4, iclass 28, count 2 2006.257.08:34:20.60#ibcon#read 4, iclass 28, count 2 2006.257.08:34:20.60#ibcon#about to read 5, iclass 28, count 2 2006.257.08:34:20.60#ibcon#read 5, iclass 28, count 2 2006.257.08:34:20.60#ibcon#about to read 6, iclass 28, count 2 2006.257.08:34:20.60#ibcon#read 6, iclass 28, count 2 2006.257.08:34:20.60#ibcon#end of sib2, iclass 28, count 2 2006.257.08:34:20.60#ibcon#*after write, iclass 28, count 2 2006.257.08:34:20.60#ibcon#*before return 0, iclass 28, count 2 2006.257.08:34:20.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:20.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:34:20.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.08:34:20.60#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:20.60#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:20.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:20.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:20.72#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:34:20.72#ibcon#first serial, iclass 28, count 0 2006.257.08:34:20.72#ibcon#enter sib2, iclass 28, count 0 2006.257.08:34:20.72#ibcon#flushed, iclass 28, count 0 2006.257.08:34:20.72#ibcon#about to write, iclass 28, count 0 2006.257.08:34:20.72#ibcon#wrote, iclass 28, count 0 2006.257.08:34:20.72#ibcon#about to read 3, iclass 28, count 0 2006.257.08:34:20.74#ibcon#read 3, iclass 28, count 0 2006.257.08:34:20.74#ibcon#about to read 4, iclass 28, count 0 2006.257.08:34:20.74#ibcon#read 4, iclass 28, count 0 2006.257.08:34:20.74#ibcon#about to read 5, iclass 28, count 0 2006.257.08:34:20.74#ibcon#read 5, iclass 28, count 0 2006.257.08:34:20.74#ibcon#about to read 6, iclass 28, count 0 2006.257.08:34:20.74#ibcon#read 6, iclass 28, count 0 2006.257.08:34:20.74#ibcon#end of sib2, iclass 28, count 0 2006.257.08:34:20.74#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:34:20.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:34:20.74#ibcon#[27=USB\r\n] 2006.257.08:34:20.74#ibcon#*before write, iclass 28, count 0 2006.257.08:34:20.74#ibcon#enter sib2, iclass 28, count 0 2006.257.08:34:20.74#ibcon#flushed, iclass 28, count 0 2006.257.08:34:20.74#ibcon#about to write, iclass 28, count 0 2006.257.08:34:20.74#ibcon#wrote, iclass 28, count 0 2006.257.08:34:20.74#ibcon#about to read 3, iclass 28, count 0 2006.257.08:34:20.77#ibcon#read 3, iclass 28, count 0 2006.257.08:34:20.77#ibcon#about to read 4, iclass 28, count 0 2006.257.08:34:20.77#ibcon#read 4, iclass 28, count 0 2006.257.08:34:20.77#ibcon#about to read 5, iclass 28, count 0 2006.257.08:34:20.77#ibcon#read 5, iclass 28, count 0 2006.257.08:34:20.77#ibcon#about to read 6, iclass 28, count 0 2006.257.08:34:20.77#ibcon#read 6, iclass 28, count 0 2006.257.08:34:20.77#ibcon#end of sib2, iclass 28, count 0 2006.257.08:34:20.77#ibcon#*after write, iclass 28, count 0 2006.257.08:34:20.77#ibcon#*before return 0, iclass 28, count 0 2006.257.08:34:20.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:20.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:34:20.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:34:20.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:34:20.77$vck44/vblo=4,679.99 2006.257.08:34:20.77#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.08:34:20.77#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.08:34:20.77#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:20.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:20.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:20.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:20.77#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:34:20.77#ibcon#first serial, iclass 30, count 0 2006.257.08:34:20.77#ibcon#enter sib2, iclass 30, count 0 2006.257.08:34:20.77#ibcon#flushed, iclass 30, count 0 2006.257.08:34:20.77#ibcon#about to write, iclass 30, count 0 2006.257.08:34:20.77#ibcon#wrote, iclass 30, count 0 2006.257.08:34:20.77#ibcon#about to read 3, iclass 30, count 0 2006.257.08:34:20.79#ibcon#read 3, iclass 30, count 0 2006.257.08:34:20.79#ibcon#about to read 4, iclass 30, count 0 2006.257.08:34:20.79#ibcon#read 4, iclass 30, count 0 2006.257.08:34:20.79#ibcon#about to read 5, iclass 30, count 0 2006.257.08:34:20.79#ibcon#read 5, iclass 30, count 0 2006.257.08:34:20.79#ibcon#about to read 6, iclass 30, count 0 2006.257.08:34:20.79#ibcon#read 6, iclass 30, count 0 2006.257.08:34:20.79#ibcon#end of sib2, iclass 30, count 0 2006.257.08:34:20.79#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:34:20.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:34:20.79#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:34:20.79#ibcon#*before write, iclass 30, count 0 2006.257.08:34:20.79#ibcon#enter sib2, iclass 30, count 0 2006.257.08:34:20.79#ibcon#flushed, iclass 30, count 0 2006.257.08:34:20.79#ibcon#about to write, iclass 30, count 0 2006.257.08:34:20.79#ibcon#wrote, iclass 30, count 0 2006.257.08:34:20.79#ibcon#about to read 3, iclass 30, count 0 2006.257.08:34:20.83#ibcon#read 3, iclass 30, count 0 2006.257.08:34:20.83#ibcon#about to read 4, iclass 30, count 0 2006.257.08:34:20.83#ibcon#read 4, iclass 30, count 0 2006.257.08:34:20.83#ibcon#about to read 5, iclass 30, count 0 2006.257.08:34:20.83#ibcon#read 5, iclass 30, count 0 2006.257.08:34:20.83#ibcon#about to read 6, iclass 30, count 0 2006.257.08:34:20.83#ibcon#read 6, iclass 30, count 0 2006.257.08:34:20.83#ibcon#end of sib2, iclass 30, count 0 2006.257.08:34:20.83#ibcon#*after write, iclass 30, count 0 2006.257.08:34:20.83#ibcon#*before return 0, iclass 30, count 0 2006.257.08:34:20.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:20.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:34:20.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:34:20.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:34:20.83$vck44/vb=4,5 2006.257.08:34:20.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.08:34:20.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.08:34:20.83#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:20.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:20.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:20.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:20.89#ibcon#enter wrdev, iclass 32, count 2 2006.257.08:34:20.89#ibcon#first serial, iclass 32, count 2 2006.257.08:34:20.89#ibcon#enter sib2, iclass 32, count 2 2006.257.08:34:20.89#ibcon#flushed, iclass 32, count 2 2006.257.08:34:20.89#ibcon#about to write, iclass 32, count 2 2006.257.08:34:20.89#ibcon#wrote, iclass 32, count 2 2006.257.08:34:20.89#ibcon#about to read 3, iclass 32, count 2 2006.257.08:34:20.91#ibcon#read 3, iclass 32, count 2 2006.257.08:34:20.91#ibcon#about to read 4, iclass 32, count 2 2006.257.08:34:20.91#ibcon#read 4, iclass 32, count 2 2006.257.08:34:20.91#ibcon#about to read 5, iclass 32, count 2 2006.257.08:34:20.91#ibcon#read 5, iclass 32, count 2 2006.257.08:34:20.91#ibcon#about to read 6, iclass 32, count 2 2006.257.08:34:20.91#ibcon#read 6, iclass 32, count 2 2006.257.08:34:20.91#ibcon#end of sib2, iclass 32, count 2 2006.257.08:34:20.91#ibcon#*mode == 0, iclass 32, count 2 2006.257.08:34:20.91#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.08:34:20.91#ibcon#[27=AT04-05\r\n] 2006.257.08:34:20.91#ibcon#*before write, iclass 32, count 2 2006.257.08:34:20.91#ibcon#enter sib2, iclass 32, count 2 2006.257.08:34:20.91#ibcon#flushed, iclass 32, count 2 2006.257.08:34:20.91#ibcon#about to write, iclass 32, count 2 2006.257.08:34:20.91#ibcon#wrote, iclass 32, count 2 2006.257.08:34:20.91#ibcon#about to read 3, iclass 32, count 2 2006.257.08:34:20.94#ibcon#read 3, iclass 32, count 2 2006.257.08:34:20.94#ibcon#about to read 4, iclass 32, count 2 2006.257.08:34:20.94#ibcon#read 4, iclass 32, count 2 2006.257.08:34:20.94#ibcon#about to read 5, iclass 32, count 2 2006.257.08:34:20.94#ibcon#read 5, iclass 32, count 2 2006.257.08:34:20.94#ibcon#about to read 6, iclass 32, count 2 2006.257.08:34:20.94#ibcon#read 6, iclass 32, count 2 2006.257.08:34:20.94#ibcon#end of sib2, iclass 32, count 2 2006.257.08:34:20.94#ibcon#*after write, iclass 32, count 2 2006.257.08:34:20.94#ibcon#*before return 0, iclass 32, count 2 2006.257.08:34:20.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:20.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:34:20.94#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.08:34:20.94#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:20.94#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:21.06#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:21.06#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:21.06#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:34:21.06#ibcon#first serial, iclass 32, count 0 2006.257.08:34:21.06#ibcon#enter sib2, iclass 32, count 0 2006.257.08:34:21.06#ibcon#flushed, iclass 32, count 0 2006.257.08:34:21.06#ibcon#about to write, iclass 32, count 0 2006.257.08:34:21.06#ibcon#wrote, iclass 32, count 0 2006.257.08:34:21.06#ibcon#about to read 3, iclass 32, count 0 2006.257.08:34:21.08#ibcon#read 3, iclass 32, count 0 2006.257.08:34:21.08#ibcon#about to read 4, iclass 32, count 0 2006.257.08:34:21.08#ibcon#read 4, iclass 32, count 0 2006.257.08:34:21.08#ibcon#about to read 5, iclass 32, count 0 2006.257.08:34:21.08#ibcon#read 5, iclass 32, count 0 2006.257.08:34:21.08#ibcon#about to read 6, iclass 32, count 0 2006.257.08:34:21.08#ibcon#read 6, iclass 32, count 0 2006.257.08:34:21.08#ibcon#end of sib2, iclass 32, count 0 2006.257.08:34:21.08#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:34:21.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:34:21.08#ibcon#[27=USB\r\n] 2006.257.08:34:21.08#ibcon#*before write, iclass 32, count 0 2006.257.08:34:21.08#ibcon#enter sib2, iclass 32, count 0 2006.257.08:34:21.08#ibcon#flushed, iclass 32, count 0 2006.257.08:34:21.08#ibcon#about to write, iclass 32, count 0 2006.257.08:34:21.08#ibcon#wrote, iclass 32, count 0 2006.257.08:34:21.08#ibcon#about to read 3, iclass 32, count 0 2006.257.08:34:21.11#ibcon#read 3, iclass 32, count 0 2006.257.08:34:21.11#ibcon#about to read 4, iclass 32, count 0 2006.257.08:34:21.11#ibcon#read 4, iclass 32, count 0 2006.257.08:34:21.11#ibcon#about to read 5, iclass 32, count 0 2006.257.08:34:21.11#ibcon#read 5, iclass 32, count 0 2006.257.08:34:21.11#ibcon#about to read 6, iclass 32, count 0 2006.257.08:34:21.11#ibcon#read 6, iclass 32, count 0 2006.257.08:34:21.11#ibcon#end of sib2, iclass 32, count 0 2006.257.08:34:21.11#ibcon#*after write, iclass 32, count 0 2006.257.08:34:21.11#ibcon#*before return 0, iclass 32, count 0 2006.257.08:34:21.11#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:21.11#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:34:21.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:34:21.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:34:21.11$vck44/vblo=5,709.99 2006.257.08:34:21.11#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.08:34:21.11#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.08:34:21.11#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:21.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:21.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:21.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:21.11#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:34:21.11#ibcon#first serial, iclass 34, count 0 2006.257.08:34:21.11#ibcon#enter sib2, iclass 34, count 0 2006.257.08:34:21.11#ibcon#flushed, iclass 34, count 0 2006.257.08:34:21.11#ibcon#about to write, iclass 34, count 0 2006.257.08:34:21.11#ibcon#wrote, iclass 34, count 0 2006.257.08:34:21.11#ibcon#about to read 3, iclass 34, count 0 2006.257.08:34:21.13#ibcon#read 3, iclass 34, count 0 2006.257.08:34:21.13#ibcon#about to read 4, iclass 34, count 0 2006.257.08:34:21.13#ibcon#read 4, iclass 34, count 0 2006.257.08:34:21.13#ibcon#about to read 5, iclass 34, count 0 2006.257.08:34:21.13#ibcon#read 5, iclass 34, count 0 2006.257.08:34:21.13#ibcon#about to read 6, iclass 34, count 0 2006.257.08:34:21.13#ibcon#read 6, iclass 34, count 0 2006.257.08:34:21.13#ibcon#end of sib2, iclass 34, count 0 2006.257.08:34:21.13#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:34:21.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:34:21.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:34:21.13#ibcon#*before write, iclass 34, count 0 2006.257.08:34:21.13#ibcon#enter sib2, iclass 34, count 0 2006.257.08:34:21.13#ibcon#flushed, iclass 34, count 0 2006.257.08:34:21.13#ibcon#about to write, iclass 34, count 0 2006.257.08:34:21.13#ibcon#wrote, iclass 34, count 0 2006.257.08:34:21.13#ibcon#about to read 3, iclass 34, count 0 2006.257.08:34:21.17#ibcon#read 3, iclass 34, count 0 2006.257.08:34:21.17#ibcon#about to read 4, iclass 34, count 0 2006.257.08:34:21.17#ibcon#read 4, iclass 34, count 0 2006.257.08:34:21.17#ibcon#about to read 5, iclass 34, count 0 2006.257.08:34:21.17#ibcon#read 5, iclass 34, count 0 2006.257.08:34:21.17#ibcon#about to read 6, iclass 34, count 0 2006.257.08:34:21.17#ibcon#read 6, iclass 34, count 0 2006.257.08:34:21.17#ibcon#end of sib2, iclass 34, count 0 2006.257.08:34:21.17#ibcon#*after write, iclass 34, count 0 2006.257.08:34:21.17#ibcon#*before return 0, iclass 34, count 0 2006.257.08:34:21.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:21.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:34:21.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:34:21.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:34:21.17$vck44/vb=5,4 2006.257.08:34:21.17#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.08:34:21.17#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.08:34:21.17#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:21.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:21.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:21.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:21.23#ibcon#enter wrdev, iclass 36, count 2 2006.257.08:34:21.23#ibcon#first serial, iclass 36, count 2 2006.257.08:34:21.23#ibcon#enter sib2, iclass 36, count 2 2006.257.08:34:21.23#ibcon#flushed, iclass 36, count 2 2006.257.08:34:21.23#ibcon#about to write, iclass 36, count 2 2006.257.08:34:21.23#ibcon#wrote, iclass 36, count 2 2006.257.08:34:21.23#ibcon#about to read 3, iclass 36, count 2 2006.257.08:34:21.25#ibcon#read 3, iclass 36, count 2 2006.257.08:34:21.25#ibcon#about to read 4, iclass 36, count 2 2006.257.08:34:21.25#ibcon#read 4, iclass 36, count 2 2006.257.08:34:21.25#ibcon#about to read 5, iclass 36, count 2 2006.257.08:34:21.25#ibcon#read 5, iclass 36, count 2 2006.257.08:34:21.25#ibcon#about to read 6, iclass 36, count 2 2006.257.08:34:21.25#ibcon#read 6, iclass 36, count 2 2006.257.08:34:21.25#ibcon#end of sib2, iclass 36, count 2 2006.257.08:34:21.25#ibcon#*mode == 0, iclass 36, count 2 2006.257.08:34:21.25#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.08:34:21.25#ibcon#[27=AT05-04\r\n] 2006.257.08:34:21.25#ibcon#*before write, iclass 36, count 2 2006.257.08:34:21.25#ibcon#enter sib2, iclass 36, count 2 2006.257.08:34:21.25#ibcon#flushed, iclass 36, count 2 2006.257.08:34:21.25#ibcon#about to write, iclass 36, count 2 2006.257.08:34:21.25#ibcon#wrote, iclass 36, count 2 2006.257.08:34:21.25#ibcon#about to read 3, iclass 36, count 2 2006.257.08:34:21.28#ibcon#read 3, iclass 36, count 2 2006.257.08:34:21.28#ibcon#about to read 4, iclass 36, count 2 2006.257.08:34:21.28#ibcon#read 4, iclass 36, count 2 2006.257.08:34:21.28#ibcon#about to read 5, iclass 36, count 2 2006.257.08:34:21.28#ibcon#read 5, iclass 36, count 2 2006.257.08:34:21.28#ibcon#about to read 6, iclass 36, count 2 2006.257.08:34:21.28#ibcon#read 6, iclass 36, count 2 2006.257.08:34:21.28#ibcon#end of sib2, iclass 36, count 2 2006.257.08:34:21.28#ibcon#*after write, iclass 36, count 2 2006.257.08:34:21.28#ibcon#*before return 0, iclass 36, count 2 2006.257.08:34:21.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:21.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:34:21.28#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.08:34:21.28#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:21.28#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:21.40#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:21.40#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:21.40#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:34:21.40#ibcon#first serial, iclass 36, count 0 2006.257.08:34:21.40#ibcon#enter sib2, iclass 36, count 0 2006.257.08:34:21.40#ibcon#flushed, iclass 36, count 0 2006.257.08:34:21.40#ibcon#about to write, iclass 36, count 0 2006.257.08:34:21.40#ibcon#wrote, iclass 36, count 0 2006.257.08:34:21.40#ibcon#about to read 3, iclass 36, count 0 2006.257.08:34:21.42#ibcon#read 3, iclass 36, count 0 2006.257.08:34:21.42#ibcon#about to read 4, iclass 36, count 0 2006.257.08:34:21.42#ibcon#read 4, iclass 36, count 0 2006.257.08:34:21.42#ibcon#about to read 5, iclass 36, count 0 2006.257.08:34:21.42#ibcon#read 5, iclass 36, count 0 2006.257.08:34:21.42#ibcon#about to read 6, iclass 36, count 0 2006.257.08:34:21.42#ibcon#read 6, iclass 36, count 0 2006.257.08:34:21.42#ibcon#end of sib2, iclass 36, count 0 2006.257.08:34:21.42#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:34:21.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:34:21.42#ibcon#[27=USB\r\n] 2006.257.08:34:21.42#ibcon#*before write, iclass 36, count 0 2006.257.08:34:21.42#ibcon#enter sib2, iclass 36, count 0 2006.257.08:34:21.42#ibcon#flushed, iclass 36, count 0 2006.257.08:34:21.42#ibcon#about to write, iclass 36, count 0 2006.257.08:34:21.42#ibcon#wrote, iclass 36, count 0 2006.257.08:34:21.42#ibcon#about to read 3, iclass 36, count 0 2006.257.08:34:21.45#ibcon#read 3, iclass 36, count 0 2006.257.08:34:21.45#ibcon#about to read 4, iclass 36, count 0 2006.257.08:34:21.45#ibcon#read 4, iclass 36, count 0 2006.257.08:34:21.45#ibcon#about to read 5, iclass 36, count 0 2006.257.08:34:21.45#ibcon#read 5, iclass 36, count 0 2006.257.08:34:21.45#ibcon#about to read 6, iclass 36, count 0 2006.257.08:34:21.45#ibcon#read 6, iclass 36, count 0 2006.257.08:34:21.45#ibcon#end of sib2, iclass 36, count 0 2006.257.08:34:21.45#ibcon#*after write, iclass 36, count 0 2006.257.08:34:21.45#ibcon#*before return 0, iclass 36, count 0 2006.257.08:34:21.45#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:21.45#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:34:21.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:34:21.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:34:21.45$vck44/vblo=6,719.99 2006.257.08:34:21.45#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.08:34:21.45#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.08:34:21.45#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:21.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:21.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:21.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:21.45#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:34:21.45#ibcon#first serial, iclass 38, count 0 2006.257.08:34:21.45#ibcon#enter sib2, iclass 38, count 0 2006.257.08:34:21.45#ibcon#flushed, iclass 38, count 0 2006.257.08:34:21.45#ibcon#about to write, iclass 38, count 0 2006.257.08:34:21.45#ibcon#wrote, iclass 38, count 0 2006.257.08:34:21.45#ibcon#about to read 3, iclass 38, count 0 2006.257.08:34:21.47#ibcon#read 3, iclass 38, count 0 2006.257.08:34:21.47#ibcon#about to read 4, iclass 38, count 0 2006.257.08:34:21.47#ibcon#read 4, iclass 38, count 0 2006.257.08:34:21.47#ibcon#about to read 5, iclass 38, count 0 2006.257.08:34:21.47#ibcon#read 5, iclass 38, count 0 2006.257.08:34:21.47#ibcon#about to read 6, iclass 38, count 0 2006.257.08:34:21.47#ibcon#read 6, iclass 38, count 0 2006.257.08:34:21.47#ibcon#end of sib2, iclass 38, count 0 2006.257.08:34:21.47#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:34:21.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:34:21.47#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:34:21.47#ibcon#*before write, iclass 38, count 0 2006.257.08:34:21.47#ibcon#enter sib2, iclass 38, count 0 2006.257.08:34:21.47#ibcon#flushed, iclass 38, count 0 2006.257.08:34:21.47#ibcon#about to write, iclass 38, count 0 2006.257.08:34:21.47#ibcon#wrote, iclass 38, count 0 2006.257.08:34:21.47#ibcon#about to read 3, iclass 38, count 0 2006.257.08:34:21.51#ibcon#read 3, iclass 38, count 0 2006.257.08:34:21.51#ibcon#about to read 4, iclass 38, count 0 2006.257.08:34:21.51#ibcon#read 4, iclass 38, count 0 2006.257.08:34:21.51#ibcon#about to read 5, iclass 38, count 0 2006.257.08:34:21.51#ibcon#read 5, iclass 38, count 0 2006.257.08:34:21.51#ibcon#about to read 6, iclass 38, count 0 2006.257.08:34:21.51#ibcon#read 6, iclass 38, count 0 2006.257.08:34:21.51#ibcon#end of sib2, iclass 38, count 0 2006.257.08:34:21.51#ibcon#*after write, iclass 38, count 0 2006.257.08:34:21.51#ibcon#*before return 0, iclass 38, count 0 2006.257.08:34:21.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:21.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:34:21.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:34:21.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:34:21.51$vck44/vb=6,4 2006.257.08:34:21.51#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.08:34:21.51#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.08:34:21.51#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:21.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:21.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:21.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:21.57#ibcon#enter wrdev, iclass 40, count 2 2006.257.08:34:21.57#ibcon#first serial, iclass 40, count 2 2006.257.08:34:21.57#ibcon#enter sib2, iclass 40, count 2 2006.257.08:34:21.57#ibcon#flushed, iclass 40, count 2 2006.257.08:34:21.57#ibcon#about to write, iclass 40, count 2 2006.257.08:34:21.57#ibcon#wrote, iclass 40, count 2 2006.257.08:34:21.57#ibcon#about to read 3, iclass 40, count 2 2006.257.08:34:21.59#ibcon#read 3, iclass 40, count 2 2006.257.08:34:21.59#ibcon#about to read 4, iclass 40, count 2 2006.257.08:34:21.59#ibcon#read 4, iclass 40, count 2 2006.257.08:34:21.59#ibcon#about to read 5, iclass 40, count 2 2006.257.08:34:21.59#ibcon#read 5, iclass 40, count 2 2006.257.08:34:21.59#ibcon#about to read 6, iclass 40, count 2 2006.257.08:34:21.59#ibcon#read 6, iclass 40, count 2 2006.257.08:34:21.59#ibcon#end of sib2, iclass 40, count 2 2006.257.08:34:21.59#ibcon#*mode == 0, iclass 40, count 2 2006.257.08:34:21.59#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.08:34:21.59#ibcon#[27=AT06-04\r\n] 2006.257.08:34:21.59#ibcon#*before write, iclass 40, count 2 2006.257.08:34:21.59#ibcon#enter sib2, iclass 40, count 2 2006.257.08:34:21.59#ibcon#flushed, iclass 40, count 2 2006.257.08:34:21.59#ibcon#about to write, iclass 40, count 2 2006.257.08:34:21.59#ibcon#wrote, iclass 40, count 2 2006.257.08:34:21.59#ibcon#about to read 3, iclass 40, count 2 2006.257.08:34:21.62#ibcon#read 3, iclass 40, count 2 2006.257.08:34:21.62#ibcon#about to read 4, iclass 40, count 2 2006.257.08:34:21.62#ibcon#read 4, iclass 40, count 2 2006.257.08:34:21.62#ibcon#about to read 5, iclass 40, count 2 2006.257.08:34:21.62#ibcon#read 5, iclass 40, count 2 2006.257.08:34:21.62#ibcon#about to read 6, iclass 40, count 2 2006.257.08:34:21.62#ibcon#read 6, iclass 40, count 2 2006.257.08:34:21.62#ibcon#end of sib2, iclass 40, count 2 2006.257.08:34:21.62#ibcon#*after write, iclass 40, count 2 2006.257.08:34:21.62#ibcon#*before return 0, iclass 40, count 2 2006.257.08:34:21.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:21.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:34:21.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.08:34:21.62#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:21.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:21.74#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:21.74#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:21.74#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:34:21.74#ibcon#first serial, iclass 40, count 0 2006.257.08:34:21.74#ibcon#enter sib2, iclass 40, count 0 2006.257.08:34:21.74#ibcon#flushed, iclass 40, count 0 2006.257.08:34:21.74#ibcon#about to write, iclass 40, count 0 2006.257.08:34:21.74#ibcon#wrote, iclass 40, count 0 2006.257.08:34:21.74#ibcon#about to read 3, iclass 40, count 0 2006.257.08:34:21.76#ibcon#read 3, iclass 40, count 0 2006.257.08:34:21.76#ibcon#about to read 4, iclass 40, count 0 2006.257.08:34:21.76#ibcon#read 4, iclass 40, count 0 2006.257.08:34:21.76#ibcon#about to read 5, iclass 40, count 0 2006.257.08:34:21.76#ibcon#read 5, iclass 40, count 0 2006.257.08:34:21.76#ibcon#about to read 6, iclass 40, count 0 2006.257.08:34:21.76#ibcon#read 6, iclass 40, count 0 2006.257.08:34:21.76#ibcon#end of sib2, iclass 40, count 0 2006.257.08:34:21.76#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:34:21.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:34:21.76#ibcon#[27=USB\r\n] 2006.257.08:34:21.76#ibcon#*before write, iclass 40, count 0 2006.257.08:34:21.76#ibcon#enter sib2, iclass 40, count 0 2006.257.08:34:21.76#ibcon#flushed, iclass 40, count 0 2006.257.08:34:21.76#ibcon#about to write, iclass 40, count 0 2006.257.08:34:21.76#ibcon#wrote, iclass 40, count 0 2006.257.08:34:21.76#ibcon#about to read 3, iclass 40, count 0 2006.257.08:34:21.79#ibcon#read 3, iclass 40, count 0 2006.257.08:34:21.79#ibcon#about to read 4, iclass 40, count 0 2006.257.08:34:21.79#ibcon#read 4, iclass 40, count 0 2006.257.08:34:21.79#ibcon#about to read 5, iclass 40, count 0 2006.257.08:34:21.79#ibcon#read 5, iclass 40, count 0 2006.257.08:34:21.79#ibcon#about to read 6, iclass 40, count 0 2006.257.08:34:21.79#ibcon#read 6, iclass 40, count 0 2006.257.08:34:21.79#ibcon#end of sib2, iclass 40, count 0 2006.257.08:34:21.79#ibcon#*after write, iclass 40, count 0 2006.257.08:34:21.79#ibcon#*before return 0, iclass 40, count 0 2006.257.08:34:21.79#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:21.79#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:34:21.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:34:21.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:34:21.79$vck44/vblo=7,734.99 2006.257.08:34:21.79#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.08:34:21.79#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.08:34:21.79#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:21.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:21.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:21.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:21.79#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:34:21.79#ibcon#first serial, iclass 4, count 0 2006.257.08:34:21.79#ibcon#enter sib2, iclass 4, count 0 2006.257.08:34:21.79#ibcon#flushed, iclass 4, count 0 2006.257.08:34:21.79#ibcon#about to write, iclass 4, count 0 2006.257.08:34:21.79#ibcon#wrote, iclass 4, count 0 2006.257.08:34:21.79#ibcon#about to read 3, iclass 4, count 0 2006.257.08:34:21.81#ibcon#read 3, iclass 4, count 0 2006.257.08:34:21.81#ibcon#about to read 4, iclass 4, count 0 2006.257.08:34:21.81#ibcon#read 4, iclass 4, count 0 2006.257.08:34:21.81#ibcon#about to read 5, iclass 4, count 0 2006.257.08:34:21.81#ibcon#read 5, iclass 4, count 0 2006.257.08:34:21.81#ibcon#about to read 6, iclass 4, count 0 2006.257.08:34:21.81#ibcon#read 6, iclass 4, count 0 2006.257.08:34:21.81#ibcon#end of sib2, iclass 4, count 0 2006.257.08:34:21.81#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:34:21.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:34:21.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:34:21.81#ibcon#*before write, iclass 4, count 0 2006.257.08:34:21.81#ibcon#enter sib2, iclass 4, count 0 2006.257.08:34:21.81#ibcon#flushed, iclass 4, count 0 2006.257.08:34:21.81#ibcon#about to write, iclass 4, count 0 2006.257.08:34:21.81#ibcon#wrote, iclass 4, count 0 2006.257.08:34:21.81#ibcon#about to read 3, iclass 4, count 0 2006.257.08:34:21.85#ibcon#read 3, iclass 4, count 0 2006.257.08:34:21.85#ibcon#about to read 4, iclass 4, count 0 2006.257.08:34:21.85#ibcon#read 4, iclass 4, count 0 2006.257.08:34:21.85#ibcon#about to read 5, iclass 4, count 0 2006.257.08:34:21.85#ibcon#read 5, iclass 4, count 0 2006.257.08:34:21.85#ibcon#about to read 6, iclass 4, count 0 2006.257.08:34:21.85#ibcon#read 6, iclass 4, count 0 2006.257.08:34:21.85#ibcon#end of sib2, iclass 4, count 0 2006.257.08:34:21.85#ibcon#*after write, iclass 4, count 0 2006.257.08:34:21.85#ibcon#*before return 0, iclass 4, count 0 2006.257.08:34:21.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:21.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:34:21.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:34:21.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:34:21.85$vck44/vb=7,4 2006.257.08:34:21.85#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.08:34:21.85#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.08:34:21.85#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:21.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:21.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:21.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:21.91#ibcon#enter wrdev, iclass 6, count 2 2006.257.08:34:21.91#ibcon#first serial, iclass 6, count 2 2006.257.08:34:21.91#ibcon#enter sib2, iclass 6, count 2 2006.257.08:34:21.91#ibcon#flushed, iclass 6, count 2 2006.257.08:34:21.91#ibcon#about to write, iclass 6, count 2 2006.257.08:34:21.91#ibcon#wrote, iclass 6, count 2 2006.257.08:34:21.91#ibcon#about to read 3, iclass 6, count 2 2006.257.08:34:21.93#ibcon#read 3, iclass 6, count 2 2006.257.08:34:21.93#ibcon#about to read 4, iclass 6, count 2 2006.257.08:34:21.93#ibcon#read 4, iclass 6, count 2 2006.257.08:34:21.93#ibcon#about to read 5, iclass 6, count 2 2006.257.08:34:21.93#ibcon#read 5, iclass 6, count 2 2006.257.08:34:21.93#ibcon#about to read 6, iclass 6, count 2 2006.257.08:34:21.93#ibcon#read 6, iclass 6, count 2 2006.257.08:34:21.93#ibcon#end of sib2, iclass 6, count 2 2006.257.08:34:21.93#ibcon#*mode == 0, iclass 6, count 2 2006.257.08:34:21.93#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.08:34:21.93#ibcon#[27=AT07-04\r\n] 2006.257.08:34:21.93#ibcon#*before write, iclass 6, count 2 2006.257.08:34:21.93#ibcon#enter sib2, iclass 6, count 2 2006.257.08:34:21.93#ibcon#flushed, iclass 6, count 2 2006.257.08:34:21.93#ibcon#about to write, iclass 6, count 2 2006.257.08:34:21.93#ibcon#wrote, iclass 6, count 2 2006.257.08:34:21.93#ibcon#about to read 3, iclass 6, count 2 2006.257.08:34:21.96#ibcon#read 3, iclass 6, count 2 2006.257.08:34:21.96#ibcon#about to read 4, iclass 6, count 2 2006.257.08:34:21.96#ibcon#read 4, iclass 6, count 2 2006.257.08:34:21.96#ibcon#about to read 5, iclass 6, count 2 2006.257.08:34:21.96#ibcon#read 5, iclass 6, count 2 2006.257.08:34:21.96#ibcon#about to read 6, iclass 6, count 2 2006.257.08:34:21.96#ibcon#read 6, iclass 6, count 2 2006.257.08:34:21.96#ibcon#end of sib2, iclass 6, count 2 2006.257.08:34:21.96#ibcon#*after write, iclass 6, count 2 2006.257.08:34:21.96#ibcon#*before return 0, iclass 6, count 2 2006.257.08:34:21.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:21.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:34:21.96#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.08:34:21.96#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:21.96#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:22.08#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:22.08#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:22.08#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:34:22.08#ibcon#first serial, iclass 6, count 0 2006.257.08:34:22.08#ibcon#enter sib2, iclass 6, count 0 2006.257.08:34:22.08#ibcon#flushed, iclass 6, count 0 2006.257.08:34:22.08#ibcon#about to write, iclass 6, count 0 2006.257.08:34:22.08#ibcon#wrote, iclass 6, count 0 2006.257.08:34:22.08#ibcon#about to read 3, iclass 6, count 0 2006.257.08:34:22.10#ibcon#read 3, iclass 6, count 0 2006.257.08:34:22.10#ibcon#about to read 4, iclass 6, count 0 2006.257.08:34:22.10#ibcon#read 4, iclass 6, count 0 2006.257.08:34:22.10#ibcon#about to read 5, iclass 6, count 0 2006.257.08:34:22.10#ibcon#read 5, iclass 6, count 0 2006.257.08:34:22.10#ibcon#about to read 6, iclass 6, count 0 2006.257.08:34:22.10#ibcon#read 6, iclass 6, count 0 2006.257.08:34:22.10#ibcon#end of sib2, iclass 6, count 0 2006.257.08:34:22.10#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:34:22.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:34:22.10#ibcon#[27=USB\r\n] 2006.257.08:34:22.10#ibcon#*before write, iclass 6, count 0 2006.257.08:34:22.10#ibcon#enter sib2, iclass 6, count 0 2006.257.08:34:22.10#ibcon#flushed, iclass 6, count 0 2006.257.08:34:22.10#ibcon#about to write, iclass 6, count 0 2006.257.08:34:22.10#ibcon#wrote, iclass 6, count 0 2006.257.08:34:22.10#ibcon#about to read 3, iclass 6, count 0 2006.257.08:34:22.13#ibcon#read 3, iclass 6, count 0 2006.257.08:34:22.13#ibcon#about to read 4, iclass 6, count 0 2006.257.08:34:22.13#ibcon#read 4, iclass 6, count 0 2006.257.08:34:22.13#ibcon#about to read 5, iclass 6, count 0 2006.257.08:34:22.13#ibcon#read 5, iclass 6, count 0 2006.257.08:34:22.13#ibcon#about to read 6, iclass 6, count 0 2006.257.08:34:22.13#ibcon#read 6, iclass 6, count 0 2006.257.08:34:22.13#ibcon#end of sib2, iclass 6, count 0 2006.257.08:34:22.13#ibcon#*after write, iclass 6, count 0 2006.257.08:34:22.13#ibcon#*before return 0, iclass 6, count 0 2006.257.08:34:22.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:22.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:34:22.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:34:22.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:34:22.13$vck44/vblo=8,744.99 2006.257.08:34:22.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.08:34:22.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.08:34:22.13#ibcon#ireg 17 cls_cnt 0 2006.257.08:34:22.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:22.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:22.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:22.13#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:34:22.13#ibcon#first serial, iclass 10, count 0 2006.257.08:34:22.13#ibcon#enter sib2, iclass 10, count 0 2006.257.08:34:22.13#ibcon#flushed, iclass 10, count 0 2006.257.08:34:22.13#ibcon#about to write, iclass 10, count 0 2006.257.08:34:22.13#ibcon#wrote, iclass 10, count 0 2006.257.08:34:22.13#ibcon#about to read 3, iclass 10, count 0 2006.257.08:34:22.15#ibcon#read 3, iclass 10, count 0 2006.257.08:34:22.15#ibcon#about to read 4, iclass 10, count 0 2006.257.08:34:22.15#ibcon#read 4, iclass 10, count 0 2006.257.08:34:22.15#ibcon#about to read 5, iclass 10, count 0 2006.257.08:34:22.15#ibcon#read 5, iclass 10, count 0 2006.257.08:34:22.15#ibcon#about to read 6, iclass 10, count 0 2006.257.08:34:22.15#ibcon#read 6, iclass 10, count 0 2006.257.08:34:22.15#ibcon#end of sib2, iclass 10, count 0 2006.257.08:34:22.15#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:34:22.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:34:22.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:34:22.15#ibcon#*before write, iclass 10, count 0 2006.257.08:34:22.15#ibcon#enter sib2, iclass 10, count 0 2006.257.08:34:22.15#ibcon#flushed, iclass 10, count 0 2006.257.08:34:22.15#ibcon#about to write, iclass 10, count 0 2006.257.08:34:22.15#ibcon#wrote, iclass 10, count 0 2006.257.08:34:22.15#ibcon#about to read 3, iclass 10, count 0 2006.257.08:34:22.19#ibcon#read 3, iclass 10, count 0 2006.257.08:34:22.19#ibcon#about to read 4, iclass 10, count 0 2006.257.08:34:22.19#ibcon#read 4, iclass 10, count 0 2006.257.08:34:22.19#ibcon#about to read 5, iclass 10, count 0 2006.257.08:34:22.19#ibcon#read 5, iclass 10, count 0 2006.257.08:34:22.19#ibcon#about to read 6, iclass 10, count 0 2006.257.08:34:22.19#ibcon#read 6, iclass 10, count 0 2006.257.08:34:22.19#ibcon#end of sib2, iclass 10, count 0 2006.257.08:34:22.19#ibcon#*after write, iclass 10, count 0 2006.257.08:34:22.19#ibcon#*before return 0, iclass 10, count 0 2006.257.08:34:22.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:22.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:34:22.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:34:22.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:34:22.19$vck44/vb=8,4 2006.257.08:34:22.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.08:34:22.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.08:34:22.19#ibcon#ireg 11 cls_cnt 2 2006.257.08:34:22.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:22.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:22.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:22.25#ibcon#enter wrdev, iclass 12, count 2 2006.257.08:34:22.25#ibcon#first serial, iclass 12, count 2 2006.257.08:34:22.25#ibcon#enter sib2, iclass 12, count 2 2006.257.08:34:22.25#ibcon#flushed, iclass 12, count 2 2006.257.08:34:22.25#ibcon#about to write, iclass 12, count 2 2006.257.08:34:22.25#ibcon#wrote, iclass 12, count 2 2006.257.08:34:22.25#ibcon#about to read 3, iclass 12, count 2 2006.257.08:34:22.27#ibcon#read 3, iclass 12, count 2 2006.257.08:34:22.27#ibcon#about to read 4, iclass 12, count 2 2006.257.08:34:22.27#ibcon#read 4, iclass 12, count 2 2006.257.08:34:22.27#ibcon#about to read 5, iclass 12, count 2 2006.257.08:34:22.27#ibcon#read 5, iclass 12, count 2 2006.257.08:34:22.27#ibcon#about to read 6, iclass 12, count 2 2006.257.08:34:22.27#ibcon#read 6, iclass 12, count 2 2006.257.08:34:22.27#ibcon#end of sib2, iclass 12, count 2 2006.257.08:34:22.27#ibcon#*mode == 0, iclass 12, count 2 2006.257.08:34:22.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.08:34:22.27#ibcon#[27=AT08-04\r\n] 2006.257.08:34:22.27#ibcon#*before write, iclass 12, count 2 2006.257.08:34:22.27#ibcon#enter sib2, iclass 12, count 2 2006.257.08:34:22.27#ibcon#flushed, iclass 12, count 2 2006.257.08:34:22.27#ibcon#about to write, iclass 12, count 2 2006.257.08:34:22.27#ibcon#wrote, iclass 12, count 2 2006.257.08:34:22.27#ibcon#about to read 3, iclass 12, count 2 2006.257.08:34:22.30#ibcon#read 3, iclass 12, count 2 2006.257.08:34:22.30#ibcon#about to read 4, iclass 12, count 2 2006.257.08:34:22.30#ibcon#read 4, iclass 12, count 2 2006.257.08:34:22.30#ibcon#about to read 5, iclass 12, count 2 2006.257.08:34:22.30#ibcon#read 5, iclass 12, count 2 2006.257.08:34:22.30#ibcon#about to read 6, iclass 12, count 2 2006.257.08:34:22.30#ibcon#read 6, iclass 12, count 2 2006.257.08:34:22.30#ibcon#end of sib2, iclass 12, count 2 2006.257.08:34:22.30#ibcon#*after write, iclass 12, count 2 2006.257.08:34:22.30#ibcon#*before return 0, iclass 12, count 2 2006.257.08:34:22.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:22.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:34:22.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.08:34:22.30#ibcon#ireg 7 cls_cnt 0 2006.257.08:34:22.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:22.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:22.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:22.42#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:34:22.42#ibcon#first serial, iclass 12, count 0 2006.257.08:34:22.42#ibcon#enter sib2, iclass 12, count 0 2006.257.08:34:22.42#ibcon#flushed, iclass 12, count 0 2006.257.08:34:22.42#ibcon#about to write, iclass 12, count 0 2006.257.08:34:22.42#ibcon#wrote, iclass 12, count 0 2006.257.08:34:22.42#ibcon#about to read 3, iclass 12, count 0 2006.257.08:34:22.44#ibcon#read 3, iclass 12, count 0 2006.257.08:34:22.44#ibcon#about to read 4, iclass 12, count 0 2006.257.08:34:22.44#ibcon#read 4, iclass 12, count 0 2006.257.08:34:22.44#ibcon#about to read 5, iclass 12, count 0 2006.257.08:34:22.44#ibcon#read 5, iclass 12, count 0 2006.257.08:34:22.44#ibcon#about to read 6, iclass 12, count 0 2006.257.08:34:22.44#ibcon#read 6, iclass 12, count 0 2006.257.08:34:22.44#ibcon#end of sib2, iclass 12, count 0 2006.257.08:34:22.44#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:34:22.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:34:22.44#ibcon#[27=USB\r\n] 2006.257.08:34:22.44#ibcon#*before write, iclass 12, count 0 2006.257.08:34:22.44#ibcon#enter sib2, iclass 12, count 0 2006.257.08:34:22.44#ibcon#flushed, iclass 12, count 0 2006.257.08:34:22.44#ibcon#about to write, iclass 12, count 0 2006.257.08:34:22.44#ibcon#wrote, iclass 12, count 0 2006.257.08:34:22.44#ibcon#about to read 3, iclass 12, count 0 2006.257.08:34:22.47#ibcon#read 3, iclass 12, count 0 2006.257.08:34:22.47#ibcon#about to read 4, iclass 12, count 0 2006.257.08:34:22.47#ibcon#read 4, iclass 12, count 0 2006.257.08:34:22.47#ibcon#about to read 5, iclass 12, count 0 2006.257.08:34:22.47#ibcon#read 5, iclass 12, count 0 2006.257.08:34:22.47#ibcon#about to read 6, iclass 12, count 0 2006.257.08:34:22.47#ibcon#read 6, iclass 12, count 0 2006.257.08:34:22.47#ibcon#end of sib2, iclass 12, count 0 2006.257.08:34:22.47#ibcon#*after write, iclass 12, count 0 2006.257.08:34:22.47#ibcon#*before return 0, iclass 12, count 0 2006.257.08:34:22.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:22.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:34:22.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:34:22.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:34:22.47$vck44/vabw=wide 2006.257.08:34:22.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.08:34:22.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.08:34:22.47#ibcon#ireg 8 cls_cnt 0 2006.257.08:34:22.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:22.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:22.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:22.47#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:34:22.47#ibcon#first serial, iclass 14, count 0 2006.257.08:34:22.47#ibcon#enter sib2, iclass 14, count 0 2006.257.08:34:22.47#ibcon#flushed, iclass 14, count 0 2006.257.08:34:22.47#ibcon#about to write, iclass 14, count 0 2006.257.08:34:22.47#ibcon#wrote, iclass 14, count 0 2006.257.08:34:22.47#ibcon#about to read 3, iclass 14, count 0 2006.257.08:34:22.49#ibcon#read 3, iclass 14, count 0 2006.257.08:34:22.49#ibcon#about to read 4, iclass 14, count 0 2006.257.08:34:22.49#ibcon#read 4, iclass 14, count 0 2006.257.08:34:22.49#ibcon#about to read 5, iclass 14, count 0 2006.257.08:34:22.49#ibcon#read 5, iclass 14, count 0 2006.257.08:34:22.49#ibcon#about to read 6, iclass 14, count 0 2006.257.08:34:22.49#ibcon#read 6, iclass 14, count 0 2006.257.08:34:22.49#ibcon#end of sib2, iclass 14, count 0 2006.257.08:34:22.49#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:34:22.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:34:22.49#ibcon#[25=BW32\r\n] 2006.257.08:34:22.49#ibcon#*before write, iclass 14, count 0 2006.257.08:34:22.49#ibcon#enter sib2, iclass 14, count 0 2006.257.08:34:22.49#ibcon#flushed, iclass 14, count 0 2006.257.08:34:22.49#ibcon#about to write, iclass 14, count 0 2006.257.08:34:22.49#ibcon#wrote, iclass 14, count 0 2006.257.08:34:22.49#ibcon#about to read 3, iclass 14, count 0 2006.257.08:34:22.52#ibcon#read 3, iclass 14, count 0 2006.257.08:34:22.52#ibcon#about to read 4, iclass 14, count 0 2006.257.08:34:22.52#ibcon#read 4, iclass 14, count 0 2006.257.08:34:22.52#ibcon#about to read 5, iclass 14, count 0 2006.257.08:34:22.52#ibcon#read 5, iclass 14, count 0 2006.257.08:34:22.52#ibcon#about to read 6, iclass 14, count 0 2006.257.08:34:22.52#ibcon#read 6, iclass 14, count 0 2006.257.08:34:22.52#ibcon#end of sib2, iclass 14, count 0 2006.257.08:34:22.52#ibcon#*after write, iclass 14, count 0 2006.257.08:34:22.52#ibcon#*before return 0, iclass 14, count 0 2006.257.08:34:22.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:22.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:34:22.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:34:22.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:34:22.52$vck44/vbbw=wide 2006.257.08:34:22.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.08:34:22.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.08:34:22.52#ibcon#ireg 8 cls_cnt 0 2006.257.08:34:22.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:34:22.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:34:22.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:34:22.59#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:34:22.59#ibcon#first serial, iclass 16, count 0 2006.257.08:34:22.59#ibcon#enter sib2, iclass 16, count 0 2006.257.08:34:22.59#ibcon#flushed, iclass 16, count 0 2006.257.08:34:22.59#ibcon#about to write, iclass 16, count 0 2006.257.08:34:22.59#ibcon#wrote, iclass 16, count 0 2006.257.08:34:22.59#ibcon#about to read 3, iclass 16, count 0 2006.257.08:34:22.61#ibcon#read 3, iclass 16, count 0 2006.257.08:34:22.61#ibcon#about to read 4, iclass 16, count 0 2006.257.08:34:22.61#ibcon#read 4, iclass 16, count 0 2006.257.08:34:22.61#ibcon#about to read 5, iclass 16, count 0 2006.257.08:34:22.61#ibcon#read 5, iclass 16, count 0 2006.257.08:34:22.61#ibcon#about to read 6, iclass 16, count 0 2006.257.08:34:22.61#ibcon#read 6, iclass 16, count 0 2006.257.08:34:22.61#ibcon#end of sib2, iclass 16, count 0 2006.257.08:34:22.61#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:34:22.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:34:22.61#ibcon#[27=BW32\r\n] 2006.257.08:34:22.61#ibcon#*before write, iclass 16, count 0 2006.257.08:34:22.61#ibcon#enter sib2, iclass 16, count 0 2006.257.08:34:22.61#ibcon#flushed, iclass 16, count 0 2006.257.08:34:22.61#ibcon#about to write, iclass 16, count 0 2006.257.08:34:22.61#ibcon#wrote, iclass 16, count 0 2006.257.08:34:22.61#ibcon#about to read 3, iclass 16, count 0 2006.257.08:34:22.64#ibcon#read 3, iclass 16, count 0 2006.257.08:34:22.64#ibcon#about to read 4, iclass 16, count 0 2006.257.08:34:22.64#ibcon#read 4, iclass 16, count 0 2006.257.08:34:22.64#ibcon#about to read 5, iclass 16, count 0 2006.257.08:34:22.64#ibcon#read 5, iclass 16, count 0 2006.257.08:34:22.64#ibcon#about to read 6, iclass 16, count 0 2006.257.08:34:22.64#ibcon#read 6, iclass 16, count 0 2006.257.08:34:22.64#ibcon#end of sib2, iclass 16, count 0 2006.257.08:34:22.64#ibcon#*after write, iclass 16, count 0 2006.257.08:34:22.64#ibcon#*before return 0, iclass 16, count 0 2006.257.08:34:22.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:34:22.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:34:22.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:34:22.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:34:22.64$setupk4/ifdk4 2006.257.08:34:22.64$ifdk4/lo= 2006.257.08:34:22.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:34:22.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:34:22.64$ifdk4/patch= 2006.257.08:34:22.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:34:22.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:34:22.64$setupk4/!*+20s 2006.257.08:34:25.14#trakl#Source acquired 2006.257.08:34:27.14#flagr#flagr/antenna,acquired 2006.257.08:34:30.49#abcon#<5=/16 1.0 3.1 20.65 911013.0\r\n> 2006.257.08:34:30.51#abcon#{5=INTERFACE CLEAR} 2006.257.08:34:30.57#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:34:37.15$setupk4/"tpicd 2006.257.08:34:37.15$setupk4/echo=off 2006.257.08:34:37.15$setupk4/xlog=off 2006.257.08:34:37.15:!2006.257.08:42:23 2006.257.08:42:23.00:preob 2006.257.08:42:23.13/onsource/TRACKING 2006.257.08:42:23.13:!2006.257.08:42:33 2006.257.08:42:33.00:"tape 2006.257.08:42:33.00:"st=record 2006.257.08:42:33.00:data_valid=on 2006.257.08:42:33.00:midob 2006.257.08:42:33.13/onsource/TRACKING 2006.257.08:42:33.13/wx/20.50,1013.1,92 2006.257.08:42:33.24/cable/+6.4738E-03 2006.257.08:42:34.33/va/01,08,usb,yes,35,37 2006.257.08:42:34.33/va/02,07,usb,yes,38,38 2006.257.08:42:34.33/va/03,08,usb,yes,34,36 2006.257.08:42:34.33/va/04,07,usb,yes,39,41 2006.257.08:42:34.33/va/05,04,usb,yes,35,35 2006.257.08:42:34.33/va/06,04,usb,yes,39,38 2006.257.08:42:34.33/va/07,04,usb,yes,40,40 2006.257.08:42:34.33/va/08,04,usb,yes,33,40 2006.257.08:42:34.56/valo/01,524.99,yes,locked 2006.257.08:42:34.56/valo/02,534.99,yes,locked 2006.257.08:42:34.56/valo/03,564.99,yes,locked 2006.257.08:42:34.56/valo/04,624.99,yes,locked 2006.257.08:42:34.56/valo/05,734.99,yes,locked 2006.257.08:42:34.56/valo/06,814.99,yes,locked 2006.257.08:42:34.56/valo/07,864.99,yes,locked 2006.257.08:42:34.56/valo/08,884.99,yes,locked 2006.257.08:42:35.65/vb/01,04,usb,yes,34,31 2006.257.08:42:35.65/vb/02,05,usb,yes,32,32 2006.257.08:42:35.65/vb/03,04,usb,yes,33,36 2006.257.08:42:35.65/vb/04,05,usb,yes,33,32 2006.257.08:42:35.65/vb/05,04,usb,yes,29,32 2006.257.08:42:35.65/vb/06,04,usb,yes,34,30 2006.257.08:42:35.65/vb/07,04,usb,yes,34,34 2006.257.08:42:35.65/vb/08,04,usb,yes,31,35 2006.257.08:42:35.88/vblo/01,629.99,yes,locked 2006.257.08:42:35.88/vblo/02,634.99,yes,locked 2006.257.08:42:35.88/vblo/03,649.99,yes,locked 2006.257.08:42:35.88/vblo/04,679.99,yes,locked 2006.257.08:42:35.88/vblo/05,709.99,yes,locked 2006.257.08:42:35.88/vblo/06,719.99,yes,locked 2006.257.08:42:35.88/vblo/07,734.99,yes,locked 2006.257.08:42:35.88/vblo/08,744.99,yes,locked 2006.257.08:42:36.03/vabw/8 2006.257.08:42:36.18/vbbw/8 2006.257.08:42:36.27/xfe/off,on,15.0 2006.257.08:42:36.65/ifatt/23,28,28,28 2006.257.08:42:37.07/fmout-gps/S +4.65E-07 2006.257.08:42:37.11:!2006.257.08:43:13 2006.257.08:43:13.01:data_valid=off 2006.257.08:43:13.01:"et 2006.257.08:43:13.02:!+3s 2006.257.08:43:16.03:"tape 2006.257.08:43:16.03:postob 2006.257.08:43:16.20/cable/+6.4732E-03 2006.257.08:43:16.20/wx/20.47,1013.1,92 2006.257.08:43:16.26/fmout-gps/S +4.66E-07 2006.257.08:43:16.26:scan_name=257-0844,jd0609,40 2006.257.08:43:16.26:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.257.08:43:18.14#flagr#flagr/antenna,new-source 2006.257.08:43:18.14:checkk5 2006.257.08:43:18.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:43:18.89/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:43:19.31/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:43:19.71/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:43:20.10/chk_obsdata//k5ts1/T2570842??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.08:43:20.49/chk_obsdata//k5ts2/T2570842??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.08:43:20.90/chk_obsdata//k5ts3/T2570842??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.08:43:21.31/chk_obsdata//k5ts4/T2570842??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.08:43:22.05/k5log//k5ts1_log_newline 2006.257.08:43:22.75/k5log//k5ts2_log_newline 2006.257.08:43:23.45/k5log//k5ts3_log_newline 2006.257.08:43:24.17/k5log//k5ts4_log_newline 2006.257.08:43:24.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:43:24.19:setupk4=1 2006.257.08:43:24.19$setupk4/echo=on 2006.257.08:43:24.19$setupk4/pcalon 2006.257.08:43:24.19$pcalon/"no phase cal control is implemented here 2006.257.08:43:24.19$setupk4/"tpicd=stop 2006.257.08:43:24.19$setupk4/"rec=synch_on 2006.257.08:43:24.19$setupk4/"rec_mode=128 2006.257.08:43:24.19$setupk4/!* 2006.257.08:43:24.19$setupk4/recpk4 2006.257.08:43:24.19$recpk4/recpatch= 2006.257.08:43:24.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:43:24.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:43:24.20$setupk4/vck44 2006.257.08:43:24.20$vck44/valo=1,524.99 2006.257.08:43:24.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.08:43:24.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.08:43:24.20#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:24.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:24.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:24.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:24.20#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:43:24.20#ibcon#first serial, iclass 12, count 0 2006.257.08:43:24.20#ibcon#enter sib2, iclass 12, count 0 2006.257.08:43:24.20#ibcon#flushed, iclass 12, count 0 2006.257.08:43:24.20#ibcon#about to write, iclass 12, count 0 2006.257.08:43:24.20#ibcon#wrote, iclass 12, count 0 2006.257.08:43:24.20#ibcon#about to read 3, iclass 12, count 0 2006.257.08:43:24.22#ibcon#read 3, iclass 12, count 0 2006.257.08:43:24.22#ibcon#about to read 4, iclass 12, count 0 2006.257.08:43:24.22#ibcon#read 4, iclass 12, count 0 2006.257.08:43:24.22#ibcon#about to read 5, iclass 12, count 0 2006.257.08:43:24.22#ibcon#read 5, iclass 12, count 0 2006.257.08:43:24.22#ibcon#about to read 6, iclass 12, count 0 2006.257.08:43:24.22#ibcon#read 6, iclass 12, count 0 2006.257.08:43:24.22#ibcon#end of sib2, iclass 12, count 0 2006.257.08:43:24.22#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:43:24.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:43:24.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:43:24.22#ibcon#*before write, iclass 12, count 0 2006.257.08:43:24.22#ibcon#enter sib2, iclass 12, count 0 2006.257.08:43:24.22#ibcon#flushed, iclass 12, count 0 2006.257.08:43:24.22#ibcon#about to write, iclass 12, count 0 2006.257.08:43:24.22#ibcon#wrote, iclass 12, count 0 2006.257.08:43:24.22#ibcon#about to read 3, iclass 12, count 0 2006.257.08:43:24.27#ibcon#read 3, iclass 12, count 0 2006.257.08:43:24.27#ibcon#about to read 4, iclass 12, count 0 2006.257.08:43:24.27#ibcon#read 4, iclass 12, count 0 2006.257.08:43:24.27#ibcon#about to read 5, iclass 12, count 0 2006.257.08:43:24.27#ibcon#read 5, iclass 12, count 0 2006.257.08:43:24.27#ibcon#about to read 6, iclass 12, count 0 2006.257.08:43:24.27#ibcon#read 6, iclass 12, count 0 2006.257.08:43:24.27#ibcon#end of sib2, iclass 12, count 0 2006.257.08:43:24.27#ibcon#*after write, iclass 12, count 0 2006.257.08:43:24.27#ibcon#*before return 0, iclass 12, count 0 2006.257.08:43:24.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:24.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:24.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:43:24.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:43:24.27$vck44/va=1,8 2006.257.08:43:24.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.08:43:24.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.08:43:24.27#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:24.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:24.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:24.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:24.27#ibcon#enter wrdev, iclass 14, count 2 2006.257.08:43:24.27#ibcon#first serial, iclass 14, count 2 2006.257.08:43:24.27#ibcon#enter sib2, iclass 14, count 2 2006.257.08:43:24.27#ibcon#flushed, iclass 14, count 2 2006.257.08:43:24.27#ibcon#about to write, iclass 14, count 2 2006.257.08:43:24.27#ibcon#wrote, iclass 14, count 2 2006.257.08:43:24.27#ibcon#about to read 3, iclass 14, count 2 2006.257.08:43:24.29#ibcon#read 3, iclass 14, count 2 2006.257.08:43:24.29#ibcon#about to read 4, iclass 14, count 2 2006.257.08:43:24.29#ibcon#read 4, iclass 14, count 2 2006.257.08:43:24.29#ibcon#about to read 5, iclass 14, count 2 2006.257.08:43:24.29#ibcon#read 5, iclass 14, count 2 2006.257.08:43:24.29#ibcon#about to read 6, iclass 14, count 2 2006.257.08:43:24.29#ibcon#read 6, iclass 14, count 2 2006.257.08:43:24.29#ibcon#end of sib2, iclass 14, count 2 2006.257.08:43:24.29#ibcon#*mode == 0, iclass 14, count 2 2006.257.08:43:24.29#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.08:43:24.29#ibcon#[25=AT01-08\r\n] 2006.257.08:43:24.29#ibcon#*before write, iclass 14, count 2 2006.257.08:43:24.29#ibcon#enter sib2, iclass 14, count 2 2006.257.08:43:24.29#ibcon#flushed, iclass 14, count 2 2006.257.08:43:24.29#ibcon#about to write, iclass 14, count 2 2006.257.08:43:24.29#ibcon#wrote, iclass 14, count 2 2006.257.08:43:24.29#ibcon#about to read 3, iclass 14, count 2 2006.257.08:43:24.32#ibcon#read 3, iclass 14, count 2 2006.257.08:43:24.32#ibcon#about to read 4, iclass 14, count 2 2006.257.08:43:24.32#ibcon#read 4, iclass 14, count 2 2006.257.08:43:24.32#ibcon#about to read 5, iclass 14, count 2 2006.257.08:43:24.32#ibcon#read 5, iclass 14, count 2 2006.257.08:43:24.32#ibcon#about to read 6, iclass 14, count 2 2006.257.08:43:24.32#ibcon#read 6, iclass 14, count 2 2006.257.08:43:24.32#ibcon#end of sib2, iclass 14, count 2 2006.257.08:43:24.32#ibcon#*after write, iclass 14, count 2 2006.257.08:43:24.32#ibcon#*before return 0, iclass 14, count 2 2006.257.08:43:24.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:24.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:24.32#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.08:43:24.32#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:24.32#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:24.44#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:24.44#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:24.44#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:43:24.44#ibcon#first serial, iclass 14, count 0 2006.257.08:43:24.44#ibcon#enter sib2, iclass 14, count 0 2006.257.08:43:24.44#ibcon#flushed, iclass 14, count 0 2006.257.08:43:24.44#ibcon#about to write, iclass 14, count 0 2006.257.08:43:24.44#ibcon#wrote, iclass 14, count 0 2006.257.08:43:24.44#ibcon#about to read 3, iclass 14, count 0 2006.257.08:43:24.46#ibcon#read 3, iclass 14, count 0 2006.257.08:43:24.46#ibcon#about to read 4, iclass 14, count 0 2006.257.08:43:24.46#ibcon#read 4, iclass 14, count 0 2006.257.08:43:24.46#ibcon#about to read 5, iclass 14, count 0 2006.257.08:43:24.46#ibcon#read 5, iclass 14, count 0 2006.257.08:43:24.46#ibcon#about to read 6, iclass 14, count 0 2006.257.08:43:24.46#ibcon#read 6, iclass 14, count 0 2006.257.08:43:24.46#ibcon#end of sib2, iclass 14, count 0 2006.257.08:43:24.46#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:43:24.46#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:43:24.46#ibcon#[25=USB\r\n] 2006.257.08:43:24.46#ibcon#*before write, iclass 14, count 0 2006.257.08:43:24.46#ibcon#enter sib2, iclass 14, count 0 2006.257.08:43:24.46#ibcon#flushed, iclass 14, count 0 2006.257.08:43:24.46#ibcon#about to write, iclass 14, count 0 2006.257.08:43:24.46#ibcon#wrote, iclass 14, count 0 2006.257.08:43:24.46#ibcon#about to read 3, iclass 14, count 0 2006.257.08:43:24.49#ibcon#read 3, iclass 14, count 0 2006.257.08:43:24.49#ibcon#about to read 4, iclass 14, count 0 2006.257.08:43:24.49#ibcon#read 4, iclass 14, count 0 2006.257.08:43:24.49#ibcon#about to read 5, iclass 14, count 0 2006.257.08:43:24.49#ibcon#read 5, iclass 14, count 0 2006.257.08:43:24.49#ibcon#about to read 6, iclass 14, count 0 2006.257.08:43:24.49#ibcon#read 6, iclass 14, count 0 2006.257.08:43:24.49#ibcon#end of sib2, iclass 14, count 0 2006.257.08:43:24.49#ibcon#*after write, iclass 14, count 0 2006.257.08:43:24.49#ibcon#*before return 0, iclass 14, count 0 2006.257.08:43:24.49#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:24.49#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:24.49#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:43:24.49#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:43:24.49$vck44/valo=2,534.99 2006.257.08:43:24.49#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.08:43:24.49#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.08:43:24.49#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:24.49#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:24.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:24.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:24.49#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:43:24.49#ibcon#first serial, iclass 16, count 0 2006.257.08:43:24.49#ibcon#enter sib2, iclass 16, count 0 2006.257.08:43:24.49#ibcon#flushed, iclass 16, count 0 2006.257.08:43:24.49#ibcon#about to write, iclass 16, count 0 2006.257.08:43:24.49#ibcon#wrote, iclass 16, count 0 2006.257.08:43:24.49#ibcon#about to read 3, iclass 16, count 0 2006.257.08:43:24.51#ibcon#read 3, iclass 16, count 0 2006.257.08:43:24.51#ibcon#about to read 4, iclass 16, count 0 2006.257.08:43:24.51#ibcon#read 4, iclass 16, count 0 2006.257.08:43:24.51#ibcon#about to read 5, iclass 16, count 0 2006.257.08:43:24.51#ibcon#read 5, iclass 16, count 0 2006.257.08:43:24.51#ibcon#about to read 6, iclass 16, count 0 2006.257.08:43:24.51#ibcon#read 6, iclass 16, count 0 2006.257.08:43:24.51#ibcon#end of sib2, iclass 16, count 0 2006.257.08:43:24.51#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:43:24.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:43:24.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:43:24.51#ibcon#*before write, iclass 16, count 0 2006.257.08:43:24.51#ibcon#enter sib2, iclass 16, count 0 2006.257.08:43:24.51#ibcon#flushed, iclass 16, count 0 2006.257.08:43:24.51#ibcon#about to write, iclass 16, count 0 2006.257.08:43:24.51#ibcon#wrote, iclass 16, count 0 2006.257.08:43:24.51#ibcon#about to read 3, iclass 16, count 0 2006.257.08:43:24.55#ibcon#read 3, iclass 16, count 0 2006.257.08:43:24.55#ibcon#about to read 4, iclass 16, count 0 2006.257.08:43:24.55#ibcon#read 4, iclass 16, count 0 2006.257.08:43:24.55#ibcon#about to read 5, iclass 16, count 0 2006.257.08:43:24.55#ibcon#read 5, iclass 16, count 0 2006.257.08:43:24.55#ibcon#about to read 6, iclass 16, count 0 2006.257.08:43:24.55#ibcon#read 6, iclass 16, count 0 2006.257.08:43:24.55#ibcon#end of sib2, iclass 16, count 0 2006.257.08:43:24.55#ibcon#*after write, iclass 16, count 0 2006.257.08:43:24.55#ibcon#*before return 0, iclass 16, count 0 2006.257.08:43:24.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:24.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:24.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:43:24.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:43:24.55$vck44/va=2,7 2006.257.08:43:24.55#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.08:43:24.55#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.08:43:24.55#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:24.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:24.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:24.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:24.61#ibcon#enter wrdev, iclass 18, count 2 2006.257.08:43:24.61#ibcon#first serial, iclass 18, count 2 2006.257.08:43:24.61#ibcon#enter sib2, iclass 18, count 2 2006.257.08:43:24.61#ibcon#flushed, iclass 18, count 2 2006.257.08:43:24.61#ibcon#about to write, iclass 18, count 2 2006.257.08:43:24.61#ibcon#wrote, iclass 18, count 2 2006.257.08:43:24.61#ibcon#about to read 3, iclass 18, count 2 2006.257.08:43:24.63#ibcon#read 3, iclass 18, count 2 2006.257.08:43:24.63#ibcon#about to read 4, iclass 18, count 2 2006.257.08:43:24.63#ibcon#read 4, iclass 18, count 2 2006.257.08:43:24.63#ibcon#about to read 5, iclass 18, count 2 2006.257.08:43:24.63#ibcon#read 5, iclass 18, count 2 2006.257.08:43:24.63#ibcon#about to read 6, iclass 18, count 2 2006.257.08:43:24.63#ibcon#read 6, iclass 18, count 2 2006.257.08:43:24.63#ibcon#end of sib2, iclass 18, count 2 2006.257.08:43:24.63#ibcon#*mode == 0, iclass 18, count 2 2006.257.08:43:24.63#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.08:43:24.63#ibcon#[25=AT02-07\r\n] 2006.257.08:43:24.63#ibcon#*before write, iclass 18, count 2 2006.257.08:43:24.63#ibcon#enter sib2, iclass 18, count 2 2006.257.08:43:24.63#ibcon#flushed, iclass 18, count 2 2006.257.08:43:24.63#ibcon#about to write, iclass 18, count 2 2006.257.08:43:24.63#ibcon#wrote, iclass 18, count 2 2006.257.08:43:24.63#ibcon#about to read 3, iclass 18, count 2 2006.257.08:43:24.66#ibcon#read 3, iclass 18, count 2 2006.257.08:43:24.66#ibcon#about to read 4, iclass 18, count 2 2006.257.08:43:24.66#ibcon#read 4, iclass 18, count 2 2006.257.08:43:24.66#ibcon#about to read 5, iclass 18, count 2 2006.257.08:43:24.66#ibcon#read 5, iclass 18, count 2 2006.257.08:43:24.66#ibcon#about to read 6, iclass 18, count 2 2006.257.08:43:24.66#ibcon#read 6, iclass 18, count 2 2006.257.08:43:24.66#ibcon#end of sib2, iclass 18, count 2 2006.257.08:43:24.66#ibcon#*after write, iclass 18, count 2 2006.257.08:43:24.66#ibcon#*before return 0, iclass 18, count 2 2006.257.08:43:24.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:24.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:24.66#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.08:43:24.66#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:24.66#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:24.78#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:24.78#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:24.78#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:43:24.78#ibcon#first serial, iclass 18, count 0 2006.257.08:43:24.78#ibcon#enter sib2, iclass 18, count 0 2006.257.08:43:24.78#ibcon#flushed, iclass 18, count 0 2006.257.08:43:24.78#ibcon#about to write, iclass 18, count 0 2006.257.08:43:24.78#ibcon#wrote, iclass 18, count 0 2006.257.08:43:24.78#ibcon#about to read 3, iclass 18, count 0 2006.257.08:43:24.80#ibcon#read 3, iclass 18, count 0 2006.257.08:43:24.80#ibcon#about to read 4, iclass 18, count 0 2006.257.08:43:24.80#ibcon#read 4, iclass 18, count 0 2006.257.08:43:24.80#ibcon#about to read 5, iclass 18, count 0 2006.257.08:43:24.80#ibcon#read 5, iclass 18, count 0 2006.257.08:43:24.80#ibcon#about to read 6, iclass 18, count 0 2006.257.08:43:24.80#ibcon#read 6, iclass 18, count 0 2006.257.08:43:24.80#ibcon#end of sib2, iclass 18, count 0 2006.257.08:43:24.80#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:43:24.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:43:24.80#ibcon#[25=USB\r\n] 2006.257.08:43:24.80#ibcon#*before write, iclass 18, count 0 2006.257.08:43:24.80#ibcon#enter sib2, iclass 18, count 0 2006.257.08:43:24.80#ibcon#flushed, iclass 18, count 0 2006.257.08:43:24.80#ibcon#about to write, iclass 18, count 0 2006.257.08:43:24.80#ibcon#wrote, iclass 18, count 0 2006.257.08:43:24.80#ibcon#about to read 3, iclass 18, count 0 2006.257.08:43:24.83#ibcon#read 3, iclass 18, count 0 2006.257.08:43:24.83#ibcon#about to read 4, iclass 18, count 0 2006.257.08:43:24.83#ibcon#read 4, iclass 18, count 0 2006.257.08:43:24.83#ibcon#about to read 5, iclass 18, count 0 2006.257.08:43:24.83#ibcon#read 5, iclass 18, count 0 2006.257.08:43:24.83#ibcon#about to read 6, iclass 18, count 0 2006.257.08:43:24.83#ibcon#read 6, iclass 18, count 0 2006.257.08:43:24.83#ibcon#end of sib2, iclass 18, count 0 2006.257.08:43:24.83#ibcon#*after write, iclass 18, count 0 2006.257.08:43:24.83#ibcon#*before return 0, iclass 18, count 0 2006.257.08:43:24.83#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:24.83#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:24.83#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:43:24.83#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:43:24.83$vck44/valo=3,564.99 2006.257.08:43:24.83#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.08:43:24.83#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.08:43:24.83#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:24.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:24.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:24.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:24.83#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:43:24.83#ibcon#first serial, iclass 20, count 0 2006.257.08:43:24.83#ibcon#enter sib2, iclass 20, count 0 2006.257.08:43:24.83#ibcon#flushed, iclass 20, count 0 2006.257.08:43:24.83#ibcon#about to write, iclass 20, count 0 2006.257.08:43:24.83#ibcon#wrote, iclass 20, count 0 2006.257.08:43:24.83#ibcon#about to read 3, iclass 20, count 0 2006.257.08:43:24.85#ibcon#read 3, iclass 20, count 0 2006.257.08:43:24.85#ibcon#about to read 4, iclass 20, count 0 2006.257.08:43:24.85#ibcon#read 4, iclass 20, count 0 2006.257.08:43:24.85#ibcon#about to read 5, iclass 20, count 0 2006.257.08:43:24.85#ibcon#read 5, iclass 20, count 0 2006.257.08:43:24.85#ibcon#about to read 6, iclass 20, count 0 2006.257.08:43:24.85#ibcon#read 6, iclass 20, count 0 2006.257.08:43:24.85#ibcon#end of sib2, iclass 20, count 0 2006.257.08:43:24.85#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:43:24.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:43:24.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:43:24.85#ibcon#*before write, iclass 20, count 0 2006.257.08:43:24.85#ibcon#enter sib2, iclass 20, count 0 2006.257.08:43:24.85#ibcon#flushed, iclass 20, count 0 2006.257.08:43:24.85#ibcon#about to write, iclass 20, count 0 2006.257.08:43:24.85#ibcon#wrote, iclass 20, count 0 2006.257.08:43:24.85#ibcon#about to read 3, iclass 20, count 0 2006.257.08:43:24.89#ibcon#read 3, iclass 20, count 0 2006.257.08:43:24.89#ibcon#about to read 4, iclass 20, count 0 2006.257.08:43:24.89#ibcon#read 4, iclass 20, count 0 2006.257.08:43:24.89#ibcon#about to read 5, iclass 20, count 0 2006.257.08:43:24.89#ibcon#read 5, iclass 20, count 0 2006.257.08:43:24.89#ibcon#about to read 6, iclass 20, count 0 2006.257.08:43:24.89#ibcon#read 6, iclass 20, count 0 2006.257.08:43:24.89#ibcon#end of sib2, iclass 20, count 0 2006.257.08:43:24.89#ibcon#*after write, iclass 20, count 0 2006.257.08:43:24.89#ibcon#*before return 0, iclass 20, count 0 2006.257.08:43:24.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:24.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:24.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:43:24.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:43:24.89$vck44/va=3,8 2006.257.08:43:24.89#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.08:43:24.89#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.08:43:24.89#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:24.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:24.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:24.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:24.95#ibcon#enter wrdev, iclass 22, count 2 2006.257.08:43:24.95#ibcon#first serial, iclass 22, count 2 2006.257.08:43:24.95#ibcon#enter sib2, iclass 22, count 2 2006.257.08:43:24.95#ibcon#flushed, iclass 22, count 2 2006.257.08:43:24.95#ibcon#about to write, iclass 22, count 2 2006.257.08:43:24.95#ibcon#wrote, iclass 22, count 2 2006.257.08:43:24.95#ibcon#about to read 3, iclass 22, count 2 2006.257.08:43:24.97#ibcon#read 3, iclass 22, count 2 2006.257.08:43:24.97#ibcon#about to read 4, iclass 22, count 2 2006.257.08:43:24.97#ibcon#read 4, iclass 22, count 2 2006.257.08:43:24.97#ibcon#about to read 5, iclass 22, count 2 2006.257.08:43:24.97#ibcon#read 5, iclass 22, count 2 2006.257.08:43:24.97#ibcon#about to read 6, iclass 22, count 2 2006.257.08:43:24.97#ibcon#read 6, iclass 22, count 2 2006.257.08:43:24.97#ibcon#end of sib2, iclass 22, count 2 2006.257.08:43:24.97#ibcon#*mode == 0, iclass 22, count 2 2006.257.08:43:24.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.08:43:24.97#ibcon#[25=AT03-08\r\n] 2006.257.08:43:24.97#ibcon#*before write, iclass 22, count 2 2006.257.08:43:24.97#ibcon#enter sib2, iclass 22, count 2 2006.257.08:43:24.97#ibcon#flushed, iclass 22, count 2 2006.257.08:43:24.97#ibcon#about to write, iclass 22, count 2 2006.257.08:43:24.97#ibcon#wrote, iclass 22, count 2 2006.257.08:43:24.97#ibcon#about to read 3, iclass 22, count 2 2006.257.08:43:25.00#ibcon#read 3, iclass 22, count 2 2006.257.08:43:25.00#ibcon#about to read 4, iclass 22, count 2 2006.257.08:43:25.00#ibcon#read 4, iclass 22, count 2 2006.257.08:43:25.00#ibcon#about to read 5, iclass 22, count 2 2006.257.08:43:25.00#ibcon#read 5, iclass 22, count 2 2006.257.08:43:25.00#ibcon#about to read 6, iclass 22, count 2 2006.257.08:43:25.00#ibcon#read 6, iclass 22, count 2 2006.257.08:43:25.00#ibcon#end of sib2, iclass 22, count 2 2006.257.08:43:25.00#ibcon#*after write, iclass 22, count 2 2006.257.08:43:25.00#ibcon#*before return 0, iclass 22, count 2 2006.257.08:43:25.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:25.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:25.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.08:43:25.00#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:25.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:25.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:25.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:25.12#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:43:25.12#ibcon#first serial, iclass 22, count 0 2006.257.08:43:25.12#ibcon#enter sib2, iclass 22, count 0 2006.257.08:43:25.12#ibcon#flushed, iclass 22, count 0 2006.257.08:43:25.12#ibcon#about to write, iclass 22, count 0 2006.257.08:43:25.12#ibcon#wrote, iclass 22, count 0 2006.257.08:43:25.12#ibcon#about to read 3, iclass 22, count 0 2006.257.08:43:25.14#ibcon#read 3, iclass 22, count 0 2006.257.08:43:25.14#ibcon#about to read 4, iclass 22, count 0 2006.257.08:43:25.14#ibcon#read 4, iclass 22, count 0 2006.257.08:43:25.14#ibcon#about to read 5, iclass 22, count 0 2006.257.08:43:25.14#ibcon#read 5, iclass 22, count 0 2006.257.08:43:25.14#ibcon#about to read 6, iclass 22, count 0 2006.257.08:43:25.14#ibcon#read 6, iclass 22, count 0 2006.257.08:43:25.14#ibcon#end of sib2, iclass 22, count 0 2006.257.08:43:25.14#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:43:25.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:43:25.14#ibcon#[25=USB\r\n] 2006.257.08:43:25.14#ibcon#*before write, iclass 22, count 0 2006.257.08:43:25.14#ibcon#enter sib2, iclass 22, count 0 2006.257.08:43:25.14#ibcon#flushed, iclass 22, count 0 2006.257.08:43:25.14#ibcon#about to write, iclass 22, count 0 2006.257.08:43:25.14#ibcon#wrote, iclass 22, count 0 2006.257.08:43:25.14#ibcon#about to read 3, iclass 22, count 0 2006.257.08:43:25.17#ibcon#read 3, iclass 22, count 0 2006.257.08:43:25.17#ibcon#about to read 4, iclass 22, count 0 2006.257.08:43:25.17#ibcon#read 4, iclass 22, count 0 2006.257.08:43:25.17#ibcon#about to read 5, iclass 22, count 0 2006.257.08:43:25.17#ibcon#read 5, iclass 22, count 0 2006.257.08:43:25.17#ibcon#about to read 6, iclass 22, count 0 2006.257.08:43:25.17#ibcon#read 6, iclass 22, count 0 2006.257.08:43:25.17#ibcon#end of sib2, iclass 22, count 0 2006.257.08:43:25.17#ibcon#*after write, iclass 22, count 0 2006.257.08:43:25.17#ibcon#*before return 0, iclass 22, count 0 2006.257.08:43:25.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:25.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:25.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:43:25.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:43:25.17$vck44/valo=4,624.99 2006.257.08:43:25.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.08:43:25.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.08:43:25.17#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:25.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:25.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:25.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:25.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:43:25.17#ibcon#first serial, iclass 24, count 0 2006.257.08:43:25.17#ibcon#enter sib2, iclass 24, count 0 2006.257.08:43:25.17#ibcon#flushed, iclass 24, count 0 2006.257.08:43:25.17#ibcon#about to write, iclass 24, count 0 2006.257.08:43:25.17#ibcon#wrote, iclass 24, count 0 2006.257.08:43:25.17#ibcon#about to read 3, iclass 24, count 0 2006.257.08:43:25.19#ibcon#read 3, iclass 24, count 0 2006.257.08:43:25.19#ibcon#about to read 4, iclass 24, count 0 2006.257.08:43:25.19#ibcon#read 4, iclass 24, count 0 2006.257.08:43:25.19#ibcon#about to read 5, iclass 24, count 0 2006.257.08:43:25.19#ibcon#read 5, iclass 24, count 0 2006.257.08:43:25.19#ibcon#about to read 6, iclass 24, count 0 2006.257.08:43:25.19#ibcon#read 6, iclass 24, count 0 2006.257.08:43:25.19#ibcon#end of sib2, iclass 24, count 0 2006.257.08:43:25.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:43:25.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:43:25.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:43:25.19#ibcon#*before write, iclass 24, count 0 2006.257.08:43:25.19#ibcon#enter sib2, iclass 24, count 0 2006.257.08:43:25.19#ibcon#flushed, iclass 24, count 0 2006.257.08:43:25.19#ibcon#about to write, iclass 24, count 0 2006.257.08:43:25.19#ibcon#wrote, iclass 24, count 0 2006.257.08:43:25.19#ibcon#about to read 3, iclass 24, count 0 2006.257.08:43:25.23#ibcon#read 3, iclass 24, count 0 2006.257.08:43:25.23#ibcon#about to read 4, iclass 24, count 0 2006.257.08:43:25.23#ibcon#read 4, iclass 24, count 0 2006.257.08:43:25.23#ibcon#about to read 5, iclass 24, count 0 2006.257.08:43:25.23#ibcon#read 5, iclass 24, count 0 2006.257.08:43:25.23#ibcon#about to read 6, iclass 24, count 0 2006.257.08:43:25.23#ibcon#read 6, iclass 24, count 0 2006.257.08:43:25.23#ibcon#end of sib2, iclass 24, count 0 2006.257.08:43:25.23#ibcon#*after write, iclass 24, count 0 2006.257.08:43:25.23#ibcon#*before return 0, iclass 24, count 0 2006.257.08:43:25.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:25.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:25.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:43:25.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:43:25.23$vck44/va=4,7 2006.257.08:43:25.23#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.08:43:25.23#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.08:43:25.23#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:25.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:25.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:25.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:25.29#ibcon#enter wrdev, iclass 26, count 2 2006.257.08:43:25.29#ibcon#first serial, iclass 26, count 2 2006.257.08:43:25.29#ibcon#enter sib2, iclass 26, count 2 2006.257.08:43:25.29#ibcon#flushed, iclass 26, count 2 2006.257.08:43:25.29#ibcon#about to write, iclass 26, count 2 2006.257.08:43:25.29#ibcon#wrote, iclass 26, count 2 2006.257.08:43:25.29#ibcon#about to read 3, iclass 26, count 2 2006.257.08:43:25.31#ibcon#read 3, iclass 26, count 2 2006.257.08:43:25.31#ibcon#about to read 4, iclass 26, count 2 2006.257.08:43:25.31#ibcon#read 4, iclass 26, count 2 2006.257.08:43:25.31#ibcon#about to read 5, iclass 26, count 2 2006.257.08:43:25.31#ibcon#read 5, iclass 26, count 2 2006.257.08:43:25.31#ibcon#about to read 6, iclass 26, count 2 2006.257.08:43:25.31#ibcon#read 6, iclass 26, count 2 2006.257.08:43:25.31#ibcon#end of sib2, iclass 26, count 2 2006.257.08:43:25.31#ibcon#*mode == 0, iclass 26, count 2 2006.257.08:43:25.31#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.08:43:25.31#ibcon#[25=AT04-07\r\n] 2006.257.08:43:25.31#ibcon#*before write, iclass 26, count 2 2006.257.08:43:25.31#ibcon#enter sib2, iclass 26, count 2 2006.257.08:43:25.31#ibcon#flushed, iclass 26, count 2 2006.257.08:43:25.31#ibcon#about to write, iclass 26, count 2 2006.257.08:43:25.31#ibcon#wrote, iclass 26, count 2 2006.257.08:43:25.31#ibcon#about to read 3, iclass 26, count 2 2006.257.08:43:25.34#ibcon#read 3, iclass 26, count 2 2006.257.08:43:25.34#ibcon#about to read 4, iclass 26, count 2 2006.257.08:43:25.34#ibcon#read 4, iclass 26, count 2 2006.257.08:43:25.34#ibcon#about to read 5, iclass 26, count 2 2006.257.08:43:25.34#ibcon#read 5, iclass 26, count 2 2006.257.08:43:25.34#ibcon#about to read 6, iclass 26, count 2 2006.257.08:43:25.34#ibcon#read 6, iclass 26, count 2 2006.257.08:43:25.34#ibcon#end of sib2, iclass 26, count 2 2006.257.08:43:25.34#ibcon#*after write, iclass 26, count 2 2006.257.08:43:25.34#ibcon#*before return 0, iclass 26, count 2 2006.257.08:43:25.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:25.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:25.34#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.08:43:25.34#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:25.34#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:25.46#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:25.46#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:25.46#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:43:25.46#ibcon#first serial, iclass 26, count 0 2006.257.08:43:25.46#ibcon#enter sib2, iclass 26, count 0 2006.257.08:43:25.46#ibcon#flushed, iclass 26, count 0 2006.257.08:43:25.46#ibcon#about to write, iclass 26, count 0 2006.257.08:43:25.46#ibcon#wrote, iclass 26, count 0 2006.257.08:43:25.46#ibcon#about to read 3, iclass 26, count 0 2006.257.08:43:25.48#ibcon#read 3, iclass 26, count 0 2006.257.08:43:25.48#ibcon#about to read 4, iclass 26, count 0 2006.257.08:43:25.48#ibcon#read 4, iclass 26, count 0 2006.257.08:43:25.48#ibcon#about to read 5, iclass 26, count 0 2006.257.08:43:25.48#ibcon#read 5, iclass 26, count 0 2006.257.08:43:25.48#ibcon#about to read 6, iclass 26, count 0 2006.257.08:43:25.48#ibcon#read 6, iclass 26, count 0 2006.257.08:43:25.48#ibcon#end of sib2, iclass 26, count 0 2006.257.08:43:25.48#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:43:25.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:43:25.48#ibcon#[25=USB\r\n] 2006.257.08:43:25.48#ibcon#*before write, iclass 26, count 0 2006.257.08:43:25.48#ibcon#enter sib2, iclass 26, count 0 2006.257.08:43:25.48#ibcon#flushed, iclass 26, count 0 2006.257.08:43:25.48#ibcon#about to write, iclass 26, count 0 2006.257.08:43:25.48#ibcon#wrote, iclass 26, count 0 2006.257.08:43:25.48#ibcon#about to read 3, iclass 26, count 0 2006.257.08:43:25.51#ibcon#read 3, iclass 26, count 0 2006.257.08:43:25.51#ibcon#about to read 4, iclass 26, count 0 2006.257.08:43:25.51#ibcon#read 4, iclass 26, count 0 2006.257.08:43:25.51#ibcon#about to read 5, iclass 26, count 0 2006.257.08:43:25.51#ibcon#read 5, iclass 26, count 0 2006.257.08:43:25.51#ibcon#about to read 6, iclass 26, count 0 2006.257.08:43:25.51#ibcon#read 6, iclass 26, count 0 2006.257.08:43:25.51#ibcon#end of sib2, iclass 26, count 0 2006.257.08:43:25.51#ibcon#*after write, iclass 26, count 0 2006.257.08:43:25.51#ibcon#*before return 0, iclass 26, count 0 2006.257.08:43:25.51#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:25.51#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:25.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:43:25.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:43:25.51$vck44/valo=5,734.99 2006.257.08:43:25.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.08:43:25.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.08:43:25.51#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:25.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:25.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:25.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:25.51#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:43:25.51#ibcon#first serial, iclass 28, count 0 2006.257.08:43:25.51#ibcon#enter sib2, iclass 28, count 0 2006.257.08:43:25.51#ibcon#flushed, iclass 28, count 0 2006.257.08:43:25.51#ibcon#about to write, iclass 28, count 0 2006.257.08:43:25.51#ibcon#wrote, iclass 28, count 0 2006.257.08:43:25.51#ibcon#about to read 3, iclass 28, count 0 2006.257.08:43:25.53#ibcon#read 3, iclass 28, count 0 2006.257.08:43:25.53#ibcon#about to read 4, iclass 28, count 0 2006.257.08:43:25.53#ibcon#read 4, iclass 28, count 0 2006.257.08:43:25.53#ibcon#about to read 5, iclass 28, count 0 2006.257.08:43:25.53#ibcon#read 5, iclass 28, count 0 2006.257.08:43:25.53#ibcon#about to read 6, iclass 28, count 0 2006.257.08:43:25.53#ibcon#read 6, iclass 28, count 0 2006.257.08:43:25.53#ibcon#end of sib2, iclass 28, count 0 2006.257.08:43:25.53#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:43:25.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:43:25.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:43:25.53#ibcon#*before write, iclass 28, count 0 2006.257.08:43:25.53#ibcon#enter sib2, iclass 28, count 0 2006.257.08:43:25.53#ibcon#flushed, iclass 28, count 0 2006.257.08:43:25.53#ibcon#about to write, iclass 28, count 0 2006.257.08:43:25.53#ibcon#wrote, iclass 28, count 0 2006.257.08:43:25.53#ibcon#about to read 3, iclass 28, count 0 2006.257.08:43:25.57#ibcon#read 3, iclass 28, count 0 2006.257.08:43:25.57#ibcon#about to read 4, iclass 28, count 0 2006.257.08:43:25.57#ibcon#read 4, iclass 28, count 0 2006.257.08:43:25.57#ibcon#about to read 5, iclass 28, count 0 2006.257.08:43:25.57#ibcon#read 5, iclass 28, count 0 2006.257.08:43:25.57#ibcon#about to read 6, iclass 28, count 0 2006.257.08:43:25.57#ibcon#read 6, iclass 28, count 0 2006.257.08:43:25.57#ibcon#end of sib2, iclass 28, count 0 2006.257.08:43:25.57#ibcon#*after write, iclass 28, count 0 2006.257.08:43:25.57#ibcon#*before return 0, iclass 28, count 0 2006.257.08:43:25.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:25.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:25.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:43:25.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:43:25.57$vck44/va=5,4 2006.257.08:43:25.57#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.08:43:25.57#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.08:43:25.57#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:25.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:25.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:25.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:25.63#ibcon#enter wrdev, iclass 30, count 2 2006.257.08:43:25.63#ibcon#first serial, iclass 30, count 2 2006.257.08:43:25.63#ibcon#enter sib2, iclass 30, count 2 2006.257.08:43:25.63#ibcon#flushed, iclass 30, count 2 2006.257.08:43:25.63#ibcon#about to write, iclass 30, count 2 2006.257.08:43:25.63#ibcon#wrote, iclass 30, count 2 2006.257.08:43:25.63#ibcon#about to read 3, iclass 30, count 2 2006.257.08:43:25.65#ibcon#read 3, iclass 30, count 2 2006.257.08:43:25.65#ibcon#about to read 4, iclass 30, count 2 2006.257.08:43:25.65#ibcon#read 4, iclass 30, count 2 2006.257.08:43:25.65#ibcon#about to read 5, iclass 30, count 2 2006.257.08:43:25.65#ibcon#read 5, iclass 30, count 2 2006.257.08:43:25.65#ibcon#about to read 6, iclass 30, count 2 2006.257.08:43:25.65#ibcon#read 6, iclass 30, count 2 2006.257.08:43:25.65#ibcon#end of sib2, iclass 30, count 2 2006.257.08:43:25.65#ibcon#*mode == 0, iclass 30, count 2 2006.257.08:43:25.65#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.08:43:25.65#ibcon#[25=AT05-04\r\n] 2006.257.08:43:25.65#ibcon#*before write, iclass 30, count 2 2006.257.08:43:25.65#ibcon#enter sib2, iclass 30, count 2 2006.257.08:43:25.65#ibcon#flushed, iclass 30, count 2 2006.257.08:43:25.65#ibcon#about to write, iclass 30, count 2 2006.257.08:43:25.65#ibcon#wrote, iclass 30, count 2 2006.257.08:43:25.65#ibcon#about to read 3, iclass 30, count 2 2006.257.08:43:25.68#ibcon#read 3, iclass 30, count 2 2006.257.08:43:25.68#ibcon#about to read 4, iclass 30, count 2 2006.257.08:43:25.68#ibcon#read 4, iclass 30, count 2 2006.257.08:43:25.68#ibcon#about to read 5, iclass 30, count 2 2006.257.08:43:25.68#ibcon#read 5, iclass 30, count 2 2006.257.08:43:25.68#ibcon#about to read 6, iclass 30, count 2 2006.257.08:43:25.68#ibcon#read 6, iclass 30, count 2 2006.257.08:43:25.68#ibcon#end of sib2, iclass 30, count 2 2006.257.08:43:25.68#ibcon#*after write, iclass 30, count 2 2006.257.08:43:25.68#ibcon#*before return 0, iclass 30, count 2 2006.257.08:43:25.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:25.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:25.68#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.08:43:25.68#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:25.68#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:25.80#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:25.80#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:25.80#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:43:25.80#ibcon#first serial, iclass 30, count 0 2006.257.08:43:25.80#ibcon#enter sib2, iclass 30, count 0 2006.257.08:43:25.80#ibcon#flushed, iclass 30, count 0 2006.257.08:43:25.80#ibcon#about to write, iclass 30, count 0 2006.257.08:43:25.80#ibcon#wrote, iclass 30, count 0 2006.257.08:43:25.80#ibcon#about to read 3, iclass 30, count 0 2006.257.08:43:25.82#ibcon#read 3, iclass 30, count 0 2006.257.08:43:25.82#ibcon#about to read 4, iclass 30, count 0 2006.257.08:43:25.82#ibcon#read 4, iclass 30, count 0 2006.257.08:43:25.82#ibcon#about to read 5, iclass 30, count 0 2006.257.08:43:25.82#ibcon#read 5, iclass 30, count 0 2006.257.08:43:25.82#ibcon#about to read 6, iclass 30, count 0 2006.257.08:43:25.82#ibcon#read 6, iclass 30, count 0 2006.257.08:43:25.82#ibcon#end of sib2, iclass 30, count 0 2006.257.08:43:25.82#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:43:25.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:43:25.82#ibcon#[25=USB\r\n] 2006.257.08:43:25.82#ibcon#*before write, iclass 30, count 0 2006.257.08:43:25.82#ibcon#enter sib2, iclass 30, count 0 2006.257.08:43:25.82#ibcon#flushed, iclass 30, count 0 2006.257.08:43:25.82#ibcon#about to write, iclass 30, count 0 2006.257.08:43:25.82#ibcon#wrote, iclass 30, count 0 2006.257.08:43:25.82#ibcon#about to read 3, iclass 30, count 0 2006.257.08:43:25.85#ibcon#read 3, iclass 30, count 0 2006.257.08:43:25.85#ibcon#about to read 4, iclass 30, count 0 2006.257.08:43:25.85#ibcon#read 4, iclass 30, count 0 2006.257.08:43:25.85#ibcon#about to read 5, iclass 30, count 0 2006.257.08:43:25.85#ibcon#read 5, iclass 30, count 0 2006.257.08:43:25.85#ibcon#about to read 6, iclass 30, count 0 2006.257.08:43:25.85#ibcon#read 6, iclass 30, count 0 2006.257.08:43:25.85#ibcon#end of sib2, iclass 30, count 0 2006.257.08:43:25.85#ibcon#*after write, iclass 30, count 0 2006.257.08:43:25.85#ibcon#*before return 0, iclass 30, count 0 2006.257.08:43:25.85#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:25.85#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:25.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:43:25.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:43:25.85$vck44/valo=6,814.99 2006.257.08:43:25.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.08:43:25.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.08:43:25.85#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:25.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:25.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:25.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:25.85#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:43:25.85#ibcon#first serial, iclass 32, count 0 2006.257.08:43:25.85#ibcon#enter sib2, iclass 32, count 0 2006.257.08:43:25.85#ibcon#flushed, iclass 32, count 0 2006.257.08:43:25.85#ibcon#about to write, iclass 32, count 0 2006.257.08:43:25.85#ibcon#wrote, iclass 32, count 0 2006.257.08:43:25.85#ibcon#about to read 3, iclass 32, count 0 2006.257.08:43:25.87#ibcon#read 3, iclass 32, count 0 2006.257.08:43:25.87#ibcon#about to read 4, iclass 32, count 0 2006.257.08:43:25.87#ibcon#read 4, iclass 32, count 0 2006.257.08:43:25.87#ibcon#about to read 5, iclass 32, count 0 2006.257.08:43:25.87#ibcon#read 5, iclass 32, count 0 2006.257.08:43:25.87#ibcon#about to read 6, iclass 32, count 0 2006.257.08:43:25.87#ibcon#read 6, iclass 32, count 0 2006.257.08:43:25.87#ibcon#end of sib2, iclass 32, count 0 2006.257.08:43:25.87#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:43:25.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:43:25.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:43:25.87#ibcon#*before write, iclass 32, count 0 2006.257.08:43:25.87#ibcon#enter sib2, iclass 32, count 0 2006.257.08:43:25.87#ibcon#flushed, iclass 32, count 0 2006.257.08:43:25.87#ibcon#about to write, iclass 32, count 0 2006.257.08:43:25.87#ibcon#wrote, iclass 32, count 0 2006.257.08:43:25.87#ibcon#about to read 3, iclass 32, count 0 2006.257.08:43:25.91#ibcon#read 3, iclass 32, count 0 2006.257.08:43:25.91#ibcon#about to read 4, iclass 32, count 0 2006.257.08:43:25.91#ibcon#read 4, iclass 32, count 0 2006.257.08:43:25.91#ibcon#about to read 5, iclass 32, count 0 2006.257.08:43:25.91#ibcon#read 5, iclass 32, count 0 2006.257.08:43:25.91#ibcon#about to read 6, iclass 32, count 0 2006.257.08:43:25.91#ibcon#read 6, iclass 32, count 0 2006.257.08:43:25.91#ibcon#end of sib2, iclass 32, count 0 2006.257.08:43:25.91#ibcon#*after write, iclass 32, count 0 2006.257.08:43:25.91#ibcon#*before return 0, iclass 32, count 0 2006.257.08:43:25.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:25.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:25.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:43:25.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:43:25.91$vck44/va=6,4 2006.257.08:43:25.91#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.08:43:25.91#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.08:43:25.91#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:25.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:25.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:25.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:25.97#ibcon#enter wrdev, iclass 34, count 2 2006.257.08:43:25.97#ibcon#first serial, iclass 34, count 2 2006.257.08:43:25.97#ibcon#enter sib2, iclass 34, count 2 2006.257.08:43:25.97#ibcon#flushed, iclass 34, count 2 2006.257.08:43:25.97#ibcon#about to write, iclass 34, count 2 2006.257.08:43:25.97#ibcon#wrote, iclass 34, count 2 2006.257.08:43:25.97#ibcon#about to read 3, iclass 34, count 2 2006.257.08:43:25.99#ibcon#read 3, iclass 34, count 2 2006.257.08:43:25.99#ibcon#about to read 4, iclass 34, count 2 2006.257.08:43:25.99#ibcon#read 4, iclass 34, count 2 2006.257.08:43:25.99#ibcon#about to read 5, iclass 34, count 2 2006.257.08:43:25.99#ibcon#read 5, iclass 34, count 2 2006.257.08:43:25.99#ibcon#about to read 6, iclass 34, count 2 2006.257.08:43:25.99#ibcon#read 6, iclass 34, count 2 2006.257.08:43:25.99#ibcon#end of sib2, iclass 34, count 2 2006.257.08:43:25.99#ibcon#*mode == 0, iclass 34, count 2 2006.257.08:43:25.99#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.08:43:25.99#ibcon#[25=AT06-04\r\n] 2006.257.08:43:25.99#ibcon#*before write, iclass 34, count 2 2006.257.08:43:25.99#ibcon#enter sib2, iclass 34, count 2 2006.257.08:43:25.99#ibcon#flushed, iclass 34, count 2 2006.257.08:43:25.99#ibcon#about to write, iclass 34, count 2 2006.257.08:43:25.99#ibcon#wrote, iclass 34, count 2 2006.257.08:43:25.99#ibcon#about to read 3, iclass 34, count 2 2006.257.08:43:26.02#ibcon#read 3, iclass 34, count 2 2006.257.08:43:26.02#ibcon#about to read 4, iclass 34, count 2 2006.257.08:43:26.02#ibcon#read 4, iclass 34, count 2 2006.257.08:43:26.02#ibcon#about to read 5, iclass 34, count 2 2006.257.08:43:26.02#ibcon#read 5, iclass 34, count 2 2006.257.08:43:26.02#ibcon#about to read 6, iclass 34, count 2 2006.257.08:43:26.02#ibcon#read 6, iclass 34, count 2 2006.257.08:43:26.02#ibcon#end of sib2, iclass 34, count 2 2006.257.08:43:26.02#ibcon#*after write, iclass 34, count 2 2006.257.08:43:26.02#ibcon#*before return 0, iclass 34, count 2 2006.257.08:43:26.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:26.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:26.02#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.08:43:26.02#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:26.02#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:26.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:26.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:26.14#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:43:26.14#ibcon#first serial, iclass 34, count 0 2006.257.08:43:26.14#ibcon#enter sib2, iclass 34, count 0 2006.257.08:43:26.14#ibcon#flushed, iclass 34, count 0 2006.257.08:43:26.14#ibcon#about to write, iclass 34, count 0 2006.257.08:43:26.14#ibcon#wrote, iclass 34, count 0 2006.257.08:43:26.14#ibcon#about to read 3, iclass 34, count 0 2006.257.08:43:26.16#ibcon#read 3, iclass 34, count 0 2006.257.08:43:26.16#ibcon#about to read 4, iclass 34, count 0 2006.257.08:43:26.16#ibcon#read 4, iclass 34, count 0 2006.257.08:43:26.16#ibcon#about to read 5, iclass 34, count 0 2006.257.08:43:26.16#ibcon#read 5, iclass 34, count 0 2006.257.08:43:26.16#ibcon#about to read 6, iclass 34, count 0 2006.257.08:43:26.16#ibcon#read 6, iclass 34, count 0 2006.257.08:43:26.16#ibcon#end of sib2, iclass 34, count 0 2006.257.08:43:26.16#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:43:26.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:43:26.16#ibcon#[25=USB\r\n] 2006.257.08:43:26.16#ibcon#*before write, iclass 34, count 0 2006.257.08:43:26.16#ibcon#enter sib2, iclass 34, count 0 2006.257.08:43:26.16#ibcon#flushed, iclass 34, count 0 2006.257.08:43:26.16#ibcon#about to write, iclass 34, count 0 2006.257.08:43:26.16#ibcon#wrote, iclass 34, count 0 2006.257.08:43:26.16#ibcon#about to read 3, iclass 34, count 0 2006.257.08:43:26.19#ibcon#read 3, iclass 34, count 0 2006.257.08:43:26.19#ibcon#about to read 4, iclass 34, count 0 2006.257.08:43:26.19#ibcon#read 4, iclass 34, count 0 2006.257.08:43:26.19#ibcon#about to read 5, iclass 34, count 0 2006.257.08:43:26.19#ibcon#read 5, iclass 34, count 0 2006.257.08:43:26.19#ibcon#about to read 6, iclass 34, count 0 2006.257.08:43:26.19#ibcon#read 6, iclass 34, count 0 2006.257.08:43:26.19#ibcon#end of sib2, iclass 34, count 0 2006.257.08:43:26.19#ibcon#*after write, iclass 34, count 0 2006.257.08:43:26.19#ibcon#*before return 0, iclass 34, count 0 2006.257.08:43:26.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:26.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:26.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:43:26.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:43:26.19$vck44/valo=7,864.99 2006.257.08:43:26.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.08:43:26.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.08:43:26.19#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:26.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:26.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:26.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:26.19#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:43:26.19#ibcon#first serial, iclass 36, count 0 2006.257.08:43:26.19#ibcon#enter sib2, iclass 36, count 0 2006.257.08:43:26.19#ibcon#flushed, iclass 36, count 0 2006.257.08:43:26.19#ibcon#about to write, iclass 36, count 0 2006.257.08:43:26.19#ibcon#wrote, iclass 36, count 0 2006.257.08:43:26.19#ibcon#about to read 3, iclass 36, count 0 2006.257.08:43:26.21#ibcon#read 3, iclass 36, count 0 2006.257.08:43:26.21#ibcon#about to read 4, iclass 36, count 0 2006.257.08:43:26.21#ibcon#read 4, iclass 36, count 0 2006.257.08:43:26.21#ibcon#about to read 5, iclass 36, count 0 2006.257.08:43:26.21#ibcon#read 5, iclass 36, count 0 2006.257.08:43:26.21#ibcon#about to read 6, iclass 36, count 0 2006.257.08:43:26.21#ibcon#read 6, iclass 36, count 0 2006.257.08:43:26.21#ibcon#end of sib2, iclass 36, count 0 2006.257.08:43:26.21#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:43:26.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:43:26.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:43:26.21#ibcon#*before write, iclass 36, count 0 2006.257.08:43:26.21#ibcon#enter sib2, iclass 36, count 0 2006.257.08:43:26.21#ibcon#flushed, iclass 36, count 0 2006.257.08:43:26.21#ibcon#about to write, iclass 36, count 0 2006.257.08:43:26.21#ibcon#wrote, iclass 36, count 0 2006.257.08:43:26.21#ibcon#about to read 3, iclass 36, count 0 2006.257.08:43:26.25#ibcon#read 3, iclass 36, count 0 2006.257.08:43:26.25#ibcon#about to read 4, iclass 36, count 0 2006.257.08:43:26.25#ibcon#read 4, iclass 36, count 0 2006.257.08:43:26.25#ibcon#about to read 5, iclass 36, count 0 2006.257.08:43:26.25#ibcon#read 5, iclass 36, count 0 2006.257.08:43:26.25#ibcon#about to read 6, iclass 36, count 0 2006.257.08:43:26.25#ibcon#read 6, iclass 36, count 0 2006.257.08:43:26.25#ibcon#end of sib2, iclass 36, count 0 2006.257.08:43:26.25#ibcon#*after write, iclass 36, count 0 2006.257.08:43:26.25#ibcon#*before return 0, iclass 36, count 0 2006.257.08:43:26.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:26.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:26.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:43:26.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:43:26.25$vck44/va=7,4 2006.257.08:43:26.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.08:43:26.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.08:43:26.25#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:26.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:26.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:26.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:26.31#ibcon#enter wrdev, iclass 38, count 2 2006.257.08:43:26.31#ibcon#first serial, iclass 38, count 2 2006.257.08:43:26.31#ibcon#enter sib2, iclass 38, count 2 2006.257.08:43:26.31#ibcon#flushed, iclass 38, count 2 2006.257.08:43:26.31#ibcon#about to write, iclass 38, count 2 2006.257.08:43:26.31#ibcon#wrote, iclass 38, count 2 2006.257.08:43:26.31#ibcon#about to read 3, iclass 38, count 2 2006.257.08:43:26.33#ibcon#read 3, iclass 38, count 2 2006.257.08:43:26.33#ibcon#about to read 4, iclass 38, count 2 2006.257.08:43:26.33#ibcon#read 4, iclass 38, count 2 2006.257.08:43:26.33#ibcon#about to read 5, iclass 38, count 2 2006.257.08:43:26.33#ibcon#read 5, iclass 38, count 2 2006.257.08:43:26.33#ibcon#about to read 6, iclass 38, count 2 2006.257.08:43:26.33#ibcon#read 6, iclass 38, count 2 2006.257.08:43:26.33#ibcon#end of sib2, iclass 38, count 2 2006.257.08:43:26.33#ibcon#*mode == 0, iclass 38, count 2 2006.257.08:43:26.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.08:43:26.33#ibcon#[25=AT07-04\r\n] 2006.257.08:43:26.33#ibcon#*before write, iclass 38, count 2 2006.257.08:43:26.33#ibcon#enter sib2, iclass 38, count 2 2006.257.08:43:26.33#ibcon#flushed, iclass 38, count 2 2006.257.08:43:26.33#ibcon#about to write, iclass 38, count 2 2006.257.08:43:26.33#ibcon#wrote, iclass 38, count 2 2006.257.08:43:26.33#ibcon#about to read 3, iclass 38, count 2 2006.257.08:43:26.36#ibcon#read 3, iclass 38, count 2 2006.257.08:43:26.36#ibcon#about to read 4, iclass 38, count 2 2006.257.08:43:26.36#ibcon#read 4, iclass 38, count 2 2006.257.08:43:26.36#ibcon#about to read 5, iclass 38, count 2 2006.257.08:43:26.36#ibcon#read 5, iclass 38, count 2 2006.257.08:43:26.36#ibcon#about to read 6, iclass 38, count 2 2006.257.08:43:26.36#ibcon#read 6, iclass 38, count 2 2006.257.08:43:26.36#ibcon#end of sib2, iclass 38, count 2 2006.257.08:43:26.36#ibcon#*after write, iclass 38, count 2 2006.257.08:43:26.36#ibcon#*before return 0, iclass 38, count 2 2006.257.08:43:26.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:26.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:26.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.08:43:26.36#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:26.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:26.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:26.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:26.48#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:43:26.48#ibcon#first serial, iclass 38, count 0 2006.257.08:43:26.48#ibcon#enter sib2, iclass 38, count 0 2006.257.08:43:26.48#ibcon#flushed, iclass 38, count 0 2006.257.08:43:26.48#ibcon#about to write, iclass 38, count 0 2006.257.08:43:26.48#ibcon#wrote, iclass 38, count 0 2006.257.08:43:26.48#ibcon#about to read 3, iclass 38, count 0 2006.257.08:43:26.50#ibcon#read 3, iclass 38, count 0 2006.257.08:43:26.50#ibcon#about to read 4, iclass 38, count 0 2006.257.08:43:26.50#ibcon#read 4, iclass 38, count 0 2006.257.08:43:26.50#ibcon#about to read 5, iclass 38, count 0 2006.257.08:43:26.50#ibcon#read 5, iclass 38, count 0 2006.257.08:43:26.50#ibcon#about to read 6, iclass 38, count 0 2006.257.08:43:26.50#ibcon#read 6, iclass 38, count 0 2006.257.08:43:26.50#ibcon#end of sib2, iclass 38, count 0 2006.257.08:43:26.50#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:43:26.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:43:26.50#ibcon#[25=USB\r\n] 2006.257.08:43:26.50#ibcon#*before write, iclass 38, count 0 2006.257.08:43:26.50#ibcon#enter sib2, iclass 38, count 0 2006.257.08:43:26.50#ibcon#flushed, iclass 38, count 0 2006.257.08:43:26.50#ibcon#about to write, iclass 38, count 0 2006.257.08:43:26.50#ibcon#wrote, iclass 38, count 0 2006.257.08:43:26.50#ibcon#about to read 3, iclass 38, count 0 2006.257.08:43:26.53#ibcon#read 3, iclass 38, count 0 2006.257.08:43:26.53#ibcon#about to read 4, iclass 38, count 0 2006.257.08:43:26.53#ibcon#read 4, iclass 38, count 0 2006.257.08:43:26.53#ibcon#about to read 5, iclass 38, count 0 2006.257.08:43:26.53#ibcon#read 5, iclass 38, count 0 2006.257.08:43:26.53#ibcon#about to read 6, iclass 38, count 0 2006.257.08:43:26.53#ibcon#read 6, iclass 38, count 0 2006.257.08:43:26.53#ibcon#end of sib2, iclass 38, count 0 2006.257.08:43:26.53#ibcon#*after write, iclass 38, count 0 2006.257.08:43:26.53#ibcon#*before return 0, iclass 38, count 0 2006.257.08:43:26.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:26.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:26.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:43:26.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:43:26.53$vck44/valo=8,884.99 2006.257.08:43:26.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.08:43:26.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.08:43:26.53#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:26.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:26.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:26.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:26.53#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:43:26.53#ibcon#first serial, iclass 40, count 0 2006.257.08:43:26.53#ibcon#enter sib2, iclass 40, count 0 2006.257.08:43:26.53#ibcon#flushed, iclass 40, count 0 2006.257.08:43:26.53#ibcon#about to write, iclass 40, count 0 2006.257.08:43:26.53#ibcon#wrote, iclass 40, count 0 2006.257.08:43:26.53#ibcon#about to read 3, iclass 40, count 0 2006.257.08:43:26.55#ibcon#read 3, iclass 40, count 0 2006.257.08:43:26.55#ibcon#about to read 4, iclass 40, count 0 2006.257.08:43:26.55#ibcon#read 4, iclass 40, count 0 2006.257.08:43:26.55#ibcon#about to read 5, iclass 40, count 0 2006.257.08:43:26.55#ibcon#read 5, iclass 40, count 0 2006.257.08:43:26.55#ibcon#about to read 6, iclass 40, count 0 2006.257.08:43:26.55#ibcon#read 6, iclass 40, count 0 2006.257.08:43:26.55#ibcon#end of sib2, iclass 40, count 0 2006.257.08:43:26.55#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:43:26.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:43:26.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:43:26.55#ibcon#*before write, iclass 40, count 0 2006.257.08:43:26.55#ibcon#enter sib2, iclass 40, count 0 2006.257.08:43:26.55#ibcon#flushed, iclass 40, count 0 2006.257.08:43:26.55#ibcon#about to write, iclass 40, count 0 2006.257.08:43:26.55#ibcon#wrote, iclass 40, count 0 2006.257.08:43:26.55#ibcon#about to read 3, iclass 40, count 0 2006.257.08:43:26.59#ibcon#read 3, iclass 40, count 0 2006.257.08:43:26.59#ibcon#about to read 4, iclass 40, count 0 2006.257.08:43:26.59#ibcon#read 4, iclass 40, count 0 2006.257.08:43:26.59#ibcon#about to read 5, iclass 40, count 0 2006.257.08:43:26.59#ibcon#read 5, iclass 40, count 0 2006.257.08:43:26.59#ibcon#about to read 6, iclass 40, count 0 2006.257.08:43:26.59#ibcon#read 6, iclass 40, count 0 2006.257.08:43:26.59#ibcon#end of sib2, iclass 40, count 0 2006.257.08:43:26.59#ibcon#*after write, iclass 40, count 0 2006.257.08:43:26.59#ibcon#*before return 0, iclass 40, count 0 2006.257.08:43:26.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:26.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:26.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:43:26.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:43:26.59$vck44/va=8,4 2006.257.08:43:26.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.08:43:26.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.08:43:26.59#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:26.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:43:26.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:43:26.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:43:26.65#ibcon#enter wrdev, iclass 4, count 2 2006.257.08:43:26.65#ibcon#first serial, iclass 4, count 2 2006.257.08:43:26.65#ibcon#enter sib2, iclass 4, count 2 2006.257.08:43:26.65#ibcon#flushed, iclass 4, count 2 2006.257.08:43:26.65#ibcon#about to write, iclass 4, count 2 2006.257.08:43:26.65#ibcon#wrote, iclass 4, count 2 2006.257.08:43:26.65#ibcon#about to read 3, iclass 4, count 2 2006.257.08:43:26.67#ibcon#read 3, iclass 4, count 2 2006.257.08:43:26.67#ibcon#about to read 4, iclass 4, count 2 2006.257.08:43:26.67#ibcon#read 4, iclass 4, count 2 2006.257.08:43:26.67#ibcon#about to read 5, iclass 4, count 2 2006.257.08:43:26.67#ibcon#read 5, iclass 4, count 2 2006.257.08:43:26.67#ibcon#about to read 6, iclass 4, count 2 2006.257.08:43:26.67#ibcon#read 6, iclass 4, count 2 2006.257.08:43:26.67#ibcon#end of sib2, iclass 4, count 2 2006.257.08:43:26.67#ibcon#*mode == 0, iclass 4, count 2 2006.257.08:43:26.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.08:43:26.67#ibcon#[25=AT08-04\r\n] 2006.257.08:43:26.67#ibcon#*before write, iclass 4, count 2 2006.257.08:43:26.67#ibcon#enter sib2, iclass 4, count 2 2006.257.08:43:26.67#ibcon#flushed, iclass 4, count 2 2006.257.08:43:26.67#ibcon#about to write, iclass 4, count 2 2006.257.08:43:26.67#ibcon#wrote, iclass 4, count 2 2006.257.08:43:26.67#ibcon#about to read 3, iclass 4, count 2 2006.257.08:43:26.70#ibcon#read 3, iclass 4, count 2 2006.257.08:43:26.70#ibcon#about to read 4, iclass 4, count 2 2006.257.08:43:26.70#ibcon#read 4, iclass 4, count 2 2006.257.08:43:26.70#ibcon#about to read 5, iclass 4, count 2 2006.257.08:43:26.70#ibcon#read 5, iclass 4, count 2 2006.257.08:43:26.70#ibcon#about to read 6, iclass 4, count 2 2006.257.08:43:26.70#ibcon#read 6, iclass 4, count 2 2006.257.08:43:26.70#ibcon#end of sib2, iclass 4, count 2 2006.257.08:43:26.70#ibcon#*after write, iclass 4, count 2 2006.257.08:43:26.70#ibcon#*before return 0, iclass 4, count 2 2006.257.08:43:26.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:43:26.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.08:43:26.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.08:43:26.70#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:26.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:43:26.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:43:26.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:43:26.82#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:43:26.82#ibcon#first serial, iclass 4, count 0 2006.257.08:43:26.82#ibcon#enter sib2, iclass 4, count 0 2006.257.08:43:26.82#ibcon#flushed, iclass 4, count 0 2006.257.08:43:26.82#ibcon#about to write, iclass 4, count 0 2006.257.08:43:26.82#ibcon#wrote, iclass 4, count 0 2006.257.08:43:26.82#ibcon#about to read 3, iclass 4, count 0 2006.257.08:43:26.84#ibcon#read 3, iclass 4, count 0 2006.257.08:43:26.84#ibcon#about to read 4, iclass 4, count 0 2006.257.08:43:26.84#ibcon#read 4, iclass 4, count 0 2006.257.08:43:26.84#ibcon#about to read 5, iclass 4, count 0 2006.257.08:43:26.84#ibcon#read 5, iclass 4, count 0 2006.257.08:43:26.84#ibcon#about to read 6, iclass 4, count 0 2006.257.08:43:26.84#ibcon#read 6, iclass 4, count 0 2006.257.08:43:26.84#ibcon#end of sib2, iclass 4, count 0 2006.257.08:43:26.84#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:43:26.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:43:26.84#ibcon#[25=USB\r\n] 2006.257.08:43:26.84#ibcon#*before write, iclass 4, count 0 2006.257.08:43:26.84#ibcon#enter sib2, iclass 4, count 0 2006.257.08:43:26.84#ibcon#flushed, iclass 4, count 0 2006.257.08:43:26.84#ibcon#about to write, iclass 4, count 0 2006.257.08:43:26.84#ibcon#wrote, iclass 4, count 0 2006.257.08:43:26.84#ibcon#about to read 3, iclass 4, count 0 2006.257.08:43:26.87#ibcon#read 3, iclass 4, count 0 2006.257.08:43:26.87#ibcon#about to read 4, iclass 4, count 0 2006.257.08:43:26.87#ibcon#read 4, iclass 4, count 0 2006.257.08:43:26.87#ibcon#about to read 5, iclass 4, count 0 2006.257.08:43:26.87#ibcon#read 5, iclass 4, count 0 2006.257.08:43:26.87#ibcon#about to read 6, iclass 4, count 0 2006.257.08:43:26.87#ibcon#read 6, iclass 4, count 0 2006.257.08:43:26.87#ibcon#end of sib2, iclass 4, count 0 2006.257.08:43:26.87#ibcon#*after write, iclass 4, count 0 2006.257.08:43:26.87#ibcon#*before return 0, iclass 4, count 0 2006.257.08:43:26.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:43:26.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.08:43:26.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:43:26.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:43:26.87$vck44/vblo=1,629.99 2006.257.08:43:26.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.08:43:26.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.08:43:26.87#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:26.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:43:26.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:43:26.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:43:26.87#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:43:26.87#ibcon#first serial, iclass 6, count 0 2006.257.08:43:26.87#ibcon#enter sib2, iclass 6, count 0 2006.257.08:43:26.87#ibcon#flushed, iclass 6, count 0 2006.257.08:43:26.87#ibcon#about to write, iclass 6, count 0 2006.257.08:43:26.87#ibcon#wrote, iclass 6, count 0 2006.257.08:43:26.87#ibcon#about to read 3, iclass 6, count 0 2006.257.08:43:26.89#ibcon#read 3, iclass 6, count 0 2006.257.08:43:26.89#ibcon#about to read 4, iclass 6, count 0 2006.257.08:43:26.89#ibcon#read 4, iclass 6, count 0 2006.257.08:43:26.89#ibcon#about to read 5, iclass 6, count 0 2006.257.08:43:26.89#ibcon#read 5, iclass 6, count 0 2006.257.08:43:26.89#ibcon#about to read 6, iclass 6, count 0 2006.257.08:43:26.89#ibcon#read 6, iclass 6, count 0 2006.257.08:43:26.89#ibcon#end of sib2, iclass 6, count 0 2006.257.08:43:26.89#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:43:26.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:43:26.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:43:26.89#ibcon#*before write, iclass 6, count 0 2006.257.08:43:26.89#ibcon#enter sib2, iclass 6, count 0 2006.257.08:43:26.89#ibcon#flushed, iclass 6, count 0 2006.257.08:43:26.89#ibcon#about to write, iclass 6, count 0 2006.257.08:43:26.89#ibcon#wrote, iclass 6, count 0 2006.257.08:43:26.89#ibcon#about to read 3, iclass 6, count 0 2006.257.08:43:26.93#ibcon#read 3, iclass 6, count 0 2006.257.08:43:26.93#ibcon#about to read 4, iclass 6, count 0 2006.257.08:43:26.93#ibcon#read 4, iclass 6, count 0 2006.257.08:43:26.93#ibcon#about to read 5, iclass 6, count 0 2006.257.08:43:26.93#ibcon#read 5, iclass 6, count 0 2006.257.08:43:26.93#ibcon#about to read 6, iclass 6, count 0 2006.257.08:43:26.93#ibcon#read 6, iclass 6, count 0 2006.257.08:43:26.93#ibcon#end of sib2, iclass 6, count 0 2006.257.08:43:26.93#ibcon#*after write, iclass 6, count 0 2006.257.08:43:26.93#ibcon#*before return 0, iclass 6, count 0 2006.257.08:43:26.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:43:26.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.08:43:26.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:43:26.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:43:26.93$vck44/vb=1,4 2006.257.08:43:26.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.08:43:26.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.08:43:26.93#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:26.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:43:26.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:43:26.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:43:26.93#ibcon#enter wrdev, iclass 10, count 2 2006.257.08:43:26.93#ibcon#first serial, iclass 10, count 2 2006.257.08:43:26.93#ibcon#enter sib2, iclass 10, count 2 2006.257.08:43:26.93#ibcon#flushed, iclass 10, count 2 2006.257.08:43:26.93#ibcon#about to write, iclass 10, count 2 2006.257.08:43:26.93#ibcon#wrote, iclass 10, count 2 2006.257.08:43:26.93#ibcon#about to read 3, iclass 10, count 2 2006.257.08:43:26.95#ibcon#read 3, iclass 10, count 2 2006.257.08:43:26.95#ibcon#about to read 4, iclass 10, count 2 2006.257.08:43:26.95#ibcon#read 4, iclass 10, count 2 2006.257.08:43:26.95#ibcon#about to read 5, iclass 10, count 2 2006.257.08:43:26.95#ibcon#read 5, iclass 10, count 2 2006.257.08:43:26.95#ibcon#about to read 6, iclass 10, count 2 2006.257.08:43:26.95#ibcon#read 6, iclass 10, count 2 2006.257.08:43:26.95#ibcon#end of sib2, iclass 10, count 2 2006.257.08:43:26.95#ibcon#*mode == 0, iclass 10, count 2 2006.257.08:43:26.95#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.08:43:26.95#ibcon#[27=AT01-04\r\n] 2006.257.08:43:26.95#ibcon#*before write, iclass 10, count 2 2006.257.08:43:26.95#ibcon#enter sib2, iclass 10, count 2 2006.257.08:43:26.95#ibcon#flushed, iclass 10, count 2 2006.257.08:43:26.95#ibcon#about to write, iclass 10, count 2 2006.257.08:43:26.95#ibcon#wrote, iclass 10, count 2 2006.257.08:43:26.95#ibcon#about to read 3, iclass 10, count 2 2006.257.08:43:26.98#ibcon#read 3, iclass 10, count 2 2006.257.08:43:26.98#ibcon#about to read 4, iclass 10, count 2 2006.257.08:43:26.98#ibcon#read 4, iclass 10, count 2 2006.257.08:43:26.98#ibcon#about to read 5, iclass 10, count 2 2006.257.08:43:26.98#ibcon#read 5, iclass 10, count 2 2006.257.08:43:26.98#ibcon#about to read 6, iclass 10, count 2 2006.257.08:43:26.98#ibcon#read 6, iclass 10, count 2 2006.257.08:43:26.98#ibcon#end of sib2, iclass 10, count 2 2006.257.08:43:26.98#ibcon#*after write, iclass 10, count 2 2006.257.08:43:26.98#ibcon#*before return 0, iclass 10, count 2 2006.257.08:43:26.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:43:26.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.08:43:26.98#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.08:43:26.98#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:26.98#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:43:27.10#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:43:27.10#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:43:27.10#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:43:27.10#ibcon#first serial, iclass 10, count 0 2006.257.08:43:27.10#ibcon#enter sib2, iclass 10, count 0 2006.257.08:43:27.10#ibcon#flushed, iclass 10, count 0 2006.257.08:43:27.10#ibcon#about to write, iclass 10, count 0 2006.257.08:43:27.10#ibcon#wrote, iclass 10, count 0 2006.257.08:43:27.10#ibcon#about to read 3, iclass 10, count 0 2006.257.08:43:27.12#ibcon#read 3, iclass 10, count 0 2006.257.08:43:27.12#ibcon#about to read 4, iclass 10, count 0 2006.257.08:43:27.12#ibcon#read 4, iclass 10, count 0 2006.257.08:43:27.12#ibcon#about to read 5, iclass 10, count 0 2006.257.08:43:27.12#ibcon#read 5, iclass 10, count 0 2006.257.08:43:27.12#ibcon#about to read 6, iclass 10, count 0 2006.257.08:43:27.12#ibcon#read 6, iclass 10, count 0 2006.257.08:43:27.12#ibcon#end of sib2, iclass 10, count 0 2006.257.08:43:27.12#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:43:27.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:43:27.12#ibcon#[27=USB\r\n] 2006.257.08:43:27.12#ibcon#*before write, iclass 10, count 0 2006.257.08:43:27.12#ibcon#enter sib2, iclass 10, count 0 2006.257.08:43:27.12#ibcon#flushed, iclass 10, count 0 2006.257.08:43:27.12#ibcon#about to write, iclass 10, count 0 2006.257.08:43:27.12#ibcon#wrote, iclass 10, count 0 2006.257.08:43:27.12#ibcon#about to read 3, iclass 10, count 0 2006.257.08:43:27.15#ibcon#read 3, iclass 10, count 0 2006.257.08:43:27.15#ibcon#about to read 4, iclass 10, count 0 2006.257.08:43:27.15#ibcon#read 4, iclass 10, count 0 2006.257.08:43:27.15#ibcon#about to read 5, iclass 10, count 0 2006.257.08:43:27.15#ibcon#read 5, iclass 10, count 0 2006.257.08:43:27.15#ibcon#about to read 6, iclass 10, count 0 2006.257.08:43:27.15#ibcon#read 6, iclass 10, count 0 2006.257.08:43:27.15#ibcon#end of sib2, iclass 10, count 0 2006.257.08:43:27.15#ibcon#*after write, iclass 10, count 0 2006.257.08:43:27.15#ibcon#*before return 0, iclass 10, count 0 2006.257.08:43:27.15#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:43:27.15#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.08:43:27.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:43:27.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:43:27.15$vck44/vblo=2,634.99 2006.257.08:43:27.15#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.08:43:27.15#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.08:43:27.15#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:27.15#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:27.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:27.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:27.15#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:43:27.15#ibcon#first serial, iclass 12, count 0 2006.257.08:43:27.15#ibcon#enter sib2, iclass 12, count 0 2006.257.08:43:27.15#ibcon#flushed, iclass 12, count 0 2006.257.08:43:27.15#ibcon#about to write, iclass 12, count 0 2006.257.08:43:27.15#ibcon#wrote, iclass 12, count 0 2006.257.08:43:27.15#ibcon#about to read 3, iclass 12, count 0 2006.257.08:43:27.17#ibcon#read 3, iclass 12, count 0 2006.257.08:43:27.17#ibcon#about to read 4, iclass 12, count 0 2006.257.08:43:27.17#ibcon#read 4, iclass 12, count 0 2006.257.08:43:27.17#ibcon#about to read 5, iclass 12, count 0 2006.257.08:43:27.17#ibcon#read 5, iclass 12, count 0 2006.257.08:43:27.17#ibcon#about to read 6, iclass 12, count 0 2006.257.08:43:27.17#ibcon#read 6, iclass 12, count 0 2006.257.08:43:27.17#ibcon#end of sib2, iclass 12, count 0 2006.257.08:43:27.17#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:43:27.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:43:27.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:43:27.17#ibcon#*before write, iclass 12, count 0 2006.257.08:43:27.17#ibcon#enter sib2, iclass 12, count 0 2006.257.08:43:27.17#ibcon#flushed, iclass 12, count 0 2006.257.08:43:27.17#ibcon#about to write, iclass 12, count 0 2006.257.08:43:27.17#ibcon#wrote, iclass 12, count 0 2006.257.08:43:27.17#ibcon#about to read 3, iclass 12, count 0 2006.257.08:43:27.21#ibcon#read 3, iclass 12, count 0 2006.257.08:43:27.21#ibcon#about to read 4, iclass 12, count 0 2006.257.08:43:27.21#ibcon#read 4, iclass 12, count 0 2006.257.08:43:27.21#ibcon#about to read 5, iclass 12, count 0 2006.257.08:43:27.21#ibcon#read 5, iclass 12, count 0 2006.257.08:43:27.21#ibcon#about to read 6, iclass 12, count 0 2006.257.08:43:27.21#ibcon#read 6, iclass 12, count 0 2006.257.08:43:27.21#ibcon#end of sib2, iclass 12, count 0 2006.257.08:43:27.21#ibcon#*after write, iclass 12, count 0 2006.257.08:43:27.21#ibcon#*before return 0, iclass 12, count 0 2006.257.08:43:27.21#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:27.21#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:43:27.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:43:27.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:43:27.21$vck44/vb=2,5 2006.257.08:43:27.21#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.08:43:27.21#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.08:43:27.21#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:27.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:27.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:27.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:27.27#ibcon#enter wrdev, iclass 14, count 2 2006.257.08:43:27.27#ibcon#first serial, iclass 14, count 2 2006.257.08:43:27.27#ibcon#enter sib2, iclass 14, count 2 2006.257.08:43:27.27#ibcon#flushed, iclass 14, count 2 2006.257.08:43:27.27#ibcon#about to write, iclass 14, count 2 2006.257.08:43:27.27#ibcon#wrote, iclass 14, count 2 2006.257.08:43:27.27#ibcon#about to read 3, iclass 14, count 2 2006.257.08:43:27.29#ibcon#read 3, iclass 14, count 2 2006.257.08:43:27.29#ibcon#about to read 4, iclass 14, count 2 2006.257.08:43:27.29#ibcon#read 4, iclass 14, count 2 2006.257.08:43:27.29#ibcon#about to read 5, iclass 14, count 2 2006.257.08:43:27.29#ibcon#read 5, iclass 14, count 2 2006.257.08:43:27.29#ibcon#about to read 6, iclass 14, count 2 2006.257.08:43:27.29#ibcon#read 6, iclass 14, count 2 2006.257.08:43:27.29#ibcon#end of sib2, iclass 14, count 2 2006.257.08:43:27.29#ibcon#*mode == 0, iclass 14, count 2 2006.257.08:43:27.29#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.08:43:27.29#ibcon#[27=AT02-05\r\n] 2006.257.08:43:27.29#ibcon#*before write, iclass 14, count 2 2006.257.08:43:27.29#ibcon#enter sib2, iclass 14, count 2 2006.257.08:43:27.29#ibcon#flushed, iclass 14, count 2 2006.257.08:43:27.29#ibcon#about to write, iclass 14, count 2 2006.257.08:43:27.29#ibcon#wrote, iclass 14, count 2 2006.257.08:43:27.29#ibcon#about to read 3, iclass 14, count 2 2006.257.08:43:27.32#ibcon#read 3, iclass 14, count 2 2006.257.08:43:27.32#ibcon#about to read 4, iclass 14, count 2 2006.257.08:43:27.32#ibcon#read 4, iclass 14, count 2 2006.257.08:43:27.32#ibcon#about to read 5, iclass 14, count 2 2006.257.08:43:27.32#ibcon#read 5, iclass 14, count 2 2006.257.08:43:27.32#ibcon#about to read 6, iclass 14, count 2 2006.257.08:43:27.32#ibcon#read 6, iclass 14, count 2 2006.257.08:43:27.32#ibcon#end of sib2, iclass 14, count 2 2006.257.08:43:27.32#ibcon#*after write, iclass 14, count 2 2006.257.08:43:27.32#ibcon#*before return 0, iclass 14, count 2 2006.257.08:43:27.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:27.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.08:43:27.32#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.08:43:27.32#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:27.32#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:27.44#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:27.44#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:27.44#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:43:27.44#ibcon#first serial, iclass 14, count 0 2006.257.08:43:27.44#ibcon#enter sib2, iclass 14, count 0 2006.257.08:43:27.44#ibcon#flushed, iclass 14, count 0 2006.257.08:43:27.44#ibcon#about to write, iclass 14, count 0 2006.257.08:43:27.44#ibcon#wrote, iclass 14, count 0 2006.257.08:43:27.44#ibcon#about to read 3, iclass 14, count 0 2006.257.08:43:27.46#ibcon#read 3, iclass 14, count 0 2006.257.08:43:27.46#ibcon#about to read 4, iclass 14, count 0 2006.257.08:43:27.46#ibcon#read 4, iclass 14, count 0 2006.257.08:43:27.46#ibcon#about to read 5, iclass 14, count 0 2006.257.08:43:27.46#ibcon#read 5, iclass 14, count 0 2006.257.08:43:27.46#ibcon#about to read 6, iclass 14, count 0 2006.257.08:43:27.46#ibcon#read 6, iclass 14, count 0 2006.257.08:43:27.46#ibcon#end of sib2, iclass 14, count 0 2006.257.08:43:27.46#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:43:27.46#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:43:27.46#ibcon#[27=USB\r\n] 2006.257.08:43:27.46#ibcon#*before write, iclass 14, count 0 2006.257.08:43:27.46#ibcon#enter sib2, iclass 14, count 0 2006.257.08:43:27.46#ibcon#flushed, iclass 14, count 0 2006.257.08:43:27.46#ibcon#about to write, iclass 14, count 0 2006.257.08:43:27.46#ibcon#wrote, iclass 14, count 0 2006.257.08:43:27.46#ibcon#about to read 3, iclass 14, count 0 2006.257.08:43:27.49#ibcon#read 3, iclass 14, count 0 2006.257.08:43:27.49#ibcon#about to read 4, iclass 14, count 0 2006.257.08:43:27.49#ibcon#read 4, iclass 14, count 0 2006.257.08:43:27.49#ibcon#about to read 5, iclass 14, count 0 2006.257.08:43:27.49#ibcon#read 5, iclass 14, count 0 2006.257.08:43:27.49#ibcon#about to read 6, iclass 14, count 0 2006.257.08:43:27.49#ibcon#read 6, iclass 14, count 0 2006.257.08:43:27.49#ibcon#end of sib2, iclass 14, count 0 2006.257.08:43:27.49#ibcon#*after write, iclass 14, count 0 2006.257.08:43:27.49#ibcon#*before return 0, iclass 14, count 0 2006.257.08:43:27.49#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:27.49#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.08:43:27.49#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:43:27.49#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:43:27.49$vck44/vblo=3,649.99 2006.257.08:43:27.49#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.08:43:27.49#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.08:43:27.49#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:27.49#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:27.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:27.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:27.49#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:43:27.49#ibcon#first serial, iclass 16, count 0 2006.257.08:43:27.49#ibcon#enter sib2, iclass 16, count 0 2006.257.08:43:27.49#ibcon#flushed, iclass 16, count 0 2006.257.08:43:27.49#ibcon#about to write, iclass 16, count 0 2006.257.08:43:27.49#ibcon#wrote, iclass 16, count 0 2006.257.08:43:27.49#ibcon#about to read 3, iclass 16, count 0 2006.257.08:43:27.51#ibcon#read 3, iclass 16, count 0 2006.257.08:43:27.51#ibcon#about to read 4, iclass 16, count 0 2006.257.08:43:27.51#ibcon#read 4, iclass 16, count 0 2006.257.08:43:27.51#ibcon#about to read 5, iclass 16, count 0 2006.257.08:43:27.51#ibcon#read 5, iclass 16, count 0 2006.257.08:43:27.51#ibcon#about to read 6, iclass 16, count 0 2006.257.08:43:27.51#ibcon#read 6, iclass 16, count 0 2006.257.08:43:27.51#ibcon#end of sib2, iclass 16, count 0 2006.257.08:43:27.51#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:43:27.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:43:27.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:43:27.51#ibcon#*before write, iclass 16, count 0 2006.257.08:43:27.51#ibcon#enter sib2, iclass 16, count 0 2006.257.08:43:27.51#ibcon#flushed, iclass 16, count 0 2006.257.08:43:27.51#ibcon#about to write, iclass 16, count 0 2006.257.08:43:27.51#ibcon#wrote, iclass 16, count 0 2006.257.08:43:27.51#ibcon#about to read 3, iclass 16, count 0 2006.257.08:43:27.55#ibcon#read 3, iclass 16, count 0 2006.257.08:43:27.55#ibcon#about to read 4, iclass 16, count 0 2006.257.08:43:27.55#ibcon#read 4, iclass 16, count 0 2006.257.08:43:27.55#ibcon#about to read 5, iclass 16, count 0 2006.257.08:43:27.55#ibcon#read 5, iclass 16, count 0 2006.257.08:43:27.55#ibcon#about to read 6, iclass 16, count 0 2006.257.08:43:27.55#ibcon#read 6, iclass 16, count 0 2006.257.08:43:27.55#ibcon#end of sib2, iclass 16, count 0 2006.257.08:43:27.55#ibcon#*after write, iclass 16, count 0 2006.257.08:43:27.55#ibcon#*before return 0, iclass 16, count 0 2006.257.08:43:27.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:27.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.08:43:27.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:43:27.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:43:27.55$vck44/vb=3,4 2006.257.08:43:27.55#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.08:43:27.55#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.08:43:27.55#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:27.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:27.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:27.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:27.61#ibcon#enter wrdev, iclass 18, count 2 2006.257.08:43:27.61#ibcon#first serial, iclass 18, count 2 2006.257.08:43:27.61#ibcon#enter sib2, iclass 18, count 2 2006.257.08:43:27.61#ibcon#flushed, iclass 18, count 2 2006.257.08:43:27.61#ibcon#about to write, iclass 18, count 2 2006.257.08:43:27.61#ibcon#wrote, iclass 18, count 2 2006.257.08:43:27.61#ibcon#about to read 3, iclass 18, count 2 2006.257.08:43:27.63#ibcon#read 3, iclass 18, count 2 2006.257.08:43:27.63#ibcon#about to read 4, iclass 18, count 2 2006.257.08:43:27.63#ibcon#read 4, iclass 18, count 2 2006.257.08:43:27.63#ibcon#about to read 5, iclass 18, count 2 2006.257.08:43:27.63#ibcon#read 5, iclass 18, count 2 2006.257.08:43:27.63#ibcon#about to read 6, iclass 18, count 2 2006.257.08:43:27.63#ibcon#read 6, iclass 18, count 2 2006.257.08:43:27.63#ibcon#end of sib2, iclass 18, count 2 2006.257.08:43:27.63#ibcon#*mode == 0, iclass 18, count 2 2006.257.08:43:27.63#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.08:43:27.63#ibcon#[27=AT03-04\r\n] 2006.257.08:43:27.63#ibcon#*before write, iclass 18, count 2 2006.257.08:43:27.63#ibcon#enter sib2, iclass 18, count 2 2006.257.08:43:27.63#ibcon#flushed, iclass 18, count 2 2006.257.08:43:27.63#ibcon#about to write, iclass 18, count 2 2006.257.08:43:27.63#ibcon#wrote, iclass 18, count 2 2006.257.08:43:27.63#ibcon#about to read 3, iclass 18, count 2 2006.257.08:43:27.66#ibcon#read 3, iclass 18, count 2 2006.257.08:43:27.66#ibcon#about to read 4, iclass 18, count 2 2006.257.08:43:27.66#ibcon#read 4, iclass 18, count 2 2006.257.08:43:27.66#ibcon#about to read 5, iclass 18, count 2 2006.257.08:43:27.66#ibcon#read 5, iclass 18, count 2 2006.257.08:43:27.66#ibcon#about to read 6, iclass 18, count 2 2006.257.08:43:27.66#ibcon#read 6, iclass 18, count 2 2006.257.08:43:27.66#ibcon#end of sib2, iclass 18, count 2 2006.257.08:43:27.66#ibcon#*after write, iclass 18, count 2 2006.257.08:43:27.66#ibcon#*before return 0, iclass 18, count 2 2006.257.08:43:27.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:27.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.08:43:27.66#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.08:43:27.66#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:27.66#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:27.78#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:27.78#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:27.78#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:43:27.78#ibcon#first serial, iclass 18, count 0 2006.257.08:43:27.78#ibcon#enter sib2, iclass 18, count 0 2006.257.08:43:27.78#ibcon#flushed, iclass 18, count 0 2006.257.08:43:27.78#ibcon#about to write, iclass 18, count 0 2006.257.08:43:27.78#ibcon#wrote, iclass 18, count 0 2006.257.08:43:27.78#ibcon#about to read 3, iclass 18, count 0 2006.257.08:43:27.80#ibcon#read 3, iclass 18, count 0 2006.257.08:43:27.80#ibcon#about to read 4, iclass 18, count 0 2006.257.08:43:27.80#ibcon#read 4, iclass 18, count 0 2006.257.08:43:27.80#ibcon#about to read 5, iclass 18, count 0 2006.257.08:43:27.80#ibcon#read 5, iclass 18, count 0 2006.257.08:43:27.80#ibcon#about to read 6, iclass 18, count 0 2006.257.08:43:27.80#ibcon#read 6, iclass 18, count 0 2006.257.08:43:27.80#ibcon#end of sib2, iclass 18, count 0 2006.257.08:43:27.80#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:43:27.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:43:27.80#ibcon#[27=USB\r\n] 2006.257.08:43:27.80#ibcon#*before write, iclass 18, count 0 2006.257.08:43:27.80#ibcon#enter sib2, iclass 18, count 0 2006.257.08:43:27.80#ibcon#flushed, iclass 18, count 0 2006.257.08:43:27.80#ibcon#about to write, iclass 18, count 0 2006.257.08:43:27.80#ibcon#wrote, iclass 18, count 0 2006.257.08:43:27.80#ibcon#about to read 3, iclass 18, count 0 2006.257.08:43:27.83#ibcon#read 3, iclass 18, count 0 2006.257.08:43:27.83#ibcon#about to read 4, iclass 18, count 0 2006.257.08:43:27.83#ibcon#read 4, iclass 18, count 0 2006.257.08:43:27.83#ibcon#about to read 5, iclass 18, count 0 2006.257.08:43:27.83#ibcon#read 5, iclass 18, count 0 2006.257.08:43:27.83#ibcon#about to read 6, iclass 18, count 0 2006.257.08:43:27.83#ibcon#read 6, iclass 18, count 0 2006.257.08:43:27.83#ibcon#end of sib2, iclass 18, count 0 2006.257.08:43:27.83#ibcon#*after write, iclass 18, count 0 2006.257.08:43:27.83#ibcon#*before return 0, iclass 18, count 0 2006.257.08:43:27.83#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:27.83#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.08:43:27.83#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:43:27.83#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:43:27.83$vck44/vblo=4,679.99 2006.257.08:43:27.83#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.08:43:27.83#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.08:43:27.83#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:27.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:27.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:27.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:27.83#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:43:27.83#ibcon#first serial, iclass 20, count 0 2006.257.08:43:27.83#ibcon#enter sib2, iclass 20, count 0 2006.257.08:43:27.83#ibcon#flushed, iclass 20, count 0 2006.257.08:43:27.83#ibcon#about to write, iclass 20, count 0 2006.257.08:43:27.83#ibcon#wrote, iclass 20, count 0 2006.257.08:43:27.83#ibcon#about to read 3, iclass 20, count 0 2006.257.08:43:27.85#ibcon#read 3, iclass 20, count 0 2006.257.08:43:27.85#ibcon#about to read 4, iclass 20, count 0 2006.257.08:43:27.85#ibcon#read 4, iclass 20, count 0 2006.257.08:43:27.85#ibcon#about to read 5, iclass 20, count 0 2006.257.08:43:27.85#ibcon#read 5, iclass 20, count 0 2006.257.08:43:27.85#ibcon#about to read 6, iclass 20, count 0 2006.257.08:43:27.85#ibcon#read 6, iclass 20, count 0 2006.257.08:43:27.85#ibcon#end of sib2, iclass 20, count 0 2006.257.08:43:27.85#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:43:27.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:43:27.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:43:27.85#ibcon#*before write, iclass 20, count 0 2006.257.08:43:27.85#ibcon#enter sib2, iclass 20, count 0 2006.257.08:43:27.85#ibcon#flushed, iclass 20, count 0 2006.257.08:43:27.85#ibcon#about to write, iclass 20, count 0 2006.257.08:43:27.85#ibcon#wrote, iclass 20, count 0 2006.257.08:43:27.85#ibcon#about to read 3, iclass 20, count 0 2006.257.08:43:27.89#ibcon#read 3, iclass 20, count 0 2006.257.08:43:27.89#ibcon#about to read 4, iclass 20, count 0 2006.257.08:43:27.89#ibcon#read 4, iclass 20, count 0 2006.257.08:43:27.89#ibcon#about to read 5, iclass 20, count 0 2006.257.08:43:27.89#ibcon#read 5, iclass 20, count 0 2006.257.08:43:27.89#ibcon#about to read 6, iclass 20, count 0 2006.257.08:43:27.89#ibcon#read 6, iclass 20, count 0 2006.257.08:43:27.89#ibcon#end of sib2, iclass 20, count 0 2006.257.08:43:27.89#ibcon#*after write, iclass 20, count 0 2006.257.08:43:27.89#ibcon#*before return 0, iclass 20, count 0 2006.257.08:43:27.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:27.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.08:43:27.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:43:27.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:43:27.89$vck44/vb=4,5 2006.257.08:43:27.89#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.08:43:27.89#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.08:43:27.89#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:27.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:27.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:27.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:27.95#ibcon#enter wrdev, iclass 22, count 2 2006.257.08:43:27.95#ibcon#first serial, iclass 22, count 2 2006.257.08:43:27.95#ibcon#enter sib2, iclass 22, count 2 2006.257.08:43:27.95#ibcon#flushed, iclass 22, count 2 2006.257.08:43:27.95#ibcon#about to write, iclass 22, count 2 2006.257.08:43:27.95#ibcon#wrote, iclass 22, count 2 2006.257.08:43:27.95#ibcon#about to read 3, iclass 22, count 2 2006.257.08:43:27.97#ibcon#read 3, iclass 22, count 2 2006.257.08:43:27.97#ibcon#about to read 4, iclass 22, count 2 2006.257.08:43:27.97#ibcon#read 4, iclass 22, count 2 2006.257.08:43:27.97#ibcon#about to read 5, iclass 22, count 2 2006.257.08:43:27.97#ibcon#read 5, iclass 22, count 2 2006.257.08:43:27.97#ibcon#about to read 6, iclass 22, count 2 2006.257.08:43:27.97#ibcon#read 6, iclass 22, count 2 2006.257.08:43:27.97#ibcon#end of sib2, iclass 22, count 2 2006.257.08:43:27.97#ibcon#*mode == 0, iclass 22, count 2 2006.257.08:43:27.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.08:43:27.97#ibcon#[27=AT04-05\r\n] 2006.257.08:43:27.97#ibcon#*before write, iclass 22, count 2 2006.257.08:43:27.97#ibcon#enter sib2, iclass 22, count 2 2006.257.08:43:27.97#ibcon#flushed, iclass 22, count 2 2006.257.08:43:27.97#ibcon#about to write, iclass 22, count 2 2006.257.08:43:27.97#ibcon#wrote, iclass 22, count 2 2006.257.08:43:27.97#ibcon#about to read 3, iclass 22, count 2 2006.257.08:43:28.00#ibcon#read 3, iclass 22, count 2 2006.257.08:43:28.00#ibcon#about to read 4, iclass 22, count 2 2006.257.08:43:28.00#ibcon#read 4, iclass 22, count 2 2006.257.08:43:28.00#ibcon#about to read 5, iclass 22, count 2 2006.257.08:43:28.00#ibcon#read 5, iclass 22, count 2 2006.257.08:43:28.00#ibcon#about to read 6, iclass 22, count 2 2006.257.08:43:28.00#ibcon#read 6, iclass 22, count 2 2006.257.08:43:28.00#ibcon#end of sib2, iclass 22, count 2 2006.257.08:43:28.00#ibcon#*after write, iclass 22, count 2 2006.257.08:43:28.00#ibcon#*before return 0, iclass 22, count 2 2006.257.08:43:28.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:28.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.08:43:28.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.08:43:28.00#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:28.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:28.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:28.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:28.12#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:43:28.12#ibcon#first serial, iclass 22, count 0 2006.257.08:43:28.12#ibcon#enter sib2, iclass 22, count 0 2006.257.08:43:28.12#ibcon#flushed, iclass 22, count 0 2006.257.08:43:28.12#ibcon#about to write, iclass 22, count 0 2006.257.08:43:28.12#ibcon#wrote, iclass 22, count 0 2006.257.08:43:28.12#ibcon#about to read 3, iclass 22, count 0 2006.257.08:43:28.14#ibcon#read 3, iclass 22, count 0 2006.257.08:43:28.14#ibcon#about to read 4, iclass 22, count 0 2006.257.08:43:28.14#ibcon#read 4, iclass 22, count 0 2006.257.08:43:28.14#ibcon#about to read 5, iclass 22, count 0 2006.257.08:43:28.14#ibcon#read 5, iclass 22, count 0 2006.257.08:43:28.14#ibcon#about to read 6, iclass 22, count 0 2006.257.08:43:28.14#ibcon#read 6, iclass 22, count 0 2006.257.08:43:28.14#ibcon#end of sib2, iclass 22, count 0 2006.257.08:43:28.14#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:43:28.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:43:28.14#ibcon#[27=USB\r\n] 2006.257.08:43:28.14#ibcon#*before write, iclass 22, count 0 2006.257.08:43:28.14#ibcon#enter sib2, iclass 22, count 0 2006.257.08:43:28.14#ibcon#flushed, iclass 22, count 0 2006.257.08:43:28.14#ibcon#about to write, iclass 22, count 0 2006.257.08:43:28.14#ibcon#wrote, iclass 22, count 0 2006.257.08:43:28.14#ibcon#about to read 3, iclass 22, count 0 2006.257.08:43:28.17#ibcon#read 3, iclass 22, count 0 2006.257.08:43:28.17#ibcon#about to read 4, iclass 22, count 0 2006.257.08:43:28.17#ibcon#read 4, iclass 22, count 0 2006.257.08:43:28.17#ibcon#about to read 5, iclass 22, count 0 2006.257.08:43:28.17#ibcon#read 5, iclass 22, count 0 2006.257.08:43:28.17#ibcon#about to read 6, iclass 22, count 0 2006.257.08:43:28.17#ibcon#read 6, iclass 22, count 0 2006.257.08:43:28.17#ibcon#end of sib2, iclass 22, count 0 2006.257.08:43:28.17#ibcon#*after write, iclass 22, count 0 2006.257.08:43:28.17#ibcon#*before return 0, iclass 22, count 0 2006.257.08:43:28.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:28.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.08:43:28.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:43:28.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:43:28.17$vck44/vblo=5,709.99 2006.257.08:43:28.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.08:43:28.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.08:43:28.17#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:28.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:28.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:28.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:28.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:43:28.17#ibcon#first serial, iclass 24, count 0 2006.257.08:43:28.17#ibcon#enter sib2, iclass 24, count 0 2006.257.08:43:28.17#ibcon#flushed, iclass 24, count 0 2006.257.08:43:28.17#ibcon#about to write, iclass 24, count 0 2006.257.08:43:28.17#ibcon#wrote, iclass 24, count 0 2006.257.08:43:28.17#ibcon#about to read 3, iclass 24, count 0 2006.257.08:43:28.19#ibcon#read 3, iclass 24, count 0 2006.257.08:43:28.19#ibcon#about to read 4, iclass 24, count 0 2006.257.08:43:28.19#ibcon#read 4, iclass 24, count 0 2006.257.08:43:28.19#ibcon#about to read 5, iclass 24, count 0 2006.257.08:43:28.19#ibcon#read 5, iclass 24, count 0 2006.257.08:43:28.19#ibcon#about to read 6, iclass 24, count 0 2006.257.08:43:28.19#ibcon#read 6, iclass 24, count 0 2006.257.08:43:28.19#ibcon#end of sib2, iclass 24, count 0 2006.257.08:43:28.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:43:28.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:43:28.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:43:28.19#ibcon#*before write, iclass 24, count 0 2006.257.08:43:28.19#ibcon#enter sib2, iclass 24, count 0 2006.257.08:43:28.19#ibcon#flushed, iclass 24, count 0 2006.257.08:43:28.19#ibcon#about to write, iclass 24, count 0 2006.257.08:43:28.19#ibcon#wrote, iclass 24, count 0 2006.257.08:43:28.19#ibcon#about to read 3, iclass 24, count 0 2006.257.08:43:28.23#ibcon#read 3, iclass 24, count 0 2006.257.08:43:28.23#ibcon#about to read 4, iclass 24, count 0 2006.257.08:43:28.23#ibcon#read 4, iclass 24, count 0 2006.257.08:43:28.23#ibcon#about to read 5, iclass 24, count 0 2006.257.08:43:28.23#ibcon#read 5, iclass 24, count 0 2006.257.08:43:28.23#ibcon#about to read 6, iclass 24, count 0 2006.257.08:43:28.23#ibcon#read 6, iclass 24, count 0 2006.257.08:43:28.23#ibcon#end of sib2, iclass 24, count 0 2006.257.08:43:28.23#ibcon#*after write, iclass 24, count 0 2006.257.08:43:28.23#ibcon#*before return 0, iclass 24, count 0 2006.257.08:43:28.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:28.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.08:43:28.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:43:28.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:43:28.23$vck44/vb=5,4 2006.257.08:43:28.23#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.08:43:28.23#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.08:43:28.23#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:28.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:28.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:28.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:28.29#ibcon#enter wrdev, iclass 26, count 2 2006.257.08:43:28.29#ibcon#first serial, iclass 26, count 2 2006.257.08:43:28.29#ibcon#enter sib2, iclass 26, count 2 2006.257.08:43:28.29#ibcon#flushed, iclass 26, count 2 2006.257.08:43:28.29#ibcon#about to write, iclass 26, count 2 2006.257.08:43:28.29#ibcon#wrote, iclass 26, count 2 2006.257.08:43:28.29#ibcon#about to read 3, iclass 26, count 2 2006.257.08:43:28.31#ibcon#read 3, iclass 26, count 2 2006.257.08:43:28.31#ibcon#about to read 4, iclass 26, count 2 2006.257.08:43:28.31#ibcon#read 4, iclass 26, count 2 2006.257.08:43:28.31#ibcon#about to read 5, iclass 26, count 2 2006.257.08:43:28.31#ibcon#read 5, iclass 26, count 2 2006.257.08:43:28.31#ibcon#about to read 6, iclass 26, count 2 2006.257.08:43:28.31#ibcon#read 6, iclass 26, count 2 2006.257.08:43:28.31#ibcon#end of sib2, iclass 26, count 2 2006.257.08:43:28.31#ibcon#*mode == 0, iclass 26, count 2 2006.257.08:43:28.31#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.08:43:28.31#ibcon#[27=AT05-04\r\n] 2006.257.08:43:28.31#ibcon#*before write, iclass 26, count 2 2006.257.08:43:28.31#ibcon#enter sib2, iclass 26, count 2 2006.257.08:43:28.31#ibcon#flushed, iclass 26, count 2 2006.257.08:43:28.31#ibcon#about to write, iclass 26, count 2 2006.257.08:43:28.31#ibcon#wrote, iclass 26, count 2 2006.257.08:43:28.31#ibcon#about to read 3, iclass 26, count 2 2006.257.08:43:28.34#ibcon#read 3, iclass 26, count 2 2006.257.08:43:28.34#ibcon#about to read 4, iclass 26, count 2 2006.257.08:43:28.34#ibcon#read 4, iclass 26, count 2 2006.257.08:43:28.34#ibcon#about to read 5, iclass 26, count 2 2006.257.08:43:28.34#ibcon#read 5, iclass 26, count 2 2006.257.08:43:28.34#ibcon#about to read 6, iclass 26, count 2 2006.257.08:43:28.34#ibcon#read 6, iclass 26, count 2 2006.257.08:43:28.34#ibcon#end of sib2, iclass 26, count 2 2006.257.08:43:28.34#ibcon#*after write, iclass 26, count 2 2006.257.08:43:28.34#ibcon#*before return 0, iclass 26, count 2 2006.257.08:43:28.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:28.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.08:43:28.34#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.08:43:28.34#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:28.34#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:28.46#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:28.46#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:28.46#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:43:28.46#ibcon#first serial, iclass 26, count 0 2006.257.08:43:28.46#ibcon#enter sib2, iclass 26, count 0 2006.257.08:43:28.46#ibcon#flushed, iclass 26, count 0 2006.257.08:43:28.46#ibcon#about to write, iclass 26, count 0 2006.257.08:43:28.46#ibcon#wrote, iclass 26, count 0 2006.257.08:43:28.46#ibcon#about to read 3, iclass 26, count 0 2006.257.08:43:28.48#ibcon#read 3, iclass 26, count 0 2006.257.08:43:28.48#ibcon#about to read 4, iclass 26, count 0 2006.257.08:43:28.48#ibcon#read 4, iclass 26, count 0 2006.257.08:43:28.48#ibcon#about to read 5, iclass 26, count 0 2006.257.08:43:28.48#ibcon#read 5, iclass 26, count 0 2006.257.08:43:28.48#ibcon#about to read 6, iclass 26, count 0 2006.257.08:43:28.48#ibcon#read 6, iclass 26, count 0 2006.257.08:43:28.48#ibcon#end of sib2, iclass 26, count 0 2006.257.08:43:28.48#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:43:28.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:43:28.48#ibcon#[27=USB\r\n] 2006.257.08:43:28.48#ibcon#*before write, iclass 26, count 0 2006.257.08:43:28.48#ibcon#enter sib2, iclass 26, count 0 2006.257.08:43:28.48#ibcon#flushed, iclass 26, count 0 2006.257.08:43:28.48#ibcon#about to write, iclass 26, count 0 2006.257.08:43:28.48#ibcon#wrote, iclass 26, count 0 2006.257.08:43:28.48#ibcon#about to read 3, iclass 26, count 0 2006.257.08:43:28.51#ibcon#read 3, iclass 26, count 0 2006.257.08:43:28.51#ibcon#about to read 4, iclass 26, count 0 2006.257.08:43:28.51#ibcon#read 4, iclass 26, count 0 2006.257.08:43:28.51#ibcon#about to read 5, iclass 26, count 0 2006.257.08:43:28.51#ibcon#read 5, iclass 26, count 0 2006.257.08:43:28.51#ibcon#about to read 6, iclass 26, count 0 2006.257.08:43:28.51#ibcon#read 6, iclass 26, count 0 2006.257.08:43:28.51#ibcon#end of sib2, iclass 26, count 0 2006.257.08:43:28.51#ibcon#*after write, iclass 26, count 0 2006.257.08:43:28.51#ibcon#*before return 0, iclass 26, count 0 2006.257.08:43:28.51#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:28.51#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.08:43:28.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:43:28.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:43:28.51$vck44/vblo=6,719.99 2006.257.08:43:28.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.08:43:28.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.08:43:28.51#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:28.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:28.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:28.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:28.51#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:43:28.51#ibcon#first serial, iclass 28, count 0 2006.257.08:43:28.51#ibcon#enter sib2, iclass 28, count 0 2006.257.08:43:28.51#ibcon#flushed, iclass 28, count 0 2006.257.08:43:28.51#ibcon#about to write, iclass 28, count 0 2006.257.08:43:28.51#ibcon#wrote, iclass 28, count 0 2006.257.08:43:28.51#ibcon#about to read 3, iclass 28, count 0 2006.257.08:43:28.53#ibcon#read 3, iclass 28, count 0 2006.257.08:43:28.53#ibcon#about to read 4, iclass 28, count 0 2006.257.08:43:28.53#ibcon#read 4, iclass 28, count 0 2006.257.08:43:28.53#ibcon#about to read 5, iclass 28, count 0 2006.257.08:43:28.53#ibcon#read 5, iclass 28, count 0 2006.257.08:43:28.53#ibcon#about to read 6, iclass 28, count 0 2006.257.08:43:28.53#ibcon#read 6, iclass 28, count 0 2006.257.08:43:28.53#ibcon#end of sib2, iclass 28, count 0 2006.257.08:43:28.53#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:43:28.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:43:28.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:43:28.53#ibcon#*before write, iclass 28, count 0 2006.257.08:43:28.53#ibcon#enter sib2, iclass 28, count 0 2006.257.08:43:28.53#ibcon#flushed, iclass 28, count 0 2006.257.08:43:28.53#ibcon#about to write, iclass 28, count 0 2006.257.08:43:28.53#ibcon#wrote, iclass 28, count 0 2006.257.08:43:28.53#ibcon#about to read 3, iclass 28, count 0 2006.257.08:43:28.57#ibcon#read 3, iclass 28, count 0 2006.257.08:43:28.57#ibcon#about to read 4, iclass 28, count 0 2006.257.08:43:28.57#ibcon#read 4, iclass 28, count 0 2006.257.08:43:28.57#ibcon#about to read 5, iclass 28, count 0 2006.257.08:43:28.57#ibcon#read 5, iclass 28, count 0 2006.257.08:43:28.57#ibcon#about to read 6, iclass 28, count 0 2006.257.08:43:28.57#ibcon#read 6, iclass 28, count 0 2006.257.08:43:28.57#ibcon#end of sib2, iclass 28, count 0 2006.257.08:43:28.57#ibcon#*after write, iclass 28, count 0 2006.257.08:43:28.57#ibcon#*before return 0, iclass 28, count 0 2006.257.08:43:28.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:28.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.08:43:28.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:43:28.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:43:28.57$vck44/vb=6,4 2006.257.08:43:28.57#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.08:43:28.57#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.08:43:28.57#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:28.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:28.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:28.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:28.63#ibcon#enter wrdev, iclass 30, count 2 2006.257.08:43:28.63#ibcon#first serial, iclass 30, count 2 2006.257.08:43:28.63#ibcon#enter sib2, iclass 30, count 2 2006.257.08:43:28.63#ibcon#flushed, iclass 30, count 2 2006.257.08:43:28.63#ibcon#about to write, iclass 30, count 2 2006.257.08:43:28.63#ibcon#wrote, iclass 30, count 2 2006.257.08:43:28.63#ibcon#about to read 3, iclass 30, count 2 2006.257.08:43:28.65#ibcon#read 3, iclass 30, count 2 2006.257.08:43:28.65#ibcon#about to read 4, iclass 30, count 2 2006.257.08:43:28.65#ibcon#read 4, iclass 30, count 2 2006.257.08:43:28.65#ibcon#about to read 5, iclass 30, count 2 2006.257.08:43:28.65#ibcon#read 5, iclass 30, count 2 2006.257.08:43:28.65#ibcon#about to read 6, iclass 30, count 2 2006.257.08:43:28.65#ibcon#read 6, iclass 30, count 2 2006.257.08:43:28.65#ibcon#end of sib2, iclass 30, count 2 2006.257.08:43:28.65#ibcon#*mode == 0, iclass 30, count 2 2006.257.08:43:28.65#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.08:43:28.65#ibcon#[27=AT06-04\r\n] 2006.257.08:43:28.65#ibcon#*before write, iclass 30, count 2 2006.257.08:43:28.65#ibcon#enter sib2, iclass 30, count 2 2006.257.08:43:28.65#ibcon#flushed, iclass 30, count 2 2006.257.08:43:28.65#ibcon#about to write, iclass 30, count 2 2006.257.08:43:28.65#ibcon#wrote, iclass 30, count 2 2006.257.08:43:28.65#ibcon#about to read 3, iclass 30, count 2 2006.257.08:43:28.68#ibcon#read 3, iclass 30, count 2 2006.257.08:43:28.68#ibcon#about to read 4, iclass 30, count 2 2006.257.08:43:28.68#ibcon#read 4, iclass 30, count 2 2006.257.08:43:28.68#ibcon#about to read 5, iclass 30, count 2 2006.257.08:43:28.68#ibcon#read 5, iclass 30, count 2 2006.257.08:43:28.68#ibcon#about to read 6, iclass 30, count 2 2006.257.08:43:28.68#ibcon#read 6, iclass 30, count 2 2006.257.08:43:28.68#ibcon#end of sib2, iclass 30, count 2 2006.257.08:43:28.68#ibcon#*after write, iclass 30, count 2 2006.257.08:43:28.68#ibcon#*before return 0, iclass 30, count 2 2006.257.08:43:28.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:28.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.08:43:28.68#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.08:43:28.68#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:28.68#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:28.80#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:28.80#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:28.80#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:43:28.80#ibcon#first serial, iclass 30, count 0 2006.257.08:43:28.80#ibcon#enter sib2, iclass 30, count 0 2006.257.08:43:28.80#ibcon#flushed, iclass 30, count 0 2006.257.08:43:28.80#ibcon#about to write, iclass 30, count 0 2006.257.08:43:28.80#ibcon#wrote, iclass 30, count 0 2006.257.08:43:28.80#ibcon#about to read 3, iclass 30, count 0 2006.257.08:43:28.82#ibcon#read 3, iclass 30, count 0 2006.257.08:43:28.82#ibcon#about to read 4, iclass 30, count 0 2006.257.08:43:28.82#ibcon#read 4, iclass 30, count 0 2006.257.08:43:28.82#ibcon#about to read 5, iclass 30, count 0 2006.257.08:43:28.82#ibcon#read 5, iclass 30, count 0 2006.257.08:43:28.82#ibcon#about to read 6, iclass 30, count 0 2006.257.08:43:28.82#ibcon#read 6, iclass 30, count 0 2006.257.08:43:28.82#ibcon#end of sib2, iclass 30, count 0 2006.257.08:43:28.82#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:43:28.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:43:28.82#ibcon#[27=USB\r\n] 2006.257.08:43:28.82#ibcon#*before write, iclass 30, count 0 2006.257.08:43:28.82#ibcon#enter sib2, iclass 30, count 0 2006.257.08:43:28.82#ibcon#flushed, iclass 30, count 0 2006.257.08:43:28.82#ibcon#about to write, iclass 30, count 0 2006.257.08:43:28.82#ibcon#wrote, iclass 30, count 0 2006.257.08:43:28.82#ibcon#about to read 3, iclass 30, count 0 2006.257.08:43:28.85#ibcon#read 3, iclass 30, count 0 2006.257.08:43:28.85#ibcon#about to read 4, iclass 30, count 0 2006.257.08:43:28.85#ibcon#read 4, iclass 30, count 0 2006.257.08:43:28.85#ibcon#about to read 5, iclass 30, count 0 2006.257.08:43:28.85#ibcon#read 5, iclass 30, count 0 2006.257.08:43:28.85#ibcon#about to read 6, iclass 30, count 0 2006.257.08:43:28.85#ibcon#read 6, iclass 30, count 0 2006.257.08:43:28.85#ibcon#end of sib2, iclass 30, count 0 2006.257.08:43:28.85#ibcon#*after write, iclass 30, count 0 2006.257.08:43:28.85#ibcon#*before return 0, iclass 30, count 0 2006.257.08:43:28.85#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:28.85#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.08:43:28.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:43:28.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:43:28.85$vck44/vblo=7,734.99 2006.257.08:43:28.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.08:43:28.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.08:43:28.85#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:28.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:28.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:28.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:28.85#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:43:28.85#ibcon#first serial, iclass 32, count 0 2006.257.08:43:28.85#ibcon#enter sib2, iclass 32, count 0 2006.257.08:43:28.85#ibcon#flushed, iclass 32, count 0 2006.257.08:43:28.85#ibcon#about to write, iclass 32, count 0 2006.257.08:43:28.85#ibcon#wrote, iclass 32, count 0 2006.257.08:43:28.85#ibcon#about to read 3, iclass 32, count 0 2006.257.08:43:28.87#ibcon#read 3, iclass 32, count 0 2006.257.08:43:28.87#ibcon#about to read 4, iclass 32, count 0 2006.257.08:43:28.87#ibcon#read 4, iclass 32, count 0 2006.257.08:43:28.87#ibcon#about to read 5, iclass 32, count 0 2006.257.08:43:28.87#ibcon#read 5, iclass 32, count 0 2006.257.08:43:28.87#ibcon#about to read 6, iclass 32, count 0 2006.257.08:43:28.87#ibcon#read 6, iclass 32, count 0 2006.257.08:43:28.87#ibcon#end of sib2, iclass 32, count 0 2006.257.08:43:28.87#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:43:28.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:43:28.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:43:28.87#ibcon#*before write, iclass 32, count 0 2006.257.08:43:28.87#ibcon#enter sib2, iclass 32, count 0 2006.257.08:43:28.87#ibcon#flushed, iclass 32, count 0 2006.257.08:43:28.87#ibcon#about to write, iclass 32, count 0 2006.257.08:43:28.87#ibcon#wrote, iclass 32, count 0 2006.257.08:43:28.87#ibcon#about to read 3, iclass 32, count 0 2006.257.08:43:28.91#ibcon#read 3, iclass 32, count 0 2006.257.08:43:28.91#ibcon#about to read 4, iclass 32, count 0 2006.257.08:43:28.91#ibcon#read 4, iclass 32, count 0 2006.257.08:43:28.91#ibcon#about to read 5, iclass 32, count 0 2006.257.08:43:28.91#ibcon#read 5, iclass 32, count 0 2006.257.08:43:28.91#ibcon#about to read 6, iclass 32, count 0 2006.257.08:43:28.91#ibcon#read 6, iclass 32, count 0 2006.257.08:43:28.91#ibcon#end of sib2, iclass 32, count 0 2006.257.08:43:28.91#ibcon#*after write, iclass 32, count 0 2006.257.08:43:28.91#ibcon#*before return 0, iclass 32, count 0 2006.257.08:43:28.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:28.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.08:43:28.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:43:28.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:43:28.91$vck44/vb=7,4 2006.257.08:43:28.91#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.08:43:28.91#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.08:43:28.91#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:28.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:28.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:28.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:28.97#ibcon#enter wrdev, iclass 34, count 2 2006.257.08:43:28.97#ibcon#first serial, iclass 34, count 2 2006.257.08:43:28.97#ibcon#enter sib2, iclass 34, count 2 2006.257.08:43:28.97#ibcon#flushed, iclass 34, count 2 2006.257.08:43:28.97#ibcon#about to write, iclass 34, count 2 2006.257.08:43:28.97#ibcon#wrote, iclass 34, count 2 2006.257.08:43:28.97#ibcon#about to read 3, iclass 34, count 2 2006.257.08:43:28.99#ibcon#read 3, iclass 34, count 2 2006.257.08:43:28.99#ibcon#about to read 4, iclass 34, count 2 2006.257.08:43:28.99#ibcon#read 4, iclass 34, count 2 2006.257.08:43:28.99#ibcon#about to read 5, iclass 34, count 2 2006.257.08:43:28.99#ibcon#read 5, iclass 34, count 2 2006.257.08:43:28.99#ibcon#about to read 6, iclass 34, count 2 2006.257.08:43:28.99#ibcon#read 6, iclass 34, count 2 2006.257.08:43:28.99#ibcon#end of sib2, iclass 34, count 2 2006.257.08:43:28.99#ibcon#*mode == 0, iclass 34, count 2 2006.257.08:43:28.99#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.08:43:28.99#ibcon#[27=AT07-04\r\n] 2006.257.08:43:28.99#ibcon#*before write, iclass 34, count 2 2006.257.08:43:28.99#ibcon#enter sib2, iclass 34, count 2 2006.257.08:43:28.99#ibcon#flushed, iclass 34, count 2 2006.257.08:43:28.99#ibcon#about to write, iclass 34, count 2 2006.257.08:43:28.99#ibcon#wrote, iclass 34, count 2 2006.257.08:43:28.99#ibcon#about to read 3, iclass 34, count 2 2006.257.08:43:29.02#ibcon#read 3, iclass 34, count 2 2006.257.08:43:29.02#ibcon#about to read 4, iclass 34, count 2 2006.257.08:43:29.02#ibcon#read 4, iclass 34, count 2 2006.257.08:43:29.02#ibcon#about to read 5, iclass 34, count 2 2006.257.08:43:29.02#ibcon#read 5, iclass 34, count 2 2006.257.08:43:29.02#ibcon#about to read 6, iclass 34, count 2 2006.257.08:43:29.02#ibcon#read 6, iclass 34, count 2 2006.257.08:43:29.02#ibcon#end of sib2, iclass 34, count 2 2006.257.08:43:29.02#ibcon#*after write, iclass 34, count 2 2006.257.08:43:29.02#ibcon#*before return 0, iclass 34, count 2 2006.257.08:43:29.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:29.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.08:43:29.02#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.08:43:29.02#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:29.02#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:29.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:29.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:29.14#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:43:29.14#ibcon#first serial, iclass 34, count 0 2006.257.08:43:29.14#ibcon#enter sib2, iclass 34, count 0 2006.257.08:43:29.14#ibcon#flushed, iclass 34, count 0 2006.257.08:43:29.14#ibcon#about to write, iclass 34, count 0 2006.257.08:43:29.14#ibcon#wrote, iclass 34, count 0 2006.257.08:43:29.14#ibcon#about to read 3, iclass 34, count 0 2006.257.08:43:29.16#ibcon#read 3, iclass 34, count 0 2006.257.08:43:29.16#ibcon#about to read 4, iclass 34, count 0 2006.257.08:43:29.16#ibcon#read 4, iclass 34, count 0 2006.257.08:43:29.16#ibcon#about to read 5, iclass 34, count 0 2006.257.08:43:29.16#ibcon#read 5, iclass 34, count 0 2006.257.08:43:29.16#ibcon#about to read 6, iclass 34, count 0 2006.257.08:43:29.16#ibcon#read 6, iclass 34, count 0 2006.257.08:43:29.16#ibcon#end of sib2, iclass 34, count 0 2006.257.08:43:29.16#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:43:29.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:43:29.16#ibcon#[27=USB\r\n] 2006.257.08:43:29.16#ibcon#*before write, iclass 34, count 0 2006.257.08:43:29.16#ibcon#enter sib2, iclass 34, count 0 2006.257.08:43:29.16#ibcon#flushed, iclass 34, count 0 2006.257.08:43:29.16#ibcon#about to write, iclass 34, count 0 2006.257.08:43:29.16#ibcon#wrote, iclass 34, count 0 2006.257.08:43:29.16#ibcon#about to read 3, iclass 34, count 0 2006.257.08:43:29.19#ibcon#read 3, iclass 34, count 0 2006.257.08:43:29.19#ibcon#about to read 4, iclass 34, count 0 2006.257.08:43:29.19#ibcon#read 4, iclass 34, count 0 2006.257.08:43:29.19#ibcon#about to read 5, iclass 34, count 0 2006.257.08:43:29.19#ibcon#read 5, iclass 34, count 0 2006.257.08:43:29.19#ibcon#about to read 6, iclass 34, count 0 2006.257.08:43:29.19#ibcon#read 6, iclass 34, count 0 2006.257.08:43:29.19#ibcon#end of sib2, iclass 34, count 0 2006.257.08:43:29.19#ibcon#*after write, iclass 34, count 0 2006.257.08:43:29.19#ibcon#*before return 0, iclass 34, count 0 2006.257.08:43:29.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:29.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.08:43:29.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:43:29.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:43:29.19$vck44/vblo=8,744.99 2006.257.08:43:29.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.08:43:29.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.08:43:29.19#ibcon#ireg 17 cls_cnt 0 2006.257.08:43:29.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:29.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:29.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:29.19#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:43:29.19#ibcon#first serial, iclass 36, count 0 2006.257.08:43:29.19#ibcon#enter sib2, iclass 36, count 0 2006.257.08:43:29.19#ibcon#flushed, iclass 36, count 0 2006.257.08:43:29.19#ibcon#about to write, iclass 36, count 0 2006.257.08:43:29.19#ibcon#wrote, iclass 36, count 0 2006.257.08:43:29.19#ibcon#about to read 3, iclass 36, count 0 2006.257.08:43:29.21#ibcon#read 3, iclass 36, count 0 2006.257.08:43:29.21#ibcon#about to read 4, iclass 36, count 0 2006.257.08:43:29.21#ibcon#read 4, iclass 36, count 0 2006.257.08:43:29.21#ibcon#about to read 5, iclass 36, count 0 2006.257.08:43:29.21#ibcon#read 5, iclass 36, count 0 2006.257.08:43:29.21#ibcon#about to read 6, iclass 36, count 0 2006.257.08:43:29.21#ibcon#read 6, iclass 36, count 0 2006.257.08:43:29.21#ibcon#end of sib2, iclass 36, count 0 2006.257.08:43:29.21#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:43:29.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:43:29.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:43:29.21#ibcon#*before write, iclass 36, count 0 2006.257.08:43:29.21#ibcon#enter sib2, iclass 36, count 0 2006.257.08:43:29.21#ibcon#flushed, iclass 36, count 0 2006.257.08:43:29.21#ibcon#about to write, iclass 36, count 0 2006.257.08:43:29.21#ibcon#wrote, iclass 36, count 0 2006.257.08:43:29.21#ibcon#about to read 3, iclass 36, count 0 2006.257.08:43:29.25#ibcon#read 3, iclass 36, count 0 2006.257.08:43:29.25#ibcon#about to read 4, iclass 36, count 0 2006.257.08:43:29.25#ibcon#read 4, iclass 36, count 0 2006.257.08:43:29.25#ibcon#about to read 5, iclass 36, count 0 2006.257.08:43:29.25#ibcon#read 5, iclass 36, count 0 2006.257.08:43:29.25#ibcon#about to read 6, iclass 36, count 0 2006.257.08:43:29.25#ibcon#read 6, iclass 36, count 0 2006.257.08:43:29.25#ibcon#end of sib2, iclass 36, count 0 2006.257.08:43:29.25#ibcon#*after write, iclass 36, count 0 2006.257.08:43:29.25#ibcon#*before return 0, iclass 36, count 0 2006.257.08:43:29.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:29.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.08:43:29.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:43:29.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:43:29.25$vck44/vb=8,4 2006.257.08:43:29.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.08:43:29.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.08:43:29.25#ibcon#ireg 11 cls_cnt 2 2006.257.08:43:29.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:29.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:29.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:29.31#ibcon#enter wrdev, iclass 38, count 2 2006.257.08:43:29.31#ibcon#first serial, iclass 38, count 2 2006.257.08:43:29.31#ibcon#enter sib2, iclass 38, count 2 2006.257.08:43:29.31#ibcon#flushed, iclass 38, count 2 2006.257.08:43:29.31#ibcon#about to write, iclass 38, count 2 2006.257.08:43:29.31#ibcon#wrote, iclass 38, count 2 2006.257.08:43:29.31#ibcon#about to read 3, iclass 38, count 2 2006.257.08:43:29.33#ibcon#read 3, iclass 38, count 2 2006.257.08:43:29.33#ibcon#about to read 4, iclass 38, count 2 2006.257.08:43:29.33#ibcon#read 4, iclass 38, count 2 2006.257.08:43:29.33#ibcon#about to read 5, iclass 38, count 2 2006.257.08:43:29.33#ibcon#read 5, iclass 38, count 2 2006.257.08:43:29.33#ibcon#about to read 6, iclass 38, count 2 2006.257.08:43:29.33#ibcon#read 6, iclass 38, count 2 2006.257.08:43:29.33#ibcon#end of sib2, iclass 38, count 2 2006.257.08:43:29.33#ibcon#*mode == 0, iclass 38, count 2 2006.257.08:43:29.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.08:43:29.33#ibcon#[27=AT08-04\r\n] 2006.257.08:43:29.33#ibcon#*before write, iclass 38, count 2 2006.257.08:43:29.33#ibcon#enter sib2, iclass 38, count 2 2006.257.08:43:29.33#ibcon#flushed, iclass 38, count 2 2006.257.08:43:29.33#ibcon#about to write, iclass 38, count 2 2006.257.08:43:29.33#ibcon#wrote, iclass 38, count 2 2006.257.08:43:29.33#ibcon#about to read 3, iclass 38, count 2 2006.257.08:43:29.36#ibcon#read 3, iclass 38, count 2 2006.257.08:43:29.36#ibcon#about to read 4, iclass 38, count 2 2006.257.08:43:29.36#ibcon#read 4, iclass 38, count 2 2006.257.08:43:29.36#ibcon#about to read 5, iclass 38, count 2 2006.257.08:43:29.36#ibcon#read 5, iclass 38, count 2 2006.257.08:43:29.36#ibcon#about to read 6, iclass 38, count 2 2006.257.08:43:29.36#ibcon#read 6, iclass 38, count 2 2006.257.08:43:29.36#ibcon#end of sib2, iclass 38, count 2 2006.257.08:43:29.36#ibcon#*after write, iclass 38, count 2 2006.257.08:43:29.36#ibcon#*before return 0, iclass 38, count 2 2006.257.08:43:29.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:29.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.08:43:29.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.08:43:29.36#ibcon#ireg 7 cls_cnt 0 2006.257.08:43:29.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:29.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:29.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:29.48#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:43:29.48#ibcon#first serial, iclass 38, count 0 2006.257.08:43:29.48#ibcon#enter sib2, iclass 38, count 0 2006.257.08:43:29.48#ibcon#flushed, iclass 38, count 0 2006.257.08:43:29.48#ibcon#about to write, iclass 38, count 0 2006.257.08:43:29.48#ibcon#wrote, iclass 38, count 0 2006.257.08:43:29.48#ibcon#about to read 3, iclass 38, count 0 2006.257.08:43:29.50#ibcon#read 3, iclass 38, count 0 2006.257.08:43:29.50#ibcon#about to read 4, iclass 38, count 0 2006.257.08:43:29.50#ibcon#read 4, iclass 38, count 0 2006.257.08:43:29.50#ibcon#about to read 5, iclass 38, count 0 2006.257.08:43:29.50#ibcon#read 5, iclass 38, count 0 2006.257.08:43:29.50#ibcon#about to read 6, iclass 38, count 0 2006.257.08:43:29.50#ibcon#read 6, iclass 38, count 0 2006.257.08:43:29.50#ibcon#end of sib2, iclass 38, count 0 2006.257.08:43:29.50#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:43:29.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:43:29.50#ibcon#[27=USB\r\n] 2006.257.08:43:29.50#ibcon#*before write, iclass 38, count 0 2006.257.08:43:29.50#ibcon#enter sib2, iclass 38, count 0 2006.257.08:43:29.50#ibcon#flushed, iclass 38, count 0 2006.257.08:43:29.50#ibcon#about to write, iclass 38, count 0 2006.257.08:43:29.50#ibcon#wrote, iclass 38, count 0 2006.257.08:43:29.50#ibcon#about to read 3, iclass 38, count 0 2006.257.08:43:29.53#ibcon#read 3, iclass 38, count 0 2006.257.08:43:29.53#ibcon#about to read 4, iclass 38, count 0 2006.257.08:43:29.53#ibcon#read 4, iclass 38, count 0 2006.257.08:43:29.53#ibcon#about to read 5, iclass 38, count 0 2006.257.08:43:29.53#ibcon#read 5, iclass 38, count 0 2006.257.08:43:29.53#ibcon#about to read 6, iclass 38, count 0 2006.257.08:43:29.53#ibcon#read 6, iclass 38, count 0 2006.257.08:43:29.53#ibcon#end of sib2, iclass 38, count 0 2006.257.08:43:29.53#ibcon#*after write, iclass 38, count 0 2006.257.08:43:29.53#ibcon#*before return 0, iclass 38, count 0 2006.257.08:43:29.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:29.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.08:43:29.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:43:29.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:43:29.53$vck44/vabw=wide 2006.257.08:43:29.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.08:43:29.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.08:43:29.53#ibcon#ireg 8 cls_cnt 0 2006.257.08:43:29.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:29.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:29.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:29.53#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:43:29.53#ibcon#first serial, iclass 40, count 0 2006.257.08:43:29.53#ibcon#enter sib2, iclass 40, count 0 2006.257.08:43:29.53#ibcon#flushed, iclass 40, count 0 2006.257.08:43:29.53#ibcon#about to write, iclass 40, count 0 2006.257.08:43:29.53#ibcon#wrote, iclass 40, count 0 2006.257.08:43:29.53#ibcon#about to read 3, iclass 40, count 0 2006.257.08:43:29.55#ibcon#read 3, iclass 40, count 0 2006.257.08:43:29.55#ibcon#about to read 4, iclass 40, count 0 2006.257.08:43:29.55#ibcon#read 4, iclass 40, count 0 2006.257.08:43:29.55#ibcon#about to read 5, iclass 40, count 0 2006.257.08:43:29.55#ibcon#read 5, iclass 40, count 0 2006.257.08:43:29.55#ibcon#about to read 6, iclass 40, count 0 2006.257.08:43:29.55#ibcon#read 6, iclass 40, count 0 2006.257.08:43:29.55#ibcon#end of sib2, iclass 40, count 0 2006.257.08:43:29.55#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:43:29.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:43:29.55#ibcon#[25=BW32\r\n] 2006.257.08:43:29.55#ibcon#*before write, iclass 40, count 0 2006.257.08:43:29.55#ibcon#enter sib2, iclass 40, count 0 2006.257.08:43:29.55#ibcon#flushed, iclass 40, count 0 2006.257.08:43:29.55#ibcon#about to write, iclass 40, count 0 2006.257.08:43:29.55#ibcon#wrote, iclass 40, count 0 2006.257.08:43:29.55#ibcon#about to read 3, iclass 40, count 0 2006.257.08:43:29.58#ibcon#read 3, iclass 40, count 0 2006.257.08:43:29.58#ibcon#about to read 4, iclass 40, count 0 2006.257.08:43:29.58#ibcon#read 4, iclass 40, count 0 2006.257.08:43:29.58#ibcon#about to read 5, iclass 40, count 0 2006.257.08:43:29.58#ibcon#read 5, iclass 40, count 0 2006.257.08:43:29.58#ibcon#about to read 6, iclass 40, count 0 2006.257.08:43:29.58#ibcon#read 6, iclass 40, count 0 2006.257.08:43:29.58#ibcon#end of sib2, iclass 40, count 0 2006.257.08:43:29.58#ibcon#*after write, iclass 40, count 0 2006.257.08:43:29.58#ibcon#*before return 0, iclass 40, count 0 2006.257.08:43:29.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:29.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.08:43:29.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:43:29.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:43:29.58$vck44/vbbw=wide 2006.257.08:43:29.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.08:43:29.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.08:43:29.58#ibcon#ireg 8 cls_cnt 0 2006.257.08:43:29.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:43:29.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:43:29.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:43:29.65#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:43:29.65#ibcon#first serial, iclass 4, count 0 2006.257.08:43:29.65#ibcon#enter sib2, iclass 4, count 0 2006.257.08:43:29.65#ibcon#flushed, iclass 4, count 0 2006.257.08:43:29.65#ibcon#about to write, iclass 4, count 0 2006.257.08:43:29.65#ibcon#wrote, iclass 4, count 0 2006.257.08:43:29.65#ibcon#about to read 3, iclass 4, count 0 2006.257.08:43:29.67#ibcon#read 3, iclass 4, count 0 2006.257.08:43:29.67#ibcon#about to read 4, iclass 4, count 0 2006.257.08:43:29.67#ibcon#read 4, iclass 4, count 0 2006.257.08:43:29.67#ibcon#about to read 5, iclass 4, count 0 2006.257.08:43:29.67#ibcon#read 5, iclass 4, count 0 2006.257.08:43:29.67#ibcon#about to read 6, iclass 4, count 0 2006.257.08:43:29.67#ibcon#read 6, iclass 4, count 0 2006.257.08:43:29.67#ibcon#end of sib2, iclass 4, count 0 2006.257.08:43:29.67#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:43:29.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:43:29.67#ibcon#[27=BW32\r\n] 2006.257.08:43:29.67#ibcon#*before write, iclass 4, count 0 2006.257.08:43:29.67#ibcon#enter sib2, iclass 4, count 0 2006.257.08:43:29.67#ibcon#flushed, iclass 4, count 0 2006.257.08:43:29.67#ibcon#about to write, iclass 4, count 0 2006.257.08:43:29.67#ibcon#wrote, iclass 4, count 0 2006.257.08:43:29.67#ibcon#about to read 3, iclass 4, count 0 2006.257.08:43:29.70#ibcon#read 3, iclass 4, count 0 2006.257.08:43:29.70#ibcon#about to read 4, iclass 4, count 0 2006.257.08:43:29.70#ibcon#read 4, iclass 4, count 0 2006.257.08:43:29.70#ibcon#about to read 5, iclass 4, count 0 2006.257.08:43:29.70#ibcon#read 5, iclass 4, count 0 2006.257.08:43:29.70#ibcon#about to read 6, iclass 4, count 0 2006.257.08:43:29.70#ibcon#read 6, iclass 4, count 0 2006.257.08:43:29.70#ibcon#end of sib2, iclass 4, count 0 2006.257.08:43:29.70#ibcon#*after write, iclass 4, count 0 2006.257.08:43:29.70#ibcon#*before return 0, iclass 4, count 0 2006.257.08:43:29.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:43:29.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:43:29.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:43:29.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:43:29.70$setupk4/ifdk4 2006.257.08:43:29.70$ifdk4/lo= 2006.257.08:43:29.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:43:29.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:43:29.70$ifdk4/patch= 2006.257.08:43:29.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:43:29.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:43:29.70$setupk4/!*+20s 2006.257.08:43:32.60#abcon#<5=/15 1.1 2.0 20.46 921013.1\r\n> 2006.257.08:43:32.62#abcon#{5=INTERFACE CLEAR} 2006.257.08:43:32.68#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:43:35.14#trakl#Source acquired 2006.257.08:43:37.14#flagr#flagr/antenna,acquired 2006.257.08:43:42.77#abcon#<5=/15 1.0 2.0 20.46 921013.1\r\n> 2006.257.08:43:42.79#abcon#{5=INTERFACE CLEAR} 2006.257.08:43:42.85#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:43:44.20$setupk4/"tpicd 2006.257.08:43:44.20$setupk4/echo=off 2006.257.08:43:44.20$setupk4/xlog=off 2006.257.08:43:44.20:!2006.257.08:43:51 2006.257.08:43:51.00:preob 2006.257.08:43:51.14/onsource/TRACKING 2006.257.08:43:51.14:!2006.257.08:44:01 2006.257.08:44:01.00:"tape 2006.257.08:44:01.00:"st=record 2006.257.08:44:01.00:data_valid=on 2006.257.08:44:01.00:midob 2006.257.08:44:01.14/onsource/TRACKING 2006.257.08:44:01.14/wx/20.45,1013.1,92 2006.257.08:44:01.35/cable/+6.4745E-03 2006.257.08:44:02.44/va/01,08,usb,yes,33,35 2006.257.08:44:02.44/va/02,07,usb,yes,36,36 2006.257.08:44:02.44/va/03,08,usb,yes,32,34 2006.257.08:44:02.44/va/04,07,usb,yes,37,38 2006.257.08:44:02.44/va/05,04,usb,yes,33,33 2006.257.08:44:02.44/va/06,04,usb,yes,37,36 2006.257.08:44:02.44/va/07,04,usb,yes,38,38 2006.257.08:44:02.44/va/08,04,usb,yes,31,38 2006.257.08:44:02.67/valo/01,524.99,yes,locked 2006.257.08:44:02.67/valo/02,534.99,yes,locked 2006.257.08:44:02.67/valo/03,564.99,yes,locked 2006.257.08:44:02.67/valo/04,624.99,yes,locked 2006.257.08:44:02.67/valo/05,734.99,yes,locked 2006.257.08:44:02.67/valo/06,814.99,yes,locked 2006.257.08:44:02.67/valo/07,864.99,yes,locked 2006.257.08:44:02.67/valo/08,884.99,yes,locked 2006.257.08:44:03.76/vb/01,04,usb,yes,32,30 2006.257.08:44:03.76/vb/02,05,usb,yes,31,30 2006.257.08:44:03.76/vb/03,04,usb,yes,32,35 2006.257.08:44:03.76/vb/04,05,usb,yes,32,31 2006.257.08:44:03.76/vb/05,04,usb,yes,28,31 2006.257.08:44:03.76/vb/06,04,usb,yes,33,29 2006.257.08:44:03.76/vb/07,04,usb,yes,33,33 2006.257.08:44:03.76/vb/08,04,usb,yes,30,34 2006.257.08:44:03.99/vblo/01,629.99,yes,locked 2006.257.08:44:03.99/vblo/02,634.99,yes,locked 2006.257.08:44:03.99/vblo/03,649.99,yes,locked 2006.257.08:44:03.99/vblo/04,679.99,yes,locked 2006.257.08:44:03.99/vblo/05,709.99,yes,locked 2006.257.08:44:03.99/vblo/06,719.99,yes,locked 2006.257.08:44:03.99/vblo/07,734.99,yes,locked 2006.257.08:44:03.99/vblo/08,744.99,yes,locked 2006.257.08:44:04.14/vabw/8 2006.257.08:44:04.29/vbbw/8 2006.257.08:44:04.38/xfe/off,on,14.7 2006.257.08:44:04.75/ifatt/23,28,28,28 2006.257.08:44:05.07/fmout-gps/S +4.66E-07 2006.257.08:44:05.11:!2006.257.08:44:41 2006.257.08:44:41.01:data_valid=off 2006.257.08:44:41.01:"et 2006.257.08:44:41.02:!+3s 2006.257.08:44:44.03:"tape 2006.257.08:44:44.03:postob 2006.257.08:44:44.16/cable/+6.4747E-03 2006.257.08:44:44.16/wx/20.44,1013.2,92 2006.257.08:44:44.22/fmout-gps/S +4.65E-07 2006.257.08:44:44.22:scan_name=257-0846,jd0609,130 2006.257.08:44:44.23:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.257.08:44:46.14#flagr#flagr/antenna,new-source 2006.257.08:44:46.14:checkk5 2006.257.08:44:46.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:44:46.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:44:47.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:44:47.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:44:48.13/chk_obsdata//k5ts1/T2570844??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.08:44:48.53/chk_obsdata//k5ts2/T2570844??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.08:44:48.93/chk_obsdata//k5ts3/T2570844??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.08:44:49.34/chk_obsdata//k5ts4/T2570844??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.08:44:50.07/k5log//k5ts1_log_newline 2006.257.08:44:50.76/k5log//k5ts2_log_newline 2006.257.08:44:51.48/k5log//k5ts3_log_newline 2006.257.08:44:52.18/k5log//k5ts4_log_newline 2006.257.08:44:52.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:44:52.20:setupk4=1 2006.257.08:44:52.20$setupk4/echo=on 2006.257.08:44:52.20$setupk4/pcalon 2006.257.08:44:52.20$pcalon/"no phase cal control is implemented here 2006.257.08:44:52.20$setupk4/"tpicd=stop 2006.257.08:44:52.20$setupk4/"rec=synch_on 2006.257.08:44:52.20$setupk4/"rec_mode=128 2006.257.08:44:52.20$setupk4/!* 2006.257.08:44:52.20$setupk4/recpk4 2006.257.08:44:52.21$recpk4/recpatch= 2006.257.08:44:52.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:44:52.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:44:52.21$setupk4/vck44 2006.257.08:44:52.21$vck44/valo=1,524.99 2006.257.08:44:52.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.08:44:52.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.08:44:52.21#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:52.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:52.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:52.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:52.21#ibcon#enter wrdev, iclass 5, count 0 2006.257.08:44:52.21#ibcon#first serial, iclass 5, count 0 2006.257.08:44:52.21#ibcon#enter sib2, iclass 5, count 0 2006.257.08:44:52.21#ibcon#flushed, iclass 5, count 0 2006.257.08:44:52.21#ibcon#about to write, iclass 5, count 0 2006.257.08:44:52.21#ibcon#wrote, iclass 5, count 0 2006.257.08:44:52.21#ibcon#about to read 3, iclass 5, count 0 2006.257.08:44:52.22#ibcon#read 3, iclass 5, count 0 2006.257.08:44:52.22#ibcon#about to read 4, iclass 5, count 0 2006.257.08:44:52.22#ibcon#read 4, iclass 5, count 0 2006.257.08:44:52.22#ibcon#about to read 5, iclass 5, count 0 2006.257.08:44:52.22#ibcon#read 5, iclass 5, count 0 2006.257.08:44:52.22#ibcon#about to read 6, iclass 5, count 0 2006.257.08:44:52.22#ibcon#read 6, iclass 5, count 0 2006.257.08:44:52.22#ibcon#end of sib2, iclass 5, count 0 2006.257.08:44:52.22#ibcon#*mode == 0, iclass 5, count 0 2006.257.08:44:52.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.08:44:52.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:44:52.22#ibcon#*before write, iclass 5, count 0 2006.257.08:44:52.22#ibcon#enter sib2, iclass 5, count 0 2006.257.08:44:52.22#ibcon#flushed, iclass 5, count 0 2006.257.08:44:52.22#ibcon#about to write, iclass 5, count 0 2006.257.08:44:52.22#ibcon#wrote, iclass 5, count 0 2006.257.08:44:52.22#ibcon#about to read 3, iclass 5, count 0 2006.257.08:44:52.27#ibcon#read 3, iclass 5, count 0 2006.257.08:44:52.27#ibcon#about to read 4, iclass 5, count 0 2006.257.08:44:52.27#ibcon#read 4, iclass 5, count 0 2006.257.08:44:52.27#ibcon#about to read 5, iclass 5, count 0 2006.257.08:44:52.27#ibcon#read 5, iclass 5, count 0 2006.257.08:44:52.27#ibcon#about to read 6, iclass 5, count 0 2006.257.08:44:52.27#ibcon#read 6, iclass 5, count 0 2006.257.08:44:52.27#ibcon#end of sib2, iclass 5, count 0 2006.257.08:44:52.27#ibcon#*after write, iclass 5, count 0 2006.257.08:44:52.27#ibcon#*before return 0, iclass 5, count 0 2006.257.08:44:52.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:52.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:52.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.08:44:52.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.08:44:52.27$vck44/va=1,8 2006.257.08:44:52.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.08:44:52.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.08:44:52.27#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:52.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:52.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:52.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:52.27#ibcon#enter wrdev, iclass 7, count 2 2006.257.08:44:52.27#ibcon#first serial, iclass 7, count 2 2006.257.08:44:52.27#ibcon#enter sib2, iclass 7, count 2 2006.257.08:44:52.27#ibcon#flushed, iclass 7, count 2 2006.257.08:44:52.27#ibcon#about to write, iclass 7, count 2 2006.257.08:44:52.27#ibcon#wrote, iclass 7, count 2 2006.257.08:44:52.27#ibcon#about to read 3, iclass 7, count 2 2006.257.08:44:52.29#ibcon#read 3, iclass 7, count 2 2006.257.08:44:52.29#ibcon#about to read 4, iclass 7, count 2 2006.257.08:44:52.29#ibcon#read 4, iclass 7, count 2 2006.257.08:44:52.29#ibcon#about to read 5, iclass 7, count 2 2006.257.08:44:52.29#ibcon#read 5, iclass 7, count 2 2006.257.08:44:52.29#ibcon#about to read 6, iclass 7, count 2 2006.257.08:44:52.29#ibcon#read 6, iclass 7, count 2 2006.257.08:44:52.29#ibcon#end of sib2, iclass 7, count 2 2006.257.08:44:52.29#ibcon#*mode == 0, iclass 7, count 2 2006.257.08:44:52.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.08:44:52.29#ibcon#[25=AT01-08\r\n] 2006.257.08:44:52.29#ibcon#*before write, iclass 7, count 2 2006.257.08:44:52.29#ibcon#enter sib2, iclass 7, count 2 2006.257.08:44:52.29#ibcon#flushed, iclass 7, count 2 2006.257.08:44:52.29#ibcon#about to write, iclass 7, count 2 2006.257.08:44:52.29#ibcon#wrote, iclass 7, count 2 2006.257.08:44:52.29#ibcon#about to read 3, iclass 7, count 2 2006.257.08:44:52.32#ibcon#read 3, iclass 7, count 2 2006.257.08:44:52.32#ibcon#about to read 4, iclass 7, count 2 2006.257.08:44:52.32#ibcon#read 4, iclass 7, count 2 2006.257.08:44:52.32#ibcon#about to read 5, iclass 7, count 2 2006.257.08:44:52.32#ibcon#read 5, iclass 7, count 2 2006.257.08:44:52.32#ibcon#about to read 6, iclass 7, count 2 2006.257.08:44:52.32#ibcon#read 6, iclass 7, count 2 2006.257.08:44:52.32#ibcon#end of sib2, iclass 7, count 2 2006.257.08:44:52.32#ibcon#*after write, iclass 7, count 2 2006.257.08:44:52.32#ibcon#*before return 0, iclass 7, count 2 2006.257.08:44:52.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:52.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:52.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.08:44:52.32#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:52.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:52.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:52.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:52.44#ibcon#enter wrdev, iclass 7, count 0 2006.257.08:44:52.44#ibcon#first serial, iclass 7, count 0 2006.257.08:44:52.44#ibcon#enter sib2, iclass 7, count 0 2006.257.08:44:52.44#ibcon#flushed, iclass 7, count 0 2006.257.08:44:52.44#ibcon#about to write, iclass 7, count 0 2006.257.08:44:52.44#ibcon#wrote, iclass 7, count 0 2006.257.08:44:52.44#ibcon#about to read 3, iclass 7, count 0 2006.257.08:44:52.46#ibcon#read 3, iclass 7, count 0 2006.257.08:44:52.46#ibcon#about to read 4, iclass 7, count 0 2006.257.08:44:52.46#ibcon#read 4, iclass 7, count 0 2006.257.08:44:52.46#ibcon#about to read 5, iclass 7, count 0 2006.257.08:44:52.46#ibcon#read 5, iclass 7, count 0 2006.257.08:44:52.46#ibcon#about to read 6, iclass 7, count 0 2006.257.08:44:52.46#ibcon#read 6, iclass 7, count 0 2006.257.08:44:52.46#ibcon#end of sib2, iclass 7, count 0 2006.257.08:44:52.46#ibcon#*mode == 0, iclass 7, count 0 2006.257.08:44:52.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.08:44:52.46#ibcon#[25=USB\r\n] 2006.257.08:44:52.46#ibcon#*before write, iclass 7, count 0 2006.257.08:44:52.46#ibcon#enter sib2, iclass 7, count 0 2006.257.08:44:52.46#ibcon#flushed, iclass 7, count 0 2006.257.08:44:52.46#ibcon#about to write, iclass 7, count 0 2006.257.08:44:52.46#ibcon#wrote, iclass 7, count 0 2006.257.08:44:52.46#ibcon#about to read 3, iclass 7, count 0 2006.257.08:44:52.49#ibcon#read 3, iclass 7, count 0 2006.257.08:44:52.49#ibcon#about to read 4, iclass 7, count 0 2006.257.08:44:52.49#ibcon#read 4, iclass 7, count 0 2006.257.08:44:52.49#ibcon#about to read 5, iclass 7, count 0 2006.257.08:44:52.49#ibcon#read 5, iclass 7, count 0 2006.257.08:44:52.49#ibcon#about to read 6, iclass 7, count 0 2006.257.08:44:52.49#ibcon#read 6, iclass 7, count 0 2006.257.08:44:52.49#ibcon#end of sib2, iclass 7, count 0 2006.257.08:44:52.49#ibcon#*after write, iclass 7, count 0 2006.257.08:44:52.49#ibcon#*before return 0, iclass 7, count 0 2006.257.08:44:52.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:52.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:52.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.08:44:52.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.08:44:52.49$vck44/valo=2,534.99 2006.257.08:44:52.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.08:44:52.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.08:44:52.49#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:52.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:52.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:52.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:52.49#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:44:52.49#ibcon#first serial, iclass 11, count 0 2006.257.08:44:52.49#ibcon#enter sib2, iclass 11, count 0 2006.257.08:44:52.49#ibcon#flushed, iclass 11, count 0 2006.257.08:44:52.49#ibcon#about to write, iclass 11, count 0 2006.257.08:44:52.49#ibcon#wrote, iclass 11, count 0 2006.257.08:44:52.49#ibcon#about to read 3, iclass 11, count 0 2006.257.08:44:52.51#ibcon#read 3, iclass 11, count 0 2006.257.08:44:52.51#ibcon#about to read 4, iclass 11, count 0 2006.257.08:44:52.51#ibcon#read 4, iclass 11, count 0 2006.257.08:44:52.51#ibcon#about to read 5, iclass 11, count 0 2006.257.08:44:52.51#ibcon#read 5, iclass 11, count 0 2006.257.08:44:52.51#ibcon#about to read 6, iclass 11, count 0 2006.257.08:44:52.51#ibcon#read 6, iclass 11, count 0 2006.257.08:44:52.51#ibcon#end of sib2, iclass 11, count 0 2006.257.08:44:52.51#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:44:52.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:44:52.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:44:52.51#ibcon#*before write, iclass 11, count 0 2006.257.08:44:52.51#ibcon#enter sib2, iclass 11, count 0 2006.257.08:44:52.51#ibcon#flushed, iclass 11, count 0 2006.257.08:44:52.51#ibcon#about to write, iclass 11, count 0 2006.257.08:44:52.51#ibcon#wrote, iclass 11, count 0 2006.257.08:44:52.51#ibcon#about to read 3, iclass 11, count 0 2006.257.08:44:52.55#ibcon#read 3, iclass 11, count 0 2006.257.08:44:52.55#ibcon#about to read 4, iclass 11, count 0 2006.257.08:44:52.55#ibcon#read 4, iclass 11, count 0 2006.257.08:44:52.55#ibcon#about to read 5, iclass 11, count 0 2006.257.08:44:52.55#ibcon#read 5, iclass 11, count 0 2006.257.08:44:52.55#ibcon#about to read 6, iclass 11, count 0 2006.257.08:44:52.55#ibcon#read 6, iclass 11, count 0 2006.257.08:44:52.55#ibcon#end of sib2, iclass 11, count 0 2006.257.08:44:52.55#ibcon#*after write, iclass 11, count 0 2006.257.08:44:52.55#ibcon#*before return 0, iclass 11, count 0 2006.257.08:44:52.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:52.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:52.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:44:52.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:44:52.55$vck44/va=2,7 2006.257.08:44:52.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.08:44:52.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.08:44:52.55#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:52.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:52.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:52.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:52.61#ibcon#enter wrdev, iclass 13, count 2 2006.257.08:44:52.61#ibcon#first serial, iclass 13, count 2 2006.257.08:44:52.61#ibcon#enter sib2, iclass 13, count 2 2006.257.08:44:52.61#ibcon#flushed, iclass 13, count 2 2006.257.08:44:52.61#ibcon#about to write, iclass 13, count 2 2006.257.08:44:52.61#ibcon#wrote, iclass 13, count 2 2006.257.08:44:52.61#ibcon#about to read 3, iclass 13, count 2 2006.257.08:44:52.63#ibcon#read 3, iclass 13, count 2 2006.257.08:44:52.63#ibcon#about to read 4, iclass 13, count 2 2006.257.08:44:52.63#ibcon#read 4, iclass 13, count 2 2006.257.08:44:52.63#ibcon#about to read 5, iclass 13, count 2 2006.257.08:44:52.63#ibcon#read 5, iclass 13, count 2 2006.257.08:44:52.63#ibcon#about to read 6, iclass 13, count 2 2006.257.08:44:52.63#ibcon#read 6, iclass 13, count 2 2006.257.08:44:52.63#ibcon#end of sib2, iclass 13, count 2 2006.257.08:44:52.63#ibcon#*mode == 0, iclass 13, count 2 2006.257.08:44:52.63#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.08:44:52.63#ibcon#[25=AT02-07\r\n] 2006.257.08:44:52.63#ibcon#*before write, iclass 13, count 2 2006.257.08:44:52.63#ibcon#enter sib2, iclass 13, count 2 2006.257.08:44:52.63#ibcon#flushed, iclass 13, count 2 2006.257.08:44:52.63#ibcon#about to write, iclass 13, count 2 2006.257.08:44:52.63#ibcon#wrote, iclass 13, count 2 2006.257.08:44:52.63#ibcon#about to read 3, iclass 13, count 2 2006.257.08:44:52.66#ibcon#read 3, iclass 13, count 2 2006.257.08:44:52.66#ibcon#about to read 4, iclass 13, count 2 2006.257.08:44:52.66#ibcon#read 4, iclass 13, count 2 2006.257.08:44:52.66#ibcon#about to read 5, iclass 13, count 2 2006.257.08:44:52.66#ibcon#read 5, iclass 13, count 2 2006.257.08:44:52.66#ibcon#about to read 6, iclass 13, count 2 2006.257.08:44:52.66#ibcon#read 6, iclass 13, count 2 2006.257.08:44:52.66#ibcon#end of sib2, iclass 13, count 2 2006.257.08:44:52.66#ibcon#*after write, iclass 13, count 2 2006.257.08:44:52.66#ibcon#*before return 0, iclass 13, count 2 2006.257.08:44:52.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:52.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:52.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.08:44:52.66#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:52.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:52.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:52.78#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:52.78#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:44:52.78#ibcon#first serial, iclass 13, count 0 2006.257.08:44:52.78#ibcon#enter sib2, iclass 13, count 0 2006.257.08:44:52.78#ibcon#flushed, iclass 13, count 0 2006.257.08:44:52.78#ibcon#about to write, iclass 13, count 0 2006.257.08:44:52.78#ibcon#wrote, iclass 13, count 0 2006.257.08:44:52.78#ibcon#about to read 3, iclass 13, count 0 2006.257.08:44:52.80#ibcon#read 3, iclass 13, count 0 2006.257.08:44:52.80#ibcon#about to read 4, iclass 13, count 0 2006.257.08:44:52.80#ibcon#read 4, iclass 13, count 0 2006.257.08:44:52.80#ibcon#about to read 5, iclass 13, count 0 2006.257.08:44:52.80#ibcon#read 5, iclass 13, count 0 2006.257.08:44:52.80#ibcon#about to read 6, iclass 13, count 0 2006.257.08:44:52.80#ibcon#read 6, iclass 13, count 0 2006.257.08:44:52.80#ibcon#end of sib2, iclass 13, count 0 2006.257.08:44:52.80#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:44:52.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:44:52.80#ibcon#[25=USB\r\n] 2006.257.08:44:52.80#ibcon#*before write, iclass 13, count 0 2006.257.08:44:52.80#ibcon#enter sib2, iclass 13, count 0 2006.257.08:44:52.80#ibcon#flushed, iclass 13, count 0 2006.257.08:44:52.80#ibcon#about to write, iclass 13, count 0 2006.257.08:44:52.80#ibcon#wrote, iclass 13, count 0 2006.257.08:44:52.80#ibcon#about to read 3, iclass 13, count 0 2006.257.08:44:52.83#ibcon#read 3, iclass 13, count 0 2006.257.08:44:52.83#ibcon#about to read 4, iclass 13, count 0 2006.257.08:44:52.83#ibcon#read 4, iclass 13, count 0 2006.257.08:44:52.83#ibcon#about to read 5, iclass 13, count 0 2006.257.08:44:52.83#ibcon#read 5, iclass 13, count 0 2006.257.08:44:52.83#ibcon#about to read 6, iclass 13, count 0 2006.257.08:44:52.83#ibcon#read 6, iclass 13, count 0 2006.257.08:44:52.83#ibcon#end of sib2, iclass 13, count 0 2006.257.08:44:52.83#ibcon#*after write, iclass 13, count 0 2006.257.08:44:52.83#ibcon#*before return 0, iclass 13, count 0 2006.257.08:44:52.83#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:52.83#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:52.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:44:52.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:44:52.83$vck44/valo=3,564.99 2006.257.08:44:52.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.08:44:52.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.08:44:52.83#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:52.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:52.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:52.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:52.83#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:44:52.83#ibcon#first serial, iclass 15, count 0 2006.257.08:44:52.83#ibcon#enter sib2, iclass 15, count 0 2006.257.08:44:52.83#ibcon#flushed, iclass 15, count 0 2006.257.08:44:52.83#ibcon#about to write, iclass 15, count 0 2006.257.08:44:52.83#ibcon#wrote, iclass 15, count 0 2006.257.08:44:52.83#ibcon#about to read 3, iclass 15, count 0 2006.257.08:44:52.85#ibcon#read 3, iclass 15, count 0 2006.257.08:44:52.85#ibcon#about to read 4, iclass 15, count 0 2006.257.08:44:52.85#ibcon#read 4, iclass 15, count 0 2006.257.08:44:52.85#ibcon#about to read 5, iclass 15, count 0 2006.257.08:44:52.85#ibcon#read 5, iclass 15, count 0 2006.257.08:44:52.85#ibcon#about to read 6, iclass 15, count 0 2006.257.08:44:52.85#ibcon#read 6, iclass 15, count 0 2006.257.08:44:52.85#ibcon#end of sib2, iclass 15, count 0 2006.257.08:44:52.85#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:44:52.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:44:52.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:44:52.85#ibcon#*before write, iclass 15, count 0 2006.257.08:44:52.85#ibcon#enter sib2, iclass 15, count 0 2006.257.08:44:52.85#ibcon#flushed, iclass 15, count 0 2006.257.08:44:52.85#ibcon#about to write, iclass 15, count 0 2006.257.08:44:52.85#ibcon#wrote, iclass 15, count 0 2006.257.08:44:52.85#ibcon#about to read 3, iclass 15, count 0 2006.257.08:44:52.89#ibcon#read 3, iclass 15, count 0 2006.257.08:44:52.89#ibcon#about to read 4, iclass 15, count 0 2006.257.08:44:52.89#ibcon#read 4, iclass 15, count 0 2006.257.08:44:52.89#ibcon#about to read 5, iclass 15, count 0 2006.257.08:44:52.89#ibcon#read 5, iclass 15, count 0 2006.257.08:44:52.89#ibcon#about to read 6, iclass 15, count 0 2006.257.08:44:52.89#ibcon#read 6, iclass 15, count 0 2006.257.08:44:52.89#ibcon#end of sib2, iclass 15, count 0 2006.257.08:44:52.89#ibcon#*after write, iclass 15, count 0 2006.257.08:44:52.89#ibcon#*before return 0, iclass 15, count 0 2006.257.08:44:52.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:52.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:52.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:44:52.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:44:52.89$vck44/va=3,8 2006.257.08:44:52.89#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.08:44:52.89#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.08:44:52.89#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:52.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:52.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:52.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:52.95#ibcon#enter wrdev, iclass 17, count 2 2006.257.08:44:52.95#ibcon#first serial, iclass 17, count 2 2006.257.08:44:52.95#ibcon#enter sib2, iclass 17, count 2 2006.257.08:44:52.95#ibcon#flushed, iclass 17, count 2 2006.257.08:44:52.95#ibcon#about to write, iclass 17, count 2 2006.257.08:44:52.95#ibcon#wrote, iclass 17, count 2 2006.257.08:44:52.95#ibcon#about to read 3, iclass 17, count 2 2006.257.08:44:52.97#ibcon#read 3, iclass 17, count 2 2006.257.08:44:52.97#ibcon#about to read 4, iclass 17, count 2 2006.257.08:44:52.97#ibcon#read 4, iclass 17, count 2 2006.257.08:44:52.97#ibcon#about to read 5, iclass 17, count 2 2006.257.08:44:52.97#ibcon#read 5, iclass 17, count 2 2006.257.08:44:52.97#ibcon#about to read 6, iclass 17, count 2 2006.257.08:44:52.97#ibcon#read 6, iclass 17, count 2 2006.257.08:44:52.97#ibcon#end of sib2, iclass 17, count 2 2006.257.08:44:52.97#ibcon#*mode == 0, iclass 17, count 2 2006.257.08:44:52.97#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.08:44:52.97#ibcon#[25=AT03-08\r\n] 2006.257.08:44:52.97#ibcon#*before write, iclass 17, count 2 2006.257.08:44:52.97#ibcon#enter sib2, iclass 17, count 2 2006.257.08:44:52.97#ibcon#flushed, iclass 17, count 2 2006.257.08:44:52.97#ibcon#about to write, iclass 17, count 2 2006.257.08:44:52.97#ibcon#wrote, iclass 17, count 2 2006.257.08:44:52.97#ibcon#about to read 3, iclass 17, count 2 2006.257.08:44:53.00#ibcon#read 3, iclass 17, count 2 2006.257.08:44:53.00#ibcon#about to read 4, iclass 17, count 2 2006.257.08:44:53.00#ibcon#read 4, iclass 17, count 2 2006.257.08:44:53.00#ibcon#about to read 5, iclass 17, count 2 2006.257.08:44:53.00#ibcon#read 5, iclass 17, count 2 2006.257.08:44:53.00#ibcon#about to read 6, iclass 17, count 2 2006.257.08:44:53.00#ibcon#read 6, iclass 17, count 2 2006.257.08:44:53.00#ibcon#end of sib2, iclass 17, count 2 2006.257.08:44:53.00#ibcon#*after write, iclass 17, count 2 2006.257.08:44:53.00#ibcon#*before return 0, iclass 17, count 2 2006.257.08:44:53.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:53.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:53.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.08:44:53.00#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:53.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:53.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:53.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:53.12#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:44:53.12#ibcon#first serial, iclass 17, count 0 2006.257.08:44:53.12#ibcon#enter sib2, iclass 17, count 0 2006.257.08:44:53.12#ibcon#flushed, iclass 17, count 0 2006.257.08:44:53.12#ibcon#about to write, iclass 17, count 0 2006.257.08:44:53.12#ibcon#wrote, iclass 17, count 0 2006.257.08:44:53.12#ibcon#about to read 3, iclass 17, count 0 2006.257.08:44:53.14#ibcon#read 3, iclass 17, count 0 2006.257.08:44:53.14#ibcon#about to read 4, iclass 17, count 0 2006.257.08:44:53.14#ibcon#read 4, iclass 17, count 0 2006.257.08:44:53.14#ibcon#about to read 5, iclass 17, count 0 2006.257.08:44:53.14#ibcon#read 5, iclass 17, count 0 2006.257.08:44:53.14#ibcon#about to read 6, iclass 17, count 0 2006.257.08:44:53.14#ibcon#read 6, iclass 17, count 0 2006.257.08:44:53.14#ibcon#end of sib2, iclass 17, count 0 2006.257.08:44:53.14#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:44:53.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:44:53.14#ibcon#[25=USB\r\n] 2006.257.08:44:53.14#ibcon#*before write, iclass 17, count 0 2006.257.08:44:53.14#ibcon#enter sib2, iclass 17, count 0 2006.257.08:44:53.14#ibcon#flushed, iclass 17, count 0 2006.257.08:44:53.14#ibcon#about to write, iclass 17, count 0 2006.257.08:44:53.14#ibcon#wrote, iclass 17, count 0 2006.257.08:44:53.14#ibcon#about to read 3, iclass 17, count 0 2006.257.08:44:53.17#ibcon#read 3, iclass 17, count 0 2006.257.08:44:53.17#ibcon#about to read 4, iclass 17, count 0 2006.257.08:44:53.17#ibcon#read 4, iclass 17, count 0 2006.257.08:44:53.17#ibcon#about to read 5, iclass 17, count 0 2006.257.08:44:53.17#ibcon#read 5, iclass 17, count 0 2006.257.08:44:53.17#ibcon#about to read 6, iclass 17, count 0 2006.257.08:44:53.17#ibcon#read 6, iclass 17, count 0 2006.257.08:44:53.17#ibcon#end of sib2, iclass 17, count 0 2006.257.08:44:53.17#ibcon#*after write, iclass 17, count 0 2006.257.08:44:53.17#ibcon#*before return 0, iclass 17, count 0 2006.257.08:44:53.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:53.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:53.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:44:53.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:44:53.17$vck44/valo=4,624.99 2006.257.08:44:53.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.08:44:53.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.08:44:53.17#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:53.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:53.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:53.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:53.17#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:44:53.17#ibcon#first serial, iclass 19, count 0 2006.257.08:44:53.17#ibcon#enter sib2, iclass 19, count 0 2006.257.08:44:53.17#ibcon#flushed, iclass 19, count 0 2006.257.08:44:53.17#ibcon#about to write, iclass 19, count 0 2006.257.08:44:53.17#ibcon#wrote, iclass 19, count 0 2006.257.08:44:53.17#ibcon#about to read 3, iclass 19, count 0 2006.257.08:44:53.19#ibcon#read 3, iclass 19, count 0 2006.257.08:44:53.19#ibcon#about to read 4, iclass 19, count 0 2006.257.08:44:53.19#ibcon#read 4, iclass 19, count 0 2006.257.08:44:53.19#ibcon#about to read 5, iclass 19, count 0 2006.257.08:44:53.19#ibcon#read 5, iclass 19, count 0 2006.257.08:44:53.19#ibcon#about to read 6, iclass 19, count 0 2006.257.08:44:53.19#ibcon#read 6, iclass 19, count 0 2006.257.08:44:53.19#ibcon#end of sib2, iclass 19, count 0 2006.257.08:44:53.19#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:44:53.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:44:53.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:44:53.19#ibcon#*before write, iclass 19, count 0 2006.257.08:44:53.19#ibcon#enter sib2, iclass 19, count 0 2006.257.08:44:53.19#ibcon#flushed, iclass 19, count 0 2006.257.08:44:53.19#ibcon#about to write, iclass 19, count 0 2006.257.08:44:53.19#ibcon#wrote, iclass 19, count 0 2006.257.08:44:53.19#ibcon#about to read 3, iclass 19, count 0 2006.257.08:44:53.23#ibcon#read 3, iclass 19, count 0 2006.257.08:44:53.23#ibcon#about to read 4, iclass 19, count 0 2006.257.08:44:53.23#ibcon#read 4, iclass 19, count 0 2006.257.08:44:53.23#ibcon#about to read 5, iclass 19, count 0 2006.257.08:44:53.23#ibcon#read 5, iclass 19, count 0 2006.257.08:44:53.23#ibcon#about to read 6, iclass 19, count 0 2006.257.08:44:53.23#ibcon#read 6, iclass 19, count 0 2006.257.08:44:53.23#ibcon#end of sib2, iclass 19, count 0 2006.257.08:44:53.23#ibcon#*after write, iclass 19, count 0 2006.257.08:44:53.23#ibcon#*before return 0, iclass 19, count 0 2006.257.08:44:53.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:53.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:53.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:44:53.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:44:53.23$vck44/va=4,7 2006.257.08:44:53.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.08:44:53.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.08:44:53.23#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:53.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:53.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:53.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:53.29#ibcon#enter wrdev, iclass 21, count 2 2006.257.08:44:53.29#ibcon#first serial, iclass 21, count 2 2006.257.08:44:53.29#ibcon#enter sib2, iclass 21, count 2 2006.257.08:44:53.29#ibcon#flushed, iclass 21, count 2 2006.257.08:44:53.29#ibcon#about to write, iclass 21, count 2 2006.257.08:44:53.29#ibcon#wrote, iclass 21, count 2 2006.257.08:44:53.29#ibcon#about to read 3, iclass 21, count 2 2006.257.08:44:53.31#ibcon#read 3, iclass 21, count 2 2006.257.08:44:53.31#ibcon#about to read 4, iclass 21, count 2 2006.257.08:44:53.31#ibcon#read 4, iclass 21, count 2 2006.257.08:44:53.31#ibcon#about to read 5, iclass 21, count 2 2006.257.08:44:53.31#ibcon#read 5, iclass 21, count 2 2006.257.08:44:53.31#ibcon#about to read 6, iclass 21, count 2 2006.257.08:44:53.31#ibcon#read 6, iclass 21, count 2 2006.257.08:44:53.31#ibcon#end of sib2, iclass 21, count 2 2006.257.08:44:53.31#ibcon#*mode == 0, iclass 21, count 2 2006.257.08:44:53.31#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.08:44:53.31#ibcon#[25=AT04-07\r\n] 2006.257.08:44:53.31#ibcon#*before write, iclass 21, count 2 2006.257.08:44:53.31#ibcon#enter sib2, iclass 21, count 2 2006.257.08:44:53.31#ibcon#flushed, iclass 21, count 2 2006.257.08:44:53.31#ibcon#about to write, iclass 21, count 2 2006.257.08:44:53.31#ibcon#wrote, iclass 21, count 2 2006.257.08:44:53.31#ibcon#about to read 3, iclass 21, count 2 2006.257.08:44:53.34#ibcon#read 3, iclass 21, count 2 2006.257.08:44:53.34#ibcon#about to read 4, iclass 21, count 2 2006.257.08:44:53.34#ibcon#read 4, iclass 21, count 2 2006.257.08:44:53.34#ibcon#about to read 5, iclass 21, count 2 2006.257.08:44:53.34#ibcon#read 5, iclass 21, count 2 2006.257.08:44:53.34#ibcon#about to read 6, iclass 21, count 2 2006.257.08:44:53.34#ibcon#read 6, iclass 21, count 2 2006.257.08:44:53.34#ibcon#end of sib2, iclass 21, count 2 2006.257.08:44:53.34#ibcon#*after write, iclass 21, count 2 2006.257.08:44:53.34#ibcon#*before return 0, iclass 21, count 2 2006.257.08:44:53.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:53.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:53.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.08:44:53.34#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:53.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:53.46#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:53.46#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:53.46#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:44:53.46#ibcon#first serial, iclass 21, count 0 2006.257.08:44:53.46#ibcon#enter sib2, iclass 21, count 0 2006.257.08:44:53.46#ibcon#flushed, iclass 21, count 0 2006.257.08:44:53.46#ibcon#about to write, iclass 21, count 0 2006.257.08:44:53.46#ibcon#wrote, iclass 21, count 0 2006.257.08:44:53.46#ibcon#about to read 3, iclass 21, count 0 2006.257.08:44:53.48#ibcon#read 3, iclass 21, count 0 2006.257.08:44:53.48#ibcon#about to read 4, iclass 21, count 0 2006.257.08:44:53.48#ibcon#read 4, iclass 21, count 0 2006.257.08:44:53.48#ibcon#about to read 5, iclass 21, count 0 2006.257.08:44:53.48#ibcon#read 5, iclass 21, count 0 2006.257.08:44:53.48#ibcon#about to read 6, iclass 21, count 0 2006.257.08:44:53.48#ibcon#read 6, iclass 21, count 0 2006.257.08:44:53.48#ibcon#end of sib2, iclass 21, count 0 2006.257.08:44:53.48#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:44:53.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:44:53.48#ibcon#[25=USB\r\n] 2006.257.08:44:53.48#ibcon#*before write, iclass 21, count 0 2006.257.08:44:53.48#ibcon#enter sib2, iclass 21, count 0 2006.257.08:44:53.48#ibcon#flushed, iclass 21, count 0 2006.257.08:44:53.48#ibcon#about to write, iclass 21, count 0 2006.257.08:44:53.48#ibcon#wrote, iclass 21, count 0 2006.257.08:44:53.48#ibcon#about to read 3, iclass 21, count 0 2006.257.08:44:53.51#ibcon#read 3, iclass 21, count 0 2006.257.08:44:53.51#ibcon#about to read 4, iclass 21, count 0 2006.257.08:44:53.51#ibcon#read 4, iclass 21, count 0 2006.257.08:44:53.51#ibcon#about to read 5, iclass 21, count 0 2006.257.08:44:53.51#ibcon#read 5, iclass 21, count 0 2006.257.08:44:53.51#ibcon#about to read 6, iclass 21, count 0 2006.257.08:44:53.51#ibcon#read 6, iclass 21, count 0 2006.257.08:44:53.51#ibcon#end of sib2, iclass 21, count 0 2006.257.08:44:53.51#ibcon#*after write, iclass 21, count 0 2006.257.08:44:53.51#ibcon#*before return 0, iclass 21, count 0 2006.257.08:44:53.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:53.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:53.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:44:53.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:44:53.51$vck44/valo=5,734.99 2006.257.08:44:53.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.08:44:53.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.08:44:53.51#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:53.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:53.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:53.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:53.51#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:44:53.51#ibcon#first serial, iclass 23, count 0 2006.257.08:44:53.51#ibcon#enter sib2, iclass 23, count 0 2006.257.08:44:53.51#ibcon#flushed, iclass 23, count 0 2006.257.08:44:53.51#ibcon#about to write, iclass 23, count 0 2006.257.08:44:53.51#ibcon#wrote, iclass 23, count 0 2006.257.08:44:53.51#ibcon#about to read 3, iclass 23, count 0 2006.257.08:44:53.53#ibcon#read 3, iclass 23, count 0 2006.257.08:44:53.53#ibcon#about to read 4, iclass 23, count 0 2006.257.08:44:53.53#ibcon#read 4, iclass 23, count 0 2006.257.08:44:53.53#ibcon#about to read 5, iclass 23, count 0 2006.257.08:44:53.53#ibcon#read 5, iclass 23, count 0 2006.257.08:44:53.53#ibcon#about to read 6, iclass 23, count 0 2006.257.08:44:53.53#ibcon#read 6, iclass 23, count 0 2006.257.08:44:53.53#ibcon#end of sib2, iclass 23, count 0 2006.257.08:44:53.53#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:44:53.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:44:53.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:44:53.53#ibcon#*before write, iclass 23, count 0 2006.257.08:44:53.53#ibcon#enter sib2, iclass 23, count 0 2006.257.08:44:53.53#ibcon#flushed, iclass 23, count 0 2006.257.08:44:53.53#ibcon#about to write, iclass 23, count 0 2006.257.08:44:53.53#ibcon#wrote, iclass 23, count 0 2006.257.08:44:53.53#ibcon#about to read 3, iclass 23, count 0 2006.257.08:44:53.57#ibcon#read 3, iclass 23, count 0 2006.257.08:44:53.57#ibcon#about to read 4, iclass 23, count 0 2006.257.08:44:53.57#ibcon#read 4, iclass 23, count 0 2006.257.08:44:53.57#ibcon#about to read 5, iclass 23, count 0 2006.257.08:44:53.57#ibcon#read 5, iclass 23, count 0 2006.257.08:44:53.57#ibcon#about to read 6, iclass 23, count 0 2006.257.08:44:53.57#ibcon#read 6, iclass 23, count 0 2006.257.08:44:53.57#ibcon#end of sib2, iclass 23, count 0 2006.257.08:44:53.57#ibcon#*after write, iclass 23, count 0 2006.257.08:44:53.57#ibcon#*before return 0, iclass 23, count 0 2006.257.08:44:53.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:53.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:53.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:44:53.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:44:53.57$vck44/va=5,4 2006.257.08:44:53.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.08:44:53.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.08:44:53.57#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:53.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:53.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:53.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:53.63#ibcon#enter wrdev, iclass 25, count 2 2006.257.08:44:53.63#ibcon#first serial, iclass 25, count 2 2006.257.08:44:53.63#ibcon#enter sib2, iclass 25, count 2 2006.257.08:44:53.63#ibcon#flushed, iclass 25, count 2 2006.257.08:44:53.63#ibcon#about to write, iclass 25, count 2 2006.257.08:44:53.63#ibcon#wrote, iclass 25, count 2 2006.257.08:44:53.63#ibcon#about to read 3, iclass 25, count 2 2006.257.08:44:53.65#ibcon#read 3, iclass 25, count 2 2006.257.08:44:53.65#ibcon#about to read 4, iclass 25, count 2 2006.257.08:44:53.65#ibcon#read 4, iclass 25, count 2 2006.257.08:44:53.65#ibcon#about to read 5, iclass 25, count 2 2006.257.08:44:53.65#ibcon#read 5, iclass 25, count 2 2006.257.08:44:53.65#ibcon#about to read 6, iclass 25, count 2 2006.257.08:44:53.65#ibcon#read 6, iclass 25, count 2 2006.257.08:44:53.65#ibcon#end of sib2, iclass 25, count 2 2006.257.08:44:53.65#ibcon#*mode == 0, iclass 25, count 2 2006.257.08:44:53.65#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.08:44:53.65#ibcon#[25=AT05-04\r\n] 2006.257.08:44:53.65#ibcon#*before write, iclass 25, count 2 2006.257.08:44:53.65#ibcon#enter sib2, iclass 25, count 2 2006.257.08:44:53.65#ibcon#flushed, iclass 25, count 2 2006.257.08:44:53.65#ibcon#about to write, iclass 25, count 2 2006.257.08:44:53.65#ibcon#wrote, iclass 25, count 2 2006.257.08:44:53.65#ibcon#about to read 3, iclass 25, count 2 2006.257.08:44:53.68#ibcon#read 3, iclass 25, count 2 2006.257.08:44:53.68#ibcon#about to read 4, iclass 25, count 2 2006.257.08:44:53.68#ibcon#read 4, iclass 25, count 2 2006.257.08:44:53.68#ibcon#about to read 5, iclass 25, count 2 2006.257.08:44:53.68#ibcon#read 5, iclass 25, count 2 2006.257.08:44:53.68#ibcon#about to read 6, iclass 25, count 2 2006.257.08:44:53.68#ibcon#read 6, iclass 25, count 2 2006.257.08:44:53.68#ibcon#end of sib2, iclass 25, count 2 2006.257.08:44:53.68#ibcon#*after write, iclass 25, count 2 2006.257.08:44:53.68#ibcon#*before return 0, iclass 25, count 2 2006.257.08:44:53.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:53.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:53.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.08:44:53.68#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:53.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:53.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:53.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:53.80#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:44:53.80#ibcon#first serial, iclass 25, count 0 2006.257.08:44:53.80#ibcon#enter sib2, iclass 25, count 0 2006.257.08:44:53.80#ibcon#flushed, iclass 25, count 0 2006.257.08:44:53.80#ibcon#about to write, iclass 25, count 0 2006.257.08:44:53.80#ibcon#wrote, iclass 25, count 0 2006.257.08:44:53.80#ibcon#about to read 3, iclass 25, count 0 2006.257.08:44:53.82#ibcon#read 3, iclass 25, count 0 2006.257.08:44:53.82#ibcon#about to read 4, iclass 25, count 0 2006.257.08:44:53.82#ibcon#read 4, iclass 25, count 0 2006.257.08:44:53.82#ibcon#about to read 5, iclass 25, count 0 2006.257.08:44:53.82#ibcon#read 5, iclass 25, count 0 2006.257.08:44:53.82#ibcon#about to read 6, iclass 25, count 0 2006.257.08:44:53.82#ibcon#read 6, iclass 25, count 0 2006.257.08:44:53.82#ibcon#end of sib2, iclass 25, count 0 2006.257.08:44:53.82#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:44:53.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:44:53.82#ibcon#[25=USB\r\n] 2006.257.08:44:53.82#ibcon#*before write, iclass 25, count 0 2006.257.08:44:53.82#ibcon#enter sib2, iclass 25, count 0 2006.257.08:44:53.82#ibcon#flushed, iclass 25, count 0 2006.257.08:44:53.82#ibcon#about to write, iclass 25, count 0 2006.257.08:44:53.82#ibcon#wrote, iclass 25, count 0 2006.257.08:44:53.82#ibcon#about to read 3, iclass 25, count 0 2006.257.08:44:53.85#ibcon#read 3, iclass 25, count 0 2006.257.08:44:53.85#ibcon#about to read 4, iclass 25, count 0 2006.257.08:44:53.85#ibcon#read 4, iclass 25, count 0 2006.257.08:44:53.85#ibcon#about to read 5, iclass 25, count 0 2006.257.08:44:53.85#ibcon#read 5, iclass 25, count 0 2006.257.08:44:53.85#ibcon#about to read 6, iclass 25, count 0 2006.257.08:44:53.85#ibcon#read 6, iclass 25, count 0 2006.257.08:44:53.85#ibcon#end of sib2, iclass 25, count 0 2006.257.08:44:53.85#ibcon#*after write, iclass 25, count 0 2006.257.08:44:53.85#ibcon#*before return 0, iclass 25, count 0 2006.257.08:44:53.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:53.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:53.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:44:53.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:44:53.85$vck44/valo=6,814.99 2006.257.08:44:53.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.08:44:53.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.08:44:53.85#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:53.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:53.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:53.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:53.85#ibcon#enter wrdev, iclass 27, count 0 2006.257.08:44:53.85#ibcon#first serial, iclass 27, count 0 2006.257.08:44:53.85#ibcon#enter sib2, iclass 27, count 0 2006.257.08:44:53.85#ibcon#flushed, iclass 27, count 0 2006.257.08:44:53.85#ibcon#about to write, iclass 27, count 0 2006.257.08:44:53.85#ibcon#wrote, iclass 27, count 0 2006.257.08:44:53.85#ibcon#about to read 3, iclass 27, count 0 2006.257.08:44:53.87#ibcon#read 3, iclass 27, count 0 2006.257.08:44:53.87#ibcon#about to read 4, iclass 27, count 0 2006.257.08:44:53.87#ibcon#read 4, iclass 27, count 0 2006.257.08:44:53.87#ibcon#about to read 5, iclass 27, count 0 2006.257.08:44:53.87#ibcon#read 5, iclass 27, count 0 2006.257.08:44:53.87#ibcon#about to read 6, iclass 27, count 0 2006.257.08:44:53.87#ibcon#read 6, iclass 27, count 0 2006.257.08:44:53.87#ibcon#end of sib2, iclass 27, count 0 2006.257.08:44:53.87#ibcon#*mode == 0, iclass 27, count 0 2006.257.08:44:53.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.08:44:53.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:44:53.87#ibcon#*before write, iclass 27, count 0 2006.257.08:44:53.87#ibcon#enter sib2, iclass 27, count 0 2006.257.08:44:53.87#ibcon#flushed, iclass 27, count 0 2006.257.08:44:53.87#ibcon#about to write, iclass 27, count 0 2006.257.08:44:53.87#ibcon#wrote, iclass 27, count 0 2006.257.08:44:53.87#ibcon#about to read 3, iclass 27, count 0 2006.257.08:44:53.91#ibcon#read 3, iclass 27, count 0 2006.257.08:44:53.91#ibcon#about to read 4, iclass 27, count 0 2006.257.08:44:53.91#ibcon#read 4, iclass 27, count 0 2006.257.08:44:53.91#ibcon#about to read 5, iclass 27, count 0 2006.257.08:44:53.91#ibcon#read 5, iclass 27, count 0 2006.257.08:44:53.91#ibcon#about to read 6, iclass 27, count 0 2006.257.08:44:53.91#ibcon#read 6, iclass 27, count 0 2006.257.08:44:53.91#ibcon#end of sib2, iclass 27, count 0 2006.257.08:44:53.91#ibcon#*after write, iclass 27, count 0 2006.257.08:44:53.91#ibcon#*before return 0, iclass 27, count 0 2006.257.08:44:53.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:53.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:53.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.08:44:53.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.08:44:53.91$vck44/va=6,4 2006.257.08:44:53.91#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.08:44:53.91#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.08:44:53.91#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:53.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:53.96#abcon#<5=/14 1.1 2.0 20.44 921013.1\r\n> 2006.257.08:44:53.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:53.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:53.97#ibcon#enter wrdev, iclass 29, count 2 2006.257.08:44:53.97#ibcon#first serial, iclass 29, count 2 2006.257.08:44:53.97#ibcon#enter sib2, iclass 29, count 2 2006.257.08:44:53.97#ibcon#flushed, iclass 29, count 2 2006.257.08:44:53.97#ibcon#about to write, iclass 29, count 2 2006.257.08:44:53.97#ibcon#wrote, iclass 29, count 2 2006.257.08:44:53.97#ibcon#about to read 3, iclass 29, count 2 2006.257.08:44:53.98#abcon#{5=INTERFACE CLEAR} 2006.257.08:44:53.99#ibcon#read 3, iclass 29, count 2 2006.257.08:44:53.99#ibcon#about to read 4, iclass 29, count 2 2006.257.08:44:53.99#ibcon#read 4, iclass 29, count 2 2006.257.08:44:53.99#ibcon#about to read 5, iclass 29, count 2 2006.257.08:44:53.99#ibcon#read 5, iclass 29, count 2 2006.257.08:44:53.99#ibcon#about to read 6, iclass 29, count 2 2006.257.08:44:53.99#ibcon#read 6, iclass 29, count 2 2006.257.08:44:53.99#ibcon#end of sib2, iclass 29, count 2 2006.257.08:44:53.99#ibcon#*mode == 0, iclass 29, count 2 2006.257.08:44:53.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.08:44:53.99#ibcon#[25=AT06-04\r\n] 2006.257.08:44:53.99#ibcon#*before write, iclass 29, count 2 2006.257.08:44:53.99#ibcon#enter sib2, iclass 29, count 2 2006.257.08:44:53.99#ibcon#flushed, iclass 29, count 2 2006.257.08:44:53.99#ibcon#about to write, iclass 29, count 2 2006.257.08:44:53.99#ibcon#wrote, iclass 29, count 2 2006.257.08:44:53.99#ibcon#about to read 3, iclass 29, count 2 2006.257.08:44:54.02#ibcon#read 3, iclass 29, count 2 2006.257.08:44:54.02#ibcon#about to read 4, iclass 29, count 2 2006.257.08:44:54.02#ibcon#read 4, iclass 29, count 2 2006.257.08:44:54.02#ibcon#about to read 5, iclass 29, count 2 2006.257.08:44:54.02#ibcon#read 5, iclass 29, count 2 2006.257.08:44:54.02#ibcon#about to read 6, iclass 29, count 2 2006.257.08:44:54.02#ibcon#read 6, iclass 29, count 2 2006.257.08:44:54.02#ibcon#end of sib2, iclass 29, count 2 2006.257.08:44:54.02#ibcon#*after write, iclass 29, count 2 2006.257.08:44:54.02#ibcon#*before return 0, iclass 29, count 2 2006.257.08:44:54.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:54.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:54.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.08:44:54.02#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:54.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:54.04#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:44:54.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:54.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:54.14#ibcon#enter wrdev, iclass 29, count 0 2006.257.08:44:54.14#ibcon#first serial, iclass 29, count 0 2006.257.08:44:54.14#ibcon#enter sib2, iclass 29, count 0 2006.257.08:44:54.14#ibcon#flushed, iclass 29, count 0 2006.257.08:44:54.14#ibcon#about to write, iclass 29, count 0 2006.257.08:44:54.14#ibcon#wrote, iclass 29, count 0 2006.257.08:44:54.14#ibcon#about to read 3, iclass 29, count 0 2006.257.08:44:54.16#ibcon#read 3, iclass 29, count 0 2006.257.08:44:54.16#ibcon#about to read 4, iclass 29, count 0 2006.257.08:44:54.16#ibcon#read 4, iclass 29, count 0 2006.257.08:44:54.16#ibcon#about to read 5, iclass 29, count 0 2006.257.08:44:54.16#ibcon#read 5, iclass 29, count 0 2006.257.08:44:54.16#ibcon#about to read 6, iclass 29, count 0 2006.257.08:44:54.16#ibcon#read 6, iclass 29, count 0 2006.257.08:44:54.16#ibcon#end of sib2, iclass 29, count 0 2006.257.08:44:54.16#ibcon#*mode == 0, iclass 29, count 0 2006.257.08:44:54.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.08:44:54.16#ibcon#[25=USB\r\n] 2006.257.08:44:54.16#ibcon#*before write, iclass 29, count 0 2006.257.08:44:54.16#ibcon#enter sib2, iclass 29, count 0 2006.257.08:44:54.16#ibcon#flushed, iclass 29, count 0 2006.257.08:44:54.16#ibcon#about to write, iclass 29, count 0 2006.257.08:44:54.16#ibcon#wrote, iclass 29, count 0 2006.257.08:44:54.16#ibcon#about to read 3, iclass 29, count 0 2006.257.08:44:54.19#ibcon#read 3, iclass 29, count 0 2006.257.08:44:54.19#ibcon#about to read 4, iclass 29, count 0 2006.257.08:44:54.19#ibcon#read 4, iclass 29, count 0 2006.257.08:44:54.19#ibcon#about to read 5, iclass 29, count 0 2006.257.08:44:54.19#ibcon#read 5, iclass 29, count 0 2006.257.08:44:54.19#ibcon#about to read 6, iclass 29, count 0 2006.257.08:44:54.19#ibcon#read 6, iclass 29, count 0 2006.257.08:44:54.19#ibcon#end of sib2, iclass 29, count 0 2006.257.08:44:54.19#ibcon#*after write, iclass 29, count 0 2006.257.08:44:54.19#ibcon#*before return 0, iclass 29, count 0 2006.257.08:44:54.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:54.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:54.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.08:44:54.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.08:44:54.19$vck44/valo=7,864.99 2006.257.08:44:54.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.08:44:54.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.08:44:54.19#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:54.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:54.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:54.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:54.19#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:44:54.19#ibcon#first serial, iclass 35, count 0 2006.257.08:44:54.19#ibcon#enter sib2, iclass 35, count 0 2006.257.08:44:54.19#ibcon#flushed, iclass 35, count 0 2006.257.08:44:54.19#ibcon#about to write, iclass 35, count 0 2006.257.08:44:54.19#ibcon#wrote, iclass 35, count 0 2006.257.08:44:54.19#ibcon#about to read 3, iclass 35, count 0 2006.257.08:44:54.21#ibcon#read 3, iclass 35, count 0 2006.257.08:44:54.21#ibcon#about to read 4, iclass 35, count 0 2006.257.08:44:54.21#ibcon#read 4, iclass 35, count 0 2006.257.08:44:54.21#ibcon#about to read 5, iclass 35, count 0 2006.257.08:44:54.21#ibcon#read 5, iclass 35, count 0 2006.257.08:44:54.21#ibcon#about to read 6, iclass 35, count 0 2006.257.08:44:54.21#ibcon#read 6, iclass 35, count 0 2006.257.08:44:54.21#ibcon#end of sib2, iclass 35, count 0 2006.257.08:44:54.21#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:44:54.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:44:54.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:44:54.21#ibcon#*before write, iclass 35, count 0 2006.257.08:44:54.21#ibcon#enter sib2, iclass 35, count 0 2006.257.08:44:54.21#ibcon#flushed, iclass 35, count 0 2006.257.08:44:54.21#ibcon#about to write, iclass 35, count 0 2006.257.08:44:54.21#ibcon#wrote, iclass 35, count 0 2006.257.08:44:54.21#ibcon#about to read 3, iclass 35, count 0 2006.257.08:44:54.25#ibcon#read 3, iclass 35, count 0 2006.257.08:44:54.25#ibcon#about to read 4, iclass 35, count 0 2006.257.08:44:54.25#ibcon#read 4, iclass 35, count 0 2006.257.08:44:54.25#ibcon#about to read 5, iclass 35, count 0 2006.257.08:44:54.25#ibcon#read 5, iclass 35, count 0 2006.257.08:44:54.25#ibcon#about to read 6, iclass 35, count 0 2006.257.08:44:54.25#ibcon#read 6, iclass 35, count 0 2006.257.08:44:54.25#ibcon#end of sib2, iclass 35, count 0 2006.257.08:44:54.25#ibcon#*after write, iclass 35, count 0 2006.257.08:44:54.25#ibcon#*before return 0, iclass 35, count 0 2006.257.08:44:54.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:54.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:54.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:44:54.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:44:54.25$vck44/va=7,4 2006.257.08:44:54.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.08:44:54.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.08:44:54.25#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:54.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:54.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:54.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:54.31#ibcon#enter wrdev, iclass 37, count 2 2006.257.08:44:54.31#ibcon#first serial, iclass 37, count 2 2006.257.08:44:54.31#ibcon#enter sib2, iclass 37, count 2 2006.257.08:44:54.31#ibcon#flushed, iclass 37, count 2 2006.257.08:44:54.31#ibcon#about to write, iclass 37, count 2 2006.257.08:44:54.31#ibcon#wrote, iclass 37, count 2 2006.257.08:44:54.31#ibcon#about to read 3, iclass 37, count 2 2006.257.08:44:54.33#ibcon#read 3, iclass 37, count 2 2006.257.08:44:54.33#ibcon#about to read 4, iclass 37, count 2 2006.257.08:44:54.33#ibcon#read 4, iclass 37, count 2 2006.257.08:44:54.33#ibcon#about to read 5, iclass 37, count 2 2006.257.08:44:54.33#ibcon#read 5, iclass 37, count 2 2006.257.08:44:54.33#ibcon#about to read 6, iclass 37, count 2 2006.257.08:44:54.33#ibcon#read 6, iclass 37, count 2 2006.257.08:44:54.33#ibcon#end of sib2, iclass 37, count 2 2006.257.08:44:54.33#ibcon#*mode == 0, iclass 37, count 2 2006.257.08:44:54.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.08:44:54.33#ibcon#[25=AT07-04\r\n] 2006.257.08:44:54.33#ibcon#*before write, iclass 37, count 2 2006.257.08:44:54.33#ibcon#enter sib2, iclass 37, count 2 2006.257.08:44:54.33#ibcon#flushed, iclass 37, count 2 2006.257.08:44:54.33#ibcon#about to write, iclass 37, count 2 2006.257.08:44:54.33#ibcon#wrote, iclass 37, count 2 2006.257.08:44:54.33#ibcon#about to read 3, iclass 37, count 2 2006.257.08:44:54.36#ibcon#read 3, iclass 37, count 2 2006.257.08:44:54.36#ibcon#about to read 4, iclass 37, count 2 2006.257.08:44:54.36#ibcon#read 4, iclass 37, count 2 2006.257.08:44:54.36#ibcon#about to read 5, iclass 37, count 2 2006.257.08:44:54.36#ibcon#read 5, iclass 37, count 2 2006.257.08:44:54.36#ibcon#about to read 6, iclass 37, count 2 2006.257.08:44:54.36#ibcon#read 6, iclass 37, count 2 2006.257.08:44:54.36#ibcon#end of sib2, iclass 37, count 2 2006.257.08:44:54.36#ibcon#*after write, iclass 37, count 2 2006.257.08:44:54.36#ibcon#*before return 0, iclass 37, count 2 2006.257.08:44:54.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:54.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:54.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.08:44:54.36#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:54.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:54.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:54.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:54.48#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:44:54.48#ibcon#first serial, iclass 37, count 0 2006.257.08:44:54.48#ibcon#enter sib2, iclass 37, count 0 2006.257.08:44:54.48#ibcon#flushed, iclass 37, count 0 2006.257.08:44:54.48#ibcon#about to write, iclass 37, count 0 2006.257.08:44:54.48#ibcon#wrote, iclass 37, count 0 2006.257.08:44:54.48#ibcon#about to read 3, iclass 37, count 0 2006.257.08:44:54.50#ibcon#read 3, iclass 37, count 0 2006.257.08:44:54.50#ibcon#about to read 4, iclass 37, count 0 2006.257.08:44:54.50#ibcon#read 4, iclass 37, count 0 2006.257.08:44:54.50#ibcon#about to read 5, iclass 37, count 0 2006.257.08:44:54.50#ibcon#read 5, iclass 37, count 0 2006.257.08:44:54.50#ibcon#about to read 6, iclass 37, count 0 2006.257.08:44:54.50#ibcon#read 6, iclass 37, count 0 2006.257.08:44:54.50#ibcon#end of sib2, iclass 37, count 0 2006.257.08:44:54.50#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:44:54.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:44:54.50#ibcon#[25=USB\r\n] 2006.257.08:44:54.50#ibcon#*before write, iclass 37, count 0 2006.257.08:44:54.50#ibcon#enter sib2, iclass 37, count 0 2006.257.08:44:54.50#ibcon#flushed, iclass 37, count 0 2006.257.08:44:54.50#ibcon#about to write, iclass 37, count 0 2006.257.08:44:54.50#ibcon#wrote, iclass 37, count 0 2006.257.08:44:54.50#ibcon#about to read 3, iclass 37, count 0 2006.257.08:44:54.53#ibcon#read 3, iclass 37, count 0 2006.257.08:44:54.53#ibcon#about to read 4, iclass 37, count 0 2006.257.08:44:54.53#ibcon#read 4, iclass 37, count 0 2006.257.08:44:54.53#ibcon#about to read 5, iclass 37, count 0 2006.257.08:44:54.53#ibcon#read 5, iclass 37, count 0 2006.257.08:44:54.53#ibcon#about to read 6, iclass 37, count 0 2006.257.08:44:54.53#ibcon#read 6, iclass 37, count 0 2006.257.08:44:54.53#ibcon#end of sib2, iclass 37, count 0 2006.257.08:44:54.53#ibcon#*after write, iclass 37, count 0 2006.257.08:44:54.53#ibcon#*before return 0, iclass 37, count 0 2006.257.08:44:54.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:54.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:54.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:44:54.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:44:54.53$vck44/valo=8,884.99 2006.257.08:44:54.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.08:44:54.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.08:44:54.53#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:54.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:54.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:54.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:54.53#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:44:54.53#ibcon#first serial, iclass 39, count 0 2006.257.08:44:54.53#ibcon#enter sib2, iclass 39, count 0 2006.257.08:44:54.53#ibcon#flushed, iclass 39, count 0 2006.257.08:44:54.53#ibcon#about to write, iclass 39, count 0 2006.257.08:44:54.53#ibcon#wrote, iclass 39, count 0 2006.257.08:44:54.53#ibcon#about to read 3, iclass 39, count 0 2006.257.08:44:54.55#ibcon#read 3, iclass 39, count 0 2006.257.08:44:54.55#ibcon#about to read 4, iclass 39, count 0 2006.257.08:44:54.55#ibcon#read 4, iclass 39, count 0 2006.257.08:44:54.55#ibcon#about to read 5, iclass 39, count 0 2006.257.08:44:54.55#ibcon#read 5, iclass 39, count 0 2006.257.08:44:54.55#ibcon#about to read 6, iclass 39, count 0 2006.257.08:44:54.55#ibcon#read 6, iclass 39, count 0 2006.257.08:44:54.55#ibcon#end of sib2, iclass 39, count 0 2006.257.08:44:54.55#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:44:54.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:44:54.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:44:54.55#ibcon#*before write, iclass 39, count 0 2006.257.08:44:54.55#ibcon#enter sib2, iclass 39, count 0 2006.257.08:44:54.55#ibcon#flushed, iclass 39, count 0 2006.257.08:44:54.55#ibcon#about to write, iclass 39, count 0 2006.257.08:44:54.55#ibcon#wrote, iclass 39, count 0 2006.257.08:44:54.55#ibcon#about to read 3, iclass 39, count 0 2006.257.08:44:54.59#ibcon#read 3, iclass 39, count 0 2006.257.08:44:54.59#ibcon#about to read 4, iclass 39, count 0 2006.257.08:44:54.59#ibcon#read 4, iclass 39, count 0 2006.257.08:44:54.59#ibcon#about to read 5, iclass 39, count 0 2006.257.08:44:54.59#ibcon#read 5, iclass 39, count 0 2006.257.08:44:54.59#ibcon#about to read 6, iclass 39, count 0 2006.257.08:44:54.59#ibcon#read 6, iclass 39, count 0 2006.257.08:44:54.59#ibcon#end of sib2, iclass 39, count 0 2006.257.08:44:54.59#ibcon#*after write, iclass 39, count 0 2006.257.08:44:54.59#ibcon#*before return 0, iclass 39, count 0 2006.257.08:44:54.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:54.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:54.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:44:54.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:44:54.59$vck44/va=8,4 2006.257.08:44:54.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.08:44:54.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.08:44:54.59#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:54.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:44:54.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:44:54.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:44:54.65#ibcon#enter wrdev, iclass 3, count 2 2006.257.08:44:54.65#ibcon#first serial, iclass 3, count 2 2006.257.08:44:54.65#ibcon#enter sib2, iclass 3, count 2 2006.257.08:44:54.65#ibcon#flushed, iclass 3, count 2 2006.257.08:44:54.65#ibcon#about to write, iclass 3, count 2 2006.257.08:44:54.65#ibcon#wrote, iclass 3, count 2 2006.257.08:44:54.65#ibcon#about to read 3, iclass 3, count 2 2006.257.08:44:54.67#ibcon#read 3, iclass 3, count 2 2006.257.08:44:54.67#ibcon#about to read 4, iclass 3, count 2 2006.257.08:44:54.67#ibcon#read 4, iclass 3, count 2 2006.257.08:44:54.67#ibcon#about to read 5, iclass 3, count 2 2006.257.08:44:54.67#ibcon#read 5, iclass 3, count 2 2006.257.08:44:54.67#ibcon#about to read 6, iclass 3, count 2 2006.257.08:44:54.67#ibcon#read 6, iclass 3, count 2 2006.257.08:44:54.67#ibcon#end of sib2, iclass 3, count 2 2006.257.08:44:54.67#ibcon#*mode == 0, iclass 3, count 2 2006.257.08:44:54.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.08:44:54.67#ibcon#[25=AT08-04\r\n] 2006.257.08:44:54.67#ibcon#*before write, iclass 3, count 2 2006.257.08:44:54.67#ibcon#enter sib2, iclass 3, count 2 2006.257.08:44:54.67#ibcon#flushed, iclass 3, count 2 2006.257.08:44:54.67#ibcon#about to write, iclass 3, count 2 2006.257.08:44:54.67#ibcon#wrote, iclass 3, count 2 2006.257.08:44:54.67#ibcon#about to read 3, iclass 3, count 2 2006.257.08:44:54.70#ibcon#read 3, iclass 3, count 2 2006.257.08:44:54.70#ibcon#about to read 4, iclass 3, count 2 2006.257.08:44:54.70#ibcon#read 4, iclass 3, count 2 2006.257.08:44:54.70#ibcon#about to read 5, iclass 3, count 2 2006.257.08:44:54.70#ibcon#read 5, iclass 3, count 2 2006.257.08:44:54.70#ibcon#about to read 6, iclass 3, count 2 2006.257.08:44:54.70#ibcon#read 6, iclass 3, count 2 2006.257.08:44:54.70#ibcon#end of sib2, iclass 3, count 2 2006.257.08:44:54.70#ibcon#*after write, iclass 3, count 2 2006.257.08:44:54.70#ibcon#*before return 0, iclass 3, count 2 2006.257.08:44:54.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:44:54.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.08:44:54.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.08:44:54.70#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:54.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:44:54.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:44:54.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:44:54.82#ibcon#enter wrdev, iclass 3, count 0 2006.257.08:44:54.82#ibcon#first serial, iclass 3, count 0 2006.257.08:44:54.82#ibcon#enter sib2, iclass 3, count 0 2006.257.08:44:54.82#ibcon#flushed, iclass 3, count 0 2006.257.08:44:54.82#ibcon#about to write, iclass 3, count 0 2006.257.08:44:54.82#ibcon#wrote, iclass 3, count 0 2006.257.08:44:54.82#ibcon#about to read 3, iclass 3, count 0 2006.257.08:44:54.84#ibcon#read 3, iclass 3, count 0 2006.257.08:44:54.84#ibcon#about to read 4, iclass 3, count 0 2006.257.08:44:54.84#ibcon#read 4, iclass 3, count 0 2006.257.08:44:54.84#ibcon#about to read 5, iclass 3, count 0 2006.257.08:44:54.84#ibcon#read 5, iclass 3, count 0 2006.257.08:44:54.84#ibcon#about to read 6, iclass 3, count 0 2006.257.08:44:54.84#ibcon#read 6, iclass 3, count 0 2006.257.08:44:54.84#ibcon#end of sib2, iclass 3, count 0 2006.257.08:44:54.84#ibcon#*mode == 0, iclass 3, count 0 2006.257.08:44:54.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.08:44:54.84#ibcon#[25=USB\r\n] 2006.257.08:44:54.84#ibcon#*before write, iclass 3, count 0 2006.257.08:44:54.84#ibcon#enter sib2, iclass 3, count 0 2006.257.08:44:54.84#ibcon#flushed, iclass 3, count 0 2006.257.08:44:54.84#ibcon#about to write, iclass 3, count 0 2006.257.08:44:54.84#ibcon#wrote, iclass 3, count 0 2006.257.08:44:54.84#ibcon#about to read 3, iclass 3, count 0 2006.257.08:44:54.87#ibcon#read 3, iclass 3, count 0 2006.257.08:44:54.87#ibcon#about to read 4, iclass 3, count 0 2006.257.08:44:54.87#ibcon#read 4, iclass 3, count 0 2006.257.08:44:54.87#ibcon#about to read 5, iclass 3, count 0 2006.257.08:44:54.87#ibcon#read 5, iclass 3, count 0 2006.257.08:44:54.87#ibcon#about to read 6, iclass 3, count 0 2006.257.08:44:54.87#ibcon#read 6, iclass 3, count 0 2006.257.08:44:54.87#ibcon#end of sib2, iclass 3, count 0 2006.257.08:44:54.87#ibcon#*after write, iclass 3, count 0 2006.257.08:44:54.87#ibcon#*before return 0, iclass 3, count 0 2006.257.08:44:54.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:44:54.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.08:44:54.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.08:44:54.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.08:44:54.87$vck44/vblo=1,629.99 2006.257.08:44:54.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.08:44:54.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.08:44:54.87#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:54.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:54.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:54.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:54.87#ibcon#enter wrdev, iclass 5, count 0 2006.257.08:44:54.87#ibcon#first serial, iclass 5, count 0 2006.257.08:44:54.87#ibcon#enter sib2, iclass 5, count 0 2006.257.08:44:54.87#ibcon#flushed, iclass 5, count 0 2006.257.08:44:54.87#ibcon#about to write, iclass 5, count 0 2006.257.08:44:54.87#ibcon#wrote, iclass 5, count 0 2006.257.08:44:54.87#ibcon#about to read 3, iclass 5, count 0 2006.257.08:44:54.89#ibcon#read 3, iclass 5, count 0 2006.257.08:44:54.89#ibcon#about to read 4, iclass 5, count 0 2006.257.08:44:54.89#ibcon#read 4, iclass 5, count 0 2006.257.08:44:54.89#ibcon#about to read 5, iclass 5, count 0 2006.257.08:44:54.89#ibcon#read 5, iclass 5, count 0 2006.257.08:44:54.89#ibcon#about to read 6, iclass 5, count 0 2006.257.08:44:54.89#ibcon#read 6, iclass 5, count 0 2006.257.08:44:54.89#ibcon#end of sib2, iclass 5, count 0 2006.257.08:44:54.89#ibcon#*mode == 0, iclass 5, count 0 2006.257.08:44:54.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.08:44:54.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:44:54.89#ibcon#*before write, iclass 5, count 0 2006.257.08:44:54.89#ibcon#enter sib2, iclass 5, count 0 2006.257.08:44:54.89#ibcon#flushed, iclass 5, count 0 2006.257.08:44:54.89#ibcon#about to write, iclass 5, count 0 2006.257.08:44:54.89#ibcon#wrote, iclass 5, count 0 2006.257.08:44:54.89#ibcon#about to read 3, iclass 5, count 0 2006.257.08:44:54.93#ibcon#read 3, iclass 5, count 0 2006.257.08:44:54.93#ibcon#about to read 4, iclass 5, count 0 2006.257.08:44:54.93#ibcon#read 4, iclass 5, count 0 2006.257.08:44:54.93#ibcon#about to read 5, iclass 5, count 0 2006.257.08:44:54.93#ibcon#read 5, iclass 5, count 0 2006.257.08:44:54.93#ibcon#about to read 6, iclass 5, count 0 2006.257.08:44:54.93#ibcon#read 6, iclass 5, count 0 2006.257.08:44:54.93#ibcon#end of sib2, iclass 5, count 0 2006.257.08:44:54.93#ibcon#*after write, iclass 5, count 0 2006.257.08:44:54.93#ibcon#*before return 0, iclass 5, count 0 2006.257.08:44:54.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:54.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.08:44:54.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.08:44:54.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.08:44:54.93$vck44/vb=1,4 2006.257.08:44:54.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.08:44:54.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.08:44:54.93#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:54.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:54.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:54.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:54.93#ibcon#enter wrdev, iclass 7, count 2 2006.257.08:44:54.93#ibcon#first serial, iclass 7, count 2 2006.257.08:44:54.93#ibcon#enter sib2, iclass 7, count 2 2006.257.08:44:54.93#ibcon#flushed, iclass 7, count 2 2006.257.08:44:54.93#ibcon#about to write, iclass 7, count 2 2006.257.08:44:54.93#ibcon#wrote, iclass 7, count 2 2006.257.08:44:54.93#ibcon#about to read 3, iclass 7, count 2 2006.257.08:44:54.95#ibcon#read 3, iclass 7, count 2 2006.257.08:44:54.95#ibcon#about to read 4, iclass 7, count 2 2006.257.08:44:54.95#ibcon#read 4, iclass 7, count 2 2006.257.08:44:54.95#ibcon#about to read 5, iclass 7, count 2 2006.257.08:44:54.95#ibcon#read 5, iclass 7, count 2 2006.257.08:44:54.95#ibcon#about to read 6, iclass 7, count 2 2006.257.08:44:54.95#ibcon#read 6, iclass 7, count 2 2006.257.08:44:54.95#ibcon#end of sib2, iclass 7, count 2 2006.257.08:44:54.95#ibcon#*mode == 0, iclass 7, count 2 2006.257.08:44:54.95#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.08:44:54.95#ibcon#[27=AT01-04\r\n] 2006.257.08:44:54.95#ibcon#*before write, iclass 7, count 2 2006.257.08:44:54.95#ibcon#enter sib2, iclass 7, count 2 2006.257.08:44:54.95#ibcon#flushed, iclass 7, count 2 2006.257.08:44:54.95#ibcon#about to write, iclass 7, count 2 2006.257.08:44:54.95#ibcon#wrote, iclass 7, count 2 2006.257.08:44:54.95#ibcon#about to read 3, iclass 7, count 2 2006.257.08:44:54.98#ibcon#read 3, iclass 7, count 2 2006.257.08:44:54.98#ibcon#about to read 4, iclass 7, count 2 2006.257.08:44:54.98#ibcon#read 4, iclass 7, count 2 2006.257.08:44:54.98#ibcon#about to read 5, iclass 7, count 2 2006.257.08:44:54.98#ibcon#read 5, iclass 7, count 2 2006.257.08:44:54.98#ibcon#about to read 6, iclass 7, count 2 2006.257.08:44:54.98#ibcon#read 6, iclass 7, count 2 2006.257.08:44:54.98#ibcon#end of sib2, iclass 7, count 2 2006.257.08:44:54.98#ibcon#*after write, iclass 7, count 2 2006.257.08:44:54.98#ibcon#*before return 0, iclass 7, count 2 2006.257.08:44:54.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:54.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.08:44:54.98#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.08:44:54.98#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:54.98#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:55.10#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:55.10#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:55.10#ibcon#enter wrdev, iclass 7, count 0 2006.257.08:44:55.10#ibcon#first serial, iclass 7, count 0 2006.257.08:44:55.10#ibcon#enter sib2, iclass 7, count 0 2006.257.08:44:55.10#ibcon#flushed, iclass 7, count 0 2006.257.08:44:55.10#ibcon#about to write, iclass 7, count 0 2006.257.08:44:55.10#ibcon#wrote, iclass 7, count 0 2006.257.08:44:55.10#ibcon#about to read 3, iclass 7, count 0 2006.257.08:44:55.12#ibcon#read 3, iclass 7, count 0 2006.257.08:44:55.12#ibcon#about to read 4, iclass 7, count 0 2006.257.08:44:55.12#ibcon#read 4, iclass 7, count 0 2006.257.08:44:55.12#ibcon#about to read 5, iclass 7, count 0 2006.257.08:44:55.12#ibcon#read 5, iclass 7, count 0 2006.257.08:44:55.12#ibcon#about to read 6, iclass 7, count 0 2006.257.08:44:55.12#ibcon#read 6, iclass 7, count 0 2006.257.08:44:55.12#ibcon#end of sib2, iclass 7, count 0 2006.257.08:44:55.12#ibcon#*mode == 0, iclass 7, count 0 2006.257.08:44:55.12#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.08:44:55.12#ibcon#[27=USB\r\n] 2006.257.08:44:55.12#ibcon#*before write, iclass 7, count 0 2006.257.08:44:55.12#ibcon#enter sib2, iclass 7, count 0 2006.257.08:44:55.12#ibcon#flushed, iclass 7, count 0 2006.257.08:44:55.12#ibcon#about to write, iclass 7, count 0 2006.257.08:44:55.12#ibcon#wrote, iclass 7, count 0 2006.257.08:44:55.12#ibcon#about to read 3, iclass 7, count 0 2006.257.08:44:55.15#ibcon#read 3, iclass 7, count 0 2006.257.08:44:55.15#ibcon#about to read 4, iclass 7, count 0 2006.257.08:44:55.15#ibcon#read 4, iclass 7, count 0 2006.257.08:44:55.15#ibcon#about to read 5, iclass 7, count 0 2006.257.08:44:55.15#ibcon#read 5, iclass 7, count 0 2006.257.08:44:55.15#ibcon#about to read 6, iclass 7, count 0 2006.257.08:44:55.15#ibcon#read 6, iclass 7, count 0 2006.257.08:44:55.15#ibcon#end of sib2, iclass 7, count 0 2006.257.08:44:55.15#ibcon#*after write, iclass 7, count 0 2006.257.08:44:55.15#ibcon#*before return 0, iclass 7, count 0 2006.257.08:44:55.15#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:55.15#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.08:44:55.15#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.08:44:55.15#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.08:44:55.15$vck44/vblo=2,634.99 2006.257.08:44:55.15#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.08:44:55.15#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.08:44:55.15#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:55.15#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:55.15#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:55.15#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:55.15#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:44:55.15#ibcon#first serial, iclass 11, count 0 2006.257.08:44:55.15#ibcon#enter sib2, iclass 11, count 0 2006.257.08:44:55.15#ibcon#flushed, iclass 11, count 0 2006.257.08:44:55.15#ibcon#about to write, iclass 11, count 0 2006.257.08:44:55.15#ibcon#wrote, iclass 11, count 0 2006.257.08:44:55.15#ibcon#about to read 3, iclass 11, count 0 2006.257.08:44:55.17#ibcon#read 3, iclass 11, count 0 2006.257.08:44:55.17#ibcon#about to read 4, iclass 11, count 0 2006.257.08:44:55.17#ibcon#read 4, iclass 11, count 0 2006.257.08:44:55.17#ibcon#about to read 5, iclass 11, count 0 2006.257.08:44:55.17#ibcon#read 5, iclass 11, count 0 2006.257.08:44:55.17#ibcon#about to read 6, iclass 11, count 0 2006.257.08:44:55.17#ibcon#read 6, iclass 11, count 0 2006.257.08:44:55.17#ibcon#end of sib2, iclass 11, count 0 2006.257.08:44:55.17#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:44:55.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:44:55.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:44:55.17#ibcon#*before write, iclass 11, count 0 2006.257.08:44:55.17#ibcon#enter sib2, iclass 11, count 0 2006.257.08:44:55.17#ibcon#flushed, iclass 11, count 0 2006.257.08:44:55.17#ibcon#about to write, iclass 11, count 0 2006.257.08:44:55.17#ibcon#wrote, iclass 11, count 0 2006.257.08:44:55.17#ibcon#about to read 3, iclass 11, count 0 2006.257.08:44:55.21#ibcon#read 3, iclass 11, count 0 2006.257.08:44:55.21#ibcon#about to read 4, iclass 11, count 0 2006.257.08:44:55.21#ibcon#read 4, iclass 11, count 0 2006.257.08:44:55.21#ibcon#about to read 5, iclass 11, count 0 2006.257.08:44:55.21#ibcon#read 5, iclass 11, count 0 2006.257.08:44:55.21#ibcon#about to read 6, iclass 11, count 0 2006.257.08:44:55.21#ibcon#read 6, iclass 11, count 0 2006.257.08:44:55.21#ibcon#end of sib2, iclass 11, count 0 2006.257.08:44:55.21#ibcon#*after write, iclass 11, count 0 2006.257.08:44:55.21#ibcon#*before return 0, iclass 11, count 0 2006.257.08:44:55.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:55.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.08:44:55.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:44:55.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:44:55.21$vck44/vb=2,5 2006.257.08:44:55.21#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.08:44:55.21#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.08:44:55.21#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:55.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:55.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:55.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:55.27#ibcon#enter wrdev, iclass 13, count 2 2006.257.08:44:55.27#ibcon#first serial, iclass 13, count 2 2006.257.08:44:55.27#ibcon#enter sib2, iclass 13, count 2 2006.257.08:44:55.27#ibcon#flushed, iclass 13, count 2 2006.257.08:44:55.27#ibcon#about to write, iclass 13, count 2 2006.257.08:44:55.27#ibcon#wrote, iclass 13, count 2 2006.257.08:44:55.27#ibcon#about to read 3, iclass 13, count 2 2006.257.08:44:55.29#ibcon#read 3, iclass 13, count 2 2006.257.08:44:55.29#ibcon#about to read 4, iclass 13, count 2 2006.257.08:44:55.29#ibcon#read 4, iclass 13, count 2 2006.257.08:44:55.29#ibcon#about to read 5, iclass 13, count 2 2006.257.08:44:55.29#ibcon#read 5, iclass 13, count 2 2006.257.08:44:55.29#ibcon#about to read 6, iclass 13, count 2 2006.257.08:44:55.29#ibcon#read 6, iclass 13, count 2 2006.257.08:44:55.29#ibcon#end of sib2, iclass 13, count 2 2006.257.08:44:55.29#ibcon#*mode == 0, iclass 13, count 2 2006.257.08:44:55.29#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.08:44:55.29#ibcon#[27=AT02-05\r\n] 2006.257.08:44:55.29#ibcon#*before write, iclass 13, count 2 2006.257.08:44:55.29#ibcon#enter sib2, iclass 13, count 2 2006.257.08:44:55.29#ibcon#flushed, iclass 13, count 2 2006.257.08:44:55.29#ibcon#about to write, iclass 13, count 2 2006.257.08:44:55.29#ibcon#wrote, iclass 13, count 2 2006.257.08:44:55.29#ibcon#about to read 3, iclass 13, count 2 2006.257.08:44:55.32#ibcon#read 3, iclass 13, count 2 2006.257.08:44:55.32#ibcon#about to read 4, iclass 13, count 2 2006.257.08:44:55.32#ibcon#read 4, iclass 13, count 2 2006.257.08:44:55.32#ibcon#about to read 5, iclass 13, count 2 2006.257.08:44:55.32#ibcon#read 5, iclass 13, count 2 2006.257.08:44:55.32#ibcon#about to read 6, iclass 13, count 2 2006.257.08:44:55.32#ibcon#read 6, iclass 13, count 2 2006.257.08:44:55.32#ibcon#end of sib2, iclass 13, count 2 2006.257.08:44:55.32#ibcon#*after write, iclass 13, count 2 2006.257.08:44:55.32#ibcon#*before return 0, iclass 13, count 2 2006.257.08:44:55.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:55.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.08:44:55.32#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.08:44:55.32#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:55.32#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:55.44#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:55.44#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:55.44#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:44:55.44#ibcon#first serial, iclass 13, count 0 2006.257.08:44:55.44#ibcon#enter sib2, iclass 13, count 0 2006.257.08:44:55.44#ibcon#flushed, iclass 13, count 0 2006.257.08:44:55.44#ibcon#about to write, iclass 13, count 0 2006.257.08:44:55.44#ibcon#wrote, iclass 13, count 0 2006.257.08:44:55.44#ibcon#about to read 3, iclass 13, count 0 2006.257.08:44:55.46#ibcon#read 3, iclass 13, count 0 2006.257.08:44:55.46#ibcon#about to read 4, iclass 13, count 0 2006.257.08:44:55.46#ibcon#read 4, iclass 13, count 0 2006.257.08:44:55.46#ibcon#about to read 5, iclass 13, count 0 2006.257.08:44:55.46#ibcon#read 5, iclass 13, count 0 2006.257.08:44:55.46#ibcon#about to read 6, iclass 13, count 0 2006.257.08:44:55.46#ibcon#read 6, iclass 13, count 0 2006.257.08:44:55.46#ibcon#end of sib2, iclass 13, count 0 2006.257.08:44:55.46#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:44:55.46#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:44:55.46#ibcon#[27=USB\r\n] 2006.257.08:44:55.46#ibcon#*before write, iclass 13, count 0 2006.257.08:44:55.46#ibcon#enter sib2, iclass 13, count 0 2006.257.08:44:55.46#ibcon#flushed, iclass 13, count 0 2006.257.08:44:55.46#ibcon#about to write, iclass 13, count 0 2006.257.08:44:55.46#ibcon#wrote, iclass 13, count 0 2006.257.08:44:55.46#ibcon#about to read 3, iclass 13, count 0 2006.257.08:44:55.49#ibcon#read 3, iclass 13, count 0 2006.257.08:44:55.49#ibcon#about to read 4, iclass 13, count 0 2006.257.08:44:55.49#ibcon#read 4, iclass 13, count 0 2006.257.08:44:55.49#ibcon#about to read 5, iclass 13, count 0 2006.257.08:44:55.49#ibcon#read 5, iclass 13, count 0 2006.257.08:44:55.49#ibcon#about to read 6, iclass 13, count 0 2006.257.08:44:55.49#ibcon#read 6, iclass 13, count 0 2006.257.08:44:55.49#ibcon#end of sib2, iclass 13, count 0 2006.257.08:44:55.49#ibcon#*after write, iclass 13, count 0 2006.257.08:44:55.49#ibcon#*before return 0, iclass 13, count 0 2006.257.08:44:55.49#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:55.49#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.08:44:55.49#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:44:55.49#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:44:55.49$vck44/vblo=3,649.99 2006.257.08:44:55.49#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.08:44:55.49#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.08:44:55.49#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:55.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:55.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:55.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:55.49#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:44:55.49#ibcon#first serial, iclass 15, count 0 2006.257.08:44:55.49#ibcon#enter sib2, iclass 15, count 0 2006.257.08:44:55.49#ibcon#flushed, iclass 15, count 0 2006.257.08:44:55.49#ibcon#about to write, iclass 15, count 0 2006.257.08:44:55.49#ibcon#wrote, iclass 15, count 0 2006.257.08:44:55.49#ibcon#about to read 3, iclass 15, count 0 2006.257.08:44:55.51#ibcon#read 3, iclass 15, count 0 2006.257.08:44:55.51#ibcon#about to read 4, iclass 15, count 0 2006.257.08:44:55.51#ibcon#read 4, iclass 15, count 0 2006.257.08:44:55.51#ibcon#about to read 5, iclass 15, count 0 2006.257.08:44:55.51#ibcon#read 5, iclass 15, count 0 2006.257.08:44:55.51#ibcon#about to read 6, iclass 15, count 0 2006.257.08:44:55.51#ibcon#read 6, iclass 15, count 0 2006.257.08:44:55.51#ibcon#end of sib2, iclass 15, count 0 2006.257.08:44:55.51#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:44:55.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:44:55.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:44:55.51#ibcon#*before write, iclass 15, count 0 2006.257.08:44:55.51#ibcon#enter sib2, iclass 15, count 0 2006.257.08:44:55.51#ibcon#flushed, iclass 15, count 0 2006.257.08:44:55.51#ibcon#about to write, iclass 15, count 0 2006.257.08:44:55.51#ibcon#wrote, iclass 15, count 0 2006.257.08:44:55.51#ibcon#about to read 3, iclass 15, count 0 2006.257.08:44:55.55#ibcon#read 3, iclass 15, count 0 2006.257.08:44:55.55#ibcon#about to read 4, iclass 15, count 0 2006.257.08:44:55.55#ibcon#read 4, iclass 15, count 0 2006.257.08:44:55.55#ibcon#about to read 5, iclass 15, count 0 2006.257.08:44:55.55#ibcon#read 5, iclass 15, count 0 2006.257.08:44:55.55#ibcon#about to read 6, iclass 15, count 0 2006.257.08:44:55.55#ibcon#read 6, iclass 15, count 0 2006.257.08:44:55.55#ibcon#end of sib2, iclass 15, count 0 2006.257.08:44:55.55#ibcon#*after write, iclass 15, count 0 2006.257.08:44:55.55#ibcon#*before return 0, iclass 15, count 0 2006.257.08:44:55.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:55.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.08:44:55.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:44:55.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:44:55.55$vck44/vb=3,4 2006.257.08:44:55.55#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.08:44:55.55#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.08:44:55.55#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:55.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:55.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:55.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:55.61#ibcon#enter wrdev, iclass 17, count 2 2006.257.08:44:55.61#ibcon#first serial, iclass 17, count 2 2006.257.08:44:55.61#ibcon#enter sib2, iclass 17, count 2 2006.257.08:44:55.61#ibcon#flushed, iclass 17, count 2 2006.257.08:44:55.61#ibcon#about to write, iclass 17, count 2 2006.257.08:44:55.61#ibcon#wrote, iclass 17, count 2 2006.257.08:44:55.61#ibcon#about to read 3, iclass 17, count 2 2006.257.08:44:55.63#ibcon#read 3, iclass 17, count 2 2006.257.08:44:55.63#ibcon#about to read 4, iclass 17, count 2 2006.257.08:44:55.63#ibcon#read 4, iclass 17, count 2 2006.257.08:44:55.63#ibcon#about to read 5, iclass 17, count 2 2006.257.08:44:55.63#ibcon#read 5, iclass 17, count 2 2006.257.08:44:55.63#ibcon#about to read 6, iclass 17, count 2 2006.257.08:44:55.63#ibcon#read 6, iclass 17, count 2 2006.257.08:44:55.63#ibcon#end of sib2, iclass 17, count 2 2006.257.08:44:55.63#ibcon#*mode == 0, iclass 17, count 2 2006.257.08:44:55.63#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.08:44:55.63#ibcon#[27=AT03-04\r\n] 2006.257.08:44:55.63#ibcon#*before write, iclass 17, count 2 2006.257.08:44:55.63#ibcon#enter sib2, iclass 17, count 2 2006.257.08:44:55.63#ibcon#flushed, iclass 17, count 2 2006.257.08:44:55.63#ibcon#about to write, iclass 17, count 2 2006.257.08:44:55.63#ibcon#wrote, iclass 17, count 2 2006.257.08:44:55.63#ibcon#about to read 3, iclass 17, count 2 2006.257.08:44:55.66#ibcon#read 3, iclass 17, count 2 2006.257.08:44:55.66#ibcon#about to read 4, iclass 17, count 2 2006.257.08:44:55.66#ibcon#read 4, iclass 17, count 2 2006.257.08:44:55.66#ibcon#about to read 5, iclass 17, count 2 2006.257.08:44:55.66#ibcon#read 5, iclass 17, count 2 2006.257.08:44:55.66#ibcon#about to read 6, iclass 17, count 2 2006.257.08:44:55.66#ibcon#read 6, iclass 17, count 2 2006.257.08:44:55.66#ibcon#end of sib2, iclass 17, count 2 2006.257.08:44:55.66#ibcon#*after write, iclass 17, count 2 2006.257.08:44:55.66#ibcon#*before return 0, iclass 17, count 2 2006.257.08:44:55.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:55.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.08:44:55.66#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.08:44:55.66#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:55.66#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:55.78#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:55.78#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:55.78#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:44:55.78#ibcon#first serial, iclass 17, count 0 2006.257.08:44:55.78#ibcon#enter sib2, iclass 17, count 0 2006.257.08:44:55.78#ibcon#flushed, iclass 17, count 0 2006.257.08:44:55.78#ibcon#about to write, iclass 17, count 0 2006.257.08:44:55.78#ibcon#wrote, iclass 17, count 0 2006.257.08:44:55.78#ibcon#about to read 3, iclass 17, count 0 2006.257.08:44:55.80#ibcon#read 3, iclass 17, count 0 2006.257.08:44:55.80#ibcon#about to read 4, iclass 17, count 0 2006.257.08:44:55.80#ibcon#read 4, iclass 17, count 0 2006.257.08:44:55.80#ibcon#about to read 5, iclass 17, count 0 2006.257.08:44:55.80#ibcon#read 5, iclass 17, count 0 2006.257.08:44:55.80#ibcon#about to read 6, iclass 17, count 0 2006.257.08:44:55.80#ibcon#read 6, iclass 17, count 0 2006.257.08:44:55.80#ibcon#end of sib2, iclass 17, count 0 2006.257.08:44:55.80#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:44:55.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:44:55.80#ibcon#[27=USB\r\n] 2006.257.08:44:55.80#ibcon#*before write, iclass 17, count 0 2006.257.08:44:55.80#ibcon#enter sib2, iclass 17, count 0 2006.257.08:44:55.80#ibcon#flushed, iclass 17, count 0 2006.257.08:44:55.80#ibcon#about to write, iclass 17, count 0 2006.257.08:44:55.80#ibcon#wrote, iclass 17, count 0 2006.257.08:44:55.80#ibcon#about to read 3, iclass 17, count 0 2006.257.08:44:55.83#ibcon#read 3, iclass 17, count 0 2006.257.08:44:55.83#ibcon#about to read 4, iclass 17, count 0 2006.257.08:44:55.83#ibcon#read 4, iclass 17, count 0 2006.257.08:44:55.83#ibcon#about to read 5, iclass 17, count 0 2006.257.08:44:55.83#ibcon#read 5, iclass 17, count 0 2006.257.08:44:55.83#ibcon#about to read 6, iclass 17, count 0 2006.257.08:44:55.83#ibcon#read 6, iclass 17, count 0 2006.257.08:44:55.83#ibcon#end of sib2, iclass 17, count 0 2006.257.08:44:55.83#ibcon#*after write, iclass 17, count 0 2006.257.08:44:55.83#ibcon#*before return 0, iclass 17, count 0 2006.257.08:44:55.83#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:55.83#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.08:44:55.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:44:55.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:44:55.83$vck44/vblo=4,679.99 2006.257.08:44:55.83#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.08:44:55.83#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.08:44:55.83#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:55.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:55.83#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:55.83#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:55.83#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:44:55.83#ibcon#first serial, iclass 19, count 0 2006.257.08:44:55.83#ibcon#enter sib2, iclass 19, count 0 2006.257.08:44:55.83#ibcon#flushed, iclass 19, count 0 2006.257.08:44:55.83#ibcon#about to write, iclass 19, count 0 2006.257.08:44:55.83#ibcon#wrote, iclass 19, count 0 2006.257.08:44:55.83#ibcon#about to read 3, iclass 19, count 0 2006.257.08:44:55.85#ibcon#read 3, iclass 19, count 0 2006.257.08:44:55.85#ibcon#about to read 4, iclass 19, count 0 2006.257.08:44:55.85#ibcon#read 4, iclass 19, count 0 2006.257.08:44:55.85#ibcon#about to read 5, iclass 19, count 0 2006.257.08:44:55.85#ibcon#read 5, iclass 19, count 0 2006.257.08:44:55.85#ibcon#about to read 6, iclass 19, count 0 2006.257.08:44:55.85#ibcon#read 6, iclass 19, count 0 2006.257.08:44:55.85#ibcon#end of sib2, iclass 19, count 0 2006.257.08:44:55.85#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:44:55.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:44:55.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:44:55.85#ibcon#*before write, iclass 19, count 0 2006.257.08:44:55.85#ibcon#enter sib2, iclass 19, count 0 2006.257.08:44:55.85#ibcon#flushed, iclass 19, count 0 2006.257.08:44:55.85#ibcon#about to write, iclass 19, count 0 2006.257.08:44:55.85#ibcon#wrote, iclass 19, count 0 2006.257.08:44:55.85#ibcon#about to read 3, iclass 19, count 0 2006.257.08:44:55.89#ibcon#read 3, iclass 19, count 0 2006.257.08:44:55.89#ibcon#about to read 4, iclass 19, count 0 2006.257.08:44:55.89#ibcon#read 4, iclass 19, count 0 2006.257.08:44:55.89#ibcon#about to read 5, iclass 19, count 0 2006.257.08:44:55.89#ibcon#read 5, iclass 19, count 0 2006.257.08:44:55.89#ibcon#about to read 6, iclass 19, count 0 2006.257.08:44:55.89#ibcon#read 6, iclass 19, count 0 2006.257.08:44:55.89#ibcon#end of sib2, iclass 19, count 0 2006.257.08:44:55.89#ibcon#*after write, iclass 19, count 0 2006.257.08:44:55.89#ibcon#*before return 0, iclass 19, count 0 2006.257.08:44:55.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:55.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.08:44:55.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:44:55.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:44:55.89$vck44/vb=4,5 2006.257.08:44:55.89#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.08:44:55.89#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.08:44:55.89#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:55.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:55.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:55.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:55.95#ibcon#enter wrdev, iclass 21, count 2 2006.257.08:44:55.95#ibcon#first serial, iclass 21, count 2 2006.257.08:44:55.95#ibcon#enter sib2, iclass 21, count 2 2006.257.08:44:55.95#ibcon#flushed, iclass 21, count 2 2006.257.08:44:55.95#ibcon#about to write, iclass 21, count 2 2006.257.08:44:55.95#ibcon#wrote, iclass 21, count 2 2006.257.08:44:55.95#ibcon#about to read 3, iclass 21, count 2 2006.257.08:44:55.97#ibcon#read 3, iclass 21, count 2 2006.257.08:44:55.97#ibcon#about to read 4, iclass 21, count 2 2006.257.08:44:55.97#ibcon#read 4, iclass 21, count 2 2006.257.08:44:55.97#ibcon#about to read 5, iclass 21, count 2 2006.257.08:44:55.97#ibcon#read 5, iclass 21, count 2 2006.257.08:44:55.97#ibcon#about to read 6, iclass 21, count 2 2006.257.08:44:55.97#ibcon#read 6, iclass 21, count 2 2006.257.08:44:55.97#ibcon#end of sib2, iclass 21, count 2 2006.257.08:44:55.97#ibcon#*mode == 0, iclass 21, count 2 2006.257.08:44:55.97#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.08:44:55.97#ibcon#[27=AT04-05\r\n] 2006.257.08:44:55.97#ibcon#*before write, iclass 21, count 2 2006.257.08:44:55.97#ibcon#enter sib2, iclass 21, count 2 2006.257.08:44:55.97#ibcon#flushed, iclass 21, count 2 2006.257.08:44:55.97#ibcon#about to write, iclass 21, count 2 2006.257.08:44:55.97#ibcon#wrote, iclass 21, count 2 2006.257.08:44:55.97#ibcon#about to read 3, iclass 21, count 2 2006.257.08:44:56.00#ibcon#read 3, iclass 21, count 2 2006.257.08:44:56.00#ibcon#about to read 4, iclass 21, count 2 2006.257.08:44:56.00#ibcon#read 4, iclass 21, count 2 2006.257.08:44:56.00#ibcon#about to read 5, iclass 21, count 2 2006.257.08:44:56.00#ibcon#read 5, iclass 21, count 2 2006.257.08:44:56.00#ibcon#about to read 6, iclass 21, count 2 2006.257.08:44:56.00#ibcon#read 6, iclass 21, count 2 2006.257.08:44:56.00#ibcon#end of sib2, iclass 21, count 2 2006.257.08:44:56.00#ibcon#*after write, iclass 21, count 2 2006.257.08:44:56.00#ibcon#*before return 0, iclass 21, count 2 2006.257.08:44:56.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:56.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.08:44:56.00#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.08:44:56.00#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:56.00#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:56.12#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:56.12#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:56.12#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:44:56.12#ibcon#first serial, iclass 21, count 0 2006.257.08:44:56.12#ibcon#enter sib2, iclass 21, count 0 2006.257.08:44:56.12#ibcon#flushed, iclass 21, count 0 2006.257.08:44:56.12#ibcon#about to write, iclass 21, count 0 2006.257.08:44:56.12#ibcon#wrote, iclass 21, count 0 2006.257.08:44:56.12#ibcon#about to read 3, iclass 21, count 0 2006.257.08:44:56.14#ibcon#read 3, iclass 21, count 0 2006.257.08:44:56.14#ibcon#about to read 4, iclass 21, count 0 2006.257.08:44:56.14#ibcon#read 4, iclass 21, count 0 2006.257.08:44:56.14#ibcon#about to read 5, iclass 21, count 0 2006.257.08:44:56.14#ibcon#read 5, iclass 21, count 0 2006.257.08:44:56.14#ibcon#about to read 6, iclass 21, count 0 2006.257.08:44:56.14#ibcon#read 6, iclass 21, count 0 2006.257.08:44:56.14#ibcon#end of sib2, iclass 21, count 0 2006.257.08:44:56.14#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:44:56.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:44:56.14#ibcon#[27=USB\r\n] 2006.257.08:44:56.14#ibcon#*before write, iclass 21, count 0 2006.257.08:44:56.14#ibcon#enter sib2, iclass 21, count 0 2006.257.08:44:56.14#ibcon#flushed, iclass 21, count 0 2006.257.08:44:56.14#ibcon#about to write, iclass 21, count 0 2006.257.08:44:56.14#ibcon#wrote, iclass 21, count 0 2006.257.08:44:56.14#ibcon#about to read 3, iclass 21, count 0 2006.257.08:44:56.17#ibcon#read 3, iclass 21, count 0 2006.257.08:44:56.17#ibcon#about to read 4, iclass 21, count 0 2006.257.08:44:56.17#ibcon#read 4, iclass 21, count 0 2006.257.08:44:56.17#ibcon#about to read 5, iclass 21, count 0 2006.257.08:44:56.17#ibcon#read 5, iclass 21, count 0 2006.257.08:44:56.17#ibcon#about to read 6, iclass 21, count 0 2006.257.08:44:56.17#ibcon#read 6, iclass 21, count 0 2006.257.08:44:56.17#ibcon#end of sib2, iclass 21, count 0 2006.257.08:44:56.17#ibcon#*after write, iclass 21, count 0 2006.257.08:44:56.17#ibcon#*before return 0, iclass 21, count 0 2006.257.08:44:56.17#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:56.17#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.08:44:56.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:44:56.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:44:56.17$vck44/vblo=5,709.99 2006.257.08:44:56.17#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.08:44:56.17#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.08:44:56.17#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:56.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:56.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:56.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:56.17#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:44:56.17#ibcon#first serial, iclass 23, count 0 2006.257.08:44:56.17#ibcon#enter sib2, iclass 23, count 0 2006.257.08:44:56.17#ibcon#flushed, iclass 23, count 0 2006.257.08:44:56.17#ibcon#about to write, iclass 23, count 0 2006.257.08:44:56.17#ibcon#wrote, iclass 23, count 0 2006.257.08:44:56.17#ibcon#about to read 3, iclass 23, count 0 2006.257.08:44:56.19#ibcon#read 3, iclass 23, count 0 2006.257.08:44:56.19#ibcon#about to read 4, iclass 23, count 0 2006.257.08:44:56.19#ibcon#read 4, iclass 23, count 0 2006.257.08:44:56.19#ibcon#about to read 5, iclass 23, count 0 2006.257.08:44:56.19#ibcon#read 5, iclass 23, count 0 2006.257.08:44:56.19#ibcon#about to read 6, iclass 23, count 0 2006.257.08:44:56.19#ibcon#read 6, iclass 23, count 0 2006.257.08:44:56.19#ibcon#end of sib2, iclass 23, count 0 2006.257.08:44:56.19#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:44:56.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:44:56.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:44:56.19#ibcon#*before write, iclass 23, count 0 2006.257.08:44:56.19#ibcon#enter sib2, iclass 23, count 0 2006.257.08:44:56.19#ibcon#flushed, iclass 23, count 0 2006.257.08:44:56.19#ibcon#about to write, iclass 23, count 0 2006.257.08:44:56.19#ibcon#wrote, iclass 23, count 0 2006.257.08:44:56.19#ibcon#about to read 3, iclass 23, count 0 2006.257.08:44:56.23#ibcon#read 3, iclass 23, count 0 2006.257.08:44:56.23#ibcon#about to read 4, iclass 23, count 0 2006.257.08:44:56.23#ibcon#read 4, iclass 23, count 0 2006.257.08:44:56.23#ibcon#about to read 5, iclass 23, count 0 2006.257.08:44:56.23#ibcon#read 5, iclass 23, count 0 2006.257.08:44:56.23#ibcon#about to read 6, iclass 23, count 0 2006.257.08:44:56.23#ibcon#read 6, iclass 23, count 0 2006.257.08:44:56.23#ibcon#end of sib2, iclass 23, count 0 2006.257.08:44:56.23#ibcon#*after write, iclass 23, count 0 2006.257.08:44:56.23#ibcon#*before return 0, iclass 23, count 0 2006.257.08:44:56.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:56.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.08:44:56.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:44:56.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:44:56.23$vck44/vb=5,4 2006.257.08:44:56.23#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.08:44:56.23#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.08:44:56.23#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:56.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:56.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:56.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:56.29#ibcon#enter wrdev, iclass 25, count 2 2006.257.08:44:56.29#ibcon#first serial, iclass 25, count 2 2006.257.08:44:56.29#ibcon#enter sib2, iclass 25, count 2 2006.257.08:44:56.29#ibcon#flushed, iclass 25, count 2 2006.257.08:44:56.29#ibcon#about to write, iclass 25, count 2 2006.257.08:44:56.29#ibcon#wrote, iclass 25, count 2 2006.257.08:44:56.29#ibcon#about to read 3, iclass 25, count 2 2006.257.08:44:56.31#ibcon#read 3, iclass 25, count 2 2006.257.08:44:56.31#ibcon#about to read 4, iclass 25, count 2 2006.257.08:44:56.31#ibcon#read 4, iclass 25, count 2 2006.257.08:44:56.31#ibcon#about to read 5, iclass 25, count 2 2006.257.08:44:56.31#ibcon#read 5, iclass 25, count 2 2006.257.08:44:56.31#ibcon#about to read 6, iclass 25, count 2 2006.257.08:44:56.31#ibcon#read 6, iclass 25, count 2 2006.257.08:44:56.31#ibcon#end of sib2, iclass 25, count 2 2006.257.08:44:56.31#ibcon#*mode == 0, iclass 25, count 2 2006.257.08:44:56.31#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.08:44:56.31#ibcon#[27=AT05-04\r\n] 2006.257.08:44:56.31#ibcon#*before write, iclass 25, count 2 2006.257.08:44:56.31#ibcon#enter sib2, iclass 25, count 2 2006.257.08:44:56.31#ibcon#flushed, iclass 25, count 2 2006.257.08:44:56.31#ibcon#about to write, iclass 25, count 2 2006.257.08:44:56.31#ibcon#wrote, iclass 25, count 2 2006.257.08:44:56.31#ibcon#about to read 3, iclass 25, count 2 2006.257.08:44:56.34#ibcon#read 3, iclass 25, count 2 2006.257.08:44:56.35#ibcon#about to read 4, iclass 25, count 2 2006.257.08:44:56.35#ibcon#read 4, iclass 25, count 2 2006.257.08:44:56.35#ibcon#about to read 5, iclass 25, count 2 2006.257.08:44:56.35#ibcon#read 5, iclass 25, count 2 2006.257.08:44:56.35#ibcon#about to read 6, iclass 25, count 2 2006.257.08:44:56.35#ibcon#read 6, iclass 25, count 2 2006.257.08:44:56.35#ibcon#end of sib2, iclass 25, count 2 2006.257.08:44:56.35#ibcon#*after write, iclass 25, count 2 2006.257.08:44:56.35#ibcon#*before return 0, iclass 25, count 2 2006.257.08:44:56.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:56.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.08:44:56.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.08:44:56.35#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:56.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:56.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:56.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:56.47#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:44:56.47#ibcon#first serial, iclass 25, count 0 2006.257.08:44:56.47#ibcon#enter sib2, iclass 25, count 0 2006.257.08:44:56.47#ibcon#flushed, iclass 25, count 0 2006.257.08:44:56.47#ibcon#about to write, iclass 25, count 0 2006.257.08:44:56.47#ibcon#wrote, iclass 25, count 0 2006.257.08:44:56.47#ibcon#about to read 3, iclass 25, count 0 2006.257.08:44:56.49#ibcon#read 3, iclass 25, count 0 2006.257.08:44:56.49#ibcon#about to read 4, iclass 25, count 0 2006.257.08:44:56.49#ibcon#read 4, iclass 25, count 0 2006.257.08:44:56.49#ibcon#about to read 5, iclass 25, count 0 2006.257.08:44:56.49#ibcon#read 5, iclass 25, count 0 2006.257.08:44:56.49#ibcon#about to read 6, iclass 25, count 0 2006.257.08:44:56.49#ibcon#read 6, iclass 25, count 0 2006.257.08:44:56.49#ibcon#end of sib2, iclass 25, count 0 2006.257.08:44:56.49#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:44:56.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:44:56.49#ibcon#[27=USB\r\n] 2006.257.08:44:56.49#ibcon#*before write, iclass 25, count 0 2006.257.08:44:56.49#ibcon#enter sib2, iclass 25, count 0 2006.257.08:44:56.49#ibcon#flushed, iclass 25, count 0 2006.257.08:44:56.49#ibcon#about to write, iclass 25, count 0 2006.257.08:44:56.49#ibcon#wrote, iclass 25, count 0 2006.257.08:44:56.49#ibcon#about to read 3, iclass 25, count 0 2006.257.08:44:56.52#ibcon#read 3, iclass 25, count 0 2006.257.08:44:56.52#ibcon#about to read 4, iclass 25, count 0 2006.257.08:44:56.52#ibcon#read 4, iclass 25, count 0 2006.257.08:44:56.52#ibcon#about to read 5, iclass 25, count 0 2006.257.08:44:56.52#ibcon#read 5, iclass 25, count 0 2006.257.08:44:56.52#ibcon#about to read 6, iclass 25, count 0 2006.257.08:44:56.52#ibcon#read 6, iclass 25, count 0 2006.257.08:44:56.52#ibcon#end of sib2, iclass 25, count 0 2006.257.08:44:56.52#ibcon#*after write, iclass 25, count 0 2006.257.08:44:56.52#ibcon#*before return 0, iclass 25, count 0 2006.257.08:44:56.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:56.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.08:44:56.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:44:56.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:44:56.52$vck44/vblo=6,719.99 2006.257.08:44:56.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.08:44:56.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.08:44:56.52#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:56.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:56.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:56.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:56.52#ibcon#enter wrdev, iclass 27, count 0 2006.257.08:44:56.52#ibcon#first serial, iclass 27, count 0 2006.257.08:44:56.52#ibcon#enter sib2, iclass 27, count 0 2006.257.08:44:56.52#ibcon#flushed, iclass 27, count 0 2006.257.08:44:56.52#ibcon#about to write, iclass 27, count 0 2006.257.08:44:56.52#ibcon#wrote, iclass 27, count 0 2006.257.08:44:56.52#ibcon#about to read 3, iclass 27, count 0 2006.257.08:44:56.54#ibcon#read 3, iclass 27, count 0 2006.257.08:44:56.54#ibcon#about to read 4, iclass 27, count 0 2006.257.08:44:56.54#ibcon#read 4, iclass 27, count 0 2006.257.08:44:56.54#ibcon#about to read 5, iclass 27, count 0 2006.257.08:44:56.54#ibcon#read 5, iclass 27, count 0 2006.257.08:44:56.54#ibcon#about to read 6, iclass 27, count 0 2006.257.08:44:56.54#ibcon#read 6, iclass 27, count 0 2006.257.08:44:56.54#ibcon#end of sib2, iclass 27, count 0 2006.257.08:44:56.54#ibcon#*mode == 0, iclass 27, count 0 2006.257.08:44:56.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.08:44:56.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:44:56.54#ibcon#*before write, iclass 27, count 0 2006.257.08:44:56.54#ibcon#enter sib2, iclass 27, count 0 2006.257.08:44:56.54#ibcon#flushed, iclass 27, count 0 2006.257.08:44:56.54#ibcon#about to write, iclass 27, count 0 2006.257.08:44:56.54#ibcon#wrote, iclass 27, count 0 2006.257.08:44:56.54#ibcon#about to read 3, iclass 27, count 0 2006.257.08:44:56.58#ibcon#read 3, iclass 27, count 0 2006.257.08:44:56.58#ibcon#about to read 4, iclass 27, count 0 2006.257.08:44:56.58#ibcon#read 4, iclass 27, count 0 2006.257.08:44:56.58#ibcon#about to read 5, iclass 27, count 0 2006.257.08:44:56.58#ibcon#read 5, iclass 27, count 0 2006.257.08:44:56.58#ibcon#about to read 6, iclass 27, count 0 2006.257.08:44:56.58#ibcon#read 6, iclass 27, count 0 2006.257.08:44:56.58#ibcon#end of sib2, iclass 27, count 0 2006.257.08:44:56.58#ibcon#*after write, iclass 27, count 0 2006.257.08:44:56.58#ibcon#*before return 0, iclass 27, count 0 2006.257.08:44:56.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:56.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.08:44:56.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.08:44:56.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.08:44:56.58$vck44/vb=6,4 2006.257.08:44:56.58#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.08:44:56.58#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.08:44:56.58#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:56.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:56.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:56.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:56.64#ibcon#enter wrdev, iclass 29, count 2 2006.257.08:44:56.64#ibcon#first serial, iclass 29, count 2 2006.257.08:44:56.64#ibcon#enter sib2, iclass 29, count 2 2006.257.08:44:56.64#ibcon#flushed, iclass 29, count 2 2006.257.08:44:56.64#ibcon#about to write, iclass 29, count 2 2006.257.08:44:56.64#ibcon#wrote, iclass 29, count 2 2006.257.08:44:56.64#ibcon#about to read 3, iclass 29, count 2 2006.257.08:44:56.66#ibcon#read 3, iclass 29, count 2 2006.257.08:44:56.66#ibcon#about to read 4, iclass 29, count 2 2006.257.08:44:56.66#ibcon#read 4, iclass 29, count 2 2006.257.08:44:56.66#ibcon#about to read 5, iclass 29, count 2 2006.257.08:44:56.66#ibcon#read 5, iclass 29, count 2 2006.257.08:44:56.66#ibcon#about to read 6, iclass 29, count 2 2006.257.08:44:56.66#ibcon#read 6, iclass 29, count 2 2006.257.08:44:56.66#ibcon#end of sib2, iclass 29, count 2 2006.257.08:44:56.66#ibcon#*mode == 0, iclass 29, count 2 2006.257.08:44:56.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.08:44:56.66#ibcon#[27=AT06-04\r\n] 2006.257.08:44:56.66#ibcon#*before write, iclass 29, count 2 2006.257.08:44:56.66#ibcon#enter sib2, iclass 29, count 2 2006.257.08:44:56.66#ibcon#flushed, iclass 29, count 2 2006.257.08:44:56.66#ibcon#about to write, iclass 29, count 2 2006.257.08:44:56.66#ibcon#wrote, iclass 29, count 2 2006.257.08:44:56.66#ibcon#about to read 3, iclass 29, count 2 2006.257.08:44:56.69#ibcon#read 3, iclass 29, count 2 2006.257.08:44:56.69#ibcon#about to read 4, iclass 29, count 2 2006.257.08:44:56.69#ibcon#read 4, iclass 29, count 2 2006.257.08:44:56.69#ibcon#about to read 5, iclass 29, count 2 2006.257.08:44:56.69#ibcon#read 5, iclass 29, count 2 2006.257.08:44:56.69#ibcon#about to read 6, iclass 29, count 2 2006.257.08:44:56.69#ibcon#read 6, iclass 29, count 2 2006.257.08:44:56.69#ibcon#end of sib2, iclass 29, count 2 2006.257.08:44:56.69#ibcon#*after write, iclass 29, count 2 2006.257.08:44:56.69#ibcon#*before return 0, iclass 29, count 2 2006.257.08:44:56.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:56.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.08:44:56.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.08:44:56.69#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:56.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:56.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:56.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:56.81#ibcon#enter wrdev, iclass 29, count 0 2006.257.08:44:56.81#ibcon#first serial, iclass 29, count 0 2006.257.08:44:56.81#ibcon#enter sib2, iclass 29, count 0 2006.257.08:44:56.81#ibcon#flushed, iclass 29, count 0 2006.257.08:44:56.81#ibcon#about to write, iclass 29, count 0 2006.257.08:44:56.81#ibcon#wrote, iclass 29, count 0 2006.257.08:44:56.81#ibcon#about to read 3, iclass 29, count 0 2006.257.08:44:56.83#ibcon#read 3, iclass 29, count 0 2006.257.08:44:56.83#ibcon#about to read 4, iclass 29, count 0 2006.257.08:44:56.83#ibcon#read 4, iclass 29, count 0 2006.257.08:44:56.83#ibcon#about to read 5, iclass 29, count 0 2006.257.08:44:56.83#ibcon#read 5, iclass 29, count 0 2006.257.08:44:56.83#ibcon#about to read 6, iclass 29, count 0 2006.257.08:44:56.83#ibcon#read 6, iclass 29, count 0 2006.257.08:44:56.83#ibcon#end of sib2, iclass 29, count 0 2006.257.08:44:56.83#ibcon#*mode == 0, iclass 29, count 0 2006.257.08:44:56.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.08:44:56.83#ibcon#[27=USB\r\n] 2006.257.08:44:56.83#ibcon#*before write, iclass 29, count 0 2006.257.08:44:56.83#ibcon#enter sib2, iclass 29, count 0 2006.257.08:44:56.83#ibcon#flushed, iclass 29, count 0 2006.257.08:44:56.83#ibcon#about to write, iclass 29, count 0 2006.257.08:44:56.83#ibcon#wrote, iclass 29, count 0 2006.257.08:44:56.83#ibcon#about to read 3, iclass 29, count 0 2006.257.08:44:56.86#ibcon#read 3, iclass 29, count 0 2006.257.08:44:56.86#ibcon#about to read 4, iclass 29, count 0 2006.257.08:44:56.86#ibcon#read 4, iclass 29, count 0 2006.257.08:44:56.86#ibcon#about to read 5, iclass 29, count 0 2006.257.08:44:56.86#ibcon#read 5, iclass 29, count 0 2006.257.08:44:56.86#ibcon#about to read 6, iclass 29, count 0 2006.257.08:44:56.86#ibcon#read 6, iclass 29, count 0 2006.257.08:44:56.86#ibcon#end of sib2, iclass 29, count 0 2006.257.08:44:56.86#ibcon#*after write, iclass 29, count 0 2006.257.08:44:56.86#ibcon#*before return 0, iclass 29, count 0 2006.257.08:44:56.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:56.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.08:44:56.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.08:44:56.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.08:44:56.86$vck44/vblo=7,734.99 2006.257.08:44:56.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.08:44:56.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.08:44:56.86#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:56.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:44:56.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:44:56.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:44:56.86#ibcon#enter wrdev, iclass 31, count 0 2006.257.08:44:56.86#ibcon#first serial, iclass 31, count 0 2006.257.08:44:56.86#ibcon#enter sib2, iclass 31, count 0 2006.257.08:44:56.86#ibcon#flushed, iclass 31, count 0 2006.257.08:44:56.86#ibcon#about to write, iclass 31, count 0 2006.257.08:44:56.86#ibcon#wrote, iclass 31, count 0 2006.257.08:44:56.86#ibcon#about to read 3, iclass 31, count 0 2006.257.08:44:56.88#ibcon#read 3, iclass 31, count 0 2006.257.08:44:56.88#ibcon#about to read 4, iclass 31, count 0 2006.257.08:44:56.88#ibcon#read 4, iclass 31, count 0 2006.257.08:44:56.88#ibcon#about to read 5, iclass 31, count 0 2006.257.08:44:56.88#ibcon#read 5, iclass 31, count 0 2006.257.08:44:56.88#ibcon#about to read 6, iclass 31, count 0 2006.257.08:44:56.88#ibcon#read 6, iclass 31, count 0 2006.257.08:44:56.88#ibcon#end of sib2, iclass 31, count 0 2006.257.08:44:56.88#ibcon#*mode == 0, iclass 31, count 0 2006.257.08:44:56.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.08:44:56.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:44:56.88#ibcon#*before write, iclass 31, count 0 2006.257.08:44:56.88#ibcon#enter sib2, iclass 31, count 0 2006.257.08:44:56.88#ibcon#flushed, iclass 31, count 0 2006.257.08:44:56.88#ibcon#about to write, iclass 31, count 0 2006.257.08:44:56.88#ibcon#wrote, iclass 31, count 0 2006.257.08:44:56.88#ibcon#about to read 3, iclass 31, count 0 2006.257.08:44:56.92#ibcon#read 3, iclass 31, count 0 2006.257.08:44:56.92#ibcon#about to read 4, iclass 31, count 0 2006.257.08:44:56.92#ibcon#read 4, iclass 31, count 0 2006.257.08:44:56.92#ibcon#about to read 5, iclass 31, count 0 2006.257.08:44:56.92#ibcon#read 5, iclass 31, count 0 2006.257.08:44:56.92#ibcon#about to read 6, iclass 31, count 0 2006.257.08:44:56.92#ibcon#read 6, iclass 31, count 0 2006.257.08:44:56.92#ibcon#end of sib2, iclass 31, count 0 2006.257.08:44:56.92#ibcon#*after write, iclass 31, count 0 2006.257.08:44:56.92#ibcon#*before return 0, iclass 31, count 0 2006.257.08:44:56.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:44:56.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.08:44:56.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.08:44:56.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.08:44:56.92$vck44/vb=7,4 2006.257.08:44:56.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.08:44:56.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.08:44:56.92#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:56.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:44:56.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:44:56.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:44:56.98#ibcon#enter wrdev, iclass 33, count 2 2006.257.08:44:56.98#ibcon#first serial, iclass 33, count 2 2006.257.08:44:56.98#ibcon#enter sib2, iclass 33, count 2 2006.257.08:44:56.98#ibcon#flushed, iclass 33, count 2 2006.257.08:44:56.98#ibcon#about to write, iclass 33, count 2 2006.257.08:44:56.98#ibcon#wrote, iclass 33, count 2 2006.257.08:44:56.98#ibcon#about to read 3, iclass 33, count 2 2006.257.08:44:57.00#ibcon#read 3, iclass 33, count 2 2006.257.08:44:57.00#ibcon#about to read 4, iclass 33, count 2 2006.257.08:44:57.00#ibcon#read 4, iclass 33, count 2 2006.257.08:44:57.00#ibcon#about to read 5, iclass 33, count 2 2006.257.08:44:57.00#ibcon#read 5, iclass 33, count 2 2006.257.08:44:57.00#ibcon#about to read 6, iclass 33, count 2 2006.257.08:44:57.00#ibcon#read 6, iclass 33, count 2 2006.257.08:44:57.00#ibcon#end of sib2, iclass 33, count 2 2006.257.08:44:57.00#ibcon#*mode == 0, iclass 33, count 2 2006.257.08:44:57.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.08:44:57.00#ibcon#[27=AT07-04\r\n] 2006.257.08:44:57.00#ibcon#*before write, iclass 33, count 2 2006.257.08:44:57.00#ibcon#enter sib2, iclass 33, count 2 2006.257.08:44:57.00#ibcon#flushed, iclass 33, count 2 2006.257.08:44:57.00#ibcon#about to write, iclass 33, count 2 2006.257.08:44:57.00#ibcon#wrote, iclass 33, count 2 2006.257.08:44:57.00#ibcon#about to read 3, iclass 33, count 2 2006.257.08:44:57.03#ibcon#read 3, iclass 33, count 2 2006.257.08:44:57.03#ibcon#about to read 4, iclass 33, count 2 2006.257.08:44:57.03#ibcon#read 4, iclass 33, count 2 2006.257.08:44:57.03#ibcon#about to read 5, iclass 33, count 2 2006.257.08:44:57.03#ibcon#read 5, iclass 33, count 2 2006.257.08:44:57.03#ibcon#about to read 6, iclass 33, count 2 2006.257.08:44:57.03#ibcon#read 6, iclass 33, count 2 2006.257.08:44:57.03#ibcon#end of sib2, iclass 33, count 2 2006.257.08:44:57.03#ibcon#*after write, iclass 33, count 2 2006.257.08:44:57.03#ibcon#*before return 0, iclass 33, count 2 2006.257.08:44:57.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:44:57.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.08:44:57.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.08:44:57.03#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:57.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:44:57.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:44:57.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:44:57.15#ibcon#enter wrdev, iclass 33, count 0 2006.257.08:44:57.15#ibcon#first serial, iclass 33, count 0 2006.257.08:44:57.15#ibcon#enter sib2, iclass 33, count 0 2006.257.08:44:57.15#ibcon#flushed, iclass 33, count 0 2006.257.08:44:57.15#ibcon#about to write, iclass 33, count 0 2006.257.08:44:57.15#ibcon#wrote, iclass 33, count 0 2006.257.08:44:57.15#ibcon#about to read 3, iclass 33, count 0 2006.257.08:44:57.17#ibcon#read 3, iclass 33, count 0 2006.257.08:44:57.17#ibcon#about to read 4, iclass 33, count 0 2006.257.08:44:57.17#ibcon#read 4, iclass 33, count 0 2006.257.08:44:57.17#ibcon#about to read 5, iclass 33, count 0 2006.257.08:44:57.17#ibcon#read 5, iclass 33, count 0 2006.257.08:44:57.17#ibcon#about to read 6, iclass 33, count 0 2006.257.08:44:57.17#ibcon#read 6, iclass 33, count 0 2006.257.08:44:57.17#ibcon#end of sib2, iclass 33, count 0 2006.257.08:44:57.17#ibcon#*mode == 0, iclass 33, count 0 2006.257.08:44:57.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.08:44:57.17#ibcon#[27=USB\r\n] 2006.257.08:44:57.17#ibcon#*before write, iclass 33, count 0 2006.257.08:44:57.17#ibcon#enter sib2, iclass 33, count 0 2006.257.08:44:57.17#ibcon#flushed, iclass 33, count 0 2006.257.08:44:57.17#ibcon#about to write, iclass 33, count 0 2006.257.08:44:57.17#ibcon#wrote, iclass 33, count 0 2006.257.08:44:57.17#ibcon#about to read 3, iclass 33, count 0 2006.257.08:44:57.20#ibcon#read 3, iclass 33, count 0 2006.257.08:44:57.20#ibcon#about to read 4, iclass 33, count 0 2006.257.08:44:57.20#ibcon#read 4, iclass 33, count 0 2006.257.08:44:57.20#ibcon#about to read 5, iclass 33, count 0 2006.257.08:44:57.20#ibcon#read 5, iclass 33, count 0 2006.257.08:44:57.20#ibcon#about to read 6, iclass 33, count 0 2006.257.08:44:57.20#ibcon#read 6, iclass 33, count 0 2006.257.08:44:57.20#ibcon#end of sib2, iclass 33, count 0 2006.257.08:44:57.20#ibcon#*after write, iclass 33, count 0 2006.257.08:44:57.20#ibcon#*before return 0, iclass 33, count 0 2006.257.08:44:57.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:44:57.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.08:44:57.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.08:44:57.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.08:44:57.20$vck44/vblo=8,744.99 2006.257.08:44:57.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.08:44:57.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.08:44:57.20#ibcon#ireg 17 cls_cnt 0 2006.257.08:44:57.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:57.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:57.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:57.20#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:44:57.20#ibcon#first serial, iclass 35, count 0 2006.257.08:44:57.20#ibcon#enter sib2, iclass 35, count 0 2006.257.08:44:57.20#ibcon#flushed, iclass 35, count 0 2006.257.08:44:57.20#ibcon#about to write, iclass 35, count 0 2006.257.08:44:57.20#ibcon#wrote, iclass 35, count 0 2006.257.08:44:57.20#ibcon#about to read 3, iclass 35, count 0 2006.257.08:44:57.22#ibcon#read 3, iclass 35, count 0 2006.257.08:44:57.22#ibcon#about to read 4, iclass 35, count 0 2006.257.08:44:57.22#ibcon#read 4, iclass 35, count 0 2006.257.08:44:57.22#ibcon#about to read 5, iclass 35, count 0 2006.257.08:44:57.22#ibcon#read 5, iclass 35, count 0 2006.257.08:44:57.22#ibcon#about to read 6, iclass 35, count 0 2006.257.08:44:57.22#ibcon#read 6, iclass 35, count 0 2006.257.08:44:57.22#ibcon#end of sib2, iclass 35, count 0 2006.257.08:44:57.22#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:44:57.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:44:57.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:44:57.22#ibcon#*before write, iclass 35, count 0 2006.257.08:44:57.22#ibcon#enter sib2, iclass 35, count 0 2006.257.08:44:57.22#ibcon#flushed, iclass 35, count 0 2006.257.08:44:57.22#ibcon#about to write, iclass 35, count 0 2006.257.08:44:57.22#ibcon#wrote, iclass 35, count 0 2006.257.08:44:57.22#ibcon#about to read 3, iclass 35, count 0 2006.257.08:44:57.26#ibcon#read 3, iclass 35, count 0 2006.257.08:44:57.26#ibcon#about to read 4, iclass 35, count 0 2006.257.08:44:57.26#ibcon#read 4, iclass 35, count 0 2006.257.08:44:57.26#ibcon#about to read 5, iclass 35, count 0 2006.257.08:44:57.26#ibcon#read 5, iclass 35, count 0 2006.257.08:44:57.26#ibcon#about to read 6, iclass 35, count 0 2006.257.08:44:57.26#ibcon#read 6, iclass 35, count 0 2006.257.08:44:57.26#ibcon#end of sib2, iclass 35, count 0 2006.257.08:44:57.26#ibcon#*after write, iclass 35, count 0 2006.257.08:44:57.26#ibcon#*before return 0, iclass 35, count 0 2006.257.08:44:57.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:57.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.08:44:57.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:44:57.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:44:57.26$vck44/vb=8,4 2006.257.08:44:57.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.08:44:57.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.08:44:57.26#ibcon#ireg 11 cls_cnt 2 2006.257.08:44:57.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:57.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:57.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:57.32#ibcon#enter wrdev, iclass 37, count 2 2006.257.08:44:57.32#ibcon#first serial, iclass 37, count 2 2006.257.08:44:57.32#ibcon#enter sib2, iclass 37, count 2 2006.257.08:44:57.32#ibcon#flushed, iclass 37, count 2 2006.257.08:44:57.32#ibcon#about to write, iclass 37, count 2 2006.257.08:44:57.32#ibcon#wrote, iclass 37, count 2 2006.257.08:44:57.32#ibcon#about to read 3, iclass 37, count 2 2006.257.08:44:57.34#ibcon#read 3, iclass 37, count 2 2006.257.08:44:57.34#ibcon#about to read 4, iclass 37, count 2 2006.257.08:44:57.34#ibcon#read 4, iclass 37, count 2 2006.257.08:44:57.34#ibcon#about to read 5, iclass 37, count 2 2006.257.08:44:57.34#ibcon#read 5, iclass 37, count 2 2006.257.08:44:57.34#ibcon#about to read 6, iclass 37, count 2 2006.257.08:44:57.34#ibcon#read 6, iclass 37, count 2 2006.257.08:44:57.34#ibcon#end of sib2, iclass 37, count 2 2006.257.08:44:57.34#ibcon#*mode == 0, iclass 37, count 2 2006.257.08:44:57.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.08:44:57.34#ibcon#[27=AT08-04\r\n] 2006.257.08:44:57.34#ibcon#*before write, iclass 37, count 2 2006.257.08:44:57.34#ibcon#enter sib2, iclass 37, count 2 2006.257.08:44:57.34#ibcon#flushed, iclass 37, count 2 2006.257.08:44:57.34#ibcon#about to write, iclass 37, count 2 2006.257.08:44:57.34#ibcon#wrote, iclass 37, count 2 2006.257.08:44:57.34#ibcon#about to read 3, iclass 37, count 2 2006.257.08:44:57.37#ibcon#read 3, iclass 37, count 2 2006.257.08:44:57.37#ibcon#about to read 4, iclass 37, count 2 2006.257.08:44:57.37#ibcon#read 4, iclass 37, count 2 2006.257.08:44:57.37#ibcon#about to read 5, iclass 37, count 2 2006.257.08:44:57.37#ibcon#read 5, iclass 37, count 2 2006.257.08:44:57.37#ibcon#about to read 6, iclass 37, count 2 2006.257.08:44:57.37#ibcon#read 6, iclass 37, count 2 2006.257.08:44:57.37#ibcon#end of sib2, iclass 37, count 2 2006.257.08:44:57.37#ibcon#*after write, iclass 37, count 2 2006.257.08:44:57.37#ibcon#*before return 0, iclass 37, count 2 2006.257.08:44:57.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:57.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.08:44:57.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.08:44:57.38#ibcon#ireg 7 cls_cnt 0 2006.257.08:44:57.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:57.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:57.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:57.49#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:44:57.49#ibcon#first serial, iclass 37, count 0 2006.257.08:44:57.49#ibcon#enter sib2, iclass 37, count 0 2006.257.08:44:57.49#ibcon#flushed, iclass 37, count 0 2006.257.08:44:57.49#ibcon#about to write, iclass 37, count 0 2006.257.08:44:57.49#ibcon#wrote, iclass 37, count 0 2006.257.08:44:57.49#ibcon#about to read 3, iclass 37, count 0 2006.257.08:44:57.51#ibcon#read 3, iclass 37, count 0 2006.257.08:44:57.51#ibcon#about to read 4, iclass 37, count 0 2006.257.08:44:57.51#ibcon#read 4, iclass 37, count 0 2006.257.08:44:57.51#ibcon#about to read 5, iclass 37, count 0 2006.257.08:44:57.51#ibcon#read 5, iclass 37, count 0 2006.257.08:44:57.51#ibcon#about to read 6, iclass 37, count 0 2006.257.08:44:57.51#ibcon#read 6, iclass 37, count 0 2006.257.08:44:57.51#ibcon#end of sib2, iclass 37, count 0 2006.257.08:44:57.51#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:44:57.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:44:57.51#ibcon#[27=USB\r\n] 2006.257.08:44:57.51#ibcon#*before write, iclass 37, count 0 2006.257.08:44:57.51#ibcon#enter sib2, iclass 37, count 0 2006.257.08:44:57.51#ibcon#flushed, iclass 37, count 0 2006.257.08:44:57.51#ibcon#about to write, iclass 37, count 0 2006.257.08:44:57.51#ibcon#wrote, iclass 37, count 0 2006.257.08:44:57.51#ibcon#about to read 3, iclass 37, count 0 2006.257.08:44:57.54#ibcon#read 3, iclass 37, count 0 2006.257.08:44:57.54#ibcon#about to read 4, iclass 37, count 0 2006.257.08:44:57.54#ibcon#read 4, iclass 37, count 0 2006.257.08:44:57.54#ibcon#about to read 5, iclass 37, count 0 2006.257.08:44:57.54#ibcon#read 5, iclass 37, count 0 2006.257.08:44:57.54#ibcon#about to read 6, iclass 37, count 0 2006.257.08:44:57.54#ibcon#read 6, iclass 37, count 0 2006.257.08:44:57.54#ibcon#end of sib2, iclass 37, count 0 2006.257.08:44:57.54#ibcon#*after write, iclass 37, count 0 2006.257.08:44:57.54#ibcon#*before return 0, iclass 37, count 0 2006.257.08:44:57.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:57.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.08:44:57.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:44:57.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:44:57.54$vck44/vabw=wide 2006.257.08:44:57.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.08:44:57.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.08:44:57.54#ibcon#ireg 8 cls_cnt 0 2006.257.08:44:57.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:57.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:57.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:57.54#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:44:57.54#ibcon#first serial, iclass 39, count 0 2006.257.08:44:57.54#ibcon#enter sib2, iclass 39, count 0 2006.257.08:44:57.54#ibcon#flushed, iclass 39, count 0 2006.257.08:44:57.54#ibcon#about to write, iclass 39, count 0 2006.257.08:44:57.54#ibcon#wrote, iclass 39, count 0 2006.257.08:44:57.54#ibcon#about to read 3, iclass 39, count 0 2006.257.08:44:57.56#ibcon#read 3, iclass 39, count 0 2006.257.08:44:57.56#ibcon#about to read 4, iclass 39, count 0 2006.257.08:44:57.56#ibcon#read 4, iclass 39, count 0 2006.257.08:44:57.56#ibcon#about to read 5, iclass 39, count 0 2006.257.08:44:57.56#ibcon#read 5, iclass 39, count 0 2006.257.08:44:57.56#ibcon#about to read 6, iclass 39, count 0 2006.257.08:44:57.56#ibcon#read 6, iclass 39, count 0 2006.257.08:44:57.56#ibcon#end of sib2, iclass 39, count 0 2006.257.08:44:57.56#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:44:57.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:44:57.56#ibcon#[25=BW32\r\n] 2006.257.08:44:57.56#ibcon#*before write, iclass 39, count 0 2006.257.08:44:57.56#ibcon#enter sib2, iclass 39, count 0 2006.257.08:44:57.56#ibcon#flushed, iclass 39, count 0 2006.257.08:44:57.56#ibcon#about to write, iclass 39, count 0 2006.257.08:44:57.56#ibcon#wrote, iclass 39, count 0 2006.257.08:44:57.56#ibcon#about to read 3, iclass 39, count 0 2006.257.08:44:57.59#ibcon#read 3, iclass 39, count 0 2006.257.08:44:57.59#ibcon#about to read 4, iclass 39, count 0 2006.257.08:44:57.59#ibcon#read 4, iclass 39, count 0 2006.257.08:44:57.59#ibcon#about to read 5, iclass 39, count 0 2006.257.08:44:57.59#ibcon#read 5, iclass 39, count 0 2006.257.08:44:57.59#ibcon#about to read 6, iclass 39, count 0 2006.257.08:44:57.59#ibcon#read 6, iclass 39, count 0 2006.257.08:44:57.59#ibcon#end of sib2, iclass 39, count 0 2006.257.08:44:57.59#ibcon#*after write, iclass 39, count 0 2006.257.08:44:57.59#ibcon#*before return 0, iclass 39, count 0 2006.257.08:44:57.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:57.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:44:57.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:44:57.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:44:57.59$vck44/vbbw=wide 2006.257.08:44:57.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.08:44:57.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.08:44:57.59#ibcon#ireg 8 cls_cnt 0 2006.257.08:44:57.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:44:57.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:44:57.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:44:57.66#ibcon#enter wrdev, iclass 3, count 0 2006.257.08:44:57.66#ibcon#first serial, iclass 3, count 0 2006.257.08:44:57.66#ibcon#enter sib2, iclass 3, count 0 2006.257.08:44:57.66#ibcon#flushed, iclass 3, count 0 2006.257.08:44:57.66#ibcon#about to write, iclass 3, count 0 2006.257.08:44:57.66#ibcon#wrote, iclass 3, count 0 2006.257.08:44:57.66#ibcon#about to read 3, iclass 3, count 0 2006.257.08:44:57.68#ibcon#read 3, iclass 3, count 0 2006.257.08:44:57.68#ibcon#about to read 4, iclass 3, count 0 2006.257.08:44:57.68#ibcon#read 4, iclass 3, count 0 2006.257.08:44:57.68#ibcon#about to read 5, iclass 3, count 0 2006.257.08:44:57.68#ibcon#read 5, iclass 3, count 0 2006.257.08:44:57.68#ibcon#about to read 6, iclass 3, count 0 2006.257.08:44:57.68#ibcon#read 6, iclass 3, count 0 2006.257.08:44:57.68#ibcon#end of sib2, iclass 3, count 0 2006.257.08:44:57.68#ibcon#*mode == 0, iclass 3, count 0 2006.257.08:44:57.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.08:44:57.68#ibcon#[27=BW32\r\n] 2006.257.08:44:57.68#ibcon#*before write, iclass 3, count 0 2006.257.08:44:57.68#ibcon#enter sib2, iclass 3, count 0 2006.257.08:44:57.68#ibcon#flushed, iclass 3, count 0 2006.257.08:44:57.68#ibcon#about to write, iclass 3, count 0 2006.257.08:44:57.68#ibcon#wrote, iclass 3, count 0 2006.257.08:44:57.68#ibcon#about to read 3, iclass 3, count 0 2006.257.08:44:57.71#ibcon#read 3, iclass 3, count 0 2006.257.08:44:57.71#ibcon#about to read 4, iclass 3, count 0 2006.257.08:44:57.71#ibcon#read 4, iclass 3, count 0 2006.257.08:44:57.71#ibcon#about to read 5, iclass 3, count 0 2006.257.08:44:57.71#ibcon#read 5, iclass 3, count 0 2006.257.08:44:57.71#ibcon#about to read 6, iclass 3, count 0 2006.257.08:44:57.71#ibcon#read 6, iclass 3, count 0 2006.257.08:44:57.71#ibcon#end of sib2, iclass 3, count 0 2006.257.08:44:57.71#ibcon#*after write, iclass 3, count 0 2006.257.08:44:57.71#ibcon#*before return 0, iclass 3, count 0 2006.257.08:44:57.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:44:57.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:44:57.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.08:44:57.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.08:44:57.71$setupk4/ifdk4 2006.257.08:44:57.71$ifdk4/lo= 2006.257.08:44:57.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:44:57.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:44:57.71$ifdk4/patch= 2006.257.08:44:57.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:44:57.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:44:57.71$setupk4/!*+20s 2006.257.08:45:04.13#abcon#<5=/14 1.1 2.0 20.43 921013.2\r\n> 2006.257.08:45:04.15#abcon#{5=INTERFACE CLEAR} 2006.257.08:45:04.21#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:45:12.21$setupk4/"tpicd 2006.257.08:45:12.21$setupk4/echo=off 2006.257.08:45:12.21$setupk4/xlog=off 2006.257.08:45:12.21:!2006.257.08:45:50 2006.257.08:45:14.14#trakl#Source acquired 2006.257.08:45:14.14#flagr#flagr/antenna,acquired 2006.257.08:45:50.00:preob 2006.257.08:45:51.14/onsource/TRACKING 2006.257.08:45:51.14:!2006.257.08:46:00 2006.257.08:46:00.00:"tape 2006.257.08:46:00.00:"st=record 2006.257.08:46:00.00:data_valid=on 2006.257.08:46:00.00:midob 2006.257.08:46:00.14/onsource/TRACKING 2006.257.08:46:00.14/wx/20.42,1013.2,92 2006.257.08:46:00.28/cable/+6.4738E-03 2006.257.08:46:01.37/va/01,08,usb,yes,32,35 2006.257.08:46:01.37/va/02,07,usb,yes,35,35 2006.257.08:46:01.37/va/03,08,usb,yes,31,33 2006.257.08:46:01.37/va/04,07,usb,yes,36,38 2006.257.08:46:01.37/va/05,04,usb,yes,32,33 2006.257.08:46:01.37/va/06,04,usb,yes,36,35 2006.257.08:46:01.37/va/07,04,usb,yes,37,37 2006.257.08:46:01.37/va/08,04,usb,yes,30,37 2006.257.08:46:01.60/valo/01,524.99,yes,locked 2006.257.08:46:01.60/valo/02,534.99,yes,locked 2006.257.08:46:01.60/valo/03,564.99,yes,locked 2006.257.08:46:01.60/valo/04,624.99,yes,locked 2006.257.08:46:01.60/valo/05,734.99,yes,locked 2006.257.08:46:01.60/valo/06,814.99,yes,locked 2006.257.08:46:01.60/valo/07,864.99,yes,locked 2006.257.08:46:01.60/valo/08,884.99,yes,locked 2006.257.08:46:02.69/vb/01,04,usb,yes,32,30 2006.257.08:46:02.69/vb/02,05,usb,yes,30,30 2006.257.08:46:02.69/vb/03,04,usb,yes,31,34 2006.257.08:46:02.69/vb/04,05,usb,yes,31,30 2006.257.08:46:02.69/vb/05,04,usb,yes,28,30 2006.257.08:46:02.69/vb/06,04,usb,yes,33,29 2006.257.08:46:02.69/vb/07,04,usb,yes,32,32 2006.257.08:46:02.69/vb/08,04,usb,yes,30,33 2006.257.08:46:02.92/vblo/01,629.99,yes,locked 2006.257.08:46:02.92/vblo/02,634.99,yes,locked 2006.257.08:46:02.92/vblo/03,649.99,yes,locked 2006.257.08:46:02.92/vblo/04,679.99,yes,locked 2006.257.08:46:02.92/vblo/05,709.99,yes,locked 2006.257.08:46:02.92/vblo/06,719.99,yes,locked 2006.257.08:46:02.92/vblo/07,734.99,yes,locked 2006.257.08:46:02.92/vblo/08,744.99,yes,locked 2006.257.08:46:03.07/vabw/8 2006.257.08:46:03.22/vbbw/8 2006.257.08:46:03.31/xfe/off,on,15.0 2006.257.08:46:03.69/ifatt/23,28,28,28 2006.257.08:46:04.07/fmout-gps/S +4.64E-07 2006.257.08:46:04.11:!2006.257.08:48:10 2006.257.08:48:10.01:data_valid=off 2006.257.08:48:10.01:"et 2006.257.08:48:10.02:!+3s 2006.257.08:48:13.03:"tape 2006.257.08:48:13.03:postob 2006.257.08:48:13.20/cable/+6.4735E-03 2006.257.08:48:13.20/wx/20.38,1013.1,92 2006.257.08:48:13.26/fmout-gps/S +4.64E-07 2006.257.08:48:13.26:scan_name=257-0854,jd0609,80 2006.257.08:48:13.27:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.08:48:15.14#flagr#flagr/antenna,new-source 2006.257.08:48:15.14:checkk5 2006.257.08:48:15.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:48:15.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:48:16.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:48:16.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:48:17.15/chk_obsdata//k5ts1/T2570846??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.257.08:48:17.55/chk_obsdata//k5ts2/T2570846??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.257.08:48:17.93/chk_obsdata//k5ts3/T2570846??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.257.08:48:18.33/chk_obsdata//k5ts4/T2570846??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.257.08:48:19.06/k5log//k5ts1_log_newline 2006.257.08:48:19.77/k5log//k5ts2_log_newline 2006.257.08:48:20.50/k5log//k5ts3_log_newline 2006.257.08:48:21.21/k5log//k5ts4_log_newline 2006.257.08:48:21.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:48:21.23:setupk4=1 2006.257.08:48:21.23$setupk4/echo=on 2006.257.08:48:21.23$setupk4/pcalon 2006.257.08:48:21.23$pcalon/"no phase cal control is implemented here 2006.257.08:48:21.23$setupk4/"tpicd=stop 2006.257.08:48:21.23$setupk4/"rec=synch_on 2006.257.08:48:21.23$setupk4/"rec_mode=128 2006.257.08:48:21.23$setupk4/!* 2006.257.08:48:21.23$setupk4/recpk4 2006.257.08:48:21.23$recpk4/recpatch= 2006.257.08:48:21.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:48:21.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:48:21.24$setupk4/vck44 2006.257.08:48:21.24$vck44/valo=1,524.99 2006.257.08:48:21.24#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.08:48:21.24#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.08:48:21.24#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:21.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:21.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:21.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:21.24#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:48:21.24#ibcon#first serial, iclass 18, count 0 2006.257.08:48:21.24#ibcon#enter sib2, iclass 18, count 0 2006.257.08:48:21.24#ibcon#flushed, iclass 18, count 0 2006.257.08:48:21.24#ibcon#about to write, iclass 18, count 0 2006.257.08:48:21.24#ibcon#wrote, iclass 18, count 0 2006.257.08:48:21.24#ibcon#about to read 3, iclass 18, count 0 2006.257.08:48:21.26#ibcon#read 3, iclass 18, count 0 2006.257.08:48:21.26#ibcon#about to read 4, iclass 18, count 0 2006.257.08:48:21.26#ibcon#read 4, iclass 18, count 0 2006.257.08:48:21.26#ibcon#about to read 5, iclass 18, count 0 2006.257.08:48:21.26#ibcon#read 5, iclass 18, count 0 2006.257.08:48:21.26#ibcon#about to read 6, iclass 18, count 0 2006.257.08:48:21.26#ibcon#read 6, iclass 18, count 0 2006.257.08:48:21.26#ibcon#end of sib2, iclass 18, count 0 2006.257.08:48:21.26#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:48:21.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:48:21.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:48:21.26#ibcon#*before write, iclass 18, count 0 2006.257.08:48:21.26#ibcon#enter sib2, iclass 18, count 0 2006.257.08:48:21.26#ibcon#flushed, iclass 18, count 0 2006.257.08:48:21.26#ibcon#about to write, iclass 18, count 0 2006.257.08:48:21.26#ibcon#wrote, iclass 18, count 0 2006.257.08:48:21.26#ibcon#about to read 3, iclass 18, count 0 2006.257.08:48:21.31#ibcon#read 3, iclass 18, count 0 2006.257.08:48:21.31#ibcon#about to read 4, iclass 18, count 0 2006.257.08:48:21.31#ibcon#read 4, iclass 18, count 0 2006.257.08:48:21.31#ibcon#about to read 5, iclass 18, count 0 2006.257.08:48:21.31#ibcon#read 5, iclass 18, count 0 2006.257.08:48:21.31#ibcon#about to read 6, iclass 18, count 0 2006.257.08:48:21.31#ibcon#read 6, iclass 18, count 0 2006.257.08:48:21.31#ibcon#end of sib2, iclass 18, count 0 2006.257.08:48:21.31#ibcon#*after write, iclass 18, count 0 2006.257.08:48:21.31#ibcon#*before return 0, iclass 18, count 0 2006.257.08:48:21.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:21.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:21.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:48:21.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:48:21.31$vck44/va=1,8 2006.257.08:48:21.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.08:48:21.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.08:48:21.31#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:21.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:21.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:21.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:21.31#ibcon#enter wrdev, iclass 20, count 2 2006.257.08:48:21.31#ibcon#first serial, iclass 20, count 2 2006.257.08:48:21.31#ibcon#enter sib2, iclass 20, count 2 2006.257.08:48:21.31#ibcon#flushed, iclass 20, count 2 2006.257.08:48:21.31#ibcon#about to write, iclass 20, count 2 2006.257.08:48:21.31#ibcon#wrote, iclass 20, count 2 2006.257.08:48:21.31#ibcon#about to read 3, iclass 20, count 2 2006.257.08:48:21.33#ibcon#read 3, iclass 20, count 2 2006.257.08:48:21.33#ibcon#about to read 4, iclass 20, count 2 2006.257.08:48:21.33#ibcon#read 4, iclass 20, count 2 2006.257.08:48:21.33#ibcon#about to read 5, iclass 20, count 2 2006.257.08:48:21.33#ibcon#read 5, iclass 20, count 2 2006.257.08:48:21.33#ibcon#about to read 6, iclass 20, count 2 2006.257.08:48:21.33#ibcon#read 6, iclass 20, count 2 2006.257.08:48:21.33#ibcon#end of sib2, iclass 20, count 2 2006.257.08:48:21.33#ibcon#*mode == 0, iclass 20, count 2 2006.257.08:48:21.33#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.08:48:21.33#ibcon#[25=AT01-08\r\n] 2006.257.08:48:21.33#ibcon#*before write, iclass 20, count 2 2006.257.08:48:21.33#ibcon#enter sib2, iclass 20, count 2 2006.257.08:48:21.33#ibcon#flushed, iclass 20, count 2 2006.257.08:48:21.33#ibcon#about to write, iclass 20, count 2 2006.257.08:48:21.33#ibcon#wrote, iclass 20, count 2 2006.257.08:48:21.33#ibcon#about to read 3, iclass 20, count 2 2006.257.08:48:21.36#ibcon#read 3, iclass 20, count 2 2006.257.08:48:21.36#ibcon#about to read 4, iclass 20, count 2 2006.257.08:48:21.36#ibcon#read 4, iclass 20, count 2 2006.257.08:48:21.36#ibcon#about to read 5, iclass 20, count 2 2006.257.08:48:21.36#ibcon#read 5, iclass 20, count 2 2006.257.08:48:21.36#ibcon#about to read 6, iclass 20, count 2 2006.257.08:48:21.36#ibcon#read 6, iclass 20, count 2 2006.257.08:48:21.36#ibcon#end of sib2, iclass 20, count 2 2006.257.08:48:21.36#ibcon#*after write, iclass 20, count 2 2006.257.08:48:21.36#ibcon#*before return 0, iclass 20, count 2 2006.257.08:48:21.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:21.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:21.36#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.08:48:21.36#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:21.36#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:21.48#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:21.48#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:21.48#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:48:21.48#ibcon#first serial, iclass 20, count 0 2006.257.08:48:21.48#ibcon#enter sib2, iclass 20, count 0 2006.257.08:48:21.48#ibcon#flushed, iclass 20, count 0 2006.257.08:48:21.48#ibcon#about to write, iclass 20, count 0 2006.257.08:48:21.48#ibcon#wrote, iclass 20, count 0 2006.257.08:48:21.48#ibcon#about to read 3, iclass 20, count 0 2006.257.08:48:21.50#ibcon#read 3, iclass 20, count 0 2006.257.08:48:21.50#ibcon#about to read 4, iclass 20, count 0 2006.257.08:48:21.50#ibcon#read 4, iclass 20, count 0 2006.257.08:48:21.50#ibcon#about to read 5, iclass 20, count 0 2006.257.08:48:21.50#ibcon#read 5, iclass 20, count 0 2006.257.08:48:21.50#ibcon#about to read 6, iclass 20, count 0 2006.257.08:48:21.50#ibcon#read 6, iclass 20, count 0 2006.257.08:48:21.50#ibcon#end of sib2, iclass 20, count 0 2006.257.08:48:21.50#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:48:21.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:48:21.50#ibcon#[25=USB\r\n] 2006.257.08:48:21.50#ibcon#*before write, iclass 20, count 0 2006.257.08:48:21.50#ibcon#enter sib2, iclass 20, count 0 2006.257.08:48:21.50#ibcon#flushed, iclass 20, count 0 2006.257.08:48:21.50#ibcon#about to write, iclass 20, count 0 2006.257.08:48:21.50#ibcon#wrote, iclass 20, count 0 2006.257.08:48:21.50#ibcon#about to read 3, iclass 20, count 0 2006.257.08:48:21.53#ibcon#read 3, iclass 20, count 0 2006.257.08:48:21.53#ibcon#about to read 4, iclass 20, count 0 2006.257.08:48:21.53#ibcon#read 4, iclass 20, count 0 2006.257.08:48:21.53#ibcon#about to read 5, iclass 20, count 0 2006.257.08:48:21.53#ibcon#read 5, iclass 20, count 0 2006.257.08:48:21.53#ibcon#about to read 6, iclass 20, count 0 2006.257.08:48:21.53#ibcon#read 6, iclass 20, count 0 2006.257.08:48:21.53#ibcon#end of sib2, iclass 20, count 0 2006.257.08:48:21.53#ibcon#*after write, iclass 20, count 0 2006.257.08:48:21.53#ibcon#*before return 0, iclass 20, count 0 2006.257.08:48:21.53#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:21.53#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:21.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:48:21.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:48:21.53$vck44/valo=2,534.99 2006.257.08:48:21.53#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.08:48:21.53#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.08:48:21.53#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:21.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:21.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:21.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:21.53#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:48:21.53#ibcon#first serial, iclass 22, count 0 2006.257.08:48:21.53#ibcon#enter sib2, iclass 22, count 0 2006.257.08:48:21.53#ibcon#flushed, iclass 22, count 0 2006.257.08:48:21.53#ibcon#about to write, iclass 22, count 0 2006.257.08:48:21.53#ibcon#wrote, iclass 22, count 0 2006.257.08:48:21.53#ibcon#about to read 3, iclass 22, count 0 2006.257.08:48:21.55#ibcon#read 3, iclass 22, count 0 2006.257.08:48:21.55#ibcon#about to read 4, iclass 22, count 0 2006.257.08:48:21.55#ibcon#read 4, iclass 22, count 0 2006.257.08:48:21.55#ibcon#about to read 5, iclass 22, count 0 2006.257.08:48:21.55#ibcon#read 5, iclass 22, count 0 2006.257.08:48:21.55#ibcon#about to read 6, iclass 22, count 0 2006.257.08:48:21.55#ibcon#read 6, iclass 22, count 0 2006.257.08:48:21.55#ibcon#end of sib2, iclass 22, count 0 2006.257.08:48:21.55#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:48:21.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:48:21.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:48:21.55#ibcon#*before write, iclass 22, count 0 2006.257.08:48:21.55#ibcon#enter sib2, iclass 22, count 0 2006.257.08:48:21.55#ibcon#flushed, iclass 22, count 0 2006.257.08:48:21.55#ibcon#about to write, iclass 22, count 0 2006.257.08:48:21.55#ibcon#wrote, iclass 22, count 0 2006.257.08:48:21.55#ibcon#about to read 3, iclass 22, count 0 2006.257.08:48:21.59#ibcon#read 3, iclass 22, count 0 2006.257.08:48:21.59#ibcon#about to read 4, iclass 22, count 0 2006.257.08:48:21.59#ibcon#read 4, iclass 22, count 0 2006.257.08:48:21.59#ibcon#about to read 5, iclass 22, count 0 2006.257.08:48:21.59#ibcon#read 5, iclass 22, count 0 2006.257.08:48:21.59#ibcon#about to read 6, iclass 22, count 0 2006.257.08:48:21.59#ibcon#read 6, iclass 22, count 0 2006.257.08:48:21.59#ibcon#end of sib2, iclass 22, count 0 2006.257.08:48:21.59#ibcon#*after write, iclass 22, count 0 2006.257.08:48:21.59#ibcon#*before return 0, iclass 22, count 0 2006.257.08:48:21.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:21.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:21.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:48:21.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:48:21.59$vck44/va=2,7 2006.257.08:48:21.59#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.08:48:21.59#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.08:48:21.59#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:21.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:21.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:21.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:21.65#ibcon#enter wrdev, iclass 24, count 2 2006.257.08:48:21.65#ibcon#first serial, iclass 24, count 2 2006.257.08:48:21.65#ibcon#enter sib2, iclass 24, count 2 2006.257.08:48:21.65#ibcon#flushed, iclass 24, count 2 2006.257.08:48:21.65#ibcon#about to write, iclass 24, count 2 2006.257.08:48:21.65#ibcon#wrote, iclass 24, count 2 2006.257.08:48:21.65#ibcon#about to read 3, iclass 24, count 2 2006.257.08:48:21.67#ibcon#read 3, iclass 24, count 2 2006.257.08:48:21.67#ibcon#about to read 4, iclass 24, count 2 2006.257.08:48:21.67#ibcon#read 4, iclass 24, count 2 2006.257.08:48:21.67#ibcon#about to read 5, iclass 24, count 2 2006.257.08:48:21.67#ibcon#read 5, iclass 24, count 2 2006.257.08:48:21.67#ibcon#about to read 6, iclass 24, count 2 2006.257.08:48:21.67#ibcon#read 6, iclass 24, count 2 2006.257.08:48:21.67#ibcon#end of sib2, iclass 24, count 2 2006.257.08:48:21.67#ibcon#*mode == 0, iclass 24, count 2 2006.257.08:48:21.67#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.08:48:21.67#ibcon#[25=AT02-07\r\n] 2006.257.08:48:21.67#ibcon#*before write, iclass 24, count 2 2006.257.08:48:21.67#ibcon#enter sib2, iclass 24, count 2 2006.257.08:48:21.67#ibcon#flushed, iclass 24, count 2 2006.257.08:48:21.67#ibcon#about to write, iclass 24, count 2 2006.257.08:48:21.67#ibcon#wrote, iclass 24, count 2 2006.257.08:48:21.67#ibcon#about to read 3, iclass 24, count 2 2006.257.08:48:21.70#ibcon#read 3, iclass 24, count 2 2006.257.08:48:21.70#ibcon#about to read 4, iclass 24, count 2 2006.257.08:48:21.70#ibcon#read 4, iclass 24, count 2 2006.257.08:48:21.70#ibcon#about to read 5, iclass 24, count 2 2006.257.08:48:21.70#ibcon#read 5, iclass 24, count 2 2006.257.08:48:21.70#ibcon#about to read 6, iclass 24, count 2 2006.257.08:48:21.70#ibcon#read 6, iclass 24, count 2 2006.257.08:48:21.70#ibcon#end of sib2, iclass 24, count 2 2006.257.08:48:21.70#ibcon#*after write, iclass 24, count 2 2006.257.08:48:21.70#ibcon#*before return 0, iclass 24, count 2 2006.257.08:48:21.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:21.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:21.70#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.08:48:21.70#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:21.70#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:21.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:21.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:21.82#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:48:21.82#ibcon#first serial, iclass 24, count 0 2006.257.08:48:21.82#ibcon#enter sib2, iclass 24, count 0 2006.257.08:48:21.82#ibcon#flushed, iclass 24, count 0 2006.257.08:48:21.82#ibcon#about to write, iclass 24, count 0 2006.257.08:48:21.82#ibcon#wrote, iclass 24, count 0 2006.257.08:48:21.82#ibcon#about to read 3, iclass 24, count 0 2006.257.08:48:21.84#ibcon#read 3, iclass 24, count 0 2006.257.08:48:21.84#ibcon#about to read 4, iclass 24, count 0 2006.257.08:48:21.84#ibcon#read 4, iclass 24, count 0 2006.257.08:48:21.84#ibcon#about to read 5, iclass 24, count 0 2006.257.08:48:21.84#ibcon#read 5, iclass 24, count 0 2006.257.08:48:21.84#ibcon#about to read 6, iclass 24, count 0 2006.257.08:48:21.84#ibcon#read 6, iclass 24, count 0 2006.257.08:48:21.84#ibcon#end of sib2, iclass 24, count 0 2006.257.08:48:21.84#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:48:21.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:48:21.84#ibcon#[25=USB\r\n] 2006.257.08:48:21.84#ibcon#*before write, iclass 24, count 0 2006.257.08:48:21.84#ibcon#enter sib2, iclass 24, count 0 2006.257.08:48:21.84#ibcon#flushed, iclass 24, count 0 2006.257.08:48:21.84#ibcon#about to write, iclass 24, count 0 2006.257.08:48:21.84#ibcon#wrote, iclass 24, count 0 2006.257.08:48:21.84#ibcon#about to read 3, iclass 24, count 0 2006.257.08:48:21.87#ibcon#read 3, iclass 24, count 0 2006.257.08:48:21.87#ibcon#about to read 4, iclass 24, count 0 2006.257.08:48:21.87#ibcon#read 4, iclass 24, count 0 2006.257.08:48:21.87#ibcon#about to read 5, iclass 24, count 0 2006.257.08:48:21.87#ibcon#read 5, iclass 24, count 0 2006.257.08:48:21.87#ibcon#about to read 6, iclass 24, count 0 2006.257.08:48:21.87#ibcon#read 6, iclass 24, count 0 2006.257.08:48:21.87#ibcon#end of sib2, iclass 24, count 0 2006.257.08:48:21.87#ibcon#*after write, iclass 24, count 0 2006.257.08:48:21.87#ibcon#*before return 0, iclass 24, count 0 2006.257.08:48:21.87#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:21.87#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:21.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:48:21.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:48:21.87$vck44/valo=3,564.99 2006.257.08:48:21.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.08:48:21.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.08:48:21.87#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:21.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:21.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:21.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:21.87#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:48:21.87#ibcon#first serial, iclass 26, count 0 2006.257.08:48:21.87#ibcon#enter sib2, iclass 26, count 0 2006.257.08:48:21.87#ibcon#flushed, iclass 26, count 0 2006.257.08:48:21.87#ibcon#about to write, iclass 26, count 0 2006.257.08:48:21.87#ibcon#wrote, iclass 26, count 0 2006.257.08:48:21.87#ibcon#about to read 3, iclass 26, count 0 2006.257.08:48:21.89#ibcon#read 3, iclass 26, count 0 2006.257.08:48:21.89#ibcon#about to read 4, iclass 26, count 0 2006.257.08:48:21.89#ibcon#read 4, iclass 26, count 0 2006.257.08:48:21.89#ibcon#about to read 5, iclass 26, count 0 2006.257.08:48:21.89#ibcon#read 5, iclass 26, count 0 2006.257.08:48:21.89#ibcon#about to read 6, iclass 26, count 0 2006.257.08:48:21.89#ibcon#read 6, iclass 26, count 0 2006.257.08:48:21.89#ibcon#end of sib2, iclass 26, count 0 2006.257.08:48:21.89#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:48:21.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:48:21.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:48:21.89#ibcon#*before write, iclass 26, count 0 2006.257.08:48:21.89#ibcon#enter sib2, iclass 26, count 0 2006.257.08:48:21.89#ibcon#flushed, iclass 26, count 0 2006.257.08:48:21.89#ibcon#about to write, iclass 26, count 0 2006.257.08:48:21.89#ibcon#wrote, iclass 26, count 0 2006.257.08:48:21.89#ibcon#about to read 3, iclass 26, count 0 2006.257.08:48:21.93#ibcon#read 3, iclass 26, count 0 2006.257.08:48:21.93#ibcon#about to read 4, iclass 26, count 0 2006.257.08:48:21.93#ibcon#read 4, iclass 26, count 0 2006.257.08:48:21.93#ibcon#about to read 5, iclass 26, count 0 2006.257.08:48:21.93#ibcon#read 5, iclass 26, count 0 2006.257.08:48:21.93#ibcon#about to read 6, iclass 26, count 0 2006.257.08:48:21.93#ibcon#read 6, iclass 26, count 0 2006.257.08:48:21.93#ibcon#end of sib2, iclass 26, count 0 2006.257.08:48:21.93#ibcon#*after write, iclass 26, count 0 2006.257.08:48:21.93#ibcon#*before return 0, iclass 26, count 0 2006.257.08:48:21.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:21.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:21.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:48:21.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:48:21.93$vck44/va=3,8 2006.257.08:48:21.93#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.08:48:21.93#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.08:48:21.93#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:21.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:21.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:21.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:21.99#ibcon#enter wrdev, iclass 28, count 2 2006.257.08:48:21.99#ibcon#first serial, iclass 28, count 2 2006.257.08:48:21.99#ibcon#enter sib2, iclass 28, count 2 2006.257.08:48:21.99#ibcon#flushed, iclass 28, count 2 2006.257.08:48:21.99#ibcon#about to write, iclass 28, count 2 2006.257.08:48:21.99#ibcon#wrote, iclass 28, count 2 2006.257.08:48:21.99#ibcon#about to read 3, iclass 28, count 2 2006.257.08:48:22.01#ibcon#read 3, iclass 28, count 2 2006.257.08:48:22.01#ibcon#about to read 4, iclass 28, count 2 2006.257.08:48:22.01#ibcon#read 4, iclass 28, count 2 2006.257.08:48:22.01#ibcon#about to read 5, iclass 28, count 2 2006.257.08:48:22.01#ibcon#read 5, iclass 28, count 2 2006.257.08:48:22.01#ibcon#about to read 6, iclass 28, count 2 2006.257.08:48:22.01#ibcon#read 6, iclass 28, count 2 2006.257.08:48:22.01#ibcon#end of sib2, iclass 28, count 2 2006.257.08:48:22.01#ibcon#*mode == 0, iclass 28, count 2 2006.257.08:48:22.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.08:48:22.01#ibcon#[25=AT03-08\r\n] 2006.257.08:48:22.01#ibcon#*before write, iclass 28, count 2 2006.257.08:48:22.01#ibcon#enter sib2, iclass 28, count 2 2006.257.08:48:22.01#ibcon#flushed, iclass 28, count 2 2006.257.08:48:22.01#ibcon#about to write, iclass 28, count 2 2006.257.08:48:22.01#ibcon#wrote, iclass 28, count 2 2006.257.08:48:22.01#ibcon#about to read 3, iclass 28, count 2 2006.257.08:48:22.04#ibcon#read 3, iclass 28, count 2 2006.257.08:48:22.04#ibcon#about to read 4, iclass 28, count 2 2006.257.08:48:22.04#ibcon#read 4, iclass 28, count 2 2006.257.08:48:22.04#ibcon#about to read 5, iclass 28, count 2 2006.257.08:48:22.04#ibcon#read 5, iclass 28, count 2 2006.257.08:48:22.04#ibcon#about to read 6, iclass 28, count 2 2006.257.08:48:22.04#ibcon#read 6, iclass 28, count 2 2006.257.08:48:22.04#ibcon#end of sib2, iclass 28, count 2 2006.257.08:48:22.04#ibcon#*after write, iclass 28, count 2 2006.257.08:48:22.04#ibcon#*before return 0, iclass 28, count 2 2006.257.08:48:22.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:22.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:22.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.08:48:22.04#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:22.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:22.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:22.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:22.16#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:48:22.16#ibcon#first serial, iclass 28, count 0 2006.257.08:48:22.16#ibcon#enter sib2, iclass 28, count 0 2006.257.08:48:22.16#ibcon#flushed, iclass 28, count 0 2006.257.08:48:22.16#ibcon#about to write, iclass 28, count 0 2006.257.08:48:22.16#ibcon#wrote, iclass 28, count 0 2006.257.08:48:22.16#ibcon#about to read 3, iclass 28, count 0 2006.257.08:48:22.18#ibcon#read 3, iclass 28, count 0 2006.257.08:48:22.18#ibcon#about to read 4, iclass 28, count 0 2006.257.08:48:22.18#ibcon#read 4, iclass 28, count 0 2006.257.08:48:22.18#ibcon#about to read 5, iclass 28, count 0 2006.257.08:48:22.18#ibcon#read 5, iclass 28, count 0 2006.257.08:48:22.18#ibcon#about to read 6, iclass 28, count 0 2006.257.08:48:22.18#ibcon#read 6, iclass 28, count 0 2006.257.08:48:22.18#ibcon#end of sib2, iclass 28, count 0 2006.257.08:48:22.18#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:48:22.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:48:22.18#ibcon#[25=USB\r\n] 2006.257.08:48:22.18#ibcon#*before write, iclass 28, count 0 2006.257.08:48:22.18#ibcon#enter sib2, iclass 28, count 0 2006.257.08:48:22.18#ibcon#flushed, iclass 28, count 0 2006.257.08:48:22.18#ibcon#about to write, iclass 28, count 0 2006.257.08:48:22.18#ibcon#wrote, iclass 28, count 0 2006.257.08:48:22.18#ibcon#about to read 3, iclass 28, count 0 2006.257.08:48:22.21#ibcon#read 3, iclass 28, count 0 2006.257.08:48:22.21#ibcon#about to read 4, iclass 28, count 0 2006.257.08:48:22.21#ibcon#read 4, iclass 28, count 0 2006.257.08:48:22.21#ibcon#about to read 5, iclass 28, count 0 2006.257.08:48:22.21#ibcon#read 5, iclass 28, count 0 2006.257.08:48:22.21#ibcon#about to read 6, iclass 28, count 0 2006.257.08:48:22.21#ibcon#read 6, iclass 28, count 0 2006.257.08:48:22.21#ibcon#end of sib2, iclass 28, count 0 2006.257.08:48:22.21#ibcon#*after write, iclass 28, count 0 2006.257.08:48:22.21#ibcon#*before return 0, iclass 28, count 0 2006.257.08:48:22.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:22.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:22.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:48:22.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:48:22.21$vck44/valo=4,624.99 2006.257.08:48:22.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.08:48:22.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.08:48:22.21#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:22.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:22.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:22.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:22.21#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:48:22.21#ibcon#first serial, iclass 30, count 0 2006.257.08:48:22.21#ibcon#enter sib2, iclass 30, count 0 2006.257.08:48:22.21#ibcon#flushed, iclass 30, count 0 2006.257.08:48:22.21#ibcon#about to write, iclass 30, count 0 2006.257.08:48:22.21#ibcon#wrote, iclass 30, count 0 2006.257.08:48:22.21#ibcon#about to read 3, iclass 30, count 0 2006.257.08:48:22.23#ibcon#read 3, iclass 30, count 0 2006.257.08:48:22.23#ibcon#about to read 4, iclass 30, count 0 2006.257.08:48:22.23#ibcon#read 4, iclass 30, count 0 2006.257.08:48:22.23#ibcon#about to read 5, iclass 30, count 0 2006.257.08:48:22.23#ibcon#read 5, iclass 30, count 0 2006.257.08:48:22.23#ibcon#about to read 6, iclass 30, count 0 2006.257.08:48:22.23#ibcon#read 6, iclass 30, count 0 2006.257.08:48:22.23#ibcon#end of sib2, iclass 30, count 0 2006.257.08:48:22.23#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:48:22.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:48:22.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:48:22.23#ibcon#*before write, iclass 30, count 0 2006.257.08:48:22.23#ibcon#enter sib2, iclass 30, count 0 2006.257.08:48:22.23#ibcon#flushed, iclass 30, count 0 2006.257.08:48:22.23#ibcon#about to write, iclass 30, count 0 2006.257.08:48:22.23#ibcon#wrote, iclass 30, count 0 2006.257.08:48:22.23#ibcon#about to read 3, iclass 30, count 0 2006.257.08:48:22.27#ibcon#read 3, iclass 30, count 0 2006.257.08:48:22.27#ibcon#about to read 4, iclass 30, count 0 2006.257.08:48:22.27#ibcon#read 4, iclass 30, count 0 2006.257.08:48:22.27#ibcon#about to read 5, iclass 30, count 0 2006.257.08:48:22.27#ibcon#read 5, iclass 30, count 0 2006.257.08:48:22.27#ibcon#about to read 6, iclass 30, count 0 2006.257.08:48:22.27#ibcon#read 6, iclass 30, count 0 2006.257.08:48:22.27#ibcon#end of sib2, iclass 30, count 0 2006.257.08:48:22.27#ibcon#*after write, iclass 30, count 0 2006.257.08:48:22.27#ibcon#*before return 0, iclass 30, count 0 2006.257.08:48:22.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:22.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:22.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:48:22.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:48:22.27$vck44/va=4,7 2006.257.08:48:22.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.08:48:22.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.08:48:22.27#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:22.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:22.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:22.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:22.33#ibcon#enter wrdev, iclass 32, count 2 2006.257.08:48:22.33#ibcon#first serial, iclass 32, count 2 2006.257.08:48:22.33#ibcon#enter sib2, iclass 32, count 2 2006.257.08:48:22.33#ibcon#flushed, iclass 32, count 2 2006.257.08:48:22.33#ibcon#about to write, iclass 32, count 2 2006.257.08:48:22.33#ibcon#wrote, iclass 32, count 2 2006.257.08:48:22.33#ibcon#about to read 3, iclass 32, count 2 2006.257.08:48:22.35#ibcon#read 3, iclass 32, count 2 2006.257.08:48:22.35#ibcon#about to read 4, iclass 32, count 2 2006.257.08:48:22.35#ibcon#read 4, iclass 32, count 2 2006.257.08:48:22.35#ibcon#about to read 5, iclass 32, count 2 2006.257.08:48:22.35#ibcon#read 5, iclass 32, count 2 2006.257.08:48:22.35#ibcon#about to read 6, iclass 32, count 2 2006.257.08:48:22.35#ibcon#read 6, iclass 32, count 2 2006.257.08:48:22.35#ibcon#end of sib2, iclass 32, count 2 2006.257.08:48:22.35#ibcon#*mode == 0, iclass 32, count 2 2006.257.08:48:22.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.08:48:22.35#ibcon#[25=AT04-07\r\n] 2006.257.08:48:22.35#ibcon#*before write, iclass 32, count 2 2006.257.08:48:22.35#ibcon#enter sib2, iclass 32, count 2 2006.257.08:48:22.35#ibcon#flushed, iclass 32, count 2 2006.257.08:48:22.35#ibcon#about to write, iclass 32, count 2 2006.257.08:48:22.35#ibcon#wrote, iclass 32, count 2 2006.257.08:48:22.35#ibcon#about to read 3, iclass 32, count 2 2006.257.08:48:22.38#ibcon#read 3, iclass 32, count 2 2006.257.08:48:22.38#ibcon#about to read 4, iclass 32, count 2 2006.257.08:48:22.38#ibcon#read 4, iclass 32, count 2 2006.257.08:48:22.38#ibcon#about to read 5, iclass 32, count 2 2006.257.08:48:22.38#ibcon#read 5, iclass 32, count 2 2006.257.08:48:22.38#ibcon#about to read 6, iclass 32, count 2 2006.257.08:48:22.38#ibcon#read 6, iclass 32, count 2 2006.257.08:48:22.38#ibcon#end of sib2, iclass 32, count 2 2006.257.08:48:22.38#ibcon#*after write, iclass 32, count 2 2006.257.08:48:22.38#ibcon#*before return 0, iclass 32, count 2 2006.257.08:48:22.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:22.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:22.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.08:48:22.38#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:22.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:22.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:22.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:22.50#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:48:22.50#ibcon#first serial, iclass 32, count 0 2006.257.08:48:22.50#ibcon#enter sib2, iclass 32, count 0 2006.257.08:48:22.50#ibcon#flushed, iclass 32, count 0 2006.257.08:48:22.50#ibcon#about to write, iclass 32, count 0 2006.257.08:48:22.50#ibcon#wrote, iclass 32, count 0 2006.257.08:48:22.50#ibcon#about to read 3, iclass 32, count 0 2006.257.08:48:22.52#ibcon#read 3, iclass 32, count 0 2006.257.08:48:22.52#ibcon#about to read 4, iclass 32, count 0 2006.257.08:48:22.52#ibcon#read 4, iclass 32, count 0 2006.257.08:48:22.52#ibcon#about to read 5, iclass 32, count 0 2006.257.08:48:22.52#ibcon#read 5, iclass 32, count 0 2006.257.08:48:22.52#ibcon#about to read 6, iclass 32, count 0 2006.257.08:48:22.52#ibcon#read 6, iclass 32, count 0 2006.257.08:48:22.52#ibcon#end of sib2, iclass 32, count 0 2006.257.08:48:22.52#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:48:22.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:48:22.52#ibcon#[25=USB\r\n] 2006.257.08:48:22.52#ibcon#*before write, iclass 32, count 0 2006.257.08:48:22.52#ibcon#enter sib2, iclass 32, count 0 2006.257.08:48:22.52#ibcon#flushed, iclass 32, count 0 2006.257.08:48:22.52#ibcon#about to write, iclass 32, count 0 2006.257.08:48:22.52#ibcon#wrote, iclass 32, count 0 2006.257.08:48:22.52#ibcon#about to read 3, iclass 32, count 0 2006.257.08:48:22.55#ibcon#read 3, iclass 32, count 0 2006.257.08:48:22.55#ibcon#about to read 4, iclass 32, count 0 2006.257.08:48:22.55#ibcon#read 4, iclass 32, count 0 2006.257.08:48:22.55#ibcon#about to read 5, iclass 32, count 0 2006.257.08:48:22.55#ibcon#read 5, iclass 32, count 0 2006.257.08:48:22.55#ibcon#about to read 6, iclass 32, count 0 2006.257.08:48:22.55#ibcon#read 6, iclass 32, count 0 2006.257.08:48:22.55#ibcon#end of sib2, iclass 32, count 0 2006.257.08:48:22.55#ibcon#*after write, iclass 32, count 0 2006.257.08:48:22.55#ibcon#*before return 0, iclass 32, count 0 2006.257.08:48:22.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:22.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:22.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:48:22.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:48:22.55$vck44/valo=5,734.99 2006.257.08:48:22.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.08:48:22.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.08:48:22.55#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:22.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:22.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:22.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:22.55#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:48:22.55#ibcon#first serial, iclass 34, count 0 2006.257.08:48:22.55#ibcon#enter sib2, iclass 34, count 0 2006.257.08:48:22.55#ibcon#flushed, iclass 34, count 0 2006.257.08:48:22.55#ibcon#about to write, iclass 34, count 0 2006.257.08:48:22.55#ibcon#wrote, iclass 34, count 0 2006.257.08:48:22.55#ibcon#about to read 3, iclass 34, count 0 2006.257.08:48:22.57#ibcon#read 3, iclass 34, count 0 2006.257.08:48:22.57#ibcon#about to read 4, iclass 34, count 0 2006.257.08:48:22.57#ibcon#read 4, iclass 34, count 0 2006.257.08:48:22.57#ibcon#about to read 5, iclass 34, count 0 2006.257.08:48:22.57#ibcon#read 5, iclass 34, count 0 2006.257.08:48:22.57#ibcon#about to read 6, iclass 34, count 0 2006.257.08:48:22.57#ibcon#read 6, iclass 34, count 0 2006.257.08:48:22.57#ibcon#end of sib2, iclass 34, count 0 2006.257.08:48:22.57#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:48:22.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:48:22.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:48:22.57#ibcon#*before write, iclass 34, count 0 2006.257.08:48:22.57#ibcon#enter sib2, iclass 34, count 0 2006.257.08:48:22.57#ibcon#flushed, iclass 34, count 0 2006.257.08:48:22.57#ibcon#about to write, iclass 34, count 0 2006.257.08:48:22.57#ibcon#wrote, iclass 34, count 0 2006.257.08:48:22.57#ibcon#about to read 3, iclass 34, count 0 2006.257.08:48:22.61#ibcon#read 3, iclass 34, count 0 2006.257.08:48:22.61#ibcon#about to read 4, iclass 34, count 0 2006.257.08:48:22.61#ibcon#read 4, iclass 34, count 0 2006.257.08:48:22.61#ibcon#about to read 5, iclass 34, count 0 2006.257.08:48:22.61#ibcon#read 5, iclass 34, count 0 2006.257.08:48:22.61#ibcon#about to read 6, iclass 34, count 0 2006.257.08:48:22.61#ibcon#read 6, iclass 34, count 0 2006.257.08:48:22.61#ibcon#end of sib2, iclass 34, count 0 2006.257.08:48:22.61#ibcon#*after write, iclass 34, count 0 2006.257.08:48:22.61#ibcon#*before return 0, iclass 34, count 0 2006.257.08:48:22.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:22.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:22.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:48:22.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:48:22.61$vck44/va=5,4 2006.257.08:48:22.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.08:48:22.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.08:48:22.61#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:22.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:22.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:22.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:22.67#ibcon#enter wrdev, iclass 36, count 2 2006.257.08:48:22.67#ibcon#first serial, iclass 36, count 2 2006.257.08:48:22.67#ibcon#enter sib2, iclass 36, count 2 2006.257.08:48:22.67#ibcon#flushed, iclass 36, count 2 2006.257.08:48:22.67#ibcon#about to write, iclass 36, count 2 2006.257.08:48:22.67#ibcon#wrote, iclass 36, count 2 2006.257.08:48:22.67#ibcon#about to read 3, iclass 36, count 2 2006.257.08:48:22.69#ibcon#read 3, iclass 36, count 2 2006.257.08:48:22.69#ibcon#about to read 4, iclass 36, count 2 2006.257.08:48:22.69#ibcon#read 4, iclass 36, count 2 2006.257.08:48:22.69#ibcon#about to read 5, iclass 36, count 2 2006.257.08:48:22.69#ibcon#read 5, iclass 36, count 2 2006.257.08:48:22.69#ibcon#about to read 6, iclass 36, count 2 2006.257.08:48:22.69#ibcon#read 6, iclass 36, count 2 2006.257.08:48:22.69#ibcon#end of sib2, iclass 36, count 2 2006.257.08:48:22.69#ibcon#*mode == 0, iclass 36, count 2 2006.257.08:48:22.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.08:48:22.69#ibcon#[25=AT05-04\r\n] 2006.257.08:48:22.69#ibcon#*before write, iclass 36, count 2 2006.257.08:48:22.69#ibcon#enter sib2, iclass 36, count 2 2006.257.08:48:22.69#ibcon#flushed, iclass 36, count 2 2006.257.08:48:22.69#ibcon#about to write, iclass 36, count 2 2006.257.08:48:22.69#ibcon#wrote, iclass 36, count 2 2006.257.08:48:22.69#ibcon#about to read 3, iclass 36, count 2 2006.257.08:48:22.72#ibcon#read 3, iclass 36, count 2 2006.257.08:48:22.72#ibcon#about to read 4, iclass 36, count 2 2006.257.08:48:22.72#ibcon#read 4, iclass 36, count 2 2006.257.08:48:22.72#ibcon#about to read 5, iclass 36, count 2 2006.257.08:48:22.72#ibcon#read 5, iclass 36, count 2 2006.257.08:48:22.72#ibcon#about to read 6, iclass 36, count 2 2006.257.08:48:22.72#ibcon#read 6, iclass 36, count 2 2006.257.08:48:22.72#ibcon#end of sib2, iclass 36, count 2 2006.257.08:48:22.72#ibcon#*after write, iclass 36, count 2 2006.257.08:48:22.72#ibcon#*before return 0, iclass 36, count 2 2006.257.08:48:22.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:22.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:22.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.08:48:22.72#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:22.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:22.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:22.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:22.84#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:48:22.84#ibcon#first serial, iclass 36, count 0 2006.257.08:48:22.84#ibcon#enter sib2, iclass 36, count 0 2006.257.08:48:22.84#ibcon#flushed, iclass 36, count 0 2006.257.08:48:22.84#ibcon#about to write, iclass 36, count 0 2006.257.08:48:22.84#ibcon#wrote, iclass 36, count 0 2006.257.08:48:22.84#ibcon#about to read 3, iclass 36, count 0 2006.257.08:48:22.86#ibcon#read 3, iclass 36, count 0 2006.257.08:48:22.86#ibcon#about to read 4, iclass 36, count 0 2006.257.08:48:22.86#ibcon#read 4, iclass 36, count 0 2006.257.08:48:22.86#ibcon#about to read 5, iclass 36, count 0 2006.257.08:48:22.86#ibcon#read 5, iclass 36, count 0 2006.257.08:48:22.86#ibcon#about to read 6, iclass 36, count 0 2006.257.08:48:22.86#ibcon#read 6, iclass 36, count 0 2006.257.08:48:22.86#ibcon#end of sib2, iclass 36, count 0 2006.257.08:48:22.86#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:48:22.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:48:22.86#ibcon#[25=USB\r\n] 2006.257.08:48:22.86#ibcon#*before write, iclass 36, count 0 2006.257.08:48:22.86#ibcon#enter sib2, iclass 36, count 0 2006.257.08:48:22.86#ibcon#flushed, iclass 36, count 0 2006.257.08:48:22.86#ibcon#about to write, iclass 36, count 0 2006.257.08:48:22.86#ibcon#wrote, iclass 36, count 0 2006.257.08:48:22.86#ibcon#about to read 3, iclass 36, count 0 2006.257.08:48:22.89#ibcon#read 3, iclass 36, count 0 2006.257.08:48:22.89#ibcon#about to read 4, iclass 36, count 0 2006.257.08:48:22.89#ibcon#read 4, iclass 36, count 0 2006.257.08:48:22.89#ibcon#about to read 5, iclass 36, count 0 2006.257.08:48:22.89#ibcon#read 5, iclass 36, count 0 2006.257.08:48:22.89#ibcon#about to read 6, iclass 36, count 0 2006.257.08:48:22.89#ibcon#read 6, iclass 36, count 0 2006.257.08:48:22.89#ibcon#end of sib2, iclass 36, count 0 2006.257.08:48:22.89#ibcon#*after write, iclass 36, count 0 2006.257.08:48:22.89#ibcon#*before return 0, iclass 36, count 0 2006.257.08:48:22.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:22.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:22.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:48:22.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:48:22.89$vck44/valo=6,814.99 2006.257.08:48:22.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.08:48:22.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.08:48:22.89#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:22.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:22.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:22.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:22.89#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:48:22.89#ibcon#first serial, iclass 38, count 0 2006.257.08:48:22.89#ibcon#enter sib2, iclass 38, count 0 2006.257.08:48:22.89#ibcon#flushed, iclass 38, count 0 2006.257.08:48:22.89#ibcon#about to write, iclass 38, count 0 2006.257.08:48:22.89#ibcon#wrote, iclass 38, count 0 2006.257.08:48:22.89#ibcon#about to read 3, iclass 38, count 0 2006.257.08:48:22.91#ibcon#read 3, iclass 38, count 0 2006.257.08:48:22.91#ibcon#about to read 4, iclass 38, count 0 2006.257.08:48:22.91#ibcon#read 4, iclass 38, count 0 2006.257.08:48:22.91#ibcon#about to read 5, iclass 38, count 0 2006.257.08:48:22.91#ibcon#read 5, iclass 38, count 0 2006.257.08:48:22.91#ibcon#about to read 6, iclass 38, count 0 2006.257.08:48:22.91#ibcon#read 6, iclass 38, count 0 2006.257.08:48:22.91#ibcon#end of sib2, iclass 38, count 0 2006.257.08:48:22.91#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:48:22.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:48:22.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:48:22.91#ibcon#*before write, iclass 38, count 0 2006.257.08:48:22.91#ibcon#enter sib2, iclass 38, count 0 2006.257.08:48:22.91#ibcon#flushed, iclass 38, count 0 2006.257.08:48:22.91#ibcon#about to write, iclass 38, count 0 2006.257.08:48:22.91#ibcon#wrote, iclass 38, count 0 2006.257.08:48:22.91#ibcon#about to read 3, iclass 38, count 0 2006.257.08:48:22.95#ibcon#read 3, iclass 38, count 0 2006.257.08:48:22.95#ibcon#about to read 4, iclass 38, count 0 2006.257.08:48:22.95#ibcon#read 4, iclass 38, count 0 2006.257.08:48:22.95#ibcon#about to read 5, iclass 38, count 0 2006.257.08:48:22.95#ibcon#read 5, iclass 38, count 0 2006.257.08:48:22.95#ibcon#about to read 6, iclass 38, count 0 2006.257.08:48:22.95#ibcon#read 6, iclass 38, count 0 2006.257.08:48:22.95#ibcon#end of sib2, iclass 38, count 0 2006.257.08:48:22.95#ibcon#*after write, iclass 38, count 0 2006.257.08:48:22.95#ibcon#*before return 0, iclass 38, count 0 2006.257.08:48:22.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:22.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:22.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:48:22.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:48:22.95$vck44/va=6,4 2006.257.08:48:22.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.08:48:22.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.08:48:22.95#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:22.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:23.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:23.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:23.01#ibcon#enter wrdev, iclass 40, count 2 2006.257.08:48:23.01#ibcon#first serial, iclass 40, count 2 2006.257.08:48:23.01#ibcon#enter sib2, iclass 40, count 2 2006.257.08:48:23.01#ibcon#flushed, iclass 40, count 2 2006.257.08:48:23.01#ibcon#about to write, iclass 40, count 2 2006.257.08:48:23.01#ibcon#wrote, iclass 40, count 2 2006.257.08:48:23.01#ibcon#about to read 3, iclass 40, count 2 2006.257.08:48:23.03#ibcon#read 3, iclass 40, count 2 2006.257.08:48:23.03#ibcon#about to read 4, iclass 40, count 2 2006.257.08:48:23.03#ibcon#read 4, iclass 40, count 2 2006.257.08:48:23.03#ibcon#about to read 5, iclass 40, count 2 2006.257.08:48:23.03#ibcon#read 5, iclass 40, count 2 2006.257.08:48:23.03#ibcon#about to read 6, iclass 40, count 2 2006.257.08:48:23.03#ibcon#read 6, iclass 40, count 2 2006.257.08:48:23.03#ibcon#end of sib2, iclass 40, count 2 2006.257.08:48:23.03#ibcon#*mode == 0, iclass 40, count 2 2006.257.08:48:23.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.08:48:23.03#ibcon#[25=AT06-04\r\n] 2006.257.08:48:23.03#ibcon#*before write, iclass 40, count 2 2006.257.08:48:23.03#ibcon#enter sib2, iclass 40, count 2 2006.257.08:48:23.03#ibcon#flushed, iclass 40, count 2 2006.257.08:48:23.03#ibcon#about to write, iclass 40, count 2 2006.257.08:48:23.03#ibcon#wrote, iclass 40, count 2 2006.257.08:48:23.03#ibcon#about to read 3, iclass 40, count 2 2006.257.08:48:23.06#ibcon#read 3, iclass 40, count 2 2006.257.08:48:23.06#ibcon#about to read 4, iclass 40, count 2 2006.257.08:48:23.06#ibcon#read 4, iclass 40, count 2 2006.257.08:48:23.06#ibcon#about to read 5, iclass 40, count 2 2006.257.08:48:23.06#ibcon#read 5, iclass 40, count 2 2006.257.08:48:23.06#ibcon#about to read 6, iclass 40, count 2 2006.257.08:48:23.06#ibcon#read 6, iclass 40, count 2 2006.257.08:48:23.06#ibcon#end of sib2, iclass 40, count 2 2006.257.08:48:23.06#ibcon#*after write, iclass 40, count 2 2006.257.08:48:23.06#ibcon#*before return 0, iclass 40, count 2 2006.257.08:48:23.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:23.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:23.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.08:48:23.06#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:23.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:23.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:23.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:23.18#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:48:23.18#ibcon#first serial, iclass 40, count 0 2006.257.08:48:23.18#ibcon#enter sib2, iclass 40, count 0 2006.257.08:48:23.18#ibcon#flushed, iclass 40, count 0 2006.257.08:48:23.18#ibcon#about to write, iclass 40, count 0 2006.257.08:48:23.18#ibcon#wrote, iclass 40, count 0 2006.257.08:48:23.18#ibcon#about to read 3, iclass 40, count 0 2006.257.08:48:23.20#ibcon#read 3, iclass 40, count 0 2006.257.08:48:23.20#ibcon#about to read 4, iclass 40, count 0 2006.257.08:48:23.20#ibcon#read 4, iclass 40, count 0 2006.257.08:48:23.20#ibcon#about to read 5, iclass 40, count 0 2006.257.08:48:23.20#ibcon#read 5, iclass 40, count 0 2006.257.08:48:23.20#ibcon#about to read 6, iclass 40, count 0 2006.257.08:48:23.20#ibcon#read 6, iclass 40, count 0 2006.257.08:48:23.20#ibcon#end of sib2, iclass 40, count 0 2006.257.08:48:23.20#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:48:23.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:48:23.20#ibcon#[25=USB\r\n] 2006.257.08:48:23.20#ibcon#*before write, iclass 40, count 0 2006.257.08:48:23.20#ibcon#enter sib2, iclass 40, count 0 2006.257.08:48:23.20#ibcon#flushed, iclass 40, count 0 2006.257.08:48:23.20#ibcon#about to write, iclass 40, count 0 2006.257.08:48:23.20#ibcon#wrote, iclass 40, count 0 2006.257.08:48:23.20#ibcon#about to read 3, iclass 40, count 0 2006.257.08:48:23.23#ibcon#read 3, iclass 40, count 0 2006.257.08:48:23.23#ibcon#about to read 4, iclass 40, count 0 2006.257.08:48:23.23#ibcon#read 4, iclass 40, count 0 2006.257.08:48:23.23#ibcon#about to read 5, iclass 40, count 0 2006.257.08:48:23.23#ibcon#read 5, iclass 40, count 0 2006.257.08:48:23.23#ibcon#about to read 6, iclass 40, count 0 2006.257.08:48:23.23#ibcon#read 6, iclass 40, count 0 2006.257.08:48:23.23#ibcon#end of sib2, iclass 40, count 0 2006.257.08:48:23.23#ibcon#*after write, iclass 40, count 0 2006.257.08:48:23.23#ibcon#*before return 0, iclass 40, count 0 2006.257.08:48:23.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:23.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:23.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:48:23.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:48:23.23$vck44/valo=7,864.99 2006.257.08:48:23.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.08:48:23.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.08:48:23.23#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:23.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:23.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:23.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:23.23#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:48:23.23#ibcon#first serial, iclass 4, count 0 2006.257.08:48:23.23#ibcon#enter sib2, iclass 4, count 0 2006.257.08:48:23.23#ibcon#flushed, iclass 4, count 0 2006.257.08:48:23.23#ibcon#about to write, iclass 4, count 0 2006.257.08:48:23.23#ibcon#wrote, iclass 4, count 0 2006.257.08:48:23.23#ibcon#about to read 3, iclass 4, count 0 2006.257.08:48:23.25#ibcon#read 3, iclass 4, count 0 2006.257.08:48:23.25#ibcon#about to read 4, iclass 4, count 0 2006.257.08:48:23.25#ibcon#read 4, iclass 4, count 0 2006.257.08:48:23.25#ibcon#about to read 5, iclass 4, count 0 2006.257.08:48:23.25#ibcon#read 5, iclass 4, count 0 2006.257.08:48:23.25#ibcon#about to read 6, iclass 4, count 0 2006.257.08:48:23.25#ibcon#read 6, iclass 4, count 0 2006.257.08:48:23.25#ibcon#end of sib2, iclass 4, count 0 2006.257.08:48:23.25#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:48:23.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:48:23.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:48:23.25#ibcon#*before write, iclass 4, count 0 2006.257.08:48:23.25#ibcon#enter sib2, iclass 4, count 0 2006.257.08:48:23.25#ibcon#flushed, iclass 4, count 0 2006.257.08:48:23.25#ibcon#about to write, iclass 4, count 0 2006.257.08:48:23.25#ibcon#wrote, iclass 4, count 0 2006.257.08:48:23.25#ibcon#about to read 3, iclass 4, count 0 2006.257.08:48:23.29#ibcon#read 3, iclass 4, count 0 2006.257.08:48:23.29#ibcon#about to read 4, iclass 4, count 0 2006.257.08:48:23.29#ibcon#read 4, iclass 4, count 0 2006.257.08:48:23.29#ibcon#about to read 5, iclass 4, count 0 2006.257.08:48:23.29#ibcon#read 5, iclass 4, count 0 2006.257.08:48:23.29#ibcon#about to read 6, iclass 4, count 0 2006.257.08:48:23.29#ibcon#read 6, iclass 4, count 0 2006.257.08:48:23.29#ibcon#end of sib2, iclass 4, count 0 2006.257.08:48:23.29#ibcon#*after write, iclass 4, count 0 2006.257.08:48:23.29#ibcon#*before return 0, iclass 4, count 0 2006.257.08:48:23.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:23.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:23.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:48:23.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:48:23.29$vck44/va=7,4 2006.257.08:48:23.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.08:48:23.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.08:48:23.29#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:23.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:23.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:23.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:23.35#ibcon#enter wrdev, iclass 6, count 2 2006.257.08:48:23.35#ibcon#first serial, iclass 6, count 2 2006.257.08:48:23.35#ibcon#enter sib2, iclass 6, count 2 2006.257.08:48:23.35#ibcon#flushed, iclass 6, count 2 2006.257.08:48:23.35#ibcon#about to write, iclass 6, count 2 2006.257.08:48:23.35#ibcon#wrote, iclass 6, count 2 2006.257.08:48:23.35#ibcon#about to read 3, iclass 6, count 2 2006.257.08:48:23.37#ibcon#read 3, iclass 6, count 2 2006.257.08:48:23.37#ibcon#about to read 4, iclass 6, count 2 2006.257.08:48:23.37#ibcon#read 4, iclass 6, count 2 2006.257.08:48:23.37#ibcon#about to read 5, iclass 6, count 2 2006.257.08:48:23.37#ibcon#read 5, iclass 6, count 2 2006.257.08:48:23.37#ibcon#about to read 6, iclass 6, count 2 2006.257.08:48:23.37#ibcon#read 6, iclass 6, count 2 2006.257.08:48:23.37#ibcon#end of sib2, iclass 6, count 2 2006.257.08:48:23.37#ibcon#*mode == 0, iclass 6, count 2 2006.257.08:48:23.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.08:48:23.37#ibcon#[25=AT07-04\r\n] 2006.257.08:48:23.37#ibcon#*before write, iclass 6, count 2 2006.257.08:48:23.37#ibcon#enter sib2, iclass 6, count 2 2006.257.08:48:23.37#ibcon#flushed, iclass 6, count 2 2006.257.08:48:23.37#ibcon#about to write, iclass 6, count 2 2006.257.08:48:23.37#ibcon#wrote, iclass 6, count 2 2006.257.08:48:23.37#ibcon#about to read 3, iclass 6, count 2 2006.257.08:48:23.40#ibcon#read 3, iclass 6, count 2 2006.257.08:48:23.40#ibcon#about to read 4, iclass 6, count 2 2006.257.08:48:23.40#ibcon#read 4, iclass 6, count 2 2006.257.08:48:23.40#ibcon#about to read 5, iclass 6, count 2 2006.257.08:48:23.40#ibcon#read 5, iclass 6, count 2 2006.257.08:48:23.40#ibcon#about to read 6, iclass 6, count 2 2006.257.08:48:23.40#ibcon#read 6, iclass 6, count 2 2006.257.08:48:23.40#ibcon#end of sib2, iclass 6, count 2 2006.257.08:48:23.40#ibcon#*after write, iclass 6, count 2 2006.257.08:48:23.40#ibcon#*before return 0, iclass 6, count 2 2006.257.08:48:23.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:23.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:23.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.08:48:23.40#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:23.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:23.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:23.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:23.52#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:48:23.52#ibcon#first serial, iclass 6, count 0 2006.257.08:48:23.52#ibcon#enter sib2, iclass 6, count 0 2006.257.08:48:23.52#ibcon#flushed, iclass 6, count 0 2006.257.08:48:23.52#ibcon#about to write, iclass 6, count 0 2006.257.08:48:23.52#ibcon#wrote, iclass 6, count 0 2006.257.08:48:23.52#ibcon#about to read 3, iclass 6, count 0 2006.257.08:48:23.54#ibcon#read 3, iclass 6, count 0 2006.257.08:48:23.54#ibcon#about to read 4, iclass 6, count 0 2006.257.08:48:23.54#ibcon#read 4, iclass 6, count 0 2006.257.08:48:23.54#ibcon#about to read 5, iclass 6, count 0 2006.257.08:48:23.54#ibcon#read 5, iclass 6, count 0 2006.257.08:48:23.54#ibcon#about to read 6, iclass 6, count 0 2006.257.08:48:23.54#ibcon#read 6, iclass 6, count 0 2006.257.08:48:23.54#ibcon#end of sib2, iclass 6, count 0 2006.257.08:48:23.54#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:48:23.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:48:23.54#ibcon#[25=USB\r\n] 2006.257.08:48:23.54#ibcon#*before write, iclass 6, count 0 2006.257.08:48:23.54#ibcon#enter sib2, iclass 6, count 0 2006.257.08:48:23.54#ibcon#flushed, iclass 6, count 0 2006.257.08:48:23.54#ibcon#about to write, iclass 6, count 0 2006.257.08:48:23.54#ibcon#wrote, iclass 6, count 0 2006.257.08:48:23.54#ibcon#about to read 3, iclass 6, count 0 2006.257.08:48:23.57#ibcon#read 3, iclass 6, count 0 2006.257.08:48:23.57#ibcon#about to read 4, iclass 6, count 0 2006.257.08:48:23.57#ibcon#read 4, iclass 6, count 0 2006.257.08:48:23.57#ibcon#about to read 5, iclass 6, count 0 2006.257.08:48:23.57#ibcon#read 5, iclass 6, count 0 2006.257.08:48:23.57#ibcon#about to read 6, iclass 6, count 0 2006.257.08:48:23.57#ibcon#read 6, iclass 6, count 0 2006.257.08:48:23.57#ibcon#end of sib2, iclass 6, count 0 2006.257.08:48:23.57#ibcon#*after write, iclass 6, count 0 2006.257.08:48:23.57#ibcon#*before return 0, iclass 6, count 0 2006.257.08:48:23.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:23.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:23.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:48:23.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:48:23.57$vck44/valo=8,884.99 2006.257.08:48:23.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.08:48:23.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.08:48:23.57#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:23.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:23.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:23.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:23.57#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:48:23.57#ibcon#first serial, iclass 10, count 0 2006.257.08:48:23.57#ibcon#enter sib2, iclass 10, count 0 2006.257.08:48:23.57#ibcon#flushed, iclass 10, count 0 2006.257.08:48:23.57#ibcon#about to write, iclass 10, count 0 2006.257.08:48:23.57#ibcon#wrote, iclass 10, count 0 2006.257.08:48:23.57#ibcon#about to read 3, iclass 10, count 0 2006.257.08:48:23.59#ibcon#read 3, iclass 10, count 0 2006.257.08:48:23.59#ibcon#about to read 4, iclass 10, count 0 2006.257.08:48:23.59#ibcon#read 4, iclass 10, count 0 2006.257.08:48:23.59#ibcon#about to read 5, iclass 10, count 0 2006.257.08:48:23.59#ibcon#read 5, iclass 10, count 0 2006.257.08:48:23.59#ibcon#about to read 6, iclass 10, count 0 2006.257.08:48:23.59#ibcon#read 6, iclass 10, count 0 2006.257.08:48:23.59#ibcon#end of sib2, iclass 10, count 0 2006.257.08:48:23.59#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:48:23.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:48:23.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:48:23.59#ibcon#*before write, iclass 10, count 0 2006.257.08:48:23.59#ibcon#enter sib2, iclass 10, count 0 2006.257.08:48:23.59#ibcon#flushed, iclass 10, count 0 2006.257.08:48:23.59#ibcon#about to write, iclass 10, count 0 2006.257.08:48:23.59#ibcon#wrote, iclass 10, count 0 2006.257.08:48:23.59#ibcon#about to read 3, iclass 10, count 0 2006.257.08:48:23.63#ibcon#read 3, iclass 10, count 0 2006.257.08:48:23.63#ibcon#about to read 4, iclass 10, count 0 2006.257.08:48:23.63#ibcon#read 4, iclass 10, count 0 2006.257.08:48:23.63#ibcon#about to read 5, iclass 10, count 0 2006.257.08:48:23.63#ibcon#read 5, iclass 10, count 0 2006.257.08:48:23.63#ibcon#about to read 6, iclass 10, count 0 2006.257.08:48:23.63#ibcon#read 6, iclass 10, count 0 2006.257.08:48:23.63#ibcon#end of sib2, iclass 10, count 0 2006.257.08:48:23.63#ibcon#*after write, iclass 10, count 0 2006.257.08:48:23.63#ibcon#*before return 0, iclass 10, count 0 2006.257.08:48:23.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:23.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:23.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:48:23.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:48:23.63$vck44/va=8,4 2006.257.08:48:23.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.08:48:23.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.08:48:23.63#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:23.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:48:23.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:48:23.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:48:23.69#ibcon#enter wrdev, iclass 12, count 2 2006.257.08:48:23.69#ibcon#first serial, iclass 12, count 2 2006.257.08:48:23.69#ibcon#enter sib2, iclass 12, count 2 2006.257.08:48:23.69#ibcon#flushed, iclass 12, count 2 2006.257.08:48:23.69#ibcon#about to write, iclass 12, count 2 2006.257.08:48:23.69#ibcon#wrote, iclass 12, count 2 2006.257.08:48:23.69#ibcon#about to read 3, iclass 12, count 2 2006.257.08:48:23.71#ibcon#read 3, iclass 12, count 2 2006.257.08:48:23.71#ibcon#about to read 4, iclass 12, count 2 2006.257.08:48:23.71#ibcon#read 4, iclass 12, count 2 2006.257.08:48:23.71#ibcon#about to read 5, iclass 12, count 2 2006.257.08:48:23.71#ibcon#read 5, iclass 12, count 2 2006.257.08:48:23.71#ibcon#about to read 6, iclass 12, count 2 2006.257.08:48:23.71#ibcon#read 6, iclass 12, count 2 2006.257.08:48:23.71#ibcon#end of sib2, iclass 12, count 2 2006.257.08:48:23.71#ibcon#*mode == 0, iclass 12, count 2 2006.257.08:48:23.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.08:48:23.71#ibcon#[25=AT08-04\r\n] 2006.257.08:48:23.71#ibcon#*before write, iclass 12, count 2 2006.257.08:48:23.71#ibcon#enter sib2, iclass 12, count 2 2006.257.08:48:23.71#ibcon#flushed, iclass 12, count 2 2006.257.08:48:23.71#ibcon#about to write, iclass 12, count 2 2006.257.08:48:23.71#ibcon#wrote, iclass 12, count 2 2006.257.08:48:23.71#ibcon#about to read 3, iclass 12, count 2 2006.257.08:48:23.74#ibcon#read 3, iclass 12, count 2 2006.257.08:48:23.74#ibcon#about to read 4, iclass 12, count 2 2006.257.08:48:23.74#ibcon#read 4, iclass 12, count 2 2006.257.08:48:23.74#ibcon#about to read 5, iclass 12, count 2 2006.257.08:48:23.74#ibcon#read 5, iclass 12, count 2 2006.257.08:48:23.74#ibcon#about to read 6, iclass 12, count 2 2006.257.08:48:23.74#ibcon#read 6, iclass 12, count 2 2006.257.08:48:23.74#ibcon#end of sib2, iclass 12, count 2 2006.257.08:48:23.74#ibcon#*after write, iclass 12, count 2 2006.257.08:48:23.74#ibcon#*before return 0, iclass 12, count 2 2006.257.08:48:23.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:48:23.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.08:48:23.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.08:48:23.74#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:23.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:48:23.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:48:23.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:48:23.86#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:48:23.86#ibcon#first serial, iclass 12, count 0 2006.257.08:48:23.86#ibcon#enter sib2, iclass 12, count 0 2006.257.08:48:23.86#ibcon#flushed, iclass 12, count 0 2006.257.08:48:23.86#ibcon#about to write, iclass 12, count 0 2006.257.08:48:23.86#ibcon#wrote, iclass 12, count 0 2006.257.08:48:23.86#ibcon#about to read 3, iclass 12, count 0 2006.257.08:48:23.88#ibcon#read 3, iclass 12, count 0 2006.257.08:48:23.88#ibcon#about to read 4, iclass 12, count 0 2006.257.08:48:23.88#ibcon#read 4, iclass 12, count 0 2006.257.08:48:23.88#ibcon#about to read 5, iclass 12, count 0 2006.257.08:48:23.88#ibcon#read 5, iclass 12, count 0 2006.257.08:48:23.88#ibcon#about to read 6, iclass 12, count 0 2006.257.08:48:23.88#ibcon#read 6, iclass 12, count 0 2006.257.08:48:23.88#ibcon#end of sib2, iclass 12, count 0 2006.257.08:48:23.88#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:48:23.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:48:23.88#ibcon#[25=USB\r\n] 2006.257.08:48:23.88#ibcon#*before write, iclass 12, count 0 2006.257.08:48:23.88#ibcon#enter sib2, iclass 12, count 0 2006.257.08:48:23.88#ibcon#flushed, iclass 12, count 0 2006.257.08:48:23.88#ibcon#about to write, iclass 12, count 0 2006.257.08:48:23.88#ibcon#wrote, iclass 12, count 0 2006.257.08:48:23.88#ibcon#about to read 3, iclass 12, count 0 2006.257.08:48:23.91#ibcon#read 3, iclass 12, count 0 2006.257.08:48:23.91#ibcon#about to read 4, iclass 12, count 0 2006.257.08:48:23.91#ibcon#read 4, iclass 12, count 0 2006.257.08:48:23.91#ibcon#about to read 5, iclass 12, count 0 2006.257.08:48:23.91#ibcon#read 5, iclass 12, count 0 2006.257.08:48:23.91#ibcon#about to read 6, iclass 12, count 0 2006.257.08:48:23.91#ibcon#read 6, iclass 12, count 0 2006.257.08:48:23.91#ibcon#end of sib2, iclass 12, count 0 2006.257.08:48:23.91#ibcon#*after write, iclass 12, count 0 2006.257.08:48:23.91#ibcon#*before return 0, iclass 12, count 0 2006.257.08:48:23.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:48:23.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.08:48:23.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:48:23.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:48:23.91$vck44/vblo=1,629.99 2006.257.08:48:23.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.08:48:23.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.08:48:23.91#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:23.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:48:23.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:48:23.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:48:23.91#ibcon#enter wrdev, iclass 14, count 0 2006.257.08:48:23.91#ibcon#first serial, iclass 14, count 0 2006.257.08:48:23.91#ibcon#enter sib2, iclass 14, count 0 2006.257.08:48:23.91#ibcon#flushed, iclass 14, count 0 2006.257.08:48:23.91#ibcon#about to write, iclass 14, count 0 2006.257.08:48:23.91#ibcon#wrote, iclass 14, count 0 2006.257.08:48:23.91#ibcon#about to read 3, iclass 14, count 0 2006.257.08:48:23.93#ibcon#read 3, iclass 14, count 0 2006.257.08:48:23.93#ibcon#about to read 4, iclass 14, count 0 2006.257.08:48:23.93#ibcon#read 4, iclass 14, count 0 2006.257.08:48:23.93#ibcon#about to read 5, iclass 14, count 0 2006.257.08:48:23.93#ibcon#read 5, iclass 14, count 0 2006.257.08:48:23.93#ibcon#about to read 6, iclass 14, count 0 2006.257.08:48:23.93#ibcon#read 6, iclass 14, count 0 2006.257.08:48:23.93#ibcon#end of sib2, iclass 14, count 0 2006.257.08:48:23.93#ibcon#*mode == 0, iclass 14, count 0 2006.257.08:48:23.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.08:48:23.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:48:23.93#ibcon#*before write, iclass 14, count 0 2006.257.08:48:23.93#ibcon#enter sib2, iclass 14, count 0 2006.257.08:48:23.93#ibcon#flushed, iclass 14, count 0 2006.257.08:48:23.93#ibcon#about to write, iclass 14, count 0 2006.257.08:48:23.93#ibcon#wrote, iclass 14, count 0 2006.257.08:48:23.93#ibcon#about to read 3, iclass 14, count 0 2006.257.08:48:23.97#ibcon#read 3, iclass 14, count 0 2006.257.08:48:23.97#ibcon#about to read 4, iclass 14, count 0 2006.257.08:48:23.97#ibcon#read 4, iclass 14, count 0 2006.257.08:48:23.97#ibcon#about to read 5, iclass 14, count 0 2006.257.08:48:23.97#ibcon#read 5, iclass 14, count 0 2006.257.08:48:23.97#ibcon#about to read 6, iclass 14, count 0 2006.257.08:48:23.97#ibcon#read 6, iclass 14, count 0 2006.257.08:48:23.97#ibcon#end of sib2, iclass 14, count 0 2006.257.08:48:23.97#ibcon#*after write, iclass 14, count 0 2006.257.08:48:23.97#ibcon#*before return 0, iclass 14, count 0 2006.257.08:48:23.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:48:23.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.08:48:23.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.08:48:23.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.08:48:23.97$vck44/vb=1,4 2006.257.08:48:23.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.08:48:23.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.08:48:23.97#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:23.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:48:23.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:48:23.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:48:23.97#ibcon#enter wrdev, iclass 16, count 2 2006.257.08:48:23.97#ibcon#first serial, iclass 16, count 2 2006.257.08:48:23.97#ibcon#enter sib2, iclass 16, count 2 2006.257.08:48:23.97#ibcon#flushed, iclass 16, count 2 2006.257.08:48:23.97#ibcon#about to write, iclass 16, count 2 2006.257.08:48:23.97#ibcon#wrote, iclass 16, count 2 2006.257.08:48:23.97#ibcon#about to read 3, iclass 16, count 2 2006.257.08:48:23.99#ibcon#read 3, iclass 16, count 2 2006.257.08:48:23.99#ibcon#about to read 4, iclass 16, count 2 2006.257.08:48:23.99#ibcon#read 4, iclass 16, count 2 2006.257.08:48:23.99#ibcon#about to read 5, iclass 16, count 2 2006.257.08:48:23.99#ibcon#read 5, iclass 16, count 2 2006.257.08:48:23.99#ibcon#about to read 6, iclass 16, count 2 2006.257.08:48:23.99#ibcon#read 6, iclass 16, count 2 2006.257.08:48:23.99#ibcon#end of sib2, iclass 16, count 2 2006.257.08:48:23.99#ibcon#*mode == 0, iclass 16, count 2 2006.257.08:48:23.99#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.08:48:23.99#ibcon#[27=AT01-04\r\n] 2006.257.08:48:23.99#ibcon#*before write, iclass 16, count 2 2006.257.08:48:23.99#ibcon#enter sib2, iclass 16, count 2 2006.257.08:48:23.99#ibcon#flushed, iclass 16, count 2 2006.257.08:48:23.99#ibcon#about to write, iclass 16, count 2 2006.257.08:48:23.99#ibcon#wrote, iclass 16, count 2 2006.257.08:48:23.99#ibcon#about to read 3, iclass 16, count 2 2006.257.08:48:24.02#ibcon#read 3, iclass 16, count 2 2006.257.08:48:24.02#ibcon#about to read 4, iclass 16, count 2 2006.257.08:48:24.02#ibcon#read 4, iclass 16, count 2 2006.257.08:48:24.02#ibcon#about to read 5, iclass 16, count 2 2006.257.08:48:24.02#ibcon#read 5, iclass 16, count 2 2006.257.08:48:24.02#ibcon#about to read 6, iclass 16, count 2 2006.257.08:48:24.02#ibcon#read 6, iclass 16, count 2 2006.257.08:48:24.02#ibcon#end of sib2, iclass 16, count 2 2006.257.08:48:24.02#ibcon#*after write, iclass 16, count 2 2006.257.08:48:24.02#ibcon#*before return 0, iclass 16, count 2 2006.257.08:48:24.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:48:24.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.08:48:24.02#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.08:48:24.02#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:24.02#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:48:24.14#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:48:24.14#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:48:24.14#ibcon#enter wrdev, iclass 16, count 0 2006.257.08:48:24.14#ibcon#first serial, iclass 16, count 0 2006.257.08:48:24.14#ibcon#enter sib2, iclass 16, count 0 2006.257.08:48:24.14#ibcon#flushed, iclass 16, count 0 2006.257.08:48:24.14#ibcon#about to write, iclass 16, count 0 2006.257.08:48:24.14#ibcon#wrote, iclass 16, count 0 2006.257.08:48:24.14#ibcon#about to read 3, iclass 16, count 0 2006.257.08:48:24.16#ibcon#read 3, iclass 16, count 0 2006.257.08:48:24.16#ibcon#about to read 4, iclass 16, count 0 2006.257.08:48:24.16#ibcon#read 4, iclass 16, count 0 2006.257.08:48:24.16#ibcon#about to read 5, iclass 16, count 0 2006.257.08:48:24.16#ibcon#read 5, iclass 16, count 0 2006.257.08:48:24.16#ibcon#about to read 6, iclass 16, count 0 2006.257.08:48:24.16#ibcon#read 6, iclass 16, count 0 2006.257.08:48:24.16#ibcon#end of sib2, iclass 16, count 0 2006.257.08:48:24.16#ibcon#*mode == 0, iclass 16, count 0 2006.257.08:48:24.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.08:48:24.16#ibcon#[27=USB\r\n] 2006.257.08:48:24.16#ibcon#*before write, iclass 16, count 0 2006.257.08:48:24.16#ibcon#enter sib2, iclass 16, count 0 2006.257.08:48:24.16#ibcon#flushed, iclass 16, count 0 2006.257.08:48:24.16#ibcon#about to write, iclass 16, count 0 2006.257.08:48:24.16#ibcon#wrote, iclass 16, count 0 2006.257.08:48:24.16#ibcon#about to read 3, iclass 16, count 0 2006.257.08:48:24.19#ibcon#read 3, iclass 16, count 0 2006.257.08:48:24.19#ibcon#about to read 4, iclass 16, count 0 2006.257.08:48:24.19#ibcon#read 4, iclass 16, count 0 2006.257.08:48:24.19#ibcon#about to read 5, iclass 16, count 0 2006.257.08:48:24.19#ibcon#read 5, iclass 16, count 0 2006.257.08:48:24.19#ibcon#about to read 6, iclass 16, count 0 2006.257.08:48:24.19#ibcon#read 6, iclass 16, count 0 2006.257.08:48:24.19#ibcon#end of sib2, iclass 16, count 0 2006.257.08:48:24.19#ibcon#*after write, iclass 16, count 0 2006.257.08:48:24.19#ibcon#*before return 0, iclass 16, count 0 2006.257.08:48:24.19#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:48:24.19#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.08:48:24.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.08:48:24.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.08:48:24.19$vck44/vblo=2,634.99 2006.257.08:48:24.19#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.08:48:24.19#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.08:48:24.19#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:24.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:24.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:24.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:24.19#ibcon#enter wrdev, iclass 18, count 0 2006.257.08:48:24.19#ibcon#first serial, iclass 18, count 0 2006.257.08:48:24.19#ibcon#enter sib2, iclass 18, count 0 2006.257.08:48:24.19#ibcon#flushed, iclass 18, count 0 2006.257.08:48:24.19#ibcon#about to write, iclass 18, count 0 2006.257.08:48:24.19#ibcon#wrote, iclass 18, count 0 2006.257.08:48:24.19#ibcon#about to read 3, iclass 18, count 0 2006.257.08:48:24.21#ibcon#read 3, iclass 18, count 0 2006.257.08:48:24.21#ibcon#about to read 4, iclass 18, count 0 2006.257.08:48:24.21#ibcon#read 4, iclass 18, count 0 2006.257.08:48:24.21#ibcon#about to read 5, iclass 18, count 0 2006.257.08:48:24.21#ibcon#read 5, iclass 18, count 0 2006.257.08:48:24.21#ibcon#about to read 6, iclass 18, count 0 2006.257.08:48:24.21#ibcon#read 6, iclass 18, count 0 2006.257.08:48:24.21#ibcon#end of sib2, iclass 18, count 0 2006.257.08:48:24.21#ibcon#*mode == 0, iclass 18, count 0 2006.257.08:48:24.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.08:48:24.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:48:24.21#ibcon#*before write, iclass 18, count 0 2006.257.08:48:24.21#ibcon#enter sib2, iclass 18, count 0 2006.257.08:48:24.21#ibcon#flushed, iclass 18, count 0 2006.257.08:48:24.21#ibcon#about to write, iclass 18, count 0 2006.257.08:48:24.21#ibcon#wrote, iclass 18, count 0 2006.257.08:48:24.21#ibcon#about to read 3, iclass 18, count 0 2006.257.08:48:24.25#ibcon#read 3, iclass 18, count 0 2006.257.08:48:24.25#ibcon#about to read 4, iclass 18, count 0 2006.257.08:48:24.25#ibcon#read 4, iclass 18, count 0 2006.257.08:48:24.25#ibcon#about to read 5, iclass 18, count 0 2006.257.08:48:24.25#ibcon#read 5, iclass 18, count 0 2006.257.08:48:24.25#ibcon#about to read 6, iclass 18, count 0 2006.257.08:48:24.25#ibcon#read 6, iclass 18, count 0 2006.257.08:48:24.25#ibcon#end of sib2, iclass 18, count 0 2006.257.08:48:24.25#ibcon#*after write, iclass 18, count 0 2006.257.08:48:24.25#ibcon#*before return 0, iclass 18, count 0 2006.257.08:48:24.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:24.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.08:48:24.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.08:48:24.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.08:48:24.25$vck44/vb=2,5 2006.257.08:48:24.25#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.08:48:24.25#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.08:48:24.25#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:24.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:24.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:24.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:24.31#ibcon#enter wrdev, iclass 20, count 2 2006.257.08:48:24.31#ibcon#first serial, iclass 20, count 2 2006.257.08:48:24.31#ibcon#enter sib2, iclass 20, count 2 2006.257.08:48:24.31#ibcon#flushed, iclass 20, count 2 2006.257.08:48:24.31#ibcon#about to write, iclass 20, count 2 2006.257.08:48:24.31#ibcon#wrote, iclass 20, count 2 2006.257.08:48:24.31#ibcon#about to read 3, iclass 20, count 2 2006.257.08:48:24.33#ibcon#read 3, iclass 20, count 2 2006.257.08:48:24.33#ibcon#about to read 4, iclass 20, count 2 2006.257.08:48:24.33#ibcon#read 4, iclass 20, count 2 2006.257.08:48:24.33#ibcon#about to read 5, iclass 20, count 2 2006.257.08:48:24.33#ibcon#read 5, iclass 20, count 2 2006.257.08:48:24.33#ibcon#about to read 6, iclass 20, count 2 2006.257.08:48:24.33#ibcon#read 6, iclass 20, count 2 2006.257.08:48:24.33#ibcon#end of sib2, iclass 20, count 2 2006.257.08:48:24.33#ibcon#*mode == 0, iclass 20, count 2 2006.257.08:48:24.33#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.08:48:24.33#ibcon#[27=AT02-05\r\n] 2006.257.08:48:24.33#ibcon#*before write, iclass 20, count 2 2006.257.08:48:24.33#ibcon#enter sib2, iclass 20, count 2 2006.257.08:48:24.33#ibcon#flushed, iclass 20, count 2 2006.257.08:48:24.33#ibcon#about to write, iclass 20, count 2 2006.257.08:48:24.33#ibcon#wrote, iclass 20, count 2 2006.257.08:48:24.33#ibcon#about to read 3, iclass 20, count 2 2006.257.08:48:24.36#ibcon#read 3, iclass 20, count 2 2006.257.08:48:24.36#ibcon#about to read 4, iclass 20, count 2 2006.257.08:48:24.36#ibcon#read 4, iclass 20, count 2 2006.257.08:48:24.36#ibcon#about to read 5, iclass 20, count 2 2006.257.08:48:24.36#ibcon#read 5, iclass 20, count 2 2006.257.08:48:24.36#ibcon#about to read 6, iclass 20, count 2 2006.257.08:48:24.36#ibcon#read 6, iclass 20, count 2 2006.257.08:48:24.36#ibcon#end of sib2, iclass 20, count 2 2006.257.08:48:24.36#ibcon#*after write, iclass 20, count 2 2006.257.08:48:24.36#ibcon#*before return 0, iclass 20, count 2 2006.257.08:48:24.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:24.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.08:48:24.36#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.08:48:24.36#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:24.36#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:24.48#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:24.48#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:24.48#ibcon#enter wrdev, iclass 20, count 0 2006.257.08:48:24.48#ibcon#first serial, iclass 20, count 0 2006.257.08:48:24.48#ibcon#enter sib2, iclass 20, count 0 2006.257.08:48:24.48#ibcon#flushed, iclass 20, count 0 2006.257.08:48:24.48#ibcon#about to write, iclass 20, count 0 2006.257.08:48:24.48#ibcon#wrote, iclass 20, count 0 2006.257.08:48:24.48#ibcon#about to read 3, iclass 20, count 0 2006.257.08:48:24.50#ibcon#read 3, iclass 20, count 0 2006.257.08:48:24.50#ibcon#about to read 4, iclass 20, count 0 2006.257.08:48:24.50#ibcon#read 4, iclass 20, count 0 2006.257.08:48:24.50#ibcon#about to read 5, iclass 20, count 0 2006.257.08:48:24.50#ibcon#read 5, iclass 20, count 0 2006.257.08:48:24.50#ibcon#about to read 6, iclass 20, count 0 2006.257.08:48:24.50#ibcon#read 6, iclass 20, count 0 2006.257.08:48:24.50#ibcon#end of sib2, iclass 20, count 0 2006.257.08:48:24.50#ibcon#*mode == 0, iclass 20, count 0 2006.257.08:48:24.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.08:48:24.50#ibcon#[27=USB\r\n] 2006.257.08:48:24.50#ibcon#*before write, iclass 20, count 0 2006.257.08:48:24.50#ibcon#enter sib2, iclass 20, count 0 2006.257.08:48:24.50#ibcon#flushed, iclass 20, count 0 2006.257.08:48:24.50#ibcon#about to write, iclass 20, count 0 2006.257.08:48:24.50#ibcon#wrote, iclass 20, count 0 2006.257.08:48:24.50#ibcon#about to read 3, iclass 20, count 0 2006.257.08:48:24.53#ibcon#read 3, iclass 20, count 0 2006.257.08:48:24.53#ibcon#about to read 4, iclass 20, count 0 2006.257.08:48:24.53#ibcon#read 4, iclass 20, count 0 2006.257.08:48:24.53#ibcon#about to read 5, iclass 20, count 0 2006.257.08:48:24.53#ibcon#read 5, iclass 20, count 0 2006.257.08:48:24.53#ibcon#about to read 6, iclass 20, count 0 2006.257.08:48:24.53#ibcon#read 6, iclass 20, count 0 2006.257.08:48:24.53#ibcon#end of sib2, iclass 20, count 0 2006.257.08:48:24.53#ibcon#*after write, iclass 20, count 0 2006.257.08:48:24.53#ibcon#*before return 0, iclass 20, count 0 2006.257.08:48:24.53#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:24.53#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.08:48:24.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.08:48:24.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.08:48:24.53$vck44/vblo=3,649.99 2006.257.08:48:24.53#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.08:48:24.53#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.08:48:24.53#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:24.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:24.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:24.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:24.53#ibcon#enter wrdev, iclass 22, count 0 2006.257.08:48:24.53#ibcon#first serial, iclass 22, count 0 2006.257.08:48:24.53#ibcon#enter sib2, iclass 22, count 0 2006.257.08:48:24.53#ibcon#flushed, iclass 22, count 0 2006.257.08:48:24.53#ibcon#about to write, iclass 22, count 0 2006.257.08:48:24.53#ibcon#wrote, iclass 22, count 0 2006.257.08:48:24.53#ibcon#about to read 3, iclass 22, count 0 2006.257.08:48:24.55#ibcon#read 3, iclass 22, count 0 2006.257.08:48:24.55#ibcon#about to read 4, iclass 22, count 0 2006.257.08:48:24.55#ibcon#read 4, iclass 22, count 0 2006.257.08:48:24.55#ibcon#about to read 5, iclass 22, count 0 2006.257.08:48:24.55#ibcon#read 5, iclass 22, count 0 2006.257.08:48:24.55#ibcon#about to read 6, iclass 22, count 0 2006.257.08:48:24.55#ibcon#read 6, iclass 22, count 0 2006.257.08:48:24.55#ibcon#end of sib2, iclass 22, count 0 2006.257.08:48:24.55#ibcon#*mode == 0, iclass 22, count 0 2006.257.08:48:24.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.08:48:24.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:48:24.55#ibcon#*before write, iclass 22, count 0 2006.257.08:48:24.55#ibcon#enter sib2, iclass 22, count 0 2006.257.08:48:24.55#ibcon#flushed, iclass 22, count 0 2006.257.08:48:24.55#ibcon#about to write, iclass 22, count 0 2006.257.08:48:24.55#ibcon#wrote, iclass 22, count 0 2006.257.08:48:24.55#ibcon#about to read 3, iclass 22, count 0 2006.257.08:48:24.59#ibcon#read 3, iclass 22, count 0 2006.257.08:48:24.59#ibcon#about to read 4, iclass 22, count 0 2006.257.08:48:24.59#ibcon#read 4, iclass 22, count 0 2006.257.08:48:24.59#ibcon#about to read 5, iclass 22, count 0 2006.257.08:48:24.59#ibcon#read 5, iclass 22, count 0 2006.257.08:48:24.59#ibcon#about to read 6, iclass 22, count 0 2006.257.08:48:24.59#ibcon#read 6, iclass 22, count 0 2006.257.08:48:24.59#ibcon#end of sib2, iclass 22, count 0 2006.257.08:48:24.59#ibcon#*after write, iclass 22, count 0 2006.257.08:48:24.59#ibcon#*before return 0, iclass 22, count 0 2006.257.08:48:24.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:24.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.08:48:24.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.08:48:24.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.08:48:24.59$vck44/vb=3,4 2006.257.08:48:24.59#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.08:48:24.59#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.08:48:24.59#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:24.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:24.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:24.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:24.65#ibcon#enter wrdev, iclass 24, count 2 2006.257.08:48:24.65#ibcon#first serial, iclass 24, count 2 2006.257.08:48:24.65#ibcon#enter sib2, iclass 24, count 2 2006.257.08:48:24.65#ibcon#flushed, iclass 24, count 2 2006.257.08:48:24.65#ibcon#about to write, iclass 24, count 2 2006.257.08:48:24.65#ibcon#wrote, iclass 24, count 2 2006.257.08:48:24.65#ibcon#about to read 3, iclass 24, count 2 2006.257.08:48:24.67#ibcon#read 3, iclass 24, count 2 2006.257.08:48:24.67#ibcon#about to read 4, iclass 24, count 2 2006.257.08:48:24.67#ibcon#read 4, iclass 24, count 2 2006.257.08:48:24.67#ibcon#about to read 5, iclass 24, count 2 2006.257.08:48:24.67#ibcon#read 5, iclass 24, count 2 2006.257.08:48:24.67#ibcon#about to read 6, iclass 24, count 2 2006.257.08:48:24.67#ibcon#read 6, iclass 24, count 2 2006.257.08:48:24.67#ibcon#end of sib2, iclass 24, count 2 2006.257.08:48:24.67#ibcon#*mode == 0, iclass 24, count 2 2006.257.08:48:24.67#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.08:48:24.67#ibcon#[27=AT03-04\r\n] 2006.257.08:48:24.67#ibcon#*before write, iclass 24, count 2 2006.257.08:48:24.67#ibcon#enter sib2, iclass 24, count 2 2006.257.08:48:24.67#ibcon#flushed, iclass 24, count 2 2006.257.08:48:24.67#ibcon#about to write, iclass 24, count 2 2006.257.08:48:24.67#ibcon#wrote, iclass 24, count 2 2006.257.08:48:24.67#ibcon#about to read 3, iclass 24, count 2 2006.257.08:48:24.70#ibcon#read 3, iclass 24, count 2 2006.257.08:48:24.70#ibcon#about to read 4, iclass 24, count 2 2006.257.08:48:24.70#ibcon#read 4, iclass 24, count 2 2006.257.08:48:24.70#ibcon#about to read 5, iclass 24, count 2 2006.257.08:48:24.70#ibcon#read 5, iclass 24, count 2 2006.257.08:48:24.70#ibcon#about to read 6, iclass 24, count 2 2006.257.08:48:24.70#ibcon#read 6, iclass 24, count 2 2006.257.08:48:24.70#ibcon#end of sib2, iclass 24, count 2 2006.257.08:48:24.70#ibcon#*after write, iclass 24, count 2 2006.257.08:48:24.70#ibcon#*before return 0, iclass 24, count 2 2006.257.08:48:24.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:24.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.08:48:24.70#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.08:48:24.70#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:24.70#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:24.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:24.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:24.82#ibcon#enter wrdev, iclass 24, count 0 2006.257.08:48:24.82#ibcon#first serial, iclass 24, count 0 2006.257.08:48:24.82#ibcon#enter sib2, iclass 24, count 0 2006.257.08:48:24.82#ibcon#flushed, iclass 24, count 0 2006.257.08:48:24.82#ibcon#about to write, iclass 24, count 0 2006.257.08:48:24.82#ibcon#wrote, iclass 24, count 0 2006.257.08:48:24.82#ibcon#about to read 3, iclass 24, count 0 2006.257.08:48:24.84#ibcon#read 3, iclass 24, count 0 2006.257.08:48:24.84#ibcon#about to read 4, iclass 24, count 0 2006.257.08:48:24.84#ibcon#read 4, iclass 24, count 0 2006.257.08:48:24.84#ibcon#about to read 5, iclass 24, count 0 2006.257.08:48:24.84#ibcon#read 5, iclass 24, count 0 2006.257.08:48:24.84#ibcon#about to read 6, iclass 24, count 0 2006.257.08:48:24.84#ibcon#read 6, iclass 24, count 0 2006.257.08:48:24.84#ibcon#end of sib2, iclass 24, count 0 2006.257.08:48:24.84#ibcon#*mode == 0, iclass 24, count 0 2006.257.08:48:24.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.08:48:24.84#ibcon#[27=USB\r\n] 2006.257.08:48:24.84#ibcon#*before write, iclass 24, count 0 2006.257.08:48:24.84#ibcon#enter sib2, iclass 24, count 0 2006.257.08:48:24.84#ibcon#flushed, iclass 24, count 0 2006.257.08:48:24.84#ibcon#about to write, iclass 24, count 0 2006.257.08:48:24.84#ibcon#wrote, iclass 24, count 0 2006.257.08:48:24.84#ibcon#about to read 3, iclass 24, count 0 2006.257.08:48:24.87#ibcon#read 3, iclass 24, count 0 2006.257.08:48:24.87#ibcon#about to read 4, iclass 24, count 0 2006.257.08:48:24.87#ibcon#read 4, iclass 24, count 0 2006.257.08:48:24.87#ibcon#about to read 5, iclass 24, count 0 2006.257.08:48:24.87#ibcon#read 5, iclass 24, count 0 2006.257.08:48:24.87#ibcon#about to read 6, iclass 24, count 0 2006.257.08:48:24.87#ibcon#read 6, iclass 24, count 0 2006.257.08:48:24.87#ibcon#end of sib2, iclass 24, count 0 2006.257.08:48:24.87#ibcon#*after write, iclass 24, count 0 2006.257.08:48:24.87#ibcon#*before return 0, iclass 24, count 0 2006.257.08:48:24.87#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:24.87#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.08:48:24.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.08:48:24.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.08:48:24.87$vck44/vblo=4,679.99 2006.257.08:48:24.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.08:48:24.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.08:48:24.87#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:24.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:24.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:24.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:24.87#ibcon#enter wrdev, iclass 26, count 0 2006.257.08:48:24.87#ibcon#first serial, iclass 26, count 0 2006.257.08:48:24.87#ibcon#enter sib2, iclass 26, count 0 2006.257.08:48:24.87#ibcon#flushed, iclass 26, count 0 2006.257.08:48:24.87#ibcon#about to write, iclass 26, count 0 2006.257.08:48:24.87#ibcon#wrote, iclass 26, count 0 2006.257.08:48:24.87#ibcon#about to read 3, iclass 26, count 0 2006.257.08:48:24.89#ibcon#read 3, iclass 26, count 0 2006.257.08:48:24.89#ibcon#about to read 4, iclass 26, count 0 2006.257.08:48:24.89#ibcon#read 4, iclass 26, count 0 2006.257.08:48:24.89#ibcon#about to read 5, iclass 26, count 0 2006.257.08:48:24.89#ibcon#read 5, iclass 26, count 0 2006.257.08:48:24.89#ibcon#about to read 6, iclass 26, count 0 2006.257.08:48:24.89#ibcon#read 6, iclass 26, count 0 2006.257.08:48:24.89#ibcon#end of sib2, iclass 26, count 0 2006.257.08:48:24.89#ibcon#*mode == 0, iclass 26, count 0 2006.257.08:48:24.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.08:48:24.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:48:24.89#ibcon#*before write, iclass 26, count 0 2006.257.08:48:24.89#ibcon#enter sib2, iclass 26, count 0 2006.257.08:48:24.89#ibcon#flushed, iclass 26, count 0 2006.257.08:48:24.89#ibcon#about to write, iclass 26, count 0 2006.257.08:48:24.89#ibcon#wrote, iclass 26, count 0 2006.257.08:48:24.89#ibcon#about to read 3, iclass 26, count 0 2006.257.08:48:24.93#ibcon#read 3, iclass 26, count 0 2006.257.08:48:24.93#ibcon#about to read 4, iclass 26, count 0 2006.257.08:48:24.93#ibcon#read 4, iclass 26, count 0 2006.257.08:48:24.93#ibcon#about to read 5, iclass 26, count 0 2006.257.08:48:24.93#ibcon#read 5, iclass 26, count 0 2006.257.08:48:24.93#ibcon#about to read 6, iclass 26, count 0 2006.257.08:48:24.93#ibcon#read 6, iclass 26, count 0 2006.257.08:48:24.93#ibcon#end of sib2, iclass 26, count 0 2006.257.08:48:24.93#ibcon#*after write, iclass 26, count 0 2006.257.08:48:24.93#ibcon#*before return 0, iclass 26, count 0 2006.257.08:48:24.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:24.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.08:48:24.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.08:48:24.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.08:48:24.93$vck44/vb=4,5 2006.257.08:48:24.93#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.08:48:24.93#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.08:48:24.93#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:24.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:24.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:24.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:24.99#ibcon#enter wrdev, iclass 28, count 2 2006.257.08:48:24.99#ibcon#first serial, iclass 28, count 2 2006.257.08:48:24.99#ibcon#enter sib2, iclass 28, count 2 2006.257.08:48:24.99#ibcon#flushed, iclass 28, count 2 2006.257.08:48:24.99#ibcon#about to write, iclass 28, count 2 2006.257.08:48:24.99#ibcon#wrote, iclass 28, count 2 2006.257.08:48:24.99#ibcon#about to read 3, iclass 28, count 2 2006.257.08:48:25.01#ibcon#read 3, iclass 28, count 2 2006.257.08:48:25.01#ibcon#about to read 4, iclass 28, count 2 2006.257.08:48:25.01#ibcon#read 4, iclass 28, count 2 2006.257.08:48:25.01#ibcon#about to read 5, iclass 28, count 2 2006.257.08:48:25.01#ibcon#read 5, iclass 28, count 2 2006.257.08:48:25.01#ibcon#about to read 6, iclass 28, count 2 2006.257.08:48:25.01#ibcon#read 6, iclass 28, count 2 2006.257.08:48:25.01#ibcon#end of sib2, iclass 28, count 2 2006.257.08:48:25.01#ibcon#*mode == 0, iclass 28, count 2 2006.257.08:48:25.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.08:48:25.01#ibcon#[27=AT04-05\r\n] 2006.257.08:48:25.01#ibcon#*before write, iclass 28, count 2 2006.257.08:48:25.01#ibcon#enter sib2, iclass 28, count 2 2006.257.08:48:25.01#ibcon#flushed, iclass 28, count 2 2006.257.08:48:25.01#ibcon#about to write, iclass 28, count 2 2006.257.08:48:25.01#ibcon#wrote, iclass 28, count 2 2006.257.08:48:25.01#ibcon#about to read 3, iclass 28, count 2 2006.257.08:48:25.04#ibcon#read 3, iclass 28, count 2 2006.257.08:48:25.04#ibcon#about to read 4, iclass 28, count 2 2006.257.08:48:25.04#ibcon#read 4, iclass 28, count 2 2006.257.08:48:25.04#ibcon#about to read 5, iclass 28, count 2 2006.257.08:48:25.04#ibcon#read 5, iclass 28, count 2 2006.257.08:48:25.04#ibcon#about to read 6, iclass 28, count 2 2006.257.08:48:25.04#ibcon#read 6, iclass 28, count 2 2006.257.08:48:25.04#ibcon#end of sib2, iclass 28, count 2 2006.257.08:48:25.04#ibcon#*after write, iclass 28, count 2 2006.257.08:48:25.04#ibcon#*before return 0, iclass 28, count 2 2006.257.08:48:25.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:25.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.08:48:25.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.08:48:25.04#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:25.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:25.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:25.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:25.16#ibcon#enter wrdev, iclass 28, count 0 2006.257.08:48:25.16#ibcon#first serial, iclass 28, count 0 2006.257.08:48:25.16#ibcon#enter sib2, iclass 28, count 0 2006.257.08:48:25.16#ibcon#flushed, iclass 28, count 0 2006.257.08:48:25.16#ibcon#about to write, iclass 28, count 0 2006.257.08:48:25.16#ibcon#wrote, iclass 28, count 0 2006.257.08:48:25.16#ibcon#about to read 3, iclass 28, count 0 2006.257.08:48:25.18#ibcon#read 3, iclass 28, count 0 2006.257.08:48:25.18#ibcon#about to read 4, iclass 28, count 0 2006.257.08:48:25.18#ibcon#read 4, iclass 28, count 0 2006.257.08:48:25.18#ibcon#about to read 5, iclass 28, count 0 2006.257.08:48:25.18#ibcon#read 5, iclass 28, count 0 2006.257.08:48:25.18#ibcon#about to read 6, iclass 28, count 0 2006.257.08:48:25.18#ibcon#read 6, iclass 28, count 0 2006.257.08:48:25.18#ibcon#end of sib2, iclass 28, count 0 2006.257.08:48:25.18#ibcon#*mode == 0, iclass 28, count 0 2006.257.08:48:25.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.08:48:25.18#ibcon#[27=USB\r\n] 2006.257.08:48:25.18#ibcon#*before write, iclass 28, count 0 2006.257.08:48:25.18#ibcon#enter sib2, iclass 28, count 0 2006.257.08:48:25.18#ibcon#flushed, iclass 28, count 0 2006.257.08:48:25.18#ibcon#about to write, iclass 28, count 0 2006.257.08:48:25.18#ibcon#wrote, iclass 28, count 0 2006.257.08:48:25.18#ibcon#about to read 3, iclass 28, count 0 2006.257.08:48:25.21#ibcon#read 3, iclass 28, count 0 2006.257.08:48:25.21#ibcon#about to read 4, iclass 28, count 0 2006.257.08:48:25.21#ibcon#read 4, iclass 28, count 0 2006.257.08:48:25.21#ibcon#about to read 5, iclass 28, count 0 2006.257.08:48:25.21#ibcon#read 5, iclass 28, count 0 2006.257.08:48:25.21#ibcon#about to read 6, iclass 28, count 0 2006.257.08:48:25.21#ibcon#read 6, iclass 28, count 0 2006.257.08:48:25.21#ibcon#end of sib2, iclass 28, count 0 2006.257.08:48:25.21#ibcon#*after write, iclass 28, count 0 2006.257.08:48:25.21#ibcon#*before return 0, iclass 28, count 0 2006.257.08:48:25.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:25.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.08:48:25.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.08:48:25.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.08:48:25.21$vck44/vblo=5,709.99 2006.257.08:48:25.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.08:48:25.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.08:48:25.21#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:25.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:25.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:25.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:25.21#ibcon#enter wrdev, iclass 30, count 0 2006.257.08:48:25.21#ibcon#first serial, iclass 30, count 0 2006.257.08:48:25.21#ibcon#enter sib2, iclass 30, count 0 2006.257.08:48:25.21#ibcon#flushed, iclass 30, count 0 2006.257.08:48:25.21#ibcon#about to write, iclass 30, count 0 2006.257.08:48:25.21#ibcon#wrote, iclass 30, count 0 2006.257.08:48:25.21#ibcon#about to read 3, iclass 30, count 0 2006.257.08:48:25.23#ibcon#read 3, iclass 30, count 0 2006.257.08:48:25.23#ibcon#about to read 4, iclass 30, count 0 2006.257.08:48:25.23#ibcon#read 4, iclass 30, count 0 2006.257.08:48:25.23#ibcon#about to read 5, iclass 30, count 0 2006.257.08:48:25.23#ibcon#read 5, iclass 30, count 0 2006.257.08:48:25.23#ibcon#about to read 6, iclass 30, count 0 2006.257.08:48:25.23#ibcon#read 6, iclass 30, count 0 2006.257.08:48:25.23#ibcon#end of sib2, iclass 30, count 0 2006.257.08:48:25.23#ibcon#*mode == 0, iclass 30, count 0 2006.257.08:48:25.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.08:48:25.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:48:25.23#ibcon#*before write, iclass 30, count 0 2006.257.08:48:25.23#ibcon#enter sib2, iclass 30, count 0 2006.257.08:48:25.23#ibcon#flushed, iclass 30, count 0 2006.257.08:48:25.23#ibcon#about to write, iclass 30, count 0 2006.257.08:48:25.23#ibcon#wrote, iclass 30, count 0 2006.257.08:48:25.23#ibcon#about to read 3, iclass 30, count 0 2006.257.08:48:25.27#ibcon#read 3, iclass 30, count 0 2006.257.08:48:25.27#ibcon#about to read 4, iclass 30, count 0 2006.257.08:48:25.27#ibcon#read 4, iclass 30, count 0 2006.257.08:48:25.27#ibcon#about to read 5, iclass 30, count 0 2006.257.08:48:25.27#ibcon#read 5, iclass 30, count 0 2006.257.08:48:25.27#ibcon#about to read 6, iclass 30, count 0 2006.257.08:48:25.27#ibcon#read 6, iclass 30, count 0 2006.257.08:48:25.27#ibcon#end of sib2, iclass 30, count 0 2006.257.08:48:25.27#ibcon#*after write, iclass 30, count 0 2006.257.08:48:25.27#ibcon#*before return 0, iclass 30, count 0 2006.257.08:48:25.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:25.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.08:48:25.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.08:48:25.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.08:48:25.27$vck44/vb=5,4 2006.257.08:48:25.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.08:48:25.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.08:48:25.27#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:25.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:25.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:25.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:25.33#ibcon#enter wrdev, iclass 32, count 2 2006.257.08:48:25.33#ibcon#first serial, iclass 32, count 2 2006.257.08:48:25.33#ibcon#enter sib2, iclass 32, count 2 2006.257.08:48:25.33#ibcon#flushed, iclass 32, count 2 2006.257.08:48:25.33#ibcon#about to write, iclass 32, count 2 2006.257.08:48:25.33#ibcon#wrote, iclass 32, count 2 2006.257.08:48:25.33#ibcon#about to read 3, iclass 32, count 2 2006.257.08:48:25.35#ibcon#read 3, iclass 32, count 2 2006.257.08:48:25.35#ibcon#about to read 4, iclass 32, count 2 2006.257.08:48:25.35#ibcon#read 4, iclass 32, count 2 2006.257.08:48:25.35#ibcon#about to read 5, iclass 32, count 2 2006.257.08:48:25.35#ibcon#read 5, iclass 32, count 2 2006.257.08:48:25.35#ibcon#about to read 6, iclass 32, count 2 2006.257.08:48:25.35#ibcon#read 6, iclass 32, count 2 2006.257.08:48:25.35#ibcon#end of sib2, iclass 32, count 2 2006.257.08:48:25.35#ibcon#*mode == 0, iclass 32, count 2 2006.257.08:48:25.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.08:48:25.35#ibcon#[27=AT05-04\r\n] 2006.257.08:48:25.35#ibcon#*before write, iclass 32, count 2 2006.257.08:48:25.35#ibcon#enter sib2, iclass 32, count 2 2006.257.08:48:25.35#ibcon#flushed, iclass 32, count 2 2006.257.08:48:25.35#ibcon#about to write, iclass 32, count 2 2006.257.08:48:25.35#ibcon#wrote, iclass 32, count 2 2006.257.08:48:25.35#ibcon#about to read 3, iclass 32, count 2 2006.257.08:48:25.38#ibcon#read 3, iclass 32, count 2 2006.257.08:48:25.38#ibcon#about to read 4, iclass 32, count 2 2006.257.08:48:25.38#ibcon#read 4, iclass 32, count 2 2006.257.08:48:25.38#ibcon#about to read 5, iclass 32, count 2 2006.257.08:48:25.38#ibcon#read 5, iclass 32, count 2 2006.257.08:48:25.38#ibcon#about to read 6, iclass 32, count 2 2006.257.08:48:25.38#ibcon#read 6, iclass 32, count 2 2006.257.08:48:25.38#ibcon#end of sib2, iclass 32, count 2 2006.257.08:48:25.38#ibcon#*after write, iclass 32, count 2 2006.257.08:48:25.38#ibcon#*before return 0, iclass 32, count 2 2006.257.08:48:25.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:25.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.08:48:25.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.08:48:25.38#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:25.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:25.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:25.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:25.50#ibcon#enter wrdev, iclass 32, count 0 2006.257.08:48:25.50#ibcon#first serial, iclass 32, count 0 2006.257.08:48:25.50#ibcon#enter sib2, iclass 32, count 0 2006.257.08:48:25.50#ibcon#flushed, iclass 32, count 0 2006.257.08:48:25.50#ibcon#about to write, iclass 32, count 0 2006.257.08:48:25.50#ibcon#wrote, iclass 32, count 0 2006.257.08:48:25.50#ibcon#about to read 3, iclass 32, count 0 2006.257.08:48:25.52#ibcon#read 3, iclass 32, count 0 2006.257.08:48:25.52#ibcon#about to read 4, iclass 32, count 0 2006.257.08:48:25.52#ibcon#read 4, iclass 32, count 0 2006.257.08:48:25.52#ibcon#about to read 5, iclass 32, count 0 2006.257.08:48:25.52#ibcon#read 5, iclass 32, count 0 2006.257.08:48:25.52#ibcon#about to read 6, iclass 32, count 0 2006.257.08:48:25.52#ibcon#read 6, iclass 32, count 0 2006.257.08:48:25.52#ibcon#end of sib2, iclass 32, count 0 2006.257.08:48:25.52#ibcon#*mode == 0, iclass 32, count 0 2006.257.08:48:25.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.08:48:25.52#ibcon#[27=USB\r\n] 2006.257.08:48:25.52#ibcon#*before write, iclass 32, count 0 2006.257.08:48:25.52#ibcon#enter sib2, iclass 32, count 0 2006.257.08:48:25.52#ibcon#flushed, iclass 32, count 0 2006.257.08:48:25.52#ibcon#about to write, iclass 32, count 0 2006.257.08:48:25.52#ibcon#wrote, iclass 32, count 0 2006.257.08:48:25.52#ibcon#about to read 3, iclass 32, count 0 2006.257.08:48:25.55#ibcon#read 3, iclass 32, count 0 2006.257.08:48:25.55#ibcon#about to read 4, iclass 32, count 0 2006.257.08:48:25.55#ibcon#read 4, iclass 32, count 0 2006.257.08:48:25.55#ibcon#about to read 5, iclass 32, count 0 2006.257.08:48:25.55#ibcon#read 5, iclass 32, count 0 2006.257.08:48:25.55#ibcon#about to read 6, iclass 32, count 0 2006.257.08:48:25.55#ibcon#read 6, iclass 32, count 0 2006.257.08:48:25.55#ibcon#end of sib2, iclass 32, count 0 2006.257.08:48:25.55#ibcon#*after write, iclass 32, count 0 2006.257.08:48:25.55#ibcon#*before return 0, iclass 32, count 0 2006.257.08:48:25.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:25.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.08:48:25.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.08:48:25.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.08:48:25.55$vck44/vblo=6,719.99 2006.257.08:48:25.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.08:48:25.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.08:48:25.55#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:25.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:25.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:25.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:25.55#ibcon#enter wrdev, iclass 34, count 0 2006.257.08:48:25.55#ibcon#first serial, iclass 34, count 0 2006.257.08:48:25.55#ibcon#enter sib2, iclass 34, count 0 2006.257.08:48:25.55#ibcon#flushed, iclass 34, count 0 2006.257.08:48:25.55#ibcon#about to write, iclass 34, count 0 2006.257.08:48:25.55#ibcon#wrote, iclass 34, count 0 2006.257.08:48:25.55#ibcon#about to read 3, iclass 34, count 0 2006.257.08:48:25.57#ibcon#read 3, iclass 34, count 0 2006.257.08:48:25.57#ibcon#about to read 4, iclass 34, count 0 2006.257.08:48:25.57#ibcon#read 4, iclass 34, count 0 2006.257.08:48:25.57#ibcon#about to read 5, iclass 34, count 0 2006.257.08:48:25.57#ibcon#read 5, iclass 34, count 0 2006.257.08:48:25.57#ibcon#about to read 6, iclass 34, count 0 2006.257.08:48:25.57#ibcon#read 6, iclass 34, count 0 2006.257.08:48:25.57#ibcon#end of sib2, iclass 34, count 0 2006.257.08:48:25.57#ibcon#*mode == 0, iclass 34, count 0 2006.257.08:48:25.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.08:48:25.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:48:25.57#ibcon#*before write, iclass 34, count 0 2006.257.08:48:25.57#ibcon#enter sib2, iclass 34, count 0 2006.257.08:48:25.57#ibcon#flushed, iclass 34, count 0 2006.257.08:48:25.57#ibcon#about to write, iclass 34, count 0 2006.257.08:48:25.57#ibcon#wrote, iclass 34, count 0 2006.257.08:48:25.57#ibcon#about to read 3, iclass 34, count 0 2006.257.08:48:25.61#ibcon#read 3, iclass 34, count 0 2006.257.08:48:25.61#ibcon#about to read 4, iclass 34, count 0 2006.257.08:48:25.61#ibcon#read 4, iclass 34, count 0 2006.257.08:48:25.61#ibcon#about to read 5, iclass 34, count 0 2006.257.08:48:25.61#ibcon#read 5, iclass 34, count 0 2006.257.08:48:25.61#ibcon#about to read 6, iclass 34, count 0 2006.257.08:48:25.61#ibcon#read 6, iclass 34, count 0 2006.257.08:48:25.61#ibcon#end of sib2, iclass 34, count 0 2006.257.08:48:25.61#ibcon#*after write, iclass 34, count 0 2006.257.08:48:25.61#ibcon#*before return 0, iclass 34, count 0 2006.257.08:48:25.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:25.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.08:48:25.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.08:48:25.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.08:48:25.61$vck44/vb=6,4 2006.257.08:48:25.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.08:48:25.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.08:48:25.61#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:25.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:25.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:25.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:25.67#ibcon#enter wrdev, iclass 36, count 2 2006.257.08:48:25.67#ibcon#first serial, iclass 36, count 2 2006.257.08:48:25.67#ibcon#enter sib2, iclass 36, count 2 2006.257.08:48:25.67#ibcon#flushed, iclass 36, count 2 2006.257.08:48:25.67#ibcon#about to write, iclass 36, count 2 2006.257.08:48:25.67#ibcon#wrote, iclass 36, count 2 2006.257.08:48:25.67#ibcon#about to read 3, iclass 36, count 2 2006.257.08:48:25.69#ibcon#read 3, iclass 36, count 2 2006.257.08:48:25.69#ibcon#about to read 4, iclass 36, count 2 2006.257.08:48:25.69#ibcon#read 4, iclass 36, count 2 2006.257.08:48:25.69#ibcon#about to read 5, iclass 36, count 2 2006.257.08:48:25.69#ibcon#read 5, iclass 36, count 2 2006.257.08:48:25.69#ibcon#about to read 6, iclass 36, count 2 2006.257.08:48:25.69#ibcon#read 6, iclass 36, count 2 2006.257.08:48:25.69#ibcon#end of sib2, iclass 36, count 2 2006.257.08:48:25.69#ibcon#*mode == 0, iclass 36, count 2 2006.257.08:48:25.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.08:48:25.69#ibcon#[27=AT06-04\r\n] 2006.257.08:48:25.69#ibcon#*before write, iclass 36, count 2 2006.257.08:48:25.69#ibcon#enter sib2, iclass 36, count 2 2006.257.08:48:25.69#ibcon#flushed, iclass 36, count 2 2006.257.08:48:25.69#ibcon#about to write, iclass 36, count 2 2006.257.08:48:25.69#ibcon#wrote, iclass 36, count 2 2006.257.08:48:25.69#ibcon#about to read 3, iclass 36, count 2 2006.257.08:48:25.72#ibcon#read 3, iclass 36, count 2 2006.257.08:48:25.72#ibcon#about to read 4, iclass 36, count 2 2006.257.08:48:25.72#ibcon#read 4, iclass 36, count 2 2006.257.08:48:25.72#ibcon#about to read 5, iclass 36, count 2 2006.257.08:48:25.72#ibcon#read 5, iclass 36, count 2 2006.257.08:48:25.72#ibcon#about to read 6, iclass 36, count 2 2006.257.08:48:25.72#ibcon#read 6, iclass 36, count 2 2006.257.08:48:25.72#ibcon#end of sib2, iclass 36, count 2 2006.257.08:48:25.72#ibcon#*after write, iclass 36, count 2 2006.257.08:48:25.72#ibcon#*before return 0, iclass 36, count 2 2006.257.08:48:25.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:25.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.08:48:25.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.08:48:25.72#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:25.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:25.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:25.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:25.84#ibcon#enter wrdev, iclass 36, count 0 2006.257.08:48:25.84#ibcon#first serial, iclass 36, count 0 2006.257.08:48:25.84#ibcon#enter sib2, iclass 36, count 0 2006.257.08:48:25.84#ibcon#flushed, iclass 36, count 0 2006.257.08:48:25.84#ibcon#about to write, iclass 36, count 0 2006.257.08:48:25.84#ibcon#wrote, iclass 36, count 0 2006.257.08:48:25.84#ibcon#about to read 3, iclass 36, count 0 2006.257.08:48:25.86#ibcon#read 3, iclass 36, count 0 2006.257.08:48:25.86#ibcon#about to read 4, iclass 36, count 0 2006.257.08:48:25.86#ibcon#read 4, iclass 36, count 0 2006.257.08:48:25.86#ibcon#about to read 5, iclass 36, count 0 2006.257.08:48:25.86#ibcon#read 5, iclass 36, count 0 2006.257.08:48:25.86#ibcon#about to read 6, iclass 36, count 0 2006.257.08:48:25.86#ibcon#read 6, iclass 36, count 0 2006.257.08:48:25.86#ibcon#end of sib2, iclass 36, count 0 2006.257.08:48:25.86#ibcon#*mode == 0, iclass 36, count 0 2006.257.08:48:25.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.08:48:25.86#ibcon#[27=USB\r\n] 2006.257.08:48:25.86#ibcon#*before write, iclass 36, count 0 2006.257.08:48:25.86#ibcon#enter sib2, iclass 36, count 0 2006.257.08:48:25.86#ibcon#flushed, iclass 36, count 0 2006.257.08:48:25.86#ibcon#about to write, iclass 36, count 0 2006.257.08:48:25.86#ibcon#wrote, iclass 36, count 0 2006.257.08:48:25.86#ibcon#about to read 3, iclass 36, count 0 2006.257.08:48:25.89#ibcon#read 3, iclass 36, count 0 2006.257.08:48:25.89#ibcon#about to read 4, iclass 36, count 0 2006.257.08:48:25.89#ibcon#read 4, iclass 36, count 0 2006.257.08:48:25.89#ibcon#about to read 5, iclass 36, count 0 2006.257.08:48:25.89#ibcon#read 5, iclass 36, count 0 2006.257.08:48:25.89#ibcon#about to read 6, iclass 36, count 0 2006.257.08:48:25.89#ibcon#read 6, iclass 36, count 0 2006.257.08:48:25.89#ibcon#end of sib2, iclass 36, count 0 2006.257.08:48:25.89#ibcon#*after write, iclass 36, count 0 2006.257.08:48:25.89#ibcon#*before return 0, iclass 36, count 0 2006.257.08:48:25.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:25.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.08:48:25.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.08:48:25.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.08:48:25.89$vck44/vblo=7,734.99 2006.257.08:48:25.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.08:48:25.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.08:48:25.89#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:25.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:25.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:25.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:25.89#ibcon#enter wrdev, iclass 38, count 0 2006.257.08:48:25.89#ibcon#first serial, iclass 38, count 0 2006.257.08:48:25.89#ibcon#enter sib2, iclass 38, count 0 2006.257.08:48:25.89#ibcon#flushed, iclass 38, count 0 2006.257.08:48:25.89#ibcon#about to write, iclass 38, count 0 2006.257.08:48:25.89#ibcon#wrote, iclass 38, count 0 2006.257.08:48:25.89#ibcon#about to read 3, iclass 38, count 0 2006.257.08:48:25.91#ibcon#read 3, iclass 38, count 0 2006.257.08:48:25.91#ibcon#about to read 4, iclass 38, count 0 2006.257.08:48:25.91#ibcon#read 4, iclass 38, count 0 2006.257.08:48:25.91#ibcon#about to read 5, iclass 38, count 0 2006.257.08:48:25.91#ibcon#read 5, iclass 38, count 0 2006.257.08:48:25.91#ibcon#about to read 6, iclass 38, count 0 2006.257.08:48:25.91#ibcon#read 6, iclass 38, count 0 2006.257.08:48:25.91#ibcon#end of sib2, iclass 38, count 0 2006.257.08:48:25.91#ibcon#*mode == 0, iclass 38, count 0 2006.257.08:48:25.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.08:48:25.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:48:25.91#ibcon#*before write, iclass 38, count 0 2006.257.08:48:25.91#ibcon#enter sib2, iclass 38, count 0 2006.257.08:48:25.91#ibcon#flushed, iclass 38, count 0 2006.257.08:48:25.91#ibcon#about to write, iclass 38, count 0 2006.257.08:48:25.91#ibcon#wrote, iclass 38, count 0 2006.257.08:48:25.91#ibcon#about to read 3, iclass 38, count 0 2006.257.08:48:25.95#ibcon#read 3, iclass 38, count 0 2006.257.08:48:25.95#ibcon#about to read 4, iclass 38, count 0 2006.257.08:48:25.95#ibcon#read 4, iclass 38, count 0 2006.257.08:48:25.95#ibcon#about to read 5, iclass 38, count 0 2006.257.08:48:25.95#ibcon#read 5, iclass 38, count 0 2006.257.08:48:25.95#ibcon#about to read 6, iclass 38, count 0 2006.257.08:48:25.95#ibcon#read 6, iclass 38, count 0 2006.257.08:48:25.95#ibcon#end of sib2, iclass 38, count 0 2006.257.08:48:25.95#ibcon#*after write, iclass 38, count 0 2006.257.08:48:25.95#ibcon#*before return 0, iclass 38, count 0 2006.257.08:48:25.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:25.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.08:48:25.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.08:48:25.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.08:48:25.95$vck44/vb=7,4 2006.257.08:48:25.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.08:48:25.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.08:48:25.95#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:25.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:26.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:26.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:26.01#ibcon#enter wrdev, iclass 40, count 2 2006.257.08:48:26.01#ibcon#first serial, iclass 40, count 2 2006.257.08:48:26.01#ibcon#enter sib2, iclass 40, count 2 2006.257.08:48:26.01#ibcon#flushed, iclass 40, count 2 2006.257.08:48:26.01#ibcon#about to write, iclass 40, count 2 2006.257.08:48:26.01#ibcon#wrote, iclass 40, count 2 2006.257.08:48:26.01#ibcon#about to read 3, iclass 40, count 2 2006.257.08:48:26.03#ibcon#read 3, iclass 40, count 2 2006.257.08:48:26.03#ibcon#about to read 4, iclass 40, count 2 2006.257.08:48:26.03#ibcon#read 4, iclass 40, count 2 2006.257.08:48:26.03#ibcon#about to read 5, iclass 40, count 2 2006.257.08:48:26.03#ibcon#read 5, iclass 40, count 2 2006.257.08:48:26.03#ibcon#about to read 6, iclass 40, count 2 2006.257.08:48:26.03#ibcon#read 6, iclass 40, count 2 2006.257.08:48:26.03#ibcon#end of sib2, iclass 40, count 2 2006.257.08:48:26.03#ibcon#*mode == 0, iclass 40, count 2 2006.257.08:48:26.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.08:48:26.03#ibcon#[27=AT07-04\r\n] 2006.257.08:48:26.03#ibcon#*before write, iclass 40, count 2 2006.257.08:48:26.03#ibcon#enter sib2, iclass 40, count 2 2006.257.08:48:26.03#ibcon#flushed, iclass 40, count 2 2006.257.08:48:26.03#ibcon#about to write, iclass 40, count 2 2006.257.08:48:26.03#ibcon#wrote, iclass 40, count 2 2006.257.08:48:26.03#ibcon#about to read 3, iclass 40, count 2 2006.257.08:48:26.06#ibcon#read 3, iclass 40, count 2 2006.257.08:48:26.06#ibcon#about to read 4, iclass 40, count 2 2006.257.08:48:26.06#ibcon#read 4, iclass 40, count 2 2006.257.08:48:26.06#ibcon#about to read 5, iclass 40, count 2 2006.257.08:48:26.06#ibcon#read 5, iclass 40, count 2 2006.257.08:48:26.06#ibcon#about to read 6, iclass 40, count 2 2006.257.08:48:26.06#ibcon#read 6, iclass 40, count 2 2006.257.08:48:26.06#ibcon#end of sib2, iclass 40, count 2 2006.257.08:48:26.06#ibcon#*after write, iclass 40, count 2 2006.257.08:48:26.06#ibcon#*before return 0, iclass 40, count 2 2006.257.08:48:26.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:26.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.08:48:26.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.08:48:26.06#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:26.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:26.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:26.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:26.18#ibcon#enter wrdev, iclass 40, count 0 2006.257.08:48:26.18#ibcon#first serial, iclass 40, count 0 2006.257.08:48:26.18#ibcon#enter sib2, iclass 40, count 0 2006.257.08:48:26.18#ibcon#flushed, iclass 40, count 0 2006.257.08:48:26.18#ibcon#about to write, iclass 40, count 0 2006.257.08:48:26.18#ibcon#wrote, iclass 40, count 0 2006.257.08:48:26.18#ibcon#about to read 3, iclass 40, count 0 2006.257.08:48:26.20#ibcon#read 3, iclass 40, count 0 2006.257.08:48:26.20#ibcon#about to read 4, iclass 40, count 0 2006.257.08:48:26.20#ibcon#read 4, iclass 40, count 0 2006.257.08:48:26.20#ibcon#about to read 5, iclass 40, count 0 2006.257.08:48:26.20#ibcon#read 5, iclass 40, count 0 2006.257.08:48:26.20#ibcon#about to read 6, iclass 40, count 0 2006.257.08:48:26.20#ibcon#read 6, iclass 40, count 0 2006.257.08:48:26.20#ibcon#end of sib2, iclass 40, count 0 2006.257.08:48:26.20#ibcon#*mode == 0, iclass 40, count 0 2006.257.08:48:26.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.08:48:26.20#ibcon#[27=USB\r\n] 2006.257.08:48:26.20#ibcon#*before write, iclass 40, count 0 2006.257.08:48:26.20#ibcon#enter sib2, iclass 40, count 0 2006.257.08:48:26.20#ibcon#flushed, iclass 40, count 0 2006.257.08:48:26.20#ibcon#about to write, iclass 40, count 0 2006.257.08:48:26.20#ibcon#wrote, iclass 40, count 0 2006.257.08:48:26.20#ibcon#about to read 3, iclass 40, count 0 2006.257.08:48:26.23#ibcon#read 3, iclass 40, count 0 2006.257.08:48:26.23#ibcon#about to read 4, iclass 40, count 0 2006.257.08:48:26.23#ibcon#read 4, iclass 40, count 0 2006.257.08:48:26.23#ibcon#about to read 5, iclass 40, count 0 2006.257.08:48:26.23#ibcon#read 5, iclass 40, count 0 2006.257.08:48:26.23#ibcon#about to read 6, iclass 40, count 0 2006.257.08:48:26.23#ibcon#read 6, iclass 40, count 0 2006.257.08:48:26.23#ibcon#end of sib2, iclass 40, count 0 2006.257.08:48:26.23#ibcon#*after write, iclass 40, count 0 2006.257.08:48:26.23#ibcon#*before return 0, iclass 40, count 0 2006.257.08:48:26.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:26.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.08:48:26.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.08:48:26.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.08:48:26.23$vck44/vblo=8,744.99 2006.257.08:48:26.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.08:48:26.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.08:48:26.23#ibcon#ireg 17 cls_cnt 0 2006.257.08:48:26.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:26.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:26.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:26.23#ibcon#enter wrdev, iclass 4, count 0 2006.257.08:48:26.23#ibcon#first serial, iclass 4, count 0 2006.257.08:48:26.23#ibcon#enter sib2, iclass 4, count 0 2006.257.08:48:26.23#ibcon#flushed, iclass 4, count 0 2006.257.08:48:26.23#ibcon#about to write, iclass 4, count 0 2006.257.08:48:26.23#ibcon#wrote, iclass 4, count 0 2006.257.08:48:26.23#ibcon#about to read 3, iclass 4, count 0 2006.257.08:48:26.25#ibcon#read 3, iclass 4, count 0 2006.257.08:48:26.25#ibcon#about to read 4, iclass 4, count 0 2006.257.08:48:26.25#ibcon#read 4, iclass 4, count 0 2006.257.08:48:26.25#ibcon#about to read 5, iclass 4, count 0 2006.257.08:48:26.25#ibcon#read 5, iclass 4, count 0 2006.257.08:48:26.25#ibcon#about to read 6, iclass 4, count 0 2006.257.08:48:26.25#ibcon#read 6, iclass 4, count 0 2006.257.08:48:26.25#ibcon#end of sib2, iclass 4, count 0 2006.257.08:48:26.25#ibcon#*mode == 0, iclass 4, count 0 2006.257.08:48:26.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.08:48:26.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:48:26.25#ibcon#*before write, iclass 4, count 0 2006.257.08:48:26.25#ibcon#enter sib2, iclass 4, count 0 2006.257.08:48:26.25#ibcon#flushed, iclass 4, count 0 2006.257.08:48:26.25#ibcon#about to write, iclass 4, count 0 2006.257.08:48:26.25#ibcon#wrote, iclass 4, count 0 2006.257.08:48:26.25#ibcon#about to read 3, iclass 4, count 0 2006.257.08:48:26.29#ibcon#read 3, iclass 4, count 0 2006.257.08:48:26.29#ibcon#about to read 4, iclass 4, count 0 2006.257.08:48:26.29#ibcon#read 4, iclass 4, count 0 2006.257.08:48:26.29#ibcon#about to read 5, iclass 4, count 0 2006.257.08:48:26.29#ibcon#read 5, iclass 4, count 0 2006.257.08:48:26.29#ibcon#about to read 6, iclass 4, count 0 2006.257.08:48:26.29#ibcon#read 6, iclass 4, count 0 2006.257.08:48:26.29#ibcon#end of sib2, iclass 4, count 0 2006.257.08:48:26.29#ibcon#*after write, iclass 4, count 0 2006.257.08:48:26.29#ibcon#*before return 0, iclass 4, count 0 2006.257.08:48:26.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:26.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.08:48:26.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.08:48:26.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.08:48:26.29$vck44/vb=8,4 2006.257.08:48:26.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.08:48:26.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.08:48:26.29#ibcon#ireg 11 cls_cnt 2 2006.257.08:48:26.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:26.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:26.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:26.35#ibcon#enter wrdev, iclass 6, count 2 2006.257.08:48:26.35#ibcon#first serial, iclass 6, count 2 2006.257.08:48:26.35#ibcon#enter sib2, iclass 6, count 2 2006.257.08:48:26.35#ibcon#flushed, iclass 6, count 2 2006.257.08:48:26.35#ibcon#about to write, iclass 6, count 2 2006.257.08:48:26.35#ibcon#wrote, iclass 6, count 2 2006.257.08:48:26.35#ibcon#about to read 3, iclass 6, count 2 2006.257.08:48:26.37#ibcon#read 3, iclass 6, count 2 2006.257.08:48:26.37#ibcon#about to read 4, iclass 6, count 2 2006.257.08:48:26.37#ibcon#read 4, iclass 6, count 2 2006.257.08:48:26.37#ibcon#about to read 5, iclass 6, count 2 2006.257.08:48:26.37#ibcon#read 5, iclass 6, count 2 2006.257.08:48:26.37#ibcon#about to read 6, iclass 6, count 2 2006.257.08:48:26.37#ibcon#read 6, iclass 6, count 2 2006.257.08:48:26.37#ibcon#end of sib2, iclass 6, count 2 2006.257.08:48:26.37#ibcon#*mode == 0, iclass 6, count 2 2006.257.08:48:26.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.08:48:26.37#ibcon#[27=AT08-04\r\n] 2006.257.08:48:26.37#ibcon#*before write, iclass 6, count 2 2006.257.08:48:26.37#ibcon#enter sib2, iclass 6, count 2 2006.257.08:48:26.37#ibcon#flushed, iclass 6, count 2 2006.257.08:48:26.37#ibcon#about to write, iclass 6, count 2 2006.257.08:48:26.37#ibcon#wrote, iclass 6, count 2 2006.257.08:48:26.37#ibcon#about to read 3, iclass 6, count 2 2006.257.08:48:26.40#ibcon#read 3, iclass 6, count 2 2006.257.08:48:26.40#ibcon#about to read 4, iclass 6, count 2 2006.257.08:48:26.40#ibcon#read 4, iclass 6, count 2 2006.257.08:48:26.40#ibcon#about to read 5, iclass 6, count 2 2006.257.08:48:26.40#ibcon#read 5, iclass 6, count 2 2006.257.08:48:26.40#ibcon#about to read 6, iclass 6, count 2 2006.257.08:48:26.40#ibcon#read 6, iclass 6, count 2 2006.257.08:48:26.40#ibcon#end of sib2, iclass 6, count 2 2006.257.08:48:26.40#ibcon#*after write, iclass 6, count 2 2006.257.08:48:26.40#ibcon#*before return 0, iclass 6, count 2 2006.257.08:48:26.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:26.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.08:48:26.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.08:48:26.40#ibcon#ireg 7 cls_cnt 0 2006.257.08:48:26.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:26.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:26.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:26.52#ibcon#enter wrdev, iclass 6, count 0 2006.257.08:48:26.52#ibcon#first serial, iclass 6, count 0 2006.257.08:48:26.52#ibcon#enter sib2, iclass 6, count 0 2006.257.08:48:26.52#ibcon#flushed, iclass 6, count 0 2006.257.08:48:26.52#ibcon#about to write, iclass 6, count 0 2006.257.08:48:26.52#ibcon#wrote, iclass 6, count 0 2006.257.08:48:26.52#ibcon#about to read 3, iclass 6, count 0 2006.257.08:48:26.54#ibcon#read 3, iclass 6, count 0 2006.257.08:48:26.54#ibcon#about to read 4, iclass 6, count 0 2006.257.08:48:26.54#ibcon#read 4, iclass 6, count 0 2006.257.08:48:26.54#ibcon#about to read 5, iclass 6, count 0 2006.257.08:48:26.54#ibcon#read 5, iclass 6, count 0 2006.257.08:48:26.54#ibcon#about to read 6, iclass 6, count 0 2006.257.08:48:26.54#ibcon#read 6, iclass 6, count 0 2006.257.08:48:26.54#ibcon#end of sib2, iclass 6, count 0 2006.257.08:48:26.54#ibcon#*mode == 0, iclass 6, count 0 2006.257.08:48:26.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.08:48:26.54#ibcon#[27=USB\r\n] 2006.257.08:48:26.54#ibcon#*before write, iclass 6, count 0 2006.257.08:48:26.54#ibcon#enter sib2, iclass 6, count 0 2006.257.08:48:26.54#ibcon#flushed, iclass 6, count 0 2006.257.08:48:26.54#ibcon#about to write, iclass 6, count 0 2006.257.08:48:26.54#ibcon#wrote, iclass 6, count 0 2006.257.08:48:26.54#ibcon#about to read 3, iclass 6, count 0 2006.257.08:48:26.57#ibcon#read 3, iclass 6, count 0 2006.257.08:48:26.57#ibcon#about to read 4, iclass 6, count 0 2006.257.08:48:26.57#ibcon#read 4, iclass 6, count 0 2006.257.08:48:26.57#ibcon#about to read 5, iclass 6, count 0 2006.257.08:48:26.57#ibcon#read 5, iclass 6, count 0 2006.257.08:48:26.57#ibcon#about to read 6, iclass 6, count 0 2006.257.08:48:26.57#ibcon#read 6, iclass 6, count 0 2006.257.08:48:26.57#ibcon#end of sib2, iclass 6, count 0 2006.257.08:48:26.57#ibcon#*after write, iclass 6, count 0 2006.257.08:48:26.57#ibcon#*before return 0, iclass 6, count 0 2006.257.08:48:26.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:26.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.08:48:26.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.08:48:26.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.08:48:26.57$vck44/vabw=wide 2006.257.08:48:26.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.08:48:26.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.08:48:26.57#ibcon#ireg 8 cls_cnt 0 2006.257.08:48:26.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:26.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:26.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:26.57#ibcon#enter wrdev, iclass 10, count 0 2006.257.08:48:26.57#ibcon#first serial, iclass 10, count 0 2006.257.08:48:26.57#ibcon#enter sib2, iclass 10, count 0 2006.257.08:48:26.57#ibcon#flushed, iclass 10, count 0 2006.257.08:48:26.57#ibcon#about to write, iclass 10, count 0 2006.257.08:48:26.57#ibcon#wrote, iclass 10, count 0 2006.257.08:48:26.57#ibcon#about to read 3, iclass 10, count 0 2006.257.08:48:26.59#ibcon#read 3, iclass 10, count 0 2006.257.08:48:26.59#ibcon#about to read 4, iclass 10, count 0 2006.257.08:48:26.59#ibcon#read 4, iclass 10, count 0 2006.257.08:48:26.59#ibcon#about to read 5, iclass 10, count 0 2006.257.08:48:26.59#ibcon#read 5, iclass 10, count 0 2006.257.08:48:26.59#ibcon#about to read 6, iclass 10, count 0 2006.257.08:48:26.59#ibcon#read 6, iclass 10, count 0 2006.257.08:48:26.59#ibcon#end of sib2, iclass 10, count 0 2006.257.08:48:26.59#ibcon#*mode == 0, iclass 10, count 0 2006.257.08:48:26.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.08:48:26.59#ibcon#[25=BW32\r\n] 2006.257.08:48:26.59#ibcon#*before write, iclass 10, count 0 2006.257.08:48:26.59#ibcon#enter sib2, iclass 10, count 0 2006.257.08:48:26.59#ibcon#flushed, iclass 10, count 0 2006.257.08:48:26.59#ibcon#about to write, iclass 10, count 0 2006.257.08:48:26.59#ibcon#wrote, iclass 10, count 0 2006.257.08:48:26.59#ibcon#about to read 3, iclass 10, count 0 2006.257.08:48:26.62#ibcon#read 3, iclass 10, count 0 2006.257.08:48:26.62#ibcon#about to read 4, iclass 10, count 0 2006.257.08:48:26.62#ibcon#read 4, iclass 10, count 0 2006.257.08:48:26.62#ibcon#about to read 5, iclass 10, count 0 2006.257.08:48:26.62#ibcon#read 5, iclass 10, count 0 2006.257.08:48:26.62#ibcon#about to read 6, iclass 10, count 0 2006.257.08:48:26.62#ibcon#read 6, iclass 10, count 0 2006.257.08:48:26.62#ibcon#end of sib2, iclass 10, count 0 2006.257.08:48:26.62#ibcon#*after write, iclass 10, count 0 2006.257.08:48:26.62#ibcon#*before return 0, iclass 10, count 0 2006.257.08:48:26.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:26.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.08:48:26.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.08:48:26.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.08:48:26.62$vck44/vbbw=wide 2006.257.08:48:26.62#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.08:48:26.62#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.08:48:26.62#ibcon#ireg 8 cls_cnt 0 2006.257.08:48:26.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:48:26.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:48:26.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:48:26.69#ibcon#enter wrdev, iclass 12, count 0 2006.257.08:48:26.69#ibcon#first serial, iclass 12, count 0 2006.257.08:48:26.69#ibcon#enter sib2, iclass 12, count 0 2006.257.08:48:26.69#ibcon#flushed, iclass 12, count 0 2006.257.08:48:26.69#ibcon#about to write, iclass 12, count 0 2006.257.08:48:26.69#ibcon#wrote, iclass 12, count 0 2006.257.08:48:26.69#ibcon#about to read 3, iclass 12, count 0 2006.257.08:48:26.71#ibcon#read 3, iclass 12, count 0 2006.257.08:48:26.71#ibcon#about to read 4, iclass 12, count 0 2006.257.08:48:26.71#ibcon#read 4, iclass 12, count 0 2006.257.08:48:26.71#ibcon#about to read 5, iclass 12, count 0 2006.257.08:48:26.71#ibcon#read 5, iclass 12, count 0 2006.257.08:48:26.71#ibcon#about to read 6, iclass 12, count 0 2006.257.08:48:26.71#ibcon#read 6, iclass 12, count 0 2006.257.08:48:26.71#ibcon#end of sib2, iclass 12, count 0 2006.257.08:48:26.71#ibcon#*mode == 0, iclass 12, count 0 2006.257.08:48:26.71#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.08:48:26.71#ibcon#[27=BW32\r\n] 2006.257.08:48:26.71#ibcon#*before write, iclass 12, count 0 2006.257.08:48:26.71#ibcon#enter sib2, iclass 12, count 0 2006.257.08:48:26.71#ibcon#flushed, iclass 12, count 0 2006.257.08:48:26.71#ibcon#about to write, iclass 12, count 0 2006.257.08:48:26.71#ibcon#wrote, iclass 12, count 0 2006.257.08:48:26.71#ibcon#about to read 3, iclass 12, count 0 2006.257.08:48:26.74#ibcon#read 3, iclass 12, count 0 2006.257.08:48:26.74#ibcon#about to read 4, iclass 12, count 0 2006.257.08:48:26.74#ibcon#read 4, iclass 12, count 0 2006.257.08:48:26.74#ibcon#about to read 5, iclass 12, count 0 2006.257.08:48:26.74#ibcon#read 5, iclass 12, count 0 2006.257.08:48:26.74#ibcon#about to read 6, iclass 12, count 0 2006.257.08:48:26.74#ibcon#read 6, iclass 12, count 0 2006.257.08:48:26.74#ibcon#end of sib2, iclass 12, count 0 2006.257.08:48:26.74#ibcon#*after write, iclass 12, count 0 2006.257.08:48:26.74#ibcon#*before return 0, iclass 12, count 0 2006.257.08:48:26.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:48:26.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.08:48:26.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.08:48:26.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.08:48:26.74$setupk4/ifdk4 2006.257.08:48:26.74$ifdk4/lo= 2006.257.08:48:26.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:48:26.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:48:26.74$ifdk4/patch= 2006.257.08:48:26.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:48:26.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:48:26.74$setupk4/!*+20s 2006.257.08:48:27.53#abcon#<5=/14 1.0 2.0 20.37 921013.1\r\n> 2006.257.08:48:27.55#abcon#{5=INTERFACE CLEAR} 2006.257.08:48:27.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:48:37.70#abcon#<5=/14 1.1 2.0 20.37 921013.1\r\n> 2006.257.08:48:37.72#abcon#{5=INTERFACE CLEAR} 2006.257.08:48:37.78#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:48:41.24$setupk4/"tpicd 2006.257.08:48:41.24$setupk4/echo=off 2006.257.08:48:41.24$setupk4/xlog=off 2006.257.08:48:41.24:!2006.257.08:53:57 2006.257.08:48:45.14#trakl#Source acquired 2006.257.08:48:46.14#flagr#flagr/antenna,acquired 2006.257.08:53:57.00:preob 2006.257.08:53:57.14/onsource/TRACKING 2006.257.08:53:57.14:!2006.257.08:54:07 2006.257.08:54:07.00:"tape 2006.257.08:54:07.00:"st=record 2006.257.08:54:07.00:data_valid=on 2006.257.08:54:07.00:midob 2006.257.08:54:07.14/onsource/TRACKING 2006.257.08:54:07.14/wx/20.27,1013.1,93 2006.257.08:54:07.28/cable/+6.4739E-03 2006.257.08:54:08.37/va/01,08,usb,yes,31,33 2006.257.08:54:08.37/va/02,07,usb,yes,34,34 2006.257.08:54:08.37/va/03,08,usb,yes,30,32 2006.257.08:54:08.37/va/04,07,usb,yes,35,36 2006.257.08:54:08.37/va/05,04,usb,yes,31,31 2006.257.08:54:08.37/va/06,04,usb,yes,35,34 2006.257.08:54:08.37/va/07,04,usb,yes,36,36 2006.257.08:54:08.37/va/08,04,usb,yes,29,36 2006.257.08:54:08.60/valo/01,524.99,yes,locked 2006.257.08:54:08.60/valo/02,534.99,yes,locked 2006.257.08:54:08.60/valo/03,564.99,yes,locked 2006.257.08:54:08.60/valo/04,624.99,yes,locked 2006.257.08:54:08.60/valo/05,734.99,yes,locked 2006.257.08:54:08.60/valo/06,814.99,yes,locked 2006.257.08:54:08.60/valo/07,864.99,yes,locked 2006.257.08:54:08.60/valo/08,884.99,yes,locked 2006.257.08:54:09.69/vb/01,04,usb,yes,31,28 2006.257.08:54:09.69/vb/02,05,usb,yes,29,29 2006.257.08:54:09.69/vb/03,04,usb,yes,30,33 2006.257.08:54:09.69/vb/04,05,usb,yes,30,29 2006.257.08:54:09.69/vb/05,04,usb,yes,27,29 2006.257.08:54:09.69/vb/06,04,usb,yes,31,27 2006.257.08:54:09.69/vb/07,04,usb,yes,31,31 2006.257.08:54:09.69/vb/08,04,usb,yes,28,32 2006.257.08:54:09.93/vblo/01,629.99,yes,locked 2006.257.08:54:09.93/vblo/02,634.99,yes,locked 2006.257.08:54:09.93/vblo/03,649.99,yes,locked 2006.257.08:54:09.93/vblo/04,679.99,yes,locked 2006.257.08:54:09.93/vblo/05,709.99,yes,locked 2006.257.08:54:09.93/vblo/06,719.99,yes,locked 2006.257.08:54:09.93/vblo/07,734.99,yes,locked 2006.257.08:54:09.93/vblo/08,744.99,yes,locked 2006.257.08:54:10.08/vabw/8 2006.257.08:54:10.23/vbbw/8 2006.257.08:54:10.32/xfe/off,on,15.0 2006.257.08:54:10.69/ifatt/23,28,28,28 2006.257.08:54:11.08/fmout-gps/S +4.63E-07 2006.257.08:54:11.12:!2006.257.08:55:27 2006.257.08:55:27.00:data_valid=off 2006.257.08:55:27.00:"et 2006.257.08:55:27.00:!+3s 2006.257.08:55:30.02:"tape 2006.257.08:55:30.02:postob 2006.257.08:55:30.08/cable/+6.4723E-03 2006.257.08:55:30.08/wx/20.24,1013.2,93 2006.257.08:55:30.14/fmout-gps/S +4.63E-07 2006.257.08:55:30.14:scan_name=257-0900,jd0609,40 2006.257.08:55:30.14:source=1954-388,195800.00,-384506.4,2000.0,ccw 2006.257.08:55:31.14#flagr#flagr/antenna,new-source 2006.257.08:55:31.14:checkk5 2006.257.08:55:31.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.08:55:31.89/chk_autoobs//k5ts2/ autoobs is running! 2006.257.08:55:32.31/chk_autoobs//k5ts3/ autoobs is running! 2006.257.08:55:32.78/chk_autoobs//k5ts4/ autoobs is running! 2006.257.08:55:33.16/chk_obsdata//k5ts1/T2570854??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.08:55:33.55/chk_obsdata//k5ts2/T2570854??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.08:55:33.95/chk_obsdata//k5ts3/T2570854??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.08:55:34.36/chk_obsdata//k5ts4/T2570854??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.08:55:35.10/k5log//k5ts1_log_newline 2006.257.08:55:35.82/k5log//k5ts2_log_newline 2006.257.08:55:36.53/k5log//k5ts3_log_newline 2006.257.08:55:37.23/k5log//k5ts4_log_newline 2006.257.08:55:37.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.08:55:37.25:setupk4=1 2006.257.08:55:37.25$setupk4/echo=on 2006.257.08:55:37.25$setupk4/pcalon 2006.257.08:55:37.25$pcalon/"no phase cal control is implemented here 2006.257.08:55:37.25$setupk4/"tpicd=stop 2006.257.08:55:37.25$setupk4/"rec=synch_on 2006.257.08:55:37.25$setupk4/"rec_mode=128 2006.257.08:55:37.25$setupk4/!* 2006.257.08:55:37.25$setupk4/recpk4 2006.257.08:55:37.25$recpk4/recpatch= 2006.257.08:55:37.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.08:55:37.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.08:55:37.26$setupk4/vck44 2006.257.08:55:37.26$vck44/valo=1,524.99 2006.257.08:55:37.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.08:55:37.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.08:55:37.26#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:37.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:37.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:37.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:37.26#ibcon#enter wrdev, iclass 7, count 0 2006.257.08:55:37.26#ibcon#first serial, iclass 7, count 0 2006.257.08:55:37.26#ibcon#enter sib2, iclass 7, count 0 2006.257.08:55:37.26#ibcon#flushed, iclass 7, count 0 2006.257.08:55:37.26#ibcon#about to write, iclass 7, count 0 2006.257.08:55:37.26#ibcon#wrote, iclass 7, count 0 2006.257.08:55:37.26#ibcon#about to read 3, iclass 7, count 0 2006.257.08:55:37.28#ibcon#read 3, iclass 7, count 0 2006.257.08:55:37.28#ibcon#about to read 4, iclass 7, count 0 2006.257.08:55:37.28#ibcon#read 4, iclass 7, count 0 2006.257.08:55:37.28#ibcon#about to read 5, iclass 7, count 0 2006.257.08:55:37.28#ibcon#read 5, iclass 7, count 0 2006.257.08:55:37.28#ibcon#about to read 6, iclass 7, count 0 2006.257.08:55:37.28#ibcon#read 6, iclass 7, count 0 2006.257.08:55:37.28#ibcon#end of sib2, iclass 7, count 0 2006.257.08:55:37.28#ibcon#*mode == 0, iclass 7, count 0 2006.257.08:55:37.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.08:55:37.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.08:55:37.28#ibcon#*before write, iclass 7, count 0 2006.257.08:55:37.28#ibcon#enter sib2, iclass 7, count 0 2006.257.08:55:37.28#ibcon#flushed, iclass 7, count 0 2006.257.08:55:37.28#ibcon#about to write, iclass 7, count 0 2006.257.08:55:37.28#ibcon#wrote, iclass 7, count 0 2006.257.08:55:37.28#ibcon#about to read 3, iclass 7, count 0 2006.257.08:55:37.33#ibcon#read 3, iclass 7, count 0 2006.257.08:55:37.33#ibcon#about to read 4, iclass 7, count 0 2006.257.08:55:37.33#ibcon#read 4, iclass 7, count 0 2006.257.08:55:37.33#ibcon#about to read 5, iclass 7, count 0 2006.257.08:55:37.33#ibcon#read 5, iclass 7, count 0 2006.257.08:55:37.33#ibcon#about to read 6, iclass 7, count 0 2006.257.08:55:37.33#ibcon#read 6, iclass 7, count 0 2006.257.08:55:37.33#ibcon#end of sib2, iclass 7, count 0 2006.257.08:55:37.33#ibcon#*after write, iclass 7, count 0 2006.257.08:55:37.33#ibcon#*before return 0, iclass 7, count 0 2006.257.08:55:37.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:37.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:37.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.08:55:37.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.08:55:37.33$vck44/va=1,8 2006.257.08:55:37.33#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.08:55:37.33#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.08:55:37.33#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:37.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:37.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:37.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:37.33#ibcon#enter wrdev, iclass 11, count 2 2006.257.08:55:37.33#ibcon#first serial, iclass 11, count 2 2006.257.08:55:37.33#ibcon#enter sib2, iclass 11, count 2 2006.257.08:55:37.33#ibcon#flushed, iclass 11, count 2 2006.257.08:55:37.33#ibcon#about to write, iclass 11, count 2 2006.257.08:55:37.33#ibcon#wrote, iclass 11, count 2 2006.257.08:55:37.33#ibcon#about to read 3, iclass 11, count 2 2006.257.08:55:37.35#ibcon#read 3, iclass 11, count 2 2006.257.08:55:37.35#ibcon#about to read 4, iclass 11, count 2 2006.257.08:55:37.35#ibcon#read 4, iclass 11, count 2 2006.257.08:55:37.35#ibcon#about to read 5, iclass 11, count 2 2006.257.08:55:37.35#ibcon#read 5, iclass 11, count 2 2006.257.08:55:37.35#ibcon#about to read 6, iclass 11, count 2 2006.257.08:55:37.35#ibcon#read 6, iclass 11, count 2 2006.257.08:55:37.35#ibcon#end of sib2, iclass 11, count 2 2006.257.08:55:37.35#ibcon#*mode == 0, iclass 11, count 2 2006.257.08:55:37.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.08:55:37.35#ibcon#[25=AT01-08\r\n] 2006.257.08:55:37.35#ibcon#*before write, iclass 11, count 2 2006.257.08:55:37.35#ibcon#enter sib2, iclass 11, count 2 2006.257.08:55:37.35#ibcon#flushed, iclass 11, count 2 2006.257.08:55:37.35#ibcon#about to write, iclass 11, count 2 2006.257.08:55:37.35#ibcon#wrote, iclass 11, count 2 2006.257.08:55:37.35#ibcon#about to read 3, iclass 11, count 2 2006.257.08:55:37.38#ibcon#read 3, iclass 11, count 2 2006.257.08:55:37.38#ibcon#about to read 4, iclass 11, count 2 2006.257.08:55:37.38#ibcon#read 4, iclass 11, count 2 2006.257.08:55:37.38#ibcon#about to read 5, iclass 11, count 2 2006.257.08:55:37.38#ibcon#read 5, iclass 11, count 2 2006.257.08:55:37.38#ibcon#about to read 6, iclass 11, count 2 2006.257.08:55:37.38#ibcon#read 6, iclass 11, count 2 2006.257.08:55:37.38#ibcon#end of sib2, iclass 11, count 2 2006.257.08:55:37.38#ibcon#*after write, iclass 11, count 2 2006.257.08:55:37.38#ibcon#*before return 0, iclass 11, count 2 2006.257.08:55:37.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:37.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:37.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.08:55:37.38#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:37.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:37.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:37.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:37.50#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:55:37.50#ibcon#first serial, iclass 11, count 0 2006.257.08:55:37.50#ibcon#enter sib2, iclass 11, count 0 2006.257.08:55:37.50#ibcon#flushed, iclass 11, count 0 2006.257.08:55:37.50#ibcon#about to write, iclass 11, count 0 2006.257.08:55:37.50#ibcon#wrote, iclass 11, count 0 2006.257.08:55:37.50#ibcon#about to read 3, iclass 11, count 0 2006.257.08:55:37.52#ibcon#read 3, iclass 11, count 0 2006.257.08:55:37.52#ibcon#about to read 4, iclass 11, count 0 2006.257.08:55:37.52#ibcon#read 4, iclass 11, count 0 2006.257.08:55:37.52#ibcon#about to read 5, iclass 11, count 0 2006.257.08:55:37.52#ibcon#read 5, iclass 11, count 0 2006.257.08:55:37.52#ibcon#about to read 6, iclass 11, count 0 2006.257.08:55:37.52#ibcon#read 6, iclass 11, count 0 2006.257.08:55:37.52#ibcon#end of sib2, iclass 11, count 0 2006.257.08:55:37.52#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:55:37.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:55:37.52#ibcon#[25=USB\r\n] 2006.257.08:55:37.52#ibcon#*before write, iclass 11, count 0 2006.257.08:55:37.52#ibcon#enter sib2, iclass 11, count 0 2006.257.08:55:37.52#ibcon#flushed, iclass 11, count 0 2006.257.08:55:37.52#ibcon#about to write, iclass 11, count 0 2006.257.08:55:37.52#ibcon#wrote, iclass 11, count 0 2006.257.08:55:37.52#ibcon#about to read 3, iclass 11, count 0 2006.257.08:55:37.55#ibcon#read 3, iclass 11, count 0 2006.257.08:55:37.55#ibcon#about to read 4, iclass 11, count 0 2006.257.08:55:37.55#ibcon#read 4, iclass 11, count 0 2006.257.08:55:37.55#ibcon#about to read 5, iclass 11, count 0 2006.257.08:55:37.55#ibcon#read 5, iclass 11, count 0 2006.257.08:55:37.55#ibcon#about to read 6, iclass 11, count 0 2006.257.08:55:37.55#ibcon#read 6, iclass 11, count 0 2006.257.08:55:37.55#ibcon#end of sib2, iclass 11, count 0 2006.257.08:55:37.55#ibcon#*after write, iclass 11, count 0 2006.257.08:55:37.55#ibcon#*before return 0, iclass 11, count 0 2006.257.08:55:37.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:37.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:37.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:55:37.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:55:37.55$vck44/valo=2,534.99 2006.257.08:55:37.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.08:55:37.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.08:55:37.55#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:37.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:37.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:37.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:37.55#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:55:37.55#ibcon#first serial, iclass 13, count 0 2006.257.08:55:37.55#ibcon#enter sib2, iclass 13, count 0 2006.257.08:55:37.55#ibcon#flushed, iclass 13, count 0 2006.257.08:55:37.55#ibcon#about to write, iclass 13, count 0 2006.257.08:55:37.55#ibcon#wrote, iclass 13, count 0 2006.257.08:55:37.55#ibcon#about to read 3, iclass 13, count 0 2006.257.08:55:37.57#ibcon#read 3, iclass 13, count 0 2006.257.08:55:37.57#ibcon#about to read 4, iclass 13, count 0 2006.257.08:55:37.57#ibcon#read 4, iclass 13, count 0 2006.257.08:55:37.57#ibcon#about to read 5, iclass 13, count 0 2006.257.08:55:37.57#ibcon#read 5, iclass 13, count 0 2006.257.08:55:37.57#ibcon#about to read 6, iclass 13, count 0 2006.257.08:55:37.57#ibcon#read 6, iclass 13, count 0 2006.257.08:55:37.57#ibcon#end of sib2, iclass 13, count 0 2006.257.08:55:37.57#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:55:37.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:55:37.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.08:55:37.57#ibcon#*before write, iclass 13, count 0 2006.257.08:55:37.57#ibcon#enter sib2, iclass 13, count 0 2006.257.08:55:37.57#ibcon#flushed, iclass 13, count 0 2006.257.08:55:37.57#ibcon#about to write, iclass 13, count 0 2006.257.08:55:37.57#ibcon#wrote, iclass 13, count 0 2006.257.08:55:37.57#ibcon#about to read 3, iclass 13, count 0 2006.257.08:55:37.61#ibcon#read 3, iclass 13, count 0 2006.257.08:55:37.61#ibcon#about to read 4, iclass 13, count 0 2006.257.08:55:37.61#ibcon#read 4, iclass 13, count 0 2006.257.08:55:37.61#ibcon#about to read 5, iclass 13, count 0 2006.257.08:55:37.61#ibcon#read 5, iclass 13, count 0 2006.257.08:55:37.61#ibcon#about to read 6, iclass 13, count 0 2006.257.08:55:37.61#ibcon#read 6, iclass 13, count 0 2006.257.08:55:37.61#ibcon#end of sib2, iclass 13, count 0 2006.257.08:55:37.61#ibcon#*after write, iclass 13, count 0 2006.257.08:55:37.61#ibcon#*before return 0, iclass 13, count 0 2006.257.08:55:37.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:37.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:37.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:55:37.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:55:37.61$vck44/va=2,7 2006.257.08:55:37.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.08:55:37.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.08:55:37.61#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:37.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:37.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:37.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:37.67#ibcon#enter wrdev, iclass 15, count 2 2006.257.08:55:37.67#ibcon#first serial, iclass 15, count 2 2006.257.08:55:37.67#ibcon#enter sib2, iclass 15, count 2 2006.257.08:55:37.67#ibcon#flushed, iclass 15, count 2 2006.257.08:55:37.67#ibcon#about to write, iclass 15, count 2 2006.257.08:55:37.67#ibcon#wrote, iclass 15, count 2 2006.257.08:55:37.67#ibcon#about to read 3, iclass 15, count 2 2006.257.08:55:37.69#ibcon#read 3, iclass 15, count 2 2006.257.08:55:37.69#ibcon#about to read 4, iclass 15, count 2 2006.257.08:55:37.69#ibcon#read 4, iclass 15, count 2 2006.257.08:55:37.69#ibcon#about to read 5, iclass 15, count 2 2006.257.08:55:37.69#ibcon#read 5, iclass 15, count 2 2006.257.08:55:37.69#ibcon#about to read 6, iclass 15, count 2 2006.257.08:55:37.69#ibcon#read 6, iclass 15, count 2 2006.257.08:55:37.69#ibcon#end of sib2, iclass 15, count 2 2006.257.08:55:37.69#ibcon#*mode == 0, iclass 15, count 2 2006.257.08:55:37.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.08:55:37.69#ibcon#[25=AT02-07\r\n] 2006.257.08:55:37.69#ibcon#*before write, iclass 15, count 2 2006.257.08:55:37.69#ibcon#enter sib2, iclass 15, count 2 2006.257.08:55:37.69#ibcon#flushed, iclass 15, count 2 2006.257.08:55:37.69#ibcon#about to write, iclass 15, count 2 2006.257.08:55:37.69#ibcon#wrote, iclass 15, count 2 2006.257.08:55:37.69#ibcon#about to read 3, iclass 15, count 2 2006.257.08:55:37.72#ibcon#read 3, iclass 15, count 2 2006.257.08:55:37.72#ibcon#about to read 4, iclass 15, count 2 2006.257.08:55:37.72#ibcon#read 4, iclass 15, count 2 2006.257.08:55:37.72#ibcon#about to read 5, iclass 15, count 2 2006.257.08:55:37.72#ibcon#read 5, iclass 15, count 2 2006.257.08:55:37.72#ibcon#about to read 6, iclass 15, count 2 2006.257.08:55:37.72#ibcon#read 6, iclass 15, count 2 2006.257.08:55:37.72#ibcon#end of sib2, iclass 15, count 2 2006.257.08:55:37.72#ibcon#*after write, iclass 15, count 2 2006.257.08:55:37.72#ibcon#*before return 0, iclass 15, count 2 2006.257.08:55:37.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:37.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:37.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.08:55:37.72#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:37.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:37.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:37.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:37.84#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:55:37.84#ibcon#first serial, iclass 15, count 0 2006.257.08:55:37.84#ibcon#enter sib2, iclass 15, count 0 2006.257.08:55:37.84#ibcon#flushed, iclass 15, count 0 2006.257.08:55:37.84#ibcon#about to write, iclass 15, count 0 2006.257.08:55:37.84#ibcon#wrote, iclass 15, count 0 2006.257.08:55:37.84#ibcon#about to read 3, iclass 15, count 0 2006.257.08:55:37.86#ibcon#read 3, iclass 15, count 0 2006.257.08:55:37.86#ibcon#about to read 4, iclass 15, count 0 2006.257.08:55:37.86#ibcon#read 4, iclass 15, count 0 2006.257.08:55:37.86#ibcon#about to read 5, iclass 15, count 0 2006.257.08:55:37.86#ibcon#read 5, iclass 15, count 0 2006.257.08:55:37.86#ibcon#about to read 6, iclass 15, count 0 2006.257.08:55:37.86#ibcon#read 6, iclass 15, count 0 2006.257.08:55:37.86#ibcon#end of sib2, iclass 15, count 0 2006.257.08:55:37.86#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:55:37.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:55:37.86#ibcon#[25=USB\r\n] 2006.257.08:55:37.86#ibcon#*before write, iclass 15, count 0 2006.257.08:55:37.86#ibcon#enter sib2, iclass 15, count 0 2006.257.08:55:37.86#ibcon#flushed, iclass 15, count 0 2006.257.08:55:37.86#ibcon#about to write, iclass 15, count 0 2006.257.08:55:37.86#ibcon#wrote, iclass 15, count 0 2006.257.08:55:37.86#ibcon#about to read 3, iclass 15, count 0 2006.257.08:55:37.89#ibcon#read 3, iclass 15, count 0 2006.257.08:55:37.89#ibcon#about to read 4, iclass 15, count 0 2006.257.08:55:37.89#ibcon#read 4, iclass 15, count 0 2006.257.08:55:37.89#ibcon#about to read 5, iclass 15, count 0 2006.257.08:55:37.89#ibcon#read 5, iclass 15, count 0 2006.257.08:55:37.89#ibcon#about to read 6, iclass 15, count 0 2006.257.08:55:37.89#ibcon#read 6, iclass 15, count 0 2006.257.08:55:37.89#ibcon#end of sib2, iclass 15, count 0 2006.257.08:55:37.89#ibcon#*after write, iclass 15, count 0 2006.257.08:55:37.89#ibcon#*before return 0, iclass 15, count 0 2006.257.08:55:37.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:37.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:37.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:55:37.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:55:37.89$vck44/valo=3,564.99 2006.257.08:55:37.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.08:55:37.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.08:55:37.89#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:37.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:37.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:37.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:37.89#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:55:37.89#ibcon#first serial, iclass 17, count 0 2006.257.08:55:37.89#ibcon#enter sib2, iclass 17, count 0 2006.257.08:55:37.89#ibcon#flushed, iclass 17, count 0 2006.257.08:55:37.89#ibcon#about to write, iclass 17, count 0 2006.257.08:55:37.89#ibcon#wrote, iclass 17, count 0 2006.257.08:55:37.89#ibcon#about to read 3, iclass 17, count 0 2006.257.08:55:37.91#ibcon#read 3, iclass 17, count 0 2006.257.08:55:37.91#ibcon#about to read 4, iclass 17, count 0 2006.257.08:55:37.91#ibcon#read 4, iclass 17, count 0 2006.257.08:55:37.91#ibcon#about to read 5, iclass 17, count 0 2006.257.08:55:37.91#ibcon#read 5, iclass 17, count 0 2006.257.08:55:37.91#ibcon#about to read 6, iclass 17, count 0 2006.257.08:55:37.91#ibcon#read 6, iclass 17, count 0 2006.257.08:55:37.91#ibcon#end of sib2, iclass 17, count 0 2006.257.08:55:37.91#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:55:37.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:55:37.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.08:55:37.91#ibcon#*before write, iclass 17, count 0 2006.257.08:55:37.91#ibcon#enter sib2, iclass 17, count 0 2006.257.08:55:37.91#ibcon#flushed, iclass 17, count 0 2006.257.08:55:37.91#ibcon#about to write, iclass 17, count 0 2006.257.08:55:37.91#ibcon#wrote, iclass 17, count 0 2006.257.08:55:37.91#ibcon#about to read 3, iclass 17, count 0 2006.257.08:55:37.95#ibcon#read 3, iclass 17, count 0 2006.257.08:55:37.95#ibcon#about to read 4, iclass 17, count 0 2006.257.08:55:37.95#ibcon#read 4, iclass 17, count 0 2006.257.08:55:37.95#ibcon#about to read 5, iclass 17, count 0 2006.257.08:55:37.95#ibcon#read 5, iclass 17, count 0 2006.257.08:55:37.95#ibcon#about to read 6, iclass 17, count 0 2006.257.08:55:37.95#ibcon#read 6, iclass 17, count 0 2006.257.08:55:37.95#ibcon#end of sib2, iclass 17, count 0 2006.257.08:55:37.95#ibcon#*after write, iclass 17, count 0 2006.257.08:55:37.95#ibcon#*before return 0, iclass 17, count 0 2006.257.08:55:37.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:37.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:37.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:55:37.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:55:37.95$vck44/va=3,8 2006.257.08:55:37.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.08:55:37.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.08:55:37.95#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:37.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:38.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:38.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:38.01#ibcon#enter wrdev, iclass 19, count 2 2006.257.08:55:38.01#ibcon#first serial, iclass 19, count 2 2006.257.08:55:38.01#ibcon#enter sib2, iclass 19, count 2 2006.257.08:55:38.01#ibcon#flushed, iclass 19, count 2 2006.257.08:55:38.01#ibcon#about to write, iclass 19, count 2 2006.257.08:55:38.01#ibcon#wrote, iclass 19, count 2 2006.257.08:55:38.01#ibcon#about to read 3, iclass 19, count 2 2006.257.08:55:38.03#ibcon#read 3, iclass 19, count 2 2006.257.08:55:38.03#ibcon#about to read 4, iclass 19, count 2 2006.257.08:55:38.03#ibcon#read 4, iclass 19, count 2 2006.257.08:55:38.03#ibcon#about to read 5, iclass 19, count 2 2006.257.08:55:38.03#ibcon#read 5, iclass 19, count 2 2006.257.08:55:38.03#ibcon#about to read 6, iclass 19, count 2 2006.257.08:55:38.03#ibcon#read 6, iclass 19, count 2 2006.257.08:55:38.03#ibcon#end of sib2, iclass 19, count 2 2006.257.08:55:38.03#ibcon#*mode == 0, iclass 19, count 2 2006.257.08:55:38.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.08:55:38.03#ibcon#[25=AT03-08\r\n] 2006.257.08:55:38.03#ibcon#*before write, iclass 19, count 2 2006.257.08:55:38.03#ibcon#enter sib2, iclass 19, count 2 2006.257.08:55:38.03#ibcon#flushed, iclass 19, count 2 2006.257.08:55:38.03#ibcon#about to write, iclass 19, count 2 2006.257.08:55:38.03#ibcon#wrote, iclass 19, count 2 2006.257.08:55:38.03#ibcon#about to read 3, iclass 19, count 2 2006.257.08:55:38.06#ibcon#read 3, iclass 19, count 2 2006.257.08:55:38.06#ibcon#about to read 4, iclass 19, count 2 2006.257.08:55:38.06#ibcon#read 4, iclass 19, count 2 2006.257.08:55:38.06#ibcon#about to read 5, iclass 19, count 2 2006.257.08:55:38.06#ibcon#read 5, iclass 19, count 2 2006.257.08:55:38.06#ibcon#about to read 6, iclass 19, count 2 2006.257.08:55:38.06#ibcon#read 6, iclass 19, count 2 2006.257.08:55:38.06#ibcon#end of sib2, iclass 19, count 2 2006.257.08:55:38.06#ibcon#*after write, iclass 19, count 2 2006.257.08:55:38.06#ibcon#*before return 0, iclass 19, count 2 2006.257.08:55:38.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:38.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:38.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.08:55:38.06#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:38.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:38.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:38.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:38.18#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:55:38.18#ibcon#first serial, iclass 19, count 0 2006.257.08:55:38.18#ibcon#enter sib2, iclass 19, count 0 2006.257.08:55:38.18#ibcon#flushed, iclass 19, count 0 2006.257.08:55:38.18#ibcon#about to write, iclass 19, count 0 2006.257.08:55:38.18#ibcon#wrote, iclass 19, count 0 2006.257.08:55:38.18#ibcon#about to read 3, iclass 19, count 0 2006.257.08:55:38.20#ibcon#read 3, iclass 19, count 0 2006.257.08:55:38.20#ibcon#about to read 4, iclass 19, count 0 2006.257.08:55:38.20#ibcon#read 4, iclass 19, count 0 2006.257.08:55:38.20#ibcon#about to read 5, iclass 19, count 0 2006.257.08:55:38.20#ibcon#read 5, iclass 19, count 0 2006.257.08:55:38.20#ibcon#about to read 6, iclass 19, count 0 2006.257.08:55:38.20#ibcon#read 6, iclass 19, count 0 2006.257.08:55:38.20#ibcon#end of sib2, iclass 19, count 0 2006.257.08:55:38.20#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:55:38.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:55:38.20#ibcon#[25=USB\r\n] 2006.257.08:55:38.20#ibcon#*before write, iclass 19, count 0 2006.257.08:55:38.20#ibcon#enter sib2, iclass 19, count 0 2006.257.08:55:38.20#ibcon#flushed, iclass 19, count 0 2006.257.08:55:38.20#ibcon#about to write, iclass 19, count 0 2006.257.08:55:38.20#ibcon#wrote, iclass 19, count 0 2006.257.08:55:38.20#ibcon#about to read 3, iclass 19, count 0 2006.257.08:55:38.23#ibcon#read 3, iclass 19, count 0 2006.257.08:55:38.23#ibcon#about to read 4, iclass 19, count 0 2006.257.08:55:38.23#ibcon#read 4, iclass 19, count 0 2006.257.08:55:38.23#ibcon#about to read 5, iclass 19, count 0 2006.257.08:55:38.23#ibcon#read 5, iclass 19, count 0 2006.257.08:55:38.23#ibcon#about to read 6, iclass 19, count 0 2006.257.08:55:38.23#ibcon#read 6, iclass 19, count 0 2006.257.08:55:38.23#ibcon#end of sib2, iclass 19, count 0 2006.257.08:55:38.23#ibcon#*after write, iclass 19, count 0 2006.257.08:55:38.23#ibcon#*before return 0, iclass 19, count 0 2006.257.08:55:38.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:38.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:38.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:55:38.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:55:38.23$vck44/valo=4,624.99 2006.257.08:55:38.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.08:55:38.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.08:55:38.23#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:38.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:38.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:38.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:38.23#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:55:38.23#ibcon#first serial, iclass 21, count 0 2006.257.08:55:38.23#ibcon#enter sib2, iclass 21, count 0 2006.257.08:55:38.23#ibcon#flushed, iclass 21, count 0 2006.257.08:55:38.23#ibcon#about to write, iclass 21, count 0 2006.257.08:55:38.23#ibcon#wrote, iclass 21, count 0 2006.257.08:55:38.23#ibcon#about to read 3, iclass 21, count 0 2006.257.08:55:38.25#ibcon#read 3, iclass 21, count 0 2006.257.08:55:38.25#ibcon#about to read 4, iclass 21, count 0 2006.257.08:55:38.25#ibcon#read 4, iclass 21, count 0 2006.257.08:55:38.25#ibcon#about to read 5, iclass 21, count 0 2006.257.08:55:38.25#ibcon#read 5, iclass 21, count 0 2006.257.08:55:38.25#ibcon#about to read 6, iclass 21, count 0 2006.257.08:55:38.25#ibcon#read 6, iclass 21, count 0 2006.257.08:55:38.25#ibcon#end of sib2, iclass 21, count 0 2006.257.08:55:38.25#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:55:38.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:55:38.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.08:55:38.25#ibcon#*before write, iclass 21, count 0 2006.257.08:55:38.25#ibcon#enter sib2, iclass 21, count 0 2006.257.08:55:38.25#ibcon#flushed, iclass 21, count 0 2006.257.08:55:38.25#ibcon#about to write, iclass 21, count 0 2006.257.08:55:38.25#ibcon#wrote, iclass 21, count 0 2006.257.08:55:38.25#ibcon#about to read 3, iclass 21, count 0 2006.257.08:55:38.29#ibcon#read 3, iclass 21, count 0 2006.257.08:55:38.29#ibcon#about to read 4, iclass 21, count 0 2006.257.08:55:38.29#ibcon#read 4, iclass 21, count 0 2006.257.08:55:38.29#ibcon#about to read 5, iclass 21, count 0 2006.257.08:55:38.29#ibcon#read 5, iclass 21, count 0 2006.257.08:55:38.29#ibcon#about to read 6, iclass 21, count 0 2006.257.08:55:38.29#ibcon#read 6, iclass 21, count 0 2006.257.08:55:38.29#ibcon#end of sib2, iclass 21, count 0 2006.257.08:55:38.29#ibcon#*after write, iclass 21, count 0 2006.257.08:55:38.29#ibcon#*before return 0, iclass 21, count 0 2006.257.08:55:38.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:38.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:38.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:55:38.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:55:38.29$vck44/va=4,7 2006.257.08:55:38.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.08:55:38.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.08:55:38.29#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:38.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:38.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:38.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:38.35#ibcon#enter wrdev, iclass 23, count 2 2006.257.08:55:38.35#ibcon#first serial, iclass 23, count 2 2006.257.08:55:38.35#ibcon#enter sib2, iclass 23, count 2 2006.257.08:55:38.35#ibcon#flushed, iclass 23, count 2 2006.257.08:55:38.35#ibcon#about to write, iclass 23, count 2 2006.257.08:55:38.35#ibcon#wrote, iclass 23, count 2 2006.257.08:55:38.35#ibcon#about to read 3, iclass 23, count 2 2006.257.08:55:38.37#ibcon#read 3, iclass 23, count 2 2006.257.08:55:38.37#ibcon#about to read 4, iclass 23, count 2 2006.257.08:55:38.37#ibcon#read 4, iclass 23, count 2 2006.257.08:55:38.37#ibcon#about to read 5, iclass 23, count 2 2006.257.08:55:38.37#ibcon#read 5, iclass 23, count 2 2006.257.08:55:38.37#ibcon#about to read 6, iclass 23, count 2 2006.257.08:55:38.37#ibcon#read 6, iclass 23, count 2 2006.257.08:55:38.37#ibcon#end of sib2, iclass 23, count 2 2006.257.08:55:38.37#ibcon#*mode == 0, iclass 23, count 2 2006.257.08:55:38.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.08:55:38.37#ibcon#[25=AT04-07\r\n] 2006.257.08:55:38.37#ibcon#*before write, iclass 23, count 2 2006.257.08:55:38.37#ibcon#enter sib2, iclass 23, count 2 2006.257.08:55:38.37#ibcon#flushed, iclass 23, count 2 2006.257.08:55:38.37#ibcon#about to write, iclass 23, count 2 2006.257.08:55:38.37#ibcon#wrote, iclass 23, count 2 2006.257.08:55:38.37#ibcon#about to read 3, iclass 23, count 2 2006.257.08:55:38.40#ibcon#read 3, iclass 23, count 2 2006.257.08:55:38.40#ibcon#about to read 4, iclass 23, count 2 2006.257.08:55:38.40#ibcon#read 4, iclass 23, count 2 2006.257.08:55:38.40#ibcon#about to read 5, iclass 23, count 2 2006.257.08:55:38.40#ibcon#read 5, iclass 23, count 2 2006.257.08:55:38.40#ibcon#about to read 6, iclass 23, count 2 2006.257.08:55:38.40#ibcon#read 6, iclass 23, count 2 2006.257.08:55:38.40#ibcon#end of sib2, iclass 23, count 2 2006.257.08:55:38.40#ibcon#*after write, iclass 23, count 2 2006.257.08:55:38.40#ibcon#*before return 0, iclass 23, count 2 2006.257.08:55:38.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:38.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:38.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.08:55:38.40#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:38.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:38.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:38.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:38.52#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:55:38.52#ibcon#first serial, iclass 23, count 0 2006.257.08:55:38.52#ibcon#enter sib2, iclass 23, count 0 2006.257.08:55:38.52#ibcon#flushed, iclass 23, count 0 2006.257.08:55:38.52#ibcon#about to write, iclass 23, count 0 2006.257.08:55:38.52#ibcon#wrote, iclass 23, count 0 2006.257.08:55:38.52#ibcon#about to read 3, iclass 23, count 0 2006.257.08:55:38.54#ibcon#read 3, iclass 23, count 0 2006.257.08:55:38.54#ibcon#about to read 4, iclass 23, count 0 2006.257.08:55:38.54#ibcon#read 4, iclass 23, count 0 2006.257.08:55:38.54#ibcon#about to read 5, iclass 23, count 0 2006.257.08:55:38.54#ibcon#read 5, iclass 23, count 0 2006.257.08:55:38.54#ibcon#about to read 6, iclass 23, count 0 2006.257.08:55:38.54#ibcon#read 6, iclass 23, count 0 2006.257.08:55:38.54#ibcon#end of sib2, iclass 23, count 0 2006.257.08:55:38.54#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:55:38.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:55:38.54#ibcon#[25=USB\r\n] 2006.257.08:55:38.54#ibcon#*before write, iclass 23, count 0 2006.257.08:55:38.54#ibcon#enter sib2, iclass 23, count 0 2006.257.08:55:38.54#ibcon#flushed, iclass 23, count 0 2006.257.08:55:38.54#ibcon#about to write, iclass 23, count 0 2006.257.08:55:38.54#ibcon#wrote, iclass 23, count 0 2006.257.08:55:38.54#ibcon#about to read 3, iclass 23, count 0 2006.257.08:55:38.57#ibcon#read 3, iclass 23, count 0 2006.257.08:55:38.57#ibcon#about to read 4, iclass 23, count 0 2006.257.08:55:38.57#ibcon#read 4, iclass 23, count 0 2006.257.08:55:38.57#ibcon#about to read 5, iclass 23, count 0 2006.257.08:55:38.57#ibcon#read 5, iclass 23, count 0 2006.257.08:55:38.57#ibcon#about to read 6, iclass 23, count 0 2006.257.08:55:38.57#ibcon#read 6, iclass 23, count 0 2006.257.08:55:38.57#ibcon#end of sib2, iclass 23, count 0 2006.257.08:55:38.57#ibcon#*after write, iclass 23, count 0 2006.257.08:55:38.57#ibcon#*before return 0, iclass 23, count 0 2006.257.08:55:38.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:38.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:38.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:55:38.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:55:38.57$vck44/valo=5,734.99 2006.257.08:55:38.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.08:55:38.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.08:55:38.57#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:38.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:38.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:38.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:38.57#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:55:38.57#ibcon#first serial, iclass 25, count 0 2006.257.08:55:38.57#ibcon#enter sib2, iclass 25, count 0 2006.257.08:55:38.57#ibcon#flushed, iclass 25, count 0 2006.257.08:55:38.57#ibcon#about to write, iclass 25, count 0 2006.257.08:55:38.57#ibcon#wrote, iclass 25, count 0 2006.257.08:55:38.57#ibcon#about to read 3, iclass 25, count 0 2006.257.08:55:38.59#ibcon#read 3, iclass 25, count 0 2006.257.08:55:38.59#ibcon#about to read 4, iclass 25, count 0 2006.257.08:55:38.59#ibcon#read 4, iclass 25, count 0 2006.257.08:55:38.59#ibcon#about to read 5, iclass 25, count 0 2006.257.08:55:38.59#ibcon#read 5, iclass 25, count 0 2006.257.08:55:38.59#ibcon#about to read 6, iclass 25, count 0 2006.257.08:55:38.59#ibcon#read 6, iclass 25, count 0 2006.257.08:55:38.59#ibcon#end of sib2, iclass 25, count 0 2006.257.08:55:38.59#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:55:38.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:55:38.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.08:55:38.59#ibcon#*before write, iclass 25, count 0 2006.257.08:55:38.59#ibcon#enter sib2, iclass 25, count 0 2006.257.08:55:38.59#ibcon#flushed, iclass 25, count 0 2006.257.08:55:38.59#ibcon#about to write, iclass 25, count 0 2006.257.08:55:38.59#ibcon#wrote, iclass 25, count 0 2006.257.08:55:38.59#ibcon#about to read 3, iclass 25, count 0 2006.257.08:55:38.63#ibcon#read 3, iclass 25, count 0 2006.257.08:55:38.63#ibcon#about to read 4, iclass 25, count 0 2006.257.08:55:38.63#ibcon#read 4, iclass 25, count 0 2006.257.08:55:38.63#ibcon#about to read 5, iclass 25, count 0 2006.257.08:55:38.63#ibcon#read 5, iclass 25, count 0 2006.257.08:55:38.63#ibcon#about to read 6, iclass 25, count 0 2006.257.08:55:38.63#ibcon#read 6, iclass 25, count 0 2006.257.08:55:38.63#ibcon#end of sib2, iclass 25, count 0 2006.257.08:55:38.63#ibcon#*after write, iclass 25, count 0 2006.257.08:55:38.63#ibcon#*before return 0, iclass 25, count 0 2006.257.08:55:38.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:38.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:38.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:55:38.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:55:38.63$vck44/va=5,4 2006.257.08:55:38.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.08:55:38.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.08:55:38.63#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:38.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:38.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:38.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:38.69#ibcon#enter wrdev, iclass 27, count 2 2006.257.08:55:38.69#ibcon#first serial, iclass 27, count 2 2006.257.08:55:38.69#ibcon#enter sib2, iclass 27, count 2 2006.257.08:55:38.69#ibcon#flushed, iclass 27, count 2 2006.257.08:55:38.69#ibcon#about to write, iclass 27, count 2 2006.257.08:55:38.69#ibcon#wrote, iclass 27, count 2 2006.257.08:55:38.69#ibcon#about to read 3, iclass 27, count 2 2006.257.08:55:38.71#ibcon#read 3, iclass 27, count 2 2006.257.08:55:38.71#ibcon#about to read 4, iclass 27, count 2 2006.257.08:55:38.71#ibcon#read 4, iclass 27, count 2 2006.257.08:55:38.71#ibcon#about to read 5, iclass 27, count 2 2006.257.08:55:38.71#ibcon#read 5, iclass 27, count 2 2006.257.08:55:38.71#ibcon#about to read 6, iclass 27, count 2 2006.257.08:55:38.71#ibcon#read 6, iclass 27, count 2 2006.257.08:55:38.71#ibcon#end of sib2, iclass 27, count 2 2006.257.08:55:38.71#ibcon#*mode == 0, iclass 27, count 2 2006.257.08:55:38.71#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.08:55:38.71#ibcon#[25=AT05-04\r\n] 2006.257.08:55:38.71#ibcon#*before write, iclass 27, count 2 2006.257.08:55:38.71#ibcon#enter sib2, iclass 27, count 2 2006.257.08:55:38.71#ibcon#flushed, iclass 27, count 2 2006.257.08:55:38.71#ibcon#about to write, iclass 27, count 2 2006.257.08:55:38.71#ibcon#wrote, iclass 27, count 2 2006.257.08:55:38.71#ibcon#about to read 3, iclass 27, count 2 2006.257.08:55:38.74#ibcon#read 3, iclass 27, count 2 2006.257.08:55:38.74#ibcon#about to read 4, iclass 27, count 2 2006.257.08:55:38.74#ibcon#read 4, iclass 27, count 2 2006.257.08:55:38.74#ibcon#about to read 5, iclass 27, count 2 2006.257.08:55:38.74#ibcon#read 5, iclass 27, count 2 2006.257.08:55:38.74#ibcon#about to read 6, iclass 27, count 2 2006.257.08:55:38.74#ibcon#read 6, iclass 27, count 2 2006.257.08:55:38.74#ibcon#end of sib2, iclass 27, count 2 2006.257.08:55:38.74#ibcon#*after write, iclass 27, count 2 2006.257.08:55:38.74#ibcon#*before return 0, iclass 27, count 2 2006.257.08:55:38.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:38.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:38.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.08:55:38.74#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:38.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:38.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:38.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:38.86#ibcon#enter wrdev, iclass 27, count 0 2006.257.08:55:38.86#ibcon#first serial, iclass 27, count 0 2006.257.08:55:38.86#ibcon#enter sib2, iclass 27, count 0 2006.257.08:55:38.86#ibcon#flushed, iclass 27, count 0 2006.257.08:55:38.86#ibcon#about to write, iclass 27, count 0 2006.257.08:55:38.86#ibcon#wrote, iclass 27, count 0 2006.257.08:55:38.86#ibcon#about to read 3, iclass 27, count 0 2006.257.08:55:38.88#ibcon#read 3, iclass 27, count 0 2006.257.08:55:38.88#ibcon#about to read 4, iclass 27, count 0 2006.257.08:55:38.88#ibcon#read 4, iclass 27, count 0 2006.257.08:55:38.88#ibcon#about to read 5, iclass 27, count 0 2006.257.08:55:38.88#ibcon#read 5, iclass 27, count 0 2006.257.08:55:38.88#ibcon#about to read 6, iclass 27, count 0 2006.257.08:55:38.88#ibcon#read 6, iclass 27, count 0 2006.257.08:55:38.88#ibcon#end of sib2, iclass 27, count 0 2006.257.08:55:38.88#ibcon#*mode == 0, iclass 27, count 0 2006.257.08:55:38.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.08:55:38.88#ibcon#[25=USB\r\n] 2006.257.08:55:38.88#ibcon#*before write, iclass 27, count 0 2006.257.08:55:38.88#ibcon#enter sib2, iclass 27, count 0 2006.257.08:55:38.88#ibcon#flushed, iclass 27, count 0 2006.257.08:55:38.88#ibcon#about to write, iclass 27, count 0 2006.257.08:55:38.88#ibcon#wrote, iclass 27, count 0 2006.257.08:55:38.88#ibcon#about to read 3, iclass 27, count 0 2006.257.08:55:38.91#ibcon#read 3, iclass 27, count 0 2006.257.08:55:38.91#ibcon#about to read 4, iclass 27, count 0 2006.257.08:55:38.91#ibcon#read 4, iclass 27, count 0 2006.257.08:55:38.91#ibcon#about to read 5, iclass 27, count 0 2006.257.08:55:38.91#ibcon#read 5, iclass 27, count 0 2006.257.08:55:38.91#ibcon#about to read 6, iclass 27, count 0 2006.257.08:55:38.91#ibcon#read 6, iclass 27, count 0 2006.257.08:55:38.91#ibcon#end of sib2, iclass 27, count 0 2006.257.08:55:38.91#ibcon#*after write, iclass 27, count 0 2006.257.08:55:38.91#ibcon#*before return 0, iclass 27, count 0 2006.257.08:55:38.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:38.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:38.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.08:55:38.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.08:55:38.91$vck44/valo=6,814.99 2006.257.08:55:38.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.08:55:38.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.08:55:38.91#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:38.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:38.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:38.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:38.91#ibcon#enter wrdev, iclass 29, count 0 2006.257.08:55:38.91#ibcon#first serial, iclass 29, count 0 2006.257.08:55:38.91#ibcon#enter sib2, iclass 29, count 0 2006.257.08:55:38.91#ibcon#flushed, iclass 29, count 0 2006.257.08:55:38.91#ibcon#about to write, iclass 29, count 0 2006.257.08:55:38.91#ibcon#wrote, iclass 29, count 0 2006.257.08:55:38.91#ibcon#about to read 3, iclass 29, count 0 2006.257.08:55:38.93#ibcon#read 3, iclass 29, count 0 2006.257.08:55:38.93#ibcon#about to read 4, iclass 29, count 0 2006.257.08:55:38.93#ibcon#read 4, iclass 29, count 0 2006.257.08:55:38.93#ibcon#about to read 5, iclass 29, count 0 2006.257.08:55:38.93#ibcon#read 5, iclass 29, count 0 2006.257.08:55:38.93#ibcon#about to read 6, iclass 29, count 0 2006.257.08:55:38.93#ibcon#read 6, iclass 29, count 0 2006.257.08:55:38.93#ibcon#end of sib2, iclass 29, count 0 2006.257.08:55:38.93#ibcon#*mode == 0, iclass 29, count 0 2006.257.08:55:38.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.08:55:38.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.08:55:38.93#ibcon#*before write, iclass 29, count 0 2006.257.08:55:38.93#ibcon#enter sib2, iclass 29, count 0 2006.257.08:55:38.93#ibcon#flushed, iclass 29, count 0 2006.257.08:55:38.93#ibcon#about to write, iclass 29, count 0 2006.257.08:55:38.93#ibcon#wrote, iclass 29, count 0 2006.257.08:55:38.93#ibcon#about to read 3, iclass 29, count 0 2006.257.08:55:38.97#ibcon#read 3, iclass 29, count 0 2006.257.08:55:38.97#ibcon#about to read 4, iclass 29, count 0 2006.257.08:55:38.97#ibcon#read 4, iclass 29, count 0 2006.257.08:55:38.97#ibcon#about to read 5, iclass 29, count 0 2006.257.08:55:38.97#ibcon#read 5, iclass 29, count 0 2006.257.08:55:38.97#ibcon#about to read 6, iclass 29, count 0 2006.257.08:55:38.97#ibcon#read 6, iclass 29, count 0 2006.257.08:55:38.97#ibcon#end of sib2, iclass 29, count 0 2006.257.08:55:38.97#ibcon#*after write, iclass 29, count 0 2006.257.08:55:38.97#ibcon#*before return 0, iclass 29, count 0 2006.257.08:55:38.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:38.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:38.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.08:55:38.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.08:55:38.97$vck44/va=6,4 2006.257.08:55:38.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.08:55:38.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.08:55:38.97#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:38.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:39.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:39.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:39.03#ibcon#enter wrdev, iclass 31, count 2 2006.257.08:55:39.03#ibcon#first serial, iclass 31, count 2 2006.257.08:55:39.03#ibcon#enter sib2, iclass 31, count 2 2006.257.08:55:39.03#ibcon#flushed, iclass 31, count 2 2006.257.08:55:39.03#ibcon#about to write, iclass 31, count 2 2006.257.08:55:39.03#ibcon#wrote, iclass 31, count 2 2006.257.08:55:39.03#ibcon#about to read 3, iclass 31, count 2 2006.257.08:55:39.05#ibcon#read 3, iclass 31, count 2 2006.257.08:55:39.05#ibcon#about to read 4, iclass 31, count 2 2006.257.08:55:39.05#ibcon#read 4, iclass 31, count 2 2006.257.08:55:39.05#ibcon#about to read 5, iclass 31, count 2 2006.257.08:55:39.05#ibcon#read 5, iclass 31, count 2 2006.257.08:55:39.05#ibcon#about to read 6, iclass 31, count 2 2006.257.08:55:39.05#ibcon#read 6, iclass 31, count 2 2006.257.08:55:39.05#ibcon#end of sib2, iclass 31, count 2 2006.257.08:55:39.05#ibcon#*mode == 0, iclass 31, count 2 2006.257.08:55:39.05#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.08:55:39.05#ibcon#[25=AT06-04\r\n] 2006.257.08:55:39.05#ibcon#*before write, iclass 31, count 2 2006.257.08:55:39.05#ibcon#enter sib2, iclass 31, count 2 2006.257.08:55:39.05#ibcon#flushed, iclass 31, count 2 2006.257.08:55:39.05#ibcon#about to write, iclass 31, count 2 2006.257.08:55:39.05#ibcon#wrote, iclass 31, count 2 2006.257.08:55:39.05#ibcon#about to read 3, iclass 31, count 2 2006.257.08:55:39.08#ibcon#read 3, iclass 31, count 2 2006.257.08:55:39.08#ibcon#about to read 4, iclass 31, count 2 2006.257.08:55:39.08#ibcon#read 4, iclass 31, count 2 2006.257.08:55:39.08#ibcon#about to read 5, iclass 31, count 2 2006.257.08:55:39.08#ibcon#read 5, iclass 31, count 2 2006.257.08:55:39.08#ibcon#about to read 6, iclass 31, count 2 2006.257.08:55:39.08#ibcon#read 6, iclass 31, count 2 2006.257.08:55:39.08#ibcon#end of sib2, iclass 31, count 2 2006.257.08:55:39.08#ibcon#*after write, iclass 31, count 2 2006.257.08:55:39.08#ibcon#*before return 0, iclass 31, count 2 2006.257.08:55:39.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:39.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:39.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.08:55:39.08#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:39.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:39.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:39.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:39.20#ibcon#enter wrdev, iclass 31, count 0 2006.257.08:55:39.20#ibcon#first serial, iclass 31, count 0 2006.257.08:55:39.20#ibcon#enter sib2, iclass 31, count 0 2006.257.08:55:39.20#ibcon#flushed, iclass 31, count 0 2006.257.08:55:39.20#ibcon#about to write, iclass 31, count 0 2006.257.08:55:39.20#ibcon#wrote, iclass 31, count 0 2006.257.08:55:39.20#ibcon#about to read 3, iclass 31, count 0 2006.257.08:55:39.22#ibcon#read 3, iclass 31, count 0 2006.257.08:55:39.22#ibcon#about to read 4, iclass 31, count 0 2006.257.08:55:39.22#ibcon#read 4, iclass 31, count 0 2006.257.08:55:39.22#ibcon#about to read 5, iclass 31, count 0 2006.257.08:55:39.22#ibcon#read 5, iclass 31, count 0 2006.257.08:55:39.22#ibcon#about to read 6, iclass 31, count 0 2006.257.08:55:39.22#ibcon#read 6, iclass 31, count 0 2006.257.08:55:39.22#ibcon#end of sib2, iclass 31, count 0 2006.257.08:55:39.22#ibcon#*mode == 0, iclass 31, count 0 2006.257.08:55:39.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.08:55:39.22#ibcon#[25=USB\r\n] 2006.257.08:55:39.22#ibcon#*before write, iclass 31, count 0 2006.257.08:55:39.22#ibcon#enter sib2, iclass 31, count 0 2006.257.08:55:39.22#ibcon#flushed, iclass 31, count 0 2006.257.08:55:39.22#ibcon#about to write, iclass 31, count 0 2006.257.08:55:39.22#ibcon#wrote, iclass 31, count 0 2006.257.08:55:39.22#ibcon#about to read 3, iclass 31, count 0 2006.257.08:55:39.25#ibcon#read 3, iclass 31, count 0 2006.257.08:55:39.25#ibcon#about to read 4, iclass 31, count 0 2006.257.08:55:39.25#ibcon#read 4, iclass 31, count 0 2006.257.08:55:39.25#ibcon#about to read 5, iclass 31, count 0 2006.257.08:55:39.25#ibcon#read 5, iclass 31, count 0 2006.257.08:55:39.25#ibcon#about to read 6, iclass 31, count 0 2006.257.08:55:39.25#ibcon#read 6, iclass 31, count 0 2006.257.08:55:39.25#ibcon#end of sib2, iclass 31, count 0 2006.257.08:55:39.25#ibcon#*after write, iclass 31, count 0 2006.257.08:55:39.25#ibcon#*before return 0, iclass 31, count 0 2006.257.08:55:39.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:39.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:39.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.08:55:39.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.08:55:39.25$vck44/valo=7,864.99 2006.257.08:55:39.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.08:55:39.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.08:55:39.25#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:39.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:39.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:39.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:39.25#ibcon#enter wrdev, iclass 33, count 0 2006.257.08:55:39.25#ibcon#first serial, iclass 33, count 0 2006.257.08:55:39.25#ibcon#enter sib2, iclass 33, count 0 2006.257.08:55:39.25#ibcon#flushed, iclass 33, count 0 2006.257.08:55:39.25#ibcon#about to write, iclass 33, count 0 2006.257.08:55:39.25#ibcon#wrote, iclass 33, count 0 2006.257.08:55:39.25#ibcon#about to read 3, iclass 33, count 0 2006.257.08:55:39.27#ibcon#read 3, iclass 33, count 0 2006.257.08:55:39.27#ibcon#about to read 4, iclass 33, count 0 2006.257.08:55:39.27#ibcon#read 4, iclass 33, count 0 2006.257.08:55:39.27#ibcon#about to read 5, iclass 33, count 0 2006.257.08:55:39.27#ibcon#read 5, iclass 33, count 0 2006.257.08:55:39.27#ibcon#about to read 6, iclass 33, count 0 2006.257.08:55:39.27#ibcon#read 6, iclass 33, count 0 2006.257.08:55:39.27#ibcon#end of sib2, iclass 33, count 0 2006.257.08:55:39.27#ibcon#*mode == 0, iclass 33, count 0 2006.257.08:55:39.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.08:55:39.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.08:55:39.27#ibcon#*before write, iclass 33, count 0 2006.257.08:55:39.27#ibcon#enter sib2, iclass 33, count 0 2006.257.08:55:39.27#ibcon#flushed, iclass 33, count 0 2006.257.08:55:39.27#ibcon#about to write, iclass 33, count 0 2006.257.08:55:39.27#ibcon#wrote, iclass 33, count 0 2006.257.08:55:39.27#ibcon#about to read 3, iclass 33, count 0 2006.257.08:55:39.31#ibcon#read 3, iclass 33, count 0 2006.257.08:55:39.31#ibcon#about to read 4, iclass 33, count 0 2006.257.08:55:39.31#ibcon#read 4, iclass 33, count 0 2006.257.08:55:39.31#ibcon#about to read 5, iclass 33, count 0 2006.257.08:55:39.31#ibcon#read 5, iclass 33, count 0 2006.257.08:55:39.31#ibcon#about to read 6, iclass 33, count 0 2006.257.08:55:39.31#ibcon#read 6, iclass 33, count 0 2006.257.08:55:39.31#ibcon#end of sib2, iclass 33, count 0 2006.257.08:55:39.31#ibcon#*after write, iclass 33, count 0 2006.257.08:55:39.31#ibcon#*before return 0, iclass 33, count 0 2006.257.08:55:39.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:39.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:39.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.08:55:39.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.08:55:39.31$vck44/va=7,4 2006.257.08:55:39.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.08:55:39.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.08:55:39.31#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:39.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:39.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:39.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:39.37#ibcon#enter wrdev, iclass 35, count 2 2006.257.08:55:39.37#ibcon#first serial, iclass 35, count 2 2006.257.08:55:39.37#ibcon#enter sib2, iclass 35, count 2 2006.257.08:55:39.37#ibcon#flushed, iclass 35, count 2 2006.257.08:55:39.37#ibcon#about to write, iclass 35, count 2 2006.257.08:55:39.37#ibcon#wrote, iclass 35, count 2 2006.257.08:55:39.37#ibcon#about to read 3, iclass 35, count 2 2006.257.08:55:39.39#ibcon#read 3, iclass 35, count 2 2006.257.08:55:39.39#ibcon#about to read 4, iclass 35, count 2 2006.257.08:55:39.39#ibcon#read 4, iclass 35, count 2 2006.257.08:55:39.39#ibcon#about to read 5, iclass 35, count 2 2006.257.08:55:39.39#ibcon#read 5, iclass 35, count 2 2006.257.08:55:39.39#ibcon#about to read 6, iclass 35, count 2 2006.257.08:55:39.39#ibcon#read 6, iclass 35, count 2 2006.257.08:55:39.39#ibcon#end of sib2, iclass 35, count 2 2006.257.08:55:39.39#ibcon#*mode == 0, iclass 35, count 2 2006.257.08:55:39.39#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.08:55:39.39#ibcon#[25=AT07-04\r\n] 2006.257.08:55:39.39#ibcon#*before write, iclass 35, count 2 2006.257.08:55:39.39#ibcon#enter sib2, iclass 35, count 2 2006.257.08:55:39.39#ibcon#flushed, iclass 35, count 2 2006.257.08:55:39.39#ibcon#about to write, iclass 35, count 2 2006.257.08:55:39.39#ibcon#wrote, iclass 35, count 2 2006.257.08:55:39.39#ibcon#about to read 3, iclass 35, count 2 2006.257.08:55:39.42#ibcon#read 3, iclass 35, count 2 2006.257.08:55:39.42#ibcon#about to read 4, iclass 35, count 2 2006.257.08:55:39.42#ibcon#read 4, iclass 35, count 2 2006.257.08:55:39.42#ibcon#about to read 5, iclass 35, count 2 2006.257.08:55:39.42#ibcon#read 5, iclass 35, count 2 2006.257.08:55:39.42#ibcon#about to read 6, iclass 35, count 2 2006.257.08:55:39.42#ibcon#read 6, iclass 35, count 2 2006.257.08:55:39.42#ibcon#end of sib2, iclass 35, count 2 2006.257.08:55:39.42#ibcon#*after write, iclass 35, count 2 2006.257.08:55:39.42#ibcon#*before return 0, iclass 35, count 2 2006.257.08:55:39.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:39.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:39.42#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.08:55:39.42#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:39.42#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:39.54#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:39.54#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:39.54#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:55:39.54#ibcon#first serial, iclass 35, count 0 2006.257.08:55:39.54#ibcon#enter sib2, iclass 35, count 0 2006.257.08:55:39.54#ibcon#flushed, iclass 35, count 0 2006.257.08:55:39.54#ibcon#about to write, iclass 35, count 0 2006.257.08:55:39.54#ibcon#wrote, iclass 35, count 0 2006.257.08:55:39.54#ibcon#about to read 3, iclass 35, count 0 2006.257.08:55:39.56#ibcon#read 3, iclass 35, count 0 2006.257.08:55:39.56#ibcon#about to read 4, iclass 35, count 0 2006.257.08:55:39.56#ibcon#read 4, iclass 35, count 0 2006.257.08:55:39.56#ibcon#about to read 5, iclass 35, count 0 2006.257.08:55:39.56#ibcon#read 5, iclass 35, count 0 2006.257.08:55:39.56#ibcon#about to read 6, iclass 35, count 0 2006.257.08:55:39.56#ibcon#read 6, iclass 35, count 0 2006.257.08:55:39.56#ibcon#end of sib2, iclass 35, count 0 2006.257.08:55:39.56#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:55:39.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:55:39.56#ibcon#[25=USB\r\n] 2006.257.08:55:39.56#ibcon#*before write, iclass 35, count 0 2006.257.08:55:39.56#ibcon#enter sib2, iclass 35, count 0 2006.257.08:55:39.56#ibcon#flushed, iclass 35, count 0 2006.257.08:55:39.56#ibcon#about to write, iclass 35, count 0 2006.257.08:55:39.56#ibcon#wrote, iclass 35, count 0 2006.257.08:55:39.56#ibcon#about to read 3, iclass 35, count 0 2006.257.08:55:39.59#ibcon#read 3, iclass 35, count 0 2006.257.08:55:39.59#ibcon#about to read 4, iclass 35, count 0 2006.257.08:55:39.59#ibcon#read 4, iclass 35, count 0 2006.257.08:55:39.59#ibcon#about to read 5, iclass 35, count 0 2006.257.08:55:39.59#ibcon#read 5, iclass 35, count 0 2006.257.08:55:39.59#ibcon#about to read 6, iclass 35, count 0 2006.257.08:55:39.59#ibcon#read 6, iclass 35, count 0 2006.257.08:55:39.59#ibcon#end of sib2, iclass 35, count 0 2006.257.08:55:39.59#ibcon#*after write, iclass 35, count 0 2006.257.08:55:39.59#ibcon#*before return 0, iclass 35, count 0 2006.257.08:55:39.59#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:39.59#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:39.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:55:39.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:55:39.59$vck44/valo=8,884.99 2006.257.08:55:39.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.08:55:39.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.08:55:39.59#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:39.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:39.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:39.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:39.59#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:55:39.59#ibcon#first serial, iclass 37, count 0 2006.257.08:55:39.59#ibcon#enter sib2, iclass 37, count 0 2006.257.08:55:39.59#ibcon#flushed, iclass 37, count 0 2006.257.08:55:39.59#ibcon#about to write, iclass 37, count 0 2006.257.08:55:39.59#ibcon#wrote, iclass 37, count 0 2006.257.08:55:39.59#ibcon#about to read 3, iclass 37, count 0 2006.257.08:55:39.61#ibcon#read 3, iclass 37, count 0 2006.257.08:55:39.61#ibcon#about to read 4, iclass 37, count 0 2006.257.08:55:39.61#ibcon#read 4, iclass 37, count 0 2006.257.08:55:39.61#ibcon#about to read 5, iclass 37, count 0 2006.257.08:55:39.61#ibcon#read 5, iclass 37, count 0 2006.257.08:55:39.61#ibcon#about to read 6, iclass 37, count 0 2006.257.08:55:39.61#ibcon#read 6, iclass 37, count 0 2006.257.08:55:39.61#ibcon#end of sib2, iclass 37, count 0 2006.257.08:55:39.61#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:55:39.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:55:39.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.08:55:39.61#ibcon#*before write, iclass 37, count 0 2006.257.08:55:39.61#ibcon#enter sib2, iclass 37, count 0 2006.257.08:55:39.61#ibcon#flushed, iclass 37, count 0 2006.257.08:55:39.61#ibcon#about to write, iclass 37, count 0 2006.257.08:55:39.61#ibcon#wrote, iclass 37, count 0 2006.257.08:55:39.61#ibcon#about to read 3, iclass 37, count 0 2006.257.08:55:39.65#ibcon#read 3, iclass 37, count 0 2006.257.08:55:39.65#ibcon#about to read 4, iclass 37, count 0 2006.257.08:55:39.65#ibcon#read 4, iclass 37, count 0 2006.257.08:55:39.65#ibcon#about to read 5, iclass 37, count 0 2006.257.08:55:39.65#ibcon#read 5, iclass 37, count 0 2006.257.08:55:39.65#ibcon#about to read 6, iclass 37, count 0 2006.257.08:55:39.65#ibcon#read 6, iclass 37, count 0 2006.257.08:55:39.65#ibcon#end of sib2, iclass 37, count 0 2006.257.08:55:39.65#ibcon#*after write, iclass 37, count 0 2006.257.08:55:39.65#ibcon#*before return 0, iclass 37, count 0 2006.257.08:55:39.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:39.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:39.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:55:39.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:55:39.65$vck44/va=8,4 2006.257.08:55:39.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.08:55:39.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.08:55:39.65#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:39.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:55:39.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:55:39.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:55:39.71#ibcon#enter wrdev, iclass 39, count 2 2006.257.08:55:39.71#ibcon#first serial, iclass 39, count 2 2006.257.08:55:39.71#ibcon#enter sib2, iclass 39, count 2 2006.257.08:55:39.71#ibcon#flushed, iclass 39, count 2 2006.257.08:55:39.71#ibcon#about to write, iclass 39, count 2 2006.257.08:55:39.71#ibcon#wrote, iclass 39, count 2 2006.257.08:55:39.71#ibcon#about to read 3, iclass 39, count 2 2006.257.08:55:39.73#ibcon#read 3, iclass 39, count 2 2006.257.08:55:39.73#ibcon#about to read 4, iclass 39, count 2 2006.257.08:55:39.73#ibcon#read 4, iclass 39, count 2 2006.257.08:55:39.73#ibcon#about to read 5, iclass 39, count 2 2006.257.08:55:39.73#ibcon#read 5, iclass 39, count 2 2006.257.08:55:39.73#ibcon#about to read 6, iclass 39, count 2 2006.257.08:55:39.73#ibcon#read 6, iclass 39, count 2 2006.257.08:55:39.73#ibcon#end of sib2, iclass 39, count 2 2006.257.08:55:39.73#ibcon#*mode == 0, iclass 39, count 2 2006.257.08:55:39.73#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.08:55:39.73#ibcon#[25=AT08-04\r\n] 2006.257.08:55:39.73#ibcon#*before write, iclass 39, count 2 2006.257.08:55:39.73#ibcon#enter sib2, iclass 39, count 2 2006.257.08:55:39.73#ibcon#flushed, iclass 39, count 2 2006.257.08:55:39.73#ibcon#about to write, iclass 39, count 2 2006.257.08:55:39.73#ibcon#wrote, iclass 39, count 2 2006.257.08:55:39.73#ibcon#about to read 3, iclass 39, count 2 2006.257.08:55:39.76#ibcon#read 3, iclass 39, count 2 2006.257.08:55:39.76#ibcon#about to read 4, iclass 39, count 2 2006.257.08:55:39.76#ibcon#read 4, iclass 39, count 2 2006.257.08:55:39.76#ibcon#about to read 5, iclass 39, count 2 2006.257.08:55:39.76#ibcon#read 5, iclass 39, count 2 2006.257.08:55:39.76#ibcon#about to read 6, iclass 39, count 2 2006.257.08:55:39.76#ibcon#read 6, iclass 39, count 2 2006.257.08:55:39.76#ibcon#end of sib2, iclass 39, count 2 2006.257.08:55:39.76#ibcon#*after write, iclass 39, count 2 2006.257.08:55:39.76#ibcon#*before return 0, iclass 39, count 2 2006.257.08:55:39.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:55:39.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.08:55:39.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.08:55:39.76#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:39.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:55:39.88#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:55:39.88#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:55:39.88#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:55:39.88#ibcon#first serial, iclass 39, count 0 2006.257.08:55:39.88#ibcon#enter sib2, iclass 39, count 0 2006.257.08:55:39.88#ibcon#flushed, iclass 39, count 0 2006.257.08:55:39.88#ibcon#about to write, iclass 39, count 0 2006.257.08:55:39.88#ibcon#wrote, iclass 39, count 0 2006.257.08:55:39.88#ibcon#about to read 3, iclass 39, count 0 2006.257.08:55:39.90#ibcon#read 3, iclass 39, count 0 2006.257.08:55:39.90#ibcon#about to read 4, iclass 39, count 0 2006.257.08:55:39.90#ibcon#read 4, iclass 39, count 0 2006.257.08:55:39.90#ibcon#about to read 5, iclass 39, count 0 2006.257.08:55:39.90#ibcon#read 5, iclass 39, count 0 2006.257.08:55:39.90#ibcon#about to read 6, iclass 39, count 0 2006.257.08:55:39.90#ibcon#read 6, iclass 39, count 0 2006.257.08:55:39.90#ibcon#end of sib2, iclass 39, count 0 2006.257.08:55:39.90#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:55:39.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:55:39.90#ibcon#[25=USB\r\n] 2006.257.08:55:39.90#ibcon#*before write, iclass 39, count 0 2006.257.08:55:39.90#ibcon#enter sib2, iclass 39, count 0 2006.257.08:55:39.90#ibcon#flushed, iclass 39, count 0 2006.257.08:55:39.90#ibcon#about to write, iclass 39, count 0 2006.257.08:55:39.90#ibcon#wrote, iclass 39, count 0 2006.257.08:55:39.90#ibcon#about to read 3, iclass 39, count 0 2006.257.08:55:39.93#ibcon#read 3, iclass 39, count 0 2006.257.08:55:39.93#ibcon#about to read 4, iclass 39, count 0 2006.257.08:55:39.93#ibcon#read 4, iclass 39, count 0 2006.257.08:55:39.93#ibcon#about to read 5, iclass 39, count 0 2006.257.08:55:39.93#ibcon#read 5, iclass 39, count 0 2006.257.08:55:39.93#ibcon#about to read 6, iclass 39, count 0 2006.257.08:55:39.93#ibcon#read 6, iclass 39, count 0 2006.257.08:55:39.93#ibcon#end of sib2, iclass 39, count 0 2006.257.08:55:39.93#ibcon#*after write, iclass 39, count 0 2006.257.08:55:39.93#ibcon#*before return 0, iclass 39, count 0 2006.257.08:55:39.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:55:39.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.08:55:39.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:55:39.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:55:39.93$vck44/vblo=1,629.99 2006.257.08:55:39.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.08:55:39.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.08:55:39.93#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:39.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:55:39.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:55:39.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:55:39.93#ibcon#enter wrdev, iclass 3, count 0 2006.257.08:55:39.93#ibcon#first serial, iclass 3, count 0 2006.257.08:55:39.93#ibcon#enter sib2, iclass 3, count 0 2006.257.08:55:39.93#ibcon#flushed, iclass 3, count 0 2006.257.08:55:39.93#ibcon#about to write, iclass 3, count 0 2006.257.08:55:39.93#ibcon#wrote, iclass 3, count 0 2006.257.08:55:39.93#ibcon#about to read 3, iclass 3, count 0 2006.257.08:55:39.95#ibcon#read 3, iclass 3, count 0 2006.257.08:55:39.95#ibcon#about to read 4, iclass 3, count 0 2006.257.08:55:39.95#ibcon#read 4, iclass 3, count 0 2006.257.08:55:39.95#ibcon#about to read 5, iclass 3, count 0 2006.257.08:55:39.95#ibcon#read 5, iclass 3, count 0 2006.257.08:55:39.95#ibcon#about to read 6, iclass 3, count 0 2006.257.08:55:39.95#ibcon#read 6, iclass 3, count 0 2006.257.08:55:39.95#ibcon#end of sib2, iclass 3, count 0 2006.257.08:55:39.95#ibcon#*mode == 0, iclass 3, count 0 2006.257.08:55:39.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.08:55:39.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.08:55:39.95#ibcon#*before write, iclass 3, count 0 2006.257.08:55:39.95#ibcon#enter sib2, iclass 3, count 0 2006.257.08:55:39.95#ibcon#flushed, iclass 3, count 0 2006.257.08:55:39.95#ibcon#about to write, iclass 3, count 0 2006.257.08:55:39.95#ibcon#wrote, iclass 3, count 0 2006.257.08:55:39.95#ibcon#about to read 3, iclass 3, count 0 2006.257.08:55:39.99#ibcon#read 3, iclass 3, count 0 2006.257.08:55:39.99#ibcon#about to read 4, iclass 3, count 0 2006.257.08:55:39.99#ibcon#read 4, iclass 3, count 0 2006.257.08:55:39.99#ibcon#about to read 5, iclass 3, count 0 2006.257.08:55:39.99#ibcon#read 5, iclass 3, count 0 2006.257.08:55:39.99#ibcon#about to read 6, iclass 3, count 0 2006.257.08:55:39.99#ibcon#read 6, iclass 3, count 0 2006.257.08:55:39.99#ibcon#end of sib2, iclass 3, count 0 2006.257.08:55:39.99#ibcon#*after write, iclass 3, count 0 2006.257.08:55:39.99#ibcon#*before return 0, iclass 3, count 0 2006.257.08:55:39.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:55:39.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.08:55:39.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.08:55:39.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.08:55:39.99$vck44/vb=1,4 2006.257.08:55:39.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.08:55:39.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.08:55:39.99#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:39.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:55:39.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:55:39.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:55:39.99#ibcon#enter wrdev, iclass 5, count 2 2006.257.08:55:39.99#ibcon#first serial, iclass 5, count 2 2006.257.08:55:39.99#ibcon#enter sib2, iclass 5, count 2 2006.257.08:55:39.99#ibcon#flushed, iclass 5, count 2 2006.257.08:55:39.99#ibcon#about to write, iclass 5, count 2 2006.257.08:55:39.99#ibcon#wrote, iclass 5, count 2 2006.257.08:55:39.99#ibcon#about to read 3, iclass 5, count 2 2006.257.08:55:40.01#ibcon#read 3, iclass 5, count 2 2006.257.08:55:40.01#ibcon#about to read 4, iclass 5, count 2 2006.257.08:55:40.01#ibcon#read 4, iclass 5, count 2 2006.257.08:55:40.01#ibcon#about to read 5, iclass 5, count 2 2006.257.08:55:40.01#ibcon#read 5, iclass 5, count 2 2006.257.08:55:40.01#ibcon#about to read 6, iclass 5, count 2 2006.257.08:55:40.01#ibcon#read 6, iclass 5, count 2 2006.257.08:55:40.01#ibcon#end of sib2, iclass 5, count 2 2006.257.08:55:40.01#ibcon#*mode == 0, iclass 5, count 2 2006.257.08:55:40.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.08:55:40.01#ibcon#[27=AT01-04\r\n] 2006.257.08:55:40.01#ibcon#*before write, iclass 5, count 2 2006.257.08:55:40.01#ibcon#enter sib2, iclass 5, count 2 2006.257.08:55:40.01#ibcon#flushed, iclass 5, count 2 2006.257.08:55:40.01#ibcon#about to write, iclass 5, count 2 2006.257.08:55:40.01#ibcon#wrote, iclass 5, count 2 2006.257.08:55:40.01#ibcon#about to read 3, iclass 5, count 2 2006.257.08:55:40.04#ibcon#read 3, iclass 5, count 2 2006.257.08:55:40.04#ibcon#about to read 4, iclass 5, count 2 2006.257.08:55:40.04#ibcon#read 4, iclass 5, count 2 2006.257.08:55:40.04#ibcon#about to read 5, iclass 5, count 2 2006.257.08:55:40.04#ibcon#read 5, iclass 5, count 2 2006.257.08:55:40.04#ibcon#about to read 6, iclass 5, count 2 2006.257.08:55:40.04#ibcon#read 6, iclass 5, count 2 2006.257.08:55:40.04#ibcon#end of sib2, iclass 5, count 2 2006.257.08:55:40.04#ibcon#*after write, iclass 5, count 2 2006.257.08:55:40.04#ibcon#*before return 0, iclass 5, count 2 2006.257.08:55:40.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:55:40.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.08:55:40.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.08:55:40.04#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:40.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:55:40.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:55:40.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:55:40.16#ibcon#enter wrdev, iclass 5, count 0 2006.257.08:55:40.16#ibcon#first serial, iclass 5, count 0 2006.257.08:55:40.16#ibcon#enter sib2, iclass 5, count 0 2006.257.08:55:40.16#ibcon#flushed, iclass 5, count 0 2006.257.08:55:40.16#ibcon#about to write, iclass 5, count 0 2006.257.08:55:40.16#ibcon#wrote, iclass 5, count 0 2006.257.08:55:40.16#ibcon#about to read 3, iclass 5, count 0 2006.257.08:55:40.18#ibcon#read 3, iclass 5, count 0 2006.257.08:55:40.18#ibcon#about to read 4, iclass 5, count 0 2006.257.08:55:40.18#ibcon#read 4, iclass 5, count 0 2006.257.08:55:40.18#ibcon#about to read 5, iclass 5, count 0 2006.257.08:55:40.18#ibcon#read 5, iclass 5, count 0 2006.257.08:55:40.18#ibcon#about to read 6, iclass 5, count 0 2006.257.08:55:40.18#ibcon#read 6, iclass 5, count 0 2006.257.08:55:40.18#ibcon#end of sib2, iclass 5, count 0 2006.257.08:55:40.18#ibcon#*mode == 0, iclass 5, count 0 2006.257.08:55:40.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.08:55:40.18#ibcon#[27=USB\r\n] 2006.257.08:55:40.18#ibcon#*before write, iclass 5, count 0 2006.257.08:55:40.18#ibcon#enter sib2, iclass 5, count 0 2006.257.08:55:40.18#ibcon#flushed, iclass 5, count 0 2006.257.08:55:40.18#ibcon#about to write, iclass 5, count 0 2006.257.08:55:40.18#ibcon#wrote, iclass 5, count 0 2006.257.08:55:40.18#ibcon#about to read 3, iclass 5, count 0 2006.257.08:55:40.21#ibcon#read 3, iclass 5, count 0 2006.257.08:55:40.21#ibcon#about to read 4, iclass 5, count 0 2006.257.08:55:40.21#ibcon#read 4, iclass 5, count 0 2006.257.08:55:40.21#ibcon#about to read 5, iclass 5, count 0 2006.257.08:55:40.21#ibcon#read 5, iclass 5, count 0 2006.257.08:55:40.21#ibcon#about to read 6, iclass 5, count 0 2006.257.08:55:40.21#ibcon#read 6, iclass 5, count 0 2006.257.08:55:40.21#ibcon#end of sib2, iclass 5, count 0 2006.257.08:55:40.21#ibcon#*after write, iclass 5, count 0 2006.257.08:55:40.21#ibcon#*before return 0, iclass 5, count 0 2006.257.08:55:40.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:55:40.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.08:55:40.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.08:55:40.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.08:55:40.21$vck44/vblo=2,634.99 2006.257.08:55:40.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.08:55:40.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.08:55:40.21#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:40.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:40.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:40.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:40.21#ibcon#enter wrdev, iclass 7, count 0 2006.257.08:55:40.21#ibcon#first serial, iclass 7, count 0 2006.257.08:55:40.21#ibcon#enter sib2, iclass 7, count 0 2006.257.08:55:40.21#ibcon#flushed, iclass 7, count 0 2006.257.08:55:40.21#ibcon#about to write, iclass 7, count 0 2006.257.08:55:40.21#ibcon#wrote, iclass 7, count 0 2006.257.08:55:40.21#ibcon#about to read 3, iclass 7, count 0 2006.257.08:55:40.23#ibcon#read 3, iclass 7, count 0 2006.257.08:55:40.23#ibcon#about to read 4, iclass 7, count 0 2006.257.08:55:40.23#ibcon#read 4, iclass 7, count 0 2006.257.08:55:40.23#ibcon#about to read 5, iclass 7, count 0 2006.257.08:55:40.23#ibcon#read 5, iclass 7, count 0 2006.257.08:55:40.23#ibcon#about to read 6, iclass 7, count 0 2006.257.08:55:40.23#ibcon#read 6, iclass 7, count 0 2006.257.08:55:40.23#ibcon#end of sib2, iclass 7, count 0 2006.257.08:55:40.23#ibcon#*mode == 0, iclass 7, count 0 2006.257.08:55:40.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.08:55:40.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.08:55:40.23#ibcon#*before write, iclass 7, count 0 2006.257.08:55:40.23#ibcon#enter sib2, iclass 7, count 0 2006.257.08:55:40.23#ibcon#flushed, iclass 7, count 0 2006.257.08:55:40.23#ibcon#about to write, iclass 7, count 0 2006.257.08:55:40.23#ibcon#wrote, iclass 7, count 0 2006.257.08:55:40.23#ibcon#about to read 3, iclass 7, count 0 2006.257.08:55:40.27#ibcon#read 3, iclass 7, count 0 2006.257.08:55:40.27#ibcon#about to read 4, iclass 7, count 0 2006.257.08:55:40.27#ibcon#read 4, iclass 7, count 0 2006.257.08:55:40.27#ibcon#about to read 5, iclass 7, count 0 2006.257.08:55:40.27#ibcon#read 5, iclass 7, count 0 2006.257.08:55:40.27#ibcon#about to read 6, iclass 7, count 0 2006.257.08:55:40.27#ibcon#read 6, iclass 7, count 0 2006.257.08:55:40.27#ibcon#end of sib2, iclass 7, count 0 2006.257.08:55:40.27#ibcon#*after write, iclass 7, count 0 2006.257.08:55:40.27#ibcon#*before return 0, iclass 7, count 0 2006.257.08:55:40.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:40.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.08:55:40.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.08:55:40.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.08:55:40.27$vck44/vb=2,5 2006.257.08:55:40.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.08:55:40.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.08:55:40.27#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:40.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:40.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:40.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:40.33#ibcon#enter wrdev, iclass 11, count 2 2006.257.08:55:40.33#ibcon#first serial, iclass 11, count 2 2006.257.08:55:40.33#ibcon#enter sib2, iclass 11, count 2 2006.257.08:55:40.33#ibcon#flushed, iclass 11, count 2 2006.257.08:55:40.33#ibcon#about to write, iclass 11, count 2 2006.257.08:55:40.33#ibcon#wrote, iclass 11, count 2 2006.257.08:55:40.33#ibcon#about to read 3, iclass 11, count 2 2006.257.08:55:40.35#ibcon#read 3, iclass 11, count 2 2006.257.08:55:40.35#ibcon#about to read 4, iclass 11, count 2 2006.257.08:55:40.35#ibcon#read 4, iclass 11, count 2 2006.257.08:55:40.35#ibcon#about to read 5, iclass 11, count 2 2006.257.08:55:40.35#ibcon#read 5, iclass 11, count 2 2006.257.08:55:40.35#ibcon#about to read 6, iclass 11, count 2 2006.257.08:55:40.35#ibcon#read 6, iclass 11, count 2 2006.257.08:55:40.35#ibcon#end of sib2, iclass 11, count 2 2006.257.08:55:40.35#ibcon#*mode == 0, iclass 11, count 2 2006.257.08:55:40.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.08:55:40.35#ibcon#[27=AT02-05\r\n] 2006.257.08:55:40.35#ibcon#*before write, iclass 11, count 2 2006.257.08:55:40.35#ibcon#enter sib2, iclass 11, count 2 2006.257.08:55:40.35#ibcon#flushed, iclass 11, count 2 2006.257.08:55:40.35#ibcon#about to write, iclass 11, count 2 2006.257.08:55:40.35#ibcon#wrote, iclass 11, count 2 2006.257.08:55:40.35#ibcon#about to read 3, iclass 11, count 2 2006.257.08:55:40.38#ibcon#read 3, iclass 11, count 2 2006.257.08:55:40.38#ibcon#about to read 4, iclass 11, count 2 2006.257.08:55:40.38#ibcon#read 4, iclass 11, count 2 2006.257.08:55:40.38#ibcon#about to read 5, iclass 11, count 2 2006.257.08:55:40.38#ibcon#read 5, iclass 11, count 2 2006.257.08:55:40.38#ibcon#about to read 6, iclass 11, count 2 2006.257.08:55:40.38#ibcon#read 6, iclass 11, count 2 2006.257.08:55:40.38#ibcon#end of sib2, iclass 11, count 2 2006.257.08:55:40.38#ibcon#*after write, iclass 11, count 2 2006.257.08:55:40.38#ibcon#*before return 0, iclass 11, count 2 2006.257.08:55:40.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:40.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.08:55:40.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.08:55:40.38#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:40.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:40.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:40.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:40.50#ibcon#enter wrdev, iclass 11, count 0 2006.257.08:55:40.50#ibcon#first serial, iclass 11, count 0 2006.257.08:55:40.50#ibcon#enter sib2, iclass 11, count 0 2006.257.08:55:40.50#ibcon#flushed, iclass 11, count 0 2006.257.08:55:40.50#ibcon#about to write, iclass 11, count 0 2006.257.08:55:40.50#ibcon#wrote, iclass 11, count 0 2006.257.08:55:40.50#ibcon#about to read 3, iclass 11, count 0 2006.257.08:55:40.52#ibcon#read 3, iclass 11, count 0 2006.257.08:55:40.52#ibcon#about to read 4, iclass 11, count 0 2006.257.08:55:40.52#ibcon#read 4, iclass 11, count 0 2006.257.08:55:40.52#ibcon#about to read 5, iclass 11, count 0 2006.257.08:55:40.52#ibcon#read 5, iclass 11, count 0 2006.257.08:55:40.52#ibcon#about to read 6, iclass 11, count 0 2006.257.08:55:40.52#ibcon#read 6, iclass 11, count 0 2006.257.08:55:40.52#ibcon#end of sib2, iclass 11, count 0 2006.257.08:55:40.52#ibcon#*mode == 0, iclass 11, count 0 2006.257.08:55:40.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.08:55:40.52#ibcon#[27=USB\r\n] 2006.257.08:55:40.52#ibcon#*before write, iclass 11, count 0 2006.257.08:55:40.52#ibcon#enter sib2, iclass 11, count 0 2006.257.08:55:40.52#ibcon#flushed, iclass 11, count 0 2006.257.08:55:40.52#ibcon#about to write, iclass 11, count 0 2006.257.08:55:40.52#ibcon#wrote, iclass 11, count 0 2006.257.08:55:40.52#ibcon#about to read 3, iclass 11, count 0 2006.257.08:55:40.55#ibcon#read 3, iclass 11, count 0 2006.257.08:55:40.55#ibcon#about to read 4, iclass 11, count 0 2006.257.08:55:40.55#ibcon#read 4, iclass 11, count 0 2006.257.08:55:40.55#ibcon#about to read 5, iclass 11, count 0 2006.257.08:55:40.55#ibcon#read 5, iclass 11, count 0 2006.257.08:55:40.55#ibcon#about to read 6, iclass 11, count 0 2006.257.08:55:40.55#ibcon#read 6, iclass 11, count 0 2006.257.08:55:40.55#ibcon#end of sib2, iclass 11, count 0 2006.257.08:55:40.55#ibcon#*after write, iclass 11, count 0 2006.257.08:55:40.55#ibcon#*before return 0, iclass 11, count 0 2006.257.08:55:40.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:40.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.08:55:40.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.08:55:40.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.08:55:40.55$vck44/vblo=3,649.99 2006.257.08:55:40.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.08:55:40.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.08:55:40.55#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:40.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:40.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:40.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:40.55#ibcon#enter wrdev, iclass 13, count 0 2006.257.08:55:40.55#ibcon#first serial, iclass 13, count 0 2006.257.08:55:40.55#ibcon#enter sib2, iclass 13, count 0 2006.257.08:55:40.55#ibcon#flushed, iclass 13, count 0 2006.257.08:55:40.55#ibcon#about to write, iclass 13, count 0 2006.257.08:55:40.55#ibcon#wrote, iclass 13, count 0 2006.257.08:55:40.55#ibcon#about to read 3, iclass 13, count 0 2006.257.08:55:40.57#ibcon#read 3, iclass 13, count 0 2006.257.08:55:40.57#ibcon#about to read 4, iclass 13, count 0 2006.257.08:55:40.57#ibcon#read 4, iclass 13, count 0 2006.257.08:55:40.57#ibcon#about to read 5, iclass 13, count 0 2006.257.08:55:40.57#ibcon#read 5, iclass 13, count 0 2006.257.08:55:40.57#ibcon#about to read 6, iclass 13, count 0 2006.257.08:55:40.57#ibcon#read 6, iclass 13, count 0 2006.257.08:55:40.57#ibcon#end of sib2, iclass 13, count 0 2006.257.08:55:40.57#ibcon#*mode == 0, iclass 13, count 0 2006.257.08:55:40.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.08:55:40.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.08:55:40.57#ibcon#*before write, iclass 13, count 0 2006.257.08:55:40.57#ibcon#enter sib2, iclass 13, count 0 2006.257.08:55:40.57#ibcon#flushed, iclass 13, count 0 2006.257.08:55:40.57#ibcon#about to write, iclass 13, count 0 2006.257.08:55:40.57#ibcon#wrote, iclass 13, count 0 2006.257.08:55:40.57#ibcon#about to read 3, iclass 13, count 0 2006.257.08:55:40.61#ibcon#read 3, iclass 13, count 0 2006.257.08:55:40.61#ibcon#about to read 4, iclass 13, count 0 2006.257.08:55:40.61#ibcon#read 4, iclass 13, count 0 2006.257.08:55:40.61#ibcon#about to read 5, iclass 13, count 0 2006.257.08:55:40.61#ibcon#read 5, iclass 13, count 0 2006.257.08:55:40.61#ibcon#about to read 6, iclass 13, count 0 2006.257.08:55:40.61#ibcon#read 6, iclass 13, count 0 2006.257.08:55:40.61#ibcon#end of sib2, iclass 13, count 0 2006.257.08:55:40.61#ibcon#*after write, iclass 13, count 0 2006.257.08:55:40.61#ibcon#*before return 0, iclass 13, count 0 2006.257.08:55:40.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:40.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.08:55:40.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.08:55:40.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.08:55:40.61$vck44/vb=3,4 2006.257.08:55:40.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.08:55:40.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.08:55:40.61#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:40.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:40.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:40.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:40.67#ibcon#enter wrdev, iclass 15, count 2 2006.257.08:55:40.67#ibcon#first serial, iclass 15, count 2 2006.257.08:55:40.67#ibcon#enter sib2, iclass 15, count 2 2006.257.08:55:40.67#ibcon#flushed, iclass 15, count 2 2006.257.08:55:40.67#ibcon#about to write, iclass 15, count 2 2006.257.08:55:40.67#ibcon#wrote, iclass 15, count 2 2006.257.08:55:40.67#ibcon#about to read 3, iclass 15, count 2 2006.257.08:55:40.69#ibcon#read 3, iclass 15, count 2 2006.257.08:55:40.69#ibcon#about to read 4, iclass 15, count 2 2006.257.08:55:40.69#ibcon#read 4, iclass 15, count 2 2006.257.08:55:40.69#ibcon#about to read 5, iclass 15, count 2 2006.257.08:55:40.69#ibcon#read 5, iclass 15, count 2 2006.257.08:55:40.69#ibcon#about to read 6, iclass 15, count 2 2006.257.08:55:40.69#ibcon#read 6, iclass 15, count 2 2006.257.08:55:40.69#ibcon#end of sib2, iclass 15, count 2 2006.257.08:55:40.69#ibcon#*mode == 0, iclass 15, count 2 2006.257.08:55:40.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.08:55:40.69#ibcon#[27=AT03-04\r\n] 2006.257.08:55:40.69#ibcon#*before write, iclass 15, count 2 2006.257.08:55:40.69#ibcon#enter sib2, iclass 15, count 2 2006.257.08:55:40.69#ibcon#flushed, iclass 15, count 2 2006.257.08:55:40.69#ibcon#about to write, iclass 15, count 2 2006.257.08:55:40.69#ibcon#wrote, iclass 15, count 2 2006.257.08:55:40.69#ibcon#about to read 3, iclass 15, count 2 2006.257.08:55:40.72#ibcon#read 3, iclass 15, count 2 2006.257.08:55:40.72#ibcon#about to read 4, iclass 15, count 2 2006.257.08:55:40.72#ibcon#read 4, iclass 15, count 2 2006.257.08:55:40.72#ibcon#about to read 5, iclass 15, count 2 2006.257.08:55:40.72#ibcon#read 5, iclass 15, count 2 2006.257.08:55:40.72#ibcon#about to read 6, iclass 15, count 2 2006.257.08:55:40.72#ibcon#read 6, iclass 15, count 2 2006.257.08:55:40.72#ibcon#end of sib2, iclass 15, count 2 2006.257.08:55:40.72#ibcon#*after write, iclass 15, count 2 2006.257.08:55:40.72#ibcon#*before return 0, iclass 15, count 2 2006.257.08:55:40.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:40.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.08:55:40.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.08:55:40.72#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:40.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:40.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:40.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:40.84#ibcon#enter wrdev, iclass 15, count 0 2006.257.08:55:40.84#ibcon#first serial, iclass 15, count 0 2006.257.08:55:40.84#ibcon#enter sib2, iclass 15, count 0 2006.257.08:55:40.84#ibcon#flushed, iclass 15, count 0 2006.257.08:55:40.84#ibcon#about to write, iclass 15, count 0 2006.257.08:55:40.84#ibcon#wrote, iclass 15, count 0 2006.257.08:55:40.84#ibcon#about to read 3, iclass 15, count 0 2006.257.08:55:40.86#ibcon#read 3, iclass 15, count 0 2006.257.08:55:40.86#ibcon#about to read 4, iclass 15, count 0 2006.257.08:55:40.86#ibcon#read 4, iclass 15, count 0 2006.257.08:55:40.86#ibcon#about to read 5, iclass 15, count 0 2006.257.08:55:40.86#ibcon#read 5, iclass 15, count 0 2006.257.08:55:40.86#ibcon#about to read 6, iclass 15, count 0 2006.257.08:55:40.86#ibcon#read 6, iclass 15, count 0 2006.257.08:55:40.86#ibcon#end of sib2, iclass 15, count 0 2006.257.08:55:40.86#ibcon#*mode == 0, iclass 15, count 0 2006.257.08:55:40.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.08:55:40.86#ibcon#[27=USB\r\n] 2006.257.08:55:40.86#ibcon#*before write, iclass 15, count 0 2006.257.08:55:40.86#ibcon#enter sib2, iclass 15, count 0 2006.257.08:55:40.86#ibcon#flushed, iclass 15, count 0 2006.257.08:55:40.86#ibcon#about to write, iclass 15, count 0 2006.257.08:55:40.86#ibcon#wrote, iclass 15, count 0 2006.257.08:55:40.86#ibcon#about to read 3, iclass 15, count 0 2006.257.08:55:40.89#ibcon#read 3, iclass 15, count 0 2006.257.08:55:40.89#ibcon#about to read 4, iclass 15, count 0 2006.257.08:55:40.89#ibcon#read 4, iclass 15, count 0 2006.257.08:55:40.89#ibcon#about to read 5, iclass 15, count 0 2006.257.08:55:40.89#ibcon#read 5, iclass 15, count 0 2006.257.08:55:40.89#ibcon#about to read 6, iclass 15, count 0 2006.257.08:55:40.89#ibcon#read 6, iclass 15, count 0 2006.257.08:55:40.89#ibcon#end of sib2, iclass 15, count 0 2006.257.08:55:40.89#ibcon#*after write, iclass 15, count 0 2006.257.08:55:40.89#ibcon#*before return 0, iclass 15, count 0 2006.257.08:55:40.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:40.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.08:55:40.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.08:55:40.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.08:55:40.89$vck44/vblo=4,679.99 2006.257.08:55:40.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.08:55:40.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.08:55:40.89#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:40.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:40.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:40.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:40.89#ibcon#enter wrdev, iclass 17, count 0 2006.257.08:55:40.89#ibcon#first serial, iclass 17, count 0 2006.257.08:55:40.89#ibcon#enter sib2, iclass 17, count 0 2006.257.08:55:40.89#ibcon#flushed, iclass 17, count 0 2006.257.08:55:40.89#ibcon#about to write, iclass 17, count 0 2006.257.08:55:40.89#ibcon#wrote, iclass 17, count 0 2006.257.08:55:40.89#ibcon#about to read 3, iclass 17, count 0 2006.257.08:55:40.91#ibcon#read 3, iclass 17, count 0 2006.257.08:55:40.91#ibcon#about to read 4, iclass 17, count 0 2006.257.08:55:40.91#ibcon#read 4, iclass 17, count 0 2006.257.08:55:40.91#ibcon#about to read 5, iclass 17, count 0 2006.257.08:55:40.91#ibcon#read 5, iclass 17, count 0 2006.257.08:55:40.91#ibcon#about to read 6, iclass 17, count 0 2006.257.08:55:40.91#ibcon#read 6, iclass 17, count 0 2006.257.08:55:40.91#ibcon#end of sib2, iclass 17, count 0 2006.257.08:55:40.91#ibcon#*mode == 0, iclass 17, count 0 2006.257.08:55:40.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.08:55:40.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.08:55:40.91#ibcon#*before write, iclass 17, count 0 2006.257.08:55:40.91#ibcon#enter sib2, iclass 17, count 0 2006.257.08:55:40.91#ibcon#flushed, iclass 17, count 0 2006.257.08:55:40.91#ibcon#about to write, iclass 17, count 0 2006.257.08:55:40.91#ibcon#wrote, iclass 17, count 0 2006.257.08:55:40.91#ibcon#about to read 3, iclass 17, count 0 2006.257.08:55:40.95#ibcon#read 3, iclass 17, count 0 2006.257.08:55:40.95#ibcon#about to read 4, iclass 17, count 0 2006.257.08:55:40.95#ibcon#read 4, iclass 17, count 0 2006.257.08:55:40.95#ibcon#about to read 5, iclass 17, count 0 2006.257.08:55:40.95#ibcon#read 5, iclass 17, count 0 2006.257.08:55:40.95#ibcon#about to read 6, iclass 17, count 0 2006.257.08:55:40.95#ibcon#read 6, iclass 17, count 0 2006.257.08:55:40.95#ibcon#end of sib2, iclass 17, count 0 2006.257.08:55:40.95#ibcon#*after write, iclass 17, count 0 2006.257.08:55:40.95#ibcon#*before return 0, iclass 17, count 0 2006.257.08:55:40.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:40.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.08:55:40.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.08:55:40.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.08:55:40.95$vck44/vb=4,5 2006.257.08:55:40.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.08:55:40.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.08:55:40.95#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:40.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:41.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:41.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:41.01#ibcon#enter wrdev, iclass 19, count 2 2006.257.08:55:41.01#ibcon#first serial, iclass 19, count 2 2006.257.08:55:41.01#ibcon#enter sib2, iclass 19, count 2 2006.257.08:55:41.01#ibcon#flushed, iclass 19, count 2 2006.257.08:55:41.01#ibcon#about to write, iclass 19, count 2 2006.257.08:55:41.01#ibcon#wrote, iclass 19, count 2 2006.257.08:55:41.01#ibcon#about to read 3, iclass 19, count 2 2006.257.08:55:41.03#ibcon#read 3, iclass 19, count 2 2006.257.08:55:41.03#ibcon#about to read 4, iclass 19, count 2 2006.257.08:55:41.03#ibcon#read 4, iclass 19, count 2 2006.257.08:55:41.03#ibcon#about to read 5, iclass 19, count 2 2006.257.08:55:41.03#ibcon#read 5, iclass 19, count 2 2006.257.08:55:41.03#ibcon#about to read 6, iclass 19, count 2 2006.257.08:55:41.03#ibcon#read 6, iclass 19, count 2 2006.257.08:55:41.03#ibcon#end of sib2, iclass 19, count 2 2006.257.08:55:41.03#ibcon#*mode == 0, iclass 19, count 2 2006.257.08:55:41.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.08:55:41.03#ibcon#[27=AT04-05\r\n] 2006.257.08:55:41.03#ibcon#*before write, iclass 19, count 2 2006.257.08:55:41.03#ibcon#enter sib2, iclass 19, count 2 2006.257.08:55:41.03#ibcon#flushed, iclass 19, count 2 2006.257.08:55:41.03#ibcon#about to write, iclass 19, count 2 2006.257.08:55:41.03#ibcon#wrote, iclass 19, count 2 2006.257.08:55:41.03#ibcon#about to read 3, iclass 19, count 2 2006.257.08:55:41.06#ibcon#read 3, iclass 19, count 2 2006.257.08:55:41.06#ibcon#about to read 4, iclass 19, count 2 2006.257.08:55:41.06#ibcon#read 4, iclass 19, count 2 2006.257.08:55:41.06#ibcon#about to read 5, iclass 19, count 2 2006.257.08:55:41.06#ibcon#read 5, iclass 19, count 2 2006.257.08:55:41.06#ibcon#about to read 6, iclass 19, count 2 2006.257.08:55:41.06#ibcon#read 6, iclass 19, count 2 2006.257.08:55:41.06#ibcon#end of sib2, iclass 19, count 2 2006.257.08:55:41.06#ibcon#*after write, iclass 19, count 2 2006.257.08:55:41.06#ibcon#*before return 0, iclass 19, count 2 2006.257.08:55:41.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:41.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.08:55:41.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.08:55:41.06#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:41.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:41.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:41.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:41.18#ibcon#enter wrdev, iclass 19, count 0 2006.257.08:55:41.18#ibcon#first serial, iclass 19, count 0 2006.257.08:55:41.18#ibcon#enter sib2, iclass 19, count 0 2006.257.08:55:41.18#ibcon#flushed, iclass 19, count 0 2006.257.08:55:41.18#ibcon#about to write, iclass 19, count 0 2006.257.08:55:41.18#ibcon#wrote, iclass 19, count 0 2006.257.08:55:41.18#ibcon#about to read 3, iclass 19, count 0 2006.257.08:55:41.20#ibcon#read 3, iclass 19, count 0 2006.257.08:55:41.20#ibcon#about to read 4, iclass 19, count 0 2006.257.08:55:41.20#ibcon#read 4, iclass 19, count 0 2006.257.08:55:41.20#ibcon#about to read 5, iclass 19, count 0 2006.257.08:55:41.20#ibcon#read 5, iclass 19, count 0 2006.257.08:55:41.20#ibcon#about to read 6, iclass 19, count 0 2006.257.08:55:41.20#ibcon#read 6, iclass 19, count 0 2006.257.08:55:41.20#ibcon#end of sib2, iclass 19, count 0 2006.257.08:55:41.20#ibcon#*mode == 0, iclass 19, count 0 2006.257.08:55:41.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.08:55:41.20#ibcon#[27=USB\r\n] 2006.257.08:55:41.20#ibcon#*before write, iclass 19, count 0 2006.257.08:55:41.20#ibcon#enter sib2, iclass 19, count 0 2006.257.08:55:41.20#ibcon#flushed, iclass 19, count 0 2006.257.08:55:41.20#ibcon#about to write, iclass 19, count 0 2006.257.08:55:41.20#ibcon#wrote, iclass 19, count 0 2006.257.08:55:41.20#ibcon#about to read 3, iclass 19, count 0 2006.257.08:55:41.23#ibcon#read 3, iclass 19, count 0 2006.257.08:55:41.23#ibcon#about to read 4, iclass 19, count 0 2006.257.08:55:41.23#ibcon#read 4, iclass 19, count 0 2006.257.08:55:41.23#ibcon#about to read 5, iclass 19, count 0 2006.257.08:55:41.23#ibcon#read 5, iclass 19, count 0 2006.257.08:55:41.23#ibcon#about to read 6, iclass 19, count 0 2006.257.08:55:41.23#ibcon#read 6, iclass 19, count 0 2006.257.08:55:41.23#ibcon#end of sib2, iclass 19, count 0 2006.257.08:55:41.23#ibcon#*after write, iclass 19, count 0 2006.257.08:55:41.23#ibcon#*before return 0, iclass 19, count 0 2006.257.08:55:41.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:41.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.08:55:41.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.08:55:41.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.08:55:41.23$vck44/vblo=5,709.99 2006.257.08:55:41.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.08:55:41.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.08:55:41.23#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:41.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:41.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:41.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:41.23#ibcon#enter wrdev, iclass 21, count 0 2006.257.08:55:41.23#ibcon#first serial, iclass 21, count 0 2006.257.08:55:41.23#ibcon#enter sib2, iclass 21, count 0 2006.257.08:55:41.23#ibcon#flushed, iclass 21, count 0 2006.257.08:55:41.23#ibcon#about to write, iclass 21, count 0 2006.257.08:55:41.23#ibcon#wrote, iclass 21, count 0 2006.257.08:55:41.23#ibcon#about to read 3, iclass 21, count 0 2006.257.08:55:41.25#ibcon#read 3, iclass 21, count 0 2006.257.08:55:41.25#ibcon#about to read 4, iclass 21, count 0 2006.257.08:55:41.25#ibcon#read 4, iclass 21, count 0 2006.257.08:55:41.25#ibcon#about to read 5, iclass 21, count 0 2006.257.08:55:41.25#ibcon#read 5, iclass 21, count 0 2006.257.08:55:41.25#ibcon#about to read 6, iclass 21, count 0 2006.257.08:55:41.25#ibcon#read 6, iclass 21, count 0 2006.257.08:55:41.25#ibcon#end of sib2, iclass 21, count 0 2006.257.08:55:41.25#ibcon#*mode == 0, iclass 21, count 0 2006.257.08:55:41.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.08:55:41.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.08:55:41.25#ibcon#*before write, iclass 21, count 0 2006.257.08:55:41.25#ibcon#enter sib2, iclass 21, count 0 2006.257.08:55:41.25#ibcon#flushed, iclass 21, count 0 2006.257.08:55:41.25#ibcon#about to write, iclass 21, count 0 2006.257.08:55:41.25#ibcon#wrote, iclass 21, count 0 2006.257.08:55:41.25#ibcon#about to read 3, iclass 21, count 0 2006.257.08:55:41.29#ibcon#read 3, iclass 21, count 0 2006.257.08:55:41.29#ibcon#about to read 4, iclass 21, count 0 2006.257.08:55:41.29#ibcon#read 4, iclass 21, count 0 2006.257.08:55:41.29#ibcon#about to read 5, iclass 21, count 0 2006.257.08:55:41.29#ibcon#read 5, iclass 21, count 0 2006.257.08:55:41.29#ibcon#about to read 6, iclass 21, count 0 2006.257.08:55:41.29#ibcon#read 6, iclass 21, count 0 2006.257.08:55:41.29#ibcon#end of sib2, iclass 21, count 0 2006.257.08:55:41.29#ibcon#*after write, iclass 21, count 0 2006.257.08:55:41.29#ibcon#*before return 0, iclass 21, count 0 2006.257.08:55:41.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:41.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.08:55:41.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.08:55:41.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.08:55:41.29$vck44/vb=5,4 2006.257.08:55:41.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.08:55:41.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.08:55:41.29#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:41.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:41.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:41.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:41.35#ibcon#enter wrdev, iclass 23, count 2 2006.257.08:55:41.35#ibcon#first serial, iclass 23, count 2 2006.257.08:55:41.35#ibcon#enter sib2, iclass 23, count 2 2006.257.08:55:41.35#ibcon#flushed, iclass 23, count 2 2006.257.08:55:41.35#ibcon#about to write, iclass 23, count 2 2006.257.08:55:41.35#ibcon#wrote, iclass 23, count 2 2006.257.08:55:41.35#ibcon#about to read 3, iclass 23, count 2 2006.257.08:55:41.37#ibcon#read 3, iclass 23, count 2 2006.257.08:55:41.37#ibcon#about to read 4, iclass 23, count 2 2006.257.08:55:41.37#ibcon#read 4, iclass 23, count 2 2006.257.08:55:41.37#ibcon#about to read 5, iclass 23, count 2 2006.257.08:55:41.37#ibcon#read 5, iclass 23, count 2 2006.257.08:55:41.37#ibcon#about to read 6, iclass 23, count 2 2006.257.08:55:41.37#ibcon#read 6, iclass 23, count 2 2006.257.08:55:41.37#ibcon#end of sib2, iclass 23, count 2 2006.257.08:55:41.37#ibcon#*mode == 0, iclass 23, count 2 2006.257.08:55:41.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.08:55:41.37#ibcon#[27=AT05-04\r\n] 2006.257.08:55:41.37#ibcon#*before write, iclass 23, count 2 2006.257.08:55:41.37#ibcon#enter sib2, iclass 23, count 2 2006.257.08:55:41.37#ibcon#flushed, iclass 23, count 2 2006.257.08:55:41.37#ibcon#about to write, iclass 23, count 2 2006.257.08:55:41.37#ibcon#wrote, iclass 23, count 2 2006.257.08:55:41.37#ibcon#about to read 3, iclass 23, count 2 2006.257.08:55:41.40#ibcon#read 3, iclass 23, count 2 2006.257.08:55:41.40#ibcon#about to read 4, iclass 23, count 2 2006.257.08:55:41.40#ibcon#read 4, iclass 23, count 2 2006.257.08:55:41.40#ibcon#about to read 5, iclass 23, count 2 2006.257.08:55:41.40#ibcon#read 5, iclass 23, count 2 2006.257.08:55:41.40#ibcon#about to read 6, iclass 23, count 2 2006.257.08:55:41.40#ibcon#read 6, iclass 23, count 2 2006.257.08:55:41.40#ibcon#end of sib2, iclass 23, count 2 2006.257.08:55:41.40#ibcon#*after write, iclass 23, count 2 2006.257.08:55:41.40#ibcon#*before return 0, iclass 23, count 2 2006.257.08:55:41.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:41.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.08:55:41.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.08:55:41.40#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:41.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:41.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:41.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:41.52#ibcon#enter wrdev, iclass 23, count 0 2006.257.08:55:41.52#ibcon#first serial, iclass 23, count 0 2006.257.08:55:41.52#ibcon#enter sib2, iclass 23, count 0 2006.257.08:55:41.52#ibcon#flushed, iclass 23, count 0 2006.257.08:55:41.52#ibcon#about to write, iclass 23, count 0 2006.257.08:55:41.52#ibcon#wrote, iclass 23, count 0 2006.257.08:55:41.52#ibcon#about to read 3, iclass 23, count 0 2006.257.08:55:41.54#ibcon#read 3, iclass 23, count 0 2006.257.08:55:41.54#ibcon#about to read 4, iclass 23, count 0 2006.257.08:55:41.54#ibcon#read 4, iclass 23, count 0 2006.257.08:55:41.54#ibcon#about to read 5, iclass 23, count 0 2006.257.08:55:41.54#ibcon#read 5, iclass 23, count 0 2006.257.08:55:41.54#ibcon#about to read 6, iclass 23, count 0 2006.257.08:55:41.54#ibcon#read 6, iclass 23, count 0 2006.257.08:55:41.54#ibcon#end of sib2, iclass 23, count 0 2006.257.08:55:41.54#ibcon#*mode == 0, iclass 23, count 0 2006.257.08:55:41.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.08:55:41.54#ibcon#[27=USB\r\n] 2006.257.08:55:41.54#ibcon#*before write, iclass 23, count 0 2006.257.08:55:41.54#ibcon#enter sib2, iclass 23, count 0 2006.257.08:55:41.54#ibcon#flushed, iclass 23, count 0 2006.257.08:55:41.54#ibcon#about to write, iclass 23, count 0 2006.257.08:55:41.54#ibcon#wrote, iclass 23, count 0 2006.257.08:55:41.54#ibcon#about to read 3, iclass 23, count 0 2006.257.08:55:41.57#ibcon#read 3, iclass 23, count 0 2006.257.08:55:41.57#ibcon#about to read 4, iclass 23, count 0 2006.257.08:55:41.57#ibcon#read 4, iclass 23, count 0 2006.257.08:55:41.57#ibcon#about to read 5, iclass 23, count 0 2006.257.08:55:41.57#ibcon#read 5, iclass 23, count 0 2006.257.08:55:41.57#ibcon#about to read 6, iclass 23, count 0 2006.257.08:55:41.57#ibcon#read 6, iclass 23, count 0 2006.257.08:55:41.57#ibcon#end of sib2, iclass 23, count 0 2006.257.08:55:41.57#ibcon#*after write, iclass 23, count 0 2006.257.08:55:41.57#ibcon#*before return 0, iclass 23, count 0 2006.257.08:55:41.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:41.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.08:55:41.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.08:55:41.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.08:55:41.57$vck44/vblo=6,719.99 2006.257.08:55:41.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.08:55:41.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.08:55:41.57#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:41.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:41.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:41.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:41.57#ibcon#enter wrdev, iclass 25, count 0 2006.257.08:55:41.57#ibcon#first serial, iclass 25, count 0 2006.257.08:55:41.57#ibcon#enter sib2, iclass 25, count 0 2006.257.08:55:41.57#ibcon#flushed, iclass 25, count 0 2006.257.08:55:41.57#ibcon#about to write, iclass 25, count 0 2006.257.08:55:41.57#ibcon#wrote, iclass 25, count 0 2006.257.08:55:41.57#ibcon#about to read 3, iclass 25, count 0 2006.257.08:55:41.59#ibcon#read 3, iclass 25, count 0 2006.257.08:55:41.59#ibcon#about to read 4, iclass 25, count 0 2006.257.08:55:41.59#ibcon#read 4, iclass 25, count 0 2006.257.08:55:41.59#ibcon#about to read 5, iclass 25, count 0 2006.257.08:55:41.59#ibcon#read 5, iclass 25, count 0 2006.257.08:55:41.59#ibcon#about to read 6, iclass 25, count 0 2006.257.08:55:41.59#ibcon#read 6, iclass 25, count 0 2006.257.08:55:41.59#ibcon#end of sib2, iclass 25, count 0 2006.257.08:55:41.59#ibcon#*mode == 0, iclass 25, count 0 2006.257.08:55:41.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.08:55:41.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.08:55:41.59#ibcon#*before write, iclass 25, count 0 2006.257.08:55:41.59#ibcon#enter sib2, iclass 25, count 0 2006.257.08:55:41.59#ibcon#flushed, iclass 25, count 0 2006.257.08:55:41.59#ibcon#about to write, iclass 25, count 0 2006.257.08:55:41.59#ibcon#wrote, iclass 25, count 0 2006.257.08:55:41.59#ibcon#about to read 3, iclass 25, count 0 2006.257.08:55:41.63#ibcon#read 3, iclass 25, count 0 2006.257.08:55:41.63#ibcon#about to read 4, iclass 25, count 0 2006.257.08:55:41.63#ibcon#read 4, iclass 25, count 0 2006.257.08:55:41.63#ibcon#about to read 5, iclass 25, count 0 2006.257.08:55:41.63#ibcon#read 5, iclass 25, count 0 2006.257.08:55:41.63#ibcon#about to read 6, iclass 25, count 0 2006.257.08:55:41.63#ibcon#read 6, iclass 25, count 0 2006.257.08:55:41.63#ibcon#end of sib2, iclass 25, count 0 2006.257.08:55:41.63#ibcon#*after write, iclass 25, count 0 2006.257.08:55:41.63#ibcon#*before return 0, iclass 25, count 0 2006.257.08:55:41.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:41.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.08:55:41.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.08:55:41.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.08:55:41.63$vck44/vb=6,4 2006.257.08:55:41.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.08:55:41.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.08:55:41.63#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:41.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:41.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:41.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:41.69#ibcon#enter wrdev, iclass 27, count 2 2006.257.08:55:41.69#ibcon#first serial, iclass 27, count 2 2006.257.08:55:41.69#ibcon#enter sib2, iclass 27, count 2 2006.257.08:55:41.69#ibcon#flushed, iclass 27, count 2 2006.257.08:55:41.69#ibcon#about to write, iclass 27, count 2 2006.257.08:55:41.69#ibcon#wrote, iclass 27, count 2 2006.257.08:55:41.69#ibcon#about to read 3, iclass 27, count 2 2006.257.08:55:41.71#ibcon#read 3, iclass 27, count 2 2006.257.08:55:41.71#ibcon#about to read 4, iclass 27, count 2 2006.257.08:55:41.71#ibcon#read 4, iclass 27, count 2 2006.257.08:55:41.71#ibcon#about to read 5, iclass 27, count 2 2006.257.08:55:41.71#ibcon#read 5, iclass 27, count 2 2006.257.08:55:41.71#ibcon#about to read 6, iclass 27, count 2 2006.257.08:55:41.71#ibcon#read 6, iclass 27, count 2 2006.257.08:55:41.71#ibcon#end of sib2, iclass 27, count 2 2006.257.08:55:41.71#ibcon#*mode == 0, iclass 27, count 2 2006.257.08:55:41.71#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.08:55:41.71#ibcon#[27=AT06-04\r\n] 2006.257.08:55:41.71#ibcon#*before write, iclass 27, count 2 2006.257.08:55:41.71#ibcon#enter sib2, iclass 27, count 2 2006.257.08:55:41.71#ibcon#flushed, iclass 27, count 2 2006.257.08:55:41.71#ibcon#about to write, iclass 27, count 2 2006.257.08:55:41.71#ibcon#wrote, iclass 27, count 2 2006.257.08:55:41.71#ibcon#about to read 3, iclass 27, count 2 2006.257.08:55:41.74#ibcon#read 3, iclass 27, count 2 2006.257.08:55:41.74#ibcon#about to read 4, iclass 27, count 2 2006.257.08:55:41.74#ibcon#read 4, iclass 27, count 2 2006.257.08:55:41.74#ibcon#about to read 5, iclass 27, count 2 2006.257.08:55:41.74#ibcon#read 5, iclass 27, count 2 2006.257.08:55:41.74#ibcon#about to read 6, iclass 27, count 2 2006.257.08:55:41.74#ibcon#read 6, iclass 27, count 2 2006.257.08:55:41.74#ibcon#end of sib2, iclass 27, count 2 2006.257.08:55:41.74#ibcon#*after write, iclass 27, count 2 2006.257.08:55:41.74#ibcon#*before return 0, iclass 27, count 2 2006.257.08:55:41.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:41.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.08:55:41.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.08:55:41.74#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:41.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:41.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:41.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:41.86#ibcon#enter wrdev, iclass 27, count 0 2006.257.08:55:41.86#ibcon#first serial, iclass 27, count 0 2006.257.08:55:41.86#ibcon#enter sib2, iclass 27, count 0 2006.257.08:55:41.86#ibcon#flushed, iclass 27, count 0 2006.257.08:55:41.86#ibcon#about to write, iclass 27, count 0 2006.257.08:55:41.86#ibcon#wrote, iclass 27, count 0 2006.257.08:55:41.86#ibcon#about to read 3, iclass 27, count 0 2006.257.08:55:41.88#ibcon#read 3, iclass 27, count 0 2006.257.08:55:41.88#ibcon#about to read 4, iclass 27, count 0 2006.257.08:55:41.88#ibcon#read 4, iclass 27, count 0 2006.257.08:55:41.88#ibcon#about to read 5, iclass 27, count 0 2006.257.08:55:41.88#ibcon#read 5, iclass 27, count 0 2006.257.08:55:41.88#ibcon#about to read 6, iclass 27, count 0 2006.257.08:55:41.88#ibcon#read 6, iclass 27, count 0 2006.257.08:55:41.88#ibcon#end of sib2, iclass 27, count 0 2006.257.08:55:41.88#ibcon#*mode == 0, iclass 27, count 0 2006.257.08:55:41.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.08:55:41.88#ibcon#[27=USB\r\n] 2006.257.08:55:41.88#ibcon#*before write, iclass 27, count 0 2006.257.08:55:41.88#ibcon#enter sib2, iclass 27, count 0 2006.257.08:55:41.88#ibcon#flushed, iclass 27, count 0 2006.257.08:55:41.88#ibcon#about to write, iclass 27, count 0 2006.257.08:55:41.88#ibcon#wrote, iclass 27, count 0 2006.257.08:55:41.88#ibcon#about to read 3, iclass 27, count 0 2006.257.08:55:41.91#ibcon#read 3, iclass 27, count 0 2006.257.08:55:41.91#ibcon#about to read 4, iclass 27, count 0 2006.257.08:55:41.91#ibcon#read 4, iclass 27, count 0 2006.257.08:55:41.91#ibcon#about to read 5, iclass 27, count 0 2006.257.08:55:41.91#ibcon#read 5, iclass 27, count 0 2006.257.08:55:41.91#ibcon#about to read 6, iclass 27, count 0 2006.257.08:55:41.91#ibcon#read 6, iclass 27, count 0 2006.257.08:55:41.91#ibcon#end of sib2, iclass 27, count 0 2006.257.08:55:41.91#ibcon#*after write, iclass 27, count 0 2006.257.08:55:41.91#ibcon#*before return 0, iclass 27, count 0 2006.257.08:55:41.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:41.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.08:55:41.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.08:55:41.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.08:55:41.91$vck44/vblo=7,734.99 2006.257.08:55:41.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.08:55:41.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.08:55:41.91#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:41.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:41.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:41.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:41.91#ibcon#enter wrdev, iclass 29, count 0 2006.257.08:55:41.91#ibcon#first serial, iclass 29, count 0 2006.257.08:55:41.91#ibcon#enter sib2, iclass 29, count 0 2006.257.08:55:41.91#ibcon#flushed, iclass 29, count 0 2006.257.08:55:41.91#ibcon#about to write, iclass 29, count 0 2006.257.08:55:41.91#ibcon#wrote, iclass 29, count 0 2006.257.08:55:41.91#ibcon#about to read 3, iclass 29, count 0 2006.257.08:55:41.93#ibcon#read 3, iclass 29, count 0 2006.257.08:55:41.93#ibcon#about to read 4, iclass 29, count 0 2006.257.08:55:41.93#ibcon#read 4, iclass 29, count 0 2006.257.08:55:41.93#ibcon#about to read 5, iclass 29, count 0 2006.257.08:55:41.93#ibcon#read 5, iclass 29, count 0 2006.257.08:55:41.93#ibcon#about to read 6, iclass 29, count 0 2006.257.08:55:41.93#ibcon#read 6, iclass 29, count 0 2006.257.08:55:41.93#ibcon#end of sib2, iclass 29, count 0 2006.257.08:55:41.93#ibcon#*mode == 0, iclass 29, count 0 2006.257.08:55:41.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.08:55:41.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.08:55:41.93#ibcon#*before write, iclass 29, count 0 2006.257.08:55:41.93#ibcon#enter sib2, iclass 29, count 0 2006.257.08:55:41.93#ibcon#flushed, iclass 29, count 0 2006.257.08:55:41.93#ibcon#about to write, iclass 29, count 0 2006.257.08:55:41.93#ibcon#wrote, iclass 29, count 0 2006.257.08:55:41.93#ibcon#about to read 3, iclass 29, count 0 2006.257.08:55:41.97#ibcon#read 3, iclass 29, count 0 2006.257.08:55:41.97#ibcon#about to read 4, iclass 29, count 0 2006.257.08:55:41.97#ibcon#read 4, iclass 29, count 0 2006.257.08:55:41.97#ibcon#about to read 5, iclass 29, count 0 2006.257.08:55:41.97#ibcon#read 5, iclass 29, count 0 2006.257.08:55:41.97#ibcon#about to read 6, iclass 29, count 0 2006.257.08:55:41.97#ibcon#read 6, iclass 29, count 0 2006.257.08:55:41.97#ibcon#end of sib2, iclass 29, count 0 2006.257.08:55:41.97#ibcon#*after write, iclass 29, count 0 2006.257.08:55:41.97#ibcon#*before return 0, iclass 29, count 0 2006.257.08:55:41.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:41.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.08:55:41.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.08:55:41.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.08:55:41.97$vck44/vb=7,4 2006.257.08:55:41.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.08:55:41.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.08:55:41.97#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:41.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:42.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:42.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:42.03#ibcon#enter wrdev, iclass 31, count 2 2006.257.08:55:42.03#ibcon#first serial, iclass 31, count 2 2006.257.08:55:42.03#ibcon#enter sib2, iclass 31, count 2 2006.257.08:55:42.03#ibcon#flushed, iclass 31, count 2 2006.257.08:55:42.03#ibcon#about to write, iclass 31, count 2 2006.257.08:55:42.03#ibcon#wrote, iclass 31, count 2 2006.257.08:55:42.03#ibcon#about to read 3, iclass 31, count 2 2006.257.08:55:42.05#ibcon#read 3, iclass 31, count 2 2006.257.08:55:42.05#ibcon#about to read 4, iclass 31, count 2 2006.257.08:55:42.05#ibcon#read 4, iclass 31, count 2 2006.257.08:55:42.05#ibcon#about to read 5, iclass 31, count 2 2006.257.08:55:42.05#ibcon#read 5, iclass 31, count 2 2006.257.08:55:42.05#ibcon#about to read 6, iclass 31, count 2 2006.257.08:55:42.05#ibcon#read 6, iclass 31, count 2 2006.257.08:55:42.05#ibcon#end of sib2, iclass 31, count 2 2006.257.08:55:42.05#ibcon#*mode == 0, iclass 31, count 2 2006.257.08:55:42.05#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.08:55:42.05#ibcon#[27=AT07-04\r\n] 2006.257.08:55:42.05#ibcon#*before write, iclass 31, count 2 2006.257.08:55:42.05#ibcon#enter sib2, iclass 31, count 2 2006.257.08:55:42.05#ibcon#flushed, iclass 31, count 2 2006.257.08:55:42.05#ibcon#about to write, iclass 31, count 2 2006.257.08:55:42.05#ibcon#wrote, iclass 31, count 2 2006.257.08:55:42.05#ibcon#about to read 3, iclass 31, count 2 2006.257.08:55:42.08#ibcon#read 3, iclass 31, count 2 2006.257.08:55:42.08#ibcon#about to read 4, iclass 31, count 2 2006.257.08:55:42.08#ibcon#read 4, iclass 31, count 2 2006.257.08:55:42.08#ibcon#about to read 5, iclass 31, count 2 2006.257.08:55:42.08#ibcon#read 5, iclass 31, count 2 2006.257.08:55:42.08#ibcon#about to read 6, iclass 31, count 2 2006.257.08:55:42.08#ibcon#read 6, iclass 31, count 2 2006.257.08:55:42.08#ibcon#end of sib2, iclass 31, count 2 2006.257.08:55:42.08#ibcon#*after write, iclass 31, count 2 2006.257.08:55:42.08#ibcon#*before return 0, iclass 31, count 2 2006.257.08:55:42.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:42.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.08:55:42.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.08:55:42.08#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:42.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:42.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:42.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:42.20#ibcon#enter wrdev, iclass 31, count 0 2006.257.08:55:42.20#ibcon#first serial, iclass 31, count 0 2006.257.08:55:42.20#ibcon#enter sib2, iclass 31, count 0 2006.257.08:55:42.20#ibcon#flushed, iclass 31, count 0 2006.257.08:55:42.20#ibcon#about to write, iclass 31, count 0 2006.257.08:55:42.20#ibcon#wrote, iclass 31, count 0 2006.257.08:55:42.20#ibcon#about to read 3, iclass 31, count 0 2006.257.08:55:42.22#ibcon#read 3, iclass 31, count 0 2006.257.08:55:42.22#ibcon#about to read 4, iclass 31, count 0 2006.257.08:55:42.22#ibcon#read 4, iclass 31, count 0 2006.257.08:55:42.22#ibcon#about to read 5, iclass 31, count 0 2006.257.08:55:42.22#ibcon#read 5, iclass 31, count 0 2006.257.08:55:42.22#ibcon#about to read 6, iclass 31, count 0 2006.257.08:55:42.22#ibcon#read 6, iclass 31, count 0 2006.257.08:55:42.22#ibcon#end of sib2, iclass 31, count 0 2006.257.08:55:42.22#ibcon#*mode == 0, iclass 31, count 0 2006.257.08:55:42.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.08:55:42.22#ibcon#[27=USB\r\n] 2006.257.08:55:42.22#ibcon#*before write, iclass 31, count 0 2006.257.08:55:42.22#ibcon#enter sib2, iclass 31, count 0 2006.257.08:55:42.22#ibcon#flushed, iclass 31, count 0 2006.257.08:55:42.22#ibcon#about to write, iclass 31, count 0 2006.257.08:55:42.22#ibcon#wrote, iclass 31, count 0 2006.257.08:55:42.22#ibcon#about to read 3, iclass 31, count 0 2006.257.08:55:42.25#ibcon#read 3, iclass 31, count 0 2006.257.08:55:42.25#ibcon#about to read 4, iclass 31, count 0 2006.257.08:55:42.25#ibcon#read 4, iclass 31, count 0 2006.257.08:55:42.25#ibcon#about to read 5, iclass 31, count 0 2006.257.08:55:42.25#ibcon#read 5, iclass 31, count 0 2006.257.08:55:42.25#ibcon#about to read 6, iclass 31, count 0 2006.257.08:55:42.25#ibcon#read 6, iclass 31, count 0 2006.257.08:55:42.25#ibcon#end of sib2, iclass 31, count 0 2006.257.08:55:42.25#ibcon#*after write, iclass 31, count 0 2006.257.08:55:42.25#ibcon#*before return 0, iclass 31, count 0 2006.257.08:55:42.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:42.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.08:55:42.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.08:55:42.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.08:55:42.25$vck44/vblo=8,744.99 2006.257.08:55:42.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.08:55:42.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.08:55:42.25#ibcon#ireg 17 cls_cnt 0 2006.257.08:55:42.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:42.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:42.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:42.25#ibcon#enter wrdev, iclass 33, count 0 2006.257.08:55:42.25#ibcon#first serial, iclass 33, count 0 2006.257.08:55:42.25#ibcon#enter sib2, iclass 33, count 0 2006.257.08:55:42.25#ibcon#flushed, iclass 33, count 0 2006.257.08:55:42.25#ibcon#about to write, iclass 33, count 0 2006.257.08:55:42.25#ibcon#wrote, iclass 33, count 0 2006.257.08:55:42.25#ibcon#about to read 3, iclass 33, count 0 2006.257.08:55:42.27#ibcon#read 3, iclass 33, count 0 2006.257.08:55:42.27#ibcon#about to read 4, iclass 33, count 0 2006.257.08:55:42.27#ibcon#read 4, iclass 33, count 0 2006.257.08:55:42.27#ibcon#about to read 5, iclass 33, count 0 2006.257.08:55:42.27#ibcon#read 5, iclass 33, count 0 2006.257.08:55:42.27#ibcon#about to read 6, iclass 33, count 0 2006.257.08:55:42.27#ibcon#read 6, iclass 33, count 0 2006.257.08:55:42.27#ibcon#end of sib2, iclass 33, count 0 2006.257.08:55:42.27#ibcon#*mode == 0, iclass 33, count 0 2006.257.08:55:42.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.08:55:42.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.08:55:42.27#ibcon#*before write, iclass 33, count 0 2006.257.08:55:42.27#ibcon#enter sib2, iclass 33, count 0 2006.257.08:55:42.27#ibcon#flushed, iclass 33, count 0 2006.257.08:55:42.27#ibcon#about to write, iclass 33, count 0 2006.257.08:55:42.27#ibcon#wrote, iclass 33, count 0 2006.257.08:55:42.27#ibcon#about to read 3, iclass 33, count 0 2006.257.08:55:42.31#ibcon#read 3, iclass 33, count 0 2006.257.08:55:42.31#ibcon#about to read 4, iclass 33, count 0 2006.257.08:55:42.31#ibcon#read 4, iclass 33, count 0 2006.257.08:55:42.31#ibcon#about to read 5, iclass 33, count 0 2006.257.08:55:42.31#ibcon#read 5, iclass 33, count 0 2006.257.08:55:42.31#ibcon#about to read 6, iclass 33, count 0 2006.257.08:55:42.31#ibcon#read 6, iclass 33, count 0 2006.257.08:55:42.31#ibcon#end of sib2, iclass 33, count 0 2006.257.08:55:42.31#ibcon#*after write, iclass 33, count 0 2006.257.08:55:42.31#ibcon#*before return 0, iclass 33, count 0 2006.257.08:55:42.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:42.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.08:55:42.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.08:55:42.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.08:55:42.31$vck44/vb=8,4 2006.257.08:55:42.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.08:55:42.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.08:55:42.31#ibcon#ireg 11 cls_cnt 2 2006.257.08:55:42.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:42.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:42.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:42.37#ibcon#enter wrdev, iclass 35, count 2 2006.257.08:55:42.37#ibcon#first serial, iclass 35, count 2 2006.257.08:55:42.37#ibcon#enter sib2, iclass 35, count 2 2006.257.08:55:42.37#ibcon#flushed, iclass 35, count 2 2006.257.08:55:42.37#ibcon#about to write, iclass 35, count 2 2006.257.08:55:42.37#ibcon#wrote, iclass 35, count 2 2006.257.08:55:42.37#ibcon#about to read 3, iclass 35, count 2 2006.257.08:55:42.39#ibcon#read 3, iclass 35, count 2 2006.257.08:55:42.39#ibcon#about to read 4, iclass 35, count 2 2006.257.08:55:42.39#ibcon#read 4, iclass 35, count 2 2006.257.08:55:42.39#ibcon#about to read 5, iclass 35, count 2 2006.257.08:55:42.39#ibcon#read 5, iclass 35, count 2 2006.257.08:55:42.39#ibcon#about to read 6, iclass 35, count 2 2006.257.08:55:42.39#ibcon#read 6, iclass 35, count 2 2006.257.08:55:42.39#ibcon#end of sib2, iclass 35, count 2 2006.257.08:55:42.39#ibcon#*mode == 0, iclass 35, count 2 2006.257.08:55:42.39#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.08:55:42.39#ibcon#[27=AT08-04\r\n] 2006.257.08:55:42.39#ibcon#*before write, iclass 35, count 2 2006.257.08:55:42.39#ibcon#enter sib2, iclass 35, count 2 2006.257.08:55:42.39#ibcon#flushed, iclass 35, count 2 2006.257.08:55:42.39#ibcon#about to write, iclass 35, count 2 2006.257.08:55:42.39#ibcon#wrote, iclass 35, count 2 2006.257.08:55:42.39#ibcon#about to read 3, iclass 35, count 2 2006.257.08:55:42.42#ibcon#read 3, iclass 35, count 2 2006.257.08:55:42.42#ibcon#about to read 4, iclass 35, count 2 2006.257.08:55:42.42#ibcon#read 4, iclass 35, count 2 2006.257.08:55:42.42#ibcon#about to read 5, iclass 35, count 2 2006.257.08:55:42.42#ibcon#read 5, iclass 35, count 2 2006.257.08:55:42.42#ibcon#about to read 6, iclass 35, count 2 2006.257.08:55:42.42#ibcon#read 6, iclass 35, count 2 2006.257.08:55:42.42#ibcon#end of sib2, iclass 35, count 2 2006.257.08:55:42.42#ibcon#*after write, iclass 35, count 2 2006.257.08:55:42.42#ibcon#*before return 0, iclass 35, count 2 2006.257.08:55:42.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:42.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.08:55:42.42#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.08:55:42.42#ibcon#ireg 7 cls_cnt 0 2006.257.08:55:42.42#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:42.54#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:42.54#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:42.54#ibcon#enter wrdev, iclass 35, count 0 2006.257.08:55:42.54#ibcon#first serial, iclass 35, count 0 2006.257.08:55:42.54#ibcon#enter sib2, iclass 35, count 0 2006.257.08:55:42.54#ibcon#flushed, iclass 35, count 0 2006.257.08:55:42.54#ibcon#about to write, iclass 35, count 0 2006.257.08:55:42.54#ibcon#wrote, iclass 35, count 0 2006.257.08:55:42.54#ibcon#about to read 3, iclass 35, count 0 2006.257.08:55:42.56#ibcon#read 3, iclass 35, count 0 2006.257.08:55:42.56#ibcon#about to read 4, iclass 35, count 0 2006.257.08:55:42.56#ibcon#read 4, iclass 35, count 0 2006.257.08:55:42.56#ibcon#about to read 5, iclass 35, count 0 2006.257.08:55:42.56#ibcon#read 5, iclass 35, count 0 2006.257.08:55:42.56#ibcon#about to read 6, iclass 35, count 0 2006.257.08:55:42.56#ibcon#read 6, iclass 35, count 0 2006.257.08:55:42.56#ibcon#end of sib2, iclass 35, count 0 2006.257.08:55:42.56#ibcon#*mode == 0, iclass 35, count 0 2006.257.08:55:42.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.08:55:42.56#ibcon#[27=USB\r\n] 2006.257.08:55:42.56#ibcon#*before write, iclass 35, count 0 2006.257.08:55:42.56#ibcon#enter sib2, iclass 35, count 0 2006.257.08:55:42.56#ibcon#flushed, iclass 35, count 0 2006.257.08:55:42.56#ibcon#about to write, iclass 35, count 0 2006.257.08:55:42.56#ibcon#wrote, iclass 35, count 0 2006.257.08:55:42.56#ibcon#about to read 3, iclass 35, count 0 2006.257.08:55:42.59#ibcon#read 3, iclass 35, count 0 2006.257.08:55:42.59#ibcon#about to read 4, iclass 35, count 0 2006.257.08:55:42.59#ibcon#read 4, iclass 35, count 0 2006.257.08:55:42.59#ibcon#about to read 5, iclass 35, count 0 2006.257.08:55:42.59#ibcon#read 5, iclass 35, count 0 2006.257.08:55:42.59#ibcon#about to read 6, iclass 35, count 0 2006.257.08:55:42.59#ibcon#read 6, iclass 35, count 0 2006.257.08:55:42.59#ibcon#end of sib2, iclass 35, count 0 2006.257.08:55:42.59#ibcon#*after write, iclass 35, count 0 2006.257.08:55:42.59#ibcon#*before return 0, iclass 35, count 0 2006.257.08:55:42.59#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:42.59#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.08:55:42.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.08:55:42.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.08:55:42.59$vck44/vabw=wide 2006.257.08:55:42.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.08:55:42.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.08:55:42.59#ibcon#ireg 8 cls_cnt 0 2006.257.08:55:42.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:42.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:42.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:42.59#ibcon#enter wrdev, iclass 37, count 0 2006.257.08:55:42.59#ibcon#first serial, iclass 37, count 0 2006.257.08:55:42.59#ibcon#enter sib2, iclass 37, count 0 2006.257.08:55:42.59#ibcon#flushed, iclass 37, count 0 2006.257.08:55:42.59#ibcon#about to write, iclass 37, count 0 2006.257.08:55:42.59#ibcon#wrote, iclass 37, count 0 2006.257.08:55:42.59#ibcon#about to read 3, iclass 37, count 0 2006.257.08:55:42.61#ibcon#read 3, iclass 37, count 0 2006.257.08:55:42.61#ibcon#about to read 4, iclass 37, count 0 2006.257.08:55:42.61#ibcon#read 4, iclass 37, count 0 2006.257.08:55:42.61#ibcon#about to read 5, iclass 37, count 0 2006.257.08:55:42.61#ibcon#read 5, iclass 37, count 0 2006.257.08:55:42.61#ibcon#about to read 6, iclass 37, count 0 2006.257.08:55:42.61#ibcon#read 6, iclass 37, count 0 2006.257.08:55:42.61#ibcon#end of sib2, iclass 37, count 0 2006.257.08:55:42.61#ibcon#*mode == 0, iclass 37, count 0 2006.257.08:55:42.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.08:55:42.61#ibcon#[25=BW32\r\n] 2006.257.08:55:42.61#ibcon#*before write, iclass 37, count 0 2006.257.08:55:42.61#ibcon#enter sib2, iclass 37, count 0 2006.257.08:55:42.61#ibcon#flushed, iclass 37, count 0 2006.257.08:55:42.61#ibcon#about to write, iclass 37, count 0 2006.257.08:55:42.61#ibcon#wrote, iclass 37, count 0 2006.257.08:55:42.61#ibcon#about to read 3, iclass 37, count 0 2006.257.08:55:42.64#ibcon#read 3, iclass 37, count 0 2006.257.08:55:42.64#ibcon#about to read 4, iclass 37, count 0 2006.257.08:55:42.64#ibcon#read 4, iclass 37, count 0 2006.257.08:55:42.64#ibcon#about to read 5, iclass 37, count 0 2006.257.08:55:42.64#ibcon#read 5, iclass 37, count 0 2006.257.08:55:42.64#ibcon#about to read 6, iclass 37, count 0 2006.257.08:55:42.64#ibcon#read 6, iclass 37, count 0 2006.257.08:55:42.64#ibcon#end of sib2, iclass 37, count 0 2006.257.08:55:42.64#ibcon#*after write, iclass 37, count 0 2006.257.08:55:42.64#ibcon#*before return 0, iclass 37, count 0 2006.257.08:55:42.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:42.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.08:55:42.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.08:55:42.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.08:55:42.64$vck44/vbbw=wide 2006.257.08:55:42.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.08:55:42.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.08:55:42.64#ibcon#ireg 8 cls_cnt 0 2006.257.08:55:42.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:55:42.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:55:42.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:55:42.71#ibcon#enter wrdev, iclass 39, count 0 2006.257.08:55:42.71#ibcon#first serial, iclass 39, count 0 2006.257.08:55:42.71#ibcon#enter sib2, iclass 39, count 0 2006.257.08:55:42.71#ibcon#flushed, iclass 39, count 0 2006.257.08:55:42.71#ibcon#about to write, iclass 39, count 0 2006.257.08:55:42.71#ibcon#wrote, iclass 39, count 0 2006.257.08:55:42.71#ibcon#about to read 3, iclass 39, count 0 2006.257.08:55:42.73#ibcon#read 3, iclass 39, count 0 2006.257.08:55:42.73#ibcon#about to read 4, iclass 39, count 0 2006.257.08:55:42.73#ibcon#read 4, iclass 39, count 0 2006.257.08:55:42.73#ibcon#about to read 5, iclass 39, count 0 2006.257.08:55:42.73#ibcon#read 5, iclass 39, count 0 2006.257.08:55:42.73#ibcon#about to read 6, iclass 39, count 0 2006.257.08:55:42.73#ibcon#read 6, iclass 39, count 0 2006.257.08:55:42.73#ibcon#end of sib2, iclass 39, count 0 2006.257.08:55:42.73#ibcon#*mode == 0, iclass 39, count 0 2006.257.08:55:42.73#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.08:55:42.73#ibcon#[27=BW32\r\n] 2006.257.08:55:42.73#ibcon#*before write, iclass 39, count 0 2006.257.08:55:42.73#ibcon#enter sib2, iclass 39, count 0 2006.257.08:55:42.73#ibcon#flushed, iclass 39, count 0 2006.257.08:55:42.73#ibcon#about to write, iclass 39, count 0 2006.257.08:55:42.73#ibcon#wrote, iclass 39, count 0 2006.257.08:55:42.73#ibcon#about to read 3, iclass 39, count 0 2006.257.08:55:42.76#ibcon#read 3, iclass 39, count 0 2006.257.08:55:42.76#ibcon#about to read 4, iclass 39, count 0 2006.257.08:55:42.76#ibcon#read 4, iclass 39, count 0 2006.257.08:55:42.76#ibcon#about to read 5, iclass 39, count 0 2006.257.08:55:42.76#ibcon#read 5, iclass 39, count 0 2006.257.08:55:42.76#ibcon#about to read 6, iclass 39, count 0 2006.257.08:55:42.76#ibcon#read 6, iclass 39, count 0 2006.257.08:55:42.76#ibcon#end of sib2, iclass 39, count 0 2006.257.08:55:42.76#ibcon#*after write, iclass 39, count 0 2006.257.08:55:42.76#ibcon#*before return 0, iclass 39, count 0 2006.257.08:55:42.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:55:42.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.08:55:42.76#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.08:55:42.76#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.08:55:42.76$setupk4/ifdk4 2006.257.08:55:42.76$ifdk4/lo= 2006.257.08:55:42.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.08:55:42.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.08:55:42.76$ifdk4/patch= 2006.257.08:55:42.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.08:55:42.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.08:55:42.76$setupk4/!*+20s 2006.257.08:55:44.99#abcon#<5=/14 1.1 2.0 20.24 931013.2\r\n> 2006.257.08:55:45.01#abcon#{5=INTERFACE CLEAR} 2006.257.08:55:45.07#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:55:55.16#abcon#<5=/14 1.1 2.0 20.24 931013.2\r\n> 2006.257.08:55:55.18#abcon#{5=INTERFACE CLEAR} 2006.257.08:55:55.24#abcon#[5=S1D000X0/0*\r\n] 2006.257.08:55:57.26$setupk4/"tpicd 2006.257.08:55:57.26$setupk4/echo=off 2006.257.08:55:57.26$setupk4/xlog=off 2006.257.08:55:57.26:!2006.257.08:59:55 2006.257.08:55:58.14#trakl#Source acquired 2006.257.08:55:59.14#flagr#flagr/antenna,acquired 2006.257.08:59:55.00:preob 2006.257.08:59:55.14/onsource/TRACKING 2006.257.08:59:55.14:!2006.257.09:00:05 2006.257.09:00:05.00:"tape 2006.257.09:00:05.00:"st=record 2006.257.09:00:05.00:data_valid=on 2006.257.09:00:05.00:midob 2006.257.09:00:05.14/onsource/TRACKING 2006.257.09:00:05.14/wx/20.15,1013.2,94 2006.257.09:00:05.20/cable/+6.4741E-03 2006.257.09:00:06.29/va/01,08,usb,yes,35,38 2006.257.09:00:06.29/va/02,07,usb,yes,38,39 2006.257.09:00:06.29/va/03,08,usb,yes,34,36 2006.257.09:00:06.29/va/04,07,usb,yes,39,41 2006.257.09:00:06.29/va/05,04,usb,yes,35,36 2006.257.09:00:06.29/va/06,04,usb,yes,39,39 2006.257.09:00:06.29/va/07,04,usb,yes,40,41 2006.257.09:00:06.29/va/08,04,usb,yes,34,41 2006.257.09:00:06.52/valo/01,524.99,yes,locked 2006.257.09:00:06.52/valo/02,534.99,yes,locked 2006.257.09:00:06.52/valo/03,564.99,yes,locked 2006.257.09:00:06.52/valo/04,624.99,yes,locked 2006.257.09:00:06.52/valo/05,734.99,yes,locked 2006.257.09:00:06.52/valo/06,814.99,yes,locked 2006.257.09:00:06.52/valo/07,864.99,yes,locked 2006.257.09:00:06.52/valo/08,884.99,yes,locked 2006.257.09:00:07.61/vb/01,04,usb,yes,33,31 2006.257.09:00:07.61/vb/02,05,usb,yes,31,31 2006.257.09:00:07.61/vb/03,04,usb,yes,32,36 2006.257.09:00:07.61/vb/04,05,usb,yes,33,32 2006.257.09:00:07.61/vb/05,04,usb,yes,29,32 2006.257.09:00:07.61/vb/06,04,usb,yes,34,30 2006.257.09:00:07.61/vb/07,04,usb,yes,34,34 2006.257.09:00:07.61/vb/08,04,usb,yes,31,35 2006.257.09:00:07.84/vblo/01,629.99,yes,locked 2006.257.09:00:07.84/vblo/02,634.99,yes,locked 2006.257.09:00:07.84/vblo/03,649.99,yes,locked 2006.257.09:00:07.84/vblo/04,679.99,yes,locked 2006.257.09:00:07.84/vblo/05,709.99,yes,locked 2006.257.09:00:07.84/vblo/06,719.99,yes,locked 2006.257.09:00:07.84/vblo/07,734.99,yes,locked 2006.257.09:00:07.84/vblo/08,744.99,yes,locked 2006.257.09:00:07.99/vabw/8 2006.257.09:00:08.14/vbbw/8 2006.257.09:00:08.27/xfe/off,on,14.7 2006.257.09:00:08.65/ifatt/23,28,28,28 2006.257.09:00:09.08/fmout-gps/S +4.65E-07 2006.257.09:00:09.12:!2006.257.09:00:45 2006.257.09:00:45.00:data_valid=off 2006.257.09:00:45.00:"et 2006.257.09:00:45.00:!+3s 2006.257.09:00:48.02:"tape 2006.257.09:00:48.02:postob 2006.257.09:00:48.09/cable/+6.4759E-03 2006.257.09:00:48.09/wx/20.14,1013.2,94 2006.257.09:00:49.07/fmout-gps/S +4.65E-07 2006.257.09:00:49.07:scan_name=257-0907,jd0609,40 2006.257.09:00:49.07:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.09:00:50.14#flagr#flagr/antenna,new-source 2006.257.09:00:50.14:checkk5 2006.257.09:00:50.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:00:50.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:00:51.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:00:51.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:00:52.12/chk_obsdata//k5ts1/T2570900??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:00:52.52/chk_obsdata//k5ts2/T2570900??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:00:52.92/chk_obsdata//k5ts3/T2570900??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:00:53.32/chk_obsdata//k5ts4/T2570900??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:00:54.02/k5log//k5ts1_log_newline 2006.257.09:00:54.72/k5log//k5ts2_log_newline 2006.257.09:00:55.43/k5log//k5ts3_log_newline 2006.257.09:00:56.15/k5log//k5ts4_log_newline 2006.257.09:00:56.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:00:56.17:setupk4=1 2006.257.09:00:56.17$setupk4/echo=on 2006.257.09:00:56.17$setupk4/pcalon 2006.257.09:00:56.17$pcalon/"no phase cal control is implemented here 2006.257.09:00:56.17$setupk4/"tpicd=stop 2006.257.09:00:56.17$setupk4/"rec=synch_on 2006.257.09:00:56.17$setupk4/"rec_mode=128 2006.257.09:00:56.17$setupk4/!* 2006.257.09:00:56.17$setupk4/recpk4 2006.257.09:00:56.17$recpk4/recpatch= 2006.257.09:00:56.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:00:56.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:00:56.18$setupk4/vck44 2006.257.09:00:56.18$vck44/valo=1,524.99 2006.257.09:00:56.18#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.09:00:56.18#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.09:00:56.18#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:56.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:56.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:56.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:56.18#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:00:56.18#ibcon#first serial, iclass 24, count 0 2006.257.09:00:56.18#ibcon#enter sib2, iclass 24, count 0 2006.257.09:00:56.18#ibcon#flushed, iclass 24, count 0 2006.257.09:00:56.18#ibcon#about to write, iclass 24, count 0 2006.257.09:00:56.18#ibcon#wrote, iclass 24, count 0 2006.257.09:00:56.18#ibcon#about to read 3, iclass 24, count 0 2006.257.09:00:56.20#ibcon#read 3, iclass 24, count 0 2006.257.09:00:56.20#ibcon#about to read 4, iclass 24, count 0 2006.257.09:00:56.20#ibcon#read 4, iclass 24, count 0 2006.257.09:00:56.20#ibcon#about to read 5, iclass 24, count 0 2006.257.09:00:56.20#ibcon#read 5, iclass 24, count 0 2006.257.09:00:56.20#ibcon#about to read 6, iclass 24, count 0 2006.257.09:00:56.20#ibcon#read 6, iclass 24, count 0 2006.257.09:00:56.20#ibcon#end of sib2, iclass 24, count 0 2006.257.09:00:56.20#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:00:56.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:00:56.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:00:56.20#ibcon#*before write, iclass 24, count 0 2006.257.09:00:56.20#ibcon#enter sib2, iclass 24, count 0 2006.257.09:00:56.20#ibcon#flushed, iclass 24, count 0 2006.257.09:00:56.20#ibcon#about to write, iclass 24, count 0 2006.257.09:00:56.20#ibcon#wrote, iclass 24, count 0 2006.257.09:00:56.20#ibcon#about to read 3, iclass 24, count 0 2006.257.09:00:56.25#ibcon#read 3, iclass 24, count 0 2006.257.09:00:56.25#ibcon#about to read 4, iclass 24, count 0 2006.257.09:00:56.25#ibcon#read 4, iclass 24, count 0 2006.257.09:00:56.25#ibcon#about to read 5, iclass 24, count 0 2006.257.09:00:56.25#ibcon#read 5, iclass 24, count 0 2006.257.09:00:56.25#ibcon#about to read 6, iclass 24, count 0 2006.257.09:00:56.25#ibcon#read 6, iclass 24, count 0 2006.257.09:00:56.25#ibcon#end of sib2, iclass 24, count 0 2006.257.09:00:56.25#ibcon#*after write, iclass 24, count 0 2006.257.09:00:56.25#ibcon#*before return 0, iclass 24, count 0 2006.257.09:00:56.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:56.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:56.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:00:56.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:00:56.25$vck44/va=1,8 2006.257.09:00:56.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.09:00:56.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.09:00:56.25#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:56.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:56.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:56.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:56.25#ibcon#enter wrdev, iclass 26, count 2 2006.257.09:00:56.25#ibcon#first serial, iclass 26, count 2 2006.257.09:00:56.25#ibcon#enter sib2, iclass 26, count 2 2006.257.09:00:56.25#ibcon#flushed, iclass 26, count 2 2006.257.09:00:56.25#ibcon#about to write, iclass 26, count 2 2006.257.09:00:56.25#ibcon#wrote, iclass 26, count 2 2006.257.09:00:56.25#ibcon#about to read 3, iclass 26, count 2 2006.257.09:00:56.27#ibcon#read 3, iclass 26, count 2 2006.257.09:00:56.27#ibcon#about to read 4, iclass 26, count 2 2006.257.09:00:56.27#ibcon#read 4, iclass 26, count 2 2006.257.09:00:56.27#ibcon#about to read 5, iclass 26, count 2 2006.257.09:00:56.27#ibcon#read 5, iclass 26, count 2 2006.257.09:00:56.27#ibcon#about to read 6, iclass 26, count 2 2006.257.09:00:56.27#ibcon#read 6, iclass 26, count 2 2006.257.09:00:56.27#ibcon#end of sib2, iclass 26, count 2 2006.257.09:00:56.27#ibcon#*mode == 0, iclass 26, count 2 2006.257.09:00:56.27#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.09:00:56.27#ibcon#[25=AT01-08\r\n] 2006.257.09:00:56.27#ibcon#*before write, iclass 26, count 2 2006.257.09:00:56.27#ibcon#enter sib2, iclass 26, count 2 2006.257.09:00:56.27#ibcon#flushed, iclass 26, count 2 2006.257.09:00:56.27#ibcon#about to write, iclass 26, count 2 2006.257.09:00:56.27#ibcon#wrote, iclass 26, count 2 2006.257.09:00:56.27#ibcon#about to read 3, iclass 26, count 2 2006.257.09:00:56.30#ibcon#read 3, iclass 26, count 2 2006.257.09:00:56.30#ibcon#about to read 4, iclass 26, count 2 2006.257.09:00:56.30#ibcon#read 4, iclass 26, count 2 2006.257.09:00:56.30#ibcon#about to read 5, iclass 26, count 2 2006.257.09:00:56.30#ibcon#read 5, iclass 26, count 2 2006.257.09:00:56.30#ibcon#about to read 6, iclass 26, count 2 2006.257.09:00:56.30#ibcon#read 6, iclass 26, count 2 2006.257.09:00:56.30#ibcon#end of sib2, iclass 26, count 2 2006.257.09:00:56.30#ibcon#*after write, iclass 26, count 2 2006.257.09:00:56.30#ibcon#*before return 0, iclass 26, count 2 2006.257.09:00:56.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:56.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:56.30#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.09:00:56.30#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:56.30#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:56.42#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:56.42#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:56.42#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:00:56.42#ibcon#first serial, iclass 26, count 0 2006.257.09:00:56.42#ibcon#enter sib2, iclass 26, count 0 2006.257.09:00:56.42#ibcon#flushed, iclass 26, count 0 2006.257.09:00:56.42#ibcon#about to write, iclass 26, count 0 2006.257.09:00:56.42#ibcon#wrote, iclass 26, count 0 2006.257.09:00:56.42#ibcon#about to read 3, iclass 26, count 0 2006.257.09:00:56.44#ibcon#read 3, iclass 26, count 0 2006.257.09:00:56.44#ibcon#about to read 4, iclass 26, count 0 2006.257.09:00:56.44#ibcon#read 4, iclass 26, count 0 2006.257.09:00:56.44#ibcon#about to read 5, iclass 26, count 0 2006.257.09:00:56.44#ibcon#read 5, iclass 26, count 0 2006.257.09:00:56.44#ibcon#about to read 6, iclass 26, count 0 2006.257.09:00:56.44#ibcon#read 6, iclass 26, count 0 2006.257.09:00:56.44#ibcon#end of sib2, iclass 26, count 0 2006.257.09:00:56.44#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:00:56.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:00:56.44#ibcon#[25=USB\r\n] 2006.257.09:00:56.44#ibcon#*before write, iclass 26, count 0 2006.257.09:00:56.44#ibcon#enter sib2, iclass 26, count 0 2006.257.09:00:56.44#ibcon#flushed, iclass 26, count 0 2006.257.09:00:56.44#ibcon#about to write, iclass 26, count 0 2006.257.09:00:56.44#ibcon#wrote, iclass 26, count 0 2006.257.09:00:56.44#ibcon#about to read 3, iclass 26, count 0 2006.257.09:00:56.47#ibcon#read 3, iclass 26, count 0 2006.257.09:00:56.47#ibcon#about to read 4, iclass 26, count 0 2006.257.09:00:56.47#ibcon#read 4, iclass 26, count 0 2006.257.09:00:56.47#ibcon#about to read 5, iclass 26, count 0 2006.257.09:00:56.47#ibcon#read 5, iclass 26, count 0 2006.257.09:00:56.47#ibcon#about to read 6, iclass 26, count 0 2006.257.09:00:56.47#ibcon#read 6, iclass 26, count 0 2006.257.09:00:56.47#ibcon#end of sib2, iclass 26, count 0 2006.257.09:00:56.47#ibcon#*after write, iclass 26, count 0 2006.257.09:00:56.47#ibcon#*before return 0, iclass 26, count 0 2006.257.09:00:56.47#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:56.47#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:56.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:00:56.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:00:56.47$vck44/valo=2,534.99 2006.257.09:00:56.47#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.09:00:56.47#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.09:00:56.47#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:56.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:56.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:56.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:56.47#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:00:56.47#ibcon#first serial, iclass 28, count 0 2006.257.09:00:56.47#ibcon#enter sib2, iclass 28, count 0 2006.257.09:00:56.47#ibcon#flushed, iclass 28, count 0 2006.257.09:00:56.47#ibcon#about to write, iclass 28, count 0 2006.257.09:00:56.47#ibcon#wrote, iclass 28, count 0 2006.257.09:00:56.47#ibcon#about to read 3, iclass 28, count 0 2006.257.09:00:56.49#ibcon#read 3, iclass 28, count 0 2006.257.09:00:56.49#ibcon#about to read 4, iclass 28, count 0 2006.257.09:00:56.49#ibcon#read 4, iclass 28, count 0 2006.257.09:00:56.49#ibcon#about to read 5, iclass 28, count 0 2006.257.09:00:56.49#ibcon#read 5, iclass 28, count 0 2006.257.09:00:56.49#ibcon#about to read 6, iclass 28, count 0 2006.257.09:00:56.49#ibcon#read 6, iclass 28, count 0 2006.257.09:00:56.49#ibcon#end of sib2, iclass 28, count 0 2006.257.09:00:56.49#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:00:56.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:00:56.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:00:56.49#ibcon#*before write, iclass 28, count 0 2006.257.09:00:56.49#ibcon#enter sib2, iclass 28, count 0 2006.257.09:00:56.49#ibcon#flushed, iclass 28, count 0 2006.257.09:00:56.49#ibcon#about to write, iclass 28, count 0 2006.257.09:00:56.49#ibcon#wrote, iclass 28, count 0 2006.257.09:00:56.49#ibcon#about to read 3, iclass 28, count 0 2006.257.09:00:56.53#ibcon#read 3, iclass 28, count 0 2006.257.09:00:56.53#ibcon#about to read 4, iclass 28, count 0 2006.257.09:00:56.53#ibcon#read 4, iclass 28, count 0 2006.257.09:00:56.53#ibcon#about to read 5, iclass 28, count 0 2006.257.09:00:56.53#ibcon#read 5, iclass 28, count 0 2006.257.09:00:56.53#ibcon#about to read 6, iclass 28, count 0 2006.257.09:00:56.53#ibcon#read 6, iclass 28, count 0 2006.257.09:00:56.53#ibcon#end of sib2, iclass 28, count 0 2006.257.09:00:56.53#ibcon#*after write, iclass 28, count 0 2006.257.09:00:56.53#ibcon#*before return 0, iclass 28, count 0 2006.257.09:00:56.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:56.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:56.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:00:56.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:00:56.53$vck44/va=2,7 2006.257.09:00:56.53#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.09:00:56.53#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.09:00:56.53#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:56.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:56.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:56.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:56.59#ibcon#enter wrdev, iclass 30, count 2 2006.257.09:00:56.59#ibcon#first serial, iclass 30, count 2 2006.257.09:00:56.59#ibcon#enter sib2, iclass 30, count 2 2006.257.09:00:56.59#ibcon#flushed, iclass 30, count 2 2006.257.09:00:56.59#ibcon#about to write, iclass 30, count 2 2006.257.09:00:56.59#ibcon#wrote, iclass 30, count 2 2006.257.09:00:56.59#ibcon#about to read 3, iclass 30, count 2 2006.257.09:00:56.61#ibcon#read 3, iclass 30, count 2 2006.257.09:00:56.61#ibcon#about to read 4, iclass 30, count 2 2006.257.09:00:56.61#ibcon#read 4, iclass 30, count 2 2006.257.09:00:56.61#ibcon#about to read 5, iclass 30, count 2 2006.257.09:00:56.61#ibcon#read 5, iclass 30, count 2 2006.257.09:00:56.61#ibcon#about to read 6, iclass 30, count 2 2006.257.09:00:56.61#ibcon#read 6, iclass 30, count 2 2006.257.09:00:56.61#ibcon#end of sib2, iclass 30, count 2 2006.257.09:00:56.61#ibcon#*mode == 0, iclass 30, count 2 2006.257.09:00:56.61#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.09:00:56.61#ibcon#[25=AT02-07\r\n] 2006.257.09:00:56.61#ibcon#*before write, iclass 30, count 2 2006.257.09:00:56.61#ibcon#enter sib2, iclass 30, count 2 2006.257.09:00:56.61#ibcon#flushed, iclass 30, count 2 2006.257.09:00:56.61#ibcon#about to write, iclass 30, count 2 2006.257.09:00:56.61#ibcon#wrote, iclass 30, count 2 2006.257.09:00:56.61#ibcon#about to read 3, iclass 30, count 2 2006.257.09:00:56.64#ibcon#read 3, iclass 30, count 2 2006.257.09:00:56.64#ibcon#about to read 4, iclass 30, count 2 2006.257.09:00:56.64#ibcon#read 4, iclass 30, count 2 2006.257.09:00:56.64#ibcon#about to read 5, iclass 30, count 2 2006.257.09:00:56.64#ibcon#read 5, iclass 30, count 2 2006.257.09:00:56.64#ibcon#about to read 6, iclass 30, count 2 2006.257.09:00:56.64#ibcon#read 6, iclass 30, count 2 2006.257.09:00:56.64#ibcon#end of sib2, iclass 30, count 2 2006.257.09:00:56.64#ibcon#*after write, iclass 30, count 2 2006.257.09:00:56.64#ibcon#*before return 0, iclass 30, count 2 2006.257.09:00:56.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:56.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:56.64#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.09:00:56.64#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:56.64#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:56.76#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:56.76#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:56.76#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:00:56.76#ibcon#first serial, iclass 30, count 0 2006.257.09:00:56.76#ibcon#enter sib2, iclass 30, count 0 2006.257.09:00:56.76#ibcon#flushed, iclass 30, count 0 2006.257.09:00:56.76#ibcon#about to write, iclass 30, count 0 2006.257.09:00:56.76#ibcon#wrote, iclass 30, count 0 2006.257.09:00:56.76#ibcon#about to read 3, iclass 30, count 0 2006.257.09:00:56.78#ibcon#read 3, iclass 30, count 0 2006.257.09:00:56.78#ibcon#about to read 4, iclass 30, count 0 2006.257.09:00:56.78#ibcon#read 4, iclass 30, count 0 2006.257.09:00:56.78#ibcon#about to read 5, iclass 30, count 0 2006.257.09:00:56.78#ibcon#read 5, iclass 30, count 0 2006.257.09:00:56.78#ibcon#about to read 6, iclass 30, count 0 2006.257.09:00:56.78#ibcon#read 6, iclass 30, count 0 2006.257.09:00:56.78#ibcon#end of sib2, iclass 30, count 0 2006.257.09:00:56.78#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:00:56.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:00:56.78#ibcon#[25=USB\r\n] 2006.257.09:00:56.78#ibcon#*before write, iclass 30, count 0 2006.257.09:00:56.78#ibcon#enter sib2, iclass 30, count 0 2006.257.09:00:56.78#ibcon#flushed, iclass 30, count 0 2006.257.09:00:56.78#ibcon#about to write, iclass 30, count 0 2006.257.09:00:56.78#ibcon#wrote, iclass 30, count 0 2006.257.09:00:56.78#ibcon#about to read 3, iclass 30, count 0 2006.257.09:00:56.81#ibcon#read 3, iclass 30, count 0 2006.257.09:00:56.81#ibcon#about to read 4, iclass 30, count 0 2006.257.09:00:56.81#ibcon#read 4, iclass 30, count 0 2006.257.09:00:56.81#ibcon#about to read 5, iclass 30, count 0 2006.257.09:00:56.81#ibcon#read 5, iclass 30, count 0 2006.257.09:00:56.81#ibcon#about to read 6, iclass 30, count 0 2006.257.09:00:56.81#ibcon#read 6, iclass 30, count 0 2006.257.09:00:56.81#ibcon#end of sib2, iclass 30, count 0 2006.257.09:00:56.81#ibcon#*after write, iclass 30, count 0 2006.257.09:00:56.81#ibcon#*before return 0, iclass 30, count 0 2006.257.09:00:56.81#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:56.81#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:56.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:00:56.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:00:56.81$vck44/valo=3,564.99 2006.257.09:00:56.81#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.09:00:56.81#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.09:00:56.81#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:56.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:56.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:56.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:56.81#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:00:56.81#ibcon#first serial, iclass 32, count 0 2006.257.09:00:56.81#ibcon#enter sib2, iclass 32, count 0 2006.257.09:00:56.81#ibcon#flushed, iclass 32, count 0 2006.257.09:00:56.81#ibcon#about to write, iclass 32, count 0 2006.257.09:00:56.81#ibcon#wrote, iclass 32, count 0 2006.257.09:00:56.81#ibcon#about to read 3, iclass 32, count 0 2006.257.09:00:56.83#ibcon#read 3, iclass 32, count 0 2006.257.09:00:56.83#ibcon#about to read 4, iclass 32, count 0 2006.257.09:00:56.83#ibcon#read 4, iclass 32, count 0 2006.257.09:00:56.83#ibcon#about to read 5, iclass 32, count 0 2006.257.09:00:56.83#ibcon#read 5, iclass 32, count 0 2006.257.09:00:56.83#ibcon#about to read 6, iclass 32, count 0 2006.257.09:00:56.83#ibcon#read 6, iclass 32, count 0 2006.257.09:00:56.83#ibcon#end of sib2, iclass 32, count 0 2006.257.09:00:56.83#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:00:56.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:00:56.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:00:56.83#ibcon#*before write, iclass 32, count 0 2006.257.09:00:56.83#ibcon#enter sib2, iclass 32, count 0 2006.257.09:00:56.83#ibcon#flushed, iclass 32, count 0 2006.257.09:00:56.83#ibcon#about to write, iclass 32, count 0 2006.257.09:00:56.83#ibcon#wrote, iclass 32, count 0 2006.257.09:00:56.83#ibcon#about to read 3, iclass 32, count 0 2006.257.09:00:56.87#ibcon#read 3, iclass 32, count 0 2006.257.09:00:56.87#ibcon#about to read 4, iclass 32, count 0 2006.257.09:00:56.87#ibcon#read 4, iclass 32, count 0 2006.257.09:00:56.87#ibcon#about to read 5, iclass 32, count 0 2006.257.09:00:56.87#ibcon#read 5, iclass 32, count 0 2006.257.09:00:56.87#ibcon#about to read 6, iclass 32, count 0 2006.257.09:00:56.87#ibcon#read 6, iclass 32, count 0 2006.257.09:00:56.87#ibcon#end of sib2, iclass 32, count 0 2006.257.09:00:56.87#ibcon#*after write, iclass 32, count 0 2006.257.09:00:56.87#ibcon#*before return 0, iclass 32, count 0 2006.257.09:00:56.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:56.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:56.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:00:56.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:00:56.87$vck44/va=3,8 2006.257.09:00:56.87#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.09:00:56.87#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.09:00:56.87#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:56.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:56.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:56.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:56.93#ibcon#enter wrdev, iclass 34, count 2 2006.257.09:00:56.93#ibcon#first serial, iclass 34, count 2 2006.257.09:00:56.93#ibcon#enter sib2, iclass 34, count 2 2006.257.09:00:56.93#ibcon#flushed, iclass 34, count 2 2006.257.09:00:56.93#ibcon#about to write, iclass 34, count 2 2006.257.09:00:56.93#ibcon#wrote, iclass 34, count 2 2006.257.09:00:56.93#ibcon#about to read 3, iclass 34, count 2 2006.257.09:00:56.95#ibcon#read 3, iclass 34, count 2 2006.257.09:00:56.95#ibcon#about to read 4, iclass 34, count 2 2006.257.09:00:56.95#ibcon#read 4, iclass 34, count 2 2006.257.09:00:56.95#ibcon#about to read 5, iclass 34, count 2 2006.257.09:00:56.95#ibcon#read 5, iclass 34, count 2 2006.257.09:00:56.95#ibcon#about to read 6, iclass 34, count 2 2006.257.09:00:56.95#ibcon#read 6, iclass 34, count 2 2006.257.09:00:56.95#ibcon#end of sib2, iclass 34, count 2 2006.257.09:00:56.95#ibcon#*mode == 0, iclass 34, count 2 2006.257.09:00:56.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.09:00:56.95#ibcon#[25=AT03-08\r\n] 2006.257.09:00:56.95#ibcon#*before write, iclass 34, count 2 2006.257.09:00:56.95#ibcon#enter sib2, iclass 34, count 2 2006.257.09:00:56.95#ibcon#flushed, iclass 34, count 2 2006.257.09:00:56.95#ibcon#about to write, iclass 34, count 2 2006.257.09:00:56.95#ibcon#wrote, iclass 34, count 2 2006.257.09:00:56.95#ibcon#about to read 3, iclass 34, count 2 2006.257.09:00:56.98#ibcon#read 3, iclass 34, count 2 2006.257.09:00:56.98#ibcon#about to read 4, iclass 34, count 2 2006.257.09:00:56.98#ibcon#read 4, iclass 34, count 2 2006.257.09:00:56.98#ibcon#about to read 5, iclass 34, count 2 2006.257.09:00:56.98#ibcon#read 5, iclass 34, count 2 2006.257.09:00:56.98#ibcon#about to read 6, iclass 34, count 2 2006.257.09:00:56.98#ibcon#read 6, iclass 34, count 2 2006.257.09:00:56.98#ibcon#end of sib2, iclass 34, count 2 2006.257.09:00:56.98#ibcon#*after write, iclass 34, count 2 2006.257.09:00:56.98#ibcon#*before return 0, iclass 34, count 2 2006.257.09:00:56.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:56.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:56.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.09:00:56.98#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:56.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:00:57.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:00:57.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:00:57.10#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:00:57.10#ibcon#first serial, iclass 34, count 0 2006.257.09:00:57.10#ibcon#enter sib2, iclass 34, count 0 2006.257.09:00:57.10#ibcon#flushed, iclass 34, count 0 2006.257.09:00:57.10#ibcon#about to write, iclass 34, count 0 2006.257.09:00:57.10#ibcon#wrote, iclass 34, count 0 2006.257.09:00:57.10#ibcon#about to read 3, iclass 34, count 0 2006.257.09:00:57.12#ibcon#read 3, iclass 34, count 0 2006.257.09:00:57.12#ibcon#about to read 4, iclass 34, count 0 2006.257.09:00:57.12#ibcon#read 4, iclass 34, count 0 2006.257.09:00:57.12#ibcon#about to read 5, iclass 34, count 0 2006.257.09:00:57.12#ibcon#read 5, iclass 34, count 0 2006.257.09:00:57.12#ibcon#about to read 6, iclass 34, count 0 2006.257.09:00:57.12#ibcon#read 6, iclass 34, count 0 2006.257.09:00:57.12#ibcon#end of sib2, iclass 34, count 0 2006.257.09:00:57.12#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:00:57.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:00:57.12#ibcon#[25=USB\r\n] 2006.257.09:00:57.12#ibcon#*before write, iclass 34, count 0 2006.257.09:00:57.12#ibcon#enter sib2, iclass 34, count 0 2006.257.09:00:57.12#ibcon#flushed, iclass 34, count 0 2006.257.09:00:57.12#ibcon#about to write, iclass 34, count 0 2006.257.09:00:57.12#ibcon#wrote, iclass 34, count 0 2006.257.09:00:57.12#ibcon#about to read 3, iclass 34, count 0 2006.257.09:00:57.15#ibcon#read 3, iclass 34, count 0 2006.257.09:00:57.15#ibcon#about to read 4, iclass 34, count 0 2006.257.09:00:57.15#ibcon#read 4, iclass 34, count 0 2006.257.09:00:57.15#ibcon#about to read 5, iclass 34, count 0 2006.257.09:00:57.15#ibcon#read 5, iclass 34, count 0 2006.257.09:00:57.15#ibcon#about to read 6, iclass 34, count 0 2006.257.09:00:57.15#ibcon#read 6, iclass 34, count 0 2006.257.09:00:57.15#ibcon#end of sib2, iclass 34, count 0 2006.257.09:00:57.15#ibcon#*after write, iclass 34, count 0 2006.257.09:00:57.15#ibcon#*before return 0, iclass 34, count 0 2006.257.09:00:57.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:00:57.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:00:57.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:00:57.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:00:57.15$vck44/valo=4,624.99 2006.257.09:00:57.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.09:00:57.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.09:00:57.15#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:57.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:00:57.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:00:57.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:00:57.15#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:00:57.15#ibcon#first serial, iclass 36, count 0 2006.257.09:00:57.15#ibcon#enter sib2, iclass 36, count 0 2006.257.09:00:57.15#ibcon#flushed, iclass 36, count 0 2006.257.09:00:57.15#ibcon#about to write, iclass 36, count 0 2006.257.09:00:57.15#ibcon#wrote, iclass 36, count 0 2006.257.09:00:57.15#ibcon#about to read 3, iclass 36, count 0 2006.257.09:00:57.17#ibcon#read 3, iclass 36, count 0 2006.257.09:00:57.17#ibcon#about to read 4, iclass 36, count 0 2006.257.09:00:57.17#ibcon#read 4, iclass 36, count 0 2006.257.09:00:57.17#ibcon#about to read 5, iclass 36, count 0 2006.257.09:00:57.17#ibcon#read 5, iclass 36, count 0 2006.257.09:00:57.17#ibcon#about to read 6, iclass 36, count 0 2006.257.09:00:57.17#ibcon#read 6, iclass 36, count 0 2006.257.09:00:57.17#ibcon#end of sib2, iclass 36, count 0 2006.257.09:00:57.17#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:00:57.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:00:57.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:00:57.17#ibcon#*before write, iclass 36, count 0 2006.257.09:00:57.17#ibcon#enter sib2, iclass 36, count 0 2006.257.09:00:57.17#ibcon#flushed, iclass 36, count 0 2006.257.09:00:57.17#ibcon#about to write, iclass 36, count 0 2006.257.09:00:57.17#ibcon#wrote, iclass 36, count 0 2006.257.09:00:57.17#ibcon#about to read 3, iclass 36, count 0 2006.257.09:00:57.21#ibcon#read 3, iclass 36, count 0 2006.257.09:00:57.21#ibcon#about to read 4, iclass 36, count 0 2006.257.09:00:57.21#ibcon#read 4, iclass 36, count 0 2006.257.09:00:57.21#ibcon#about to read 5, iclass 36, count 0 2006.257.09:00:57.21#ibcon#read 5, iclass 36, count 0 2006.257.09:00:57.21#ibcon#about to read 6, iclass 36, count 0 2006.257.09:00:57.21#ibcon#read 6, iclass 36, count 0 2006.257.09:00:57.21#ibcon#end of sib2, iclass 36, count 0 2006.257.09:00:57.21#ibcon#*after write, iclass 36, count 0 2006.257.09:00:57.21#ibcon#*before return 0, iclass 36, count 0 2006.257.09:00:57.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:00:57.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:00:57.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:00:57.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:00:57.21$vck44/va=4,7 2006.257.09:00:57.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.09:00:57.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.09:00:57.21#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:57.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:00:57.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:00:57.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:00:57.27#ibcon#enter wrdev, iclass 38, count 2 2006.257.09:00:57.27#ibcon#first serial, iclass 38, count 2 2006.257.09:00:57.27#ibcon#enter sib2, iclass 38, count 2 2006.257.09:00:57.27#ibcon#flushed, iclass 38, count 2 2006.257.09:00:57.27#ibcon#about to write, iclass 38, count 2 2006.257.09:00:57.27#ibcon#wrote, iclass 38, count 2 2006.257.09:00:57.27#ibcon#about to read 3, iclass 38, count 2 2006.257.09:00:57.29#ibcon#read 3, iclass 38, count 2 2006.257.09:00:57.29#ibcon#about to read 4, iclass 38, count 2 2006.257.09:00:57.29#ibcon#read 4, iclass 38, count 2 2006.257.09:00:57.29#ibcon#about to read 5, iclass 38, count 2 2006.257.09:00:57.29#ibcon#read 5, iclass 38, count 2 2006.257.09:00:57.29#ibcon#about to read 6, iclass 38, count 2 2006.257.09:00:57.29#ibcon#read 6, iclass 38, count 2 2006.257.09:00:57.29#ibcon#end of sib2, iclass 38, count 2 2006.257.09:00:57.29#ibcon#*mode == 0, iclass 38, count 2 2006.257.09:00:57.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.09:00:57.29#ibcon#[25=AT04-07\r\n] 2006.257.09:00:57.29#ibcon#*before write, iclass 38, count 2 2006.257.09:00:57.29#ibcon#enter sib2, iclass 38, count 2 2006.257.09:00:57.29#ibcon#flushed, iclass 38, count 2 2006.257.09:00:57.29#ibcon#about to write, iclass 38, count 2 2006.257.09:00:57.29#ibcon#wrote, iclass 38, count 2 2006.257.09:00:57.29#ibcon#about to read 3, iclass 38, count 2 2006.257.09:00:57.32#ibcon#read 3, iclass 38, count 2 2006.257.09:00:57.32#ibcon#about to read 4, iclass 38, count 2 2006.257.09:00:57.32#ibcon#read 4, iclass 38, count 2 2006.257.09:00:57.32#ibcon#about to read 5, iclass 38, count 2 2006.257.09:00:57.32#ibcon#read 5, iclass 38, count 2 2006.257.09:00:57.32#ibcon#about to read 6, iclass 38, count 2 2006.257.09:00:57.32#ibcon#read 6, iclass 38, count 2 2006.257.09:00:57.32#ibcon#end of sib2, iclass 38, count 2 2006.257.09:00:57.32#ibcon#*after write, iclass 38, count 2 2006.257.09:00:57.32#ibcon#*before return 0, iclass 38, count 2 2006.257.09:00:57.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:00:57.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:00:57.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.09:00:57.32#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:57.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:00:57.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:00:57.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:00:57.44#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:00:57.44#ibcon#first serial, iclass 38, count 0 2006.257.09:00:57.44#ibcon#enter sib2, iclass 38, count 0 2006.257.09:00:57.44#ibcon#flushed, iclass 38, count 0 2006.257.09:00:57.44#ibcon#about to write, iclass 38, count 0 2006.257.09:00:57.44#ibcon#wrote, iclass 38, count 0 2006.257.09:00:57.44#ibcon#about to read 3, iclass 38, count 0 2006.257.09:00:57.46#ibcon#read 3, iclass 38, count 0 2006.257.09:00:57.46#ibcon#about to read 4, iclass 38, count 0 2006.257.09:00:57.46#ibcon#read 4, iclass 38, count 0 2006.257.09:00:57.46#ibcon#about to read 5, iclass 38, count 0 2006.257.09:00:57.46#ibcon#read 5, iclass 38, count 0 2006.257.09:00:57.46#ibcon#about to read 6, iclass 38, count 0 2006.257.09:00:57.46#ibcon#read 6, iclass 38, count 0 2006.257.09:00:57.46#ibcon#end of sib2, iclass 38, count 0 2006.257.09:00:57.46#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:00:57.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:00:57.46#ibcon#[25=USB\r\n] 2006.257.09:00:57.46#ibcon#*before write, iclass 38, count 0 2006.257.09:00:57.46#ibcon#enter sib2, iclass 38, count 0 2006.257.09:00:57.46#ibcon#flushed, iclass 38, count 0 2006.257.09:00:57.46#ibcon#about to write, iclass 38, count 0 2006.257.09:00:57.46#ibcon#wrote, iclass 38, count 0 2006.257.09:00:57.46#ibcon#about to read 3, iclass 38, count 0 2006.257.09:00:57.49#ibcon#read 3, iclass 38, count 0 2006.257.09:00:57.49#ibcon#about to read 4, iclass 38, count 0 2006.257.09:00:57.49#ibcon#read 4, iclass 38, count 0 2006.257.09:00:57.49#ibcon#about to read 5, iclass 38, count 0 2006.257.09:00:57.49#ibcon#read 5, iclass 38, count 0 2006.257.09:00:57.49#ibcon#about to read 6, iclass 38, count 0 2006.257.09:00:57.49#ibcon#read 6, iclass 38, count 0 2006.257.09:00:57.49#ibcon#end of sib2, iclass 38, count 0 2006.257.09:00:57.49#ibcon#*after write, iclass 38, count 0 2006.257.09:00:57.49#ibcon#*before return 0, iclass 38, count 0 2006.257.09:00:57.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:00:57.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:00:57.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:00:57.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:00:57.49$vck44/valo=5,734.99 2006.257.09:00:57.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.09:00:57.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.09:00:57.49#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:57.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:00:57.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:00:57.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:00:57.49#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:00:57.49#ibcon#first serial, iclass 40, count 0 2006.257.09:00:57.49#ibcon#enter sib2, iclass 40, count 0 2006.257.09:00:57.49#ibcon#flushed, iclass 40, count 0 2006.257.09:00:57.49#ibcon#about to write, iclass 40, count 0 2006.257.09:00:57.49#ibcon#wrote, iclass 40, count 0 2006.257.09:00:57.49#ibcon#about to read 3, iclass 40, count 0 2006.257.09:00:57.51#ibcon#read 3, iclass 40, count 0 2006.257.09:00:57.51#ibcon#about to read 4, iclass 40, count 0 2006.257.09:00:57.51#ibcon#read 4, iclass 40, count 0 2006.257.09:00:57.51#ibcon#about to read 5, iclass 40, count 0 2006.257.09:00:57.51#ibcon#read 5, iclass 40, count 0 2006.257.09:00:57.51#ibcon#about to read 6, iclass 40, count 0 2006.257.09:00:57.51#ibcon#read 6, iclass 40, count 0 2006.257.09:00:57.51#ibcon#end of sib2, iclass 40, count 0 2006.257.09:00:57.51#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:00:57.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:00:57.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:00:57.51#ibcon#*before write, iclass 40, count 0 2006.257.09:00:57.51#ibcon#enter sib2, iclass 40, count 0 2006.257.09:00:57.51#ibcon#flushed, iclass 40, count 0 2006.257.09:00:57.51#ibcon#about to write, iclass 40, count 0 2006.257.09:00:57.51#ibcon#wrote, iclass 40, count 0 2006.257.09:00:57.51#ibcon#about to read 3, iclass 40, count 0 2006.257.09:00:57.55#ibcon#read 3, iclass 40, count 0 2006.257.09:00:57.55#ibcon#about to read 4, iclass 40, count 0 2006.257.09:00:57.55#ibcon#read 4, iclass 40, count 0 2006.257.09:00:57.55#ibcon#about to read 5, iclass 40, count 0 2006.257.09:00:57.55#ibcon#read 5, iclass 40, count 0 2006.257.09:00:57.55#ibcon#about to read 6, iclass 40, count 0 2006.257.09:00:57.55#ibcon#read 6, iclass 40, count 0 2006.257.09:00:57.55#ibcon#end of sib2, iclass 40, count 0 2006.257.09:00:57.55#ibcon#*after write, iclass 40, count 0 2006.257.09:00:57.55#ibcon#*before return 0, iclass 40, count 0 2006.257.09:00:57.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:00:57.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:00:57.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:00:57.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:00:57.55$vck44/va=5,4 2006.257.09:00:57.55#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.09:00:57.55#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.09:00:57.55#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:57.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:00:57.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:00:57.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:00:57.61#ibcon#enter wrdev, iclass 4, count 2 2006.257.09:00:57.61#ibcon#first serial, iclass 4, count 2 2006.257.09:00:57.61#ibcon#enter sib2, iclass 4, count 2 2006.257.09:00:57.61#ibcon#flushed, iclass 4, count 2 2006.257.09:00:57.61#ibcon#about to write, iclass 4, count 2 2006.257.09:00:57.61#ibcon#wrote, iclass 4, count 2 2006.257.09:00:57.61#ibcon#about to read 3, iclass 4, count 2 2006.257.09:00:57.63#ibcon#read 3, iclass 4, count 2 2006.257.09:00:57.63#ibcon#about to read 4, iclass 4, count 2 2006.257.09:00:57.63#ibcon#read 4, iclass 4, count 2 2006.257.09:00:57.63#ibcon#about to read 5, iclass 4, count 2 2006.257.09:00:57.63#ibcon#read 5, iclass 4, count 2 2006.257.09:00:57.63#ibcon#about to read 6, iclass 4, count 2 2006.257.09:00:57.63#ibcon#read 6, iclass 4, count 2 2006.257.09:00:57.63#ibcon#end of sib2, iclass 4, count 2 2006.257.09:00:57.63#ibcon#*mode == 0, iclass 4, count 2 2006.257.09:00:57.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.09:00:57.63#ibcon#[25=AT05-04\r\n] 2006.257.09:00:57.63#ibcon#*before write, iclass 4, count 2 2006.257.09:00:57.63#ibcon#enter sib2, iclass 4, count 2 2006.257.09:00:57.63#ibcon#flushed, iclass 4, count 2 2006.257.09:00:57.63#ibcon#about to write, iclass 4, count 2 2006.257.09:00:57.63#ibcon#wrote, iclass 4, count 2 2006.257.09:00:57.63#ibcon#about to read 3, iclass 4, count 2 2006.257.09:00:57.66#ibcon#read 3, iclass 4, count 2 2006.257.09:00:57.66#ibcon#about to read 4, iclass 4, count 2 2006.257.09:00:57.66#ibcon#read 4, iclass 4, count 2 2006.257.09:00:57.66#ibcon#about to read 5, iclass 4, count 2 2006.257.09:00:57.66#ibcon#read 5, iclass 4, count 2 2006.257.09:00:57.66#ibcon#about to read 6, iclass 4, count 2 2006.257.09:00:57.66#ibcon#read 6, iclass 4, count 2 2006.257.09:00:57.66#ibcon#end of sib2, iclass 4, count 2 2006.257.09:00:57.66#ibcon#*after write, iclass 4, count 2 2006.257.09:00:57.66#ibcon#*before return 0, iclass 4, count 2 2006.257.09:00:57.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:00:57.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:00:57.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.09:00:57.66#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:57.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:00:57.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:00:57.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:00:57.78#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:00:57.78#ibcon#first serial, iclass 4, count 0 2006.257.09:00:57.78#ibcon#enter sib2, iclass 4, count 0 2006.257.09:00:57.78#ibcon#flushed, iclass 4, count 0 2006.257.09:00:57.78#ibcon#about to write, iclass 4, count 0 2006.257.09:00:57.78#ibcon#wrote, iclass 4, count 0 2006.257.09:00:57.78#ibcon#about to read 3, iclass 4, count 0 2006.257.09:00:57.80#ibcon#read 3, iclass 4, count 0 2006.257.09:00:57.80#ibcon#about to read 4, iclass 4, count 0 2006.257.09:00:57.80#ibcon#read 4, iclass 4, count 0 2006.257.09:00:57.80#ibcon#about to read 5, iclass 4, count 0 2006.257.09:00:57.80#ibcon#read 5, iclass 4, count 0 2006.257.09:00:57.80#ibcon#about to read 6, iclass 4, count 0 2006.257.09:00:57.80#ibcon#read 6, iclass 4, count 0 2006.257.09:00:57.80#ibcon#end of sib2, iclass 4, count 0 2006.257.09:00:57.80#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:00:57.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:00:57.80#ibcon#[25=USB\r\n] 2006.257.09:00:57.80#ibcon#*before write, iclass 4, count 0 2006.257.09:00:57.80#ibcon#enter sib2, iclass 4, count 0 2006.257.09:00:57.80#ibcon#flushed, iclass 4, count 0 2006.257.09:00:57.80#ibcon#about to write, iclass 4, count 0 2006.257.09:00:57.80#ibcon#wrote, iclass 4, count 0 2006.257.09:00:57.80#ibcon#about to read 3, iclass 4, count 0 2006.257.09:00:57.83#ibcon#read 3, iclass 4, count 0 2006.257.09:00:57.83#ibcon#about to read 4, iclass 4, count 0 2006.257.09:00:57.83#ibcon#read 4, iclass 4, count 0 2006.257.09:00:57.83#ibcon#about to read 5, iclass 4, count 0 2006.257.09:00:57.83#ibcon#read 5, iclass 4, count 0 2006.257.09:00:57.83#ibcon#about to read 6, iclass 4, count 0 2006.257.09:00:57.83#ibcon#read 6, iclass 4, count 0 2006.257.09:00:57.83#ibcon#end of sib2, iclass 4, count 0 2006.257.09:00:57.83#ibcon#*after write, iclass 4, count 0 2006.257.09:00:57.83#ibcon#*before return 0, iclass 4, count 0 2006.257.09:00:57.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:00:57.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:00:57.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:00:57.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:00:57.83$vck44/valo=6,814.99 2006.257.09:00:57.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.09:00:57.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.09:00:57.83#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:57.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:00:57.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:00:57.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:00:57.83#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:00:57.83#ibcon#first serial, iclass 6, count 0 2006.257.09:00:57.83#ibcon#enter sib2, iclass 6, count 0 2006.257.09:00:57.83#ibcon#flushed, iclass 6, count 0 2006.257.09:00:57.83#ibcon#about to write, iclass 6, count 0 2006.257.09:00:57.83#ibcon#wrote, iclass 6, count 0 2006.257.09:00:57.83#ibcon#about to read 3, iclass 6, count 0 2006.257.09:00:57.85#ibcon#read 3, iclass 6, count 0 2006.257.09:00:57.85#ibcon#about to read 4, iclass 6, count 0 2006.257.09:00:57.85#ibcon#read 4, iclass 6, count 0 2006.257.09:00:57.85#ibcon#about to read 5, iclass 6, count 0 2006.257.09:00:57.85#ibcon#read 5, iclass 6, count 0 2006.257.09:00:57.85#ibcon#about to read 6, iclass 6, count 0 2006.257.09:00:57.85#ibcon#read 6, iclass 6, count 0 2006.257.09:00:57.85#ibcon#end of sib2, iclass 6, count 0 2006.257.09:00:57.85#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:00:57.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:00:57.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:00:57.85#ibcon#*before write, iclass 6, count 0 2006.257.09:00:57.85#ibcon#enter sib2, iclass 6, count 0 2006.257.09:00:57.85#ibcon#flushed, iclass 6, count 0 2006.257.09:00:57.85#ibcon#about to write, iclass 6, count 0 2006.257.09:00:57.85#ibcon#wrote, iclass 6, count 0 2006.257.09:00:57.85#ibcon#about to read 3, iclass 6, count 0 2006.257.09:00:57.89#ibcon#read 3, iclass 6, count 0 2006.257.09:00:57.89#ibcon#about to read 4, iclass 6, count 0 2006.257.09:00:57.89#ibcon#read 4, iclass 6, count 0 2006.257.09:00:57.89#ibcon#about to read 5, iclass 6, count 0 2006.257.09:00:57.89#ibcon#read 5, iclass 6, count 0 2006.257.09:00:57.89#ibcon#about to read 6, iclass 6, count 0 2006.257.09:00:57.89#ibcon#read 6, iclass 6, count 0 2006.257.09:00:57.89#ibcon#end of sib2, iclass 6, count 0 2006.257.09:00:57.89#ibcon#*after write, iclass 6, count 0 2006.257.09:00:57.89#ibcon#*before return 0, iclass 6, count 0 2006.257.09:00:57.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:00:57.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:00:57.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:00:57.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:00:57.89$vck44/va=6,4 2006.257.09:00:57.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.09:00:57.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.09:00:57.89#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:57.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:00:57.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:00:57.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:00:57.95#ibcon#enter wrdev, iclass 10, count 2 2006.257.09:00:57.95#ibcon#first serial, iclass 10, count 2 2006.257.09:00:57.95#ibcon#enter sib2, iclass 10, count 2 2006.257.09:00:57.95#ibcon#flushed, iclass 10, count 2 2006.257.09:00:57.95#ibcon#about to write, iclass 10, count 2 2006.257.09:00:57.95#ibcon#wrote, iclass 10, count 2 2006.257.09:00:57.95#ibcon#about to read 3, iclass 10, count 2 2006.257.09:00:57.97#ibcon#read 3, iclass 10, count 2 2006.257.09:00:57.97#ibcon#about to read 4, iclass 10, count 2 2006.257.09:00:57.97#ibcon#read 4, iclass 10, count 2 2006.257.09:00:57.97#ibcon#about to read 5, iclass 10, count 2 2006.257.09:00:57.97#ibcon#read 5, iclass 10, count 2 2006.257.09:00:57.97#ibcon#about to read 6, iclass 10, count 2 2006.257.09:00:57.97#ibcon#read 6, iclass 10, count 2 2006.257.09:00:57.97#ibcon#end of sib2, iclass 10, count 2 2006.257.09:00:57.97#ibcon#*mode == 0, iclass 10, count 2 2006.257.09:00:57.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.09:00:57.97#ibcon#[25=AT06-04\r\n] 2006.257.09:00:57.97#ibcon#*before write, iclass 10, count 2 2006.257.09:00:57.97#ibcon#enter sib2, iclass 10, count 2 2006.257.09:00:57.97#ibcon#flushed, iclass 10, count 2 2006.257.09:00:57.97#ibcon#about to write, iclass 10, count 2 2006.257.09:00:57.97#ibcon#wrote, iclass 10, count 2 2006.257.09:00:57.97#ibcon#about to read 3, iclass 10, count 2 2006.257.09:00:58.00#ibcon#read 3, iclass 10, count 2 2006.257.09:00:58.00#ibcon#about to read 4, iclass 10, count 2 2006.257.09:00:58.00#ibcon#read 4, iclass 10, count 2 2006.257.09:00:58.00#ibcon#about to read 5, iclass 10, count 2 2006.257.09:00:58.00#ibcon#read 5, iclass 10, count 2 2006.257.09:00:58.00#ibcon#about to read 6, iclass 10, count 2 2006.257.09:00:58.00#ibcon#read 6, iclass 10, count 2 2006.257.09:00:58.00#ibcon#end of sib2, iclass 10, count 2 2006.257.09:00:58.00#ibcon#*after write, iclass 10, count 2 2006.257.09:00:58.00#ibcon#*before return 0, iclass 10, count 2 2006.257.09:00:58.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:00:58.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:00:58.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.09:00:58.00#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:58.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:00:58.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:00:58.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:00:58.12#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:00:58.12#ibcon#first serial, iclass 10, count 0 2006.257.09:00:58.12#ibcon#enter sib2, iclass 10, count 0 2006.257.09:00:58.12#ibcon#flushed, iclass 10, count 0 2006.257.09:00:58.12#ibcon#about to write, iclass 10, count 0 2006.257.09:00:58.12#ibcon#wrote, iclass 10, count 0 2006.257.09:00:58.12#ibcon#about to read 3, iclass 10, count 0 2006.257.09:00:58.14#ibcon#read 3, iclass 10, count 0 2006.257.09:00:58.14#ibcon#about to read 4, iclass 10, count 0 2006.257.09:00:58.14#ibcon#read 4, iclass 10, count 0 2006.257.09:00:58.14#ibcon#about to read 5, iclass 10, count 0 2006.257.09:00:58.14#ibcon#read 5, iclass 10, count 0 2006.257.09:00:58.14#ibcon#about to read 6, iclass 10, count 0 2006.257.09:00:58.14#ibcon#read 6, iclass 10, count 0 2006.257.09:00:58.14#ibcon#end of sib2, iclass 10, count 0 2006.257.09:00:58.14#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:00:58.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:00:58.14#ibcon#[25=USB\r\n] 2006.257.09:00:58.14#ibcon#*before write, iclass 10, count 0 2006.257.09:00:58.14#ibcon#enter sib2, iclass 10, count 0 2006.257.09:00:58.14#ibcon#flushed, iclass 10, count 0 2006.257.09:00:58.14#ibcon#about to write, iclass 10, count 0 2006.257.09:00:58.14#ibcon#wrote, iclass 10, count 0 2006.257.09:00:58.14#ibcon#about to read 3, iclass 10, count 0 2006.257.09:00:58.17#ibcon#read 3, iclass 10, count 0 2006.257.09:00:58.17#ibcon#about to read 4, iclass 10, count 0 2006.257.09:00:58.17#ibcon#read 4, iclass 10, count 0 2006.257.09:00:58.17#ibcon#about to read 5, iclass 10, count 0 2006.257.09:00:58.17#ibcon#read 5, iclass 10, count 0 2006.257.09:00:58.17#ibcon#about to read 6, iclass 10, count 0 2006.257.09:00:58.17#ibcon#read 6, iclass 10, count 0 2006.257.09:00:58.17#ibcon#end of sib2, iclass 10, count 0 2006.257.09:00:58.17#ibcon#*after write, iclass 10, count 0 2006.257.09:00:58.17#ibcon#*before return 0, iclass 10, count 0 2006.257.09:00:58.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:00:58.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:00:58.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:00:58.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:00:58.17$vck44/valo=7,864.99 2006.257.09:00:58.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.09:00:58.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.09:00:58.17#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:58.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:00:58.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:00:58.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:00:58.17#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:00:58.17#ibcon#first serial, iclass 12, count 0 2006.257.09:00:58.17#ibcon#enter sib2, iclass 12, count 0 2006.257.09:00:58.17#ibcon#flushed, iclass 12, count 0 2006.257.09:00:58.17#ibcon#about to write, iclass 12, count 0 2006.257.09:00:58.17#ibcon#wrote, iclass 12, count 0 2006.257.09:00:58.17#ibcon#about to read 3, iclass 12, count 0 2006.257.09:00:58.19#ibcon#read 3, iclass 12, count 0 2006.257.09:00:58.19#ibcon#about to read 4, iclass 12, count 0 2006.257.09:00:58.19#ibcon#read 4, iclass 12, count 0 2006.257.09:00:58.19#ibcon#about to read 5, iclass 12, count 0 2006.257.09:00:58.19#ibcon#read 5, iclass 12, count 0 2006.257.09:00:58.19#ibcon#about to read 6, iclass 12, count 0 2006.257.09:00:58.19#ibcon#read 6, iclass 12, count 0 2006.257.09:00:58.19#ibcon#end of sib2, iclass 12, count 0 2006.257.09:00:58.19#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:00:58.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:00:58.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:00:58.19#ibcon#*before write, iclass 12, count 0 2006.257.09:00:58.19#ibcon#enter sib2, iclass 12, count 0 2006.257.09:00:58.19#ibcon#flushed, iclass 12, count 0 2006.257.09:00:58.19#ibcon#about to write, iclass 12, count 0 2006.257.09:00:58.19#ibcon#wrote, iclass 12, count 0 2006.257.09:00:58.19#ibcon#about to read 3, iclass 12, count 0 2006.257.09:00:58.23#ibcon#read 3, iclass 12, count 0 2006.257.09:00:58.23#ibcon#about to read 4, iclass 12, count 0 2006.257.09:00:58.23#ibcon#read 4, iclass 12, count 0 2006.257.09:00:58.23#ibcon#about to read 5, iclass 12, count 0 2006.257.09:00:58.23#ibcon#read 5, iclass 12, count 0 2006.257.09:00:58.23#ibcon#about to read 6, iclass 12, count 0 2006.257.09:00:58.23#ibcon#read 6, iclass 12, count 0 2006.257.09:00:58.23#ibcon#end of sib2, iclass 12, count 0 2006.257.09:00:58.23#ibcon#*after write, iclass 12, count 0 2006.257.09:00:58.23#ibcon#*before return 0, iclass 12, count 0 2006.257.09:00:58.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:00:58.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:00:58.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:00:58.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:00:58.23$vck44/va=7,4 2006.257.09:00:58.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.09:00:58.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.09:00:58.23#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:58.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:00:58.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:00:58.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:00:58.29#ibcon#enter wrdev, iclass 14, count 2 2006.257.09:00:58.29#ibcon#first serial, iclass 14, count 2 2006.257.09:00:58.29#ibcon#enter sib2, iclass 14, count 2 2006.257.09:00:58.29#ibcon#flushed, iclass 14, count 2 2006.257.09:00:58.29#ibcon#about to write, iclass 14, count 2 2006.257.09:00:58.29#ibcon#wrote, iclass 14, count 2 2006.257.09:00:58.29#ibcon#about to read 3, iclass 14, count 2 2006.257.09:00:58.31#ibcon#read 3, iclass 14, count 2 2006.257.09:00:58.31#ibcon#about to read 4, iclass 14, count 2 2006.257.09:00:58.31#ibcon#read 4, iclass 14, count 2 2006.257.09:00:58.31#ibcon#about to read 5, iclass 14, count 2 2006.257.09:00:58.31#ibcon#read 5, iclass 14, count 2 2006.257.09:00:58.31#ibcon#about to read 6, iclass 14, count 2 2006.257.09:00:58.31#ibcon#read 6, iclass 14, count 2 2006.257.09:00:58.31#ibcon#end of sib2, iclass 14, count 2 2006.257.09:00:58.31#ibcon#*mode == 0, iclass 14, count 2 2006.257.09:00:58.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.09:00:58.31#ibcon#[25=AT07-04\r\n] 2006.257.09:00:58.31#ibcon#*before write, iclass 14, count 2 2006.257.09:00:58.31#ibcon#enter sib2, iclass 14, count 2 2006.257.09:00:58.31#ibcon#flushed, iclass 14, count 2 2006.257.09:00:58.31#ibcon#about to write, iclass 14, count 2 2006.257.09:00:58.31#ibcon#wrote, iclass 14, count 2 2006.257.09:00:58.31#ibcon#about to read 3, iclass 14, count 2 2006.257.09:00:58.34#ibcon#read 3, iclass 14, count 2 2006.257.09:00:58.34#ibcon#about to read 4, iclass 14, count 2 2006.257.09:00:58.34#ibcon#read 4, iclass 14, count 2 2006.257.09:00:58.34#ibcon#about to read 5, iclass 14, count 2 2006.257.09:00:58.34#ibcon#read 5, iclass 14, count 2 2006.257.09:00:58.34#ibcon#about to read 6, iclass 14, count 2 2006.257.09:00:58.34#ibcon#read 6, iclass 14, count 2 2006.257.09:00:58.34#ibcon#end of sib2, iclass 14, count 2 2006.257.09:00:58.34#ibcon#*after write, iclass 14, count 2 2006.257.09:00:58.34#ibcon#*before return 0, iclass 14, count 2 2006.257.09:00:58.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:00:58.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:00:58.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.09:00:58.34#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:58.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:00:58.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:00:58.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:00:58.46#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:00:58.46#ibcon#first serial, iclass 14, count 0 2006.257.09:00:58.46#ibcon#enter sib2, iclass 14, count 0 2006.257.09:00:58.46#ibcon#flushed, iclass 14, count 0 2006.257.09:00:58.46#ibcon#about to write, iclass 14, count 0 2006.257.09:00:58.46#ibcon#wrote, iclass 14, count 0 2006.257.09:00:58.46#ibcon#about to read 3, iclass 14, count 0 2006.257.09:00:58.48#ibcon#read 3, iclass 14, count 0 2006.257.09:00:58.48#ibcon#about to read 4, iclass 14, count 0 2006.257.09:00:58.48#ibcon#read 4, iclass 14, count 0 2006.257.09:00:58.48#ibcon#about to read 5, iclass 14, count 0 2006.257.09:00:58.48#ibcon#read 5, iclass 14, count 0 2006.257.09:00:58.48#ibcon#about to read 6, iclass 14, count 0 2006.257.09:00:58.48#ibcon#read 6, iclass 14, count 0 2006.257.09:00:58.48#ibcon#end of sib2, iclass 14, count 0 2006.257.09:00:58.48#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:00:58.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:00:58.48#ibcon#[25=USB\r\n] 2006.257.09:00:58.48#ibcon#*before write, iclass 14, count 0 2006.257.09:00:58.48#ibcon#enter sib2, iclass 14, count 0 2006.257.09:00:58.48#ibcon#flushed, iclass 14, count 0 2006.257.09:00:58.48#ibcon#about to write, iclass 14, count 0 2006.257.09:00:58.48#ibcon#wrote, iclass 14, count 0 2006.257.09:00:58.48#ibcon#about to read 3, iclass 14, count 0 2006.257.09:00:58.51#ibcon#read 3, iclass 14, count 0 2006.257.09:00:58.51#ibcon#about to read 4, iclass 14, count 0 2006.257.09:00:58.51#ibcon#read 4, iclass 14, count 0 2006.257.09:00:58.51#ibcon#about to read 5, iclass 14, count 0 2006.257.09:00:58.51#ibcon#read 5, iclass 14, count 0 2006.257.09:00:58.51#ibcon#about to read 6, iclass 14, count 0 2006.257.09:00:58.51#ibcon#read 6, iclass 14, count 0 2006.257.09:00:58.51#ibcon#end of sib2, iclass 14, count 0 2006.257.09:00:58.51#ibcon#*after write, iclass 14, count 0 2006.257.09:00:58.51#ibcon#*before return 0, iclass 14, count 0 2006.257.09:00:58.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:00:58.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:00:58.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:00:58.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:00:58.51$vck44/valo=8,884.99 2006.257.09:00:58.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.09:00:58.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.09:00:58.51#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:58.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:00:58.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:00:58.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:00:58.51#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:00:58.51#ibcon#first serial, iclass 16, count 0 2006.257.09:00:58.51#ibcon#enter sib2, iclass 16, count 0 2006.257.09:00:58.51#ibcon#flushed, iclass 16, count 0 2006.257.09:00:58.51#ibcon#about to write, iclass 16, count 0 2006.257.09:00:58.51#ibcon#wrote, iclass 16, count 0 2006.257.09:00:58.51#ibcon#about to read 3, iclass 16, count 0 2006.257.09:00:58.53#ibcon#read 3, iclass 16, count 0 2006.257.09:00:58.53#ibcon#about to read 4, iclass 16, count 0 2006.257.09:00:58.53#ibcon#read 4, iclass 16, count 0 2006.257.09:00:58.53#ibcon#about to read 5, iclass 16, count 0 2006.257.09:00:58.53#ibcon#read 5, iclass 16, count 0 2006.257.09:00:58.53#ibcon#about to read 6, iclass 16, count 0 2006.257.09:00:58.53#ibcon#read 6, iclass 16, count 0 2006.257.09:00:58.53#ibcon#end of sib2, iclass 16, count 0 2006.257.09:00:58.53#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:00:58.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:00:58.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:00:58.53#ibcon#*before write, iclass 16, count 0 2006.257.09:00:58.53#ibcon#enter sib2, iclass 16, count 0 2006.257.09:00:58.53#ibcon#flushed, iclass 16, count 0 2006.257.09:00:58.53#ibcon#about to write, iclass 16, count 0 2006.257.09:00:58.53#ibcon#wrote, iclass 16, count 0 2006.257.09:00:58.53#ibcon#about to read 3, iclass 16, count 0 2006.257.09:00:58.57#ibcon#read 3, iclass 16, count 0 2006.257.09:00:58.57#ibcon#about to read 4, iclass 16, count 0 2006.257.09:00:58.57#ibcon#read 4, iclass 16, count 0 2006.257.09:00:58.57#ibcon#about to read 5, iclass 16, count 0 2006.257.09:00:58.57#ibcon#read 5, iclass 16, count 0 2006.257.09:00:58.57#ibcon#about to read 6, iclass 16, count 0 2006.257.09:00:58.57#ibcon#read 6, iclass 16, count 0 2006.257.09:00:58.57#ibcon#end of sib2, iclass 16, count 0 2006.257.09:00:58.57#ibcon#*after write, iclass 16, count 0 2006.257.09:00:58.57#ibcon#*before return 0, iclass 16, count 0 2006.257.09:00:58.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:00:58.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:00:58.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:00:58.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:00:58.57$vck44/va=8,4 2006.257.09:00:58.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.09:00:58.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.09:00:58.57#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:58.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:00:58.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:00:58.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:00:58.63#ibcon#enter wrdev, iclass 18, count 2 2006.257.09:00:58.63#ibcon#first serial, iclass 18, count 2 2006.257.09:00:58.63#ibcon#enter sib2, iclass 18, count 2 2006.257.09:00:58.63#ibcon#flushed, iclass 18, count 2 2006.257.09:00:58.63#ibcon#about to write, iclass 18, count 2 2006.257.09:00:58.63#ibcon#wrote, iclass 18, count 2 2006.257.09:00:58.63#ibcon#about to read 3, iclass 18, count 2 2006.257.09:00:58.65#ibcon#read 3, iclass 18, count 2 2006.257.09:00:58.65#ibcon#about to read 4, iclass 18, count 2 2006.257.09:00:58.65#ibcon#read 4, iclass 18, count 2 2006.257.09:00:58.65#ibcon#about to read 5, iclass 18, count 2 2006.257.09:00:58.65#ibcon#read 5, iclass 18, count 2 2006.257.09:00:58.65#ibcon#about to read 6, iclass 18, count 2 2006.257.09:00:58.65#ibcon#read 6, iclass 18, count 2 2006.257.09:00:58.65#ibcon#end of sib2, iclass 18, count 2 2006.257.09:00:58.65#ibcon#*mode == 0, iclass 18, count 2 2006.257.09:00:58.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.09:00:58.65#ibcon#[25=AT08-04\r\n] 2006.257.09:00:58.65#ibcon#*before write, iclass 18, count 2 2006.257.09:00:58.65#ibcon#enter sib2, iclass 18, count 2 2006.257.09:00:58.65#ibcon#flushed, iclass 18, count 2 2006.257.09:00:58.65#ibcon#about to write, iclass 18, count 2 2006.257.09:00:58.65#ibcon#wrote, iclass 18, count 2 2006.257.09:00:58.65#ibcon#about to read 3, iclass 18, count 2 2006.257.09:00:58.68#ibcon#read 3, iclass 18, count 2 2006.257.09:00:58.68#ibcon#about to read 4, iclass 18, count 2 2006.257.09:00:58.68#ibcon#read 4, iclass 18, count 2 2006.257.09:00:58.68#ibcon#about to read 5, iclass 18, count 2 2006.257.09:00:58.68#ibcon#read 5, iclass 18, count 2 2006.257.09:00:58.68#ibcon#about to read 6, iclass 18, count 2 2006.257.09:00:58.68#ibcon#read 6, iclass 18, count 2 2006.257.09:00:58.68#ibcon#end of sib2, iclass 18, count 2 2006.257.09:00:58.68#ibcon#*after write, iclass 18, count 2 2006.257.09:00:58.68#ibcon#*before return 0, iclass 18, count 2 2006.257.09:00:58.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:00:58.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:00:58.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.09:00:58.68#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:58.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:00:58.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:00:58.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:00:58.80#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:00:58.80#ibcon#first serial, iclass 18, count 0 2006.257.09:00:58.80#ibcon#enter sib2, iclass 18, count 0 2006.257.09:00:58.80#ibcon#flushed, iclass 18, count 0 2006.257.09:00:58.80#ibcon#about to write, iclass 18, count 0 2006.257.09:00:58.80#ibcon#wrote, iclass 18, count 0 2006.257.09:00:58.80#ibcon#about to read 3, iclass 18, count 0 2006.257.09:00:58.82#ibcon#read 3, iclass 18, count 0 2006.257.09:00:58.82#ibcon#about to read 4, iclass 18, count 0 2006.257.09:00:58.82#ibcon#read 4, iclass 18, count 0 2006.257.09:00:58.82#ibcon#about to read 5, iclass 18, count 0 2006.257.09:00:58.82#ibcon#read 5, iclass 18, count 0 2006.257.09:00:58.82#ibcon#about to read 6, iclass 18, count 0 2006.257.09:00:58.82#ibcon#read 6, iclass 18, count 0 2006.257.09:00:58.82#ibcon#end of sib2, iclass 18, count 0 2006.257.09:00:58.82#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:00:58.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:00:58.82#ibcon#[25=USB\r\n] 2006.257.09:00:58.82#ibcon#*before write, iclass 18, count 0 2006.257.09:00:58.82#ibcon#enter sib2, iclass 18, count 0 2006.257.09:00:58.82#ibcon#flushed, iclass 18, count 0 2006.257.09:00:58.82#ibcon#about to write, iclass 18, count 0 2006.257.09:00:58.82#ibcon#wrote, iclass 18, count 0 2006.257.09:00:58.82#ibcon#about to read 3, iclass 18, count 0 2006.257.09:00:58.85#ibcon#read 3, iclass 18, count 0 2006.257.09:00:58.85#ibcon#about to read 4, iclass 18, count 0 2006.257.09:00:58.85#ibcon#read 4, iclass 18, count 0 2006.257.09:00:58.85#ibcon#about to read 5, iclass 18, count 0 2006.257.09:00:58.85#ibcon#read 5, iclass 18, count 0 2006.257.09:00:58.85#ibcon#about to read 6, iclass 18, count 0 2006.257.09:00:58.85#ibcon#read 6, iclass 18, count 0 2006.257.09:00:58.85#ibcon#end of sib2, iclass 18, count 0 2006.257.09:00:58.85#ibcon#*after write, iclass 18, count 0 2006.257.09:00:58.85#ibcon#*before return 0, iclass 18, count 0 2006.257.09:00:58.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:00:58.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:00:58.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:00:58.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:00:58.85$vck44/vblo=1,629.99 2006.257.09:00:58.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.09:00:58.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.09:00:58.85#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:58.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:00:58.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:00:58.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:00:58.85#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:00:58.85#ibcon#first serial, iclass 20, count 0 2006.257.09:00:58.85#ibcon#enter sib2, iclass 20, count 0 2006.257.09:00:58.85#ibcon#flushed, iclass 20, count 0 2006.257.09:00:58.85#ibcon#about to write, iclass 20, count 0 2006.257.09:00:58.85#ibcon#wrote, iclass 20, count 0 2006.257.09:00:58.85#ibcon#about to read 3, iclass 20, count 0 2006.257.09:00:58.87#ibcon#read 3, iclass 20, count 0 2006.257.09:00:58.87#ibcon#about to read 4, iclass 20, count 0 2006.257.09:00:58.87#ibcon#read 4, iclass 20, count 0 2006.257.09:00:58.87#ibcon#about to read 5, iclass 20, count 0 2006.257.09:00:58.87#ibcon#read 5, iclass 20, count 0 2006.257.09:00:58.87#ibcon#about to read 6, iclass 20, count 0 2006.257.09:00:58.87#ibcon#read 6, iclass 20, count 0 2006.257.09:00:58.87#ibcon#end of sib2, iclass 20, count 0 2006.257.09:00:58.87#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:00:58.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:00:58.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:00:58.87#ibcon#*before write, iclass 20, count 0 2006.257.09:00:58.87#ibcon#enter sib2, iclass 20, count 0 2006.257.09:00:58.87#ibcon#flushed, iclass 20, count 0 2006.257.09:00:58.87#ibcon#about to write, iclass 20, count 0 2006.257.09:00:58.87#ibcon#wrote, iclass 20, count 0 2006.257.09:00:58.87#ibcon#about to read 3, iclass 20, count 0 2006.257.09:00:58.91#ibcon#read 3, iclass 20, count 0 2006.257.09:00:58.91#ibcon#about to read 4, iclass 20, count 0 2006.257.09:00:58.91#ibcon#read 4, iclass 20, count 0 2006.257.09:00:58.91#ibcon#about to read 5, iclass 20, count 0 2006.257.09:00:58.91#ibcon#read 5, iclass 20, count 0 2006.257.09:00:58.91#ibcon#about to read 6, iclass 20, count 0 2006.257.09:00:58.91#ibcon#read 6, iclass 20, count 0 2006.257.09:00:58.91#ibcon#end of sib2, iclass 20, count 0 2006.257.09:00:58.91#ibcon#*after write, iclass 20, count 0 2006.257.09:00:58.91#ibcon#*before return 0, iclass 20, count 0 2006.257.09:00:58.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:00:58.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:00:58.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:00:58.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:00:58.91$vck44/vb=1,4 2006.257.09:00:58.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.09:00:58.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.09:00:58.91#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:58.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:00:58.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:00:58.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:00:58.91#ibcon#enter wrdev, iclass 22, count 2 2006.257.09:00:58.91#ibcon#first serial, iclass 22, count 2 2006.257.09:00:58.91#ibcon#enter sib2, iclass 22, count 2 2006.257.09:00:58.91#ibcon#flushed, iclass 22, count 2 2006.257.09:00:58.91#ibcon#about to write, iclass 22, count 2 2006.257.09:00:58.91#ibcon#wrote, iclass 22, count 2 2006.257.09:00:58.91#ibcon#about to read 3, iclass 22, count 2 2006.257.09:00:58.93#ibcon#read 3, iclass 22, count 2 2006.257.09:00:58.93#ibcon#about to read 4, iclass 22, count 2 2006.257.09:00:58.93#ibcon#read 4, iclass 22, count 2 2006.257.09:00:58.93#ibcon#about to read 5, iclass 22, count 2 2006.257.09:00:58.93#ibcon#read 5, iclass 22, count 2 2006.257.09:00:58.93#ibcon#about to read 6, iclass 22, count 2 2006.257.09:00:58.93#ibcon#read 6, iclass 22, count 2 2006.257.09:00:58.93#ibcon#end of sib2, iclass 22, count 2 2006.257.09:00:58.93#ibcon#*mode == 0, iclass 22, count 2 2006.257.09:00:58.93#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.09:00:58.93#ibcon#[27=AT01-04\r\n] 2006.257.09:00:58.93#ibcon#*before write, iclass 22, count 2 2006.257.09:00:58.93#ibcon#enter sib2, iclass 22, count 2 2006.257.09:00:58.93#ibcon#flushed, iclass 22, count 2 2006.257.09:00:58.93#ibcon#about to write, iclass 22, count 2 2006.257.09:00:58.93#ibcon#wrote, iclass 22, count 2 2006.257.09:00:58.93#ibcon#about to read 3, iclass 22, count 2 2006.257.09:00:58.96#ibcon#read 3, iclass 22, count 2 2006.257.09:00:58.96#ibcon#about to read 4, iclass 22, count 2 2006.257.09:00:58.96#ibcon#read 4, iclass 22, count 2 2006.257.09:00:58.96#ibcon#about to read 5, iclass 22, count 2 2006.257.09:00:58.96#ibcon#read 5, iclass 22, count 2 2006.257.09:00:58.96#ibcon#about to read 6, iclass 22, count 2 2006.257.09:00:58.96#ibcon#read 6, iclass 22, count 2 2006.257.09:00:58.96#ibcon#end of sib2, iclass 22, count 2 2006.257.09:00:58.96#ibcon#*after write, iclass 22, count 2 2006.257.09:00:58.96#ibcon#*before return 0, iclass 22, count 2 2006.257.09:00:58.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:00:58.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:00:58.96#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.09:00:58.96#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:58.96#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:00:59.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:00:59.08#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:00:59.08#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:00:59.08#ibcon#first serial, iclass 22, count 0 2006.257.09:00:59.08#ibcon#enter sib2, iclass 22, count 0 2006.257.09:00:59.08#ibcon#flushed, iclass 22, count 0 2006.257.09:00:59.08#ibcon#about to write, iclass 22, count 0 2006.257.09:00:59.08#ibcon#wrote, iclass 22, count 0 2006.257.09:00:59.08#ibcon#about to read 3, iclass 22, count 0 2006.257.09:00:59.10#ibcon#read 3, iclass 22, count 0 2006.257.09:00:59.10#ibcon#about to read 4, iclass 22, count 0 2006.257.09:00:59.10#ibcon#read 4, iclass 22, count 0 2006.257.09:00:59.10#ibcon#about to read 5, iclass 22, count 0 2006.257.09:00:59.10#ibcon#read 5, iclass 22, count 0 2006.257.09:00:59.10#ibcon#about to read 6, iclass 22, count 0 2006.257.09:00:59.10#ibcon#read 6, iclass 22, count 0 2006.257.09:00:59.10#ibcon#end of sib2, iclass 22, count 0 2006.257.09:00:59.10#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:00:59.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:00:59.10#ibcon#[27=USB\r\n] 2006.257.09:00:59.10#ibcon#*before write, iclass 22, count 0 2006.257.09:00:59.10#ibcon#enter sib2, iclass 22, count 0 2006.257.09:00:59.10#ibcon#flushed, iclass 22, count 0 2006.257.09:00:59.10#ibcon#about to write, iclass 22, count 0 2006.257.09:00:59.10#ibcon#wrote, iclass 22, count 0 2006.257.09:00:59.10#ibcon#about to read 3, iclass 22, count 0 2006.257.09:00:59.13#ibcon#read 3, iclass 22, count 0 2006.257.09:00:59.13#ibcon#about to read 4, iclass 22, count 0 2006.257.09:00:59.13#ibcon#read 4, iclass 22, count 0 2006.257.09:00:59.13#ibcon#about to read 5, iclass 22, count 0 2006.257.09:00:59.13#ibcon#read 5, iclass 22, count 0 2006.257.09:00:59.13#ibcon#about to read 6, iclass 22, count 0 2006.257.09:00:59.13#ibcon#read 6, iclass 22, count 0 2006.257.09:00:59.13#ibcon#end of sib2, iclass 22, count 0 2006.257.09:00:59.13#ibcon#*after write, iclass 22, count 0 2006.257.09:00:59.13#ibcon#*before return 0, iclass 22, count 0 2006.257.09:00:59.13#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:00:59.13#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:00:59.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:00:59.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:00:59.13$vck44/vblo=2,634.99 2006.257.09:00:59.13#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.09:00:59.13#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.09:00:59.13#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:59.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:59.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:59.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:59.13#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:00:59.13#ibcon#first serial, iclass 24, count 0 2006.257.09:00:59.13#ibcon#enter sib2, iclass 24, count 0 2006.257.09:00:59.13#ibcon#flushed, iclass 24, count 0 2006.257.09:00:59.13#ibcon#about to write, iclass 24, count 0 2006.257.09:00:59.13#ibcon#wrote, iclass 24, count 0 2006.257.09:00:59.13#ibcon#about to read 3, iclass 24, count 0 2006.257.09:00:59.15#ibcon#read 3, iclass 24, count 0 2006.257.09:00:59.15#ibcon#about to read 4, iclass 24, count 0 2006.257.09:00:59.15#ibcon#read 4, iclass 24, count 0 2006.257.09:00:59.15#ibcon#about to read 5, iclass 24, count 0 2006.257.09:00:59.15#ibcon#read 5, iclass 24, count 0 2006.257.09:00:59.15#ibcon#about to read 6, iclass 24, count 0 2006.257.09:00:59.15#ibcon#read 6, iclass 24, count 0 2006.257.09:00:59.15#ibcon#end of sib2, iclass 24, count 0 2006.257.09:00:59.15#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:00:59.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:00:59.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:00:59.15#ibcon#*before write, iclass 24, count 0 2006.257.09:00:59.15#ibcon#enter sib2, iclass 24, count 0 2006.257.09:00:59.15#ibcon#flushed, iclass 24, count 0 2006.257.09:00:59.15#ibcon#about to write, iclass 24, count 0 2006.257.09:00:59.15#ibcon#wrote, iclass 24, count 0 2006.257.09:00:59.15#ibcon#about to read 3, iclass 24, count 0 2006.257.09:00:59.19#ibcon#read 3, iclass 24, count 0 2006.257.09:00:59.19#ibcon#about to read 4, iclass 24, count 0 2006.257.09:00:59.19#ibcon#read 4, iclass 24, count 0 2006.257.09:00:59.19#ibcon#about to read 5, iclass 24, count 0 2006.257.09:00:59.19#ibcon#read 5, iclass 24, count 0 2006.257.09:00:59.19#ibcon#about to read 6, iclass 24, count 0 2006.257.09:00:59.19#ibcon#read 6, iclass 24, count 0 2006.257.09:00:59.19#ibcon#end of sib2, iclass 24, count 0 2006.257.09:00:59.19#ibcon#*after write, iclass 24, count 0 2006.257.09:00:59.19#ibcon#*before return 0, iclass 24, count 0 2006.257.09:00:59.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:59.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:00:59.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:00:59.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:00:59.19$vck44/vb=2,5 2006.257.09:00:59.19#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.09:00:59.19#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.09:00:59.19#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:59.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:59.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:59.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:59.25#ibcon#enter wrdev, iclass 26, count 2 2006.257.09:00:59.25#ibcon#first serial, iclass 26, count 2 2006.257.09:00:59.25#ibcon#enter sib2, iclass 26, count 2 2006.257.09:00:59.25#ibcon#flushed, iclass 26, count 2 2006.257.09:00:59.25#ibcon#about to write, iclass 26, count 2 2006.257.09:00:59.25#ibcon#wrote, iclass 26, count 2 2006.257.09:00:59.25#ibcon#about to read 3, iclass 26, count 2 2006.257.09:00:59.27#ibcon#read 3, iclass 26, count 2 2006.257.09:00:59.27#ibcon#about to read 4, iclass 26, count 2 2006.257.09:00:59.27#ibcon#read 4, iclass 26, count 2 2006.257.09:00:59.27#ibcon#about to read 5, iclass 26, count 2 2006.257.09:00:59.27#ibcon#read 5, iclass 26, count 2 2006.257.09:00:59.27#ibcon#about to read 6, iclass 26, count 2 2006.257.09:00:59.27#ibcon#read 6, iclass 26, count 2 2006.257.09:00:59.27#ibcon#end of sib2, iclass 26, count 2 2006.257.09:00:59.27#ibcon#*mode == 0, iclass 26, count 2 2006.257.09:00:59.27#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.09:00:59.27#ibcon#[27=AT02-05\r\n] 2006.257.09:00:59.27#ibcon#*before write, iclass 26, count 2 2006.257.09:00:59.27#ibcon#enter sib2, iclass 26, count 2 2006.257.09:00:59.27#ibcon#flushed, iclass 26, count 2 2006.257.09:00:59.27#ibcon#about to write, iclass 26, count 2 2006.257.09:00:59.28#ibcon#wrote, iclass 26, count 2 2006.257.09:00:59.28#ibcon#about to read 3, iclass 26, count 2 2006.257.09:00:59.31#ibcon#read 3, iclass 26, count 2 2006.257.09:00:59.31#ibcon#about to read 4, iclass 26, count 2 2006.257.09:00:59.31#ibcon#read 4, iclass 26, count 2 2006.257.09:00:59.31#ibcon#about to read 5, iclass 26, count 2 2006.257.09:00:59.31#ibcon#read 5, iclass 26, count 2 2006.257.09:00:59.31#ibcon#about to read 6, iclass 26, count 2 2006.257.09:00:59.31#ibcon#read 6, iclass 26, count 2 2006.257.09:00:59.31#ibcon#end of sib2, iclass 26, count 2 2006.257.09:00:59.31#ibcon#*after write, iclass 26, count 2 2006.257.09:00:59.31#ibcon#*before return 0, iclass 26, count 2 2006.257.09:00:59.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:59.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:00:59.31#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.09:00:59.31#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:59.31#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:59.43#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:59.43#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:59.43#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:00:59.43#ibcon#first serial, iclass 26, count 0 2006.257.09:00:59.43#ibcon#enter sib2, iclass 26, count 0 2006.257.09:00:59.43#ibcon#flushed, iclass 26, count 0 2006.257.09:00:59.43#ibcon#about to write, iclass 26, count 0 2006.257.09:00:59.43#ibcon#wrote, iclass 26, count 0 2006.257.09:00:59.43#ibcon#about to read 3, iclass 26, count 0 2006.257.09:00:59.45#ibcon#read 3, iclass 26, count 0 2006.257.09:00:59.45#ibcon#about to read 4, iclass 26, count 0 2006.257.09:00:59.45#ibcon#read 4, iclass 26, count 0 2006.257.09:00:59.45#ibcon#about to read 5, iclass 26, count 0 2006.257.09:00:59.45#ibcon#read 5, iclass 26, count 0 2006.257.09:00:59.45#ibcon#about to read 6, iclass 26, count 0 2006.257.09:00:59.45#ibcon#read 6, iclass 26, count 0 2006.257.09:00:59.45#ibcon#end of sib2, iclass 26, count 0 2006.257.09:00:59.45#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:00:59.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:00:59.45#ibcon#[27=USB\r\n] 2006.257.09:00:59.45#ibcon#*before write, iclass 26, count 0 2006.257.09:00:59.45#ibcon#enter sib2, iclass 26, count 0 2006.257.09:00:59.45#ibcon#flushed, iclass 26, count 0 2006.257.09:00:59.45#ibcon#about to write, iclass 26, count 0 2006.257.09:00:59.45#ibcon#wrote, iclass 26, count 0 2006.257.09:00:59.45#ibcon#about to read 3, iclass 26, count 0 2006.257.09:00:59.48#ibcon#read 3, iclass 26, count 0 2006.257.09:00:59.48#ibcon#about to read 4, iclass 26, count 0 2006.257.09:00:59.48#ibcon#read 4, iclass 26, count 0 2006.257.09:00:59.48#ibcon#about to read 5, iclass 26, count 0 2006.257.09:00:59.48#ibcon#read 5, iclass 26, count 0 2006.257.09:00:59.48#ibcon#about to read 6, iclass 26, count 0 2006.257.09:00:59.48#ibcon#read 6, iclass 26, count 0 2006.257.09:00:59.48#ibcon#end of sib2, iclass 26, count 0 2006.257.09:00:59.48#ibcon#*after write, iclass 26, count 0 2006.257.09:00:59.48#ibcon#*before return 0, iclass 26, count 0 2006.257.09:00:59.48#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:59.48#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:00:59.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:00:59.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:00:59.48$vck44/vblo=3,649.99 2006.257.09:00:59.48#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.09:00:59.48#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.09:00:59.48#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:59.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:59.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:59.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:59.48#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:00:59.48#ibcon#first serial, iclass 28, count 0 2006.257.09:00:59.48#ibcon#enter sib2, iclass 28, count 0 2006.257.09:00:59.48#ibcon#flushed, iclass 28, count 0 2006.257.09:00:59.48#ibcon#about to write, iclass 28, count 0 2006.257.09:00:59.48#ibcon#wrote, iclass 28, count 0 2006.257.09:00:59.48#ibcon#about to read 3, iclass 28, count 0 2006.257.09:00:59.50#ibcon#read 3, iclass 28, count 0 2006.257.09:00:59.50#ibcon#about to read 4, iclass 28, count 0 2006.257.09:00:59.50#ibcon#read 4, iclass 28, count 0 2006.257.09:00:59.50#ibcon#about to read 5, iclass 28, count 0 2006.257.09:00:59.50#ibcon#read 5, iclass 28, count 0 2006.257.09:00:59.50#ibcon#about to read 6, iclass 28, count 0 2006.257.09:00:59.50#ibcon#read 6, iclass 28, count 0 2006.257.09:00:59.50#ibcon#end of sib2, iclass 28, count 0 2006.257.09:00:59.50#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:00:59.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:00:59.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:00:59.50#ibcon#*before write, iclass 28, count 0 2006.257.09:00:59.50#ibcon#enter sib2, iclass 28, count 0 2006.257.09:00:59.50#ibcon#flushed, iclass 28, count 0 2006.257.09:00:59.50#ibcon#about to write, iclass 28, count 0 2006.257.09:00:59.50#ibcon#wrote, iclass 28, count 0 2006.257.09:00:59.50#ibcon#about to read 3, iclass 28, count 0 2006.257.09:00:59.54#ibcon#read 3, iclass 28, count 0 2006.257.09:00:59.54#ibcon#about to read 4, iclass 28, count 0 2006.257.09:00:59.54#ibcon#read 4, iclass 28, count 0 2006.257.09:00:59.54#ibcon#about to read 5, iclass 28, count 0 2006.257.09:00:59.54#ibcon#read 5, iclass 28, count 0 2006.257.09:00:59.54#ibcon#about to read 6, iclass 28, count 0 2006.257.09:00:59.54#ibcon#read 6, iclass 28, count 0 2006.257.09:00:59.54#ibcon#end of sib2, iclass 28, count 0 2006.257.09:00:59.54#ibcon#*after write, iclass 28, count 0 2006.257.09:00:59.54#ibcon#*before return 0, iclass 28, count 0 2006.257.09:00:59.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:59.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:00:59.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:00:59.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:00:59.54$vck44/vb=3,4 2006.257.09:00:59.54#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.09:00:59.54#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.09:00:59.54#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:59.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:59.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:59.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:59.60#ibcon#enter wrdev, iclass 30, count 2 2006.257.09:00:59.60#ibcon#first serial, iclass 30, count 2 2006.257.09:00:59.60#ibcon#enter sib2, iclass 30, count 2 2006.257.09:00:59.60#ibcon#flushed, iclass 30, count 2 2006.257.09:00:59.60#ibcon#about to write, iclass 30, count 2 2006.257.09:00:59.60#ibcon#wrote, iclass 30, count 2 2006.257.09:00:59.60#ibcon#about to read 3, iclass 30, count 2 2006.257.09:00:59.62#ibcon#read 3, iclass 30, count 2 2006.257.09:00:59.62#ibcon#about to read 4, iclass 30, count 2 2006.257.09:00:59.62#ibcon#read 4, iclass 30, count 2 2006.257.09:00:59.62#ibcon#about to read 5, iclass 30, count 2 2006.257.09:00:59.62#ibcon#read 5, iclass 30, count 2 2006.257.09:00:59.62#ibcon#about to read 6, iclass 30, count 2 2006.257.09:00:59.62#ibcon#read 6, iclass 30, count 2 2006.257.09:00:59.62#ibcon#end of sib2, iclass 30, count 2 2006.257.09:00:59.62#ibcon#*mode == 0, iclass 30, count 2 2006.257.09:00:59.62#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.09:00:59.62#ibcon#[27=AT03-04\r\n] 2006.257.09:00:59.62#ibcon#*before write, iclass 30, count 2 2006.257.09:00:59.62#ibcon#enter sib2, iclass 30, count 2 2006.257.09:00:59.62#ibcon#flushed, iclass 30, count 2 2006.257.09:00:59.62#ibcon#about to write, iclass 30, count 2 2006.257.09:00:59.62#ibcon#wrote, iclass 30, count 2 2006.257.09:00:59.62#ibcon#about to read 3, iclass 30, count 2 2006.257.09:00:59.65#ibcon#read 3, iclass 30, count 2 2006.257.09:00:59.65#ibcon#about to read 4, iclass 30, count 2 2006.257.09:00:59.65#ibcon#read 4, iclass 30, count 2 2006.257.09:00:59.65#ibcon#about to read 5, iclass 30, count 2 2006.257.09:00:59.65#ibcon#read 5, iclass 30, count 2 2006.257.09:00:59.65#ibcon#about to read 6, iclass 30, count 2 2006.257.09:00:59.65#ibcon#read 6, iclass 30, count 2 2006.257.09:00:59.65#ibcon#end of sib2, iclass 30, count 2 2006.257.09:00:59.65#ibcon#*after write, iclass 30, count 2 2006.257.09:00:59.65#ibcon#*before return 0, iclass 30, count 2 2006.257.09:00:59.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:59.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:00:59.65#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.09:00:59.65#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:59.65#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:59.77#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:59.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:59.77#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:00:59.77#ibcon#first serial, iclass 30, count 0 2006.257.09:00:59.77#ibcon#enter sib2, iclass 30, count 0 2006.257.09:00:59.77#ibcon#flushed, iclass 30, count 0 2006.257.09:00:59.77#ibcon#about to write, iclass 30, count 0 2006.257.09:00:59.77#ibcon#wrote, iclass 30, count 0 2006.257.09:00:59.77#ibcon#about to read 3, iclass 30, count 0 2006.257.09:00:59.79#ibcon#read 3, iclass 30, count 0 2006.257.09:00:59.79#ibcon#about to read 4, iclass 30, count 0 2006.257.09:00:59.79#ibcon#read 4, iclass 30, count 0 2006.257.09:00:59.79#ibcon#about to read 5, iclass 30, count 0 2006.257.09:00:59.79#ibcon#read 5, iclass 30, count 0 2006.257.09:00:59.79#ibcon#about to read 6, iclass 30, count 0 2006.257.09:00:59.79#ibcon#read 6, iclass 30, count 0 2006.257.09:00:59.79#ibcon#end of sib2, iclass 30, count 0 2006.257.09:00:59.79#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:00:59.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:00:59.79#ibcon#[27=USB\r\n] 2006.257.09:00:59.79#ibcon#*before write, iclass 30, count 0 2006.257.09:00:59.79#ibcon#enter sib2, iclass 30, count 0 2006.257.09:00:59.79#ibcon#flushed, iclass 30, count 0 2006.257.09:00:59.79#ibcon#about to write, iclass 30, count 0 2006.257.09:00:59.79#ibcon#wrote, iclass 30, count 0 2006.257.09:00:59.79#ibcon#about to read 3, iclass 30, count 0 2006.257.09:00:59.82#ibcon#read 3, iclass 30, count 0 2006.257.09:00:59.82#ibcon#about to read 4, iclass 30, count 0 2006.257.09:00:59.82#ibcon#read 4, iclass 30, count 0 2006.257.09:00:59.82#ibcon#about to read 5, iclass 30, count 0 2006.257.09:00:59.82#ibcon#read 5, iclass 30, count 0 2006.257.09:00:59.82#ibcon#about to read 6, iclass 30, count 0 2006.257.09:00:59.82#ibcon#read 6, iclass 30, count 0 2006.257.09:00:59.82#ibcon#end of sib2, iclass 30, count 0 2006.257.09:00:59.82#ibcon#*after write, iclass 30, count 0 2006.257.09:00:59.82#ibcon#*before return 0, iclass 30, count 0 2006.257.09:00:59.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:59.82#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:00:59.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:00:59.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:00:59.82$vck44/vblo=4,679.99 2006.257.09:00:59.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.09:00:59.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.09:00:59.82#ibcon#ireg 17 cls_cnt 0 2006.257.09:00:59.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:59.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:59.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:59.82#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:00:59.82#ibcon#first serial, iclass 32, count 0 2006.257.09:00:59.82#ibcon#enter sib2, iclass 32, count 0 2006.257.09:00:59.82#ibcon#flushed, iclass 32, count 0 2006.257.09:00:59.82#ibcon#about to write, iclass 32, count 0 2006.257.09:00:59.82#ibcon#wrote, iclass 32, count 0 2006.257.09:00:59.82#ibcon#about to read 3, iclass 32, count 0 2006.257.09:00:59.84#ibcon#read 3, iclass 32, count 0 2006.257.09:00:59.84#ibcon#about to read 4, iclass 32, count 0 2006.257.09:00:59.84#ibcon#read 4, iclass 32, count 0 2006.257.09:00:59.84#ibcon#about to read 5, iclass 32, count 0 2006.257.09:00:59.84#ibcon#read 5, iclass 32, count 0 2006.257.09:00:59.84#ibcon#about to read 6, iclass 32, count 0 2006.257.09:00:59.84#ibcon#read 6, iclass 32, count 0 2006.257.09:00:59.84#ibcon#end of sib2, iclass 32, count 0 2006.257.09:00:59.84#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:00:59.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:00:59.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:00:59.84#ibcon#*before write, iclass 32, count 0 2006.257.09:00:59.84#ibcon#enter sib2, iclass 32, count 0 2006.257.09:00:59.84#ibcon#flushed, iclass 32, count 0 2006.257.09:00:59.84#ibcon#about to write, iclass 32, count 0 2006.257.09:00:59.84#ibcon#wrote, iclass 32, count 0 2006.257.09:00:59.84#ibcon#about to read 3, iclass 32, count 0 2006.257.09:00:59.88#ibcon#read 3, iclass 32, count 0 2006.257.09:00:59.88#ibcon#about to read 4, iclass 32, count 0 2006.257.09:00:59.88#ibcon#read 4, iclass 32, count 0 2006.257.09:00:59.88#ibcon#about to read 5, iclass 32, count 0 2006.257.09:00:59.88#ibcon#read 5, iclass 32, count 0 2006.257.09:00:59.88#ibcon#about to read 6, iclass 32, count 0 2006.257.09:00:59.88#ibcon#read 6, iclass 32, count 0 2006.257.09:00:59.88#ibcon#end of sib2, iclass 32, count 0 2006.257.09:00:59.88#ibcon#*after write, iclass 32, count 0 2006.257.09:00:59.88#ibcon#*before return 0, iclass 32, count 0 2006.257.09:00:59.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:59.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:00:59.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:00:59.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:00:59.88$vck44/vb=4,5 2006.257.09:00:59.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.09:00:59.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.09:00:59.88#ibcon#ireg 11 cls_cnt 2 2006.257.09:00:59.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:59.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:59.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:59.94#ibcon#enter wrdev, iclass 34, count 2 2006.257.09:00:59.94#ibcon#first serial, iclass 34, count 2 2006.257.09:00:59.94#ibcon#enter sib2, iclass 34, count 2 2006.257.09:00:59.94#ibcon#flushed, iclass 34, count 2 2006.257.09:00:59.94#ibcon#about to write, iclass 34, count 2 2006.257.09:00:59.94#ibcon#wrote, iclass 34, count 2 2006.257.09:00:59.94#ibcon#about to read 3, iclass 34, count 2 2006.257.09:00:59.96#ibcon#read 3, iclass 34, count 2 2006.257.09:00:59.96#ibcon#about to read 4, iclass 34, count 2 2006.257.09:00:59.96#ibcon#read 4, iclass 34, count 2 2006.257.09:00:59.96#ibcon#about to read 5, iclass 34, count 2 2006.257.09:00:59.96#ibcon#read 5, iclass 34, count 2 2006.257.09:00:59.96#ibcon#about to read 6, iclass 34, count 2 2006.257.09:00:59.96#ibcon#read 6, iclass 34, count 2 2006.257.09:00:59.96#ibcon#end of sib2, iclass 34, count 2 2006.257.09:00:59.96#ibcon#*mode == 0, iclass 34, count 2 2006.257.09:00:59.96#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.09:00:59.96#ibcon#[27=AT04-05\r\n] 2006.257.09:00:59.96#ibcon#*before write, iclass 34, count 2 2006.257.09:00:59.96#ibcon#enter sib2, iclass 34, count 2 2006.257.09:00:59.96#ibcon#flushed, iclass 34, count 2 2006.257.09:00:59.96#ibcon#about to write, iclass 34, count 2 2006.257.09:00:59.96#ibcon#wrote, iclass 34, count 2 2006.257.09:00:59.96#ibcon#about to read 3, iclass 34, count 2 2006.257.09:00:59.99#ibcon#read 3, iclass 34, count 2 2006.257.09:00:59.99#ibcon#about to read 4, iclass 34, count 2 2006.257.09:00:59.99#ibcon#read 4, iclass 34, count 2 2006.257.09:00:59.99#ibcon#about to read 5, iclass 34, count 2 2006.257.09:00:59.99#ibcon#read 5, iclass 34, count 2 2006.257.09:00:59.99#ibcon#about to read 6, iclass 34, count 2 2006.257.09:00:59.99#ibcon#read 6, iclass 34, count 2 2006.257.09:00:59.99#ibcon#end of sib2, iclass 34, count 2 2006.257.09:00:59.99#ibcon#*after write, iclass 34, count 2 2006.257.09:00:59.99#ibcon#*before return 0, iclass 34, count 2 2006.257.09:00:59.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:59.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:00:59.99#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.09:00:59.99#ibcon#ireg 7 cls_cnt 0 2006.257.09:00:59.99#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:01:00.11#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:01:00.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:01:00.11#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:01:00.11#ibcon#first serial, iclass 34, count 0 2006.257.09:01:00.11#ibcon#enter sib2, iclass 34, count 0 2006.257.09:01:00.11#ibcon#flushed, iclass 34, count 0 2006.257.09:01:00.11#ibcon#about to write, iclass 34, count 0 2006.257.09:01:00.11#ibcon#wrote, iclass 34, count 0 2006.257.09:01:00.11#ibcon#about to read 3, iclass 34, count 0 2006.257.09:01:00.13#ibcon#read 3, iclass 34, count 0 2006.257.09:01:00.13#ibcon#about to read 4, iclass 34, count 0 2006.257.09:01:00.13#ibcon#read 4, iclass 34, count 0 2006.257.09:01:00.13#ibcon#about to read 5, iclass 34, count 0 2006.257.09:01:00.13#ibcon#read 5, iclass 34, count 0 2006.257.09:01:00.13#ibcon#about to read 6, iclass 34, count 0 2006.257.09:01:00.13#ibcon#read 6, iclass 34, count 0 2006.257.09:01:00.13#ibcon#end of sib2, iclass 34, count 0 2006.257.09:01:00.13#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:01:00.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:01:00.13#ibcon#[27=USB\r\n] 2006.257.09:01:00.13#ibcon#*before write, iclass 34, count 0 2006.257.09:01:00.13#ibcon#enter sib2, iclass 34, count 0 2006.257.09:01:00.13#ibcon#flushed, iclass 34, count 0 2006.257.09:01:00.13#ibcon#about to write, iclass 34, count 0 2006.257.09:01:00.13#ibcon#wrote, iclass 34, count 0 2006.257.09:01:00.13#ibcon#about to read 3, iclass 34, count 0 2006.257.09:01:00.16#ibcon#read 3, iclass 34, count 0 2006.257.09:01:00.16#ibcon#about to read 4, iclass 34, count 0 2006.257.09:01:00.16#ibcon#read 4, iclass 34, count 0 2006.257.09:01:00.16#ibcon#about to read 5, iclass 34, count 0 2006.257.09:01:00.16#ibcon#read 5, iclass 34, count 0 2006.257.09:01:00.16#ibcon#about to read 6, iclass 34, count 0 2006.257.09:01:00.16#ibcon#read 6, iclass 34, count 0 2006.257.09:01:00.16#ibcon#end of sib2, iclass 34, count 0 2006.257.09:01:00.16#ibcon#*after write, iclass 34, count 0 2006.257.09:01:00.16#ibcon#*before return 0, iclass 34, count 0 2006.257.09:01:00.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:01:00.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:01:00.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:01:00.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:01:00.16$vck44/vblo=5,709.99 2006.257.09:01:00.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.09:01:00.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.09:01:00.16#ibcon#ireg 17 cls_cnt 0 2006.257.09:01:00.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:01:00.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:01:00.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:01:00.16#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:01:00.16#ibcon#first serial, iclass 36, count 0 2006.257.09:01:00.16#ibcon#enter sib2, iclass 36, count 0 2006.257.09:01:00.16#ibcon#flushed, iclass 36, count 0 2006.257.09:01:00.16#ibcon#about to write, iclass 36, count 0 2006.257.09:01:00.16#ibcon#wrote, iclass 36, count 0 2006.257.09:01:00.16#ibcon#about to read 3, iclass 36, count 0 2006.257.09:01:00.18#ibcon#read 3, iclass 36, count 0 2006.257.09:01:00.18#ibcon#about to read 4, iclass 36, count 0 2006.257.09:01:00.18#ibcon#read 4, iclass 36, count 0 2006.257.09:01:00.18#ibcon#about to read 5, iclass 36, count 0 2006.257.09:01:00.18#ibcon#read 5, iclass 36, count 0 2006.257.09:01:00.18#ibcon#about to read 6, iclass 36, count 0 2006.257.09:01:00.18#ibcon#read 6, iclass 36, count 0 2006.257.09:01:00.18#ibcon#end of sib2, iclass 36, count 0 2006.257.09:01:00.18#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:01:00.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:01:00.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:01:00.18#ibcon#*before write, iclass 36, count 0 2006.257.09:01:00.18#ibcon#enter sib2, iclass 36, count 0 2006.257.09:01:00.18#ibcon#flushed, iclass 36, count 0 2006.257.09:01:00.18#ibcon#about to write, iclass 36, count 0 2006.257.09:01:00.18#ibcon#wrote, iclass 36, count 0 2006.257.09:01:00.18#ibcon#about to read 3, iclass 36, count 0 2006.257.09:01:00.22#ibcon#read 3, iclass 36, count 0 2006.257.09:01:00.22#ibcon#about to read 4, iclass 36, count 0 2006.257.09:01:00.22#ibcon#read 4, iclass 36, count 0 2006.257.09:01:00.22#ibcon#about to read 5, iclass 36, count 0 2006.257.09:01:00.22#ibcon#read 5, iclass 36, count 0 2006.257.09:01:00.22#ibcon#about to read 6, iclass 36, count 0 2006.257.09:01:00.22#ibcon#read 6, iclass 36, count 0 2006.257.09:01:00.22#ibcon#end of sib2, iclass 36, count 0 2006.257.09:01:00.22#ibcon#*after write, iclass 36, count 0 2006.257.09:01:00.22#ibcon#*before return 0, iclass 36, count 0 2006.257.09:01:00.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:01:00.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:01:00.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:01:00.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:01:00.22$vck44/vb=5,4 2006.257.09:01:00.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.09:01:00.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.09:01:00.22#ibcon#ireg 11 cls_cnt 2 2006.257.09:01:00.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:01:00.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:01:00.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:01:00.28#ibcon#enter wrdev, iclass 38, count 2 2006.257.09:01:00.28#ibcon#first serial, iclass 38, count 2 2006.257.09:01:00.28#ibcon#enter sib2, iclass 38, count 2 2006.257.09:01:00.28#ibcon#flushed, iclass 38, count 2 2006.257.09:01:00.28#ibcon#about to write, iclass 38, count 2 2006.257.09:01:00.28#ibcon#wrote, iclass 38, count 2 2006.257.09:01:00.28#ibcon#about to read 3, iclass 38, count 2 2006.257.09:01:00.30#ibcon#read 3, iclass 38, count 2 2006.257.09:01:00.30#ibcon#about to read 4, iclass 38, count 2 2006.257.09:01:00.30#ibcon#read 4, iclass 38, count 2 2006.257.09:01:00.30#ibcon#about to read 5, iclass 38, count 2 2006.257.09:01:00.30#ibcon#read 5, iclass 38, count 2 2006.257.09:01:00.30#ibcon#about to read 6, iclass 38, count 2 2006.257.09:01:00.30#ibcon#read 6, iclass 38, count 2 2006.257.09:01:00.30#ibcon#end of sib2, iclass 38, count 2 2006.257.09:01:00.30#ibcon#*mode == 0, iclass 38, count 2 2006.257.09:01:00.30#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.09:01:00.30#ibcon#[27=AT05-04\r\n] 2006.257.09:01:00.30#ibcon#*before write, iclass 38, count 2 2006.257.09:01:00.30#ibcon#enter sib2, iclass 38, count 2 2006.257.09:01:00.30#ibcon#flushed, iclass 38, count 2 2006.257.09:01:00.30#ibcon#about to write, iclass 38, count 2 2006.257.09:01:00.30#ibcon#wrote, iclass 38, count 2 2006.257.09:01:00.30#ibcon#about to read 3, iclass 38, count 2 2006.257.09:01:00.33#ibcon#read 3, iclass 38, count 2 2006.257.09:01:00.33#ibcon#about to read 4, iclass 38, count 2 2006.257.09:01:00.33#ibcon#read 4, iclass 38, count 2 2006.257.09:01:00.33#ibcon#about to read 5, iclass 38, count 2 2006.257.09:01:00.33#ibcon#read 5, iclass 38, count 2 2006.257.09:01:00.33#ibcon#about to read 6, iclass 38, count 2 2006.257.09:01:00.33#ibcon#read 6, iclass 38, count 2 2006.257.09:01:00.33#ibcon#end of sib2, iclass 38, count 2 2006.257.09:01:00.33#ibcon#*after write, iclass 38, count 2 2006.257.09:01:00.33#ibcon#*before return 0, iclass 38, count 2 2006.257.09:01:00.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:01:00.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:01:00.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.09:01:00.33#ibcon#ireg 7 cls_cnt 0 2006.257.09:01:00.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:01:00.41#abcon#<5=/14 1.1 1.9 20.13 941013.2\r\n> 2006.257.09:01:00.43#abcon#{5=INTERFACE CLEAR} 2006.257.09:01:00.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:01:00.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:01:00.45#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:01:00.45#ibcon#first serial, iclass 38, count 0 2006.257.09:01:00.45#ibcon#enter sib2, iclass 38, count 0 2006.257.09:01:00.45#ibcon#flushed, iclass 38, count 0 2006.257.09:01:00.45#ibcon#about to write, iclass 38, count 0 2006.257.09:01:00.45#ibcon#wrote, iclass 38, count 0 2006.257.09:01:00.45#ibcon#about to read 3, iclass 38, count 0 2006.257.09:01:00.47#ibcon#read 3, iclass 38, count 0 2006.257.09:01:00.47#ibcon#about to read 4, iclass 38, count 0 2006.257.09:01:00.47#ibcon#read 4, iclass 38, count 0 2006.257.09:01:00.47#ibcon#about to read 5, iclass 38, count 0 2006.257.09:01:00.47#ibcon#read 5, iclass 38, count 0 2006.257.09:01:00.47#ibcon#about to read 6, iclass 38, count 0 2006.257.09:01:00.47#ibcon#read 6, iclass 38, count 0 2006.257.09:01:00.47#ibcon#end of sib2, iclass 38, count 0 2006.257.09:01:00.47#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:01:00.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:01:00.47#ibcon#[27=USB\r\n] 2006.257.09:01:00.47#ibcon#*before write, iclass 38, count 0 2006.257.09:01:00.47#ibcon#enter sib2, iclass 38, count 0 2006.257.09:01:00.47#ibcon#flushed, iclass 38, count 0 2006.257.09:01:00.47#ibcon#about to write, iclass 38, count 0 2006.257.09:01:00.47#ibcon#wrote, iclass 38, count 0 2006.257.09:01:00.47#ibcon#about to read 3, iclass 38, count 0 2006.257.09:01:00.49#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:01:00.50#ibcon#read 3, iclass 38, count 0 2006.257.09:01:00.50#ibcon#about to read 4, iclass 38, count 0 2006.257.09:01:00.50#ibcon#read 4, iclass 38, count 0 2006.257.09:01:00.50#ibcon#about to read 5, iclass 38, count 0 2006.257.09:01:00.50#ibcon#read 5, iclass 38, count 0 2006.257.09:01:00.50#ibcon#about to read 6, iclass 38, count 0 2006.257.09:01:00.50#ibcon#read 6, iclass 38, count 0 2006.257.09:01:00.50#ibcon#end of sib2, iclass 38, count 0 2006.257.09:01:00.50#ibcon#*after write, iclass 38, count 0 2006.257.09:01:00.50#ibcon#*before return 0, iclass 38, count 0 2006.257.09:01:00.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:01:00.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:01:00.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:01:00.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:01:00.50$vck44/vblo=6,719.99 2006.257.09:01:00.50#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.09:01:00.50#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.09:01:00.50#ibcon#ireg 17 cls_cnt 0 2006.257.09:01:00.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:01:00.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:01:00.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:01:00.50#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:01:00.50#ibcon#first serial, iclass 6, count 0 2006.257.09:01:00.50#ibcon#enter sib2, iclass 6, count 0 2006.257.09:01:00.50#ibcon#flushed, iclass 6, count 0 2006.257.09:01:00.50#ibcon#about to write, iclass 6, count 0 2006.257.09:01:00.50#ibcon#wrote, iclass 6, count 0 2006.257.09:01:00.50#ibcon#about to read 3, iclass 6, count 0 2006.257.09:01:00.52#ibcon#read 3, iclass 6, count 0 2006.257.09:01:00.52#ibcon#about to read 4, iclass 6, count 0 2006.257.09:01:00.52#ibcon#read 4, iclass 6, count 0 2006.257.09:01:00.52#ibcon#about to read 5, iclass 6, count 0 2006.257.09:01:00.52#ibcon#read 5, iclass 6, count 0 2006.257.09:01:00.52#ibcon#about to read 6, iclass 6, count 0 2006.257.09:01:00.52#ibcon#read 6, iclass 6, count 0 2006.257.09:01:00.52#ibcon#end of sib2, iclass 6, count 0 2006.257.09:01:00.52#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:01:00.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:01:00.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:01:00.52#ibcon#*before write, iclass 6, count 0 2006.257.09:01:00.52#ibcon#enter sib2, iclass 6, count 0 2006.257.09:01:00.52#ibcon#flushed, iclass 6, count 0 2006.257.09:01:00.52#ibcon#about to write, iclass 6, count 0 2006.257.09:01:00.52#ibcon#wrote, iclass 6, count 0 2006.257.09:01:00.52#ibcon#about to read 3, iclass 6, count 0 2006.257.09:01:00.56#ibcon#read 3, iclass 6, count 0 2006.257.09:01:00.56#ibcon#about to read 4, iclass 6, count 0 2006.257.09:01:00.56#ibcon#read 4, iclass 6, count 0 2006.257.09:01:00.56#ibcon#about to read 5, iclass 6, count 0 2006.257.09:01:00.56#ibcon#read 5, iclass 6, count 0 2006.257.09:01:00.56#ibcon#about to read 6, iclass 6, count 0 2006.257.09:01:00.56#ibcon#read 6, iclass 6, count 0 2006.257.09:01:00.56#ibcon#end of sib2, iclass 6, count 0 2006.257.09:01:00.56#ibcon#*after write, iclass 6, count 0 2006.257.09:01:00.56#ibcon#*before return 0, iclass 6, count 0 2006.257.09:01:00.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:01:00.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:01:00.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:01:00.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:01:00.56$vck44/vb=6,4 2006.257.09:01:00.56#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.09:01:00.56#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.09:01:00.56#ibcon#ireg 11 cls_cnt 2 2006.257.09:01:00.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:01:00.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:01:00.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:01:00.62#ibcon#enter wrdev, iclass 10, count 2 2006.257.09:01:00.62#ibcon#first serial, iclass 10, count 2 2006.257.09:01:00.62#ibcon#enter sib2, iclass 10, count 2 2006.257.09:01:00.62#ibcon#flushed, iclass 10, count 2 2006.257.09:01:00.62#ibcon#about to write, iclass 10, count 2 2006.257.09:01:00.62#ibcon#wrote, iclass 10, count 2 2006.257.09:01:00.62#ibcon#about to read 3, iclass 10, count 2 2006.257.09:01:00.64#ibcon#read 3, iclass 10, count 2 2006.257.09:01:00.64#ibcon#about to read 4, iclass 10, count 2 2006.257.09:01:00.64#ibcon#read 4, iclass 10, count 2 2006.257.09:01:00.64#ibcon#about to read 5, iclass 10, count 2 2006.257.09:01:00.64#ibcon#read 5, iclass 10, count 2 2006.257.09:01:00.64#ibcon#about to read 6, iclass 10, count 2 2006.257.09:01:00.64#ibcon#read 6, iclass 10, count 2 2006.257.09:01:00.64#ibcon#end of sib2, iclass 10, count 2 2006.257.09:01:00.64#ibcon#*mode == 0, iclass 10, count 2 2006.257.09:01:00.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.09:01:00.64#ibcon#[27=AT06-04\r\n] 2006.257.09:01:00.64#ibcon#*before write, iclass 10, count 2 2006.257.09:01:00.64#ibcon#enter sib2, iclass 10, count 2 2006.257.09:01:00.64#ibcon#flushed, iclass 10, count 2 2006.257.09:01:00.64#ibcon#about to write, iclass 10, count 2 2006.257.09:01:00.64#ibcon#wrote, iclass 10, count 2 2006.257.09:01:00.64#ibcon#about to read 3, iclass 10, count 2 2006.257.09:01:00.67#ibcon#read 3, iclass 10, count 2 2006.257.09:01:00.67#ibcon#about to read 4, iclass 10, count 2 2006.257.09:01:00.67#ibcon#read 4, iclass 10, count 2 2006.257.09:01:00.67#ibcon#about to read 5, iclass 10, count 2 2006.257.09:01:00.67#ibcon#read 5, iclass 10, count 2 2006.257.09:01:00.67#ibcon#about to read 6, iclass 10, count 2 2006.257.09:01:00.67#ibcon#read 6, iclass 10, count 2 2006.257.09:01:00.67#ibcon#end of sib2, iclass 10, count 2 2006.257.09:01:00.67#ibcon#*after write, iclass 10, count 2 2006.257.09:01:00.67#ibcon#*before return 0, iclass 10, count 2 2006.257.09:01:00.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:01:00.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:01:00.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.09:01:00.67#ibcon#ireg 7 cls_cnt 0 2006.257.09:01:00.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:01:00.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:01:00.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:01:00.79#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:01:00.79#ibcon#first serial, iclass 10, count 0 2006.257.09:01:00.79#ibcon#enter sib2, iclass 10, count 0 2006.257.09:01:00.79#ibcon#flushed, iclass 10, count 0 2006.257.09:01:00.79#ibcon#about to write, iclass 10, count 0 2006.257.09:01:00.79#ibcon#wrote, iclass 10, count 0 2006.257.09:01:00.79#ibcon#about to read 3, iclass 10, count 0 2006.257.09:01:00.81#ibcon#read 3, iclass 10, count 0 2006.257.09:01:00.81#ibcon#about to read 4, iclass 10, count 0 2006.257.09:01:00.81#ibcon#read 4, iclass 10, count 0 2006.257.09:01:00.81#ibcon#about to read 5, iclass 10, count 0 2006.257.09:01:00.81#ibcon#read 5, iclass 10, count 0 2006.257.09:01:00.81#ibcon#about to read 6, iclass 10, count 0 2006.257.09:01:00.81#ibcon#read 6, iclass 10, count 0 2006.257.09:01:00.81#ibcon#end of sib2, iclass 10, count 0 2006.257.09:01:00.81#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:01:00.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:01:00.81#ibcon#[27=USB\r\n] 2006.257.09:01:00.81#ibcon#*before write, iclass 10, count 0 2006.257.09:01:00.81#ibcon#enter sib2, iclass 10, count 0 2006.257.09:01:00.81#ibcon#flushed, iclass 10, count 0 2006.257.09:01:00.81#ibcon#about to write, iclass 10, count 0 2006.257.09:01:00.81#ibcon#wrote, iclass 10, count 0 2006.257.09:01:00.81#ibcon#about to read 3, iclass 10, count 0 2006.257.09:01:00.84#ibcon#read 3, iclass 10, count 0 2006.257.09:01:00.84#ibcon#about to read 4, iclass 10, count 0 2006.257.09:01:00.84#ibcon#read 4, iclass 10, count 0 2006.257.09:01:00.84#ibcon#about to read 5, iclass 10, count 0 2006.257.09:01:00.84#ibcon#read 5, iclass 10, count 0 2006.257.09:01:00.84#ibcon#about to read 6, iclass 10, count 0 2006.257.09:01:00.84#ibcon#read 6, iclass 10, count 0 2006.257.09:01:00.84#ibcon#end of sib2, iclass 10, count 0 2006.257.09:01:00.84#ibcon#*after write, iclass 10, count 0 2006.257.09:01:00.84#ibcon#*before return 0, iclass 10, count 0 2006.257.09:01:00.84#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:01:00.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:01:00.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:01:00.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:01:00.84$vck44/vblo=7,734.99 2006.257.09:01:00.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.09:01:00.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.09:01:00.84#ibcon#ireg 17 cls_cnt 0 2006.257.09:01:00.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:01:00.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:01:00.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:01:00.84#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:01:00.84#ibcon#first serial, iclass 12, count 0 2006.257.09:01:00.84#ibcon#enter sib2, iclass 12, count 0 2006.257.09:01:00.84#ibcon#flushed, iclass 12, count 0 2006.257.09:01:00.84#ibcon#about to write, iclass 12, count 0 2006.257.09:01:00.84#ibcon#wrote, iclass 12, count 0 2006.257.09:01:00.84#ibcon#about to read 3, iclass 12, count 0 2006.257.09:01:00.86#ibcon#read 3, iclass 12, count 0 2006.257.09:01:00.86#ibcon#about to read 4, iclass 12, count 0 2006.257.09:01:00.86#ibcon#read 4, iclass 12, count 0 2006.257.09:01:00.86#ibcon#about to read 5, iclass 12, count 0 2006.257.09:01:00.86#ibcon#read 5, iclass 12, count 0 2006.257.09:01:00.86#ibcon#about to read 6, iclass 12, count 0 2006.257.09:01:00.86#ibcon#read 6, iclass 12, count 0 2006.257.09:01:00.86#ibcon#end of sib2, iclass 12, count 0 2006.257.09:01:00.86#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:01:00.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:01:00.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:01:00.86#ibcon#*before write, iclass 12, count 0 2006.257.09:01:00.86#ibcon#enter sib2, iclass 12, count 0 2006.257.09:01:00.86#ibcon#flushed, iclass 12, count 0 2006.257.09:01:00.86#ibcon#about to write, iclass 12, count 0 2006.257.09:01:00.86#ibcon#wrote, iclass 12, count 0 2006.257.09:01:00.86#ibcon#about to read 3, iclass 12, count 0 2006.257.09:01:00.90#ibcon#read 3, iclass 12, count 0 2006.257.09:01:00.90#ibcon#about to read 4, iclass 12, count 0 2006.257.09:01:00.90#ibcon#read 4, iclass 12, count 0 2006.257.09:01:00.90#ibcon#about to read 5, iclass 12, count 0 2006.257.09:01:00.90#ibcon#read 5, iclass 12, count 0 2006.257.09:01:00.90#ibcon#about to read 6, iclass 12, count 0 2006.257.09:01:00.90#ibcon#read 6, iclass 12, count 0 2006.257.09:01:00.90#ibcon#end of sib2, iclass 12, count 0 2006.257.09:01:00.90#ibcon#*after write, iclass 12, count 0 2006.257.09:01:00.90#ibcon#*before return 0, iclass 12, count 0 2006.257.09:01:00.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:01:00.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:01:00.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:01:00.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:01:00.90$vck44/vb=7,4 2006.257.09:01:00.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.09:01:00.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.09:01:00.90#ibcon#ireg 11 cls_cnt 2 2006.257.09:01:00.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:01:00.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:01:00.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:01:00.96#ibcon#enter wrdev, iclass 14, count 2 2006.257.09:01:00.96#ibcon#first serial, iclass 14, count 2 2006.257.09:01:00.96#ibcon#enter sib2, iclass 14, count 2 2006.257.09:01:00.96#ibcon#flushed, iclass 14, count 2 2006.257.09:01:00.96#ibcon#about to write, iclass 14, count 2 2006.257.09:01:00.96#ibcon#wrote, iclass 14, count 2 2006.257.09:01:00.96#ibcon#about to read 3, iclass 14, count 2 2006.257.09:01:00.98#ibcon#read 3, iclass 14, count 2 2006.257.09:01:00.98#ibcon#about to read 4, iclass 14, count 2 2006.257.09:01:00.98#ibcon#read 4, iclass 14, count 2 2006.257.09:01:00.98#ibcon#about to read 5, iclass 14, count 2 2006.257.09:01:00.98#ibcon#read 5, iclass 14, count 2 2006.257.09:01:00.98#ibcon#about to read 6, iclass 14, count 2 2006.257.09:01:00.98#ibcon#read 6, iclass 14, count 2 2006.257.09:01:00.98#ibcon#end of sib2, iclass 14, count 2 2006.257.09:01:00.98#ibcon#*mode == 0, iclass 14, count 2 2006.257.09:01:00.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.09:01:00.98#ibcon#[27=AT07-04\r\n] 2006.257.09:01:00.98#ibcon#*before write, iclass 14, count 2 2006.257.09:01:00.98#ibcon#enter sib2, iclass 14, count 2 2006.257.09:01:00.98#ibcon#flushed, iclass 14, count 2 2006.257.09:01:00.98#ibcon#about to write, iclass 14, count 2 2006.257.09:01:00.98#ibcon#wrote, iclass 14, count 2 2006.257.09:01:00.98#ibcon#about to read 3, iclass 14, count 2 2006.257.09:01:01.01#ibcon#read 3, iclass 14, count 2 2006.257.09:01:01.01#ibcon#about to read 4, iclass 14, count 2 2006.257.09:01:01.01#ibcon#read 4, iclass 14, count 2 2006.257.09:01:01.01#ibcon#about to read 5, iclass 14, count 2 2006.257.09:01:01.01#ibcon#read 5, iclass 14, count 2 2006.257.09:01:01.01#ibcon#about to read 6, iclass 14, count 2 2006.257.09:01:01.01#ibcon#read 6, iclass 14, count 2 2006.257.09:01:01.01#ibcon#end of sib2, iclass 14, count 2 2006.257.09:01:01.01#ibcon#*after write, iclass 14, count 2 2006.257.09:01:01.01#ibcon#*before return 0, iclass 14, count 2 2006.257.09:01:01.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:01:01.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:01:01.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.09:01:01.01#ibcon#ireg 7 cls_cnt 0 2006.257.09:01:01.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:01:01.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:01:01.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:01:01.13#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:01:01.13#ibcon#first serial, iclass 14, count 0 2006.257.09:01:01.13#ibcon#enter sib2, iclass 14, count 0 2006.257.09:01:01.13#ibcon#flushed, iclass 14, count 0 2006.257.09:01:01.13#ibcon#about to write, iclass 14, count 0 2006.257.09:01:01.13#ibcon#wrote, iclass 14, count 0 2006.257.09:01:01.13#ibcon#about to read 3, iclass 14, count 0 2006.257.09:01:01.15#ibcon#read 3, iclass 14, count 0 2006.257.09:01:01.15#ibcon#about to read 4, iclass 14, count 0 2006.257.09:01:01.15#ibcon#read 4, iclass 14, count 0 2006.257.09:01:01.15#ibcon#about to read 5, iclass 14, count 0 2006.257.09:01:01.15#ibcon#read 5, iclass 14, count 0 2006.257.09:01:01.15#ibcon#about to read 6, iclass 14, count 0 2006.257.09:01:01.15#ibcon#read 6, iclass 14, count 0 2006.257.09:01:01.15#ibcon#end of sib2, iclass 14, count 0 2006.257.09:01:01.15#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:01:01.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:01:01.15#ibcon#[27=USB\r\n] 2006.257.09:01:01.15#ibcon#*before write, iclass 14, count 0 2006.257.09:01:01.15#ibcon#enter sib2, iclass 14, count 0 2006.257.09:01:01.15#ibcon#flushed, iclass 14, count 0 2006.257.09:01:01.15#ibcon#about to write, iclass 14, count 0 2006.257.09:01:01.15#ibcon#wrote, iclass 14, count 0 2006.257.09:01:01.15#ibcon#about to read 3, iclass 14, count 0 2006.257.09:01:01.18#ibcon#read 3, iclass 14, count 0 2006.257.09:01:01.18#ibcon#about to read 4, iclass 14, count 0 2006.257.09:01:01.18#ibcon#read 4, iclass 14, count 0 2006.257.09:01:01.18#ibcon#about to read 5, iclass 14, count 0 2006.257.09:01:01.18#ibcon#read 5, iclass 14, count 0 2006.257.09:01:01.18#ibcon#about to read 6, iclass 14, count 0 2006.257.09:01:01.18#ibcon#read 6, iclass 14, count 0 2006.257.09:01:01.18#ibcon#end of sib2, iclass 14, count 0 2006.257.09:01:01.18#ibcon#*after write, iclass 14, count 0 2006.257.09:01:01.18#ibcon#*before return 0, iclass 14, count 0 2006.257.09:01:01.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:01:01.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:01:01.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:01:01.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:01:01.18$vck44/vblo=8,744.99 2006.257.09:01:01.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.09:01:01.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.09:01:01.18#ibcon#ireg 17 cls_cnt 0 2006.257.09:01:01.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:01:01.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:01:01.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:01:01.18#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:01:01.18#ibcon#first serial, iclass 16, count 0 2006.257.09:01:01.18#ibcon#enter sib2, iclass 16, count 0 2006.257.09:01:01.18#ibcon#flushed, iclass 16, count 0 2006.257.09:01:01.18#ibcon#about to write, iclass 16, count 0 2006.257.09:01:01.18#ibcon#wrote, iclass 16, count 0 2006.257.09:01:01.18#ibcon#about to read 3, iclass 16, count 0 2006.257.09:01:01.20#ibcon#read 3, iclass 16, count 0 2006.257.09:01:01.20#ibcon#about to read 4, iclass 16, count 0 2006.257.09:01:01.20#ibcon#read 4, iclass 16, count 0 2006.257.09:01:01.20#ibcon#about to read 5, iclass 16, count 0 2006.257.09:01:01.20#ibcon#read 5, iclass 16, count 0 2006.257.09:01:01.20#ibcon#about to read 6, iclass 16, count 0 2006.257.09:01:01.20#ibcon#read 6, iclass 16, count 0 2006.257.09:01:01.20#ibcon#end of sib2, iclass 16, count 0 2006.257.09:01:01.20#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:01:01.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:01:01.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:01:01.20#ibcon#*before write, iclass 16, count 0 2006.257.09:01:01.20#ibcon#enter sib2, iclass 16, count 0 2006.257.09:01:01.20#ibcon#flushed, iclass 16, count 0 2006.257.09:01:01.20#ibcon#about to write, iclass 16, count 0 2006.257.09:01:01.20#ibcon#wrote, iclass 16, count 0 2006.257.09:01:01.20#ibcon#about to read 3, iclass 16, count 0 2006.257.09:01:01.24#ibcon#read 3, iclass 16, count 0 2006.257.09:01:01.24#ibcon#about to read 4, iclass 16, count 0 2006.257.09:01:01.24#ibcon#read 4, iclass 16, count 0 2006.257.09:01:01.24#ibcon#about to read 5, iclass 16, count 0 2006.257.09:01:01.24#ibcon#read 5, iclass 16, count 0 2006.257.09:01:01.24#ibcon#about to read 6, iclass 16, count 0 2006.257.09:01:01.24#ibcon#read 6, iclass 16, count 0 2006.257.09:01:01.24#ibcon#end of sib2, iclass 16, count 0 2006.257.09:01:01.24#ibcon#*after write, iclass 16, count 0 2006.257.09:01:01.24#ibcon#*before return 0, iclass 16, count 0 2006.257.09:01:01.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:01:01.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:01:01.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:01:01.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:01:01.24$vck44/vb=8,4 2006.257.09:01:01.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.09:01:01.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.09:01:01.24#ibcon#ireg 11 cls_cnt 2 2006.257.09:01:01.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:01:01.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:01:01.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:01:01.30#ibcon#enter wrdev, iclass 18, count 2 2006.257.09:01:01.30#ibcon#first serial, iclass 18, count 2 2006.257.09:01:01.30#ibcon#enter sib2, iclass 18, count 2 2006.257.09:01:01.30#ibcon#flushed, iclass 18, count 2 2006.257.09:01:01.30#ibcon#about to write, iclass 18, count 2 2006.257.09:01:01.30#ibcon#wrote, iclass 18, count 2 2006.257.09:01:01.30#ibcon#about to read 3, iclass 18, count 2 2006.257.09:01:01.32#ibcon#read 3, iclass 18, count 2 2006.257.09:01:01.32#ibcon#about to read 4, iclass 18, count 2 2006.257.09:01:01.32#ibcon#read 4, iclass 18, count 2 2006.257.09:01:01.32#ibcon#about to read 5, iclass 18, count 2 2006.257.09:01:01.32#ibcon#read 5, iclass 18, count 2 2006.257.09:01:01.32#ibcon#about to read 6, iclass 18, count 2 2006.257.09:01:01.32#ibcon#read 6, iclass 18, count 2 2006.257.09:01:01.32#ibcon#end of sib2, iclass 18, count 2 2006.257.09:01:01.32#ibcon#*mode == 0, iclass 18, count 2 2006.257.09:01:01.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.09:01:01.32#ibcon#[27=AT08-04\r\n] 2006.257.09:01:01.32#ibcon#*before write, iclass 18, count 2 2006.257.09:01:01.32#ibcon#enter sib2, iclass 18, count 2 2006.257.09:01:01.32#ibcon#flushed, iclass 18, count 2 2006.257.09:01:01.32#ibcon#about to write, iclass 18, count 2 2006.257.09:01:01.32#ibcon#wrote, iclass 18, count 2 2006.257.09:01:01.32#ibcon#about to read 3, iclass 18, count 2 2006.257.09:01:01.35#ibcon#read 3, iclass 18, count 2 2006.257.09:01:01.35#ibcon#about to read 4, iclass 18, count 2 2006.257.09:01:01.35#ibcon#read 4, iclass 18, count 2 2006.257.09:01:01.35#ibcon#about to read 5, iclass 18, count 2 2006.257.09:01:01.35#ibcon#read 5, iclass 18, count 2 2006.257.09:01:01.35#ibcon#about to read 6, iclass 18, count 2 2006.257.09:01:01.35#ibcon#read 6, iclass 18, count 2 2006.257.09:01:01.35#ibcon#end of sib2, iclass 18, count 2 2006.257.09:01:01.35#ibcon#*after write, iclass 18, count 2 2006.257.09:01:01.35#ibcon#*before return 0, iclass 18, count 2 2006.257.09:01:01.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:01:01.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:01:01.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.09:01:01.35#ibcon#ireg 7 cls_cnt 0 2006.257.09:01:01.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:01:01.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:01:01.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:01:01.48#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:01:01.48#ibcon#first serial, iclass 18, count 0 2006.257.09:01:01.48#ibcon#enter sib2, iclass 18, count 0 2006.257.09:01:01.48#ibcon#flushed, iclass 18, count 0 2006.257.09:01:01.48#ibcon#about to write, iclass 18, count 0 2006.257.09:01:01.48#ibcon#wrote, iclass 18, count 0 2006.257.09:01:01.48#ibcon#about to read 3, iclass 18, count 0 2006.257.09:01:01.50#ibcon#read 3, iclass 18, count 0 2006.257.09:01:01.50#ibcon#about to read 4, iclass 18, count 0 2006.257.09:01:01.50#ibcon#read 4, iclass 18, count 0 2006.257.09:01:01.50#ibcon#about to read 5, iclass 18, count 0 2006.257.09:01:01.50#ibcon#read 5, iclass 18, count 0 2006.257.09:01:01.50#ibcon#about to read 6, iclass 18, count 0 2006.257.09:01:01.50#ibcon#read 6, iclass 18, count 0 2006.257.09:01:01.50#ibcon#end of sib2, iclass 18, count 0 2006.257.09:01:01.50#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:01:01.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:01:01.50#ibcon#[27=USB\r\n] 2006.257.09:01:01.50#ibcon#*before write, iclass 18, count 0 2006.257.09:01:01.50#ibcon#enter sib2, iclass 18, count 0 2006.257.09:01:01.50#ibcon#flushed, iclass 18, count 0 2006.257.09:01:01.50#ibcon#about to write, iclass 18, count 0 2006.257.09:01:01.50#ibcon#wrote, iclass 18, count 0 2006.257.09:01:01.50#ibcon#about to read 3, iclass 18, count 0 2006.257.09:01:01.53#ibcon#read 3, iclass 18, count 0 2006.257.09:01:01.53#ibcon#about to read 4, iclass 18, count 0 2006.257.09:01:01.53#ibcon#read 4, iclass 18, count 0 2006.257.09:01:01.53#ibcon#about to read 5, iclass 18, count 0 2006.257.09:01:01.53#ibcon#read 5, iclass 18, count 0 2006.257.09:01:01.53#ibcon#about to read 6, iclass 18, count 0 2006.257.09:01:01.53#ibcon#read 6, iclass 18, count 0 2006.257.09:01:01.53#ibcon#end of sib2, iclass 18, count 0 2006.257.09:01:01.53#ibcon#*after write, iclass 18, count 0 2006.257.09:01:01.53#ibcon#*before return 0, iclass 18, count 0 2006.257.09:01:01.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:01:01.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:01:01.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:01:01.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:01:01.53$vck44/vabw=wide 2006.257.09:01:01.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.09:01:01.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.09:01:01.53#ibcon#ireg 8 cls_cnt 0 2006.257.09:01:01.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:01:01.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:01:01.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:01:01.53#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:01:01.53#ibcon#first serial, iclass 20, count 0 2006.257.09:01:01.53#ibcon#enter sib2, iclass 20, count 0 2006.257.09:01:01.53#ibcon#flushed, iclass 20, count 0 2006.257.09:01:01.53#ibcon#about to write, iclass 20, count 0 2006.257.09:01:01.53#ibcon#wrote, iclass 20, count 0 2006.257.09:01:01.53#ibcon#about to read 3, iclass 20, count 0 2006.257.09:01:01.55#ibcon#read 3, iclass 20, count 0 2006.257.09:01:01.55#ibcon#about to read 4, iclass 20, count 0 2006.257.09:01:01.55#ibcon#read 4, iclass 20, count 0 2006.257.09:01:01.55#ibcon#about to read 5, iclass 20, count 0 2006.257.09:01:01.55#ibcon#read 5, iclass 20, count 0 2006.257.09:01:01.55#ibcon#about to read 6, iclass 20, count 0 2006.257.09:01:01.55#ibcon#read 6, iclass 20, count 0 2006.257.09:01:01.55#ibcon#end of sib2, iclass 20, count 0 2006.257.09:01:01.55#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:01:01.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:01:01.55#ibcon#[25=BW32\r\n] 2006.257.09:01:01.55#ibcon#*before write, iclass 20, count 0 2006.257.09:01:01.55#ibcon#enter sib2, iclass 20, count 0 2006.257.09:01:01.55#ibcon#flushed, iclass 20, count 0 2006.257.09:01:01.55#ibcon#about to write, iclass 20, count 0 2006.257.09:01:01.55#ibcon#wrote, iclass 20, count 0 2006.257.09:01:01.55#ibcon#about to read 3, iclass 20, count 0 2006.257.09:01:01.58#ibcon#read 3, iclass 20, count 0 2006.257.09:01:01.58#ibcon#about to read 4, iclass 20, count 0 2006.257.09:01:01.58#ibcon#read 4, iclass 20, count 0 2006.257.09:01:01.58#ibcon#about to read 5, iclass 20, count 0 2006.257.09:01:01.58#ibcon#read 5, iclass 20, count 0 2006.257.09:01:01.58#ibcon#about to read 6, iclass 20, count 0 2006.257.09:01:01.58#ibcon#read 6, iclass 20, count 0 2006.257.09:01:01.58#ibcon#end of sib2, iclass 20, count 0 2006.257.09:01:01.58#ibcon#*after write, iclass 20, count 0 2006.257.09:01:01.58#ibcon#*before return 0, iclass 20, count 0 2006.257.09:01:01.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:01:01.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:01:01.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:01:01.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:01:01.58$vck44/vbbw=wide 2006.257.09:01:01.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.09:01:01.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.09:01:01.58#ibcon#ireg 8 cls_cnt 0 2006.257.09:01:01.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:01:01.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:01:01.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:01:01.65#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:01:01.65#ibcon#first serial, iclass 22, count 0 2006.257.09:01:01.65#ibcon#enter sib2, iclass 22, count 0 2006.257.09:01:01.65#ibcon#flushed, iclass 22, count 0 2006.257.09:01:01.65#ibcon#about to write, iclass 22, count 0 2006.257.09:01:01.65#ibcon#wrote, iclass 22, count 0 2006.257.09:01:01.65#ibcon#about to read 3, iclass 22, count 0 2006.257.09:01:01.67#ibcon#read 3, iclass 22, count 0 2006.257.09:01:01.67#ibcon#about to read 4, iclass 22, count 0 2006.257.09:01:01.67#ibcon#read 4, iclass 22, count 0 2006.257.09:01:01.67#ibcon#about to read 5, iclass 22, count 0 2006.257.09:01:01.67#ibcon#read 5, iclass 22, count 0 2006.257.09:01:01.67#ibcon#about to read 6, iclass 22, count 0 2006.257.09:01:01.67#ibcon#read 6, iclass 22, count 0 2006.257.09:01:01.67#ibcon#end of sib2, iclass 22, count 0 2006.257.09:01:01.67#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:01:01.67#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:01:01.67#ibcon#[27=BW32\r\n] 2006.257.09:01:01.67#ibcon#*before write, iclass 22, count 0 2006.257.09:01:01.67#ibcon#enter sib2, iclass 22, count 0 2006.257.09:01:01.67#ibcon#flushed, iclass 22, count 0 2006.257.09:01:01.67#ibcon#about to write, iclass 22, count 0 2006.257.09:01:01.67#ibcon#wrote, iclass 22, count 0 2006.257.09:01:01.67#ibcon#about to read 3, iclass 22, count 0 2006.257.09:01:01.70#ibcon#read 3, iclass 22, count 0 2006.257.09:01:01.70#ibcon#about to read 4, iclass 22, count 0 2006.257.09:01:01.70#ibcon#read 4, iclass 22, count 0 2006.257.09:01:01.70#ibcon#about to read 5, iclass 22, count 0 2006.257.09:01:01.70#ibcon#read 5, iclass 22, count 0 2006.257.09:01:01.70#ibcon#about to read 6, iclass 22, count 0 2006.257.09:01:01.70#ibcon#read 6, iclass 22, count 0 2006.257.09:01:01.70#ibcon#end of sib2, iclass 22, count 0 2006.257.09:01:01.70#ibcon#*after write, iclass 22, count 0 2006.257.09:01:01.70#ibcon#*before return 0, iclass 22, count 0 2006.257.09:01:01.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:01:01.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:01:01.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:01:01.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:01:01.70$setupk4/ifdk4 2006.257.09:01:01.70$ifdk4/lo= 2006.257.09:01:01.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:01:01.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:01:01.70$ifdk4/patch= 2006.257.09:01:01.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:01:01.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:01:01.70$setupk4/!*+20s 2006.257.09:01:10.58#abcon#<5=/14 1.1 1.9 20.13 941013.2\r\n> 2006.257.09:01:10.60#abcon#{5=INTERFACE CLEAR} 2006.257.09:01:10.66#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:01:13.14#trakl#Source acquired 2006.257.09:01:15.14#flagr#flagr/antenna,acquired 2006.257.09:01:16.18$setupk4/"tpicd 2006.257.09:01:16.18$setupk4/echo=off 2006.257.09:01:16.18$setupk4/xlog=off 2006.257.09:01:16.18:!2006.257.09:07:02 2006.257.09:07:02.00:preob 2006.257.09:07:02.13/onsource/TRACKING 2006.257.09:07:02.13:!2006.257.09:07:12 2006.257.09:07:12.00:"tape 2006.257.09:07:12.00:"st=record 2006.257.09:07:12.00:data_valid=on 2006.257.09:07:12.00:midob 2006.257.09:07:12.13/onsource/TRACKING 2006.257.09:07:12.14/wx/20.02,1013.2,95 2006.257.09:07:12.23/cable/+6.4720E-03 2006.257.09:07:13.32/va/01,08,usb,yes,30,33 2006.257.09:07:13.32/va/02,07,usb,yes,33,34 2006.257.09:07:13.32/va/03,08,usb,yes,30,31 2006.257.09:07:13.32/va/04,07,usb,yes,34,36 2006.257.09:07:13.32/va/05,04,usb,yes,30,31 2006.257.09:07:13.32/va/06,04,usb,yes,34,34 2006.257.09:07:13.32/va/07,04,usb,yes,35,35 2006.257.09:07:13.32/va/08,04,usb,yes,29,36 2006.257.09:07:13.55/valo/01,524.99,yes,locked 2006.257.09:07:13.55/valo/02,534.99,yes,locked 2006.257.09:07:13.55/valo/03,564.99,yes,locked 2006.257.09:07:13.55/valo/04,624.99,yes,locked 2006.257.09:07:13.55/valo/05,734.99,yes,locked 2006.257.09:07:13.55/valo/06,814.99,yes,locked 2006.257.09:07:13.55/valo/07,864.99,yes,locked 2006.257.09:07:13.55/valo/08,884.99,yes,locked 2006.257.09:07:14.64/vb/01,04,usb,yes,31,28 2006.257.09:07:14.64/vb/02,05,usb,yes,29,29 2006.257.09:07:14.64/vb/03,04,usb,yes,30,33 2006.257.09:07:14.64/vb/04,05,usb,yes,30,29 2006.257.09:07:14.64/vb/05,04,usb,yes,26,29 2006.257.09:07:14.64/vb/06,04,usb,yes,31,27 2006.257.09:07:14.64/vb/07,04,usb,yes,31,31 2006.257.09:07:14.64/vb/08,04,usb,yes,28,32 2006.257.09:07:14.87/vblo/01,629.99,yes,locked 2006.257.09:07:14.87/vblo/02,634.99,yes,locked 2006.257.09:07:14.87/vblo/03,649.99,yes,locked 2006.257.09:07:14.87/vblo/04,679.99,yes,locked 2006.257.09:07:14.87/vblo/05,709.99,yes,locked 2006.257.09:07:14.87/vblo/06,719.99,yes,locked 2006.257.09:07:14.87/vblo/07,734.99,yes,locked 2006.257.09:07:14.87/vblo/08,744.99,yes,locked 2006.257.09:07:15.02/vabw/8 2006.257.09:07:15.17/vbbw/8 2006.257.09:07:15.26/xfe/off,on,14.7 2006.257.09:07:15.65/ifatt/23,28,28,28 2006.257.09:07:16.07/fmout-gps/S +4.63E-07 2006.257.09:07:16.11:!2006.257.09:07:52 2006.257.09:07:52.01:data_valid=off 2006.257.09:07:52.02:"et 2006.257.09:07:52.02:!+3s 2006.257.09:07:55.03:"tape 2006.257.09:07:55.03:postob 2006.257.09:07:55.23/cable/+6.4737E-03 2006.257.09:07:55.23/wx/20.01,1013.1,95 2006.257.09:07:55.29/fmout-gps/S +4.64E-07 2006.257.09:07:55.29:scan_name=257-0909,jd0609,80 2006.257.09:07:55.29:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.09:07:57.13#flagr#flagr/antenna,new-source 2006.257.09:07:57.13:checkk5 2006.257.09:07:57.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:07:57.88/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:07:58.28/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:07:58.69/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:07:59.07/chk_obsdata//k5ts1/T2570907??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:07:59.46/chk_obsdata//k5ts2/T2570907??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:07:59.86/chk_obsdata//k5ts3/T2570907??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:08:00.25/chk_obsdata//k5ts4/T2570907??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:08:01.01/k5log//k5ts1_log_newline 2006.257.09:08:01.75/k5log//k5ts2_log_newline 2006.257.09:08:02.48/k5log//k5ts3_log_newline 2006.257.09:08:03.21/k5log//k5ts4_log_newline 2006.257.09:08:03.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:08:03.23:setupk4=1 2006.257.09:08:03.23$setupk4/echo=on 2006.257.09:08:03.23$setupk4/pcalon 2006.257.09:08:03.23$pcalon/"no phase cal control is implemented here 2006.257.09:08:03.23$setupk4/"tpicd=stop 2006.257.09:08:03.23$setupk4/"rec=synch_on 2006.257.09:08:03.23$setupk4/"rec_mode=128 2006.257.09:08:03.23$setupk4/!* 2006.257.09:08:03.23$setupk4/recpk4 2006.257.09:08:03.23$recpk4/recpatch= 2006.257.09:08:03.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:08:03.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:08:03.24$setupk4/vck44 2006.257.09:08:03.24$vck44/valo=1,524.99 2006.257.09:08:03.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.09:08:03.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.09:08:03.24#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:03.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:03.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:03.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:03.24#ibcon#enter wrdev, iclass 11, count 0 2006.257.09:08:03.24#ibcon#first serial, iclass 11, count 0 2006.257.09:08:03.24#ibcon#enter sib2, iclass 11, count 0 2006.257.09:08:03.24#ibcon#flushed, iclass 11, count 0 2006.257.09:08:03.24#ibcon#about to write, iclass 11, count 0 2006.257.09:08:03.24#ibcon#wrote, iclass 11, count 0 2006.257.09:08:03.24#ibcon#about to read 3, iclass 11, count 0 2006.257.09:08:03.25#ibcon#read 3, iclass 11, count 0 2006.257.09:08:03.25#ibcon#about to read 4, iclass 11, count 0 2006.257.09:08:03.25#ibcon#read 4, iclass 11, count 0 2006.257.09:08:03.25#ibcon#about to read 5, iclass 11, count 0 2006.257.09:08:03.25#ibcon#read 5, iclass 11, count 0 2006.257.09:08:03.25#ibcon#about to read 6, iclass 11, count 0 2006.257.09:08:03.25#ibcon#read 6, iclass 11, count 0 2006.257.09:08:03.25#ibcon#end of sib2, iclass 11, count 0 2006.257.09:08:03.25#ibcon#*mode == 0, iclass 11, count 0 2006.257.09:08:03.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.09:08:03.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:08:03.25#ibcon#*before write, iclass 11, count 0 2006.257.09:08:03.25#ibcon#enter sib2, iclass 11, count 0 2006.257.09:08:03.25#ibcon#flushed, iclass 11, count 0 2006.257.09:08:03.25#ibcon#about to write, iclass 11, count 0 2006.257.09:08:03.25#ibcon#wrote, iclass 11, count 0 2006.257.09:08:03.25#ibcon#about to read 3, iclass 11, count 0 2006.257.09:08:03.30#ibcon#read 3, iclass 11, count 0 2006.257.09:08:03.30#ibcon#about to read 4, iclass 11, count 0 2006.257.09:08:03.30#ibcon#read 4, iclass 11, count 0 2006.257.09:08:03.30#ibcon#about to read 5, iclass 11, count 0 2006.257.09:08:03.30#ibcon#read 5, iclass 11, count 0 2006.257.09:08:03.30#ibcon#about to read 6, iclass 11, count 0 2006.257.09:08:03.30#ibcon#read 6, iclass 11, count 0 2006.257.09:08:03.30#ibcon#end of sib2, iclass 11, count 0 2006.257.09:08:03.30#ibcon#*after write, iclass 11, count 0 2006.257.09:08:03.30#ibcon#*before return 0, iclass 11, count 0 2006.257.09:08:03.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:03.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:03.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.09:08:03.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.09:08:03.31$vck44/va=1,8 2006.257.09:08:03.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.09:08:03.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.09:08:03.31#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:03.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:03.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:03.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:03.31#ibcon#enter wrdev, iclass 13, count 2 2006.257.09:08:03.31#ibcon#first serial, iclass 13, count 2 2006.257.09:08:03.31#ibcon#enter sib2, iclass 13, count 2 2006.257.09:08:03.31#ibcon#flushed, iclass 13, count 2 2006.257.09:08:03.31#ibcon#about to write, iclass 13, count 2 2006.257.09:08:03.31#ibcon#wrote, iclass 13, count 2 2006.257.09:08:03.31#ibcon#about to read 3, iclass 13, count 2 2006.257.09:08:03.32#ibcon#read 3, iclass 13, count 2 2006.257.09:08:03.32#ibcon#about to read 4, iclass 13, count 2 2006.257.09:08:03.32#ibcon#read 4, iclass 13, count 2 2006.257.09:08:03.32#ibcon#about to read 5, iclass 13, count 2 2006.257.09:08:03.32#ibcon#read 5, iclass 13, count 2 2006.257.09:08:03.32#ibcon#about to read 6, iclass 13, count 2 2006.257.09:08:03.32#ibcon#read 6, iclass 13, count 2 2006.257.09:08:03.32#ibcon#end of sib2, iclass 13, count 2 2006.257.09:08:03.32#ibcon#*mode == 0, iclass 13, count 2 2006.257.09:08:03.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.09:08:03.32#ibcon#[25=AT01-08\r\n] 2006.257.09:08:03.32#ibcon#*before write, iclass 13, count 2 2006.257.09:08:03.32#ibcon#enter sib2, iclass 13, count 2 2006.257.09:08:03.32#ibcon#flushed, iclass 13, count 2 2006.257.09:08:03.32#ibcon#about to write, iclass 13, count 2 2006.257.09:08:03.32#ibcon#wrote, iclass 13, count 2 2006.257.09:08:03.32#ibcon#about to read 3, iclass 13, count 2 2006.257.09:08:03.35#ibcon#read 3, iclass 13, count 2 2006.257.09:08:03.35#ibcon#about to read 4, iclass 13, count 2 2006.257.09:08:03.35#ibcon#read 4, iclass 13, count 2 2006.257.09:08:03.35#ibcon#about to read 5, iclass 13, count 2 2006.257.09:08:03.35#ibcon#read 5, iclass 13, count 2 2006.257.09:08:03.35#ibcon#about to read 6, iclass 13, count 2 2006.257.09:08:03.35#ibcon#read 6, iclass 13, count 2 2006.257.09:08:03.35#ibcon#end of sib2, iclass 13, count 2 2006.257.09:08:03.35#ibcon#*after write, iclass 13, count 2 2006.257.09:08:03.35#ibcon#*before return 0, iclass 13, count 2 2006.257.09:08:03.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:03.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:03.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.09:08:03.35#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:03.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:03.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:03.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:03.47#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:08:03.47#ibcon#first serial, iclass 13, count 0 2006.257.09:08:03.47#ibcon#enter sib2, iclass 13, count 0 2006.257.09:08:03.47#ibcon#flushed, iclass 13, count 0 2006.257.09:08:03.47#ibcon#about to write, iclass 13, count 0 2006.257.09:08:03.47#ibcon#wrote, iclass 13, count 0 2006.257.09:08:03.47#ibcon#about to read 3, iclass 13, count 0 2006.257.09:08:03.49#ibcon#read 3, iclass 13, count 0 2006.257.09:08:03.49#ibcon#about to read 4, iclass 13, count 0 2006.257.09:08:03.49#ibcon#read 4, iclass 13, count 0 2006.257.09:08:03.49#ibcon#about to read 5, iclass 13, count 0 2006.257.09:08:03.49#ibcon#read 5, iclass 13, count 0 2006.257.09:08:03.49#ibcon#about to read 6, iclass 13, count 0 2006.257.09:08:03.49#ibcon#read 6, iclass 13, count 0 2006.257.09:08:03.49#ibcon#end of sib2, iclass 13, count 0 2006.257.09:08:03.49#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:08:03.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:08:03.49#ibcon#[25=USB\r\n] 2006.257.09:08:03.49#ibcon#*before write, iclass 13, count 0 2006.257.09:08:03.49#ibcon#enter sib2, iclass 13, count 0 2006.257.09:08:03.49#ibcon#flushed, iclass 13, count 0 2006.257.09:08:03.49#ibcon#about to write, iclass 13, count 0 2006.257.09:08:03.49#ibcon#wrote, iclass 13, count 0 2006.257.09:08:03.49#ibcon#about to read 3, iclass 13, count 0 2006.257.09:08:03.52#ibcon#read 3, iclass 13, count 0 2006.257.09:08:03.52#ibcon#about to read 4, iclass 13, count 0 2006.257.09:08:03.52#ibcon#read 4, iclass 13, count 0 2006.257.09:08:03.52#ibcon#about to read 5, iclass 13, count 0 2006.257.09:08:03.52#ibcon#read 5, iclass 13, count 0 2006.257.09:08:03.52#ibcon#about to read 6, iclass 13, count 0 2006.257.09:08:03.52#ibcon#read 6, iclass 13, count 0 2006.257.09:08:03.52#ibcon#end of sib2, iclass 13, count 0 2006.257.09:08:03.52#ibcon#*after write, iclass 13, count 0 2006.257.09:08:03.52#ibcon#*before return 0, iclass 13, count 0 2006.257.09:08:03.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:03.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:03.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:08:03.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:08:03.52$vck44/valo=2,534.99 2006.257.09:08:03.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.09:08:03.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.09:08:03.52#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:03.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:03.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:03.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:03.52#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:08:03.52#ibcon#first serial, iclass 15, count 0 2006.257.09:08:03.52#ibcon#enter sib2, iclass 15, count 0 2006.257.09:08:03.52#ibcon#flushed, iclass 15, count 0 2006.257.09:08:03.52#ibcon#about to write, iclass 15, count 0 2006.257.09:08:03.52#ibcon#wrote, iclass 15, count 0 2006.257.09:08:03.52#ibcon#about to read 3, iclass 15, count 0 2006.257.09:08:03.54#ibcon#read 3, iclass 15, count 0 2006.257.09:08:03.54#ibcon#about to read 4, iclass 15, count 0 2006.257.09:08:03.54#ibcon#read 4, iclass 15, count 0 2006.257.09:08:03.54#ibcon#about to read 5, iclass 15, count 0 2006.257.09:08:03.54#ibcon#read 5, iclass 15, count 0 2006.257.09:08:03.54#ibcon#about to read 6, iclass 15, count 0 2006.257.09:08:03.54#ibcon#read 6, iclass 15, count 0 2006.257.09:08:03.54#ibcon#end of sib2, iclass 15, count 0 2006.257.09:08:03.54#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:08:03.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:08:03.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:08:03.54#ibcon#*before write, iclass 15, count 0 2006.257.09:08:03.54#ibcon#enter sib2, iclass 15, count 0 2006.257.09:08:03.54#ibcon#flushed, iclass 15, count 0 2006.257.09:08:03.54#ibcon#about to write, iclass 15, count 0 2006.257.09:08:03.54#ibcon#wrote, iclass 15, count 0 2006.257.09:08:03.54#ibcon#about to read 3, iclass 15, count 0 2006.257.09:08:03.58#ibcon#read 3, iclass 15, count 0 2006.257.09:08:03.58#ibcon#about to read 4, iclass 15, count 0 2006.257.09:08:03.58#ibcon#read 4, iclass 15, count 0 2006.257.09:08:03.58#ibcon#about to read 5, iclass 15, count 0 2006.257.09:08:03.58#ibcon#read 5, iclass 15, count 0 2006.257.09:08:03.58#ibcon#about to read 6, iclass 15, count 0 2006.257.09:08:03.58#ibcon#read 6, iclass 15, count 0 2006.257.09:08:03.58#ibcon#end of sib2, iclass 15, count 0 2006.257.09:08:03.58#ibcon#*after write, iclass 15, count 0 2006.257.09:08:03.58#ibcon#*before return 0, iclass 15, count 0 2006.257.09:08:03.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:03.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:03.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:08:03.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:08:03.58$vck44/va=2,7 2006.257.09:08:03.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.09:08:03.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.09:08:03.58#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:03.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:03.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:03.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:03.64#ibcon#enter wrdev, iclass 17, count 2 2006.257.09:08:03.64#ibcon#first serial, iclass 17, count 2 2006.257.09:08:03.64#ibcon#enter sib2, iclass 17, count 2 2006.257.09:08:03.64#ibcon#flushed, iclass 17, count 2 2006.257.09:08:03.64#ibcon#about to write, iclass 17, count 2 2006.257.09:08:03.64#ibcon#wrote, iclass 17, count 2 2006.257.09:08:03.64#ibcon#about to read 3, iclass 17, count 2 2006.257.09:08:03.66#ibcon#read 3, iclass 17, count 2 2006.257.09:08:03.66#ibcon#about to read 4, iclass 17, count 2 2006.257.09:08:03.66#ibcon#read 4, iclass 17, count 2 2006.257.09:08:03.66#ibcon#about to read 5, iclass 17, count 2 2006.257.09:08:03.66#ibcon#read 5, iclass 17, count 2 2006.257.09:08:03.66#ibcon#about to read 6, iclass 17, count 2 2006.257.09:08:03.66#ibcon#read 6, iclass 17, count 2 2006.257.09:08:03.66#ibcon#end of sib2, iclass 17, count 2 2006.257.09:08:03.66#ibcon#*mode == 0, iclass 17, count 2 2006.257.09:08:03.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.09:08:03.66#ibcon#[25=AT02-07\r\n] 2006.257.09:08:03.66#ibcon#*before write, iclass 17, count 2 2006.257.09:08:03.66#ibcon#enter sib2, iclass 17, count 2 2006.257.09:08:03.66#ibcon#flushed, iclass 17, count 2 2006.257.09:08:03.66#ibcon#about to write, iclass 17, count 2 2006.257.09:08:03.66#ibcon#wrote, iclass 17, count 2 2006.257.09:08:03.66#ibcon#about to read 3, iclass 17, count 2 2006.257.09:08:03.69#ibcon#read 3, iclass 17, count 2 2006.257.09:08:03.69#ibcon#about to read 4, iclass 17, count 2 2006.257.09:08:03.69#ibcon#read 4, iclass 17, count 2 2006.257.09:08:03.69#ibcon#about to read 5, iclass 17, count 2 2006.257.09:08:03.69#ibcon#read 5, iclass 17, count 2 2006.257.09:08:03.69#ibcon#about to read 6, iclass 17, count 2 2006.257.09:08:03.69#ibcon#read 6, iclass 17, count 2 2006.257.09:08:03.69#ibcon#end of sib2, iclass 17, count 2 2006.257.09:08:03.69#ibcon#*after write, iclass 17, count 2 2006.257.09:08:03.69#ibcon#*before return 0, iclass 17, count 2 2006.257.09:08:03.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:03.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:03.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.09:08:03.69#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:03.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:03.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:03.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:03.81#ibcon#enter wrdev, iclass 17, count 0 2006.257.09:08:03.81#ibcon#first serial, iclass 17, count 0 2006.257.09:08:03.81#ibcon#enter sib2, iclass 17, count 0 2006.257.09:08:03.81#ibcon#flushed, iclass 17, count 0 2006.257.09:08:03.81#ibcon#about to write, iclass 17, count 0 2006.257.09:08:03.81#ibcon#wrote, iclass 17, count 0 2006.257.09:08:03.81#ibcon#about to read 3, iclass 17, count 0 2006.257.09:08:03.83#ibcon#read 3, iclass 17, count 0 2006.257.09:08:03.83#ibcon#about to read 4, iclass 17, count 0 2006.257.09:08:03.83#ibcon#read 4, iclass 17, count 0 2006.257.09:08:03.83#ibcon#about to read 5, iclass 17, count 0 2006.257.09:08:03.83#ibcon#read 5, iclass 17, count 0 2006.257.09:08:03.83#ibcon#about to read 6, iclass 17, count 0 2006.257.09:08:03.83#ibcon#read 6, iclass 17, count 0 2006.257.09:08:03.83#ibcon#end of sib2, iclass 17, count 0 2006.257.09:08:03.83#ibcon#*mode == 0, iclass 17, count 0 2006.257.09:08:03.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.09:08:03.83#ibcon#[25=USB\r\n] 2006.257.09:08:03.83#ibcon#*before write, iclass 17, count 0 2006.257.09:08:03.83#ibcon#enter sib2, iclass 17, count 0 2006.257.09:08:03.83#ibcon#flushed, iclass 17, count 0 2006.257.09:08:03.83#ibcon#about to write, iclass 17, count 0 2006.257.09:08:03.83#ibcon#wrote, iclass 17, count 0 2006.257.09:08:03.83#ibcon#about to read 3, iclass 17, count 0 2006.257.09:08:03.86#ibcon#read 3, iclass 17, count 0 2006.257.09:08:03.86#ibcon#about to read 4, iclass 17, count 0 2006.257.09:08:03.86#ibcon#read 4, iclass 17, count 0 2006.257.09:08:03.86#ibcon#about to read 5, iclass 17, count 0 2006.257.09:08:03.86#ibcon#read 5, iclass 17, count 0 2006.257.09:08:03.86#ibcon#about to read 6, iclass 17, count 0 2006.257.09:08:03.86#ibcon#read 6, iclass 17, count 0 2006.257.09:08:03.86#ibcon#end of sib2, iclass 17, count 0 2006.257.09:08:03.86#ibcon#*after write, iclass 17, count 0 2006.257.09:08:03.86#ibcon#*before return 0, iclass 17, count 0 2006.257.09:08:03.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:03.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:03.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.09:08:03.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.09:08:03.86$vck44/valo=3,564.99 2006.257.09:08:03.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.09:08:03.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.09:08:03.86#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:03.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:03.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:03.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:03.86#ibcon#enter wrdev, iclass 19, count 0 2006.257.09:08:03.86#ibcon#first serial, iclass 19, count 0 2006.257.09:08:03.86#ibcon#enter sib2, iclass 19, count 0 2006.257.09:08:03.86#ibcon#flushed, iclass 19, count 0 2006.257.09:08:03.86#ibcon#about to write, iclass 19, count 0 2006.257.09:08:03.86#ibcon#wrote, iclass 19, count 0 2006.257.09:08:03.86#ibcon#about to read 3, iclass 19, count 0 2006.257.09:08:03.88#ibcon#read 3, iclass 19, count 0 2006.257.09:08:03.88#ibcon#about to read 4, iclass 19, count 0 2006.257.09:08:03.88#ibcon#read 4, iclass 19, count 0 2006.257.09:08:03.88#ibcon#about to read 5, iclass 19, count 0 2006.257.09:08:03.88#ibcon#read 5, iclass 19, count 0 2006.257.09:08:03.88#ibcon#about to read 6, iclass 19, count 0 2006.257.09:08:03.88#ibcon#read 6, iclass 19, count 0 2006.257.09:08:03.88#ibcon#end of sib2, iclass 19, count 0 2006.257.09:08:03.88#ibcon#*mode == 0, iclass 19, count 0 2006.257.09:08:03.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.09:08:03.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:08:03.88#ibcon#*before write, iclass 19, count 0 2006.257.09:08:03.88#ibcon#enter sib2, iclass 19, count 0 2006.257.09:08:03.88#ibcon#flushed, iclass 19, count 0 2006.257.09:08:03.88#ibcon#about to write, iclass 19, count 0 2006.257.09:08:03.88#ibcon#wrote, iclass 19, count 0 2006.257.09:08:03.88#ibcon#about to read 3, iclass 19, count 0 2006.257.09:08:03.92#ibcon#read 3, iclass 19, count 0 2006.257.09:08:03.92#ibcon#about to read 4, iclass 19, count 0 2006.257.09:08:03.92#ibcon#read 4, iclass 19, count 0 2006.257.09:08:03.92#ibcon#about to read 5, iclass 19, count 0 2006.257.09:08:03.92#ibcon#read 5, iclass 19, count 0 2006.257.09:08:03.92#ibcon#about to read 6, iclass 19, count 0 2006.257.09:08:03.92#ibcon#read 6, iclass 19, count 0 2006.257.09:08:03.92#ibcon#end of sib2, iclass 19, count 0 2006.257.09:08:03.92#ibcon#*after write, iclass 19, count 0 2006.257.09:08:03.92#ibcon#*before return 0, iclass 19, count 0 2006.257.09:08:03.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:03.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:03.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.09:08:03.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.09:08:03.92$vck44/va=3,8 2006.257.09:08:03.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.09:08:03.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.09:08:03.92#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:03.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:03.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:03.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:03.98#ibcon#enter wrdev, iclass 21, count 2 2006.257.09:08:03.98#ibcon#first serial, iclass 21, count 2 2006.257.09:08:03.98#ibcon#enter sib2, iclass 21, count 2 2006.257.09:08:03.98#ibcon#flushed, iclass 21, count 2 2006.257.09:08:03.98#ibcon#about to write, iclass 21, count 2 2006.257.09:08:03.98#ibcon#wrote, iclass 21, count 2 2006.257.09:08:03.98#ibcon#about to read 3, iclass 21, count 2 2006.257.09:08:04.00#ibcon#read 3, iclass 21, count 2 2006.257.09:08:04.00#ibcon#about to read 4, iclass 21, count 2 2006.257.09:08:04.00#ibcon#read 4, iclass 21, count 2 2006.257.09:08:04.00#ibcon#about to read 5, iclass 21, count 2 2006.257.09:08:04.00#ibcon#read 5, iclass 21, count 2 2006.257.09:08:04.00#ibcon#about to read 6, iclass 21, count 2 2006.257.09:08:04.00#ibcon#read 6, iclass 21, count 2 2006.257.09:08:04.00#ibcon#end of sib2, iclass 21, count 2 2006.257.09:08:04.00#ibcon#*mode == 0, iclass 21, count 2 2006.257.09:08:04.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.09:08:04.00#ibcon#[25=AT03-08\r\n] 2006.257.09:08:04.00#ibcon#*before write, iclass 21, count 2 2006.257.09:08:04.00#ibcon#enter sib2, iclass 21, count 2 2006.257.09:08:04.00#ibcon#flushed, iclass 21, count 2 2006.257.09:08:04.00#ibcon#about to write, iclass 21, count 2 2006.257.09:08:04.00#ibcon#wrote, iclass 21, count 2 2006.257.09:08:04.00#ibcon#about to read 3, iclass 21, count 2 2006.257.09:08:04.03#ibcon#read 3, iclass 21, count 2 2006.257.09:08:04.03#ibcon#about to read 4, iclass 21, count 2 2006.257.09:08:04.03#ibcon#read 4, iclass 21, count 2 2006.257.09:08:04.03#ibcon#about to read 5, iclass 21, count 2 2006.257.09:08:04.03#ibcon#read 5, iclass 21, count 2 2006.257.09:08:04.03#ibcon#about to read 6, iclass 21, count 2 2006.257.09:08:04.03#ibcon#read 6, iclass 21, count 2 2006.257.09:08:04.03#ibcon#end of sib2, iclass 21, count 2 2006.257.09:08:04.03#ibcon#*after write, iclass 21, count 2 2006.257.09:08:04.03#ibcon#*before return 0, iclass 21, count 2 2006.257.09:08:04.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:04.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:04.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.09:08:04.03#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:04.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:04.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:04.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:04.15#ibcon#enter wrdev, iclass 21, count 0 2006.257.09:08:04.15#ibcon#first serial, iclass 21, count 0 2006.257.09:08:04.15#ibcon#enter sib2, iclass 21, count 0 2006.257.09:08:04.15#ibcon#flushed, iclass 21, count 0 2006.257.09:08:04.15#ibcon#about to write, iclass 21, count 0 2006.257.09:08:04.15#ibcon#wrote, iclass 21, count 0 2006.257.09:08:04.15#ibcon#about to read 3, iclass 21, count 0 2006.257.09:08:04.17#ibcon#read 3, iclass 21, count 0 2006.257.09:08:04.17#ibcon#about to read 4, iclass 21, count 0 2006.257.09:08:04.17#ibcon#read 4, iclass 21, count 0 2006.257.09:08:04.17#ibcon#about to read 5, iclass 21, count 0 2006.257.09:08:04.17#ibcon#read 5, iclass 21, count 0 2006.257.09:08:04.17#ibcon#about to read 6, iclass 21, count 0 2006.257.09:08:04.17#ibcon#read 6, iclass 21, count 0 2006.257.09:08:04.17#ibcon#end of sib2, iclass 21, count 0 2006.257.09:08:04.17#ibcon#*mode == 0, iclass 21, count 0 2006.257.09:08:04.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.09:08:04.17#ibcon#[25=USB\r\n] 2006.257.09:08:04.17#ibcon#*before write, iclass 21, count 0 2006.257.09:08:04.17#ibcon#enter sib2, iclass 21, count 0 2006.257.09:08:04.17#ibcon#flushed, iclass 21, count 0 2006.257.09:08:04.17#ibcon#about to write, iclass 21, count 0 2006.257.09:08:04.17#ibcon#wrote, iclass 21, count 0 2006.257.09:08:04.17#ibcon#about to read 3, iclass 21, count 0 2006.257.09:08:04.20#ibcon#read 3, iclass 21, count 0 2006.257.09:08:04.20#ibcon#about to read 4, iclass 21, count 0 2006.257.09:08:04.20#ibcon#read 4, iclass 21, count 0 2006.257.09:08:04.20#ibcon#about to read 5, iclass 21, count 0 2006.257.09:08:04.20#ibcon#read 5, iclass 21, count 0 2006.257.09:08:04.20#ibcon#about to read 6, iclass 21, count 0 2006.257.09:08:04.20#ibcon#read 6, iclass 21, count 0 2006.257.09:08:04.20#ibcon#end of sib2, iclass 21, count 0 2006.257.09:08:04.20#ibcon#*after write, iclass 21, count 0 2006.257.09:08:04.20#ibcon#*before return 0, iclass 21, count 0 2006.257.09:08:04.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:04.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:04.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.09:08:04.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.09:08:04.20$vck44/valo=4,624.99 2006.257.09:08:04.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.09:08:04.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.09:08:04.20#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:04.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:04.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:04.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:04.20#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:08:04.20#ibcon#first serial, iclass 23, count 0 2006.257.09:08:04.20#ibcon#enter sib2, iclass 23, count 0 2006.257.09:08:04.20#ibcon#flushed, iclass 23, count 0 2006.257.09:08:04.20#ibcon#about to write, iclass 23, count 0 2006.257.09:08:04.20#ibcon#wrote, iclass 23, count 0 2006.257.09:08:04.20#ibcon#about to read 3, iclass 23, count 0 2006.257.09:08:04.22#ibcon#read 3, iclass 23, count 0 2006.257.09:08:04.22#ibcon#about to read 4, iclass 23, count 0 2006.257.09:08:04.22#ibcon#read 4, iclass 23, count 0 2006.257.09:08:04.22#ibcon#about to read 5, iclass 23, count 0 2006.257.09:08:04.22#ibcon#read 5, iclass 23, count 0 2006.257.09:08:04.22#ibcon#about to read 6, iclass 23, count 0 2006.257.09:08:04.22#ibcon#read 6, iclass 23, count 0 2006.257.09:08:04.22#ibcon#end of sib2, iclass 23, count 0 2006.257.09:08:04.22#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:08:04.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:08:04.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:08:04.22#ibcon#*before write, iclass 23, count 0 2006.257.09:08:04.22#ibcon#enter sib2, iclass 23, count 0 2006.257.09:08:04.22#ibcon#flushed, iclass 23, count 0 2006.257.09:08:04.22#ibcon#about to write, iclass 23, count 0 2006.257.09:08:04.22#ibcon#wrote, iclass 23, count 0 2006.257.09:08:04.22#ibcon#about to read 3, iclass 23, count 0 2006.257.09:08:04.26#ibcon#read 3, iclass 23, count 0 2006.257.09:08:04.26#ibcon#about to read 4, iclass 23, count 0 2006.257.09:08:04.26#ibcon#read 4, iclass 23, count 0 2006.257.09:08:04.26#ibcon#about to read 5, iclass 23, count 0 2006.257.09:08:04.26#ibcon#read 5, iclass 23, count 0 2006.257.09:08:04.26#ibcon#about to read 6, iclass 23, count 0 2006.257.09:08:04.26#ibcon#read 6, iclass 23, count 0 2006.257.09:08:04.26#ibcon#end of sib2, iclass 23, count 0 2006.257.09:08:04.26#ibcon#*after write, iclass 23, count 0 2006.257.09:08:04.26#ibcon#*before return 0, iclass 23, count 0 2006.257.09:08:04.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:04.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:04.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:08:04.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:08:04.26$vck44/va=4,7 2006.257.09:08:04.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.09:08:04.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.09:08:04.26#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:04.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:04.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:04.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:04.32#ibcon#enter wrdev, iclass 25, count 2 2006.257.09:08:04.32#ibcon#first serial, iclass 25, count 2 2006.257.09:08:04.32#ibcon#enter sib2, iclass 25, count 2 2006.257.09:08:04.32#ibcon#flushed, iclass 25, count 2 2006.257.09:08:04.32#ibcon#about to write, iclass 25, count 2 2006.257.09:08:04.32#ibcon#wrote, iclass 25, count 2 2006.257.09:08:04.32#ibcon#about to read 3, iclass 25, count 2 2006.257.09:08:04.34#ibcon#read 3, iclass 25, count 2 2006.257.09:08:04.34#ibcon#about to read 4, iclass 25, count 2 2006.257.09:08:04.34#ibcon#read 4, iclass 25, count 2 2006.257.09:08:04.34#ibcon#about to read 5, iclass 25, count 2 2006.257.09:08:04.34#ibcon#read 5, iclass 25, count 2 2006.257.09:08:04.34#ibcon#about to read 6, iclass 25, count 2 2006.257.09:08:04.34#ibcon#read 6, iclass 25, count 2 2006.257.09:08:04.34#ibcon#end of sib2, iclass 25, count 2 2006.257.09:08:04.34#ibcon#*mode == 0, iclass 25, count 2 2006.257.09:08:04.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.09:08:04.34#ibcon#[25=AT04-07\r\n] 2006.257.09:08:04.34#ibcon#*before write, iclass 25, count 2 2006.257.09:08:04.34#ibcon#enter sib2, iclass 25, count 2 2006.257.09:08:04.34#ibcon#flushed, iclass 25, count 2 2006.257.09:08:04.34#ibcon#about to write, iclass 25, count 2 2006.257.09:08:04.34#ibcon#wrote, iclass 25, count 2 2006.257.09:08:04.34#ibcon#about to read 3, iclass 25, count 2 2006.257.09:08:04.37#ibcon#read 3, iclass 25, count 2 2006.257.09:08:04.37#ibcon#about to read 4, iclass 25, count 2 2006.257.09:08:04.37#ibcon#read 4, iclass 25, count 2 2006.257.09:08:04.37#ibcon#about to read 5, iclass 25, count 2 2006.257.09:08:04.37#ibcon#read 5, iclass 25, count 2 2006.257.09:08:04.37#ibcon#about to read 6, iclass 25, count 2 2006.257.09:08:04.37#ibcon#read 6, iclass 25, count 2 2006.257.09:08:04.37#ibcon#end of sib2, iclass 25, count 2 2006.257.09:08:04.37#ibcon#*after write, iclass 25, count 2 2006.257.09:08:04.37#ibcon#*before return 0, iclass 25, count 2 2006.257.09:08:04.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:04.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:04.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.09:08:04.37#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:04.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:04.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:04.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:04.49#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:08:04.49#ibcon#first serial, iclass 25, count 0 2006.257.09:08:04.49#ibcon#enter sib2, iclass 25, count 0 2006.257.09:08:04.49#ibcon#flushed, iclass 25, count 0 2006.257.09:08:04.49#ibcon#about to write, iclass 25, count 0 2006.257.09:08:04.49#ibcon#wrote, iclass 25, count 0 2006.257.09:08:04.49#ibcon#about to read 3, iclass 25, count 0 2006.257.09:08:04.51#ibcon#read 3, iclass 25, count 0 2006.257.09:08:04.51#ibcon#about to read 4, iclass 25, count 0 2006.257.09:08:04.51#ibcon#read 4, iclass 25, count 0 2006.257.09:08:04.51#ibcon#about to read 5, iclass 25, count 0 2006.257.09:08:04.51#ibcon#read 5, iclass 25, count 0 2006.257.09:08:04.51#ibcon#about to read 6, iclass 25, count 0 2006.257.09:08:04.51#ibcon#read 6, iclass 25, count 0 2006.257.09:08:04.51#ibcon#end of sib2, iclass 25, count 0 2006.257.09:08:04.51#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:08:04.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:08:04.51#ibcon#[25=USB\r\n] 2006.257.09:08:04.51#ibcon#*before write, iclass 25, count 0 2006.257.09:08:04.51#ibcon#enter sib2, iclass 25, count 0 2006.257.09:08:04.51#ibcon#flushed, iclass 25, count 0 2006.257.09:08:04.51#ibcon#about to write, iclass 25, count 0 2006.257.09:08:04.51#ibcon#wrote, iclass 25, count 0 2006.257.09:08:04.51#ibcon#about to read 3, iclass 25, count 0 2006.257.09:08:04.54#ibcon#read 3, iclass 25, count 0 2006.257.09:08:04.54#ibcon#about to read 4, iclass 25, count 0 2006.257.09:08:04.54#ibcon#read 4, iclass 25, count 0 2006.257.09:08:04.54#ibcon#about to read 5, iclass 25, count 0 2006.257.09:08:04.54#ibcon#read 5, iclass 25, count 0 2006.257.09:08:04.54#ibcon#about to read 6, iclass 25, count 0 2006.257.09:08:04.54#ibcon#read 6, iclass 25, count 0 2006.257.09:08:04.54#ibcon#end of sib2, iclass 25, count 0 2006.257.09:08:04.54#ibcon#*after write, iclass 25, count 0 2006.257.09:08:04.54#ibcon#*before return 0, iclass 25, count 0 2006.257.09:08:04.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:04.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:04.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:08:04.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:08:04.54$vck44/valo=5,734.99 2006.257.09:08:04.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.09:08:04.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.09:08:04.54#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:04.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:08:04.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:08:04.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:08:04.54#ibcon#enter wrdev, iclass 27, count 0 2006.257.09:08:04.54#ibcon#first serial, iclass 27, count 0 2006.257.09:08:04.54#ibcon#enter sib2, iclass 27, count 0 2006.257.09:08:04.54#ibcon#flushed, iclass 27, count 0 2006.257.09:08:04.54#ibcon#about to write, iclass 27, count 0 2006.257.09:08:04.54#ibcon#wrote, iclass 27, count 0 2006.257.09:08:04.54#ibcon#about to read 3, iclass 27, count 0 2006.257.09:08:04.56#ibcon#read 3, iclass 27, count 0 2006.257.09:08:04.56#ibcon#about to read 4, iclass 27, count 0 2006.257.09:08:04.56#ibcon#read 4, iclass 27, count 0 2006.257.09:08:04.56#ibcon#about to read 5, iclass 27, count 0 2006.257.09:08:04.56#ibcon#read 5, iclass 27, count 0 2006.257.09:08:04.56#ibcon#about to read 6, iclass 27, count 0 2006.257.09:08:04.56#ibcon#read 6, iclass 27, count 0 2006.257.09:08:04.56#ibcon#end of sib2, iclass 27, count 0 2006.257.09:08:04.56#ibcon#*mode == 0, iclass 27, count 0 2006.257.09:08:04.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.09:08:04.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:08:04.56#ibcon#*before write, iclass 27, count 0 2006.257.09:08:04.56#ibcon#enter sib2, iclass 27, count 0 2006.257.09:08:04.56#ibcon#flushed, iclass 27, count 0 2006.257.09:08:04.56#ibcon#about to write, iclass 27, count 0 2006.257.09:08:04.56#ibcon#wrote, iclass 27, count 0 2006.257.09:08:04.56#ibcon#about to read 3, iclass 27, count 0 2006.257.09:08:04.60#ibcon#read 3, iclass 27, count 0 2006.257.09:08:04.60#ibcon#about to read 4, iclass 27, count 0 2006.257.09:08:04.60#ibcon#read 4, iclass 27, count 0 2006.257.09:08:04.60#ibcon#about to read 5, iclass 27, count 0 2006.257.09:08:04.60#ibcon#read 5, iclass 27, count 0 2006.257.09:08:04.60#ibcon#about to read 6, iclass 27, count 0 2006.257.09:08:04.60#ibcon#read 6, iclass 27, count 0 2006.257.09:08:04.60#ibcon#end of sib2, iclass 27, count 0 2006.257.09:08:04.60#ibcon#*after write, iclass 27, count 0 2006.257.09:08:04.60#ibcon#*before return 0, iclass 27, count 0 2006.257.09:08:04.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:08:04.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:08:04.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.09:08:04.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.09:08:04.60$vck44/va=5,4 2006.257.09:08:04.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.09:08:04.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.09:08:04.60#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:04.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:08:04.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:08:04.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:08:04.66#ibcon#enter wrdev, iclass 29, count 2 2006.257.09:08:04.66#ibcon#first serial, iclass 29, count 2 2006.257.09:08:04.66#ibcon#enter sib2, iclass 29, count 2 2006.257.09:08:04.66#ibcon#flushed, iclass 29, count 2 2006.257.09:08:04.66#ibcon#about to write, iclass 29, count 2 2006.257.09:08:04.66#ibcon#wrote, iclass 29, count 2 2006.257.09:08:04.66#ibcon#about to read 3, iclass 29, count 2 2006.257.09:08:04.68#ibcon#read 3, iclass 29, count 2 2006.257.09:08:04.68#ibcon#about to read 4, iclass 29, count 2 2006.257.09:08:04.68#ibcon#read 4, iclass 29, count 2 2006.257.09:08:04.68#ibcon#about to read 5, iclass 29, count 2 2006.257.09:08:04.68#ibcon#read 5, iclass 29, count 2 2006.257.09:08:04.68#ibcon#about to read 6, iclass 29, count 2 2006.257.09:08:04.68#ibcon#read 6, iclass 29, count 2 2006.257.09:08:04.68#ibcon#end of sib2, iclass 29, count 2 2006.257.09:08:04.68#ibcon#*mode == 0, iclass 29, count 2 2006.257.09:08:04.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.09:08:04.68#ibcon#[25=AT05-04\r\n] 2006.257.09:08:04.68#ibcon#*before write, iclass 29, count 2 2006.257.09:08:04.68#ibcon#enter sib2, iclass 29, count 2 2006.257.09:08:04.68#ibcon#flushed, iclass 29, count 2 2006.257.09:08:04.68#ibcon#about to write, iclass 29, count 2 2006.257.09:08:04.68#ibcon#wrote, iclass 29, count 2 2006.257.09:08:04.68#ibcon#about to read 3, iclass 29, count 2 2006.257.09:08:04.71#ibcon#read 3, iclass 29, count 2 2006.257.09:08:04.71#ibcon#about to read 4, iclass 29, count 2 2006.257.09:08:04.71#ibcon#read 4, iclass 29, count 2 2006.257.09:08:04.71#ibcon#about to read 5, iclass 29, count 2 2006.257.09:08:04.71#ibcon#read 5, iclass 29, count 2 2006.257.09:08:04.71#ibcon#about to read 6, iclass 29, count 2 2006.257.09:08:04.71#ibcon#read 6, iclass 29, count 2 2006.257.09:08:04.71#ibcon#end of sib2, iclass 29, count 2 2006.257.09:08:04.71#ibcon#*after write, iclass 29, count 2 2006.257.09:08:04.71#ibcon#*before return 0, iclass 29, count 2 2006.257.09:08:04.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:08:04.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:08:04.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.09:08:04.71#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:04.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:08:04.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:08:04.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:08:04.83#ibcon#enter wrdev, iclass 29, count 0 2006.257.09:08:04.83#ibcon#first serial, iclass 29, count 0 2006.257.09:08:04.83#ibcon#enter sib2, iclass 29, count 0 2006.257.09:08:04.83#ibcon#flushed, iclass 29, count 0 2006.257.09:08:04.83#ibcon#about to write, iclass 29, count 0 2006.257.09:08:04.83#ibcon#wrote, iclass 29, count 0 2006.257.09:08:04.83#ibcon#about to read 3, iclass 29, count 0 2006.257.09:08:04.85#ibcon#read 3, iclass 29, count 0 2006.257.09:08:04.85#ibcon#about to read 4, iclass 29, count 0 2006.257.09:08:04.85#ibcon#read 4, iclass 29, count 0 2006.257.09:08:04.85#ibcon#about to read 5, iclass 29, count 0 2006.257.09:08:04.85#ibcon#read 5, iclass 29, count 0 2006.257.09:08:04.85#ibcon#about to read 6, iclass 29, count 0 2006.257.09:08:04.85#ibcon#read 6, iclass 29, count 0 2006.257.09:08:04.85#ibcon#end of sib2, iclass 29, count 0 2006.257.09:08:04.85#ibcon#*mode == 0, iclass 29, count 0 2006.257.09:08:04.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.09:08:04.85#ibcon#[25=USB\r\n] 2006.257.09:08:04.85#ibcon#*before write, iclass 29, count 0 2006.257.09:08:04.85#ibcon#enter sib2, iclass 29, count 0 2006.257.09:08:04.85#ibcon#flushed, iclass 29, count 0 2006.257.09:08:04.85#ibcon#about to write, iclass 29, count 0 2006.257.09:08:04.85#ibcon#wrote, iclass 29, count 0 2006.257.09:08:04.85#ibcon#about to read 3, iclass 29, count 0 2006.257.09:08:04.88#ibcon#read 3, iclass 29, count 0 2006.257.09:08:04.88#ibcon#about to read 4, iclass 29, count 0 2006.257.09:08:04.88#ibcon#read 4, iclass 29, count 0 2006.257.09:08:04.88#ibcon#about to read 5, iclass 29, count 0 2006.257.09:08:04.88#ibcon#read 5, iclass 29, count 0 2006.257.09:08:04.88#ibcon#about to read 6, iclass 29, count 0 2006.257.09:08:04.88#ibcon#read 6, iclass 29, count 0 2006.257.09:08:04.88#ibcon#end of sib2, iclass 29, count 0 2006.257.09:08:04.88#ibcon#*after write, iclass 29, count 0 2006.257.09:08:04.88#ibcon#*before return 0, iclass 29, count 0 2006.257.09:08:04.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:08:04.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:08:04.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.09:08:04.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.09:08:04.88$vck44/valo=6,814.99 2006.257.09:08:04.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.09:08:04.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.09:08:04.88#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:04.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:08:04.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:08:04.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:08:04.88#ibcon#enter wrdev, iclass 31, count 0 2006.257.09:08:04.88#ibcon#first serial, iclass 31, count 0 2006.257.09:08:04.88#ibcon#enter sib2, iclass 31, count 0 2006.257.09:08:04.88#ibcon#flushed, iclass 31, count 0 2006.257.09:08:04.88#ibcon#about to write, iclass 31, count 0 2006.257.09:08:04.88#ibcon#wrote, iclass 31, count 0 2006.257.09:08:04.88#ibcon#about to read 3, iclass 31, count 0 2006.257.09:08:04.90#ibcon#read 3, iclass 31, count 0 2006.257.09:08:04.90#ibcon#about to read 4, iclass 31, count 0 2006.257.09:08:04.90#ibcon#read 4, iclass 31, count 0 2006.257.09:08:04.90#ibcon#about to read 5, iclass 31, count 0 2006.257.09:08:04.90#ibcon#read 5, iclass 31, count 0 2006.257.09:08:04.90#ibcon#about to read 6, iclass 31, count 0 2006.257.09:08:04.90#ibcon#read 6, iclass 31, count 0 2006.257.09:08:04.90#ibcon#end of sib2, iclass 31, count 0 2006.257.09:08:04.90#ibcon#*mode == 0, iclass 31, count 0 2006.257.09:08:04.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.09:08:04.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:08:04.90#ibcon#*before write, iclass 31, count 0 2006.257.09:08:04.90#ibcon#enter sib2, iclass 31, count 0 2006.257.09:08:04.90#ibcon#flushed, iclass 31, count 0 2006.257.09:08:04.90#ibcon#about to write, iclass 31, count 0 2006.257.09:08:04.90#ibcon#wrote, iclass 31, count 0 2006.257.09:08:04.90#ibcon#about to read 3, iclass 31, count 0 2006.257.09:08:04.94#ibcon#read 3, iclass 31, count 0 2006.257.09:08:04.94#ibcon#about to read 4, iclass 31, count 0 2006.257.09:08:04.94#ibcon#read 4, iclass 31, count 0 2006.257.09:08:04.94#ibcon#about to read 5, iclass 31, count 0 2006.257.09:08:04.94#ibcon#read 5, iclass 31, count 0 2006.257.09:08:04.94#ibcon#about to read 6, iclass 31, count 0 2006.257.09:08:04.94#ibcon#read 6, iclass 31, count 0 2006.257.09:08:04.94#ibcon#end of sib2, iclass 31, count 0 2006.257.09:08:04.94#ibcon#*after write, iclass 31, count 0 2006.257.09:08:04.94#ibcon#*before return 0, iclass 31, count 0 2006.257.09:08:04.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:08:04.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:08:04.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.09:08:04.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.09:08:04.94$vck44/va=6,4 2006.257.09:08:04.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.09:08:04.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.09:08:04.94#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:04.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:05.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:05.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:05.00#ibcon#enter wrdev, iclass 33, count 2 2006.257.09:08:05.00#ibcon#first serial, iclass 33, count 2 2006.257.09:08:05.00#ibcon#enter sib2, iclass 33, count 2 2006.257.09:08:05.00#ibcon#flushed, iclass 33, count 2 2006.257.09:08:05.00#ibcon#about to write, iclass 33, count 2 2006.257.09:08:05.00#ibcon#wrote, iclass 33, count 2 2006.257.09:08:05.00#ibcon#about to read 3, iclass 33, count 2 2006.257.09:08:05.02#ibcon#read 3, iclass 33, count 2 2006.257.09:08:05.02#ibcon#about to read 4, iclass 33, count 2 2006.257.09:08:05.02#ibcon#read 4, iclass 33, count 2 2006.257.09:08:05.02#ibcon#about to read 5, iclass 33, count 2 2006.257.09:08:05.02#ibcon#read 5, iclass 33, count 2 2006.257.09:08:05.02#ibcon#about to read 6, iclass 33, count 2 2006.257.09:08:05.02#ibcon#read 6, iclass 33, count 2 2006.257.09:08:05.02#ibcon#end of sib2, iclass 33, count 2 2006.257.09:08:05.02#ibcon#*mode == 0, iclass 33, count 2 2006.257.09:08:05.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.09:08:05.02#ibcon#[25=AT06-04\r\n] 2006.257.09:08:05.02#ibcon#*before write, iclass 33, count 2 2006.257.09:08:05.02#ibcon#enter sib2, iclass 33, count 2 2006.257.09:08:05.02#ibcon#flushed, iclass 33, count 2 2006.257.09:08:05.02#ibcon#about to write, iclass 33, count 2 2006.257.09:08:05.02#ibcon#wrote, iclass 33, count 2 2006.257.09:08:05.02#ibcon#about to read 3, iclass 33, count 2 2006.257.09:08:05.05#ibcon#read 3, iclass 33, count 2 2006.257.09:08:05.05#ibcon#about to read 4, iclass 33, count 2 2006.257.09:08:05.05#ibcon#read 4, iclass 33, count 2 2006.257.09:08:05.05#ibcon#about to read 5, iclass 33, count 2 2006.257.09:08:05.05#ibcon#read 5, iclass 33, count 2 2006.257.09:08:05.05#ibcon#about to read 6, iclass 33, count 2 2006.257.09:08:05.05#ibcon#read 6, iclass 33, count 2 2006.257.09:08:05.05#ibcon#end of sib2, iclass 33, count 2 2006.257.09:08:05.05#ibcon#*after write, iclass 33, count 2 2006.257.09:08:05.05#ibcon#*before return 0, iclass 33, count 2 2006.257.09:08:05.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:05.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:05.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.09:08:05.05#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:05.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:05.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:05.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:05.17#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:08:05.17#ibcon#first serial, iclass 33, count 0 2006.257.09:08:05.17#ibcon#enter sib2, iclass 33, count 0 2006.257.09:08:05.17#ibcon#flushed, iclass 33, count 0 2006.257.09:08:05.17#ibcon#about to write, iclass 33, count 0 2006.257.09:08:05.17#ibcon#wrote, iclass 33, count 0 2006.257.09:08:05.17#ibcon#about to read 3, iclass 33, count 0 2006.257.09:08:05.19#ibcon#read 3, iclass 33, count 0 2006.257.09:08:05.19#ibcon#about to read 4, iclass 33, count 0 2006.257.09:08:05.19#ibcon#read 4, iclass 33, count 0 2006.257.09:08:05.19#ibcon#about to read 5, iclass 33, count 0 2006.257.09:08:05.19#ibcon#read 5, iclass 33, count 0 2006.257.09:08:05.19#ibcon#about to read 6, iclass 33, count 0 2006.257.09:08:05.19#ibcon#read 6, iclass 33, count 0 2006.257.09:08:05.19#ibcon#end of sib2, iclass 33, count 0 2006.257.09:08:05.19#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:08:05.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:08:05.19#ibcon#[25=USB\r\n] 2006.257.09:08:05.19#ibcon#*before write, iclass 33, count 0 2006.257.09:08:05.19#ibcon#enter sib2, iclass 33, count 0 2006.257.09:08:05.19#ibcon#flushed, iclass 33, count 0 2006.257.09:08:05.19#ibcon#about to write, iclass 33, count 0 2006.257.09:08:05.19#ibcon#wrote, iclass 33, count 0 2006.257.09:08:05.19#ibcon#about to read 3, iclass 33, count 0 2006.257.09:08:05.22#ibcon#read 3, iclass 33, count 0 2006.257.09:08:05.22#ibcon#about to read 4, iclass 33, count 0 2006.257.09:08:05.22#ibcon#read 4, iclass 33, count 0 2006.257.09:08:05.22#ibcon#about to read 5, iclass 33, count 0 2006.257.09:08:05.22#ibcon#read 5, iclass 33, count 0 2006.257.09:08:05.22#ibcon#about to read 6, iclass 33, count 0 2006.257.09:08:05.22#ibcon#read 6, iclass 33, count 0 2006.257.09:08:05.22#ibcon#end of sib2, iclass 33, count 0 2006.257.09:08:05.22#ibcon#*after write, iclass 33, count 0 2006.257.09:08:05.22#ibcon#*before return 0, iclass 33, count 0 2006.257.09:08:05.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:05.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:05.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:08:05.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:08:05.22$vck44/valo=7,864.99 2006.257.09:08:05.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.09:08:05.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.09:08:05.22#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:05.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:05.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:05.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:05.22#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:08:05.22#ibcon#first serial, iclass 35, count 0 2006.257.09:08:05.22#ibcon#enter sib2, iclass 35, count 0 2006.257.09:08:05.22#ibcon#flushed, iclass 35, count 0 2006.257.09:08:05.22#ibcon#about to write, iclass 35, count 0 2006.257.09:08:05.22#ibcon#wrote, iclass 35, count 0 2006.257.09:08:05.22#ibcon#about to read 3, iclass 35, count 0 2006.257.09:08:05.24#ibcon#read 3, iclass 35, count 0 2006.257.09:08:05.24#ibcon#about to read 4, iclass 35, count 0 2006.257.09:08:05.24#ibcon#read 4, iclass 35, count 0 2006.257.09:08:05.24#ibcon#about to read 5, iclass 35, count 0 2006.257.09:08:05.24#ibcon#read 5, iclass 35, count 0 2006.257.09:08:05.24#ibcon#about to read 6, iclass 35, count 0 2006.257.09:08:05.24#ibcon#read 6, iclass 35, count 0 2006.257.09:08:05.24#ibcon#end of sib2, iclass 35, count 0 2006.257.09:08:05.24#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:08:05.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:08:05.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:08:05.24#ibcon#*before write, iclass 35, count 0 2006.257.09:08:05.24#ibcon#enter sib2, iclass 35, count 0 2006.257.09:08:05.24#ibcon#flushed, iclass 35, count 0 2006.257.09:08:05.24#ibcon#about to write, iclass 35, count 0 2006.257.09:08:05.24#ibcon#wrote, iclass 35, count 0 2006.257.09:08:05.24#ibcon#about to read 3, iclass 35, count 0 2006.257.09:08:05.28#ibcon#read 3, iclass 35, count 0 2006.257.09:08:05.28#ibcon#about to read 4, iclass 35, count 0 2006.257.09:08:05.28#ibcon#read 4, iclass 35, count 0 2006.257.09:08:05.28#ibcon#about to read 5, iclass 35, count 0 2006.257.09:08:05.28#ibcon#read 5, iclass 35, count 0 2006.257.09:08:05.28#ibcon#about to read 6, iclass 35, count 0 2006.257.09:08:05.28#ibcon#read 6, iclass 35, count 0 2006.257.09:08:05.28#ibcon#end of sib2, iclass 35, count 0 2006.257.09:08:05.28#ibcon#*after write, iclass 35, count 0 2006.257.09:08:05.28#ibcon#*before return 0, iclass 35, count 0 2006.257.09:08:05.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:05.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:05.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:08:05.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:08:05.28$vck44/va=7,4 2006.257.09:08:05.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.09:08:05.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.09:08:05.28#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:05.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:05.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:05.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:05.34#ibcon#enter wrdev, iclass 37, count 2 2006.257.09:08:05.34#ibcon#first serial, iclass 37, count 2 2006.257.09:08:05.34#ibcon#enter sib2, iclass 37, count 2 2006.257.09:08:05.34#ibcon#flushed, iclass 37, count 2 2006.257.09:08:05.34#ibcon#about to write, iclass 37, count 2 2006.257.09:08:05.34#ibcon#wrote, iclass 37, count 2 2006.257.09:08:05.34#ibcon#about to read 3, iclass 37, count 2 2006.257.09:08:05.36#ibcon#read 3, iclass 37, count 2 2006.257.09:08:05.36#ibcon#about to read 4, iclass 37, count 2 2006.257.09:08:05.36#ibcon#read 4, iclass 37, count 2 2006.257.09:08:05.36#ibcon#about to read 5, iclass 37, count 2 2006.257.09:08:05.36#ibcon#read 5, iclass 37, count 2 2006.257.09:08:05.36#ibcon#about to read 6, iclass 37, count 2 2006.257.09:08:05.36#ibcon#read 6, iclass 37, count 2 2006.257.09:08:05.36#ibcon#end of sib2, iclass 37, count 2 2006.257.09:08:05.36#ibcon#*mode == 0, iclass 37, count 2 2006.257.09:08:05.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.09:08:05.36#ibcon#[25=AT07-04\r\n] 2006.257.09:08:05.36#ibcon#*before write, iclass 37, count 2 2006.257.09:08:05.36#ibcon#enter sib2, iclass 37, count 2 2006.257.09:08:05.36#ibcon#flushed, iclass 37, count 2 2006.257.09:08:05.36#ibcon#about to write, iclass 37, count 2 2006.257.09:08:05.36#ibcon#wrote, iclass 37, count 2 2006.257.09:08:05.36#ibcon#about to read 3, iclass 37, count 2 2006.257.09:08:05.39#ibcon#read 3, iclass 37, count 2 2006.257.09:08:05.39#ibcon#about to read 4, iclass 37, count 2 2006.257.09:08:05.39#ibcon#read 4, iclass 37, count 2 2006.257.09:08:05.39#ibcon#about to read 5, iclass 37, count 2 2006.257.09:08:05.39#ibcon#read 5, iclass 37, count 2 2006.257.09:08:05.39#ibcon#about to read 6, iclass 37, count 2 2006.257.09:08:05.39#ibcon#read 6, iclass 37, count 2 2006.257.09:08:05.39#ibcon#end of sib2, iclass 37, count 2 2006.257.09:08:05.39#ibcon#*after write, iclass 37, count 2 2006.257.09:08:05.39#ibcon#*before return 0, iclass 37, count 2 2006.257.09:08:05.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:05.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:05.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.09:08:05.39#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:05.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:05.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:05.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:05.51#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:08:05.51#ibcon#first serial, iclass 37, count 0 2006.257.09:08:05.51#ibcon#enter sib2, iclass 37, count 0 2006.257.09:08:05.51#ibcon#flushed, iclass 37, count 0 2006.257.09:08:05.51#ibcon#about to write, iclass 37, count 0 2006.257.09:08:05.51#ibcon#wrote, iclass 37, count 0 2006.257.09:08:05.51#ibcon#about to read 3, iclass 37, count 0 2006.257.09:08:05.53#ibcon#read 3, iclass 37, count 0 2006.257.09:08:05.53#ibcon#about to read 4, iclass 37, count 0 2006.257.09:08:05.53#ibcon#read 4, iclass 37, count 0 2006.257.09:08:05.53#ibcon#about to read 5, iclass 37, count 0 2006.257.09:08:05.53#ibcon#read 5, iclass 37, count 0 2006.257.09:08:05.53#ibcon#about to read 6, iclass 37, count 0 2006.257.09:08:05.53#ibcon#read 6, iclass 37, count 0 2006.257.09:08:05.53#ibcon#end of sib2, iclass 37, count 0 2006.257.09:08:05.53#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:08:05.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:08:05.53#ibcon#[25=USB\r\n] 2006.257.09:08:05.53#ibcon#*before write, iclass 37, count 0 2006.257.09:08:05.53#ibcon#enter sib2, iclass 37, count 0 2006.257.09:08:05.53#ibcon#flushed, iclass 37, count 0 2006.257.09:08:05.53#ibcon#about to write, iclass 37, count 0 2006.257.09:08:05.53#ibcon#wrote, iclass 37, count 0 2006.257.09:08:05.53#ibcon#about to read 3, iclass 37, count 0 2006.257.09:08:05.56#ibcon#read 3, iclass 37, count 0 2006.257.09:08:05.56#ibcon#about to read 4, iclass 37, count 0 2006.257.09:08:05.56#ibcon#read 4, iclass 37, count 0 2006.257.09:08:05.56#ibcon#about to read 5, iclass 37, count 0 2006.257.09:08:05.56#ibcon#read 5, iclass 37, count 0 2006.257.09:08:05.56#ibcon#about to read 6, iclass 37, count 0 2006.257.09:08:05.56#ibcon#read 6, iclass 37, count 0 2006.257.09:08:05.56#ibcon#end of sib2, iclass 37, count 0 2006.257.09:08:05.56#ibcon#*after write, iclass 37, count 0 2006.257.09:08:05.56#ibcon#*before return 0, iclass 37, count 0 2006.257.09:08:05.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:05.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:05.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:08:05.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:08:05.56$vck44/valo=8,884.99 2006.257.09:08:05.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.09:08:05.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.09:08:05.56#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:05.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:05.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:05.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:05.56#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:08:05.56#ibcon#first serial, iclass 39, count 0 2006.257.09:08:05.56#ibcon#enter sib2, iclass 39, count 0 2006.257.09:08:05.56#ibcon#flushed, iclass 39, count 0 2006.257.09:08:05.56#ibcon#about to write, iclass 39, count 0 2006.257.09:08:05.56#ibcon#wrote, iclass 39, count 0 2006.257.09:08:05.56#ibcon#about to read 3, iclass 39, count 0 2006.257.09:08:05.58#ibcon#read 3, iclass 39, count 0 2006.257.09:08:05.58#ibcon#about to read 4, iclass 39, count 0 2006.257.09:08:05.58#ibcon#read 4, iclass 39, count 0 2006.257.09:08:05.58#ibcon#about to read 5, iclass 39, count 0 2006.257.09:08:05.58#ibcon#read 5, iclass 39, count 0 2006.257.09:08:05.58#ibcon#about to read 6, iclass 39, count 0 2006.257.09:08:05.58#ibcon#read 6, iclass 39, count 0 2006.257.09:08:05.58#ibcon#end of sib2, iclass 39, count 0 2006.257.09:08:05.58#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:08:05.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:08:05.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:08:05.58#ibcon#*before write, iclass 39, count 0 2006.257.09:08:05.58#ibcon#enter sib2, iclass 39, count 0 2006.257.09:08:05.58#ibcon#flushed, iclass 39, count 0 2006.257.09:08:05.58#ibcon#about to write, iclass 39, count 0 2006.257.09:08:05.58#ibcon#wrote, iclass 39, count 0 2006.257.09:08:05.58#ibcon#about to read 3, iclass 39, count 0 2006.257.09:08:05.62#ibcon#read 3, iclass 39, count 0 2006.257.09:08:05.62#ibcon#about to read 4, iclass 39, count 0 2006.257.09:08:05.62#ibcon#read 4, iclass 39, count 0 2006.257.09:08:05.62#ibcon#about to read 5, iclass 39, count 0 2006.257.09:08:05.62#ibcon#read 5, iclass 39, count 0 2006.257.09:08:05.62#ibcon#about to read 6, iclass 39, count 0 2006.257.09:08:05.62#ibcon#read 6, iclass 39, count 0 2006.257.09:08:05.62#ibcon#end of sib2, iclass 39, count 0 2006.257.09:08:05.62#ibcon#*after write, iclass 39, count 0 2006.257.09:08:05.62#ibcon#*before return 0, iclass 39, count 0 2006.257.09:08:05.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:05.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:05.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:08:05.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:08:05.62$vck44/va=8,4 2006.257.09:08:05.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.09:08:05.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.09:08:05.62#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:05.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:05.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:05.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:05.68#ibcon#enter wrdev, iclass 3, count 2 2006.257.09:08:05.68#ibcon#first serial, iclass 3, count 2 2006.257.09:08:05.68#ibcon#enter sib2, iclass 3, count 2 2006.257.09:08:05.68#ibcon#flushed, iclass 3, count 2 2006.257.09:08:05.68#ibcon#about to write, iclass 3, count 2 2006.257.09:08:05.68#ibcon#wrote, iclass 3, count 2 2006.257.09:08:05.68#ibcon#about to read 3, iclass 3, count 2 2006.257.09:08:05.70#ibcon#read 3, iclass 3, count 2 2006.257.09:08:05.70#ibcon#about to read 4, iclass 3, count 2 2006.257.09:08:05.70#ibcon#read 4, iclass 3, count 2 2006.257.09:08:05.70#ibcon#about to read 5, iclass 3, count 2 2006.257.09:08:05.70#ibcon#read 5, iclass 3, count 2 2006.257.09:08:05.70#ibcon#about to read 6, iclass 3, count 2 2006.257.09:08:05.70#ibcon#read 6, iclass 3, count 2 2006.257.09:08:05.70#ibcon#end of sib2, iclass 3, count 2 2006.257.09:08:05.70#ibcon#*mode == 0, iclass 3, count 2 2006.257.09:08:05.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.09:08:05.70#ibcon#[25=AT08-04\r\n] 2006.257.09:08:05.70#ibcon#*before write, iclass 3, count 2 2006.257.09:08:05.70#ibcon#enter sib2, iclass 3, count 2 2006.257.09:08:05.70#ibcon#flushed, iclass 3, count 2 2006.257.09:08:05.70#ibcon#about to write, iclass 3, count 2 2006.257.09:08:05.70#ibcon#wrote, iclass 3, count 2 2006.257.09:08:05.70#ibcon#about to read 3, iclass 3, count 2 2006.257.09:08:05.73#ibcon#read 3, iclass 3, count 2 2006.257.09:08:05.73#ibcon#about to read 4, iclass 3, count 2 2006.257.09:08:05.73#ibcon#read 4, iclass 3, count 2 2006.257.09:08:05.73#ibcon#about to read 5, iclass 3, count 2 2006.257.09:08:05.73#ibcon#read 5, iclass 3, count 2 2006.257.09:08:05.73#ibcon#about to read 6, iclass 3, count 2 2006.257.09:08:05.73#ibcon#read 6, iclass 3, count 2 2006.257.09:08:05.73#ibcon#end of sib2, iclass 3, count 2 2006.257.09:08:05.73#ibcon#*after write, iclass 3, count 2 2006.257.09:08:05.73#ibcon#*before return 0, iclass 3, count 2 2006.257.09:08:05.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:05.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:05.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.09:08:05.73#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:05.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:05.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:05.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:05.85#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:08:05.85#ibcon#first serial, iclass 3, count 0 2006.257.09:08:05.85#ibcon#enter sib2, iclass 3, count 0 2006.257.09:08:05.85#ibcon#flushed, iclass 3, count 0 2006.257.09:08:05.85#ibcon#about to write, iclass 3, count 0 2006.257.09:08:05.85#ibcon#wrote, iclass 3, count 0 2006.257.09:08:05.85#ibcon#about to read 3, iclass 3, count 0 2006.257.09:08:05.87#ibcon#read 3, iclass 3, count 0 2006.257.09:08:05.87#ibcon#about to read 4, iclass 3, count 0 2006.257.09:08:05.87#ibcon#read 4, iclass 3, count 0 2006.257.09:08:05.87#ibcon#about to read 5, iclass 3, count 0 2006.257.09:08:05.87#ibcon#read 5, iclass 3, count 0 2006.257.09:08:05.87#ibcon#about to read 6, iclass 3, count 0 2006.257.09:08:05.87#ibcon#read 6, iclass 3, count 0 2006.257.09:08:05.87#ibcon#end of sib2, iclass 3, count 0 2006.257.09:08:05.87#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:08:05.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:08:05.87#ibcon#[25=USB\r\n] 2006.257.09:08:05.87#ibcon#*before write, iclass 3, count 0 2006.257.09:08:05.87#ibcon#enter sib2, iclass 3, count 0 2006.257.09:08:05.87#ibcon#flushed, iclass 3, count 0 2006.257.09:08:05.87#ibcon#about to write, iclass 3, count 0 2006.257.09:08:05.87#ibcon#wrote, iclass 3, count 0 2006.257.09:08:05.87#ibcon#about to read 3, iclass 3, count 0 2006.257.09:08:05.90#ibcon#read 3, iclass 3, count 0 2006.257.09:08:05.90#ibcon#about to read 4, iclass 3, count 0 2006.257.09:08:05.90#ibcon#read 4, iclass 3, count 0 2006.257.09:08:05.90#ibcon#about to read 5, iclass 3, count 0 2006.257.09:08:05.90#ibcon#read 5, iclass 3, count 0 2006.257.09:08:05.90#ibcon#about to read 6, iclass 3, count 0 2006.257.09:08:05.90#ibcon#read 6, iclass 3, count 0 2006.257.09:08:05.90#ibcon#end of sib2, iclass 3, count 0 2006.257.09:08:05.90#ibcon#*after write, iclass 3, count 0 2006.257.09:08:05.90#ibcon#*before return 0, iclass 3, count 0 2006.257.09:08:05.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:05.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:05.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:08:05.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:08:05.90$vck44/vblo=1,629.99 2006.257.09:08:05.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.09:08:05.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.09:08:05.90#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:05.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:05.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:05.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:05.90#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:08:05.90#ibcon#first serial, iclass 5, count 0 2006.257.09:08:05.90#ibcon#enter sib2, iclass 5, count 0 2006.257.09:08:05.90#ibcon#flushed, iclass 5, count 0 2006.257.09:08:05.90#ibcon#about to write, iclass 5, count 0 2006.257.09:08:05.90#ibcon#wrote, iclass 5, count 0 2006.257.09:08:05.90#ibcon#about to read 3, iclass 5, count 0 2006.257.09:08:05.92#ibcon#read 3, iclass 5, count 0 2006.257.09:08:05.92#ibcon#about to read 4, iclass 5, count 0 2006.257.09:08:05.92#ibcon#read 4, iclass 5, count 0 2006.257.09:08:05.92#ibcon#about to read 5, iclass 5, count 0 2006.257.09:08:05.92#ibcon#read 5, iclass 5, count 0 2006.257.09:08:05.92#ibcon#about to read 6, iclass 5, count 0 2006.257.09:08:05.92#ibcon#read 6, iclass 5, count 0 2006.257.09:08:05.92#ibcon#end of sib2, iclass 5, count 0 2006.257.09:08:05.92#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:08:05.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:08:05.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:08:05.92#ibcon#*before write, iclass 5, count 0 2006.257.09:08:05.92#ibcon#enter sib2, iclass 5, count 0 2006.257.09:08:05.92#ibcon#flushed, iclass 5, count 0 2006.257.09:08:05.92#ibcon#about to write, iclass 5, count 0 2006.257.09:08:05.92#ibcon#wrote, iclass 5, count 0 2006.257.09:08:05.92#ibcon#about to read 3, iclass 5, count 0 2006.257.09:08:05.96#ibcon#read 3, iclass 5, count 0 2006.257.09:08:05.96#ibcon#about to read 4, iclass 5, count 0 2006.257.09:08:05.96#ibcon#read 4, iclass 5, count 0 2006.257.09:08:05.96#ibcon#about to read 5, iclass 5, count 0 2006.257.09:08:05.96#ibcon#read 5, iclass 5, count 0 2006.257.09:08:05.96#ibcon#about to read 6, iclass 5, count 0 2006.257.09:08:05.96#ibcon#read 6, iclass 5, count 0 2006.257.09:08:05.96#ibcon#end of sib2, iclass 5, count 0 2006.257.09:08:05.96#ibcon#*after write, iclass 5, count 0 2006.257.09:08:05.96#ibcon#*before return 0, iclass 5, count 0 2006.257.09:08:05.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:05.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:05.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:08:05.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:08:05.96$vck44/vb=1,4 2006.257.09:08:05.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.09:08:05.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.09:08:05.96#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:05.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:08:05.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:08:05.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:08:05.96#ibcon#enter wrdev, iclass 7, count 2 2006.257.09:08:05.96#ibcon#first serial, iclass 7, count 2 2006.257.09:08:05.96#ibcon#enter sib2, iclass 7, count 2 2006.257.09:08:05.96#ibcon#flushed, iclass 7, count 2 2006.257.09:08:05.96#ibcon#about to write, iclass 7, count 2 2006.257.09:08:05.96#ibcon#wrote, iclass 7, count 2 2006.257.09:08:05.96#ibcon#about to read 3, iclass 7, count 2 2006.257.09:08:05.98#ibcon#read 3, iclass 7, count 2 2006.257.09:08:05.98#ibcon#about to read 4, iclass 7, count 2 2006.257.09:08:05.98#ibcon#read 4, iclass 7, count 2 2006.257.09:08:05.98#ibcon#about to read 5, iclass 7, count 2 2006.257.09:08:05.98#ibcon#read 5, iclass 7, count 2 2006.257.09:08:05.98#ibcon#about to read 6, iclass 7, count 2 2006.257.09:08:05.98#ibcon#read 6, iclass 7, count 2 2006.257.09:08:05.98#ibcon#end of sib2, iclass 7, count 2 2006.257.09:08:05.98#ibcon#*mode == 0, iclass 7, count 2 2006.257.09:08:05.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.09:08:05.98#ibcon#[27=AT01-04\r\n] 2006.257.09:08:05.98#ibcon#*before write, iclass 7, count 2 2006.257.09:08:05.98#ibcon#enter sib2, iclass 7, count 2 2006.257.09:08:05.98#ibcon#flushed, iclass 7, count 2 2006.257.09:08:05.98#ibcon#about to write, iclass 7, count 2 2006.257.09:08:05.98#ibcon#wrote, iclass 7, count 2 2006.257.09:08:05.98#ibcon#about to read 3, iclass 7, count 2 2006.257.09:08:06.01#ibcon#read 3, iclass 7, count 2 2006.257.09:08:06.01#ibcon#about to read 4, iclass 7, count 2 2006.257.09:08:06.01#ibcon#read 4, iclass 7, count 2 2006.257.09:08:06.01#ibcon#about to read 5, iclass 7, count 2 2006.257.09:08:06.01#ibcon#read 5, iclass 7, count 2 2006.257.09:08:06.01#ibcon#about to read 6, iclass 7, count 2 2006.257.09:08:06.01#ibcon#read 6, iclass 7, count 2 2006.257.09:08:06.01#ibcon#end of sib2, iclass 7, count 2 2006.257.09:08:06.01#ibcon#*after write, iclass 7, count 2 2006.257.09:08:06.01#ibcon#*before return 0, iclass 7, count 2 2006.257.09:08:06.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:08:06.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:08:06.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.09:08:06.01#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:06.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:08:06.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:08:06.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:08:06.13#ibcon#enter wrdev, iclass 7, count 0 2006.257.09:08:06.13#ibcon#first serial, iclass 7, count 0 2006.257.09:08:06.13#ibcon#enter sib2, iclass 7, count 0 2006.257.09:08:06.13#ibcon#flushed, iclass 7, count 0 2006.257.09:08:06.13#ibcon#about to write, iclass 7, count 0 2006.257.09:08:06.13#ibcon#wrote, iclass 7, count 0 2006.257.09:08:06.13#ibcon#about to read 3, iclass 7, count 0 2006.257.09:08:06.15#ibcon#read 3, iclass 7, count 0 2006.257.09:08:06.15#ibcon#about to read 4, iclass 7, count 0 2006.257.09:08:06.15#ibcon#read 4, iclass 7, count 0 2006.257.09:08:06.15#ibcon#about to read 5, iclass 7, count 0 2006.257.09:08:06.15#ibcon#read 5, iclass 7, count 0 2006.257.09:08:06.15#ibcon#about to read 6, iclass 7, count 0 2006.257.09:08:06.15#ibcon#read 6, iclass 7, count 0 2006.257.09:08:06.15#ibcon#end of sib2, iclass 7, count 0 2006.257.09:08:06.15#ibcon#*mode == 0, iclass 7, count 0 2006.257.09:08:06.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.09:08:06.15#ibcon#[27=USB\r\n] 2006.257.09:08:06.15#ibcon#*before write, iclass 7, count 0 2006.257.09:08:06.15#ibcon#enter sib2, iclass 7, count 0 2006.257.09:08:06.15#ibcon#flushed, iclass 7, count 0 2006.257.09:08:06.15#ibcon#about to write, iclass 7, count 0 2006.257.09:08:06.15#ibcon#wrote, iclass 7, count 0 2006.257.09:08:06.15#ibcon#about to read 3, iclass 7, count 0 2006.257.09:08:06.18#ibcon#read 3, iclass 7, count 0 2006.257.09:08:06.18#ibcon#about to read 4, iclass 7, count 0 2006.257.09:08:06.18#ibcon#read 4, iclass 7, count 0 2006.257.09:08:06.18#ibcon#about to read 5, iclass 7, count 0 2006.257.09:08:06.18#ibcon#read 5, iclass 7, count 0 2006.257.09:08:06.18#ibcon#about to read 6, iclass 7, count 0 2006.257.09:08:06.18#ibcon#read 6, iclass 7, count 0 2006.257.09:08:06.18#ibcon#end of sib2, iclass 7, count 0 2006.257.09:08:06.18#ibcon#*after write, iclass 7, count 0 2006.257.09:08:06.18#ibcon#*before return 0, iclass 7, count 0 2006.257.09:08:06.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:08:06.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:08:06.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.09:08:06.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.09:08:06.18$vck44/vblo=2,634.99 2006.257.09:08:06.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.09:08:06.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.09:08:06.18#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:06.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:06.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:06.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:06.18#ibcon#enter wrdev, iclass 11, count 0 2006.257.09:08:06.18#ibcon#first serial, iclass 11, count 0 2006.257.09:08:06.18#ibcon#enter sib2, iclass 11, count 0 2006.257.09:08:06.18#ibcon#flushed, iclass 11, count 0 2006.257.09:08:06.18#ibcon#about to write, iclass 11, count 0 2006.257.09:08:06.18#ibcon#wrote, iclass 11, count 0 2006.257.09:08:06.18#ibcon#about to read 3, iclass 11, count 0 2006.257.09:08:06.20#ibcon#read 3, iclass 11, count 0 2006.257.09:08:06.20#ibcon#about to read 4, iclass 11, count 0 2006.257.09:08:06.20#ibcon#read 4, iclass 11, count 0 2006.257.09:08:06.20#ibcon#about to read 5, iclass 11, count 0 2006.257.09:08:06.20#ibcon#read 5, iclass 11, count 0 2006.257.09:08:06.20#ibcon#about to read 6, iclass 11, count 0 2006.257.09:08:06.20#ibcon#read 6, iclass 11, count 0 2006.257.09:08:06.20#ibcon#end of sib2, iclass 11, count 0 2006.257.09:08:06.20#ibcon#*mode == 0, iclass 11, count 0 2006.257.09:08:06.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.09:08:06.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:08:06.20#ibcon#*before write, iclass 11, count 0 2006.257.09:08:06.20#ibcon#enter sib2, iclass 11, count 0 2006.257.09:08:06.20#ibcon#flushed, iclass 11, count 0 2006.257.09:08:06.20#ibcon#about to write, iclass 11, count 0 2006.257.09:08:06.20#ibcon#wrote, iclass 11, count 0 2006.257.09:08:06.20#ibcon#about to read 3, iclass 11, count 0 2006.257.09:08:06.24#ibcon#read 3, iclass 11, count 0 2006.257.09:08:06.24#ibcon#about to read 4, iclass 11, count 0 2006.257.09:08:06.24#ibcon#read 4, iclass 11, count 0 2006.257.09:08:06.24#ibcon#about to read 5, iclass 11, count 0 2006.257.09:08:06.24#ibcon#read 5, iclass 11, count 0 2006.257.09:08:06.24#ibcon#about to read 6, iclass 11, count 0 2006.257.09:08:06.24#ibcon#read 6, iclass 11, count 0 2006.257.09:08:06.24#ibcon#end of sib2, iclass 11, count 0 2006.257.09:08:06.24#ibcon#*after write, iclass 11, count 0 2006.257.09:08:06.24#ibcon#*before return 0, iclass 11, count 0 2006.257.09:08:06.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:06.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:08:06.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.09:08:06.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.09:08:06.24$vck44/vb=2,5 2006.257.09:08:06.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.09:08:06.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.09:08:06.24#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:06.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:06.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:06.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:06.30#ibcon#enter wrdev, iclass 13, count 2 2006.257.09:08:06.30#ibcon#first serial, iclass 13, count 2 2006.257.09:08:06.30#ibcon#enter sib2, iclass 13, count 2 2006.257.09:08:06.30#ibcon#flushed, iclass 13, count 2 2006.257.09:08:06.30#ibcon#about to write, iclass 13, count 2 2006.257.09:08:06.30#ibcon#wrote, iclass 13, count 2 2006.257.09:08:06.30#ibcon#about to read 3, iclass 13, count 2 2006.257.09:08:06.32#ibcon#read 3, iclass 13, count 2 2006.257.09:08:06.32#ibcon#about to read 4, iclass 13, count 2 2006.257.09:08:06.32#ibcon#read 4, iclass 13, count 2 2006.257.09:08:06.32#ibcon#about to read 5, iclass 13, count 2 2006.257.09:08:06.32#ibcon#read 5, iclass 13, count 2 2006.257.09:08:06.32#ibcon#about to read 6, iclass 13, count 2 2006.257.09:08:06.32#ibcon#read 6, iclass 13, count 2 2006.257.09:08:06.32#ibcon#end of sib2, iclass 13, count 2 2006.257.09:08:06.32#ibcon#*mode == 0, iclass 13, count 2 2006.257.09:08:06.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.09:08:06.32#ibcon#[27=AT02-05\r\n] 2006.257.09:08:06.32#ibcon#*before write, iclass 13, count 2 2006.257.09:08:06.32#ibcon#enter sib2, iclass 13, count 2 2006.257.09:08:06.32#ibcon#flushed, iclass 13, count 2 2006.257.09:08:06.32#ibcon#about to write, iclass 13, count 2 2006.257.09:08:06.32#ibcon#wrote, iclass 13, count 2 2006.257.09:08:06.32#ibcon#about to read 3, iclass 13, count 2 2006.257.09:08:06.35#ibcon#read 3, iclass 13, count 2 2006.257.09:08:06.35#ibcon#about to read 4, iclass 13, count 2 2006.257.09:08:06.35#ibcon#read 4, iclass 13, count 2 2006.257.09:08:06.35#ibcon#about to read 5, iclass 13, count 2 2006.257.09:08:06.35#ibcon#read 5, iclass 13, count 2 2006.257.09:08:06.35#ibcon#about to read 6, iclass 13, count 2 2006.257.09:08:06.35#ibcon#read 6, iclass 13, count 2 2006.257.09:08:06.35#ibcon#end of sib2, iclass 13, count 2 2006.257.09:08:06.35#ibcon#*after write, iclass 13, count 2 2006.257.09:08:06.35#ibcon#*before return 0, iclass 13, count 2 2006.257.09:08:06.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:06.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:08:06.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.09:08:06.35#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:06.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:06.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:06.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:06.47#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:08:06.47#ibcon#first serial, iclass 13, count 0 2006.257.09:08:06.47#ibcon#enter sib2, iclass 13, count 0 2006.257.09:08:06.47#ibcon#flushed, iclass 13, count 0 2006.257.09:08:06.47#ibcon#about to write, iclass 13, count 0 2006.257.09:08:06.47#ibcon#wrote, iclass 13, count 0 2006.257.09:08:06.47#ibcon#about to read 3, iclass 13, count 0 2006.257.09:08:06.49#ibcon#read 3, iclass 13, count 0 2006.257.09:08:06.49#ibcon#about to read 4, iclass 13, count 0 2006.257.09:08:06.49#ibcon#read 4, iclass 13, count 0 2006.257.09:08:06.49#ibcon#about to read 5, iclass 13, count 0 2006.257.09:08:06.49#ibcon#read 5, iclass 13, count 0 2006.257.09:08:06.49#ibcon#about to read 6, iclass 13, count 0 2006.257.09:08:06.49#ibcon#read 6, iclass 13, count 0 2006.257.09:08:06.49#ibcon#end of sib2, iclass 13, count 0 2006.257.09:08:06.49#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:08:06.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:08:06.49#ibcon#[27=USB\r\n] 2006.257.09:08:06.49#ibcon#*before write, iclass 13, count 0 2006.257.09:08:06.49#ibcon#enter sib2, iclass 13, count 0 2006.257.09:08:06.49#ibcon#flushed, iclass 13, count 0 2006.257.09:08:06.49#ibcon#about to write, iclass 13, count 0 2006.257.09:08:06.49#ibcon#wrote, iclass 13, count 0 2006.257.09:08:06.49#ibcon#about to read 3, iclass 13, count 0 2006.257.09:08:06.52#ibcon#read 3, iclass 13, count 0 2006.257.09:08:06.52#ibcon#about to read 4, iclass 13, count 0 2006.257.09:08:06.52#ibcon#read 4, iclass 13, count 0 2006.257.09:08:06.52#ibcon#about to read 5, iclass 13, count 0 2006.257.09:08:06.52#ibcon#read 5, iclass 13, count 0 2006.257.09:08:06.52#ibcon#about to read 6, iclass 13, count 0 2006.257.09:08:06.52#ibcon#read 6, iclass 13, count 0 2006.257.09:08:06.52#ibcon#end of sib2, iclass 13, count 0 2006.257.09:08:06.52#ibcon#*after write, iclass 13, count 0 2006.257.09:08:06.52#ibcon#*before return 0, iclass 13, count 0 2006.257.09:08:06.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:06.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:08:06.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:08:06.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:08:06.52$vck44/vblo=3,649.99 2006.257.09:08:06.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.09:08:06.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.09:08:06.52#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:06.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:06.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:06.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:06.52#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:08:06.52#ibcon#first serial, iclass 15, count 0 2006.257.09:08:06.52#ibcon#enter sib2, iclass 15, count 0 2006.257.09:08:06.52#ibcon#flushed, iclass 15, count 0 2006.257.09:08:06.52#ibcon#about to write, iclass 15, count 0 2006.257.09:08:06.52#ibcon#wrote, iclass 15, count 0 2006.257.09:08:06.52#ibcon#about to read 3, iclass 15, count 0 2006.257.09:08:06.54#ibcon#read 3, iclass 15, count 0 2006.257.09:08:06.54#ibcon#about to read 4, iclass 15, count 0 2006.257.09:08:06.54#ibcon#read 4, iclass 15, count 0 2006.257.09:08:06.54#ibcon#about to read 5, iclass 15, count 0 2006.257.09:08:06.54#ibcon#read 5, iclass 15, count 0 2006.257.09:08:06.54#ibcon#about to read 6, iclass 15, count 0 2006.257.09:08:06.54#ibcon#read 6, iclass 15, count 0 2006.257.09:08:06.54#ibcon#end of sib2, iclass 15, count 0 2006.257.09:08:06.54#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:08:06.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:08:06.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:08:06.54#ibcon#*before write, iclass 15, count 0 2006.257.09:08:06.54#ibcon#enter sib2, iclass 15, count 0 2006.257.09:08:06.54#ibcon#flushed, iclass 15, count 0 2006.257.09:08:06.54#ibcon#about to write, iclass 15, count 0 2006.257.09:08:06.54#ibcon#wrote, iclass 15, count 0 2006.257.09:08:06.54#ibcon#about to read 3, iclass 15, count 0 2006.257.09:08:06.58#ibcon#read 3, iclass 15, count 0 2006.257.09:08:06.58#ibcon#about to read 4, iclass 15, count 0 2006.257.09:08:06.58#ibcon#read 4, iclass 15, count 0 2006.257.09:08:06.58#ibcon#about to read 5, iclass 15, count 0 2006.257.09:08:06.58#ibcon#read 5, iclass 15, count 0 2006.257.09:08:06.58#ibcon#about to read 6, iclass 15, count 0 2006.257.09:08:06.58#ibcon#read 6, iclass 15, count 0 2006.257.09:08:06.58#ibcon#end of sib2, iclass 15, count 0 2006.257.09:08:06.58#ibcon#*after write, iclass 15, count 0 2006.257.09:08:06.58#ibcon#*before return 0, iclass 15, count 0 2006.257.09:08:06.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:06.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:08:06.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:08:06.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:08:06.58$vck44/vb=3,4 2006.257.09:08:06.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.09:08:06.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.09:08:06.58#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:06.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:06.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:06.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:06.64#ibcon#enter wrdev, iclass 17, count 2 2006.257.09:08:06.64#ibcon#first serial, iclass 17, count 2 2006.257.09:08:06.64#ibcon#enter sib2, iclass 17, count 2 2006.257.09:08:06.64#ibcon#flushed, iclass 17, count 2 2006.257.09:08:06.64#ibcon#about to write, iclass 17, count 2 2006.257.09:08:06.64#ibcon#wrote, iclass 17, count 2 2006.257.09:08:06.64#ibcon#about to read 3, iclass 17, count 2 2006.257.09:08:06.66#ibcon#read 3, iclass 17, count 2 2006.257.09:08:06.66#ibcon#about to read 4, iclass 17, count 2 2006.257.09:08:06.66#ibcon#read 4, iclass 17, count 2 2006.257.09:08:06.66#ibcon#about to read 5, iclass 17, count 2 2006.257.09:08:06.66#ibcon#read 5, iclass 17, count 2 2006.257.09:08:06.66#ibcon#about to read 6, iclass 17, count 2 2006.257.09:08:06.66#ibcon#read 6, iclass 17, count 2 2006.257.09:08:06.66#ibcon#end of sib2, iclass 17, count 2 2006.257.09:08:06.66#ibcon#*mode == 0, iclass 17, count 2 2006.257.09:08:06.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.09:08:06.66#ibcon#[27=AT03-04\r\n] 2006.257.09:08:06.66#ibcon#*before write, iclass 17, count 2 2006.257.09:08:06.66#ibcon#enter sib2, iclass 17, count 2 2006.257.09:08:06.66#ibcon#flushed, iclass 17, count 2 2006.257.09:08:06.66#ibcon#about to write, iclass 17, count 2 2006.257.09:08:06.66#ibcon#wrote, iclass 17, count 2 2006.257.09:08:06.66#ibcon#about to read 3, iclass 17, count 2 2006.257.09:08:06.69#ibcon#read 3, iclass 17, count 2 2006.257.09:08:06.69#ibcon#about to read 4, iclass 17, count 2 2006.257.09:08:06.69#ibcon#read 4, iclass 17, count 2 2006.257.09:08:06.69#ibcon#about to read 5, iclass 17, count 2 2006.257.09:08:06.69#ibcon#read 5, iclass 17, count 2 2006.257.09:08:06.69#ibcon#about to read 6, iclass 17, count 2 2006.257.09:08:06.69#ibcon#read 6, iclass 17, count 2 2006.257.09:08:06.69#ibcon#end of sib2, iclass 17, count 2 2006.257.09:08:06.69#ibcon#*after write, iclass 17, count 2 2006.257.09:08:06.69#ibcon#*before return 0, iclass 17, count 2 2006.257.09:08:06.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:06.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:08:06.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.09:08:06.69#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:06.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:06.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:06.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:06.81#ibcon#enter wrdev, iclass 17, count 0 2006.257.09:08:06.81#ibcon#first serial, iclass 17, count 0 2006.257.09:08:06.81#ibcon#enter sib2, iclass 17, count 0 2006.257.09:08:06.81#ibcon#flushed, iclass 17, count 0 2006.257.09:08:06.81#ibcon#about to write, iclass 17, count 0 2006.257.09:08:06.81#ibcon#wrote, iclass 17, count 0 2006.257.09:08:06.81#ibcon#about to read 3, iclass 17, count 0 2006.257.09:08:06.83#ibcon#read 3, iclass 17, count 0 2006.257.09:08:06.83#ibcon#about to read 4, iclass 17, count 0 2006.257.09:08:06.83#ibcon#read 4, iclass 17, count 0 2006.257.09:08:06.83#ibcon#about to read 5, iclass 17, count 0 2006.257.09:08:06.83#ibcon#read 5, iclass 17, count 0 2006.257.09:08:06.83#ibcon#about to read 6, iclass 17, count 0 2006.257.09:08:06.83#ibcon#read 6, iclass 17, count 0 2006.257.09:08:06.83#ibcon#end of sib2, iclass 17, count 0 2006.257.09:08:06.83#ibcon#*mode == 0, iclass 17, count 0 2006.257.09:08:06.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.09:08:06.83#ibcon#[27=USB\r\n] 2006.257.09:08:06.83#ibcon#*before write, iclass 17, count 0 2006.257.09:08:06.83#ibcon#enter sib2, iclass 17, count 0 2006.257.09:08:06.83#ibcon#flushed, iclass 17, count 0 2006.257.09:08:06.83#ibcon#about to write, iclass 17, count 0 2006.257.09:08:06.83#ibcon#wrote, iclass 17, count 0 2006.257.09:08:06.83#ibcon#about to read 3, iclass 17, count 0 2006.257.09:08:06.86#ibcon#read 3, iclass 17, count 0 2006.257.09:08:06.86#ibcon#about to read 4, iclass 17, count 0 2006.257.09:08:06.86#ibcon#read 4, iclass 17, count 0 2006.257.09:08:06.86#ibcon#about to read 5, iclass 17, count 0 2006.257.09:08:06.86#ibcon#read 5, iclass 17, count 0 2006.257.09:08:06.86#ibcon#about to read 6, iclass 17, count 0 2006.257.09:08:06.86#ibcon#read 6, iclass 17, count 0 2006.257.09:08:06.86#ibcon#end of sib2, iclass 17, count 0 2006.257.09:08:06.86#ibcon#*after write, iclass 17, count 0 2006.257.09:08:06.86#ibcon#*before return 0, iclass 17, count 0 2006.257.09:08:06.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:06.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:08:06.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.09:08:06.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.09:08:06.86$vck44/vblo=4,679.99 2006.257.09:08:06.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.09:08:06.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.09:08:06.86#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:06.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:06.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:06.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:06.86#ibcon#enter wrdev, iclass 19, count 0 2006.257.09:08:06.86#ibcon#first serial, iclass 19, count 0 2006.257.09:08:06.86#ibcon#enter sib2, iclass 19, count 0 2006.257.09:08:06.86#ibcon#flushed, iclass 19, count 0 2006.257.09:08:06.86#ibcon#about to write, iclass 19, count 0 2006.257.09:08:06.86#ibcon#wrote, iclass 19, count 0 2006.257.09:08:06.86#ibcon#about to read 3, iclass 19, count 0 2006.257.09:08:06.88#ibcon#read 3, iclass 19, count 0 2006.257.09:08:06.88#ibcon#about to read 4, iclass 19, count 0 2006.257.09:08:06.88#ibcon#read 4, iclass 19, count 0 2006.257.09:08:06.88#ibcon#about to read 5, iclass 19, count 0 2006.257.09:08:06.88#ibcon#read 5, iclass 19, count 0 2006.257.09:08:06.88#ibcon#about to read 6, iclass 19, count 0 2006.257.09:08:06.88#ibcon#read 6, iclass 19, count 0 2006.257.09:08:06.88#ibcon#end of sib2, iclass 19, count 0 2006.257.09:08:06.88#ibcon#*mode == 0, iclass 19, count 0 2006.257.09:08:06.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.09:08:06.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:08:06.88#ibcon#*before write, iclass 19, count 0 2006.257.09:08:06.88#ibcon#enter sib2, iclass 19, count 0 2006.257.09:08:06.88#ibcon#flushed, iclass 19, count 0 2006.257.09:08:06.88#ibcon#about to write, iclass 19, count 0 2006.257.09:08:06.88#ibcon#wrote, iclass 19, count 0 2006.257.09:08:06.88#ibcon#about to read 3, iclass 19, count 0 2006.257.09:08:06.92#ibcon#read 3, iclass 19, count 0 2006.257.09:08:06.92#ibcon#about to read 4, iclass 19, count 0 2006.257.09:08:06.92#ibcon#read 4, iclass 19, count 0 2006.257.09:08:06.92#ibcon#about to read 5, iclass 19, count 0 2006.257.09:08:06.92#ibcon#read 5, iclass 19, count 0 2006.257.09:08:06.92#ibcon#about to read 6, iclass 19, count 0 2006.257.09:08:06.92#ibcon#read 6, iclass 19, count 0 2006.257.09:08:06.92#ibcon#end of sib2, iclass 19, count 0 2006.257.09:08:06.92#ibcon#*after write, iclass 19, count 0 2006.257.09:08:06.92#ibcon#*before return 0, iclass 19, count 0 2006.257.09:08:06.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:06.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:08:06.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.09:08:06.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.09:08:06.92$vck44/vb=4,5 2006.257.09:08:06.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.09:08:06.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.09:08:06.92#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:06.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:06.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:06.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:06.98#ibcon#enter wrdev, iclass 21, count 2 2006.257.09:08:06.98#ibcon#first serial, iclass 21, count 2 2006.257.09:08:06.98#ibcon#enter sib2, iclass 21, count 2 2006.257.09:08:06.98#ibcon#flushed, iclass 21, count 2 2006.257.09:08:06.98#ibcon#about to write, iclass 21, count 2 2006.257.09:08:06.98#ibcon#wrote, iclass 21, count 2 2006.257.09:08:06.98#ibcon#about to read 3, iclass 21, count 2 2006.257.09:08:07.00#ibcon#read 3, iclass 21, count 2 2006.257.09:08:07.00#ibcon#about to read 4, iclass 21, count 2 2006.257.09:08:07.00#ibcon#read 4, iclass 21, count 2 2006.257.09:08:07.00#ibcon#about to read 5, iclass 21, count 2 2006.257.09:08:07.00#ibcon#read 5, iclass 21, count 2 2006.257.09:08:07.00#ibcon#about to read 6, iclass 21, count 2 2006.257.09:08:07.00#ibcon#read 6, iclass 21, count 2 2006.257.09:08:07.00#ibcon#end of sib2, iclass 21, count 2 2006.257.09:08:07.00#ibcon#*mode == 0, iclass 21, count 2 2006.257.09:08:07.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.09:08:07.00#ibcon#[27=AT04-05\r\n] 2006.257.09:08:07.00#ibcon#*before write, iclass 21, count 2 2006.257.09:08:07.00#ibcon#enter sib2, iclass 21, count 2 2006.257.09:08:07.00#ibcon#flushed, iclass 21, count 2 2006.257.09:08:07.00#ibcon#about to write, iclass 21, count 2 2006.257.09:08:07.00#ibcon#wrote, iclass 21, count 2 2006.257.09:08:07.00#ibcon#about to read 3, iclass 21, count 2 2006.257.09:08:07.03#ibcon#read 3, iclass 21, count 2 2006.257.09:08:07.03#ibcon#about to read 4, iclass 21, count 2 2006.257.09:08:07.03#ibcon#read 4, iclass 21, count 2 2006.257.09:08:07.03#ibcon#about to read 5, iclass 21, count 2 2006.257.09:08:07.03#ibcon#read 5, iclass 21, count 2 2006.257.09:08:07.03#ibcon#about to read 6, iclass 21, count 2 2006.257.09:08:07.03#ibcon#read 6, iclass 21, count 2 2006.257.09:08:07.03#ibcon#end of sib2, iclass 21, count 2 2006.257.09:08:07.03#ibcon#*after write, iclass 21, count 2 2006.257.09:08:07.03#ibcon#*before return 0, iclass 21, count 2 2006.257.09:08:07.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:07.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:08:07.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.09:08:07.03#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:07.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:07.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:07.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:07.15#ibcon#enter wrdev, iclass 21, count 0 2006.257.09:08:07.15#ibcon#first serial, iclass 21, count 0 2006.257.09:08:07.15#ibcon#enter sib2, iclass 21, count 0 2006.257.09:08:07.15#ibcon#flushed, iclass 21, count 0 2006.257.09:08:07.15#ibcon#about to write, iclass 21, count 0 2006.257.09:08:07.15#ibcon#wrote, iclass 21, count 0 2006.257.09:08:07.15#ibcon#about to read 3, iclass 21, count 0 2006.257.09:08:07.17#ibcon#read 3, iclass 21, count 0 2006.257.09:08:07.17#ibcon#about to read 4, iclass 21, count 0 2006.257.09:08:07.17#ibcon#read 4, iclass 21, count 0 2006.257.09:08:07.17#ibcon#about to read 5, iclass 21, count 0 2006.257.09:08:07.17#ibcon#read 5, iclass 21, count 0 2006.257.09:08:07.17#ibcon#about to read 6, iclass 21, count 0 2006.257.09:08:07.17#ibcon#read 6, iclass 21, count 0 2006.257.09:08:07.17#ibcon#end of sib2, iclass 21, count 0 2006.257.09:08:07.17#ibcon#*mode == 0, iclass 21, count 0 2006.257.09:08:07.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.09:08:07.17#ibcon#[27=USB\r\n] 2006.257.09:08:07.17#ibcon#*before write, iclass 21, count 0 2006.257.09:08:07.17#ibcon#enter sib2, iclass 21, count 0 2006.257.09:08:07.17#ibcon#flushed, iclass 21, count 0 2006.257.09:08:07.17#ibcon#about to write, iclass 21, count 0 2006.257.09:08:07.17#ibcon#wrote, iclass 21, count 0 2006.257.09:08:07.17#ibcon#about to read 3, iclass 21, count 0 2006.257.09:08:07.20#ibcon#read 3, iclass 21, count 0 2006.257.09:08:07.20#ibcon#about to read 4, iclass 21, count 0 2006.257.09:08:07.20#ibcon#read 4, iclass 21, count 0 2006.257.09:08:07.20#ibcon#about to read 5, iclass 21, count 0 2006.257.09:08:07.20#ibcon#read 5, iclass 21, count 0 2006.257.09:08:07.20#ibcon#about to read 6, iclass 21, count 0 2006.257.09:08:07.20#ibcon#read 6, iclass 21, count 0 2006.257.09:08:07.20#ibcon#end of sib2, iclass 21, count 0 2006.257.09:08:07.20#ibcon#*after write, iclass 21, count 0 2006.257.09:08:07.20#ibcon#*before return 0, iclass 21, count 0 2006.257.09:08:07.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:07.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:08:07.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.09:08:07.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.09:08:07.20$vck44/vblo=5,709.99 2006.257.09:08:07.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.09:08:07.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.09:08:07.20#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:07.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:07.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:07.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:07.20#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:08:07.20#ibcon#first serial, iclass 23, count 0 2006.257.09:08:07.20#ibcon#enter sib2, iclass 23, count 0 2006.257.09:08:07.20#ibcon#flushed, iclass 23, count 0 2006.257.09:08:07.20#ibcon#about to write, iclass 23, count 0 2006.257.09:08:07.20#ibcon#wrote, iclass 23, count 0 2006.257.09:08:07.20#ibcon#about to read 3, iclass 23, count 0 2006.257.09:08:07.22#ibcon#read 3, iclass 23, count 0 2006.257.09:08:07.22#ibcon#about to read 4, iclass 23, count 0 2006.257.09:08:07.22#ibcon#read 4, iclass 23, count 0 2006.257.09:08:07.22#ibcon#about to read 5, iclass 23, count 0 2006.257.09:08:07.22#ibcon#read 5, iclass 23, count 0 2006.257.09:08:07.22#ibcon#about to read 6, iclass 23, count 0 2006.257.09:08:07.22#ibcon#read 6, iclass 23, count 0 2006.257.09:08:07.22#ibcon#end of sib2, iclass 23, count 0 2006.257.09:08:07.22#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:08:07.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:08:07.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:08:07.22#ibcon#*before write, iclass 23, count 0 2006.257.09:08:07.22#ibcon#enter sib2, iclass 23, count 0 2006.257.09:08:07.22#ibcon#flushed, iclass 23, count 0 2006.257.09:08:07.22#ibcon#about to write, iclass 23, count 0 2006.257.09:08:07.22#ibcon#wrote, iclass 23, count 0 2006.257.09:08:07.22#ibcon#about to read 3, iclass 23, count 0 2006.257.09:08:07.26#ibcon#read 3, iclass 23, count 0 2006.257.09:08:07.26#ibcon#about to read 4, iclass 23, count 0 2006.257.09:08:07.26#ibcon#read 4, iclass 23, count 0 2006.257.09:08:07.26#ibcon#about to read 5, iclass 23, count 0 2006.257.09:08:07.26#ibcon#read 5, iclass 23, count 0 2006.257.09:08:07.26#ibcon#about to read 6, iclass 23, count 0 2006.257.09:08:07.26#ibcon#read 6, iclass 23, count 0 2006.257.09:08:07.26#ibcon#end of sib2, iclass 23, count 0 2006.257.09:08:07.26#ibcon#*after write, iclass 23, count 0 2006.257.09:08:07.26#ibcon#*before return 0, iclass 23, count 0 2006.257.09:08:07.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:07.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:08:07.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:08:07.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:08:07.26$vck44/vb=5,4 2006.257.09:08:07.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.09:08:07.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.09:08:07.26#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:07.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:07.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:07.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:07.32#ibcon#enter wrdev, iclass 25, count 2 2006.257.09:08:07.32#ibcon#first serial, iclass 25, count 2 2006.257.09:08:07.32#ibcon#enter sib2, iclass 25, count 2 2006.257.09:08:07.32#ibcon#flushed, iclass 25, count 2 2006.257.09:08:07.32#ibcon#about to write, iclass 25, count 2 2006.257.09:08:07.32#ibcon#wrote, iclass 25, count 2 2006.257.09:08:07.32#ibcon#about to read 3, iclass 25, count 2 2006.257.09:08:07.34#ibcon#read 3, iclass 25, count 2 2006.257.09:08:07.34#ibcon#about to read 4, iclass 25, count 2 2006.257.09:08:07.34#ibcon#read 4, iclass 25, count 2 2006.257.09:08:07.34#ibcon#about to read 5, iclass 25, count 2 2006.257.09:08:07.34#ibcon#read 5, iclass 25, count 2 2006.257.09:08:07.34#ibcon#about to read 6, iclass 25, count 2 2006.257.09:08:07.34#ibcon#read 6, iclass 25, count 2 2006.257.09:08:07.34#ibcon#end of sib2, iclass 25, count 2 2006.257.09:08:07.34#ibcon#*mode == 0, iclass 25, count 2 2006.257.09:08:07.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.09:08:07.34#ibcon#[27=AT05-04\r\n] 2006.257.09:08:07.34#ibcon#*before write, iclass 25, count 2 2006.257.09:08:07.34#ibcon#enter sib2, iclass 25, count 2 2006.257.09:08:07.34#ibcon#flushed, iclass 25, count 2 2006.257.09:08:07.34#ibcon#about to write, iclass 25, count 2 2006.257.09:08:07.34#ibcon#wrote, iclass 25, count 2 2006.257.09:08:07.34#ibcon#about to read 3, iclass 25, count 2 2006.257.09:08:07.37#ibcon#read 3, iclass 25, count 2 2006.257.09:08:07.37#ibcon#about to read 4, iclass 25, count 2 2006.257.09:08:07.37#ibcon#read 4, iclass 25, count 2 2006.257.09:08:07.37#ibcon#about to read 5, iclass 25, count 2 2006.257.09:08:07.37#ibcon#read 5, iclass 25, count 2 2006.257.09:08:07.37#ibcon#about to read 6, iclass 25, count 2 2006.257.09:08:07.37#ibcon#read 6, iclass 25, count 2 2006.257.09:08:07.37#ibcon#end of sib2, iclass 25, count 2 2006.257.09:08:07.37#ibcon#*after write, iclass 25, count 2 2006.257.09:08:07.37#ibcon#*before return 0, iclass 25, count 2 2006.257.09:08:07.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:07.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:08:07.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.09:08:07.37#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:07.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:07.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:07.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:07.49#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:08:07.49#ibcon#first serial, iclass 25, count 0 2006.257.09:08:07.49#ibcon#enter sib2, iclass 25, count 0 2006.257.09:08:07.49#ibcon#flushed, iclass 25, count 0 2006.257.09:08:07.49#ibcon#about to write, iclass 25, count 0 2006.257.09:08:07.49#ibcon#wrote, iclass 25, count 0 2006.257.09:08:07.49#ibcon#about to read 3, iclass 25, count 0 2006.257.09:08:07.51#ibcon#read 3, iclass 25, count 0 2006.257.09:08:07.51#ibcon#about to read 4, iclass 25, count 0 2006.257.09:08:07.51#ibcon#read 4, iclass 25, count 0 2006.257.09:08:07.51#ibcon#about to read 5, iclass 25, count 0 2006.257.09:08:07.51#ibcon#read 5, iclass 25, count 0 2006.257.09:08:07.51#ibcon#about to read 6, iclass 25, count 0 2006.257.09:08:07.51#ibcon#read 6, iclass 25, count 0 2006.257.09:08:07.51#ibcon#end of sib2, iclass 25, count 0 2006.257.09:08:07.51#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:08:07.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:08:07.51#ibcon#[27=USB\r\n] 2006.257.09:08:07.51#ibcon#*before write, iclass 25, count 0 2006.257.09:08:07.51#ibcon#enter sib2, iclass 25, count 0 2006.257.09:08:07.51#ibcon#flushed, iclass 25, count 0 2006.257.09:08:07.51#ibcon#about to write, iclass 25, count 0 2006.257.09:08:07.51#ibcon#wrote, iclass 25, count 0 2006.257.09:08:07.51#ibcon#about to read 3, iclass 25, count 0 2006.257.09:08:07.54#abcon#<5=/14 1.1 2.3 20.00 951013.2\r\n> 2006.257.09:08:07.54#ibcon#read 3, iclass 25, count 0 2006.257.09:08:07.54#ibcon#about to read 4, iclass 25, count 0 2006.257.09:08:07.54#ibcon#read 4, iclass 25, count 0 2006.257.09:08:07.54#ibcon#about to read 5, iclass 25, count 0 2006.257.09:08:07.54#ibcon#read 5, iclass 25, count 0 2006.257.09:08:07.54#ibcon#about to read 6, iclass 25, count 0 2006.257.09:08:07.54#ibcon#read 6, iclass 25, count 0 2006.257.09:08:07.54#ibcon#end of sib2, iclass 25, count 0 2006.257.09:08:07.54#ibcon#*after write, iclass 25, count 0 2006.257.09:08:07.54#ibcon#*before return 0, iclass 25, count 0 2006.257.09:08:07.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:07.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:08:07.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:08:07.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:08:07.54$vck44/vblo=6,719.99 2006.257.09:08:07.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.09:08:07.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.09:08:07.54#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:07.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:08:07.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:08:07.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:08:07.54#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:08:07.54#ibcon#first serial, iclass 30, count 0 2006.257.09:08:07.54#ibcon#enter sib2, iclass 30, count 0 2006.257.09:08:07.54#ibcon#flushed, iclass 30, count 0 2006.257.09:08:07.54#ibcon#about to write, iclass 30, count 0 2006.257.09:08:07.54#ibcon#wrote, iclass 30, count 0 2006.257.09:08:07.54#ibcon#about to read 3, iclass 30, count 0 2006.257.09:08:07.56#abcon#{5=INTERFACE CLEAR} 2006.257.09:08:07.56#ibcon#read 3, iclass 30, count 0 2006.257.09:08:07.56#ibcon#about to read 4, iclass 30, count 0 2006.257.09:08:07.56#ibcon#read 4, iclass 30, count 0 2006.257.09:08:07.56#ibcon#about to read 5, iclass 30, count 0 2006.257.09:08:07.56#ibcon#read 5, iclass 30, count 0 2006.257.09:08:07.56#ibcon#about to read 6, iclass 30, count 0 2006.257.09:08:07.56#ibcon#read 6, iclass 30, count 0 2006.257.09:08:07.56#ibcon#end of sib2, iclass 30, count 0 2006.257.09:08:07.56#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:08:07.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:08:07.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:08:07.56#ibcon#*before write, iclass 30, count 0 2006.257.09:08:07.56#ibcon#enter sib2, iclass 30, count 0 2006.257.09:08:07.56#ibcon#flushed, iclass 30, count 0 2006.257.09:08:07.56#ibcon#about to write, iclass 30, count 0 2006.257.09:08:07.56#ibcon#wrote, iclass 30, count 0 2006.257.09:08:07.56#ibcon#about to read 3, iclass 30, count 0 2006.257.09:08:07.60#ibcon#read 3, iclass 30, count 0 2006.257.09:08:07.60#ibcon#about to read 4, iclass 30, count 0 2006.257.09:08:07.60#ibcon#read 4, iclass 30, count 0 2006.257.09:08:07.60#ibcon#about to read 5, iclass 30, count 0 2006.257.09:08:07.60#ibcon#read 5, iclass 30, count 0 2006.257.09:08:07.60#ibcon#about to read 6, iclass 30, count 0 2006.257.09:08:07.60#ibcon#read 6, iclass 30, count 0 2006.257.09:08:07.60#ibcon#end of sib2, iclass 30, count 0 2006.257.09:08:07.60#ibcon#*after write, iclass 30, count 0 2006.257.09:08:07.60#ibcon#*before return 0, iclass 30, count 0 2006.257.09:08:07.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:08:07.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:08:07.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:08:07.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:08:07.60$vck44/vb=6,4 2006.257.09:08:07.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.09:08:07.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.09:08:07.60#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:07.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:07.62#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:08:07.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:07.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:07.66#ibcon#enter wrdev, iclass 33, count 2 2006.257.09:08:07.66#ibcon#first serial, iclass 33, count 2 2006.257.09:08:07.66#ibcon#enter sib2, iclass 33, count 2 2006.257.09:08:07.66#ibcon#flushed, iclass 33, count 2 2006.257.09:08:07.66#ibcon#about to write, iclass 33, count 2 2006.257.09:08:07.66#ibcon#wrote, iclass 33, count 2 2006.257.09:08:07.66#ibcon#about to read 3, iclass 33, count 2 2006.257.09:08:07.68#ibcon#read 3, iclass 33, count 2 2006.257.09:08:07.68#ibcon#about to read 4, iclass 33, count 2 2006.257.09:08:07.68#ibcon#read 4, iclass 33, count 2 2006.257.09:08:07.68#ibcon#about to read 5, iclass 33, count 2 2006.257.09:08:07.68#ibcon#read 5, iclass 33, count 2 2006.257.09:08:07.68#ibcon#about to read 6, iclass 33, count 2 2006.257.09:08:07.68#ibcon#read 6, iclass 33, count 2 2006.257.09:08:07.68#ibcon#end of sib2, iclass 33, count 2 2006.257.09:08:07.68#ibcon#*mode == 0, iclass 33, count 2 2006.257.09:08:07.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.09:08:07.68#ibcon#[27=AT06-04\r\n] 2006.257.09:08:07.68#ibcon#*before write, iclass 33, count 2 2006.257.09:08:07.68#ibcon#enter sib2, iclass 33, count 2 2006.257.09:08:07.68#ibcon#flushed, iclass 33, count 2 2006.257.09:08:07.68#ibcon#about to write, iclass 33, count 2 2006.257.09:08:07.68#ibcon#wrote, iclass 33, count 2 2006.257.09:08:07.68#ibcon#about to read 3, iclass 33, count 2 2006.257.09:08:07.71#ibcon#read 3, iclass 33, count 2 2006.257.09:08:07.71#ibcon#about to read 4, iclass 33, count 2 2006.257.09:08:07.71#ibcon#read 4, iclass 33, count 2 2006.257.09:08:07.71#ibcon#about to read 5, iclass 33, count 2 2006.257.09:08:07.71#ibcon#read 5, iclass 33, count 2 2006.257.09:08:07.71#ibcon#about to read 6, iclass 33, count 2 2006.257.09:08:07.71#ibcon#read 6, iclass 33, count 2 2006.257.09:08:07.71#ibcon#end of sib2, iclass 33, count 2 2006.257.09:08:07.71#ibcon#*after write, iclass 33, count 2 2006.257.09:08:07.71#ibcon#*before return 0, iclass 33, count 2 2006.257.09:08:07.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:07.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:08:07.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.09:08:07.71#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:07.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:07.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:07.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:07.83#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:08:07.83#ibcon#first serial, iclass 33, count 0 2006.257.09:08:07.83#ibcon#enter sib2, iclass 33, count 0 2006.257.09:08:07.83#ibcon#flushed, iclass 33, count 0 2006.257.09:08:07.83#ibcon#about to write, iclass 33, count 0 2006.257.09:08:07.83#ibcon#wrote, iclass 33, count 0 2006.257.09:08:07.83#ibcon#about to read 3, iclass 33, count 0 2006.257.09:08:07.85#ibcon#read 3, iclass 33, count 0 2006.257.09:08:07.85#ibcon#about to read 4, iclass 33, count 0 2006.257.09:08:07.85#ibcon#read 4, iclass 33, count 0 2006.257.09:08:07.85#ibcon#about to read 5, iclass 33, count 0 2006.257.09:08:07.85#ibcon#read 5, iclass 33, count 0 2006.257.09:08:07.85#ibcon#about to read 6, iclass 33, count 0 2006.257.09:08:07.85#ibcon#read 6, iclass 33, count 0 2006.257.09:08:07.85#ibcon#end of sib2, iclass 33, count 0 2006.257.09:08:07.85#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:08:07.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:08:07.85#ibcon#[27=USB\r\n] 2006.257.09:08:07.85#ibcon#*before write, iclass 33, count 0 2006.257.09:08:07.85#ibcon#enter sib2, iclass 33, count 0 2006.257.09:08:07.85#ibcon#flushed, iclass 33, count 0 2006.257.09:08:07.85#ibcon#about to write, iclass 33, count 0 2006.257.09:08:07.85#ibcon#wrote, iclass 33, count 0 2006.257.09:08:07.85#ibcon#about to read 3, iclass 33, count 0 2006.257.09:08:07.88#ibcon#read 3, iclass 33, count 0 2006.257.09:08:07.88#ibcon#about to read 4, iclass 33, count 0 2006.257.09:08:07.88#ibcon#read 4, iclass 33, count 0 2006.257.09:08:07.88#ibcon#about to read 5, iclass 33, count 0 2006.257.09:08:07.88#ibcon#read 5, iclass 33, count 0 2006.257.09:08:07.88#ibcon#about to read 6, iclass 33, count 0 2006.257.09:08:07.88#ibcon#read 6, iclass 33, count 0 2006.257.09:08:07.88#ibcon#end of sib2, iclass 33, count 0 2006.257.09:08:07.88#ibcon#*after write, iclass 33, count 0 2006.257.09:08:07.88#ibcon#*before return 0, iclass 33, count 0 2006.257.09:08:07.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:07.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:08:07.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:08:07.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:08:07.88$vck44/vblo=7,734.99 2006.257.09:08:07.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.09:08:07.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.09:08:07.88#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:07.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:07.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:07.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:07.88#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:08:07.88#ibcon#first serial, iclass 35, count 0 2006.257.09:08:07.88#ibcon#enter sib2, iclass 35, count 0 2006.257.09:08:07.88#ibcon#flushed, iclass 35, count 0 2006.257.09:08:07.88#ibcon#about to write, iclass 35, count 0 2006.257.09:08:07.88#ibcon#wrote, iclass 35, count 0 2006.257.09:08:07.88#ibcon#about to read 3, iclass 35, count 0 2006.257.09:08:07.90#ibcon#read 3, iclass 35, count 0 2006.257.09:08:07.90#ibcon#about to read 4, iclass 35, count 0 2006.257.09:08:07.90#ibcon#read 4, iclass 35, count 0 2006.257.09:08:07.90#ibcon#about to read 5, iclass 35, count 0 2006.257.09:08:07.90#ibcon#read 5, iclass 35, count 0 2006.257.09:08:07.90#ibcon#about to read 6, iclass 35, count 0 2006.257.09:08:07.90#ibcon#read 6, iclass 35, count 0 2006.257.09:08:07.90#ibcon#end of sib2, iclass 35, count 0 2006.257.09:08:07.90#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:08:07.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:08:07.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:08:07.90#ibcon#*before write, iclass 35, count 0 2006.257.09:08:07.90#ibcon#enter sib2, iclass 35, count 0 2006.257.09:08:07.90#ibcon#flushed, iclass 35, count 0 2006.257.09:08:07.90#ibcon#about to write, iclass 35, count 0 2006.257.09:08:07.90#ibcon#wrote, iclass 35, count 0 2006.257.09:08:07.90#ibcon#about to read 3, iclass 35, count 0 2006.257.09:08:07.94#ibcon#read 3, iclass 35, count 0 2006.257.09:08:07.94#ibcon#about to read 4, iclass 35, count 0 2006.257.09:08:07.94#ibcon#read 4, iclass 35, count 0 2006.257.09:08:07.94#ibcon#about to read 5, iclass 35, count 0 2006.257.09:08:07.94#ibcon#read 5, iclass 35, count 0 2006.257.09:08:07.94#ibcon#about to read 6, iclass 35, count 0 2006.257.09:08:07.94#ibcon#read 6, iclass 35, count 0 2006.257.09:08:07.94#ibcon#end of sib2, iclass 35, count 0 2006.257.09:08:07.94#ibcon#*after write, iclass 35, count 0 2006.257.09:08:07.94#ibcon#*before return 0, iclass 35, count 0 2006.257.09:08:07.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:07.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:08:07.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:08:07.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:08:07.94$vck44/vb=7,4 2006.257.09:08:07.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.09:08:07.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.09:08:07.94#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:07.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:08.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:08.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:08.00#ibcon#enter wrdev, iclass 37, count 2 2006.257.09:08:08.00#ibcon#first serial, iclass 37, count 2 2006.257.09:08:08.00#ibcon#enter sib2, iclass 37, count 2 2006.257.09:08:08.00#ibcon#flushed, iclass 37, count 2 2006.257.09:08:08.00#ibcon#about to write, iclass 37, count 2 2006.257.09:08:08.00#ibcon#wrote, iclass 37, count 2 2006.257.09:08:08.00#ibcon#about to read 3, iclass 37, count 2 2006.257.09:08:08.02#ibcon#read 3, iclass 37, count 2 2006.257.09:08:08.02#ibcon#about to read 4, iclass 37, count 2 2006.257.09:08:08.02#ibcon#read 4, iclass 37, count 2 2006.257.09:08:08.02#ibcon#about to read 5, iclass 37, count 2 2006.257.09:08:08.02#ibcon#read 5, iclass 37, count 2 2006.257.09:08:08.02#ibcon#about to read 6, iclass 37, count 2 2006.257.09:08:08.02#ibcon#read 6, iclass 37, count 2 2006.257.09:08:08.02#ibcon#end of sib2, iclass 37, count 2 2006.257.09:08:08.02#ibcon#*mode == 0, iclass 37, count 2 2006.257.09:08:08.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.09:08:08.02#ibcon#[27=AT07-04\r\n] 2006.257.09:08:08.02#ibcon#*before write, iclass 37, count 2 2006.257.09:08:08.02#ibcon#enter sib2, iclass 37, count 2 2006.257.09:08:08.02#ibcon#flushed, iclass 37, count 2 2006.257.09:08:08.02#ibcon#about to write, iclass 37, count 2 2006.257.09:08:08.02#ibcon#wrote, iclass 37, count 2 2006.257.09:08:08.02#ibcon#about to read 3, iclass 37, count 2 2006.257.09:08:08.05#ibcon#read 3, iclass 37, count 2 2006.257.09:08:08.05#ibcon#about to read 4, iclass 37, count 2 2006.257.09:08:08.05#ibcon#read 4, iclass 37, count 2 2006.257.09:08:08.05#ibcon#about to read 5, iclass 37, count 2 2006.257.09:08:08.05#ibcon#read 5, iclass 37, count 2 2006.257.09:08:08.05#ibcon#about to read 6, iclass 37, count 2 2006.257.09:08:08.05#ibcon#read 6, iclass 37, count 2 2006.257.09:08:08.05#ibcon#end of sib2, iclass 37, count 2 2006.257.09:08:08.05#ibcon#*after write, iclass 37, count 2 2006.257.09:08:08.05#ibcon#*before return 0, iclass 37, count 2 2006.257.09:08:08.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:08.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:08:08.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.09:08:08.05#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:08.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:08.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:08.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:08.17#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:08:08.17#ibcon#first serial, iclass 37, count 0 2006.257.09:08:08.17#ibcon#enter sib2, iclass 37, count 0 2006.257.09:08:08.17#ibcon#flushed, iclass 37, count 0 2006.257.09:08:08.17#ibcon#about to write, iclass 37, count 0 2006.257.09:08:08.17#ibcon#wrote, iclass 37, count 0 2006.257.09:08:08.17#ibcon#about to read 3, iclass 37, count 0 2006.257.09:08:08.19#ibcon#read 3, iclass 37, count 0 2006.257.09:08:08.19#ibcon#about to read 4, iclass 37, count 0 2006.257.09:08:08.19#ibcon#read 4, iclass 37, count 0 2006.257.09:08:08.19#ibcon#about to read 5, iclass 37, count 0 2006.257.09:08:08.19#ibcon#read 5, iclass 37, count 0 2006.257.09:08:08.19#ibcon#about to read 6, iclass 37, count 0 2006.257.09:08:08.19#ibcon#read 6, iclass 37, count 0 2006.257.09:08:08.19#ibcon#end of sib2, iclass 37, count 0 2006.257.09:08:08.19#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:08:08.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:08:08.19#ibcon#[27=USB\r\n] 2006.257.09:08:08.19#ibcon#*before write, iclass 37, count 0 2006.257.09:08:08.19#ibcon#enter sib2, iclass 37, count 0 2006.257.09:08:08.19#ibcon#flushed, iclass 37, count 0 2006.257.09:08:08.19#ibcon#about to write, iclass 37, count 0 2006.257.09:08:08.19#ibcon#wrote, iclass 37, count 0 2006.257.09:08:08.19#ibcon#about to read 3, iclass 37, count 0 2006.257.09:08:08.22#ibcon#read 3, iclass 37, count 0 2006.257.09:08:08.22#ibcon#about to read 4, iclass 37, count 0 2006.257.09:08:08.22#ibcon#read 4, iclass 37, count 0 2006.257.09:08:08.22#ibcon#about to read 5, iclass 37, count 0 2006.257.09:08:08.22#ibcon#read 5, iclass 37, count 0 2006.257.09:08:08.22#ibcon#about to read 6, iclass 37, count 0 2006.257.09:08:08.22#ibcon#read 6, iclass 37, count 0 2006.257.09:08:08.22#ibcon#end of sib2, iclass 37, count 0 2006.257.09:08:08.22#ibcon#*after write, iclass 37, count 0 2006.257.09:08:08.22#ibcon#*before return 0, iclass 37, count 0 2006.257.09:08:08.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:08.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:08:08.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:08:08.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:08:08.22$vck44/vblo=8,744.99 2006.257.09:08:08.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.09:08:08.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.09:08:08.22#ibcon#ireg 17 cls_cnt 0 2006.257.09:08:08.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:08.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:08.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:08.22#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:08:08.22#ibcon#first serial, iclass 39, count 0 2006.257.09:08:08.22#ibcon#enter sib2, iclass 39, count 0 2006.257.09:08:08.22#ibcon#flushed, iclass 39, count 0 2006.257.09:08:08.22#ibcon#about to write, iclass 39, count 0 2006.257.09:08:08.22#ibcon#wrote, iclass 39, count 0 2006.257.09:08:08.22#ibcon#about to read 3, iclass 39, count 0 2006.257.09:08:08.24#ibcon#read 3, iclass 39, count 0 2006.257.09:08:08.24#ibcon#about to read 4, iclass 39, count 0 2006.257.09:08:08.24#ibcon#read 4, iclass 39, count 0 2006.257.09:08:08.24#ibcon#about to read 5, iclass 39, count 0 2006.257.09:08:08.24#ibcon#read 5, iclass 39, count 0 2006.257.09:08:08.24#ibcon#about to read 6, iclass 39, count 0 2006.257.09:08:08.24#ibcon#read 6, iclass 39, count 0 2006.257.09:08:08.24#ibcon#end of sib2, iclass 39, count 0 2006.257.09:08:08.24#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:08:08.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:08:08.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:08:08.24#ibcon#*before write, iclass 39, count 0 2006.257.09:08:08.24#ibcon#enter sib2, iclass 39, count 0 2006.257.09:08:08.24#ibcon#flushed, iclass 39, count 0 2006.257.09:08:08.24#ibcon#about to write, iclass 39, count 0 2006.257.09:08:08.24#ibcon#wrote, iclass 39, count 0 2006.257.09:08:08.24#ibcon#about to read 3, iclass 39, count 0 2006.257.09:08:08.28#ibcon#read 3, iclass 39, count 0 2006.257.09:08:08.28#ibcon#about to read 4, iclass 39, count 0 2006.257.09:08:08.28#ibcon#read 4, iclass 39, count 0 2006.257.09:08:08.28#ibcon#about to read 5, iclass 39, count 0 2006.257.09:08:08.28#ibcon#read 5, iclass 39, count 0 2006.257.09:08:08.28#ibcon#about to read 6, iclass 39, count 0 2006.257.09:08:08.28#ibcon#read 6, iclass 39, count 0 2006.257.09:08:08.28#ibcon#end of sib2, iclass 39, count 0 2006.257.09:08:08.28#ibcon#*after write, iclass 39, count 0 2006.257.09:08:08.28#ibcon#*before return 0, iclass 39, count 0 2006.257.09:08:08.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:08.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:08:08.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:08:08.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:08:08.28$vck44/vb=8,4 2006.257.09:08:08.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.09:08:08.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.09:08:08.28#ibcon#ireg 11 cls_cnt 2 2006.257.09:08:08.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:08.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:08.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:08.34#ibcon#enter wrdev, iclass 3, count 2 2006.257.09:08:08.34#ibcon#first serial, iclass 3, count 2 2006.257.09:08:08.34#ibcon#enter sib2, iclass 3, count 2 2006.257.09:08:08.34#ibcon#flushed, iclass 3, count 2 2006.257.09:08:08.34#ibcon#about to write, iclass 3, count 2 2006.257.09:08:08.34#ibcon#wrote, iclass 3, count 2 2006.257.09:08:08.34#ibcon#about to read 3, iclass 3, count 2 2006.257.09:08:08.36#ibcon#read 3, iclass 3, count 2 2006.257.09:08:08.36#ibcon#about to read 4, iclass 3, count 2 2006.257.09:08:08.36#ibcon#read 4, iclass 3, count 2 2006.257.09:08:08.36#ibcon#about to read 5, iclass 3, count 2 2006.257.09:08:08.36#ibcon#read 5, iclass 3, count 2 2006.257.09:08:08.36#ibcon#about to read 6, iclass 3, count 2 2006.257.09:08:08.36#ibcon#read 6, iclass 3, count 2 2006.257.09:08:08.36#ibcon#end of sib2, iclass 3, count 2 2006.257.09:08:08.36#ibcon#*mode == 0, iclass 3, count 2 2006.257.09:08:08.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.09:08:08.36#ibcon#[27=AT08-04\r\n] 2006.257.09:08:08.36#ibcon#*before write, iclass 3, count 2 2006.257.09:08:08.36#ibcon#enter sib2, iclass 3, count 2 2006.257.09:08:08.36#ibcon#flushed, iclass 3, count 2 2006.257.09:08:08.36#ibcon#about to write, iclass 3, count 2 2006.257.09:08:08.36#ibcon#wrote, iclass 3, count 2 2006.257.09:08:08.36#ibcon#about to read 3, iclass 3, count 2 2006.257.09:08:08.39#ibcon#read 3, iclass 3, count 2 2006.257.09:08:08.39#ibcon#about to read 4, iclass 3, count 2 2006.257.09:08:08.39#ibcon#read 4, iclass 3, count 2 2006.257.09:08:08.39#ibcon#about to read 5, iclass 3, count 2 2006.257.09:08:08.39#ibcon#read 5, iclass 3, count 2 2006.257.09:08:08.39#ibcon#about to read 6, iclass 3, count 2 2006.257.09:08:08.39#ibcon#read 6, iclass 3, count 2 2006.257.09:08:08.39#ibcon#end of sib2, iclass 3, count 2 2006.257.09:08:08.39#ibcon#*after write, iclass 3, count 2 2006.257.09:08:08.39#ibcon#*before return 0, iclass 3, count 2 2006.257.09:08:08.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:08.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:08:08.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.09:08:08.39#ibcon#ireg 7 cls_cnt 0 2006.257.09:08:08.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:08.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:08.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:08.51#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:08:08.51#ibcon#first serial, iclass 3, count 0 2006.257.09:08:08.51#ibcon#enter sib2, iclass 3, count 0 2006.257.09:08:08.51#ibcon#flushed, iclass 3, count 0 2006.257.09:08:08.51#ibcon#about to write, iclass 3, count 0 2006.257.09:08:08.51#ibcon#wrote, iclass 3, count 0 2006.257.09:08:08.51#ibcon#about to read 3, iclass 3, count 0 2006.257.09:08:08.53#ibcon#read 3, iclass 3, count 0 2006.257.09:08:08.53#ibcon#about to read 4, iclass 3, count 0 2006.257.09:08:08.53#ibcon#read 4, iclass 3, count 0 2006.257.09:08:08.53#ibcon#about to read 5, iclass 3, count 0 2006.257.09:08:08.53#ibcon#read 5, iclass 3, count 0 2006.257.09:08:08.53#ibcon#about to read 6, iclass 3, count 0 2006.257.09:08:08.53#ibcon#read 6, iclass 3, count 0 2006.257.09:08:08.53#ibcon#end of sib2, iclass 3, count 0 2006.257.09:08:08.53#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:08:08.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:08:08.53#ibcon#[27=USB\r\n] 2006.257.09:08:08.53#ibcon#*before write, iclass 3, count 0 2006.257.09:08:08.53#ibcon#enter sib2, iclass 3, count 0 2006.257.09:08:08.53#ibcon#flushed, iclass 3, count 0 2006.257.09:08:08.53#ibcon#about to write, iclass 3, count 0 2006.257.09:08:08.53#ibcon#wrote, iclass 3, count 0 2006.257.09:08:08.53#ibcon#about to read 3, iclass 3, count 0 2006.257.09:08:08.56#ibcon#read 3, iclass 3, count 0 2006.257.09:08:08.56#ibcon#about to read 4, iclass 3, count 0 2006.257.09:08:08.56#ibcon#read 4, iclass 3, count 0 2006.257.09:08:08.56#ibcon#about to read 5, iclass 3, count 0 2006.257.09:08:08.56#ibcon#read 5, iclass 3, count 0 2006.257.09:08:08.56#ibcon#about to read 6, iclass 3, count 0 2006.257.09:08:08.56#ibcon#read 6, iclass 3, count 0 2006.257.09:08:08.56#ibcon#end of sib2, iclass 3, count 0 2006.257.09:08:08.56#ibcon#*after write, iclass 3, count 0 2006.257.09:08:08.56#ibcon#*before return 0, iclass 3, count 0 2006.257.09:08:08.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:08.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:08:08.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:08:08.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:08:08.56$vck44/vabw=wide 2006.257.09:08:08.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.09:08:08.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.09:08:08.56#ibcon#ireg 8 cls_cnt 0 2006.257.09:08:08.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:08.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:08.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:08.56#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:08:08.56#ibcon#first serial, iclass 5, count 0 2006.257.09:08:08.56#ibcon#enter sib2, iclass 5, count 0 2006.257.09:08:08.56#ibcon#flushed, iclass 5, count 0 2006.257.09:08:08.56#ibcon#about to write, iclass 5, count 0 2006.257.09:08:08.56#ibcon#wrote, iclass 5, count 0 2006.257.09:08:08.56#ibcon#about to read 3, iclass 5, count 0 2006.257.09:08:08.58#ibcon#read 3, iclass 5, count 0 2006.257.09:08:08.58#ibcon#about to read 4, iclass 5, count 0 2006.257.09:08:08.58#ibcon#read 4, iclass 5, count 0 2006.257.09:08:08.58#ibcon#about to read 5, iclass 5, count 0 2006.257.09:08:08.58#ibcon#read 5, iclass 5, count 0 2006.257.09:08:08.58#ibcon#about to read 6, iclass 5, count 0 2006.257.09:08:08.58#ibcon#read 6, iclass 5, count 0 2006.257.09:08:08.58#ibcon#end of sib2, iclass 5, count 0 2006.257.09:08:08.58#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:08:08.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:08:08.58#ibcon#[25=BW32\r\n] 2006.257.09:08:08.58#ibcon#*before write, iclass 5, count 0 2006.257.09:08:08.58#ibcon#enter sib2, iclass 5, count 0 2006.257.09:08:08.58#ibcon#flushed, iclass 5, count 0 2006.257.09:08:08.58#ibcon#about to write, iclass 5, count 0 2006.257.09:08:08.58#ibcon#wrote, iclass 5, count 0 2006.257.09:08:08.58#ibcon#about to read 3, iclass 5, count 0 2006.257.09:08:08.61#ibcon#read 3, iclass 5, count 0 2006.257.09:08:08.61#ibcon#about to read 4, iclass 5, count 0 2006.257.09:08:08.61#ibcon#read 4, iclass 5, count 0 2006.257.09:08:08.61#ibcon#about to read 5, iclass 5, count 0 2006.257.09:08:08.61#ibcon#read 5, iclass 5, count 0 2006.257.09:08:08.61#ibcon#about to read 6, iclass 5, count 0 2006.257.09:08:08.61#ibcon#read 6, iclass 5, count 0 2006.257.09:08:08.61#ibcon#end of sib2, iclass 5, count 0 2006.257.09:08:08.61#ibcon#*after write, iclass 5, count 0 2006.257.09:08:08.61#ibcon#*before return 0, iclass 5, count 0 2006.257.09:08:08.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:08.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:08:08.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:08:08.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:08:08.61$vck44/vbbw=wide 2006.257.09:08:08.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.09:08:08.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.09:08:08.61#ibcon#ireg 8 cls_cnt 0 2006.257.09:08:08.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:08:08.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:08:08.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:08:08.68#ibcon#enter wrdev, iclass 7, count 0 2006.257.09:08:08.68#ibcon#first serial, iclass 7, count 0 2006.257.09:08:08.68#ibcon#enter sib2, iclass 7, count 0 2006.257.09:08:08.68#ibcon#flushed, iclass 7, count 0 2006.257.09:08:08.68#ibcon#about to write, iclass 7, count 0 2006.257.09:08:08.68#ibcon#wrote, iclass 7, count 0 2006.257.09:08:08.68#ibcon#about to read 3, iclass 7, count 0 2006.257.09:08:08.70#ibcon#read 3, iclass 7, count 0 2006.257.09:08:08.70#ibcon#about to read 4, iclass 7, count 0 2006.257.09:08:08.70#ibcon#read 4, iclass 7, count 0 2006.257.09:08:08.70#ibcon#about to read 5, iclass 7, count 0 2006.257.09:08:08.70#ibcon#read 5, iclass 7, count 0 2006.257.09:08:08.70#ibcon#about to read 6, iclass 7, count 0 2006.257.09:08:08.70#ibcon#read 6, iclass 7, count 0 2006.257.09:08:08.70#ibcon#end of sib2, iclass 7, count 0 2006.257.09:08:08.70#ibcon#*mode == 0, iclass 7, count 0 2006.257.09:08:08.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.09:08:08.70#ibcon#[27=BW32\r\n] 2006.257.09:08:08.70#ibcon#*before write, iclass 7, count 0 2006.257.09:08:08.70#ibcon#enter sib2, iclass 7, count 0 2006.257.09:08:08.70#ibcon#flushed, iclass 7, count 0 2006.257.09:08:08.70#ibcon#about to write, iclass 7, count 0 2006.257.09:08:08.70#ibcon#wrote, iclass 7, count 0 2006.257.09:08:08.70#ibcon#about to read 3, iclass 7, count 0 2006.257.09:08:08.73#ibcon#read 3, iclass 7, count 0 2006.257.09:08:08.73#ibcon#about to read 4, iclass 7, count 0 2006.257.09:08:08.73#ibcon#read 4, iclass 7, count 0 2006.257.09:08:08.73#ibcon#about to read 5, iclass 7, count 0 2006.257.09:08:08.73#ibcon#read 5, iclass 7, count 0 2006.257.09:08:08.73#ibcon#about to read 6, iclass 7, count 0 2006.257.09:08:08.73#ibcon#read 6, iclass 7, count 0 2006.257.09:08:08.73#ibcon#end of sib2, iclass 7, count 0 2006.257.09:08:08.73#ibcon#*after write, iclass 7, count 0 2006.257.09:08:08.73#ibcon#*before return 0, iclass 7, count 0 2006.257.09:08:08.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:08:08.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:08:08.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.09:08:08.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.09:08:08.73$setupk4/ifdk4 2006.257.09:08:08.73$ifdk4/lo= 2006.257.09:08:08.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:08:08.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:08:08.73$ifdk4/patch= 2006.257.09:08:08.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:08:08.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:08:08.74$setupk4/!*+20s 2006.257.09:08:17.71#abcon#<5=/14 1.1 2.2 20.00 951013.1\r\n> 2006.257.09:08:17.73#abcon#{5=INTERFACE CLEAR} 2006.257.09:08:17.79#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:08:23.25$setupk4/"tpicd 2006.257.09:08:23.25$setupk4/echo=off 2006.257.09:08:23.25$setupk4/xlog=off 2006.257.09:08:23.25:!2006.257.09:09:20 2006.257.09:08:30.14#trakl#Source acquired 2006.257.09:08:31.14#flagr#flagr/antenna,acquired 2006.257.09:09:20.00:preob 2006.257.09:09:20.14/onsource/TRACKING 2006.257.09:09:20.14:!2006.257.09:09:30 2006.257.09:09:30.00:"tape 2006.257.09:09:30.00:"st=record 2006.257.09:09:30.00:data_valid=on 2006.257.09:09:30.00:midob 2006.257.09:09:31.14/onsource/TRACKING 2006.257.09:09:31.14/wx/19.98,1013.2,95 2006.257.09:09:31.23/cable/+6.4739E-03 2006.257.09:09:32.32/va/01,08,usb,yes,31,33 2006.257.09:09:32.32/va/02,07,usb,yes,34,34 2006.257.09:09:32.32/va/03,08,usb,yes,30,32 2006.257.09:09:32.32/va/04,07,usb,yes,34,36 2006.257.09:09:32.32/va/05,04,usb,yes,31,31 2006.257.09:09:32.32/va/06,04,usb,yes,34,34 2006.257.09:09:32.32/va/07,04,usb,yes,35,36 2006.257.09:09:32.32/va/08,04,usb,yes,29,36 2006.257.09:09:32.55/valo/01,524.99,yes,locked 2006.257.09:09:32.55/valo/02,534.99,yes,locked 2006.257.09:09:32.55/valo/03,564.99,yes,locked 2006.257.09:09:32.55/valo/04,624.99,yes,locked 2006.257.09:09:32.55/valo/05,734.99,yes,locked 2006.257.09:09:32.55/valo/06,814.99,yes,locked 2006.257.09:09:32.55/valo/07,864.99,yes,locked 2006.257.09:09:32.55/valo/08,884.99,yes,locked 2006.257.09:09:33.64/vb/01,04,usb,yes,30,29 2006.257.09:09:33.64/vb/02,05,usb,yes,28,29 2006.257.09:09:33.64/vb/03,04,usb,yes,29,32 2006.257.09:09:33.64/vb/04,05,usb,yes,30,29 2006.257.09:09:33.64/vb/05,04,usb,yes,26,29 2006.257.09:09:33.64/vb/06,04,usb,yes,31,27 2006.257.09:09:33.64/vb/07,04,usb,yes,31,30 2006.257.09:09:33.64/vb/08,04,usb,yes,28,31 2006.257.09:09:33.88/vblo/01,629.99,yes,locked 2006.257.09:09:33.88/vblo/02,634.99,yes,locked 2006.257.09:09:33.88/vblo/03,649.99,yes,locked 2006.257.09:09:33.88/vblo/04,679.99,yes,locked 2006.257.09:09:33.88/vblo/05,709.99,yes,locked 2006.257.09:09:33.88/vblo/06,719.99,yes,locked 2006.257.09:09:33.88/vblo/07,734.99,yes,locked 2006.257.09:09:33.88/vblo/08,744.99,yes,locked 2006.257.09:09:34.03/vabw/8 2006.257.09:09:34.18/vbbw/8 2006.257.09:09:34.27/xfe/off,on,14.5 2006.257.09:09:34.65/ifatt/23,28,28,28 2006.257.09:09:35.07/fmout-gps/S +4.63E-07 2006.257.09:09:35.11:!2006.257.09:10:50 2006.257.09:10:50.01:data_valid=off 2006.257.09:10:50.02:"et 2006.257.09:10:50.02:!+3s 2006.257.09:10:53.03:"tape 2006.257.09:10:53.04:postob 2006.257.09:10:53.24/cable/+6.4737E-03 2006.257.09:10:53.25/wx/19.96,1013.1,95 2006.257.09:10:53.30/fmout-gps/S +4.64E-07 2006.257.09:10:53.31:scan_name=257-0913,jd0609,50 2006.257.09:10:53.31:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.09:10:54.14#flagr#flagr/antenna,new-source 2006.257.09:10:54.15:checkk5 2006.257.09:10:54.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:10:54.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:10:55.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:10:55.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:10:56.15/chk_obsdata//k5ts1/T2570909??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.09:10:56.55/chk_obsdata//k5ts2/T2570909??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.09:10:56.97/chk_obsdata//k5ts3/T2570909??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.09:10:57.36/chk_obsdata//k5ts4/T2570909??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.09:10:58.08/k5log//k5ts1_log_newline 2006.257.09:10:58.79/k5log//k5ts2_log_newline 2006.257.09:10:59.50/k5log//k5ts3_log_newline 2006.257.09:11:00.22/k5log//k5ts4_log_newline 2006.257.09:11:00.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:11:00.24:setupk4=1 2006.257.09:11:00.24$setupk4/echo=on 2006.257.09:11:00.24$setupk4/pcalon 2006.257.09:11:00.24$pcalon/"no phase cal control is implemented here 2006.257.09:11:00.24$setupk4/"tpicd=stop 2006.257.09:11:00.24$setupk4/"rec=synch_on 2006.257.09:11:00.24$setupk4/"rec_mode=128 2006.257.09:11:00.24$setupk4/!* 2006.257.09:11:00.24$setupk4/recpk4 2006.257.09:11:00.24$recpk4/recpatch= 2006.257.09:11:00.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:11:00.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:11:00.25$setupk4/vck44 2006.257.09:11:00.25$vck44/valo=1,524.99 2006.257.09:11:00.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.09:11:00.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.09:11:00.25#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:00.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:00.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:00.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:00.25#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:11:00.25#ibcon#first serial, iclass 4, count 0 2006.257.09:11:00.25#ibcon#enter sib2, iclass 4, count 0 2006.257.09:11:00.25#ibcon#flushed, iclass 4, count 0 2006.257.09:11:00.25#ibcon#about to write, iclass 4, count 0 2006.257.09:11:00.25#ibcon#wrote, iclass 4, count 0 2006.257.09:11:00.25#ibcon#about to read 3, iclass 4, count 0 2006.257.09:11:00.26#ibcon#read 3, iclass 4, count 0 2006.257.09:11:00.26#ibcon#about to read 4, iclass 4, count 0 2006.257.09:11:00.26#ibcon#read 4, iclass 4, count 0 2006.257.09:11:00.26#ibcon#about to read 5, iclass 4, count 0 2006.257.09:11:00.26#ibcon#read 5, iclass 4, count 0 2006.257.09:11:00.26#ibcon#about to read 6, iclass 4, count 0 2006.257.09:11:00.26#ibcon#read 6, iclass 4, count 0 2006.257.09:11:00.26#ibcon#end of sib2, iclass 4, count 0 2006.257.09:11:00.26#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:11:00.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:11:00.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:11:00.26#ibcon#*before write, iclass 4, count 0 2006.257.09:11:00.26#ibcon#enter sib2, iclass 4, count 0 2006.257.09:11:00.26#ibcon#flushed, iclass 4, count 0 2006.257.09:11:00.26#ibcon#about to write, iclass 4, count 0 2006.257.09:11:00.26#ibcon#wrote, iclass 4, count 0 2006.257.09:11:00.26#ibcon#about to read 3, iclass 4, count 0 2006.257.09:11:00.31#ibcon#read 3, iclass 4, count 0 2006.257.09:11:00.31#ibcon#about to read 4, iclass 4, count 0 2006.257.09:11:00.31#ibcon#read 4, iclass 4, count 0 2006.257.09:11:00.31#ibcon#about to read 5, iclass 4, count 0 2006.257.09:11:00.31#ibcon#read 5, iclass 4, count 0 2006.257.09:11:00.31#ibcon#about to read 6, iclass 4, count 0 2006.257.09:11:00.31#ibcon#read 6, iclass 4, count 0 2006.257.09:11:00.31#ibcon#end of sib2, iclass 4, count 0 2006.257.09:11:00.31#ibcon#*after write, iclass 4, count 0 2006.257.09:11:00.31#ibcon#*before return 0, iclass 4, count 0 2006.257.09:11:00.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:00.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:00.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:11:00.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:11:00.31$vck44/va=1,8 2006.257.09:11:00.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.09:11:00.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.09:11:00.31#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:00.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:00.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:00.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:00.31#ibcon#enter wrdev, iclass 6, count 2 2006.257.09:11:00.31#ibcon#first serial, iclass 6, count 2 2006.257.09:11:00.31#ibcon#enter sib2, iclass 6, count 2 2006.257.09:11:00.31#ibcon#flushed, iclass 6, count 2 2006.257.09:11:00.31#ibcon#about to write, iclass 6, count 2 2006.257.09:11:00.31#ibcon#wrote, iclass 6, count 2 2006.257.09:11:00.31#ibcon#about to read 3, iclass 6, count 2 2006.257.09:11:00.33#ibcon#read 3, iclass 6, count 2 2006.257.09:11:00.33#ibcon#about to read 4, iclass 6, count 2 2006.257.09:11:00.33#ibcon#read 4, iclass 6, count 2 2006.257.09:11:00.33#ibcon#about to read 5, iclass 6, count 2 2006.257.09:11:00.33#ibcon#read 5, iclass 6, count 2 2006.257.09:11:00.33#ibcon#about to read 6, iclass 6, count 2 2006.257.09:11:00.33#ibcon#read 6, iclass 6, count 2 2006.257.09:11:00.33#ibcon#end of sib2, iclass 6, count 2 2006.257.09:11:00.33#ibcon#*mode == 0, iclass 6, count 2 2006.257.09:11:00.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.09:11:00.33#ibcon#[25=AT01-08\r\n] 2006.257.09:11:00.33#ibcon#*before write, iclass 6, count 2 2006.257.09:11:00.33#ibcon#enter sib2, iclass 6, count 2 2006.257.09:11:00.33#ibcon#flushed, iclass 6, count 2 2006.257.09:11:00.33#ibcon#about to write, iclass 6, count 2 2006.257.09:11:00.33#ibcon#wrote, iclass 6, count 2 2006.257.09:11:00.33#ibcon#about to read 3, iclass 6, count 2 2006.257.09:11:00.36#ibcon#read 3, iclass 6, count 2 2006.257.09:11:00.36#ibcon#about to read 4, iclass 6, count 2 2006.257.09:11:00.36#ibcon#read 4, iclass 6, count 2 2006.257.09:11:00.36#ibcon#about to read 5, iclass 6, count 2 2006.257.09:11:00.36#ibcon#read 5, iclass 6, count 2 2006.257.09:11:00.36#ibcon#about to read 6, iclass 6, count 2 2006.257.09:11:00.36#ibcon#read 6, iclass 6, count 2 2006.257.09:11:00.36#ibcon#end of sib2, iclass 6, count 2 2006.257.09:11:00.36#ibcon#*after write, iclass 6, count 2 2006.257.09:11:00.36#ibcon#*before return 0, iclass 6, count 2 2006.257.09:11:00.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:00.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:00.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.09:11:00.36#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:00.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:00.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:00.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:00.48#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:11:00.48#ibcon#first serial, iclass 6, count 0 2006.257.09:11:00.48#ibcon#enter sib2, iclass 6, count 0 2006.257.09:11:00.48#ibcon#flushed, iclass 6, count 0 2006.257.09:11:00.48#ibcon#about to write, iclass 6, count 0 2006.257.09:11:00.48#ibcon#wrote, iclass 6, count 0 2006.257.09:11:00.48#ibcon#about to read 3, iclass 6, count 0 2006.257.09:11:00.50#ibcon#read 3, iclass 6, count 0 2006.257.09:11:00.50#ibcon#about to read 4, iclass 6, count 0 2006.257.09:11:00.50#ibcon#read 4, iclass 6, count 0 2006.257.09:11:00.50#ibcon#about to read 5, iclass 6, count 0 2006.257.09:11:00.50#ibcon#read 5, iclass 6, count 0 2006.257.09:11:00.50#ibcon#about to read 6, iclass 6, count 0 2006.257.09:11:00.50#ibcon#read 6, iclass 6, count 0 2006.257.09:11:00.50#ibcon#end of sib2, iclass 6, count 0 2006.257.09:11:00.50#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:11:00.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:11:00.50#ibcon#[25=USB\r\n] 2006.257.09:11:00.50#ibcon#*before write, iclass 6, count 0 2006.257.09:11:00.50#ibcon#enter sib2, iclass 6, count 0 2006.257.09:11:00.50#ibcon#flushed, iclass 6, count 0 2006.257.09:11:00.50#ibcon#about to write, iclass 6, count 0 2006.257.09:11:00.50#ibcon#wrote, iclass 6, count 0 2006.257.09:11:00.50#ibcon#about to read 3, iclass 6, count 0 2006.257.09:11:00.53#ibcon#read 3, iclass 6, count 0 2006.257.09:11:00.53#ibcon#about to read 4, iclass 6, count 0 2006.257.09:11:00.53#ibcon#read 4, iclass 6, count 0 2006.257.09:11:00.53#ibcon#about to read 5, iclass 6, count 0 2006.257.09:11:00.53#ibcon#read 5, iclass 6, count 0 2006.257.09:11:00.53#ibcon#about to read 6, iclass 6, count 0 2006.257.09:11:00.53#ibcon#read 6, iclass 6, count 0 2006.257.09:11:00.53#ibcon#end of sib2, iclass 6, count 0 2006.257.09:11:00.53#ibcon#*after write, iclass 6, count 0 2006.257.09:11:00.53#ibcon#*before return 0, iclass 6, count 0 2006.257.09:11:00.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:00.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:00.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:11:00.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:11:00.53$vck44/valo=2,534.99 2006.257.09:11:00.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.09:11:00.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.09:11:00.53#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:00.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:00.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:00.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:00.53#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:11:00.53#ibcon#first serial, iclass 10, count 0 2006.257.09:11:00.53#ibcon#enter sib2, iclass 10, count 0 2006.257.09:11:00.53#ibcon#flushed, iclass 10, count 0 2006.257.09:11:00.53#ibcon#about to write, iclass 10, count 0 2006.257.09:11:00.53#ibcon#wrote, iclass 10, count 0 2006.257.09:11:00.53#ibcon#about to read 3, iclass 10, count 0 2006.257.09:11:00.55#ibcon#read 3, iclass 10, count 0 2006.257.09:11:00.55#ibcon#about to read 4, iclass 10, count 0 2006.257.09:11:00.55#ibcon#read 4, iclass 10, count 0 2006.257.09:11:00.55#ibcon#about to read 5, iclass 10, count 0 2006.257.09:11:00.55#ibcon#read 5, iclass 10, count 0 2006.257.09:11:00.55#ibcon#about to read 6, iclass 10, count 0 2006.257.09:11:00.55#ibcon#read 6, iclass 10, count 0 2006.257.09:11:00.55#ibcon#end of sib2, iclass 10, count 0 2006.257.09:11:00.55#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:11:00.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:11:00.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:11:00.55#ibcon#*before write, iclass 10, count 0 2006.257.09:11:00.55#ibcon#enter sib2, iclass 10, count 0 2006.257.09:11:00.55#ibcon#flushed, iclass 10, count 0 2006.257.09:11:00.55#ibcon#about to write, iclass 10, count 0 2006.257.09:11:00.55#ibcon#wrote, iclass 10, count 0 2006.257.09:11:00.55#ibcon#about to read 3, iclass 10, count 0 2006.257.09:11:00.58#abcon#<5=/14 1.1 2.2 19.96 951013.1\r\n> 2006.257.09:11:00.59#ibcon#read 3, iclass 10, count 0 2006.257.09:11:00.59#ibcon#about to read 4, iclass 10, count 0 2006.257.09:11:00.59#ibcon#read 4, iclass 10, count 0 2006.257.09:11:00.59#ibcon#about to read 5, iclass 10, count 0 2006.257.09:11:00.59#ibcon#read 5, iclass 10, count 0 2006.257.09:11:00.59#ibcon#about to read 6, iclass 10, count 0 2006.257.09:11:00.59#ibcon#read 6, iclass 10, count 0 2006.257.09:11:00.59#ibcon#end of sib2, iclass 10, count 0 2006.257.09:11:00.59#ibcon#*after write, iclass 10, count 0 2006.257.09:11:00.59#ibcon#*before return 0, iclass 10, count 0 2006.257.09:11:00.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:00.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:00.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:11:00.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:11:00.59$vck44/va=2,7 2006.257.09:11:00.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.09:11:00.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.09:11:00.59#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:00.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:11:00.60#abcon#{5=INTERFACE CLEAR} 2006.257.09:11:00.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:11:00.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:11:00.65#ibcon#enter wrdev, iclass 15, count 2 2006.257.09:11:00.65#ibcon#first serial, iclass 15, count 2 2006.257.09:11:00.65#ibcon#enter sib2, iclass 15, count 2 2006.257.09:11:00.65#ibcon#flushed, iclass 15, count 2 2006.257.09:11:00.65#ibcon#about to write, iclass 15, count 2 2006.257.09:11:00.65#ibcon#wrote, iclass 15, count 2 2006.257.09:11:00.65#ibcon#about to read 3, iclass 15, count 2 2006.257.09:11:00.66#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:11:00.67#ibcon#read 3, iclass 15, count 2 2006.257.09:11:00.67#ibcon#about to read 4, iclass 15, count 2 2006.257.09:11:00.67#ibcon#read 4, iclass 15, count 2 2006.257.09:11:00.67#ibcon#about to read 5, iclass 15, count 2 2006.257.09:11:00.67#ibcon#read 5, iclass 15, count 2 2006.257.09:11:00.67#ibcon#about to read 6, iclass 15, count 2 2006.257.09:11:00.67#ibcon#read 6, iclass 15, count 2 2006.257.09:11:00.67#ibcon#end of sib2, iclass 15, count 2 2006.257.09:11:00.67#ibcon#*mode == 0, iclass 15, count 2 2006.257.09:11:00.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.09:11:00.67#ibcon#[25=AT02-07\r\n] 2006.257.09:11:00.67#ibcon#*before write, iclass 15, count 2 2006.257.09:11:00.67#ibcon#enter sib2, iclass 15, count 2 2006.257.09:11:00.67#ibcon#flushed, iclass 15, count 2 2006.257.09:11:00.67#ibcon#about to write, iclass 15, count 2 2006.257.09:11:00.67#ibcon#wrote, iclass 15, count 2 2006.257.09:11:00.67#ibcon#about to read 3, iclass 15, count 2 2006.257.09:11:00.70#ibcon#read 3, iclass 15, count 2 2006.257.09:11:00.70#ibcon#about to read 4, iclass 15, count 2 2006.257.09:11:00.70#ibcon#read 4, iclass 15, count 2 2006.257.09:11:00.70#ibcon#about to read 5, iclass 15, count 2 2006.257.09:11:00.70#ibcon#read 5, iclass 15, count 2 2006.257.09:11:00.70#ibcon#about to read 6, iclass 15, count 2 2006.257.09:11:00.70#ibcon#read 6, iclass 15, count 2 2006.257.09:11:00.70#ibcon#end of sib2, iclass 15, count 2 2006.257.09:11:00.70#ibcon#*after write, iclass 15, count 2 2006.257.09:11:00.70#ibcon#*before return 0, iclass 15, count 2 2006.257.09:11:00.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:11:00.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:11:00.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.09:11:00.70#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:00.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:11:00.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:11:00.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:11:00.82#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:11:00.82#ibcon#first serial, iclass 15, count 0 2006.257.09:11:00.82#ibcon#enter sib2, iclass 15, count 0 2006.257.09:11:00.82#ibcon#flushed, iclass 15, count 0 2006.257.09:11:00.82#ibcon#about to write, iclass 15, count 0 2006.257.09:11:00.82#ibcon#wrote, iclass 15, count 0 2006.257.09:11:00.82#ibcon#about to read 3, iclass 15, count 0 2006.257.09:11:00.84#ibcon#read 3, iclass 15, count 0 2006.257.09:11:00.84#ibcon#about to read 4, iclass 15, count 0 2006.257.09:11:00.84#ibcon#read 4, iclass 15, count 0 2006.257.09:11:00.84#ibcon#about to read 5, iclass 15, count 0 2006.257.09:11:00.84#ibcon#read 5, iclass 15, count 0 2006.257.09:11:00.84#ibcon#about to read 6, iclass 15, count 0 2006.257.09:11:00.84#ibcon#read 6, iclass 15, count 0 2006.257.09:11:00.84#ibcon#end of sib2, iclass 15, count 0 2006.257.09:11:00.84#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:11:00.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:11:00.84#ibcon#[25=USB\r\n] 2006.257.09:11:00.84#ibcon#*before write, iclass 15, count 0 2006.257.09:11:00.84#ibcon#enter sib2, iclass 15, count 0 2006.257.09:11:00.84#ibcon#flushed, iclass 15, count 0 2006.257.09:11:00.84#ibcon#about to write, iclass 15, count 0 2006.257.09:11:00.84#ibcon#wrote, iclass 15, count 0 2006.257.09:11:00.84#ibcon#about to read 3, iclass 15, count 0 2006.257.09:11:00.87#ibcon#read 3, iclass 15, count 0 2006.257.09:11:00.87#ibcon#about to read 4, iclass 15, count 0 2006.257.09:11:00.87#ibcon#read 4, iclass 15, count 0 2006.257.09:11:00.87#ibcon#about to read 5, iclass 15, count 0 2006.257.09:11:00.87#ibcon#read 5, iclass 15, count 0 2006.257.09:11:00.87#ibcon#about to read 6, iclass 15, count 0 2006.257.09:11:00.87#ibcon#read 6, iclass 15, count 0 2006.257.09:11:00.87#ibcon#end of sib2, iclass 15, count 0 2006.257.09:11:00.87#ibcon#*after write, iclass 15, count 0 2006.257.09:11:00.87#ibcon#*before return 0, iclass 15, count 0 2006.257.09:11:00.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:11:00.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:11:00.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:11:00.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:11:00.87$vck44/valo=3,564.99 2006.257.09:11:00.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.09:11:00.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.09:11:00.87#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:00.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:00.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:00.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:00.87#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:11:00.87#ibcon#first serial, iclass 18, count 0 2006.257.09:11:00.87#ibcon#enter sib2, iclass 18, count 0 2006.257.09:11:00.87#ibcon#flushed, iclass 18, count 0 2006.257.09:11:00.87#ibcon#about to write, iclass 18, count 0 2006.257.09:11:00.87#ibcon#wrote, iclass 18, count 0 2006.257.09:11:00.87#ibcon#about to read 3, iclass 18, count 0 2006.257.09:11:00.89#ibcon#read 3, iclass 18, count 0 2006.257.09:11:00.89#ibcon#about to read 4, iclass 18, count 0 2006.257.09:11:00.89#ibcon#read 4, iclass 18, count 0 2006.257.09:11:00.89#ibcon#about to read 5, iclass 18, count 0 2006.257.09:11:00.89#ibcon#read 5, iclass 18, count 0 2006.257.09:11:00.89#ibcon#about to read 6, iclass 18, count 0 2006.257.09:11:00.89#ibcon#read 6, iclass 18, count 0 2006.257.09:11:00.89#ibcon#end of sib2, iclass 18, count 0 2006.257.09:11:00.89#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:11:00.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:11:00.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:11:00.89#ibcon#*before write, iclass 18, count 0 2006.257.09:11:00.89#ibcon#enter sib2, iclass 18, count 0 2006.257.09:11:00.89#ibcon#flushed, iclass 18, count 0 2006.257.09:11:00.89#ibcon#about to write, iclass 18, count 0 2006.257.09:11:00.89#ibcon#wrote, iclass 18, count 0 2006.257.09:11:00.89#ibcon#about to read 3, iclass 18, count 0 2006.257.09:11:00.93#ibcon#read 3, iclass 18, count 0 2006.257.09:11:00.93#ibcon#about to read 4, iclass 18, count 0 2006.257.09:11:00.93#ibcon#read 4, iclass 18, count 0 2006.257.09:11:00.93#ibcon#about to read 5, iclass 18, count 0 2006.257.09:11:00.93#ibcon#read 5, iclass 18, count 0 2006.257.09:11:00.93#ibcon#about to read 6, iclass 18, count 0 2006.257.09:11:00.93#ibcon#read 6, iclass 18, count 0 2006.257.09:11:00.93#ibcon#end of sib2, iclass 18, count 0 2006.257.09:11:00.93#ibcon#*after write, iclass 18, count 0 2006.257.09:11:00.93#ibcon#*before return 0, iclass 18, count 0 2006.257.09:11:00.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:00.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:00.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:11:00.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:11:00.93$vck44/va=3,8 2006.257.09:11:00.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.09:11:00.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.09:11:00.93#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:00.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:00.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:00.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:00.99#ibcon#enter wrdev, iclass 20, count 2 2006.257.09:11:00.99#ibcon#first serial, iclass 20, count 2 2006.257.09:11:00.99#ibcon#enter sib2, iclass 20, count 2 2006.257.09:11:00.99#ibcon#flushed, iclass 20, count 2 2006.257.09:11:00.99#ibcon#about to write, iclass 20, count 2 2006.257.09:11:00.99#ibcon#wrote, iclass 20, count 2 2006.257.09:11:00.99#ibcon#about to read 3, iclass 20, count 2 2006.257.09:11:01.01#ibcon#read 3, iclass 20, count 2 2006.257.09:11:01.01#ibcon#about to read 4, iclass 20, count 2 2006.257.09:11:01.01#ibcon#read 4, iclass 20, count 2 2006.257.09:11:01.01#ibcon#about to read 5, iclass 20, count 2 2006.257.09:11:01.01#ibcon#read 5, iclass 20, count 2 2006.257.09:11:01.01#ibcon#about to read 6, iclass 20, count 2 2006.257.09:11:01.01#ibcon#read 6, iclass 20, count 2 2006.257.09:11:01.01#ibcon#end of sib2, iclass 20, count 2 2006.257.09:11:01.01#ibcon#*mode == 0, iclass 20, count 2 2006.257.09:11:01.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.09:11:01.01#ibcon#[25=AT03-08\r\n] 2006.257.09:11:01.01#ibcon#*before write, iclass 20, count 2 2006.257.09:11:01.01#ibcon#enter sib2, iclass 20, count 2 2006.257.09:11:01.01#ibcon#flushed, iclass 20, count 2 2006.257.09:11:01.01#ibcon#about to write, iclass 20, count 2 2006.257.09:11:01.01#ibcon#wrote, iclass 20, count 2 2006.257.09:11:01.01#ibcon#about to read 3, iclass 20, count 2 2006.257.09:11:01.04#ibcon#read 3, iclass 20, count 2 2006.257.09:11:01.04#ibcon#about to read 4, iclass 20, count 2 2006.257.09:11:01.04#ibcon#read 4, iclass 20, count 2 2006.257.09:11:01.04#ibcon#about to read 5, iclass 20, count 2 2006.257.09:11:01.04#ibcon#read 5, iclass 20, count 2 2006.257.09:11:01.04#ibcon#about to read 6, iclass 20, count 2 2006.257.09:11:01.04#ibcon#read 6, iclass 20, count 2 2006.257.09:11:01.04#ibcon#end of sib2, iclass 20, count 2 2006.257.09:11:01.04#ibcon#*after write, iclass 20, count 2 2006.257.09:11:01.04#ibcon#*before return 0, iclass 20, count 2 2006.257.09:11:01.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:01.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:01.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.09:11:01.04#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:01.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:01.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:01.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:01.16#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:11:01.16#ibcon#first serial, iclass 20, count 0 2006.257.09:11:01.16#ibcon#enter sib2, iclass 20, count 0 2006.257.09:11:01.16#ibcon#flushed, iclass 20, count 0 2006.257.09:11:01.16#ibcon#about to write, iclass 20, count 0 2006.257.09:11:01.16#ibcon#wrote, iclass 20, count 0 2006.257.09:11:01.16#ibcon#about to read 3, iclass 20, count 0 2006.257.09:11:01.18#ibcon#read 3, iclass 20, count 0 2006.257.09:11:01.18#ibcon#about to read 4, iclass 20, count 0 2006.257.09:11:01.18#ibcon#read 4, iclass 20, count 0 2006.257.09:11:01.18#ibcon#about to read 5, iclass 20, count 0 2006.257.09:11:01.18#ibcon#read 5, iclass 20, count 0 2006.257.09:11:01.18#ibcon#about to read 6, iclass 20, count 0 2006.257.09:11:01.18#ibcon#read 6, iclass 20, count 0 2006.257.09:11:01.18#ibcon#end of sib2, iclass 20, count 0 2006.257.09:11:01.18#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:11:01.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:11:01.18#ibcon#[25=USB\r\n] 2006.257.09:11:01.18#ibcon#*before write, iclass 20, count 0 2006.257.09:11:01.18#ibcon#enter sib2, iclass 20, count 0 2006.257.09:11:01.18#ibcon#flushed, iclass 20, count 0 2006.257.09:11:01.18#ibcon#about to write, iclass 20, count 0 2006.257.09:11:01.18#ibcon#wrote, iclass 20, count 0 2006.257.09:11:01.18#ibcon#about to read 3, iclass 20, count 0 2006.257.09:11:01.21#ibcon#read 3, iclass 20, count 0 2006.257.09:11:01.21#ibcon#about to read 4, iclass 20, count 0 2006.257.09:11:01.21#ibcon#read 4, iclass 20, count 0 2006.257.09:11:01.21#ibcon#about to read 5, iclass 20, count 0 2006.257.09:11:01.21#ibcon#read 5, iclass 20, count 0 2006.257.09:11:01.21#ibcon#about to read 6, iclass 20, count 0 2006.257.09:11:01.21#ibcon#read 6, iclass 20, count 0 2006.257.09:11:01.21#ibcon#end of sib2, iclass 20, count 0 2006.257.09:11:01.21#ibcon#*after write, iclass 20, count 0 2006.257.09:11:01.21#ibcon#*before return 0, iclass 20, count 0 2006.257.09:11:01.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:01.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:01.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:11:01.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:11:01.21$vck44/valo=4,624.99 2006.257.09:11:01.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.09:11:01.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.09:11:01.21#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:01.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:01.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:01.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:01.21#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:11:01.21#ibcon#first serial, iclass 22, count 0 2006.257.09:11:01.21#ibcon#enter sib2, iclass 22, count 0 2006.257.09:11:01.21#ibcon#flushed, iclass 22, count 0 2006.257.09:11:01.21#ibcon#about to write, iclass 22, count 0 2006.257.09:11:01.21#ibcon#wrote, iclass 22, count 0 2006.257.09:11:01.21#ibcon#about to read 3, iclass 22, count 0 2006.257.09:11:01.23#ibcon#read 3, iclass 22, count 0 2006.257.09:11:01.23#ibcon#about to read 4, iclass 22, count 0 2006.257.09:11:01.23#ibcon#read 4, iclass 22, count 0 2006.257.09:11:01.23#ibcon#about to read 5, iclass 22, count 0 2006.257.09:11:01.23#ibcon#read 5, iclass 22, count 0 2006.257.09:11:01.23#ibcon#about to read 6, iclass 22, count 0 2006.257.09:11:01.23#ibcon#read 6, iclass 22, count 0 2006.257.09:11:01.23#ibcon#end of sib2, iclass 22, count 0 2006.257.09:11:01.23#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:11:01.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:11:01.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:11:01.23#ibcon#*before write, iclass 22, count 0 2006.257.09:11:01.23#ibcon#enter sib2, iclass 22, count 0 2006.257.09:11:01.23#ibcon#flushed, iclass 22, count 0 2006.257.09:11:01.23#ibcon#about to write, iclass 22, count 0 2006.257.09:11:01.23#ibcon#wrote, iclass 22, count 0 2006.257.09:11:01.23#ibcon#about to read 3, iclass 22, count 0 2006.257.09:11:01.27#ibcon#read 3, iclass 22, count 0 2006.257.09:11:01.27#ibcon#about to read 4, iclass 22, count 0 2006.257.09:11:01.27#ibcon#read 4, iclass 22, count 0 2006.257.09:11:01.27#ibcon#about to read 5, iclass 22, count 0 2006.257.09:11:01.27#ibcon#read 5, iclass 22, count 0 2006.257.09:11:01.27#ibcon#about to read 6, iclass 22, count 0 2006.257.09:11:01.27#ibcon#read 6, iclass 22, count 0 2006.257.09:11:01.27#ibcon#end of sib2, iclass 22, count 0 2006.257.09:11:01.27#ibcon#*after write, iclass 22, count 0 2006.257.09:11:01.27#ibcon#*before return 0, iclass 22, count 0 2006.257.09:11:01.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:01.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:01.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:11:01.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:11:01.27$vck44/va=4,7 2006.257.09:11:01.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.09:11:01.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.09:11:01.27#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:01.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:01.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:01.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:01.33#ibcon#enter wrdev, iclass 24, count 2 2006.257.09:11:01.33#ibcon#first serial, iclass 24, count 2 2006.257.09:11:01.33#ibcon#enter sib2, iclass 24, count 2 2006.257.09:11:01.33#ibcon#flushed, iclass 24, count 2 2006.257.09:11:01.33#ibcon#about to write, iclass 24, count 2 2006.257.09:11:01.33#ibcon#wrote, iclass 24, count 2 2006.257.09:11:01.33#ibcon#about to read 3, iclass 24, count 2 2006.257.09:11:01.35#ibcon#read 3, iclass 24, count 2 2006.257.09:11:01.35#ibcon#about to read 4, iclass 24, count 2 2006.257.09:11:01.35#ibcon#read 4, iclass 24, count 2 2006.257.09:11:01.35#ibcon#about to read 5, iclass 24, count 2 2006.257.09:11:01.35#ibcon#read 5, iclass 24, count 2 2006.257.09:11:01.35#ibcon#about to read 6, iclass 24, count 2 2006.257.09:11:01.35#ibcon#read 6, iclass 24, count 2 2006.257.09:11:01.35#ibcon#end of sib2, iclass 24, count 2 2006.257.09:11:01.35#ibcon#*mode == 0, iclass 24, count 2 2006.257.09:11:01.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.09:11:01.35#ibcon#[25=AT04-07\r\n] 2006.257.09:11:01.35#ibcon#*before write, iclass 24, count 2 2006.257.09:11:01.35#ibcon#enter sib2, iclass 24, count 2 2006.257.09:11:01.35#ibcon#flushed, iclass 24, count 2 2006.257.09:11:01.35#ibcon#about to write, iclass 24, count 2 2006.257.09:11:01.35#ibcon#wrote, iclass 24, count 2 2006.257.09:11:01.35#ibcon#about to read 3, iclass 24, count 2 2006.257.09:11:01.38#ibcon#read 3, iclass 24, count 2 2006.257.09:11:01.38#ibcon#about to read 4, iclass 24, count 2 2006.257.09:11:01.38#ibcon#read 4, iclass 24, count 2 2006.257.09:11:01.38#ibcon#about to read 5, iclass 24, count 2 2006.257.09:11:01.38#ibcon#read 5, iclass 24, count 2 2006.257.09:11:01.38#ibcon#about to read 6, iclass 24, count 2 2006.257.09:11:01.40#ibcon#read 6, iclass 24, count 2 2006.257.09:11:01.40#ibcon#end of sib2, iclass 24, count 2 2006.257.09:11:01.40#ibcon#*after write, iclass 24, count 2 2006.257.09:11:01.40#ibcon#*before return 0, iclass 24, count 2 2006.257.09:11:01.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:01.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:01.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.09:11:01.40#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:01.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:01.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:01.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:01.51#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:11:01.51#ibcon#first serial, iclass 24, count 0 2006.257.09:11:01.51#ibcon#enter sib2, iclass 24, count 0 2006.257.09:11:01.51#ibcon#flushed, iclass 24, count 0 2006.257.09:11:01.51#ibcon#about to write, iclass 24, count 0 2006.257.09:11:01.51#ibcon#wrote, iclass 24, count 0 2006.257.09:11:01.51#ibcon#about to read 3, iclass 24, count 0 2006.257.09:11:01.53#ibcon#read 3, iclass 24, count 0 2006.257.09:11:01.53#ibcon#about to read 4, iclass 24, count 0 2006.257.09:11:01.53#ibcon#read 4, iclass 24, count 0 2006.257.09:11:01.53#ibcon#about to read 5, iclass 24, count 0 2006.257.09:11:01.53#ibcon#read 5, iclass 24, count 0 2006.257.09:11:01.53#ibcon#about to read 6, iclass 24, count 0 2006.257.09:11:01.53#ibcon#read 6, iclass 24, count 0 2006.257.09:11:01.53#ibcon#end of sib2, iclass 24, count 0 2006.257.09:11:01.53#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:11:01.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:11:01.53#ibcon#[25=USB\r\n] 2006.257.09:11:01.53#ibcon#*before write, iclass 24, count 0 2006.257.09:11:01.53#ibcon#enter sib2, iclass 24, count 0 2006.257.09:11:01.53#ibcon#flushed, iclass 24, count 0 2006.257.09:11:01.53#ibcon#about to write, iclass 24, count 0 2006.257.09:11:01.53#ibcon#wrote, iclass 24, count 0 2006.257.09:11:01.53#ibcon#about to read 3, iclass 24, count 0 2006.257.09:11:01.56#ibcon#read 3, iclass 24, count 0 2006.257.09:11:01.56#ibcon#about to read 4, iclass 24, count 0 2006.257.09:11:01.56#ibcon#read 4, iclass 24, count 0 2006.257.09:11:01.56#ibcon#about to read 5, iclass 24, count 0 2006.257.09:11:01.56#ibcon#read 5, iclass 24, count 0 2006.257.09:11:01.56#ibcon#about to read 6, iclass 24, count 0 2006.257.09:11:01.56#ibcon#read 6, iclass 24, count 0 2006.257.09:11:01.56#ibcon#end of sib2, iclass 24, count 0 2006.257.09:11:01.56#ibcon#*after write, iclass 24, count 0 2006.257.09:11:01.56#ibcon#*before return 0, iclass 24, count 0 2006.257.09:11:01.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:01.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:01.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:11:01.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:11:01.56$vck44/valo=5,734.99 2006.257.09:11:01.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.09:11:01.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.09:11:01.56#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:01.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:01.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:01.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:01.56#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:11:01.56#ibcon#first serial, iclass 26, count 0 2006.257.09:11:01.56#ibcon#enter sib2, iclass 26, count 0 2006.257.09:11:01.56#ibcon#flushed, iclass 26, count 0 2006.257.09:11:01.56#ibcon#about to write, iclass 26, count 0 2006.257.09:11:01.56#ibcon#wrote, iclass 26, count 0 2006.257.09:11:01.56#ibcon#about to read 3, iclass 26, count 0 2006.257.09:11:01.58#ibcon#read 3, iclass 26, count 0 2006.257.09:11:01.58#ibcon#about to read 4, iclass 26, count 0 2006.257.09:11:01.58#ibcon#read 4, iclass 26, count 0 2006.257.09:11:01.58#ibcon#about to read 5, iclass 26, count 0 2006.257.09:11:01.58#ibcon#read 5, iclass 26, count 0 2006.257.09:11:01.58#ibcon#about to read 6, iclass 26, count 0 2006.257.09:11:01.58#ibcon#read 6, iclass 26, count 0 2006.257.09:11:01.58#ibcon#end of sib2, iclass 26, count 0 2006.257.09:11:01.58#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:11:01.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:11:01.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:11:01.58#ibcon#*before write, iclass 26, count 0 2006.257.09:11:01.58#ibcon#enter sib2, iclass 26, count 0 2006.257.09:11:01.58#ibcon#flushed, iclass 26, count 0 2006.257.09:11:01.58#ibcon#about to write, iclass 26, count 0 2006.257.09:11:01.58#ibcon#wrote, iclass 26, count 0 2006.257.09:11:01.58#ibcon#about to read 3, iclass 26, count 0 2006.257.09:11:01.62#ibcon#read 3, iclass 26, count 0 2006.257.09:11:01.62#ibcon#about to read 4, iclass 26, count 0 2006.257.09:11:01.62#ibcon#read 4, iclass 26, count 0 2006.257.09:11:01.62#ibcon#about to read 5, iclass 26, count 0 2006.257.09:11:01.62#ibcon#read 5, iclass 26, count 0 2006.257.09:11:01.62#ibcon#about to read 6, iclass 26, count 0 2006.257.09:11:01.62#ibcon#read 6, iclass 26, count 0 2006.257.09:11:01.62#ibcon#end of sib2, iclass 26, count 0 2006.257.09:11:01.62#ibcon#*after write, iclass 26, count 0 2006.257.09:11:01.62#ibcon#*before return 0, iclass 26, count 0 2006.257.09:11:01.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:01.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:01.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:11:01.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:11:01.62$vck44/va=5,4 2006.257.09:11:01.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.09:11:01.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.09:11:01.62#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:01.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:01.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:01.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:01.68#ibcon#enter wrdev, iclass 28, count 2 2006.257.09:11:01.68#ibcon#first serial, iclass 28, count 2 2006.257.09:11:01.68#ibcon#enter sib2, iclass 28, count 2 2006.257.09:11:01.68#ibcon#flushed, iclass 28, count 2 2006.257.09:11:01.68#ibcon#about to write, iclass 28, count 2 2006.257.09:11:01.68#ibcon#wrote, iclass 28, count 2 2006.257.09:11:01.68#ibcon#about to read 3, iclass 28, count 2 2006.257.09:11:01.70#ibcon#read 3, iclass 28, count 2 2006.257.09:11:01.70#ibcon#about to read 4, iclass 28, count 2 2006.257.09:11:01.70#ibcon#read 4, iclass 28, count 2 2006.257.09:11:01.70#ibcon#about to read 5, iclass 28, count 2 2006.257.09:11:01.70#ibcon#read 5, iclass 28, count 2 2006.257.09:11:01.70#ibcon#about to read 6, iclass 28, count 2 2006.257.09:11:01.70#ibcon#read 6, iclass 28, count 2 2006.257.09:11:01.70#ibcon#end of sib2, iclass 28, count 2 2006.257.09:11:01.70#ibcon#*mode == 0, iclass 28, count 2 2006.257.09:11:01.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.09:11:01.70#ibcon#[25=AT05-04\r\n] 2006.257.09:11:01.70#ibcon#*before write, iclass 28, count 2 2006.257.09:11:01.70#ibcon#enter sib2, iclass 28, count 2 2006.257.09:11:01.70#ibcon#flushed, iclass 28, count 2 2006.257.09:11:01.70#ibcon#about to write, iclass 28, count 2 2006.257.09:11:01.70#ibcon#wrote, iclass 28, count 2 2006.257.09:11:01.70#ibcon#about to read 3, iclass 28, count 2 2006.257.09:11:01.73#ibcon#read 3, iclass 28, count 2 2006.257.09:11:01.73#ibcon#about to read 4, iclass 28, count 2 2006.257.09:11:01.73#ibcon#read 4, iclass 28, count 2 2006.257.09:11:01.73#ibcon#about to read 5, iclass 28, count 2 2006.257.09:11:01.73#ibcon#read 5, iclass 28, count 2 2006.257.09:11:01.73#ibcon#about to read 6, iclass 28, count 2 2006.257.09:11:01.73#ibcon#read 6, iclass 28, count 2 2006.257.09:11:01.73#ibcon#end of sib2, iclass 28, count 2 2006.257.09:11:01.73#ibcon#*after write, iclass 28, count 2 2006.257.09:11:01.73#ibcon#*before return 0, iclass 28, count 2 2006.257.09:11:01.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:01.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:01.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.09:11:01.73#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:01.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:01.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:01.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:01.85#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:11:01.85#ibcon#first serial, iclass 28, count 0 2006.257.09:11:01.85#ibcon#enter sib2, iclass 28, count 0 2006.257.09:11:01.85#ibcon#flushed, iclass 28, count 0 2006.257.09:11:01.85#ibcon#about to write, iclass 28, count 0 2006.257.09:11:01.85#ibcon#wrote, iclass 28, count 0 2006.257.09:11:01.85#ibcon#about to read 3, iclass 28, count 0 2006.257.09:11:01.87#ibcon#read 3, iclass 28, count 0 2006.257.09:11:01.87#ibcon#about to read 4, iclass 28, count 0 2006.257.09:11:01.87#ibcon#read 4, iclass 28, count 0 2006.257.09:11:01.87#ibcon#about to read 5, iclass 28, count 0 2006.257.09:11:01.87#ibcon#read 5, iclass 28, count 0 2006.257.09:11:01.87#ibcon#about to read 6, iclass 28, count 0 2006.257.09:11:01.87#ibcon#read 6, iclass 28, count 0 2006.257.09:11:01.87#ibcon#end of sib2, iclass 28, count 0 2006.257.09:11:01.87#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:11:01.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:11:01.87#ibcon#[25=USB\r\n] 2006.257.09:11:01.87#ibcon#*before write, iclass 28, count 0 2006.257.09:11:01.87#ibcon#enter sib2, iclass 28, count 0 2006.257.09:11:01.87#ibcon#flushed, iclass 28, count 0 2006.257.09:11:01.87#ibcon#about to write, iclass 28, count 0 2006.257.09:11:01.87#ibcon#wrote, iclass 28, count 0 2006.257.09:11:01.87#ibcon#about to read 3, iclass 28, count 0 2006.257.09:11:01.90#ibcon#read 3, iclass 28, count 0 2006.257.09:11:01.90#ibcon#about to read 4, iclass 28, count 0 2006.257.09:11:01.90#ibcon#read 4, iclass 28, count 0 2006.257.09:11:01.90#ibcon#about to read 5, iclass 28, count 0 2006.257.09:11:01.90#ibcon#read 5, iclass 28, count 0 2006.257.09:11:01.90#ibcon#about to read 6, iclass 28, count 0 2006.257.09:11:01.90#ibcon#read 6, iclass 28, count 0 2006.257.09:11:01.90#ibcon#end of sib2, iclass 28, count 0 2006.257.09:11:01.90#ibcon#*after write, iclass 28, count 0 2006.257.09:11:01.90#ibcon#*before return 0, iclass 28, count 0 2006.257.09:11:01.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:01.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:01.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:11:01.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:11:01.90$vck44/valo=6,814.99 2006.257.09:11:01.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.09:11:01.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.09:11:01.90#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:01.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:01.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:01.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:01.90#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:11:01.90#ibcon#first serial, iclass 30, count 0 2006.257.09:11:01.90#ibcon#enter sib2, iclass 30, count 0 2006.257.09:11:01.90#ibcon#flushed, iclass 30, count 0 2006.257.09:11:01.90#ibcon#about to write, iclass 30, count 0 2006.257.09:11:01.90#ibcon#wrote, iclass 30, count 0 2006.257.09:11:01.90#ibcon#about to read 3, iclass 30, count 0 2006.257.09:11:01.92#ibcon#read 3, iclass 30, count 0 2006.257.09:11:01.92#ibcon#about to read 4, iclass 30, count 0 2006.257.09:11:01.92#ibcon#read 4, iclass 30, count 0 2006.257.09:11:01.92#ibcon#about to read 5, iclass 30, count 0 2006.257.09:11:01.92#ibcon#read 5, iclass 30, count 0 2006.257.09:11:01.92#ibcon#about to read 6, iclass 30, count 0 2006.257.09:11:01.92#ibcon#read 6, iclass 30, count 0 2006.257.09:11:01.92#ibcon#end of sib2, iclass 30, count 0 2006.257.09:11:01.92#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:11:01.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:11:01.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:11:01.92#ibcon#*before write, iclass 30, count 0 2006.257.09:11:01.92#ibcon#enter sib2, iclass 30, count 0 2006.257.09:11:01.92#ibcon#flushed, iclass 30, count 0 2006.257.09:11:01.92#ibcon#about to write, iclass 30, count 0 2006.257.09:11:01.92#ibcon#wrote, iclass 30, count 0 2006.257.09:11:01.92#ibcon#about to read 3, iclass 30, count 0 2006.257.09:11:01.96#ibcon#read 3, iclass 30, count 0 2006.257.09:11:01.96#ibcon#about to read 4, iclass 30, count 0 2006.257.09:11:01.96#ibcon#read 4, iclass 30, count 0 2006.257.09:11:01.96#ibcon#about to read 5, iclass 30, count 0 2006.257.09:11:01.96#ibcon#read 5, iclass 30, count 0 2006.257.09:11:01.96#ibcon#about to read 6, iclass 30, count 0 2006.257.09:11:01.96#ibcon#read 6, iclass 30, count 0 2006.257.09:11:01.96#ibcon#end of sib2, iclass 30, count 0 2006.257.09:11:01.96#ibcon#*after write, iclass 30, count 0 2006.257.09:11:01.96#ibcon#*before return 0, iclass 30, count 0 2006.257.09:11:01.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:01.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:01.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:11:01.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:11:01.96$vck44/va=6,4 2006.257.09:11:01.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.09:11:01.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.09:11:01.96#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:01.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:02.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:02.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:02.02#ibcon#enter wrdev, iclass 32, count 2 2006.257.09:11:02.02#ibcon#first serial, iclass 32, count 2 2006.257.09:11:02.02#ibcon#enter sib2, iclass 32, count 2 2006.257.09:11:02.02#ibcon#flushed, iclass 32, count 2 2006.257.09:11:02.02#ibcon#about to write, iclass 32, count 2 2006.257.09:11:02.02#ibcon#wrote, iclass 32, count 2 2006.257.09:11:02.02#ibcon#about to read 3, iclass 32, count 2 2006.257.09:11:02.04#ibcon#read 3, iclass 32, count 2 2006.257.09:11:02.04#ibcon#about to read 4, iclass 32, count 2 2006.257.09:11:02.04#ibcon#read 4, iclass 32, count 2 2006.257.09:11:02.04#ibcon#about to read 5, iclass 32, count 2 2006.257.09:11:02.04#ibcon#read 5, iclass 32, count 2 2006.257.09:11:02.04#ibcon#about to read 6, iclass 32, count 2 2006.257.09:11:02.04#ibcon#read 6, iclass 32, count 2 2006.257.09:11:02.04#ibcon#end of sib2, iclass 32, count 2 2006.257.09:11:02.04#ibcon#*mode == 0, iclass 32, count 2 2006.257.09:11:02.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.09:11:02.04#ibcon#[25=AT06-04\r\n] 2006.257.09:11:02.04#ibcon#*before write, iclass 32, count 2 2006.257.09:11:02.04#ibcon#enter sib2, iclass 32, count 2 2006.257.09:11:02.04#ibcon#flushed, iclass 32, count 2 2006.257.09:11:02.04#ibcon#about to write, iclass 32, count 2 2006.257.09:11:02.04#ibcon#wrote, iclass 32, count 2 2006.257.09:11:02.04#ibcon#about to read 3, iclass 32, count 2 2006.257.09:11:02.07#ibcon#read 3, iclass 32, count 2 2006.257.09:11:02.07#ibcon#about to read 4, iclass 32, count 2 2006.257.09:11:02.07#ibcon#read 4, iclass 32, count 2 2006.257.09:11:02.07#ibcon#about to read 5, iclass 32, count 2 2006.257.09:11:02.07#ibcon#read 5, iclass 32, count 2 2006.257.09:11:02.07#ibcon#about to read 6, iclass 32, count 2 2006.257.09:11:02.07#ibcon#read 6, iclass 32, count 2 2006.257.09:11:02.07#ibcon#end of sib2, iclass 32, count 2 2006.257.09:11:02.07#ibcon#*after write, iclass 32, count 2 2006.257.09:11:02.07#ibcon#*before return 0, iclass 32, count 2 2006.257.09:11:02.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:02.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:02.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.09:11:02.07#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:02.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:02.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:02.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:02.19#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:11:02.19#ibcon#first serial, iclass 32, count 0 2006.257.09:11:02.19#ibcon#enter sib2, iclass 32, count 0 2006.257.09:11:02.19#ibcon#flushed, iclass 32, count 0 2006.257.09:11:02.19#ibcon#about to write, iclass 32, count 0 2006.257.09:11:02.19#ibcon#wrote, iclass 32, count 0 2006.257.09:11:02.19#ibcon#about to read 3, iclass 32, count 0 2006.257.09:11:02.21#ibcon#read 3, iclass 32, count 0 2006.257.09:11:02.21#ibcon#about to read 4, iclass 32, count 0 2006.257.09:11:02.21#ibcon#read 4, iclass 32, count 0 2006.257.09:11:02.21#ibcon#about to read 5, iclass 32, count 0 2006.257.09:11:02.21#ibcon#read 5, iclass 32, count 0 2006.257.09:11:02.21#ibcon#about to read 6, iclass 32, count 0 2006.257.09:11:02.21#ibcon#read 6, iclass 32, count 0 2006.257.09:11:02.21#ibcon#end of sib2, iclass 32, count 0 2006.257.09:11:02.21#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:11:02.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:11:02.21#ibcon#[25=USB\r\n] 2006.257.09:11:02.21#ibcon#*before write, iclass 32, count 0 2006.257.09:11:02.21#ibcon#enter sib2, iclass 32, count 0 2006.257.09:11:02.21#ibcon#flushed, iclass 32, count 0 2006.257.09:11:02.21#ibcon#about to write, iclass 32, count 0 2006.257.09:11:02.21#ibcon#wrote, iclass 32, count 0 2006.257.09:11:02.21#ibcon#about to read 3, iclass 32, count 0 2006.257.09:11:02.24#ibcon#read 3, iclass 32, count 0 2006.257.09:11:02.24#ibcon#about to read 4, iclass 32, count 0 2006.257.09:11:02.24#ibcon#read 4, iclass 32, count 0 2006.257.09:11:02.24#ibcon#about to read 5, iclass 32, count 0 2006.257.09:11:02.24#ibcon#read 5, iclass 32, count 0 2006.257.09:11:02.24#ibcon#about to read 6, iclass 32, count 0 2006.257.09:11:02.24#ibcon#read 6, iclass 32, count 0 2006.257.09:11:02.24#ibcon#end of sib2, iclass 32, count 0 2006.257.09:11:02.24#ibcon#*after write, iclass 32, count 0 2006.257.09:11:02.24#ibcon#*before return 0, iclass 32, count 0 2006.257.09:11:02.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:02.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:02.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:11:02.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:11:02.24$vck44/valo=7,864.99 2006.257.09:11:02.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.09:11:02.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.09:11:02.24#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:02.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:02.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:02.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:02.24#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:11:02.24#ibcon#first serial, iclass 34, count 0 2006.257.09:11:02.24#ibcon#enter sib2, iclass 34, count 0 2006.257.09:11:02.24#ibcon#flushed, iclass 34, count 0 2006.257.09:11:02.24#ibcon#about to write, iclass 34, count 0 2006.257.09:11:02.24#ibcon#wrote, iclass 34, count 0 2006.257.09:11:02.24#ibcon#about to read 3, iclass 34, count 0 2006.257.09:11:02.26#ibcon#read 3, iclass 34, count 0 2006.257.09:11:02.26#ibcon#about to read 4, iclass 34, count 0 2006.257.09:11:02.26#ibcon#read 4, iclass 34, count 0 2006.257.09:11:02.26#ibcon#about to read 5, iclass 34, count 0 2006.257.09:11:02.26#ibcon#read 5, iclass 34, count 0 2006.257.09:11:02.26#ibcon#about to read 6, iclass 34, count 0 2006.257.09:11:02.26#ibcon#read 6, iclass 34, count 0 2006.257.09:11:02.26#ibcon#end of sib2, iclass 34, count 0 2006.257.09:11:02.26#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:11:02.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:11:02.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:11:02.26#ibcon#*before write, iclass 34, count 0 2006.257.09:11:02.26#ibcon#enter sib2, iclass 34, count 0 2006.257.09:11:02.26#ibcon#flushed, iclass 34, count 0 2006.257.09:11:02.26#ibcon#about to write, iclass 34, count 0 2006.257.09:11:02.26#ibcon#wrote, iclass 34, count 0 2006.257.09:11:02.26#ibcon#about to read 3, iclass 34, count 0 2006.257.09:11:02.30#ibcon#read 3, iclass 34, count 0 2006.257.09:11:02.30#ibcon#about to read 4, iclass 34, count 0 2006.257.09:11:02.30#ibcon#read 4, iclass 34, count 0 2006.257.09:11:02.30#ibcon#about to read 5, iclass 34, count 0 2006.257.09:11:02.30#ibcon#read 5, iclass 34, count 0 2006.257.09:11:02.30#ibcon#about to read 6, iclass 34, count 0 2006.257.09:11:02.30#ibcon#read 6, iclass 34, count 0 2006.257.09:11:02.30#ibcon#end of sib2, iclass 34, count 0 2006.257.09:11:02.30#ibcon#*after write, iclass 34, count 0 2006.257.09:11:02.30#ibcon#*before return 0, iclass 34, count 0 2006.257.09:11:02.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:02.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:02.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:11:02.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:11:02.30$vck44/va=7,4 2006.257.09:11:02.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.09:11:02.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.09:11:02.30#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:02.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:02.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:02.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:02.36#ibcon#enter wrdev, iclass 36, count 2 2006.257.09:11:02.36#ibcon#first serial, iclass 36, count 2 2006.257.09:11:02.36#ibcon#enter sib2, iclass 36, count 2 2006.257.09:11:02.36#ibcon#flushed, iclass 36, count 2 2006.257.09:11:02.36#ibcon#about to write, iclass 36, count 2 2006.257.09:11:02.36#ibcon#wrote, iclass 36, count 2 2006.257.09:11:02.36#ibcon#about to read 3, iclass 36, count 2 2006.257.09:11:02.38#ibcon#read 3, iclass 36, count 2 2006.257.09:11:02.38#ibcon#about to read 4, iclass 36, count 2 2006.257.09:11:02.38#ibcon#read 4, iclass 36, count 2 2006.257.09:11:02.38#ibcon#about to read 5, iclass 36, count 2 2006.257.09:11:02.38#ibcon#read 5, iclass 36, count 2 2006.257.09:11:02.38#ibcon#about to read 6, iclass 36, count 2 2006.257.09:11:02.38#ibcon#read 6, iclass 36, count 2 2006.257.09:11:02.38#ibcon#end of sib2, iclass 36, count 2 2006.257.09:11:02.38#ibcon#*mode == 0, iclass 36, count 2 2006.257.09:11:02.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.09:11:02.38#ibcon#[25=AT07-04\r\n] 2006.257.09:11:02.38#ibcon#*before write, iclass 36, count 2 2006.257.09:11:02.38#ibcon#enter sib2, iclass 36, count 2 2006.257.09:11:02.38#ibcon#flushed, iclass 36, count 2 2006.257.09:11:02.38#ibcon#about to write, iclass 36, count 2 2006.257.09:11:02.38#ibcon#wrote, iclass 36, count 2 2006.257.09:11:02.38#ibcon#about to read 3, iclass 36, count 2 2006.257.09:11:02.41#ibcon#read 3, iclass 36, count 2 2006.257.09:11:02.41#ibcon#about to read 4, iclass 36, count 2 2006.257.09:11:02.41#ibcon#read 4, iclass 36, count 2 2006.257.09:11:02.41#ibcon#about to read 5, iclass 36, count 2 2006.257.09:11:02.41#ibcon#read 5, iclass 36, count 2 2006.257.09:11:02.41#ibcon#about to read 6, iclass 36, count 2 2006.257.09:11:02.41#ibcon#read 6, iclass 36, count 2 2006.257.09:11:02.41#ibcon#end of sib2, iclass 36, count 2 2006.257.09:11:02.41#ibcon#*after write, iclass 36, count 2 2006.257.09:11:02.41#ibcon#*before return 0, iclass 36, count 2 2006.257.09:11:02.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:02.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:02.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.09:11:02.41#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:02.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:02.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:02.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:02.53#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:11:02.53#ibcon#first serial, iclass 36, count 0 2006.257.09:11:02.53#ibcon#enter sib2, iclass 36, count 0 2006.257.09:11:02.53#ibcon#flushed, iclass 36, count 0 2006.257.09:11:02.53#ibcon#about to write, iclass 36, count 0 2006.257.09:11:02.53#ibcon#wrote, iclass 36, count 0 2006.257.09:11:02.53#ibcon#about to read 3, iclass 36, count 0 2006.257.09:11:02.55#ibcon#read 3, iclass 36, count 0 2006.257.09:11:02.55#ibcon#about to read 4, iclass 36, count 0 2006.257.09:11:02.55#ibcon#read 4, iclass 36, count 0 2006.257.09:11:02.55#ibcon#about to read 5, iclass 36, count 0 2006.257.09:11:02.55#ibcon#read 5, iclass 36, count 0 2006.257.09:11:02.55#ibcon#about to read 6, iclass 36, count 0 2006.257.09:11:02.55#ibcon#read 6, iclass 36, count 0 2006.257.09:11:02.55#ibcon#end of sib2, iclass 36, count 0 2006.257.09:11:02.55#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:11:02.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:11:02.55#ibcon#[25=USB\r\n] 2006.257.09:11:02.55#ibcon#*before write, iclass 36, count 0 2006.257.09:11:02.55#ibcon#enter sib2, iclass 36, count 0 2006.257.09:11:02.55#ibcon#flushed, iclass 36, count 0 2006.257.09:11:02.55#ibcon#about to write, iclass 36, count 0 2006.257.09:11:02.55#ibcon#wrote, iclass 36, count 0 2006.257.09:11:02.55#ibcon#about to read 3, iclass 36, count 0 2006.257.09:11:02.58#ibcon#read 3, iclass 36, count 0 2006.257.09:11:02.58#ibcon#about to read 4, iclass 36, count 0 2006.257.09:11:02.58#ibcon#read 4, iclass 36, count 0 2006.257.09:11:02.58#ibcon#about to read 5, iclass 36, count 0 2006.257.09:11:02.58#ibcon#read 5, iclass 36, count 0 2006.257.09:11:02.58#ibcon#about to read 6, iclass 36, count 0 2006.257.09:11:02.58#ibcon#read 6, iclass 36, count 0 2006.257.09:11:02.58#ibcon#end of sib2, iclass 36, count 0 2006.257.09:11:02.58#ibcon#*after write, iclass 36, count 0 2006.257.09:11:02.58#ibcon#*before return 0, iclass 36, count 0 2006.257.09:11:02.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:02.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:02.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:11:02.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:11:02.58$vck44/valo=8,884.99 2006.257.09:11:02.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.09:11:02.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.09:11:02.58#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:02.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:02.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:02.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:02.58#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:11:02.58#ibcon#first serial, iclass 38, count 0 2006.257.09:11:02.58#ibcon#enter sib2, iclass 38, count 0 2006.257.09:11:02.58#ibcon#flushed, iclass 38, count 0 2006.257.09:11:02.58#ibcon#about to write, iclass 38, count 0 2006.257.09:11:02.58#ibcon#wrote, iclass 38, count 0 2006.257.09:11:02.58#ibcon#about to read 3, iclass 38, count 0 2006.257.09:11:02.60#ibcon#read 3, iclass 38, count 0 2006.257.09:11:02.60#ibcon#about to read 4, iclass 38, count 0 2006.257.09:11:02.60#ibcon#read 4, iclass 38, count 0 2006.257.09:11:02.60#ibcon#about to read 5, iclass 38, count 0 2006.257.09:11:02.60#ibcon#read 5, iclass 38, count 0 2006.257.09:11:02.60#ibcon#about to read 6, iclass 38, count 0 2006.257.09:11:02.60#ibcon#read 6, iclass 38, count 0 2006.257.09:11:02.60#ibcon#end of sib2, iclass 38, count 0 2006.257.09:11:02.60#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:11:02.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:11:02.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:11:02.60#ibcon#*before write, iclass 38, count 0 2006.257.09:11:02.60#ibcon#enter sib2, iclass 38, count 0 2006.257.09:11:02.60#ibcon#flushed, iclass 38, count 0 2006.257.09:11:02.60#ibcon#about to write, iclass 38, count 0 2006.257.09:11:02.60#ibcon#wrote, iclass 38, count 0 2006.257.09:11:02.60#ibcon#about to read 3, iclass 38, count 0 2006.257.09:11:02.64#ibcon#read 3, iclass 38, count 0 2006.257.09:11:02.64#ibcon#about to read 4, iclass 38, count 0 2006.257.09:11:02.64#ibcon#read 4, iclass 38, count 0 2006.257.09:11:02.64#ibcon#about to read 5, iclass 38, count 0 2006.257.09:11:02.64#ibcon#read 5, iclass 38, count 0 2006.257.09:11:02.64#ibcon#about to read 6, iclass 38, count 0 2006.257.09:11:02.64#ibcon#read 6, iclass 38, count 0 2006.257.09:11:02.64#ibcon#end of sib2, iclass 38, count 0 2006.257.09:11:02.64#ibcon#*after write, iclass 38, count 0 2006.257.09:11:02.64#ibcon#*before return 0, iclass 38, count 0 2006.257.09:11:02.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:02.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:02.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:11:02.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:11:02.64$vck44/va=8,4 2006.257.09:11:02.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.09:11:02.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.09:11:02.64#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:02.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:11:02.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:11:02.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:11:02.70#ibcon#enter wrdev, iclass 40, count 2 2006.257.09:11:02.70#ibcon#first serial, iclass 40, count 2 2006.257.09:11:02.70#ibcon#enter sib2, iclass 40, count 2 2006.257.09:11:02.70#ibcon#flushed, iclass 40, count 2 2006.257.09:11:02.70#ibcon#about to write, iclass 40, count 2 2006.257.09:11:02.70#ibcon#wrote, iclass 40, count 2 2006.257.09:11:02.70#ibcon#about to read 3, iclass 40, count 2 2006.257.09:11:02.72#ibcon#read 3, iclass 40, count 2 2006.257.09:11:02.72#ibcon#about to read 4, iclass 40, count 2 2006.257.09:11:02.72#ibcon#read 4, iclass 40, count 2 2006.257.09:11:02.72#ibcon#about to read 5, iclass 40, count 2 2006.257.09:11:02.72#ibcon#read 5, iclass 40, count 2 2006.257.09:11:02.72#ibcon#about to read 6, iclass 40, count 2 2006.257.09:11:02.72#ibcon#read 6, iclass 40, count 2 2006.257.09:11:02.72#ibcon#end of sib2, iclass 40, count 2 2006.257.09:11:02.72#ibcon#*mode == 0, iclass 40, count 2 2006.257.09:11:02.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.09:11:02.72#ibcon#[25=AT08-04\r\n] 2006.257.09:11:02.72#ibcon#*before write, iclass 40, count 2 2006.257.09:11:02.72#ibcon#enter sib2, iclass 40, count 2 2006.257.09:11:02.72#ibcon#flushed, iclass 40, count 2 2006.257.09:11:02.72#ibcon#about to write, iclass 40, count 2 2006.257.09:11:02.72#ibcon#wrote, iclass 40, count 2 2006.257.09:11:02.72#ibcon#about to read 3, iclass 40, count 2 2006.257.09:11:02.75#ibcon#read 3, iclass 40, count 2 2006.257.09:11:02.75#ibcon#about to read 4, iclass 40, count 2 2006.257.09:11:02.75#ibcon#read 4, iclass 40, count 2 2006.257.09:11:02.75#ibcon#about to read 5, iclass 40, count 2 2006.257.09:11:02.75#ibcon#read 5, iclass 40, count 2 2006.257.09:11:02.75#ibcon#about to read 6, iclass 40, count 2 2006.257.09:11:02.75#ibcon#read 6, iclass 40, count 2 2006.257.09:11:02.75#ibcon#end of sib2, iclass 40, count 2 2006.257.09:11:02.75#ibcon#*after write, iclass 40, count 2 2006.257.09:11:02.75#ibcon#*before return 0, iclass 40, count 2 2006.257.09:11:02.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:11:02.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:11:02.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.09:11:02.75#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:02.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:11:02.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:11:02.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:11:02.87#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:11:02.87#ibcon#first serial, iclass 40, count 0 2006.257.09:11:02.87#ibcon#enter sib2, iclass 40, count 0 2006.257.09:11:02.87#ibcon#flushed, iclass 40, count 0 2006.257.09:11:02.87#ibcon#about to write, iclass 40, count 0 2006.257.09:11:02.87#ibcon#wrote, iclass 40, count 0 2006.257.09:11:02.87#ibcon#about to read 3, iclass 40, count 0 2006.257.09:11:02.89#ibcon#read 3, iclass 40, count 0 2006.257.09:11:02.89#ibcon#about to read 4, iclass 40, count 0 2006.257.09:11:02.89#ibcon#read 4, iclass 40, count 0 2006.257.09:11:02.89#ibcon#about to read 5, iclass 40, count 0 2006.257.09:11:02.89#ibcon#read 5, iclass 40, count 0 2006.257.09:11:02.89#ibcon#about to read 6, iclass 40, count 0 2006.257.09:11:02.89#ibcon#read 6, iclass 40, count 0 2006.257.09:11:02.89#ibcon#end of sib2, iclass 40, count 0 2006.257.09:11:02.89#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:11:02.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:11:02.89#ibcon#[25=USB\r\n] 2006.257.09:11:02.89#ibcon#*before write, iclass 40, count 0 2006.257.09:11:02.89#ibcon#enter sib2, iclass 40, count 0 2006.257.09:11:02.89#ibcon#flushed, iclass 40, count 0 2006.257.09:11:02.89#ibcon#about to write, iclass 40, count 0 2006.257.09:11:02.89#ibcon#wrote, iclass 40, count 0 2006.257.09:11:02.89#ibcon#about to read 3, iclass 40, count 0 2006.257.09:11:02.92#ibcon#read 3, iclass 40, count 0 2006.257.09:11:02.92#ibcon#about to read 4, iclass 40, count 0 2006.257.09:11:02.92#ibcon#read 4, iclass 40, count 0 2006.257.09:11:02.92#ibcon#about to read 5, iclass 40, count 0 2006.257.09:11:02.92#ibcon#read 5, iclass 40, count 0 2006.257.09:11:02.92#ibcon#about to read 6, iclass 40, count 0 2006.257.09:11:02.92#ibcon#read 6, iclass 40, count 0 2006.257.09:11:02.92#ibcon#end of sib2, iclass 40, count 0 2006.257.09:11:02.92#ibcon#*after write, iclass 40, count 0 2006.257.09:11:02.92#ibcon#*before return 0, iclass 40, count 0 2006.257.09:11:02.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:11:02.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:11:02.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:11:02.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:11:02.92$vck44/vblo=1,629.99 2006.257.09:11:02.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.09:11:02.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.09:11:02.92#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:02.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:02.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:02.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:02.92#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:11:02.92#ibcon#first serial, iclass 4, count 0 2006.257.09:11:02.92#ibcon#enter sib2, iclass 4, count 0 2006.257.09:11:02.92#ibcon#flushed, iclass 4, count 0 2006.257.09:11:02.92#ibcon#about to write, iclass 4, count 0 2006.257.09:11:02.92#ibcon#wrote, iclass 4, count 0 2006.257.09:11:02.92#ibcon#about to read 3, iclass 4, count 0 2006.257.09:11:02.94#ibcon#read 3, iclass 4, count 0 2006.257.09:11:02.94#ibcon#about to read 4, iclass 4, count 0 2006.257.09:11:02.94#ibcon#read 4, iclass 4, count 0 2006.257.09:11:02.94#ibcon#about to read 5, iclass 4, count 0 2006.257.09:11:02.94#ibcon#read 5, iclass 4, count 0 2006.257.09:11:02.94#ibcon#about to read 6, iclass 4, count 0 2006.257.09:11:02.94#ibcon#read 6, iclass 4, count 0 2006.257.09:11:02.94#ibcon#end of sib2, iclass 4, count 0 2006.257.09:11:02.94#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:11:02.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:11:02.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:11:02.94#ibcon#*before write, iclass 4, count 0 2006.257.09:11:02.94#ibcon#enter sib2, iclass 4, count 0 2006.257.09:11:02.94#ibcon#flushed, iclass 4, count 0 2006.257.09:11:02.94#ibcon#about to write, iclass 4, count 0 2006.257.09:11:02.94#ibcon#wrote, iclass 4, count 0 2006.257.09:11:02.94#ibcon#about to read 3, iclass 4, count 0 2006.257.09:11:02.98#ibcon#read 3, iclass 4, count 0 2006.257.09:11:02.98#ibcon#about to read 4, iclass 4, count 0 2006.257.09:11:02.98#ibcon#read 4, iclass 4, count 0 2006.257.09:11:02.98#ibcon#about to read 5, iclass 4, count 0 2006.257.09:11:02.98#ibcon#read 5, iclass 4, count 0 2006.257.09:11:02.98#ibcon#about to read 6, iclass 4, count 0 2006.257.09:11:02.98#ibcon#read 6, iclass 4, count 0 2006.257.09:11:02.98#ibcon#end of sib2, iclass 4, count 0 2006.257.09:11:02.98#ibcon#*after write, iclass 4, count 0 2006.257.09:11:02.98#ibcon#*before return 0, iclass 4, count 0 2006.257.09:11:02.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:02.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:11:02.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:11:02.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:11:02.98$vck44/vb=1,4 2006.257.09:11:02.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.09:11:02.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.09:11:02.98#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:02.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:02.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:02.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:02.98#ibcon#enter wrdev, iclass 6, count 2 2006.257.09:11:02.98#ibcon#first serial, iclass 6, count 2 2006.257.09:11:02.98#ibcon#enter sib2, iclass 6, count 2 2006.257.09:11:02.98#ibcon#flushed, iclass 6, count 2 2006.257.09:11:02.98#ibcon#about to write, iclass 6, count 2 2006.257.09:11:02.98#ibcon#wrote, iclass 6, count 2 2006.257.09:11:02.98#ibcon#about to read 3, iclass 6, count 2 2006.257.09:11:03.00#ibcon#read 3, iclass 6, count 2 2006.257.09:11:03.00#ibcon#about to read 4, iclass 6, count 2 2006.257.09:11:03.00#ibcon#read 4, iclass 6, count 2 2006.257.09:11:03.00#ibcon#about to read 5, iclass 6, count 2 2006.257.09:11:03.00#ibcon#read 5, iclass 6, count 2 2006.257.09:11:03.00#ibcon#about to read 6, iclass 6, count 2 2006.257.09:11:03.00#ibcon#read 6, iclass 6, count 2 2006.257.09:11:03.00#ibcon#end of sib2, iclass 6, count 2 2006.257.09:11:03.00#ibcon#*mode == 0, iclass 6, count 2 2006.257.09:11:03.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.09:11:03.00#ibcon#[27=AT01-04\r\n] 2006.257.09:11:03.00#ibcon#*before write, iclass 6, count 2 2006.257.09:11:03.00#ibcon#enter sib2, iclass 6, count 2 2006.257.09:11:03.00#ibcon#flushed, iclass 6, count 2 2006.257.09:11:03.00#ibcon#about to write, iclass 6, count 2 2006.257.09:11:03.00#ibcon#wrote, iclass 6, count 2 2006.257.09:11:03.00#ibcon#about to read 3, iclass 6, count 2 2006.257.09:11:03.03#ibcon#read 3, iclass 6, count 2 2006.257.09:11:03.03#ibcon#about to read 4, iclass 6, count 2 2006.257.09:11:03.03#ibcon#read 4, iclass 6, count 2 2006.257.09:11:03.03#ibcon#about to read 5, iclass 6, count 2 2006.257.09:11:03.03#ibcon#read 5, iclass 6, count 2 2006.257.09:11:03.03#ibcon#about to read 6, iclass 6, count 2 2006.257.09:11:03.03#ibcon#read 6, iclass 6, count 2 2006.257.09:11:03.03#ibcon#end of sib2, iclass 6, count 2 2006.257.09:11:03.03#ibcon#*after write, iclass 6, count 2 2006.257.09:11:03.03#ibcon#*before return 0, iclass 6, count 2 2006.257.09:11:03.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:03.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:11:03.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.09:11:03.03#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:03.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:03.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:03.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:03.15#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:11:03.15#ibcon#first serial, iclass 6, count 0 2006.257.09:11:03.15#ibcon#enter sib2, iclass 6, count 0 2006.257.09:11:03.15#ibcon#flushed, iclass 6, count 0 2006.257.09:11:03.15#ibcon#about to write, iclass 6, count 0 2006.257.09:11:03.15#ibcon#wrote, iclass 6, count 0 2006.257.09:11:03.15#ibcon#about to read 3, iclass 6, count 0 2006.257.09:11:03.17#ibcon#read 3, iclass 6, count 0 2006.257.09:11:03.17#ibcon#about to read 4, iclass 6, count 0 2006.257.09:11:03.17#ibcon#read 4, iclass 6, count 0 2006.257.09:11:03.17#ibcon#about to read 5, iclass 6, count 0 2006.257.09:11:03.17#ibcon#read 5, iclass 6, count 0 2006.257.09:11:03.17#ibcon#about to read 6, iclass 6, count 0 2006.257.09:11:03.17#ibcon#read 6, iclass 6, count 0 2006.257.09:11:03.17#ibcon#end of sib2, iclass 6, count 0 2006.257.09:11:03.17#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:11:03.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:11:03.17#ibcon#[27=USB\r\n] 2006.257.09:11:03.17#ibcon#*before write, iclass 6, count 0 2006.257.09:11:03.17#ibcon#enter sib2, iclass 6, count 0 2006.257.09:11:03.17#ibcon#flushed, iclass 6, count 0 2006.257.09:11:03.17#ibcon#about to write, iclass 6, count 0 2006.257.09:11:03.17#ibcon#wrote, iclass 6, count 0 2006.257.09:11:03.17#ibcon#about to read 3, iclass 6, count 0 2006.257.09:11:03.20#ibcon#read 3, iclass 6, count 0 2006.257.09:11:03.20#ibcon#about to read 4, iclass 6, count 0 2006.257.09:11:03.20#ibcon#read 4, iclass 6, count 0 2006.257.09:11:03.20#ibcon#about to read 5, iclass 6, count 0 2006.257.09:11:03.20#ibcon#read 5, iclass 6, count 0 2006.257.09:11:03.20#ibcon#about to read 6, iclass 6, count 0 2006.257.09:11:03.20#ibcon#read 6, iclass 6, count 0 2006.257.09:11:03.20#ibcon#end of sib2, iclass 6, count 0 2006.257.09:11:03.20#ibcon#*after write, iclass 6, count 0 2006.257.09:11:03.20#ibcon#*before return 0, iclass 6, count 0 2006.257.09:11:03.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:03.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:11:03.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:11:03.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:11:03.20$vck44/vblo=2,634.99 2006.257.09:11:03.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.09:11:03.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.09:11:03.20#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:03.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:03.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:03.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:03.20#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:11:03.20#ibcon#first serial, iclass 10, count 0 2006.257.09:11:03.20#ibcon#enter sib2, iclass 10, count 0 2006.257.09:11:03.20#ibcon#flushed, iclass 10, count 0 2006.257.09:11:03.20#ibcon#about to write, iclass 10, count 0 2006.257.09:11:03.20#ibcon#wrote, iclass 10, count 0 2006.257.09:11:03.20#ibcon#about to read 3, iclass 10, count 0 2006.257.09:11:03.22#ibcon#read 3, iclass 10, count 0 2006.257.09:11:03.22#ibcon#about to read 4, iclass 10, count 0 2006.257.09:11:03.22#ibcon#read 4, iclass 10, count 0 2006.257.09:11:03.22#ibcon#about to read 5, iclass 10, count 0 2006.257.09:11:03.22#ibcon#read 5, iclass 10, count 0 2006.257.09:11:03.22#ibcon#about to read 6, iclass 10, count 0 2006.257.09:11:03.22#ibcon#read 6, iclass 10, count 0 2006.257.09:11:03.22#ibcon#end of sib2, iclass 10, count 0 2006.257.09:11:03.22#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:11:03.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:11:03.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:11:03.22#ibcon#*before write, iclass 10, count 0 2006.257.09:11:03.22#ibcon#enter sib2, iclass 10, count 0 2006.257.09:11:03.22#ibcon#flushed, iclass 10, count 0 2006.257.09:11:03.22#ibcon#about to write, iclass 10, count 0 2006.257.09:11:03.22#ibcon#wrote, iclass 10, count 0 2006.257.09:11:03.22#ibcon#about to read 3, iclass 10, count 0 2006.257.09:11:03.26#ibcon#read 3, iclass 10, count 0 2006.257.09:11:03.26#ibcon#about to read 4, iclass 10, count 0 2006.257.09:11:03.26#ibcon#read 4, iclass 10, count 0 2006.257.09:11:03.26#ibcon#about to read 5, iclass 10, count 0 2006.257.09:11:03.26#ibcon#read 5, iclass 10, count 0 2006.257.09:11:03.26#ibcon#about to read 6, iclass 10, count 0 2006.257.09:11:03.26#ibcon#read 6, iclass 10, count 0 2006.257.09:11:03.26#ibcon#end of sib2, iclass 10, count 0 2006.257.09:11:03.26#ibcon#*after write, iclass 10, count 0 2006.257.09:11:03.26#ibcon#*before return 0, iclass 10, count 0 2006.257.09:11:03.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:03.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:11:03.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:11:03.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:11:03.26$vck44/vb=2,5 2006.257.09:11:03.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.09:11:03.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.09:11:03.26#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:03.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:11:03.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:11:03.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:11:03.32#ibcon#enter wrdev, iclass 12, count 2 2006.257.09:11:03.32#ibcon#first serial, iclass 12, count 2 2006.257.09:11:03.32#ibcon#enter sib2, iclass 12, count 2 2006.257.09:11:03.32#ibcon#flushed, iclass 12, count 2 2006.257.09:11:03.32#ibcon#about to write, iclass 12, count 2 2006.257.09:11:03.32#ibcon#wrote, iclass 12, count 2 2006.257.09:11:03.32#ibcon#about to read 3, iclass 12, count 2 2006.257.09:11:03.34#ibcon#read 3, iclass 12, count 2 2006.257.09:11:03.34#ibcon#about to read 4, iclass 12, count 2 2006.257.09:11:03.34#ibcon#read 4, iclass 12, count 2 2006.257.09:11:03.34#ibcon#about to read 5, iclass 12, count 2 2006.257.09:11:03.34#ibcon#read 5, iclass 12, count 2 2006.257.09:11:03.34#ibcon#about to read 6, iclass 12, count 2 2006.257.09:11:03.34#ibcon#read 6, iclass 12, count 2 2006.257.09:11:03.34#ibcon#end of sib2, iclass 12, count 2 2006.257.09:11:03.34#ibcon#*mode == 0, iclass 12, count 2 2006.257.09:11:03.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.09:11:03.34#ibcon#[27=AT02-05\r\n] 2006.257.09:11:03.34#ibcon#*before write, iclass 12, count 2 2006.257.09:11:03.34#ibcon#enter sib2, iclass 12, count 2 2006.257.09:11:03.34#ibcon#flushed, iclass 12, count 2 2006.257.09:11:03.34#ibcon#about to write, iclass 12, count 2 2006.257.09:11:03.34#ibcon#wrote, iclass 12, count 2 2006.257.09:11:03.34#ibcon#about to read 3, iclass 12, count 2 2006.257.09:11:03.37#ibcon#read 3, iclass 12, count 2 2006.257.09:11:03.37#ibcon#about to read 4, iclass 12, count 2 2006.257.09:11:03.37#ibcon#read 4, iclass 12, count 2 2006.257.09:11:03.37#ibcon#about to read 5, iclass 12, count 2 2006.257.09:11:03.37#ibcon#read 5, iclass 12, count 2 2006.257.09:11:03.37#ibcon#about to read 6, iclass 12, count 2 2006.257.09:11:03.37#ibcon#read 6, iclass 12, count 2 2006.257.09:11:03.37#ibcon#end of sib2, iclass 12, count 2 2006.257.09:11:03.37#ibcon#*after write, iclass 12, count 2 2006.257.09:11:03.37#ibcon#*before return 0, iclass 12, count 2 2006.257.09:11:03.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:11:03.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:11:03.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.09:11:03.37#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:03.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:11:03.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:11:03.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:11:03.49#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:11:03.49#ibcon#first serial, iclass 12, count 0 2006.257.09:11:03.49#ibcon#enter sib2, iclass 12, count 0 2006.257.09:11:03.49#ibcon#flushed, iclass 12, count 0 2006.257.09:11:03.49#ibcon#about to write, iclass 12, count 0 2006.257.09:11:03.49#ibcon#wrote, iclass 12, count 0 2006.257.09:11:03.49#ibcon#about to read 3, iclass 12, count 0 2006.257.09:11:03.51#ibcon#read 3, iclass 12, count 0 2006.257.09:11:03.51#ibcon#about to read 4, iclass 12, count 0 2006.257.09:11:03.51#ibcon#read 4, iclass 12, count 0 2006.257.09:11:03.51#ibcon#about to read 5, iclass 12, count 0 2006.257.09:11:03.51#ibcon#read 5, iclass 12, count 0 2006.257.09:11:03.51#ibcon#about to read 6, iclass 12, count 0 2006.257.09:11:03.51#ibcon#read 6, iclass 12, count 0 2006.257.09:11:03.51#ibcon#end of sib2, iclass 12, count 0 2006.257.09:11:03.51#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:11:03.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:11:03.51#ibcon#[27=USB\r\n] 2006.257.09:11:03.51#ibcon#*before write, iclass 12, count 0 2006.257.09:11:03.51#ibcon#enter sib2, iclass 12, count 0 2006.257.09:11:03.51#ibcon#flushed, iclass 12, count 0 2006.257.09:11:03.51#ibcon#about to write, iclass 12, count 0 2006.257.09:11:03.51#ibcon#wrote, iclass 12, count 0 2006.257.09:11:03.51#ibcon#about to read 3, iclass 12, count 0 2006.257.09:11:03.54#ibcon#read 3, iclass 12, count 0 2006.257.09:11:03.54#ibcon#about to read 4, iclass 12, count 0 2006.257.09:11:03.54#ibcon#read 4, iclass 12, count 0 2006.257.09:11:03.54#ibcon#about to read 5, iclass 12, count 0 2006.257.09:11:03.54#ibcon#read 5, iclass 12, count 0 2006.257.09:11:03.54#ibcon#about to read 6, iclass 12, count 0 2006.257.09:11:03.54#ibcon#read 6, iclass 12, count 0 2006.257.09:11:03.54#ibcon#end of sib2, iclass 12, count 0 2006.257.09:11:03.54#ibcon#*after write, iclass 12, count 0 2006.257.09:11:03.54#ibcon#*before return 0, iclass 12, count 0 2006.257.09:11:03.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:11:03.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:11:03.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:11:03.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:11:03.54$vck44/vblo=3,649.99 2006.257.09:11:03.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.09:11:03.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.09:11:03.54#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:03.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:11:03.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:11:03.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:11:03.54#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:11:03.54#ibcon#first serial, iclass 14, count 0 2006.257.09:11:03.54#ibcon#enter sib2, iclass 14, count 0 2006.257.09:11:03.54#ibcon#flushed, iclass 14, count 0 2006.257.09:11:03.54#ibcon#about to write, iclass 14, count 0 2006.257.09:11:03.54#ibcon#wrote, iclass 14, count 0 2006.257.09:11:03.54#ibcon#about to read 3, iclass 14, count 0 2006.257.09:11:03.56#ibcon#read 3, iclass 14, count 0 2006.257.09:11:03.56#ibcon#about to read 4, iclass 14, count 0 2006.257.09:11:03.56#ibcon#read 4, iclass 14, count 0 2006.257.09:11:03.56#ibcon#about to read 5, iclass 14, count 0 2006.257.09:11:03.56#ibcon#read 5, iclass 14, count 0 2006.257.09:11:03.56#ibcon#about to read 6, iclass 14, count 0 2006.257.09:11:03.56#ibcon#read 6, iclass 14, count 0 2006.257.09:11:03.56#ibcon#end of sib2, iclass 14, count 0 2006.257.09:11:03.56#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:11:03.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:11:03.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:11:03.56#ibcon#*before write, iclass 14, count 0 2006.257.09:11:03.56#ibcon#enter sib2, iclass 14, count 0 2006.257.09:11:03.56#ibcon#flushed, iclass 14, count 0 2006.257.09:11:03.56#ibcon#about to write, iclass 14, count 0 2006.257.09:11:03.56#ibcon#wrote, iclass 14, count 0 2006.257.09:11:03.56#ibcon#about to read 3, iclass 14, count 0 2006.257.09:11:03.60#ibcon#read 3, iclass 14, count 0 2006.257.09:11:03.60#ibcon#about to read 4, iclass 14, count 0 2006.257.09:11:03.60#ibcon#read 4, iclass 14, count 0 2006.257.09:11:03.60#ibcon#about to read 5, iclass 14, count 0 2006.257.09:11:03.60#ibcon#read 5, iclass 14, count 0 2006.257.09:11:03.60#ibcon#about to read 6, iclass 14, count 0 2006.257.09:11:03.60#ibcon#read 6, iclass 14, count 0 2006.257.09:11:03.60#ibcon#end of sib2, iclass 14, count 0 2006.257.09:11:03.60#ibcon#*after write, iclass 14, count 0 2006.257.09:11:03.60#ibcon#*before return 0, iclass 14, count 0 2006.257.09:11:03.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:11:03.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:11:03.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:11:03.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:11:03.60$vck44/vb=3,4 2006.257.09:11:03.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.09:11:03.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.09:11:03.60#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:03.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:11:03.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:11:03.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:11:03.66#ibcon#enter wrdev, iclass 16, count 2 2006.257.09:11:03.66#ibcon#first serial, iclass 16, count 2 2006.257.09:11:03.66#ibcon#enter sib2, iclass 16, count 2 2006.257.09:11:03.66#ibcon#flushed, iclass 16, count 2 2006.257.09:11:03.66#ibcon#about to write, iclass 16, count 2 2006.257.09:11:03.66#ibcon#wrote, iclass 16, count 2 2006.257.09:11:03.66#ibcon#about to read 3, iclass 16, count 2 2006.257.09:11:03.68#ibcon#read 3, iclass 16, count 2 2006.257.09:11:03.68#ibcon#about to read 4, iclass 16, count 2 2006.257.09:11:03.68#ibcon#read 4, iclass 16, count 2 2006.257.09:11:03.68#ibcon#about to read 5, iclass 16, count 2 2006.257.09:11:03.68#ibcon#read 5, iclass 16, count 2 2006.257.09:11:03.68#ibcon#about to read 6, iclass 16, count 2 2006.257.09:11:03.68#ibcon#read 6, iclass 16, count 2 2006.257.09:11:03.68#ibcon#end of sib2, iclass 16, count 2 2006.257.09:11:03.68#ibcon#*mode == 0, iclass 16, count 2 2006.257.09:11:03.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.09:11:03.68#ibcon#[27=AT03-04\r\n] 2006.257.09:11:03.68#ibcon#*before write, iclass 16, count 2 2006.257.09:11:03.68#ibcon#enter sib2, iclass 16, count 2 2006.257.09:11:03.68#ibcon#flushed, iclass 16, count 2 2006.257.09:11:03.68#ibcon#about to write, iclass 16, count 2 2006.257.09:11:03.68#ibcon#wrote, iclass 16, count 2 2006.257.09:11:03.68#ibcon#about to read 3, iclass 16, count 2 2006.257.09:11:03.71#ibcon#read 3, iclass 16, count 2 2006.257.09:11:03.71#ibcon#about to read 4, iclass 16, count 2 2006.257.09:11:03.71#ibcon#read 4, iclass 16, count 2 2006.257.09:11:03.71#ibcon#about to read 5, iclass 16, count 2 2006.257.09:11:03.71#ibcon#read 5, iclass 16, count 2 2006.257.09:11:03.71#ibcon#about to read 6, iclass 16, count 2 2006.257.09:11:03.71#ibcon#read 6, iclass 16, count 2 2006.257.09:11:03.71#ibcon#end of sib2, iclass 16, count 2 2006.257.09:11:03.71#ibcon#*after write, iclass 16, count 2 2006.257.09:11:03.71#ibcon#*before return 0, iclass 16, count 2 2006.257.09:11:03.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:11:03.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:11:03.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.09:11:03.71#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:03.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:11:03.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:11:03.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:11:03.83#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:11:03.83#ibcon#first serial, iclass 16, count 0 2006.257.09:11:03.83#ibcon#enter sib2, iclass 16, count 0 2006.257.09:11:03.83#ibcon#flushed, iclass 16, count 0 2006.257.09:11:03.83#ibcon#about to write, iclass 16, count 0 2006.257.09:11:03.83#ibcon#wrote, iclass 16, count 0 2006.257.09:11:03.83#ibcon#about to read 3, iclass 16, count 0 2006.257.09:11:03.85#ibcon#read 3, iclass 16, count 0 2006.257.09:11:03.85#ibcon#about to read 4, iclass 16, count 0 2006.257.09:11:03.85#ibcon#read 4, iclass 16, count 0 2006.257.09:11:03.85#ibcon#about to read 5, iclass 16, count 0 2006.257.09:11:03.85#ibcon#read 5, iclass 16, count 0 2006.257.09:11:03.85#ibcon#about to read 6, iclass 16, count 0 2006.257.09:11:03.85#ibcon#read 6, iclass 16, count 0 2006.257.09:11:03.85#ibcon#end of sib2, iclass 16, count 0 2006.257.09:11:03.85#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:11:03.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:11:03.85#ibcon#[27=USB\r\n] 2006.257.09:11:03.85#ibcon#*before write, iclass 16, count 0 2006.257.09:11:03.85#ibcon#enter sib2, iclass 16, count 0 2006.257.09:11:03.85#ibcon#flushed, iclass 16, count 0 2006.257.09:11:03.85#ibcon#about to write, iclass 16, count 0 2006.257.09:11:03.85#ibcon#wrote, iclass 16, count 0 2006.257.09:11:03.85#ibcon#about to read 3, iclass 16, count 0 2006.257.09:11:03.88#ibcon#read 3, iclass 16, count 0 2006.257.09:11:03.88#ibcon#about to read 4, iclass 16, count 0 2006.257.09:11:03.88#ibcon#read 4, iclass 16, count 0 2006.257.09:11:03.88#ibcon#about to read 5, iclass 16, count 0 2006.257.09:11:03.88#ibcon#read 5, iclass 16, count 0 2006.257.09:11:03.88#ibcon#about to read 6, iclass 16, count 0 2006.257.09:11:03.88#ibcon#read 6, iclass 16, count 0 2006.257.09:11:03.88#ibcon#end of sib2, iclass 16, count 0 2006.257.09:11:03.88#ibcon#*after write, iclass 16, count 0 2006.257.09:11:03.88#ibcon#*before return 0, iclass 16, count 0 2006.257.09:11:03.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:11:03.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:11:03.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:11:03.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:11:03.88$vck44/vblo=4,679.99 2006.257.09:11:03.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.09:11:03.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.09:11:03.88#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:03.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:03.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:03.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:03.88#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:11:03.88#ibcon#first serial, iclass 18, count 0 2006.257.09:11:03.88#ibcon#enter sib2, iclass 18, count 0 2006.257.09:11:03.88#ibcon#flushed, iclass 18, count 0 2006.257.09:11:03.88#ibcon#about to write, iclass 18, count 0 2006.257.09:11:03.88#ibcon#wrote, iclass 18, count 0 2006.257.09:11:03.88#ibcon#about to read 3, iclass 18, count 0 2006.257.09:11:03.90#ibcon#read 3, iclass 18, count 0 2006.257.09:11:03.90#ibcon#about to read 4, iclass 18, count 0 2006.257.09:11:03.90#ibcon#read 4, iclass 18, count 0 2006.257.09:11:03.90#ibcon#about to read 5, iclass 18, count 0 2006.257.09:11:03.90#ibcon#read 5, iclass 18, count 0 2006.257.09:11:03.90#ibcon#about to read 6, iclass 18, count 0 2006.257.09:11:03.90#ibcon#read 6, iclass 18, count 0 2006.257.09:11:03.90#ibcon#end of sib2, iclass 18, count 0 2006.257.09:11:03.90#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:11:03.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:11:03.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:11:03.90#ibcon#*before write, iclass 18, count 0 2006.257.09:11:03.90#ibcon#enter sib2, iclass 18, count 0 2006.257.09:11:03.90#ibcon#flushed, iclass 18, count 0 2006.257.09:11:03.90#ibcon#about to write, iclass 18, count 0 2006.257.09:11:03.90#ibcon#wrote, iclass 18, count 0 2006.257.09:11:03.90#ibcon#about to read 3, iclass 18, count 0 2006.257.09:11:03.94#ibcon#read 3, iclass 18, count 0 2006.257.09:11:03.94#ibcon#about to read 4, iclass 18, count 0 2006.257.09:11:03.94#ibcon#read 4, iclass 18, count 0 2006.257.09:11:03.94#ibcon#about to read 5, iclass 18, count 0 2006.257.09:11:03.94#ibcon#read 5, iclass 18, count 0 2006.257.09:11:03.94#ibcon#about to read 6, iclass 18, count 0 2006.257.09:11:03.94#ibcon#read 6, iclass 18, count 0 2006.257.09:11:03.94#ibcon#end of sib2, iclass 18, count 0 2006.257.09:11:03.94#ibcon#*after write, iclass 18, count 0 2006.257.09:11:03.94#ibcon#*before return 0, iclass 18, count 0 2006.257.09:11:03.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:03.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:11:03.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:11:03.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:11:03.94$vck44/vb=4,5 2006.257.09:11:03.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.09:11:03.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.09:11:03.94#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:03.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:04.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:04.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:04.00#ibcon#enter wrdev, iclass 20, count 2 2006.257.09:11:04.00#ibcon#first serial, iclass 20, count 2 2006.257.09:11:04.00#ibcon#enter sib2, iclass 20, count 2 2006.257.09:11:04.00#ibcon#flushed, iclass 20, count 2 2006.257.09:11:04.00#ibcon#about to write, iclass 20, count 2 2006.257.09:11:04.00#ibcon#wrote, iclass 20, count 2 2006.257.09:11:04.00#ibcon#about to read 3, iclass 20, count 2 2006.257.09:11:04.02#ibcon#read 3, iclass 20, count 2 2006.257.09:11:04.02#ibcon#about to read 4, iclass 20, count 2 2006.257.09:11:04.02#ibcon#read 4, iclass 20, count 2 2006.257.09:11:04.02#ibcon#about to read 5, iclass 20, count 2 2006.257.09:11:04.02#ibcon#read 5, iclass 20, count 2 2006.257.09:11:04.02#ibcon#about to read 6, iclass 20, count 2 2006.257.09:11:04.02#ibcon#read 6, iclass 20, count 2 2006.257.09:11:04.02#ibcon#end of sib2, iclass 20, count 2 2006.257.09:11:04.02#ibcon#*mode == 0, iclass 20, count 2 2006.257.09:11:04.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.09:11:04.02#ibcon#[27=AT04-05\r\n] 2006.257.09:11:04.02#ibcon#*before write, iclass 20, count 2 2006.257.09:11:04.02#ibcon#enter sib2, iclass 20, count 2 2006.257.09:11:04.02#ibcon#flushed, iclass 20, count 2 2006.257.09:11:04.02#ibcon#about to write, iclass 20, count 2 2006.257.09:11:04.02#ibcon#wrote, iclass 20, count 2 2006.257.09:11:04.02#ibcon#about to read 3, iclass 20, count 2 2006.257.09:11:04.05#ibcon#read 3, iclass 20, count 2 2006.257.09:11:04.05#ibcon#about to read 4, iclass 20, count 2 2006.257.09:11:04.05#ibcon#read 4, iclass 20, count 2 2006.257.09:11:04.05#ibcon#about to read 5, iclass 20, count 2 2006.257.09:11:04.05#ibcon#read 5, iclass 20, count 2 2006.257.09:11:04.05#ibcon#about to read 6, iclass 20, count 2 2006.257.09:11:04.05#ibcon#read 6, iclass 20, count 2 2006.257.09:11:04.05#ibcon#end of sib2, iclass 20, count 2 2006.257.09:11:04.05#ibcon#*after write, iclass 20, count 2 2006.257.09:11:04.05#ibcon#*before return 0, iclass 20, count 2 2006.257.09:11:04.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:04.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:11:04.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.09:11:04.05#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:04.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:04.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:04.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:04.17#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:11:04.17#ibcon#first serial, iclass 20, count 0 2006.257.09:11:04.17#ibcon#enter sib2, iclass 20, count 0 2006.257.09:11:04.17#ibcon#flushed, iclass 20, count 0 2006.257.09:11:04.17#ibcon#about to write, iclass 20, count 0 2006.257.09:11:04.17#ibcon#wrote, iclass 20, count 0 2006.257.09:11:04.17#ibcon#about to read 3, iclass 20, count 0 2006.257.09:11:04.19#ibcon#read 3, iclass 20, count 0 2006.257.09:11:04.19#ibcon#about to read 4, iclass 20, count 0 2006.257.09:11:04.19#ibcon#read 4, iclass 20, count 0 2006.257.09:11:04.19#ibcon#about to read 5, iclass 20, count 0 2006.257.09:11:04.19#ibcon#read 5, iclass 20, count 0 2006.257.09:11:04.19#ibcon#about to read 6, iclass 20, count 0 2006.257.09:11:04.19#ibcon#read 6, iclass 20, count 0 2006.257.09:11:04.19#ibcon#end of sib2, iclass 20, count 0 2006.257.09:11:04.19#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:11:04.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:11:04.19#ibcon#[27=USB\r\n] 2006.257.09:11:04.19#ibcon#*before write, iclass 20, count 0 2006.257.09:11:04.19#ibcon#enter sib2, iclass 20, count 0 2006.257.09:11:04.19#ibcon#flushed, iclass 20, count 0 2006.257.09:11:04.19#ibcon#about to write, iclass 20, count 0 2006.257.09:11:04.19#ibcon#wrote, iclass 20, count 0 2006.257.09:11:04.19#ibcon#about to read 3, iclass 20, count 0 2006.257.09:11:04.22#ibcon#read 3, iclass 20, count 0 2006.257.09:11:04.22#ibcon#about to read 4, iclass 20, count 0 2006.257.09:11:04.22#ibcon#read 4, iclass 20, count 0 2006.257.09:11:04.22#ibcon#about to read 5, iclass 20, count 0 2006.257.09:11:04.22#ibcon#read 5, iclass 20, count 0 2006.257.09:11:04.22#ibcon#about to read 6, iclass 20, count 0 2006.257.09:11:04.22#ibcon#read 6, iclass 20, count 0 2006.257.09:11:04.22#ibcon#end of sib2, iclass 20, count 0 2006.257.09:11:04.22#ibcon#*after write, iclass 20, count 0 2006.257.09:11:04.22#ibcon#*before return 0, iclass 20, count 0 2006.257.09:11:04.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:04.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:11:04.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:11:04.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:11:04.22$vck44/vblo=5,709.99 2006.257.09:11:04.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.09:11:04.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.09:11:04.22#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:04.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:04.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:04.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:04.22#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:11:04.22#ibcon#first serial, iclass 22, count 0 2006.257.09:11:04.22#ibcon#enter sib2, iclass 22, count 0 2006.257.09:11:04.22#ibcon#flushed, iclass 22, count 0 2006.257.09:11:04.22#ibcon#about to write, iclass 22, count 0 2006.257.09:11:04.22#ibcon#wrote, iclass 22, count 0 2006.257.09:11:04.22#ibcon#about to read 3, iclass 22, count 0 2006.257.09:11:04.24#ibcon#read 3, iclass 22, count 0 2006.257.09:11:04.24#ibcon#about to read 4, iclass 22, count 0 2006.257.09:11:04.24#ibcon#read 4, iclass 22, count 0 2006.257.09:11:04.24#ibcon#about to read 5, iclass 22, count 0 2006.257.09:11:04.24#ibcon#read 5, iclass 22, count 0 2006.257.09:11:04.24#ibcon#about to read 6, iclass 22, count 0 2006.257.09:11:04.24#ibcon#read 6, iclass 22, count 0 2006.257.09:11:04.24#ibcon#end of sib2, iclass 22, count 0 2006.257.09:11:04.24#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:11:04.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:11:04.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:11:04.24#ibcon#*before write, iclass 22, count 0 2006.257.09:11:04.24#ibcon#enter sib2, iclass 22, count 0 2006.257.09:11:04.24#ibcon#flushed, iclass 22, count 0 2006.257.09:11:04.24#ibcon#about to write, iclass 22, count 0 2006.257.09:11:04.24#ibcon#wrote, iclass 22, count 0 2006.257.09:11:04.24#ibcon#about to read 3, iclass 22, count 0 2006.257.09:11:04.28#ibcon#read 3, iclass 22, count 0 2006.257.09:11:04.28#ibcon#about to read 4, iclass 22, count 0 2006.257.09:11:04.28#ibcon#read 4, iclass 22, count 0 2006.257.09:11:04.28#ibcon#about to read 5, iclass 22, count 0 2006.257.09:11:04.28#ibcon#read 5, iclass 22, count 0 2006.257.09:11:04.28#ibcon#about to read 6, iclass 22, count 0 2006.257.09:11:04.28#ibcon#read 6, iclass 22, count 0 2006.257.09:11:04.28#ibcon#end of sib2, iclass 22, count 0 2006.257.09:11:04.28#ibcon#*after write, iclass 22, count 0 2006.257.09:11:04.28#ibcon#*before return 0, iclass 22, count 0 2006.257.09:11:04.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:04.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:11:04.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:11:04.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:11:04.28$vck44/vb=5,4 2006.257.09:11:04.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.09:11:04.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.09:11:04.28#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:04.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:04.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:04.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:04.34#ibcon#enter wrdev, iclass 24, count 2 2006.257.09:11:04.34#ibcon#first serial, iclass 24, count 2 2006.257.09:11:04.34#ibcon#enter sib2, iclass 24, count 2 2006.257.09:11:04.34#ibcon#flushed, iclass 24, count 2 2006.257.09:11:04.34#ibcon#about to write, iclass 24, count 2 2006.257.09:11:04.34#ibcon#wrote, iclass 24, count 2 2006.257.09:11:04.34#ibcon#about to read 3, iclass 24, count 2 2006.257.09:11:04.36#ibcon#read 3, iclass 24, count 2 2006.257.09:11:04.36#ibcon#about to read 4, iclass 24, count 2 2006.257.09:11:04.36#ibcon#read 4, iclass 24, count 2 2006.257.09:11:04.36#ibcon#about to read 5, iclass 24, count 2 2006.257.09:11:04.36#ibcon#read 5, iclass 24, count 2 2006.257.09:11:04.36#ibcon#about to read 6, iclass 24, count 2 2006.257.09:11:04.36#ibcon#read 6, iclass 24, count 2 2006.257.09:11:04.36#ibcon#end of sib2, iclass 24, count 2 2006.257.09:11:04.36#ibcon#*mode == 0, iclass 24, count 2 2006.257.09:11:04.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.09:11:04.36#ibcon#[27=AT05-04\r\n] 2006.257.09:11:04.36#ibcon#*before write, iclass 24, count 2 2006.257.09:11:04.36#ibcon#enter sib2, iclass 24, count 2 2006.257.09:11:04.36#ibcon#flushed, iclass 24, count 2 2006.257.09:11:04.36#ibcon#about to write, iclass 24, count 2 2006.257.09:11:04.36#ibcon#wrote, iclass 24, count 2 2006.257.09:11:04.36#ibcon#about to read 3, iclass 24, count 2 2006.257.09:11:04.39#ibcon#read 3, iclass 24, count 2 2006.257.09:11:04.39#ibcon#about to read 4, iclass 24, count 2 2006.257.09:11:04.39#ibcon#read 4, iclass 24, count 2 2006.257.09:11:04.39#ibcon#about to read 5, iclass 24, count 2 2006.257.09:11:04.39#ibcon#read 5, iclass 24, count 2 2006.257.09:11:04.39#ibcon#about to read 6, iclass 24, count 2 2006.257.09:11:04.39#ibcon#read 6, iclass 24, count 2 2006.257.09:11:04.39#ibcon#end of sib2, iclass 24, count 2 2006.257.09:11:04.39#ibcon#*after write, iclass 24, count 2 2006.257.09:11:04.39#ibcon#*before return 0, iclass 24, count 2 2006.257.09:11:04.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:04.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:11:04.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.09:11:04.39#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:04.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:04.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:04.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:04.51#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:11:04.51#ibcon#first serial, iclass 24, count 0 2006.257.09:11:04.51#ibcon#enter sib2, iclass 24, count 0 2006.257.09:11:04.51#ibcon#flushed, iclass 24, count 0 2006.257.09:11:04.51#ibcon#about to write, iclass 24, count 0 2006.257.09:11:04.51#ibcon#wrote, iclass 24, count 0 2006.257.09:11:04.51#ibcon#about to read 3, iclass 24, count 0 2006.257.09:11:04.53#ibcon#read 3, iclass 24, count 0 2006.257.09:11:04.53#ibcon#about to read 4, iclass 24, count 0 2006.257.09:11:04.53#ibcon#read 4, iclass 24, count 0 2006.257.09:11:04.53#ibcon#about to read 5, iclass 24, count 0 2006.257.09:11:04.53#ibcon#read 5, iclass 24, count 0 2006.257.09:11:04.53#ibcon#about to read 6, iclass 24, count 0 2006.257.09:11:04.53#ibcon#read 6, iclass 24, count 0 2006.257.09:11:04.53#ibcon#end of sib2, iclass 24, count 0 2006.257.09:11:04.53#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:11:04.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:11:04.53#ibcon#[27=USB\r\n] 2006.257.09:11:04.53#ibcon#*before write, iclass 24, count 0 2006.257.09:11:04.53#ibcon#enter sib2, iclass 24, count 0 2006.257.09:11:04.53#ibcon#flushed, iclass 24, count 0 2006.257.09:11:04.53#ibcon#about to write, iclass 24, count 0 2006.257.09:11:04.53#ibcon#wrote, iclass 24, count 0 2006.257.09:11:04.53#ibcon#about to read 3, iclass 24, count 0 2006.257.09:11:04.56#ibcon#read 3, iclass 24, count 0 2006.257.09:11:04.56#ibcon#about to read 4, iclass 24, count 0 2006.257.09:11:04.56#ibcon#read 4, iclass 24, count 0 2006.257.09:11:04.56#ibcon#about to read 5, iclass 24, count 0 2006.257.09:11:04.56#ibcon#read 5, iclass 24, count 0 2006.257.09:11:04.56#ibcon#about to read 6, iclass 24, count 0 2006.257.09:11:04.56#ibcon#read 6, iclass 24, count 0 2006.257.09:11:04.56#ibcon#end of sib2, iclass 24, count 0 2006.257.09:11:04.56#ibcon#*after write, iclass 24, count 0 2006.257.09:11:04.56#ibcon#*before return 0, iclass 24, count 0 2006.257.09:11:04.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:04.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:11:04.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:11:04.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:11:04.56$vck44/vblo=6,719.99 2006.257.09:11:04.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.09:11:04.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.09:11:04.56#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:04.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:04.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:04.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:04.56#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:11:04.56#ibcon#first serial, iclass 26, count 0 2006.257.09:11:04.56#ibcon#enter sib2, iclass 26, count 0 2006.257.09:11:04.56#ibcon#flushed, iclass 26, count 0 2006.257.09:11:04.56#ibcon#about to write, iclass 26, count 0 2006.257.09:11:04.56#ibcon#wrote, iclass 26, count 0 2006.257.09:11:04.56#ibcon#about to read 3, iclass 26, count 0 2006.257.09:11:04.58#ibcon#read 3, iclass 26, count 0 2006.257.09:11:04.58#ibcon#about to read 4, iclass 26, count 0 2006.257.09:11:04.58#ibcon#read 4, iclass 26, count 0 2006.257.09:11:04.58#ibcon#about to read 5, iclass 26, count 0 2006.257.09:11:04.58#ibcon#read 5, iclass 26, count 0 2006.257.09:11:04.58#ibcon#about to read 6, iclass 26, count 0 2006.257.09:11:04.58#ibcon#read 6, iclass 26, count 0 2006.257.09:11:04.58#ibcon#end of sib2, iclass 26, count 0 2006.257.09:11:04.58#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:11:04.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:11:04.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:11:04.58#ibcon#*before write, iclass 26, count 0 2006.257.09:11:04.58#ibcon#enter sib2, iclass 26, count 0 2006.257.09:11:04.58#ibcon#flushed, iclass 26, count 0 2006.257.09:11:04.58#ibcon#about to write, iclass 26, count 0 2006.257.09:11:04.58#ibcon#wrote, iclass 26, count 0 2006.257.09:11:04.58#ibcon#about to read 3, iclass 26, count 0 2006.257.09:11:04.62#ibcon#read 3, iclass 26, count 0 2006.257.09:11:04.62#ibcon#about to read 4, iclass 26, count 0 2006.257.09:11:04.62#ibcon#read 4, iclass 26, count 0 2006.257.09:11:04.62#ibcon#about to read 5, iclass 26, count 0 2006.257.09:11:04.62#ibcon#read 5, iclass 26, count 0 2006.257.09:11:04.62#ibcon#about to read 6, iclass 26, count 0 2006.257.09:11:04.62#ibcon#read 6, iclass 26, count 0 2006.257.09:11:04.62#ibcon#end of sib2, iclass 26, count 0 2006.257.09:11:04.62#ibcon#*after write, iclass 26, count 0 2006.257.09:11:04.62#ibcon#*before return 0, iclass 26, count 0 2006.257.09:11:04.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:04.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:11:04.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:11:04.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:11:04.62$vck44/vb=6,4 2006.257.09:11:04.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.09:11:04.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.09:11:04.62#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:04.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:04.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:04.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:04.68#ibcon#enter wrdev, iclass 28, count 2 2006.257.09:11:04.68#ibcon#first serial, iclass 28, count 2 2006.257.09:11:04.68#ibcon#enter sib2, iclass 28, count 2 2006.257.09:11:04.68#ibcon#flushed, iclass 28, count 2 2006.257.09:11:04.68#ibcon#about to write, iclass 28, count 2 2006.257.09:11:04.68#ibcon#wrote, iclass 28, count 2 2006.257.09:11:04.68#ibcon#about to read 3, iclass 28, count 2 2006.257.09:11:04.70#ibcon#read 3, iclass 28, count 2 2006.257.09:11:04.70#ibcon#about to read 4, iclass 28, count 2 2006.257.09:11:04.70#ibcon#read 4, iclass 28, count 2 2006.257.09:11:04.70#ibcon#about to read 5, iclass 28, count 2 2006.257.09:11:04.70#ibcon#read 5, iclass 28, count 2 2006.257.09:11:04.70#ibcon#about to read 6, iclass 28, count 2 2006.257.09:11:04.70#ibcon#read 6, iclass 28, count 2 2006.257.09:11:04.70#ibcon#end of sib2, iclass 28, count 2 2006.257.09:11:04.70#ibcon#*mode == 0, iclass 28, count 2 2006.257.09:11:04.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.09:11:04.70#ibcon#[27=AT06-04\r\n] 2006.257.09:11:04.70#ibcon#*before write, iclass 28, count 2 2006.257.09:11:04.70#ibcon#enter sib2, iclass 28, count 2 2006.257.09:11:04.70#ibcon#flushed, iclass 28, count 2 2006.257.09:11:04.70#ibcon#about to write, iclass 28, count 2 2006.257.09:11:04.70#ibcon#wrote, iclass 28, count 2 2006.257.09:11:04.70#ibcon#about to read 3, iclass 28, count 2 2006.257.09:11:04.73#ibcon#read 3, iclass 28, count 2 2006.257.09:11:04.73#ibcon#about to read 4, iclass 28, count 2 2006.257.09:11:04.73#ibcon#read 4, iclass 28, count 2 2006.257.09:11:04.73#ibcon#about to read 5, iclass 28, count 2 2006.257.09:11:04.73#ibcon#read 5, iclass 28, count 2 2006.257.09:11:04.73#ibcon#about to read 6, iclass 28, count 2 2006.257.09:11:04.73#ibcon#read 6, iclass 28, count 2 2006.257.09:11:04.73#ibcon#end of sib2, iclass 28, count 2 2006.257.09:11:04.73#ibcon#*after write, iclass 28, count 2 2006.257.09:11:04.73#ibcon#*before return 0, iclass 28, count 2 2006.257.09:11:04.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:04.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:11:04.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.09:11:04.73#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:04.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:04.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:04.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:04.85#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:11:04.85#ibcon#first serial, iclass 28, count 0 2006.257.09:11:04.85#ibcon#enter sib2, iclass 28, count 0 2006.257.09:11:04.85#ibcon#flushed, iclass 28, count 0 2006.257.09:11:04.85#ibcon#about to write, iclass 28, count 0 2006.257.09:11:04.85#ibcon#wrote, iclass 28, count 0 2006.257.09:11:04.85#ibcon#about to read 3, iclass 28, count 0 2006.257.09:11:04.87#ibcon#read 3, iclass 28, count 0 2006.257.09:11:04.87#ibcon#about to read 4, iclass 28, count 0 2006.257.09:11:04.87#ibcon#read 4, iclass 28, count 0 2006.257.09:11:04.87#ibcon#about to read 5, iclass 28, count 0 2006.257.09:11:04.87#ibcon#read 5, iclass 28, count 0 2006.257.09:11:04.87#ibcon#about to read 6, iclass 28, count 0 2006.257.09:11:04.87#ibcon#read 6, iclass 28, count 0 2006.257.09:11:04.87#ibcon#end of sib2, iclass 28, count 0 2006.257.09:11:04.87#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:11:04.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:11:04.87#ibcon#[27=USB\r\n] 2006.257.09:11:04.87#ibcon#*before write, iclass 28, count 0 2006.257.09:11:04.87#ibcon#enter sib2, iclass 28, count 0 2006.257.09:11:04.87#ibcon#flushed, iclass 28, count 0 2006.257.09:11:04.87#ibcon#about to write, iclass 28, count 0 2006.257.09:11:04.87#ibcon#wrote, iclass 28, count 0 2006.257.09:11:04.87#ibcon#about to read 3, iclass 28, count 0 2006.257.09:11:04.90#ibcon#read 3, iclass 28, count 0 2006.257.09:11:04.90#ibcon#about to read 4, iclass 28, count 0 2006.257.09:11:04.90#ibcon#read 4, iclass 28, count 0 2006.257.09:11:04.90#ibcon#about to read 5, iclass 28, count 0 2006.257.09:11:04.90#ibcon#read 5, iclass 28, count 0 2006.257.09:11:04.90#ibcon#about to read 6, iclass 28, count 0 2006.257.09:11:04.90#ibcon#read 6, iclass 28, count 0 2006.257.09:11:04.90#ibcon#end of sib2, iclass 28, count 0 2006.257.09:11:04.90#ibcon#*after write, iclass 28, count 0 2006.257.09:11:04.90#ibcon#*before return 0, iclass 28, count 0 2006.257.09:11:04.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:04.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:11:04.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:11:04.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:11:04.90$vck44/vblo=7,734.99 2006.257.09:11:04.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.09:11:04.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.09:11:04.90#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:04.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:04.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:04.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:04.90#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:11:04.90#ibcon#first serial, iclass 30, count 0 2006.257.09:11:04.90#ibcon#enter sib2, iclass 30, count 0 2006.257.09:11:04.90#ibcon#flushed, iclass 30, count 0 2006.257.09:11:04.90#ibcon#about to write, iclass 30, count 0 2006.257.09:11:04.90#ibcon#wrote, iclass 30, count 0 2006.257.09:11:04.90#ibcon#about to read 3, iclass 30, count 0 2006.257.09:11:04.92#ibcon#read 3, iclass 30, count 0 2006.257.09:11:04.92#ibcon#about to read 4, iclass 30, count 0 2006.257.09:11:04.92#ibcon#read 4, iclass 30, count 0 2006.257.09:11:04.92#ibcon#about to read 5, iclass 30, count 0 2006.257.09:11:04.92#ibcon#read 5, iclass 30, count 0 2006.257.09:11:04.92#ibcon#about to read 6, iclass 30, count 0 2006.257.09:11:04.92#ibcon#read 6, iclass 30, count 0 2006.257.09:11:04.92#ibcon#end of sib2, iclass 30, count 0 2006.257.09:11:04.92#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:11:04.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:11:04.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:11:04.92#ibcon#*before write, iclass 30, count 0 2006.257.09:11:04.92#ibcon#enter sib2, iclass 30, count 0 2006.257.09:11:04.92#ibcon#flushed, iclass 30, count 0 2006.257.09:11:04.92#ibcon#about to write, iclass 30, count 0 2006.257.09:11:04.92#ibcon#wrote, iclass 30, count 0 2006.257.09:11:04.92#ibcon#about to read 3, iclass 30, count 0 2006.257.09:11:04.96#ibcon#read 3, iclass 30, count 0 2006.257.09:11:04.96#ibcon#about to read 4, iclass 30, count 0 2006.257.09:11:04.96#ibcon#read 4, iclass 30, count 0 2006.257.09:11:04.96#ibcon#about to read 5, iclass 30, count 0 2006.257.09:11:04.96#ibcon#read 5, iclass 30, count 0 2006.257.09:11:04.96#ibcon#about to read 6, iclass 30, count 0 2006.257.09:11:04.96#ibcon#read 6, iclass 30, count 0 2006.257.09:11:04.96#ibcon#end of sib2, iclass 30, count 0 2006.257.09:11:04.96#ibcon#*after write, iclass 30, count 0 2006.257.09:11:04.96#ibcon#*before return 0, iclass 30, count 0 2006.257.09:11:04.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:04.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:11:04.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:11:04.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:11:04.96$vck44/vb=7,4 2006.257.09:11:04.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.09:11:04.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.09:11:04.96#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:04.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:05.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:05.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:05.02#ibcon#enter wrdev, iclass 32, count 2 2006.257.09:11:05.02#ibcon#first serial, iclass 32, count 2 2006.257.09:11:05.02#ibcon#enter sib2, iclass 32, count 2 2006.257.09:11:05.02#ibcon#flushed, iclass 32, count 2 2006.257.09:11:05.02#ibcon#about to write, iclass 32, count 2 2006.257.09:11:05.02#ibcon#wrote, iclass 32, count 2 2006.257.09:11:05.02#ibcon#about to read 3, iclass 32, count 2 2006.257.09:11:05.04#ibcon#read 3, iclass 32, count 2 2006.257.09:11:05.04#ibcon#about to read 4, iclass 32, count 2 2006.257.09:11:05.04#ibcon#read 4, iclass 32, count 2 2006.257.09:11:05.04#ibcon#about to read 5, iclass 32, count 2 2006.257.09:11:05.04#ibcon#read 5, iclass 32, count 2 2006.257.09:11:05.04#ibcon#about to read 6, iclass 32, count 2 2006.257.09:11:05.04#ibcon#read 6, iclass 32, count 2 2006.257.09:11:05.04#ibcon#end of sib2, iclass 32, count 2 2006.257.09:11:05.04#ibcon#*mode == 0, iclass 32, count 2 2006.257.09:11:05.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.09:11:05.04#ibcon#[27=AT07-04\r\n] 2006.257.09:11:05.04#ibcon#*before write, iclass 32, count 2 2006.257.09:11:05.04#ibcon#enter sib2, iclass 32, count 2 2006.257.09:11:05.04#ibcon#flushed, iclass 32, count 2 2006.257.09:11:05.04#ibcon#about to write, iclass 32, count 2 2006.257.09:11:05.04#ibcon#wrote, iclass 32, count 2 2006.257.09:11:05.04#ibcon#about to read 3, iclass 32, count 2 2006.257.09:11:05.07#ibcon#read 3, iclass 32, count 2 2006.257.09:11:05.07#ibcon#about to read 4, iclass 32, count 2 2006.257.09:11:05.07#ibcon#read 4, iclass 32, count 2 2006.257.09:11:05.07#ibcon#about to read 5, iclass 32, count 2 2006.257.09:11:05.07#ibcon#read 5, iclass 32, count 2 2006.257.09:11:05.07#ibcon#about to read 6, iclass 32, count 2 2006.257.09:11:05.07#ibcon#read 6, iclass 32, count 2 2006.257.09:11:05.07#ibcon#end of sib2, iclass 32, count 2 2006.257.09:11:05.07#ibcon#*after write, iclass 32, count 2 2006.257.09:11:05.07#ibcon#*before return 0, iclass 32, count 2 2006.257.09:11:05.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:05.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:11:05.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.09:11:05.07#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:05.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:05.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:05.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:05.19#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:11:05.19#ibcon#first serial, iclass 32, count 0 2006.257.09:11:05.19#ibcon#enter sib2, iclass 32, count 0 2006.257.09:11:05.19#ibcon#flushed, iclass 32, count 0 2006.257.09:11:05.19#ibcon#about to write, iclass 32, count 0 2006.257.09:11:05.19#ibcon#wrote, iclass 32, count 0 2006.257.09:11:05.19#ibcon#about to read 3, iclass 32, count 0 2006.257.09:11:05.21#ibcon#read 3, iclass 32, count 0 2006.257.09:11:05.21#ibcon#about to read 4, iclass 32, count 0 2006.257.09:11:05.21#ibcon#read 4, iclass 32, count 0 2006.257.09:11:05.21#ibcon#about to read 5, iclass 32, count 0 2006.257.09:11:05.21#ibcon#read 5, iclass 32, count 0 2006.257.09:11:05.21#ibcon#about to read 6, iclass 32, count 0 2006.257.09:11:05.21#ibcon#read 6, iclass 32, count 0 2006.257.09:11:05.21#ibcon#end of sib2, iclass 32, count 0 2006.257.09:11:05.21#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:11:05.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:11:05.21#ibcon#[27=USB\r\n] 2006.257.09:11:05.21#ibcon#*before write, iclass 32, count 0 2006.257.09:11:05.21#ibcon#enter sib2, iclass 32, count 0 2006.257.09:11:05.21#ibcon#flushed, iclass 32, count 0 2006.257.09:11:05.21#ibcon#about to write, iclass 32, count 0 2006.257.09:11:05.21#ibcon#wrote, iclass 32, count 0 2006.257.09:11:05.21#ibcon#about to read 3, iclass 32, count 0 2006.257.09:11:05.24#ibcon#read 3, iclass 32, count 0 2006.257.09:11:05.24#ibcon#about to read 4, iclass 32, count 0 2006.257.09:11:05.24#ibcon#read 4, iclass 32, count 0 2006.257.09:11:05.24#ibcon#about to read 5, iclass 32, count 0 2006.257.09:11:05.24#ibcon#read 5, iclass 32, count 0 2006.257.09:11:05.24#ibcon#about to read 6, iclass 32, count 0 2006.257.09:11:05.24#ibcon#read 6, iclass 32, count 0 2006.257.09:11:05.24#ibcon#end of sib2, iclass 32, count 0 2006.257.09:11:05.24#ibcon#*after write, iclass 32, count 0 2006.257.09:11:05.24#ibcon#*before return 0, iclass 32, count 0 2006.257.09:11:05.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:05.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:11:05.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:11:05.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:11:05.24$vck44/vblo=8,744.99 2006.257.09:11:05.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.09:11:05.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.09:11:05.24#ibcon#ireg 17 cls_cnt 0 2006.257.09:11:05.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:05.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:05.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:05.24#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:11:05.24#ibcon#first serial, iclass 34, count 0 2006.257.09:11:05.24#ibcon#enter sib2, iclass 34, count 0 2006.257.09:11:05.24#ibcon#flushed, iclass 34, count 0 2006.257.09:11:05.24#ibcon#about to write, iclass 34, count 0 2006.257.09:11:05.24#ibcon#wrote, iclass 34, count 0 2006.257.09:11:05.24#ibcon#about to read 3, iclass 34, count 0 2006.257.09:11:05.26#ibcon#read 3, iclass 34, count 0 2006.257.09:11:05.26#ibcon#about to read 4, iclass 34, count 0 2006.257.09:11:05.26#ibcon#read 4, iclass 34, count 0 2006.257.09:11:05.26#ibcon#about to read 5, iclass 34, count 0 2006.257.09:11:05.26#ibcon#read 5, iclass 34, count 0 2006.257.09:11:05.26#ibcon#about to read 6, iclass 34, count 0 2006.257.09:11:05.26#ibcon#read 6, iclass 34, count 0 2006.257.09:11:05.26#ibcon#end of sib2, iclass 34, count 0 2006.257.09:11:05.26#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:11:05.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:11:05.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:11:05.26#ibcon#*before write, iclass 34, count 0 2006.257.09:11:05.26#ibcon#enter sib2, iclass 34, count 0 2006.257.09:11:05.26#ibcon#flushed, iclass 34, count 0 2006.257.09:11:05.26#ibcon#about to write, iclass 34, count 0 2006.257.09:11:05.26#ibcon#wrote, iclass 34, count 0 2006.257.09:11:05.26#ibcon#about to read 3, iclass 34, count 0 2006.257.09:11:05.30#ibcon#read 3, iclass 34, count 0 2006.257.09:11:05.30#ibcon#about to read 4, iclass 34, count 0 2006.257.09:11:05.30#ibcon#read 4, iclass 34, count 0 2006.257.09:11:05.30#ibcon#about to read 5, iclass 34, count 0 2006.257.09:11:05.30#ibcon#read 5, iclass 34, count 0 2006.257.09:11:05.30#ibcon#about to read 6, iclass 34, count 0 2006.257.09:11:05.30#ibcon#read 6, iclass 34, count 0 2006.257.09:11:05.30#ibcon#end of sib2, iclass 34, count 0 2006.257.09:11:05.30#ibcon#*after write, iclass 34, count 0 2006.257.09:11:05.30#ibcon#*before return 0, iclass 34, count 0 2006.257.09:11:05.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:05.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:11:05.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:11:05.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:11:05.30$vck44/vb=8,4 2006.257.09:11:05.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.09:11:05.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.09:11:05.30#ibcon#ireg 11 cls_cnt 2 2006.257.09:11:05.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:05.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:05.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:05.36#ibcon#enter wrdev, iclass 36, count 2 2006.257.09:11:05.36#ibcon#first serial, iclass 36, count 2 2006.257.09:11:05.36#ibcon#enter sib2, iclass 36, count 2 2006.257.09:11:05.36#ibcon#flushed, iclass 36, count 2 2006.257.09:11:05.36#ibcon#about to write, iclass 36, count 2 2006.257.09:11:05.36#ibcon#wrote, iclass 36, count 2 2006.257.09:11:05.36#ibcon#about to read 3, iclass 36, count 2 2006.257.09:11:05.38#ibcon#read 3, iclass 36, count 2 2006.257.09:11:05.38#ibcon#about to read 4, iclass 36, count 2 2006.257.09:11:05.38#ibcon#read 4, iclass 36, count 2 2006.257.09:11:05.38#ibcon#about to read 5, iclass 36, count 2 2006.257.09:11:05.38#ibcon#read 5, iclass 36, count 2 2006.257.09:11:05.38#ibcon#about to read 6, iclass 36, count 2 2006.257.09:11:05.38#ibcon#read 6, iclass 36, count 2 2006.257.09:11:05.38#ibcon#end of sib2, iclass 36, count 2 2006.257.09:11:05.38#ibcon#*mode == 0, iclass 36, count 2 2006.257.09:11:05.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.09:11:05.38#ibcon#[27=AT08-04\r\n] 2006.257.09:11:05.38#ibcon#*before write, iclass 36, count 2 2006.257.09:11:05.38#ibcon#enter sib2, iclass 36, count 2 2006.257.09:11:05.38#ibcon#flushed, iclass 36, count 2 2006.257.09:11:05.38#ibcon#about to write, iclass 36, count 2 2006.257.09:11:05.38#ibcon#wrote, iclass 36, count 2 2006.257.09:11:05.38#ibcon#about to read 3, iclass 36, count 2 2006.257.09:11:05.41#ibcon#read 3, iclass 36, count 2 2006.257.09:11:05.41#ibcon#about to read 4, iclass 36, count 2 2006.257.09:11:05.41#ibcon#read 4, iclass 36, count 2 2006.257.09:11:05.41#ibcon#about to read 5, iclass 36, count 2 2006.257.09:11:05.41#ibcon#read 5, iclass 36, count 2 2006.257.09:11:05.41#ibcon#about to read 6, iclass 36, count 2 2006.257.09:11:05.41#ibcon#read 6, iclass 36, count 2 2006.257.09:11:05.41#ibcon#end of sib2, iclass 36, count 2 2006.257.09:11:05.41#ibcon#*after write, iclass 36, count 2 2006.257.09:11:05.41#ibcon#*before return 0, iclass 36, count 2 2006.257.09:11:05.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:05.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:11:05.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.09:11:05.41#ibcon#ireg 7 cls_cnt 0 2006.257.09:11:05.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:05.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:05.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:05.53#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:11:05.53#ibcon#first serial, iclass 36, count 0 2006.257.09:11:05.53#ibcon#enter sib2, iclass 36, count 0 2006.257.09:11:05.53#ibcon#flushed, iclass 36, count 0 2006.257.09:11:05.53#ibcon#about to write, iclass 36, count 0 2006.257.09:11:05.53#ibcon#wrote, iclass 36, count 0 2006.257.09:11:05.53#ibcon#about to read 3, iclass 36, count 0 2006.257.09:11:05.55#ibcon#read 3, iclass 36, count 0 2006.257.09:11:05.55#ibcon#about to read 4, iclass 36, count 0 2006.257.09:11:05.55#ibcon#read 4, iclass 36, count 0 2006.257.09:11:05.55#ibcon#about to read 5, iclass 36, count 0 2006.257.09:11:05.55#ibcon#read 5, iclass 36, count 0 2006.257.09:11:05.55#ibcon#about to read 6, iclass 36, count 0 2006.257.09:11:05.55#ibcon#read 6, iclass 36, count 0 2006.257.09:11:05.55#ibcon#end of sib2, iclass 36, count 0 2006.257.09:11:05.55#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:11:05.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:11:05.55#ibcon#[27=USB\r\n] 2006.257.09:11:05.55#ibcon#*before write, iclass 36, count 0 2006.257.09:11:05.55#ibcon#enter sib2, iclass 36, count 0 2006.257.09:11:05.55#ibcon#flushed, iclass 36, count 0 2006.257.09:11:05.55#ibcon#about to write, iclass 36, count 0 2006.257.09:11:05.55#ibcon#wrote, iclass 36, count 0 2006.257.09:11:05.55#ibcon#about to read 3, iclass 36, count 0 2006.257.09:11:05.58#ibcon#read 3, iclass 36, count 0 2006.257.09:11:05.58#ibcon#about to read 4, iclass 36, count 0 2006.257.09:11:05.58#ibcon#read 4, iclass 36, count 0 2006.257.09:11:05.58#ibcon#about to read 5, iclass 36, count 0 2006.257.09:11:05.58#ibcon#read 5, iclass 36, count 0 2006.257.09:11:05.58#ibcon#about to read 6, iclass 36, count 0 2006.257.09:11:05.58#ibcon#read 6, iclass 36, count 0 2006.257.09:11:05.58#ibcon#end of sib2, iclass 36, count 0 2006.257.09:11:05.58#ibcon#*after write, iclass 36, count 0 2006.257.09:11:05.58#ibcon#*before return 0, iclass 36, count 0 2006.257.09:11:05.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:05.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:11:05.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:11:05.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:11:05.58$vck44/vabw=wide 2006.257.09:11:05.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.09:11:05.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.09:11:05.58#ibcon#ireg 8 cls_cnt 0 2006.257.09:11:05.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:05.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:05.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:05.58#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:11:05.58#ibcon#first serial, iclass 38, count 0 2006.257.09:11:05.58#ibcon#enter sib2, iclass 38, count 0 2006.257.09:11:05.58#ibcon#flushed, iclass 38, count 0 2006.257.09:11:05.58#ibcon#about to write, iclass 38, count 0 2006.257.09:11:05.58#ibcon#wrote, iclass 38, count 0 2006.257.09:11:05.58#ibcon#about to read 3, iclass 38, count 0 2006.257.09:11:05.60#ibcon#read 3, iclass 38, count 0 2006.257.09:11:05.60#ibcon#about to read 4, iclass 38, count 0 2006.257.09:11:05.60#ibcon#read 4, iclass 38, count 0 2006.257.09:11:05.60#ibcon#about to read 5, iclass 38, count 0 2006.257.09:11:05.60#ibcon#read 5, iclass 38, count 0 2006.257.09:11:05.60#ibcon#about to read 6, iclass 38, count 0 2006.257.09:11:05.60#ibcon#read 6, iclass 38, count 0 2006.257.09:11:05.60#ibcon#end of sib2, iclass 38, count 0 2006.257.09:11:05.60#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:11:05.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:11:05.60#ibcon#[25=BW32\r\n] 2006.257.09:11:05.60#ibcon#*before write, iclass 38, count 0 2006.257.09:11:05.60#ibcon#enter sib2, iclass 38, count 0 2006.257.09:11:05.60#ibcon#flushed, iclass 38, count 0 2006.257.09:11:05.60#ibcon#about to write, iclass 38, count 0 2006.257.09:11:05.60#ibcon#wrote, iclass 38, count 0 2006.257.09:11:05.60#ibcon#about to read 3, iclass 38, count 0 2006.257.09:11:05.63#ibcon#read 3, iclass 38, count 0 2006.257.09:11:05.63#ibcon#about to read 4, iclass 38, count 0 2006.257.09:11:05.63#ibcon#read 4, iclass 38, count 0 2006.257.09:11:05.63#ibcon#about to read 5, iclass 38, count 0 2006.257.09:11:05.63#ibcon#read 5, iclass 38, count 0 2006.257.09:11:05.63#ibcon#about to read 6, iclass 38, count 0 2006.257.09:11:05.63#ibcon#read 6, iclass 38, count 0 2006.257.09:11:05.63#ibcon#end of sib2, iclass 38, count 0 2006.257.09:11:05.63#ibcon#*after write, iclass 38, count 0 2006.257.09:11:05.63#ibcon#*before return 0, iclass 38, count 0 2006.257.09:11:05.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:05.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:11:05.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:11:05.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:11:05.63$vck44/vbbw=wide 2006.257.09:11:05.63#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.09:11:05.63#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.09:11:05.63#ibcon#ireg 8 cls_cnt 0 2006.257.09:11:05.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:11:05.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:11:05.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:11:05.70#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:11:05.70#ibcon#first serial, iclass 40, count 0 2006.257.09:11:05.70#ibcon#enter sib2, iclass 40, count 0 2006.257.09:11:05.70#ibcon#flushed, iclass 40, count 0 2006.257.09:11:05.70#ibcon#about to write, iclass 40, count 0 2006.257.09:11:05.70#ibcon#wrote, iclass 40, count 0 2006.257.09:11:05.70#ibcon#about to read 3, iclass 40, count 0 2006.257.09:11:05.72#ibcon#read 3, iclass 40, count 0 2006.257.09:11:05.72#ibcon#about to read 4, iclass 40, count 0 2006.257.09:11:05.72#ibcon#read 4, iclass 40, count 0 2006.257.09:11:05.72#ibcon#about to read 5, iclass 40, count 0 2006.257.09:11:05.72#ibcon#read 5, iclass 40, count 0 2006.257.09:11:05.72#ibcon#about to read 6, iclass 40, count 0 2006.257.09:11:05.72#ibcon#read 6, iclass 40, count 0 2006.257.09:11:05.72#ibcon#end of sib2, iclass 40, count 0 2006.257.09:11:05.72#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:11:05.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:11:05.72#ibcon#[27=BW32\r\n] 2006.257.09:11:05.72#ibcon#*before write, iclass 40, count 0 2006.257.09:11:05.72#ibcon#enter sib2, iclass 40, count 0 2006.257.09:11:05.72#ibcon#flushed, iclass 40, count 0 2006.257.09:11:05.72#ibcon#about to write, iclass 40, count 0 2006.257.09:11:05.72#ibcon#wrote, iclass 40, count 0 2006.257.09:11:05.72#ibcon#about to read 3, iclass 40, count 0 2006.257.09:11:05.75#ibcon#read 3, iclass 40, count 0 2006.257.09:11:05.75#ibcon#about to read 4, iclass 40, count 0 2006.257.09:11:05.75#ibcon#read 4, iclass 40, count 0 2006.257.09:11:05.75#ibcon#about to read 5, iclass 40, count 0 2006.257.09:11:05.75#ibcon#read 5, iclass 40, count 0 2006.257.09:11:05.75#ibcon#about to read 6, iclass 40, count 0 2006.257.09:11:05.75#ibcon#read 6, iclass 40, count 0 2006.257.09:11:05.75#ibcon#end of sib2, iclass 40, count 0 2006.257.09:11:05.75#ibcon#*after write, iclass 40, count 0 2006.257.09:11:05.75#ibcon#*before return 0, iclass 40, count 0 2006.257.09:11:05.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:11:05.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:11:05.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:11:05.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:11:05.75$setupk4/ifdk4 2006.257.09:11:05.75$ifdk4/lo= 2006.257.09:11:05.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:11:05.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:11:05.75$ifdk4/patch= 2006.257.09:11:05.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:11:05.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:11:05.75$setupk4/!*+20s 2006.257.09:11:10.75#abcon#<5=/14 1.0 2.2 19.95 941013.2\r\n> 2006.257.09:11:10.77#abcon#{5=INTERFACE CLEAR} 2006.257.09:11:10.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:11:20.25$setupk4/"tpicd 2006.257.09:11:20.25$setupk4/echo=off 2006.257.09:11:20.25$setupk4/xlog=off 2006.257.09:11:20.25:!2006.257.09:13:27 2006.257.09:11:53.14#trakl#Source acquired 2006.257.09:11:55.14#flagr#flagr/antenna,acquired 2006.257.09:13:27.00:preob 2006.257.09:13:27.14/onsource/TRACKING 2006.257.09:13:27.14:!2006.257.09:13:37 2006.257.09:13:37.00:"tape 2006.257.09:13:37.00:"st=record 2006.257.09:13:37.00:data_valid=on 2006.257.09:13:37.00:midob 2006.257.09:13:37.14/onsource/TRACKING 2006.257.09:13:37.14/wx/19.91,1013.2,94 2006.257.09:13:37.31/cable/+6.4749E-03 2006.257.09:13:38.40/va/01,08,usb,yes,30,33 2006.257.09:13:38.40/va/02,07,usb,yes,33,33 2006.257.09:13:38.40/va/03,08,usb,yes,29,31 2006.257.09:13:38.40/va/04,07,usb,yes,34,35 2006.257.09:13:38.40/va/05,04,usb,yes,30,31 2006.257.09:13:38.40/va/06,04,usb,yes,34,33 2006.257.09:13:38.40/va/07,04,usb,yes,35,35 2006.257.09:13:38.40/va/08,04,usb,yes,29,35 2006.257.09:13:38.63/valo/01,524.99,yes,locked 2006.257.09:13:38.63/valo/02,534.99,yes,locked 2006.257.09:13:38.63/valo/03,564.99,yes,locked 2006.257.09:13:38.63/valo/04,624.99,yes,locked 2006.257.09:13:38.63/valo/05,734.99,yes,locked 2006.257.09:13:38.63/valo/06,814.99,yes,locked 2006.257.09:13:38.63/valo/07,864.99,yes,locked 2006.257.09:13:38.63/valo/08,884.99,yes,locked 2006.257.09:13:39.72/vb/01,04,usb,yes,30,28 2006.257.09:13:39.72/vb/02,05,usb,yes,29,28 2006.257.09:13:39.72/vb/03,04,usb,yes,30,33 2006.257.09:13:39.72/vb/04,05,usb,yes,30,29 2006.257.09:13:39.72/vb/05,04,usb,yes,26,29 2006.257.09:13:39.72/vb/06,04,usb,yes,31,27 2006.257.09:13:39.72/vb/07,04,usb,yes,31,30 2006.257.09:13:39.72/vb/08,04,usb,yes,28,31 2006.257.09:13:39.96/vblo/01,629.99,yes,locked 2006.257.09:13:39.96/vblo/02,634.99,yes,locked 2006.257.09:13:39.96/vblo/03,649.99,yes,locked 2006.257.09:13:39.96/vblo/04,679.99,yes,locked 2006.257.09:13:39.96/vblo/05,709.99,yes,locked 2006.257.09:13:39.96/vblo/06,719.99,yes,locked 2006.257.09:13:39.96/vblo/07,734.99,yes,locked 2006.257.09:13:39.96/vblo/08,744.99,yes,locked 2006.257.09:13:40.11/vabw/8 2006.257.09:13:40.26/vbbw/8 2006.257.09:13:40.35/xfe/off,on,15.0 2006.257.09:13:40.73/ifatt/23,28,28,28 2006.257.09:13:41.07/fmout-gps/S +4.62E-07 2006.257.09:13:41.11:!2006.257.09:14:27 2006.257.09:14:27.01:data_valid=off 2006.257.09:14:27.02:"et 2006.257.09:14:27.02:!+3s 2006.257.09:14:30.03:"tape 2006.257.09:14:30.04:postob 2006.257.09:14:30.24/cable/+6.4755E-03 2006.257.09:14:30.25/wx/19.90,1013.2,95 2006.257.09:14:30.30/fmout-gps/S +4.63E-07 2006.257.09:14:30.31:scan_name=257-0919,jd0609,130 2006.257.09:14:30.31:source=3c274,123049.42,122328.0,2000.0,ccw 2006.257.09:14:31.13#flagr#flagr/antenna,new-source 2006.257.09:14:31.13:checkk5 2006.257.09:14:31.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:14:32.11/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:14:32.52/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:14:32.90/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:14:33.29/chk_obsdata//k5ts1/T2570913??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.09:14:33.69/chk_obsdata//k5ts2/T2570913??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.09:14:34.08/chk_obsdata//k5ts3/T2570913??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.09:14:34.48/chk_obsdata//k5ts4/T2570913??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.09:14:35.22/k5log//k5ts1_log_newline 2006.257.09:14:35.93/k5log//k5ts2_log_newline 2006.257.09:14:36.63/k5log//k5ts3_log_newline 2006.257.09:14:37.34/k5log//k5ts4_log_newline 2006.257.09:14:37.36/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:14:37.36:setupk4=1 2006.257.09:14:37.37$setupk4/echo=on 2006.257.09:14:37.37$setupk4/pcalon 2006.257.09:14:37.37$pcalon/"no phase cal control is implemented here 2006.257.09:14:37.37$setupk4/"tpicd=stop 2006.257.09:14:37.37$setupk4/"rec=synch_on 2006.257.09:14:37.37$setupk4/"rec_mode=128 2006.257.09:14:37.37$setupk4/!* 2006.257.09:14:37.37$setupk4/recpk4 2006.257.09:14:37.37$recpk4/recpatch= 2006.257.09:14:37.37$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:14:37.37$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:14:37.37$setupk4/vck44 2006.257.09:14:37.37$vck44/valo=1,524.99 2006.257.09:14:37.37#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.09:14:37.37#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.09:14:37.37#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:37.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:37.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:37.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:37.37#ibcon#enter wrdev, iclass 21, count 0 2006.257.09:14:37.37#ibcon#first serial, iclass 21, count 0 2006.257.09:14:37.37#ibcon#enter sib2, iclass 21, count 0 2006.257.09:14:37.37#ibcon#flushed, iclass 21, count 0 2006.257.09:14:37.37#ibcon#about to write, iclass 21, count 0 2006.257.09:14:37.37#ibcon#wrote, iclass 21, count 0 2006.257.09:14:37.37#ibcon#about to read 3, iclass 21, count 0 2006.257.09:14:37.38#ibcon#read 3, iclass 21, count 0 2006.257.09:14:37.38#ibcon#about to read 4, iclass 21, count 0 2006.257.09:14:37.38#ibcon#read 4, iclass 21, count 0 2006.257.09:14:37.38#ibcon#about to read 5, iclass 21, count 0 2006.257.09:14:37.38#ibcon#read 5, iclass 21, count 0 2006.257.09:14:37.38#ibcon#about to read 6, iclass 21, count 0 2006.257.09:14:37.38#ibcon#read 6, iclass 21, count 0 2006.257.09:14:37.38#ibcon#end of sib2, iclass 21, count 0 2006.257.09:14:37.38#ibcon#*mode == 0, iclass 21, count 0 2006.257.09:14:37.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.09:14:37.38#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:14:37.38#ibcon#*before write, iclass 21, count 0 2006.257.09:14:37.38#ibcon#enter sib2, iclass 21, count 0 2006.257.09:14:37.38#ibcon#flushed, iclass 21, count 0 2006.257.09:14:37.38#ibcon#about to write, iclass 21, count 0 2006.257.09:14:37.38#ibcon#wrote, iclass 21, count 0 2006.257.09:14:37.38#ibcon#about to read 3, iclass 21, count 0 2006.257.09:14:37.43#ibcon#read 3, iclass 21, count 0 2006.257.09:14:37.43#ibcon#about to read 4, iclass 21, count 0 2006.257.09:14:37.43#ibcon#read 4, iclass 21, count 0 2006.257.09:14:37.43#ibcon#about to read 5, iclass 21, count 0 2006.257.09:14:37.43#ibcon#read 5, iclass 21, count 0 2006.257.09:14:37.43#ibcon#about to read 6, iclass 21, count 0 2006.257.09:14:37.43#ibcon#read 6, iclass 21, count 0 2006.257.09:14:37.43#ibcon#end of sib2, iclass 21, count 0 2006.257.09:14:37.43#ibcon#*after write, iclass 21, count 0 2006.257.09:14:37.43#ibcon#*before return 0, iclass 21, count 0 2006.257.09:14:37.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:37.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:37.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.09:14:37.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.09:14:37.43$vck44/va=1,8 2006.257.09:14:37.43#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.09:14:37.43#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.09:14:37.43#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:37.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:37.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:37.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:37.43#ibcon#enter wrdev, iclass 23, count 2 2006.257.09:14:37.43#ibcon#first serial, iclass 23, count 2 2006.257.09:14:37.43#ibcon#enter sib2, iclass 23, count 2 2006.257.09:14:37.43#ibcon#flushed, iclass 23, count 2 2006.257.09:14:37.43#ibcon#about to write, iclass 23, count 2 2006.257.09:14:37.43#ibcon#wrote, iclass 23, count 2 2006.257.09:14:37.43#ibcon#about to read 3, iclass 23, count 2 2006.257.09:14:37.45#ibcon#read 3, iclass 23, count 2 2006.257.09:14:37.45#ibcon#about to read 4, iclass 23, count 2 2006.257.09:14:37.45#ibcon#read 4, iclass 23, count 2 2006.257.09:14:37.45#ibcon#about to read 5, iclass 23, count 2 2006.257.09:14:37.45#ibcon#read 5, iclass 23, count 2 2006.257.09:14:37.45#ibcon#about to read 6, iclass 23, count 2 2006.257.09:14:37.45#ibcon#read 6, iclass 23, count 2 2006.257.09:14:37.45#ibcon#end of sib2, iclass 23, count 2 2006.257.09:14:37.45#ibcon#*mode == 0, iclass 23, count 2 2006.257.09:14:37.45#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.09:14:37.45#ibcon#[25=AT01-08\r\n] 2006.257.09:14:37.45#ibcon#*before write, iclass 23, count 2 2006.257.09:14:37.45#ibcon#enter sib2, iclass 23, count 2 2006.257.09:14:37.45#ibcon#flushed, iclass 23, count 2 2006.257.09:14:37.45#ibcon#about to write, iclass 23, count 2 2006.257.09:14:37.45#ibcon#wrote, iclass 23, count 2 2006.257.09:14:37.45#ibcon#about to read 3, iclass 23, count 2 2006.257.09:14:37.48#ibcon#read 3, iclass 23, count 2 2006.257.09:14:37.48#ibcon#about to read 4, iclass 23, count 2 2006.257.09:14:37.48#ibcon#read 4, iclass 23, count 2 2006.257.09:14:37.48#ibcon#about to read 5, iclass 23, count 2 2006.257.09:14:37.48#ibcon#read 5, iclass 23, count 2 2006.257.09:14:37.48#ibcon#about to read 6, iclass 23, count 2 2006.257.09:14:37.48#ibcon#read 6, iclass 23, count 2 2006.257.09:14:37.48#ibcon#end of sib2, iclass 23, count 2 2006.257.09:14:37.48#ibcon#*after write, iclass 23, count 2 2006.257.09:14:37.48#ibcon#*before return 0, iclass 23, count 2 2006.257.09:14:37.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:37.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:37.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.09:14:37.48#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:37.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:37.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:37.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:37.60#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:14:37.60#ibcon#first serial, iclass 23, count 0 2006.257.09:14:37.60#ibcon#enter sib2, iclass 23, count 0 2006.257.09:14:37.60#ibcon#flushed, iclass 23, count 0 2006.257.09:14:37.60#ibcon#about to write, iclass 23, count 0 2006.257.09:14:37.60#ibcon#wrote, iclass 23, count 0 2006.257.09:14:37.60#ibcon#about to read 3, iclass 23, count 0 2006.257.09:14:37.62#ibcon#read 3, iclass 23, count 0 2006.257.09:14:37.62#ibcon#about to read 4, iclass 23, count 0 2006.257.09:14:37.62#ibcon#read 4, iclass 23, count 0 2006.257.09:14:37.62#ibcon#about to read 5, iclass 23, count 0 2006.257.09:14:37.62#ibcon#read 5, iclass 23, count 0 2006.257.09:14:37.62#ibcon#about to read 6, iclass 23, count 0 2006.257.09:14:37.62#ibcon#read 6, iclass 23, count 0 2006.257.09:14:37.62#ibcon#end of sib2, iclass 23, count 0 2006.257.09:14:37.62#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:14:37.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:14:37.62#ibcon#[25=USB\r\n] 2006.257.09:14:37.62#ibcon#*before write, iclass 23, count 0 2006.257.09:14:37.62#ibcon#enter sib2, iclass 23, count 0 2006.257.09:14:37.62#ibcon#flushed, iclass 23, count 0 2006.257.09:14:37.62#ibcon#about to write, iclass 23, count 0 2006.257.09:14:37.62#ibcon#wrote, iclass 23, count 0 2006.257.09:14:37.62#ibcon#about to read 3, iclass 23, count 0 2006.257.09:14:37.65#ibcon#read 3, iclass 23, count 0 2006.257.09:14:37.65#ibcon#about to read 4, iclass 23, count 0 2006.257.09:14:37.65#ibcon#read 4, iclass 23, count 0 2006.257.09:14:37.65#ibcon#about to read 5, iclass 23, count 0 2006.257.09:14:37.65#ibcon#read 5, iclass 23, count 0 2006.257.09:14:37.65#ibcon#about to read 6, iclass 23, count 0 2006.257.09:14:37.65#ibcon#read 6, iclass 23, count 0 2006.257.09:14:37.65#ibcon#end of sib2, iclass 23, count 0 2006.257.09:14:37.65#ibcon#*after write, iclass 23, count 0 2006.257.09:14:37.65#ibcon#*before return 0, iclass 23, count 0 2006.257.09:14:37.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:37.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:37.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:14:37.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:14:37.65$vck44/valo=2,534.99 2006.257.09:14:37.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.09:14:37.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.09:14:37.65#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:37.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:37.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:37.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:37.65#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:14:37.65#ibcon#first serial, iclass 25, count 0 2006.257.09:14:37.65#ibcon#enter sib2, iclass 25, count 0 2006.257.09:14:37.65#ibcon#flushed, iclass 25, count 0 2006.257.09:14:37.65#ibcon#about to write, iclass 25, count 0 2006.257.09:14:37.65#ibcon#wrote, iclass 25, count 0 2006.257.09:14:37.65#ibcon#about to read 3, iclass 25, count 0 2006.257.09:14:37.67#ibcon#read 3, iclass 25, count 0 2006.257.09:14:37.67#ibcon#about to read 4, iclass 25, count 0 2006.257.09:14:37.67#ibcon#read 4, iclass 25, count 0 2006.257.09:14:37.67#ibcon#about to read 5, iclass 25, count 0 2006.257.09:14:37.67#ibcon#read 5, iclass 25, count 0 2006.257.09:14:37.67#ibcon#about to read 6, iclass 25, count 0 2006.257.09:14:37.67#ibcon#read 6, iclass 25, count 0 2006.257.09:14:37.67#ibcon#end of sib2, iclass 25, count 0 2006.257.09:14:37.67#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:14:37.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:14:37.67#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:14:37.67#ibcon#*before write, iclass 25, count 0 2006.257.09:14:37.67#ibcon#enter sib2, iclass 25, count 0 2006.257.09:14:37.67#ibcon#flushed, iclass 25, count 0 2006.257.09:14:37.67#ibcon#about to write, iclass 25, count 0 2006.257.09:14:37.67#ibcon#wrote, iclass 25, count 0 2006.257.09:14:37.67#ibcon#about to read 3, iclass 25, count 0 2006.257.09:14:37.71#ibcon#read 3, iclass 25, count 0 2006.257.09:14:37.71#ibcon#about to read 4, iclass 25, count 0 2006.257.09:14:37.71#ibcon#read 4, iclass 25, count 0 2006.257.09:14:37.71#ibcon#about to read 5, iclass 25, count 0 2006.257.09:14:37.71#ibcon#read 5, iclass 25, count 0 2006.257.09:14:37.71#ibcon#about to read 6, iclass 25, count 0 2006.257.09:14:37.71#ibcon#read 6, iclass 25, count 0 2006.257.09:14:37.71#ibcon#end of sib2, iclass 25, count 0 2006.257.09:14:37.71#ibcon#*after write, iclass 25, count 0 2006.257.09:14:37.71#ibcon#*before return 0, iclass 25, count 0 2006.257.09:14:37.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:37.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:37.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:14:37.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:14:37.71$vck44/va=2,7 2006.257.09:14:37.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.09:14:37.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.09:14:37.71#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:37.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:37.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:37.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:37.77#ibcon#enter wrdev, iclass 27, count 2 2006.257.09:14:37.77#ibcon#first serial, iclass 27, count 2 2006.257.09:14:37.77#ibcon#enter sib2, iclass 27, count 2 2006.257.09:14:37.77#ibcon#flushed, iclass 27, count 2 2006.257.09:14:37.77#ibcon#about to write, iclass 27, count 2 2006.257.09:14:37.77#ibcon#wrote, iclass 27, count 2 2006.257.09:14:37.77#ibcon#about to read 3, iclass 27, count 2 2006.257.09:14:37.79#ibcon#read 3, iclass 27, count 2 2006.257.09:14:37.79#ibcon#about to read 4, iclass 27, count 2 2006.257.09:14:37.79#ibcon#read 4, iclass 27, count 2 2006.257.09:14:37.79#ibcon#about to read 5, iclass 27, count 2 2006.257.09:14:37.79#ibcon#read 5, iclass 27, count 2 2006.257.09:14:37.79#ibcon#about to read 6, iclass 27, count 2 2006.257.09:14:37.79#ibcon#read 6, iclass 27, count 2 2006.257.09:14:37.79#ibcon#end of sib2, iclass 27, count 2 2006.257.09:14:37.79#ibcon#*mode == 0, iclass 27, count 2 2006.257.09:14:37.79#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.09:14:37.79#ibcon#[25=AT02-07\r\n] 2006.257.09:14:37.79#ibcon#*before write, iclass 27, count 2 2006.257.09:14:37.79#ibcon#enter sib2, iclass 27, count 2 2006.257.09:14:37.79#ibcon#flushed, iclass 27, count 2 2006.257.09:14:37.79#ibcon#about to write, iclass 27, count 2 2006.257.09:14:37.79#ibcon#wrote, iclass 27, count 2 2006.257.09:14:37.79#ibcon#about to read 3, iclass 27, count 2 2006.257.09:14:37.82#ibcon#read 3, iclass 27, count 2 2006.257.09:14:37.82#ibcon#about to read 4, iclass 27, count 2 2006.257.09:14:37.82#ibcon#read 4, iclass 27, count 2 2006.257.09:14:37.82#ibcon#about to read 5, iclass 27, count 2 2006.257.09:14:37.82#ibcon#read 5, iclass 27, count 2 2006.257.09:14:37.82#ibcon#about to read 6, iclass 27, count 2 2006.257.09:14:37.82#ibcon#read 6, iclass 27, count 2 2006.257.09:14:37.82#ibcon#end of sib2, iclass 27, count 2 2006.257.09:14:37.82#ibcon#*after write, iclass 27, count 2 2006.257.09:14:37.82#ibcon#*before return 0, iclass 27, count 2 2006.257.09:14:37.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:37.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:37.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.09:14:37.82#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:37.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:37.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:37.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:37.94#ibcon#enter wrdev, iclass 27, count 0 2006.257.09:14:37.94#ibcon#first serial, iclass 27, count 0 2006.257.09:14:37.94#ibcon#enter sib2, iclass 27, count 0 2006.257.09:14:37.94#ibcon#flushed, iclass 27, count 0 2006.257.09:14:37.94#ibcon#about to write, iclass 27, count 0 2006.257.09:14:37.94#ibcon#wrote, iclass 27, count 0 2006.257.09:14:37.94#ibcon#about to read 3, iclass 27, count 0 2006.257.09:14:37.96#ibcon#read 3, iclass 27, count 0 2006.257.09:14:37.96#ibcon#about to read 4, iclass 27, count 0 2006.257.09:14:37.96#ibcon#read 4, iclass 27, count 0 2006.257.09:14:37.96#ibcon#about to read 5, iclass 27, count 0 2006.257.09:14:37.96#ibcon#read 5, iclass 27, count 0 2006.257.09:14:37.96#ibcon#about to read 6, iclass 27, count 0 2006.257.09:14:37.96#ibcon#read 6, iclass 27, count 0 2006.257.09:14:37.96#ibcon#end of sib2, iclass 27, count 0 2006.257.09:14:37.96#ibcon#*mode == 0, iclass 27, count 0 2006.257.09:14:37.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.09:14:37.96#ibcon#[25=USB\r\n] 2006.257.09:14:37.96#ibcon#*before write, iclass 27, count 0 2006.257.09:14:37.96#ibcon#enter sib2, iclass 27, count 0 2006.257.09:14:37.96#ibcon#flushed, iclass 27, count 0 2006.257.09:14:37.96#ibcon#about to write, iclass 27, count 0 2006.257.09:14:37.96#ibcon#wrote, iclass 27, count 0 2006.257.09:14:37.96#ibcon#about to read 3, iclass 27, count 0 2006.257.09:14:37.99#ibcon#read 3, iclass 27, count 0 2006.257.09:14:37.99#ibcon#about to read 4, iclass 27, count 0 2006.257.09:14:37.99#ibcon#read 4, iclass 27, count 0 2006.257.09:14:37.99#ibcon#about to read 5, iclass 27, count 0 2006.257.09:14:37.99#ibcon#read 5, iclass 27, count 0 2006.257.09:14:37.99#ibcon#about to read 6, iclass 27, count 0 2006.257.09:14:37.99#ibcon#read 6, iclass 27, count 0 2006.257.09:14:37.99#ibcon#end of sib2, iclass 27, count 0 2006.257.09:14:37.99#ibcon#*after write, iclass 27, count 0 2006.257.09:14:37.99#ibcon#*before return 0, iclass 27, count 0 2006.257.09:14:37.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:37.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:37.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.09:14:37.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.09:14:37.99$vck44/valo=3,564.99 2006.257.09:14:37.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.09:14:37.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.09:14:37.99#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:37.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:37.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:37.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:37.99#ibcon#enter wrdev, iclass 29, count 0 2006.257.09:14:37.99#ibcon#first serial, iclass 29, count 0 2006.257.09:14:37.99#ibcon#enter sib2, iclass 29, count 0 2006.257.09:14:37.99#ibcon#flushed, iclass 29, count 0 2006.257.09:14:37.99#ibcon#about to write, iclass 29, count 0 2006.257.09:14:37.99#ibcon#wrote, iclass 29, count 0 2006.257.09:14:37.99#ibcon#about to read 3, iclass 29, count 0 2006.257.09:14:38.01#ibcon#read 3, iclass 29, count 0 2006.257.09:14:38.01#ibcon#about to read 4, iclass 29, count 0 2006.257.09:14:38.01#ibcon#read 4, iclass 29, count 0 2006.257.09:14:38.01#ibcon#about to read 5, iclass 29, count 0 2006.257.09:14:38.01#ibcon#read 5, iclass 29, count 0 2006.257.09:14:38.01#ibcon#about to read 6, iclass 29, count 0 2006.257.09:14:38.01#ibcon#read 6, iclass 29, count 0 2006.257.09:14:38.01#ibcon#end of sib2, iclass 29, count 0 2006.257.09:14:38.01#ibcon#*mode == 0, iclass 29, count 0 2006.257.09:14:38.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.09:14:38.01#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:14:38.01#ibcon#*before write, iclass 29, count 0 2006.257.09:14:38.01#ibcon#enter sib2, iclass 29, count 0 2006.257.09:14:38.01#ibcon#flushed, iclass 29, count 0 2006.257.09:14:38.01#ibcon#about to write, iclass 29, count 0 2006.257.09:14:38.01#ibcon#wrote, iclass 29, count 0 2006.257.09:14:38.01#ibcon#about to read 3, iclass 29, count 0 2006.257.09:14:38.05#ibcon#read 3, iclass 29, count 0 2006.257.09:14:38.05#ibcon#about to read 4, iclass 29, count 0 2006.257.09:14:38.05#ibcon#read 4, iclass 29, count 0 2006.257.09:14:38.05#ibcon#about to read 5, iclass 29, count 0 2006.257.09:14:38.05#ibcon#read 5, iclass 29, count 0 2006.257.09:14:38.05#ibcon#about to read 6, iclass 29, count 0 2006.257.09:14:38.05#ibcon#read 6, iclass 29, count 0 2006.257.09:14:38.05#ibcon#end of sib2, iclass 29, count 0 2006.257.09:14:38.05#ibcon#*after write, iclass 29, count 0 2006.257.09:14:38.05#ibcon#*before return 0, iclass 29, count 0 2006.257.09:14:38.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:38.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:38.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.09:14:38.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.09:14:38.05$vck44/va=3,8 2006.257.09:14:38.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.09:14:38.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.09:14:38.05#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:38.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:38.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:38.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:38.11#ibcon#enter wrdev, iclass 31, count 2 2006.257.09:14:38.11#ibcon#first serial, iclass 31, count 2 2006.257.09:14:38.11#ibcon#enter sib2, iclass 31, count 2 2006.257.09:14:38.11#ibcon#flushed, iclass 31, count 2 2006.257.09:14:38.11#ibcon#about to write, iclass 31, count 2 2006.257.09:14:38.11#ibcon#wrote, iclass 31, count 2 2006.257.09:14:38.11#ibcon#about to read 3, iclass 31, count 2 2006.257.09:14:38.13#ibcon#read 3, iclass 31, count 2 2006.257.09:14:38.13#ibcon#about to read 4, iclass 31, count 2 2006.257.09:14:38.13#ibcon#read 4, iclass 31, count 2 2006.257.09:14:38.13#ibcon#about to read 5, iclass 31, count 2 2006.257.09:14:38.13#ibcon#read 5, iclass 31, count 2 2006.257.09:14:38.13#ibcon#about to read 6, iclass 31, count 2 2006.257.09:14:38.13#ibcon#read 6, iclass 31, count 2 2006.257.09:14:38.13#ibcon#end of sib2, iclass 31, count 2 2006.257.09:14:38.13#ibcon#*mode == 0, iclass 31, count 2 2006.257.09:14:38.13#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.09:14:38.13#ibcon#[25=AT03-08\r\n] 2006.257.09:14:38.13#ibcon#*before write, iclass 31, count 2 2006.257.09:14:38.13#ibcon#enter sib2, iclass 31, count 2 2006.257.09:14:38.13#ibcon#flushed, iclass 31, count 2 2006.257.09:14:38.13#ibcon#about to write, iclass 31, count 2 2006.257.09:14:38.13#ibcon#wrote, iclass 31, count 2 2006.257.09:14:38.13#ibcon#about to read 3, iclass 31, count 2 2006.257.09:14:38.16#ibcon#read 3, iclass 31, count 2 2006.257.09:14:38.16#ibcon#about to read 4, iclass 31, count 2 2006.257.09:14:38.16#ibcon#read 4, iclass 31, count 2 2006.257.09:14:38.16#ibcon#about to read 5, iclass 31, count 2 2006.257.09:14:38.16#ibcon#read 5, iclass 31, count 2 2006.257.09:14:38.16#ibcon#about to read 6, iclass 31, count 2 2006.257.09:14:38.16#ibcon#read 6, iclass 31, count 2 2006.257.09:14:38.16#ibcon#end of sib2, iclass 31, count 2 2006.257.09:14:38.16#ibcon#*after write, iclass 31, count 2 2006.257.09:14:38.16#ibcon#*before return 0, iclass 31, count 2 2006.257.09:14:38.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:38.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:38.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.09:14:38.16#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:38.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:38.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:38.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:38.28#ibcon#enter wrdev, iclass 31, count 0 2006.257.09:14:38.28#ibcon#first serial, iclass 31, count 0 2006.257.09:14:38.28#ibcon#enter sib2, iclass 31, count 0 2006.257.09:14:38.28#ibcon#flushed, iclass 31, count 0 2006.257.09:14:38.28#ibcon#about to write, iclass 31, count 0 2006.257.09:14:38.28#ibcon#wrote, iclass 31, count 0 2006.257.09:14:38.28#ibcon#about to read 3, iclass 31, count 0 2006.257.09:14:38.30#ibcon#read 3, iclass 31, count 0 2006.257.09:14:38.30#ibcon#about to read 4, iclass 31, count 0 2006.257.09:14:38.30#ibcon#read 4, iclass 31, count 0 2006.257.09:14:38.30#ibcon#about to read 5, iclass 31, count 0 2006.257.09:14:38.30#ibcon#read 5, iclass 31, count 0 2006.257.09:14:38.30#ibcon#about to read 6, iclass 31, count 0 2006.257.09:14:38.30#ibcon#read 6, iclass 31, count 0 2006.257.09:14:38.30#ibcon#end of sib2, iclass 31, count 0 2006.257.09:14:38.30#ibcon#*mode == 0, iclass 31, count 0 2006.257.09:14:38.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.09:14:38.30#ibcon#[25=USB\r\n] 2006.257.09:14:38.30#ibcon#*before write, iclass 31, count 0 2006.257.09:14:38.30#ibcon#enter sib2, iclass 31, count 0 2006.257.09:14:38.30#ibcon#flushed, iclass 31, count 0 2006.257.09:14:38.30#ibcon#about to write, iclass 31, count 0 2006.257.09:14:38.30#ibcon#wrote, iclass 31, count 0 2006.257.09:14:38.30#ibcon#about to read 3, iclass 31, count 0 2006.257.09:14:38.33#ibcon#read 3, iclass 31, count 0 2006.257.09:14:38.33#ibcon#about to read 4, iclass 31, count 0 2006.257.09:14:38.33#ibcon#read 4, iclass 31, count 0 2006.257.09:14:38.33#ibcon#about to read 5, iclass 31, count 0 2006.257.09:14:38.33#ibcon#read 5, iclass 31, count 0 2006.257.09:14:38.33#ibcon#about to read 6, iclass 31, count 0 2006.257.09:14:38.33#ibcon#read 6, iclass 31, count 0 2006.257.09:14:38.33#ibcon#end of sib2, iclass 31, count 0 2006.257.09:14:38.33#ibcon#*after write, iclass 31, count 0 2006.257.09:14:38.33#ibcon#*before return 0, iclass 31, count 0 2006.257.09:14:38.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:38.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:38.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.09:14:38.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.09:14:38.33$vck44/valo=4,624.99 2006.257.09:14:38.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.09:14:38.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.09:14:38.33#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:38.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:38.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:38.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:38.33#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:14:38.33#ibcon#first serial, iclass 33, count 0 2006.257.09:14:38.33#ibcon#enter sib2, iclass 33, count 0 2006.257.09:14:38.33#ibcon#flushed, iclass 33, count 0 2006.257.09:14:38.33#ibcon#about to write, iclass 33, count 0 2006.257.09:14:38.33#ibcon#wrote, iclass 33, count 0 2006.257.09:14:38.33#ibcon#about to read 3, iclass 33, count 0 2006.257.09:14:38.35#ibcon#read 3, iclass 33, count 0 2006.257.09:14:38.35#ibcon#about to read 4, iclass 33, count 0 2006.257.09:14:38.35#ibcon#read 4, iclass 33, count 0 2006.257.09:14:38.35#ibcon#about to read 5, iclass 33, count 0 2006.257.09:14:38.35#ibcon#read 5, iclass 33, count 0 2006.257.09:14:38.35#ibcon#about to read 6, iclass 33, count 0 2006.257.09:14:38.35#ibcon#read 6, iclass 33, count 0 2006.257.09:14:38.35#ibcon#end of sib2, iclass 33, count 0 2006.257.09:14:38.35#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:14:38.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:14:38.35#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:14:38.35#ibcon#*before write, iclass 33, count 0 2006.257.09:14:38.35#ibcon#enter sib2, iclass 33, count 0 2006.257.09:14:38.35#ibcon#flushed, iclass 33, count 0 2006.257.09:14:38.35#ibcon#about to write, iclass 33, count 0 2006.257.09:14:38.35#ibcon#wrote, iclass 33, count 0 2006.257.09:14:38.35#ibcon#about to read 3, iclass 33, count 0 2006.257.09:14:38.39#ibcon#read 3, iclass 33, count 0 2006.257.09:14:38.39#ibcon#about to read 4, iclass 33, count 0 2006.257.09:14:38.39#ibcon#read 4, iclass 33, count 0 2006.257.09:14:38.39#ibcon#about to read 5, iclass 33, count 0 2006.257.09:14:38.39#ibcon#read 5, iclass 33, count 0 2006.257.09:14:38.39#ibcon#about to read 6, iclass 33, count 0 2006.257.09:14:38.39#ibcon#read 6, iclass 33, count 0 2006.257.09:14:38.39#ibcon#end of sib2, iclass 33, count 0 2006.257.09:14:38.39#ibcon#*after write, iclass 33, count 0 2006.257.09:14:38.39#ibcon#*before return 0, iclass 33, count 0 2006.257.09:14:38.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:38.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:38.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:14:38.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:14:38.39$vck44/va=4,7 2006.257.09:14:38.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.09:14:38.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.09:14:38.39#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:38.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:38.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:38.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:38.45#ibcon#enter wrdev, iclass 35, count 2 2006.257.09:14:38.45#ibcon#first serial, iclass 35, count 2 2006.257.09:14:38.45#ibcon#enter sib2, iclass 35, count 2 2006.257.09:14:38.45#ibcon#flushed, iclass 35, count 2 2006.257.09:14:38.45#ibcon#about to write, iclass 35, count 2 2006.257.09:14:38.45#ibcon#wrote, iclass 35, count 2 2006.257.09:14:38.45#ibcon#about to read 3, iclass 35, count 2 2006.257.09:14:38.47#ibcon#read 3, iclass 35, count 2 2006.257.09:14:38.47#ibcon#about to read 4, iclass 35, count 2 2006.257.09:14:38.47#ibcon#read 4, iclass 35, count 2 2006.257.09:14:38.47#ibcon#about to read 5, iclass 35, count 2 2006.257.09:14:38.47#ibcon#read 5, iclass 35, count 2 2006.257.09:14:38.47#ibcon#about to read 6, iclass 35, count 2 2006.257.09:14:38.47#ibcon#read 6, iclass 35, count 2 2006.257.09:14:38.47#ibcon#end of sib2, iclass 35, count 2 2006.257.09:14:38.47#ibcon#*mode == 0, iclass 35, count 2 2006.257.09:14:38.47#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.09:14:38.47#ibcon#[25=AT04-07\r\n] 2006.257.09:14:38.47#ibcon#*before write, iclass 35, count 2 2006.257.09:14:38.47#ibcon#enter sib2, iclass 35, count 2 2006.257.09:14:38.47#ibcon#flushed, iclass 35, count 2 2006.257.09:14:38.47#ibcon#about to write, iclass 35, count 2 2006.257.09:14:38.47#ibcon#wrote, iclass 35, count 2 2006.257.09:14:38.47#ibcon#about to read 3, iclass 35, count 2 2006.257.09:14:38.50#ibcon#read 3, iclass 35, count 2 2006.257.09:14:38.50#ibcon#about to read 4, iclass 35, count 2 2006.257.09:14:38.50#ibcon#read 4, iclass 35, count 2 2006.257.09:14:38.50#ibcon#about to read 5, iclass 35, count 2 2006.257.09:14:38.50#ibcon#read 5, iclass 35, count 2 2006.257.09:14:38.50#ibcon#about to read 6, iclass 35, count 2 2006.257.09:14:38.50#ibcon#read 6, iclass 35, count 2 2006.257.09:14:38.50#ibcon#end of sib2, iclass 35, count 2 2006.257.09:14:38.50#ibcon#*after write, iclass 35, count 2 2006.257.09:14:38.50#ibcon#*before return 0, iclass 35, count 2 2006.257.09:14:38.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:38.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:38.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.09:14:38.50#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:38.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:38.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:38.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:38.62#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:14:38.62#ibcon#first serial, iclass 35, count 0 2006.257.09:14:38.62#ibcon#enter sib2, iclass 35, count 0 2006.257.09:14:38.62#ibcon#flushed, iclass 35, count 0 2006.257.09:14:38.62#ibcon#about to write, iclass 35, count 0 2006.257.09:14:38.62#ibcon#wrote, iclass 35, count 0 2006.257.09:14:38.62#ibcon#about to read 3, iclass 35, count 0 2006.257.09:14:38.64#ibcon#read 3, iclass 35, count 0 2006.257.09:14:38.64#ibcon#about to read 4, iclass 35, count 0 2006.257.09:14:38.64#ibcon#read 4, iclass 35, count 0 2006.257.09:14:38.64#ibcon#about to read 5, iclass 35, count 0 2006.257.09:14:38.64#ibcon#read 5, iclass 35, count 0 2006.257.09:14:38.64#ibcon#about to read 6, iclass 35, count 0 2006.257.09:14:38.64#ibcon#read 6, iclass 35, count 0 2006.257.09:14:38.64#ibcon#end of sib2, iclass 35, count 0 2006.257.09:14:38.64#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:14:38.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:14:38.64#ibcon#[25=USB\r\n] 2006.257.09:14:38.64#ibcon#*before write, iclass 35, count 0 2006.257.09:14:38.64#ibcon#enter sib2, iclass 35, count 0 2006.257.09:14:38.64#ibcon#flushed, iclass 35, count 0 2006.257.09:14:38.64#ibcon#about to write, iclass 35, count 0 2006.257.09:14:38.64#ibcon#wrote, iclass 35, count 0 2006.257.09:14:38.64#ibcon#about to read 3, iclass 35, count 0 2006.257.09:14:38.67#ibcon#read 3, iclass 35, count 0 2006.257.09:14:38.67#ibcon#about to read 4, iclass 35, count 0 2006.257.09:14:38.67#ibcon#read 4, iclass 35, count 0 2006.257.09:14:38.67#ibcon#about to read 5, iclass 35, count 0 2006.257.09:14:38.67#ibcon#read 5, iclass 35, count 0 2006.257.09:14:38.67#ibcon#about to read 6, iclass 35, count 0 2006.257.09:14:38.67#ibcon#read 6, iclass 35, count 0 2006.257.09:14:38.67#ibcon#end of sib2, iclass 35, count 0 2006.257.09:14:38.67#ibcon#*after write, iclass 35, count 0 2006.257.09:14:38.67#ibcon#*before return 0, iclass 35, count 0 2006.257.09:14:38.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:38.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:38.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:14:38.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:14:38.67$vck44/valo=5,734.99 2006.257.09:14:38.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.09:14:38.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.09:14:38.67#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:38.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:38.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:38.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:38.67#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:14:38.67#ibcon#first serial, iclass 37, count 0 2006.257.09:14:38.67#ibcon#enter sib2, iclass 37, count 0 2006.257.09:14:38.67#ibcon#flushed, iclass 37, count 0 2006.257.09:14:38.67#ibcon#about to write, iclass 37, count 0 2006.257.09:14:38.67#ibcon#wrote, iclass 37, count 0 2006.257.09:14:38.67#ibcon#about to read 3, iclass 37, count 0 2006.257.09:14:38.69#ibcon#read 3, iclass 37, count 0 2006.257.09:14:38.69#ibcon#about to read 4, iclass 37, count 0 2006.257.09:14:38.69#ibcon#read 4, iclass 37, count 0 2006.257.09:14:38.69#ibcon#about to read 5, iclass 37, count 0 2006.257.09:14:38.69#ibcon#read 5, iclass 37, count 0 2006.257.09:14:38.69#ibcon#about to read 6, iclass 37, count 0 2006.257.09:14:38.69#ibcon#read 6, iclass 37, count 0 2006.257.09:14:38.69#ibcon#end of sib2, iclass 37, count 0 2006.257.09:14:38.69#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:14:38.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:14:38.69#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:14:38.69#ibcon#*before write, iclass 37, count 0 2006.257.09:14:38.69#ibcon#enter sib2, iclass 37, count 0 2006.257.09:14:38.69#ibcon#flushed, iclass 37, count 0 2006.257.09:14:38.69#ibcon#about to write, iclass 37, count 0 2006.257.09:14:38.69#ibcon#wrote, iclass 37, count 0 2006.257.09:14:38.69#ibcon#about to read 3, iclass 37, count 0 2006.257.09:14:38.73#ibcon#read 3, iclass 37, count 0 2006.257.09:14:38.73#ibcon#about to read 4, iclass 37, count 0 2006.257.09:14:38.73#ibcon#read 4, iclass 37, count 0 2006.257.09:14:38.73#ibcon#about to read 5, iclass 37, count 0 2006.257.09:14:38.73#ibcon#read 5, iclass 37, count 0 2006.257.09:14:38.73#ibcon#about to read 6, iclass 37, count 0 2006.257.09:14:38.73#ibcon#read 6, iclass 37, count 0 2006.257.09:14:38.73#ibcon#end of sib2, iclass 37, count 0 2006.257.09:14:38.73#ibcon#*after write, iclass 37, count 0 2006.257.09:14:38.73#ibcon#*before return 0, iclass 37, count 0 2006.257.09:14:38.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:38.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:38.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:14:38.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:14:38.73$vck44/va=5,4 2006.257.09:14:38.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.09:14:38.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.09:14:38.73#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:38.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:38.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:38.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:38.79#ibcon#enter wrdev, iclass 39, count 2 2006.257.09:14:38.79#ibcon#first serial, iclass 39, count 2 2006.257.09:14:38.79#ibcon#enter sib2, iclass 39, count 2 2006.257.09:14:38.79#ibcon#flushed, iclass 39, count 2 2006.257.09:14:38.79#ibcon#about to write, iclass 39, count 2 2006.257.09:14:38.79#ibcon#wrote, iclass 39, count 2 2006.257.09:14:38.79#ibcon#about to read 3, iclass 39, count 2 2006.257.09:14:38.81#ibcon#read 3, iclass 39, count 2 2006.257.09:14:38.81#ibcon#about to read 4, iclass 39, count 2 2006.257.09:14:38.81#ibcon#read 4, iclass 39, count 2 2006.257.09:14:38.81#ibcon#about to read 5, iclass 39, count 2 2006.257.09:14:38.81#ibcon#read 5, iclass 39, count 2 2006.257.09:14:38.81#ibcon#about to read 6, iclass 39, count 2 2006.257.09:14:38.81#ibcon#read 6, iclass 39, count 2 2006.257.09:14:38.81#ibcon#end of sib2, iclass 39, count 2 2006.257.09:14:38.81#ibcon#*mode == 0, iclass 39, count 2 2006.257.09:14:38.81#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.09:14:38.81#ibcon#[25=AT05-04\r\n] 2006.257.09:14:38.81#ibcon#*before write, iclass 39, count 2 2006.257.09:14:38.81#ibcon#enter sib2, iclass 39, count 2 2006.257.09:14:38.81#ibcon#flushed, iclass 39, count 2 2006.257.09:14:38.81#ibcon#about to write, iclass 39, count 2 2006.257.09:14:38.81#ibcon#wrote, iclass 39, count 2 2006.257.09:14:38.81#ibcon#about to read 3, iclass 39, count 2 2006.257.09:14:38.84#ibcon#read 3, iclass 39, count 2 2006.257.09:14:38.84#ibcon#about to read 4, iclass 39, count 2 2006.257.09:14:38.84#ibcon#read 4, iclass 39, count 2 2006.257.09:14:38.84#ibcon#about to read 5, iclass 39, count 2 2006.257.09:14:38.84#ibcon#read 5, iclass 39, count 2 2006.257.09:14:38.84#ibcon#about to read 6, iclass 39, count 2 2006.257.09:14:38.84#ibcon#read 6, iclass 39, count 2 2006.257.09:14:38.84#ibcon#end of sib2, iclass 39, count 2 2006.257.09:14:38.84#ibcon#*after write, iclass 39, count 2 2006.257.09:14:38.84#ibcon#*before return 0, iclass 39, count 2 2006.257.09:14:38.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:38.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:38.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.09:14:38.84#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:38.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:38.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:38.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:38.96#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:14:38.96#ibcon#first serial, iclass 39, count 0 2006.257.09:14:38.96#ibcon#enter sib2, iclass 39, count 0 2006.257.09:14:38.96#ibcon#flushed, iclass 39, count 0 2006.257.09:14:38.96#ibcon#about to write, iclass 39, count 0 2006.257.09:14:38.96#ibcon#wrote, iclass 39, count 0 2006.257.09:14:38.96#ibcon#about to read 3, iclass 39, count 0 2006.257.09:14:38.98#ibcon#read 3, iclass 39, count 0 2006.257.09:14:38.98#ibcon#about to read 4, iclass 39, count 0 2006.257.09:14:38.98#ibcon#read 4, iclass 39, count 0 2006.257.09:14:38.98#ibcon#about to read 5, iclass 39, count 0 2006.257.09:14:38.98#ibcon#read 5, iclass 39, count 0 2006.257.09:14:38.98#ibcon#about to read 6, iclass 39, count 0 2006.257.09:14:38.98#ibcon#read 6, iclass 39, count 0 2006.257.09:14:38.98#ibcon#end of sib2, iclass 39, count 0 2006.257.09:14:38.98#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:14:38.98#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:14:38.98#ibcon#[25=USB\r\n] 2006.257.09:14:38.98#ibcon#*before write, iclass 39, count 0 2006.257.09:14:38.98#ibcon#enter sib2, iclass 39, count 0 2006.257.09:14:38.98#ibcon#flushed, iclass 39, count 0 2006.257.09:14:38.98#ibcon#about to write, iclass 39, count 0 2006.257.09:14:38.98#ibcon#wrote, iclass 39, count 0 2006.257.09:14:38.98#ibcon#about to read 3, iclass 39, count 0 2006.257.09:14:39.01#ibcon#read 3, iclass 39, count 0 2006.257.09:14:39.01#ibcon#about to read 4, iclass 39, count 0 2006.257.09:14:39.01#ibcon#read 4, iclass 39, count 0 2006.257.09:14:39.01#ibcon#about to read 5, iclass 39, count 0 2006.257.09:14:39.01#ibcon#read 5, iclass 39, count 0 2006.257.09:14:39.01#ibcon#about to read 6, iclass 39, count 0 2006.257.09:14:39.01#ibcon#read 6, iclass 39, count 0 2006.257.09:14:39.01#ibcon#end of sib2, iclass 39, count 0 2006.257.09:14:39.01#ibcon#*after write, iclass 39, count 0 2006.257.09:14:39.01#ibcon#*before return 0, iclass 39, count 0 2006.257.09:14:39.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:39.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:39.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:14:39.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:14:39.01$vck44/valo=6,814.99 2006.257.09:14:39.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.09:14:39.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.09:14:39.01#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:39.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:39.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:39.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:39.01#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:14:39.01#ibcon#first serial, iclass 3, count 0 2006.257.09:14:39.01#ibcon#enter sib2, iclass 3, count 0 2006.257.09:14:39.01#ibcon#flushed, iclass 3, count 0 2006.257.09:14:39.01#ibcon#about to write, iclass 3, count 0 2006.257.09:14:39.01#ibcon#wrote, iclass 3, count 0 2006.257.09:14:39.01#ibcon#about to read 3, iclass 3, count 0 2006.257.09:14:39.03#ibcon#read 3, iclass 3, count 0 2006.257.09:14:39.03#ibcon#about to read 4, iclass 3, count 0 2006.257.09:14:39.03#ibcon#read 4, iclass 3, count 0 2006.257.09:14:39.03#ibcon#about to read 5, iclass 3, count 0 2006.257.09:14:39.03#ibcon#read 5, iclass 3, count 0 2006.257.09:14:39.03#ibcon#about to read 6, iclass 3, count 0 2006.257.09:14:39.03#ibcon#read 6, iclass 3, count 0 2006.257.09:14:39.03#ibcon#end of sib2, iclass 3, count 0 2006.257.09:14:39.03#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:14:39.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:14:39.03#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:14:39.03#ibcon#*before write, iclass 3, count 0 2006.257.09:14:39.03#ibcon#enter sib2, iclass 3, count 0 2006.257.09:14:39.03#ibcon#flushed, iclass 3, count 0 2006.257.09:14:39.03#ibcon#about to write, iclass 3, count 0 2006.257.09:14:39.03#ibcon#wrote, iclass 3, count 0 2006.257.09:14:39.03#ibcon#about to read 3, iclass 3, count 0 2006.257.09:14:39.07#ibcon#read 3, iclass 3, count 0 2006.257.09:14:39.07#ibcon#about to read 4, iclass 3, count 0 2006.257.09:14:39.07#ibcon#read 4, iclass 3, count 0 2006.257.09:14:39.07#ibcon#about to read 5, iclass 3, count 0 2006.257.09:14:39.07#ibcon#read 5, iclass 3, count 0 2006.257.09:14:39.07#ibcon#about to read 6, iclass 3, count 0 2006.257.09:14:39.07#ibcon#read 6, iclass 3, count 0 2006.257.09:14:39.07#ibcon#end of sib2, iclass 3, count 0 2006.257.09:14:39.07#ibcon#*after write, iclass 3, count 0 2006.257.09:14:39.07#ibcon#*before return 0, iclass 3, count 0 2006.257.09:14:39.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:39.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:39.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:14:39.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:14:39.07$vck44/va=6,4 2006.257.09:14:39.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.09:14:39.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.09:14:39.07#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:39.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:39.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:39.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:39.13#ibcon#enter wrdev, iclass 5, count 2 2006.257.09:14:39.13#ibcon#first serial, iclass 5, count 2 2006.257.09:14:39.13#ibcon#enter sib2, iclass 5, count 2 2006.257.09:14:39.13#ibcon#flushed, iclass 5, count 2 2006.257.09:14:39.13#ibcon#about to write, iclass 5, count 2 2006.257.09:14:39.13#ibcon#wrote, iclass 5, count 2 2006.257.09:14:39.13#ibcon#about to read 3, iclass 5, count 2 2006.257.09:14:39.15#ibcon#read 3, iclass 5, count 2 2006.257.09:14:39.15#ibcon#about to read 4, iclass 5, count 2 2006.257.09:14:39.15#ibcon#read 4, iclass 5, count 2 2006.257.09:14:39.15#ibcon#about to read 5, iclass 5, count 2 2006.257.09:14:39.15#ibcon#read 5, iclass 5, count 2 2006.257.09:14:39.15#ibcon#about to read 6, iclass 5, count 2 2006.257.09:14:39.15#ibcon#read 6, iclass 5, count 2 2006.257.09:14:39.15#ibcon#end of sib2, iclass 5, count 2 2006.257.09:14:39.15#ibcon#*mode == 0, iclass 5, count 2 2006.257.09:14:39.15#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.09:14:39.15#ibcon#[25=AT06-04\r\n] 2006.257.09:14:39.15#ibcon#*before write, iclass 5, count 2 2006.257.09:14:39.15#ibcon#enter sib2, iclass 5, count 2 2006.257.09:14:39.15#ibcon#flushed, iclass 5, count 2 2006.257.09:14:39.15#ibcon#about to write, iclass 5, count 2 2006.257.09:14:39.15#ibcon#wrote, iclass 5, count 2 2006.257.09:14:39.15#ibcon#about to read 3, iclass 5, count 2 2006.257.09:14:39.18#ibcon#read 3, iclass 5, count 2 2006.257.09:14:39.18#ibcon#about to read 4, iclass 5, count 2 2006.257.09:14:39.18#ibcon#read 4, iclass 5, count 2 2006.257.09:14:39.18#ibcon#about to read 5, iclass 5, count 2 2006.257.09:14:39.18#ibcon#read 5, iclass 5, count 2 2006.257.09:14:39.18#ibcon#about to read 6, iclass 5, count 2 2006.257.09:14:39.18#ibcon#read 6, iclass 5, count 2 2006.257.09:14:39.18#ibcon#end of sib2, iclass 5, count 2 2006.257.09:14:39.18#ibcon#*after write, iclass 5, count 2 2006.257.09:14:39.18#ibcon#*before return 0, iclass 5, count 2 2006.257.09:14:39.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:39.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:39.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.09:14:39.18#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:39.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:39.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:39.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:39.30#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:14:39.30#ibcon#first serial, iclass 5, count 0 2006.257.09:14:39.30#ibcon#enter sib2, iclass 5, count 0 2006.257.09:14:39.30#ibcon#flushed, iclass 5, count 0 2006.257.09:14:39.30#ibcon#about to write, iclass 5, count 0 2006.257.09:14:39.30#ibcon#wrote, iclass 5, count 0 2006.257.09:14:39.30#ibcon#about to read 3, iclass 5, count 0 2006.257.09:14:39.32#ibcon#read 3, iclass 5, count 0 2006.257.09:14:39.32#ibcon#about to read 4, iclass 5, count 0 2006.257.09:14:39.32#ibcon#read 4, iclass 5, count 0 2006.257.09:14:39.32#ibcon#about to read 5, iclass 5, count 0 2006.257.09:14:39.32#ibcon#read 5, iclass 5, count 0 2006.257.09:14:39.32#ibcon#about to read 6, iclass 5, count 0 2006.257.09:14:39.32#ibcon#read 6, iclass 5, count 0 2006.257.09:14:39.32#ibcon#end of sib2, iclass 5, count 0 2006.257.09:14:39.32#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:14:39.32#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:14:39.32#ibcon#[25=USB\r\n] 2006.257.09:14:39.32#ibcon#*before write, iclass 5, count 0 2006.257.09:14:39.32#ibcon#enter sib2, iclass 5, count 0 2006.257.09:14:39.32#ibcon#flushed, iclass 5, count 0 2006.257.09:14:39.32#ibcon#about to write, iclass 5, count 0 2006.257.09:14:39.32#ibcon#wrote, iclass 5, count 0 2006.257.09:14:39.32#ibcon#about to read 3, iclass 5, count 0 2006.257.09:14:39.35#ibcon#read 3, iclass 5, count 0 2006.257.09:14:39.35#ibcon#about to read 4, iclass 5, count 0 2006.257.09:14:39.35#ibcon#read 4, iclass 5, count 0 2006.257.09:14:39.35#ibcon#about to read 5, iclass 5, count 0 2006.257.09:14:39.35#ibcon#read 5, iclass 5, count 0 2006.257.09:14:39.35#ibcon#about to read 6, iclass 5, count 0 2006.257.09:14:39.35#ibcon#read 6, iclass 5, count 0 2006.257.09:14:39.35#ibcon#end of sib2, iclass 5, count 0 2006.257.09:14:39.35#ibcon#*after write, iclass 5, count 0 2006.257.09:14:39.35#ibcon#*before return 0, iclass 5, count 0 2006.257.09:14:39.35#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:39.35#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:39.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:14:39.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:14:39.35$vck44/valo=7,864.99 2006.257.09:14:39.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.09:14:39.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.09:14:39.35#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:39.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:39.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:39.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:39.35#ibcon#enter wrdev, iclass 7, count 0 2006.257.09:14:39.35#ibcon#first serial, iclass 7, count 0 2006.257.09:14:39.35#ibcon#enter sib2, iclass 7, count 0 2006.257.09:14:39.35#ibcon#flushed, iclass 7, count 0 2006.257.09:14:39.35#ibcon#about to write, iclass 7, count 0 2006.257.09:14:39.35#ibcon#wrote, iclass 7, count 0 2006.257.09:14:39.35#ibcon#about to read 3, iclass 7, count 0 2006.257.09:14:39.37#ibcon#read 3, iclass 7, count 0 2006.257.09:14:39.37#ibcon#about to read 4, iclass 7, count 0 2006.257.09:14:39.37#ibcon#read 4, iclass 7, count 0 2006.257.09:14:39.37#ibcon#about to read 5, iclass 7, count 0 2006.257.09:14:39.37#ibcon#read 5, iclass 7, count 0 2006.257.09:14:39.37#ibcon#about to read 6, iclass 7, count 0 2006.257.09:14:39.37#ibcon#read 6, iclass 7, count 0 2006.257.09:14:39.37#ibcon#end of sib2, iclass 7, count 0 2006.257.09:14:39.37#ibcon#*mode == 0, iclass 7, count 0 2006.257.09:14:39.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.09:14:39.37#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:14:39.37#ibcon#*before write, iclass 7, count 0 2006.257.09:14:39.37#ibcon#enter sib2, iclass 7, count 0 2006.257.09:14:39.37#ibcon#flushed, iclass 7, count 0 2006.257.09:14:39.37#ibcon#about to write, iclass 7, count 0 2006.257.09:14:39.37#ibcon#wrote, iclass 7, count 0 2006.257.09:14:39.37#ibcon#about to read 3, iclass 7, count 0 2006.257.09:14:39.41#ibcon#read 3, iclass 7, count 0 2006.257.09:14:39.41#ibcon#about to read 4, iclass 7, count 0 2006.257.09:14:39.41#ibcon#read 4, iclass 7, count 0 2006.257.09:14:39.41#ibcon#about to read 5, iclass 7, count 0 2006.257.09:14:39.41#ibcon#read 5, iclass 7, count 0 2006.257.09:14:39.41#ibcon#about to read 6, iclass 7, count 0 2006.257.09:14:39.41#ibcon#read 6, iclass 7, count 0 2006.257.09:14:39.41#ibcon#end of sib2, iclass 7, count 0 2006.257.09:14:39.41#ibcon#*after write, iclass 7, count 0 2006.257.09:14:39.41#ibcon#*before return 0, iclass 7, count 0 2006.257.09:14:39.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:39.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:39.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.09:14:39.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.09:14:39.41$vck44/va=7,4 2006.257.09:14:39.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.09:14:39.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.09:14:39.41#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:39.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:39.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:39.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:39.47#ibcon#enter wrdev, iclass 11, count 2 2006.257.09:14:39.47#ibcon#first serial, iclass 11, count 2 2006.257.09:14:39.47#ibcon#enter sib2, iclass 11, count 2 2006.257.09:14:39.47#ibcon#flushed, iclass 11, count 2 2006.257.09:14:39.47#ibcon#about to write, iclass 11, count 2 2006.257.09:14:39.47#ibcon#wrote, iclass 11, count 2 2006.257.09:14:39.47#ibcon#about to read 3, iclass 11, count 2 2006.257.09:14:39.49#ibcon#read 3, iclass 11, count 2 2006.257.09:14:39.49#ibcon#about to read 4, iclass 11, count 2 2006.257.09:14:39.49#ibcon#read 4, iclass 11, count 2 2006.257.09:14:39.49#ibcon#about to read 5, iclass 11, count 2 2006.257.09:14:39.49#ibcon#read 5, iclass 11, count 2 2006.257.09:14:39.49#ibcon#about to read 6, iclass 11, count 2 2006.257.09:14:39.49#ibcon#read 6, iclass 11, count 2 2006.257.09:14:39.49#ibcon#end of sib2, iclass 11, count 2 2006.257.09:14:39.49#ibcon#*mode == 0, iclass 11, count 2 2006.257.09:14:39.49#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.09:14:39.49#ibcon#[25=AT07-04\r\n] 2006.257.09:14:39.49#ibcon#*before write, iclass 11, count 2 2006.257.09:14:39.49#ibcon#enter sib2, iclass 11, count 2 2006.257.09:14:39.49#ibcon#flushed, iclass 11, count 2 2006.257.09:14:39.49#ibcon#about to write, iclass 11, count 2 2006.257.09:14:39.49#ibcon#wrote, iclass 11, count 2 2006.257.09:14:39.49#ibcon#about to read 3, iclass 11, count 2 2006.257.09:14:39.52#ibcon#read 3, iclass 11, count 2 2006.257.09:14:39.52#ibcon#about to read 4, iclass 11, count 2 2006.257.09:14:39.52#ibcon#read 4, iclass 11, count 2 2006.257.09:14:39.54#ibcon#about to read 5, iclass 11, count 2 2006.257.09:14:39.54#ibcon#read 5, iclass 11, count 2 2006.257.09:14:39.54#ibcon#about to read 6, iclass 11, count 2 2006.257.09:14:39.54#ibcon#read 6, iclass 11, count 2 2006.257.09:14:39.54#ibcon#end of sib2, iclass 11, count 2 2006.257.09:14:39.54#ibcon#*after write, iclass 11, count 2 2006.257.09:14:39.54#ibcon#*before return 0, iclass 11, count 2 2006.257.09:14:39.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:39.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:39.54#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.09:14:39.54#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:39.54#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:39.66#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:39.66#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:39.66#ibcon#enter wrdev, iclass 11, count 0 2006.257.09:14:39.66#ibcon#first serial, iclass 11, count 0 2006.257.09:14:39.66#ibcon#enter sib2, iclass 11, count 0 2006.257.09:14:39.66#ibcon#flushed, iclass 11, count 0 2006.257.09:14:39.66#ibcon#about to write, iclass 11, count 0 2006.257.09:14:39.66#ibcon#wrote, iclass 11, count 0 2006.257.09:14:39.66#ibcon#about to read 3, iclass 11, count 0 2006.257.09:14:39.68#ibcon#read 3, iclass 11, count 0 2006.257.09:14:39.68#ibcon#about to read 4, iclass 11, count 0 2006.257.09:14:39.68#ibcon#read 4, iclass 11, count 0 2006.257.09:14:39.68#ibcon#about to read 5, iclass 11, count 0 2006.257.09:14:39.68#ibcon#read 5, iclass 11, count 0 2006.257.09:14:39.68#ibcon#about to read 6, iclass 11, count 0 2006.257.09:14:39.68#ibcon#read 6, iclass 11, count 0 2006.257.09:14:39.68#ibcon#end of sib2, iclass 11, count 0 2006.257.09:14:39.68#ibcon#*mode == 0, iclass 11, count 0 2006.257.09:14:39.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.09:14:39.68#ibcon#[25=USB\r\n] 2006.257.09:14:39.68#ibcon#*before write, iclass 11, count 0 2006.257.09:14:39.68#ibcon#enter sib2, iclass 11, count 0 2006.257.09:14:39.68#ibcon#flushed, iclass 11, count 0 2006.257.09:14:39.68#ibcon#about to write, iclass 11, count 0 2006.257.09:14:39.68#ibcon#wrote, iclass 11, count 0 2006.257.09:14:39.68#ibcon#about to read 3, iclass 11, count 0 2006.257.09:14:39.71#ibcon#read 3, iclass 11, count 0 2006.257.09:14:39.71#ibcon#about to read 4, iclass 11, count 0 2006.257.09:14:39.71#ibcon#read 4, iclass 11, count 0 2006.257.09:14:39.71#ibcon#about to read 5, iclass 11, count 0 2006.257.09:14:39.71#ibcon#read 5, iclass 11, count 0 2006.257.09:14:39.71#ibcon#about to read 6, iclass 11, count 0 2006.257.09:14:39.71#ibcon#read 6, iclass 11, count 0 2006.257.09:14:39.71#ibcon#end of sib2, iclass 11, count 0 2006.257.09:14:39.71#ibcon#*after write, iclass 11, count 0 2006.257.09:14:39.71#ibcon#*before return 0, iclass 11, count 0 2006.257.09:14:39.71#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:39.71#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:39.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.09:14:39.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.09:14:39.71$vck44/valo=8,884.99 2006.257.09:14:39.71#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.09:14:39.71#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.09:14:39.71#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:39.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:39.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:39.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:39.71#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:14:39.71#ibcon#first serial, iclass 13, count 0 2006.257.09:14:39.71#ibcon#enter sib2, iclass 13, count 0 2006.257.09:14:39.71#ibcon#flushed, iclass 13, count 0 2006.257.09:14:39.71#ibcon#about to write, iclass 13, count 0 2006.257.09:14:39.71#ibcon#wrote, iclass 13, count 0 2006.257.09:14:39.71#ibcon#about to read 3, iclass 13, count 0 2006.257.09:14:39.73#ibcon#read 3, iclass 13, count 0 2006.257.09:14:39.73#ibcon#about to read 4, iclass 13, count 0 2006.257.09:14:39.73#ibcon#read 4, iclass 13, count 0 2006.257.09:14:39.73#ibcon#about to read 5, iclass 13, count 0 2006.257.09:14:39.73#ibcon#read 5, iclass 13, count 0 2006.257.09:14:39.73#ibcon#about to read 6, iclass 13, count 0 2006.257.09:14:39.73#ibcon#read 6, iclass 13, count 0 2006.257.09:14:39.73#ibcon#end of sib2, iclass 13, count 0 2006.257.09:14:39.73#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:14:39.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:14:39.73#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:14:39.73#ibcon#*before write, iclass 13, count 0 2006.257.09:14:39.73#ibcon#enter sib2, iclass 13, count 0 2006.257.09:14:39.73#ibcon#flushed, iclass 13, count 0 2006.257.09:14:39.73#ibcon#about to write, iclass 13, count 0 2006.257.09:14:39.73#ibcon#wrote, iclass 13, count 0 2006.257.09:14:39.73#ibcon#about to read 3, iclass 13, count 0 2006.257.09:14:39.77#ibcon#read 3, iclass 13, count 0 2006.257.09:14:39.77#ibcon#about to read 4, iclass 13, count 0 2006.257.09:14:39.77#ibcon#read 4, iclass 13, count 0 2006.257.09:14:39.77#ibcon#about to read 5, iclass 13, count 0 2006.257.09:14:39.77#ibcon#read 5, iclass 13, count 0 2006.257.09:14:39.77#ibcon#about to read 6, iclass 13, count 0 2006.257.09:14:39.77#ibcon#read 6, iclass 13, count 0 2006.257.09:14:39.77#ibcon#end of sib2, iclass 13, count 0 2006.257.09:14:39.77#ibcon#*after write, iclass 13, count 0 2006.257.09:14:39.77#ibcon#*before return 0, iclass 13, count 0 2006.257.09:14:39.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:39.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:39.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:14:39.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:14:39.77$vck44/va=8,4 2006.257.09:14:39.77#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.09:14:39.77#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.09:14:39.77#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:39.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:14:39.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:14:39.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:14:39.83#ibcon#enter wrdev, iclass 15, count 2 2006.257.09:14:39.83#ibcon#first serial, iclass 15, count 2 2006.257.09:14:39.83#ibcon#enter sib2, iclass 15, count 2 2006.257.09:14:39.83#ibcon#flushed, iclass 15, count 2 2006.257.09:14:39.83#ibcon#about to write, iclass 15, count 2 2006.257.09:14:39.83#ibcon#wrote, iclass 15, count 2 2006.257.09:14:39.83#ibcon#about to read 3, iclass 15, count 2 2006.257.09:14:39.85#ibcon#read 3, iclass 15, count 2 2006.257.09:14:39.85#ibcon#about to read 4, iclass 15, count 2 2006.257.09:14:39.85#ibcon#read 4, iclass 15, count 2 2006.257.09:14:39.85#ibcon#about to read 5, iclass 15, count 2 2006.257.09:14:39.85#ibcon#read 5, iclass 15, count 2 2006.257.09:14:39.85#ibcon#about to read 6, iclass 15, count 2 2006.257.09:14:39.85#ibcon#read 6, iclass 15, count 2 2006.257.09:14:39.85#ibcon#end of sib2, iclass 15, count 2 2006.257.09:14:39.85#ibcon#*mode == 0, iclass 15, count 2 2006.257.09:14:39.85#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.09:14:39.85#ibcon#[25=AT08-04\r\n] 2006.257.09:14:39.85#ibcon#*before write, iclass 15, count 2 2006.257.09:14:39.85#ibcon#enter sib2, iclass 15, count 2 2006.257.09:14:39.85#ibcon#flushed, iclass 15, count 2 2006.257.09:14:39.85#ibcon#about to write, iclass 15, count 2 2006.257.09:14:39.85#ibcon#wrote, iclass 15, count 2 2006.257.09:14:39.85#ibcon#about to read 3, iclass 15, count 2 2006.257.09:14:39.88#ibcon#read 3, iclass 15, count 2 2006.257.09:14:39.88#ibcon#about to read 4, iclass 15, count 2 2006.257.09:14:39.88#ibcon#read 4, iclass 15, count 2 2006.257.09:14:39.88#ibcon#about to read 5, iclass 15, count 2 2006.257.09:14:39.88#ibcon#read 5, iclass 15, count 2 2006.257.09:14:39.88#ibcon#about to read 6, iclass 15, count 2 2006.257.09:14:39.88#ibcon#read 6, iclass 15, count 2 2006.257.09:14:39.88#ibcon#end of sib2, iclass 15, count 2 2006.257.09:14:39.88#ibcon#*after write, iclass 15, count 2 2006.257.09:14:39.88#ibcon#*before return 0, iclass 15, count 2 2006.257.09:14:39.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:14:39.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:14:39.88#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.09:14:39.88#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:39.88#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:14:40.00#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:14:40.00#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:14:40.00#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:14:40.00#ibcon#first serial, iclass 15, count 0 2006.257.09:14:40.00#ibcon#enter sib2, iclass 15, count 0 2006.257.09:14:40.00#ibcon#flushed, iclass 15, count 0 2006.257.09:14:40.00#ibcon#about to write, iclass 15, count 0 2006.257.09:14:40.00#ibcon#wrote, iclass 15, count 0 2006.257.09:14:40.00#ibcon#about to read 3, iclass 15, count 0 2006.257.09:14:40.02#ibcon#read 3, iclass 15, count 0 2006.257.09:14:40.02#ibcon#about to read 4, iclass 15, count 0 2006.257.09:14:40.02#ibcon#read 4, iclass 15, count 0 2006.257.09:14:40.02#ibcon#about to read 5, iclass 15, count 0 2006.257.09:14:40.02#ibcon#read 5, iclass 15, count 0 2006.257.09:14:40.02#ibcon#about to read 6, iclass 15, count 0 2006.257.09:14:40.02#ibcon#read 6, iclass 15, count 0 2006.257.09:14:40.02#ibcon#end of sib2, iclass 15, count 0 2006.257.09:14:40.02#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:14:40.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:14:40.02#ibcon#[25=USB\r\n] 2006.257.09:14:40.02#ibcon#*before write, iclass 15, count 0 2006.257.09:14:40.02#ibcon#enter sib2, iclass 15, count 0 2006.257.09:14:40.02#ibcon#flushed, iclass 15, count 0 2006.257.09:14:40.02#ibcon#about to write, iclass 15, count 0 2006.257.09:14:40.02#ibcon#wrote, iclass 15, count 0 2006.257.09:14:40.02#ibcon#about to read 3, iclass 15, count 0 2006.257.09:14:40.05#ibcon#read 3, iclass 15, count 0 2006.257.09:14:40.05#ibcon#about to read 4, iclass 15, count 0 2006.257.09:14:40.05#ibcon#read 4, iclass 15, count 0 2006.257.09:14:40.05#ibcon#about to read 5, iclass 15, count 0 2006.257.09:14:40.05#ibcon#read 5, iclass 15, count 0 2006.257.09:14:40.05#ibcon#about to read 6, iclass 15, count 0 2006.257.09:14:40.05#ibcon#read 6, iclass 15, count 0 2006.257.09:14:40.05#ibcon#end of sib2, iclass 15, count 0 2006.257.09:14:40.05#ibcon#*after write, iclass 15, count 0 2006.257.09:14:40.05#ibcon#*before return 0, iclass 15, count 0 2006.257.09:14:40.05#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:14:40.05#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:14:40.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:14:40.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:14:40.05$vck44/vblo=1,629.99 2006.257.09:14:40.05#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.09:14:40.05#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.09:14:40.05#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:40.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:14:40.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:14:40.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:14:40.05#ibcon#enter wrdev, iclass 17, count 0 2006.257.09:14:40.05#ibcon#first serial, iclass 17, count 0 2006.257.09:14:40.05#ibcon#enter sib2, iclass 17, count 0 2006.257.09:14:40.05#ibcon#flushed, iclass 17, count 0 2006.257.09:14:40.05#ibcon#about to write, iclass 17, count 0 2006.257.09:14:40.05#ibcon#wrote, iclass 17, count 0 2006.257.09:14:40.05#ibcon#about to read 3, iclass 17, count 0 2006.257.09:14:40.07#ibcon#read 3, iclass 17, count 0 2006.257.09:14:40.07#ibcon#about to read 4, iclass 17, count 0 2006.257.09:14:40.07#ibcon#read 4, iclass 17, count 0 2006.257.09:14:40.07#ibcon#about to read 5, iclass 17, count 0 2006.257.09:14:40.07#ibcon#read 5, iclass 17, count 0 2006.257.09:14:40.07#ibcon#about to read 6, iclass 17, count 0 2006.257.09:14:40.07#ibcon#read 6, iclass 17, count 0 2006.257.09:14:40.07#ibcon#end of sib2, iclass 17, count 0 2006.257.09:14:40.07#ibcon#*mode == 0, iclass 17, count 0 2006.257.09:14:40.07#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.09:14:40.07#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:14:40.07#ibcon#*before write, iclass 17, count 0 2006.257.09:14:40.07#ibcon#enter sib2, iclass 17, count 0 2006.257.09:14:40.07#ibcon#flushed, iclass 17, count 0 2006.257.09:14:40.07#ibcon#about to write, iclass 17, count 0 2006.257.09:14:40.07#ibcon#wrote, iclass 17, count 0 2006.257.09:14:40.07#ibcon#about to read 3, iclass 17, count 0 2006.257.09:14:40.11#ibcon#read 3, iclass 17, count 0 2006.257.09:14:40.11#ibcon#about to read 4, iclass 17, count 0 2006.257.09:14:40.11#ibcon#read 4, iclass 17, count 0 2006.257.09:14:40.11#ibcon#about to read 5, iclass 17, count 0 2006.257.09:14:40.11#ibcon#read 5, iclass 17, count 0 2006.257.09:14:40.11#ibcon#about to read 6, iclass 17, count 0 2006.257.09:14:40.11#ibcon#read 6, iclass 17, count 0 2006.257.09:14:40.11#ibcon#end of sib2, iclass 17, count 0 2006.257.09:14:40.11#ibcon#*after write, iclass 17, count 0 2006.257.09:14:40.11#ibcon#*before return 0, iclass 17, count 0 2006.257.09:14:40.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:14:40.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:14:40.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.09:14:40.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.09:14:40.11$vck44/vb=1,4 2006.257.09:14:40.11#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.09:14:40.11#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.09:14:40.11#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:40.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:14:40.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:14:40.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:14:40.11#ibcon#enter wrdev, iclass 19, count 2 2006.257.09:14:40.11#ibcon#first serial, iclass 19, count 2 2006.257.09:14:40.11#ibcon#enter sib2, iclass 19, count 2 2006.257.09:14:40.11#ibcon#flushed, iclass 19, count 2 2006.257.09:14:40.11#ibcon#about to write, iclass 19, count 2 2006.257.09:14:40.11#ibcon#wrote, iclass 19, count 2 2006.257.09:14:40.11#ibcon#about to read 3, iclass 19, count 2 2006.257.09:14:40.13#ibcon#read 3, iclass 19, count 2 2006.257.09:14:40.13#ibcon#about to read 4, iclass 19, count 2 2006.257.09:14:40.13#ibcon#read 4, iclass 19, count 2 2006.257.09:14:40.13#ibcon#about to read 5, iclass 19, count 2 2006.257.09:14:40.13#ibcon#read 5, iclass 19, count 2 2006.257.09:14:40.13#ibcon#about to read 6, iclass 19, count 2 2006.257.09:14:40.13#ibcon#read 6, iclass 19, count 2 2006.257.09:14:40.13#ibcon#end of sib2, iclass 19, count 2 2006.257.09:14:40.13#ibcon#*mode == 0, iclass 19, count 2 2006.257.09:14:40.13#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.09:14:40.13#ibcon#[27=AT01-04\r\n] 2006.257.09:14:40.13#ibcon#*before write, iclass 19, count 2 2006.257.09:14:40.13#ibcon#enter sib2, iclass 19, count 2 2006.257.09:14:40.13#ibcon#flushed, iclass 19, count 2 2006.257.09:14:40.13#ibcon#about to write, iclass 19, count 2 2006.257.09:14:40.13#ibcon#wrote, iclass 19, count 2 2006.257.09:14:40.13#ibcon#about to read 3, iclass 19, count 2 2006.257.09:14:40.16#ibcon#read 3, iclass 19, count 2 2006.257.09:14:40.16#ibcon#about to read 4, iclass 19, count 2 2006.257.09:14:40.16#ibcon#read 4, iclass 19, count 2 2006.257.09:14:40.16#ibcon#about to read 5, iclass 19, count 2 2006.257.09:14:40.16#ibcon#read 5, iclass 19, count 2 2006.257.09:14:40.16#ibcon#about to read 6, iclass 19, count 2 2006.257.09:14:40.16#ibcon#read 6, iclass 19, count 2 2006.257.09:14:40.16#ibcon#end of sib2, iclass 19, count 2 2006.257.09:14:40.16#ibcon#*after write, iclass 19, count 2 2006.257.09:14:40.16#ibcon#*before return 0, iclass 19, count 2 2006.257.09:14:40.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:14:40.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:14:40.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.09:14:40.16#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:40.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:14:40.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:14:40.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:14:40.28#ibcon#enter wrdev, iclass 19, count 0 2006.257.09:14:40.28#ibcon#first serial, iclass 19, count 0 2006.257.09:14:40.28#ibcon#enter sib2, iclass 19, count 0 2006.257.09:14:40.28#ibcon#flushed, iclass 19, count 0 2006.257.09:14:40.28#ibcon#about to write, iclass 19, count 0 2006.257.09:14:40.28#ibcon#wrote, iclass 19, count 0 2006.257.09:14:40.28#ibcon#about to read 3, iclass 19, count 0 2006.257.09:14:40.30#ibcon#read 3, iclass 19, count 0 2006.257.09:14:40.30#ibcon#about to read 4, iclass 19, count 0 2006.257.09:14:40.30#ibcon#read 4, iclass 19, count 0 2006.257.09:14:40.30#ibcon#about to read 5, iclass 19, count 0 2006.257.09:14:40.30#ibcon#read 5, iclass 19, count 0 2006.257.09:14:40.30#ibcon#about to read 6, iclass 19, count 0 2006.257.09:14:40.30#ibcon#read 6, iclass 19, count 0 2006.257.09:14:40.30#ibcon#end of sib2, iclass 19, count 0 2006.257.09:14:40.30#ibcon#*mode == 0, iclass 19, count 0 2006.257.09:14:40.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.09:14:40.30#ibcon#[27=USB\r\n] 2006.257.09:14:40.30#ibcon#*before write, iclass 19, count 0 2006.257.09:14:40.30#ibcon#enter sib2, iclass 19, count 0 2006.257.09:14:40.30#ibcon#flushed, iclass 19, count 0 2006.257.09:14:40.30#ibcon#about to write, iclass 19, count 0 2006.257.09:14:40.30#ibcon#wrote, iclass 19, count 0 2006.257.09:14:40.30#ibcon#about to read 3, iclass 19, count 0 2006.257.09:14:40.33#ibcon#read 3, iclass 19, count 0 2006.257.09:14:40.33#ibcon#about to read 4, iclass 19, count 0 2006.257.09:14:40.33#ibcon#read 4, iclass 19, count 0 2006.257.09:14:40.33#ibcon#about to read 5, iclass 19, count 0 2006.257.09:14:40.33#ibcon#read 5, iclass 19, count 0 2006.257.09:14:40.33#ibcon#about to read 6, iclass 19, count 0 2006.257.09:14:40.33#ibcon#read 6, iclass 19, count 0 2006.257.09:14:40.33#ibcon#end of sib2, iclass 19, count 0 2006.257.09:14:40.33#ibcon#*after write, iclass 19, count 0 2006.257.09:14:40.33#ibcon#*before return 0, iclass 19, count 0 2006.257.09:14:40.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:14:40.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:14:40.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.09:14:40.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.09:14:40.33$vck44/vblo=2,634.99 2006.257.09:14:40.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.09:14:40.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.09:14:40.33#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:40.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:40.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:40.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:40.33#ibcon#enter wrdev, iclass 21, count 0 2006.257.09:14:40.33#ibcon#first serial, iclass 21, count 0 2006.257.09:14:40.33#ibcon#enter sib2, iclass 21, count 0 2006.257.09:14:40.33#ibcon#flushed, iclass 21, count 0 2006.257.09:14:40.33#ibcon#about to write, iclass 21, count 0 2006.257.09:14:40.33#ibcon#wrote, iclass 21, count 0 2006.257.09:14:40.33#ibcon#about to read 3, iclass 21, count 0 2006.257.09:14:40.35#ibcon#read 3, iclass 21, count 0 2006.257.09:14:40.35#ibcon#about to read 4, iclass 21, count 0 2006.257.09:14:40.35#ibcon#read 4, iclass 21, count 0 2006.257.09:14:40.35#ibcon#about to read 5, iclass 21, count 0 2006.257.09:14:40.35#ibcon#read 5, iclass 21, count 0 2006.257.09:14:40.35#ibcon#about to read 6, iclass 21, count 0 2006.257.09:14:40.35#ibcon#read 6, iclass 21, count 0 2006.257.09:14:40.35#ibcon#end of sib2, iclass 21, count 0 2006.257.09:14:40.35#ibcon#*mode == 0, iclass 21, count 0 2006.257.09:14:40.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.09:14:40.35#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:14:40.35#ibcon#*before write, iclass 21, count 0 2006.257.09:14:40.35#ibcon#enter sib2, iclass 21, count 0 2006.257.09:14:40.35#ibcon#flushed, iclass 21, count 0 2006.257.09:14:40.35#ibcon#about to write, iclass 21, count 0 2006.257.09:14:40.35#ibcon#wrote, iclass 21, count 0 2006.257.09:14:40.35#ibcon#about to read 3, iclass 21, count 0 2006.257.09:14:40.39#ibcon#read 3, iclass 21, count 0 2006.257.09:14:40.39#ibcon#about to read 4, iclass 21, count 0 2006.257.09:14:40.39#ibcon#read 4, iclass 21, count 0 2006.257.09:14:40.39#ibcon#about to read 5, iclass 21, count 0 2006.257.09:14:40.39#ibcon#read 5, iclass 21, count 0 2006.257.09:14:40.39#ibcon#about to read 6, iclass 21, count 0 2006.257.09:14:40.39#ibcon#read 6, iclass 21, count 0 2006.257.09:14:40.39#ibcon#end of sib2, iclass 21, count 0 2006.257.09:14:40.39#ibcon#*after write, iclass 21, count 0 2006.257.09:14:40.39#ibcon#*before return 0, iclass 21, count 0 2006.257.09:14:40.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:40.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:14:40.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.09:14:40.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.09:14:40.39$vck44/vb=2,5 2006.257.09:14:40.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.09:14:40.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.09:14:40.39#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:40.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:40.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:40.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:40.45#ibcon#enter wrdev, iclass 23, count 2 2006.257.09:14:40.45#ibcon#first serial, iclass 23, count 2 2006.257.09:14:40.45#ibcon#enter sib2, iclass 23, count 2 2006.257.09:14:40.45#ibcon#flushed, iclass 23, count 2 2006.257.09:14:40.45#ibcon#about to write, iclass 23, count 2 2006.257.09:14:40.45#ibcon#wrote, iclass 23, count 2 2006.257.09:14:40.45#ibcon#about to read 3, iclass 23, count 2 2006.257.09:14:40.47#ibcon#read 3, iclass 23, count 2 2006.257.09:14:40.47#ibcon#about to read 4, iclass 23, count 2 2006.257.09:14:40.47#ibcon#read 4, iclass 23, count 2 2006.257.09:14:40.47#ibcon#about to read 5, iclass 23, count 2 2006.257.09:14:40.47#ibcon#read 5, iclass 23, count 2 2006.257.09:14:40.47#ibcon#about to read 6, iclass 23, count 2 2006.257.09:14:40.47#ibcon#read 6, iclass 23, count 2 2006.257.09:14:40.47#ibcon#end of sib2, iclass 23, count 2 2006.257.09:14:40.47#ibcon#*mode == 0, iclass 23, count 2 2006.257.09:14:40.47#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.09:14:40.47#ibcon#[27=AT02-05\r\n] 2006.257.09:14:40.47#ibcon#*before write, iclass 23, count 2 2006.257.09:14:40.47#ibcon#enter sib2, iclass 23, count 2 2006.257.09:14:40.47#ibcon#flushed, iclass 23, count 2 2006.257.09:14:40.47#ibcon#about to write, iclass 23, count 2 2006.257.09:14:40.47#ibcon#wrote, iclass 23, count 2 2006.257.09:14:40.47#ibcon#about to read 3, iclass 23, count 2 2006.257.09:14:40.54#ibcon#read 3, iclass 23, count 2 2006.257.09:14:40.54#ibcon#about to read 4, iclass 23, count 2 2006.257.09:14:40.54#ibcon#read 4, iclass 23, count 2 2006.257.09:14:40.54#ibcon#about to read 5, iclass 23, count 2 2006.257.09:14:40.54#ibcon#read 5, iclass 23, count 2 2006.257.09:14:40.54#ibcon#about to read 6, iclass 23, count 2 2006.257.09:14:40.55#ibcon#read 6, iclass 23, count 2 2006.257.09:14:40.55#ibcon#end of sib2, iclass 23, count 2 2006.257.09:14:40.55#ibcon#*after write, iclass 23, count 2 2006.257.09:14:40.55#ibcon#*before return 0, iclass 23, count 2 2006.257.09:14:40.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:40.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:14:40.55#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.09:14:40.55#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:40.55#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:40.66#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:40.66#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:40.66#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:14:40.66#ibcon#first serial, iclass 23, count 0 2006.257.09:14:40.66#ibcon#enter sib2, iclass 23, count 0 2006.257.09:14:40.66#ibcon#flushed, iclass 23, count 0 2006.257.09:14:40.66#ibcon#about to write, iclass 23, count 0 2006.257.09:14:40.66#ibcon#wrote, iclass 23, count 0 2006.257.09:14:40.66#ibcon#about to read 3, iclass 23, count 0 2006.257.09:14:40.68#ibcon#read 3, iclass 23, count 0 2006.257.09:14:40.68#ibcon#about to read 4, iclass 23, count 0 2006.257.09:14:40.68#ibcon#read 4, iclass 23, count 0 2006.257.09:14:40.68#ibcon#about to read 5, iclass 23, count 0 2006.257.09:14:40.68#ibcon#read 5, iclass 23, count 0 2006.257.09:14:40.68#ibcon#about to read 6, iclass 23, count 0 2006.257.09:14:40.68#ibcon#read 6, iclass 23, count 0 2006.257.09:14:40.68#ibcon#end of sib2, iclass 23, count 0 2006.257.09:14:40.68#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:14:40.68#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:14:40.68#ibcon#[27=USB\r\n] 2006.257.09:14:40.68#ibcon#*before write, iclass 23, count 0 2006.257.09:14:40.68#ibcon#enter sib2, iclass 23, count 0 2006.257.09:14:40.68#ibcon#flushed, iclass 23, count 0 2006.257.09:14:40.68#ibcon#about to write, iclass 23, count 0 2006.257.09:14:40.68#ibcon#wrote, iclass 23, count 0 2006.257.09:14:40.68#ibcon#about to read 3, iclass 23, count 0 2006.257.09:14:40.71#ibcon#read 3, iclass 23, count 0 2006.257.09:14:40.71#ibcon#about to read 4, iclass 23, count 0 2006.257.09:14:40.71#ibcon#read 4, iclass 23, count 0 2006.257.09:14:40.71#ibcon#about to read 5, iclass 23, count 0 2006.257.09:14:40.71#ibcon#read 5, iclass 23, count 0 2006.257.09:14:40.71#ibcon#about to read 6, iclass 23, count 0 2006.257.09:14:40.71#ibcon#read 6, iclass 23, count 0 2006.257.09:14:40.71#ibcon#end of sib2, iclass 23, count 0 2006.257.09:14:40.71#ibcon#*after write, iclass 23, count 0 2006.257.09:14:40.71#ibcon#*before return 0, iclass 23, count 0 2006.257.09:14:40.71#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:40.71#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:14:40.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:14:40.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:14:40.71$vck44/vblo=3,649.99 2006.257.09:14:40.71#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.09:14:40.71#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.09:14:40.71#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:40.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:40.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:40.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:40.71#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:14:40.71#ibcon#first serial, iclass 25, count 0 2006.257.09:14:40.71#ibcon#enter sib2, iclass 25, count 0 2006.257.09:14:40.71#ibcon#flushed, iclass 25, count 0 2006.257.09:14:40.71#ibcon#about to write, iclass 25, count 0 2006.257.09:14:40.71#ibcon#wrote, iclass 25, count 0 2006.257.09:14:40.71#ibcon#about to read 3, iclass 25, count 0 2006.257.09:14:40.73#ibcon#read 3, iclass 25, count 0 2006.257.09:14:40.73#ibcon#about to read 4, iclass 25, count 0 2006.257.09:14:40.73#ibcon#read 4, iclass 25, count 0 2006.257.09:14:40.73#ibcon#about to read 5, iclass 25, count 0 2006.257.09:14:40.73#ibcon#read 5, iclass 25, count 0 2006.257.09:14:40.73#ibcon#about to read 6, iclass 25, count 0 2006.257.09:14:40.73#ibcon#read 6, iclass 25, count 0 2006.257.09:14:40.73#ibcon#end of sib2, iclass 25, count 0 2006.257.09:14:40.73#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:14:40.73#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:14:40.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:14:40.73#ibcon#*before write, iclass 25, count 0 2006.257.09:14:40.73#ibcon#enter sib2, iclass 25, count 0 2006.257.09:14:40.73#ibcon#flushed, iclass 25, count 0 2006.257.09:14:40.73#ibcon#about to write, iclass 25, count 0 2006.257.09:14:40.73#ibcon#wrote, iclass 25, count 0 2006.257.09:14:40.73#ibcon#about to read 3, iclass 25, count 0 2006.257.09:14:40.77#ibcon#read 3, iclass 25, count 0 2006.257.09:14:40.77#ibcon#about to read 4, iclass 25, count 0 2006.257.09:14:40.77#ibcon#read 4, iclass 25, count 0 2006.257.09:14:40.77#ibcon#about to read 5, iclass 25, count 0 2006.257.09:14:40.77#ibcon#read 5, iclass 25, count 0 2006.257.09:14:40.77#ibcon#about to read 6, iclass 25, count 0 2006.257.09:14:40.77#ibcon#read 6, iclass 25, count 0 2006.257.09:14:40.77#ibcon#end of sib2, iclass 25, count 0 2006.257.09:14:40.77#ibcon#*after write, iclass 25, count 0 2006.257.09:14:40.77#ibcon#*before return 0, iclass 25, count 0 2006.257.09:14:40.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:40.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:14:40.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:14:40.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:14:40.77$vck44/vb=3,4 2006.257.09:14:40.77#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.09:14:40.77#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.09:14:40.77#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:40.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:40.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:40.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:40.83#ibcon#enter wrdev, iclass 27, count 2 2006.257.09:14:40.83#ibcon#first serial, iclass 27, count 2 2006.257.09:14:40.83#ibcon#enter sib2, iclass 27, count 2 2006.257.09:14:40.83#ibcon#flushed, iclass 27, count 2 2006.257.09:14:40.83#ibcon#about to write, iclass 27, count 2 2006.257.09:14:40.83#ibcon#wrote, iclass 27, count 2 2006.257.09:14:40.83#ibcon#about to read 3, iclass 27, count 2 2006.257.09:14:40.85#ibcon#read 3, iclass 27, count 2 2006.257.09:14:40.85#ibcon#about to read 4, iclass 27, count 2 2006.257.09:14:40.85#ibcon#read 4, iclass 27, count 2 2006.257.09:14:40.85#ibcon#about to read 5, iclass 27, count 2 2006.257.09:14:40.85#ibcon#read 5, iclass 27, count 2 2006.257.09:14:40.85#ibcon#about to read 6, iclass 27, count 2 2006.257.09:14:40.85#ibcon#read 6, iclass 27, count 2 2006.257.09:14:40.85#ibcon#end of sib2, iclass 27, count 2 2006.257.09:14:40.85#ibcon#*mode == 0, iclass 27, count 2 2006.257.09:14:40.85#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.09:14:40.85#ibcon#[27=AT03-04\r\n] 2006.257.09:14:40.85#ibcon#*before write, iclass 27, count 2 2006.257.09:14:40.85#ibcon#enter sib2, iclass 27, count 2 2006.257.09:14:40.85#ibcon#flushed, iclass 27, count 2 2006.257.09:14:40.85#ibcon#about to write, iclass 27, count 2 2006.257.09:14:40.85#ibcon#wrote, iclass 27, count 2 2006.257.09:14:40.85#ibcon#about to read 3, iclass 27, count 2 2006.257.09:14:40.88#ibcon#read 3, iclass 27, count 2 2006.257.09:14:40.88#ibcon#about to read 4, iclass 27, count 2 2006.257.09:14:40.88#ibcon#read 4, iclass 27, count 2 2006.257.09:14:40.88#ibcon#about to read 5, iclass 27, count 2 2006.257.09:14:40.88#ibcon#read 5, iclass 27, count 2 2006.257.09:14:40.88#ibcon#about to read 6, iclass 27, count 2 2006.257.09:14:40.88#ibcon#read 6, iclass 27, count 2 2006.257.09:14:40.88#ibcon#end of sib2, iclass 27, count 2 2006.257.09:14:40.88#ibcon#*after write, iclass 27, count 2 2006.257.09:14:40.88#ibcon#*before return 0, iclass 27, count 2 2006.257.09:14:40.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:40.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:14:40.88#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.09:14:40.88#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:40.88#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:41.00#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:41.00#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:41.00#ibcon#enter wrdev, iclass 27, count 0 2006.257.09:14:41.00#ibcon#first serial, iclass 27, count 0 2006.257.09:14:41.00#ibcon#enter sib2, iclass 27, count 0 2006.257.09:14:41.00#ibcon#flushed, iclass 27, count 0 2006.257.09:14:41.00#ibcon#about to write, iclass 27, count 0 2006.257.09:14:41.00#ibcon#wrote, iclass 27, count 0 2006.257.09:14:41.00#ibcon#about to read 3, iclass 27, count 0 2006.257.09:14:41.02#ibcon#read 3, iclass 27, count 0 2006.257.09:14:41.02#ibcon#about to read 4, iclass 27, count 0 2006.257.09:14:41.02#ibcon#read 4, iclass 27, count 0 2006.257.09:14:41.02#ibcon#about to read 5, iclass 27, count 0 2006.257.09:14:41.02#ibcon#read 5, iclass 27, count 0 2006.257.09:14:41.02#ibcon#about to read 6, iclass 27, count 0 2006.257.09:14:41.02#ibcon#read 6, iclass 27, count 0 2006.257.09:14:41.02#ibcon#end of sib2, iclass 27, count 0 2006.257.09:14:41.02#ibcon#*mode == 0, iclass 27, count 0 2006.257.09:14:41.02#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.09:14:41.02#ibcon#[27=USB\r\n] 2006.257.09:14:41.02#ibcon#*before write, iclass 27, count 0 2006.257.09:14:41.02#ibcon#enter sib2, iclass 27, count 0 2006.257.09:14:41.02#ibcon#flushed, iclass 27, count 0 2006.257.09:14:41.02#ibcon#about to write, iclass 27, count 0 2006.257.09:14:41.02#ibcon#wrote, iclass 27, count 0 2006.257.09:14:41.02#ibcon#about to read 3, iclass 27, count 0 2006.257.09:14:41.05#ibcon#read 3, iclass 27, count 0 2006.257.09:14:41.05#ibcon#about to read 4, iclass 27, count 0 2006.257.09:14:41.05#ibcon#read 4, iclass 27, count 0 2006.257.09:14:41.05#ibcon#about to read 5, iclass 27, count 0 2006.257.09:14:41.05#ibcon#read 5, iclass 27, count 0 2006.257.09:14:41.05#ibcon#about to read 6, iclass 27, count 0 2006.257.09:14:41.05#ibcon#read 6, iclass 27, count 0 2006.257.09:14:41.05#ibcon#end of sib2, iclass 27, count 0 2006.257.09:14:41.05#ibcon#*after write, iclass 27, count 0 2006.257.09:14:41.05#ibcon#*before return 0, iclass 27, count 0 2006.257.09:14:41.05#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:41.05#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:14:41.05#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.09:14:41.05#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.09:14:41.05$vck44/vblo=4,679.99 2006.257.09:14:41.05#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.09:14:41.05#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.09:14:41.05#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:41.05#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:41.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:41.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:41.05#ibcon#enter wrdev, iclass 29, count 0 2006.257.09:14:41.05#ibcon#first serial, iclass 29, count 0 2006.257.09:14:41.05#ibcon#enter sib2, iclass 29, count 0 2006.257.09:14:41.05#ibcon#flushed, iclass 29, count 0 2006.257.09:14:41.05#ibcon#about to write, iclass 29, count 0 2006.257.09:14:41.05#ibcon#wrote, iclass 29, count 0 2006.257.09:14:41.05#ibcon#about to read 3, iclass 29, count 0 2006.257.09:14:41.07#ibcon#read 3, iclass 29, count 0 2006.257.09:14:41.07#ibcon#about to read 4, iclass 29, count 0 2006.257.09:14:41.07#ibcon#read 4, iclass 29, count 0 2006.257.09:14:41.07#ibcon#about to read 5, iclass 29, count 0 2006.257.09:14:41.07#ibcon#read 5, iclass 29, count 0 2006.257.09:14:41.07#ibcon#about to read 6, iclass 29, count 0 2006.257.09:14:41.07#ibcon#read 6, iclass 29, count 0 2006.257.09:14:41.07#ibcon#end of sib2, iclass 29, count 0 2006.257.09:14:41.07#ibcon#*mode == 0, iclass 29, count 0 2006.257.09:14:41.07#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.09:14:41.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:14:41.07#ibcon#*before write, iclass 29, count 0 2006.257.09:14:41.07#ibcon#enter sib2, iclass 29, count 0 2006.257.09:14:41.07#ibcon#flushed, iclass 29, count 0 2006.257.09:14:41.07#ibcon#about to write, iclass 29, count 0 2006.257.09:14:41.07#ibcon#wrote, iclass 29, count 0 2006.257.09:14:41.07#ibcon#about to read 3, iclass 29, count 0 2006.257.09:14:41.11#ibcon#read 3, iclass 29, count 0 2006.257.09:14:41.11#ibcon#about to read 4, iclass 29, count 0 2006.257.09:14:41.11#ibcon#read 4, iclass 29, count 0 2006.257.09:14:41.11#ibcon#about to read 5, iclass 29, count 0 2006.257.09:14:41.11#ibcon#read 5, iclass 29, count 0 2006.257.09:14:41.11#ibcon#about to read 6, iclass 29, count 0 2006.257.09:14:41.11#ibcon#read 6, iclass 29, count 0 2006.257.09:14:41.11#ibcon#end of sib2, iclass 29, count 0 2006.257.09:14:41.11#ibcon#*after write, iclass 29, count 0 2006.257.09:14:41.11#ibcon#*before return 0, iclass 29, count 0 2006.257.09:14:41.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:41.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:14:41.11#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.09:14:41.11#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.09:14:41.11$vck44/vb=4,5 2006.257.09:14:41.11#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.09:14:41.11#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.09:14:41.11#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:41.11#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:41.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:41.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:41.17#ibcon#enter wrdev, iclass 31, count 2 2006.257.09:14:41.17#ibcon#first serial, iclass 31, count 2 2006.257.09:14:41.17#ibcon#enter sib2, iclass 31, count 2 2006.257.09:14:41.17#ibcon#flushed, iclass 31, count 2 2006.257.09:14:41.17#ibcon#about to write, iclass 31, count 2 2006.257.09:14:41.17#ibcon#wrote, iclass 31, count 2 2006.257.09:14:41.17#ibcon#about to read 3, iclass 31, count 2 2006.257.09:14:41.19#ibcon#read 3, iclass 31, count 2 2006.257.09:14:41.19#ibcon#about to read 4, iclass 31, count 2 2006.257.09:14:41.19#ibcon#read 4, iclass 31, count 2 2006.257.09:14:41.19#ibcon#about to read 5, iclass 31, count 2 2006.257.09:14:41.19#ibcon#read 5, iclass 31, count 2 2006.257.09:14:41.19#ibcon#about to read 6, iclass 31, count 2 2006.257.09:14:41.19#ibcon#read 6, iclass 31, count 2 2006.257.09:14:41.19#ibcon#end of sib2, iclass 31, count 2 2006.257.09:14:41.19#ibcon#*mode == 0, iclass 31, count 2 2006.257.09:14:41.19#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.09:14:41.19#ibcon#[27=AT04-05\r\n] 2006.257.09:14:41.19#ibcon#*before write, iclass 31, count 2 2006.257.09:14:41.19#ibcon#enter sib2, iclass 31, count 2 2006.257.09:14:41.19#ibcon#flushed, iclass 31, count 2 2006.257.09:14:41.19#ibcon#about to write, iclass 31, count 2 2006.257.09:14:41.19#ibcon#wrote, iclass 31, count 2 2006.257.09:14:41.19#ibcon#about to read 3, iclass 31, count 2 2006.257.09:14:41.22#ibcon#read 3, iclass 31, count 2 2006.257.09:14:41.22#ibcon#about to read 4, iclass 31, count 2 2006.257.09:14:41.22#ibcon#read 4, iclass 31, count 2 2006.257.09:14:41.22#ibcon#about to read 5, iclass 31, count 2 2006.257.09:14:41.22#ibcon#read 5, iclass 31, count 2 2006.257.09:14:41.22#ibcon#about to read 6, iclass 31, count 2 2006.257.09:14:41.22#ibcon#read 6, iclass 31, count 2 2006.257.09:14:41.22#ibcon#end of sib2, iclass 31, count 2 2006.257.09:14:41.22#ibcon#*after write, iclass 31, count 2 2006.257.09:14:41.22#ibcon#*before return 0, iclass 31, count 2 2006.257.09:14:41.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:41.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:14:41.22#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.09:14:41.22#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:41.22#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:41.34#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:41.34#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:41.34#ibcon#enter wrdev, iclass 31, count 0 2006.257.09:14:41.34#ibcon#first serial, iclass 31, count 0 2006.257.09:14:41.34#ibcon#enter sib2, iclass 31, count 0 2006.257.09:14:41.34#ibcon#flushed, iclass 31, count 0 2006.257.09:14:41.34#ibcon#about to write, iclass 31, count 0 2006.257.09:14:41.34#ibcon#wrote, iclass 31, count 0 2006.257.09:14:41.34#ibcon#about to read 3, iclass 31, count 0 2006.257.09:14:41.36#ibcon#read 3, iclass 31, count 0 2006.257.09:14:41.36#ibcon#about to read 4, iclass 31, count 0 2006.257.09:14:41.36#ibcon#read 4, iclass 31, count 0 2006.257.09:14:41.36#ibcon#about to read 5, iclass 31, count 0 2006.257.09:14:41.36#ibcon#read 5, iclass 31, count 0 2006.257.09:14:41.36#ibcon#about to read 6, iclass 31, count 0 2006.257.09:14:41.36#ibcon#read 6, iclass 31, count 0 2006.257.09:14:41.36#ibcon#end of sib2, iclass 31, count 0 2006.257.09:14:41.36#ibcon#*mode == 0, iclass 31, count 0 2006.257.09:14:41.36#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.09:14:41.36#ibcon#[27=USB\r\n] 2006.257.09:14:41.36#ibcon#*before write, iclass 31, count 0 2006.257.09:14:41.36#ibcon#enter sib2, iclass 31, count 0 2006.257.09:14:41.36#ibcon#flushed, iclass 31, count 0 2006.257.09:14:41.36#ibcon#about to write, iclass 31, count 0 2006.257.09:14:41.36#ibcon#wrote, iclass 31, count 0 2006.257.09:14:41.36#ibcon#about to read 3, iclass 31, count 0 2006.257.09:14:41.39#ibcon#read 3, iclass 31, count 0 2006.257.09:14:41.39#ibcon#about to read 4, iclass 31, count 0 2006.257.09:14:41.39#ibcon#read 4, iclass 31, count 0 2006.257.09:14:41.39#ibcon#about to read 5, iclass 31, count 0 2006.257.09:14:41.39#ibcon#read 5, iclass 31, count 0 2006.257.09:14:41.39#ibcon#about to read 6, iclass 31, count 0 2006.257.09:14:41.39#ibcon#read 6, iclass 31, count 0 2006.257.09:14:41.39#ibcon#end of sib2, iclass 31, count 0 2006.257.09:14:41.39#ibcon#*after write, iclass 31, count 0 2006.257.09:14:41.39#ibcon#*before return 0, iclass 31, count 0 2006.257.09:14:41.39#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:41.39#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:14:41.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.09:14:41.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.09:14:41.39$vck44/vblo=5,709.99 2006.257.09:14:41.39#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.09:14:41.39#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.09:14:41.39#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:41.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:41.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:41.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:41.39#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:14:41.39#ibcon#first serial, iclass 33, count 0 2006.257.09:14:41.39#ibcon#enter sib2, iclass 33, count 0 2006.257.09:14:41.39#ibcon#flushed, iclass 33, count 0 2006.257.09:14:41.39#ibcon#about to write, iclass 33, count 0 2006.257.09:14:41.39#ibcon#wrote, iclass 33, count 0 2006.257.09:14:41.39#ibcon#about to read 3, iclass 33, count 0 2006.257.09:14:41.41#ibcon#read 3, iclass 33, count 0 2006.257.09:14:41.41#ibcon#about to read 4, iclass 33, count 0 2006.257.09:14:41.41#ibcon#read 4, iclass 33, count 0 2006.257.09:14:41.41#ibcon#about to read 5, iclass 33, count 0 2006.257.09:14:41.41#ibcon#read 5, iclass 33, count 0 2006.257.09:14:41.41#ibcon#about to read 6, iclass 33, count 0 2006.257.09:14:41.41#ibcon#read 6, iclass 33, count 0 2006.257.09:14:41.41#ibcon#end of sib2, iclass 33, count 0 2006.257.09:14:41.41#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:14:41.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:14:41.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:14:41.41#ibcon#*before write, iclass 33, count 0 2006.257.09:14:41.41#ibcon#enter sib2, iclass 33, count 0 2006.257.09:14:41.41#ibcon#flushed, iclass 33, count 0 2006.257.09:14:41.41#ibcon#about to write, iclass 33, count 0 2006.257.09:14:41.41#ibcon#wrote, iclass 33, count 0 2006.257.09:14:41.41#ibcon#about to read 3, iclass 33, count 0 2006.257.09:14:41.45#ibcon#read 3, iclass 33, count 0 2006.257.09:14:41.45#ibcon#about to read 4, iclass 33, count 0 2006.257.09:14:41.45#ibcon#read 4, iclass 33, count 0 2006.257.09:14:41.45#ibcon#about to read 5, iclass 33, count 0 2006.257.09:14:41.45#ibcon#read 5, iclass 33, count 0 2006.257.09:14:41.45#ibcon#about to read 6, iclass 33, count 0 2006.257.09:14:41.45#ibcon#read 6, iclass 33, count 0 2006.257.09:14:41.45#ibcon#end of sib2, iclass 33, count 0 2006.257.09:14:41.45#ibcon#*after write, iclass 33, count 0 2006.257.09:14:41.45#ibcon#*before return 0, iclass 33, count 0 2006.257.09:14:41.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:41.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:14:41.45#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:14:41.45#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:14:41.45$vck44/vb=5,4 2006.257.09:14:41.45#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.09:14:41.45#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.09:14:41.45#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:41.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:41.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:41.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:41.51#ibcon#enter wrdev, iclass 35, count 2 2006.257.09:14:41.51#ibcon#first serial, iclass 35, count 2 2006.257.09:14:41.51#ibcon#enter sib2, iclass 35, count 2 2006.257.09:14:41.51#ibcon#flushed, iclass 35, count 2 2006.257.09:14:41.51#ibcon#about to write, iclass 35, count 2 2006.257.09:14:41.51#ibcon#wrote, iclass 35, count 2 2006.257.09:14:41.51#ibcon#about to read 3, iclass 35, count 2 2006.257.09:14:41.53#ibcon#read 3, iclass 35, count 2 2006.257.09:14:41.53#ibcon#about to read 4, iclass 35, count 2 2006.257.09:14:41.53#ibcon#read 4, iclass 35, count 2 2006.257.09:14:41.53#ibcon#about to read 5, iclass 35, count 2 2006.257.09:14:41.53#ibcon#read 5, iclass 35, count 2 2006.257.09:14:41.53#ibcon#about to read 6, iclass 35, count 2 2006.257.09:14:41.53#ibcon#read 6, iclass 35, count 2 2006.257.09:14:41.53#ibcon#end of sib2, iclass 35, count 2 2006.257.09:14:41.53#ibcon#*mode == 0, iclass 35, count 2 2006.257.09:14:41.53#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.09:14:41.53#ibcon#[27=AT05-04\r\n] 2006.257.09:14:41.53#ibcon#*before write, iclass 35, count 2 2006.257.09:14:41.53#ibcon#enter sib2, iclass 35, count 2 2006.257.09:14:41.53#ibcon#flushed, iclass 35, count 2 2006.257.09:14:41.53#ibcon#about to write, iclass 35, count 2 2006.257.09:14:41.53#ibcon#wrote, iclass 35, count 2 2006.257.09:14:41.53#ibcon#about to read 3, iclass 35, count 2 2006.257.09:14:41.56#ibcon#read 3, iclass 35, count 2 2006.257.09:14:41.56#ibcon#about to read 4, iclass 35, count 2 2006.257.09:14:41.56#ibcon#read 4, iclass 35, count 2 2006.257.09:14:41.56#ibcon#about to read 5, iclass 35, count 2 2006.257.09:14:41.56#ibcon#read 5, iclass 35, count 2 2006.257.09:14:41.56#ibcon#about to read 6, iclass 35, count 2 2006.257.09:14:41.56#ibcon#read 6, iclass 35, count 2 2006.257.09:14:41.56#ibcon#end of sib2, iclass 35, count 2 2006.257.09:14:41.56#ibcon#*after write, iclass 35, count 2 2006.257.09:14:41.56#ibcon#*before return 0, iclass 35, count 2 2006.257.09:14:41.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:41.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:14:41.56#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.09:14:41.56#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:41.56#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:41.68#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:41.68#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:41.68#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:14:41.68#ibcon#first serial, iclass 35, count 0 2006.257.09:14:41.68#ibcon#enter sib2, iclass 35, count 0 2006.257.09:14:41.68#ibcon#flushed, iclass 35, count 0 2006.257.09:14:41.68#ibcon#about to write, iclass 35, count 0 2006.257.09:14:41.68#ibcon#wrote, iclass 35, count 0 2006.257.09:14:41.68#ibcon#about to read 3, iclass 35, count 0 2006.257.09:14:41.70#ibcon#read 3, iclass 35, count 0 2006.257.09:14:41.70#ibcon#about to read 4, iclass 35, count 0 2006.257.09:14:41.70#ibcon#read 4, iclass 35, count 0 2006.257.09:14:41.70#ibcon#about to read 5, iclass 35, count 0 2006.257.09:14:41.70#ibcon#read 5, iclass 35, count 0 2006.257.09:14:41.70#ibcon#about to read 6, iclass 35, count 0 2006.257.09:14:41.70#ibcon#read 6, iclass 35, count 0 2006.257.09:14:41.70#ibcon#end of sib2, iclass 35, count 0 2006.257.09:14:41.70#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:14:41.70#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:14:41.70#ibcon#[27=USB\r\n] 2006.257.09:14:41.70#ibcon#*before write, iclass 35, count 0 2006.257.09:14:41.70#ibcon#enter sib2, iclass 35, count 0 2006.257.09:14:41.70#ibcon#flushed, iclass 35, count 0 2006.257.09:14:41.70#ibcon#about to write, iclass 35, count 0 2006.257.09:14:41.70#ibcon#wrote, iclass 35, count 0 2006.257.09:14:41.70#ibcon#about to read 3, iclass 35, count 0 2006.257.09:14:41.73#ibcon#read 3, iclass 35, count 0 2006.257.09:14:41.73#ibcon#about to read 4, iclass 35, count 0 2006.257.09:14:41.73#ibcon#read 4, iclass 35, count 0 2006.257.09:14:41.73#ibcon#about to read 5, iclass 35, count 0 2006.257.09:14:41.73#ibcon#read 5, iclass 35, count 0 2006.257.09:14:41.73#ibcon#about to read 6, iclass 35, count 0 2006.257.09:14:41.73#ibcon#read 6, iclass 35, count 0 2006.257.09:14:41.73#ibcon#end of sib2, iclass 35, count 0 2006.257.09:14:41.73#ibcon#*after write, iclass 35, count 0 2006.257.09:14:41.73#ibcon#*before return 0, iclass 35, count 0 2006.257.09:14:41.73#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:41.73#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:14:41.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:14:41.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:14:41.73$vck44/vblo=6,719.99 2006.257.09:14:41.73#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.09:14:41.73#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.09:14:41.73#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:41.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:41.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:41.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:41.73#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:14:41.73#ibcon#first serial, iclass 37, count 0 2006.257.09:14:41.73#ibcon#enter sib2, iclass 37, count 0 2006.257.09:14:41.73#ibcon#flushed, iclass 37, count 0 2006.257.09:14:41.73#ibcon#about to write, iclass 37, count 0 2006.257.09:14:41.73#ibcon#wrote, iclass 37, count 0 2006.257.09:14:41.73#ibcon#about to read 3, iclass 37, count 0 2006.257.09:14:41.75#ibcon#read 3, iclass 37, count 0 2006.257.09:14:41.75#ibcon#about to read 4, iclass 37, count 0 2006.257.09:14:41.75#ibcon#read 4, iclass 37, count 0 2006.257.09:14:41.75#ibcon#about to read 5, iclass 37, count 0 2006.257.09:14:41.75#ibcon#read 5, iclass 37, count 0 2006.257.09:14:41.75#ibcon#about to read 6, iclass 37, count 0 2006.257.09:14:41.75#ibcon#read 6, iclass 37, count 0 2006.257.09:14:41.75#ibcon#end of sib2, iclass 37, count 0 2006.257.09:14:41.75#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:14:41.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:14:41.75#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:14:41.75#ibcon#*before write, iclass 37, count 0 2006.257.09:14:41.75#ibcon#enter sib2, iclass 37, count 0 2006.257.09:14:41.75#ibcon#flushed, iclass 37, count 0 2006.257.09:14:41.75#ibcon#about to write, iclass 37, count 0 2006.257.09:14:41.75#ibcon#wrote, iclass 37, count 0 2006.257.09:14:41.75#ibcon#about to read 3, iclass 37, count 0 2006.257.09:14:41.79#ibcon#read 3, iclass 37, count 0 2006.257.09:14:41.79#ibcon#about to read 4, iclass 37, count 0 2006.257.09:14:41.79#ibcon#read 4, iclass 37, count 0 2006.257.09:14:41.79#ibcon#about to read 5, iclass 37, count 0 2006.257.09:14:41.79#ibcon#read 5, iclass 37, count 0 2006.257.09:14:41.79#ibcon#about to read 6, iclass 37, count 0 2006.257.09:14:41.79#ibcon#read 6, iclass 37, count 0 2006.257.09:14:41.79#ibcon#end of sib2, iclass 37, count 0 2006.257.09:14:41.79#ibcon#*after write, iclass 37, count 0 2006.257.09:14:41.79#ibcon#*before return 0, iclass 37, count 0 2006.257.09:14:41.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:41.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:14:41.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:14:41.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:14:41.79$vck44/vb=6,4 2006.257.09:14:41.79#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.09:14:41.79#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.09:14:41.79#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:41.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:41.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:41.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:41.85#ibcon#enter wrdev, iclass 39, count 2 2006.257.09:14:41.85#ibcon#first serial, iclass 39, count 2 2006.257.09:14:41.85#ibcon#enter sib2, iclass 39, count 2 2006.257.09:14:41.85#ibcon#flushed, iclass 39, count 2 2006.257.09:14:41.85#ibcon#about to write, iclass 39, count 2 2006.257.09:14:41.85#ibcon#wrote, iclass 39, count 2 2006.257.09:14:41.85#ibcon#about to read 3, iclass 39, count 2 2006.257.09:14:41.87#ibcon#read 3, iclass 39, count 2 2006.257.09:14:41.87#ibcon#about to read 4, iclass 39, count 2 2006.257.09:14:41.87#ibcon#read 4, iclass 39, count 2 2006.257.09:14:41.87#ibcon#about to read 5, iclass 39, count 2 2006.257.09:14:41.87#ibcon#read 5, iclass 39, count 2 2006.257.09:14:41.87#ibcon#about to read 6, iclass 39, count 2 2006.257.09:14:41.87#ibcon#read 6, iclass 39, count 2 2006.257.09:14:41.87#ibcon#end of sib2, iclass 39, count 2 2006.257.09:14:41.87#ibcon#*mode == 0, iclass 39, count 2 2006.257.09:14:41.87#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.09:14:41.87#ibcon#[27=AT06-04\r\n] 2006.257.09:14:41.87#ibcon#*before write, iclass 39, count 2 2006.257.09:14:41.87#ibcon#enter sib2, iclass 39, count 2 2006.257.09:14:41.87#ibcon#flushed, iclass 39, count 2 2006.257.09:14:41.87#ibcon#about to write, iclass 39, count 2 2006.257.09:14:41.87#ibcon#wrote, iclass 39, count 2 2006.257.09:14:41.87#ibcon#about to read 3, iclass 39, count 2 2006.257.09:14:41.90#ibcon#read 3, iclass 39, count 2 2006.257.09:14:41.90#ibcon#about to read 4, iclass 39, count 2 2006.257.09:14:41.90#ibcon#read 4, iclass 39, count 2 2006.257.09:14:41.90#ibcon#about to read 5, iclass 39, count 2 2006.257.09:14:41.90#ibcon#read 5, iclass 39, count 2 2006.257.09:14:41.90#ibcon#about to read 6, iclass 39, count 2 2006.257.09:14:41.90#ibcon#read 6, iclass 39, count 2 2006.257.09:14:41.90#ibcon#end of sib2, iclass 39, count 2 2006.257.09:14:41.90#ibcon#*after write, iclass 39, count 2 2006.257.09:14:41.90#ibcon#*before return 0, iclass 39, count 2 2006.257.09:14:41.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:41.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:14:41.90#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.09:14:41.90#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:41.90#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:42.02#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:42.02#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:42.02#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:14:42.02#ibcon#first serial, iclass 39, count 0 2006.257.09:14:42.02#ibcon#enter sib2, iclass 39, count 0 2006.257.09:14:42.02#ibcon#flushed, iclass 39, count 0 2006.257.09:14:42.02#ibcon#about to write, iclass 39, count 0 2006.257.09:14:42.02#ibcon#wrote, iclass 39, count 0 2006.257.09:14:42.02#ibcon#about to read 3, iclass 39, count 0 2006.257.09:14:42.04#ibcon#read 3, iclass 39, count 0 2006.257.09:14:42.04#ibcon#about to read 4, iclass 39, count 0 2006.257.09:14:42.04#ibcon#read 4, iclass 39, count 0 2006.257.09:14:42.04#ibcon#about to read 5, iclass 39, count 0 2006.257.09:14:42.04#ibcon#read 5, iclass 39, count 0 2006.257.09:14:42.04#ibcon#about to read 6, iclass 39, count 0 2006.257.09:14:42.04#ibcon#read 6, iclass 39, count 0 2006.257.09:14:42.04#ibcon#end of sib2, iclass 39, count 0 2006.257.09:14:42.04#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:14:42.04#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:14:42.04#ibcon#[27=USB\r\n] 2006.257.09:14:42.04#ibcon#*before write, iclass 39, count 0 2006.257.09:14:42.04#ibcon#enter sib2, iclass 39, count 0 2006.257.09:14:42.04#ibcon#flushed, iclass 39, count 0 2006.257.09:14:42.04#ibcon#about to write, iclass 39, count 0 2006.257.09:14:42.04#ibcon#wrote, iclass 39, count 0 2006.257.09:14:42.04#ibcon#about to read 3, iclass 39, count 0 2006.257.09:14:42.07#ibcon#read 3, iclass 39, count 0 2006.257.09:14:42.07#ibcon#about to read 4, iclass 39, count 0 2006.257.09:14:42.07#ibcon#read 4, iclass 39, count 0 2006.257.09:14:42.07#ibcon#about to read 5, iclass 39, count 0 2006.257.09:14:42.07#ibcon#read 5, iclass 39, count 0 2006.257.09:14:42.07#ibcon#about to read 6, iclass 39, count 0 2006.257.09:14:42.07#ibcon#read 6, iclass 39, count 0 2006.257.09:14:42.07#ibcon#end of sib2, iclass 39, count 0 2006.257.09:14:42.07#ibcon#*after write, iclass 39, count 0 2006.257.09:14:42.07#ibcon#*before return 0, iclass 39, count 0 2006.257.09:14:42.07#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:42.07#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:14:42.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:14:42.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:14:42.07$vck44/vblo=7,734.99 2006.257.09:14:42.07#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.09:14:42.07#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.09:14:42.07#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:42.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:42.07#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:42.07#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:42.07#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:14:42.07#ibcon#first serial, iclass 3, count 0 2006.257.09:14:42.07#ibcon#enter sib2, iclass 3, count 0 2006.257.09:14:42.07#ibcon#flushed, iclass 3, count 0 2006.257.09:14:42.07#ibcon#about to write, iclass 3, count 0 2006.257.09:14:42.07#ibcon#wrote, iclass 3, count 0 2006.257.09:14:42.07#ibcon#about to read 3, iclass 3, count 0 2006.257.09:14:42.09#ibcon#read 3, iclass 3, count 0 2006.257.09:14:42.09#ibcon#about to read 4, iclass 3, count 0 2006.257.09:14:42.09#ibcon#read 4, iclass 3, count 0 2006.257.09:14:42.09#ibcon#about to read 5, iclass 3, count 0 2006.257.09:14:42.09#ibcon#read 5, iclass 3, count 0 2006.257.09:14:42.09#ibcon#about to read 6, iclass 3, count 0 2006.257.09:14:42.09#ibcon#read 6, iclass 3, count 0 2006.257.09:14:42.09#ibcon#end of sib2, iclass 3, count 0 2006.257.09:14:42.09#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:14:42.09#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:14:42.09#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:14:42.09#ibcon#*before write, iclass 3, count 0 2006.257.09:14:42.09#ibcon#enter sib2, iclass 3, count 0 2006.257.09:14:42.09#ibcon#flushed, iclass 3, count 0 2006.257.09:14:42.09#ibcon#about to write, iclass 3, count 0 2006.257.09:14:42.09#ibcon#wrote, iclass 3, count 0 2006.257.09:14:42.09#ibcon#about to read 3, iclass 3, count 0 2006.257.09:14:42.13#ibcon#read 3, iclass 3, count 0 2006.257.09:14:42.13#ibcon#about to read 4, iclass 3, count 0 2006.257.09:14:42.13#ibcon#read 4, iclass 3, count 0 2006.257.09:14:42.13#ibcon#about to read 5, iclass 3, count 0 2006.257.09:14:42.13#ibcon#read 5, iclass 3, count 0 2006.257.09:14:42.13#ibcon#about to read 6, iclass 3, count 0 2006.257.09:14:42.13#ibcon#read 6, iclass 3, count 0 2006.257.09:14:42.13#ibcon#end of sib2, iclass 3, count 0 2006.257.09:14:42.13#ibcon#*after write, iclass 3, count 0 2006.257.09:14:42.13#ibcon#*before return 0, iclass 3, count 0 2006.257.09:14:42.13#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:42.13#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:14:42.13#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:14:42.13#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:14:42.13$vck44/vb=7,4 2006.257.09:14:42.13#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.09:14:42.13#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.09:14:42.13#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:42.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:42.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:42.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:42.19#ibcon#enter wrdev, iclass 5, count 2 2006.257.09:14:42.19#ibcon#first serial, iclass 5, count 2 2006.257.09:14:42.19#ibcon#enter sib2, iclass 5, count 2 2006.257.09:14:42.19#ibcon#flushed, iclass 5, count 2 2006.257.09:14:42.19#ibcon#about to write, iclass 5, count 2 2006.257.09:14:42.19#ibcon#wrote, iclass 5, count 2 2006.257.09:14:42.19#ibcon#about to read 3, iclass 5, count 2 2006.257.09:14:42.21#ibcon#read 3, iclass 5, count 2 2006.257.09:14:42.21#ibcon#about to read 4, iclass 5, count 2 2006.257.09:14:42.21#ibcon#read 4, iclass 5, count 2 2006.257.09:14:42.21#ibcon#about to read 5, iclass 5, count 2 2006.257.09:14:42.21#ibcon#read 5, iclass 5, count 2 2006.257.09:14:42.21#ibcon#about to read 6, iclass 5, count 2 2006.257.09:14:42.21#ibcon#read 6, iclass 5, count 2 2006.257.09:14:42.21#ibcon#end of sib2, iclass 5, count 2 2006.257.09:14:42.21#ibcon#*mode == 0, iclass 5, count 2 2006.257.09:14:42.21#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.09:14:42.21#ibcon#[27=AT07-04\r\n] 2006.257.09:14:42.21#ibcon#*before write, iclass 5, count 2 2006.257.09:14:42.21#ibcon#enter sib2, iclass 5, count 2 2006.257.09:14:42.21#ibcon#flushed, iclass 5, count 2 2006.257.09:14:42.21#ibcon#about to write, iclass 5, count 2 2006.257.09:14:42.21#ibcon#wrote, iclass 5, count 2 2006.257.09:14:42.21#ibcon#about to read 3, iclass 5, count 2 2006.257.09:14:42.24#ibcon#read 3, iclass 5, count 2 2006.257.09:14:42.24#ibcon#about to read 4, iclass 5, count 2 2006.257.09:14:42.24#ibcon#read 4, iclass 5, count 2 2006.257.09:14:42.24#ibcon#about to read 5, iclass 5, count 2 2006.257.09:14:42.24#ibcon#read 5, iclass 5, count 2 2006.257.09:14:42.24#ibcon#about to read 6, iclass 5, count 2 2006.257.09:14:42.24#ibcon#read 6, iclass 5, count 2 2006.257.09:14:42.24#ibcon#end of sib2, iclass 5, count 2 2006.257.09:14:42.24#ibcon#*after write, iclass 5, count 2 2006.257.09:14:42.24#ibcon#*before return 0, iclass 5, count 2 2006.257.09:14:42.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:42.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:14:42.24#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.09:14:42.24#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:42.24#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:42.36#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:42.36#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:42.36#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:14:42.36#ibcon#first serial, iclass 5, count 0 2006.257.09:14:42.36#ibcon#enter sib2, iclass 5, count 0 2006.257.09:14:42.36#ibcon#flushed, iclass 5, count 0 2006.257.09:14:42.36#ibcon#about to write, iclass 5, count 0 2006.257.09:14:42.36#ibcon#wrote, iclass 5, count 0 2006.257.09:14:42.36#ibcon#about to read 3, iclass 5, count 0 2006.257.09:14:42.38#ibcon#read 3, iclass 5, count 0 2006.257.09:14:42.38#ibcon#about to read 4, iclass 5, count 0 2006.257.09:14:42.38#ibcon#read 4, iclass 5, count 0 2006.257.09:14:42.38#ibcon#about to read 5, iclass 5, count 0 2006.257.09:14:42.38#ibcon#read 5, iclass 5, count 0 2006.257.09:14:42.38#ibcon#about to read 6, iclass 5, count 0 2006.257.09:14:42.38#ibcon#read 6, iclass 5, count 0 2006.257.09:14:42.38#ibcon#end of sib2, iclass 5, count 0 2006.257.09:14:42.38#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:14:42.38#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:14:42.38#ibcon#[27=USB\r\n] 2006.257.09:14:42.38#ibcon#*before write, iclass 5, count 0 2006.257.09:14:42.38#ibcon#enter sib2, iclass 5, count 0 2006.257.09:14:42.38#ibcon#flushed, iclass 5, count 0 2006.257.09:14:42.38#ibcon#about to write, iclass 5, count 0 2006.257.09:14:42.38#ibcon#wrote, iclass 5, count 0 2006.257.09:14:42.38#ibcon#about to read 3, iclass 5, count 0 2006.257.09:14:42.41#ibcon#read 3, iclass 5, count 0 2006.257.09:14:42.41#ibcon#about to read 4, iclass 5, count 0 2006.257.09:14:42.41#ibcon#read 4, iclass 5, count 0 2006.257.09:14:42.41#ibcon#about to read 5, iclass 5, count 0 2006.257.09:14:42.41#ibcon#read 5, iclass 5, count 0 2006.257.09:14:42.41#ibcon#about to read 6, iclass 5, count 0 2006.257.09:14:42.41#ibcon#read 6, iclass 5, count 0 2006.257.09:14:42.41#ibcon#end of sib2, iclass 5, count 0 2006.257.09:14:42.41#ibcon#*after write, iclass 5, count 0 2006.257.09:14:42.41#ibcon#*before return 0, iclass 5, count 0 2006.257.09:14:42.41#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:42.41#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:14:42.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:14:42.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:14:42.41$vck44/vblo=8,744.99 2006.257.09:14:42.41#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.09:14:42.41#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.09:14:42.41#ibcon#ireg 17 cls_cnt 0 2006.257.09:14:42.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:42.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:42.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:42.41#ibcon#enter wrdev, iclass 7, count 0 2006.257.09:14:42.41#ibcon#first serial, iclass 7, count 0 2006.257.09:14:42.41#ibcon#enter sib2, iclass 7, count 0 2006.257.09:14:42.41#ibcon#flushed, iclass 7, count 0 2006.257.09:14:42.41#ibcon#about to write, iclass 7, count 0 2006.257.09:14:42.41#ibcon#wrote, iclass 7, count 0 2006.257.09:14:42.41#ibcon#about to read 3, iclass 7, count 0 2006.257.09:14:42.43#ibcon#read 3, iclass 7, count 0 2006.257.09:14:42.43#ibcon#about to read 4, iclass 7, count 0 2006.257.09:14:42.43#ibcon#read 4, iclass 7, count 0 2006.257.09:14:42.43#ibcon#about to read 5, iclass 7, count 0 2006.257.09:14:42.43#ibcon#read 5, iclass 7, count 0 2006.257.09:14:42.43#ibcon#about to read 6, iclass 7, count 0 2006.257.09:14:42.43#ibcon#read 6, iclass 7, count 0 2006.257.09:14:42.43#ibcon#end of sib2, iclass 7, count 0 2006.257.09:14:42.43#ibcon#*mode == 0, iclass 7, count 0 2006.257.09:14:42.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.09:14:42.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:14:42.43#ibcon#*before write, iclass 7, count 0 2006.257.09:14:42.43#ibcon#enter sib2, iclass 7, count 0 2006.257.09:14:42.43#ibcon#flushed, iclass 7, count 0 2006.257.09:14:42.43#ibcon#about to write, iclass 7, count 0 2006.257.09:14:42.43#ibcon#wrote, iclass 7, count 0 2006.257.09:14:42.43#ibcon#about to read 3, iclass 7, count 0 2006.257.09:14:42.47#ibcon#read 3, iclass 7, count 0 2006.257.09:14:42.47#ibcon#about to read 4, iclass 7, count 0 2006.257.09:14:42.47#ibcon#read 4, iclass 7, count 0 2006.257.09:14:42.47#ibcon#about to read 5, iclass 7, count 0 2006.257.09:14:42.47#ibcon#read 5, iclass 7, count 0 2006.257.09:14:42.47#ibcon#about to read 6, iclass 7, count 0 2006.257.09:14:42.47#ibcon#read 6, iclass 7, count 0 2006.257.09:14:42.47#ibcon#end of sib2, iclass 7, count 0 2006.257.09:14:42.47#ibcon#*after write, iclass 7, count 0 2006.257.09:14:42.47#ibcon#*before return 0, iclass 7, count 0 2006.257.09:14:42.47#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:42.47#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:14:42.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.09:14:42.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.09:14:42.47$vck44/vb=8,4 2006.257.09:14:42.47#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.09:14:42.47#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.09:14:42.47#ibcon#ireg 11 cls_cnt 2 2006.257.09:14:42.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:42.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:42.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:42.53#ibcon#enter wrdev, iclass 11, count 2 2006.257.09:14:42.53#ibcon#first serial, iclass 11, count 2 2006.257.09:14:42.53#ibcon#enter sib2, iclass 11, count 2 2006.257.09:14:42.53#ibcon#flushed, iclass 11, count 2 2006.257.09:14:42.53#ibcon#about to write, iclass 11, count 2 2006.257.09:14:42.53#ibcon#wrote, iclass 11, count 2 2006.257.09:14:42.53#ibcon#about to read 3, iclass 11, count 2 2006.257.09:14:42.55#ibcon#read 3, iclass 11, count 2 2006.257.09:14:42.55#ibcon#about to read 4, iclass 11, count 2 2006.257.09:14:42.55#ibcon#read 4, iclass 11, count 2 2006.257.09:14:42.55#ibcon#about to read 5, iclass 11, count 2 2006.257.09:14:42.55#ibcon#read 5, iclass 11, count 2 2006.257.09:14:42.55#ibcon#about to read 6, iclass 11, count 2 2006.257.09:14:42.55#ibcon#read 6, iclass 11, count 2 2006.257.09:14:42.55#ibcon#end of sib2, iclass 11, count 2 2006.257.09:14:42.55#ibcon#*mode == 0, iclass 11, count 2 2006.257.09:14:42.55#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.09:14:42.55#ibcon#[27=AT08-04\r\n] 2006.257.09:14:42.55#ibcon#*before write, iclass 11, count 2 2006.257.09:14:42.55#ibcon#enter sib2, iclass 11, count 2 2006.257.09:14:42.55#ibcon#flushed, iclass 11, count 2 2006.257.09:14:42.55#ibcon#about to write, iclass 11, count 2 2006.257.09:14:42.55#ibcon#wrote, iclass 11, count 2 2006.257.09:14:42.55#ibcon#about to read 3, iclass 11, count 2 2006.257.09:14:42.58#ibcon#read 3, iclass 11, count 2 2006.257.09:14:42.58#ibcon#about to read 4, iclass 11, count 2 2006.257.09:14:42.58#ibcon#read 4, iclass 11, count 2 2006.257.09:14:42.58#ibcon#about to read 5, iclass 11, count 2 2006.257.09:14:42.58#ibcon#read 5, iclass 11, count 2 2006.257.09:14:42.58#ibcon#about to read 6, iclass 11, count 2 2006.257.09:14:42.58#ibcon#read 6, iclass 11, count 2 2006.257.09:14:42.58#ibcon#end of sib2, iclass 11, count 2 2006.257.09:14:42.58#ibcon#*after write, iclass 11, count 2 2006.257.09:14:42.58#ibcon#*before return 0, iclass 11, count 2 2006.257.09:14:42.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:42.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:14:42.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.09:14:42.62#ibcon#ireg 7 cls_cnt 0 2006.257.09:14:42.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:42.70#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:42.70#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:42.70#ibcon#enter wrdev, iclass 11, count 0 2006.257.09:14:42.70#ibcon#first serial, iclass 11, count 0 2006.257.09:14:42.70#ibcon#enter sib2, iclass 11, count 0 2006.257.09:14:42.70#ibcon#flushed, iclass 11, count 0 2006.257.09:14:42.70#ibcon#about to write, iclass 11, count 0 2006.257.09:14:42.70#ibcon#wrote, iclass 11, count 0 2006.257.09:14:42.70#ibcon#about to read 3, iclass 11, count 0 2006.257.09:14:42.72#ibcon#read 3, iclass 11, count 0 2006.257.09:14:42.72#ibcon#about to read 4, iclass 11, count 0 2006.257.09:14:42.72#ibcon#read 4, iclass 11, count 0 2006.257.09:14:42.72#ibcon#about to read 5, iclass 11, count 0 2006.257.09:14:42.72#ibcon#read 5, iclass 11, count 0 2006.257.09:14:42.72#ibcon#about to read 6, iclass 11, count 0 2006.257.09:14:42.72#ibcon#read 6, iclass 11, count 0 2006.257.09:14:42.72#ibcon#end of sib2, iclass 11, count 0 2006.257.09:14:42.72#ibcon#*mode == 0, iclass 11, count 0 2006.257.09:14:42.72#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.09:14:42.72#ibcon#[27=USB\r\n] 2006.257.09:14:42.72#ibcon#*before write, iclass 11, count 0 2006.257.09:14:42.72#ibcon#enter sib2, iclass 11, count 0 2006.257.09:14:42.72#ibcon#flushed, iclass 11, count 0 2006.257.09:14:42.72#ibcon#about to write, iclass 11, count 0 2006.257.09:14:42.72#ibcon#wrote, iclass 11, count 0 2006.257.09:14:42.72#ibcon#about to read 3, iclass 11, count 0 2006.257.09:14:42.75#ibcon#read 3, iclass 11, count 0 2006.257.09:14:42.75#ibcon#about to read 4, iclass 11, count 0 2006.257.09:14:42.75#ibcon#read 4, iclass 11, count 0 2006.257.09:14:42.75#ibcon#about to read 5, iclass 11, count 0 2006.257.09:14:42.75#ibcon#read 5, iclass 11, count 0 2006.257.09:14:42.75#ibcon#about to read 6, iclass 11, count 0 2006.257.09:14:42.75#ibcon#read 6, iclass 11, count 0 2006.257.09:14:42.75#ibcon#end of sib2, iclass 11, count 0 2006.257.09:14:42.75#ibcon#*after write, iclass 11, count 0 2006.257.09:14:42.75#ibcon#*before return 0, iclass 11, count 0 2006.257.09:14:42.75#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:42.75#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:14:42.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.09:14:42.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.09:14:42.75$vck44/vabw=wide 2006.257.09:14:42.75#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.09:14:42.75#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.09:14:42.75#ibcon#ireg 8 cls_cnt 0 2006.257.09:14:42.75#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:42.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:42.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:42.75#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:14:42.75#ibcon#first serial, iclass 13, count 0 2006.257.09:14:42.75#ibcon#enter sib2, iclass 13, count 0 2006.257.09:14:42.75#ibcon#flushed, iclass 13, count 0 2006.257.09:14:42.75#ibcon#about to write, iclass 13, count 0 2006.257.09:14:42.75#ibcon#wrote, iclass 13, count 0 2006.257.09:14:42.75#ibcon#about to read 3, iclass 13, count 0 2006.257.09:14:42.77#ibcon#read 3, iclass 13, count 0 2006.257.09:14:42.77#ibcon#about to read 4, iclass 13, count 0 2006.257.09:14:42.77#ibcon#read 4, iclass 13, count 0 2006.257.09:14:42.77#ibcon#about to read 5, iclass 13, count 0 2006.257.09:14:42.77#ibcon#read 5, iclass 13, count 0 2006.257.09:14:42.77#ibcon#about to read 6, iclass 13, count 0 2006.257.09:14:42.77#ibcon#read 6, iclass 13, count 0 2006.257.09:14:42.77#ibcon#end of sib2, iclass 13, count 0 2006.257.09:14:42.77#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:14:42.77#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:14:42.77#ibcon#[25=BW32\r\n] 2006.257.09:14:42.77#ibcon#*before write, iclass 13, count 0 2006.257.09:14:42.77#ibcon#enter sib2, iclass 13, count 0 2006.257.09:14:42.77#ibcon#flushed, iclass 13, count 0 2006.257.09:14:42.77#ibcon#about to write, iclass 13, count 0 2006.257.09:14:42.77#ibcon#wrote, iclass 13, count 0 2006.257.09:14:42.77#ibcon#about to read 3, iclass 13, count 0 2006.257.09:14:42.80#ibcon#read 3, iclass 13, count 0 2006.257.09:14:42.80#ibcon#about to read 4, iclass 13, count 0 2006.257.09:14:42.80#ibcon#read 4, iclass 13, count 0 2006.257.09:14:42.80#ibcon#about to read 5, iclass 13, count 0 2006.257.09:14:42.80#ibcon#read 5, iclass 13, count 0 2006.257.09:14:42.80#ibcon#about to read 6, iclass 13, count 0 2006.257.09:14:42.80#ibcon#read 6, iclass 13, count 0 2006.257.09:14:42.80#ibcon#end of sib2, iclass 13, count 0 2006.257.09:14:42.80#ibcon#*after write, iclass 13, count 0 2006.257.09:14:42.80#ibcon#*before return 0, iclass 13, count 0 2006.257.09:14:42.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:42.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:14:42.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:14:42.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:14:42.80$vck44/vbbw=wide 2006.257.09:14:42.80#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.09:14:42.80#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.09:14:42.80#ibcon#ireg 8 cls_cnt 0 2006.257.09:14:42.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:14:42.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:14:42.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:14:42.87#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:14:42.87#ibcon#first serial, iclass 15, count 0 2006.257.09:14:42.87#ibcon#enter sib2, iclass 15, count 0 2006.257.09:14:42.87#ibcon#flushed, iclass 15, count 0 2006.257.09:14:42.87#ibcon#about to write, iclass 15, count 0 2006.257.09:14:42.87#ibcon#wrote, iclass 15, count 0 2006.257.09:14:42.87#ibcon#about to read 3, iclass 15, count 0 2006.257.09:14:42.89#ibcon#read 3, iclass 15, count 0 2006.257.09:14:42.89#ibcon#about to read 4, iclass 15, count 0 2006.257.09:14:42.89#ibcon#read 4, iclass 15, count 0 2006.257.09:14:42.89#ibcon#about to read 5, iclass 15, count 0 2006.257.09:14:42.89#ibcon#read 5, iclass 15, count 0 2006.257.09:14:42.89#ibcon#about to read 6, iclass 15, count 0 2006.257.09:14:42.89#ibcon#read 6, iclass 15, count 0 2006.257.09:14:42.89#ibcon#end of sib2, iclass 15, count 0 2006.257.09:14:42.89#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:14:42.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:14:42.89#ibcon#[27=BW32\r\n] 2006.257.09:14:42.89#ibcon#*before write, iclass 15, count 0 2006.257.09:14:42.89#ibcon#enter sib2, iclass 15, count 0 2006.257.09:14:42.89#ibcon#flushed, iclass 15, count 0 2006.257.09:14:42.89#ibcon#about to write, iclass 15, count 0 2006.257.09:14:42.89#ibcon#wrote, iclass 15, count 0 2006.257.09:14:42.89#ibcon#about to read 3, iclass 15, count 0 2006.257.09:14:42.92#ibcon#read 3, iclass 15, count 0 2006.257.09:14:42.92#ibcon#about to read 4, iclass 15, count 0 2006.257.09:14:42.92#ibcon#read 4, iclass 15, count 0 2006.257.09:14:42.92#ibcon#about to read 5, iclass 15, count 0 2006.257.09:14:42.92#ibcon#read 5, iclass 15, count 0 2006.257.09:14:42.92#ibcon#about to read 6, iclass 15, count 0 2006.257.09:14:42.92#ibcon#read 6, iclass 15, count 0 2006.257.09:14:42.92#ibcon#end of sib2, iclass 15, count 0 2006.257.09:14:42.92#ibcon#*after write, iclass 15, count 0 2006.257.09:14:42.92#ibcon#*before return 0, iclass 15, count 0 2006.257.09:14:42.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:14:42.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:14:42.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:14:42.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:14:42.92$setupk4/ifdk4 2006.257.09:14:42.92$ifdk4/lo= 2006.257.09:14:42.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:14:42.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:14:42.92$ifdk4/patch= 2006.257.09:14:42.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:14:42.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:14:42.92$setupk4/!*+20s 2006.257.09:14:44.32#abcon#<5=/14 1.0 2.2 19.89 951013.2\r\n> 2006.257.09:14:44.34#abcon#{5=INTERFACE CLEAR} 2006.257.09:14:44.40#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:14:54.49#abcon#<5=/14 1.0 2.2 19.89 951013.2\r\n> 2006.257.09:14:54.51#abcon#{5=INTERFACE CLEAR} 2006.257.09:14:54.57#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:14:57.38$setupk4/"tpicd 2006.257.09:14:57.38$setupk4/echo=off 2006.257.09:14:57.38$setupk4/xlog=off 2006.257.09:14:57.38:!2006.257.09:18:54 2006.257.09:15:01.13#trakl#Source acquired 2006.257.09:15:02.13#flagr#flagr/antenna,acquired 2006.257.09:18:54.00:preob 2006.257.09:18:54.14/onsource/TRACKING 2006.257.09:18:54.14:!2006.257.09:19:04 2006.257.09:19:04.00:"tape 2006.257.09:19:04.00:"st=record 2006.257.09:19:04.00:data_valid=on 2006.257.09:19:04.00:midob 2006.257.09:19:05.14/onsource/TRACKING 2006.257.09:19:05.14/wx/19.80,1013.2,95 2006.257.09:19:05.28/cable/+6.4756E-03 2006.257.09:19:06.37/va/01,08,usb,yes,36,39 2006.257.09:19:06.37/va/02,07,usb,yes,39,40 2006.257.09:19:06.37/va/03,08,usb,yes,36,37 2006.257.09:19:06.37/va/04,07,usb,yes,41,43 2006.257.09:19:06.37/va/05,04,usb,yes,36,37 2006.257.09:19:06.37/va/06,04,usb,yes,40,40 2006.257.09:19:06.37/va/07,04,usb,yes,41,42 2006.257.09:19:06.37/va/08,04,usb,yes,35,42 2006.257.09:19:06.60/valo/01,524.99,yes,locked 2006.257.09:19:06.60/valo/02,534.99,yes,locked 2006.257.09:19:06.60/valo/03,564.99,yes,locked 2006.257.09:19:06.60/valo/04,624.99,yes,locked 2006.257.09:19:06.60/valo/05,734.99,yes,locked 2006.257.09:19:06.60/valo/06,814.99,yes,locked 2006.257.09:19:06.60/valo/07,864.99,yes,locked 2006.257.09:19:06.60/valo/08,884.99,yes,locked 2006.257.09:19:07.69/vb/01,04,usb,yes,39,36 2006.257.09:19:07.69/vb/02,05,usb,yes,37,36 2006.257.09:19:07.69/vb/03,04,usb,yes,38,41 2006.257.09:19:07.69/vb/04,05,usb,yes,38,37 2006.257.09:19:07.69/vb/05,04,usb,yes,34,37 2006.257.09:19:07.69/vb/06,04,usb,yes,39,35 2006.257.09:19:07.69/vb/07,04,usb,yes,39,39 2006.257.09:19:07.69/vb/08,04,usb,yes,35,40 2006.257.09:19:07.93/vblo/01,629.99,yes,locked 2006.257.09:19:07.93/vblo/02,634.99,yes,locked 2006.257.09:19:07.93/vblo/03,649.99,yes,locked 2006.257.09:19:07.93/vblo/04,679.99,yes,locked 2006.257.09:19:07.93/vblo/05,709.99,yes,locked 2006.257.09:19:07.93/vblo/06,719.99,yes,locked 2006.257.09:19:07.93/vblo/07,734.99,yes,locked 2006.257.09:19:07.93/vblo/08,744.99,yes,locked 2006.257.09:19:08.08/vabw/8 2006.257.09:19:08.23/vbbw/8 2006.257.09:19:08.32/xfe/off,on,15.2 2006.257.09:19:08.69/ifatt/23,28,28,28 2006.257.09:19:09.07/fmout-gps/S +4.62E-07 2006.257.09:19:09.11:!2006.257.09:21:14 2006.257.09:21:14.01:data_valid=off 2006.257.09:21:14.01:"et 2006.257.09:21:14.01:!+3s 2006.257.09:21:17.02:"tape 2006.257.09:21:17.02:postob 2006.257.09:21:17.11/cable/+6.4749E-03 2006.257.09:21:17.11/wx/19.76,1013.2,95 2006.257.09:21:17.17/fmout-gps/S +4.61E-07 2006.257.09:21:17.17:scan_name=257-0925,jd0609,220 2006.257.09:21:17.17:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.257.09:21:19.14#flagr#flagr/antenna,new-source 2006.257.09:21:19.14:checkk5 2006.257.09:21:19.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:21:19.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:21:20.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:21:20.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:21:21.13/chk_obsdata//k5ts1/T2570919??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.09:21:21.55/chk_obsdata//k5ts2/T2570919??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.09:21:21.95/chk_obsdata//k5ts3/T2570919??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.09:21:22.35/chk_obsdata//k5ts4/T2570919??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.09:21:23.06/k5log//k5ts1_log_newline 2006.257.09:21:23.78/k5log//k5ts2_log_newline 2006.257.09:21:24.50/k5log//k5ts3_log_newline 2006.257.09:21:25.19/k5log//k5ts4_log_newline 2006.257.09:21:25.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:21:25.22:setupk4=1 2006.257.09:21:25.22$setupk4/echo=on 2006.257.09:21:25.22$setupk4/pcalon 2006.257.09:21:25.22$pcalon/"no phase cal control is implemented here 2006.257.09:21:25.22$setupk4/"tpicd=stop 2006.257.09:21:25.22$setupk4/"rec=synch_on 2006.257.09:21:25.22$setupk4/"rec_mode=128 2006.257.09:21:25.22$setupk4/!* 2006.257.09:21:25.22$setupk4/recpk4 2006.257.09:21:25.22$recpk4/recpatch= 2006.257.09:21:25.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:21:25.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:21:25.22$setupk4/vck44 2006.257.09:21:25.22$vck44/valo=1,524.99 2006.257.09:21:25.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.09:21:25.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.09:21:25.22#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:25.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:25.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:25.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:25.22#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:21:25.22#ibcon#first serial, iclass 36, count 0 2006.257.09:21:25.22#ibcon#enter sib2, iclass 36, count 0 2006.257.09:21:25.22#ibcon#flushed, iclass 36, count 0 2006.257.09:21:25.22#ibcon#about to write, iclass 36, count 0 2006.257.09:21:25.22#ibcon#wrote, iclass 36, count 0 2006.257.09:21:25.22#ibcon#about to read 3, iclass 36, count 0 2006.257.09:21:25.24#ibcon#read 3, iclass 36, count 0 2006.257.09:21:25.24#ibcon#about to read 4, iclass 36, count 0 2006.257.09:21:25.24#ibcon#read 4, iclass 36, count 0 2006.257.09:21:25.24#ibcon#about to read 5, iclass 36, count 0 2006.257.09:21:25.24#ibcon#read 5, iclass 36, count 0 2006.257.09:21:25.24#ibcon#about to read 6, iclass 36, count 0 2006.257.09:21:25.24#ibcon#read 6, iclass 36, count 0 2006.257.09:21:25.24#ibcon#end of sib2, iclass 36, count 0 2006.257.09:21:25.24#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:21:25.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:21:25.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:21:25.24#ibcon#*before write, iclass 36, count 0 2006.257.09:21:25.24#ibcon#enter sib2, iclass 36, count 0 2006.257.09:21:25.24#ibcon#flushed, iclass 36, count 0 2006.257.09:21:25.24#ibcon#about to write, iclass 36, count 0 2006.257.09:21:25.24#ibcon#wrote, iclass 36, count 0 2006.257.09:21:25.24#ibcon#about to read 3, iclass 36, count 0 2006.257.09:21:25.29#ibcon#read 3, iclass 36, count 0 2006.257.09:21:25.29#ibcon#about to read 4, iclass 36, count 0 2006.257.09:21:25.29#ibcon#read 4, iclass 36, count 0 2006.257.09:21:25.29#ibcon#about to read 5, iclass 36, count 0 2006.257.09:21:25.29#ibcon#read 5, iclass 36, count 0 2006.257.09:21:25.29#ibcon#about to read 6, iclass 36, count 0 2006.257.09:21:25.29#ibcon#read 6, iclass 36, count 0 2006.257.09:21:25.29#ibcon#end of sib2, iclass 36, count 0 2006.257.09:21:25.29#ibcon#*after write, iclass 36, count 0 2006.257.09:21:25.29#ibcon#*before return 0, iclass 36, count 0 2006.257.09:21:25.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:25.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:25.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:21:25.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:21:25.29$vck44/va=1,8 2006.257.09:21:25.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.09:21:25.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.09:21:25.29#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:25.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:25.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:25.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:25.29#ibcon#enter wrdev, iclass 38, count 2 2006.257.09:21:25.29#ibcon#first serial, iclass 38, count 2 2006.257.09:21:25.29#ibcon#enter sib2, iclass 38, count 2 2006.257.09:21:25.29#ibcon#flushed, iclass 38, count 2 2006.257.09:21:25.29#ibcon#about to write, iclass 38, count 2 2006.257.09:21:25.29#ibcon#wrote, iclass 38, count 2 2006.257.09:21:25.29#ibcon#about to read 3, iclass 38, count 2 2006.257.09:21:25.31#ibcon#read 3, iclass 38, count 2 2006.257.09:21:25.31#ibcon#about to read 4, iclass 38, count 2 2006.257.09:21:25.31#ibcon#read 4, iclass 38, count 2 2006.257.09:21:25.31#ibcon#about to read 5, iclass 38, count 2 2006.257.09:21:25.31#ibcon#read 5, iclass 38, count 2 2006.257.09:21:25.31#ibcon#about to read 6, iclass 38, count 2 2006.257.09:21:25.31#ibcon#read 6, iclass 38, count 2 2006.257.09:21:25.31#ibcon#end of sib2, iclass 38, count 2 2006.257.09:21:25.31#ibcon#*mode == 0, iclass 38, count 2 2006.257.09:21:25.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.09:21:25.31#ibcon#[25=AT01-08\r\n] 2006.257.09:21:25.31#ibcon#*before write, iclass 38, count 2 2006.257.09:21:25.31#ibcon#enter sib2, iclass 38, count 2 2006.257.09:21:25.31#ibcon#flushed, iclass 38, count 2 2006.257.09:21:25.31#ibcon#about to write, iclass 38, count 2 2006.257.09:21:25.31#ibcon#wrote, iclass 38, count 2 2006.257.09:21:25.31#ibcon#about to read 3, iclass 38, count 2 2006.257.09:21:25.34#ibcon#read 3, iclass 38, count 2 2006.257.09:21:25.34#ibcon#about to read 4, iclass 38, count 2 2006.257.09:21:25.34#ibcon#read 4, iclass 38, count 2 2006.257.09:21:25.34#ibcon#about to read 5, iclass 38, count 2 2006.257.09:21:25.34#ibcon#read 5, iclass 38, count 2 2006.257.09:21:25.34#ibcon#about to read 6, iclass 38, count 2 2006.257.09:21:25.34#ibcon#read 6, iclass 38, count 2 2006.257.09:21:25.34#ibcon#end of sib2, iclass 38, count 2 2006.257.09:21:25.34#ibcon#*after write, iclass 38, count 2 2006.257.09:21:25.34#ibcon#*before return 0, iclass 38, count 2 2006.257.09:21:25.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:25.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:25.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.09:21:25.34#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:25.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:25.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:25.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:25.46#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:21:25.46#ibcon#first serial, iclass 38, count 0 2006.257.09:21:25.46#ibcon#enter sib2, iclass 38, count 0 2006.257.09:21:25.46#ibcon#flushed, iclass 38, count 0 2006.257.09:21:25.46#ibcon#about to write, iclass 38, count 0 2006.257.09:21:25.46#ibcon#wrote, iclass 38, count 0 2006.257.09:21:25.46#ibcon#about to read 3, iclass 38, count 0 2006.257.09:21:25.48#ibcon#read 3, iclass 38, count 0 2006.257.09:21:25.48#ibcon#about to read 4, iclass 38, count 0 2006.257.09:21:25.48#ibcon#read 4, iclass 38, count 0 2006.257.09:21:25.48#ibcon#about to read 5, iclass 38, count 0 2006.257.09:21:25.48#ibcon#read 5, iclass 38, count 0 2006.257.09:21:25.48#ibcon#about to read 6, iclass 38, count 0 2006.257.09:21:25.48#ibcon#read 6, iclass 38, count 0 2006.257.09:21:25.48#ibcon#end of sib2, iclass 38, count 0 2006.257.09:21:25.48#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:21:25.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:21:25.48#ibcon#[25=USB\r\n] 2006.257.09:21:25.48#ibcon#*before write, iclass 38, count 0 2006.257.09:21:25.48#ibcon#enter sib2, iclass 38, count 0 2006.257.09:21:25.48#ibcon#flushed, iclass 38, count 0 2006.257.09:21:25.48#ibcon#about to write, iclass 38, count 0 2006.257.09:21:25.48#ibcon#wrote, iclass 38, count 0 2006.257.09:21:25.48#ibcon#about to read 3, iclass 38, count 0 2006.257.09:21:25.51#ibcon#read 3, iclass 38, count 0 2006.257.09:21:25.51#ibcon#about to read 4, iclass 38, count 0 2006.257.09:21:25.51#ibcon#read 4, iclass 38, count 0 2006.257.09:21:25.51#ibcon#about to read 5, iclass 38, count 0 2006.257.09:21:25.51#ibcon#read 5, iclass 38, count 0 2006.257.09:21:25.51#ibcon#about to read 6, iclass 38, count 0 2006.257.09:21:25.51#ibcon#read 6, iclass 38, count 0 2006.257.09:21:25.51#ibcon#end of sib2, iclass 38, count 0 2006.257.09:21:25.51#ibcon#*after write, iclass 38, count 0 2006.257.09:21:25.51#ibcon#*before return 0, iclass 38, count 0 2006.257.09:21:25.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:25.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:25.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:21:25.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:21:25.51$vck44/valo=2,534.99 2006.257.09:21:25.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.09:21:25.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.09:21:25.51#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:25.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:25.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:25.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:25.51#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:21:25.51#ibcon#first serial, iclass 40, count 0 2006.257.09:21:25.51#ibcon#enter sib2, iclass 40, count 0 2006.257.09:21:25.51#ibcon#flushed, iclass 40, count 0 2006.257.09:21:25.51#ibcon#about to write, iclass 40, count 0 2006.257.09:21:25.51#ibcon#wrote, iclass 40, count 0 2006.257.09:21:25.51#ibcon#about to read 3, iclass 40, count 0 2006.257.09:21:25.53#ibcon#read 3, iclass 40, count 0 2006.257.09:21:25.53#ibcon#about to read 4, iclass 40, count 0 2006.257.09:21:25.53#ibcon#read 4, iclass 40, count 0 2006.257.09:21:25.53#ibcon#about to read 5, iclass 40, count 0 2006.257.09:21:25.53#ibcon#read 5, iclass 40, count 0 2006.257.09:21:25.53#ibcon#about to read 6, iclass 40, count 0 2006.257.09:21:25.53#ibcon#read 6, iclass 40, count 0 2006.257.09:21:25.53#ibcon#end of sib2, iclass 40, count 0 2006.257.09:21:25.53#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:21:25.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:21:25.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:21:25.53#ibcon#*before write, iclass 40, count 0 2006.257.09:21:25.53#ibcon#enter sib2, iclass 40, count 0 2006.257.09:21:25.53#ibcon#flushed, iclass 40, count 0 2006.257.09:21:25.53#ibcon#about to write, iclass 40, count 0 2006.257.09:21:25.53#ibcon#wrote, iclass 40, count 0 2006.257.09:21:25.53#ibcon#about to read 3, iclass 40, count 0 2006.257.09:21:25.57#ibcon#read 3, iclass 40, count 0 2006.257.09:21:25.57#ibcon#about to read 4, iclass 40, count 0 2006.257.09:21:25.57#ibcon#read 4, iclass 40, count 0 2006.257.09:21:25.57#ibcon#about to read 5, iclass 40, count 0 2006.257.09:21:25.57#ibcon#read 5, iclass 40, count 0 2006.257.09:21:25.57#ibcon#about to read 6, iclass 40, count 0 2006.257.09:21:25.57#ibcon#read 6, iclass 40, count 0 2006.257.09:21:25.57#ibcon#end of sib2, iclass 40, count 0 2006.257.09:21:25.57#ibcon#*after write, iclass 40, count 0 2006.257.09:21:25.57#ibcon#*before return 0, iclass 40, count 0 2006.257.09:21:25.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:25.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:25.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:21:25.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:21:25.57$vck44/va=2,7 2006.257.09:21:25.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.09:21:25.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.09:21:25.57#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:25.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:25.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:25.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:25.63#ibcon#enter wrdev, iclass 4, count 2 2006.257.09:21:25.63#ibcon#first serial, iclass 4, count 2 2006.257.09:21:25.63#ibcon#enter sib2, iclass 4, count 2 2006.257.09:21:25.63#ibcon#flushed, iclass 4, count 2 2006.257.09:21:25.63#ibcon#about to write, iclass 4, count 2 2006.257.09:21:25.63#ibcon#wrote, iclass 4, count 2 2006.257.09:21:25.63#ibcon#about to read 3, iclass 4, count 2 2006.257.09:21:25.65#ibcon#read 3, iclass 4, count 2 2006.257.09:21:25.65#ibcon#about to read 4, iclass 4, count 2 2006.257.09:21:25.65#ibcon#read 4, iclass 4, count 2 2006.257.09:21:25.65#ibcon#about to read 5, iclass 4, count 2 2006.257.09:21:25.65#ibcon#read 5, iclass 4, count 2 2006.257.09:21:25.65#ibcon#about to read 6, iclass 4, count 2 2006.257.09:21:25.65#ibcon#read 6, iclass 4, count 2 2006.257.09:21:25.65#ibcon#end of sib2, iclass 4, count 2 2006.257.09:21:25.65#ibcon#*mode == 0, iclass 4, count 2 2006.257.09:21:25.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.09:21:25.65#ibcon#[25=AT02-07\r\n] 2006.257.09:21:25.65#ibcon#*before write, iclass 4, count 2 2006.257.09:21:25.65#ibcon#enter sib2, iclass 4, count 2 2006.257.09:21:25.65#ibcon#flushed, iclass 4, count 2 2006.257.09:21:25.65#ibcon#about to write, iclass 4, count 2 2006.257.09:21:25.65#ibcon#wrote, iclass 4, count 2 2006.257.09:21:25.65#ibcon#about to read 3, iclass 4, count 2 2006.257.09:21:25.68#ibcon#read 3, iclass 4, count 2 2006.257.09:21:25.68#ibcon#about to read 4, iclass 4, count 2 2006.257.09:21:25.68#ibcon#read 4, iclass 4, count 2 2006.257.09:21:25.68#ibcon#about to read 5, iclass 4, count 2 2006.257.09:21:25.68#ibcon#read 5, iclass 4, count 2 2006.257.09:21:25.68#ibcon#about to read 6, iclass 4, count 2 2006.257.09:21:25.68#ibcon#read 6, iclass 4, count 2 2006.257.09:21:25.68#ibcon#end of sib2, iclass 4, count 2 2006.257.09:21:25.68#ibcon#*after write, iclass 4, count 2 2006.257.09:21:25.68#ibcon#*before return 0, iclass 4, count 2 2006.257.09:21:25.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:25.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:25.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.09:21:25.68#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:25.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:25.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:25.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:25.80#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:21:25.80#ibcon#first serial, iclass 4, count 0 2006.257.09:21:25.80#ibcon#enter sib2, iclass 4, count 0 2006.257.09:21:25.80#ibcon#flushed, iclass 4, count 0 2006.257.09:21:25.80#ibcon#about to write, iclass 4, count 0 2006.257.09:21:25.80#ibcon#wrote, iclass 4, count 0 2006.257.09:21:25.80#ibcon#about to read 3, iclass 4, count 0 2006.257.09:21:25.82#ibcon#read 3, iclass 4, count 0 2006.257.09:21:25.82#ibcon#about to read 4, iclass 4, count 0 2006.257.09:21:25.82#ibcon#read 4, iclass 4, count 0 2006.257.09:21:25.82#ibcon#about to read 5, iclass 4, count 0 2006.257.09:21:25.82#ibcon#read 5, iclass 4, count 0 2006.257.09:21:25.82#ibcon#about to read 6, iclass 4, count 0 2006.257.09:21:25.82#ibcon#read 6, iclass 4, count 0 2006.257.09:21:25.82#ibcon#end of sib2, iclass 4, count 0 2006.257.09:21:25.82#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:21:25.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:21:25.82#ibcon#[25=USB\r\n] 2006.257.09:21:25.82#ibcon#*before write, iclass 4, count 0 2006.257.09:21:25.82#ibcon#enter sib2, iclass 4, count 0 2006.257.09:21:25.82#ibcon#flushed, iclass 4, count 0 2006.257.09:21:25.82#ibcon#about to write, iclass 4, count 0 2006.257.09:21:25.82#ibcon#wrote, iclass 4, count 0 2006.257.09:21:25.82#ibcon#about to read 3, iclass 4, count 0 2006.257.09:21:25.85#ibcon#read 3, iclass 4, count 0 2006.257.09:21:25.85#ibcon#about to read 4, iclass 4, count 0 2006.257.09:21:25.85#ibcon#read 4, iclass 4, count 0 2006.257.09:21:25.85#ibcon#about to read 5, iclass 4, count 0 2006.257.09:21:25.85#ibcon#read 5, iclass 4, count 0 2006.257.09:21:25.85#ibcon#about to read 6, iclass 4, count 0 2006.257.09:21:25.85#ibcon#read 6, iclass 4, count 0 2006.257.09:21:25.85#ibcon#end of sib2, iclass 4, count 0 2006.257.09:21:25.85#ibcon#*after write, iclass 4, count 0 2006.257.09:21:25.85#ibcon#*before return 0, iclass 4, count 0 2006.257.09:21:25.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:25.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:25.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:21:25.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:21:25.85$vck44/valo=3,564.99 2006.257.09:21:25.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.09:21:25.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.09:21:25.85#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:25.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:25.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:25.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:25.85#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:21:25.85#ibcon#first serial, iclass 6, count 0 2006.257.09:21:25.85#ibcon#enter sib2, iclass 6, count 0 2006.257.09:21:25.85#ibcon#flushed, iclass 6, count 0 2006.257.09:21:25.85#ibcon#about to write, iclass 6, count 0 2006.257.09:21:25.85#ibcon#wrote, iclass 6, count 0 2006.257.09:21:25.85#ibcon#about to read 3, iclass 6, count 0 2006.257.09:21:25.87#ibcon#read 3, iclass 6, count 0 2006.257.09:21:25.87#ibcon#about to read 4, iclass 6, count 0 2006.257.09:21:25.87#ibcon#read 4, iclass 6, count 0 2006.257.09:21:25.87#ibcon#about to read 5, iclass 6, count 0 2006.257.09:21:25.87#ibcon#read 5, iclass 6, count 0 2006.257.09:21:25.87#ibcon#about to read 6, iclass 6, count 0 2006.257.09:21:25.87#ibcon#read 6, iclass 6, count 0 2006.257.09:21:25.87#ibcon#end of sib2, iclass 6, count 0 2006.257.09:21:25.87#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:21:25.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:21:25.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:21:25.87#ibcon#*before write, iclass 6, count 0 2006.257.09:21:25.87#ibcon#enter sib2, iclass 6, count 0 2006.257.09:21:25.87#ibcon#flushed, iclass 6, count 0 2006.257.09:21:25.87#ibcon#about to write, iclass 6, count 0 2006.257.09:21:25.87#ibcon#wrote, iclass 6, count 0 2006.257.09:21:25.87#ibcon#about to read 3, iclass 6, count 0 2006.257.09:21:25.91#ibcon#read 3, iclass 6, count 0 2006.257.09:21:25.91#ibcon#about to read 4, iclass 6, count 0 2006.257.09:21:25.91#ibcon#read 4, iclass 6, count 0 2006.257.09:21:25.91#ibcon#about to read 5, iclass 6, count 0 2006.257.09:21:25.91#ibcon#read 5, iclass 6, count 0 2006.257.09:21:25.91#ibcon#about to read 6, iclass 6, count 0 2006.257.09:21:25.91#ibcon#read 6, iclass 6, count 0 2006.257.09:21:25.91#ibcon#end of sib2, iclass 6, count 0 2006.257.09:21:25.91#ibcon#*after write, iclass 6, count 0 2006.257.09:21:25.91#ibcon#*before return 0, iclass 6, count 0 2006.257.09:21:25.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:25.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:25.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:21:25.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:21:25.91$vck44/va=3,8 2006.257.09:21:25.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.09:21:25.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.09:21:25.91#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:25.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:25.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:25.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:25.97#ibcon#enter wrdev, iclass 10, count 2 2006.257.09:21:25.97#ibcon#first serial, iclass 10, count 2 2006.257.09:21:25.97#ibcon#enter sib2, iclass 10, count 2 2006.257.09:21:25.97#ibcon#flushed, iclass 10, count 2 2006.257.09:21:25.97#ibcon#about to write, iclass 10, count 2 2006.257.09:21:25.97#ibcon#wrote, iclass 10, count 2 2006.257.09:21:25.97#ibcon#about to read 3, iclass 10, count 2 2006.257.09:21:25.99#ibcon#read 3, iclass 10, count 2 2006.257.09:21:25.99#ibcon#about to read 4, iclass 10, count 2 2006.257.09:21:25.99#ibcon#read 4, iclass 10, count 2 2006.257.09:21:25.99#ibcon#about to read 5, iclass 10, count 2 2006.257.09:21:25.99#ibcon#read 5, iclass 10, count 2 2006.257.09:21:25.99#ibcon#about to read 6, iclass 10, count 2 2006.257.09:21:25.99#ibcon#read 6, iclass 10, count 2 2006.257.09:21:25.99#ibcon#end of sib2, iclass 10, count 2 2006.257.09:21:25.99#ibcon#*mode == 0, iclass 10, count 2 2006.257.09:21:25.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.09:21:25.99#ibcon#[25=AT03-08\r\n] 2006.257.09:21:25.99#ibcon#*before write, iclass 10, count 2 2006.257.09:21:25.99#ibcon#enter sib2, iclass 10, count 2 2006.257.09:21:25.99#ibcon#flushed, iclass 10, count 2 2006.257.09:21:25.99#ibcon#about to write, iclass 10, count 2 2006.257.09:21:25.99#ibcon#wrote, iclass 10, count 2 2006.257.09:21:25.99#ibcon#about to read 3, iclass 10, count 2 2006.257.09:21:26.02#ibcon#read 3, iclass 10, count 2 2006.257.09:21:26.02#ibcon#about to read 4, iclass 10, count 2 2006.257.09:21:26.02#ibcon#read 4, iclass 10, count 2 2006.257.09:21:26.02#ibcon#about to read 5, iclass 10, count 2 2006.257.09:21:26.02#ibcon#read 5, iclass 10, count 2 2006.257.09:21:26.02#ibcon#about to read 6, iclass 10, count 2 2006.257.09:21:26.02#ibcon#read 6, iclass 10, count 2 2006.257.09:21:26.02#ibcon#end of sib2, iclass 10, count 2 2006.257.09:21:26.02#ibcon#*after write, iclass 10, count 2 2006.257.09:21:26.02#ibcon#*before return 0, iclass 10, count 2 2006.257.09:21:26.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:26.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:26.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.09:21:26.02#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:26.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:26.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:26.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:26.14#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:21:26.14#ibcon#first serial, iclass 10, count 0 2006.257.09:21:26.14#ibcon#enter sib2, iclass 10, count 0 2006.257.09:21:26.14#ibcon#flushed, iclass 10, count 0 2006.257.09:21:26.14#ibcon#about to write, iclass 10, count 0 2006.257.09:21:26.14#ibcon#wrote, iclass 10, count 0 2006.257.09:21:26.14#ibcon#about to read 3, iclass 10, count 0 2006.257.09:21:26.16#ibcon#read 3, iclass 10, count 0 2006.257.09:21:26.16#ibcon#about to read 4, iclass 10, count 0 2006.257.09:21:26.16#ibcon#read 4, iclass 10, count 0 2006.257.09:21:26.16#ibcon#about to read 5, iclass 10, count 0 2006.257.09:21:26.16#ibcon#read 5, iclass 10, count 0 2006.257.09:21:26.16#ibcon#about to read 6, iclass 10, count 0 2006.257.09:21:26.16#ibcon#read 6, iclass 10, count 0 2006.257.09:21:26.16#ibcon#end of sib2, iclass 10, count 0 2006.257.09:21:26.16#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:21:26.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:21:26.16#ibcon#[25=USB\r\n] 2006.257.09:21:26.16#ibcon#*before write, iclass 10, count 0 2006.257.09:21:26.16#ibcon#enter sib2, iclass 10, count 0 2006.257.09:21:26.16#ibcon#flushed, iclass 10, count 0 2006.257.09:21:26.16#ibcon#about to write, iclass 10, count 0 2006.257.09:21:26.16#ibcon#wrote, iclass 10, count 0 2006.257.09:21:26.16#ibcon#about to read 3, iclass 10, count 0 2006.257.09:21:26.19#ibcon#read 3, iclass 10, count 0 2006.257.09:21:26.19#ibcon#about to read 4, iclass 10, count 0 2006.257.09:21:26.19#ibcon#read 4, iclass 10, count 0 2006.257.09:21:26.19#ibcon#about to read 5, iclass 10, count 0 2006.257.09:21:26.19#ibcon#read 5, iclass 10, count 0 2006.257.09:21:26.19#ibcon#about to read 6, iclass 10, count 0 2006.257.09:21:26.19#ibcon#read 6, iclass 10, count 0 2006.257.09:21:26.19#ibcon#end of sib2, iclass 10, count 0 2006.257.09:21:26.19#ibcon#*after write, iclass 10, count 0 2006.257.09:21:26.19#ibcon#*before return 0, iclass 10, count 0 2006.257.09:21:26.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:26.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:26.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:21:26.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:21:26.19$vck44/valo=4,624.99 2006.257.09:21:26.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.09:21:26.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.09:21:26.19#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:26.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:26.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:26.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:26.19#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:21:26.19#ibcon#first serial, iclass 12, count 0 2006.257.09:21:26.19#ibcon#enter sib2, iclass 12, count 0 2006.257.09:21:26.19#ibcon#flushed, iclass 12, count 0 2006.257.09:21:26.19#ibcon#about to write, iclass 12, count 0 2006.257.09:21:26.19#ibcon#wrote, iclass 12, count 0 2006.257.09:21:26.19#ibcon#about to read 3, iclass 12, count 0 2006.257.09:21:26.21#ibcon#read 3, iclass 12, count 0 2006.257.09:21:26.21#ibcon#about to read 4, iclass 12, count 0 2006.257.09:21:26.21#ibcon#read 4, iclass 12, count 0 2006.257.09:21:26.21#ibcon#about to read 5, iclass 12, count 0 2006.257.09:21:26.21#ibcon#read 5, iclass 12, count 0 2006.257.09:21:26.21#ibcon#about to read 6, iclass 12, count 0 2006.257.09:21:26.21#ibcon#read 6, iclass 12, count 0 2006.257.09:21:26.21#ibcon#end of sib2, iclass 12, count 0 2006.257.09:21:26.21#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:21:26.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:21:26.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:21:26.21#ibcon#*before write, iclass 12, count 0 2006.257.09:21:26.21#ibcon#enter sib2, iclass 12, count 0 2006.257.09:21:26.21#ibcon#flushed, iclass 12, count 0 2006.257.09:21:26.21#ibcon#about to write, iclass 12, count 0 2006.257.09:21:26.21#ibcon#wrote, iclass 12, count 0 2006.257.09:21:26.21#ibcon#about to read 3, iclass 12, count 0 2006.257.09:21:26.25#ibcon#read 3, iclass 12, count 0 2006.257.09:21:26.25#ibcon#about to read 4, iclass 12, count 0 2006.257.09:21:26.25#ibcon#read 4, iclass 12, count 0 2006.257.09:21:26.25#ibcon#about to read 5, iclass 12, count 0 2006.257.09:21:26.25#ibcon#read 5, iclass 12, count 0 2006.257.09:21:26.25#ibcon#about to read 6, iclass 12, count 0 2006.257.09:21:26.25#ibcon#read 6, iclass 12, count 0 2006.257.09:21:26.25#ibcon#end of sib2, iclass 12, count 0 2006.257.09:21:26.25#ibcon#*after write, iclass 12, count 0 2006.257.09:21:26.25#ibcon#*before return 0, iclass 12, count 0 2006.257.09:21:26.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:26.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:26.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:21:26.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:21:26.25$vck44/va=4,7 2006.257.09:21:26.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.09:21:26.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.09:21:26.25#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:26.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:26.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:26.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:26.31#ibcon#enter wrdev, iclass 14, count 2 2006.257.09:21:26.31#ibcon#first serial, iclass 14, count 2 2006.257.09:21:26.31#ibcon#enter sib2, iclass 14, count 2 2006.257.09:21:26.31#ibcon#flushed, iclass 14, count 2 2006.257.09:21:26.31#ibcon#about to write, iclass 14, count 2 2006.257.09:21:26.31#ibcon#wrote, iclass 14, count 2 2006.257.09:21:26.31#ibcon#about to read 3, iclass 14, count 2 2006.257.09:21:26.33#ibcon#read 3, iclass 14, count 2 2006.257.09:21:26.33#ibcon#about to read 4, iclass 14, count 2 2006.257.09:21:26.33#ibcon#read 4, iclass 14, count 2 2006.257.09:21:26.33#ibcon#about to read 5, iclass 14, count 2 2006.257.09:21:26.33#ibcon#read 5, iclass 14, count 2 2006.257.09:21:26.33#ibcon#about to read 6, iclass 14, count 2 2006.257.09:21:26.33#ibcon#read 6, iclass 14, count 2 2006.257.09:21:26.33#ibcon#end of sib2, iclass 14, count 2 2006.257.09:21:26.33#ibcon#*mode == 0, iclass 14, count 2 2006.257.09:21:26.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.09:21:26.33#ibcon#[25=AT04-07\r\n] 2006.257.09:21:26.33#ibcon#*before write, iclass 14, count 2 2006.257.09:21:26.33#ibcon#enter sib2, iclass 14, count 2 2006.257.09:21:26.33#ibcon#flushed, iclass 14, count 2 2006.257.09:21:26.33#ibcon#about to write, iclass 14, count 2 2006.257.09:21:26.33#ibcon#wrote, iclass 14, count 2 2006.257.09:21:26.33#ibcon#about to read 3, iclass 14, count 2 2006.257.09:21:26.36#ibcon#read 3, iclass 14, count 2 2006.257.09:21:26.36#ibcon#about to read 4, iclass 14, count 2 2006.257.09:21:26.36#ibcon#read 4, iclass 14, count 2 2006.257.09:21:26.36#ibcon#about to read 5, iclass 14, count 2 2006.257.09:21:26.36#ibcon#read 5, iclass 14, count 2 2006.257.09:21:26.36#ibcon#about to read 6, iclass 14, count 2 2006.257.09:21:26.36#ibcon#read 6, iclass 14, count 2 2006.257.09:21:26.36#ibcon#end of sib2, iclass 14, count 2 2006.257.09:21:26.36#ibcon#*after write, iclass 14, count 2 2006.257.09:21:26.36#ibcon#*before return 0, iclass 14, count 2 2006.257.09:21:26.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:26.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:26.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.09:21:26.36#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:26.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:26.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:26.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:26.48#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:21:26.48#ibcon#first serial, iclass 14, count 0 2006.257.09:21:26.48#ibcon#enter sib2, iclass 14, count 0 2006.257.09:21:26.48#ibcon#flushed, iclass 14, count 0 2006.257.09:21:26.48#ibcon#about to write, iclass 14, count 0 2006.257.09:21:26.48#ibcon#wrote, iclass 14, count 0 2006.257.09:21:26.48#ibcon#about to read 3, iclass 14, count 0 2006.257.09:21:26.50#ibcon#read 3, iclass 14, count 0 2006.257.09:21:26.50#ibcon#about to read 4, iclass 14, count 0 2006.257.09:21:26.50#ibcon#read 4, iclass 14, count 0 2006.257.09:21:26.50#ibcon#about to read 5, iclass 14, count 0 2006.257.09:21:26.50#ibcon#read 5, iclass 14, count 0 2006.257.09:21:26.50#ibcon#about to read 6, iclass 14, count 0 2006.257.09:21:26.50#ibcon#read 6, iclass 14, count 0 2006.257.09:21:26.50#ibcon#end of sib2, iclass 14, count 0 2006.257.09:21:26.50#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:21:26.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:21:26.50#ibcon#[25=USB\r\n] 2006.257.09:21:26.50#ibcon#*before write, iclass 14, count 0 2006.257.09:21:26.50#ibcon#enter sib2, iclass 14, count 0 2006.257.09:21:26.50#ibcon#flushed, iclass 14, count 0 2006.257.09:21:26.50#ibcon#about to write, iclass 14, count 0 2006.257.09:21:26.50#ibcon#wrote, iclass 14, count 0 2006.257.09:21:26.50#ibcon#about to read 3, iclass 14, count 0 2006.257.09:21:26.53#ibcon#read 3, iclass 14, count 0 2006.257.09:21:26.53#ibcon#about to read 4, iclass 14, count 0 2006.257.09:21:26.53#ibcon#read 4, iclass 14, count 0 2006.257.09:21:26.53#ibcon#about to read 5, iclass 14, count 0 2006.257.09:21:26.53#ibcon#read 5, iclass 14, count 0 2006.257.09:21:26.53#ibcon#about to read 6, iclass 14, count 0 2006.257.09:21:26.53#ibcon#read 6, iclass 14, count 0 2006.257.09:21:26.53#ibcon#end of sib2, iclass 14, count 0 2006.257.09:21:26.53#ibcon#*after write, iclass 14, count 0 2006.257.09:21:26.53#ibcon#*before return 0, iclass 14, count 0 2006.257.09:21:26.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:26.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:26.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:21:26.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:21:26.53$vck44/valo=5,734.99 2006.257.09:21:26.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.09:21:26.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.09:21:26.53#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:26.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:26.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:26.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:26.53#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:21:26.53#ibcon#first serial, iclass 16, count 0 2006.257.09:21:26.53#ibcon#enter sib2, iclass 16, count 0 2006.257.09:21:26.53#ibcon#flushed, iclass 16, count 0 2006.257.09:21:26.53#ibcon#about to write, iclass 16, count 0 2006.257.09:21:26.53#ibcon#wrote, iclass 16, count 0 2006.257.09:21:26.53#ibcon#about to read 3, iclass 16, count 0 2006.257.09:21:26.55#ibcon#read 3, iclass 16, count 0 2006.257.09:21:26.55#ibcon#about to read 4, iclass 16, count 0 2006.257.09:21:26.55#ibcon#read 4, iclass 16, count 0 2006.257.09:21:26.55#ibcon#about to read 5, iclass 16, count 0 2006.257.09:21:26.55#ibcon#read 5, iclass 16, count 0 2006.257.09:21:26.55#ibcon#about to read 6, iclass 16, count 0 2006.257.09:21:26.55#ibcon#read 6, iclass 16, count 0 2006.257.09:21:26.55#ibcon#end of sib2, iclass 16, count 0 2006.257.09:21:26.55#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:21:26.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:21:26.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:21:26.55#ibcon#*before write, iclass 16, count 0 2006.257.09:21:26.55#ibcon#enter sib2, iclass 16, count 0 2006.257.09:21:26.55#ibcon#flushed, iclass 16, count 0 2006.257.09:21:26.55#ibcon#about to write, iclass 16, count 0 2006.257.09:21:26.55#ibcon#wrote, iclass 16, count 0 2006.257.09:21:26.55#ibcon#about to read 3, iclass 16, count 0 2006.257.09:21:26.59#ibcon#read 3, iclass 16, count 0 2006.257.09:21:26.59#ibcon#about to read 4, iclass 16, count 0 2006.257.09:21:26.59#ibcon#read 4, iclass 16, count 0 2006.257.09:21:26.59#ibcon#about to read 5, iclass 16, count 0 2006.257.09:21:26.59#ibcon#read 5, iclass 16, count 0 2006.257.09:21:26.59#ibcon#about to read 6, iclass 16, count 0 2006.257.09:21:26.59#ibcon#read 6, iclass 16, count 0 2006.257.09:21:26.59#ibcon#end of sib2, iclass 16, count 0 2006.257.09:21:26.59#ibcon#*after write, iclass 16, count 0 2006.257.09:21:26.59#ibcon#*before return 0, iclass 16, count 0 2006.257.09:21:26.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:26.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:26.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:21:26.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:21:26.59$vck44/va=5,4 2006.257.09:21:26.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.09:21:26.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.09:21:26.59#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:26.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:26.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:26.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:26.65#ibcon#enter wrdev, iclass 18, count 2 2006.257.09:21:26.65#ibcon#first serial, iclass 18, count 2 2006.257.09:21:26.65#ibcon#enter sib2, iclass 18, count 2 2006.257.09:21:26.65#ibcon#flushed, iclass 18, count 2 2006.257.09:21:26.65#ibcon#about to write, iclass 18, count 2 2006.257.09:21:26.65#ibcon#wrote, iclass 18, count 2 2006.257.09:21:26.65#ibcon#about to read 3, iclass 18, count 2 2006.257.09:21:26.67#ibcon#read 3, iclass 18, count 2 2006.257.09:21:26.67#ibcon#about to read 4, iclass 18, count 2 2006.257.09:21:26.67#ibcon#read 4, iclass 18, count 2 2006.257.09:21:26.67#ibcon#about to read 5, iclass 18, count 2 2006.257.09:21:26.67#ibcon#read 5, iclass 18, count 2 2006.257.09:21:26.67#ibcon#about to read 6, iclass 18, count 2 2006.257.09:21:26.67#ibcon#read 6, iclass 18, count 2 2006.257.09:21:26.67#ibcon#end of sib2, iclass 18, count 2 2006.257.09:21:26.67#ibcon#*mode == 0, iclass 18, count 2 2006.257.09:21:26.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.09:21:26.67#ibcon#[25=AT05-04\r\n] 2006.257.09:21:26.67#ibcon#*before write, iclass 18, count 2 2006.257.09:21:26.67#ibcon#enter sib2, iclass 18, count 2 2006.257.09:21:26.67#ibcon#flushed, iclass 18, count 2 2006.257.09:21:26.67#ibcon#about to write, iclass 18, count 2 2006.257.09:21:26.67#ibcon#wrote, iclass 18, count 2 2006.257.09:21:26.67#ibcon#about to read 3, iclass 18, count 2 2006.257.09:21:26.70#ibcon#read 3, iclass 18, count 2 2006.257.09:21:26.70#ibcon#about to read 4, iclass 18, count 2 2006.257.09:21:26.70#ibcon#read 4, iclass 18, count 2 2006.257.09:21:26.70#ibcon#about to read 5, iclass 18, count 2 2006.257.09:21:26.70#ibcon#read 5, iclass 18, count 2 2006.257.09:21:26.70#ibcon#about to read 6, iclass 18, count 2 2006.257.09:21:26.70#ibcon#read 6, iclass 18, count 2 2006.257.09:21:26.70#ibcon#end of sib2, iclass 18, count 2 2006.257.09:21:26.70#ibcon#*after write, iclass 18, count 2 2006.257.09:21:26.70#ibcon#*before return 0, iclass 18, count 2 2006.257.09:21:26.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:26.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:26.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.09:21:26.70#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:26.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:26.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:26.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:26.82#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:21:26.82#ibcon#first serial, iclass 18, count 0 2006.257.09:21:26.82#ibcon#enter sib2, iclass 18, count 0 2006.257.09:21:26.82#ibcon#flushed, iclass 18, count 0 2006.257.09:21:26.82#ibcon#about to write, iclass 18, count 0 2006.257.09:21:26.82#ibcon#wrote, iclass 18, count 0 2006.257.09:21:26.82#ibcon#about to read 3, iclass 18, count 0 2006.257.09:21:26.84#ibcon#read 3, iclass 18, count 0 2006.257.09:21:26.84#ibcon#about to read 4, iclass 18, count 0 2006.257.09:21:26.84#ibcon#read 4, iclass 18, count 0 2006.257.09:21:26.84#ibcon#about to read 5, iclass 18, count 0 2006.257.09:21:26.84#ibcon#read 5, iclass 18, count 0 2006.257.09:21:26.84#ibcon#about to read 6, iclass 18, count 0 2006.257.09:21:26.84#ibcon#read 6, iclass 18, count 0 2006.257.09:21:26.84#ibcon#end of sib2, iclass 18, count 0 2006.257.09:21:26.84#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:21:26.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:21:26.84#ibcon#[25=USB\r\n] 2006.257.09:21:26.84#ibcon#*before write, iclass 18, count 0 2006.257.09:21:26.84#ibcon#enter sib2, iclass 18, count 0 2006.257.09:21:26.84#ibcon#flushed, iclass 18, count 0 2006.257.09:21:26.84#ibcon#about to write, iclass 18, count 0 2006.257.09:21:26.84#ibcon#wrote, iclass 18, count 0 2006.257.09:21:26.84#ibcon#about to read 3, iclass 18, count 0 2006.257.09:21:26.87#ibcon#read 3, iclass 18, count 0 2006.257.09:21:26.87#ibcon#about to read 4, iclass 18, count 0 2006.257.09:21:26.87#ibcon#read 4, iclass 18, count 0 2006.257.09:21:26.87#ibcon#about to read 5, iclass 18, count 0 2006.257.09:21:26.87#ibcon#read 5, iclass 18, count 0 2006.257.09:21:26.87#ibcon#about to read 6, iclass 18, count 0 2006.257.09:21:26.87#ibcon#read 6, iclass 18, count 0 2006.257.09:21:26.87#ibcon#end of sib2, iclass 18, count 0 2006.257.09:21:26.87#ibcon#*after write, iclass 18, count 0 2006.257.09:21:26.87#ibcon#*before return 0, iclass 18, count 0 2006.257.09:21:26.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:26.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:26.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:21:26.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:21:26.87$vck44/valo=6,814.99 2006.257.09:21:26.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.09:21:26.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.09:21:26.87#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:26.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:26.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:26.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:26.87#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:21:26.87#ibcon#first serial, iclass 20, count 0 2006.257.09:21:26.87#ibcon#enter sib2, iclass 20, count 0 2006.257.09:21:26.87#ibcon#flushed, iclass 20, count 0 2006.257.09:21:26.87#ibcon#about to write, iclass 20, count 0 2006.257.09:21:26.87#ibcon#wrote, iclass 20, count 0 2006.257.09:21:26.87#ibcon#about to read 3, iclass 20, count 0 2006.257.09:21:26.89#ibcon#read 3, iclass 20, count 0 2006.257.09:21:26.89#ibcon#about to read 4, iclass 20, count 0 2006.257.09:21:26.89#ibcon#read 4, iclass 20, count 0 2006.257.09:21:26.89#ibcon#about to read 5, iclass 20, count 0 2006.257.09:21:26.89#ibcon#read 5, iclass 20, count 0 2006.257.09:21:26.89#ibcon#about to read 6, iclass 20, count 0 2006.257.09:21:26.89#ibcon#read 6, iclass 20, count 0 2006.257.09:21:26.89#ibcon#end of sib2, iclass 20, count 0 2006.257.09:21:26.89#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:21:26.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:21:26.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:21:26.89#ibcon#*before write, iclass 20, count 0 2006.257.09:21:26.89#ibcon#enter sib2, iclass 20, count 0 2006.257.09:21:26.89#ibcon#flushed, iclass 20, count 0 2006.257.09:21:26.89#ibcon#about to write, iclass 20, count 0 2006.257.09:21:26.89#ibcon#wrote, iclass 20, count 0 2006.257.09:21:26.89#ibcon#about to read 3, iclass 20, count 0 2006.257.09:21:26.93#ibcon#read 3, iclass 20, count 0 2006.257.09:21:26.93#ibcon#about to read 4, iclass 20, count 0 2006.257.09:21:26.93#ibcon#read 4, iclass 20, count 0 2006.257.09:21:26.93#ibcon#about to read 5, iclass 20, count 0 2006.257.09:21:26.93#ibcon#read 5, iclass 20, count 0 2006.257.09:21:26.93#ibcon#about to read 6, iclass 20, count 0 2006.257.09:21:26.93#ibcon#read 6, iclass 20, count 0 2006.257.09:21:26.93#ibcon#end of sib2, iclass 20, count 0 2006.257.09:21:26.93#ibcon#*after write, iclass 20, count 0 2006.257.09:21:26.93#ibcon#*before return 0, iclass 20, count 0 2006.257.09:21:26.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:26.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:26.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:21:26.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:21:26.93$vck44/va=6,4 2006.257.09:21:26.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.09:21:26.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.09:21:26.93#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:26.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:26.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:26.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:26.99#ibcon#enter wrdev, iclass 22, count 2 2006.257.09:21:26.99#ibcon#first serial, iclass 22, count 2 2006.257.09:21:26.99#ibcon#enter sib2, iclass 22, count 2 2006.257.09:21:26.99#ibcon#flushed, iclass 22, count 2 2006.257.09:21:26.99#ibcon#about to write, iclass 22, count 2 2006.257.09:21:26.99#ibcon#wrote, iclass 22, count 2 2006.257.09:21:26.99#ibcon#about to read 3, iclass 22, count 2 2006.257.09:21:27.01#ibcon#read 3, iclass 22, count 2 2006.257.09:21:27.01#ibcon#about to read 4, iclass 22, count 2 2006.257.09:21:27.01#ibcon#read 4, iclass 22, count 2 2006.257.09:21:27.01#ibcon#about to read 5, iclass 22, count 2 2006.257.09:21:27.01#ibcon#read 5, iclass 22, count 2 2006.257.09:21:27.01#ibcon#about to read 6, iclass 22, count 2 2006.257.09:21:27.01#ibcon#read 6, iclass 22, count 2 2006.257.09:21:27.01#ibcon#end of sib2, iclass 22, count 2 2006.257.09:21:27.01#ibcon#*mode == 0, iclass 22, count 2 2006.257.09:21:27.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.09:21:27.01#ibcon#[25=AT06-04\r\n] 2006.257.09:21:27.01#ibcon#*before write, iclass 22, count 2 2006.257.09:21:27.01#ibcon#enter sib2, iclass 22, count 2 2006.257.09:21:27.01#ibcon#flushed, iclass 22, count 2 2006.257.09:21:27.01#ibcon#about to write, iclass 22, count 2 2006.257.09:21:27.01#ibcon#wrote, iclass 22, count 2 2006.257.09:21:27.01#ibcon#about to read 3, iclass 22, count 2 2006.257.09:21:27.04#ibcon#read 3, iclass 22, count 2 2006.257.09:21:27.04#ibcon#about to read 4, iclass 22, count 2 2006.257.09:21:27.04#ibcon#read 4, iclass 22, count 2 2006.257.09:21:27.04#ibcon#about to read 5, iclass 22, count 2 2006.257.09:21:27.04#ibcon#read 5, iclass 22, count 2 2006.257.09:21:27.04#ibcon#about to read 6, iclass 22, count 2 2006.257.09:21:27.04#ibcon#read 6, iclass 22, count 2 2006.257.09:21:27.04#ibcon#end of sib2, iclass 22, count 2 2006.257.09:21:27.04#ibcon#*after write, iclass 22, count 2 2006.257.09:21:27.04#ibcon#*before return 0, iclass 22, count 2 2006.257.09:21:27.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:27.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:27.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.09:21:27.04#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:27.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:27.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:27.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:27.16#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:21:27.16#ibcon#first serial, iclass 22, count 0 2006.257.09:21:27.16#ibcon#enter sib2, iclass 22, count 0 2006.257.09:21:27.16#ibcon#flushed, iclass 22, count 0 2006.257.09:21:27.16#ibcon#about to write, iclass 22, count 0 2006.257.09:21:27.16#ibcon#wrote, iclass 22, count 0 2006.257.09:21:27.16#ibcon#about to read 3, iclass 22, count 0 2006.257.09:21:27.18#ibcon#read 3, iclass 22, count 0 2006.257.09:21:27.18#ibcon#about to read 4, iclass 22, count 0 2006.257.09:21:27.18#ibcon#read 4, iclass 22, count 0 2006.257.09:21:27.18#ibcon#about to read 5, iclass 22, count 0 2006.257.09:21:27.18#ibcon#read 5, iclass 22, count 0 2006.257.09:21:27.18#ibcon#about to read 6, iclass 22, count 0 2006.257.09:21:27.18#ibcon#read 6, iclass 22, count 0 2006.257.09:21:27.18#ibcon#end of sib2, iclass 22, count 0 2006.257.09:21:27.18#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:21:27.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:21:27.18#ibcon#[25=USB\r\n] 2006.257.09:21:27.18#ibcon#*before write, iclass 22, count 0 2006.257.09:21:27.18#ibcon#enter sib2, iclass 22, count 0 2006.257.09:21:27.18#ibcon#flushed, iclass 22, count 0 2006.257.09:21:27.18#ibcon#about to write, iclass 22, count 0 2006.257.09:21:27.18#ibcon#wrote, iclass 22, count 0 2006.257.09:21:27.18#ibcon#about to read 3, iclass 22, count 0 2006.257.09:21:27.21#ibcon#read 3, iclass 22, count 0 2006.257.09:21:27.21#ibcon#about to read 4, iclass 22, count 0 2006.257.09:21:27.21#ibcon#read 4, iclass 22, count 0 2006.257.09:21:27.21#ibcon#about to read 5, iclass 22, count 0 2006.257.09:21:27.21#ibcon#read 5, iclass 22, count 0 2006.257.09:21:27.21#ibcon#about to read 6, iclass 22, count 0 2006.257.09:21:27.21#ibcon#read 6, iclass 22, count 0 2006.257.09:21:27.21#ibcon#end of sib2, iclass 22, count 0 2006.257.09:21:27.21#ibcon#*after write, iclass 22, count 0 2006.257.09:21:27.21#ibcon#*before return 0, iclass 22, count 0 2006.257.09:21:27.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:27.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:27.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:21:27.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:21:27.21$vck44/valo=7,864.99 2006.257.09:21:27.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.09:21:27.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.09:21:27.21#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:27.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:27.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:27.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:27.21#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:21:27.21#ibcon#first serial, iclass 24, count 0 2006.257.09:21:27.21#ibcon#enter sib2, iclass 24, count 0 2006.257.09:21:27.21#ibcon#flushed, iclass 24, count 0 2006.257.09:21:27.21#ibcon#about to write, iclass 24, count 0 2006.257.09:21:27.21#ibcon#wrote, iclass 24, count 0 2006.257.09:21:27.21#ibcon#about to read 3, iclass 24, count 0 2006.257.09:21:27.23#ibcon#read 3, iclass 24, count 0 2006.257.09:21:27.23#ibcon#about to read 4, iclass 24, count 0 2006.257.09:21:27.23#ibcon#read 4, iclass 24, count 0 2006.257.09:21:27.23#ibcon#about to read 5, iclass 24, count 0 2006.257.09:21:27.23#ibcon#read 5, iclass 24, count 0 2006.257.09:21:27.23#ibcon#about to read 6, iclass 24, count 0 2006.257.09:21:27.23#ibcon#read 6, iclass 24, count 0 2006.257.09:21:27.23#ibcon#end of sib2, iclass 24, count 0 2006.257.09:21:27.23#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:21:27.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:21:27.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:21:27.23#ibcon#*before write, iclass 24, count 0 2006.257.09:21:27.23#ibcon#enter sib2, iclass 24, count 0 2006.257.09:21:27.23#ibcon#flushed, iclass 24, count 0 2006.257.09:21:27.23#ibcon#about to write, iclass 24, count 0 2006.257.09:21:27.23#ibcon#wrote, iclass 24, count 0 2006.257.09:21:27.23#ibcon#about to read 3, iclass 24, count 0 2006.257.09:21:27.27#ibcon#read 3, iclass 24, count 0 2006.257.09:21:27.27#ibcon#about to read 4, iclass 24, count 0 2006.257.09:21:27.27#ibcon#read 4, iclass 24, count 0 2006.257.09:21:27.27#ibcon#about to read 5, iclass 24, count 0 2006.257.09:21:27.27#ibcon#read 5, iclass 24, count 0 2006.257.09:21:27.27#ibcon#about to read 6, iclass 24, count 0 2006.257.09:21:27.27#ibcon#read 6, iclass 24, count 0 2006.257.09:21:27.27#ibcon#end of sib2, iclass 24, count 0 2006.257.09:21:27.27#ibcon#*after write, iclass 24, count 0 2006.257.09:21:27.27#ibcon#*before return 0, iclass 24, count 0 2006.257.09:21:27.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:27.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:27.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:21:27.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:21:27.27$vck44/va=7,4 2006.257.09:21:27.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.09:21:27.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.09:21:27.27#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:27.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:27.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:27.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:27.33#ibcon#enter wrdev, iclass 26, count 2 2006.257.09:21:27.33#ibcon#first serial, iclass 26, count 2 2006.257.09:21:27.33#ibcon#enter sib2, iclass 26, count 2 2006.257.09:21:27.33#ibcon#flushed, iclass 26, count 2 2006.257.09:21:27.33#ibcon#about to write, iclass 26, count 2 2006.257.09:21:27.33#ibcon#wrote, iclass 26, count 2 2006.257.09:21:27.33#ibcon#about to read 3, iclass 26, count 2 2006.257.09:21:27.35#ibcon#read 3, iclass 26, count 2 2006.257.09:21:27.35#ibcon#about to read 4, iclass 26, count 2 2006.257.09:21:27.35#ibcon#read 4, iclass 26, count 2 2006.257.09:21:27.35#ibcon#about to read 5, iclass 26, count 2 2006.257.09:21:27.35#ibcon#read 5, iclass 26, count 2 2006.257.09:21:27.35#ibcon#about to read 6, iclass 26, count 2 2006.257.09:21:27.35#ibcon#read 6, iclass 26, count 2 2006.257.09:21:27.35#ibcon#end of sib2, iclass 26, count 2 2006.257.09:21:27.35#ibcon#*mode == 0, iclass 26, count 2 2006.257.09:21:27.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.09:21:27.35#ibcon#[25=AT07-04\r\n] 2006.257.09:21:27.35#ibcon#*before write, iclass 26, count 2 2006.257.09:21:27.35#ibcon#enter sib2, iclass 26, count 2 2006.257.09:21:27.35#ibcon#flushed, iclass 26, count 2 2006.257.09:21:27.35#ibcon#about to write, iclass 26, count 2 2006.257.09:21:27.35#ibcon#wrote, iclass 26, count 2 2006.257.09:21:27.35#ibcon#about to read 3, iclass 26, count 2 2006.257.09:21:27.38#ibcon#read 3, iclass 26, count 2 2006.257.09:21:27.38#ibcon#about to read 4, iclass 26, count 2 2006.257.09:21:27.38#ibcon#read 4, iclass 26, count 2 2006.257.09:21:27.38#ibcon#about to read 5, iclass 26, count 2 2006.257.09:21:27.38#ibcon#read 5, iclass 26, count 2 2006.257.09:21:27.38#ibcon#about to read 6, iclass 26, count 2 2006.257.09:21:27.38#ibcon#read 6, iclass 26, count 2 2006.257.09:21:27.38#ibcon#end of sib2, iclass 26, count 2 2006.257.09:21:27.38#ibcon#*after write, iclass 26, count 2 2006.257.09:21:27.38#ibcon#*before return 0, iclass 26, count 2 2006.257.09:21:27.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:27.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:27.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.09:21:27.38#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:27.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:27.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:27.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:27.50#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:21:27.50#ibcon#first serial, iclass 26, count 0 2006.257.09:21:27.50#ibcon#enter sib2, iclass 26, count 0 2006.257.09:21:27.50#ibcon#flushed, iclass 26, count 0 2006.257.09:21:27.50#ibcon#about to write, iclass 26, count 0 2006.257.09:21:27.50#ibcon#wrote, iclass 26, count 0 2006.257.09:21:27.50#ibcon#about to read 3, iclass 26, count 0 2006.257.09:21:27.52#ibcon#read 3, iclass 26, count 0 2006.257.09:21:27.52#ibcon#about to read 4, iclass 26, count 0 2006.257.09:21:27.52#ibcon#read 4, iclass 26, count 0 2006.257.09:21:27.52#ibcon#about to read 5, iclass 26, count 0 2006.257.09:21:27.52#ibcon#read 5, iclass 26, count 0 2006.257.09:21:27.52#ibcon#about to read 6, iclass 26, count 0 2006.257.09:21:27.52#ibcon#read 6, iclass 26, count 0 2006.257.09:21:27.52#ibcon#end of sib2, iclass 26, count 0 2006.257.09:21:27.52#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:21:27.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:21:27.52#ibcon#[25=USB\r\n] 2006.257.09:21:27.52#ibcon#*before write, iclass 26, count 0 2006.257.09:21:27.52#ibcon#enter sib2, iclass 26, count 0 2006.257.09:21:27.52#ibcon#flushed, iclass 26, count 0 2006.257.09:21:27.52#ibcon#about to write, iclass 26, count 0 2006.257.09:21:27.52#ibcon#wrote, iclass 26, count 0 2006.257.09:21:27.52#ibcon#about to read 3, iclass 26, count 0 2006.257.09:21:27.55#ibcon#read 3, iclass 26, count 0 2006.257.09:21:27.55#ibcon#about to read 4, iclass 26, count 0 2006.257.09:21:27.55#ibcon#read 4, iclass 26, count 0 2006.257.09:21:27.55#ibcon#about to read 5, iclass 26, count 0 2006.257.09:21:27.55#ibcon#read 5, iclass 26, count 0 2006.257.09:21:27.55#ibcon#about to read 6, iclass 26, count 0 2006.257.09:21:27.55#ibcon#read 6, iclass 26, count 0 2006.257.09:21:27.55#ibcon#end of sib2, iclass 26, count 0 2006.257.09:21:27.55#ibcon#*after write, iclass 26, count 0 2006.257.09:21:27.55#ibcon#*before return 0, iclass 26, count 0 2006.257.09:21:27.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:27.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:27.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:21:27.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:21:27.55$vck44/valo=8,884.99 2006.257.09:21:27.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.09:21:27.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.09:21:27.55#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:27.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:27.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:27.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:27.55#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:21:27.55#ibcon#first serial, iclass 28, count 0 2006.257.09:21:27.55#ibcon#enter sib2, iclass 28, count 0 2006.257.09:21:27.55#ibcon#flushed, iclass 28, count 0 2006.257.09:21:27.55#ibcon#about to write, iclass 28, count 0 2006.257.09:21:27.55#ibcon#wrote, iclass 28, count 0 2006.257.09:21:27.55#ibcon#about to read 3, iclass 28, count 0 2006.257.09:21:27.57#ibcon#read 3, iclass 28, count 0 2006.257.09:21:27.57#ibcon#about to read 4, iclass 28, count 0 2006.257.09:21:27.57#ibcon#read 4, iclass 28, count 0 2006.257.09:21:27.57#ibcon#about to read 5, iclass 28, count 0 2006.257.09:21:27.57#ibcon#read 5, iclass 28, count 0 2006.257.09:21:27.57#ibcon#about to read 6, iclass 28, count 0 2006.257.09:21:27.57#ibcon#read 6, iclass 28, count 0 2006.257.09:21:27.57#ibcon#end of sib2, iclass 28, count 0 2006.257.09:21:27.57#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:21:27.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:21:27.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:21:27.57#ibcon#*before write, iclass 28, count 0 2006.257.09:21:27.57#ibcon#enter sib2, iclass 28, count 0 2006.257.09:21:27.57#ibcon#flushed, iclass 28, count 0 2006.257.09:21:27.57#ibcon#about to write, iclass 28, count 0 2006.257.09:21:27.57#ibcon#wrote, iclass 28, count 0 2006.257.09:21:27.57#ibcon#about to read 3, iclass 28, count 0 2006.257.09:21:27.61#ibcon#read 3, iclass 28, count 0 2006.257.09:21:27.61#ibcon#about to read 4, iclass 28, count 0 2006.257.09:21:27.61#ibcon#read 4, iclass 28, count 0 2006.257.09:21:27.61#ibcon#about to read 5, iclass 28, count 0 2006.257.09:21:27.61#ibcon#read 5, iclass 28, count 0 2006.257.09:21:27.61#ibcon#about to read 6, iclass 28, count 0 2006.257.09:21:27.61#ibcon#read 6, iclass 28, count 0 2006.257.09:21:27.61#ibcon#end of sib2, iclass 28, count 0 2006.257.09:21:27.61#ibcon#*after write, iclass 28, count 0 2006.257.09:21:27.61#ibcon#*before return 0, iclass 28, count 0 2006.257.09:21:27.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:27.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:27.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:21:27.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:21:27.61$vck44/va=8,4 2006.257.09:21:27.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.09:21:27.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.09:21:27.61#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:27.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:21:27.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:21:27.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:21:27.67#ibcon#enter wrdev, iclass 30, count 2 2006.257.09:21:27.67#ibcon#first serial, iclass 30, count 2 2006.257.09:21:27.67#ibcon#enter sib2, iclass 30, count 2 2006.257.09:21:27.67#ibcon#flushed, iclass 30, count 2 2006.257.09:21:27.67#ibcon#about to write, iclass 30, count 2 2006.257.09:21:27.67#ibcon#wrote, iclass 30, count 2 2006.257.09:21:27.67#ibcon#about to read 3, iclass 30, count 2 2006.257.09:21:27.69#ibcon#read 3, iclass 30, count 2 2006.257.09:21:27.69#ibcon#about to read 4, iclass 30, count 2 2006.257.09:21:27.69#ibcon#read 4, iclass 30, count 2 2006.257.09:21:27.69#ibcon#about to read 5, iclass 30, count 2 2006.257.09:21:27.69#ibcon#read 5, iclass 30, count 2 2006.257.09:21:27.69#ibcon#about to read 6, iclass 30, count 2 2006.257.09:21:27.69#ibcon#read 6, iclass 30, count 2 2006.257.09:21:27.69#ibcon#end of sib2, iclass 30, count 2 2006.257.09:21:27.69#ibcon#*mode == 0, iclass 30, count 2 2006.257.09:21:27.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.09:21:27.69#ibcon#[25=AT08-04\r\n] 2006.257.09:21:27.69#ibcon#*before write, iclass 30, count 2 2006.257.09:21:27.69#ibcon#enter sib2, iclass 30, count 2 2006.257.09:21:27.69#ibcon#flushed, iclass 30, count 2 2006.257.09:21:27.69#ibcon#about to write, iclass 30, count 2 2006.257.09:21:27.69#ibcon#wrote, iclass 30, count 2 2006.257.09:21:27.69#ibcon#about to read 3, iclass 30, count 2 2006.257.09:21:27.72#ibcon#read 3, iclass 30, count 2 2006.257.09:21:27.72#ibcon#about to read 4, iclass 30, count 2 2006.257.09:21:27.72#ibcon#read 4, iclass 30, count 2 2006.257.09:21:27.72#ibcon#about to read 5, iclass 30, count 2 2006.257.09:21:27.72#ibcon#read 5, iclass 30, count 2 2006.257.09:21:27.72#ibcon#about to read 6, iclass 30, count 2 2006.257.09:21:27.72#ibcon#read 6, iclass 30, count 2 2006.257.09:21:27.72#ibcon#end of sib2, iclass 30, count 2 2006.257.09:21:27.72#ibcon#*after write, iclass 30, count 2 2006.257.09:21:27.72#ibcon#*before return 0, iclass 30, count 2 2006.257.09:21:27.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:21:27.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:21:27.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.09:21:27.72#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:27.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:21:27.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:21:27.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:21:27.84#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:21:27.84#ibcon#first serial, iclass 30, count 0 2006.257.09:21:27.84#ibcon#enter sib2, iclass 30, count 0 2006.257.09:21:27.84#ibcon#flushed, iclass 30, count 0 2006.257.09:21:27.84#ibcon#about to write, iclass 30, count 0 2006.257.09:21:27.84#ibcon#wrote, iclass 30, count 0 2006.257.09:21:27.84#ibcon#about to read 3, iclass 30, count 0 2006.257.09:21:27.86#ibcon#read 3, iclass 30, count 0 2006.257.09:21:27.86#ibcon#about to read 4, iclass 30, count 0 2006.257.09:21:27.86#ibcon#read 4, iclass 30, count 0 2006.257.09:21:27.86#ibcon#about to read 5, iclass 30, count 0 2006.257.09:21:27.86#ibcon#read 5, iclass 30, count 0 2006.257.09:21:27.86#ibcon#about to read 6, iclass 30, count 0 2006.257.09:21:27.86#ibcon#read 6, iclass 30, count 0 2006.257.09:21:27.86#ibcon#end of sib2, iclass 30, count 0 2006.257.09:21:27.86#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:21:27.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:21:27.86#ibcon#[25=USB\r\n] 2006.257.09:21:27.86#ibcon#*before write, iclass 30, count 0 2006.257.09:21:27.86#ibcon#enter sib2, iclass 30, count 0 2006.257.09:21:27.86#ibcon#flushed, iclass 30, count 0 2006.257.09:21:27.86#ibcon#about to write, iclass 30, count 0 2006.257.09:21:27.86#ibcon#wrote, iclass 30, count 0 2006.257.09:21:27.86#ibcon#about to read 3, iclass 30, count 0 2006.257.09:21:27.89#ibcon#read 3, iclass 30, count 0 2006.257.09:21:27.89#ibcon#about to read 4, iclass 30, count 0 2006.257.09:21:27.89#ibcon#read 4, iclass 30, count 0 2006.257.09:21:27.89#ibcon#about to read 5, iclass 30, count 0 2006.257.09:21:27.89#ibcon#read 5, iclass 30, count 0 2006.257.09:21:27.89#ibcon#about to read 6, iclass 30, count 0 2006.257.09:21:27.89#ibcon#read 6, iclass 30, count 0 2006.257.09:21:27.89#ibcon#end of sib2, iclass 30, count 0 2006.257.09:21:27.89#ibcon#*after write, iclass 30, count 0 2006.257.09:21:27.89#ibcon#*before return 0, iclass 30, count 0 2006.257.09:21:27.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:21:27.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:21:27.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:21:27.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:21:27.89$vck44/vblo=1,629.99 2006.257.09:21:27.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.09:21:27.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.09:21:27.89#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:27.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:21:27.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:21:27.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:21:27.89#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:21:27.89#ibcon#first serial, iclass 32, count 0 2006.257.09:21:27.89#ibcon#enter sib2, iclass 32, count 0 2006.257.09:21:27.89#ibcon#flushed, iclass 32, count 0 2006.257.09:21:27.89#ibcon#about to write, iclass 32, count 0 2006.257.09:21:27.89#ibcon#wrote, iclass 32, count 0 2006.257.09:21:27.89#ibcon#about to read 3, iclass 32, count 0 2006.257.09:21:27.91#ibcon#read 3, iclass 32, count 0 2006.257.09:21:27.91#ibcon#about to read 4, iclass 32, count 0 2006.257.09:21:27.91#ibcon#read 4, iclass 32, count 0 2006.257.09:21:27.91#ibcon#about to read 5, iclass 32, count 0 2006.257.09:21:27.91#ibcon#read 5, iclass 32, count 0 2006.257.09:21:27.91#ibcon#about to read 6, iclass 32, count 0 2006.257.09:21:27.91#ibcon#read 6, iclass 32, count 0 2006.257.09:21:27.91#ibcon#end of sib2, iclass 32, count 0 2006.257.09:21:27.91#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:21:27.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:21:27.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:21:27.91#ibcon#*before write, iclass 32, count 0 2006.257.09:21:27.91#ibcon#enter sib2, iclass 32, count 0 2006.257.09:21:27.91#ibcon#flushed, iclass 32, count 0 2006.257.09:21:27.91#ibcon#about to write, iclass 32, count 0 2006.257.09:21:27.91#ibcon#wrote, iclass 32, count 0 2006.257.09:21:27.91#ibcon#about to read 3, iclass 32, count 0 2006.257.09:21:27.95#ibcon#read 3, iclass 32, count 0 2006.257.09:21:27.95#ibcon#about to read 4, iclass 32, count 0 2006.257.09:21:27.95#ibcon#read 4, iclass 32, count 0 2006.257.09:21:27.95#ibcon#about to read 5, iclass 32, count 0 2006.257.09:21:27.95#ibcon#read 5, iclass 32, count 0 2006.257.09:21:27.95#ibcon#about to read 6, iclass 32, count 0 2006.257.09:21:27.95#ibcon#read 6, iclass 32, count 0 2006.257.09:21:27.95#ibcon#end of sib2, iclass 32, count 0 2006.257.09:21:27.95#ibcon#*after write, iclass 32, count 0 2006.257.09:21:27.95#ibcon#*before return 0, iclass 32, count 0 2006.257.09:21:27.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:21:27.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:21:27.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:21:27.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:21:27.95$vck44/vb=1,4 2006.257.09:21:27.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.09:21:27.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.09:21:27.95#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:27.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:21:27.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:21:27.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:21:27.95#ibcon#enter wrdev, iclass 34, count 2 2006.257.09:21:27.95#ibcon#first serial, iclass 34, count 2 2006.257.09:21:27.95#ibcon#enter sib2, iclass 34, count 2 2006.257.09:21:27.95#ibcon#flushed, iclass 34, count 2 2006.257.09:21:27.95#ibcon#about to write, iclass 34, count 2 2006.257.09:21:27.95#ibcon#wrote, iclass 34, count 2 2006.257.09:21:27.95#ibcon#about to read 3, iclass 34, count 2 2006.257.09:21:27.97#ibcon#read 3, iclass 34, count 2 2006.257.09:21:27.97#ibcon#about to read 4, iclass 34, count 2 2006.257.09:21:27.97#ibcon#read 4, iclass 34, count 2 2006.257.09:21:27.97#ibcon#about to read 5, iclass 34, count 2 2006.257.09:21:27.97#ibcon#read 5, iclass 34, count 2 2006.257.09:21:27.97#ibcon#about to read 6, iclass 34, count 2 2006.257.09:21:27.97#ibcon#read 6, iclass 34, count 2 2006.257.09:21:27.97#ibcon#end of sib2, iclass 34, count 2 2006.257.09:21:27.97#ibcon#*mode == 0, iclass 34, count 2 2006.257.09:21:27.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.09:21:27.97#ibcon#[27=AT01-04\r\n] 2006.257.09:21:27.97#ibcon#*before write, iclass 34, count 2 2006.257.09:21:27.97#ibcon#enter sib2, iclass 34, count 2 2006.257.09:21:27.97#ibcon#flushed, iclass 34, count 2 2006.257.09:21:27.97#ibcon#about to write, iclass 34, count 2 2006.257.09:21:27.97#ibcon#wrote, iclass 34, count 2 2006.257.09:21:27.97#ibcon#about to read 3, iclass 34, count 2 2006.257.09:21:28.00#ibcon#read 3, iclass 34, count 2 2006.257.09:21:28.00#ibcon#about to read 4, iclass 34, count 2 2006.257.09:21:28.00#ibcon#read 4, iclass 34, count 2 2006.257.09:21:28.00#ibcon#about to read 5, iclass 34, count 2 2006.257.09:21:28.00#ibcon#read 5, iclass 34, count 2 2006.257.09:21:28.00#ibcon#about to read 6, iclass 34, count 2 2006.257.09:21:28.00#ibcon#read 6, iclass 34, count 2 2006.257.09:21:28.00#ibcon#end of sib2, iclass 34, count 2 2006.257.09:21:28.00#ibcon#*after write, iclass 34, count 2 2006.257.09:21:28.00#ibcon#*before return 0, iclass 34, count 2 2006.257.09:21:28.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:21:28.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:21:28.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.09:21:28.00#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:28.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:21:28.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:21:28.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:21:28.12#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:21:28.12#ibcon#first serial, iclass 34, count 0 2006.257.09:21:28.12#ibcon#enter sib2, iclass 34, count 0 2006.257.09:21:28.12#ibcon#flushed, iclass 34, count 0 2006.257.09:21:28.12#ibcon#about to write, iclass 34, count 0 2006.257.09:21:28.12#ibcon#wrote, iclass 34, count 0 2006.257.09:21:28.12#ibcon#about to read 3, iclass 34, count 0 2006.257.09:21:28.14#ibcon#read 3, iclass 34, count 0 2006.257.09:21:28.14#ibcon#about to read 4, iclass 34, count 0 2006.257.09:21:28.14#ibcon#read 4, iclass 34, count 0 2006.257.09:21:28.14#ibcon#about to read 5, iclass 34, count 0 2006.257.09:21:28.14#ibcon#read 5, iclass 34, count 0 2006.257.09:21:28.14#ibcon#about to read 6, iclass 34, count 0 2006.257.09:21:28.14#ibcon#read 6, iclass 34, count 0 2006.257.09:21:28.14#ibcon#end of sib2, iclass 34, count 0 2006.257.09:21:28.14#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:21:28.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:21:28.14#ibcon#[27=USB\r\n] 2006.257.09:21:28.14#ibcon#*before write, iclass 34, count 0 2006.257.09:21:28.14#ibcon#enter sib2, iclass 34, count 0 2006.257.09:21:28.14#ibcon#flushed, iclass 34, count 0 2006.257.09:21:28.14#ibcon#about to write, iclass 34, count 0 2006.257.09:21:28.14#ibcon#wrote, iclass 34, count 0 2006.257.09:21:28.14#ibcon#about to read 3, iclass 34, count 0 2006.257.09:21:28.17#ibcon#read 3, iclass 34, count 0 2006.257.09:21:28.17#ibcon#about to read 4, iclass 34, count 0 2006.257.09:21:28.17#ibcon#read 4, iclass 34, count 0 2006.257.09:21:28.17#ibcon#about to read 5, iclass 34, count 0 2006.257.09:21:28.17#ibcon#read 5, iclass 34, count 0 2006.257.09:21:28.17#ibcon#about to read 6, iclass 34, count 0 2006.257.09:21:28.17#ibcon#read 6, iclass 34, count 0 2006.257.09:21:28.17#ibcon#end of sib2, iclass 34, count 0 2006.257.09:21:28.17#ibcon#*after write, iclass 34, count 0 2006.257.09:21:28.17#ibcon#*before return 0, iclass 34, count 0 2006.257.09:21:28.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:21:28.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:21:28.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:21:28.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:21:28.17$vck44/vblo=2,634.99 2006.257.09:21:28.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.09:21:28.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.09:21:28.17#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:28.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:28.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:28.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:28.17#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:21:28.17#ibcon#first serial, iclass 36, count 0 2006.257.09:21:28.17#ibcon#enter sib2, iclass 36, count 0 2006.257.09:21:28.17#ibcon#flushed, iclass 36, count 0 2006.257.09:21:28.17#ibcon#about to write, iclass 36, count 0 2006.257.09:21:28.17#ibcon#wrote, iclass 36, count 0 2006.257.09:21:28.17#ibcon#about to read 3, iclass 36, count 0 2006.257.09:21:28.19#ibcon#read 3, iclass 36, count 0 2006.257.09:21:28.19#ibcon#about to read 4, iclass 36, count 0 2006.257.09:21:28.19#ibcon#read 4, iclass 36, count 0 2006.257.09:21:28.19#ibcon#about to read 5, iclass 36, count 0 2006.257.09:21:28.19#ibcon#read 5, iclass 36, count 0 2006.257.09:21:28.19#ibcon#about to read 6, iclass 36, count 0 2006.257.09:21:28.19#ibcon#read 6, iclass 36, count 0 2006.257.09:21:28.19#ibcon#end of sib2, iclass 36, count 0 2006.257.09:21:28.19#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:21:28.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:21:28.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:21:28.19#ibcon#*before write, iclass 36, count 0 2006.257.09:21:28.19#ibcon#enter sib2, iclass 36, count 0 2006.257.09:21:28.19#ibcon#flushed, iclass 36, count 0 2006.257.09:21:28.19#ibcon#about to write, iclass 36, count 0 2006.257.09:21:28.19#ibcon#wrote, iclass 36, count 0 2006.257.09:21:28.19#ibcon#about to read 3, iclass 36, count 0 2006.257.09:21:28.23#ibcon#read 3, iclass 36, count 0 2006.257.09:21:28.23#ibcon#about to read 4, iclass 36, count 0 2006.257.09:21:28.23#ibcon#read 4, iclass 36, count 0 2006.257.09:21:28.23#ibcon#about to read 5, iclass 36, count 0 2006.257.09:21:28.23#ibcon#read 5, iclass 36, count 0 2006.257.09:21:28.23#ibcon#about to read 6, iclass 36, count 0 2006.257.09:21:28.23#ibcon#read 6, iclass 36, count 0 2006.257.09:21:28.23#ibcon#end of sib2, iclass 36, count 0 2006.257.09:21:28.23#ibcon#*after write, iclass 36, count 0 2006.257.09:21:28.23#ibcon#*before return 0, iclass 36, count 0 2006.257.09:21:28.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:28.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:21:28.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:21:28.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:21:28.23$vck44/vb=2,5 2006.257.09:21:28.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.09:21:28.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.09:21:28.23#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:28.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:28.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:28.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:28.29#ibcon#enter wrdev, iclass 38, count 2 2006.257.09:21:28.29#ibcon#first serial, iclass 38, count 2 2006.257.09:21:28.29#ibcon#enter sib2, iclass 38, count 2 2006.257.09:21:28.29#ibcon#flushed, iclass 38, count 2 2006.257.09:21:28.29#ibcon#about to write, iclass 38, count 2 2006.257.09:21:28.29#ibcon#wrote, iclass 38, count 2 2006.257.09:21:28.29#ibcon#about to read 3, iclass 38, count 2 2006.257.09:21:28.31#ibcon#read 3, iclass 38, count 2 2006.257.09:21:28.31#ibcon#about to read 4, iclass 38, count 2 2006.257.09:21:28.31#ibcon#read 4, iclass 38, count 2 2006.257.09:21:28.31#ibcon#about to read 5, iclass 38, count 2 2006.257.09:21:28.31#ibcon#read 5, iclass 38, count 2 2006.257.09:21:28.31#ibcon#about to read 6, iclass 38, count 2 2006.257.09:21:28.31#ibcon#read 6, iclass 38, count 2 2006.257.09:21:28.31#ibcon#end of sib2, iclass 38, count 2 2006.257.09:21:28.31#ibcon#*mode == 0, iclass 38, count 2 2006.257.09:21:28.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.09:21:28.31#ibcon#[27=AT02-05\r\n] 2006.257.09:21:28.31#ibcon#*before write, iclass 38, count 2 2006.257.09:21:28.31#ibcon#enter sib2, iclass 38, count 2 2006.257.09:21:28.31#ibcon#flushed, iclass 38, count 2 2006.257.09:21:28.31#ibcon#about to write, iclass 38, count 2 2006.257.09:21:28.31#ibcon#wrote, iclass 38, count 2 2006.257.09:21:28.31#ibcon#about to read 3, iclass 38, count 2 2006.257.09:21:28.34#ibcon#read 3, iclass 38, count 2 2006.257.09:21:28.34#ibcon#about to read 4, iclass 38, count 2 2006.257.09:21:28.34#ibcon#read 4, iclass 38, count 2 2006.257.09:21:28.34#ibcon#about to read 5, iclass 38, count 2 2006.257.09:21:28.34#ibcon#read 5, iclass 38, count 2 2006.257.09:21:28.34#ibcon#about to read 6, iclass 38, count 2 2006.257.09:21:28.34#ibcon#read 6, iclass 38, count 2 2006.257.09:21:28.34#ibcon#end of sib2, iclass 38, count 2 2006.257.09:21:28.34#ibcon#*after write, iclass 38, count 2 2006.257.09:21:28.34#ibcon#*before return 0, iclass 38, count 2 2006.257.09:21:28.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:28.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:21:28.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.09:21:28.34#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:28.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:28.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:28.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:28.46#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:21:28.46#ibcon#first serial, iclass 38, count 0 2006.257.09:21:28.46#ibcon#enter sib2, iclass 38, count 0 2006.257.09:21:28.46#ibcon#flushed, iclass 38, count 0 2006.257.09:21:28.46#ibcon#about to write, iclass 38, count 0 2006.257.09:21:28.46#ibcon#wrote, iclass 38, count 0 2006.257.09:21:28.46#ibcon#about to read 3, iclass 38, count 0 2006.257.09:21:28.48#ibcon#read 3, iclass 38, count 0 2006.257.09:21:28.48#ibcon#about to read 4, iclass 38, count 0 2006.257.09:21:28.48#ibcon#read 4, iclass 38, count 0 2006.257.09:21:28.48#ibcon#about to read 5, iclass 38, count 0 2006.257.09:21:28.48#ibcon#read 5, iclass 38, count 0 2006.257.09:21:28.48#ibcon#about to read 6, iclass 38, count 0 2006.257.09:21:28.48#ibcon#read 6, iclass 38, count 0 2006.257.09:21:28.48#ibcon#end of sib2, iclass 38, count 0 2006.257.09:21:28.48#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:21:28.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:21:28.48#ibcon#[27=USB\r\n] 2006.257.09:21:28.48#ibcon#*before write, iclass 38, count 0 2006.257.09:21:28.48#ibcon#enter sib2, iclass 38, count 0 2006.257.09:21:28.48#ibcon#flushed, iclass 38, count 0 2006.257.09:21:28.48#ibcon#about to write, iclass 38, count 0 2006.257.09:21:28.48#ibcon#wrote, iclass 38, count 0 2006.257.09:21:28.48#ibcon#about to read 3, iclass 38, count 0 2006.257.09:21:28.51#ibcon#read 3, iclass 38, count 0 2006.257.09:21:28.51#ibcon#about to read 4, iclass 38, count 0 2006.257.09:21:28.51#ibcon#read 4, iclass 38, count 0 2006.257.09:21:28.51#ibcon#about to read 5, iclass 38, count 0 2006.257.09:21:28.51#ibcon#read 5, iclass 38, count 0 2006.257.09:21:28.51#ibcon#about to read 6, iclass 38, count 0 2006.257.09:21:28.51#ibcon#read 6, iclass 38, count 0 2006.257.09:21:28.51#ibcon#end of sib2, iclass 38, count 0 2006.257.09:21:28.51#ibcon#*after write, iclass 38, count 0 2006.257.09:21:28.51#ibcon#*before return 0, iclass 38, count 0 2006.257.09:21:28.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:28.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:21:28.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:21:28.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:21:28.51$vck44/vblo=3,649.99 2006.257.09:21:28.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.09:21:28.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.09:21:28.51#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:28.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:28.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:28.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:28.51#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:21:28.51#ibcon#first serial, iclass 40, count 0 2006.257.09:21:28.51#ibcon#enter sib2, iclass 40, count 0 2006.257.09:21:28.51#ibcon#flushed, iclass 40, count 0 2006.257.09:21:28.51#ibcon#about to write, iclass 40, count 0 2006.257.09:21:28.51#ibcon#wrote, iclass 40, count 0 2006.257.09:21:28.51#ibcon#about to read 3, iclass 40, count 0 2006.257.09:21:28.53#ibcon#read 3, iclass 40, count 0 2006.257.09:21:28.53#ibcon#about to read 4, iclass 40, count 0 2006.257.09:21:28.53#ibcon#read 4, iclass 40, count 0 2006.257.09:21:28.53#ibcon#about to read 5, iclass 40, count 0 2006.257.09:21:28.53#ibcon#read 5, iclass 40, count 0 2006.257.09:21:28.53#ibcon#about to read 6, iclass 40, count 0 2006.257.09:21:28.53#ibcon#read 6, iclass 40, count 0 2006.257.09:21:28.53#ibcon#end of sib2, iclass 40, count 0 2006.257.09:21:28.53#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:21:28.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:21:28.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:21:28.53#ibcon#*before write, iclass 40, count 0 2006.257.09:21:28.53#ibcon#enter sib2, iclass 40, count 0 2006.257.09:21:28.53#ibcon#flushed, iclass 40, count 0 2006.257.09:21:28.53#ibcon#about to write, iclass 40, count 0 2006.257.09:21:28.53#ibcon#wrote, iclass 40, count 0 2006.257.09:21:28.53#ibcon#about to read 3, iclass 40, count 0 2006.257.09:21:28.57#ibcon#read 3, iclass 40, count 0 2006.257.09:21:28.57#ibcon#about to read 4, iclass 40, count 0 2006.257.09:21:28.57#ibcon#read 4, iclass 40, count 0 2006.257.09:21:28.57#ibcon#about to read 5, iclass 40, count 0 2006.257.09:21:28.57#ibcon#read 5, iclass 40, count 0 2006.257.09:21:28.57#ibcon#about to read 6, iclass 40, count 0 2006.257.09:21:28.57#ibcon#read 6, iclass 40, count 0 2006.257.09:21:28.57#ibcon#end of sib2, iclass 40, count 0 2006.257.09:21:28.57#ibcon#*after write, iclass 40, count 0 2006.257.09:21:28.57#ibcon#*before return 0, iclass 40, count 0 2006.257.09:21:28.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:28.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:21:28.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:21:28.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:21:28.57$vck44/vb=3,4 2006.257.09:21:28.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.09:21:28.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.09:21:28.57#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:28.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:28.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:28.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:28.63#ibcon#enter wrdev, iclass 4, count 2 2006.257.09:21:28.63#ibcon#first serial, iclass 4, count 2 2006.257.09:21:28.63#ibcon#enter sib2, iclass 4, count 2 2006.257.09:21:28.63#ibcon#flushed, iclass 4, count 2 2006.257.09:21:28.63#ibcon#about to write, iclass 4, count 2 2006.257.09:21:28.63#ibcon#wrote, iclass 4, count 2 2006.257.09:21:28.63#ibcon#about to read 3, iclass 4, count 2 2006.257.09:21:28.65#ibcon#read 3, iclass 4, count 2 2006.257.09:21:28.65#ibcon#about to read 4, iclass 4, count 2 2006.257.09:21:28.65#ibcon#read 4, iclass 4, count 2 2006.257.09:21:28.65#ibcon#about to read 5, iclass 4, count 2 2006.257.09:21:28.65#ibcon#read 5, iclass 4, count 2 2006.257.09:21:28.65#ibcon#about to read 6, iclass 4, count 2 2006.257.09:21:28.65#ibcon#read 6, iclass 4, count 2 2006.257.09:21:28.65#ibcon#end of sib2, iclass 4, count 2 2006.257.09:21:28.65#ibcon#*mode == 0, iclass 4, count 2 2006.257.09:21:28.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.09:21:28.65#ibcon#[27=AT03-04\r\n] 2006.257.09:21:28.65#ibcon#*before write, iclass 4, count 2 2006.257.09:21:28.65#ibcon#enter sib2, iclass 4, count 2 2006.257.09:21:28.65#ibcon#flushed, iclass 4, count 2 2006.257.09:21:28.65#ibcon#about to write, iclass 4, count 2 2006.257.09:21:28.65#ibcon#wrote, iclass 4, count 2 2006.257.09:21:28.65#ibcon#about to read 3, iclass 4, count 2 2006.257.09:21:28.68#ibcon#read 3, iclass 4, count 2 2006.257.09:21:28.68#ibcon#about to read 4, iclass 4, count 2 2006.257.09:21:28.68#ibcon#read 4, iclass 4, count 2 2006.257.09:21:28.68#ibcon#about to read 5, iclass 4, count 2 2006.257.09:21:28.68#ibcon#read 5, iclass 4, count 2 2006.257.09:21:28.68#ibcon#about to read 6, iclass 4, count 2 2006.257.09:21:28.68#ibcon#read 6, iclass 4, count 2 2006.257.09:21:28.68#ibcon#end of sib2, iclass 4, count 2 2006.257.09:21:28.68#ibcon#*after write, iclass 4, count 2 2006.257.09:21:28.68#ibcon#*before return 0, iclass 4, count 2 2006.257.09:21:28.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:28.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:21:28.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.09:21:28.68#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:28.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:28.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:28.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:28.80#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:21:28.80#ibcon#first serial, iclass 4, count 0 2006.257.09:21:28.80#ibcon#enter sib2, iclass 4, count 0 2006.257.09:21:28.80#ibcon#flushed, iclass 4, count 0 2006.257.09:21:28.80#ibcon#about to write, iclass 4, count 0 2006.257.09:21:28.80#ibcon#wrote, iclass 4, count 0 2006.257.09:21:28.80#ibcon#about to read 3, iclass 4, count 0 2006.257.09:21:28.82#ibcon#read 3, iclass 4, count 0 2006.257.09:21:28.82#ibcon#about to read 4, iclass 4, count 0 2006.257.09:21:28.82#ibcon#read 4, iclass 4, count 0 2006.257.09:21:28.82#ibcon#about to read 5, iclass 4, count 0 2006.257.09:21:28.82#ibcon#read 5, iclass 4, count 0 2006.257.09:21:28.82#ibcon#about to read 6, iclass 4, count 0 2006.257.09:21:28.82#ibcon#read 6, iclass 4, count 0 2006.257.09:21:28.82#ibcon#end of sib2, iclass 4, count 0 2006.257.09:21:28.82#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:21:28.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:21:28.82#ibcon#[27=USB\r\n] 2006.257.09:21:28.82#ibcon#*before write, iclass 4, count 0 2006.257.09:21:28.82#ibcon#enter sib2, iclass 4, count 0 2006.257.09:21:28.82#ibcon#flushed, iclass 4, count 0 2006.257.09:21:28.82#ibcon#about to write, iclass 4, count 0 2006.257.09:21:28.82#ibcon#wrote, iclass 4, count 0 2006.257.09:21:28.82#ibcon#about to read 3, iclass 4, count 0 2006.257.09:21:28.85#ibcon#read 3, iclass 4, count 0 2006.257.09:21:28.85#ibcon#about to read 4, iclass 4, count 0 2006.257.09:21:28.85#ibcon#read 4, iclass 4, count 0 2006.257.09:21:28.85#ibcon#about to read 5, iclass 4, count 0 2006.257.09:21:28.85#ibcon#read 5, iclass 4, count 0 2006.257.09:21:28.85#ibcon#about to read 6, iclass 4, count 0 2006.257.09:21:28.85#ibcon#read 6, iclass 4, count 0 2006.257.09:21:28.85#ibcon#end of sib2, iclass 4, count 0 2006.257.09:21:28.85#ibcon#*after write, iclass 4, count 0 2006.257.09:21:28.85#ibcon#*before return 0, iclass 4, count 0 2006.257.09:21:28.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:28.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:21:28.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:21:28.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:21:28.85$vck44/vblo=4,679.99 2006.257.09:21:28.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.09:21:28.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.09:21:28.85#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:28.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:28.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:28.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:28.85#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:21:28.85#ibcon#first serial, iclass 6, count 0 2006.257.09:21:28.85#ibcon#enter sib2, iclass 6, count 0 2006.257.09:21:28.85#ibcon#flushed, iclass 6, count 0 2006.257.09:21:28.85#ibcon#about to write, iclass 6, count 0 2006.257.09:21:28.85#ibcon#wrote, iclass 6, count 0 2006.257.09:21:28.85#ibcon#about to read 3, iclass 6, count 0 2006.257.09:21:28.87#ibcon#read 3, iclass 6, count 0 2006.257.09:21:28.87#ibcon#about to read 4, iclass 6, count 0 2006.257.09:21:28.87#ibcon#read 4, iclass 6, count 0 2006.257.09:21:28.87#ibcon#about to read 5, iclass 6, count 0 2006.257.09:21:28.87#ibcon#read 5, iclass 6, count 0 2006.257.09:21:28.87#ibcon#about to read 6, iclass 6, count 0 2006.257.09:21:28.87#ibcon#read 6, iclass 6, count 0 2006.257.09:21:28.87#ibcon#end of sib2, iclass 6, count 0 2006.257.09:21:28.87#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:21:28.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:21:28.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:21:28.87#ibcon#*before write, iclass 6, count 0 2006.257.09:21:28.87#ibcon#enter sib2, iclass 6, count 0 2006.257.09:21:28.87#ibcon#flushed, iclass 6, count 0 2006.257.09:21:28.87#ibcon#about to write, iclass 6, count 0 2006.257.09:21:28.87#ibcon#wrote, iclass 6, count 0 2006.257.09:21:28.87#ibcon#about to read 3, iclass 6, count 0 2006.257.09:21:28.91#ibcon#read 3, iclass 6, count 0 2006.257.09:21:28.91#ibcon#about to read 4, iclass 6, count 0 2006.257.09:21:28.91#ibcon#read 4, iclass 6, count 0 2006.257.09:21:28.91#ibcon#about to read 5, iclass 6, count 0 2006.257.09:21:28.91#ibcon#read 5, iclass 6, count 0 2006.257.09:21:28.91#ibcon#about to read 6, iclass 6, count 0 2006.257.09:21:28.91#ibcon#read 6, iclass 6, count 0 2006.257.09:21:28.91#ibcon#end of sib2, iclass 6, count 0 2006.257.09:21:28.91#ibcon#*after write, iclass 6, count 0 2006.257.09:21:28.91#ibcon#*before return 0, iclass 6, count 0 2006.257.09:21:28.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:28.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:21:28.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:21:28.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:21:28.91$vck44/vb=4,5 2006.257.09:21:28.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.09:21:28.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.09:21:28.91#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:28.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:28.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:28.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:28.97#ibcon#enter wrdev, iclass 10, count 2 2006.257.09:21:28.97#ibcon#first serial, iclass 10, count 2 2006.257.09:21:28.97#ibcon#enter sib2, iclass 10, count 2 2006.257.09:21:28.97#ibcon#flushed, iclass 10, count 2 2006.257.09:21:28.97#ibcon#about to write, iclass 10, count 2 2006.257.09:21:28.97#ibcon#wrote, iclass 10, count 2 2006.257.09:21:28.97#ibcon#about to read 3, iclass 10, count 2 2006.257.09:21:28.99#ibcon#read 3, iclass 10, count 2 2006.257.09:21:28.99#ibcon#about to read 4, iclass 10, count 2 2006.257.09:21:28.99#ibcon#read 4, iclass 10, count 2 2006.257.09:21:28.99#ibcon#about to read 5, iclass 10, count 2 2006.257.09:21:28.99#ibcon#read 5, iclass 10, count 2 2006.257.09:21:28.99#ibcon#about to read 6, iclass 10, count 2 2006.257.09:21:28.99#ibcon#read 6, iclass 10, count 2 2006.257.09:21:28.99#ibcon#end of sib2, iclass 10, count 2 2006.257.09:21:28.99#ibcon#*mode == 0, iclass 10, count 2 2006.257.09:21:28.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.09:21:28.99#ibcon#[27=AT04-05\r\n] 2006.257.09:21:28.99#ibcon#*before write, iclass 10, count 2 2006.257.09:21:28.99#ibcon#enter sib2, iclass 10, count 2 2006.257.09:21:28.99#ibcon#flushed, iclass 10, count 2 2006.257.09:21:28.99#ibcon#about to write, iclass 10, count 2 2006.257.09:21:28.99#ibcon#wrote, iclass 10, count 2 2006.257.09:21:28.99#ibcon#about to read 3, iclass 10, count 2 2006.257.09:21:29.02#ibcon#read 3, iclass 10, count 2 2006.257.09:21:29.02#ibcon#about to read 4, iclass 10, count 2 2006.257.09:21:29.02#ibcon#read 4, iclass 10, count 2 2006.257.09:21:29.02#ibcon#about to read 5, iclass 10, count 2 2006.257.09:21:29.02#ibcon#read 5, iclass 10, count 2 2006.257.09:21:29.02#ibcon#about to read 6, iclass 10, count 2 2006.257.09:21:29.02#ibcon#read 6, iclass 10, count 2 2006.257.09:21:29.02#ibcon#end of sib2, iclass 10, count 2 2006.257.09:21:29.02#ibcon#*after write, iclass 10, count 2 2006.257.09:21:29.02#ibcon#*before return 0, iclass 10, count 2 2006.257.09:21:29.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:29.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:21:29.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.09:21:29.02#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:29.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:29.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:29.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:29.14#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:21:29.14#ibcon#first serial, iclass 10, count 0 2006.257.09:21:29.14#ibcon#enter sib2, iclass 10, count 0 2006.257.09:21:29.14#ibcon#flushed, iclass 10, count 0 2006.257.09:21:29.14#ibcon#about to write, iclass 10, count 0 2006.257.09:21:29.14#ibcon#wrote, iclass 10, count 0 2006.257.09:21:29.14#ibcon#about to read 3, iclass 10, count 0 2006.257.09:21:29.16#ibcon#read 3, iclass 10, count 0 2006.257.09:21:29.16#ibcon#about to read 4, iclass 10, count 0 2006.257.09:21:29.16#ibcon#read 4, iclass 10, count 0 2006.257.09:21:29.16#ibcon#about to read 5, iclass 10, count 0 2006.257.09:21:29.16#ibcon#read 5, iclass 10, count 0 2006.257.09:21:29.16#ibcon#about to read 6, iclass 10, count 0 2006.257.09:21:29.16#ibcon#read 6, iclass 10, count 0 2006.257.09:21:29.16#ibcon#end of sib2, iclass 10, count 0 2006.257.09:21:29.16#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:21:29.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:21:29.16#ibcon#[27=USB\r\n] 2006.257.09:21:29.16#ibcon#*before write, iclass 10, count 0 2006.257.09:21:29.16#ibcon#enter sib2, iclass 10, count 0 2006.257.09:21:29.16#ibcon#flushed, iclass 10, count 0 2006.257.09:21:29.16#ibcon#about to write, iclass 10, count 0 2006.257.09:21:29.16#ibcon#wrote, iclass 10, count 0 2006.257.09:21:29.16#ibcon#about to read 3, iclass 10, count 0 2006.257.09:21:29.19#ibcon#read 3, iclass 10, count 0 2006.257.09:21:29.19#ibcon#about to read 4, iclass 10, count 0 2006.257.09:21:29.19#ibcon#read 4, iclass 10, count 0 2006.257.09:21:29.19#ibcon#about to read 5, iclass 10, count 0 2006.257.09:21:29.19#ibcon#read 5, iclass 10, count 0 2006.257.09:21:29.19#ibcon#about to read 6, iclass 10, count 0 2006.257.09:21:29.19#ibcon#read 6, iclass 10, count 0 2006.257.09:21:29.19#ibcon#end of sib2, iclass 10, count 0 2006.257.09:21:29.19#ibcon#*after write, iclass 10, count 0 2006.257.09:21:29.19#ibcon#*before return 0, iclass 10, count 0 2006.257.09:21:29.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:29.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:21:29.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:21:29.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:21:29.19$vck44/vblo=5,709.99 2006.257.09:21:29.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.09:21:29.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.09:21:29.19#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:29.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:29.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:29.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:29.19#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:21:29.19#ibcon#first serial, iclass 12, count 0 2006.257.09:21:29.19#ibcon#enter sib2, iclass 12, count 0 2006.257.09:21:29.19#ibcon#flushed, iclass 12, count 0 2006.257.09:21:29.19#ibcon#about to write, iclass 12, count 0 2006.257.09:21:29.19#ibcon#wrote, iclass 12, count 0 2006.257.09:21:29.19#ibcon#about to read 3, iclass 12, count 0 2006.257.09:21:29.21#ibcon#read 3, iclass 12, count 0 2006.257.09:21:29.21#ibcon#about to read 4, iclass 12, count 0 2006.257.09:21:29.21#ibcon#read 4, iclass 12, count 0 2006.257.09:21:29.21#ibcon#about to read 5, iclass 12, count 0 2006.257.09:21:29.21#ibcon#read 5, iclass 12, count 0 2006.257.09:21:29.21#ibcon#about to read 6, iclass 12, count 0 2006.257.09:21:29.21#ibcon#read 6, iclass 12, count 0 2006.257.09:21:29.21#ibcon#end of sib2, iclass 12, count 0 2006.257.09:21:29.21#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:21:29.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:21:29.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:21:29.21#ibcon#*before write, iclass 12, count 0 2006.257.09:21:29.21#ibcon#enter sib2, iclass 12, count 0 2006.257.09:21:29.21#ibcon#flushed, iclass 12, count 0 2006.257.09:21:29.21#ibcon#about to write, iclass 12, count 0 2006.257.09:21:29.21#ibcon#wrote, iclass 12, count 0 2006.257.09:21:29.21#ibcon#about to read 3, iclass 12, count 0 2006.257.09:21:29.25#ibcon#read 3, iclass 12, count 0 2006.257.09:21:29.25#ibcon#about to read 4, iclass 12, count 0 2006.257.09:21:29.25#ibcon#read 4, iclass 12, count 0 2006.257.09:21:29.25#ibcon#about to read 5, iclass 12, count 0 2006.257.09:21:29.25#ibcon#read 5, iclass 12, count 0 2006.257.09:21:29.25#ibcon#about to read 6, iclass 12, count 0 2006.257.09:21:29.25#ibcon#read 6, iclass 12, count 0 2006.257.09:21:29.25#ibcon#end of sib2, iclass 12, count 0 2006.257.09:21:29.25#ibcon#*after write, iclass 12, count 0 2006.257.09:21:29.25#ibcon#*before return 0, iclass 12, count 0 2006.257.09:21:29.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:29.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:21:29.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:21:29.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:21:29.25$vck44/vb=5,4 2006.257.09:21:29.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.09:21:29.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.09:21:29.25#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:29.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:29.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:29.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:29.31#ibcon#enter wrdev, iclass 14, count 2 2006.257.09:21:29.31#ibcon#first serial, iclass 14, count 2 2006.257.09:21:29.31#ibcon#enter sib2, iclass 14, count 2 2006.257.09:21:29.31#ibcon#flushed, iclass 14, count 2 2006.257.09:21:29.31#ibcon#about to write, iclass 14, count 2 2006.257.09:21:29.31#ibcon#wrote, iclass 14, count 2 2006.257.09:21:29.31#ibcon#about to read 3, iclass 14, count 2 2006.257.09:21:29.33#ibcon#read 3, iclass 14, count 2 2006.257.09:21:29.33#ibcon#about to read 4, iclass 14, count 2 2006.257.09:21:29.33#ibcon#read 4, iclass 14, count 2 2006.257.09:21:29.33#ibcon#about to read 5, iclass 14, count 2 2006.257.09:21:29.33#ibcon#read 5, iclass 14, count 2 2006.257.09:21:29.33#ibcon#about to read 6, iclass 14, count 2 2006.257.09:21:29.33#ibcon#read 6, iclass 14, count 2 2006.257.09:21:29.33#ibcon#end of sib2, iclass 14, count 2 2006.257.09:21:29.33#ibcon#*mode == 0, iclass 14, count 2 2006.257.09:21:29.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.09:21:29.33#ibcon#[27=AT05-04\r\n] 2006.257.09:21:29.33#ibcon#*before write, iclass 14, count 2 2006.257.09:21:29.33#ibcon#enter sib2, iclass 14, count 2 2006.257.09:21:29.33#ibcon#flushed, iclass 14, count 2 2006.257.09:21:29.33#ibcon#about to write, iclass 14, count 2 2006.257.09:21:29.33#ibcon#wrote, iclass 14, count 2 2006.257.09:21:29.33#ibcon#about to read 3, iclass 14, count 2 2006.257.09:21:29.36#ibcon#read 3, iclass 14, count 2 2006.257.09:21:29.36#ibcon#about to read 4, iclass 14, count 2 2006.257.09:21:29.36#ibcon#read 4, iclass 14, count 2 2006.257.09:21:29.36#ibcon#about to read 5, iclass 14, count 2 2006.257.09:21:29.36#ibcon#read 5, iclass 14, count 2 2006.257.09:21:29.36#ibcon#about to read 6, iclass 14, count 2 2006.257.09:21:29.36#ibcon#read 6, iclass 14, count 2 2006.257.09:21:29.36#ibcon#end of sib2, iclass 14, count 2 2006.257.09:21:29.36#ibcon#*after write, iclass 14, count 2 2006.257.09:21:29.36#ibcon#*before return 0, iclass 14, count 2 2006.257.09:21:29.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:29.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:21:29.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.09:21:29.36#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:29.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:29.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:29.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:29.48#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:21:29.48#ibcon#first serial, iclass 14, count 0 2006.257.09:21:29.48#ibcon#enter sib2, iclass 14, count 0 2006.257.09:21:29.48#ibcon#flushed, iclass 14, count 0 2006.257.09:21:29.48#ibcon#about to write, iclass 14, count 0 2006.257.09:21:29.48#ibcon#wrote, iclass 14, count 0 2006.257.09:21:29.48#ibcon#about to read 3, iclass 14, count 0 2006.257.09:21:29.50#ibcon#read 3, iclass 14, count 0 2006.257.09:21:29.50#ibcon#about to read 4, iclass 14, count 0 2006.257.09:21:29.50#ibcon#read 4, iclass 14, count 0 2006.257.09:21:29.50#ibcon#about to read 5, iclass 14, count 0 2006.257.09:21:29.50#ibcon#read 5, iclass 14, count 0 2006.257.09:21:29.50#ibcon#about to read 6, iclass 14, count 0 2006.257.09:21:29.50#ibcon#read 6, iclass 14, count 0 2006.257.09:21:29.50#ibcon#end of sib2, iclass 14, count 0 2006.257.09:21:29.50#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:21:29.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:21:29.50#ibcon#[27=USB\r\n] 2006.257.09:21:29.50#ibcon#*before write, iclass 14, count 0 2006.257.09:21:29.50#ibcon#enter sib2, iclass 14, count 0 2006.257.09:21:29.50#ibcon#flushed, iclass 14, count 0 2006.257.09:21:29.50#ibcon#about to write, iclass 14, count 0 2006.257.09:21:29.50#ibcon#wrote, iclass 14, count 0 2006.257.09:21:29.50#ibcon#about to read 3, iclass 14, count 0 2006.257.09:21:29.53#ibcon#read 3, iclass 14, count 0 2006.257.09:21:29.53#ibcon#about to read 4, iclass 14, count 0 2006.257.09:21:29.53#ibcon#read 4, iclass 14, count 0 2006.257.09:21:29.53#ibcon#about to read 5, iclass 14, count 0 2006.257.09:21:29.53#ibcon#read 5, iclass 14, count 0 2006.257.09:21:29.53#ibcon#about to read 6, iclass 14, count 0 2006.257.09:21:29.53#ibcon#read 6, iclass 14, count 0 2006.257.09:21:29.53#ibcon#end of sib2, iclass 14, count 0 2006.257.09:21:29.53#ibcon#*after write, iclass 14, count 0 2006.257.09:21:29.53#ibcon#*before return 0, iclass 14, count 0 2006.257.09:21:29.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:29.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:21:29.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:21:29.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:21:29.53$vck44/vblo=6,719.99 2006.257.09:21:29.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.09:21:29.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.09:21:29.53#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:29.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:29.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:29.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:29.53#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:21:29.53#ibcon#first serial, iclass 16, count 0 2006.257.09:21:29.53#ibcon#enter sib2, iclass 16, count 0 2006.257.09:21:29.53#ibcon#flushed, iclass 16, count 0 2006.257.09:21:29.53#ibcon#about to write, iclass 16, count 0 2006.257.09:21:29.53#ibcon#wrote, iclass 16, count 0 2006.257.09:21:29.53#ibcon#about to read 3, iclass 16, count 0 2006.257.09:21:29.55#ibcon#read 3, iclass 16, count 0 2006.257.09:21:29.55#ibcon#about to read 4, iclass 16, count 0 2006.257.09:21:29.55#ibcon#read 4, iclass 16, count 0 2006.257.09:21:29.55#ibcon#about to read 5, iclass 16, count 0 2006.257.09:21:29.55#ibcon#read 5, iclass 16, count 0 2006.257.09:21:29.55#ibcon#about to read 6, iclass 16, count 0 2006.257.09:21:29.55#ibcon#read 6, iclass 16, count 0 2006.257.09:21:29.55#ibcon#end of sib2, iclass 16, count 0 2006.257.09:21:29.55#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:21:29.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:21:29.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:21:29.55#ibcon#*before write, iclass 16, count 0 2006.257.09:21:29.55#ibcon#enter sib2, iclass 16, count 0 2006.257.09:21:29.55#ibcon#flushed, iclass 16, count 0 2006.257.09:21:29.55#ibcon#about to write, iclass 16, count 0 2006.257.09:21:29.55#ibcon#wrote, iclass 16, count 0 2006.257.09:21:29.55#ibcon#about to read 3, iclass 16, count 0 2006.257.09:21:29.59#ibcon#read 3, iclass 16, count 0 2006.257.09:21:29.59#ibcon#about to read 4, iclass 16, count 0 2006.257.09:21:29.59#ibcon#read 4, iclass 16, count 0 2006.257.09:21:29.59#ibcon#about to read 5, iclass 16, count 0 2006.257.09:21:29.59#ibcon#read 5, iclass 16, count 0 2006.257.09:21:29.59#ibcon#about to read 6, iclass 16, count 0 2006.257.09:21:29.59#ibcon#read 6, iclass 16, count 0 2006.257.09:21:29.59#ibcon#end of sib2, iclass 16, count 0 2006.257.09:21:29.59#ibcon#*after write, iclass 16, count 0 2006.257.09:21:29.59#ibcon#*before return 0, iclass 16, count 0 2006.257.09:21:29.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:29.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:21:29.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:21:29.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:21:29.59$vck44/vb=6,4 2006.257.09:21:29.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.09:21:29.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.09:21:29.59#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:29.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:29.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:29.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:29.65#ibcon#enter wrdev, iclass 18, count 2 2006.257.09:21:29.65#ibcon#first serial, iclass 18, count 2 2006.257.09:21:29.65#ibcon#enter sib2, iclass 18, count 2 2006.257.09:21:29.65#ibcon#flushed, iclass 18, count 2 2006.257.09:21:29.65#ibcon#about to write, iclass 18, count 2 2006.257.09:21:29.65#ibcon#wrote, iclass 18, count 2 2006.257.09:21:29.65#ibcon#about to read 3, iclass 18, count 2 2006.257.09:21:29.67#ibcon#read 3, iclass 18, count 2 2006.257.09:21:29.67#ibcon#about to read 4, iclass 18, count 2 2006.257.09:21:29.67#ibcon#read 4, iclass 18, count 2 2006.257.09:21:29.67#ibcon#about to read 5, iclass 18, count 2 2006.257.09:21:29.67#ibcon#read 5, iclass 18, count 2 2006.257.09:21:29.67#ibcon#about to read 6, iclass 18, count 2 2006.257.09:21:29.67#ibcon#read 6, iclass 18, count 2 2006.257.09:21:29.67#ibcon#end of sib2, iclass 18, count 2 2006.257.09:21:29.67#ibcon#*mode == 0, iclass 18, count 2 2006.257.09:21:29.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.09:21:29.67#ibcon#[27=AT06-04\r\n] 2006.257.09:21:29.67#ibcon#*before write, iclass 18, count 2 2006.257.09:21:29.67#ibcon#enter sib2, iclass 18, count 2 2006.257.09:21:29.67#ibcon#flushed, iclass 18, count 2 2006.257.09:21:29.67#ibcon#about to write, iclass 18, count 2 2006.257.09:21:29.67#ibcon#wrote, iclass 18, count 2 2006.257.09:21:29.67#ibcon#about to read 3, iclass 18, count 2 2006.257.09:21:29.70#ibcon#read 3, iclass 18, count 2 2006.257.09:21:29.70#ibcon#about to read 4, iclass 18, count 2 2006.257.09:21:29.70#ibcon#read 4, iclass 18, count 2 2006.257.09:21:29.70#ibcon#about to read 5, iclass 18, count 2 2006.257.09:21:29.70#ibcon#read 5, iclass 18, count 2 2006.257.09:21:29.70#ibcon#about to read 6, iclass 18, count 2 2006.257.09:21:29.70#ibcon#read 6, iclass 18, count 2 2006.257.09:21:29.70#ibcon#end of sib2, iclass 18, count 2 2006.257.09:21:29.70#ibcon#*after write, iclass 18, count 2 2006.257.09:21:29.70#ibcon#*before return 0, iclass 18, count 2 2006.257.09:21:29.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:29.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:21:29.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.09:21:29.70#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:29.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:29.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:29.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:29.82#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:21:29.82#ibcon#first serial, iclass 18, count 0 2006.257.09:21:29.82#ibcon#enter sib2, iclass 18, count 0 2006.257.09:21:29.82#ibcon#flushed, iclass 18, count 0 2006.257.09:21:29.82#ibcon#about to write, iclass 18, count 0 2006.257.09:21:29.82#ibcon#wrote, iclass 18, count 0 2006.257.09:21:29.82#ibcon#about to read 3, iclass 18, count 0 2006.257.09:21:29.84#ibcon#read 3, iclass 18, count 0 2006.257.09:21:29.84#ibcon#about to read 4, iclass 18, count 0 2006.257.09:21:29.84#ibcon#read 4, iclass 18, count 0 2006.257.09:21:29.84#ibcon#about to read 5, iclass 18, count 0 2006.257.09:21:29.84#ibcon#read 5, iclass 18, count 0 2006.257.09:21:29.84#ibcon#about to read 6, iclass 18, count 0 2006.257.09:21:29.84#ibcon#read 6, iclass 18, count 0 2006.257.09:21:29.84#ibcon#end of sib2, iclass 18, count 0 2006.257.09:21:29.84#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:21:29.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:21:29.84#ibcon#[27=USB\r\n] 2006.257.09:21:29.84#ibcon#*before write, iclass 18, count 0 2006.257.09:21:29.84#ibcon#enter sib2, iclass 18, count 0 2006.257.09:21:29.84#ibcon#flushed, iclass 18, count 0 2006.257.09:21:29.84#ibcon#about to write, iclass 18, count 0 2006.257.09:21:29.84#ibcon#wrote, iclass 18, count 0 2006.257.09:21:29.84#ibcon#about to read 3, iclass 18, count 0 2006.257.09:21:29.87#ibcon#read 3, iclass 18, count 0 2006.257.09:21:29.87#ibcon#about to read 4, iclass 18, count 0 2006.257.09:21:29.87#ibcon#read 4, iclass 18, count 0 2006.257.09:21:29.87#ibcon#about to read 5, iclass 18, count 0 2006.257.09:21:29.87#ibcon#read 5, iclass 18, count 0 2006.257.09:21:29.87#ibcon#about to read 6, iclass 18, count 0 2006.257.09:21:29.87#ibcon#read 6, iclass 18, count 0 2006.257.09:21:29.87#ibcon#end of sib2, iclass 18, count 0 2006.257.09:21:29.87#ibcon#*after write, iclass 18, count 0 2006.257.09:21:29.87#ibcon#*before return 0, iclass 18, count 0 2006.257.09:21:29.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:29.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:21:29.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:21:29.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:21:29.87$vck44/vblo=7,734.99 2006.257.09:21:29.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.09:21:29.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.09:21:29.87#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:29.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:29.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:29.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:29.87#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:21:29.87#ibcon#first serial, iclass 20, count 0 2006.257.09:21:29.87#ibcon#enter sib2, iclass 20, count 0 2006.257.09:21:29.87#ibcon#flushed, iclass 20, count 0 2006.257.09:21:29.87#ibcon#about to write, iclass 20, count 0 2006.257.09:21:29.87#ibcon#wrote, iclass 20, count 0 2006.257.09:21:29.87#ibcon#about to read 3, iclass 20, count 0 2006.257.09:21:29.89#ibcon#read 3, iclass 20, count 0 2006.257.09:21:29.89#ibcon#about to read 4, iclass 20, count 0 2006.257.09:21:29.89#ibcon#read 4, iclass 20, count 0 2006.257.09:21:29.89#ibcon#about to read 5, iclass 20, count 0 2006.257.09:21:29.89#ibcon#read 5, iclass 20, count 0 2006.257.09:21:29.89#ibcon#about to read 6, iclass 20, count 0 2006.257.09:21:29.89#ibcon#read 6, iclass 20, count 0 2006.257.09:21:29.89#ibcon#end of sib2, iclass 20, count 0 2006.257.09:21:29.89#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:21:29.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:21:29.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:21:29.89#ibcon#*before write, iclass 20, count 0 2006.257.09:21:29.89#ibcon#enter sib2, iclass 20, count 0 2006.257.09:21:29.89#ibcon#flushed, iclass 20, count 0 2006.257.09:21:29.89#ibcon#about to write, iclass 20, count 0 2006.257.09:21:29.89#ibcon#wrote, iclass 20, count 0 2006.257.09:21:29.89#ibcon#about to read 3, iclass 20, count 0 2006.257.09:21:29.93#ibcon#read 3, iclass 20, count 0 2006.257.09:21:29.93#ibcon#about to read 4, iclass 20, count 0 2006.257.09:21:29.93#ibcon#read 4, iclass 20, count 0 2006.257.09:21:29.93#ibcon#about to read 5, iclass 20, count 0 2006.257.09:21:29.93#ibcon#read 5, iclass 20, count 0 2006.257.09:21:29.93#ibcon#about to read 6, iclass 20, count 0 2006.257.09:21:29.93#ibcon#read 6, iclass 20, count 0 2006.257.09:21:29.93#ibcon#end of sib2, iclass 20, count 0 2006.257.09:21:29.93#ibcon#*after write, iclass 20, count 0 2006.257.09:21:29.93#ibcon#*before return 0, iclass 20, count 0 2006.257.09:21:29.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:29.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:21:29.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:21:29.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:21:29.93$vck44/vb=7,4 2006.257.09:21:29.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.09:21:29.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.09:21:29.93#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:29.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:29.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:29.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:29.99#ibcon#enter wrdev, iclass 22, count 2 2006.257.09:21:29.99#ibcon#first serial, iclass 22, count 2 2006.257.09:21:29.99#ibcon#enter sib2, iclass 22, count 2 2006.257.09:21:29.99#ibcon#flushed, iclass 22, count 2 2006.257.09:21:29.99#ibcon#about to write, iclass 22, count 2 2006.257.09:21:29.99#ibcon#wrote, iclass 22, count 2 2006.257.09:21:29.99#ibcon#about to read 3, iclass 22, count 2 2006.257.09:21:30.01#ibcon#read 3, iclass 22, count 2 2006.257.09:21:30.01#ibcon#about to read 4, iclass 22, count 2 2006.257.09:21:30.01#ibcon#read 4, iclass 22, count 2 2006.257.09:21:30.01#ibcon#about to read 5, iclass 22, count 2 2006.257.09:21:30.01#ibcon#read 5, iclass 22, count 2 2006.257.09:21:30.01#ibcon#about to read 6, iclass 22, count 2 2006.257.09:21:30.01#ibcon#read 6, iclass 22, count 2 2006.257.09:21:30.01#ibcon#end of sib2, iclass 22, count 2 2006.257.09:21:30.01#ibcon#*mode == 0, iclass 22, count 2 2006.257.09:21:30.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.09:21:30.01#ibcon#[27=AT07-04\r\n] 2006.257.09:21:30.01#ibcon#*before write, iclass 22, count 2 2006.257.09:21:30.01#ibcon#enter sib2, iclass 22, count 2 2006.257.09:21:30.01#ibcon#flushed, iclass 22, count 2 2006.257.09:21:30.01#ibcon#about to write, iclass 22, count 2 2006.257.09:21:30.01#ibcon#wrote, iclass 22, count 2 2006.257.09:21:30.01#ibcon#about to read 3, iclass 22, count 2 2006.257.09:21:30.04#ibcon#read 3, iclass 22, count 2 2006.257.09:21:30.04#ibcon#about to read 4, iclass 22, count 2 2006.257.09:21:30.04#ibcon#read 4, iclass 22, count 2 2006.257.09:21:30.04#ibcon#about to read 5, iclass 22, count 2 2006.257.09:21:30.04#ibcon#read 5, iclass 22, count 2 2006.257.09:21:30.04#ibcon#about to read 6, iclass 22, count 2 2006.257.09:21:30.04#ibcon#read 6, iclass 22, count 2 2006.257.09:21:30.04#ibcon#end of sib2, iclass 22, count 2 2006.257.09:21:30.04#ibcon#*after write, iclass 22, count 2 2006.257.09:21:30.04#ibcon#*before return 0, iclass 22, count 2 2006.257.09:21:30.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:30.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:21:30.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.09:21:30.04#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:30.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:30.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:30.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:30.16#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:21:30.16#ibcon#first serial, iclass 22, count 0 2006.257.09:21:30.16#ibcon#enter sib2, iclass 22, count 0 2006.257.09:21:30.16#ibcon#flushed, iclass 22, count 0 2006.257.09:21:30.16#ibcon#about to write, iclass 22, count 0 2006.257.09:21:30.16#ibcon#wrote, iclass 22, count 0 2006.257.09:21:30.16#ibcon#about to read 3, iclass 22, count 0 2006.257.09:21:30.18#ibcon#read 3, iclass 22, count 0 2006.257.09:21:30.18#ibcon#about to read 4, iclass 22, count 0 2006.257.09:21:30.18#ibcon#read 4, iclass 22, count 0 2006.257.09:21:30.18#ibcon#about to read 5, iclass 22, count 0 2006.257.09:21:30.18#ibcon#read 5, iclass 22, count 0 2006.257.09:21:30.18#ibcon#about to read 6, iclass 22, count 0 2006.257.09:21:30.18#ibcon#read 6, iclass 22, count 0 2006.257.09:21:30.18#ibcon#end of sib2, iclass 22, count 0 2006.257.09:21:30.18#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:21:30.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:21:30.18#ibcon#[27=USB\r\n] 2006.257.09:21:30.18#ibcon#*before write, iclass 22, count 0 2006.257.09:21:30.18#ibcon#enter sib2, iclass 22, count 0 2006.257.09:21:30.18#ibcon#flushed, iclass 22, count 0 2006.257.09:21:30.18#ibcon#about to write, iclass 22, count 0 2006.257.09:21:30.18#ibcon#wrote, iclass 22, count 0 2006.257.09:21:30.18#ibcon#about to read 3, iclass 22, count 0 2006.257.09:21:30.21#ibcon#read 3, iclass 22, count 0 2006.257.09:21:30.21#ibcon#about to read 4, iclass 22, count 0 2006.257.09:21:30.21#ibcon#read 4, iclass 22, count 0 2006.257.09:21:30.21#ibcon#about to read 5, iclass 22, count 0 2006.257.09:21:30.21#ibcon#read 5, iclass 22, count 0 2006.257.09:21:30.21#ibcon#about to read 6, iclass 22, count 0 2006.257.09:21:30.21#ibcon#read 6, iclass 22, count 0 2006.257.09:21:30.21#ibcon#end of sib2, iclass 22, count 0 2006.257.09:21:30.21#ibcon#*after write, iclass 22, count 0 2006.257.09:21:30.21#ibcon#*before return 0, iclass 22, count 0 2006.257.09:21:30.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:30.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:21:30.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:21:30.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:21:30.21$vck44/vblo=8,744.99 2006.257.09:21:30.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.09:21:30.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.09:21:30.21#ibcon#ireg 17 cls_cnt 0 2006.257.09:21:30.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:30.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:30.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:30.21#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:21:30.21#ibcon#first serial, iclass 24, count 0 2006.257.09:21:30.21#ibcon#enter sib2, iclass 24, count 0 2006.257.09:21:30.21#ibcon#flushed, iclass 24, count 0 2006.257.09:21:30.21#ibcon#about to write, iclass 24, count 0 2006.257.09:21:30.21#ibcon#wrote, iclass 24, count 0 2006.257.09:21:30.21#ibcon#about to read 3, iclass 24, count 0 2006.257.09:21:30.23#ibcon#read 3, iclass 24, count 0 2006.257.09:21:30.23#ibcon#about to read 4, iclass 24, count 0 2006.257.09:21:30.23#ibcon#read 4, iclass 24, count 0 2006.257.09:21:30.23#ibcon#about to read 5, iclass 24, count 0 2006.257.09:21:30.23#ibcon#read 5, iclass 24, count 0 2006.257.09:21:30.23#ibcon#about to read 6, iclass 24, count 0 2006.257.09:21:30.23#ibcon#read 6, iclass 24, count 0 2006.257.09:21:30.23#ibcon#end of sib2, iclass 24, count 0 2006.257.09:21:30.23#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:21:30.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:21:30.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:21:30.23#ibcon#*before write, iclass 24, count 0 2006.257.09:21:30.23#ibcon#enter sib2, iclass 24, count 0 2006.257.09:21:30.23#ibcon#flushed, iclass 24, count 0 2006.257.09:21:30.23#ibcon#about to write, iclass 24, count 0 2006.257.09:21:30.23#ibcon#wrote, iclass 24, count 0 2006.257.09:21:30.23#ibcon#about to read 3, iclass 24, count 0 2006.257.09:21:30.27#ibcon#read 3, iclass 24, count 0 2006.257.09:21:30.27#ibcon#about to read 4, iclass 24, count 0 2006.257.09:21:30.27#ibcon#read 4, iclass 24, count 0 2006.257.09:21:30.27#ibcon#about to read 5, iclass 24, count 0 2006.257.09:21:30.27#ibcon#read 5, iclass 24, count 0 2006.257.09:21:30.27#ibcon#about to read 6, iclass 24, count 0 2006.257.09:21:30.27#ibcon#read 6, iclass 24, count 0 2006.257.09:21:30.27#ibcon#end of sib2, iclass 24, count 0 2006.257.09:21:30.27#ibcon#*after write, iclass 24, count 0 2006.257.09:21:30.27#ibcon#*before return 0, iclass 24, count 0 2006.257.09:21:30.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:30.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:21:30.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:21:30.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:21:30.27$vck44/vb=8,4 2006.257.09:21:30.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.09:21:30.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.09:21:30.27#ibcon#ireg 11 cls_cnt 2 2006.257.09:21:30.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:30.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:30.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:30.33#ibcon#enter wrdev, iclass 26, count 2 2006.257.09:21:30.33#ibcon#first serial, iclass 26, count 2 2006.257.09:21:30.33#ibcon#enter sib2, iclass 26, count 2 2006.257.09:21:30.33#ibcon#flushed, iclass 26, count 2 2006.257.09:21:30.33#ibcon#about to write, iclass 26, count 2 2006.257.09:21:30.33#ibcon#wrote, iclass 26, count 2 2006.257.09:21:30.33#ibcon#about to read 3, iclass 26, count 2 2006.257.09:21:30.35#ibcon#read 3, iclass 26, count 2 2006.257.09:21:30.35#ibcon#about to read 4, iclass 26, count 2 2006.257.09:21:30.35#ibcon#read 4, iclass 26, count 2 2006.257.09:21:30.35#ibcon#about to read 5, iclass 26, count 2 2006.257.09:21:30.35#ibcon#read 5, iclass 26, count 2 2006.257.09:21:30.35#ibcon#about to read 6, iclass 26, count 2 2006.257.09:21:30.35#ibcon#read 6, iclass 26, count 2 2006.257.09:21:30.35#ibcon#end of sib2, iclass 26, count 2 2006.257.09:21:30.35#ibcon#*mode == 0, iclass 26, count 2 2006.257.09:21:30.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.09:21:30.35#ibcon#[27=AT08-04\r\n] 2006.257.09:21:30.35#ibcon#*before write, iclass 26, count 2 2006.257.09:21:30.35#ibcon#enter sib2, iclass 26, count 2 2006.257.09:21:30.35#ibcon#flushed, iclass 26, count 2 2006.257.09:21:30.35#ibcon#about to write, iclass 26, count 2 2006.257.09:21:30.35#ibcon#wrote, iclass 26, count 2 2006.257.09:21:30.35#ibcon#about to read 3, iclass 26, count 2 2006.257.09:21:30.38#ibcon#read 3, iclass 26, count 2 2006.257.09:21:30.38#ibcon#about to read 4, iclass 26, count 2 2006.257.09:21:30.38#ibcon#read 4, iclass 26, count 2 2006.257.09:21:30.38#ibcon#about to read 5, iclass 26, count 2 2006.257.09:21:30.38#ibcon#read 5, iclass 26, count 2 2006.257.09:21:30.38#ibcon#about to read 6, iclass 26, count 2 2006.257.09:21:30.38#ibcon#read 6, iclass 26, count 2 2006.257.09:21:30.38#ibcon#end of sib2, iclass 26, count 2 2006.257.09:21:30.38#ibcon#*after write, iclass 26, count 2 2006.257.09:21:30.38#ibcon#*before return 0, iclass 26, count 2 2006.257.09:21:30.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:30.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:21:30.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.09:21:30.38#ibcon#ireg 7 cls_cnt 0 2006.257.09:21:30.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:30.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:30.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:30.50#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:21:30.50#ibcon#first serial, iclass 26, count 0 2006.257.09:21:30.50#ibcon#enter sib2, iclass 26, count 0 2006.257.09:21:30.50#ibcon#flushed, iclass 26, count 0 2006.257.09:21:30.50#ibcon#about to write, iclass 26, count 0 2006.257.09:21:30.50#ibcon#wrote, iclass 26, count 0 2006.257.09:21:30.50#ibcon#about to read 3, iclass 26, count 0 2006.257.09:21:30.52#ibcon#read 3, iclass 26, count 0 2006.257.09:21:30.52#ibcon#about to read 4, iclass 26, count 0 2006.257.09:21:30.52#ibcon#read 4, iclass 26, count 0 2006.257.09:21:30.52#ibcon#about to read 5, iclass 26, count 0 2006.257.09:21:30.52#ibcon#read 5, iclass 26, count 0 2006.257.09:21:30.52#ibcon#about to read 6, iclass 26, count 0 2006.257.09:21:30.52#ibcon#read 6, iclass 26, count 0 2006.257.09:21:30.52#ibcon#end of sib2, iclass 26, count 0 2006.257.09:21:30.52#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:21:30.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:21:30.52#ibcon#[27=USB\r\n] 2006.257.09:21:30.52#ibcon#*before write, iclass 26, count 0 2006.257.09:21:30.52#ibcon#enter sib2, iclass 26, count 0 2006.257.09:21:30.52#ibcon#flushed, iclass 26, count 0 2006.257.09:21:30.52#ibcon#about to write, iclass 26, count 0 2006.257.09:21:30.52#ibcon#wrote, iclass 26, count 0 2006.257.09:21:30.52#ibcon#about to read 3, iclass 26, count 0 2006.257.09:21:30.55#ibcon#read 3, iclass 26, count 0 2006.257.09:21:30.55#ibcon#about to read 4, iclass 26, count 0 2006.257.09:21:30.55#ibcon#read 4, iclass 26, count 0 2006.257.09:21:30.55#ibcon#about to read 5, iclass 26, count 0 2006.257.09:21:30.55#ibcon#read 5, iclass 26, count 0 2006.257.09:21:30.55#ibcon#about to read 6, iclass 26, count 0 2006.257.09:21:30.55#ibcon#read 6, iclass 26, count 0 2006.257.09:21:30.55#ibcon#end of sib2, iclass 26, count 0 2006.257.09:21:30.55#ibcon#*after write, iclass 26, count 0 2006.257.09:21:30.55#ibcon#*before return 0, iclass 26, count 0 2006.257.09:21:30.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:30.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:21:30.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:21:30.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:21:30.55$vck44/vabw=wide 2006.257.09:21:30.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.09:21:30.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.09:21:30.55#ibcon#ireg 8 cls_cnt 0 2006.257.09:21:30.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:30.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:30.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:30.55#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:21:30.55#ibcon#first serial, iclass 28, count 0 2006.257.09:21:30.55#ibcon#enter sib2, iclass 28, count 0 2006.257.09:21:30.55#ibcon#flushed, iclass 28, count 0 2006.257.09:21:30.55#ibcon#about to write, iclass 28, count 0 2006.257.09:21:30.55#ibcon#wrote, iclass 28, count 0 2006.257.09:21:30.55#ibcon#about to read 3, iclass 28, count 0 2006.257.09:21:30.57#ibcon#read 3, iclass 28, count 0 2006.257.09:21:30.57#ibcon#about to read 4, iclass 28, count 0 2006.257.09:21:30.57#ibcon#read 4, iclass 28, count 0 2006.257.09:21:30.57#ibcon#about to read 5, iclass 28, count 0 2006.257.09:21:30.57#ibcon#read 5, iclass 28, count 0 2006.257.09:21:30.57#ibcon#about to read 6, iclass 28, count 0 2006.257.09:21:30.57#ibcon#read 6, iclass 28, count 0 2006.257.09:21:30.57#ibcon#end of sib2, iclass 28, count 0 2006.257.09:21:30.57#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:21:30.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:21:30.57#ibcon#[25=BW32\r\n] 2006.257.09:21:30.57#ibcon#*before write, iclass 28, count 0 2006.257.09:21:30.57#ibcon#enter sib2, iclass 28, count 0 2006.257.09:21:30.57#ibcon#flushed, iclass 28, count 0 2006.257.09:21:30.57#ibcon#about to write, iclass 28, count 0 2006.257.09:21:30.57#ibcon#wrote, iclass 28, count 0 2006.257.09:21:30.57#ibcon#about to read 3, iclass 28, count 0 2006.257.09:21:30.60#ibcon#read 3, iclass 28, count 0 2006.257.09:21:30.60#ibcon#about to read 4, iclass 28, count 0 2006.257.09:21:30.60#ibcon#read 4, iclass 28, count 0 2006.257.09:21:30.60#ibcon#about to read 5, iclass 28, count 0 2006.257.09:21:30.60#ibcon#read 5, iclass 28, count 0 2006.257.09:21:30.60#ibcon#about to read 6, iclass 28, count 0 2006.257.09:21:30.60#ibcon#read 6, iclass 28, count 0 2006.257.09:21:30.60#ibcon#end of sib2, iclass 28, count 0 2006.257.09:21:30.60#ibcon#*after write, iclass 28, count 0 2006.257.09:21:30.60#ibcon#*before return 0, iclass 28, count 0 2006.257.09:21:30.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:30.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:21:30.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:21:30.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:21:30.60$vck44/vbbw=wide 2006.257.09:21:30.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.09:21:30.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.09:21:30.60#ibcon#ireg 8 cls_cnt 0 2006.257.09:21:30.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:21:30.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:21:30.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:21:30.67#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:21:30.67#ibcon#first serial, iclass 30, count 0 2006.257.09:21:30.67#ibcon#enter sib2, iclass 30, count 0 2006.257.09:21:30.67#ibcon#flushed, iclass 30, count 0 2006.257.09:21:30.67#ibcon#about to write, iclass 30, count 0 2006.257.09:21:30.67#ibcon#wrote, iclass 30, count 0 2006.257.09:21:30.67#ibcon#about to read 3, iclass 30, count 0 2006.257.09:21:30.69#ibcon#read 3, iclass 30, count 0 2006.257.09:21:30.69#ibcon#about to read 4, iclass 30, count 0 2006.257.09:21:30.69#ibcon#read 4, iclass 30, count 0 2006.257.09:21:30.69#ibcon#about to read 5, iclass 30, count 0 2006.257.09:21:30.69#ibcon#read 5, iclass 30, count 0 2006.257.09:21:30.69#ibcon#about to read 6, iclass 30, count 0 2006.257.09:21:30.69#ibcon#read 6, iclass 30, count 0 2006.257.09:21:30.69#ibcon#end of sib2, iclass 30, count 0 2006.257.09:21:30.69#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:21:30.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:21:30.69#ibcon#[27=BW32\r\n] 2006.257.09:21:30.69#ibcon#*before write, iclass 30, count 0 2006.257.09:21:30.69#ibcon#enter sib2, iclass 30, count 0 2006.257.09:21:30.69#ibcon#flushed, iclass 30, count 0 2006.257.09:21:30.69#ibcon#about to write, iclass 30, count 0 2006.257.09:21:30.69#ibcon#wrote, iclass 30, count 0 2006.257.09:21:30.69#ibcon#about to read 3, iclass 30, count 0 2006.257.09:21:30.72#ibcon#read 3, iclass 30, count 0 2006.257.09:21:30.72#ibcon#about to read 4, iclass 30, count 0 2006.257.09:21:30.72#ibcon#read 4, iclass 30, count 0 2006.257.09:21:30.72#ibcon#about to read 5, iclass 30, count 0 2006.257.09:21:30.72#ibcon#read 5, iclass 30, count 0 2006.257.09:21:30.72#ibcon#about to read 6, iclass 30, count 0 2006.257.09:21:30.72#ibcon#read 6, iclass 30, count 0 2006.257.09:21:30.72#ibcon#end of sib2, iclass 30, count 0 2006.257.09:21:30.72#ibcon#*after write, iclass 30, count 0 2006.257.09:21:30.72#ibcon#*before return 0, iclass 30, count 0 2006.257.09:21:30.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:21:30.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:21:30.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:21:30.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:21:30.72$setupk4/ifdk4 2006.257.09:21:30.72$ifdk4/lo= 2006.257.09:21:30.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:21:30.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:21:30.72$ifdk4/patch= 2006.257.09:21:30.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:21:30.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:21:30.72$setupk4/!*+20s 2006.257.09:21:31.26#abcon#<5=/15 1.0 2.3 19.75 951013.2\r\n> 2006.257.09:21:31.28#abcon#{5=INTERFACE CLEAR} 2006.257.09:21:31.34#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:21:41.43#abcon#<5=/15 0.9 2.3 19.75 951013.2\r\n> 2006.257.09:21:41.45#abcon#{5=INTERFACE CLEAR} 2006.257.09:21:41.51#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:21:45.23$setupk4/"tpicd 2006.257.09:21:45.23$setupk4/echo=off 2006.257.09:21:45.23$setupk4/xlog=off 2006.257.09:21:45.23:!2006.257.09:24:53 2006.257.09:21:48.14#trakl#Source acquired 2006.257.09:21:50.14#flagr#flagr/antenna,acquired 2006.257.09:24:53.00:preob 2006.257.09:24:54.13/onsource/TRACKING 2006.257.09:24:54.13:!2006.257.09:25:03 2006.257.09:25:03.00:"tape 2006.257.09:25:03.00:"st=record 2006.257.09:25:03.00:data_valid=on 2006.257.09:25:03.00:midob 2006.257.09:25:03.14/onsource/TRACKING 2006.257.09:25:03.14/wx/19.69,1013.2,95 2006.257.09:25:03.27/cable/+6.4747E-03 2006.257.09:25:04.36/va/01,08,usb,yes,31,34 2006.257.09:25:04.36/va/02,07,usb,yes,34,34 2006.257.09:25:04.36/va/03,08,usb,yes,30,32 2006.257.09:25:04.36/va/04,07,usb,yes,35,37 2006.257.09:25:04.36/va/05,04,usb,yes,31,32 2006.257.09:25:04.36/va/06,04,usb,yes,35,35 2006.257.09:25:04.36/va/07,04,usb,yes,36,36 2006.257.09:25:04.36/va/08,04,usb,yes,30,37 2006.257.09:25:04.59/valo/01,524.99,yes,locked 2006.257.09:25:04.59/valo/02,534.99,yes,locked 2006.257.09:25:04.59/valo/03,564.99,yes,locked 2006.257.09:25:04.59/valo/04,624.99,yes,locked 2006.257.09:25:04.59/valo/05,734.99,yes,locked 2006.257.09:25:04.59/valo/06,814.99,yes,locked 2006.257.09:25:04.59/valo/07,864.99,yes,locked 2006.257.09:25:04.59/valo/08,884.99,yes,locked 2006.257.09:25:05.68/vb/01,04,usb,yes,31,29 2006.257.09:25:05.68/vb/02,05,usb,yes,29,29 2006.257.09:25:05.68/vb/03,04,usb,yes,30,33 2006.257.09:25:05.68/vb/04,05,usb,yes,31,30 2006.257.09:25:05.68/vb/05,04,usb,yes,27,30 2006.257.09:25:05.68/vb/06,04,usb,yes,32,28 2006.257.09:25:05.68/vb/07,04,usb,yes,31,31 2006.257.09:25:05.68/vb/08,04,usb,yes,29,32 2006.257.09:25:05.92/vblo/01,629.99,yes,locked 2006.257.09:25:05.92/vblo/02,634.99,yes,locked 2006.257.09:25:05.92/vblo/03,649.99,yes,locked 2006.257.09:25:05.92/vblo/04,679.99,yes,locked 2006.257.09:25:05.92/vblo/05,709.99,yes,locked 2006.257.09:25:05.92/vblo/06,719.99,yes,locked 2006.257.09:25:05.92/vblo/07,734.99,yes,locked 2006.257.09:25:05.92/vblo/08,744.99,yes,locked 2006.257.09:25:06.07/vabw/8 2006.257.09:25:06.22/vbbw/8 2006.257.09:25:06.31/xfe/off,on,15.0 2006.257.09:25:06.68/ifatt/23,28,28,28 2006.257.09:25:07.08/fmout-gps/S +4.61E-07 2006.257.09:25:07.12:!2006.257.09:28:43 2006.257.09:28:43.00:data_valid=off 2006.257.09:28:43.00:"et 2006.257.09:28:43.00:!+3s 2006.257.09:28:46.01:"tape 2006.257.09:28:46.01:postob 2006.257.09:28:46.19/cable/+6.4747E-03 2006.257.09:28:46.19/wx/19.62,1013.3,95 2006.257.09:28:47.07/fmout-gps/S +4.61E-07 2006.257.09:28:47.07:scan_name=257-0932,jd0609,170 2006.257.09:28:47.07:source=2201+315,220314.98,314538.3,2000.0,cw 2006.257.09:28:48.14#flagr#flagr/antenna,new-source 2006.257.09:28:48.14:checkk5 2006.257.09:28:48.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:28:48.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:28:49.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:28:49.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:28:50.13/chk_obsdata//k5ts1/T2570925??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.09:28:50.52/chk_obsdata//k5ts2/T2570925??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.09:28:50.92/chk_obsdata//k5ts3/T2570925??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.09:28:51.32/chk_obsdata//k5ts4/T2570925??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.09:28:52.05/k5log//k5ts1_log_newline 2006.257.09:28:52.75/k5log//k5ts2_log_newline 2006.257.09:28:53.47/k5log//k5ts3_log_newline 2006.257.09:28:54.17/k5log//k5ts4_log_newline 2006.257.09:28:54.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:28:54.20:setupk4=1 2006.257.09:28:54.20$setupk4/echo=on 2006.257.09:28:54.20$setupk4/pcalon 2006.257.09:28:54.20$pcalon/"no phase cal control is implemented here 2006.257.09:28:54.20$setupk4/"tpicd=stop 2006.257.09:28:54.20$setupk4/"rec=synch_on 2006.257.09:28:54.20$setupk4/"rec_mode=128 2006.257.09:28:54.20$setupk4/!* 2006.257.09:28:54.20$setupk4/recpk4 2006.257.09:28:54.20$recpk4/recpatch= 2006.257.09:28:54.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:28:54.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:28:54.20$setupk4/vck44 2006.257.09:28:54.20$vck44/valo=1,524.99 2006.257.09:28:54.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.09:28:54.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.09:28:54.20#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:54.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:54.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:54.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:54.20#ibcon#enter wrdev, iclass 31, count 0 2006.257.09:28:54.20#ibcon#first serial, iclass 31, count 0 2006.257.09:28:54.20#ibcon#enter sib2, iclass 31, count 0 2006.257.09:28:54.20#ibcon#flushed, iclass 31, count 0 2006.257.09:28:54.20#ibcon#about to write, iclass 31, count 0 2006.257.09:28:54.20#ibcon#wrote, iclass 31, count 0 2006.257.09:28:54.20#ibcon#about to read 3, iclass 31, count 0 2006.257.09:28:54.22#ibcon#read 3, iclass 31, count 0 2006.257.09:28:54.22#ibcon#about to read 4, iclass 31, count 0 2006.257.09:28:54.22#ibcon#read 4, iclass 31, count 0 2006.257.09:28:54.22#ibcon#about to read 5, iclass 31, count 0 2006.257.09:28:54.22#ibcon#read 5, iclass 31, count 0 2006.257.09:28:54.22#ibcon#about to read 6, iclass 31, count 0 2006.257.09:28:54.22#ibcon#read 6, iclass 31, count 0 2006.257.09:28:54.22#ibcon#end of sib2, iclass 31, count 0 2006.257.09:28:54.22#ibcon#*mode == 0, iclass 31, count 0 2006.257.09:28:54.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.09:28:54.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:28:54.22#ibcon#*before write, iclass 31, count 0 2006.257.09:28:54.22#ibcon#enter sib2, iclass 31, count 0 2006.257.09:28:54.22#ibcon#flushed, iclass 31, count 0 2006.257.09:28:54.22#ibcon#about to write, iclass 31, count 0 2006.257.09:28:54.22#ibcon#wrote, iclass 31, count 0 2006.257.09:28:54.22#ibcon#about to read 3, iclass 31, count 0 2006.257.09:28:54.27#ibcon#read 3, iclass 31, count 0 2006.257.09:28:54.27#ibcon#about to read 4, iclass 31, count 0 2006.257.09:28:54.27#ibcon#read 4, iclass 31, count 0 2006.257.09:28:54.27#ibcon#about to read 5, iclass 31, count 0 2006.257.09:28:54.27#ibcon#read 5, iclass 31, count 0 2006.257.09:28:54.27#ibcon#about to read 6, iclass 31, count 0 2006.257.09:28:54.27#ibcon#read 6, iclass 31, count 0 2006.257.09:28:54.27#ibcon#end of sib2, iclass 31, count 0 2006.257.09:28:54.27#ibcon#*after write, iclass 31, count 0 2006.257.09:28:54.27#ibcon#*before return 0, iclass 31, count 0 2006.257.09:28:54.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:54.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:54.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.09:28:54.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.09:28:54.27$vck44/va=1,8 2006.257.09:28:54.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.09:28:54.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.09:28:54.27#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:54.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:54.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:54.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:54.27#ibcon#enter wrdev, iclass 33, count 2 2006.257.09:28:54.27#ibcon#first serial, iclass 33, count 2 2006.257.09:28:54.27#ibcon#enter sib2, iclass 33, count 2 2006.257.09:28:54.27#ibcon#flushed, iclass 33, count 2 2006.257.09:28:54.27#ibcon#about to write, iclass 33, count 2 2006.257.09:28:54.27#ibcon#wrote, iclass 33, count 2 2006.257.09:28:54.27#ibcon#about to read 3, iclass 33, count 2 2006.257.09:28:54.29#ibcon#read 3, iclass 33, count 2 2006.257.09:28:54.29#ibcon#about to read 4, iclass 33, count 2 2006.257.09:28:54.29#ibcon#read 4, iclass 33, count 2 2006.257.09:28:54.29#ibcon#about to read 5, iclass 33, count 2 2006.257.09:28:54.29#ibcon#read 5, iclass 33, count 2 2006.257.09:28:54.29#ibcon#about to read 6, iclass 33, count 2 2006.257.09:28:54.29#ibcon#read 6, iclass 33, count 2 2006.257.09:28:54.29#ibcon#end of sib2, iclass 33, count 2 2006.257.09:28:54.29#ibcon#*mode == 0, iclass 33, count 2 2006.257.09:28:54.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.09:28:54.29#ibcon#[25=AT01-08\r\n] 2006.257.09:28:54.29#ibcon#*before write, iclass 33, count 2 2006.257.09:28:54.29#ibcon#enter sib2, iclass 33, count 2 2006.257.09:28:54.29#ibcon#flushed, iclass 33, count 2 2006.257.09:28:54.29#ibcon#about to write, iclass 33, count 2 2006.257.09:28:54.29#ibcon#wrote, iclass 33, count 2 2006.257.09:28:54.29#ibcon#about to read 3, iclass 33, count 2 2006.257.09:28:54.32#ibcon#read 3, iclass 33, count 2 2006.257.09:28:54.32#ibcon#about to read 4, iclass 33, count 2 2006.257.09:28:54.32#ibcon#read 4, iclass 33, count 2 2006.257.09:28:54.32#ibcon#about to read 5, iclass 33, count 2 2006.257.09:28:54.32#ibcon#read 5, iclass 33, count 2 2006.257.09:28:54.32#ibcon#about to read 6, iclass 33, count 2 2006.257.09:28:54.32#ibcon#read 6, iclass 33, count 2 2006.257.09:28:54.32#ibcon#end of sib2, iclass 33, count 2 2006.257.09:28:54.32#ibcon#*after write, iclass 33, count 2 2006.257.09:28:54.32#ibcon#*before return 0, iclass 33, count 2 2006.257.09:28:54.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:54.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:54.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.09:28:54.32#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:54.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:54.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:54.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:54.44#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:28:54.44#ibcon#first serial, iclass 33, count 0 2006.257.09:28:54.44#ibcon#enter sib2, iclass 33, count 0 2006.257.09:28:54.44#ibcon#flushed, iclass 33, count 0 2006.257.09:28:54.44#ibcon#about to write, iclass 33, count 0 2006.257.09:28:54.44#ibcon#wrote, iclass 33, count 0 2006.257.09:28:54.44#ibcon#about to read 3, iclass 33, count 0 2006.257.09:28:54.46#ibcon#read 3, iclass 33, count 0 2006.257.09:28:54.46#ibcon#about to read 4, iclass 33, count 0 2006.257.09:28:54.46#ibcon#read 4, iclass 33, count 0 2006.257.09:28:54.46#ibcon#about to read 5, iclass 33, count 0 2006.257.09:28:54.46#ibcon#read 5, iclass 33, count 0 2006.257.09:28:54.46#ibcon#about to read 6, iclass 33, count 0 2006.257.09:28:54.46#ibcon#read 6, iclass 33, count 0 2006.257.09:28:54.46#ibcon#end of sib2, iclass 33, count 0 2006.257.09:28:54.46#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:28:54.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:28:54.46#ibcon#[25=USB\r\n] 2006.257.09:28:54.46#ibcon#*before write, iclass 33, count 0 2006.257.09:28:54.46#ibcon#enter sib2, iclass 33, count 0 2006.257.09:28:54.46#ibcon#flushed, iclass 33, count 0 2006.257.09:28:54.46#ibcon#about to write, iclass 33, count 0 2006.257.09:28:54.46#ibcon#wrote, iclass 33, count 0 2006.257.09:28:54.46#ibcon#about to read 3, iclass 33, count 0 2006.257.09:28:54.49#ibcon#read 3, iclass 33, count 0 2006.257.09:28:54.49#ibcon#about to read 4, iclass 33, count 0 2006.257.09:28:54.49#ibcon#read 4, iclass 33, count 0 2006.257.09:28:54.49#ibcon#about to read 5, iclass 33, count 0 2006.257.09:28:54.49#ibcon#read 5, iclass 33, count 0 2006.257.09:28:54.49#ibcon#about to read 6, iclass 33, count 0 2006.257.09:28:54.49#ibcon#read 6, iclass 33, count 0 2006.257.09:28:54.49#ibcon#end of sib2, iclass 33, count 0 2006.257.09:28:54.49#ibcon#*after write, iclass 33, count 0 2006.257.09:28:54.49#ibcon#*before return 0, iclass 33, count 0 2006.257.09:28:54.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:54.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:54.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:28:54.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:28:54.49$vck44/valo=2,534.99 2006.257.09:28:54.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.09:28:54.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.09:28:54.49#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:54.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:54.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:54.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:54.49#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:28:54.49#ibcon#first serial, iclass 35, count 0 2006.257.09:28:54.49#ibcon#enter sib2, iclass 35, count 0 2006.257.09:28:54.49#ibcon#flushed, iclass 35, count 0 2006.257.09:28:54.49#ibcon#about to write, iclass 35, count 0 2006.257.09:28:54.49#ibcon#wrote, iclass 35, count 0 2006.257.09:28:54.49#ibcon#about to read 3, iclass 35, count 0 2006.257.09:28:54.51#ibcon#read 3, iclass 35, count 0 2006.257.09:28:54.51#ibcon#about to read 4, iclass 35, count 0 2006.257.09:28:54.51#ibcon#read 4, iclass 35, count 0 2006.257.09:28:54.51#ibcon#about to read 5, iclass 35, count 0 2006.257.09:28:54.51#ibcon#read 5, iclass 35, count 0 2006.257.09:28:54.51#ibcon#about to read 6, iclass 35, count 0 2006.257.09:28:54.51#ibcon#read 6, iclass 35, count 0 2006.257.09:28:54.51#ibcon#end of sib2, iclass 35, count 0 2006.257.09:28:54.51#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:28:54.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:28:54.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:28:54.51#ibcon#*before write, iclass 35, count 0 2006.257.09:28:54.51#ibcon#enter sib2, iclass 35, count 0 2006.257.09:28:54.51#ibcon#flushed, iclass 35, count 0 2006.257.09:28:54.51#ibcon#about to write, iclass 35, count 0 2006.257.09:28:54.51#ibcon#wrote, iclass 35, count 0 2006.257.09:28:54.51#ibcon#about to read 3, iclass 35, count 0 2006.257.09:28:54.55#ibcon#read 3, iclass 35, count 0 2006.257.09:28:54.55#ibcon#about to read 4, iclass 35, count 0 2006.257.09:28:54.55#ibcon#read 4, iclass 35, count 0 2006.257.09:28:54.55#ibcon#about to read 5, iclass 35, count 0 2006.257.09:28:54.55#ibcon#read 5, iclass 35, count 0 2006.257.09:28:54.55#ibcon#about to read 6, iclass 35, count 0 2006.257.09:28:54.55#ibcon#read 6, iclass 35, count 0 2006.257.09:28:54.55#ibcon#end of sib2, iclass 35, count 0 2006.257.09:28:54.55#ibcon#*after write, iclass 35, count 0 2006.257.09:28:54.55#ibcon#*before return 0, iclass 35, count 0 2006.257.09:28:54.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:54.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:54.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:28:54.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:28:54.55$vck44/va=2,7 2006.257.09:28:54.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.09:28:54.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.09:28:54.55#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:54.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:54.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:54.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:54.61#ibcon#enter wrdev, iclass 37, count 2 2006.257.09:28:54.61#ibcon#first serial, iclass 37, count 2 2006.257.09:28:54.61#ibcon#enter sib2, iclass 37, count 2 2006.257.09:28:54.61#ibcon#flushed, iclass 37, count 2 2006.257.09:28:54.61#ibcon#about to write, iclass 37, count 2 2006.257.09:28:54.61#ibcon#wrote, iclass 37, count 2 2006.257.09:28:54.61#ibcon#about to read 3, iclass 37, count 2 2006.257.09:28:54.63#ibcon#read 3, iclass 37, count 2 2006.257.09:28:54.63#ibcon#about to read 4, iclass 37, count 2 2006.257.09:28:54.63#ibcon#read 4, iclass 37, count 2 2006.257.09:28:54.63#ibcon#about to read 5, iclass 37, count 2 2006.257.09:28:54.63#ibcon#read 5, iclass 37, count 2 2006.257.09:28:54.63#ibcon#about to read 6, iclass 37, count 2 2006.257.09:28:54.63#ibcon#read 6, iclass 37, count 2 2006.257.09:28:54.63#ibcon#end of sib2, iclass 37, count 2 2006.257.09:28:54.63#ibcon#*mode == 0, iclass 37, count 2 2006.257.09:28:54.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.09:28:54.63#ibcon#[25=AT02-07\r\n] 2006.257.09:28:54.63#ibcon#*before write, iclass 37, count 2 2006.257.09:28:54.63#ibcon#enter sib2, iclass 37, count 2 2006.257.09:28:54.63#ibcon#flushed, iclass 37, count 2 2006.257.09:28:54.63#ibcon#about to write, iclass 37, count 2 2006.257.09:28:54.63#ibcon#wrote, iclass 37, count 2 2006.257.09:28:54.63#ibcon#about to read 3, iclass 37, count 2 2006.257.09:28:54.66#ibcon#read 3, iclass 37, count 2 2006.257.09:28:54.66#ibcon#about to read 4, iclass 37, count 2 2006.257.09:28:54.66#ibcon#read 4, iclass 37, count 2 2006.257.09:28:54.66#ibcon#about to read 5, iclass 37, count 2 2006.257.09:28:54.66#ibcon#read 5, iclass 37, count 2 2006.257.09:28:54.66#ibcon#about to read 6, iclass 37, count 2 2006.257.09:28:54.66#ibcon#read 6, iclass 37, count 2 2006.257.09:28:54.66#ibcon#end of sib2, iclass 37, count 2 2006.257.09:28:54.66#ibcon#*after write, iclass 37, count 2 2006.257.09:28:54.66#ibcon#*before return 0, iclass 37, count 2 2006.257.09:28:54.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:54.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:54.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.09:28:54.66#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:54.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:54.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:54.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:54.78#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:28:54.78#ibcon#first serial, iclass 37, count 0 2006.257.09:28:54.78#ibcon#enter sib2, iclass 37, count 0 2006.257.09:28:54.78#ibcon#flushed, iclass 37, count 0 2006.257.09:28:54.78#ibcon#about to write, iclass 37, count 0 2006.257.09:28:54.78#ibcon#wrote, iclass 37, count 0 2006.257.09:28:54.78#ibcon#about to read 3, iclass 37, count 0 2006.257.09:28:54.80#ibcon#read 3, iclass 37, count 0 2006.257.09:28:54.80#ibcon#about to read 4, iclass 37, count 0 2006.257.09:28:54.80#ibcon#read 4, iclass 37, count 0 2006.257.09:28:54.80#ibcon#about to read 5, iclass 37, count 0 2006.257.09:28:54.80#ibcon#read 5, iclass 37, count 0 2006.257.09:28:54.80#ibcon#about to read 6, iclass 37, count 0 2006.257.09:28:54.80#ibcon#read 6, iclass 37, count 0 2006.257.09:28:54.80#ibcon#end of sib2, iclass 37, count 0 2006.257.09:28:54.80#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:28:54.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:28:54.80#ibcon#[25=USB\r\n] 2006.257.09:28:54.80#ibcon#*before write, iclass 37, count 0 2006.257.09:28:54.80#ibcon#enter sib2, iclass 37, count 0 2006.257.09:28:54.80#ibcon#flushed, iclass 37, count 0 2006.257.09:28:54.80#ibcon#about to write, iclass 37, count 0 2006.257.09:28:54.80#ibcon#wrote, iclass 37, count 0 2006.257.09:28:54.80#ibcon#about to read 3, iclass 37, count 0 2006.257.09:28:54.83#ibcon#read 3, iclass 37, count 0 2006.257.09:28:54.83#ibcon#about to read 4, iclass 37, count 0 2006.257.09:28:54.83#ibcon#read 4, iclass 37, count 0 2006.257.09:28:54.83#ibcon#about to read 5, iclass 37, count 0 2006.257.09:28:54.83#ibcon#read 5, iclass 37, count 0 2006.257.09:28:54.83#ibcon#about to read 6, iclass 37, count 0 2006.257.09:28:54.83#ibcon#read 6, iclass 37, count 0 2006.257.09:28:54.83#ibcon#end of sib2, iclass 37, count 0 2006.257.09:28:54.83#ibcon#*after write, iclass 37, count 0 2006.257.09:28:54.83#ibcon#*before return 0, iclass 37, count 0 2006.257.09:28:54.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:54.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:54.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:28:54.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:28:54.83$vck44/valo=3,564.99 2006.257.09:28:54.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.09:28:54.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.09:28:54.83#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:54.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:54.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:54.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:54.83#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:28:54.83#ibcon#first serial, iclass 39, count 0 2006.257.09:28:54.83#ibcon#enter sib2, iclass 39, count 0 2006.257.09:28:54.83#ibcon#flushed, iclass 39, count 0 2006.257.09:28:54.83#ibcon#about to write, iclass 39, count 0 2006.257.09:28:54.83#ibcon#wrote, iclass 39, count 0 2006.257.09:28:54.83#ibcon#about to read 3, iclass 39, count 0 2006.257.09:28:54.85#ibcon#read 3, iclass 39, count 0 2006.257.09:28:54.85#ibcon#about to read 4, iclass 39, count 0 2006.257.09:28:54.85#ibcon#read 4, iclass 39, count 0 2006.257.09:28:54.85#ibcon#about to read 5, iclass 39, count 0 2006.257.09:28:54.85#ibcon#read 5, iclass 39, count 0 2006.257.09:28:54.85#ibcon#about to read 6, iclass 39, count 0 2006.257.09:28:54.85#ibcon#read 6, iclass 39, count 0 2006.257.09:28:54.85#ibcon#end of sib2, iclass 39, count 0 2006.257.09:28:54.85#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:28:54.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:28:54.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:28:54.85#ibcon#*before write, iclass 39, count 0 2006.257.09:28:54.85#ibcon#enter sib2, iclass 39, count 0 2006.257.09:28:54.85#ibcon#flushed, iclass 39, count 0 2006.257.09:28:54.85#ibcon#about to write, iclass 39, count 0 2006.257.09:28:54.85#ibcon#wrote, iclass 39, count 0 2006.257.09:28:54.85#ibcon#about to read 3, iclass 39, count 0 2006.257.09:28:54.89#ibcon#read 3, iclass 39, count 0 2006.257.09:28:54.89#ibcon#about to read 4, iclass 39, count 0 2006.257.09:28:54.89#ibcon#read 4, iclass 39, count 0 2006.257.09:28:54.89#ibcon#about to read 5, iclass 39, count 0 2006.257.09:28:54.89#ibcon#read 5, iclass 39, count 0 2006.257.09:28:54.89#ibcon#about to read 6, iclass 39, count 0 2006.257.09:28:54.89#ibcon#read 6, iclass 39, count 0 2006.257.09:28:54.89#ibcon#end of sib2, iclass 39, count 0 2006.257.09:28:54.89#ibcon#*after write, iclass 39, count 0 2006.257.09:28:54.89#ibcon#*before return 0, iclass 39, count 0 2006.257.09:28:54.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:54.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:54.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:28:54.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:28:54.89$vck44/va=3,8 2006.257.09:28:54.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.09:28:54.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.09:28:54.89#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:54.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:54.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:54.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:54.95#ibcon#enter wrdev, iclass 3, count 2 2006.257.09:28:54.95#ibcon#first serial, iclass 3, count 2 2006.257.09:28:54.95#ibcon#enter sib2, iclass 3, count 2 2006.257.09:28:54.95#ibcon#flushed, iclass 3, count 2 2006.257.09:28:54.95#ibcon#about to write, iclass 3, count 2 2006.257.09:28:54.95#ibcon#wrote, iclass 3, count 2 2006.257.09:28:54.95#ibcon#about to read 3, iclass 3, count 2 2006.257.09:28:54.97#ibcon#read 3, iclass 3, count 2 2006.257.09:28:54.97#ibcon#about to read 4, iclass 3, count 2 2006.257.09:28:54.97#ibcon#read 4, iclass 3, count 2 2006.257.09:28:54.97#ibcon#about to read 5, iclass 3, count 2 2006.257.09:28:54.97#ibcon#read 5, iclass 3, count 2 2006.257.09:28:54.97#ibcon#about to read 6, iclass 3, count 2 2006.257.09:28:54.97#ibcon#read 6, iclass 3, count 2 2006.257.09:28:54.97#ibcon#end of sib2, iclass 3, count 2 2006.257.09:28:54.97#ibcon#*mode == 0, iclass 3, count 2 2006.257.09:28:54.97#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.09:28:54.97#ibcon#[25=AT03-08\r\n] 2006.257.09:28:54.97#ibcon#*before write, iclass 3, count 2 2006.257.09:28:54.97#ibcon#enter sib2, iclass 3, count 2 2006.257.09:28:54.97#ibcon#flushed, iclass 3, count 2 2006.257.09:28:54.97#ibcon#about to write, iclass 3, count 2 2006.257.09:28:54.97#ibcon#wrote, iclass 3, count 2 2006.257.09:28:54.97#ibcon#about to read 3, iclass 3, count 2 2006.257.09:28:55.00#ibcon#read 3, iclass 3, count 2 2006.257.09:28:55.00#ibcon#about to read 4, iclass 3, count 2 2006.257.09:28:55.00#ibcon#read 4, iclass 3, count 2 2006.257.09:28:55.00#ibcon#about to read 5, iclass 3, count 2 2006.257.09:28:55.00#ibcon#read 5, iclass 3, count 2 2006.257.09:28:55.00#ibcon#about to read 6, iclass 3, count 2 2006.257.09:28:55.00#ibcon#read 6, iclass 3, count 2 2006.257.09:28:55.00#ibcon#end of sib2, iclass 3, count 2 2006.257.09:28:55.00#ibcon#*after write, iclass 3, count 2 2006.257.09:28:55.00#ibcon#*before return 0, iclass 3, count 2 2006.257.09:28:55.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:55.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:55.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.09:28:55.00#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:55.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:55.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:55.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:55.12#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:28:55.12#ibcon#first serial, iclass 3, count 0 2006.257.09:28:55.12#ibcon#enter sib2, iclass 3, count 0 2006.257.09:28:55.12#ibcon#flushed, iclass 3, count 0 2006.257.09:28:55.12#ibcon#about to write, iclass 3, count 0 2006.257.09:28:55.12#ibcon#wrote, iclass 3, count 0 2006.257.09:28:55.12#ibcon#about to read 3, iclass 3, count 0 2006.257.09:28:55.14#ibcon#read 3, iclass 3, count 0 2006.257.09:28:55.14#ibcon#about to read 4, iclass 3, count 0 2006.257.09:28:55.14#ibcon#read 4, iclass 3, count 0 2006.257.09:28:55.14#ibcon#about to read 5, iclass 3, count 0 2006.257.09:28:55.14#ibcon#read 5, iclass 3, count 0 2006.257.09:28:55.14#ibcon#about to read 6, iclass 3, count 0 2006.257.09:28:55.14#ibcon#read 6, iclass 3, count 0 2006.257.09:28:55.14#ibcon#end of sib2, iclass 3, count 0 2006.257.09:28:55.14#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:28:55.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:28:55.14#ibcon#[25=USB\r\n] 2006.257.09:28:55.14#ibcon#*before write, iclass 3, count 0 2006.257.09:28:55.14#ibcon#enter sib2, iclass 3, count 0 2006.257.09:28:55.14#ibcon#flushed, iclass 3, count 0 2006.257.09:28:55.14#ibcon#about to write, iclass 3, count 0 2006.257.09:28:55.14#ibcon#wrote, iclass 3, count 0 2006.257.09:28:55.14#ibcon#about to read 3, iclass 3, count 0 2006.257.09:28:55.17#ibcon#read 3, iclass 3, count 0 2006.257.09:28:55.17#ibcon#about to read 4, iclass 3, count 0 2006.257.09:28:55.17#ibcon#read 4, iclass 3, count 0 2006.257.09:28:55.17#ibcon#about to read 5, iclass 3, count 0 2006.257.09:28:55.17#ibcon#read 5, iclass 3, count 0 2006.257.09:28:55.17#ibcon#about to read 6, iclass 3, count 0 2006.257.09:28:55.17#ibcon#read 6, iclass 3, count 0 2006.257.09:28:55.17#ibcon#end of sib2, iclass 3, count 0 2006.257.09:28:55.17#ibcon#*after write, iclass 3, count 0 2006.257.09:28:55.17#ibcon#*before return 0, iclass 3, count 0 2006.257.09:28:55.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:55.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:55.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:28:55.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:28:55.17$vck44/valo=4,624.99 2006.257.09:28:55.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.09:28:55.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.09:28:55.17#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:55.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:55.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:55.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:55.17#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:28:55.17#ibcon#first serial, iclass 5, count 0 2006.257.09:28:55.17#ibcon#enter sib2, iclass 5, count 0 2006.257.09:28:55.17#ibcon#flushed, iclass 5, count 0 2006.257.09:28:55.17#ibcon#about to write, iclass 5, count 0 2006.257.09:28:55.17#ibcon#wrote, iclass 5, count 0 2006.257.09:28:55.17#ibcon#about to read 3, iclass 5, count 0 2006.257.09:28:55.19#ibcon#read 3, iclass 5, count 0 2006.257.09:28:55.19#ibcon#about to read 4, iclass 5, count 0 2006.257.09:28:55.19#ibcon#read 4, iclass 5, count 0 2006.257.09:28:55.19#ibcon#about to read 5, iclass 5, count 0 2006.257.09:28:55.19#ibcon#read 5, iclass 5, count 0 2006.257.09:28:55.19#ibcon#about to read 6, iclass 5, count 0 2006.257.09:28:55.19#ibcon#read 6, iclass 5, count 0 2006.257.09:28:55.19#ibcon#end of sib2, iclass 5, count 0 2006.257.09:28:55.19#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:28:55.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:28:55.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:28:55.19#ibcon#*before write, iclass 5, count 0 2006.257.09:28:55.19#ibcon#enter sib2, iclass 5, count 0 2006.257.09:28:55.19#ibcon#flushed, iclass 5, count 0 2006.257.09:28:55.19#ibcon#about to write, iclass 5, count 0 2006.257.09:28:55.19#ibcon#wrote, iclass 5, count 0 2006.257.09:28:55.19#ibcon#about to read 3, iclass 5, count 0 2006.257.09:28:55.23#ibcon#read 3, iclass 5, count 0 2006.257.09:28:55.23#ibcon#about to read 4, iclass 5, count 0 2006.257.09:28:55.23#ibcon#read 4, iclass 5, count 0 2006.257.09:28:55.23#ibcon#about to read 5, iclass 5, count 0 2006.257.09:28:55.23#ibcon#read 5, iclass 5, count 0 2006.257.09:28:55.23#ibcon#about to read 6, iclass 5, count 0 2006.257.09:28:55.23#ibcon#read 6, iclass 5, count 0 2006.257.09:28:55.23#ibcon#end of sib2, iclass 5, count 0 2006.257.09:28:55.23#ibcon#*after write, iclass 5, count 0 2006.257.09:28:55.23#ibcon#*before return 0, iclass 5, count 0 2006.257.09:28:55.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:55.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:55.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:28:55.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:28:55.23$vck44/va=4,7 2006.257.09:28:55.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.09:28:55.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.09:28:55.23#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:55.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:55.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:55.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:55.29#ibcon#enter wrdev, iclass 7, count 2 2006.257.09:28:55.29#ibcon#first serial, iclass 7, count 2 2006.257.09:28:55.29#ibcon#enter sib2, iclass 7, count 2 2006.257.09:28:55.29#ibcon#flushed, iclass 7, count 2 2006.257.09:28:55.29#ibcon#about to write, iclass 7, count 2 2006.257.09:28:55.29#ibcon#wrote, iclass 7, count 2 2006.257.09:28:55.29#ibcon#about to read 3, iclass 7, count 2 2006.257.09:28:55.31#ibcon#read 3, iclass 7, count 2 2006.257.09:28:55.31#ibcon#about to read 4, iclass 7, count 2 2006.257.09:28:55.31#ibcon#read 4, iclass 7, count 2 2006.257.09:28:55.31#ibcon#about to read 5, iclass 7, count 2 2006.257.09:28:55.31#ibcon#read 5, iclass 7, count 2 2006.257.09:28:55.31#ibcon#about to read 6, iclass 7, count 2 2006.257.09:28:55.31#ibcon#read 6, iclass 7, count 2 2006.257.09:28:55.31#ibcon#end of sib2, iclass 7, count 2 2006.257.09:28:55.31#ibcon#*mode == 0, iclass 7, count 2 2006.257.09:28:55.31#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.09:28:55.31#ibcon#[25=AT04-07\r\n] 2006.257.09:28:55.31#ibcon#*before write, iclass 7, count 2 2006.257.09:28:55.31#ibcon#enter sib2, iclass 7, count 2 2006.257.09:28:55.31#ibcon#flushed, iclass 7, count 2 2006.257.09:28:55.31#ibcon#about to write, iclass 7, count 2 2006.257.09:28:55.31#ibcon#wrote, iclass 7, count 2 2006.257.09:28:55.31#ibcon#about to read 3, iclass 7, count 2 2006.257.09:28:55.34#ibcon#read 3, iclass 7, count 2 2006.257.09:28:55.34#ibcon#about to read 4, iclass 7, count 2 2006.257.09:28:55.34#ibcon#read 4, iclass 7, count 2 2006.257.09:28:55.34#ibcon#about to read 5, iclass 7, count 2 2006.257.09:28:55.34#ibcon#read 5, iclass 7, count 2 2006.257.09:28:55.34#ibcon#about to read 6, iclass 7, count 2 2006.257.09:28:55.34#ibcon#read 6, iclass 7, count 2 2006.257.09:28:55.34#ibcon#end of sib2, iclass 7, count 2 2006.257.09:28:55.34#ibcon#*after write, iclass 7, count 2 2006.257.09:28:55.34#ibcon#*before return 0, iclass 7, count 2 2006.257.09:28:55.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:55.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:55.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.09:28:55.34#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:55.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:55.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:55.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:55.46#ibcon#enter wrdev, iclass 7, count 0 2006.257.09:28:55.46#ibcon#first serial, iclass 7, count 0 2006.257.09:28:55.46#ibcon#enter sib2, iclass 7, count 0 2006.257.09:28:55.46#ibcon#flushed, iclass 7, count 0 2006.257.09:28:55.46#ibcon#about to write, iclass 7, count 0 2006.257.09:28:55.46#ibcon#wrote, iclass 7, count 0 2006.257.09:28:55.46#ibcon#about to read 3, iclass 7, count 0 2006.257.09:28:55.48#ibcon#read 3, iclass 7, count 0 2006.257.09:28:55.48#ibcon#about to read 4, iclass 7, count 0 2006.257.09:28:55.48#ibcon#read 4, iclass 7, count 0 2006.257.09:28:55.48#ibcon#about to read 5, iclass 7, count 0 2006.257.09:28:55.48#ibcon#read 5, iclass 7, count 0 2006.257.09:28:55.48#ibcon#about to read 6, iclass 7, count 0 2006.257.09:28:55.48#ibcon#read 6, iclass 7, count 0 2006.257.09:28:55.48#ibcon#end of sib2, iclass 7, count 0 2006.257.09:28:55.48#ibcon#*mode == 0, iclass 7, count 0 2006.257.09:28:55.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.09:28:55.48#ibcon#[25=USB\r\n] 2006.257.09:28:55.48#ibcon#*before write, iclass 7, count 0 2006.257.09:28:55.48#ibcon#enter sib2, iclass 7, count 0 2006.257.09:28:55.48#ibcon#flushed, iclass 7, count 0 2006.257.09:28:55.48#ibcon#about to write, iclass 7, count 0 2006.257.09:28:55.48#ibcon#wrote, iclass 7, count 0 2006.257.09:28:55.48#ibcon#about to read 3, iclass 7, count 0 2006.257.09:28:55.51#ibcon#read 3, iclass 7, count 0 2006.257.09:28:55.51#ibcon#about to read 4, iclass 7, count 0 2006.257.09:28:55.51#ibcon#read 4, iclass 7, count 0 2006.257.09:28:55.51#ibcon#about to read 5, iclass 7, count 0 2006.257.09:28:55.51#ibcon#read 5, iclass 7, count 0 2006.257.09:28:55.51#ibcon#about to read 6, iclass 7, count 0 2006.257.09:28:55.51#ibcon#read 6, iclass 7, count 0 2006.257.09:28:55.51#ibcon#end of sib2, iclass 7, count 0 2006.257.09:28:55.51#ibcon#*after write, iclass 7, count 0 2006.257.09:28:55.51#ibcon#*before return 0, iclass 7, count 0 2006.257.09:28:55.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:55.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:55.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.09:28:55.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.09:28:55.51$vck44/valo=5,734.99 2006.257.09:28:55.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.09:28:55.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.09:28:55.51#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:55.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:55.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:55.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:55.51#ibcon#enter wrdev, iclass 11, count 0 2006.257.09:28:55.51#ibcon#first serial, iclass 11, count 0 2006.257.09:28:55.51#ibcon#enter sib2, iclass 11, count 0 2006.257.09:28:55.51#ibcon#flushed, iclass 11, count 0 2006.257.09:28:55.51#ibcon#about to write, iclass 11, count 0 2006.257.09:28:55.51#ibcon#wrote, iclass 11, count 0 2006.257.09:28:55.51#ibcon#about to read 3, iclass 11, count 0 2006.257.09:28:55.53#ibcon#read 3, iclass 11, count 0 2006.257.09:28:55.53#ibcon#about to read 4, iclass 11, count 0 2006.257.09:28:55.53#ibcon#read 4, iclass 11, count 0 2006.257.09:28:55.53#ibcon#about to read 5, iclass 11, count 0 2006.257.09:28:55.53#ibcon#read 5, iclass 11, count 0 2006.257.09:28:55.53#ibcon#about to read 6, iclass 11, count 0 2006.257.09:28:55.53#ibcon#read 6, iclass 11, count 0 2006.257.09:28:55.53#ibcon#end of sib2, iclass 11, count 0 2006.257.09:28:55.53#ibcon#*mode == 0, iclass 11, count 0 2006.257.09:28:55.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.09:28:55.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:28:55.53#ibcon#*before write, iclass 11, count 0 2006.257.09:28:55.53#ibcon#enter sib2, iclass 11, count 0 2006.257.09:28:55.53#ibcon#flushed, iclass 11, count 0 2006.257.09:28:55.53#ibcon#about to write, iclass 11, count 0 2006.257.09:28:55.53#ibcon#wrote, iclass 11, count 0 2006.257.09:28:55.53#ibcon#about to read 3, iclass 11, count 0 2006.257.09:28:55.57#ibcon#read 3, iclass 11, count 0 2006.257.09:28:55.57#ibcon#about to read 4, iclass 11, count 0 2006.257.09:28:55.57#ibcon#read 4, iclass 11, count 0 2006.257.09:28:55.57#ibcon#about to read 5, iclass 11, count 0 2006.257.09:28:55.57#ibcon#read 5, iclass 11, count 0 2006.257.09:28:55.57#ibcon#about to read 6, iclass 11, count 0 2006.257.09:28:55.57#ibcon#read 6, iclass 11, count 0 2006.257.09:28:55.57#ibcon#end of sib2, iclass 11, count 0 2006.257.09:28:55.57#ibcon#*after write, iclass 11, count 0 2006.257.09:28:55.57#ibcon#*before return 0, iclass 11, count 0 2006.257.09:28:55.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:55.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:55.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.09:28:55.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.09:28:55.57$vck44/va=5,4 2006.257.09:28:55.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.09:28:55.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.09:28:55.57#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:55.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:55.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:55.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:55.63#ibcon#enter wrdev, iclass 13, count 2 2006.257.09:28:55.63#ibcon#first serial, iclass 13, count 2 2006.257.09:28:55.63#ibcon#enter sib2, iclass 13, count 2 2006.257.09:28:55.63#ibcon#flushed, iclass 13, count 2 2006.257.09:28:55.63#ibcon#about to write, iclass 13, count 2 2006.257.09:28:55.63#ibcon#wrote, iclass 13, count 2 2006.257.09:28:55.63#ibcon#about to read 3, iclass 13, count 2 2006.257.09:28:55.65#ibcon#read 3, iclass 13, count 2 2006.257.09:28:55.65#ibcon#about to read 4, iclass 13, count 2 2006.257.09:28:55.65#ibcon#read 4, iclass 13, count 2 2006.257.09:28:55.65#ibcon#about to read 5, iclass 13, count 2 2006.257.09:28:55.65#ibcon#read 5, iclass 13, count 2 2006.257.09:28:55.65#ibcon#about to read 6, iclass 13, count 2 2006.257.09:28:55.65#ibcon#read 6, iclass 13, count 2 2006.257.09:28:55.65#ibcon#end of sib2, iclass 13, count 2 2006.257.09:28:55.65#ibcon#*mode == 0, iclass 13, count 2 2006.257.09:28:55.65#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.09:28:55.65#ibcon#[25=AT05-04\r\n] 2006.257.09:28:55.65#ibcon#*before write, iclass 13, count 2 2006.257.09:28:55.65#ibcon#enter sib2, iclass 13, count 2 2006.257.09:28:55.65#ibcon#flushed, iclass 13, count 2 2006.257.09:28:55.65#ibcon#about to write, iclass 13, count 2 2006.257.09:28:55.65#ibcon#wrote, iclass 13, count 2 2006.257.09:28:55.65#ibcon#about to read 3, iclass 13, count 2 2006.257.09:28:55.68#ibcon#read 3, iclass 13, count 2 2006.257.09:28:55.68#ibcon#about to read 4, iclass 13, count 2 2006.257.09:28:55.68#ibcon#read 4, iclass 13, count 2 2006.257.09:28:55.68#ibcon#about to read 5, iclass 13, count 2 2006.257.09:28:55.68#ibcon#read 5, iclass 13, count 2 2006.257.09:28:55.68#ibcon#about to read 6, iclass 13, count 2 2006.257.09:28:55.68#ibcon#read 6, iclass 13, count 2 2006.257.09:28:55.68#ibcon#end of sib2, iclass 13, count 2 2006.257.09:28:55.68#ibcon#*after write, iclass 13, count 2 2006.257.09:28:55.68#ibcon#*before return 0, iclass 13, count 2 2006.257.09:28:55.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:55.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:55.68#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.09:28:55.68#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:55.68#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:55.80#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:55.80#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:55.80#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:28:55.80#ibcon#first serial, iclass 13, count 0 2006.257.09:28:55.80#ibcon#enter sib2, iclass 13, count 0 2006.257.09:28:55.80#ibcon#flushed, iclass 13, count 0 2006.257.09:28:55.80#ibcon#about to write, iclass 13, count 0 2006.257.09:28:55.80#ibcon#wrote, iclass 13, count 0 2006.257.09:28:55.80#ibcon#about to read 3, iclass 13, count 0 2006.257.09:28:55.82#ibcon#read 3, iclass 13, count 0 2006.257.09:28:55.82#ibcon#about to read 4, iclass 13, count 0 2006.257.09:28:55.82#ibcon#read 4, iclass 13, count 0 2006.257.09:28:55.82#ibcon#about to read 5, iclass 13, count 0 2006.257.09:28:55.82#ibcon#read 5, iclass 13, count 0 2006.257.09:28:55.82#ibcon#about to read 6, iclass 13, count 0 2006.257.09:28:55.82#ibcon#read 6, iclass 13, count 0 2006.257.09:28:55.82#ibcon#end of sib2, iclass 13, count 0 2006.257.09:28:55.82#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:28:55.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:28:55.82#ibcon#[25=USB\r\n] 2006.257.09:28:55.82#ibcon#*before write, iclass 13, count 0 2006.257.09:28:55.82#ibcon#enter sib2, iclass 13, count 0 2006.257.09:28:55.82#ibcon#flushed, iclass 13, count 0 2006.257.09:28:55.82#ibcon#about to write, iclass 13, count 0 2006.257.09:28:55.82#ibcon#wrote, iclass 13, count 0 2006.257.09:28:55.82#ibcon#about to read 3, iclass 13, count 0 2006.257.09:28:55.85#ibcon#read 3, iclass 13, count 0 2006.257.09:28:55.85#ibcon#about to read 4, iclass 13, count 0 2006.257.09:28:55.85#ibcon#read 4, iclass 13, count 0 2006.257.09:28:55.85#ibcon#about to read 5, iclass 13, count 0 2006.257.09:28:55.85#ibcon#read 5, iclass 13, count 0 2006.257.09:28:55.85#ibcon#about to read 6, iclass 13, count 0 2006.257.09:28:55.85#ibcon#read 6, iclass 13, count 0 2006.257.09:28:55.85#ibcon#end of sib2, iclass 13, count 0 2006.257.09:28:55.85#ibcon#*after write, iclass 13, count 0 2006.257.09:28:55.85#ibcon#*before return 0, iclass 13, count 0 2006.257.09:28:55.85#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:55.85#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:55.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:28:55.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:28:55.85$vck44/valo=6,814.99 2006.257.09:28:55.85#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.09:28:55.85#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.09:28:55.85#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:55.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:55.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:55.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:55.85#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:28:55.85#ibcon#first serial, iclass 15, count 0 2006.257.09:28:55.85#ibcon#enter sib2, iclass 15, count 0 2006.257.09:28:55.85#ibcon#flushed, iclass 15, count 0 2006.257.09:28:55.85#ibcon#about to write, iclass 15, count 0 2006.257.09:28:55.85#ibcon#wrote, iclass 15, count 0 2006.257.09:28:55.85#ibcon#about to read 3, iclass 15, count 0 2006.257.09:28:55.87#ibcon#read 3, iclass 15, count 0 2006.257.09:28:55.87#ibcon#about to read 4, iclass 15, count 0 2006.257.09:28:55.87#ibcon#read 4, iclass 15, count 0 2006.257.09:28:55.87#ibcon#about to read 5, iclass 15, count 0 2006.257.09:28:55.87#ibcon#read 5, iclass 15, count 0 2006.257.09:28:55.87#ibcon#about to read 6, iclass 15, count 0 2006.257.09:28:55.87#ibcon#read 6, iclass 15, count 0 2006.257.09:28:55.87#ibcon#end of sib2, iclass 15, count 0 2006.257.09:28:55.87#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:28:55.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:28:55.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:28:55.87#ibcon#*before write, iclass 15, count 0 2006.257.09:28:55.87#ibcon#enter sib2, iclass 15, count 0 2006.257.09:28:55.87#ibcon#flushed, iclass 15, count 0 2006.257.09:28:55.87#ibcon#about to write, iclass 15, count 0 2006.257.09:28:55.87#ibcon#wrote, iclass 15, count 0 2006.257.09:28:55.87#ibcon#about to read 3, iclass 15, count 0 2006.257.09:28:55.91#ibcon#read 3, iclass 15, count 0 2006.257.09:28:55.91#ibcon#about to read 4, iclass 15, count 0 2006.257.09:28:55.91#ibcon#read 4, iclass 15, count 0 2006.257.09:28:55.91#ibcon#about to read 5, iclass 15, count 0 2006.257.09:28:55.91#ibcon#read 5, iclass 15, count 0 2006.257.09:28:55.91#ibcon#about to read 6, iclass 15, count 0 2006.257.09:28:55.91#ibcon#read 6, iclass 15, count 0 2006.257.09:28:55.91#ibcon#end of sib2, iclass 15, count 0 2006.257.09:28:55.91#ibcon#*after write, iclass 15, count 0 2006.257.09:28:55.91#ibcon#*before return 0, iclass 15, count 0 2006.257.09:28:55.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:55.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:55.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:28:55.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:28:55.91$vck44/va=6,4 2006.257.09:28:55.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.09:28:55.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.09:28:55.91#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:55.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:55.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:55.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:55.97#ibcon#enter wrdev, iclass 17, count 2 2006.257.09:28:55.97#ibcon#first serial, iclass 17, count 2 2006.257.09:28:55.97#ibcon#enter sib2, iclass 17, count 2 2006.257.09:28:55.97#ibcon#flushed, iclass 17, count 2 2006.257.09:28:55.97#ibcon#about to write, iclass 17, count 2 2006.257.09:28:55.97#ibcon#wrote, iclass 17, count 2 2006.257.09:28:55.97#ibcon#about to read 3, iclass 17, count 2 2006.257.09:28:55.99#ibcon#read 3, iclass 17, count 2 2006.257.09:28:55.99#ibcon#about to read 4, iclass 17, count 2 2006.257.09:28:55.99#ibcon#read 4, iclass 17, count 2 2006.257.09:28:55.99#ibcon#about to read 5, iclass 17, count 2 2006.257.09:28:55.99#ibcon#read 5, iclass 17, count 2 2006.257.09:28:55.99#ibcon#about to read 6, iclass 17, count 2 2006.257.09:28:55.99#ibcon#read 6, iclass 17, count 2 2006.257.09:28:55.99#ibcon#end of sib2, iclass 17, count 2 2006.257.09:28:55.99#ibcon#*mode == 0, iclass 17, count 2 2006.257.09:28:55.99#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.09:28:55.99#ibcon#[25=AT06-04\r\n] 2006.257.09:28:55.99#ibcon#*before write, iclass 17, count 2 2006.257.09:28:55.99#ibcon#enter sib2, iclass 17, count 2 2006.257.09:28:55.99#ibcon#flushed, iclass 17, count 2 2006.257.09:28:55.99#ibcon#about to write, iclass 17, count 2 2006.257.09:28:55.99#ibcon#wrote, iclass 17, count 2 2006.257.09:28:55.99#ibcon#about to read 3, iclass 17, count 2 2006.257.09:28:56.02#ibcon#read 3, iclass 17, count 2 2006.257.09:28:56.02#ibcon#about to read 4, iclass 17, count 2 2006.257.09:28:56.02#ibcon#read 4, iclass 17, count 2 2006.257.09:28:56.02#ibcon#about to read 5, iclass 17, count 2 2006.257.09:28:56.02#ibcon#read 5, iclass 17, count 2 2006.257.09:28:56.02#ibcon#about to read 6, iclass 17, count 2 2006.257.09:28:56.02#ibcon#read 6, iclass 17, count 2 2006.257.09:28:56.02#ibcon#end of sib2, iclass 17, count 2 2006.257.09:28:56.02#ibcon#*after write, iclass 17, count 2 2006.257.09:28:56.02#ibcon#*before return 0, iclass 17, count 2 2006.257.09:28:56.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:56.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:56.02#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.09:28:56.02#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:56.02#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:56.14#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:56.14#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:56.14#ibcon#enter wrdev, iclass 17, count 0 2006.257.09:28:56.14#ibcon#first serial, iclass 17, count 0 2006.257.09:28:56.14#ibcon#enter sib2, iclass 17, count 0 2006.257.09:28:56.14#ibcon#flushed, iclass 17, count 0 2006.257.09:28:56.14#ibcon#about to write, iclass 17, count 0 2006.257.09:28:56.14#ibcon#wrote, iclass 17, count 0 2006.257.09:28:56.14#ibcon#about to read 3, iclass 17, count 0 2006.257.09:28:56.16#ibcon#read 3, iclass 17, count 0 2006.257.09:28:56.16#ibcon#about to read 4, iclass 17, count 0 2006.257.09:28:56.16#ibcon#read 4, iclass 17, count 0 2006.257.09:28:56.16#ibcon#about to read 5, iclass 17, count 0 2006.257.09:28:56.16#ibcon#read 5, iclass 17, count 0 2006.257.09:28:56.16#ibcon#about to read 6, iclass 17, count 0 2006.257.09:28:56.16#ibcon#read 6, iclass 17, count 0 2006.257.09:28:56.16#ibcon#end of sib2, iclass 17, count 0 2006.257.09:28:56.16#ibcon#*mode == 0, iclass 17, count 0 2006.257.09:28:56.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.09:28:56.16#ibcon#[25=USB\r\n] 2006.257.09:28:56.16#ibcon#*before write, iclass 17, count 0 2006.257.09:28:56.16#ibcon#enter sib2, iclass 17, count 0 2006.257.09:28:56.16#ibcon#flushed, iclass 17, count 0 2006.257.09:28:56.16#ibcon#about to write, iclass 17, count 0 2006.257.09:28:56.16#ibcon#wrote, iclass 17, count 0 2006.257.09:28:56.16#ibcon#about to read 3, iclass 17, count 0 2006.257.09:28:56.19#ibcon#read 3, iclass 17, count 0 2006.257.09:28:56.19#ibcon#about to read 4, iclass 17, count 0 2006.257.09:28:56.19#ibcon#read 4, iclass 17, count 0 2006.257.09:28:56.19#ibcon#about to read 5, iclass 17, count 0 2006.257.09:28:56.19#ibcon#read 5, iclass 17, count 0 2006.257.09:28:56.19#ibcon#about to read 6, iclass 17, count 0 2006.257.09:28:56.19#ibcon#read 6, iclass 17, count 0 2006.257.09:28:56.19#ibcon#end of sib2, iclass 17, count 0 2006.257.09:28:56.19#ibcon#*after write, iclass 17, count 0 2006.257.09:28:56.19#ibcon#*before return 0, iclass 17, count 0 2006.257.09:28:56.19#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:56.19#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:56.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.09:28:56.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.09:28:56.19$vck44/valo=7,864.99 2006.257.09:28:56.19#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.09:28:56.19#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.09:28:56.19#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:56.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:28:56.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:28:56.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:28:56.19#ibcon#enter wrdev, iclass 19, count 0 2006.257.09:28:56.19#ibcon#first serial, iclass 19, count 0 2006.257.09:28:56.19#ibcon#enter sib2, iclass 19, count 0 2006.257.09:28:56.19#ibcon#flushed, iclass 19, count 0 2006.257.09:28:56.19#ibcon#about to write, iclass 19, count 0 2006.257.09:28:56.19#ibcon#wrote, iclass 19, count 0 2006.257.09:28:56.19#ibcon#about to read 3, iclass 19, count 0 2006.257.09:28:56.21#ibcon#read 3, iclass 19, count 0 2006.257.09:28:56.21#ibcon#about to read 4, iclass 19, count 0 2006.257.09:28:56.21#ibcon#read 4, iclass 19, count 0 2006.257.09:28:56.21#ibcon#about to read 5, iclass 19, count 0 2006.257.09:28:56.21#ibcon#read 5, iclass 19, count 0 2006.257.09:28:56.21#ibcon#about to read 6, iclass 19, count 0 2006.257.09:28:56.21#ibcon#read 6, iclass 19, count 0 2006.257.09:28:56.21#ibcon#end of sib2, iclass 19, count 0 2006.257.09:28:56.21#ibcon#*mode == 0, iclass 19, count 0 2006.257.09:28:56.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.09:28:56.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:28:56.21#ibcon#*before write, iclass 19, count 0 2006.257.09:28:56.21#ibcon#enter sib2, iclass 19, count 0 2006.257.09:28:56.21#ibcon#flushed, iclass 19, count 0 2006.257.09:28:56.21#ibcon#about to write, iclass 19, count 0 2006.257.09:28:56.21#ibcon#wrote, iclass 19, count 0 2006.257.09:28:56.21#ibcon#about to read 3, iclass 19, count 0 2006.257.09:28:56.25#ibcon#read 3, iclass 19, count 0 2006.257.09:28:56.25#ibcon#about to read 4, iclass 19, count 0 2006.257.09:28:56.25#ibcon#read 4, iclass 19, count 0 2006.257.09:28:56.25#ibcon#about to read 5, iclass 19, count 0 2006.257.09:28:56.25#ibcon#read 5, iclass 19, count 0 2006.257.09:28:56.25#ibcon#about to read 6, iclass 19, count 0 2006.257.09:28:56.25#ibcon#read 6, iclass 19, count 0 2006.257.09:28:56.25#ibcon#end of sib2, iclass 19, count 0 2006.257.09:28:56.25#ibcon#*after write, iclass 19, count 0 2006.257.09:28:56.25#ibcon#*before return 0, iclass 19, count 0 2006.257.09:28:56.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:28:56.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:28:56.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.09:28:56.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.09:28:56.25$vck44/va=7,4 2006.257.09:28:56.25#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.09:28:56.25#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.09:28:56.25#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:56.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:28:56.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:28:56.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:28:56.31#ibcon#enter wrdev, iclass 21, count 2 2006.257.09:28:56.31#ibcon#first serial, iclass 21, count 2 2006.257.09:28:56.31#ibcon#enter sib2, iclass 21, count 2 2006.257.09:28:56.31#ibcon#flushed, iclass 21, count 2 2006.257.09:28:56.31#ibcon#about to write, iclass 21, count 2 2006.257.09:28:56.31#ibcon#wrote, iclass 21, count 2 2006.257.09:28:56.31#ibcon#about to read 3, iclass 21, count 2 2006.257.09:28:56.33#ibcon#read 3, iclass 21, count 2 2006.257.09:28:56.33#ibcon#about to read 4, iclass 21, count 2 2006.257.09:28:56.33#ibcon#read 4, iclass 21, count 2 2006.257.09:28:56.33#ibcon#about to read 5, iclass 21, count 2 2006.257.09:28:56.33#ibcon#read 5, iclass 21, count 2 2006.257.09:28:56.33#ibcon#about to read 6, iclass 21, count 2 2006.257.09:28:56.33#ibcon#read 6, iclass 21, count 2 2006.257.09:28:56.33#ibcon#end of sib2, iclass 21, count 2 2006.257.09:28:56.33#ibcon#*mode == 0, iclass 21, count 2 2006.257.09:28:56.33#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.09:28:56.33#ibcon#[25=AT07-04\r\n] 2006.257.09:28:56.33#ibcon#*before write, iclass 21, count 2 2006.257.09:28:56.33#ibcon#enter sib2, iclass 21, count 2 2006.257.09:28:56.33#ibcon#flushed, iclass 21, count 2 2006.257.09:28:56.33#ibcon#about to write, iclass 21, count 2 2006.257.09:28:56.33#ibcon#wrote, iclass 21, count 2 2006.257.09:28:56.33#ibcon#about to read 3, iclass 21, count 2 2006.257.09:28:56.36#ibcon#read 3, iclass 21, count 2 2006.257.09:28:56.36#ibcon#about to read 4, iclass 21, count 2 2006.257.09:28:56.36#ibcon#read 4, iclass 21, count 2 2006.257.09:28:56.36#ibcon#about to read 5, iclass 21, count 2 2006.257.09:28:56.36#ibcon#read 5, iclass 21, count 2 2006.257.09:28:56.36#ibcon#about to read 6, iclass 21, count 2 2006.257.09:28:56.36#ibcon#read 6, iclass 21, count 2 2006.257.09:28:56.36#ibcon#end of sib2, iclass 21, count 2 2006.257.09:28:56.36#ibcon#*after write, iclass 21, count 2 2006.257.09:28:56.36#ibcon#*before return 0, iclass 21, count 2 2006.257.09:28:56.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:28:56.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:28:56.36#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.09:28:56.36#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:56.36#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:28:56.48#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:28:56.48#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:28:56.48#ibcon#enter wrdev, iclass 21, count 0 2006.257.09:28:56.48#ibcon#first serial, iclass 21, count 0 2006.257.09:28:56.48#ibcon#enter sib2, iclass 21, count 0 2006.257.09:28:56.48#ibcon#flushed, iclass 21, count 0 2006.257.09:28:56.48#ibcon#about to write, iclass 21, count 0 2006.257.09:28:56.48#ibcon#wrote, iclass 21, count 0 2006.257.09:28:56.48#ibcon#about to read 3, iclass 21, count 0 2006.257.09:28:56.50#ibcon#read 3, iclass 21, count 0 2006.257.09:28:56.50#ibcon#about to read 4, iclass 21, count 0 2006.257.09:28:56.50#ibcon#read 4, iclass 21, count 0 2006.257.09:28:56.50#ibcon#about to read 5, iclass 21, count 0 2006.257.09:28:56.50#ibcon#read 5, iclass 21, count 0 2006.257.09:28:56.50#ibcon#about to read 6, iclass 21, count 0 2006.257.09:28:56.50#ibcon#read 6, iclass 21, count 0 2006.257.09:28:56.50#ibcon#end of sib2, iclass 21, count 0 2006.257.09:28:56.50#ibcon#*mode == 0, iclass 21, count 0 2006.257.09:28:56.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.09:28:56.50#ibcon#[25=USB\r\n] 2006.257.09:28:56.50#ibcon#*before write, iclass 21, count 0 2006.257.09:28:56.50#ibcon#enter sib2, iclass 21, count 0 2006.257.09:28:56.50#ibcon#flushed, iclass 21, count 0 2006.257.09:28:56.50#ibcon#about to write, iclass 21, count 0 2006.257.09:28:56.50#ibcon#wrote, iclass 21, count 0 2006.257.09:28:56.50#ibcon#about to read 3, iclass 21, count 0 2006.257.09:28:56.53#ibcon#read 3, iclass 21, count 0 2006.257.09:28:56.53#ibcon#about to read 4, iclass 21, count 0 2006.257.09:28:56.53#ibcon#read 4, iclass 21, count 0 2006.257.09:28:56.53#ibcon#about to read 5, iclass 21, count 0 2006.257.09:28:56.53#ibcon#read 5, iclass 21, count 0 2006.257.09:28:56.53#ibcon#about to read 6, iclass 21, count 0 2006.257.09:28:56.53#ibcon#read 6, iclass 21, count 0 2006.257.09:28:56.53#ibcon#end of sib2, iclass 21, count 0 2006.257.09:28:56.53#ibcon#*after write, iclass 21, count 0 2006.257.09:28:56.53#ibcon#*before return 0, iclass 21, count 0 2006.257.09:28:56.53#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:28:56.53#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:28:56.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.09:28:56.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.09:28:56.53$vck44/valo=8,884.99 2006.257.09:28:56.53#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.09:28:56.53#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.09:28:56.53#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:56.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:56.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:56.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:56.53#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:28:56.53#ibcon#first serial, iclass 23, count 0 2006.257.09:28:56.53#ibcon#enter sib2, iclass 23, count 0 2006.257.09:28:56.53#ibcon#flushed, iclass 23, count 0 2006.257.09:28:56.53#ibcon#about to write, iclass 23, count 0 2006.257.09:28:56.53#ibcon#wrote, iclass 23, count 0 2006.257.09:28:56.53#ibcon#about to read 3, iclass 23, count 0 2006.257.09:28:56.55#ibcon#read 3, iclass 23, count 0 2006.257.09:28:56.55#ibcon#about to read 4, iclass 23, count 0 2006.257.09:28:56.55#ibcon#read 4, iclass 23, count 0 2006.257.09:28:56.55#ibcon#about to read 5, iclass 23, count 0 2006.257.09:28:56.55#ibcon#read 5, iclass 23, count 0 2006.257.09:28:56.55#ibcon#about to read 6, iclass 23, count 0 2006.257.09:28:56.55#ibcon#read 6, iclass 23, count 0 2006.257.09:28:56.55#ibcon#end of sib2, iclass 23, count 0 2006.257.09:28:56.55#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:28:56.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:28:56.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:28:56.55#ibcon#*before write, iclass 23, count 0 2006.257.09:28:56.55#ibcon#enter sib2, iclass 23, count 0 2006.257.09:28:56.55#ibcon#flushed, iclass 23, count 0 2006.257.09:28:56.55#ibcon#about to write, iclass 23, count 0 2006.257.09:28:56.55#ibcon#wrote, iclass 23, count 0 2006.257.09:28:56.55#ibcon#about to read 3, iclass 23, count 0 2006.257.09:28:56.59#ibcon#read 3, iclass 23, count 0 2006.257.09:28:56.59#ibcon#about to read 4, iclass 23, count 0 2006.257.09:28:56.59#ibcon#read 4, iclass 23, count 0 2006.257.09:28:56.59#ibcon#about to read 5, iclass 23, count 0 2006.257.09:28:56.59#ibcon#read 5, iclass 23, count 0 2006.257.09:28:56.59#ibcon#about to read 6, iclass 23, count 0 2006.257.09:28:56.59#ibcon#read 6, iclass 23, count 0 2006.257.09:28:56.59#ibcon#end of sib2, iclass 23, count 0 2006.257.09:28:56.59#ibcon#*after write, iclass 23, count 0 2006.257.09:28:56.59#ibcon#*before return 0, iclass 23, count 0 2006.257.09:28:56.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:56.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:56.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:28:56.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:28:56.59$vck44/va=8,4 2006.257.09:28:56.59#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.09:28:56.59#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.09:28:56.59#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:56.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:56.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:56.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:56.65#ibcon#enter wrdev, iclass 25, count 2 2006.257.09:28:56.65#ibcon#first serial, iclass 25, count 2 2006.257.09:28:56.65#ibcon#enter sib2, iclass 25, count 2 2006.257.09:28:56.65#ibcon#flushed, iclass 25, count 2 2006.257.09:28:56.65#ibcon#about to write, iclass 25, count 2 2006.257.09:28:56.65#ibcon#wrote, iclass 25, count 2 2006.257.09:28:56.65#ibcon#about to read 3, iclass 25, count 2 2006.257.09:28:56.67#ibcon#read 3, iclass 25, count 2 2006.257.09:28:56.67#ibcon#about to read 4, iclass 25, count 2 2006.257.09:28:56.67#ibcon#read 4, iclass 25, count 2 2006.257.09:28:56.67#ibcon#about to read 5, iclass 25, count 2 2006.257.09:28:56.67#ibcon#read 5, iclass 25, count 2 2006.257.09:28:56.67#ibcon#about to read 6, iclass 25, count 2 2006.257.09:28:56.67#ibcon#read 6, iclass 25, count 2 2006.257.09:28:56.67#ibcon#end of sib2, iclass 25, count 2 2006.257.09:28:56.67#ibcon#*mode == 0, iclass 25, count 2 2006.257.09:28:56.67#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.09:28:56.67#ibcon#[25=AT08-04\r\n] 2006.257.09:28:56.67#ibcon#*before write, iclass 25, count 2 2006.257.09:28:56.67#ibcon#enter sib2, iclass 25, count 2 2006.257.09:28:56.67#ibcon#flushed, iclass 25, count 2 2006.257.09:28:56.67#ibcon#about to write, iclass 25, count 2 2006.257.09:28:56.67#ibcon#wrote, iclass 25, count 2 2006.257.09:28:56.67#ibcon#about to read 3, iclass 25, count 2 2006.257.09:28:56.70#ibcon#read 3, iclass 25, count 2 2006.257.09:28:56.70#ibcon#about to read 4, iclass 25, count 2 2006.257.09:28:56.70#ibcon#read 4, iclass 25, count 2 2006.257.09:28:56.70#ibcon#about to read 5, iclass 25, count 2 2006.257.09:28:56.70#ibcon#read 5, iclass 25, count 2 2006.257.09:28:56.70#ibcon#about to read 6, iclass 25, count 2 2006.257.09:28:56.70#ibcon#read 6, iclass 25, count 2 2006.257.09:28:56.70#ibcon#end of sib2, iclass 25, count 2 2006.257.09:28:56.70#ibcon#*after write, iclass 25, count 2 2006.257.09:28:56.70#ibcon#*before return 0, iclass 25, count 2 2006.257.09:28:56.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:56.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:56.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.09:28:56.70#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:56.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:56.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:56.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:56.82#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:28:56.82#ibcon#first serial, iclass 25, count 0 2006.257.09:28:56.82#ibcon#enter sib2, iclass 25, count 0 2006.257.09:28:56.82#ibcon#flushed, iclass 25, count 0 2006.257.09:28:56.82#ibcon#about to write, iclass 25, count 0 2006.257.09:28:56.82#ibcon#wrote, iclass 25, count 0 2006.257.09:28:56.82#ibcon#about to read 3, iclass 25, count 0 2006.257.09:28:56.84#ibcon#read 3, iclass 25, count 0 2006.257.09:28:56.84#ibcon#about to read 4, iclass 25, count 0 2006.257.09:28:56.84#ibcon#read 4, iclass 25, count 0 2006.257.09:28:56.84#ibcon#about to read 5, iclass 25, count 0 2006.257.09:28:56.84#ibcon#read 5, iclass 25, count 0 2006.257.09:28:56.84#ibcon#about to read 6, iclass 25, count 0 2006.257.09:28:56.84#ibcon#read 6, iclass 25, count 0 2006.257.09:28:56.84#ibcon#end of sib2, iclass 25, count 0 2006.257.09:28:56.84#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:28:56.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:28:56.84#ibcon#[25=USB\r\n] 2006.257.09:28:56.84#ibcon#*before write, iclass 25, count 0 2006.257.09:28:56.84#ibcon#enter sib2, iclass 25, count 0 2006.257.09:28:56.84#ibcon#flushed, iclass 25, count 0 2006.257.09:28:56.84#ibcon#about to write, iclass 25, count 0 2006.257.09:28:56.84#ibcon#wrote, iclass 25, count 0 2006.257.09:28:56.84#ibcon#about to read 3, iclass 25, count 0 2006.257.09:28:56.87#ibcon#read 3, iclass 25, count 0 2006.257.09:28:56.87#ibcon#about to read 4, iclass 25, count 0 2006.257.09:28:56.87#ibcon#read 4, iclass 25, count 0 2006.257.09:28:56.87#ibcon#about to read 5, iclass 25, count 0 2006.257.09:28:56.87#ibcon#read 5, iclass 25, count 0 2006.257.09:28:56.87#ibcon#about to read 6, iclass 25, count 0 2006.257.09:28:56.87#ibcon#read 6, iclass 25, count 0 2006.257.09:28:56.87#ibcon#end of sib2, iclass 25, count 0 2006.257.09:28:56.87#ibcon#*after write, iclass 25, count 0 2006.257.09:28:56.87#ibcon#*before return 0, iclass 25, count 0 2006.257.09:28:56.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:56.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:56.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:28:56.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:28:56.87$vck44/vblo=1,629.99 2006.257.09:28:56.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.09:28:56.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.09:28:56.87#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:56.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:56.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:56.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:56.87#ibcon#enter wrdev, iclass 27, count 0 2006.257.09:28:56.87#ibcon#first serial, iclass 27, count 0 2006.257.09:28:56.87#ibcon#enter sib2, iclass 27, count 0 2006.257.09:28:56.87#ibcon#flushed, iclass 27, count 0 2006.257.09:28:56.87#ibcon#about to write, iclass 27, count 0 2006.257.09:28:56.87#ibcon#wrote, iclass 27, count 0 2006.257.09:28:56.87#ibcon#about to read 3, iclass 27, count 0 2006.257.09:28:56.89#ibcon#read 3, iclass 27, count 0 2006.257.09:28:56.89#ibcon#about to read 4, iclass 27, count 0 2006.257.09:28:56.89#ibcon#read 4, iclass 27, count 0 2006.257.09:28:56.89#ibcon#about to read 5, iclass 27, count 0 2006.257.09:28:56.89#ibcon#read 5, iclass 27, count 0 2006.257.09:28:56.89#ibcon#about to read 6, iclass 27, count 0 2006.257.09:28:56.89#ibcon#read 6, iclass 27, count 0 2006.257.09:28:56.89#ibcon#end of sib2, iclass 27, count 0 2006.257.09:28:56.89#ibcon#*mode == 0, iclass 27, count 0 2006.257.09:28:56.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.09:28:56.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:28:56.89#ibcon#*before write, iclass 27, count 0 2006.257.09:28:56.89#ibcon#enter sib2, iclass 27, count 0 2006.257.09:28:56.89#ibcon#flushed, iclass 27, count 0 2006.257.09:28:56.89#ibcon#about to write, iclass 27, count 0 2006.257.09:28:56.89#ibcon#wrote, iclass 27, count 0 2006.257.09:28:56.89#ibcon#about to read 3, iclass 27, count 0 2006.257.09:28:56.93#ibcon#read 3, iclass 27, count 0 2006.257.09:28:56.93#ibcon#about to read 4, iclass 27, count 0 2006.257.09:28:56.93#ibcon#read 4, iclass 27, count 0 2006.257.09:28:56.93#ibcon#about to read 5, iclass 27, count 0 2006.257.09:28:56.93#ibcon#read 5, iclass 27, count 0 2006.257.09:28:56.93#ibcon#about to read 6, iclass 27, count 0 2006.257.09:28:56.93#ibcon#read 6, iclass 27, count 0 2006.257.09:28:56.93#ibcon#end of sib2, iclass 27, count 0 2006.257.09:28:56.93#ibcon#*after write, iclass 27, count 0 2006.257.09:28:56.93#ibcon#*before return 0, iclass 27, count 0 2006.257.09:28:56.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:56.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:56.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.09:28:56.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.09:28:56.93$vck44/vb=1,4 2006.257.09:28:56.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.09:28:56.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.09:28:56.93#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:56.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:28:56.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:28:56.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:28:56.93#ibcon#enter wrdev, iclass 29, count 2 2006.257.09:28:56.93#ibcon#first serial, iclass 29, count 2 2006.257.09:28:56.93#ibcon#enter sib2, iclass 29, count 2 2006.257.09:28:56.93#ibcon#flushed, iclass 29, count 2 2006.257.09:28:56.93#ibcon#about to write, iclass 29, count 2 2006.257.09:28:56.93#ibcon#wrote, iclass 29, count 2 2006.257.09:28:56.93#ibcon#about to read 3, iclass 29, count 2 2006.257.09:28:56.95#ibcon#read 3, iclass 29, count 2 2006.257.09:28:56.95#ibcon#about to read 4, iclass 29, count 2 2006.257.09:28:56.95#ibcon#read 4, iclass 29, count 2 2006.257.09:28:56.95#ibcon#about to read 5, iclass 29, count 2 2006.257.09:28:56.95#ibcon#read 5, iclass 29, count 2 2006.257.09:28:56.95#ibcon#about to read 6, iclass 29, count 2 2006.257.09:28:56.95#ibcon#read 6, iclass 29, count 2 2006.257.09:28:56.95#ibcon#end of sib2, iclass 29, count 2 2006.257.09:28:56.95#ibcon#*mode == 0, iclass 29, count 2 2006.257.09:28:56.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.09:28:56.95#ibcon#[27=AT01-04\r\n] 2006.257.09:28:56.95#ibcon#*before write, iclass 29, count 2 2006.257.09:28:56.95#ibcon#enter sib2, iclass 29, count 2 2006.257.09:28:56.95#ibcon#flushed, iclass 29, count 2 2006.257.09:28:56.95#ibcon#about to write, iclass 29, count 2 2006.257.09:28:56.95#ibcon#wrote, iclass 29, count 2 2006.257.09:28:56.95#ibcon#about to read 3, iclass 29, count 2 2006.257.09:28:56.98#ibcon#read 3, iclass 29, count 2 2006.257.09:28:56.98#ibcon#about to read 4, iclass 29, count 2 2006.257.09:28:56.98#ibcon#read 4, iclass 29, count 2 2006.257.09:28:56.98#ibcon#about to read 5, iclass 29, count 2 2006.257.09:28:56.98#ibcon#read 5, iclass 29, count 2 2006.257.09:28:56.98#ibcon#about to read 6, iclass 29, count 2 2006.257.09:28:56.98#ibcon#read 6, iclass 29, count 2 2006.257.09:28:56.98#ibcon#end of sib2, iclass 29, count 2 2006.257.09:28:56.98#ibcon#*after write, iclass 29, count 2 2006.257.09:28:56.98#ibcon#*before return 0, iclass 29, count 2 2006.257.09:28:56.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:28:56.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:28:56.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.09:28:56.98#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:56.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:28:57.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:28:57.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:28:57.10#ibcon#enter wrdev, iclass 29, count 0 2006.257.09:28:57.10#ibcon#first serial, iclass 29, count 0 2006.257.09:28:57.10#ibcon#enter sib2, iclass 29, count 0 2006.257.09:28:57.10#ibcon#flushed, iclass 29, count 0 2006.257.09:28:57.10#ibcon#about to write, iclass 29, count 0 2006.257.09:28:57.10#ibcon#wrote, iclass 29, count 0 2006.257.09:28:57.10#ibcon#about to read 3, iclass 29, count 0 2006.257.09:28:57.12#ibcon#read 3, iclass 29, count 0 2006.257.09:28:57.12#ibcon#about to read 4, iclass 29, count 0 2006.257.09:28:57.12#ibcon#read 4, iclass 29, count 0 2006.257.09:28:57.12#ibcon#about to read 5, iclass 29, count 0 2006.257.09:28:57.12#ibcon#read 5, iclass 29, count 0 2006.257.09:28:57.12#ibcon#about to read 6, iclass 29, count 0 2006.257.09:28:57.12#ibcon#read 6, iclass 29, count 0 2006.257.09:28:57.12#ibcon#end of sib2, iclass 29, count 0 2006.257.09:28:57.12#ibcon#*mode == 0, iclass 29, count 0 2006.257.09:28:57.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.09:28:57.12#ibcon#[27=USB\r\n] 2006.257.09:28:57.12#ibcon#*before write, iclass 29, count 0 2006.257.09:28:57.12#ibcon#enter sib2, iclass 29, count 0 2006.257.09:28:57.12#ibcon#flushed, iclass 29, count 0 2006.257.09:28:57.12#ibcon#about to write, iclass 29, count 0 2006.257.09:28:57.12#ibcon#wrote, iclass 29, count 0 2006.257.09:28:57.12#ibcon#about to read 3, iclass 29, count 0 2006.257.09:28:57.15#ibcon#read 3, iclass 29, count 0 2006.257.09:28:57.15#ibcon#about to read 4, iclass 29, count 0 2006.257.09:28:57.15#ibcon#read 4, iclass 29, count 0 2006.257.09:28:57.15#ibcon#about to read 5, iclass 29, count 0 2006.257.09:28:57.15#ibcon#read 5, iclass 29, count 0 2006.257.09:28:57.15#ibcon#about to read 6, iclass 29, count 0 2006.257.09:28:57.15#ibcon#read 6, iclass 29, count 0 2006.257.09:28:57.15#ibcon#end of sib2, iclass 29, count 0 2006.257.09:28:57.15#ibcon#*after write, iclass 29, count 0 2006.257.09:28:57.15#ibcon#*before return 0, iclass 29, count 0 2006.257.09:28:57.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:28:57.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:28:57.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.09:28:57.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.09:28:57.15$vck44/vblo=2,634.99 2006.257.09:28:57.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.09:28:57.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.09:28:57.15#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:57.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:57.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:57.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:57.15#ibcon#enter wrdev, iclass 31, count 0 2006.257.09:28:57.15#ibcon#first serial, iclass 31, count 0 2006.257.09:28:57.15#ibcon#enter sib2, iclass 31, count 0 2006.257.09:28:57.15#ibcon#flushed, iclass 31, count 0 2006.257.09:28:57.15#ibcon#about to write, iclass 31, count 0 2006.257.09:28:57.15#ibcon#wrote, iclass 31, count 0 2006.257.09:28:57.15#ibcon#about to read 3, iclass 31, count 0 2006.257.09:28:57.17#ibcon#read 3, iclass 31, count 0 2006.257.09:28:57.17#ibcon#about to read 4, iclass 31, count 0 2006.257.09:28:57.17#ibcon#read 4, iclass 31, count 0 2006.257.09:28:57.17#ibcon#about to read 5, iclass 31, count 0 2006.257.09:28:57.17#ibcon#read 5, iclass 31, count 0 2006.257.09:28:57.17#ibcon#about to read 6, iclass 31, count 0 2006.257.09:28:57.17#ibcon#read 6, iclass 31, count 0 2006.257.09:28:57.17#ibcon#end of sib2, iclass 31, count 0 2006.257.09:28:57.17#ibcon#*mode == 0, iclass 31, count 0 2006.257.09:28:57.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.09:28:57.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:28:57.17#ibcon#*before write, iclass 31, count 0 2006.257.09:28:57.17#ibcon#enter sib2, iclass 31, count 0 2006.257.09:28:57.17#ibcon#flushed, iclass 31, count 0 2006.257.09:28:57.17#ibcon#about to write, iclass 31, count 0 2006.257.09:28:57.17#ibcon#wrote, iclass 31, count 0 2006.257.09:28:57.17#ibcon#about to read 3, iclass 31, count 0 2006.257.09:28:57.21#ibcon#read 3, iclass 31, count 0 2006.257.09:28:57.21#ibcon#about to read 4, iclass 31, count 0 2006.257.09:28:57.21#ibcon#read 4, iclass 31, count 0 2006.257.09:28:57.21#ibcon#about to read 5, iclass 31, count 0 2006.257.09:28:57.21#ibcon#read 5, iclass 31, count 0 2006.257.09:28:57.21#ibcon#about to read 6, iclass 31, count 0 2006.257.09:28:57.21#ibcon#read 6, iclass 31, count 0 2006.257.09:28:57.21#ibcon#end of sib2, iclass 31, count 0 2006.257.09:28:57.21#ibcon#*after write, iclass 31, count 0 2006.257.09:28:57.21#ibcon#*before return 0, iclass 31, count 0 2006.257.09:28:57.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:57.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:28:57.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.09:28:57.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.09:28:57.21$vck44/vb=2,5 2006.257.09:28:57.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.09:28:57.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.09:28:57.21#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:57.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:57.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:57.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:57.27#ibcon#enter wrdev, iclass 33, count 2 2006.257.09:28:57.27#ibcon#first serial, iclass 33, count 2 2006.257.09:28:57.27#ibcon#enter sib2, iclass 33, count 2 2006.257.09:28:57.27#ibcon#flushed, iclass 33, count 2 2006.257.09:28:57.27#ibcon#about to write, iclass 33, count 2 2006.257.09:28:57.27#ibcon#wrote, iclass 33, count 2 2006.257.09:28:57.27#ibcon#about to read 3, iclass 33, count 2 2006.257.09:28:57.29#ibcon#read 3, iclass 33, count 2 2006.257.09:28:57.29#ibcon#about to read 4, iclass 33, count 2 2006.257.09:28:57.29#ibcon#read 4, iclass 33, count 2 2006.257.09:28:57.29#ibcon#about to read 5, iclass 33, count 2 2006.257.09:28:57.29#ibcon#read 5, iclass 33, count 2 2006.257.09:28:57.29#ibcon#about to read 6, iclass 33, count 2 2006.257.09:28:57.29#ibcon#read 6, iclass 33, count 2 2006.257.09:28:57.29#ibcon#end of sib2, iclass 33, count 2 2006.257.09:28:57.29#ibcon#*mode == 0, iclass 33, count 2 2006.257.09:28:57.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.09:28:57.29#ibcon#[27=AT02-05\r\n] 2006.257.09:28:57.29#ibcon#*before write, iclass 33, count 2 2006.257.09:28:57.29#ibcon#enter sib2, iclass 33, count 2 2006.257.09:28:57.29#ibcon#flushed, iclass 33, count 2 2006.257.09:28:57.29#ibcon#about to write, iclass 33, count 2 2006.257.09:28:57.30#ibcon#wrote, iclass 33, count 2 2006.257.09:28:57.30#ibcon#about to read 3, iclass 33, count 2 2006.257.09:28:57.33#ibcon#read 3, iclass 33, count 2 2006.257.09:28:57.33#ibcon#about to read 4, iclass 33, count 2 2006.257.09:28:57.33#ibcon#read 4, iclass 33, count 2 2006.257.09:28:57.33#ibcon#about to read 5, iclass 33, count 2 2006.257.09:28:57.33#ibcon#read 5, iclass 33, count 2 2006.257.09:28:57.33#ibcon#about to read 6, iclass 33, count 2 2006.257.09:28:57.33#ibcon#read 6, iclass 33, count 2 2006.257.09:28:57.33#ibcon#end of sib2, iclass 33, count 2 2006.257.09:28:57.33#ibcon#*after write, iclass 33, count 2 2006.257.09:28:57.33#ibcon#*before return 0, iclass 33, count 2 2006.257.09:28:57.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:57.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:28:57.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.09:28:57.33#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:57.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:57.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:57.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:57.45#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:28:57.45#ibcon#first serial, iclass 33, count 0 2006.257.09:28:57.45#ibcon#enter sib2, iclass 33, count 0 2006.257.09:28:57.45#ibcon#flushed, iclass 33, count 0 2006.257.09:28:57.45#ibcon#about to write, iclass 33, count 0 2006.257.09:28:57.45#ibcon#wrote, iclass 33, count 0 2006.257.09:28:57.45#ibcon#about to read 3, iclass 33, count 0 2006.257.09:28:57.47#ibcon#read 3, iclass 33, count 0 2006.257.09:28:57.47#ibcon#about to read 4, iclass 33, count 0 2006.257.09:28:57.47#ibcon#read 4, iclass 33, count 0 2006.257.09:28:57.47#ibcon#about to read 5, iclass 33, count 0 2006.257.09:28:57.47#ibcon#read 5, iclass 33, count 0 2006.257.09:28:57.47#ibcon#about to read 6, iclass 33, count 0 2006.257.09:28:57.47#ibcon#read 6, iclass 33, count 0 2006.257.09:28:57.47#ibcon#end of sib2, iclass 33, count 0 2006.257.09:28:57.47#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:28:57.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:28:57.47#ibcon#[27=USB\r\n] 2006.257.09:28:57.47#ibcon#*before write, iclass 33, count 0 2006.257.09:28:57.47#ibcon#enter sib2, iclass 33, count 0 2006.257.09:28:57.47#ibcon#flushed, iclass 33, count 0 2006.257.09:28:57.47#ibcon#about to write, iclass 33, count 0 2006.257.09:28:57.47#ibcon#wrote, iclass 33, count 0 2006.257.09:28:57.47#ibcon#about to read 3, iclass 33, count 0 2006.257.09:28:57.50#ibcon#read 3, iclass 33, count 0 2006.257.09:28:57.50#ibcon#about to read 4, iclass 33, count 0 2006.257.09:28:57.50#ibcon#read 4, iclass 33, count 0 2006.257.09:28:57.50#ibcon#about to read 5, iclass 33, count 0 2006.257.09:28:57.50#ibcon#read 5, iclass 33, count 0 2006.257.09:28:57.50#ibcon#about to read 6, iclass 33, count 0 2006.257.09:28:57.50#ibcon#read 6, iclass 33, count 0 2006.257.09:28:57.50#ibcon#end of sib2, iclass 33, count 0 2006.257.09:28:57.50#ibcon#*after write, iclass 33, count 0 2006.257.09:28:57.50#ibcon#*before return 0, iclass 33, count 0 2006.257.09:28:57.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:57.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:28:57.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:28:57.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:28:57.50$vck44/vblo=3,649.99 2006.257.09:28:57.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.09:28:57.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.09:28:57.50#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:57.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:57.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:57.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:57.50#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:28:57.50#ibcon#first serial, iclass 35, count 0 2006.257.09:28:57.50#ibcon#enter sib2, iclass 35, count 0 2006.257.09:28:57.50#ibcon#flushed, iclass 35, count 0 2006.257.09:28:57.50#ibcon#about to write, iclass 35, count 0 2006.257.09:28:57.50#ibcon#wrote, iclass 35, count 0 2006.257.09:28:57.50#ibcon#about to read 3, iclass 35, count 0 2006.257.09:28:57.52#ibcon#read 3, iclass 35, count 0 2006.257.09:28:57.52#ibcon#about to read 4, iclass 35, count 0 2006.257.09:28:57.52#ibcon#read 4, iclass 35, count 0 2006.257.09:28:57.52#ibcon#about to read 5, iclass 35, count 0 2006.257.09:28:57.52#ibcon#read 5, iclass 35, count 0 2006.257.09:28:57.52#ibcon#about to read 6, iclass 35, count 0 2006.257.09:28:57.52#ibcon#read 6, iclass 35, count 0 2006.257.09:28:57.52#ibcon#end of sib2, iclass 35, count 0 2006.257.09:28:57.52#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:28:57.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:28:57.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:28:57.52#ibcon#*before write, iclass 35, count 0 2006.257.09:28:57.52#ibcon#enter sib2, iclass 35, count 0 2006.257.09:28:57.52#ibcon#flushed, iclass 35, count 0 2006.257.09:28:57.52#ibcon#about to write, iclass 35, count 0 2006.257.09:28:57.52#ibcon#wrote, iclass 35, count 0 2006.257.09:28:57.52#ibcon#about to read 3, iclass 35, count 0 2006.257.09:28:57.56#ibcon#read 3, iclass 35, count 0 2006.257.09:28:57.56#ibcon#about to read 4, iclass 35, count 0 2006.257.09:28:57.56#ibcon#read 4, iclass 35, count 0 2006.257.09:28:57.56#ibcon#about to read 5, iclass 35, count 0 2006.257.09:28:57.56#ibcon#read 5, iclass 35, count 0 2006.257.09:28:57.56#ibcon#about to read 6, iclass 35, count 0 2006.257.09:28:57.56#ibcon#read 6, iclass 35, count 0 2006.257.09:28:57.56#ibcon#end of sib2, iclass 35, count 0 2006.257.09:28:57.56#ibcon#*after write, iclass 35, count 0 2006.257.09:28:57.56#ibcon#*before return 0, iclass 35, count 0 2006.257.09:28:57.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:57.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:28:57.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:28:57.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:28:57.56$vck44/vb=3,4 2006.257.09:28:57.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.09:28:57.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.09:28:57.56#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:57.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:57.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:57.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:57.62#ibcon#enter wrdev, iclass 37, count 2 2006.257.09:28:57.62#ibcon#first serial, iclass 37, count 2 2006.257.09:28:57.62#ibcon#enter sib2, iclass 37, count 2 2006.257.09:28:57.62#ibcon#flushed, iclass 37, count 2 2006.257.09:28:57.62#ibcon#about to write, iclass 37, count 2 2006.257.09:28:57.62#ibcon#wrote, iclass 37, count 2 2006.257.09:28:57.62#ibcon#about to read 3, iclass 37, count 2 2006.257.09:28:57.64#ibcon#read 3, iclass 37, count 2 2006.257.09:28:57.64#ibcon#about to read 4, iclass 37, count 2 2006.257.09:28:57.64#ibcon#read 4, iclass 37, count 2 2006.257.09:28:57.64#ibcon#about to read 5, iclass 37, count 2 2006.257.09:28:57.64#ibcon#read 5, iclass 37, count 2 2006.257.09:28:57.64#ibcon#about to read 6, iclass 37, count 2 2006.257.09:28:57.64#ibcon#read 6, iclass 37, count 2 2006.257.09:28:57.64#ibcon#end of sib2, iclass 37, count 2 2006.257.09:28:57.64#ibcon#*mode == 0, iclass 37, count 2 2006.257.09:28:57.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.09:28:57.64#ibcon#[27=AT03-04\r\n] 2006.257.09:28:57.64#ibcon#*before write, iclass 37, count 2 2006.257.09:28:57.64#ibcon#enter sib2, iclass 37, count 2 2006.257.09:28:57.64#ibcon#flushed, iclass 37, count 2 2006.257.09:28:57.64#ibcon#about to write, iclass 37, count 2 2006.257.09:28:57.64#ibcon#wrote, iclass 37, count 2 2006.257.09:28:57.64#ibcon#about to read 3, iclass 37, count 2 2006.257.09:28:57.67#ibcon#read 3, iclass 37, count 2 2006.257.09:28:57.67#ibcon#about to read 4, iclass 37, count 2 2006.257.09:28:57.67#ibcon#read 4, iclass 37, count 2 2006.257.09:28:57.67#ibcon#about to read 5, iclass 37, count 2 2006.257.09:28:57.67#ibcon#read 5, iclass 37, count 2 2006.257.09:28:57.67#ibcon#about to read 6, iclass 37, count 2 2006.257.09:28:57.67#ibcon#read 6, iclass 37, count 2 2006.257.09:28:57.67#ibcon#end of sib2, iclass 37, count 2 2006.257.09:28:57.67#ibcon#*after write, iclass 37, count 2 2006.257.09:28:57.67#ibcon#*before return 0, iclass 37, count 2 2006.257.09:28:57.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:57.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:28:57.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.09:28:57.67#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:57.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:57.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:57.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:57.79#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:28:57.79#ibcon#first serial, iclass 37, count 0 2006.257.09:28:57.79#ibcon#enter sib2, iclass 37, count 0 2006.257.09:28:57.79#ibcon#flushed, iclass 37, count 0 2006.257.09:28:57.79#ibcon#about to write, iclass 37, count 0 2006.257.09:28:57.79#ibcon#wrote, iclass 37, count 0 2006.257.09:28:57.79#ibcon#about to read 3, iclass 37, count 0 2006.257.09:28:57.81#ibcon#read 3, iclass 37, count 0 2006.257.09:28:57.81#ibcon#about to read 4, iclass 37, count 0 2006.257.09:28:57.81#ibcon#read 4, iclass 37, count 0 2006.257.09:28:57.81#ibcon#about to read 5, iclass 37, count 0 2006.257.09:28:57.81#ibcon#read 5, iclass 37, count 0 2006.257.09:28:57.81#ibcon#about to read 6, iclass 37, count 0 2006.257.09:28:57.81#ibcon#read 6, iclass 37, count 0 2006.257.09:28:57.81#ibcon#end of sib2, iclass 37, count 0 2006.257.09:28:57.81#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:28:57.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:28:57.81#ibcon#[27=USB\r\n] 2006.257.09:28:57.81#ibcon#*before write, iclass 37, count 0 2006.257.09:28:57.81#ibcon#enter sib2, iclass 37, count 0 2006.257.09:28:57.81#ibcon#flushed, iclass 37, count 0 2006.257.09:28:57.81#ibcon#about to write, iclass 37, count 0 2006.257.09:28:57.81#ibcon#wrote, iclass 37, count 0 2006.257.09:28:57.81#ibcon#about to read 3, iclass 37, count 0 2006.257.09:28:57.84#ibcon#read 3, iclass 37, count 0 2006.257.09:28:57.84#ibcon#about to read 4, iclass 37, count 0 2006.257.09:28:57.84#ibcon#read 4, iclass 37, count 0 2006.257.09:28:57.84#ibcon#about to read 5, iclass 37, count 0 2006.257.09:28:57.84#ibcon#read 5, iclass 37, count 0 2006.257.09:28:57.84#ibcon#about to read 6, iclass 37, count 0 2006.257.09:28:57.84#ibcon#read 6, iclass 37, count 0 2006.257.09:28:57.84#ibcon#end of sib2, iclass 37, count 0 2006.257.09:28:57.84#ibcon#*after write, iclass 37, count 0 2006.257.09:28:57.84#ibcon#*before return 0, iclass 37, count 0 2006.257.09:28:57.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:57.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:28:57.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:28:57.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:28:57.84$vck44/vblo=4,679.99 2006.257.09:28:57.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.09:28:57.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.09:28:57.84#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:57.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:57.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:57.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:57.84#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:28:57.84#ibcon#first serial, iclass 39, count 0 2006.257.09:28:57.84#ibcon#enter sib2, iclass 39, count 0 2006.257.09:28:57.84#ibcon#flushed, iclass 39, count 0 2006.257.09:28:57.84#ibcon#about to write, iclass 39, count 0 2006.257.09:28:57.84#ibcon#wrote, iclass 39, count 0 2006.257.09:28:57.84#ibcon#about to read 3, iclass 39, count 0 2006.257.09:28:57.86#ibcon#read 3, iclass 39, count 0 2006.257.09:28:57.86#ibcon#about to read 4, iclass 39, count 0 2006.257.09:28:57.86#ibcon#read 4, iclass 39, count 0 2006.257.09:28:57.86#ibcon#about to read 5, iclass 39, count 0 2006.257.09:28:57.86#ibcon#read 5, iclass 39, count 0 2006.257.09:28:57.86#ibcon#about to read 6, iclass 39, count 0 2006.257.09:28:57.86#ibcon#read 6, iclass 39, count 0 2006.257.09:28:57.86#ibcon#end of sib2, iclass 39, count 0 2006.257.09:28:57.86#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:28:57.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:28:57.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:28:57.86#ibcon#*before write, iclass 39, count 0 2006.257.09:28:57.86#ibcon#enter sib2, iclass 39, count 0 2006.257.09:28:57.86#ibcon#flushed, iclass 39, count 0 2006.257.09:28:57.86#ibcon#about to write, iclass 39, count 0 2006.257.09:28:57.86#ibcon#wrote, iclass 39, count 0 2006.257.09:28:57.86#ibcon#about to read 3, iclass 39, count 0 2006.257.09:28:57.90#ibcon#read 3, iclass 39, count 0 2006.257.09:28:57.90#ibcon#about to read 4, iclass 39, count 0 2006.257.09:28:57.90#ibcon#read 4, iclass 39, count 0 2006.257.09:28:57.90#ibcon#about to read 5, iclass 39, count 0 2006.257.09:28:57.90#ibcon#read 5, iclass 39, count 0 2006.257.09:28:57.90#ibcon#about to read 6, iclass 39, count 0 2006.257.09:28:57.90#ibcon#read 6, iclass 39, count 0 2006.257.09:28:57.90#ibcon#end of sib2, iclass 39, count 0 2006.257.09:28:57.90#ibcon#*after write, iclass 39, count 0 2006.257.09:28:57.90#ibcon#*before return 0, iclass 39, count 0 2006.257.09:28:57.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:57.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:28:57.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:28:57.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:28:57.90$vck44/vb=4,5 2006.257.09:28:57.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.09:28:57.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.09:28:57.90#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:57.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:57.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:57.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:57.96#ibcon#enter wrdev, iclass 3, count 2 2006.257.09:28:57.96#ibcon#first serial, iclass 3, count 2 2006.257.09:28:57.96#ibcon#enter sib2, iclass 3, count 2 2006.257.09:28:57.96#ibcon#flushed, iclass 3, count 2 2006.257.09:28:57.96#ibcon#about to write, iclass 3, count 2 2006.257.09:28:57.96#ibcon#wrote, iclass 3, count 2 2006.257.09:28:57.96#ibcon#about to read 3, iclass 3, count 2 2006.257.09:28:57.98#ibcon#read 3, iclass 3, count 2 2006.257.09:28:57.98#ibcon#about to read 4, iclass 3, count 2 2006.257.09:28:57.98#ibcon#read 4, iclass 3, count 2 2006.257.09:28:57.98#ibcon#about to read 5, iclass 3, count 2 2006.257.09:28:57.98#ibcon#read 5, iclass 3, count 2 2006.257.09:28:57.98#ibcon#about to read 6, iclass 3, count 2 2006.257.09:28:57.98#ibcon#read 6, iclass 3, count 2 2006.257.09:28:57.98#ibcon#end of sib2, iclass 3, count 2 2006.257.09:28:57.98#ibcon#*mode == 0, iclass 3, count 2 2006.257.09:28:57.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.09:28:57.98#ibcon#[27=AT04-05\r\n] 2006.257.09:28:57.98#ibcon#*before write, iclass 3, count 2 2006.257.09:28:57.98#ibcon#enter sib2, iclass 3, count 2 2006.257.09:28:57.98#ibcon#flushed, iclass 3, count 2 2006.257.09:28:57.98#ibcon#about to write, iclass 3, count 2 2006.257.09:28:57.98#ibcon#wrote, iclass 3, count 2 2006.257.09:28:57.98#ibcon#about to read 3, iclass 3, count 2 2006.257.09:28:58.01#ibcon#read 3, iclass 3, count 2 2006.257.09:28:58.01#ibcon#about to read 4, iclass 3, count 2 2006.257.09:28:58.01#ibcon#read 4, iclass 3, count 2 2006.257.09:28:58.01#ibcon#about to read 5, iclass 3, count 2 2006.257.09:28:58.01#ibcon#read 5, iclass 3, count 2 2006.257.09:28:58.01#ibcon#about to read 6, iclass 3, count 2 2006.257.09:28:58.01#ibcon#read 6, iclass 3, count 2 2006.257.09:28:58.01#ibcon#end of sib2, iclass 3, count 2 2006.257.09:28:58.01#ibcon#*after write, iclass 3, count 2 2006.257.09:28:58.01#ibcon#*before return 0, iclass 3, count 2 2006.257.09:28:58.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:58.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:28:58.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.09:28:58.01#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:58.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:58.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:58.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:58.13#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:28:58.13#ibcon#first serial, iclass 3, count 0 2006.257.09:28:58.13#ibcon#enter sib2, iclass 3, count 0 2006.257.09:28:58.13#ibcon#flushed, iclass 3, count 0 2006.257.09:28:58.13#ibcon#about to write, iclass 3, count 0 2006.257.09:28:58.13#ibcon#wrote, iclass 3, count 0 2006.257.09:28:58.13#ibcon#about to read 3, iclass 3, count 0 2006.257.09:28:58.15#ibcon#read 3, iclass 3, count 0 2006.257.09:28:58.15#ibcon#about to read 4, iclass 3, count 0 2006.257.09:28:58.15#ibcon#read 4, iclass 3, count 0 2006.257.09:28:58.15#ibcon#about to read 5, iclass 3, count 0 2006.257.09:28:58.15#ibcon#read 5, iclass 3, count 0 2006.257.09:28:58.15#ibcon#about to read 6, iclass 3, count 0 2006.257.09:28:58.15#ibcon#read 6, iclass 3, count 0 2006.257.09:28:58.15#ibcon#end of sib2, iclass 3, count 0 2006.257.09:28:58.15#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:28:58.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:28:58.15#ibcon#[27=USB\r\n] 2006.257.09:28:58.15#ibcon#*before write, iclass 3, count 0 2006.257.09:28:58.15#ibcon#enter sib2, iclass 3, count 0 2006.257.09:28:58.15#ibcon#flushed, iclass 3, count 0 2006.257.09:28:58.15#ibcon#about to write, iclass 3, count 0 2006.257.09:28:58.15#ibcon#wrote, iclass 3, count 0 2006.257.09:28:58.15#ibcon#about to read 3, iclass 3, count 0 2006.257.09:28:58.18#ibcon#read 3, iclass 3, count 0 2006.257.09:28:58.18#ibcon#about to read 4, iclass 3, count 0 2006.257.09:28:58.18#ibcon#read 4, iclass 3, count 0 2006.257.09:28:58.18#ibcon#about to read 5, iclass 3, count 0 2006.257.09:28:58.18#ibcon#read 5, iclass 3, count 0 2006.257.09:28:58.18#ibcon#about to read 6, iclass 3, count 0 2006.257.09:28:58.18#ibcon#read 6, iclass 3, count 0 2006.257.09:28:58.18#ibcon#end of sib2, iclass 3, count 0 2006.257.09:28:58.18#ibcon#*after write, iclass 3, count 0 2006.257.09:28:58.18#ibcon#*before return 0, iclass 3, count 0 2006.257.09:28:58.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:58.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:28:58.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:28:58.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:28:58.18$vck44/vblo=5,709.99 2006.257.09:28:58.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.09:28:58.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.09:28:58.18#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:58.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:58.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:58.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:58.18#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:28:58.18#ibcon#first serial, iclass 5, count 0 2006.257.09:28:58.18#ibcon#enter sib2, iclass 5, count 0 2006.257.09:28:58.18#ibcon#flushed, iclass 5, count 0 2006.257.09:28:58.18#ibcon#about to write, iclass 5, count 0 2006.257.09:28:58.18#ibcon#wrote, iclass 5, count 0 2006.257.09:28:58.18#ibcon#about to read 3, iclass 5, count 0 2006.257.09:28:58.20#ibcon#read 3, iclass 5, count 0 2006.257.09:28:58.20#ibcon#about to read 4, iclass 5, count 0 2006.257.09:28:58.20#ibcon#read 4, iclass 5, count 0 2006.257.09:28:58.20#ibcon#about to read 5, iclass 5, count 0 2006.257.09:28:58.20#ibcon#read 5, iclass 5, count 0 2006.257.09:28:58.20#ibcon#about to read 6, iclass 5, count 0 2006.257.09:28:58.20#ibcon#read 6, iclass 5, count 0 2006.257.09:28:58.20#ibcon#end of sib2, iclass 5, count 0 2006.257.09:28:58.20#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:28:58.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:28:58.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:28:58.20#ibcon#*before write, iclass 5, count 0 2006.257.09:28:58.20#ibcon#enter sib2, iclass 5, count 0 2006.257.09:28:58.20#ibcon#flushed, iclass 5, count 0 2006.257.09:28:58.20#ibcon#about to write, iclass 5, count 0 2006.257.09:28:58.20#ibcon#wrote, iclass 5, count 0 2006.257.09:28:58.20#ibcon#about to read 3, iclass 5, count 0 2006.257.09:28:58.24#ibcon#read 3, iclass 5, count 0 2006.257.09:28:58.24#ibcon#about to read 4, iclass 5, count 0 2006.257.09:28:58.24#ibcon#read 4, iclass 5, count 0 2006.257.09:28:58.24#ibcon#about to read 5, iclass 5, count 0 2006.257.09:28:58.24#ibcon#read 5, iclass 5, count 0 2006.257.09:28:58.24#ibcon#about to read 6, iclass 5, count 0 2006.257.09:28:58.24#ibcon#read 6, iclass 5, count 0 2006.257.09:28:58.24#ibcon#end of sib2, iclass 5, count 0 2006.257.09:28:58.24#ibcon#*after write, iclass 5, count 0 2006.257.09:28:58.24#ibcon#*before return 0, iclass 5, count 0 2006.257.09:28:58.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:58.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:28:58.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:28:58.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:28:58.24$vck44/vb=5,4 2006.257.09:28:58.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.09:28:58.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.09:28:58.24#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:58.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:58.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:58.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:58.30#ibcon#enter wrdev, iclass 7, count 2 2006.257.09:28:58.30#ibcon#first serial, iclass 7, count 2 2006.257.09:28:58.30#ibcon#enter sib2, iclass 7, count 2 2006.257.09:28:58.30#ibcon#flushed, iclass 7, count 2 2006.257.09:28:58.30#ibcon#about to write, iclass 7, count 2 2006.257.09:28:58.30#ibcon#wrote, iclass 7, count 2 2006.257.09:28:58.30#ibcon#about to read 3, iclass 7, count 2 2006.257.09:28:58.32#ibcon#read 3, iclass 7, count 2 2006.257.09:28:58.32#ibcon#about to read 4, iclass 7, count 2 2006.257.09:28:58.32#ibcon#read 4, iclass 7, count 2 2006.257.09:28:58.32#ibcon#about to read 5, iclass 7, count 2 2006.257.09:28:58.32#ibcon#read 5, iclass 7, count 2 2006.257.09:28:58.32#ibcon#about to read 6, iclass 7, count 2 2006.257.09:28:58.32#ibcon#read 6, iclass 7, count 2 2006.257.09:28:58.32#ibcon#end of sib2, iclass 7, count 2 2006.257.09:28:58.32#ibcon#*mode == 0, iclass 7, count 2 2006.257.09:28:58.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.09:28:58.32#ibcon#[27=AT05-04\r\n] 2006.257.09:28:58.32#ibcon#*before write, iclass 7, count 2 2006.257.09:28:58.32#ibcon#enter sib2, iclass 7, count 2 2006.257.09:28:58.32#ibcon#flushed, iclass 7, count 2 2006.257.09:28:58.32#ibcon#about to write, iclass 7, count 2 2006.257.09:28:58.32#ibcon#wrote, iclass 7, count 2 2006.257.09:28:58.32#ibcon#about to read 3, iclass 7, count 2 2006.257.09:28:58.35#ibcon#read 3, iclass 7, count 2 2006.257.09:28:58.35#ibcon#about to read 4, iclass 7, count 2 2006.257.09:28:58.35#ibcon#read 4, iclass 7, count 2 2006.257.09:28:58.37#ibcon#about to read 5, iclass 7, count 2 2006.257.09:28:58.37#ibcon#read 5, iclass 7, count 2 2006.257.09:28:58.37#ibcon#about to read 6, iclass 7, count 2 2006.257.09:28:58.37#ibcon#read 6, iclass 7, count 2 2006.257.09:28:58.37#ibcon#end of sib2, iclass 7, count 2 2006.257.09:28:58.37#ibcon#*after write, iclass 7, count 2 2006.257.09:28:58.37#ibcon#*before return 0, iclass 7, count 2 2006.257.09:28:58.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:58.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:28:58.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.09:28:58.37#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:58.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:58.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:58.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:58.49#ibcon#enter wrdev, iclass 7, count 0 2006.257.09:28:58.49#ibcon#first serial, iclass 7, count 0 2006.257.09:28:58.49#ibcon#enter sib2, iclass 7, count 0 2006.257.09:28:58.49#ibcon#flushed, iclass 7, count 0 2006.257.09:28:58.49#ibcon#about to write, iclass 7, count 0 2006.257.09:28:58.49#ibcon#wrote, iclass 7, count 0 2006.257.09:28:58.49#ibcon#about to read 3, iclass 7, count 0 2006.257.09:28:58.51#ibcon#read 3, iclass 7, count 0 2006.257.09:28:58.51#ibcon#about to read 4, iclass 7, count 0 2006.257.09:28:58.51#ibcon#read 4, iclass 7, count 0 2006.257.09:28:58.51#ibcon#about to read 5, iclass 7, count 0 2006.257.09:28:58.51#ibcon#read 5, iclass 7, count 0 2006.257.09:28:58.51#ibcon#about to read 6, iclass 7, count 0 2006.257.09:28:58.51#ibcon#read 6, iclass 7, count 0 2006.257.09:28:58.51#ibcon#end of sib2, iclass 7, count 0 2006.257.09:28:58.51#ibcon#*mode == 0, iclass 7, count 0 2006.257.09:28:58.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.09:28:58.51#ibcon#[27=USB\r\n] 2006.257.09:28:58.51#ibcon#*before write, iclass 7, count 0 2006.257.09:28:58.51#ibcon#enter sib2, iclass 7, count 0 2006.257.09:28:58.51#ibcon#flushed, iclass 7, count 0 2006.257.09:28:58.51#ibcon#about to write, iclass 7, count 0 2006.257.09:28:58.51#ibcon#wrote, iclass 7, count 0 2006.257.09:28:58.51#ibcon#about to read 3, iclass 7, count 0 2006.257.09:28:58.54#ibcon#read 3, iclass 7, count 0 2006.257.09:28:58.54#ibcon#about to read 4, iclass 7, count 0 2006.257.09:28:58.54#ibcon#read 4, iclass 7, count 0 2006.257.09:28:58.54#ibcon#about to read 5, iclass 7, count 0 2006.257.09:28:58.54#ibcon#read 5, iclass 7, count 0 2006.257.09:28:58.54#ibcon#about to read 6, iclass 7, count 0 2006.257.09:28:58.54#ibcon#read 6, iclass 7, count 0 2006.257.09:28:58.54#ibcon#end of sib2, iclass 7, count 0 2006.257.09:28:58.54#ibcon#*after write, iclass 7, count 0 2006.257.09:28:58.54#ibcon#*before return 0, iclass 7, count 0 2006.257.09:28:58.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:58.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:28:58.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.09:28:58.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.09:28:58.54$vck44/vblo=6,719.99 2006.257.09:28:58.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.09:28:58.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.09:28:58.54#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:58.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:58.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:58.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:58.54#ibcon#enter wrdev, iclass 11, count 0 2006.257.09:28:58.54#ibcon#first serial, iclass 11, count 0 2006.257.09:28:58.54#ibcon#enter sib2, iclass 11, count 0 2006.257.09:28:58.54#ibcon#flushed, iclass 11, count 0 2006.257.09:28:58.54#ibcon#about to write, iclass 11, count 0 2006.257.09:28:58.54#ibcon#wrote, iclass 11, count 0 2006.257.09:28:58.54#ibcon#about to read 3, iclass 11, count 0 2006.257.09:28:58.56#ibcon#read 3, iclass 11, count 0 2006.257.09:28:58.56#ibcon#about to read 4, iclass 11, count 0 2006.257.09:28:58.56#ibcon#read 4, iclass 11, count 0 2006.257.09:28:58.56#ibcon#about to read 5, iclass 11, count 0 2006.257.09:28:58.56#ibcon#read 5, iclass 11, count 0 2006.257.09:28:58.56#ibcon#about to read 6, iclass 11, count 0 2006.257.09:28:58.56#ibcon#read 6, iclass 11, count 0 2006.257.09:28:58.56#ibcon#end of sib2, iclass 11, count 0 2006.257.09:28:58.56#ibcon#*mode == 0, iclass 11, count 0 2006.257.09:28:58.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.09:28:58.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:28:58.56#ibcon#*before write, iclass 11, count 0 2006.257.09:28:58.56#ibcon#enter sib2, iclass 11, count 0 2006.257.09:28:58.56#ibcon#flushed, iclass 11, count 0 2006.257.09:28:58.56#ibcon#about to write, iclass 11, count 0 2006.257.09:28:58.56#ibcon#wrote, iclass 11, count 0 2006.257.09:28:58.56#ibcon#about to read 3, iclass 11, count 0 2006.257.09:28:58.60#ibcon#read 3, iclass 11, count 0 2006.257.09:28:58.60#ibcon#about to read 4, iclass 11, count 0 2006.257.09:28:58.60#ibcon#read 4, iclass 11, count 0 2006.257.09:28:58.60#ibcon#about to read 5, iclass 11, count 0 2006.257.09:28:58.60#ibcon#read 5, iclass 11, count 0 2006.257.09:28:58.60#ibcon#about to read 6, iclass 11, count 0 2006.257.09:28:58.60#ibcon#read 6, iclass 11, count 0 2006.257.09:28:58.60#ibcon#end of sib2, iclass 11, count 0 2006.257.09:28:58.60#ibcon#*after write, iclass 11, count 0 2006.257.09:28:58.60#ibcon#*before return 0, iclass 11, count 0 2006.257.09:28:58.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:58.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:28:58.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.09:28:58.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.09:28:58.60$vck44/vb=6,4 2006.257.09:28:58.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.09:28:58.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.09:28:58.60#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:58.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:58.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:58.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:58.66#ibcon#enter wrdev, iclass 13, count 2 2006.257.09:28:58.66#ibcon#first serial, iclass 13, count 2 2006.257.09:28:58.66#ibcon#enter sib2, iclass 13, count 2 2006.257.09:28:58.66#ibcon#flushed, iclass 13, count 2 2006.257.09:28:58.66#ibcon#about to write, iclass 13, count 2 2006.257.09:28:58.66#ibcon#wrote, iclass 13, count 2 2006.257.09:28:58.66#ibcon#about to read 3, iclass 13, count 2 2006.257.09:28:58.68#ibcon#read 3, iclass 13, count 2 2006.257.09:28:58.68#ibcon#about to read 4, iclass 13, count 2 2006.257.09:28:58.68#ibcon#read 4, iclass 13, count 2 2006.257.09:28:58.68#ibcon#about to read 5, iclass 13, count 2 2006.257.09:28:58.68#ibcon#read 5, iclass 13, count 2 2006.257.09:28:58.68#ibcon#about to read 6, iclass 13, count 2 2006.257.09:28:58.68#ibcon#read 6, iclass 13, count 2 2006.257.09:28:58.68#ibcon#end of sib2, iclass 13, count 2 2006.257.09:28:58.68#ibcon#*mode == 0, iclass 13, count 2 2006.257.09:28:58.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.09:28:58.68#ibcon#[27=AT06-04\r\n] 2006.257.09:28:58.68#ibcon#*before write, iclass 13, count 2 2006.257.09:28:58.68#ibcon#enter sib2, iclass 13, count 2 2006.257.09:28:58.68#ibcon#flushed, iclass 13, count 2 2006.257.09:28:58.68#ibcon#about to write, iclass 13, count 2 2006.257.09:28:58.68#ibcon#wrote, iclass 13, count 2 2006.257.09:28:58.68#ibcon#about to read 3, iclass 13, count 2 2006.257.09:28:58.71#ibcon#read 3, iclass 13, count 2 2006.257.09:28:58.71#ibcon#about to read 4, iclass 13, count 2 2006.257.09:28:58.71#ibcon#read 4, iclass 13, count 2 2006.257.09:28:58.71#ibcon#about to read 5, iclass 13, count 2 2006.257.09:28:58.71#ibcon#read 5, iclass 13, count 2 2006.257.09:28:58.71#ibcon#about to read 6, iclass 13, count 2 2006.257.09:28:58.71#ibcon#read 6, iclass 13, count 2 2006.257.09:28:58.71#ibcon#end of sib2, iclass 13, count 2 2006.257.09:28:58.71#ibcon#*after write, iclass 13, count 2 2006.257.09:28:58.71#ibcon#*before return 0, iclass 13, count 2 2006.257.09:28:58.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:58.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:28:58.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.09:28:58.71#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:58.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:58.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:58.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:58.83#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:28:58.83#ibcon#first serial, iclass 13, count 0 2006.257.09:28:58.83#ibcon#enter sib2, iclass 13, count 0 2006.257.09:28:58.83#ibcon#flushed, iclass 13, count 0 2006.257.09:28:58.83#ibcon#about to write, iclass 13, count 0 2006.257.09:28:58.83#ibcon#wrote, iclass 13, count 0 2006.257.09:28:58.83#ibcon#about to read 3, iclass 13, count 0 2006.257.09:28:58.85#ibcon#read 3, iclass 13, count 0 2006.257.09:28:58.85#ibcon#about to read 4, iclass 13, count 0 2006.257.09:28:58.85#ibcon#read 4, iclass 13, count 0 2006.257.09:28:58.85#ibcon#about to read 5, iclass 13, count 0 2006.257.09:28:58.85#ibcon#read 5, iclass 13, count 0 2006.257.09:28:58.85#ibcon#about to read 6, iclass 13, count 0 2006.257.09:28:58.85#ibcon#read 6, iclass 13, count 0 2006.257.09:28:58.85#ibcon#end of sib2, iclass 13, count 0 2006.257.09:28:58.85#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:28:58.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:28:58.85#ibcon#[27=USB\r\n] 2006.257.09:28:58.85#ibcon#*before write, iclass 13, count 0 2006.257.09:28:58.85#ibcon#enter sib2, iclass 13, count 0 2006.257.09:28:58.85#ibcon#flushed, iclass 13, count 0 2006.257.09:28:58.85#ibcon#about to write, iclass 13, count 0 2006.257.09:28:58.85#ibcon#wrote, iclass 13, count 0 2006.257.09:28:58.85#ibcon#about to read 3, iclass 13, count 0 2006.257.09:28:58.88#ibcon#read 3, iclass 13, count 0 2006.257.09:28:58.88#ibcon#about to read 4, iclass 13, count 0 2006.257.09:28:58.88#ibcon#read 4, iclass 13, count 0 2006.257.09:28:58.88#ibcon#about to read 5, iclass 13, count 0 2006.257.09:28:58.88#ibcon#read 5, iclass 13, count 0 2006.257.09:28:58.88#ibcon#about to read 6, iclass 13, count 0 2006.257.09:28:58.88#ibcon#read 6, iclass 13, count 0 2006.257.09:28:58.88#ibcon#end of sib2, iclass 13, count 0 2006.257.09:28:58.88#ibcon#*after write, iclass 13, count 0 2006.257.09:28:58.88#ibcon#*before return 0, iclass 13, count 0 2006.257.09:28:58.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:58.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:28:58.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:28:58.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:28:58.88$vck44/vblo=7,734.99 2006.257.09:28:58.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.09:28:58.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.09:28:58.88#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:58.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:58.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:58.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:58.88#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:28:58.88#ibcon#first serial, iclass 15, count 0 2006.257.09:28:58.88#ibcon#enter sib2, iclass 15, count 0 2006.257.09:28:58.88#ibcon#flushed, iclass 15, count 0 2006.257.09:28:58.88#ibcon#about to write, iclass 15, count 0 2006.257.09:28:58.88#ibcon#wrote, iclass 15, count 0 2006.257.09:28:58.88#ibcon#about to read 3, iclass 15, count 0 2006.257.09:28:58.90#ibcon#read 3, iclass 15, count 0 2006.257.09:28:58.90#ibcon#about to read 4, iclass 15, count 0 2006.257.09:28:58.90#ibcon#read 4, iclass 15, count 0 2006.257.09:28:58.90#ibcon#about to read 5, iclass 15, count 0 2006.257.09:28:58.90#ibcon#read 5, iclass 15, count 0 2006.257.09:28:58.90#ibcon#about to read 6, iclass 15, count 0 2006.257.09:28:58.90#ibcon#read 6, iclass 15, count 0 2006.257.09:28:58.90#ibcon#end of sib2, iclass 15, count 0 2006.257.09:28:58.90#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:28:58.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:28:58.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:28:58.90#ibcon#*before write, iclass 15, count 0 2006.257.09:28:58.90#ibcon#enter sib2, iclass 15, count 0 2006.257.09:28:58.90#ibcon#flushed, iclass 15, count 0 2006.257.09:28:58.90#ibcon#about to write, iclass 15, count 0 2006.257.09:28:58.90#ibcon#wrote, iclass 15, count 0 2006.257.09:28:58.90#ibcon#about to read 3, iclass 15, count 0 2006.257.09:28:58.94#ibcon#read 3, iclass 15, count 0 2006.257.09:28:58.94#ibcon#about to read 4, iclass 15, count 0 2006.257.09:28:58.94#ibcon#read 4, iclass 15, count 0 2006.257.09:28:58.94#ibcon#about to read 5, iclass 15, count 0 2006.257.09:28:58.94#ibcon#read 5, iclass 15, count 0 2006.257.09:28:58.94#ibcon#about to read 6, iclass 15, count 0 2006.257.09:28:58.94#ibcon#read 6, iclass 15, count 0 2006.257.09:28:58.94#ibcon#end of sib2, iclass 15, count 0 2006.257.09:28:58.94#ibcon#*after write, iclass 15, count 0 2006.257.09:28:58.94#ibcon#*before return 0, iclass 15, count 0 2006.257.09:28:58.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:58.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:28:58.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:28:58.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:28:58.94$vck44/vb=7,4 2006.257.09:28:58.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.09:28:58.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.09:28:58.94#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:58.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:59.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:59.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:59.00#ibcon#enter wrdev, iclass 17, count 2 2006.257.09:28:59.00#ibcon#first serial, iclass 17, count 2 2006.257.09:28:59.00#ibcon#enter sib2, iclass 17, count 2 2006.257.09:28:59.00#ibcon#flushed, iclass 17, count 2 2006.257.09:28:59.00#ibcon#about to write, iclass 17, count 2 2006.257.09:28:59.00#ibcon#wrote, iclass 17, count 2 2006.257.09:28:59.00#ibcon#about to read 3, iclass 17, count 2 2006.257.09:28:59.02#ibcon#read 3, iclass 17, count 2 2006.257.09:28:59.02#ibcon#about to read 4, iclass 17, count 2 2006.257.09:28:59.02#ibcon#read 4, iclass 17, count 2 2006.257.09:28:59.02#ibcon#about to read 5, iclass 17, count 2 2006.257.09:28:59.02#ibcon#read 5, iclass 17, count 2 2006.257.09:28:59.02#ibcon#about to read 6, iclass 17, count 2 2006.257.09:28:59.02#ibcon#read 6, iclass 17, count 2 2006.257.09:28:59.02#ibcon#end of sib2, iclass 17, count 2 2006.257.09:28:59.02#ibcon#*mode == 0, iclass 17, count 2 2006.257.09:28:59.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.09:28:59.02#ibcon#[27=AT07-04\r\n] 2006.257.09:28:59.02#ibcon#*before write, iclass 17, count 2 2006.257.09:28:59.02#ibcon#enter sib2, iclass 17, count 2 2006.257.09:28:59.02#ibcon#flushed, iclass 17, count 2 2006.257.09:28:59.02#ibcon#about to write, iclass 17, count 2 2006.257.09:28:59.02#ibcon#wrote, iclass 17, count 2 2006.257.09:28:59.02#ibcon#about to read 3, iclass 17, count 2 2006.257.09:28:59.05#abcon#<5=/16 0.7 1.8 19.61 951013.3\r\n> 2006.257.09:28:59.05#ibcon#read 3, iclass 17, count 2 2006.257.09:28:59.05#ibcon#about to read 4, iclass 17, count 2 2006.257.09:28:59.05#ibcon#read 4, iclass 17, count 2 2006.257.09:28:59.05#ibcon#about to read 5, iclass 17, count 2 2006.257.09:28:59.05#ibcon#read 5, iclass 17, count 2 2006.257.09:28:59.05#ibcon#about to read 6, iclass 17, count 2 2006.257.09:28:59.05#ibcon#read 6, iclass 17, count 2 2006.257.09:28:59.05#ibcon#end of sib2, iclass 17, count 2 2006.257.09:28:59.05#ibcon#*after write, iclass 17, count 2 2006.257.09:28:59.05#ibcon#*before return 0, iclass 17, count 2 2006.257.09:28:59.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:59.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:28:59.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.09:28:59.05#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:59.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:59.07#abcon#{5=INTERFACE CLEAR} 2006.257.09:28:59.13#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:28:59.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:59.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:59.17#ibcon#enter wrdev, iclass 17, count 0 2006.257.09:28:59.17#ibcon#first serial, iclass 17, count 0 2006.257.09:28:59.17#ibcon#enter sib2, iclass 17, count 0 2006.257.09:28:59.17#ibcon#flushed, iclass 17, count 0 2006.257.09:28:59.17#ibcon#about to write, iclass 17, count 0 2006.257.09:28:59.17#ibcon#wrote, iclass 17, count 0 2006.257.09:28:59.17#ibcon#about to read 3, iclass 17, count 0 2006.257.09:28:59.19#ibcon#read 3, iclass 17, count 0 2006.257.09:28:59.19#ibcon#about to read 4, iclass 17, count 0 2006.257.09:28:59.19#ibcon#read 4, iclass 17, count 0 2006.257.09:28:59.19#ibcon#about to read 5, iclass 17, count 0 2006.257.09:28:59.19#ibcon#read 5, iclass 17, count 0 2006.257.09:28:59.19#ibcon#about to read 6, iclass 17, count 0 2006.257.09:28:59.19#ibcon#read 6, iclass 17, count 0 2006.257.09:28:59.19#ibcon#end of sib2, iclass 17, count 0 2006.257.09:28:59.19#ibcon#*mode == 0, iclass 17, count 0 2006.257.09:28:59.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.09:28:59.19#ibcon#[27=USB\r\n] 2006.257.09:28:59.19#ibcon#*before write, iclass 17, count 0 2006.257.09:28:59.19#ibcon#enter sib2, iclass 17, count 0 2006.257.09:28:59.19#ibcon#flushed, iclass 17, count 0 2006.257.09:28:59.19#ibcon#about to write, iclass 17, count 0 2006.257.09:28:59.19#ibcon#wrote, iclass 17, count 0 2006.257.09:28:59.19#ibcon#about to read 3, iclass 17, count 0 2006.257.09:28:59.22#ibcon#read 3, iclass 17, count 0 2006.257.09:28:59.22#ibcon#about to read 4, iclass 17, count 0 2006.257.09:28:59.22#ibcon#read 4, iclass 17, count 0 2006.257.09:28:59.22#ibcon#about to read 5, iclass 17, count 0 2006.257.09:28:59.22#ibcon#read 5, iclass 17, count 0 2006.257.09:28:59.22#ibcon#about to read 6, iclass 17, count 0 2006.257.09:28:59.22#ibcon#read 6, iclass 17, count 0 2006.257.09:28:59.22#ibcon#end of sib2, iclass 17, count 0 2006.257.09:28:59.22#ibcon#*after write, iclass 17, count 0 2006.257.09:28:59.22#ibcon#*before return 0, iclass 17, count 0 2006.257.09:28:59.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:59.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:28:59.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.09:28:59.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.09:28:59.22$vck44/vblo=8,744.99 2006.257.09:28:59.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.09:28:59.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.09:28:59.22#ibcon#ireg 17 cls_cnt 0 2006.257.09:28:59.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:59.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:59.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:59.22#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:28:59.22#ibcon#first serial, iclass 23, count 0 2006.257.09:28:59.22#ibcon#enter sib2, iclass 23, count 0 2006.257.09:28:59.22#ibcon#flushed, iclass 23, count 0 2006.257.09:28:59.22#ibcon#about to write, iclass 23, count 0 2006.257.09:28:59.22#ibcon#wrote, iclass 23, count 0 2006.257.09:28:59.22#ibcon#about to read 3, iclass 23, count 0 2006.257.09:28:59.24#ibcon#read 3, iclass 23, count 0 2006.257.09:28:59.24#ibcon#about to read 4, iclass 23, count 0 2006.257.09:28:59.24#ibcon#read 4, iclass 23, count 0 2006.257.09:28:59.24#ibcon#about to read 5, iclass 23, count 0 2006.257.09:28:59.24#ibcon#read 5, iclass 23, count 0 2006.257.09:28:59.24#ibcon#about to read 6, iclass 23, count 0 2006.257.09:28:59.24#ibcon#read 6, iclass 23, count 0 2006.257.09:28:59.24#ibcon#end of sib2, iclass 23, count 0 2006.257.09:28:59.24#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:28:59.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:28:59.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:28:59.24#ibcon#*before write, iclass 23, count 0 2006.257.09:28:59.24#ibcon#enter sib2, iclass 23, count 0 2006.257.09:28:59.24#ibcon#flushed, iclass 23, count 0 2006.257.09:28:59.24#ibcon#about to write, iclass 23, count 0 2006.257.09:28:59.24#ibcon#wrote, iclass 23, count 0 2006.257.09:28:59.24#ibcon#about to read 3, iclass 23, count 0 2006.257.09:28:59.28#ibcon#read 3, iclass 23, count 0 2006.257.09:28:59.28#ibcon#about to read 4, iclass 23, count 0 2006.257.09:28:59.28#ibcon#read 4, iclass 23, count 0 2006.257.09:28:59.28#ibcon#about to read 5, iclass 23, count 0 2006.257.09:28:59.28#ibcon#read 5, iclass 23, count 0 2006.257.09:28:59.28#ibcon#about to read 6, iclass 23, count 0 2006.257.09:28:59.28#ibcon#read 6, iclass 23, count 0 2006.257.09:28:59.28#ibcon#end of sib2, iclass 23, count 0 2006.257.09:28:59.28#ibcon#*after write, iclass 23, count 0 2006.257.09:28:59.28#ibcon#*before return 0, iclass 23, count 0 2006.257.09:28:59.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:59.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:28:59.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:28:59.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:28:59.28$vck44/vb=8,4 2006.257.09:28:59.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.09:28:59.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.09:28:59.28#ibcon#ireg 11 cls_cnt 2 2006.257.09:28:59.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:59.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:59.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:59.34#ibcon#enter wrdev, iclass 25, count 2 2006.257.09:28:59.34#ibcon#first serial, iclass 25, count 2 2006.257.09:28:59.34#ibcon#enter sib2, iclass 25, count 2 2006.257.09:28:59.34#ibcon#flushed, iclass 25, count 2 2006.257.09:28:59.34#ibcon#about to write, iclass 25, count 2 2006.257.09:28:59.34#ibcon#wrote, iclass 25, count 2 2006.257.09:28:59.34#ibcon#about to read 3, iclass 25, count 2 2006.257.09:28:59.36#ibcon#read 3, iclass 25, count 2 2006.257.09:28:59.36#ibcon#about to read 4, iclass 25, count 2 2006.257.09:28:59.36#ibcon#read 4, iclass 25, count 2 2006.257.09:28:59.36#ibcon#about to read 5, iclass 25, count 2 2006.257.09:28:59.36#ibcon#read 5, iclass 25, count 2 2006.257.09:28:59.36#ibcon#about to read 6, iclass 25, count 2 2006.257.09:28:59.36#ibcon#read 6, iclass 25, count 2 2006.257.09:28:59.36#ibcon#end of sib2, iclass 25, count 2 2006.257.09:28:59.36#ibcon#*mode == 0, iclass 25, count 2 2006.257.09:28:59.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.09:28:59.36#ibcon#[27=AT08-04\r\n] 2006.257.09:28:59.36#ibcon#*before write, iclass 25, count 2 2006.257.09:28:59.36#ibcon#enter sib2, iclass 25, count 2 2006.257.09:28:59.36#ibcon#flushed, iclass 25, count 2 2006.257.09:28:59.36#ibcon#about to write, iclass 25, count 2 2006.257.09:28:59.36#ibcon#wrote, iclass 25, count 2 2006.257.09:28:59.37#ibcon#about to read 3, iclass 25, count 2 2006.257.09:28:59.39#ibcon#read 3, iclass 25, count 2 2006.257.09:28:59.39#ibcon#about to read 4, iclass 25, count 2 2006.257.09:28:59.39#ibcon#read 4, iclass 25, count 2 2006.257.09:28:59.39#ibcon#about to read 5, iclass 25, count 2 2006.257.09:28:59.39#ibcon#read 5, iclass 25, count 2 2006.257.09:28:59.39#ibcon#about to read 6, iclass 25, count 2 2006.257.09:28:59.39#ibcon#read 6, iclass 25, count 2 2006.257.09:28:59.39#ibcon#end of sib2, iclass 25, count 2 2006.257.09:28:59.39#ibcon#*after write, iclass 25, count 2 2006.257.09:28:59.39#ibcon#*before return 0, iclass 25, count 2 2006.257.09:28:59.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:59.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:28:59.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.09:28:59.39#ibcon#ireg 7 cls_cnt 0 2006.257.09:28:59.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:59.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:59.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:59.51#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:28:59.51#ibcon#first serial, iclass 25, count 0 2006.257.09:28:59.51#ibcon#enter sib2, iclass 25, count 0 2006.257.09:28:59.51#ibcon#flushed, iclass 25, count 0 2006.257.09:28:59.51#ibcon#about to write, iclass 25, count 0 2006.257.09:28:59.51#ibcon#wrote, iclass 25, count 0 2006.257.09:28:59.51#ibcon#about to read 3, iclass 25, count 0 2006.257.09:28:59.53#ibcon#read 3, iclass 25, count 0 2006.257.09:28:59.53#ibcon#about to read 4, iclass 25, count 0 2006.257.09:28:59.53#ibcon#read 4, iclass 25, count 0 2006.257.09:28:59.53#ibcon#about to read 5, iclass 25, count 0 2006.257.09:28:59.53#ibcon#read 5, iclass 25, count 0 2006.257.09:28:59.53#ibcon#about to read 6, iclass 25, count 0 2006.257.09:28:59.53#ibcon#read 6, iclass 25, count 0 2006.257.09:28:59.53#ibcon#end of sib2, iclass 25, count 0 2006.257.09:28:59.53#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:28:59.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:28:59.53#ibcon#[27=USB\r\n] 2006.257.09:28:59.53#ibcon#*before write, iclass 25, count 0 2006.257.09:28:59.53#ibcon#enter sib2, iclass 25, count 0 2006.257.09:28:59.53#ibcon#flushed, iclass 25, count 0 2006.257.09:28:59.53#ibcon#about to write, iclass 25, count 0 2006.257.09:28:59.53#ibcon#wrote, iclass 25, count 0 2006.257.09:28:59.53#ibcon#about to read 3, iclass 25, count 0 2006.257.09:28:59.56#ibcon#read 3, iclass 25, count 0 2006.257.09:28:59.56#ibcon#about to read 4, iclass 25, count 0 2006.257.09:28:59.56#ibcon#read 4, iclass 25, count 0 2006.257.09:28:59.56#ibcon#about to read 5, iclass 25, count 0 2006.257.09:28:59.56#ibcon#read 5, iclass 25, count 0 2006.257.09:28:59.56#ibcon#about to read 6, iclass 25, count 0 2006.257.09:28:59.56#ibcon#read 6, iclass 25, count 0 2006.257.09:28:59.56#ibcon#end of sib2, iclass 25, count 0 2006.257.09:28:59.56#ibcon#*after write, iclass 25, count 0 2006.257.09:28:59.56#ibcon#*before return 0, iclass 25, count 0 2006.257.09:28:59.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:59.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:28:59.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:28:59.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:28:59.56$vck44/vabw=wide 2006.257.09:28:59.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.09:28:59.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.09:28:59.56#ibcon#ireg 8 cls_cnt 0 2006.257.09:28:59.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:59.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:59.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:59.56#ibcon#enter wrdev, iclass 27, count 0 2006.257.09:28:59.56#ibcon#first serial, iclass 27, count 0 2006.257.09:28:59.56#ibcon#enter sib2, iclass 27, count 0 2006.257.09:28:59.56#ibcon#flushed, iclass 27, count 0 2006.257.09:28:59.56#ibcon#about to write, iclass 27, count 0 2006.257.09:28:59.56#ibcon#wrote, iclass 27, count 0 2006.257.09:28:59.56#ibcon#about to read 3, iclass 27, count 0 2006.257.09:28:59.58#ibcon#read 3, iclass 27, count 0 2006.257.09:28:59.58#ibcon#about to read 4, iclass 27, count 0 2006.257.09:28:59.58#ibcon#read 4, iclass 27, count 0 2006.257.09:28:59.58#ibcon#about to read 5, iclass 27, count 0 2006.257.09:28:59.58#ibcon#read 5, iclass 27, count 0 2006.257.09:28:59.58#ibcon#about to read 6, iclass 27, count 0 2006.257.09:28:59.58#ibcon#read 6, iclass 27, count 0 2006.257.09:28:59.58#ibcon#end of sib2, iclass 27, count 0 2006.257.09:28:59.58#ibcon#*mode == 0, iclass 27, count 0 2006.257.09:28:59.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.09:28:59.58#ibcon#[25=BW32\r\n] 2006.257.09:28:59.58#ibcon#*before write, iclass 27, count 0 2006.257.09:28:59.58#ibcon#enter sib2, iclass 27, count 0 2006.257.09:28:59.58#ibcon#flushed, iclass 27, count 0 2006.257.09:28:59.58#ibcon#about to write, iclass 27, count 0 2006.257.09:28:59.58#ibcon#wrote, iclass 27, count 0 2006.257.09:28:59.58#ibcon#about to read 3, iclass 27, count 0 2006.257.09:28:59.61#ibcon#read 3, iclass 27, count 0 2006.257.09:28:59.61#ibcon#about to read 4, iclass 27, count 0 2006.257.09:28:59.61#ibcon#read 4, iclass 27, count 0 2006.257.09:28:59.61#ibcon#about to read 5, iclass 27, count 0 2006.257.09:28:59.61#ibcon#read 5, iclass 27, count 0 2006.257.09:28:59.61#ibcon#about to read 6, iclass 27, count 0 2006.257.09:28:59.61#ibcon#read 6, iclass 27, count 0 2006.257.09:28:59.61#ibcon#end of sib2, iclass 27, count 0 2006.257.09:28:59.61#ibcon#*after write, iclass 27, count 0 2006.257.09:28:59.61#ibcon#*before return 0, iclass 27, count 0 2006.257.09:28:59.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:59.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:28:59.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.09:28:59.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.09:28:59.61$vck44/vbbw=wide 2006.257.09:28:59.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.09:28:59.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.09:28:59.61#ibcon#ireg 8 cls_cnt 0 2006.257.09:28:59.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:28:59.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:28:59.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:28:59.68#ibcon#enter wrdev, iclass 29, count 0 2006.257.09:28:59.68#ibcon#first serial, iclass 29, count 0 2006.257.09:28:59.68#ibcon#enter sib2, iclass 29, count 0 2006.257.09:28:59.68#ibcon#flushed, iclass 29, count 0 2006.257.09:28:59.68#ibcon#about to write, iclass 29, count 0 2006.257.09:28:59.68#ibcon#wrote, iclass 29, count 0 2006.257.09:28:59.68#ibcon#about to read 3, iclass 29, count 0 2006.257.09:28:59.70#ibcon#read 3, iclass 29, count 0 2006.257.09:28:59.70#ibcon#about to read 4, iclass 29, count 0 2006.257.09:28:59.70#ibcon#read 4, iclass 29, count 0 2006.257.09:28:59.70#ibcon#about to read 5, iclass 29, count 0 2006.257.09:28:59.70#ibcon#read 5, iclass 29, count 0 2006.257.09:28:59.70#ibcon#about to read 6, iclass 29, count 0 2006.257.09:28:59.70#ibcon#read 6, iclass 29, count 0 2006.257.09:28:59.70#ibcon#end of sib2, iclass 29, count 0 2006.257.09:28:59.70#ibcon#*mode == 0, iclass 29, count 0 2006.257.09:28:59.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.09:28:59.70#ibcon#[27=BW32\r\n] 2006.257.09:28:59.70#ibcon#*before write, iclass 29, count 0 2006.257.09:28:59.70#ibcon#enter sib2, iclass 29, count 0 2006.257.09:28:59.70#ibcon#flushed, iclass 29, count 0 2006.257.09:28:59.70#ibcon#about to write, iclass 29, count 0 2006.257.09:28:59.70#ibcon#wrote, iclass 29, count 0 2006.257.09:28:59.70#ibcon#about to read 3, iclass 29, count 0 2006.257.09:28:59.73#ibcon#read 3, iclass 29, count 0 2006.257.09:28:59.73#ibcon#about to read 4, iclass 29, count 0 2006.257.09:28:59.73#ibcon#read 4, iclass 29, count 0 2006.257.09:28:59.73#ibcon#about to read 5, iclass 29, count 0 2006.257.09:28:59.73#ibcon#read 5, iclass 29, count 0 2006.257.09:28:59.73#ibcon#about to read 6, iclass 29, count 0 2006.257.09:28:59.73#ibcon#read 6, iclass 29, count 0 2006.257.09:28:59.73#ibcon#end of sib2, iclass 29, count 0 2006.257.09:28:59.73#ibcon#*after write, iclass 29, count 0 2006.257.09:28:59.73#ibcon#*before return 0, iclass 29, count 0 2006.257.09:28:59.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:28:59.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:28:59.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.09:28:59.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.09:28:59.73$setupk4/ifdk4 2006.257.09:28:59.73$ifdk4/lo= 2006.257.09:28:59.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:28:59.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:28:59.73$ifdk4/patch= 2006.257.09:28:59.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:28:59.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:28:59.73$setupk4/!*+20s 2006.257.09:29:09.22#abcon#<5=/16 0.8 1.8 19.61 951013.3\r\n> 2006.257.09:29:09.24#abcon#{5=INTERFACE CLEAR} 2006.257.09:29:09.30#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:29:14.21$setupk4/"tpicd 2006.257.09:29:14.21$setupk4/echo=off 2006.257.09:29:14.21$setupk4/xlog=off 2006.257.09:29:14.21:!2006.257.09:32:30 2006.257.09:29:28.14#trakl#Source acquired 2006.257.09:29:28.14#flagr#flagr/antenna,acquired 2006.257.09:32:30.00:preob 2006.257.09:32:30.13/onsource/TRACKING 2006.257.09:32:30.13:!2006.257.09:32:40 2006.257.09:32:40.00:"tape 2006.257.09:32:40.00:"st=record 2006.257.09:32:40.00:data_valid=on 2006.257.09:32:40.00:midob 2006.257.09:32:40.13/onsource/TRACKING 2006.257.09:32:40.13/wx/19.55,1013.1,95 2006.257.09:32:40.32/cable/+6.4756E-03 2006.257.09:32:41.41/va/01,08,usb,yes,30,33 2006.257.09:32:41.41/va/02,07,usb,yes,33,33 2006.257.09:32:41.41/va/03,08,usb,yes,30,31 2006.257.09:32:41.41/va/04,07,usb,yes,34,36 2006.257.09:32:41.41/va/05,04,usb,yes,30,31 2006.257.09:32:41.41/va/06,04,usb,yes,34,34 2006.257.09:32:41.41/va/07,04,usb,yes,35,35 2006.257.09:32:41.41/va/08,04,usb,yes,29,36 2006.257.09:32:41.64/valo/01,524.99,yes,locked 2006.257.09:32:41.64/valo/02,534.99,yes,locked 2006.257.09:32:41.64/valo/03,564.99,yes,locked 2006.257.09:32:41.64/valo/04,624.99,yes,locked 2006.257.09:32:41.64/valo/05,734.99,yes,locked 2006.257.09:32:41.64/valo/06,814.99,yes,locked 2006.257.09:32:41.64/valo/07,864.99,yes,locked 2006.257.09:32:41.64/valo/08,884.99,yes,locked 2006.257.09:32:42.73/vb/01,04,usb,yes,30,28 2006.257.09:32:42.73/vb/02,05,usb,yes,29,28 2006.257.09:32:42.73/vb/03,04,usb,yes,29,32 2006.257.09:32:42.73/vb/04,05,usb,yes,30,29 2006.257.09:32:42.73/vb/05,04,usb,yes,26,29 2006.257.09:32:42.73/vb/06,04,usb,yes,31,27 2006.257.09:32:42.73/vb/07,04,usb,yes,30,30 2006.257.09:32:42.73/vb/08,04,usb,yes,28,31 2006.257.09:32:42.96/vblo/01,629.99,yes,locked 2006.257.09:32:42.96/vblo/02,634.99,yes,locked 2006.257.09:32:42.96/vblo/03,649.99,yes,locked 2006.257.09:32:42.96/vblo/04,679.99,yes,locked 2006.257.09:32:42.96/vblo/05,709.99,yes,locked 2006.257.09:32:42.96/vblo/06,719.99,yes,locked 2006.257.09:32:42.96/vblo/07,734.99,yes,locked 2006.257.09:32:42.96/vblo/08,744.99,yes,locked 2006.257.09:32:43.11/vabw/8 2006.257.09:32:43.26/vbbw/8 2006.257.09:32:43.35/xfe/off,on,15.0 2006.257.09:32:43.73/ifatt/23,28,28,28 2006.257.09:32:44.08/fmout-gps/S +4.61E-07 2006.257.09:32:44.11:!2006.257.09:35:30 2006.257.09:35:30.01:data_valid=off 2006.257.09:35:30.01:"et 2006.257.09:35:30.01:!+3s 2006.257.09:35:33.02:"tape 2006.257.09:35:33.02:postob 2006.257.09:35:33.20/cable/+6.4749E-03 2006.257.09:35:33.20/wx/19.52,1013.1,95 2006.257.09:35:34.08/fmout-gps/S +4.65E-07 2006.257.09:35:34.08:scan_name=257-0941,jd0609,80 2006.257.09:35:34.08:source=2136+141,213901.31,142336.0,2000.0,cw 2006.257.09:35:35.14#flagr#flagr/antenna,new-source 2006.257.09:35:35.14:checkk5 2006.257.09:35:35.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:35:35.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:35:36.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:35:36.80/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:35:37.18/chk_obsdata//k5ts1/T2570932??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.257.09:35:37.57/chk_obsdata//k5ts2/T2570932??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.257.09:35:37.98/chk_obsdata//k5ts3/T2570932??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.257.09:35:38.39/chk_obsdata//k5ts4/T2570932??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.257.09:35:39.11/k5log//k5ts1_log_newline 2006.257.09:35:39.83/k5log//k5ts2_log_newline 2006.257.09:35:40.54/k5log//k5ts3_log_newline 2006.257.09:35:41.24/k5log//k5ts4_log_newline 2006.257.09:35:41.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:35:41.26:setupk4=1 2006.257.09:35:41.26$setupk4/echo=on 2006.257.09:35:41.26$setupk4/pcalon 2006.257.09:35:41.26$pcalon/"no phase cal control is implemented here 2006.257.09:35:41.26$setupk4/"tpicd=stop 2006.257.09:35:41.26$setupk4/"rec=synch_on 2006.257.09:35:41.26$setupk4/"rec_mode=128 2006.257.09:35:41.26$setupk4/!* 2006.257.09:35:41.26$setupk4/recpk4 2006.257.09:35:41.26$recpk4/recpatch= 2006.257.09:35:41.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:35:41.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:35:41.27$setupk4/vck44 2006.257.09:35:41.27$vck44/valo=1,524.99 2006.257.09:35:41.27#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.09:35:41.27#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.09:35:41.27#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:41.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:41.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:41.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:41.27#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:35:41.27#ibcon#first serial, iclass 10, count 0 2006.257.09:35:41.27#ibcon#enter sib2, iclass 10, count 0 2006.257.09:35:41.27#ibcon#flushed, iclass 10, count 0 2006.257.09:35:41.27#ibcon#about to write, iclass 10, count 0 2006.257.09:35:41.27#ibcon#wrote, iclass 10, count 0 2006.257.09:35:41.27#ibcon#about to read 3, iclass 10, count 0 2006.257.09:35:41.29#ibcon#read 3, iclass 10, count 0 2006.257.09:35:41.29#ibcon#about to read 4, iclass 10, count 0 2006.257.09:35:41.29#ibcon#read 4, iclass 10, count 0 2006.257.09:35:41.29#ibcon#about to read 5, iclass 10, count 0 2006.257.09:35:41.29#ibcon#read 5, iclass 10, count 0 2006.257.09:35:41.29#ibcon#about to read 6, iclass 10, count 0 2006.257.09:35:41.29#ibcon#read 6, iclass 10, count 0 2006.257.09:35:41.29#ibcon#end of sib2, iclass 10, count 0 2006.257.09:35:41.29#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:35:41.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:35:41.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:35:41.29#ibcon#*before write, iclass 10, count 0 2006.257.09:35:41.29#ibcon#enter sib2, iclass 10, count 0 2006.257.09:35:41.29#ibcon#flushed, iclass 10, count 0 2006.257.09:35:41.29#ibcon#about to write, iclass 10, count 0 2006.257.09:35:41.29#ibcon#wrote, iclass 10, count 0 2006.257.09:35:41.29#ibcon#about to read 3, iclass 10, count 0 2006.257.09:35:41.34#ibcon#read 3, iclass 10, count 0 2006.257.09:35:41.34#ibcon#about to read 4, iclass 10, count 0 2006.257.09:35:41.34#ibcon#read 4, iclass 10, count 0 2006.257.09:35:41.34#ibcon#about to read 5, iclass 10, count 0 2006.257.09:35:41.34#ibcon#read 5, iclass 10, count 0 2006.257.09:35:41.34#ibcon#about to read 6, iclass 10, count 0 2006.257.09:35:41.34#ibcon#read 6, iclass 10, count 0 2006.257.09:35:41.34#ibcon#end of sib2, iclass 10, count 0 2006.257.09:35:41.34#ibcon#*after write, iclass 10, count 0 2006.257.09:35:41.34#ibcon#*before return 0, iclass 10, count 0 2006.257.09:35:41.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:41.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:41.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:35:41.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:35:41.34$vck44/va=1,8 2006.257.09:35:41.34#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.09:35:41.34#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.09:35:41.34#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:41.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:41.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:41.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:41.34#ibcon#enter wrdev, iclass 12, count 2 2006.257.09:35:41.34#ibcon#first serial, iclass 12, count 2 2006.257.09:35:41.34#ibcon#enter sib2, iclass 12, count 2 2006.257.09:35:41.34#ibcon#flushed, iclass 12, count 2 2006.257.09:35:41.34#ibcon#about to write, iclass 12, count 2 2006.257.09:35:41.34#ibcon#wrote, iclass 12, count 2 2006.257.09:35:41.34#ibcon#about to read 3, iclass 12, count 2 2006.257.09:35:41.36#ibcon#read 3, iclass 12, count 2 2006.257.09:35:41.36#ibcon#about to read 4, iclass 12, count 2 2006.257.09:35:41.36#ibcon#read 4, iclass 12, count 2 2006.257.09:35:41.36#ibcon#about to read 5, iclass 12, count 2 2006.257.09:35:41.36#ibcon#read 5, iclass 12, count 2 2006.257.09:35:41.36#ibcon#about to read 6, iclass 12, count 2 2006.257.09:35:41.36#ibcon#read 6, iclass 12, count 2 2006.257.09:35:41.36#ibcon#end of sib2, iclass 12, count 2 2006.257.09:35:41.36#ibcon#*mode == 0, iclass 12, count 2 2006.257.09:35:41.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.09:35:41.36#ibcon#[25=AT01-08\r\n] 2006.257.09:35:41.36#ibcon#*before write, iclass 12, count 2 2006.257.09:35:41.36#ibcon#enter sib2, iclass 12, count 2 2006.257.09:35:41.36#ibcon#flushed, iclass 12, count 2 2006.257.09:35:41.36#ibcon#about to write, iclass 12, count 2 2006.257.09:35:41.36#ibcon#wrote, iclass 12, count 2 2006.257.09:35:41.36#ibcon#about to read 3, iclass 12, count 2 2006.257.09:35:41.39#ibcon#read 3, iclass 12, count 2 2006.257.09:35:41.39#ibcon#about to read 4, iclass 12, count 2 2006.257.09:35:41.39#ibcon#read 4, iclass 12, count 2 2006.257.09:35:41.39#ibcon#about to read 5, iclass 12, count 2 2006.257.09:35:41.39#ibcon#read 5, iclass 12, count 2 2006.257.09:35:41.39#ibcon#about to read 6, iclass 12, count 2 2006.257.09:35:41.39#ibcon#read 6, iclass 12, count 2 2006.257.09:35:41.39#ibcon#end of sib2, iclass 12, count 2 2006.257.09:35:41.39#ibcon#*after write, iclass 12, count 2 2006.257.09:35:41.39#ibcon#*before return 0, iclass 12, count 2 2006.257.09:35:41.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:41.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:41.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.09:35:41.39#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:41.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:41.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:41.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:41.51#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:35:41.51#ibcon#first serial, iclass 12, count 0 2006.257.09:35:41.51#ibcon#enter sib2, iclass 12, count 0 2006.257.09:35:41.51#ibcon#flushed, iclass 12, count 0 2006.257.09:35:41.51#ibcon#about to write, iclass 12, count 0 2006.257.09:35:41.51#ibcon#wrote, iclass 12, count 0 2006.257.09:35:41.51#ibcon#about to read 3, iclass 12, count 0 2006.257.09:35:41.53#ibcon#read 3, iclass 12, count 0 2006.257.09:35:41.53#ibcon#about to read 4, iclass 12, count 0 2006.257.09:35:41.53#ibcon#read 4, iclass 12, count 0 2006.257.09:35:41.53#ibcon#about to read 5, iclass 12, count 0 2006.257.09:35:41.53#ibcon#read 5, iclass 12, count 0 2006.257.09:35:41.53#ibcon#about to read 6, iclass 12, count 0 2006.257.09:35:41.53#ibcon#read 6, iclass 12, count 0 2006.257.09:35:41.53#ibcon#end of sib2, iclass 12, count 0 2006.257.09:35:41.53#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:35:41.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:35:41.53#ibcon#[25=USB\r\n] 2006.257.09:35:41.53#ibcon#*before write, iclass 12, count 0 2006.257.09:35:41.53#ibcon#enter sib2, iclass 12, count 0 2006.257.09:35:41.53#ibcon#flushed, iclass 12, count 0 2006.257.09:35:41.53#ibcon#about to write, iclass 12, count 0 2006.257.09:35:41.53#ibcon#wrote, iclass 12, count 0 2006.257.09:35:41.53#ibcon#about to read 3, iclass 12, count 0 2006.257.09:35:41.56#ibcon#read 3, iclass 12, count 0 2006.257.09:35:41.56#ibcon#about to read 4, iclass 12, count 0 2006.257.09:35:41.56#ibcon#read 4, iclass 12, count 0 2006.257.09:35:41.56#ibcon#about to read 5, iclass 12, count 0 2006.257.09:35:41.56#ibcon#read 5, iclass 12, count 0 2006.257.09:35:41.56#ibcon#about to read 6, iclass 12, count 0 2006.257.09:35:41.56#ibcon#read 6, iclass 12, count 0 2006.257.09:35:41.56#ibcon#end of sib2, iclass 12, count 0 2006.257.09:35:41.56#ibcon#*after write, iclass 12, count 0 2006.257.09:35:41.56#ibcon#*before return 0, iclass 12, count 0 2006.257.09:35:41.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:41.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:41.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:35:41.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:35:41.56$vck44/valo=2,534.99 2006.257.09:35:41.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.09:35:41.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.09:35:41.56#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:41.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:41.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:41.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:41.56#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:35:41.56#ibcon#first serial, iclass 14, count 0 2006.257.09:35:41.56#ibcon#enter sib2, iclass 14, count 0 2006.257.09:35:41.56#ibcon#flushed, iclass 14, count 0 2006.257.09:35:41.56#ibcon#about to write, iclass 14, count 0 2006.257.09:35:41.56#ibcon#wrote, iclass 14, count 0 2006.257.09:35:41.56#ibcon#about to read 3, iclass 14, count 0 2006.257.09:35:41.58#ibcon#read 3, iclass 14, count 0 2006.257.09:35:41.58#ibcon#about to read 4, iclass 14, count 0 2006.257.09:35:41.58#ibcon#read 4, iclass 14, count 0 2006.257.09:35:41.58#ibcon#about to read 5, iclass 14, count 0 2006.257.09:35:41.58#ibcon#read 5, iclass 14, count 0 2006.257.09:35:41.58#ibcon#about to read 6, iclass 14, count 0 2006.257.09:35:41.58#ibcon#read 6, iclass 14, count 0 2006.257.09:35:41.58#ibcon#end of sib2, iclass 14, count 0 2006.257.09:35:41.58#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:35:41.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:35:41.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:35:41.58#ibcon#*before write, iclass 14, count 0 2006.257.09:35:41.58#ibcon#enter sib2, iclass 14, count 0 2006.257.09:35:41.58#ibcon#flushed, iclass 14, count 0 2006.257.09:35:41.58#ibcon#about to write, iclass 14, count 0 2006.257.09:35:41.58#ibcon#wrote, iclass 14, count 0 2006.257.09:35:41.58#ibcon#about to read 3, iclass 14, count 0 2006.257.09:35:41.62#ibcon#read 3, iclass 14, count 0 2006.257.09:35:41.62#ibcon#about to read 4, iclass 14, count 0 2006.257.09:35:41.62#ibcon#read 4, iclass 14, count 0 2006.257.09:35:41.62#ibcon#about to read 5, iclass 14, count 0 2006.257.09:35:41.62#ibcon#read 5, iclass 14, count 0 2006.257.09:35:41.62#ibcon#about to read 6, iclass 14, count 0 2006.257.09:35:41.62#ibcon#read 6, iclass 14, count 0 2006.257.09:35:41.62#ibcon#end of sib2, iclass 14, count 0 2006.257.09:35:41.62#ibcon#*after write, iclass 14, count 0 2006.257.09:35:41.62#ibcon#*before return 0, iclass 14, count 0 2006.257.09:35:41.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:41.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:41.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:35:41.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:35:41.62$vck44/va=2,7 2006.257.09:35:41.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.09:35:41.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.09:35:41.62#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:41.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:41.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:41.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:41.68#ibcon#enter wrdev, iclass 16, count 2 2006.257.09:35:41.68#ibcon#first serial, iclass 16, count 2 2006.257.09:35:41.68#ibcon#enter sib2, iclass 16, count 2 2006.257.09:35:41.68#ibcon#flushed, iclass 16, count 2 2006.257.09:35:41.68#ibcon#about to write, iclass 16, count 2 2006.257.09:35:41.68#ibcon#wrote, iclass 16, count 2 2006.257.09:35:41.68#ibcon#about to read 3, iclass 16, count 2 2006.257.09:35:41.70#ibcon#read 3, iclass 16, count 2 2006.257.09:35:41.70#ibcon#about to read 4, iclass 16, count 2 2006.257.09:35:41.70#ibcon#read 4, iclass 16, count 2 2006.257.09:35:41.70#ibcon#about to read 5, iclass 16, count 2 2006.257.09:35:41.70#ibcon#read 5, iclass 16, count 2 2006.257.09:35:41.70#ibcon#about to read 6, iclass 16, count 2 2006.257.09:35:41.70#ibcon#read 6, iclass 16, count 2 2006.257.09:35:41.70#ibcon#end of sib2, iclass 16, count 2 2006.257.09:35:41.70#ibcon#*mode == 0, iclass 16, count 2 2006.257.09:35:41.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.09:35:41.70#ibcon#[25=AT02-07\r\n] 2006.257.09:35:41.70#ibcon#*before write, iclass 16, count 2 2006.257.09:35:41.70#ibcon#enter sib2, iclass 16, count 2 2006.257.09:35:41.70#ibcon#flushed, iclass 16, count 2 2006.257.09:35:41.70#ibcon#about to write, iclass 16, count 2 2006.257.09:35:41.70#ibcon#wrote, iclass 16, count 2 2006.257.09:35:41.70#ibcon#about to read 3, iclass 16, count 2 2006.257.09:35:41.73#ibcon#read 3, iclass 16, count 2 2006.257.09:35:41.73#ibcon#about to read 4, iclass 16, count 2 2006.257.09:35:41.73#ibcon#read 4, iclass 16, count 2 2006.257.09:35:41.73#ibcon#about to read 5, iclass 16, count 2 2006.257.09:35:41.73#ibcon#read 5, iclass 16, count 2 2006.257.09:35:41.73#ibcon#about to read 6, iclass 16, count 2 2006.257.09:35:41.73#ibcon#read 6, iclass 16, count 2 2006.257.09:35:41.73#ibcon#end of sib2, iclass 16, count 2 2006.257.09:35:41.73#ibcon#*after write, iclass 16, count 2 2006.257.09:35:41.73#ibcon#*before return 0, iclass 16, count 2 2006.257.09:35:41.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:41.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:41.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.09:35:41.73#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:41.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:41.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:41.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:41.85#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:35:41.85#ibcon#first serial, iclass 16, count 0 2006.257.09:35:41.85#ibcon#enter sib2, iclass 16, count 0 2006.257.09:35:41.85#ibcon#flushed, iclass 16, count 0 2006.257.09:35:41.85#ibcon#about to write, iclass 16, count 0 2006.257.09:35:41.85#ibcon#wrote, iclass 16, count 0 2006.257.09:35:41.85#ibcon#about to read 3, iclass 16, count 0 2006.257.09:35:41.87#ibcon#read 3, iclass 16, count 0 2006.257.09:35:41.87#ibcon#about to read 4, iclass 16, count 0 2006.257.09:35:41.87#ibcon#read 4, iclass 16, count 0 2006.257.09:35:41.87#ibcon#about to read 5, iclass 16, count 0 2006.257.09:35:41.87#ibcon#read 5, iclass 16, count 0 2006.257.09:35:41.87#ibcon#about to read 6, iclass 16, count 0 2006.257.09:35:41.87#ibcon#read 6, iclass 16, count 0 2006.257.09:35:41.87#ibcon#end of sib2, iclass 16, count 0 2006.257.09:35:41.87#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:35:41.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:35:41.87#ibcon#[25=USB\r\n] 2006.257.09:35:41.87#ibcon#*before write, iclass 16, count 0 2006.257.09:35:41.87#ibcon#enter sib2, iclass 16, count 0 2006.257.09:35:41.87#ibcon#flushed, iclass 16, count 0 2006.257.09:35:41.87#ibcon#about to write, iclass 16, count 0 2006.257.09:35:41.87#ibcon#wrote, iclass 16, count 0 2006.257.09:35:41.87#ibcon#about to read 3, iclass 16, count 0 2006.257.09:35:41.90#ibcon#read 3, iclass 16, count 0 2006.257.09:35:41.90#ibcon#about to read 4, iclass 16, count 0 2006.257.09:35:41.90#ibcon#read 4, iclass 16, count 0 2006.257.09:35:41.90#ibcon#about to read 5, iclass 16, count 0 2006.257.09:35:41.90#ibcon#read 5, iclass 16, count 0 2006.257.09:35:41.90#ibcon#about to read 6, iclass 16, count 0 2006.257.09:35:41.90#ibcon#read 6, iclass 16, count 0 2006.257.09:35:41.90#ibcon#end of sib2, iclass 16, count 0 2006.257.09:35:41.90#ibcon#*after write, iclass 16, count 0 2006.257.09:35:41.90#ibcon#*before return 0, iclass 16, count 0 2006.257.09:35:41.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:41.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:41.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:35:41.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:35:41.90$vck44/valo=3,564.99 2006.257.09:35:41.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.09:35:41.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.09:35:41.90#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:41.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:41.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:41.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:41.90#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:35:41.90#ibcon#first serial, iclass 18, count 0 2006.257.09:35:41.90#ibcon#enter sib2, iclass 18, count 0 2006.257.09:35:41.90#ibcon#flushed, iclass 18, count 0 2006.257.09:35:41.90#ibcon#about to write, iclass 18, count 0 2006.257.09:35:41.90#ibcon#wrote, iclass 18, count 0 2006.257.09:35:41.90#ibcon#about to read 3, iclass 18, count 0 2006.257.09:35:41.92#ibcon#read 3, iclass 18, count 0 2006.257.09:35:41.92#ibcon#about to read 4, iclass 18, count 0 2006.257.09:35:41.92#ibcon#read 4, iclass 18, count 0 2006.257.09:35:41.92#ibcon#about to read 5, iclass 18, count 0 2006.257.09:35:41.92#ibcon#read 5, iclass 18, count 0 2006.257.09:35:41.92#ibcon#about to read 6, iclass 18, count 0 2006.257.09:35:41.92#ibcon#read 6, iclass 18, count 0 2006.257.09:35:41.92#ibcon#end of sib2, iclass 18, count 0 2006.257.09:35:41.92#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:35:41.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:35:41.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:35:41.92#ibcon#*before write, iclass 18, count 0 2006.257.09:35:41.92#ibcon#enter sib2, iclass 18, count 0 2006.257.09:35:41.92#ibcon#flushed, iclass 18, count 0 2006.257.09:35:41.92#ibcon#about to write, iclass 18, count 0 2006.257.09:35:41.92#ibcon#wrote, iclass 18, count 0 2006.257.09:35:41.92#ibcon#about to read 3, iclass 18, count 0 2006.257.09:35:41.96#ibcon#read 3, iclass 18, count 0 2006.257.09:35:41.96#ibcon#about to read 4, iclass 18, count 0 2006.257.09:35:41.96#ibcon#read 4, iclass 18, count 0 2006.257.09:35:41.96#ibcon#about to read 5, iclass 18, count 0 2006.257.09:35:41.96#ibcon#read 5, iclass 18, count 0 2006.257.09:35:41.96#ibcon#about to read 6, iclass 18, count 0 2006.257.09:35:41.96#ibcon#read 6, iclass 18, count 0 2006.257.09:35:41.96#ibcon#end of sib2, iclass 18, count 0 2006.257.09:35:41.96#ibcon#*after write, iclass 18, count 0 2006.257.09:35:41.96#ibcon#*before return 0, iclass 18, count 0 2006.257.09:35:41.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:41.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:41.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:35:41.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:35:41.96$vck44/va=3,8 2006.257.09:35:41.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.09:35:41.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.09:35:41.96#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:41.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:42.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:42.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:42.02#ibcon#enter wrdev, iclass 20, count 2 2006.257.09:35:42.02#ibcon#first serial, iclass 20, count 2 2006.257.09:35:42.02#ibcon#enter sib2, iclass 20, count 2 2006.257.09:35:42.02#ibcon#flushed, iclass 20, count 2 2006.257.09:35:42.02#ibcon#about to write, iclass 20, count 2 2006.257.09:35:42.02#ibcon#wrote, iclass 20, count 2 2006.257.09:35:42.02#ibcon#about to read 3, iclass 20, count 2 2006.257.09:35:42.04#ibcon#read 3, iclass 20, count 2 2006.257.09:35:42.04#ibcon#about to read 4, iclass 20, count 2 2006.257.09:35:42.04#ibcon#read 4, iclass 20, count 2 2006.257.09:35:42.04#ibcon#about to read 5, iclass 20, count 2 2006.257.09:35:42.04#ibcon#read 5, iclass 20, count 2 2006.257.09:35:42.04#ibcon#about to read 6, iclass 20, count 2 2006.257.09:35:42.04#ibcon#read 6, iclass 20, count 2 2006.257.09:35:42.04#ibcon#end of sib2, iclass 20, count 2 2006.257.09:35:42.04#ibcon#*mode == 0, iclass 20, count 2 2006.257.09:35:42.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.09:35:42.04#ibcon#[25=AT03-08\r\n] 2006.257.09:35:42.04#ibcon#*before write, iclass 20, count 2 2006.257.09:35:42.04#ibcon#enter sib2, iclass 20, count 2 2006.257.09:35:42.04#ibcon#flushed, iclass 20, count 2 2006.257.09:35:42.04#ibcon#about to write, iclass 20, count 2 2006.257.09:35:42.04#ibcon#wrote, iclass 20, count 2 2006.257.09:35:42.04#ibcon#about to read 3, iclass 20, count 2 2006.257.09:35:42.07#ibcon#read 3, iclass 20, count 2 2006.257.09:35:42.07#ibcon#about to read 4, iclass 20, count 2 2006.257.09:35:42.07#ibcon#read 4, iclass 20, count 2 2006.257.09:35:42.07#ibcon#about to read 5, iclass 20, count 2 2006.257.09:35:42.07#ibcon#read 5, iclass 20, count 2 2006.257.09:35:42.07#ibcon#about to read 6, iclass 20, count 2 2006.257.09:35:42.07#ibcon#read 6, iclass 20, count 2 2006.257.09:35:42.07#ibcon#end of sib2, iclass 20, count 2 2006.257.09:35:42.07#ibcon#*after write, iclass 20, count 2 2006.257.09:35:42.07#ibcon#*before return 0, iclass 20, count 2 2006.257.09:35:42.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:42.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:42.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.09:35:42.07#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:42.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:42.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:42.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:42.19#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:35:42.19#ibcon#first serial, iclass 20, count 0 2006.257.09:35:42.19#ibcon#enter sib2, iclass 20, count 0 2006.257.09:35:42.19#ibcon#flushed, iclass 20, count 0 2006.257.09:35:42.19#ibcon#about to write, iclass 20, count 0 2006.257.09:35:42.19#ibcon#wrote, iclass 20, count 0 2006.257.09:35:42.19#ibcon#about to read 3, iclass 20, count 0 2006.257.09:35:42.21#ibcon#read 3, iclass 20, count 0 2006.257.09:35:42.21#ibcon#about to read 4, iclass 20, count 0 2006.257.09:35:42.21#ibcon#read 4, iclass 20, count 0 2006.257.09:35:42.21#ibcon#about to read 5, iclass 20, count 0 2006.257.09:35:42.21#ibcon#read 5, iclass 20, count 0 2006.257.09:35:42.21#ibcon#about to read 6, iclass 20, count 0 2006.257.09:35:42.21#ibcon#read 6, iclass 20, count 0 2006.257.09:35:42.21#ibcon#end of sib2, iclass 20, count 0 2006.257.09:35:42.21#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:35:42.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:35:42.21#ibcon#[25=USB\r\n] 2006.257.09:35:42.21#ibcon#*before write, iclass 20, count 0 2006.257.09:35:42.21#ibcon#enter sib2, iclass 20, count 0 2006.257.09:35:42.21#ibcon#flushed, iclass 20, count 0 2006.257.09:35:42.21#ibcon#about to write, iclass 20, count 0 2006.257.09:35:42.21#ibcon#wrote, iclass 20, count 0 2006.257.09:35:42.21#ibcon#about to read 3, iclass 20, count 0 2006.257.09:35:42.24#ibcon#read 3, iclass 20, count 0 2006.257.09:35:42.24#ibcon#about to read 4, iclass 20, count 0 2006.257.09:35:42.24#ibcon#read 4, iclass 20, count 0 2006.257.09:35:42.24#ibcon#about to read 5, iclass 20, count 0 2006.257.09:35:42.24#ibcon#read 5, iclass 20, count 0 2006.257.09:35:42.24#ibcon#about to read 6, iclass 20, count 0 2006.257.09:35:42.24#ibcon#read 6, iclass 20, count 0 2006.257.09:35:42.24#ibcon#end of sib2, iclass 20, count 0 2006.257.09:35:42.24#ibcon#*after write, iclass 20, count 0 2006.257.09:35:42.24#ibcon#*before return 0, iclass 20, count 0 2006.257.09:35:42.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:42.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:42.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:35:42.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:35:42.24$vck44/valo=4,624.99 2006.257.09:35:42.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.09:35:42.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.09:35:42.24#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:42.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:42.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:42.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:42.24#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:35:42.24#ibcon#first serial, iclass 22, count 0 2006.257.09:35:42.24#ibcon#enter sib2, iclass 22, count 0 2006.257.09:35:42.24#ibcon#flushed, iclass 22, count 0 2006.257.09:35:42.24#ibcon#about to write, iclass 22, count 0 2006.257.09:35:42.24#ibcon#wrote, iclass 22, count 0 2006.257.09:35:42.24#ibcon#about to read 3, iclass 22, count 0 2006.257.09:35:42.26#ibcon#read 3, iclass 22, count 0 2006.257.09:35:42.26#ibcon#about to read 4, iclass 22, count 0 2006.257.09:35:42.26#ibcon#read 4, iclass 22, count 0 2006.257.09:35:42.26#ibcon#about to read 5, iclass 22, count 0 2006.257.09:35:42.26#ibcon#read 5, iclass 22, count 0 2006.257.09:35:42.26#ibcon#about to read 6, iclass 22, count 0 2006.257.09:35:42.26#ibcon#read 6, iclass 22, count 0 2006.257.09:35:42.26#ibcon#end of sib2, iclass 22, count 0 2006.257.09:35:42.26#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:35:42.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:35:42.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:35:42.26#ibcon#*before write, iclass 22, count 0 2006.257.09:35:42.26#ibcon#enter sib2, iclass 22, count 0 2006.257.09:35:42.26#ibcon#flushed, iclass 22, count 0 2006.257.09:35:42.26#ibcon#about to write, iclass 22, count 0 2006.257.09:35:42.26#ibcon#wrote, iclass 22, count 0 2006.257.09:35:42.26#ibcon#about to read 3, iclass 22, count 0 2006.257.09:35:42.30#ibcon#read 3, iclass 22, count 0 2006.257.09:35:42.30#ibcon#about to read 4, iclass 22, count 0 2006.257.09:35:42.30#ibcon#read 4, iclass 22, count 0 2006.257.09:35:42.30#ibcon#about to read 5, iclass 22, count 0 2006.257.09:35:42.30#ibcon#read 5, iclass 22, count 0 2006.257.09:35:42.30#ibcon#about to read 6, iclass 22, count 0 2006.257.09:35:42.30#ibcon#read 6, iclass 22, count 0 2006.257.09:35:42.30#ibcon#end of sib2, iclass 22, count 0 2006.257.09:35:42.30#ibcon#*after write, iclass 22, count 0 2006.257.09:35:42.30#ibcon#*before return 0, iclass 22, count 0 2006.257.09:35:42.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:42.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:42.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:35:42.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:35:42.30$vck44/va=4,7 2006.257.09:35:42.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.09:35:42.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.09:35:42.30#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:42.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:42.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:42.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:42.36#ibcon#enter wrdev, iclass 24, count 2 2006.257.09:35:42.36#ibcon#first serial, iclass 24, count 2 2006.257.09:35:42.36#ibcon#enter sib2, iclass 24, count 2 2006.257.09:35:42.36#ibcon#flushed, iclass 24, count 2 2006.257.09:35:42.36#ibcon#about to write, iclass 24, count 2 2006.257.09:35:42.36#ibcon#wrote, iclass 24, count 2 2006.257.09:35:42.36#ibcon#about to read 3, iclass 24, count 2 2006.257.09:35:42.38#ibcon#read 3, iclass 24, count 2 2006.257.09:35:42.38#ibcon#about to read 4, iclass 24, count 2 2006.257.09:35:42.38#ibcon#read 4, iclass 24, count 2 2006.257.09:35:42.38#ibcon#about to read 5, iclass 24, count 2 2006.257.09:35:42.38#ibcon#read 5, iclass 24, count 2 2006.257.09:35:42.38#ibcon#about to read 6, iclass 24, count 2 2006.257.09:35:42.38#ibcon#read 6, iclass 24, count 2 2006.257.09:35:42.38#ibcon#end of sib2, iclass 24, count 2 2006.257.09:35:42.38#ibcon#*mode == 0, iclass 24, count 2 2006.257.09:35:42.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.09:35:42.38#ibcon#[25=AT04-07\r\n] 2006.257.09:35:42.38#ibcon#*before write, iclass 24, count 2 2006.257.09:35:42.38#ibcon#enter sib2, iclass 24, count 2 2006.257.09:35:42.38#ibcon#flushed, iclass 24, count 2 2006.257.09:35:42.38#ibcon#about to write, iclass 24, count 2 2006.257.09:35:42.38#ibcon#wrote, iclass 24, count 2 2006.257.09:35:42.38#ibcon#about to read 3, iclass 24, count 2 2006.257.09:35:42.41#ibcon#read 3, iclass 24, count 2 2006.257.09:35:42.41#ibcon#about to read 4, iclass 24, count 2 2006.257.09:35:42.41#ibcon#read 4, iclass 24, count 2 2006.257.09:35:42.41#ibcon#about to read 5, iclass 24, count 2 2006.257.09:35:42.41#ibcon#read 5, iclass 24, count 2 2006.257.09:35:42.41#ibcon#about to read 6, iclass 24, count 2 2006.257.09:35:42.41#ibcon#read 6, iclass 24, count 2 2006.257.09:35:42.41#ibcon#end of sib2, iclass 24, count 2 2006.257.09:35:42.41#ibcon#*after write, iclass 24, count 2 2006.257.09:35:42.41#ibcon#*before return 0, iclass 24, count 2 2006.257.09:35:42.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:42.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:42.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.09:35:42.41#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:42.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:42.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:42.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:42.53#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:35:42.53#ibcon#first serial, iclass 24, count 0 2006.257.09:35:42.53#ibcon#enter sib2, iclass 24, count 0 2006.257.09:35:42.53#ibcon#flushed, iclass 24, count 0 2006.257.09:35:42.53#ibcon#about to write, iclass 24, count 0 2006.257.09:35:42.53#ibcon#wrote, iclass 24, count 0 2006.257.09:35:42.53#ibcon#about to read 3, iclass 24, count 0 2006.257.09:35:42.55#ibcon#read 3, iclass 24, count 0 2006.257.09:35:42.55#ibcon#about to read 4, iclass 24, count 0 2006.257.09:35:42.55#ibcon#read 4, iclass 24, count 0 2006.257.09:35:42.55#ibcon#about to read 5, iclass 24, count 0 2006.257.09:35:42.55#ibcon#read 5, iclass 24, count 0 2006.257.09:35:42.55#ibcon#about to read 6, iclass 24, count 0 2006.257.09:35:42.55#ibcon#read 6, iclass 24, count 0 2006.257.09:35:42.55#ibcon#end of sib2, iclass 24, count 0 2006.257.09:35:42.55#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:35:42.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:35:42.55#ibcon#[25=USB\r\n] 2006.257.09:35:42.55#ibcon#*before write, iclass 24, count 0 2006.257.09:35:42.55#ibcon#enter sib2, iclass 24, count 0 2006.257.09:35:42.55#ibcon#flushed, iclass 24, count 0 2006.257.09:35:42.55#ibcon#about to write, iclass 24, count 0 2006.257.09:35:42.55#ibcon#wrote, iclass 24, count 0 2006.257.09:35:42.55#ibcon#about to read 3, iclass 24, count 0 2006.257.09:35:42.58#ibcon#read 3, iclass 24, count 0 2006.257.09:35:42.58#ibcon#about to read 4, iclass 24, count 0 2006.257.09:35:42.58#ibcon#read 4, iclass 24, count 0 2006.257.09:35:42.58#ibcon#about to read 5, iclass 24, count 0 2006.257.09:35:42.58#ibcon#read 5, iclass 24, count 0 2006.257.09:35:42.58#ibcon#about to read 6, iclass 24, count 0 2006.257.09:35:42.58#ibcon#read 6, iclass 24, count 0 2006.257.09:35:42.58#ibcon#end of sib2, iclass 24, count 0 2006.257.09:35:42.58#ibcon#*after write, iclass 24, count 0 2006.257.09:35:42.58#ibcon#*before return 0, iclass 24, count 0 2006.257.09:35:42.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:42.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:42.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:35:42.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:35:42.58$vck44/valo=5,734.99 2006.257.09:35:42.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.09:35:42.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.09:35:42.58#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:42.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:42.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:42.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:42.58#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:35:42.58#ibcon#first serial, iclass 26, count 0 2006.257.09:35:42.58#ibcon#enter sib2, iclass 26, count 0 2006.257.09:35:42.58#ibcon#flushed, iclass 26, count 0 2006.257.09:35:42.58#ibcon#about to write, iclass 26, count 0 2006.257.09:35:42.58#ibcon#wrote, iclass 26, count 0 2006.257.09:35:42.58#ibcon#about to read 3, iclass 26, count 0 2006.257.09:35:42.60#ibcon#read 3, iclass 26, count 0 2006.257.09:35:42.60#ibcon#about to read 4, iclass 26, count 0 2006.257.09:35:42.60#ibcon#read 4, iclass 26, count 0 2006.257.09:35:42.60#ibcon#about to read 5, iclass 26, count 0 2006.257.09:35:42.60#ibcon#read 5, iclass 26, count 0 2006.257.09:35:42.60#ibcon#about to read 6, iclass 26, count 0 2006.257.09:35:42.60#ibcon#read 6, iclass 26, count 0 2006.257.09:35:42.60#ibcon#end of sib2, iclass 26, count 0 2006.257.09:35:42.60#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:35:42.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:35:42.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:35:42.60#ibcon#*before write, iclass 26, count 0 2006.257.09:35:42.60#ibcon#enter sib2, iclass 26, count 0 2006.257.09:35:42.60#ibcon#flushed, iclass 26, count 0 2006.257.09:35:42.60#ibcon#about to write, iclass 26, count 0 2006.257.09:35:42.60#ibcon#wrote, iclass 26, count 0 2006.257.09:35:42.60#ibcon#about to read 3, iclass 26, count 0 2006.257.09:35:42.64#ibcon#read 3, iclass 26, count 0 2006.257.09:35:42.64#ibcon#about to read 4, iclass 26, count 0 2006.257.09:35:42.64#ibcon#read 4, iclass 26, count 0 2006.257.09:35:42.64#ibcon#about to read 5, iclass 26, count 0 2006.257.09:35:42.64#ibcon#read 5, iclass 26, count 0 2006.257.09:35:42.64#ibcon#about to read 6, iclass 26, count 0 2006.257.09:35:42.64#ibcon#read 6, iclass 26, count 0 2006.257.09:35:42.64#ibcon#end of sib2, iclass 26, count 0 2006.257.09:35:42.64#ibcon#*after write, iclass 26, count 0 2006.257.09:35:42.64#ibcon#*before return 0, iclass 26, count 0 2006.257.09:35:42.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:42.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:42.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:35:42.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:35:42.64$vck44/va=5,4 2006.257.09:35:42.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.09:35:42.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.09:35:42.64#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:42.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:42.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:42.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:42.70#ibcon#enter wrdev, iclass 28, count 2 2006.257.09:35:42.70#ibcon#first serial, iclass 28, count 2 2006.257.09:35:42.70#ibcon#enter sib2, iclass 28, count 2 2006.257.09:35:42.70#ibcon#flushed, iclass 28, count 2 2006.257.09:35:42.70#ibcon#about to write, iclass 28, count 2 2006.257.09:35:42.70#ibcon#wrote, iclass 28, count 2 2006.257.09:35:42.70#ibcon#about to read 3, iclass 28, count 2 2006.257.09:35:42.72#ibcon#read 3, iclass 28, count 2 2006.257.09:35:42.72#ibcon#about to read 4, iclass 28, count 2 2006.257.09:35:42.72#ibcon#read 4, iclass 28, count 2 2006.257.09:35:42.72#ibcon#about to read 5, iclass 28, count 2 2006.257.09:35:42.72#ibcon#read 5, iclass 28, count 2 2006.257.09:35:42.72#ibcon#about to read 6, iclass 28, count 2 2006.257.09:35:42.72#ibcon#read 6, iclass 28, count 2 2006.257.09:35:42.72#ibcon#end of sib2, iclass 28, count 2 2006.257.09:35:42.72#ibcon#*mode == 0, iclass 28, count 2 2006.257.09:35:42.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.09:35:42.72#ibcon#[25=AT05-04\r\n] 2006.257.09:35:42.72#ibcon#*before write, iclass 28, count 2 2006.257.09:35:42.72#ibcon#enter sib2, iclass 28, count 2 2006.257.09:35:42.72#ibcon#flushed, iclass 28, count 2 2006.257.09:35:42.72#ibcon#about to write, iclass 28, count 2 2006.257.09:35:42.72#ibcon#wrote, iclass 28, count 2 2006.257.09:35:42.72#ibcon#about to read 3, iclass 28, count 2 2006.257.09:35:42.75#ibcon#read 3, iclass 28, count 2 2006.257.09:35:42.75#ibcon#about to read 4, iclass 28, count 2 2006.257.09:35:42.75#ibcon#read 4, iclass 28, count 2 2006.257.09:35:42.75#ibcon#about to read 5, iclass 28, count 2 2006.257.09:35:42.75#ibcon#read 5, iclass 28, count 2 2006.257.09:35:42.75#ibcon#about to read 6, iclass 28, count 2 2006.257.09:35:42.75#ibcon#read 6, iclass 28, count 2 2006.257.09:35:42.75#ibcon#end of sib2, iclass 28, count 2 2006.257.09:35:42.75#ibcon#*after write, iclass 28, count 2 2006.257.09:35:42.75#ibcon#*before return 0, iclass 28, count 2 2006.257.09:35:42.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:42.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:42.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.09:35:42.75#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:42.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:42.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:42.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:42.87#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:35:42.87#ibcon#first serial, iclass 28, count 0 2006.257.09:35:42.87#ibcon#enter sib2, iclass 28, count 0 2006.257.09:35:42.87#ibcon#flushed, iclass 28, count 0 2006.257.09:35:42.87#ibcon#about to write, iclass 28, count 0 2006.257.09:35:42.87#ibcon#wrote, iclass 28, count 0 2006.257.09:35:42.87#ibcon#about to read 3, iclass 28, count 0 2006.257.09:35:42.89#ibcon#read 3, iclass 28, count 0 2006.257.09:35:42.89#ibcon#about to read 4, iclass 28, count 0 2006.257.09:35:42.89#ibcon#read 4, iclass 28, count 0 2006.257.09:35:42.89#ibcon#about to read 5, iclass 28, count 0 2006.257.09:35:42.89#ibcon#read 5, iclass 28, count 0 2006.257.09:35:42.89#ibcon#about to read 6, iclass 28, count 0 2006.257.09:35:42.89#ibcon#read 6, iclass 28, count 0 2006.257.09:35:42.89#ibcon#end of sib2, iclass 28, count 0 2006.257.09:35:42.89#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:35:42.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:35:42.89#ibcon#[25=USB\r\n] 2006.257.09:35:42.89#ibcon#*before write, iclass 28, count 0 2006.257.09:35:42.89#ibcon#enter sib2, iclass 28, count 0 2006.257.09:35:42.89#ibcon#flushed, iclass 28, count 0 2006.257.09:35:42.89#ibcon#about to write, iclass 28, count 0 2006.257.09:35:42.89#ibcon#wrote, iclass 28, count 0 2006.257.09:35:42.89#ibcon#about to read 3, iclass 28, count 0 2006.257.09:35:42.92#ibcon#read 3, iclass 28, count 0 2006.257.09:35:42.92#ibcon#about to read 4, iclass 28, count 0 2006.257.09:35:42.92#ibcon#read 4, iclass 28, count 0 2006.257.09:35:42.92#ibcon#about to read 5, iclass 28, count 0 2006.257.09:35:42.92#ibcon#read 5, iclass 28, count 0 2006.257.09:35:42.92#ibcon#about to read 6, iclass 28, count 0 2006.257.09:35:42.92#ibcon#read 6, iclass 28, count 0 2006.257.09:35:42.92#ibcon#end of sib2, iclass 28, count 0 2006.257.09:35:42.92#ibcon#*after write, iclass 28, count 0 2006.257.09:35:42.92#ibcon#*before return 0, iclass 28, count 0 2006.257.09:35:42.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:42.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:42.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:35:42.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:35:42.92$vck44/valo=6,814.99 2006.257.09:35:42.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.09:35:42.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.09:35:42.92#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:42.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:35:42.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:35:42.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:35:42.92#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:35:42.92#ibcon#first serial, iclass 30, count 0 2006.257.09:35:42.92#ibcon#enter sib2, iclass 30, count 0 2006.257.09:35:42.92#ibcon#flushed, iclass 30, count 0 2006.257.09:35:42.92#ibcon#about to write, iclass 30, count 0 2006.257.09:35:42.92#ibcon#wrote, iclass 30, count 0 2006.257.09:35:42.92#ibcon#about to read 3, iclass 30, count 0 2006.257.09:35:42.94#ibcon#read 3, iclass 30, count 0 2006.257.09:35:42.94#ibcon#about to read 4, iclass 30, count 0 2006.257.09:35:42.94#ibcon#read 4, iclass 30, count 0 2006.257.09:35:42.94#ibcon#about to read 5, iclass 30, count 0 2006.257.09:35:42.94#ibcon#read 5, iclass 30, count 0 2006.257.09:35:42.94#ibcon#about to read 6, iclass 30, count 0 2006.257.09:35:42.94#ibcon#read 6, iclass 30, count 0 2006.257.09:35:42.94#ibcon#end of sib2, iclass 30, count 0 2006.257.09:35:42.94#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:35:42.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:35:42.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:35:42.94#ibcon#*before write, iclass 30, count 0 2006.257.09:35:42.94#ibcon#enter sib2, iclass 30, count 0 2006.257.09:35:42.94#ibcon#flushed, iclass 30, count 0 2006.257.09:35:42.94#ibcon#about to write, iclass 30, count 0 2006.257.09:35:42.94#ibcon#wrote, iclass 30, count 0 2006.257.09:35:42.94#ibcon#about to read 3, iclass 30, count 0 2006.257.09:35:42.98#ibcon#read 3, iclass 30, count 0 2006.257.09:35:42.98#ibcon#about to read 4, iclass 30, count 0 2006.257.09:35:42.98#ibcon#read 4, iclass 30, count 0 2006.257.09:35:42.98#ibcon#about to read 5, iclass 30, count 0 2006.257.09:35:42.98#ibcon#read 5, iclass 30, count 0 2006.257.09:35:42.98#ibcon#about to read 6, iclass 30, count 0 2006.257.09:35:42.98#ibcon#read 6, iclass 30, count 0 2006.257.09:35:42.98#ibcon#end of sib2, iclass 30, count 0 2006.257.09:35:42.98#ibcon#*after write, iclass 30, count 0 2006.257.09:35:42.98#ibcon#*before return 0, iclass 30, count 0 2006.257.09:35:42.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:35:42.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:35:42.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:35:42.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:35:42.98$vck44/va=6,4 2006.257.09:35:42.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.09:35:42.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.09:35:42.98#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:42.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:35:43.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:35:43.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:35:43.04#ibcon#enter wrdev, iclass 32, count 2 2006.257.09:35:43.04#ibcon#first serial, iclass 32, count 2 2006.257.09:35:43.04#ibcon#enter sib2, iclass 32, count 2 2006.257.09:35:43.04#ibcon#flushed, iclass 32, count 2 2006.257.09:35:43.04#ibcon#about to write, iclass 32, count 2 2006.257.09:35:43.04#ibcon#wrote, iclass 32, count 2 2006.257.09:35:43.04#ibcon#about to read 3, iclass 32, count 2 2006.257.09:35:43.06#ibcon#read 3, iclass 32, count 2 2006.257.09:35:43.06#ibcon#about to read 4, iclass 32, count 2 2006.257.09:35:43.06#ibcon#read 4, iclass 32, count 2 2006.257.09:35:43.06#ibcon#about to read 5, iclass 32, count 2 2006.257.09:35:43.06#ibcon#read 5, iclass 32, count 2 2006.257.09:35:43.06#ibcon#about to read 6, iclass 32, count 2 2006.257.09:35:43.06#ibcon#read 6, iclass 32, count 2 2006.257.09:35:43.06#ibcon#end of sib2, iclass 32, count 2 2006.257.09:35:43.06#ibcon#*mode == 0, iclass 32, count 2 2006.257.09:35:43.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.09:35:43.06#ibcon#[25=AT06-04\r\n] 2006.257.09:35:43.06#ibcon#*before write, iclass 32, count 2 2006.257.09:35:43.06#ibcon#enter sib2, iclass 32, count 2 2006.257.09:35:43.06#ibcon#flushed, iclass 32, count 2 2006.257.09:35:43.06#ibcon#about to write, iclass 32, count 2 2006.257.09:35:43.06#ibcon#wrote, iclass 32, count 2 2006.257.09:35:43.06#ibcon#about to read 3, iclass 32, count 2 2006.257.09:35:43.09#ibcon#read 3, iclass 32, count 2 2006.257.09:35:43.09#ibcon#about to read 4, iclass 32, count 2 2006.257.09:35:43.09#ibcon#read 4, iclass 32, count 2 2006.257.09:35:43.09#ibcon#about to read 5, iclass 32, count 2 2006.257.09:35:43.09#ibcon#read 5, iclass 32, count 2 2006.257.09:35:43.09#ibcon#about to read 6, iclass 32, count 2 2006.257.09:35:43.09#ibcon#read 6, iclass 32, count 2 2006.257.09:35:43.09#ibcon#end of sib2, iclass 32, count 2 2006.257.09:35:43.09#ibcon#*after write, iclass 32, count 2 2006.257.09:35:43.09#ibcon#*before return 0, iclass 32, count 2 2006.257.09:35:43.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:35:43.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:35:43.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.09:35:43.09#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:43.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:35:43.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:35:43.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:35:43.21#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:35:43.21#ibcon#first serial, iclass 32, count 0 2006.257.09:35:43.21#ibcon#enter sib2, iclass 32, count 0 2006.257.09:35:43.21#ibcon#flushed, iclass 32, count 0 2006.257.09:35:43.21#ibcon#about to write, iclass 32, count 0 2006.257.09:35:43.21#ibcon#wrote, iclass 32, count 0 2006.257.09:35:43.21#ibcon#about to read 3, iclass 32, count 0 2006.257.09:35:43.23#ibcon#read 3, iclass 32, count 0 2006.257.09:35:43.23#ibcon#about to read 4, iclass 32, count 0 2006.257.09:35:43.23#ibcon#read 4, iclass 32, count 0 2006.257.09:35:43.23#ibcon#about to read 5, iclass 32, count 0 2006.257.09:35:43.23#ibcon#read 5, iclass 32, count 0 2006.257.09:35:43.23#ibcon#about to read 6, iclass 32, count 0 2006.257.09:35:43.23#ibcon#read 6, iclass 32, count 0 2006.257.09:35:43.23#ibcon#end of sib2, iclass 32, count 0 2006.257.09:35:43.23#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:35:43.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:35:43.23#ibcon#[25=USB\r\n] 2006.257.09:35:43.23#ibcon#*before write, iclass 32, count 0 2006.257.09:35:43.23#ibcon#enter sib2, iclass 32, count 0 2006.257.09:35:43.23#ibcon#flushed, iclass 32, count 0 2006.257.09:35:43.23#ibcon#about to write, iclass 32, count 0 2006.257.09:35:43.23#ibcon#wrote, iclass 32, count 0 2006.257.09:35:43.23#ibcon#about to read 3, iclass 32, count 0 2006.257.09:35:43.26#ibcon#read 3, iclass 32, count 0 2006.257.09:35:43.26#ibcon#about to read 4, iclass 32, count 0 2006.257.09:35:43.26#ibcon#read 4, iclass 32, count 0 2006.257.09:35:43.26#ibcon#about to read 5, iclass 32, count 0 2006.257.09:35:43.26#ibcon#read 5, iclass 32, count 0 2006.257.09:35:43.26#ibcon#about to read 6, iclass 32, count 0 2006.257.09:35:43.26#ibcon#read 6, iclass 32, count 0 2006.257.09:35:43.26#ibcon#end of sib2, iclass 32, count 0 2006.257.09:35:43.26#ibcon#*after write, iclass 32, count 0 2006.257.09:35:43.26#ibcon#*before return 0, iclass 32, count 0 2006.257.09:35:43.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:35:43.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:35:43.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:35:43.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:35:43.26$vck44/valo=7,864.99 2006.257.09:35:43.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.09:35:43.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.09:35:43.26#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:43.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:43.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:43.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:43.26#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:35:43.26#ibcon#first serial, iclass 34, count 0 2006.257.09:35:43.26#ibcon#enter sib2, iclass 34, count 0 2006.257.09:35:43.26#ibcon#flushed, iclass 34, count 0 2006.257.09:35:43.26#ibcon#about to write, iclass 34, count 0 2006.257.09:35:43.26#ibcon#wrote, iclass 34, count 0 2006.257.09:35:43.26#ibcon#about to read 3, iclass 34, count 0 2006.257.09:35:43.28#ibcon#read 3, iclass 34, count 0 2006.257.09:35:43.28#ibcon#about to read 4, iclass 34, count 0 2006.257.09:35:43.28#ibcon#read 4, iclass 34, count 0 2006.257.09:35:43.28#ibcon#about to read 5, iclass 34, count 0 2006.257.09:35:43.28#ibcon#read 5, iclass 34, count 0 2006.257.09:35:43.28#ibcon#about to read 6, iclass 34, count 0 2006.257.09:35:43.28#ibcon#read 6, iclass 34, count 0 2006.257.09:35:43.28#ibcon#end of sib2, iclass 34, count 0 2006.257.09:35:43.28#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:35:43.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:35:43.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:35:43.28#ibcon#*before write, iclass 34, count 0 2006.257.09:35:43.28#ibcon#enter sib2, iclass 34, count 0 2006.257.09:35:43.28#ibcon#flushed, iclass 34, count 0 2006.257.09:35:43.28#ibcon#about to write, iclass 34, count 0 2006.257.09:35:43.28#ibcon#wrote, iclass 34, count 0 2006.257.09:35:43.28#ibcon#about to read 3, iclass 34, count 0 2006.257.09:35:43.32#ibcon#read 3, iclass 34, count 0 2006.257.09:35:43.32#ibcon#about to read 4, iclass 34, count 0 2006.257.09:35:43.32#ibcon#read 4, iclass 34, count 0 2006.257.09:35:43.32#ibcon#about to read 5, iclass 34, count 0 2006.257.09:35:43.32#ibcon#read 5, iclass 34, count 0 2006.257.09:35:43.32#ibcon#about to read 6, iclass 34, count 0 2006.257.09:35:43.32#ibcon#read 6, iclass 34, count 0 2006.257.09:35:43.32#ibcon#end of sib2, iclass 34, count 0 2006.257.09:35:43.32#ibcon#*after write, iclass 34, count 0 2006.257.09:35:43.32#ibcon#*before return 0, iclass 34, count 0 2006.257.09:35:43.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:43.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:43.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:35:43.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:35:43.32$vck44/va=7,4 2006.257.09:35:43.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.09:35:43.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.09:35:43.32#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:43.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:43.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:43.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:43.38#ibcon#enter wrdev, iclass 36, count 2 2006.257.09:35:43.38#ibcon#first serial, iclass 36, count 2 2006.257.09:35:43.38#ibcon#enter sib2, iclass 36, count 2 2006.257.09:35:43.38#ibcon#flushed, iclass 36, count 2 2006.257.09:35:43.38#ibcon#about to write, iclass 36, count 2 2006.257.09:35:43.38#ibcon#wrote, iclass 36, count 2 2006.257.09:35:43.38#ibcon#about to read 3, iclass 36, count 2 2006.257.09:35:43.40#ibcon#read 3, iclass 36, count 2 2006.257.09:35:43.40#ibcon#about to read 4, iclass 36, count 2 2006.257.09:35:43.40#ibcon#read 4, iclass 36, count 2 2006.257.09:35:43.40#ibcon#about to read 5, iclass 36, count 2 2006.257.09:35:43.40#ibcon#read 5, iclass 36, count 2 2006.257.09:35:43.40#ibcon#about to read 6, iclass 36, count 2 2006.257.09:35:43.40#ibcon#read 6, iclass 36, count 2 2006.257.09:35:43.40#ibcon#end of sib2, iclass 36, count 2 2006.257.09:35:43.40#ibcon#*mode == 0, iclass 36, count 2 2006.257.09:35:43.40#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.09:35:43.40#ibcon#[25=AT07-04\r\n] 2006.257.09:35:43.40#ibcon#*before write, iclass 36, count 2 2006.257.09:35:43.40#ibcon#enter sib2, iclass 36, count 2 2006.257.09:35:43.40#ibcon#flushed, iclass 36, count 2 2006.257.09:35:43.40#ibcon#about to write, iclass 36, count 2 2006.257.09:35:43.40#ibcon#wrote, iclass 36, count 2 2006.257.09:35:43.40#ibcon#about to read 3, iclass 36, count 2 2006.257.09:35:43.43#ibcon#read 3, iclass 36, count 2 2006.257.09:35:43.43#ibcon#about to read 4, iclass 36, count 2 2006.257.09:35:43.43#ibcon#read 4, iclass 36, count 2 2006.257.09:35:43.43#ibcon#about to read 5, iclass 36, count 2 2006.257.09:35:43.43#ibcon#read 5, iclass 36, count 2 2006.257.09:35:43.43#ibcon#about to read 6, iclass 36, count 2 2006.257.09:35:43.43#ibcon#read 6, iclass 36, count 2 2006.257.09:35:43.43#ibcon#end of sib2, iclass 36, count 2 2006.257.09:35:43.43#ibcon#*after write, iclass 36, count 2 2006.257.09:35:43.43#ibcon#*before return 0, iclass 36, count 2 2006.257.09:35:43.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:43.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:43.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.09:35:43.43#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:43.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:43.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:43.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:43.55#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:35:43.55#ibcon#first serial, iclass 36, count 0 2006.257.09:35:43.55#ibcon#enter sib2, iclass 36, count 0 2006.257.09:35:43.55#ibcon#flushed, iclass 36, count 0 2006.257.09:35:43.55#ibcon#about to write, iclass 36, count 0 2006.257.09:35:43.55#ibcon#wrote, iclass 36, count 0 2006.257.09:35:43.55#ibcon#about to read 3, iclass 36, count 0 2006.257.09:35:43.57#ibcon#read 3, iclass 36, count 0 2006.257.09:35:43.57#ibcon#about to read 4, iclass 36, count 0 2006.257.09:35:43.57#ibcon#read 4, iclass 36, count 0 2006.257.09:35:43.57#ibcon#about to read 5, iclass 36, count 0 2006.257.09:35:43.57#ibcon#read 5, iclass 36, count 0 2006.257.09:35:43.57#ibcon#about to read 6, iclass 36, count 0 2006.257.09:35:43.57#ibcon#read 6, iclass 36, count 0 2006.257.09:35:43.57#ibcon#end of sib2, iclass 36, count 0 2006.257.09:35:43.57#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:35:43.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:35:43.57#ibcon#[25=USB\r\n] 2006.257.09:35:43.57#ibcon#*before write, iclass 36, count 0 2006.257.09:35:43.57#ibcon#enter sib2, iclass 36, count 0 2006.257.09:35:43.57#ibcon#flushed, iclass 36, count 0 2006.257.09:35:43.57#ibcon#about to write, iclass 36, count 0 2006.257.09:35:43.57#ibcon#wrote, iclass 36, count 0 2006.257.09:35:43.57#ibcon#about to read 3, iclass 36, count 0 2006.257.09:35:43.60#ibcon#read 3, iclass 36, count 0 2006.257.09:35:43.60#ibcon#about to read 4, iclass 36, count 0 2006.257.09:35:43.60#ibcon#read 4, iclass 36, count 0 2006.257.09:35:43.60#ibcon#about to read 5, iclass 36, count 0 2006.257.09:35:43.60#ibcon#read 5, iclass 36, count 0 2006.257.09:35:43.60#ibcon#about to read 6, iclass 36, count 0 2006.257.09:35:43.60#ibcon#read 6, iclass 36, count 0 2006.257.09:35:43.60#ibcon#end of sib2, iclass 36, count 0 2006.257.09:35:43.60#ibcon#*after write, iclass 36, count 0 2006.257.09:35:43.60#ibcon#*before return 0, iclass 36, count 0 2006.257.09:35:43.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:43.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:43.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:35:43.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:35:43.60$vck44/valo=8,884.99 2006.257.09:35:43.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.09:35:43.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.09:35:43.60#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:43.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:43.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:43.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:43.60#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:35:43.60#ibcon#first serial, iclass 38, count 0 2006.257.09:35:43.60#ibcon#enter sib2, iclass 38, count 0 2006.257.09:35:43.60#ibcon#flushed, iclass 38, count 0 2006.257.09:35:43.60#ibcon#about to write, iclass 38, count 0 2006.257.09:35:43.60#ibcon#wrote, iclass 38, count 0 2006.257.09:35:43.60#ibcon#about to read 3, iclass 38, count 0 2006.257.09:35:43.62#ibcon#read 3, iclass 38, count 0 2006.257.09:35:43.62#ibcon#about to read 4, iclass 38, count 0 2006.257.09:35:43.62#ibcon#read 4, iclass 38, count 0 2006.257.09:35:43.62#ibcon#about to read 5, iclass 38, count 0 2006.257.09:35:43.62#ibcon#read 5, iclass 38, count 0 2006.257.09:35:43.62#ibcon#about to read 6, iclass 38, count 0 2006.257.09:35:43.62#ibcon#read 6, iclass 38, count 0 2006.257.09:35:43.62#ibcon#end of sib2, iclass 38, count 0 2006.257.09:35:43.62#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:35:43.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:35:43.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:35:43.62#ibcon#*before write, iclass 38, count 0 2006.257.09:35:43.62#ibcon#enter sib2, iclass 38, count 0 2006.257.09:35:43.62#ibcon#flushed, iclass 38, count 0 2006.257.09:35:43.62#ibcon#about to write, iclass 38, count 0 2006.257.09:35:43.62#ibcon#wrote, iclass 38, count 0 2006.257.09:35:43.62#ibcon#about to read 3, iclass 38, count 0 2006.257.09:35:43.66#ibcon#read 3, iclass 38, count 0 2006.257.09:35:43.66#ibcon#about to read 4, iclass 38, count 0 2006.257.09:35:43.66#ibcon#read 4, iclass 38, count 0 2006.257.09:35:43.66#ibcon#about to read 5, iclass 38, count 0 2006.257.09:35:43.66#ibcon#read 5, iclass 38, count 0 2006.257.09:35:43.66#ibcon#about to read 6, iclass 38, count 0 2006.257.09:35:43.66#ibcon#read 6, iclass 38, count 0 2006.257.09:35:43.66#ibcon#end of sib2, iclass 38, count 0 2006.257.09:35:43.66#ibcon#*after write, iclass 38, count 0 2006.257.09:35:43.66#ibcon#*before return 0, iclass 38, count 0 2006.257.09:35:43.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:43.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:43.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:35:43.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:35:43.66$vck44/va=8,4 2006.257.09:35:43.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.09:35:43.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.09:35:43.66#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:43.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:43.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:43.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:43.72#ibcon#enter wrdev, iclass 40, count 2 2006.257.09:35:43.72#ibcon#first serial, iclass 40, count 2 2006.257.09:35:43.72#ibcon#enter sib2, iclass 40, count 2 2006.257.09:35:43.72#ibcon#flushed, iclass 40, count 2 2006.257.09:35:43.72#ibcon#about to write, iclass 40, count 2 2006.257.09:35:43.72#ibcon#wrote, iclass 40, count 2 2006.257.09:35:43.72#ibcon#about to read 3, iclass 40, count 2 2006.257.09:35:43.74#ibcon#read 3, iclass 40, count 2 2006.257.09:35:43.74#ibcon#about to read 4, iclass 40, count 2 2006.257.09:35:43.74#ibcon#read 4, iclass 40, count 2 2006.257.09:35:43.74#ibcon#about to read 5, iclass 40, count 2 2006.257.09:35:43.74#ibcon#read 5, iclass 40, count 2 2006.257.09:35:43.74#ibcon#about to read 6, iclass 40, count 2 2006.257.09:35:43.74#ibcon#read 6, iclass 40, count 2 2006.257.09:35:43.74#ibcon#end of sib2, iclass 40, count 2 2006.257.09:35:43.74#ibcon#*mode == 0, iclass 40, count 2 2006.257.09:35:43.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.09:35:43.74#ibcon#[25=AT08-04\r\n] 2006.257.09:35:43.74#ibcon#*before write, iclass 40, count 2 2006.257.09:35:43.74#ibcon#enter sib2, iclass 40, count 2 2006.257.09:35:43.74#ibcon#flushed, iclass 40, count 2 2006.257.09:35:43.74#ibcon#about to write, iclass 40, count 2 2006.257.09:35:43.74#ibcon#wrote, iclass 40, count 2 2006.257.09:35:43.74#ibcon#about to read 3, iclass 40, count 2 2006.257.09:35:43.77#ibcon#read 3, iclass 40, count 2 2006.257.09:35:43.77#ibcon#about to read 4, iclass 40, count 2 2006.257.09:35:43.77#ibcon#read 4, iclass 40, count 2 2006.257.09:35:43.77#ibcon#about to read 5, iclass 40, count 2 2006.257.09:35:43.77#ibcon#read 5, iclass 40, count 2 2006.257.09:35:43.77#ibcon#about to read 6, iclass 40, count 2 2006.257.09:35:43.77#ibcon#read 6, iclass 40, count 2 2006.257.09:35:43.77#ibcon#end of sib2, iclass 40, count 2 2006.257.09:35:43.77#ibcon#*after write, iclass 40, count 2 2006.257.09:35:43.77#ibcon#*before return 0, iclass 40, count 2 2006.257.09:35:43.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:43.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:43.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.09:35:43.77#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:43.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:43.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:43.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:43.89#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:35:43.89#ibcon#first serial, iclass 40, count 0 2006.257.09:35:43.89#ibcon#enter sib2, iclass 40, count 0 2006.257.09:35:43.89#ibcon#flushed, iclass 40, count 0 2006.257.09:35:43.89#ibcon#about to write, iclass 40, count 0 2006.257.09:35:43.89#ibcon#wrote, iclass 40, count 0 2006.257.09:35:43.89#ibcon#about to read 3, iclass 40, count 0 2006.257.09:35:43.91#ibcon#read 3, iclass 40, count 0 2006.257.09:35:43.91#ibcon#about to read 4, iclass 40, count 0 2006.257.09:35:43.91#ibcon#read 4, iclass 40, count 0 2006.257.09:35:43.91#ibcon#about to read 5, iclass 40, count 0 2006.257.09:35:43.91#ibcon#read 5, iclass 40, count 0 2006.257.09:35:43.91#ibcon#about to read 6, iclass 40, count 0 2006.257.09:35:43.91#ibcon#read 6, iclass 40, count 0 2006.257.09:35:43.91#ibcon#end of sib2, iclass 40, count 0 2006.257.09:35:43.91#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:35:43.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:35:43.91#ibcon#[25=USB\r\n] 2006.257.09:35:43.91#ibcon#*before write, iclass 40, count 0 2006.257.09:35:43.91#ibcon#enter sib2, iclass 40, count 0 2006.257.09:35:43.91#ibcon#flushed, iclass 40, count 0 2006.257.09:35:43.91#ibcon#about to write, iclass 40, count 0 2006.257.09:35:43.91#ibcon#wrote, iclass 40, count 0 2006.257.09:35:43.91#ibcon#about to read 3, iclass 40, count 0 2006.257.09:35:43.94#ibcon#read 3, iclass 40, count 0 2006.257.09:35:43.94#ibcon#about to read 4, iclass 40, count 0 2006.257.09:35:43.94#ibcon#read 4, iclass 40, count 0 2006.257.09:35:43.94#ibcon#about to read 5, iclass 40, count 0 2006.257.09:35:43.94#ibcon#read 5, iclass 40, count 0 2006.257.09:35:43.94#ibcon#about to read 6, iclass 40, count 0 2006.257.09:35:43.94#ibcon#read 6, iclass 40, count 0 2006.257.09:35:43.94#ibcon#end of sib2, iclass 40, count 0 2006.257.09:35:43.94#ibcon#*after write, iclass 40, count 0 2006.257.09:35:43.94#ibcon#*before return 0, iclass 40, count 0 2006.257.09:35:43.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:43.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:43.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:35:43.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:35:43.94$vck44/vblo=1,629.99 2006.257.09:35:43.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.09:35:43.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.09:35:43.94#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:43.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:43.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:43.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:43.94#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:35:43.94#ibcon#first serial, iclass 4, count 0 2006.257.09:35:43.94#ibcon#enter sib2, iclass 4, count 0 2006.257.09:35:43.94#ibcon#flushed, iclass 4, count 0 2006.257.09:35:43.94#ibcon#about to write, iclass 4, count 0 2006.257.09:35:43.94#ibcon#wrote, iclass 4, count 0 2006.257.09:35:43.94#ibcon#about to read 3, iclass 4, count 0 2006.257.09:35:43.96#ibcon#read 3, iclass 4, count 0 2006.257.09:35:43.96#ibcon#about to read 4, iclass 4, count 0 2006.257.09:35:43.96#ibcon#read 4, iclass 4, count 0 2006.257.09:35:43.96#ibcon#about to read 5, iclass 4, count 0 2006.257.09:35:43.96#ibcon#read 5, iclass 4, count 0 2006.257.09:35:43.96#ibcon#about to read 6, iclass 4, count 0 2006.257.09:35:43.96#ibcon#read 6, iclass 4, count 0 2006.257.09:35:43.96#ibcon#end of sib2, iclass 4, count 0 2006.257.09:35:43.96#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:35:43.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:35:43.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:35:43.96#ibcon#*before write, iclass 4, count 0 2006.257.09:35:43.96#ibcon#enter sib2, iclass 4, count 0 2006.257.09:35:43.96#ibcon#flushed, iclass 4, count 0 2006.257.09:35:43.96#ibcon#about to write, iclass 4, count 0 2006.257.09:35:43.96#ibcon#wrote, iclass 4, count 0 2006.257.09:35:43.96#ibcon#about to read 3, iclass 4, count 0 2006.257.09:35:44.00#ibcon#read 3, iclass 4, count 0 2006.257.09:35:44.00#ibcon#about to read 4, iclass 4, count 0 2006.257.09:35:44.00#ibcon#read 4, iclass 4, count 0 2006.257.09:35:44.00#ibcon#about to read 5, iclass 4, count 0 2006.257.09:35:44.00#ibcon#read 5, iclass 4, count 0 2006.257.09:35:44.00#ibcon#about to read 6, iclass 4, count 0 2006.257.09:35:44.00#ibcon#read 6, iclass 4, count 0 2006.257.09:35:44.00#ibcon#end of sib2, iclass 4, count 0 2006.257.09:35:44.00#ibcon#*after write, iclass 4, count 0 2006.257.09:35:44.00#ibcon#*before return 0, iclass 4, count 0 2006.257.09:35:44.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:44.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:44.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:35:44.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:35:44.00$vck44/vb=1,4 2006.257.09:35:44.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.09:35:44.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.09:35:44.00#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:44.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:35:44.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:35:44.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:35:44.00#ibcon#enter wrdev, iclass 6, count 2 2006.257.09:35:44.00#ibcon#first serial, iclass 6, count 2 2006.257.09:35:44.00#ibcon#enter sib2, iclass 6, count 2 2006.257.09:35:44.00#ibcon#flushed, iclass 6, count 2 2006.257.09:35:44.00#ibcon#about to write, iclass 6, count 2 2006.257.09:35:44.00#ibcon#wrote, iclass 6, count 2 2006.257.09:35:44.00#ibcon#about to read 3, iclass 6, count 2 2006.257.09:35:44.02#ibcon#read 3, iclass 6, count 2 2006.257.09:35:44.02#ibcon#about to read 4, iclass 6, count 2 2006.257.09:35:44.02#ibcon#read 4, iclass 6, count 2 2006.257.09:35:44.02#ibcon#about to read 5, iclass 6, count 2 2006.257.09:35:44.02#ibcon#read 5, iclass 6, count 2 2006.257.09:35:44.02#ibcon#about to read 6, iclass 6, count 2 2006.257.09:35:44.02#ibcon#read 6, iclass 6, count 2 2006.257.09:35:44.02#ibcon#end of sib2, iclass 6, count 2 2006.257.09:35:44.02#ibcon#*mode == 0, iclass 6, count 2 2006.257.09:35:44.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.09:35:44.02#ibcon#[27=AT01-04\r\n] 2006.257.09:35:44.02#ibcon#*before write, iclass 6, count 2 2006.257.09:35:44.02#ibcon#enter sib2, iclass 6, count 2 2006.257.09:35:44.02#ibcon#flushed, iclass 6, count 2 2006.257.09:35:44.02#ibcon#about to write, iclass 6, count 2 2006.257.09:35:44.02#ibcon#wrote, iclass 6, count 2 2006.257.09:35:44.02#ibcon#about to read 3, iclass 6, count 2 2006.257.09:35:44.05#ibcon#read 3, iclass 6, count 2 2006.257.09:35:44.05#ibcon#about to read 4, iclass 6, count 2 2006.257.09:35:44.05#ibcon#read 4, iclass 6, count 2 2006.257.09:35:44.05#ibcon#about to read 5, iclass 6, count 2 2006.257.09:35:44.05#ibcon#read 5, iclass 6, count 2 2006.257.09:35:44.05#ibcon#about to read 6, iclass 6, count 2 2006.257.09:35:44.05#ibcon#read 6, iclass 6, count 2 2006.257.09:35:44.05#ibcon#end of sib2, iclass 6, count 2 2006.257.09:35:44.05#ibcon#*after write, iclass 6, count 2 2006.257.09:35:44.05#ibcon#*before return 0, iclass 6, count 2 2006.257.09:35:44.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:35:44.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:35:44.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.09:35:44.05#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:44.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:35:44.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:35:44.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:35:44.17#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:35:44.17#ibcon#first serial, iclass 6, count 0 2006.257.09:35:44.17#ibcon#enter sib2, iclass 6, count 0 2006.257.09:35:44.17#ibcon#flushed, iclass 6, count 0 2006.257.09:35:44.17#ibcon#about to write, iclass 6, count 0 2006.257.09:35:44.17#ibcon#wrote, iclass 6, count 0 2006.257.09:35:44.17#ibcon#about to read 3, iclass 6, count 0 2006.257.09:35:44.19#ibcon#read 3, iclass 6, count 0 2006.257.09:35:44.19#ibcon#about to read 4, iclass 6, count 0 2006.257.09:35:44.19#ibcon#read 4, iclass 6, count 0 2006.257.09:35:44.19#ibcon#about to read 5, iclass 6, count 0 2006.257.09:35:44.19#ibcon#read 5, iclass 6, count 0 2006.257.09:35:44.19#ibcon#about to read 6, iclass 6, count 0 2006.257.09:35:44.19#ibcon#read 6, iclass 6, count 0 2006.257.09:35:44.19#ibcon#end of sib2, iclass 6, count 0 2006.257.09:35:44.19#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:35:44.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:35:44.19#ibcon#[27=USB\r\n] 2006.257.09:35:44.19#ibcon#*before write, iclass 6, count 0 2006.257.09:35:44.19#ibcon#enter sib2, iclass 6, count 0 2006.257.09:35:44.19#ibcon#flushed, iclass 6, count 0 2006.257.09:35:44.19#ibcon#about to write, iclass 6, count 0 2006.257.09:35:44.19#ibcon#wrote, iclass 6, count 0 2006.257.09:35:44.19#ibcon#about to read 3, iclass 6, count 0 2006.257.09:35:44.22#ibcon#read 3, iclass 6, count 0 2006.257.09:35:44.22#ibcon#about to read 4, iclass 6, count 0 2006.257.09:35:44.22#ibcon#read 4, iclass 6, count 0 2006.257.09:35:44.22#ibcon#about to read 5, iclass 6, count 0 2006.257.09:35:44.22#ibcon#read 5, iclass 6, count 0 2006.257.09:35:44.22#ibcon#about to read 6, iclass 6, count 0 2006.257.09:35:44.22#ibcon#read 6, iclass 6, count 0 2006.257.09:35:44.22#ibcon#end of sib2, iclass 6, count 0 2006.257.09:35:44.22#ibcon#*after write, iclass 6, count 0 2006.257.09:35:44.22#ibcon#*before return 0, iclass 6, count 0 2006.257.09:35:44.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:35:44.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:35:44.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:35:44.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:35:44.22$vck44/vblo=2,634.99 2006.257.09:35:44.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.09:35:44.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.09:35:44.22#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:44.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:44.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:44.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:44.22#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:35:44.22#ibcon#first serial, iclass 10, count 0 2006.257.09:35:44.22#ibcon#enter sib2, iclass 10, count 0 2006.257.09:35:44.22#ibcon#flushed, iclass 10, count 0 2006.257.09:35:44.22#ibcon#about to write, iclass 10, count 0 2006.257.09:35:44.22#ibcon#wrote, iclass 10, count 0 2006.257.09:35:44.22#ibcon#about to read 3, iclass 10, count 0 2006.257.09:35:44.24#ibcon#read 3, iclass 10, count 0 2006.257.09:35:44.24#ibcon#about to read 4, iclass 10, count 0 2006.257.09:35:44.24#ibcon#read 4, iclass 10, count 0 2006.257.09:35:44.24#ibcon#about to read 5, iclass 10, count 0 2006.257.09:35:44.24#ibcon#read 5, iclass 10, count 0 2006.257.09:35:44.24#ibcon#about to read 6, iclass 10, count 0 2006.257.09:35:44.24#ibcon#read 6, iclass 10, count 0 2006.257.09:35:44.24#ibcon#end of sib2, iclass 10, count 0 2006.257.09:35:44.24#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:35:44.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:35:44.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:35:44.24#ibcon#*before write, iclass 10, count 0 2006.257.09:35:44.24#ibcon#enter sib2, iclass 10, count 0 2006.257.09:35:44.24#ibcon#flushed, iclass 10, count 0 2006.257.09:35:44.24#ibcon#about to write, iclass 10, count 0 2006.257.09:35:44.24#ibcon#wrote, iclass 10, count 0 2006.257.09:35:44.24#ibcon#about to read 3, iclass 10, count 0 2006.257.09:35:44.28#ibcon#read 3, iclass 10, count 0 2006.257.09:35:44.28#ibcon#about to read 4, iclass 10, count 0 2006.257.09:35:44.28#ibcon#read 4, iclass 10, count 0 2006.257.09:35:44.28#ibcon#about to read 5, iclass 10, count 0 2006.257.09:35:44.28#ibcon#read 5, iclass 10, count 0 2006.257.09:35:44.28#ibcon#about to read 6, iclass 10, count 0 2006.257.09:35:44.28#ibcon#read 6, iclass 10, count 0 2006.257.09:35:44.28#ibcon#end of sib2, iclass 10, count 0 2006.257.09:35:44.28#ibcon#*after write, iclass 10, count 0 2006.257.09:35:44.28#ibcon#*before return 0, iclass 10, count 0 2006.257.09:35:44.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:44.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:35:44.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:35:44.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:35:44.28$vck44/vb=2,5 2006.257.09:35:44.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.09:35:44.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.09:35:44.28#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:44.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:44.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:44.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:44.34#ibcon#enter wrdev, iclass 12, count 2 2006.257.09:35:44.34#ibcon#first serial, iclass 12, count 2 2006.257.09:35:44.34#ibcon#enter sib2, iclass 12, count 2 2006.257.09:35:44.34#ibcon#flushed, iclass 12, count 2 2006.257.09:35:44.34#ibcon#about to write, iclass 12, count 2 2006.257.09:35:44.34#ibcon#wrote, iclass 12, count 2 2006.257.09:35:44.34#ibcon#about to read 3, iclass 12, count 2 2006.257.09:35:44.36#ibcon#read 3, iclass 12, count 2 2006.257.09:35:44.36#ibcon#about to read 4, iclass 12, count 2 2006.257.09:35:44.36#ibcon#read 4, iclass 12, count 2 2006.257.09:35:44.36#ibcon#about to read 5, iclass 12, count 2 2006.257.09:35:44.36#ibcon#read 5, iclass 12, count 2 2006.257.09:35:44.36#ibcon#about to read 6, iclass 12, count 2 2006.257.09:35:44.36#ibcon#read 6, iclass 12, count 2 2006.257.09:35:44.36#ibcon#end of sib2, iclass 12, count 2 2006.257.09:35:44.36#ibcon#*mode == 0, iclass 12, count 2 2006.257.09:35:44.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.09:35:44.36#ibcon#[27=AT02-05\r\n] 2006.257.09:35:44.36#ibcon#*before write, iclass 12, count 2 2006.257.09:35:44.36#ibcon#enter sib2, iclass 12, count 2 2006.257.09:35:44.36#ibcon#flushed, iclass 12, count 2 2006.257.09:35:44.36#ibcon#about to write, iclass 12, count 2 2006.257.09:35:44.36#ibcon#wrote, iclass 12, count 2 2006.257.09:35:44.36#ibcon#about to read 3, iclass 12, count 2 2006.257.09:35:44.39#ibcon#read 3, iclass 12, count 2 2006.257.09:35:44.39#ibcon#about to read 4, iclass 12, count 2 2006.257.09:35:44.44#ibcon#read 4, iclass 12, count 2 2006.257.09:35:44.45#ibcon#about to read 5, iclass 12, count 2 2006.257.09:35:44.45#ibcon#read 5, iclass 12, count 2 2006.257.09:35:44.45#ibcon#about to read 6, iclass 12, count 2 2006.257.09:35:44.45#ibcon#read 6, iclass 12, count 2 2006.257.09:35:44.45#ibcon#end of sib2, iclass 12, count 2 2006.257.09:35:44.45#ibcon#*after write, iclass 12, count 2 2006.257.09:35:44.45#ibcon#*before return 0, iclass 12, count 2 2006.257.09:35:44.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:44.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:35:44.45#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.09:35:44.45#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:44.45#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:44.57#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:44.57#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:44.57#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:35:44.57#ibcon#first serial, iclass 12, count 0 2006.257.09:35:44.57#ibcon#enter sib2, iclass 12, count 0 2006.257.09:35:44.57#ibcon#flushed, iclass 12, count 0 2006.257.09:35:44.57#ibcon#about to write, iclass 12, count 0 2006.257.09:35:44.57#ibcon#wrote, iclass 12, count 0 2006.257.09:35:44.57#ibcon#about to read 3, iclass 12, count 0 2006.257.09:35:44.59#ibcon#read 3, iclass 12, count 0 2006.257.09:35:44.59#ibcon#about to read 4, iclass 12, count 0 2006.257.09:35:44.59#ibcon#read 4, iclass 12, count 0 2006.257.09:35:44.59#ibcon#about to read 5, iclass 12, count 0 2006.257.09:35:44.59#ibcon#read 5, iclass 12, count 0 2006.257.09:35:44.59#ibcon#about to read 6, iclass 12, count 0 2006.257.09:35:44.59#ibcon#read 6, iclass 12, count 0 2006.257.09:35:44.59#ibcon#end of sib2, iclass 12, count 0 2006.257.09:35:44.59#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:35:44.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:35:44.59#ibcon#[27=USB\r\n] 2006.257.09:35:44.59#ibcon#*before write, iclass 12, count 0 2006.257.09:35:44.59#ibcon#enter sib2, iclass 12, count 0 2006.257.09:35:44.59#ibcon#flushed, iclass 12, count 0 2006.257.09:35:44.59#ibcon#about to write, iclass 12, count 0 2006.257.09:35:44.59#ibcon#wrote, iclass 12, count 0 2006.257.09:35:44.59#ibcon#about to read 3, iclass 12, count 0 2006.257.09:35:44.62#ibcon#read 3, iclass 12, count 0 2006.257.09:35:44.62#ibcon#about to read 4, iclass 12, count 0 2006.257.09:35:44.62#ibcon#read 4, iclass 12, count 0 2006.257.09:35:44.62#ibcon#about to read 5, iclass 12, count 0 2006.257.09:35:44.62#ibcon#read 5, iclass 12, count 0 2006.257.09:35:44.62#ibcon#about to read 6, iclass 12, count 0 2006.257.09:35:44.62#ibcon#read 6, iclass 12, count 0 2006.257.09:35:44.62#ibcon#end of sib2, iclass 12, count 0 2006.257.09:35:44.62#ibcon#*after write, iclass 12, count 0 2006.257.09:35:44.62#ibcon#*before return 0, iclass 12, count 0 2006.257.09:35:44.62#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:44.62#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:35:44.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:35:44.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:35:44.62$vck44/vblo=3,649.99 2006.257.09:35:44.62#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.09:35:44.62#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.09:35:44.62#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:44.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:44.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:44.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:44.62#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:35:44.62#ibcon#first serial, iclass 14, count 0 2006.257.09:35:44.62#ibcon#enter sib2, iclass 14, count 0 2006.257.09:35:44.62#ibcon#flushed, iclass 14, count 0 2006.257.09:35:44.62#ibcon#about to write, iclass 14, count 0 2006.257.09:35:44.62#ibcon#wrote, iclass 14, count 0 2006.257.09:35:44.62#ibcon#about to read 3, iclass 14, count 0 2006.257.09:35:44.64#ibcon#read 3, iclass 14, count 0 2006.257.09:35:44.64#ibcon#about to read 4, iclass 14, count 0 2006.257.09:35:44.64#ibcon#read 4, iclass 14, count 0 2006.257.09:35:44.64#ibcon#about to read 5, iclass 14, count 0 2006.257.09:35:44.64#ibcon#read 5, iclass 14, count 0 2006.257.09:35:44.64#ibcon#about to read 6, iclass 14, count 0 2006.257.09:35:44.64#ibcon#read 6, iclass 14, count 0 2006.257.09:35:44.64#ibcon#end of sib2, iclass 14, count 0 2006.257.09:35:44.64#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:35:44.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:35:44.64#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:35:44.64#ibcon#*before write, iclass 14, count 0 2006.257.09:35:44.64#ibcon#enter sib2, iclass 14, count 0 2006.257.09:35:44.64#ibcon#flushed, iclass 14, count 0 2006.257.09:35:44.64#ibcon#about to write, iclass 14, count 0 2006.257.09:35:44.64#ibcon#wrote, iclass 14, count 0 2006.257.09:35:44.64#ibcon#about to read 3, iclass 14, count 0 2006.257.09:35:44.68#ibcon#read 3, iclass 14, count 0 2006.257.09:35:44.68#ibcon#about to read 4, iclass 14, count 0 2006.257.09:35:44.68#ibcon#read 4, iclass 14, count 0 2006.257.09:35:44.68#ibcon#about to read 5, iclass 14, count 0 2006.257.09:35:44.68#ibcon#read 5, iclass 14, count 0 2006.257.09:35:44.68#ibcon#about to read 6, iclass 14, count 0 2006.257.09:35:44.68#ibcon#read 6, iclass 14, count 0 2006.257.09:35:44.68#ibcon#end of sib2, iclass 14, count 0 2006.257.09:35:44.68#ibcon#*after write, iclass 14, count 0 2006.257.09:35:44.68#ibcon#*before return 0, iclass 14, count 0 2006.257.09:35:44.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:44.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:35:44.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:35:44.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:35:44.68$vck44/vb=3,4 2006.257.09:35:44.68#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.09:35:44.68#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.09:35:44.68#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:44.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:44.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:44.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:44.74#ibcon#enter wrdev, iclass 16, count 2 2006.257.09:35:44.74#ibcon#first serial, iclass 16, count 2 2006.257.09:35:44.74#ibcon#enter sib2, iclass 16, count 2 2006.257.09:35:44.74#ibcon#flushed, iclass 16, count 2 2006.257.09:35:44.74#ibcon#about to write, iclass 16, count 2 2006.257.09:35:44.74#ibcon#wrote, iclass 16, count 2 2006.257.09:35:44.74#ibcon#about to read 3, iclass 16, count 2 2006.257.09:35:44.76#ibcon#read 3, iclass 16, count 2 2006.257.09:35:44.76#ibcon#about to read 4, iclass 16, count 2 2006.257.09:35:44.76#ibcon#read 4, iclass 16, count 2 2006.257.09:35:44.76#ibcon#about to read 5, iclass 16, count 2 2006.257.09:35:44.76#ibcon#read 5, iclass 16, count 2 2006.257.09:35:44.76#ibcon#about to read 6, iclass 16, count 2 2006.257.09:35:44.76#ibcon#read 6, iclass 16, count 2 2006.257.09:35:44.76#ibcon#end of sib2, iclass 16, count 2 2006.257.09:35:44.76#ibcon#*mode == 0, iclass 16, count 2 2006.257.09:35:44.76#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.09:35:44.76#ibcon#[27=AT03-04\r\n] 2006.257.09:35:44.76#ibcon#*before write, iclass 16, count 2 2006.257.09:35:44.76#ibcon#enter sib2, iclass 16, count 2 2006.257.09:35:44.76#ibcon#flushed, iclass 16, count 2 2006.257.09:35:44.76#ibcon#about to write, iclass 16, count 2 2006.257.09:35:44.76#ibcon#wrote, iclass 16, count 2 2006.257.09:35:44.76#ibcon#about to read 3, iclass 16, count 2 2006.257.09:35:44.79#ibcon#read 3, iclass 16, count 2 2006.257.09:35:44.79#ibcon#about to read 4, iclass 16, count 2 2006.257.09:35:44.79#ibcon#read 4, iclass 16, count 2 2006.257.09:35:44.79#ibcon#about to read 5, iclass 16, count 2 2006.257.09:35:44.79#ibcon#read 5, iclass 16, count 2 2006.257.09:35:44.79#ibcon#about to read 6, iclass 16, count 2 2006.257.09:35:44.79#ibcon#read 6, iclass 16, count 2 2006.257.09:35:44.79#ibcon#end of sib2, iclass 16, count 2 2006.257.09:35:44.79#ibcon#*after write, iclass 16, count 2 2006.257.09:35:44.79#ibcon#*before return 0, iclass 16, count 2 2006.257.09:35:44.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:44.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:35:44.79#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.09:35:44.79#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:44.79#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:44.91#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:44.91#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:44.91#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:35:44.91#ibcon#first serial, iclass 16, count 0 2006.257.09:35:44.91#ibcon#enter sib2, iclass 16, count 0 2006.257.09:35:44.91#ibcon#flushed, iclass 16, count 0 2006.257.09:35:44.91#ibcon#about to write, iclass 16, count 0 2006.257.09:35:44.91#ibcon#wrote, iclass 16, count 0 2006.257.09:35:44.91#ibcon#about to read 3, iclass 16, count 0 2006.257.09:35:44.93#ibcon#read 3, iclass 16, count 0 2006.257.09:35:44.93#ibcon#about to read 4, iclass 16, count 0 2006.257.09:35:44.93#ibcon#read 4, iclass 16, count 0 2006.257.09:35:44.93#ibcon#about to read 5, iclass 16, count 0 2006.257.09:35:44.93#ibcon#read 5, iclass 16, count 0 2006.257.09:35:44.93#ibcon#about to read 6, iclass 16, count 0 2006.257.09:35:44.93#ibcon#read 6, iclass 16, count 0 2006.257.09:35:44.93#ibcon#end of sib2, iclass 16, count 0 2006.257.09:35:44.93#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:35:44.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:35:44.93#ibcon#[27=USB\r\n] 2006.257.09:35:44.93#ibcon#*before write, iclass 16, count 0 2006.257.09:35:44.93#ibcon#enter sib2, iclass 16, count 0 2006.257.09:35:44.93#ibcon#flushed, iclass 16, count 0 2006.257.09:35:44.93#ibcon#about to write, iclass 16, count 0 2006.257.09:35:44.93#ibcon#wrote, iclass 16, count 0 2006.257.09:35:44.93#ibcon#about to read 3, iclass 16, count 0 2006.257.09:35:44.96#ibcon#read 3, iclass 16, count 0 2006.257.09:35:44.96#ibcon#about to read 4, iclass 16, count 0 2006.257.09:35:44.96#ibcon#read 4, iclass 16, count 0 2006.257.09:35:44.96#ibcon#about to read 5, iclass 16, count 0 2006.257.09:35:44.96#ibcon#read 5, iclass 16, count 0 2006.257.09:35:44.96#ibcon#about to read 6, iclass 16, count 0 2006.257.09:35:44.96#ibcon#read 6, iclass 16, count 0 2006.257.09:35:44.96#ibcon#end of sib2, iclass 16, count 0 2006.257.09:35:44.96#ibcon#*after write, iclass 16, count 0 2006.257.09:35:44.96#ibcon#*before return 0, iclass 16, count 0 2006.257.09:35:44.96#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:44.96#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:35:44.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:35:44.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:35:44.96$vck44/vblo=4,679.99 2006.257.09:35:44.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.09:35:44.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.09:35:44.96#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:44.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:44.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:44.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:44.96#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:35:44.96#ibcon#first serial, iclass 18, count 0 2006.257.09:35:44.96#ibcon#enter sib2, iclass 18, count 0 2006.257.09:35:44.96#ibcon#flushed, iclass 18, count 0 2006.257.09:35:44.96#ibcon#about to write, iclass 18, count 0 2006.257.09:35:44.96#ibcon#wrote, iclass 18, count 0 2006.257.09:35:44.96#ibcon#about to read 3, iclass 18, count 0 2006.257.09:35:44.98#ibcon#read 3, iclass 18, count 0 2006.257.09:35:44.98#ibcon#about to read 4, iclass 18, count 0 2006.257.09:35:44.98#ibcon#read 4, iclass 18, count 0 2006.257.09:35:44.98#ibcon#about to read 5, iclass 18, count 0 2006.257.09:35:44.98#ibcon#read 5, iclass 18, count 0 2006.257.09:35:44.98#ibcon#about to read 6, iclass 18, count 0 2006.257.09:35:44.98#ibcon#read 6, iclass 18, count 0 2006.257.09:35:44.98#ibcon#end of sib2, iclass 18, count 0 2006.257.09:35:44.98#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:35:44.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:35:44.98#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:35:44.98#ibcon#*before write, iclass 18, count 0 2006.257.09:35:44.98#ibcon#enter sib2, iclass 18, count 0 2006.257.09:35:44.98#ibcon#flushed, iclass 18, count 0 2006.257.09:35:44.98#ibcon#about to write, iclass 18, count 0 2006.257.09:35:44.98#ibcon#wrote, iclass 18, count 0 2006.257.09:35:44.98#ibcon#about to read 3, iclass 18, count 0 2006.257.09:35:45.02#ibcon#read 3, iclass 18, count 0 2006.257.09:35:45.02#ibcon#about to read 4, iclass 18, count 0 2006.257.09:35:45.02#ibcon#read 4, iclass 18, count 0 2006.257.09:35:45.02#ibcon#about to read 5, iclass 18, count 0 2006.257.09:35:45.02#ibcon#read 5, iclass 18, count 0 2006.257.09:35:45.02#ibcon#about to read 6, iclass 18, count 0 2006.257.09:35:45.02#ibcon#read 6, iclass 18, count 0 2006.257.09:35:45.02#ibcon#end of sib2, iclass 18, count 0 2006.257.09:35:45.02#ibcon#*after write, iclass 18, count 0 2006.257.09:35:45.02#ibcon#*before return 0, iclass 18, count 0 2006.257.09:35:45.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:45.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:35:45.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:35:45.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:35:45.02$vck44/vb=4,5 2006.257.09:35:45.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.09:35:45.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.09:35:45.02#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:45.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:45.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:45.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:45.08#ibcon#enter wrdev, iclass 20, count 2 2006.257.09:35:45.08#ibcon#first serial, iclass 20, count 2 2006.257.09:35:45.08#ibcon#enter sib2, iclass 20, count 2 2006.257.09:35:45.08#ibcon#flushed, iclass 20, count 2 2006.257.09:35:45.08#ibcon#about to write, iclass 20, count 2 2006.257.09:35:45.08#ibcon#wrote, iclass 20, count 2 2006.257.09:35:45.08#ibcon#about to read 3, iclass 20, count 2 2006.257.09:35:45.10#ibcon#read 3, iclass 20, count 2 2006.257.09:35:45.10#ibcon#about to read 4, iclass 20, count 2 2006.257.09:35:45.10#ibcon#read 4, iclass 20, count 2 2006.257.09:35:45.10#ibcon#about to read 5, iclass 20, count 2 2006.257.09:35:45.10#ibcon#read 5, iclass 20, count 2 2006.257.09:35:45.10#ibcon#about to read 6, iclass 20, count 2 2006.257.09:35:45.10#ibcon#read 6, iclass 20, count 2 2006.257.09:35:45.10#ibcon#end of sib2, iclass 20, count 2 2006.257.09:35:45.10#ibcon#*mode == 0, iclass 20, count 2 2006.257.09:35:45.10#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.09:35:45.10#ibcon#[27=AT04-05\r\n] 2006.257.09:35:45.10#ibcon#*before write, iclass 20, count 2 2006.257.09:35:45.10#ibcon#enter sib2, iclass 20, count 2 2006.257.09:35:45.10#ibcon#flushed, iclass 20, count 2 2006.257.09:35:45.10#ibcon#about to write, iclass 20, count 2 2006.257.09:35:45.10#ibcon#wrote, iclass 20, count 2 2006.257.09:35:45.10#ibcon#about to read 3, iclass 20, count 2 2006.257.09:35:45.13#ibcon#read 3, iclass 20, count 2 2006.257.09:35:45.13#ibcon#about to read 4, iclass 20, count 2 2006.257.09:35:45.13#ibcon#read 4, iclass 20, count 2 2006.257.09:35:45.13#ibcon#about to read 5, iclass 20, count 2 2006.257.09:35:45.13#ibcon#read 5, iclass 20, count 2 2006.257.09:35:45.13#ibcon#about to read 6, iclass 20, count 2 2006.257.09:35:45.13#ibcon#read 6, iclass 20, count 2 2006.257.09:35:45.13#ibcon#end of sib2, iclass 20, count 2 2006.257.09:35:45.13#ibcon#*after write, iclass 20, count 2 2006.257.09:35:45.13#ibcon#*before return 0, iclass 20, count 2 2006.257.09:35:45.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:45.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:35:45.13#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.09:35:45.13#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:45.13#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:45.25#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:45.25#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:45.25#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:35:45.25#ibcon#first serial, iclass 20, count 0 2006.257.09:35:45.25#ibcon#enter sib2, iclass 20, count 0 2006.257.09:35:45.25#ibcon#flushed, iclass 20, count 0 2006.257.09:35:45.25#ibcon#about to write, iclass 20, count 0 2006.257.09:35:45.25#ibcon#wrote, iclass 20, count 0 2006.257.09:35:45.25#ibcon#about to read 3, iclass 20, count 0 2006.257.09:35:45.27#ibcon#read 3, iclass 20, count 0 2006.257.09:35:45.27#ibcon#about to read 4, iclass 20, count 0 2006.257.09:35:45.27#ibcon#read 4, iclass 20, count 0 2006.257.09:35:45.27#ibcon#about to read 5, iclass 20, count 0 2006.257.09:35:45.27#ibcon#read 5, iclass 20, count 0 2006.257.09:35:45.27#ibcon#about to read 6, iclass 20, count 0 2006.257.09:35:45.27#ibcon#read 6, iclass 20, count 0 2006.257.09:35:45.27#ibcon#end of sib2, iclass 20, count 0 2006.257.09:35:45.27#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:35:45.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:35:45.27#ibcon#[27=USB\r\n] 2006.257.09:35:45.27#ibcon#*before write, iclass 20, count 0 2006.257.09:35:45.27#ibcon#enter sib2, iclass 20, count 0 2006.257.09:35:45.27#ibcon#flushed, iclass 20, count 0 2006.257.09:35:45.27#ibcon#about to write, iclass 20, count 0 2006.257.09:35:45.27#ibcon#wrote, iclass 20, count 0 2006.257.09:35:45.27#ibcon#about to read 3, iclass 20, count 0 2006.257.09:35:45.30#ibcon#read 3, iclass 20, count 0 2006.257.09:35:45.30#ibcon#about to read 4, iclass 20, count 0 2006.257.09:35:45.30#ibcon#read 4, iclass 20, count 0 2006.257.09:35:45.30#ibcon#about to read 5, iclass 20, count 0 2006.257.09:35:45.30#ibcon#read 5, iclass 20, count 0 2006.257.09:35:45.30#ibcon#about to read 6, iclass 20, count 0 2006.257.09:35:45.30#ibcon#read 6, iclass 20, count 0 2006.257.09:35:45.30#ibcon#end of sib2, iclass 20, count 0 2006.257.09:35:45.30#ibcon#*after write, iclass 20, count 0 2006.257.09:35:45.30#ibcon#*before return 0, iclass 20, count 0 2006.257.09:35:45.30#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:45.30#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:35:45.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:35:45.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:35:45.30$vck44/vblo=5,709.99 2006.257.09:35:45.30#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.09:35:45.30#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.09:35:45.30#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:45.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:45.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:45.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:45.30#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:35:45.30#ibcon#first serial, iclass 22, count 0 2006.257.09:35:45.30#ibcon#enter sib2, iclass 22, count 0 2006.257.09:35:45.30#ibcon#flushed, iclass 22, count 0 2006.257.09:35:45.30#ibcon#about to write, iclass 22, count 0 2006.257.09:35:45.30#ibcon#wrote, iclass 22, count 0 2006.257.09:35:45.30#ibcon#about to read 3, iclass 22, count 0 2006.257.09:35:45.32#ibcon#read 3, iclass 22, count 0 2006.257.09:35:45.32#ibcon#about to read 4, iclass 22, count 0 2006.257.09:35:45.32#ibcon#read 4, iclass 22, count 0 2006.257.09:35:45.32#ibcon#about to read 5, iclass 22, count 0 2006.257.09:35:45.32#ibcon#read 5, iclass 22, count 0 2006.257.09:35:45.32#ibcon#about to read 6, iclass 22, count 0 2006.257.09:35:45.32#ibcon#read 6, iclass 22, count 0 2006.257.09:35:45.32#ibcon#end of sib2, iclass 22, count 0 2006.257.09:35:45.32#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:35:45.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:35:45.32#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:35:45.32#ibcon#*before write, iclass 22, count 0 2006.257.09:35:45.32#ibcon#enter sib2, iclass 22, count 0 2006.257.09:35:45.32#ibcon#flushed, iclass 22, count 0 2006.257.09:35:45.32#ibcon#about to write, iclass 22, count 0 2006.257.09:35:45.32#ibcon#wrote, iclass 22, count 0 2006.257.09:35:45.32#ibcon#about to read 3, iclass 22, count 0 2006.257.09:35:45.36#ibcon#read 3, iclass 22, count 0 2006.257.09:35:45.36#ibcon#about to read 4, iclass 22, count 0 2006.257.09:35:45.36#ibcon#read 4, iclass 22, count 0 2006.257.09:35:45.36#ibcon#about to read 5, iclass 22, count 0 2006.257.09:35:45.36#ibcon#read 5, iclass 22, count 0 2006.257.09:35:45.36#ibcon#about to read 6, iclass 22, count 0 2006.257.09:35:45.36#ibcon#read 6, iclass 22, count 0 2006.257.09:35:45.36#ibcon#end of sib2, iclass 22, count 0 2006.257.09:35:45.36#ibcon#*after write, iclass 22, count 0 2006.257.09:35:45.36#ibcon#*before return 0, iclass 22, count 0 2006.257.09:35:45.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:45.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:35:45.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:35:45.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:35:45.36$vck44/vb=5,4 2006.257.09:35:45.36#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.09:35:45.36#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.09:35:45.36#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:45.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:45.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:45.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:45.42#ibcon#enter wrdev, iclass 24, count 2 2006.257.09:35:45.42#ibcon#first serial, iclass 24, count 2 2006.257.09:35:45.42#ibcon#enter sib2, iclass 24, count 2 2006.257.09:35:45.42#ibcon#flushed, iclass 24, count 2 2006.257.09:35:45.42#ibcon#about to write, iclass 24, count 2 2006.257.09:35:45.42#ibcon#wrote, iclass 24, count 2 2006.257.09:35:45.42#ibcon#about to read 3, iclass 24, count 2 2006.257.09:35:45.44#ibcon#read 3, iclass 24, count 2 2006.257.09:35:45.44#ibcon#about to read 4, iclass 24, count 2 2006.257.09:35:45.44#ibcon#read 4, iclass 24, count 2 2006.257.09:35:45.44#ibcon#about to read 5, iclass 24, count 2 2006.257.09:35:45.44#ibcon#read 5, iclass 24, count 2 2006.257.09:35:45.44#ibcon#about to read 6, iclass 24, count 2 2006.257.09:35:45.44#ibcon#read 6, iclass 24, count 2 2006.257.09:35:45.44#ibcon#end of sib2, iclass 24, count 2 2006.257.09:35:45.44#ibcon#*mode == 0, iclass 24, count 2 2006.257.09:35:45.44#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.09:35:45.44#ibcon#[27=AT05-04\r\n] 2006.257.09:35:45.44#ibcon#*before write, iclass 24, count 2 2006.257.09:35:45.44#ibcon#enter sib2, iclass 24, count 2 2006.257.09:35:45.44#ibcon#flushed, iclass 24, count 2 2006.257.09:35:45.44#ibcon#about to write, iclass 24, count 2 2006.257.09:35:45.44#ibcon#wrote, iclass 24, count 2 2006.257.09:35:45.44#ibcon#about to read 3, iclass 24, count 2 2006.257.09:35:45.47#ibcon#read 3, iclass 24, count 2 2006.257.09:35:45.47#ibcon#about to read 4, iclass 24, count 2 2006.257.09:35:45.47#ibcon#read 4, iclass 24, count 2 2006.257.09:35:45.47#ibcon#about to read 5, iclass 24, count 2 2006.257.09:35:45.47#ibcon#read 5, iclass 24, count 2 2006.257.09:35:45.47#ibcon#about to read 6, iclass 24, count 2 2006.257.09:35:45.47#ibcon#read 6, iclass 24, count 2 2006.257.09:35:45.47#ibcon#end of sib2, iclass 24, count 2 2006.257.09:35:45.47#ibcon#*after write, iclass 24, count 2 2006.257.09:35:45.47#ibcon#*before return 0, iclass 24, count 2 2006.257.09:35:45.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:45.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:35:45.48#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.09:35:45.48#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:45.48#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:45.60#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:45.60#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:45.60#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:35:45.60#ibcon#first serial, iclass 24, count 0 2006.257.09:35:45.60#ibcon#enter sib2, iclass 24, count 0 2006.257.09:35:45.60#ibcon#flushed, iclass 24, count 0 2006.257.09:35:45.60#ibcon#about to write, iclass 24, count 0 2006.257.09:35:45.60#ibcon#wrote, iclass 24, count 0 2006.257.09:35:45.60#ibcon#about to read 3, iclass 24, count 0 2006.257.09:35:45.62#ibcon#read 3, iclass 24, count 0 2006.257.09:35:45.62#ibcon#about to read 4, iclass 24, count 0 2006.257.09:35:45.62#ibcon#read 4, iclass 24, count 0 2006.257.09:35:45.62#ibcon#about to read 5, iclass 24, count 0 2006.257.09:35:45.62#ibcon#read 5, iclass 24, count 0 2006.257.09:35:45.62#ibcon#about to read 6, iclass 24, count 0 2006.257.09:35:45.62#ibcon#read 6, iclass 24, count 0 2006.257.09:35:45.62#ibcon#end of sib2, iclass 24, count 0 2006.257.09:35:45.62#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:35:45.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:35:45.62#ibcon#[27=USB\r\n] 2006.257.09:35:45.62#ibcon#*before write, iclass 24, count 0 2006.257.09:35:45.62#ibcon#enter sib2, iclass 24, count 0 2006.257.09:35:45.62#ibcon#flushed, iclass 24, count 0 2006.257.09:35:45.62#ibcon#about to write, iclass 24, count 0 2006.257.09:35:45.62#ibcon#wrote, iclass 24, count 0 2006.257.09:35:45.62#ibcon#about to read 3, iclass 24, count 0 2006.257.09:35:45.65#ibcon#read 3, iclass 24, count 0 2006.257.09:35:45.65#ibcon#about to read 4, iclass 24, count 0 2006.257.09:35:45.65#ibcon#read 4, iclass 24, count 0 2006.257.09:35:45.65#ibcon#about to read 5, iclass 24, count 0 2006.257.09:35:45.65#ibcon#read 5, iclass 24, count 0 2006.257.09:35:45.65#ibcon#about to read 6, iclass 24, count 0 2006.257.09:35:45.65#ibcon#read 6, iclass 24, count 0 2006.257.09:35:45.65#ibcon#end of sib2, iclass 24, count 0 2006.257.09:35:45.65#ibcon#*after write, iclass 24, count 0 2006.257.09:35:45.65#ibcon#*before return 0, iclass 24, count 0 2006.257.09:35:45.65#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:45.65#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:35:45.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:35:45.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:35:45.65$vck44/vblo=6,719.99 2006.257.09:35:45.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.09:35:45.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.09:35:45.65#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:45.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:45.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:45.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:45.65#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:35:45.65#ibcon#first serial, iclass 26, count 0 2006.257.09:35:45.65#ibcon#enter sib2, iclass 26, count 0 2006.257.09:35:45.65#ibcon#flushed, iclass 26, count 0 2006.257.09:35:45.65#ibcon#about to write, iclass 26, count 0 2006.257.09:35:45.65#ibcon#wrote, iclass 26, count 0 2006.257.09:35:45.65#ibcon#about to read 3, iclass 26, count 0 2006.257.09:35:45.67#ibcon#read 3, iclass 26, count 0 2006.257.09:35:45.67#ibcon#about to read 4, iclass 26, count 0 2006.257.09:35:45.67#ibcon#read 4, iclass 26, count 0 2006.257.09:35:45.67#ibcon#about to read 5, iclass 26, count 0 2006.257.09:35:45.67#ibcon#read 5, iclass 26, count 0 2006.257.09:35:45.67#ibcon#about to read 6, iclass 26, count 0 2006.257.09:35:45.67#ibcon#read 6, iclass 26, count 0 2006.257.09:35:45.67#ibcon#end of sib2, iclass 26, count 0 2006.257.09:35:45.67#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:35:45.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:35:45.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:35:45.67#ibcon#*before write, iclass 26, count 0 2006.257.09:35:45.67#ibcon#enter sib2, iclass 26, count 0 2006.257.09:35:45.67#ibcon#flushed, iclass 26, count 0 2006.257.09:35:45.67#ibcon#about to write, iclass 26, count 0 2006.257.09:35:45.67#ibcon#wrote, iclass 26, count 0 2006.257.09:35:45.67#ibcon#about to read 3, iclass 26, count 0 2006.257.09:35:45.71#ibcon#read 3, iclass 26, count 0 2006.257.09:35:45.71#ibcon#about to read 4, iclass 26, count 0 2006.257.09:35:45.71#ibcon#read 4, iclass 26, count 0 2006.257.09:35:45.71#ibcon#about to read 5, iclass 26, count 0 2006.257.09:35:45.71#ibcon#read 5, iclass 26, count 0 2006.257.09:35:45.71#ibcon#about to read 6, iclass 26, count 0 2006.257.09:35:45.71#ibcon#read 6, iclass 26, count 0 2006.257.09:35:45.71#ibcon#end of sib2, iclass 26, count 0 2006.257.09:35:45.71#ibcon#*after write, iclass 26, count 0 2006.257.09:35:45.71#ibcon#*before return 0, iclass 26, count 0 2006.257.09:35:45.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:45.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:35:45.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:35:45.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:35:45.71$vck44/vb=6,4 2006.257.09:35:45.71#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.09:35:45.71#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.09:35:45.71#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:45.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:45.77#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:45.77#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:45.77#ibcon#enter wrdev, iclass 28, count 2 2006.257.09:35:45.77#ibcon#first serial, iclass 28, count 2 2006.257.09:35:45.77#ibcon#enter sib2, iclass 28, count 2 2006.257.09:35:45.77#ibcon#flushed, iclass 28, count 2 2006.257.09:35:45.77#ibcon#about to write, iclass 28, count 2 2006.257.09:35:45.77#ibcon#wrote, iclass 28, count 2 2006.257.09:35:45.77#ibcon#about to read 3, iclass 28, count 2 2006.257.09:35:45.79#ibcon#read 3, iclass 28, count 2 2006.257.09:35:45.79#ibcon#about to read 4, iclass 28, count 2 2006.257.09:35:45.79#ibcon#read 4, iclass 28, count 2 2006.257.09:35:45.79#ibcon#about to read 5, iclass 28, count 2 2006.257.09:35:45.79#ibcon#read 5, iclass 28, count 2 2006.257.09:35:45.79#ibcon#about to read 6, iclass 28, count 2 2006.257.09:35:45.79#ibcon#read 6, iclass 28, count 2 2006.257.09:35:45.79#ibcon#end of sib2, iclass 28, count 2 2006.257.09:35:45.79#ibcon#*mode == 0, iclass 28, count 2 2006.257.09:35:45.79#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.09:35:45.79#ibcon#[27=AT06-04\r\n] 2006.257.09:35:45.79#ibcon#*before write, iclass 28, count 2 2006.257.09:35:45.79#ibcon#enter sib2, iclass 28, count 2 2006.257.09:35:45.79#ibcon#flushed, iclass 28, count 2 2006.257.09:35:45.79#ibcon#about to write, iclass 28, count 2 2006.257.09:35:45.79#ibcon#wrote, iclass 28, count 2 2006.257.09:35:45.79#ibcon#about to read 3, iclass 28, count 2 2006.257.09:35:45.82#ibcon#read 3, iclass 28, count 2 2006.257.09:35:45.82#ibcon#about to read 4, iclass 28, count 2 2006.257.09:35:45.82#ibcon#read 4, iclass 28, count 2 2006.257.09:35:45.82#ibcon#about to read 5, iclass 28, count 2 2006.257.09:35:45.82#ibcon#read 5, iclass 28, count 2 2006.257.09:35:45.82#ibcon#about to read 6, iclass 28, count 2 2006.257.09:35:45.82#ibcon#read 6, iclass 28, count 2 2006.257.09:35:45.82#ibcon#end of sib2, iclass 28, count 2 2006.257.09:35:45.82#ibcon#*after write, iclass 28, count 2 2006.257.09:35:45.82#ibcon#*before return 0, iclass 28, count 2 2006.257.09:35:45.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:45.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:35:45.82#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.09:35:45.82#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:45.82#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:45.85#abcon#<5=/14 1.1 3.2 19.51 951013.1\r\n> 2006.257.09:35:45.87#abcon#{5=INTERFACE CLEAR} 2006.257.09:35:45.93#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:35:45.94#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:45.94#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:45.94#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:35:45.94#ibcon#first serial, iclass 28, count 0 2006.257.09:35:45.94#ibcon#enter sib2, iclass 28, count 0 2006.257.09:35:45.94#ibcon#flushed, iclass 28, count 0 2006.257.09:35:45.94#ibcon#about to write, iclass 28, count 0 2006.257.09:35:45.94#ibcon#wrote, iclass 28, count 0 2006.257.09:35:45.94#ibcon#about to read 3, iclass 28, count 0 2006.257.09:35:45.96#ibcon#read 3, iclass 28, count 0 2006.257.09:35:45.96#ibcon#about to read 4, iclass 28, count 0 2006.257.09:35:45.96#ibcon#read 4, iclass 28, count 0 2006.257.09:35:45.96#ibcon#about to read 5, iclass 28, count 0 2006.257.09:35:45.96#ibcon#read 5, iclass 28, count 0 2006.257.09:35:45.96#ibcon#about to read 6, iclass 28, count 0 2006.257.09:35:45.96#ibcon#read 6, iclass 28, count 0 2006.257.09:35:45.96#ibcon#end of sib2, iclass 28, count 0 2006.257.09:35:45.96#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:35:45.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:35:45.96#ibcon#[27=USB\r\n] 2006.257.09:35:45.96#ibcon#*before write, iclass 28, count 0 2006.257.09:35:45.96#ibcon#enter sib2, iclass 28, count 0 2006.257.09:35:45.96#ibcon#flushed, iclass 28, count 0 2006.257.09:35:45.96#ibcon#about to write, iclass 28, count 0 2006.257.09:35:45.96#ibcon#wrote, iclass 28, count 0 2006.257.09:35:45.96#ibcon#about to read 3, iclass 28, count 0 2006.257.09:35:45.99#ibcon#read 3, iclass 28, count 0 2006.257.09:35:45.99#ibcon#about to read 4, iclass 28, count 0 2006.257.09:35:45.99#ibcon#read 4, iclass 28, count 0 2006.257.09:35:45.99#ibcon#about to read 5, iclass 28, count 0 2006.257.09:35:45.99#ibcon#read 5, iclass 28, count 0 2006.257.09:35:45.99#ibcon#about to read 6, iclass 28, count 0 2006.257.09:35:45.99#ibcon#read 6, iclass 28, count 0 2006.257.09:35:45.99#ibcon#end of sib2, iclass 28, count 0 2006.257.09:35:45.99#ibcon#*after write, iclass 28, count 0 2006.257.09:35:45.99#ibcon#*before return 0, iclass 28, count 0 2006.257.09:35:45.99#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:45.99#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:35:45.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:35:45.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:35:45.99$vck44/vblo=7,734.99 2006.257.09:35:45.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.09:35:45.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.09:35:45.99#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:45.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:45.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:45.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:45.99#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:35:45.99#ibcon#first serial, iclass 34, count 0 2006.257.09:35:45.99#ibcon#enter sib2, iclass 34, count 0 2006.257.09:35:45.99#ibcon#flushed, iclass 34, count 0 2006.257.09:35:45.99#ibcon#about to write, iclass 34, count 0 2006.257.09:35:45.99#ibcon#wrote, iclass 34, count 0 2006.257.09:35:45.99#ibcon#about to read 3, iclass 34, count 0 2006.257.09:35:46.01#ibcon#read 3, iclass 34, count 0 2006.257.09:35:46.01#ibcon#about to read 4, iclass 34, count 0 2006.257.09:35:46.01#ibcon#read 4, iclass 34, count 0 2006.257.09:35:46.01#ibcon#about to read 5, iclass 34, count 0 2006.257.09:35:46.01#ibcon#read 5, iclass 34, count 0 2006.257.09:35:46.01#ibcon#about to read 6, iclass 34, count 0 2006.257.09:35:46.01#ibcon#read 6, iclass 34, count 0 2006.257.09:35:46.01#ibcon#end of sib2, iclass 34, count 0 2006.257.09:35:46.01#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:35:46.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:35:46.01#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:35:46.01#ibcon#*before write, iclass 34, count 0 2006.257.09:35:46.01#ibcon#enter sib2, iclass 34, count 0 2006.257.09:35:46.01#ibcon#flushed, iclass 34, count 0 2006.257.09:35:46.01#ibcon#about to write, iclass 34, count 0 2006.257.09:35:46.01#ibcon#wrote, iclass 34, count 0 2006.257.09:35:46.01#ibcon#about to read 3, iclass 34, count 0 2006.257.09:35:46.05#ibcon#read 3, iclass 34, count 0 2006.257.09:35:46.05#ibcon#about to read 4, iclass 34, count 0 2006.257.09:35:46.05#ibcon#read 4, iclass 34, count 0 2006.257.09:35:46.05#ibcon#about to read 5, iclass 34, count 0 2006.257.09:35:46.05#ibcon#read 5, iclass 34, count 0 2006.257.09:35:46.05#ibcon#about to read 6, iclass 34, count 0 2006.257.09:35:46.05#ibcon#read 6, iclass 34, count 0 2006.257.09:35:46.05#ibcon#end of sib2, iclass 34, count 0 2006.257.09:35:46.05#ibcon#*after write, iclass 34, count 0 2006.257.09:35:46.05#ibcon#*before return 0, iclass 34, count 0 2006.257.09:35:46.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:46.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:35:46.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:35:46.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:35:46.05$vck44/vb=7,4 2006.257.09:35:46.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.09:35:46.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.09:35:46.05#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:46.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:46.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:46.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:46.11#ibcon#enter wrdev, iclass 36, count 2 2006.257.09:35:46.11#ibcon#first serial, iclass 36, count 2 2006.257.09:35:46.11#ibcon#enter sib2, iclass 36, count 2 2006.257.09:35:46.11#ibcon#flushed, iclass 36, count 2 2006.257.09:35:46.11#ibcon#about to write, iclass 36, count 2 2006.257.09:35:46.11#ibcon#wrote, iclass 36, count 2 2006.257.09:35:46.11#ibcon#about to read 3, iclass 36, count 2 2006.257.09:35:46.13#ibcon#read 3, iclass 36, count 2 2006.257.09:35:46.13#ibcon#about to read 4, iclass 36, count 2 2006.257.09:35:46.13#ibcon#read 4, iclass 36, count 2 2006.257.09:35:46.13#ibcon#about to read 5, iclass 36, count 2 2006.257.09:35:46.13#ibcon#read 5, iclass 36, count 2 2006.257.09:35:46.13#ibcon#about to read 6, iclass 36, count 2 2006.257.09:35:46.13#ibcon#read 6, iclass 36, count 2 2006.257.09:35:46.13#ibcon#end of sib2, iclass 36, count 2 2006.257.09:35:46.13#ibcon#*mode == 0, iclass 36, count 2 2006.257.09:35:46.13#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.09:35:46.13#ibcon#[27=AT07-04\r\n] 2006.257.09:35:46.13#ibcon#*before write, iclass 36, count 2 2006.257.09:35:46.13#ibcon#enter sib2, iclass 36, count 2 2006.257.09:35:46.13#ibcon#flushed, iclass 36, count 2 2006.257.09:35:46.13#ibcon#about to write, iclass 36, count 2 2006.257.09:35:46.13#ibcon#wrote, iclass 36, count 2 2006.257.09:35:46.13#ibcon#about to read 3, iclass 36, count 2 2006.257.09:35:46.16#ibcon#read 3, iclass 36, count 2 2006.257.09:35:46.16#ibcon#about to read 4, iclass 36, count 2 2006.257.09:35:46.16#ibcon#read 4, iclass 36, count 2 2006.257.09:35:46.16#ibcon#about to read 5, iclass 36, count 2 2006.257.09:35:46.16#ibcon#read 5, iclass 36, count 2 2006.257.09:35:46.16#ibcon#about to read 6, iclass 36, count 2 2006.257.09:35:46.16#ibcon#read 6, iclass 36, count 2 2006.257.09:35:46.16#ibcon#end of sib2, iclass 36, count 2 2006.257.09:35:46.16#ibcon#*after write, iclass 36, count 2 2006.257.09:35:46.16#ibcon#*before return 0, iclass 36, count 2 2006.257.09:35:46.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:46.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:35:46.16#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.09:35:46.16#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:46.16#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:46.28#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:46.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:46.28#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:35:46.28#ibcon#first serial, iclass 36, count 0 2006.257.09:35:46.28#ibcon#enter sib2, iclass 36, count 0 2006.257.09:35:46.28#ibcon#flushed, iclass 36, count 0 2006.257.09:35:46.28#ibcon#about to write, iclass 36, count 0 2006.257.09:35:46.28#ibcon#wrote, iclass 36, count 0 2006.257.09:35:46.28#ibcon#about to read 3, iclass 36, count 0 2006.257.09:35:46.30#ibcon#read 3, iclass 36, count 0 2006.257.09:35:46.30#ibcon#about to read 4, iclass 36, count 0 2006.257.09:35:46.30#ibcon#read 4, iclass 36, count 0 2006.257.09:35:46.30#ibcon#about to read 5, iclass 36, count 0 2006.257.09:35:46.30#ibcon#read 5, iclass 36, count 0 2006.257.09:35:46.30#ibcon#about to read 6, iclass 36, count 0 2006.257.09:35:46.30#ibcon#read 6, iclass 36, count 0 2006.257.09:35:46.30#ibcon#end of sib2, iclass 36, count 0 2006.257.09:35:46.30#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:35:46.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:35:46.30#ibcon#[27=USB\r\n] 2006.257.09:35:46.30#ibcon#*before write, iclass 36, count 0 2006.257.09:35:46.30#ibcon#enter sib2, iclass 36, count 0 2006.257.09:35:46.30#ibcon#flushed, iclass 36, count 0 2006.257.09:35:46.30#ibcon#about to write, iclass 36, count 0 2006.257.09:35:46.30#ibcon#wrote, iclass 36, count 0 2006.257.09:35:46.30#ibcon#about to read 3, iclass 36, count 0 2006.257.09:35:46.33#ibcon#read 3, iclass 36, count 0 2006.257.09:35:46.33#ibcon#about to read 4, iclass 36, count 0 2006.257.09:35:46.33#ibcon#read 4, iclass 36, count 0 2006.257.09:35:46.33#ibcon#about to read 5, iclass 36, count 0 2006.257.09:35:46.33#ibcon#read 5, iclass 36, count 0 2006.257.09:35:46.33#ibcon#about to read 6, iclass 36, count 0 2006.257.09:35:46.33#ibcon#read 6, iclass 36, count 0 2006.257.09:35:46.33#ibcon#end of sib2, iclass 36, count 0 2006.257.09:35:46.33#ibcon#*after write, iclass 36, count 0 2006.257.09:35:46.33#ibcon#*before return 0, iclass 36, count 0 2006.257.09:35:46.33#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:46.33#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:35:46.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:35:46.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:35:46.33$vck44/vblo=8,744.99 2006.257.09:35:46.33#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.09:35:46.33#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.09:35:46.33#ibcon#ireg 17 cls_cnt 0 2006.257.09:35:46.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:46.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:46.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:46.33#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:35:46.33#ibcon#first serial, iclass 38, count 0 2006.257.09:35:46.33#ibcon#enter sib2, iclass 38, count 0 2006.257.09:35:46.33#ibcon#flushed, iclass 38, count 0 2006.257.09:35:46.33#ibcon#about to write, iclass 38, count 0 2006.257.09:35:46.33#ibcon#wrote, iclass 38, count 0 2006.257.09:35:46.33#ibcon#about to read 3, iclass 38, count 0 2006.257.09:35:46.35#ibcon#read 3, iclass 38, count 0 2006.257.09:35:46.35#ibcon#about to read 4, iclass 38, count 0 2006.257.09:35:46.35#ibcon#read 4, iclass 38, count 0 2006.257.09:35:46.35#ibcon#about to read 5, iclass 38, count 0 2006.257.09:35:46.35#ibcon#read 5, iclass 38, count 0 2006.257.09:35:46.35#ibcon#about to read 6, iclass 38, count 0 2006.257.09:35:46.35#ibcon#read 6, iclass 38, count 0 2006.257.09:35:46.35#ibcon#end of sib2, iclass 38, count 0 2006.257.09:35:46.35#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:35:46.35#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:35:46.35#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:35:46.35#ibcon#*before write, iclass 38, count 0 2006.257.09:35:46.35#ibcon#enter sib2, iclass 38, count 0 2006.257.09:35:46.35#ibcon#flushed, iclass 38, count 0 2006.257.09:35:46.35#ibcon#about to write, iclass 38, count 0 2006.257.09:35:46.35#ibcon#wrote, iclass 38, count 0 2006.257.09:35:46.35#ibcon#about to read 3, iclass 38, count 0 2006.257.09:35:46.39#ibcon#read 3, iclass 38, count 0 2006.257.09:35:46.39#ibcon#about to read 4, iclass 38, count 0 2006.257.09:35:46.39#ibcon#read 4, iclass 38, count 0 2006.257.09:35:46.39#ibcon#about to read 5, iclass 38, count 0 2006.257.09:35:46.39#ibcon#read 5, iclass 38, count 0 2006.257.09:35:46.39#ibcon#about to read 6, iclass 38, count 0 2006.257.09:35:46.39#ibcon#read 6, iclass 38, count 0 2006.257.09:35:46.39#ibcon#end of sib2, iclass 38, count 0 2006.257.09:35:46.39#ibcon#*after write, iclass 38, count 0 2006.257.09:35:46.39#ibcon#*before return 0, iclass 38, count 0 2006.257.09:35:46.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:46.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:35:46.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:35:46.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:35:46.39$vck44/vb=8,4 2006.257.09:35:46.39#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.09:35:46.39#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.09:35:46.39#ibcon#ireg 11 cls_cnt 2 2006.257.09:35:46.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:46.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:46.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:46.45#ibcon#enter wrdev, iclass 40, count 2 2006.257.09:35:46.45#ibcon#first serial, iclass 40, count 2 2006.257.09:35:46.45#ibcon#enter sib2, iclass 40, count 2 2006.257.09:35:46.45#ibcon#flushed, iclass 40, count 2 2006.257.09:35:46.45#ibcon#about to write, iclass 40, count 2 2006.257.09:35:46.45#ibcon#wrote, iclass 40, count 2 2006.257.09:35:46.45#ibcon#about to read 3, iclass 40, count 2 2006.257.09:35:46.47#ibcon#read 3, iclass 40, count 2 2006.257.09:35:46.47#ibcon#about to read 4, iclass 40, count 2 2006.257.09:35:46.47#ibcon#read 4, iclass 40, count 2 2006.257.09:35:46.47#ibcon#about to read 5, iclass 40, count 2 2006.257.09:35:46.47#ibcon#read 5, iclass 40, count 2 2006.257.09:35:46.47#ibcon#about to read 6, iclass 40, count 2 2006.257.09:35:46.47#ibcon#read 6, iclass 40, count 2 2006.257.09:35:46.47#ibcon#end of sib2, iclass 40, count 2 2006.257.09:35:46.47#ibcon#*mode == 0, iclass 40, count 2 2006.257.09:35:46.47#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.09:35:46.47#ibcon#[27=AT08-04\r\n] 2006.257.09:35:46.47#ibcon#*before write, iclass 40, count 2 2006.257.09:35:46.47#ibcon#enter sib2, iclass 40, count 2 2006.257.09:35:46.47#ibcon#flushed, iclass 40, count 2 2006.257.09:35:46.47#ibcon#about to write, iclass 40, count 2 2006.257.09:35:46.51#ibcon#wrote, iclass 40, count 2 2006.257.09:35:46.51#ibcon#about to read 3, iclass 40, count 2 2006.257.09:35:46.55#ibcon#read 3, iclass 40, count 2 2006.257.09:35:46.55#ibcon#about to read 4, iclass 40, count 2 2006.257.09:35:46.55#ibcon#read 4, iclass 40, count 2 2006.257.09:35:46.55#ibcon#about to read 5, iclass 40, count 2 2006.257.09:35:46.55#ibcon#read 5, iclass 40, count 2 2006.257.09:35:46.55#ibcon#about to read 6, iclass 40, count 2 2006.257.09:35:46.55#ibcon#read 6, iclass 40, count 2 2006.257.09:35:46.55#ibcon#end of sib2, iclass 40, count 2 2006.257.09:35:46.55#ibcon#*after write, iclass 40, count 2 2006.257.09:35:46.55#ibcon#*before return 0, iclass 40, count 2 2006.257.09:35:46.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:46.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:35:46.55#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.09:35:46.55#ibcon#ireg 7 cls_cnt 0 2006.257.09:35:46.55#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:46.67#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:46.67#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:46.67#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:35:46.67#ibcon#first serial, iclass 40, count 0 2006.257.09:35:46.67#ibcon#enter sib2, iclass 40, count 0 2006.257.09:35:46.67#ibcon#flushed, iclass 40, count 0 2006.257.09:35:46.67#ibcon#about to write, iclass 40, count 0 2006.257.09:35:46.67#ibcon#wrote, iclass 40, count 0 2006.257.09:35:46.67#ibcon#about to read 3, iclass 40, count 0 2006.257.09:35:46.69#ibcon#read 3, iclass 40, count 0 2006.257.09:35:46.69#ibcon#about to read 4, iclass 40, count 0 2006.257.09:35:46.69#ibcon#read 4, iclass 40, count 0 2006.257.09:35:46.69#ibcon#about to read 5, iclass 40, count 0 2006.257.09:35:46.69#ibcon#read 5, iclass 40, count 0 2006.257.09:35:46.69#ibcon#about to read 6, iclass 40, count 0 2006.257.09:35:46.69#ibcon#read 6, iclass 40, count 0 2006.257.09:35:46.69#ibcon#end of sib2, iclass 40, count 0 2006.257.09:35:46.69#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:35:46.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:35:46.69#ibcon#[27=USB\r\n] 2006.257.09:35:46.69#ibcon#*before write, iclass 40, count 0 2006.257.09:35:46.69#ibcon#enter sib2, iclass 40, count 0 2006.257.09:35:46.69#ibcon#flushed, iclass 40, count 0 2006.257.09:35:46.69#ibcon#about to write, iclass 40, count 0 2006.257.09:35:46.69#ibcon#wrote, iclass 40, count 0 2006.257.09:35:46.69#ibcon#about to read 3, iclass 40, count 0 2006.257.09:35:46.72#ibcon#read 3, iclass 40, count 0 2006.257.09:35:46.72#ibcon#about to read 4, iclass 40, count 0 2006.257.09:35:46.72#ibcon#read 4, iclass 40, count 0 2006.257.09:35:46.72#ibcon#about to read 5, iclass 40, count 0 2006.257.09:35:46.72#ibcon#read 5, iclass 40, count 0 2006.257.09:35:46.72#ibcon#about to read 6, iclass 40, count 0 2006.257.09:35:46.72#ibcon#read 6, iclass 40, count 0 2006.257.09:35:46.72#ibcon#end of sib2, iclass 40, count 0 2006.257.09:35:46.72#ibcon#*after write, iclass 40, count 0 2006.257.09:35:46.72#ibcon#*before return 0, iclass 40, count 0 2006.257.09:35:46.72#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:46.72#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:35:46.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:35:46.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:35:46.72$vck44/vabw=wide 2006.257.09:35:46.72#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.09:35:46.72#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.09:35:46.72#ibcon#ireg 8 cls_cnt 0 2006.257.09:35:46.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:46.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:46.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:46.72#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:35:46.72#ibcon#first serial, iclass 4, count 0 2006.257.09:35:46.72#ibcon#enter sib2, iclass 4, count 0 2006.257.09:35:46.72#ibcon#flushed, iclass 4, count 0 2006.257.09:35:46.72#ibcon#about to write, iclass 4, count 0 2006.257.09:35:46.72#ibcon#wrote, iclass 4, count 0 2006.257.09:35:46.72#ibcon#about to read 3, iclass 4, count 0 2006.257.09:35:46.74#ibcon#read 3, iclass 4, count 0 2006.257.09:35:46.74#ibcon#about to read 4, iclass 4, count 0 2006.257.09:35:46.74#ibcon#read 4, iclass 4, count 0 2006.257.09:35:46.74#ibcon#about to read 5, iclass 4, count 0 2006.257.09:35:46.74#ibcon#read 5, iclass 4, count 0 2006.257.09:35:46.74#ibcon#about to read 6, iclass 4, count 0 2006.257.09:35:46.74#ibcon#read 6, iclass 4, count 0 2006.257.09:35:46.74#ibcon#end of sib2, iclass 4, count 0 2006.257.09:35:46.74#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:35:46.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:35:46.74#ibcon#[25=BW32\r\n] 2006.257.09:35:46.74#ibcon#*before write, iclass 4, count 0 2006.257.09:35:46.74#ibcon#enter sib2, iclass 4, count 0 2006.257.09:35:46.74#ibcon#flushed, iclass 4, count 0 2006.257.09:35:46.74#ibcon#about to write, iclass 4, count 0 2006.257.09:35:46.74#ibcon#wrote, iclass 4, count 0 2006.257.09:35:46.74#ibcon#about to read 3, iclass 4, count 0 2006.257.09:35:46.77#ibcon#read 3, iclass 4, count 0 2006.257.09:35:46.77#ibcon#about to read 4, iclass 4, count 0 2006.257.09:35:46.77#ibcon#read 4, iclass 4, count 0 2006.257.09:35:46.77#ibcon#about to read 5, iclass 4, count 0 2006.257.09:35:46.77#ibcon#read 5, iclass 4, count 0 2006.257.09:35:46.77#ibcon#about to read 6, iclass 4, count 0 2006.257.09:35:46.77#ibcon#read 6, iclass 4, count 0 2006.257.09:35:46.77#ibcon#end of sib2, iclass 4, count 0 2006.257.09:35:46.77#ibcon#*after write, iclass 4, count 0 2006.257.09:35:46.77#ibcon#*before return 0, iclass 4, count 0 2006.257.09:35:46.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:46.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:35:46.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:35:46.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:35:46.77$vck44/vbbw=wide 2006.257.09:35:46.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.09:35:46.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.09:35:46.77#ibcon#ireg 8 cls_cnt 0 2006.257.09:35:46.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:35:46.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:35:46.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:35:46.84#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:35:46.84#ibcon#first serial, iclass 6, count 0 2006.257.09:35:46.84#ibcon#enter sib2, iclass 6, count 0 2006.257.09:35:46.84#ibcon#flushed, iclass 6, count 0 2006.257.09:35:46.84#ibcon#about to write, iclass 6, count 0 2006.257.09:35:46.84#ibcon#wrote, iclass 6, count 0 2006.257.09:35:46.84#ibcon#about to read 3, iclass 6, count 0 2006.257.09:35:46.86#ibcon#read 3, iclass 6, count 0 2006.257.09:35:46.86#ibcon#about to read 4, iclass 6, count 0 2006.257.09:35:46.86#ibcon#read 4, iclass 6, count 0 2006.257.09:35:46.86#ibcon#about to read 5, iclass 6, count 0 2006.257.09:35:46.86#ibcon#read 5, iclass 6, count 0 2006.257.09:35:46.86#ibcon#about to read 6, iclass 6, count 0 2006.257.09:35:46.86#ibcon#read 6, iclass 6, count 0 2006.257.09:35:46.86#ibcon#end of sib2, iclass 6, count 0 2006.257.09:35:46.86#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:35:46.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:35:46.86#ibcon#[27=BW32\r\n] 2006.257.09:35:46.86#ibcon#*before write, iclass 6, count 0 2006.257.09:35:46.86#ibcon#enter sib2, iclass 6, count 0 2006.257.09:35:46.86#ibcon#flushed, iclass 6, count 0 2006.257.09:35:46.86#ibcon#about to write, iclass 6, count 0 2006.257.09:35:46.86#ibcon#wrote, iclass 6, count 0 2006.257.09:35:46.86#ibcon#about to read 3, iclass 6, count 0 2006.257.09:35:46.89#ibcon#read 3, iclass 6, count 0 2006.257.09:35:46.89#ibcon#about to read 4, iclass 6, count 0 2006.257.09:35:46.89#ibcon#read 4, iclass 6, count 0 2006.257.09:35:46.89#ibcon#about to read 5, iclass 6, count 0 2006.257.09:35:46.89#ibcon#read 5, iclass 6, count 0 2006.257.09:35:46.89#ibcon#about to read 6, iclass 6, count 0 2006.257.09:35:46.89#ibcon#read 6, iclass 6, count 0 2006.257.09:35:46.89#ibcon#end of sib2, iclass 6, count 0 2006.257.09:35:46.89#ibcon#*after write, iclass 6, count 0 2006.257.09:35:46.89#ibcon#*before return 0, iclass 6, count 0 2006.257.09:35:46.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:35:46.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:35:46.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:35:46.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:35:46.89$setupk4/ifdk4 2006.257.09:35:46.89$ifdk4/lo= 2006.257.09:35:46.89$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:35:46.89$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:35:46.89$ifdk4/patch= 2006.257.09:35:46.89$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:35:46.89$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:35:46.89$setupk4/!*+20s 2006.257.09:35:52.14#trakl#Source acquired 2006.257.09:35:52.14#flagr#flagr/antenna,acquired 2006.257.09:35:56.02#abcon#<5=/14 1.1 3.2 19.51 951013.1\r\n> 2006.257.09:35:56.04#abcon#{5=INTERFACE CLEAR} 2006.257.09:35:56.10#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:36:01.27$setupk4/"tpicd 2006.257.09:36:01.27$setupk4/echo=off 2006.257.09:36:01.27$setupk4/xlog=off 2006.257.09:36:01.27:!2006.257.09:41:47 2006.257.09:41:47.00:preob 2006.257.09:41:47.13/onsource/TRACKING 2006.257.09:41:47.13:!2006.257.09:41:57 2006.257.09:41:57.01:"tape 2006.257.09:41:57.01:"st=record 2006.257.09:41:57.01:data_valid=on 2006.257.09:41:57.02:midob 2006.257.09:41:58.13/onsource/TRACKING 2006.257.09:41:58.14/wx/19.43,1013.3,95 2006.257.09:41:58.28/cable/+6.4753E-03 2006.257.09:41:59.37/va/01,08,usb,yes,31,33 2006.257.09:41:59.37/va/02,07,usb,yes,33,33 2006.257.09:41:59.37/va/03,08,usb,yes,30,31 2006.257.09:41:59.37/va/04,07,usb,yes,34,36 2006.257.09:41:59.37/va/05,04,usb,yes,31,31 2006.257.09:41:59.37/va/06,04,usb,yes,34,34 2006.257.09:41:59.37/va/07,04,usb,yes,35,35 2006.257.09:41:59.37/va/08,04,usb,yes,29,36 2006.257.09:41:59.60/valo/01,524.99,yes,locked 2006.257.09:41:59.60/valo/02,534.99,yes,locked 2006.257.09:41:59.60/valo/03,564.99,yes,locked 2006.257.09:41:59.60/valo/04,624.99,yes,locked 2006.257.09:41:59.60/valo/05,734.99,yes,locked 2006.257.09:41:59.60/valo/06,814.99,yes,locked 2006.257.09:41:59.60/valo/07,864.99,yes,locked 2006.257.09:41:59.60/valo/08,884.99,yes,locked 2006.257.09:42:00.69/vb/01,04,usb,yes,30,28 2006.257.09:42:00.69/vb/02,05,usb,yes,28,28 2006.257.09:42:00.69/vb/03,04,usb,yes,29,32 2006.257.09:42:00.69/vb/04,05,usb,yes,30,29 2006.257.09:42:00.69/vb/05,04,usb,yes,26,29 2006.257.09:42:00.69/vb/06,04,usb,yes,31,27 2006.257.09:42:00.69/vb/07,04,usb,yes,30,30 2006.257.09:42:00.69/vb/08,04,usb,yes,28,31 2006.257.09:42:00.92/vblo/01,629.99,yes,locked 2006.257.09:42:00.92/vblo/02,634.99,yes,locked 2006.257.09:42:00.92/vblo/03,649.99,yes,locked 2006.257.09:42:00.92/vblo/04,679.99,yes,locked 2006.257.09:42:00.92/vblo/05,709.99,yes,locked 2006.257.09:42:00.92/vblo/06,719.99,yes,locked 2006.257.09:42:00.92/vblo/07,734.99,yes,locked 2006.257.09:42:00.92/vblo/08,744.99,yes,locked 2006.257.09:42:01.07/vabw/8 2006.257.09:42:01.22/vbbw/8 2006.257.09:42:01.31/xfe/off,on,15.0 2006.257.09:42:01.68/ifatt/23,28,28,28 2006.257.09:42:02.07/fmout-gps/S +4.65E-07 2006.257.09:42:02.12:!2006.257.09:43:17 2006.257.09:43:17.01:data_valid=off 2006.257.09:43:17.01:"et 2006.257.09:43:17.02:!+3s 2006.257.09:43:20.04:"tape 2006.257.09:43:20.04:postob 2006.257.09:43:20.16/cable/+6.4748E-03 2006.257.09:43:20.16/wx/19.42,1013.3,96 2006.257.09:43:20.22/fmout-gps/S +4.66E-07 2006.257.09:43:20.22:scan_name=257-0947,jd0609,80 2006.257.09:43:20.22:source=2121+053,212344.52,053522.1,2000.0,cw 2006.257.09:43:21.14#flagr#flagr/antenna,new-source 2006.257.09:43:21.14:checkk5 2006.257.09:43:21.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:43:21.91/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:43:22.32/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:43:22.72/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:43:23.10/chk_obsdata//k5ts1/T2570941??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.09:43:23.50/chk_obsdata//k5ts2/T2570941??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.09:43:23.91/chk_obsdata//k5ts3/T2570941??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.09:43:24.32/chk_obsdata//k5ts4/T2570941??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.09:43:25.09/k5log//k5ts1_log_newline 2006.257.09:43:25.80/k5log//k5ts2_log_newline 2006.257.09:43:26.50/k5log//k5ts3_log_newline 2006.257.09:43:27.21/k5log//k5ts4_log_newline 2006.257.09:43:27.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:43:27.24:setupk4=1 2006.257.09:43:27.24$setupk4/echo=on 2006.257.09:43:27.24$setupk4/pcalon 2006.257.09:43:27.24$pcalon/"no phase cal control is implemented here 2006.257.09:43:27.24$setupk4/"tpicd=stop 2006.257.09:43:27.24$setupk4/"rec=synch_on 2006.257.09:43:27.24$setupk4/"rec_mode=128 2006.257.09:43:27.24$setupk4/!* 2006.257.09:43:27.24$setupk4/recpk4 2006.257.09:43:27.24$recpk4/recpatch= 2006.257.09:43:27.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:43:27.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:43:27.24$setupk4/vck44 2006.257.09:43:27.24$vck44/valo=1,524.99 2006.257.09:43:27.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.09:43:27.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.09:43:27.24#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:27.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:27.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:27.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:27.24#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:43:27.24#ibcon#first serial, iclass 13, count 0 2006.257.09:43:27.24#ibcon#enter sib2, iclass 13, count 0 2006.257.09:43:27.24#ibcon#flushed, iclass 13, count 0 2006.257.09:43:27.24#ibcon#about to write, iclass 13, count 0 2006.257.09:43:27.24#ibcon#wrote, iclass 13, count 0 2006.257.09:43:27.24#ibcon#about to read 3, iclass 13, count 0 2006.257.09:43:27.25#ibcon#read 3, iclass 13, count 0 2006.257.09:43:27.25#ibcon#about to read 4, iclass 13, count 0 2006.257.09:43:27.25#ibcon#read 4, iclass 13, count 0 2006.257.09:43:27.25#ibcon#about to read 5, iclass 13, count 0 2006.257.09:43:27.25#ibcon#read 5, iclass 13, count 0 2006.257.09:43:27.25#ibcon#about to read 6, iclass 13, count 0 2006.257.09:43:27.25#ibcon#read 6, iclass 13, count 0 2006.257.09:43:27.25#ibcon#end of sib2, iclass 13, count 0 2006.257.09:43:27.25#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:43:27.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:43:27.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:43:27.25#ibcon#*before write, iclass 13, count 0 2006.257.09:43:27.25#ibcon#enter sib2, iclass 13, count 0 2006.257.09:43:27.25#ibcon#flushed, iclass 13, count 0 2006.257.09:43:27.25#ibcon#about to write, iclass 13, count 0 2006.257.09:43:27.25#ibcon#wrote, iclass 13, count 0 2006.257.09:43:27.25#ibcon#about to read 3, iclass 13, count 0 2006.257.09:43:27.30#ibcon#read 3, iclass 13, count 0 2006.257.09:43:27.30#ibcon#about to read 4, iclass 13, count 0 2006.257.09:43:27.30#ibcon#read 4, iclass 13, count 0 2006.257.09:43:27.30#ibcon#about to read 5, iclass 13, count 0 2006.257.09:43:27.30#ibcon#read 5, iclass 13, count 0 2006.257.09:43:27.30#ibcon#about to read 6, iclass 13, count 0 2006.257.09:43:27.30#ibcon#read 6, iclass 13, count 0 2006.257.09:43:27.30#ibcon#end of sib2, iclass 13, count 0 2006.257.09:43:27.30#ibcon#*after write, iclass 13, count 0 2006.257.09:43:27.30#ibcon#*before return 0, iclass 13, count 0 2006.257.09:43:27.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:27.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:27.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:43:27.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:43:27.30$vck44/va=1,8 2006.257.09:43:27.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.09:43:27.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.09:43:27.30#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:27.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:27.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:27.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:27.30#ibcon#enter wrdev, iclass 15, count 2 2006.257.09:43:27.30#ibcon#first serial, iclass 15, count 2 2006.257.09:43:27.30#ibcon#enter sib2, iclass 15, count 2 2006.257.09:43:27.30#ibcon#flushed, iclass 15, count 2 2006.257.09:43:27.30#ibcon#about to write, iclass 15, count 2 2006.257.09:43:27.30#ibcon#wrote, iclass 15, count 2 2006.257.09:43:27.30#ibcon#about to read 3, iclass 15, count 2 2006.257.09:43:27.32#ibcon#read 3, iclass 15, count 2 2006.257.09:43:27.32#ibcon#about to read 4, iclass 15, count 2 2006.257.09:43:27.32#ibcon#read 4, iclass 15, count 2 2006.257.09:43:27.32#ibcon#about to read 5, iclass 15, count 2 2006.257.09:43:27.32#ibcon#read 5, iclass 15, count 2 2006.257.09:43:27.32#ibcon#about to read 6, iclass 15, count 2 2006.257.09:43:27.32#ibcon#read 6, iclass 15, count 2 2006.257.09:43:27.32#ibcon#end of sib2, iclass 15, count 2 2006.257.09:43:27.32#ibcon#*mode == 0, iclass 15, count 2 2006.257.09:43:27.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.09:43:27.32#ibcon#[25=AT01-08\r\n] 2006.257.09:43:27.32#ibcon#*before write, iclass 15, count 2 2006.257.09:43:27.32#ibcon#enter sib2, iclass 15, count 2 2006.257.09:43:27.32#ibcon#flushed, iclass 15, count 2 2006.257.09:43:27.32#ibcon#about to write, iclass 15, count 2 2006.257.09:43:27.32#ibcon#wrote, iclass 15, count 2 2006.257.09:43:27.32#ibcon#about to read 3, iclass 15, count 2 2006.257.09:43:27.35#ibcon#read 3, iclass 15, count 2 2006.257.09:43:27.35#ibcon#about to read 4, iclass 15, count 2 2006.257.09:43:27.35#ibcon#read 4, iclass 15, count 2 2006.257.09:43:27.35#ibcon#about to read 5, iclass 15, count 2 2006.257.09:43:27.35#ibcon#read 5, iclass 15, count 2 2006.257.09:43:27.35#ibcon#about to read 6, iclass 15, count 2 2006.257.09:43:27.35#ibcon#read 6, iclass 15, count 2 2006.257.09:43:27.35#ibcon#end of sib2, iclass 15, count 2 2006.257.09:43:27.35#ibcon#*after write, iclass 15, count 2 2006.257.09:43:27.35#ibcon#*before return 0, iclass 15, count 2 2006.257.09:43:27.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:27.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:27.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.09:43:27.35#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:27.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:27.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:27.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:27.47#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:43:27.47#ibcon#first serial, iclass 15, count 0 2006.257.09:43:27.47#ibcon#enter sib2, iclass 15, count 0 2006.257.09:43:27.47#ibcon#flushed, iclass 15, count 0 2006.257.09:43:27.47#ibcon#about to write, iclass 15, count 0 2006.257.09:43:27.47#ibcon#wrote, iclass 15, count 0 2006.257.09:43:27.47#ibcon#about to read 3, iclass 15, count 0 2006.257.09:43:27.49#ibcon#read 3, iclass 15, count 0 2006.257.09:43:27.49#ibcon#about to read 4, iclass 15, count 0 2006.257.09:43:27.49#ibcon#read 4, iclass 15, count 0 2006.257.09:43:27.49#ibcon#about to read 5, iclass 15, count 0 2006.257.09:43:27.49#ibcon#read 5, iclass 15, count 0 2006.257.09:43:27.49#ibcon#about to read 6, iclass 15, count 0 2006.257.09:43:27.49#ibcon#read 6, iclass 15, count 0 2006.257.09:43:27.49#ibcon#end of sib2, iclass 15, count 0 2006.257.09:43:27.49#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:43:27.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:43:27.49#ibcon#[25=USB\r\n] 2006.257.09:43:27.49#ibcon#*before write, iclass 15, count 0 2006.257.09:43:27.49#ibcon#enter sib2, iclass 15, count 0 2006.257.09:43:27.49#ibcon#flushed, iclass 15, count 0 2006.257.09:43:27.49#ibcon#about to write, iclass 15, count 0 2006.257.09:43:27.49#ibcon#wrote, iclass 15, count 0 2006.257.09:43:27.49#ibcon#about to read 3, iclass 15, count 0 2006.257.09:43:27.52#ibcon#read 3, iclass 15, count 0 2006.257.09:43:27.52#ibcon#about to read 4, iclass 15, count 0 2006.257.09:43:27.52#ibcon#read 4, iclass 15, count 0 2006.257.09:43:27.52#ibcon#about to read 5, iclass 15, count 0 2006.257.09:43:27.52#ibcon#read 5, iclass 15, count 0 2006.257.09:43:27.52#ibcon#about to read 6, iclass 15, count 0 2006.257.09:43:27.52#ibcon#read 6, iclass 15, count 0 2006.257.09:43:27.52#ibcon#end of sib2, iclass 15, count 0 2006.257.09:43:27.52#ibcon#*after write, iclass 15, count 0 2006.257.09:43:27.52#ibcon#*before return 0, iclass 15, count 0 2006.257.09:43:27.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:27.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:27.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:43:27.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:43:27.52$vck44/valo=2,534.99 2006.257.09:43:27.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.09:43:27.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.09:43:27.52#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:27.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:27.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:27.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:27.52#ibcon#enter wrdev, iclass 17, count 0 2006.257.09:43:27.52#ibcon#first serial, iclass 17, count 0 2006.257.09:43:27.52#ibcon#enter sib2, iclass 17, count 0 2006.257.09:43:27.52#ibcon#flushed, iclass 17, count 0 2006.257.09:43:27.52#ibcon#about to write, iclass 17, count 0 2006.257.09:43:27.52#ibcon#wrote, iclass 17, count 0 2006.257.09:43:27.52#ibcon#about to read 3, iclass 17, count 0 2006.257.09:43:27.54#ibcon#read 3, iclass 17, count 0 2006.257.09:43:27.54#ibcon#about to read 4, iclass 17, count 0 2006.257.09:43:27.54#ibcon#read 4, iclass 17, count 0 2006.257.09:43:27.54#ibcon#about to read 5, iclass 17, count 0 2006.257.09:43:27.54#ibcon#read 5, iclass 17, count 0 2006.257.09:43:27.54#ibcon#about to read 6, iclass 17, count 0 2006.257.09:43:27.54#ibcon#read 6, iclass 17, count 0 2006.257.09:43:27.54#ibcon#end of sib2, iclass 17, count 0 2006.257.09:43:27.54#ibcon#*mode == 0, iclass 17, count 0 2006.257.09:43:27.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.09:43:27.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:43:27.54#ibcon#*before write, iclass 17, count 0 2006.257.09:43:27.54#ibcon#enter sib2, iclass 17, count 0 2006.257.09:43:27.54#ibcon#flushed, iclass 17, count 0 2006.257.09:43:27.54#ibcon#about to write, iclass 17, count 0 2006.257.09:43:27.54#ibcon#wrote, iclass 17, count 0 2006.257.09:43:27.54#ibcon#about to read 3, iclass 17, count 0 2006.257.09:43:27.58#ibcon#read 3, iclass 17, count 0 2006.257.09:43:27.58#ibcon#about to read 4, iclass 17, count 0 2006.257.09:43:27.58#ibcon#read 4, iclass 17, count 0 2006.257.09:43:27.58#ibcon#about to read 5, iclass 17, count 0 2006.257.09:43:27.58#ibcon#read 5, iclass 17, count 0 2006.257.09:43:27.58#ibcon#about to read 6, iclass 17, count 0 2006.257.09:43:27.58#ibcon#read 6, iclass 17, count 0 2006.257.09:43:27.58#ibcon#end of sib2, iclass 17, count 0 2006.257.09:43:27.58#ibcon#*after write, iclass 17, count 0 2006.257.09:43:27.58#ibcon#*before return 0, iclass 17, count 0 2006.257.09:43:27.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:27.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:27.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.09:43:27.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.09:43:27.58$vck44/va=2,7 2006.257.09:43:27.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.09:43:27.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.09:43:27.58#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:27.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:27.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:27.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:27.64#ibcon#enter wrdev, iclass 19, count 2 2006.257.09:43:27.64#ibcon#first serial, iclass 19, count 2 2006.257.09:43:27.64#ibcon#enter sib2, iclass 19, count 2 2006.257.09:43:27.64#ibcon#flushed, iclass 19, count 2 2006.257.09:43:27.64#ibcon#about to write, iclass 19, count 2 2006.257.09:43:27.64#ibcon#wrote, iclass 19, count 2 2006.257.09:43:27.64#ibcon#about to read 3, iclass 19, count 2 2006.257.09:43:27.66#ibcon#read 3, iclass 19, count 2 2006.257.09:43:27.66#ibcon#about to read 4, iclass 19, count 2 2006.257.09:43:27.66#ibcon#read 4, iclass 19, count 2 2006.257.09:43:27.66#ibcon#about to read 5, iclass 19, count 2 2006.257.09:43:27.66#ibcon#read 5, iclass 19, count 2 2006.257.09:43:27.66#ibcon#about to read 6, iclass 19, count 2 2006.257.09:43:27.66#ibcon#read 6, iclass 19, count 2 2006.257.09:43:27.66#ibcon#end of sib2, iclass 19, count 2 2006.257.09:43:27.66#ibcon#*mode == 0, iclass 19, count 2 2006.257.09:43:27.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.09:43:27.66#ibcon#[25=AT02-07\r\n] 2006.257.09:43:27.66#ibcon#*before write, iclass 19, count 2 2006.257.09:43:27.66#ibcon#enter sib2, iclass 19, count 2 2006.257.09:43:27.66#ibcon#flushed, iclass 19, count 2 2006.257.09:43:27.66#ibcon#about to write, iclass 19, count 2 2006.257.09:43:27.66#ibcon#wrote, iclass 19, count 2 2006.257.09:43:27.66#ibcon#about to read 3, iclass 19, count 2 2006.257.09:43:27.69#ibcon#read 3, iclass 19, count 2 2006.257.09:43:27.69#ibcon#about to read 4, iclass 19, count 2 2006.257.09:43:27.69#ibcon#read 4, iclass 19, count 2 2006.257.09:43:27.69#ibcon#about to read 5, iclass 19, count 2 2006.257.09:43:27.69#ibcon#read 5, iclass 19, count 2 2006.257.09:43:27.69#ibcon#about to read 6, iclass 19, count 2 2006.257.09:43:27.69#ibcon#read 6, iclass 19, count 2 2006.257.09:43:27.69#ibcon#end of sib2, iclass 19, count 2 2006.257.09:43:27.69#ibcon#*after write, iclass 19, count 2 2006.257.09:43:27.69#ibcon#*before return 0, iclass 19, count 2 2006.257.09:43:27.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:27.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:27.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.09:43:27.69#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:27.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:27.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:27.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:27.81#ibcon#enter wrdev, iclass 19, count 0 2006.257.09:43:27.81#ibcon#first serial, iclass 19, count 0 2006.257.09:43:27.81#ibcon#enter sib2, iclass 19, count 0 2006.257.09:43:27.81#ibcon#flushed, iclass 19, count 0 2006.257.09:43:27.81#ibcon#about to write, iclass 19, count 0 2006.257.09:43:27.81#ibcon#wrote, iclass 19, count 0 2006.257.09:43:27.81#ibcon#about to read 3, iclass 19, count 0 2006.257.09:43:27.83#ibcon#read 3, iclass 19, count 0 2006.257.09:43:27.83#ibcon#about to read 4, iclass 19, count 0 2006.257.09:43:27.83#ibcon#read 4, iclass 19, count 0 2006.257.09:43:27.83#ibcon#about to read 5, iclass 19, count 0 2006.257.09:43:27.83#ibcon#read 5, iclass 19, count 0 2006.257.09:43:27.83#ibcon#about to read 6, iclass 19, count 0 2006.257.09:43:27.83#ibcon#read 6, iclass 19, count 0 2006.257.09:43:27.83#ibcon#end of sib2, iclass 19, count 0 2006.257.09:43:27.83#ibcon#*mode == 0, iclass 19, count 0 2006.257.09:43:27.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.09:43:27.83#ibcon#[25=USB\r\n] 2006.257.09:43:27.83#ibcon#*before write, iclass 19, count 0 2006.257.09:43:27.83#ibcon#enter sib2, iclass 19, count 0 2006.257.09:43:27.83#ibcon#flushed, iclass 19, count 0 2006.257.09:43:27.83#ibcon#about to write, iclass 19, count 0 2006.257.09:43:27.83#ibcon#wrote, iclass 19, count 0 2006.257.09:43:27.83#ibcon#about to read 3, iclass 19, count 0 2006.257.09:43:27.86#ibcon#read 3, iclass 19, count 0 2006.257.09:43:27.86#ibcon#about to read 4, iclass 19, count 0 2006.257.09:43:27.86#ibcon#read 4, iclass 19, count 0 2006.257.09:43:27.86#ibcon#about to read 5, iclass 19, count 0 2006.257.09:43:27.86#ibcon#read 5, iclass 19, count 0 2006.257.09:43:27.86#ibcon#about to read 6, iclass 19, count 0 2006.257.09:43:27.86#ibcon#read 6, iclass 19, count 0 2006.257.09:43:27.86#ibcon#end of sib2, iclass 19, count 0 2006.257.09:43:27.86#ibcon#*after write, iclass 19, count 0 2006.257.09:43:27.86#ibcon#*before return 0, iclass 19, count 0 2006.257.09:43:27.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:27.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:27.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.09:43:27.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.09:43:27.86$vck44/valo=3,564.99 2006.257.09:43:27.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.09:43:27.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.09:43:27.86#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:27.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:27.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:27.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:27.86#ibcon#enter wrdev, iclass 21, count 0 2006.257.09:43:27.86#ibcon#first serial, iclass 21, count 0 2006.257.09:43:27.86#ibcon#enter sib2, iclass 21, count 0 2006.257.09:43:27.86#ibcon#flushed, iclass 21, count 0 2006.257.09:43:27.86#ibcon#about to write, iclass 21, count 0 2006.257.09:43:27.86#ibcon#wrote, iclass 21, count 0 2006.257.09:43:27.86#ibcon#about to read 3, iclass 21, count 0 2006.257.09:43:27.88#ibcon#read 3, iclass 21, count 0 2006.257.09:43:27.88#ibcon#about to read 4, iclass 21, count 0 2006.257.09:43:27.88#ibcon#read 4, iclass 21, count 0 2006.257.09:43:27.88#ibcon#about to read 5, iclass 21, count 0 2006.257.09:43:27.88#ibcon#read 5, iclass 21, count 0 2006.257.09:43:27.88#ibcon#about to read 6, iclass 21, count 0 2006.257.09:43:27.88#ibcon#read 6, iclass 21, count 0 2006.257.09:43:27.88#ibcon#end of sib2, iclass 21, count 0 2006.257.09:43:27.88#ibcon#*mode == 0, iclass 21, count 0 2006.257.09:43:27.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.09:43:27.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:43:27.88#ibcon#*before write, iclass 21, count 0 2006.257.09:43:27.88#ibcon#enter sib2, iclass 21, count 0 2006.257.09:43:27.88#ibcon#flushed, iclass 21, count 0 2006.257.09:43:27.88#ibcon#about to write, iclass 21, count 0 2006.257.09:43:27.88#ibcon#wrote, iclass 21, count 0 2006.257.09:43:27.88#ibcon#about to read 3, iclass 21, count 0 2006.257.09:43:27.92#ibcon#read 3, iclass 21, count 0 2006.257.09:43:27.92#ibcon#about to read 4, iclass 21, count 0 2006.257.09:43:27.92#ibcon#read 4, iclass 21, count 0 2006.257.09:43:27.92#ibcon#about to read 5, iclass 21, count 0 2006.257.09:43:27.92#ibcon#read 5, iclass 21, count 0 2006.257.09:43:27.92#ibcon#about to read 6, iclass 21, count 0 2006.257.09:43:27.92#ibcon#read 6, iclass 21, count 0 2006.257.09:43:27.92#ibcon#end of sib2, iclass 21, count 0 2006.257.09:43:27.92#ibcon#*after write, iclass 21, count 0 2006.257.09:43:27.92#ibcon#*before return 0, iclass 21, count 0 2006.257.09:43:27.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:27.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:27.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.09:43:27.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.09:43:27.92$vck44/va=3,8 2006.257.09:43:27.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.09:43:27.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.09:43:27.92#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:27.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:27.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:27.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:27.98#ibcon#enter wrdev, iclass 23, count 2 2006.257.09:43:27.98#ibcon#first serial, iclass 23, count 2 2006.257.09:43:27.98#ibcon#enter sib2, iclass 23, count 2 2006.257.09:43:27.98#ibcon#flushed, iclass 23, count 2 2006.257.09:43:27.98#ibcon#about to write, iclass 23, count 2 2006.257.09:43:27.98#ibcon#wrote, iclass 23, count 2 2006.257.09:43:27.98#ibcon#about to read 3, iclass 23, count 2 2006.257.09:43:28.00#ibcon#read 3, iclass 23, count 2 2006.257.09:43:28.00#ibcon#about to read 4, iclass 23, count 2 2006.257.09:43:28.00#ibcon#read 4, iclass 23, count 2 2006.257.09:43:28.00#ibcon#about to read 5, iclass 23, count 2 2006.257.09:43:28.00#ibcon#read 5, iclass 23, count 2 2006.257.09:43:28.00#ibcon#about to read 6, iclass 23, count 2 2006.257.09:43:28.00#ibcon#read 6, iclass 23, count 2 2006.257.09:43:28.00#ibcon#end of sib2, iclass 23, count 2 2006.257.09:43:28.00#ibcon#*mode == 0, iclass 23, count 2 2006.257.09:43:28.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.09:43:28.00#ibcon#[25=AT03-08\r\n] 2006.257.09:43:28.00#ibcon#*before write, iclass 23, count 2 2006.257.09:43:28.00#ibcon#enter sib2, iclass 23, count 2 2006.257.09:43:28.00#ibcon#flushed, iclass 23, count 2 2006.257.09:43:28.00#ibcon#about to write, iclass 23, count 2 2006.257.09:43:28.00#ibcon#wrote, iclass 23, count 2 2006.257.09:43:28.00#ibcon#about to read 3, iclass 23, count 2 2006.257.09:43:28.03#ibcon#read 3, iclass 23, count 2 2006.257.09:43:28.03#ibcon#about to read 4, iclass 23, count 2 2006.257.09:43:28.03#ibcon#read 4, iclass 23, count 2 2006.257.09:43:28.03#ibcon#about to read 5, iclass 23, count 2 2006.257.09:43:28.03#ibcon#read 5, iclass 23, count 2 2006.257.09:43:28.03#ibcon#about to read 6, iclass 23, count 2 2006.257.09:43:28.03#ibcon#read 6, iclass 23, count 2 2006.257.09:43:28.03#ibcon#end of sib2, iclass 23, count 2 2006.257.09:43:28.03#ibcon#*after write, iclass 23, count 2 2006.257.09:43:28.03#ibcon#*before return 0, iclass 23, count 2 2006.257.09:43:28.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:28.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:28.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.09:43:28.03#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:28.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:28.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:28.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:28.15#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:43:28.15#ibcon#first serial, iclass 23, count 0 2006.257.09:43:28.15#ibcon#enter sib2, iclass 23, count 0 2006.257.09:43:28.15#ibcon#flushed, iclass 23, count 0 2006.257.09:43:28.15#ibcon#about to write, iclass 23, count 0 2006.257.09:43:28.15#ibcon#wrote, iclass 23, count 0 2006.257.09:43:28.15#ibcon#about to read 3, iclass 23, count 0 2006.257.09:43:28.17#ibcon#read 3, iclass 23, count 0 2006.257.09:43:28.17#ibcon#about to read 4, iclass 23, count 0 2006.257.09:43:28.17#ibcon#read 4, iclass 23, count 0 2006.257.09:43:28.17#ibcon#about to read 5, iclass 23, count 0 2006.257.09:43:28.17#ibcon#read 5, iclass 23, count 0 2006.257.09:43:28.17#ibcon#about to read 6, iclass 23, count 0 2006.257.09:43:28.17#ibcon#read 6, iclass 23, count 0 2006.257.09:43:28.17#ibcon#end of sib2, iclass 23, count 0 2006.257.09:43:28.17#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:43:28.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:43:28.17#ibcon#[25=USB\r\n] 2006.257.09:43:28.17#ibcon#*before write, iclass 23, count 0 2006.257.09:43:28.17#ibcon#enter sib2, iclass 23, count 0 2006.257.09:43:28.17#ibcon#flushed, iclass 23, count 0 2006.257.09:43:28.17#ibcon#about to write, iclass 23, count 0 2006.257.09:43:28.17#ibcon#wrote, iclass 23, count 0 2006.257.09:43:28.17#ibcon#about to read 3, iclass 23, count 0 2006.257.09:43:28.20#ibcon#read 3, iclass 23, count 0 2006.257.09:43:28.20#ibcon#about to read 4, iclass 23, count 0 2006.257.09:43:28.20#ibcon#read 4, iclass 23, count 0 2006.257.09:43:28.20#ibcon#about to read 5, iclass 23, count 0 2006.257.09:43:28.20#ibcon#read 5, iclass 23, count 0 2006.257.09:43:28.20#ibcon#about to read 6, iclass 23, count 0 2006.257.09:43:28.20#ibcon#read 6, iclass 23, count 0 2006.257.09:43:28.20#ibcon#end of sib2, iclass 23, count 0 2006.257.09:43:28.20#ibcon#*after write, iclass 23, count 0 2006.257.09:43:28.20#ibcon#*before return 0, iclass 23, count 0 2006.257.09:43:28.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:28.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:28.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:43:28.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:43:28.20$vck44/valo=4,624.99 2006.257.09:43:28.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.09:43:28.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.09:43:28.20#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:28.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:28.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:28.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:28.20#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:43:28.20#ibcon#first serial, iclass 25, count 0 2006.257.09:43:28.20#ibcon#enter sib2, iclass 25, count 0 2006.257.09:43:28.20#ibcon#flushed, iclass 25, count 0 2006.257.09:43:28.20#ibcon#about to write, iclass 25, count 0 2006.257.09:43:28.20#ibcon#wrote, iclass 25, count 0 2006.257.09:43:28.20#ibcon#about to read 3, iclass 25, count 0 2006.257.09:43:28.22#ibcon#read 3, iclass 25, count 0 2006.257.09:43:28.22#ibcon#about to read 4, iclass 25, count 0 2006.257.09:43:28.22#ibcon#read 4, iclass 25, count 0 2006.257.09:43:28.22#ibcon#about to read 5, iclass 25, count 0 2006.257.09:43:28.22#ibcon#read 5, iclass 25, count 0 2006.257.09:43:28.22#ibcon#about to read 6, iclass 25, count 0 2006.257.09:43:28.22#ibcon#read 6, iclass 25, count 0 2006.257.09:43:28.22#ibcon#end of sib2, iclass 25, count 0 2006.257.09:43:28.22#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:43:28.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:43:28.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:43:28.22#ibcon#*before write, iclass 25, count 0 2006.257.09:43:28.22#ibcon#enter sib2, iclass 25, count 0 2006.257.09:43:28.22#ibcon#flushed, iclass 25, count 0 2006.257.09:43:28.22#ibcon#about to write, iclass 25, count 0 2006.257.09:43:28.22#ibcon#wrote, iclass 25, count 0 2006.257.09:43:28.22#ibcon#about to read 3, iclass 25, count 0 2006.257.09:43:28.26#ibcon#read 3, iclass 25, count 0 2006.257.09:43:28.26#ibcon#about to read 4, iclass 25, count 0 2006.257.09:43:28.26#ibcon#read 4, iclass 25, count 0 2006.257.09:43:28.26#ibcon#about to read 5, iclass 25, count 0 2006.257.09:43:28.26#ibcon#read 5, iclass 25, count 0 2006.257.09:43:28.26#ibcon#about to read 6, iclass 25, count 0 2006.257.09:43:28.26#ibcon#read 6, iclass 25, count 0 2006.257.09:43:28.26#ibcon#end of sib2, iclass 25, count 0 2006.257.09:43:28.26#ibcon#*after write, iclass 25, count 0 2006.257.09:43:28.26#ibcon#*before return 0, iclass 25, count 0 2006.257.09:43:28.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:28.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:28.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:43:28.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:43:28.26$vck44/va=4,7 2006.257.09:43:28.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.09:43:28.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.09:43:28.26#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:28.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:28.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:28.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:28.32#ibcon#enter wrdev, iclass 27, count 2 2006.257.09:43:28.32#ibcon#first serial, iclass 27, count 2 2006.257.09:43:28.32#ibcon#enter sib2, iclass 27, count 2 2006.257.09:43:28.32#ibcon#flushed, iclass 27, count 2 2006.257.09:43:28.32#ibcon#about to write, iclass 27, count 2 2006.257.09:43:28.32#ibcon#wrote, iclass 27, count 2 2006.257.09:43:28.32#ibcon#about to read 3, iclass 27, count 2 2006.257.09:43:28.34#ibcon#read 3, iclass 27, count 2 2006.257.09:43:28.34#ibcon#about to read 4, iclass 27, count 2 2006.257.09:43:28.34#ibcon#read 4, iclass 27, count 2 2006.257.09:43:28.34#ibcon#about to read 5, iclass 27, count 2 2006.257.09:43:28.34#ibcon#read 5, iclass 27, count 2 2006.257.09:43:28.34#ibcon#about to read 6, iclass 27, count 2 2006.257.09:43:28.34#ibcon#read 6, iclass 27, count 2 2006.257.09:43:28.34#ibcon#end of sib2, iclass 27, count 2 2006.257.09:43:28.34#ibcon#*mode == 0, iclass 27, count 2 2006.257.09:43:28.34#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.09:43:28.34#ibcon#[25=AT04-07\r\n] 2006.257.09:43:28.34#ibcon#*before write, iclass 27, count 2 2006.257.09:43:28.34#ibcon#enter sib2, iclass 27, count 2 2006.257.09:43:28.34#ibcon#flushed, iclass 27, count 2 2006.257.09:43:28.34#ibcon#about to write, iclass 27, count 2 2006.257.09:43:28.34#ibcon#wrote, iclass 27, count 2 2006.257.09:43:28.34#ibcon#about to read 3, iclass 27, count 2 2006.257.09:43:28.37#ibcon#read 3, iclass 27, count 2 2006.257.09:43:28.37#ibcon#about to read 4, iclass 27, count 2 2006.257.09:43:28.37#ibcon#read 4, iclass 27, count 2 2006.257.09:43:28.37#ibcon#about to read 5, iclass 27, count 2 2006.257.09:43:28.37#ibcon#read 5, iclass 27, count 2 2006.257.09:43:28.37#ibcon#about to read 6, iclass 27, count 2 2006.257.09:43:28.37#ibcon#read 6, iclass 27, count 2 2006.257.09:43:28.37#ibcon#end of sib2, iclass 27, count 2 2006.257.09:43:28.37#ibcon#*after write, iclass 27, count 2 2006.257.09:43:28.37#ibcon#*before return 0, iclass 27, count 2 2006.257.09:43:28.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:28.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:28.37#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.09:43:28.37#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:28.37#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:28.49#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:28.49#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:28.49#ibcon#enter wrdev, iclass 27, count 0 2006.257.09:43:28.49#ibcon#first serial, iclass 27, count 0 2006.257.09:43:28.49#ibcon#enter sib2, iclass 27, count 0 2006.257.09:43:28.49#ibcon#flushed, iclass 27, count 0 2006.257.09:43:28.49#ibcon#about to write, iclass 27, count 0 2006.257.09:43:28.49#ibcon#wrote, iclass 27, count 0 2006.257.09:43:28.49#ibcon#about to read 3, iclass 27, count 0 2006.257.09:43:28.51#ibcon#read 3, iclass 27, count 0 2006.257.09:43:28.51#ibcon#about to read 4, iclass 27, count 0 2006.257.09:43:28.51#ibcon#read 4, iclass 27, count 0 2006.257.09:43:28.51#ibcon#about to read 5, iclass 27, count 0 2006.257.09:43:28.51#ibcon#read 5, iclass 27, count 0 2006.257.09:43:28.51#ibcon#about to read 6, iclass 27, count 0 2006.257.09:43:28.51#ibcon#read 6, iclass 27, count 0 2006.257.09:43:28.51#ibcon#end of sib2, iclass 27, count 0 2006.257.09:43:28.51#ibcon#*mode == 0, iclass 27, count 0 2006.257.09:43:28.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.09:43:28.51#ibcon#[25=USB\r\n] 2006.257.09:43:28.51#ibcon#*before write, iclass 27, count 0 2006.257.09:43:28.51#ibcon#enter sib2, iclass 27, count 0 2006.257.09:43:28.51#ibcon#flushed, iclass 27, count 0 2006.257.09:43:28.51#ibcon#about to write, iclass 27, count 0 2006.257.09:43:28.51#ibcon#wrote, iclass 27, count 0 2006.257.09:43:28.51#ibcon#about to read 3, iclass 27, count 0 2006.257.09:43:28.54#ibcon#read 3, iclass 27, count 0 2006.257.09:43:28.54#ibcon#about to read 4, iclass 27, count 0 2006.257.09:43:28.54#ibcon#read 4, iclass 27, count 0 2006.257.09:43:28.54#ibcon#about to read 5, iclass 27, count 0 2006.257.09:43:28.54#ibcon#read 5, iclass 27, count 0 2006.257.09:43:28.54#ibcon#about to read 6, iclass 27, count 0 2006.257.09:43:28.54#ibcon#read 6, iclass 27, count 0 2006.257.09:43:28.54#ibcon#end of sib2, iclass 27, count 0 2006.257.09:43:28.54#ibcon#*after write, iclass 27, count 0 2006.257.09:43:28.54#ibcon#*before return 0, iclass 27, count 0 2006.257.09:43:28.54#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:28.54#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:28.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.09:43:28.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.09:43:28.54$vck44/valo=5,734.99 2006.257.09:43:28.54#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.09:43:28.54#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.09:43:28.54#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:28.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:28.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:28.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:28.54#ibcon#enter wrdev, iclass 29, count 0 2006.257.09:43:28.54#ibcon#first serial, iclass 29, count 0 2006.257.09:43:28.54#ibcon#enter sib2, iclass 29, count 0 2006.257.09:43:28.54#ibcon#flushed, iclass 29, count 0 2006.257.09:43:28.54#ibcon#about to write, iclass 29, count 0 2006.257.09:43:28.54#ibcon#wrote, iclass 29, count 0 2006.257.09:43:28.54#ibcon#about to read 3, iclass 29, count 0 2006.257.09:43:28.56#ibcon#read 3, iclass 29, count 0 2006.257.09:43:28.56#ibcon#about to read 4, iclass 29, count 0 2006.257.09:43:28.56#ibcon#read 4, iclass 29, count 0 2006.257.09:43:28.56#ibcon#about to read 5, iclass 29, count 0 2006.257.09:43:28.56#ibcon#read 5, iclass 29, count 0 2006.257.09:43:28.56#ibcon#about to read 6, iclass 29, count 0 2006.257.09:43:28.56#ibcon#read 6, iclass 29, count 0 2006.257.09:43:28.56#ibcon#end of sib2, iclass 29, count 0 2006.257.09:43:28.56#ibcon#*mode == 0, iclass 29, count 0 2006.257.09:43:28.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.09:43:28.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:43:28.56#ibcon#*before write, iclass 29, count 0 2006.257.09:43:28.56#ibcon#enter sib2, iclass 29, count 0 2006.257.09:43:28.56#ibcon#flushed, iclass 29, count 0 2006.257.09:43:28.56#ibcon#about to write, iclass 29, count 0 2006.257.09:43:28.56#ibcon#wrote, iclass 29, count 0 2006.257.09:43:28.56#ibcon#about to read 3, iclass 29, count 0 2006.257.09:43:28.60#ibcon#read 3, iclass 29, count 0 2006.257.09:43:28.60#ibcon#about to read 4, iclass 29, count 0 2006.257.09:43:28.60#ibcon#read 4, iclass 29, count 0 2006.257.09:43:28.60#ibcon#about to read 5, iclass 29, count 0 2006.257.09:43:28.60#ibcon#read 5, iclass 29, count 0 2006.257.09:43:28.60#ibcon#about to read 6, iclass 29, count 0 2006.257.09:43:28.60#ibcon#read 6, iclass 29, count 0 2006.257.09:43:28.60#ibcon#end of sib2, iclass 29, count 0 2006.257.09:43:28.60#ibcon#*after write, iclass 29, count 0 2006.257.09:43:28.60#ibcon#*before return 0, iclass 29, count 0 2006.257.09:43:28.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:28.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:28.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.09:43:28.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.09:43:28.60$vck44/va=5,4 2006.257.09:43:28.60#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.09:43:28.60#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.09:43:28.60#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:28.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:28.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:28.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:28.66#ibcon#enter wrdev, iclass 31, count 2 2006.257.09:43:28.66#ibcon#first serial, iclass 31, count 2 2006.257.09:43:28.66#ibcon#enter sib2, iclass 31, count 2 2006.257.09:43:28.66#ibcon#flushed, iclass 31, count 2 2006.257.09:43:28.66#ibcon#about to write, iclass 31, count 2 2006.257.09:43:28.66#ibcon#wrote, iclass 31, count 2 2006.257.09:43:28.66#ibcon#about to read 3, iclass 31, count 2 2006.257.09:43:28.68#ibcon#read 3, iclass 31, count 2 2006.257.09:43:28.68#ibcon#about to read 4, iclass 31, count 2 2006.257.09:43:28.68#ibcon#read 4, iclass 31, count 2 2006.257.09:43:28.68#ibcon#about to read 5, iclass 31, count 2 2006.257.09:43:28.68#ibcon#read 5, iclass 31, count 2 2006.257.09:43:28.68#ibcon#about to read 6, iclass 31, count 2 2006.257.09:43:28.68#ibcon#read 6, iclass 31, count 2 2006.257.09:43:28.68#ibcon#end of sib2, iclass 31, count 2 2006.257.09:43:28.68#ibcon#*mode == 0, iclass 31, count 2 2006.257.09:43:28.68#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.09:43:28.68#ibcon#[25=AT05-04\r\n] 2006.257.09:43:28.68#ibcon#*before write, iclass 31, count 2 2006.257.09:43:28.68#ibcon#enter sib2, iclass 31, count 2 2006.257.09:43:28.68#ibcon#flushed, iclass 31, count 2 2006.257.09:43:28.68#ibcon#about to write, iclass 31, count 2 2006.257.09:43:28.68#ibcon#wrote, iclass 31, count 2 2006.257.09:43:28.68#ibcon#about to read 3, iclass 31, count 2 2006.257.09:43:28.71#ibcon#read 3, iclass 31, count 2 2006.257.09:43:28.71#ibcon#about to read 4, iclass 31, count 2 2006.257.09:43:28.71#ibcon#read 4, iclass 31, count 2 2006.257.09:43:28.71#ibcon#about to read 5, iclass 31, count 2 2006.257.09:43:28.71#ibcon#read 5, iclass 31, count 2 2006.257.09:43:28.71#ibcon#about to read 6, iclass 31, count 2 2006.257.09:43:28.71#ibcon#read 6, iclass 31, count 2 2006.257.09:43:28.71#ibcon#end of sib2, iclass 31, count 2 2006.257.09:43:28.71#ibcon#*after write, iclass 31, count 2 2006.257.09:43:28.71#ibcon#*before return 0, iclass 31, count 2 2006.257.09:43:28.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:28.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:28.71#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.09:43:28.71#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:28.71#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:28.83#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:28.83#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:28.83#ibcon#enter wrdev, iclass 31, count 0 2006.257.09:43:28.83#ibcon#first serial, iclass 31, count 0 2006.257.09:43:28.83#ibcon#enter sib2, iclass 31, count 0 2006.257.09:43:28.83#ibcon#flushed, iclass 31, count 0 2006.257.09:43:28.83#ibcon#about to write, iclass 31, count 0 2006.257.09:43:28.83#ibcon#wrote, iclass 31, count 0 2006.257.09:43:28.83#ibcon#about to read 3, iclass 31, count 0 2006.257.09:43:28.85#ibcon#read 3, iclass 31, count 0 2006.257.09:43:28.85#ibcon#about to read 4, iclass 31, count 0 2006.257.09:43:28.85#ibcon#read 4, iclass 31, count 0 2006.257.09:43:28.85#ibcon#about to read 5, iclass 31, count 0 2006.257.09:43:28.85#ibcon#read 5, iclass 31, count 0 2006.257.09:43:28.85#ibcon#about to read 6, iclass 31, count 0 2006.257.09:43:28.85#ibcon#read 6, iclass 31, count 0 2006.257.09:43:28.85#ibcon#end of sib2, iclass 31, count 0 2006.257.09:43:28.85#ibcon#*mode == 0, iclass 31, count 0 2006.257.09:43:28.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.09:43:28.85#ibcon#[25=USB\r\n] 2006.257.09:43:28.85#ibcon#*before write, iclass 31, count 0 2006.257.09:43:28.85#ibcon#enter sib2, iclass 31, count 0 2006.257.09:43:28.85#ibcon#flushed, iclass 31, count 0 2006.257.09:43:28.85#ibcon#about to write, iclass 31, count 0 2006.257.09:43:28.85#ibcon#wrote, iclass 31, count 0 2006.257.09:43:28.85#ibcon#about to read 3, iclass 31, count 0 2006.257.09:43:28.88#ibcon#read 3, iclass 31, count 0 2006.257.09:43:28.88#ibcon#about to read 4, iclass 31, count 0 2006.257.09:43:28.88#ibcon#read 4, iclass 31, count 0 2006.257.09:43:28.88#ibcon#about to read 5, iclass 31, count 0 2006.257.09:43:28.88#ibcon#read 5, iclass 31, count 0 2006.257.09:43:28.88#ibcon#about to read 6, iclass 31, count 0 2006.257.09:43:28.88#ibcon#read 6, iclass 31, count 0 2006.257.09:43:28.88#ibcon#end of sib2, iclass 31, count 0 2006.257.09:43:28.88#ibcon#*after write, iclass 31, count 0 2006.257.09:43:28.88#ibcon#*before return 0, iclass 31, count 0 2006.257.09:43:28.88#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:28.88#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:28.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.09:43:28.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.09:43:28.88$vck44/valo=6,814.99 2006.257.09:43:28.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.09:43:28.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.09:43:28.88#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:28.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:28.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:28.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:28.88#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:43:28.88#ibcon#first serial, iclass 33, count 0 2006.257.09:43:28.88#ibcon#enter sib2, iclass 33, count 0 2006.257.09:43:28.88#ibcon#flushed, iclass 33, count 0 2006.257.09:43:28.88#ibcon#about to write, iclass 33, count 0 2006.257.09:43:28.88#ibcon#wrote, iclass 33, count 0 2006.257.09:43:28.88#ibcon#about to read 3, iclass 33, count 0 2006.257.09:43:28.90#ibcon#read 3, iclass 33, count 0 2006.257.09:43:28.90#ibcon#about to read 4, iclass 33, count 0 2006.257.09:43:28.90#ibcon#read 4, iclass 33, count 0 2006.257.09:43:28.90#ibcon#about to read 5, iclass 33, count 0 2006.257.09:43:28.90#ibcon#read 5, iclass 33, count 0 2006.257.09:43:28.90#ibcon#about to read 6, iclass 33, count 0 2006.257.09:43:28.90#ibcon#read 6, iclass 33, count 0 2006.257.09:43:28.90#ibcon#end of sib2, iclass 33, count 0 2006.257.09:43:28.90#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:43:28.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:43:28.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:43:28.90#ibcon#*before write, iclass 33, count 0 2006.257.09:43:28.90#ibcon#enter sib2, iclass 33, count 0 2006.257.09:43:28.90#ibcon#flushed, iclass 33, count 0 2006.257.09:43:28.90#ibcon#about to write, iclass 33, count 0 2006.257.09:43:28.90#ibcon#wrote, iclass 33, count 0 2006.257.09:43:28.90#ibcon#about to read 3, iclass 33, count 0 2006.257.09:43:28.94#ibcon#read 3, iclass 33, count 0 2006.257.09:43:28.94#ibcon#about to read 4, iclass 33, count 0 2006.257.09:43:28.94#ibcon#read 4, iclass 33, count 0 2006.257.09:43:28.94#ibcon#about to read 5, iclass 33, count 0 2006.257.09:43:28.94#ibcon#read 5, iclass 33, count 0 2006.257.09:43:28.94#ibcon#about to read 6, iclass 33, count 0 2006.257.09:43:28.94#ibcon#read 6, iclass 33, count 0 2006.257.09:43:28.94#ibcon#end of sib2, iclass 33, count 0 2006.257.09:43:28.94#ibcon#*after write, iclass 33, count 0 2006.257.09:43:28.94#ibcon#*before return 0, iclass 33, count 0 2006.257.09:43:28.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:28.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:28.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:43:28.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:43:28.94$vck44/va=6,4 2006.257.09:43:28.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.09:43:28.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.09:43:28.94#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:28.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:29.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:29.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:29.00#ibcon#enter wrdev, iclass 35, count 2 2006.257.09:43:29.00#ibcon#first serial, iclass 35, count 2 2006.257.09:43:29.00#ibcon#enter sib2, iclass 35, count 2 2006.257.09:43:29.00#ibcon#flushed, iclass 35, count 2 2006.257.09:43:29.00#ibcon#about to write, iclass 35, count 2 2006.257.09:43:29.00#ibcon#wrote, iclass 35, count 2 2006.257.09:43:29.00#ibcon#about to read 3, iclass 35, count 2 2006.257.09:43:29.02#ibcon#read 3, iclass 35, count 2 2006.257.09:43:29.02#ibcon#about to read 4, iclass 35, count 2 2006.257.09:43:29.02#ibcon#read 4, iclass 35, count 2 2006.257.09:43:29.02#ibcon#about to read 5, iclass 35, count 2 2006.257.09:43:29.02#ibcon#read 5, iclass 35, count 2 2006.257.09:43:29.02#ibcon#about to read 6, iclass 35, count 2 2006.257.09:43:29.02#ibcon#read 6, iclass 35, count 2 2006.257.09:43:29.02#ibcon#end of sib2, iclass 35, count 2 2006.257.09:43:29.02#ibcon#*mode == 0, iclass 35, count 2 2006.257.09:43:29.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.09:43:29.02#ibcon#[25=AT06-04\r\n] 2006.257.09:43:29.02#ibcon#*before write, iclass 35, count 2 2006.257.09:43:29.02#ibcon#enter sib2, iclass 35, count 2 2006.257.09:43:29.02#ibcon#flushed, iclass 35, count 2 2006.257.09:43:29.02#ibcon#about to write, iclass 35, count 2 2006.257.09:43:29.02#ibcon#wrote, iclass 35, count 2 2006.257.09:43:29.02#ibcon#about to read 3, iclass 35, count 2 2006.257.09:43:29.05#ibcon#read 3, iclass 35, count 2 2006.257.09:43:29.05#ibcon#about to read 4, iclass 35, count 2 2006.257.09:43:29.05#ibcon#read 4, iclass 35, count 2 2006.257.09:43:29.05#ibcon#about to read 5, iclass 35, count 2 2006.257.09:43:29.05#ibcon#read 5, iclass 35, count 2 2006.257.09:43:29.05#ibcon#about to read 6, iclass 35, count 2 2006.257.09:43:29.05#ibcon#read 6, iclass 35, count 2 2006.257.09:43:29.05#ibcon#end of sib2, iclass 35, count 2 2006.257.09:43:29.05#ibcon#*after write, iclass 35, count 2 2006.257.09:43:29.05#ibcon#*before return 0, iclass 35, count 2 2006.257.09:43:29.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:29.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:29.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.09:43:29.05#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:29.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:29.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:29.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:29.17#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:43:29.17#ibcon#first serial, iclass 35, count 0 2006.257.09:43:29.17#ibcon#enter sib2, iclass 35, count 0 2006.257.09:43:29.17#ibcon#flushed, iclass 35, count 0 2006.257.09:43:29.17#ibcon#about to write, iclass 35, count 0 2006.257.09:43:29.17#ibcon#wrote, iclass 35, count 0 2006.257.09:43:29.17#ibcon#about to read 3, iclass 35, count 0 2006.257.09:43:29.19#ibcon#read 3, iclass 35, count 0 2006.257.09:43:29.19#ibcon#about to read 4, iclass 35, count 0 2006.257.09:43:29.19#ibcon#read 4, iclass 35, count 0 2006.257.09:43:29.19#ibcon#about to read 5, iclass 35, count 0 2006.257.09:43:29.19#ibcon#read 5, iclass 35, count 0 2006.257.09:43:29.19#ibcon#about to read 6, iclass 35, count 0 2006.257.09:43:29.19#ibcon#read 6, iclass 35, count 0 2006.257.09:43:29.19#ibcon#end of sib2, iclass 35, count 0 2006.257.09:43:29.19#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:43:29.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:43:29.19#ibcon#[25=USB\r\n] 2006.257.09:43:29.19#ibcon#*before write, iclass 35, count 0 2006.257.09:43:29.19#ibcon#enter sib2, iclass 35, count 0 2006.257.09:43:29.19#ibcon#flushed, iclass 35, count 0 2006.257.09:43:29.19#ibcon#about to write, iclass 35, count 0 2006.257.09:43:29.19#ibcon#wrote, iclass 35, count 0 2006.257.09:43:29.19#ibcon#about to read 3, iclass 35, count 0 2006.257.09:43:29.22#ibcon#read 3, iclass 35, count 0 2006.257.09:43:29.22#ibcon#about to read 4, iclass 35, count 0 2006.257.09:43:29.22#ibcon#read 4, iclass 35, count 0 2006.257.09:43:29.22#ibcon#about to read 5, iclass 35, count 0 2006.257.09:43:29.22#ibcon#read 5, iclass 35, count 0 2006.257.09:43:29.22#ibcon#about to read 6, iclass 35, count 0 2006.257.09:43:29.22#ibcon#read 6, iclass 35, count 0 2006.257.09:43:29.22#ibcon#end of sib2, iclass 35, count 0 2006.257.09:43:29.22#ibcon#*after write, iclass 35, count 0 2006.257.09:43:29.22#ibcon#*before return 0, iclass 35, count 0 2006.257.09:43:29.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:29.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:29.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:43:29.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:43:29.22$vck44/valo=7,864.99 2006.257.09:43:29.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.09:43:29.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.09:43:29.22#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:29.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:29.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:29.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:29.22#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:43:29.22#ibcon#first serial, iclass 37, count 0 2006.257.09:43:29.22#ibcon#enter sib2, iclass 37, count 0 2006.257.09:43:29.22#ibcon#flushed, iclass 37, count 0 2006.257.09:43:29.22#ibcon#about to write, iclass 37, count 0 2006.257.09:43:29.22#ibcon#wrote, iclass 37, count 0 2006.257.09:43:29.22#ibcon#about to read 3, iclass 37, count 0 2006.257.09:43:29.24#ibcon#read 3, iclass 37, count 0 2006.257.09:43:29.24#ibcon#about to read 4, iclass 37, count 0 2006.257.09:43:29.24#ibcon#read 4, iclass 37, count 0 2006.257.09:43:29.24#ibcon#about to read 5, iclass 37, count 0 2006.257.09:43:29.24#ibcon#read 5, iclass 37, count 0 2006.257.09:43:29.24#ibcon#about to read 6, iclass 37, count 0 2006.257.09:43:29.24#ibcon#read 6, iclass 37, count 0 2006.257.09:43:29.24#ibcon#end of sib2, iclass 37, count 0 2006.257.09:43:29.24#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:43:29.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:43:29.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:43:29.24#ibcon#*before write, iclass 37, count 0 2006.257.09:43:29.24#ibcon#enter sib2, iclass 37, count 0 2006.257.09:43:29.24#ibcon#flushed, iclass 37, count 0 2006.257.09:43:29.24#ibcon#about to write, iclass 37, count 0 2006.257.09:43:29.24#ibcon#wrote, iclass 37, count 0 2006.257.09:43:29.24#ibcon#about to read 3, iclass 37, count 0 2006.257.09:43:29.28#ibcon#read 3, iclass 37, count 0 2006.257.09:43:29.28#ibcon#about to read 4, iclass 37, count 0 2006.257.09:43:29.28#ibcon#read 4, iclass 37, count 0 2006.257.09:43:29.28#ibcon#about to read 5, iclass 37, count 0 2006.257.09:43:29.28#ibcon#read 5, iclass 37, count 0 2006.257.09:43:29.28#ibcon#about to read 6, iclass 37, count 0 2006.257.09:43:29.28#ibcon#read 6, iclass 37, count 0 2006.257.09:43:29.28#ibcon#end of sib2, iclass 37, count 0 2006.257.09:43:29.28#ibcon#*after write, iclass 37, count 0 2006.257.09:43:29.28#ibcon#*before return 0, iclass 37, count 0 2006.257.09:43:29.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:29.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:29.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:43:29.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:43:29.28$vck44/va=7,4 2006.257.09:43:29.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.09:43:29.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.09:43:29.28#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:29.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:29.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:29.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:29.34#ibcon#enter wrdev, iclass 39, count 2 2006.257.09:43:29.34#ibcon#first serial, iclass 39, count 2 2006.257.09:43:29.34#ibcon#enter sib2, iclass 39, count 2 2006.257.09:43:29.34#ibcon#flushed, iclass 39, count 2 2006.257.09:43:29.34#ibcon#about to write, iclass 39, count 2 2006.257.09:43:29.34#ibcon#wrote, iclass 39, count 2 2006.257.09:43:29.34#ibcon#about to read 3, iclass 39, count 2 2006.257.09:43:29.36#ibcon#read 3, iclass 39, count 2 2006.257.09:43:29.36#ibcon#about to read 4, iclass 39, count 2 2006.257.09:43:29.36#ibcon#read 4, iclass 39, count 2 2006.257.09:43:29.36#ibcon#about to read 5, iclass 39, count 2 2006.257.09:43:29.36#ibcon#read 5, iclass 39, count 2 2006.257.09:43:29.36#ibcon#about to read 6, iclass 39, count 2 2006.257.09:43:29.36#ibcon#read 6, iclass 39, count 2 2006.257.09:43:29.36#ibcon#end of sib2, iclass 39, count 2 2006.257.09:43:29.36#ibcon#*mode == 0, iclass 39, count 2 2006.257.09:43:29.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.09:43:29.36#ibcon#[25=AT07-04\r\n] 2006.257.09:43:29.36#ibcon#*before write, iclass 39, count 2 2006.257.09:43:29.36#ibcon#enter sib2, iclass 39, count 2 2006.257.09:43:29.36#ibcon#flushed, iclass 39, count 2 2006.257.09:43:29.36#ibcon#about to write, iclass 39, count 2 2006.257.09:43:29.36#ibcon#wrote, iclass 39, count 2 2006.257.09:43:29.36#ibcon#about to read 3, iclass 39, count 2 2006.257.09:43:29.39#ibcon#read 3, iclass 39, count 2 2006.257.09:43:29.39#ibcon#about to read 4, iclass 39, count 2 2006.257.09:43:29.39#ibcon#read 4, iclass 39, count 2 2006.257.09:43:29.39#ibcon#about to read 5, iclass 39, count 2 2006.257.09:43:29.39#ibcon#read 5, iclass 39, count 2 2006.257.09:43:29.39#ibcon#about to read 6, iclass 39, count 2 2006.257.09:43:29.39#ibcon#read 6, iclass 39, count 2 2006.257.09:43:29.39#ibcon#end of sib2, iclass 39, count 2 2006.257.09:43:29.39#ibcon#*after write, iclass 39, count 2 2006.257.09:43:29.39#ibcon#*before return 0, iclass 39, count 2 2006.257.09:43:29.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:29.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:29.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.09:43:29.39#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:29.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:29.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:29.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:29.51#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:43:29.51#ibcon#first serial, iclass 39, count 0 2006.257.09:43:29.51#ibcon#enter sib2, iclass 39, count 0 2006.257.09:43:29.51#ibcon#flushed, iclass 39, count 0 2006.257.09:43:29.51#ibcon#about to write, iclass 39, count 0 2006.257.09:43:29.51#ibcon#wrote, iclass 39, count 0 2006.257.09:43:29.51#ibcon#about to read 3, iclass 39, count 0 2006.257.09:43:29.53#ibcon#read 3, iclass 39, count 0 2006.257.09:43:29.53#ibcon#about to read 4, iclass 39, count 0 2006.257.09:43:29.53#ibcon#read 4, iclass 39, count 0 2006.257.09:43:29.53#ibcon#about to read 5, iclass 39, count 0 2006.257.09:43:29.53#ibcon#read 5, iclass 39, count 0 2006.257.09:43:29.53#ibcon#about to read 6, iclass 39, count 0 2006.257.09:43:29.53#ibcon#read 6, iclass 39, count 0 2006.257.09:43:29.53#ibcon#end of sib2, iclass 39, count 0 2006.257.09:43:29.53#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:43:29.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:43:29.53#ibcon#[25=USB\r\n] 2006.257.09:43:29.53#ibcon#*before write, iclass 39, count 0 2006.257.09:43:29.53#ibcon#enter sib2, iclass 39, count 0 2006.257.09:43:29.53#ibcon#flushed, iclass 39, count 0 2006.257.09:43:29.53#ibcon#about to write, iclass 39, count 0 2006.257.09:43:29.53#ibcon#wrote, iclass 39, count 0 2006.257.09:43:29.53#ibcon#about to read 3, iclass 39, count 0 2006.257.09:43:29.56#ibcon#read 3, iclass 39, count 0 2006.257.09:43:29.56#ibcon#about to read 4, iclass 39, count 0 2006.257.09:43:29.56#ibcon#read 4, iclass 39, count 0 2006.257.09:43:29.56#ibcon#about to read 5, iclass 39, count 0 2006.257.09:43:29.56#ibcon#read 5, iclass 39, count 0 2006.257.09:43:29.56#ibcon#about to read 6, iclass 39, count 0 2006.257.09:43:29.56#ibcon#read 6, iclass 39, count 0 2006.257.09:43:29.56#ibcon#end of sib2, iclass 39, count 0 2006.257.09:43:29.56#ibcon#*after write, iclass 39, count 0 2006.257.09:43:29.56#ibcon#*before return 0, iclass 39, count 0 2006.257.09:43:29.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:29.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:29.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:43:29.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:43:29.56$vck44/valo=8,884.99 2006.257.09:43:29.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.09:43:29.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.09:43:29.56#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:29.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:29.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:29.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:29.56#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:43:29.56#ibcon#first serial, iclass 3, count 0 2006.257.09:43:29.56#ibcon#enter sib2, iclass 3, count 0 2006.257.09:43:29.56#ibcon#flushed, iclass 3, count 0 2006.257.09:43:29.56#ibcon#about to write, iclass 3, count 0 2006.257.09:43:29.56#ibcon#wrote, iclass 3, count 0 2006.257.09:43:29.56#ibcon#about to read 3, iclass 3, count 0 2006.257.09:43:29.58#ibcon#read 3, iclass 3, count 0 2006.257.09:43:29.58#ibcon#about to read 4, iclass 3, count 0 2006.257.09:43:29.58#ibcon#read 4, iclass 3, count 0 2006.257.09:43:29.58#ibcon#about to read 5, iclass 3, count 0 2006.257.09:43:29.58#ibcon#read 5, iclass 3, count 0 2006.257.09:43:29.58#ibcon#about to read 6, iclass 3, count 0 2006.257.09:43:29.58#ibcon#read 6, iclass 3, count 0 2006.257.09:43:29.58#ibcon#end of sib2, iclass 3, count 0 2006.257.09:43:29.58#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:43:29.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:43:29.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:43:29.58#ibcon#*before write, iclass 3, count 0 2006.257.09:43:29.58#ibcon#enter sib2, iclass 3, count 0 2006.257.09:43:29.58#ibcon#flushed, iclass 3, count 0 2006.257.09:43:29.58#ibcon#about to write, iclass 3, count 0 2006.257.09:43:29.58#ibcon#wrote, iclass 3, count 0 2006.257.09:43:29.58#ibcon#about to read 3, iclass 3, count 0 2006.257.09:43:29.62#ibcon#read 3, iclass 3, count 0 2006.257.09:43:29.62#ibcon#about to read 4, iclass 3, count 0 2006.257.09:43:29.62#ibcon#read 4, iclass 3, count 0 2006.257.09:43:29.62#ibcon#about to read 5, iclass 3, count 0 2006.257.09:43:29.62#ibcon#read 5, iclass 3, count 0 2006.257.09:43:29.62#ibcon#about to read 6, iclass 3, count 0 2006.257.09:43:29.62#ibcon#read 6, iclass 3, count 0 2006.257.09:43:29.62#ibcon#end of sib2, iclass 3, count 0 2006.257.09:43:29.62#ibcon#*after write, iclass 3, count 0 2006.257.09:43:29.62#ibcon#*before return 0, iclass 3, count 0 2006.257.09:43:29.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:29.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:29.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:43:29.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:43:29.62$vck44/va=8,4 2006.257.09:43:29.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.09:43:29.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.09:43:29.62#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:29.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:43:29.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:43:29.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:43:29.68#ibcon#enter wrdev, iclass 5, count 2 2006.257.09:43:29.68#ibcon#first serial, iclass 5, count 2 2006.257.09:43:29.68#ibcon#enter sib2, iclass 5, count 2 2006.257.09:43:29.68#ibcon#flushed, iclass 5, count 2 2006.257.09:43:29.68#ibcon#about to write, iclass 5, count 2 2006.257.09:43:29.68#ibcon#wrote, iclass 5, count 2 2006.257.09:43:29.68#ibcon#about to read 3, iclass 5, count 2 2006.257.09:43:29.70#ibcon#read 3, iclass 5, count 2 2006.257.09:43:29.70#ibcon#about to read 4, iclass 5, count 2 2006.257.09:43:29.70#ibcon#read 4, iclass 5, count 2 2006.257.09:43:29.70#ibcon#about to read 5, iclass 5, count 2 2006.257.09:43:29.70#ibcon#read 5, iclass 5, count 2 2006.257.09:43:29.70#ibcon#about to read 6, iclass 5, count 2 2006.257.09:43:29.70#ibcon#read 6, iclass 5, count 2 2006.257.09:43:29.70#ibcon#end of sib2, iclass 5, count 2 2006.257.09:43:29.70#ibcon#*mode == 0, iclass 5, count 2 2006.257.09:43:29.70#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.09:43:29.70#ibcon#[25=AT08-04\r\n] 2006.257.09:43:29.70#ibcon#*before write, iclass 5, count 2 2006.257.09:43:29.70#ibcon#enter sib2, iclass 5, count 2 2006.257.09:43:29.70#ibcon#flushed, iclass 5, count 2 2006.257.09:43:29.70#ibcon#about to write, iclass 5, count 2 2006.257.09:43:29.70#ibcon#wrote, iclass 5, count 2 2006.257.09:43:29.70#ibcon#about to read 3, iclass 5, count 2 2006.257.09:43:29.73#ibcon#read 3, iclass 5, count 2 2006.257.09:43:29.73#ibcon#about to read 4, iclass 5, count 2 2006.257.09:43:29.73#ibcon#read 4, iclass 5, count 2 2006.257.09:43:29.73#ibcon#about to read 5, iclass 5, count 2 2006.257.09:43:29.73#ibcon#read 5, iclass 5, count 2 2006.257.09:43:29.73#ibcon#about to read 6, iclass 5, count 2 2006.257.09:43:29.73#ibcon#read 6, iclass 5, count 2 2006.257.09:43:29.73#ibcon#end of sib2, iclass 5, count 2 2006.257.09:43:29.73#ibcon#*after write, iclass 5, count 2 2006.257.09:43:29.73#ibcon#*before return 0, iclass 5, count 2 2006.257.09:43:29.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:43:29.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.09:43:29.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.09:43:29.73#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:29.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:43:29.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:43:29.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:43:29.85#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:43:29.85#ibcon#first serial, iclass 5, count 0 2006.257.09:43:29.85#ibcon#enter sib2, iclass 5, count 0 2006.257.09:43:29.85#ibcon#flushed, iclass 5, count 0 2006.257.09:43:29.85#ibcon#about to write, iclass 5, count 0 2006.257.09:43:29.85#ibcon#wrote, iclass 5, count 0 2006.257.09:43:29.85#ibcon#about to read 3, iclass 5, count 0 2006.257.09:43:29.87#ibcon#read 3, iclass 5, count 0 2006.257.09:43:29.87#ibcon#about to read 4, iclass 5, count 0 2006.257.09:43:29.87#ibcon#read 4, iclass 5, count 0 2006.257.09:43:29.87#ibcon#about to read 5, iclass 5, count 0 2006.257.09:43:29.87#ibcon#read 5, iclass 5, count 0 2006.257.09:43:29.87#ibcon#about to read 6, iclass 5, count 0 2006.257.09:43:29.87#ibcon#read 6, iclass 5, count 0 2006.257.09:43:29.87#ibcon#end of sib2, iclass 5, count 0 2006.257.09:43:29.87#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:43:29.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:43:29.87#ibcon#[25=USB\r\n] 2006.257.09:43:29.87#ibcon#*before write, iclass 5, count 0 2006.257.09:43:29.87#ibcon#enter sib2, iclass 5, count 0 2006.257.09:43:29.87#ibcon#flushed, iclass 5, count 0 2006.257.09:43:29.87#ibcon#about to write, iclass 5, count 0 2006.257.09:43:29.87#ibcon#wrote, iclass 5, count 0 2006.257.09:43:29.87#ibcon#about to read 3, iclass 5, count 0 2006.257.09:43:29.90#ibcon#read 3, iclass 5, count 0 2006.257.09:43:29.90#ibcon#about to read 4, iclass 5, count 0 2006.257.09:43:29.90#ibcon#read 4, iclass 5, count 0 2006.257.09:43:29.90#ibcon#about to read 5, iclass 5, count 0 2006.257.09:43:29.90#ibcon#read 5, iclass 5, count 0 2006.257.09:43:29.90#ibcon#about to read 6, iclass 5, count 0 2006.257.09:43:29.90#ibcon#read 6, iclass 5, count 0 2006.257.09:43:29.90#ibcon#end of sib2, iclass 5, count 0 2006.257.09:43:29.90#ibcon#*after write, iclass 5, count 0 2006.257.09:43:29.90#ibcon#*before return 0, iclass 5, count 0 2006.257.09:43:29.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:43:29.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.09:43:29.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:43:29.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:43:29.90$vck44/vblo=1,629.99 2006.257.09:43:29.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.09:43:29.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.09:43:29.90#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:29.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:43:29.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:43:29.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:43:29.90#ibcon#enter wrdev, iclass 7, count 0 2006.257.09:43:29.90#ibcon#first serial, iclass 7, count 0 2006.257.09:43:29.90#ibcon#enter sib2, iclass 7, count 0 2006.257.09:43:29.90#ibcon#flushed, iclass 7, count 0 2006.257.09:43:29.90#ibcon#about to write, iclass 7, count 0 2006.257.09:43:29.90#ibcon#wrote, iclass 7, count 0 2006.257.09:43:29.90#ibcon#about to read 3, iclass 7, count 0 2006.257.09:43:29.92#ibcon#read 3, iclass 7, count 0 2006.257.09:43:29.92#ibcon#about to read 4, iclass 7, count 0 2006.257.09:43:29.92#ibcon#read 4, iclass 7, count 0 2006.257.09:43:29.92#ibcon#about to read 5, iclass 7, count 0 2006.257.09:43:29.92#ibcon#read 5, iclass 7, count 0 2006.257.09:43:29.92#ibcon#about to read 6, iclass 7, count 0 2006.257.09:43:29.92#ibcon#read 6, iclass 7, count 0 2006.257.09:43:29.92#ibcon#end of sib2, iclass 7, count 0 2006.257.09:43:29.92#ibcon#*mode == 0, iclass 7, count 0 2006.257.09:43:29.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.09:43:29.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:43:29.92#ibcon#*before write, iclass 7, count 0 2006.257.09:43:29.92#ibcon#enter sib2, iclass 7, count 0 2006.257.09:43:29.92#ibcon#flushed, iclass 7, count 0 2006.257.09:43:29.92#ibcon#about to write, iclass 7, count 0 2006.257.09:43:29.92#ibcon#wrote, iclass 7, count 0 2006.257.09:43:29.92#ibcon#about to read 3, iclass 7, count 0 2006.257.09:43:29.96#ibcon#read 3, iclass 7, count 0 2006.257.09:43:29.96#ibcon#about to read 4, iclass 7, count 0 2006.257.09:43:29.96#ibcon#read 4, iclass 7, count 0 2006.257.09:43:29.96#ibcon#about to read 5, iclass 7, count 0 2006.257.09:43:29.96#ibcon#read 5, iclass 7, count 0 2006.257.09:43:29.96#ibcon#about to read 6, iclass 7, count 0 2006.257.09:43:29.96#ibcon#read 6, iclass 7, count 0 2006.257.09:43:29.96#ibcon#end of sib2, iclass 7, count 0 2006.257.09:43:29.96#ibcon#*after write, iclass 7, count 0 2006.257.09:43:29.96#ibcon#*before return 0, iclass 7, count 0 2006.257.09:43:29.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:43:29.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.09:43:29.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.09:43:29.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.09:43:29.96$vck44/vb=1,4 2006.257.09:43:29.96#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.09:43:29.96#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.09:43:29.96#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:29.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:43:29.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:43:29.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:43:29.96#ibcon#enter wrdev, iclass 11, count 2 2006.257.09:43:29.96#ibcon#first serial, iclass 11, count 2 2006.257.09:43:29.96#ibcon#enter sib2, iclass 11, count 2 2006.257.09:43:29.96#ibcon#flushed, iclass 11, count 2 2006.257.09:43:29.96#ibcon#about to write, iclass 11, count 2 2006.257.09:43:29.96#ibcon#wrote, iclass 11, count 2 2006.257.09:43:29.96#ibcon#about to read 3, iclass 11, count 2 2006.257.09:43:29.98#ibcon#read 3, iclass 11, count 2 2006.257.09:43:29.98#ibcon#about to read 4, iclass 11, count 2 2006.257.09:43:29.98#ibcon#read 4, iclass 11, count 2 2006.257.09:43:29.98#ibcon#about to read 5, iclass 11, count 2 2006.257.09:43:29.98#ibcon#read 5, iclass 11, count 2 2006.257.09:43:29.98#ibcon#about to read 6, iclass 11, count 2 2006.257.09:43:29.98#ibcon#read 6, iclass 11, count 2 2006.257.09:43:29.98#ibcon#end of sib2, iclass 11, count 2 2006.257.09:43:29.98#ibcon#*mode == 0, iclass 11, count 2 2006.257.09:43:29.98#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.09:43:29.98#ibcon#[27=AT01-04\r\n] 2006.257.09:43:29.98#ibcon#*before write, iclass 11, count 2 2006.257.09:43:29.98#ibcon#enter sib2, iclass 11, count 2 2006.257.09:43:29.98#ibcon#flushed, iclass 11, count 2 2006.257.09:43:29.98#ibcon#about to write, iclass 11, count 2 2006.257.09:43:29.98#ibcon#wrote, iclass 11, count 2 2006.257.09:43:29.98#ibcon#about to read 3, iclass 11, count 2 2006.257.09:43:30.01#ibcon#read 3, iclass 11, count 2 2006.257.09:43:30.01#ibcon#about to read 4, iclass 11, count 2 2006.257.09:43:30.01#ibcon#read 4, iclass 11, count 2 2006.257.09:43:30.01#ibcon#about to read 5, iclass 11, count 2 2006.257.09:43:30.01#ibcon#read 5, iclass 11, count 2 2006.257.09:43:30.01#ibcon#about to read 6, iclass 11, count 2 2006.257.09:43:30.01#ibcon#read 6, iclass 11, count 2 2006.257.09:43:30.01#ibcon#end of sib2, iclass 11, count 2 2006.257.09:43:30.01#ibcon#*after write, iclass 11, count 2 2006.257.09:43:30.01#ibcon#*before return 0, iclass 11, count 2 2006.257.09:43:30.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:43:30.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.09:43:30.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.09:43:30.01#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:30.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:43:30.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:43:30.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:43:30.13#ibcon#enter wrdev, iclass 11, count 0 2006.257.09:43:30.13#ibcon#first serial, iclass 11, count 0 2006.257.09:43:30.13#ibcon#enter sib2, iclass 11, count 0 2006.257.09:43:30.13#ibcon#flushed, iclass 11, count 0 2006.257.09:43:30.13#ibcon#about to write, iclass 11, count 0 2006.257.09:43:30.13#ibcon#wrote, iclass 11, count 0 2006.257.09:43:30.13#ibcon#about to read 3, iclass 11, count 0 2006.257.09:43:30.15#ibcon#read 3, iclass 11, count 0 2006.257.09:43:30.15#ibcon#about to read 4, iclass 11, count 0 2006.257.09:43:30.15#ibcon#read 4, iclass 11, count 0 2006.257.09:43:30.15#ibcon#about to read 5, iclass 11, count 0 2006.257.09:43:30.15#ibcon#read 5, iclass 11, count 0 2006.257.09:43:30.15#ibcon#about to read 6, iclass 11, count 0 2006.257.09:43:30.15#ibcon#read 6, iclass 11, count 0 2006.257.09:43:30.15#ibcon#end of sib2, iclass 11, count 0 2006.257.09:43:30.15#ibcon#*mode == 0, iclass 11, count 0 2006.257.09:43:30.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.09:43:30.15#ibcon#[27=USB\r\n] 2006.257.09:43:30.15#ibcon#*before write, iclass 11, count 0 2006.257.09:43:30.15#ibcon#enter sib2, iclass 11, count 0 2006.257.09:43:30.15#ibcon#flushed, iclass 11, count 0 2006.257.09:43:30.15#ibcon#about to write, iclass 11, count 0 2006.257.09:43:30.15#ibcon#wrote, iclass 11, count 0 2006.257.09:43:30.15#ibcon#about to read 3, iclass 11, count 0 2006.257.09:43:30.18#ibcon#read 3, iclass 11, count 0 2006.257.09:43:30.18#ibcon#about to read 4, iclass 11, count 0 2006.257.09:43:30.18#ibcon#read 4, iclass 11, count 0 2006.257.09:43:30.18#ibcon#about to read 5, iclass 11, count 0 2006.257.09:43:30.18#ibcon#read 5, iclass 11, count 0 2006.257.09:43:30.18#ibcon#about to read 6, iclass 11, count 0 2006.257.09:43:30.18#ibcon#read 6, iclass 11, count 0 2006.257.09:43:30.18#ibcon#end of sib2, iclass 11, count 0 2006.257.09:43:30.18#ibcon#*after write, iclass 11, count 0 2006.257.09:43:30.18#ibcon#*before return 0, iclass 11, count 0 2006.257.09:43:30.18#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:43:30.18#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.09:43:30.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.09:43:30.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.09:43:30.18$vck44/vblo=2,634.99 2006.257.09:43:30.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.09:43:30.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.09:43:30.18#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:30.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:30.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:30.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:30.18#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:43:30.18#ibcon#first serial, iclass 13, count 0 2006.257.09:43:30.18#ibcon#enter sib2, iclass 13, count 0 2006.257.09:43:30.18#ibcon#flushed, iclass 13, count 0 2006.257.09:43:30.18#ibcon#about to write, iclass 13, count 0 2006.257.09:43:30.18#ibcon#wrote, iclass 13, count 0 2006.257.09:43:30.18#ibcon#about to read 3, iclass 13, count 0 2006.257.09:43:30.20#ibcon#read 3, iclass 13, count 0 2006.257.09:43:30.20#ibcon#about to read 4, iclass 13, count 0 2006.257.09:43:30.20#ibcon#read 4, iclass 13, count 0 2006.257.09:43:30.20#ibcon#about to read 5, iclass 13, count 0 2006.257.09:43:30.20#ibcon#read 5, iclass 13, count 0 2006.257.09:43:30.20#ibcon#about to read 6, iclass 13, count 0 2006.257.09:43:30.20#ibcon#read 6, iclass 13, count 0 2006.257.09:43:30.20#ibcon#end of sib2, iclass 13, count 0 2006.257.09:43:30.20#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:43:30.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:43:30.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:43:30.20#ibcon#*before write, iclass 13, count 0 2006.257.09:43:30.20#ibcon#enter sib2, iclass 13, count 0 2006.257.09:43:30.20#ibcon#flushed, iclass 13, count 0 2006.257.09:43:30.20#ibcon#about to write, iclass 13, count 0 2006.257.09:43:30.20#ibcon#wrote, iclass 13, count 0 2006.257.09:43:30.20#ibcon#about to read 3, iclass 13, count 0 2006.257.09:43:30.24#ibcon#read 3, iclass 13, count 0 2006.257.09:43:30.24#ibcon#about to read 4, iclass 13, count 0 2006.257.09:43:30.24#ibcon#read 4, iclass 13, count 0 2006.257.09:43:30.24#ibcon#about to read 5, iclass 13, count 0 2006.257.09:43:30.24#ibcon#read 5, iclass 13, count 0 2006.257.09:43:30.24#ibcon#about to read 6, iclass 13, count 0 2006.257.09:43:30.24#ibcon#read 6, iclass 13, count 0 2006.257.09:43:30.24#ibcon#end of sib2, iclass 13, count 0 2006.257.09:43:30.24#ibcon#*after write, iclass 13, count 0 2006.257.09:43:30.24#ibcon#*before return 0, iclass 13, count 0 2006.257.09:43:30.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:30.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:43:30.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:43:30.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:43:30.24$vck44/vb=2,5 2006.257.09:43:30.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.09:43:30.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.09:43:30.24#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:30.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:30.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:30.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:30.30#ibcon#enter wrdev, iclass 15, count 2 2006.257.09:43:30.30#ibcon#first serial, iclass 15, count 2 2006.257.09:43:30.30#ibcon#enter sib2, iclass 15, count 2 2006.257.09:43:30.30#ibcon#flushed, iclass 15, count 2 2006.257.09:43:30.30#ibcon#about to write, iclass 15, count 2 2006.257.09:43:30.30#ibcon#wrote, iclass 15, count 2 2006.257.09:43:30.30#ibcon#about to read 3, iclass 15, count 2 2006.257.09:43:30.32#ibcon#read 3, iclass 15, count 2 2006.257.09:43:30.32#ibcon#about to read 4, iclass 15, count 2 2006.257.09:43:30.32#ibcon#read 4, iclass 15, count 2 2006.257.09:43:30.32#ibcon#about to read 5, iclass 15, count 2 2006.257.09:43:30.32#ibcon#read 5, iclass 15, count 2 2006.257.09:43:30.32#ibcon#about to read 6, iclass 15, count 2 2006.257.09:43:30.32#ibcon#read 6, iclass 15, count 2 2006.257.09:43:30.32#ibcon#end of sib2, iclass 15, count 2 2006.257.09:43:30.32#ibcon#*mode == 0, iclass 15, count 2 2006.257.09:43:30.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.09:43:30.32#ibcon#[27=AT02-05\r\n] 2006.257.09:43:30.32#ibcon#*before write, iclass 15, count 2 2006.257.09:43:30.32#ibcon#enter sib2, iclass 15, count 2 2006.257.09:43:30.32#ibcon#flushed, iclass 15, count 2 2006.257.09:43:30.32#ibcon#about to write, iclass 15, count 2 2006.257.09:43:30.32#ibcon#wrote, iclass 15, count 2 2006.257.09:43:30.32#ibcon#about to read 3, iclass 15, count 2 2006.257.09:43:30.35#ibcon#read 3, iclass 15, count 2 2006.257.09:43:30.35#ibcon#about to read 4, iclass 15, count 2 2006.257.09:43:30.35#ibcon#read 4, iclass 15, count 2 2006.257.09:43:30.35#ibcon#about to read 5, iclass 15, count 2 2006.257.09:43:30.35#ibcon#read 5, iclass 15, count 2 2006.257.09:43:30.35#ibcon#about to read 6, iclass 15, count 2 2006.257.09:43:30.35#ibcon#read 6, iclass 15, count 2 2006.257.09:43:30.35#ibcon#end of sib2, iclass 15, count 2 2006.257.09:43:30.35#ibcon#*after write, iclass 15, count 2 2006.257.09:43:30.35#ibcon#*before return 0, iclass 15, count 2 2006.257.09:43:30.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:30.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.09:43:30.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.09:43:30.35#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:30.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:30.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:30.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:30.47#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:43:30.47#ibcon#first serial, iclass 15, count 0 2006.257.09:43:30.47#ibcon#enter sib2, iclass 15, count 0 2006.257.09:43:30.47#ibcon#flushed, iclass 15, count 0 2006.257.09:43:30.47#ibcon#about to write, iclass 15, count 0 2006.257.09:43:30.47#ibcon#wrote, iclass 15, count 0 2006.257.09:43:30.47#ibcon#about to read 3, iclass 15, count 0 2006.257.09:43:30.49#ibcon#read 3, iclass 15, count 0 2006.257.09:43:30.49#ibcon#about to read 4, iclass 15, count 0 2006.257.09:43:30.49#ibcon#read 4, iclass 15, count 0 2006.257.09:43:30.49#ibcon#about to read 5, iclass 15, count 0 2006.257.09:43:30.49#ibcon#read 5, iclass 15, count 0 2006.257.09:43:30.49#ibcon#about to read 6, iclass 15, count 0 2006.257.09:43:30.49#ibcon#read 6, iclass 15, count 0 2006.257.09:43:30.49#ibcon#end of sib2, iclass 15, count 0 2006.257.09:43:30.49#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:43:30.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:43:30.49#ibcon#[27=USB\r\n] 2006.257.09:43:30.49#ibcon#*before write, iclass 15, count 0 2006.257.09:43:30.49#ibcon#enter sib2, iclass 15, count 0 2006.257.09:43:30.49#ibcon#flushed, iclass 15, count 0 2006.257.09:43:30.49#ibcon#about to write, iclass 15, count 0 2006.257.09:43:30.49#ibcon#wrote, iclass 15, count 0 2006.257.09:43:30.49#ibcon#about to read 3, iclass 15, count 0 2006.257.09:43:30.52#ibcon#read 3, iclass 15, count 0 2006.257.09:43:30.52#ibcon#about to read 4, iclass 15, count 0 2006.257.09:43:30.52#ibcon#read 4, iclass 15, count 0 2006.257.09:43:30.52#ibcon#about to read 5, iclass 15, count 0 2006.257.09:43:30.52#ibcon#read 5, iclass 15, count 0 2006.257.09:43:30.52#ibcon#about to read 6, iclass 15, count 0 2006.257.09:43:30.52#ibcon#read 6, iclass 15, count 0 2006.257.09:43:30.52#ibcon#end of sib2, iclass 15, count 0 2006.257.09:43:30.52#ibcon#*after write, iclass 15, count 0 2006.257.09:43:30.52#ibcon#*before return 0, iclass 15, count 0 2006.257.09:43:30.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:30.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.09:43:30.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:43:30.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:43:30.52$vck44/vblo=3,649.99 2006.257.09:43:30.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.09:43:30.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.09:43:30.52#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:30.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:30.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:30.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:30.52#ibcon#enter wrdev, iclass 17, count 0 2006.257.09:43:30.52#ibcon#first serial, iclass 17, count 0 2006.257.09:43:30.52#ibcon#enter sib2, iclass 17, count 0 2006.257.09:43:30.52#ibcon#flushed, iclass 17, count 0 2006.257.09:43:30.52#ibcon#about to write, iclass 17, count 0 2006.257.09:43:30.52#ibcon#wrote, iclass 17, count 0 2006.257.09:43:30.52#ibcon#about to read 3, iclass 17, count 0 2006.257.09:43:30.54#ibcon#read 3, iclass 17, count 0 2006.257.09:43:30.54#ibcon#about to read 4, iclass 17, count 0 2006.257.09:43:30.54#ibcon#read 4, iclass 17, count 0 2006.257.09:43:30.54#ibcon#about to read 5, iclass 17, count 0 2006.257.09:43:30.54#ibcon#read 5, iclass 17, count 0 2006.257.09:43:30.54#ibcon#about to read 6, iclass 17, count 0 2006.257.09:43:30.54#ibcon#read 6, iclass 17, count 0 2006.257.09:43:30.54#ibcon#end of sib2, iclass 17, count 0 2006.257.09:43:30.54#ibcon#*mode == 0, iclass 17, count 0 2006.257.09:43:30.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.09:43:30.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:43:30.54#ibcon#*before write, iclass 17, count 0 2006.257.09:43:30.54#ibcon#enter sib2, iclass 17, count 0 2006.257.09:43:30.54#ibcon#flushed, iclass 17, count 0 2006.257.09:43:30.54#ibcon#about to write, iclass 17, count 0 2006.257.09:43:30.54#ibcon#wrote, iclass 17, count 0 2006.257.09:43:30.54#ibcon#about to read 3, iclass 17, count 0 2006.257.09:43:30.58#ibcon#read 3, iclass 17, count 0 2006.257.09:43:30.58#ibcon#about to read 4, iclass 17, count 0 2006.257.09:43:30.58#ibcon#read 4, iclass 17, count 0 2006.257.09:43:30.58#ibcon#about to read 5, iclass 17, count 0 2006.257.09:43:30.58#ibcon#read 5, iclass 17, count 0 2006.257.09:43:30.58#ibcon#about to read 6, iclass 17, count 0 2006.257.09:43:30.58#ibcon#read 6, iclass 17, count 0 2006.257.09:43:30.58#ibcon#end of sib2, iclass 17, count 0 2006.257.09:43:30.58#ibcon#*after write, iclass 17, count 0 2006.257.09:43:30.58#ibcon#*before return 0, iclass 17, count 0 2006.257.09:43:30.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:30.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.09:43:30.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.09:43:30.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.09:43:30.58$vck44/vb=3,4 2006.257.09:43:30.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.09:43:30.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.09:43:30.58#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:30.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:30.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:30.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:30.64#ibcon#enter wrdev, iclass 19, count 2 2006.257.09:43:30.64#ibcon#first serial, iclass 19, count 2 2006.257.09:43:30.64#ibcon#enter sib2, iclass 19, count 2 2006.257.09:43:30.64#ibcon#flushed, iclass 19, count 2 2006.257.09:43:30.64#ibcon#about to write, iclass 19, count 2 2006.257.09:43:30.64#ibcon#wrote, iclass 19, count 2 2006.257.09:43:30.64#ibcon#about to read 3, iclass 19, count 2 2006.257.09:43:30.66#ibcon#read 3, iclass 19, count 2 2006.257.09:43:30.66#ibcon#about to read 4, iclass 19, count 2 2006.257.09:43:30.66#ibcon#read 4, iclass 19, count 2 2006.257.09:43:30.66#ibcon#about to read 5, iclass 19, count 2 2006.257.09:43:30.66#ibcon#read 5, iclass 19, count 2 2006.257.09:43:30.66#ibcon#about to read 6, iclass 19, count 2 2006.257.09:43:30.66#ibcon#read 6, iclass 19, count 2 2006.257.09:43:30.66#ibcon#end of sib2, iclass 19, count 2 2006.257.09:43:30.66#ibcon#*mode == 0, iclass 19, count 2 2006.257.09:43:30.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.09:43:30.66#ibcon#[27=AT03-04\r\n] 2006.257.09:43:30.66#ibcon#*before write, iclass 19, count 2 2006.257.09:43:30.66#ibcon#enter sib2, iclass 19, count 2 2006.257.09:43:30.66#ibcon#flushed, iclass 19, count 2 2006.257.09:43:30.66#ibcon#about to write, iclass 19, count 2 2006.257.09:43:30.66#ibcon#wrote, iclass 19, count 2 2006.257.09:43:30.66#ibcon#about to read 3, iclass 19, count 2 2006.257.09:43:30.69#ibcon#read 3, iclass 19, count 2 2006.257.09:43:30.69#ibcon#about to read 4, iclass 19, count 2 2006.257.09:43:30.69#ibcon#read 4, iclass 19, count 2 2006.257.09:43:30.69#ibcon#about to read 5, iclass 19, count 2 2006.257.09:43:30.69#ibcon#read 5, iclass 19, count 2 2006.257.09:43:30.69#ibcon#about to read 6, iclass 19, count 2 2006.257.09:43:30.69#ibcon#read 6, iclass 19, count 2 2006.257.09:43:30.69#ibcon#end of sib2, iclass 19, count 2 2006.257.09:43:30.69#ibcon#*after write, iclass 19, count 2 2006.257.09:43:30.69#ibcon#*before return 0, iclass 19, count 2 2006.257.09:43:30.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:30.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.09:43:30.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.09:43:30.69#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:30.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:30.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:30.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:30.81#ibcon#enter wrdev, iclass 19, count 0 2006.257.09:43:30.81#ibcon#first serial, iclass 19, count 0 2006.257.09:43:30.81#ibcon#enter sib2, iclass 19, count 0 2006.257.09:43:30.81#ibcon#flushed, iclass 19, count 0 2006.257.09:43:30.81#ibcon#about to write, iclass 19, count 0 2006.257.09:43:30.81#ibcon#wrote, iclass 19, count 0 2006.257.09:43:30.81#ibcon#about to read 3, iclass 19, count 0 2006.257.09:43:30.83#ibcon#read 3, iclass 19, count 0 2006.257.09:43:30.83#ibcon#about to read 4, iclass 19, count 0 2006.257.09:43:30.83#ibcon#read 4, iclass 19, count 0 2006.257.09:43:30.83#ibcon#about to read 5, iclass 19, count 0 2006.257.09:43:30.83#ibcon#read 5, iclass 19, count 0 2006.257.09:43:30.83#ibcon#about to read 6, iclass 19, count 0 2006.257.09:43:30.83#ibcon#read 6, iclass 19, count 0 2006.257.09:43:30.83#ibcon#end of sib2, iclass 19, count 0 2006.257.09:43:30.83#ibcon#*mode == 0, iclass 19, count 0 2006.257.09:43:30.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.09:43:30.83#ibcon#[27=USB\r\n] 2006.257.09:43:30.83#ibcon#*before write, iclass 19, count 0 2006.257.09:43:30.83#ibcon#enter sib2, iclass 19, count 0 2006.257.09:43:30.83#ibcon#flushed, iclass 19, count 0 2006.257.09:43:30.83#ibcon#about to write, iclass 19, count 0 2006.257.09:43:30.83#ibcon#wrote, iclass 19, count 0 2006.257.09:43:30.83#ibcon#about to read 3, iclass 19, count 0 2006.257.09:43:30.86#ibcon#read 3, iclass 19, count 0 2006.257.09:43:30.86#ibcon#about to read 4, iclass 19, count 0 2006.257.09:43:30.86#ibcon#read 4, iclass 19, count 0 2006.257.09:43:30.86#ibcon#about to read 5, iclass 19, count 0 2006.257.09:43:30.86#ibcon#read 5, iclass 19, count 0 2006.257.09:43:30.86#ibcon#about to read 6, iclass 19, count 0 2006.257.09:43:30.86#ibcon#read 6, iclass 19, count 0 2006.257.09:43:30.86#ibcon#end of sib2, iclass 19, count 0 2006.257.09:43:30.86#ibcon#*after write, iclass 19, count 0 2006.257.09:43:30.86#ibcon#*before return 0, iclass 19, count 0 2006.257.09:43:30.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:30.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.09:43:30.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.09:43:30.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.09:43:30.86$vck44/vblo=4,679.99 2006.257.09:43:30.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.09:43:30.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.09:43:30.86#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:30.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:30.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:30.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:30.86#ibcon#enter wrdev, iclass 21, count 0 2006.257.09:43:30.86#ibcon#first serial, iclass 21, count 0 2006.257.09:43:30.86#ibcon#enter sib2, iclass 21, count 0 2006.257.09:43:30.86#ibcon#flushed, iclass 21, count 0 2006.257.09:43:30.86#ibcon#about to write, iclass 21, count 0 2006.257.09:43:30.86#ibcon#wrote, iclass 21, count 0 2006.257.09:43:30.86#ibcon#about to read 3, iclass 21, count 0 2006.257.09:43:30.88#ibcon#read 3, iclass 21, count 0 2006.257.09:43:30.88#ibcon#about to read 4, iclass 21, count 0 2006.257.09:43:30.88#ibcon#read 4, iclass 21, count 0 2006.257.09:43:30.88#ibcon#about to read 5, iclass 21, count 0 2006.257.09:43:30.88#ibcon#read 5, iclass 21, count 0 2006.257.09:43:30.88#ibcon#about to read 6, iclass 21, count 0 2006.257.09:43:30.88#ibcon#read 6, iclass 21, count 0 2006.257.09:43:30.88#ibcon#end of sib2, iclass 21, count 0 2006.257.09:43:30.88#ibcon#*mode == 0, iclass 21, count 0 2006.257.09:43:30.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.09:43:30.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:43:30.88#ibcon#*before write, iclass 21, count 0 2006.257.09:43:30.88#ibcon#enter sib2, iclass 21, count 0 2006.257.09:43:30.88#ibcon#flushed, iclass 21, count 0 2006.257.09:43:30.88#ibcon#about to write, iclass 21, count 0 2006.257.09:43:30.88#ibcon#wrote, iclass 21, count 0 2006.257.09:43:30.88#ibcon#about to read 3, iclass 21, count 0 2006.257.09:43:30.92#ibcon#read 3, iclass 21, count 0 2006.257.09:43:30.92#ibcon#about to read 4, iclass 21, count 0 2006.257.09:43:30.92#ibcon#read 4, iclass 21, count 0 2006.257.09:43:30.92#ibcon#about to read 5, iclass 21, count 0 2006.257.09:43:30.92#ibcon#read 5, iclass 21, count 0 2006.257.09:43:30.92#ibcon#about to read 6, iclass 21, count 0 2006.257.09:43:30.92#ibcon#read 6, iclass 21, count 0 2006.257.09:43:30.92#ibcon#end of sib2, iclass 21, count 0 2006.257.09:43:30.92#ibcon#*after write, iclass 21, count 0 2006.257.09:43:30.92#ibcon#*before return 0, iclass 21, count 0 2006.257.09:43:30.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:30.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.09:43:30.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.09:43:30.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.09:43:30.92$vck44/vb=4,5 2006.257.09:43:30.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.09:43:30.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.09:43:30.92#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:30.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:30.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:30.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:30.98#ibcon#enter wrdev, iclass 23, count 2 2006.257.09:43:30.98#ibcon#first serial, iclass 23, count 2 2006.257.09:43:30.98#ibcon#enter sib2, iclass 23, count 2 2006.257.09:43:30.98#ibcon#flushed, iclass 23, count 2 2006.257.09:43:30.98#ibcon#about to write, iclass 23, count 2 2006.257.09:43:30.98#ibcon#wrote, iclass 23, count 2 2006.257.09:43:30.98#ibcon#about to read 3, iclass 23, count 2 2006.257.09:43:31.00#ibcon#read 3, iclass 23, count 2 2006.257.09:43:31.00#ibcon#about to read 4, iclass 23, count 2 2006.257.09:43:31.00#ibcon#read 4, iclass 23, count 2 2006.257.09:43:31.00#ibcon#about to read 5, iclass 23, count 2 2006.257.09:43:31.00#ibcon#read 5, iclass 23, count 2 2006.257.09:43:31.00#ibcon#about to read 6, iclass 23, count 2 2006.257.09:43:31.00#ibcon#read 6, iclass 23, count 2 2006.257.09:43:31.00#ibcon#end of sib2, iclass 23, count 2 2006.257.09:43:31.00#ibcon#*mode == 0, iclass 23, count 2 2006.257.09:43:31.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.09:43:31.00#ibcon#[27=AT04-05\r\n] 2006.257.09:43:31.00#ibcon#*before write, iclass 23, count 2 2006.257.09:43:31.00#ibcon#enter sib2, iclass 23, count 2 2006.257.09:43:31.00#ibcon#flushed, iclass 23, count 2 2006.257.09:43:31.00#ibcon#about to write, iclass 23, count 2 2006.257.09:43:31.00#ibcon#wrote, iclass 23, count 2 2006.257.09:43:31.00#ibcon#about to read 3, iclass 23, count 2 2006.257.09:43:31.03#ibcon#read 3, iclass 23, count 2 2006.257.09:43:31.03#ibcon#about to read 4, iclass 23, count 2 2006.257.09:43:31.03#ibcon#read 4, iclass 23, count 2 2006.257.09:43:31.03#ibcon#about to read 5, iclass 23, count 2 2006.257.09:43:31.03#ibcon#read 5, iclass 23, count 2 2006.257.09:43:31.03#ibcon#about to read 6, iclass 23, count 2 2006.257.09:43:31.03#ibcon#read 6, iclass 23, count 2 2006.257.09:43:31.03#ibcon#end of sib2, iclass 23, count 2 2006.257.09:43:31.03#ibcon#*after write, iclass 23, count 2 2006.257.09:43:31.03#ibcon#*before return 0, iclass 23, count 2 2006.257.09:43:31.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:31.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:43:31.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.09:43:31.03#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:31.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:31.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:31.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:31.15#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:43:31.15#ibcon#first serial, iclass 23, count 0 2006.257.09:43:31.15#ibcon#enter sib2, iclass 23, count 0 2006.257.09:43:31.15#ibcon#flushed, iclass 23, count 0 2006.257.09:43:31.15#ibcon#about to write, iclass 23, count 0 2006.257.09:43:31.15#ibcon#wrote, iclass 23, count 0 2006.257.09:43:31.15#ibcon#about to read 3, iclass 23, count 0 2006.257.09:43:31.17#ibcon#read 3, iclass 23, count 0 2006.257.09:43:31.17#ibcon#about to read 4, iclass 23, count 0 2006.257.09:43:31.17#ibcon#read 4, iclass 23, count 0 2006.257.09:43:31.17#ibcon#about to read 5, iclass 23, count 0 2006.257.09:43:31.17#ibcon#read 5, iclass 23, count 0 2006.257.09:43:31.17#ibcon#about to read 6, iclass 23, count 0 2006.257.09:43:31.17#ibcon#read 6, iclass 23, count 0 2006.257.09:43:31.17#ibcon#end of sib2, iclass 23, count 0 2006.257.09:43:31.17#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:43:31.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:43:31.17#ibcon#[27=USB\r\n] 2006.257.09:43:31.17#ibcon#*before write, iclass 23, count 0 2006.257.09:43:31.17#ibcon#enter sib2, iclass 23, count 0 2006.257.09:43:31.17#ibcon#flushed, iclass 23, count 0 2006.257.09:43:31.17#ibcon#about to write, iclass 23, count 0 2006.257.09:43:31.17#ibcon#wrote, iclass 23, count 0 2006.257.09:43:31.17#ibcon#about to read 3, iclass 23, count 0 2006.257.09:43:31.20#ibcon#read 3, iclass 23, count 0 2006.257.09:43:31.20#ibcon#about to read 4, iclass 23, count 0 2006.257.09:43:31.20#ibcon#read 4, iclass 23, count 0 2006.257.09:43:31.20#ibcon#about to read 5, iclass 23, count 0 2006.257.09:43:31.20#ibcon#read 5, iclass 23, count 0 2006.257.09:43:31.20#ibcon#about to read 6, iclass 23, count 0 2006.257.09:43:31.20#ibcon#read 6, iclass 23, count 0 2006.257.09:43:31.20#ibcon#end of sib2, iclass 23, count 0 2006.257.09:43:31.20#ibcon#*after write, iclass 23, count 0 2006.257.09:43:31.20#ibcon#*before return 0, iclass 23, count 0 2006.257.09:43:31.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:31.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:43:31.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:43:31.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:43:31.20$vck44/vblo=5,709.99 2006.257.09:43:31.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.09:43:31.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.09:43:31.20#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:31.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:31.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:31.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:31.20#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:43:31.20#ibcon#first serial, iclass 25, count 0 2006.257.09:43:31.20#ibcon#enter sib2, iclass 25, count 0 2006.257.09:43:31.20#ibcon#flushed, iclass 25, count 0 2006.257.09:43:31.20#ibcon#about to write, iclass 25, count 0 2006.257.09:43:31.20#ibcon#wrote, iclass 25, count 0 2006.257.09:43:31.20#ibcon#about to read 3, iclass 25, count 0 2006.257.09:43:31.22#ibcon#read 3, iclass 25, count 0 2006.257.09:43:31.22#ibcon#about to read 4, iclass 25, count 0 2006.257.09:43:31.22#ibcon#read 4, iclass 25, count 0 2006.257.09:43:31.22#ibcon#about to read 5, iclass 25, count 0 2006.257.09:43:31.22#ibcon#read 5, iclass 25, count 0 2006.257.09:43:31.22#ibcon#about to read 6, iclass 25, count 0 2006.257.09:43:31.22#ibcon#read 6, iclass 25, count 0 2006.257.09:43:31.22#ibcon#end of sib2, iclass 25, count 0 2006.257.09:43:31.22#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:43:31.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:43:31.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:43:31.22#ibcon#*before write, iclass 25, count 0 2006.257.09:43:31.22#ibcon#enter sib2, iclass 25, count 0 2006.257.09:43:31.22#ibcon#flushed, iclass 25, count 0 2006.257.09:43:31.22#ibcon#about to write, iclass 25, count 0 2006.257.09:43:31.22#ibcon#wrote, iclass 25, count 0 2006.257.09:43:31.22#ibcon#about to read 3, iclass 25, count 0 2006.257.09:43:31.26#ibcon#read 3, iclass 25, count 0 2006.257.09:43:31.26#ibcon#about to read 4, iclass 25, count 0 2006.257.09:43:31.26#ibcon#read 4, iclass 25, count 0 2006.257.09:43:31.26#ibcon#about to read 5, iclass 25, count 0 2006.257.09:43:31.26#ibcon#read 5, iclass 25, count 0 2006.257.09:43:31.26#ibcon#about to read 6, iclass 25, count 0 2006.257.09:43:31.26#ibcon#read 6, iclass 25, count 0 2006.257.09:43:31.26#ibcon#end of sib2, iclass 25, count 0 2006.257.09:43:31.26#ibcon#*after write, iclass 25, count 0 2006.257.09:43:31.26#ibcon#*before return 0, iclass 25, count 0 2006.257.09:43:31.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:31.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.09:43:31.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:43:31.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:43:31.26$vck44/vb=5,4 2006.257.09:43:31.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.09:43:31.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.09:43:31.26#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:31.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:31.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:31.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:31.32#ibcon#enter wrdev, iclass 27, count 2 2006.257.09:43:31.32#ibcon#first serial, iclass 27, count 2 2006.257.09:43:31.32#ibcon#enter sib2, iclass 27, count 2 2006.257.09:43:31.32#ibcon#flushed, iclass 27, count 2 2006.257.09:43:31.32#ibcon#about to write, iclass 27, count 2 2006.257.09:43:31.32#ibcon#wrote, iclass 27, count 2 2006.257.09:43:31.32#ibcon#about to read 3, iclass 27, count 2 2006.257.09:43:31.34#ibcon#read 3, iclass 27, count 2 2006.257.09:43:31.34#ibcon#about to read 4, iclass 27, count 2 2006.257.09:43:31.34#ibcon#read 4, iclass 27, count 2 2006.257.09:43:31.34#ibcon#about to read 5, iclass 27, count 2 2006.257.09:43:31.34#ibcon#read 5, iclass 27, count 2 2006.257.09:43:31.34#ibcon#about to read 6, iclass 27, count 2 2006.257.09:43:31.34#ibcon#read 6, iclass 27, count 2 2006.257.09:43:31.34#ibcon#end of sib2, iclass 27, count 2 2006.257.09:43:31.34#ibcon#*mode == 0, iclass 27, count 2 2006.257.09:43:31.34#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.09:43:31.34#ibcon#[27=AT05-04\r\n] 2006.257.09:43:31.34#ibcon#*before write, iclass 27, count 2 2006.257.09:43:31.34#ibcon#enter sib2, iclass 27, count 2 2006.257.09:43:31.34#ibcon#flushed, iclass 27, count 2 2006.257.09:43:31.34#ibcon#about to write, iclass 27, count 2 2006.257.09:43:31.34#ibcon#wrote, iclass 27, count 2 2006.257.09:43:31.34#ibcon#about to read 3, iclass 27, count 2 2006.257.09:43:31.37#ibcon#read 3, iclass 27, count 2 2006.257.09:43:31.37#ibcon#about to read 4, iclass 27, count 2 2006.257.09:43:31.37#ibcon#read 4, iclass 27, count 2 2006.257.09:43:31.37#ibcon#about to read 5, iclass 27, count 2 2006.257.09:43:31.37#ibcon#read 5, iclass 27, count 2 2006.257.09:43:31.37#ibcon#about to read 6, iclass 27, count 2 2006.257.09:43:31.37#ibcon#read 6, iclass 27, count 2 2006.257.09:43:31.37#ibcon#end of sib2, iclass 27, count 2 2006.257.09:43:31.37#ibcon#*after write, iclass 27, count 2 2006.257.09:43:31.37#ibcon#*before return 0, iclass 27, count 2 2006.257.09:43:31.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:31.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.09:43:31.37#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.09:43:31.37#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:31.37#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:31.49#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:31.49#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:31.49#ibcon#enter wrdev, iclass 27, count 0 2006.257.09:43:31.49#ibcon#first serial, iclass 27, count 0 2006.257.09:43:31.49#ibcon#enter sib2, iclass 27, count 0 2006.257.09:43:31.49#ibcon#flushed, iclass 27, count 0 2006.257.09:43:31.49#ibcon#about to write, iclass 27, count 0 2006.257.09:43:31.49#ibcon#wrote, iclass 27, count 0 2006.257.09:43:31.49#ibcon#about to read 3, iclass 27, count 0 2006.257.09:43:31.51#ibcon#read 3, iclass 27, count 0 2006.257.09:43:31.51#ibcon#about to read 4, iclass 27, count 0 2006.257.09:43:31.51#ibcon#read 4, iclass 27, count 0 2006.257.09:43:31.51#ibcon#about to read 5, iclass 27, count 0 2006.257.09:43:31.51#ibcon#read 5, iclass 27, count 0 2006.257.09:43:31.51#ibcon#about to read 6, iclass 27, count 0 2006.257.09:43:31.51#ibcon#read 6, iclass 27, count 0 2006.257.09:43:31.51#ibcon#end of sib2, iclass 27, count 0 2006.257.09:43:31.51#ibcon#*mode == 0, iclass 27, count 0 2006.257.09:43:31.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.09:43:31.51#ibcon#[27=USB\r\n] 2006.257.09:43:31.51#ibcon#*before write, iclass 27, count 0 2006.257.09:43:31.51#ibcon#enter sib2, iclass 27, count 0 2006.257.09:43:31.51#ibcon#flushed, iclass 27, count 0 2006.257.09:43:31.51#ibcon#about to write, iclass 27, count 0 2006.257.09:43:31.51#ibcon#wrote, iclass 27, count 0 2006.257.09:43:31.51#ibcon#about to read 3, iclass 27, count 0 2006.257.09:43:31.54#ibcon#read 3, iclass 27, count 0 2006.257.09:43:31.54#ibcon#about to read 4, iclass 27, count 0 2006.257.09:43:31.54#ibcon#read 4, iclass 27, count 0 2006.257.09:43:31.54#ibcon#about to read 5, iclass 27, count 0 2006.257.09:43:31.54#ibcon#read 5, iclass 27, count 0 2006.257.09:43:31.54#ibcon#about to read 6, iclass 27, count 0 2006.257.09:43:31.54#ibcon#read 6, iclass 27, count 0 2006.257.09:43:31.54#ibcon#end of sib2, iclass 27, count 0 2006.257.09:43:31.54#ibcon#*after write, iclass 27, count 0 2006.257.09:43:31.54#ibcon#*before return 0, iclass 27, count 0 2006.257.09:43:31.54#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:31.54#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.09:43:31.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.09:43:31.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.09:43:31.54$vck44/vblo=6,719.99 2006.257.09:43:31.54#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.09:43:31.54#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.09:43:31.54#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:31.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:31.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:31.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:31.54#ibcon#enter wrdev, iclass 29, count 0 2006.257.09:43:31.54#ibcon#first serial, iclass 29, count 0 2006.257.09:43:31.54#ibcon#enter sib2, iclass 29, count 0 2006.257.09:43:31.54#ibcon#flushed, iclass 29, count 0 2006.257.09:43:31.54#ibcon#about to write, iclass 29, count 0 2006.257.09:43:31.54#ibcon#wrote, iclass 29, count 0 2006.257.09:43:31.54#ibcon#about to read 3, iclass 29, count 0 2006.257.09:43:31.56#ibcon#read 3, iclass 29, count 0 2006.257.09:43:31.56#ibcon#about to read 4, iclass 29, count 0 2006.257.09:43:31.56#ibcon#read 4, iclass 29, count 0 2006.257.09:43:31.56#ibcon#about to read 5, iclass 29, count 0 2006.257.09:43:31.56#ibcon#read 5, iclass 29, count 0 2006.257.09:43:31.56#ibcon#about to read 6, iclass 29, count 0 2006.257.09:43:31.56#ibcon#read 6, iclass 29, count 0 2006.257.09:43:31.56#ibcon#end of sib2, iclass 29, count 0 2006.257.09:43:31.56#ibcon#*mode == 0, iclass 29, count 0 2006.257.09:43:31.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.09:43:31.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:43:31.56#ibcon#*before write, iclass 29, count 0 2006.257.09:43:31.56#ibcon#enter sib2, iclass 29, count 0 2006.257.09:43:31.56#ibcon#flushed, iclass 29, count 0 2006.257.09:43:31.56#ibcon#about to write, iclass 29, count 0 2006.257.09:43:31.56#ibcon#wrote, iclass 29, count 0 2006.257.09:43:31.56#ibcon#about to read 3, iclass 29, count 0 2006.257.09:43:31.60#ibcon#read 3, iclass 29, count 0 2006.257.09:43:31.60#ibcon#about to read 4, iclass 29, count 0 2006.257.09:43:31.60#ibcon#read 4, iclass 29, count 0 2006.257.09:43:31.60#ibcon#about to read 5, iclass 29, count 0 2006.257.09:43:31.60#ibcon#read 5, iclass 29, count 0 2006.257.09:43:31.60#ibcon#about to read 6, iclass 29, count 0 2006.257.09:43:31.60#ibcon#read 6, iclass 29, count 0 2006.257.09:43:31.60#ibcon#end of sib2, iclass 29, count 0 2006.257.09:43:31.60#ibcon#*after write, iclass 29, count 0 2006.257.09:43:31.60#ibcon#*before return 0, iclass 29, count 0 2006.257.09:43:31.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:31.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.09:43:31.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.09:43:31.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.09:43:31.60$vck44/vb=6,4 2006.257.09:43:31.60#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.09:43:31.60#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.09:43:31.60#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:31.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:31.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:31.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:31.66#ibcon#enter wrdev, iclass 31, count 2 2006.257.09:43:31.66#ibcon#first serial, iclass 31, count 2 2006.257.09:43:31.66#ibcon#enter sib2, iclass 31, count 2 2006.257.09:43:31.66#ibcon#flushed, iclass 31, count 2 2006.257.09:43:31.66#ibcon#about to write, iclass 31, count 2 2006.257.09:43:31.66#ibcon#wrote, iclass 31, count 2 2006.257.09:43:31.66#ibcon#about to read 3, iclass 31, count 2 2006.257.09:43:31.68#ibcon#read 3, iclass 31, count 2 2006.257.09:43:31.68#ibcon#about to read 4, iclass 31, count 2 2006.257.09:43:31.68#ibcon#read 4, iclass 31, count 2 2006.257.09:43:31.68#ibcon#about to read 5, iclass 31, count 2 2006.257.09:43:31.68#ibcon#read 5, iclass 31, count 2 2006.257.09:43:31.68#ibcon#about to read 6, iclass 31, count 2 2006.257.09:43:31.68#ibcon#read 6, iclass 31, count 2 2006.257.09:43:31.68#ibcon#end of sib2, iclass 31, count 2 2006.257.09:43:31.68#ibcon#*mode == 0, iclass 31, count 2 2006.257.09:43:31.68#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.09:43:31.68#ibcon#[27=AT06-04\r\n] 2006.257.09:43:31.68#ibcon#*before write, iclass 31, count 2 2006.257.09:43:31.68#ibcon#enter sib2, iclass 31, count 2 2006.257.09:43:31.68#ibcon#flushed, iclass 31, count 2 2006.257.09:43:31.68#ibcon#about to write, iclass 31, count 2 2006.257.09:43:31.68#ibcon#wrote, iclass 31, count 2 2006.257.09:43:31.68#ibcon#about to read 3, iclass 31, count 2 2006.257.09:43:31.71#ibcon#read 3, iclass 31, count 2 2006.257.09:43:31.72#ibcon#about to read 4, iclass 31, count 2 2006.257.09:43:31.72#ibcon#read 4, iclass 31, count 2 2006.257.09:43:31.72#ibcon#about to read 5, iclass 31, count 2 2006.257.09:43:31.72#ibcon#read 5, iclass 31, count 2 2006.257.09:43:31.72#ibcon#about to read 6, iclass 31, count 2 2006.257.09:43:31.72#ibcon#read 6, iclass 31, count 2 2006.257.09:43:31.72#ibcon#end of sib2, iclass 31, count 2 2006.257.09:43:31.72#ibcon#*after write, iclass 31, count 2 2006.257.09:43:31.72#ibcon#*before return 0, iclass 31, count 2 2006.257.09:43:31.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:31.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.09:43:31.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.09:43:31.72#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:31.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:31.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:31.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:31.84#ibcon#enter wrdev, iclass 31, count 0 2006.257.09:43:31.84#ibcon#first serial, iclass 31, count 0 2006.257.09:43:31.84#ibcon#enter sib2, iclass 31, count 0 2006.257.09:43:31.84#ibcon#flushed, iclass 31, count 0 2006.257.09:43:31.84#ibcon#about to write, iclass 31, count 0 2006.257.09:43:31.84#ibcon#wrote, iclass 31, count 0 2006.257.09:43:31.84#ibcon#about to read 3, iclass 31, count 0 2006.257.09:43:31.86#ibcon#read 3, iclass 31, count 0 2006.257.09:43:31.86#ibcon#about to read 4, iclass 31, count 0 2006.257.09:43:31.86#ibcon#read 4, iclass 31, count 0 2006.257.09:43:31.86#ibcon#about to read 5, iclass 31, count 0 2006.257.09:43:31.86#ibcon#read 5, iclass 31, count 0 2006.257.09:43:31.86#ibcon#about to read 6, iclass 31, count 0 2006.257.09:43:31.86#ibcon#read 6, iclass 31, count 0 2006.257.09:43:31.86#ibcon#end of sib2, iclass 31, count 0 2006.257.09:43:31.86#ibcon#*mode == 0, iclass 31, count 0 2006.257.09:43:31.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.09:43:31.86#ibcon#[27=USB\r\n] 2006.257.09:43:31.86#ibcon#*before write, iclass 31, count 0 2006.257.09:43:31.86#ibcon#enter sib2, iclass 31, count 0 2006.257.09:43:31.86#ibcon#flushed, iclass 31, count 0 2006.257.09:43:31.86#ibcon#about to write, iclass 31, count 0 2006.257.09:43:31.86#ibcon#wrote, iclass 31, count 0 2006.257.09:43:31.86#ibcon#about to read 3, iclass 31, count 0 2006.257.09:43:31.89#ibcon#read 3, iclass 31, count 0 2006.257.09:43:31.89#ibcon#about to read 4, iclass 31, count 0 2006.257.09:43:31.89#ibcon#read 4, iclass 31, count 0 2006.257.09:43:31.89#ibcon#about to read 5, iclass 31, count 0 2006.257.09:43:31.89#ibcon#read 5, iclass 31, count 0 2006.257.09:43:31.89#ibcon#about to read 6, iclass 31, count 0 2006.257.09:43:31.89#ibcon#read 6, iclass 31, count 0 2006.257.09:43:31.89#ibcon#end of sib2, iclass 31, count 0 2006.257.09:43:31.89#ibcon#*after write, iclass 31, count 0 2006.257.09:43:31.89#ibcon#*before return 0, iclass 31, count 0 2006.257.09:43:31.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:31.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.09:43:31.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.09:43:31.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.09:43:31.89$vck44/vblo=7,734.99 2006.257.09:43:31.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.09:43:31.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.09:43:31.89#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:31.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:31.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:31.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:31.89#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:43:31.89#ibcon#first serial, iclass 33, count 0 2006.257.09:43:31.89#ibcon#enter sib2, iclass 33, count 0 2006.257.09:43:31.89#ibcon#flushed, iclass 33, count 0 2006.257.09:43:31.89#ibcon#about to write, iclass 33, count 0 2006.257.09:43:31.89#ibcon#wrote, iclass 33, count 0 2006.257.09:43:31.89#ibcon#about to read 3, iclass 33, count 0 2006.257.09:43:31.91#ibcon#read 3, iclass 33, count 0 2006.257.09:43:31.91#ibcon#about to read 4, iclass 33, count 0 2006.257.09:43:31.91#ibcon#read 4, iclass 33, count 0 2006.257.09:43:31.91#ibcon#about to read 5, iclass 33, count 0 2006.257.09:43:31.91#ibcon#read 5, iclass 33, count 0 2006.257.09:43:31.91#ibcon#about to read 6, iclass 33, count 0 2006.257.09:43:31.91#ibcon#read 6, iclass 33, count 0 2006.257.09:43:31.91#ibcon#end of sib2, iclass 33, count 0 2006.257.09:43:31.91#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:43:31.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:43:31.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:43:31.91#ibcon#*before write, iclass 33, count 0 2006.257.09:43:31.91#ibcon#enter sib2, iclass 33, count 0 2006.257.09:43:31.91#ibcon#flushed, iclass 33, count 0 2006.257.09:43:31.91#ibcon#about to write, iclass 33, count 0 2006.257.09:43:31.91#ibcon#wrote, iclass 33, count 0 2006.257.09:43:31.91#ibcon#about to read 3, iclass 33, count 0 2006.257.09:43:31.95#ibcon#read 3, iclass 33, count 0 2006.257.09:43:31.95#ibcon#about to read 4, iclass 33, count 0 2006.257.09:43:31.95#ibcon#read 4, iclass 33, count 0 2006.257.09:43:31.95#ibcon#about to read 5, iclass 33, count 0 2006.257.09:43:31.95#ibcon#read 5, iclass 33, count 0 2006.257.09:43:31.95#ibcon#about to read 6, iclass 33, count 0 2006.257.09:43:31.95#ibcon#read 6, iclass 33, count 0 2006.257.09:43:31.95#ibcon#end of sib2, iclass 33, count 0 2006.257.09:43:31.95#ibcon#*after write, iclass 33, count 0 2006.257.09:43:31.95#ibcon#*before return 0, iclass 33, count 0 2006.257.09:43:31.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:31.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.09:43:31.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:43:31.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:43:31.95$vck44/vb=7,4 2006.257.09:43:31.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.09:43:31.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.09:43:31.95#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:31.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:32.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:32.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:32.01#ibcon#enter wrdev, iclass 35, count 2 2006.257.09:43:32.01#ibcon#first serial, iclass 35, count 2 2006.257.09:43:32.01#ibcon#enter sib2, iclass 35, count 2 2006.257.09:43:32.01#ibcon#flushed, iclass 35, count 2 2006.257.09:43:32.01#ibcon#about to write, iclass 35, count 2 2006.257.09:43:32.01#ibcon#wrote, iclass 35, count 2 2006.257.09:43:32.01#ibcon#about to read 3, iclass 35, count 2 2006.257.09:43:32.03#ibcon#read 3, iclass 35, count 2 2006.257.09:43:32.03#ibcon#about to read 4, iclass 35, count 2 2006.257.09:43:32.03#ibcon#read 4, iclass 35, count 2 2006.257.09:43:32.03#ibcon#about to read 5, iclass 35, count 2 2006.257.09:43:32.03#ibcon#read 5, iclass 35, count 2 2006.257.09:43:32.03#ibcon#about to read 6, iclass 35, count 2 2006.257.09:43:32.03#ibcon#read 6, iclass 35, count 2 2006.257.09:43:32.03#ibcon#end of sib2, iclass 35, count 2 2006.257.09:43:32.03#ibcon#*mode == 0, iclass 35, count 2 2006.257.09:43:32.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.09:43:32.03#ibcon#[27=AT07-04\r\n] 2006.257.09:43:32.03#ibcon#*before write, iclass 35, count 2 2006.257.09:43:32.03#ibcon#enter sib2, iclass 35, count 2 2006.257.09:43:32.03#ibcon#flushed, iclass 35, count 2 2006.257.09:43:32.03#ibcon#about to write, iclass 35, count 2 2006.257.09:43:32.03#ibcon#wrote, iclass 35, count 2 2006.257.09:43:32.03#ibcon#about to read 3, iclass 35, count 2 2006.257.09:43:32.06#ibcon#read 3, iclass 35, count 2 2006.257.09:43:32.06#ibcon#about to read 4, iclass 35, count 2 2006.257.09:43:32.06#ibcon#read 4, iclass 35, count 2 2006.257.09:43:32.06#ibcon#about to read 5, iclass 35, count 2 2006.257.09:43:32.06#ibcon#read 5, iclass 35, count 2 2006.257.09:43:32.06#ibcon#about to read 6, iclass 35, count 2 2006.257.09:43:32.06#ibcon#read 6, iclass 35, count 2 2006.257.09:43:32.06#ibcon#end of sib2, iclass 35, count 2 2006.257.09:43:32.06#ibcon#*after write, iclass 35, count 2 2006.257.09:43:32.06#ibcon#*before return 0, iclass 35, count 2 2006.257.09:43:32.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:32.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.09:43:32.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.09:43:32.06#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:32.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:32.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:32.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:32.18#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:43:32.18#ibcon#first serial, iclass 35, count 0 2006.257.09:43:32.18#ibcon#enter sib2, iclass 35, count 0 2006.257.09:43:32.18#ibcon#flushed, iclass 35, count 0 2006.257.09:43:32.18#ibcon#about to write, iclass 35, count 0 2006.257.09:43:32.18#ibcon#wrote, iclass 35, count 0 2006.257.09:43:32.18#ibcon#about to read 3, iclass 35, count 0 2006.257.09:43:32.20#ibcon#read 3, iclass 35, count 0 2006.257.09:43:32.20#ibcon#about to read 4, iclass 35, count 0 2006.257.09:43:32.20#ibcon#read 4, iclass 35, count 0 2006.257.09:43:32.20#ibcon#about to read 5, iclass 35, count 0 2006.257.09:43:32.20#ibcon#read 5, iclass 35, count 0 2006.257.09:43:32.20#ibcon#about to read 6, iclass 35, count 0 2006.257.09:43:32.20#ibcon#read 6, iclass 35, count 0 2006.257.09:43:32.20#ibcon#end of sib2, iclass 35, count 0 2006.257.09:43:32.20#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:43:32.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:43:32.20#ibcon#[27=USB\r\n] 2006.257.09:43:32.20#ibcon#*before write, iclass 35, count 0 2006.257.09:43:32.20#ibcon#enter sib2, iclass 35, count 0 2006.257.09:43:32.20#ibcon#flushed, iclass 35, count 0 2006.257.09:43:32.20#ibcon#about to write, iclass 35, count 0 2006.257.09:43:32.20#ibcon#wrote, iclass 35, count 0 2006.257.09:43:32.20#ibcon#about to read 3, iclass 35, count 0 2006.257.09:43:32.23#ibcon#read 3, iclass 35, count 0 2006.257.09:43:32.23#ibcon#about to read 4, iclass 35, count 0 2006.257.09:43:32.23#ibcon#read 4, iclass 35, count 0 2006.257.09:43:32.23#ibcon#about to read 5, iclass 35, count 0 2006.257.09:43:32.23#ibcon#read 5, iclass 35, count 0 2006.257.09:43:32.23#ibcon#about to read 6, iclass 35, count 0 2006.257.09:43:32.23#ibcon#read 6, iclass 35, count 0 2006.257.09:43:32.23#ibcon#end of sib2, iclass 35, count 0 2006.257.09:43:32.23#ibcon#*after write, iclass 35, count 0 2006.257.09:43:32.23#ibcon#*before return 0, iclass 35, count 0 2006.257.09:43:32.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:32.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.09:43:32.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:43:32.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:43:32.23$vck44/vblo=8,744.99 2006.257.09:43:32.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.09:43:32.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.09:43:32.23#ibcon#ireg 17 cls_cnt 0 2006.257.09:43:32.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:32.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:32.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:32.23#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:43:32.23#ibcon#first serial, iclass 37, count 0 2006.257.09:43:32.23#ibcon#enter sib2, iclass 37, count 0 2006.257.09:43:32.23#ibcon#flushed, iclass 37, count 0 2006.257.09:43:32.23#ibcon#about to write, iclass 37, count 0 2006.257.09:43:32.23#ibcon#wrote, iclass 37, count 0 2006.257.09:43:32.23#ibcon#about to read 3, iclass 37, count 0 2006.257.09:43:32.25#ibcon#read 3, iclass 37, count 0 2006.257.09:43:32.25#ibcon#about to read 4, iclass 37, count 0 2006.257.09:43:32.25#ibcon#read 4, iclass 37, count 0 2006.257.09:43:32.25#ibcon#about to read 5, iclass 37, count 0 2006.257.09:43:32.25#ibcon#read 5, iclass 37, count 0 2006.257.09:43:32.25#ibcon#about to read 6, iclass 37, count 0 2006.257.09:43:32.25#ibcon#read 6, iclass 37, count 0 2006.257.09:43:32.25#ibcon#end of sib2, iclass 37, count 0 2006.257.09:43:32.25#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:43:32.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:43:32.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:43:32.25#ibcon#*before write, iclass 37, count 0 2006.257.09:43:32.25#ibcon#enter sib2, iclass 37, count 0 2006.257.09:43:32.25#ibcon#flushed, iclass 37, count 0 2006.257.09:43:32.25#ibcon#about to write, iclass 37, count 0 2006.257.09:43:32.25#ibcon#wrote, iclass 37, count 0 2006.257.09:43:32.25#ibcon#about to read 3, iclass 37, count 0 2006.257.09:43:32.29#ibcon#read 3, iclass 37, count 0 2006.257.09:43:32.29#ibcon#about to read 4, iclass 37, count 0 2006.257.09:43:32.29#ibcon#read 4, iclass 37, count 0 2006.257.09:43:32.29#ibcon#about to read 5, iclass 37, count 0 2006.257.09:43:32.29#ibcon#read 5, iclass 37, count 0 2006.257.09:43:32.29#ibcon#about to read 6, iclass 37, count 0 2006.257.09:43:32.29#ibcon#read 6, iclass 37, count 0 2006.257.09:43:32.29#ibcon#end of sib2, iclass 37, count 0 2006.257.09:43:32.29#ibcon#*after write, iclass 37, count 0 2006.257.09:43:32.29#ibcon#*before return 0, iclass 37, count 0 2006.257.09:43:32.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:32.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.09:43:32.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:43:32.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:43:32.29$vck44/vb=8,4 2006.257.09:43:32.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.09:43:32.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.09:43:32.29#ibcon#ireg 11 cls_cnt 2 2006.257.09:43:32.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:32.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:32.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:32.35#ibcon#enter wrdev, iclass 39, count 2 2006.257.09:43:32.35#ibcon#first serial, iclass 39, count 2 2006.257.09:43:32.35#ibcon#enter sib2, iclass 39, count 2 2006.257.09:43:32.35#ibcon#flushed, iclass 39, count 2 2006.257.09:43:32.35#ibcon#about to write, iclass 39, count 2 2006.257.09:43:32.35#ibcon#wrote, iclass 39, count 2 2006.257.09:43:32.35#ibcon#about to read 3, iclass 39, count 2 2006.257.09:43:32.37#ibcon#read 3, iclass 39, count 2 2006.257.09:43:32.37#ibcon#about to read 4, iclass 39, count 2 2006.257.09:43:32.37#ibcon#read 4, iclass 39, count 2 2006.257.09:43:32.37#ibcon#about to read 5, iclass 39, count 2 2006.257.09:43:32.37#ibcon#read 5, iclass 39, count 2 2006.257.09:43:32.37#ibcon#about to read 6, iclass 39, count 2 2006.257.09:43:32.37#ibcon#read 6, iclass 39, count 2 2006.257.09:43:32.37#ibcon#end of sib2, iclass 39, count 2 2006.257.09:43:32.37#ibcon#*mode == 0, iclass 39, count 2 2006.257.09:43:32.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.09:43:32.37#ibcon#[27=AT08-04\r\n] 2006.257.09:43:32.37#ibcon#*before write, iclass 39, count 2 2006.257.09:43:32.37#ibcon#enter sib2, iclass 39, count 2 2006.257.09:43:32.37#ibcon#flushed, iclass 39, count 2 2006.257.09:43:32.37#ibcon#about to write, iclass 39, count 2 2006.257.09:43:32.37#ibcon#wrote, iclass 39, count 2 2006.257.09:43:32.37#ibcon#about to read 3, iclass 39, count 2 2006.257.09:43:32.40#ibcon#read 3, iclass 39, count 2 2006.257.09:43:32.40#ibcon#about to read 4, iclass 39, count 2 2006.257.09:43:32.40#ibcon#read 4, iclass 39, count 2 2006.257.09:43:32.40#ibcon#about to read 5, iclass 39, count 2 2006.257.09:43:32.40#ibcon#read 5, iclass 39, count 2 2006.257.09:43:32.40#ibcon#about to read 6, iclass 39, count 2 2006.257.09:43:32.40#ibcon#read 6, iclass 39, count 2 2006.257.09:43:32.40#ibcon#end of sib2, iclass 39, count 2 2006.257.09:43:32.40#ibcon#*after write, iclass 39, count 2 2006.257.09:43:32.40#ibcon#*before return 0, iclass 39, count 2 2006.257.09:43:32.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:32.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.09:43:32.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.09:43:32.40#ibcon#ireg 7 cls_cnt 0 2006.257.09:43:32.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:32.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:32.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:32.52#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:43:32.52#ibcon#first serial, iclass 39, count 0 2006.257.09:43:32.52#ibcon#enter sib2, iclass 39, count 0 2006.257.09:43:32.52#ibcon#flushed, iclass 39, count 0 2006.257.09:43:32.52#ibcon#about to write, iclass 39, count 0 2006.257.09:43:32.52#ibcon#wrote, iclass 39, count 0 2006.257.09:43:32.52#ibcon#about to read 3, iclass 39, count 0 2006.257.09:43:32.54#ibcon#read 3, iclass 39, count 0 2006.257.09:43:32.54#ibcon#about to read 4, iclass 39, count 0 2006.257.09:43:32.54#ibcon#read 4, iclass 39, count 0 2006.257.09:43:32.54#ibcon#about to read 5, iclass 39, count 0 2006.257.09:43:32.54#ibcon#read 5, iclass 39, count 0 2006.257.09:43:32.54#ibcon#about to read 6, iclass 39, count 0 2006.257.09:43:32.54#ibcon#read 6, iclass 39, count 0 2006.257.09:43:32.54#ibcon#end of sib2, iclass 39, count 0 2006.257.09:43:32.54#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:43:32.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:43:32.54#ibcon#[27=USB\r\n] 2006.257.09:43:32.54#ibcon#*before write, iclass 39, count 0 2006.257.09:43:32.54#ibcon#enter sib2, iclass 39, count 0 2006.257.09:43:32.54#ibcon#flushed, iclass 39, count 0 2006.257.09:43:32.54#ibcon#about to write, iclass 39, count 0 2006.257.09:43:32.54#ibcon#wrote, iclass 39, count 0 2006.257.09:43:32.54#ibcon#about to read 3, iclass 39, count 0 2006.257.09:43:32.57#ibcon#read 3, iclass 39, count 0 2006.257.09:43:32.57#ibcon#about to read 4, iclass 39, count 0 2006.257.09:43:32.57#ibcon#read 4, iclass 39, count 0 2006.257.09:43:32.57#ibcon#about to read 5, iclass 39, count 0 2006.257.09:43:32.57#ibcon#read 5, iclass 39, count 0 2006.257.09:43:32.57#ibcon#about to read 6, iclass 39, count 0 2006.257.09:43:32.57#ibcon#read 6, iclass 39, count 0 2006.257.09:43:32.57#ibcon#end of sib2, iclass 39, count 0 2006.257.09:43:32.57#ibcon#*after write, iclass 39, count 0 2006.257.09:43:32.57#ibcon#*before return 0, iclass 39, count 0 2006.257.09:43:32.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:32.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.09:43:32.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:43:32.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:43:32.57$vck44/vabw=wide 2006.257.09:43:32.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.09:43:32.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.09:43:32.57#ibcon#ireg 8 cls_cnt 0 2006.257.09:43:32.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:32.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:32.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:32.57#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:43:32.57#ibcon#first serial, iclass 3, count 0 2006.257.09:43:32.57#ibcon#enter sib2, iclass 3, count 0 2006.257.09:43:32.57#ibcon#flushed, iclass 3, count 0 2006.257.09:43:32.57#ibcon#about to write, iclass 3, count 0 2006.257.09:43:32.57#ibcon#wrote, iclass 3, count 0 2006.257.09:43:32.57#ibcon#about to read 3, iclass 3, count 0 2006.257.09:43:32.59#ibcon#read 3, iclass 3, count 0 2006.257.09:43:32.59#ibcon#about to read 4, iclass 3, count 0 2006.257.09:43:32.59#ibcon#read 4, iclass 3, count 0 2006.257.09:43:32.59#ibcon#about to read 5, iclass 3, count 0 2006.257.09:43:32.59#ibcon#read 5, iclass 3, count 0 2006.257.09:43:32.59#ibcon#about to read 6, iclass 3, count 0 2006.257.09:43:32.59#ibcon#read 6, iclass 3, count 0 2006.257.09:43:32.59#ibcon#end of sib2, iclass 3, count 0 2006.257.09:43:32.59#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:43:32.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:43:32.59#ibcon#[25=BW32\r\n] 2006.257.09:43:32.59#ibcon#*before write, iclass 3, count 0 2006.257.09:43:32.59#ibcon#enter sib2, iclass 3, count 0 2006.257.09:43:32.59#ibcon#flushed, iclass 3, count 0 2006.257.09:43:32.59#ibcon#about to write, iclass 3, count 0 2006.257.09:43:32.59#ibcon#wrote, iclass 3, count 0 2006.257.09:43:32.59#ibcon#about to read 3, iclass 3, count 0 2006.257.09:43:32.62#ibcon#read 3, iclass 3, count 0 2006.257.09:43:32.62#ibcon#about to read 4, iclass 3, count 0 2006.257.09:43:32.62#ibcon#read 4, iclass 3, count 0 2006.257.09:43:32.62#ibcon#about to read 5, iclass 3, count 0 2006.257.09:43:32.62#ibcon#read 5, iclass 3, count 0 2006.257.09:43:32.62#ibcon#about to read 6, iclass 3, count 0 2006.257.09:43:32.62#ibcon#read 6, iclass 3, count 0 2006.257.09:43:32.62#ibcon#end of sib2, iclass 3, count 0 2006.257.09:43:32.62#ibcon#*after write, iclass 3, count 0 2006.257.09:43:32.62#ibcon#*before return 0, iclass 3, count 0 2006.257.09:43:32.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:32.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.09:43:32.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:43:32.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:43:32.62$vck44/vbbw=wide 2006.257.09:43:32.62#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.09:43:32.62#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.09:43:32.62#ibcon#ireg 8 cls_cnt 0 2006.257.09:43:32.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:43:32.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:43:32.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:43:32.69#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:43:32.69#ibcon#first serial, iclass 5, count 0 2006.257.09:43:32.69#ibcon#enter sib2, iclass 5, count 0 2006.257.09:43:32.69#ibcon#flushed, iclass 5, count 0 2006.257.09:43:32.69#ibcon#about to write, iclass 5, count 0 2006.257.09:43:32.69#ibcon#wrote, iclass 5, count 0 2006.257.09:43:32.69#ibcon#about to read 3, iclass 5, count 0 2006.257.09:43:32.71#ibcon#read 3, iclass 5, count 0 2006.257.09:43:32.71#ibcon#about to read 4, iclass 5, count 0 2006.257.09:43:32.71#ibcon#read 4, iclass 5, count 0 2006.257.09:43:32.71#ibcon#about to read 5, iclass 5, count 0 2006.257.09:43:32.71#ibcon#read 5, iclass 5, count 0 2006.257.09:43:32.71#ibcon#about to read 6, iclass 5, count 0 2006.257.09:43:32.71#ibcon#read 6, iclass 5, count 0 2006.257.09:43:32.71#ibcon#end of sib2, iclass 5, count 0 2006.257.09:43:32.71#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:43:32.71#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:43:32.71#ibcon#[27=BW32\r\n] 2006.257.09:43:32.71#ibcon#*before write, iclass 5, count 0 2006.257.09:43:32.71#ibcon#enter sib2, iclass 5, count 0 2006.257.09:43:32.71#ibcon#flushed, iclass 5, count 0 2006.257.09:43:32.71#ibcon#about to write, iclass 5, count 0 2006.257.09:43:32.71#ibcon#wrote, iclass 5, count 0 2006.257.09:43:32.71#ibcon#about to read 3, iclass 5, count 0 2006.257.09:43:32.74#ibcon#read 3, iclass 5, count 0 2006.257.09:43:32.74#ibcon#about to read 4, iclass 5, count 0 2006.257.09:43:32.74#ibcon#read 4, iclass 5, count 0 2006.257.09:43:32.74#ibcon#about to read 5, iclass 5, count 0 2006.257.09:43:32.74#ibcon#read 5, iclass 5, count 0 2006.257.09:43:32.74#ibcon#about to read 6, iclass 5, count 0 2006.257.09:43:32.74#ibcon#read 6, iclass 5, count 0 2006.257.09:43:32.74#ibcon#end of sib2, iclass 5, count 0 2006.257.09:43:32.74#ibcon#*after write, iclass 5, count 0 2006.257.09:43:32.74#ibcon#*before return 0, iclass 5, count 0 2006.257.09:43:32.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:43:32.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:43:32.74#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:43:32.74#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:43:32.74$setupk4/ifdk4 2006.257.09:43:32.74$ifdk4/lo= 2006.257.09:43:32.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:43:32.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:43:32.74$ifdk4/patch= 2006.257.09:43:32.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:43:32.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:43:32.75$setupk4/!*+20s 2006.257.09:43:33.80#abcon#<5=/14 0.9 2.2 19.42 961013.3\r\n> 2006.257.09:43:33.82#abcon#{5=INTERFACE CLEAR} 2006.257.09:43:33.88#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:43:35.14#trakl#Source acquired 2006.257.09:43:37.14#flagr#flagr/antenna,acquired 2006.257.09:43:43.97#abcon#<5=/14 0.9 2.2 19.41 961013.3\r\n> 2006.257.09:43:43.99#abcon#{5=INTERFACE CLEAR} 2006.257.09:43:44.05#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:43:47.26$setupk4/"tpicd 2006.257.09:43:47.26$setupk4/echo=off 2006.257.09:43:47.26$setupk4/xlog=off 2006.257.09:43:47.26:!2006.257.09:47:14 2006.257.09:47:14.00:preob 2006.257.09:47:14.14/onsource/TRACKING 2006.257.09:47:14.14:!2006.257.09:47:24 2006.257.09:47:24.00:"tape 2006.257.09:47:24.00:"st=record 2006.257.09:47:24.00:data_valid=on 2006.257.09:47:24.00:midob 2006.257.09:47:25.14/onsource/TRACKING 2006.257.09:47:25.14/wx/19.38,1013.4,96 2006.257.09:47:25.27/cable/+6.4739E-03 2006.257.09:47:26.36/va/01,08,usb,yes,31,33 2006.257.09:47:26.36/va/02,07,usb,yes,33,33 2006.257.09:47:26.36/va/03,08,usb,yes,30,31 2006.257.09:47:26.36/va/04,07,usb,yes,34,36 2006.257.09:47:26.36/va/05,04,usb,yes,30,31 2006.257.09:47:26.36/va/06,04,usb,yes,34,34 2006.257.09:47:26.36/va/07,04,usb,yes,35,35 2006.257.09:47:26.36/va/08,04,usb,yes,29,36 2006.257.09:47:26.59/valo/01,524.99,yes,locked 2006.257.09:47:26.59/valo/02,534.99,yes,locked 2006.257.09:47:26.59/valo/03,564.99,yes,locked 2006.257.09:47:26.59/valo/04,624.99,yes,locked 2006.257.09:47:26.59/valo/05,734.99,yes,locked 2006.257.09:47:26.59/valo/06,814.99,yes,locked 2006.257.09:47:26.59/valo/07,864.99,yes,locked 2006.257.09:47:26.59/valo/08,884.99,yes,locked 2006.257.09:47:27.68/vb/01,04,usb,yes,30,28 2006.257.09:47:27.68/vb/02,05,usb,yes,28,28 2006.257.09:47:27.68/vb/03,04,usb,yes,29,32 2006.257.09:47:27.68/vb/04,05,usb,yes,30,29 2006.257.09:47:27.68/vb/05,04,usb,yes,26,28 2006.257.09:47:27.68/vb/06,04,usb,yes,31,27 2006.257.09:47:27.68/vb/07,04,usb,yes,30,30 2006.257.09:47:27.68/vb/08,04,usb,yes,28,31 2006.257.09:47:27.92/vblo/01,629.99,yes,locked 2006.257.09:47:27.92/vblo/02,634.99,yes,locked 2006.257.09:47:27.92/vblo/03,649.99,yes,locked 2006.257.09:47:27.92/vblo/04,679.99,yes,locked 2006.257.09:47:27.92/vblo/05,709.99,yes,locked 2006.257.09:47:27.92/vblo/06,719.99,yes,locked 2006.257.09:47:27.92/vblo/07,734.99,yes,locked 2006.257.09:47:27.92/vblo/08,744.99,yes,locked 2006.257.09:47:28.07/vabw/8 2006.257.09:47:28.22/vbbw/8 2006.257.09:47:28.31/xfe/off,on,14.7 2006.257.09:47:28.70/ifatt/23,28,28,28 2006.257.09:47:29.07/fmout-gps/S +4.65E-07 2006.257.09:47:29.11:!2006.257.09:48:44 2006.257.09:48:44.01:data_valid=off 2006.257.09:48:44.02:"et 2006.257.09:48:44.02:!+3s 2006.257.09:48:47.03:"tape 2006.257.09:48:47.04:postob 2006.257.09:48:47.19/cable/+6.4739E-03 2006.257.09:48:47.20/wx/19.36,1013.4,96 2006.257.09:48:47.25/fmout-gps/S +4.65E-07 2006.257.09:48:47.26:scan_name=257-0950,jd0609,40 2006.257.09:48:47.26:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.257.09:48:48.13#flagr#flagr/antenna,new-source 2006.257.09:48:48.14:checkk5 2006.257.09:48:48.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:48:48.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:48:49.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:48:49.81/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:48:50.20/chk_obsdata//k5ts1/T2570947??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.09:48:50.61/chk_obsdata//k5ts2/T2570947??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.09:48:51.01/chk_obsdata//k5ts3/T2570947??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.09:48:51.42/chk_obsdata//k5ts4/T2570947??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.09:48:52.13/k5log//k5ts1_log_newline 2006.257.09:48:52.84/k5log//k5ts2_log_newline 2006.257.09:48:53.56/k5log//k5ts3_log_newline 2006.257.09:48:54.28/k5log//k5ts4_log_newline 2006.257.09:48:54.30/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:48:54.30:setupk4=1 2006.257.09:48:54.30$setupk4/echo=on 2006.257.09:48:54.30$setupk4/pcalon 2006.257.09:48:54.30$pcalon/"no phase cal control is implemented here 2006.257.09:48:54.30$setupk4/"tpicd=stop 2006.257.09:48:54.30$setupk4/"rec=synch_on 2006.257.09:48:54.30$setupk4/"rec_mode=128 2006.257.09:48:54.30$setupk4/!* 2006.257.09:48:54.30$setupk4/recpk4 2006.257.09:48:54.30$recpk4/recpatch= 2006.257.09:48:54.30$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:48:54.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:48:54.31$setupk4/vck44 2006.257.09:48:54.31$vck44/valo=1,524.99 2006.257.09:48:54.31#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.09:48:54.31#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.09:48:54.31#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:54.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:54.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:54.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:54.31#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:48:54.31#ibcon#first serial, iclass 32, count 0 2006.257.09:48:54.31#ibcon#enter sib2, iclass 32, count 0 2006.257.09:48:54.31#ibcon#flushed, iclass 32, count 0 2006.257.09:48:54.31#ibcon#about to write, iclass 32, count 0 2006.257.09:48:54.31#ibcon#wrote, iclass 32, count 0 2006.257.09:48:54.31#ibcon#about to read 3, iclass 32, count 0 2006.257.09:48:54.32#ibcon#read 3, iclass 32, count 0 2006.257.09:48:54.32#ibcon#about to read 4, iclass 32, count 0 2006.257.09:48:54.32#ibcon#read 4, iclass 32, count 0 2006.257.09:48:54.32#ibcon#about to read 5, iclass 32, count 0 2006.257.09:48:54.32#ibcon#read 5, iclass 32, count 0 2006.257.09:48:54.32#ibcon#about to read 6, iclass 32, count 0 2006.257.09:48:54.32#ibcon#read 6, iclass 32, count 0 2006.257.09:48:54.32#ibcon#end of sib2, iclass 32, count 0 2006.257.09:48:54.32#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:48:54.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:48:54.32#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:48:54.32#ibcon#*before write, iclass 32, count 0 2006.257.09:48:54.32#ibcon#enter sib2, iclass 32, count 0 2006.257.09:48:54.32#ibcon#flushed, iclass 32, count 0 2006.257.09:48:54.32#ibcon#about to write, iclass 32, count 0 2006.257.09:48:54.32#ibcon#wrote, iclass 32, count 0 2006.257.09:48:54.32#ibcon#about to read 3, iclass 32, count 0 2006.257.09:48:54.37#ibcon#read 3, iclass 32, count 0 2006.257.09:48:54.37#ibcon#about to read 4, iclass 32, count 0 2006.257.09:48:54.37#ibcon#read 4, iclass 32, count 0 2006.257.09:48:54.37#ibcon#about to read 5, iclass 32, count 0 2006.257.09:48:54.37#ibcon#read 5, iclass 32, count 0 2006.257.09:48:54.37#ibcon#about to read 6, iclass 32, count 0 2006.257.09:48:54.37#ibcon#read 6, iclass 32, count 0 2006.257.09:48:54.37#ibcon#end of sib2, iclass 32, count 0 2006.257.09:48:54.37#ibcon#*after write, iclass 32, count 0 2006.257.09:48:54.37#ibcon#*before return 0, iclass 32, count 0 2006.257.09:48:54.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:54.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:54.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:48:54.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:48:54.37$vck44/va=1,8 2006.257.09:48:54.37#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.09:48:54.37#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.09:48:54.37#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:54.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:54.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:54.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:54.37#ibcon#enter wrdev, iclass 34, count 2 2006.257.09:48:54.37#ibcon#first serial, iclass 34, count 2 2006.257.09:48:54.37#ibcon#enter sib2, iclass 34, count 2 2006.257.09:48:54.37#ibcon#flushed, iclass 34, count 2 2006.257.09:48:54.37#ibcon#about to write, iclass 34, count 2 2006.257.09:48:54.37#ibcon#wrote, iclass 34, count 2 2006.257.09:48:54.37#ibcon#about to read 3, iclass 34, count 2 2006.257.09:48:54.39#ibcon#read 3, iclass 34, count 2 2006.257.09:48:54.39#ibcon#about to read 4, iclass 34, count 2 2006.257.09:48:54.39#ibcon#read 4, iclass 34, count 2 2006.257.09:48:54.39#ibcon#about to read 5, iclass 34, count 2 2006.257.09:48:54.39#ibcon#read 5, iclass 34, count 2 2006.257.09:48:54.39#ibcon#about to read 6, iclass 34, count 2 2006.257.09:48:54.39#ibcon#read 6, iclass 34, count 2 2006.257.09:48:54.39#ibcon#end of sib2, iclass 34, count 2 2006.257.09:48:54.39#ibcon#*mode == 0, iclass 34, count 2 2006.257.09:48:54.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.09:48:54.39#ibcon#[25=AT01-08\r\n] 2006.257.09:48:54.39#ibcon#*before write, iclass 34, count 2 2006.257.09:48:54.39#ibcon#enter sib2, iclass 34, count 2 2006.257.09:48:54.39#ibcon#flushed, iclass 34, count 2 2006.257.09:48:54.39#ibcon#about to write, iclass 34, count 2 2006.257.09:48:54.39#ibcon#wrote, iclass 34, count 2 2006.257.09:48:54.39#ibcon#about to read 3, iclass 34, count 2 2006.257.09:48:54.42#ibcon#read 3, iclass 34, count 2 2006.257.09:48:54.42#ibcon#about to read 4, iclass 34, count 2 2006.257.09:48:54.42#ibcon#read 4, iclass 34, count 2 2006.257.09:48:54.42#ibcon#about to read 5, iclass 34, count 2 2006.257.09:48:54.42#ibcon#read 5, iclass 34, count 2 2006.257.09:48:54.42#ibcon#about to read 6, iclass 34, count 2 2006.257.09:48:54.42#ibcon#read 6, iclass 34, count 2 2006.257.09:48:54.42#ibcon#end of sib2, iclass 34, count 2 2006.257.09:48:54.42#ibcon#*after write, iclass 34, count 2 2006.257.09:48:54.42#ibcon#*before return 0, iclass 34, count 2 2006.257.09:48:54.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:54.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:54.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.09:48:54.42#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:54.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:54.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:54.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:54.54#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:48:54.54#ibcon#first serial, iclass 34, count 0 2006.257.09:48:54.54#ibcon#enter sib2, iclass 34, count 0 2006.257.09:48:54.54#ibcon#flushed, iclass 34, count 0 2006.257.09:48:54.54#ibcon#about to write, iclass 34, count 0 2006.257.09:48:54.54#ibcon#wrote, iclass 34, count 0 2006.257.09:48:54.54#ibcon#about to read 3, iclass 34, count 0 2006.257.09:48:54.56#ibcon#read 3, iclass 34, count 0 2006.257.09:48:54.56#ibcon#about to read 4, iclass 34, count 0 2006.257.09:48:54.56#ibcon#read 4, iclass 34, count 0 2006.257.09:48:54.56#ibcon#about to read 5, iclass 34, count 0 2006.257.09:48:54.56#ibcon#read 5, iclass 34, count 0 2006.257.09:48:54.56#ibcon#about to read 6, iclass 34, count 0 2006.257.09:48:54.56#ibcon#read 6, iclass 34, count 0 2006.257.09:48:54.56#ibcon#end of sib2, iclass 34, count 0 2006.257.09:48:54.56#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:48:54.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:48:54.56#ibcon#[25=USB\r\n] 2006.257.09:48:54.56#ibcon#*before write, iclass 34, count 0 2006.257.09:48:54.56#ibcon#enter sib2, iclass 34, count 0 2006.257.09:48:54.56#ibcon#flushed, iclass 34, count 0 2006.257.09:48:54.56#ibcon#about to write, iclass 34, count 0 2006.257.09:48:54.56#ibcon#wrote, iclass 34, count 0 2006.257.09:48:54.56#ibcon#about to read 3, iclass 34, count 0 2006.257.09:48:54.59#ibcon#read 3, iclass 34, count 0 2006.257.09:48:54.59#ibcon#about to read 4, iclass 34, count 0 2006.257.09:48:54.59#ibcon#read 4, iclass 34, count 0 2006.257.09:48:54.59#ibcon#about to read 5, iclass 34, count 0 2006.257.09:48:54.59#ibcon#read 5, iclass 34, count 0 2006.257.09:48:54.59#ibcon#about to read 6, iclass 34, count 0 2006.257.09:48:54.59#ibcon#read 6, iclass 34, count 0 2006.257.09:48:54.59#ibcon#end of sib2, iclass 34, count 0 2006.257.09:48:54.59#ibcon#*after write, iclass 34, count 0 2006.257.09:48:54.59#ibcon#*before return 0, iclass 34, count 0 2006.257.09:48:54.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:54.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:54.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:48:54.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:48:54.59$vck44/valo=2,534.99 2006.257.09:48:54.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.09:48:54.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.09:48:54.59#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:54.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:54.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:54.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:54.59#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:48:54.59#ibcon#first serial, iclass 36, count 0 2006.257.09:48:54.59#ibcon#enter sib2, iclass 36, count 0 2006.257.09:48:54.59#ibcon#flushed, iclass 36, count 0 2006.257.09:48:54.59#ibcon#about to write, iclass 36, count 0 2006.257.09:48:54.59#ibcon#wrote, iclass 36, count 0 2006.257.09:48:54.59#ibcon#about to read 3, iclass 36, count 0 2006.257.09:48:54.61#ibcon#read 3, iclass 36, count 0 2006.257.09:48:54.61#ibcon#about to read 4, iclass 36, count 0 2006.257.09:48:54.61#ibcon#read 4, iclass 36, count 0 2006.257.09:48:54.61#ibcon#about to read 5, iclass 36, count 0 2006.257.09:48:54.61#ibcon#read 5, iclass 36, count 0 2006.257.09:48:54.61#ibcon#about to read 6, iclass 36, count 0 2006.257.09:48:54.61#ibcon#read 6, iclass 36, count 0 2006.257.09:48:54.61#ibcon#end of sib2, iclass 36, count 0 2006.257.09:48:54.61#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:48:54.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:48:54.61#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:48:54.61#ibcon#*before write, iclass 36, count 0 2006.257.09:48:54.61#ibcon#enter sib2, iclass 36, count 0 2006.257.09:48:54.61#ibcon#flushed, iclass 36, count 0 2006.257.09:48:54.61#ibcon#about to write, iclass 36, count 0 2006.257.09:48:54.61#ibcon#wrote, iclass 36, count 0 2006.257.09:48:54.61#ibcon#about to read 3, iclass 36, count 0 2006.257.09:48:54.65#ibcon#read 3, iclass 36, count 0 2006.257.09:48:54.65#ibcon#about to read 4, iclass 36, count 0 2006.257.09:48:54.65#ibcon#read 4, iclass 36, count 0 2006.257.09:48:54.65#ibcon#about to read 5, iclass 36, count 0 2006.257.09:48:54.65#ibcon#read 5, iclass 36, count 0 2006.257.09:48:54.65#ibcon#about to read 6, iclass 36, count 0 2006.257.09:48:54.65#ibcon#read 6, iclass 36, count 0 2006.257.09:48:54.65#ibcon#end of sib2, iclass 36, count 0 2006.257.09:48:54.65#ibcon#*after write, iclass 36, count 0 2006.257.09:48:54.65#ibcon#*before return 0, iclass 36, count 0 2006.257.09:48:54.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:54.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:54.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:48:54.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:48:54.65$vck44/va=2,7 2006.257.09:48:54.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.09:48:54.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.09:48:54.65#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:54.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:54.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:54.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:54.71#ibcon#enter wrdev, iclass 38, count 2 2006.257.09:48:54.71#ibcon#first serial, iclass 38, count 2 2006.257.09:48:54.71#ibcon#enter sib2, iclass 38, count 2 2006.257.09:48:54.71#ibcon#flushed, iclass 38, count 2 2006.257.09:48:54.71#ibcon#about to write, iclass 38, count 2 2006.257.09:48:54.71#ibcon#wrote, iclass 38, count 2 2006.257.09:48:54.71#ibcon#about to read 3, iclass 38, count 2 2006.257.09:48:54.73#ibcon#read 3, iclass 38, count 2 2006.257.09:48:54.73#ibcon#about to read 4, iclass 38, count 2 2006.257.09:48:54.73#ibcon#read 4, iclass 38, count 2 2006.257.09:48:54.73#ibcon#about to read 5, iclass 38, count 2 2006.257.09:48:54.73#ibcon#read 5, iclass 38, count 2 2006.257.09:48:54.73#ibcon#about to read 6, iclass 38, count 2 2006.257.09:48:54.73#ibcon#read 6, iclass 38, count 2 2006.257.09:48:54.73#ibcon#end of sib2, iclass 38, count 2 2006.257.09:48:54.73#ibcon#*mode == 0, iclass 38, count 2 2006.257.09:48:54.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.09:48:54.73#ibcon#[25=AT02-07\r\n] 2006.257.09:48:54.73#ibcon#*before write, iclass 38, count 2 2006.257.09:48:54.73#ibcon#enter sib2, iclass 38, count 2 2006.257.09:48:54.73#ibcon#flushed, iclass 38, count 2 2006.257.09:48:54.73#ibcon#about to write, iclass 38, count 2 2006.257.09:48:54.73#ibcon#wrote, iclass 38, count 2 2006.257.09:48:54.73#ibcon#about to read 3, iclass 38, count 2 2006.257.09:48:54.76#ibcon#read 3, iclass 38, count 2 2006.257.09:48:54.76#ibcon#about to read 4, iclass 38, count 2 2006.257.09:48:54.76#ibcon#read 4, iclass 38, count 2 2006.257.09:48:54.76#ibcon#about to read 5, iclass 38, count 2 2006.257.09:48:54.76#ibcon#read 5, iclass 38, count 2 2006.257.09:48:54.76#ibcon#about to read 6, iclass 38, count 2 2006.257.09:48:54.76#ibcon#read 6, iclass 38, count 2 2006.257.09:48:54.76#ibcon#end of sib2, iclass 38, count 2 2006.257.09:48:54.76#ibcon#*after write, iclass 38, count 2 2006.257.09:48:54.76#ibcon#*before return 0, iclass 38, count 2 2006.257.09:48:54.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:54.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:54.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.09:48:54.76#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:54.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:54.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:54.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:54.88#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:48:54.88#ibcon#first serial, iclass 38, count 0 2006.257.09:48:54.88#ibcon#enter sib2, iclass 38, count 0 2006.257.09:48:54.88#ibcon#flushed, iclass 38, count 0 2006.257.09:48:54.88#ibcon#about to write, iclass 38, count 0 2006.257.09:48:54.88#ibcon#wrote, iclass 38, count 0 2006.257.09:48:54.88#ibcon#about to read 3, iclass 38, count 0 2006.257.09:48:54.90#ibcon#read 3, iclass 38, count 0 2006.257.09:48:54.90#ibcon#about to read 4, iclass 38, count 0 2006.257.09:48:54.90#ibcon#read 4, iclass 38, count 0 2006.257.09:48:54.90#ibcon#about to read 5, iclass 38, count 0 2006.257.09:48:54.90#ibcon#read 5, iclass 38, count 0 2006.257.09:48:54.90#ibcon#about to read 6, iclass 38, count 0 2006.257.09:48:54.90#ibcon#read 6, iclass 38, count 0 2006.257.09:48:54.90#ibcon#end of sib2, iclass 38, count 0 2006.257.09:48:54.90#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:48:54.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:48:54.90#ibcon#[25=USB\r\n] 2006.257.09:48:54.90#ibcon#*before write, iclass 38, count 0 2006.257.09:48:54.90#ibcon#enter sib2, iclass 38, count 0 2006.257.09:48:54.90#ibcon#flushed, iclass 38, count 0 2006.257.09:48:54.90#ibcon#about to write, iclass 38, count 0 2006.257.09:48:54.90#ibcon#wrote, iclass 38, count 0 2006.257.09:48:54.90#ibcon#about to read 3, iclass 38, count 0 2006.257.09:48:54.93#ibcon#read 3, iclass 38, count 0 2006.257.09:48:54.93#ibcon#about to read 4, iclass 38, count 0 2006.257.09:48:54.93#ibcon#read 4, iclass 38, count 0 2006.257.09:48:54.93#ibcon#about to read 5, iclass 38, count 0 2006.257.09:48:54.93#ibcon#read 5, iclass 38, count 0 2006.257.09:48:54.93#ibcon#about to read 6, iclass 38, count 0 2006.257.09:48:54.93#ibcon#read 6, iclass 38, count 0 2006.257.09:48:54.93#ibcon#end of sib2, iclass 38, count 0 2006.257.09:48:54.93#ibcon#*after write, iclass 38, count 0 2006.257.09:48:54.93#ibcon#*before return 0, iclass 38, count 0 2006.257.09:48:54.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:54.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:54.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:48:54.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:48:54.93$vck44/valo=3,564.99 2006.257.09:48:54.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.09:48:54.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.09:48:54.93#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:54.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:54.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:54.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:54.93#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:48:54.93#ibcon#first serial, iclass 40, count 0 2006.257.09:48:54.93#ibcon#enter sib2, iclass 40, count 0 2006.257.09:48:54.93#ibcon#flushed, iclass 40, count 0 2006.257.09:48:54.93#ibcon#about to write, iclass 40, count 0 2006.257.09:48:54.93#ibcon#wrote, iclass 40, count 0 2006.257.09:48:54.93#ibcon#about to read 3, iclass 40, count 0 2006.257.09:48:54.95#ibcon#read 3, iclass 40, count 0 2006.257.09:48:54.95#ibcon#about to read 4, iclass 40, count 0 2006.257.09:48:54.95#ibcon#read 4, iclass 40, count 0 2006.257.09:48:54.95#ibcon#about to read 5, iclass 40, count 0 2006.257.09:48:54.95#ibcon#read 5, iclass 40, count 0 2006.257.09:48:54.95#ibcon#about to read 6, iclass 40, count 0 2006.257.09:48:54.95#ibcon#read 6, iclass 40, count 0 2006.257.09:48:54.95#ibcon#end of sib2, iclass 40, count 0 2006.257.09:48:54.95#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:48:54.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:48:54.95#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:48:54.95#ibcon#*before write, iclass 40, count 0 2006.257.09:48:54.95#ibcon#enter sib2, iclass 40, count 0 2006.257.09:48:54.95#ibcon#flushed, iclass 40, count 0 2006.257.09:48:54.95#ibcon#about to write, iclass 40, count 0 2006.257.09:48:54.95#ibcon#wrote, iclass 40, count 0 2006.257.09:48:54.95#ibcon#about to read 3, iclass 40, count 0 2006.257.09:48:54.99#ibcon#read 3, iclass 40, count 0 2006.257.09:48:54.99#ibcon#about to read 4, iclass 40, count 0 2006.257.09:48:54.99#ibcon#read 4, iclass 40, count 0 2006.257.09:48:54.99#ibcon#about to read 5, iclass 40, count 0 2006.257.09:48:54.99#ibcon#read 5, iclass 40, count 0 2006.257.09:48:54.99#ibcon#about to read 6, iclass 40, count 0 2006.257.09:48:54.99#ibcon#read 6, iclass 40, count 0 2006.257.09:48:54.99#ibcon#end of sib2, iclass 40, count 0 2006.257.09:48:54.99#ibcon#*after write, iclass 40, count 0 2006.257.09:48:54.99#ibcon#*before return 0, iclass 40, count 0 2006.257.09:48:54.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:54.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:54.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:48:54.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:48:54.99$vck44/va=3,8 2006.257.09:48:54.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.09:48:54.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.09:48:54.99#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:54.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:55.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:55.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:55.05#ibcon#enter wrdev, iclass 4, count 2 2006.257.09:48:55.05#ibcon#first serial, iclass 4, count 2 2006.257.09:48:55.05#ibcon#enter sib2, iclass 4, count 2 2006.257.09:48:55.05#ibcon#flushed, iclass 4, count 2 2006.257.09:48:55.05#ibcon#about to write, iclass 4, count 2 2006.257.09:48:55.05#ibcon#wrote, iclass 4, count 2 2006.257.09:48:55.05#ibcon#about to read 3, iclass 4, count 2 2006.257.09:48:55.07#ibcon#read 3, iclass 4, count 2 2006.257.09:48:55.07#ibcon#about to read 4, iclass 4, count 2 2006.257.09:48:55.07#ibcon#read 4, iclass 4, count 2 2006.257.09:48:55.07#ibcon#about to read 5, iclass 4, count 2 2006.257.09:48:55.07#ibcon#read 5, iclass 4, count 2 2006.257.09:48:55.07#ibcon#about to read 6, iclass 4, count 2 2006.257.09:48:55.07#ibcon#read 6, iclass 4, count 2 2006.257.09:48:55.07#ibcon#end of sib2, iclass 4, count 2 2006.257.09:48:55.07#ibcon#*mode == 0, iclass 4, count 2 2006.257.09:48:55.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.09:48:55.07#ibcon#[25=AT03-08\r\n] 2006.257.09:48:55.07#ibcon#*before write, iclass 4, count 2 2006.257.09:48:55.07#ibcon#enter sib2, iclass 4, count 2 2006.257.09:48:55.07#ibcon#flushed, iclass 4, count 2 2006.257.09:48:55.07#ibcon#about to write, iclass 4, count 2 2006.257.09:48:55.07#ibcon#wrote, iclass 4, count 2 2006.257.09:48:55.07#ibcon#about to read 3, iclass 4, count 2 2006.257.09:48:55.10#ibcon#read 3, iclass 4, count 2 2006.257.09:48:55.10#ibcon#about to read 4, iclass 4, count 2 2006.257.09:48:55.10#ibcon#read 4, iclass 4, count 2 2006.257.09:48:55.10#ibcon#about to read 5, iclass 4, count 2 2006.257.09:48:55.10#ibcon#read 5, iclass 4, count 2 2006.257.09:48:55.10#ibcon#about to read 6, iclass 4, count 2 2006.257.09:48:55.10#ibcon#read 6, iclass 4, count 2 2006.257.09:48:55.10#ibcon#end of sib2, iclass 4, count 2 2006.257.09:48:55.10#ibcon#*after write, iclass 4, count 2 2006.257.09:48:55.10#ibcon#*before return 0, iclass 4, count 2 2006.257.09:48:55.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:55.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:55.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.09:48:55.10#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:55.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:55.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:55.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:55.22#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:48:55.22#ibcon#first serial, iclass 4, count 0 2006.257.09:48:55.22#ibcon#enter sib2, iclass 4, count 0 2006.257.09:48:55.22#ibcon#flushed, iclass 4, count 0 2006.257.09:48:55.22#ibcon#about to write, iclass 4, count 0 2006.257.09:48:55.22#ibcon#wrote, iclass 4, count 0 2006.257.09:48:55.22#ibcon#about to read 3, iclass 4, count 0 2006.257.09:48:55.24#ibcon#read 3, iclass 4, count 0 2006.257.09:48:55.24#ibcon#about to read 4, iclass 4, count 0 2006.257.09:48:55.24#ibcon#read 4, iclass 4, count 0 2006.257.09:48:55.24#ibcon#about to read 5, iclass 4, count 0 2006.257.09:48:55.24#ibcon#read 5, iclass 4, count 0 2006.257.09:48:55.24#ibcon#about to read 6, iclass 4, count 0 2006.257.09:48:55.24#ibcon#read 6, iclass 4, count 0 2006.257.09:48:55.24#ibcon#end of sib2, iclass 4, count 0 2006.257.09:48:55.24#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:48:55.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:48:55.24#ibcon#[25=USB\r\n] 2006.257.09:48:55.24#ibcon#*before write, iclass 4, count 0 2006.257.09:48:55.24#ibcon#enter sib2, iclass 4, count 0 2006.257.09:48:55.24#ibcon#flushed, iclass 4, count 0 2006.257.09:48:55.24#ibcon#about to write, iclass 4, count 0 2006.257.09:48:55.24#ibcon#wrote, iclass 4, count 0 2006.257.09:48:55.24#ibcon#about to read 3, iclass 4, count 0 2006.257.09:48:55.27#ibcon#read 3, iclass 4, count 0 2006.257.09:48:55.27#ibcon#about to read 4, iclass 4, count 0 2006.257.09:48:55.27#ibcon#read 4, iclass 4, count 0 2006.257.09:48:55.27#ibcon#about to read 5, iclass 4, count 0 2006.257.09:48:55.27#ibcon#read 5, iclass 4, count 0 2006.257.09:48:55.27#ibcon#about to read 6, iclass 4, count 0 2006.257.09:48:55.27#ibcon#read 6, iclass 4, count 0 2006.257.09:48:55.27#ibcon#end of sib2, iclass 4, count 0 2006.257.09:48:55.27#ibcon#*after write, iclass 4, count 0 2006.257.09:48:55.27#ibcon#*before return 0, iclass 4, count 0 2006.257.09:48:55.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:55.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:55.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:48:55.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:48:55.27$vck44/valo=4,624.99 2006.257.09:48:55.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.09:48:55.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.09:48:55.27#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:55.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:55.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:55.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:55.27#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:48:55.27#ibcon#first serial, iclass 6, count 0 2006.257.09:48:55.27#ibcon#enter sib2, iclass 6, count 0 2006.257.09:48:55.27#ibcon#flushed, iclass 6, count 0 2006.257.09:48:55.27#ibcon#about to write, iclass 6, count 0 2006.257.09:48:55.27#ibcon#wrote, iclass 6, count 0 2006.257.09:48:55.27#ibcon#about to read 3, iclass 6, count 0 2006.257.09:48:55.29#ibcon#read 3, iclass 6, count 0 2006.257.09:48:55.29#ibcon#about to read 4, iclass 6, count 0 2006.257.09:48:55.29#ibcon#read 4, iclass 6, count 0 2006.257.09:48:55.29#ibcon#about to read 5, iclass 6, count 0 2006.257.09:48:55.29#ibcon#read 5, iclass 6, count 0 2006.257.09:48:55.29#ibcon#about to read 6, iclass 6, count 0 2006.257.09:48:55.29#ibcon#read 6, iclass 6, count 0 2006.257.09:48:55.29#ibcon#end of sib2, iclass 6, count 0 2006.257.09:48:55.29#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:48:55.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:48:55.29#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:48:55.29#ibcon#*before write, iclass 6, count 0 2006.257.09:48:55.29#ibcon#enter sib2, iclass 6, count 0 2006.257.09:48:55.29#ibcon#flushed, iclass 6, count 0 2006.257.09:48:55.29#ibcon#about to write, iclass 6, count 0 2006.257.09:48:55.29#ibcon#wrote, iclass 6, count 0 2006.257.09:48:55.29#ibcon#about to read 3, iclass 6, count 0 2006.257.09:48:55.33#ibcon#read 3, iclass 6, count 0 2006.257.09:48:55.33#ibcon#about to read 4, iclass 6, count 0 2006.257.09:48:55.33#ibcon#read 4, iclass 6, count 0 2006.257.09:48:55.33#ibcon#about to read 5, iclass 6, count 0 2006.257.09:48:55.33#ibcon#read 5, iclass 6, count 0 2006.257.09:48:55.33#ibcon#about to read 6, iclass 6, count 0 2006.257.09:48:55.33#ibcon#read 6, iclass 6, count 0 2006.257.09:48:55.33#ibcon#end of sib2, iclass 6, count 0 2006.257.09:48:55.33#ibcon#*after write, iclass 6, count 0 2006.257.09:48:55.33#ibcon#*before return 0, iclass 6, count 0 2006.257.09:48:55.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:55.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:55.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:48:55.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:48:55.33$vck44/va=4,7 2006.257.09:48:55.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.09:48:55.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.09:48:55.33#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:55.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:55.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:55.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:55.39#ibcon#enter wrdev, iclass 10, count 2 2006.257.09:48:55.39#ibcon#first serial, iclass 10, count 2 2006.257.09:48:55.39#ibcon#enter sib2, iclass 10, count 2 2006.257.09:48:55.39#ibcon#flushed, iclass 10, count 2 2006.257.09:48:55.39#ibcon#about to write, iclass 10, count 2 2006.257.09:48:55.39#ibcon#wrote, iclass 10, count 2 2006.257.09:48:55.39#ibcon#about to read 3, iclass 10, count 2 2006.257.09:48:55.41#ibcon#read 3, iclass 10, count 2 2006.257.09:48:55.41#ibcon#about to read 4, iclass 10, count 2 2006.257.09:48:55.41#ibcon#read 4, iclass 10, count 2 2006.257.09:48:55.41#ibcon#about to read 5, iclass 10, count 2 2006.257.09:48:55.41#ibcon#read 5, iclass 10, count 2 2006.257.09:48:55.41#ibcon#about to read 6, iclass 10, count 2 2006.257.09:48:55.41#ibcon#read 6, iclass 10, count 2 2006.257.09:48:55.41#ibcon#end of sib2, iclass 10, count 2 2006.257.09:48:55.41#ibcon#*mode == 0, iclass 10, count 2 2006.257.09:48:55.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.09:48:55.41#ibcon#[25=AT04-07\r\n] 2006.257.09:48:55.41#ibcon#*before write, iclass 10, count 2 2006.257.09:48:55.41#ibcon#enter sib2, iclass 10, count 2 2006.257.09:48:55.41#ibcon#flushed, iclass 10, count 2 2006.257.09:48:55.41#ibcon#about to write, iclass 10, count 2 2006.257.09:48:55.41#ibcon#wrote, iclass 10, count 2 2006.257.09:48:55.41#ibcon#about to read 3, iclass 10, count 2 2006.257.09:48:55.44#ibcon#read 3, iclass 10, count 2 2006.257.09:48:55.44#ibcon#about to read 4, iclass 10, count 2 2006.257.09:48:55.44#ibcon#read 4, iclass 10, count 2 2006.257.09:48:55.44#ibcon#about to read 5, iclass 10, count 2 2006.257.09:48:55.44#ibcon#read 5, iclass 10, count 2 2006.257.09:48:55.44#ibcon#about to read 6, iclass 10, count 2 2006.257.09:48:55.44#ibcon#read 6, iclass 10, count 2 2006.257.09:48:55.44#ibcon#end of sib2, iclass 10, count 2 2006.257.09:48:55.44#ibcon#*after write, iclass 10, count 2 2006.257.09:48:55.44#ibcon#*before return 0, iclass 10, count 2 2006.257.09:48:55.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:55.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:55.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.09:48:55.44#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:55.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:55.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:55.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:55.56#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:48:55.56#ibcon#first serial, iclass 10, count 0 2006.257.09:48:55.56#ibcon#enter sib2, iclass 10, count 0 2006.257.09:48:55.56#ibcon#flushed, iclass 10, count 0 2006.257.09:48:55.56#ibcon#about to write, iclass 10, count 0 2006.257.09:48:55.56#ibcon#wrote, iclass 10, count 0 2006.257.09:48:55.56#ibcon#about to read 3, iclass 10, count 0 2006.257.09:48:55.58#ibcon#read 3, iclass 10, count 0 2006.257.09:48:55.58#ibcon#about to read 4, iclass 10, count 0 2006.257.09:48:55.58#ibcon#read 4, iclass 10, count 0 2006.257.09:48:55.58#ibcon#about to read 5, iclass 10, count 0 2006.257.09:48:55.58#ibcon#read 5, iclass 10, count 0 2006.257.09:48:55.58#ibcon#about to read 6, iclass 10, count 0 2006.257.09:48:55.58#ibcon#read 6, iclass 10, count 0 2006.257.09:48:55.58#ibcon#end of sib2, iclass 10, count 0 2006.257.09:48:55.58#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:48:55.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:48:55.58#ibcon#[25=USB\r\n] 2006.257.09:48:55.58#ibcon#*before write, iclass 10, count 0 2006.257.09:48:55.58#ibcon#enter sib2, iclass 10, count 0 2006.257.09:48:55.58#ibcon#flushed, iclass 10, count 0 2006.257.09:48:55.58#ibcon#about to write, iclass 10, count 0 2006.257.09:48:55.58#ibcon#wrote, iclass 10, count 0 2006.257.09:48:55.58#ibcon#about to read 3, iclass 10, count 0 2006.257.09:48:55.61#ibcon#read 3, iclass 10, count 0 2006.257.09:48:55.61#ibcon#about to read 4, iclass 10, count 0 2006.257.09:48:55.61#ibcon#read 4, iclass 10, count 0 2006.257.09:48:55.61#ibcon#about to read 5, iclass 10, count 0 2006.257.09:48:55.61#ibcon#read 5, iclass 10, count 0 2006.257.09:48:55.61#ibcon#about to read 6, iclass 10, count 0 2006.257.09:48:55.61#ibcon#read 6, iclass 10, count 0 2006.257.09:48:55.61#ibcon#end of sib2, iclass 10, count 0 2006.257.09:48:55.61#ibcon#*after write, iclass 10, count 0 2006.257.09:48:55.61#ibcon#*before return 0, iclass 10, count 0 2006.257.09:48:55.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:55.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:55.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:48:55.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:48:55.61$vck44/valo=5,734.99 2006.257.09:48:55.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.09:48:55.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.09:48:55.61#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:55.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:55.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:55.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:55.61#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:48:55.61#ibcon#first serial, iclass 12, count 0 2006.257.09:48:55.61#ibcon#enter sib2, iclass 12, count 0 2006.257.09:48:55.61#ibcon#flushed, iclass 12, count 0 2006.257.09:48:55.61#ibcon#about to write, iclass 12, count 0 2006.257.09:48:55.61#ibcon#wrote, iclass 12, count 0 2006.257.09:48:55.61#ibcon#about to read 3, iclass 12, count 0 2006.257.09:48:55.63#ibcon#read 3, iclass 12, count 0 2006.257.09:48:55.63#ibcon#about to read 4, iclass 12, count 0 2006.257.09:48:55.63#ibcon#read 4, iclass 12, count 0 2006.257.09:48:55.63#ibcon#about to read 5, iclass 12, count 0 2006.257.09:48:55.63#ibcon#read 5, iclass 12, count 0 2006.257.09:48:55.63#ibcon#about to read 6, iclass 12, count 0 2006.257.09:48:55.63#ibcon#read 6, iclass 12, count 0 2006.257.09:48:55.63#ibcon#end of sib2, iclass 12, count 0 2006.257.09:48:55.63#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:48:55.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:48:55.63#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:48:55.63#ibcon#*before write, iclass 12, count 0 2006.257.09:48:55.63#ibcon#enter sib2, iclass 12, count 0 2006.257.09:48:55.63#ibcon#flushed, iclass 12, count 0 2006.257.09:48:55.63#ibcon#about to write, iclass 12, count 0 2006.257.09:48:55.63#ibcon#wrote, iclass 12, count 0 2006.257.09:48:55.63#ibcon#about to read 3, iclass 12, count 0 2006.257.09:48:55.67#ibcon#read 3, iclass 12, count 0 2006.257.09:48:55.67#ibcon#about to read 4, iclass 12, count 0 2006.257.09:48:55.67#ibcon#read 4, iclass 12, count 0 2006.257.09:48:55.67#ibcon#about to read 5, iclass 12, count 0 2006.257.09:48:55.67#ibcon#read 5, iclass 12, count 0 2006.257.09:48:55.67#ibcon#about to read 6, iclass 12, count 0 2006.257.09:48:55.67#ibcon#read 6, iclass 12, count 0 2006.257.09:48:55.67#ibcon#end of sib2, iclass 12, count 0 2006.257.09:48:55.67#ibcon#*after write, iclass 12, count 0 2006.257.09:48:55.67#ibcon#*before return 0, iclass 12, count 0 2006.257.09:48:55.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:55.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:55.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:48:55.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:48:55.67$vck44/va=5,4 2006.257.09:48:55.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.09:48:55.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.09:48:55.67#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:55.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:55.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:55.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:55.73#ibcon#enter wrdev, iclass 14, count 2 2006.257.09:48:55.73#ibcon#first serial, iclass 14, count 2 2006.257.09:48:55.73#ibcon#enter sib2, iclass 14, count 2 2006.257.09:48:55.73#ibcon#flushed, iclass 14, count 2 2006.257.09:48:55.73#ibcon#about to write, iclass 14, count 2 2006.257.09:48:55.73#ibcon#wrote, iclass 14, count 2 2006.257.09:48:55.73#ibcon#about to read 3, iclass 14, count 2 2006.257.09:48:55.75#ibcon#read 3, iclass 14, count 2 2006.257.09:48:55.75#ibcon#about to read 4, iclass 14, count 2 2006.257.09:48:55.75#ibcon#read 4, iclass 14, count 2 2006.257.09:48:55.75#ibcon#about to read 5, iclass 14, count 2 2006.257.09:48:55.75#ibcon#read 5, iclass 14, count 2 2006.257.09:48:55.75#ibcon#about to read 6, iclass 14, count 2 2006.257.09:48:55.75#ibcon#read 6, iclass 14, count 2 2006.257.09:48:55.75#ibcon#end of sib2, iclass 14, count 2 2006.257.09:48:55.75#ibcon#*mode == 0, iclass 14, count 2 2006.257.09:48:55.75#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.09:48:55.75#ibcon#[25=AT05-04\r\n] 2006.257.09:48:55.75#ibcon#*before write, iclass 14, count 2 2006.257.09:48:55.75#ibcon#enter sib2, iclass 14, count 2 2006.257.09:48:55.75#ibcon#flushed, iclass 14, count 2 2006.257.09:48:55.75#ibcon#about to write, iclass 14, count 2 2006.257.09:48:55.75#ibcon#wrote, iclass 14, count 2 2006.257.09:48:55.75#ibcon#about to read 3, iclass 14, count 2 2006.257.09:48:55.78#ibcon#read 3, iclass 14, count 2 2006.257.09:48:55.78#ibcon#about to read 4, iclass 14, count 2 2006.257.09:48:55.78#ibcon#read 4, iclass 14, count 2 2006.257.09:48:55.78#ibcon#about to read 5, iclass 14, count 2 2006.257.09:48:55.78#ibcon#read 5, iclass 14, count 2 2006.257.09:48:55.78#ibcon#about to read 6, iclass 14, count 2 2006.257.09:48:55.78#ibcon#read 6, iclass 14, count 2 2006.257.09:48:55.78#ibcon#end of sib2, iclass 14, count 2 2006.257.09:48:55.78#ibcon#*after write, iclass 14, count 2 2006.257.09:48:55.78#ibcon#*before return 0, iclass 14, count 2 2006.257.09:48:55.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:55.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:55.78#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.09:48:55.78#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:55.78#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:55.90#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:55.90#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:55.90#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:48:55.90#ibcon#first serial, iclass 14, count 0 2006.257.09:48:55.90#ibcon#enter sib2, iclass 14, count 0 2006.257.09:48:55.90#ibcon#flushed, iclass 14, count 0 2006.257.09:48:55.90#ibcon#about to write, iclass 14, count 0 2006.257.09:48:55.90#ibcon#wrote, iclass 14, count 0 2006.257.09:48:55.90#ibcon#about to read 3, iclass 14, count 0 2006.257.09:48:55.92#ibcon#read 3, iclass 14, count 0 2006.257.09:48:55.92#ibcon#about to read 4, iclass 14, count 0 2006.257.09:48:55.92#ibcon#read 4, iclass 14, count 0 2006.257.09:48:55.92#ibcon#about to read 5, iclass 14, count 0 2006.257.09:48:55.92#ibcon#read 5, iclass 14, count 0 2006.257.09:48:55.92#ibcon#about to read 6, iclass 14, count 0 2006.257.09:48:55.92#ibcon#read 6, iclass 14, count 0 2006.257.09:48:55.92#ibcon#end of sib2, iclass 14, count 0 2006.257.09:48:55.92#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:48:55.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:48:55.92#ibcon#[25=USB\r\n] 2006.257.09:48:55.92#ibcon#*before write, iclass 14, count 0 2006.257.09:48:55.92#ibcon#enter sib2, iclass 14, count 0 2006.257.09:48:55.92#ibcon#flushed, iclass 14, count 0 2006.257.09:48:55.92#ibcon#about to write, iclass 14, count 0 2006.257.09:48:55.92#ibcon#wrote, iclass 14, count 0 2006.257.09:48:55.92#ibcon#about to read 3, iclass 14, count 0 2006.257.09:48:55.95#ibcon#read 3, iclass 14, count 0 2006.257.09:48:55.95#ibcon#about to read 4, iclass 14, count 0 2006.257.09:48:55.95#ibcon#read 4, iclass 14, count 0 2006.257.09:48:55.95#ibcon#about to read 5, iclass 14, count 0 2006.257.09:48:55.95#ibcon#read 5, iclass 14, count 0 2006.257.09:48:55.95#ibcon#about to read 6, iclass 14, count 0 2006.257.09:48:55.95#ibcon#read 6, iclass 14, count 0 2006.257.09:48:55.95#ibcon#end of sib2, iclass 14, count 0 2006.257.09:48:55.95#ibcon#*after write, iclass 14, count 0 2006.257.09:48:55.95#ibcon#*before return 0, iclass 14, count 0 2006.257.09:48:55.95#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:55.95#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:55.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:48:55.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:48:55.95$vck44/valo=6,814.99 2006.257.09:48:55.95#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.09:48:55.95#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.09:48:55.95#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:55.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:55.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:55.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:55.95#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:48:55.95#ibcon#first serial, iclass 16, count 0 2006.257.09:48:55.95#ibcon#enter sib2, iclass 16, count 0 2006.257.09:48:55.95#ibcon#flushed, iclass 16, count 0 2006.257.09:48:55.95#ibcon#about to write, iclass 16, count 0 2006.257.09:48:55.95#ibcon#wrote, iclass 16, count 0 2006.257.09:48:55.95#ibcon#about to read 3, iclass 16, count 0 2006.257.09:48:55.97#ibcon#read 3, iclass 16, count 0 2006.257.09:48:55.97#ibcon#about to read 4, iclass 16, count 0 2006.257.09:48:55.97#ibcon#read 4, iclass 16, count 0 2006.257.09:48:55.97#ibcon#about to read 5, iclass 16, count 0 2006.257.09:48:55.97#ibcon#read 5, iclass 16, count 0 2006.257.09:48:55.97#ibcon#about to read 6, iclass 16, count 0 2006.257.09:48:55.97#ibcon#read 6, iclass 16, count 0 2006.257.09:48:55.97#ibcon#end of sib2, iclass 16, count 0 2006.257.09:48:55.97#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:48:55.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:48:55.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:48:55.97#ibcon#*before write, iclass 16, count 0 2006.257.09:48:55.97#ibcon#enter sib2, iclass 16, count 0 2006.257.09:48:55.97#ibcon#flushed, iclass 16, count 0 2006.257.09:48:55.97#ibcon#about to write, iclass 16, count 0 2006.257.09:48:55.97#ibcon#wrote, iclass 16, count 0 2006.257.09:48:55.97#ibcon#about to read 3, iclass 16, count 0 2006.257.09:48:56.01#ibcon#read 3, iclass 16, count 0 2006.257.09:48:56.01#ibcon#about to read 4, iclass 16, count 0 2006.257.09:48:56.01#ibcon#read 4, iclass 16, count 0 2006.257.09:48:56.01#ibcon#about to read 5, iclass 16, count 0 2006.257.09:48:56.01#ibcon#read 5, iclass 16, count 0 2006.257.09:48:56.01#ibcon#about to read 6, iclass 16, count 0 2006.257.09:48:56.01#ibcon#read 6, iclass 16, count 0 2006.257.09:48:56.01#ibcon#end of sib2, iclass 16, count 0 2006.257.09:48:56.01#ibcon#*after write, iclass 16, count 0 2006.257.09:48:56.01#ibcon#*before return 0, iclass 16, count 0 2006.257.09:48:56.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:56.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:56.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:48:56.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:48:56.01$vck44/va=6,4 2006.257.09:48:56.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.09:48:56.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.09:48:56.01#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:56.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:56.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:56.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:56.07#ibcon#enter wrdev, iclass 18, count 2 2006.257.09:48:56.07#ibcon#first serial, iclass 18, count 2 2006.257.09:48:56.07#ibcon#enter sib2, iclass 18, count 2 2006.257.09:48:56.07#ibcon#flushed, iclass 18, count 2 2006.257.09:48:56.07#ibcon#about to write, iclass 18, count 2 2006.257.09:48:56.07#ibcon#wrote, iclass 18, count 2 2006.257.09:48:56.07#ibcon#about to read 3, iclass 18, count 2 2006.257.09:48:56.09#ibcon#read 3, iclass 18, count 2 2006.257.09:48:56.09#ibcon#about to read 4, iclass 18, count 2 2006.257.09:48:56.09#ibcon#read 4, iclass 18, count 2 2006.257.09:48:56.09#ibcon#about to read 5, iclass 18, count 2 2006.257.09:48:56.09#ibcon#read 5, iclass 18, count 2 2006.257.09:48:56.09#ibcon#about to read 6, iclass 18, count 2 2006.257.09:48:56.09#ibcon#read 6, iclass 18, count 2 2006.257.09:48:56.09#ibcon#end of sib2, iclass 18, count 2 2006.257.09:48:56.09#ibcon#*mode == 0, iclass 18, count 2 2006.257.09:48:56.09#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.09:48:56.09#ibcon#[25=AT06-04\r\n] 2006.257.09:48:56.09#ibcon#*before write, iclass 18, count 2 2006.257.09:48:56.09#ibcon#enter sib2, iclass 18, count 2 2006.257.09:48:56.09#ibcon#flushed, iclass 18, count 2 2006.257.09:48:56.09#ibcon#about to write, iclass 18, count 2 2006.257.09:48:56.09#ibcon#wrote, iclass 18, count 2 2006.257.09:48:56.09#ibcon#about to read 3, iclass 18, count 2 2006.257.09:48:56.12#ibcon#read 3, iclass 18, count 2 2006.257.09:48:56.12#ibcon#about to read 4, iclass 18, count 2 2006.257.09:48:56.12#ibcon#read 4, iclass 18, count 2 2006.257.09:48:56.12#ibcon#about to read 5, iclass 18, count 2 2006.257.09:48:56.12#ibcon#read 5, iclass 18, count 2 2006.257.09:48:56.12#ibcon#about to read 6, iclass 18, count 2 2006.257.09:48:56.12#ibcon#read 6, iclass 18, count 2 2006.257.09:48:56.12#ibcon#end of sib2, iclass 18, count 2 2006.257.09:48:56.12#ibcon#*after write, iclass 18, count 2 2006.257.09:48:56.12#ibcon#*before return 0, iclass 18, count 2 2006.257.09:48:56.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:56.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:56.12#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.09:48:56.12#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:56.12#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:56.24#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:56.24#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:56.24#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:48:56.24#ibcon#first serial, iclass 18, count 0 2006.257.09:48:56.24#ibcon#enter sib2, iclass 18, count 0 2006.257.09:48:56.24#ibcon#flushed, iclass 18, count 0 2006.257.09:48:56.24#ibcon#about to write, iclass 18, count 0 2006.257.09:48:56.24#ibcon#wrote, iclass 18, count 0 2006.257.09:48:56.24#ibcon#about to read 3, iclass 18, count 0 2006.257.09:48:56.26#ibcon#read 3, iclass 18, count 0 2006.257.09:48:56.26#ibcon#about to read 4, iclass 18, count 0 2006.257.09:48:56.26#ibcon#read 4, iclass 18, count 0 2006.257.09:48:56.26#ibcon#about to read 5, iclass 18, count 0 2006.257.09:48:56.26#ibcon#read 5, iclass 18, count 0 2006.257.09:48:56.26#ibcon#about to read 6, iclass 18, count 0 2006.257.09:48:56.26#ibcon#read 6, iclass 18, count 0 2006.257.09:48:56.26#ibcon#end of sib2, iclass 18, count 0 2006.257.09:48:56.26#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:48:56.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:48:56.26#ibcon#[25=USB\r\n] 2006.257.09:48:56.26#ibcon#*before write, iclass 18, count 0 2006.257.09:48:56.26#ibcon#enter sib2, iclass 18, count 0 2006.257.09:48:56.26#ibcon#flushed, iclass 18, count 0 2006.257.09:48:56.26#ibcon#about to write, iclass 18, count 0 2006.257.09:48:56.26#ibcon#wrote, iclass 18, count 0 2006.257.09:48:56.26#ibcon#about to read 3, iclass 18, count 0 2006.257.09:48:56.29#ibcon#read 3, iclass 18, count 0 2006.257.09:48:56.29#ibcon#about to read 4, iclass 18, count 0 2006.257.09:48:56.29#ibcon#read 4, iclass 18, count 0 2006.257.09:48:56.29#ibcon#about to read 5, iclass 18, count 0 2006.257.09:48:56.29#ibcon#read 5, iclass 18, count 0 2006.257.09:48:56.29#ibcon#about to read 6, iclass 18, count 0 2006.257.09:48:56.29#ibcon#read 6, iclass 18, count 0 2006.257.09:48:56.29#ibcon#end of sib2, iclass 18, count 0 2006.257.09:48:56.29#ibcon#*after write, iclass 18, count 0 2006.257.09:48:56.29#ibcon#*before return 0, iclass 18, count 0 2006.257.09:48:56.29#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:56.29#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:56.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:48:56.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:48:56.29$vck44/valo=7,864.99 2006.257.09:48:56.29#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.09:48:56.29#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.09:48:56.29#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:56.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:56.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:56.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:56.29#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:48:56.29#ibcon#first serial, iclass 20, count 0 2006.257.09:48:56.29#ibcon#enter sib2, iclass 20, count 0 2006.257.09:48:56.29#ibcon#flushed, iclass 20, count 0 2006.257.09:48:56.29#ibcon#about to write, iclass 20, count 0 2006.257.09:48:56.29#ibcon#wrote, iclass 20, count 0 2006.257.09:48:56.29#ibcon#about to read 3, iclass 20, count 0 2006.257.09:48:56.31#ibcon#read 3, iclass 20, count 0 2006.257.09:48:56.31#ibcon#about to read 4, iclass 20, count 0 2006.257.09:48:56.31#ibcon#read 4, iclass 20, count 0 2006.257.09:48:56.31#ibcon#about to read 5, iclass 20, count 0 2006.257.09:48:56.31#ibcon#read 5, iclass 20, count 0 2006.257.09:48:56.31#ibcon#about to read 6, iclass 20, count 0 2006.257.09:48:56.31#ibcon#read 6, iclass 20, count 0 2006.257.09:48:56.31#ibcon#end of sib2, iclass 20, count 0 2006.257.09:48:56.31#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:48:56.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:48:56.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:48:56.31#ibcon#*before write, iclass 20, count 0 2006.257.09:48:56.31#ibcon#enter sib2, iclass 20, count 0 2006.257.09:48:56.31#ibcon#flushed, iclass 20, count 0 2006.257.09:48:56.31#ibcon#about to write, iclass 20, count 0 2006.257.09:48:56.31#ibcon#wrote, iclass 20, count 0 2006.257.09:48:56.31#ibcon#about to read 3, iclass 20, count 0 2006.257.09:48:56.35#ibcon#read 3, iclass 20, count 0 2006.257.09:48:56.35#ibcon#about to read 4, iclass 20, count 0 2006.257.09:48:56.35#ibcon#read 4, iclass 20, count 0 2006.257.09:48:56.35#ibcon#about to read 5, iclass 20, count 0 2006.257.09:48:56.35#ibcon#read 5, iclass 20, count 0 2006.257.09:48:56.35#ibcon#about to read 6, iclass 20, count 0 2006.257.09:48:56.35#ibcon#read 6, iclass 20, count 0 2006.257.09:48:56.35#ibcon#end of sib2, iclass 20, count 0 2006.257.09:48:56.35#ibcon#*after write, iclass 20, count 0 2006.257.09:48:56.35#ibcon#*before return 0, iclass 20, count 0 2006.257.09:48:56.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:56.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:56.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:48:56.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:48:56.35$vck44/va=7,4 2006.257.09:48:56.35#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.09:48:56.35#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.09:48:56.35#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:56.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:48:56.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:48:56.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:48:56.41#ibcon#enter wrdev, iclass 22, count 2 2006.257.09:48:56.41#ibcon#first serial, iclass 22, count 2 2006.257.09:48:56.41#ibcon#enter sib2, iclass 22, count 2 2006.257.09:48:56.41#ibcon#flushed, iclass 22, count 2 2006.257.09:48:56.41#ibcon#about to write, iclass 22, count 2 2006.257.09:48:56.41#ibcon#wrote, iclass 22, count 2 2006.257.09:48:56.41#ibcon#about to read 3, iclass 22, count 2 2006.257.09:48:56.43#ibcon#read 3, iclass 22, count 2 2006.257.09:48:56.43#ibcon#about to read 4, iclass 22, count 2 2006.257.09:48:56.43#ibcon#read 4, iclass 22, count 2 2006.257.09:48:56.43#ibcon#about to read 5, iclass 22, count 2 2006.257.09:48:56.43#ibcon#read 5, iclass 22, count 2 2006.257.09:48:56.43#ibcon#about to read 6, iclass 22, count 2 2006.257.09:48:56.43#ibcon#read 6, iclass 22, count 2 2006.257.09:48:56.43#ibcon#end of sib2, iclass 22, count 2 2006.257.09:48:56.43#ibcon#*mode == 0, iclass 22, count 2 2006.257.09:48:56.43#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.09:48:56.43#ibcon#[25=AT07-04\r\n] 2006.257.09:48:56.43#ibcon#*before write, iclass 22, count 2 2006.257.09:48:56.43#ibcon#enter sib2, iclass 22, count 2 2006.257.09:48:56.43#ibcon#flushed, iclass 22, count 2 2006.257.09:48:56.43#ibcon#about to write, iclass 22, count 2 2006.257.09:48:56.43#ibcon#wrote, iclass 22, count 2 2006.257.09:48:56.43#ibcon#about to read 3, iclass 22, count 2 2006.257.09:48:56.46#ibcon#read 3, iclass 22, count 2 2006.257.09:48:56.46#ibcon#about to read 4, iclass 22, count 2 2006.257.09:48:56.46#ibcon#read 4, iclass 22, count 2 2006.257.09:48:56.46#ibcon#about to read 5, iclass 22, count 2 2006.257.09:48:56.46#ibcon#read 5, iclass 22, count 2 2006.257.09:48:56.46#ibcon#about to read 6, iclass 22, count 2 2006.257.09:48:56.46#ibcon#read 6, iclass 22, count 2 2006.257.09:48:56.46#ibcon#end of sib2, iclass 22, count 2 2006.257.09:48:56.46#ibcon#*after write, iclass 22, count 2 2006.257.09:48:56.46#ibcon#*before return 0, iclass 22, count 2 2006.257.09:48:56.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:48:56.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.09:48:56.46#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.09:48:56.46#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:56.46#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:48:56.58#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:48:56.58#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:48:56.58#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:48:56.58#ibcon#first serial, iclass 22, count 0 2006.257.09:48:56.58#ibcon#enter sib2, iclass 22, count 0 2006.257.09:48:56.58#ibcon#flushed, iclass 22, count 0 2006.257.09:48:56.58#ibcon#about to write, iclass 22, count 0 2006.257.09:48:56.58#ibcon#wrote, iclass 22, count 0 2006.257.09:48:56.58#ibcon#about to read 3, iclass 22, count 0 2006.257.09:48:56.60#ibcon#read 3, iclass 22, count 0 2006.257.09:48:56.60#ibcon#about to read 4, iclass 22, count 0 2006.257.09:48:56.60#ibcon#read 4, iclass 22, count 0 2006.257.09:48:56.60#ibcon#about to read 5, iclass 22, count 0 2006.257.09:48:56.60#ibcon#read 5, iclass 22, count 0 2006.257.09:48:56.60#ibcon#about to read 6, iclass 22, count 0 2006.257.09:48:56.60#ibcon#read 6, iclass 22, count 0 2006.257.09:48:56.60#ibcon#end of sib2, iclass 22, count 0 2006.257.09:48:56.60#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:48:56.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:48:56.60#ibcon#[25=USB\r\n] 2006.257.09:48:56.60#ibcon#*before write, iclass 22, count 0 2006.257.09:48:56.60#ibcon#enter sib2, iclass 22, count 0 2006.257.09:48:56.60#ibcon#flushed, iclass 22, count 0 2006.257.09:48:56.60#ibcon#about to write, iclass 22, count 0 2006.257.09:48:56.60#ibcon#wrote, iclass 22, count 0 2006.257.09:48:56.60#ibcon#about to read 3, iclass 22, count 0 2006.257.09:48:56.63#ibcon#read 3, iclass 22, count 0 2006.257.09:48:56.63#ibcon#about to read 4, iclass 22, count 0 2006.257.09:48:56.63#ibcon#read 4, iclass 22, count 0 2006.257.09:48:56.63#ibcon#about to read 5, iclass 22, count 0 2006.257.09:48:56.63#ibcon#read 5, iclass 22, count 0 2006.257.09:48:56.63#ibcon#about to read 6, iclass 22, count 0 2006.257.09:48:56.63#ibcon#read 6, iclass 22, count 0 2006.257.09:48:56.63#ibcon#end of sib2, iclass 22, count 0 2006.257.09:48:56.63#ibcon#*after write, iclass 22, count 0 2006.257.09:48:56.63#ibcon#*before return 0, iclass 22, count 0 2006.257.09:48:56.63#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:48:56.63#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.09:48:56.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:48:56.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:48:56.63$vck44/valo=8,884.99 2006.257.09:48:56.63#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.09:48:56.63#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.09:48:56.63#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:56.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:48:56.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:48:56.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:48:56.63#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:48:56.63#ibcon#first serial, iclass 24, count 0 2006.257.09:48:56.63#ibcon#enter sib2, iclass 24, count 0 2006.257.09:48:56.63#ibcon#flushed, iclass 24, count 0 2006.257.09:48:56.63#ibcon#about to write, iclass 24, count 0 2006.257.09:48:56.63#ibcon#wrote, iclass 24, count 0 2006.257.09:48:56.63#ibcon#about to read 3, iclass 24, count 0 2006.257.09:48:56.65#ibcon#read 3, iclass 24, count 0 2006.257.09:48:56.65#ibcon#about to read 4, iclass 24, count 0 2006.257.09:48:56.65#ibcon#read 4, iclass 24, count 0 2006.257.09:48:56.65#ibcon#about to read 5, iclass 24, count 0 2006.257.09:48:56.65#ibcon#read 5, iclass 24, count 0 2006.257.09:48:56.65#ibcon#about to read 6, iclass 24, count 0 2006.257.09:48:56.65#ibcon#read 6, iclass 24, count 0 2006.257.09:48:56.65#ibcon#end of sib2, iclass 24, count 0 2006.257.09:48:56.65#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:48:56.65#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:48:56.65#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:48:56.65#ibcon#*before write, iclass 24, count 0 2006.257.09:48:56.65#ibcon#enter sib2, iclass 24, count 0 2006.257.09:48:56.65#ibcon#flushed, iclass 24, count 0 2006.257.09:48:56.65#ibcon#about to write, iclass 24, count 0 2006.257.09:48:56.65#ibcon#wrote, iclass 24, count 0 2006.257.09:48:56.65#ibcon#about to read 3, iclass 24, count 0 2006.257.09:48:56.69#ibcon#read 3, iclass 24, count 0 2006.257.09:48:56.69#ibcon#about to read 4, iclass 24, count 0 2006.257.09:48:56.69#ibcon#read 4, iclass 24, count 0 2006.257.09:48:56.69#ibcon#about to read 5, iclass 24, count 0 2006.257.09:48:56.69#ibcon#read 5, iclass 24, count 0 2006.257.09:48:56.69#ibcon#about to read 6, iclass 24, count 0 2006.257.09:48:56.69#ibcon#read 6, iclass 24, count 0 2006.257.09:48:56.69#ibcon#end of sib2, iclass 24, count 0 2006.257.09:48:56.69#ibcon#*after write, iclass 24, count 0 2006.257.09:48:56.69#ibcon#*before return 0, iclass 24, count 0 2006.257.09:48:56.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:48:56.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.09:48:56.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:48:56.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:48:56.69$vck44/va=8,4 2006.257.09:48:56.69#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.09:48:56.69#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.09:48:56.69#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:56.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:48:56.75#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:48:56.75#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:48:56.75#ibcon#enter wrdev, iclass 26, count 2 2006.257.09:48:56.75#ibcon#first serial, iclass 26, count 2 2006.257.09:48:56.75#ibcon#enter sib2, iclass 26, count 2 2006.257.09:48:56.75#ibcon#flushed, iclass 26, count 2 2006.257.09:48:56.75#ibcon#about to write, iclass 26, count 2 2006.257.09:48:56.75#ibcon#wrote, iclass 26, count 2 2006.257.09:48:56.75#ibcon#about to read 3, iclass 26, count 2 2006.257.09:48:56.77#ibcon#read 3, iclass 26, count 2 2006.257.09:48:56.77#ibcon#about to read 4, iclass 26, count 2 2006.257.09:48:56.77#ibcon#read 4, iclass 26, count 2 2006.257.09:48:56.77#ibcon#about to read 5, iclass 26, count 2 2006.257.09:48:56.77#ibcon#read 5, iclass 26, count 2 2006.257.09:48:56.77#ibcon#about to read 6, iclass 26, count 2 2006.257.09:48:56.77#ibcon#read 6, iclass 26, count 2 2006.257.09:48:56.77#ibcon#end of sib2, iclass 26, count 2 2006.257.09:48:56.77#ibcon#*mode == 0, iclass 26, count 2 2006.257.09:48:56.77#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.09:48:56.77#ibcon#[25=AT08-04\r\n] 2006.257.09:48:56.77#ibcon#*before write, iclass 26, count 2 2006.257.09:48:56.77#ibcon#enter sib2, iclass 26, count 2 2006.257.09:48:56.77#ibcon#flushed, iclass 26, count 2 2006.257.09:48:56.77#ibcon#about to write, iclass 26, count 2 2006.257.09:48:56.77#ibcon#wrote, iclass 26, count 2 2006.257.09:48:56.77#ibcon#about to read 3, iclass 26, count 2 2006.257.09:48:56.80#ibcon#read 3, iclass 26, count 2 2006.257.09:48:56.80#ibcon#about to read 4, iclass 26, count 2 2006.257.09:48:56.80#ibcon#read 4, iclass 26, count 2 2006.257.09:48:56.80#ibcon#about to read 5, iclass 26, count 2 2006.257.09:48:56.80#ibcon#read 5, iclass 26, count 2 2006.257.09:48:56.80#ibcon#about to read 6, iclass 26, count 2 2006.257.09:48:56.80#ibcon#read 6, iclass 26, count 2 2006.257.09:48:56.80#ibcon#end of sib2, iclass 26, count 2 2006.257.09:48:56.80#ibcon#*after write, iclass 26, count 2 2006.257.09:48:56.80#ibcon#*before return 0, iclass 26, count 2 2006.257.09:48:56.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:48:56.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.09:48:56.80#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.09:48:56.80#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:56.80#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:48:56.92#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:48:56.92#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:48:56.92#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:48:56.92#ibcon#first serial, iclass 26, count 0 2006.257.09:48:56.92#ibcon#enter sib2, iclass 26, count 0 2006.257.09:48:56.92#ibcon#flushed, iclass 26, count 0 2006.257.09:48:56.92#ibcon#about to write, iclass 26, count 0 2006.257.09:48:56.92#ibcon#wrote, iclass 26, count 0 2006.257.09:48:56.92#ibcon#about to read 3, iclass 26, count 0 2006.257.09:48:56.94#ibcon#read 3, iclass 26, count 0 2006.257.09:48:56.94#ibcon#about to read 4, iclass 26, count 0 2006.257.09:48:56.94#ibcon#read 4, iclass 26, count 0 2006.257.09:48:56.94#ibcon#about to read 5, iclass 26, count 0 2006.257.09:48:56.94#ibcon#read 5, iclass 26, count 0 2006.257.09:48:56.94#ibcon#about to read 6, iclass 26, count 0 2006.257.09:48:56.94#ibcon#read 6, iclass 26, count 0 2006.257.09:48:56.94#ibcon#end of sib2, iclass 26, count 0 2006.257.09:48:56.94#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:48:56.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:48:56.94#ibcon#[25=USB\r\n] 2006.257.09:48:56.94#ibcon#*before write, iclass 26, count 0 2006.257.09:48:56.94#ibcon#enter sib2, iclass 26, count 0 2006.257.09:48:56.94#ibcon#flushed, iclass 26, count 0 2006.257.09:48:56.94#ibcon#about to write, iclass 26, count 0 2006.257.09:48:56.94#ibcon#wrote, iclass 26, count 0 2006.257.09:48:56.94#ibcon#about to read 3, iclass 26, count 0 2006.257.09:48:56.97#ibcon#read 3, iclass 26, count 0 2006.257.09:48:56.97#ibcon#about to read 4, iclass 26, count 0 2006.257.09:48:56.97#ibcon#read 4, iclass 26, count 0 2006.257.09:48:56.97#ibcon#about to read 5, iclass 26, count 0 2006.257.09:48:56.97#ibcon#read 5, iclass 26, count 0 2006.257.09:48:56.97#ibcon#about to read 6, iclass 26, count 0 2006.257.09:48:56.97#ibcon#read 6, iclass 26, count 0 2006.257.09:48:56.97#ibcon#end of sib2, iclass 26, count 0 2006.257.09:48:56.97#ibcon#*after write, iclass 26, count 0 2006.257.09:48:56.97#ibcon#*before return 0, iclass 26, count 0 2006.257.09:48:56.97#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:48:56.97#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.09:48:56.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:48:56.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:48:56.97$vck44/vblo=1,629.99 2006.257.09:48:56.97#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.09:48:56.97#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.09:48:56.97#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:56.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:56.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:56.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:56.97#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:48:56.97#ibcon#first serial, iclass 28, count 0 2006.257.09:48:56.97#ibcon#enter sib2, iclass 28, count 0 2006.257.09:48:56.97#ibcon#flushed, iclass 28, count 0 2006.257.09:48:56.97#ibcon#about to write, iclass 28, count 0 2006.257.09:48:56.97#ibcon#wrote, iclass 28, count 0 2006.257.09:48:56.97#ibcon#about to read 3, iclass 28, count 0 2006.257.09:48:56.99#ibcon#read 3, iclass 28, count 0 2006.257.09:48:56.99#ibcon#about to read 4, iclass 28, count 0 2006.257.09:48:56.99#ibcon#read 4, iclass 28, count 0 2006.257.09:48:56.99#ibcon#about to read 5, iclass 28, count 0 2006.257.09:48:56.99#ibcon#read 5, iclass 28, count 0 2006.257.09:48:56.99#ibcon#about to read 6, iclass 28, count 0 2006.257.09:48:56.99#ibcon#read 6, iclass 28, count 0 2006.257.09:48:56.99#ibcon#end of sib2, iclass 28, count 0 2006.257.09:48:56.99#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:48:56.99#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:48:56.99#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:48:56.99#ibcon#*before write, iclass 28, count 0 2006.257.09:48:56.99#ibcon#enter sib2, iclass 28, count 0 2006.257.09:48:56.99#ibcon#flushed, iclass 28, count 0 2006.257.09:48:56.99#ibcon#about to write, iclass 28, count 0 2006.257.09:48:56.99#ibcon#wrote, iclass 28, count 0 2006.257.09:48:56.99#ibcon#about to read 3, iclass 28, count 0 2006.257.09:48:57.03#ibcon#read 3, iclass 28, count 0 2006.257.09:48:57.03#ibcon#about to read 4, iclass 28, count 0 2006.257.09:48:57.03#ibcon#read 4, iclass 28, count 0 2006.257.09:48:57.03#ibcon#about to read 5, iclass 28, count 0 2006.257.09:48:57.03#ibcon#read 5, iclass 28, count 0 2006.257.09:48:57.03#ibcon#about to read 6, iclass 28, count 0 2006.257.09:48:57.03#ibcon#read 6, iclass 28, count 0 2006.257.09:48:57.03#ibcon#end of sib2, iclass 28, count 0 2006.257.09:48:57.03#ibcon#*after write, iclass 28, count 0 2006.257.09:48:57.03#ibcon#*before return 0, iclass 28, count 0 2006.257.09:48:57.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:57.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:57.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:48:57.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:48:57.03$vck44/vb=1,4 2006.257.09:48:57.03#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.09:48:57.03#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.09:48:57.03#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:57.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:48:57.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:48:57.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:48:57.03#ibcon#enter wrdev, iclass 30, count 2 2006.257.09:48:57.03#ibcon#first serial, iclass 30, count 2 2006.257.09:48:57.03#ibcon#enter sib2, iclass 30, count 2 2006.257.09:48:57.03#ibcon#flushed, iclass 30, count 2 2006.257.09:48:57.03#ibcon#about to write, iclass 30, count 2 2006.257.09:48:57.03#ibcon#wrote, iclass 30, count 2 2006.257.09:48:57.03#ibcon#about to read 3, iclass 30, count 2 2006.257.09:48:57.05#ibcon#read 3, iclass 30, count 2 2006.257.09:48:57.05#ibcon#about to read 4, iclass 30, count 2 2006.257.09:48:57.05#ibcon#read 4, iclass 30, count 2 2006.257.09:48:57.05#ibcon#about to read 5, iclass 30, count 2 2006.257.09:48:57.05#ibcon#read 5, iclass 30, count 2 2006.257.09:48:57.05#ibcon#about to read 6, iclass 30, count 2 2006.257.09:48:57.05#ibcon#read 6, iclass 30, count 2 2006.257.09:48:57.05#ibcon#end of sib2, iclass 30, count 2 2006.257.09:48:57.05#ibcon#*mode == 0, iclass 30, count 2 2006.257.09:48:57.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.09:48:57.05#ibcon#[27=AT01-04\r\n] 2006.257.09:48:57.05#ibcon#*before write, iclass 30, count 2 2006.257.09:48:57.05#ibcon#enter sib2, iclass 30, count 2 2006.257.09:48:57.05#ibcon#flushed, iclass 30, count 2 2006.257.09:48:57.05#ibcon#about to write, iclass 30, count 2 2006.257.09:48:57.05#ibcon#wrote, iclass 30, count 2 2006.257.09:48:57.05#ibcon#about to read 3, iclass 30, count 2 2006.257.09:48:57.08#ibcon#read 3, iclass 30, count 2 2006.257.09:48:57.08#ibcon#about to read 4, iclass 30, count 2 2006.257.09:48:57.08#ibcon#read 4, iclass 30, count 2 2006.257.09:48:57.08#ibcon#about to read 5, iclass 30, count 2 2006.257.09:48:57.08#ibcon#read 5, iclass 30, count 2 2006.257.09:48:57.08#ibcon#about to read 6, iclass 30, count 2 2006.257.09:48:57.08#ibcon#read 6, iclass 30, count 2 2006.257.09:48:57.08#ibcon#end of sib2, iclass 30, count 2 2006.257.09:48:57.08#ibcon#*after write, iclass 30, count 2 2006.257.09:48:57.08#ibcon#*before return 0, iclass 30, count 2 2006.257.09:48:57.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:48:57.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.09:48:57.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.09:48:57.08#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:57.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:48:57.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:48:57.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:48:57.20#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:48:57.20#ibcon#first serial, iclass 30, count 0 2006.257.09:48:57.20#ibcon#enter sib2, iclass 30, count 0 2006.257.09:48:57.20#ibcon#flushed, iclass 30, count 0 2006.257.09:48:57.20#ibcon#about to write, iclass 30, count 0 2006.257.09:48:57.20#ibcon#wrote, iclass 30, count 0 2006.257.09:48:57.20#ibcon#about to read 3, iclass 30, count 0 2006.257.09:48:57.22#ibcon#read 3, iclass 30, count 0 2006.257.09:48:57.22#ibcon#about to read 4, iclass 30, count 0 2006.257.09:48:57.22#ibcon#read 4, iclass 30, count 0 2006.257.09:48:57.22#ibcon#about to read 5, iclass 30, count 0 2006.257.09:48:57.22#ibcon#read 5, iclass 30, count 0 2006.257.09:48:57.22#ibcon#about to read 6, iclass 30, count 0 2006.257.09:48:57.22#ibcon#read 6, iclass 30, count 0 2006.257.09:48:57.22#ibcon#end of sib2, iclass 30, count 0 2006.257.09:48:57.22#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:48:57.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:48:57.22#ibcon#[27=USB\r\n] 2006.257.09:48:57.22#ibcon#*before write, iclass 30, count 0 2006.257.09:48:57.22#ibcon#enter sib2, iclass 30, count 0 2006.257.09:48:57.22#ibcon#flushed, iclass 30, count 0 2006.257.09:48:57.22#ibcon#about to write, iclass 30, count 0 2006.257.09:48:57.22#ibcon#wrote, iclass 30, count 0 2006.257.09:48:57.22#ibcon#about to read 3, iclass 30, count 0 2006.257.09:48:57.25#ibcon#read 3, iclass 30, count 0 2006.257.09:48:57.25#ibcon#about to read 4, iclass 30, count 0 2006.257.09:48:57.25#ibcon#read 4, iclass 30, count 0 2006.257.09:48:57.25#ibcon#about to read 5, iclass 30, count 0 2006.257.09:48:57.25#ibcon#read 5, iclass 30, count 0 2006.257.09:48:57.25#ibcon#about to read 6, iclass 30, count 0 2006.257.09:48:57.25#ibcon#read 6, iclass 30, count 0 2006.257.09:48:57.25#ibcon#end of sib2, iclass 30, count 0 2006.257.09:48:57.25#ibcon#*after write, iclass 30, count 0 2006.257.09:48:57.25#ibcon#*before return 0, iclass 30, count 0 2006.257.09:48:57.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:48:57.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.09:48:57.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:48:57.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:48:57.25$vck44/vblo=2,634.99 2006.257.09:48:57.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.09:48:57.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.09:48:57.25#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:57.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:57.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:57.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:57.25#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:48:57.25#ibcon#first serial, iclass 32, count 0 2006.257.09:48:57.25#ibcon#enter sib2, iclass 32, count 0 2006.257.09:48:57.25#ibcon#flushed, iclass 32, count 0 2006.257.09:48:57.25#ibcon#about to write, iclass 32, count 0 2006.257.09:48:57.25#ibcon#wrote, iclass 32, count 0 2006.257.09:48:57.25#ibcon#about to read 3, iclass 32, count 0 2006.257.09:48:57.27#ibcon#read 3, iclass 32, count 0 2006.257.09:48:57.27#ibcon#about to read 4, iclass 32, count 0 2006.257.09:48:57.27#ibcon#read 4, iclass 32, count 0 2006.257.09:48:57.27#ibcon#about to read 5, iclass 32, count 0 2006.257.09:48:57.27#ibcon#read 5, iclass 32, count 0 2006.257.09:48:57.27#ibcon#about to read 6, iclass 32, count 0 2006.257.09:48:57.27#ibcon#read 6, iclass 32, count 0 2006.257.09:48:57.27#ibcon#end of sib2, iclass 32, count 0 2006.257.09:48:57.27#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:48:57.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:48:57.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:48:57.27#ibcon#*before write, iclass 32, count 0 2006.257.09:48:57.27#ibcon#enter sib2, iclass 32, count 0 2006.257.09:48:57.27#ibcon#flushed, iclass 32, count 0 2006.257.09:48:57.27#ibcon#about to write, iclass 32, count 0 2006.257.09:48:57.27#ibcon#wrote, iclass 32, count 0 2006.257.09:48:57.27#ibcon#about to read 3, iclass 32, count 0 2006.257.09:48:57.31#ibcon#read 3, iclass 32, count 0 2006.257.09:48:57.31#ibcon#about to read 4, iclass 32, count 0 2006.257.09:48:57.31#ibcon#read 4, iclass 32, count 0 2006.257.09:48:57.31#ibcon#about to read 5, iclass 32, count 0 2006.257.09:48:57.31#ibcon#read 5, iclass 32, count 0 2006.257.09:48:57.31#ibcon#about to read 6, iclass 32, count 0 2006.257.09:48:57.31#ibcon#read 6, iclass 32, count 0 2006.257.09:48:57.31#ibcon#end of sib2, iclass 32, count 0 2006.257.09:48:57.31#ibcon#*after write, iclass 32, count 0 2006.257.09:48:57.31#ibcon#*before return 0, iclass 32, count 0 2006.257.09:48:57.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:57.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.09:48:57.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:48:57.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:48:57.31$vck44/vb=2,5 2006.257.09:48:57.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.09:48:57.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.09:48:57.31#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:57.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:57.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:57.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:57.37#ibcon#enter wrdev, iclass 34, count 2 2006.257.09:48:57.37#ibcon#first serial, iclass 34, count 2 2006.257.09:48:57.37#ibcon#enter sib2, iclass 34, count 2 2006.257.09:48:57.37#ibcon#flushed, iclass 34, count 2 2006.257.09:48:57.37#ibcon#about to write, iclass 34, count 2 2006.257.09:48:57.37#ibcon#wrote, iclass 34, count 2 2006.257.09:48:57.37#ibcon#about to read 3, iclass 34, count 2 2006.257.09:48:57.39#ibcon#read 3, iclass 34, count 2 2006.257.09:48:57.39#ibcon#about to read 4, iclass 34, count 2 2006.257.09:48:57.39#ibcon#read 4, iclass 34, count 2 2006.257.09:48:57.39#ibcon#about to read 5, iclass 34, count 2 2006.257.09:48:57.39#ibcon#read 5, iclass 34, count 2 2006.257.09:48:57.39#ibcon#about to read 6, iclass 34, count 2 2006.257.09:48:57.39#ibcon#read 6, iclass 34, count 2 2006.257.09:48:57.39#ibcon#end of sib2, iclass 34, count 2 2006.257.09:48:57.39#ibcon#*mode == 0, iclass 34, count 2 2006.257.09:48:57.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.09:48:57.39#ibcon#[27=AT02-05\r\n] 2006.257.09:48:57.39#ibcon#*before write, iclass 34, count 2 2006.257.09:48:57.39#ibcon#enter sib2, iclass 34, count 2 2006.257.09:48:57.39#ibcon#flushed, iclass 34, count 2 2006.257.09:48:57.39#ibcon#about to write, iclass 34, count 2 2006.257.09:48:57.39#ibcon#wrote, iclass 34, count 2 2006.257.09:48:57.39#ibcon#about to read 3, iclass 34, count 2 2006.257.09:48:57.42#ibcon#read 3, iclass 34, count 2 2006.257.09:48:57.42#ibcon#about to read 4, iclass 34, count 2 2006.257.09:48:57.42#ibcon#read 4, iclass 34, count 2 2006.257.09:48:57.42#ibcon#about to read 5, iclass 34, count 2 2006.257.09:48:57.42#ibcon#read 5, iclass 34, count 2 2006.257.09:48:57.42#ibcon#about to read 6, iclass 34, count 2 2006.257.09:48:57.42#ibcon#read 6, iclass 34, count 2 2006.257.09:48:57.42#ibcon#end of sib2, iclass 34, count 2 2006.257.09:48:57.42#ibcon#*after write, iclass 34, count 2 2006.257.09:48:57.42#ibcon#*before return 0, iclass 34, count 2 2006.257.09:48:57.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:57.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.09:48:57.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.09:48:57.42#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:57.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:57.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:57.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:57.54#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:48:57.54#ibcon#first serial, iclass 34, count 0 2006.257.09:48:57.54#ibcon#enter sib2, iclass 34, count 0 2006.257.09:48:57.54#ibcon#flushed, iclass 34, count 0 2006.257.09:48:57.54#ibcon#about to write, iclass 34, count 0 2006.257.09:48:57.54#ibcon#wrote, iclass 34, count 0 2006.257.09:48:57.54#ibcon#about to read 3, iclass 34, count 0 2006.257.09:48:57.56#ibcon#read 3, iclass 34, count 0 2006.257.09:48:57.56#ibcon#about to read 4, iclass 34, count 0 2006.257.09:48:57.56#ibcon#read 4, iclass 34, count 0 2006.257.09:48:57.56#ibcon#about to read 5, iclass 34, count 0 2006.257.09:48:57.56#ibcon#read 5, iclass 34, count 0 2006.257.09:48:57.56#ibcon#about to read 6, iclass 34, count 0 2006.257.09:48:57.56#ibcon#read 6, iclass 34, count 0 2006.257.09:48:57.56#ibcon#end of sib2, iclass 34, count 0 2006.257.09:48:57.56#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:48:57.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:48:57.56#ibcon#[27=USB\r\n] 2006.257.09:48:57.56#ibcon#*before write, iclass 34, count 0 2006.257.09:48:57.56#ibcon#enter sib2, iclass 34, count 0 2006.257.09:48:57.56#ibcon#flushed, iclass 34, count 0 2006.257.09:48:57.56#ibcon#about to write, iclass 34, count 0 2006.257.09:48:57.56#ibcon#wrote, iclass 34, count 0 2006.257.09:48:57.56#ibcon#about to read 3, iclass 34, count 0 2006.257.09:48:57.59#ibcon#read 3, iclass 34, count 0 2006.257.09:48:57.59#ibcon#about to read 4, iclass 34, count 0 2006.257.09:48:57.59#ibcon#read 4, iclass 34, count 0 2006.257.09:48:57.59#ibcon#about to read 5, iclass 34, count 0 2006.257.09:48:57.59#ibcon#read 5, iclass 34, count 0 2006.257.09:48:57.59#ibcon#about to read 6, iclass 34, count 0 2006.257.09:48:57.59#ibcon#read 6, iclass 34, count 0 2006.257.09:48:57.59#ibcon#end of sib2, iclass 34, count 0 2006.257.09:48:57.59#ibcon#*after write, iclass 34, count 0 2006.257.09:48:57.59#ibcon#*before return 0, iclass 34, count 0 2006.257.09:48:57.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:57.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.09:48:57.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:48:57.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:48:57.59$vck44/vblo=3,649.99 2006.257.09:48:57.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.09:48:57.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.09:48:57.59#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:57.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:57.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:57.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:57.59#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:48:57.59#ibcon#first serial, iclass 36, count 0 2006.257.09:48:57.59#ibcon#enter sib2, iclass 36, count 0 2006.257.09:48:57.59#ibcon#flushed, iclass 36, count 0 2006.257.09:48:57.59#ibcon#about to write, iclass 36, count 0 2006.257.09:48:57.59#ibcon#wrote, iclass 36, count 0 2006.257.09:48:57.59#ibcon#about to read 3, iclass 36, count 0 2006.257.09:48:57.61#ibcon#read 3, iclass 36, count 0 2006.257.09:48:57.61#ibcon#about to read 4, iclass 36, count 0 2006.257.09:48:57.61#ibcon#read 4, iclass 36, count 0 2006.257.09:48:57.61#ibcon#about to read 5, iclass 36, count 0 2006.257.09:48:57.61#ibcon#read 5, iclass 36, count 0 2006.257.09:48:57.61#ibcon#about to read 6, iclass 36, count 0 2006.257.09:48:57.61#ibcon#read 6, iclass 36, count 0 2006.257.09:48:57.61#ibcon#end of sib2, iclass 36, count 0 2006.257.09:48:57.61#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:48:57.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:48:57.61#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:48:57.61#ibcon#*before write, iclass 36, count 0 2006.257.09:48:57.61#ibcon#enter sib2, iclass 36, count 0 2006.257.09:48:57.61#ibcon#flushed, iclass 36, count 0 2006.257.09:48:57.61#ibcon#about to write, iclass 36, count 0 2006.257.09:48:57.61#ibcon#wrote, iclass 36, count 0 2006.257.09:48:57.61#ibcon#about to read 3, iclass 36, count 0 2006.257.09:48:57.65#ibcon#read 3, iclass 36, count 0 2006.257.09:48:57.65#ibcon#about to read 4, iclass 36, count 0 2006.257.09:48:57.65#ibcon#read 4, iclass 36, count 0 2006.257.09:48:57.65#ibcon#about to read 5, iclass 36, count 0 2006.257.09:48:57.65#ibcon#read 5, iclass 36, count 0 2006.257.09:48:57.65#ibcon#about to read 6, iclass 36, count 0 2006.257.09:48:57.65#ibcon#read 6, iclass 36, count 0 2006.257.09:48:57.65#ibcon#end of sib2, iclass 36, count 0 2006.257.09:48:57.65#ibcon#*after write, iclass 36, count 0 2006.257.09:48:57.65#ibcon#*before return 0, iclass 36, count 0 2006.257.09:48:57.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:57.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.09:48:57.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:48:57.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:48:57.65$vck44/vb=3,4 2006.257.09:48:57.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.09:48:57.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.09:48:57.65#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:57.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:57.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:57.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:57.71#ibcon#enter wrdev, iclass 38, count 2 2006.257.09:48:57.71#ibcon#first serial, iclass 38, count 2 2006.257.09:48:57.71#ibcon#enter sib2, iclass 38, count 2 2006.257.09:48:57.71#ibcon#flushed, iclass 38, count 2 2006.257.09:48:57.71#ibcon#about to write, iclass 38, count 2 2006.257.09:48:57.71#ibcon#wrote, iclass 38, count 2 2006.257.09:48:57.71#ibcon#about to read 3, iclass 38, count 2 2006.257.09:48:57.73#ibcon#read 3, iclass 38, count 2 2006.257.09:48:57.73#ibcon#about to read 4, iclass 38, count 2 2006.257.09:48:57.73#ibcon#read 4, iclass 38, count 2 2006.257.09:48:57.73#ibcon#about to read 5, iclass 38, count 2 2006.257.09:48:57.73#ibcon#read 5, iclass 38, count 2 2006.257.09:48:57.73#ibcon#about to read 6, iclass 38, count 2 2006.257.09:48:57.73#ibcon#read 6, iclass 38, count 2 2006.257.09:48:57.73#ibcon#end of sib2, iclass 38, count 2 2006.257.09:48:57.73#ibcon#*mode == 0, iclass 38, count 2 2006.257.09:48:57.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.09:48:57.73#ibcon#[27=AT03-04\r\n] 2006.257.09:48:57.73#ibcon#*before write, iclass 38, count 2 2006.257.09:48:57.73#ibcon#enter sib2, iclass 38, count 2 2006.257.09:48:57.73#ibcon#flushed, iclass 38, count 2 2006.257.09:48:57.73#ibcon#about to write, iclass 38, count 2 2006.257.09:48:57.73#ibcon#wrote, iclass 38, count 2 2006.257.09:48:57.73#ibcon#about to read 3, iclass 38, count 2 2006.257.09:48:57.76#ibcon#read 3, iclass 38, count 2 2006.257.09:48:57.76#ibcon#about to read 4, iclass 38, count 2 2006.257.09:48:57.76#ibcon#read 4, iclass 38, count 2 2006.257.09:48:57.76#ibcon#about to read 5, iclass 38, count 2 2006.257.09:48:57.76#ibcon#read 5, iclass 38, count 2 2006.257.09:48:57.76#ibcon#about to read 6, iclass 38, count 2 2006.257.09:48:57.76#ibcon#read 6, iclass 38, count 2 2006.257.09:48:57.76#ibcon#end of sib2, iclass 38, count 2 2006.257.09:48:57.76#ibcon#*after write, iclass 38, count 2 2006.257.09:48:57.76#ibcon#*before return 0, iclass 38, count 2 2006.257.09:48:57.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:57.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.09:48:57.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.09:48:57.76#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:57.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:57.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:57.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:57.88#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:48:57.88#ibcon#first serial, iclass 38, count 0 2006.257.09:48:57.88#ibcon#enter sib2, iclass 38, count 0 2006.257.09:48:57.88#ibcon#flushed, iclass 38, count 0 2006.257.09:48:57.88#ibcon#about to write, iclass 38, count 0 2006.257.09:48:57.88#ibcon#wrote, iclass 38, count 0 2006.257.09:48:57.88#ibcon#about to read 3, iclass 38, count 0 2006.257.09:48:57.90#ibcon#read 3, iclass 38, count 0 2006.257.09:48:57.90#ibcon#about to read 4, iclass 38, count 0 2006.257.09:48:57.90#ibcon#read 4, iclass 38, count 0 2006.257.09:48:57.90#ibcon#about to read 5, iclass 38, count 0 2006.257.09:48:57.90#ibcon#read 5, iclass 38, count 0 2006.257.09:48:57.90#ibcon#about to read 6, iclass 38, count 0 2006.257.09:48:57.90#ibcon#read 6, iclass 38, count 0 2006.257.09:48:57.90#ibcon#end of sib2, iclass 38, count 0 2006.257.09:48:57.90#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:48:57.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:48:57.90#ibcon#[27=USB\r\n] 2006.257.09:48:57.90#ibcon#*before write, iclass 38, count 0 2006.257.09:48:57.90#ibcon#enter sib2, iclass 38, count 0 2006.257.09:48:57.90#ibcon#flushed, iclass 38, count 0 2006.257.09:48:57.90#ibcon#about to write, iclass 38, count 0 2006.257.09:48:57.90#ibcon#wrote, iclass 38, count 0 2006.257.09:48:57.90#ibcon#about to read 3, iclass 38, count 0 2006.257.09:48:57.93#ibcon#read 3, iclass 38, count 0 2006.257.09:48:57.93#ibcon#about to read 4, iclass 38, count 0 2006.257.09:48:57.93#ibcon#read 4, iclass 38, count 0 2006.257.09:48:57.93#ibcon#about to read 5, iclass 38, count 0 2006.257.09:48:57.93#ibcon#read 5, iclass 38, count 0 2006.257.09:48:57.93#ibcon#about to read 6, iclass 38, count 0 2006.257.09:48:57.93#ibcon#read 6, iclass 38, count 0 2006.257.09:48:57.93#ibcon#end of sib2, iclass 38, count 0 2006.257.09:48:57.93#ibcon#*after write, iclass 38, count 0 2006.257.09:48:57.93#ibcon#*before return 0, iclass 38, count 0 2006.257.09:48:57.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:57.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.09:48:57.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:48:57.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:48:57.93$vck44/vblo=4,679.99 2006.257.09:48:57.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.09:48:57.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.09:48:57.93#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:57.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:57.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:57.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:57.93#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:48:57.93#ibcon#first serial, iclass 40, count 0 2006.257.09:48:57.93#ibcon#enter sib2, iclass 40, count 0 2006.257.09:48:57.93#ibcon#flushed, iclass 40, count 0 2006.257.09:48:57.93#ibcon#about to write, iclass 40, count 0 2006.257.09:48:57.93#ibcon#wrote, iclass 40, count 0 2006.257.09:48:57.93#ibcon#about to read 3, iclass 40, count 0 2006.257.09:48:57.95#ibcon#read 3, iclass 40, count 0 2006.257.09:48:57.95#ibcon#about to read 4, iclass 40, count 0 2006.257.09:48:57.95#ibcon#read 4, iclass 40, count 0 2006.257.09:48:57.95#ibcon#about to read 5, iclass 40, count 0 2006.257.09:48:57.95#ibcon#read 5, iclass 40, count 0 2006.257.09:48:57.95#ibcon#about to read 6, iclass 40, count 0 2006.257.09:48:57.95#ibcon#read 6, iclass 40, count 0 2006.257.09:48:57.95#ibcon#end of sib2, iclass 40, count 0 2006.257.09:48:57.95#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:48:57.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:48:57.95#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:48:57.95#ibcon#*before write, iclass 40, count 0 2006.257.09:48:57.95#ibcon#enter sib2, iclass 40, count 0 2006.257.09:48:57.95#ibcon#flushed, iclass 40, count 0 2006.257.09:48:57.95#ibcon#about to write, iclass 40, count 0 2006.257.09:48:57.95#ibcon#wrote, iclass 40, count 0 2006.257.09:48:57.95#ibcon#about to read 3, iclass 40, count 0 2006.257.09:48:57.99#ibcon#read 3, iclass 40, count 0 2006.257.09:48:57.99#ibcon#about to read 4, iclass 40, count 0 2006.257.09:48:57.99#ibcon#read 4, iclass 40, count 0 2006.257.09:48:57.99#ibcon#about to read 5, iclass 40, count 0 2006.257.09:48:57.99#ibcon#read 5, iclass 40, count 0 2006.257.09:48:57.99#ibcon#about to read 6, iclass 40, count 0 2006.257.09:48:57.99#ibcon#read 6, iclass 40, count 0 2006.257.09:48:57.99#ibcon#end of sib2, iclass 40, count 0 2006.257.09:48:57.99#ibcon#*after write, iclass 40, count 0 2006.257.09:48:57.99#ibcon#*before return 0, iclass 40, count 0 2006.257.09:48:57.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:57.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.09:48:57.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:48:57.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:48:57.99$vck44/vb=4,5 2006.257.09:48:57.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.09:48:57.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.09:48:57.99#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:57.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:58.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:58.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:58.05#ibcon#enter wrdev, iclass 4, count 2 2006.257.09:48:58.05#ibcon#first serial, iclass 4, count 2 2006.257.09:48:58.05#ibcon#enter sib2, iclass 4, count 2 2006.257.09:48:58.05#ibcon#flushed, iclass 4, count 2 2006.257.09:48:58.05#ibcon#about to write, iclass 4, count 2 2006.257.09:48:58.05#ibcon#wrote, iclass 4, count 2 2006.257.09:48:58.05#ibcon#about to read 3, iclass 4, count 2 2006.257.09:48:58.07#ibcon#read 3, iclass 4, count 2 2006.257.09:48:58.07#ibcon#about to read 4, iclass 4, count 2 2006.257.09:48:58.07#ibcon#read 4, iclass 4, count 2 2006.257.09:48:58.07#ibcon#about to read 5, iclass 4, count 2 2006.257.09:48:58.07#ibcon#read 5, iclass 4, count 2 2006.257.09:48:58.07#ibcon#about to read 6, iclass 4, count 2 2006.257.09:48:58.07#ibcon#read 6, iclass 4, count 2 2006.257.09:48:58.07#ibcon#end of sib2, iclass 4, count 2 2006.257.09:48:58.07#ibcon#*mode == 0, iclass 4, count 2 2006.257.09:48:58.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.09:48:58.07#ibcon#[27=AT04-05\r\n] 2006.257.09:48:58.07#ibcon#*before write, iclass 4, count 2 2006.257.09:48:58.07#ibcon#enter sib2, iclass 4, count 2 2006.257.09:48:58.07#ibcon#flushed, iclass 4, count 2 2006.257.09:48:58.07#ibcon#about to write, iclass 4, count 2 2006.257.09:48:58.07#ibcon#wrote, iclass 4, count 2 2006.257.09:48:58.07#ibcon#about to read 3, iclass 4, count 2 2006.257.09:48:58.10#ibcon#read 3, iclass 4, count 2 2006.257.09:48:58.10#ibcon#about to read 4, iclass 4, count 2 2006.257.09:48:58.10#ibcon#read 4, iclass 4, count 2 2006.257.09:48:58.10#ibcon#about to read 5, iclass 4, count 2 2006.257.09:48:58.10#ibcon#read 5, iclass 4, count 2 2006.257.09:48:58.10#ibcon#about to read 6, iclass 4, count 2 2006.257.09:48:58.10#ibcon#read 6, iclass 4, count 2 2006.257.09:48:58.10#ibcon#end of sib2, iclass 4, count 2 2006.257.09:48:58.10#ibcon#*after write, iclass 4, count 2 2006.257.09:48:58.10#ibcon#*before return 0, iclass 4, count 2 2006.257.09:48:58.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:58.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.09:48:58.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.09:48:58.10#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:58.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:58.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:58.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:58.22#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:48:58.22#ibcon#first serial, iclass 4, count 0 2006.257.09:48:58.22#ibcon#enter sib2, iclass 4, count 0 2006.257.09:48:58.22#ibcon#flushed, iclass 4, count 0 2006.257.09:48:58.22#ibcon#about to write, iclass 4, count 0 2006.257.09:48:58.22#ibcon#wrote, iclass 4, count 0 2006.257.09:48:58.22#ibcon#about to read 3, iclass 4, count 0 2006.257.09:48:58.24#ibcon#read 3, iclass 4, count 0 2006.257.09:48:58.24#ibcon#about to read 4, iclass 4, count 0 2006.257.09:48:58.24#ibcon#read 4, iclass 4, count 0 2006.257.09:48:58.24#ibcon#about to read 5, iclass 4, count 0 2006.257.09:48:58.24#ibcon#read 5, iclass 4, count 0 2006.257.09:48:58.24#ibcon#about to read 6, iclass 4, count 0 2006.257.09:48:58.24#ibcon#read 6, iclass 4, count 0 2006.257.09:48:58.24#ibcon#end of sib2, iclass 4, count 0 2006.257.09:48:58.24#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:48:58.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:48:58.24#ibcon#[27=USB\r\n] 2006.257.09:48:58.24#ibcon#*before write, iclass 4, count 0 2006.257.09:48:58.24#ibcon#enter sib2, iclass 4, count 0 2006.257.09:48:58.24#ibcon#flushed, iclass 4, count 0 2006.257.09:48:58.24#ibcon#about to write, iclass 4, count 0 2006.257.09:48:58.24#ibcon#wrote, iclass 4, count 0 2006.257.09:48:58.24#ibcon#about to read 3, iclass 4, count 0 2006.257.09:48:58.27#ibcon#read 3, iclass 4, count 0 2006.257.09:48:58.27#ibcon#about to read 4, iclass 4, count 0 2006.257.09:48:58.27#ibcon#read 4, iclass 4, count 0 2006.257.09:48:58.27#ibcon#about to read 5, iclass 4, count 0 2006.257.09:48:58.27#ibcon#read 5, iclass 4, count 0 2006.257.09:48:58.27#ibcon#about to read 6, iclass 4, count 0 2006.257.09:48:58.27#ibcon#read 6, iclass 4, count 0 2006.257.09:48:58.27#ibcon#end of sib2, iclass 4, count 0 2006.257.09:48:58.27#ibcon#*after write, iclass 4, count 0 2006.257.09:48:58.27#ibcon#*before return 0, iclass 4, count 0 2006.257.09:48:58.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:58.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.09:48:58.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:48:58.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:48:58.27$vck44/vblo=5,709.99 2006.257.09:48:58.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.09:48:58.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.09:48:58.27#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:58.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:58.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:58.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:58.27#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:48:58.27#ibcon#first serial, iclass 6, count 0 2006.257.09:48:58.27#ibcon#enter sib2, iclass 6, count 0 2006.257.09:48:58.27#ibcon#flushed, iclass 6, count 0 2006.257.09:48:58.27#ibcon#about to write, iclass 6, count 0 2006.257.09:48:58.27#ibcon#wrote, iclass 6, count 0 2006.257.09:48:58.27#ibcon#about to read 3, iclass 6, count 0 2006.257.09:48:58.29#ibcon#read 3, iclass 6, count 0 2006.257.09:48:58.29#ibcon#about to read 4, iclass 6, count 0 2006.257.09:48:58.29#ibcon#read 4, iclass 6, count 0 2006.257.09:48:58.29#ibcon#about to read 5, iclass 6, count 0 2006.257.09:48:58.29#ibcon#read 5, iclass 6, count 0 2006.257.09:48:58.29#ibcon#about to read 6, iclass 6, count 0 2006.257.09:48:58.29#ibcon#read 6, iclass 6, count 0 2006.257.09:48:58.29#ibcon#end of sib2, iclass 6, count 0 2006.257.09:48:58.29#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:48:58.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:48:58.29#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:48:58.29#ibcon#*before write, iclass 6, count 0 2006.257.09:48:58.29#ibcon#enter sib2, iclass 6, count 0 2006.257.09:48:58.29#ibcon#flushed, iclass 6, count 0 2006.257.09:48:58.29#ibcon#about to write, iclass 6, count 0 2006.257.09:48:58.29#ibcon#wrote, iclass 6, count 0 2006.257.09:48:58.29#ibcon#about to read 3, iclass 6, count 0 2006.257.09:48:58.33#ibcon#read 3, iclass 6, count 0 2006.257.09:48:58.33#ibcon#about to read 4, iclass 6, count 0 2006.257.09:48:58.33#ibcon#read 4, iclass 6, count 0 2006.257.09:48:58.33#ibcon#about to read 5, iclass 6, count 0 2006.257.09:48:58.33#ibcon#read 5, iclass 6, count 0 2006.257.09:48:58.33#ibcon#about to read 6, iclass 6, count 0 2006.257.09:48:58.33#ibcon#read 6, iclass 6, count 0 2006.257.09:48:58.33#ibcon#end of sib2, iclass 6, count 0 2006.257.09:48:58.33#ibcon#*after write, iclass 6, count 0 2006.257.09:48:58.33#ibcon#*before return 0, iclass 6, count 0 2006.257.09:48:58.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:58.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.09:48:58.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:48:58.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:48:58.33$vck44/vb=5,4 2006.257.09:48:58.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.09:48:58.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.09:48:58.33#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:58.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:58.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:58.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:58.39#ibcon#enter wrdev, iclass 10, count 2 2006.257.09:48:58.39#ibcon#first serial, iclass 10, count 2 2006.257.09:48:58.39#ibcon#enter sib2, iclass 10, count 2 2006.257.09:48:58.39#ibcon#flushed, iclass 10, count 2 2006.257.09:48:58.39#ibcon#about to write, iclass 10, count 2 2006.257.09:48:58.39#ibcon#wrote, iclass 10, count 2 2006.257.09:48:58.39#ibcon#about to read 3, iclass 10, count 2 2006.257.09:48:58.41#ibcon#read 3, iclass 10, count 2 2006.257.09:48:58.41#ibcon#about to read 4, iclass 10, count 2 2006.257.09:48:58.41#ibcon#read 4, iclass 10, count 2 2006.257.09:48:58.41#ibcon#about to read 5, iclass 10, count 2 2006.257.09:48:58.41#ibcon#read 5, iclass 10, count 2 2006.257.09:48:58.41#ibcon#about to read 6, iclass 10, count 2 2006.257.09:48:58.41#ibcon#read 6, iclass 10, count 2 2006.257.09:48:58.41#ibcon#end of sib2, iclass 10, count 2 2006.257.09:48:58.41#ibcon#*mode == 0, iclass 10, count 2 2006.257.09:48:58.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.09:48:58.41#ibcon#[27=AT05-04\r\n] 2006.257.09:48:58.41#ibcon#*before write, iclass 10, count 2 2006.257.09:48:58.41#ibcon#enter sib2, iclass 10, count 2 2006.257.09:48:58.41#ibcon#flushed, iclass 10, count 2 2006.257.09:48:58.41#ibcon#about to write, iclass 10, count 2 2006.257.09:48:58.41#ibcon#wrote, iclass 10, count 2 2006.257.09:48:58.41#ibcon#about to read 3, iclass 10, count 2 2006.257.09:48:58.44#ibcon#read 3, iclass 10, count 2 2006.257.09:48:58.44#ibcon#about to read 4, iclass 10, count 2 2006.257.09:48:58.44#ibcon#read 4, iclass 10, count 2 2006.257.09:48:58.44#ibcon#about to read 5, iclass 10, count 2 2006.257.09:48:58.44#ibcon#read 5, iclass 10, count 2 2006.257.09:48:58.44#ibcon#about to read 6, iclass 10, count 2 2006.257.09:48:58.44#ibcon#read 6, iclass 10, count 2 2006.257.09:48:58.44#ibcon#end of sib2, iclass 10, count 2 2006.257.09:48:58.44#ibcon#*after write, iclass 10, count 2 2006.257.09:48:58.44#ibcon#*before return 0, iclass 10, count 2 2006.257.09:48:58.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:58.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.09:48:58.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.09:48:58.44#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:58.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:58.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:58.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:58.56#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:48:58.56#ibcon#first serial, iclass 10, count 0 2006.257.09:48:58.56#ibcon#enter sib2, iclass 10, count 0 2006.257.09:48:58.56#ibcon#flushed, iclass 10, count 0 2006.257.09:48:58.56#ibcon#about to write, iclass 10, count 0 2006.257.09:48:58.56#ibcon#wrote, iclass 10, count 0 2006.257.09:48:58.56#ibcon#about to read 3, iclass 10, count 0 2006.257.09:48:58.58#ibcon#read 3, iclass 10, count 0 2006.257.09:48:58.58#ibcon#about to read 4, iclass 10, count 0 2006.257.09:48:58.58#ibcon#read 4, iclass 10, count 0 2006.257.09:48:58.58#ibcon#about to read 5, iclass 10, count 0 2006.257.09:48:58.58#ibcon#read 5, iclass 10, count 0 2006.257.09:48:58.58#ibcon#about to read 6, iclass 10, count 0 2006.257.09:48:58.58#ibcon#read 6, iclass 10, count 0 2006.257.09:48:58.58#ibcon#end of sib2, iclass 10, count 0 2006.257.09:48:58.58#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:48:58.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:48:58.58#ibcon#[27=USB\r\n] 2006.257.09:48:58.58#ibcon#*before write, iclass 10, count 0 2006.257.09:48:58.58#ibcon#enter sib2, iclass 10, count 0 2006.257.09:48:58.58#ibcon#flushed, iclass 10, count 0 2006.257.09:48:58.58#ibcon#about to write, iclass 10, count 0 2006.257.09:48:58.58#ibcon#wrote, iclass 10, count 0 2006.257.09:48:58.58#ibcon#about to read 3, iclass 10, count 0 2006.257.09:48:58.61#ibcon#read 3, iclass 10, count 0 2006.257.09:48:58.61#ibcon#about to read 4, iclass 10, count 0 2006.257.09:48:58.61#ibcon#read 4, iclass 10, count 0 2006.257.09:48:58.61#ibcon#about to read 5, iclass 10, count 0 2006.257.09:48:58.61#ibcon#read 5, iclass 10, count 0 2006.257.09:48:58.61#ibcon#about to read 6, iclass 10, count 0 2006.257.09:48:58.61#ibcon#read 6, iclass 10, count 0 2006.257.09:48:58.61#ibcon#end of sib2, iclass 10, count 0 2006.257.09:48:58.61#ibcon#*after write, iclass 10, count 0 2006.257.09:48:58.61#ibcon#*before return 0, iclass 10, count 0 2006.257.09:48:58.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:58.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.09:48:58.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:48:58.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:48:58.61$vck44/vblo=6,719.99 2006.257.09:48:58.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.09:48:58.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.09:48:58.61#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:58.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:58.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:58.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:58.61#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:48:58.61#ibcon#first serial, iclass 12, count 0 2006.257.09:48:58.61#ibcon#enter sib2, iclass 12, count 0 2006.257.09:48:58.61#ibcon#flushed, iclass 12, count 0 2006.257.09:48:58.61#ibcon#about to write, iclass 12, count 0 2006.257.09:48:58.61#ibcon#wrote, iclass 12, count 0 2006.257.09:48:58.61#ibcon#about to read 3, iclass 12, count 0 2006.257.09:48:58.63#ibcon#read 3, iclass 12, count 0 2006.257.09:48:58.63#ibcon#about to read 4, iclass 12, count 0 2006.257.09:48:58.63#ibcon#read 4, iclass 12, count 0 2006.257.09:48:58.63#ibcon#about to read 5, iclass 12, count 0 2006.257.09:48:58.63#ibcon#read 5, iclass 12, count 0 2006.257.09:48:58.63#ibcon#about to read 6, iclass 12, count 0 2006.257.09:48:58.63#ibcon#read 6, iclass 12, count 0 2006.257.09:48:58.63#ibcon#end of sib2, iclass 12, count 0 2006.257.09:48:58.63#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:48:58.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:48:58.63#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:48:58.63#ibcon#*before write, iclass 12, count 0 2006.257.09:48:58.63#ibcon#enter sib2, iclass 12, count 0 2006.257.09:48:58.63#ibcon#flushed, iclass 12, count 0 2006.257.09:48:58.63#ibcon#about to write, iclass 12, count 0 2006.257.09:48:58.63#ibcon#wrote, iclass 12, count 0 2006.257.09:48:58.63#ibcon#about to read 3, iclass 12, count 0 2006.257.09:48:58.67#ibcon#read 3, iclass 12, count 0 2006.257.09:48:58.67#ibcon#about to read 4, iclass 12, count 0 2006.257.09:48:58.67#ibcon#read 4, iclass 12, count 0 2006.257.09:48:58.67#ibcon#about to read 5, iclass 12, count 0 2006.257.09:48:58.67#ibcon#read 5, iclass 12, count 0 2006.257.09:48:58.67#ibcon#about to read 6, iclass 12, count 0 2006.257.09:48:58.67#ibcon#read 6, iclass 12, count 0 2006.257.09:48:58.67#ibcon#end of sib2, iclass 12, count 0 2006.257.09:48:58.67#ibcon#*after write, iclass 12, count 0 2006.257.09:48:58.67#ibcon#*before return 0, iclass 12, count 0 2006.257.09:48:58.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:58.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.09:48:58.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:48:58.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:48:58.67$vck44/vb=6,4 2006.257.09:48:58.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.09:48:58.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.09:48:58.67#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:58.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:58.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:58.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:58.73#ibcon#enter wrdev, iclass 14, count 2 2006.257.09:48:58.73#ibcon#first serial, iclass 14, count 2 2006.257.09:48:58.73#ibcon#enter sib2, iclass 14, count 2 2006.257.09:48:58.73#ibcon#flushed, iclass 14, count 2 2006.257.09:48:58.73#ibcon#about to write, iclass 14, count 2 2006.257.09:48:58.73#ibcon#wrote, iclass 14, count 2 2006.257.09:48:58.73#ibcon#about to read 3, iclass 14, count 2 2006.257.09:48:58.75#ibcon#read 3, iclass 14, count 2 2006.257.09:48:58.75#ibcon#about to read 4, iclass 14, count 2 2006.257.09:48:58.75#ibcon#read 4, iclass 14, count 2 2006.257.09:48:58.75#ibcon#about to read 5, iclass 14, count 2 2006.257.09:48:58.75#ibcon#read 5, iclass 14, count 2 2006.257.09:48:58.75#ibcon#about to read 6, iclass 14, count 2 2006.257.09:48:58.75#ibcon#read 6, iclass 14, count 2 2006.257.09:48:58.75#ibcon#end of sib2, iclass 14, count 2 2006.257.09:48:58.75#ibcon#*mode == 0, iclass 14, count 2 2006.257.09:48:58.75#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.09:48:58.75#ibcon#[27=AT06-04\r\n] 2006.257.09:48:58.75#ibcon#*before write, iclass 14, count 2 2006.257.09:48:58.75#ibcon#enter sib2, iclass 14, count 2 2006.257.09:48:58.75#ibcon#flushed, iclass 14, count 2 2006.257.09:48:58.75#ibcon#about to write, iclass 14, count 2 2006.257.09:48:58.75#ibcon#wrote, iclass 14, count 2 2006.257.09:48:58.75#ibcon#about to read 3, iclass 14, count 2 2006.257.09:48:58.78#ibcon#read 3, iclass 14, count 2 2006.257.09:48:58.78#ibcon#about to read 4, iclass 14, count 2 2006.257.09:48:58.78#ibcon#read 4, iclass 14, count 2 2006.257.09:48:58.78#ibcon#about to read 5, iclass 14, count 2 2006.257.09:48:58.78#ibcon#read 5, iclass 14, count 2 2006.257.09:48:58.78#ibcon#about to read 6, iclass 14, count 2 2006.257.09:48:58.78#ibcon#read 6, iclass 14, count 2 2006.257.09:48:58.78#ibcon#end of sib2, iclass 14, count 2 2006.257.09:48:58.78#ibcon#*after write, iclass 14, count 2 2006.257.09:48:58.78#ibcon#*before return 0, iclass 14, count 2 2006.257.09:48:58.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:58.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.09:48:58.78#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.09:48:58.78#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:58.78#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:58.90#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:58.90#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:58.90#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:48:58.90#ibcon#first serial, iclass 14, count 0 2006.257.09:48:58.90#ibcon#enter sib2, iclass 14, count 0 2006.257.09:48:58.90#ibcon#flushed, iclass 14, count 0 2006.257.09:48:58.90#ibcon#about to write, iclass 14, count 0 2006.257.09:48:58.90#ibcon#wrote, iclass 14, count 0 2006.257.09:48:58.90#ibcon#about to read 3, iclass 14, count 0 2006.257.09:48:58.92#ibcon#read 3, iclass 14, count 0 2006.257.09:48:58.92#ibcon#about to read 4, iclass 14, count 0 2006.257.09:48:58.92#ibcon#read 4, iclass 14, count 0 2006.257.09:48:58.92#ibcon#about to read 5, iclass 14, count 0 2006.257.09:48:58.92#ibcon#read 5, iclass 14, count 0 2006.257.09:48:58.92#ibcon#about to read 6, iclass 14, count 0 2006.257.09:48:58.92#ibcon#read 6, iclass 14, count 0 2006.257.09:48:58.92#ibcon#end of sib2, iclass 14, count 0 2006.257.09:48:58.92#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:48:58.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:48:58.92#ibcon#[27=USB\r\n] 2006.257.09:48:58.92#ibcon#*before write, iclass 14, count 0 2006.257.09:48:58.92#ibcon#enter sib2, iclass 14, count 0 2006.257.09:48:58.92#ibcon#flushed, iclass 14, count 0 2006.257.09:48:58.92#ibcon#about to write, iclass 14, count 0 2006.257.09:48:58.92#ibcon#wrote, iclass 14, count 0 2006.257.09:48:58.92#ibcon#about to read 3, iclass 14, count 0 2006.257.09:48:58.95#ibcon#read 3, iclass 14, count 0 2006.257.09:48:58.95#ibcon#about to read 4, iclass 14, count 0 2006.257.09:48:58.95#ibcon#read 4, iclass 14, count 0 2006.257.09:48:58.95#ibcon#about to read 5, iclass 14, count 0 2006.257.09:48:58.95#ibcon#read 5, iclass 14, count 0 2006.257.09:48:58.95#ibcon#about to read 6, iclass 14, count 0 2006.257.09:48:58.95#ibcon#read 6, iclass 14, count 0 2006.257.09:48:58.95#ibcon#end of sib2, iclass 14, count 0 2006.257.09:48:58.95#ibcon#*after write, iclass 14, count 0 2006.257.09:48:58.95#ibcon#*before return 0, iclass 14, count 0 2006.257.09:48:58.95#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:58.95#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.09:48:58.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:48:58.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:48:58.95$vck44/vblo=7,734.99 2006.257.09:48:58.95#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.09:48:58.95#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.09:48:58.95#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:58.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:58.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:58.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:58.95#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:48:58.95#ibcon#first serial, iclass 16, count 0 2006.257.09:48:58.95#ibcon#enter sib2, iclass 16, count 0 2006.257.09:48:58.95#ibcon#flushed, iclass 16, count 0 2006.257.09:48:58.95#ibcon#about to write, iclass 16, count 0 2006.257.09:48:58.95#ibcon#wrote, iclass 16, count 0 2006.257.09:48:58.95#ibcon#about to read 3, iclass 16, count 0 2006.257.09:48:58.97#ibcon#read 3, iclass 16, count 0 2006.257.09:48:58.97#ibcon#about to read 4, iclass 16, count 0 2006.257.09:48:58.97#ibcon#read 4, iclass 16, count 0 2006.257.09:48:58.97#ibcon#about to read 5, iclass 16, count 0 2006.257.09:48:58.97#ibcon#read 5, iclass 16, count 0 2006.257.09:48:58.97#ibcon#about to read 6, iclass 16, count 0 2006.257.09:48:58.97#ibcon#read 6, iclass 16, count 0 2006.257.09:48:58.97#ibcon#end of sib2, iclass 16, count 0 2006.257.09:48:58.97#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:48:58.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:48:58.97#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:48:58.97#ibcon#*before write, iclass 16, count 0 2006.257.09:48:58.97#ibcon#enter sib2, iclass 16, count 0 2006.257.09:48:58.97#ibcon#flushed, iclass 16, count 0 2006.257.09:48:58.97#ibcon#about to write, iclass 16, count 0 2006.257.09:48:58.97#ibcon#wrote, iclass 16, count 0 2006.257.09:48:58.97#ibcon#about to read 3, iclass 16, count 0 2006.257.09:48:59.01#ibcon#read 3, iclass 16, count 0 2006.257.09:48:59.01#ibcon#about to read 4, iclass 16, count 0 2006.257.09:48:59.01#ibcon#read 4, iclass 16, count 0 2006.257.09:48:59.01#ibcon#about to read 5, iclass 16, count 0 2006.257.09:48:59.01#ibcon#read 5, iclass 16, count 0 2006.257.09:48:59.01#ibcon#about to read 6, iclass 16, count 0 2006.257.09:48:59.01#ibcon#read 6, iclass 16, count 0 2006.257.09:48:59.01#ibcon#end of sib2, iclass 16, count 0 2006.257.09:48:59.01#ibcon#*after write, iclass 16, count 0 2006.257.09:48:59.01#ibcon#*before return 0, iclass 16, count 0 2006.257.09:48:59.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:59.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.09:48:59.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:48:59.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:48:59.01$vck44/vb=7,4 2006.257.09:48:59.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.09:48:59.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.09:48:59.01#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:59.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:59.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:59.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:59.07#ibcon#enter wrdev, iclass 18, count 2 2006.257.09:48:59.07#ibcon#first serial, iclass 18, count 2 2006.257.09:48:59.07#ibcon#enter sib2, iclass 18, count 2 2006.257.09:48:59.07#ibcon#flushed, iclass 18, count 2 2006.257.09:48:59.07#ibcon#about to write, iclass 18, count 2 2006.257.09:48:59.07#ibcon#wrote, iclass 18, count 2 2006.257.09:48:59.07#ibcon#about to read 3, iclass 18, count 2 2006.257.09:48:59.09#ibcon#read 3, iclass 18, count 2 2006.257.09:48:59.09#ibcon#about to read 4, iclass 18, count 2 2006.257.09:48:59.09#ibcon#read 4, iclass 18, count 2 2006.257.09:48:59.09#ibcon#about to read 5, iclass 18, count 2 2006.257.09:48:59.09#ibcon#read 5, iclass 18, count 2 2006.257.09:48:59.09#ibcon#about to read 6, iclass 18, count 2 2006.257.09:48:59.09#ibcon#read 6, iclass 18, count 2 2006.257.09:48:59.09#ibcon#end of sib2, iclass 18, count 2 2006.257.09:48:59.09#ibcon#*mode == 0, iclass 18, count 2 2006.257.09:48:59.09#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.09:48:59.09#ibcon#[27=AT07-04\r\n] 2006.257.09:48:59.09#ibcon#*before write, iclass 18, count 2 2006.257.09:48:59.09#ibcon#enter sib2, iclass 18, count 2 2006.257.09:48:59.09#ibcon#flushed, iclass 18, count 2 2006.257.09:48:59.09#ibcon#about to write, iclass 18, count 2 2006.257.09:48:59.09#ibcon#wrote, iclass 18, count 2 2006.257.09:48:59.09#ibcon#about to read 3, iclass 18, count 2 2006.257.09:48:59.12#ibcon#read 3, iclass 18, count 2 2006.257.09:48:59.12#ibcon#about to read 4, iclass 18, count 2 2006.257.09:48:59.12#ibcon#read 4, iclass 18, count 2 2006.257.09:48:59.12#ibcon#about to read 5, iclass 18, count 2 2006.257.09:48:59.12#ibcon#read 5, iclass 18, count 2 2006.257.09:48:59.12#ibcon#about to read 6, iclass 18, count 2 2006.257.09:48:59.12#ibcon#read 6, iclass 18, count 2 2006.257.09:48:59.12#ibcon#end of sib2, iclass 18, count 2 2006.257.09:48:59.12#ibcon#*after write, iclass 18, count 2 2006.257.09:48:59.12#ibcon#*before return 0, iclass 18, count 2 2006.257.09:48:59.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:59.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.09:48:59.12#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.09:48:59.12#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:59.12#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:59.24#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:59.24#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:59.24#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:48:59.24#ibcon#first serial, iclass 18, count 0 2006.257.09:48:59.24#ibcon#enter sib2, iclass 18, count 0 2006.257.09:48:59.24#ibcon#flushed, iclass 18, count 0 2006.257.09:48:59.24#ibcon#about to write, iclass 18, count 0 2006.257.09:48:59.24#ibcon#wrote, iclass 18, count 0 2006.257.09:48:59.24#ibcon#about to read 3, iclass 18, count 0 2006.257.09:48:59.26#ibcon#read 3, iclass 18, count 0 2006.257.09:48:59.26#ibcon#about to read 4, iclass 18, count 0 2006.257.09:48:59.26#ibcon#read 4, iclass 18, count 0 2006.257.09:48:59.26#ibcon#about to read 5, iclass 18, count 0 2006.257.09:48:59.26#ibcon#read 5, iclass 18, count 0 2006.257.09:48:59.26#ibcon#about to read 6, iclass 18, count 0 2006.257.09:48:59.26#ibcon#read 6, iclass 18, count 0 2006.257.09:48:59.26#ibcon#end of sib2, iclass 18, count 0 2006.257.09:48:59.26#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:48:59.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:48:59.26#ibcon#[27=USB\r\n] 2006.257.09:48:59.26#ibcon#*before write, iclass 18, count 0 2006.257.09:48:59.26#ibcon#enter sib2, iclass 18, count 0 2006.257.09:48:59.26#ibcon#flushed, iclass 18, count 0 2006.257.09:48:59.26#ibcon#about to write, iclass 18, count 0 2006.257.09:48:59.26#ibcon#wrote, iclass 18, count 0 2006.257.09:48:59.26#ibcon#about to read 3, iclass 18, count 0 2006.257.09:48:59.29#ibcon#read 3, iclass 18, count 0 2006.257.09:48:59.29#ibcon#about to read 4, iclass 18, count 0 2006.257.09:48:59.29#ibcon#read 4, iclass 18, count 0 2006.257.09:48:59.29#ibcon#about to read 5, iclass 18, count 0 2006.257.09:48:59.29#ibcon#read 5, iclass 18, count 0 2006.257.09:48:59.29#ibcon#about to read 6, iclass 18, count 0 2006.257.09:48:59.29#ibcon#read 6, iclass 18, count 0 2006.257.09:48:59.29#ibcon#end of sib2, iclass 18, count 0 2006.257.09:48:59.29#ibcon#*after write, iclass 18, count 0 2006.257.09:48:59.29#ibcon#*before return 0, iclass 18, count 0 2006.257.09:48:59.29#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:59.29#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.09:48:59.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:48:59.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:48:59.29$vck44/vblo=8,744.99 2006.257.09:48:59.29#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.09:48:59.29#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.09:48:59.29#ibcon#ireg 17 cls_cnt 0 2006.257.09:48:59.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:59.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:59.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:59.29#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:48:59.29#ibcon#first serial, iclass 20, count 0 2006.257.09:48:59.29#ibcon#enter sib2, iclass 20, count 0 2006.257.09:48:59.29#ibcon#flushed, iclass 20, count 0 2006.257.09:48:59.29#ibcon#about to write, iclass 20, count 0 2006.257.09:48:59.29#ibcon#wrote, iclass 20, count 0 2006.257.09:48:59.29#ibcon#about to read 3, iclass 20, count 0 2006.257.09:48:59.31#ibcon#read 3, iclass 20, count 0 2006.257.09:48:59.31#ibcon#about to read 4, iclass 20, count 0 2006.257.09:48:59.31#ibcon#read 4, iclass 20, count 0 2006.257.09:48:59.31#ibcon#about to read 5, iclass 20, count 0 2006.257.09:48:59.31#ibcon#read 5, iclass 20, count 0 2006.257.09:48:59.31#ibcon#about to read 6, iclass 20, count 0 2006.257.09:48:59.31#ibcon#read 6, iclass 20, count 0 2006.257.09:48:59.31#ibcon#end of sib2, iclass 20, count 0 2006.257.09:48:59.31#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:48:59.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:48:59.31#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:48:59.31#ibcon#*before write, iclass 20, count 0 2006.257.09:48:59.31#ibcon#enter sib2, iclass 20, count 0 2006.257.09:48:59.31#ibcon#flushed, iclass 20, count 0 2006.257.09:48:59.31#ibcon#about to write, iclass 20, count 0 2006.257.09:48:59.31#ibcon#wrote, iclass 20, count 0 2006.257.09:48:59.31#ibcon#about to read 3, iclass 20, count 0 2006.257.09:48:59.35#ibcon#read 3, iclass 20, count 0 2006.257.09:48:59.35#ibcon#about to read 4, iclass 20, count 0 2006.257.09:48:59.35#ibcon#read 4, iclass 20, count 0 2006.257.09:48:59.35#ibcon#about to read 5, iclass 20, count 0 2006.257.09:48:59.35#ibcon#read 5, iclass 20, count 0 2006.257.09:48:59.35#ibcon#about to read 6, iclass 20, count 0 2006.257.09:48:59.35#ibcon#read 6, iclass 20, count 0 2006.257.09:48:59.35#ibcon#end of sib2, iclass 20, count 0 2006.257.09:48:59.35#ibcon#*after write, iclass 20, count 0 2006.257.09:48:59.35#ibcon#*before return 0, iclass 20, count 0 2006.257.09:48:59.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:59.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.09:48:59.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:48:59.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:48:59.35$vck44/vb=8,4 2006.257.09:48:59.35#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.09:48:59.35#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.09:48:59.35#ibcon#ireg 11 cls_cnt 2 2006.257.09:48:59.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:48:59.38#abcon#<5=/14 0.8 1.9 19.35 961013.4\r\n> 2006.257.09:48:59.40#abcon#{5=INTERFACE CLEAR} 2006.257.09:48:59.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:48:59.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:48:59.41#ibcon#enter wrdev, iclass 23, count 2 2006.257.09:48:59.41#ibcon#first serial, iclass 23, count 2 2006.257.09:48:59.41#ibcon#enter sib2, iclass 23, count 2 2006.257.09:48:59.41#ibcon#flushed, iclass 23, count 2 2006.257.09:48:59.41#ibcon#about to write, iclass 23, count 2 2006.257.09:48:59.41#ibcon#wrote, iclass 23, count 2 2006.257.09:48:59.41#ibcon#about to read 3, iclass 23, count 2 2006.257.09:48:59.43#ibcon#read 3, iclass 23, count 2 2006.257.09:48:59.43#ibcon#about to read 4, iclass 23, count 2 2006.257.09:48:59.43#ibcon#read 4, iclass 23, count 2 2006.257.09:48:59.43#ibcon#about to read 5, iclass 23, count 2 2006.257.09:48:59.43#ibcon#read 5, iclass 23, count 2 2006.257.09:48:59.43#ibcon#about to read 6, iclass 23, count 2 2006.257.09:48:59.43#ibcon#read 6, iclass 23, count 2 2006.257.09:48:59.43#ibcon#end of sib2, iclass 23, count 2 2006.257.09:48:59.43#ibcon#*mode == 0, iclass 23, count 2 2006.257.09:48:59.43#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.09:48:59.43#ibcon#[27=AT08-04\r\n] 2006.257.09:48:59.43#ibcon#*before write, iclass 23, count 2 2006.257.09:48:59.43#ibcon#enter sib2, iclass 23, count 2 2006.257.09:48:59.43#ibcon#flushed, iclass 23, count 2 2006.257.09:48:59.43#ibcon#about to write, iclass 23, count 2 2006.257.09:48:59.43#ibcon#wrote, iclass 23, count 2 2006.257.09:48:59.43#ibcon#about to read 3, iclass 23, count 2 2006.257.09:48:59.46#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:48:59.46#ibcon#read 3, iclass 23, count 2 2006.257.09:48:59.46#ibcon#about to read 4, iclass 23, count 2 2006.257.09:48:59.46#ibcon#read 4, iclass 23, count 2 2006.257.09:48:59.46#ibcon#about to read 5, iclass 23, count 2 2006.257.09:48:59.46#ibcon#read 5, iclass 23, count 2 2006.257.09:48:59.46#ibcon#about to read 6, iclass 23, count 2 2006.257.09:48:59.46#ibcon#read 6, iclass 23, count 2 2006.257.09:48:59.46#ibcon#end of sib2, iclass 23, count 2 2006.257.09:48:59.46#ibcon#*after write, iclass 23, count 2 2006.257.09:48:59.46#ibcon#*before return 0, iclass 23, count 2 2006.257.09:48:59.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:48:59.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.09:48:59.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.09:48:59.46#ibcon#ireg 7 cls_cnt 0 2006.257.09:48:59.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:48:59.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:48:59.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:48:59.58#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:48:59.58#ibcon#first serial, iclass 23, count 0 2006.257.09:48:59.58#ibcon#enter sib2, iclass 23, count 0 2006.257.09:48:59.58#ibcon#flushed, iclass 23, count 0 2006.257.09:48:59.58#ibcon#about to write, iclass 23, count 0 2006.257.09:48:59.58#ibcon#wrote, iclass 23, count 0 2006.257.09:48:59.58#ibcon#about to read 3, iclass 23, count 0 2006.257.09:48:59.60#ibcon#read 3, iclass 23, count 0 2006.257.09:48:59.60#ibcon#about to read 4, iclass 23, count 0 2006.257.09:48:59.60#ibcon#read 4, iclass 23, count 0 2006.257.09:48:59.60#ibcon#about to read 5, iclass 23, count 0 2006.257.09:48:59.60#ibcon#read 5, iclass 23, count 0 2006.257.09:48:59.60#ibcon#about to read 6, iclass 23, count 0 2006.257.09:48:59.60#ibcon#read 6, iclass 23, count 0 2006.257.09:48:59.60#ibcon#end of sib2, iclass 23, count 0 2006.257.09:48:59.60#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:48:59.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:48:59.60#ibcon#[27=USB\r\n] 2006.257.09:48:59.60#ibcon#*before write, iclass 23, count 0 2006.257.09:48:59.60#ibcon#enter sib2, iclass 23, count 0 2006.257.09:48:59.60#ibcon#flushed, iclass 23, count 0 2006.257.09:48:59.60#ibcon#about to write, iclass 23, count 0 2006.257.09:48:59.60#ibcon#wrote, iclass 23, count 0 2006.257.09:48:59.60#ibcon#about to read 3, iclass 23, count 0 2006.257.09:48:59.63#ibcon#read 3, iclass 23, count 0 2006.257.09:48:59.63#ibcon#about to read 4, iclass 23, count 0 2006.257.09:48:59.63#ibcon#read 4, iclass 23, count 0 2006.257.09:48:59.63#ibcon#about to read 5, iclass 23, count 0 2006.257.09:48:59.63#ibcon#read 5, iclass 23, count 0 2006.257.09:48:59.63#ibcon#about to read 6, iclass 23, count 0 2006.257.09:48:59.63#ibcon#read 6, iclass 23, count 0 2006.257.09:48:59.63#ibcon#end of sib2, iclass 23, count 0 2006.257.09:48:59.63#ibcon#*after write, iclass 23, count 0 2006.257.09:48:59.63#ibcon#*before return 0, iclass 23, count 0 2006.257.09:48:59.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:48:59.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.09:48:59.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:48:59.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:48:59.63$vck44/vabw=wide 2006.257.09:48:59.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.09:48:59.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.09:48:59.63#ibcon#ireg 8 cls_cnt 0 2006.257.09:48:59.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:59.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:59.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:59.63#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:48:59.63#ibcon#first serial, iclass 28, count 0 2006.257.09:48:59.63#ibcon#enter sib2, iclass 28, count 0 2006.257.09:48:59.63#ibcon#flushed, iclass 28, count 0 2006.257.09:48:59.63#ibcon#about to write, iclass 28, count 0 2006.257.09:48:59.63#ibcon#wrote, iclass 28, count 0 2006.257.09:48:59.63#ibcon#about to read 3, iclass 28, count 0 2006.257.09:48:59.65#ibcon#read 3, iclass 28, count 0 2006.257.09:48:59.65#ibcon#about to read 4, iclass 28, count 0 2006.257.09:48:59.65#ibcon#read 4, iclass 28, count 0 2006.257.09:48:59.65#ibcon#about to read 5, iclass 28, count 0 2006.257.09:48:59.65#ibcon#read 5, iclass 28, count 0 2006.257.09:48:59.65#ibcon#about to read 6, iclass 28, count 0 2006.257.09:48:59.65#ibcon#read 6, iclass 28, count 0 2006.257.09:48:59.65#ibcon#end of sib2, iclass 28, count 0 2006.257.09:48:59.65#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:48:59.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:48:59.65#ibcon#[25=BW32\r\n] 2006.257.09:48:59.65#ibcon#*before write, iclass 28, count 0 2006.257.09:48:59.65#ibcon#enter sib2, iclass 28, count 0 2006.257.09:48:59.65#ibcon#flushed, iclass 28, count 0 2006.257.09:48:59.65#ibcon#about to write, iclass 28, count 0 2006.257.09:48:59.65#ibcon#wrote, iclass 28, count 0 2006.257.09:48:59.65#ibcon#about to read 3, iclass 28, count 0 2006.257.09:48:59.68#ibcon#read 3, iclass 28, count 0 2006.257.09:48:59.68#ibcon#about to read 4, iclass 28, count 0 2006.257.09:48:59.68#ibcon#read 4, iclass 28, count 0 2006.257.09:48:59.68#ibcon#about to read 5, iclass 28, count 0 2006.257.09:48:59.68#ibcon#read 5, iclass 28, count 0 2006.257.09:48:59.68#ibcon#about to read 6, iclass 28, count 0 2006.257.09:48:59.68#ibcon#read 6, iclass 28, count 0 2006.257.09:48:59.68#ibcon#end of sib2, iclass 28, count 0 2006.257.09:48:59.68#ibcon#*after write, iclass 28, count 0 2006.257.09:48:59.68#ibcon#*before return 0, iclass 28, count 0 2006.257.09:48:59.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:59.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.09:48:59.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:48:59.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:48:59.68$vck44/vbbw=wide 2006.257.09:48:59.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.09:48:59.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.09:48:59.68#ibcon#ireg 8 cls_cnt 0 2006.257.09:48:59.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:48:59.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:48:59.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:48:59.75#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:48:59.75#ibcon#first serial, iclass 30, count 0 2006.257.09:48:59.75#ibcon#enter sib2, iclass 30, count 0 2006.257.09:48:59.75#ibcon#flushed, iclass 30, count 0 2006.257.09:48:59.75#ibcon#about to write, iclass 30, count 0 2006.257.09:48:59.75#ibcon#wrote, iclass 30, count 0 2006.257.09:48:59.75#ibcon#about to read 3, iclass 30, count 0 2006.257.09:48:59.77#ibcon#read 3, iclass 30, count 0 2006.257.09:48:59.77#ibcon#about to read 4, iclass 30, count 0 2006.257.09:48:59.77#ibcon#read 4, iclass 30, count 0 2006.257.09:48:59.77#ibcon#about to read 5, iclass 30, count 0 2006.257.09:48:59.77#ibcon#read 5, iclass 30, count 0 2006.257.09:48:59.77#ibcon#about to read 6, iclass 30, count 0 2006.257.09:48:59.77#ibcon#read 6, iclass 30, count 0 2006.257.09:48:59.77#ibcon#end of sib2, iclass 30, count 0 2006.257.09:48:59.77#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:48:59.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:48:59.77#ibcon#[27=BW32\r\n] 2006.257.09:48:59.77#ibcon#*before write, iclass 30, count 0 2006.257.09:48:59.77#ibcon#enter sib2, iclass 30, count 0 2006.257.09:48:59.77#ibcon#flushed, iclass 30, count 0 2006.257.09:48:59.77#ibcon#about to write, iclass 30, count 0 2006.257.09:48:59.77#ibcon#wrote, iclass 30, count 0 2006.257.09:48:59.77#ibcon#about to read 3, iclass 30, count 0 2006.257.09:48:59.80#ibcon#read 3, iclass 30, count 0 2006.257.09:48:59.80#ibcon#about to read 4, iclass 30, count 0 2006.257.09:48:59.80#ibcon#read 4, iclass 30, count 0 2006.257.09:48:59.80#ibcon#about to read 5, iclass 30, count 0 2006.257.09:48:59.80#ibcon#read 5, iclass 30, count 0 2006.257.09:48:59.80#ibcon#about to read 6, iclass 30, count 0 2006.257.09:48:59.80#ibcon#read 6, iclass 30, count 0 2006.257.09:48:59.80#ibcon#end of sib2, iclass 30, count 0 2006.257.09:48:59.80#ibcon#*after write, iclass 30, count 0 2006.257.09:48:59.80#ibcon#*before return 0, iclass 30, count 0 2006.257.09:48:59.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:48:59.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:48:59.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:48:59.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:48:59.80$setupk4/ifdk4 2006.257.09:48:59.80$ifdk4/lo= 2006.257.09:48:59.80$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:48:59.80$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:48:59.80$ifdk4/patch= 2006.257.09:48:59.80$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:48:59.80$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:48:59.80$setupk4/!*+20s 2006.257.09:49:09.55#abcon#<5=/14 0.8 2.0 19.35 961013.4\r\n> 2006.257.09:49:09.57#abcon#{5=INTERFACE CLEAR} 2006.257.09:49:09.63#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:49:14.31$setupk4/"tpicd 2006.257.09:49:14.31$setupk4/echo=off 2006.257.09:49:14.31$setupk4/xlog=off 2006.257.09:49:14.31:!2006.257.09:50:23 2006.257.09:49:23.13#trakl#Source acquired 2006.257.09:49:25.13#flagr#flagr/antenna,acquired 2006.257.09:50:23.00:preob 2006.257.09:50:23.13/onsource/TRACKING 2006.257.09:50:23.13:!2006.257.09:50:33 2006.257.09:50:33.00:"tape 2006.257.09:50:33.00:"st=record 2006.257.09:50:33.00:data_valid=on 2006.257.09:50:33.00:midob 2006.257.09:50:34.14/onsource/TRACKING 2006.257.09:50:34.14/wx/19.33,1013.4,96 2006.257.09:50:34.24/cable/+6.4753E-03 2006.257.09:50:35.33/va/01,08,usb,yes,31,33 2006.257.09:50:35.33/va/02,07,usb,yes,33,34 2006.257.09:50:35.33/va/03,08,usb,yes,30,31 2006.257.09:50:35.33/va/04,07,usb,yes,34,36 2006.257.09:50:35.33/va/05,04,usb,yes,31,31 2006.257.09:50:35.33/va/06,04,usb,yes,34,34 2006.257.09:50:35.33/va/07,04,usb,yes,35,35 2006.257.09:50:35.33/va/08,04,usb,yes,29,36 2006.257.09:50:35.56/valo/01,524.99,yes,locked 2006.257.09:50:35.56/valo/02,534.99,yes,locked 2006.257.09:50:35.56/valo/03,564.99,yes,locked 2006.257.09:50:35.56/valo/04,624.99,yes,locked 2006.257.09:50:35.56/valo/05,734.99,yes,locked 2006.257.09:50:35.56/valo/06,814.99,yes,locked 2006.257.09:50:35.56/valo/07,864.99,yes,locked 2006.257.09:50:35.56/valo/08,884.99,yes,locked 2006.257.09:50:36.65/vb/01,04,usb,yes,30,28 2006.257.09:50:36.65/vb/02,05,usb,yes,29,29 2006.257.09:50:36.65/vb/03,04,usb,yes,30,33 2006.257.09:50:36.65/vb/04,05,usb,yes,30,29 2006.257.09:50:36.65/vb/05,04,usb,yes,26,29 2006.257.09:50:36.65/vb/06,04,usb,yes,31,27 2006.257.09:50:36.65/vb/07,04,usb,yes,31,31 2006.257.09:50:36.65/vb/08,04,usb,yes,28,32 2006.257.09:50:36.89/vblo/01,629.99,yes,locked 2006.257.09:50:36.89/vblo/02,634.99,yes,locked 2006.257.09:50:36.89/vblo/03,649.99,yes,locked 2006.257.09:50:36.89/vblo/04,679.99,yes,locked 2006.257.09:50:36.89/vblo/05,709.99,yes,locked 2006.257.09:50:36.89/vblo/06,719.99,yes,locked 2006.257.09:50:36.89/vblo/07,734.99,yes,locked 2006.257.09:50:36.89/vblo/08,744.99,yes,locked 2006.257.09:50:37.04/vabw/8 2006.257.09:50:37.19/vbbw/8 2006.257.09:50:37.28/xfe/off,on,15.2 2006.257.09:50:37.65/ifatt/23,28,28,28 2006.257.09:50:38.07/fmout-gps/S +4.65E-07 2006.257.09:50:38.11:!2006.257.09:51:13 2006.257.09:51:13.01:data_valid=off 2006.257.09:51:13.01:"et 2006.257.09:51:13.01:!+3s 2006.257.09:51:16.02:"tape 2006.257.09:51:16.02:postob 2006.257.09:51:16.08/cable/+6.4749E-03 2006.257.09:51:16.08/wx/19.32,1013.4,96 2006.257.09:51:16.14/fmout-gps/S +4.64E-07 2006.257.09:51:16.14:scan_name=257-0953,jd0609,180 2006.257.09:51:16.14:source=3c446,222547.26,-045701.4,2000.0,cw 2006.257.09:51:18.14#flagr#flagr/antenna,new-source 2006.257.09:51:18.14:checkk5 2006.257.09:51:18.52/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:51:18.91/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:51:19.29/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:51:19.68/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:51:20.07/chk_obsdata//k5ts1/T2570950??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:51:20.47/chk_obsdata//k5ts2/T2570950??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:51:20.87/chk_obsdata//k5ts3/T2570950??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:51:21.26/chk_obsdata//k5ts4/T2570950??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.09:51:21.98/k5log//k5ts1_log_newline 2006.257.09:51:22.68/k5log//k5ts2_log_newline 2006.257.09:51:23.39/k5log//k5ts3_log_newline 2006.257.09:51:24.09/k5log//k5ts4_log_newline 2006.257.09:51:24.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:51:24.11:setupk4=1 2006.257.09:51:24.11$setupk4/echo=on 2006.257.09:51:24.11$setupk4/pcalon 2006.257.09:51:24.11$pcalon/"no phase cal control is implemented here 2006.257.09:51:24.11$setupk4/"tpicd=stop 2006.257.09:51:24.11$setupk4/"rec=synch_on 2006.257.09:51:24.11$setupk4/"rec_mode=128 2006.257.09:51:24.11$setupk4/!* 2006.257.09:51:24.11$setupk4/recpk4 2006.257.09:51:24.11$recpk4/recpatch= 2006.257.09:51:24.12$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:51:24.12$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:51:24.12$setupk4/vck44 2006.257.09:51:24.12$vck44/valo=1,524.99 2006.257.09:51:24.12#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.09:51:24.12#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.09:51:24.12#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:24.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:24.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:24.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:24.12#ibcon#enter wrdev, iclass 19, count 0 2006.257.09:51:24.12#ibcon#first serial, iclass 19, count 0 2006.257.09:51:24.12#ibcon#enter sib2, iclass 19, count 0 2006.257.09:51:24.12#ibcon#flushed, iclass 19, count 0 2006.257.09:51:24.12#ibcon#about to write, iclass 19, count 0 2006.257.09:51:24.12#ibcon#wrote, iclass 19, count 0 2006.257.09:51:24.12#ibcon#about to read 3, iclass 19, count 0 2006.257.09:51:24.14#ibcon#read 3, iclass 19, count 0 2006.257.09:51:24.14#ibcon#about to read 4, iclass 19, count 0 2006.257.09:51:24.14#ibcon#read 4, iclass 19, count 0 2006.257.09:51:24.14#ibcon#about to read 5, iclass 19, count 0 2006.257.09:51:24.14#ibcon#read 5, iclass 19, count 0 2006.257.09:51:24.14#ibcon#about to read 6, iclass 19, count 0 2006.257.09:51:24.14#ibcon#read 6, iclass 19, count 0 2006.257.09:51:24.14#ibcon#end of sib2, iclass 19, count 0 2006.257.09:51:24.14#ibcon#*mode == 0, iclass 19, count 0 2006.257.09:51:24.14#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.09:51:24.14#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:51:24.14#ibcon#*before write, iclass 19, count 0 2006.257.09:51:24.14#ibcon#enter sib2, iclass 19, count 0 2006.257.09:51:24.14#ibcon#flushed, iclass 19, count 0 2006.257.09:51:24.14#ibcon#about to write, iclass 19, count 0 2006.257.09:51:24.14#ibcon#wrote, iclass 19, count 0 2006.257.09:51:24.14#ibcon#about to read 3, iclass 19, count 0 2006.257.09:51:24.19#ibcon#read 3, iclass 19, count 0 2006.257.09:51:24.19#ibcon#about to read 4, iclass 19, count 0 2006.257.09:51:24.19#ibcon#read 4, iclass 19, count 0 2006.257.09:51:24.19#ibcon#about to read 5, iclass 19, count 0 2006.257.09:51:24.19#ibcon#read 5, iclass 19, count 0 2006.257.09:51:24.19#ibcon#about to read 6, iclass 19, count 0 2006.257.09:51:24.19#ibcon#read 6, iclass 19, count 0 2006.257.09:51:24.19#ibcon#end of sib2, iclass 19, count 0 2006.257.09:51:24.19#ibcon#*after write, iclass 19, count 0 2006.257.09:51:24.19#ibcon#*before return 0, iclass 19, count 0 2006.257.09:51:24.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:24.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:24.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.09:51:24.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.09:51:24.19$vck44/va=1,8 2006.257.09:51:24.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.09:51:24.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.09:51:24.19#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:24.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:24.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:24.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:24.19#ibcon#enter wrdev, iclass 21, count 2 2006.257.09:51:24.19#ibcon#first serial, iclass 21, count 2 2006.257.09:51:24.19#ibcon#enter sib2, iclass 21, count 2 2006.257.09:51:24.19#ibcon#flushed, iclass 21, count 2 2006.257.09:51:24.19#ibcon#about to write, iclass 21, count 2 2006.257.09:51:24.19#ibcon#wrote, iclass 21, count 2 2006.257.09:51:24.19#ibcon#about to read 3, iclass 21, count 2 2006.257.09:51:24.21#ibcon#read 3, iclass 21, count 2 2006.257.09:51:24.21#ibcon#about to read 4, iclass 21, count 2 2006.257.09:51:24.21#ibcon#read 4, iclass 21, count 2 2006.257.09:51:24.21#ibcon#about to read 5, iclass 21, count 2 2006.257.09:51:24.21#ibcon#read 5, iclass 21, count 2 2006.257.09:51:24.21#ibcon#about to read 6, iclass 21, count 2 2006.257.09:51:24.21#ibcon#read 6, iclass 21, count 2 2006.257.09:51:24.21#ibcon#end of sib2, iclass 21, count 2 2006.257.09:51:24.21#ibcon#*mode == 0, iclass 21, count 2 2006.257.09:51:24.21#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.09:51:24.21#ibcon#[25=AT01-08\r\n] 2006.257.09:51:24.21#ibcon#*before write, iclass 21, count 2 2006.257.09:51:24.21#ibcon#enter sib2, iclass 21, count 2 2006.257.09:51:24.21#ibcon#flushed, iclass 21, count 2 2006.257.09:51:24.21#ibcon#about to write, iclass 21, count 2 2006.257.09:51:24.21#ibcon#wrote, iclass 21, count 2 2006.257.09:51:24.21#ibcon#about to read 3, iclass 21, count 2 2006.257.09:51:24.24#ibcon#read 3, iclass 21, count 2 2006.257.09:51:24.24#ibcon#about to read 4, iclass 21, count 2 2006.257.09:51:24.24#ibcon#read 4, iclass 21, count 2 2006.257.09:51:24.24#ibcon#about to read 5, iclass 21, count 2 2006.257.09:51:24.24#ibcon#read 5, iclass 21, count 2 2006.257.09:51:24.24#ibcon#about to read 6, iclass 21, count 2 2006.257.09:51:24.24#ibcon#read 6, iclass 21, count 2 2006.257.09:51:24.24#ibcon#end of sib2, iclass 21, count 2 2006.257.09:51:24.24#ibcon#*after write, iclass 21, count 2 2006.257.09:51:24.24#ibcon#*before return 0, iclass 21, count 2 2006.257.09:51:24.24#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:24.24#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:24.24#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.09:51:24.24#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:24.24#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:24.36#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:24.36#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:24.36#ibcon#enter wrdev, iclass 21, count 0 2006.257.09:51:24.36#ibcon#first serial, iclass 21, count 0 2006.257.09:51:24.36#ibcon#enter sib2, iclass 21, count 0 2006.257.09:51:24.36#ibcon#flushed, iclass 21, count 0 2006.257.09:51:24.36#ibcon#about to write, iclass 21, count 0 2006.257.09:51:24.36#ibcon#wrote, iclass 21, count 0 2006.257.09:51:24.36#ibcon#about to read 3, iclass 21, count 0 2006.257.09:51:24.38#ibcon#read 3, iclass 21, count 0 2006.257.09:51:24.38#ibcon#about to read 4, iclass 21, count 0 2006.257.09:51:24.38#ibcon#read 4, iclass 21, count 0 2006.257.09:51:24.38#ibcon#about to read 5, iclass 21, count 0 2006.257.09:51:24.38#ibcon#read 5, iclass 21, count 0 2006.257.09:51:24.38#ibcon#about to read 6, iclass 21, count 0 2006.257.09:51:24.38#ibcon#read 6, iclass 21, count 0 2006.257.09:51:24.38#ibcon#end of sib2, iclass 21, count 0 2006.257.09:51:24.38#ibcon#*mode == 0, iclass 21, count 0 2006.257.09:51:24.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.09:51:24.38#ibcon#[25=USB\r\n] 2006.257.09:51:24.38#ibcon#*before write, iclass 21, count 0 2006.257.09:51:24.38#ibcon#enter sib2, iclass 21, count 0 2006.257.09:51:24.38#ibcon#flushed, iclass 21, count 0 2006.257.09:51:24.38#ibcon#about to write, iclass 21, count 0 2006.257.09:51:24.38#ibcon#wrote, iclass 21, count 0 2006.257.09:51:24.38#ibcon#about to read 3, iclass 21, count 0 2006.257.09:51:24.41#ibcon#read 3, iclass 21, count 0 2006.257.09:51:24.41#ibcon#about to read 4, iclass 21, count 0 2006.257.09:51:24.41#ibcon#read 4, iclass 21, count 0 2006.257.09:51:24.41#ibcon#about to read 5, iclass 21, count 0 2006.257.09:51:24.41#ibcon#read 5, iclass 21, count 0 2006.257.09:51:24.41#ibcon#about to read 6, iclass 21, count 0 2006.257.09:51:24.41#ibcon#read 6, iclass 21, count 0 2006.257.09:51:24.41#ibcon#end of sib2, iclass 21, count 0 2006.257.09:51:24.41#ibcon#*after write, iclass 21, count 0 2006.257.09:51:24.41#ibcon#*before return 0, iclass 21, count 0 2006.257.09:51:24.41#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:24.41#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:24.41#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.09:51:24.41#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.09:51:24.41$vck44/valo=2,534.99 2006.257.09:51:24.41#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.09:51:24.41#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.09:51:24.41#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:24.41#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:24.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:24.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:24.41#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:51:24.41#ibcon#first serial, iclass 23, count 0 2006.257.09:51:24.41#ibcon#enter sib2, iclass 23, count 0 2006.257.09:51:24.41#ibcon#flushed, iclass 23, count 0 2006.257.09:51:24.41#ibcon#about to write, iclass 23, count 0 2006.257.09:51:24.41#ibcon#wrote, iclass 23, count 0 2006.257.09:51:24.41#ibcon#about to read 3, iclass 23, count 0 2006.257.09:51:24.43#ibcon#read 3, iclass 23, count 0 2006.257.09:51:24.43#ibcon#about to read 4, iclass 23, count 0 2006.257.09:51:24.43#ibcon#read 4, iclass 23, count 0 2006.257.09:51:24.43#ibcon#about to read 5, iclass 23, count 0 2006.257.09:51:24.43#ibcon#read 5, iclass 23, count 0 2006.257.09:51:24.43#ibcon#about to read 6, iclass 23, count 0 2006.257.09:51:24.43#ibcon#read 6, iclass 23, count 0 2006.257.09:51:24.43#ibcon#end of sib2, iclass 23, count 0 2006.257.09:51:24.43#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:51:24.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:51:24.43#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:51:24.43#ibcon#*before write, iclass 23, count 0 2006.257.09:51:24.43#ibcon#enter sib2, iclass 23, count 0 2006.257.09:51:24.43#ibcon#flushed, iclass 23, count 0 2006.257.09:51:24.43#ibcon#about to write, iclass 23, count 0 2006.257.09:51:24.43#ibcon#wrote, iclass 23, count 0 2006.257.09:51:24.43#ibcon#about to read 3, iclass 23, count 0 2006.257.09:51:24.47#ibcon#read 3, iclass 23, count 0 2006.257.09:51:24.47#ibcon#about to read 4, iclass 23, count 0 2006.257.09:51:24.47#ibcon#read 4, iclass 23, count 0 2006.257.09:51:24.47#ibcon#about to read 5, iclass 23, count 0 2006.257.09:51:24.47#ibcon#read 5, iclass 23, count 0 2006.257.09:51:24.47#ibcon#about to read 6, iclass 23, count 0 2006.257.09:51:24.47#ibcon#read 6, iclass 23, count 0 2006.257.09:51:24.47#ibcon#end of sib2, iclass 23, count 0 2006.257.09:51:24.47#ibcon#*after write, iclass 23, count 0 2006.257.09:51:24.47#ibcon#*before return 0, iclass 23, count 0 2006.257.09:51:24.47#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:24.47#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:24.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:51:24.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:51:24.47$vck44/va=2,7 2006.257.09:51:24.47#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.09:51:24.47#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.09:51:24.47#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:24.47#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:24.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:24.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:24.53#ibcon#enter wrdev, iclass 25, count 2 2006.257.09:51:24.53#ibcon#first serial, iclass 25, count 2 2006.257.09:51:24.53#ibcon#enter sib2, iclass 25, count 2 2006.257.09:51:24.53#ibcon#flushed, iclass 25, count 2 2006.257.09:51:24.53#ibcon#about to write, iclass 25, count 2 2006.257.09:51:24.53#ibcon#wrote, iclass 25, count 2 2006.257.09:51:24.53#ibcon#about to read 3, iclass 25, count 2 2006.257.09:51:24.55#ibcon#read 3, iclass 25, count 2 2006.257.09:51:24.55#ibcon#about to read 4, iclass 25, count 2 2006.257.09:51:24.55#ibcon#read 4, iclass 25, count 2 2006.257.09:51:24.55#ibcon#about to read 5, iclass 25, count 2 2006.257.09:51:24.55#ibcon#read 5, iclass 25, count 2 2006.257.09:51:24.55#ibcon#about to read 6, iclass 25, count 2 2006.257.09:51:24.55#ibcon#read 6, iclass 25, count 2 2006.257.09:51:24.55#ibcon#end of sib2, iclass 25, count 2 2006.257.09:51:24.55#ibcon#*mode == 0, iclass 25, count 2 2006.257.09:51:24.55#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.09:51:24.55#ibcon#[25=AT02-07\r\n] 2006.257.09:51:24.55#ibcon#*before write, iclass 25, count 2 2006.257.09:51:24.55#ibcon#enter sib2, iclass 25, count 2 2006.257.09:51:24.55#ibcon#flushed, iclass 25, count 2 2006.257.09:51:24.55#ibcon#about to write, iclass 25, count 2 2006.257.09:51:24.55#ibcon#wrote, iclass 25, count 2 2006.257.09:51:24.55#ibcon#about to read 3, iclass 25, count 2 2006.257.09:51:24.58#ibcon#read 3, iclass 25, count 2 2006.257.09:51:24.58#ibcon#about to read 4, iclass 25, count 2 2006.257.09:51:24.58#ibcon#read 4, iclass 25, count 2 2006.257.09:51:24.58#ibcon#about to read 5, iclass 25, count 2 2006.257.09:51:24.58#ibcon#read 5, iclass 25, count 2 2006.257.09:51:24.58#ibcon#about to read 6, iclass 25, count 2 2006.257.09:51:24.58#ibcon#read 6, iclass 25, count 2 2006.257.09:51:24.58#ibcon#end of sib2, iclass 25, count 2 2006.257.09:51:24.58#ibcon#*after write, iclass 25, count 2 2006.257.09:51:24.58#ibcon#*before return 0, iclass 25, count 2 2006.257.09:51:24.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:24.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:24.58#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.09:51:24.58#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:24.58#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:24.70#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:24.70#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:24.70#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:51:24.70#ibcon#first serial, iclass 25, count 0 2006.257.09:51:24.70#ibcon#enter sib2, iclass 25, count 0 2006.257.09:51:24.70#ibcon#flushed, iclass 25, count 0 2006.257.09:51:24.70#ibcon#about to write, iclass 25, count 0 2006.257.09:51:24.70#ibcon#wrote, iclass 25, count 0 2006.257.09:51:24.70#ibcon#about to read 3, iclass 25, count 0 2006.257.09:51:24.72#ibcon#read 3, iclass 25, count 0 2006.257.09:51:24.72#ibcon#about to read 4, iclass 25, count 0 2006.257.09:51:24.72#ibcon#read 4, iclass 25, count 0 2006.257.09:51:24.72#ibcon#about to read 5, iclass 25, count 0 2006.257.09:51:24.72#ibcon#read 5, iclass 25, count 0 2006.257.09:51:24.72#ibcon#about to read 6, iclass 25, count 0 2006.257.09:51:24.72#ibcon#read 6, iclass 25, count 0 2006.257.09:51:24.72#ibcon#end of sib2, iclass 25, count 0 2006.257.09:51:24.72#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:51:24.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:51:24.72#ibcon#[25=USB\r\n] 2006.257.09:51:24.72#ibcon#*before write, iclass 25, count 0 2006.257.09:51:24.72#ibcon#enter sib2, iclass 25, count 0 2006.257.09:51:24.72#ibcon#flushed, iclass 25, count 0 2006.257.09:51:24.72#ibcon#about to write, iclass 25, count 0 2006.257.09:51:24.72#ibcon#wrote, iclass 25, count 0 2006.257.09:51:24.72#ibcon#about to read 3, iclass 25, count 0 2006.257.09:51:24.75#ibcon#read 3, iclass 25, count 0 2006.257.09:51:24.75#ibcon#about to read 4, iclass 25, count 0 2006.257.09:51:24.75#ibcon#read 4, iclass 25, count 0 2006.257.09:51:24.75#ibcon#about to read 5, iclass 25, count 0 2006.257.09:51:24.75#ibcon#read 5, iclass 25, count 0 2006.257.09:51:24.75#ibcon#about to read 6, iclass 25, count 0 2006.257.09:51:24.75#ibcon#read 6, iclass 25, count 0 2006.257.09:51:24.75#ibcon#end of sib2, iclass 25, count 0 2006.257.09:51:24.75#ibcon#*after write, iclass 25, count 0 2006.257.09:51:24.75#ibcon#*before return 0, iclass 25, count 0 2006.257.09:51:24.75#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:24.75#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:24.75#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:51:24.75#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:51:24.75$vck44/valo=3,564.99 2006.257.09:51:24.75#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.09:51:24.75#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.09:51:24.75#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:24.75#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:24.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:24.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:24.75#ibcon#enter wrdev, iclass 27, count 0 2006.257.09:51:24.75#ibcon#first serial, iclass 27, count 0 2006.257.09:51:24.75#ibcon#enter sib2, iclass 27, count 0 2006.257.09:51:24.75#ibcon#flushed, iclass 27, count 0 2006.257.09:51:24.75#ibcon#about to write, iclass 27, count 0 2006.257.09:51:24.75#ibcon#wrote, iclass 27, count 0 2006.257.09:51:24.75#ibcon#about to read 3, iclass 27, count 0 2006.257.09:51:24.77#ibcon#read 3, iclass 27, count 0 2006.257.09:51:24.77#ibcon#about to read 4, iclass 27, count 0 2006.257.09:51:24.77#ibcon#read 4, iclass 27, count 0 2006.257.09:51:24.77#ibcon#about to read 5, iclass 27, count 0 2006.257.09:51:24.77#ibcon#read 5, iclass 27, count 0 2006.257.09:51:24.77#ibcon#about to read 6, iclass 27, count 0 2006.257.09:51:24.77#ibcon#read 6, iclass 27, count 0 2006.257.09:51:24.77#ibcon#end of sib2, iclass 27, count 0 2006.257.09:51:24.77#ibcon#*mode == 0, iclass 27, count 0 2006.257.09:51:24.77#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.09:51:24.77#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:51:24.77#ibcon#*before write, iclass 27, count 0 2006.257.09:51:24.77#ibcon#enter sib2, iclass 27, count 0 2006.257.09:51:24.77#ibcon#flushed, iclass 27, count 0 2006.257.09:51:24.77#ibcon#about to write, iclass 27, count 0 2006.257.09:51:24.77#ibcon#wrote, iclass 27, count 0 2006.257.09:51:24.77#ibcon#about to read 3, iclass 27, count 0 2006.257.09:51:24.81#ibcon#read 3, iclass 27, count 0 2006.257.09:51:24.81#ibcon#about to read 4, iclass 27, count 0 2006.257.09:51:24.81#ibcon#read 4, iclass 27, count 0 2006.257.09:51:24.81#ibcon#about to read 5, iclass 27, count 0 2006.257.09:51:24.81#ibcon#read 5, iclass 27, count 0 2006.257.09:51:24.81#ibcon#about to read 6, iclass 27, count 0 2006.257.09:51:24.81#ibcon#read 6, iclass 27, count 0 2006.257.09:51:24.81#ibcon#end of sib2, iclass 27, count 0 2006.257.09:51:24.81#ibcon#*after write, iclass 27, count 0 2006.257.09:51:24.81#ibcon#*before return 0, iclass 27, count 0 2006.257.09:51:24.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:24.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:24.81#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.09:51:24.81#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.09:51:24.81$vck44/va=3,8 2006.257.09:51:24.81#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.09:51:24.81#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.09:51:24.81#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:24.81#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:24.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:24.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:24.87#ibcon#enter wrdev, iclass 29, count 2 2006.257.09:51:24.87#ibcon#first serial, iclass 29, count 2 2006.257.09:51:24.87#ibcon#enter sib2, iclass 29, count 2 2006.257.09:51:24.87#ibcon#flushed, iclass 29, count 2 2006.257.09:51:24.87#ibcon#about to write, iclass 29, count 2 2006.257.09:51:24.87#ibcon#wrote, iclass 29, count 2 2006.257.09:51:24.87#ibcon#about to read 3, iclass 29, count 2 2006.257.09:51:24.89#ibcon#read 3, iclass 29, count 2 2006.257.09:51:24.89#ibcon#about to read 4, iclass 29, count 2 2006.257.09:51:24.89#ibcon#read 4, iclass 29, count 2 2006.257.09:51:24.89#ibcon#about to read 5, iclass 29, count 2 2006.257.09:51:24.89#ibcon#read 5, iclass 29, count 2 2006.257.09:51:24.89#ibcon#about to read 6, iclass 29, count 2 2006.257.09:51:24.89#ibcon#read 6, iclass 29, count 2 2006.257.09:51:24.89#ibcon#end of sib2, iclass 29, count 2 2006.257.09:51:24.89#ibcon#*mode == 0, iclass 29, count 2 2006.257.09:51:24.89#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.09:51:24.89#ibcon#[25=AT03-08\r\n] 2006.257.09:51:24.89#ibcon#*before write, iclass 29, count 2 2006.257.09:51:24.89#ibcon#enter sib2, iclass 29, count 2 2006.257.09:51:24.89#ibcon#flushed, iclass 29, count 2 2006.257.09:51:24.89#ibcon#about to write, iclass 29, count 2 2006.257.09:51:24.89#ibcon#wrote, iclass 29, count 2 2006.257.09:51:24.89#ibcon#about to read 3, iclass 29, count 2 2006.257.09:51:24.92#ibcon#read 3, iclass 29, count 2 2006.257.09:51:24.92#ibcon#about to read 4, iclass 29, count 2 2006.257.09:51:24.92#ibcon#read 4, iclass 29, count 2 2006.257.09:51:24.92#ibcon#about to read 5, iclass 29, count 2 2006.257.09:51:24.92#ibcon#read 5, iclass 29, count 2 2006.257.09:51:24.92#ibcon#about to read 6, iclass 29, count 2 2006.257.09:51:24.92#ibcon#read 6, iclass 29, count 2 2006.257.09:51:24.92#ibcon#end of sib2, iclass 29, count 2 2006.257.09:51:24.92#ibcon#*after write, iclass 29, count 2 2006.257.09:51:24.92#ibcon#*before return 0, iclass 29, count 2 2006.257.09:51:24.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:24.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:24.92#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.09:51:24.92#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:24.92#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:25.04#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:25.04#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:25.04#ibcon#enter wrdev, iclass 29, count 0 2006.257.09:51:25.04#ibcon#first serial, iclass 29, count 0 2006.257.09:51:25.04#ibcon#enter sib2, iclass 29, count 0 2006.257.09:51:25.04#ibcon#flushed, iclass 29, count 0 2006.257.09:51:25.04#ibcon#about to write, iclass 29, count 0 2006.257.09:51:25.04#ibcon#wrote, iclass 29, count 0 2006.257.09:51:25.04#ibcon#about to read 3, iclass 29, count 0 2006.257.09:51:25.06#ibcon#read 3, iclass 29, count 0 2006.257.09:51:25.06#ibcon#about to read 4, iclass 29, count 0 2006.257.09:51:25.06#ibcon#read 4, iclass 29, count 0 2006.257.09:51:25.06#ibcon#about to read 5, iclass 29, count 0 2006.257.09:51:25.06#ibcon#read 5, iclass 29, count 0 2006.257.09:51:25.06#ibcon#about to read 6, iclass 29, count 0 2006.257.09:51:25.06#ibcon#read 6, iclass 29, count 0 2006.257.09:51:25.06#ibcon#end of sib2, iclass 29, count 0 2006.257.09:51:25.06#ibcon#*mode == 0, iclass 29, count 0 2006.257.09:51:25.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.09:51:25.06#ibcon#[25=USB\r\n] 2006.257.09:51:25.06#ibcon#*before write, iclass 29, count 0 2006.257.09:51:25.06#ibcon#enter sib2, iclass 29, count 0 2006.257.09:51:25.06#ibcon#flushed, iclass 29, count 0 2006.257.09:51:25.06#ibcon#about to write, iclass 29, count 0 2006.257.09:51:25.06#ibcon#wrote, iclass 29, count 0 2006.257.09:51:25.06#ibcon#about to read 3, iclass 29, count 0 2006.257.09:51:25.09#ibcon#read 3, iclass 29, count 0 2006.257.09:51:25.09#ibcon#about to read 4, iclass 29, count 0 2006.257.09:51:25.09#ibcon#read 4, iclass 29, count 0 2006.257.09:51:25.09#ibcon#about to read 5, iclass 29, count 0 2006.257.09:51:25.09#ibcon#read 5, iclass 29, count 0 2006.257.09:51:25.09#ibcon#about to read 6, iclass 29, count 0 2006.257.09:51:25.09#ibcon#read 6, iclass 29, count 0 2006.257.09:51:25.09#ibcon#end of sib2, iclass 29, count 0 2006.257.09:51:25.09#ibcon#*after write, iclass 29, count 0 2006.257.09:51:25.09#ibcon#*before return 0, iclass 29, count 0 2006.257.09:51:25.09#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:25.09#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:25.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.09:51:25.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.09:51:25.09$vck44/valo=4,624.99 2006.257.09:51:25.09#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.09:51:25.09#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.09:51:25.09#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:25.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:25.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:25.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:25.09#ibcon#enter wrdev, iclass 31, count 0 2006.257.09:51:25.09#ibcon#first serial, iclass 31, count 0 2006.257.09:51:25.09#ibcon#enter sib2, iclass 31, count 0 2006.257.09:51:25.09#ibcon#flushed, iclass 31, count 0 2006.257.09:51:25.09#ibcon#about to write, iclass 31, count 0 2006.257.09:51:25.09#ibcon#wrote, iclass 31, count 0 2006.257.09:51:25.09#ibcon#about to read 3, iclass 31, count 0 2006.257.09:51:25.11#ibcon#read 3, iclass 31, count 0 2006.257.09:51:25.11#ibcon#about to read 4, iclass 31, count 0 2006.257.09:51:25.11#ibcon#read 4, iclass 31, count 0 2006.257.09:51:25.11#ibcon#about to read 5, iclass 31, count 0 2006.257.09:51:25.11#ibcon#read 5, iclass 31, count 0 2006.257.09:51:25.11#ibcon#about to read 6, iclass 31, count 0 2006.257.09:51:25.11#ibcon#read 6, iclass 31, count 0 2006.257.09:51:25.11#ibcon#end of sib2, iclass 31, count 0 2006.257.09:51:25.11#ibcon#*mode == 0, iclass 31, count 0 2006.257.09:51:25.11#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.09:51:25.11#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:51:25.11#ibcon#*before write, iclass 31, count 0 2006.257.09:51:25.11#ibcon#enter sib2, iclass 31, count 0 2006.257.09:51:25.11#ibcon#flushed, iclass 31, count 0 2006.257.09:51:25.11#ibcon#about to write, iclass 31, count 0 2006.257.09:51:25.11#ibcon#wrote, iclass 31, count 0 2006.257.09:51:25.11#ibcon#about to read 3, iclass 31, count 0 2006.257.09:51:25.15#ibcon#read 3, iclass 31, count 0 2006.257.09:51:25.15#ibcon#about to read 4, iclass 31, count 0 2006.257.09:51:25.15#ibcon#read 4, iclass 31, count 0 2006.257.09:51:25.15#ibcon#about to read 5, iclass 31, count 0 2006.257.09:51:25.15#ibcon#read 5, iclass 31, count 0 2006.257.09:51:25.15#ibcon#about to read 6, iclass 31, count 0 2006.257.09:51:25.15#ibcon#read 6, iclass 31, count 0 2006.257.09:51:25.15#ibcon#end of sib2, iclass 31, count 0 2006.257.09:51:25.15#ibcon#*after write, iclass 31, count 0 2006.257.09:51:25.15#ibcon#*before return 0, iclass 31, count 0 2006.257.09:51:25.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:25.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:25.15#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.09:51:25.15#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.09:51:25.15$vck44/va=4,7 2006.257.09:51:25.15#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.09:51:25.15#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.09:51:25.15#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:25.15#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:25.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:25.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:25.21#ibcon#enter wrdev, iclass 33, count 2 2006.257.09:51:25.21#ibcon#first serial, iclass 33, count 2 2006.257.09:51:25.21#ibcon#enter sib2, iclass 33, count 2 2006.257.09:51:25.21#ibcon#flushed, iclass 33, count 2 2006.257.09:51:25.21#ibcon#about to write, iclass 33, count 2 2006.257.09:51:25.21#ibcon#wrote, iclass 33, count 2 2006.257.09:51:25.21#ibcon#about to read 3, iclass 33, count 2 2006.257.09:51:25.23#ibcon#read 3, iclass 33, count 2 2006.257.09:51:25.23#ibcon#about to read 4, iclass 33, count 2 2006.257.09:51:25.23#ibcon#read 4, iclass 33, count 2 2006.257.09:51:25.23#ibcon#about to read 5, iclass 33, count 2 2006.257.09:51:25.23#ibcon#read 5, iclass 33, count 2 2006.257.09:51:25.23#ibcon#about to read 6, iclass 33, count 2 2006.257.09:51:25.23#ibcon#read 6, iclass 33, count 2 2006.257.09:51:25.23#ibcon#end of sib2, iclass 33, count 2 2006.257.09:51:25.23#ibcon#*mode == 0, iclass 33, count 2 2006.257.09:51:25.23#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.09:51:25.23#ibcon#[25=AT04-07\r\n] 2006.257.09:51:25.23#ibcon#*before write, iclass 33, count 2 2006.257.09:51:25.23#ibcon#enter sib2, iclass 33, count 2 2006.257.09:51:25.23#ibcon#flushed, iclass 33, count 2 2006.257.09:51:25.23#ibcon#about to write, iclass 33, count 2 2006.257.09:51:25.23#ibcon#wrote, iclass 33, count 2 2006.257.09:51:25.23#ibcon#about to read 3, iclass 33, count 2 2006.257.09:51:25.26#ibcon#read 3, iclass 33, count 2 2006.257.09:51:25.26#ibcon#about to read 4, iclass 33, count 2 2006.257.09:51:25.26#ibcon#read 4, iclass 33, count 2 2006.257.09:51:25.26#ibcon#about to read 5, iclass 33, count 2 2006.257.09:51:25.26#ibcon#read 5, iclass 33, count 2 2006.257.09:51:25.26#ibcon#about to read 6, iclass 33, count 2 2006.257.09:51:25.26#ibcon#read 6, iclass 33, count 2 2006.257.09:51:25.26#ibcon#end of sib2, iclass 33, count 2 2006.257.09:51:25.26#ibcon#*after write, iclass 33, count 2 2006.257.09:51:25.30#ibcon#*before return 0, iclass 33, count 2 2006.257.09:51:25.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:25.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:25.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.09:51:25.30#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:25.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:25.41#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:25.41#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:25.41#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:51:25.41#ibcon#first serial, iclass 33, count 0 2006.257.09:51:25.41#ibcon#enter sib2, iclass 33, count 0 2006.257.09:51:25.41#ibcon#flushed, iclass 33, count 0 2006.257.09:51:25.41#ibcon#about to write, iclass 33, count 0 2006.257.09:51:25.41#ibcon#wrote, iclass 33, count 0 2006.257.09:51:25.41#ibcon#about to read 3, iclass 33, count 0 2006.257.09:51:25.43#ibcon#read 3, iclass 33, count 0 2006.257.09:51:25.43#ibcon#about to read 4, iclass 33, count 0 2006.257.09:51:25.43#ibcon#read 4, iclass 33, count 0 2006.257.09:51:25.43#ibcon#about to read 5, iclass 33, count 0 2006.257.09:51:25.43#ibcon#read 5, iclass 33, count 0 2006.257.09:51:25.43#ibcon#about to read 6, iclass 33, count 0 2006.257.09:51:25.43#ibcon#read 6, iclass 33, count 0 2006.257.09:51:25.43#ibcon#end of sib2, iclass 33, count 0 2006.257.09:51:25.43#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:51:25.43#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:51:25.43#ibcon#[25=USB\r\n] 2006.257.09:51:25.43#ibcon#*before write, iclass 33, count 0 2006.257.09:51:25.43#ibcon#enter sib2, iclass 33, count 0 2006.257.09:51:25.43#ibcon#flushed, iclass 33, count 0 2006.257.09:51:25.43#ibcon#about to write, iclass 33, count 0 2006.257.09:51:25.43#ibcon#wrote, iclass 33, count 0 2006.257.09:51:25.43#ibcon#about to read 3, iclass 33, count 0 2006.257.09:51:25.46#ibcon#read 3, iclass 33, count 0 2006.257.09:51:25.46#ibcon#about to read 4, iclass 33, count 0 2006.257.09:51:25.46#ibcon#read 4, iclass 33, count 0 2006.257.09:51:25.46#ibcon#about to read 5, iclass 33, count 0 2006.257.09:51:25.46#ibcon#read 5, iclass 33, count 0 2006.257.09:51:25.46#ibcon#about to read 6, iclass 33, count 0 2006.257.09:51:25.46#ibcon#read 6, iclass 33, count 0 2006.257.09:51:25.46#ibcon#end of sib2, iclass 33, count 0 2006.257.09:51:25.46#ibcon#*after write, iclass 33, count 0 2006.257.09:51:25.46#ibcon#*before return 0, iclass 33, count 0 2006.257.09:51:25.46#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:25.46#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:25.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:51:25.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:51:25.46$vck44/valo=5,734.99 2006.257.09:51:25.46#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.09:51:25.46#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.09:51:25.46#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:25.46#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:25.46#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:25.46#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:25.46#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:51:25.46#ibcon#first serial, iclass 35, count 0 2006.257.09:51:25.46#ibcon#enter sib2, iclass 35, count 0 2006.257.09:51:25.46#ibcon#flushed, iclass 35, count 0 2006.257.09:51:25.46#ibcon#about to write, iclass 35, count 0 2006.257.09:51:25.46#ibcon#wrote, iclass 35, count 0 2006.257.09:51:25.46#ibcon#about to read 3, iclass 35, count 0 2006.257.09:51:25.48#ibcon#read 3, iclass 35, count 0 2006.257.09:51:25.48#ibcon#about to read 4, iclass 35, count 0 2006.257.09:51:25.48#ibcon#read 4, iclass 35, count 0 2006.257.09:51:25.48#ibcon#about to read 5, iclass 35, count 0 2006.257.09:51:25.48#ibcon#read 5, iclass 35, count 0 2006.257.09:51:25.48#ibcon#about to read 6, iclass 35, count 0 2006.257.09:51:25.48#ibcon#read 6, iclass 35, count 0 2006.257.09:51:25.48#ibcon#end of sib2, iclass 35, count 0 2006.257.09:51:25.48#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:51:25.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:51:25.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:51:25.48#ibcon#*before write, iclass 35, count 0 2006.257.09:51:25.48#ibcon#enter sib2, iclass 35, count 0 2006.257.09:51:25.48#ibcon#flushed, iclass 35, count 0 2006.257.09:51:25.48#ibcon#about to write, iclass 35, count 0 2006.257.09:51:25.48#ibcon#wrote, iclass 35, count 0 2006.257.09:51:25.48#ibcon#about to read 3, iclass 35, count 0 2006.257.09:51:25.52#ibcon#read 3, iclass 35, count 0 2006.257.09:51:25.52#ibcon#about to read 4, iclass 35, count 0 2006.257.09:51:25.52#ibcon#read 4, iclass 35, count 0 2006.257.09:51:25.52#ibcon#about to read 5, iclass 35, count 0 2006.257.09:51:25.52#ibcon#read 5, iclass 35, count 0 2006.257.09:51:25.52#ibcon#about to read 6, iclass 35, count 0 2006.257.09:51:25.52#ibcon#read 6, iclass 35, count 0 2006.257.09:51:25.52#ibcon#end of sib2, iclass 35, count 0 2006.257.09:51:25.52#ibcon#*after write, iclass 35, count 0 2006.257.09:51:25.52#ibcon#*before return 0, iclass 35, count 0 2006.257.09:51:25.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:25.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:25.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:51:25.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:51:25.52$vck44/va=5,4 2006.257.09:51:25.52#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.09:51:25.52#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.09:51:25.52#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:25.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:25.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:25.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:25.58#ibcon#enter wrdev, iclass 37, count 2 2006.257.09:51:25.58#ibcon#first serial, iclass 37, count 2 2006.257.09:51:25.58#ibcon#enter sib2, iclass 37, count 2 2006.257.09:51:25.58#ibcon#flushed, iclass 37, count 2 2006.257.09:51:25.58#ibcon#about to write, iclass 37, count 2 2006.257.09:51:25.58#ibcon#wrote, iclass 37, count 2 2006.257.09:51:25.58#ibcon#about to read 3, iclass 37, count 2 2006.257.09:51:25.60#ibcon#read 3, iclass 37, count 2 2006.257.09:51:25.60#ibcon#about to read 4, iclass 37, count 2 2006.257.09:51:25.60#ibcon#read 4, iclass 37, count 2 2006.257.09:51:25.60#ibcon#about to read 5, iclass 37, count 2 2006.257.09:51:25.60#ibcon#read 5, iclass 37, count 2 2006.257.09:51:25.60#ibcon#about to read 6, iclass 37, count 2 2006.257.09:51:25.60#ibcon#read 6, iclass 37, count 2 2006.257.09:51:25.60#ibcon#end of sib2, iclass 37, count 2 2006.257.09:51:25.60#ibcon#*mode == 0, iclass 37, count 2 2006.257.09:51:25.60#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.09:51:25.60#ibcon#[25=AT05-04\r\n] 2006.257.09:51:25.60#ibcon#*before write, iclass 37, count 2 2006.257.09:51:25.60#ibcon#enter sib2, iclass 37, count 2 2006.257.09:51:25.60#ibcon#flushed, iclass 37, count 2 2006.257.09:51:25.60#ibcon#about to write, iclass 37, count 2 2006.257.09:51:25.60#ibcon#wrote, iclass 37, count 2 2006.257.09:51:25.60#ibcon#about to read 3, iclass 37, count 2 2006.257.09:51:25.63#ibcon#read 3, iclass 37, count 2 2006.257.09:51:25.63#ibcon#about to read 4, iclass 37, count 2 2006.257.09:51:25.63#ibcon#read 4, iclass 37, count 2 2006.257.09:51:25.63#ibcon#about to read 5, iclass 37, count 2 2006.257.09:51:25.63#ibcon#read 5, iclass 37, count 2 2006.257.09:51:25.63#ibcon#about to read 6, iclass 37, count 2 2006.257.09:51:25.63#ibcon#read 6, iclass 37, count 2 2006.257.09:51:25.63#ibcon#end of sib2, iclass 37, count 2 2006.257.09:51:25.63#ibcon#*after write, iclass 37, count 2 2006.257.09:51:25.63#ibcon#*before return 0, iclass 37, count 2 2006.257.09:51:25.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:25.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:25.63#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.09:51:25.63#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:25.63#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:25.75#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:25.75#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:25.75#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:51:25.75#ibcon#first serial, iclass 37, count 0 2006.257.09:51:25.75#ibcon#enter sib2, iclass 37, count 0 2006.257.09:51:25.75#ibcon#flushed, iclass 37, count 0 2006.257.09:51:25.75#ibcon#about to write, iclass 37, count 0 2006.257.09:51:25.75#ibcon#wrote, iclass 37, count 0 2006.257.09:51:25.75#ibcon#about to read 3, iclass 37, count 0 2006.257.09:51:25.77#ibcon#read 3, iclass 37, count 0 2006.257.09:51:25.77#ibcon#about to read 4, iclass 37, count 0 2006.257.09:51:25.77#ibcon#read 4, iclass 37, count 0 2006.257.09:51:25.77#ibcon#about to read 5, iclass 37, count 0 2006.257.09:51:25.77#ibcon#read 5, iclass 37, count 0 2006.257.09:51:25.77#ibcon#about to read 6, iclass 37, count 0 2006.257.09:51:25.77#ibcon#read 6, iclass 37, count 0 2006.257.09:51:25.77#ibcon#end of sib2, iclass 37, count 0 2006.257.09:51:25.77#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:51:25.77#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:51:25.77#ibcon#[25=USB\r\n] 2006.257.09:51:25.77#ibcon#*before write, iclass 37, count 0 2006.257.09:51:25.77#ibcon#enter sib2, iclass 37, count 0 2006.257.09:51:25.77#ibcon#flushed, iclass 37, count 0 2006.257.09:51:25.77#ibcon#about to write, iclass 37, count 0 2006.257.09:51:25.77#ibcon#wrote, iclass 37, count 0 2006.257.09:51:25.77#ibcon#about to read 3, iclass 37, count 0 2006.257.09:51:25.80#ibcon#read 3, iclass 37, count 0 2006.257.09:51:25.80#ibcon#about to read 4, iclass 37, count 0 2006.257.09:51:25.80#ibcon#read 4, iclass 37, count 0 2006.257.09:51:25.80#ibcon#about to read 5, iclass 37, count 0 2006.257.09:51:25.80#ibcon#read 5, iclass 37, count 0 2006.257.09:51:25.80#ibcon#about to read 6, iclass 37, count 0 2006.257.09:51:25.80#ibcon#read 6, iclass 37, count 0 2006.257.09:51:25.80#ibcon#end of sib2, iclass 37, count 0 2006.257.09:51:25.80#ibcon#*after write, iclass 37, count 0 2006.257.09:51:25.80#ibcon#*before return 0, iclass 37, count 0 2006.257.09:51:25.80#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:25.80#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:25.80#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:51:25.80#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:51:25.80$vck44/valo=6,814.99 2006.257.09:51:25.80#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.09:51:25.80#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.09:51:25.80#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:25.80#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:25.80#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:25.80#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:25.80#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:51:25.80#ibcon#first serial, iclass 39, count 0 2006.257.09:51:25.80#ibcon#enter sib2, iclass 39, count 0 2006.257.09:51:25.80#ibcon#flushed, iclass 39, count 0 2006.257.09:51:25.80#ibcon#about to write, iclass 39, count 0 2006.257.09:51:25.80#ibcon#wrote, iclass 39, count 0 2006.257.09:51:25.80#ibcon#about to read 3, iclass 39, count 0 2006.257.09:51:25.82#ibcon#read 3, iclass 39, count 0 2006.257.09:51:25.82#ibcon#about to read 4, iclass 39, count 0 2006.257.09:51:25.82#ibcon#read 4, iclass 39, count 0 2006.257.09:51:25.82#ibcon#about to read 5, iclass 39, count 0 2006.257.09:51:25.82#ibcon#read 5, iclass 39, count 0 2006.257.09:51:25.82#ibcon#about to read 6, iclass 39, count 0 2006.257.09:51:25.82#ibcon#read 6, iclass 39, count 0 2006.257.09:51:25.82#ibcon#end of sib2, iclass 39, count 0 2006.257.09:51:25.82#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:51:25.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:51:25.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:51:25.82#ibcon#*before write, iclass 39, count 0 2006.257.09:51:25.82#ibcon#enter sib2, iclass 39, count 0 2006.257.09:51:25.82#ibcon#flushed, iclass 39, count 0 2006.257.09:51:25.82#ibcon#about to write, iclass 39, count 0 2006.257.09:51:25.82#ibcon#wrote, iclass 39, count 0 2006.257.09:51:25.82#ibcon#about to read 3, iclass 39, count 0 2006.257.09:51:25.86#ibcon#read 3, iclass 39, count 0 2006.257.09:51:25.86#ibcon#about to read 4, iclass 39, count 0 2006.257.09:51:25.86#ibcon#read 4, iclass 39, count 0 2006.257.09:51:25.86#ibcon#about to read 5, iclass 39, count 0 2006.257.09:51:25.86#ibcon#read 5, iclass 39, count 0 2006.257.09:51:25.86#ibcon#about to read 6, iclass 39, count 0 2006.257.09:51:25.86#ibcon#read 6, iclass 39, count 0 2006.257.09:51:25.86#ibcon#end of sib2, iclass 39, count 0 2006.257.09:51:25.86#ibcon#*after write, iclass 39, count 0 2006.257.09:51:25.86#ibcon#*before return 0, iclass 39, count 0 2006.257.09:51:25.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:25.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:25.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:51:25.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:51:25.86$vck44/va=6,4 2006.257.09:51:25.86#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.09:51:25.86#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.09:51:25.86#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:25.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:25.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:25.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:25.92#ibcon#enter wrdev, iclass 3, count 2 2006.257.09:51:25.92#ibcon#first serial, iclass 3, count 2 2006.257.09:51:25.92#ibcon#enter sib2, iclass 3, count 2 2006.257.09:51:25.92#ibcon#flushed, iclass 3, count 2 2006.257.09:51:25.92#ibcon#about to write, iclass 3, count 2 2006.257.09:51:25.92#ibcon#wrote, iclass 3, count 2 2006.257.09:51:25.92#ibcon#about to read 3, iclass 3, count 2 2006.257.09:51:25.94#ibcon#read 3, iclass 3, count 2 2006.257.09:51:25.94#ibcon#about to read 4, iclass 3, count 2 2006.257.09:51:25.94#ibcon#read 4, iclass 3, count 2 2006.257.09:51:25.94#ibcon#about to read 5, iclass 3, count 2 2006.257.09:51:25.94#ibcon#read 5, iclass 3, count 2 2006.257.09:51:25.94#ibcon#about to read 6, iclass 3, count 2 2006.257.09:51:25.94#ibcon#read 6, iclass 3, count 2 2006.257.09:51:25.94#ibcon#end of sib2, iclass 3, count 2 2006.257.09:51:25.94#ibcon#*mode == 0, iclass 3, count 2 2006.257.09:51:25.94#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.09:51:25.94#ibcon#[25=AT06-04\r\n] 2006.257.09:51:25.94#ibcon#*before write, iclass 3, count 2 2006.257.09:51:25.94#ibcon#enter sib2, iclass 3, count 2 2006.257.09:51:25.94#ibcon#flushed, iclass 3, count 2 2006.257.09:51:25.94#ibcon#about to write, iclass 3, count 2 2006.257.09:51:25.94#ibcon#wrote, iclass 3, count 2 2006.257.09:51:25.94#ibcon#about to read 3, iclass 3, count 2 2006.257.09:51:25.97#ibcon#read 3, iclass 3, count 2 2006.257.09:51:25.97#ibcon#about to read 4, iclass 3, count 2 2006.257.09:51:25.97#ibcon#read 4, iclass 3, count 2 2006.257.09:51:25.97#ibcon#about to read 5, iclass 3, count 2 2006.257.09:51:25.97#ibcon#read 5, iclass 3, count 2 2006.257.09:51:25.97#ibcon#about to read 6, iclass 3, count 2 2006.257.09:51:25.97#ibcon#read 6, iclass 3, count 2 2006.257.09:51:25.97#ibcon#end of sib2, iclass 3, count 2 2006.257.09:51:25.97#ibcon#*after write, iclass 3, count 2 2006.257.09:51:25.97#ibcon#*before return 0, iclass 3, count 2 2006.257.09:51:25.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:25.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:25.97#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.09:51:25.97#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:25.97#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:26.09#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:26.09#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:26.09#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:51:26.09#ibcon#first serial, iclass 3, count 0 2006.257.09:51:26.09#ibcon#enter sib2, iclass 3, count 0 2006.257.09:51:26.09#ibcon#flushed, iclass 3, count 0 2006.257.09:51:26.09#ibcon#about to write, iclass 3, count 0 2006.257.09:51:26.09#ibcon#wrote, iclass 3, count 0 2006.257.09:51:26.09#ibcon#about to read 3, iclass 3, count 0 2006.257.09:51:26.11#ibcon#read 3, iclass 3, count 0 2006.257.09:51:26.11#ibcon#about to read 4, iclass 3, count 0 2006.257.09:51:26.11#ibcon#read 4, iclass 3, count 0 2006.257.09:51:26.11#ibcon#about to read 5, iclass 3, count 0 2006.257.09:51:26.11#ibcon#read 5, iclass 3, count 0 2006.257.09:51:26.11#ibcon#about to read 6, iclass 3, count 0 2006.257.09:51:26.11#ibcon#read 6, iclass 3, count 0 2006.257.09:51:26.11#ibcon#end of sib2, iclass 3, count 0 2006.257.09:51:26.11#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:51:26.11#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:51:26.11#ibcon#[25=USB\r\n] 2006.257.09:51:26.11#ibcon#*before write, iclass 3, count 0 2006.257.09:51:26.11#ibcon#enter sib2, iclass 3, count 0 2006.257.09:51:26.11#ibcon#flushed, iclass 3, count 0 2006.257.09:51:26.11#ibcon#about to write, iclass 3, count 0 2006.257.09:51:26.11#ibcon#wrote, iclass 3, count 0 2006.257.09:51:26.11#ibcon#about to read 3, iclass 3, count 0 2006.257.09:51:26.14#ibcon#read 3, iclass 3, count 0 2006.257.09:51:26.14#ibcon#about to read 4, iclass 3, count 0 2006.257.09:51:26.14#ibcon#read 4, iclass 3, count 0 2006.257.09:51:26.14#ibcon#about to read 5, iclass 3, count 0 2006.257.09:51:26.14#ibcon#read 5, iclass 3, count 0 2006.257.09:51:26.14#ibcon#about to read 6, iclass 3, count 0 2006.257.09:51:26.14#ibcon#read 6, iclass 3, count 0 2006.257.09:51:26.14#ibcon#end of sib2, iclass 3, count 0 2006.257.09:51:26.14#ibcon#*after write, iclass 3, count 0 2006.257.09:51:26.14#ibcon#*before return 0, iclass 3, count 0 2006.257.09:51:26.14#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:26.14#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:26.14#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:51:26.14#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:51:26.14$vck44/valo=7,864.99 2006.257.09:51:26.14#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.09:51:26.14#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.09:51:26.14#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:26.14#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:26.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:26.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:26.14#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:51:26.14#ibcon#first serial, iclass 5, count 0 2006.257.09:51:26.14#ibcon#enter sib2, iclass 5, count 0 2006.257.09:51:26.14#ibcon#flushed, iclass 5, count 0 2006.257.09:51:26.14#ibcon#about to write, iclass 5, count 0 2006.257.09:51:26.14#ibcon#wrote, iclass 5, count 0 2006.257.09:51:26.14#ibcon#about to read 3, iclass 5, count 0 2006.257.09:51:26.16#ibcon#read 3, iclass 5, count 0 2006.257.09:51:26.16#ibcon#about to read 4, iclass 5, count 0 2006.257.09:51:26.16#ibcon#read 4, iclass 5, count 0 2006.257.09:51:26.16#ibcon#about to read 5, iclass 5, count 0 2006.257.09:51:26.16#ibcon#read 5, iclass 5, count 0 2006.257.09:51:26.16#ibcon#about to read 6, iclass 5, count 0 2006.257.09:51:26.16#ibcon#read 6, iclass 5, count 0 2006.257.09:51:26.16#ibcon#end of sib2, iclass 5, count 0 2006.257.09:51:26.16#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:51:26.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:51:26.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:51:26.16#ibcon#*before write, iclass 5, count 0 2006.257.09:51:26.16#ibcon#enter sib2, iclass 5, count 0 2006.257.09:51:26.16#ibcon#flushed, iclass 5, count 0 2006.257.09:51:26.16#ibcon#about to write, iclass 5, count 0 2006.257.09:51:26.16#ibcon#wrote, iclass 5, count 0 2006.257.09:51:26.16#ibcon#about to read 3, iclass 5, count 0 2006.257.09:51:26.20#ibcon#read 3, iclass 5, count 0 2006.257.09:51:26.20#ibcon#about to read 4, iclass 5, count 0 2006.257.09:51:26.20#ibcon#read 4, iclass 5, count 0 2006.257.09:51:26.20#ibcon#about to read 5, iclass 5, count 0 2006.257.09:51:26.20#ibcon#read 5, iclass 5, count 0 2006.257.09:51:26.20#ibcon#about to read 6, iclass 5, count 0 2006.257.09:51:26.20#ibcon#read 6, iclass 5, count 0 2006.257.09:51:26.20#ibcon#end of sib2, iclass 5, count 0 2006.257.09:51:26.20#ibcon#*after write, iclass 5, count 0 2006.257.09:51:26.20#ibcon#*before return 0, iclass 5, count 0 2006.257.09:51:26.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:26.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:26.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:51:26.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:51:26.20$vck44/va=7,4 2006.257.09:51:26.20#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.09:51:26.20#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.09:51:26.20#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:26.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:26.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:26.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:26.26#ibcon#enter wrdev, iclass 7, count 2 2006.257.09:51:26.26#ibcon#first serial, iclass 7, count 2 2006.257.09:51:26.26#ibcon#enter sib2, iclass 7, count 2 2006.257.09:51:26.26#ibcon#flushed, iclass 7, count 2 2006.257.09:51:26.26#ibcon#about to write, iclass 7, count 2 2006.257.09:51:26.26#ibcon#wrote, iclass 7, count 2 2006.257.09:51:26.26#ibcon#about to read 3, iclass 7, count 2 2006.257.09:51:26.28#ibcon#read 3, iclass 7, count 2 2006.257.09:51:26.28#ibcon#about to read 4, iclass 7, count 2 2006.257.09:51:26.28#ibcon#read 4, iclass 7, count 2 2006.257.09:51:26.28#ibcon#about to read 5, iclass 7, count 2 2006.257.09:51:26.28#ibcon#read 5, iclass 7, count 2 2006.257.09:51:26.28#ibcon#about to read 6, iclass 7, count 2 2006.257.09:51:26.28#ibcon#read 6, iclass 7, count 2 2006.257.09:51:26.28#ibcon#end of sib2, iclass 7, count 2 2006.257.09:51:26.28#ibcon#*mode == 0, iclass 7, count 2 2006.257.09:51:26.28#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.09:51:26.28#ibcon#[25=AT07-04\r\n] 2006.257.09:51:26.28#ibcon#*before write, iclass 7, count 2 2006.257.09:51:26.28#ibcon#enter sib2, iclass 7, count 2 2006.257.09:51:26.28#ibcon#flushed, iclass 7, count 2 2006.257.09:51:26.28#ibcon#about to write, iclass 7, count 2 2006.257.09:51:26.28#ibcon#wrote, iclass 7, count 2 2006.257.09:51:26.28#ibcon#about to read 3, iclass 7, count 2 2006.257.09:51:26.31#ibcon#read 3, iclass 7, count 2 2006.257.09:51:26.31#ibcon#about to read 4, iclass 7, count 2 2006.257.09:51:26.31#ibcon#read 4, iclass 7, count 2 2006.257.09:51:26.31#ibcon#about to read 5, iclass 7, count 2 2006.257.09:51:26.31#ibcon#read 5, iclass 7, count 2 2006.257.09:51:26.31#ibcon#about to read 6, iclass 7, count 2 2006.257.09:51:26.31#ibcon#read 6, iclass 7, count 2 2006.257.09:51:26.31#ibcon#end of sib2, iclass 7, count 2 2006.257.09:51:26.31#ibcon#*after write, iclass 7, count 2 2006.257.09:51:26.31#ibcon#*before return 0, iclass 7, count 2 2006.257.09:51:26.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:26.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:26.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.09:51:26.36#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:26.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:26.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:26.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:26.48#ibcon#enter wrdev, iclass 7, count 0 2006.257.09:51:26.48#ibcon#first serial, iclass 7, count 0 2006.257.09:51:26.48#ibcon#enter sib2, iclass 7, count 0 2006.257.09:51:26.48#ibcon#flushed, iclass 7, count 0 2006.257.09:51:26.48#ibcon#about to write, iclass 7, count 0 2006.257.09:51:26.48#ibcon#wrote, iclass 7, count 0 2006.257.09:51:26.48#ibcon#about to read 3, iclass 7, count 0 2006.257.09:51:26.50#ibcon#read 3, iclass 7, count 0 2006.257.09:51:26.50#ibcon#about to read 4, iclass 7, count 0 2006.257.09:51:26.50#ibcon#read 4, iclass 7, count 0 2006.257.09:51:26.50#ibcon#about to read 5, iclass 7, count 0 2006.257.09:51:26.50#ibcon#read 5, iclass 7, count 0 2006.257.09:51:26.50#ibcon#about to read 6, iclass 7, count 0 2006.257.09:51:26.50#ibcon#read 6, iclass 7, count 0 2006.257.09:51:26.50#ibcon#end of sib2, iclass 7, count 0 2006.257.09:51:26.50#ibcon#*mode == 0, iclass 7, count 0 2006.257.09:51:26.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.09:51:26.50#ibcon#[25=USB\r\n] 2006.257.09:51:26.50#ibcon#*before write, iclass 7, count 0 2006.257.09:51:26.50#ibcon#enter sib2, iclass 7, count 0 2006.257.09:51:26.50#ibcon#flushed, iclass 7, count 0 2006.257.09:51:26.50#ibcon#about to write, iclass 7, count 0 2006.257.09:51:26.50#ibcon#wrote, iclass 7, count 0 2006.257.09:51:26.50#ibcon#about to read 3, iclass 7, count 0 2006.257.09:51:26.53#ibcon#read 3, iclass 7, count 0 2006.257.09:51:26.53#ibcon#about to read 4, iclass 7, count 0 2006.257.09:51:26.53#ibcon#read 4, iclass 7, count 0 2006.257.09:51:26.53#ibcon#about to read 5, iclass 7, count 0 2006.257.09:51:26.53#ibcon#read 5, iclass 7, count 0 2006.257.09:51:26.53#ibcon#about to read 6, iclass 7, count 0 2006.257.09:51:26.53#ibcon#read 6, iclass 7, count 0 2006.257.09:51:26.53#ibcon#end of sib2, iclass 7, count 0 2006.257.09:51:26.53#ibcon#*after write, iclass 7, count 0 2006.257.09:51:26.53#ibcon#*before return 0, iclass 7, count 0 2006.257.09:51:26.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:26.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:26.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.09:51:26.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.09:51:26.53$vck44/valo=8,884.99 2006.257.09:51:26.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.09:51:26.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.09:51:26.53#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:26.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:26.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:26.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:26.53#ibcon#enter wrdev, iclass 11, count 0 2006.257.09:51:26.53#ibcon#first serial, iclass 11, count 0 2006.257.09:51:26.53#ibcon#enter sib2, iclass 11, count 0 2006.257.09:51:26.53#ibcon#flushed, iclass 11, count 0 2006.257.09:51:26.53#ibcon#about to write, iclass 11, count 0 2006.257.09:51:26.53#ibcon#wrote, iclass 11, count 0 2006.257.09:51:26.53#ibcon#about to read 3, iclass 11, count 0 2006.257.09:51:26.55#ibcon#read 3, iclass 11, count 0 2006.257.09:51:26.55#ibcon#about to read 4, iclass 11, count 0 2006.257.09:51:26.55#ibcon#read 4, iclass 11, count 0 2006.257.09:51:26.55#ibcon#about to read 5, iclass 11, count 0 2006.257.09:51:26.55#ibcon#read 5, iclass 11, count 0 2006.257.09:51:26.55#ibcon#about to read 6, iclass 11, count 0 2006.257.09:51:26.55#ibcon#read 6, iclass 11, count 0 2006.257.09:51:26.55#ibcon#end of sib2, iclass 11, count 0 2006.257.09:51:26.55#ibcon#*mode == 0, iclass 11, count 0 2006.257.09:51:26.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.09:51:26.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:51:26.55#ibcon#*before write, iclass 11, count 0 2006.257.09:51:26.55#ibcon#enter sib2, iclass 11, count 0 2006.257.09:51:26.55#ibcon#flushed, iclass 11, count 0 2006.257.09:51:26.55#ibcon#about to write, iclass 11, count 0 2006.257.09:51:26.55#ibcon#wrote, iclass 11, count 0 2006.257.09:51:26.55#ibcon#about to read 3, iclass 11, count 0 2006.257.09:51:26.59#ibcon#read 3, iclass 11, count 0 2006.257.09:51:26.59#ibcon#about to read 4, iclass 11, count 0 2006.257.09:51:26.59#ibcon#read 4, iclass 11, count 0 2006.257.09:51:26.59#ibcon#about to read 5, iclass 11, count 0 2006.257.09:51:26.59#ibcon#read 5, iclass 11, count 0 2006.257.09:51:26.59#ibcon#about to read 6, iclass 11, count 0 2006.257.09:51:26.59#ibcon#read 6, iclass 11, count 0 2006.257.09:51:26.59#ibcon#end of sib2, iclass 11, count 0 2006.257.09:51:26.59#ibcon#*after write, iclass 11, count 0 2006.257.09:51:26.59#ibcon#*before return 0, iclass 11, count 0 2006.257.09:51:26.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:26.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:26.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.09:51:26.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.09:51:26.59$vck44/va=8,4 2006.257.09:51:26.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.09:51:26.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.09:51:26.59#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:26.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:51:26.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:51:26.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:51:26.65#ibcon#enter wrdev, iclass 13, count 2 2006.257.09:51:26.65#ibcon#first serial, iclass 13, count 2 2006.257.09:51:26.65#ibcon#enter sib2, iclass 13, count 2 2006.257.09:51:26.65#ibcon#flushed, iclass 13, count 2 2006.257.09:51:26.65#ibcon#about to write, iclass 13, count 2 2006.257.09:51:26.65#ibcon#wrote, iclass 13, count 2 2006.257.09:51:26.65#ibcon#about to read 3, iclass 13, count 2 2006.257.09:51:26.67#ibcon#read 3, iclass 13, count 2 2006.257.09:51:26.67#ibcon#about to read 4, iclass 13, count 2 2006.257.09:51:26.67#ibcon#read 4, iclass 13, count 2 2006.257.09:51:26.67#ibcon#about to read 5, iclass 13, count 2 2006.257.09:51:26.67#ibcon#read 5, iclass 13, count 2 2006.257.09:51:26.67#ibcon#about to read 6, iclass 13, count 2 2006.257.09:51:26.67#ibcon#read 6, iclass 13, count 2 2006.257.09:51:26.67#ibcon#end of sib2, iclass 13, count 2 2006.257.09:51:26.67#ibcon#*mode == 0, iclass 13, count 2 2006.257.09:51:26.67#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.09:51:26.67#ibcon#[25=AT08-04\r\n] 2006.257.09:51:26.67#ibcon#*before write, iclass 13, count 2 2006.257.09:51:26.67#ibcon#enter sib2, iclass 13, count 2 2006.257.09:51:26.67#ibcon#flushed, iclass 13, count 2 2006.257.09:51:26.67#ibcon#about to write, iclass 13, count 2 2006.257.09:51:26.67#ibcon#wrote, iclass 13, count 2 2006.257.09:51:26.67#ibcon#about to read 3, iclass 13, count 2 2006.257.09:51:26.70#ibcon#read 3, iclass 13, count 2 2006.257.09:51:26.70#ibcon#about to read 4, iclass 13, count 2 2006.257.09:51:26.70#ibcon#read 4, iclass 13, count 2 2006.257.09:51:26.70#ibcon#about to read 5, iclass 13, count 2 2006.257.09:51:26.70#ibcon#read 5, iclass 13, count 2 2006.257.09:51:26.70#ibcon#about to read 6, iclass 13, count 2 2006.257.09:51:26.70#ibcon#read 6, iclass 13, count 2 2006.257.09:51:26.70#ibcon#end of sib2, iclass 13, count 2 2006.257.09:51:26.70#ibcon#*after write, iclass 13, count 2 2006.257.09:51:26.70#ibcon#*before return 0, iclass 13, count 2 2006.257.09:51:26.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:51:26.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.09:51:26.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.09:51:26.70#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:26.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:51:26.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:51:26.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:51:26.82#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:51:26.82#ibcon#first serial, iclass 13, count 0 2006.257.09:51:26.82#ibcon#enter sib2, iclass 13, count 0 2006.257.09:51:26.82#ibcon#flushed, iclass 13, count 0 2006.257.09:51:26.82#ibcon#about to write, iclass 13, count 0 2006.257.09:51:26.82#ibcon#wrote, iclass 13, count 0 2006.257.09:51:26.82#ibcon#about to read 3, iclass 13, count 0 2006.257.09:51:26.84#ibcon#read 3, iclass 13, count 0 2006.257.09:51:26.84#ibcon#about to read 4, iclass 13, count 0 2006.257.09:51:26.84#ibcon#read 4, iclass 13, count 0 2006.257.09:51:26.84#ibcon#about to read 5, iclass 13, count 0 2006.257.09:51:26.84#ibcon#read 5, iclass 13, count 0 2006.257.09:51:26.84#ibcon#about to read 6, iclass 13, count 0 2006.257.09:51:26.84#ibcon#read 6, iclass 13, count 0 2006.257.09:51:26.84#ibcon#end of sib2, iclass 13, count 0 2006.257.09:51:26.84#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:51:26.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:51:26.84#ibcon#[25=USB\r\n] 2006.257.09:51:26.84#ibcon#*before write, iclass 13, count 0 2006.257.09:51:26.84#ibcon#enter sib2, iclass 13, count 0 2006.257.09:51:26.84#ibcon#flushed, iclass 13, count 0 2006.257.09:51:26.84#ibcon#about to write, iclass 13, count 0 2006.257.09:51:26.84#ibcon#wrote, iclass 13, count 0 2006.257.09:51:26.84#ibcon#about to read 3, iclass 13, count 0 2006.257.09:51:26.87#ibcon#read 3, iclass 13, count 0 2006.257.09:51:26.87#ibcon#about to read 4, iclass 13, count 0 2006.257.09:51:26.87#ibcon#read 4, iclass 13, count 0 2006.257.09:51:26.87#ibcon#about to read 5, iclass 13, count 0 2006.257.09:51:26.87#ibcon#read 5, iclass 13, count 0 2006.257.09:51:26.87#ibcon#about to read 6, iclass 13, count 0 2006.257.09:51:26.87#ibcon#read 6, iclass 13, count 0 2006.257.09:51:26.87#ibcon#end of sib2, iclass 13, count 0 2006.257.09:51:26.87#ibcon#*after write, iclass 13, count 0 2006.257.09:51:26.87#ibcon#*before return 0, iclass 13, count 0 2006.257.09:51:26.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:51:26.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.09:51:26.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:51:26.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:51:26.87$vck44/vblo=1,629.99 2006.257.09:51:26.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.09:51:26.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.09:51:26.87#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:26.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:51:26.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:51:26.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:51:26.87#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:51:26.87#ibcon#first serial, iclass 15, count 0 2006.257.09:51:26.87#ibcon#enter sib2, iclass 15, count 0 2006.257.09:51:26.87#ibcon#flushed, iclass 15, count 0 2006.257.09:51:26.87#ibcon#about to write, iclass 15, count 0 2006.257.09:51:26.87#ibcon#wrote, iclass 15, count 0 2006.257.09:51:26.87#ibcon#about to read 3, iclass 15, count 0 2006.257.09:51:26.89#ibcon#read 3, iclass 15, count 0 2006.257.09:51:26.89#ibcon#about to read 4, iclass 15, count 0 2006.257.09:51:26.89#ibcon#read 4, iclass 15, count 0 2006.257.09:51:26.89#ibcon#about to read 5, iclass 15, count 0 2006.257.09:51:26.89#ibcon#read 5, iclass 15, count 0 2006.257.09:51:26.89#ibcon#about to read 6, iclass 15, count 0 2006.257.09:51:26.89#ibcon#read 6, iclass 15, count 0 2006.257.09:51:26.89#ibcon#end of sib2, iclass 15, count 0 2006.257.09:51:26.89#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:51:26.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:51:26.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:51:26.89#ibcon#*before write, iclass 15, count 0 2006.257.09:51:26.89#ibcon#enter sib2, iclass 15, count 0 2006.257.09:51:26.89#ibcon#flushed, iclass 15, count 0 2006.257.09:51:26.89#ibcon#about to write, iclass 15, count 0 2006.257.09:51:26.89#ibcon#wrote, iclass 15, count 0 2006.257.09:51:26.89#ibcon#about to read 3, iclass 15, count 0 2006.257.09:51:26.93#ibcon#read 3, iclass 15, count 0 2006.257.09:51:26.93#ibcon#about to read 4, iclass 15, count 0 2006.257.09:51:26.93#ibcon#read 4, iclass 15, count 0 2006.257.09:51:26.93#ibcon#about to read 5, iclass 15, count 0 2006.257.09:51:26.93#ibcon#read 5, iclass 15, count 0 2006.257.09:51:26.93#ibcon#about to read 6, iclass 15, count 0 2006.257.09:51:26.93#ibcon#read 6, iclass 15, count 0 2006.257.09:51:26.93#ibcon#end of sib2, iclass 15, count 0 2006.257.09:51:26.93#ibcon#*after write, iclass 15, count 0 2006.257.09:51:26.93#ibcon#*before return 0, iclass 15, count 0 2006.257.09:51:26.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:51:26.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:51:26.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:51:26.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:51:26.93$vck44/vb=1,4 2006.257.09:51:26.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.09:51:26.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.09:51:26.93#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:26.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:51:26.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:51:26.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:51:26.93#ibcon#enter wrdev, iclass 17, count 2 2006.257.09:51:26.93#ibcon#first serial, iclass 17, count 2 2006.257.09:51:26.93#ibcon#enter sib2, iclass 17, count 2 2006.257.09:51:26.93#ibcon#flushed, iclass 17, count 2 2006.257.09:51:26.93#ibcon#about to write, iclass 17, count 2 2006.257.09:51:26.93#ibcon#wrote, iclass 17, count 2 2006.257.09:51:26.93#ibcon#about to read 3, iclass 17, count 2 2006.257.09:51:26.95#ibcon#read 3, iclass 17, count 2 2006.257.09:51:26.95#ibcon#about to read 4, iclass 17, count 2 2006.257.09:51:26.95#ibcon#read 4, iclass 17, count 2 2006.257.09:51:26.95#ibcon#about to read 5, iclass 17, count 2 2006.257.09:51:26.95#ibcon#read 5, iclass 17, count 2 2006.257.09:51:26.95#ibcon#about to read 6, iclass 17, count 2 2006.257.09:51:26.95#ibcon#read 6, iclass 17, count 2 2006.257.09:51:26.95#ibcon#end of sib2, iclass 17, count 2 2006.257.09:51:26.95#ibcon#*mode == 0, iclass 17, count 2 2006.257.09:51:26.95#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.09:51:26.95#ibcon#[27=AT01-04\r\n] 2006.257.09:51:26.95#ibcon#*before write, iclass 17, count 2 2006.257.09:51:26.95#ibcon#enter sib2, iclass 17, count 2 2006.257.09:51:26.95#ibcon#flushed, iclass 17, count 2 2006.257.09:51:26.95#ibcon#about to write, iclass 17, count 2 2006.257.09:51:26.95#ibcon#wrote, iclass 17, count 2 2006.257.09:51:26.95#ibcon#about to read 3, iclass 17, count 2 2006.257.09:51:26.98#ibcon#read 3, iclass 17, count 2 2006.257.09:51:26.98#ibcon#about to read 4, iclass 17, count 2 2006.257.09:51:26.98#ibcon#read 4, iclass 17, count 2 2006.257.09:51:26.98#ibcon#about to read 5, iclass 17, count 2 2006.257.09:51:26.98#ibcon#read 5, iclass 17, count 2 2006.257.09:51:26.98#ibcon#about to read 6, iclass 17, count 2 2006.257.09:51:26.98#ibcon#read 6, iclass 17, count 2 2006.257.09:51:26.98#ibcon#end of sib2, iclass 17, count 2 2006.257.09:51:26.98#ibcon#*after write, iclass 17, count 2 2006.257.09:51:26.98#ibcon#*before return 0, iclass 17, count 2 2006.257.09:51:26.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:51:26.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.09:51:26.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.09:51:26.98#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:26.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:51:27.10#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:51:27.10#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:51:27.10#ibcon#enter wrdev, iclass 17, count 0 2006.257.09:51:27.10#ibcon#first serial, iclass 17, count 0 2006.257.09:51:27.10#ibcon#enter sib2, iclass 17, count 0 2006.257.09:51:27.10#ibcon#flushed, iclass 17, count 0 2006.257.09:51:27.10#ibcon#about to write, iclass 17, count 0 2006.257.09:51:27.10#ibcon#wrote, iclass 17, count 0 2006.257.09:51:27.10#ibcon#about to read 3, iclass 17, count 0 2006.257.09:51:27.12#ibcon#read 3, iclass 17, count 0 2006.257.09:51:27.12#ibcon#about to read 4, iclass 17, count 0 2006.257.09:51:27.12#ibcon#read 4, iclass 17, count 0 2006.257.09:51:27.12#ibcon#about to read 5, iclass 17, count 0 2006.257.09:51:27.12#ibcon#read 5, iclass 17, count 0 2006.257.09:51:27.12#ibcon#about to read 6, iclass 17, count 0 2006.257.09:51:27.12#ibcon#read 6, iclass 17, count 0 2006.257.09:51:27.12#ibcon#end of sib2, iclass 17, count 0 2006.257.09:51:27.12#ibcon#*mode == 0, iclass 17, count 0 2006.257.09:51:27.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.09:51:27.12#ibcon#[27=USB\r\n] 2006.257.09:51:27.12#ibcon#*before write, iclass 17, count 0 2006.257.09:51:27.12#ibcon#enter sib2, iclass 17, count 0 2006.257.09:51:27.12#ibcon#flushed, iclass 17, count 0 2006.257.09:51:27.12#ibcon#about to write, iclass 17, count 0 2006.257.09:51:27.12#ibcon#wrote, iclass 17, count 0 2006.257.09:51:27.12#ibcon#about to read 3, iclass 17, count 0 2006.257.09:51:27.15#ibcon#read 3, iclass 17, count 0 2006.257.09:51:27.15#ibcon#about to read 4, iclass 17, count 0 2006.257.09:51:27.15#ibcon#read 4, iclass 17, count 0 2006.257.09:51:27.15#ibcon#about to read 5, iclass 17, count 0 2006.257.09:51:27.15#ibcon#read 5, iclass 17, count 0 2006.257.09:51:27.15#ibcon#about to read 6, iclass 17, count 0 2006.257.09:51:27.15#ibcon#read 6, iclass 17, count 0 2006.257.09:51:27.15#ibcon#end of sib2, iclass 17, count 0 2006.257.09:51:27.15#ibcon#*after write, iclass 17, count 0 2006.257.09:51:27.15#ibcon#*before return 0, iclass 17, count 0 2006.257.09:51:27.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:51:27.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.09:51:27.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.09:51:27.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.09:51:27.15$vck44/vblo=2,634.99 2006.257.09:51:27.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.09:51:27.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.09:51:27.15#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:27.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:27.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:27.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:27.15#ibcon#enter wrdev, iclass 19, count 0 2006.257.09:51:27.15#ibcon#first serial, iclass 19, count 0 2006.257.09:51:27.15#ibcon#enter sib2, iclass 19, count 0 2006.257.09:51:27.15#ibcon#flushed, iclass 19, count 0 2006.257.09:51:27.15#ibcon#about to write, iclass 19, count 0 2006.257.09:51:27.15#ibcon#wrote, iclass 19, count 0 2006.257.09:51:27.15#ibcon#about to read 3, iclass 19, count 0 2006.257.09:51:27.17#ibcon#read 3, iclass 19, count 0 2006.257.09:51:27.17#ibcon#about to read 4, iclass 19, count 0 2006.257.09:51:27.17#ibcon#read 4, iclass 19, count 0 2006.257.09:51:27.17#ibcon#about to read 5, iclass 19, count 0 2006.257.09:51:27.17#ibcon#read 5, iclass 19, count 0 2006.257.09:51:27.17#ibcon#about to read 6, iclass 19, count 0 2006.257.09:51:27.17#ibcon#read 6, iclass 19, count 0 2006.257.09:51:27.17#ibcon#end of sib2, iclass 19, count 0 2006.257.09:51:27.17#ibcon#*mode == 0, iclass 19, count 0 2006.257.09:51:27.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.09:51:27.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:51:27.17#ibcon#*before write, iclass 19, count 0 2006.257.09:51:27.17#ibcon#enter sib2, iclass 19, count 0 2006.257.09:51:27.17#ibcon#flushed, iclass 19, count 0 2006.257.09:51:27.17#ibcon#about to write, iclass 19, count 0 2006.257.09:51:27.17#ibcon#wrote, iclass 19, count 0 2006.257.09:51:27.17#ibcon#about to read 3, iclass 19, count 0 2006.257.09:51:27.21#ibcon#read 3, iclass 19, count 0 2006.257.09:51:27.21#ibcon#about to read 4, iclass 19, count 0 2006.257.09:51:27.21#ibcon#read 4, iclass 19, count 0 2006.257.09:51:27.21#ibcon#about to read 5, iclass 19, count 0 2006.257.09:51:27.21#ibcon#read 5, iclass 19, count 0 2006.257.09:51:27.21#ibcon#about to read 6, iclass 19, count 0 2006.257.09:51:27.21#ibcon#read 6, iclass 19, count 0 2006.257.09:51:27.21#ibcon#end of sib2, iclass 19, count 0 2006.257.09:51:27.21#ibcon#*after write, iclass 19, count 0 2006.257.09:51:27.21#ibcon#*before return 0, iclass 19, count 0 2006.257.09:51:27.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:27.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:51:27.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.09:51:27.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.09:51:27.21$vck44/vb=2,5 2006.257.09:51:27.21#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.09:51:27.21#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.09:51:27.21#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:27.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:27.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:27.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:27.27#ibcon#enter wrdev, iclass 21, count 2 2006.257.09:51:27.27#ibcon#first serial, iclass 21, count 2 2006.257.09:51:27.27#ibcon#enter sib2, iclass 21, count 2 2006.257.09:51:27.27#ibcon#flushed, iclass 21, count 2 2006.257.09:51:27.27#ibcon#about to write, iclass 21, count 2 2006.257.09:51:27.27#ibcon#wrote, iclass 21, count 2 2006.257.09:51:27.27#ibcon#about to read 3, iclass 21, count 2 2006.257.09:51:27.29#ibcon#read 3, iclass 21, count 2 2006.257.09:51:27.29#ibcon#about to read 4, iclass 21, count 2 2006.257.09:51:27.29#ibcon#read 4, iclass 21, count 2 2006.257.09:51:27.29#ibcon#about to read 5, iclass 21, count 2 2006.257.09:51:27.29#ibcon#read 5, iclass 21, count 2 2006.257.09:51:27.29#ibcon#about to read 6, iclass 21, count 2 2006.257.09:51:27.29#ibcon#read 6, iclass 21, count 2 2006.257.09:51:27.29#ibcon#end of sib2, iclass 21, count 2 2006.257.09:51:27.29#ibcon#*mode == 0, iclass 21, count 2 2006.257.09:51:27.29#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.09:51:27.29#ibcon#[27=AT02-05\r\n] 2006.257.09:51:27.29#ibcon#*before write, iclass 21, count 2 2006.257.09:51:27.29#ibcon#enter sib2, iclass 21, count 2 2006.257.09:51:27.29#ibcon#flushed, iclass 21, count 2 2006.257.09:51:27.29#ibcon#about to write, iclass 21, count 2 2006.257.09:51:27.29#ibcon#wrote, iclass 21, count 2 2006.257.09:51:27.29#ibcon#about to read 3, iclass 21, count 2 2006.257.09:51:27.32#ibcon#read 3, iclass 21, count 2 2006.257.09:51:27.32#ibcon#about to read 4, iclass 21, count 2 2006.257.09:51:27.32#ibcon#read 4, iclass 21, count 2 2006.257.09:51:27.32#ibcon#about to read 5, iclass 21, count 2 2006.257.09:51:27.32#ibcon#read 5, iclass 21, count 2 2006.257.09:51:27.32#ibcon#about to read 6, iclass 21, count 2 2006.257.09:51:27.32#ibcon#read 6, iclass 21, count 2 2006.257.09:51:27.32#ibcon#end of sib2, iclass 21, count 2 2006.257.09:51:27.32#ibcon#*after write, iclass 21, count 2 2006.257.09:51:27.32#ibcon#*before return 0, iclass 21, count 2 2006.257.09:51:27.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:27.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.09:51:27.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.09:51:27.37#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:27.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:27.48#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:27.48#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:27.48#ibcon#enter wrdev, iclass 21, count 0 2006.257.09:51:27.48#ibcon#first serial, iclass 21, count 0 2006.257.09:51:27.48#ibcon#enter sib2, iclass 21, count 0 2006.257.09:51:27.48#ibcon#flushed, iclass 21, count 0 2006.257.09:51:27.48#ibcon#about to write, iclass 21, count 0 2006.257.09:51:27.48#ibcon#wrote, iclass 21, count 0 2006.257.09:51:27.48#ibcon#about to read 3, iclass 21, count 0 2006.257.09:51:27.50#ibcon#read 3, iclass 21, count 0 2006.257.09:51:27.50#ibcon#about to read 4, iclass 21, count 0 2006.257.09:51:27.50#ibcon#read 4, iclass 21, count 0 2006.257.09:51:27.50#ibcon#about to read 5, iclass 21, count 0 2006.257.09:51:27.50#ibcon#read 5, iclass 21, count 0 2006.257.09:51:27.50#ibcon#about to read 6, iclass 21, count 0 2006.257.09:51:27.50#ibcon#read 6, iclass 21, count 0 2006.257.09:51:27.50#ibcon#end of sib2, iclass 21, count 0 2006.257.09:51:27.50#ibcon#*mode == 0, iclass 21, count 0 2006.257.09:51:27.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.09:51:27.50#ibcon#[27=USB\r\n] 2006.257.09:51:27.50#ibcon#*before write, iclass 21, count 0 2006.257.09:51:27.50#ibcon#enter sib2, iclass 21, count 0 2006.257.09:51:27.50#ibcon#flushed, iclass 21, count 0 2006.257.09:51:27.50#ibcon#about to write, iclass 21, count 0 2006.257.09:51:27.50#ibcon#wrote, iclass 21, count 0 2006.257.09:51:27.50#ibcon#about to read 3, iclass 21, count 0 2006.257.09:51:27.53#ibcon#read 3, iclass 21, count 0 2006.257.09:51:27.53#ibcon#about to read 4, iclass 21, count 0 2006.257.09:51:27.53#ibcon#read 4, iclass 21, count 0 2006.257.09:51:27.53#ibcon#about to read 5, iclass 21, count 0 2006.257.09:51:27.53#ibcon#read 5, iclass 21, count 0 2006.257.09:51:27.53#ibcon#about to read 6, iclass 21, count 0 2006.257.09:51:27.53#ibcon#read 6, iclass 21, count 0 2006.257.09:51:27.53#ibcon#end of sib2, iclass 21, count 0 2006.257.09:51:27.53#ibcon#*after write, iclass 21, count 0 2006.257.09:51:27.53#ibcon#*before return 0, iclass 21, count 0 2006.257.09:51:27.53#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:27.53#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.09:51:27.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.09:51:27.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.09:51:27.53$vck44/vblo=3,649.99 2006.257.09:51:27.53#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.09:51:27.53#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.09:51:27.53#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:27.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:27.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:27.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:27.53#ibcon#enter wrdev, iclass 23, count 0 2006.257.09:51:27.53#ibcon#first serial, iclass 23, count 0 2006.257.09:51:27.53#ibcon#enter sib2, iclass 23, count 0 2006.257.09:51:27.53#ibcon#flushed, iclass 23, count 0 2006.257.09:51:27.53#ibcon#about to write, iclass 23, count 0 2006.257.09:51:27.53#ibcon#wrote, iclass 23, count 0 2006.257.09:51:27.53#ibcon#about to read 3, iclass 23, count 0 2006.257.09:51:27.55#ibcon#read 3, iclass 23, count 0 2006.257.09:51:27.55#ibcon#about to read 4, iclass 23, count 0 2006.257.09:51:27.55#ibcon#read 4, iclass 23, count 0 2006.257.09:51:27.55#ibcon#about to read 5, iclass 23, count 0 2006.257.09:51:27.55#ibcon#read 5, iclass 23, count 0 2006.257.09:51:27.55#ibcon#about to read 6, iclass 23, count 0 2006.257.09:51:27.55#ibcon#read 6, iclass 23, count 0 2006.257.09:51:27.55#ibcon#end of sib2, iclass 23, count 0 2006.257.09:51:27.55#ibcon#*mode == 0, iclass 23, count 0 2006.257.09:51:27.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.09:51:27.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:51:27.55#ibcon#*before write, iclass 23, count 0 2006.257.09:51:27.55#ibcon#enter sib2, iclass 23, count 0 2006.257.09:51:27.55#ibcon#flushed, iclass 23, count 0 2006.257.09:51:27.55#ibcon#about to write, iclass 23, count 0 2006.257.09:51:27.55#ibcon#wrote, iclass 23, count 0 2006.257.09:51:27.55#ibcon#about to read 3, iclass 23, count 0 2006.257.09:51:27.59#ibcon#read 3, iclass 23, count 0 2006.257.09:51:27.59#ibcon#about to read 4, iclass 23, count 0 2006.257.09:51:27.59#ibcon#read 4, iclass 23, count 0 2006.257.09:51:27.59#ibcon#about to read 5, iclass 23, count 0 2006.257.09:51:27.59#ibcon#read 5, iclass 23, count 0 2006.257.09:51:27.59#ibcon#about to read 6, iclass 23, count 0 2006.257.09:51:27.59#ibcon#read 6, iclass 23, count 0 2006.257.09:51:27.59#ibcon#end of sib2, iclass 23, count 0 2006.257.09:51:27.59#ibcon#*after write, iclass 23, count 0 2006.257.09:51:27.59#ibcon#*before return 0, iclass 23, count 0 2006.257.09:51:27.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:27.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.09:51:27.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.09:51:27.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.09:51:27.59$vck44/vb=3,4 2006.257.09:51:27.59#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.09:51:27.59#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.09:51:27.59#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:27.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:27.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:27.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:27.65#ibcon#enter wrdev, iclass 25, count 2 2006.257.09:51:27.65#ibcon#first serial, iclass 25, count 2 2006.257.09:51:27.65#ibcon#enter sib2, iclass 25, count 2 2006.257.09:51:27.65#ibcon#flushed, iclass 25, count 2 2006.257.09:51:27.65#ibcon#about to write, iclass 25, count 2 2006.257.09:51:27.65#ibcon#wrote, iclass 25, count 2 2006.257.09:51:27.65#ibcon#about to read 3, iclass 25, count 2 2006.257.09:51:27.67#ibcon#read 3, iclass 25, count 2 2006.257.09:51:27.67#ibcon#about to read 4, iclass 25, count 2 2006.257.09:51:27.67#ibcon#read 4, iclass 25, count 2 2006.257.09:51:27.67#ibcon#about to read 5, iclass 25, count 2 2006.257.09:51:27.67#ibcon#read 5, iclass 25, count 2 2006.257.09:51:27.67#ibcon#about to read 6, iclass 25, count 2 2006.257.09:51:27.67#ibcon#read 6, iclass 25, count 2 2006.257.09:51:27.67#ibcon#end of sib2, iclass 25, count 2 2006.257.09:51:27.67#ibcon#*mode == 0, iclass 25, count 2 2006.257.09:51:27.67#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.09:51:27.67#ibcon#[27=AT03-04\r\n] 2006.257.09:51:27.67#ibcon#*before write, iclass 25, count 2 2006.257.09:51:27.67#ibcon#enter sib2, iclass 25, count 2 2006.257.09:51:27.67#ibcon#flushed, iclass 25, count 2 2006.257.09:51:27.67#ibcon#about to write, iclass 25, count 2 2006.257.09:51:27.67#ibcon#wrote, iclass 25, count 2 2006.257.09:51:27.67#ibcon#about to read 3, iclass 25, count 2 2006.257.09:51:27.70#ibcon#read 3, iclass 25, count 2 2006.257.09:51:27.70#ibcon#about to read 4, iclass 25, count 2 2006.257.09:51:27.70#ibcon#read 4, iclass 25, count 2 2006.257.09:51:27.70#ibcon#about to read 5, iclass 25, count 2 2006.257.09:51:27.70#ibcon#read 5, iclass 25, count 2 2006.257.09:51:27.70#ibcon#about to read 6, iclass 25, count 2 2006.257.09:51:27.70#ibcon#read 6, iclass 25, count 2 2006.257.09:51:27.70#ibcon#end of sib2, iclass 25, count 2 2006.257.09:51:27.70#ibcon#*after write, iclass 25, count 2 2006.257.09:51:27.70#ibcon#*before return 0, iclass 25, count 2 2006.257.09:51:27.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:27.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.09:51:27.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.09:51:27.70#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:27.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:27.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:27.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:27.82#ibcon#enter wrdev, iclass 25, count 0 2006.257.09:51:27.82#ibcon#first serial, iclass 25, count 0 2006.257.09:51:27.82#ibcon#enter sib2, iclass 25, count 0 2006.257.09:51:27.82#ibcon#flushed, iclass 25, count 0 2006.257.09:51:27.82#ibcon#about to write, iclass 25, count 0 2006.257.09:51:27.82#ibcon#wrote, iclass 25, count 0 2006.257.09:51:27.82#ibcon#about to read 3, iclass 25, count 0 2006.257.09:51:27.84#ibcon#read 3, iclass 25, count 0 2006.257.09:51:27.84#ibcon#about to read 4, iclass 25, count 0 2006.257.09:51:27.84#ibcon#read 4, iclass 25, count 0 2006.257.09:51:27.84#ibcon#about to read 5, iclass 25, count 0 2006.257.09:51:27.84#ibcon#read 5, iclass 25, count 0 2006.257.09:51:27.84#ibcon#about to read 6, iclass 25, count 0 2006.257.09:51:27.84#ibcon#read 6, iclass 25, count 0 2006.257.09:51:27.84#ibcon#end of sib2, iclass 25, count 0 2006.257.09:51:27.84#ibcon#*mode == 0, iclass 25, count 0 2006.257.09:51:27.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.09:51:27.84#ibcon#[27=USB\r\n] 2006.257.09:51:27.84#ibcon#*before write, iclass 25, count 0 2006.257.09:51:27.84#ibcon#enter sib2, iclass 25, count 0 2006.257.09:51:27.84#ibcon#flushed, iclass 25, count 0 2006.257.09:51:27.84#ibcon#about to write, iclass 25, count 0 2006.257.09:51:27.84#ibcon#wrote, iclass 25, count 0 2006.257.09:51:27.84#ibcon#about to read 3, iclass 25, count 0 2006.257.09:51:27.87#ibcon#read 3, iclass 25, count 0 2006.257.09:51:27.87#ibcon#about to read 4, iclass 25, count 0 2006.257.09:51:27.87#ibcon#read 4, iclass 25, count 0 2006.257.09:51:27.87#ibcon#about to read 5, iclass 25, count 0 2006.257.09:51:27.87#ibcon#read 5, iclass 25, count 0 2006.257.09:51:27.87#ibcon#about to read 6, iclass 25, count 0 2006.257.09:51:27.87#ibcon#read 6, iclass 25, count 0 2006.257.09:51:27.87#ibcon#end of sib2, iclass 25, count 0 2006.257.09:51:27.87#ibcon#*after write, iclass 25, count 0 2006.257.09:51:27.87#ibcon#*before return 0, iclass 25, count 0 2006.257.09:51:27.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:27.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.09:51:27.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.09:51:27.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.09:51:27.87$vck44/vblo=4,679.99 2006.257.09:51:27.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.09:51:27.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.09:51:27.87#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:27.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:27.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:27.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:27.87#ibcon#enter wrdev, iclass 27, count 0 2006.257.09:51:27.87#ibcon#first serial, iclass 27, count 0 2006.257.09:51:27.87#ibcon#enter sib2, iclass 27, count 0 2006.257.09:51:27.87#ibcon#flushed, iclass 27, count 0 2006.257.09:51:27.87#ibcon#about to write, iclass 27, count 0 2006.257.09:51:27.87#ibcon#wrote, iclass 27, count 0 2006.257.09:51:27.87#ibcon#about to read 3, iclass 27, count 0 2006.257.09:51:27.89#ibcon#read 3, iclass 27, count 0 2006.257.09:51:27.89#ibcon#about to read 4, iclass 27, count 0 2006.257.09:51:27.89#ibcon#read 4, iclass 27, count 0 2006.257.09:51:27.89#ibcon#about to read 5, iclass 27, count 0 2006.257.09:51:27.89#ibcon#read 5, iclass 27, count 0 2006.257.09:51:27.89#ibcon#about to read 6, iclass 27, count 0 2006.257.09:51:27.89#ibcon#read 6, iclass 27, count 0 2006.257.09:51:27.89#ibcon#end of sib2, iclass 27, count 0 2006.257.09:51:27.89#ibcon#*mode == 0, iclass 27, count 0 2006.257.09:51:27.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.09:51:27.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:51:27.89#ibcon#*before write, iclass 27, count 0 2006.257.09:51:27.89#ibcon#enter sib2, iclass 27, count 0 2006.257.09:51:27.89#ibcon#flushed, iclass 27, count 0 2006.257.09:51:27.89#ibcon#about to write, iclass 27, count 0 2006.257.09:51:27.89#ibcon#wrote, iclass 27, count 0 2006.257.09:51:27.89#ibcon#about to read 3, iclass 27, count 0 2006.257.09:51:27.93#ibcon#read 3, iclass 27, count 0 2006.257.09:51:27.93#ibcon#about to read 4, iclass 27, count 0 2006.257.09:51:27.93#ibcon#read 4, iclass 27, count 0 2006.257.09:51:27.93#ibcon#about to read 5, iclass 27, count 0 2006.257.09:51:27.93#ibcon#read 5, iclass 27, count 0 2006.257.09:51:27.93#ibcon#about to read 6, iclass 27, count 0 2006.257.09:51:27.93#ibcon#read 6, iclass 27, count 0 2006.257.09:51:27.93#ibcon#end of sib2, iclass 27, count 0 2006.257.09:51:27.93#ibcon#*after write, iclass 27, count 0 2006.257.09:51:27.93#ibcon#*before return 0, iclass 27, count 0 2006.257.09:51:27.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:27.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.09:51:27.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.09:51:27.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.09:51:27.93$vck44/vb=4,5 2006.257.09:51:27.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.09:51:27.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.09:51:27.93#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:27.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:27.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:27.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:27.99#ibcon#enter wrdev, iclass 29, count 2 2006.257.09:51:27.99#ibcon#first serial, iclass 29, count 2 2006.257.09:51:27.99#ibcon#enter sib2, iclass 29, count 2 2006.257.09:51:27.99#ibcon#flushed, iclass 29, count 2 2006.257.09:51:27.99#ibcon#about to write, iclass 29, count 2 2006.257.09:51:27.99#ibcon#wrote, iclass 29, count 2 2006.257.09:51:27.99#ibcon#about to read 3, iclass 29, count 2 2006.257.09:51:28.01#ibcon#read 3, iclass 29, count 2 2006.257.09:51:28.01#ibcon#about to read 4, iclass 29, count 2 2006.257.09:51:28.01#ibcon#read 4, iclass 29, count 2 2006.257.09:51:28.01#ibcon#about to read 5, iclass 29, count 2 2006.257.09:51:28.01#ibcon#read 5, iclass 29, count 2 2006.257.09:51:28.01#ibcon#about to read 6, iclass 29, count 2 2006.257.09:51:28.01#ibcon#read 6, iclass 29, count 2 2006.257.09:51:28.01#ibcon#end of sib2, iclass 29, count 2 2006.257.09:51:28.01#ibcon#*mode == 0, iclass 29, count 2 2006.257.09:51:28.01#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.09:51:28.01#ibcon#[27=AT04-05\r\n] 2006.257.09:51:28.01#ibcon#*before write, iclass 29, count 2 2006.257.09:51:28.01#ibcon#enter sib2, iclass 29, count 2 2006.257.09:51:28.01#ibcon#flushed, iclass 29, count 2 2006.257.09:51:28.01#ibcon#about to write, iclass 29, count 2 2006.257.09:51:28.01#ibcon#wrote, iclass 29, count 2 2006.257.09:51:28.01#ibcon#about to read 3, iclass 29, count 2 2006.257.09:51:28.04#ibcon#read 3, iclass 29, count 2 2006.257.09:51:28.04#ibcon#about to read 4, iclass 29, count 2 2006.257.09:51:28.04#ibcon#read 4, iclass 29, count 2 2006.257.09:51:28.04#ibcon#about to read 5, iclass 29, count 2 2006.257.09:51:28.04#ibcon#read 5, iclass 29, count 2 2006.257.09:51:28.04#ibcon#about to read 6, iclass 29, count 2 2006.257.09:51:28.04#ibcon#read 6, iclass 29, count 2 2006.257.09:51:28.04#ibcon#end of sib2, iclass 29, count 2 2006.257.09:51:28.04#ibcon#*after write, iclass 29, count 2 2006.257.09:51:28.04#ibcon#*before return 0, iclass 29, count 2 2006.257.09:51:28.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:28.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.09:51:28.04#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.09:51:28.04#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:28.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:28.16#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:28.16#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:28.16#ibcon#enter wrdev, iclass 29, count 0 2006.257.09:51:28.16#ibcon#first serial, iclass 29, count 0 2006.257.09:51:28.16#ibcon#enter sib2, iclass 29, count 0 2006.257.09:51:28.16#ibcon#flushed, iclass 29, count 0 2006.257.09:51:28.16#ibcon#about to write, iclass 29, count 0 2006.257.09:51:28.16#ibcon#wrote, iclass 29, count 0 2006.257.09:51:28.16#ibcon#about to read 3, iclass 29, count 0 2006.257.09:51:28.18#ibcon#read 3, iclass 29, count 0 2006.257.09:51:28.18#ibcon#about to read 4, iclass 29, count 0 2006.257.09:51:28.18#ibcon#read 4, iclass 29, count 0 2006.257.09:51:28.18#ibcon#about to read 5, iclass 29, count 0 2006.257.09:51:28.18#ibcon#read 5, iclass 29, count 0 2006.257.09:51:28.18#ibcon#about to read 6, iclass 29, count 0 2006.257.09:51:28.18#ibcon#read 6, iclass 29, count 0 2006.257.09:51:28.18#ibcon#end of sib2, iclass 29, count 0 2006.257.09:51:28.18#ibcon#*mode == 0, iclass 29, count 0 2006.257.09:51:28.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.09:51:28.18#ibcon#[27=USB\r\n] 2006.257.09:51:28.18#ibcon#*before write, iclass 29, count 0 2006.257.09:51:28.18#ibcon#enter sib2, iclass 29, count 0 2006.257.09:51:28.18#ibcon#flushed, iclass 29, count 0 2006.257.09:51:28.18#ibcon#about to write, iclass 29, count 0 2006.257.09:51:28.18#ibcon#wrote, iclass 29, count 0 2006.257.09:51:28.18#ibcon#about to read 3, iclass 29, count 0 2006.257.09:51:28.21#ibcon#read 3, iclass 29, count 0 2006.257.09:51:28.21#ibcon#about to read 4, iclass 29, count 0 2006.257.09:51:28.21#ibcon#read 4, iclass 29, count 0 2006.257.09:51:28.21#ibcon#about to read 5, iclass 29, count 0 2006.257.09:51:28.21#ibcon#read 5, iclass 29, count 0 2006.257.09:51:28.21#ibcon#about to read 6, iclass 29, count 0 2006.257.09:51:28.21#ibcon#read 6, iclass 29, count 0 2006.257.09:51:28.21#ibcon#end of sib2, iclass 29, count 0 2006.257.09:51:28.21#ibcon#*after write, iclass 29, count 0 2006.257.09:51:28.21#ibcon#*before return 0, iclass 29, count 0 2006.257.09:51:28.21#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:28.21#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.09:51:28.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.09:51:28.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.09:51:28.21$vck44/vblo=5,709.99 2006.257.09:51:28.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.09:51:28.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.09:51:28.21#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:28.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:28.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:28.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:28.21#ibcon#enter wrdev, iclass 31, count 0 2006.257.09:51:28.21#ibcon#first serial, iclass 31, count 0 2006.257.09:51:28.21#ibcon#enter sib2, iclass 31, count 0 2006.257.09:51:28.21#ibcon#flushed, iclass 31, count 0 2006.257.09:51:28.21#ibcon#about to write, iclass 31, count 0 2006.257.09:51:28.21#ibcon#wrote, iclass 31, count 0 2006.257.09:51:28.21#ibcon#about to read 3, iclass 31, count 0 2006.257.09:51:28.23#ibcon#read 3, iclass 31, count 0 2006.257.09:51:28.23#ibcon#about to read 4, iclass 31, count 0 2006.257.09:51:28.23#ibcon#read 4, iclass 31, count 0 2006.257.09:51:28.23#ibcon#about to read 5, iclass 31, count 0 2006.257.09:51:28.23#ibcon#read 5, iclass 31, count 0 2006.257.09:51:28.23#ibcon#about to read 6, iclass 31, count 0 2006.257.09:51:28.23#ibcon#read 6, iclass 31, count 0 2006.257.09:51:28.23#ibcon#end of sib2, iclass 31, count 0 2006.257.09:51:28.23#ibcon#*mode == 0, iclass 31, count 0 2006.257.09:51:28.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.09:51:28.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:51:28.23#ibcon#*before write, iclass 31, count 0 2006.257.09:51:28.23#ibcon#enter sib2, iclass 31, count 0 2006.257.09:51:28.23#ibcon#flushed, iclass 31, count 0 2006.257.09:51:28.23#ibcon#about to write, iclass 31, count 0 2006.257.09:51:28.23#ibcon#wrote, iclass 31, count 0 2006.257.09:51:28.23#ibcon#about to read 3, iclass 31, count 0 2006.257.09:51:28.27#ibcon#read 3, iclass 31, count 0 2006.257.09:51:28.27#ibcon#about to read 4, iclass 31, count 0 2006.257.09:51:28.27#ibcon#read 4, iclass 31, count 0 2006.257.09:51:28.27#ibcon#about to read 5, iclass 31, count 0 2006.257.09:51:28.27#ibcon#read 5, iclass 31, count 0 2006.257.09:51:28.27#ibcon#about to read 6, iclass 31, count 0 2006.257.09:51:28.27#ibcon#read 6, iclass 31, count 0 2006.257.09:51:28.27#ibcon#end of sib2, iclass 31, count 0 2006.257.09:51:28.27#ibcon#*after write, iclass 31, count 0 2006.257.09:51:28.27#ibcon#*before return 0, iclass 31, count 0 2006.257.09:51:28.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:28.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.09:51:28.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.09:51:28.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.09:51:28.27$vck44/vb=5,4 2006.257.09:51:28.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.09:51:28.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.09:51:28.27#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:28.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:28.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:28.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:28.33#ibcon#enter wrdev, iclass 33, count 2 2006.257.09:51:28.33#ibcon#first serial, iclass 33, count 2 2006.257.09:51:28.33#ibcon#enter sib2, iclass 33, count 2 2006.257.09:51:28.33#ibcon#flushed, iclass 33, count 2 2006.257.09:51:28.33#ibcon#about to write, iclass 33, count 2 2006.257.09:51:28.33#ibcon#wrote, iclass 33, count 2 2006.257.09:51:28.33#ibcon#about to read 3, iclass 33, count 2 2006.257.09:51:28.35#ibcon#read 3, iclass 33, count 2 2006.257.09:51:28.35#ibcon#about to read 4, iclass 33, count 2 2006.257.09:51:28.35#ibcon#read 4, iclass 33, count 2 2006.257.09:51:28.35#ibcon#about to read 5, iclass 33, count 2 2006.257.09:51:28.35#ibcon#read 5, iclass 33, count 2 2006.257.09:51:28.35#ibcon#about to read 6, iclass 33, count 2 2006.257.09:51:28.35#ibcon#read 6, iclass 33, count 2 2006.257.09:51:28.35#ibcon#end of sib2, iclass 33, count 2 2006.257.09:51:28.35#ibcon#*mode == 0, iclass 33, count 2 2006.257.09:51:28.35#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.09:51:28.35#ibcon#[27=AT05-04\r\n] 2006.257.09:51:28.35#ibcon#*before write, iclass 33, count 2 2006.257.09:51:28.35#ibcon#enter sib2, iclass 33, count 2 2006.257.09:51:28.35#ibcon#flushed, iclass 33, count 2 2006.257.09:51:28.35#ibcon#about to write, iclass 33, count 2 2006.257.09:51:28.35#ibcon#wrote, iclass 33, count 2 2006.257.09:51:28.35#ibcon#about to read 3, iclass 33, count 2 2006.257.09:51:28.38#ibcon#read 3, iclass 33, count 2 2006.257.09:51:28.38#ibcon#about to read 4, iclass 33, count 2 2006.257.09:51:28.38#ibcon#read 4, iclass 33, count 2 2006.257.09:51:28.38#ibcon#about to read 5, iclass 33, count 2 2006.257.09:51:28.38#ibcon#read 5, iclass 33, count 2 2006.257.09:51:28.38#ibcon#about to read 6, iclass 33, count 2 2006.257.09:51:28.38#ibcon#read 6, iclass 33, count 2 2006.257.09:51:28.38#ibcon#end of sib2, iclass 33, count 2 2006.257.09:51:28.38#ibcon#*after write, iclass 33, count 2 2006.257.09:51:28.38#ibcon#*before return 0, iclass 33, count 2 2006.257.09:51:28.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:28.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.09:51:28.38#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.09:51:28.38#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:28.38#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:28.50#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:28.50#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:28.50#ibcon#enter wrdev, iclass 33, count 0 2006.257.09:51:28.50#ibcon#first serial, iclass 33, count 0 2006.257.09:51:28.50#ibcon#enter sib2, iclass 33, count 0 2006.257.09:51:28.50#ibcon#flushed, iclass 33, count 0 2006.257.09:51:28.50#ibcon#about to write, iclass 33, count 0 2006.257.09:51:28.50#ibcon#wrote, iclass 33, count 0 2006.257.09:51:28.50#ibcon#about to read 3, iclass 33, count 0 2006.257.09:51:28.52#ibcon#read 3, iclass 33, count 0 2006.257.09:51:28.52#ibcon#about to read 4, iclass 33, count 0 2006.257.09:51:28.52#ibcon#read 4, iclass 33, count 0 2006.257.09:51:28.52#ibcon#about to read 5, iclass 33, count 0 2006.257.09:51:28.52#ibcon#read 5, iclass 33, count 0 2006.257.09:51:28.52#ibcon#about to read 6, iclass 33, count 0 2006.257.09:51:28.52#ibcon#read 6, iclass 33, count 0 2006.257.09:51:28.52#ibcon#end of sib2, iclass 33, count 0 2006.257.09:51:28.52#ibcon#*mode == 0, iclass 33, count 0 2006.257.09:51:28.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.09:51:28.52#ibcon#[27=USB\r\n] 2006.257.09:51:28.52#ibcon#*before write, iclass 33, count 0 2006.257.09:51:28.52#ibcon#enter sib2, iclass 33, count 0 2006.257.09:51:28.52#ibcon#flushed, iclass 33, count 0 2006.257.09:51:28.52#ibcon#about to write, iclass 33, count 0 2006.257.09:51:28.52#ibcon#wrote, iclass 33, count 0 2006.257.09:51:28.52#ibcon#about to read 3, iclass 33, count 0 2006.257.09:51:28.55#ibcon#read 3, iclass 33, count 0 2006.257.09:51:28.55#ibcon#about to read 4, iclass 33, count 0 2006.257.09:51:28.55#ibcon#read 4, iclass 33, count 0 2006.257.09:51:28.55#ibcon#about to read 5, iclass 33, count 0 2006.257.09:51:28.55#ibcon#read 5, iclass 33, count 0 2006.257.09:51:28.55#ibcon#about to read 6, iclass 33, count 0 2006.257.09:51:28.55#ibcon#read 6, iclass 33, count 0 2006.257.09:51:28.55#ibcon#end of sib2, iclass 33, count 0 2006.257.09:51:28.55#ibcon#*after write, iclass 33, count 0 2006.257.09:51:28.55#ibcon#*before return 0, iclass 33, count 0 2006.257.09:51:28.55#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:28.55#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.09:51:28.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.09:51:28.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.09:51:28.55$vck44/vblo=6,719.99 2006.257.09:51:28.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.09:51:28.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.09:51:28.55#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:28.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:28.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:28.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:28.55#ibcon#enter wrdev, iclass 35, count 0 2006.257.09:51:28.55#ibcon#first serial, iclass 35, count 0 2006.257.09:51:28.55#ibcon#enter sib2, iclass 35, count 0 2006.257.09:51:28.55#ibcon#flushed, iclass 35, count 0 2006.257.09:51:28.55#ibcon#about to write, iclass 35, count 0 2006.257.09:51:28.55#ibcon#wrote, iclass 35, count 0 2006.257.09:51:28.55#ibcon#about to read 3, iclass 35, count 0 2006.257.09:51:28.57#ibcon#read 3, iclass 35, count 0 2006.257.09:51:28.57#ibcon#about to read 4, iclass 35, count 0 2006.257.09:51:28.57#ibcon#read 4, iclass 35, count 0 2006.257.09:51:28.57#ibcon#about to read 5, iclass 35, count 0 2006.257.09:51:28.57#ibcon#read 5, iclass 35, count 0 2006.257.09:51:28.57#ibcon#about to read 6, iclass 35, count 0 2006.257.09:51:28.57#ibcon#read 6, iclass 35, count 0 2006.257.09:51:28.57#ibcon#end of sib2, iclass 35, count 0 2006.257.09:51:28.57#ibcon#*mode == 0, iclass 35, count 0 2006.257.09:51:28.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.09:51:28.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:51:28.57#ibcon#*before write, iclass 35, count 0 2006.257.09:51:28.57#ibcon#enter sib2, iclass 35, count 0 2006.257.09:51:28.57#ibcon#flushed, iclass 35, count 0 2006.257.09:51:28.57#ibcon#about to write, iclass 35, count 0 2006.257.09:51:28.57#ibcon#wrote, iclass 35, count 0 2006.257.09:51:28.57#ibcon#about to read 3, iclass 35, count 0 2006.257.09:51:28.61#ibcon#read 3, iclass 35, count 0 2006.257.09:51:28.61#ibcon#about to read 4, iclass 35, count 0 2006.257.09:51:28.61#ibcon#read 4, iclass 35, count 0 2006.257.09:51:28.61#ibcon#about to read 5, iclass 35, count 0 2006.257.09:51:28.61#ibcon#read 5, iclass 35, count 0 2006.257.09:51:28.61#ibcon#about to read 6, iclass 35, count 0 2006.257.09:51:28.61#ibcon#read 6, iclass 35, count 0 2006.257.09:51:28.61#ibcon#end of sib2, iclass 35, count 0 2006.257.09:51:28.61#ibcon#*after write, iclass 35, count 0 2006.257.09:51:28.61#ibcon#*before return 0, iclass 35, count 0 2006.257.09:51:28.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:28.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.09:51:28.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.09:51:28.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.09:51:28.61$vck44/vb=6,4 2006.257.09:51:28.61#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.09:51:28.61#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.09:51:28.61#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:28.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:28.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:28.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:28.67#ibcon#enter wrdev, iclass 37, count 2 2006.257.09:51:28.67#ibcon#first serial, iclass 37, count 2 2006.257.09:51:28.67#ibcon#enter sib2, iclass 37, count 2 2006.257.09:51:28.67#ibcon#flushed, iclass 37, count 2 2006.257.09:51:28.67#ibcon#about to write, iclass 37, count 2 2006.257.09:51:28.67#ibcon#wrote, iclass 37, count 2 2006.257.09:51:28.67#ibcon#about to read 3, iclass 37, count 2 2006.257.09:51:28.69#ibcon#read 3, iclass 37, count 2 2006.257.09:51:28.69#ibcon#about to read 4, iclass 37, count 2 2006.257.09:51:28.69#ibcon#read 4, iclass 37, count 2 2006.257.09:51:28.69#ibcon#about to read 5, iclass 37, count 2 2006.257.09:51:28.69#ibcon#read 5, iclass 37, count 2 2006.257.09:51:28.69#ibcon#about to read 6, iclass 37, count 2 2006.257.09:51:28.69#ibcon#read 6, iclass 37, count 2 2006.257.09:51:28.69#ibcon#end of sib2, iclass 37, count 2 2006.257.09:51:28.69#ibcon#*mode == 0, iclass 37, count 2 2006.257.09:51:28.69#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.09:51:28.69#ibcon#[27=AT06-04\r\n] 2006.257.09:51:28.69#ibcon#*before write, iclass 37, count 2 2006.257.09:51:28.69#ibcon#enter sib2, iclass 37, count 2 2006.257.09:51:28.69#ibcon#flushed, iclass 37, count 2 2006.257.09:51:28.69#ibcon#about to write, iclass 37, count 2 2006.257.09:51:28.69#ibcon#wrote, iclass 37, count 2 2006.257.09:51:28.69#ibcon#about to read 3, iclass 37, count 2 2006.257.09:51:28.72#ibcon#read 3, iclass 37, count 2 2006.257.09:51:28.72#ibcon#about to read 4, iclass 37, count 2 2006.257.09:51:28.72#ibcon#read 4, iclass 37, count 2 2006.257.09:51:28.72#ibcon#about to read 5, iclass 37, count 2 2006.257.09:51:28.72#ibcon#read 5, iclass 37, count 2 2006.257.09:51:28.72#ibcon#about to read 6, iclass 37, count 2 2006.257.09:51:28.72#ibcon#read 6, iclass 37, count 2 2006.257.09:51:28.72#ibcon#end of sib2, iclass 37, count 2 2006.257.09:51:28.72#ibcon#*after write, iclass 37, count 2 2006.257.09:51:28.72#ibcon#*before return 0, iclass 37, count 2 2006.257.09:51:28.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:28.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.09:51:28.72#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.09:51:28.72#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:28.72#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:28.84#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:28.84#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:28.84#ibcon#enter wrdev, iclass 37, count 0 2006.257.09:51:28.84#ibcon#first serial, iclass 37, count 0 2006.257.09:51:28.84#ibcon#enter sib2, iclass 37, count 0 2006.257.09:51:28.84#ibcon#flushed, iclass 37, count 0 2006.257.09:51:28.84#ibcon#about to write, iclass 37, count 0 2006.257.09:51:28.84#ibcon#wrote, iclass 37, count 0 2006.257.09:51:28.84#ibcon#about to read 3, iclass 37, count 0 2006.257.09:51:28.86#ibcon#read 3, iclass 37, count 0 2006.257.09:51:28.86#ibcon#about to read 4, iclass 37, count 0 2006.257.09:51:28.86#ibcon#read 4, iclass 37, count 0 2006.257.09:51:28.86#ibcon#about to read 5, iclass 37, count 0 2006.257.09:51:28.86#ibcon#read 5, iclass 37, count 0 2006.257.09:51:28.86#ibcon#about to read 6, iclass 37, count 0 2006.257.09:51:28.86#ibcon#read 6, iclass 37, count 0 2006.257.09:51:28.86#ibcon#end of sib2, iclass 37, count 0 2006.257.09:51:28.86#ibcon#*mode == 0, iclass 37, count 0 2006.257.09:51:28.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.09:51:28.86#ibcon#[27=USB\r\n] 2006.257.09:51:28.86#ibcon#*before write, iclass 37, count 0 2006.257.09:51:28.86#ibcon#enter sib2, iclass 37, count 0 2006.257.09:51:28.86#ibcon#flushed, iclass 37, count 0 2006.257.09:51:28.86#ibcon#about to write, iclass 37, count 0 2006.257.09:51:28.86#ibcon#wrote, iclass 37, count 0 2006.257.09:51:28.86#ibcon#about to read 3, iclass 37, count 0 2006.257.09:51:28.89#ibcon#read 3, iclass 37, count 0 2006.257.09:51:28.89#ibcon#about to read 4, iclass 37, count 0 2006.257.09:51:28.89#ibcon#read 4, iclass 37, count 0 2006.257.09:51:28.89#ibcon#about to read 5, iclass 37, count 0 2006.257.09:51:28.89#ibcon#read 5, iclass 37, count 0 2006.257.09:51:28.89#ibcon#about to read 6, iclass 37, count 0 2006.257.09:51:28.89#ibcon#read 6, iclass 37, count 0 2006.257.09:51:28.89#ibcon#end of sib2, iclass 37, count 0 2006.257.09:51:28.89#ibcon#*after write, iclass 37, count 0 2006.257.09:51:28.89#ibcon#*before return 0, iclass 37, count 0 2006.257.09:51:28.89#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:28.89#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.09:51:28.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.09:51:28.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.09:51:28.89$vck44/vblo=7,734.99 2006.257.09:51:28.89#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.09:51:28.89#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.09:51:28.89#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:28.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:28.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:28.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:28.89#ibcon#enter wrdev, iclass 39, count 0 2006.257.09:51:28.89#ibcon#first serial, iclass 39, count 0 2006.257.09:51:28.89#ibcon#enter sib2, iclass 39, count 0 2006.257.09:51:28.89#ibcon#flushed, iclass 39, count 0 2006.257.09:51:28.89#ibcon#about to write, iclass 39, count 0 2006.257.09:51:28.89#ibcon#wrote, iclass 39, count 0 2006.257.09:51:28.89#ibcon#about to read 3, iclass 39, count 0 2006.257.09:51:28.91#ibcon#read 3, iclass 39, count 0 2006.257.09:51:28.91#ibcon#about to read 4, iclass 39, count 0 2006.257.09:51:28.91#ibcon#read 4, iclass 39, count 0 2006.257.09:51:28.91#ibcon#about to read 5, iclass 39, count 0 2006.257.09:51:28.91#ibcon#read 5, iclass 39, count 0 2006.257.09:51:28.91#ibcon#about to read 6, iclass 39, count 0 2006.257.09:51:28.91#ibcon#read 6, iclass 39, count 0 2006.257.09:51:28.91#ibcon#end of sib2, iclass 39, count 0 2006.257.09:51:28.91#ibcon#*mode == 0, iclass 39, count 0 2006.257.09:51:28.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.09:51:28.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:51:28.91#ibcon#*before write, iclass 39, count 0 2006.257.09:51:28.91#ibcon#enter sib2, iclass 39, count 0 2006.257.09:51:28.91#ibcon#flushed, iclass 39, count 0 2006.257.09:51:28.91#ibcon#about to write, iclass 39, count 0 2006.257.09:51:28.91#ibcon#wrote, iclass 39, count 0 2006.257.09:51:28.91#ibcon#about to read 3, iclass 39, count 0 2006.257.09:51:28.95#ibcon#read 3, iclass 39, count 0 2006.257.09:51:28.95#ibcon#about to read 4, iclass 39, count 0 2006.257.09:51:28.95#ibcon#read 4, iclass 39, count 0 2006.257.09:51:28.95#ibcon#about to read 5, iclass 39, count 0 2006.257.09:51:28.95#ibcon#read 5, iclass 39, count 0 2006.257.09:51:28.95#ibcon#about to read 6, iclass 39, count 0 2006.257.09:51:28.95#ibcon#read 6, iclass 39, count 0 2006.257.09:51:28.95#ibcon#end of sib2, iclass 39, count 0 2006.257.09:51:28.95#ibcon#*after write, iclass 39, count 0 2006.257.09:51:28.95#ibcon#*before return 0, iclass 39, count 0 2006.257.09:51:28.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:28.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.09:51:28.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.09:51:28.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.09:51:28.95$vck44/vb=7,4 2006.257.09:51:28.95#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.09:51:28.95#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.09:51:28.95#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:28.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:29.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:29.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:29.01#ibcon#enter wrdev, iclass 3, count 2 2006.257.09:51:29.01#ibcon#first serial, iclass 3, count 2 2006.257.09:51:29.01#ibcon#enter sib2, iclass 3, count 2 2006.257.09:51:29.01#ibcon#flushed, iclass 3, count 2 2006.257.09:51:29.01#ibcon#about to write, iclass 3, count 2 2006.257.09:51:29.01#ibcon#wrote, iclass 3, count 2 2006.257.09:51:29.01#ibcon#about to read 3, iclass 3, count 2 2006.257.09:51:29.03#ibcon#read 3, iclass 3, count 2 2006.257.09:51:29.03#ibcon#about to read 4, iclass 3, count 2 2006.257.09:51:29.03#ibcon#read 4, iclass 3, count 2 2006.257.09:51:29.03#ibcon#about to read 5, iclass 3, count 2 2006.257.09:51:29.03#ibcon#read 5, iclass 3, count 2 2006.257.09:51:29.03#ibcon#about to read 6, iclass 3, count 2 2006.257.09:51:29.03#ibcon#read 6, iclass 3, count 2 2006.257.09:51:29.03#ibcon#end of sib2, iclass 3, count 2 2006.257.09:51:29.03#ibcon#*mode == 0, iclass 3, count 2 2006.257.09:51:29.03#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.09:51:29.03#ibcon#[27=AT07-04\r\n] 2006.257.09:51:29.03#ibcon#*before write, iclass 3, count 2 2006.257.09:51:29.03#ibcon#enter sib2, iclass 3, count 2 2006.257.09:51:29.03#ibcon#flushed, iclass 3, count 2 2006.257.09:51:29.03#ibcon#about to write, iclass 3, count 2 2006.257.09:51:29.03#ibcon#wrote, iclass 3, count 2 2006.257.09:51:29.03#ibcon#about to read 3, iclass 3, count 2 2006.257.09:51:29.06#ibcon#read 3, iclass 3, count 2 2006.257.09:51:29.06#ibcon#about to read 4, iclass 3, count 2 2006.257.09:51:29.06#ibcon#read 4, iclass 3, count 2 2006.257.09:51:29.06#ibcon#about to read 5, iclass 3, count 2 2006.257.09:51:29.06#ibcon#read 5, iclass 3, count 2 2006.257.09:51:29.06#ibcon#about to read 6, iclass 3, count 2 2006.257.09:51:29.06#ibcon#read 6, iclass 3, count 2 2006.257.09:51:29.06#ibcon#end of sib2, iclass 3, count 2 2006.257.09:51:29.06#ibcon#*after write, iclass 3, count 2 2006.257.09:51:29.06#ibcon#*before return 0, iclass 3, count 2 2006.257.09:51:29.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:29.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.09:51:29.06#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.09:51:29.06#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:29.06#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:29.18#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:29.18#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:29.18#ibcon#enter wrdev, iclass 3, count 0 2006.257.09:51:29.18#ibcon#first serial, iclass 3, count 0 2006.257.09:51:29.18#ibcon#enter sib2, iclass 3, count 0 2006.257.09:51:29.18#ibcon#flushed, iclass 3, count 0 2006.257.09:51:29.18#ibcon#about to write, iclass 3, count 0 2006.257.09:51:29.18#ibcon#wrote, iclass 3, count 0 2006.257.09:51:29.18#ibcon#about to read 3, iclass 3, count 0 2006.257.09:51:29.20#ibcon#read 3, iclass 3, count 0 2006.257.09:51:29.20#ibcon#about to read 4, iclass 3, count 0 2006.257.09:51:29.20#ibcon#read 4, iclass 3, count 0 2006.257.09:51:29.20#ibcon#about to read 5, iclass 3, count 0 2006.257.09:51:29.20#ibcon#read 5, iclass 3, count 0 2006.257.09:51:29.20#ibcon#about to read 6, iclass 3, count 0 2006.257.09:51:29.20#ibcon#read 6, iclass 3, count 0 2006.257.09:51:29.20#ibcon#end of sib2, iclass 3, count 0 2006.257.09:51:29.20#ibcon#*mode == 0, iclass 3, count 0 2006.257.09:51:29.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.09:51:29.20#ibcon#[27=USB\r\n] 2006.257.09:51:29.20#ibcon#*before write, iclass 3, count 0 2006.257.09:51:29.20#ibcon#enter sib2, iclass 3, count 0 2006.257.09:51:29.20#ibcon#flushed, iclass 3, count 0 2006.257.09:51:29.20#ibcon#about to write, iclass 3, count 0 2006.257.09:51:29.20#ibcon#wrote, iclass 3, count 0 2006.257.09:51:29.20#ibcon#about to read 3, iclass 3, count 0 2006.257.09:51:29.23#ibcon#read 3, iclass 3, count 0 2006.257.09:51:29.23#ibcon#about to read 4, iclass 3, count 0 2006.257.09:51:29.23#ibcon#read 4, iclass 3, count 0 2006.257.09:51:29.23#ibcon#about to read 5, iclass 3, count 0 2006.257.09:51:29.23#ibcon#read 5, iclass 3, count 0 2006.257.09:51:29.23#ibcon#about to read 6, iclass 3, count 0 2006.257.09:51:29.23#ibcon#read 6, iclass 3, count 0 2006.257.09:51:29.23#ibcon#end of sib2, iclass 3, count 0 2006.257.09:51:29.23#ibcon#*after write, iclass 3, count 0 2006.257.09:51:29.23#ibcon#*before return 0, iclass 3, count 0 2006.257.09:51:29.23#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:29.23#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.09:51:29.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.09:51:29.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.09:51:29.23$vck44/vblo=8,744.99 2006.257.09:51:29.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.09:51:29.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.09:51:29.23#ibcon#ireg 17 cls_cnt 0 2006.257.09:51:29.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:29.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:29.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:29.23#ibcon#enter wrdev, iclass 5, count 0 2006.257.09:51:29.23#ibcon#first serial, iclass 5, count 0 2006.257.09:51:29.23#ibcon#enter sib2, iclass 5, count 0 2006.257.09:51:29.23#ibcon#flushed, iclass 5, count 0 2006.257.09:51:29.23#ibcon#about to write, iclass 5, count 0 2006.257.09:51:29.23#ibcon#wrote, iclass 5, count 0 2006.257.09:51:29.23#ibcon#about to read 3, iclass 5, count 0 2006.257.09:51:29.25#ibcon#read 3, iclass 5, count 0 2006.257.09:51:29.25#ibcon#about to read 4, iclass 5, count 0 2006.257.09:51:29.25#ibcon#read 4, iclass 5, count 0 2006.257.09:51:29.25#ibcon#about to read 5, iclass 5, count 0 2006.257.09:51:29.25#ibcon#read 5, iclass 5, count 0 2006.257.09:51:29.25#ibcon#about to read 6, iclass 5, count 0 2006.257.09:51:29.25#ibcon#read 6, iclass 5, count 0 2006.257.09:51:29.25#ibcon#end of sib2, iclass 5, count 0 2006.257.09:51:29.25#ibcon#*mode == 0, iclass 5, count 0 2006.257.09:51:29.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.09:51:29.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:51:29.25#ibcon#*before write, iclass 5, count 0 2006.257.09:51:29.25#ibcon#enter sib2, iclass 5, count 0 2006.257.09:51:29.25#ibcon#flushed, iclass 5, count 0 2006.257.09:51:29.25#ibcon#about to write, iclass 5, count 0 2006.257.09:51:29.25#ibcon#wrote, iclass 5, count 0 2006.257.09:51:29.25#ibcon#about to read 3, iclass 5, count 0 2006.257.09:51:29.29#ibcon#read 3, iclass 5, count 0 2006.257.09:51:29.29#ibcon#about to read 4, iclass 5, count 0 2006.257.09:51:29.29#ibcon#read 4, iclass 5, count 0 2006.257.09:51:29.29#ibcon#about to read 5, iclass 5, count 0 2006.257.09:51:29.29#ibcon#read 5, iclass 5, count 0 2006.257.09:51:29.29#ibcon#about to read 6, iclass 5, count 0 2006.257.09:51:29.29#ibcon#read 6, iclass 5, count 0 2006.257.09:51:29.29#ibcon#end of sib2, iclass 5, count 0 2006.257.09:51:29.29#ibcon#*after write, iclass 5, count 0 2006.257.09:51:29.29#ibcon#*before return 0, iclass 5, count 0 2006.257.09:51:29.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:29.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.09:51:29.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.09:51:29.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.09:51:29.29$vck44/vb=8,4 2006.257.09:51:29.29#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.09:51:29.29#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.09:51:29.29#ibcon#ireg 11 cls_cnt 2 2006.257.09:51:29.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:29.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:29.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:29.35#ibcon#enter wrdev, iclass 7, count 2 2006.257.09:51:29.35#ibcon#first serial, iclass 7, count 2 2006.257.09:51:29.35#ibcon#enter sib2, iclass 7, count 2 2006.257.09:51:29.35#ibcon#flushed, iclass 7, count 2 2006.257.09:51:29.35#ibcon#about to write, iclass 7, count 2 2006.257.09:51:29.35#ibcon#wrote, iclass 7, count 2 2006.257.09:51:29.35#ibcon#about to read 3, iclass 7, count 2 2006.257.09:51:29.37#ibcon#read 3, iclass 7, count 2 2006.257.09:51:29.37#ibcon#about to read 4, iclass 7, count 2 2006.257.09:51:29.37#ibcon#read 4, iclass 7, count 2 2006.257.09:51:29.37#ibcon#about to read 5, iclass 7, count 2 2006.257.09:51:29.37#ibcon#read 5, iclass 7, count 2 2006.257.09:51:29.37#ibcon#about to read 6, iclass 7, count 2 2006.257.09:51:29.37#ibcon#read 6, iclass 7, count 2 2006.257.09:51:29.37#ibcon#end of sib2, iclass 7, count 2 2006.257.09:51:29.37#ibcon#*mode == 0, iclass 7, count 2 2006.257.09:51:29.37#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.09:51:29.37#ibcon#[27=AT08-04\r\n] 2006.257.09:51:29.37#ibcon#*before write, iclass 7, count 2 2006.257.09:51:29.37#ibcon#enter sib2, iclass 7, count 2 2006.257.09:51:29.37#ibcon#flushed, iclass 7, count 2 2006.257.09:51:29.37#ibcon#about to write, iclass 7, count 2 2006.257.09:51:29.37#ibcon#wrote, iclass 7, count 2 2006.257.09:51:29.37#ibcon#about to read 3, iclass 7, count 2 2006.257.09:51:29.40#ibcon#read 3, iclass 7, count 2 2006.257.09:51:29.40#ibcon#about to read 4, iclass 7, count 2 2006.257.09:51:29.40#ibcon#read 4, iclass 7, count 2 2006.257.09:51:29.40#ibcon#about to read 5, iclass 7, count 2 2006.257.09:51:29.40#ibcon#read 5, iclass 7, count 2 2006.257.09:51:29.40#ibcon#about to read 6, iclass 7, count 2 2006.257.09:51:29.40#ibcon#read 6, iclass 7, count 2 2006.257.09:51:29.40#ibcon#end of sib2, iclass 7, count 2 2006.257.09:51:29.40#ibcon#*after write, iclass 7, count 2 2006.257.09:51:29.40#ibcon#*before return 0, iclass 7, count 2 2006.257.09:51:29.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:29.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.09:51:29.44#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.09:51:29.44#ibcon#ireg 7 cls_cnt 0 2006.257.09:51:29.44#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:29.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:29.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:29.52#ibcon#enter wrdev, iclass 7, count 0 2006.257.09:51:29.52#ibcon#first serial, iclass 7, count 0 2006.257.09:51:29.52#ibcon#enter sib2, iclass 7, count 0 2006.257.09:51:29.52#ibcon#flushed, iclass 7, count 0 2006.257.09:51:29.52#ibcon#about to write, iclass 7, count 0 2006.257.09:51:29.52#ibcon#wrote, iclass 7, count 0 2006.257.09:51:29.52#ibcon#about to read 3, iclass 7, count 0 2006.257.09:51:29.54#ibcon#read 3, iclass 7, count 0 2006.257.09:51:29.54#ibcon#about to read 4, iclass 7, count 0 2006.257.09:51:29.54#ibcon#read 4, iclass 7, count 0 2006.257.09:51:29.54#ibcon#about to read 5, iclass 7, count 0 2006.257.09:51:29.54#ibcon#read 5, iclass 7, count 0 2006.257.09:51:29.54#ibcon#about to read 6, iclass 7, count 0 2006.257.09:51:29.54#ibcon#read 6, iclass 7, count 0 2006.257.09:51:29.54#ibcon#end of sib2, iclass 7, count 0 2006.257.09:51:29.54#ibcon#*mode == 0, iclass 7, count 0 2006.257.09:51:29.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.09:51:29.54#ibcon#[27=USB\r\n] 2006.257.09:51:29.54#ibcon#*before write, iclass 7, count 0 2006.257.09:51:29.54#ibcon#enter sib2, iclass 7, count 0 2006.257.09:51:29.54#ibcon#flushed, iclass 7, count 0 2006.257.09:51:29.54#ibcon#about to write, iclass 7, count 0 2006.257.09:51:29.54#ibcon#wrote, iclass 7, count 0 2006.257.09:51:29.54#ibcon#about to read 3, iclass 7, count 0 2006.257.09:51:29.57#ibcon#read 3, iclass 7, count 0 2006.257.09:51:29.57#ibcon#about to read 4, iclass 7, count 0 2006.257.09:51:29.57#ibcon#read 4, iclass 7, count 0 2006.257.09:51:29.57#ibcon#about to read 5, iclass 7, count 0 2006.257.09:51:29.57#ibcon#read 5, iclass 7, count 0 2006.257.09:51:29.57#ibcon#about to read 6, iclass 7, count 0 2006.257.09:51:29.57#ibcon#read 6, iclass 7, count 0 2006.257.09:51:29.57#ibcon#end of sib2, iclass 7, count 0 2006.257.09:51:29.57#ibcon#*after write, iclass 7, count 0 2006.257.09:51:29.57#ibcon#*before return 0, iclass 7, count 0 2006.257.09:51:29.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:29.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.09:51:29.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.09:51:29.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.09:51:29.57$vck44/vabw=wide 2006.257.09:51:29.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.09:51:29.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.09:51:29.57#ibcon#ireg 8 cls_cnt 0 2006.257.09:51:29.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:29.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:29.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:29.57#ibcon#enter wrdev, iclass 11, count 0 2006.257.09:51:29.57#ibcon#first serial, iclass 11, count 0 2006.257.09:51:29.57#ibcon#enter sib2, iclass 11, count 0 2006.257.09:51:29.57#ibcon#flushed, iclass 11, count 0 2006.257.09:51:29.57#ibcon#about to write, iclass 11, count 0 2006.257.09:51:29.57#ibcon#wrote, iclass 11, count 0 2006.257.09:51:29.57#ibcon#about to read 3, iclass 11, count 0 2006.257.09:51:29.59#ibcon#read 3, iclass 11, count 0 2006.257.09:51:29.59#ibcon#about to read 4, iclass 11, count 0 2006.257.09:51:29.59#ibcon#read 4, iclass 11, count 0 2006.257.09:51:29.59#ibcon#about to read 5, iclass 11, count 0 2006.257.09:51:29.59#ibcon#read 5, iclass 11, count 0 2006.257.09:51:29.59#ibcon#about to read 6, iclass 11, count 0 2006.257.09:51:29.59#ibcon#read 6, iclass 11, count 0 2006.257.09:51:29.59#ibcon#end of sib2, iclass 11, count 0 2006.257.09:51:29.59#ibcon#*mode == 0, iclass 11, count 0 2006.257.09:51:29.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.09:51:29.59#ibcon#[25=BW32\r\n] 2006.257.09:51:29.59#ibcon#*before write, iclass 11, count 0 2006.257.09:51:29.59#ibcon#enter sib2, iclass 11, count 0 2006.257.09:51:29.59#ibcon#flushed, iclass 11, count 0 2006.257.09:51:29.59#ibcon#about to write, iclass 11, count 0 2006.257.09:51:29.59#ibcon#wrote, iclass 11, count 0 2006.257.09:51:29.59#ibcon#about to read 3, iclass 11, count 0 2006.257.09:51:29.62#ibcon#read 3, iclass 11, count 0 2006.257.09:51:29.62#ibcon#about to read 4, iclass 11, count 0 2006.257.09:51:29.62#ibcon#read 4, iclass 11, count 0 2006.257.09:51:29.62#ibcon#about to read 5, iclass 11, count 0 2006.257.09:51:29.62#ibcon#read 5, iclass 11, count 0 2006.257.09:51:29.62#ibcon#about to read 6, iclass 11, count 0 2006.257.09:51:29.62#ibcon#read 6, iclass 11, count 0 2006.257.09:51:29.62#ibcon#end of sib2, iclass 11, count 0 2006.257.09:51:29.62#ibcon#*after write, iclass 11, count 0 2006.257.09:51:29.62#ibcon#*before return 0, iclass 11, count 0 2006.257.09:51:29.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:29.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.09:51:29.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.09:51:29.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.09:51:29.62$vck44/vbbw=wide 2006.257.09:51:29.62#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.09:51:29.62#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.09:51:29.62#ibcon#ireg 8 cls_cnt 0 2006.257.09:51:29.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:51:29.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:51:29.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:51:29.69#ibcon#enter wrdev, iclass 13, count 0 2006.257.09:51:29.69#ibcon#first serial, iclass 13, count 0 2006.257.09:51:29.69#ibcon#enter sib2, iclass 13, count 0 2006.257.09:51:29.69#ibcon#flushed, iclass 13, count 0 2006.257.09:51:29.69#ibcon#about to write, iclass 13, count 0 2006.257.09:51:29.69#ibcon#wrote, iclass 13, count 0 2006.257.09:51:29.69#ibcon#about to read 3, iclass 13, count 0 2006.257.09:51:29.71#ibcon#read 3, iclass 13, count 0 2006.257.09:51:29.71#ibcon#about to read 4, iclass 13, count 0 2006.257.09:51:29.71#ibcon#read 4, iclass 13, count 0 2006.257.09:51:29.71#ibcon#about to read 5, iclass 13, count 0 2006.257.09:51:29.71#ibcon#read 5, iclass 13, count 0 2006.257.09:51:29.71#ibcon#about to read 6, iclass 13, count 0 2006.257.09:51:29.71#ibcon#read 6, iclass 13, count 0 2006.257.09:51:29.71#ibcon#end of sib2, iclass 13, count 0 2006.257.09:51:29.71#ibcon#*mode == 0, iclass 13, count 0 2006.257.09:51:29.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.09:51:29.71#ibcon#[27=BW32\r\n] 2006.257.09:51:29.71#ibcon#*before write, iclass 13, count 0 2006.257.09:51:29.71#ibcon#enter sib2, iclass 13, count 0 2006.257.09:51:29.71#ibcon#flushed, iclass 13, count 0 2006.257.09:51:29.71#ibcon#about to write, iclass 13, count 0 2006.257.09:51:29.71#ibcon#wrote, iclass 13, count 0 2006.257.09:51:29.71#ibcon#about to read 3, iclass 13, count 0 2006.257.09:51:29.74#ibcon#read 3, iclass 13, count 0 2006.257.09:51:29.74#ibcon#about to read 4, iclass 13, count 0 2006.257.09:51:29.74#ibcon#read 4, iclass 13, count 0 2006.257.09:51:29.74#ibcon#about to read 5, iclass 13, count 0 2006.257.09:51:29.74#ibcon#read 5, iclass 13, count 0 2006.257.09:51:29.74#ibcon#about to read 6, iclass 13, count 0 2006.257.09:51:29.74#ibcon#read 6, iclass 13, count 0 2006.257.09:51:29.74#ibcon#end of sib2, iclass 13, count 0 2006.257.09:51:29.74#ibcon#*after write, iclass 13, count 0 2006.257.09:51:29.74#ibcon#*before return 0, iclass 13, count 0 2006.257.09:51:29.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:51:29.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.09:51:29.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.09:51:29.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.09:51:29.74$setupk4/ifdk4 2006.257.09:51:29.74$ifdk4/lo= 2006.257.09:51:29.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:51:29.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:51:29.74$ifdk4/patch= 2006.257.09:51:29.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:51:29.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:51:29.74$setupk4/!*+20s 2006.257.09:51:31.93#abcon#<5=/14 0.7 1.9 19.31 961013.4\r\n> 2006.257.09:51:31.95#abcon#{5=INTERFACE CLEAR} 2006.257.09:51:32.01#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:51:42.10#abcon#<5=/14 0.7 1.9 19.31 961013.4\r\n> 2006.257.09:51:42.12#abcon#{5=INTERFACE CLEAR} 2006.257.09:51:42.18#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:51:44.12$setupk4/"tpicd 2006.257.09:51:44.12$setupk4/echo=off 2006.257.09:51:44.12$setupk4/xlog=off 2006.257.09:51:44.12:!2006.257.09:52:51 2006.257.09:51:54.14#trakl#Source acquired 2006.257.09:51:55.14#flagr#flagr/antenna,acquired 2006.257.09:52:51.00:preob 2006.257.09:52:51.14/onsource/TRACKING 2006.257.09:52:51.14:!2006.257.09:53:01 2006.257.09:53:01.00:"tape 2006.257.09:53:01.00:"st=record 2006.257.09:53:01.00:data_valid=on 2006.257.09:53:01.00:midob 2006.257.09:53:01.14/onsource/TRACKING 2006.257.09:53:01.14/wx/19.29,1013.4,96 2006.257.09:53:01.23/cable/+6.4758E-03 2006.257.09:53:02.32/va/01,08,usb,yes,32,34 2006.257.09:53:02.32/va/02,07,usb,yes,34,35 2006.257.09:53:02.32/va/03,08,usb,yes,31,32 2006.257.09:53:02.32/va/04,07,usb,yes,35,37 2006.257.09:53:02.32/va/05,04,usb,yes,32,32 2006.257.09:53:02.32/va/06,04,usb,yes,35,35 2006.257.09:53:02.32/va/07,04,usb,yes,36,37 2006.257.09:53:02.32/va/08,04,usb,yes,30,37 2006.257.09:53:02.55/valo/01,524.99,yes,locked 2006.257.09:53:02.55/valo/02,534.99,yes,locked 2006.257.09:53:02.55/valo/03,564.99,yes,locked 2006.257.09:53:02.55/valo/04,624.99,yes,locked 2006.257.09:53:02.55/valo/05,734.99,yes,locked 2006.257.09:53:02.55/valo/06,814.99,yes,locked 2006.257.09:53:02.55/valo/07,864.99,yes,locked 2006.257.09:53:02.55/valo/08,884.99,yes,locked 2006.257.09:53:03.64/vb/01,04,usb,yes,31,29 2006.257.09:53:03.64/vb/02,05,usb,yes,29,29 2006.257.09:53:03.64/vb/03,04,usb,yes,30,33 2006.257.09:53:03.64/vb/04,05,usb,yes,30,29 2006.257.09:53:03.64/vb/05,04,usb,yes,27,29 2006.257.09:53:03.64/vb/06,04,usb,yes,31,28 2006.257.09:53:03.64/vb/07,04,usb,yes,31,31 2006.257.09:53:03.64/vb/08,04,usb,yes,29,32 2006.257.09:53:03.88/vblo/01,629.99,yes,locked 2006.257.09:53:03.88/vblo/02,634.99,yes,locked 2006.257.09:53:03.88/vblo/03,649.99,yes,locked 2006.257.09:53:03.88/vblo/04,679.99,yes,locked 2006.257.09:53:03.88/vblo/05,709.99,yes,locked 2006.257.09:53:03.88/vblo/06,719.99,yes,locked 2006.257.09:53:03.88/vblo/07,734.99,yes,locked 2006.257.09:53:03.88/vblo/08,744.99,yes,locked 2006.257.09:53:04.03/vabw/8 2006.257.09:53:04.18/vbbw/8 2006.257.09:53:04.27/xfe/off,on,15.2 2006.257.09:53:04.64/ifatt/23,28,28,28 2006.257.09:53:05.07/fmout-gps/S +4.65E-07 2006.257.09:53:05.11:!2006.257.09:56:01 2006.257.09:56:01.01:data_valid=off 2006.257.09:56:01.01:"et 2006.257.09:56:01.02:!+3s 2006.257.09:56:04.03:"tape 2006.257.09:56:04.03:postob 2006.257.09:56:04.12/cable/+6.4760E-03 2006.257.09:56:04.12/wx/19.27,1013.3,96 2006.257.09:56:04.18/fmout-gps/S +4.65E-07 2006.257.09:56:04.18:scan_name=257-0958,jd0609,120 2006.257.09:56:04.19:source=0059+581,010245.76,582411.1,2000.0,cw 2006.257.09:56:05.14#flagr#flagr/antenna,new-source 2006.257.09:56:05.14:checkk5 2006.257.09:56:05.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.09:56:05.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.09:56:06.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.09:56:06.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.09:56:07.17/chk_obsdata//k5ts1/T2570953??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.257.09:56:07.57/chk_obsdata//k5ts2/T2570953??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.257.09:56:07.98/chk_obsdata//k5ts3/T2570953??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.257.09:56:08.39/chk_obsdata//k5ts4/T2570953??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.257.09:56:09.12/k5log//k5ts1_log_newline 2006.257.09:56:09.84/k5log//k5ts2_log_newline 2006.257.09:56:10.57/k5log//k5ts3_log_newline 2006.257.09:56:11.30/k5log//k5ts4_log_newline 2006.257.09:56:11.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.09:56:11.33:setupk4=1 2006.257.09:56:11.33$setupk4/echo=on 2006.257.09:56:11.33$setupk4/pcalon 2006.257.09:56:11.33$pcalon/"no phase cal control is implemented here 2006.257.09:56:11.33$setupk4/"tpicd=stop 2006.257.09:56:11.33$setupk4/"rec=synch_on 2006.257.09:56:11.33$setupk4/"rec_mode=128 2006.257.09:56:11.33$setupk4/!* 2006.257.09:56:11.33$setupk4/recpk4 2006.257.09:56:11.33$recpk4/recpatch= 2006.257.09:56:11.33$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.09:56:11.33$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.09:56:11.33$setupk4/vck44 2006.257.09:56:11.33$vck44/valo=1,524.99 2006.257.09:56:11.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.09:56:11.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.09:56:11.33#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:11.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:11.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:11.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:11.33#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:56:11.33#ibcon#first serial, iclass 22, count 0 2006.257.09:56:11.33#ibcon#enter sib2, iclass 22, count 0 2006.257.09:56:11.33#ibcon#flushed, iclass 22, count 0 2006.257.09:56:11.33#ibcon#about to write, iclass 22, count 0 2006.257.09:56:11.33#ibcon#wrote, iclass 22, count 0 2006.257.09:56:11.33#ibcon#about to read 3, iclass 22, count 0 2006.257.09:56:11.35#ibcon#read 3, iclass 22, count 0 2006.257.09:56:11.35#ibcon#about to read 4, iclass 22, count 0 2006.257.09:56:11.35#ibcon#read 4, iclass 22, count 0 2006.257.09:56:11.35#ibcon#about to read 5, iclass 22, count 0 2006.257.09:56:11.35#ibcon#read 5, iclass 22, count 0 2006.257.09:56:11.35#ibcon#about to read 6, iclass 22, count 0 2006.257.09:56:11.35#ibcon#read 6, iclass 22, count 0 2006.257.09:56:11.35#ibcon#end of sib2, iclass 22, count 0 2006.257.09:56:11.35#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:56:11.35#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:56:11.35#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.09:56:11.35#ibcon#*before write, iclass 22, count 0 2006.257.09:56:11.35#ibcon#enter sib2, iclass 22, count 0 2006.257.09:56:11.35#ibcon#flushed, iclass 22, count 0 2006.257.09:56:11.35#ibcon#about to write, iclass 22, count 0 2006.257.09:56:11.35#ibcon#wrote, iclass 22, count 0 2006.257.09:56:11.35#ibcon#about to read 3, iclass 22, count 0 2006.257.09:56:11.40#ibcon#read 3, iclass 22, count 0 2006.257.09:56:11.40#ibcon#about to read 4, iclass 22, count 0 2006.257.09:56:11.40#ibcon#read 4, iclass 22, count 0 2006.257.09:56:11.40#ibcon#about to read 5, iclass 22, count 0 2006.257.09:56:11.40#ibcon#read 5, iclass 22, count 0 2006.257.09:56:11.40#ibcon#about to read 6, iclass 22, count 0 2006.257.09:56:11.40#ibcon#read 6, iclass 22, count 0 2006.257.09:56:11.40#ibcon#end of sib2, iclass 22, count 0 2006.257.09:56:11.40#ibcon#*after write, iclass 22, count 0 2006.257.09:56:11.40#ibcon#*before return 0, iclass 22, count 0 2006.257.09:56:11.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:11.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:11.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:56:11.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:56:11.40$vck44/va=1,8 2006.257.09:56:11.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.09:56:11.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.09:56:11.40#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:11.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:11.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:11.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:11.40#ibcon#enter wrdev, iclass 24, count 2 2006.257.09:56:11.40#ibcon#first serial, iclass 24, count 2 2006.257.09:56:11.40#ibcon#enter sib2, iclass 24, count 2 2006.257.09:56:11.40#ibcon#flushed, iclass 24, count 2 2006.257.09:56:11.40#ibcon#about to write, iclass 24, count 2 2006.257.09:56:11.40#ibcon#wrote, iclass 24, count 2 2006.257.09:56:11.40#ibcon#about to read 3, iclass 24, count 2 2006.257.09:56:11.42#ibcon#read 3, iclass 24, count 2 2006.257.09:56:11.42#ibcon#about to read 4, iclass 24, count 2 2006.257.09:56:11.42#ibcon#read 4, iclass 24, count 2 2006.257.09:56:11.42#ibcon#about to read 5, iclass 24, count 2 2006.257.09:56:11.42#ibcon#read 5, iclass 24, count 2 2006.257.09:56:11.42#ibcon#about to read 6, iclass 24, count 2 2006.257.09:56:11.42#ibcon#read 6, iclass 24, count 2 2006.257.09:56:11.42#ibcon#end of sib2, iclass 24, count 2 2006.257.09:56:11.42#ibcon#*mode == 0, iclass 24, count 2 2006.257.09:56:11.42#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.09:56:11.42#ibcon#[25=AT01-08\r\n] 2006.257.09:56:11.42#ibcon#*before write, iclass 24, count 2 2006.257.09:56:11.42#ibcon#enter sib2, iclass 24, count 2 2006.257.09:56:11.42#ibcon#flushed, iclass 24, count 2 2006.257.09:56:11.42#ibcon#about to write, iclass 24, count 2 2006.257.09:56:11.42#ibcon#wrote, iclass 24, count 2 2006.257.09:56:11.42#ibcon#about to read 3, iclass 24, count 2 2006.257.09:56:11.45#ibcon#read 3, iclass 24, count 2 2006.257.09:56:11.45#ibcon#about to read 4, iclass 24, count 2 2006.257.09:56:11.45#ibcon#read 4, iclass 24, count 2 2006.257.09:56:11.45#ibcon#about to read 5, iclass 24, count 2 2006.257.09:56:11.45#ibcon#read 5, iclass 24, count 2 2006.257.09:56:11.45#ibcon#about to read 6, iclass 24, count 2 2006.257.09:56:11.45#ibcon#read 6, iclass 24, count 2 2006.257.09:56:11.45#ibcon#end of sib2, iclass 24, count 2 2006.257.09:56:11.45#ibcon#*after write, iclass 24, count 2 2006.257.09:56:11.45#ibcon#*before return 0, iclass 24, count 2 2006.257.09:56:11.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:11.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:11.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.09:56:11.45#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:11.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:11.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:11.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:11.57#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:56:11.57#ibcon#first serial, iclass 24, count 0 2006.257.09:56:11.57#ibcon#enter sib2, iclass 24, count 0 2006.257.09:56:11.57#ibcon#flushed, iclass 24, count 0 2006.257.09:56:11.57#ibcon#about to write, iclass 24, count 0 2006.257.09:56:11.57#ibcon#wrote, iclass 24, count 0 2006.257.09:56:11.57#ibcon#about to read 3, iclass 24, count 0 2006.257.09:56:11.59#ibcon#read 3, iclass 24, count 0 2006.257.09:56:11.59#ibcon#about to read 4, iclass 24, count 0 2006.257.09:56:11.59#ibcon#read 4, iclass 24, count 0 2006.257.09:56:11.59#ibcon#about to read 5, iclass 24, count 0 2006.257.09:56:11.59#ibcon#read 5, iclass 24, count 0 2006.257.09:56:11.59#ibcon#about to read 6, iclass 24, count 0 2006.257.09:56:11.59#ibcon#read 6, iclass 24, count 0 2006.257.09:56:11.59#ibcon#end of sib2, iclass 24, count 0 2006.257.09:56:11.59#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:56:11.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:56:11.59#ibcon#[25=USB\r\n] 2006.257.09:56:11.59#ibcon#*before write, iclass 24, count 0 2006.257.09:56:11.59#ibcon#enter sib2, iclass 24, count 0 2006.257.09:56:11.59#ibcon#flushed, iclass 24, count 0 2006.257.09:56:11.59#ibcon#about to write, iclass 24, count 0 2006.257.09:56:11.59#ibcon#wrote, iclass 24, count 0 2006.257.09:56:11.59#ibcon#about to read 3, iclass 24, count 0 2006.257.09:56:11.62#ibcon#read 3, iclass 24, count 0 2006.257.09:56:11.62#ibcon#about to read 4, iclass 24, count 0 2006.257.09:56:11.62#ibcon#read 4, iclass 24, count 0 2006.257.09:56:11.62#ibcon#about to read 5, iclass 24, count 0 2006.257.09:56:11.62#ibcon#read 5, iclass 24, count 0 2006.257.09:56:11.62#ibcon#about to read 6, iclass 24, count 0 2006.257.09:56:11.62#ibcon#read 6, iclass 24, count 0 2006.257.09:56:11.62#ibcon#end of sib2, iclass 24, count 0 2006.257.09:56:11.62#ibcon#*after write, iclass 24, count 0 2006.257.09:56:11.62#ibcon#*before return 0, iclass 24, count 0 2006.257.09:56:11.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:11.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:11.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:56:11.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:56:11.62$vck44/valo=2,534.99 2006.257.09:56:11.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.09:56:11.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.09:56:11.62#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:11.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:11.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:11.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:11.62#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:56:11.62#ibcon#first serial, iclass 26, count 0 2006.257.09:56:11.62#ibcon#enter sib2, iclass 26, count 0 2006.257.09:56:11.62#ibcon#flushed, iclass 26, count 0 2006.257.09:56:11.62#ibcon#about to write, iclass 26, count 0 2006.257.09:56:11.62#ibcon#wrote, iclass 26, count 0 2006.257.09:56:11.62#ibcon#about to read 3, iclass 26, count 0 2006.257.09:56:11.64#ibcon#read 3, iclass 26, count 0 2006.257.09:56:11.64#ibcon#about to read 4, iclass 26, count 0 2006.257.09:56:11.64#ibcon#read 4, iclass 26, count 0 2006.257.09:56:11.64#ibcon#about to read 5, iclass 26, count 0 2006.257.09:56:11.64#ibcon#read 5, iclass 26, count 0 2006.257.09:56:11.64#ibcon#about to read 6, iclass 26, count 0 2006.257.09:56:11.64#ibcon#read 6, iclass 26, count 0 2006.257.09:56:11.64#ibcon#end of sib2, iclass 26, count 0 2006.257.09:56:11.64#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:56:11.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:56:11.64#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.09:56:11.64#ibcon#*before write, iclass 26, count 0 2006.257.09:56:11.64#ibcon#enter sib2, iclass 26, count 0 2006.257.09:56:11.64#ibcon#flushed, iclass 26, count 0 2006.257.09:56:11.64#ibcon#about to write, iclass 26, count 0 2006.257.09:56:11.64#ibcon#wrote, iclass 26, count 0 2006.257.09:56:11.64#ibcon#about to read 3, iclass 26, count 0 2006.257.09:56:11.68#ibcon#read 3, iclass 26, count 0 2006.257.09:56:11.68#ibcon#about to read 4, iclass 26, count 0 2006.257.09:56:11.68#ibcon#read 4, iclass 26, count 0 2006.257.09:56:11.68#ibcon#about to read 5, iclass 26, count 0 2006.257.09:56:11.68#ibcon#read 5, iclass 26, count 0 2006.257.09:56:11.68#ibcon#about to read 6, iclass 26, count 0 2006.257.09:56:11.68#ibcon#read 6, iclass 26, count 0 2006.257.09:56:11.68#ibcon#end of sib2, iclass 26, count 0 2006.257.09:56:11.68#ibcon#*after write, iclass 26, count 0 2006.257.09:56:11.68#ibcon#*before return 0, iclass 26, count 0 2006.257.09:56:11.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:11.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:11.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:56:11.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:56:11.68$vck44/va=2,7 2006.257.09:56:11.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.09:56:11.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.09:56:11.68#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:11.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:11.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:11.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:11.74#ibcon#enter wrdev, iclass 28, count 2 2006.257.09:56:11.74#ibcon#first serial, iclass 28, count 2 2006.257.09:56:11.74#ibcon#enter sib2, iclass 28, count 2 2006.257.09:56:11.74#ibcon#flushed, iclass 28, count 2 2006.257.09:56:11.74#ibcon#about to write, iclass 28, count 2 2006.257.09:56:11.74#ibcon#wrote, iclass 28, count 2 2006.257.09:56:11.74#ibcon#about to read 3, iclass 28, count 2 2006.257.09:56:11.76#ibcon#read 3, iclass 28, count 2 2006.257.09:56:11.76#ibcon#about to read 4, iclass 28, count 2 2006.257.09:56:11.76#ibcon#read 4, iclass 28, count 2 2006.257.09:56:11.76#ibcon#about to read 5, iclass 28, count 2 2006.257.09:56:11.76#ibcon#read 5, iclass 28, count 2 2006.257.09:56:11.76#ibcon#about to read 6, iclass 28, count 2 2006.257.09:56:11.76#ibcon#read 6, iclass 28, count 2 2006.257.09:56:11.76#ibcon#end of sib2, iclass 28, count 2 2006.257.09:56:11.76#ibcon#*mode == 0, iclass 28, count 2 2006.257.09:56:11.76#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.09:56:11.76#ibcon#[25=AT02-07\r\n] 2006.257.09:56:11.76#ibcon#*before write, iclass 28, count 2 2006.257.09:56:11.76#ibcon#enter sib2, iclass 28, count 2 2006.257.09:56:11.76#ibcon#flushed, iclass 28, count 2 2006.257.09:56:11.76#ibcon#about to write, iclass 28, count 2 2006.257.09:56:11.76#ibcon#wrote, iclass 28, count 2 2006.257.09:56:11.76#ibcon#about to read 3, iclass 28, count 2 2006.257.09:56:11.79#ibcon#read 3, iclass 28, count 2 2006.257.09:56:11.79#ibcon#about to read 4, iclass 28, count 2 2006.257.09:56:11.79#ibcon#read 4, iclass 28, count 2 2006.257.09:56:11.79#ibcon#about to read 5, iclass 28, count 2 2006.257.09:56:11.79#ibcon#read 5, iclass 28, count 2 2006.257.09:56:11.79#ibcon#about to read 6, iclass 28, count 2 2006.257.09:56:11.79#ibcon#read 6, iclass 28, count 2 2006.257.09:56:11.79#ibcon#end of sib2, iclass 28, count 2 2006.257.09:56:11.79#ibcon#*after write, iclass 28, count 2 2006.257.09:56:11.79#ibcon#*before return 0, iclass 28, count 2 2006.257.09:56:11.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:11.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:11.79#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.09:56:11.79#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:11.79#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:11.91#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:11.91#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:11.91#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:56:11.91#ibcon#first serial, iclass 28, count 0 2006.257.09:56:11.91#ibcon#enter sib2, iclass 28, count 0 2006.257.09:56:11.91#ibcon#flushed, iclass 28, count 0 2006.257.09:56:11.91#ibcon#about to write, iclass 28, count 0 2006.257.09:56:11.91#ibcon#wrote, iclass 28, count 0 2006.257.09:56:11.91#ibcon#about to read 3, iclass 28, count 0 2006.257.09:56:11.93#ibcon#read 3, iclass 28, count 0 2006.257.09:56:11.93#ibcon#about to read 4, iclass 28, count 0 2006.257.09:56:11.93#ibcon#read 4, iclass 28, count 0 2006.257.09:56:11.93#ibcon#about to read 5, iclass 28, count 0 2006.257.09:56:11.93#ibcon#read 5, iclass 28, count 0 2006.257.09:56:11.93#ibcon#about to read 6, iclass 28, count 0 2006.257.09:56:11.93#ibcon#read 6, iclass 28, count 0 2006.257.09:56:11.93#ibcon#end of sib2, iclass 28, count 0 2006.257.09:56:11.93#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:56:11.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:56:11.93#ibcon#[25=USB\r\n] 2006.257.09:56:11.93#ibcon#*before write, iclass 28, count 0 2006.257.09:56:11.93#ibcon#enter sib2, iclass 28, count 0 2006.257.09:56:11.93#ibcon#flushed, iclass 28, count 0 2006.257.09:56:11.93#ibcon#about to write, iclass 28, count 0 2006.257.09:56:11.93#ibcon#wrote, iclass 28, count 0 2006.257.09:56:11.93#ibcon#about to read 3, iclass 28, count 0 2006.257.09:56:11.96#ibcon#read 3, iclass 28, count 0 2006.257.09:56:11.96#ibcon#about to read 4, iclass 28, count 0 2006.257.09:56:11.96#ibcon#read 4, iclass 28, count 0 2006.257.09:56:11.96#ibcon#about to read 5, iclass 28, count 0 2006.257.09:56:11.96#ibcon#read 5, iclass 28, count 0 2006.257.09:56:11.96#ibcon#about to read 6, iclass 28, count 0 2006.257.09:56:11.96#ibcon#read 6, iclass 28, count 0 2006.257.09:56:11.96#ibcon#end of sib2, iclass 28, count 0 2006.257.09:56:11.96#ibcon#*after write, iclass 28, count 0 2006.257.09:56:11.96#ibcon#*before return 0, iclass 28, count 0 2006.257.09:56:11.96#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:11.96#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:11.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:56:11.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:56:11.96$vck44/valo=3,564.99 2006.257.09:56:11.96#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.09:56:11.96#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.09:56:11.96#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:11.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:11.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:11.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:11.96#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:56:11.96#ibcon#first serial, iclass 30, count 0 2006.257.09:56:11.96#ibcon#enter sib2, iclass 30, count 0 2006.257.09:56:11.96#ibcon#flushed, iclass 30, count 0 2006.257.09:56:11.96#ibcon#about to write, iclass 30, count 0 2006.257.09:56:11.96#ibcon#wrote, iclass 30, count 0 2006.257.09:56:11.96#ibcon#about to read 3, iclass 30, count 0 2006.257.09:56:11.98#ibcon#read 3, iclass 30, count 0 2006.257.09:56:11.98#ibcon#about to read 4, iclass 30, count 0 2006.257.09:56:11.98#ibcon#read 4, iclass 30, count 0 2006.257.09:56:11.98#ibcon#about to read 5, iclass 30, count 0 2006.257.09:56:11.98#ibcon#read 5, iclass 30, count 0 2006.257.09:56:11.98#ibcon#about to read 6, iclass 30, count 0 2006.257.09:56:11.98#ibcon#read 6, iclass 30, count 0 2006.257.09:56:11.98#ibcon#end of sib2, iclass 30, count 0 2006.257.09:56:11.98#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:56:11.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:56:11.98#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.09:56:11.98#ibcon#*before write, iclass 30, count 0 2006.257.09:56:11.98#ibcon#enter sib2, iclass 30, count 0 2006.257.09:56:11.98#ibcon#flushed, iclass 30, count 0 2006.257.09:56:11.98#ibcon#about to write, iclass 30, count 0 2006.257.09:56:11.98#ibcon#wrote, iclass 30, count 0 2006.257.09:56:11.98#ibcon#about to read 3, iclass 30, count 0 2006.257.09:56:12.02#ibcon#read 3, iclass 30, count 0 2006.257.09:56:12.02#ibcon#about to read 4, iclass 30, count 0 2006.257.09:56:12.02#ibcon#read 4, iclass 30, count 0 2006.257.09:56:12.02#ibcon#about to read 5, iclass 30, count 0 2006.257.09:56:12.02#ibcon#read 5, iclass 30, count 0 2006.257.09:56:12.02#ibcon#about to read 6, iclass 30, count 0 2006.257.09:56:12.02#ibcon#read 6, iclass 30, count 0 2006.257.09:56:12.02#ibcon#end of sib2, iclass 30, count 0 2006.257.09:56:12.02#ibcon#*after write, iclass 30, count 0 2006.257.09:56:12.02#ibcon#*before return 0, iclass 30, count 0 2006.257.09:56:12.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:12.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:12.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:56:12.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:56:12.02$vck44/va=3,8 2006.257.09:56:12.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.09:56:12.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.09:56:12.02#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:12.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:12.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:12.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:12.08#ibcon#enter wrdev, iclass 32, count 2 2006.257.09:56:12.08#ibcon#first serial, iclass 32, count 2 2006.257.09:56:12.08#ibcon#enter sib2, iclass 32, count 2 2006.257.09:56:12.08#ibcon#flushed, iclass 32, count 2 2006.257.09:56:12.08#ibcon#about to write, iclass 32, count 2 2006.257.09:56:12.08#ibcon#wrote, iclass 32, count 2 2006.257.09:56:12.08#ibcon#about to read 3, iclass 32, count 2 2006.257.09:56:12.10#ibcon#read 3, iclass 32, count 2 2006.257.09:56:12.10#ibcon#about to read 4, iclass 32, count 2 2006.257.09:56:12.10#ibcon#read 4, iclass 32, count 2 2006.257.09:56:12.10#ibcon#about to read 5, iclass 32, count 2 2006.257.09:56:12.10#ibcon#read 5, iclass 32, count 2 2006.257.09:56:12.10#ibcon#about to read 6, iclass 32, count 2 2006.257.09:56:12.10#ibcon#read 6, iclass 32, count 2 2006.257.09:56:12.10#ibcon#end of sib2, iclass 32, count 2 2006.257.09:56:12.10#ibcon#*mode == 0, iclass 32, count 2 2006.257.09:56:12.10#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.09:56:12.10#ibcon#[25=AT03-08\r\n] 2006.257.09:56:12.10#ibcon#*before write, iclass 32, count 2 2006.257.09:56:12.10#ibcon#enter sib2, iclass 32, count 2 2006.257.09:56:12.10#ibcon#flushed, iclass 32, count 2 2006.257.09:56:12.10#ibcon#about to write, iclass 32, count 2 2006.257.09:56:12.10#ibcon#wrote, iclass 32, count 2 2006.257.09:56:12.10#ibcon#about to read 3, iclass 32, count 2 2006.257.09:56:12.13#ibcon#read 3, iclass 32, count 2 2006.257.09:56:12.13#ibcon#about to read 4, iclass 32, count 2 2006.257.09:56:12.13#ibcon#read 4, iclass 32, count 2 2006.257.09:56:12.13#ibcon#about to read 5, iclass 32, count 2 2006.257.09:56:12.13#ibcon#read 5, iclass 32, count 2 2006.257.09:56:12.13#ibcon#about to read 6, iclass 32, count 2 2006.257.09:56:12.13#ibcon#read 6, iclass 32, count 2 2006.257.09:56:12.13#ibcon#end of sib2, iclass 32, count 2 2006.257.09:56:12.13#ibcon#*after write, iclass 32, count 2 2006.257.09:56:12.13#ibcon#*before return 0, iclass 32, count 2 2006.257.09:56:12.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:12.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:12.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.09:56:12.13#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:12.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:12.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:12.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:12.25#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:56:12.25#ibcon#first serial, iclass 32, count 0 2006.257.09:56:12.25#ibcon#enter sib2, iclass 32, count 0 2006.257.09:56:12.25#ibcon#flushed, iclass 32, count 0 2006.257.09:56:12.25#ibcon#about to write, iclass 32, count 0 2006.257.09:56:12.25#ibcon#wrote, iclass 32, count 0 2006.257.09:56:12.25#ibcon#about to read 3, iclass 32, count 0 2006.257.09:56:12.27#ibcon#read 3, iclass 32, count 0 2006.257.09:56:12.27#ibcon#about to read 4, iclass 32, count 0 2006.257.09:56:12.27#ibcon#read 4, iclass 32, count 0 2006.257.09:56:12.27#ibcon#about to read 5, iclass 32, count 0 2006.257.09:56:12.27#ibcon#read 5, iclass 32, count 0 2006.257.09:56:12.27#ibcon#about to read 6, iclass 32, count 0 2006.257.09:56:12.27#ibcon#read 6, iclass 32, count 0 2006.257.09:56:12.27#ibcon#end of sib2, iclass 32, count 0 2006.257.09:56:12.27#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:56:12.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:56:12.27#ibcon#[25=USB\r\n] 2006.257.09:56:12.27#ibcon#*before write, iclass 32, count 0 2006.257.09:56:12.27#ibcon#enter sib2, iclass 32, count 0 2006.257.09:56:12.27#ibcon#flushed, iclass 32, count 0 2006.257.09:56:12.27#ibcon#about to write, iclass 32, count 0 2006.257.09:56:12.27#ibcon#wrote, iclass 32, count 0 2006.257.09:56:12.27#ibcon#about to read 3, iclass 32, count 0 2006.257.09:56:12.30#ibcon#read 3, iclass 32, count 0 2006.257.09:56:12.30#ibcon#about to read 4, iclass 32, count 0 2006.257.09:56:12.30#ibcon#read 4, iclass 32, count 0 2006.257.09:56:12.30#ibcon#about to read 5, iclass 32, count 0 2006.257.09:56:12.30#ibcon#read 5, iclass 32, count 0 2006.257.09:56:12.30#ibcon#about to read 6, iclass 32, count 0 2006.257.09:56:12.30#ibcon#read 6, iclass 32, count 0 2006.257.09:56:12.30#ibcon#end of sib2, iclass 32, count 0 2006.257.09:56:12.30#ibcon#*after write, iclass 32, count 0 2006.257.09:56:12.30#ibcon#*before return 0, iclass 32, count 0 2006.257.09:56:12.30#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:12.30#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:12.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:56:12.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:56:12.30$vck44/valo=4,624.99 2006.257.09:56:12.30#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.09:56:12.30#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.09:56:12.30#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:12.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:12.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:12.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:12.30#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:56:12.30#ibcon#first serial, iclass 34, count 0 2006.257.09:56:12.30#ibcon#enter sib2, iclass 34, count 0 2006.257.09:56:12.30#ibcon#flushed, iclass 34, count 0 2006.257.09:56:12.30#ibcon#about to write, iclass 34, count 0 2006.257.09:56:12.30#ibcon#wrote, iclass 34, count 0 2006.257.09:56:12.30#ibcon#about to read 3, iclass 34, count 0 2006.257.09:56:12.32#ibcon#read 3, iclass 34, count 0 2006.257.09:56:12.32#ibcon#about to read 4, iclass 34, count 0 2006.257.09:56:12.32#ibcon#read 4, iclass 34, count 0 2006.257.09:56:12.32#ibcon#about to read 5, iclass 34, count 0 2006.257.09:56:12.32#ibcon#read 5, iclass 34, count 0 2006.257.09:56:12.32#ibcon#about to read 6, iclass 34, count 0 2006.257.09:56:12.32#ibcon#read 6, iclass 34, count 0 2006.257.09:56:12.32#ibcon#end of sib2, iclass 34, count 0 2006.257.09:56:12.32#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:56:12.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:56:12.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.09:56:12.32#ibcon#*before write, iclass 34, count 0 2006.257.09:56:12.32#ibcon#enter sib2, iclass 34, count 0 2006.257.09:56:12.32#ibcon#flushed, iclass 34, count 0 2006.257.09:56:12.32#ibcon#about to write, iclass 34, count 0 2006.257.09:56:12.32#ibcon#wrote, iclass 34, count 0 2006.257.09:56:12.32#ibcon#about to read 3, iclass 34, count 0 2006.257.09:56:12.36#ibcon#read 3, iclass 34, count 0 2006.257.09:56:12.36#ibcon#about to read 4, iclass 34, count 0 2006.257.09:56:12.36#ibcon#read 4, iclass 34, count 0 2006.257.09:56:12.36#ibcon#about to read 5, iclass 34, count 0 2006.257.09:56:12.36#ibcon#read 5, iclass 34, count 0 2006.257.09:56:12.36#ibcon#about to read 6, iclass 34, count 0 2006.257.09:56:12.36#ibcon#read 6, iclass 34, count 0 2006.257.09:56:12.36#ibcon#end of sib2, iclass 34, count 0 2006.257.09:56:12.36#ibcon#*after write, iclass 34, count 0 2006.257.09:56:12.36#ibcon#*before return 0, iclass 34, count 0 2006.257.09:56:12.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:12.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:12.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:56:12.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:56:12.36$vck44/va=4,7 2006.257.09:56:12.36#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.09:56:12.36#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.09:56:12.36#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:12.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:12.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:12.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:12.42#ibcon#enter wrdev, iclass 36, count 2 2006.257.09:56:12.42#ibcon#first serial, iclass 36, count 2 2006.257.09:56:12.42#ibcon#enter sib2, iclass 36, count 2 2006.257.09:56:12.42#ibcon#flushed, iclass 36, count 2 2006.257.09:56:12.42#ibcon#about to write, iclass 36, count 2 2006.257.09:56:12.42#ibcon#wrote, iclass 36, count 2 2006.257.09:56:12.42#ibcon#about to read 3, iclass 36, count 2 2006.257.09:56:12.44#ibcon#read 3, iclass 36, count 2 2006.257.09:56:12.44#ibcon#about to read 4, iclass 36, count 2 2006.257.09:56:12.44#ibcon#read 4, iclass 36, count 2 2006.257.09:56:12.44#ibcon#about to read 5, iclass 36, count 2 2006.257.09:56:12.44#ibcon#read 5, iclass 36, count 2 2006.257.09:56:12.44#ibcon#about to read 6, iclass 36, count 2 2006.257.09:56:12.44#ibcon#read 6, iclass 36, count 2 2006.257.09:56:12.44#ibcon#end of sib2, iclass 36, count 2 2006.257.09:56:12.44#ibcon#*mode == 0, iclass 36, count 2 2006.257.09:56:12.44#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.09:56:12.44#ibcon#[25=AT04-07\r\n] 2006.257.09:56:12.44#ibcon#*before write, iclass 36, count 2 2006.257.09:56:12.44#ibcon#enter sib2, iclass 36, count 2 2006.257.09:56:12.44#ibcon#flushed, iclass 36, count 2 2006.257.09:56:12.44#ibcon#about to write, iclass 36, count 2 2006.257.09:56:12.44#ibcon#wrote, iclass 36, count 2 2006.257.09:56:12.44#ibcon#about to read 3, iclass 36, count 2 2006.257.09:56:12.47#ibcon#read 3, iclass 36, count 2 2006.257.09:56:12.47#ibcon#about to read 4, iclass 36, count 2 2006.257.09:56:12.47#ibcon#read 4, iclass 36, count 2 2006.257.09:56:12.47#ibcon#about to read 5, iclass 36, count 2 2006.257.09:56:12.47#ibcon#read 5, iclass 36, count 2 2006.257.09:56:12.47#ibcon#about to read 6, iclass 36, count 2 2006.257.09:56:12.47#ibcon#read 6, iclass 36, count 2 2006.257.09:56:12.47#ibcon#end of sib2, iclass 36, count 2 2006.257.09:56:12.47#ibcon#*after write, iclass 36, count 2 2006.257.09:56:12.49#ibcon#*before return 0, iclass 36, count 2 2006.257.09:56:12.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:12.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:12.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.09:56:12.49#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:12.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:12.60#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:12.60#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:12.60#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:56:12.60#ibcon#first serial, iclass 36, count 0 2006.257.09:56:12.60#ibcon#enter sib2, iclass 36, count 0 2006.257.09:56:12.60#ibcon#flushed, iclass 36, count 0 2006.257.09:56:12.60#ibcon#about to write, iclass 36, count 0 2006.257.09:56:12.60#ibcon#wrote, iclass 36, count 0 2006.257.09:56:12.60#ibcon#about to read 3, iclass 36, count 0 2006.257.09:56:12.62#ibcon#read 3, iclass 36, count 0 2006.257.09:56:12.62#ibcon#about to read 4, iclass 36, count 0 2006.257.09:56:12.62#ibcon#read 4, iclass 36, count 0 2006.257.09:56:12.62#ibcon#about to read 5, iclass 36, count 0 2006.257.09:56:12.62#ibcon#read 5, iclass 36, count 0 2006.257.09:56:12.62#ibcon#about to read 6, iclass 36, count 0 2006.257.09:56:12.62#ibcon#read 6, iclass 36, count 0 2006.257.09:56:12.62#ibcon#end of sib2, iclass 36, count 0 2006.257.09:56:12.62#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:56:12.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:56:12.62#ibcon#[25=USB\r\n] 2006.257.09:56:12.62#ibcon#*before write, iclass 36, count 0 2006.257.09:56:12.62#ibcon#enter sib2, iclass 36, count 0 2006.257.09:56:12.62#ibcon#flushed, iclass 36, count 0 2006.257.09:56:12.62#ibcon#about to write, iclass 36, count 0 2006.257.09:56:12.62#ibcon#wrote, iclass 36, count 0 2006.257.09:56:12.62#ibcon#about to read 3, iclass 36, count 0 2006.257.09:56:12.65#ibcon#read 3, iclass 36, count 0 2006.257.09:56:12.65#ibcon#about to read 4, iclass 36, count 0 2006.257.09:56:12.65#ibcon#read 4, iclass 36, count 0 2006.257.09:56:12.65#ibcon#about to read 5, iclass 36, count 0 2006.257.09:56:12.65#ibcon#read 5, iclass 36, count 0 2006.257.09:56:12.65#ibcon#about to read 6, iclass 36, count 0 2006.257.09:56:12.65#ibcon#read 6, iclass 36, count 0 2006.257.09:56:12.65#ibcon#end of sib2, iclass 36, count 0 2006.257.09:56:12.65#ibcon#*after write, iclass 36, count 0 2006.257.09:56:12.65#ibcon#*before return 0, iclass 36, count 0 2006.257.09:56:12.65#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:12.65#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:12.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:56:12.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:56:12.65$vck44/valo=5,734.99 2006.257.09:56:12.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.09:56:12.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.09:56:12.65#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:12.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:12.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:12.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:12.65#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:56:12.65#ibcon#first serial, iclass 38, count 0 2006.257.09:56:12.65#ibcon#enter sib2, iclass 38, count 0 2006.257.09:56:12.65#ibcon#flushed, iclass 38, count 0 2006.257.09:56:12.65#ibcon#about to write, iclass 38, count 0 2006.257.09:56:12.65#ibcon#wrote, iclass 38, count 0 2006.257.09:56:12.65#ibcon#about to read 3, iclass 38, count 0 2006.257.09:56:12.67#ibcon#read 3, iclass 38, count 0 2006.257.09:56:12.67#ibcon#about to read 4, iclass 38, count 0 2006.257.09:56:12.67#ibcon#read 4, iclass 38, count 0 2006.257.09:56:12.67#ibcon#about to read 5, iclass 38, count 0 2006.257.09:56:12.67#ibcon#read 5, iclass 38, count 0 2006.257.09:56:12.67#ibcon#about to read 6, iclass 38, count 0 2006.257.09:56:12.67#ibcon#read 6, iclass 38, count 0 2006.257.09:56:12.67#ibcon#end of sib2, iclass 38, count 0 2006.257.09:56:12.67#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:56:12.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:56:12.67#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.09:56:12.67#ibcon#*before write, iclass 38, count 0 2006.257.09:56:12.67#ibcon#enter sib2, iclass 38, count 0 2006.257.09:56:12.67#ibcon#flushed, iclass 38, count 0 2006.257.09:56:12.67#ibcon#about to write, iclass 38, count 0 2006.257.09:56:12.67#ibcon#wrote, iclass 38, count 0 2006.257.09:56:12.67#ibcon#about to read 3, iclass 38, count 0 2006.257.09:56:12.71#ibcon#read 3, iclass 38, count 0 2006.257.09:56:12.71#ibcon#about to read 4, iclass 38, count 0 2006.257.09:56:12.71#ibcon#read 4, iclass 38, count 0 2006.257.09:56:12.71#ibcon#about to read 5, iclass 38, count 0 2006.257.09:56:12.71#ibcon#read 5, iclass 38, count 0 2006.257.09:56:12.71#ibcon#about to read 6, iclass 38, count 0 2006.257.09:56:12.71#ibcon#read 6, iclass 38, count 0 2006.257.09:56:12.71#ibcon#end of sib2, iclass 38, count 0 2006.257.09:56:12.71#ibcon#*after write, iclass 38, count 0 2006.257.09:56:12.71#ibcon#*before return 0, iclass 38, count 0 2006.257.09:56:12.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:12.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:12.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:56:12.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:56:12.71$vck44/va=5,4 2006.257.09:56:12.71#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.09:56:12.71#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.09:56:12.71#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:12.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:12.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:12.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:12.77#ibcon#enter wrdev, iclass 40, count 2 2006.257.09:56:12.77#ibcon#first serial, iclass 40, count 2 2006.257.09:56:12.77#ibcon#enter sib2, iclass 40, count 2 2006.257.09:56:12.77#ibcon#flushed, iclass 40, count 2 2006.257.09:56:12.77#ibcon#about to write, iclass 40, count 2 2006.257.09:56:12.77#ibcon#wrote, iclass 40, count 2 2006.257.09:56:12.77#ibcon#about to read 3, iclass 40, count 2 2006.257.09:56:12.79#ibcon#read 3, iclass 40, count 2 2006.257.09:56:12.79#ibcon#about to read 4, iclass 40, count 2 2006.257.09:56:12.79#ibcon#read 4, iclass 40, count 2 2006.257.09:56:12.79#ibcon#about to read 5, iclass 40, count 2 2006.257.09:56:12.79#ibcon#read 5, iclass 40, count 2 2006.257.09:56:12.79#ibcon#about to read 6, iclass 40, count 2 2006.257.09:56:12.79#ibcon#read 6, iclass 40, count 2 2006.257.09:56:12.79#ibcon#end of sib2, iclass 40, count 2 2006.257.09:56:12.79#ibcon#*mode == 0, iclass 40, count 2 2006.257.09:56:12.79#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.09:56:12.79#ibcon#[25=AT05-04\r\n] 2006.257.09:56:12.79#ibcon#*before write, iclass 40, count 2 2006.257.09:56:12.79#ibcon#enter sib2, iclass 40, count 2 2006.257.09:56:12.79#ibcon#flushed, iclass 40, count 2 2006.257.09:56:12.79#ibcon#about to write, iclass 40, count 2 2006.257.09:56:12.79#ibcon#wrote, iclass 40, count 2 2006.257.09:56:12.79#ibcon#about to read 3, iclass 40, count 2 2006.257.09:56:12.82#ibcon#read 3, iclass 40, count 2 2006.257.09:56:12.82#ibcon#about to read 4, iclass 40, count 2 2006.257.09:56:12.82#ibcon#read 4, iclass 40, count 2 2006.257.09:56:12.82#ibcon#about to read 5, iclass 40, count 2 2006.257.09:56:12.82#ibcon#read 5, iclass 40, count 2 2006.257.09:56:12.82#ibcon#about to read 6, iclass 40, count 2 2006.257.09:56:12.82#ibcon#read 6, iclass 40, count 2 2006.257.09:56:12.82#ibcon#end of sib2, iclass 40, count 2 2006.257.09:56:12.82#ibcon#*after write, iclass 40, count 2 2006.257.09:56:12.82#ibcon#*before return 0, iclass 40, count 2 2006.257.09:56:12.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:12.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:12.82#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.09:56:12.82#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:12.82#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:12.94#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:12.94#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:12.94#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:56:12.94#ibcon#first serial, iclass 40, count 0 2006.257.09:56:12.94#ibcon#enter sib2, iclass 40, count 0 2006.257.09:56:12.94#ibcon#flushed, iclass 40, count 0 2006.257.09:56:12.94#ibcon#about to write, iclass 40, count 0 2006.257.09:56:12.94#ibcon#wrote, iclass 40, count 0 2006.257.09:56:12.94#ibcon#about to read 3, iclass 40, count 0 2006.257.09:56:12.96#ibcon#read 3, iclass 40, count 0 2006.257.09:56:12.96#ibcon#about to read 4, iclass 40, count 0 2006.257.09:56:12.96#ibcon#read 4, iclass 40, count 0 2006.257.09:56:12.96#ibcon#about to read 5, iclass 40, count 0 2006.257.09:56:12.96#ibcon#read 5, iclass 40, count 0 2006.257.09:56:12.96#ibcon#about to read 6, iclass 40, count 0 2006.257.09:56:12.96#ibcon#read 6, iclass 40, count 0 2006.257.09:56:12.96#ibcon#end of sib2, iclass 40, count 0 2006.257.09:56:12.96#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:56:12.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:56:12.96#ibcon#[25=USB\r\n] 2006.257.09:56:12.96#ibcon#*before write, iclass 40, count 0 2006.257.09:56:12.96#ibcon#enter sib2, iclass 40, count 0 2006.257.09:56:12.96#ibcon#flushed, iclass 40, count 0 2006.257.09:56:12.96#ibcon#about to write, iclass 40, count 0 2006.257.09:56:12.96#ibcon#wrote, iclass 40, count 0 2006.257.09:56:12.96#ibcon#about to read 3, iclass 40, count 0 2006.257.09:56:12.99#ibcon#read 3, iclass 40, count 0 2006.257.09:56:12.99#ibcon#about to read 4, iclass 40, count 0 2006.257.09:56:12.99#ibcon#read 4, iclass 40, count 0 2006.257.09:56:12.99#ibcon#about to read 5, iclass 40, count 0 2006.257.09:56:12.99#ibcon#read 5, iclass 40, count 0 2006.257.09:56:12.99#ibcon#about to read 6, iclass 40, count 0 2006.257.09:56:12.99#ibcon#read 6, iclass 40, count 0 2006.257.09:56:12.99#ibcon#end of sib2, iclass 40, count 0 2006.257.09:56:12.99#ibcon#*after write, iclass 40, count 0 2006.257.09:56:12.99#ibcon#*before return 0, iclass 40, count 0 2006.257.09:56:12.99#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:12.99#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:12.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:56:12.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:56:12.99$vck44/valo=6,814.99 2006.257.09:56:12.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.09:56:12.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.09:56:12.99#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:12.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:12.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:12.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:12.99#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:56:12.99#ibcon#first serial, iclass 4, count 0 2006.257.09:56:12.99#ibcon#enter sib2, iclass 4, count 0 2006.257.09:56:12.99#ibcon#flushed, iclass 4, count 0 2006.257.09:56:12.99#ibcon#about to write, iclass 4, count 0 2006.257.09:56:12.99#ibcon#wrote, iclass 4, count 0 2006.257.09:56:12.99#ibcon#about to read 3, iclass 4, count 0 2006.257.09:56:13.01#ibcon#read 3, iclass 4, count 0 2006.257.09:56:13.01#ibcon#about to read 4, iclass 4, count 0 2006.257.09:56:13.01#ibcon#read 4, iclass 4, count 0 2006.257.09:56:13.01#ibcon#about to read 5, iclass 4, count 0 2006.257.09:56:13.01#ibcon#read 5, iclass 4, count 0 2006.257.09:56:13.01#ibcon#about to read 6, iclass 4, count 0 2006.257.09:56:13.01#ibcon#read 6, iclass 4, count 0 2006.257.09:56:13.01#ibcon#end of sib2, iclass 4, count 0 2006.257.09:56:13.01#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:56:13.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:56:13.01#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.09:56:13.01#ibcon#*before write, iclass 4, count 0 2006.257.09:56:13.01#ibcon#enter sib2, iclass 4, count 0 2006.257.09:56:13.01#ibcon#flushed, iclass 4, count 0 2006.257.09:56:13.01#ibcon#about to write, iclass 4, count 0 2006.257.09:56:13.01#ibcon#wrote, iclass 4, count 0 2006.257.09:56:13.01#ibcon#about to read 3, iclass 4, count 0 2006.257.09:56:13.05#ibcon#read 3, iclass 4, count 0 2006.257.09:56:13.05#ibcon#about to read 4, iclass 4, count 0 2006.257.09:56:13.05#ibcon#read 4, iclass 4, count 0 2006.257.09:56:13.05#ibcon#about to read 5, iclass 4, count 0 2006.257.09:56:13.05#ibcon#read 5, iclass 4, count 0 2006.257.09:56:13.05#ibcon#about to read 6, iclass 4, count 0 2006.257.09:56:13.05#ibcon#read 6, iclass 4, count 0 2006.257.09:56:13.05#ibcon#end of sib2, iclass 4, count 0 2006.257.09:56:13.05#ibcon#*after write, iclass 4, count 0 2006.257.09:56:13.05#ibcon#*before return 0, iclass 4, count 0 2006.257.09:56:13.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:13.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:13.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:56:13.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:56:13.05$vck44/va=6,4 2006.257.09:56:13.05#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.09:56:13.05#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.09:56:13.05#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:13.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:13.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:13.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:13.11#ibcon#enter wrdev, iclass 6, count 2 2006.257.09:56:13.11#ibcon#first serial, iclass 6, count 2 2006.257.09:56:13.11#ibcon#enter sib2, iclass 6, count 2 2006.257.09:56:13.11#ibcon#flushed, iclass 6, count 2 2006.257.09:56:13.11#ibcon#about to write, iclass 6, count 2 2006.257.09:56:13.11#ibcon#wrote, iclass 6, count 2 2006.257.09:56:13.11#ibcon#about to read 3, iclass 6, count 2 2006.257.09:56:13.13#ibcon#read 3, iclass 6, count 2 2006.257.09:56:13.13#ibcon#about to read 4, iclass 6, count 2 2006.257.09:56:13.13#ibcon#read 4, iclass 6, count 2 2006.257.09:56:13.13#ibcon#about to read 5, iclass 6, count 2 2006.257.09:56:13.13#ibcon#read 5, iclass 6, count 2 2006.257.09:56:13.13#ibcon#about to read 6, iclass 6, count 2 2006.257.09:56:13.13#ibcon#read 6, iclass 6, count 2 2006.257.09:56:13.13#ibcon#end of sib2, iclass 6, count 2 2006.257.09:56:13.13#ibcon#*mode == 0, iclass 6, count 2 2006.257.09:56:13.13#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.09:56:13.13#ibcon#[25=AT06-04\r\n] 2006.257.09:56:13.13#ibcon#*before write, iclass 6, count 2 2006.257.09:56:13.13#ibcon#enter sib2, iclass 6, count 2 2006.257.09:56:13.13#ibcon#flushed, iclass 6, count 2 2006.257.09:56:13.13#ibcon#about to write, iclass 6, count 2 2006.257.09:56:13.13#ibcon#wrote, iclass 6, count 2 2006.257.09:56:13.13#ibcon#about to read 3, iclass 6, count 2 2006.257.09:56:13.16#ibcon#read 3, iclass 6, count 2 2006.257.09:56:13.16#ibcon#about to read 4, iclass 6, count 2 2006.257.09:56:13.16#ibcon#read 4, iclass 6, count 2 2006.257.09:56:13.16#ibcon#about to read 5, iclass 6, count 2 2006.257.09:56:13.16#ibcon#read 5, iclass 6, count 2 2006.257.09:56:13.16#ibcon#about to read 6, iclass 6, count 2 2006.257.09:56:13.16#ibcon#read 6, iclass 6, count 2 2006.257.09:56:13.16#ibcon#end of sib2, iclass 6, count 2 2006.257.09:56:13.16#ibcon#*after write, iclass 6, count 2 2006.257.09:56:13.16#ibcon#*before return 0, iclass 6, count 2 2006.257.09:56:13.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:13.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:13.16#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.09:56:13.16#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:13.16#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:13.28#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:13.28#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:13.28#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:56:13.28#ibcon#first serial, iclass 6, count 0 2006.257.09:56:13.28#ibcon#enter sib2, iclass 6, count 0 2006.257.09:56:13.28#ibcon#flushed, iclass 6, count 0 2006.257.09:56:13.28#ibcon#about to write, iclass 6, count 0 2006.257.09:56:13.28#ibcon#wrote, iclass 6, count 0 2006.257.09:56:13.28#ibcon#about to read 3, iclass 6, count 0 2006.257.09:56:13.30#ibcon#read 3, iclass 6, count 0 2006.257.09:56:13.30#ibcon#about to read 4, iclass 6, count 0 2006.257.09:56:13.30#ibcon#read 4, iclass 6, count 0 2006.257.09:56:13.30#ibcon#about to read 5, iclass 6, count 0 2006.257.09:56:13.30#ibcon#read 5, iclass 6, count 0 2006.257.09:56:13.30#ibcon#about to read 6, iclass 6, count 0 2006.257.09:56:13.30#ibcon#read 6, iclass 6, count 0 2006.257.09:56:13.30#ibcon#end of sib2, iclass 6, count 0 2006.257.09:56:13.30#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:56:13.30#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:56:13.30#ibcon#[25=USB\r\n] 2006.257.09:56:13.30#ibcon#*before write, iclass 6, count 0 2006.257.09:56:13.30#ibcon#enter sib2, iclass 6, count 0 2006.257.09:56:13.30#ibcon#flushed, iclass 6, count 0 2006.257.09:56:13.30#ibcon#about to write, iclass 6, count 0 2006.257.09:56:13.30#ibcon#wrote, iclass 6, count 0 2006.257.09:56:13.30#ibcon#about to read 3, iclass 6, count 0 2006.257.09:56:13.33#ibcon#read 3, iclass 6, count 0 2006.257.09:56:13.33#ibcon#about to read 4, iclass 6, count 0 2006.257.09:56:13.33#ibcon#read 4, iclass 6, count 0 2006.257.09:56:13.33#ibcon#about to read 5, iclass 6, count 0 2006.257.09:56:13.33#ibcon#read 5, iclass 6, count 0 2006.257.09:56:13.33#ibcon#about to read 6, iclass 6, count 0 2006.257.09:56:13.33#ibcon#read 6, iclass 6, count 0 2006.257.09:56:13.33#ibcon#end of sib2, iclass 6, count 0 2006.257.09:56:13.33#ibcon#*after write, iclass 6, count 0 2006.257.09:56:13.33#ibcon#*before return 0, iclass 6, count 0 2006.257.09:56:13.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:13.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:13.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:56:13.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:56:13.33$vck44/valo=7,864.99 2006.257.09:56:13.33#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.09:56:13.33#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.09:56:13.33#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:13.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:13.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:13.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:13.33#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:56:13.33#ibcon#first serial, iclass 10, count 0 2006.257.09:56:13.33#ibcon#enter sib2, iclass 10, count 0 2006.257.09:56:13.33#ibcon#flushed, iclass 10, count 0 2006.257.09:56:13.33#ibcon#about to write, iclass 10, count 0 2006.257.09:56:13.33#ibcon#wrote, iclass 10, count 0 2006.257.09:56:13.33#ibcon#about to read 3, iclass 10, count 0 2006.257.09:56:13.35#ibcon#read 3, iclass 10, count 0 2006.257.09:56:13.35#ibcon#about to read 4, iclass 10, count 0 2006.257.09:56:13.35#ibcon#read 4, iclass 10, count 0 2006.257.09:56:13.35#ibcon#about to read 5, iclass 10, count 0 2006.257.09:56:13.35#ibcon#read 5, iclass 10, count 0 2006.257.09:56:13.35#ibcon#about to read 6, iclass 10, count 0 2006.257.09:56:13.35#ibcon#read 6, iclass 10, count 0 2006.257.09:56:13.35#ibcon#end of sib2, iclass 10, count 0 2006.257.09:56:13.35#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:56:13.35#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:56:13.35#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.09:56:13.35#ibcon#*before write, iclass 10, count 0 2006.257.09:56:13.35#ibcon#enter sib2, iclass 10, count 0 2006.257.09:56:13.35#ibcon#flushed, iclass 10, count 0 2006.257.09:56:13.35#ibcon#about to write, iclass 10, count 0 2006.257.09:56:13.35#ibcon#wrote, iclass 10, count 0 2006.257.09:56:13.35#ibcon#about to read 3, iclass 10, count 0 2006.257.09:56:13.39#ibcon#read 3, iclass 10, count 0 2006.257.09:56:13.39#ibcon#about to read 4, iclass 10, count 0 2006.257.09:56:13.39#ibcon#read 4, iclass 10, count 0 2006.257.09:56:13.39#ibcon#about to read 5, iclass 10, count 0 2006.257.09:56:13.39#ibcon#read 5, iclass 10, count 0 2006.257.09:56:13.39#ibcon#about to read 6, iclass 10, count 0 2006.257.09:56:13.39#ibcon#read 6, iclass 10, count 0 2006.257.09:56:13.39#ibcon#end of sib2, iclass 10, count 0 2006.257.09:56:13.39#ibcon#*after write, iclass 10, count 0 2006.257.09:56:13.39#ibcon#*before return 0, iclass 10, count 0 2006.257.09:56:13.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:13.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:13.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:56:13.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:56:13.39$vck44/va=7,4 2006.257.09:56:13.39#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.09:56:13.39#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.09:56:13.39#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:13.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:13.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:13.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:13.45#ibcon#enter wrdev, iclass 12, count 2 2006.257.09:56:13.45#ibcon#first serial, iclass 12, count 2 2006.257.09:56:13.45#ibcon#enter sib2, iclass 12, count 2 2006.257.09:56:13.45#ibcon#flushed, iclass 12, count 2 2006.257.09:56:13.45#ibcon#about to write, iclass 12, count 2 2006.257.09:56:13.45#ibcon#wrote, iclass 12, count 2 2006.257.09:56:13.45#ibcon#about to read 3, iclass 12, count 2 2006.257.09:56:13.47#ibcon#read 3, iclass 12, count 2 2006.257.09:56:13.47#ibcon#about to read 4, iclass 12, count 2 2006.257.09:56:13.47#ibcon#read 4, iclass 12, count 2 2006.257.09:56:13.47#ibcon#about to read 5, iclass 12, count 2 2006.257.09:56:13.47#ibcon#read 5, iclass 12, count 2 2006.257.09:56:13.47#ibcon#about to read 6, iclass 12, count 2 2006.257.09:56:13.47#ibcon#read 6, iclass 12, count 2 2006.257.09:56:13.47#ibcon#end of sib2, iclass 12, count 2 2006.257.09:56:13.47#ibcon#*mode == 0, iclass 12, count 2 2006.257.09:56:13.47#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.09:56:13.47#ibcon#[25=AT07-04\r\n] 2006.257.09:56:13.47#ibcon#*before write, iclass 12, count 2 2006.257.09:56:13.47#ibcon#enter sib2, iclass 12, count 2 2006.257.09:56:13.47#ibcon#flushed, iclass 12, count 2 2006.257.09:56:13.47#ibcon#about to write, iclass 12, count 2 2006.257.09:56:13.47#ibcon#wrote, iclass 12, count 2 2006.257.09:56:13.47#ibcon#about to read 3, iclass 12, count 2 2006.257.09:56:13.50#ibcon#read 3, iclass 12, count 2 2006.257.09:56:13.50#ibcon#about to read 4, iclass 12, count 2 2006.257.09:56:13.50#ibcon#read 4, iclass 12, count 2 2006.257.09:56:13.50#ibcon#about to read 5, iclass 12, count 2 2006.257.09:56:13.50#ibcon#read 5, iclass 12, count 2 2006.257.09:56:13.50#ibcon#about to read 6, iclass 12, count 2 2006.257.09:56:13.50#ibcon#read 6, iclass 12, count 2 2006.257.09:56:13.50#ibcon#end of sib2, iclass 12, count 2 2006.257.09:56:13.50#ibcon#*after write, iclass 12, count 2 2006.257.09:56:13.50#ibcon#*before return 0, iclass 12, count 2 2006.257.09:56:13.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:13.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:13.50#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.09:56:13.50#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:13.50#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:13.62#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:13.62#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:13.62#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:56:13.62#ibcon#first serial, iclass 12, count 0 2006.257.09:56:13.62#ibcon#enter sib2, iclass 12, count 0 2006.257.09:56:13.62#ibcon#flushed, iclass 12, count 0 2006.257.09:56:13.62#ibcon#about to write, iclass 12, count 0 2006.257.09:56:13.62#ibcon#wrote, iclass 12, count 0 2006.257.09:56:13.62#ibcon#about to read 3, iclass 12, count 0 2006.257.09:56:13.64#ibcon#read 3, iclass 12, count 0 2006.257.09:56:13.64#ibcon#about to read 4, iclass 12, count 0 2006.257.09:56:13.64#ibcon#read 4, iclass 12, count 0 2006.257.09:56:13.64#ibcon#about to read 5, iclass 12, count 0 2006.257.09:56:13.64#ibcon#read 5, iclass 12, count 0 2006.257.09:56:13.64#ibcon#about to read 6, iclass 12, count 0 2006.257.09:56:13.64#ibcon#read 6, iclass 12, count 0 2006.257.09:56:13.64#ibcon#end of sib2, iclass 12, count 0 2006.257.09:56:13.64#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:56:13.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:56:13.64#ibcon#[25=USB\r\n] 2006.257.09:56:13.64#ibcon#*before write, iclass 12, count 0 2006.257.09:56:13.64#ibcon#enter sib2, iclass 12, count 0 2006.257.09:56:13.64#ibcon#flushed, iclass 12, count 0 2006.257.09:56:13.64#ibcon#about to write, iclass 12, count 0 2006.257.09:56:13.64#ibcon#wrote, iclass 12, count 0 2006.257.09:56:13.64#ibcon#about to read 3, iclass 12, count 0 2006.257.09:56:13.67#ibcon#read 3, iclass 12, count 0 2006.257.09:56:13.67#ibcon#about to read 4, iclass 12, count 0 2006.257.09:56:13.67#ibcon#read 4, iclass 12, count 0 2006.257.09:56:13.67#ibcon#about to read 5, iclass 12, count 0 2006.257.09:56:13.67#ibcon#read 5, iclass 12, count 0 2006.257.09:56:13.67#ibcon#about to read 6, iclass 12, count 0 2006.257.09:56:13.67#ibcon#read 6, iclass 12, count 0 2006.257.09:56:13.67#ibcon#end of sib2, iclass 12, count 0 2006.257.09:56:13.67#ibcon#*after write, iclass 12, count 0 2006.257.09:56:13.67#ibcon#*before return 0, iclass 12, count 0 2006.257.09:56:13.67#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:13.67#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:13.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:56:13.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:56:13.67$vck44/valo=8,884.99 2006.257.09:56:13.67#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.09:56:13.67#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.09:56:13.67#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:13.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:56:13.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:56:13.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:56:13.67#ibcon#enter wrdev, iclass 14, count 0 2006.257.09:56:13.67#ibcon#first serial, iclass 14, count 0 2006.257.09:56:13.67#ibcon#enter sib2, iclass 14, count 0 2006.257.09:56:13.67#ibcon#flushed, iclass 14, count 0 2006.257.09:56:13.67#ibcon#about to write, iclass 14, count 0 2006.257.09:56:13.67#ibcon#wrote, iclass 14, count 0 2006.257.09:56:13.67#ibcon#about to read 3, iclass 14, count 0 2006.257.09:56:13.69#ibcon#read 3, iclass 14, count 0 2006.257.09:56:13.69#ibcon#about to read 4, iclass 14, count 0 2006.257.09:56:13.69#ibcon#read 4, iclass 14, count 0 2006.257.09:56:13.69#ibcon#about to read 5, iclass 14, count 0 2006.257.09:56:13.69#ibcon#read 5, iclass 14, count 0 2006.257.09:56:13.69#ibcon#about to read 6, iclass 14, count 0 2006.257.09:56:13.69#ibcon#read 6, iclass 14, count 0 2006.257.09:56:13.69#ibcon#end of sib2, iclass 14, count 0 2006.257.09:56:13.69#ibcon#*mode == 0, iclass 14, count 0 2006.257.09:56:13.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.09:56:13.69#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.09:56:13.69#ibcon#*before write, iclass 14, count 0 2006.257.09:56:13.69#ibcon#enter sib2, iclass 14, count 0 2006.257.09:56:13.69#ibcon#flushed, iclass 14, count 0 2006.257.09:56:13.69#ibcon#about to write, iclass 14, count 0 2006.257.09:56:13.69#ibcon#wrote, iclass 14, count 0 2006.257.09:56:13.69#ibcon#about to read 3, iclass 14, count 0 2006.257.09:56:13.73#ibcon#read 3, iclass 14, count 0 2006.257.09:56:13.73#ibcon#about to read 4, iclass 14, count 0 2006.257.09:56:13.73#ibcon#read 4, iclass 14, count 0 2006.257.09:56:13.73#ibcon#about to read 5, iclass 14, count 0 2006.257.09:56:13.73#ibcon#read 5, iclass 14, count 0 2006.257.09:56:13.73#ibcon#about to read 6, iclass 14, count 0 2006.257.09:56:13.73#ibcon#read 6, iclass 14, count 0 2006.257.09:56:13.73#ibcon#end of sib2, iclass 14, count 0 2006.257.09:56:13.73#ibcon#*after write, iclass 14, count 0 2006.257.09:56:13.73#ibcon#*before return 0, iclass 14, count 0 2006.257.09:56:13.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:56:13.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.09:56:13.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.09:56:13.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.09:56:13.73$vck44/va=8,4 2006.257.09:56:13.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.09:56:13.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.09:56:13.73#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:13.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:56:13.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:56:13.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:56:13.79#ibcon#enter wrdev, iclass 16, count 2 2006.257.09:56:13.79#ibcon#first serial, iclass 16, count 2 2006.257.09:56:13.79#ibcon#enter sib2, iclass 16, count 2 2006.257.09:56:13.79#ibcon#flushed, iclass 16, count 2 2006.257.09:56:13.79#ibcon#about to write, iclass 16, count 2 2006.257.09:56:13.79#ibcon#wrote, iclass 16, count 2 2006.257.09:56:13.79#ibcon#about to read 3, iclass 16, count 2 2006.257.09:56:13.81#ibcon#read 3, iclass 16, count 2 2006.257.09:56:13.81#ibcon#about to read 4, iclass 16, count 2 2006.257.09:56:13.81#ibcon#read 4, iclass 16, count 2 2006.257.09:56:13.81#ibcon#about to read 5, iclass 16, count 2 2006.257.09:56:13.81#ibcon#read 5, iclass 16, count 2 2006.257.09:56:13.81#ibcon#about to read 6, iclass 16, count 2 2006.257.09:56:13.81#ibcon#read 6, iclass 16, count 2 2006.257.09:56:13.81#ibcon#end of sib2, iclass 16, count 2 2006.257.09:56:13.81#ibcon#*mode == 0, iclass 16, count 2 2006.257.09:56:13.81#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.09:56:13.81#ibcon#[25=AT08-04\r\n] 2006.257.09:56:13.81#ibcon#*before write, iclass 16, count 2 2006.257.09:56:13.81#ibcon#enter sib2, iclass 16, count 2 2006.257.09:56:13.81#ibcon#flushed, iclass 16, count 2 2006.257.09:56:13.81#ibcon#about to write, iclass 16, count 2 2006.257.09:56:13.81#ibcon#wrote, iclass 16, count 2 2006.257.09:56:13.81#ibcon#about to read 3, iclass 16, count 2 2006.257.09:56:13.84#ibcon#read 3, iclass 16, count 2 2006.257.09:56:13.84#ibcon#about to read 4, iclass 16, count 2 2006.257.09:56:13.84#ibcon#read 4, iclass 16, count 2 2006.257.09:56:13.84#ibcon#about to read 5, iclass 16, count 2 2006.257.09:56:13.84#ibcon#read 5, iclass 16, count 2 2006.257.09:56:13.84#ibcon#about to read 6, iclass 16, count 2 2006.257.09:56:13.84#ibcon#read 6, iclass 16, count 2 2006.257.09:56:13.84#ibcon#end of sib2, iclass 16, count 2 2006.257.09:56:13.84#ibcon#*after write, iclass 16, count 2 2006.257.09:56:13.84#ibcon#*before return 0, iclass 16, count 2 2006.257.09:56:13.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:56:13.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.09:56:13.84#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.09:56:13.84#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:13.84#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:56:13.96#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:56:13.96#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:56:13.96#ibcon#enter wrdev, iclass 16, count 0 2006.257.09:56:13.96#ibcon#first serial, iclass 16, count 0 2006.257.09:56:13.96#ibcon#enter sib2, iclass 16, count 0 2006.257.09:56:13.96#ibcon#flushed, iclass 16, count 0 2006.257.09:56:13.96#ibcon#about to write, iclass 16, count 0 2006.257.09:56:13.96#ibcon#wrote, iclass 16, count 0 2006.257.09:56:13.96#ibcon#about to read 3, iclass 16, count 0 2006.257.09:56:13.98#ibcon#read 3, iclass 16, count 0 2006.257.09:56:13.98#ibcon#about to read 4, iclass 16, count 0 2006.257.09:56:13.98#ibcon#read 4, iclass 16, count 0 2006.257.09:56:13.98#ibcon#about to read 5, iclass 16, count 0 2006.257.09:56:13.98#ibcon#read 5, iclass 16, count 0 2006.257.09:56:13.98#ibcon#about to read 6, iclass 16, count 0 2006.257.09:56:13.98#ibcon#read 6, iclass 16, count 0 2006.257.09:56:13.98#ibcon#end of sib2, iclass 16, count 0 2006.257.09:56:13.98#ibcon#*mode == 0, iclass 16, count 0 2006.257.09:56:13.98#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.09:56:13.98#ibcon#[25=USB\r\n] 2006.257.09:56:13.98#ibcon#*before write, iclass 16, count 0 2006.257.09:56:13.98#ibcon#enter sib2, iclass 16, count 0 2006.257.09:56:13.98#ibcon#flushed, iclass 16, count 0 2006.257.09:56:13.98#ibcon#about to write, iclass 16, count 0 2006.257.09:56:13.98#ibcon#wrote, iclass 16, count 0 2006.257.09:56:13.98#ibcon#about to read 3, iclass 16, count 0 2006.257.09:56:14.01#ibcon#read 3, iclass 16, count 0 2006.257.09:56:14.01#ibcon#about to read 4, iclass 16, count 0 2006.257.09:56:14.01#ibcon#read 4, iclass 16, count 0 2006.257.09:56:14.01#ibcon#about to read 5, iclass 16, count 0 2006.257.09:56:14.01#ibcon#read 5, iclass 16, count 0 2006.257.09:56:14.01#ibcon#about to read 6, iclass 16, count 0 2006.257.09:56:14.01#ibcon#read 6, iclass 16, count 0 2006.257.09:56:14.01#ibcon#end of sib2, iclass 16, count 0 2006.257.09:56:14.01#ibcon#*after write, iclass 16, count 0 2006.257.09:56:14.01#ibcon#*before return 0, iclass 16, count 0 2006.257.09:56:14.01#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:56:14.01#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.09:56:14.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.09:56:14.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.09:56:14.01$vck44/vblo=1,629.99 2006.257.09:56:14.01#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.09:56:14.01#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.09:56:14.01#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:14.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:56:14.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:56:14.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:56:14.01#ibcon#enter wrdev, iclass 18, count 0 2006.257.09:56:14.01#ibcon#first serial, iclass 18, count 0 2006.257.09:56:14.01#ibcon#enter sib2, iclass 18, count 0 2006.257.09:56:14.01#ibcon#flushed, iclass 18, count 0 2006.257.09:56:14.01#ibcon#about to write, iclass 18, count 0 2006.257.09:56:14.01#ibcon#wrote, iclass 18, count 0 2006.257.09:56:14.01#ibcon#about to read 3, iclass 18, count 0 2006.257.09:56:14.03#ibcon#read 3, iclass 18, count 0 2006.257.09:56:14.03#ibcon#about to read 4, iclass 18, count 0 2006.257.09:56:14.03#ibcon#read 4, iclass 18, count 0 2006.257.09:56:14.03#ibcon#about to read 5, iclass 18, count 0 2006.257.09:56:14.03#ibcon#read 5, iclass 18, count 0 2006.257.09:56:14.03#ibcon#about to read 6, iclass 18, count 0 2006.257.09:56:14.03#ibcon#read 6, iclass 18, count 0 2006.257.09:56:14.03#ibcon#end of sib2, iclass 18, count 0 2006.257.09:56:14.03#ibcon#*mode == 0, iclass 18, count 0 2006.257.09:56:14.03#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.09:56:14.03#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.09:56:14.03#ibcon#*before write, iclass 18, count 0 2006.257.09:56:14.03#ibcon#enter sib2, iclass 18, count 0 2006.257.09:56:14.03#ibcon#flushed, iclass 18, count 0 2006.257.09:56:14.03#ibcon#about to write, iclass 18, count 0 2006.257.09:56:14.03#ibcon#wrote, iclass 18, count 0 2006.257.09:56:14.03#ibcon#about to read 3, iclass 18, count 0 2006.257.09:56:14.07#ibcon#read 3, iclass 18, count 0 2006.257.09:56:14.07#ibcon#about to read 4, iclass 18, count 0 2006.257.09:56:14.07#ibcon#read 4, iclass 18, count 0 2006.257.09:56:14.07#ibcon#about to read 5, iclass 18, count 0 2006.257.09:56:14.07#ibcon#read 5, iclass 18, count 0 2006.257.09:56:14.07#ibcon#about to read 6, iclass 18, count 0 2006.257.09:56:14.07#ibcon#read 6, iclass 18, count 0 2006.257.09:56:14.07#ibcon#end of sib2, iclass 18, count 0 2006.257.09:56:14.07#ibcon#*after write, iclass 18, count 0 2006.257.09:56:14.07#ibcon#*before return 0, iclass 18, count 0 2006.257.09:56:14.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:56:14.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.09:56:14.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.09:56:14.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.09:56:14.07$vck44/vb=1,4 2006.257.09:56:14.07#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.09:56:14.07#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.09:56:14.07#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:14.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:56:14.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:56:14.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:56:14.07#ibcon#enter wrdev, iclass 20, count 2 2006.257.09:56:14.07#ibcon#first serial, iclass 20, count 2 2006.257.09:56:14.07#ibcon#enter sib2, iclass 20, count 2 2006.257.09:56:14.07#ibcon#flushed, iclass 20, count 2 2006.257.09:56:14.07#ibcon#about to write, iclass 20, count 2 2006.257.09:56:14.07#ibcon#wrote, iclass 20, count 2 2006.257.09:56:14.07#ibcon#about to read 3, iclass 20, count 2 2006.257.09:56:14.09#ibcon#read 3, iclass 20, count 2 2006.257.09:56:14.09#ibcon#about to read 4, iclass 20, count 2 2006.257.09:56:14.09#ibcon#read 4, iclass 20, count 2 2006.257.09:56:14.09#ibcon#about to read 5, iclass 20, count 2 2006.257.09:56:14.09#ibcon#read 5, iclass 20, count 2 2006.257.09:56:14.09#ibcon#about to read 6, iclass 20, count 2 2006.257.09:56:14.09#ibcon#read 6, iclass 20, count 2 2006.257.09:56:14.09#ibcon#end of sib2, iclass 20, count 2 2006.257.09:56:14.09#ibcon#*mode == 0, iclass 20, count 2 2006.257.09:56:14.09#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.09:56:14.09#ibcon#[27=AT01-04\r\n] 2006.257.09:56:14.09#ibcon#*before write, iclass 20, count 2 2006.257.09:56:14.09#ibcon#enter sib2, iclass 20, count 2 2006.257.09:56:14.09#ibcon#flushed, iclass 20, count 2 2006.257.09:56:14.09#ibcon#about to write, iclass 20, count 2 2006.257.09:56:14.09#ibcon#wrote, iclass 20, count 2 2006.257.09:56:14.09#ibcon#about to read 3, iclass 20, count 2 2006.257.09:56:14.12#ibcon#read 3, iclass 20, count 2 2006.257.09:56:14.12#ibcon#about to read 4, iclass 20, count 2 2006.257.09:56:14.12#ibcon#read 4, iclass 20, count 2 2006.257.09:56:14.12#ibcon#about to read 5, iclass 20, count 2 2006.257.09:56:14.12#ibcon#read 5, iclass 20, count 2 2006.257.09:56:14.12#ibcon#about to read 6, iclass 20, count 2 2006.257.09:56:14.12#ibcon#read 6, iclass 20, count 2 2006.257.09:56:14.12#ibcon#end of sib2, iclass 20, count 2 2006.257.09:56:14.12#ibcon#*after write, iclass 20, count 2 2006.257.09:56:14.12#ibcon#*before return 0, iclass 20, count 2 2006.257.09:56:14.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:56:14.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.09:56:14.12#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.09:56:14.12#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:14.12#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:56:14.24#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:56:14.24#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:56:14.24#ibcon#enter wrdev, iclass 20, count 0 2006.257.09:56:14.24#ibcon#first serial, iclass 20, count 0 2006.257.09:56:14.24#ibcon#enter sib2, iclass 20, count 0 2006.257.09:56:14.24#ibcon#flushed, iclass 20, count 0 2006.257.09:56:14.24#ibcon#about to write, iclass 20, count 0 2006.257.09:56:14.24#ibcon#wrote, iclass 20, count 0 2006.257.09:56:14.24#ibcon#about to read 3, iclass 20, count 0 2006.257.09:56:14.26#ibcon#read 3, iclass 20, count 0 2006.257.09:56:14.26#ibcon#about to read 4, iclass 20, count 0 2006.257.09:56:14.26#ibcon#read 4, iclass 20, count 0 2006.257.09:56:14.26#ibcon#about to read 5, iclass 20, count 0 2006.257.09:56:14.26#ibcon#read 5, iclass 20, count 0 2006.257.09:56:14.26#ibcon#about to read 6, iclass 20, count 0 2006.257.09:56:14.26#ibcon#read 6, iclass 20, count 0 2006.257.09:56:14.26#ibcon#end of sib2, iclass 20, count 0 2006.257.09:56:14.26#ibcon#*mode == 0, iclass 20, count 0 2006.257.09:56:14.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.09:56:14.26#ibcon#[27=USB\r\n] 2006.257.09:56:14.26#ibcon#*before write, iclass 20, count 0 2006.257.09:56:14.26#ibcon#enter sib2, iclass 20, count 0 2006.257.09:56:14.26#ibcon#flushed, iclass 20, count 0 2006.257.09:56:14.26#ibcon#about to write, iclass 20, count 0 2006.257.09:56:14.26#ibcon#wrote, iclass 20, count 0 2006.257.09:56:14.26#ibcon#about to read 3, iclass 20, count 0 2006.257.09:56:14.29#ibcon#read 3, iclass 20, count 0 2006.257.09:56:14.29#ibcon#about to read 4, iclass 20, count 0 2006.257.09:56:14.29#ibcon#read 4, iclass 20, count 0 2006.257.09:56:14.29#ibcon#about to read 5, iclass 20, count 0 2006.257.09:56:14.29#ibcon#read 5, iclass 20, count 0 2006.257.09:56:14.29#ibcon#about to read 6, iclass 20, count 0 2006.257.09:56:14.29#ibcon#read 6, iclass 20, count 0 2006.257.09:56:14.29#ibcon#end of sib2, iclass 20, count 0 2006.257.09:56:14.29#ibcon#*after write, iclass 20, count 0 2006.257.09:56:14.29#ibcon#*before return 0, iclass 20, count 0 2006.257.09:56:14.29#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:56:14.29#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.09:56:14.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.09:56:14.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.09:56:14.29$vck44/vblo=2,634.99 2006.257.09:56:14.29#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.09:56:14.29#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.09:56:14.29#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:14.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:14.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:14.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:14.29#ibcon#enter wrdev, iclass 22, count 0 2006.257.09:56:14.29#ibcon#first serial, iclass 22, count 0 2006.257.09:56:14.29#ibcon#enter sib2, iclass 22, count 0 2006.257.09:56:14.29#ibcon#flushed, iclass 22, count 0 2006.257.09:56:14.29#ibcon#about to write, iclass 22, count 0 2006.257.09:56:14.29#ibcon#wrote, iclass 22, count 0 2006.257.09:56:14.29#ibcon#about to read 3, iclass 22, count 0 2006.257.09:56:14.31#ibcon#read 3, iclass 22, count 0 2006.257.09:56:14.31#ibcon#about to read 4, iclass 22, count 0 2006.257.09:56:14.31#ibcon#read 4, iclass 22, count 0 2006.257.09:56:14.31#ibcon#about to read 5, iclass 22, count 0 2006.257.09:56:14.31#ibcon#read 5, iclass 22, count 0 2006.257.09:56:14.31#ibcon#about to read 6, iclass 22, count 0 2006.257.09:56:14.31#ibcon#read 6, iclass 22, count 0 2006.257.09:56:14.31#ibcon#end of sib2, iclass 22, count 0 2006.257.09:56:14.31#ibcon#*mode == 0, iclass 22, count 0 2006.257.09:56:14.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.09:56:14.31#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.09:56:14.31#ibcon#*before write, iclass 22, count 0 2006.257.09:56:14.31#ibcon#enter sib2, iclass 22, count 0 2006.257.09:56:14.31#ibcon#flushed, iclass 22, count 0 2006.257.09:56:14.31#ibcon#about to write, iclass 22, count 0 2006.257.09:56:14.31#ibcon#wrote, iclass 22, count 0 2006.257.09:56:14.31#ibcon#about to read 3, iclass 22, count 0 2006.257.09:56:14.35#ibcon#read 3, iclass 22, count 0 2006.257.09:56:14.35#ibcon#about to read 4, iclass 22, count 0 2006.257.09:56:14.35#ibcon#read 4, iclass 22, count 0 2006.257.09:56:14.35#ibcon#about to read 5, iclass 22, count 0 2006.257.09:56:14.35#ibcon#read 5, iclass 22, count 0 2006.257.09:56:14.35#ibcon#about to read 6, iclass 22, count 0 2006.257.09:56:14.35#ibcon#read 6, iclass 22, count 0 2006.257.09:56:14.35#ibcon#end of sib2, iclass 22, count 0 2006.257.09:56:14.35#ibcon#*after write, iclass 22, count 0 2006.257.09:56:14.35#ibcon#*before return 0, iclass 22, count 0 2006.257.09:56:14.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:14.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.09:56:14.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.09:56:14.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.09:56:14.35$vck44/vb=2,5 2006.257.09:56:14.35#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.09:56:14.35#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.09:56:14.35#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:14.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:14.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:14.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:14.41#ibcon#enter wrdev, iclass 24, count 2 2006.257.09:56:14.41#ibcon#first serial, iclass 24, count 2 2006.257.09:56:14.41#ibcon#enter sib2, iclass 24, count 2 2006.257.09:56:14.41#ibcon#flushed, iclass 24, count 2 2006.257.09:56:14.41#ibcon#about to write, iclass 24, count 2 2006.257.09:56:14.41#ibcon#wrote, iclass 24, count 2 2006.257.09:56:14.41#ibcon#about to read 3, iclass 24, count 2 2006.257.09:56:14.43#ibcon#read 3, iclass 24, count 2 2006.257.09:56:14.43#ibcon#about to read 4, iclass 24, count 2 2006.257.09:56:14.43#ibcon#read 4, iclass 24, count 2 2006.257.09:56:14.43#ibcon#about to read 5, iclass 24, count 2 2006.257.09:56:14.43#ibcon#read 5, iclass 24, count 2 2006.257.09:56:14.43#ibcon#about to read 6, iclass 24, count 2 2006.257.09:56:14.43#ibcon#read 6, iclass 24, count 2 2006.257.09:56:14.43#ibcon#end of sib2, iclass 24, count 2 2006.257.09:56:14.43#ibcon#*mode == 0, iclass 24, count 2 2006.257.09:56:14.43#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.09:56:14.43#ibcon#[27=AT02-05\r\n] 2006.257.09:56:14.43#ibcon#*before write, iclass 24, count 2 2006.257.09:56:14.43#ibcon#enter sib2, iclass 24, count 2 2006.257.09:56:14.43#ibcon#flushed, iclass 24, count 2 2006.257.09:56:14.43#ibcon#about to write, iclass 24, count 2 2006.257.09:56:14.43#ibcon#wrote, iclass 24, count 2 2006.257.09:56:14.43#ibcon#about to read 3, iclass 24, count 2 2006.257.09:56:14.46#ibcon#read 3, iclass 24, count 2 2006.257.09:56:14.46#ibcon#about to read 4, iclass 24, count 2 2006.257.09:56:14.46#ibcon#read 4, iclass 24, count 2 2006.257.09:56:14.46#ibcon#about to read 5, iclass 24, count 2 2006.257.09:56:14.46#ibcon#read 5, iclass 24, count 2 2006.257.09:56:14.46#ibcon#about to read 6, iclass 24, count 2 2006.257.09:56:14.46#ibcon#read 6, iclass 24, count 2 2006.257.09:56:14.46#ibcon#end of sib2, iclass 24, count 2 2006.257.09:56:14.46#ibcon#*after write, iclass 24, count 2 2006.257.09:56:14.46#ibcon#*before return 0, iclass 24, count 2 2006.257.09:56:14.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:14.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.09:56:14.46#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.09:56:14.46#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:14.46#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:14.58#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:14.58#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:14.58#ibcon#enter wrdev, iclass 24, count 0 2006.257.09:56:14.58#ibcon#first serial, iclass 24, count 0 2006.257.09:56:14.58#ibcon#enter sib2, iclass 24, count 0 2006.257.09:56:14.58#ibcon#flushed, iclass 24, count 0 2006.257.09:56:14.58#ibcon#about to write, iclass 24, count 0 2006.257.09:56:14.58#ibcon#wrote, iclass 24, count 0 2006.257.09:56:14.58#ibcon#about to read 3, iclass 24, count 0 2006.257.09:56:14.60#ibcon#read 3, iclass 24, count 0 2006.257.09:56:14.60#ibcon#about to read 4, iclass 24, count 0 2006.257.09:56:14.60#ibcon#read 4, iclass 24, count 0 2006.257.09:56:14.60#ibcon#about to read 5, iclass 24, count 0 2006.257.09:56:14.60#ibcon#read 5, iclass 24, count 0 2006.257.09:56:14.60#ibcon#about to read 6, iclass 24, count 0 2006.257.09:56:14.60#ibcon#read 6, iclass 24, count 0 2006.257.09:56:14.60#ibcon#end of sib2, iclass 24, count 0 2006.257.09:56:14.60#ibcon#*mode == 0, iclass 24, count 0 2006.257.09:56:14.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.09:56:14.60#ibcon#[27=USB\r\n] 2006.257.09:56:14.60#ibcon#*before write, iclass 24, count 0 2006.257.09:56:14.60#ibcon#enter sib2, iclass 24, count 0 2006.257.09:56:14.60#ibcon#flushed, iclass 24, count 0 2006.257.09:56:14.60#ibcon#about to write, iclass 24, count 0 2006.257.09:56:14.60#ibcon#wrote, iclass 24, count 0 2006.257.09:56:14.60#ibcon#about to read 3, iclass 24, count 0 2006.257.09:56:14.63#ibcon#read 3, iclass 24, count 0 2006.257.09:56:14.63#ibcon#about to read 4, iclass 24, count 0 2006.257.09:56:14.63#ibcon#read 4, iclass 24, count 0 2006.257.09:56:14.63#ibcon#about to read 5, iclass 24, count 0 2006.257.09:56:14.63#ibcon#read 5, iclass 24, count 0 2006.257.09:56:14.63#ibcon#about to read 6, iclass 24, count 0 2006.257.09:56:14.63#ibcon#read 6, iclass 24, count 0 2006.257.09:56:14.63#ibcon#end of sib2, iclass 24, count 0 2006.257.09:56:14.63#ibcon#*after write, iclass 24, count 0 2006.257.09:56:14.63#ibcon#*before return 0, iclass 24, count 0 2006.257.09:56:14.63#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:14.63#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.09:56:14.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.09:56:14.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.09:56:14.63$vck44/vblo=3,649.99 2006.257.09:56:14.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.09:56:14.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.09:56:14.63#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:14.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:14.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:14.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:14.63#ibcon#enter wrdev, iclass 26, count 0 2006.257.09:56:14.63#ibcon#first serial, iclass 26, count 0 2006.257.09:56:14.63#ibcon#enter sib2, iclass 26, count 0 2006.257.09:56:14.63#ibcon#flushed, iclass 26, count 0 2006.257.09:56:14.63#ibcon#about to write, iclass 26, count 0 2006.257.09:56:14.63#ibcon#wrote, iclass 26, count 0 2006.257.09:56:14.63#ibcon#about to read 3, iclass 26, count 0 2006.257.09:56:14.67#ibcon#read 3, iclass 26, count 0 2006.257.09:56:14.67#ibcon#about to read 4, iclass 26, count 0 2006.257.09:56:14.67#ibcon#read 4, iclass 26, count 0 2006.257.09:56:14.67#ibcon#about to read 5, iclass 26, count 0 2006.257.09:56:14.67#ibcon#read 5, iclass 26, count 0 2006.257.09:56:14.67#ibcon#about to read 6, iclass 26, count 0 2006.257.09:56:14.67#ibcon#read 6, iclass 26, count 0 2006.257.09:56:14.67#ibcon#end of sib2, iclass 26, count 0 2006.257.09:56:14.67#ibcon#*mode == 0, iclass 26, count 0 2006.257.09:56:14.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.09:56:14.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.09:56:14.67#ibcon#*before write, iclass 26, count 0 2006.257.09:56:14.68#ibcon#enter sib2, iclass 26, count 0 2006.257.09:56:14.68#ibcon#flushed, iclass 26, count 0 2006.257.09:56:14.68#ibcon#about to write, iclass 26, count 0 2006.257.09:56:14.68#ibcon#wrote, iclass 26, count 0 2006.257.09:56:14.68#ibcon#about to read 3, iclass 26, count 0 2006.257.09:56:14.72#ibcon#read 3, iclass 26, count 0 2006.257.09:56:14.72#ibcon#about to read 4, iclass 26, count 0 2006.257.09:56:14.72#ibcon#read 4, iclass 26, count 0 2006.257.09:56:14.72#ibcon#about to read 5, iclass 26, count 0 2006.257.09:56:14.72#ibcon#read 5, iclass 26, count 0 2006.257.09:56:14.72#ibcon#about to read 6, iclass 26, count 0 2006.257.09:56:14.72#ibcon#read 6, iclass 26, count 0 2006.257.09:56:14.72#ibcon#end of sib2, iclass 26, count 0 2006.257.09:56:14.72#ibcon#*after write, iclass 26, count 0 2006.257.09:56:14.72#ibcon#*before return 0, iclass 26, count 0 2006.257.09:56:14.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:14.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.09:56:14.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.09:56:14.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.09:56:14.72$vck44/vb=3,4 2006.257.09:56:14.72#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.09:56:14.72#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.09:56:14.72#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:14.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:14.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:14.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:14.75#ibcon#enter wrdev, iclass 28, count 2 2006.257.09:56:14.75#ibcon#first serial, iclass 28, count 2 2006.257.09:56:14.75#ibcon#enter sib2, iclass 28, count 2 2006.257.09:56:14.75#ibcon#flushed, iclass 28, count 2 2006.257.09:56:14.75#ibcon#about to write, iclass 28, count 2 2006.257.09:56:14.75#ibcon#wrote, iclass 28, count 2 2006.257.09:56:14.75#ibcon#about to read 3, iclass 28, count 2 2006.257.09:56:14.77#ibcon#read 3, iclass 28, count 2 2006.257.09:56:14.77#ibcon#about to read 4, iclass 28, count 2 2006.257.09:56:14.77#ibcon#read 4, iclass 28, count 2 2006.257.09:56:14.77#ibcon#about to read 5, iclass 28, count 2 2006.257.09:56:14.77#ibcon#read 5, iclass 28, count 2 2006.257.09:56:14.77#ibcon#about to read 6, iclass 28, count 2 2006.257.09:56:14.77#ibcon#read 6, iclass 28, count 2 2006.257.09:56:14.77#ibcon#end of sib2, iclass 28, count 2 2006.257.09:56:14.77#ibcon#*mode == 0, iclass 28, count 2 2006.257.09:56:14.77#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.09:56:14.77#ibcon#[27=AT03-04\r\n] 2006.257.09:56:14.77#ibcon#*before write, iclass 28, count 2 2006.257.09:56:14.77#ibcon#enter sib2, iclass 28, count 2 2006.257.09:56:14.77#ibcon#flushed, iclass 28, count 2 2006.257.09:56:14.77#ibcon#about to write, iclass 28, count 2 2006.257.09:56:14.77#ibcon#wrote, iclass 28, count 2 2006.257.09:56:14.77#ibcon#about to read 3, iclass 28, count 2 2006.257.09:56:14.80#ibcon#read 3, iclass 28, count 2 2006.257.09:56:14.80#ibcon#about to read 4, iclass 28, count 2 2006.257.09:56:14.80#ibcon#read 4, iclass 28, count 2 2006.257.09:56:14.80#ibcon#about to read 5, iclass 28, count 2 2006.257.09:56:14.80#ibcon#read 5, iclass 28, count 2 2006.257.09:56:14.80#ibcon#about to read 6, iclass 28, count 2 2006.257.09:56:14.80#ibcon#read 6, iclass 28, count 2 2006.257.09:56:14.80#ibcon#end of sib2, iclass 28, count 2 2006.257.09:56:14.80#ibcon#*after write, iclass 28, count 2 2006.257.09:56:14.80#ibcon#*before return 0, iclass 28, count 2 2006.257.09:56:14.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:14.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.09:56:14.80#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.09:56:14.80#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:14.80#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:14.92#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:14.92#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:14.92#ibcon#enter wrdev, iclass 28, count 0 2006.257.09:56:14.92#ibcon#first serial, iclass 28, count 0 2006.257.09:56:14.92#ibcon#enter sib2, iclass 28, count 0 2006.257.09:56:14.92#ibcon#flushed, iclass 28, count 0 2006.257.09:56:14.92#ibcon#about to write, iclass 28, count 0 2006.257.09:56:14.92#ibcon#wrote, iclass 28, count 0 2006.257.09:56:14.92#ibcon#about to read 3, iclass 28, count 0 2006.257.09:56:14.94#ibcon#read 3, iclass 28, count 0 2006.257.09:56:14.94#ibcon#about to read 4, iclass 28, count 0 2006.257.09:56:14.94#ibcon#read 4, iclass 28, count 0 2006.257.09:56:14.94#ibcon#about to read 5, iclass 28, count 0 2006.257.09:56:14.94#ibcon#read 5, iclass 28, count 0 2006.257.09:56:14.94#ibcon#about to read 6, iclass 28, count 0 2006.257.09:56:14.94#ibcon#read 6, iclass 28, count 0 2006.257.09:56:14.94#ibcon#end of sib2, iclass 28, count 0 2006.257.09:56:14.94#ibcon#*mode == 0, iclass 28, count 0 2006.257.09:56:14.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.09:56:14.94#ibcon#[27=USB\r\n] 2006.257.09:56:14.94#ibcon#*before write, iclass 28, count 0 2006.257.09:56:14.94#ibcon#enter sib2, iclass 28, count 0 2006.257.09:56:14.94#ibcon#flushed, iclass 28, count 0 2006.257.09:56:14.94#ibcon#about to write, iclass 28, count 0 2006.257.09:56:14.94#ibcon#wrote, iclass 28, count 0 2006.257.09:56:14.94#ibcon#about to read 3, iclass 28, count 0 2006.257.09:56:14.97#ibcon#read 3, iclass 28, count 0 2006.257.09:56:14.97#ibcon#about to read 4, iclass 28, count 0 2006.257.09:56:14.97#ibcon#read 4, iclass 28, count 0 2006.257.09:56:14.97#ibcon#about to read 5, iclass 28, count 0 2006.257.09:56:14.97#ibcon#read 5, iclass 28, count 0 2006.257.09:56:14.97#ibcon#about to read 6, iclass 28, count 0 2006.257.09:56:14.97#ibcon#read 6, iclass 28, count 0 2006.257.09:56:14.97#ibcon#end of sib2, iclass 28, count 0 2006.257.09:56:14.97#ibcon#*after write, iclass 28, count 0 2006.257.09:56:14.97#ibcon#*before return 0, iclass 28, count 0 2006.257.09:56:14.97#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:14.97#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.09:56:14.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.09:56:14.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.09:56:14.97$vck44/vblo=4,679.99 2006.257.09:56:14.97#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.09:56:14.97#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.09:56:14.97#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:14.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:14.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:14.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:14.97#ibcon#enter wrdev, iclass 30, count 0 2006.257.09:56:14.97#ibcon#first serial, iclass 30, count 0 2006.257.09:56:14.97#ibcon#enter sib2, iclass 30, count 0 2006.257.09:56:14.97#ibcon#flushed, iclass 30, count 0 2006.257.09:56:14.97#ibcon#about to write, iclass 30, count 0 2006.257.09:56:14.97#ibcon#wrote, iclass 30, count 0 2006.257.09:56:14.97#ibcon#about to read 3, iclass 30, count 0 2006.257.09:56:14.99#ibcon#read 3, iclass 30, count 0 2006.257.09:56:14.99#ibcon#about to read 4, iclass 30, count 0 2006.257.09:56:14.99#ibcon#read 4, iclass 30, count 0 2006.257.09:56:14.99#ibcon#about to read 5, iclass 30, count 0 2006.257.09:56:14.99#ibcon#read 5, iclass 30, count 0 2006.257.09:56:14.99#ibcon#about to read 6, iclass 30, count 0 2006.257.09:56:14.99#ibcon#read 6, iclass 30, count 0 2006.257.09:56:14.99#ibcon#end of sib2, iclass 30, count 0 2006.257.09:56:14.99#ibcon#*mode == 0, iclass 30, count 0 2006.257.09:56:14.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.09:56:14.99#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.09:56:14.99#ibcon#*before write, iclass 30, count 0 2006.257.09:56:14.99#ibcon#enter sib2, iclass 30, count 0 2006.257.09:56:14.99#ibcon#flushed, iclass 30, count 0 2006.257.09:56:14.99#ibcon#about to write, iclass 30, count 0 2006.257.09:56:14.99#ibcon#wrote, iclass 30, count 0 2006.257.09:56:14.99#ibcon#about to read 3, iclass 30, count 0 2006.257.09:56:15.03#ibcon#read 3, iclass 30, count 0 2006.257.09:56:15.03#ibcon#about to read 4, iclass 30, count 0 2006.257.09:56:15.03#ibcon#read 4, iclass 30, count 0 2006.257.09:56:15.03#ibcon#about to read 5, iclass 30, count 0 2006.257.09:56:15.03#ibcon#read 5, iclass 30, count 0 2006.257.09:56:15.03#ibcon#about to read 6, iclass 30, count 0 2006.257.09:56:15.03#ibcon#read 6, iclass 30, count 0 2006.257.09:56:15.03#ibcon#end of sib2, iclass 30, count 0 2006.257.09:56:15.03#ibcon#*after write, iclass 30, count 0 2006.257.09:56:15.03#ibcon#*before return 0, iclass 30, count 0 2006.257.09:56:15.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:15.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.09:56:15.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.09:56:15.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.09:56:15.03$vck44/vb=4,5 2006.257.09:56:15.03#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.09:56:15.03#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.09:56:15.03#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:15.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:15.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:15.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:15.09#ibcon#enter wrdev, iclass 32, count 2 2006.257.09:56:15.09#ibcon#first serial, iclass 32, count 2 2006.257.09:56:15.09#ibcon#enter sib2, iclass 32, count 2 2006.257.09:56:15.09#ibcon#flushed, iclass 32, count 2 2006.257.09:56:15.09#ibcon#about to write, iclass 32, count 2 2006.257.09:56:15.09#ibcon#wrote, iclass 32, count 2 2006.257.09:56:15.09#ibcon#about to read 3, iclass 32, count 2 2006.257.09:56:15.11#ibcon#read 3, iclass 32, count 2 2006.257.09:56:15.11#ibcon#about to read 4, iclass 32, count 2 2006.257.09:56:15.11#ibcon#read 4, iclass 32, count 2 2006.257.09:56:15.11#ibcon#about to read 5, iclass 32, count 2 2006.257.09:56:15.11#ibcon#read 5, iclass 32, count 2 2006.257.09:56:15.11#ibcon#about to read 6, iclass 32, count 2 2006.257.09:56:15.11#ibcon#read 6, iclass 32, count 2 2006.257.09:56:15.11#ibcon#end of sib2, iclass 32, count 2 2006.257.09:56:15.11#ibcon#*mode == 0, iclass 32, count 2 2006.257.09:56:15.11#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.09:56:15.11#ibcon#[27=AT04-05\r\n] 2006.257.09:56:15.11#ibcon#*before write, iclass 32, count 2 2006.257.09:56:15.11#ibcon#enter sib2, iclass 32, count 2 2006.257.09:56:15.11#ibcon#flushed, iclass 32, count 2 2006.257.09:56:15.11#ibcon#about to write, iclass 32, count 2 2006.257.09:56:15.11#ibcon#wrote, iclass 32, count 2 2006.257.09:56:15.11#ibcon#about to read 3, iclass 32, count 2 2006.257.09:56:15.14#ibcon#read 3, iclass 32, count 2 2006.257.09:56:15.14#ibcon#about to read 4, iclass 32, count 2 2006.257.09:56:15.14#ibcon#read 4, iclass 32, count 2 2006.257.09:56:15.14#ibcon#about to read 5, iclass 32, count 2 2006.257.09:56:15.14#ibcon#read 5, iclass 32, count 2 2006.257.09:56:15.14#ibcon#about to read 6, iclass 32, count 2 2006.257.09:56:15.14#ibcon#read 6, iclass 32, count 2 2006.257.09:56:15.14#ibcon#end of sib2, iclass 32, count 2 2006.257.09:56:15.14#ibcon#*after write, iclass 32, count 2 2006.257.09:56:15.14#ibcon#*before return 0, iclass 32, count 2 2006.257.09:56:15.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:15.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.09:56:15.14#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.09:56:15.14#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:15.14#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:15.26#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:15.26#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:15.26#ibcon#enter wrdev, iclass 32, count 0 2006.257.09:56:15.26#ibcon#first serial, iclass 32, count 0 2006.257.09:56:15.26#ibcon#enter sib2, iclass 32, count 0 2006.257.09:56:15.26#ibcon#flushed, iclass 32, count 0 2006.257.09:56:15.26#ibcon#about to write, iclass 32, count 0 2006.257.09:56:15.26#ibcon#wrote, iclass 32, count 0 2006.257.09:56:15.26#ibcon#about to read 3, iclass 32, count 0 2006.257.09:56:15.28#ibcon#read 3, iclass 32, count 0 2006.257.09:56:15.28#ibcon#about to read 4, iclass 32, count 0 2006.257.09:56:15.28#ibcon#read 4, iclass 32, count 0 2006.257.09:56:15.28#ibcon#about to read 5, iclass 32, count 0 2006.257.09:56:15.28#ibcon#read 5, iclass 32, count 0 2006.257.09:56:15.28#ibcon#about to read 6, iclass 32, count 0 2006.257.09:56:15.28#ibcon#read 6, iclass 32, count 0 2006.257.09:56:15.28#ibcon#end of sib2, iclass 32, count 0 2006.257.09:56:15.28#ibcon#*mode == 0, iclass 32, count 0 2006.257.09:56:15.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.09:56:15.28#ibcon#[27=USB\r\n] 2006.257.09:56:15.28#ibcon#*before write, iclass 32, count 0 2006.257.09:56:15.28#ibcon#enter sib2, iclass 32, count 0 2006.257.09:56:15.28#ibcon#flushed, iclass 32, count 0 2006.257.09:56:15.28#ibcon#about to write, iclass 32, count 0 2006.257.09:56:15.28#ibcon#wrote, iclass 32, count 0 2006.257.09:56:15.28#ibcon#about to read 3, iclass 32, count 0 2006.257.09:56:15.31#ibcon#read 3, iclass 32, count 0 2006.257.09:56:15.31#ibcon#about to read 4, iclass 32, count 0 2006.257.09:56:15.31#ibcon#read 4, iclass 32, count 0 2006.257.09:56:15.31#ibcon#about to read 5, iclass 32, count 0 2006.257.09:56:15.31#ibcon#read 5, iclass 32, count 0 2006.257.09:56:15.31#ibcon#about to read 6, iclass 32, count 0 2006.257.09:56:15.31#ibcon#read 6, iclass 32, count 0 2006.257.09:56:15.31#ibcon#end of sib2, iclass 32, count 0 2006.257.09:56:15.31#ibcon#*after write, iclass 32, count 0 2006.257.09:56:15.31#ibcon#*before return 0, iclass 32, count 0 2006.257.09:56:15.31#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:15.31#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.09:56:15.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.09:56:15.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.09:56:15.31$vck44/vblo=5,709.99 2006.257.09:56:15.31#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.09:56:15.31#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.09:56:15.31#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:15.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:15.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:15.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:15.31#ibcon#enter wrdev, iclass 34, count 0 2006.257.09:56:15.31#ibcon#first serial, iclass 34, count 0 2006.257.09:56:15.31#ibcon#enter sib2, iclass 34, count 0 2006.257.09:56:15.31#ibcon#flushed, iclass 34, count 0 2006.257.09:56:15.31#ibcon#about to write, iclass 34, count 0 2006.257.09:56:15.31#ibcon#wrote, iclass 34, count 0 2006.257.09:56:15.31#ibcon#about to read 3, iclass 34, count 0 2006.257.09:56:15.33#ibcon#read 3, iclass 34, count 0 2006.257.09:56:15.33#ibcon#about to read 4, iclass 34, count 0 2006.257.09:56:15.33#ibcon#read 4, iclass 34, count 0 2006.257.09:56:15.33#ibcon#about to read 5, iclass 34, count 0 2006.257.09:56:15.33#ibcon#read 5, iclass 34, count 0 2006.257.09:56:15.33#ibcon#about to read 6, iclass 34, count 0 2006.257.09:56:15.33#ibcon#read 6, iclass 34, count 0 2006.257.09:56:15.33#ibcon#end of sib2, iclass 34, count 0 2006.257.09:56:15.33#ibcon#*mode == 0, iclass 34, count 0 2006.257.09:56:15.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.09:56:15.33#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.09:56:15.33#ibcon#*before write, iclass 34, count 0 2006.257.09:56:15.33#ibcon#enter sib2, iclass 34, count 0 2006.257.09:56:15.33#ibcon#flushed, iclass 34, count 0 2006.257.09:56:15.33#ibcon#about to write, iclass 34, count 0 2006.257.09:56:15.33#ibcon#wrote, iclass 34, count 0 2006.257.09:56:15.33#ibcon#about to read 3, iclass 34, count 0 2006.257.09:56:15.37#ibcon#read 3, iclass 34, count 0 2006.257.09:56:15.37#ibcon#about to read 4, iclass 34, count 0 2006.257.09:56:15.37#ibcon#read 4, iclass 34, count 0 2006.257.09:56:15.37#ibcon#about to read 5, iclass 34, count 0 2006.257.09:56:15.37#ibcon#read 5, iclass 34, count 0 2006.257.09:56:15.37#ibcon#about to read 6, iclass 34, count 0 2006.257.09:56:15.37#ibcon#read 6, iclass 34, count 0 2006.257.09:56:15.37#ibcon#end of sib2, iclass 34, count 0 2006.257.09:56:15.37#ibcon#*after write, iclass 34, count 0 2006.257.09:56:15.37#ibcon#*before return 0, iclass 34, count 0 2006.257.09:56:15.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:15.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.09:56:15.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.09:56:15.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.09:56:15.37$vck44/vb=5,4 2006.257.09:56:15.37#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.09:56:15.37#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.09:56:15.37#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:15.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:15.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:15.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:15.43#ibcon#enter wrdev, iclass 36, count 2 2006.257.09:56:15.43#ibcon#first serial, iclass 36, count 2 2006.257.09:56:15.43#ibcon#enter sib2, iclass 36, count 2 2006.257.09:56:15.43#ibcon#flushed, iclass 36, count 2 2006.257.09:56:15.43#ibcon#about to write, iclass 36, count 2 2006.257.09:56:15.43#ibcon#wrote, iclass 36, count 2 2006.257.09:56:15.43#ibcon#about to read 3, iclass 36, count 2 2006.257.09:56:15.45#ibcon#read 3, iclass 36, count 2 2006.257.09:56:15.45#ibcon#about to read 4, iclass 36, count 2 2006.257.09:56:15.45#ibcon#read 4, iclass 36, count 2 2006.257.09:56:15.45#ibcon#about to read 5, iclass 36, count 2 2006.257.09:56:15.45#ibcon#read 5, iclass 36, count 2 2006.257.09:56:15.45#ibcon#about to read 6, iclass 36, count 2 2006.257.09:56:15.45#ibcon#read 6, iclass 36, count 2 2006.257.09:56:15.45#ibcon#end of sib2, iclass 36, count 2 2006.257.09:56:15.45#ibcon#*mode == 0, iclass 36, count 2 2006.257.09:56:15.45#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.09:56:15.45#ibcon#[27=AT05-04\r\n] 2006.257.09:56:15.45#ibcon#*before write, iclass 36, count 2 2006.257.09:56:15.45#ibcon#enter sib2, iclass 36, count 2 2006.257.09:56:15.45#ibcon#flushed, iclass 36, count 2 2006.257.09:56:15.45#ibcon#about to write, iclass 36, count 2 2006.257.09:56:15.45#ibcon#wrote, iclass 36, count 2 2006.257.09:56:15.45#ibcon#about to read 3, iclass 36, count 2 2006.257.09:56:15.48#ibcon#read 3, iclass 36, count 2 2006.257.09:56:15.48#ibcon#about to read 4, iclass 36, count 2 2006.257.09:56:15.48#ibcon#read 4, iclass 36, count 2 2006.257.09:56:15.48#ibcon#about to read 5, iclass 36, count 2 2006.257.09:56:15.48#ibcon#read 5, iclass 36, count 2 2006.257.09:56:15.48#ibcon#about to read 6, iclass 36, count 2 2006.257.09:56:15.48#ibcon#read 6, iclass 36, count 2 2006.257.09:56:15.48#ibcon#end of sib2, iclass 36, count 2 2006.257.09:56:15.48#ibcon#*after write, iclass 36, count 2 2006.257.09:56:15.48#ibcon#*before return 0, iclass 36, count 2 2006.257.09:56:15.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:15.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.09:56:15.48#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.09:56:15.48#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:15.48#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:15.60#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:15.60#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:15.60#ibcon#enter wrdev, iclass 36, count 0 2006.257.09:56:15.60#ibcon#first serial, iclass 36, count 0 2006.257.09:56:15.60#ibcon#enter sib2, iclass 36, count 0 2006.257.09:56:15.60#ibcon#flushed, iclass 36, count 0 2006.257.09:56:15.60#ibcon#about to write, iclass 36, count 0 2006.257.09:56:15.60#ibcon#wrote, iclass 36, count 0 2006.257.09:56:15.60#ibcon#about to read 3, iclass 36, count 0 2006.257.09:56:15.62#ibcon#read 3, iclass 36, count 0 2006.257.09:56:15.62#ibcon#about to read 4, iclass 36, count 0 2006.257.09:56:15.62#ibcon#read 4, iclass 36, count 0 2006.257.09:56:15.62#ibcon#about to read 5, iclass 36, count 0 2006.257.09:56:15.62#ibcon#read 5, iclass 36, count 0 2006.257.09:56:15.62#ibcon#about to read 6, iclass 36, count 0 2006.257.09:56:15.62#ibcon#read 6, iclass 36, count 0 2006.257.09:56:15.62#ibcon#end of sib2, iclass 36, count 0 2006.257.09:56:15.62#ibcon#*mode == 0, iclass 36, count 0 2006.257.09:56:15.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.09:56:15.62#ibcon#[27=USB\r\n] 2006.257.09:56:15.62#ibcon#*before write, iclass 36, count 0 2006.257.09:56:15.62#ibcon#enter sib2, iclass 36, count 0 2006.257.09:56:15.62#ibcon#flushed, iclass 36, count 0 2006.257.09:56:15.62#ibcon#about to write, iclass 36, count 0 2006.257.09:56:15.62#ibcon#wrote, iclass 36, count 0 2006.257.09:56:15.62#ibcon#about to read 3, iclass 36, count 0 2006.257.09:56:15.65#ibcon#read 3, iclass 36, count 0 2006.257.09:56:15.65#ibcon#about to read 4, iclass 36, count 0 2006.257.09:56:15.65#ibcon#read 4, iclass 36, count 0 2006.257.09:56:15.65#ibcon#about to read 5, iclass 36, count 0 2006.257.09:56:15.65#ibcon#read 5, iclass 36, count 0 2006.257.09:56:15.65#ibcon#about to read 6, iclass 36, count 0 2006.257.09:56:15.65#ibcon#read 6, iclass 36, count 0 2006.257.09:56:15.65#ibcon#end of sib2, iclass 36, count 0 2006.257.09:56:15.65#ibcon#*after write, iclass 36, count 0 2006.257.09:56:15.65#ibcon#*before return 0, iclass 36, count 0 2006.257.09:56:15.65#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:15.65#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.09:56:15.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.09:56:15.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.09:56:15.65$vck44/vblo=6,719.99 2006.257.09:56:15.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.09:56:15.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.09:56:15.65#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:15.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:15.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:15.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:15.65#ibcon#enter wrdev, iclass 38, count 0 2006.257.09:56:15.65#ibcon#first serial, iclass 38, count 0 2006.257.09:56:15.65#ibcon#enter sib2, iclass 38, count 0 2006.257.09:56:15.65#ibcon#flushed, iclass 38, count 0 2006.257.09:56:15.65#ibcon#about to write, iclass 38, count 0 2006.257.09:56:15.65#ibcon#wrote, iclass 38, count 0 2006.257.09:56:15.65#ibcon#about to read 3, iclass 38, count 0 2006.257.09:56:15.67#ibcon#read 3, iclass 38, count 0 2006.257.09:56:15.67#ibcon#about to read 4, iclass 38, count 0 2006.257.09:56:15.67#ibcon#read 4, iclass 38, count 0 2006.257.09:56:15.67#ibcon#about to read 5, iclass 38, count 0 2006.257.09:56:15.67#ibcon#read 5, iclass 38, count 0 2006.257.09:56:15.67#ibcon#about to read 6, iclass 38, count 0 2006.257.09:56:15.67#ibcon#read 6, iclass 38, count 0 2006.257.09:56:15.67#ibcon#end of sib2, iclass 38, count 0 2006.257.09:56:15.67#ibcon#*mode == 0, iclass 38, count 0 2006.257.09:56:15.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.09:56:15.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.09:56:15.67#ibcon#*before write, iclass 38, count 0 2006.257.09:56:15.67#ibcon#enter sib2, iclass 38, count 0 2006.257.09:56:15.67#ibcon#flushed, iclass 38, count 0 2006.257.09:56:15.67#ibcon#about to write, iclass 38, count 0 2006.257.09:56:15.67#ibcon#wrote, iclass 38, count 0 2006.257.09:56:15.67#ibcon#about to read 3, iclass 38, count 0 2006.257.09:56:15.71#ibcon#read 3, iclass 38, count 0 2006.257.09:56:15.71#ibcon#about to read 4, iclass 38, count 0 2006.257.09:56:15.71#ibcon#read 4, iclass 38, count 0 2006.257.09:56:15.71#ibcon#about to read 5, iclass 38, count 0 2006.257.09:56:15.71#ibcon#read 5, iclass 38, count 0 2006.257.09:56:15.71#ibcon#about to read 6, iclass 38, count 0 2006.257.09:56:15.71#ibcon#read 6, iclass 38, count 0 2006.257.09:56:15.71#ibcon#end of sib2, iclass 38, count 0 2006.257.09:56:15.71#ibcon#*after write, iclass 38, count 0 2006.257.09:56:15.71#ibcon#*before return 0, iclass 38, count 0 2006.257.09:56:15.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:15.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.09:56:15.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.09:56:15.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.09:56:15.71$vck44/vb=6,4 2006.257.09:56:15.71#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.09:56:15.71#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.09:56:15.71#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:15.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:15.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:15.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:15.77#ibcon#enter wrdev, iclass 40, count 2 2006.257.09:56:15.77#ibcon#first serial, iclass 40, count 2 2006.257.09:56:15.77#ibcon#enter sib2, iclass 40, count 2 2006.257.09:56:15.77#ibcon#flushed, iclass 40, count 2 2006.257.09:56:15.77#ibcon#about to write, iclass 40, count 2 2006.257.09:56:15.77#ibcon#wrote, iclass 40, count 2 2006.257.09:56:15.77#ibcon#about to read 3, iclass 40, count 2 2006.257.09:56:15.79#ibcon#read 3, iclass 40, count 2 2006.257.09:56:15.79#ibcon#about to read 4, iclass 40, count 2 2006.257.09:56:15.79#ibcon#read 4, iclass 40, count 2 2006.257.09:56:15.79#ibcon#about to read 5, iclass 40, count 2 2006.257.09:56:15.79#ibcon#read 5, iclass 40, count 2 2006.257.09:56:15.79#ibcon#about to read 6, iclass 40, count 2 2006.257.09:56:15.79#ibcon#read 6, iclass 40, count 2 2006.257.09:56:15.79#ibcon#end of sib2, iclass 40, count 2 2006.257.09:56:15.79#ibcon#*mode == 0, iclass 40, count 2 2006.257.09:56:15.79#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.09:56:15.79#ibcon#[27=AT06-04\r\n] 2006.257.09:56:15.79#ibcon#*before write, iclass 40, count 2 2006.257.09:56:15.79#ibcon#enter sib2, iclass 40, count 2 2006.257.09:56:15.79#ibcon#flushed, iclass 40, count 2 2006.257.09:56:15.79#ibcon#about to write, iclass 40, count 2 2006.257.09:56:15.79#ibcon#wrote, iclass 40, count 2 2006.257.09:56:15.79#ibcon#about to read 3, iclass 40, count 2 2006.257.09:56:15.82#ibcon#read 3, iclass 40, count 2 2006.257.09:56:15.82#ibcon#about to read 4, iclass 40, count 2 2006.257.09:56:15.82#ibcon#read 4, iclass 40, count 2 2006.257.09:56:15.82#ibcon#about to read 5, iclass 40, count 2 2006.257.09:56:15.82#ibcon#read 5, iclass 40, count 2 2006.257.09:56:15.82#ibcon#about to read 6, iclass 40, count 2 2006.257.09:56:15.82#ibcon#read 6, iclass 40, count 2 2006.257.09:56:15.82#ibcon#end of sib2, iclass 40, count 2 2006.257.09:56:15.82#ibcon#*after write, iclass 40, count 2 2006.257.09:56:15.82#ibcon#*before return 0, iclass 40, count 2 2006.257.09:56:15.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:15.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.09:56:15.82#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.09:56:15.82#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:15.82#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:15.94#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:15.94#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:15.94#ibcon#enter wrdev, iclass 40, count 0 2006.257.09:56:15.94#ibcon#first serial, iclass 40, count 0 2006.257.09:56:15.94#ibcon#enter sib2, iclass 40, count 0 2006.257.09:56:15.94#ibcon#flushed, iclass 40, count 0 2006.257.09:56:15.94#ibcon#about to write, iclass 40, count 0 2006.257.09:56:15.94#ibcon#wrote, iclass 40, count 0 2006.257.09:56:15.94#ibcon#about to read 3, iclass 40, count 0 2006.257.09:56:15.96#ibcon#read 3, iclass 40, count 0 2006.257.09:56:15.96#ibcon#about to read 4, iclass 40, count 0 2006.257.09:56:15.96#ibcon#read 4, iclass 40, count 0 2006.257.09:56:15.96#ibcon#about to read 5, iclass 40, count 0 2006.257.09:56:15.96#ibcon#read 5, iclass 40, count 0 2006.257.09:56:15.96#ibcon#about to read 6, iclass 40, count 0 2006.257.09:56:15.96#ibcon#read 6, iclass 40, count 0 2006.257.09:56:15.96#ibcon#end of sib2, iclass 40, count 0 2006.257.09:56:15.96#ibcon#*mode == 0, iclass 40, count 0 2006.257.09:56:15.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.09:56:15.96#ibcon#[27=USB\r\n] 2006.257.09:56:15.96#ibcon#*before write, iclass 40, count 0 2006.257.09:56:15.96#ibcon#enter sib2, iclass 40, count 0 2006.257.09:56:15.96#ibcon#flushed, iclass 40, count 0 2006.257.09:56:15.96#ibcon#about to write, iclass 40, count 0 2006.257.09:56:15.96#ibcon#wrote, iclass 40, count 0 2006.257.09:56:15.96#ibcon#about to read 3, iclass 40, count 0 2006.257.09:56:15.99#ibcon#read 3, iclass 40, count 0 2006.257.09:56:15.99#ibcon#about to read 4, iclass 40, count 0 2006.257.09:56:15.99#ibcon#read 4, iclass 40, count 0 2006.257.09:56:15.99#ibcon#about to read 5, iclass 40, count 0 2006.257.09:56:15.99#ibcon#read 5, iclass 40, count 0 2006.257.09:56:15.99#ibcon#about to read 6, iclass 40, count 0 2006.257.09:56:15.99#ibcon#read 6, iclass 40, count 0 2006.257.09:56:15.99#ibcon#end of sib2, iclass 40, count 0 2006.257.09:56:15.99#ibcon#*after write, iclass 40, count 0 2006.257.09:56:15.99#ibcon#*before return 0, iclass 40, count 0 2006.257.09:56:15.99#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:15.99#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.09:56:15.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.09:56:15.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.09:56:15.99$vck44/vblo=7,734.99 2006.257.09:56:15.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.09:56:15.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.09:56:15.99#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:15.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:15.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:15.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:15.99#ibcon#enter wrdev, iclass 4, count 0 2006.257.09:56:15.99#ibcon#first serial, iclass 4, count 0 2006.257.09:56:15.99#ibcon#enter sib2, iclass 4, count 0 2006.257.09:56:15.99#ibcon#flushed, iclass 4, count 0 2006.257.09:56:15.99#ibcon#about to write, iclass 4, count 0 2006.257.09:56:15.99#ibcon#wrote, iclass 4, count 0 2006.257.09:56:15.99#ibcon#about to read 3, iclass 4, count 0 2006.257.09:56:16.01#ibcon#read 3, iclass 4, count 0 2006.257.09:56:16.01#ibcon#about to read 4, iclass 4, count 0 2006.257.09:56:16.01#ibcon#read 4, iclass 4, count 0 2006.257.09:56:16.01#ibcon#about to read 5, iclass 4, count 0 2006.257.09:56:16.01#ibcon#read 5, iclass 4, count 0 2006.257.09:56:16.01#ibcon#about to read 6, iclass 4, count 0 2006.257.09:56:16.01#ibcon#read 6, iclass 4, count 0 2006.257.09:56:16.01#ibcon#end of sib2, iclass 4, count 0 2006.257.09:56:16.01#ibcon#*mode == 0, iclass 4, count 0 2006.257.09:56:16.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.09:56:16.01#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.09:56:16.01#ibcon#*before write, iclass 4, count 0 2006.257.09:56:16.01#ibcon#enter sib2, iclass 4, count 0 2006.257.09:56:16.01#ibcon#flushed, iclass 4, count 0 2006.257.09:56:16.01#ibcon#about to write, iclass 4, count 0 2006.257.09:56:16.01#ibcon#wrote, iclass 4, count 0 2006.257.09:56:16.01#ibcon#about to read 3, iclass 4, count 0 2006.257.09:56:16.05#ibcon#read 3, iclass 4, count 0 2006.257.09:56:16.05#ibcon#about to read 4, iclass 4, count 0 2006.257.09:56:16.05#ibcon#read 4, iclass 4, count 0 2006.257.09:56:16.05#ibcon#about to read 5, iclass 4, count 0 2006.257.09:56:16.05#ibcon#read 5, iclass 4, count 0 2006.257.09:56:16.05#ibcon#about to read 6, iclass 4, count 0 2006.257.09:56:16.05#ibcon#read 6, iclass 4, count 0 2006.257.09:56:16.05#ibcon#end of sib2, iclass 4, count 0 2006.257.09:56:16.05#ibcon#*after write, iclass 4, count 0 2006.257.09:56:16.05#ibcon#*before return 0, iclass 4, count 0 2006.257.09:56:16.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:16.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.09:56:16.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.09:56:16.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.09:56:16.05$vck44/vb=7,4 2006.257.09:56:16.05#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.09:56:16.05#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.09:56:16.05#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:16.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:16.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:16.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:16.11#ibcon#enter wrdev, iclass 6, count 2 2006.257.09:56:16.11#ibcon#first serial, iclass 6, count 2 2006.257.09:56:16.11#ibcon#enter sib2, iclass 6, count 2 2006.257.09:56:16.11#ibcon#flushed, iclass 6, count 2 2006.257.09:56:16.11#ibcon#about to write, iclass 6, count 2 2006.257.09:56:16.11#ibcon#wrote, iclass 6, count 2 2006.257.09:56:16.11#ibcon#about to read 3, iclass 6, count 2 2006.257.09:56:16.13#ibcon#read 3, iclass 6, count 2 2006.257.09:56:16.13#ibcon#about to read 4, iclass 6, count 2 2006.257.09:56:16.13#ibcon#read 4, iclass 6, count 2 2006.257.09:56:16.13#ibcon#about to read 5, iclass 6, count 2 2006.257.09:56:16.13#ibcon#read 5, iclass 6, count 2 2006.257.09:56:16.13#ibcon#about to read 6, iclass 6, count 2 2006.257.09:56:16.13#ibcon#read 6, iclass 6, count 2 2006.257.09:56:16.13#ibcon#end of sib2, iclass 6, count 2 2006.257.09:56:16.13#ibcon#*mode == 0, iclass 6, count 2 2006.257.09:56:16.13#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.09:56:16.13#ibcon#[27=AT07-04\r\n] 2006.257.09:56:16.13#ibcon#*before write, iclass 6, count 2 2006.257.09:56:16.13#ibcon#enter sib2, iclass 6, count 2 2006.257.09:56:16.13#ibcon#flushed, iclass 6, count 2 2006.257.09:56:16.13#ibcon#about to write, iclass 6, count 2 2006.257.09:56:16.13#ibcon#wrote, iclass 6, count 2 2006.257.09:56:16.13#ibcon#about to read 3, iclass 6, count 2 2006.257.09:56:16.16#ibcon#read 3, iclass 6, count 2 2006.257.09:56:16.16#ibcon#about to read 4, iclass 6, count 2 2006.257.09:56:16.16#ibcon#read 4, iclass 6, count 2 2006.257.09:56:16.16#ibcon#about to read 5, iclass 6, count 2 2006.257.09:56:16.16#ibcon#read 5, iclass 6, count 2 2006.257.09:56:16.16#ibcon#about to read 6, iclass 6, count 2 2006.257.09:56:16.16#ibcon#read 6, iclass 6, count 2 2006.257.09:56:16.16#ibcon#end of sib2, iclass 6, count 2 2006.257.09:56:16.16#ibcon#*after write, iclass 6, count 2 2006.257.09:56:16.16#ibcon#*before return 0, iclass 6, count 2 2006.257.09:56:16.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:16.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.09:56:16.16#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.09:56:16.16#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:16.16#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:16.28#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:16.28#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:16.28#ibcon#enter wrdev, iclass 6, count 0 2006.257.09:56:16.28#ibcon#first serial, iclass 6, count 0 2006.257.09:56:16.28#ibcon#enter sib2, iclass 6, count 0 2006.257.09:56:16.28#ibcon#flushed, iclass 6, count 0 2006.257.09:56:16.28#ibcon#about to write, iclass 6, count 0 2006.257.09:56:16.28#ibcon#wrote, iclass 6, count 0 2006.257.09:56:16.28#ibcon#about to read 3, iclass 6, count 0 2006.257.09:56:16.30#ibcon#read 3, iclass 6, count 0 2006.257.09:56:16.30#ibcon#about to read 4, iclass 6, count 0 2006.257.09:56:16.30#ibcon#read 4, iclass 6, count 0 2006.257.09:56:16.30#ibcon#about to read 5, iclass 6, count 0 2006.257.09:56:16.30#ibcon#read 5, iclass 6, count 0 2006.257.09:56:16.30#ibcon#about to read 6, iclass 6, count 0 2006.257.09:56:16.30#ibcon#read 6, iclass 6, count 0 2006.257.09:56:16.30#ibcon#end of sib2, iclass 6, count 0 2006.257.09:56:16.30#ibcon#*mode == 0, iclass 6, count 0 2006.257.09:56:16.30#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.09:56:16.30#ibcon#[27=USB\r\n] 2006.257.09:56:16.30#ibcon#*before write, iclass 6, count 0 2006.257.09:56:16.30#ibcon#enter sib2, iclass 6, count 0 2006.257.09:56:16.30#ibcon#flushed, iclass 6, count 0 2006.257.09:56:16.30#ibcon#about to write, iclass 6, count 0 2006.257.09:56:16.30#ibcon#wrote, iclass 6, count 0 2006.257.09:56:16.30#ibcon#about to read 3, iclass 6, count 0 2006.257.09:56:16.33#ibcon#read 3, iclass 6, count 0 2006.257.09:56:16.33#ibcon#about to read 4, iclass 6, count 0 2006.257.09:56:16.33#ibcon#read 4, iclass 6, count 0 2006.257.09:56:16.33#ibcon#about to read 5, iclass 6, count 0 2006.257.09:56:16.33#ibcon#read 5, iclass 6, count 0 2006.257.09:56:16.33#ibcon#about to read 6, iclass 6, count 0 2006.257.09:56:16.33#ibcon#read 6, iclass 6, count 0 2006.257.09:56:16.33#ibcon#end of sib2, iclass 6, count 0 2006.257.09:56:16.33#ibcon#*after write, iclass 6, count 0 2006.257.09:56:16.33#ibcon#*before return 0, iclass 6, count 0 2006.257.09:56:16.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:16.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.09:56:16.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.09:56:16.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.09:56:16.33$vck44/vblo=8,744.99 2006.257.09:56:16.33#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.09:56:16.33#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.09:56:16.33#ibcon#ireg 17 cls_cnt 0 2006.257.09:56:16.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:16.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:16.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:16.33#ibcon#enter wrdev, iclass 10, count 0 2006.257.09:56:16.33#ibcon#first serial, iclass 10, count 0 2006.257.09:56:16.33#ibcon#enter sib2, iclass 10, count 0 2006.257.09:56:16.33#ibcon#flushed, iclass 10, count 0 2006.257.09:56:16.33#ibcon#about to write, iclass 10, count 0 2006.257.09:56:16.33#ibcon#wrote, iclass 10, count 0 2006.257.09:56:16.33#ibcon#about to read 3, iclass 10, count 0 2006.257.09:56:16.35#ibcon#read 3, iclass 10, count 0 2006.257.09:56:16.35#ibcon#about to read 4, iclass 10, count 0 2006.257.09:56:16.35#ibcon#read 4, iclass 10, count 0 2006.257.09:56:16.35#ibcon#about to read 5, iclass 10, count 0 2006.257.09:56:16.35#ibcon#read 5, iclass 10, count 0 2006.257.09:56:16.35#ibcon#about to read 6, iclass 10, count 0 2006.257.09:56:16.35#ibcon#read 6, iclass 10, count 0 2006.257.09:56:16.35#ibcon#end of sib2, iclass 10, count 0 2006.257.09:56:16.35#ibcon#*mode == 0, iclass 10, count 0 2006.257.09:56:16.35#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.09:56:16.35#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.09:56:16.35#ibcon#*before write, iclass 10, count 0 2006.257.09:56:16.35#ibcon#enter sib2, iclass 10, count 0 2006.257.09:56:16.35#ibcon#flushed, iclass 10, count 0 2006.257.09:56:16.35#ibcon#about to write, iclass 10, count 0 2006.257.09:56:16.35#ibcon#wrote, iclass 10, count 0 2006.257.09:56:16.35#ibcon#about to read 3, iclass 10, count 0 2006.257.09:56:16.39#ibcon#read 3, iclass 10, count 0 2006.257.09:56:16.39#ibcon#about to read 4, iclass 10, count 0 2006.257.09:56:16.39#ibcon#read 4, iclass 10, count 0 2006.257.09:56:16.39#ibcon#about to read 5, iclass 10, count 0 2006.257.09:56:16.39#ibcon#read 5, iclass 10, count 0 2006.257.09:56:16.39#ibcon#about to read 6, iclass 10, count 0 2006.257.09:56:16.39#ibcon#read 6, iclass 10, count 0 2006.257.09:56:16.39#ibcon#end of sib2, iclass 10, count 0 2006.257.09:56:16.39#ibcon#*after write, iclass 10, count 0 2006.257.09:56:16.39#ibcon#*before return 0, iclass 10, count 0 2006.257.09:56:16.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:16.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.09:56:16.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.09:56:16.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.09:56:16.39$vck44/vb=8,4 2006.257.09:56:16.39#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.09:56:16.39#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.09:56:16.39#ibcon#ireg 11 cls_cnt 2 2006.257.09:56:16.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:16.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:16.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:16.45#ibcon#enter wrdev, iclass 12, count 2 2006.257.09:56:16.45#ibcon#first serial, iclass 12, count 2 2006.257.09:56:16.45#ibcon#enter sib2, iclass 12, count 2 2006.257.09:56:16.45#ibcon#flushed, iclass 12, count 2 2006.257.09:56:16.45#ibcon#about to write, iclass 12, count 2 2006.257.09:56:16.45#ibcon#wrote, iclass 12, count 2 2006.257.09:56:16.45#ibcon#about to read 3, iclass 12, count 2 2006.257.09:56:16.47#ibcon#read 3, iclass 12, count 2 2006.257.09:56:16.47#ibcon#about to read 4, iclass 12, count 2 2006.257.09:56:16.47#ibcon#read 4, iclass 12, count 2 2006.257.09:56:16.47#ibcon#about to read 5, iclass 12, count 2 2006.257.09:56:16.47#ibcon#read 5, iclass 12, count 2 2006.257.09:56:16.47#ibcon#about to read 6, iclass 12, count 2 2006.257.09:56:16.47#ibcon#read 6, iclass 12, count 2 2006.257.09:56:16.47#ibcon#end of sib2, iclass 12, count 2 2006.257.09:56:16.47#ibcon#*mode == 0, iclass 12, count 2 2006.257.09:56:16.47#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.09:56:16.47#ibcon#[27=AT08-04\r\n] 2006.257.09:56:16.47#ibcon#*before write, iclass 12, count 2 2006.257.09:56:16.47#ibcon#enter sib2, iclass 12, count 2 2006.257.09:56:16.47#ibcon#flushed, iclass 12, count 2 2006.257.09:56:16.47#ibcon#about to write, iclass 12, count 2 2006.257.09:56:16.47#ibcon#wrote, iclass 12, count 2 2006.257.09:56:16.47#ibcon#about to read 3, iclass 12, count 2 2006.257.09:56:16.50#ibcon#read 3, iclass 12, count 2 2006.257.09:56:16.50#ibcon#about to read 4, iclass 12, count 2 2006.257.09:56:16.50#ibcon#read 4, iclass 12, count 2 2006.257.09:56:16.50#ibcon#about to read 5, iclass 12, count 2 2006.257.09:56:16.50#ibcon#read 5, iclass 12, count 2 2006.257.09:56:16.50#ibcon#about to read 6, iclass 12, count 2 2006.257.09:56:16.50#ibcon#read 6, iclass 12, count 2 2006.257.09:56:16.50#ibcon#end of sib2, iclass 12, count 2 2006.257.09:56:16.50#ibcon#*after write, iclass 12, count 2 2006.257.09:56:16.50#ibcon#*before return 0, iclass 12, count 2 2006.257.09:56:16.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:16.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.09:56:16.50#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.09:56:16.50#ibcon#ireg 7 cls_cnt 0 2006.257.09:56:16.50#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:16.62#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:16.62#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:16.62#ibcon#enter wrdev, iclass 12, count 0 2006.257.09:56:16.62#ibcon#first serial, iclass 12, count 0 2006.257.09:56:16.62#ibcon#enter sib2, iclass 12, count 0 2006.257.09:56:16.62#ibcon#flushed, iclass 12, count 0 2006.257.09:56:16.62#ibcon#about to write, iclass 12, count 0 2006.257.09:56:16.62#ibcon#wrote, iclass 12, count 0 2006.257.09:56:16.62#ibcon#about to read 3, iclass 12, count 0 2006.257.09:56:16.64#ibcon#read 3, iclass 12, count 0 2006.257.09:56:16.64#ibcon#about to read 4, iclass 12, count 0 2006.257.09:56:16.64#ibcon#read 4, iclass 12, count 0 2006.257.09:56:16.64#ibcon#about to read 5, iclass 12, count 0 2006.257.09:56:16.64#ibcon#read 5, iclass 12, count 0 2006.257.09:56:16.64#ibcon#about to read 6, iclass 12, count 0 2006.257.09:56:16.64#ibcon#read 6, iclass 12, count 0 2006.257.09:56:16.64#ibcon#end of sib2, iclass 12, count 0 2006.257.09:56:16.64#ibcon#*mode == 0, iclass 12, count 0 2006.257.09:56:16.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.09:56:16.64#ibcon#[27=USB\r\n] 2006.257.09:56:16.64#ibcon#*before write, iclass 12, count 0 2006.257.09:56:16.64#ibcon#enter sib2, iclass 12, count 0 2006.257.09:56:16.64#ibcon#flushed, iclass 12, count 0 2006.257.09:56:16.64#ibcon#about to write, iclass 12, count 0 2006.257.09:56:16.64#ibcon#wrote, iclass 12, count 0 2006.257.09:56:16.64#ibcon#about to read 3, iclass 12, count 0 2006.257.09:56:16.67#ibcon#read 3, iclass 12, count 0 2006.257.09:56:16.67#ibcon#about to read 4, iclass 12, count 0 2006.257.09:56:16.67#ibcon#read 4, iclass 12, count 0 2006.257.09:56:16.67#ibcon#about to read 5, iclass 12, count 0 2006.257.09:56:16.67#ibcon#read 5, iclass 12, count 0 2006.257.09:56:16.67#ibcon#about to read 6, iclass 12, count 0 2006.257.09:56:16.67#ibcon#read 6, iclass 12, count 0 2006.257.09:56:16.67#ibcon#end of sib2, iclass 12, count 0 2006.257.09:56:16.67#ibcon#*after write, iclass 12, count 0 2006.257.09:56:16.67#ibcon#*before return 0, iclass 12, count 0 2006.257.09:56:16.67#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:16.67#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.09:56:16.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.09:56:16.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.09:56:16.67$vck44/vabw=wide 2006.257.09:56:16.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.09:56:16.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.09:56:16.67#ibcon#ireg 8 cls_cnt 0 2006.257.09:56:16.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:56:16.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:56:16.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:56:16.67#ibcon#enter wrdev, iclass 15, count 0 2006.257.09:56:16.67#ibcon#first serial, iclass 15, count 0 2006.257.09:56:16.67#ibcon#enter sib2, iclass 15, count 0 2006.257.09:56:16.67#ibcon#flushed, iclass 15, count 0 2006.257.09:56:16.67#ibcon#about to write, iclass 15, count 0 2006.257.09:56:16.67#ibcon#wrote, iclass 15, count 0 2006.257.09:56:16.67#ibcon#about to read 3, iclass 15, count 0 2006.257.09:56:16.69#ibcon#read 3, iclass 15, count 0 2006.257.09:56:16.69#ibcon#about to read 4, iclass 15, count 0 2006.257.09:56:16.69#ibcon#read 4, iclass 15, count 0 2006.257.09:56:16.69#ibcon#about to read 5, iclass 15, count 0 2006.257.09:56:16.69#ibcon#read 5, iclass 15, count 0 2006.257.09:56:16.69#ibcon#about to read 6, iclass 15, count 0 2006.257.09:56:16.69#ibcon#read 6, iclass 15, count 0 2006.257.09:56:16.69#ibcon#end of sib2, iclass 15, count 0 2006.257.09:56:16.69#ibcon#*mode == 0, iclass 15, count 0 2006.257.09:56:16.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.09:56:16.69#ibcon#[25=BW32\r\n] 2006.257.09:56:16.69#ibcon#*before write, iclass 15, count 0 2006.257.09:56:16.69#ibcon#enter sib2, iclass 15, count 0 2006.257.09:56:16.69#ibcon#flushed, iclass 15, count 0 2006.257.09:56:16.69#ibcon#about to write, iclass 15, count 0 2006.257.09:56:16.69#ibcon#wrote, iclass 15, count 0 2006.257.09:56:16.69#ibcon#about to read 3, iclass 15, count 0 2006.257.09:56:16.69#abcon#<5=/15 0.6 1.5 19.27 961013.3\r\n> 2006.257.09:56:16.71#abcon#{5=INTERFACE CLEAR} 2006.257.09:56:16.72#ibcon#read 3, iclass 15, count 0 2006.257.09:56:16.72#ibcon#about to read 4, iclass 15, count 0 2006.257.09:56:16.72#ibcon#read 4, iclass 15, count 0 2006.257.09:56:16.72#ibcon#about to read 5, iclass 15, count 0 2006.257.09:56:16.72#ibcon#read 5, iclass 15, count 0 2006.257.09:56:16.72#ibcon#about to read 6, iclass 15, count 0 2006.257.09:56:16.72#ibcon#read 6, iclass 15, count 0 2006.257.09:56:16.72#ibcon#end of sib2, iclass 15, count 0 2006.257.09:56:16.72#ibcon#*after write, iclass 15, count 0 2006.257.09:56:16.72#ibcon#*before return 0, iclass 15, count 0 2006.257.09:56:16.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:56:16.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.09:56:16.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.09:56:16.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.09:56:16.72$vck44/vbbw=wide 2006.257.09:56:16.72#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.09:56:16.72#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.09:56:16.72#ibcon#ireg 8 cls_cnt 0 2006.257.09:56:16.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:56:16.77#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:56:16.79#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:56:16.79#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:56:16.79#ibcon#enter wrdev, iclass 19, count 0 2006.257.09:56:16.79#ibcon#first serial, iclass 19, count 0 2006.257.09:56:16.79#ibcon#enter sib2, iclass 19, count 0 2006.257.09:56:16.79#ibcon#flushed, iclass 19, count 0 2006.257.09:56:16.79#ibcon#about to write, iclass 19, count 0 2006.257.09:56:16.79#ibcon#wrote, iclass 19, count 0 2006.257.09:56:16.79#ibcon#about to read 3, iclass 19, count 0 2006.257.09:56:16.81#ibcon#read 3, iclass 19, count 0 2006.257.09:56:16.81#ibcon#about to read 4, iclass 19, count 0 2006.257.09:56:16.81#ibcon#read 4, iclass 19, count 0 2006.257.09:56:16.81#ibcon#about to read 5, iclass 19, count 0 2006.257.09:56:16.81#ibcon#read 5, iclass 19, count 0 2006.257.09:56:16.81#ibcon#about to read 6, iclass 19, count 0 2006.257.09:56:16.81#ibcon#read 6, iclass 19, count 0 2006.257.09:56:16.81#ibcon#end of sib2, iclass 19, count 0 2006.257.09:56:16.81#ibcon#*mode == 0, iclass 19, count 0 2006.257.09:56:16.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.09:56:16.81#ibcon#[27=BW32\r\n] 2006.257.09:56:16.81#ibcon#*before write, iclass 19, count 0 2006.257.09:56:16.81#ibcon#enter sib2, iclass 19, count 0 2006.257.09:56:16.81#ibcon#flushed, iclass 19, count 0 2006.257.09:56:16.81#ibcon#about to write, iclass 19, count 0 2006.257.09:56:16.81#ibcon#wrote, iclass 19, count 0 2006.257.09:56:16.81#ibcon#about to read 3, iclass 19, count 0 2006.257.09:56:16.84#ibcon#read 3, iclass 19, count 0 2006.257.09:56:16.84#ibcon#about to read 4, iclass 19, count 0 2006.257.09:56:16.84#ibcon#read 4, iclass 19, count 0 2006.257.09:56:16.84#ibcon#about to read 5, iclass 19, count 0 2006.257.09:56:16.84#ibcon#read 5, iclass 19, count 0 2006.257.09:56:16.84#ibcon#about to read 6, iclass 19, count 0 2006.257.09:56:16.84#ibcon#read 6, iclass 19, count 0 2006.257.09:56:16.84#ibcon#end of sib2, iclass 19, count 0 2006.257.09:56:16.84#ibcon#*after write, iclass 19, count 0 2006.257.09:56:16.84#ibcon#*before return 0, iclass 19, count 0 2006.257.09:56:16.84#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:56:16.84#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.09:56:16.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.09:56:16.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.09:56:16.84$setupk4/ifdk4 2006.257.09:56:16.84$ifdk4/lo= 2006.257.09:56:16.84$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.09:56:16.84$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.09:56:16.84$ifdk4/patch= 2006.257.09:56:16.84$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.09:56:16.84$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.09:56:16.84$setupk4/!*+20s 2006.257.09:56:26.86#abcon#<5=/15 0.6 1.4 19.27 961013.3\r\n> 2006.257.09:56:26.88#abcon#{5=INTERFACE CLEAR} 2006.257.09:56:26.94#abcon#[5=S1D000X0/0*\r\n] 2006.257.09:56:31.34$setupk4/"tpicd 2006.257.09:56:31.34$setupk4/echo=off 2006.257.09:56:31.34$setupk4/xlog=off 2006.257.09:56:31.34:!2006.257.09:58:34 2006.257.09:56:40.14#trakl#Source acquired 2006.257.09:56:40.14#flagr#flagr/antenna,acquired 2006.257.09:58:34.00:preob 2006.257.09:58:35.13/onsource/TRACKING 2006.257.09:58:35.13:!2006.257.09:58:44 2006.257.09:58:44.00:"tape 2006.257.09:58:44.00:"st=record 2006.257.09:58:44.00:data_valid=on 2006.257.09:58:44.00:midob 2006.257.09:58:44.13/onsource/TRACKING 2006.257.09:58:44.13/wx/19.25,1013.3,96 2006.257.09:58:44.19/cable/+6.4751E-03 2006.257.09:58:45.28/va/01,08,usb,yes,31,33 2006.257.09:58:45.28/va/02,07,usb,yes,34,34 2006.257.09:58:45.28/va/03,08,usb,yes,30,32 2006.257.09:58:45.28/va/04,07,usb,yes,35,36 2006.257.09:58:45.28/va/05,04,usb,yes,31,31 2006.257.09:58:45.28/va/06,04,usb,yes,35,34 2006.257.09:58:45.28/va/07,04,usb,yes,36,36 2006.257.09:58:45.28/va/08,04,usb,yes,29,36 2006.257.09:58:45.51/valo/01,524.99,yes,locked 2006.257.09:58:45.51/valo/02,534.99,yes,locked 2006.257.09:58:45.51/valo/03,564.99,yes,locked 2006.257.09:58:45.51/valo/04,624.99,yes,locked 2006.257.09:58:45.51/valo/05,734.99,yes,locked 2006.257.09:58:45.51/valo/06,814.99,yes,locked 2006.257.09:58:45.51/valo/07,864.99,yes,locked 2006.257.09:58:45.51/valo/08,884.99,yes,locked 2006.257.09:58:46.60/vb/01,04,usb,yes,31,29 2006.257.09:58:46.60/vb/02,05,usb,yes,29,29 2006.257.09:58:46.60/vb/03,04,usb,yes,30,33 2006.257.09:58:46.60/vb/04,05,usb,yes,31,30 2006.257.09:58:46.60/vb/05,04,usb,yes,27,30 2006.257.09:58:46.60/vb/06,04,usb,yes,32,28 2006.257.09:58:46.60/vb/07,04,usb,yes,31,31 2006.257.09:58:46.60/vb/08,04,usb,yes,29,32 2006.257.09:58:46.83/vblo/01,629.99,yes,locked 2006.257.09:58:46.83/vblo/02,634.99,yes,locked 2006.257.09:58:46.83/vblo/03,649.99,yes,locked 2006.257.09:58:46.83/vblo/04,679.99,yes,locked 2006.257.09:58:46.83/vblo/05,709.99,yes,locked 2006.257.09:58:46.83/vblo/06,719.99,yes,locked 2006.257.09:58:46.83/vblo/07,734.99,yes,locked 2006.257.09:58:46.83/vblo/08,744.99,yes,locked 2006.257.09:58:46.98/vabw/8 2006.257.09:58:47.13/vbbw/8 2006.257.09:58:47.22/xfe/off,on,15.0 2006.257.09:58:47.59/ifatt/23,28,28,28 2006.257.09:58:48.08/fmout-gps/S +4.64E-07 2006.257.09:58:48.12:!2006.257.10:00:44 2006.257.10:00:44.01:data_valid=off 2006.257.10:00:44.01:"et 2006.257.10:00:44.02:!+3s 2006.257.10:00:47.03:"tape 2006.257.10:00:47.03:postob 2006.257.10:00:47.20/cable/+6.4757E-03 2006.257.10:00:47.20/wx/19.23,1013.4,96 2006.257.10:00:47.26/fmout-gps/S +4.63E-07 2006.257.10:00:47.26:scan_name=257-1005,jd0609,50 2006.257.10:00:47.27:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.10:00:48.14#flagr#flagr/antenna,new-source 2006.257.10:00:48.14:checkk5 2006.257.10:00:48.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:00:48.85/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:00:49.19/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:00:49.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:00:50.00/chk_obsdata//k5ts1/T2570958??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.257.10:00:50.41/chk_obsdata//k5ts2/T2570958??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.257.10:00:50.81/chk_obsdata//k5ts3/T2570958??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.257.10:00:51.20/chk_obsdata//k5ts4/T2570958??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.257.10:00:51.92/k5log//k5ts1_log_newline 2006.257.10:00:52.64/k5log//k5ts2_log_newline 2006.257.10:00:53.35/k5log//k5ts3_log_newline 2006.257.10:00:54.06/k5log//k5ts4_log_newline 2006.257.10:00:54.08/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:00:54.08:setupk4=1 2006.257.10:00:54.08$setupk4/echo=on 2006.257.10:00:54.08$setupk4/pcalon 2006.257.10:00:54.08$pcalon/"no phase cal control is implemented here 2006.257.10:00:54.08$setupk4/"tpicd=stop 2006.257.10:00:54.08$setupk4/"rec=synch_on 2006.257.10:00:54.08$setupk4/"rec_mode=128 2006.257.10:00:54.08$setupk4/!* 2006.257.10:00:54.08$setupk4/recpk4 2006.257.10:00:54.08$recpk4/recpatch= 2006.257.10:00:54.09$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:00:54.09$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:00:54.09$setupk4/vck44 2006.257.10:00:54.09$vck44/valo=1,524.99 2006.257.10:00:54.09#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.10:00:54.09#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.10:00:54.09#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:54.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:54.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:54.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:54.09#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:00:54.09#ibcon#first serial, iclass 25, count 0 2006.257.10:00:54.09#ibcon#enter sib2, iclass 25, count 0 2006.257.10:00:54.09#ibcon#flushed, iclass 25, count 0 2006.257.10:00:54.09#ibcon#about to write, iclass 25, count 0 2006.257.10:00:54.09#ibcon#wrote, iclass 25, count 0 2006.257.10:00:54.09#ibcon#about to read 3, iclass 25, count 0 2006.257.10:00:54.10#ibcon#read 3, iclass 25, count 0 2006.257.10:00:54.10#ibcon#about to read 4, iclass 25, count 0 2006.257.10:00:54.10#ibcon#read 4, iclass 25, count 0 2006.257.10:00:54.10#ibcon#about to read 5, iclass 25, count 0 2006.257.10:00:54.10#ibcon#read 5, iclass 25, count 0 2006.257.10:00:54.10#ibcon#about to read 6, iclass 25, count 0 2006.257.10:00:54.10#ibcon#read 6, iclass 25, count 0 2006.257.10:00:54.10#ibcon#end of sib2, iclass 25, count 0 2006.257.10:00:54.10#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:00:54.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:00:54.10#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:00:54.10#ibcon#*before write, iclass 25, count 0 2006.257.10:00:54.10#ibcon#enter sib2, iclass 25, count 0 2006.257.10:00:54.10#ibcon#flushed, iclass 25, count 0 2006.257.10:00:54.10#ibcon#about to write, iclass 25, count 0 2006.257.10:00:54.10#ibcon#wrote, iclass 25, count 0 2006.257.10:00:54.10#ibcon#about to read 3, iclass 25, count 0 2006.257.10:00:54.15#ibcon#read 3, iclass 25, count 0 2006.257.10:00:54.15#ibcon#about to read 4, iclass 25, count 0 2006.257.10:00:54.15#ibcon#read 4, iclass 25, count 0 2006.257.10:00:54.15#ibcon#about to read 5, iclass 25, count 0 2006.257.10:00:54.15#ibcon#read 5, iclass 25, count 0 2006.257.10:00:54.15#ibcon#about to read 6, iclass 25, count 0 2006.257.10:00:54.15#ibcon#read 6, iclass 25, count 0 2006.257.10:00:54.15#ibcon#end of sib2, iclass 25, count 0 2006.257.10:00:54.15#ibcon#*after write, iclass 25, count 0 2006.257.10:00:54.15#ibcon#*before return 0, iclass 25, count 0 2006.257.10:00:54.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:54.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:54.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:00:54.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:00:54.15$vck44/va=1,8 2006.257.10:00:54.15#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.10:00:54.15#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.10:00:54.15#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:54.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:54.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:54.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:54.15#ibcon#enter wrdev, iclass 27, count 2 2006.257.10:00:54.15#ibcon#first serial, iclass 27, count 2 2006.257.10:00:54.15#ibcon#enter sib2, iclass 27, count 2 2006.257.10:00:54.15#ibcon#flushed, iclass 27, count 2 2006.257.10:00:54.15#ibcon#about to write, iclass 27, count 2 2006.257.10:00:54.15#ibcon#wrote, iclass 27, count 2 2006.257.10:00:54.15#ibcon#about to read 3, iclass 27, count 2 2006.257.10:00:54.17#ibcon#read 3, iclass 27, count 2 2006.257.10:00:54.17#ibcon#about to read 4, iclass 27, count 2 2006.257.10:00:54.17#ibcon#read 4, iclass 27, count 2 2006.257.10:00:54.17#ibcon#about to read 5, iclass 27, count 2 2006.257.10:00:54.17#ibcon#read 5, iclass 27, count 2 2006.257.10:00:54.17#ibcon#about to read 6, iclass 27, count 2 2006.257.10:00:54.17#ibcon#read 6, iclass 27, count 2 2006.257.10:00:54.17#ibcon#end of sib2, iclass 27, count 2 2006.257.10:00:54.17#ibcon#*mode == 0, iclass 27, count 2 2006.257.10:00:54.17#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.10:00:54.17#ibcon#[25=AT01-08\r\n] 2006.257.10:00:54.17#ibcon#*before write, iclass 27, count 2 2006.257.10:00:54.17#ibcon#enter sib2, iclass 27, count 2 2006.257.10:00:54.17#ibcon#flushed, iclass 27, count 2 2006.257.10:00:54.17#ibcon#about to write, iclass 27, count 2 2006.257.10:00:54.17#ibcon#wrote, iclass 27, count 2 2006.257.10:00:54.17#ibcon#about to read 3, iclass 27, count 2 2006.257.10:00:54.20#ibcon#read 3, iclass 27, count 2 2006.257.10:00:54.20#ibcon#about to read 4, iclass 27, count 2 2006.257.10:00:54.20#ibcon#read 4, iclass 27, count 2 2006.257.10:00:54.20#ibcon#about to read 5, iclass 27, count 2 2006.257.10:00:54.20#ibcon#read 5, iclass 27, count 2 2006.257.10:00:54.20#ibcon#about to read 6, iclass 27, count 2 2006.257.10:00:54.20#ibcon#read 6, iclass 27, count 2 2006.257.10:00:54.20#ibcon#end of sib2, iclass 27, count 2 2006.257.10:00:54.20#ibcon#*after write, iclass 27, count 2 2006.257.10:00:54.20#ibcon#*before return 0, iclass 27, count 2 2006.257.10:00:54.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:54.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:54.20#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.10:00:54.20#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:54.20#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:54.32#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:54.32#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:54.32#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:00:54.32#ibcon#first serial, iclass 27, count 0 2006.257.10:00:54.32#ibcon#enter sib2, iclass 27, count 0 2006.257.10:00:54.32#ibcon#flushed, iclass 27, count 0 2006.257.10:00:54.32#ibcon#about to write, iclass 27, count 0 2006.257.10:00:54.32#ibcon#wrote, iclass 27, count 0 2006.257.10:00:54.32#ibcon#about to read 3, iclass 27, count 0 2006.257.10:00:54.34#ibcon#read 3, iclass 27, count 0 2006.257.10:00:54.34#ibcon#about to read 4, iclass 27, count 0 2006.257.10:00:54.34#ibcon#read 4, iclass 27, count 0 2006.257.10:00:54.34#ibcon#about to read 5, iclass 27, count 0 2006.257.10:00:54.34#ibcon#read 5, iclass 27, count 0 2006.257.10:00:54.34#ibcon#about to read 6, iclass 27, count 0 2006.257.10:00:54.34#ibcon#read 6, iclass 27, count 0 2006.257.10:00:54.34#ibcon#end of sib2, iclass 27, count 0 2006.257.10:00:54.34#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:00:54.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:00:54.34#ibcon#[25=USB\r\n] 2006.257.10:00:54.34#ibcon#*before write, iclass 27, count 0 2006.257.10:00:54.34#ibcon#enter sib2, iclass 27, count 0 2006.257.10:00:54.34#ibcon#flushed, iclass 27, count 0 2006.257.10:00:54.34#ibcon#about to write, iclass 27, count 0 2006.257.10:00:54.34#ibcon#wrote, iclass 27, count 0 2006.257.10:00:54.34#ibcon#about to read 3, iclass 27, count 0 2006.257.10:00:54.37#ibcon#read 3, iclass 27, count 0 2006.257.10:00:54.37#ibcon#about to read 4, iclass 27, count 0 2006.257.10:00:54.37#ibcon#read 4, iclass 27, count 0 2006.257.10:00:54.37#ibcon#about to read 5, iclass 27, count 0 2006.257.10:00:54.37#ibcon#read 5, iclass 27, count 0 2006.257.10:00:54.37#ibcon#about to read 6, iclass 27, count 0 2006.257.10:00:54.37#ibcon#read 6, iclass 27, count 0 2006.257.10:00:54.37#ibcon#end of sib2, iclass 27, count 0 2006.257.10:00:54.37#ibcon#*after write, iclass 27, count 0 2006.257.10:00:54.37#ibcon#*before return 0, iclass 27, count 0 2006.257.10:00:54.37#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:54.37#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:54.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:00:54.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:00:54.37$vck44/valo=2,534.99 2006.257.10:00:54.37#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.10:00:54.37#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.10:00:54.37#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:54.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:54.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:54.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:54.37#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:00:54.37#ibcon#first serial, iclass 29, count 0 2006.257.10:00:54.37#ibcon#enter sib2, iclass 29, count 0 2006.257.10:00:54.37#ibcon#flushed, iclass 29, count 0 2006.257.10:00:54.37#ibcon#about to write, iclass 29, count 0 2006.257.10:00:54.37#ibcon#wrote, iclass 29, count 0 2006.257.10:00:54.37#ibcon#about to read 3, iclass 29, count 0 2006.257.10:00:54.39#ibcon#read 3, iclass 29, count 0 2006.257.10:00:54.39#ibcon#about to read 4, iclass 29, count 0 2006.257.10:00:54.39#ibcon#read 4, iclass 29, count 0 2006.257.10:00:54.39#ibcon#about to read 5, iclass 29, count 0 2006.257.10:00:54.39#ibcon#read 5, iclass 29, count 0 2006.257.10:00:54.39#ibcon#about to read 6, iclass 29, count 0 2006.257.10:00:54.39#ibcon#read 6, iclass 29, count 0 2006.257.10:00:54.39#ibcon#end of sib2, iclass 29, count 0 2006.257.10:00:54.39#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:00:54.39#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:00:54.39#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:00:54.39#ibcon#*before write, iclass 29, count 0 2006.257.10:00:54.39#ibcon#enter sib2, iclass 29, count 0 2006.257.10:00:54.39#ibcon#flushed, iclass 29, count 0 2006.257.10:00:54.39#ibcon#about to write, iclass 29, count 0 2006.257.10:00:54.39#ibcon#wrote, iclass 29, count 0 2006.257.10:00:54.39#ibcon#about to read 3, iclass 29, count 0 2006.257.10:00:54.43#ibcon#read 3, iclass 29, count 0 2006.257.10:00:54.43#ibcon#about to read 4, iclass 29, count 0 2006.257.10:00:54.43#ibcon#read 4, iclass 29, count 0 2006.257.10:00:54.43#ibcon#about to read 5, iclass 29, count 0 2006.257.10:00:54.43#ibcon#read 5, iclass 29, count 0 2006.257.10:00:54.43#ibcon#about to read 6, iclass 29, count 0 2006.257.10:00:54.43#ibcon#read 6, iclass 29, count 0 2006.257.10:00:54.43#ibcon#end of sib2, iclass 29, count 0 2006.257.10:00:54.43#ibcon#*after write, iclass 29, count 0 2006.257.10:00:54.43#ibcon#*before return 0, iclass 29, count 0 2006.257.10:00:54.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:54.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:54.43#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:00:54.43#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:00:54.43$vck44/va=2,7 2006.257.10:00:54.43#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.10:00:54.43#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.10:00:54.43#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:54.43#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:54.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:54.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:54.49#ibcon#enter wrdev, iclass 31, count 2 2006.257.10:00:54.49#ibcon#first serial, iclass 31, count 2 2006.257.10:00:54.49#ibcon#enter sib2, iclass 31, count 2 2006.257.10:00:54.49#ibcon#flushed, iclass 31, count 2 2006.257.10:00:54.49#ibcon#about to write, iclass 31, count 2 2006.257.10:00:54.49#ibcon#wrote, iclass 31, count 2 2006.257.10:00:54.49#ibcon#about to read 3, iclass 31, count 2 2006.257.10:00:54.51#ibcon#read 3, iclass 31, count 2 2006.257.10:00:54.51#ibcon#about to read 4, iclass 31, count 2 2006.257.10:00:54.51#ibcon#read 4, iclass 31, count 2 2006.257.10:00:54.51#ibcon#about to read 5, iclass 31, count 2 2006.257.10:00:54.51#ibcon#read 5, iclass 31, count 2 2006.257.10:00:54.51#ibcon#about to read 6, iclass 31, count 2 2006.257.10:00:54.51#ibcon#read 6, iclass 31, count 2 2006.257.10:00:54.51#ibcon#end of sib2, iclass 31, count 2 2006.257.10:00:54.51#ibcon#*mode == 0, iclass 31, count 2 2006.257.10:00:54.51#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.10:00:54.51#ibcon#[25=AT02-07\r\n] 2006.257.10:00:54.51#ibcon#*before write, iclass 31, count 2 2006.257.10:00:54.51#ibcon#enter sib2, iclass 31, count 2 2006.257.10:00:54.51#ibcon#flushed, iclass 31, count 2 2006.257.10:00:54.51#ibcon#about to write, iclass 31, count 2 2006.257.10:00:54.51#ibcon#wrote, iclass 31, count 2 2006.257.10:00:54.51#ibcon#about to read 3, iclass 31, count 2 2006.257.10:00:54.54#ibcon#read 3, iclass 31, count 2 2006.257.10:00:54.54#ibcon#about to read 4, iclass 31, count 2 2006.257.10:00:54.54#ibcon#read 4, iclass 31, count 2 2006.257.10:00:54.54#ibcon#about to read 5, iclass 31, count 2 2006.257.10:00:54.54#ibcon#read 5, iclass 31, count 2 2006.257.10:00:54.54#ibcon#about to read 6, iclass 31, count 2 2006.257.10:00:54.54#ibcon#read 6, iclass 31, count 2 2006.257.10:00:54.54#ibcon#end of sib2, iclass 31, count 2 2006.257.10:00:54.54#ibcon#*after write, iclass 31, count 2 2006.257.10:00:54.54#ibcon#*before return 0, iclass 31, count 2 2006.257.10:00:54.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:54.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:54.54#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.10:00:54.54#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:54.54#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:54.66#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:54.66#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:54.66#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:00:54.66#ibcon#first serial, iclass 31, count 0 2006.257.10:00:54.66#ibcon#enter sib2, iclass 31, count 0 2006.257.10:00:54.66#ibcon#flushed, iclass 31, count 0 2006.257.10:00:54.66#ibcon#about to write, iclass 31, count 0 2006.257.10:00:54.66#ibcon#wrote, iclass 31, count 0 2006.257.10:00:54.66#ibcon#about to read 3, iclass 31, count 0 2006.257.10:00:54.68#ibcon#read 3, iclass 31, count 0 2006.257.10:00:54.68#ibcon#about to read 4, iclass 31, count 0 2006.257.10:00:54.68#ibcon#read 4, iclass 31, count 0 2006.257.10:00:54.68#ibcon#about to read 5, iclass 31, count 0 2006.257.10:00:54.68#ibcon#read 5, iclass 31, count 0 2006.257.10:00:54.68#ibcon#about to read 6, iclass 31, count 0 2006.257.10:00:54.68#ibcon#read 6, iclass 31, count 0 2006.257.10:00:54.68#ibcon#end of sib2, iclass 31, count 0 2006.257.10:00:54.68#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:00:54.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:00:54.68#ibcon#[25=USB\r\n] 2006.257.10:00:54.68#ibcon#*before write, iclass 31, count 0 2006.257.10:00:54.68#ibcon#enter sib2, iclass 31, count 0 2006.257.10:00:54.68#ibcon#flushed, iclass 31, count 0 2006.257.10:00:54.68#ibcon#about to write, iclass 31, count 0 2006.257.10:00:54.68#ibcon#wrote, iclass 31, count 0 2006.257.10:00:54.68#ibcon#about to read 3, iclass 31, count 0 2006.257.10:00:54.71#ibcon#read 3, iclass 31, count 0 2006.257.10:00:54.71#ibcon#about to read 4, iclass 31, count 0 2006.257.10:00:54.71#ibcon#read 4, iclass 31, count 0 2006.257.10:00:54.71#ibcon#about to read 5, iclass 31, count 0 2006.257.10:00:54.71#ibcon#read 5, iclass 31, count 0 2006.257.10:00:54.71#ibcon#about to read 6, iclass 31, count 0 2006.257.10:00:54.71#ibcon#read 6, iclass 31, count 0 2006.257.10:00:54.71#ibcon#end of sib2, iclass 31, count 0 2006.257.10:00:54.71#ibcon#*after write, iclass 31, count 0 2006.257.10:00:54.71#ibcon#*before return 0, iclass 31, count 0 2006.257.10:00:54.71#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:54.71#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:54.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:00:54.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:00:54.71$vck44/valo=3,564.99 2006.257.10:00:54.71#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.10:00:54.71#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.10:00:54.71#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:54.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:54.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:54.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:54.71#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:00:54.71#ibcon#first serial, iclass 33, count 0 2006.257.10:00:54.71#ibcon#enter sib2, iclass 33, count 0 2006.257.10:00:54.71#ibcon#flushed, iclass 33, count 0 2006.257.10:00:54.71#ibcon#about to write, iclass 33, count 0 2006.257.10:00:54.71#ibcon#wrote, iclass 33, count 0 2006.257.10:00:54.71#ibcon#about to read 3, iclass 33, count 0 2006.257.10:00:54.73#ibcon#read 3, iclass 33, count 0 2006.257.10:00:54.73#ibcon#about to read 4, iclass 33, count 0 2006.257.10:00:54.73#ibcon#read 4, iclass 33, count 0 2006.257.10:00:54.73#ibcon#about to read 5, iclass 33, count 0 2006.257.10:00:54.73#ibcon#read 5, iclass 33, count 0 2006.257.10:00:54.73#ibcon#about to read 6, iclass 33, count 0 2006.257.10:00:54.73#ibcon#read 6, iclass 33, count 0 2006.257.10:00:54.73#ibcon#end of sib2, iclass 33, count 0 2006.257.10:00:54.73#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:00:54.73#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:00:54.73#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:00:54.73#ibcon#*before write, iclass 33, count 0 2006.257.10:00:54.73#ibcon#enter sib2, iclass 33, count 0 2006.257.10:00:54.73#ibcon#flushed, iclass 33, count 0 2006.257.10:00:54.73#ibcon#about to write, iclass 33, count 0 2006.257.10:00:54.73#ibcon#wrote, iclass 33, count 0 2006.257.10:00:54.73#ibcon#about to read 3, iclass 33, count 0 2006.257.10:00:54.77#ibcon#read 3, iclass 33, count 0 2006.257.10:00:54.77#ibcon#about to read 4, iclass 33, count 0 2006.257.10:00:54.77#ibcon#read 4, iclass 33, count 0 2006.257.10:00:54.77#ibcon#about to read 5, iclass 33, count 0 2006.257.10:00:54.77#ibcon#read 5, iclass 33, count 0 2006.257.10:00:54.77#ibcon#about to read 6, iclass 33, count 0 2006.257.10:00:54.77#ibcon#read 6, iclass 33, count 0 2006.257.10:00:54.77#ibcon#end of sib2, iclass 33, count 0 2006.257.10:00:54.77#ibcon#*after write, iclass 33, count 0 2006.257.10:00:54.77#ibcon#*before return 0, iclass 33, count 0 2006.257.10:00:54.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:54.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:54.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:00:54.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:00:54.77$vck44/va=3,8 2006.257.10:00:54.77#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.10:00:54.77#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.10:00:54.77#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:54.77#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:54.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:54.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:54.83#ibcon#enter wrdev, iclass 35, count 2 2006.257.10:00:54.83#ibcon#first serial, iclass 35, count 2 2006.257.10:00:54.83#ibcon#enter sib2, iclass 35, count 2 2006.257.10:00:54.83#ibcon#flushed, iclass 35, count 2 2006.257.10:00:54.83#ibcon#about to write, iclass 35, count 2 2006.257.10:00:54.83#ibcon#wrote, iclass 35, count 2 2006.257.10:00:54.83#ibcon#about to read 3, iclass 35, count 2 2006.257.10:00:54.85#ibcon#read 3, iclass 35, count 2 2006.257.10:00:54.85#ibcon#about to read 4, iclass 35, count 2 2006.257.10:00:54.85#ibcon#read 4, iclass 35, count 2 2006.257.10:00:54.85#ibcon#about to read 5, iclass 35, count 2 2006.257.10:00:54.85#ibcon#read 5, iclass 35, count 2 2006.257.10:00:54.85#ibcon#about to read 6, iclass 35, count 2 2006.257.10:00:54.85#ibcon#read 6, iclass 35, count 2 2006.257.10:00:54.85#ibcon#end of sib2, iclass 35, count 2 2006.257.10:00:54.85#ibcon#*mode == 0, iclass 35, count 2 2006.257.10:00:54.85#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.10:00:54.85#ibcon#[25=AT03-08\r\n] 2006.257.10:00:54.85#ibcon#*before write, iclass 35, count 2 2006.257.10:00:54.85#ibcon#enter sib2, iclass 35, count 2 2006.257.10:00:54.85#ibcon#flushed, iclass 35, count 2 2006.257.10:00:54.85#ibcon#about to write, iclass 35, count 2 2006.257.10:00:54.85#ibcon#wrote, iclass 35, count 2 2006.257.10:00:54.85#ibcon#about to read 3, iclass 35, count 2 2006.257.10:00:54.88#ibcon#read 3, iclass 35, count 2 2006.257.10:00:54.88#ibcon#about to read 4, iclass 35, count 2 2006.257.10:00:54.88#ibcon#read 4, iclass 35, count 2 2006.257.10:00:54.88#ibcon#about to read 5, iclass 35, count 2 2006.257.10:00:54.88#ibcon#read 5, iclass 35, count 2 2006.257.10:00:54.88#ibcon#about to read 6, iclass 35, count 2 2006.257.10:00:54.88#ibcon#read 6, iclass 35, count 2 2006.257.10:00:54.88#ibcon#end of sib2, iclass 35, count 2 2006.257.10:00:54.88#ibcon#*after write, iclass 35, count 2 2006.257.10:00:54.88#ibcon#*before return 0, iclass 35, count 2 2006.257.10:00:54.88#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:54.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:54.88#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.10:00:54.88#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:54.88#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:55.00#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:55.00#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:55.00#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:00:55.00#ibcon#first serial, iclass 35, count 0 2006.257.10:00:55.00#ibcon#enter sib2, iclass 35, count 0 2006.257.10:00:55.00#ibcon#flushed, iclass 35, count 0 2006.257.10:00:55.00#ibcon#about to write, iclass 35, count 0 2006.257.10:00:55.00#ibcon#wrote, iclass 35, count 0 2006.257.10:00:55.00#ibcon#about to read 3, iclass 35, count 0 2006.257.10:00:55.02#ibcon#read 3, iclass 35, count 0 2006.257.10:00:55.02#ibcon#about to read 4, iclass 35, count 0 2006.257.10:00:55.02#ibcon#read 4, iclass 35, count 0 2006.257.10:00:55.02#ibcon#about to read 5, iclass 35, count 0 2006.257.10:00:55.02#ibcon#read 5, iclass 35, count 0 2006.257.10:00:55.02#ibcon#about to read 6, iclass 35, count 0 2006.257.10:00:55.02#ibcon#read 6, iclass 35, count 0 2006.257.10:00:55.02#ibcon#end of sib2, iclass 35, count 0 2006.257.10:00:55.02#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:00:55.02#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:00:55.02#ibcon#[25=USB\r\n] 2006.257.10:00:55.02#ibcon#*before write, iclass 35, count 0 2006.257.10:00:55.02#ibcon#enter sib2, iclass 35, count 0 2006.257.10:00:55.02#ibcon#flushed, iclass 35, count 0 2006.257.10:00:55.02#ibcon#about to write, iclass 35, count 0 2006.257.10:00:55.02#ibcon#wrote, iclass 35, count 0 2006.257.10:00:55.02#ibcon#about to read 3, iclass 35, count 0 2006.257.10:00:55.05#ibcon#read 3, iclass 35, count 0 2006.257.10:00:55.05#ibcon#about to read 4, iclass 35, count 0 2006.257.10:00:55.05#ibcon#read 4, iclass 35, count 0 2006.257.10:00:55.05#ibcon#about to read 5, iclass 35, count 0 2006.257.10:00:55.05#ibcon#read 5, iclass 35, count 0 2006.257.10:00:55.05#ibcon#about to read 6, iclass 35, count 0 2006.257.10:00:55.05#ibcon#read 6, iclass 35, count 0 2006.257.10:00:55.05#ibcon#end of sib2, iclass 35, count 0 2006.257.10:00:55.05#ibcon#*after write, iclass 35, count 0 2006.257.10:00:55.05#ibcon#*before return 0, iclass 35, count 0 2006.257.10:00:55.05#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:55.05#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:55.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:00:55.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:00:55.05$vck44/valo=4,624.99 2006.257.10:00:55.05#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.10:00:55.05#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.10:00:55.05#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:55.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:55.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:55.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:55.05#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:00:55.05#ibcon#first serial, iclass 37, count 0 2006.257.10:00:55.05#ibcon#enter sib2, iclass 37, count 0 2006.257.10:00:55.05#ibcon#flushed, iclass 37, count 0 2006.257.10:00:55.05#ibcon#about to write, iclass 37, count 0 2006.257.10:00:55.05#ibcon#wrote, iclass 37, count 0 2006.257.10:00:55.05#ibcon#about to read 3, iclass 37, count 0 2006.257.10:00:55.07#ibcon#read 3, iclass 37, count 0 2006.257.10:00:55.07#ibcon#about to read 4, iclass 37, count 0 2006.257.10:00:55.07#ibcon#read 4, iclass 37, count 0 2006.257.10:00:55.07#ibcon#about to read 5, iclass 37, count 0 2006.257.10:00:55.07#ibcon#read 5, iclass 37, count 0 2006.257.10:00:55.07#ibcon#about to read 6, iclass 37, count 0 2006.257.10:00:55.07#ibcon#read 6, iclass 37, count 0 2006.257.10:00:55.07#ibcon#end of sib2, iclass 37, count 0 2006.257.10:00:55.07#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:00:55.07#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:00:55.07#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:00:55.07#ibcon#*before write, iclass 37, count 0 2006.257.10:00:55.07#ibcon#enter sib2, iclass 37, count 0 2006.257.10:00:55.07#ibcon#flushed, iclass 37, count 0 2006.257.10:00:55.07#ibcon#about to write, iclass 37, count 0 2006.257.10:00:55.07#ibcon#wrote, iclass 37, count 0 2006.257.10:00:55.07#ibcon#about to read 3, iclass 37, count 0 2006.257.10:00:55.11#ibcon#read 3, iclass 37, count 0 2006.257.10:00:55.11#ibcon#about to read 4, iclass 37, count 0 2006.257.10:00:55.11#ibcon#read 4, iclass 37, count 0 2006.257.10:00:55.11#ibcon#about to read 5, iclass 37, count 0 2006.257.10:00:55.11#ibcon#read 5, iclass 37, count 0 2006.257.10:00:55.11#ibcon#about to read 6, iclass 37, count 0 2006.257.10:00:55.11#ibcon#read 6, iclass 37, count 0 2006.257.10:00:55.11#ibcon#end of sib2, iclass 37, count 0 2006.257.10:00:55.11#ibcon#*after write, iclass 37, count 0 2006.257.10:00:55.11#ibcon#*before return 0, iclass 37, count 0 2006.257.10:00:55.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:55.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:55.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:00:55.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:00:55.11$vck44/va=4,7 2006.257.10:00:55.11#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.10:00:55.11#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.10:00:55.11#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:55.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:55.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:55.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:55.17#ibcon#enter wrdev, iclass 39, count 2 2006.257.10:00:55.17#ibcon#first serial, iclass 39, count 2 2006.257.10:00:55.17#ibcon#enter sib2, iclass 39, count 2 2006.257.10:00:55.17#ibcon#flushed, iclass 39, count 2 2006.257.10:00:55.17#ibcon#about to write, iclass 39, count 2 2006.257.10:00:55.17#ibcon#wrote, iclass 39, count 2 2006.257.10:00:55.17#ibcon#about to read 3, iclass 39, count 2 2006.257.10:00:55.19#ibcon#read 3, iclass 39, count 2 2006.257.10:00:55.19#ibcon#about to read 4, iclass 39, count 2 2006.257.10:00:55.19#ibcon#read 4, iclass 39, count 2 2006.257.10:00:55.19#ibcon#about to read 5, iclass 39, count 2 2006.257.10:00:55.19#ibcon#read 5, iclass 39, count 2 2006.257.10:00:55.19#ibcon#about to read 6, iclass 39, count 2 2006.257.10:00:55.19#ibcon#read 6, iclass 39, count 2 2006.257.10:00:55.19#ibcon#end of sib2, iclass 39, count 2 2006.257.10:00:55.19#ibcon#*mode == 0, iclass 39, count 2 2006.257.10:00:55.19#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.10:00:55.19#ibcon#[25=AT04-07\r\n] 2006.257.10:00:55.19#ibcon#*before write, iclass 39, count 2 2006.257.10:00:55.19#ibcon#enter sib2, iclass 39, count 2 2006.257.10:00:55.19#ibcon#flushed, iclass 39, count 2 2006.257.10:00:55.19#ibcon#about to write, iclass 39, count 2 2006.257.10:00:55.19#ibcon#wrote, iclass 39, count 2 2006.257.10:00:55.19#ibcon#about to read 3, iclass 39, count 2 2006.257.10:00:55.22#ibcon#read 3, iclass 39, count 2 2006.257.10:00:55.22#ibcon#about to read 4, iclass 39, count 2 2006.257.10:00:55.22#ibcon#read 4, iclass 39, count 2 2006.257.10:00:55.22#ibcon#about to read 5, iclass 39, count 2 2006.257.10:00:55.22#ibcon#read 5, iclass 39, count 2 2006.257.10:00:55.22#ibcon#about to read 6, iclass 39, count 2 2006.257.10:00:55.22#ibcon#read 6, iclass 39, count 2 2006.257.10:00:55.22#ibcon#end of sib2, iclass 39, count 2 2006.257.10:00:55.22#ibcon#*after write, iclass 39, count 2 2006.257.10:00:55.22#ibcon#*before return 0, iclass 39, count 2 2006.257.10:00:55.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:55.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:55.22#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.10:00:55.22#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:55.22#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:55.34#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:55.34#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:55.34#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:00:55.34#ibcon#first serial, iclass 39, count 0 2006.257.10:00:55.34#ibcon#enter sib2, iclass 39, count 0 2006.257.10:00:55.34#ibcon#flushed, iclass 39, count 0 2006.257.10:00:55.34#ibcon#about to write, iclass 39, count 0 2006.257.10:00:55.34#ibcon#wrote, iclass 39, count 0 2006.257.10:00:55.34#ibcon#about to read 3, iclass 39, count 0 2006.257.10:00:55.36#ibcon#read 3, iclass 39, count 0 2006.257.10:00:55.36#ibcon#about to read 4, iclass 39, count 0 2006.257.10:00:55.36#ibcon#read 4, iclass 39, count 0 2006.257.10:00:55.36#ibcon#about to read 5, iclass 39, count 0 2006.257.10:00:55.36#ibcon#read 5, iclass 39, count 0 2006.257.10:00:55.36#ibcon#about to read 6, iclass 39, count 0 2006.257.10:00:55.36#ibcon#read 6, iclass 39, count 0 2006.257.10:00:55.36#ibcon#end of sib2, iclass 39, count 0 2006.257.10:00:55.36#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:00:55.36#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:00:55.36#ibcon#[25=USB\r\n] 2006.257.10:00:55.36#ibcon#*before write, iclass 39, count 0 2006.257.10:00:55.36#ibcon#enter sib2, iclass 39, count 0 2006.257.10:00:55.36#ibcon#flushed, iclass 39, count 0 2006.257.10:00:55.36#ibcon#about to write, iclass 39, count 0 2006.257.10:00:55.36#ibcon#wrote, iclass 39, count 0 2006.257.10:00:55.36#ibcon#about to read 3, iclass 39, count 0 2006.257.10:00:55.39#ibcon#read 3, iclass 39, count 0 2006.257.10:00:55.39#ibcon#about to read 4, iclass 39, count 0 2006.257.10:00:55.39#ibcon#read 4, iclass 39, count 0 2006.257.10:00:55.39#ibcon#about to read 5, iclass 39, count 0 2006.257.10:00:55.39#ibcon#read 5, iclass 39, count 0 2006.257.10:00:55.39#ibcon#about to read 6, iclass 39, count 0 2006.257.10:00:55.39#ibcon#read 6, iclass 39, count 0 2006.257.10:00:55.39#ibcon#end of sib2, iclass 39, count 0 2006.257.10:00:55.39#ibcon#*after write, iclass 39, count 0 2006.257.10:00:55.39#ibcon#*before return 0, iclass 39, count 0 2006.257.10:00:55.39#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:55.39#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:55.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:00:55.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:00:55.39$vck44/valo=5,734.99 2006.257.10:00:55.39#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.10:00:55.39#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.10:00:55.39#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:55.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:55.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:55.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:55.39#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:00:55.39#ibcon#first serial, iclass 3, count 0 2006.257.10:00:55.39#ibcon#enter sib2, iclass 3, count 0 2006.257.10:00:55.39#ibcon#flushed, iclass 3, count 0 2006.257.10:00:55.39#ibcon#about to write, iclass 3, count 0 2006.257.10:00:55.39#ibcon#wrote, iclass 3, count 0 2006.257.10:00:55.39#ibcon#about to read 3, iclass 3, count 0 2006.257.10:00:55.41#ibcon#read 3, iclass 3, count 0 2006.257.10:00:55.41#ibcon#about to read 4, iclass 3, count 0 2006.257.10:00:55.41#ibcon#read 4, iclass 3, count 0 2006.257.10:00:55.41#ibcon#about to read 5, iclass 3, count 0 2006.257.10:00:55.41#ibcon#read 5, iclass 3, count 0 2006.257.10:00:55.41#ibcon#about to read 6, iclass 3, count 0 2006.257.10:00:55.41#ibcon#read 6, iclass 3, count 0 2006.257.10:00:55.41#ibcon#end of sib2, iclass 3, count 0 2006.257.10:00:55.41#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:00:55.41#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:00:55.41#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:00:55.41#ibcon#*before write, iclass 3, count 0 2006.257.10:00:55.41#ibcon#enter sib2, iclass 3, count 0 2006.257.10:00:55.41#ibcon#flushed, iclass 3, count 0 2006.257.10:00:55.41#ibcon#about to write, iclass 3, count 0 2006.257.10:00:55.41#ibcon#wrote, iclass 3, count 0 2006.257.10:00:55.41#ibcon#about to read 3, iclass 3, count 0 2006.257.10:00:55.45#ibcon#read 3, iclass 3, count 0 2006.257.10:00:55.45#ibcon#about to read 4, iclass 3, count 0 2006.257.10:00:55.45#ibcon#read 4, iclass 3, count 0 2006.257.10:00:55.45#ibcon#about to read 5, iclass 3, count 0 2006.257.10:00:55.45#ibcon#read 5, iclass 3, count 0 2006.257.10:00:55.45#ibcon#about to read 6, iclass 3, count 0 2006.257.10:00:55.45#ibcon#read 6, iclass 3, count 0 2006.257.10:00:55.45#ibcon#end of sib2, iclass 3, count 0 2006.257.10:00:55.45#ibcon#*after write, iclass 3, count 0 2006.257.10:00:55.45#ibcon#*before return 0, iclass 3, count 0 2006.257.10:00:55.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:55.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:55.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:00:55.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:00:55.45$vck44/va=5,4 2006.257.10:00:55.45#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.10:00:55.45#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.10:00:55.45#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:55.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:55.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:55.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:55.51#ibcon#enter wrdev, iclass 5, count 2 2006.257.10:00:55.51#ibcon#first serial, iclass 5, count 2 2006.257.10:00:55.51#ibcon#enter sib2, iclass 5, count 2 2006.257.10:00:55.51#ibcon#flushed, iclass 5, count 2 2006.257.10:00:55.51#ibcon#about to write, iclass 5, count 2 2006.257.10:00:55.51#ibcon#wrote, iclass 5, count 2 2006.257.10:00:55.51#ibcon#about to read 3, iclass 5, count 2 2006.257.10:00:55.53#ibcon#read 3, iclass 5, count 2 2006.257.10:00:55.53#ibcon#about to read 4, iclass 5, count 2 2006.257.10:00:55.53#ibcon#read 4, iclass 5, count 2 2006.257.10:00:55.53#ibcon#about to read 5, iclass 5, count 2 2006.257.10:00:55.53#ibcon#read 5, iclass 5, count 2 2006.257.10:00:55.53#ibcon#about to read 6, iclass 5, count 2 2006.257.10:00:55.53#ibcon#read 6, iclass 5, count 2 2006.257.10:00:55.53#ibcon#end of sib2, iclass 5, count 2 2006.257.10:00:55.53#ibcon#*mode == 0, iclass 5, count 2 2006.257.10:00:55.53#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.10:00:55.53#ibcon#[25=AT05-04\r\n] 2006.257.10:00:55.53#ibcon#*before write, iclass 5, count 2 2006.257.10:00:55.53#ibcon#enter sib2, iclass 5, count 2 2006.257.10:00:55.53#ibcon#flushed, iclass 5, count 2 2006.257.10:00:55.53#ibcon#about to write, iclass 5, count 2 2006.257.10:00:55.53#ibcon#wrote, iclass 5, count 2 2006.257.10:00:55.53#ibcon#about to read 3, iclass 5, count 2 2006.257.10:00:55.56#ibcon#read 3, iclass 5, count 2 2006.257.10:00:55.56#ibcon#about to read 4, iclass 5, count 2 2006.257.10:00:55.56#ibcon#read 4, iclass 5, count 2 2006.257.10:00:55.56#ibcon#about to read 5, iclass 5, count 2 2006.257.10:00:55.56#ibcon#read 5, iclass 5, count 2 2006.257.10:00:55.56#ibcon#about to read 6, iclass 5, count 2 2006.257.10:00:55.56#ibcon#read 6, iclass 5, count 2 2006.257.10:00:55.56#ibcon#end of sib2, iclass 5, count 2 2006.257.10:00:55.56#ibcon#*after write, iclass 5, count 2 2006.257.10:00:55.56#ibcon#*before return 0, iclass 5, count 2 2006.257.10:00:55.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:55.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:55.56#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.10:00:55.56#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:55.56#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:55.68#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:55.68#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:55.68#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:00:55.68#ibcon#first serial, iclass 5, count 0 2006.257.10:00:55.68#ibcon#enter sib2, iclass 5, count 0 2006.257.10:00:55.68#ibcon#flushed, iclass 5, count 0 2006.257.10:00:55.68#ibcon#about to write, iclass 5, count 0 2006.257.10:00:55.68#ibcon#wrote, iclass 5, count 0 2006.257.10:00:55.68#ibcon#about to read 3, iclass 5, count 0 2006.257.10:00:55.70#ibcon#read 3, iclass 5, count 0 2006.257.10:00:55.70#ibcon#about to read 4, iclass 5, count 0 2006.257.10:00:55.70#ibcon#read 4, iclass 5, count 0 2006.257.10:00:55.70#ibcon#about to read 5, iclass 5, count 0 2006.257.10:00:55.70#ibcon#read 5, iclass 5, count 0 2006.257.10:00:55.70#ibcon#about to read 6, iclass 5, count 0 2006.257.10:00:55.70#ibcon#read 6, iclass 5, count 0 2006.257.10:00:55.70#ibcon#end of sib2, iclass 5, count 0 2006.257.10:00:55.70#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:00:55.70#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:00:55.70#ibcon#[25=USB\r\n] 2006.257.10:00:55.70#ibcon#*before write, iclass 5, count 0 2006.257.10:00:55.70#ibcon#enter sib2, iclass 5, count 0 2006.257.10:00:55.70#ibcon#flushed, iclass 5, count 0 2006.257.10:00:55.70#ibcon#about to write, iclass 5, count 0 2006.257.10:00:55.70#ibcon#wrote, iclass 5, count 0 2006.257.10:00:55.70#ibcon#about to read 3, iclass 5, count 0 2006.257.10:00:55.73#ibcon#read 3, iclass 5, count 0 2006.257.10:00:55.73#ibcon#about to read 4, iclass 5, count 0 2006.257.10:00:55.73#ibcon#read 4, iclass 5, count 0 2006.257.10:00:55.73#ibcon#about to read 5, iclass 5, count 0 2006.257.10:00:55.73#ibcon#read 5, iclass 5, count 0 2006.257.10:00:55.73#ibcon#about to read 6, iclass 5, count 0 2006.257.10:00:55.73#ibcon#read 6, iclass 5, count 0 2006.257.10:00:55.73#ibcon#end of sib2, iclass 5, count 0 2006.257.10:00:55.73#ibcon#*after write, iclass 5, count 0 2006.257.10:00:55.73#ibcon#*before return 0, iclass 5, count 0 2006.257.10:00:55.73#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:55.73#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:55.73#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:00:55.73#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:00:55.73$vck44/valo=6,814.99 2006.257.10:00:55.73#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.10:00:55.73#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.10:00:55.73#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:55.73#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:55.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:55.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:55.73#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:00:55.73#ibcon#first serial, iclass 7, count 0 2006.257.10:00:55.73#ibcon#enter sib2, iclass 7, count 0 2006.257.10:00:55.73#ibcon#flushed, iclass 7, count 0 2006.257.10:00:55.73#ibcon#about to write, iclass 7, count 0 2006.257.10:00:55.73#ibcon#wrote, iclass 7, count 0 2006.257.10:00:55.73#ibcon#about to read 3, iclass 7, count 0 2006.257.10:00:55.75#ibcon#read 3, iclass 7, count 0 2006.257.10:00:55.75#ibcon#about to read 4, iclass 7, count 0 2006.257.10:00:55.75#ibcon#read 4, iclass 7, count 0 2006.257.10:00:55.75#ibcon#about to read 5, iclass 7, count 0 2006.257.10:00:55.75#ibcon#read 5, iclass 7, count 0 2006.257.10:00:55.75#ibcon#about to read 6, iclass 7, count 0 2006.257.10:00:55.75#ibcon#read 6, iclass 7, count 0 2006.257.10:00:55.75#ibcon#end of sib2, iclass 7, count 0 2006.257.10:00:55.75#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:00:55.75#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:00:55.75#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:00:55.75#ibcon#*before write, iclass 7, count 0 2006.257.10:00:55.75#ibcon#enter sib2, iclass 7, count 0 2006.257.10:00:55.75#ibcon#flushed, iclass 7, count 0 2006.257.10:00:55.75#ibcon#about to write, iclass 7, count 0 2006.257.10:00:55.75#ibcon#wrote, iclass 7, count 0 2006.257.10:00:55.75#ibcon#about to read 3, iclass 7, count 0 2006.257.10:00:55.79#ibcon#read 3, iclass 7, count 0 2006.257.10:00:55.79#ibcon#about to read 4, iclass 7, count 0 2006.257.10:00:55.79#ibcon#read 4, iclass 7, count 0 2006.257.10:00:55.79#ibcon#about to read 5, iclass 7, count 0 2006.257.10:00:55.79#ibcon#read 5, iclass 7, count 0 2006.257.10:00:55.79#ibcon#about to read 6, iclass 7, count 0 2006.257.10:00:55.79#ibcon#read 6, iclass 7, count 0 2006.257.10:00:55.79#ibcon#end of sib2, iclass 7, count 0 2006.257.10:00:55.79#ibcon#*after write, iclass 7, count 0 2006.257.10:00:55.79#ibcon#*before return 0, iclass 7, count 0 2006.257.10:00:55.79#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:55.79#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:55.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:00:55.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:00:55.79$vck44/va=6,4 2006.257.10:00:55.79#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.10:00:55.79#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.10:00:55.79#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:55.79#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:55.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:55.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:55.85#ibcon#enter wrdev, iclass 11, count 2 2006.257.10:00:55.85#ibcon#first serial, iclass 11, count 2 2006.257.10:00:55.85#ibcon#enter sib2, iclass 11, count 2 2006.257.10:00:55.85#ibcon#flushed, iclass 11, count 2 2006.257.10:00:55.85#ibcon#about to write, iclass 11, count 2 2006.257.10:00:55.85#ibcon#wrote, iclass 11, count 2 2006.257.10:00:55.85#ibcon#about to read 3, iclass 11, count 2 2006.257.10:00:55.87#ibcon#read 3, iclass 11, count 2 2006.257.10:00:55.87#ibcon#about to read 4, iclass 11, count 2 2006.257.10:00:55.87#ibcon#read 4, iclass 11, count 2 2006.257.10:00:55.87#ibcon#about to read 5, iclass 11, count 2 2006.257.10:00:55.87#ibcon#read 5, iclass 11, count 2 2006.257.10:00:55.87#ibcon#about to read 6, iclass 11, count 2 2006.257.10:00:55.87#ibcon#read 6, iclass 11, count 2 2006.257.10:00:55.87#ibcon#end of sib2, iclass 11, count 2 2006.257.10:00:55.87#ibcon#*mode == 0, iclass 11, count 2 2006.257.10:00:55.87#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.10:00:55.87#ibcon#[25=AT06-04\r\n] 2006.257.10:00:55.87#ibcon#*before write, iclass 11, count 2 2006.257.10:00:55.87#ibcon#enter sib2, iclass 11, count 2 2006.257.10:00:55.87#ibcon#flushed, iclass 11, count 2 2006.257.10:00:55.87#ibcon#about to write, iclass 11, count 2 2006.257.10:00:55.87#ibcon#wrote, iclass 11, count 2 2006.257.10:00:55.87#ibcon#about to read 3, iclass 11, count 2 2006.257.10:00:55.90#ibcon#read 3, iclass 11, count 2 2006.257.10:00:55.90#ibcon#about to read 4, iclass 11, count 2 2006.257.10:00:55.90#ibcon#read 4, iclass 11, count 2 2006.257.10:00:55.90#ibcon#about to read 5, iclass 11, count 2 2006.257.10:00:55.90#ibcon#read 5, iclass 11, count 2 2006.257.10:00:55.90#ibcon#about to read 6, iclass 11, count 2 2006.257.10:00:55.90#ibcon#read 6, iclass 11, count 2 2006.257.10:00:55.90#ibcon#end of sib2, iclass 11, count 2 2006.257.10:00:55.90#ibcon#*after write, iclass 11, count 2 2006.257.10:00:55.90#ibcon#*before return 0, iclass 11, count 2 2006.257.10:00:55.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:55.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:55.90#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.10:00:55.90#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:55.90#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:56.02#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:56.02#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:56.02#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:00:56.02#ibcon#first serial, iclass 11, count 0 2006.257.10:00:56.02#ibcon#enter sib2, iclass 11, count 0 2006.257.10:00:56.02#ibcon#flushed, iclass 11, count 0 2006.257.10:00:56.02#ibcon#about to write, iclass 11, count 0 2006.257.10:00:56.02#ibcon#wrote, iclass 11, count 0 2006.257.10:00:56.02#ibcon#about to read 3, iclass 11, count 0 2006.257.10:00:56.04#ibcon#read 3, iclass 11, count 0 2006.257.10:00:56.04#ibcon#about to read 4, iclass 11, count 0 2006.257.10:00:56.04#ibcon#read 4, iclass 11, count 0 2006.257.10:00:56.04#ibcon#about to read 5, iclass 11, count 0 2006.257.10:00:56.04#ibcon#read 5, iclass 11, count 0 2006.257.10:00:56.04#ibcon#about to read 6, iclass 11, count 0 2006.257.10:00:56.04#ibcon#read 6, iclass 11, count 0 2006.257.10:00:56.04#ibcon#end of sib2, iclass 11, count 0 2006.257.10:00:56.04#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:00:56.04#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:00:56.04#ibcon#[25=USB\r\n] 2006.257.10:00:56.04#ibcon#*before write, iclass 11, count 0 2006.257.10:00:56.04#ibcon#enter sib2, iclass 11, count 0 2006.257.10:00:56.04#ibcon#flushed, iclass 11, count 0 2006.257.10:00:56.04#ibcon#about to write, iclass 11, count 0 2006.257.10:00:56.04#ibcon#wrote, iclass 11, count 0 2006.257.10:00:56.04#ibcon#about to read 3, iclass 11, count 0 2006.257.10:00:56.07#ibcon#read 3, iclass 11, count 0 2006.257.10:00:56.07#ibcon#about to read 4, iclass 11, count 0 2006.257.10:00:56.07#ibcon#read 4, iclass 11, count 0 2006.257.10:00:56.07#ibcon#about to read 5, iclass 11, count 0 2006.257.10:00:56.07#ibcon#read 5, iclass 11, count 0 2006.257.10:00:56.07#ibcon#about to read 6, iclass 11, count 0 2006.257.10:00:56.07#ibcon#read 6, iclass 11, count 0 2006.257.10:00:56.07#ibcon#end of sib2, iclass 11, count 0 2006.257.10:00:56.07#ibcon#*after write, iclass 11, count 0 2006.257.10:00:56.07#ibcon#*before return 0, iclass 11, count 0 2006.257.10:00:56.07#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:56.07#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:56.07#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:00:56.07#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:00:56.07$vck44/valo=7,864.99 2006.257.10:00:56.07#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.10:00:56.07#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.10:00:56.07#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:56.07#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:56.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:56.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:56.07#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:00:56.07#ibcon#first serial, iclass 13, count 0 2006.257.10:00:56.07#ibcon#enter sib2, iclass 13, count 0 2006.257.10:00:56.07#ibcon#flushed, iclass 13, count 0 2006.257.10:00:56.07#ibcon#about to write, iclass 13, count 0 2006.257.10:00:56.07#ibcon#wrote, iclass 13, count 0 2006.257.10:00:56.07#ibcon#about to read 3, iclass 13, count 0 2006.257.10:00:56.09#ibcon#read 3, iclass 13, count 0 2006.257.10:00:56.09#ibcon#about to read 4, iclass 13, count 0 2006.257.10:00:56.09#ibcon#read 4, iclass 13, count 0 2006.257.10:00:56.09#ibcon#about to read 5, iclass 13, count 0 2006.257.10:00:56.09#ibcon#read 5, iclass 13, count 0 2006.257.10:00:56.09#ibcon#about to read 6, iclass 13, count 0 2006.257.10:00:56.09#ibcon#read 6, iclass 13, count 0 2006.257.10:00:56.09#ibcon#end of sib2, iclass 13, count 0 2006.257.10:00:56.09#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:00:56.09#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:00:56.09#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:00:56.09#ibcon#*before write, iclass 13, count 0 2006.257.10:00:56.09#ibcon#enter sib2, iclass 13, count 0 2006.257.10:00:56.09#ibcon#flushed, iclass 13, count 0 2006.257.10:00:56.09#ibcon#about to write, iclass 13, count 0 2006.257.10:00:56.09#ibcon#wrote, iclass 13, count 0 2006.257.10:00:56.09#ibcon#about to read 3, iclass 13, count 0 2006.257.10:00:56.13#ibcon#read 3, iclass 13, count 0 2006.257.10:00:56.13#ibcon#about to read 4, iclass 13, count 0 2006.257.10:00:56.13#ibcon#read 4, iclass 13, count 0 2006.257.10:00:56.13#ibcon#about to read 5, iclass 13, count 0 2006.257.10:00:56.13#ibcon#read 5, iclass 13, count 0 2006.257.10:00:56.13#ibcon#about to read 6, iclass 13, count 0 2006.257.10:00:56.13#ibcon#read 6, iclass 13, count 0 2006.257.10:00:56.13#ibcon#end of sib2, iclass 13, count 0 2006.257.10:00:56.13#ibcon#*after write, iclass 13, count 0 2006.257.10:00:56.13#ibcon#*before return 0, iclass 13, count 0 2006.257.10:00:56.13#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:56.13#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:56.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:00:56.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:00:56.13$vck44/va=7,4 2006.257.10:00:56.13#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.10:00:56.13#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.10:00:56.13#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:56.13#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:56.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:56.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:56.19#ibcon#enter wrdev, iclass 15, count 2 2006.257.10:00:56.19#ibcon#first serial, iclass 15, count 2 2006.257.10:00:56.19#ibcon#enter sib2, iclass 15, count 2 2006.257.10:00:56.19#ibcon#flushed, iclass 15, count 2 2006.257.10:00:56.19#ibcon#about to write, iclass 15, count 2 2006.257.10:00:56.19#ibcon#wrote, iclass 15, count 2 2006.257.10:00:56.19#ibcon#about to read 3, iclass 15, count 2 2006.257.10:00:56.21#ibcon#read 3, iclass 15, count 2 2006.257.10:00:56.21#ibcon#about to read 4, iclass 15, count 2 2006.257.10:00:56.21#ibcon#read 4, iclass 15, count 2 2006.257.10:00:56.21#ibcon#about to read 5, iclass 15, count 2 2006.257.10:00:56.21#ibcon#read 5, iclass 15, count 2 2006.257.10:00:56.21#ibcon#about to read 6, iclass 15, count 2 2006.257.10:00:56.21#ibcon#read 6, iclass 15, count 2 2006.257.10:00:56.21#ibcon#end of sib2, iclass 15, count 2 2006.257.10:00:56.21#ibcon#*mode == 0, iclass 15, count 2 2006.257.10:00:56.21#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.10:00:56.21#ibcon#[25=AT07-04\r\n] 2006.257.10:00:56.21#ibcon#*before write, iclass 15, count 2 2006.257.10:00:56.21#ibcon#enter sib2, iclass 15, count 2 2006.257.10:00:56.21#ibcon#flushed, iclass 15, count 2 2006.257.10:00:56.21#ibcon#about to write, iclass 15, count 2 2006.257.10:00:56.21#ibcon#wrote, iclass 15, count 2 2006.257.10:00:56.21#ibcon#about to read 3, iclass 15, count 2 2006.257.10:00:56.24#ibcon#read 3, iclass 15, count 2 2006.257.10:00:56.24#ibcon#about to read 4, iclass 15, count 2 2006.257.10:00:56.24#ibcon#read 4, iclass 15, count 2 2006.257.10:00:56.24#ibcon#about to read 5, iclass 15, count 2 2006.257.10:00:56.24#ibcon#read 5, iclass 15, count 2 2006.257.10:00:56.24#ibcon#about to read 6, iclass 15, count 2 2006.257.10:00:56.24#ibcon#read 6, iclass 15, count 2 2006.257.10:00:56.24#ibcon#end of sib2, iclass 15, count 2 2006.257.10:00:56.24#ibcon#*after write, iclass 15, count 2 2006.257.10:00:56.24#ibcon#*before return 0, iclass 15, count 2 2006.257.10:00:56.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:56.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:56.24#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.10:00:56.24#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:56.24#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:56.36#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:56.36#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:56.36#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:00:56.36#ibcon#first serial, iclass 15, count 0 2006.257.10:00:56.36#ibcon#enter sib2, iclass 15, count 0 2006.257.10:00:56.36#ibcon#flushed, iclass 15, count 0 2006.257.10:00:56.36#ibcon#about to write, iclass 15, count 0 2006.257.10:00:56.36#ibcon#wrote, iclass 15, count 0 2006.257.10:00:56.36#ibcon#about to read 3, iclass 15, count 0 2006.257.10:00:56.38#ibcon#read 3, iclass 15, count 0 2006.257.10:00:56.38#ibcon#about to read 4, iclass 15, count 0 2006.257.10:00:56.38#ibcon#read 4, iclass 15, count 0 2006.257.10:00:56.38#ibcon#about to read 5, iclass 15, count 0 2006.257.10:00:56.38#ibcon#read 5, iclass 15, count 0 2006.257.10:00:56.38#ibcon#about to read 6, iclass 15, count 0 2006.257.10:00:56.38#ibcon#read 6, iclass 15, count 0 2006.257.10:00:56.38#ibcon#end of sib2, iclass 15, count 0 2006.257.10:00:56.38#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:00:56.38#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:00:56.38#ibcon#[25=USB\r\n] 2006.257.10:00:56.38#ibcon#*before write, iclass 15, count 0 2006.257.10:00:56.38#ibcon#enter sib2, iclass 15, count 0 2006.257.10:00:56.38#ibcon#flushed, iclass 15, count 0 2006.257.10:00:56.38#ibcon#about to write, iclass 15, count 0 2006.257.10:00:56.38#ibcon#wrote, iclass 15, count 0 2006.257.10:00:56.38#ibcon#about to read 3, iclass 15, count 0 2006.257.10:00:56.41#ibcon#read 3, iclass 15, count 0 2006.257.10:00:56.41#ibcon#about to read 4, iclass 15, count 0 2006.257.10:00:56.41#ibcon#read 4, iclass 15, count 0 2006.257.10:00:56.41#ibcon#about to read 5, iclass 15, count 0 2006.257.10:00:56.41#ibcon#read 5, iclass 15, count 0 2006.257.10:00:56.41#ibcon#about to read 6, iclass 15, count 0 2006.257.10:00:56.41#ibcon#read 6, iclass 15, count 0 2006.257.10:00:56.41#ibcon#end of sib2, iclass 15, count 0 2006.257.10:00:56.41#ibcon#*after write, iclass 15, count 0 2006.257.10:00:56.41#ibcon#*before return 0, iclass 15, count 0 2006.257.10:00:56.41#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:56.41#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:56.41#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:00:56.41#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:00:56.41$vck44/valo=8,884.99 2006.257.10:00:56.41#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.10:00:56.41#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.10:00:56.41#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:56.41#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:56.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:56.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:56.41#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:00:56.41#ibcon#first serial, iclass 17, count 0 2006.257.10:00:56.41#ibcon#enter sib2, iclass 17, count 0 2006.257.10:00:56.41#ibcon#flushed, iclass 17, count 0 2006.257.10:00:56.41#ibcon#about to write, iclass 17, count 0 2006.257.10:00:56.41#ibcon#wrote, iclass 17, count 0 2006.257.10:00:56.41#ibcon#about to read 3, iclass 17, count 0 2006.257.10:00:56.43#ibcon#read 3, iclass 17, count 0 2006.257.10:00:56.43#ibcon#about to read 4, iclass 17, count 0 2006.257.10:00:56.43#ibcon#read 4, iclass 17, count 0 2006.257.10:00:56.43#ibcon#about to read 5, iclass 17, count 0 2006.257.10:00:56.43#ibcon#read 5, iclass 17, count 0 2006.257.10:00:56.43#ibcon#about to read 6, iclass 17, count 0 2006.257.10:00:56.43#ibcon#read 6, iclass 17, count 0 2006.257.10:00:56.43#ibcon#end of sib2, iclass 17, count 0 2006.257.10:00:56.43#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:00:56.43#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:00:56.43#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:00:56.43#ibcon#*before write, iclass 17, count 0 2006.257.10:00:56.43#ibcon#enter sib2, iclass 17, count 0 2006.257.10:00:56.43#ibcon#flushed, iclass 17, count 0 2006.257.10:00:56.43#ibcon#about to write, iclass 17, count 0 2006.257.10:00:56.43#ibcon#wrote, iclass 17, count 0 2006.257.10:00:56.43#ibcon#about to read 3, iclass 17, count 0 2006.257.10:00:56.47#ibcon#read 3, iclass 17, count 0 2006.257.10:00:56.47#ibcon#about to read 4, iclass 17, count 0 2006.257.10:00:56.47#ibcon#read 4, iclass 17, count 0 2006.257.10:00:56.47#ibcon#about to read 5, iclass 17, count 0 2006.257.10:00:56.47#ibcon#read 5, iclass 17, count 0 2006.257.10:00:56.47#ibcon#about to read 6, iclass 17, count 0 2006.257.10:00:56.47#ibcon#read 6, iclass 17, count 0 2006.257.10:00:56.47#ibcon#end of sib2, iclass 17, count 0 2006.257.10:00:56.47#ibcon#*after write, iclass 17, count 0 2006.257.10:00:56.47#ibcon#*before return 0, iclass 17, count 0 2006.257.10:00:56.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:56.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:56.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:00:56.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:00:56.47$vck44/va=8,4 2006.257.10:00:56.47#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.10:00:56.47#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.10:00:56.47#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:56.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:00:56.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:00:56.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:00:56.53#ibcon#enter wrdev, iclass 19, count 2 2006.257.10:00:56.53#ibcon#first serial, iclass 19, count 2 2006.257.10:00:56.53#ibcon#enter sib2, iclass 19, count 2 2006.257.10:00:56.53#ibcon#flushed, iclass 19, count 2 2006.257.10:00:56.53#ibcon#about to write, iclass 19, count 2 2006.257.10:00:56.53#ibcon#wrote, iclass 19, count 2 2006.257.10:00:56.53#ibcon#about to read 3, iclass 19, count 2 2006.257.10:00:56.55#ibcon#read 3, iclass 19, count 2 2006.257.10:00:56.55#ibcon#about to read 4, iclass 19, count 2 2006.257.10:00:56.55#ibcon#read 4, iclass 19, count 2 2006.257.10:00:56.55#ibcon#about to read 5, iclass 19, count 2 2006.257.10:00:56.55#ibcon#read 5, iclass 19, count 2 2006.257.10:00:56.55#ibcon#about to read 6, iclass 19, count 2 2006.257.10:00:56.55#ibcon#read 6, iclass 19, count 2 2006.257.10:00:56.55#ibcon#end of sib2, iclass 19, count 2 2006.257.10:00:56.55#ibcon#*mode == 0, iclass 19, count 2 2006.257.10:00:56.55#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.10:00:56.55#ibcon#[25=AT08-04\r\n] 2006.257.10:00:56.55#ibcon#*before write, iclass 19, count 2 2006.257.10:00:56.55#ibcon#enter sib2, iclass 19, count 2 2006.257.10:00:56.55#ibcon#flushed, iclass 19, count 2 2006.257.10:00:56.55#ibcon#about to write, iclass 19, count 2 2006.257.10:00:56.55#ibcon#wrote, iclass 19, count 2 2006.257.10:00:56.55#ibcon#about to read 3, iclass 19, count 2 2006.257.10:00:56.58#ibcon#read 3, iclass 19, count 2 2006.257.10:00:56.58#ibcon#about to read 4, iclass 19, count 2 2006.257.10:00:56.58#ibcon#read 4, iclass 19, count 2 2006.257.10:00:56.58#ibcon#about to read 5, iclass 19, count 2 2006.257.10:00:56.58#ibcon#read 5, iclass 19, count 2 2006.257.10:00:56.58#ibcon#about to read 6, iclass 19, count 2 2006.257.10:00:56.58#ibcon#read 6, iclass 19, count 2 2006.257.10:00:56.58#ibcon#end of sib2, iclass 19, count 2 2006.257.10:00:56.58#ibcon#*after write, iclass 19, count 2 2006.257.10:00:56.58#ibcon#*before return 0, iclass 19, count 2 2006.257.10:00:56.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:00:56.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:00:56.58#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.10:00:56.58#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:56.58#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:00:56.70#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:00:56.70#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:00:56.70#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:00:56.70#ibcon#first serial, iclass 19, count 0 2006.257.10:00:56.70#ibcon#enter sib2, iclass 19, count 0 2006.257.10:00:56.70#ibcon#flushed, iclass 19, count 0 2006.257.10:00:56.70#ibcon#about to write, iclass 19, count 0 2006.257.10:00:56.70#ibcon#wrote, iclass 19, count 0 2006.257.10:00:56.70#ibcon#about to read 3, iclass 19, count 0 2006.257.10:00:56.72#ibcon#read 3, iclass 19, count 0 2006.257.10:00:56.72#ibcon#about to read 4, iclass 19, count 0 2006.257.10:00:56.72#ibcon#read 4, iclass 19, count 0 2006.257.10:00:56.72#ibcon#about to read 5, iclass 19, count 0 2006.257.10:00:56.72#ibcon#read 5, iclass 19, count 0 2006.257.10:00:56.72#ibcon#about to read 6, iclass 19, count 0 2006.257.10:00:56.72#ibcon#read 6, iclass 19, count 0 2006.257.10:00:56.72#ibcon#end of sib2, iclass 19, count 0 2006.257.10:00:56.72#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:00:56.72#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:00:56.72#ibcon#[25=USB\r\n] 2006.257.10:00:56.72#ibcon#*before write, iclass 19, count 0 2006.257.10:00:56.72#ibcon#enter sib2, iclass 19, count 0 2006.257.10:00:56.72#ibcon#flushed, iclass 19, count 0 2006.257.10:00:56.72#ibcon#about to write, iclass 19, count 0 2006.257.10:00:56.72#ibcon#wrote, iclass 19, count 0 2006.257.10:00:56.72#ibcon#about to read 3, iclass 19, count 0 2006.257.10:00:56.75#ibcon#read 3, iclass 19, count 0 2006.257.10:00:56.75#ibcon#about to read 4, iclass 19, count 0 2006.257.10:00:56.75#ibcon#read 4, iclass 19, count 0 2006.257.10:00:56.75#ibcon#about to read 5, iclass 19, count 0 2006.257.10:00:56.75#ibcon#read 5, iclass 19, count 0 2006.257.10:00:56.75#ibcon#about to read 6, iclass 19, count 0 2006.257.10:00:56.75#ibcon#read 6, iclass 19, count 0 2006.257.10:00:56.75#ibcon#end of sib2, iclass 19, count 0 2006.257.10:00:56.75#ibcon#*after write, iclass 19, count 0 2006.257.10:00:56.75#ibcon#*before return 0, iclass 19, count 0 2006.257.10:00:56.75#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:00:56.75#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:00:56.75#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:00:56.75#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:00:56.75$vck44/vblo=1,629.99 2006.257.10:00:56.75#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.10:00:56.75#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.10:00:56.75#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:56.75#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:00:56.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:00:56.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:00:56.75#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:00:56.75#ibcon#first serial, iclass 21, count 0 2006.257.10:00:56.75#ibcon#enter sib2, iclass 21, count 0 2006.257.10:00:56.75#ibcon#flushed, iclass 21, count 0 2006.257.10:00:56.75#ibcon#about to write, iclass 21, count 0 2006.257.10:00:56.75#ibcon#wrote, iclass 21, count 0 2006.257.10:00:56.75#ibcon#about to read 3, iclass 21, count 0 2006.257.10:00:56.77#ibcon#read 3, iclass 21, count 0 2006.257.10:00:56.77#ibcon#about to read 4, iclass 21, count 0 2006.257.10:00:56.77#ibcon#read 4, iclass 21, count 0 2006.257.10:00:56.77#ibcon#about to read 5, iclass 21, count 0 2006.257.10:00:56.77#ibcon#read 5, iclass 21, count 0 2006.257.10:00:56.77#ibcon#about to read 6, iclass 21, count 0 2006.257.10:00:56.77#ibcon#read 6, iclass 21, count 0 2006.257.10:00:56.77#ibcon#end of sib2, iclass 21, count 0 2006.257.10:00:56.77#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:00:56.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:00:56.77#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:00:56.77#ibcon#*before write, iclass 21, count 0 2006.257.10:00:56.77#ibcon#enter sib2, iclass 21, count 0 2006.257.10:00:56.77#ibcon#flushed, iclass 21, count 0 2006.257.10:00:56.77#ibcon#about to write, iclass 21, count 0 2006.257.10:00:56.77#ibcon#wrote, iclass 21, count 0 2006.257.10:00:56.77#ibcon#about to read 3, iclass 21, count 0 2006.257.10:00:56.81#ibcon#read 3, iclass 21, count 0 2006.257.10:00:56.81#ibcon#about to read 4, iclass 21, count 0 2006.257.10:00:56.81#ibcon#read 4, iclass 21, count 0 2006.257.10:00:56.81#ibcon#about to read 5, iclass 21, count 0 2006.257.10:00:56.81#ibcon#read 5, iclass 21, count 0 2006.257.10:00:56.81#ibcon#about to read 6, iclass 21, count 0 2006.257.10:00:56.81#ibcon#read 6, iclass 21, count 0 2006.257.10:00:56.81#ibcon#end of sib2, iclass 21, count 0 2006.257.10:00:56.81#ibcon#*after write, iclass 21, count 0 2006.257.10:00:56.81#ibcon#*before return 0, iclass 21, count 0 2006.257.10:00:56.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:00:56.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:00:56.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:00:56.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:00:56.81$vck44/vb=1,4 2006.257.10:00:56.81#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.10:00:56.81#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.10:00:56.81#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:56.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:00:56.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:00:56.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:00:56.81#ibcon#enter wrdev, iclass 23, count 2 2006.257.10:00:56.81#ibcon#first serial, iclass 23, count 2 2006.257.10:00:56.81#ibcon#enter sib2, iclass 23, count 2 2006.257.10:00:56.81#ibcon#flushed, iclass 23, count 2 2006.257.10:00:56.81#ibcon#about to write, iclass 23, count 2 2006.257.10:00:56.81#ibcon#wrote, iclass 23, count 2 2006.257.10:00:56.81#ibcon#about to read 3, iclass 23, count 2 2006.257.10:00:56.83#ibcon#read 3, iclass 23, count 2 2006.257.10:00:56.83#ibcon#about to read 4, iclass 23, count 2 2006.257.10:00:56.83#ibcon#read 4, iclass 23, count 2 2006.257.10:00:56.83#ibcon#about to read 5, iclass 23, count 2 2006.257.10:00:56.83#ibcon#read 5, iclass 23, count 2 2006.257.10:00:56.83#ibcon#about to read 6, iclass 23, count 2 2006.257.10:00:56.83#ibcon#read 6, iclass 23, count 2 2006.257.10:00:56.83#ibcon#end of sib2, iclass 23, count 2 2006.257.10:00:56.83#ibcon#*mode == 0, iclass 23, count 2 2006.257.10:00:56.83#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.10:00:56.83#ibcon#[27=AT01-04\r\n] 2006.257.10:00:56.83#ibcon#*before write, iclass 23, count 2 2006.257.10:00:56.83#ibcon#enter sib2, iclass 23, count 2 2006.257.10:00:56.83#ibcon#flushed, iclass 23, count 2 2006.257.10:00:56.83#ibcon#about to write, iclass 23, count 2 2006.257.10:00:56.83#ibcon#wrote, iclass 23, count 2 2006.257.10:00:56.83#ibcon#about to read 3, iclass 23, count 2 2006.257.10:00:56.86#ibcon#read 3, iclass 23, count 2 2006.257.10:00:56.86#ibcon#about to read 4, iclass 23, count 2 2006.257.10:00:56.86#ibcon#read 4, iclass 23, count 2 2006.257.10:00:56.86#ibcon#about to read 5, iclass 23, count 2 2006.257.10:00:56.86#ibcon#read 5, iclass 23, count 2 2006.257.10:00:56.86#ibcon#about to read 6, iclass 23, count 2 2006.257.10:00:56.86#ibcon#read 6, iclass 23, count 2 2006.257.10:00:56.86#ibcon#end of sib2, iclass 23, count 2 2006.257.10:00:56.86#ibcon#*after write, iclass 23, count 2 2006.257.10:00:56.86#ibcon#*before return 0, iclass 23, count 2 2006.257.10:00:56.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:00:56.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:00:56.86#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.10:00:56.86#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:56.86#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:00:56.98#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:00:56.98#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:00:56.98#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:00:56.98#ibcon#first serial, iclass 23, count 0 2006.257.10:00:56.98#ibcon#enter sib2, iclass 23, count 0 2006.257.10:00:56.98#ibcon#flushed, iclass 23, count 0 2006.257.10:00:56.98#ibcon#about to write, iclass 23, count 0 2006.257.10:00:56.98#ibcon#wrote, iclass 23, count 0 2006.257.10:00:56.98#ibcon#about to read 3, iclass 23, count 0 2006.257.10:00:57.00#ibcon#read 3, iclass 23, count 0 2006.257.10:00:57.00#ibcon#about to read 4, iclass 23, count 0 2006.257.10:00:57.00#ibcon#read 4, iclass 23, count 0 2006.257.10:00:57.00#ibcon#about to read 5, iclass 23, count 0 2006.257.10:00:57.00#ibcon#read 5, iclass 23, count 0 2006.257.10:00:57.00#ibcon#about to read 6, iclass 23, count 0 2006.257.10:00:57.00#ibcon#read 6, iclass 23, count 0 2006.257.10:00:57.00#ibcon#end of sib2, iclass 23, count 0 2006.257.10:00:57.00#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:00:57.00#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:00:57.00#ibcon#[27=USB\r\n] 2006.257.10:00:57.00#ibcon#*before write, iclass 23, count 0 2006.257.10:00:57.00#ibcon#enter sib2, iclass 23, count 0 2006.257.10:00:57.00#ibcon#flushed, iclass 23, count 0 2006.257.10:00:57.00#ibcon#about to write, iclass 23, count 0 2006.257.10:00:57.00#ibcon#wrote, iclass 23, count 0 2006.257.10:00:57.00#ibcon#about to read 3, iclass 23, count 0 2006.257.10:00:57.03#ibcon#read 3, iclass 23, count 0 2006.257.10:00:57.03#ibcon#about to read 4, iclass 23, count 0 2006.257.10:00:57.03#ibcon#read 4, iclass 23, count 0 2006.257.10:00:57.03#ibcon#about to read 5, iclass 23, count 0 2006.257.10:00:57.03#ibcon#read 5, iclass 23, count 0 2006.257.10:00:57.03#ibcon#about to read 6, iclass 23, count 0 2006.257.10:00:57.03#ibcon#read 6, iclass 23, count 0 2006.257.10:00:57.03#ibcon#end of sib2, iclass 23, count 0 2006.257.10:00:57.03#ibcon#*after write, iclass 23, count 0 2006.257.10:00:57.03#ibcon#*before return 0, iclass 23, count 0 2006.257.10:00:57.03#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:00:57.03#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:00:57.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:00:57.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:00:57.03$vck44/vblo=2,634.99 2006.257.10:00:57.03#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.10:00:57.03#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.10:00:57.03#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:57.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:57.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:57.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:57.03#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:00:57.03#ibcon#first serial, iclass 25, count 0 2006.257.10:00:57.03#ibcon#enter sib2, iclass 25, count 0 2006.257.10:00:57.03#ibcon#flushed, iclass 25, count 0 2006.257.10:00:57.03#ibcon#about to write, iclass 25, count 0 2006.257.10:00:57.03#ibcon#wrote, iclass 25, count 0 2006.257.10:00:57.03#ibcon#about to read 3, iclass 25, count 0 2006.257.10:00:57.05#ibcon#read 3, iclass 25, count 0 2006.257.10:00:57.05#ibcon#about to read 4, iclass 25, count 0 2006.257.10:00:57.05#ibcon#read 4, iclass 25, count 0 2006.257.10:00:57.05#ibcon#about to read 5, iclass 25, count 0 2006.257.10:00:57.05#ibcon#read 5, iclass 25, count 0 2006.257.10:00:57.05#ibcon#about to read 6, iclass 25, count 0 2006.257.10:00:57.05#ibcon#read 6, iclass 25, count 0 2006.257.10:00:57.05#ibcon#end of sib2, iclass 25, count 0 2006.257.10:00:57.05#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:00:57.05#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:00:57.05#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:00:57.05#ibcon#*before write, iclass 25, count 0 2006.257.10:00:57.05#ibcon#enter sib2, iclass 25, count 0 2006.257.10:00:57.05#ibcon#flushed, iclass 25, count 0 2006.257.10:00:57.05#ibcon#about to write, iclass 25, count 0 2006.257.10:00:57.05#ibcon#wrote, iclass 25, count 0 2006.257.10:00:57.05#ibcon#about to read 3, iclass 25, count 0 2006.257.10:00:57.09#ibcon#read 3, iclass 25, count 0 2006.257.10:00:57.09#ibcon#about to read 4, iclass 25, count 0 2006.257.10:00:57.09#ibcon#read 4, iclass 25, count 0 2006.257.10:00:57.09#ibcon#about to read 5, iclass 25, count 0 2006.257.10:00:57.09#ibcon#read 5, iclass 25, count 0 2006.257.10:00:57.09#ibcon#about to read 6, iclass 25, count 0 2006.257.10:00:57.09#ibcon#read 6, iclass 25, count 0 2006.257.10:00:57.09#ibcon#end of sib2, iclass 25, count 0 2006.257.10:00:57.09#ibcon#*after write, iclass 25, count 0 2006.257.10:00:57.09#ibcon#*before return 0, iclass 25, count 0 2006.257.10:00:57.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:57.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:00:57.09#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:00:57.09#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:00:57.09$vck44/vb=2,5 2006.257.10:00:57.09#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.10:00:57.09#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.10:00:57.09#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:57.09#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:57.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:57.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:57.15#ibcon#enter wrdev, iclass 27, count 2 2006.257.10:00:57.15#ibcon#first serial, iclass 27, count 2 2006.257.10:00:57.15#ibcon#enter sib2, iclass 27, count 2 2006.257.10:00:57.15#ibcon#flushed, iclass 27, count 2 2006.257.10:00:57.15#ibcon#about to write, iclass 27, count 2 2006.257.10:00:57.15#ibcon#wrote, iclass 27, count 2 2006.257.10:00:57.15#ibcon#about to read 3, iclass 27, count 2 2006.257.10:00:57.17#ibcon#read 3, iclass 27, count 2 2006.257.10:00:57.17#ibcon#about to read 4, iclass 27, count 2 2006.257.10:00:57.17#ibcon#read 4, iclass 27, count 2 2006.257.10:00:57.17#ibcon#about to read 5, iclass 27, count 2 2006.257.10:00:57.17#ibcon#read 5, iclass 27, count 2 2006.257.10:00:57.17#ibcon#about to read 6, iclass 27, count 2 2006.257.10:00:57.17#ibcon#read 6, iclass 27, count 2 2006.257.10:00:57.17#ibcon#end of sib2, iclass 27, count 2 2006.257.10:00:57.17#ibcon#*mode == 0, iclass 27, count 2 2006.257.10:00:57.17#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.10:00:57.17#ibcon#[27=AT02-05\r\n] 2006.257.10:00:57.17#ibcon#*before write, iclass 27, count 2 2006.257.10:00:57.17#ibcon#enter sib2, iclass 27, count 2 2006.257.10:00:57.17#ibcon#flushed, iclass 27, count 2 2006.257.10:00:57.17#ibcon#about to write, iclass 27, count 2 2006.257.10:00:57.17#ibcon#wrote, iclass 27, count 2 2006.257.10:00:57.17#ibcon#about to read 3, iclass 27, count 2 2006.257.10:00:57.20#ibcon#read 3, iclass 27, count 2 2006.257.10:00:57.20#ibcon#about to read 4, iclass 27, count 2 2006.257.10:00:57.20#ibcon#read 4, iclass 27, count 2 2006.257.10:00:57.20#ibcon#about to read 5, iclass 27, count 2 2006.257.10:00:57.20#ibcon#read 5, iclass 27, count 2 2006.257.10:00:57.20#ibcon#about to read 6, iclass 27, count 2 2006.257.10:00:57.20#ibcon#read 6, iclass 27, count 2 2006.257.10:00:57.20#ibcon#end of sib2, iclass 27, count 2 2006.257.10:00:57.20#ibcon#*after write, iclass 27, count 2 2006.257.10:00:57.20#ibcon#*before return 0, iclass 27, count 2 2006.257.10:00:57.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:57.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:00:57.20#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.10:00:57.20#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:57.20#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:57.32#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:57.32#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:57.32#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:00:57.32#ibcon#first serial, iclass 27, count 0 2006.257.10:00:57.32#ibcon#enter sib2, iclass 27, count 0 2006.257.10:00:57.32#ibcon#flushed, iclass 27, count 0 2006.257.10:00:57.32#ibcon#about to write, iclass 27, count 0 2006.257.10:00:57.32#ibcon#wrote, iclass 27, count 0 2006.257.10:00:57.32#ibcon#about to read 3, iclass 27, count 0 2006.257.10:00:57.34#ibcon#read 3, iclass 27, count 0 2006.257.10:00:57.34#ibcon#about to read 4, iclass 27, count 0 2006.257.10:00:57.34#ibcon#read 4, iclass 27, count 0 2006.257.10:00:57.34#ibcon#about to read 5, iclass 27, count 0 2006.257.10:00:57.34#ibcon#read 5, iclass 27, count 0 2006.257.10:00:57.34#ibcon#about to read 6, iclass 27, count 0 2006.257.10:00:57.34#ibcon#read 6, iclass 27, count 0 2006.257.10:00:57.34#ibcon#end of sib2, iclass 27, count 0 2006.257.10:00:57.34#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:00:57.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:00:57.34#ibcon#[27=USB\r\n] 2006.257.10:00:57.34#ibcon#*before write, iclass 27, count 0 2006.257.10:00:57.34#ibcon#enter sib2, iclass 27, count 0 2006.257.10:00:57.34#ibcon#flushed, iclass 27, count 0 2006.257.10:00:57.34#ibcon#about to write, iclass 27, count 0 2006.257.10:00:57.34#ibcon#wrote, iclass 27, count 0 2006.257.10:00:57.34#ibcon#about to read 3, iclass 27, count 0 2006.257.10:00:57.37#ibcon#read 3, iclass 27, count 0 2006.257.10:00:57.37#ibcon#about to read 4, iclass 27, count 0 2006.257.10:00:57.37#ibcon#read 4, iclass 27, count 0 2006.257.10:00:57.37#ibcon#about to read 5, iclass 27, count 0 2006.257.10:00:57.37#ibcon#read 5, iclass 27, count 0 2006.257.10:00:57.37#ibcon#about to read 6, iclass 27, count 0 2006.257.10:00:57.37#ibcon#read 6, iclass 27, count 0 2006.257.10:00:57.37#ibcon#end of sib2, iclass 27, count 0 2006.257.10:00:57.37#ibcon#*after write, iclass 27, count 0 2006.257.10:00:57.37#ibcon#*before return 0, iclass 27, count 0 2006.257.10:00:57.37#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:57.37#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:00:57.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:00:57.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:00:57.37$vck44/vblo=3,649.99 2006.257.10:00:57.37#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.10:00:57.37#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.10:00:57.37#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:57.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:57.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:57.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:57.37#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:00:57.37#ibcon#first serial, iclass 29, count 0 2006.257.10:00:57.37#ibcon#enter sib2, iclass 29, count 0 2006.257.10:00:57.37#ibcon#flushed, iclass 29, count 0 2006.257.10:00:57.37#ibcon#about to write, iclass 29, count 0 2006.257.10:00:57.37#ibcon#wrote, iclass 29, count 0 2006.257.10:00:57.37#ibcon#about to read 3, iclass 29, count 0 2006.257.10:00:57.39#ibcon#read 3, iclass 29, count 0 2006.257.10:00:57.39#ibcon#about to read 4, iclass 29, count 0 2006.257.10:00:57.39#ibcon#read 4, iclass 29, count 0 2006.257.10:00:57.39#ibcon#about to read 5, iclass 29, count 0 2006.257.10:00:57.39#ibcon#read 5, iclass 29, count 0 2006.257.10:00:57.39#ibcon#about to read 6, iclass 29, count 0 2006.257.10:00:57.39#ibcon#read 6, iclass 29, count 0 2006.257.10:00:57.39#ibcon#end of sib2, iclass 29, count 0 2006.257.10:00:57.39#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:00:57.39#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:00:57.39#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:00:57.39#ibcon#*before write, iclass 29, count 0 2006.257.10:00:57.39#ibcon#enter sib2, iclass 29, count 0 2006.257.10:00:57.39#ibcon#flushed, iclass 29, count 0 2006.257.10:00:57.39#ibcon#about to write, iclass 29, count 0 2006.257.10:00:57.39#ibcon#wrote, iclass 29, count 0 2006.257.10:00:57.39#ibcon#about to read 3, iclass 29, count 0 2006.257.10:00:57.43#ibcon#read 3, iclass 29, count 0 2006.257.10:00:57.43#ibcon#about to read 4, iclass 29, count 0 2006.257.10:00:57.43#ibcon#read 4, iclass 29, count 0 2006.257.10:00:57.43#ibcon#about to read 5, iclass 29, count 0 2006.257.10:00:57.43#ibcon#read 5, iclass 29, count 0 2006.257.10:00:57.43#ibcon#about to read 6, iclass 29, count 0 2006.257.10:00:57.43#ibcon#read 6, iclass 29, count 0 2006.257.10:00:57.43#ibcon#end of sib2, iclass 29, count 0 2006.257.10:00:57.43#ibcon#*after write, iclass 29, count 0 2006.257.10:00:57.43#ibcon#*before return 0, iclass 29, count 0 2006.257.10:00:57.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:57.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:00:57.43#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:00:57.43#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:00:57.43$vck44/vb=3,4 2006.257.10:00:57.43#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.10:00:57.43#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.10:00:57.43#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:57.43#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:57.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:57.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:57.49#ibcon#enter wrdev, iclass 31, count 2 2006.257.10:00:57.49#ibcon#first serial, iclass 31, count 2 2006.257.10:00:57.49#ibcon#enter sib2, iclass 31, count 2 2006.257.10:00:57.49#ibcon#flushed, iclass 31, count 2 2006.257.10:00:57.49#ibcon#about to write, iclass 31, count 2 2006.257.10:00:57.49#ibcon#wrote, iclass 31, count 2 2006.257.10:00:57.49#ibcon#about to read 3, iclass 31, count 2 2006.257.10:00:57.51#ibcon#read 3, iclass 31, count 2 2006.257.10:00:57.51#ibcon#about to read 4, iclass 31, count 2 2006.257.10:00:57.51#ibcon#read 4, iclass 31, count 2 2006.257.10:00:57.51#ibcon#about to read 5, iclass 31, count 2 2006.257.10:00:57.51#ibcon#read 5, iclass 31, count 2 2006.257.10:00:57.51#ibcon#about to read 6, iclass 31, count 2 2006.257.10:00:57.51#ibcon#read 6, iclass 31, count 2 2006.257.10:00:57.51#ibcon#end of sib2, iclass 31, count 2 2006.257.10:00:57.51#ibcon#*mode == 0, iclass 31, count 2 2006.257.10:00:57.51#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.10:00:57.51#ibcon#[27=AT03-04\r\n] 2006.257.10:00:57.51#ibcon#*before write, iclass 31, count 2 2006.257.10:00:57.51#ibcon#enter sib2, iclass 31, count 2 2006.257.10:00:57.51#ibcon#flushed, iclass 31, count 2 2006.257.10:00:57.51#ibcon#about to write, iclass 31, count 2 2006.257.10:00:57.51#ibcon#wrote, iclass 31, count 2 2006.257.10:00:57.51#ibcon#about to read 3, iclass 31, count 2 2006.257.10:00:57.54#ibcon#read 3, iclass 31, count 2 2006.257.10:00:57.54#ibcon#about to read 4, iclass 31, count 2 2006.257.10:00:57.54#ibcon#read 4, iclass 31, count 2 2006.257.10:00:57.54#ibcon#about to read 5, iclass 31, count 2 2006.257.10:00:57.54#ibcon#read 5, iclass 31, count 2 2006.257.10:00:57.54#ibcon#about to read 6, iclass 31, count 2 2006.257.10:00:57.54#ibcon#read 6, iclass 31, count 2 2006.257.10:00:57.54#ibcon#end of sib2, iclass 31, count 2 2006.257.10:00:57.54#ibcon#*after write, iclass 31, count 2 2006.257.10:00:57.54#ibcon#*before return 0, iclass 31, count 2 2006.257.10:00:57.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:57.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:00:57.54#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.10:00:57.54#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:57.54#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:57.66#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:57.66#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:57.66#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:00:57.66#ibcon#first serial, iclass 31, count 0 2006.257.10:00:57.66#ibcon#enter sib2, iclass 31, count 0 2006.257.10:00:57.66#ibcon#flushed, iclass 31, count 0 2006.257.10:00:57.66#ibcon#about to write, iclass 31, count 0 2006.257.10:00:57.66#ibcon#wrote, iclass 31, count 0 2006.257.10:00:57.66#ibcon#about to read 3, iclass 31, count 0 2006.257.10:00:57.68#ibcon#read 3, iclass 31, count 0 2006.257.10:00:57.68#ibcon#about to read 4, iclass 31, count 0 2006.257.10:00:57.68#ibcon#read 4, iclass 31, count 0 2006.257.10:00:57.68#ibcon#about to read 5, iclass 31, count 0 2006.257.10:00:57.68#ibcon#read 5, iclass 31, count 0 2006.257.10:00:57.68#ibcon#about to read 6, iclass 31, count 0 2006.257.10:00:57.68#ibcon#read 6, iclass 31, count 0 2006.257.10:00:57.68#ibcon#end of sib2, iclass 31, count 0 2006.257.10:00:57.68#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:00:57.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:00:57.68#ibcon#[27=USB\r\n] 2006.257.10:00:57.68#ibcon#*before write, iclass 31, count 0 2006.257.10:00:57.68#ibcon#enter sib2, iclass 31, count 0 2006.257.10:00:57.68#ibcon#flushed, iclass 31, count 0 2006.257.10:00:57.68#ibcon#about to write, iclass 31, count 0 2006.257.10:00:57.68#ibcon#wrote, iclass 31, count 0 2006.257.10:00:57.68#ibcon#about to read 3, iclass 31, count 0 2006.257.10:00:57.71#ibcon#read 3, iclass 31, count 0 2006.257.10:00:57.71#ibcon#about to read 4, iclass 31, count 0 2006.257.10:00:57.71#ibcon#read 4, iclass 31, count 0 2006.257.10:00:57.71#ibcon#about to read 5, iclass 31, count 0 2006.257.10:00:57.71#ibcon#read 5, iclass 31, count 0 2006.257.10:00:57.71#ibcon#about to read 6, iclass 31, count 0 2006.257.10:00:57.71#ibcon#read 6, iclass 31, count 0 2006.257.10:00:57.71#ibcon#end of sib2, iclass 31, count 0 2006.257.10:00:57.71#ibcon#*after write, iclass 31, count 0 2006.257.10:00:57.71#ibcon#*before return 0, iclass 31, count 0 2006.257.10:00:57.71#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:57.71#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:00:57.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:00:57.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:00:57.71$vck44/vblo=4,679.99 2006.257.10:00:57.71#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.10:00:57.71#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.10:00:57.71#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:57.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:57.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:57.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:57.71#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:00:57.71#ibcon#first serial, iclass 33, count 0 2006.257.10:00:57.71#ibcon#enter sib2, iclass 33, count 0 2006.257.10:00:57.71#ibcon#flushed, iclass 33, count 0 2006.257.10:00:57.71#ibcon#about to write, iclass 33, count 0 2006.257.10:00:57.71#ibcon#wrote, iclass 33, count 0 2006.257.10:00:57.71#ibcon#about to read 3, iclass 33, count 0 2006.257.10:00:57.73#ibcon#read 3, iclass 33, count 0 2006.257.10:00:57.73#ibcon#about to read 4, iclass 33, count 0 2006.257.10:00:57.73#ibcon#read 4, iclass 33, count 0 2006.257.10:00:57.73#ibcon#about to read 5, iclass 33, count 0 2006.257.10:00:57.73#ibcon#read 5, iclass 33, count 0 2006.257.10:00:57.73#ibcon#about to read 6, iclass 33, count 0 2006.257.10:00:57.73#ibcon#read 6, iclass 33, count 0 2006.257.10:00:57.73#ibcon#end of sib2, iclass 33, count 0 2006.257.10:00:57.73#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:00:57.73#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:00:57.73#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:00:57.73#ibcon#*before write, iclass 33, count 0 2006.257.10:00:57.73#ibcon#enter sib2, iclass 33, count 0 2006.257.10:00:57.73#ibcon#flushed, iclass 33, count 0 2006.257.10:00:57.73#ibcon#about to write, iclass 33, count 0 2006.257.10:00:57.73#ibcon#wrote, iclass 33, count 0 2006.257.10:00:57.73#ibcon#about to read 3, iclass 33, count 0 2006.257.10:00:57.77#ibcon#read 3, iclass 33, count 0 2006.257.10:00:57.77#ibcon#about to read 4, iclass 33, count 0 2006.257.10:00:57.77#ibcon#read 4, iclass 33, count 0 2006.257.10:00:57.77#ibcon#about to read 5, iclass 33, count 0 2006.257.10:00:57.77#ibcon#read 5, iclass 33, count 0 2006.257.10:00:57.77#ibcon#about to read 6, iclass 33, count 0 2006.257.10:00:57.77#ibcon#read 6, iclass 33, count 0 2006.257.10:00:57.77#ibcon#end of sib2, iclass 33, count 0 2006.257.10:00:57.77#ibcon#*after write, iclass 33, count 0 2006.257.10:00:57.77#ibcon#*before return 0, iclass 33, count 0 2006.257.10:00:57.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:57.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:00:57.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:00:57.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:00:57.77$vck44/vb=4,5 2006.257.10:00:57.77#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.10:00:57.77#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.10:00:57.77#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:57.77#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:57.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:57.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:57.83#ibcon#enter wrdev, iclass 35, count 2 2006.257.10:00:57.83#ibcon#first serial, iclass 35, count 2 2006.257.10:00:57.83#ibcon#enter sib2, iclass 35, count 2 2006.257.10:00:57.83#ibcon#flushed, iclass 35, count 2 2006.257.10:00:57.83#ibcon#about to write, iclass 35, count 2 2006.257.10:00:57.83#ibcon#wrote, iclass 35, count 2 2006.257.10:00:57.83#ibcon#about to read 3, iclass 35, count 2 2006.257.10:00:57.85#ibcon#read 3, iclass 35, count 2 2006.257.10:00:57.85#ibcon#about to read 4, iclass 35, count 2 2006.257.10:00:57.85#ibcon#read 4, iclass 35, count 2 2006.257.10:00:57.85#ibcon#about to read 5, iclass 35, count 2 2006.257.10:00:57.85#ibcon#read 5, iclass 35, count 2 2006.257.10:00:57.85#ibcon#about to read 6, iclass 35, count 2 2006.257.10:00:57.85#ibcon#read 6, iclass 35, count 2 2006.257.10:00:57.85#ibcon#end of sib2, iclass 35, count 2 2006.257.10:00:57.85#ibcon#*mode == 0, iclass 35, count 2 2006.257.10:00:57.85#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.10:00:57.85#ibcon#[27=AT04-05\r\n] 2006.257.10:00:57.85#ibcon#*before write, iclass 35, count 2 2006.257.10:00:57.85#ibcon#enter sib2, iclass 35, count 2 2006.257.10:00:57.85#ibcon#flushed, iclass 35, count 2 2006.257.10:00:57.85#ibcon#about to write, iclass 35, count 2 2006.257.10:00:57.85#ibcon#wrote, iclass 35, count 2 2006.257.10:00:57.85#ibcon#about to read 3, iclass 35, count 2 2006.257.10:00:57.88#ibcon#read 3, iclass 35, count 2 2006.257.10:00:57.88#ibcon#about to read 4, iclass 35, count 2 2006.257.10:00:57.88#ibcon#read 4, iclass 35, count 2 2006.257.10:00:57.88#ibcon#about to read 5, iclass 35, count 2 2006.257.10:00:57.88#ibcon#read 5, iclass 35, count 2 2006.257.10:00:57.88#ibcon#about to read 6, iclass 35, count 2 2006.257.10:00:57.88#ibcon#read 6, iclass 35, count 2 2006.257.10:00:57.88#ibcon#end of sib2, iclass 35, count 2 2006.257.10:00:57.88#ibcon#*after write, iclass 35, count 2 2006.257.10:00:57.88#ibcon#*before return 0, iclass 35, count 2 2006.257.10:00:57.88#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:57.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:00:57.88#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.10:00:57.88#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:57.88#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:58.00#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:58.00#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:58.00#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:00:58.00#ibcon#first serial, iclass 35, count 0 2006.257.10:00:58.00#ibcon#enter sib2, iclass 35, count 0 2006.257.10:00:58.00#ibcon#flushed, iclass 35, count 0 2006.257.10:00:58.00#ibcon#about to write, iclass 35, count 0 2006.257.10:00:58.00#ibcon#wrote, iclass 35, count 0 2006.257.10:00:58.00#ibcon#about to read 3, iclass 35, count 0 2006.257.10:00:58.02#ibcon#read 3, iclass 35, count 0 2006.257.10:00:58.02#ibcon#about to read 4, iclass 35, count 0 2006.257.10:00:58.02#ibcon#read 4, iclass 35, count 0 2006.257.10:00:58.02#ibcon#about to read 5, iclass 35, count 0 2006.257.10:00:58.02#ibcon#read 5, iclass 35, count 0 2006.257.10:00:58.02#ibcon#about to read 6, iclass 35, count 0 2006.257.10:00:58.02#ibcon#read 6, iclass 35, count 0 2006.257.10:00:58.02#ibcon#end of sib2, iclass 35, count 0 2006.257.10:00:58.02#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:00:58.02#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:00:58.02#ibcon#[27=USB\r\n] 2006.257.10:00:58.02#ibcon#*before write, iclass 35, count 0 2006.257.10:00:58.02#ibcon#enter sib2, iclass 35, count 0 2006.257.10:00:58.02#ibcon#flushed, iclass 35, count 0 2006.257.10:00:58.02#ibcon#about to write, iclass 35, count 0 2006.257.10:00:58.02#ibcon#wrote, iclass 35, count 0 2006.257.10:00:58.02#ibcon#about to read 3, iclass 35, count 0 2006.257.10:00:58.05#ibcon#read 3, iclass 35, count 0 2006.257.10:00:58.05#ibcon#about to read 4, iclass 35, count 0 2006.257.10:00:58.05#ibcon#read 4, iclass 35, count 0 2006.257.10:00:58.05#ibcon#about to read 5, iclass 35, count 0 2006.257.10:00:58.05#ibcon#read 5, iclass 35, count 0 2006.257.10:00:58.05#ibcon#about to read 6, iclass 35, count 0 2006.257.10:00:58.05#ibcon#read 6, iclass 35, count 0 2006.257.10:00:58.05#ibcon#end of sib2, iclass 35, count 0 2006.257.10:00:58.05#ibcon#*after write, iclass 35, count 0 2006.257.10:00:58.05#ibcon#*before return 0, iclass 35, count 0 2006.257.10:00:58.05#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:58.05#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:00:58.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:00:58.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:00:58.05$vck44/vblo=5,709.99 2006.257.10:00:58.05#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.10:00:58.05#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.10:00:58.05#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:58.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:58.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:58.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:58.05#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:00:58.05#ibcon#first serial, iclass 37, count 0 2006.257.10:00:58.05#ibcon#enter sib2, iclass 37, count 0 2006.257.10:00:58.05#ibcon#flushed, iclass 37, count 0 2006.257.10:00:58.05#ibcon#about to write, iclass 37, count 0 2006.257.10:00:58.05#ibcon#wrote, iclass 37, count 0 2006.257.10:00:58.05#ibcon#about to read 3, iclass 37, count 0 2006.257.10:00:58.07#ibcon#read 3, iclass 37, count 0 2006.257.10:00:58.07#ibcon#about to read 4, iclass 37, count 0 2006.257.10:00:58.07#ibcon#read 4, iclass 37, count 0 2006.257.10:00:58.07#ibcon#about to read 5, iclass 37, count 0 2006.257.10:00:58.07#ibcon#read 5, iclass 37, count 0 2006.257.10:00:58.07#ibcon#about to read 6, iclass 37, count 0 2006.257.10:00:58.07#ibcon#read 6, iclass 37, count 0 2006.257.10:00:58.07#ibcon#end of sib2, iclass 37, count 0 2006.257.10:00:58.07#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:00:58.07#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:00:58.07#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:00:58.07#ibcon#*before write, iclass 37, count 0 2006.257.10:00:58.07#ibcon#enter sib2, iclass 37, count 0 2006.257.10:00:58.07#ibcon#flushed, iclass 37, count 0 2006.257.10:00:58.07#ibcon#about to write, iclass 37, count 0 2006.257.10:00:58.07#ibcon#wrote, iclass 37, count 0 2006.257.10:00:58.07#ibcon#about to read 3, iclass 37, count 0 2006.257.10:00:58.11#ibcon#read 3, iclass 37, count 0 2006.257.10:00:58.11#ibcon#about to read 4, iclass 37, count 0 2006.257.10:00:58.11#ibcon#read 4, iclass 37, count 0 2006.257.10:00:58.11#ibcon#about to read 5, iclass 37, count 0 2006.257.10:00:58.11#ibcon#read 5, iclass 37, count 0 2006.257.10:00:58.11#ibcon#about to read 6, iclass 37, count 0 2006.257.10:00:58.11#ibcon#read 6, iclass 37, count 0 2006.257.10:00:58.11#ibcon#end of sib2, iclass 37, count 0 2006.257.10:00:58.11#ibcon#*after write, iclass 37, count 0 2006.257.10:00:58.11#ibcon#*before return 0, iclass 37, count 0 2006.257.10:00:58.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:58.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:00:58.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:00:58.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:00:58.11$vck44/vb=5,4 2006.257.10:00:58.11#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.10:00:58.11#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.10:00:58.11#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:58.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:58.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:58.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:58.17#ibcon#enter wrdev, iclass 39, count 2 2006.257.10:00:58.17#ibcon#first serial, iclass 39, count 2 2006.257.10:00:58.17#ibcon#enter sib2, iclass 39, count 2 2006.257.10:00:58.17#ibcon#flushed, iclass 39, count 2 2006.257.10:00:58.17#ibcon#about to write, iclass 39, count 2 2006.257.10:00:58.17#ibcon#wrote, iclass 39, count 2 2006.257.10:00:58.17#ibcon#about to read 3, iclass 39, count 2 2006.257.10:00:58.19#ibcon#read 3, iclass 39, count 2 2006.257.10:00:58.19#ibcon#about to read 4, iclass 39, count 2 2006.257.10:00:58.19#ibcon#read 4, iclass 39, count 2 2006.257.10:00:58.19#ibcon#about to read 5, iclass 39, count 2 2006.257.10:00:58.19#ibcon#read 5, iclass 39, count 2 2006.257.10:00:58.19#ibcon#about to read 6, iclass 39, count 2 2006.257.10:00:58.19#ibcon#read 6, iclass 39, count 2 2006.257.10:00:58.19#ibcon#end of sib2, iclass 39, count 2 2006.257.10:00:58.19#ibcon#*mode == 0, iclass 39, count 2 2006.257.10:00:58.19#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.10:00:58.19#ibcon#[27=AT05-04\r\n] 2006.257.10:00:58.19#ibcon#*before write, iclass 39, count 2 2006.257.10:00:58.19#ibcon#enter sib2, iclass 39, count 2 2006.257.10:00:58.19#ibcon#flushed, iclass 39, count 2 2006.257.10:00:58.19#ibcon#about to write, iclass 39, count 2 2006.257.10:00:58.19#ibcon#wrote, iclass 39, count 2 2006.257.10:00:58.19#ibcon#about to read 3, iclass 39, count 2 2006.257.10:00:58.22#ibcon#read 3, iclass 39, count 2 2006.257.10:00:58.22#ibcon#about to read 4, iclass 39, count 2 2006.257.10:00:58.22#ibcon#read 4, iclass 39, count 2 2006.257.10:00:58.22#ibcon#about to read 5, iclass 39, count 2 2006.257.10:00:58.22#ibcon#read 5, iclass 39, count 2 2006.257.10:00:58.22#ibcon#about to read 6, iclass 39, count 2 2006.257.10:00:58.22#ibcon#read 6, iclass 39, count 2 2006.257.10:00:58.22#ibcon#end of sib2, iclass 39, count 2 2006.257.10:00:58.22#ibcon#*after write, iclass 39, count 2 2006.257.10:00:58.22#ibcon#*before return 0, iclass 39, count 2 2006.257.10:00:58.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:58.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:00:58.22#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.10:00:58.22#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:58.22#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:58.34#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:58.34#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:58.34#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:00:58.34#ibcon#first serial, iclass 39, count 0 2006.257.10:00:58.34#ibcon#enter sib2, iclass 39, count 0 2006.257.10:00:58.34#ibcon#flushed, iclass 39, count 0 2006.257.10:00:58.34#ibcon#about to write, iclass 39, count 0 2006.257.10:00:58.34#ibcon#wrote, iclass 39, count 0 2006.257.10:00:58.34#ibcon#about to read 3, iclass 39, count 0 2006.257.10:00:58.36#ibcon#read 3, iclass 39, count 0 2006.257.10:00:58.36#ibcon#about to read 4, iclass 39, count 0 2006.257.10:00:58.36#ibcon#read 4, iclass 39, count 0 2006.257.10:00:58.36#ibcon#about to read 5, iclass 39, count 0 2006.257.10:00:58.36#ibcon#read 5, iclass 39, count 0 2006.257.10:00:58.36#ibcon#about to read 6, iclass 39, count 0 2006.257.10:00:58.36#ibcon#read 6, iclass 39, count 0 2006.257.10:00:58.36#ibcon#end of sib2, iclass 39, count 0 2006.257.10:00:58.36#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:00:58.36#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:00:58.36#ibcon#[27=USB\r\n] 2006.257.10:00:58.36#ibcon#*before write, iclass 39, count 0 2006.257.10:00:58.36#ibcon#enter sib2, iclass 39, count 0 2006.257.10:00:58.36#ibcon#flushed, iclass 39, count 0 2006.257.10:00:58.36#ibcon#about to write, iclass 39, count 0 2006.257.10:00:58.36#ibcon#wrote, iclass 39, count 0 2006.257.10:00:58.36#ibcon#about to read 3, iclass 39, count 0 2006.257.10:00:58.39#ibcon#read 3, iclass 39, count 0 2006.257.10:00:58.39#ibcon#about to read 4, iclass 39, count 0 2006.257.10:00:58.39#ibcon#read 4, iclass 39, count 0 2006.257.10:00:58.39#ibcon#about to read 5, iclass 39, count 0 2006.257.10:00:58.39#ibcon#read 5, iclass 39, count 0 2006.257.10:00:58.39#ibcon#about to read 6, iclass 39, count 0 2006.257.10:00:58.39#ibcon#read 6, iclass 39, count 0 2006.257.10:00:58.39#ibcon#end of sib2, iclass 39, count 0 2006.257.10:00:58.39#ibcon#*after write, iclass 39, count 0 2006.257.10:00:58.39#ibcon#*before return 0, iclass 39, count 0 2006.257.10:00:58.39#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:58.39#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:00:58.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:00:58.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:00:58.39$vck44/vblo=6,719.99 2006.257.10:00:58.39#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.10:00:58.39#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.10:00:58.39#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:58.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:58.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:58.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:58.39#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:00:58.39#ibcon#first serial, iclass 3, count 0 2006.257.10:00:58.39#ibcon#enter sib2, iclass 3, count 0 2006.257.10:00:58.39#ibcon#flushed, iclass 3, count 0 2006.257.10:00:58.39#ibcon#about to write, iclass 3, count 0 2006.257.10:00:58.39#ibcon#wrote, iclass 3, count 0 2006.257.10:00:58.39#ibcon#about to read 3, iclass 3, count 0 2006.257.10:00:58.41#ibcon#read 3, iclass 3, count 0 2006.257.10:00:58.41#ibcon#about to read 4, iclass 3, count 0 2006.257.10:00:58.41#ibcon#read 4, iclass 3, count 0 2006.257.10:00:58.41#ibcon#about to read 5, iclass 3, count 0 2006.257.10:00:58.41#ibcon#read 5, iclass 3, count 0 2006.257.10:00:58.41#ibcon#about to read 6, iclass 3, count 0 2006.257.10:00:58.41#ibcon#read 6, iclass 3, count 0 2006.257.10:00:58.41#ibcon#end of sib2, iclass 3, count 0 2006.257.10:00:58.41#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:00:58.41#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:00:58.41#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:00:58.41#ibcon#*before write, iclass 3, count 0 2006.257.10:00:58.41#ibcon#enter sib2, iclass 3, count 0 2006.257.10:00:58.41#ibcon#flushed, iclass 3, count 0 2006.257.10:00:58.41#ibcon#about to write, iclass 3, count 0 2006.257.10:00:58.41#ibcon#wrote, iclass 3, count 0 2006.257.10:00:58.41#ibcon#about to read 3, iclass 3, count 0 2006.257.10:00:58.45#ibcon#read 3, iclass 3, count 0 2006.257.10:00:58.45#ibcon#about to read 4, iclass 3, count 0 2006.257.10:00:58.45#ibcon#read 4, iclass 3, count 0 2006.257.10:00:58.45#ibcon#about to read 5, iclass 3, count 0 2006.257.10:00:58.45#ibcon#read 5, iclass 3, count 0 2006.257.10:00:58.45#ibcon#about to read 6, iclass 3, count 0 2006.257.10:00:58.45#ibcon#read 6, iclass 3, count 0 2006.257.10:00:58.45#ibcon#end of sib2, iclass 3, count 0 2006.257.10:00:58.45#ibcon#*after write, iclass 3, count 0 2006.257.10:00:58.45#ibcon#*before return 0, iclass 3, count 0 2006.257.10:00:58.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:58.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:00:58.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:00:58.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:00:58.45$vck44/vb=6,4 2006.257.10:00:58.45#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.10:00:58.45#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.10:00:58.45#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:58.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:58.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:58.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:58.51#ibcon#enter wrdev, iclass 5, count 2 2006.257.10:00:58.51#ibcon#first serial, iclass 5, count 2 2006.257.10:00:58.51#ibcon#enter sib2, iclass 5, count 2 2006.257.10:00:58.51#ibcon#flushed, iclass 5, count 2 2006.257.10:00:58.51#ibcon#about to write, iclass 5, count 2 2006.257.10:00:58.51#ibcon#wrote, iclass 5, count 2 2006.257.10:00:58.51#ibcon#about to read 3, iclass 5, count 2 2006.257.10:00:58.53#ibcon#read 3, iclass 5, count 2 2006.257.10:00:58.53#ibcon#about to read 4, iclass 5, count 2 2006.257.10:00:58.53#ibcon#read 4, iclass 5, count 2 2006.257.10:00:58.53#ibcon#about to read 5, iclass 5, count 2 2006.257.10:00:58.53#ibcon#read 5, iclass 5, count 2 2006.257.10:00:58.53#ibcon#about to read 6, iclass 5, count 2 2006.257.10:00:58.53#ibcon#read 6, iclass 5, count 2 2006.257.10:00:58.53#ibcon#end of sib2, iclass 5, count 2 2006.257.10:00:58.53#ibcon#*mode == 0, iclass 5, count 2 2006.257.10:00:58.53#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.10:00:58.53#ibcon#[27=AT06-04\r\n] 2006.257.10:00:58.53#ibcon#*before write, iclass 5, count 2 2006.257.10:00:58.53#ibcon#enter sib2, iclass 5, count 2 2006.257.10:00:58.53#ibcon#flushed, iclass 5, count 2 2006.257.10:00:58.53#ibcon#about to write, iclass 5, count 2 2006.257.10:00:58.53#ibcon#wrote, iclass 5, count 2 2006.257.10:00:58.53#ibcon#about to read 3, iclass 5, count 2 2006.257.10:00:58.62#ibcon#read 3, iclass 5, count 2 2006.257.10:00:58.62#ibcon#about to read 4, iclass 5, count 2 2006.257.10:00:58.62#ibcon#read 4, iclass 5, count 2 2006.257.10:00:58.62#ibcon#about to read 5, iclass 5, count 2 2006.257.10:00:58.62#ibcon#read 5, iclass 5, count 2 2006.257.10:00:58.62#ibcon#about to read 6, iclass 5, count 2 2006.257.10:00:58.62#ibcon#read 6, iclass 5, count 2 2006.257.10:00:58.62#ibcon#end of sib2, iclass 5, count 2 2006.257.10:00:58.62#ibcon#*after write, iclass 5, count 2 2006.257.10:00:58.62#ibcon#*before return 0, iclass 5, count 2 2006.257.10:00:58.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:58.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:00:58.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.10:00:58.62#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:58.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:58.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:58.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:58.74#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:00:58.74#ibcon#first serial, iclass 5, count 0 2006.257.10:00:58.74#ibcon#enter sib2, iclass 5, count 0 2006.257.10:00:58.74#ibcon#flushed, iclass 5, count 0 2006.257.10:00:58.74#ibcon#about to write, iclass 5, count 0 2006.257.10:00:58.74#ibcon#wrote, iclass 5, count 0 2006.257.10:00:58.74#ibcon#about to read 3, iclass 5, count 0 2006.257.10:00:58.76#ibcon#read 3, iclass 5, count 0 2006.257.10:00:58.76#ibcon#about to read 4, iclass 5, count 0 2006.257.10:00:58.76#ibcon#read 4, iclass 5, count 0 2006.257.10:00:58.76#ibcon#about to read 5, iclass 5, count 0 2006.257.10:00:58.76#ibcon#read 5, iclass 5, count 0 2006.257.10:00:58.76#ibcon#about to read 6, iclass 5, count 0 2006.257.10:00:58.76#ibcon#read 6, iclass 5, count 0 2006.257.10:00:58.76#ibcon#end of sib2, iclass 5, count 0 2006.257.10:00:58.76#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:00:58.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:00:58.76#ibcon#[27=USB\r\n] 2006.257.10:00:58.76#ibcon#*before write, iclass 5, count 0 2006.257.10:00:58.76#ibcon#enter sib2, iclass 5, count 0 2006.257.10:00:58.76#ibcon#flushed, iclass 5, count 0 2006.257.10:00:58.76#ibcon#about to write, iclass 5, count 0 2006.257.10:00:58.76#ibcon#wrote, iclass 5, count 0 2006.257.10:00:58.76#ibcon#about to read 3, iclass 5, count 0 2006.257.10:00:58.79#ibcon#read 3, iclass 5, count 0 2006.257.10:00:58.79#ibcon#about to read 4, iclass 5, count 0 2006.257.10:00:58.79#ibcon#read 4, iclass 5, count 0 2006.257.10:00:58.79#ibcon#about to read 5, iclass 5, count 0 2006.257.10:00:58.79#ibcon#read 5, iclass 5, count 0 2006.257.10:00:58.79#ibcon#about to read 6, iclass 5, count 0 2006.257.10:00:58.79#ibcon#read 6, iclass 5, count 0 2006.257.10:00:58.79#ibcon#end of sib2, iclass 5, count 0 2006.257.10:00:58.79#ibcon#*after write, iclass 5, count 0 2006.257.10:00:58.79#ibcon#*before return 0, iclass 5, count 0 2006.257.10:00:58.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:58.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:00:58.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:00:58.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:00:58.79$vck44/vblo=7,734.99 2006.257.10:00:58.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.10:00:58.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.10:00:58.79#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:58.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:58.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:58.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:58.79#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:00:58.79#ibcon#first serial, iclass 7, count 0 2006.257.10:00:58.79#ibcon#enter sib2, iclass 7, count 0 2006.257.10:00:58.79#ibcon#flushed, iclass 7, count 0 2006.257.10:00:58.79#ibcon#about to write, iclass 7, count 0 2006.257.10:00:58.79#ibcon#wrote, iclass 7, count 0 2006.257.10:00:58.79#ibcon#about to read 3, iclass 7, count 0 2006.257.10:00:58.81#ibcon#read 3, iclass 7, count 0 2006.257.10:00:58.81#ibcon#about to read 4, iclass 7, count 0 2006.257.10:00:58.81#ibcon#read 4, iclass 7, count 0 2006.257.10:00:58.81#ibcon#about to read 5, iclass 7, count 0 2006.257.10:00:58.81#ibcon#read 5, iclass 7, count 0 2006.257.10:00:58.81#ibcon#about to read 6, iclass 7, count 0 2006.257.10:00:58.81#ibcon#read 6, iclass 7, count 0 2006.257.10:00:58.81#ibcon#end of sib2, iclass 7, count 0 2006.257.10:00:58.81#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:00:58.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:00:58.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:00:58.81#ibcon#*before write, iclass 7, count 0 2006.257.10:00:58.81#ibcon#enter sib2, iclass 7, count 0 2006.257.10:00:58.81#ibcon#flushed, iclass 7, count 0 2006.257.10:00:58.81#ibcon#about to write, iclass 7, count 0 2006.257.10:00:58.81#ibcon#wrote, iclass 7, count 0 2006.257.10:00:58.81#ibcon#about to read 3, iclass 7, count 0 2006.257.10:00:58.85#ibcon#read 3, iclass 7, count 0 2006.257.10:00:58.85#ibcon#about to read 4, iclass 7, count 0 2006.257.10:00:58.85#ibcon#read 4, iclass 7, count 0 2006.257.10:00:58.85#ibcon#about to read 5, iclass 7, count 0 2006.257.10:00:58.85#ibcon#read 5, iclass 7, count 0 2006.257.10:00:58.85#ibcon#about to read 6, iclass 7, count 0 2006.257.10:00:58.85#ibcon#read 6, iclass 7, count 0 2006.257.10:00:58.85#ibcon#end of sib2, iclass 7, count 0 2006.257.10:00:58.85#ibcon#*after write, iclass 7, count 0 2006.257.10:00:58.85#ibcon#*before return 0, iclass 7, count 0 2006.257.10:00:58.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:58.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:00:58.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:00:58.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:00:58.85$vck44/vb=7,4 2006.257.10:00:58.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.10:00:58.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.10:00:58.85#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:58.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:58.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:58.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:58.91#ibcon#enter wrdev, iclass 11, count 2 2006.257.10:00:58.91#ibcon#first serial, iclass 11, count 2 2006.257.10:00:58.91#ibcon#enter sib2, iclass 11, count 2 2006.257.10:00:58.91#ibcon#flushed, iclass 11, count 2 2006.257.10:00:58.91#ibcon#about to write, iclass 11, count 2 2006.257.10:00:58.91#ibcon#wrote, iclass 11, count 2 2006.257.10:00:58.91#ibcon#about to read 3, iclass 11, count 2 2006.257.10:00:58.93#ibcon#read 3, iclass 11, count 2 2006.257.10:00:58.93#ibcon#about to read 4, iclass 11, count 2 2006.257.10:00:58.93#ibcon#read 4, iclass 11, count 2 2006.257.10:00:58.93#ibcon#about to read 5, iclass 11, count 2 2006.257.10:00:58.93#ibcon#read 5, iclass 11, count 2 2006.257.10:00:58.93#ibcon#about to read 6, iclass 11, count 2 2006.257.10:00:58.93#ibcon#read 6, iclass 11, count 2 2006.257.10:00:58.93#ibcon#end of sib2, iclass 11, count 2 2006.257.10:00:58.93#ibcon#*mode == 0, iclass 11, count 2 2006.257.10:00:58.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.10:00:58.93#ibcon#[27=AT07-04\r\n] 2006.257.10:00:58.93#ibcon#*before write, iclass 11, count 2 2006.257.10:00:58.93#ibcon#enter sib2, iclass 11, count 2 2006.257.10:00:58.93#ibcon#flushed, iclass 11, count 2 2006.257.10:00:58.93#ibcon#about to write, iclass 11, count 2 2006.257.10:00:58.93#ibcon#wrote, iclass 11, count 2 2006.257.10:00:58.93#ibcon#about to read 3, iclass 11, count 2 2006.257.10:00:58.96#ibcon#read 3, iclass 11, count 2 2006.257.10:00:58.96#ibcon#about to read 4, iclass 11, count 2 2006.257.10:00:58.96#ibcon#read 4, iclass 11, count 2 2006.257.10:00:58.96#ibcon#about to read 5, iclass 11, count 2 2006.257.10:00:58.96#ibcon#read 5, iclass 11, count 2 2006.257.10:00:58.96#ibcon#about to read 6, iclass 11, count 2 2006.257.10:00:58.96#ibcon#read 6, iclass 11, count 2 2006.257.10:00:58.96#ibcon#end of sib2, iclass 11, count 2 2006.257.10:00:58.96#ibcon#*after write, iclass 11, count 2 2006.257.10:00:58.96#ibcon#*before return 0, iclass 11, count 2 2006.257.10:00:58.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:58.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:00:58.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.10:00:58.96#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:58.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:59.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:59.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:59.08#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:00:59.08#ibcon#first serial, iclass 11, count 0 2006.257.10:00:59.08#ibcon#enter sib2, iclass 11, count 0 2006.257.10:00:59.08#ibcon#flushed, iclass 11, count 0 2006.257.10:00:59.08#ibcon#about to write, iclass 11, count 0 2006.257.10:00:59.08#ibcon#wrote, iclass 11, count 0 2006.257.10:00:59.08#ibcon#about to read 3, iclass 11, count 0 2006.257.10:00:59.10#ibcon#read 3, iclass 11, count 0 2006.257.10:00:59.10#ibcon#about to read 4, iclass 11, count 0 2006.257.10:00:59.10#ibcon#read 4, iclass 11, count 0 2006.257.10:00:59.10#ibcon#about to read 5, iclass 11, count 0 2006.257.10:00:59.10#ibcon#read 5, iclass 11, count 0 2006.257.10:00:59.10#ibcon#about to read 6, iclass 11, count 0 2006.257.10:00:59.10#ibcon#read 6, iclass 11, count 0 2006.257.10:00:59.10#ibcon#end of sib2, iclass 11, count 0 2006.257.10:00:59.10#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:00:59.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:00:59.10#ibcon#[27=USB\r\n] 2006.257.10:00:59.10#ibcon#*before write, iclass 11, count 0 2006.257.10:00:59.10#ibcon#enter sib2, iclass 11, count 0 2006.257.10:00:59.10#ibcon#flushed, iclass 11, count 0 2006.257.10:00:59.10#ibcon#about to write, iclass 11, count 0 2006.257.10:00:59.10#ibcon#wrote, iclass 11, count 0 2006.257.10:00:59.10#ibcon#about to read 3, iclass 11, count 0 2006.257.10:00:59.13#ibcon#read 3, iclass 11, count 0 2006.257.10:00:59.13#ibcon#about to read 4, iclass 11, count 0 2006.257.10:00:59.13#ibcon#read 4, iclass 11, count 0 2006.257.10:00:59.13#ibcon#about to read 5, iclass 11, count 0 2006.257.10:00:59.13#ibcon#read 5, iclass 11, count 0 2006.257.10:00:59.13#ibcon#about to read 6, iclass 11, count 0 2006.257.10:00:59.13#ibcon#read 6, iclass 11, count 0 2006.257.10:00:59.13#ibcon#end of sib2, iclass 11, count 0 2006.257.10:00:59.13#ibcon#*after write, iclass 11, count 0 2006.257.10:00:59.13#ibcon#*before return 0, iclass 11, count 0 2006.257.10:00:59.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:59.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:00:59.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:00:59.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:00:59.13$vck44/vblo=8,744.99 2006.257.10:00:59.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.10:00:59.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.10:00:59.13#ibcon#ireg 17 cls_cnt 0 2006.257.10:00:59.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:59.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:59.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:59.13#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:00:59.13#ibcon#first serial, iclass 13, count 0 2006.257.10:00:59.13#ibcon#enter sib2, iclass 13, count 0 2006.257.10:00:59.13#ibcon#flushed, iclass 13, count 0 2006.257.10:00:59.13#ibcon#about to write, iclass 13, count 0 2006.257.10:00:59.13#ibcon#wrote, iclass 13, count 0 2006.257.10:00:59.13#ibcon#about to read 3, iclass 13, count 0 2006.257.10:00:59.15#ibcon#read 3, iclass 13, count 0 2006.257.10:00:59.15#ibcon#about to read 4, iclass 13, count 0 2006.257.10:00:59.15#ibcon#read 4, iclass 13, count 0 2006.257.10:00:59.15#ibcon#about to read 5, iclass 13, count 0 2006.257.10:00:59.15#ibcon#read 5, iclass 13, count 0 2006.257.10:00:59.15#ibcon#about to read 6, iclass 13, count 0 2006.257.10:00:59.15#ibcon#read 6, iclass 13, count 0 2006.257.10:00:59.15#ibcon#end of sib2, iclass 13, count 0 2006.257.10:00:59.15#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:00:59.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:00:59.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:00:59.15#ibcon#*before write, iclass 13, count 0 2006.257.10:00:59.15#ibcon#enter sib2, iclass 13, count 0 2006.257.10:00:59.15#ibcon#flushed, iclass 13, count 0 2006.257.10:00:59.15#ibcon#about to write, iclass 13, count 0 2006.257.10:00:59.15#ibcon#wrote, iclass 13, count 0 2006.257.10:00:59.15#ibcon#about to read 3, iclass 13, count 0 2006.257.10:00:59.19#ibcon#read 3, iclass 13, count 0 2006.257.10:00:59.19#ibcon#about to read 4, iclass 13, count 0 2006.257.10:00:59.19#ibcon#read 4, iclass 13, count 0 2006.257.10:00:59.19#ibcon#about to read 5, iclass 13, count 0 2006.257.10:00:59.19#ibcon#read 5, iclass 13, count 0 2006.257.10:00:59.19#ibcon#about to read 6, iclass 13, count 0 2006.257.10:00:59.19#ibcon#read 6, iclass 13, count 0 2006.257.10:00:59.19#ibcon#end of sib2, iclass 13, count 0 2006.257.10:00:59.19#ibcon#*after write, iclass 13, count 0 2006.257.10:00:59.19#ibcon#*before return 0, iclass 13, count 0 2006.257.10:00:59.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:59.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:00:59.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:00:59.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:00:59.19$vck44/vb=8,4 2006.257.10:00:59.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.10:00:59.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.10:00:59.19#ibcon#ireg 11 cls_cnt 2 2006.257.10:00:59.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:59.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:59.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:59.25#ibcon#enter wrdev, iclass 15, count 2 2006.257.10:00:59.25#ibcon#first serial, iclass 15, count 2 2006.257.10:00:59.25#ibcon#enter sib2, iclass 15, count 2 2006.257.10:00:59.25#ibcon#flushed, iclass 15, count 2 2006.257.10:00:59.25#ibcon#about to write, iclass 15, count 2 2006.257.10:00:59.25#ibcon#wrote, iclass 15, count 2 2006.257.10:00:59.25#ibcon#about to read 3, iclass 15, count 2 2006.257.10:00:59.27#ibcon#read 3, iclass 15, count 2 2006.257.10:00:59.27#ibcon#about to read 4, iclass 15, count 2 2006.257.10:00:59.27#ibcon#read 4, iclass 15, count 2 2006.257.10:00:59.27#ibcon#about to read 5, iclass 15, count 2 2006.257.10:00:59.27#ibcon#read 5, iclass 15, count 2 2006.257.10:00:59.27#ibcon#about to read 6, iclass 15, count 2 2006.257.10:00:59.27#ibcon#read 6, iclass 15, count 2 2006.257.10:00:59.27#ibcon#end of sib2, iclass 15, count 2 2006.257.10:00:59.27#ibcon#*mode == 0, iclass 15, count 2 2006.257.10:00:59.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.10:00:59.27#ibcon#[27=AT08-04\r\n] 2006.257.10:00:59.27#ibcon#*before write, iclass 15, count 2 2006.257.10:00:59.27#ibcon#enter sib2, iclass 15, count 2 2006.257.10:00:59.27#ibcon#flushed, iclass 15, count 2 2006.257.10:00:59.27#ibcon#about to write, iclass 15, count 2 2006.257.10:00:59.27#ibcon#wrote, iclass 15, count 2 2006.257.10:00:59.27#ibcon#about to read 3, iclass 15, count 2 2006.257.10:00:59.30#ibcon#read 3, iclass 15, count 2 2006.257.10:00:59.30#ibcon#about to read 4, iclass 15, count 2 2006.257.10:00:59.30#ibcon#read 4, iclass 15, count 2 2006.257.10:00:59.30#ibcon#about to read 5, iclass 15, count 2 2006.257.10:00:59.30#ibcon#read 5, iclass 15, count 2 2006.257.10:00:59.30#ibcon#about to read 6, iclass 15, count 2 2006.257.10:00:59.30#ibcon#read 6, iclass 15, count 2 2006.257.10:00:59.30#ibcon#end of sib2, iclass 15, count 2 2006.257.10:00:59.30#ibcon#*after write, iclass 15, count 2 2006.257.10:00:59.30#ibcon#*before return 0, iclass 15, count 2 2006.257.10:00:59.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:59.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:00:59.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.10:00:59.30#ibcon#ireg 7 cls_cnt 0 2006.257.10:00:59.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:59.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:59.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:59.42#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:00:59.42#ibcon#first serial, iclass 15, count 0 2006.257.10:00:59.42#ibcon#enter sib2, iclass 15, count 0 2006.257.10:00:59.42#ibcon#flushed, iclass 15, count 0 2006.257.10:00:59.42#ibcon#about to write, iclass 15, count 0 2006.257.10:00:59.42#ibcon#wrote, iclass 15, count 0 2006.257.10:00:59.42#ibcon#about to read 3, iclass 15, count 0 2006.257.10:00:59.44#ibcon#read 3, iclass 15, count 0 2006.257.10:00:59.44#ibcon#about to read 4, iclass 15, count 0 2006.257.10:00:59.44#ibcon#read 4, iclass 15, count 0 2006.257.10:00:59.44#ibcon#about to read 5, iclass 15, count 0 2006.257.10:00:59.44#ibcon#read 5, iclass 15, count 0 2006.257.10:00:59.44#ibcon#about to read 6, iclass 15, count 0 2006.257.10:00:59.44#ibcon#read 6, iclass 15, count 0 2006.257.10:00:59.44#ibcon#end of sib2, iclass 15, count 0 2006.257.10:00:59.44#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:00:59.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:00:59.44#ibcon#[27=USB\r\n] 2006.257.10:00:59.44#ibcon#*before write, iclass 15, count 0 2006.257.10:00:59.44#ibcon#enter sib2, iclass 15, count 0 2006.257.10:00:59.44#ibcon#flushed, iclass 15, count 0 2006.257.10:00:59.44#ibcon#about to write, iclass 15, count 0 2006.257.10:00:59.44#ibcon#wrote, iclass 15, count 0 2006.257.10:00:59.44#ibcon#about to read 3, iclass 15, count 0 2006.257.10:00:59.47#ibcon#read 3, iclass 15, count 0 2006.257.10:00:59.47#ibcon#about to read 4, iclass 15, count 0 2006.257.10:00:59.47#ibcon#read 4, iclass 15, count 0 2006.257.10:00:59.47#ibcon#about to read 5, iclass 15, count 0 2006.257.10:00:59.47#ibcon#read 5, iclass 15, count 0 2006.257.10:00:59.47#ibcon#about to read 6, iclass 15, count 0 2006.257.10:00:59.47#ibcon#read 6, iclass 15, count 0 2006.257.10:00:59.47#ibcon#end of sib2, iclass 15, count 0 2006.257.10:00:59.47#ibcon#*after write, iclass 15, count 0 2006.257.10:00:59.47#ibcon#*before return 0, iclass 15, count 0 2006.257.10:00:59.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:59.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:00:59.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:00:59.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:00:59.47$vck44/vabw=wide 2006.257.10:00:59.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.10:00:59.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.10:00:59.47#ibcon#ireg 8 cls_cnt 0 2006.257.10:00:59.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:59.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:59.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:59.47#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:00:59.47#ibcon#first serial, iclass 17, count 0 2006.257.10:00:59.47#ibcon#enter sib2, iclass 17, count 0 2006.257.10:00:59.47#ibcon#flushed, iclass 17, count 0 2006.257.10:00:59.47#ibcon#about to write, iclass 17, count 0 2006.257.10:00:59.47#ibcon#wrote, iclass 17, count 0 2006.257.10:00:59.47#ibcon#about to read 3, iclass 17, count 0 2006.257.10:00:59.49#ibcon#read 3, iclass 17, count 0 2006.257.10:00:59.49#ibcon#about to read 4, iclass 17, count 0 2006.257.10:00:59.49#ibcon#read 4, iclass 17, count 0 2006.257.10:00:59.49#ibcon#about to read 5, iclass 17, count 0 2006.257.10:00:59.49#ibcon#read 5, iclass 17, count 0 2006.257.10:00:59.49#ibcon#about to read 6, iclass 17, count 0 2006.257.10:00:59.49#ibcon#read 6, iclass 17, count 0 2006.257.10:00:59.49#ibcon#end of sib2, iclass 17, count 0 2006.257.10:00:59.49#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:00:59.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:00:59.49#ibcon#[25=BW32\r\n] 2006.257.10:00:59.49#ibcon#*before write, iclass 17, count 0 2006.257.10:00:59.49#ibcon#enter sib2, iclass 17, count 0 2006.257.10:00:59.49#ibcon#flushed, iclass 17, count 0 2006.257.10:00:59.49#ibcon#about to write, iclass 17, count 0 2006.257.10:00:59.49#ibcon#wrote, iclass 17, count 0 2006.257.10:00:59.49#ibcon#about to read 3, iclass 17, count 0 2006.257.10:00:59.52#ibcon#read 3, iclass 17, count 0 2006.257.10:00:59.52#ibcon#about to read 4, iclass 17, count 0 2006.257.10:00:59.52#ibcon#read 4, iclass 17, count 0 2006.257.10:00:59.52#ibcon#about to read 5, iclass 17, count 0 2006.257.10:00:59.52#ibcon#read 5, iclass 17, count 0 2006.257.10:00:59.52#ibcon#about to read 6, iclass 17, count 0 2006.257.10:00:59.52#ibcon#read 6, iclass 17, count 0 2006.257.10:00:59.52#ibcon#end of sib2, iclass 17, count 0 2006.257.10:00:59.52#ibcon#*after write, iclass 17, count 0 2006.257.10:00:59.52#ibcon#*before return 0, iclass 17, count 0 2006.257.10:00:59.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:59.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:00:59.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:00:59.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:00:59.52$vck44/vbbw=wide 2006.257.10:00:59.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.10:00:59.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.10:00:59.52#ibcon#ireg 8 cls_cnt 0 2006.257.10:00:59.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:00:59.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:00:59.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:00:59.59#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:00:59.59#ibcon#first serial, iclass 19, count 0 2006.257.10:00:59.59#ibcon#enter sib2, iclass 19, count 0 2006.257.10:00:59.59#ibcon#flushed, iclass 19, count 0 2006.257.10:00:59.59#ibcon#about to write, iclass 19, count 0 2006.257.10:00:59.59#ibcon#wrote, iclass 19, count 0 2006.257.10:00:59.59#ibcon#about to read 3, iclass 19, count 0 2006.257.10:00:59.61#ibcon#read 3, iclass 19, count 0 2006.257.10:00:59.61#ibcon#about to read 4, iclass 19, count 0 2006.257.10:00:59.61#ibcon#read 4, iclass 19, count 0 2006.257.10:00:59.61#ibcon#about to read 5, iclass 19, count 0 2006.257.10:00:59.61#ibcon#read 5, iclass 19, count 0 2006.257.10:00:59.61#ibcon#about to read 6, iclass 19, count 0 2006.257.10:00:59.61#ibcon#read 6, iclass 19, count 0 2006.257.10:00:59.61#ibcon#end of sib2, iclass 19, count 0 2006.257.10:00:59.61#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:00:59.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:00:59.61#ibcon#[27=BW32\r\n] 2006.257.10:00:59.61#ibcon#*before write, iclass 19, count 0 2006.257.10:00:59.61#ibcon#enter sib2, iclass 19, count 0 2006.257.10:00:59.61#ibcon#flushed, iclass 19, count 0 2006.257.10:00:59.61#ibcon#about to write, iclass 19, count 0 2006.257.10:00:59.61#ibcon#wrote, iclass 19, count 0 2006.257.10:00:59.61#ibcon#about to read 3, iclass 19, count 0 2006.257.10:00:59.64#ibcon#read 3, iclass 19, count 0 2006.257.10:00:59.64#ibcon#about to read 4, iclass 19, count 0 2006.257.10:00:59.64#ibcon#read 4, iclass 19, count 0 2006.257.10:00:59.64#ibcon#about to read 5, iclass 19, count 0 2006.257.10:00:59.64#ibcon#read 5, iclass 19, count 0 2006.257.10:00:59.64#ibcon#about to read 6, iclass 19, count 0 2006.257.10:00:59.64#ibcon#read 6, iclass 19, count 0 2006.257.10:00:59.64#ibcon#end of sib2, iclass 19, count 0 2006.257.10:00:59.64#ibcon#*after write, iclass 19, count 0 2006.257.10:00:59.64#ibcon#*before return 0, iclass 19, count 0 2006.257.10:00:59.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:00:59.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:00:59.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:00:59.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:00:59.68$setupk4/ifdk4 2006.257.10:00:59.68$ifdk4/lo= 2006.257.10:00:59.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:00:59.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:00:59.68$ifdk4/patch= 2006.257.10:00:59.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:00:59.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:00:59.68$setupk4/!*+20s 2006.257.10:01:01.58#abcon#<5=/15 0.6 1.7 19.23 961013.4\r\n> 2006.257.10:01:01.60#abcon#{5=INTERFACE CLEAR} 2006.257.10:01:01.66#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:01:11.75#abcon#<5=/15 0.6 1.8 19.22 961013.4\r\n> 2006.257.10:01:11.77#abcon#{5=INTERFACE CLEAR} 2006.257.10:01:11.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:01:14.10$setupk4/"tpicd 2006.257.10:01:14.10$setupk4/echo=off 2006.257.10:01:14.10$setupk4/xlog=off 2006.257.10:01:14.10:!2006.257.10:04:57 2006.257.10:01:34.14#trakl#Source acquired 2006.257.10:01:35.14#flagr#flagr/antenna,acquired 2006.257.10:04:57.00:preob 2006.257.10:04:57.14/onsource/TRACKING 2006.257.10:04:57.14:!2006.257.10:05:07 2006.257.10:05:07.00:"tape 2006.257.10:05:07.00:"st=record 2006.257.10:05:07.00:data_valid=on 2006.257.10:05:07.00:midob 2006.257.10:05:08.14/onsource/TRACKING 2006.257.10:05:08.14/wx/19.21,1013.4,96 2006.257.10:05:08.32/cable/+6.4779E-03 2006.257.10:05:09.41/va/01,08,usb,yes,30,33 2006.257.10:05:09.41/va/02,07,usb,yes,33,33 2006.257.10:05:09.41/va/03,08,usb,yes,29,31 2006.257.10:05:09.41/va/04,07,usb,yes,34,35 2006.257.10:05:09.41/va/05,04,usb,yes,30,31 2006.257.10:05:09.41/va/06,04,usb,yes,34,33 2006.257.10:05:09.41/va/07,04,usb,yes,35,35 2006.257.10:05:09.41/va/08,04,usb,yes,29,35 2006.257.10:05:09.64/valo/01,524.99,yes,locked 2006.257.10:05:09.64/valo/02,534.99,yes,locked 2006.257.10:05:09.64/valo/03,564.99,yes,locked 2006.257.10:05:09.64/valo/04,624.99,yes,locked 2006.257.10:05:09.64/valo/05,734.99,yes,locked 2006.257.10:05:09.64/valo/06,814.99,yes,locked 2006.257.10:05:09.64/valo/07,864.99,yes,locked 2006.257.10:05:09.64/valo/08,884.99,yes,locked 2006.257.10:05:10.73/vb/01,04,usb,yes,30,28 2006.257.10:05:10.73/vb/02,05,usb,yes,29,29 2006.257.10:05:10.73/vb/03,04,usb,yes,30,33 2006.257.10:05:10.73/vb/04,05,usb,yes,30,29 2006.257.10:05:10.73/vb/05,04,usb,yes,26,29 2006.257.10:05:10.73/vb/06,04,usb,yes,31,27 2006.257.10:05:10.73/vb/07,04,usb,yes,31,31 2006.257.10:05:10.73/vb/08,04,usb,yes,28,32 2006.257.10:05:10.97/vblo/01,629.99,yes,locked 2006.257.10:05:10.97/vblo/02,634.99,yes,locked 2006.257.10:05:10.97/vblo/03,649.99,yes,locked 2006.257.10:05:10.97/vblo/04,679.99,yes,locked 2006.257.10:05:10.97/vblo/05,709.99,yes,locked 2006.257.10:05:10.97/vblo/06,719.99,yes,locked 2006.257.10:05:10.97/vblo/07,734.99,yes,locked 2006.257.10:05:10.97/vblo/08,744.99,yes,locked 2006.257.10:05:11.12/vabw/8 2006.257.10:05:11.27/vbbw/8 2006.257.10:05:11.36/xfe/off,on,15.2 2006.257.10:05:11.74/ifatt/23,28,28,28 2006.257.10:05:12.08/fmout-gps/S +4.63E-07 2006.257.10:05:12.12:!2006.257.10:05:57 2006.257.10:05:57.00:data_valid=off 2006.257.10:05:57.00:"et 2006.257.10:05:57.00:!+3s 2006.257.10:06:00.01:"tape 2006.257.10:06:00.01:postob 2006.257.10:06:00.08/cable/+6.4774E-03 2006.257.10:06:00.08/wx/19.20,1013.4,96 2006.257.10:06:01.07/fmout-gps/S +4.63E-07 2006.257.10:06:01.07:scan_name=257-1010,jd0609,340 2006.257.10:06:01.07:source=1622-253,162546.89,-252738.3,2000.0,ccw 2006.257.10:06:02.13#flagr#flagr/antenna,new-source 2006.257.10:06:02.13:checkk5 2006.257.10:06:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:06:02.86/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:06:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:06:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:06:04.04/chk_obsdata//k5ts1/T2571005??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.10:06:04.45/chk_obsdata//k5ts2/T2571005??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.10:06:04.84/chk_obsdata//k5ts3/T2571005??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.10:06:05.26/chk_obsdata//k5ts4/T2571005??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.10:06:05.99/k5log//k5ts1_log_newline 2006.257.10:06:06.70/k5log//k5ts2_log_newline 2006.257.10:06:07.40/k5log//k5ts3_log_newline 2006.257.10:06:08.10/k5log//k5ts4_log_newline 2006.257.10:06:08.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:06:08.12:setupk4=1 2006.257.10:06:08.12$setupk4/echo=on 2006.257.10:06:08.12$setupk4/pcalon 2006.257.10:06:08.12$pcalon/"no phase cal control is implemented here 2006.257.10:06:08.12$setupk4/"tpicd=stop 2006.257.10:06:08.12$setupk4/"rec=synch_on 2006.257.10:06:08.12$setupk4/"rec_mode=128 2006.257.10:06:08.12$setupk4/!* 2006.257.10:06:08.12$setupk4/recpk4 2006.257.10:06:08.12$recpk4/recpatch= 2006.257.10:06:08.13$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:06:08.13$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:06:08.13$setupk4/vck44 2006.257.10:06:08.13$vck44/valo=1,524.99 2006.257.10:06:08.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.10:06:08.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.10:06:08.13#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:08.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:08.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:08.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:08.13#ibcon#enter wrdev, iclass 40, count 0 2006.257.10:06:08.13#ibcon#first serial, iclass 40, count 0 2006.257.10:06:08.13#ibcon#enter sib2, iclass 40, count 0 2006.257.10:06:08.13#ibcon#flushed, iclass 40, count 0 2006.257.10:06:08.13#ibcon#about to write, iclass 40, count 0 2006.257.10:06:08.13#ibcon#wrote, iclass 40, count 0 2006.257.10:06:08.13#ibcon#about to read 3, iclass 40, count 0 2006.257.10:06:08.15#ibcon#read 3, iclass 40, count 0 2006.257.10:06:08.15#ibcon#about to read 4, iclass 40, count 0 2006.257.10:06:08.15#ibcon#read 4, iclass 40, count 0 2006.257.10:06:08.15#ibcon#about to read 5, iclass 40, count 0 2006.257.10:06:08.15#ibcon#read 5, iclass 40, count 0 2006.257.10:06:08.15#ibcon#about to read 6, iclass 40, count 0 2006.257.10:06:08.15#ibcon#read 6, iclass 40, count 0 2006.257.10:06:08.15#ibcon#end of sib2, iclass 40, count 0 2006.257.10:06:08.15#ibcon#*mode == 0, iclass 40, count 0 2006.257.10:06:08.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.10:06:08.15#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:06:08.15#ibcon#*before write, iclass 40, count 0 2006.257.10:06:08.15#ibcon#enter sib2, iclass 40, count 0 2006.257.10:06:08.15#ibcon#flushed, iclass 40, count 0 2006.257.10:06:08.15#ibcon#about to write, iclass 40, count 0 2006.257.10:06:08.15#ibcon#wrote, iclass 40, count 0 2006.257.10:06:08.15#ibcon#about to read 3, iclass 40, count 0 2006.257.10:06:08.20#ibcon#read 3, iclass 40, count 0 2006.257.10:06:08.20#ibcon#about to read 4, iclass 40, count 0 2006.257.10:06:08.20#ibcon#read 4, iclass 40, count 0 2006.257.10:06:08.20#ibcon#about to read 5, iclass 40, count 0 2006.257.10:06:08.20#ibcon#read 5, iclass 40, count 0 2006.257.10:06:08.20#ibcon#about to read 6, iclass 40, count 0 2006.257.10:06:08.20#ibcon#read 6, iclass 40, count 0 2006.257.10:06:08.20#ibcon#end of sib2, iclass 40, count 0 2006.257.10:06:08.20#ibcon#*after write, iclass 40, count 0 2006.257.10:06:08.20#ibcon#*before return 0, iclass 40, count 0 2006.257.10:06:08.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:08.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:08.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.10:06:08.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.10:06:08.20$vck44/va=1,8 2006.257.10:06:08.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.10:06:08.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.10:06:08.20#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:08.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:08.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:08.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:08.20#ibcon#enter wrdev, iclass 4, count 2 2006.257.10:06:08.20#ibcon#first serial, iclass 4, count 2 2006.257.10:06:08.20#ibcon#enter sib2, iclass 4, count 2 2006.257.10:06:08.20#ibcon#flushed, iclass 4, count 2 2006.257.10:06:08.20#ibcon#about to write, iclass 4, count 2 2006.257.10:06:08.20#ibcon#wrote, iclass 4, count 2 2006.257.10:06:08.20#ibcon#about to read 3, iclass 4, count 2 2006.257.10:06:08.22#ibcon#read 3, iclass 4, count 2 2006.257.10:06:08.22#ibcon#about to read 4, iclass 4, count 2 2006.257.10:06:08.22#ibcon#read 4, iclass 4, count 2 2006.257.10:06:08.22#ibcon#about to read 5, iclass 4, count 2 2006.257.10:06:08.22#ibcon#read 5, iclass 4, count 2 2006.257.10:06:08.22#ibcon#about to read 6, iclass 4, count 2 2006.257.10:06:08.22#ibcon#read 6, iclass 4, count 2 2006.257.10:06:08.22#ibcon#end of sib2, iclass 4, count 2 2006.257.10:06:08.22#ibcon#*mode == 0, iclass 4, count 2 2006.257.10:06:08.22#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.10:06:08.22#ibcon#[25=AT01-08\r\n] 2006.257.10:06:08.22#ibcon#*before write, iclass 4, count 2 2006.257.10:06:08.22#ibcon#enter sib2, iclass 4, count 2 2006.257.10:06:08.22#ibcon#flushed, iclass 4, count 2 2006.257.10:06:08.22#ibcon#about to write, iclass 4, count 2 2006.257.10:06:08.22#ibcon#wrote, iclass 4, count 2 2006.257.10:06:08.22#ibcon#about to read 3, iclass 4, count 2 2006.257.10:06:08.25#ibcon#read 3, iclass 4, count 2 2006.257.10:06:08.25#ibcon#about to read 4, iclass 4, count 2 2006.257.10:06:08.25#ibcon#read 4, iclass 4, count 2 2006.257.10:06:08.25#ibcon#about to read 5, iclass 4, count 2 2006.257.10:06:08.25#ibcon#read 5, iclass 4, count 2 2006.257.10:06:08.25#ibcon#about to read 6, iclass 4, count 2 2006.257.10:06:08.25#ibcon#read 6, iclass 4, count 2 2006.257.10:06:08.25#ibcon#end of sib2, iclass 4, count 2 2006.257.10:06:08.25#ibcon#*after write, iclass 4, count 2 2006.257.10:06:08.25#ibcon#*before return 0, iclass 4, count 2 2006.257.10:06:08.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:08.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:08.25#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.10:06:08.25#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:08.25#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:08.37#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:08.37#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:08.37#ibcon#enter wrdev, iclass 4, count 0 2006.257.10:06:08.37#ibcon#first serial, iclass 4, count 0 2006.257.10:06:08.37#ibcon#enter sib2, iclass 4, count 0 2006.257.10:06:08.37#ibcon#flushed, iclass 4, count 0 2006.257.10:06:08.37#ibcon#about to write, iclass 4, count 0 2006.257.10:06:08.37#ibcon#wrote, iclass 4, count 0 2006.257.10:06:08.37#ibcon#about to read 3, iclass 4, count 0 2006.257.10:06:08.39#ibcon#read 3, iclass 4, count 0 2006.257.10:06:08.39#ibcon#about to read 4, iclass 4, count 0 2006.257.10:06:08.39#ibcon#read 4, iclass 4, count 0 2006.257.10:06:08.39#ibcon#about to read 5, iclass 4, count 0 2006.257.10:06:08.39#ibcon#read 5, iclass 4, count 0 2006.257.10:06:08.39#ibcon#about to read 6, iclass 4, count 0 2006.257.10:06:08.39#ibcon#read 6, iclass 4, count 0 2006.257.10:06:08.39#ibcon#end of sib2, iclass 4, count 0 2006.257.10:06:08.39#ibcon#*mode == 0, iclass 4, count 0 2006.257.10:06:08.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.10:06:08.39#ibcon#[25=USB\r\n] 2006.257.10:06:08.39#ibcon#*before write, iclass 4, count 0 2006.257.10:06:08.39#ibcon#enter sib2, iclass 4, count 0 2006.257.10:06:08.39#ibcon#flushed, iclass 4, count 0 2006.257.10:06:08.39#ibcon#about to write, iclass 4, count 0 2006.257.10:06:08.39#ibcon#wrote, iclass 4, count 0 2006.257.10:06:08.39#ibcon#about to read 3, iclass 4, count 0 2006.257.10:06:08.42#ibcon#read 3, iclass 4, count 0 2006.257.10:06:08.42#ibcon#about to read 4, iclass 4, count 0 2006.257.10:06:08.42#ibcon#read 4, iclass 4, count 0 2006.257.10:06:08.42#ibcon#about to read 5, iclass 4, count 0 2006.257.10:06:08.42#ibcon#read 5, iclass 4, count 0 2006.257.10:06:08.42#ibcon#about to read 6, iclass 4, count 0 2006.257.10:06:08.42#ibcon#read 6, iclass 4, count 0 2006.257.10:06:08.42#ibcon#end of sib2, iclass 4, count 0 2006.257.10:06:08.42#ibcon#*after write, iclass 4, count 0 2006.257.10:06:08.42#ibcon#*before return 0, iclass 4, count 0 2006.257.10:06:08.42#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:08.42#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:08.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.10:06:08.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.10:06:08.42$vck44/valo=2,534.99 2006.257.10:06:08.42#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.10:06:08.42#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.10:06:08.42#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:08.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:08.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:08.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:08.42#ibcon#enter wrdev, iclass 6, count 0 2006.257.10:06:08.42#ibcon#first serial, iclass 6, count 0 2006.257.10:06:08.42#ibcon#enter sib2, iclass 6, count 0 2006.257.10:06:08.42#ibcon#flushed, iclass 6, count 0 2006.257.10:06:08.42#ibcon#about to write, iclass 6, count 0 2006.257.10:06:08.42#ibcon#wrote, iclass 6, count 0 2006.257.10:06:08.42#ibcon#about to read 3, iclass 6, count 0 2006.257.10:06:08.44#ibcon#read 3, iclass 6, count 0 2006.257.10:06:08.44#ibcon#about to read 4, iclass 6, count 0 2006.257.10:06:08.44#ibcon#read 4, iclass 6, count 0 2006.257.10:06:08.44#ibcon#about to read 5, iclass 6, count 0 2006.257.10:06:08.44#ibcon#read 5, iclass 6, count 0 2006.257.10:06:08.44#ibcon#about to read 6, iclass 6, count 0 2006.257.10:06:08.44#ibcon#read 6, iclass 6, count 0 2006.257.10:06:08.44#ibcon#end of sib2, iclass 6, count 0 2006.257.10:06:08.44#ibcon#*mode == 0, iclass 6, count 0 2006.257.10:06:08.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.10:06:08.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:06:08.44#ibcon#*before write, iclass 6, count 0 2006.257.10:06:08.44#ibcon#enter sib2, iclass 6, count 0 2006.257.10:06:08.44#ibcon#flushed, iclass 6, count 0 2006.257.10:06:08.44#ibcon#about to write, iclass 6, count 0 2006.257.10:06:08.44#ibcon#wrote, iclass 6, count 0 2006.257.10:06:08.44#ibcon#about to read 3, iclass 6, count 0 2006.257.10:06:08.48#ibcon#read 3, iclass 6, count 0 2006.257.10:06:08.48#ibcon#about to read 4, iclass 6, count 0 2006.257.10:06:08.48#ibcon#read 4, iclass 6, count 0 2006.257.10:06:08.48#ibcon#about to read 5, iclass 6, count 0 2006.257.10:06:08.48#ibcon#read 5, iclass 6, count 0 2006.257.10:06:08.48#ibcon#about to read 6, iclass 6, count 0 2006.257.10:06:08.48#ibcon#read 6, iclass 6, count 0 2006.257.10:06:08.48#ibcon#end of sib2, iclass 6, count 0 2006.257.10:06:08.48#ibcon#*after write, iclass 6, count 0 2006.257.10:06:08.48#ibcon#*before return 0, iclass 6, count 0 2006.257.10:06:08.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:08.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:08.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.10:06:08.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.10:06:08.48$vck44/va=2,7 2006.257.10:06:08.48#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.10:06:08.48#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.10:06:08.48#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:08.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:08.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:08.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:08.54#ibcon#enter wrdev, iclass 10, count 2 2006.257.10:06:08.54#ibcon#first serial, iclass 10, count 2 2006.257.10:06:08.54#ibcon#enter sib2, iclass 10, count 2 2006.257.10:06:08.54#ibcon#flushed, iclass 10, count 2 2006.257.10:06:08.54#ibcon#about to write, iclass 10, count 2 2006.257.10:06:08.54#ibcon#wrote, iclass 10, count 2 2006.257.10:06:08.54#ibcon#about to read 3, iclass 10, count 2 2006.257.10:06:08.56#ibcon#read 3, iclass 10, count 2 2006.257.10:06:08.56#ibcon#about to read 4, iclass 10, count 2 2006.257.10:06:08.56#ibcon#read 4, iclass 10, count 2 2006.257.10:06:08.56#ibcon#about to read 5, iclass 10, count 2 2006.257.10:06:08.56#ibcon#read 5, iclass 10, count 2 2006.257.10:06:08.56#ibcon#about to read 6, iclass 10, count 2 2006.257.10:06:08.56#ibcon#read 6, iclass 10, count 2 2006.257.10:06:08.56#ibcon#end of sib2, iclass 10, count 2 2006.257.10:06:08.56#ibcon#*mode == 0, iclass 10, count 2 2006.257.10:06:08.56#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.10:06:08.56#ibcon#[25=AT02-07\r\n] 2006.257.10:06:08.56#ibcon#*before write, iclass 10, count 2 2006.257.10:06:08.56#ibcon#enter sib2, iclass 10, count 2 2006.257.10:06:08.56#ibcon#flushed, iclass 10, count 2 2006.257.10:06:08.56#ibcon#about to write, iclass 10, count 2 2006.257.10:06:08.56#ibcon#wrote, iclass 10, count 2 2006.257.10:06:08.56#ibcon#about to read 3, iclass 10, count 2 2006.257.10:06:08.59#ibcon#read 3, iclass 10, count 2 2006.257.10:06:08.59#ibcon#about to read 4, iclass 10, count 2 2006.257.10:06:08.59#ibcon#read 4, iclass 10, count 2 2006.257.10:06:08.59#ibcon#about to read 5, iclass 10, count 2 2006.257.10:06:08.59#ibcon#read 5, iclass 10, count 2 2006.257.10:06:08.59#ibcon#about to read 6, iclass 10, count 2 2006.257.10:06:08.59#ibcon#read 6, iclass 10, count 2 2006.257.10:06:08.59#ibcon#end of sib2, iclass 10, count 2 2006.257.10:06:08.59#ibcon#*after write, iclass 10, count 2 2006.257.10:06:08.59#ibcon#*before return 0, iclass 10, count 2 2006.257.10:06:08.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:08.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:08.59#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.10:06:08.59#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:08.59#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:08.71#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:08.71#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:08.71#ibcon#enter wrdev, iclass 10, count 0 2006.257.10:06:08.71#ibcon#first serial, iclass 10, count 0 2006.257.10:06:08.71#ibcon#enter sib2, iclass 10, count 0 2006.257.10:06:08.71#ibcon#flushed, iclass 10, count 0 2006.257.10:06:08.71#ibcon#about to write, iclass 10, count 0 2006.257.10:06:08.71#ibcon#wrote, iclass 10, count 0 2006.257.10:06:08.71#ibcon#about to read 3, iclass 10, count 0 2006.257.10:06:08.73#ibcon#read 3, iclass 10, count 0 2006.257.10:06:08.73#ibcon#about to read 4, iclass 10, count 0 2006.257.10:06:08.73#ibcon#read 4, iclass 10, count 0 2006.257.10:06:08.73#ibcon#about to read 5, iclass 10, count 0 2006.257.10:06:08.73#ibcon#read 5, iclass 10, count 0 2006.257.10:06:08.73#ibcon#about to read 6, iclass 10, count 0 2006.257.10:06:08.73#ibcon#read 6, iclass 10, count 0 2006.257.10:06:08.73#ibcon#end of sib2, iclass 10, count 0 2006.257.10:06:08.73#ibcon#*mode == 0, iclass 10, count 0 2006.257.10:06:08.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.10:06:08.73#ibcon#[25=USB\r\n] 2006.257.10:06:08.73#ibcon#*before write, iclass 10, count 0 2006.257.10:06:08.73#ibcon#enter sib2, iclass 10, count 0 2006.257.10:06:08.73#ibcon#flushed, iclass 10, count 0 2006.257.10:06:08.73#ibcon#about to write, iclass 10, count 0 2006.257.10:06:08.73#ibcon#wrote, iclass 10, count 0 2006.257.10:06:08.73#ibcon#about to read 3, iclass 10, count 0 2006.257.10:06:08.76#ibcon#read 3, iclass 10, count 0 2006.257.10:06:08.76#ibcon#about to read 4, iclass 10, count 0 2006.257.10:06:08.76#ibcon#read 4, iclass 10, count 0 2006.257.10:06:08.76#ibcon#about to read 5, iclass 10, count 0 2006.257.10:06:08.76#ibcon#read 5, iclass 10, count 0 2006.257.10:06:08.76#ibcon#about to read 6, iclass 10, count 0 2006.257.10:06:08.76#ibcon#read 6, iclass 10, count 0 2006.257.10:06:08.76#ibcon#end of sib2, iclass 10, count 0 2006.257.10:06:08.76#ibcon#*after write, iclass 10, count 0 2006.257.10:06:08.76#ibcon#*before return 0, iclass 10, count 0 2006.257.10:06:08.76#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:08.76#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:08.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.10:06:08.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.10:06:08.76$vck44/valo=3,564.99 2006.257.10:06:08.76#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.10:06:08.76#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.10:06:08.76#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:08.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:08.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:08.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:08.76#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:06:08.76#ibcon#first serial, iclass 12, count 0 2006.257.10:06:08.76#ibcon#enter sib2, iclass 12, count 0 2006.257.10:06:08.76#ibcon#flushed, iclass 12, count 0 2006.257.10:06:08.76#ibcon#about to write, iclass 12, count 0 2006.257.10:06:08.76#ibcon#wrote, iclass 12, count 0 2006.257.10:06:08.76#ibcon#about to read 3, iclass 12, count 0 2006.257.10:06:08.78#ibcon#read 3, iclass 12, count 0 2006.257.10:06:08.78#ibcon#about to read 4, iclass 12, count 0 2006.257.10:06:08.78#ibcon#read 4, iclass 12, count 0 2006.257.10:06:08.78#ibcon#about to read 5, iclass 12, count 0 2006.257.10:06:08.78#ibcon#read 5, iclass 12, count 0 2006.257.10:06:08.78#ibcon#about to read 6, iclass 12, count 0 2006.257.10:06:08.78#ibcon#read 6, iclass 12, count 0 2006.257.10:06:08.78#ibcon#end of sib2, iclass 12, count 0 2006.257.10:06:08.78#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:06:08.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:06:08.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:06:08.78#ibcon#*before write, iclass 12, count 0 2006.257.10:06:08.78#ibcon#enter sib2, iclass 12, count 0 2006.257.10:06:08.78#ibcon#flushed, iclass 12, count 0 2006.257.10:06:08.78#ibcon#about to write, iclass 12, count 0 2006.257.10:06:08.78#ibcon#wrote, iclass 12, count 0 2006.257.10:06:08.78#ibcon#about to read 3, iclass 12, count 0 2006.257.10:06:08.82#ibcon#read 3, iclass 12, count 0 2006.257.10:06:08.82#ibcon#about to read 4, iclass 12, count 0 2006.257.10:06:08.82#ibcon#read 4, iclass 12, count 0 2006.257.10:06:08.82#ibcon#about to read 5, iclass 12, count 0 2006.257.10:06:08.82#ibcon#read 5, iclass 12, count 0 2006.257.10:06:08.82#ibcon#about to read 6, iclass 12, count 0 2006.257.10:06:08.82#ibcon#read 6, iclass 12, count 0 2006.257.10:06:08.82#ibcon#end of sib2, iclass 12, count 0 2006.257.10:06:08.82#ibcon#*after write, iclass 12, count 0 2006.257.10:06:08.82#ibcon#*before return 0, iclass 12, count 0 2006.257.10:06:08.82#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:08.82#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:08.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:06:08.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:06:08.82$vck44/va=3,8 2006.257.10:06:08.82#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.10:06:08.82#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.10:06:08.82#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:08.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:08.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:08.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:08.88#ibcon#enter wrdev, iclass 14, count 2 2006.257.10:06:08.88#ibcon#first serial, iclass 14, count 2 2006.257.10:06:08.88#ibcon#enter sib2, iclass 14, count 2 2006.257.10:06:08.88#ibcon#flushed, iclass 14, count 2 2006.257.10:06:08.88#ibcon#about to write, iclass 14, count 2 2006.257.10:06:08.88#ibcon#wrote, iclass 14, count 2 2006.257.10:06:08.88#ibcon#about to read 3, iclass 14, count 2 2006.257.10:06:08.90#ibcon#read 3, iclass 14, count 2 2006.257.10:06:08.90#ibcon#about to read 4, iclass 14, count 2 2006.257.10:06:08.90#ibcon#read 4, iclass 14, count 2 2006.257.10:06:08.90#ibcon#about to read 5, iclass 14, count 2 2006.257.10:06:08.90#ibcon#read 5, iclass 14, count 2 2006.257.10:06:08.90#ibcon#about to read 6, iclass 14, count 2 2006.257.10:06:08.90#ibcon#read 6, iclass 14, count 2 2006.257.10:06:08.90#ibcon#end of sib2, iclass 14, count 2 2006.257.10:06:08.90#ibcon#*mode == 0, iclass 14, count 2 2006.257.10:06:08.90#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.10:06:08.90#ibcon#[25=AT03-08\r\n] 2006.257.10:06:08.90#ibcon#*before write, iclass 14, count 2 2006.257.10:06:08.90#ibcon#enter sib2, iclass 14, count 2 2006.257.10:06:08.90#ibcon#flushed, iclass 14, count 2 2006.257.10:06:08.90#ibcon#about to write, iclass 14, count 2 2006.257.10:06:08.90#ibcon#wrote, iclass 14, count 2 2006.257.10:06:08.90#ibcon#about to read 3, iclass 14, count 2 2006.257.10:06:08.93#ibcon#read 3, iclass 14, count 2 2006.257.10:06:08.93#ibcon#about to read 4, iclass 14, count 2 2006.257.10:06:08.93#ibcon#read 4, iclass 14, count 2 2006.257.10:06:08.93#ibcon#about to read 5, iclass 14, count 2 2006.257.10:06:08.93#ibcon#read 5, iclass 14, count 2 2006.257.10:06:08.93#ibcon#about to read 6, iclass 14, count 2 2006.257.10:06:08.93#ibcon#read 6, iclass 14, count 2 2006.257.10:06:08.93#ibcon#end of sib2, iclass 14, count 2 2006.257.10:06:08.93#ibcon#*after write, iclass 14, count 2 2006.257.10:06:08.93#ibcon#*before return 0, iclass 14, count 2 2006.257.10:06:08.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:08.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:08.93#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.10:06:08.93#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:08.93#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:09.05#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:09.05#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:09.05#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:06:09.05#ibcon#first serial, iclass 14, count 0 2006.257.10:06:09.05#ibcon#enter sib2, iclass 14, count 0 2006.257.10:06:09.05#ibcon#flushed, iclass 14, count 0 2006.257.10:06:09.05#ibcon#about to write, iclass 14, count 0 2006.257.10:06:09.05#ibcon#wrote, iclass 14, count 0 2006.257.10:06:09.05#ibcon#about to read 3, iclass 14, count 0 2006.257.10:06:09.07#ibcon#read 3, iclass 14, count 0 2006.257.10:06:09.07#ibcon#about to read 4, iclass 14, count 0 2006.257.10:06:09.07#ibcon#read 4, iclass 14, count 0 2006.257.10:06:09.07#ibcon#about to read 5, iclass 14, count 0 2006.257.10:06:09.07#ibcon#read 5, iclass 14, count 0 2006.257.10:06:09.07#ibcon#about to read 6, iclass 14, count 0 2006.257.10:06:09.07#ibcon#read 6, iclass 14, count 0 2006.257.10:06:09.07#ibcon#end of sib2, iclass 14, count 0 2006.257.10:06:09.07#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:06:09.07#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:06:09.07#ibcon#[25=USB\r\n] 2006.257.10:06:09.07#ibcon#*before write, iclass 14, count 0 2006.257.10:06:09.07#ibcon#enter sib2, iclass 14, count 0 2006.257.10:06:09.07#ibcon#flushed, iclass 14, count 0 2006.257.10:06:09.07#ibcon#about to write, iclass 14, count 0 2006.257.10:06:09.07#ibcon#wrote, iclass 14, count 0 2006.257.10:06:09.07#ibcon#about to read 3, iclass 14, count 0 2006.257.10:06:09.10#ibcon#read 3, iclass 14, count 0 2006.257.10:06:09.10#ibcon#about to read 4, iclass 14, count 0 2006.257.10:06:09.10#ibcon#read 4, iclass 14, count 0 2006.257.10:06:09.10#ibcon#about to read 5, iclass 14, count 0 2006.257.10:06:09.10#ibcon#read 5, iclass 14, count 0 2006.257.10:06:09.10#ibcon#about to read 6, iclass 14, count 0 2006.257.10:06:09.10#ibcon#read 6, iclass 14, count 0 2006.257.10:06:09.10#ibcon#end of sib2, iclass 14, count 0 2006.257.10:06:09.10#ibcon#*after write, iclass 14, count 0 2006.257.10:06:09.10#ibcon#*before return 0, iclass 14, count 0 2006.257.10:06:09.10#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:09.10#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:09.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:06:09.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:06:09.10$vck44/valo=4,624.99 2006.257.10:06:09.10#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.10:06:09.10#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.10:06:09.10#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:09.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:09.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:09.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:09.10#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:06:09.10#ibcon#first serial, iclass 16, count 0 2006.257.10:06:09.10#ibcon#enter sib2, iclass 16, count 0 2006.257.10:06:09.10#ibcon#flushed, iclass 16, count 0 2006.257.10:06:09.10#ibcon#about to write, iclass 16, count 0 2006.257.10:06:09.10#ibcon#wrote, iclass 16, count 0 2006.257.10:06:09.10#ibcon#about to read 3, iclass 16, count 0 2006.257.10:06:09.12#ibcon#read 3, iclass 16, count 0 2006.257.10:06:09.12#ibcon#about to read 4, iclass 16, count 0 2006.257.10:06:09.12#ibcon#read 4, iclass 16, count 0 2006.257.10:06:09.12#ibcon#about to read 5, iclass 16, count 0 2006.257.10:06:09.12#ibcon#read 5, iclass 16, count 0 2006.257.10:06:09.12#ibcon#about to read 6, iclass 16, count 0 2006.257.10:06:09.12#ibcon#read 6, iclass 16, count 0 2006.257.10:06:09.12#ibcon#end of sib2, iclass 16, count 0 2006.257.10:06:09.12#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:06:09.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:06:09.12#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:06:09.12#ibcon#*before write, iclass 16, count 0 2006.257.10:06:09.12#ibcon#enter sib2, iclass 16, count 0 2006.257.10:06:09.12#ibcon#flushed, iclass 16, count 0 2006.257.10:06:09.12#ibcon#about to write, iclass 16, count 0 2006.257.10:06:09.12#ibcon#wrote, iclass 16, count 0 2006.257.10:06:09.12#ibcon#about to read 3, iclass 16, count 0 2006.257.10:06:09.16#ibcon#read 3, iclass 16, count 0 2006.257.10:06:09.16#ibcon#about to read 4, iclass 16, count 0 2006.257.10:06:09.16#ibcon#read 4, iclass 16, count 0 2006.257.10:06:09.16#ibcon#about to read 5, iclass 16, count 0 2006.257.10:06:09.16#ibcon#read 5, iclass 16, count 0 2006.257.10:06:09.16#ibcon#about to read 6, iclass 16, count 0 2006.257.10:06:09.16#ibcon#read 6, iclass 16, count 0 2006.257.10:06:09.16#ibcon#end of sib2, iclass 16, count 0 2006.257.10:06:09.16#ibcon#*after write, iclass 16, count 0 2006.257.10:06:09.16#ibcon#*before return 0, iclass 16, count 0 2006.257.10:06:09.16#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:09.16#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:09.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:06:09.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:06:09.16$vck44/va=4,7 2006.257.10:06:09.16#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.10:06:09.16#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.10:06:09.16#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:09.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:09.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:09.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:09.22#ibcon#enter wrdev, iclass 18, count 2 2006.257.10:06:09.22#ibcon#first serial, iclass 18, count 2 2006.257.10:06:09.22#ibcon#enter sib2, iclass 18, count 2 2006.257.10:06:09.22#ibcon#flushed, iclass 18, count 2 2006.257.10:06:09.22#ibcon#about to write, iclass 18, count 2 2006.257.10:06:09.22#ibcon#wrote, iclass 18, count 2 2006.257.10:06:09.22#ibcon#about to read 3, iclass 18, count 2 2006.257.10:06:09.24#ibcon#read 3, iclass 18, count 2 2006.257.10:06:09.24#ibcon#about to read 4, iclass 18, count 2 2006.257.10:06:09.24#ibcon#read 4, iclass 18, count 2 2006.257.10:06:09.24#ibcon#about to read 5, iclass 18, count 2 2006.257.10:06:09.24#ibcon#read 5, iclass 18, count 2 2006.257.10:06:09.24#ibcon#about to read 6, iclass 18, count 2 2006.257.10:06:09.24#ibcon#read 6, iclass 18, count 2 2006.257.10:06:09.24#ibcon#end of sib2, iclass 18, count 2 2006.257.10:06:09.24#ibcon#*mode == 0, iclass 18, count 2 2006.257.10:06:09.24#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.10:06:09.24#ibcon#[25=AT04-07\r\n] 2006.257.10:06:09.24#ibcon#*before write, iclass 18, count 2 2006.257.10:06:09.24#ibcon#enter sib2, iclass 18, count 2 2006.257.10:06:09.24#ibcon#flushed, iclass 18, count 2 2006.257.10:06:09.24#ibcon#about to write, iclass 18, count 2 2006.257.10:06:09.24#ibcon#wrote, iclass 18, count 2 2006.257.10:06:09.24#ibcon#about to read 3, iclass 18, count 2 2006.257.10:06:09.27#ibcon#read 3, iclass 18, count 2 2006.257.10:06:09.27#ibcon#about to read 4, iclass 18, count 2 2006.257.10:06:09.27#ibcon#read 4, iclass 18, count 2 2006.257.10:06:09.27#ibcon#about to read 5, iclass 18, count 2 2006.257.10:06:09.27#ibcon#read 5, iclass 18, count 2 2006.257.10:06:09.27#ibcon#about to read 6, iclass 18, count 2 2006.257.10:06:09.27#ibcon#read 6, iclass 18, count 2 2006.257.10:06:09.27#ibcon#end of sib2, iclass 18, count 2 2006.257.10:06:09.27#ibcon#*after write, iclass 18, count 2 2006.257.10:06:09.27#ibcon#*before return 0, iclass 18, count 2 2006.257.10:06:09.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:09.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:09.27#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.10:06:09.27#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:09.27#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:09.39#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:09.39#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:09.39#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:06:09.39#ibcon#first serial, iclass 18, count 0 2006.257.10:06:09.39#ibcon#enter sib2, iclass 18, count 0 2006.257.10:06:09.39#ibcon#flushed, iclass 18, count 0 2006.257.10:06:09.39#ibcon#about to write, iclass 18, count 0 2006.257.10:06:09.39#ibcon#wrote, iclass 18, count 0 2006.257.10:06:09.39#ibcon#about to read 3, iclass 18, count 0 2006.257.10:06:09.41#ibcon#read 3, iclass 18, count 0 2006.257.10:06:09.41#ibcon#about to read 4, iclass 18, count 0 2006.257.10:06:09.41#ibcon#read 4, iclass 18, count 0 2006.257.10:06:09.41#ibcon#about to read 5, iclass 18, count 0 2006.257.10:06:09.41#ibcon#read 5, iclass 18, count 0 2006.257.10:06:09.41#ibcon#about to read 6, iclass 18, count 0 2006.257.10:06:09.41#ibcon#read 6, iclass 18, count 0 2006.257.10:06:09.41#ibcon#end of sib2, iclass 18, count 0 2006.257.10:06:09.41#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:06:09.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:06:09.41#ibcon#[25=USB\r\n] 2006.257.10:06:09.41#ibcon#*before write, iclass 18, count 0 2006.257.10:06:09.41#ibcon#enter sib2, iclass 18, count 0 2006.257.10:06:09.41#ibcon#flushed, iclass 18, count 0 2006.257.10:06:09.41#ibcon#about to write, iclass 18, count 0 2006.257.10:06:09.41#ibcon#wrote, iclass 18, count 0 2006.257.10:06:09.41#ibcon#about to read 3, iclass 18, count 0 2006.257.10:06:09.44#ibcon#read 3, iclass 18, count 0 2006.257.10:06:09.44#ibcon#about to read 4, iclass 18, count 0 2006.257.10:06:09.44#ibcon#read 4, iclass 18, count 0 2006.257.10:06:09.44#ibcon#about to read 5, iclass 18, count 0 2006.257.10:06:09.44#ibcon#read 5, iclass 18, count 0 2006.257.10:06:09.44#ibcon#about to read 6, iclass 18, count 0 2006.257.10:06:09.44#ibcon#read 6, iclass 18, count 0 2006.257.10:06:09.44#ibcon#end of sib2, iclass 18, count 0 2006.257.10:06:09.44#ibcon#*after write, iclass 18, count 0 2006.257.10:06:09.44#ibcon#*before return 0, iclass 18, count 0 2006.257.10:06:09.44#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:09.44#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:09.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:06:09.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:06:09.44$vck44/valo=5,734.99 2006.257.10:06:09.44#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.10:06:09.44#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.10:06:09.44#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:09.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:09.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:09.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:09.44#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:06:09.44#ibcon#first serial, iclass 20, count 0 2006.257.10:06:09.44#ibcon#enter sib2, iclass 20, count 0 2006.257.10:06:09.44#ibcon#flushed, iclass 20, count 0 2006.257.10:06:09.44#ibcon#about to write, iclass 20, count 0 2006.257.10:06:09.44#ibcon#wrote, iclass 20, count 0 2006.257.10:06:09.44#ibcon#about to read 3, iclass 20, count 0 2006.257.10:06:09.46#ibcon#read 3, iclass 20, count 0 2006.257.10:06:09.46#ibcon#about to read 4, iclass 20, count 0 2006.257.10:06:09.46#ibcon#read 4, iclass 20, count 0 2006.257.10:06:09.46#ibcon#about to read 5, iclass 20, count 0 2006.257.10:06:09.46#ibcon#read 5, iclass 20, count 0 2006.257.10:06:09.46#ibcon#about to read 6, iclass 20, count 0 2006.257.10:06:09.46#ibcon#read 6, iclass 20, count 0 2006.257.10:06:09.46#ibcon#end of sib2, iclass 20, count 0 2006.257.10:06:09.46#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:06:09.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:06:09.46#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:06:09.46#ibcon#*before write, iclass 20, count 0 2006.257.10:06:09.46#ibcon#enter sib2, iclass 20, count 0 2006.257.10:06:09.46#ibcon#flushed, iclass 20, count 0 2006.257.10:06:09.46#ibcon#about to write, iclass 20, count 0 2006.257.10:06:09.46#ibcon#wrote, iclass 20, count 0 2006.257.10:06:09.46#ibcon#about to read 3, iclass 20, count 0 2006.257.10:06:09.50#ibcon#read 3, iclass 20, count 0 2006.257.10:06:09.50#ibcon#about to read 4, iclass 20, count 0 2006.257.10:06:09.50#ibcon#read 4, iclass 20, count 0 2006.257.10:06:09.50#ibcon#about to read 5, iclass 20, count 0 2006.257.10:06:09.50#ibcon#read 5, iclass 20, count 0 2006.257.10:06:09.50#ibcon#about to read 6, iclass 20, count 0 2006.257.10:06:09.50#ibcon#read 6, iclass 20, count 0 2006.257.10:06:09.50#ibcon#end of sib2, iclass 20, count 0 2006.257.10:06:09.50#ibcon#*after write, iclass 20, count 0 2006.257.10:06:09.50#ibcon#*before return 0, iclass 20, count 0 2006.257.10:06:09.50#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:09.50#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:09.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:06:09.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:06:09.50$vck44/va=5,4 2006.257.10:06:09.50#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.10:06:09.50#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.10:06:09.50#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:09.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:09.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:09.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:09.56#ibcon#enter wrdev, iclass 22, count 2 2006.257.10:06:09.56#ibcon#first serial, iclass 22, count 2 2006.257.10:06:09.56#ibcon#enter sib2, iclass 22, count 2 2006.257.10:06:09.56#ibcon#flushed, iclass 22, count 2 2006.257.10:06:09.56#ibcon#about to write, iclass 22, count 2 2006.257.10:06:09.56#ibcon#wrote, iclass 22, count 2 2006.257.10:06:09.56#ibcon#about to read 3, iclass 22, count 2 2006.257.10:06:09.58#ibcon#read 3, iclass 22, count 2 2006.257.10:06:09.58#ibcon#about to read 4, iclass 22, count 2 2006.257.10:06:09.58#ibcon#read 4, iclass 22, count 2 2006.257.10:06:09.58#ibcon#about to read 5, iclass 22, count 2 2006.257.10:06:09.58#ibcon#read 5, iclass 22, count 2 2006.257.10:06:09.58#ibcon#about to read 6, iclass 22, count 2 2006.257.10:06:09.58#ibcon#read 6, iclass 22, count 2 2006.257.10:06:09.58#ibcon#end of sib2, iclass 22, count 2 2006.257.10:06:09.58#ibcon#*mode == 0, iclass 22, count 2 2006.257.10:06:09.58#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.10:06:09.58#ibcon#[25=AT05-04\r\n] 2006.257.10:06:09.58#ibcon#*before write, iclass 22, count 2 2006.257.10:06:09.58#ibcon#enter sib2, iclass 22, count 2 2006.257.10:06:09.58#ibcon#flushed, iclass 22, count 2 2006.257.10:06:09.58#ibcon#about to write, iclass 22, count 2 2006.257.10:06:09.58#ibcon#wrote, iclass 22, count 2 2006.257.10:06:09.58#ibcon#about to read 3, iclass 22, count 2 2006.257.10:06:09.61#ibcon#read 3, iclass 22, count 2 2006.257.10:06:09.61#ibcon#about to read 4, iclass 22, count 2 2006.257.10:06:09.61#ibcon#read 4, iclass 22, count 2 2006.257.10:06:09.61#ibcon#about to read 5, iclass 22, count 2 2006.257.10:06:09.61#ibcon#read 5, iclass 22, count 2 2006.257.10:06:09.61#ibcon#about to read 6, iclass 22, count 2 2006.257.10:06:09.61#ibcon#read 6, iclass 22, count 2 2006.257.10:06:09.61#ibcon#end of sib2, iclass 22, count 2 2006.257.10:06:09.61#ibcon#*after write, iclass 22, count 2 2006.257.10:06:09.61#ibcon#*before return 0, iclass 22, count 2 2006.257.10:06:09.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:09.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:09.61#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.10:06:09.61#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:09.61#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:09.73#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:09.73#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:09.73#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:06:09.73#ibcon#first serial, iclass 22, count 0 2006.257.10:06:09.73#ibcon#enter sib2, iclass 22, count 0 2006.257.10:06:09.73#ibcon#flushed, iclass 22, count 0 2006.257.10:06:09.73#ibcon#about to write, iclass 22, count 0 2006.257.10:06:09.73#ibcon#wrote, iclass 22, count 0 2006.257.10:06:09.73#ibcon#about to read 3, iclass 22, count 0 2006.257.10:06:09.75#ibcon#read 3, iclass 22, count 0 2006.257.10:06:09.75#ibcon#about to read 4, iclass 22, count 0 2006.257.10:06:09.75#ibcon#read 4, iclass 22, count 0 2006.257.10:06:09.75#ibcon#about to read 5, iclass 22, count 0 2006.257.10:06:09.75#ibcon#read 5, iclass 22, count 0 2006.257.10:06:09.75#ibcon#about to read 6, iclass 22, count 0 2006.257.10:06:09.75#ibcon#read 6, iclass 22, count 0 2006.257.10:06:09.75#ibcon#end of sib2, iclass 22, count 0 2006.257.10:06:09.75#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:06:09.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:06:09.75#ibcon#[25=USB\r\n] 2006.257.10:06:09.75#ibcon#*before write, iclass 22, count 0 2006.257.10:06:09.75#ibcon#enter sib2, iclass 22, count 0 2006.257.10:06:09.75#ibcon#flushed, iclass 22, count 0 2006.257.10:06:09.75#ibcon#about to write, iclass 22, count 0 2006.257.10:06:09.75#ibcon#wrote, iclass 22, count 0 2006.257.10:06:09.75#ibcon#about to read 3, iclass 22, count 0 2006.257.10:06:09.78#ibcon#read 3, iclass 22, count 0 2006.257.10:06:09.78#ibcon#about to read 4, iclass 22, count 0 2006.257.10:06:09.78#ibcon#read 4, iclass 22, count 0 2006.257.10:06:09.78#ibcon#about to read 5, iclass 22, count 0 2006.257.10:06:09.78#ibcon#read 5, iclass 22, count 0 2006.257.10:06:09.78#ibcon#about to read 6, iclass 22, count 0 2006.257.10:06:09.78#ibcon#read 6, iclass 22, count 0 2006.257.10:06:09.78#ibcon#end of sib2, iclass 22, count 0 2006.257.10:06:09.78#ibcon#*after write, iclass 22, count 0 2006.257.10:06:09.78#ibcon#*before return 0, iclass 22, count 0 2006.257.10:06:09.78#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:09.78#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:09.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:06:09.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:06:09.78$vck44/valo=6,814.99 2006.257.10:06:09.78#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.10:06:09.78#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.10:06:09.78#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:09.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:09.78#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:09.78#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:09.78#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:06:09.78#ibcon#first serial, iclass 24, count 0 2006.257.10:06:09.78#ibcon#enter sib2, iclass 24, count 0 2006.257.10:06:09.78#ibcon#flushed, iclass 24, count 0 2006.257.10:06:09.78#ibcon#about to write, iclass 24, count 0 2006.257.10:06:09.78#ibcon#wrote, iclass 24, count 0 2006.257.10:06:09.78#ibcon#about to read 3, iclass 24, count 0 2006.257.10:06:09.80#ibcon#read 3, iclass 24, count 0 2006.257.10:06:09.80#ibcon#about to read 4, iclass 24, count 0 2006.257.10:06:09.80#ibcon#read 4, iclass 24, count 0 2006.257.10:06:09.80#ibcon#about to read 5, iclass 24, count 0 2006.257.10:06:09.80#ibcon#read 5, iclass 24, count 0 2006.257.10:06:09.80#ibcon#about to read 6, iclass 24, count 0 2006.257.10:06:09.80#ibcon#read 6, iclass 24, count 0 2006.257.10:06:09.80#ibcon#end of sib2, iclass 24, count 0 2006.257.10:06:09.80#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:06:09.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:06:09.80#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:06:09.80#ibcon#*before write, iclass 24, count 0 2006.257.10:06:09.80#ibcon#enter sib2, iclass 24, count 0 2006.257.10:06:09.80#ibcon#flushed, iclass 24, count 0 2006.257.10:06:09.80#ibcon#about to write, iclass 24, count 0 2006.257.10:06:09.80#ibcon#wrote, iclass 24, count 0 2006.257.10:06:09.80#ibcon#about to read 3, iclass 24, count 0 2006.257.10:06:09.84#ibcon#read 3, iclass 24, count 0 2006.257.10:06:09.84#ibcon#about to read 4, iclass 24, count 0 2006.257.10:06:09.84#ibcon#read 4, iclass 24, count 0 2006.257.10:06:09.84#ibcon#about to read 5, iclass 24, count 0 2006.257.10:06:09.84#ibcon#read 5, iclass 24, count 0 2006.257.10:06:09.84#ibcon#about to read 6, iclass 24, count 0 2006.257.10:06:09.84#ibcon#read 6, iclass 24, count 0 2006.257.10:06:09.84#ibcon#end of sib2, iclass 24, count 0 2006.257.10:06:09.84#ibcon#*after write, iclass 24, count 0 2006.257.10:06:09.84#ibcon#*before return 0, iclass 24, count 0 2006.257.10:06:09.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:09.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:09.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:06:09.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:06:09.84$vck44/va=6,4 2006.257.10:06:09.84#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.10:06:09.84#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.10:06:09.84#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:09.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:09.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:09.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:09.90#ibcon#enter wrdev, iclass 26, count 2 2006.257.10:06:09.90#ibcon#first serial, iclass 26, count 2 2006.257.10:06:09.90#ibcon#enter sib2, iclass 26, count 2 2006.257.10:06:09.90#ibcon#flushed, iclass 26, count 2 2006.257.10:06:09.90#ibcon#about to write, iclass 26, count 2 2006.257.10:06:09.90#ibcon#wrote, iclass 26, count 2 2006.257.10:06:09.90#ibcon#about to read 3, iclass 26, count 2 2006.257.10:06:09.92#ibcon#read 3, iclass 26, count 2 2006.257.10:06:09.92#ibcon#about to read 4, iclass 26, count 2 2006.257.10:06:09.92#ibcon#read 4, iclass 26, count 2 2006.257.10:06:09.92#ibcon#about to read 5, iclass 26, count 2 2006.257.10:06:09.92#ibcon#read 5, iclass 26, count 2 2006.257.10:06:09.92#ibcon#about to read 6, iclass 26, count 2 2006.257.10:06:09.92#ibcon#read 6, iclass 26, count 2 2006.257.10:06:09.92#ibcon#end of sib2, iclass 26, count 2 2006.257.10:06:09.92#ibcon#*mode == 0, iclass 26, count 2 2006.257.10:06:09.92#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.10:06:09.92#ibcon#[25=AT06-04\r\n] 2006.257.10:06:09.92#ibcon#*before write, iclass 26, count 2 2006.257.10:06:09.92#ibcon#enter sib2, iclass 26, count 2 2006.257.10:06:09.92#ibcon#flushed, iclass 26, count 2 2006.257.10:06:09.92#ibcon#about to write, iclass 26, count 2 2006.257.10:06:09.92#ibcon#wrote, iclass 26, count 2 2006.257.10:06:09.92#ibcon#about to read 3, iclass 26, count 2 2006.257.10:06:09.95#ibcon#read 3, iclass 26, count 2 2006.257.10:06:09.95#ibcon#about to read 4, iclass 26, count 2 2006.257.10:06:09.95#ibcon#read 4, iclass 26, count 2 2006.257.10:06:09.95#ibcon#about to read 5, iclass 26, count 2 2006.257.10:06:09.95#ibcon#read 5, iclass 26, count 2 2006.257.10:06:09.95#ibcon#about to read 6, iclass 26, count 2 2006.257.10:06:09.95#ibcon#read 6, iclass 26, count 2 2006.257.10:06:09.95#ibcon#end of sib2, iclass 26, count 2 2006.257.10:06:09.95#ibcon#*after write, iclass 26, count 2 2006.257.10:06:09.95#ibcon#*before return 0, iclass 26, count 2 2006.257.10:06:09.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:09.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:09.95#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.10:06:09.95#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:09.95#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:10.07#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:10.07#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:10.07#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:06:10.07#ibcon#first serial, iclass 26, count 0 2006.257.10:06:10.07#ibcon#enter sib2, iclass 26, count 0 2006.257.10:06:10.07#ibcon#flushed, iclass 26, count 0 2006.257.10:06:10.07#ibcon#about to write, iclass 26, count 0 2006.257.10:06:10.07#ibcon#wrote, iclass 26, count 0 2006.257.10:06:10.07#ibcon#about to read 3, iclass 26, count 0 2006.257.10:06:10.09#ibcon#read 3, iclass 26, count 0 2006.257.10:06:10.09#ibcon#about to read 4, iclass 26, count 0 2006.257.10:06:10.09#ibcon#read 4, iclass 26, count 0 2006.257.10:06:10.09#ibcon#about to read 5, iclass 26, count 0 2006.257.10:06:10.09#ibcon#read 5, iclass 26, count 0 2006.257.10:06:10.09#ibcon#about to read 6, iclass 26, count 0 2006.257.10:06:10.09#ibcon#read 6, iclass 26, count 0 2006.257.10:06:10.09#ibcon#end of sib2, iclass 26, count 0 2006.257.10:06:10.09#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:06:10.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:06:10.09#ibcon#[25=USB\r\n] 2006.257.10:06:10.09#ibcon#*before write, iclass 26, count 0 2006.257.10:06:10.09#ibcon#enter sib2, iclass 26, count 0 2006.257.10:06:10.09#ibcon#flushed, iclass 26, count 0 2006.257.10:06:10.09#ibcon#about to write, iclass 26, count 0 2006.257.10:06:10.09#ibcon#wrote, iclass 26, count 0 2006.257.10:06:10.09#ibcon#about to read 3, iclass 26, count 0 2006.257.10:06:10.12#ibcon#read 3, iclass 26, count 0 2006.257.10:06:10.12#ibcon#about to read 4, iclass 26, count 0 2006.257.10:06:10.12#ibcon#read 4, iclass 26, count 0 2006.257.10:06:10.12#ibcon#about to read 5, iclass 26, count 0 2006.257.10:06:10.12#ibcon#read 5, iclass 26, count 0 2006.257.10:06:10.12#ibcon#about to read 6, iclass 26, count 0 2006.257.10:06:10.12#ibcon#read 6, iclass 26, count 0 2006.257.10:06:10.12#ibcon#end of sib2, iclass 26, count 0 2006.257.10:06:10.12#ibcon#*after write, iclass 26, count 0 2006.257.10:06:10.12#ibcon#*before return 0, iclass 26, count 0 2006.257.10:06:10.12#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:10.12#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:10.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:06:10.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:06:10.12$vck44/valo=7,864.99 2006.257.10:06:10.12#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.10:06:10.12#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.10:06:10.12#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:10.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:10.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:10.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:10.12#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:06:10.12#ibcon#first serial, iclass 28, count 0 2006.257.10:06:10.12#ibcon#enter sib2, iclass 28, count 0 2006.257.10:06:10.12#ibcon#flushed, iclass 28, count 0 2006.257.10:06:10.12#ibcon#about to write, iclass 28, count 0 2006.257.10:06:10.12#ibcon#wrote, iclass 28, count 0 2006.257.10:06:10.12#ibcon#about to read 3, iclass 28, count 0 2006.257.10:06:10.14#ibcon#read 3, iclass 28, count 0 2006.257.10:06:10.14#ibcon#about to read 4, iclass 28, count 0 2006.257.10:06:10.14#ibcon#read 4, iclass 28, count 0 2006.257.10:06:10.14#ibcon#about to read 5, iclass 28, count 0 2006.257.10:06:10.14#ibcon#read 5, iclass 28, count 0 2006.257.10:06:10.14#ibcon#about to read 6, iclass 28, count 0 2006.257.10:06:10.14#ibcon#read 6, iclass 28, count 0 2006.257.10:06:10.14#ibcon#end of sib2, iclass 28, count 0 2006.257.10:06:10.14#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:06:10.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:06:10.14#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:06:10.14#ibcon#*before write, iclass 28, count 0 2006.257.10:06:10.14#ibcon#enter sib2, iclass 28, count 0 2006.257.10:06:10.14#ibcon#flushed, iclass 28, count 0 2006.257.10:06:10.14#ibcon#about to write, iclass 28, count 0 2006.257.10:06:10.14#ibcon#wrote, iclass 28, count 0 2006.257.10:06:10.14#ibcon#about to read 3, iclass 28, count 0 2006.257.10:06:10.18#ibcon#read 3, iclass 28, count 0 2006.257.10:06:10.18#ibcon#about to read 4, iclass 28, count 0 2006.257.10:06:10.18#ibcon#read 4, iclass 28, count 0 2006.257.10:06:10.18#ibcon#about to read 5, iclass 28, count 0 2006.257.10:06:10.18#ibcon#read 5, iclass 28, count 0 2006.257.10:06:10.18#ibcon#about to read 6, iclass 28, count 0 2006.257.10:06:10.18#ibcon#read 6, iclass 28, count 0 2006.257.10:06:10.18#ibcon#end of sib2, iclass 28, count 0 2006.257.10:06:10.18#ibcon#*after write, iclass 28, count 0 2006.257.10:06:10.18#ibcon#*before return 0, iclass 28, count 0 2006.257.10:06:10.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:10.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:10.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:06:10.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:06:10.18$vck44/va=7,4 2006.257.10:06:10.18#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.10:06:10.18#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.10:06:10.18#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:10.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:10.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:10.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:10.24#ibcon#enter wrdev, iclass 30, count 2 2006.257.10:06:10.24#ibcon#first serial, iclass 30, count 2 2006.257.10:06:10.24#ibcon#enter sib2, iclass 30, count 2 2006.257.10:06:10.24#ibcon#flushed, iclass 30, count 2 2006.257.10:06:10.24#ibcon#about to write, iclass 30, count 2 2006.257.10:06:10.24#ibcon#wrote, iclass 30, count 2 2006.257.10:06:10.24#ibcon#about to read 3, iclass 30, count 2 2006.257.10:06:10.26#ibcon#read 3, iclass 30, count 2 2006.257.10:06:10.26#ibcon#about to read 4, iclass 30, count 2 2006.257.10:06:10.26#ibcon#read 4, iclass 30, count 2 2006.257.10:06:10.26#ibcon#about to read 5, iclass 30, count 2 2006.257.10:06:10.26#ibcon#read 5, iclass 30, count 2 2006.257.10:06:10.26#ibcon#about to read 6, iclass 30, count 2 2006.257.10:06:10.26#ibcon#read 6, iclass 30, count 2 2006.257.10:06:10.26#ibcon#end of sib2, iclass 30, count 2 2006.257.10:06:10.26#ibcon#*mode == 0, iclass 30, count 2 2006.257.10:06:10.26#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.10:06:10.26#ibcon#[25=AT07-04\r\n] 2006.257.10:06:10.26#ibcon#*before write, iclass 30, count 2 2006.257.10:06:10.26#ibcon#enter sib2, iclass 30, count 2 2006.257.10:06:10.26#ibcon#flushed, iclass 30, count 2 2006.257.10:06:10.26#ibcon#about to write, iclass 30, count 2 2006.257.10:06:10.26#ibcon#wrote, iclass 30, count 2 2006.257.10:06:10.26#ibcon#about to read 3, iclass 30, count 2 2006.257.10:06:10.29#ibcon#read 3, iclass 30, count 2 2006.257.10:06:10.29#ibcon#about to read 4, iclass 30, count 2 2006.257.10:06:10.29#ibcon#read 4, iclass 30, count 2 2006.257.10:06:10.29#ibcon#about to read 5, iclass 30, count 2 2006.257.10:06:10.29#ibcon#read 5, iclass 30, count 2 2006.257.10:06:10.29#ibcon#about to read 6, iclass 30, count 2 2006.257.10:06:10.29#ibcon#read 6, iclass 30, count 2 2006.257.10:06:10.29#ibcon#end of sib2, iclass 30, count 2 2006.257.10:06:10.29#ibcon#*after write, iclass 30, count 2 2006.257.10:06:10.29#ibcon#*before return 0, iclass 30, count 2 2006.257.10:06:10.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:10.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:10.29#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.10:06:10.29#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:10.29#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:10.41#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:10.41#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:10.41#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:06:10.41#ibcon#first serial, iclass 30, count 0 2006.257.10:06:10.41#ibcon#enter sib2, iclass 30, count 0 2006.257.10:06:10.41#ibcon#flushed, iclass 30, count 0 2006.257.10:06:10.41#ibcon#about to write, iclass 30, count 0 2006.257.10:06:10.41#ibcon#wrote, iclass 30, count 0 2006.257.10:06:10.41#ibcon#about to read 3, iclass 30, count 0 2006.257.10:06:10.43#ibcon#read 3, iclass 30, count 0 2006.257.10:06:10.43#ibcon#about to read 4, iclass 30, count 0 2006.257.10:06:10.43#ibcon#read 4, iclass 30, count 0 2006.257.10:06:10.43#ibcon#about to read 5, iclass 30, count 0 2006.257.10:06:10.43#ibcon#read 5, iclass 30, count 0 2006.257.10:06:10.43#ibcon#about to read 6, iclass 30, count 0 2006.257.10:06:10.43#ibcon#read 6, iclass 30, count 0 2006.257.10:06:10.43#ibcon#end of sib2, iclass 30, count 0 2006.257.10:06:10.43#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:06:10.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:06:10.43#ibcon#[25=USB\r\n] 2006.257.10:06:10.43#ibcon#*before write, iclass 30, count 0 2006.257.10:06:10.43#ibcon#enter sib2, iclass 30, count 0 2006.257.10:06:10.43#ibcon#flushed, iclass 30, count 0 2006.257.10:06:10.43#ibcon#about to write, iclass 30, count 0 2006.257.10:06:10.43#ibcon#wrote, iclass 30, count 0 2006.257.10:06:10.43#ibcon#about to read 3, iclass 30, count 0 2006.257.10:06:10.46#ibcon#read 3, iclass 30, count 0 2006.257.10:06:10.46#ibcon#about to read 4, iclass 30, count 0 2006.257.10:06:10.46#ibcon#read 4, iclass 30, count 0 2006.257.10:06:10.46#ibcon#about to read 5, iclass 30, count 0 2006.257.10:06:10.46#ibcon#read 5, iclass 30, count 0 2006.257.10:06:10.46#ibcon#about to read 6, iclass 30, count 0 2006.257.10:06:10.46#ibcon#read 6, iclass 30, count 0 2006.257.10:06:10.46#ibcon#end of sib2, iclass 30, count 0 2006.257.10:06:10.46#ibcon#*after write, iclass 30, count 0 2006.257.10:06:10.46#ibcon#*before return 0, iclass 30, count 0 2006.257.10:06:10.46#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:10.46#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:10.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:06:10.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:06:10.46$vck44/valo=8,884.99 2006.257.10:06:10.46#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.10:06:10.46#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.10:06:10.46#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:10.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:10.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:10.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:10.46#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:06:10.46#ibcon#first serial, iclass 32, count 0 2006.257.10:06:10.46#ibcon#enter sib2, iclass 32, count 0 2006.257.10:06:10.46#ibcon#flushed, iclass 32, count 0 2006.257.10:06:10.46#ibcon#about to write, iclass 32, count 0 2006.257.10:06:10.46#ibcon#wrote, iclass 32, count 0 2006.257.10:06:10.46#ibcon#about to read 3, iclass 32, count 0 2006.257.10:06:10.48#ibcon#read 3, iclass 32, count 0 2006.257.10:06:10.48#ibcon#about to read 4, iclass 32, count 0 2006.257.10:06:10.48#ibcon#read 4, iclass 32, count 0 2006.257.10:06:10.48#ibcon#about to read 5, iclass 32, count 0 2006.257.10:06:10.48#ibcon#read 5, iclass 32, count 0 2006.257.10:06:10.48#ibcon#about to read 6, iclass 32, count 0 2006.257.10:06:10.48#ibcon#read 6, iclass 32, count 0 2006.257.10:06:10.48#ibcon#end of sib2, iclass 32, count 0 2006.257.10:06:10.48#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:06:10.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:06:10.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:06:10.48#ibcon#*before write, iclass 32, count 0 2006.257.10:06:10.48#ibcon#enter sib2, iclass 32, count 0 2006.257.10:06:10.48#ibcon#flushed, iclass 32, count 0 2006.257.10:06:10.48#ibcon#about to write, iclass 32, count 0 2006.257.10:06:10.48#ibcon#wrote, iclass 32, count 0 2006.257.10:06:10.48#ibcon#about to read 3, iclass 32, count 0 2006.257.10:06:10.52#ibcon#read 3, iclass 32, count 0 2006.257.10:06:10.52#ibcon#about to read 4, iclass 32, count 0 2006.257.10:06:10.52#ibcon#read 4, iclass 32, count 0 2006.257.10:06:10.52#ibcon#about to read 5, iclass 32, count 0 2006.257.10:06:10.52#ibcon#read 5, iclass 32, count 0 2006.257.10:06:10.52#ibcon#about to read 6, iclass 32, count 0 2006.257.10:06:10.52#ibcon#read 6, iclass 32, count 0 2006.257.10:06:10.52#ibcon#end of sib2, iclass 32, count 0 2006.257.10:06:10.52#ibcon#*after write, iclass 32, count 0 2006.257.10:06:10.52#ibcon#*before return 0, iclass 32, count 0 2006.257.10:06:10.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:10.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:10.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:06:10.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:06:10.52$vck44/va=8,4 2006.257.10:06:10.52#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.10:06:10.52#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.10:06:10.52#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:10.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:06:10.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:06:10.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:06:10.58#ibcon#enter wrdev, iclass 34, count 2 2006.257.10:06:10.58#ibcon#first serial, iclass 34, count 2 2006.257.10:06:10.58#ibcon#enter sib2, iclass 34, count 2 2006.257.10:06:10.58#ibcon#flushed, iclass 34, count 2 2006.257.10:06:10.58#ibcon#about to write, iclass 34, count 2 2006.257.10:06:10.58#ibcon#wrote, iclass 34, count 2 2006.257.10:06:10.58#ibcon#about to read 3, iclass 34, count 2 2006.257.10:06:10.60#ibcon#read 3, iclass 34, count 2 2006.257.10:06:10.60#ibcon#about to read 4, iclass 34, count 2 2006.257.10:06:10.60#ibcon#read 4, iclass 34, count 2 2006.257.10:06:10.60#ibcon#about to read 5, iclass 34, count 2 2006.257.10:06:10.60#ibcon#read 5, iclass 34, count 2 2006.257.10:06:10.60#ibcon#about to read 6, iclass 34, count 2 2006.257.10:06:10.60#ibcon#read 6, iclass 34, count 2 2006.257.10:06:10.60#ibcon#end of sib2, iclass 34, count 2 2006.257.10:06:10.60#ibcon#*mode == 0, iclass 34, count 2 2006.257.10:06:10.60#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.10:06:10.60#ibcon#[25=AT08-04\r\n] 2006.257.10:06:10.60#ibcon#*before write, iclass 34, count 2 2006.257.10:06:10.60#ibcon#enter sib2, iclass 34, count 2 2006.257.10:06:10.60#ibcon#flushed, iclass 34, count 2 2006.257.10:06:10.60#ibcon#about to write, iclass 34, count 2 2006.257.10:06:10.60#ibcon#wrote, iclass 34, count 2 2006.257.10:06:10.60#ibcon#about to read 3, iclass 34, count 2 2006.257.10:06:10.63#ibcon#read 3, iclass 34, count 2 2006.257.10:06:10.63#ibcon#about to read 4, iclass 34, count 2 2006.257.10:06:10.63#ibcon#read 4, iclass 34, count 2 2006.257.10:06:10.63#ibcon#about to read 5, iclass 34, count 2 2006.257.10:06:10.63#ibcon#read 5, iclass 34, count 2 2006.257.10:06:10.63#ibcon#about to read 6, iclass 34, count 2 2006.257.10:06:10.63#ibcon#read 6, iclass 34, count 2 2006.257.10:06:10.63#ibcon#end of sib2, iclass 34, count 2 2006.257.10:06:10.63#ibcon#*after write, iclass 34, count 2 2006.257.10:06:10.63#ibcon#*before return 0, iclass 34, count 2 2006.257.10:06:10.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:06:10.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:06:10.63#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.10:06:10.63#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:10.63#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:06:10.75#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:06:10.75#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:06:10.75#ibcon#enter wrdev, iclass 34, count 0 2006.257.10:06:10.75#ibcon#first serial, iclass 34, count 0 2006.257.10:06:10.75#ibcon#enter sib2, iclass 34, count 0 2006.257.10:06:10.75#ibcon#flushed, iclass 34, count 0 2006.257.10:06:10.75#ibcon#about to write, iclass 34, count 0 2006.257.10:06:10.75#ibcon#wrote, iclass 34, count 0 2006.257.10:06:10.75#ibcon#about to read 3, iclass 34, count 0 2006.257.10:06:10.77#ibcon#read 3, iclass 34, count 0 2006.257.10:06:10.77#ibcon#about to read 4, iclass 34, count 0 2006.257.10:06:10.77#ibcon#read 4, iclass 34, count 0 2006.257.10:06:10.77#ibcon#about to read 5, iclass 34, count 0 2006.257.10:06:10.77#ibcon#read 5, iclass 34, count 0 2006.257.10:06:10.77#ibcon#about to read 6, iclass 34, count 0 2006.257.10:06:10.77#ibcon#read 6, iclass 34, count 0 2006.257.10:06:10.77#ibcon#end of sib2, iclass 34, count 0 2006.257.10:06:10.77#ibcon#*mode == 0, iclass 34, count 0 2006.257.10:06:10.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.10:06:10.77#ibcon#[25=USB\r\n] 2006.257.10:06:10.77#ibcon#*before write, iclass 34, count 0 2006.257.10:06:10.77#ibcon#enter sib2, iclass 34, count 0 2006.257.10:06:10.77#ibcon#flushed, iclass 34, count 0 2006.257.10:06:10.77#ibcon#about to write, iclass 34, count 0 2006.257.10:06:10.77#ibcon#wrote, iclass 34, count 0 2006.257.10:06:10.77#ibcon#about to read 3, iclass 34, count 0 2006.257.10:06:10.80#ibcon#read 3, iclass 34, count 0 2006.257.10:06:10.80#ibcon#about to read 4, iclass 34, count 0 2006.257.10:06:10.80#ibcon#read 4, iclass 34, count 0 2006.257.10:06:10.80#ibcon#about to read 5, iclass 34, count 0 2006.257.10:06:10.80#ibcon#read 5, iclass 34, count 0 2006.257.10:06:10.80#ibcon#about to read 6, iclass 34, count 0 2006.257.10:06:10.80#ibcon#read 6, iclass 34, count 0 2006.257.10:06:10.80#ibcon#end of sib2, iclass 34, count 0 2006.257.10:06:10.80#ibcon#*after write, iclass 34, count 0 2006.257.10:06:10.80#ibcon#*before return 0, iclass 34, count 0 2006.257.10:06:10.80#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:06:10.80#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:06:10.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.10:06:10.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.10:06:10.80$vck44/vblo=1,629.99 2006.257.10:06:10.80#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.10:06:10.80#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.10:06:10.80#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:10.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:06:10.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:06:10.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:06:10.80#ibcon#enter wrdev, iclass 36, count 0 2006.257.10:06:10.80#ibcon#first serial, iclass 36, count 0 2006.257.10:06:10.80#ibcon#enter sib2, iclass 36, count 0 2006.257.10:06:10.80#ibcon#flushed, iclass 36, count 0 2006.257.10:06:10.80#ibcon#about to write, iclass 36, count 0 2006.257.10:06:10.80#ibcon#wrote, iclass 36, count 0 2006.257.10:06:10.80#ibcon#about to read 3, iclass 36, count 0 2006.257.10:06:10.82#ibcon#read 3, iclass 36, count 0 2006.257.10:06:10.82#ibcon#about to read 4, iclass 36, count 0 2006.257.10:06:10.82#ibcon#read 4, iclass 36, count 0 2006.257.10:06:10.82#ibcon#about to read 5, iclass 36, count 0 2006.257.10:06:10.82#ibcon#read 5, iclass 36, count 0 2006.257.10:06:10.82#ibcon#about to read 6, iclass 36, count 0 2006.257.10:06:10.82#ibcon#read 6, iclass 36, count 0 2006.257.10:06:10.82#ibcon#end of sib2, iclass 36, count 0 2006.257.10:06:10.82#ibcon#*mode == 0, iclass 36, count 0 2006.257.10:06:10.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.10:06:10.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:06:10.82#ibcon#*before write, iclass 36, count 0 2006.257.10:06:10.82#ibcon#enter sib2, iclass 36, count 0 2006.257.10:06:10.82#ibcon#flushed, iclass 36, count 0 2006.257.10:06:10.82#ibcon#about to write, iclass 36, count 0 2006.257.10:06:10.82#ibcon#wrote, iclass 36, count 0 2006.257.10:06:10.82#ibcon#about to read 3, iclass 36, count 0 2006.257.10:06:10.86#ibcon#read 3, iclass 36, count 0 2006.257.10:06:10.86#ibcon#about to read 4, iclass 36, count 0 2006.257.10:06:10.86#ibcon#read 4, iclass 36, count 0 2006.257.10:06:10.86#ibcon#about to read 5, iclass 36, count 0 2006.257.10:06:10.86#ibcon#read 5, iclass 36, count 0 2006.257.10:06:10.86#ibcon#about to read 6, iclass 36, count 0 2006.257.10:06:10.86#ibcon#read 6, iclass 36, count 0 2006.257.10:06:10.86#ibcon#end of sib2, iclass 36, count 0 2006.257.10:06:10.86#ibcon#*after write, iclass 36, count 0 2006.257.10:06:10.86#ibcon#*before return 0, iclass 36, count 0 2006.257.10:06:10.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:06:10.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:06:10.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.10:06:10.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.10:06:10.86$vck44/vb=1,4 2006.257.10:06:10.86#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.10:06:10.86#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.10:06:10.86#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:10.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:06:10.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:06:10.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:06:10.86#ibcon#enter wrdev, iclass 38, count 2 2006.257.10:06:10.86#ibcon#first serial, iclass 38, count 2 2006.257.10:06:10.86#ibcon#enter sib2, iclass 38, count 2 2006.257.10:06:10.86#ibcon#flushed, iclass 38, count 2 2006.257.10:06:10.86#ibcon#about to write, iclass 38, count 2 2006.257.10:06:10.86#ibcon#wrote, iclass 38, count 2 2006.257.10:06:10.86#ibcon#about to read 3, iclass 38, count 2 2006.257.10:06:10.88#ibcon#read 3, iclass 38, count 2 2006.257.10:06:10.88#ibcon#about to read 4, iclass 38, count 2 2006.257.10:06:10.88#ibcon#read 4, iclass 38, count 2 2006.257.10:06:10.88#ibcon#about to read 5, iclass 38, count 2 2006.257.10:06:10.88#ibcon#read 5, iclass 38, count 2 2006.257.10:06:10.88#ibcon#about to read 6, iclass 38, count 2 2006.257.10:06:10.88#ibcon#read 6, iclass 38, count 2 2006.257.10:06:10.88#ibcon#end of sib2, iclass 38, count 2 2006.257.10:06:10.88#ibcon#*mode == 0, iclass 38, count 2 2006.257.10:06:10.88#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.10:06:10.88#ibcon#[27=AT01-04\r\n] 2006.257.10:06:10.88#ibcon#*before write, iclass 38, count 2 2006.257.10:06:10.88#ibcon#enter sib2, iclass 38, count 2 2006.257.10:06:10.88#ibcon#flushed, iclass 38, count 2 2006.257.10:06:10.88#ibcon#about to write, iclass 38, count 2 2006.257.10:06:10.88#ibcon#wrote, iclass 38, count 2 2006.257.10:06:10.88#ibcon#about to read 3, iclass 38, count 2 2006.257.10:06:10.91#ibcon#read 3, iclass 38, count 2 2006.257.10:06:10.91#ibcon#about to read 4, iclass 38, count 2 2006.257.10:06:10.91#ibcon#read 4, iclass 38, count 2 2006.257.10:06:10.91#ibcon#about to read 5, iclass 38, count 2 2006.257.10:06:10.91#ibcon#read 5, iclass 38, count 2 2006.257.10:06:10.91#ibcon#about to read 6, iclass 38, count 2 2006.257.10:06:10.91#ibcon#read 6, iclass 38, count 2 2006.257.10:06:10.91#ibcon#end of sib2, iclass 38, count 2 2006.257.10:06:10.91#ibcon#*after write, iclass 38, count 2 2006.257.10:06:10.91#ibcon#*before return 0, iclass 38, count 2 2006.257.10:06:10.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:06:10.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:06:10.91#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.10:06:10.91#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:10.91#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:06:11.03#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:06:11.03#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:06:11.03#ibcon#enter wrdev, iclass 38, count 0 2006.257.10:06:11.03#ibcon#first serial, iclass 38, count 0 2006.257.10:06:11.03#ibcon#enter sib2, iclass 38, count 0 2006.257.10:06:11.03#ibcon#flushed, iclass 38, count 0 2006.257.10:06:11.03#ibcon#about to write, iclass 38, count 0 2006.257.10:06:11.03#ibcon#wrote, iclass 38, count 0 2006.257.10:06:11.03#ibcon#about to read 3, iclass 38, count 0 2006.257.10:06:11.05#ibcon#read 3, iclass 38, count 0 2006.257.10:06:11.05#ibcon#about to read 4, iclass 38, count 0 2006.257.10:06:11.05#ibcon#read 4, iclass 38, count 0 2006.257.10:06:11.05#ibcon#about to read 5, iclass 38, count 0 2006.257.10:06:11.05#ibcon#read 5, iclass 38, count 0 2006.257.10:06:11.05#ibcon#about to read 6, iclass 38, count 0 2006.257.10:06:11.05#ibcon#read 6, iclass 38, count 0 2006.257.10:06:11.05#ibcon#end of sib2, iclass 38, count 0 2006.257.10:06:11.05#ibcon#*mode == 0, iclass 38, count 0 2006.257.10:06:11.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.10:06:11.05#ibcon#[27=USB\r\n] 2006.257.10:06:11.05#ibcon#*before write, iclass 38, count 0 2006.257.10:06:11.05#ibcon#enter sib2, iclass 38, count 0 2006.257.10:06:11.05#ibcon#flushed, iclass 38, count 0 2006.257.10:06:11.05#ibcon#about to write, iclass 38, count 0 2006.257.10:06:11.05#ibcon#wrote, iclass 38, count 0 2006.257.10:06:11.05#ibcon#about to read 3, iclass 38, count 0 2006.257.10:06:11.08#ibcon#read 3, iclass 38, count 0 2006.257.10:06:11.08#ibcon#about to read 4, iclass 38, count 0 2006.257.10:06:11.08#ibcon#read 4, iclass 38, count 0 2006.257.10:06:11.08#ibcon#about to read 5, iclass 38, count 0 2006.257.10:06:11.08#ibcon#read 5, iclass 38, count 0 2006.257.10:06:11.08#ibcon#about to read 6, iclass 38, count 0 2006.257.10:06:11.08#ibcon#read 6, iclass 38, count 0 2006.257.10:06:11.08#ibcon#end of sib2, iclass 38, count 0 2006.257.10:06:11.08#ibcon#*after write, iclass 38, count 0 2006.257.10:06:11.08#ibcon#*before return 0, iclass 38, count 0 2006.257.10:06:11.08#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:06:11.08#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:06:11.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.10:06:11.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.10:06:11.08$vck44/vblo=2,634.99 2006.257.10:06:11.08#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.10:06:11.08#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.10:06:11.08#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:11.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:11.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:11.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:11.08#ibcon#enter wrdev, iclass 40, count 0 2006.257.10:06:11.08#ibcon#first serial, iclass 40, count 0 2006.257.10:06:11.08#ibcon#enter sib2, iclass 40, count 0 2006.257.10:06:11.08#ibcon#flushed, iclass 40, count 0 2006.257.10:06:11.08#ibcon#about to write, iclass 40, count 0 2006.257.10:06:11.08#ibcon#wrote, iclass 40, count 0 2006.257.10:06:11.08#ibcon#about to read 3, iclass 40, count 0 2006.257.10:06:11.10#ibcon#read 3, iclass 40, count 0 2006.257.10:06:11.10#ibcon#about to read 4, iclass 40, count 0 2006.257.10:06:11.10#ibcon#read 4, iclass 40, count 0 2006.257.10:06:11.10#ibcon#about to read 5, iclass 40, count 0 2006.257.10:06:11.10#ibcon#read 5, iclass 40, count 0 2006.257.10:06:11.10#ibcon#about to read 6, iclass 40, count 0 2006.257.10:06:11.10#ibcon#read 6, iclass 40, count 0 2006.257.10:06:11.10#ibcon#end of sib2, iclass 40, count 0 2006.257.10:06:11.10#ibcon#*mode == 0, iclass 40, count 0 2006.257.10:06:11.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.10:06:11.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:06:11.10#ibcon#*before write, iclass 40, count 0 2006.257.10:06:11.10#ibcon#enter sib2, iclass 40, count 0 2006.257.10:06:11.10#ibcon#flushed, iclass 40, count 0 2006.257.10:06:11.10#ibcon#about to write, iclass 40, count 0 2006.257.10:06:11.10#ibcon#wrote, iclass 40, count 0 2006.257.10:06:11.10#ibcon#about to read 3, iclass 40, count 0 2006.257.10:06:11.14#ibcon#read 3, iclass 40, count 0 2006.257.10:06:11.14#ibcon#about to read 4, iclass 40, count 0 2006.257.10:06:11.14#ibcon#read 4, iclass 40, count 0 2006.257.10:06:11.14#ibcon#about to read 5, iclass 40, count 0 2006.257.10:06:11.14#ibcon#read 5, iclass 40, count 0 2006.257.10:06:11.14#ibcon#about to read 6, iclass 40, count 0 2006.257.10:06:11.14#ibcon#read 6, iclass 40, count 0 2006.257.10:06:11.14#ibcon#end of sib2, iclass 40, count 0 2006.257.10:06:11.14#ibcon#*after write, iclass 40, count 0 2006.257.10:06:11.14#ibcon#*before return 0, iclass 40, count 0 2006.257.10:06:11.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:11.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:06:11.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.10:06:11.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.10:06:11.14$vck44/vb=2,5 2006.257.10:06:11.14#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.10:06:11.14#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.10:06:11.14#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:11.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:11.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:11.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:11.20#ibcon#enter wrdev, iclass 4, count 2 2006.257.10:06:11.20#ibcon#first serial, iclass 4, count 2 2006.257.10:06:11.20#ibcon#enter sib2, iclass 4, count 2 2006.257.10:06:11.20#ibcon#flushed, iclass 4, count 2 2006.257.10:06:11.20#ibcon#about to write, iclass 4, count 2 2006.257.10:06:11.20#ibcon#wrote, iclass 4, count 2 2006.257.10:06:11.20#ibcon#about to read 3, iclass 4, count 2 2006.257.10:06:11.22#ibcon#read 3, iclass 4, count 2 2006.257.10:06:11.22#ibcon#about to read 4, iclass 4, count 2 2006.257.10:06:11.22#ibcon#read 4, iclass 4, count 2 2006.257.10:06:11.22#ibcon#about to read 5, iclass 4, count 2 2006.257.10:06:11.22#ibcon#read 5, iclass 4, count 2 2006.257.10:06:11.22#ibcon#about to read 6, iclass 4, count 2 2006.257.10:06:11.22#ibcon#read 6, iclass 4, count 2 2006.257.10:06:11.22#ibcon#end of sib2, iclass 4, count 2 2006.257.10:06:11.22#ibcon#*mode == 0, iclass 4, count 2 2006.257.10:06:11.22#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.10:06:11.22#ibcon#[27=AT02-05\r\n] 2006.257.10:06:11.22#ibcon#*before write, iclass 4, count 2 2006.257.10:06:11.22#ibcon#enter sib2, iclass 4, count 2 2006.257.10:06:11.22#ibcon#flushed, iclass 4, count 2 2006.257.10:06:11.22#ibcon#about to write, iclass 4, count 2 2006.257.10:06:11.22#ibcon#wrote, iclass 4, count 2 2006.257.10:06:11.22#ibcon#about to read 3, iclass 4, count 2 2006.257.10:06:11.25#ibcon#read 3, iclass 4, count 2 2006.257.10:06:11.34#ibcon#about to read 4, iclass 4, count 2 2006.257.10:06:11.34#ibcon#read 4, iclass 4, count 2 2006.257.10:06:11.34#ibcon#about to read 5, iclass 4, count 2 2006.257.10:06:11.34#ibcon#read 5, iclass 4, count 2 2006.257.10:06:11.34#ibcon#about to read 6, iclass 4, count 2 2006.257.10:06:11.34#ibcon#read 6, iclass 4, count 2 2006.257.10:06:11.34#ibcon#end of sib2, iclass 4, count 2 2006.257.10:06:11.34#ibcon#*after write, iclass 4, count 2 2006.257.10:06:11.34#ibcon#*before return 0, iclass 4, count 2 2006.257.10:06:11.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:11.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:06:11.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.10:06:11.34#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:11.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:11.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:11.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:11.46#ibcon#enter wrdev, iclass 4, count 0 2006.257.10:06:11.46#ibcon#first serial, iclass 4, count 0 2006.257.10:06:11.46#ibcon#enter sib2, iclass 4, count 0 2006.257.10:06:11.46#ibcon#flushed, iclass 4, count 0 2006.257.10:06:11.46#ibcon#about to write, iclass 4, count 0 2006.257.10:06:11.46#ibcon#wrote, iclass 4, count 0 2006.257.10:06:11.46#ibcon#about to read 3, iclass 4, count 0 2006.257.10:06:11.48#ibcon#read 3, iclass 4, count 0 2006.257.10:06:11.48#ibcon#about to read 4, iclass 4, count 0 2006.257.10:06:11.48#ibcon#read 4, iclass 4, count 0 2006.257.10:06:11.48#ibcon#about to read 5, iclass 4, count 0 2006.257.10:06:11.48#ibcon#read 5, iclass 4, count 0 2006.257.10:06:11.48#ibcon#about to read 6, iclass 4, count 0 2006.257.10:06:11.48#ibcon#read 6, iclass 4, count 0 2006.257.10:06:11.48#ibcon#end of sib2, iclass 4, count 0 2006.257.10:06:11.48#ibcon#*mode == 0, iclass 4, count 0 2006.257.10:06:11.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.10:06:11.48#ibcon#[27=USB\r\n] 2006.257.10:06:11.48#ibcon#*before write, iclass 4, count 0 2006.257.10:06:11.48#ibcon#enter sib2, iclass 4, count 0 2006.257.10:06:11.48#ibcon#flushed, iclass 4, count 0 2006.257.10:06:11.48#ibcon#about to write, iclass 4, count 0 2006.257.10:06:11.48#ibcon#wrote, iclass 4, count 0 2006.257.10:06:11.48#ibcon#about to read 3, iclass 4, count 0 2006.257.10:06:11.51#ibcon#read 3, iclass 4, count 0 2006.257.10:06:11.51#ibcon#about to read 4, iclass 4, count 0 2006.257.10:06:11.51#ibcon#read 4, iclass 4, count 0 2006.257.10:06:11.51#ibcon#about to read 5, iclass 4, count 0 2006.257.10:06:11.51#ibcon#read 5, iclass 4, count 0 2006.257.10:06:11.51#ibcon#about to read 6, iclass 4, count 0 2006.257.10:06:11.51#ibcon#read 6, iclass 4, count 0 2006.257.10:06:11.51#ibcon#end of sib2, iclass 4, count 0 2006.257.10:06:11.51#ibcon#*after write, iclass 4, count 0 2006.257.10:06:11.51#ibcon#*before return 0, iclass 4, count 0 2006.257.10:06:11.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:11.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:06:11.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.10:06:11.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.10:06:11.51$vck44/vblo=3,649.99 2006.257.10:06:11.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.10:06:11.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.10:06:11.51#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:11.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:11.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:11.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:11.51#ibcon#enter wrdev, iclass 6, count 0 2006.257.10:06:11.51#ibcon#first serial, iclass 6, count 0 2006.257.10:06:11.51#ibcon#enter sib2, iclass 6, count 0 2006.257.10:06:11.51#ibcon#flushed, iclass 6, count 0 2006.257.10:06:11.51#ibcon#about to write, iclass 6, count 0 2006.257.10:06:11.51#ibcon#wrote, iclass 6, count 0 2006.257.10:06:11.51#ibcon#about to read 3, iclass 6, count 0 2006.257.10:06:11.53#ibcon#read 3, iclass 6, count 0 2006.257.10:06:11.53#ibcon#about to read 4, iclass 6, count 0 2006.257.10:06:11.53#ibcon#read 4, iclass 6, count 0 2006.257.10:06:11.53#ibcon#about to read 5, iclass 6, count 0 2006.257.10:06:11.53#ibcon#read 5, iclass 6, count 0 2006.257.10:06:11.53#ibcon#about to read 6, iclass 6, count 0 2006.257.10:06:11.53#ibcon#read 6, iclass 6, count 0 2006.257.10:06:11.53#ibcon#end of sib2, iclass 6, count 0 2006.257.10:06:11.53#ibcon#*mode == 0, iclass 6, count 0 2006.257.10:06:11.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.10:06:11.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:06:11.53#ibcon#*before write, iclass 6, count 0 2006.257.10:06:11.53#ibcon#enter sib2, iclass 6, count 0 2006.257.10:06:11.53#ibcon#flushed, iclass 6, count 0 2006.257.10:06:11.53#ibcon#about to write, iclass 6, count 0 2006.257.10:06:11.53#ibcon#wrote, iclass 6, count 0 2006.257.10:06:11.53#ibcon#about to read 3, iclass 6, count 0 2006.257.10:06:11.57#ibcon#read 3, iclass 6, count 0 2006.257.10:06:11.57#ibcon#about to read 4, iclass 6, count 0 2006.257.10:06:11.57#ibcon#read 4, iclass 6, count 0 2006.257.10:06:11.57#ibcon#about to read 5, iclass 6, count 0 2006.257.10:06:11.57#ibcon#read 5, iclass 6, count 0 2006.257.10:06:11.57#ibcon#about to read 6, iclass 6, count 0 2006.257.10:06:11.57#ibcon#read 6, iclass 6, count 0 2006.257.10:06:11.57#ibcon#end of sib2, iclass 6, count 0 2006.257.10:06:11.57#ibcon#*after write, iclass 6, count 0 2006.257.10:06:11.57#ibcon#*before return 0, iclass 6, count 0 2006.257.10:06:11.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:11.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:06:11.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.10:06:11.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.10:06:11.57$vck44/vb=3,4 2006.257.10:06:11.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.10:06:11.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.10:06:11.57#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:11.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:11.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:11.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:11.63#ibcon#enter wrdev, iclass 10, count 2 2006.257.10:06:11.63#ibcon#first serial, iclass 10, count 2 2006.257.10:06:11.63#ibcon#enter sib2, iclass 10, count 2 2006.257.10:06:11.63#ibcon#flushed, iclass 10, count 2 2006.257.10:06:11.63#ibcon#about to write, iclass 10, count 2 2006.257.10:06:11.63#ibcon#wrote, iclass 10, count 2 2006.257.10:06:11.63#ibcon#about to read 3, iclass 10, count 2 2006.257.10:06:11.65#ibcon#read 3, iclass 10, count 2 2006.257.10:06:11.65#ibcon#about to read 4, iclass 10, count 2 2006.257.10:06:11.65#ibcon#read 4, iclass 10, count 2 2006.257.10:06:11.65#ibcon#about to read 5, iclass 10, count 2 2006.257.10:06:11.65#ibcon#read 5, iclass 10, count 2 2006.257.10:06:11.65#ibcon#about to read 6, iclass 10, count 2 2006.257.10:06:11.65#ibcon#read 6, iclass 10, count 2 2006.257.10:06:11.65#ibcon#end of sib2, iclass 10, count 2 2006.257.10:06:11.65#ibcon#*mode == 0, iclass 10, count 2 2006.257.10:06:11.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.10:06:11.65#ibcon#[27=AT03-04\r\n] 2006.257.10:06:11.65#ibcon#*before write, iclass 10, count 2 2006.257.10:06:11.65#ibcon#enter sib2, iclass 10, count 2 2006.257.10:06:11.65#ibcon#flushed, iclass 10, count 2 2006.257.10:06:11.65#ibcon#about to write, iclass 10, count 2 2006.257.10:06:11.65#ibcon#wrote, iclass 10, count 2 2006.257.10:06:11.65#ibcon#about to read 3, iclass 10, count 2 2006.257.10:06:11.68#ibcon#read 3, iclass 10, count 2 2006.257.10:06:11.68#ibcon#about to read 4, iclass 10, count 2 2006.257.10:06:11.68#ibcon#read 4, iclass 10, count 2 2006.257.10:06:11.68#ibcon#about to read 5, iclass 10, count 2 2006.257.10:06:11.68#ibcon#read 5, iclass 10, count 2 2006.257.10:06:11.68#ibcon#about to read 6, iclass 10, count 2 2006.257.10:06:11.68#ibcon#read 6, iclass 10, count 2 2006.257.10:06:11.68#ibcon#end of sib2, iclass 10, count 2 2006.257.10:06:11.68#ibcon#*after write, iclass 10, count 2 2006.257.10:06:11.68#ibcon#*before return 0, iclass 10, count 2 2006.257.10:06:11.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:11.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:06:11.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.10:06:11.68#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:11.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:11.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:11.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:11.80#ibcon#enter wrdev, iclass 10, count 0 2006.257.10:06:11.80#ibcon#first serial, iclass 10, count 0 2006.257.10:06:11.80#ibcon#enter sib2, iclass 10, count 0 2006.257.10:06:11.80#ibcon#flushed, iclass 10, count 0 2006.257.10:06:11.80#ibcon#about to write, iclass 10, count 0 2006.257.10:06:11.80#ibcon#wrote, iclass 10, count 0 2006.257.10:06:11.80#ibcon#about to read 3, iclass 10, count 0 2006.257.10:06:11.82#ibcon#read 3, iclass 10, count 0 2006.257.10:06:11.82#ibcon#about to read 4, iclass 10, count 0 2006.257.10:06:11.82#ibcon#read 4, iclass 10, count 0 2006.257.10:06:11.82#ibcon#about to read 5, iclass 10, count 0 2006.257.10:06:11.82#ibcon#read 5, iclass 10, count 0 2006.257.10:06:11.82#ibcon#about to read 6, iclass 10, count 0 2006.257.10:06:11.82#ibcon#read 6, iclass 10, count 0 2006.257.10:06:11.82#ibcon#end of sib2, iclass 10, count 0 2006.257.10:06:11.82#ibcon#*mode == 0, iclass 10, count 0 2006.257.10:06:11.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.10:06:11.82#ibcon#[27=USB\r\n] 2006.257.10:06:11.82#ibcon#*before write, iclass 10, count 0 2006.257.10:06:11.82#ibcon#enter sib2, iclass 10, count 0 2006.257.10:06:11.82#ibcon#flushed, iclass 10, count 0 2006.257.10:06:11.82#ibcon#about to write, iclass 10, count 0 2006.257.10:06:11.82#ibcon#wrote, iclass 10, count 0 2006.257.10:06:11.82#ibcon#about to read 3, iclass 10, count 0 2006.257.10:06:11.85#ibcon#read 3, iclass 10, count 0 2006.257.10:06:11.85#ibcon#about to read 4, iclass 10, count 0 2006.257.10:06:11.85#ibcon#read 4, iclass 10, count 0 2006.257.10:06:11.85#ibcon#about to read 5, iclass 10, count 0 2006.257.10:06:11.85#ibcon#read 5, iclass 10, count 0 2006.257.10:06:11.85#ibcon#about to read 6, iclass 10, count 0 2006.257.10:06:11.85#ibcon#read 6, iclass 10, count 0 2006.257.10:06:11.85#ibcon#end of sib2, iclass 10, count 0 2006.257.10:06:11.85#ibcon#*after write, iclass 10, count 0 2006.257.10:06:11.85#ibcon#*before return 0, iclass 10, count 0 2006.257.10:06:11.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:11.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:06:11.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.10:06:11.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.10:06:11.85$vck44/vblo=4,679.99 2006.257.10:06:11.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.10:06:11.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.10:06:11.85#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:11.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:11.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:11.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:11.85#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:06:11.85#ibcon#first serial, iclass 12, count 0 2006.257.10:06:11.85#ibcon#enter sib2, iclass 12, count 0 2006.257.10:06:11.85#ibcon#flushed, iclass 12, count 0 2006.257.10:06:11.85#ibcon#about to write, iclass 12, count 0 2006.257.10:06:11.85#ibcon#wrote, iclass 12, count 0 2006.257.10:06:11.85#ibcon#about to read 3, iclass 12, count 0 2006.257.10:06:11.87#ibcon#read 3, iclass 12, count 0 2006.257.10:06:11.87#ibcon#about to read 4, iclass 12, count 0 2006.257.10:06:11.87#ibcon#read 4, iclass 12, count 0 2006.257.10:06:11.87#ibcon#about to read 5, iclass 12, count 0 2006.257.10:06:11.87#ibcon#read 5, iclass 12, count 0 2006.257.10:06:11.87#ibcon#about to read 6, iclass 12, count 0 2006.257.10:06:11.87#ibcon#read 6, iclass 12, count 0 2006.257.10:06:11.87#ibcon#end of sib2, iclass 12, count 0 2006.257.10:06:11.87#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:06:11.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:06:11.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:06:11.87#ibcon#*before write, iclass 12, count 0 2006.257.10:06:11.87#ibcon#enter sib2, iclass 12, count 0 2006.257.10:06:11.87#ibcon#flushed, iclass 12, count 0 2006.257.10:06:11.87#ibcon#about to write, iclass 12, count 0 2006.257.10:06:11.87#ibcon#wrote, iclass 12, count 0 2006.257.10:06:11.87#ibcon#about to read 3, iclass 12, count 0 2006.257.10:06:11.91#ibcon#read 3, iclass 12, count 0 2006.257.10:06:11.91#ibcon#about to read 4, iclass 12, count 0 2006.257.10:06:11.91#ibcon#read 4, iclass 12, count 0 2006.257.10:06:11.91#ibcon#about to read 5, iclass 12, count 0 2006.257.10:06:11.91#ibcon#read 5, iclass 12, count 0 2006.257.10:06:11.91#ibcon#about to read 6, iclass 12, count 0 2006.257.10:06:11.91#ibcon#read 6, iclass 12, count 0 2006.257.10:06:11.91#ibcon#end of sib2, iclass 12, count 0 2006.257.10:06:11.91#ibcon#*after write, iclass 12, count 0 2006.257.10:06:11.91#ibcon#*before return 0, iclass 12, count 0 2006.257.10:06:11.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:11.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:06:11.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:06:11.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:06:11.91$vck44/vb=4,5 2006.257.10:06:11.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.10:06:11.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.10:06:11.91#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:11.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:11.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:11.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:11.97#ibcon#enter wrdev, iclass 14, count 2 2006.257.10:06:11.97#ibcon#first serial, iclass 14, count 2 2006.257.10:06:11.97#ibcon#enter sib2, iclass 14, count 2 2006.257.10:06:11.97#ibcon#flushed, iclass 14, count 2 2006.257.10:06:11.97#ibcon#about to write, iclass 14, count 2 2006.257.10:06:11.97#ibcon#wrote, iclass 14, count 2 2006.257.10:06:11.97#ibcon#about to read 3, iclass 14, count 2 2006.257.10:06:11.99#ibcon#read 3, iclass 14, count 2 2006.257.10:06:11.99#ibcon#about to read 4, iclass 14, count 2 2006.257.10:06:11.99#ibcon#read 4, iclass 14, count 2 2006.257.10:06:11.99#ibcon#about to read 5, iclass 14, count 2 2006.257.10:06:11.99#ibcon#read 5, iclass 14, count 2 2006.257.10:06:11.99#ibcon#about to read 6, iclass 14, count 2 2006.257.10:06:11.99#ibcon#read 6, iclass 14, count 2 2006.257.10:06:11.99#ibcon#end of sib2, iclass 14, count 2 2006.257.10:06:11.99#ibcon#*mode == 0, iclass 14, count 2 2006.257.10:06:11.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.10:06:11.99#ibcon#[27=AT04-05\r\n] 2006.257.10:06:11.99#ibcon#*before write, iclass 14, count 2 2006.257.10:06:11.99#ibcon#enter sib2, iclass 14, count 2 2006.257.10:06:11.99#ibcon#flushed, iclass 14, count 2 2006.257.10:06:11.99#ibcon#about to write, iclass 14, count 2 2006.257.10:06:11.99#ibcon#wrote, iclass 14, count 2 2006.257.10:06:11.99#ibcon#about to read 3, iclass 14, count 2 2006.257.10:06:12.02#ibcon#read 3, iclass 14, count 2 2006.257.10:06:12.02#ibcon#about to read 4, iclass 14, count 2 2006.257.10:06:12.02#ibcon#read 4, iclass 14, count 2 2006.257.10:06:12.02#ibcon#about to read 5, iclass 14, count 2 2006.257.10:06:12.02#ibcon#read 5, iclass 14, count 2 2006.257.10:06:12.02#ibcon#about to read 6, iclass 14, count 2 2006.257.10:06:12.02#ibcon#read 6, iclass 14, count 2 2006.257.10:06:12.02#ibcon#end of sib2, iclass 14, count 2 2006.257.10:06:12.02#ibcon#*after write, iclass 14, count 2 2006.257.10:06:12.02#ibcon#*before return 0, iclass 14, count 2 2006.257.10:06:12.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:12.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:06:12.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.10:06:12.02#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:12.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:12.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:12.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:12.14#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:06:12.14#ibcon#first serial, iclass 14, count 0 2006.257.10:06:12.14#ibcon#enter sib2, iclass 14, count 0 2006.257.10:06:12.14#ibcon#flushed, iclass 14, count 0 2006.257.10:06:12.14#ibcon#about to write, iclass 14, count 0 2006.257.10:06:12.14#ibcon#wrote, iclass 14, count 0 2006.257.10:06:12.14#ibcon#about to read 3, iclass 14, count 0 2006.257.10:06:12.16#ibcon#read 3, iclass 14, count 0 2006.257.10:06:12.16#ibcon#about to read 4, iclass 14, count 0 2006.257.10:06:12.16#ibcon#read 4, iclass 14, count 0 2006.257.10:06:12.16#ibcon#about to read 5, iclass 14, count 0 2006.257.10:06:12.16#ibcon#read 5, iclass 14, count 0 2006.257.10:06:12.16#ibcon#about to read 6, iclass 14, count 0 2006.257.10:06:12.16#ibcon#read 6, iclass 14, count 0 2006.257.10:06:12.16#ibcon#end of sib2, iclass 14, count 0 2006.257.10:06:12.16#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:06:12.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:06:12.16#ibcon#[27=USB\r\n] 2006.257.10:06:12.16#ibcon#*before write, iclass 14, count 0 2006.257.10:06:12.16#ibcon#enter sib2, iclass 14, count 0 2006.257.10:06:12.16#ibcon#flushed, iclass 14, count 0 2006.257.10:06:12.16#ibcon#about to write, iclass 14, count 0 2006.257.10:06:12.16#ibcon#wrote, iclass 14, count 0 2006.257.10:06:12.16#ibcon#about to read 3, iclass 14, count 0 2006.257.10:06:12.19#ibcon#read 3, iclass 14, count 0 2006.257.10:06:12.19#ibcon#about to read 4, iclass 14, count 0 2006.257.10:06:12.19#ibcon#read 4, iclass 14, count 0 2006.257.10:06:12.19#ibcon#about to read 5, iclass 14, count 0 2006.257.10:06:12.19#ibcon#read 5, iclass 14, count 0 2006.257.10:06:12.19#ibcon#about to read 6, iclass 14, count 0 2006.257.10:06:12.19#ibcon#read 6, iclass 14, count 0 2006.257.10:06:12.19#ibcon#end of sib2, iclass 14, count 0 2006.257.10:06:12.19#ibcon#*after write, iclass 14, count 0 2006.257.10:06:12.19#ibcon#*before return 0, iclass 14, count 0 2006.257.10:06:12.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:12.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:06:12.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:06:12.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:06:12.19$vck44/vblo=5,709.99 2006.257.10:06:12.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.10:06:12.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.10:06:12.19#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:12.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:12.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:12.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:12.19#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:06:12.19#ibcon#first serial, iclass 16, count 0 2006.257.10:06:12.19#ibcon#enter sib2, iclass 16, count 0 2006.257.10:06:12.19#ibcon#flushed, iclass 16, count 0 2006.257.10:06:12.19#ibcon#about to write, iclass 16, count 0 2006.257.10:06:12.19#ibcon#wrote, iclass 16, count 0 2006.257.10:06:12.19#ibcon#about to read 3, iclass 16, count 0 2006.257.10:06:12.21#ibcon#read 3, iclass 16, count 0 2006.257.10:06:12.21#ibcon#about to read 4, iclass 16, count 0 2006.257.10:06:12.21#ibcon#read 4, iclass 16, count 0 2006.257.10:06:12.21#ibcon#about to read 5, iclass 16, count 0 2006.257.10:06:12.21#ibcon#read 5, iclass 16, count 0 2006.257.10:06:12.21#ibcon#about to read 6, iclass 16, count 0 2006.257.10:06:12.21#ibcon#read 6, iclass 16, count 0 2006.257.10:06:12.21#ibcon#end of sib2, iclass 16, count 0 2006.257.10:06:12.21#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:06:12.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:06:12.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:06:12.21#ibcon#*before write, iclass 16, count 0 2006.257.10:06:12.21#ibcon#enter sib2, iclass 16, count 0 2006.257.10:06:12.21#ibcon#flushed, iclass 16, count 0 2006.257.10:06:12.21#ibcon#about to write, iclass 16, count 0 2006.257.10:06:12.21#ibcon#wrote, iclass 16, count 0 2006.257.10:06:12.21#ibcon#about to read 3, iclass 16, count 0 2006.257.10:06:12.25#ibcon#read 3, iclass 16, count 0 2006.257.10:06:12.25#ibcon#about to read 4, iclass 16, count 0 2006.257.10:06:12.25#ibcon#read 4, iclass 16, count 0 2006.257.10:06:12.25#ibcon#about to read 5, iclass 16, count 0 2006.257.10:06:12.25#ibcon#read 5, iclass 16, count 0 2006.257.10:06:12.25#ibcon#about to read 6, iclass 16, count 0 2006.257.10:06:12.25#ibcon#read 6, iclass 16, count 0 2006.257.10:06:12.25#ibcon#end of sib2, iclass 16, count 0 2006.257.10:06:12.25#ibcon#*after write, iclass 16, count 0 2006.257.10:06:12.25#ibcon#*before return 0, iclass 16, count 0 2006.257.10:06:12.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:12.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:06:12.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:06:12.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:06:12.25$vck44/vb=5,4 2006.257.10:06:12.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.10:06:12.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.10:06:12.25#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:12.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:12.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:12.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:12.31#ibcon#enter wrdev, iclass 18, count 2 2006.257.10:06:12.31#ibcon#first serial, iclass 18, count 2 2006.257.10:06:12.31#ibcon#enter sib2, iclass 18, count 2 2006.257.10:06:12.31#ibcon#flushed, iclass 18, count 2 2006.257.10:06:12.31#ibcon#about to write, iclass 18, count 2 2006.257.10:06:12.31#ibcon#wrote, iclass 18, count 2 2006.257.10:06:12.31#ibcon#about to read 3, iclass 18, count 2 2006.257.10:06:12.33#ibcon#read 3, iclass 18, count 2 2006.257.10:06:12.33#ibcon#about to read 4, iclass 18, count 2 2006.257.10:06:12.33#ibcon#read 4, iclass 18, count 2 2006.257.10:06:12.33#ibcon#about to read 5, iclass 18, count 2 2006.257.10:06:12.33#ibcon#read 5, iclass 18, count 2 2006.257.10:06:12.33#ibcon#about to read 6, iclass 18, count 2 2006.257.10:06:12.33#ibcon#read 6, iclass 18, count 2 2006.257.10:06:12.33#ibcon#end of sib2, iclass 18, count 2 2006.257.10:06:12.33#ibcon#*mode == 0, iclass 18, count 2 2006.257.10:06:12.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.10:06:12.33#ibcon#[27=AT05-04\r\n] 2006.257.10:06:12.33#ibcon#*before write, iclass 18, count 2 2006.257.10:06:12.33#ibcon#enter sib2, iclass 18, count 2 2006.257.10:06:12.33#ibcon#flushed, iclass 18, count 2 2006.257.10:06:12.33#ibcon#about to write, iclass 18, count 2 2006.257.10:06:12.33#ibcon#wrote, iclass 18, count 2 2006.257.10:06:12.33#ibcon#about to read 3, iclass 18, count 2 2006.257.10:06:12.36#ibcon#read 3, iclass 18, count 2 2006.257.10:06:12.36#ibcon#about to read 4, iclass 18, count 2 2006.257.10:06:12.36#ibcon#read 4, iclass 18, count 2 2006.257.10:06:12.36#ibcon#about to read 5, iclass 18, count 2 2006.257.10:06:12.36#ibcon#read 5, iclass 18, count 2 2006.257.10:06:12.36#ibcon#about to read 6, iclass 18, count 2 2006.257.10:06:12.36#ibcon#read 6, iclass 18, count 2 2006.257.10:06:12.36#ibcon#end of sib2, iclass 18, count 2 2006.257.10:06:12.36#ibcon#*after write, iclass 18, count 2 2006.257.10:06:12.36#ibcon#*before return 0, iclass 18, count 2 2006.257.10:06:12.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:12.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:06:12.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.10:06:12.36#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:12.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:12.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:12.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:12.48#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:06:12.48#ibcon#first serial, iclass 18, count 0 2006.257.10:06:12.48#ibcon#enter sib2, iclass 18, count 0 2006.257.10:06:12.48#ibcon#flushed, iclass 18, count 0 2006.257.10:06:12.48#ibcon#about to write, iclass 18, count 0 2006.257.10:06:12.48#ibcon#wrote, iclass 18, count 0 2006.257.10:06:12.48#ibcon#about to read 3, iclass 18, count 0 2006.257.10:06:12.50#ibcon#read 3, iclass 18, count 0 2006.257.10:06:12.50#ibcon#about to read 4, iclass 18, count 0 2006.257.10:06:12.50#ibcon#read 4, iclass 18, count 0 2006.257.10:06:12.50#ibcon#about to read 5, iclass 18, count 0 2006.257.10:06:12.50#ibcon#read 5, iclass 18, count 0 2006.257.10:06:12.50#ibcon#about to read 6, iclass 18, count 0 2006.257.10:06:12.50#ibcon#read 6, iclass 18, count 0 2006.257.10:06:12.50#ibcon#end of sib2, iclass 18, count 0 2006.257.10:06:12.50#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:06:12.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:06:12.50#ibcon#[27=USB\r\n] 2006.257.10:06:12.50#ibcon#*before write, iclass 18, count 0 2006.257.10:06:12.50#ibcon#enter sib2, iclass 18, count 0 2006.257.10:06:12.50#ibcon#flushed, iclass 18, count 0 2006.257.10:06:12.50#ibcon#about to write, iclass 18, count 0 2006.257.10:06:12.50#ibcon#wrote, iclass 18, count 0 2006.257.10:06:12.50#ibcon#about to read 3, iclass 18, count 0 2006.257.10:06:12.53#ibcon#read 3, iclass 18, count 0 2006.257.10:06:12.53#ibcon#about to read 4, iclass 18, count 0 2006.257.10:06:12.53#ibcon#read 4, iclass 18, count 0 2006.257.10:06:12.53#ibcon#about to read 5, iclass 18, count 0 2006.257.10:06:12.53#ibcon#read 5, iclass 18, count 0 2006.257.10:06:12.53#ibcon#about to read 6, iclass 18, count 0 2006.257.10:06:12.53#ibcon#read 6, iclass 18, count 0 2006.257.10:06:12.53#ibcon#end of sib2, iclass 18, count 0 2006.257.10:06:12.53#ibcon#*after write, iclass 18, count 0 2006.257.10:06:12.53#ibcon#*before return 0, iclass 18, count 0 2006.257.10:06:12.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:12.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:06:12.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:06:12.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:06:12.53$vck44/vblo=6,719.99 2006.257.10:06:12.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.10:06:12.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.10:06:12.53#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:12.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:12.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:12.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:12.53#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:06:12.53#ibcon#first serial, iclass 20, count 0 2006.257.10:06:12.53#ibcon#enter sib2, iclass 20, count 0 2006.257.10:06:12.53#ibcon#flushed, iclass 20, count 0 2006.257.10:06:12.53#ibcon#about to write, iclass 20, count 0 2006.257.10:06:12.53#ibcon#wrote, iclass 20, count 0 2006.257.10:06:12.53#ibcon#about to read 3, iclass 20, count 0 2006.257.10:06:12.55#ibcon#read 3, iclass 20, count 0 2006.257.10:06:12.55#ibcon#about to read 4, iclass 20, count 0 2006.257.10:06:12.55#ibcon#read 4, iclass 20, count 0 2006.257.10:06:12.55#ibcon#about to read 5, iclass 20, count 0 2006.257.10:06:12.55#ibcon#read 5, iclass 20, count 0 2006.257.10:06:12.55#ibcon#about to read 6, iclass 20, count 0 2006.257.10:06:12.55#ibcon#read 6, iclass 20, count 0 2006.257.10:06:12.55#ibcon#end of sib2, iclass 20, count 0 2006.257.10:06:12.55#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:06:12.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:06:12.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:06:12.55#ibcon#*before write, iclass 20, count 0 2006.257.10:06:12.55#ibcon#enter sib2, iclass 20, count 0 2006.257.10:06:12.55#ibcon#flushed, iclass 20, count 0 2006.257.10:06:12.55#ibcon#about to write, iclass 20, count 0 2006.257.10:06:12.55#ibcon#wrote, iclass 20, count 0 2006.257.10:06:12.55#ibcon#about to read 3, iclass 20, count 0 2006.257.10:06:12.59#ibcon#read 3, iclass 20, count 0 2006.257.10:06:12.59#ibcon#about to read 4, iclass 20, count 0 2006.257.10:06:12.59#ibcon#read 4, iclass 20, count 0 2006.257.10:06:12.59#ibcon#about to read 5, iclass 20, count 0 2006.257.10:06:12.59#ibcon#read 5, iclass 20, count 0 2006.257.10:06:12.59#ibcon#about to read 6, iclass 20, count 0 2006.257.10:06:12.59#ibcon#read 6, iclass 20, count 0 2006.257.10:06:12.59#ibcon#end of sib2, iclass 20, count 0 2006.257.10:06:12.59#ibcon#*after write, iclass 20, count 0 2006.257.10:06:12.59#ibcon#*before return 0, iclass 20, count 0 2006.257.10:06:12.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:12.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:06:12.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:06:12.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:06:12.59$vck44/vb=6,4 2006.257.10:06:12.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.10:06:12.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.10:06:12.59#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:12.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:12.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:12.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:12.65#ibcon#enter wrdev, iclass 22, count 2 2006.257.10:06:12.65#ibcon#first serial, iclass 22, count 2 2006.257.10:06:12.65#ibcon#enter sib2, iclass 22, count 2 2006.257.10:06:12.65#ibcon#flushed, iclass 22, count 2 2006.257.10:06:12.65#ibcon#about to write, iclass 22, count 2 2006.257.10:06:12.65#ibcon#wrote, iclass 22, count 2 2006.257.10:06:12.65#ibcon#about to read 3, iclass 22, count 2 2006.257.10:06:12.67#ibcon#read 3, iclass 22, count 2 2006.257.10:06:12.67#ibcon#about to read 4, iclass 22, count 2 2006.257.10:06:12.67#ibcon#read 4, iclass 22, count 2 2006.257.10:06:12.67#ibcon#about to read 5, iclass 22, count 2 2006.257.10:06:12.67#ibcon#read 5, iclass 22, count 2 2006.257.10:06:12.67#ibcon#about to read 6, iclass 22, count 2 2006.257.10:06:12.67#ibcon#read 6, iclass 22, count 2 2006.257.10:06:12.67#ibcon#end of sib2, iclass 22, count 2 2006.257.10:06:12.67#ibcon#*mode == 0, iclass 22, count 2 2006.257.10:06:12.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.10:06:12.67#ibcon#[27=AT06-04\r\n] 2006.257.10:06:12.67#ibcon#*before write, iclass 22, count 2 2006.257.10:06:12.67#ibcon#enter sib2, iclass 22, count 2 2006.257.10:06:12.67#ibcon#flushed, iclass 22, count 2 2006.257.10:06:12.67#ibcon#about to write, iclass 22, count 2 2006.257.10:06:12.67#ibcon#wrote, iclass 22, count 2 2006.257.10:06:12.67#ibcon#about to read 3, iclass 22, count 2 2006.257.10:06:12.70#ibcon#read 3, iclass 22, count 2 2006.257.10:06:12.70#ibcon#about to read 4, iclass 22, count 2 2006.257.10:06:12.70#ibcon#read 4, iclass 22, count 2 2006.257.10:06:12.70#ibcon#about to read 5, iclass 22, count 2 2006.257.10:06:12.70#ibcon#read 5, iclass 22, count 2 2006.257.10:06:12.70#ibcon#about to read 6, iclass 22, count 2 2006.257.10:06:12.70#ibcon#read 6, iclass 22, count 2 2006.257.10:06:12.70#ibcon#end of sib2, iclass 22, count 2 2006.257.10:06:12.70#ibcon#*after write, iclass 22, count 2 2006.257.10:06:12.70#ibcon#*before return 0, iclass 22, count 2 2006.257.10:06:12.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:12.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:06:12.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.10:06:12.70#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:12.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:12.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:12.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:12.82#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:06:12.82#ibcon#first serial, iclass 22, count 0 2006.257.10:06:12.82#ibcon#enter sib2, iclass 22, count 0 2006.257.10:06:12.82#ibcon#flushed, iclass 22, count 0 2006.257.10:06:12.82#ibcon#about to write, iclass 22, count 0 2006.257.10:06:12.82#ibcon#wrote, iclass 22, count 0 2006.257.10:06:12.82#ibcon#about to read 3, iclass 22, count 0 2006.257.10:06:12.84#ibcon#read 3, iclass 22, count 0 2006.257.10:06:12.84#ibcon#about to read 4, iclass 22, count 0 2006.257.10:06:12.84#ibcon#read 4, iclass 22, count 0 2006.257.10:06:12.84#ibcon#about to read 5, iclass 22, count 0 2006.257.10:06:12.84#ibcon#read 5, iclass 22, count 0 2006.257.10:06:12.84#ibcon#about to read 6, iclass 22, count 0 2006.257.10:06:12.84#ibcon#read 6, iclass 22, count 0 2006.257.10:06:12.84#ibcon#end of sib2, iclass 22, count 0 2006.257.10:06:12.84#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:06:12.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:06:12.84#ibcon#[27=USB\r\n] 2006.257.10:06:12.84#ibcon#*before write, iclass 22, count 0 2006.257.10:06:12.84#ibcon#enter sib2, iclass 22, count 0 2006.257.10:06:12.84#ibcon#flushed, iclass 22, count 0 2006.257.10:06:12.84#ibcon#about to write, iclass 22, count 0 2006.257.10:06:12.84#ibcon#wrote, iclass 22, count 0 2006.257.10:06:12.84#ibcon#about to read 3, iclass 22, count 0 2006.257.10:06:12.87#ibcon#read 3, iclass 22, count 0 2006.257.10:06:12.87#ibcon#about to read 4, iclass 22, count 0 2006.257.10:06:12.87#ibcon#read 4, iclass 22, count 0 2006.257.10:06:12.87#ibcon#about to read 5, iclass 22, count 0 2006.257.10:06:12.87#ibcon#read 5, iclass 22, count 0 2006.257.10:06:12.87#ibcon#about to read 6, iclass 22, count 0 2006.257.10:06:12.87#ibcon#read 6, iclass 22, count 0 2006.257.10:06:12.87#ibcon#end of sib2, iclass 22, count 0 2006.257.10:06:12.87#ibcon#*after write, iclass 22, count 0 2006.257.10:06:12.87#ibcon#*before return 0, iclass 22, count 0 2006.257.10:06:12.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:12.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:06:12.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:06:12.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:06:12.87$vck44/vblo=7,734.99 2006.257.10:06:12.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.10:06:12.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.10:06:12.87#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:12.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:12.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:12.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:12.87#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:06:12.87#ibcon#first serial, iclass 24, count 0 2006.257.10:06:12.87#ibcon#enter sib2, iclass 24, count 0 2006.257.10:06:12.87#ibcon#flushed, iclass 24, count 0 2006.257.10:06:12.87#ibcon#about to write, iclass 24, count 0 2006.257.10:06:12.87#ibcon#wrote, iclass 24, count 0 2006.257.10:06:12.87#ibcon#about to read 3, iclass 24, count 0 2006.257.10:06:12.89#ibcon#read 3, iclass 24, count 0 2006.257.10:06:12.89#ibcon#about to read 4, iclass 24, count 0 2006.257.10:06:12.89#ibcon#read 4, iclass 24, count 0 2006.257.10:06:12.89#ibcon#about to read 5, iclass 24, count 0 2006.257.10:06:12.89#ibcon#read 5, iclass 24, count 0 2006.257.10:06:12.89#ibcon#about to read 6, iclass 24, count 0 2006.257.10:06:12.89#ibcon#read 6, iclass 24, count 0 2006.257.10:06:12.89#ibcon#end of sib2, iclass 24, count 0 2006.257.10:06:12.89#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:06:12.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:06:12.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:06:12.89#ibcon#*before write, iclass 24, count 0 2006.257.10:06:12.89#ibcon#enter sib2, iclass 24, count 0 2006.257.10:06:12.89#ibcon#flushed, iclass 24, count 0 2006.257.10:06:12.89#ibcon#about to write, iclass 24, count 0 2006.257.10:06:12.89#ibcon#wrote, iclass 24, count 0 2006.257.10:06:12.89#ibcon#about to read 3, iclass 24, count 0 2006.257.10:06:12.93#ibcon#read 3, iclass 24, count 0 2006.257.10:06:12.93#ibcon#about to read 4, iclass 24, count 0 2006.257.10:06:12.93#ibcon#read 4, iclass 24, count 0 2006.257.10:06:12.93#ibcon#about to read 5, iclass 24, count 0 2006.257.10:06:12.93#ibcon#read 5, iclass 24, count 0 2006.257.10:06:12.93#ibcon#about to read 6, iclass 24, count 0 2006.257.10:06:12.93#ibcon#read 6, iclass 24, count 0 2006.257.10:06:12.93#ibcon#end of sib2, iclass 24, count 0 2006.257.10:06:12.93#ibcon#*after write, iclass 24, count 0 2006.257.10:06:12.93#ibcon#*before return 0, iclass 24, count 0 2006.257.10:06:12.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:12.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:06:12.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:06:12.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:06:12.93$vck44/vb=7,4 2006.257.10:06:12.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.10:06:12.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.10:06:12.93#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:12.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:12.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:12.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:12.99#ibcon#enter wrdev, iclass 26, count 2 2006.257.10:06:12.99#ibcon#first serial, iclass 26, count 2 2006.257.10:06:12.99#ibcon#enter sib2, iclass 26, count 2 2006.257.10:06:12.99#ibcon#flushed, iclass 26, count 2 2006.257.10:06:12.99#ibcon#about to write, iclass 26, count 2 2006.257.10:06:12.99#ibcon#wrote, iclass 26, count 2 2006.257.10:06:12.99#ibcon#about to read 3, iclass 26, count 2 2006.257.10:06:13.01#ibcon#read 3, iclass 26, count 2 2006.257.10:06:13.01#ibcon#about to read 4, iclass 26, count 2 2006.257.10:06:13.01#ibcon#read 4, iclass 26, count 2 2006.257.10:06:13.01#ibcon#about to read 5, iclass 26, count 2 2006.257.10:06:13.01#ibcon#read 5, iclass 26, count 2 2006.257.10:06:13.01#ibcon#about to read 6, iclass 26, count 2 2006.257.10:06:13.01#ibcon#read 6, iclass 26, count 2 2006.257.10:06:13.01#ibcon#end of sib2, iclass 26, count 2 2006.257.10:06:13.01#ibcon#*mode == 0, iclass 26, count 2 2006.257.10:06:13.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.10:06:13.01#ibcon#[27=AT07-04\r\n] 2006.257.10:06:13.01#ibcon#*before write, iclass 26, count 2 2006.257.10:06:13.01#ibcon#enter sib2, iclass 26, count 2 2006.257.10:06:13.01#ibcon#flushed, iclass 26, count 2 2006.257.10:06:13.01#ibcon#about to write, iclass 26, count 2 2006.257.10:06:13.01#ibcon#wrote, iclass 26, count 2 2006.257.10:06:13.01#ibcon#about to read 3, iclass 26, count 2 2006.257.10:06:13.04#ibcon#read 3, iclass 26, count 2 2006.257.10:06:13.04#ibcon#about to read 4, iclass 26, count 2 2006.257.10:06:13.04#ibcon#read 4, iclass 26, count 2 2006.257.10:06:13.04#ibcon#about to read 5, iclass 26, count 2 2006.257.10:06:13.04#ibcon#read 5, iclass 26, count 2 2006.257.10:06:13.04#ibcon#about to read 6, iclass 26, count 2 2006.257.10:06:13.04#ibcon#read 6, iclass 26, count 2 2006.257.10:06:13.04#ibcon#end of sib2, iclass 26, count 2 2006.257.10:06:13.04#ibcon#*after write, iclass 26, count 2 2006.257.10:06:13.04#ibcon#*before return 0, iclass 26, count 2 2006.257.10:06:13.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:13.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:06:13.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.10:06:13.04#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:13.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:13.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:13.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:13.16#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:06:13.16#ibcon#first serial, iclass 26, count 0 2006.257.10:06:13.16#ibcon#enter sib2, iclass 26, count 0 2006.257.10:06:13.16#ibcon#flushed, iclass 26, count 0 2006.257.10:06:13.16#ibcon#about to write, iclass 26, count 0 2006.257.10:06:13.16#ibcon#wrote, iclass 26, count 0 2006.257.10:06:13.16#ibcon#about to read 3, iclass 26, count 0 2006.257.10:06:13.18#ibcon#read 3, iclass 26, count 0 2006.257.10:06:13.18#ibcon#about to read 4, iclass 26, count 0 2006.257.10:06:13.18#ibcon#read 4, iclass 26, count 0 2006.257.10:06:13.18#ibcon#about to read 5, iclass 26, count 0 2006.257.10:06:13.18#ibcon#read 5, iclass 26, count 0 2006.257.10:06:13.18#ibcon#about to read 6, iclass 26, count 0 2006.257.10:06:13.18#ibcon#read 6, iclass 26, count 0 2006.257.10:06:13.18#ibcon#end of sib2, iclass 26, count 0 2006.257.10:06:13.18#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:06:13.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:06:13.18#ibcon#[27=USB\r\n] 2006.257.10:06:13.18#ibcon#*before write, iclass 26, count 0 2006.257.10:06:13.18#ibcon#enter sib2, iclass 26, count 0 2006.257.10:06:13.18#ibcon#flushed, iclass 26, count 0 2006.257.10:06:13.18#ibcon#about to write, iclass 26, count 0 2006.257.10:06:13.18#ibcon#wrote, iclass 26, count 0 2006.257.10:06:13.18#ibcon#about to read 3, iclass 26, count 0 2006.257.10:06:13.21#ibcon#read 3, iclass 26, count 0 2006.257.10:06:13.21#ibcon#about to read 4, iclass 26, count 0 2006.257.10:06:13.21#ibcon#read 4, iclass 26, count 0 2006.257.10:06:13.21#ibcon#about to read 5, iclass 26, count 0 2006.257.10:06:13.21#ibcon#read 5, iclass 26, count 0 2006.257.10:06:13.21#ibcon#about to read 6, iclass 26, count 0 2006.257.10:06:13.21#ibcon#read 6, iclass 26, count 0 2006.257.10:06:13.21#ibcon#end of sib2, iclass 26, count 0 2006.257.10:06:13.21#ibcon#*after write, iclass 26, count 0 2006.257.10:06:13.21#ibcon#*before return 0, iclass 26, count 0 2006.257.10:06:13.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:13.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:06:13.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:06:13.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:06:13.21$vck44/vblo=8,744.99 2006.257.10:06:13.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.10:06:13.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.10:06:13.21#ibcon#ireg 17 cls_cnt 0 2006.257.10:06:13.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:13.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:13.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:13.21#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:06:13.21#ibcon#first serial, iclass 28, count 0 2006.257.10:06:13.21#ibcon#enter sib2, iclass 28, count 0 2006.257.10:06:13.21#ibcon#flushed, iclass 28, count 0 2006.257.10:06:13.21#ibcon#about to write, iclass 28, count 0 2006.257.10:06:13.21#ibcon#wrote, iclass 28, count 0 2006.257.10:06:13.21#ibcon#about to read 3, iclass 28, count 0 2006.257.10:06:13.23#ibcon#read 3, iclass 28, count 0 2006.257.10:06:13.23#ibcon#about to read 4, iclass 28, count 0 2006.257.10:06:13.23#ibcon#read 4, iclass 28, count 0 2006.257.10:06:13.23#ibcon#about to read 5, iclass 28, count 0 2006.257.10:06:13.23#ibcon#read 5, iclass 28, count 0 2006.257.10:06:13.23#ibcon#about to read 6, iclass 28, count 0 2006.257.10:06:13.23#ibcon#read 6, iclass 28, count 0 2006.257.10:06:13.23#ibcon#end of sib2, iclass 28, count 0 2006.257.10:06:13.23#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:06:13.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:06:13.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:06:13.23#ibcon#*before write, iclass 28, count 0 2006.257.10:06:13.23#ibcon#enter sib2, iclass 28, count 0 2006.257.10:06:13.23#ibcon#flushed, iclass 28, count 0 2006.257.10:06:13.23#ibcon#about to write, iclass 28, count 0 2006.257.10:06:13.23#ibcon#wrote, iclass 28, count 0 2006.257.10:06:13.23#ibcon#about to read 3, iclass 28, count 0 2006.257.10:06:13.27#ibcon#read 3, iclass 28, count 0 2006.257.10:06:13.27#ibcon#about to read 4, iclass 28, count 0 2006.257.10:06:13.27#ibcon#read 4, iclass 28, count 0 2006.257.10:06:13.27#ibcon#about to read 5, iclass 28, count 0 2006.257.10:06:13.27#ibcon#read 5, iclass 28, count 0 2006.257.10:06:13.27#ibcon#about to read 6, iclass 28, count 0 2006.257.10:06:13.27#ibcon#read 6, iclass 28, count 0 2006.257.10:06:13.27#ibcon#end of sib2, iclass 28, count 0 2006.257.10:06:13.27#ibcon#*after write, iclass 28, count 0 2006.257.10:06:13.27#ibcon#*before return 0, iclass 28, count 0 2006.257.10:06:13.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:13.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:06:13.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:06:13.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:06:13.27$vck44/vb=8,4 2006.257.10:06:13.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.10:06:13.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.10:06:13.27#ibcon#ireg 11 cls_cnt 2 2006.257.10:06:13.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:13.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:13.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:13.33#ibcon#enter wrdev, iclass 30, count 2 2006.257.10:06:13.33#ibcon#first serial, iclass 30, count 2 2006.257.10:06:13.33#ibcon#enter sib2, iclass 30, count 2 2006.257.10:06:13.33#ibcon#flushed, iclass 30, count 2 2006.257.10:06:13.33#ibcon#about to write, iclass 30, count 2 2006.257.10:06:13.33#ibcon#wrote, iclass 30, count 2 2006.257.10:06:13.33#ibcon#about to read 3, iclass 30, count 2 2006.257.10:06:13.35#ibcon#read 3, iclass 30, count 2 2006.257.10:06:13.35#ibcon#about to read 4, iclass 30, count 2 2006.257.10:06:13.35#ibcon#read 4, iclass 30, count 2 2006.257.10:06:13.35#ibcon#about to read 5, iclass 30, count 2 2006.257.10:06:13.35#ibcon#read 5, iclass 30, count 2 2006.257.10:06:13.35#ibcon#about to read 6, iclass 30, count 2 2006.257.10:06:13.35#ibcon#read 6, iclass 30, count 2 2006.257.10:06:13.35#ibcon#end of sib2, iclass 30, count 2 2006.257.10:06:13.35#ibcon#*mode == 0, iclass 30, count 2 2006.257.10:06:13.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.10:06:13.35#ibcon#[27=AT08-04\r\n] 2006.257.10:06:13.35#ibcon#*before write, iclass 30, count 2 2006.257.10:06:13.35#ibcon#enter sib2, iclass 30, count 2 2006.257.10:06:13.35#ibcon#flushed, iclass 30, count 2 2006.257.10:06:13.35#ibcon#about to write, iclass 30, count 2 2006.257.10:06:13.35#ibcon#wrote, iclass 30, count 2 2006.257.10:06:13.35#ibcon#about to read 3, iclass 30, count 2 2006.257.10:06:13.38#ibcon#read 3, iclass 30, count 2 2006.257.10:06:13.38#ibcon#about to read 4, iclass 30, count 2 2006.257.10:06:13.38#ibcon#read 4, iclass 30, count 2 2006.257.10:06:13.38#ibcon#about to read 5, iclass 30, count 2 2006.257.10:06:13.38#ibcon#read 5, iclass 30, count 2 2006.257.10:06:13.38#ibcon#about to read 6, iclass 30, count 2 2006.257.10:06:13.38#ibcon#read 6, iclass 30, count 2 2006.257.10:06:13.38#ibcon#end of sib2, iclass 30, count 2 2006.257.10:06:13.38#ibcon#*after write, iclass 30, count 2 2006.257.10:06:13.38#ibcon#*before return 0, iclass 30, count 2 2006.257.10:06:13.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:13.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:06:13.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.10:06:13.38#ibcon#ireg 7 cls_cnt 0 2006.257.10:06:13.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:13.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:13.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:13.50#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:06:13.50#ibcon#first serial, iclass 30, count 0 2006.257.10:06:13.50#ibcon#enter sib2, iclass 30, count 0 2006.257.10:06:13.50#ibcon#flushed, iclass 30, count 0 2006.257.10:06:13.50#ibcon#about to write, iclass 30, count 0 2006.257.10:06:13.50#ibcon#wrote, iclass 30, count 0 2006.257.10:06:13.50#ibcon#about to read 3, iclass 30, count 0 2006.257.10:06:13.52#ibcon#read 3, iclass 30, count 0 2006.257.10:06:13.52#ibcon#about to read 4, iclass 30, count 0 2006.257.10:06:13.52#ibcon#read 4, iclass 30, count 0 2006.257.10:06:13.52#ibcon#about to read 5, iclass 30, count 0 2006.257.10:06:13.52#ibcon#read 5, iclass 30, count 0 2006.257.10:06:13.52#ibcon#about to read 6, iclass 30, count 0 2006.257.10:06:13.52#ibcon#read 6, iclass 30, count 0 2006.257.10:06:13.52#ibcon#end of sib2, iclass 30, count 0 2006.257.10:06:13.52#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:06:13.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:06:13.52#ibcon#[27=USB\r\n] 2006.257.10:06:13.52#ibcon#*before write, iclass 30, count 0 2006.257.10:06:13.52#ibcon#enter sib2, iclass 30, count 0 2006.257.10:06:13.52#ibcon#flushed, iclass 30, count 0 2006.257.10:06:13.52#ibcon#about to write, iclass 30, count 0 2006.257.10:06:13.52#ibcon#wrote, iclass 30, count 0 2006.257.10:06:13.52#ibcon#about to read 3, iclass 30, count 0 2006.257.10:06:13.55#ibcon#read 3, iclass 30, count 0 2006.257.10:06:13.55#ibcon#about to read 4, iclass 30, count 0 2006.257.10:06:13.55#ibcon#read 4, iclass 30, count 0 2006.257.10:06:13.55#ibcon#about to read 5, iclass 30, count 0 2006.257.10:06:13.55#ibcon#read 5, iclass 30, count 0 2006.257.10:06:13.55#ibcon#about to read 6, iclass 30, count 0 2006.257.10:06:13.55#ibcon#read 6, iclass 30, count 0 2006.257.10:06:13.55#ibcon#end of sib2, iclass 30, count 0 2006.257.10:06:13.55#ibcon#*after write, iclass 30, count 0 2006.257.10:06:13.55#ibcon#*before return 0, iclass 30, count 0 2006.257.10:06:13.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:13.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:06:13.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:06:13.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:06:13.55$vck44/vabw=wide 2006.257.10:06:13.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.10:06:13.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.10:06:13.55#ibcon#ireg 8 cls_cnt 0 2006.257.10:06:13.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:13.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:13.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:13.55#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:06:13.55#ibcon#first serial, iclass 32, count 0 2006.257.10:06:13.55#ibcon#enter sib2, iclass 32, count 0 2006.257.10:06:13.55#ibcon#flushed, iclass 32, count 0 2006.257.10:06:13.55#ibcon#about to write, iclass 32, count 0 2006.257.10:06:13.55#ibcon#wrote, iclass 32, count 0 2006.257.10:06:13.55#ibcon#about to read 3, iclass 32, count 0 2006.257.10:06:13.57#ibcon#read 3, iclass 32, count 0 2006.257.10:06:13.57#ibcon#about to read 4, iclass 32, count 0 2006.257.10:06:13.57#ibcon#read 4, iclass 32, count 0 2006.257.10:06:13.57#ibcon#about to read 5, iclass 32, count 0 2006.257.10:06:13.57#ibcon#read 5, iclass 32, count 0 2006.257.10:06:13.57#ibcon#about to read 6, iclass 32, count 0 2006.257.10:06:13.57#ibcon#read 6, iclass 32, count 0 2006.257.10:06:13.57#ibcon#end of sib2, iclass 32, count 0 2006.257.10:06:13.57#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:06:13.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:06:13.57#ibcon#[25=BW32\r\n] 2006.257.10:06:13.57#ibcon#*before write, iclass 32, count 0 2006.257.10:06:13.57#ibcon#enter sib2, iclass 32, count 0 2006.257.10:06:13.57#ibcon#flushed, iclass 32, count 0 2006.257.10:06:13.57#ibcon#about to write, iclass 32, count 0 2006.257.10:06:13.57#ibcon#wrote, iclass 32, count 0 2006.257.10:06:13.57#ibcon#about to read 3, iclass 32, count 0 2006.257.10:06:13.60#ibcon#read 3, iclass 32, count 0 2006.257.10:06:13.60#ibcon#about to read 4, iclass 32, count 0 2006.257.10:06:13.60#ibcon#read 4, iclass 32, count 0 2006.257.10:06:13.60#ibcon#about to read 5, iclass 32, count 0 2006.257.10:06:13.60#ibcon#read 5, iclass 32, count 0 2006.257.10:06:13.60#ibcon#about to read 6, iclass 32, count 0 2006.257.10:06:13.60#ibcon#read 6, iclass 32, count 0 2006.257.10:06:13.60#ibcon#end of sib2, iclass 32, count 0 2006.257.10:06:13.60#ibcon#*after write, iclass 32, count 0 2006.257.10:06:13.60#ibcon#*before return 0, iclass 32, count 0 2006.257.10:06:13.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:13.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:06:13.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:06:13.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:06:13.60$vck44/vbbw=wide 2006.257.10:06:13.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.10:06:13.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.10:06:13.60#ibcon#ireg 8 cls_cnt 0 2006.257.10:06:13.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:06:13.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:06:13.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:06:13.67#ibcon#enter wrdev, iclass 34, count 0 2006.257.10:06:13.67#ibcon#first serial, iclass 34, count 0 2006.257.10:06:13.67#ibcon#enter sib2, iclass 34, count 0 2006.257.10:06:13.67#ibcon#flushed, iclass 34, count 0 2006.257.10:06:13.67#ibcon#about to write, iclass 34, count 0 2006.257.10:06:13.67#ibcon#wrote, iclass 34, count 0 2006.257.10:06:13.67#ibcon#about to read 3, iclass 34, count 0 2006.257.10:06:13.69#ibcon#read 3, iclass 34, count 0 2006.257.10:06:13.69#ibcon#about to read 4, iclass 34, count 0 2006.257.10:06:13.69#ibcon#read 4, iclass 34, count 0 2006.257.10:06:13.69#ibcon#about to read 5, iclass 34, count 0 2006.257.10:06:13.69#ibcon#read 5, iclass 34, count 0 2006.257.10:06:13.69#ibcon#about to read 6, iclass 34, count 0 2006.257.10:06:13.69#ibcon#read 6, iclass 34, count 0 2006.257.10:06:13.69#ibcon#end of sib2, iclass 34, count 0 2006.257.10:06:13.69#ibcon#*mode == 0, iclass 34, count 0 2006.257.10:06:13.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.10:06:13.69#ibcon#[27=BW32\r\n] 2006.257.10:06:13.69#ibcon#*before write, iclass 34, count 0 2006.257.10:06:13.69#ibcon#enter sib2, iclass 34, count 0 2006.257.10:06:13.69#ibcon#flushed, iclass 34, count 0 2006.257.10:06:13.69#ibcon#about to write, iclass 34, count 0 2006.257.10:06:13.69#ibcon#wrote, iclass 34, count 0 2006.257.10:06:13.69#ibcon#about to read 3, iclass 34, count 0 2006.257.10:06:13.72#ibcon#read 3, iclass 34, count 0 2006.257.10:06:13.72#ibcon#about to read 4, iclass 34, count 0 2006.257.10:06:13.72#ibcon#read 4, iclass 34, count 0 2006.257.10:06:13.72#ibcon#about to read 5, iclass 34, count 0 2006.257.10:06:13.72#ibcon#read 5, iclass 34, count 0 2006.257.10:06:13.72#ibcon#about to read 6, iclass 34, count 0 2006.257.10:06:13.72#ibcon#read 6, iclass 34, count 0 2006.257.10:06:13.72#ibcon#end of sib2, iclass 34, count 0 2006.257.10:06:13.72#ibcon#*after write, iclass 34, count 0 2006.257.10:06:13.72#ibcon#*before return 0, iclass 34, count 0 2006.257.10:06:13.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:06:13.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:06:13.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.10:06:13.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.10:06:13.72$setupk4/ifdk4 2006.257.10:06:13.72$ifdk4/lo= 2006.257.10:06:13.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:06:13.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:06:13.72$ifdk4/patch= 2006.257.10:06:13.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:06:13.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:06:13.72$setupk4/!*+20s 2006.257.10:06:16.94#abcon#<5=/14 0.7 2.2 19.20 961013.4\r\n> 2006.257.10:06:16.96#abcon#{5=INTERFACE CLEAR} 2006.257.10:06:17.02#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:06:27.11#abcon#<5=/14 0.7 2.2 19.20 961013.4\r\n> 2006.257.10:06:27.13#abcon#{5=INTERFACE CLEAR} 2006.257.10:06:27.19#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:06:28.13$setupk4/"tpicd 2006.257.10:06:28.13$setupk4/echo=off 2006.257.10:06:28.13$setupk4/xlog=off 2006.257.10:06:28.13:!2006.257.10:10:38 2006.257.10:06:31.13#trakl#Source acquired 2006.257.10:06:31.13#flagr#flagr/antenna,acquired 2006.257.10:10:38.00:preob 2006.257.10:10:38.14/onsource/TRACKING 2006.257.10:10:38.14:!2006.257.10:10:48 2006.257.10:10:48.00:"tape 2006.257.10:10:48.00:"st=record 2006.257.10:10:48.00:data_valid=on 2006.257.10:10:48.00:midob 2006.257.10:10:49.14/onsource/TRACKING 2006.257.10:10:49.14/wx/19.13,1013.5,96 2006.257.10:10:49.28/cable/+6.4776E-03 2006.257.10:10:50.37/va/01,08,usb,yes,32,35 2006.257.10:10:50.37/va/02,07,usb,yes,35,35 2006.257.10:10:50.37/va/03,08,usb,yes,31,33 2006.257.10:10:50.37/va/04,07,usb,yes,36,38 2006.257.10:10:50.37/va/05,04,usb,yes,32,33 2006.257.10:10:50.37/va/06,04,usb,yes,36,36 2006.257.10:10:50.37/va/07,04,usb,yes,37,37 2006.257.10:10:50.37/va/08,04,usb,yes,31,38 2006.257.10:10:50.60/valo/01,524.99,yes,locked 2006.257.10:10:50.60/valo/02,534.99,yes,locked 2006.257.10:10:50.60/valo/03,564.99,yes,locked 2006.257.10:10:50.60/valo/04,624.99,yes,locked 2006.257.10:10:50.60/valo/05,734.99,yes,locked 2006.257.10:10:50.60/valo/06,814.99,yes,locked 2006.257.10:10:50.60/valo/07,864.99,yes,locked 2006.257.10:10:50.60/valo/08,884.99,yes,locked 2006.257.10:10:51.69/vb/01,04,usb,yes,31,29 2006.257.10:10:51.69/vb/02,05,usb,yes,30,30 2006.257.10:10:51.69/vb/03,04,usb,yes,31,34 2006.257.10:10:51.69/vb/04,05,usb,yes,31,30 2006.257.10:10:51.69/vb/05,04,usb,yes,27,30 2006.257.10:10:51.69/vb/06,04,usb,yes,32,28 2006.257.10:10:51.69/vb/07,04,usb,yes,32,32 2006.257.10:10:51.69/vb/08,04,usb,yes,29,33 2006.257.10:10:51.93/vblo/01,629.99,yes,locked 2006.257.10:10:51.93/vblo/02,634.99,yes,locked 2006.257.10:10:51.93/vblo/03,649.99,yes,locked 2006.257.10:10:51.93/vblo/04,679.99,yes,locked 2006.257.10:10:51.93/vblo/05,709.99,yes,locked 2006.257.10:10:51.93/vblo/06,719.99,yes,locked 2006.257.10:10:51.93/vblo/07,734.99,yes,locked 2006.257.10:10:51.93/vblo/08,744.99,yes,locked 2006.257.10:10:52.08/vabw/8 2006.257.10:10:52.23/vbbw/8 2006.257.10:10:52.32/xfe/off,on,15.2 2006.257.10:10:52.70/ifatt/23,28,28,28 2006.257.10:10:53.08/fmout-gps/S +4.60E-07 2006.257.10:10:53.12:!2006.257.10:16:28 2006.257.10:16:28.00:data_valid=off 2006.257.10:16:28.01:"et 2006.257.10:16:28.01:!+3s 2006.257.10:16:31.04:"tape 2006.257.10:16:31.05:postob 2006.257.10:16:31.16/cable/+6.4767E-03 2006.257.10:16:31.17/wx/19.06,1013.6,96 2006.257.10:16:31.22/fmout-gps/S +4.59E-07 2006.257.10:16:31.23:scan_name=257-1019,jd0609,40 2006.257.10:16:31.23:source=1954-388,195800.00,-384506.4,2000.0,ccw 2006.257.10:16:33.15#flagr#flagr/antenna,new-source 2006.257.10:16:33.15:checkk5 2006.257.10:16:33.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:16:33.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:16:34.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:16:34.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:16:35.18/chk_obsdata//k5ts1/T2571010??a.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.257.10:16:35.58/chk_obsdata//k5ts2/T2571010??b.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.257.10:16:35.98/chk_obsdata//k5ts3/T2571010??c.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.257.10:16:36.39/chk_obsdata//k5ts4/T2571010??d.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.257.10:16:37.11/k5log//k5ts1_log_newline 2006.257.10:16:37.82/k5log//k5ts2_log_newline 2006.257.10:16:38.56/k5log//k5ts3_log_newline 2006.257.10:16:39.28/k5log//k5ts4_log_newline 2006.257.10:16:39.30/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:16:39.30:setupk4=1 2006.257.10:16:39.30$setupk4/echo=on 2006.257.10:16:39.30$setupk4/pcalon 2006.257.10:16:39.30$pcalon/"no phase cal control is implemented here 2006.257.10:16:39.30$setupk4/"tpicd=stop 2006.257.10:16:39.30$setupk4/"rec=synch_on 2006.257.10:16:39.30$setupk4/"rec_mode=128 2006.257.10:16:39.30$setupk4/!* 2006.257.10:16:39.30$setupk4/recpk4 2006.257.10:16:39.30$recpk4/recpatch= 2006.257.10:16:39.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:16:39.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:16:39.31$setupk4/vck44 2006.257.10:16:39.31$vck44/valo=1,524.99 2006.257.10:16:39.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.10:16:39.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.10:16:39.31#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:39.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:39.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:39.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:39.31#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:16:39.31#ibcon#first serial, iclass 21, count 0 2006.257.10:16:39.31#ibcon#enter sib2, iclass 21, count 0 2006.257.10:16:39.31#ibcon#flushed, iclass 21, count 0 2006.257.10:16:39.31#ibcon#about to write, iclass 21, count 0 2006.257.10:16:39.31#ibcon#wrote, iclass 21, count 0 2006.257.10:16:39.31#ibcon#about to read 3, iclass 21, count 0 2006.257.10:16:39.32#ibcon#read 3, iclass 21, count 0 2006.257.10:16:39.32#ibcon#about to read 4, iclass 21, count 0 2006.257.10:16:39.32#ibcon#read 4, iclass 21, count 0 2006.257.10:16:39.32#ibcon#about to read 5, iclass 21, count 0 2006.257.10:16:39.32#ibcon#read 5, iclass 21, count 0 2006.257.10:16:39.32#ibcon#about to read 6, iclass 21, count 0 2006.257.10:16:39.32#ibcon#read 6, iclass 21, count 0 2006.257.10:16:39.32#ibcon#end of sib2, iclass 21, count 0 2006.257.10:16:39.32#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:16:39.32#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:16:39.32#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:16:39.32#ibcon#*before write, iclass 21, count 0 2006.257.10:16:39.32#ibcon#enter sib2, iclass 21, count 0 2006.257.10:16:39.32#ibcon#flushed, iclass 21, count 0 2006.257.10:16:39.32#ibcon#about to write, iclass 21, count 0 2006.257.10:16:39.32#ibcon#wrote, iclass 21, count 0 2006.257.10:16:39.32#ibcon#about to read 3, iclass 21, count 0 2006.257.10:16:39.37#ibcon#read 3, iclass 21, count 0 2006.257.10:16:39.37#ibcon#about to read 4, iclass 21, count 0 2006.257.10:16:39.37#ibcon#read 4, iclass 21, count 0 2006.257.10:16:39.37#ibcon#about to read 5, iclass 21, count 0 2006.257.10:16:39.37#ibcon#read 5, iclass 21, count 0 2006.257.10:16:39.37#ibcon#about to read 6, iclass 21, count 0 2006.257.10:16:39.37#ibcon#read 6, iclass 21, count 0 2006.257.10:16:39.37#ibcon#end of sib2, iclass 21, count 0 2006.257.10:16:39.37#ibcon#*after write, iclass 21, count 0 2006.257.10:16:39.37#ibcon#*before return 0, iclass 21, count 0 2006.257.10:16:39.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:39.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:39.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:16:39.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:16:39.37$vck44/va=1,8 2006.257.10:16:39.38#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.10:16:39.38#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.10:16:39.38#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:39.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:39.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:39.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:39.38#ibcon#enter wrdev, iclass 23, count 2 2006.257.10:16:39.38#ibcon#first serial, iclass 23, count 2 2006.257.10:16:39.38#ibcon#enter sib2, iclass 23, count 2 2006.257.10:16:39.38#ibcon#flushed, iclass 23, count 2 2006.257.10:16:39.38#ibcon#about to write, iclass 23, count 2 2006.257.10:16:39.38#ibcon#wrote, iclass 23, count 2 2006.257.10:16:39.38#ibcon#about to read 3, iclass 23, count 2 2006.257.10:16:39.39#ibcon#read 3, iclass 23, count 2 2006.257.10:16:39.39#ibcon#about to read 4, iclass 23, count 2 2006.257.10:16:39.39#ibcon#read 4, iclass 23, count 2 2006.257.10:16:39.39#ibcon#about to read 5, iclass 23, count 2 2006.257.10:16:39.39#ibcon#read 5, iclass 23, count 2 2006.257.10:16:39.39#ibcon#about to read 6, iclass 23, count 2 2006.257.10:16:39.39#ibcon#read 6, iclass 23, count 2 2006.257.10:16:39.39#ibcon#end of sib2, iclass 23, count 2 2006.257.10:16:39.39#ibcon#*mode == 0, iclass 23, count 2 2006.257.10:16:39.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.10:16:39.39#ibcon#[25=AT01-08\r\n] 2006.257.10:16:39.39#ibcon#*before write, iclass 23, count 2 2006.257.10:16:39.39#ibcon#enter sib2, iclass 23, count 2 2006.257.10:16:39.39#ibcon#flushed, iclass 23, count 2 2006.257.10:16:39.39#ibcon#about to write, iclass 23, count 2 2006.257.10:16:39.39#ibcon#wrote, iclass 23, count 2 2006.257.10:16:39.39#ibcon#about to read 3, iclass 23, count 2 2006.257.10:16:39.42#ibcon#read 3, iclass 23, count 2 2006.257.10:16:39.42#ibcon#about to read 4, iclass 23, count 2 2006.257.10:16:39.42#ibcon#read 4, iclass 23, count 2 2006.257.10:16:39.42#ibcon#about to read 5, iclass 23, count 2 2006.257.10:16:39.42#ibcon#read 5, iclass 23, count 2 2006.257.10:16:39.42#ibcon#about to read 6, iclass 23, count 2 2006.257.10:16:39.42#ibcon#read 6, iclass 23, count 2 2006.257.10:16:39.42#ibcon#end of sib2, iclass 23, count 2 2006.257.10:16:39.42#ibcon#*after write, iclass 23, count 2 2006.257.10:16:39.42#ibcon#*before return 0, iclass 23, count 2 2006.257.10:16:39.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:39.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:39.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.10:16:39.42#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:39.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:39.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:39.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:39.54#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:16:39.54#ibcon#first serial, iclass 23, count 0 2006.257.10:16:39.54#ibcon#enter sib2, iclass 23, count 0 2006.257.10:16:39.54#ibcon#flushed, iclass 23, count 0 2006.257.10:16:39.54#ibcon#about to write, iclass 23, count 0 2006.257.10:16:39.54#ibcon#wrote, iclass 23, count 0 2006.257.10:16:39.54#ibcon#about to read 3, iclass 23, count 0 2006.257.10:16:39.56#ibcon#read 3, iclass 23, count 0 2006.257.10:16:39.56#ibcon#about to read 4, iclass 23, count 0 2006.257.10:16:39.56#ibcon#read 4, iclass 23, count 0 2006.257.10:16:39.56#ibcon#about to read 5, iclass 23, count 0 2006.257.10:16:39.56#ibcon#read 5, iclass 23, count 0 2006.257.10:16:39.56#ibcon#about to read 6, iclass 23, count 0 2006.257.10:16:39.56#ibcon#read 6, iclass 23, count 0 2006.257.10:16:39.56#ibcon#end of sib2, iclass 23, count 0 2006.257.10:16:39.56#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:16:39.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:16:39.56#ibcon#[25=USB\r\n] 2006.257.10:16:39.56#ibcon#*before write, iclass 23, count 0 2006.257.10:16:39.56#ibcon#enter sib2, iclass 23, count 0 2006.257.10:16:39.56#ibcon#flushed, iclass 23, count 0 2006.257.10:16:39.56#ibcon#about to write, iclass 23, count 0 2006.257.10:16:39.56#ibcon#wrote, iclass 23, count 0 2006.257.10:16:39.56#ibcon#about to read 3, iclass 23, count 0 2006.257.10:16:39.59#ibcon#read 3, iclass 23, count 0 2006.257.10:16:39.59#ibcon#about to read 4, iclass 23, count 0 2006.257.10:16:39.59#ibcon#read 4, iclass 23, count 0 2006.257.10:16:39.59#ibcon#about to read 5, iclass 23, count 0 2006.257.10:16:39.59#ibcon#read 5, iclass 23, count 0 2006.257.10:16:39.59#ibcon#about to read 6, iclass 23, count 0 2006.257.10:16:39.59#ibcon#read 6, iclass 23, count 0 2006.257.10:16:39.59#ibcon#end of sib2, iclass 23, count 0 2006.257.10:16:39.59#ibcon#*after write, iclass 23, count 0 2006.257.10:16:39.59#ibcon#*before return 0, iclass 23, count 0 2006.257.10:16:39.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:39.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:39.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:16:39.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:16:39.59$vck44/valo=2,534.99 2006.257.10:16:39.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.10:16:39.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.10:16:39.60#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:39.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:39.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:39.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:39.60#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:16:39.60#ibcon#first serial, iclass 25, count 0 2006.257.10:16:39.60#ibcon#enter sib2, iclass 25, count 0 2006.257.10:16:39.60#ibcon#flushed, iclass 25, count 0 2006.257.10:16:39.60#ibcon#about to write, iclass 25, count 0 2006.257.10:16:39.60#ibcon#wrote, iclass 25, count 0 2006.257.10:16:39.60#ibcon#about to read 3, iclass 25, count 0 2006.257.10:16:39.61#ibcon#read 3, iclass 25, count 0 2006.257.10:16:39.61#ibcon#about to read 4, iclass 25, count 0 2006.257.10:16:39.61#ibcon#read 4, iclass 25, count 0 2006.257.10:16:39.61#ibcon#about to read 5, iclass 25, count 0 2006.257.10:16:39.61#ibcon#read 5, iclass 25, count 0 2006.257.10:16:39.61#ibcon#about to read 6, iclass 25, count 0 2006.257.10:16:39.61#ibcon#read 6, iclass 25, count 0 2006.257.10:16:39.61#ibcon#end of sib2, iclass 25, count 0 2006.257.10:16:39.61#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:16:39.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:16:39.61#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:16:39.61#ibcon#*before write, iclass 25, count 0 2006.257.10:16:39.61#ibcon#enter sib2, iclass 25, count 0 2006.257.10:16:39.61#ibcon#flushed, iclass 25, count 0 2006.257.10:16:39.61#ibcon#about to write, iclass 25, count 0 2006.257.10:16:39.61#ibcon#wrote, iclass 25, count 0 2006.257.10:16:39.61#ibcon#about to read 3, iclass 25, count 0 2006.257.10:16:39.65#ibcon#read 3, iclass 25, count 0 2006.257.10:16:39.65#ibcon#about to read 4, iclass 25, count 0 2006.257.10:16:39.65#ibcon#read 4, iclass 25, count 0 2006.257.10:16:39.65#ibcon#about to read 5, iclass 25, count 0 2006.257.10:16:39.65#ibcon#read 5, iclass 25, count 0 2006.257.10:16:39.65#ibcon#about to read 6, iclass 25, count 0 2006.257.10:16:39.65#ibcon#read 6, iclass 25, count 0 2006.257.10:16:39.65#ibcon#end of sib2, iclass 25, count 0 2006.257.10:16:39.65#ibcon#*after write, iclass 25, count 0 2006.257.10:16:39.65#ibcon#*before return 0, iclass 25, count 0 2006.257.10:16:39.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:39.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:39.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:16:39.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:16:39.65$vck44/va=2,7 2006.257.10:16:39.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.10:16:39.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.10:16:39.66#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:39.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:39.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:39.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:39.70#ibcon#enter wrdev, iclass 27, count 2 2006.257.10:16:39.70#ibcon#first serial, iclass 27, count 2 2006.257.10:16:39.70#ibcon#enter sib2, iclass 27, count 2 2006.257.10:16:39.70#ibcon#flushed, iclass 27, count 2 2006.257.10:16:39.70#ibcon#about to write, iclass 27, count 2 2006.257.10:16:39.70#ibcon#wrote, iclass 27, count 2 2006.257.10:16:39.70#ibcon#about to read 3, iclass 27, count 2 2006.257.10:16:39.72#ibcon#read 3, iclass 27, count 2 2006.257.10:16:39.72#ibcon#about to read 4, iclass 27, count 2 2006.257.10:16:39.72#ibcon#read 4, iclass 27, count 2 2006.257.10:16:39.72#ibcon#about to read 5, iclass 27, count 2 2006.257.10:16:39.72#ibcon#read 5, iclass 27, count 2 2006.257.10:16:39.72#ibcon#about to read 6, iclass 27, count 2 2006.257.10:16:39.72#ibcon#read 6, iclass 27, count 2 2006.257.10:16:39.72#ibcon#end of sib2, iclass 27, count 2 2006.257.10:16:39.72#ibcon#*mode == 0, iclass 27, count 2 2006.257.10:16:39.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.10:16:39.72#ibcon#[25=AT02-07\r\n] 2006.257.10:16:39.72#ibcon#*before write, iclass 27, count 2 2006.257.10:16:39.72#ibcon#enter sib2, iclass 27, count 2 2006.257.10:16:39.72#ibcon#flushed, iclass 27, count 2 2006.257.10:16:39.72#ibcon#about to write, iclass 27, count 2 2006.257.10:16:39.72#ibcon#wrote, iclass 27, count 2 2006.257.10:16:39.72#ibcon#about to read 3, iclass 27, count 2 2006.257.10:16:39.75#ibcon#read 3, iclass 27, count 2 2006.257.10:16:39.75#ibcon#about to read 4, iclass 27, count 2 2006.257.10:16:39.75#ibcon#read 4, iclass 27, count 2 2006.257.10:16:39.75#ibcon#about to read 5, iclass 27, count 2 2006.257.10:16:39.75#ibcon#read 5, iclass 27, count 2 2006.257.10:16:39.75#ibcon#about to read 6, iclass 27, count 2 2006.257.10:16:39.75#ibcon#read 6, iclass 27, count 2 2006.257.10:16:39.75#ibcon#end of sib2, iclass 27, count 2 2006.257.10:16:39.75#ibcon#*after write, iclass 27, count 2 2006.257.10:16:39.75#ibcon#*before return 0, iclass 27, count 2 2006.257.10:16:39.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:39.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:39.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.10:16:39.75#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:39.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:39.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:39.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:39.87#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:16:39.87#ibcon#first serial, iclass 27, count 0 2006.257.10:16:39.87#ibcon#enter sib2, iclass 27, count 0 2006.257.10:16:39.87#ibcon#flushed, iclass 27, count 0 2006.257.10:16:39.87#ibcon#about to write, iclass 27, count 0 2006.257.10:16:39.87#ibcon#wrote, iclass 27, count 0 2006.257.10:16:39.87#ibcon#about to read 3, iclass 27, count 0 2006.257.10:16:39.89#ibcon#read 3, iclass 27, count 0 2006.257.10:16:39.89#ibcon#about to read 4, iclass 27, count 0 2006.257.10:16:39.89#ibcon#read 4, iclass 27, count 0 2006.257.10:16:39.89#ibcon#about to read 5, iclass 27, count 0 2006.257.10:16:39.89#ibcon#read 5, iclass 27, count 0 2006.257.10:16:39.89#ibcon#about to read 6, iclass 27, count 0 2006.257.10:16:39.89#ibcon#read 6, iclass 27, count 0 2006.257.10:16:39.89#ibcon#end of sib2, iclass 27, count 0 2006.257.10:16:39.89#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:16:39.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:16:39.89#ibcon#[25=USB\r\n] 2006.257.10:16:39.89#ibcon#*before write, iclass 27, count 0 2006.257.10:16:39.89#ibcon#enter sib2, iclass 27, count 0 2006.257.10:16:39.89#ibcon#flushed, iclass 27, count 0 2006.257.10:16:39.89#ibcon#about to write, iclass 27, count 0 2006.257.10:16:39.89#ibcon#wrote, iclass 27, count 0 2006.257.10:16:39.89#ibcon#about to read 3, iclass 27, count 0 2006.257.10:16:39.92#ibcon#read 3, iclass 27, count 0 2006.257.10:16:39.92#ibcon#about to read 4, iclass 27, count 0 2006.257.10:16:39.92#ibcon#read 4, iclass 27, count 0 2006.257.10:16:39.92#ibcon#about to read 5, iclass 27, count 0 2006.257.10:16:39.92#ibcon#read 5, iclass 27, count 0 2006.257.10:16:39.92#ibcon#about to read 6, iclass 27, count 0 2006.257.10:16:39.92#ibcon#read 6, iclass 27, count 0 2006.257.10:16:39.92#ibcon#end of sib2, iclass 27, count 0 2006.257.10:16:39.92#ibcon#*after write, iclass 27, count 0 2006.257.10:16:39.92#ibcon#*before return 0, iclass 27, count 0 2006.257.10:16:39.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:39.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:39.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:16:39.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:16:39.92$vck44/valo=3,564.99 2006.257.10:16:39.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.10:16:39.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.10:16:39.92#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:39.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:39.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:39.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:39.93#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:16:39.93#ibcon#first serial, iclass 29, count 0 2006.257.10:16:39.93#ibcon#enter sib2, iclass 29, count 0 2006.257.10:16:39.93#ibcon#flushed, iclass 29, count 0 2006.257.10:16:39.93#ibcon#about to write, iclass 29, count 0 2006.257.10:16:39.93#ibcon#wrote, iclass 29, count 0 2006.257.10:16:39.93#ibcon#about to read 3, iclass 29, count 0 2006.257.10:16:39.94#ibcon#read 3, iclass 29, count 0 2006.257.10:16:39.94#ibcon#about to read 4, iclass 29, count 0 2006.257.10:16:39.94#ibcon#read 4, iclass 29, count 0 2006.257.10:16:39.94#ibcon#about to read 5, iclass 29, count 0 2006.257.10:16:39.94#ibcon#read 5, iclass 29, count 0 2006.257.10:16:39.94#ibcon#about to read 6, iclass 29, count 0 2006.257.10:16:39.94#ibcon#read 6, iclass 29, count 0 2006.257.10:16:39.94#ibcon#end of sib2, iclass 29, count 0 2006.257.10:16:39.94#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:16:39.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:16:39.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:16:39.94#ibcon#*before write, iclass 29, count 0 2006.257.10:16:39.94#ibcon#enter sib2, iclass 29, count 0 2006.257.10:16:39.94#ibcon#flushed, iclass 29, count 0 2006.257.10:16:39.94#ibcon#about to write, iclass 29, count 0 2006.257.10:16:39.94#ibcon#wrote, iclass 29, count 0 2006.257.10:16:39.94#ibcon#about to read 3, iclass 29, count 0 2006.257.10:16:39.98#ibcon#read 3, iclass 29, count 0 2006.257.10:16:39.98#ibcon#about to read 4, iclass 29, count 0 2006.257.10:16:39.98#ibcon#read 4, iclass 29, count 0 2006.257.10:16:39.98#ibcon#about to read 5, iclass 29, count 0 2006.257.10:16:39.98#ibcon#read 5, iclass 29, count 0 2006.257.10:16:39.98#ibcon#about to read 6, iclass 29, count 0 2006.257.10:16:39.98#ibcon#read 6, iclass 29, count 0 2006.257.10:16:39.98#ibcon#end of sib2, iclass 29, count 0 2006.257.10:16:39.98#ibcon#*after write, iclass 29, count 0 2006.257.10:16:39.98#ibcon#*before return 0, iclass 29, count 0 2006.257.10:16:39.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:39.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:39.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:16:39.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:16:39.98$vck44/va=3,8 2006.257.10:16:39.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.10:16:39.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.10:16:39.99#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:39.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:16:40.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:16:40.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:16:40.03#ibcon#enter wrdev, iclass 31, count 2 2006.257.10:16:40.03#ibcon#first serial, iclass 31, count 2 2006.257.10:16:40.03#ibcon#enter sib2, iclass 31, count 2 2006.257.10:16:40.03#ibcon#flushed, iclass 31, count 2 2006.257.10:16:40.03#ibcon#about to write, iclass 31, count 2 2006.257.10:16:40.03#ibcon#wrote, iclass 31, count 2 2006.257.10:16:40.03#ibcon#about to read 3, iclass 31, count 2 2006.257.10:16:40.05#ibcon#read 3, iclass 31, count 2 2006.257.10:16:40.05#ibcon#about to read 4, iclass 31, count 2 2006.257.10:16:40.05#ibcon#read 4, iclass 31, count 2 2006.257.10:16:40.05#ibcon#about to read 5, iclass 31, count 2 2006.257.10:16:40.05#ibcon#read 5, iclass 31, count 2 2006.257.10:16:40.05#ibcon#about to read 6, iclass 31, count 2 2006.257.10:16:40.05#ibcon#read 6, iclass 31, count 2 2006.257.10:16:40.05#ibcon#end of sib2, iclass 31, count 2 2006.257.10:16:40.05#ibcon#*mode == 0, iclass 31, count 2 2006.257.10:16:40.05#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.10:16:40.05#ibcon#[25=AT03-08\r\n] 2006.257.10:16:40.05#ibcon#*before write, iclass 31, count 2 2006.257.10:16:40.05#ibcon#enter sib2, iclass 31, count 2 2006.257.10:16:40.05#ibcon#flushed, iclass 31, count 2 2006.257.10:16:40.05#ibcon#about to write, iclass 31, count 2 2006.257.10:16:40.05#ibcon#wrote, iclass 31, count 2 2006.257.10:16:40.05#ibcon#about to read 3, iclass 31, count 2 2006.257.10:16:40.08#ibcon#read 3, iclass 31, count 2 2006.257.10:16:40.08#ibcon#about to read 4, iclass 31, count 2 2006.257.10:16:40.08#ibcon#read 4, iclass 31, count 2 2006.257.10:16:40.08#ibcon#about to read 5, iclass 31, count 2 2006.257.10:16:40.08#ibcon#read 5, iclass 31, count 2 2006.257.10:16:40.08#ibcon#about to read 6, iclass 31, count 2 2006.257.10:16:40.08#ibcon#read 6, iclass 31, count 2 2006.257.10:16:40.08#ibcon#end of sib2, iclass 31, count 2 2006.257.10:16:40.08#ibcon#*after write, iclass 31, count 2 2006.257.10:16:40.08#ibcon#*before return 0, iclass 31, count 2 2006.257.10:16:40.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:16:40.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:16:40.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.10:16:40.08#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:40.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:16:40.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:16:40.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:16:40.20#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:16:40.20#ibcon#first serial, iclass 31, count 0 2006.257.10:16:40.20#ibcon#enter sib2, iclass 31, count 0 2006.257.10:16:40.20#ibcon#flushed, iclass 31, count 0 2006.257.10:16:40.20#ibcon#about to write, iclass 31, count 0 2006.257.10:16:40.20#ibcon#wrote, iclass 31, count 0 2006.257.10:16:40.20#ibcon#about to read 3, iclass 31, count 0 2006.257.10:16:40.22#ibcon#read 3, iclass 31, count 0 2006.257.10:16:40.22#ibcon#about to read 4, iclass 31, count 0 2006.257.10:16:40.22#ibcon#read 4, iclass 31, count 0 2006.257.10:16:40.22#ibcon#about to read 5, iclass 31, count 0 2006.257.10:16:40.22#ibcon#read 5, iclass 31, count 0 2006.257.10:16:40.22#ibcon#about to read 6, iclass 31, count 0 2006.257.10:16:40.22#ibcon#read 6, iclass 31, count 0 2006.257.10:16:40.22#ibcon#end of sib2, iclass 31, count 0 2006.257.10:16:40.22#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:16:40.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:16:40.22#ibcon#[25=USB\r\n] 2006.257.10:16:40.22#ibcon#*before write, iclass 31, count 0 2006.257.10:16:40.22#ibcon#enter sib2, iclass 31, count 0 2006.257.10:16:40.22#ibcon#flushed, iclass 31, count 0 2006.257.10:16:40.22#ibcon#about to write, iclass 31, count 0 2006.257.10:16:40.22#ibcon#wrote, iclass 31, count 0 2006.257.10:16:40.22#ibcon#about to read 3, iclass 31, count 0 2006.257.10:16:40.25#ibcon#read 3, iclass 31, count 0 2006.257.10:16:40.25#ibcon#about to read 4, iclass 31, count 0 2006.257.10:16:40.25#ibcon#read 4, iclass 31, count 0 2006.257.10:16:40.25#ibcon#about to read 5, iclass 31, count 0 2006.257.10:16:40.25#ibcon#read 5, iclass 31, count 0 2006.257.10:16:40.25#ibcon#about to read 6, iclass 31, count 0 2006.257.10:16:40.25#ibcon#read 6, iclass 31, count 0 2006.257.10:16:40.25#ibcon#end of sib2, iclass 31, count 0 2006.257.10:16:40.25#ibcon#*after write, iclass 31, count 0 2006.257.10:16:40.25#ibcon#*before return 0, iclass 31, count 0 2006.257.10:16:40.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:16:40.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:16:40.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:16:40.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:16:40.25$vck44/valo=4,624.99 2006.257.10:16:40.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.10:16:40.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.10:16:40.26#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:40.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:16:40.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:16:40.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:16:40.26#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:16:40.26#ibcon#first serial, iclass 33, count 0 2006.257.10:16:40.26#ibcon#enter sib2, iclass 33, count 0 2006.257.10:16:40.26#ibcon#flushed, iclass 33, count 0 2006.257.10:16:40.26#ibcon#about to write, iclass 33, count 0 2006.257.10:16:40.26#ibcon#wrote, iclass 33, count 0 2006.257.10:16:40.26#ibcon#about to read 3, iclass 33, count 0 2006.257.10:16:40.27#ibcon#read 3, iclass 33, count 0 2006.257.10:16:40.27#ibcon#about to read 4, iclass 33, count 0 2006.257.10:16:40.27#ibcon#read 4, iclass 33, count 0 2006.257.10:16:40.27#ibcon#about to read 5, iclass 33, count 0 2006.257.10:16:40.27#ibcon#read 5, iclass 33, count 0 2006.257.10:16:40.27#ibcon#about to read 6, iclass 33, count 0 2006.257.10:16:40.27#ibcon#read 6, iclass 33, count 0 2006.257.10:16:40.27#ibcon#end of sib2, iclass 33, count 0 2006.257.10:16:40.27#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:16:40.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:16:40.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:16:40.27#ibcon#*before write, iclass 33, count 0 2006.257.10:16:40.27#ibcon#enter sib2, iclass 33, count 0 2006.257.10:16:40.27#ibcon#flushed, iclass 33, count 0 2006.257.10:16:40.27#ibcon#about to write, iclass 33, count 0 2006.257.10:16:40.27#ibcon#wrote, iclass 33, count 0 2006.257.10:16:40.27#ibcon#about to read 3, iclass 33, count 0 2006.257.10:16:40.31#ibcon#read 3, iclass 33, count 0 2006.257.10:16:40.31#ibcon#about to read 4, iclass 33, count 0 2006.257.10:16:40.31#ibcon#read 4, iclass 33, count 0 2006.257.10:16:40.31#ibcon#about to read 5, iclass 33, count 0 2006.257.10:16:40.31#ibcon#read 5, iclass 33, count 0 2006.257.10:16:40.31#ibcon#about to read 6, iclass 33, count 0 2006.257.10:16:40.31#ibcon#read 6, iclass 33, count 0 2006.257.10:16:40.31#ibcon#end of sib2, iclass 33, count 0 2006.257.10:16:40.31#ibcon#*after write, iclass 33, count 0 2006.257.10:16:40.31#ibcon#*before return 0, iclass 33, count 0 2006.257.10:16:40.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:16:40.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:16:40.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:16:40.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:16:40.31$vck44/va=4,7 2006.257.10:16:40.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.10:16:40.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.10:16:40.32#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:40.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:16:40.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:16:40.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:16:40.36#ibcon#enter wrdev, iclass 35, count 2 2006.257.10:16:40.36#ibcon#first serial, iclass 35, count 2 2006.257.10:16:40.36#ibcon#enter sib2, iclass 35, count 2 2006.257.10:16:40.36#ibcon#flushed, iclass 35, count 2 2006.257.10:16:40.36#ibcon#about to write, iclass 35, count 2 2006.257.10:16:40.36#ibcon#wrote, iclass 35, count 2 2006.257.10:16:40.36#ibcon#about to read 3, iclass 35, count 2 2006.257.10:16:40.38#ibcon#read 3, iclass 35, count 2 2006.257.10:16:40.38#ibcon#about to read 4, iclass 35, count 2 2006.257.10:16:40.38#ibcon#read 4, iclass 35, count 2 2006.257.10:16:40.38#ibcon#about to read 5, iclass 35, count 2 2006.257.10:16:40.38#ibcon#read 5, iclass 35, count 2 2006.257.10:16:40.38#ibcon#about to read 6, iclass 35, count 2 2006.257.10:16:40.38#ibcon#read 6, iclass 35, count 2 2006.257.10:16:40.38#ibcon#end of sib2, iclass 35, count 2 2006.257.10:16:40.38#ibcon#*mode == 0, iclass 35, count 2 2006.257.10:16:40.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.10:16:40.38#ibcon#[25=AT04-07\r\n] 2006.257.10:16:40.38#ibcon#*before write, iclass 35, count 2 2006.257.10:16:40.38#ibcon#enter sib2, iclass 35, count 2 2006.257.10:16:40.38#ibcon#flushed, iclass 35, count 2 2006.257.10:16:40.38#ibcon#about to write, iclass 35, count 2 2006.257.10:16:40.38#ibcon#wrote, iclass 35, count 2 2006.257.10:16:40.38#ibcon#about to read 3, iclass 35, count 2 2006.257.10:16:40.41#ibcon#read 3, iclass 35, count 2 2006.257.10:16:40.41#ibcon#about to read 4, iclass 35, count 2 2006.257.10:16:40.41#ibcon#read 4, iclass 35, count 2 2006.257.10:16:40.41#ibcon#about to read 5, iclass 35, count 2 2006.257.10:16:40.41#ibcon#read 5, iclass 35, count 2 2006.257.10:16:40.41#ibcon#about to read 6, iclass 35, count 2 2006.257.10:16:40.41#ibcon#read 6, iclass 35, count 2 2006.257.10:16:40.41#ibcon#end of sib2, iclass 35, count 2 2006.257.10:16:40.41#ibcon#*after write, iclass 35, count 2 2006.257.10:16:40.46#ibcon#*before return 0, iclass 35, count 2 2006.257.10:16:40.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:16:40.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:16:40.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.10:16:40.46#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:40.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:16:40.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:16:40.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:16:40.57#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:16:40.57#ibcon#first serial, iclass 35, count 0 2006.257.10:16:40.57#ibcon#enter sib2, iclass 35, count 0 2006.257.10:16:40.57#ibcon#flushed, iclass 35, count 0 2006.257.10:16:40.57#ibcon#about to write, iclass 35, count 0 2006.257.10:16:40.57#ibcon#wrote, iclass 35, count 0 2006.257.10:16:40.57#ibcon#about to read 3, iclass 35, count 0 2006.257.10:16:40.59#ibcon#read 3, iclass 35, count 0 2006.257.10:16:40.59#ibcon#about to read 4, iclass 35, count 0 2006.257.10:16:40.59#ibcon#read 4, iclass 35, count 0 2006.257.10:16:40.59#ibcon#about to read 5, iclass 35, count 0 2006.257.10:16:40.59#ibcon#read 5, iclass 35, count 0 2006.257.10:16:40.59#ibcon#about to read 6, iclass 35, count 0 2006.257.10:16:40.59#ibcon#read 6, iclass 35, count 0 2006.257.10:16:40.59#ibcon#end of sib2, iclass 35, count 0 2006.257.10:16:40.59#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:16:40.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:16:40.59#ibcon#[25=USB\r\n] 2006.257.10:16:40.59#ibcon#*before write, iclass 35, count 0 2006.257.10:16:40.59#ibcon#enter sib2, iclass 35, count 0 2006.257.10:16:40.59#ibcon#flushed, iclass 35, count 0 2006.257.10:16:40.59#ibcon#about to write, iclass 35, count 0 2006.257.10:16:40.59#ibcon#wrote, iclass 35, count 0 2006.257.10:16:40.59#ibcon#about to read 3, iclass 35, count 0 2006.257.10:16:40.62#ibcon#read 3, iclass 35, count 0 2006.257.10:16:40.62#ibcon#about to read 4, iclass 35, count 0 2006.257.10:16:40.62#ibcon#read 4, iclass 35, count 0 2006.257.10:16:40.62#ibcon#about to read 5, iclass 35, count 0 2006.257.10:16:40.62#ibcon#read 5, iclass 35, count 0 2006.257.10:16:40.62#ibcon#about to read 6, iclass 35, count 0 2006.257.10:16:40.62#ibcon#read 6, iclass 35, count 0 2006.257.10:16:40.62#ibcon#end of sib2, iclass 35, count 0 2006.257.10:16:40.62#ibcon#*after write, iclass 35, count 0 2006.257.10:16:40.62#ibcon#*before return 0, iclass 35, count 0 2006.257.10:16:40.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:16:40.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:16:40.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:16:40.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:16:40.62$vck44/valo=5,734.99 2006.257.10:16:40.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.10:16:40.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.10:16:40.63#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:40.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:40.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:40.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:40.63#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:16:40.63#ibcon#first serial, iclass 37, count 0 2006.257.10:16:40.63#ibcon#enter sib2, iclass 37, count 0 2006.257.10:16:40.63#ibcon#flushed, iclass 37, count 0 2006.257.10:16:40.63#ibcon#about to write, iclass 37, count 0 2006.257.10:16:40.63#ibcon#wrote, iclass 37, count 0 2006.257.10:16:40.63#ibcon#about to read 3, iclass 37, count 0 2006.257.10:16:40.64#ibcon#read 3, iclass 37, count 0 2006.257.10:16:40.64#ibcon#about to read 4, iclass 37, count 0 2006.257.10:16:40.64#ibcon#read 4, iclass 37, count 0 2006.257.10:16:40.64#ibcon#about to read 5, iclass 37, count 0 2006.257.10:16:40.64#ibcon#read 5, iclass 37, count 0 2006.257.10:16:40.64#ibcon#about to read 6, iclass 37, count 0 2006.257.10:16:40.64#ibcon#read 6, iclass 37, count 0 2006.257.10:16:40.64#ibcon#end of sib2, iclass 37, count 0 2006.257.10:16:40.64#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:16:40.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:16:40.64#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:16:40.64#ibcon#*before write, iclass 37, count 0 2006.257.10:16:40.64#ibcon#enter sib2, iclass 37, count 0 2006.257.10:16:40.64#ibcon#flushed, iclass 37, count 0 2006.257.10:16:40.64#ibcon#about to write, iclass 37, count 0 2006.257.10:16:40.64#ibcon#wrote, iclass 37, count 0 2006.257.10:16:40.64#ibcon#about to read 3, iclass 37, count 0 2006.257.10:16:40.68#ibcon#read 3, iclass 37, count 0 2006.257.10:16:40.68#ibcon#about to read 4, iclass 37, count 0 2006.257.10:16:40.68#ibcon#read 4, iclass 37, count 0 2006.257.10:16:40.68#ibcon#about to read 5, iclass 37, count 0 2006.257.10:16:40.68#ibcon#read 5, iclass 37, count 0 2006.257.10:16:40.68#ibcon#about to read 6, iclass 37, count 0 2006.257.10:16:40.68#ibcon#read 6, iclass 37, count 0 2006.257.10:16:40.68#ibcon#end of sib2, iclass 37, count 0 2006.257.10:16:40.68#ibcon#*after write, iclass 37, count 0 2006.257.10:16:40.68#ibcon#*before return 0, iclass 37, count 0 2006.257.10:16:40.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:40.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:40.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:16:40.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:16:40.68$vck44/va=5,4 2006.257.10:16:40.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.10:16:40.69#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.10:16:40.69#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:40.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:40.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:40.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:40.73#ibcon#enter wrdev, iclass 39, count 2 2006.257.10:16:40.73#ibcon#first serial, iclass 39, count 2 2006.257.10:16:40.73#ibcon#enter sib2, iclass 39, count 2 2006.257.10:16:40.73#ibcon#flushed, iclass 39, count 2 2006.257.10:16:40.73#ibcon#about to write, iclass 39, count 2 2006.257.10:16:40.73#ibcon#wrote, iclass 39, count 2 2006.257.10:16:40.73#ibcon#about to read 3, iclass 39, count 2 2006.257.10:16:40.75#ibcon#read 3, iclass 39, count 2 2006.257.10:16:40.75#ibcon#about to read 4, iclass 39, count 2 2006.257.10:16:40.75#ibcon#read 4, iclass 39, count 2 2006.257.10:16:40.75#ibcon#about to read 5, iclass 39, count 2 2006.257.10:16:40.75#ibcon#read 5, iclass 39, count 2 2006.257.10:16:40.75#ibcon#about to read 6, iclass 39, count 2 2006.257.10:16:40.75#ibcon#read 6, iclass 39, count 2 2006.257.10:16:40.75#ibcon#end of sib2, iclass 39, count 2 2006.257.10:16:40.75#ibcon#*mode == 0, iclass 39, count 2 2006.257.10:16:40.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.10:16:40.75#ibcon#[25=AT05-04\r\n] 2006.257.10:16:40.75#ibcon#*before write, iclass 39, count 2 2006.257.10:16:40.75#ibcon#enter sib2, iclass 39, count 2 2006.257.10:16:40.75#ibcon#flushed, iclass 39, count 2 2006.257.10:16:40.75#ibcon#about to write, iclass 39, count 2 2006.257.10:16:40.75#ibcon#wrote, iclass 39, count 2 2006.257.10:16:40.75#ibcon#about to read 3, iclass 39, count 2 2006.257.10:16:40.78#ibcon#read 3, iclass 39, count 2 2006.257.10:16:40.78#ibcon#about to read 4, iclass 39, count 2 2006.257.10:16:40.78#ibcon#read 4, iclass 39, count 2 2006.257.10:16:40.78#ibcon#about to read 5, iclass 39, count 2 2006.257.10:16:40.78#ibcon#read 5, iclass 39, count 2 2006.257.10:16:40.78#ibcon#about to read 6, iclass 39, count 2 2006.257.10:16:40.78#ibcon#read 6, iclass 39, count 2 2006.257.10:16:40.78#ibcon#end of sib2, iclass 39, count 2 2006.257.10:16:40.78#ibcon#*after write, iclass 39, count 2 2006.257.10:16:40.78#ibcon#*before return 0, iclass 39, count 2 2006.257.10:16:40.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:40.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:40.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.10:16:40.78#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:40.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:40.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:40.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:40.90#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:16:40.90#ibcon#first serial, iclass 39, count 0 2006.257.10:16:40.90#ibcon#enter sib2, iclass 39, count 0 2006.257.10:16:40.90#ibcon#flushed, iclass 39, count 0 2006.257.10:16:40.90#ibcon#about to write, iclass 39, count 0 2006.257.10:16:40.90#ibcon#wrote, iclass 39, count 0 2006.257.10:16:40.90#ibcon#about to read 3, iclass 39, count 0 2006.257.10:16:40.92#ibcon#read 3, iclass 39, count 0 2006.257.10:16:40.92#ibcon#about to read 4, iclass 39, count 0 2006.257.10:16:40.92#ibcon#read 4, iclass 39, count 0 2006.257.10:16:40.92#ibcon#about to read 5, iclass 39, count 0 2006.257.10:16:40.92#ibcon#read 5, iclass 39, count 0 2006.257.10:16:40.92#ibcon#about to read 6, iclass 39, count 0 2006.257.10:16:40.92#ibcon#read 6, iclass 39, count 0 2006.257.10:16:40.92#ibcon#end of sib2, iclass 39, count 0 2006.257.10:16:40.92#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:16:40.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:16:40.92#ibcon#[25=USB\r\n] 2006.257.10:16:40.92#ibcon#*before write, iclass 39, count 0 2006.257.10:16:40.92#ibcon#enter sib2, iclass 39, count 0 2006.257.10:16:40.92#ibcon#flushed, iclass 39, count 0 2006.257.10:16:40.92#ibcon#about to write, iclass 39, count 0 2006.257.10:16:40.92#ibcon#wrote, iclass 39, count 0 2006.257.10:16:40.92#ibcon#about to read 3, iclass 39, count 0 2006.257.10:16:40.95#ibcon#read 3, iclass 39, count 0 2006.257.10:16:40.95#ibcon#about to read 4, iclass 39, count 0 2006.257.10:16:40.95#ibcon#read 4, iclass 39, count 0 2006.257.10:16:40.95#ibcon#about to read 5, iclass 39, count 0 2006.257.10:16:40.95#ibcon#read 5, iclass 39, count 0 2006.257.10:16:40.95#ibcon#about to read 6, iclass 39, count 0 2006.257.10:16:40.95#ibcon#read 6, iclass 39, count 0 2006.257.10:16:40.95#ibcon#end of sib2, iclass 39, count 0 2006.257.10:16:40.95#ibcon#*after write, iclass 39, count 0 2006.257.10:16:40.95#ibcon#*before return 0, iclass 39, count 0 2006.257.10:16:40.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:40.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:40.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:16:40.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:16:40.95$vck44/valo=6,814.99 2006.257.10:16:40.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.10:16:40.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.10:16:40.96#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:40.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:40.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:40.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:40.96#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:16:40.96#ibcon#first serial, iclass 3, count 0 2006.257.10:16:40.96#ibcon#enter sib2, iclass 3, count 0 2006.257.10:16:40.96#ibcon#flushed, iclass 3, count 0 2006.257.10:16:40.96#ibcon#about to write, iclass 3, count 0 2006.257.10:16:40.96#ibcon#wrote, iclass 3, count 0 2006.257.10:16:40.96#ibcon#about to read 3, iclass 3, count 0 2006.257.10:16:40.97#ibcon#read 3, iclass 3, count 0 2006.257.10:16:40.97#ibcon#about to read 4, iclass 3, count 0 2006.257.10:16:40.97#ibcon#read 4, iclass 3, count 0 2006.257.10:16:40.97#ibcon#about to read 5, iclass 3, count 0 2006.257.10:16:40.97#ibcon#read 5, iclass 3, count 0 2006.257.10:16:40.97#ibcon#about to read 6, iclass 3, count 0 2006.257.10:16:40.97#ibcon#read 6, iclass 3, count 0 2006.257.10:16:40.97#ibcon#end of sib2, iclass 3, count 0 2006.257.10:16:40.97#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:16:40.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:16:40.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:16:40.97#ibcon#*before write, iclass 3, count 0 2006.257.10:16:40.97#ibcon#enter sib2, iclass 3, count 0 2006.257.10:16:40.97#ibcon#flushed, iclass 3, count 0 2006.257.10:16:40.97#ibcon#about to write, iclass 3, count 0 2006.257.10:16:40.97#ibcon#wrote, iclass 3, count 0 2006.257.10:16:40.97#ibcon#about to read 3, iclass 3, count 0 2006.257.10:16:41.01#ibcon#read 3, iclass 3, count 0 2006.257.10:16:41.01#ibcon#about to read 4, iclass 3, count 0 2006.257.10:16:41.01#ibcon#read 4, iclass 3, count 0 2006.257.10:16:41.01#ibcon#about to read 5, iclass 3, count 0 2006.257.10:16:41.01#ibcon#read 5, iclass 3, count 0 2006.257.10:16:41.01#ibcon#about to read 6, iclass 3, count 0 2006.257.10:16:41.01#ibcon#read 6, iclass 3, count 0 2006.257.10:16:41.01#ibcon#end of sib2, iclass 3, count 0 2006.257.10:16:41.01#ibcon#*after write, iclass 3, count 0 2006.257.10:16:41.01#ibcon#*before return 0, iclass 3, count 0 2006.257.10:16:41.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:41.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:41.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:16:41.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:16:41.01$vck44/va=6,4 2006.257.10:16:41.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.10:16:41.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.10:16:41.02#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:41.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:41.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:41.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:41.06#ibcon#enter wrdev, iclass 5, count 2 2006.257.10:16:41.06#ibcon#first serial, iclass 5, count 2 2006.257.10:16:41.06#ibcon#enter sib2, iclass 5, count 2 2006.257.10:16:41.06#ibcon#flushed, iclass 5, count 2 2006.257.10:16:41.06#ibcon#about to write, iclass 5, count 2 2006.257.10:16:41.06#ibcon#wrote, iclass 5, count 2 2006.257.10:16:41.06#ibcon#about to read 3, iclass 5, count 2 2006.257.10:16:41.08#ibcon#read 3, iclass 5, count 2 2006.257.10:16:41.08#ibcon#about to read 4, iclass 5, count 2 2006.257.10:16:41.08#ibcon#read 4, iclass 5, count 2 2006.257.10:16:41.08#ibcon#about to read 5, iclass 5, count 2 2006.257.10:16:41.08#ibcon#read 5, iclass 5, count 2 2006.257.10:16:41.08#ibcon#about to read 6, iclass 5, count 2 2006.257.10:16:41.08#ibcon#read 6, iclass 5, count 2 2006.257.10:16:41.08#ibcon#end of sib2, iclass 5, count 2 2006.257.10:16:41.08#ibcon#*mode == 0, iclass 5, count 2 2006.257.10:16:41.08#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.10:16:41.08#ibcon#[25=AT06-04\r\n] 2006.257.10:16:41.08#ibcon#*before write, iclass 5, count 2 2006.257.10:16:41.08#ibcon#enter sib2, iclass 5, count 2 2006.257.10:16:41.08#ibcon#flushed, iclass 5, count 2 2006.257.10:16:41.08#ibcon#about to write, iclass 5, count 2 2006.257.10:16:41.08#ibcon#wrote, iclass 5, count 2 2006.257.10:16:41.08#ibcon#about to read 3, iclass 5, count 2 2006.257.10:16:41.11#ibcon#read 3, iclass 5, count 2 2006.257.10:16:41.11#ibcon#about to read 4, iclass 5, count 2 2006.257.10:16:41.11#ibcon#read 4, iclass 5, count 2 2006.257.10:16:41.11#ibcon#about to read 5, iclass 5, count 2 2006.257.10:16:41.11#ibcon#read 5, iclass 5, count 2 2006.257.10:16:41.11#ibcon#about to read 6, iclass 5, count 2 2006.257.10:16:41.11#ibcon#read 6, iclass 5, count 2 2006.257.10:16:41.11#ibcon#end of sib2, iclass 5, count 2 2006.257.10:16:41.11#ibcon#*after write, iclass 5, count 2 2006.257.10:16:41.11#ibcon#*before return 0, iclass 5, count 2 2006.257.10:16:41.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:41.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:41.11#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.10:16:41.11#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:41.11#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:41.23#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:41.23#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:41.23#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:16:41.23#ibcon#first serial, iclass 5, count 0 2006.257.10:16:41.23#ibcon#enter sib2, iclass 5, count 0 2006.257.10:16:41.23#ibcon#flushed, iclass 5, count 0 2006.257.10:16:41.23#ibcon#about to write, iclass 5, count 0 2006.257.10:16:41.23#ibcon#wrote, iclass 5, count 0 2006.257.10:16:41.23#ibcon#about to read 3, iclass 5, count 0 2006.257.10:16:41.25#ibcon#read 3, iclass 5, count 0 2006.257.10:16:41.25#ibcon#about to read 4, iclass 5, count 0 2006.257.10:16:41.25#ibcon#read 4, iclass 5, count 0 2006.257.10:16:41.25#ibcon#about to read 5, iclass 5, count 0 2006.257.10:16:41.25#ibcon#read 5, iclass 5, count 0 2006.257.10:16:41.25#ibcon#about to read 6, iclass 5, count 0 2006.257.10:16:41.25#ibcon#read 6, iclass 5, count 0 2006.257.10:16:41.25#ibcon#end of sib2, iclass 5, count 0 2006.257.10:16:41.25#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:16:41.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:16:41.25#ibcon#[25=USB\r\n] 2006.257.10:16:41.25#ibcon#*before write, iclass 5, count 0 2006.257.10:16:41.25#ibcon#enter sib2, iclass 5, count 0 2006.257.10:16:41.25#ibcon#flushed, iclass 5, count 0 2006.257.10:16:41.25#ibcon#about to write, iclass 5, count 0 2006.257.10:16:41.25#ibcon#wrote, iclass 5, count 0 2006.257.10:16:41.25#ibcon#about to read 3, iclass 5, count 0 2006.257.10:16:41.28#ibcon#read 3, iclass 5, count 0 2006.257.10:16:41.28#ibcon#about to read 4, iclass 5, count 0 2006.257.10:16:41.28#ibcon#read 4, iclass 5, count 0 2006.257.10:16:41.28#ibcon#about to read 5, iclass 5, count 0 2006.257.10:16:41.28#ibcon#read 5, iclass 5, count 0 2006.257.10:16:41.28#ibcon#about to read 6, iclass 5, count 0 2006.257.10:16:41.28#ibcon#read 6, iclass 5, count 0 2006.257.10:16:41.28#ibcon#end of sib2, iclass 5, count 0 2006.257.10:16:41.28#ibcon#*after write, iclass 5, count 0 2006.257.10:16:41.28#ibcon#*before return 0, iclass 5, count 0 2006.257.10:16:41.28#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:41.28#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:41.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:16:41.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:16:41.28$vck44/valo=7,864.99 2006.257.10:16:41.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.10:16:41.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.10:16:41.29#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:41.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:41.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:41.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:41.29#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:16:41.29#ibcon#first serial, iclass 7, count 0 2006.257.10:16:41.29#ibcon#enter sib2, iclass 7, count 0 2006.257.10:16:41.29#ibcon#flushed, iclass 7, count 0 2006.257.10:16:41.29#ibcon#about to write, iclass 7, count 0 2006.257.10:16:41.29#ibcon#wrote, iclass 7, count 0 2006.257.10:16:41.29#ibcon#about to read 3, iclass 7, count 0 2006.257.10:16:41.30#ibcon#read 3, iclass 7, count 0 2006.257.10:16:41.30#ibcon#about to read 4, iclass 7, count 0 2006.257.10:16:41.30#ibcon#read 4, iclass 7, count 0 2006.257.10:16:41.30#ibcon#about to read 5, iclass 7, count 0 2006.257.10:16:41.30#ibcon#read 5, iclass 7, count 0 2006.257.10:16:41.30#ibcon#about to read 6, iclass 7, count 0 2006.257.10:16:41.30#ibcon#read 6, iclass 7, count 0 2006.257.10:16:41.30#ibcon#end of sib2, iclass 7, count 0 2006.257.10:16:41.30#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:16:41.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:16:41.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:16:41.30#ibcon#*before write, iclass 7, count 0 2006.257.10:16:41.30#ibcon#enter sib2, iclass 7, count 0 2006.257.10:16:41.30#ibcon#flushed, iclass 7, count 0 2006.257.10:16:41.30#ibcon#about to write, iclass 7, count 0 2006.257.10:16:41.30#ibcon#wrote, iclass 7, count 0 2006.257.10:16:41.30#ibcon#about to read 3, iclass 7, count 0 2006.257.10:16:41.34#ibcon#read 3, iclass 7, count 0 2006.257.10:16:41.34#ibcon#about to read 4, iclass 7, count 0 2006.257.10:16:41.34#ibcon#read 4, iclass 7, count 0 2006.257.10:16:41.34#ibcon#about to read 5, iclass 7, count 0 2006.257.10:16:41.34#ibcon#read 5, iclass 7, count 0 2006.257.10:16:41.34#ibcon#about to read 6, iclass 7, count 0 2006.257.10:16:41.34#ibcon#read 6, iclass 7, count 0 2006.257.10:16:41.34#ibcon#end of sib2, iclass 7, count 0 2006.257.10:16:41.34#ibcon#*after write, iclass 7, count 0 2006.257.10:16:41.34#ibcon#*before return 0, iclass 7, count 0 2006.257.10:16:41.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:41.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:41.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:16:41.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:16:41.34$vck44/va=7,4 2006.257.10:16:41.35#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.10:16:41.35#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.10:16:41.35#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:41.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:41.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:41.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:41.39#ibcon#enter wrdev, iclass 11, count 2 2006.257.10:16:41.39#ibcon#first serial, iclass 11, count 2 2006.257.10:16:41.39#ibcon#enter sib2, iclass 11, count 2 2006.257.10:16:41.39#ibcon#flushed, iclass 11, count 2 2006.257.10:16:41.39#ibcon#about to write, iclass 11, count 2 2006.257.10:16:41.39#ibcon#wrote, iclass 11, count 2 2006.257.10:16:41.39#ibcon#about to read 3, iclass 11, count 2 2006.257.10:16:41.41#ibcon#read 3, iclass 11, count 2 2006.257.10:16:41.41#ibcon#about to read 4, iclass 11, count 2 2006.257.10:16:41.41#ibcon#read 4, iclass 11, count 2 2006.257.10:16:41.41#ibcon#about to read 5, iclass 11, count 2 2006.257.10:16:41.41#ibcon#read 5, iclass 11, count 2 2006.257.10:16:41.41#ibcon#about to read 6, iclass 11, count 2 2006.257.10:16:41.41#ibcon#read 6, iclass 11, count 2 2006.257.10:16:41.41#ibcon#end of sib2, iclass 11, count 2 2006.257.10:16:41.41#ibcon#*mode == 0, iclass 11, count 2 2006.257.10:16:41.41#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.10:16:41.41#ibcon#[25=AT07-04\r\n] 2006.257.10:16:41.41#ibcon#*before write, iclass 11, count 2 2006.257.10:16:41.41#ibcon#enter sib2, iclass 11, count 2 2006.257.10:16:41.41#ibcon#flushed, iclass 11, count 2 2006.257.10:16:41.41#ibcon#about to write, iclass 11, count 2 2006.257.10:16:41.41#ibcon#wrote, iclass 11, count 2 2006.257.10:16:41.41#ibcon#about to read 3, iclass 11, count 2 2006.257.10:16:41.44#ibcon#read 3, iclass 11, count 2 2006.257.10:16:41.44#ibcon#about to read 4, iclass 11, count 2 2006.257.10:16:41.44#ibcon#read 4, iclass 11, count 2 2006.257.10:16:41.44#ibcon#about to read 5, iclass 11, count 2 2006.257.10:16:41.44#ibcon#read 5, iclass 11, count 2 2006.257.10:16:41.44#ibcon#about to read 6, iclass 11, count 2 2006.257.10:16:41.44#ibcon#read 6, iclass 11, count 2 2006.257.10:16:41.44#ibcon#end of sib2, iclass 11, count 2 2006.257.10:16:41.44#ibcon#*after write, iclass 11, count 2 2006.257.10:16:41.44#ibcon#*before return 0, iclass 11, count 2 2006.257.10:16:41.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:41.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:41.53#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.10:16:41.53#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:41.53#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:41.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:41.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:41.55#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:16:41.55#ibcon#first serial, iclass 11, count 0 2006.257.10:16:41.55#ibcon#enter sib2, iclass 11, count 0 2006.257.10:16:41.55#ibcon#flushed, iclass 11, count 0 2006.257.10:16:41.55#ibcon#about to write, iclass 11, count 0 2006.257.10:16:41.55#ibcon#wrote, iclass 11, count 0 2006.257.10:16:41.55#ibcon#about to read 3, iclass 11, count 0 2006.257.10:16:41.57#ibcon#read 3, iclass 11, count 0 2006.257.10:16:41.57#ibcon#about to read 4, iclass 11, count 0 2006.257.10:16:41.57#ibcon#read 4, iclass 11, count 0 2006.257.10:16:41.57#ibcon#about to read 5, iclass 11, count 0 2006.257.10:16:41.57#ibcon#read 5, iclass 11, count 0 2006.257.10:16:41.57#ibcon#about to read 6, iclass 11, count 0 2006.257.10:16:41.57#ibcon#read 6, iclass 11, count 0 2006.257.10:16:41.57#ibcon#end of sib2, iclass 11, count 0 2006.257.10:16:41.57#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:16:41.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:16:41.57#ibcon#[25=USB\r\n] 2006.257.10:16:41.57#ibcon#*before write, iclass 11, count 0 2006.257.10:16:41.57#ibcon#enter sib2, iclass 11, count 0 2006.257.10:16:41.57#ibcon#flushed, iclass 11, count 0 2006.257.10:16:41.57#ibcon#about to write, iclass 11, count 0 2006.257.10:16:41.57#ibcon#wrote, iclass 11, count 0 2006.257.10:16:41.57#ibcon#about to read 3, iclass 11, count 0 2006.257.10:16:41.60#ibcon#read 3, iclass 11, count 0 2006.257.10:16:41.60#ibcon#about to read 4, iclass 11, count 0 2006.257.10:16:41.60#ibcon#read 4, iclass 11, count 0 2006.257.10:16:41.60#ibcon#about to read 5, iclass 11, count 0 2006.257.10:16:41.60#ibcon#read 5, iclass 11, count 0 2006.257.10:16:41.60#ibcon#about to read 6, iclass 11, count 0 2006.257.10:16:41.60#ibcon#read 6, iclass 11, count 0 2006.257.10:16:41.60#ibcon#end of sib2, iclass 11, count 0 2006.257.10:16:41.60#ibcon#*after write, iclass 11, count 0 2006.257.10:16:41.60#ibcon#*before return 0, iclass 11, count 0 2006.257.10:16:41.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:41.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:41.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:16:41.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:16:41.60$vck44/valo=8,884.99 2006.257.10:16:41.61#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.10:16:41.61#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.10:16:41.61#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:41.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:41.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:41.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:41.61#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:16:41.61#ibcon#first serial, iclass 13, count 0 2006.257.10:16:41.61#ibcon#enter sib2, iclass 13, count 0 2006.257.10:16:41.61#ibcon#flushed, iclass 13, count 0 2006.257.10:16:41.61#ibcon#about to write, iclass 13, count 0 2006.257.10:16:41.61#ibcon#wrote, iclass 13, count 0 2006.257.10:16:41.61#ibcon#about to read 3, iclass 13, count 0 2006.257.10:16:41.62#ibcon#read 3, iclass 13, count 0 2006.257.10:16:41.62#ibcon#about to read 4, iclass 13, count 0 2006.257.10:16:41.62#ibcon#read 4, iclass 13, count 0 2006.257.10:16:41.62#ibcon#about to read 5, iclass 13, count 0 2006.257.10:16:41.62#ibcon#read 5, iclass 13, count 0 2006.257.10:16:41.62#ibcon#about to read 6, iclass 13, count 0 2006.257.10:16:41.62#ibcon#read 6, iclass 13, count 0 2006.257.10:16:41.62#ibcon#end of sib2, iclass 13, count 0 2006.257.10:16:41.62#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:16:41.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:16:41.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:16:41.62#ibcon#*before write, iclass 13, count 0 2006.257.10:16:41.62#ibcon#enter sib2, iclass 13, count 0 2006.257.10:16:41.62#ibcon#flushed, iclass 13, count 0 2006.257.10:16:41.62#ibcon#about to write, iclass 13, count 0 2006.257.10:16:41.62#ibcon#wrote, iclass 13, count 0 2006.257.10:16:41.62#ibcon#about to read 3, iclass 13, count 0 2006.257.10:16:41.66#ibcon#read 3, iclass 13, count 0 2006.257.10:16:41.66#ibcon#about to read 4, iclass 13, count 0 2006.257.10:16:41.66#ibcon#read 4, iclass 13, count 0 2006.257.10:16:41.66#ibcon#about to read 5, iclass 13, count 0 2006.257.10:16:41.66#ibcon#read 5, iclass 13, count 0 2006.257.10:16:41.66#ibcon#about to read 6, iclass 13, count 0 2006.257.10:16:41.66#ibcon#read 6, iclass 13, count 0 2006.257.10:16:41.66#ibcon#end of sib2, iclass 13, count 0 2006.257.10:16:41.66#ibcon#*after write, iclass 13, count 0 2006.257.10:16:41.66#ibcon#*before return 0, iclass 13, count 0 2006.257.10:16:41.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:41.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:41.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:16:41.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:16:41.66$vck44/va=8,4 2006.257.10:16:41.66#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.10:16:41.67#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.10:16:41.67#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:41.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:41.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:41.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:41.71#ibcon#enter wrdev, iclass 15, count 2 2006.257.10:16:41.71#ibcon#first serial, iclass 15, count 2 2006.257.10:16:41.71#ibcon#enter sib2, iclass 15, count 2 2006.257.10:16:41.71#ibcon#flushed, iclass 15, count 2 2006.257.10:16:41.71#ibcon#about to write, iclass 15, count 2 2006.257.10:16:41.71#ibcon#wrote, iclass 15, count 2 2006.257.10:16:41.71#ibcon#about to read 3, iclass 15, count 2 2006.257.10:16:41.73#ibcon#read 3, iclass 15, count 2 2006.257.10:16:41.73#ibcon#about to read 4, iclass 15, count 2 2006.257.10:16:41.73#ibcon#read 4, iclass 15, count 2 2006.257.10:16:41.73#ibcon#about to read 5, iclass 15, count 2 2006.257.10:16:41.73#ibcon#read 5, iclass 15, count 2 2006.257.10:16:41.73#ibcon#about to read 6, iclass 15, count 2 2006.257.10:16:41.73#ibcon#read 6, iclass 15, count 2 2006.257.10:16:41.73#ibcon#end of sib2, iclass 15, count 2 2006.257.10:16:41.73#ibcon#*mode == 0, iclass 15, count 2 2006.257.10:16:41.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.10:16:41.73#ibcon#[25=AT08-04\r\n] 2006.257.10:16:41.73#ibcon#*before write, iclass 15, count 2 2006.257.10:16:41.73#ibcon#enter sib2, iclass 15, count 2 2006.257.10:16:41.73#ibcon#flushed, iclass 15, count 2 2006.257.10:16:41.73#ibcon#about to write, iclass 15, count 2 2006.257.10:16:41.73#ibcon#wrote, iclass 15, count 2 2006.257.10:16:41.73#ibcon#about to read 3, iclass 15, count 2 2006.257.10:16:41.76#ibcon#read 3, iclass 15, count 2 2006.257.10:16:41.76#ibcon#about to read 4, iclass 15, count 2 2006.257.10:16:41.76#ibcon#read 4, iclass 15, count 2 2006.257.10:16:41.76#ibcon#about to read 5, iclass 15, count 2 2006.257.10:16:41.76#ibcon#read 5, iclass 15, count 2 2006.257.10:16:41.76#ibcon#about to read 6, iclass 15, count 2 2006.257.10:16:41.76#ibcon#read 6, iclass 15, count 2 2006.257.10:16:41.76#ibcon#end of sib2, iclass 15, count 2 2006.257.10:16:41.76#ibcon#*after write, iclass 15, count 2 2006.257.10:16:41.76#ibcon#*before return 0, iclass 15, count 2 2006.257.10:16:41.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:41.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:41.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.10:16:41.76#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:41.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:41.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:41.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:41.88#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:16:41.88#ibcon#first serial, iclass 15, count 0 2006.257.10:16:41.88#ibcon#enter sib2, iclass 15, count 0 2006.257.10:16:41.88#ibcon#flushed, iclass 15, count 0 2006.257.10:16:41.88#ibcon#about to write, iclass 15, count 0 2006.257.10:16:41.88#ibcon#wrote, iclass 15, count 0 2006.257.10:16:41.88#ibcon#about to read 3, iclass 15, count 0 2006.257.10:16:41.90#ibcon#read 3, iclass 15, count 0 2006.257.10:16:41.90#ibcon#about to read 4, iclass 15, count 0 2006.257.10:16:41.90#ibcon#read 4, iclass 15, count 0 2006.257.10:16:41.90#ibcon#about to read 5, iclass 15, count 0 2006.257.10:16:41.90#ibcon#read 5, iclass 15, count 0 2006.257.10:16:41.90#ibcon#about to read 6, iclass 15, count 0 2006.257.10:16:41.90#ibcon#read 6, iclass 15, count 0 2006.257.10:16:41.90#ibcon#end of sib2, iclass 15, count 0 2006.257.10:16:41.90#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:16:41.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:16:41.90#ibcon#[25=USB\r\n] 2006.257.10:16:41.90#ibcon#*before write, iclass 15, count 0 2006.257.10:16:41.90#ibcon#enter sib2, iclass 15, count 0 2006.257.10:16:41.90#ibcon#flushed, iclass 15, count 0 2006.257.10:16:41.90#ibcon#about to write, iclass 15, count 0 2006.257.10:16:41.90#ibcon#wrote, iclass 15, count 0 2006.257.10:16:41.90#ibcon#about to read 3, iclass 15, count 0 2006.257.10:16:41.93#ibcon#read 3, iclass 15, count 0 2006.257.10:16:41.93#ibcon#about to read 4, iclass 15, count 0 2006.257.10:16:41.93#ibcon#read 4, iclass 15, count 0 2006.257.10:16:41.93#ibcon#about to read 5, iclass 15, count 0 2006.257.10:16:41.93#ibcon#read 5, iclass 15, count 0 2006.257.10:16:41.93#ibcon#about to read 6, iclass 15, count 0 2006.257.10:16:41.93#ibcon#read 6, iclass 15, count 0 2006.257.10:16:41.93#ibcon#end of sib2, iclass 15, count 0 2006.257.10:16:41.93#ibcon#*after write, iclass 15, count 0 2006.257.10:16:41.93#ibcon#*before return 0, iclass 15, count 0 2006.257.10:16:41.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:41.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:41.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:16:41.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:16:41.93$vck44/vblo=1,629.99 2006.257.10:16:41.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.10:16:41.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.10:16:41.93#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:41.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:41.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:41.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:41.94#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:16:41.94#ibcon#first serial, iclass 17, count 0 2006.257.10:16:41.94#ibcon#enter sib2, iclass 17, count 0 2006.257.10:16:41.94#ibcon#flushed, iclass 17, count 0 2006.257.10:16:41.94#ibcon#about to write, iclass 17, count 0 2006.257.10:16:41.94#ibcon#wrote, iclass 17, count 0 2006.257.10:16:41.94#ibcon#about to read 3, iclass 17, count 0 2006.257.10:16:41.95#ibcon#read 3, iclass 17, count 0 2006.257.10:16:41.95#ibcon#about to read 4, iclass 17, count 0 2006.257.10:16:41.95#ibcon#read 4, iclass 17, count 0 2006.257.10:16:41.95#ibcon#about to read 5, iclass 17, count 0 2006.257.10:16:41.95#ibcon#read 5, iclass 17, count 0 2006.257.10:16:41.95#ibcon#about to read 6, iclass 17, count 0 2006.257.10:16:41.95#ibcon#read 6, iclass 17, count 0 2006.257.10:16:41.95#ibcon#end of sib2, iclass 17, count 0 2006.257.10:16:41.95#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:16:41.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:16:41.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:16:41.95#ibcon#*before write, iclass 17, count 0 2006.257.10:16:41.95#ibcon#enter sib2, iclass 17, count 0 2006.257.10:16:41.95#ibcon#flushed, iclass 17, count 0 2006.257.10:16:41.95#ibcon#about to write, iclass 17, count 0 2006.257.10:16:41.95#ibcon#wrote, iclass 17, count 0 2006.257.10:16:41.95#ibcon#about to read 3, iclass 17, count 0 2006.257.10:16:41.99#ibcon#read 3, iclass 17, count 0 2006.257.10:16:41.99#ibcon#about to read 4, iclass 17, count 0 2006.257.10:16:41.99#ibcon#read 4, iclass 17, count 0 2006.257.10:16:41.99#ibcon#about to read 5, iclass 17, count 0 2006.257.10:16:41.99#ibcon#read 5, iclass 17, count 0 2006.257.10:16:41.99#ibcon#about to read 6, iclass 17, count 0 2006.257.10:16:41.99#ibcon#read 6, iclass 17, count 0 2006.257.10:16:41.99#ibcon#end of sib2, iclass 17, count 0 2006.257.10:16:41.99#ibcon#*after write, iclass 17, count 0 2006.257.10:16:41.99#ibcon#*before return 0, iclass 17, count 0 2006.257.10:16:41.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:41.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:41.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:16:41.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:16:41.99$vck44/vb=1,4 2006.257.10:16:41.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.10:16:41.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.10:16:41.99#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:41.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:16:42.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:16:42.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:16:42.00#ibcon#enter wrdev, iclass 19, count 2 2006.257.10:16:42.00#ibcon#first serial, iclass 19, count 2 2006.257.10:16:42.00#ibcon#enter sib2, iclass 19, count 2 2006.257.10:16:42.00#ibcon#flushed, iclass 19, count 2 2006.257.10:16:42.00#ibcon#about to write, iclass 19, count 2 2006.257.10:16:42.00#ibcon#wrote, iclass 19, count 2 2006.257.10:16:42.00#ibcon#about to read 3, iclass 19, count 2 2006.257.10:16:42.01#ibcon#read 3, iclass 19, count 2 2006.257.10:16:42.01#ibcon#about to read 4, iclass 19, count 2 2006.257.10:16:42.01#ibcon#read 4, iclass 19, count 2 2006.257.10:16:42.01#ibcon#about to read 5, iclass 19, count 2 2006.257.10:16:42.01#ibcon#read 5, iclass 19, count 2 2006.257.10:16:42.01#ibcon#about to read 6, iclass 19, count 2 2006.257.10:16:42.01#ibcon#read 6, iclass 19, count 2 2006.257.10:16:42.01#ibcon#end of sib2, iclass 19, count 2 2006.257.10:16:42.01#ibcon#*mode == 0, iclass 19, count 2 2006.257.10:16:42.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.10:16:42.01#ibcon#[27=AT01-04\r\n] 2006.257.10:16:42.01#ibcon#*before write, iclass 19, count 2 2006.257.10:16:42.01#ibcon#enter sib2, iclass 19, count 2 2006.257.10:16:42.01#ibcon#flushed, iclass 19, count 2 2006.257.10:16:42.01#ibcon#about to write, iclass 19, count 2 2006.257.10:16:42.01#ibcon#wrote, iclass 19, count 2 2006.257.10:16:42.01#ibcon#about to read 3, iclass 19, count 2 2006.257.10:16:42.04#ibcon#read 3, iclass 19, count 2 2006.257.10:16:42.04#ibcon#about to read 4, iclass 19, count 2 2006.257.10:16:42.04#ibcon#read 4, iclass 19, count 2 2006.257.10:16:42.04#ibcon#about to read 5, iclass 19, count 2 2006.257.10:16:42.04#ibcon#read 5, iclass 19, count 2 2006.257.10:16:42.04#ibcon#about to read 6, iclass 19, count 2 2006.257.10:16:42.04#ibcon#read 6, iclass 19, count 2 2006.257.10:16:42.04#ibcon#end of sib2, iclass 19, count 2 2006.257.10:16:42.04#ibcon#*after write, iclass 19, count 2 2006.257.10:16:42.04#ibcon#*before return 0, iclass 19, count 2 2006.257.10:16:42.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:16:42.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:16:42.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.10:16:42.04#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:42.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:16:42.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:16:42.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:16:42.16#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:16:42.16#ibcon#first serial, iclass 19, count 0 2006.257.10:16:42.16#ibcon#enter sib2, iclass 19, count 0 2006.257.10:16:42.16#ibcon#flushed, iclass 19, count 0 2006.257.10:16:42.16#ibcon#about to write, iclass 19, count 0 2006.257.10:16:42.16#ibcon#wrote, iclass 19, count 0 2006.257.10:16:42.16#ibcon#about to read 3, iclass 19, count 0 2006.257.10:16:42.18#ibcon#read 3, iclass 19, count 0 2006.257.10:16:42.18#ibcon#about to read 4, iclass 19, count 0 2006.257.10:16:42.18#ibcon#read 4, iclass 19, count 0 2006.257.10:16:42.18#ibcon#about to read 5, iclass 19, count 0 2006.257.10:16:42.18#ibcon#read 5, iclass 19, count 0 2006.257.10:16:42.18#ibcon#about to read 6, iclass 19, count 0 2006.257.10:16:42.18#ibcon#read 6, iclass 19, count 0 2006.257.10:16:42.18#ibcon#end of sib2, iclass 19, count 0 2006.257.10:16:42.18#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:16:42.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:16:42.18#ibcon#[27=USB\r\n] 2006.257.10:16:42.18#ibcon#*before write, iclass 19, count 0 2006.257.10:16:42.18#ibcon#enter sib2, iclass 19, count 0 2006.257.10:16:42.18#ibcon#flushed, iclass 19, count 0 2006.257.10:16:42.18#ibcon#about to write, iclass 19, count 0 2006.257.10:16:42.18#ibcon#wrote, iclass 19, count 0 2006.257.10:16:42.18#ibcon#about to read 3, iclass 19, count 0 2006.257.10:16:42.21#ibcon#read 3, iclass 19, count 0 2006.257.10:16:42.21#ibcon#about to read 4, iclass 19, count 0 2006.257.10:16:42.21#ibcon#read 4, iclass 19, count 0 2006.257.10:16:42.21#ibcon#about to read 5, iclass 19, count 0 2006.257.10:16:42.21#ibcon#read 5, iclass 19, count 0 2006.257.10:16:42.21#ibcon#about to read 6, iclass 19, count 0 2006.257.10:16:42.21#ibcon#read 6, iclass 19, count 0 2006.257.10:16:42.21#ibcon#end of sib2, iclass 19, count 0 2006.257.10:16:42.21#ibcon#*after write, iclass 19, count 0 2006.257.10:16:42.21#ibcon#*before return 0, iclass 19, count 0 2006.257.10:16:42.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:16:42.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:16:42.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:16:42.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:16:42.21$vck44/vblo=2,634.99 2006.257.10:16:42.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.10:16:42.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.10:16:42.22#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:42.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:42.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:42.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:42.22#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:16:42.22#ibcon#first serial, iclass 21, count 0 2006.257.10:16:42.22#ibcon#enter sib2, iclass 21, count 0 2006.257.10:16:42.22#ibcon#flushed, iclass 21, count 0 2006.257.10:16:42.22#ibcon#about to write, iclass 21, count 0 2006.257.10:16:42.22#ibcon#wrote, iclass 21, count 0 2006.257.10:16:42.22#ibcon#about to read 3, iclass 21, count 0 2006.257.10:16:42.23#ibcon#read 3, iclass 21, count 0 2006.257.10:16:42.23#ibcon#about to read 4, iclass 21, count 0 2006.257.10:16:42.23#ibcon#read 4, iclass 21, count 0 2006.257.10:16:42.23#ibcon#about to read 5, iclass 21, count 0 2006.257.10:16:42.23#ibcon#read 5, iclass 21, count 0 2006.257.10:16:42.23#ibcon#about to read 6, iclass 21, count 0 2006.257.10:16:42.23#ibcon#read 6, iclass 21, count 0 2006.257.10:16:42.23#ibcon#end of sib2, iclass 21, count 0 2006.257.10:16:42.23#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:16:42.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:16:42.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:16:42.23#ibcon#*before write, iclass 21, count 0 2006.257.10:16:42.23#ibcon#enter sib2, iclass 21, count 0 2006.257.10:16:42.23#ibcon#flushed, iclass 21, count 0 2006.257.10:16:42.23#ibcon#about to write, iclass 21, count 0 2006.257.10:16:42.23#ibcon#wrote, iclass 21, count 0 2006.257.10:16:42.23#ibcon#about to read 3, iclass 21, count 0 2006.257.10:16:42.27#ibcon#read 3, iclass 21, count 0 2006.257.10:16:42.27#ibcon#about to read 4, iclass 21, count 0 2006.257.10:16:42.27#ibcon#read 4, iclass 21, count 0 2006.257.10:16:42.27#ibcon#about to read 5, iclass 21, count 0 2006.257.10:16:42.27#ibcon#read 5, iclass 21, count 0 2006.257.10:16:42.27#ibcon#about to read 6, iclass 21, count 0 2006.257.10:16:42.27#ibcon#read 6, iclass 21, count 0 2006.257.10:16:42.27#ibcon#end of sib2, iclass 21, count 0 2006.257.10:16:42.27#ibcon#*after write, iclass 21, count 0 2006.257.10:16:42.27#ibcon#*before return 0, iclass 21, count 0 2006.257.10:16:42.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:42.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:16:42.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:16:42.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:16:42.27$vck44/vb=2,5 2006.257.10:16:42.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.10:16:42.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.10:16:42.28#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:42.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:42.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:42.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:42.32#ibcon#enter wrdev, iclass 23, count 2 2006.257.10:16:42.32#ibcon#first serial, iclass 23, count 2 2006.257.10:16:42.32#ibcon#enter sib2, iclass 23, count 2 2006.257.10:16:42.32#ibcon#flushed, iclass 23, count 2 2006.257.10:16:42.32#ibcon#about to write, iclass 23, count 2 2006.257.10:16:42.32#ibcon#wrote, iclass 23, count 2 2006.257.10:16:42.32#ibcon#about to read 3, iclass 23, count 2 2006.257.10:16:42.34#ibcon#read 3, iclass 23, count 2 2006.257.10:16:42.34#ibcon#about to read 4, iclass 23, count 2 2006.257.10:16:42.34#ibcon#read 4, iclass 23, count 2 2006.257.10:16:42.34#ibcon#about to read 5, iclass 23, count 2 2006.257.10:16:42.34#ibcon#read 5, iclass 23, count 2 2006.257.10:16:42.34#ibcon#about to read 6, iclass 23, count 2 2006.257.10:16:42.34#ibcon#read 6, iclass 23, count 2 2006.257.10:16:42.34#ibcon#end of sib2, iclass 23, count 2 2006.257.10:16:42.34#ibcon#*mode == 0, iclass 23, count 2 2006.257.10:16:42.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.10:16:42.34#ibcon#[27=AT02-05\r\n] 2006.257.10:16:42.34#ibcon#*before write, iclass 23, count 2 2006.257.10:16:42.34#ibcon#enter sib2, iclass 23, count 2 2006.257.10:16:42.34#ibcon#flushed, iclass 23, count 2 2006.257.10:16:42.34#ibcon#about to write, iclass 23, count 2 2006.257.10:16:42.34#ibcon#wrote, iclass 23, count 2 2006.257.10:16:42.34#ibcon#about to read 3, iclass 23, count 2 2006.257.10:16:42.37#ibcon#read 3, iclass 23, count 2 2006.257.10:16:42.37#ibcon#about to read 4, iclass 23, count 2 2006.257.10:16:42.37#ibcon#read 4, iclass 23, count 2 2006.257.10:16:42.37#ibcon#about to read 5, iclass 23, count 2 2006.257.10:16:42.37#ibcon#read 5, iclass 23, count 2 2006.257.10:16:42.37#ibcon#about to read 6, iclass 23, count 2 2006.257.10:16:42.37#ibcon#read 6, iclass 23, count 2 2006.257.10:16:42.37#ibcon#end of sib2, iclass 23, count 2 2006.257.10:16:42.37#ibcon#*after write, iclass 23, count 2 2006.257.10:16:42.37#ibcon#*before return 0, iclass 23, count 2 2006.257.10:16:42.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:42.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:16:42.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.10:16:42.37#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:42.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:42.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:42.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:42.49#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:16:42.49#ibcon#first serial, iclass 23, count 0 2006.257.10:16:42.49#ibcon#enter sib2, iclass 23, count 0 2006.257.10:16:42.49#ibcon#flushed, iclass 23, count 0 2006.257.10:16:42.49#ibcon#about to write, iclass 23, count 0 2006.257.10:16:42.49#ibcon#wrote, iclass 23, count 0 2006.257.10:16:42.49#ibcon#about to read 3, iclass 23, count 0 2006.257.10:16:42.51#ibcon#read 3, iclass 23, count 0 2006.257.10:16:42.51#ibcon#about to read 4, iclass 23, count 0 2006.257.10:16:42.51#ibcon#read 4, iclass 23, count 0 2006.257.10:16:42.51#ibcon#about to read 5, iclass 23, count 0 2006.257.10:16:42.51#ibcon#read 5, iclass 23, count 0 2006.257.10:16:42.51#ibcon#about to read 6, iclass 23, count 0 2006.257.10:16:42.51#ibcon#read 6, iclass 23, count 0 2006.257.10:16:42.51#ibcon#end of sib2, iclass 23, count 0 2006.257.10:16:42.51#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:16:42.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:16:42.51#ibcon#[27=USB\r\n] 2006.257.10:16:42.51#ibcon#*before write, iclass 23, count 0 2006.257.10:16:42.51#ibcon#enter sib2, iclass 23, count 0 2006.257.10:16:42.51#ibcon#flushed, iclass 23, count 0 2006.257.10:16:42.51#ibcon#about to write, iclass 23, count 0 2006.257.10:16:42.51#ibcon#wrote, iclass 23, count 0 2006.257.10:16:42.51#ibcon#about to read 3, iclass 23, count 0 2006.257.10:16:42.54#ibcon#read 3, iclass 23, count 0 2006.257.10:16:42.54#ibcon#about to read 4, iclass 23, count 0 2006.257.10:16:42.54#ibcon#read 4, iclass 23, count 0 2006.257.10:16:42.54#ibcon#about to read 5, iclass 23, count 0 2006.257.10:16:42.54#ibcon#read 5, iclass 23, count 0 2006.257.10:16:42.54#ibcon#about to read 6, iclass 23, count 0 2006.257.10:16:42.54#ibcon#read 6, iclass 23, count 0 2006.257.10:16:42.54#ibcon#end of sib2, iclass 23, count 0 2006.257.10:16:42.54#ibcon#*after write, iclass 23, count 0 2006.257.10:16:42.54#ibcon#*before return 0, iclass 23, count 0 2006.257.10:16:42.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:42.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:16:42.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:16:42.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:16:42.54$vck44/vblo=3,649.99 2006.257.10:16:42.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.10:16:42.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.10:16:42.55#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:42.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:42.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:42.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:42.55#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:16:42.55#ibcon#first serial, iclass 25, count 0 2006.257.10:16:42.55#ibcon#enter sib2, iclass 25, count 0 2006.257.10:16:42.55#ibcon#flushed, iclass 25, count 0 2006.257.10:16:42.57#ibcon#about to write, iclass 25, count 0 2006.257.10:16:42.57#ibcon#wrote, iclass 25, count 0 2006.257.10:16:42.57#ibcon#about to read 3, iclass 25, count 0 2006.257.10:16:42.58#ibcon#read 3, iclass 25, count 0 2006.257.10:16:42.58#ibcon#about to read 4, iclass 25, count 0 2006.257.10:16:42.58#ibcon#read 4, iclass 25, count 0 2006.257.10:16:42.58#ibcon#about to read 5, iclass 25, count 0 2006.257.10:16:42.58#ibcon#read 5, iclass 25, count 0 2006.257.10:16:42.58#ibcon#about to read 6, iclass 25, count 0 2006.257.10:16:42.58#ibcon#read 6, iclass 25, count 0 2006.257.10:16:42.58#ibcon#end of sib2, iclass 25, count 0 2006.257.10:16:42.58#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:16:42.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:16:42.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:16:42.58#ibcon#*before write, iclass 25, count 0 2006.257.10:16:42.58#ibcon#enter sib2, iclass 25, count 0 2006.257.10:16:42.58#ibcon#flushed, iclass 25, count 0 2006.257.10:16:42.58#ibcon#about to write, iclass 25, count 0 2006.257.10:16:42.58#ibcon#wrote, iclass 25, count 0 2006.257.10:16:42.58#ibcon#about to read 3, iclass 25, count 0 2006.257.10:16:42.62#ibcon#read 3, iclass 25, count 0 2006.257.10:16:42.62#ibcon#about to read 4, iclass 25, count 0 2006.257.10:16:42.62#ibcon#read 4, iclass 25, count 0 2006.257.10:16:42.62#ibcon#about to read 5, iclass 25, count 0 2006.257.10:16:42.62#ibcon#read 5, iclass 25, count 0 2006.257.10:16:42.62#ibcon#about to read 6, iclass 25, count 0 2006.257.10:16:42.62#ibcon#read 6, iclass 25, count 0 2006.257.10:16:42.62#ibcon#end of sib2, iclass 25, count 0 2006.257.10:16:42.62#ibcon#*after write, iclass 25, count 0 2006.257.10:16:42.62#ibcon#*before return 0, iclass 25, count 0 2006.257.10:16:42.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:42.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:16:42.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:16:42.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:16:42.62$vck44/vb=3,4 2006.257.10:16:42.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.10:16:42.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.10:16:42.63#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:42.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:42.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:42.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:42.65#ibcon#enter wrdev, iclass 27, count 2 2006.257.10:16:42.65#ibcon#first serial, iclass 27, count 2 2006.257.10:16:42.65#ibcon#enter sib2, iclass 27, count 2 2006.257.10:16:42.65#ibcon#flushed, iclass 27, count 2 2006.257.10:16:42.65#ibcon#about to write, iclass 27, count 2 2006.257.10:16:42.65#ibcon#wrote, iclass 27, count 2 2006.257.10:16:42.65#ibcon#about to read 3, iclass 27, count 2 2006.257.10:16:42.67#ibcon#read 3, iclass 27, count 2 2006.257.10:16:42.67#ibcon#about to read 4, iclass 27, count 2 2006.257.10:16:42.67#ibcon#read 4, iclass 27, count 2 2006.257.10:16:42.67#ibcon#about to read 5, iclass 27, count 2 2006.257.10:16:42.67#ibcon#read 5, iclass 27, count 2 2006.257.10:16:42.67#ibcon#about to read 6, iclass 27, count 2 2006.257.10:16:42.67#ibcon#read 6, iclass 27, count 2 2006.257.10:16:42.67#ibcon#end of sib2, iclass 27, count 2 2006.257.10:16:42.67#ibcon#*mode == 0, iclass 27, count 2 2006.257.10:16:42.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.10:16:42.67#ibcon#[27=AT03-04\r\n] 2006.257.10:16:42.67#ibcon#*before write, iclass 27, count 2 2006.257.10:16:42.67#ibcon#enter sib2, iclass 27, count 2 2006.257.10:16:42.67#ibcon#flushed, iclass 27, count 2 2006.257.10:16:42.67#ibcon#about to write, iclass 27, count 2 2006.257.10:16:42.67#ibcon#wrote, iclass 27, count 2 2006.257.10:16:42.67#ibcon#about to read 3, iclass 27, count 2 2006.257.10:16:42.70#ibcon#read 3, iclass 27, count 2 2006.257.10:16:42.70#ibcon#about to read 4, iclass 27, count 2 2006.257.10:16:42.70#ibcon#read 4, iclass 27, count 2 2006.257.10:16:42.70#ibcon#about to read 5, iclass 27, count 2 2006.257.10:16:42.70#ibcon#read 5, iclass 27, count 2 2006.257.10:16:42.70#ibcon#about to read 6, iclass 27, count 2 2006.257.10:16:42.70#ibcon#read 6, iclass 27, count 2 2006.257.10:16:42.70#ibcon#end of sib2, iclass 27, count 2 2006.257.10:16:42.70#ibcon#*after write, iclass 27, count 2 2006.257.10:16:42.70#ibcon#*before return 0, iclass 27, count 2 2006.257.10:16:42.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:42.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:16:42.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.10:16:42.70#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:42.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:42.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:42.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:42.82#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:16:42.82#ibcon#first serial, iclass 27, count 0 2006.257.10:16:42.82#ibcon#enter sib2, iclass 27, count 0 2006.257.10:16:42.82#ibcon#flushed, iclass 27, count 0 2006.257.10:16:42.82#ibcon#about to write, iclass 27, count 0 2006.257.10:16:42.82#ibcon#wrote, iclass 27, count 0 2006.257.10:16:42.82#ibcon#about to read 3, iclass 27, count 0 2006.257.10:16:42.84#ibcon#read 3, iclass 27, count 0 2006.257.10:16:42.84#ibcon#about to read 4, iclass 27, count 0 2006.257.10:16:42.84#ibcon#read 4, iclass 27, count 0 2006.257.10:16:42.84#ibcon#about to read 5, iclass 27, count 0 2006.257.10:16:42.84#ibcon#read 5, iclass 27, count 0 2006.257.10:16:42.84#ibcon#about to read 6, iclass 27, count 0 2006.257.10:16:42.84#ibcon#read 6, iclass 27, count 0 2006.257.10:16:42.84#ibcon#end of sib2, iclass 27, count 0 2006.257.10:16:42.84#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:16:42.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:16:42.84#ibcon#[27=USB\r\n] 2006.257.10:16:42.84#ibcon#*before write, iclass 27, count 0 2006.257.10:16:42.84#ibcon#enter sib2, iclass 27, count 0 2006.257.10:16:42.84#ibcon#flushed, iclass 27, count 0 2006.257.10:16:42.84#ibcon#about to write, iclass 27, count 0 2006.257.10:16:42.84#ibcon#wrote, iclass 27, count 0 2006.257.10:16:42.84#ibcon#about to read 3, iclass 27, count 0 2006.257.10:16:42.87#ibcon#read 3, iclass 27, count 0 2006.257.10:16:42.87#ibcon#about to read 4, iclass 27, count 0 2006.257.10:16:42.87#ibcon#read 4, iclass 27, count 0 2006.257.10:16:42.87#ibcon#about to read 5, iclass 27, count 0 2006.257.10:16:42.87#ibcon#read 5, iclass 27, count 0 2006.257.10:16:42.87#ibcon#about to read 6, iclass 27, count 0 2006.257.10:16:42.87#ibcon#read 6, iclass 27, count 0 2006.257.10:16:42.87#ibcon#end of sib2, iclass 27, count 0 2006.257.10:16:42.87#ibcon#*after write, iclass 27, count 0 2006.257.10:16:42.87#ibcon#*before return 0, iclass 27, count 0 2006.257.10:16:42.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:42.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:16:42.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:16:42.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:16:42.87$vck44/vblo=4,679.99 2006.257.10:16:42.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.10:16:42.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.10:16:42.88#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:42.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:42.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:42.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:42.88#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:16:42.88#ibcon#first serial, iclass 29, count 0 2006.257.10:16:42.88#ibcon#enter sib2, iclass 29, count 0 2006.257.10:16:42.88#ibcon#flushed, iclass 29, count 0 2006.257.10:16:42.88#ibcon#about to write, iclass 29, count 0 2006.257.10:16:42.88#ibcon#wrote, iclass 29, count 0 2006.257.10:16:42.88#ibcon#about to read 3, iclass 29, count 0 2006.257.10:16:42.89#ibcon#read 3, iclass 29, count 0 2006.257.10:16:42.89#ibcon#about to read 4, iclass 29, count 0 2006.257.10:16:42.89#ibcon#read 4, iclass 29, count 0 2006.257.10:16:42.89#ibcon#about to read 5, iclass 29, count 0 2006.257.10:16:42.89#ibcon#read 5, iclass 29, count 0 2006.257.10:16:42.89#ibcon#about to read 6, iclass 29, count 0 2006.257.10:16:42.89#ibcon#read 6, iclass 29, count 0 2006.257.10:16:42.89#ibcon#end of sib2, iclass 29, count 0 2006.257.10:16:42.89#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:16:42.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:16:42.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:16:42.89#ibcon#*before write, iclass 29, count 0 2006.257.10:16:42.89#ibcon#enter sib2, iclass 29, count 0 2006.257.10:16:42.89#ibcon#flushed, iclass 29, count 0 2006.257.10:16:42.89#ibcon#about to write, iclass 29, count 0 2006.257.10:16:42.89#ibcon#wrote, iclass 29, count 0 2006.257.10:16:42.89#ibcon#about to read 3, iclass 29, count 0 2006.257.10:16:42.93#ibcon#read 3, iclass 29, count 0 2006.257.10:16:42.93#ibcon#about to read 4, iclass 29, count 0 2006.257.10:16:42.93#ibcon#read 4, iclass 29, count 0 2006.257.10:16:42.93#ibcon#about to read 5, iclass 29, count 0 2006.257.10:16:42.93#ibcon#read 5, iclass 29, count 0 2006.257.10:16:42.93#ibcon#about to read 6, iclass 29, count 0 2006.257.10:16:42.93#ibcon#read 6, iclass 29, count 0 2006.257.10:16:42.93#ibcon#end of sib2, iclass 29, count 0 2006.257.10:16:42.93#ibcon#*after write, iclass 29, count 0 2006.257.10:16:42.93#ibcon#*before return 0, iclass 29, count 0 2006.257.10:16:42.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:42.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:16:42.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:16:42.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:16:42.93$vck44/vb=4,5 2006.257.10:16:42.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.10:16:42.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.10:16:42.94#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:42.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:16:42.96#abcon#<5=/14 1.0 2.7 19.05 961013.6\r\n> 2006.257.10:16:42.98#abcon#{5=INTERFACE CLEAR} 2006.257.10:16:42.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:16:42.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:16:42.98#ibcon#enter wrdev, iclass 32, count 2 2006.257.10:16:42.98#ibcon#first serial, iclass 32, count 2 2006.257.10:16:42.98#ibcon#enter sib2, iclass 32, count 2 2006.257.10:16:42.98#ibcon#flushed, iclass 32, count 2 2006.257.10:16:42.98#ibcon#about to write, iclass 32, count 2 2006.257.10:16:42.98#ibcon#wrote, iclass 32, count 2 2006.257.10:16:42.98#ibcon#about to read 3, iclass 32, count 2 2006.257.10:16:43.00#ibcon#read 3, iclass 32, count 2 2006.257.10:16:43.00#ibcon#about to read 4, iclass 32, count 2 2006.257.10:16:43.00#ibcon#read 4, iclass 32, count 2 2006.257.10:16:43.00#ibcon#about to read 5, iclass 32, count 2 2006.257.10:16:43.00#ibcon#read 5, iclass 32, count 2 2006.257.10:16:43.00#ibcon#about to read 6, iclass 32, count 2 2006.257.10:16:43.00#ibcon#read 6, iclass 32, count 2 2006.257.10:16:43.00#ibcon#end of sib2, iclass 32, count 2 2006.257.10:16:43.00#ibcon#*mode == 0, iclass 32, count 2 2006.257.10:16:43.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.10:16:43.00#ibcon#[27=AT04-05\r\n] 2006.257.10:16:43.00#ibcon#*before write, iclass 32, count 2 2006.257.10:16:43.00#ibcon#enter sib2, iclass 32, count 2 2006.257.10:16:43.00#ibcon#flushed, iclass 32, count 2 2006.257.10:16:43.00#ibcon#about to write, iclass 32, count 2 2006.257.10:16:43.00#ibcon#wrote, iclass 32, count 2 2006.257.10:16:43.00#ibcon#about to read 3, iclass 32, count 2 2006.257.10:16:43.03#ibcon#read 3, iclass 32, count 2 2006.257.10:16:43.03#ibcon#about to read 4, iclass 32, count 2 2006.257.10:16:43.03#ibcon#read 4, iclass 32, count 2 2006.257.10:16:43.03#ibcon#about to read 5, iclass 32, count 2 2006.257.10:16:43.03#ibcon#read 5, iclass 32, count 2 2006.257.10:16:43.03#ibcon#about to read 6, iclass 32, count 2 2006.257.10:16:43.03#ibcon#read 6, iclass 32, count 2 2006.257.10:16:43.03#ibcon#end of sib2, iclass 32, count 2 2006.257.10:16:43.03#ibcon#*after write, iclass 32, count 2 2006.257.10:16:43.03#ibcon#*before return 0, iclass 32, count 2 2006.257.10:16:43.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:16:43.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:16:43.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.10:16:43.03#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:43.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:16:43.04#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:16:43.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:16:43.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:16:43.15#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:16:43.15#ibcon#first serial, iclass 32, count 0 2006.257.10:16:43.15#ibcon#enter sib2, iclass 32, count 0 2006.257.10:16:43.15#ibcon#flushed, iclass 32, count 0 2006.257.10:16:43.15#ibcon#about to write, iclass 32, count 0 2006.257.10:16:43.15#ibcon#wrote, iclass 32, count 0 2006.257.10:16:43.15#ibcon#about to read 3, iclass 32, count 0 2006.257.10:16:43.17#ibcon#read 3, iclass 32, count 0 2006.257.10:16:43.17#ibcon#about to read 4, iclass 32, count 0 2006.257.10:16:43.17#ibcon#read 4, iclass 32, count 0 2006.257.10:16:43.17#ibcon#about to read 5, iclass 32, count 0 2006.257.10:16:43.17#ibcon#read 5, iclass 32, count 0 2006.257.10:16:43.17#ibcon#about to read 6, iclass 32, count 0 2006.257.10:16:43.17#ibcon#read 6, iclass 32, count 0 2006.257.10:16:43.17#ibcon#end of sib2, iclass 32, count 0 2006.257.10:16:43.17#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:16:43.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:16:43.17#ibcon#[27=USB\r\n] 2006.257.10:16:43.17#ibcon#*before write, iclass 32, count 0 2006.257.10:16:43.17#ibcon#enter sib2, iclass 32, count 0 2006.257.10:16:43.17#ibcon#flushed, iclass 32, count 0 2006.257.10:16:43.17#ibcon#about to write, iclass 32, count 0 2006.257.10:16:43.17#ibcon#wrote, iclass 32, count 0 2006.257.10:16:43.17#ibcon#about to read 3, iclass 32, count 0 2006.257.10:16:43.20#ibcon#read 3, iclass 32, count 0 2006.257.10:16:43.20#ibcon#about to read 4, iclass 32, count 0 2006.257.10:16:43.20#ibcon#read 4, iclass 32, count 0 2006.257.10:16:43.20#ibcon#about to read 5, iclass 32, count 0 2006.257.10:16:43.20#ibcon#read 5, iclass 32, count 0 2006.257.10:16:43.20#ibcon#about to read 6, iclass 32, count 0 2006.257.10:16:43.20#ibcon#read 6, iclass 32, count 0 2006.257.10:16:43.20#ibcon#end of sib2, iclass 32, count 0 2006.257.10:16:43.20#ibcon#*after write, iclass 32, count 0 2006.257.10:16:43.20#ibcon#*before return 0, iclass 32, count 0 2006.257.10:16:43.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:16:43.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:16:43.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:16:43.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:16:43.20$vck44/vblo=5,709.99 2006.257.10:16:43.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.10:16:43.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.10:16:43.21#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:43.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:43.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:43.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:43.21#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:16:43.21#ibcon#first serial, iclass 37, count 0 2006.257.10:16:43.21#ibcon#enter sib2, iclass 37, count 0 2006.257.10:16:43.21#ibcon#flushed, iclass 37, count 0 2006.257.10:16:43.21#ibcon#about to write, iclass 37, count 0 2006.257.10:16:43.21#ibcon#wrote, iclass 37, count 0 2006.257.10:16:43.21#ibcon#about to read 3, iclass 37, count 0 2006.257.10:16:43.22#ibcon#read 3, iclass 37, count 0 2006.257.10:16:43.22#ibcon#about to read 4, iclass 37, count 0 2006.257.10:16:43.22#ibcon#read 4, iclass 37, count 0 2006.257.10:16:43.22#ibcon#about to read 5, iclass 37, count 0 2006.257.10:16:43.22#ibcon#read 5, iclass 37, count 0 2006.257.10:16:43.22#ibcon#about to read 6, iclass 37, count 0 2006.257.10:16:43.22#ibcon#read 6, iclass 37, count 0 2006.257.10:16:43.22#ibcon#end of sib2, iclass 37, count 0 2006.257.10:16:43.22#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:16:43.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:16:43.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:16:43.22#ibcon#*before write, iclass 37, count 0 2006.257.10:16:43.22#ibcon#enter sib2, iclass 37, count 0 2006.257.10:16:43.22#ibcon#flushed, iclass 37, count 0 2006.257.10:16:43.22#ibcon#about to write, iclass 37, count 0 2006.257.10:16:43.22#ibcon#wrote, iclass 37, count 0 2006.257.10:16:43.22#ibcon#about to read 3, iclass 37, count 0 2006.257.10:16:43.26#ibcon#read 3, iclass 37, count 0 2006.257.10:16:43.26#ibcon#about to read 4, iclass 37, count 0 2006.257.10:16:43.26#ibcon#read 4, iclass 37, count 0 2006.257.10:16:43.26#ibcon#about to read 5, iclass 37, count 0 2006.257.10:16:43.26#ibcon#read 5, iclass 37, count 0 2006.257.10:16:43.26#ibcon#about to read 6, iclass 37, count 0 2006.257.10:16:43.26#ibcon#read 6, iclass 37, count 0 2006.257.10:16:43.26#ibcon#end of sib2, iclass 37, count 0 2006.257.10:16:43.26#ibcon#*after write, iclass 37, count 0 2006.257.10:16:43.26#ibcon#*before return 0, iclass 37, count 0 2006.257.10:16:43.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:43.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:16:43.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:16:43.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:16:43.26$vck44/vb=5,4 2006.257.10:16:43.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.10:16:43.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.10:16:43.27#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:43.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:43.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:43.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:43.31#ibcon#enter wrdev, iclass 39, count 2 2006.257.10:16:43.31#ibcon#first serial, iclass 39, count 2 2006.257.10:16:43.31#ibcon#enter sib2, iclass 39, count 2 2006.257.10:16:43.31#ibcon#flushed, iclass 39, count 2 2006.257.10:16:43.31#ibcon#about to write, iclass 39, count 2 2006.257.10:16:43.31#ibcon#wrote, iclass 39, count 2 2006.257.10:16:43.31#ibcon#about to read 3, iclass 39, count 2 2006.257.10:16:43.33#ibcon#read 3, iclass 39, count 2 2006.257.10:16:43.33#ibcon#about to read 4, iclass 39, count 2 2006.257.10:16:43.33#ibcon#read 4, iclass 39, count 2 2006.257.10:16:43.33#ibcon#about to read 5, iclass 39, count 2 2006.257.10:16:43.33#ibcon#read 5, iclass 39, count 2 2006.257.10:16:43.33#ibcon#about to read 6, iclass 39, count 2 2006.257.10:16:43.33#ibcon#read 6, iclass 39, count 2 2006.257.10:16:43.33#ibcon#end of sib2, iclass 39, count 2 2006.257.10:16:43.33#ibcon#*mode == 0, iclass 39, count 2 2006.257.10:16:43.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.10:16:43.33#ibcon#[27=AT05-04\r\n] 2006.257.10:16:43.33#ibcon#*before write, iclass 39, count 2 2006.257.10:16:43.33#ibcon#enter sib2, iclass 39, count 2 2006.257.10:16:43.33#ibcon#flushed, iclass 39, count 2 2006.257.10:16:43.33#ibcon#about to write, iclass 39, count 2 2006.257.10:16:43.33#ibcon#wrote, iclass 39, count 2 2006.257.10:16:43.33#ibcon#about to read 3, iclass 39, count 2 2006.257.10:16:43.36#ibcon#read 3, iclass 39, count 2 2006.257.10:16:43.36#ibcon#about to read 4, iclass 39, count 2 2006.257.10:16:43.36#ibcon#read 4, iclass 39, count 2 2006.257.10:16:43.36#ibcon#about to read 5, iclass 39, count 2 2006.257.10:16:43.36#ibcon#read 5, iclass 39, count 2 2006.257.10:16:43.36#ibcon#about to read 6, iclass 39, count 2 2006.257.10:16:43.36#ibcon#read 6, iclass 39, count 2 2006.257.10:16:43.36#ibcon#end of sib2, iclass 39, count 2 2006.257.10:16:43.36#ibcon#*after write, iclass 39, count 2 2006.257.10:16:43.36#ibcon#*before return 0, iclass 39, count 2 2006.257.10:16:43.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:43.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:16:43.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.10:16:43.36#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:43.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:43.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:43.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:43.48#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:16:43.48#ibcon#first serial, iclass 39, count 0 2006.257.10:16:43.48#ibcon#enter sib2, iclass 39, count 0 2006.257.10:16:43.48#ibcon#flushed, iclass 39, count 0 2006.257.10:16:43.48#ibcon#about to write, iclass 39, count 0 2006.257.10:16:43.48#ibcon#wrote, iclass 39, count 0 2006.257.10:16:43.48#ibcon#about to read 3, iclass 39, count 0 2006.257.10:16:43.50#ibcon#read 3, iclass 39, count 0 2006.257.10:16:43.50#ibcon#about to read 4, iclass 39, count 0 2006.257.10:16:43.50#ibcon#read 4, iclass 39, count 0 2006.257.10:16:43.50#ibcon#about to read 5, iclass 39, count 0 2006.257.10:16:43.50#ibcon#read 5, iclass 39, count 0 2006.257.10:16:43.50#ibcon#about to read 6, iclass 39, count 0 2006.257.10:16:43.50#ibcon#read 6, iclass 39, count 0 2006.257.10:16:43.50#ibcon#end of sib2, iclass 39, count 0 2006.257.10:16:43.50#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:16:43.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:16:43.50#ibcon#[27=USB\r\n] 2006.257.10:16:43.50#ibcon#*before write, iclass 39, count 0 2006.257.10:16:43.50#ibcon#enter sib2, iclass 39, count 0 2006.257.10:16:43.50#ibcon#flushed, iclass 39, count 0 2006.257.10:16:43.50#ibcon#about to write, iclass 39, count 0 2006.257.10:16:43.50#ibcon#wrote, iclass 39, count 0 2006.257.10:16:43.50#ibcon#about to read 3, iclass 39, count 0 2006.257.10:16:43.53#ibcon#read 3, iclass 39, count 0 2006.257.10:16:43.53#ibcon#about to read 4, iclass 39, count 0 2006.257.10:16:43.53#ibcon#read 4, iclass 39, count 0 2006.257.10:16:43.53#ibcon#about to read 5, iclass 39, count 0 2006.257.10:16:43.53#ibcon#read 5, iclass 39, count 0 2006.257.10:16:43.53#ibcon#about to read 6, iclass 39, count 0 2006.257.10:16:43.53#ibcon#read 6, iclass 39, count 0 2006.257.10:16:43.53#ibcon#end of sib2, iclass 39, count 0 2006.257.10:16:43.53#ibcon#*after write, iclass 39, count 0 2006.257.10:16:43.53#ibcon#*before return 0, iclass 39, count 0 2006.257.10:16:43.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:43.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:16:43.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:16:43.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:16:43.53$vck44/vblo=6,719.99 2006.257.10:16:43.54#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.10:16:43.54#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.10:16:43.54#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:43.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:43.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:43.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:43.54#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:16:43.54#ibcon#first serial, iclass 3, count 0 2006.257.10:16:43.54#ibcon#enter sib2, iclass 3, count 0 2006.257.10:16:43.54#ibcon#flushed, iclass 3, count 0 2006.257.10:16:43.54#ibcon#about to write, iclass 3, count 0 2006.257.10:16:43.54#ibcon#wrote, iclass 3, count 0 2006.257.10:16:43.54#ibcon#about to read 3, iclass 3, count 0 2006.257.10:16:43.55#ibcon#read 3, iclass 3, count 0 2006.257.10:16:43.55#ibcon#about to read 4, iclass 3, count 0 2006.257.10:16:43.55#ibcon#read 4, iclass 3, count 0 2006.257.10:16:43.55#ibcon#about to read 5, iclass 3, count 0 2006.257.10:16:43.55#ibcon#read 5, iclass 3, count 0 2006.257.10:16:43.55#ibcon#about to read 6, iclass 3, count 0 2006.257.10:16:43.55#ibcon#read 6, iclass 3, count 0 2006.257.10:16:43.55#ibcon#end of sib2, iclass 3, count 0 2006.257.10:16:43.55#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:16:43.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:16:43.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:16:43.55#ibcon#*before write, iclass 3, count 0 2006.257.10:16:43.55#ibcon#enter sib2, iclass 3, count 0 2006.257.10:16:43.55#ibcon#flushed, iclass 3, count 0 2006.257.10:16:43.55#ibcon#about to write, iclass 3, count 0 2006.257.10:16:43.55#ibcon#wrote, iclass 3, count 0 2006.257.10:16:43.55#ibcon#about to read 3, iclass 3, count 0 2006.257.10:16:43.59#ibcon#read 3, iclass 3, count 0 2006.257.10:16:43.59#ibcon#about to read 4, iclass 3, count 0 2006.257.10:16:43.59#ibcon#read 4, iclass 3, count 0 2006.257.10:16:43.59#ibcon#about to read 5, iclass 3, count 0 2006.257.10:16:43.59#ibcon#read 5, iclass 3, count 0 2006.257.10:16:43.59#ibcon#about to read 6, iclass 3, count 0 2006.257.10:16:43.59#ibcon#read 6, iclass 3, count 0 2006.257.10:16:43.59#ibcon#end of sib2, iclass 3, count 0 2006.257.10:16:43.59#ibcon#*after write, iclass 3, count 0 2006.257.10:16:43.59#ibcon#*before return 0, iclass 3, count 0 2006.257.10:16:43.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:43.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:16:43.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:16:43.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:16:43.59$vck44/vb=6,4 2006.257.10:16:43.60#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.10:16:43.60#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.10:16:43.60#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:43.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:43.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:43.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:43.64#ibcon#enter wrdev, iclass 5, count 2 2006.257.10:16:43.64#ibcon#first serial, iclass 5, count 2 2006.257.10:16:43.64#ibcon#enter sib2, iclass 5, count 2 2006.257.10:16:43.64#ibcon#flushed, iclass 5, count 2 2006.257.10:16:43.64#ibcon#about to write, iclass 5, count 2 2006.257.10:16:43.64#ibcon#wrote, iclass 5, count 2 2006.257.10:16:43.64#ibcon#about to read 3, iclass 5, count 2 2006.257.10:16:43.66#ibcon#read 3, iclass 5, count 2 2006.257.10:16:43.66#ibcon#about to read 4, iclass 5, count 2 2006.257.10:16:43.66#ibcon#read 4, iclass 5, count 2 2006.257.10:16:43.66#ibcon#about to read 5, iclass 5, count 2 2006.257.10:16:43.66#ibcon#read 5, iclass 5, count 2 2006.257.10:16:43.66#ibcon#about to read 6, iclass 5, count 2 2006.257.10:16:43.66#ibcon#read 6, iclass 5, count 2 2006.257.10:16:43.66#ibcon#end of sib2, iclass 5, count 2 2006.257.10:16:43.66#ibcon#*mode == 0, iclass 5, count 2 2006.257.10:16:43.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.10:16:43.66#ibcon#[27=AT06-04\r\n] 2006.257.10:16:43.66#ibcon#*before write, iclass 5, count 2 2006.257.10:16:43.66#ibcon#enter sib2, iclass 5, count 2 2006.257.10:16:43.66#ibcon#flushed, iclass 5, count 2 2006.257.10:16:43.66#ibcon#about to write, iclass 5, count 2 2006.257.10:16:43.66#ibcon#wrote, iclass 5, count 2 2006.257.10:16:43.66#ibcon#about to read 3, iclass 5, count 2 2006.257.10:16:43.69#ibcon#read 3, iclass 5, count 2 2006.257.10:16:43.69#ibcon#about to read 4, iclass 5, count 2 2006.257.10:16:43.69#ibcon#read 4, iclass 5, count 2 2006.257.10:16:43.69#ibcon#about to read 5, iclass 5, count 2 2006.257.10:16:43.69#ibcon#read 5, iclass 5, count 2 2006.257.10:16:43.69#ibcon#about to read 6, iclass 5, count 2 2006.257.10:16:43.69#ibcon#read 6, iclass 5, count 2 2006.257.10:16:43.69#ibcon#end of sib2, iclass 5, count 2 2006.257.10:16:43.69#ibcon#*after write, iclass 5, count 2 2006.257.10:16:43.69#ibcon#*before return 0, iclass 5, count 2 2006.257.10:16:43.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:43.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:16:43.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.10:16:43.69#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:43.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:43.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:43.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:43.81#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:16:43.81#ibcon#first serial, iclass 5, count 0 2006.257.10:16:43.81#ibcon#enter sib2, iclass 5, count 0 2006.257.10:16:43.81#ibcon#flushed, iclass 5, count 0 2006.257.10:16:43.81#ibcon#about to write, iclass 5, count 0 2006.257.10:16:43.81#ibcon#wrote, iclass 5, count 0 2006.257.10:16:43.81#ibcon#about to read 3, iclass 5, count 0 2006.257.10:16:43.83#ibcon#read 3, iclass 5, count 0 2006.257.10:16:43.83#ibcon#about to read 4, iclass 5, count 0 2006.257.10:16:43.83#ibcon#read 4, iclass 5, count 0 2006.257.10:16:43.83#ibcon#about to read 5, iclass 5, count 0 2006.257.10:16:43.83#ibcon#read 5, iclass 5, count 0 2006.257.10:16:43.83#ibcon#about to read 6, iclass 5, count 0 2006.257.10:16:43.83#ibcon#read 6, iclass 5, count 0 2006.257.10:16:43.83#ibcon#end of sib2, iclass 5, count 0 2006.257.10:16:43.83#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:16:43.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:16:43.83#ibcon#[27=USB\r\n] 2006.257.10:16:43.83#ibcon#*before write, iclass 5, count 0 2006.257.10:16:43.83#ibcon#enter sib2, iclass 5, count 0 2006.257.10:16:43.83#ibcon#flushed, iclass 5, count 0 2006.257.10:16:43.83#ibcon#about to write, iclass 5, count 0 2006.257.10:16:43.83#ibcon#wrote, iclass 5, count 0 2006.257.10:16:43.83#ibcon#about to read 3, iclass 5, count 0 2006.257.10:16:43.86#ibcon#read 3, iclass 5, count 0 2006.257.10:16:43.86#ibcon#about to read 4, iclass 5, count 0 2006.257.10:16:43.86#ibcon#read 4, iclass 5, count 0 2006.257.10:16:43.86#ibcon#about to read 5, iclass 5, count 0 2006.257.10:16:43.86#ibcon#read 5, iclass 5, count 0 2006.257.10:16:43.86#ibcon#about to read 6, iclass 5, count 0 2006.257.10:16:43.86#ibcon#read 6, iclass 5, count 0 2006.257.10:16:43.86#ibcon#end of sib2, iclass 5, count 0 2006.257.10:16:43.86#ibcon#*after write, iclass 5, count 0 2006.257.10:16:43.86#ibcon#*before return 0, iclass 5, count 0 2006.257.10:16:43.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:43.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:16:43.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:16:43.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:16:43.86$vck44/vblo=7,734.99 2006.257.10:16:43.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.10:16:43.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.10:16:43.87#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:43.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:43.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:43.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:43.87#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:16:43.87#ibcon#first serial, iclass 7, count 0 2006.257.10:16:43.87#ibcon#enter sib2, iclass 7, count 0 2006.257.10:16:43.87#ibcon#flushed, iclass 7, count 0 2006.257.10:16:43.87#ibcon#about to write, iclass 7, count 0 2006.257.10:16:43.87#ibcon#wrote, iclass 7, count 0 2006.257.10:16:43.87#ibcon#about to read 3, iclass 7, count 0 2006.257.10:16:43.88#ibcon#read 3, iclass 7, count 0 2006.257.10:16:43.88#ibcon#about to read 4, iclass 7, count 0 2006.257.10:16:43.88#ibcon#read 4, iclass 7, count 0 2006.257.10:16:43.88#ibcon#about to read 5, iclass 7, count 0 2006.257.10:16:43.88#ibcon#read 5, iclass 7, count 0 2006.257.10:16:43.88#ibcon#about to read 6, iclass 7, count 0 2006.257.10:16:43.88#ibcon#read 6, iclass 7, count 0 2006.257.10:16:43.88#ibcon#end of sib2, iclass 7, count 0 2006.257.10:16:43.88#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:16:43.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:16:43.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:16:43.88#ibcon#*before write, iclass 7, count 0 2006.257.10:16:43.88#ibcon#enter sib2, iclass 7, count 0 2006.257.10:16:43.88#ibcon#flushed, iclass 7, count 0 2006.257.10:16:43.88#ibcon#about to write, iclass 7, count 0 2006.257.10:16:43.88#ibcon#wrote, iclass 7, count 0 2006.257.10:16:43.88#ibcon#about to read 3, iclass 7, count 0 2006.257.10:16:43.92#ibcon#read 3, iclass 7, count 0 2006.257.10:16:43.92#ibcon#about to read 4, iclass 7, count 0 2006.257.10:16:43.92#ibcon#read 4, iclass 7, count 0 2006.257.10:16:43.92#ibcon#about to read 5, iclass 7, count 0 2006.257.10:16:43.92#ibcon#read 5, iclass 7, count 0 2006.257.10:16:43.92#ibcon#about to read 6, iclass 7, count 0 2006.257.10:16:43.92#ibcon#read 6, iclass 7, count 0 2006.257.10:16:43.92#ibcon#end of sib2, iclass 7, count 0 2006.257.10:16:43.92#ibcon#*after write, iclass 7, count 0 2006.257.10:16:43.92#ibcon#*before return 0, iclass 7, count 0 2006.257.10:16:43.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:43.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:16:43.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:16:43.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:16:43.92$vck44/vb=7,4 2006.257.10:16:43.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.10:16:43.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.10:16:43.93#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:43.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:43.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:43.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:43.97#ibcon#enter wrdev, iclass 11, count 2 2006.257.10:16:43.97#ibcon#first serial, iclass 11, count 2 2006.257.10:16:43.97#ibcon#enter sib2, iclass 11, count 2 2006.257.10:16:43.97#ibcon#flushed, iclass 11, count 2 2006.257.10:16:43.97#ibcon#about to write, iclass 11, count 2 2006.257.10:16:43.97#ibcon#wrote, iclass 11, count 2 2006.257.10:16:43.97#ibcon#about to read 3, iclass 11, count 2 2006.257.10:16:43.99#ibcon#read 3, iclass 11, count 2 2006.257.10:16:43.99#ibcon#about to read 4, iclass 11, count 2 2006.257.10:16:43.99#ibcon#read 4, iclass 11, count 2 2006.257.10:16:43.99#ibcon#about to read 5, iclass 11, count 2 2006.257.10:16:43.99#ibcon#read 5, iclass 11, count 2 2006.257.10:16:43.99#ibcon#about to read 6, iclass 11, count 2 2006.257.10:16:43.99#ibcon#read 6, iclass 11, count 2 2006.257.10:16:43.99#ibcon#end of sib2, iclass 11, count 2 2006.257.10:16:43.99#ibcon#*mode == 0, iclass 11, count 2 2006.257.10:16:43.99#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.10:16:43.99#ibcon#[27=AT07-04\r\n] 2006.257.10:16:43.99#ibcon#*before write, iclass 11, count 2 2006.257.10:16:43.99#ibcon#enter sib2, iclass 11, count 2 2006.257.10:16:43.99#ibcon#flushed, iclass 11, count 2 2006.257.10:16:43.99#ibcon#about to write, iclass 11, count 2 2006.257.10:16:43.99#ibcon#wrote, iclass 11, count 2 2006.257.10:16:43.99#ibcon#about to read 3, iclass 11, count 2 2006.257.10:16:44.02#ibcon#read 3, iclass 11, count 2 2006.257.10:16:44.02#ibcon#about to read 4, iclass 11, count 2 2006.257.10:16:44.02#ibcon#read 4, iclass 11, count 2 2006.257.10:16:44.02#ibcon#about to read 5, iclass 11, count 2 2006.257.10:16:44.02#ibcon#read 5, iclass 11, count 2 2006.257.10:16:44.02#ibcon#about to read 6, iclass 11, count 2 2006.257.10:16:44.02#ibcon#read 6, iclass 11, count 2 2006.257.10:16:44.02#ibcon#end of sib2, iclass 11, count 2 2006.257.10:16:44.02#ibcon#*after write, iclass 11, count 2 2006.257.10:16:44.02#ibcon#*before return 0, iclass 11, count 2 2006.257.10:16:44.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:44.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:16:44.02#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.10:16:44.02#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:44.02#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:44.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:44.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:44.15#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:16:44.15#ibcon#first serial, iclass 11, count 0 2006.257.10:16:44.15#ibcon#enter sib2, iclass 11, count 0 2006.257.10:16:44.15#ibcon#flushed, iclass 11, count 0 2006.257.10:16:44.15#ibcon#about to write, iclass 11, count 0 2006.257.10:16:44.15#ibcon#wrote, iclass 11, count 0 2006.257.10:16:44.15#ibcon#about to read 3, iclass 11, count 0 2006.257.10:16:44.16#ibcon#read 3, iclass 11, count 0 2006.257.10:16:44.16#ibcon#about to read 4, iclass 11, count 0 2006.257.10:16:44.16#ibcon#read 4, iclass 11, count 0 2006.257.10:16:44.16#ibcon#about to read 5, iclass 11, count 0 2006.257.10:16:44.16#ibcon#read 5, iclass 11, count 0 2006.257.10:16:44.16#ibcon#about to read 6, iclass 11, count 0 2006.257.10:16:44.16#ibcon#read 6, iclass 11, count 0 2006.257.10:16:44.16#ibcon#end of sib2, iclass 11, count 0 2006.257.10:16:44.16#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:16:44.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:16:44.16#ibcon#[27=USB\r\n] 2006.257.10:16:44.16#ibcon#*before write, iclass 11, count 0 2006.257.10:16:44.16#ibcon#enter sib2, iclass 11, count 0 2006.257.10:16:44.16#ibcon#flushed, iclass 11, count 0 2006.257.10:16:44.16#ibcon#about to write, iclass 11, count 0 2006.257.10:16:44.16#ibcon#wrote, iclass 11, count 0 2006.257.10:16:44.16#ibcon#about to read 3, iclass 11, count 0 2006.257.10:16:44.19#ibcon#read 3, iclass 11, count 0 2006.257.10:16:44.19#ibcon#about to read 4, iclass 11, count 0 2006.257.10:16:44.19#ibcon#read 4, iclass 11, count 0 2006.257.10:16:44.19#ibcon#about to read 5, iclass 11, count 0 2006.257.10:16:44.19#ibcon#read 5, iclass 11, count 0 2006.257.10:16:44.19#ibcon#about to read 6, iclass 11, count 0 2006.257.10:16:44.19#ibcon#read 6, iclass 11, count 0 2006.257.10:16:44.19#ibcon#end of sib2, iclass 11, count 0 2006.257.10:16:44.19#ibcon#*after write, iclass 11, count 0 2006.257.10:16:44.19#ibcon#*before return 0, iclass 11, count 0 2006.257.10:16:44.19#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:44.19#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:16:44.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:16:44.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:16:44.19$vck44/vblo=8,744.99 2006.257.10:16:44.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.10:16:44.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.10:16:44.20#ibcon#ireg 17 cls_cnt 0 2006.257.10:16:44.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:44.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:44.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:44.20#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:16:44.20#ibcon#first serial, iclass 13, count 0 2006.257.10:16:44.20#ibcon#enter sib2, iclass 13, count 0 2006.257.10:16:44.20#ibcon#flushed, iclass 13, count 0 2006.257.10:16:44.20#ibcon#about to write, iclass 13, count 0 2006.257.10:16:44.20#ibcon#wrote, iclass 13, count 0 2006.257.10:16:44.20#ibcon#about to read 3, iclass 13, count 0 2006.257.10:16:44.21#ibcon#read 3, iclass 13, count 0 2006.257.10:16:44.21#ibcon#about to read 4, iclass 13, count 0 2006.257.10:16:44.21#ibcon#read 4, iclass 13, count 0 2006.257.10:16:44.21#ibcon#about to read 5, iclass 13, count 0 2006.257.10:16:44.21#ibcon#read 5, iclass 13, count 0 2006.257.10:16:44.21#ibcon#about to read 6, iclass 13, count 0 2006.257.10:16:44.21#ibcon#read 6, iclass 13, count 0 2006.257.10:16:44.21#ibcon#end of sib2, iclass 13, count 0 2006.257.10:16:44.21#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:16:44.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:16:44.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:16:44.21#ibcon#*before write, iclass 13, count 0 2006.257.10:16:44.21#ibcon#enter sib2, iclass 13, count 0 2006.257.10:16:44.21#ibcon#flushed, iclass 13, count 0 2006.257.10:16:44.21#ibcon#about to write, iclass 13, count 0 2006.257.10:16:44.21#ibcon#wrote, iclass 13, count 0 2006.257.10:16:44.21#ibcon#about to read 3, iclass 13, count 0 2006.257.10:16:44.25#ibcon#read 3, iclass 13, count 0 2006.257.10:16:44.25#ibcon#about to read 4, iclass 13, count 0 2006.257.10:16:44.25#ibcon#read 4, iclass 13, count 0 2006.257.10:16:44.25#ibcon#about to read 5, iclass 13, count 0 2006.257.10:16:44.25#ibcon#read 5, iclass 13, count 0 2006.257.10:16:44.25#ibcon#about to read 6, iclass 13, count 0 2006.257.10:16:44.25#ibcon#read 6, iclass 13, count 0 2006.257.10:16:44.25#ibcon#end of sib2, iclass 13, count 0 2006.257.10:16:44.25#ibcon#*after write, iclass 13, count 0 2006.257.10:16:44.25#ibcon#*before return 0, iclass 13, count 0 2006.257.10:16:44.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:44.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:16:44.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:16:44.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:16:44.25$vck44/vb=8,4 2006.257.10:16:44.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.10:16:44.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.10:16:44.25#ibcon#ireg 11 cls_cnt 2 2006.257.10:16:44.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:44.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:44.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:44.31#ibcon#enter wrdev, iclass 15, count 2 2006.257.10:16:44.31#ibcon#first serial, iclass 15, count 2 2006.257.10:16:44.31#ibcon#enter sib2, iclass 15, count 2 2006.257.10:16:44.31#ibcon#flushed, iclass 15, count 2 2006.257.10:16:44.31#ibcon#about to write, iclass 15, count 2 2006.257.10:16:44.31#ibcon#wrote, iclass 15, count 2 2006.257.10:16:44.31#ibcon#about to read 3, iclass 15, count 2 2006.257.10:16:44.33#ibcon#read 3, iclass 15, count 2 2006.257.10:16:44.33#ibcon#about to read 4, iclass 15, count 2 2006.257.10:16:44.33#ibcon#read 4, iclass 15, count 2 2006.257.10:16:44.33#ibcon#about to read 5, iclass 15, count 2 2006.257.10:16:44.33#ibcon#read 5, iclass 15, count 2 2006.257.10:16:44.33#ibcon#about to read 6, iclass 15, count 2 2006.257.10:16:44.33#ibcon#read 6, iclass 15, count 2 2006.257.10:16:44.33#ibcon#end of sib2, iclass 15, count 2 2006.257.10:16:44.33#ibcon#*mode == 0, iclass 15, count 2 2006.257.10:16:44.33#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.10:16:44.33#ibcon#[27=AT08-04\r\n] 2006.257.10:16:44.33#ibcon#*before write, iclass 15, count 2 2006.257.10:16:44.33#ibcon#enter sib2, iclass 15, count 2 2006.257.10:16:44.33#ibcon#flushed, iclass 15, count 2 2006.257.10:16:44.33#ibcon#about to write, iclass 15, count 2 2006.257.10:16:44.33#ibcon#wrote, iclass 15, count 2 2006.257.10:16:44.33#ibcon#about to read 3, iclass 15, count 2 2006.257.10:16:44.36#ibcon#read 3, iclass 15, count 2 2006.257.10:16:44.36#ibcon#about to read 4, iclass 15, count 2 2006.257.10:16:44.36#ibcon#read 4, iclass 15, count 2 2006.257.10:16:44.36#ibcon#about to read 5, iclass 15, count 2 2006.257.10:16:44.36#ibcon#read 5, iclass 15, count 2 2006.257.10:16:44.36#ibcon#about to read 6, iclass 15, count 2 2006.257.10:16:44.36#ibcon#read 6, iclass 15, count 2 2006.257.10:16:44.36#ibcon#end of sib2, iclass 15, count 2 2006.257.10:16:44.36#ibcon#*after write, iclass 15, count 2 2006.257.10:16:44.36#ibcon#*before return 0, iclass 15, count 2 2006.257.10:16:44.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:44.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:16:44.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.10:16:44.36#ibcon#ireg 7 cls_cnt 0 2006.257.10:16:44.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:44.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:44.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:44.48#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:16:44.48#ibcon#first serial, iclass 15, count 0 2006.257.10:16:44.48#ibcon#enter sib2, iclass 15, count 0 2006.257.10:16:44.48#ibcon#flushed, iclass 15, count 0 2006.257.10:16:44.48#ibcon#about to write, iclass 15, count 0 2006.257.10:16:44.48#ibcon#wrote, iclass 15, count 0 2006.257.10:16:44.48#ibcon#about to read 3, iclass 15, count 0 2006.257.10:16:44.50#ibcon#read 3, iclass 15, count 0 2006.257.10:16:44.50#ibcon#about to read 4, iclass 15, count 0 2006.257.10:16:44.50#ibcon#read 4, iclass 15, count 0 2006.257.10:16:44.50#ibcon#about to read 5, iclass 15, count 0 2006.257.10:16:44.50#ibcon#read 5, iclass 15, count 0 2006.257.10:16:44.50#ibcon#about to read 6, iclass 15, count 0 2006.257.10:16:44.50#ibcon#read 6, iclass 15, count 0 2006.257.10:16:44.50#ibcon#end of sib2, iclass 15, count 0 2006.257.10:16:44.50#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:16:44.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:16:44.50#ibcon#[27=USB\r\n] 2006.257.10:16:44.50#ibcon#*before write, iclass 15, count 0 2006.257.10:16:44.50#ibcon#enter sib2, iclass 15, count 0 2006.257.10:16:44.50#ibcon#flushed, iclass 15, count 0 2006.257.10:16:44.50#ibcon#about to write, iclass 15, count 0 2006.257.10:16:44.50#ibcon#wrote, iclass 15, count 0 2006.257.10:16:44.50#ibcon#about to read 3, iclass 15, count 0 2006.257.10:16:44.53#ibcon#read 3, iclass 15, count 0 2006.257.10:16:44.53#ibcon#about to read 4, iclass 15, count 0 2006.257.10:16:44.53#ibcon#read 4, iclass 15, count 0 2006.257.10:16:44.53#ibcon#about to read 5, iclass 15, count 0 2006.257.10:16:44.53#ibcon#read 5, iclass 15, count 0 2006.257.10:16:44.53#ibcon#about to read 6, iclass 15, count 0 2006.257.10:16:44.53#ibcon#read 6, iclass 15, count 0 2006.257.10:16:44.53#ibcon#end of sib2, iclass 15, count 0 2006.257.10:16:44.53#ibcon#*after write, iclass 15, count 0 2006.257.10:16:44.53#ibcon#*before return 0, iclass 15, count 0 2006.257.10:16:44.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:44.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:16:44.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:16:44.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:16:44.53$vck44/vabw=wide 2006.257.10:16:44.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.10:16:44.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.10:16:44.54#ibcon#ireg 8 cls_cnt 0 2006.257.10:16:44.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:44.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:44.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:44.54#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:16:44.54#ibcon#first serial, iclass 17, count 0 2006.257.10:16:44.54#ibcon#enter sib2, iclass 17, count 0 2006.257.10:16:44.54#ibcon#flushed, iclass 17, count 0 2006.257.10:16:44.54#ibcon#about to write, iclass 17, count 0 2006.257.10:16:44.54#ibcon#wrote, iclass 17, count 0 2006.257.10:16:44.54#ibcon#about to read 3, iclass 17, count 0 2006.257.10:16:44.55#ibcon#read 3, iclass 17, count 0 2006.257.10:16:44.55#ibcon#about to read 4, iclass 17, count 0 2006.257.10:16:44.55#ibcon#read 4, iclass 17, count 0 2006.257.10:16:44.55#ibcon#about to read 5, iclass 17, count 0 2006.257.10:16:44.55#ibcon#read 5, iclass 17, count 0 2006.257.10:16:44.55#ibcon#about to read 6, iclass 17, count 0 2006.257.10:16:44.55#ibcon#read 6, iclass 17, count 0 2006.257.10:16:44.55#ibcon#end of sib2, iclass 17, count 0 2006.257.10:16:44.55#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:16:44.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:16:44.55#ibcon#[25=BW32\r\n] 2006.257.10:16:44.55#ibcon#*before write, iclass 17, count 0 2006.257.10:16:44.55#ibcon#enter sib2, iclass 17, count 0 2006.257.10:16:44.55#ibcon#flushed, iclass 17, count 0 2006.257.10:16:44.55#ibcon#about to write, iclass 17, count 0 2006.257.10:16:44.55#ibcon#wrote, iclass 17, count 0 2006.257.10:16:44.55#ibcon#about to read 3, iclass 17, count 0 2006.257.10:16:44.58#ibcon#read 3, iclass 17, count 0 2006.257.10:16:44.58#ibcon#about to read 4, iclass 17, count 0 2006.257.10:16:44.58#ibcon#read 4, iclass 17, count 0 2006.257.10:16:44.58#ibcon#about to read 5, iclass 17, count 0 2006.257.10:16:44.58#ibcon#read 5, iclass 17, count 0 2006.257.10:16:44.58#ibcon#about to read 6, iclass 17, count 0 2006.257.10:16:44.58#ibcon#read 6, iclass 17, count 0 2006.257.10:16:44.58#ibcon#end of sib2, iclass 17, count 0 2006.257.10:16:44.58#ibcon#*after write, iclass 17, count 0 2006.257.10:16:44.58#ibcon#*before return 0, iclass 17, count 0 2006.257.10:16:44.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:44.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:16:44.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:16:44.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:16:44.58$vck44/vbbw=wide 2006.257.10:16:44.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.10:16:44.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.10:16:44.59#ibcon#ireg 8 cls_cnt 0 2006.257.10:16:44.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:16:44.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:16:44.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:16:44.64#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:16:44.64#ibcon#first serial, iclass 19, count 0 2006.257.10:16:44.64#ibcon#enter sib2, iclass 19, count 0 2006.257.10:16:44.64#ibcon#flushed, iclass 19, count 0 2006.257.10:16:44.64#ibcon#about to write, iclass 19, count 0 2006.257.10:16:44.64#ibcon#wrote, iclass 19, count 0 2006.257.10:16:44.64#ibcon#about to read 3, iclass 19, count 0 2006.257.10:16:44.66#ibcon#read 3, iclass 19, count 0 2006.257.10:16:44.66#ibcon#about to read 4, iclass 19, count 0 2006.257.10:16:44.66#ibcon#read 4, iclass 19, count 0 2006.257.10:16:44.66#ibcon#about to read 5, iclass 19, count 0 2006.257.10:16:44.66#ibcon#read 5, iclass 19, count 0 2006.257.10:16:44.66#ibcon#about to read 6, iclass 19, count 0 2006.257.10:16:44.66#ibcon#read 6, iclass 19, count 0 2006.257.10:16:44.66#ibcon#end of sib2, iclass 19, count 0 2006.257.10:16:44.66#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:16:44.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:16:44.66#ibcon#[27=BW32\r\n] 2006.257.10:16:44.66#ibcon#*before write, iclass 19, count 0 2006.257.10:16:44.66#ibcon#enter sib2, iclass 19, count 0 2006.257.10:16:44.66#ibcon#flushed, iclass 19, count 0 2006.257.10:16:44.66#ibcon#about to write, iclass 19, count 0 2006.257.10:16:44.66#ibcon#wrote, iclass 19, count 0 2006.257.10:16:44.66#ibcon#about to read 3, iclass 19, count 0 2006.257.10:16:44.69#ibcon#read 3, iclass 19, count 0 2006.257.10:16:44.69#ibcon#about to read 4, iclass 19, count 0 2006.257.10:16:44.69#ibcon#read 4, iclass 19, count 0 2006.257.10:16:44.69#ibcon#about to read 5, iclass 19, count 0 2006.257.10:16:44.69#ibcon#read 5, iclass 19, count 0 2006.257.10:16:44.69#ibcon#about to read 6, iclass 19, count 0 2006.257.10:16:44.69#ibcon#read 6, iclass 19, count 0 2006.257.10:16:44.69#ibcon#end of sib2, iclass 19, count 0 2006.257.10:16:44.69#ibcon#*after write, iclass 19, count 0 2006.257.10:16:44.69#ibcon#*before return 0, iclass 19, count 0 2006.257.10:16:44.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:16:44.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:16:44.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:16:44.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:16:44.70$setupk4/ifdk4 2006.257.10:16:44.70$ifdk4/lo= 2006.257.10:16:44.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:16:44.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:16:44.70$ifdk4/patch= 2006.257.10:16:44.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:16:44.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:16:44.70$setupk4/!*+20s 2006.257.10:16:53.13#abcon#<5=/14 1.0 2.7 19.05 961013.6\r\n> 2006.257.10:16:53.15#abcon#{5=INTERFACE CLEAR} 2006.257.10:16:53.21#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:16:58.14#trakl#Source acquired 2006.257.10:16:58.14#flagr#flagr/antenna,acquired 2006.257.10:16:59.32$setupk4/"tpicd 2006.257.10:16:59.32$setupk4/echo=off 2006.257.10:16:59.32$setupk4/xlog=off 2006.257.10:16:59.32:!2006.257.10:19:15 2006.257.10:19:15.00:preob 2006.257.10:19:15.14/onsource/TRACKING 2006.257.10:19:15.14:!2006.257.10:19:25 2006.257.10:19:25.00:"tape 2006.257.10:19:25.00:"st=record 2006.257.10:19:25.00:data_valid=on 2006.257.10:19:25.00:midob 2006.257.10:19:25.14/onsource/TRACKING 2006.257.10:19:25.15/wx/19.03,1013.6,96 2006.257.10:19:25.19/cable/+6.4769E-03 2006.257.10:19:26.28/va/01,08,usb,yes,33,35 2006.257.10:19:26.28/va/02,07,usb,yes,36,36 2006.257.10:19:26.28/va/03,08,usb,yes,32,34 2006.257.10:19:26.28/va/04,07,usb,yes,37,39 2006.257.10:19:26.28/va/05,04,usb,yes,33,33 2006.257.10:19:26.28/va/06,04,usb,yes,37,36 2006.257.10:19:26.28/va/07,04,usb,yes,38,38 2006.257.10:19:26.28/va/08,04,usb,yes,31,39 2006.257.10:19:26.51/valo/01,524.99,yes,locked 2006.257.10:19:26.51/valo/02,534.99,yes,locked 2006.257.10:19:26.51/valo/03,564.99,yes,locked 2006.257.10:19:26.51/valo/04,624.99,yes,locked 2006.257.10:19:26.51/valo/05,734.99,yes,locked 2006.257.10:19:26.51/valo/06,814.99,yes,locked 2006.257.10:19:26.51/valo/07,864.99,yes,locked 2006.257.10:19:26.51/valo/08,884.99,yes,locked 2006.257.10:19:27.60/vb/01,04,usb,yes,31,29 2006.257.10:19:27.60/vb/02,05,usb,yes,30,29 2006.257.10:19:27.60/vb/03,04,usb,yes,31,34 2006.257.10:19:27.60/vb/04,05,usb,yes,31,30 2006.257.10:19:27.60/vb/05,04,usb,yes,27,30 2006.257.10:19:27.60/vb/06,04,usb,yes,32,28 2006.257.10:19:27.60/vb/07,04,usb,yes,32,32 2006.257.10:19:27.60/vb/08,04,usb,yes,29,33 2006.257.10:19:27.83/vblo/01,629.99,yes,locked 2006.257.10:19:27.83/vblo/02,634.99,yes,locked 2006.257.10:19:27.83/vblo/03,649.99,yes,locked 2006.257.10:19:27.83/vblo/04,679.99,yes,locked 2006.257.10:19:27.83/vblo/05,709.99,yes,locked 2006.257.10:19:27.83/vblo/06,719.99,yes,locked 2006.257.10:19:27.83/vblo/07,734.99,yes,locked 2006.257.10:19:27.83/vblo/08,744.99,yes,locked 2006.257.10:19:27.98/vabw/8 2006.257.10:19:28.13/vbbw/8 2006.257.10:19:28.22/xfe/off,on,15.2 2006.257.10:19:28.59/ifatt/23,28,28,28 2006.257.10:19:29.07/fmout-gps/S +4.58E-07 2006.257.10:19:29.11:!2006.257.10:20:05 2006.257.10:20:05.01:data_valid=off 2006.257.10:20:05.01:"et 2006.257.10:20:05.01:!+3s 2006.257.10:20:08.03:"tape 2006.257.10:20:08.03:postob 2006.257.10:20:08.27/cable/+6.4766E-03 2006.257.10:20:08.27/wx/19.02,1013.6,96 2006.257.10:20:08.33/fmout-gps/S +4.58E-07 2006.257.10:20:08.33:scan_name=257-1025,jd0609,140 2006.257.10:20:08.33:source=1958-179,200057.09,-174857.7,2000.0,ccw 2006.257.10:20:10.14#flagr#flagr/antenna,new-source 2006.257.10:20:10.14:checkk5 2006.257.10:20:10.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:20:10.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:20:11.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:20:11.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:20:12.14/chk_obsdata//k5ts1/T2571019??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.10:20:12.53/chk_obsdata//k5ts2/T2571019??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.10:20:12.92/chk_obsdata//k5ts3/T2571019??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.10:20:13.31/chk_obsdata//k5ts4/T2571019??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.10:20:14.04/k5log//k5ts1_log_newline 2006.257.10:20:14.75/k5log//k5ts2_log_newline 2006.257.10:20:15.46/k5log//k5ts3_log_newline 2006.257.10:20:16.16/k5log//k5ts4_log_newline 2006.257.10:20:16.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:20:16.19:setupk4=1 2006.257.10:20:16.19$setupk4/echo=on 2006.257.10:20:16.19$setupk4/pcalon 2006.257.10:20:16.19$pcalon/"no phase cal control is implemented here 2006.257.10:20:16.19$setupk4/"tpicd=stop 2006.257.10:20:16.19$setupk4/"rec=synch_on 2006.257.10:20:16.19$setupk4/"rec_mode=128 2006.257.10:20:16.19$setupk4/!* 2006.257.10:20:16.19$setupk4/recpk4 2006.257.10:20:16.19$recpk4/recpatch= 2006.257.10:20:16.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:20:16.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:20:16.19$setupk4/vck44 2006.257.10:20:16.19$vck44/valo=1,524.99 2006.257.10:20:16.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.10:20:16.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.10:20:16.19#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:16.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:16.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:16.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:16.19#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:20:16.19#ibcon#first serial, iclass 32, count 0 2006.257.10:20:16.19#ibcon#enter sib2, iclass 32, count 0 2006.257.10:20:16.19#ibcon#flushed, iclass 32, count 0 2006.257.10:20:16.19#ibcon#about to write, iclass 32, count 0 2006.257.10:20:16.19#ibcon#wrote, iclass 32, count 0 2006.257.10:20:16.19#ibcon#about to read 3, iclass 32, count 0 2006.257.10:20:16.20#ibcon#read 3, iclass 32, count 0 2006.257.10:20:16.20#ibcon#about to read 4, iclass 32, count 0 2006.257.10:20:16.20#ibcon#read 4, iclass 32, count 0 2006.257.10:20:16.20#ibcon#about to read 5, iclass 32, count 0 2006.257.10:20:16.20#ibcon#read 5, iclass 32, count 0 2006.257.10:20:16.20#ibcon#about to read 6, iclass 32, count 0 2006.257.10:20:16.20#ibcon#read 6, iclass 32, count 0 2006.257.10:20:16.20#ibcon#end of sib2, iclass 32, count 0 2006.257.10:20:16.20#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:20:16.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:20:16.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:20:16.20#ibcon#*before write, iclass 32, count 0 2006.257.10:20:16.20#ibcon#enter sib2, iclass 32, count 0 2006.257.10:20:16.20#ibcon#flushed, iclass 32, count 0 2006.257.10:20:16.20#ibcon#about to write, iclass 32, count 0 2006.257.10:20:16.20#ibcon#wrote, iclass 32, count 0 2006.257.10:20:16.20#ibcon#about to read 3, iclass 32, count 0 2006.257.10:20:16.25#ibcon#read 3, iclass 32, count 0 2006.257.10:20:16.25#ibcon#about to read 4, iclass 32, count 0 2006.257.10:20:16.25#ibcon#read 4, iclass 32, count 0 2006.257.10:20:16.25#ibcon#about to read 5, iclass 32, count 0 2006.257.10:20:16.25#ibcon#read 5, iclass 32, count 0 2006.257.10:20:16.25#ibcon#about to read 6, iclass 32, count 0 2006.257.10:20:16.25#ibcon#read 6, iclass 32, count 0 2006.257.10:20:16.25#ibcon#end of sib2, iclass 32, count 0 2006.257.10:20:16.25#ibcon#*after write, iclass 32, count 0 2006.257.10:20:16.25#ibcon#*before return 0, iclass 32, count 0 2006.257.10:20:16.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:16.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:16.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:20:16.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:20:16.25$vck44/va=1,8 2006.257.10:20:16.25#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.10:20:16.25#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.10:20:16.25#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:16.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:16.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:16.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:16.25#ibcon#enter wrdev, iclass 34, count 2 2006.257.10:20:16.25#ibcon#first serial, iclass 34, count 2 2006.257.10:20:16.25#ibcon#enter sib2, iclass 34, count 2 2006.257.10:20:16.25#ibcon#flushed, iclass 34, count 2 2006.257.10:20:16.25#ibcon#about to write, iclass 34, count 2 2006.257.10:20:16.25#ibcon#wrote, iclass 34, count 2 2006.257.10:20:16.25#ibcon#about to read 3, iclass 34, count 2 2006.257.10:20:16.27#ibcon#read 3, iclass 34, count 2 2006.257.10:20:16.27#ibcon#about to read 4, iclass 34, count 2 2006.257.10:20:16.27#ibcon#read 4, iclass 34, count 2 2006.257.10:20:16.27#ibcon#about to read 5, iclass 34, count 2 2006.257.10:20:16.27#ibcon#read 5, iclass 34, count 2 2006.257.10:20:16.27#ibcon#about to read 6, iclass 34, count 2 2006.257.10:20:16.27#ibcon#read 6, iclass 34, count 2 2006.257.10:20:16.27#ibcon#end of sib2, iclass 34, count 2 2006.257.10:20:16.27#ibcon#*mode == 0, iclass 34, count 2 2006.257.10:20:16.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.10:20:16.27#ibcon#[25=AT01-08\r\n] 2006.257.10:20:16.27#ibcon#*before write, iclass 34, count 2 2006.257.10:20:16.27#ibcon#enter sib2, iclass 34, count 2 2006.257.10:20:16.27#ibcon#flushed, iclass 34, count 2 2006.257.10:20:16.27#ibcon#about to write, iclass 34, count 2 2006.257.10:20:16.27#ibcon#wrote, iclass 34, count 2 2006.257.10:20:16.27#ibcon#about to read 3, iclass 34, count 2 2006.257.10:20:16.30#ibcon#read 3, iclass 34, count 2 2006.257.10:20:16.30#ibcon#about to read 4, iclass 34, count 2 2006.257.10:20:16.30#ibcon#read 4, iclass 34, count 2 2006.257.10:20:16.30#ibcon#about to read 5, iclass 34, count 2 2006.257.10:20:16.30#ibcon#read 5, iclass 34, count 2 2006.257.10:20:16.30#ibcon#about to read 6, iclass 34, count 2 2006.257.10:20:16.30#ibcon#read 6, iclass 34, count 2 2006.257.10:20:16.30#ibcon#end of sib2, iclass 34, count 2 2006.257.10:20:16.30#ibcon#*after write, iclass 34, count 2 2006.257.10:20:16.30#ibcon#*before return 0, iclass 34, count 2 2006.257.10:20:16.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:16.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:16.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.10:20:16.30#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:16.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:16.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:16.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:16.42#ibcon#enter wrdev, iclass 34, count 0 2006.257.10:20:16.42#ibcon#first serial, iclass 34, count 0 2006.257.10:20:16.42#ibcon#enter sib2, iclass 34, count 0 2006.257.10:20:16.42#ibcon#flushed, iclass 34, count 0 2006.257.10:20:16.42#ibcon#about to write, iclass 34, count 0 2006.257.10:20:16.42#ibcon#wrote, iclass 34, count 0 2006.257.10:20:16.42#ibcon#about to read 3, iclass 34, count 0 2006.257.10:20:16.44#ibcon#read 3, iclass 34, count 0 2006.257.10:20:16.44#ibcon#about to read 4, iclass 34, count 0 2006.257.10:20:16.44#ibcon#read 4, iclass 34, count 0 2006.257.10:20:16.44#ibcon#about to read 5, iclass 34, count 0 2006.257.10:20:16.44#ibcon#read 5, iclass 34, count 0 2006.257.10:20:16.44#ibcon#about to read 6, iclass 34, count 0 2006.257.10:20:16.44#ibcon#read 6, iclass 34, count 0 2006.257.10:20:16.44#ibcon#end of sib2, iclass 34, count 0 2006.257.10:20:16.44#ibcon#*mode == 0, iclass 34, count 0 2006.257.10:20:16.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.10:20:16.44#ibcon#[25=USB\r\n] 2006.257.10:20:16.44#ibcon#*before write, iclass 34, count 0 2006.257.10:20:16.44#ibcon#enter sib2, iclass 34, count 0 2006.257.10:20:16.44#ibcon#flushed, iclass 34, count 0 2006.257.10:20:16.44#ibcon#about to write, iclass 34, count 0 2006.257.10:20:16.44#ibcon#wrote, iclass 34, count 0 2006.257.10:20:16.44#ibcon#about to read 3, iclass 34, count 0 2006.257.10:20:16.47#ibcon#read 3, iclass 34, count 0 2006.257.10:20:16.47#ibcon#about to read 4, iclass 34, count 0 2006.257.10:20:16.47#ibcon#read 4, iclass 34, count 0 2006.257.10:20:16.47#ibcon#about to read 5, iclass 34, count 0 2006.257.10:20:16.47#ibcon#read 5, iclass 34, count 0 2006.257.10:20:16.47#ibcon#about to read 6, iclass 34, count 0 2006.257.10:20:16.47#ibcon#read 6, iclass 34, count 0 2006.257.10:20:16.47#ibcon#end of sib2, iclass 34, count 0 2006.257.10:20:16.47#ibcon#*after write, iclass 34, count 0 2006.257.10:20:16.47#ibcon#*before return 0, iclass 34, count 0 2006.257.10:20:16.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:16.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:16.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.10:20:16.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.10:20:16.47$vck44/valo=2,534.99 2006.257.10:20:16.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.10:20:16.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.10:20:16.47#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:16.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:16.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:16.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:16.47#ibcon#enter wrdev, iclass 36, count 0 2006.257.10:20:16.47#ibcon#first serial, iclass 36, count 0 2006.257.10:20:16.47#ibcon#enter sib2, iclass 36, count 0 2006.257.10:20:16.47#ibcon#flushed, iclass 36, count 0 2006.257.10:20:16.47#ibcon#about to write, iclass 36, count 0 2006.257.10:20:16.47#ibcon#wrote, iclass 36, count 0 2006.257.10:20:16.47#ibcon#about to read 3, iclass 36, count 0 2006.257.10:20:16.49#ibcon#read 3, iclass 36, count 0 2006.257.10:20:16.49#ibcon#about to read 4, iclass 36, count 0 2006.257.10:20:16.49#ibcon#read 4, iclass 36, count 0 2006.257.10:20:16.49#ibcon#about to read 5, iclass 36, count 0 2006.257.10:20:16.49#ibcon#read 5, iclass 36, count 0 2006.257.10:20:16.49#ibcon#about to read 6, iclass 36, count 0 2006.257.10:20:16.49#ibcon#read 6, iclass 36, count 0 2006.257.10:20:16.49#ibcon#end of sib2, iclass 36, count 0 2006.257.10:20:16.49#ibcon#*mode == 0, iclass 36, count 0 2006.257.10:20:16.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.10:20:16.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:20:16.49#ibcon#*before write, iclass 36, count 0 2006.257.10:20:16.49#ibcon#enter sib2, iclass 36, count 0 2006.257.10:20:16.49#ibcon#flushed, iclass 36, count 0 2006.257.10:20:16.49#ibcon#about to write, iclass 36, count 0 2006.257.10:20:16.49#ibcon#wrote, iclass 36, count 0 2006.257.10:20:16.49#ibcon#about to read 3, iclass 36, count 0 2006.257.10:20:16.53#abcon#<5=/14 1.1 3.4 19.02 961013.6\r\n> 2006.257.10:20:16.53#ibcon#read 3, iclass 36, count 0 2006.257.10:20:16.53#ibcon#about to read 4, iclass 36, count 0 2006.257.10:20:16.53#ibcon#read 4, iclass 36, count 0 2006.257.10:20:16.53#ibcon#about to read 5, iclass 36, count 0 2006.257.10:20:16.53#ibcon#read 5, iclass 36, count 0 2006.257.10:20:16.53#ibcon#about to read 6, iclass 36, count 0 2006.257.10:20:16.53#ibcon#read 6, iclass 36, count 0 2006.257.10:20:16.53#ibcon#end of sib2, iclass 36, count 0 2006.257.10:20:16.53#ibcon#*after write, iclass 36, count 0 2006.257.10:20:16.53#ibcon#*before return 0, iclass 36, count 0 2006.257.10:20:16.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:16.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:16.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.10:20:16.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.10:20:16.53$vck44/va=2,7 2006.257.10:20:16.53#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.10:20:16.53#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.10:20:16.53#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:16.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:20:16.55#abcon#{5=INTERFACE CLEAR} 2006.257.10:20:16.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:20:16.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:20:16.59#ibcon#enter wrdev, iclass 3, count 2 2006.257.10:20:16.59#ibcon#first serial, iclass 3, count 2 2006.257.10:20:16.59#ibcon#enter sib2, iclass 3, count 2 2006.257.10:20:16.59#ibcon#flushed, iclass 3, count 2 2006.257.10:20:16.59#ibcon#about to write, iclass 3, count 2 2006.257.10:20:16.59#ibcon#wrote, iclass 3, count 2 2006.257.10:20:16.59#ibcon#about to read 3, iclass 3, count 2 2006.257.10:20:16.61#ibcon#read 3, iclass 3, count 2 2006.257.10:20:16.61#ibcon#about to read 4, iclass 3, count 2 2006.257.10:20:16.61#ibcon#read 4, iclass 3, count 2 2006.257.10:20:16.61#ibcon#about to read 5, iclass 3, count 2 2006.257.10:20:16.61#ibcon#read 5, iclass 3, count 2 2006.257.10:20:16.61#ibcon#about to read 6, iclass 3, count 2 2006.257.10:20:16.61#ibcon#read 6, iclass 3, count 2 2006.257.10:20:16.61#ibcon#end of sib2, iclass 3, count 2 2006.257.10:20:16.61#ibcon#*mode == 0, iclass 3, count 2 2006.257.10:20:16.61#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.10:20:16.61#ibcon#[25=AT02-07\r\n] 2006.257.10:20:16.61#ibcon#*before write, iclass 3, count 2 2006.257.10:20:16.61#ibcon#enter sib2, iclass 3, count 2 2006.257.10:20:16.61#ibcon#flushed, iclass 3, count 2 2006.257.10:20:16.61#ibcon#about to write, iclass 3, count 2 2006.257.10:20:16.61#ibcon#wrote, iclass 3, count 2 2006.257.10:20:16.61#ibcon#about to read 3, iclass 3, count 2 2006.257.10:20:16.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:20:16.64#ibcon#read 3, iclass 3, count 2 2006.257.10:20:16.64#ibcon#about to read 4, iclass 3, count 2 2006.257.10:20:16.64#ibcon#read 4, iclass 3, count 2 2006.257.10:20:16.64#ibcon#about to read 5, iclass 3, count 2 2006.257.10:20:16.64#ibcon#read 5, iclass 3, count 2 2006.257.10:20:16.64#ibcon#about to read 6, iclass 3, count 2 2006.257.10:20:16.64#ibcon#read 6, iclass 3, count 2 2006.257.10:20:16.64#ibcon#end of sib2, iclass 3, count 2 2006.257.10:20:16.64#ibcon#*after write, iclass 3, count 2 2006.257.10:20:16.64#ibcon#*before return 0, iclass 3, count 2 2006.257.10:20:16.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:20:16.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:20:16.64#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.10:20:16.64#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:16.64#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:20:16.76#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:20:16.76#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:20:16.76#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:20:16.76#ibcon#first serial, iclass 3, count 0 2006.257.10:20:16.76#ibcon#enter sib2, iclass 3, count 0 2006.257.10:20:16.76#ibcon#flushed, iclass 3, count 0 2006.257.10:20:16.76#ibcon#about to write, iclass 3, count 0 2006.257.10:20:16.76#ibcon#wrote, iclass 3, count 0 2006.257.10:20:16.76#ibcon#about to read 3, iclass 3, count 0 2006.257.10:20:16.78#ibcon#read 3, iclass 3, count 0 2006.257.10:20:16.78#ibcon#about to read 4, iclass 3, count 0 2006.257.10:20:16.78#ibcon#read 4, iclass 3, count 0 2006.257.10:20:16.78#ibcon#about to read 5, iclass 3, count 0 2006.257.10:20:16.78#ibcon#read 5, iclass 3, count 0 2006.257.10:20:16.78#ibcon#about to read 6, iclass 3, count 0 2006.257.10:20:16.78#ibcon#read 6, iclass 3, count 0 2006.257.10:20:16.78#ibcon#end of sib2, iclass 3, count 0 2006.257.10:20:16.78#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:20:16.78#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:20:16.78#ibcon#[25=USB\r\n] 2006.257.10:20:16.78#ibcon#*before write, iclass 3, count 0 2006.257.10:20:16.78#ibcon#enter sib2, iclass 3, count 0 2006.257.10:20:16.78#ibcon#flushed, iclass 3, count 0 2006.257.10:20:16.78#ibcon#about to write, iclass 3, count 0 2006.257.10:20:16.78#ibcon#wrote, iclass 3, count 0 2006.257.10:20:16.78#ibcon#about to read 3, iclass 3, count 0 2006.257.10:20:16.81#ibcon#read 3, iclass 3, count 0 2006.257.10:20:16.81#ibcon#about to read 4, iclass 3, count 0 2006.257.10:20:16.81#ibcon#read 4, iclass 3, count 0 2006.257.10:20:16.81#ibcon#about to read 5, iclass 3, count 0 2006.257.10:20:16.81#ibcon#read 5, iclass 3, count 0 2006.257.10:20:16.81#ibcon#about to read 6, iclass 3, count 0 2006.257.10:20:16.81#ibcon#read 6, iclass 3, count 0 2006.257.10:20:16.81#ibcon#end of sib2, iclass 3, count 0 2006.257.10:20:16.81#ibcon#*after write, iclass 3, count 0 2006.257.10:20:16.81#ibcon#*before return 0, iclass 3, count 0 2006.257.10:20:16.81#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:20:16.81#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:20:16.81#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:20:16.81#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:20:16.81$vck44/valo=3,564.99 2006.257.10:20:16.81#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.10:20:16.81#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.10:20:16.81#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:16.81#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:16.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:16.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:16.81#ibcon#enter wrdev, iclass 6, count 0 2006.257.10:20:16.81#ibcon#first serial, iclass 6, count 0 2006.257.10:20:16.81#ibcon#enter sib2, iclass 6, count 0 2006.257.10:20:16.81#ibcon#flushed, iclass 6, count 0 2006.257.10:20:16.81#ibcon#about to write, iclass 6, count 0 2006.257.10:20:16.81#ibcon#wrote, iclass 6, count 0 2006.257.10:20:16.81#ibcon#about to read 3, iclass 6, count 0 2006.257.10:20:16.83#ibcon#read 3, iclass 6, count 0 2006.257.10:20:16.83#ibcon#about to read 4, iclass 6, count 0 2006.257.10:20:16.83#ibcon#read 4, iclass 6, count 0 2006.257.10:20:16.83#ibcon#about to read 5, iclass 6, count 0 2006.257.10:20:16.83#ibcon#read 5, iclass 6, count 0 2006.257.10:20:16.83#ibcon#about to read 6, iclass 6, count 0 2006.257.10:20:16.83#ibcon#read 6, iclass 6, count 0 2006.257.10:20:16.83#ibcon#end of sib2, iclass 6, count 0 2006.257.10:20:16.83#ibcon#*mode == 0, iclass 6, count 0 2006.257.10:20:16.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.10:20:16.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:20:16.83#ibcon#*before write, iclass 6, count 0 2006.257.10:20:16.83#ibcon#enter sib2, iclass 6, count 0 2006.257.10:20:16.83#ibcon#flushed, iclass 6, count 0 2006.257.10:20:16.83#ibcon#about to write, iclass 6, count 0 2006.257.10:20:16.83#ibcon#wrote, iclass 6, count 0 2006.257.10:20:16.83#ibcon#about to read 3, iclass 6, count 0 2006.257.10:20:16.87#ibcon#read 3, iclass 6, count 0 2006.257.10:20:16.87#ibcon#about to read 4, iclass 6, count 0 2006.257.10:20:16.87#ibcon#read 4, iclass 6, count 0 2006.257.10:20:16.87#ibcon#about to read 5, iclass 6, count 0 2006.257.10:20:16.87#ibcon#read 5, iclass 6, count 0 2006.257.10:20:16.87#ibcon#about to read 6, iclass 6, count 0 2006.257.10:20:16.87#ibcon#read 6, iclass 6, count 0 2006.257.10:20:16.87#ibcon#end of sib2, iclass 6, count 0 2006.257.10:20:16.87#ibcon#*after write, iclass 6, count 0 2006.257.10:20:16.87#ibcon#*before return 0, iclass 6, count 0 2006.257.10:20:16.87#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:16.87#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:16.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.10:20:16.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.10:20:16.87$vck44/va=3,8 2006.257.10:20:16.87#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.10:20:16.87#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.10:20:16.87#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:16.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:16.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:16.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:16.93#ibcon#enter wrdev, iclass 10, count 2 2006.257.10:20:16.93#ibcon#first serial, iclass 10, count 2 2006.257.10:20:16.93#ibcon#enter sib2, iclass 10, count 2 2006.257.10:20:16.93#ibcon#flushed, iclass 10, count 2 2006.257.10:20:16.93#ibcon#about to write, iclass 10, count 2 2006.257.10:20:16.93#ibcon#wrote, iclass 10, count 2 2006.257.10:20:16.93#ibcon#about to read 3, iclass 10, count 2 2006.257.10:20:16.95#ibcon#read 3, iclass 10, count 2 2006.257.10:20:16.95#ibcon#about to read 4, iclass 10, count 2 2006.257.10:20:16.95#ibcon#read 4, iclass 10, count 2 2006.257.10:20:16.95#ibcon#about to read 5, iclass 10, count 2 2006.257.10:20:16.95#ibcon#read 5, iclass 10, count 2 2006.257.10:20:16.95#ibcon#about to read 6, iclass 10, count 2 2006.257.10:20:16.95#ibcon#read 6, iclass 10, count 2 2006.257.10:20:16.95#ibcon#end of sib2, iclass 10, count 2 2006.257.10:20:16.95#ibcon#*mode == 0, iclass 10, count 2 2006.257.10:20:16.95#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.10:20:16.95#ibcon#[25=AT03-08\r\n] 2006.257.10:20:16.95#ibcon#*before write, iclass 10, count 2 2006.257.10:20:16.95#ibcon#enter sib2, iclass 10, count 2 2006.257.10:20:16.95#ibcon#flushed, iclass 10, count 2 2006.257.10:20:16.95#ibcon#about to write, iclass 10, count 2 2006.257.10:20:16.95#ibcon#wrote, iclass 10, count 2 2006.257.10:20:16.95#ibcon#about to read 3, iclass 10, count 2 2006.257.10:20:16.98#ibcon#read 3, iclass 10, count 2 2006.257.10:20:16.98#ibcon#about to read 4, iclass 10, count 2 2006.257.10:20:16.98#ibcon#read 4, iclass 10, count 2 2006.257.10:20:16.98#ibcon#about to read 5, iclass 10, count 2 2006.257.10:20:16.98#ibcon#read 5, iclass 10, count 2 2006.257.10:20:16.98#ibcon#about to read 6, iclass 10, count 2 2006.257.10:20:16.98#ibcon#read 6, iclass 10, count 2 2006.257.10:20:16.98#ibcon#end of sib2, iclass 10, count 2 2006.257.10:20:16.98#ibcon#*after write, iclass 10, count 2 2006.257.10:20:16.98#ibcon#*before return 0, iclass 10, count 2 2006.257.10:20:16.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:16.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:16.98#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.10:20:16.98#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:16.98#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:17.10#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:17.10#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:17.10#ibcon#enter wrdev, iclass 10, count 0 2006.257.10:20:17.10#ibcon#first serial, iclass 10, count 0 2006.257.10:20:17.10#ibcon#enter sib2, iclass 10, count 0 2006.257.10:20:17.10#ibcon#flushed, iclass 10, count 0 2006.257.10:20:17.10#ibcon#about to write, iclass 10, count 0 2006.257.10:20:17.10#ibcon#wrote, iclass 10, count 0 2006.257.10:20:17.10#ibcon#about to read 3, iclass 10, count 0 2006.257.10:20:17.12#ibcon#read 3, iclass 10, count 0 2006.257.10:20:17.12#ibcon#about to read 4, iclass 10, count 0 2006.257.10:20:17.12#ibcon#read 4, iclass 10, count 0 2006.257.10:20:17.12#ibcon#about to read 5, iclass 10, count 0 2006.257.10:20:17.12#ibcon#read 5, iclass 10, count 0 2006.257.10:20:17.12#ibcon#about to read 6, iclass 10, count 0 2006.257.10:20:17.12#ibcon#read 6, iclass 10, count 0 2006.257.10:20:17.12#ibcon#end of sib2, iclass 10, count 0 2006.257.10:20:17.12#ibcon#*mode == 0, iclass 10, count 0 2006.257.10:20:17.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.10:20:17.12#ibcon#[25=USB\r\n] 2006.257.10:20:17.12#ibcon#*before write, iclass 10, count 0 2006.257.10:20:17.12#ibcon#enter sib2, iclass 10, count 0 2006.257.10:20:17.12#ibcon#flushed, iclass 10, count 0 2006.257.10:20:17.12#ibcon#about to write, iclass 10, count 0 2006.257.10:20:17.12#ibcon#wrote, iclass 10, count 0 2006.257.10:20:17.12#ibcon#about to read 3, iclass 10, count 0 2006.257.10:20:17.15#ibcon#read 3, iclass 10, count 0 2006.257.10:20:17.15#ibcon#about to read 4, iclass 10, count 0 2006.257.10:20:17.15#ibcon#read 4, iclass 10, count 0 2006.257.10:20:17.15#ibcon#about to read 5, iclass 10, count 0 2006.257.10:20:17.15#ibcon#read 5, iclass 10, count 0 2006.257.10:20:17.15#ibcon#about to read 6, iclass 10, count 0 2006.257.10:20:17.15#ibcon#read 6, iclass 10, count 0 2006.257.10:20:17.15#ibcon#end of sib2, iclass 10, count 0 2006.257.10:20:17.15#ibcon#*after write, iclass 10, count 0 2006.257.10:20:17.15#ibcon#*before return 0, iclass 10, count 0 2006.257.10:20:17.15#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:17.15#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:17.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.10:20:17.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.10:20:17.15$vck44/valo=4,624.99 2006.257.10:20:17.15#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.10:20:17.15#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.10:20:17.15#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:17.15#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:17.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:17.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:17.15#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:20:17.15#ibcon#first serial, iclass 12, count 0 2006.257.10:20:17.15#ibcon#enter sib2, iclass 12, count 0 2006.257.10:20:17.15#ibcon#flushed, iclass 12, count 0 2006.257.10:20:17.15#ibcon#about to write, iclass 12, count 0 2006.257.10:20:17.15#ibcon#wrote, iclass 12, count 0 2006.257.10:20:17.15#ibcon#about to read 3, iclass 12, count 0 2006.257.10:20:17.17#ibcon#read 3, iclass 12, count 0 2006.257.10:20:17.17#ibcon#about to read 4, iclass 12, count 0 2006.257.10:20:17.17#ibcon#read 4, iclass 12, count 0 2006.257.10:20:17.17#ibcon#about to read 5, iclass 12, count 0 2006.257.10:20:17.17#ibcon#read 5, iclass 12, count 0 2006.257.10:20:17.17#ibcon#about to read 6, iclass 12, count 0 2006.257.10:20:17.17#ibcon#read 6, iclass 12, count 0 2006.257.10:20:17.17#ibcon#end of sib2, iclass 12, count 0 2006.257.10:20:17.17#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:20:17.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:20:17.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:20:17.17#ibcon#*before write, iclass 12, count 0 2006.257.10:20:17.17#ibcon#enter sib2, iclass 12, count 0 2006.257.10:20:17.17#ibcon#flushed, iclass 12, count 0 2006.257.10:20:17.17#ibcon#about to write, iclass 12, count 0 2006.257.10:20:17.17#ibcon#wrote, iclass 12, count 0 2006.257.10:20:17.17#ibcon#about to read 3, iclass 12, count 0 2006.257.10:20:17.21#ibcon#read 3, iclass 12, count 0 2006.257.10:20:17.21#ibcon#about to read 4, iclass 12, count 0 2006.257.10:20:17.21#ibcon#read 4, iclass 12, count 0 2006.257.10:20:17.21#ibcon#about to read 5, iclass 12, count 0 2006.257.10:20:17.21#ibcon#read 5, iclass 12, count 0 2006.257.10:20:17.21#ibcon#about to read 6, iclass 12, count 0 2006.257.10:20:17.21#ibcon#read 6, iclass 12, count 0 2006.257.10:20:17.21#ibcon#end of sib2, iclass 12, count 0 2006.257.10:20:17.21#ibcon#*after write, iclass 12, count 0 2006.257.10:20:17.21#ibcon#*before return 0, iclass 12, count 0 2006.257.10:20:17.21#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:17.21#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:17.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:20:17.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:20:17.21$vck44/va=4,7 2006.257.10:20:17.21#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.10:20:17.21#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.10:20:17.21#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:17.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:17.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:17.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:17.27#ibcon#enter wrdev, iclass 14, count 2 2006.257.10:20:17.27#ibcon#first serial, iclass 14, count 2 2006.257.10:20:17.27#ibcon#enter sib2, iclass 14, count 2 2006.257.10:20:17.27#ibcon#flushed, iclass 14, count 2 2006.257.10:20:17.27#ibcon#about to write, iclass 14, count 2 2006.257.10:20:17.27#ibcon#wrote, iclass 14, count 2 2006.257.10:20:17.27#ibcon#about to read 3, iclass 14, count 2 2006.257.10:20:17.29#ibcon#read 3, iclass 14, count 2 2006.257.10:20:17.29#ibcon#about to read 4, iclass 14, count 2 2006.257.10:20:17.29#ibcon#read 4, iclass 14, count 2 2006.257.10:20:17.29#ibcon#about to read 5, iclass 14, count 2 2006.257.10:20:17.29#ibcon#read 5, iclass 14, count 2 2006.257.10:20:17.29#ibcon#about to read 6, iclass 14, count 2 2006.257.10:20:17.29#ibcon#read 6, iclass 14, count 2 2006.257.10:20:17.29#ibcon#end of sib2, iclass 14, count 2 2006.257.10:20:17.29#ibcon#*mode == 0, iclass 14, count 2 2006.257.10:20:17.29#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.10:20:17.29#ibcon#[25=AT04-07\r\n] 2006.257.10:20:17.29#ibcon#*before write, iclass 14, count 2 2006.257.10:20:17.29#ibcon#enter sib2, iclass 14, count 2 2006.257.10:20:17.29#ibcon#flushed, iclass 14, count 2 2006.257.10:20:17.29#ibcon#about to write, iclass 14, count 2 2006.257.10:20:17.29#ibcon#wrote, iclass 14, count 2 2006.257.10:20:17.29#ibcon#about to read 3, iclass 14, count 2 2006.257.10:20:17.32#ibcon#read 3, iclass 14, count 2 2006.257.10:20:17.32#ibcon#about to read 4, iclass 14, count 2 2006.257.10:20:17.32#ibcon#read 4, iclass 14, count 2 2006.257.10:20:17.32#ibcon#about to read 5, iclass 14, count 2 2006.257.10:20:17.32#ibcon#read 5, iclass 14, count 2 2006.257.10:20:17.32#ibcon#about to read 6, iclass 14, count 2 2006.257.10:20:17.32#ibcon#read 6, iclass 14, count 2 2006.257.10:20:17.32#ibcon#end of sib2, iclass 14, count 2 2006.257.10:20:17.32#ibcon#*after write, iclass 14, count 2 2006.257.10:20:17.32#ibcon#*before return 0, iclass 14, count 2 2006.257.10:20:17.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:17.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:17.32#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.10:20:17.32#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:17.32#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:17.44#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:17.44#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:17.44#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:20:17.44#ibcon#first serial, iclass 14, count 0 2006.257.10:20:17.44#ibcon#enter sib2, iclass 14, count 0 2006.257.10:20:17.44#ibcon#flushed, iclass 14, count 0 2006.257.10:20:17.44#ibcon#about to write, iclass 14, count 0 2006.257.10:20:17.44#ibcon#wrote, iclass 14, count 0 2006.257.10:20:17.44#ibcon#about to read 3, iclass 14, count 0 2006.257.10:20:17.46#ibcon#read 3, iclass 14, count 0 2006.257.10:20:17.46#ibcon#about to read 4, iclass 14, count 0 2006.257.10:20:17.46#ibcon#read 4, iclass 14, count 0 2006.257.10:20:17.46#ibcon#about to read 5, iclass 14, count 0 2006.257.10:20:17.46#ibcon#read 5, iclass 14, count 0 2006.257.10:20:17.46#ibcon#about to read 6, iclass 14, count 0 2006.257.10:20:17.46#ibcon#read 6, iclass 14, count 0 2006.257.10:20:17.46#ibcon#end of sib2, iclass 14, count 0 2006.257.10:20:17.46#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:20:17.46#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:20:17.46#ibcon#[25=USB\r\n] 2006.257.10:20:17.46#ibcon#*before write, iclass 14, count 0 2006.257.10:20:17.46#ibcon#enter sib2, iclass 14, count 0 2006.257.10:20:17.46#ibcon#flushed, iclass 14, count 0 2006.257.10:20:17.46#ibcon#about to write, iclass 14, count 0 2006.257.10:20:17.46#ibcon#wrote, iclass 14, count 0 2006.257.10:20:17.46#ibcon#about to read 3, iclass 14, count 0 2006.257.10:20:17.49#ibcon#read 3, iclass 14, count 0 2006.257.10:20:17.49#ibcon#about to read 4, iclass 14, count 0 2006.257.10:20:17.49#ibcon#read 4, iclass 14, count 0 2006.257.10:20:17.49#ibcon#about to read 5, iclass 14, count 0 2006.257.10:20:17.49#ibcon#read 5, iclass 14, count 0 2006.257.10:20:17.49#ibcon#about to read 6, iclass 14, count 0 2006.257.10:20:17.49#ibcon#read 6, iclass 14, count 0 2006.257.10:20:17.49#ibcon#end of sib2, iclass 14, count 0 2006.257.10:20:17.49#ibcon#*after write, iclass 14, count 0 2006.257.10:20:17.49#ibcon#*before return 0, iclass 14, count 0 2006.257.10:20:17.49#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:17.49#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:17.49#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:20:17.49#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:20:17.49$vck44/valo=5,734.99 2006.257.10:20:17.49#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.10:20:17.49#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.10:20:17.49#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:17.49#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:17.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:17.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:17.49#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:20:17.49#ibcon#first serial, iclass 16, count 0 2006.257.10:20:17.49#ibcon#enter sib2, iclass 16, count 0 2006.257.10:20:17.49#ibcon#flushed, iclass 16, count 0 2006.257.10:20:17.49#ibcon#about to write, iclass 16, count 0 2006.257.10:20:17.49#ibcon#wrote, iclass 16, count 0 2006.257.10:20:17.49#ibcon#about to read 3, iclass 16, count 0 2006.257.10:20:17.51#ibcon#read 3, iclass 16, count 0 2006.257.10:20:17.51#ibcon#about to read 4, iclass 16, count 0 2006.257.10:20:17.51#ibcon#read 4, iclass 16, count 0 2006.257.10:20:17.51#ibcon#about to read 5, iclass 16, count 0 2006.257.10:20:17.51#ibcon#read 5, iclass 16, count 0 2006.257.10:20:17.51#ibcon#about to read 6, iclass 16, count 0 2006.257.10:20:17.51#ibcon#read 6, iclass 16, count 0 2006.257.10:20:17.51#ibcon#end of sib2, iclass 16, count 0 2006.257.10:20:17.51#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:20:17.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:20:17.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:20:17.51#ibcon#*before write, iclass 16, count 0 2006.257.10:20:17.51#ibcon#enter sib2, iclass 16, count 0 2006.257.10:20:17.51#ibcon#flushed, iclass 16, count 0 2006.257.10:20:17.51#ibcon#about to write, iclass 16, count 0 2006.257.10:20:17.51#ibcon#wrote, iclass 16, count 0 2006.257.10:20:17.51#ibcon#about to read 3, iclass 16, count 0 2006.257.10:20:17.55#ibcon#read 3, iclass 16, count 0 2006.257.10:20:17.55#ibcon#about to read 4, iclass 16, count 0 2006.257.10:20:17.55#ibcon#read 4, iclass 16, count 0 2006.257.10:20:17.55#ibcon#about to read 5, iclass 16, count 0 2006.257.10:20:17.55#ibcon#read 5, iclass 16, count 0 2006.257.10:20:17.55#ibcon#about to read 6, iclass 16, count 0 2006.257.10:20:17.55#ibcon#read 6, iclass 16, count 0 2006.257.10:20:17.55#ibcon#end of sib2, iclass 16, count 0 2006.257.10:20:17.55#ibcon#*after write, iclass 16, count 0 2006.257.10:20:17.55#ibcon#*before return 0, iclass 16, count 0 2006.257.10:20:17.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:17.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:17.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:20:17.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:20:17.55$vck44/va=5,4 2006.257.10:20:17.55#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.10:20:17.55#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.10:20:17.55#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:17.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:17.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:17.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:17.61#ibcon#enter wrdev, iclass 18, count 2 2006.257.10:20:17.61#ibcon#first serial, iclass 18, count 2 2006.257.10:20:17.61#ibcon#enter sib2, iclass 18, count 2 2006.257.10:20:17.61#ibcon#flushed, iclass 18, count 2 2006.257.10:20:17.61#ibcon#about to write, iclass 18, count 2 2006.257.10:20:17.61#ibcon#wrote, iclass 18, count 2 2006.257.10:20:17.61#ibcon#about to read 3, iclass 18, count 2 2006.257.10:20:17.63#ibcon#read 3, iclass 18, count 2 2006.257.10:20:17.63#ibcon#about to read 4, iclass 18, count 2 2006.257.10:20:17.63#ibcon#read 4, iclass 18, count 2 2006.257.10:20:17.63#ibcon#about to read 5, iclass 18, count 2 2006.257.10:20:17.63#ibcon#read 5, iclass 18, count 2 2006.257.10:20:17.63#ibcon#about to read 6, iclass 18, count 2 2006.257.10:20:17.63#ibcon#read 6, iclass 18, count 2 2006.257.10:20:17.63#ibcon#end of sib2, iclass 18, count 2 2006.257.10:20:17.63#ibcon#*mode == 0, iclass 18, count 2 2006.257.10:20:17.63#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.10:20:17.63#ibcon#[25=AT05-04\r\n] 2006.257.10:20:17.63#ibcon#*before write, iclass 18, count 2 2006.257.10:20:17.63#ibcon#enter sib2, iclass 18, count 2 2006.257.10:20:17.63#ibcon#flushed, iclass 18, count 2 2006.257.10:20:17.63#ibcon#about to write, iclass 18, count 2 2006.257.10:20:17.63#ibcon#wrote, iclass 18, count 2 2006.257.10:20:17.63#ibcon#about to read 3, iclass 18, count 2 2006.257.10:20:17.66#ibcon#read 3, iclass 18, count 2 2006.257.10:20:17.66#ibcon#about to read 4, iclass 18, count 2 2006.257.10:20:17.66#ibcon#read 4, iclass 18, count 2 2006.257.10:20:17.66#ibcon#about to read 5, iclass 18, count 2 2006.257.10:20:17.66#ibcon#read 5, iclass 18, count 2 2006.257.10:20:17.66#ibcon#about to read 6, iclass 18, count 2 2006.257.10:20:17.66#ibcon#read 6, iclass 18, count 2 2006.257.10:20:17.66#ibcon#end of sib2, iclass 18, count 2 2006.257.10:20:17.66#ibcon#*after write, iclass 18, count 2 2006.257.10:20:17.66#ibcon#*before return 0, iclass 18, count 2 2006.257.10:20:17.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:17.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:17.66#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.10:20:17.66#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:17.66#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:17.78#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:17.78#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:17.78#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:20:17.78#ibcon#first serial, iclass 18, count 0 2006.257.10:20:17.78#ibcon#enter sib2, iclass 18, count 0 2006.257.10:20:17.78#ibcon#flushed, iclass 18, count 0 2006.257.10:20:17.78#ibcon#about to write, iclass 18, count 0 2006.257.10:20:17.78#ibcon#wrote, iclass 18, count 0 2006.257.10:20:17.78#ibcon#about to read 3, iclass 18, count 0 2006.257.10:20:17.80#ibcon#read 3, iclass 18, count 0 2006.257.10:20:17.80#ibcon#about to read 4, iclass 18, count 0 2006.257.10:20:17.80#ibcon#read 4, iclass 18, count 0 2006.257.10:20:17.80#ibcon#about to read 5, iclass 18, count 0 2006.257.10:20:17.80#ibcon#read 5, iclass 18, count 0 2006.257.10:20:17.80#ibcon#about to read 6, iclass 18, count 0 2006.257.10:20:17.80#ibcon#read 6, iclass 18, count 0 2006.257.10:20:17.80#ibcon#end of sib2, iclass 18, count 0 2006.257.10:20:17.80#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:20:17.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:20:17.80#ibcon#[25=USB\r\n] 2006.257.10:20:17.80#ibcon#*before write, iclass 18, count 0 2006.257.10:20:17.80#ibcon#enter sib2, iclass 18, count 0 2006.257.10:20:17.80#ibcon#flushed, iclass 18, count 0 2006.257.10:20:17.80#ibcon#about to write, iclass 18, count 0 2006.257.10:20:17.80#ibcon#wrote, iclass 18, count 0 2006.257.10:20:17.80#ibcon#about to read 3, iclass 18, count 0 2006.257.10:20:17.83#ibcon#read 3, iclass 18, count 0 2006.257.10:20:17.83#ibcon#about to read 4, iclass 18, count 0 2006.257.10:20:17.83#ibcon#read 4, iclass 18, count 0 2006.257.10:20:17.83#ibcon#about to read 5, iclass 18, count 0 2006.257.10:20:17.83#ibcon#read 5, iclass 18, count 0 2006.257.10:20:17.83#ibcon#about to read 6, iclass 18, count 0 2006.257.10:20:17.83#ibcon#read 6, iclass 18, count 0 2006.257.10:20:17.83#ibcon#end of sib2, iclass 18, count 0 2006.257.10:20:17.83#ibcon#*after write, iclass 18, count 0 2006.257.10:20:17.83#ibcon#*before return 0, iclass 18, count 0 2006.257.10:20:17.83#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:17.83#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:17.83#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:20:17.83#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:20:17.83$vck44/valo=6,814.99 2006.257.10:20:17.83#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.10:20:17.83#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.10:20:17.83#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:17.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:17.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:17.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:17.83#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:20:17.83#ibcon#first serial, iclass 20, count 0 2006.257.10:20:17.83#ibcon#enter sib2, iclass 20, count 0 2006.257.10:20:17.83#ibcon#flushed, iclass 20, count 0 2006.257.10:20:17.83#ibcon#about to write, iclass 20, count 0 2006.257.10:20:17.83#ibcon#wrote, iclass 20, count 0 2006.257.10:20:17.83#ibcon#about to read 3, iclass 20, count 0 2006.257.10:20:17.85#ibcon#read 3, iclass 20, count 0 2006.257.10:20:17.85#ibcon#about to read 4, iclass 20, count 0 2006.257.10:20:17.85#ibcon#read 4, iclass 20, count 0 2006.257.10:20:17.85#ibcon#about to read 5, iclass 20, count 0 2006.257.10:20:17.85#ibcon#read 5, iclass 20, count 0 2006.257.10:20:17.85#ibcon#about to read 6, iclass 20, count 0 2006.257.10:20:17.85#ibcon#read 6, iclass 20, count 0 2006.257.10:20:17.85#ibcon#end of sib2, iclass 20, count 0 2006.257.10:20:17.85#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:20:17.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:20:17.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:20:17.85#ibcon#*before write, iclass 20, count 0 2006.257.10:20:17.85#ibcon#enter sib2, iclass 20, count 0 2006.257.10:20:17.85#ibcon#flushed, iclass 20, count 0 2006.257.10:20:17.85#ibcon#about to write, iclass 20, count 0 2006.257.10:20:17.85#ibcon#wrote, iclass 20, count 0 2006.257.10:20:17.85#ibcon#about to read 3, iclass 20, count 0 2006.257.10:20:17.89#ibcon#read 3, iclass 20, count 0 2006.257.10:20:17.89#ibcon#about to read 4, iclass 20, count 0 2006.257.10:20:17.89#ibcon#read 4, iclass 20, count 0 2006.257.10:20:17.89#ibcon#about to read 5, iclass 20, count 0 2006.257.10:20:17.89#ibcon#read 5, iclass 20, count 0 2006.257.10:20:17.89#ibcon#about to read 6, iclass 20, count 0 2006.257.10:20:17.89#ibcon#read 6, iclass 20, count 0 2006.257.10:20:17.89#ibcon#end of sib2, iclass 20, count 0 2006.257.10:20:17.89#ibcon#*after write, iclass 20, count 0 2006.257.10:20:17.89#ibcon#*before return 0, iclass 20, count 0 2006.257.10:20:17.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:17.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:17.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:20:17.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:20:17.89$vck44/va=6,4 2006.257.10:20:17.89#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.10:20:17.89#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.10:20:17.89#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:17.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:17.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:17.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:17.95#ibcon#enter wrdev, iclass 22, count 2 2006.257.10:20:17.95#ibcon#first serial, iclass 22, count 2 2006.257.10:20:17.95#ibcon#enter sib2, iclass 22, count 2 2006.257.10:20:17.95#ibcon#flushed, iclass 22, count 2 2006.257.10:20:17.95#ibcon#about to write, iclass 22, count 2 2006.257.10:20:17.95#ibcon#wrote, iclass 22, count 2 2006.257.10:20:17.95#ibcon#about to read 3, iclass 22, count 2 2006.257.10:20:17.97#ibcon#read 3, iclass 22, count 2 2006.257.10:20:17.97#ibcon#about to read 4, iclass 22, count 2 2006.257.10:20:17.97#ibcon#read 4, iclass 22, count 2 2006.257.10:20:17.97#ibcon#about to read 5, iclass 22, count 2 2006.257.10:20:17.97#ibcon#read 5, iclass 22, count 2 2006.257.10:20:17.97#ibcon#about to read 6, iclass 22, count 2 2006.257.10:20:17.97#ibcon#read 6, iclass 22, count 2 2006.257.10:20:17.97#ibcon#end of sib2, iclass 22, count 2 2006.257.10:20:17.97#ibcon#*mode == 0, iclass 22, count 2 2006.257.10:20:17.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.10:20:17.97#ibcon#[25=AT06-04\r\n] 2006.257.10:20:17.97#ibcon#*before write, iclass 22, count 2 2006.257.10:20:17.97#ibcon#enter sib2, iclass 22, count 2 2006.257.10:20:17.97#ibcon#flushed, iclass 22, count 2 2006.257.10:20:17.97#ibcon#about to write, iclass 22, count 2 2006.257.10:20:17.97#ibcon#wrote, iclass 22, count 2 2006.257.10:20:17.97#ibcon#about to read 3, iclass 22, count 2 2006.257.10:20:18.00#ibcon#read 3, iclass 22, count 2 2006.257.10:20:18.00#ibcon#about to read 4, iclass 22, count 2 2006.257.10:20:18.00#ibcon#read 4, iclass 22, count 2 2006.257.10:20:18.00#ibcon#about to read 5, iclass 22, count 2 2006.257.10:20:18.00#ibcon#read 5, iclass 22, count 2 2006.257.10:20:18.00#ibcon#about to read 6, iclass 22, count 2 2006.257.10:20:18.00#ibcon#read 6, iclass 22, count 2 2006.257.10:20:18.00#ibcon#end of sib2, iclass 22, count 2 2006.257.10:20:18.00#ibcon#*after write, iclass 22, count 2 2006.257.10:20:18.00#ibcon#*before return 0, iclass 22, count 2 2006.257.10:20:18.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:18.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:18.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.10:20:18.00#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:18.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:18.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:18.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:18.12#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:20:18.12#ibcon#first serial, iclass 22, count 0 2006.257.10:20:18.12#ibcon#enter sib2, iclass 22, count 0 2006.257.10:20:18.12#ibcon#flushed, iclass 22, count 0 2006.257.10:20:18.12#ibcon#about to write, iclass 22, count 0 2006.257.10:20:18.12#ibcon#wrote, iclass 22, count 0 2006.257.10:20:18.12#ibcon#about to read 3, iclass 22, count 0 2006.257.10:20:18.14#ibcon#read 3, iclass 22, count 0 2006.257.10:20:18.14#ibcon#about to read 4, iclass 22, count 0 2006.257.10:20:18.14#ibcon#read 4, iclass 22, count 0 2006.257.10:20:18.14#ibcon#about to read 5, iclass 22, count 0 2006.257.10:20:18.14#ibcon#read 5, iclass 22, count 0 2006.257.10:20:18.14#ibcon#about to read 6, iclass 22, count 0 2006.257.10:20:18.14#ibcon#read 6, iclass 22, count 0 2006.257.10:20:18.14#ibcon#end of sib2, iclass 22, count 0 2006.257.10:20:18.14#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:20:18.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:20:18.14#ibcon#[25=USB\r\n] 2006.257.10:20:18.14#ibcon#*before write, iclass 22, count 0 2006.257.10:20:18.14#ibcon#enter sib2, iclass 22, count 0 2006.257.10:20:18.14#ibcon#flushed, iclass 22, count 0 2006.257.10:20:18.14#ibcon#about to write, iclass 22, count 0 2006.257.10:20:18.14#ibcon#wrote, iclass 22, count 0 2006.257.10:20:18.14#ibcon#about to read 3, iclass 22, count 0 2006.257.10:20:18.17#ibcon#read 3, iclass 22, count 0 2006.257.10:20:18.17#ibcon#about to read 4, iclass 22, count 0 2006.257.10:20:18.17#ibcon#read 4, iclass 22, count 0 2006.257.10:20:18.17#ibcon#about to read 5, iclass 22, count 0 2006.257.10:20:18.17#ibcon#read 5, iclass 22, count 0 2006.257.10:20:18.17#ibcon#about to read 6, iclass 22, count 0 2006.257.10:20:18.17#ibcon#read 6, iclass 22, count 0 2006.257.10:20:18.17#ibcon#end of sib2, iclass 22, count 0 2006.257.10:20:18.17#ibcon#*after write, iclass 22, count 0 2006.257.10:20:18.17#ibcon#*before return 0, iclass 22, count 0 2006.257.10:20:18.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:18.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:18.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:20:18.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:20:18.17$vck44/valo=7,864.99 2006.257.10:20:18.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.10:20:18.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.10:20:18.17#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:18.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:18.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:18.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:18.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:20:18.17#ibcon#first serial, iclass 24, count 0 2006.257.10:20:18.17#ibcon#enter sib2, iclass 24, count 0 2006.257.10:20:18.17#ibcon#flushed, iclass 24, count 0 2006.257.10:20:18.17#ibcon#about to write, iclass 24, count 0 2006.257.10:20:18.17#ibcon#wrote, iclass 24, count 0 2006.257.10:20:18.17#ibcon#about to read 3, iclass 24, count 0 2006.257.10:20:18.19#ibcon#read 3, iclass 24, count 0 2006.257.10:20:18.19#ibcon#about to read 4, iclass 24, count 0 2006.257.10:20:18.19#ibcon#read 4, iclass 24, count 0 2006.257.10:20:18.19#ibcon#about to read 5, iclass 24, count 0 2006.257.10:20:18.19#ibcon#read 5, iclass 24, count 0 2006.257.10:20:18.19#ibcon#about to read 6, iclass 24, count 0 2006.257.10:20:18.19#ibcon#read 6, iclass 24, count 0 2006.257.10:20:18.19#ibcon#end of sib2, iclass 24, count 0 2006.257.10:20:18.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:20:18.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:20:18.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:20:18.19#ibcon#*before write, iclass 24, count 0 2006.257.10:20:18.19#ibcon#enter sib2, iclass 24, count 0 2006.257.10:20:18.19#ibcon#flushed, iclass 24, count 0 2006.257.10:20:18.19#ibcon#about to write, iclass 24, count 0 2006.257.10:20:18.19#ibcon#wrote, iclass 24, count 0 2006.257.10:20:18.19#ibcon#about to read 3, iclass 24, count 0 2006.257.10:20:18.23#ibcon#read 3, iclass 24, count 0 2006.257.10:20:18.23#ibcon#about to read 4, iclass 24, count 0 2006.257.10:20:18.23#ibcon#read 4, iclass 24, count 0 2006.257.10:20:18.23#ibcon#about to read 5, iclass 24, count 0 2006.257.10:20:18.23#ibcon#read 5, iclass 24, count 0 2006.257.10:20:18.23#ibcon#about to read 6, iclass 24, count 0 2006.257.10:20:18.23#ibcon#read 6, iclass 24, count 0 2006.257.10:20:18.23#ibcon#end of sib2, iclass 24, count 0 2006.257.10:20:18.23#ibcon#*after write, iclass 24, count 0 2006.257.10:20:18.23#ibcon#*before return 0, iclass 24, count 0 2006.257.10:20:18.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:18.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:18.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:20:18.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:20:18.23$vck44/va=7,4 2006.257.10:20:18.23#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.10:20:18.23#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.10:20:18.23#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:18.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:18.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:18.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:18.29#ibcon#enter wrdev, iclass 26, count 2 2006.257.10:20:18.29#ibcon#first serial, iclass 26, count 2 2006.257.10:20:18.29#ibcon#enter sib2, iclass 26, count 2 2006.257.10:20:18.29#ibcon#flushed, iclass 26, count 2 2006.257.10:20:18.29#ibcon#about to write, iclass 26, count 2 2006.257.10:20:18.29#ibcon#wrote, iclass 26, count 2 2006.257.10:20:18.29#ibcon#about to read 3, iclass 26, count 2 2006.257.10:20:18.31#ibcon#read 3, iclass 26, count 2 2006.257.10:20:18.31#ibcon#about to read 4, iclass 26, count 2 2006.257.10:20:18.31#ibcon#read 4, iclass 26, count 2 2006.257.10:20:18.31#ibcon#about to read 5, iclass 26, count 2 2006.257.10:20:18.31#ibcon#read 5, iclass 26, count 2 2006.257.10:20:18.31#ibcon#about to read 6, iclass 26, count 2 2006.257.10:20:18.31#ibcon#read 6, iclass 26, count 2 2006.257.10:20:18.31#ibcon#end of sib2, iclass 26, count 2 2006.257.10:20:18.31#ibcon#*mode == 0, iclass 26, count 2 2006.257.10:20:18.31#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.10:20:18.31#ibcon#[25=AT07-04\r\n] 2006.257.10:20:18.31#ibcon#*before write, iclass 26, count 2 2006.257.10:20:18.31#ibcon#enter sib2, iclass 26, count 2 2006.257.10:20:18.31#ibcon#flushed, iclass 26, count 2 2006.257.10:20:18.31#ibcon#about to write, iclass 26, count 2 2006.257.10:20:18.31#ibcon#wrote, iclass 26, count 2 2006.257.10:20:18.31#ibcon#about to read 3, iclass 26, count 2 2006.257.10:20:18.34#ibcon#read 3, iclass 26, count 2 2006.257.10:20:18.34#ibcon#about to read 4, iclass 26, count 2 2006.257.10:20:18.34#ibcon#read 4, iclass 26, count 2 2006.257.10:20:18.34#ibcon#about to read 5, iclass 26, count 2 2006.257.10:20:18.34#ibcon#read 5, iclass 26, count 2 2006.257.10:20:18.34#ibcon#about to read 6, iclass 26, count 2 2006.257.10:20:18.34#ibcon#read 6, iclass 26, count 2 2006.257.10:20:18.34#ibcon#end of sib2, iclass 26, count 2 2006.257.10:20:18.34#ibcon#*after write, iclass 26, count 2 2006.257.10:20:18.34#ibcon#*before return 0, iclass 26, count 2 2006.257.10:20:18.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:18.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:18.34#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.10:20:18.34#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:18.34#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:18.46#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:18.46#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:18.46#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:20:18.46#ibcon#first serial, iclass 26, count 0 2006.257.10:20:18.46#ibcon#enter sib2, iclass 26, count 0 2006.257.10:20:18.46#ibcon#flushed, iclass 26, count 0 2006.257.10:20:18.46#ibcon#about to write, iclass 26, count 0 2006.257.10:20:18.46#ibcon#wrote, iclass 26, count 0 2006.257.10:20:18.46#ibcon#about to read 3, iclass 26, count 0 2006.257.10:20:18.48#ibcon#read 3, iclass 26, count 0 2006.257.10:20:18.48#ibcon#about to read 4, iclass 26, count 0 2006.257.10:20:18.48#ibcon#read 4, iclass 26, count 0 2006.257.10:20:18.48#ibcon#about to read 5, iclass 26, count 0 2006.257.10:20:18.48#ibcon#read 5, iclass 26, count 0 2006.257.10:20:18.48#ibcon#about to read 6, iclass 26, count 0 2006.257.10:20:18.48#ibcon#read 6, iclass 26, count 0 2006.257.10:20:18.48#ibcon#end of sib2, iclass 26, count 0 2006.257.10:20:18.48#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:20:18.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:20:18.48#ibcon#[25=USB\r\n] 2006.257.10:20:18.48#ibcon#*before write, iclass 26, count 0 2006.257.10:20:18.48#ibcon#enter sib2, iclass 26, count 0 2006.257.10:20:18.48#ibcon#flushed, iclass 26, count 0 2006.257.10:20:18.48#ibcon#about to write, iclass 26, count 0 2006.257.10:20:18.48#ibcon#wrote, iclass 26, count 0 2006.257.10:20:18.48#ibcon#about to read 3, iclass 26, count 0 2006.257.10:20:18.51#ibcon#read 3, iclass 26, count 0 2006.257.10:20:18.51#ibcon#about to read 4, iclass 26, count 0 2006.257.10:20:18.51#ibcon#read 4, iclass 26, count 0 2006.257.10:20:18.51#ibcon#about to read 5, iclass 26, count 0 2006.257.10:20:18.51#ibcon#read 5, iclass 26, count 0 2006.257.10:20:18.51#ibcon#about to read 6, iclass 26, count 0 2006.257.10:20:18.51#ibcon#read 6, iclass 26, count 0 2006.257.10:20:18.51#ibcon#end of sib2, iclass 26, count 0 2006.257.10:20:18.51#ibcon#*after write, iclass 26, count 0 2006.257.10:20:18.51#ibcon#*before return 0, iclass 26, count 0 2006.257.10:20:18.51#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:18.51#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:18.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:20:18.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:20:18.51$vck44/valo=8,884.99 2006.257.10:20:18.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.10:20:18.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.10:20:18.51#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:18.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:18.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:18.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:18.51#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:20:18.51#ibcon#first serial, iclass 28, count 0 2006.257.10:20:18.51#ibcon#enter sib2, iclass 28, count 0 2006.257.10:20:18.51#ibcon#flushed, iclass 28, count 0 2006.257.10:20:18.51#ibcon#about to write, iclass 28, count 0 2006.257.10:20:18.51#ibcon#wrote, iclass 28, count 0 2006.257.10:20:18.51#ibcon#about to read 3, iclass 28, count 0 2006.257.10:20:18.53#ibcon#read 3, iclass 28, count 0 2006.257.10:20:18.53#ibcon#about to read 4, iclass 28, count 0 2006.257.10:20:18.53#ibcon#read 4, iclass 28, count 0 2006.257.10:20:18.53#ibcon#about to read 5, iclass 28, count 0 2006.257.10:20:18.53#ibcon#read 5, iclass 28, count 0 2006.257.10:20:18.53#ibcon#about to read 6, iclass 28, count 0 2006.257.10:20:18.53#ibcon#read 6, iclass 28, count 0 2006.257.10:20:18.53#ibcon#end of sib2, iclass 28, count 0 2006.257.10:20:18.53#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:20:18.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:20:18.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:20:18.53#ibcon#*before write, iclass 28, count 0 2006.257.10:20:18.53#ibcon#enter sib2, iclass 28, count 0 2006.257.10:20:18.53#ibcon#flushed, iclass 28, count 0 2006.257.10:20:18.53#ibcon#about to write, iclass 28, count 0 2006.257.10:20:18.53#ibcon#wrote, iclass 28, count 0 2006.257.10:20:18.53#ibcon#about to read 3, iclass 28, count 0 2006.257.10:20:18.57#ibcon#read 3, iclass 28, count 0 2006.257.10:20:18.57#ibcon#about to read 4, iclass 28, count 0 2006.257.10:20:18.57#ibcon#read 4, iclass 28, count 0 2006.257.10:20:18.57#ibcon#about to read 5, iclass 28, count 0 2006.257.10:20:18.57#ibcon#read 5, iclass 28, count 0 2006.257.10:20:18.57#ibcon#about to read 6, iclass 28, count 0 2006.257.10:20:18.57#ibcon#read 6, iclass 28, count 0 2006.257.10:20:18.57#ibcon#end of sib2, iclass 28, count 0 2006.257.10:20:18.57#ibcon#*after write, iclass 28, count 0 2006.257.10:20:18.57#ibcon#*before return 0, iclass 28, count 0 2006.257.10:20:18.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:18.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:18.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:20:18.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:20:18.57$vck44/va=8,4 2006.257.10:20:18.57#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.10:20:18.57#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.10:20:18.57#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:18.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:20:18.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:20:18.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:20:18.63#ibcon#enter wrdev, iclass 30, count 2 2006.257.10:20:18.63#ibcon#first serial, iclass 30, count 2 2006.257.10:20:18.63#ibcon#enter sib2, iclass 30, count 2 2006.257.10:20:18.63#ibcon#flushed, iclass 30, count 2 2006.257.10:20:18.63#ibcon#about to write, iclass 30, count 2 2006.257.10:20:18.63#ibcon#wrote, iclass 30, count 2 2006.257.10:20:18.63#ibcon#about to read 3, iclass 30, count 2 2006.257.10:20:18.65#ibcon#read 3, iclass 30, count 2 2006.257.10:20:18.65#ibcon#about to read 4, iclass 30, count 2 2006.257.10:20:18.65#ibcon#read 4, iclass 30, count 2 2006.257.10:20:18.65#ibcon#about to read 5, iclass 30, count 2 2006.257.10:20:18.65#ibcon#read 5, iclass 30, count 2 2006.257.10:20:18.65#ibcon#about to read 6, iclass 30, count 2 2006.257.10:20:18.65#ibcon#read 6, iclass 30, count 2 2006.257.10:20:18.65#ibcon#end of sib2, iclass 30, count 2 2006.257.10:20:18.65#ibcon#*mode == 0, iclass 30, count 2 2006.257.10:20:18.65#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.10:20:18.65#ibcon#[25=AT08-04\r\n] 2006.257.10:20:18.65#ibcon#*before write, iclass 30, count 2 2006.257.10:20:18.65#ibcon#enter sib2, iclass 30, count 2 2006.257.10:20:18.65#ibcon#flushed, iclass 30, count 2 2006.257.10:20:18.65#ibcon#about to write, iclass 30, count 2 2006.257.10:20:18.65#ibcon#wrote, iclass 30, count 2 2006.257.10:20:18.65#ibcon#about to read 3, iclass 30, count 2 2006.257.10:20:18.68#ibcon#read 3, iclass 30, count 2 2006.257.10:20:18.68#ibcon#about to read 4, iclass 30, count 2 2006.257.10:20:18.68#ibcon#read 4, iclass 30, count 2 2006.257.10:20:18.68#ibcon#about to read 5, iclass 30, count 2 2006.257.10:20:18.68#ibcon#read 5, iclass 30, count 2 2006.257.10:20:18.68#ibcon#about to read 6, iclass 30, count 2 2006.257.10:20:18.68#ibcon#read 6, iclass 30, count 2 2006.257.10:20:18.68#ibcon#end of sib2, iclass 30, count 2 2006.257.10:20:18.68#ibcon#*after write, iclass 30, count 2 2006.257.10:20:18.68#ibcon#*before return 0, iclass 30, count 2 2006.257.10:20:18.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:20:18.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:20:18.68#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.10:20:18.68#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:18.68#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:20:18.80#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:20:18.80#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:20:18.80#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:20:18.80#ibcon#first serial, iclass 30, count 0 2006.257.10:20:18.80#ibcon#enter sib2, iclass 30, count 0 2006.257.10:20:18.80#ibcon#flushed, iclass 30, count 0 2006.257.10:20:18.80#ibcon#about to write, iclass 30, count 0 2006.257.10:20:18.80#ibcon#wrote, iclass 30, count 0 2006.257.10:20:18.80#ibcon#about to read 3, iclass 30, count 0 2006.257.10:20:18.82#ibcon#read 3, iclass 30, count 0 2006.257.10:20:18.82#ibcon#about to read 4, iclass 30, count 0 2006.257.10:20:18.82#ibcon#read 4, iclass 30, count 0 2006.257.10:20:18.82#ibcon#about to read 5, iclass 30, count 0 2006.257.10:20:18.82#ibcon#read 5, iclass 30, count 0 2006.257.10:20:18.82#ibcon#about to read 6, iclass 30, count 0 2006.257.10:20:18.82#ibcon#read 6, iclass 30, count 0 2006.257.10:20:18.82#ibcon#end of sib2, iclass 30, count 0 2006.257.10:20:18.82#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:20:18.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:20:18.82#ibcon#[25=USB\r\n] 2006.257.10:20:18.82#ibcon#*before write, iclass 30, count 0 2006.257.10:20:18.82#ibcon#enter sib2, iclass 30, count 0 2006.257.10:20:18.82#ibcon#flushed, iclass 30, count 0 2006.257.10:20:18.82#ibcon#about to write, iclass 30, count 0 2006.257.10:20:18.82#ibcon#wrote, iclass 30, count 0 2006.257.10:20:18.82#ibcon#about to read 3, iclass 30, count 0 2006.257.10:20:18.85#ibcon#read 3, iclass 30, count 0 2006.257.10:20:18.85#ibcon#about to read 4, iclass 30, count 0 2006.257.10:20:18.85#ibcon#read 4, iclass 30, count 0 2006.257.10:20:18.85#ibcon#about to read 5, iclass 30, count 0 2006.257.10:20:18.85#ibcon#read 5, iclass 30, count 0 2006.257.10:20:18.85#ibcon#about to read 6, iclass 30, count 0 2006.257.10:20:18.85#ibcon#read 6, iclass 30, count 0 2006.257.10:20:18.85#ibcon#end of sib2, iclass 30, count 0 2006.257.10:20:18.85#ibcon#*after write, iclass 30, count 0 2006.257.10:20:18.85#ibcon#*before return 0, iclass 30, count 0 2006.257.10:20:18.85#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:20:18.85#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:20:18.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:20:18.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:20:18.85$vck44/vblo=1,629.99 2006.257.10:20:18.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.10:20:18.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.10:20:18.85#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:18.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:18.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:18.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:18.85#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:20:18.85#ibcon#first serial, iclass 32, count 0 2006.257.10:20:18.85#ibcon#enter sib2, iclass 32, count 0 2006.257.10:20:18.85#ibcon#flushed, iclass 32, count 0 2006.257.10:20:18.85#ibcon#about to write, iclass 32, count 0 2006.257.10:20:18.85#ibcon#wrote, iclass 32, count 0 2006.257.10:20:18.85#ibcon#about to read 3, iclass 32, count 0 2006.257.10:20:18.87#ibcon#read 3, iclass 32, count 0 2006.257.10:20:18.87#ibcon#about to read 4, iclass 32, count 0 2006.257.10:20:18.87#ibcon#read 4, iclass 32, count 0 2006.257.10:20:18.87#ibcon#about to read 5, iclass 32, count 0 2006.257.10:20:18.87#ibcon#read 5, iclass 32, count 0 2006.257.10:20:18.87#ibcon#about to read 6, iclass 32, count 0 2006.257.10:20:18.87#ibcon#read 6, iclass 32, count 0 2006.257.10:20:18.87#ibcon#end of sib2, iclass 32, count 0 2006.257.10:20:18.87#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:20:18.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:20:18.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:20:18.87#ibcon#*before write, iclass 32, count 0 2006.257.10:20:18.87#ibcon#enter sib2, iclass 32, count 0 2006.257.10:20:18.87#ibcon#flushed, iclass 32, count 0 2006.257.10:20:18.87#ibcon#about to write, iclass 32, count 0 2006.257.10:20:18.87#ibcon#wrote, iclass 32, count 0 2006.257.10:20:18.87#ibcon#about to read 3, iclass 32, count 0 2006.257.10:20:18.91#ibcon#read 3, iclass 32, count 0 2006.257.10:20:18.91#ibcon#about to read 4, iclass 32, count 0 2006.257.10:20:18.91#ibcon#read 4, iclass 32, count 0 2006.257.10:20:18.91#ibcon#about to read 5, iclass 32, count 0 2006.257.10:20:18.91#ibcon#read 5, iclass 32, count 0 2006.257.10:20:18.91#ibcon#about to read 6, iclass 32, count 0 2006.257.10:20:18.91#ibcon#read 6, iclass 32, count 0 2006.257.10:20:18.91#ibcon#end of sib2, iclass 32, count 0 2006.257.10:20:18.91#ibcon#*after write, iclass 32, count 0 2006.257.10:20:18.91#ibcon#*before return 0, iclass 32, count 0 2006.257.10:20:18.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:18.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:20:18.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:20:18.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:20:18.91$vck44/vb=1,4 2006.257.10:20:18.91#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.10:20:18.91#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.10:20:18.91#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:18.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:18.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:18.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:18.91#ibcon#enter wrdev, iclass 34, count 2 2006.257.10:20:18.91#ibcon#first serial, iclass 34, count 2 2006.257.10:20:18.91#ibcon#enter sib2, iclass 34, count 2 2006.257.10:20:18.91#ibcon#flushed, iclass 34, count 2 2006.257.10:20:18.91#ibcon#about to write, iclass 34, count 2 2006.257.10:20:18.91#ibcon#wrote, iclass 34, count 2 2006.257.10:20:18.91#ibcon#about to read 3, iclass 34, count 2 2006.257.10:20:18.93#ibcon#read 3, iclass 34, count 2 2006.257.10:20:18.93#ibcon#about to read 4, iclass 34, count 2 2006.257.10:20:18.93#ibcon#read 4, iclass 34, count 2 2006.257.10:20:18.93#ibcon#about to read 5, iclass 34, count 2 2006.257.10:20:18.93#ibcon#read 5, iclass 34, count 2 2006.257.10:20:18.93#ibcon#about to read 6, iclass 34, count 2 2006.257.10:20:18.93#ibcon#read 6, iclass 34, count 2 2006.257.10:20:18.93#ibcon#end of sib2, iclass 34, count 2 2006.257.10:20:18.93#ibcon#*mode == 0, iclass 34, count 2 2006.257.10:20:18.93#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.10:20:18.93#ibcon#[27=AT01-04\r\n] 2006.257.10:20:18.93#ibcon#*before write, iclass 34, count 2 2006.257.10:20:18.93#ibcon#enter sib2, iclass 34, count 2 2006.257.10:20:18.93#ibcon#flushed, iclass 34, count 2 2006.257.10:20:18.93#ibcon#about to write, iclass 34, count 2 2006.257.10:20:18.93#ibcon#wrote, iclass 34, count 2 2006.257.10:20:18.93#ibcon#about to read 3, iclass 34, count 2 2006.257.10:20:18.96#ibcon#read 3, iclass 34, count 2 2006.257.10:20:18.96#ibcon#about to read 4, iclass 34, count 2 2006.257.10:20:18.96#ibcon#read 4, iclass 34, count 2 2006.257.10:20:18.96#ibcon#about to read 5, iclass 34, count 2 2006.257.10:20:18.96#ibcon#read 5, iclass 34, count 2 2006.257.10:20:18.96#ibcon#about to read 6, iclass 34, count 2 2006.257.10:20:18.96#ibcon#read 6, iclass 34, count 2 2006.257.10:20:18.96#ibcon#end of sib2, iclass 34, count 2 2006.257.10:20:18.96#ibcon#*after write, iclass 34, count 2 2006.257.10:20:18.96#ibcon#*before return 0, iclass 34, count 2 2006.257.10:20:18.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:18.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:20:18.96#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.10:20:18.96#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:18.96#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:19.08#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:19.08#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:19.08#ibcon#enter wrdev, iclass 34, count 0 2006.257.10:20:19.08#ibcon#first serial, iclass 34, count 0 2006.257.10:20:19.08#ibcon#enter sib2, iclass 34, count 0 2006.257.10:20:19.08#ibcon#flushed, iclass 34, count 0 2006.257.10:20:19.08#ibcon#about to write, iclass 34, count 0 2006.257.10:20:19.08#ibcon#wrote, iclass 34, count 0 2006.257.10:20:19.08#ibcon#about to read 3, iclass 34, count 0 2006.257.10:20:19.10#ibcon#read 3, iclass 34, count 0 2006.257.10:20:19.10#ibcon#about to read 4, iclass 34, count 0 2006.257.10:20:19.10#ibcon#read 4, iclass 34, count 0 2006.257.10:20:19.10#ibcon#about to read 5, iclass 34, count 0 2006.257.10:20:19.10#ibcon#read 5, iclass 34, count 0 2006.257.10:20:19.10#ibcon#about to read 6, iclass 34, count 0 2006.257.10:20:19.10#ibcon#read 6, iclass 34, count 0 2006.257.10:20:19.10#ibcon#end of sib2, iclass 34, count 0 2006.257.10:20:19.10#ibcon#*mode == 0, iclass 34, count 0 2006.257.10:20:19.10#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.10:20:19.10#ibcon#[27=USB\r\n] 2006.257.10:20:19.10#ibcon#*before write, iclass 34, count 0 2006.257.10:20:19.10#ibcon#enter sib2, iclass 34, count 0 2006.257.10:20:19.10#ibcon#flushed, iclass 34, count 0 2006.257.10:20:19.10#ibcon#about to write, iclass 34, count 0 2006.257.10:20:19.10#ibcon#wrote, iclass 34, count 0 2006.257.10:20:19.10#ibcon#about to read 3, iclass 34, count 0 2006.257.10:20:19.13#ibcon#read 3, iclass 34, count 0 2006.257.10:20:19.13#ibcon#about to read 4, iclass 34, count 0 2006.257.10:20:19.13#ibcon#read 4, iclass 34, count 0 2006.257.10:20:19.13#ibcon#about to read 5, iclass 34, count 0 2006.257.10:20:19.13#ibcon#read 5, iclass 34, count 0 2006.257.10:20:19.13#ibcon#about to read 6, iclass 34, count 0 2006.257.10:20:19.13#ibcon#read 6, iclass 34, count 0 2006.257.10:20:19.13#ibcon#end of sib2, iclass 34, count 0 2006.257.10:20:19.13#ibcon#*after write, iclass 34, count 0 2006.257.10:20:19.13#ibcon#*before return 0, iclass 34, count 0 2006.257.10:20:19.13#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:19.13#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:20:19.13#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.10:20:19.13#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.10:20:19.13$vck44/vblo=2,634.99 2006.257.10:20:19.13#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.10:20:19.13#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.10:20:19.13#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:19.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:19.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:19.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:19.13#ibcon#enter wrdev, iclass 36, count 0 2006.257.10:20:19.13#ibcon#first serial, iclass 36, count 0 2006.257.10:20:19.13#ibcon#enter sib2, iclass 36, count 0 2006.257.10:20:19.13#ibcon#flushed, iclass 36, count 0 2006.257.10:20:19.13#ibcon#about to write, iclass 36, count 0 2006.257.10:20:19.13#ibcon#wrote, iclass 36, count 0 2006.257.10:20:19.13#ibcon#about to read 3, iclass 36, count 0 2006.257.10:20:19.15#ibcon#read 3, iclass 36, count 0 2006.257.10:20:19.15#ibcon#about to read 4, iclass 36, count 0 2006.257.10:20:19.15#ibcon#read 4, iclass 36, count 0 2006.257.10:20:19.15#ibcon#about to read 5, iclass 36, count 0 2006.257.10:20:19.15#ibcon#read 5, iclass 36, count 0 2006.257.10:20:19.15#ibcon#about to read 6, iclass 36, count 0 2006.257.10:20:19.15#ibcon#read 6, iclass 36, count 0 2006.257.10:20:19.15#ibcon#end of sib2, iclass 36, count 0 2006.257.10:20:19.15#ibcon#*mode == 0, iclass 36, count 0 2006.257.10:20:19.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.10:20:19.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:20:19.15#ibcon#*before write, iclass 36, count 0 2006.257.10:20:19.15#ibcon#enter sib2, iclass 36, count 0 2006.257.10:20:19.15#ibcon#flushed, iclass 36, count 0 2006.257.10:20:19.15#ibcon#about to write, iclass 36, count 0 2006.257.10:20:19.15#ibcon#wrote, iclass 36, count 0 2006.257.10:20:19.15#ibcon#about to read 3, iclass 36, count 0 2006.257.10:20:19.19#ibcon#read 3, iclass 36, count 0 2006.257.10:20:19.19#ibcon#about to read 4, iclass 36, count 0 2006.257.10:20:19.19#ibcon#read 4, iclass 36, count 0 2006.257.10:20:19.19#ibcon#about to read 5, iclass 36, count 0 2006.257.10:20:19.19#ibcon#read 5, iclass 36, count 0 2006.257.10:20:19.19#ibcon#about to read 6, iclass 36, count 0 2006.257.10:20:19.19#ibcon#read 6, iclass 36, count 0 2006.257.10:20:19.19#ibcon#end of sib2, iclass 36, count 0 2006.257.10:20:19.19#ibcon#*after write, iclass 36, count 0 2006.257.10:20:19.19#ibcon#*before return 0, iclass 36, count 0 2006.257.10:20:19.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:19.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:20:19.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.10:20:19.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.10:20:19.19$vck44/vb=2,5 2006.257.10:20:19.19#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.10:20:19.19#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.10:20:19.19#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:19.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:20:19.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:20:19.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:20:19.25#ibcon#enter wrdev, iclass 38, count 2 2006.257.10:20:19.25#ibcon#first serial, iclass 38, count 2 2006.257.10:20:19.25#ibcon#enter sib2, iclass 38, count 2 2006.257.10:20:19.25#ibcon#flushed, iclass 38, count 2 2006.257.10:20:19.25#ibcon#about to write, iclass 38, count 2 2006.257.10:20:19.25#ibcon#wrote, iclass 38, count 2 2006.257.10:20:19.25#ibcon#about to read 3, iclass 38, count 2 2006.257.10:20:19.27#ibcon#read 3, iclass 38, count 2 2006.257.10:20:19.27#ibcon#about to read 4, iclass 38, count 2 2006.257.10:20:19.27#ibcon#read 4, iclass 38, count 2 2006.257.10:20:19.27#ibcon#about to read 5, iclass 38, count 2 2006.257.10:20:19.27#ibcon#read 5, iclass 38, count 2 2006.257.10:20:19.27#ibcon#about to read 6, iclass 38, count 2 2006.257.10:20:19.27#ibcon#read 6, iclass 38, count 2 2006.257.10:20:19.27#ibcon#end of sib2, iclass 38, count 2 2006.257.10:20:19.27#ibcon#*mode == 0, iclass 38, count 2 2006.257.10:20:19.27#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.10:20:19.27#ibcon#[27=AT02-05\r\n] 2006.257.10:20:19.27#ibcon#*before write, iclass 38, count 2 2006.257.10:20:19.27#ibcon#enter sib2, iclass 38, count 2 2006.257.10:20:19.27#ibcon#flushed, iclass 38, count 2 2006.257.10:20:19.27#ibcon#about to write, iclass 38, count 2 2006.257.10:20:19.27#ibcon#wrote, iclass 38, count 2 2006.257.10:20:19.27#ibcon#about to read 3, iclass 38, count 2 2006.257.10:20:19.30#ibcon#read 3, iclass 38, count 2 2006.257.10:20:19.34#ibcon#about to read 4, iclass 38, count 2 2006.257.10:20:19.35#ibcon#read 4, iclass 38, count 2 2006.257.10:20:19.35#ibcon#about to read 5, iclass 38, count 2 2006.257.10:20:19.35#ibcon#read 5, iclass 38, count 2 2006.257.10:20:19.35#ibcon#about to read 6, iclass 38, count 2 2006.257.10:20:19.35#ibcon#read 6, iclass 38, count 2 2006.257.10:20:19.35#ibcon#end of sib2, iclass 38, count 2 2006.257.10:20:19.35#ibcon#*after write, iclass 38, count 2 2006.257.10:20:19.35#ibcon#*before return 0, iclass 38, count 2 2006.257.10:20:19.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:20:19.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:20:19.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.10:20:19.35#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:19.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:20:19.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:20:19.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:20:19.46#ibcon#enter wrdev, iclass 38, count 0 2006.257.10:20:19.46#ibcon#first serial, iclass 38, count 0 2006.257.10:20:19.46#ibcon#enter sib2, iclass 38, count 0 2006.257.10:20:19.46#ibcon#flushed, iclass 38, count 0 2006.257.10:20:19.46#ibcon#about to write, iclass 38, count 0 2006.257.10:20:19.46#ibcon#wrote, iclass 38, count 0 2006.257.10:20:19.46#ibcon#about to read 3, iclass 38, count 0 2006.257.10:20:19.48#ibcon#read 3, iclass 38, count 0 2006.257.10:20:19.48#ibcon#about to read 4, iclass 38, count 0 2006.257.10:20:19.48#ibcon#read 4, iclass 38, count 0 2006.257.10:20:19.48#ibcon#about to read 5, iclass 38, count 0 2006.257.10:20:19.48#ibcon#read 5, iclass 38, count 0 2006.257.10:20:19.48#ibcon#about to read 6, iclass 38, count 0 2006.257.10:20:19.48#ibcon#read 6, iclass 38, count 0 2006.257.10:20:19.48#ibcon#end of sib2, iclass 38, count 0 2006.257.10:20:19.48#ibcon#*mode == 0, iclass 38, count 0 2006.257.10:20:19.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.10:20:19.48#ibcon#[27=USB\r\n] 2006.257.10:20:19.48#ibcon#*before write, iclass 38, count 0 2006.257.10:20:19.48#ibcon#enter sib2, iclass 38, count 0 2006.257.10:20:19.48#ibcon#flushed, iclass 38, count 0 2006.257.10:20:19.48#ibcon#about to write, iclass 38, count 0 2006.257.10:20:19.48#ibcon#wrote, iclass 38, count 0 2006.257.10:20:19.48#ibcon#about to read 3, iclass 38, count 0 2006.257.10:20:19.51#ibcon#read 3, iclass 38, count 0 2006.257.10:20:19.51#ibcon#about to read 4, iclass 38, count 0 2006.257.10:20:19.51#ibcon#read 4, iclass 38, count 0 2006.257.10:20:19.51#ibcon#about to read 5, iclass 38, count 0 2006.257.10:20:19.51#ibcon#read 5, iclass 38, count 0 2006.257.10:20:19.51#ibcon#about to read 6, iclass 38, count 0 2006.257.10:20:19.51#ibcon#read 6, iclass 38, count 0 2006.257.10:20:19.51#ibcon#end of sib2, iclass 38, count 0 2006.257.10:20:19.51#ibcon#*after write, iclass 38, count 0 2006.257.10:20:19.51#ibcon#*before return 0, iclass 38, count 0 2006.257.10:20:19.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:20:19.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:20:19.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.10:20:19.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.10:20:19.51$vck44/vblo=3,649.99 2006.257.10:20:19.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.10:20:19.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.10:20:19.51#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:19.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:20:19.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:20:19.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:20:19.51#ibcon#enter wrdev, iclass 40, count 0 2006.257.10:20:19.51#ibcon#first serial, iclass 40, count 0 2006.257.10:20:19.51#ibcon#enter sib2, iclass 40, count 0 2006.257.10:20:19.51#ibcon#flushed, iclass 40, count 0 2006.257.10:20:19.51#ibcon#about to write, iclass 40, count 0 2006.257.10:20:19.51#ibcon#wrote, iclass 40, count 0 2006.257.10:20:19.51#ibcon#about to read 3, iclass 40, count 0 2006.257.10:20:19.53#ibcon#read 3, iclass 40, count 0 2006.257.10:20:19.53#ibcon#about to read 4, iclass 40, count 0 2006.257.10:20:19.53#ibcon#read 4, iclass 40, count 0 2006.257.10:20:19.53#ibcon#about to read 5, iclass 40, count 0 2006.257.10:20:19.53#ibcon#read 5, iclass 40, count 0 2006.257.10:20:19.53#ibcon#about to read 6, iclass 40, count 0 2006.257.10:20:19.53#ibcon#read 6, iclass 40, count 0 2006.257.10:20:19.53#ibcon#end of sib2, iclass 40, count 0 2006.257.10:20:19.53#ibcon#*mode == 0, iclass 40, count 0 2006.257.10:20:19.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.10:20:19.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:20:19.53#ibcon#*before write, iclass 40, count 0 2006.257.10:20:19.53#ibcon#enter sib2, iclass 40, count 0 2006.257.10:20:19.53#ibcon#flushed, iclass 40, count 0 2006.257.10:20:19.53#ibcon#about to write, iclass 40, count 0 2006.257.10:20:19.53#ibcon#wrote, iclass 40, count 0 2006.257.10:20:19.53#ibcon#about to read 3, iclass 40, count 0 2006.257.10:20:19.57#ibcon#read 3, iclass 40, count 0 2006.257.10:20:19.57#ibcon#about to read 4, iclass 40, count 0 2006.257.10:20:19.57#ibcon#read 4, iclass 40, count 0 2006.257.10:20:19.57#ibcon#about to read 5, iclass 40, count 0 2006.257.10:20:19.57#ibcon#read 5, iclass 40, count 0 2006.257.10:20:19.57#ibcon#about to read 6, iclass 40, count 0 2006.257.10:20:19.57#ibcon#read 6, iclass 40, count 0 2006.257.10:20:19.57#ibcon#end of sib2, iclass 40, count 0 2006.257.10:20:19.57#ibcon#*after write, iclass 40, count 0 2006.257.10:20:19.57#ibcon#*before return 0, iclass 40, count 0 2006.257.10:20:19.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:20:19.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:20:19.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.10:20:19.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.10:20:19.57$vck44/vb=3,4 2006.257.10:20:19.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.10:20:19.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.10:20:19.57#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:19.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:20:19.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:20:19.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:20:19.63#ibcon#enter wrdev, iclass 4, count 2 2006.257.10:20:19.63#ibcon#first serial, iclass 4, count 2 2006.257.10:20:19.63#ibcon#enter sib2, iclass 4, count 2 2006.257.10:20:19.63#ibcon#flushed, iclass 4, count 2 2006.257.10:20:19.63#ibcon#about to write, iclass 4, count 2 2006.257.10:20:19.63#ibcon#wrote, iclass 4, count 2 2006.257.10:20:19.63#ibcon#about to read 3, iclass 4, count 2 2006.257.10:20:19.65#ibcon#read 3, iclass 4, count 2 2006.257.10:20:19.65#ibcon#about to read 4, iclass 4, count 2 2006.257.10:20:19.65#ibcon#read 4, iclass 4, count 2 2006.257.10:20:19.65#ibcon#about to read 5, iclass 4, count 2 2006.257.10:20:19.65#ibcon#read 5, iclass 4, count 2 2006.257.10:20:19.65#ibcon#about to read 6, iclass 4, count 2 2006.257.10:20:19.65#ibcon#read 6, iclass 4, count 2 2006.257.10:20:19.65#ibcon#end of sib2, iclass 4, count 2 2006.257.10:20:19.65#ibcon#*mode == 0, iclass 4, count 2 2006.257.10:20:19.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.10:20:19.65#ibcon#[27=AT03-04\r\n] 2006.257.10:20:19.65#ibcon#*before write, iclass 4, count 2 2006.257.10:20:19.65#ibcon#enter sib2, iclass 4, count 2 2006.257.10:20:19.65#ibcon#flushed, iclass 4, count 2 2006.257.10:20:19.65#ibcon#about to write, iclass 4, count 2 2006.257.10:20:19.65#ibcon#wrote, iclass 4, count 2 2006.257.10:20:19.65#ibcon#about to read 3, iclass 4, count 2 2006.257.10:20:19.68#ibcon#read 3, iclass 4, count 2 2006.257.10:20:19.68#ibcon#about to read 4, iclass 4, count 2 2006.257.10:20:19.68#ibcon#read 4, iclass 4, count 2 2006.257.10:20:19.68#ibcon#about to read 5, iclass 4, count 2 2006.257.10:20:19.68#ibcon#read 5, iclass 4, count 2 2006.257.10:20:19.68#ibcon#about to read 6, iclass 4, count 2 2006.257.10:20:19.68#ibcon#read 6, iclass 4, count 2 2006.257.10:20:19.68#ibcon#end of sib2, iclass 4, count 2 2006.257.10:20:19.68#ibcon#*after write, iclass 4, count 2 2006.257.10:20:19.68#ibcon#*before return 0, iclass 4, count 2 2006.257.10:20:19.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:20:19.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:20:19.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.10:20:19.68#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:19.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:20:19.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:20:19.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:20:19.80#ibcon#enter wrdev, iclass 4, count 0 2006.257.10:20:19.80#ibcon#first serial, iclass 4, count 0 2006.257.10:20:19.80#ibcon#enter sib2, iclass 4, count 0 2006.257.10:20:19.80#ibcon#flushed, iclass 4, count 0 2006.257.10:20:19.80#ibcon#about to write, iclass 4, count 0 2006.257.10:20:19.80#ibcon#wrote, iclass 4, count 0 2006.257.10:20:19.80#ibcon#about to read 3, iclass 4, count 0 2006.257.10:20:19.82#ibcon#read 3, iclass 4, count 0 2006.257.10:20:19.82#ibcon#about to read 4, iclass 4, count 0 2006.257.10:20:19.82#ibcon#read 4, iclass 4, count 0 2006.257.10:20:19.82#ibcon#about to read 5, iclass 4, count 0 2006.257.10:20:19.82#ibcon#read 5, iclass 4, count 0 2006.257.10:20:19.82#ibcon#about to read 6, iclass 4, count 0 2006.257.10:20:19.82#ibcon#read 6, iclass 4, count 0 2006.257.10:20:19.82#ibcon#end of sib2, iclass 4, count 0 2006.257.10:20:19.82#ibcon#*mode == 0, iclass 4, count 0 2006.257.10:20:19.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.10:20:19.82#ibcon#[27=USB\r\n] 2006.257.10:20:19.82#ibcon#*before write, iclass 4, count 0 2006.257.10:20:19.82#ibcon#enter sib2, iclass 4, count 0 2006.257.10:20:19.82#ibcon#flushed, iclass 4, count 0 2006.257.10:20:19.82#ibcon#about to write, iclass 4, count 0 2006.257.10:20:19.82#ibcon#wrote, iclass 4, count 0 2006.257.10:20:19.82#ibcon#about to read 3, iclass 4, count 0 2006.257.10:20:19.85#ibcon#read 3, iclass 4, count 0 2006.257.10:20:19.85#ibcon#about to read 4, iclass 4, count 0 2006.257.10:20:19.85#ibcon#read 4, iclass 4, count 0 2006.257.10:20:19.85#ibcon#about to read 5, iclass 4, count 0 2006.257.10:20:19.85#ibcon#read 5, iclass 4, count 0 2006.257.10:20:19.85#ibcon#about to read 6, iclass 4, count 0 2006.257.10:20:19.85#ibcon#read 6, iclass 4, count 0 2006.257.10:20:19.85#ibcon#end of sib2, iclass 4, count 0 2006.257.10:20:19.85#ibcon#*after write, iclass 4, count 0 2006.257.10:20:19.85#ibcon#*before return 0, iclass 4, count 0 2006.257.10:20:19.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:20:19.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:20:19.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.10:20:19.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.10:20:19.85$vck44/vblo=4,679.99 2006.257.10:20:19.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.10:20:19.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.10:20:19.85#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:19.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:19.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:19.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:19.85#ibcon#enter wrdev, iclass 6, count 0 2006.257.10:20:19.85#ibcon#first serial, iclass 6, count 0 2006.257.10:20:19.85#ibcon#enter sib2, iclass 6, count 0 2006.257.10:20:19.85#ibcon#flushed, iclass 6, count 0 2006.257.10:20:19.85#ibcon#about to write, iclass 6, count 0 2006.257.10:20:19.85#ibcon#wrote, iclass 6, count 0 2006.257.10:20:19.85#ibcon#about to read 3, iclass 6, count 0 2006.257.10:20:19.87#ibcon#read 3, iclass 6, count 0 2006.257.10:20:19.87#ibcon#about to read 4, iclass 6, count 0 2006.257.10:20:19.87#ibcon#read 4, iclass 6, count 0 2006.257.10:20:19.87#ibcon#about to read 5, iclass 6, count 0 2006.257.10:20:19.87#ibcon#read 5, iclass 6, count 0 2006.257.10:20:19.87#ibcon#about to read 6, iclass 6, count 0 2006.257.10:20:19.87#ibcon#read 6, iclass 6, count 0 2006.257.10:20:19.87#ibcon#end of sib2, iclass 6, count 0 2006.257.10:20:19.87#ibcon#*mode == 0, iclass 6, count 0 2006.257.10:20:19.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.10:20:19.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:20:19.87#ibcon#*before write, iclass 6, count 0 2006.257.10:20:19.87#ibcon#enter sib2, iclass 6, count 0 2006.257.10:20:19.87#ibcon#flushed, iclass 6, count 0 2006.257.10:20:19.87#ibcon#about to write, iclass 6, count 0 2006.257.10:20:19.87#ibcon#wrote, iclass 6, count 0 2006.257.10:20:19.87#ibcon#about to read 3, iclass 6, count 0 2006.257.10:20:19.91#ibcon#read 3, iclass 6, count 0 2006.257.10:20:19.91#ibcon#about to read 4, iclass 6, count 0 2006.257.10:20:19.91#ibcon#read 4, iclass 6, count 0 2006.257.10:20:19.91#ibcon#about to read 5, iclass 6, count 0 2006.257.10:20:19.91#ibcon#read 5, iclass 6, count 0 2006.257.10:20:19.91#ibcon#about to read 6, iclass 6, count 0 2006.257.10:20:19.91#ibcon#read 6, iclass 6, count 0 2006.257.10:20:19.91#ibcon#end of sib2, iclass 6, count 0 2006.257.10:20:19.91#ibcon#*after write, iclass 6, count 0 2006.257.10:20:19.91#ibcon#*before return 0, iclass 6, count 0 2006.257.10:20:19.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:19.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:20:19.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.10:20:19.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.10:20:19.91$vck44/vb=4,5 2006.257.10:20:19.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.10:20:19.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.10:20:19.91#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:19.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:19.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:19.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:19.97#ibcon#enter wrdev, iclass 10, count 2 2006.257.10:20:19.97#ibcon#first serial, iclass 10, count 2 2006.257.10:20:19.97#ibcon#enter sib2, iclass 10, count 2 2006.257.10:20:19.97#ibcon#flushed, iclass 10, count 2 2006.257.10:20:19.97#ibcon#about to write, iclass 10, count 2 2006.257.10:20:19.97#ibcon#wrote, iclass 10, count 2 2006.257.10:20:19.97#ibcon#about to read 3, iclass 10, count 2 2006.257.10:20:19.99#ibcon#read 3, iclass 10, count 2 2006.257.10:20:19.99#ibcon#about to read 4, iclass 10, count 2 2006.257.10:20:19.99#ibcon#read 4, iclass 10, count 2 2006.257.10:20:19.99#ibcon#about to read 5, iclass 10, count 2 2006.257.10:20:19.99#ibcon#read 5, iclass 10, count 2 2006.257.10:20:19.99#ibcon#about to read 6, iclass 10, count 2 2006.257.10:20:19.99#ibcon#read 6, iclass 10, count 2 2006.257.10:20:19.99#ibcon#end of sib2, iclass 10, count 2 2006.257.10:20:19.99#ibcon#*mode == 0, iclass 10, count 2 2006.257.10:20:19.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.10:20:19.99#ibcon#[27=AT04-05\r\n] 2006.257.10:20:19.99#ibcon#*before write, iclass 10, count 2 2006.257.10:20:19.99#ibcon#enter sib2, iclass 10, count 2 2006.257.10:20:19.99#ibcon#flushed, iclass 10, count 2 2006.257.10:20:19.99#ibcon#about to write, iclass 10, count 2 2006.257.10:20:19.99#ibcon#wrote, iclass 10, count 2 2006.257.10:20:19.99#ibcon#about to read 3, iclass 10, count 2 2006.257.10:20:20.02#ibcon#read 3, iclass 10, count 2 2006.257.10:20:20.02#ibcon#about to read 4, iclass 10, count 2 2006.257.10:20:20.02#ibcon#read 4, iclass 10, count 2 2006.257.10:20:20.02#ibcon#about to read 5, iclass 10, count 2 2006.257.10:20:20.02#ibcon#read 5, iclass 10, count 2 2006.257.10:20:20.02#ibcon#about to read 6, iclass 10, count 2 2006.257.10:20:20.02#ibcon#read 6, iclass 10, count 2 2006.257.10:20:20.02#ibcon#end of sib2, iclass 10, count 2 2006.257.10:20:20.02#ibcon#*after write, iclass 10, count 2 2006.257.10:20:20.02#ibcon#*before return 0, iclass 10, count 2 2006.257.10:20:20.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:20.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:20:20.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.10:20:20.02#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:20.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:20.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:20.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:20.14#ibcon#enter wrdev, iclass 10, count 0 2006.257.10:20:20.14#ibcon#first serial, iclass 10, count 0 2006.257.10:20:20.14#ibcon#enter sib2, iclass 10, count 0 2006.257.10:20:20.14#ibcon#flushed, iclass 10, count 0 2006.257.10:20:20.14#ibcon#about to write, iclass 10, count 0 2006.257.10:20:20.14#ibcon#wrote, iclass 10, count 0 2006.257.10:20:20.14#ibcon#about to read 3, iclass 10, count 0 2006.257.10:20:20.16#ibcon#read 3, iclass 10, count 0 2006.257.10:20:20.16#ibcon#about to read 4, iclass 10, count 0 2006.257.10:20:20.16#ibcon#read 4, iclass 10, count 0 2006.257.10:20:20.16#ibcon#about to read 5, iclass 10, count 0 2006.257.10:20:20.16#ibcon#read 5, iclass 10, count 0 2006.257.10:20:20.16#ibcon#about to read 6, iclass 10, count 0 2006.257.10:20:20.16#ibcon#read 6, iclass 10, count 0 2006.257.10:20:20.16#ibcon#end of sib2, iclass 10, count 0 2006.257.10:20:20.16#ibcon#*mode == 0, iclass 10, count 0 2006.257.10:20:20.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.10:20:20.16#ibcon#[27=USB\r\n] 2006.257.10:20:20.16#ibcon#*before write, iclass 10, count 0 2006.257.10:20:20.16#ibcon#enter sib2, iclass 10, count 0 2006.257.10:20:20.16#ibcon#flushed, iclass 10, count 0 2006.257.10:20:20.16#ibcon#about to write, iclass 10, count 0 2006.257.10:20:20.16#ibcon#wrote, iclass 10, count 0 2006.257.10:20:20.16#ibcon#about to read 3, iclass 10, count 0 2006.257.10:20:20.19#ibcon#read 3, iclass 10, count 0 2006.257.10:20:20.19#ibcon#about to read 4, iclass 10, count 0 2006.257.10:20:20.19#ibcon#read 4, iclass 10, count 0 2006.257.10:20:20.19#ibcon#about to read 5, iclass 10, count 0 2006.257.10:20:20.19#ibcon#read 5, iclass 10, count 0 2006.257.10:20:20.19#ibcon#about to read 6, iclass 10, count 0 2006.257.10:20:20.19#ibcon#read 6, iclass 10, count 0 2006.257.10:20:20.19#ibcon#end of sib2, iclass 10, count 0 2006.257.10:20:20.19#ibcon#*after write, iclass 10, count 0 2006.257.10:20:20.19#ibcon#*before return 0, iclass 10, count 0 2006.257.10:20:20.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:20.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:20:20.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.10:20:20.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.10:20:20.19$vck44/vblo=5,709.99 2006.257.10:20:20.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.10:20:20.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.10:20:20.19#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:20.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:20.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:20.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:20.19#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:20:20.19#ibcon#first serial, iclass 12, count 0 2006.257.10:20:20.19#ibcon#enter sib2, iclass 12, count 0 2006.257.10:20:20.19#ibcon#flushed, iclass 12, count 0 2006.257.10:20:20.19#ibcon#about to write, iclass 12, count 0 2006.257.10:20:20.19#ibcon#wrote, iclass 12, count 0 2006.257.10:20:20.19#ibcon#about to read 3, iclass 12, count 0 2006.257.10:20:20.21#ibcon#read 3, iclass 12, count 0 2006.257.10:20:20.21#ibcon#about to read 4, iclass 12, count 0 2006.257.10:20:20.21#ibcon#read 4, iclass 12, count 0 2006.257.10:20:20.21#ibcon#about to read 5, iclass 12, count 0 2006.257.10:20:20.21#ibcon#read 5, iclass 12, count 0 2006.257.10:20:20.21#ibcon#about to read 6, iclass 12, count 0 2006.257.10:20:20.21#ibcon#read 6, iclass 12, count 0 2006.257.10:20:20.21#ibcon#end of sib2, iclass 12, count 0 2006.257.10:20:20.21#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:20:20.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:20:20.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:20:20.21#ibcon#*before write, iclass 12, count 0 2006.257.10:20:20.21#ibcon#enter sib2, iclass 12, count 0 2006.257.10:20:20.21#ibcon#flushed, iclass 12, count 0 2006.257.10:20:20.21#ibcon#about to write, iclass 12, count 0 2006.257.10:20:20.21#ibcon#wrote, iclass 12, count 0 2006.257.10:20:20.21#ibcon#about to read 3, iclass 12, count 0 2006.257.10:20:20.25#ibcon#read 3, iclass 12, count 0 2006.257.10:20:20.25#ibcon#about to read 4, iclass 12, count 0 2006.257.10:20:20.25#ibcon#read 4, iclass 12, count 0 2006.257.10:20:20.25#ibcon#about to read 5, iclass 12, count 0 2006.257.10:20:20.25#ibcon#read 5, iclass 12, count 0 2006.257.10:20:20.25#ibcon#about to read 6, iclass 12, count 0 2006.257.10:20:20.25#ibcon#read 6, iclass 12, count 0 2006.257.10:20:20.25#ibcon#end of sib2, iclass 12, count 0 2006.257.10:20:20.25#ibcon#*after write, iclass 12, count 0 2006.257.10:20:20.25#ibcon#*before return 0, iclass 12, count 0 2006.257.10:20:20.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:20.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:20:20.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:20:20.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:20:20.25$vck44/vb=5,4 2006.257.10:20:20.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.10:20:20.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.10:20:20.25#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:20.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:20.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:20.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:20.31#ibcon#enter wrdev, iclass 14, count 2 2006.257.10:20:20.31#ibcon#first serial, iclass 14, count 2 2006.257.10:20:20.31#ibcon#enter sib2, iclass 14, count 2 2006.257.10:20:20.31#ibcon#flushed, iclass 14, count 2 2006.257.10:20:20.31#ibcon#about to write, iclass 14, count 2 2006.257.10:20:20.31#ibcon#wrote, iclass 14, count 2 2006.257.10:20:20.31#ibcon#about to read 3, iclass 14, count 2 2006.257.10:20:20.33#ibcon#read 3, iclass 14, count 2 2006.257.10:20:20.33#ibcon#about to read 4, iclass 14, count 2 2006.257.10:20:20.33#ibcon#read 4, iclass 14, count 2 2006.257.10:20:20.33#ibcon#about to read 5, iclass 14, count 2 2006.257.10:20:20.33#ibcon#read 5, iclass 14, count 2 2006.257.10:20:20.33#ibcon#about to read 6, iclass 14, count 2 2006.257.10:20:20.33#ibcon#read 6, iclass 14, count 2 2006.257.10:20:20.33#ibcon#end of sib2, iclass 14, count 2 2006.257.10:20:20.33#ibcon#*mode == 0, iclass 14, count 2 2006.257.10:20:20.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.10:20:20.33#ibcon#[27=AT05-04\r\n] 2006.257.10:20:20.33#ibcon#*before write, iclass 14, count 2 2006.257.10:20:20.33#ibcon#enter sib2, iclass 14, count 2 2006.257.10:20:20.33#ibcon#flushed, iclass 14, count 2 2006.257.10:20:20.33#ibcon#about to write, iclass 14, count 2 2006.257.10:20:20.33#ibcon#wrote, iclass 14, count 2 2006.257.10:20:20.33#ibcon#about to read 3, iclass 14, count 2 2006.257.10:20:20.36#ibcon#read 3, iclass 14, count 2 2006.257.10:20:20.36#ibcon#about to read 4, iclass 14, count 2 2006.257.10:20:20.36#ibcon#read 4, iclass 14, count 2 2006.257.10:20:20.36#ibcon#about to read 5, iclass 14, count 2 2006.257.10:20:20.36#ibcon#read 5, iclass 14, count 2 2006.257.10:20:20.37#ibcon#about to read 6, iclass 14, count 2 2006.257.10:20:20.37#ibcon#read 6, iclass 14, count 2 2006.257.10:20:20.37#ibcon#end of sib2, iclass 14, count 2 2006.257.10:20:20.37#ibcon#*after write, iclass 14, count 2 2006.257.10:20:20.37#ibcon#*before return 0, iclass 14, count 2 2006.257.10:20:20.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:20.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:20:20.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.10:20:20.37#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:20.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:20.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:20.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:20.48#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:20:20.48#ibcon#first serial, iclass 14, count 0 2006.257.10:20:20.48#ibcon#enter sib2, iclass 14, count 0 2006.257.10:20:20.48#ibcon#flushed, iclass 14, count 0 2006.257.10:20:20.48#ibcon#about to write, iclass 14, count 0 2006.257.10:20:20.48#ibcon#wrote, iclass 14, count 0 2006.257.10:20:20.48#ibcon#about to read 3, iclass 14, count 0 2006.257.10:20:20.50#ibcon#read 3, iclass 14, count 0 2006.257.10:20:20.50#ibcon#about to read 4, iclass 14, count 0 2006.257.10:20:20.50#ibcon#read 4, iclass 14, count 0 2006.257.10:20:20.50#ibcon#about to read 5, iclass 14, count 0 2006.257.10:20:20.50#ibcon#read 5, iclass 14, count 0 2006.257.10:20:20.50#ibcon#about to read 6, iclass 14, count 0 2006.257.10:20:20.50#ibcon#read 6, iclass 14, count 0 2006.257.10:20:20.50#ibcon#end of sib2, iclass 14, count 0 2006.257.10:20:20.50#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:20:20.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:20:20.50#ibcon#[27=USB\r\n] 2006.257.10:20:20.50#ibcon#*before write, iclass 14, count 0 2006.257.10:20:20.50#ibcon#enter sib2, iclass 14, count 0 2006.257.10:20:20.50#ibcon#flushed, iclass 14, count 0 2006.257.10:20:20.50#ibcon#about to write, iclass 14, count 0 2006.257.10:20:20.50#ibcon#wrote, iclass 14, count 0 2006.257.10:20:20.50#ibcon#about to read 3, iclass 14, count 0 2006.257.10:20:20.53#ibcon#read 3, iclass 14, count 0 2006.257.10:20:20.53#ibcon#about to read 4, iclass 14, count 0 2006.257.10:20:20.53#ibcon#read 4, iclass 14, count 0 2006.257.10:20:20.53#ibcon#about to read 5, iclass 14, count 0 2006.257.10:20:20.53#ibcon#read 5, iclass 14, count 0 2006.257.10:20:20.53#ibcon#about to read 6, iclass 14, count 0 2006.257.10:20:20.53#ibcon#read 6, iclass 14, count 0 2006.257.10:20:20.53#ibcon#end of sib2, iclass 14, count 0 2006.257.10:20:20.53#ibcon#*after write, iclass 14, count 0 2006.257.10:20:20.53#ibcon#*before return 0, iclass 14, count 0 2006.257.10:20:20.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:20.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:20:20.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:20:20.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:20:20.53$vck44/vblo=6,719.99 2006.257.10:20:20.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.10:20:20.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.10:20:20.53#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:20.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:20.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:20.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:20.53#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:20:20.53#ibcon#first serial, iclass 16, count 0 2006.257.10:20:20.53#ibcon#enter sib2, iclass 16, count 0 2006.257.10:20:20.53#ibcon#flushed, iclass 16, count 0 2006.257.10:20:20.53#ibcon#about to write, iclass 16, count 0 2006.257.10:20:20.53#ibcon#wrote, iclass 16, count 0 2006.257.10:20:20.53#ibcon#about to read 3, iclass 16, count 0 2006.257.10:20:20.55#ibcon#read 3, iclass 16, count 0 2006.257.10:20:20.55#ibcon#about to read 4, iclass 16, count 0 2006.257.10:20:20.55#ibcon#read 4, iclass 16, count 0 2006.257.10:20:20.55#ibcon#about to read 5, iclass 16, count 0 2006.257.10:20:20.55#ibcon#read 5, iclass 16, count 0 2006.257.10:20:20.55#ibcon#about to read 6, iclass 16, count 0 2006.257.10:20:20.55#ibcon#read 6, iclass 16, count 0 2006.257.10:20:20.55#ibcon#end of sib2, iclass 16, count 0 2006.257.10:20:20.55#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:20:20.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:20:20.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:20:20.55#ibcon#*before write, iclass 16, count 0 2006.257.10:20:20.55#ibcon#enter sib2, iclass 16, count 0 2006.257.10:20:20.55#ibcon#flushed, iclass 16, count 0 2006.257.10:20:20.55#ibcon#about to write, iclass 16, count 0 2006.257.10:20:20.55#ibcon#wrote, iclass 16, count 0 2006.257.10:20:20.55#ibcon#about to read 3, iclass 16, count 0 2006.257.10:20:20.59#ibcon#read 3, iclass 16, count 0 2006.257.10:20:20.59#ibcon#about to read 4, iclass 16, count 0 2006.257.10:20:20.59#ibcon#read 4, iclass 16, count 0 2006.257.10:20:20.59#ibcon#about to read 5, iclass 16, count 0 2006.257.10:20:20.59#ibcon#read 5, iclass 16, count 0 2006.257.10:20:20.59#ibcon#about to read 6, iclass 16, count 0 2006.257.10:20:20.59#ibcon#read 6, iclass 16, count 0 2006.257.10:20:20.59#ibcon#end of sib2, iclass 16, count 0 2006.257.10:20:20.59#ibcon#*after write, iclass 16, count 0 2006.257.10:20:20.59#ibcon#*before return 0, iclass 16, count 0 2006.257.10:20:20.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:20.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:20:20.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:20:20.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:20:20.59$vck44/vb=6,4 2006.257.10:20:20.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.10:20:20.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.10:20:20.59#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:20.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:20.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:20.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:20.65#ibcon#enter wrdev, iclass 18, count 2 2006.257.10:20:20.65#ibcon#first serial, iclass 18, count 2 2006.257.10:20:20.65#ibcon#enter sib2, iclass 18, count 2 2006.257.10:20:20.65#ibcon#flushed, iclass 18, count 2 2006.257.10:20:20.65#ibcon#about to write, iclass 18, count 2 2006.257.10:20:20.65#ibcon#wrote, iclass 18, count 2 2006.257.10:20:20.65#ibcon#about to read 3, iclass 18, count 2 2006.257.10:20:20.67#ibcon#read 3, iclass 18, count 2 2006.257.10:20:20.67#ibcon#about to read 4, iclass 18, count 2 2006.257.10:20:20.67#ibcon#read 4, iclass 18, count 2 2006.257.10:20:20.67#ibcon#about to read 5, iclass 18, count 2 2006.257.10:20:20.67#ibcon#read 5, iclass 18, count 2 2006.257.10:20:20.67#ibcon#about to read 6, iclass 18, count 2 2006.257.10:20:20.67#ibcon#read 6, iclass 18, count 2 2006.257.10:20:20.67#ibcon#end of sib2, iclass 18, count 2 2006.257.10:20:20.67#ibcon#*mode == 0, iclass 18, count 2 2006.257.10:20:20.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.10:20:20.67#ibcon#[27=AT06-04\r\n] 2006.257.10:20:20.67#ibcon#*before write, iclass 18, count 2 2006.257.10:20:20.67#ibcon#enter sib2, iclass 18, count 2 2006.257.10:20:20.67#ibcon#flushed, iclass 18, count 2 2006.257.10:20:20.67#ibcon#about to write, iclass 18, count 2 2006.257.10:20:20.67#ibcon#wrote, iclass 18, count 2 2006.257.10:20:20.67#ibcon#about to read 3, iclass 18, count 2 2006.257.10:20:20.70#ibcon#read 3, iclass 18, count 2 2006.257.10:20:20.70#ibcon#about to read 4, iclass 18, count 2 2006.257.10:20:20.70#ibcon#read 4, iclass 18, count 2 2006.257.10:20:20.70#ibcon#about to read 5, iclass 18, count 2 2006.257.10:20:20.70#ibcon#read 5, iclass 18, count 2 2006.257.10:20:20.70#ibcon#about to read 6, iclass 18, count 2 2006.257.10:20:20.70#ibcon#read 6, iclass 18, count 2 2006.257.10:20:20.70#ibcon#end of sib2, iclass 18, count 2 2006.257.10:20:20.70#ibcon#*after write, iclass 18, count 2 2006.257.10:20:20.70#ibcon#*before return 0, iclass 18, count 2 2006.257.10:20:20.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:20.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:20:20.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.10:20:20.70#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:20.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:20.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:20.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:20.82#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:20:20.82#ibcon#first serial, iclass 18, count 0 2006.257.10:20:20.82#ibcon#enter sib2, iclass 18, count 0 2006.257.10:20:20.82#ibcon#flushed, iclass 18, count 0 2006.257.10:20:20.82#ibcon#about to write, iclass 18, count 0 2006.257.10:20:20.82#ibcon#wrote, iclass 18, count 0 2006.257.10:20:20.82#ibcon#about to read 3, iclass 18, count 0 2006.257.10:20:20.84#ibcon#read 3, iclass 18, count 0 2006.257.10:20:20.84#ibcon#about to read 4, iclass 18, count 0 2006.257.10:20:20.84#ibcon#read 4, iclass 18, count 0 2006.257.10:20:20.84#ibcon#about to read 5, iclass 18, count 0 2006.257.10:20:20.84#ibcon#read 5, iclass 18, count 0 2006.257.10:20:20.84#ibcon#about to read 6, iclass 18, count 0 2006.257.10:20:20.84#ibcon#read 6, iclass 18, count 0 2006.257.10:20:20.84#ibcon#end of sib2, iclass 18, count 0 2006.257.10:20:20.84#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:20:20.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:20:20.84#ibcon#[27=USB\r\n] 2006.257.10:20:20.84#ibcon#*before write, iclass 18, count 0 2006.257.10:20:20.84#ibcon#enter sib2, iclass 18, count 0 2006.257.10:20:20.84#ibcon#flushed, iclass 18, count 0 2006.257.10:20:20.84#ibcon#about to write, iclass 18, count 0 2006.257.10:20:20.84#ibcon#wrote, iclass 18, count 0 2006.257.10:20:20.84#ibcon#about to read 3, iclass 18, count 0 2006.257.10:20:20.87#ibcon#read 3, iclass 18, count 0 2006.257.10:20:20.87#ibcon#about to read 4, iclass 18, count 0 2006.257.10:20:20.87#ibcon#read 4, iclass 18, count 0 2006.257.10:20:20.87#ibcon#about to read 5, iclass 18, count 0 2006.257.10:20:20.87#ibcon#read 5, iclass 18, count 0 2006.257.10:20:20.87#ibcon#about to read 6, iclass 18, count 0 2006.257.10:20:20.87#ibcon#read 6, iclass 18, count 0 2006.257.10:20:20.87#ibcon#end of sib2, iclass 18, count 0 2006.257.10:20:20.87#ibcon#*after write, iclass 18, count 0 2006.257.10:20:20.87#ibcon#*before return 0, iclass 18, count 0 2006.257.10:20:20.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:20.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:20:20.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:20:20.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:20:20.87$vck44/vblo=7,734.99 2006.257.10:20:20.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.10:20:20.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.10:20:20.87#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:20.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:20.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:20.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:20.87#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:20:20.87#ibcon#first serial, iclass 20, count 0 2006.257.10:20:20.87#ibcon#enter sib2, iclass 20, count 0 2006.257.10:20:20.87#ibcon#flushed, iclass 20, count 0 2006.257.10:20:20.87#ibcon#about to write, iclass 20, count 0 2006.257.10:20:20.87#ibcon#wrote, iclass 20, count 0 2006.257.10:20:20.87#ibcon#about to read 3, iclass 20, count 0 2006.257.10:20:20.89#ibcon#read 3, iclass 20, count 0 2006.257.10:20:20.89#ibcon#about to read 4, iclass 20, count 0 2006.257.10:20:20.89#ibcon#read 4, iclass 20, count 0 2006.257.10:20:20.89#ibcon#about to read 5, iclass 20, count 0 2006.257.10:20:20.89#ibcon#read 5, iclass 20, count 0 2006.257.10:20:20.89#ibcon#about to read 6, iclass 20, count 0 2006.257.10:20:20.89#ibcon#read 6, iclass 20, count 0 2006.257.10:20:20.89#ibcon#end of sib2, iclass 20, count 0 2006.257.10:20:20.89#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:20:20.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:20:20.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:20:20.89#ibcon#*before write, iclass 20, count 0 2006.257.10:20:20.89#ibcon#enter sib2, iclass 20, count 0 2006.257.10:20:20.89#ibcon#flushed, iclass 20, count 0 2006.257.10:20:20.89#ibcon#about to write, iclass 20, count 0 2006.257.10:20:20.89#ibcon#wrote, iclass 20, count 0 2006.257.10:20:20.89#ibcon#about to read 3, iclass 20, count 0 2006.257.10:20:20.93#ibcon#read 3, iclass 20, count 0 2006.257.10:20:20.93#ibcon#about to read 4, iclass 20, count 0 2006.257.10:20:20.93#ibcon#read 4, iclass 20, count 0 2006.257.10:20:20.93#ibcon#about to read 5, iclass 20, count 0 2006.257.10:20:20.93#ibcon#read 5, iclass 20, count 0 2006.257.10:20:20.93#ibcon#about to read 6, iclass 20, count 0 2006.257.10:20:20.93#ibcon#read 6, iclass 20, count 0 2006.257.10:20:20.93#ibcon#end of sib2, iclass 20, count 0 2006.257.10:20:20.93#ibcon#*after write, iclass 20, count 0 2006.257.10:20:20.93#ibcon#*before return 0, iclass 20, count 0 2006.257.10:20:20.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:20.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:20:20.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:20:20.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:20:20.93$vck44/vb=7,4 2006.257.10:20:20.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.10:20:20.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.10:20:20.93#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:20.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:20.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:20.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:20.99#ibcon#enter wrdev, iclass 22, count 2 2006.257.10:20:20.99#ibcon#first serial, iclass 22, count 2 2006.257.10:20:20.99#ibcon#enter sib2, iclass 22, count 2 2006.257.10:20:20.99#ibcon#flushed, iclass 22, count 2 2006.257.10:20:20.99#ibcon#about to write, iclass 22, count 2 2006.257.10:20:20.99#ibcon#wrote, iclass 22, count 2 2006.257.10:20:20.99#ibcon#about to read 3, iclass 22, count 2 2006.257.10:20:21.01#ibcon#read 3, iclass 22, count 2 2006.257.10:20:21.01#ibcon#about to read 4, iclass 22, count 2 2006.257.10:20:21.01#ibcon#read 4, iclass 22, count 2 2006.257.10:20:21.01#ibcon#about to read 5, iclass 22, count 2 2006.257.10:20:21.01#ibcon#read 5, iclass 22, count 2 2006.257.10:20:21.01#ibcon#about to read 6, iclass 22, count 2 2006.257.10:20:21.01#ibcon#read 6, iclass 22, count 2 2006.257.10:20:21.01#ibcon#end of sib2, iclass 22, count 2 2006.257.10:20:21.01#ibcon#*mode == 0, iclass 22, count 2 2006.257.10:20:21.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.10:20:21.01#ibcon#[27=AT07-04\r\n] 2006.257.10:20:21.01#ibcon#*before write, iclass 22, count 2 2006.257.10:20:21.01#ibcon#enter sib2, iclass 22, count 2 2006.257.10:20:21.01#ibcon#flushed, iclass 22, count 2 2006.257.10:20:21.01#ibcon#about to write, iclass 22, count 2 2006.257.10:20:21.01#ibcon#wrote, iclass 22, count 2 2006.257.10:20:21.01#ibcon#about to read 3, iclass 22, count 2 2006.257.10:20:21.04#ibcon#read 3, iclass 22, count 2 2006.257.10:20:21.04#ibcon#about to read 4, iclass 22, count 2 2006.257.10:20:21.04#ibcon#read 4, iclass 22, count 2 2006.257.10:20:21.04#ibcon#about to read 5, iclass 22, count 2 2006.257.10:20:21.04#ibcon#read 5, iclass 22, count 2 2006.257.10:20:21.04#ibcon#about to read 6, iclass 22, count 2 2006.257.10:20:21.04#ibcon#read 6, iclass 22, count 2 2006.257.10:20:21.04#ibcon#end of sib2, iclass 22, count 2 2006.257.10:20:21.04#ibcon#*after write, iclass 22, count 2 2006.257.10:20:21.04#ibcon#*before return 0, iclass 22, count 2 2006.257.10:20:21.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:21.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:20:21.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.10:20:21.04#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:21.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:21.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:21.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:21.16#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:20:21.16#ibcon#first serial, iclass 22, count 0 2006.257.10:20:21.16#ibcon#enter sib2, iclass 22, count 0 2006.257.10:20:21.16#ibcon#flushed, iclass 22, count 0 2006.257.10:20:21.16#ibcon#about to write, iclass 22, count 0 2006.257.10:20:21.16#ibcon#wrote, iclass 22, count 0 2006.257.10:20:21.16#ibcon#about to read 3, iclass 22, count 0 2006.257.10:20:21.18#ibcon#read 3, iclass 22, count 0 2006.257.10:20:21.18#ibcon#about to read 4, iclass 22, count 0 2006.257.10:20:21.18#ibcon#read 4, iclass 22, count 0 2006.257.10:20:21.18#ibcon#about to read 5, iclass 22, count 0 2006.257.10:20:21.18#ibcon#read 5, iclass 22, count 0 2006.257.10:20:21.18#ibcon#about to read 6, iclass 22, count 0 2006.257.10:20:21.18#ibcon#read 6, iclass 22, count 0 2006.257.10:20:21.18#ibcon#end of sib2, iclass 22, count 0 2006.257.10:20:21.18#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:20:21.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:20:21.18#ibcon#[27=USB\r\n] 2006.257.10:20:21.18#ibcon#*before write, iclass 22, count 0 2006.257.10:20:21.18#ibcon#enter sib2, iclass 22, count 0 2006.257.10:20:21.18#ibcon#flushed, iclass 22, count 0 2006.257.10:20:21.18#ibcon#about to write, iclass 22, count 0 2006.257.10:20:21.18#ibcon#wrote, iclass 22, count 0 2006.257.10:20:21.18#ibcon#about to read 3, iclass 22, count 0 2006.257.10:20:21.21#ibcon#read 3, iclass 22, count 0 2006.257.10:20:21.21#ibcon#about to read 4, iclass 22, count 0 2006.257.10:20:21.21#ibcon#read 4, iclass 22, count 0 2006.257.10:20:21.21#ibcon#about to read 5, iclass 22, count 0 2006.257.10:20:21.21#ibcon#read 5, iclass 22, count 0 2006.257.10:20:21.21#ibcon#about to read 6, iclass 22, count 0 2006.257.10:20:21.21#ibcon#read 6, iclass 22, count 0 2006.257.10:20:21.21#ibcon#end of sib2, iclass 22, count 0 2006.257.10:20:21.21#ibcon#*after write, iclass 22, count 0 2006.257.10:20:21.21#ibcon#*before return 0, iclass 22, count 0 2006.257.10:20:21.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:21.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:20:21.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:20:21.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:20:21.21$vck44/vblo=8,744.99 2006.257.10:20:21.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.10:20:21.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.10:20:21.21#ibcon#ireg 17 cls_cnt 0 2006.257.10:20:21.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:21.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:21.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:21.21#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:20:21.21#ibcon#first serial, iclass 24, count 0 2006.257.10:20:21.21#ibcon#enter sib2, iclass 24, count 0 2006.257.10:20:21.21#ibcon#flushed, iclass 24, count 0 2006.257.10:20:21.21#ibcon#about to write, iclass 24, count 0 2006.257.10:20:21.21#ibcon#wrote, iclass 24, count 0 2006.257.10:20:21.21#ibcon#about to read 3, iclass 24, count 0 2006.257.10:20:21.23#ibcon#read 3, iclass 24, count 0 2006.257.10:20:21.23#ibcon#about to read 4, iclass 24, count 0 2006.257.10:20:21.23#ibcon#read 4, iclass 24, count 0 2006.257.10:20:21.23#ibcon#about to read 5, iclass 24, count 0 2006.257.10:20:21.23#ibcon#read 5, iclass 24, count 0 2006.257.10:20:21.23#ibcon#about to read 6, iclass 24, count 0 2006.257.10:20:21.23#ibcon#read 6, iclass 24, count 0 2006.257.10:20:21.23#ibcon#end of sib2, iclass 24, count 0 2006.257.10:20:21.23#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:20:21.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:20:21.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:20:21.23#ibcon#*before write, iclass 24, count 0 2006.257.10:20:21.23#ibcon#enter sib2, iclass 24, count 0 2006.257.10:20:21.23#ibcon#flushed, iclass 24, count 0 2006.257.10:20:21.23#ibcon#about to write, iclass 24, count 0 2006.257.10:20:21.23#ibcon#wrote, iclass 24, count 0 2006.257.10:20:21.23#ibcon#about to read 3, iclass 24, count 0 2006.257.10:20:21.27#ibcon#read 3, iclass 24, count 0 2006.257.10:20:21.27#ibcon#about to read 4, iclass 24, count 0 2006.257.10:20:21.27#ibcon#read 4, iclass 24, count 0 2006.257.10:20:21.27#ibcon#about to read 5, iclass 24, count 0 2006.257.10:20:21.27#ibcon#read 5, iclass 24, count 0 2006.257.10:20:21.27#ibcon#about to read 6, iclass 24, count 0 2006.257.10:20:21.27#ibcon#read 6, iclass 24, count 0 2006.257.10:20:21.27#ibcon#end of sib2, iclass 24, count 0 2006.257.10:20:21.27#ibcon#*after write, iclass 24, count 0 2006.257.10:20:21.27#ibcon#*before return 0, iclass 24, count 0 2006.257.10:20:21.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:21.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:20:21.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:20:21.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:20:21.27$vck44/vb=8,4 2006.257.10:20:21.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.10:20:21.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.10:20:21.27#ibcon#ireg 11 cls_cnt 2 2006.257.10:20:21.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:21.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:21.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:21.33#ibcon#enter wrdev, iclass 26, count 2 2006.257.10:20:21.33#ibcon#first serial, iclass 26, count 2 2006.257.10:20:21.33#ibcon#enter sib2, iclass 26, count 2 2006.257.10:20:21.33#ibcon#flushed, iclass 26, count 2 2006.257.10:20:21.33#ibcon#about to write, iclass 26, count 2 2006.257.10:20:21.33#ibcon#wrote, iclass 26, count 2 2006.257.10:20:21.33#ibcon#about to read 3, iclass 26, count 2 2006.257.10:20:21.35#ibcon#read 3, iclass 26, count 2 2006.257.10:20:21.35#ibcon#about to read 4, iclass 26, count 2 2006.257.10:20:21.35#ibcon#read 4, iclass 26, count 2 2006.257.10:20:21.35#ibcon#about to read 5, iclass 26, count 2 2006.257.10:20:21.35#ibcon#read 5, iclass 26, count 2 2006.257.10:20:21.35#ibcon#about to read 6, iclass 26, count 2 2006.257.10:20:21.35#ibcon#read 6, iclass 26, count 2 2006.257.10:20:21.35#ibcon#end of sib2, iclass 26, count 2 2006.257.10:20:21.35#ibcon#*mode == 0, iclass 26, count 2 2006.257.10:20:21.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.10:20:21.35#ibcon#[27=AT08-04\r\n] 2006.257.10:20:21.35#ibcon#*before write, iclass 26, count 2 2006.257.10:20:21.35#ibcon#enter sib2, iclass 26, count 2 2006.257.10:20:21.35#ibcon#flushed, iclass 26, count 2 2006.257.10:20:21.35#ibcon#about to write, iclass 26, count 2 2006.257.10:20:21.35#ibcon#wrote, iclass 26, count 2 2006.257.10:20:21.35#ibcon#about to read 3, iclass 26, count 2 2006.257.10:20:21.38#ibcon#read 3, iclass 26, count 2 2006.257.10:20:21.38#ibcon#about to read 4, iclass 26, count 2 2006.257.10:20:21.38#ibcon#read 4, iclass 26, count 2 2006.257.10:20:21.38#ibcon#about to read 5, iclass 26, count 2 2006.257.10:20:21.38#ibcon#read 5, iclass 26, count 2 2006.257.10:20:21.38#ibcon#about to read 6, iclass 26, count 2 2006.257.10:20:21.38#ibcon#read 6, iclass 26, count 2 2006.257.10:20:21.38#ibcon#end of sib2, iclass 26, count 2 2006.257.10:20:21.38#ibcon#*after write, iclass 26, count 2 2006.257.10:20:21.40#ibcon#*before return 0, iclass 26, count 2 2006.257.10:20:21.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:21.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:20:21.40#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.10:20:21.40#ibcon#ireg 7 cls_cnt 0 2006.257.10:20:21.40#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:21.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:21.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:21.51#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:20:21.51#ibcon#first serial, iclass 26, count 0 2006.257.10:20:21.51#ibcon#enter sib2, iclass 26, count 0 2006.257.10:20:21.51#ibcon#flushed, iclass 26, count 0 2006.257.10:20:21.51#ibcon#about to write, iclass 26, count 0 2006.257.10:20:21.51#ibcon#wrote, iclass 26, count 0 2006.257.10:20:21.51#ibcon#about to read 3, iclass 26, count 0 2006.257.10:20:21.53#ibcon#read 3, iclass 26, count 0 2006.257.10:20:21.53#ibcon#about to read 4, iclass 26, count 0 2006.257.10:20:21.53#ibcon#read 4, iclass 26, count 0 2006.257.10:20:21.53#ibcon#about to read 5, iclass 26, count 0 2006.257.10:20:21.53#ibcon#read 5, iclass 26, count 0 2006.257.10:20:21.53#ibcon#about to read 6, iclass 26, count 0 2006.257.10:20:21.53#ibcon#read 6, iclass 26, count 0 2006.257.10:20:21.53#ibcon#end of sib2, iclass 26, count 0 2006.257.10:20:21.53#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:20:21.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:20:21.53#ibcon#[27=USB\r\n] 2006.257.10:20:21.53#ibcon#*before write, iclass 26, count 0 2006.257.10:20:21.53#ibcon#enter sib2, iclass 26, count 0 2006.257.10:20:21.53#ibcon#flushed, iclass 26, count 0 2006.257.10:20:21.53#ibcon#about to write, iclass 26, count 0 2006.257.10:20:21.53#ibcon#wrote, iclass 26, count 0 2006.257.10:20:21.53#ibcon#about to read 3, iclass 26, count 0 2006.257.10:20:21.56#ibcon#read 3, iclass 26, count 0 2006.257.10:20:21.56#ibcon#about to read 4, iclass 26, count 0 2006.257.10:20:21.56#ibcon#read 4, iclass 26, count 0 2006.257.10:20:21.56#ibcon#about to read 5, iclass 26, count 0 2006.257.10:20:21.56#ibcon#read 5, iclass 26, count 0 2006.257.10:20:21.56#ibcon#about to read 6, iclass 26, count 0 2006.257.10:20:21.56#ibcon#read 6, iclass 26, count 0 2006.257.10:20:21.56#ibcon#end of sib2, iclass 26, count 0 2006.257.10:20:21.56#ibcon#*after write, iclass 26, count 0 2006.257.10:20:21.56#ibcon#*before return 0, iclass 26, count 0 2006.257.10:20:21.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:21.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:20:21.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:20:21.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:20:21.56$vck44/vabw=wide 2006.257.10:20:21.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.10:20:21.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.10:20:21.56#ibcon#ireg 8 cls_cnt 0 2006.257.10:20:21.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:21.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:21.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:21.56#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:20:21.56#ibcon#first serial, iclass 28, count 0 2006.257.10:20:21.56#ibcon#enter sib2, iclass 28, count 0 2006.257.10:20:21.56#ibcon#flushed, iclass 28, count 0 2006.257.10:20:21.56#ibcon#about to write, iclass 28, count 0 2006.257.10:20:21.56#ibcon#wrote, iclass 28, count 0 2006.257.10:20:21.56#ibcon#about to read 3, iclass 28, count 0 2006.257.10:20:21.58#ibcon#read 3, iclass 28, count 0 2006.257.10:20:21.58#ibcon#about to read 4, iclass 28, count 0 2006.257.10:20:21.58#ibcon#read 4, iclass 28, count 0 2006.257.10:20:21.58#ibcon#about to read 5, iclass 28, count 0 2006.257.10:20:21.58#ibcon#read 5, iclass 28, count 0 2006.257.10:20:21.58#ibcon#about to read 6, iclass 28, count 0 2006.257.10:20:21.58#ibcon#read 6, iclass 28, count 0 2006.257.10:20:21.58#ibcon#end of sib2, iclass 28, count 0 2006.257.10:20:21.58#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:20:21.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:20:21.58#ibcon#[25=BW32\r\n] 2006.257.10:20:21.58#ibcon#*before write, iclass 28, count 0 2006.257.10:20:21.58#ibcon#enter sib2, iclass 28, count 0 2006.257.10:20:21.58#ibcon#flushed, iclass 28, count 0 2006.257.10:20:21.58#ibcon#about to write, iclass 28, count 0 2006.257.10:20:21.58#ibcon#wrote, iclass 28, count 0 2006.257.10:20:21.58#ibcon#about to read 3, iclass 28, count 0 2006.257.10:20:21.61#ibcon#read 3, iclass 28, count 0 2006.257.10:20:21.61#ibcon#about to read 4, iclass 28, count 0 2006.257.10:20:21.61#ibcon#read 4, iclass 28, count 0 2006.257.10:20:21.61#ibcon#about to read 5, iclass 28, count 0 2006.257.10:20:21.61#ibcon#read 5, iclass 28, count 0 2006.257.10:20:21.61#ibcon#about to read 6, iclass 28, count 0 2006.257.10:20:21.61#ibcon#read 6, iclass 28, count 0 2006.257.10:20:21.61#ibcon#end of sib2, iclass 28, count 0 2006.257.10:20:21.61#ibcon#*after write, iclass 28, count 0 2006.257.10:20:21.61#ibcon#*before return 0, iclass 28, count 0 2006.257.10:20:21.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:21.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:20:21.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:20:21.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:20:21.61$vck44/vbbw=wide 2006.257.10:20:21.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.10:20:21.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.10:20:21.61#ibcon#ireg 8 cls_cnt 0 2006.257.10:20:21.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:20:21.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:20:21.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:20:21.68#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:20:21.68#ibcon#first serial, iclass 30, count 0 2006.257.10:20:21.68#ibcon#enter sib2, iclass 30, count 0 2006.257.10:20:21.68#ibcon#flushed, iclass 30, count 0 2006.257.10:20:21.68#ibcon#about to write, iclass 30, count 0 2006.257.10:20:21.68#ibcon#wrote, iclass 30, count 0 2006.257.10:20:21.68#ibcon#about to read 3, iclass 30, count 0 2006.257.10:20:21.70#ibcon#read 3, iclass 30, count 0 2006.257.10:20:21.70#ibcon#about to read 4, iclass 30, count 0 2006.257.10:20:21.70#ibcon#read 4, iclass 30, count 0 2006.257.10:20:21.70#ibcon#about to read 5, iclass 30, count 0 2006.257.10:20:21.70#ibcon#read 5, iclass 30, count 0 2006.257.10:20:21.70#ibcon#about to read 6, iclass 30, count 0 2006.257.10:20:21.70#ibcon#read 6, iclass 30, count 0 2006.257.10:20:21.70#ibcon#end of sib2, iclass 30, count 0 2006.257.10:20:21.70#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:20:21.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:20:21.70#ibcon#[27=BW32\r\n] 2006.257.10:20:21.70#ibcon#*before write, iclass 30, count 0 2006.257.10:20:21.70#ibcon#enter sib2, iclass 30, count 0 2006.257.10:20:21.70#ibcon#flushed, iclass 30, count 0 2006.257.10:20:21.70#ibcon#about to write, iclass 30, count 0 2006.257.10:20:21.70#ibcon#wrote, iclass 30, count 0 2006.257.10:20:21.70#ibcon#about to read 3, iclass 30, count 0 2006.257.10:20:21.73#ibcon#read 3, iclass 30, count 0 2006.257.10:20:21.73#ibcon#about to read 4, iclass 30, count 0 2006.257.10:20:21.73#ibcon#read 4, iclass 30, count 0 2006.257.10:20:21.73#ibcon#about to read 5, iclass 30, count 0 2006.257.10:20:21.73#ibcon#read 5, iclass 30, count 0 2006.257.10:20:21.73#ibcon#about to read 6, iclass 30, count 0 2006.257.10:20:21.73#ibcon#read 6, iclass 30, count 0 2006.257.10:20:21.73#ibcon#end of sib2, iclass 30, count 0 2006.257.10:20:21.73#ibcon#*after write, iclass 30, count 0 2006.257.10:20:21.73#ibcon#*before return 0, iclass 30, count 0 2006.257.10:20:21.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:20:21.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:20:21.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:20:21.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:20:21.73$setupk4/ifdk4 2006.257.10:20:21.73$ifdk4/lo= 2006.257.10:20:21.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:20:21.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:20:21.73$ifdk4/patch= 2006.257.10:20:21.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:20:21.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:20:21.74$setupk4/!*+20s 2006.257.10:20:26.70#abcon#<5=/14 1.1 3.4 19.01 961013.6\r\n> 2006.257.10:20:26.72#abcon#{5=INTERFACE CLEAR} 2006.257.10:20:26.78#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:20:29.14#trakl#Source acquired 2006.257.10:20:29.14#flagr#flagr/antenna,acquired 2006.257.10:20:36.21$setupk4/"tpicd 2006.257.10:20:36.21$setupk4/echo=off 2006.257.10:20:36.21$setupk4/xlog=off 2006.257.10:20:36.21:!2006.257.10:24:52 2006.257.10:24:52.00:preob 2006.257.10:24:52.14/onsource/TRACKING 2006.257.10:24:52.14:!2006.257.10:25:02 2006.257.10:25:02.00:"tape 2006.257.10:25:02.00:"st=record 2006.257.10:25:02.00:data_valid=on 2006.257.10:25:02.00:midob 2006.257.10:25:02.14/onsource/TRACKING 2006.257.10:25:02.14/wx/18.96,1013.6,96 2006.257.10:25:02.31/cable/+6.4764E-03 2006.257.10:25:03.40/va/01,08,usb,yes,31,33 2006.257.10:25:03.40/va/02,07,usb,yes,33,34 2006.257.10:25:03.40/va/03,08,usb,yes,30,31 2006.257.10:25:03.40/va/04,07,usb,yes,34,36 2006.257.10:25:03.40/va/05,04,usb,yes,30,31 2006.257.10:25:03.40/va/06,04,usb,yes,34,34 2006.257.10:25:03.40/va/07,04,usb,yes,35,35 2006.257.10:25:03.40/va/08,04,usb,yes,29,36 2006.257.10:25:03.63/valo/01,524.99,yes,locked 2006.257.10:25:03.63/valo/02,534.99,yes,locked 2006.257.10:25:03.63/valo/03,564.99,yes,locked 2006.257.10:25:03.63/valo/04,624.99,yes,locked 2006.257.10:25:03.63/valo/05,734.99,yes,locked 2006.257.10:25:03.63/valo/06,814.99,yes,locked 2006.257.10:25:03.63/valo/07,864.99,yes,locked 2006.257.10:25:03.63/valo/08,884.99,yes,locked 2006.257.10:25:04.72/vb/01,04,usb,yes,31,28 2006.257.10:25:04.72/vb/02,05,usb,yes,29,29 2006.257.10:25:04.72/vb/03,04,usb,yes,30,33 2006.257.10:25:04.72/vb/04,05,usb,yes,30,29 2006.257.10:25:04.72/vb/05,04,usb,yes,27,29 2006.257.10:25:04.72/vb/06,04,usb,yes,31,27 2006.257.10:25:04.72/vb/07,04,usb,yes,31,31 2006.257.10:25:04.72/vb/08,04,usb,yes,28,32 2006.257.10:25:04.96/vblo/01,629.99,yes,locked 2006.257.10:25:04.96/vblo/02,634.99,yes,locked 2006.257.10:25:04.96/vblo/03,649.99,yes,locked 2006.257.10:25:04.96/vblo/04,679.99,yes,locked 2006.257.10:25:04.96/vblo/05,709.99,yes,locked 2006.257.10:25:04.96/vblo/06,719.99,yes,locked 2006.257.10:25:04.96/vblo/07,734.99,yes,locked 2006.257.10:25:04.96/vblo/08,744.99,yes,locked 2006.257.10:25:05.11/vabw/8 2006.257.10:25:05.26/vbbw/8 2006.257.10:25:05.35/xfe/off,on,14.7 2006.257.10:25:05.72/ifatt/23,28,28,28 2006.257.10:25:06.07/fmout-gps/S +4.59E-07 2006.257.10:25:06.11:!2006.257.10:27:22 2006.257.10:27:22.01:data_valid=off 2006.257.10:27:22.02:"et 2006.257.10:27:22.02:!+3s 2006.257.10:27:25.03:"tape 2006.257.10:27:25.03:postob 2006.257.10:27:25.15/cable/+6.4748E-03 2006.257.10:27:25.16/wx/18.93,1013.6,96 2006.257.10:27:25.21/fmout-gps/S +4.61E-07 2006.257.10:27:25.22:scan_name=257-1029,jd0609,80 2006.257.10:27:25.22:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.10:27:26.14#flagr#flagr/antenna,new-source 2006.257.10:27:26.15:checkk5 2006.257.10:27:26.58/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:27:26.98/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:27:27.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:27:27.78/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:27:28.17/chk_obsdata//k5ts1/T2571025??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.10:27:28.57/chk_obsdata//k5ts2/T2571025??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.10:27:28.96/chk_obsdata//k5ts3/T2571025??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.10:27:29.35/chk_obsdata//k5ts4/T2571025??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.10:27:30.08/k5log//k5ts1_log_newline 2006.257.10:27:30.80/k5log//k5ts2_log_newline 2006.257.10:27:31.53/k5log//k5ts3_log_newline 2006.257.10:27:32.24/k5log//k5ts4_log_newline 2006.257.10:27:32.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:27:32.26:setupk4=1 2006.257.10:27:32.26$setupk4/echo=on 2006.257.10:27:32.26$setupk4/pcalon 2006.257.10:27:32.26$pcalon/"no phase cal control is implemented here 2006.257.10:27:32.26$setupk4/"tpicd=stop 2006.257.10:27:32.26$setupk4/"rec=synch_on 2006.257.10:27:32.26$setupk4/"rec_mode=128 2006.257.10:27:32.26$setupk4/!* 2006.257.10:27:32.26$setupk4/recpk4 2006.257.10:27:32.26$recpk4/recpatch= 2006.257.10:27:32.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:27:32.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:27:32.26$setupk4/vck44 2006.257.10:27:32.27$vck44/valo=1,524.99 2006.257.10:27:32.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.10:27:32.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.10:27:32.27#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:32.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:32.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:32.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:32.27#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:27:32.27#ibcon#first serial, iclass 23, count 0 2006.257.10:27:32.27#ibcon#enter sib2, iclass 23, count 0 2006.257.10:27:32.27#ibcon#flushed, iclass 23, count 0 2006.257.10:27:32.27#ibcon#about to write, iclass 23, count 0 2006.257.10:27:32.27#ibcon#wrote, iclass 23, count 0 2006.257.10:27:32.27#ibcon#about to read 3, iclass 23, count 0 2006.257.10:27:32.28#ibcon#read 3, iclass 23, count 0 2006.257.10:27:32.28#ibcon#about to read 4, iclass 23, count 0 2006.257.10:27:32.28#ibcon#read 4, iclass 23, count 0 2006.257.10:27:32.28#ibcon#about to read 5, iclass 23, count 0 2006.257.10:27:32.28#ibcon#read 5, iclass 23, count 0 2006.257.10:27:32.28#ibcon#about to read 6, iclass 23, count 0 2006.257.10:27:32.28#ibcon#read 6, iclass 23, count 0 2006.257.10:27:32.28#ibcon#end of sib2, iclass 23, count 0 2006.257.10:27:32.28#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:27:32.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:27:32.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:27:32.28#ibcon#*before write, iclass 23, count 0 2006.257.10:27:32.28#ibcon#enter sib2, iclass 23, count 0 2006.257.10:27:32.28#ibcon#flushed, iclass 23, count 0 2006.257.10:27:32.28#ibcon#about to write, iclass 23, count 0 2006.257.10:27:32.28#ibcon#wrote, iclass 23, count 0 2006.257.10:27:32.28#ibcon#about to read 3, iclass 23, count 0 2006.257.10:27:32.33#ibcon#read 3, iclass 23, count 0 2006.257.10:27:32.33#ibcon#about to read 4, iclass 23, count 0 2006.257.10:27:32.33#ibcon#read 4, iclass 23, count 0 2006.257.10:27:32.33#ibcon#about to read 5, iclass 23, count 0 2006.257.10:27:32.33#ibcon#read 5, iclass 23, count 0 2006.257.10:27:32.33#ibcon#about to read 6, iclass 23, count 0 2006.257.10:27:32.33#ibcon#read 6, iclass 23, count 0 2006.257.10:27:32.33#ibcon#end of sib2, iclass 23, count 0 2006.257.10:27:32.33#ibcon#*after write, iclass 23, count 0 2006.257.10:27:32.33#ibcon#*before return 0, iclass 23, count 0 2006.257.10:27:32.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:32.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:32.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:27:32.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:27:32.33$vck44/va=1,8 2006.257.10:27:32.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.10:27:32.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.10:27:32.33#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:32.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:32.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:32.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:32.33#ibcon#enter wrdev, iclass 25, count 2 2006.257.10:27:32.33#ibcon#first serial, iclass 25, count 2 2006.257.10:27:32.33#ibcon#enter sib2, iclass 25, count 2 2006.257.10:27:32.33#ibcon#flushed, iclass 25, count 2 2006.257.10:27:32.33#ibcon#about to write, iclass 25, count 2 2006.257.10:27:32.33#ibcon#wrote, iclass 25, count 2 2006.257.10:27:32.33#ibcon#about to read 3, iclass 25, count 2 2006.257.10:27:32.35#ibcon#read 3, iclass 25, count 2 2006.257.10:27:32.35#ibcon#about to read 4, iclass 25, count 2 2006.257.10:27:32.35#ibcon#read 4, iclass 25, count 2 2006.257.10:27:32.35#ibcon#about to read 5, iclass 25, count 2 2006.257.10:27:32.35#ibcon#read 5, iclass 25, count 2 2006.257.10:27:32.35#ibcon#about to read 6, iclass 25, count 2 2006.257.10:27:32.35#ibcon#read 6, iclass 25, count 2 2006.257.10:27:32.35#ibcon#end of sib2, iclass 25, count 2 2006.257.10:27:32.35#ibcon#*mode == 0, iclass 25, count 2 2006.257.10:27:32.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.10:27:32.35#ibcon#[25=AT01-08\r\n] 2006.257.10:27:32.35#ibcon#*before write, iclass 25, count 2 2006.257.10:27:32.35#ibcon#enter sib2, iclass 25, count 2 2006.257.10:27:32.35#ibcon#flushed, iclass 25, count 2 2006.257.10:27:32.35#ibcon#about to write, iclass 25, count 2 2006.257.10:27:32.35#ibcon#wrote, iclass 25, count 2 2006.257.10:27:32.35#ibcon#about to read 3, iclass 25, count 2 2006.257.10:27:32.38#ibcon#read 3, iclass 25, count 2 2006.257.10:27:32.38#ibcon#about to read 4, iclass 25, count 2 2006.257.10:27:32.38#ibcon#read 4, iclass 25, count 2 2006.257.10:27:32.38#ibcon#about to read 5, iclass 25, count 2 2006.257.10:27:32.38#ibcon#read 5, iclass 25, count 2 2006.257.10:27:32.38#ibcon#about to read 6, iclass 25, count 2 2006.257.10:27:32.38#ibcon#read 6, iclass 25, count 2 2006.257.10:27:32.38#ibcon#end of sib2, iclass 25, count 2 2006.257.10:27:32.38#ibcon#*after write, iclass 25, count 2 2006.257.10:27:32.38#ibcon#*before return 0, iclass 25, count 2 2006.257.10:27:32.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:32.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:32.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.10:27:32.38#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:32.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:32.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:32.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:32.50#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:27:32.50#ibcon#first serial, iclass 25, count 0 2006.257.10:27:32.50#ibcon#enter sib2, iclass 25, count 0 2006.257.10:27:32.50#ibcon#flushed, iclass 25, count 0 2006.257.10:27:32.50#ibcon#about to write, iclass 25, count 0 2006.257.10:27:32.50#ibcon#wrote, iclass 25, count 0 2006.257.10:27:32.50#ibcon#about to read 3, iclass 25, count 0 2006.257.10:27:32.52#ibcon#read 3, iclass 25, count 0 2006.257.10:27:32.52#ibcon#about to read 4, iclass 25, count 0 2006.257.10:27:32.52#ibcon#read 4, iclass 25, count 0 2006.257.10:27:32.52#ibcon#about to read 5, iclass 25, count 0 2006.257.10:27:32.52#ibcon#read 5, iclass 25, count 0 2006.257.10:27:32.52#ibcon#about to read 6, iclass 25, count 0 2006.257.10:27:32.52#ibcon#read 6, iclass 25, count 0 2006.257.10:27:32.52#ibcon#end of sib2, iclass 25, count 0 2006.257.10:27:32.52#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:27:32.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:27:32.52#ibcon#[25=USB\r\n] 2006.257.10:27:32.52#ibcon#*before write, iclass 25, count 0 2006.257.10:27:32.52#ibcon#enter sib2, iclass 25, count 0 2006.257.10:27:32.52#ibcon#flushed, iclass 25, count 0 2006.257.10:27:32.52#ibcon#about to write, iclass 25, count 0 2006.257.10:27:32.52#ibcon#wrote, iclass 25, count 0 2006.257.10:27:32.52#ibcon#about to read 3, iclass 25, count 0 2006.257.10:27:32.55#ibcon#read 3, iclass 25, count 0 2006.257.10:27:32.55#ibcon#about to read 4, iclass 25, count 0 2006.257.10:27:32.55#ibcon#read 4, iclass 25, count 0 2006.257.10:27:32.55#ibcon#about to read 5, iclass 25, count 0 2006.257.10:27:32.55#ibcon#read 5, iclass 25, count 0 2006.257.10:27:32.55#ibcon#about to read 6, iclass 25, count 0 2006.257.10:27:32.55#ibcon#read 6, iclass 25, count 0 2006.257.10:27:32.55#ibcon#end of sib2, iclass 25, count 0 2006.257.10:27:32.55#ibcon#*after write, iclass 25, count 0 2006.257.10:27:32.55#ibcon#*before return 0, iclass 25, count 0 2006.257.10:27:32.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:32.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:32.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:27:32.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:27:32.55$vck44/valo=2,534.99 2006.257.10:27:32.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.10:27:32.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.10:27:32.55#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:32.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:32.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:32.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:32.55#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:27:32.55#ibcon#first serial, iclass 27, count 0 2006.257.10:27:32.55#ibcon#enter sib2, iclass 27, count 0 2006.257.10:27:32.55#ibcon#flushed, iclass 27, count 0 2006.257.10:27:32.55#ibcon#about to write, iclass 27, count 0 2006.257.10:27:32.55#ibcon#wrote, iclass 27, count 0 2006.257.10:27:32.55#ibcon#about to read 3, iclass 27, count 0 2006.257.10:27:32.57#ibcon#read 3, iclass 27, count 0 2006.257.10:27:32.57#ibcon#about to read 4, iclass 27, count 0 2006.257.10:27:32.57#ibcon#read 4, iclass 27, count 0 2006.257.10:27:32.57#ibcon#about to read 5, iclass 27, count 0 2006.257.10:27:32.57#ibcon#read 5, iclass 27, count 0 2006.257.10:27:32.57#ibcon#about to read 6, iclass 27, count 0 2006.257.10:27:32.57#ibcon#read 6, iclass 27, count 0 2006.257.10:27:32.57#ibcon#end of sib2, iclass 27, count 0 2006.257.10:27:32.57#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:27:32.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:27:32.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:27:32.57#ibcon#*before write, iclass 27, count 0 2006.257.10:27:32.57#ibcon#enter sib2, iclass 27, count 0 2006.257.10:27:32.57#ibcon#flushed, iclass 27, count 0 2006.257.10:27:32.57#ibcon#about to write, iclass 27, count 0 2006.257.10:27:32.57#ibcon#wrote, iclass 27, count 0 2006.257.10:27:32.57#ibcon#about to read 3, iclass 27, count 0 2006.257.10:27:32.61#ibcon#read 3, iclass 27, count 0 2006.257.10:27:32.61#ibcon#about to read 4, iclass 27, count 0 2006.257.10:27:32.61#ibcon#read 4, iclass 27, count 0 2006.257.10:27:32.61#ibcon#about to read 5, iclass 27, count 0 2006.257.10:27:32.61#ibcon#read 5, iclass 27, count 0 2006.257.10:27:32.61#ibcon#about to read 6, iclass 27, count 0 2006.257.10:27:32.61#ibcon#read 6, iclass 27, count 0 2006.257.10:27:32.61#ibcon#end of sib2, iclass 27, count 0 2006.257.10:27:32.61#ibcon#*after write, iclass 27, count 0 2006.257.10:27:32.61#ibcon#*before return 0, iclass 27, count 0 2006.257.10:27:32.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:32.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:32.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:27:32.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:27:32.61$vck44/va=2,7 2006.257.10:27:32.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.10:27:32.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.10:27:32.61#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:32.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:32.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:32.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:32.67#ibcon#enter wrdev, iclass 29, count 2 2006.257.10:27:32.67#ibcon#first serial, iclass 29, count 2 2006.257.10:27:32.67#ibcon#enter sib2, iclass 29, count 2 2006.257.10:27:32.67#ibcon#flushed, iclass 29, count 2 2006.257.10:27:32.67#ibcon#about to write, iclass 29, count 2 2006.257.10:27:32.67#ibcon#wrote, iclass 29, count 2 2006.257.10:27:32.67#ibcon#about to read 3, iclass 29, count 2 2006.257.10:27:32.69#ibcon#read 3, iclass 29, count 2 2006.257.10:27:32.69#ibcon#about to read 4, iclass 29, count 2 2006.257.10:27:32.69#ibcon#read 4, iclass 29, count 2 2006.257.10:27:32.69#ibcon#about to read 5, iclass 29, count 2 2006.257.10:27:32.69#ibcon#read 5, iclass 29, count 2 2006.257.10:27:32.69#ibcon#about to read 6, iclass 29, count 2 2006.257.10:27:32.69#ibcon#read 6, iclass 29, count 2 2006.257.10:27:32.69#ibcon#end of sib2, iclass 29, count 2 2006.257.10:27:32.69#ibcon#*mode == 0, iclass 29, count 2 2006.257.10:27:32.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.10:27:32.69#ibcon#[25=AT02-07\r\n] 2006.257.10:27:32.69#ibcon#*before write, iclass 29, count 2 2006.257.10:27:32.69#ibcon#enter sib2, iclass 29, count 2 2006.257.10:27:32.69#ibcon#flushed, iclass 29, count 2 2006.257.10:27:32.69#ibcon#about to write, iclass 29, count 2 2006.257.10:27:32.69#ibcon#wrote, iclass 29, count 2 2006.257.10:27:32.69#ibcon#about to read 3, iclass 29, count 2 2006.257.10:27:32.72#ibcon#read 3, iclass 29, count 2 2006.257.10:27:32.72#ibcon#about to read 4, iclass 29, count 2 2006.257.10:27:32.72#ibcon#read 4, iclass 29, count 2 2006.257.10:27:32.72#ibcon#about to read 5, iclass 29, count 2 2006.257.10:27:32.72#ibcon#read 5, iclass 29, count 2 2006.257.10:27:32.72#ibcon#about to read 6, iclass 29, count 2 2006.257.10:27:32.72#ibcon#read 6, iclass 29, count 2 2006.257.10:27:32.72#ibcon#end of sib2, iclass 29, count 2 2006.257.10:27:32.72#ibcon#*after write, iclass 29, count 2 2006.257.10:27:32.72#ibcon#*before return 0, iclass 29, count 2 2006.257.10:27:32.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:32.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:32.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.10:27:32.72#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:32.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:32.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:32.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:32.84#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:27:32.84#ibcon#first serial, iclass 29, count 0 2006.257.10:27:32.84#ibcon#enter sib2, iclass 29, count 0 2006.257.10:27:32.84#ibcon#flushed, iclass 29, count 0 2006.257.10:27:32.84#ibcon#about to write, iclass 29, count 0 2006.257.10:27:32.84#ibcon#wrote, iclass 29, count 0 2006.257.10:27:32.84#ibcon#about to read 3, iclass 29, count 0 2006.257.10:27:32.86#ibcon#read 3, iclass 29, count 0 2006.257.10:27:32.86#ibcon#about to read 4, iclass 29, count 0 2006.257.10:27:32.86#ibcon#read 4, iclass 29, count 0 2006.257.10:27:32.86#ibcon#about to read 5, iclass 29, count 0 2006.257.10:27:32.86#ibcon#read 5, iclass 29, count 0 2006.257.10:27:32.86#ibcon#about to read 6, iclass 29, count 0 2006.257.10:27:32.86#ibcon#read 6, iclass 29, count 0 2006.257.10:27:32.86#ibcon#end of sib2, iclass 29, count 0 2006.257.10:27:32.86#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:27:32.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:27:32.86#ibcon#[25=USB\r\n] 2006.257.10:27:32.86#ibcon#*before write, iclass 29, count 0 2006.257.10:27:32.86#ibcon#enter sib2, iclass 29, count 0 2006.257.10:27:32.86#ibcon#flushed, iclass 29, count 0 2006.257.10:27:32.86#ibcon#about to write, iclass 29, count 0 2006.257.10:27:32.86#ibcon#wrote, iclass 29, count 0 2006.257.10:27:32.86#ibcon#about to read 3, iclass 29, count 0 2006.257.10:27:32.89#ibcon#read 3, iclass 29, count 0 2006.257.10:27:32.89#ibcon#about to read 4, iclass 29, count 0 2006.257.10:27:32.89#ibcon#read 4, iclass 29, count 0 2006.257.10:27:32.89#ibcon#about to read 5, iclass 29, count 0 2006.257.10:27:32.89#ibcon#read 5, iclass 29, count 0 2006.257.10:27:32.89#ibcon#about to read 6, iclass 29, count 0 2006.257.10:27:32.89#ibcon#read 6, iclass 29, count 0 2006.257.10:27:32.89#ibcon#end of sib2, iclass 29, count 0 2006.257.10:27:32.89#ibcon#*after write, iclass 29, count 0 2006.257.10:27:32.89#ibcon#*before return 0, iclass 29, count 0 2006.257.10:27:32.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:32.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:32.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:27:32.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:27:32.89$vck44/valo=3,564.99 2006.257.10:27:32.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.10:27:32.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.10:27:32.89#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:32.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:32.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:32.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:32.89#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:27:32.89#ibcon#first serial, iclass 31, count 0 2006.257.10:27:32.89#ibcon#enter sib2, iclass 31, count 0 2006.257.10:27:32.89#ibcon#flushed, iclass 31, count 0 2006.257.10:27:32.89#ibcon#about to write, iclass 31, count 0 2006.257.10:27:32.89#ibcon#wrote, iclass 31, count 0 2006.257.10:27:32.89#ibcon#about to read 3, iclass 31, count 0 2006.257.10:27:32.91#ibcon#read 3, iclass 31, count 0 2006.257.10:27:32.91#ibcon#about to read 4, iclass 31, count 0 2006.257.10:27:32.91#ibcon#read 4, iclass 31, count 0 2006.257.10:27:32.91#ibcon#about to read 5, iclass 31, count 0 2006.257.10:27:32.91#ibcon#read 5, iclass 31, count 0 2006.257.10:27:32.91#ibcon#about to read 6, iclass 31, count 0 2006.257.10:27:32.91#ibcon#read 6, iclass 31, count 0 2006.257.10:27:32.91#ibcon#end of sib2, iclass 31, count 0 2006.257.10:27:32.91#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:27:32.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:27:32.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:27:32.91#ibcon#*before write, iclass 31, count 0 2006.257.10:27:32.91#ibcon#enter sib2, iclass 31, count 0 2006.257.10:27:32.91#ibcon#flushed, iclass 31, count 0 2006.257.10:27:32.91#ibcon#about to write, iclass 31, count 0 2006.257.10:27:32.91#ibcon#wrote, iclass 31, count 0 2006.257.10:27:32.91#ibcon#about to read 3, iclass 31, count 0 2006.257.10:27:32.95#ibcon#read 3, iclass 31, count 0 2006.257.10:27:32.95#ibcon#about to read 4, iclass 31, count 0 2006.257.10:27:32.95#ibcon#read 4, iclass 31, count 0 2006.257.10:27:32.95#ibcon#about to read 5, iclass 31, count 0 2006.257.10:27:32.95#ibcon#read 5, iclass 31, count 0 2006.257.10:27:32.95#ibcon#about to read 6, iclass 31, count 0 2006.257.10:27:32.95#ibcon#read 6, iclass 31, count 0 2006.257.10:27:32.95#ibcon#end of sib2, iclass 31, count 0 2006.257.10:27:32.95#ibcon#*after write, iclass 31, count 0 2006.257.10:27:32.95#ibcon#*before return 0, iclass 31, count 0 2006.257.10:27:32.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:32.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:32.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:27:32.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:27:32.95$vck44/va=3,8 2006.257.10:27:32.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.10:27:32.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.10:27:32.95#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:32.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:33.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:33.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:33.01#ibcon#enter wrdev, iclass 33, count 2 2006.257.10:27:33.01#ibcon#first serial, iclass 33, count 2 2006.257.10:27:33.01#ibcon#enter sib2, iclass 33, count 2 2006.257.10:27:33.01#ibcon#flushed, iclass 33, count 2 2006.257.10:27:33.01#ibcon#about to write, iclass 33, count 2 2006.257.10:27:33.01#ibcon#wrote, iclass 33, count 2 2006.257.10:27:33.01#ibcon#about to read 3, iclass 33, count 2 2006.257.10:27:33.03#ibcon#read 3, iclass 33, count 2 2006.257.10:27:33.03#ibcon#about to read 4, iclass 33, count 2 2006.257.10:27:33.03#ibcon#read 4, iclass 33, count 2 2006.257.10:27:33.03#ibcon#about to read 5, iclass 33, count 2 2006.257.10:27:33.03#ibcon#read 5, iclass 33, count 2 2006.257.10:27:33.03#ibcon#about to read 6, iclass 33, count 2 2006.257.10:27:33.03#ibcon#read 6, iclass 33, count 2 2006.257.10:27:33.03#ibcon#end of sib2, iclass 33, count 2 2006.257.10:27:33.03#ibcon#*mode == 0, iclass 33, count 2 2006.257.10:27:33.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.10:27:33.03#ibcon#[25=AT03-08\r\n] 2006.257.10:27:33.03#ibcon#*before write, iclass 33, count 2 2006.257.10:27:33.03#ibcon#enter sib2, iclass 33, count 2 2006.257.10:27:33.03#ibcon#flushed, iclass 33, count 2 2006.257.10:27:33.03#ibcon#about to write, iclass 33, count 2 2006.257.10:27:33.03#ibcon#wrote, iclass 33, count 2 2006.257.10:27:33.03#ibcon#about to read 3, iclass 33, count 2 2006.257.10:27:33.06#ibcon#read 3, iclass 33, count 2 2006.257.10:27:33.06#ibcon#about to read 4, iclass 33, count 2 2006.257.10:27:33.06#ibcon#read 4, iclass 33, count 2 2006.257.10:27:33.06#ibcon#about to read 5, iclass 33, count 2 2006.257.10:27:33.06#ibcon#read 5, iclass 33, count 2 2006.257.10:27:33.06#ibcon#about to read 6, iclass 33, count 2 2006.257.10:27:33.06#ibcon#read 6, iclass 33, count 2 2006.257.10:27:33.06#ibcon#end of sib2, iclass 33, count 2 2006.257.10:27:33.06#ibcon#*after write, iclass 33, count 2 2006.257.10:27:33.06#ibcon#*before return 0, iclass 33, count 2 2006.257.10:27:33.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:33.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:33.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.10:27:33.06#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:33.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:33.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:33.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:33.18#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:27:33.18#ibcon#first serial, iclass 33, count 0 2006.257.10:27:33.18#ibcon#enter sib2, iclass 33, count 0 2006.257.10:27:33.18#ibcon#flushed, iclass 33, count 0 2006.257.10:27:33.18#ibcon#about to write, iclass 33, count 0 2006.257.10:27:33.18#ibcon#wrote, iclass 33, count 0 2006.257.10:27:33.18#ibcon#about to read 3, iclass 33, count 0 2006.257.10:27:33.20#ibcon#read 3, iclass 33, count 0 2006.257.10:27:33.20#ibcon#about to read 4, iclass 33, count 0 2006.257.10:27:33.20#ibcon#read 4, iclass 33, count 0 2006.257.10:27:33.20#ibcon#about to read 5, iclass 33, count 0 2006.257.10:27:33.20#ibcon#read 5, iclass 33, count 0 2006.257.10:27:33.20#ibcon#about to read 6, iclass 33, count 0 2006.257.10:27:33.20#ibcon#read 6, iclass 33, count 0 2006.257.10:27:33.20#ibcon#end of sib2, iclass 33, count 0 2006.257.10:27:33.20#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:27:33.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:27:33.20#ibcon#[25=USB\r\n] 2006.257.10:27:33.20#ibcon#*before write, iclass 33, count 0 2006.257.10:27:33.20#ibcon#enter sib2, iclass 33, count 0 2006.257.10:27:33.20#ibcon#flushed, iclass 33, count 0 2006.257.10:27:33.20#ibcon#about to write, iclass 33, count 0 2006.257.10:27:33.20#ibcon#wrote, iclass 33, count 0 2006.257.10:27:33.20#ibcon#about to read 3, iclass 33, count 0 2006.257.10:27:33.23#ibcon#read 3, iclass 33, count 0 2006.257.10:27:33.23#ibcon#about to read 4, iclass 33, count 0 2006.257.10:27:33.23#ibcon#read 4, iclass 33, count 0 2006.257.10:27:33.23#ibcon#about to read 5, iclass 33, count 0 2006.257.10:27:33.23#ibcon#read 5, iclass 33, count 0 2006.257.10:27:33.23#ibcon#about to read 6, iclass 33, count 0 2006.257.10:27:33.23#ibcon#read 6, iclass 33, count 0 2006.257.10:27:33.23#ibcon#end of sib2, iclass 33, count 0 2006.257.10:27:33.23#ibcon#*after write, iclass 33, count 0 2006.257.10:27:33.23#ibcon#*before return 0, iclass 33, count 0 2006.257.10:27:33.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:33.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:33.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:27:33.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:27:33.23$vck44/valo=4,624.99 2006.257.10:27:33.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.10:27:33.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.10:27:33.23#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:33.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:33.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:33.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:33.23#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:27:33.23#ibcon#first serial, iclass 35, count 0 2006.257.10:27:33.23#ibcon#enter sib2, iclass 35, count 0 2006.257.10:27:33.23#ibcon#flushed, iclass 35, count 0 2006.257.10:27:33.23#ibcon#about to write, iclass 35, count 0 2006.257.10:27:33.23#ibcon#wrote, iclass 35, count 0 2006.257.10:27:33.23#ibcon#about to read 3, iclass 35, count 0 2006.257.10:27:33.25#ibcon#read 3, iclass 35, count 0 2006.257.10:27:33.25#ibcon#about to read 4, iclass 35, count 0 2006.257.10:27:33.25#ibcon#read 4, iclass 35, count 0 2006.257.10:27:33.25#ibcon#about to read 5, iclass 35, count 0 2006.257.10:27:33.25#ibcon#read 5, iclass 35, count 0 2006.257.10:27:33.25#ibcon#about to read 6, iclass 35, count 0 2006.257.10:27:33.25#ibcon#read 6, iclass 35, count 0 2006.257.10:27:33.25#ibcon#end of sib2, iclass 35, count 0 2006.257.10:27:33.25#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:27:33.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:27:33.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:27:33.25#ibcon#*before write, iclass 35, count 0 2006.257.10:27:33.25#ibcon#enter sib2, iclass 35, count 0 2006.257.10:27:33.25#ibcon#flushed, iclass 35, count 0 2006.257.10:27:33.25#ibcon#about to write, iclass 35, count 0 2006.257.10:27:33.25#ibcon#wrote, iclass 35, count 0 2006.257.10:27:33.25#ibcon#about to read 3, iclass 35, count 0 2006.257.10:27:33.29#ibcon#read 3, iclass 35, count 0 2006.257.10:27:33.29#ibcon#about to read 4, iclass 35, count 0 2006.257.10:27:33.29#ibcon#read 4, iclass 35, count 0 2006.257.10:27:33.29#ibcon#about to read 5, iclass 35, count 0 2006.257.10:27:33.29#ibcon#read 5, iclass 35, count 0 2006.257.10:27:33.29#ibcon#about to read 6, iclass 35, count 0 2006.257.10:27:33.29#ibcon#read 6, iclass 35, count 0 2006.257.10:27:33.29#ibcon#end of sib2, iclass 35, count 0 2006.257.10:27:33.29#ibcon#*after write, iclass 35, count 0 2006.257.10:27:33.29#ibcon#*before return 0, iclass 35, count 0 2006.257.10:27:33.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:33.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:33.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:27:33.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:27:33.29$vck44/va=4,7 2006.257.10:27:33.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.10:27:33.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.10:27:33.29#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:33.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:33.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:33.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:33.35#ibcon#enter wrdev, iclass 37, count 2 2006.257.10:27:33.35#ibcon#first serial, iclass 37, count 2 2006.257.10:27:33.35#ibcon#enter sib2, iclass 37, count 2 2006.257.10:27:33.35#ibcon#flushed, iclass 37, count 2 2006.257.10:27:33.35#ibcon#about to write, iclass 37, count 2 2006.257.10:27:33.35#ibcon#wrote, iclass 37, count 2 2006.257.10:27:33.35#ibcon#about to read 3, iclass 37, count 2 2006.257.10:27:33.37#ibcon#read 3, iclass 37, count 2 2006.257.10:27:33.37#ibcon#about to read 4, iclass 37, count 2 2006.257.10:27:33.37#ibcon#read 4, iclass 37, count 2 2006.257.10:27:33.37#ibcon#about to read 5, iclass 37, count 2 2006.257.10:27:33.37#ibcon#read 5, iclass 37, count 2 2006.257.10:27:33.37#ibcon#about to read 6, iclass 37, count 2 2006.257.10:27:33.37#ibcon#read 6, iclass 37, count 2 2006.257.10:27:33.37#ibcon#end of sib2, iclass 37, count 2 2006.257.10:27:33.37#ibcon#*mode == 0, iclass 37, count 2 2006.257.10:27:33.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.10:27:33.37#ibcon#[25=AT04-07\r\n] 2006.257.10:27:33.37#ibcon#*before write, iclass 37, count 2 2006.257.10:27:33.37#ibcon#enter sib2, iclass 37, count 2 2006.257.10:27:33.37#ibcon#flushed, iclass 37, count 2 2006.257.10:27:33.37#ibcon#about to write, iclass 37, count 2 2006.257.10:27:33.37#ibcon#wrote, iclass 37, count 2 2006.257.10:27:33.37#ibcon#about to read 3, iclass 37, count 2 2006.257.10:27:33.40#ibcon#read 3, iclass 37, count 2 2006.257.10:27:33.40#ibcon#about to read 4, iclass 37, count 2 2006.257.10:27:33.40#ibcon#read 4, iclass 37, count 2 2006.257.10:27:33.40#ibcon#about to read 5, iclass 37, count 2 2006.257.10:27:33.40#ibcon#read 5, iclass 37, count 2 2006.257.10:27:33.40#ibcon#about to read 6, iclass 37, count 2 2006.257.10:27:33.40#ibcon#read 6, iclass 37, count 2 2006.257.10:27:33.40#ibcon#end of sib2, iclass 37, count 2 2006.257.10:27:33.40#ibcon#*after write, iclass 37, count 2 2006.257.10:27:33.40#ibcon#*before return 0, iclass 37, count 2 2006.257.10:27:33.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:33.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:33.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.10:27:33.40#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:33.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:33.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:33.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:33.52#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:27:33.52#ibcon#first serial, iclass 37, count 0 2006.257.10:27:33.52#ibcon#enter sib2, iclass 37, count 0 2006.257.10:27:33.52#ibcon#flushed, iclass 37, count 0 2006.257.10:27:33.52#ibcon#about to write, iclass 37, count 0 2006.257.10:27:33.52#ibcon#wrote, iclass 37, count 0 2006.257.10:27:33.52#ibcon#about to read 3, iclass 37, count 0 2006.257.10:27:33.54#ibcon#read 3, iclass 37, count 0 2006.257.10:27:33.54#ibcon#about to read 4, iclass 37, count 0 2006.257.10:27:33.54#ibcon#read 4, iclass 37, count 0 2006.257.10:27:33.54#ibcon#about to read 5, iclass 37, count 0 2006.257.10:27:33.54#ibcon#read 5, iclass 37, count 0 2006.257.10:27:33.54#ibcon#about to read 6, iclass 37, count 0 2006.257.10:27:33.54#ibcon#read 6, iclass 37, count 0 2006.257.10:27:33.54#ibcon#end of sib2, iclass 37, count 0 2006.257.10:27:33.54#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:27:33.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:27:33.54#ibcon#[25=USB\r\n] 2006.257.10:27:33.54#ibcon#*before write, iclass 37, count 0 2006.257.10:27:33.54#ibcon#enter sib2, iclass 37, count 0 2006.257.10:27:33.54#ibcon#flushed, iclass 37, count 0 2006.257.10:27:33.54#ibcon#about to write, iclass 37, count 0 2006.257.10:27:33.54#ibcon#wrote, iclass 37, count 0 2006.257.10:27:33.54#ibcon#about to read 3, iclass 37, count 0 2006.257.10:27:33.57#ibcon#read 3, iclass 37, count 0 2006.257.10:27:33.57#ibcon#about to read 4, iclass 37, count 0 2006.257.10:27:33.57#ibcon#read 4, iclass 37, count 0 2006.257.10:27:33.57#ibcon#about to read 5, iclass 37, count 0 2006.257.10:27:33.57#ibcon#read 5, iclass 37, count 0 2006.257.10:27:33.57#ibcon#about to read 6, iclass 37, count 0 2006.257.10:27:33.57#ibcon#read 6, iclass 37, count 0 2006.257.10:27:33.57#ibcon#end of sib2, iclass 37, count 0 2006.257.10:27:33.57#ibcon#*after write, iclass 37, count 0 2006.257.10:27:33.57#ibcon#*before return 0, iclass 37, count 0 2006.257.10:27:33.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:33.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:33.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:27:33.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:27:33.57$vck44/valo=5,734.99 2006.257.10:27:33.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.10:27:33.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.10:27:33.57#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:33.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:33.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:33.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:33.57#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:27:33.57#ibcon#first serial, iclass 39, count 0 2006.257.10:27:33.57#ibcon#enter sib2, iclass 39, count 0 2006.257.10:27:33.57#ibcon#flushed, iclass 39, count 0 2006.257.10:27:33.57#ibcon#about to write, iclass 39, count 0 2006.257.10:27:33.57#ibcon#wrote, iclass 39, count 0 2006.257.10:27:33.57#ibcon#about to read 3, iclass 39, count 0 2006.257.10:27:33.59#ibcon#read 3, iclass 39, count 0 2006.257.10:27:33.59#ibcon#about to read 4, iclass 39, count 0 2006.257.10:27:33.59#ibcon#read 4, iclass 39, count 0 2006.257.10:27:33.59#ibcon#about to read 5, iclass 39, count 0 2006.257.10:27:33.59#ibcon#read 5, iclass 39, count 0 2006.257.10:27:33.59#ibcon#about to read 6, iclass 39, count 0 2006.257.10:27:33.59#ibcon#read 6, iclass 39, count 0 2006.257.10:27:33.59#ibcon#end of sib2, iclass 39, count 0 2006.257.10:27:33.59#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:27:33.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:27:33.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:27:33.59#ibcon#*before write, iclass 39, count 0 2006.257.10:27:33.59#ibcon#enter sib2, iclass 39, count 0 2006.257.10:27:33.59#ibcon#flushed, iclass 39, count 0 2006.257.10:27:33.59#ibcon#about to write, iclass 39, count 0 2006.257.10:27:33.59#ibcon#wrote, iclass 39, count 0 2006.257.10:27:33.59#ibcon#about to read 3, iclass 39, count 0 2006.257.10:27:33.63#ibcon#read 3, iclass 39, count 0 2006.257.10:27:33.63#ibcon#about to read 4, iclass 39, count 0 2006.257.10:27:33.63#ibcon#read 4, iclass 39, count 0 2006.257.10:27:33.63#ibcon#about to read 5, iclass 39, count 0 2006.257.10:27:33.63#ibcon#read 5, iclass 39, count 0 2006.257.10:27:33.63#ibcon#about to read 6, iclass 39, count 0 2006.257.10:27:33.63#ibcon#read 6, iclass 39, count 0 2006.257.10:27:33.63#ibcon#end of sib2, iclass 39, count 0 2006.257.10:27:33.63#ibcon#*after write, iclass 39, count 0 2006.257.10:27:33.63#ibcon#*before return 0, iclass 39, count 0 2006.257.10:27:33.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:33.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:33.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:27:33.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:27:33.63$vck44/va=5,4 2006.257.10:27:33.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.10:27:33.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.10:27:33.63#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:33.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:33.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:33.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:33.69#ibcon#enter wrdev, iclass 3, count 2 2006.257.10:27:33.69#ibcon#first serial, iclass 3, count 2 2006.257.10:27:33.69#ibcon#enter sib2, iclass 3, count 2 2006.257.10:27:33.69#ibcon#flushed, iclass 3, count 2 2006.257.10:27:33.69#ibcon#about to write, iclass 3, count 2 2006.257.10:27:33.69#ibcon#wrote, iclass 3, count 2 2006.257.10:27:33.69#ibcon#about to read 3, iclass 3, count 2 2006.257.10:27:33.71#ibcon#read 3, iclass 3, count 2 2006.257.10:27:33.71#ibcon#about to read 4, iclass 3, count 2 2006.257.10:27:33.71#ibcon#read 4, iclass 3, count 2 2006.257.10:27:33.71#ibcon#about to read 5, iclass 3, count 2 2006.257.10:27:33.71#ibcon#read 5, iclass 3, count 2 2006.257.10:27:33.71#ibcon#about to read 6, iclass 3, count 2 2006.257.10:27:33.71#ibcon#read 6, iclass 3, count 2 2006.257.10:27:33.71#ibcon#end of sib2, iclass 3, count 2 2006.257.10:27:33.71#ibcon#*mode == 0, iclass 3, count 2 2006.257.10:27:33.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.10:27:33.71#ibcon#[25=AT05-04\r\n] 2006.257.10:27:33.71#ibcon#*before write, iclass 3, count 2 2006.257.10:27:33.71#ibcon#enter sib2, iclass 3, count 2 2006.257.10:27:33.71#ibcon#flushed, iclass 3, count 2 2006.257.10:27:33.71#ibcon#about to write, iclass 3, count 2 2006.257.10:27:33.71#ibcon#wrote, iclass 3, count 2 2006.257.10:27:33.71#ibcon#about to read 3, iclass 3, count 2 2006.257.10:27:33.74#ibcon#read 3, iclass 3, count 2 2006.257.10:27:33.74#ibcon#about to read 4, iclass 3, count 2 2006.257.10:27:33.74#ibcon#read 4, iclass 3, count 2 2006.257.10:27:33.74#ibcon#about to read 5, iclass 3, count 2 2006.257.10:27:33.74#ibcon#read 5, iclass 3, count 2 2006.257.10:27:33.74#ibcon#about to read 6, iclass 3, count 2 2006.257.10:27:33.74#ibcon#read 6, iclass 3, count 2 2006.257.10:27:33.74#ibcon#end of sib2, iclass 3, count 2 2006.257.10:27:33.74#ibcon#*after write, iclass 3, count 2 2006.257.10:27:33.74#ibcon#*before return 0, iclass 3, count 2 2006.257.10:27:33.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:33.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:33.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.10:27:33.74#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:33.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:33.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:33.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:33.86#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:27:33.86#ibcon#first serial, iclass 3, count 0 2006.257.10:27:33.86#ibcon#enter sib2, iclass 3, count 0 2006.257.10:27:33.86#ibcon#flushed, iclass 3, count 0 2006.257.10:27:33.86#ibcon#about to write, iclass 3, count 0 2006.257.10:27:33.86#ibcon#wrote, iclass 3, count 0 2006.257.10:27:33.86#ibcon#about to read 3, iclass 3, count 0 2006.257.10:27:33.88#ibcon#read 3, iclass 3, count 0 2006.257.10:27:33.88#ibcon#about to read 4, iclass 3, count 0 2006.257.10:27:33.88#ibcon#read 4, iclass 3, count 0 2006.257.10:27:33.88#ibcon#about to read 5, iclass 3, count 0 2006.257.10:27:33.88#ibcon#read 5, iclass 3, count 0 2006.257.10:27:33.88#ibcon#about to read 6, iclass 3, count 0 2006.257.10:27:33.88#ibcon#read 6, iclass 3, count 0 2006.257.10:27:33.88#ibcon#end of sib2, iclass 3, count 0 2006.257.10:27:33.88#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:27:33.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:27:33.88#ibcon#[25=USB\r\n] 2006.257.10:27:33.88#ibcon#*before write, iclass 3, count 0 2006.257.10:27:33.88#ibcon#enter sib2, iclass 3, count 0 2006.257.10:27:33.88#ibcon#flushed, iclass 3, count 0 2006.257.10:27:33.88#ibcon#about to write, iclass 3, count 0 2006.257.10:27:33.88#ibcon#wrote, iclass 3, count 0 2006.257.10:27:33.88#ibcon#about to read 3, iclass 3, count 0 2006.257.10:27:33.91#ibcon#read 3, iclass 3, count 0 2006.257.10:27:33.91#ibcon#about to read 4, iclass 3, count 0 2006.257.10:27:33.91#ibcon#read 4, iclass 3, count 0 2006.257.10:27:33.91#ibcon#about to read 5, iclass 3, count 0 2006.257.10:27:33.91#ibcon#read 5, iclass 3, count 0 2006.257.10:27:33.91#ibcon#about to read 6, iclass 3, count 0 2006.257.10:27:33.91#ibcon#read 6, iclass 3, count 0 2006.257.10:27:33.91#ibcon#end of sib2, iclass 3, count 0 2006.257.10:27:33.91#ibcon#*after write, iclass 3, count 0 2006.257.10:27:33.91#ibcon#*before return 0, iclass 3, count 0 2006.257.10:27:33.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:33.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:33.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:27:33.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:27:33.91$vck44/valo=6,814.99 2006.257.10:27:33.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.10:27:33.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.10:27:33.91#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:33.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:33.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:33.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:33.91#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:27:33.91#ibcon#first serial, iclass 5, count 0 2006.257.10:27:33.91#ibcon#enter sib2, iclass 5, count 0 2006.257.10:27:33.91#ibcon#flushed, iclass 5, count 0 2006.257.10:27:33.91#ibcon#about to write, iclass 5, count 0 2006.257.10:27:33.91#ibcon#wrote, iclass 5, count 0 2006.257.10:27:33.91#ibcon#about to read 3, iclass 5, count 0 2006.257.10:27:33.93#ibcon#read 3, iclass 5, count 0 2006.257.10:27:33.93#ibcon#about to read 4, iclass 5, count 0 2006.257.10:27:33.93#ibcon#read 4, iclass 5, count 0 2006.257.10:27:33.93#ibcon#about to read 5, iclass 5, count 0 2006.257.10:27:33.93#ibcon#read 5, iclass 5, count 0 2006.257.10:27:33.93#ibcon#about to read 6, iclass 5, count 0 2006.257.10:27:33.93#ibcon#read 6, iclass 5, count 0 2006.257.10:27:33.93#ibcon#end of sib2, iclass 5, count 0 2006.257.10:27:33.93#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:27:33.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:27:33.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:27:33.93#ibcon#*before write, iclass 5, count 0 2006.257.10:27:33.93#ibcon#enter sib2, iclass 5, count 0 2006.257.10:27:33.93#ibcon#flushed, iclass 5, count 0 2006.257.10:27:33.93#ibcon#about to write, iclass 5, count 0 2006.257.10:27:33.93#ibcon#wrote, iclass 5, count 0 2006.257.10:27:33.93#ibcon#about to read 3, iclass 5, count 0 2006.257.10:27:33.96#abcon#<5=/14 1.7 4.4 18.93 961013.6\r\n> 2006.257.10:27:33.97#ibcon#read 3, iclass 5, count 0 2006.257.10:27:33.97#ibcon#about to read 4, iclass 5, count 0 2006.257.10:27:33.97#ibcon#read 4, iclass 5, count 0 2006.257.10:27:33.97#ibcon#about to read 5, iclass 5, count 0 2006.257.10:27:33.97#ibcon#read 5, iclass 5, count 0 2006.257.10:27:33.97#ibcon#about to read 6, iclass 5, count 0 2006.257.10:27:33.97#ibcon#read 6, iclass 5, count 0 2006.257.10:27:33.97#ibcon#end of sib2, iclass 5, count 0 2006.257.10:27:33.97#ibcon#*after write, iclass 5, count 0 2006.257.10:27:33.97#ibcon#*before return 0, iclass 5, count 0 2006.257.10:27:33.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:33.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:33.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:27:33.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:27:33.97$vck44/va=6,4 2006.257.10:27:33.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.10:27:33.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.10:27:33.97#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:33.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:27:33.98#abcon#{5=INTERFACE CLEAR} 2006.257.10:27:34.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:27:34.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:27:34.03#ibcon#enter wrdev, iclass 12, count 2 2006.257.10:27:34.03#ibcon#first serial, iclass 12, count 2 2006.257.10:27:34.03#ibcon#enter sib2, iclass 12, count 2 2006.257.10:27:34.03#ibcon#flushed, iclass 12, count 2 2006.257.10:27:34.03#ibcon#about to write, iclass 12, count 2 2006.257.10:27:34.03#ibcon#wrote, iclass 12, count 2 2006.257.10:27:34.03#ibcon#about to read 3, iclass 12, count 2 2006.257.10:27:34.04#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:27:34.05#ibcon#read 3, iclass 12, count 2 2006.257.10:27:34.05#ibcon#about to read 4, iclass 12, count 2 2006.257.10:27:34.05#ibcon#read 4, iclass 12, count 2 2006.257.10:27:34.05#ibcon#about to read 5, iclass 12, count 2 2006.257.10:27:34.05#ibcon#read 5, iclass 12, count 2 2006.257.10:27:34.05#ibcon#about to read 6, iclass 12, count 2 2006.257.10:27:34.05#ibcon#read 6, iclass 12, count 2 2006.257.10:27:34.05#ibcon#end of sib2, iclass 12, count 2 2006.257.10:27:34.05#ibcon#*mode == 0, iclass 12, count 2 2006.257.10:27:34.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.10:27:34.05#ibcon#[25=AT06-04\r\n] 2006.257.10:27:34.05#ibcon#*before write, iclass 12, count 2 2006.257.10:27:34.05#ibcon#enter sib2, iclass 12, count 2 2006.257.10:27:34.05#ibcon#flushed, iclass 12, count 2 2006.257.10:27:34.05#ibcon#about to write, iclass 12, count 2 2006.257.10:27:34.05#ibcon#wrote, iclass 12, count 2 2006.257.10:27:34.05#ibcon#about to read 3, iclass 12, count 2 2006.257.10:27:34.08#ibcon#read 3, iclass 12, count 2 2006.257.10:27:34.08#ibcon#about to read 4, iclass 12, count 2 2006.257.10:27:34.08#ibcon#read 4, iclass 12, count 2 2006.257.10:27:34.08#ibcon#about to read 5, iclass 12, count 2 2006.257.10:27:34.08#ibcon#read 5, iclass 12, count 2 2006.257.10:27:34.08#ibcon#about to read 6, iclass 12, count 2 2006.257.10:27:34.08#ibcon#read 6, iclass 12, count 2 2006.257.10:27:34.08#ibcon#end of sib2, iclass 12, count 2 2006.257.10:27:34.08#ibcon#*after write, iclass 12, count 2 2006.257.10:27:34.08#ibcon#*before return 0, iclass 12, count 2 2006.257.10:27:34.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:27:34.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:27:34.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.10:27:34.08#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:34.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:27:34.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:27:34.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:27:34.20#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:27:34.20#ibcon#first serial, iclass 12, count 0 2006.257.10:27:34.20#ibcon#enter sib2, iclass 12, count 0 2006.257.10:27:34.20#ibcon#flushed, iclass 12, count 0 2006.257.10:27:34.20#ibcon#about to write, iclass 12, count 0 2006.257.10:27:34.20#ibcon#wrote, iclass 12, count 0 2006.257.10:27:34.20#ibcon#about to read 3, iclass 12, count 0 2006.257.10:27:34.22#ibcon#read 3, iclass 12, count 0 2006.257.10:27:34.22#ibcon#about to read 4, iclass 12, count 0 2006.257.10:27:34.22#ibcon#read 4, iclass 12, count 0 2006.257.10:27:34.22#ibcon#about to read 5, iclass 12, count 0 2006.257.10:27:34.22#ibcon#read 5, iclass 12, count 0 2006.257.10:27:34.22#ibcon#about to read 6, iclass 12, count 0 2006.257.10:27:34.22#ibcon#read 6, iclass 12, count 0 2006.257.10:27:34.22#ibcon#end of sib2, iclass 12, count 0 2006.257.10:27:34.22#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:27:34.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:27:34.22#ibcon#[25=USB\r\n] 2006.257.10:27:34.22#ibcon#*before write, iclass 12, count 0 2006.257.10:27:34.22#ibcon#enter sib2, iclass 12, count 0 2006.257.10:27:34.22#ibcon#flushed, iclass 12, count 0 2006.257.10:27:34.22#ibcon#about to write, iclass 12, count 0 2006.257.10:27:34.22#ibcon#wrote, iclass 12, count 0 2006.257.10:27:34.22#ibcon#about to read 3, iclass 12, count 0 2006.257.10:27:34.25#ibcon#read 3, iclass 12, count 0 2006.257.10:27:34.25#ibcon#about to read 4, iclass 12, count 0 2006.257.10:27:34.25#ibcon#read 4, iclass 12, count 0 2006.257.10:27:34.25#ibcon#about to read 5, iclass 12, count 0 2006.257.10:27:34.25#ibcon#read 5, iclass 12, count 0 2006.257.10:27:34.25#ibcon#about to read 6, iclass 12, count 0 2006.257.10:27:34.25#ibcon#read 6, iclass 12, count 0 2006.257.10:27:34.25#ibcon#end of sib2, iclass 12, count 0 2006.257.10:27:34.25#ibcon#*after write, iclass 12, count 0 2006.257.10:27:34.25#ibcon#*before return 0, iclass 12, count 0 2006.257.10:27:34.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:27:34.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:27:34.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:27:34.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:27:34.25$vck44/valo=7,864.99 2006.257.10:27:34.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.10:27:34.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.10:27:34.25#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:34.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:34.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:34.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:34.25#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:27:34.25#ibcon#first serial, iclass 15, count 0 2006.257.10:27:34.25#ibcon#enter sib2, iclass 15, count 0 2006.257.10:27:34.25#ibcon#flushed, iclass 15, count 0 2006.257.10:27:34.25#ibcon#about to write, iclass 15, count 0 2006.257.10:27:34.25#ibcon#wrote, iclass 15, count 0 2006.257.10:27:34.25#ibcon#about to read 3, iclass 15, count 0 2006.257.10:27:34.27#ibcon#read 3, iclass 15, count 0 2006.257.10:27:34.27#ibcon#about to read 4, iclass 15, count 0 2006.257.10:27:34.27#ibcon#read 4, iclass 15, count 0 2006.257.10:27:34.27#ibcon#about to read 5, iclass 15, count 0 2006.257.10:27:34.27#ibcon#read 5, iclass 15, count 0 2006.257.10:27:34.27#ibcon#about to read 6, iclass 15, count 0 2006.257.10:27:34.27#ibcon#read 6, iclass 15, count 0 2006.257.10:27:34.27#ibcon#end of sib2, iclass 15, count 0 2006.257.10:27:34.27#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:27:34.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:27:34.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:27:34.27#ibcon#*before write, iclass 15, count 0 2006.257.10:27:34.27#ibcon#enter sib2, iclass 15, count 0 2006.257.10:27:34.27#ibcon#flushed, iclass 15, count 0 2006.257.10:27:34.27#ibcon#about to write, iclass 15, count 0 2006.257.10:27:34.27#ibcon#wrote, iclass 15, count 0 2006.257.10:27:34.27#ibcon#about to read 3, iclass 15, count 0 2006.257.10:27:34.31#ibcon#read 3, iclass 15, count 0 2006.257.10:27:34.31#ibcon#about to read 4, iclass 15, count 0 2006.257.10:27:34.31#ibcon#read 4, iclass 15, count 0 2006.257.10:27:34.31#ibcon#about to read 5, iclass 15, count 0 2006.257.10:27:34.31#ibcon#read 5, iclass 15, count 0 2006.257.10:27:34.31#ibcon#about to read 6, iclass 15, count 0 2006.257.10:27:34.31#ibcon#read 6, iclass 15, count 0 2006.257.10:27:34.31#ibcon#end of sib2, iclass 15, count 0 2006.257.10:27:34.31#ibcon#*after write, iclass 15, count 0 2006.257.10:27:34.31#ibcon#*before return 0, iclass 15, count 0 2006.257.10:27:34.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:34.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:34.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:27:34.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:27:34.31$vck44/va=7,4 2006.257.10:27:34.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.10:27:34.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.10:27:34.31#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:34.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:34.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:34.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:34.37#ibcon#enter wrdev, iclass 17, count 2 2006.257.10:27:34.37#ibcon#first serial, iclass 17, count 2 2006.257.10:27:34.37#ibcon#enter sib2, iclass 17, count 2 2006.257.10:27:34.37#ibcon#flushed, iclass 17, count 2 2006.257.10:27:34.37#ibcon#about to write, iclass 17, count 2 2006.257.10:27:34.37#ibcon#wrote, iclass 17, count 2 2006.257.10:27:34.37#ibcon#about to read 3, iclass 17, count 2 2006.257.10:27:34.39#ibcon#read 3, iclass 17, count 2 2006.257.10:27:34.39#ibcon#about to read 4, iclass 17, count 2 2006.257.10:27:34.39#ibcon#read 4, iclass 17, count 2 2006.257.10:27:34.39#ibcon#about to read 5, iclass 17, count 2 2006.257.10:27:34.39#ibcon#read 5, iclass 17, count 2 2006.257.10:27:34.39#ibcon#about to read 6, iclass 17, count 2 2006.257.10:27:34.39#ibcon#read 6, iclass 17, count 2 2006.257.10:27:34.39#ibcon#end of sib2, iclass 17, count 2 2006.257.10:27:34.39#ibcon#*mode == 0, iclass 17, count 2 2006.257.10:27:34.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.10:27:34.39#ibcon#[25=AT07-04\r\n] 2006.257.10:27:34.39#ibcon#*before write, iclass 17, count 2 2006.257.10:27:34.39#ibcon#enter sib2, iclass 17, count 2 2006.257.10:27:34.39#ibcon#flushed, iclass 17, count 2 2006.257.10:27:34.39#ibcon#about to write, iclass 17, count 2 2006.257.10:27:34.39#ibcon#wrote, iclass 17, count 2 2006.257.10:27:34.39#ibcon#about to read 3, iclass 17, count 2 2006.257.10:27:34.42#ibcon#read 3, iclass 17, count 2 2006.257.10:27:34.42#ibcon#about to read 4, iclass 17, count 2 2006.257.10:27:34.42#ibcon#read 4, iclass 17, count 2 2006.257.10:27:34.42#ibcon#about to read 5, iclass 17, count 2 2006.257.10:27:34.42#ibcon#read 5, iclass 17, count 2 2006.257.10:27:34.42#ibcon#about to read 6, iclass 17, count 2 2006.257.10:27:34.42#ibcon#read 6, iclass 17, count 2 2006.257.10:27:34.42#ibcon#end of sib2, iclass 17, count 2 2006.257.10:27:34.42#ibcon#*after write, iclass 17, count 2 2006.257.10:27:34.50#ibcon#*before return 0, iclass 17, count 2 2006.257.10:27:34.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:34.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:34.50#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.10:27:34.50#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:34.50#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:34.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:34.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:34.61#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:27:34.61#ibcon#first serial, iclass 17, count 0 2006.257.10:27:34.61#ibcon#enter sib2, iclass 17, count 0 2006.257.10:27:34.61#ibcon#flushed, iclass 17, count 0 2006.257.10:27:34.61#ibcon#about to write, iclass 17, count 0 2006.257.10:27:34.61#ibcon#wrote, iclass 17, count 0 2006.257.10:27:34.61#ibcon#about to read 3, iclass 17, count 0 2006.257.10:27:34.63#ibcon#read 3, iclass 17, count 0 2006.257.10:27:34.63#ibcon#about to read 4, iclass 17, count 0 2006.257.10:27:34.63#ibcon#read 4, iclass 17, count 0 2006.257.10:27:34.63#ibcon#about to read 5, iclass 17, count 0 2006.257.10:27:34.63#ibcon#read 5, iclass 17, count 0 2006.257.10:27:34.63#ibcon#about to read 6, iclass 17, count 0 2006.257.10:27:34.63#ibcon#read 6, iclass 17, count 0 2006.257.10:27:34.63#ibcon#end of sib2, iclass 17, count 0 2006.257.10:27:34.63#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:27:34.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:27:34.63#ibcon#[25=USB\r\n] 2006.257.10:27:34.63#ibcon#*before write, iclass 17, count 0 2006.257.10:27:34.63#ibcon#enter sib2, iclass 17, count 0 2006.257.10:27:34.63#ibcon#flushed, iclass 17, count 0 2006.257.10:27:34.63#ibcon#about to write, iclass 17, count 0 2006.257.10:27:34.63#ibcon#wrote, iclass 17, count 0 2006.257.10:27:34.63#ibcon#about to read 3, iclass 17, count 0 2006.257.10:27:34.66#ibcon#read 3, iclass 17, count 0 2006.257.10:27:34.66#ibcon#about to read 4, iclass 17, count 0 2006.257.10:27:34.66#ibcon#read 4, iclass 17, count 0 2006.257.10:27:34.66#ibcon#about to read 5, iclass 17, count 0 2006.257.10:27:34.66#ibcon#read 5, iclass 17, count 0 2006.257.10:27:34.66#ibcon#about to read 6, iclass 17, count 0 2006.257.10:27:34.66#ibcon#read 6, iclass 17, count 0 2006.257.10:27:34.66#ibcon#end of sib2, iclass 17, count 0 2006.257.10:27:34.66#ibcon#*after write, iclass 17, count 0 2006.257.10:27:34.66#ibcon#*before return 0, iclass 17, count 0 2006.257.10:27:34.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:34.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:34.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:27:34.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:27:34.66$vck44/valo=8,884.99 2006.257.10:27:34.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.10:27:34.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.10:27:34.66#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:34.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:34.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:34.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:34.66#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:27:34.66#ibcon#first serial, iclass 19, count 0 2006.257.10:27:34.66#ibcon#enter sib2, iclass 19, count 0 2006.257.10:27:34.66#ibcon#flushed, iclass 19, count 0 2006.257.10:27:34.66#ibcon#about to write, iclass 19, count 0 2006.257.10:27:34.66#ibcon#wrote, iclass 19, count 0 2006.257.10:27:34.66#ibcon#about to read 3, iclass 19, count 0 2006.257.10:27:34.68#ibcon#read 3, iclass 19, count 0 2006.257.10:27:34.68#ibcon#about to read 4, iclass 19, count 0 2006.257.10:27:34.68#ibcon#read 4, iclass 19, count 0 2006.257.10:27:34.68#ibcon#about to read 5, iclass 19, count 0 2006.257.10:27:34.68#ibcon#read 5, iclass 19, count 0 2006.257.10:27:34.68#ibcon#about to read 6, iclass 19, count 0 2006.257.10:27:34.68#ibcon#read 6, iclass 19, count 0 2006.257.10:27:34.68#ibcon#end of sib2, iclass 19, count 0 2006.257.10:27:34.68#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:27:34.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:27:34.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:27:34.68#ibcon#*before write, iclass 19, count 0 2006.257.10:27:34.68#ibcon#enter sib2, iclass 19, count 0 2006.257.10:27:34.68#ibcon#flushed, iclass 19, count 0 2006.257.10:27:34.68#ibcon#about to write, iclass 19, count 0 2006.257.10:27:34.68#ibcon#wrote, iclass 19, count 0 2006.257.10:27:34.68#ibcon#about to read 3, iclass 19, count 0 2006.257.10:27:34.72#ibcon#read 3, iclass 19, count 0 2006.257.10:27:34.72#ibcon#about to read 4, iclass 19, count 0 2006.257.10:27:34.72#ibcon#read 4, iclass 19, count 0 2006.257.10:27:34.72#ibcon#about to read 5, iclass 19, count 0 2006.257.10:27:34.72#ibcon#read 5, iclass 19, count 0 2006.257.10:27:34.72#ibcon#about to read 6, iclass 19, count 0 2006.257.10:27:34.72#ibcon#read 6, iclass 19, count 0 2006.257.10:27:34.72#ibcon#end of sib2, iclass 19, count 0 2006.257.10:27:34.72#ibcon#*after write, iclass 19, count 0 2006.257.10:27:34.72#ibcon#*before return 0, iclass 19, count 0 2006.257.10:27:34.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:34.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:34.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:27:34.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:27:34.72$vck44/va=8,4 2006.257.10:27:34.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.10:27:34.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.10:27:34.72#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:34.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:27:34.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:27:34.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:27:34.78#ibcon#enter wrdev, iclass 21, count 2 2006.257.10:27:34.78#ibcon#first serial, iclass 21, count 2 2006.257.10:27:34.78#ibcon#enter sib2, iclass 21, count 2 2006.257.10:27:34.78#ibcon#flushed, iclass 21, count 2 2006.257.10:27:34.78#ibcon#about to write, iclass 21, count 2 2006.257.10:27:34.78#ibcon#wrote, iclass 21, count 2 2006.257.10:27:34.78#ibcon#about to read 3, iclass 21, count 2 2006.257.10:27:34.80#ibcon#read 3, iclass 21, count 2 2006.257.10:27:34.80#ibcon#about to read 4, iclass 21, count 2 2006.257.10:27:34.80#ibcon#read 4, iclass 21, count 2 2006.257.10:27:34.80#ibcon#about to read 5, iclass 21, count 2 2006.257.10:27:34.80#ibcon#read 5, iclass 21, count 2 2006.257.10:27:34.80#ibcon#about to read 6, iclass 21, count 2 2006.257.10:27:34.80#ibcon#read 6, iclass 21, count 2 2006.257.10:27:34.80#ibcon#end of sib2, iclass 21, count 2 2006.257.10:27:34.80#ibcon#*mode == 0, iclass 21, count 2 2006.257.10:27:34.80#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.10:27:34.80#ibcon#[25=AT08-04\r\n] 2006.257.10:27:34.80#ibcon#*before write, iclass 21, count 2 2006.257.10:27:34.80#ibcon#enter sib2, iclass 21, count 2 2006.257.10:27:34.80#ibcon#flushed, iclass 21, count 2 2006.257.10:27:34.80#ibcon#about to write, iclass 21, count 2 2006.257.10:27:34.80#ibcon#wrote, iclass 21, count 2 2006.257.10:27:34.80#ibcon#about to read 3, iclass 21, count 2 2006.257.10:27:34.83#ibcon#read 3, iclass 21, count 2 2006.257.10:27:34.83#ibcon#about to read 4, iclass 21, count 2 2006.257.10:27:34.83#ibcon#read 4, iclass 21, count 2 2006.257.10:27:34.83#ibcon#about to read 5, iclass 21, count 2 2006.257.10:27:34.83#ibcon#read 5, iclass 21, count 2 2006.257.10:27:34.83#ibcon#about to read 6, iclass 21, count 2 2006.257.10:27:34.83#ibcon#read 6, iclass 21, count 2 2006.257.10:27:34.83#ibcon#end of sib2, iclass 21, count 2 2006.257.10:27:34.83#ibcon#*after write, iclass 21, count 2 2006.257.10:27:34.83#ibcon#*before return 0, iclass 21, count 2 2006.257.10:27:34.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:27:34.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:27:34.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.10:27:34.83#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:34.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:27:34.95#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:27:34.95#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:27:34.95#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:27:34.95#ibcon#first serial, iclass 21, count 0 2006.257.10:27:34.95#ibcon#enter sib2, iclass 21, count 0 2006.257.10:27:34.95#ibcon#flushed, iclass 21, count 0 2006.257.10:27:34.95#ibcon#about to write, iclass 21, count 0 2006.257.10:27:34.95#ibcon#wrote, iclass 21, count 0 2006.257.10:27:34.95#ibcon#about to read 3, iclass 21, count 0 2006.257.10:27:34.97#ibcon#read 3, iclass 21, count 0 2006.257.10:27:34.97#ibcon#about to read 4, iclass 21, count 0 2006.257.10:27:34.97#ibcon#read 4, iclass 21, count 0 2006.257.10:27:34.97#ibcon#about to read 5, iclass 21, count 0 2006.257.10:27:34.97#ibcon#read 5, iclass 21, count 0 2006.257.10:27:34.97#ibcon#about to read 6, iclass 21, count 0 2006.257.10:27:34.97#ibcon#read 6, iclass 21, count 0 2006.257.10:27:34.97#ibcon#end of sib2, iclass 21, count 0 2006.257.10:27:34.97#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:27:34.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:27:34.97#ibcon#[25=USB\r\n] 2006.257.10:27:34.97#ibcon#*before write, iclass 21, count 0 2006.257.10:27:34.97#ibcon#enter sib2, iclass 21, count 0 2006.257.10:27:34.97#ibcon#flushed, iclass 21, count 0 2006.257.10:27:34.97#ibcon#about to write, iclass 21, count 0 2006.257.10:27:34.97#ibcon#wrote, iclass 21, count 0 2006.257.10:27:34.97#ibcon#about to read 3, iclass 21, count 0 2006.257.10:27:35.00#ibcon#read 3, iclass 21, count 0 2006.257.10:27:35.00#ibcon#about to read 4, iclass 21, count 0 2006.257.10:27:35.00#ibcon#read 4, iclass 21, count 0 2006.257.10:27:35.00#ibcon#about to read 5, iclass 21, count 0 2006.257.10:27:35.00#ibcon#read 5, iclass 21, count 0 2006.257.10:27:35.00#ibcon#about to read 6, iclass 21, count 0 2006.257.10:27:35.00#ibcon#read 6, iclass 21, count 0 2006.257.10:27:35.00#ibcon#end of sib2, iclass 21, count 0 2006.257.10:27:35.00#ibcon#*after write, iclass 21, count 0 2006.257.10:27:35.00#ibcon#*before return 0, iclass 21, count 0 2006.257.10:27:35.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:27:35.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:27:35.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:27:35.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:27:35.00$vck44/vblo=1,629.99 2006.257.10:27:35.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.10:27:35.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.10:27:35.00#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:35.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:35.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:35.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:35.00#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:27:35.00#ibcon#first serial, iclass 23, count 0 2006.257.10:27:35.00#ibcon#enter sib2, iclass 23, count 0 2006.257.10:27:35.00#ibcon#flushed, iclass 23, count 0 2006.257.10:27:35.00#ibcon#about to write, iclass 23, count 0 2006.257.10:27:35.00#ibcon#wrote, iclass 23, count 0 2006.257.10:27:35.00#ibcon#about to read 3, iclass 23, count 0 2006.257.10:27:35.02#ibcon#read 3, iclass 23, count 0 2006.257.10:27:35.02#ibcon#about to read 4, iclass 23, count 0 2006.257.10:27:35.02#ibcon#read 4, iclass 23, count 0 2006.257.10:27:35.02#ibcon#about to read 5, iclass 23, count 0 2006.257.10:27:35.02#ibcon#read 5, iclass 23, count 0 2006.257.10:27:35.02#ibcon#about to read 6, iclass 23, count 0 2006.257.10:27:35.02#ibcon#read 6, iclass 23, count 0 2006.257.10:27:35.02#ibcon#end of sib2, iclass 23, count 0 2006.257.10:27:35.02#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:27:35.02#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:27:35.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:27:35.02#ibcon#*before write, iclass 23, count 0 2006.257.10:27:35.02#ibcon#enter sib2, iclass 23, count 0 2006.257.10:27:35.02#ibcon#flushed, iclass 23, count 0 2006.257.10:27:35.02#ibcon#about to write, iclass 23, count 0 2006.257.10:27:35.02#ibcon#wrote, iclass 23, count 0 2006.257.10:27:35.02#ibcon#about to read 3, iclass 23, count 0 2006.257.10:27:35.06#ibcon#read 3, iclass 23, count 0 2006.257.10:27:35.06#ibcon#about to read 4, iclass 23, count 0 2006.257.10:27:35.06#ibcon#read 4, iclass 23, count 0 2006.257.10:27:35.06#ibcon#about to read 5, iclass 23, count 0 2006.257.10:27:35.06#ibcon#read 5, iclass 23, count 0 2006.257.10:27:35.06#ibcon#about to read 6, iclass 23, count 0 2006.257.10:27:35.06#ibcon#read 6, iclass 23, count 0 2006.257.10:27:35.06#ibcon#end of sib2, iclass 23, count 0 2006.257.10:27:35.06#ibcon#*after write, iclass 23, count 0 2006.257.10:27:35.06#ibcon#*before return 0, iclass 23, count 0 2006.257.10:27:35.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:35.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:27:35.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:27:35.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:27:35.06$vck44/vb=1,4 2006.257.10:27:35.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.10:27:35.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.10:27:35.06#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:35.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:35.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:35.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:35.06#ibcon#enter wrdev, iclass 25, count 2 2006.257.10:27:35.06#ibcon#first serial, iclass 25, count 2 2006.257.10:27:35.06#ibcon#enter sib2, iclass 25, count 2 2006.257.10:27:35.06#ibcon#flushed, iclass 25, count 2 2006.257.10:27:35.06#ibcon#about to write, iclass 25, count 2 2006.257.10:27:35.06#ibcon#wrote, iclass 25, count 2 2006.257.10:27:35.06#ibcon#about to read 3, iclass 25, count 2 2006.257.10:27:35.08#ibcon#read 3, iclass 25, count 2 2006.257.10:27:35.08#ibcon#about to read 4, iclass 25, count 2 2006.257.10:27:35.08#ibcon#read 4, iclass 25, count 2 2006.257.10:27:35.08#ibcon#about to read 5, iclass 25, count 2 2006.257.10:27:35.08#ibcon#read 5, iclass 25, count 2 2006.257.10:27:35.08#ibcon#about to read 6, iclass 25, count 2 2006.257.10:27:35.08#ibcon#read 6, iclass 25, count 2 2006.257.10:27:35.08#ibcon#end of sib2, iclass 25, count 2 2006.257.10:27:35.08#ibcon#*mode == 0, iclass 25, count 2 2006.257.10:27:35.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.10:27:35.08#ibcon#[27=AT01-04\r\n] 2006.257.10:27:35.08#ibcon#*before write, iclass 25, count 2 2006.257.10:27:35.08#ibcon#enter sib2, iclass 25, count 2 2006.257.10:27:35.08#ibcon#flushed, iclass 25, count 2 2006.257.10:27:35.08#ibcon#about to write, iclass 25, count 2 2006.257.10:27:35.08#ibcon#wrote, iclass 25, count 2 2006.257.10:27:35.08#ibcon#about to read 3, iclass 25, count 2 2006.257.10:27:35.11#ibcon#read 3, iclass 25, count 2 2006.257.10:27:35.11#ibcon#about to read 4, iclass 25, count 2 2006.257.10:27:35.11#ibcon#read 4, iclass 25, count 2 2006.257.10:27:35.11#ibcon#about to read 5, iclass 25, count 2 2006.257.10:27:35.11#ibcon#read 5, iclass 25, count 2 2006.257.10:27:35.11#ibcon#about to read 6, iclass 25, count 2 2006.257.10:27:35.11#ibcon#read 6, iclass 25, count 2 2006.257.10:27:35.11#ibcon#end of sib2, iclass 25, count 2 2006.257.10:27:35.11#ibcon#*after write, iclass 25, count 2 2006.257.10:27:35.11#ibcon#*before return 0, iclass 25, count 2 2006.257.10:27:35.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:35.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:27:35.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.10:27:35.11#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:35.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:35.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:35.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:35.23#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:27:35.23#ibcon#first serial, iclass 25, count 0 2006.257.10:27:35.23#ibcon#enter sib2, iclass 25, count 0 2006.257.10:27:35.23#ibcon#flushed, iclass 25, count 0 2006.257.10:27:35.23#ibcon#about to write, iclass 25, count 0 2006.257.10:27:35.23#ibcon#wrote, iclass 25, count 0 2006.257.10:27:35.23#ibcon#about to read 3, iclass 25, count 0 2006.257.10:27:35.25#ibcon#read 3, iclass 25, count 0 2006.257.10:27:35.25#ibcon#about to read 4, iclass 25, count 0 2006.257.10:27:35.25#ibcon#read 4, iclass 25, count 0 2006.257.10:27:35.25#ibcon#about to read 5, iclass 25, count 0 2006.257.10:27:35.25#ibcon#read 5, iclass 25, count 0 2006.257.10:27:35.25#ibcon#about to read 6, iclass 25, count 0 2006.257.10:27:35.25#ibcon#read 6, iclass 25, count 0 2006.257.10:27:35.25#ibcon#end of sib2, iclass 25, count 0 2006.257.10:27:35.25#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:27:35.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:27:35.25#ibcon#[27=USB\r\n] 2006.257.10:27:35.25#ibcon#*before write, iclass 25, count 0 2006.257.10:27:35.25#ibcon#enter sib2, iclass 25, count 0 2006.257.10:27:35.25#ibcon#flushed, iclass 25, count 0 2006.257.10:27:35.25#ibcon#about to write, iclass 25, count 0 2006.257.10:27:35.25#ibcon#wrote, iclass 25, count 0 2006.257.10:27:35.25#ibcon#about to read 3, iclass 25, count 0 2006.257.10:27:35.28#ibcon#read 3, iclass 25, count 0 2006.257.10:27:35.28#ibcon#about to read 4, iclass 25, count 0 2006.257.10:27:35.28#ibcon#read 4, iclass 25, count 0 2006.257.10:27:35.28#ibcon#about to read 5, iclass 25, count 0 2006.257.10:27:35.28#ibcon#read 5, iclass 25, count 0 2006.257.10:27:35.28#ibcon#about to read 6, iclass 25, count 0 2006.257.10:27:35.28#ibcon#read 6, iclass 25, count 0 2006.257.10:27:35.28#ibcon#end of sib2, iclass 25, count 0 2006.257.10:27:35.28#ibcon#*after write, iclass 25, count 0 2006.257.10:27:35.28#ibcon#*before return 0, iclass 25, count 0 2006.257.10:27:35.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:35.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:27:35.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:27:35.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:27:35.28$vck44/vblo=2,634.99 2006.257.10:27:35.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.10:27:35.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.10:27:35.28#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:35.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:35.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:35.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:35.28#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:27:35.28#ibcon#first serial, iclass 27, count 0 2006.257.10:27:35.28#ibcon#enter sib2, iclass 27, count 0 2006.257.10:27:35.28#ibcon#flushed, iclass 27, count 0 2006.257.10:27:35.28#ibcon#about to write, iclass 27, count 0 2006.257.10:27:35.28#ibcon#wrote, iclass 27, count 0 2006.257.10:27:35.28#ibcon#about to read 3, iclass 27, count 0 2006.257.10:27:35.30#ibcon#read 3, iclass 27, count 0 2006.257.10:27:35.30#ibcon#about to read 4, iclass 27, count 0 2006.257.10:27:35.30#ibcon#read 4, iclass 27, count 0 2006.257.10:27:35.30#ibcon#about to read 5, iclass 27, count 0 2006.257.10:27:35.30#ibcon#read 5, iclass 27, count 0 2006.257.10:27:35.30#ibcon#about to read 6, iclass 27, count 0 2006.257.10:27:35.30#ibcon#read 6, iclass 27, count 0 2006.257.10:27:35.30#ibcon#end of sib2, iclass 27, count 0 2006.257.10:27:35.30#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:27:35.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:27:35.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:27:35.30#ibcon#*before write, iclass 27, count 0 2006.257.10:27:35.30#ibcon#enter sib2, iclass 27, count 0 2006.257.10:27:35.30#ibcon#flushed, iclass 27, count 0 2006.257.10:27:35.30#ibcon#about to write, iclass 27, count 0 2006.257.10:27:35.30#ibcon#wrote, iclass 27, count 0 2006.257.10:27:35.30#ibcon#about to read 3, iclass 27, count 0 2006.257.10:27:35.34#ibcon#read 3, iclass 27, count 0 2006.257.10:27:35.34#ibcon#about to read 4, iclass 27, count 0 2006.257.10:27:35.34#ibcon#read 4, iclass 27, count 0 2006.257.10:27:35.34#ibcon#about to read 5, iclass 27, count 0 2006.257.10:27:35.34#ibcon#read 5, iclass 27, count 0 2006.257.10:27:35.34#ibcon#about to read 6, iclass 27, count 0 2006.257.10:27:35.34#ibcon#read 6, iclass 27, count 0 2006.257.10:27:35.34#ibcon#end of sib2, iclass 27, count 0 2006.257.10:27:35.34#ibcon#*after write, iclass 27, count 0 2006.257.10:27:35.34#ibcon#*before return 0, iclass 27, count 0 2006.257.10:27:35.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:35.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:27:35.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:27:35.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:27:35.34$vck44/vb=2,5 2006.257.10:27:35.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.10:27:35.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.10:27:35.34#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:35.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:35.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:35.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:35.40#ibcon#enter wrdev, iclass 29, count 2 2006.257.10:27:35.40#ibcon#first serial, iclass 29, count 2 2006.257.10:27:35.40#ibcon#enter sib2, iclass 29, count 2 2006.257.10:27:35.40#ibcon#flushed, iclass 29, count 2 2006.257.10:27:35.40#ibcon#about to write, iclass 29, count 2 2006.257.10:27:35.40#ibcon#wrote, iclass 29, count 2 2006.257.10:27:35.40#ibcon#about to read 3, iclass 29, count 2 2006.257.10:27:35.42#ibcon#read 3, iclass 29, count 2 2006.257.10:27:35.42#ibcon#about to read 4, iclass 29, count 2 2006.257.10:27:35.42#ibcon#read 4, iclass 29, count 2 2006.257.10:27:35.42#ibcon#about to read 5, iclass 29, count 2 2006.257.10:27:35.42#ibcon#read 5, iclass 29, count 2 2006.257.10:27:35.42#ibcon#about to read 6, iclass 29, count 2 2006.257.10:27:35.42#ibcon#read 6, iclass 29, count 2 2006.257.10:27:35.42#ibcon#end of sib2, iclass 29, count 2 2006.257.10:27:35.42#ibcon#*mode == 0, iclass 29, count 2 2006.257.10:27:35.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.10:27:35.42#ibcon#[27=AT02-05\r\n] 2006.257.10:27:35.42#ibcon#*before write, iclass 29, count 2 2006.257.10:27:35.42#ibcon#enter sib2, iclass 29, count 2 2006.257.10:27:35.42#ibcon#flushed, iclass 29, count 2 2006.257.10:27:35.42#ibcon#about to write, iclass 29, count 2 2006.257.10:27:35.42#ibcon#wrote, iclass 29, count 2 2006.257.10:27:35.42#ibcon#about to read 3, iclass 29, count 2 2006.257.10:27:35.45#ibcon#read 3, iclass 29, count 2 2006.257.10:27:35.54#ibcon#about to read 4, iclass 29, count 2 2006.257.10:27:35.54#ibcon#read 4, iclass 29, count 2 2006.257.10:27:35.54#ibcon#about to read 5, iclass 29, count 2 2006.257.10:27:35.54#ibcon#read 5, iclass 29, count 2 2006.257.10:27:35.54#ibcon#about to read 6, iclass 29, count 2 2006.257.10:27:35.54#ibcon#read 6, iclass 29, count 2 2006.257.10:27:35.54#ibcon#end of sib2, iclass 29, count 2 2006.257.10:27:35.54#ibcon#*after write, iclass 29, count 2 2006.257.10:27:35.54#ibcon#*before return 0, iclass 29, count 2 2006.257.10:27:35.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:35.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:27:35.54#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.10:27:35.54#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:35.54#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:35.66#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:35.66#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:35.66#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:27:35.66#ibcon#first serial, iclass 29, count 0 2006.257.10:27:35.66#ibcon#enter sib2, iclass 29, count 0 2006.257.10:27:35.66#ibcon#flushed, iclass 29, count 0 2006.257.10:27:35.66#ibcon#about to write, iclass 29, count 0 2006.257.10:27:35.66#ibcon#wrote, iclass 29, count 0 2006.257.10:27:35.66#ibcon#about to read 3, iclass 29, count 0 2006.257.10:27:35.68#ibcon#read 3, iclass 29, count 0 2006.257.10:27:35.68#ibcon#about to read 4, iclass 29, count 0 2006.257.10:27:35.68#ibcon#read 4, iclass 29, count 0 2006.257.10:27:35.68#ibcon#about to read 5, iclass 29, count 0 2006.257.10:27:35.68#ibcon#read 5, iclass 29, count 0 2006.257.10:27:35.68#ibcon#about to read 6, iclass 29, count 0 2006.257.10:27:35.68#ibcon#read 6, iclass 29, count 0 2006.257.10:27:35.68#ibcon#end of sib2, iclass 29, count 0 2006.257.10:27:35.68#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:27:35.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:27:35.68#ibcon#[27=USB\r\n] 2006.257.10:27:35.68#ibcon#*before write, iclass 29, count 0 2006.257.10:27:35.68#ibcon#enter sib2, iclass 29, count 0 2006.257.10:27:35.68#ibcon#flushed, iclass 29, count 0 2006.257.10:27:35.68#ibcon#about to write, iclass 29, count 0 2006.257.10:27:35.68#ibcon#wrote, iclass 29, count 0 2006.257.10:27:35.68#ibcon#about to read 3, iclass 29, count 0 2006.257.10:27:35.71#ibcon#read 3, iclass 29, count 0 2006.257.10:27:35.71#ibcon#about to read 4, iclass 29, count 0 2006.257.10:27:35.71#ibcon#read 4, iclass 29, count 0 2006.257.10:27:35.71#ibcon#about to read 5, iclass 29, count 0 2006.257.10:27:35.71#ibcon#read 5, iclass 29, count 0 2006.257.10:27:35.71#ibcon#about to read 6, iclass 29, count 0 2006.257.10:27:35.71#ibcon#read 6, iclass 29, count 0 2006.257.10:27:35.71#ibcon#end of sib2, iclass 29, count 0 2006.257.10:27:35.71#ibcon#*after write, iclass 29, count 0 2006.257.10:27:35.71#ibcon#*before return 0, iclass 29, count 0 2006.257.10:27:35.71#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:35.71#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:27:35.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:27:35.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:27:35.71$vck44/vblo=3,649.99 2006.257.10:27:35.71#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.10:27:35.71#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.10:27:35.71#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:35.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:35.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:35.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:35.71#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:27:35.71#ibcon#first serial, iclass 31, count 0 2006.257.10:27:35.71#ibcon#enter sib2, iclass 31, count 0 2006.257.10:27:35.71#ibcon#flushed, iclass 31, count 0 2006.257.10:27:35.71#ibcon#about to write, iclass 31, count 0 2006.257.10:27:35.71#ibcon#wrote, iclass 31, count 0 2006.257.10:27:35.71#ibcon#about to read 3, iclass 31, count 0 2006.257.10:27:35.73#ibcon#read 3, iclass 31, count 0 2006.257.10:27:35.73#ibcon#about to read 4, iclass 31, count 0 2006.257.10:27:35.73#ibcon#read 4, iclass 31, count 0 2006.257.10:27:35.73#ibcon#about to read 5, iclass 31, count 0 2006.257.10:27:35.73#ibcon#read 5, iclass 31, count 0 2006.257.10:27:35.73#ibcon#about to read 6, iclass 31, count 0 2006.257.10:27:35.73#ibcon#read 6, iclass 31, count 0 2006.257.10:27:35.73#ibcon#end of sib2, iclass 31, count 0 2006.257.10:27:35.73#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:27:35.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:27:35.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:27:35.73#ibcon#*before write, iclass 31, count 0 2006.257.10:27:35.73#ibcon#enter sib2, iclass 31, count 0 2006.257.10:27:35.73#ibcon#flushed, iclass 31, count 0 2006.257.10:27:35.73#ibcon#about to write, iclass 31, count 0 2006.257.10:27:35.73#ibcon#wrote, iclass 31, count 0 2006.257.10:27:35.73#ibcon#about to read 3, iclass 31, count 0 2006.257.10:27:35.77#ibcon#read 3, iclass 31, count 0 2006.257.10:27:35.77#ibcon#about to read 4, iclass 31, count 0 2006.257.10:27:35.77#ibcon#read 4, iclass 31, count 0 2006.257.10:27:35.77#ibcon#about to read 5, iclass 31, count 0 2006.257.10:27:35.77#ibcon#read 5, iclass 31, count 0 2006.257.10:27:35.77#ibcon#about to read 6, iclass 31, count 0 2006.257.10:27:35.77#ibcon#read 6, iclass 31, count 0 2006.257.10:27:35.77#ibcon#end of sib2, iclass 31, count 0 2006.257.10:27:35.77#ibcon#*after write, iclass 31, count 0 2006.257.10:27:35.77#ibcon#*before return 0, iclass 31, count 0 2006.257.10:27:35.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:35.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:27:35.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:27:35.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:27:35.77$vck44/vb=3,4 2006.257.10:27:35.77#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.10:27:35.77#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.10:27:35.77#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:35.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:35.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:35.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:35.83#ibcon#enter wrdev, iclass 33, count 2 2006.257.10:27:35.83#ibcon#first serial, iclass 33, count 2 2006.257.10:27:35.83#ibcon#enter sib2, iclass 33, count 2 2006.257.10:27:35.83#ibcon#flushed, iclass 33, count 2 2006.257.10:27:35.83#ibcon#about to write, iclass 33, count 2 2006.257.10:27:35.83#ibcon#wrote, iclass 33, count 2 2006.257.10:27:35.83#ibcon#about to read 3, iclass 33, count 2 2006.257.10:27:35.85#ibcon#read 3, iclass 33, count 2 2006.257.10:27:35.85#ibcon#about to read 4, iclass 33, count 2 2006.257.10:27:35.85#ibcon#read 4, iclass 33, count 2 2006.257.10:27:35.85#ibcon#about to read 5, iclass 33, count 2 2006.257.10:27:35.85#ibcon#read 5, iclass 33, count 2 2006.257.10:27:35.85#ibcon#about to read 6, iclass 33, count 2 2006.257.10:27:35.85#ibcon#read 6, iclass 33, count 2 2006.257.10:27:35.85#ibcon#end of sib2, iclass 33, count 2 2006.257.10:27:35.85#ibcon#*mode == 0, iclass 33, count 2 2006.257.10:27:35.85#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.10:27:35.85#ibcon#[27=AT03-04\r\n] 2006.257.10:27:35.85#ibcon#*before write, iclass 33, count 2 2006.257.10:27:35.85#ibcon#enter sib2, iclass 33, count 2 2006.257.10:27:35.85#ibcon#flushed, iclass 33, count 2 2006.257.10:27:35.85#ibcon#about to write, iclass 33, count 2 2006.257.10:27:35.85#ibcon#wrote, iclass 33, count 2 2006.257.10:27:35.85#ibcon#about to read 3, iclass 33, count 2 2006.257.10:27:35.88#ibcon#read 3, iclass 33, count 2 2006.257.10:27:35.88#ibcon#about to read 4, iclass 33, count 2 2006.257.10:27:35.88#ibcon#read 4, iclass 33, count 2 2006.257.10:27:35.88#ibcon#about to read 5, iclass 33, count 2 2006.257.10:27:35.88#ibcon#read 5, iclass 33, count 2 2006.257.10:27:35.88#ibcon#about to read 6, iclass 33, count 2 2006.257.10:27:35.88#ibcon#read 6, iclass 33, count 2 2006.257.10:27:35.88#ibcon#end of sib2, iclass 33, count 2 2006.257.10:27:35.88#ibcon#*after write, iclass 33, count 2 2006.257.10:27:35.88#ibcon#*before return 0, iclass 33, count 2 2006.257.10:27:35.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:35.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:27:35.88#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.10:27:35.88#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:35.88#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:36.00#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:36.00#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:36.00#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:27:36.00#ibcon#first serial, iclass 33, count 0 2006.257.10:27:36.00#ibcon#enter sib2, iclass 33, count 0 2006.257.10:27:36.00#ibcon#flushed, iclass 33, count 0 2006.257.10:27:36.00#ibcon#about to write, iclass 33, count 0 2006.257.10:27:36.00#ibcon#wrote, iclass 33, count 0 2006.257.10:27:36.00#ibcon#about to read 3, iclass 33, count 0 2006.257.10:27:36.02#ibcon#read 3, iclass 33, count 0 2006.257.10:27:36.02#ibcon#about to read 4, iclass 33, count 0 2006.257.10:27:36.02#ibcon#read 4, iclass 33, count 0 2006.257.10:27:36.02#ibcon#about to read 5, iclass 33, count 0 2006.257.10:27:36.02#ibcon#read 5, iclass 33, count 0 2006.257.10:27:36.02#ibcon#about to read 6, iclass 33, count 0 2006.257.10:27:36.02#ibcon#read 6, iclass 33, count 0 2006.257.10:27:36.02#ibcon#end of sib2, iclass 33, count 0 2006.257.10:27:36.02#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:27:36.02#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:27:36.02#ibcon#[27=USB\r\n] 2006.257.10:27:36.02#ibcon#*before write, iclass 33, count 0 2006.257.10:27:36.02#ibcon#enter sib2, iclass 33, count 0 2006.257.10:27:36.02#ibcon#flushed, iclass 33, count 0 2006.257.10:27:36.02#ibcon#about to write, iclass 33, count 0 2006.257.10:27:36.02#ibcon#wrote, iclass 33, count 0 2006.257.10:27:36.02#ibcon#about to read 3, iclass 33, count 0 2006.257.10:27:36.05#ibcon#read 3, iclass 33, count 0 2006.257.10:27:36.05#ibcon#about to read 4, iclass 33, count 0 2006.257.10:27:36.05#ibcon#read 4, iclass 33, count 0 2006.257.10:27:36.05#ibcon#about to read 5, iclass 33, count 0 2006.257.10:27:36.05#ibcon#read 5, iclass 33, count 0 2006.257.10:27:36.05#ibcon#about to read 6, iclass 33, count 0 2006.257.10:27:36.05#ibcon#read 6, iclass 33, count 0 2006.257.10:27:36.05#ibcon#end of sib2, iclass 33, count 0 2006.257.10:27:36.05#ibcon#*after write, iclass 33, count 0 2006.257.10:27:36.05#ibcon#*before return 0, iclass 33, count 0 2006.257.10:27:36.05#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:36.05#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:27:36.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:27:36.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:27:36.05$vck44/vblo=4,679.99 2006.257.10:27:36.05#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.10:27:36.05#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.10:27:36.05#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:36.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:36.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:36.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:36.05#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:27:36.05#ibcon#first serial, iclass 35, count 0 2006.257.10:27:36.05#ibcon#enter sib2, iclass 35, count 0 2006.257.10:27:36.05#ibcon#flushed, iclass 35, count 0 2006.257.10:27:36.05#ibcon#about to write, iclass 35, count 0 2006.257.10:27:36.05#ibcon#wrote, iclass 35, count 0 2006.257.10:27:36.05#ibcon#about to read 3, iclass 35, count 0 2006.257.10:27:36.07#ibcon#read 3, iclass 35, count 0 2006.257.10:27:36.07#ibcon#about to read 4, iclass 35, count 0 2006.257.10:27:36.07#ibcon#read 4, iclass 35, count 0 2006.257.10:27:36.07#ibcon#about to read 5, iclass 35, count 0 2006.257.10:27:36.07#ibcon#read 5, iclass 35, count 0 2006.257.10:27:36.07#ibcon#about to read 6, iclass 35, count 0 2006.257.10:27:36.07#ibcon#read 6, iclass 35, count 0 2006.257.10:27:36.07#ibcon#end of sib2, iclass 35, count 0 2006.257.10:27:36.07#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:27:36.07#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:27:36.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:27:36.07#ibcon#*before write, iclass 35, count 0 2006.257.10:27:36.07#ibcon#enter sib2, iclass 35, count 0 2006.257.10:27:36.07#ibcon#flushed, iclass 35, count 0 2006.257.10:27:36.07#ibcon#about to write, iclass 35, count 0 2006.257.10:27:36.07#ibcon#wrote, iclass 35, count 0 2006.257.10:27:36.07#ibcon#about to read 3, iclass 35, count 0 2006.257.10:27:36.11#ibcon#read 3, iclass 35, count 0 2006.257.10:27:36.11#ibcon#about to read 4, iclass 35, count 0 2006.257.10:27:36.11#ibcon#read 4, iclass 35, count 0 2006.257.10:27:36.11#ibcon#about to read 5, iclass 35, count 0 2006.257.10:27:36.11#ibcon#read 5, iclass 35, count 0 2006.257.10:27:36.11#ibcon#about to read 6, iclass 35, count 0 2006.257.10:27:36.11#ibcon#read 6, iclass 35, count 0 2006.257.10:27:36.11#ibcon#end of sib2, iclass 35, count 0 2006.257.10:27:36.11#ibcon#*after write, iclass 35, count 0 2006.257.10:27:36.11#ibcon#*before return 0, iclass 35, count 0 2006.257.10:27:36.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:36.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:27:36.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:27:36.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:27:36.11$vck44/vb=4,5 2006.257.10:27:36.11#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.10:27:36.11#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.10:27:36.11#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:36.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:36.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:36.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:36.17#ibcon#enter wrdev, iclass 37, count 2 2006.257.10:27:36.17#ibcon#first serial, iclass 37, count 2 2006.257.10:27:36.17#ibcon#enter sib2, iclass 37, count 2 2006.257.10:27:36.17#ibcon#flushed, iclass 37, count 2 2006.257.10:27:36.17#ibcon#about to write, iclass 37, count 2 2006.257.10:27:36.17#ibcon#wrote, iclass 37, count 2 2006.257.10:27:36.17#ibcon#about to read 3, iclass 37, count 2 2006.257.10:27:36.19#ibcon#read 3, iclass 37, count 2 2006.257.10:27:36.19#ibcon#about to read 4, iclass 37, count 2 2006.257.10:27:36.19#ibcon#read 4, iclass 37, count 2 2006.257.10:27:36.19#ibcon#about to read 5, iclass 37, count 2 2006.257.10:27:36.19#ibcon#read 5, iclass 37, count 2 2006.257.10:27:36.19#ibcon#about to read 6, iclass 37, count 2 2006.257.10:27:36.19#ibcon#read 6, iclass 37, count 2 2006.257.10:27:36.19#ibcon#end of sib2, iclass 37, count 2 2006.257.10:27:36.19#ibcon#*mode == 0, iclass 37, count 2 2006.257.10:27:36.19#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.10:27:36.19#ibcon#[27=AT04-05\r\n] 2006.257.10:27:36.19#ibcon#*before write, iclass 37, count 2 2006.257.10:27:36.19#ibcon#enter sib2, iclass 37, count 2 2006.257.10:27:36.19#ibcon#flushed, iclass 37, count 2 2006.257.10:27:36.19#ibcon#about to write, iclass 37, count 2 2006.257.10:27:36.19#ibcon#wrote, iclass 37, count 2 2006.257.10:27:36.19#ibcon#about to read 3, iclass 37, count 2 2006.257.10:27:36.22#ibcon#read 3, iclass 37, count 2 2006.257.10:27:36.22#ibcon#about to read 4, iclass 37, count 2 2006.257.10:27:36.22#ibcon#read 4, iclass 37, count 2 2006.257.10:27:36.22#ibcon#about to read 5, iclass 37, count 2 2006.257.10:27:36.22#ibcon#read 5, iclass 37, count 2 2006.257.10:27:36.22#ibcon#about to read 6, iclass 37, count 2 2006.257.10:27:36.22#ibcon#read 6, iclass 37, count 2 2006.257.10:27:36.22#ibcon#end of sib2, iclass 37, count 2 2006.257.10:27:36.22#ibcon#*after write, iclass 37, count 2 2006.257.10:27:36.22#ibcon#*before return 0, iclass 37, count 2 2006.257.10:27:36.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:36.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:27:36.22#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.10:27:36.22#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:36.22#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:36.34#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:36.34#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:36.34#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:27:36.34#ibcon#first serial, iclass 37, count 0 2006.257.10:27:36.34#ibcon#enter sib2, iclass 37, count 0 2006.257.10:27:36.34#ibcon#flushed, iclass 37, count 0 2006.257.10:27:36.34#ibcon#about to write, iclass 37, count 0 2006.257.10:27:36.34#ibcon#wrote, iclass 37, count 0 2006.257.10:27:36.34#ibcon#about to read 3, iclass 37, count 0 2006.257.10:27:36.36#ibcon#read 3, iclass 37, count 0 2006.257.10:27:36.36#ibcon#about to read 4, iclass 37, count 0 2006.257.10:27:36.36#ibcon#read 4, iclass 37, count 0 2006.257.10:27:36.36#ibcon#about to read 5, iclass 37, count 0 2006.257.10:27:36.36#ibcon#read 5, iclass 37, count 0 2006.257.10:27:36.36#ibcon#about to read 6, iclass 37, count 0 2006.257.10:27:36.36#ibcon#read 6, iclass 37, count 0 2006.257.10:27:36.36#ibcon#end of sib2, iclass 37, count 0 2006.257.10:27:36.36#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:27:36.36#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:27:36.36#ibcon#[27=USB\r\n] 2006.257.10:27:36.36#ibcon#*before write, iclass 37, count 0 2006.257.10:27:36.36#ibcon#enter sib2, iclass 37, count 0 2006.257.10:27:36.36#ibcon#flushed, iclass 37, count 0 2006.257.10:27:36.36#ibcon#about to write, iclass 37, count 0 2006.257.10:27:36.36#ibcon#wrote, iclass 37, count 0 2006.257.10:27:36.36#ibcon#about to read 3, iclass 37, count 0 2006.257.10:27:36.39#ibcon#read 3, iclass 37, count 0 2006.257.10:27:36.39#ibcon#about to read 4, iclass 37, count 0 2006.257.10:27:36.39#ibcon#read 4, iclass 37, count 0 2006.257.10:27:36.39#ibcon#about to read 5, iclass 37, count 0 2006.257.10:27:36.39#ibcon#read 5, iclass 37, count 0 2006.257.10:27:36.39#ibcon#about to read 6, iclass 37, count 0 2006.257.10:27:36.39#ibcon#read 6, iclass 37, count 0 2006.257.10:27:36.39#ibcon#end of sib2, iclass 37, count 0 2006.257.10:27:36.39#ibcon#*after write, iclass 37, count 0 2006.257.10:27:36.39#ibcon#*before return 0, iclass 37, count 0 2006.257.10:27:36.39#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:36.39#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:27:36.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:27:36.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:27:36.39$vck44/vblo=5,709.99 2006.257.10:27:36.39#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.10:27:36.39#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.10:27:36.39#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:36.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:36.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:36.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:36.39#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:27:36.39#ibcon#first serial, iclass 39, count 0 2006.257.10:27:36.39#ibcon#enter sib2, iclass 39, count 0 2006.257.10:27:36.39#ibcon#flushed, iclass 39, count 0 2006.257.10:27:36.39#ibcon#about to write, iclass 39, count 0 2006.257.10:27:36.39#ibcon#wrote, iclass 39, count 0 2006.257.10:27:36.39#ibcon#about to read 3, iclass 39, count 0 2006.257.10:27:36.41#ibcon#read 3, iclass 39, count 0 2006.257.10:27:36.41#ibcon#about to read 4, iclass 39, count 0 2006.257.10:27:36.41#ibcon#read 4, iclass 39, count 0 2006.257.10:27:36.41#ibcon#about to read 5, iclass 39, count 0 2006.257.10:27:36.41#ibcon#read 5, iclass 39, count 0 2006.257.10:27:36.41#ibcon#about to read 6, iclass 39, count 0 2006.257.10:27:36.41#ibcon#read 6, iclass 39, count 0 2006.257.10:27:36.41#ibcon#end of sib2, iclass 39, count 0 2006.257.10:27:36.41#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:27:36.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:27:36.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:27:36.41#ibcon#*before write, iclass 39, count 0 2006.257.10:27:36.41#ibcon#enter sib2, iclass 39, count 0 2006.257.10:27:36.41#ibcon#flushed, iclass 39, count 0 2006.257.10:27:36.41#ibcon#about to write, iclass 39, count 0 2006.257.10:27:36.41#ibcon#wrote, iclass 39, count 0 2006.257.10:27:36.41#ibcon#about to read 3, iclass 39, count 0 2006.257.10:27:36.45#ibcon#read 3, iclass 39, count 0 2006.257.10:27:36.45#ibcon#about to read 4, iclass 39, count 0 2006.257.10:27:36.45#ibcon#read 4, iclass 39, count 0 2006.257.10:27:36.45#ibcon#about to read 5, iclass 39, count 0 2006.257.10:27:36.45#ibcon#read 5, iclass 39, count 0 2006.257.10:27:36.45#ibcon#about to read 6, iclass 39, count 0 2006.257.10:27:36.45#ibcon#read 6, iclass 39, count 0 2006.257.10:27:36.45#ibcon#end of sib2, iclass 39, count 0 2006.257.10:27:36.45#ibcon#*after write, iclass 39, count 0 2006.257.10:27:36.45#ibcon#*before return 0, iclass 39, count 0 2006.257.10:27:36.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:36.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:27:36.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:27:36.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:27:36.45$vck44/vb=5,4 2006.257.10:27:36.45#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.10:27:36.45#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.10:27:36.45#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:36.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:36.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:36.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:36.51#ibcon#enter wrdev, iclass 3, count 2 2006.257.10:27:36.51#ibcon#first serial, iclass 3, count 2 2006.257.10:27:36.51#ibcon#enter sib2, iclass 3, count 2 2006.257.10:27:36.51#ibcon#flushed, iclass 3, count 2 2006.257.10:27:36.51#ibcon#about to write, iclass 3, count 2 2006.257.10:27:36.51#ibcon#wrote, iclass 3, count 2 2006.257.10:27:36.51#ibcon#about to read 3, iclass 3, count 2 2006.257.10:27:36.53#ibcon#read 3, iclass 3, count 2 2006.257.10:27:36.53#ibcon#about to read 4, iclass 3, count 2 2006.257.10:27:36.53#ibcon#read 4, iclass 3, count 2 2006.257.10:27:36.53#ibcon#about to read 5, iclass 3, count 2 2006.257.10:27:36.53#ibcon#read 5, iclass 3, count 2 2006.257.10:27:36.53#ibcon#about to read 6, iclass 3, count 2 2006.257.10:27:36.53#ibcon#read 6, iclass 3, count 2 2006.257.10:27:36.53#ibcon#end of sib2, iclass 3, count 2 2006.257.10:27:36.53#ibcon#*mode == 0, iclass 3, count 2 2006.257.10:27:36.53#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.10:27:36.53#ibcon#[27=AT05-04\r\n] 2006.257.10:27:36.53#ibcon#*before write, iclass 3, count 2 2006.257.10:27:36.53#ibcon#enter sib2, iclass 3, count 2 2006.257.10:27:36.53#ibcon#flushed, iclass 3, count 2 2006.257.10:27:36.53#ibcon#about to write, iclass 3, count 2 2006.257.10:27:36.53#ibcon#wrote, iclass 3, count 2 2006.257.10:27:36.53#ibcon#about to read 3, iclass 3, count 2 2006.257.10:27:36.56#ibcon#read 3, iclass 3, count 2 2006.257.10:27:36.57#ibcon#about to read 4, iclass 3, count 2 2006.257.10:27:36.57#ibcon#read 4, iclass 3, count 2 2006.257.10:27:36.57#ibcon#about to read 5, iclass 3, count 2 2006.257.10:27:36.57#ibcon#read 5, iclass 3, count 2 2006.257.10:27:36.57#ibcon#about to read 6, iclass 3, count 2 2006.257.10:27:36.57#ibcon#read 6, iclass 3, count 2 2006.257.10:27:36.57#ibcon#end of sib2, iclass 3, count 2 2006.257.10:27:36.57#ibcon#*after write, iclass 3, count 2 2006.257.10:27:36.57#ibcon#*before return 0, iclass 3, count 2 2006.257.10:27:36.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:36.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:27:36.57#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.10:27:36.57#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:36.57#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:36.69#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:36.69#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:36.69#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:27:36.69#ibcon#first serial, iclass 3, count 0 2006.257.10:27:36.69#ibcon#enter sib2, iclass 3, count 0 2006.257.10:27:36.69#ibcon#flushed, iclass 3, count 0 2006.257.10:27:36.69#ibcon#about to write, iclass 3, count 0 2006.257.10:27:36.69#ibcon#wrote, iclass 3, count 0 2006.257.10:27:36.69#ibcon#about to read 3, iclass 3, count 0 2006.257.10:27:36.71#ibcon#read 3, iclass 3, count 0 2006.257.10:27:36.71#ibcon#about to read 4, iclass 3, count 0 2006.257.10:27:36.71#ibcon#read 4, iclass 3, count 0 2006.257.10:27:36.71#ibcon#about to read 5, iclass 3, count 0 2006.257.10:27:36.71#ibcon#read 5, iclass 3, count 0 2006.257.10:27:36.71#ibcon#about to read 6, iclass 3, count 0 2006.257.10:27:36.71#ibcon#read 6, iclass 3, count 0 2006.257.10:27:36.71#ibcon#end of sib2, iclass 3, count 0 2006.257.10:27:36.71#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:27:36.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:27:36.71#ibcon#[27=USB\r\n] 2006.257.10:27:36.71#ibcon#*before write, iclass 3, count 0 2006.257.10:27:36.71#ibcon#enter sib2, iclass 3, count 0 2006.257.10:27:36.71#ibcon#flushed, iclass 3, count 0 2006.257.10:27:36.71#ibcon#about to write, iclass 3, count 0 2006.257.10:27:36.71#ibcon#wrote, iclass 3, count 0 2006.257.10:27:36.71#ibcon#about to read 3, iclass 3, count 0 2006.257.10:27:36.74#ibcon#read 3, iclass 3, count 0 2006.257.10:27:36.74#ibcon#about to read 4, iclass 3, count 0 2006.257.10:27:36.74#ibcon#read 4, iclass 3, count 0 2006.257.10:27:36.74#ibcon#about to read 5, iclass 3, count 0 2006.257.10:27:36.74#ibcon#read 5, iclass 3, count 0 2006.257.10:27:36.74#ibcon#about to read 6, iclass 3, count 0 2006.257.10:27:36.74#ibcon#read 6, iclass 3, count 0 2006.257.10:27:36.74#ibcon#end of sib2, iclass 3, count 0 2006.257.10:27:36.74#ibcon#*after write, iclass 3, count 0 2006.257.10:27:36.74#ibcon#*before return 0, iclass 3, count 0 2006.257.10:27:36.74#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:36.74#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:27:36.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:27:36.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:27:36.74$vck44/vblo=6,719.99 2006.257.10:27:36.74#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.10:27:36.74#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.10:27:36.74#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:36.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:36.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:36.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:36.74#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:27:36.74#ibcon#first serial, iclass 5, count 0 2006.257.10:27:36.74#ibcon#enter sib2, iclass 5, count 0 2006.257.10:27:36.74#ibcon#flushed, iclass 5, count 0 2006.257.10:27:36.74#ibcon#about to write, iclass 5, count 0 2006.257.10:27:36.74#ibcon#wrote, iclass 5, count 0 2006.257.10:27:36.74#ibcon#about to read 3, iclass 5, count 0 2006.257.10:27:36.76#ibcon#read 3, iclass 5, count 0 2006.257.10:27:36.76#ibcon#about to read 4, iclass 5, count 0 2006.257.10:27:36.76#ibcon#read 4, iclass 5, count 0 2006.257.10:27:36.76#ibcon#about to read 5, iclass 5, count 0 2006.257.10:27:36.76#ibcon#read 5, iclass 5, count 0 2006.257.10:27:36.76#ibcon#about to read 6, iclass 5, count 0 2006.257.10:27:36.76#ibcon#read 6, iclass 5, count 0 2006.257.10:27:36.76#ibcon#end of sib2, iclass 5, count 0 2006.257.10:27:36.76#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:27:36.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:27:36.76#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:27:36.76#ibcon#*before write, iclass 5, count 0 2006.257.10:27:36.76#ibcon#enter sib2, iclass 5, count 0 2006.257.10:27:36.76#ibcon#flushed, iclass 5, count 0 2006.257.10:27:36.76#ibcon#about to write, iclass 5, count 0 2006.257.10:27:36.76#ibcon#wrote, iclass 5, count 0 2006.257.10:27:36.76#ibcon#about to read 3, iclass 5, count 0 2006.257.10:27:36.80#ibcon#read 3, iclass 5, count 0 2006.257.10:27:36.80#ibcon#about to read 4, iclass 5, count 0 2006.257.10:27:36.80#ibcon#read 4, iclass 5, count 0 2006.257.10:27:36.80#ibcon#about to read 5, iclass 5, count 0 2006.257.10:27:36.80#ibcon#read 5, iclass 5, count 0 2006.257.10:27:36.80#ibcon#about to read 6, iclass 5, count 0 2006.257.10:27:36.80#ibcon#read 6, iclass 5, count 0 2006.257.10:27:36.80#ibcon#end of sib2, iclass 5, count 0 2006.257.10:27:36.80#ibcon#*after write, iclass 5, count 0 2006.257.10:27:36.80#ibcon#*before return 0, iclass 5, count 0 2006.257.10:27:36.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:36.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:27:36.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:27:36.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:27:36.80$vck44/vb=6,4 2006.257.10:27:36.80#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.10:27:36.80#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.10:27:36.80#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:36.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:27:36.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:27:36.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:27:36.86#ibcon#enter wrdev, iclass 7, count 2 2006.257.10:27:36.86#ibcon#first serial, iclass 7, count 2 2006.257.10:27:36.86#ibcon#enter sib2, iclass 7, count 2 2006.257.10:27:36.86#ibcon#flushed, iclass 7, count 2 2006.257.10:27:36.86#ibcon#about to write, iclass 7, count 2 2006.257.10:27:36.86#ibcon#wrote, iclass 7, count 2 2006.257.10:27:36.86#ibcon#about to read 3, iclass 7, count 2 2006.257.10:27:36.88#ibcon#read 3, iclass 7, count 2 2006.257.10:27:36.88#ibcon#about to read 4, iclass 7, count 2 2006.257.10:27:36.88#ibcon#read 4, iclass 7, count 2 2006.257.10:27:36.88#ibcon#about to read 5, iclass 7, count 2 2006.257.10:27:36.88#ibcon#read 5, iclass 7, count 2 2006.257.10:27:36.88#ibcon#about to read 6, iclass 7, count 2 2006.257.10:27:36.88#ibcon#read 6, iclass 7, count 2 2006.257.10:27:36.88#ibcon#end of sib2, iclass 7, count 2 2006.257.10:27:36.88#ibcon#*mode == 0, iclass 7, count 2 2006.257.10:27:36.88#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.10:27:36.88#ibcon#[27=AT06-04\r\n] 2006.257.10:27:36.88#ibcon#*before write, iclass 7, count 2 2006.257.10:27:36.88#ibcon#enter sib2, iclass 7, count 2 2006.257.10:27:36.88#ibcon#flushed, iclass 7, count 2 2006.257.10:27:36.88#ibcon#about to write, iclass 7, count 2 2006.257.10:27:36.88#ibcon#wrote, iclass 7, count 2 2006.257.10:27:36.88#ibcon#about to read 3, iclass 7, count 2 2006.257.10:27:36.91#ibcon#read 3, iclass 7, count 2 2006.257.10:27:36.91#ibcon#about to read 4, iclass 7, count 2 2006.257.10:27:36.91#ibcon#read 4, iclass 7, count 2 2006.257.10:27:36.91#ibcon#about to read 5, iclass 7, count 2 2006.257.10:27:36.91#ibcon#read 5, iclass 7, count 2 2006.257.10:27:36.91#ibcon#about to read 6, iclass 7, count 2 2006.257.10:27:36.91#ibcon#read 6, iclass 7, count 2 2006.257.10:27:36.91#ibcon#end of sib2, iclass 7, count 2 2006.257.10:27:36.91#ibcon#*after write, iclass 7, count 2 2006.257.10:27:36.91#ibcon#*before return 0, iclass 7, count 2 2006.257.10:27:36.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:27:36.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:27:36.91#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.10:27:36.91#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:36.91#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:27:37.03#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:27:37.03#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:27:37.03#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:27:37.03#ibcon#first serial, iclass 7, count 0 2006.257.10:27:37.03#ibcon#enter sib2, iclass 7, count 0 2006.257.10:27:37.03#ibcon#flushed, iclass 7, count 0 2006.257.10:27:37.03#ibcon#about to write, iclass 7, count 0 2006.257.10:27:37.03#ibcon#wrote, iclass 7, count 0 2006.257.10:27:37.03#ibcon#about to read 3, iclass 7, count 0 2006.257.10:27:37.05#ibcon#read 3, iclass 7, count 0 2006.257.10:27:37.05#ibcon#about to read 4, iclass 7, count 0 2006.257.10:27:37.05#ibcon#read 4, iclass 7, count 0 2006.257.10:27:37.05#ibcon#about to read 5, iclass 7, count 0 2006.257.10:27:37.05#ibcon#read 5, iclass 7, count 0 2006.257.10:27:37.05#ibcon#about to read 6, iclass 7, count 0 2006.257.10:27:37.05#ibcon#read 6, iclass 7, count 0 2006.257.10:27:37.05#ibcon#end of sib2, iclass 7, count 0 2006.257.10:27:37.05#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:27:37.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:27:37.05#ibcon#[27=USB\r\n] 2006.257.10:27:37.05#ibcon#*before write, iclass 7, count 0 2006.257.10:27:37.05#ibcon#enter sib2, iclass 7, count 0 2006.257.10:27:37.05#ibcon#flushed, iclass 7, count 0 2006.257.10:27:37.05#ibcon#about to write, iclass 7, count 0 2006.257.10:27:37.05#ibcon#wrote, iclass 7, count 0 2006.257.10:27:37.05#ibcon#about to read 3, iclass 7, count 0 2006.257.10:27:37.08#ibcon#read 3, iclass 7, count 0 2006.257.10:27:37.08#ibcon#about to read 4, iclass 7, count 0 2006.257.10:27:37.08#ibcon#read 4, iclass 7, count 0 2006.257.10:27:37.08#ibcon#about to read 5, iclass 7, count 0 2006.257.10:27:37.08#ibcon#read 5, iclass 7, count 0 2006.257.10:27:37.08#ibcon#about to read 6, iclass 7, count 0 2006.257.10:27:37.08#ibcon#read 6, iclass 7, count 0 2006.257.10:27:37.08#ibcon#end of sib2, iclass 7, count 0 2006.257.10:27:37.08#ibcon#*after write, iclass 7, count 0 2006.257.10:27:37.08#ibcon#*before return 0, iclass 7, count 0 2006.257.10:27:37.08#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:27:37.08#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:27:37.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:27:37.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:27:37.08$vck44/vblo=7,734.99 2006.257.10:27:37.08#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.10:27:37.08#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.10:27:37.08#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:37.08#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:27:37.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:27:37.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:27:37.08#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:27:37.08#ibcon#first serial, iclass 11, count 0 2006.257.10:27:37.08#ibcon#enter sib2, iclass 11, count 0 2006.257.10:27:37.08#ibcon#flushed, iclass 11, count 0 2006.257.10:27:37.08#ibcon#about to write, iclass 11, count 0 2006.257.10:27:37.08#ibcon#wrote, iclass 11, count 0 2006.257.10:27:37.08#ibcon#about to read 3, iclass 11, count 0 2006.257.10:27:37.10#ibcon#read 3, iclass 11, count 0 2006.257.10:27:37.10#ibcon#about to read 4, iclass 11, count 0 2006.257.10:27:37.10#ibcon#read 4, iclass 11, count 0 2006.257.10:27:37.10#ibcon#about to read 5, iclass 11, count 0 2006.257.10:27:37.10#ibcon#read 5, iclass 11, count 0 2006.257.10:27:37.10#ibcon#about to read 6, iclass 11, count 0 2006.257.10:27:37.10#ibcon#read 6, iclass 11, count 0 2006.257.10:27:37.10#ibcon#end of sib2, iclass 11, count 0 2006.257.10:27:37.10#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:27:37.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:27:37.10#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:27:37.10#ibcon#*before write, iclass 11, count 0 2006.257.10:27:37.10#ibcon#enter sib2, iclass 11, count 0 2006.257.10:27:37.10#ibcon#flushed, iclass 11, count 0 2006.257.10:27:37.10#ibcon#about to write, iclass 11, count 0 2006.257.10:27:37.10#ibcon#wrote, iclass 11, count 0 2006.257.10:27:37.10#ibcon#about to read 3, iclass 11, count 0 2006.257.10:27:37.14#ibcon#read 3, iclass 11, count 0 2006.257.10:27:37.14#ibcon#about to read 4, iclass 11, count 0 2006.257.10:27:37.14#ibcon#read 4, iclass 11, count 0 2006.257.10:27:37.14#ibcon#about to read 5, iclass 11, count 0 2006.257.10:27:37.14#ibcon#read 5, iclass 11, count 0 2006.257.10:27:37.14#ibcon#about to read 6, iclass 11, count 0 2006.257.10:27:37.14#ibcon#read 6, iclass 11, count 0 2006.257.10:27:37.14#ibcon#end of sib2, iclass 11, count 0 2006.257.10:27:37.14#ibcon#*after write, iclass 11, count 0 2006.257.10:27:37.14#ibcon#*before return 0, iclass 11, count 0 2006.257.10:27:37.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:27:37.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:27:37.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:27:37.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:27:37.14$vck44/vb=7,4 2006.257.10:27:37.14#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.10:27:37.14#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.10:27:37.14#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:37.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:27:37.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:27:37.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:27:37.20#ibcon#enter wrdev, iclass 13, count 2 2006.257.10:27:37.20#ibcon#first serial, iclass 13, count 2 2006.257.10:27:37.20#ibcon#enter sib2, iclass 13, count 2 2006.257.10:27:37.20#ibcon#flushed, iclass 13, count 2 2006.257.10:27:37.20#ibcon#about to write, iclass 13, count 2 2006.257.10:27:37.20#ibcon#wrote, iclass 13, count 2 2006.257.10:27:37.20#ibcon#about to read 3, iclass 13, count 2 2006.257.10:27:37.22#ibcon#read 3, iclass 13, count 2 2006.257.10:27:37.22#ibcon#about to read 4, iclass 13, count 2 2006.257.10:27:37.22#ibcon#read 4, iclass 13, count 2 2006.257.10:27:37.22#ibcon#about to read 5, iclass 13, count 2 2006.257.10:27:37.22#ibcon#read 5, iclass 13, count 2 2006.257.10:27:37.22#ibcon#about to read 6, iclass 13, count 2 2006.257.10:27:37.22#ibcon#read 6, iclass 13, count 2 2006.257.10:27:37.22#ibcon#end of sib2, iclass 13, count 2 2006.257.10:27:37.22#ibcon#*mode == 0, iclass 13, count 2 2006.257.10:27:37.22#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.10:27:37.22#ibcon#[27=AT07-04\r\n] 2006.257.10:27:37.22#ibcon#*before write, iclass 13, count 2 2006.257.10:27:37.22#ibcon#enter sib2, iclass 13, count 2 2006.257.10:27:37.22#ibcon#flushed, iclass 13, count 2 2006.257.10:27:37.22#ibcon#about to write, iclass 13, count 2 2006.257.10:27:37.22#ibcon#wrote, iclass 13, count 2 2006.257.10:27:37.22#ibcon#about to read 3, iclass 13, count 2 2006.257.10:27:37.25#ibcon#read 3, iclass 13, count 2 2006.257.10:27:37.25#ibcon#about to read 4, iclass 13, count 2 2006.257.10:27:37.25#ibcon#read 4, iclass 13, count 2 2006.257.10:27:37.25#ibcon#about to read 5, iclass 13, count 2 2006.257.10:27:37.25#ibcon#read 5, iclass 13, count 2 2006.257.10:27:37.25#ibcon#about to read 6, iclass 13, count 2 2006.257.10:27:37.25#ibcon#read 6, iclass 13, count 2 2006.257.10:27:37.25#ibcon#end of sib2, iclass 13, count 2 2006.257.10:27:37.25#ibcon#*after write, iclass 13, count 2 2006.257.10:27:37.25#ibcon#*before return 0, iclass 13, count 2 2006.257.10:27:37.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:27:37.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:27:37.25#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.10:27:37.25#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:37.25#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:27:37.37#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:27:37.37#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:27:37.37#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:27:37.37#ibcon#first serial, iclass 13, count 0 2006.257.10:27:37.37#ibcon#enter sib2, iclass 13, count 0 2006.257.10:27:37.37#ibcon#flushed, iclass 13, count 0 2006.257.10:27:37.37#ibcon#about to write, iclass 13, count 0 2006.257.10:27:37.37#ibcon#wrote, iclass 13, count 0 2006.257.10:27:37.37#ibcon#about to read 3, iclass 13, count 0 2006.257.10:27:37.39#ibcon#read 3, iclass 13, count 0 2006.257.10:27:37.39#ibcon#about to read 4, iclass 13, count 0 2006.257.10:27:37.39#ibcon#read 4, iclass 13, count 0 2006.257.10:27:37.39#ibcon#about to read 5, iclass 13, count 0 2006.257.10:27:37.39#ibcon#read 5, iclass 13, count 0 2006.257.10:27:37.39#ibcon#about to read 6, iclass 13, count 0 2006.257.10:27:37.39#ibcon#read 6, iclass 13, count 0 2006.257.10:27:37.39#ibcon#end of sib2, iclass 13, count 0 2006.257.10:27:37.39#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:27:37.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:27:37.39#ibcon#[27=USB\r\n] 2006.257.10:27:37.39#ibcon#*before write, iclass 13, count 0 2006.257.10:27:37.39#ibcon#enter sib2, iclass 13, count 0 2006.257.10:27:37.39#ibcon#flushed, iclass 13, count 0 2006.257.10:27:37.39#ibcon#about to write, iclass 13, count 0 2006.257.10:27:37.39#ibcon#wrote, iclass 13, count 0 2006.257.10:27:37.39#ibcon#about to read 3, iclass 13, count 0 2006.257.10:27:37.42#ibcon#read 3, iclass 13, count 0 2006.257.10:27:37.42#ibcon#about to read 4, iclass 13, count 0 2006.257.10:27:37.42#ibcon#read 4, iclass 13, count 0 2006.257.10:27:37.42#ibcon#about to read 5, iclass 13, count 0 2006.257.10:27:37.42#ibcon#read 5, iclass 13, count 0 2006.257.10:27:37.42#ibcon#about to read 6, iclass 13, count 0 2006.257.10:27:37.42#ibcon#read 6, iclass 13, count 0 2006.257.10:27:37.42#ibcon#end of sib2, iclass 13, count 0 2006.257.10:27:37.42#ibcon#*after write, iclass 13, count 0 2006.257.10:27:37.42#ibcon#*before return 0, iclass 13, count 0 2006.257.10:27:37.42#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:27:37.42#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:27:37.42#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:27:37.42#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:27:37.42$vck44/vblo=8,744.99 2006.257.10:27:37.42#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.10:27:37.42#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.10:27:37.42#ibcon#ireg 17 cls_cnt 0 2006.257.10:27:37.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:37.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:37.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:37.42#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:27:37.42#ibcon#first serial, iclass 15, count 0 2006.257.10:27:37.42#ibcon#enter sib2, iclass 15, count 0 2006.257.10:27:37.42#ibcon#flushed, iclass 15, count 0 2006.257.10:27:37.42#ibcon#about to write, iclass 15, count 0 2006.257.10:27:37.42#ibcon#wrote, iclass 15, count 0 2006.257.10:27:37.42#ibcon#about to read 3, iclass 15, count 0 2006.257.10:27:37.44#ibcon#read 3, iclass 15, count 0 2006.257.10:27:37.44#ibcon#about to read 4, iclass 15, count 0 2006.257.10:27:37.44#ibcon#read 4, iclass 15, count 0 2006.257.10:27:37.44#ibcon#about to read 5, iclass 15, count 0 2006.257.10:27:37.44#ibcon#read 5, iclass 15, count 0 2006.257.10:27:37.44#ibcon#about to read 6, iclass 15, count 0 2006.257.10:27:37.44#ibcon#read 6, iclass 15, count 0 2006.257.10:27:37.44#ibcon#end of sib2, iclass 15, count 0 2006.257.10:27:37.44#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:27:37.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:27:37.44#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:27:37.44#ibcon#*before write, iclass 15, count 0 2006.257.10:27:37.44#ibcon#enter sib2, iclass 15, count 0 2006.257.10:27:37.44#ibcon#flushed, iclass 15, count 0 2006.257.10:27:37.44#ibcon#about to write, iclass 15, count 0 2006.257.10:27:37.44#ibcon#wrote, iclass 15, count 0 2006.257.10:27:37.44#ibcon#about to read 3, iclass 15, count 0 2006.257.10:27:37.48#ibcon#read 3, iclass 15, count 0 2006.257.10:27:37.48#ibcon#about to read 4, iclass 15, count 0 2006.257.10:27:37.48#ibcon#read 4, iclass 15, count 0 2006.257.10:27:37.48#ibcon#about to read 5, iclass 15, count 0 2006.257.10:27:37.48#ibcon#read 5, iclass 15, count 0 2006.257.10:27:37.48#ibcon#about to read 6, iclass 15, count 0 2006.257.10:27:37.48#ibcon#read 6, iclass 15, count 0 2006.257.10:27:37.48#ibcon#end of sib2, iclass 15, count 0 2006.257.10:27:37.48#ibcon#*after write, iclass 15, count 0 2006.257.10:27:37.48#ibcon#*before return 0, iclass 15, count 0 2006.257.10:27:37.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:37.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:27:37.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:27:37.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:27:37.48$vck44/vb=8,4 2006.257.10:27:37.48#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.10:27:37.48#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.10:27:37.48#ibcon#ireg 11 cls_cnt 2 2006.257.10:27:37.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:37.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:37.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:37.54#ibcon#enter wrdev, iclass 17, count 2 2006.257.10:27:37.54#ibcon#first serial, iclass 17, count 2 2006.257.10:27:37.54#ibcon#enter sib2, iclass 17, count 2 2006.257.10:27:37.54#ibcon#flushed, iclass 17, count 2 2006.257.10:27:37.54#ibcon#about to write, iclass 17, count 2 2006.257.10:27:37.54#ibcon#wrote, iclass 17, count 2 2006.257.10:27:37.54#ibcon#about to read 3, iclass 17, count 2 2006.257.10:27:37.56#ibcon#read 3, iclass 17, count 2 2006.257.10:27:37.56#ibcon#about to read 4, iclass 17, count 2 2006.257.10:27:37.56#ibcon#read 4, iclass 17, count 2 2006.257.10:27:37.56#ibcon#about to read 5, iclass 17, count 2 2006.257.10:27:37.56#ibcon#read 5, iclass 17, count 2 2006.257.10:27:37.56#ibcon#about to read 6, iclass 17, count 2 2006.257.10:27:37.56#ibcon#read 6, iclass 17, count 2 2006.257.10:27:37.56#ibcon#end of sib2, iclass 17, count 2 2006.257.10:27:37.56#ibcon#*mode == 0, iclass 17, count 2 2006.257.10:27:37.56#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.10:27:37.56#ibcon#[27=AT08-04\r\n] 2006.257.10:27:37.56#ibcon#*before write, iclass 17, count 2 2006.257.10:27:37.56#ibcon#enter sib2, iclass 17, count 2 2006.257.10:27:37.56#ibcon#flushed, iclass 17, count 2 2006.257.10:27:37.56#ibcon#about to write, iclass 17, count 2 2006.257.10:27:37.56#ibcon#wrote, iclass 17, count 2 2006.257.10:27:37.56#ibcon#about to read 3, iclass 17, count 2 2006.257.10:27:37.59#ibcon#read 3, iclass 17, count 2 2006.257.10:27:37.59#ibcon#about to read 4, iclass 17, count 2 2006.257.10:27:37.59#ibcon#read 4, iclass 17, count 2 2006.257.10:27:37.62#ibcon#about to read 5, iclass 17, count 2 2006.257.10:27:37.62#ibcon#read 5, iclass 17, count 2 2006.257.10:27:37.62#ibcon#about to read 6, iclass 17, count 2 2006.257.10:27:37.62#ibcon#read 6, iclass 17, count 2 2006.257.10:27:37.62#ibcon#end of sib2, iclass 17, count 2 2006.257.10:27:37.62#ibcon#*after write, iclass 17, count 2 2006.257.10:27:37.62#ibcon#*before return 0, iclass 17, count 2 2006.257.10:27:37.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:37.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:27:37.62#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.10:27:37.62#ibcon#ireg 7 cls_cnt 0 2006.257.10:27:37.62#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:37.73#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:37.73#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:37.73#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:27:37.73#ibcon#first serial, iclass 17, count 0 2006.257.10:27:37.73#ibcon#enter sib2, iclass 17, count 0 2006.257.10:27:37.73#ibcon#flushed, iclass 17, count 0 2006.257.10:27:37.73#ibcon#about to write, iclass 17, count 0 2006.257.10:27:37.73#ibcon#wrote, iclass 17, count 0 2006.257.10:27:37.73#ibcon#about to read 3, iclass 17, count 0 2006.257.10:27:37.75#ibcon#read 3, iclass 17, count 0 2006.257.10:27:37.75#ibcon#about to read 4, iclass 17, count 0 2006.257.10:27:37.75#ibcon#read 4, iclass 17, count 0 2006.257.10:27:37.75#ibcon#about to read 5, iclass 17, count 0 2006.257.10:27:37.75#ibcon#read 5, iclass 17, count 0 2006.257.10:27:37.75#ibcon#about to read 6, iclass 17, count 0 2006.257.10:27:37.75#ibcon#read 6, iclass 17, count 0 2006.257.10:27:37.75#ibcon#end of sib2, iclass 17, count 0 2006.257.10:27:37.75#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:27:37.75#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:27:37.75#ibcon#[27=USB\r\n] 2006.257.10:27:37.75#ibcon#*before write, iclass 17, count 0 2006.257.10:27:37.75#ibcon#enter sib2, iclass 17, count 0 2006.257.10:27:37.75#ibcon#flushed, iclass 17, count 0 2006.257.10:27:37.75#ibcon#about to write, iclass 17, count 0 2006.257.10:27:37.75#ibcon#wrote, iclass 17, count 0 2006.257.10:27:37.75#ibcon#about to read 3, iclass 17, count 0 2006.257.10:27:37.78#ibcon#read 3, iclass 17, count 0 2006.257.10:27:37.78#ibcon#about to read 4, iclass 17, count 0 2006.257.10:27:37.78#ibcon#read 4, iclass 17, count 0 2006.257.10:27:37.78#ibcon#about to read 5, iclass 17, count 0 2006.257.10:27:37.78#ibcon#read 5, iclass 17, count 0 2006.257.10:27:37.78#ibcon#about to read 6, iclass 17, count 0 2006.257.10:27:37.78#ibcon#read 6, iclass 17, count 0 2006.257.10:27:37.78#ibcon#end of sib2, iclass 17, count 0 2006.257.10:27:37.78#ibcon#*after write, iclass 17, count 0 2006.257.10:27:37.78#ibcon#*before return 0, iclass 17, count 0 2006.257.10:27:37.78#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:37.78#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:27:37.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:27:37.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:27:37.78$vck44/vabw=wide 2006.257.10:27:37.78#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.10:27:37.78#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.10:27:37.78#ibcon#ireg 8 cls_cnt 0 2006.257.10:27:37.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:37.78#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:37.78#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:37.78#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:27:37.78#ibcon#first serial, iclass 19, count 0 2006.257.10:27:37.78#ibcon#enter sib2, iclass 19, count 0 2006.257.10:27:37.78#ibcon#flushed, iclass 19, count 0 2006.257.10:27:37.78#ibcon#about to write, iclass 19, count 0 2006.257.10:27:37.78#ibcon#wrote, iclass 19, count 0 2006.257.10:27:37.78#ibcon#about to read 3, iclass 19, count 0 2006.257.10:27:37.80#ibcon#read 3, iclass 19, count 0 2006.257.10:27:37.80#ibcon#about to read 4, iclass 19, count 0 2006.257.10:27:37.80#ibcon#read 4, iclass 19, count 0 2006.257.10:27:37.80#ibcon#about to read 5, iclass 19, count 0 2006.257.10:27:37.80#ibcon#read 5, iclass 19, count 0 2006.257.10:27:37.80#ibcon#about to read 6, iclass 19, count 0 2006.257.10:27:37.80#ibcon#read 6, iclass 19, count 0 2006.257.10:27:37.80#ibcon#end of sib2, iclass 19, count 0 2006.257.10:27:37.80#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:27:37.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:27:37.80#ibcon#[25=BW32\r\n] 2006.257.10:27:37.80#ibcon#*before write, iclass 19, count 0 2006.257.10:27:37.80#ibcon#enter sib2, iclass 19, count 0 2006.257.10:27:37.80#ibcon#flushed, iclass 19, count 0 2006.257.10:27:37.80#ibcon#about to write, iclass 19, count 0 2006.257.10:27:37.80#ibcon#wrote, iclass 19, count 0 2006.257.10:27:37.80#ibcon#about to read 3, iclass 19, count 0 2006.257.10:27:37.83#ibcon#read 3, iclass 19, count 0 2006.257.10:27:37.83#ibcon#about to read 4, iclass 19, count 0 2006.257.10:27:37.83#ibcon#read 4, iclass 19, count 0 2006.257.10:27:37.83#ibcon#about to read 5, iclass 19, count 0 2006.257.10:27:37.83#ibcon#read 5, iclass 19, count 0 2006.257.10:27:37.83#ibcon#about to read 6, iclass 19, count 0 2006.257.10:27:37.83#ibcon#read 6, iclass 19, count 0 2006.257.10:27:37.83#ibcon#end of sib2, iclass 19, count 0 2006.257.10:27:37.83#ibcon#*after write, iclass 19, count 0 2006.257.10:27:37.83#ibcon#*before return 0, iclass 19, count 0 2006.257.10:27:37.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:37.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:27:37.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:27:37.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:27:37.83$vck44/vbbw=wide 2006.257.10:27:37.83#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.10:27:37.83#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.10:27:37.83#ibcon#ireg 8 cls_cnt 0 2006.257.10:27:37.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:27:37.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:27:37.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:27:37.90#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:27:37.90#ibcon#first serial, iclass 21, count 0 2006.257.10:27:37.90#ibcon#enter sib2, iclass 21, count 0 2006.257.10:27:37.90#ibcon#flushed, iclass 21, count 0 2006.257.10:27:37.90#ibcon#about to write, iclass 21, count 0 2006.257.10:27:37.90#ibcon#wrote, iclass 21, count 0 2006.257.10:27:37.90#ibcon#about to read 3, iclass 21, count 0 2006.257.10:27:37.92#ibcon#read 3, iclass 21, count 0 2006.257.10:27:37.92#ibcon#about to read 4, iclass 21, count 0 2006.257.10:27:37.92#ibcon#read 4, iclass 21, count 0 2006.257.10:27:37.92#ibcon#about to read 5, iclass 21, count 0 2006.257.10:27:37.92#ibcon#read 5, iclass 21, count 0 2006.257.10:27:37.92#ibcon#about to read 6, iclass 21, count 0 2006.257.10:27:37.92#ibcon#read 6, iclass 21, count 0 2006.257.10:27:37.92#ibcon#end of sib2, iclass 21, count 0 2006.257.10:27:37.92#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:27:37.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:27:37.92#ibcon#[27=BW32\r\n] 2006.257.10:27:37.92#ibcon#*before write, iclass 21, count 0 2006.257.10:27:37.92#ibcon#enter sib2, iclass 21, count 0 2006.257.10:27:37.92#ibcon#flushed, iclass 21, count 0 2006.257.10:27:37.92#ibcon#about to write, iclass 21, count 0 2006.257.10:27:37.92#ibcon#wrote, iclass 21, count 0 2006.257.10:27:37.92#ibcon#about to read 3, iclass 21, count 0 2006.257.10:27:37.95#ibcon#read 3, iclass 21, count 0 2006.257.10:27:37.95#ibcon#about to read 4, iclass 21, count 0 2006.257.10:27:37.95#ibcon#read 4, iclass 21, count 0 2006.257.10:27:37.95#ibcon#about to read 5, iclass 21, count 0 2006.257.10:27:37.95#ibcon#read 5, iclass 21, count 0 2006.257.10:27:37.95#ibcon#about to read 6, iclass 21, count 0 2006.257.10:27:37.95#ibcon#read 6, iclass 21, count 0 2006.257.10:27:37.95#ibcon#end of sib2, iclass 21, count 0 2006.257.10:27:37.95#ibcon#*after write, iclass 21, count 0 2006.257.10:27:37.95#ibcon#*before return 0, iclass 21, count 0 2006.257.10:27:37.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:27:37.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:27:37.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:27:37.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:27:37.95$setupk4/ifdk4 2006.257.10:27:37.95$ifdk4/lo= 2006.257.10:27:37.95$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:27:37.95$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:27:37.95$ifdk4/patch= 2006.257.10:27:37.95$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:27:37.95$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:27:37.95$setupk4/!*+20s 2006.257.10:27:44.13#abcon#<5=/14 1.7 4.4 18.93 961013.6\r\n> 2006.257.10:27:44.15#abcon#{5=INTERFACE CLEAR} 2006.257.10:27:44.21#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:27:48.14#trakl#Source acquired 2006.257.10:27:48.14#flagr#flagr/antenna,acquired 2006.257.10:27:52.27$setupk4/"tpicd 2006.257.10:27:52.27$setupk4/echo=off 2006.257.10:27:52.27$setupk4/xlog=off 2006.257.10:27:52.27:!2006.257.10:29:29 2006.257.10:29:29.00:preob 2006.257.10:29:29.14/onsource/TRACKING 2006.257.10:29:29.14:!2006.257.10:29:39 2006.257.10:29:39.00:"tape 2006.257.10:29:39.00:"st=record 2006.257.10:29:39.00:data_valid=on 2006.257.10:29:39.00:midob 2006.257.10:29:39.14/onsource/TRACKING 2006.257.10:29:39.14/wx/18.91,1013.8,96 2006.257.10:29:39.36/cable/+6.4769E-03 2006.257.10:29:40.45/va/01,08,usb,yes,30,33 2006.257.10:29:40.45/va/02,07,usb,yes,33,33 2006.257.10:29:40.45/va/03,08,usb,yes,29,31 2006.257.10:29:40.45/va/04,07,usb,yes,34,35 2006.257.10:29:40.45/va/05,04,usb,yes,30,31 2006.257.10:29:40.45/va/06,04,usb,yes,34,33 2006.257.10:29:40.45/va/07,04,usb,yes,35,35 2006.257.10:29:40.45/va/08,04,usb,yes,29,35 2006.257.10:29:40.68/valo/01,524.99,yes,locked 2006.257.10:29:40.68/valo/02,534.99,yes,locked 2006.257.10:29:40.68/valo/03,564.99,yes,locked 2006.257.10:29:40.68/valo/04,624.99,yes,locked 2006.257.10:29:40.68/valo/05,734.99,yes,locked 2006.257.10:29:40.68/valo/06,814.99,yes,locked 2006.257.10:29:40.68/valo/07,864.99,yes,locked 2006.257.10:29:40.68/valo/08,884.99,yes,locked 2006.257.10:29:41.77/vb/01,04,usb,yes,30,28 2006.257.10:29:41.77/vb/02,05,usb,yes,28,28 2006.257.10:29:41.77/vb/03,04,usb,yes,29,32 2006.257.10:29:41.77/vb/04,05,usb,yes,30,29 2006.257.10:29:41.77/vb/05,04,usb,yes,26,29 2006.257.10:29:41.77/vb/06,04,usb,yes,31,27 2006.257.10:29:41.77/vb/07,04,usb,yes,30,30 2006.257.10:29:41.77/vb/08,04,usb,yes,28,31 2006.257.10:29:42.01/vblo/01,629.99,yes,locked 2006.257.10:29:42.01/vblo/02,634.99,yes,locked 2006.257.10:29:42.01/vblo/03,649.99,yes,locked 2006.257.10:29:42.01/vblo/04,679.99,yes,locked 2006.257.10:29:42.01/vblo/05,709.99,yes,locked 2006.257.10:29:42.01/vblo/06,719.99,yes,locked 2006.257.10:29:42.01/vblo/07,734.99,yes,locked 2006.257.10:29:42.01/vblo/08,744.99,yes,locked 2006.257.10:29:42.16/vabw/8 2006.257.10:29:42.31/vbbw/8 2006.257.10:29:42.40/xfe/off,on,15.0 2006.257.10:29:42.77/ifatt/23,28,28,28 2006.257.10:29:43.07/fmout-gps/S +4.61E-07 2006.257.10:29:43.11:!2006.257.10:30:59 2006.257.10:30:59.01:data_valid=off 2006.257.10:30:59.01:"et 2006.257.10:30:59.01:!+3s 2006.257.10:31:02.02:"tape 2006.257.10:31:02.02:postob 2006.257.10:31:02.11/cable/+6.4767E-03 2006.257.10:31:02.11/wx/18.91,1013.9,96 2006.257.10:31:02.17/fmout-gps/S +4.62E-07 2006.257.10:31:02.17:scan_name=257-1032,jd0609,40 2006.257.10:31:02.17:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.10:31:03.13#flagr#flagr/antenna,new-source 2006.257.10:31:03.13:checkk5 2006.257.10:31:03.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:31:03.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:31:04.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:31:04.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:31:05.13/chk_obsdata//k5ts1/T2571029??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.10:31:05.52/chk_obsdata//k5ts2/T2571029??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.10:31:05.92/chk_obsdata//k5ts3/T2571029??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.10:31:06.32/chk_obsdata//k5ts4/T2571029??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.10:31:07.03/k5log//k5ts1_log_newline 2006.257.10:31:07.74/k5log//k5ts2_log_newline 2006.257.10:31:08.46/k5log//k5ts3_log_newline 2006.257.10:31:09.20/k5log//k5ts4_log_newline 2006.257.10:31:09.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:31:09.22:setupk4=1 2006.257.10:31:09.23$setupk4/echo=on 2006.257.10:31:09.23$setupk4/pcalon 2006.257.10:31:09.23$pcalon/"no phase cal control is implemented here 2006.257.10:31:09.23$setupk4/"tpicd=stop 2006.257.10:31:09.23$setupk4/"rec=synch_on 2006.257.10:31:09.23$setupk4/"rec_mode=128 2006.257.10:31:09.23$setupk4/!* 2006.257.10:31:09.23$setupk4/recpk4 2006.257.10:31:09.23$recpk4/recpatch= 2006.257.10:31:09.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:31:09.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:31:09.23$setupk4/vck44 2006.257.10:31:09.23$vck44/valo=1,524.99 2006.257.10:31:09.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.10:31:09.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.10:31:09.23#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:09.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:09.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:09.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:09.23#ibcon#enter wrdev, iclass 38, count 0 2006.257.10:31:09.23#ibcon#first serial, iclass 38, count 0 2006.257.10:31:09.23#ibcon#enter sib2, iclass 38, count 0 2006.257.10:31:09.23#ibcon#flushed, iclass 38, count 0 2006.257.10:31:09.23#ibcon#about to write, iclass 38, count 0 2006.257.10:31:09.23#ibcon#wrote, iclass 38, count 0 2006.257.10:31:09.23#ibcon#about to read 3, iclass 38, count 0 2006.257.10:31:09.25#ibcon#read 3, iclass 38, count 0 2006.257.10:31:09.25#ibcon#about to read 4, iclass 38, count 0 2006.257.10:31:09.25#ibcon#read 4, iclass 38, count 0 2006.257.10:31:09.25#ibcon#about to read 5, iclass 38, count 0 2006.257.10:31:09.25#ibcon#read 5, iclass 38, count 0 2006.257.10:31:09.25#ibcon#about to read 6, iclass 38, count 0 2006.257.10:31:09.25#ibcon#read 6, iclass 38, count 0 2006.257.10:31:09.25#ibcon#end of sib2, iclass 38, count 0 2006.257.10:31:09.25#ibcon#*mode == 0, iclass 38, count 0 2006.257.10:31:09.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.10:31:09.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:31:09.25#ibcon#*before write, iclass 38, count 0 2006.257.10:31:09.25#ibcon#enter sib2, iclass 38, count 0 2006.257.10:31:09.25#ibcon#flushed, iclass 38, count 0 2006.257.10:31:09.25#ibcon#about to write, iclass 38, count 0 2006.257.10:31:09.25#ibcon#wrote, iclass 38, count 0 2006.257.10:31:09.25#ibcon#about to read 3, iclass 38, count 0 2006.257.10:31:09.30#ibcon#read 3, iclass 38, count 0 2006.257.10:31:09.30#ibcon#about to read 4, iclass 38, count 0 2006.257.10:31:09.30#ibcon#read 4, iclass 38, count 0 2006.257.10:31:09.30#ibcon#about to read 5, iclass 38, count 0 2006.257.10:31:09.30#ibcon#read 5, iclass 38, count 0 2006.257.10:31:09.30#ibcon#about to read 6, iclass 38, count 0 2006.257.10:31:09.30#ibcon#read 6, iclass 38, count 0 2006.257.10:31:09.30#ibcon#end of sib2, iclass 38, count 0 2006.257.10:31:09.30#ibcon#*after write, iclass 38, count 0 2006.257.10:31:09.30#ibcon#*before return 0, iclass 38, count 0 2006.257.10:31:09.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:09.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:09.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.10:31:09.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.10:31:09.30$vck44/va=1,8 2006.257.10:31:09.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.10:31:09.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.10:31:09.30#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:09.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:09.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:09.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:09.30#ibcon#enter wrdev, iclass 40, count 2 2006.257.10:31:09.30#ibcon#first serial, iclass 40, count 2 2006.257.10:31:09.30#ibcon#enter sib2, iclass 40, count 2 2006.257.10:31:09.30#ibcon#flushed, iclass 40, count 2 2006.257.10:31:09.30#ibcon#about to write, iclass 40, count 2 2006.257.10:31:09.30#ibcon#wrote, iclass 40, count 2 2006.257.10:31:09.30#ibcon#about to read 3, iclass 40, count 2 2006.257.10:31:09.32#ibcon#read 3, iclass 40, count 2 2006.257.10:31:09.32#ibcon#about to read 4, iclass 40, count 2 2006.257.10:31:09.32#ibcon#read 4, iclass 40, count 2 2006.257.10:31:09.32#ibcon#about to read 5, iclass 40, count 2 2006.257.10:31:09.32#ibcon#read 5, iclass 40, count 2 2006.257.10:31:09.32#ibcon#about to read 6, iclass 40, count 2 2006.257.10:31:09.32#ibcon#read 6, iclass 40, count 2 2006.257.10:31:09.32#ibcon#end of sib2, iclass 40, count 2 2006.257.10:31:09.32#ibcon#*mode == 0, iclass 40, count 2 2006.257.10:31:09.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.10:31:09.32#ibcon#[25=AT01-08\r\n] 2006.257.10:31:09.32#ibcon#*before write, iclass 40, count 2 2006.257.10:31:09.32#ibcon#enter sib2, iclass 40, count 2 2006.257.10:31:09.32#ibcon#flushed, iclass 40, count 2 2006.257.10:31:09.32#ibcon#about to write, iclass 40, count 2 2006.257.10:31:09.32#ibcon#wrote, iclass 40, count 2 2006.257.10:31:09.32#ibcon#about to read 3, iclass 40, count 2 2006.257.10:31:09.35#ibcon#read 3, iclass 40, count 2 2006.257.10:31:09.35#ibcon#about to read 4, iclass 40, count 2 2006.257.10:31:09.35#ibcon#read 4, iclass 40, count 2 2006.257.10:31:09.35#ibcon#about to read 5, iclass 40, count 2 2006.257.10:31:09.35#ibcon#read 5, iclass 40, count 2 2006.257.10:31:09.35#ibcon#about to read 6, iclass 40, count 2 2006.257.10:31:09.35#ibcon#read 6, iclass 40, count 2 2006.257.10:31:09.35#ibcon#end of sib2, iclass 40, count 2 2006.257.10:31:09.35#ibcon#*after write, iclass 40, count 2 2006.257.10:31:09.35#ibcon#*before return 0, iclass 40, count 2 2006.257.10:31:09.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:09.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:09.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.10:31:09.35#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:09.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:09.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:09.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:09.47#ibcon#enter wrdev, iclass 40, count 0 2006.257.10:31:09.47#ibcon#first serial, iclass 40, count 0 2006.257.10:31:09.47#ibcon#enter sib2, iclass 40, count 0 2006.257.10:31:09.47#ibcon#flushed, iclass 40, count 0 2006.257.10:31:09.47#ibcon#about to write, iclass 40, count 0 2006.257.10:31:09.47#ibcon#wrote, iclass 40, count 0 2006.257.10:31:09.47#ibcon#about to read 3, iclass 40, count 0 2006.257.10:31:09.49#ibcon#read 3, iclass 40, count 0 2006.257.10:31:09.49#ibcon#about to read 4, iclass 40, count 0 2006.257.10:31:09.49#ibcon#read 4, iclass 40, count 0 2006.257.10:31:09.49#ibcon#about to read 5, iclass 40, count 0 2006.257.10:31:09.49#ibcon#read 5, iclass 40, count 0 2006.257.10:31:09.49#ibcon#about to read 6, iclass 40, count 0 2006.257.10:31:09.49#ibcon#read 6, iclass 40, count 0 2006.257.10:31:09.49#ibcon#end of sib2, iclass 40, count 0 2006.257.10:31:09.49#ibcon#*mode == 0, iclass 40, count 0 2006.257.10:31:09.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.10:31:09.49#ibcon#[25=USB\r\n] 2006.257.10:31:09.49#ibcon#*before write, iclass 40, count 0 2006.257.10:31:09.49#ibcon#enter sib2, iclass 40, count 0 2006.257.10:31:09.49#ibcon#flushed, iclass 40, count 0 2006.257.10:31:09.49#ibcon#about to write, iclass 40, count 0 2006.257.10:31:09.49#ibcon#wrote, iclass 40, count 0 2006.257.10:31:09.49#ibcon#about to read 3, iclass 40, count 0 2006.257.10:31:09.52#ibcon#read 3, iclass 40, count 0 2006.257.10:31:09.52#ibcon#about to read 4, iclass 40, count 0 2006.257.10:31:09.52#ibcon#read 4, iclass 40, count 0 2006.257.10:31:09.52#ibcon#about to read 5, iclass 40, count 0 2006.257.10:31:09.52#ibcon#read 5, iclass 40, count 0 2006.257.10:31:09.52#ibcon#about to read 6, iclass 40, count 0 2006.257.10:31:09.52#ibcon#read 6, iclass 40, count 0 2006.257.10:31:09.52#ibcon#end of sib2, iclass 40, count 0 2006.257.10:31:09.52#ibcon#*after write, iclass 40, count 0 2006.257.10:31:09.52#ibcon#*before return 0, iclass 40, count 0 2006.257.10:31:09.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:09.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:09.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.10:31:09.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.10:31:09.52$vck44/valo=2,534.99 2006.257.10:31:09.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.10:31:09.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.10:31:09.52#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:09.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:09.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:09.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:09.52#ibcon#enter wrdev, iclass 4, count 0 2006.257.10:31:09.52#ibcon#first serial, iclass 4, count 0 2006.257.10:31:09.52#ibcon#enter sib2, iclass 4, count 0 2006.257.10:31:09.52#ibcon#flushed, iclass 4, count 0 2006.257.10:31:09.52#ibcon#about to write, iclass 4, count 0 2006.257.10:31:09.52#ibcon#wrote, iclass 4, count 0 2006.257.10:31:09.52#ibcon#about to read 3, iclass 4, count 0 2006.257.10:31:09.54#ibcon#read 3, iclass 4, count 0 2006.257.10:31:09.54#ibcon#about to read 4, iclass 4, count 0 2006.257.10:31:09.54#ibcon#read 4, iclass 4, count 0 2006.257.10:31:09.54#ibcon#about to read 5, iclass 4, count 0 2006.257.10:31:09.54#ibcon#read 5, iclass 4, count 0 2006.257.10:31:09.54#ibcon#about to read 6, iclass 4, count 0 2006.257.10:31:09.54#ibcon#read 6, iclass 4, count 0 2006.257.10:31:09.54#ibcon#end of sib2, iclass 4, count 0 2006.257.10:31:09.54#ibcon#*mode == 0, iclass 4, count 0 2006.257.10:31:09.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.10:31:09.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:31:09.54#ibcon#*before write, iclass 4, count 0 2006.257.10:31:09.54#ibcon#enter sib2, iclass 4, count 0 2006.257.10:31:09.54#ibcon#flushed, iclass 4, count 0 2006.257.10:31:09.54#ibcon#about to write, iclass 4, count 0 2006.257.10:31:09.54#ibcon#wrote, iclass 4, count 0 2006.257.10:31:09.54#ibcon#about to read 3, iclass 4, count 0 2006.257.10:31:09.58#ibcon#read 3, iclass 4, count 0 2006.257.10:31:09.58#ibcon#about to read 4, iclass 4, count 0 2006.257.10:31:09.58#ibcon#read 4, iclass 4, count 0 2006.257.10:31:09.58#ibcon#about to read 5, iclass 4, count 0 2006.257.10:31:09.58#ibcon#read 5, iclass 4, count 0 2006.257.10:31:09.58#ibcon#about to read 6, iclass 4, count 0 2006.257.10:31:09.58#ibcon#read 6, iclass 4, count 0 2006.257.10:31:09.58#ibcon#end of sib2, iclass 4, count 0 2006.257.10:31:09.58#ibcon#*after write, iclass 4, count 0 2006.257.10:31:09.58#ibcon#*before return 0, iclass 4, count 0 2006.257.10:31:09.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:09.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:09.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.10:31:09.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.10:31:09.58$vck44/va=2,7 2006.257.10:31:09.58#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.10:31:09.58#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.10:31:09.58#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:09.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:09.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:09.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:09.64#ibcon#enter wrdev, iclass 6, count 2 2006.257.10:31:09.64#ibcon#first serial, iclass 6, count 2 2006.257.10:31:09.64#ibcon#enter sib2, iclass 6, count 2 2006.257.10:31:09.64#ibcon#flushed, iclass 6, count 2 2006.257.10:31:09.64#ibcon#about to write, iclass 6, count 2 2006.257.10:31:09.64#ibcon#wrote, iclass 6, count 2 2006.257.10:31:09.64#ibcon#about to read 3, iclass 6, count 2 2006.257.10:31:09.66#ibcon#read 3, iclass 6, count 2 2006.257.10:31:09.66#ibcon#about to read 4, iclass 6, count 2 2006.257.10:31:09.66#ibcon#read 4, iclass 6, count 2 2006.257.10:31:09.66#ibcon#about to read 5, iclass 6, count 2 2006.257.10:31:09.66#ibcon#read 5, iclass 6, count 2 2006.257.10:31:09.66#ibcon#about to read 6, iclass 6, count 2 2006.257.10:31:09.66#ibcon#read 6, iclass 6, count 2 2006.257.10:31:09.66#ibcon#end of sib2, iclass 6, count 2 2006.257.10:31:09.66#ibcon#*mode == 0, iclass 6, count 2 2006.257.10:31:09.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.10:31:09.66#ibcon#[25=AT02-07\r\n] 2006.257.10:31:09.66#ibcon#*before write, iclass 6, count 2 2006.257.10:31:09.66#ibcon#enter sib2, iclass 6, count 2 2006.257.10:31:09.66#ibcon#flushed, iclass 6, count 2 2006.257.10:31:09.66#ibcon#about to write, iclass 6, count 2 2006.257.10:31:09.66#ibcon#wrote, iclass 6, count 2 2006.257.10:31:09.66#ibcon#about to read 3, iclass 6, count 2 2006.257.10:31:09.69#ibcon#read 3, iclass 6, count 2 2006.257.10:31:09.69#ibcon#about to read 4, iclass 6, count 2 2006.257.10:31:09.69#ibcon#read 4, iclass 6, count 2 2006.257.10:31:09.69#ibcon#about to read 5, iclass 6, count 2 2006.257.10:31:09.69#ibcon#read 5, iclass 6, count 2 2006.257.10:31:09.69#ibcon#about to read 6, iclass 6, count 2 2006.257.10:31:09.69#ibcon#read 6, iclass 6, count 2 2006.257.10:31:09.69#ibcon#end of sib2, iclass 6, count 2 2006.257.10:31:09.69#ibcon#*after write, iclass 6, count 2 2006.257.10:31:09.69#ibcon#*before return 0, iclass 6, count 2 2006.257.10:31:09.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:09.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:09.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.10:31:09.69#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:09.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:09.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:09.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:09.81#ibcon#enter wrdev, iclass 6, count 0 2006.257.10:31:09.81#ibcon#first serial, iclass 6, count 0 2006.257.10:31:09.81#ibcon#enter sib2, iclass 6, count 0 2006.257.10:31:09.81#ibcon#flushed, iclass 6, count 0 2006.257.10:31:09.81#ibcon#about to write, iclass 6, count 0 2006.257.10:31:09.81#ibcon#wrote, iclass 6, count 0 2006.257.10:31:09.81#ibcon#about to read 3, iclass 6, count 0 2006.257.10:31:09.83#ibcon#read 3, iclass 6, count 0 2006.257.10:31:09.83#ibcon#about to read 4, iclass 6, count 0 2006.257.10:31:09.83#ibcon#read 4, iclass 6, count 0 2006.257.10:31:09.83#ibcon#about to read 5, iclass 6, count 0 2006.257.10:31:09.83#ibcon#read 5, iclass 6, count 0 2006.257.10:31:09.83#ibcon#about to read 6, iclass 6, count 0 2006.257.10:31:09.83#ibcon#read 6, iclass 6, count 0 2006.257.10:31:09.83#ibcon#end of sib2, iclass 6, count 0 2006.257.10:31:09.83#ibcon#*mode == 0, iclass 6, count 0 2006.257.10:31:09.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.10:31:09.83#ibcon#[25=USB\r\n] 2006.257.10:31:09.83#ibcon#*before write, iclass 6, count 0 2006.257.10:31:09.83#ibcon#enter sib2, iclass 6, count 0 2006.257.10:31:09.83#ibcon#flushed, iclass 6, count 0 2006.257.10:31:09.83#ibcon#about to write, iclass 6, count 0 2006.257.10:31:09.83#ibcon#wrote, iclass 6, count 0 2006.257.10:31:09.83#ibcon#about to read 3, iclass 6, count 0 2006.257.10:31:09.86#ibcon#read 3, iclass 6, count 0 2006.257.10:31:09.86#ibcon#about to read 4, iclass 6, count 0 2006.257.10:31:09.86#ibcon#read 4, iclass 6, count 0 2006.257.10:31:09.86#ibcon#about to read 5, iclass 6, count 0 2006.257.10:31:09.86#ibcon#read 5, iclass 6, count 0 2006.257.10:31:09.86#ibcon#about to read 6, iclass 6, count 0 2006.257.10:31:09.86#ibcon#read 6, iclass 6, count 0 2006.257.10:31:09.86#ibcon#end of sib2, iclass 6, count 0 2006.257.10:31:09.86#ibcon#*after write, iclass 6, count 0 2006.257.10:31:09.86#ibcon#*before return 0, iclass 6, count 0 2006.257.10:31:09.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:09.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:09.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.10:31:09.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.10:31:09.86$vck44/valo=3,564.99 2006.257.10:31:09.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.10:31:09.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.10:31:09.86#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:09.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:09.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:09.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:09.86#ibcon#enter wrdev, iclass 10, count 0 2006.257.10:31:09.86#ibcon#first serial, iclass 10, count 0 2006.257.10:31:09.86#ibcon#enter sib2, iclass 10, count 0 2006.257.10:31:09.86#ibcon#flushed, iclass 10, count 0 2006.257.10:31:09.86#ibcon#about to write, iclass 10, count 0 2006.257.10:31:09.86#ibcon#wrote, iclass 10, count 0 2006.257.10:31:09.86#ibcon#about to read 3, iclass 10, count 0 2006.257.10:31:09.88#ibcon#read 3, iclass 10, count 0 2006.257.10:31:09.88#ibcon#about to read 4, iclass 10, count 0 2006.257.10:31:09.88#ibcon#read 4, iclass 10, count 0 2006.257.10:31:09.88#ibcon#about to read 5, iclass 10, count 0 2006.257.10:31:09.88#ibcon#read 5, iclass 10, count 0 2006.257.10:31:09.88#ibcon#about to read 6, iclass 10, count 0 2006.257.10:31:09.88#ibcon#read 6, iclass 10, count 0 2006.257.10:31:09.88#ibcon#end of sib2, iclass 10, count 0 2006.257.10:31:09.88#ibcon#*mode == 0, iclass 10, count 0 2006.257.10:31:09.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.10:31:09.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:31:09.88#ibcon#*before write, iclass 10, count 0 2006.257.10:31:09.88#ibcon#enter sib2, iclass 10, count 0 2006.257.10:31:09.88#ibcon#flushed, iclass 10, count 0 2006.257.10:31:09.88#ibcon#about to write, iclass 10, count 0 2006.257.10:31:09.88#ibcon#wrote, iclass 10, count 0 2006.257.10:31:09.88#ibcon#about to read 3, iclass 10, count 0 2006.257.10:31:09.92#ibcon#read 3, iclass 10, count 0 2006.257.10:31:09.92#ibcon#about to read 4, iclass 10, count 0 2006.257.10:31:09.92#ibcon#read 4, iclass 10, count 0 2006.257.10:31:09.92#ibcon#about to read 5, iclass 10, count 0 2006.257.10:31:09.92#ibcon#read 5, iclass 10, count 0 2006.257.10:31:09.92#ibcon#about to read 6, iclass 10, count 0 2006.257.10:31:09.92#ibcon#read 6, iclass 10, count 0 2006.257.10:31:09.92#ibcon#end of sib2, iclass 10, count 0 2006.257.10:31:09.92#ibcon#*after write, iclass 10, count 0 2006.257.10:31:09.92#ibcon#*before return 0, iclass 10, count 0 2006.257.10:31:09.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:09.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:09.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.10:31:09.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.10:31:09.92$vck44/va=3,8 2006.257.10:31:09.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.10:31:09.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.10:31:09.92#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:09.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:09.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:09.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:09.98#ibcon#enter wrdev, iclass 12, count 2 2006.257.10:31:09.98#ibcon#first serial, iclass 12, count 2 2006.257.10:31:09.98#ibcon#enter sib2, iclass 12, count 2 2006.257.10:31:09.98#ibcon#flushed, iclass 12, count 2 2006.257.10:31:09.98#ibcon#about to write, iclass 12, count 2 2006.257.10:31:09.98#ibcon#wrote, iclass 12, count 2 2006.257.10:31:09.98#ibcon#about to read 3, iclass 12, count 2 2006.257.10:31:10.00#ibcon#read 3, iclass 12, count 2 2006.257.10:31:10.00#ibcon#about to read 4, iclass 12, count 2 2006.257.10:31:10.00#ibcon#read 4, iclass 12, count 2 2006.257.10:31:10.00#ibcon#about to read 5, iclass 12, count 2 2006.257.10:31:10.00#ibcon#read 5, iclass 12, count 2 2006.257.10:31:10.00#ibcon#about to read 6, iclass 12, count 2 2006.257.10:31:10.00#ibcon#read 6, iclass 12, count 2 2006.257.10:31:10.00#ibcon#end of sib2, iclass 12, count 2 2006.257.10:31:10.00#ibcon#*mode == 0, iclass 12, count 2 2006.257.10:31:10.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.10:31:10.00#ibcon#[25=AT03-08\r\n] 2006.257.10:31:10.00#ibcon#*before write, iclass 12, count 2 2006.257.10:31:10.00#ibcon#enter sib2, iclass 12, count 2 2006.257.10:31:10.00#ibcon#flushed, iclass 12, count 2 2006.257.10:31:10.00#ibcon#about to write, iclass 12, count 2 2006.257.10:31:10.00#ibcon#wrote, iclass 12, count 2 2006.257.10:31:10.00#ibcon#about to read 3, iclass 12, count 2 2006.257.10:31:10.03#ibcon#read 3, iclass 12, count 2 2006.257.10:31:10.03#ibcon#about to read 4, iclass 12, count 2 2006.257.10:31:10.03#ibcon#read 4, iclass 12, count 2 2006.257.10:31:10.03#ibcon#about to read 5, iclass 12, count 2 2006.257.10:31:10.03#ibcon#read 5, iclass 12, count 2 2006.257.10:31:10.03#ibcon#about to read 6, iclass 12, count 2 2006.257.10:31:10.03#ibcon#read 6, iclass 12, count 2 2006.257.10:31:10.03#ibcon#end of sib2, iclass 12, count 2 2006.257.10:31:10.03#ibcon#*after write, iclass 12, count 2 2006.257.10:31:10.03#ibcon#*before return 0, iclass 12, count 2 2006.257.10:31:10.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:10.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:10.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.10:31:10.03#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:10.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:10.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:10.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:10.15#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:31:10.15#ibcon#first serial, iclass 12, count 0 2006.257.10:31:10.15#ibcon#enter sib2, iclass 12, count 0 2006.257.10:31:10.15#ibcon#flushed, iclass 12, count 0 2006.257.10:31:10.15#ibcon#about to write, iclass 12, count 0 2006.257.10:31:10.15#ibcon#wrote, iclass 12, count 0 2006.257.10:31:10.15#ibcon#about to read 3, iclass 12, count 0 2006.257.10:31:10.17#ibcon#read 3, iclass 12, count 0 2006.257.10:31:10.17#ibcon#about to read 4, iclass 12, count 0 2006.257.10:31:10.17#ibcon#read 4, iclass 12, count 0 2006.257.10:31:10.17#ibcon#about to read 5, iclass 12, count 0 2006.257.10:31:10.17#ibcon#read 5, iclass 12, count 0 2006.257.10:31:10.17#ibcon#about to read 6, iclass 12, count 0 2006.257.10:31:10.17#ibcon#read 6, iclass 12, count 0 2006.257.10:31:10.17#ibcon#end of sib2, iclass 12, count 0 2006.257.10:31:10.17#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:31:10.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:31:10.17#ibcon#[25=USB\r\n] 2006.257.10:31:10.17#ibcon#*before write, iclass 12, count 0 2006.257.10:31:10.17#ibcon#enter sib2, iclass 12, count 0 2006.257.10:31:10.17#ibcon#flushed, iclass 12, count 0 2006.257.10:31:10.17#ibcon#about to write, iclass 12, count 0 2006.257.10:31:10.17#ibcon#wrote, iclass 12, count 0 2006.257.10:31:10.17#ibcon#about to read 3, iclass 12, count 0 2006.257.10:31:10.20#ibcon#read 3, iclass 12, count 0 2006.257.10:31:10.20#ibcon#about to read 4, iclass 12, count 0 2006.257.10:31:10.20#ibcon#read 4, iclass 12, count 0 2006.257.10:31:10.20#ibcon#about to read 5, iclass 12, count 0 2006.257.10:31:10.20#ibcon#read 5, iclass 12, count 0 2006.257.10:31:10.20#ibcon#about to read 6, iclass 12, count 0 2006.257.10:31:10.20#ibcon#read 6, iclass 12, count 0 2006.257.10:31:10.20#ibcon#end of sib2, iclass 12, count 0 2006.257.10:31:10.20#ibcon#*after write, iclass 12, count 0 2006.257.10:31:10.20#ibcon#*before return 0, iclass 12, count 0 2006.257.10:31:10.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:10.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:10.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:31:10.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:31:10.20$vck44/valo=4,624.99 2006.257.10:31:10.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.10:31:10.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.10:31:10.20#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:10.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:10.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:10.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:10.20#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:31:10.20#ibcon#first serial, iclass 14, count 0 2006.257.10:31:10.20#ibcon#enter sib2, iclass 14, count 0 2006.257.10:31:10.20#ibcon#flushed, iclass 14, count 0 2006.257.10:31:10.20#ibcon#about to write, iclass 14, count 0 2006.257.10:31:10.20#ibcon#wrote, iclass 14, count 0 2006.257.10:31:10.20#ibcon#about to read 3, iclass 14, count 0 2006.257.10:31:10.22#ibcon#read 3, iclass 14, count 0 2006.257.10:31:10.22#ibcon#about to read 4, iclass 14, count 0 2006.257.10:31:10.22#ibcon#read 4, iclass 14, count 0 2006.257.10:31:10.22#ibcon#about to read 5, iclass 14, count 0 2006.257.10:31:10.22#ibcon#read 5, iclass 14, count 0 2006.257.10:31:10.22#ibcon#about to read 6, iclass 14, count 0 2006.257.10:31:10.22#ibcon#read 6, iclass 14, count 0 2006.257.10:31:10.22#ibcon#end of sib2, iclass 14, count 0 2006.257.10:31:10.22#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:31:10.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:31:10.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:31:10.22#ibcon#*before write, iclass 14, count 0 2006.257.10:31:10.22#ibcon#enter sib2, iclass 14, count 0 2006.257.10:31:10.22#ibcon#flushed, iclass 14, count 0 2006.257.10:31:10.22#ibcon#about to write, iclass 14, count 0 2006.257.10:31:10.22#ibcon#wrote, iclass 14, count 0 2006.257.10:31:10.22#ibcon#about to read 3, iclass 14, count 0 2006.257.10:31:10.26#ibcon#read 3, iclass 14, count 0 2006.257.10:31:10.26#ibcon#about to read 4, iclass 14, count 0 2006.257.10:31:10.26#ibcon#read 4, iclass 14, count 0 2006.257.10:31:10.26#ibcon#about to read 5, iclass 14, count 0 2006.257.10:31:10.26#ibcon#read 5, iclass 14, count 0 2006.257.10:31:10.26#ibcon#about to read 6, iclass 14, count 0 2006.257.10:31:10.26#ibcon#read 6, iclass 14, count 0 2006.257.10:31:10.26#ibcon#end of sib2, iclass 14, count 0 2006.257.10:31:10.26#ibcon#*after write, iclass 14, count 0 2006.257.10:31:10.26#ibcon#*before return 0, iclass 14, count 0 2006.257.10:31:10.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:10.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:10.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:31:10.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:31:10.26$vck44/va=4,7 2006.257.10:31:10.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.10:31:10.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.10:31:10.26#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:10.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:10.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:10.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:10.32#ibcon#enter wrdev, iclass 16, count 2 2006.257.10:31:10.32#ibcon#first serial, iclass 16, count 2 2006.257.10:31:10.32#ibcon#enter sib2, iclass 16, count 2 2006.257.10:31:10.32#ibcon#flushed, iclass 16, count 2 2006.257.10:31:10.32#ibcon#about to write, iclass 16, count 2 2006.257.10:31:10.32#ibcon#wrote, iclass 16, count 2 2006.257.10:31:10.32#ibcon#about to read 3, iclass 16, count 2 2006.257.10:31:10.34#ibcon#read 3, iclass 16, count 2 2006.257.10:31:10.34#ibcon#about to read 4, iclass 16, count 2 2006.257.10:31:10.34#ibcon#read 4, iclass 16, count 2 2006.257.10:31:10.34#ibcon#about to read 5, iclass 16, count 2 2006.257.10:31:10.34#ibcon#read 5, iclass 16, count 2 2006.257.10:31:10.34#ibcon#about to read 6, iclass 16, count 2 2006.257.10:31:10.34#ibcon#read 6, iclass 16, count 2 2006.257.10:31:10.34#ibcon#end of sib2, iclass 16, count 2 2006.257.10:31:10.34#ibcon#*mode == 0, iclass 16, count 2 2006.257.10:31:10.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.10:31:10.34#ibcon#[25=AT04-07\r\n] 2006.257.10:31:10.34#ibcon#*before write, iclass 16, count 2 2006.257.10:31:10.34#ibcon#enter sib2, iclass 16, count 2 2006.257.10:31:10.34#ibcon#flushed, iclass 16, count 2 2006.257.10:31:10.34#ibcon#about to write, iclass 16, count 2 2006.257.10:31:10.34#ibcon#wrote, iclass 16, count 2 2006.257.10:31:10.34#ibcon#about to read 3, iclass 16, count 2 2006.257.10:31:10.37#ibcon#read 3, iclass 16, count 2 2006.257.10:31:10.37#ibcon#about to read 4, iclass 16, count 2 2006.257.10:31:10.37#ibcon#read 4, iclass 16, count 2 2006.257.10:31:10.37#ibcon#about to read 5, iclass 16, count 2 2006.257.10:31:10.37#ibcon#read 5, iclass 16, count 2 2006.257.10:31:10.37#ibcon#about to read 6, iclass 16, count 2 2006.257.10:31:10.37#ibcon#read 6, iclass 16, count 2 2006.257.10:31:10.37#ibcon#end of sib2, iclass 16, count 2 2006.257.10:31:10.37#ibcon#*after write, iclass 16, count 2 2006.257.10:31:10.37#ibcon#*before return 0, iclass 16, count 2 2006.257.10:31:10.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:10.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:10.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.10:31:10.37#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:10.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:10.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:10.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:10.49#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:31:10.49#ibcon#first serial, iclass 16, count 0 2006.257.10:31:10.49#ibcon#enter sib2, iclass 16, count 0 2006.257.10:31:10.49#ibcon#flushed, iclass 16, count 0 2006.257.10:31:10.49#ibcon#about to write, iclass 16, count 0 2006.257.10:31:10.49#ibcon#wrote, iclass 16, count 0 2006.257.10:31:10.49#ibcon#about to read 3, iclass 16, count 0 2006.257.10:31:10.51#ibcon#read 3, iclass 16, count 0 2006.257.10:31:10.51#ibcon#about to read 4, iclass 16, count 0 2006.257.10:31:10.51#ibcon#read 4, iclass 16, count 0 2006.257.10:31:10.51#ibcon#about to read 5, iclass 16, count 0 2006.257.10:31:10.51#ibcon#read 5, iclass 16, count 0 2006.257.10:31:10.51#ibcon#about to read 6, iclass 16, count 0 2006.257.10:31:10.51#ibcon#read 6, iclass 16, count 0 2006.257.10:31:10.51#ibcon#end of sib2, iclass 16, count 0 2006.257.10:31:10.51#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:31:10.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:31:10.51#ibcon#[25=USB\r\n] 2006.257.10:31:10.51#ibcon#*before write, iclass 16, count 0 2006.257.10:31:10.51#ibcon#enter sib2, iclass 16, count 0 2006.257.10:31:10.51#ibcon#flushed, iclass 16, count 0 2006.257.10:31:10.51#ibcon#about to write, iclass 16, count 0 2006.257.10:31:10.51#ibcon#wrote, iclass 16, count 0 2006.257.10:31:10.51#ibcon#about to read 3, iclass 16, count 0 2006.257.10:31:10.54#ibcon#read 3, iclass 16, count 0 2006.257.10:31:10.54#ibcon#about to read 4, iclass 16, count 0 2006.257.10:31:10.54#ibcon#read 4, iclass 16, count 0 2006.257.10:31:10.54#ibcon#about to read 5, iclass 16, count 0 2006.257.10:31:10.54#ibcon#read 5, iclass 16, count 0 2006.257.10:31:10.54#ibcon#about to read 6, iclass 16, count 0 2006.257.10:31:10.54#ibcon#read 6, iclass 16, count 0 2006.257.10:31:10.54#ibcon#end of sib2, iclass 16, count 0 2006.257.10:31:10.54#ibcon#*after write, iclass 16, count 0 2006.257.10:31:10.54#ibcon#*before return 0, iclass 16, count 0 2006.257.10:31:10.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:10.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:10.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:31:10.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:31:10.54$vck44/valo=5,734.99 2006.257.10:31:10.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.10:31:10.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.10:31:10.54#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:10.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:10.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:10.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:10.54#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:31:10.54#ibcon#first serial, iclass 18, count 0 2006.257.10:31:10.54#ibcon#enter sib2, iclass 18, count 0 2006.257.10:31:10.54#ibcon#flushed, iclass 18, count 0 2006.257.10:31:10.54#ibcon#about to write, iclass 18, count 0 2006.257.10:31:10.54#ibcon#wrote, iclass 18, count 0 2006.257.10:31:10.54#ibcon#about to read 3, iclass 18, count 0 2006.257.10:31:10.56#ibcon#read 3, iclass 18, count 0 2006.257.10:31:10.56#ibcon#about to read 4, iclass 18, count 0 2006.257.10:31:10.56#ibcon#read 4, iclass 18, count 0 2006.257.10:31:10.56#ibcon#about to read 5, iclass 18, count 0 2006.257.10:31:10.56#ibcon#read 5, iclass 18, count 0 2006.257.10:31:10.56#ibcon#about to read 6, iclass 18, count 0 2006.257.10:31:10.56#ibcon#read 6, iclass 18, count 0 2006.257.10:31:10.56#ibcon#end of sib2, iclass 18, count 0 2006.257.10:31:10.56#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:31:10.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:31:10.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:31:10.56#ibcon#*before write, iclass 18, count 0 2006.257.10:31:10.56#ibcon#enter sib2, iclass 18, count 0 2006.257.10:31:10.56#ibcon#flushed, iclass 18, count 0 2006.257.10:31:10.56#ibcon#about to write, iclass 18, count 0 2006.257.10:31:10.56#ibcon#wrote, iclass 18, count 0 2006.257.10:31:10.56#ibcon#about to read 3, iclass 18, count 0 2006.257.10:31:10.60#ibcon#read 3, iclass 18, count 0 2006.257.10:31:10.60#ibcon#about to read 4, iclass 18, count 0 2006.257.10:31:10.60#ibcon#read 4, iclass 18, count 0 2006.257.10:31:10.60#ibcon#about to read 5, iclass 18, count 0 2006.257.10:31:10.60#ibcon#read 5, iclass 18, count 0 2006.257.10:31:10.60#ibcon#about to read 6, iclass 18, count 0 2006.257.10:31:10.60#ibcon#read 6, iclass 18, count 0 2006.257.10:31:10.60#ibcon#end of sib2, iclass 18, count 0 2006.257.10:31:10.60#ibcon#*after write, iclass 18, count 0 2006.257.10:31:10.60#ibcon#*before return 0, iclass 18, count 0 2006.257.10:31:10.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:10.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:10.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:31:10.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:31:10.60$vck44/va=5,4 2006.257.10:31:10.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.10:31:10.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.10:31:10.60#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:10.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:10.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:10.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:10.66#ibcon#enter wrdev, iclass 20, count 2 2006.257.10:31:10.66#ibcon#first serial, iclass 20, count 2 2006.257.10:31:10.66#ibcon#enter sib2, iclass 20, count 2 2006.257.10:31:10.66#ibcon#flushed, iclass 20, count 2 2006.257.10:31:10.66#ibcon#about to write, iclass 20, count 2 2006.257.10:31:10.66#ibcon#wrote, iclass 20, count 2 2006.257.10:31:10.66#ibcon#about to read 3, iclass 20, count 2 2006.257.10:31:10.68#ibcon#read 3, iclass 20, count 2 2006.257.10:31:10.68#ibcon#about to read 4, iclass 20, count 2 2006.257.10:31:10.68#ibcon#read 4, iclass 20, count 2 2006.257.10:31:10.68#ibcon#about to read 5, iclass 20, count 2 2006.257.10:31:10.68#ibcon#read 5, iclass 20, count 2 2006.257.10:31:10.68#ibcon#about to read 6, iclass 20, count 2 2006.257.10:31:10.68#ibcon#read 6, iclass 20, count 2 2006.257.10:31:10.68#ibcon#end of sib2, iclass 20, count 2 2006.257.10:31:10.68#ibcon#*mode == 0, iclass 20, count 2 2006.257.10:31:10.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.10:31:10.68#ibcon#[25=AT05-04\r\n] 2006.257.10:31:10.68#ibcon#*before write, iclass 20, count 2 2006.257.10:31:10.68#ibcon#enter sib2, iclass 20, count 2 2006.257.10:31:10.68#ibcon#flushed, iclass 20, count 2 2006.257.10:31:10.68#ibcon#about to write, iclass 20, count 2 2006.257.10:31:10.68#ibcon#wrote, iclass 20, count 2 2006.257.10:31:10.68#ibcon#about to read 3, iclass 20, count 2 2006.257.10:31:10.71#ibcon#read 3, iclass 20, count 2 2006.257.10:31:10.71#ibcon#about to read 4, iclass 20, count 2 2006.257.10:31:10.71#ibcon#read 4, iclass 20, count 2 2006.257.10:31:10.71#ibcon#about to read 5, iclass 20, count 2 2006.257.10:31:10.71#ibcon#read 5, iclass 20, count 2 2006.257.10:31:10.71#ibcon#about to read 6, iclass 20, count 2 2006.257.10:31:10.71#ibcon#read 6, iclass 20, count 2 2006.257.10:31:10.71#ibcon#end of sib2, iclass 20, count 2 2006.257.10:31:10.71#ibcon#*after write, iclass 20, count 2 2006.257.10:31:10.71#ibcon#*before return 0, iclass 20, count 2 2006.257.10:31:10.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:10.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:10.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.10:31:10.71#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:10.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:10.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:10.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:10.83#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:31:10.83#ibcon#first serial, iclass 20, count 0 2006.257.10:31:10.83#ibcon#enter sib2, iclass 20, count 0 2006.257.10:31:10.83#ibcon#flushed, iclass 20, count 0 2006.257.10:31:10.83#ibcon#about to write, iclass 20, count 0 2006.257.10:31:10.83#ibcon#wrote, iclass 20, count 0 2006.257.10:31:10.83#ibcon#about to read 3, iclass 20, count 0 2006.257.10:31:10.85#ibcon#read 3, iclass 20, count 0 2006.257.10:31:10.85#ibcon#about to read 4, iclass 20, count 0 2006.257.10:31:10.85#ibcon#read 4, iclass 20, count 0 2006.257.10:31:10.85#ibcon#about to read 5, iclass 20, count 0 2006.257.10:31:10.85#ibcon#read 5, iclass 20, count 0 2006.257.10:31:10.85#ibcon#about to read 6, iclass 20, count 0 2006.257.10:31:10.85#ibcon#read 6, iclass 20, count 0 2006.257.10:31:10.85#ibcon#end of sib2, iclass 20, count 0 2006.257.10:31:10.85#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:31:10.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:31:10.85#ibcon#[25=USB\r\n] 2006.257.10:31:10.85#ibcon#*before write, iclass 20, count 0 2006.257.10:31:10.85#ibcon#enter sib2, iclass 20, count 0 2006.257.10:31:10.85#ibcon#flushed, iclass 20, count 0 2006.257.10:31:10.85#ibcon#about to write, iclass 20, count 0 2006.257.10:31:10.85#ibcon#wrote, iclass 20, count 0 2006.257.10:31:10.85#ibcon#about to read 3, iclass 20, count 0 2006.257.10:31:10.88#ibcon#read 3, iclass 20, count 0 2006.257.10:31:10.88#ibcon#about to read 4, iclass 20, count 0 2006.257.10:31:10.88#ibcon#read 4, iclass 20, count 0 2006.257.10:31:10.88#ibcon#about to read 5, iclass 20, count 0 2006.257.10:31:10.88#ibcon#read 5, iclass 20, count 0 2006.257.10:31:10.88#ibcon#about to read 6, iclass 20, count 0 2006.257.10:31:10.88#ibcon#read 6, iclass 20, count 0 2006.257.10:31:10.88#ibcon#end of sib2, iclass 20, count 0 2006.257.10:31:10.88#ibcon#*after write, iclass 20, count 0 2006.257.10:31:10.88#ibcon#*before return 0, iclass 20, count 0 2006.257.10:31:10.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:10.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:10.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:31:10.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:31:10.88$vck44/valo=6,814.99 2006.257.10:31:10.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.10:31:10.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.10:31:10.88#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:10.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:10.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:10.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:10.88#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:31:10.88#ibcon#first serial, iclass 22, count 0 2006.257.10:31:10.88#ibcon#enter sib2, iclass 22, count 0 2006.257.10:31:10.88#ibcon#flushed, iclass 22, count 0 2006.257.10:31:10.88#ibcon#about to write, iclass 22, count 0 2006.257.10:31:10.88#ibcon#wrote, iclass 22, count 0 2006.257.10:31:10.88#ibcon#about to read 3, iclass 22, count 0 2006.257.10:31:10.90#ibcon#read 3, iclass 22, count 0 2006.257.10:31:10.90#ibcon#about to read 4, iclass 22, count 0 2006.257.10:31:10.90#ibcon#read 4, iclass 22, count 0 2006.257.10:31:10.90#ibcon#about to read 5, iclass 22, count 0 2006.257.10:31:10.90#ibcon#read 5, iclass 22, count 0 2006.257.10:31:10.90#ibcon#about to read 6, iclass 22, count 0 2006.257.10:31:10.90#ibcon#read 6, iclass 22, count 0 2006.257.10:31:10.90#ibcon#end of sib2, iclass 22, count 0 2006.257.10:31:10.90#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:31:10.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:31:10.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:31:10.90#ibcon#*before write, iclass 22, count 0 2006.257.10:31:10.90#ibcon#enter sib2, iclass 22, count 0 2006.257.10:31:10.90#ibcon#flushed, iclass 22, count 0 2006.257.10:31:10.90#ibcon#about to write, iclass 22, count 0 2006.257.10:31:10.90#ibcon#wrote, iclass 22, count 0 2006.257.10:31:10.90#ibcon#about to read 3, iclass 22, count 0 2006.257.10:31:10.94#ibcon#read 3, iclass 22, count 0 2006.257.10:31:10.94#ibcon#about to read 4, iclass 22, count 0 2006.257.10:31:10.94#ibcon#read 4, iclass 22, count 0 2006.257.10:31:10.94#ibcon#about to read 5, iclass 22, count 0 2006.257.10:31:10.94#ibcon#read 5, iclass 22, count 0 2006.257.10:31:10.94#ibcon#about to read 6, iclass 22, count 0 2006.257.10:31:10.94#ibcon#read 6, iclass 22, count 0 2006.257.10:31:10.94#ibcon#end of sib2, iclass 22, count 0 2006.257.10:31:10.94#ibcon#*after write, iclass 22, count 0 2006.257.10:31:10.94#ibcon#*before return 0, iclass 22, count 0 2006.257.10:31:10.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:10.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:10.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:31:10.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:31:10.94$vck44/va=6,4 2006.257.10:31:10.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.10:31:10.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.10:31:10.94#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:10.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:11.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:11.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:11.00#ibcon#enter wrdev, iclass 24, count 2 2006.257.10:31:11.00#ibcon#first serial, iclass 24, count 2 2006.257.10:31:11.00#ibcon#enter sib2, iclass 24, count 2 2006.257.10:31:11.00#ibcon#flushed, iclass 24, count 2 2006.257.10:31:11.00#ibcon#about to write, iclass 24, count 2 2006.257.10:31:11.00#ibcon#wrote, iclass 24, count 2 2006.257.10:31:11.00#ibcon#about to read 3, iclass 24, count 2 2006.257.10:31:11.02#ibcon#read 3, iclass 24, count 2 2006.257.10:31:11.02#ibcon#about to read 4, iclass 24, count 2 2006.257.10:31:11.02#ibcon#read 4, iclass 24, count 2 2006.257.10:31:11.02#ibcon#about to read 5, iclass 24, count 2 2006.257.10:31:11.02#ibcon#read 5, iclass 24, count 2 2006.257.10:31:11.02#ibcon#about to read 6, iclass 24, count 2 2006.257.10:31:11.02#ibcon#read 6, iclass 24, count 2 2006.257.10:31:11.02#ibcon#end of sib2, iclass 24, count 2 2006.257.10:31:11.02#ibcon#*mode == 0, iclass 24, count 2 2006.257.10:31:11.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.10:31:11.02#ibcon#[25=AT06-04\r\n] 2006.257.10:31:11.02#ibcon#*before write, iclass 24, count 2 2006.257.10:31:11.02#ibcon#enter sib2, iclass 24, count 2 2006.257.10:31:11.02#ibcon#flushed, iclass 24, count 2 2006.257.10:31:11.02#ibcon#about to write, iclass 24, count 2 2006.257.10:31:11.02#ibcon#wrote, iclass 24, count 2 2006.257.10:31:11.02#ibcon#about to read 3, iclass 24, count 2 2006.257.10:31:11.05#ibcon#read 3, iclass 24, count 2 2006.257.10:31:11.05#ibcon#about to read 4, iclass 24, count 2 2006.257.10:31:11.05#ibcon#read 4, iclass 24, count 2 2006.257.10:31:11.05#ibcon#about to read 5, iclass 24, count 2 2006.257.10:31:11.05#ibcon#read 5, iclass 24, count 2 2006.257.10:31:11.05#ibcon#about to read 6, iclass 24, count 2 2006.257.10:31:11.05#ibcon#read 6, iclass 24, count 2 2006.257.10:31:11.05#ibcon#end of sib2, iclass 24, count 2 2006.257.10:31:11.05#ibcon#*after write, iclass 24, count 2 2006.257.10:31:11.05#ibcon#*before return 0, iclass 24, count 2 2006.257.10:31:11.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:11.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:11.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.10:31:11.05#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:11.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:11.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:11.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:11.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:31:11.17#ibcon#first serial, iclass 24, count 0 2006.257.10:31:11.17#ibcon#enter sib2, iclass 24, count 0 2006.257.10:31:11.17#ibcon#flushed, iclass 24, count 0 2006.257.10:31:11.17#ibcon#about to write, iclass 24, count 0 2006.257.10:31:11.17#ibcon#wrote, iclass 24, count 0 2006.257.10:31:11.17#ibcon#about to read 3, iclass 24, count 0 2006.257.10:31:11.19#ibcon#read 3, iclass 24, count 0 2006.257.10:31:11.19#ibcon#about to read 4, iclass 24, count 0 2006.257.10:31:11.19#ibcon#read 4, iclass 24, count 0 2006.257.10:31:11.19#ibcon#about to read 5, iclass 24, count 0 2006.257.10:31:11.19#ibcon#read 5, iclass 24, count 0 2006.257.10:31:11.19#ibcon#about to read 6, iclass 24, count 0 2006.257.10:31:11.19#ibcon#read 6, iclass 24, count 0 2006.257.10:31:11.19#ibcon#end of sib2, iclass 24, count 0 2006.257.10:31:11.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:31:11.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:31:11.19#ibcon#[25=USB\r\n] 2006.257.10:31:11.19#ibcon#*before write, iclass 24, count 0 2006.257.10:31:11.19#ibcon#enter sib2, iclass 24, count 0 2006.257.10:31:11.19#ibcon#flushed, iclass 24, count 0 2006.257.10:31:11.19#ibcon#about to write, iclass 24, count 0 2006.257.10:31:11.19#ibcon#wrote, iclass 24, count 0 2006.257.10:31:11.19#ibcon#about to read 3, iclass 24, count 0 2006.257.10:31:11.22#ibcon#read 3, iclass 24, count 0 2006.257.10:31:11.22#ibcon#about to read 4, iclass 24, count 0 2006.257.10:31:11.22#ibcon#read 4, iclass 24, count 0 2006.257.10:31:11.22#ibcon#about to read 5, iclass 24, count 0 2006.257.10:31:11.22#ibcon#read 5, iclass 24, count 0 2006.257.10:31:11.22#ibcon#about to read 6, iclass 24, count 0 2006.257.10:31:11.22#ibcon#read 6, iclass 24, count 0 2006.257.10:31:11.22#ibcon#end of sib2, iclass 24, count 0 2006.257.10:31:11.22#ibcon#*after write, iclass 24, count 0 2006.257.10:31:11.22#ibcon#*before return 0, iclass 24, count 0 2006.257.10:31:11.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:11.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:11.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:31:11.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:31:11.22$vck44/valo=7,864.99 2006.257.10:31:11.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.10:31:11.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.10:31:11.22#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:11.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:11.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:11.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:11.22#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:31:11.22#ibcon#first serial, iclass 26, count 0 2006.257.10:31:11.22#ibcon#enter sib2, iclass 26, count 0 2006.257.10:31:11.22#ibcon#flushed, iclass 26, count 0 2006.257.10:31:11.22#ibcon#about to write, iclass 26, count 0 2006.257.10:31:11.22#ibcon#wrote, iclass 26, count 0 2006.257.10:31:11.22#ibcon#about to read 3, iclass 26, count 0 2006.257.10:31:11.24#ibcon#read 3, iclass 26, count 0 2006.257.10:31:11.24#ibcon#about to read 4, iclass 26, count 0 2006.257.10:31:11.24#ibcon#read 4, iclass 26, count 0 2006.257.10:31:11.24#ibcon#about to read 5, iclass 26, count 0 2006.257.10:31:11.24#ibcon#read 5, iclass 26, count 0 2006.257.10:31:11.24#ibcon#about to read 6, iclass 26, count 0 2006.257.10:31:11.24#ibcon#read 6, iclass 26, count 0 2006.257.10:31:11.24#ibcon#end of sib2, iclass 26, count 0 2006.257.10:31:11.24#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:31:11.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:31:11.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:31:11.24#ibcon#*before write, iclass 26, count 0 2006.257.10:31:11.24#ibcon#enter sib2, iclass 26, count 0 2006.257.10:31:11.24#ibcon#flushed, iclass 26, count 0 2006.257.10:31:11.24#ibcon#about to write, iclass 26, count 0 2006.257.10:31:11.24#ibcon#wrote, iclass 26, count 0 2006.257.10:31:11.24#ibcon#about to read 3, iclass 26, count 0 2006.257.10:31:11.28#ibcon#read 3, iclass 26, count 0 2006.257.10:31:11.28#ibcon#about to read 4, iclass 26, count 0 2006.257.10:31:11.28#ibcon#read 4, iclass 26, count 0 2006.257.10:31:11.28#ibcon#about to read 5, iclass 26, count 0 2006.257.10:31:11.28#ibcon#read 5, iclass 26, count 0 2006.257.10:31:11.28#ibcon#about to read 6, iclass 26, count 0 2006.257.10:31:11.28#ibcon#read 6, iclass 26, count 0 2006.257.10:31:11.28#ibcon#end of sib2, iclass 26, count 0 2006.257.10:31:11.28#ibcon#*after write, iclass 26, count 0 2006.257.10:31:11.28#ibcon#*before return 0, iclass 26, count 0 2006.257.10:31:11.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:11.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:11.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:31:11.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:31:11.28$vck44/va=7,4 2006.257.10:31:11.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.10:31:11.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.10:31:11.28#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:11.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:11.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:11.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:11.34#ibcon#enter wrdev, iclass 28, count 2 2006.257.10:31:11.34#ibcon#first serial, iclass 28, count 2 2006.257.10:31:11.34#ibcon#enter sib2, iclass 28, count 2 2006.257.10:31:11.34#ibcon#flushed, iclass 28, count 2 2006.257.10:31:11.34#ibcon#about to write, iclass 28, count 2 2006.257.10:31:11.34#ibcon#wrote, iclass 28, count 2 2006.257.10:31:11.34#ibcon#about to read 3, iclass 28, count 2 2006.257.10:31:11.36#ibcon#read 3, iclass 28, count 2 2006.257.10:31:11.36#ibcon#about to read 4, iclass 28, count 2 2006.257.10:31:11.36#ibcon#read 4, iclass 28, count 2 2006.257.10:31:11.36#ibcon#about to read 5, iclass 28, count 2 2006.257.10:31:11.36#ibcon#read 5, iclass 28, count 2 2006.257.10:31:11.36#ibcon#about to read 6, iclass 28, count 2 2006.257.10:31:11.36#ibcon#read 6, iclass 28, count 2 2006.257.10:31:11.36#ibcon#end of sib2, iclass 28, count 2 2006.257.10:31:11.36#ibcon#*mode == 0, iclass 28, count 2 2006.257.10:31:11.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.10:31:11.36#ibcon#[25=AT07-04\r\n] 2006.257.10:31:11.36#ibcon#*before write, iclass 28, count 2 2006.257.10:31:11.36#ibcon#enter sib2, iclass 28, count 2 2006.257.10:31:11.36#ibcon#flushed, iclass 28, count 2 2006.257.10:31:11.36#ibcon#about to write, iclass 28, count 2 2006.257.10:31:11.36#ibcon#wrote, iclass 28, count 2 2006.257.10:31:11.36#ibcon#about to read 3, iclass 28, count 2 2006.257.10:31:11.39#ibcon#read 3, iclass 28, count 2 2006.257.10:31:11.39#ibcon#about to read 4, iclass 28, count 2 2006.257.10:31:11.39#ibcon#read 4, iclass 28, count 2 2006.257.10:31:11.39#ibcon#about to read 5, iclass 28, count 2 2006.257.10:31:11.39#ibcon#read 5, iclass 28, count 2 2006.257.10:31:11.39#ibcon#about to read 6, iclass 28, count 2 2006.257.10:31:11.39#ibcon#read 6, iclass 28, count 2 2006.257.10:31:11.39#ibcon#end of sib2, iclass 28, count 2 2006.257.10:31:11.39#ibcon#*after write, iclass 28, count 2 2006.257.10:31:11.39#ibcon#*before return 0, iclass 28, count 2 2006.257.10:31:11.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:11.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:11.45#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.10:31:11.45#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:11.45#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:11.56#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:11.56#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:11.56#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:31:11.56#ibcon#first serial, iclass 28, count 0 2006.257.10:31:11.56#ibcon#enter sib2, iclass 28, count 0 2006.257.10:31:11.56#ibcon#flushed, iclass 28, count 0 2006.257.10:31:11.56#ibcon#about to write, iclass 28, count 0 2006.257.10:31:11.56#ibcon#wrote, iclass 28, count 0 2006.257.10:31:11.56#ibcon#about to read 3, iclass 28, count 0 2006.257.10:31:11.58#ibcon#read 3, iclass 28, count 0 2006.257.10:31:11.58#ibcon#about to read 4, iclass 28, count 0 2006.257.10:31:11.58#ibcon#read 4, iclass 28, count 0 2006.257.10:31:11.58#ibcon#about to read 5, iclass 28, count 0 2006.257.10:31:11.58#ibcon#read 5, iclass 28, count 0 2006.257.10:31:11.58#ibcon#about to read 6, iclass 28, count 0 2006.257.10:31:11.58#ibcon#read 6, iclass 28, count 0 2006.257.10:31:11.58#ibcon#end of sib2, iclass 28, count 0 2006.257.10:31:11.58#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:31:11.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:31:11.58#ibcon#[25=USB\r\n] 2006.257.10:31:11.58#ibcon#*before write, iclass 28, count 0 2006.257.10:31:11.58#ibcon#enter sib2, iclass 28, count 0 2006.257.10:31:11.58#ibcon#flushed, iclass 28, count 0 2006.257.10:31:11.58#ibcon#about to write, iclass 28, count 0 2006.257.10:31:11.58#ibcon#wrote, iclass 28, count 0 2006.257.10:31:11.58#ibcon#about to read 3, iclass 28, count 0 2006.257.10:31:11.61#ibcon#read 3, iclass 28, count 0 2006.257.10:31:11.61#ibcon#about to read 4, iclass 28, count 0 2006.257.10:31:11.61#ibcon#read 4, iclass 28, count 0 2006.257.10:31:11.61#ibcon#about to read 5, iclass 28, count 0 2006.257.10:31:11.61#ibcon#read 5, iclass 28, count 0 2006.257.10:31:11.61#ibcon#about to read 6, iclass 28, count 0 2006.257.10:31:11.61#ibcon#read 6, iclass 28, count 0 2006.257.10:31:11.61#ibcon#end of sib2, iclass 28, count 0 2006.257.10:31:11.61#ibcon#*after write, iclass 28, count 0 2006.257.10:31:11.61#ibcon#*before return 0, iclass 28, count 0 2006.257.10:31:11.61#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:11.61#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:11.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:31:11.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:31:11.61$vck44/valo=8,884.99 2006.257.10:31:11.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.10:31:11.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.10:31:11.61#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:11.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:11.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:11.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:11.61#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:31:11.61#ibcon#first serial, iclass 30, count 0 2006.257.10:31:11.61#ibcon#enter sib2, iclass 30, count 0 2006.257.10:31:11.61#ibcon#flushed, iclass 30, count 0 2006.257.10:31:11.61#ibcon#about to write, iclass 30, count 0 2006.257.10:31:11.61#ibcon#wrote, iclass 30, count 0 2006.257.10:31:11.61#ibcon#about to read 3, iclass 30, count 0 2006.257.10:31:11.63#ibcon#read 3, iclass 30, count 0 2006.257.10:31:11.63#ibcon#about to read 4, iclass 30, count 0 2006.257.10:31:11.63#ibcon#read 4, iclass 30, count 0 2006.257.10:31:11.63#ibcon#about to read 5, iclass 30, count 0 2006.257.10:31:11.63#ibcon#read 5, iclass 30, count 0 2006.257.10:31:11.63#ibcon#about to read 6, iclass 30, count 0 2006.257.10:31:11.63#ibcon#read 6, iclass 30, count 0 2006.257.10:31:11.63#ibcon#end of sib2, iclass 30, count 0 2006.257.10:31:11.63#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:31:11.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:31:11.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:31:11.63#ibcon#*before write, iclass 30, count 0 2006.257.10:31:11.63#ibcon#enter sib2, iclass 30, count 0 2006.257.10:31:11.63#ibcon#flushed, iclass 30, count 0 2006.257.10:31:11.63#ibcon#about to write, iclass 30, count 0 2006.257.10:31:11.63#ibcon#wrote, iclass 30, count 0 2006.257.10:31:11.63#ibcon#about to read 3, iclass 30, count 0 2006.257.10:31:11.67#ibcon#read 3, iclass 30, count 0 2006.257.10:31:11.67#ibcon#about to read 4, iclass 30, count 0 2006.257.10:31:11.67#ibcon#read 4, iclass 30, count 0 2006.257.10:31:11.67#ibcon#about to read 5, iclass 30, count 0 2006.257.10:31:11.67#ibcon#read 5, iclass 30, count 0 2006.257.10:31:11.67#ibcon#about to read 6, iclass 30, count 0 2006.257.10:31:11.67#ibcon#read 6, iclass 30, count 0 2006.257.10:31:11.67#ibcon#end of sib2, iclass 30, count 0 2006.257.10:31:11.67#ibcon#*after write, iclass 30, count 0 2006.257.10:31:11.67#ibcon#*before return 0, iclass 30, count 0 2006.257.10:31:11.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:11.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:11.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:31:11.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:31:11.67$vck44/va=8,4 2006.257.10:31:11.67#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.10:31:11.67#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.10:31:11.67#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:11.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:31:11.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:31:11.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:31:11.73#ibcon#enter wrdev, iclass 32, count 2 2006.257.10:31:11.73#ibcon#first serial, iclass 32, count 2 2006.257.10:31:11.73#ibcon#enter sib2, iclass 32, count 2 2006.257.10:31:11.73#ibcon#flushed, iclass 32, count 2 2006.257.10:31:11.73#ibcon#about to write, iclass 32, count 2 2006.257.10:31:11.73#ibcon#wrote, iclass 32, count 2 2006.257.10:31:11.73#ibcon#about to read 3, iclass 32, count 2 2006.257.10:31:11.75#ibcon#read 3, iclass 32, count 2 2006.257.10:31:11.75#ibcon#about to read 4, iclass 32, count 2 2006.257.10:31:11.75#ibcon#read 4, iclass 32, count 2 2006.257.10:31:11.75#ibcon#about to read 5, iclass 32, count 2 2006.257.10:31:11.75#ibcon#read 5, iclass 32, count 2 2006.257.10:31:11.75#ibcon#about to read 6, iclass 32, count 2 2006.257.10:31:11.75#ibcon#read 6, iclass 32, count 2 2006.257.10:31:11.75#ibcon#end of sib2, iclass 32, count 2 2006.257.10:31:11.75#ibcon#*mode == 0, iclass 32, count 2 2006.257.10:31:11.75#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.10:31:11.75#ibcon#[25=AT08-04\r\n] 2006.257.10:31:11.75#ibcon#*before write, iclass 32, count 2 2006.257.10:31:11.75#ibcon#enter sib2, iclass 32, count 2 2006.257.10:31:11.75#ibcon#flushed, iclass 32, count 2 2006.257.10:31:11.75#ibcon#about to write, iclass 32, count 2 2006.257.10:31:11.75#ibcon#wrote, iclass 32, count 2 2006.257.10:31:11.75#ibcon#about to read 3, iclass 32, count 2 2006.257.10:31:11.78#ibcon#read 3, iclass 32, count 2 2006.257.10:31:11.78#ibcon#about to read 4, iclass 32, count 2 2006.257.10:31:11.78#ibcon#read 4, iclass 32, count 2 2006.257.10:31:11.78#ibcon#about to read 5, iclass 32, count 2 2006.257.10:31:11.78#ibcon#read 5, iclass 32, count 2 2006.257.10:31:11.78#ibcon#about to read 6, iclass 32, count 2 2006.257.10:31:11.78#ibcon#read 6, iclass 32, count 2 2006.257.10:31:11.78#ibcon#end of sib2, iclass 32, count 2 2006.257.10:31:11.78#ibcon#*after write, iclass 32, count 2 2006.257.10:31:11.78#ibcon#*before return 0, iclass 32, count 2 2006.257.10:31:11.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:31:11.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:31:11.78#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.10:31:11.78#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:11.78#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:31:11.90#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:31:11.90#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:31:11.90#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:31:11.90#ibcon#first serial, iclass 32, count 0 2006.257.10:31:11.90#ibcon#enter sib2, iclass 32, count 0 2006.257.10:31:11.90#ibcon#flushed, iclass 32, count 0 2006.257.10:31:11.90#ibcon#about to write, iclass 32, count 0 2006.257.10:31:11.90#ibcon#wrote, iclass 32, count 0 2006.257.10:31:11.90#ibcon#about to read 3, iclass 32, count 0 2006.257.10:31:11.92#ibcon#read 3, iclass 32, count 0 2006.257.10:31:11.92#ibcon#about to read 4, iclass 32, count 0 2006.257.10:31:11.92#ibcon#read 4, iclass 32, count 0 2006.257.10:31:11.92#ibcon#about to read 5, iclass 32, count 0 2006.257.10:31:11.92#ibcon#read 5, iclass 32, count 0 2006.257.10:31:11.92#ibcon#about to read 6, iclass 32, count 0 2006.257.10:31:11.92#ibcon#read 6, iclass 32, count 0 2006.257.10:31:11.92#ibcon#end of sib2, iclass 32, count 0 2006.257.10:31:11.92#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:31:11.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:31:11.92#ibcon#[25=USB\r\n] 2006.257.10:31:11.92#ibcon#*before write, iclass 32, count 0 2006.257.10:31:11.92#ibcon#enter sib2, iclass 32, count 0 2006.257.10:31:11.92#ibcon#flushed, iclass 32, count 0 2006.257.10:31:11.92#ibcon#about to write, iclass 32, count 0 2006.257.10:31:11.92#ibcon#wrote, iclass 32, count 0 2006.257.10:31:11.92#ibcon#about to read 3, iclass 32, count 0 2006.257.10:31:11.95#ibcon#read 3, iclass 32, count 0 2006.257.10:31:11.95#ibcon#about to read 4, iclass 32, count 0 2006.257.10:31:11.95#ibcon#read 4, iclass 32, count 0 2006.257.10:31:11.95#ibcon#about to read 5, iclass 32, count 0 2006.257.10:31:11.95#ibcon#read 5, iclass 32, count 0 2006.257.10:31:11.95#ibcon#about to read 6, iclass 32, count 0 2006.257.10:31:11.95#ibcon#read 6, iclass 32, count 0 2006.257.10:31:11.95#ibcon#end of sib2, iclass 32, count 0 2006.257.10:31:11.95#ibcon#*after write, iclass 32, count 0 2006.257.10:31:11.95#ibcon#*before return 0, iclass 32, count 0 2006.257.10:31:11.95#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:31:11.95#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:31:11.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:31:11.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:31:11.95$vck44/vblo=1,629.99 2006.257.10:31:11.95#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.10:31:11.95#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.10:31:11.95#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:11.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:31:11.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:31:11.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:31:11.95#ibcon#enter wrdev, iclass 34, count 0 2006.257.10:31:11.95#ibcon#first serial, iclass 34, count 0 2006.257.10:31:11.95#ibcon#enter sib2, iclass 34, count 0 2006.257.10:31:11.95#ibcon#flushed, iclass 34, count 0 2006.257.10:31:11.95#ibcon#about to write, iclass 34, count 0 2006.257.10:31:11.95#ibcon#wrote, iclass 34, count 0 2006.257.10:31:11.95#ibcon#about to read 3, iclass 34, count 0 2006.257.10:31:11.97#ibcon#read 3, iclass 34, count 0 2006.257.10:31:11.97#ibcon#about to read 4, iclass 34, count 0 2006.257.10:31:11.97#ibcon#read 4, iclass 34, count 0 2006.257.10:31:11.97#ibcon#about to read 5, iclass 34, count 0 2006.257.10:31:11.97#ibcon#read 5, iclass 34, count 0 2006.257.10:31:11.97#ibcon#about to read 6, iclass 34, count 0 2006.257.10:31:11.97#ibcon#read 6, iclass 34, count 0 2006.257.10:31:11.97#ibcon#end of sib2, iclass 34, count 0 2006.257.10:31:11.97#ibcon#*mode == 0, iclass 34, count 0 2006.257.10:31:11.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.10:31:11.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:31:11.97#ibcon#*before write, iclass 34, count 0 2006.257.10:31:11.97#ibcon#enter sib2, iclass 34, count 0 2006.257.10:31:11.97#ibcon#flushed, iclass 34, count 0 2006.257.10:31:11.97#ibcon#about to write, iclass 34, count 0 2006.257.10:31:11.97#ibcon#wrote, iclass 34, count 0 2006.257.10:31:11.97#ibcon#about to read 3, iclass 34, count 0 2006.257.10:31:12.01#ibcon#read 3, iclass 34, count 0 2006.257.10:31:12.01#ibcon#about to read 4, iclass 34, count 0 2006.257.10:31:12.01#ibcon#read 4, iclass 34, count 0 2006.257.10:31:12.01#ibcon#about to read 5, iclass 34, count 0 2006.257.10:31:12.01#ibcon#read 5, iclass 34, count 0 2006.257.10:31:12.01#ibcon#about to read 6, iclass 34, count 0 2006.257.10:31:12.01#ibcon#read 6, iclass 34, count 0 2006.257.10:31:12.01#ibcon#end of sib2, iclass 34, count 0 2006.257.10:31:12.01#ibcon#*after write, iclass 34, count 0 2006.257.10:31:12.01#ibcon#*before return 0, iclass 34, count 0 2006.257.10:31:12.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:31:12.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:31:12.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.10:31:12.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.10:31:12.01$vck44/vb=1,4 2006.257.10:31:12.01#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.10:31:12.01#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.10:31:12.01#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:12.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:31:12.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:31:12.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:31:12.01#ibcon#enter wrdev, iclass 36, count 2 2006.257.10:31:12.01#ibcon#first serial, iclass 36, count 2 2006.257.10:31:12.01#ibcon#enter sib2, iclass 36, count 2 2006.257.10:31:12.01#ibcon#flushed, iclass 36, count 2 2006.257.10:31:12.01#ibcon#about to write, iclass 36, count 2 2006.257.10:31:12.01#ibcon#wrote, iclass 36, count 2 2006.257.10:31:12.01#ibcon#about to read 3, iclass 36, count 2 2006.257.10:31:12.03#ibcon#read 3, iclass 36, count 2 2006.257.10:31:12.03#ibcon#about to read 4, iclass 36, count 2 2006.257.10:31:12.03#ibcon#read 4, iclass 36, count 2 2006.257.10:31:12.03#ibcon#about to read 5, iclass 36, count 2 2006.257.10:31:12.03#ibcon#read 5, iclass 36, count 2 2006.257.10:31:12.03#ibcon#about to read 6, iclass 36, count 2 2006.257.10:31:12.03#ibcon#read 6, iclass 36, count 2 2006.257.10:31:12.03#ibcon#end of sib2, iclass 36, count 2 2006.257.10:31:12.03#ibcon#*mode == 0, iclass 36, count 2 2006.257.10:31:12.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.10:31:12.03#ibcon#[27=AT01-04\r\n] 2006.257.10:31:12.03#ibcon#*before write, iclass 36, count 2 2006.257.10:31:12.03#ibcon#enter sib2, iclass 36, count 2 2006.257.10:31:12.03#ibcon#flushed, iclass 36, count 2 2006.257.10:31:12.03#ibcon#about to write, iclass 36, count 2 2006.257.10:31:12.03#ibcon#wrote, iclass 36, count 2 2006.257.10:31:12.03#ibcon#about to read 3, iclass 36, count 2 2006.257.10:31:12.06#ibcon#read 3, iclass 36, count 2 2006.257.10:31:12.06#ibcon#about to read 4, iclass 36, count 2 2006.257.10:31:12.06#ibcon#read 4, iclass 36, count 2 2006.257.10:31:12.06#ibcon#about to read 5, iclass 36, count 2 2006.257.10:31:12.06#ibcon#read 5, iclass 36, count 2 2006.257.10:31:12.06#ibcon#about to read 6, iclass 36, count 2 2006.257.10:31:12.06#ibcon#read 6, iclass 36, count 2 2006.257.10:31:12.06#ibcon#end of sib2, iclass 36, count 2 2006.257.10:31:12.06#ibcon#*after write, iclass 36, count 2 2006.257.10:31:12.06#ibcon#*before return 0, iclass 36, count 2 2006.257.10:31:12.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:31:12.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:31:12.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.10:31:12.06#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:12.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:31:12.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:31:12.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:31:12.18#ibcon#enter wrdev, iclass 36, count 0 2006.257.10:31:12.18#ibcon#first serial, iclass 36, count 0 2006.257.10:31:12.18#ibcon#enter sib2, iclass 36, count 0 2006.257.10:31:12.18#ibcon#flushed, iclass 36, count 0 2006.257.10:31:12.18#ibcon#about to write, iclass 36, count 0 2006.257.10:31:12.18#ibcon#wrote, iclass 36, count 0 2006.257.10:31:12.18#ibcon#about to read 3, iclass 36, count 0 2006.257.10:31:12.20#ibcon#read 3, iclass 36, count 0 2006.257.10:31:12.20#ibcon#about to read 4, iclass 36, count 0 2006.257.10:31:12.20#ibcon#read 4, iclass 36, count 0 2006.257.10:31:12.20#ibcon#about to read 5, iclass 36, count 0 2006.257.10:31:12.20#ibcon#read 5, iclass 36, count 0 2006.257.10:31:12.20#ibcon#about to read 6, iclass 36, count 0 2006.257.10:31:12.20#ibcon#read 6, iclass 36, count 0 2006.257.10:31:12.20#ibcon#end of sib2, iclass 36, count 0 2006.257.10:31:12.20#ibcon#*mode == 0, iclass 36, count 0 2006.257.10:31:12.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.10:31:12.20#ibcon#[27=USB\r\n] 2006.257.10:31:12.20#ibcon#*before write, iclass 36, count 0 2006.257.10:31:12.20#ibcon#enter sib2, iclass 36, count 0 2006.257.10:31:12.20#ibcon#flushed, iclass 36, count 0 2006.257.10:31:12.20#ibcon#about to write, iclass 36, count 0 2006.257.10:31:12.20#ibcon#wrote, iclass 36, count 0 2006.257.10:31:12.20#ibcon#about to read 3, iclass 36, count 0 2006.257.10:31:12.23#ibcon#read 3, iclass 36, count 0 2006.257.10:31:12.23#ibcon#about to read 4, iclass 36, count 0 2006.257.10:31:12.23#ibcon#read 4, iclass 36, count 0 2006.257.10:31:12.23#ibcon#about to read 5, iclass 36, count 0 2006.257.10:31:12.23#ibcon#read 5, iclass 36, count 0 2006.257.10:31:12.23#ibcon#about to read 6, iclass 36, count 0 2006.257.10:31:12.23#ibcon#read 6, iclass 36, count 0 2006.257.10:31:12.23#ibcon#end of sib2, iclass 36, count 0 2006.257.10:31:12.23#ibcon#*after write, iclass 36, count 0 2006.257.10:31:12.23#ibcon#*before return 0, iclass 36, count 0 2006.257.10:31:12.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:31:12.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:31:12.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.10:31:12.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.10:31:12.23$vck44/vblo=2,634.99 2006.257.10:31:12.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.10:31:12.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.10:31:12.23#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:12.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:12.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:12.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:12.23#ibcon#enter wrdev, iclass 38, count 0 2006.257.10:31:12.23#ibcon#first serial, iclass 38, count 0 2006.257.10:31:12.23#ibcon#enter sib2, iclass 38, count 0 2006.257.10:31:12.23#ibcon#flushed, iclass 38, count 0 2006.257.10:31:12.23#ibcon#about to write, iclass 38, count 0 2006.257.10:31:12.23#ibcon#wrote, iclass 38, count 0 2006.257.10:31:12.23#ibcon#about to read 3, iclass 38, count 0 2006.257.10:31:12.25#ibcon#read 3, iclass 38, count 0 2006.257.10:31:12.25#ibcon#about to read 4, iclass 38, count 0 2006.257.10:31:12.25#ibcon#read 4, iclass 38, count 0 2006.257.10:31:12.25#ibcon#about to read 5, iclass 38, count 0 2006.257.10:31:12.25#ibcon#read 5, iclass 38, count 0 2006.257.10:31:12.25#ibcon#about to read 6, iclass 38, count 0 2006.257.10:31:12.25#ibcon#read 6, iclass 38, count 0 2006.257.10:31:12.25#ibcon#end of sib2, iclass 38, count 0 2006.257.10:31:12.25#ibcon#*mode == 0, iclass 38, count 0 2006.257.10:31:12.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.10:31:12.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:31:12.25#ibcon#*before write, iclass 38, count 0 2006.257.10:31:12.25#ibcon#enter sib2, iclass 38, count 0 2006.257.10:31:12.25#ibcon#flushed, iclass 38, count 0 2006.257.10:31:12.25#ibcon#about to write, iclass 38, count 0 2006.257.10:31:12.25#ibcon#wrote, iclass 38, count 0 2006.257.10:31:12.25#ibcon#about to read 3, iclass 38, count 0 2006.257.10:31:12.29#ibcon#read 3, iclass 38, count 0 2006.257.10:31:12.29#ibcon#about to read 4, iclass 38, count 0 2006.257.10:31:12.29#ibcon#read 4, iclass 38, count 0 2006.257.10:31:12.29#ibcon#about to read 5, iclass 38, count 0 2006.257.10:31:12.29#ibcon#read 5, iclass 38, count 0 2006.257.10:31:12.29#ibcon#about to read 6, iclass 38, count 0 2006.257.10:31:12.29#ibcon#read 6, iclass 38, count 0 2006.257.10:31:12.29#ibcon#end of sib2, iclass 38, count 0 2006.257.10:31:12.29#ibcon#*after write, iclass 38, count 0 2006.257.10:31:12.29#ibcon#*before return 0, iclass 38, count 0 2006.257.10:31:12.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:12.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:31:12.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.10:31:12.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.10:31:12.29$vck44/vb=2,5 2006.257.10:31:12.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.10:31:12.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.10:31:12.29#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:12.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:12.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:12.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:12.35#ibcon#enter wrdev, iclass 40, count 2 2006.257.10:31:12.35#ibcon#first serial, iclass 40, count 2 2006.257.10:31:12.35#ibcon#enter sib2, iclass 40, count 2 2006.257.10:31:12.35#ibcon#flushed, iclass 40, count 2 2006.257.10:31:12.35#ibcon#about to write, iclass 40, count 2 2006.257.10:31:12.35#ibcon#wrote, iclass 40, count 2 2006.257.10:31:12.35#ibcon#about to read 3, iclass 40, count 2 2006.257.10:31:12.37#ibcon#read 3, iclass 40, count 2 2006.257.10:31:12.37#ibcon#about to read 4, iclass 40, count 2 2006.257.10:31:12.37#ibcon#read 4, iclass 40, count 2 2006.257.10:31:12.37#ibcon#about to read 5, iclass 40, count 2 2006.257.10:31:12.37#ibcon#read 5, iclass 40, count 2 2006.257.10:31:12.37#ibcon#about to read 6, iclass 40, count 2 2006.257.10:31:12.37#ibcon#read 6, iclass 40, count 2 2006.257.10:31:12.37#ibcon#end of sib2, iclass 40, count 2 2006.257.10:31:12.37#ibcon#*mode == 0, iclass 40, count 2 2006.257.10:31:12.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.10:31:12.37#ibcon#[27=AT02-05\r\n] 2006.257.10:31:12.37#ibcon#*before write, iclass 40, count 2 2006.257.10:31:12.37#ibcon#enter sib2, iclass 40, count 2 2006.257.10:31:12.37#ibcon#flushed, iclass 40, count 2 2006.257.10:31:12.37#ibcon#about to write, iclass 40, count 2 2006.257.10:31:12.37#ibcon#wrote, iclass 40, count 2 2006.257.10:31:12.37#ibcon#about to read 3, iclass 40, count 2 2006.257.10:31:12.40#ibcon#read 3, iclass 40, count 2 2006.257.10:31:12.44#ibcon#about to read 4, iclass 40, count 2 2006.257.10:31:12.44#ibcon#read 4, iclass 40, count 2 2006.257.10:31:12.44#ibcon#about to read 5, iclass 40, count 2 2006.257.10:31:12.44#ibcon#read 5, iclass 40, count 2 2006.257.10:31:12.44#ibcon#about to read 6, iclass 40, count 2 2006.257.10:31:12.44#ibcon#read 6, iclass 40, count 2 2006.257.10:31:12.44#ibcon#end of sib2, iclass 40, count 2 2006.257.10:31:12.44#ibcon#*after write, iclass 40, count 2 2006.257.10:31:12.44#ibcon#*before return 0, iclass 40, count 2 2006.257.10:31:12.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:12.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:31:12.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.10:31:12.45#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:12.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:12.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:12.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:12.56#ibcon#enter wrdev, iclass 40, count 0 2006.257.10:31:12.56#ibcon#first serial, iclass 40, count 0 2006.257.10:31:12.56#ibcon#enter sib2, iclass 40, count 0 2006.257.10:31:12.56#ibcon#flushed, iclass 40, count 0 2006.257.10:31:12.56#ibcon#about to write, iclass 40, count 0 2006.257.10:31:12.56#ibcon#wrote, iclass 40, count 0 2006.257.10:31:12.56#ibcon#about to read 3, iclass 40, count 0 2006.257.10:31:12.58#ibcon#read 3, iclass 40, count 0 2006.257.10:31:12.58#ibcon#about to read 4, iclass 40, count 0 2006.257.10:31:12.58#ibcon#read 4, iclass 40, count 0 2006.257.10:31:12.58#ibcon#about to read 5, iclass 40, count 0 2006.257.10:31:12.58#ibcon#read 5, iclass 40, count 0 2006.257.10:31:12.58#ibcon#about to read 6, iclass 40, count 0 2006.257.10:31:12.58#ibcon#read 6, iclass 40, count 0 2006.257.10:31:12.58#ibcon#end of sib2, iclass 40, count 0 2006.257.10:31:12.58#ibcon#*mode == 0, iclass 40, count 0 2006.257.10:31:12.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.10:31:12.58#ibcon#[27=USB\r\n] 2006.257.10:31:12.58#ibcon#*before write, iclass 40, count 0 2006.257.10:31:12.58#ibcon#enter sib2, iclass 40, count 0 2006.257.10:31:12.58#ibcon#flushed, iclass 40, count 0 2006.257.10:31:12.58#ibcon#about to write, iclass 40, count 0 2006.257.10:31:12.58#ibcon#wrote, iclass 40, count 0 2006.257.10:31:12.58#ibcon#about to read 3, iclass 40, count 0 2006.257.10:31:12.61#ibcon#read 3, iclass 40, count 0 2006.257.10:31:12.61#ibcon#about to read 4, iclass 40, count 0 2006.257.10:31:12.61#ibcon#read 4, iclass 40, count 0 2006.257.10:31:12.61#ibcon#about to read 5, iclass 40, count 0 2006.257.10:31:12.61#ibcon#read 5, iclass 40, count 0 2006.257.10:31:12.61#ibcon#about to read 6, iclass 40, count 0 2006.257.10:31:12.61#ibcon#read 6, iclass 40, count 0 2006.257.10:31:12.61#ibcon#end of sib2, iclass 40, count 0 2006.257.10:31:12.61#ibcon#*after write, iclass 40, count 0 2006.257.10:31:12.61#ibcon#*before return 0, iclass 40, count 0 2006.257.10:31:12.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:12.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:31:12.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.10:31:12.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.10:31:12.61$vck44/vblo=3,649.99 2006.257.10:31:12.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.10:31:12.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.10:31:12.61#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:12.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:12.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:12.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:12.61#ibcon#enter wrdev, iclass 4, count 0 2006.257.10:31:12.61#ibcon#first serial, iclass 4, count 0 2006.257.10:31:12.61#ibcon#enter sib2, iclass 4, count 0 2006.257.10:31:12.61#ibcon#flushed, iclass 4, count 0 2006.257.10:31:12.61#ibcon#about to write, iclass 4, count 0 2006.257.10:31:12.61#ibcon#wrote, iclass 4, count 0 2006.257.10:31:12.61#ibcon#about to read 3, iclass 4, count 0 2006.257.10:31:12.63#ibcon#read 3, iclass 4, count 0 2006.257.10:31:12.63#ibcon#about to read 4, iclass 4, count 0 2006.257.10:31:12.63#ibcon#read 4, iclass 4, count 0 2006.257.10:31:12.63#ibcon#about to read 5, iclass 4, count 0 2006.257.10:31:12.63#ibcon#read 5, iclass 4, count 0 2006.257.10:31:12.63#ibcon#about to read 6, iclass 4, count 0 2006.257.10:31:12.63#ibcon#read 6, iclass 4, count 0 2006.257.10:31:12.63#ibcon#end of sib2, iclass 4, count 0 2006.257.10:31:12.63#ibcon#*mode == 0, iclass 4, count 0 2006.257.10:31:12.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.10:31:12.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:31:12.63#ibcon#*before write, iclass 4, count 0 2006.257.10:31:12.63#ibcon#enter sib2, iclass 4, count 0 2006.257.10:31:12.63#ibcon#flushed, iclass 4, count 0 2006.257.10:31:12.63#ibcon#about to write, iclass 4, count 0 2006.257.10:31:12.63#ibcon#wrote, iclass 4, count 0 2006.257.10:31:12.63#ibcon#about to read 3, iclass 4, count 0 2006.257.10:31:12.67#ibcon#read 3, iclass 4, count 0 2006.257.10:31:12.67#ibcon#about to read 4, iclass 4, count 0 2006.257.10:31:12.67#ibcon#read 4, iclass 4, count 0 2006.257.10:31:12.67#ibcon#about to read 5, iclass 4, count 0 2006.257.10:31:12.67#ibcon#read 5, iclass 4, count 0 2006.257.10:31:12.67#ibcon#about to read 6, iclass 4, count 0 2006.257.10:31:12.67#ibcon#read 6, iclass 4, count 0 2006.257.10:31:12.67#ibcon#end of sib2, iclass 4, count 0 2006.257.10:31:12.67#ibcon#*after write, iclass 4, count 0 2006.257.10:31:12.67#ibcon#*before return 0, iclass 4, count 0 2006.257.10:31:12.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:12.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:31:12.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.10:31:12.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.10:31:12.67$vck44/vb=3,4 2006.257.10:31:12.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.10:31:12.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.10:31:12.67#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:12.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:12.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:12.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:12.73#ibcon#enter wrdev, iclass 6, count 2 2006.257.10:31:12.73#ibcon#first serial, iclass 6, count 2 2006.257.10:31:12.73#ibcon#enter sib2, iclass 6, count 2 2006.257.10:31:12.73#ibcon#flushed, iclass 6, count 2 2006.257.10:31:12.73#ibcon#about to write, iclass 6, count 2 2006.257.10:31:12.73#ibcon#wrote, iclass 6, count 2 2006.257.10:31:12.73#ibcon#about to read 3, iclass 6, count 2 2006.257.10:31:12.75#ibcon#read 3, iclass 6, count 2 2006.257.10:31:12.75#ibcon#about to read 4, iclass 6, count 2 2006.257.10:31:12.75#ibcon#read 4, iclass 6, count 2 2006.257.10:31:12.75#ibcon#about to read 5, iclass 6, count 2 2006.257.10:31:12.75#ibcon#read 5, iclass 6, count 2 2006.257.10:31:12.75#ibcon#about to read 6, iclass 6, count 2 2006.257.10:31:12.75#ibcon#read 6, iclass 6, count 2 2006.257.10:31:12.75#ibcon#end of sib2, iclass 6, count 2 2006.257.10:31:12.75#ibcon#*mode == 0, iclass 6, count 2 2006.257.10:31:12.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.10:31:12.75#ibcon#[27=AT03-04\r\n] 2006.257.10:31:12.75#ibcon#*before write, iclass 6, count 2 2006.257.10:31:12.75#ibcon#enter sib2, iclass 6, count 2 2006.257.10:31:12.75#ibcon#flushed, iclass 6, count 2 2006.257.10:31:12.75#ibcon#about to write, iclass 6, count 2 2006.257.10:31:12.75#ibcon#wrote, iclass 6, count 2 2006.257.10:31:12.75#ibcon#about to read 3, iclass 6, count 2 2006.257.10:31:12.78#ibcon#read 3, iclass 6, count 2 2006.257.10:31:12.78#ibcon#about to read 4, iclass 6, count 2 2006.257.10:31:12.78#ibcon#read 4, iclass 6, count 2 2006.257.10:31:12.78#ibcon#about to read 5, iclass 6, count 2 2006.257.10:31:12.78#ibcon#read 5, iclass 6, count 2 2006.257.10:31:12.78#ibcon#about to read 6, iclass 6, count 2 2006.257.10:31:12.78#ibcon#read 6, iclass 6, count 2 2006.257.10:31:12.78#ibcon#end of sib2, iclass 6, count 2 2006.257.10:31:12.78#ibcon#*after write, iclass 6, count 2 2006.257.10:31:12.78#ibcon#*before return 0, iclass 6, count 2 2006.257.10:31:12.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:12.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:31:12.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.10:31:12.78#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:12.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:12.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:12.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:12.90#ibcon#enter wrdev, iclass 6, count 0 2006.257.10:31:12.90#ibcon#first serial, iclass 6, count 0 2006.257.10:31:12.90#ibcon#enter sib2, iclass 6, count 0 2006.257.10:31:12.90#ibcon#flushed, iclass 6, count 0 2006.257.10:31:12.90#ibcon#about to write, iclass 6, count 0 2006.257.10:31:12.90#ibcon#wrote, iclass 6, count 0 2006.257.10:31:12.90#ibcon#about to read 3, iclass 6, count 0 2006.257.10:31:12.92#ibcon#read 3, iclass 6, count 0 2006.257.10:31:12.92#ibcon#about to read 4, iclass 6, count 0 2006.257.10:31:12.92#ibcon#read 4, iclass 6, count 0 2006.257.10:31:12.92#ibcon#about to read 5, iclass 6, count 0 2006.257.10:31:12.92#ibcon#read 5, iclass 6, count 0 2006.257.10:31:12.92#ibcon#about to read 6, iclass 6, count 0 2006.257.10:31:12.92#ibcon#read 6, iclass 6, count 0 2006.257.10:31:12.92#ibcon#end of sib2, iclass 6, count 0 2006.257.10:31:12.92#ibcon#*mode == 0, iclass 6, count 0 2006.257.10:31:12.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.10:31:12.92#ibcon#[27=USB\r\n] 2006.257.10:31:12.92#ibcon#*before write, iclass 6, count 0 2006.257.10:31:12.92#ibcon#enter sib2, iclass 6, count 0 2006.257.10:31:12.92#ibcon#flushed, iclass 6, count 0 2006.257.10:31:12.92#ibcon#about to write, iclass 6, count 0 2006.257.10:31:12.92#ibcon#wrote, iclass 6, count 0 2006.257.10:31:12.92#ibcon#about to read 3, iclass 6, count 0 2006.257.10:31:12.95#ibcon#read 3, iclass 6, count 0 2006.257.10:31:12.95#ibcon#about to read 4, iclass 6, count 0 2006.257.10:31:12.95#ibcon#read 4, iclass 6, count 0 2006.257.10:31:12.95#ibcon#about to read 5, iclass 6, count 0 2006.257.10:31:12.95#ibcon#read 5, iclass 6, count 0 2006.257.10:31:12.95#ibcon#about to read 6, iclass 6, count 0 2006.257.10:31:12.95#ibcon#read 6, iclass 6, count 0 2006.257.10:31:12.95#ibcon#end of sib2, iclass 6, count 0 2006.257.10:31:12.95#ibcon#*after write, iclass 6, count 0 2006.257.10:31:12.95#ibcon#*before return 0, iclass 6, count 0 2006.257.10:31:12.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:12.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:31:12.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.10:31:12.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.10:31:12.95$vck44/vblo=4,679.99 2006.257.10:31:12.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.10:31:12.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.10:31:12.95#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:12.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:12.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:12.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:12.95#ibcon#enter wrdev, iclass 10, count 0 2006.257.10:31:12.95#ibcon#first serial, iclass 10, count 0 2006.257.10:31:12.95#ibcon#enter sib2, iclass 10, count 0 2006.257.10:31:12.95#ibcon#flushed, iclass 10, count 0 2006.257.10:31:12.95#ibcon#about to write, iclass 10, count 0 2006.257.10:31:12.95#ibcon#wrote, iclass 10, count 0 2006.257.10:31:12.95#ibcon#about to read 3, iclass 10, count 0 2006.257.10:31:12.97#ibcon#read 3, iclass 10, count 0 2006.257.10:31:12.97#ibcon#about to read 4, iclass 10, count 0 2006.257.10:31:12.97#ibcon#read 4, iclass 10, count 0 2006.257.10:31:12.97#ibcon#about to read 5, iclass 10, count 0 2006.257.10:31:12.97#ibcon#read 5, iclass 10, count 0 2006.257.10:31:12.97#ibcon#about to read 6, iclass 10, count 0 2006.257.10:31:12.97#ibcon#read 6, iclass 10, count 0 2006.257.10:31:12.97#ibcon#end of sib2, iclass 10, count 0 2006.257.10:31:12.97#ibcon#*mode == 0, iclass 10, count 0 2006.257.10:31:12.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.10:31:12.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:31:12.97#ibcon#*before write, iclass 10, count 0 2006.257.10:31:12.97#ibcon#enter sib2, iclass 10, count 0 2006.257.10:31:12.97#ibcon#flushed, iclass 10, count 0 2006.257.10:31:12.97#ibcon#about to write, iclass 10, count 0 2006.257.10:31:12.97#ibcon#wrote, iclass 10, count 0 2006.257.10:31:12.97#ibcon#about to read 3, iclass 10, count 0 2006.257.10:31:13.01#ibcon#read 3, iclass 10, count 0 2006.257.10:31:13.01#ibcon#about to read 4, iclass 10, count 0 2006.257.10:31:13.01#ibcon#read 4, iclass 10, count 0 2006.257.10:31:13.01#ibcon#about to read 5, iclass 10, count 0 2006.257.10:31:13.01#ibcon#read 5, iclass 10, count 0 2006.257.10:31:13.01#ibcon#about to read 6, iclass 10, count 0 2006.257.10:31:13.01#ibcon#read 6, iclass 10, count 0 2006.257.10:31:13.01#ibcon#end of sib2, iclass 10, count 0 2006.257.10:31:13.01#ibcon#*after write, iclass 10, count 0 2006.257.10:31:13.01#ibcon#*before return 0, iclass 10, count 0 2006.257.10:31:13.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:13.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:31:13.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.10:31:13.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.10:31:13.01$vck44/vb=4,5 2006.257.10:31:13.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.10:31:13.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.10:31:13.01#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:13.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:13.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:13.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:13.07#ibcon#enter wrdev, iclass 12, count 2 2006.257.10:31:13.07#ibcon#first serial, iclass 12, count 2 2006.257.10:31:13.07#ibcon#enter sib2, iclass 12, count 2 2006.257.10:31:13.07#ibcon#flushed, iclass 12, count 2 2006.257.10:31:13.07#ibcon#about to write, iclass 12, count 2 2006.257.10:31:13.07#ibcon#wrote, iclass 12, count 2 2006.257.10:31:13.07#ibcon#about to read 3, iclass 12, count 2 2006.257.10:31:13.09#ibcon#read 3, iclass 12, count 2 2006.257.10:31:13.09#ibcon#about to read 4, iclass 12, count 2 2006.257.10:31:13.09#ibcon#read 4, iclass 12, count 2 2006.257.10:31:13.09#ibcon#about to read 5, iclass 12, count 2 2006.257.10:31:13.09#ibcon#read 5, iclass 12, count 2 2006.257.10:31:13.09#ibcon#about to read 6, iclass 12, count 2 2006.257.10:31:13.09#ibcon#read 6, iclass 12, count 2 2006.257.10:31:13.09#ibcon#end of sib2, iclass 12, count 2 2006.257.10:31:13.09#ibcon#*mode == 0, iclass 12, count 2 2006.257.10:31:13.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.10:31:13.09#ibcon#[27=AT04-05\r\n] 2006.257.10:31:13.09#ibcon#*before write, iclass 12, count 2 2006.257.10:31:13.09#ibcon#enter sib2, iclass 12, count 2 2006.257.10:31:13.09#ibcon#flushed, iclass 12, count 2 2006.257.10:31:13.09#ibcon#about to write, iclass 12, count 2 2006.257.10:31:13.09#ibcon#wrote, iclass 12, count 2 2006.257.10:31:13.09#ibcon#about to read 3, iclass 12, count 2 2006.257.10:31:13.12#ibcon#read 3, iclass 12, count 2 2006.257.10:31:13.12#ibcon#about to read 4, iclass 12, count 2 2006.257.10:31:13.12#ibcon#read 4, iclass 12, count 2 2006.257.10:31:13.12#ibcon#about to read 5, iclass 12, count 2 2006.257.10:31:13.12#ibcon#read 5, iclass 12, count 2 2006.257.10:31:13.12#ibcon#about to read 6, iclass 12, count 2 2006.257.10:31:13.12#ibcon#read 6, iclass 12, count 2 2006.257.10:31:13.12#ibcon#end of sib2, iclass 12, count 2 2006.257.10:31:13.12#ibcon#*after write, iclass 12, count 2 2006.257.10:31:13.12#ibcon#*before return 0, iclass 12, count 2 2006.257.10:31:13.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:13.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:31:13.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.10:31:13.12#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:13.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:13.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:13.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:13.24#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:31:13.24#ibcon#first serial, iclass 12, count 0 2006.257.10:31:13.24#ibcon#enter sib2, iclass 12, count 0 2006.257.10:31:13.24#ibcon#flushed, iclass 12, count 0 2006.257.10:31:13.24#ibcon#about to write, iclass 12, count 0 2006.257.10:31:13.24#ibcon#wrote, iclass 12, count 0 2006.257.10:31:13.24#ibcon#about to read 3, iclass 12, count 0 2006.257.10:31:13.26#ibcon#read 3, iclass 12, count 0 2006.257.10:31:13.26#ibcon#about to read 4, iclass 12, count 0 2006.257.10:31:13.26#ibcon#read 4, iclass 12, count 0 2006.257.10:31:13.26#ibcon#about to read 5, iclass 12, count 0 2006.257.10:31:13.26#ibcon#read 5, iclass 12, count 0 2006.257.10:31:13.26#ibcon#about to read 6, iclass 12, count 0 2006.257.10:31:13.26#ibcon#read 6, iclass 12, count 0 2006.257.10:31:13.26#ibcon#end of sib2, iclass 12, count 0 2006.257.10:31:13.26#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:31:13.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:31:13.26#ibcon#[27=USB\r\n] 2006.257.10:31:13.26#ibcon#*before write, iclass 12, count 0 2006.257.10:31:13.26#ibcon#enter sib2, iclass 12, count 0 2006.257.10:31:13.26#ibcon#flushed, iclass 12, count 0 2006.257.10:31:13.26#ibcon#about to write, iclass 12, count 0 2006.257.10:31:13.26#ibcon#wrote, iclass 12, count 0 2006.257.10:31:13.26#ibcon#about to read 3, iclass 12, count 0 2006.257.10:31:13.29#ibcon#read 3, iclass 12, count 0 2006.257.10:31:13.29#ibcon#about to read 4, iclass 12, count 0 2006.257.10:31:13.29#ibcon#read 4, iclass 12, count 0 2006.257.10:31:13.29#ibcon#about to read 5, iclass 12, count 0 2006.257.10:31:13.29#ibcon#read 5, iclass 12, count 0 2006.257.10:31:13.29#ibcon#about to read 6, iclass 12, count 0 2006.257.10:31:13.29#ibcon#read 6, iclass 12, count 0 2006.257.10:31:13.29#ibcon#end of sib2, iclass 12, count 0 2006.257.10:31:13.29#ibcon#*after write, iclass 12, count 0 2006.257.10:31:13.29#ibcon#*before return 0, iclass 12, count 0 2006.257.10:31:13.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:13.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:31:13.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:31:13.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:31:13.29$vck44/vblo=5,709.99 2006.257.10:31:13.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.10:31:13.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.10:31:13.29#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:13.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:13.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:13.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:13.29#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:31:13.29#ibcon#first serial, iclass 14, count 0 2006.257.10:31:13.29#ibcon#enter sib2, iclass 14, count 0 2006.257.10:31:13.29#ibcon#flushed, iclass 14, count 0 2006.257.10:31:13.29#ibcon#about to write, iclass 14, count 0 2006.257.10:31:13.29#ibcon#wrote, iclass 14, count 0 2006.257.10:31:13.29#ibcon#about to read 3, iclass 14, count 0 2006.257.10:31:13.31#ibcon#read 3, iclass 14, count 0 2006.257.10:31:13.31#ibcon#about to read 4, iclass 14, count 0 2006.257.10:31:13.31#ibcon#read 4, iclass 14, count 0 2006.257.10:31:13.31#ibcon#about to read 5, iclass 14, count 0 2006.257.10:31:13.31#ibcon#read 5, iclass 14, count 0 2006.257.10:31:13.31#ibcon#about to read 6, iclass 14, count 0 2006.257.10:31:13.31#ibcon#read 6, iclass 14, count 0 2006.257.10:31:13.31#ibcon#end of sib2, iclass 14, count 0 2006.257.10:31:13.31#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:31:13.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:31:13.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:31:13.31#ibcon#*before write, iclass 14, count 0 2006.257.10:31:13.31#ibcon#enter sib2, iclass 14, count 0 2006.257.10:31:13.31#ibcon#flushed, iclass 14, count 0 2006.257.10:31:13.31#ibcon#about to write, iclass 14, count 0 2006.257.10:31:13.31#ibcon#wrote, iclass 14, count 0 2006.257.10:31:13.31#ibcon#about to read 3, iclass 14, count 0 2006.257.10:31:13.35#ibcon#read 3, iclass 14, count 0 2006.257.10:31:13.35#ibcon#about to read 4, iclass 14, count 0 2006.257.10:31:13.35#ibcon#read 4, iclass 14, count 0 2006.257.10:31:13.35#ibcon#about to read 5, iclass 14, count 0 2006.257.10:31:13.35#ibcon#read 5, iclass 14, count 0 2006.257.10:31:13.35#ibcon#about to read 6, iclass 14, count 0 2006.257.10:31:13.35#ibcon#read 6, iclass 14, count 0 2006.257.10:31:13.35#ibcon#end of sib2, iclass 14, count 0 2006.257.10:31:13.35#ibcon#*after write, iclass 14, count 0 2006.257.10:31:13.35#ibcon#*before return 0, iclass 14, count 0 2006.257.10:31:13.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:13.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:31:13.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:31:13.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:31:13.35$vck44/vb=5,4 2006.257.10:31:13.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.10:31:13.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.10:31:13.35#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:13.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:13.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:13.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:13.41#ibcon#enter wrdev, iclass 16, count 2 2006.257.10:31:13.41#ibcon#first serial, iclass 16, count 2 2006.257.10:31:13.41#ibcon#enter sib2, iclass 16, count 2 2006.257.10:31:13.41#ibcon#flushed, iclass 16, count 2 2006.257.10:31:13.41#ibcon#about to write, iclass 16, count 2 2006.257.10:31:13.41#ibcon#wrote, iclass 16, count 2 2006.257.10:31:13.41#ibcon#about to read 3, iclass 16, count 2 2006.257.10:31:13.43#ibcon#read 3, iclass 16, count 2 2006.257.10:31:13.43#ibcon#about to read 4, iclass 16, count 2 2006.257.10:31:13.43#ibcon#read 4, iclass 16, count 2 2006.257.10:31:13.43#ibcon#about to read 5, iclass 16, count 2 2006.257.10:31:13.43#ibcon#read 5, iclass 16, count 2 2006.257.10:31:13.43#ibcon#about to read 6, iclass 16, count 2 2006.257.10:31:13.43#ibcon#read 6, iclass 16, count 2 2006.257.10:31:13.43#ibcon#end of sib2, iclass 16, count 2 2006.257.10:31:13.43#ibcon#*mode == 0, iclass 16, count 2 2006.257.10:31:13.43#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.10:31:13.43#ibcon#[27=AT05-04\r\n] 2006.257.10:31:13.43#ibcon#*before write, iclass 16, count 2 2006.257.10:31:13.43#ibcon#enter sib2, iclass 16, count 2 2006.257.10:31:13.43#ibcon#flushed, iclass 16, count 2 2006.257.10:31:13.43#ibcon#about to write, iclass 16, count 2 2006.257.10:31:13.43#ibcon#wrote, iclass 16, count 2 2006.257.10:31:13.43#ibcon#about to read 3, iclass 16, count 2 2006.257.10:31:13.46#ibcon#read 3, iclass 16, count 2 2006.257.10:31:13.46#ibcon#about to read 4, iclass 16, count 2 2006.257.10:31:13.46#ibcon#read 4, iclass 16, count 2 2006.257.10:31:13.46#ibcon#about to read 5, iclass 16, count 2 2006.257.10:31:13.46#ibcon#read 5, iclass 16, count 2 2006.257.10:31:13.46#ibcon#about to read 6, iclass 16, count 2 2006.257.10:31:13.46#ibcon#read 6, iclass 16, count 2 2006.257.10:31:13.46#ibcon#end of sib2, iclass 16, count 2 2006.257.10:31:13.46#ibcon#*after write, iclass 16, count 2 2006.257.10:31:13.46#ibcon#*before return 0, iclass 16, count 2 2006.257.10:31:13.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:13.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:31:13.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.10:31:13.46#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:13.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:13.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:13.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:13.58#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:31:13.58#ibcon#first serial, iclass 16, count 0 2006.257.10:31:13.58#ibcon#enter sib2, iclass 16, count 0 2006.257.10:31:13.58#ibcon#flushed, iclass 16, count 0 2006.257.10:31:13.58#ibcon#about to write, iclass 16, count 0 2006.257.10:31:13.58#ibcon#wrote, iclass 16, count 0 2006.257.10:31:13.58#ibcon#about to read 3, iclass 16, count 0 2006.257.10:31:13.60#ibcon#read 3, iclass 16, count 0 2006.257.10:31:13.60#ibcon#about to read 4, iclass 16, count 0 2006.257.10:31:13.60#ibcon#read 4, iclass 16, count 0 2006.257.10:31:13.60#ibcon#about to read 5, iclass 16, count 0 2006.257.10:31:13.60#ibcon#read 5, iclass 16, count 0 2006.257.10:31:13.60#ibcon#about to read 6, iclass 16, count 0 2006.257.10:31:13.60#ibcon#read 6, iclass 16, count 0 2006.257.10:31:13.60#ibcon#end of sib2, iclass 16, count 0 2006.257.10:31:13.60#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:31:13.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:31:13.60#ibcon#[27=USB\r\n] 2006.257.10:31:13.60#ibcon#*before write, iclass 16, count 0 2006.257.10:31:13.60#ibcon#enter sib2, iclass 16, count 0 2006.257.10:31:13.60#ibcon#flushed, iclass 16, count 0 2006.257.10:31:13.60#ibcon#about to write, iclass 16, count 0 2006.257.10:31:13.60#ibcon#wrote, iclass 16, count 0 2006.257.10:31:13.60#ibcon#about to read 3, iclass 16, count 0 2006.257.10:31:13.63#ibcon#read 3, iclass 16, count 0 2006.257.10:31:13.63#ibcon#about to read 4, iclass 16, count 0 2006.257.10:31:13.63#ibcon#read 4, iclass 16, count 0 2006.257.10:31:13.63#ibcon#about to read 5, iclass 16, count 0 2006.257.10:31:13.63#ibcon#read 5, iclass 16, count 0 2006.257.10:31:13.63#ibcon#about to read 6, iclass 16, count 0 2006.257.10:31:13.63#ibcon#read 6, iclass 16, count 0 2006.257.10:31:13.63#ibcon#end of sib2, iclass 16, count 0 2006.257.10:31:13.63#ibcon#*after write, iclass 16, count 0 2006.257.10:31:13.63#ibcon#*before return 0, iclass 16, count 0 2006.257.10:31:13.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:13.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:31:13.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:31:13.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:31:13.63$vck44/vblo=6,719.99 2006.257.10:31:13.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.10:31:13.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.10:31:13.63#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:13.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:13.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:13.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:13.63#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:31:13.63#ibcon#first serial, iclass 18, count 0 2006.257.10:31:13.63#ibcon#enter sib2, iclass 18, count 0 2006.257.10:31:13.63#ibcon#flushed, iclass 18, count 0 2006.257.10:31:13.63#ibcon#about to write, iclass 18, count 0 2006.257.10:31:13.63#ibcon#wrote, iclass 18, count 0 2006.257.10:31:13.63#ibcon#about to read 3, iclass 18, count 0 2006.257.10:31:13.65#ibcon#read 3, iclass 18, count 0 2006.257.10:31:13.65#ibcon#about to read 4, iclass 18, count 0 2006.257.10:31:13.65#ibcon#read 4, iclass 18, count 0 2006.257.10:31:13.65#ibcon#about to read 5, iclass 18, count 0 2006.257.10:31:13.65#ibcon#read 5, iclass 18, count 0 2006.257.10:31:13.65#ibcon#about to read 6, iclass 18, count 0 2006.257.10:31:13.65#ibcon#read 6, iclass 18, count 0 2006.257.10:31:13.65#ibcon#end of sib2, iclass 18, count 0 2006.257.10:31:13.65#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:31:13.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:31:13.65#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:31:13.65#ibcon#*before write, iclass 18, count 0 2006.257.10:31:13.65#ibcon#enter sib2, iclass 18, count 0 2006.257.10:31:13.65#ibcon#flushed, iclass 18, count 0 2006.257.10:31:13.65#ibcon#about to write, iclass 18, count 0 2006.257.10:31:13.65#ibcon#wrote, iclass 18, count 0 2006.257.10:31:13.65#ibcon#about to read 3, iclass 18, count 0 2006.257.10:31:13.69#ibcon#read 3, iclass 18, count 0 2006.257.10:31:13.69#ibcon#about to read 4, iclass 18, count 0 2006.257.10:31:13.69#ibcon#read 4, iclass 18, count 0 2006.257.10:31:13.69#ibcon#about to read 5, iclass 18, count 0 2006.257.10:31:13.69#ibcon#read 5, iclass 18, count 0 2006.257.10:31:13.69#ibcon#about to read 6, iclass 18, count 0 2006.257.10:31:13.69#ibcon#read 6, iclass 18, count 0 2006.257.10:31:13.69#ibcon#end of sib2, iclass 18, count 0 2006.257.10:31:13.69#ibcon#*after write, iclass 18, count 0 2006.257.10:31:13.69#ibcon#*before return 0, iclass 18, count 0 2006.257.10:31:13.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:13.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:31:13.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:31:13.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:31:13.69$vck44/vb=6,4 2006.257.10:31:13.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.10:31:13.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.10:31:13.69#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:13.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:13.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:13.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:13.75#ibcon#enter wrdev, iclass 20, count 2 2006.257.10:31:13.75#ibcon#first serial, iclass 20, count 2 2006.257.10:31:13.75#ibcon#enter sib2, iclass 20, count 2 2006.257.10:31:13.75#ibcon#flushed, iclass 20, count 2 2006.257.10:31:13.75#ibcon#about to write, iclass 20, count 2 2006.257.10:31:13.75#ibcon#wrote, iclass 20, count 2 2006.257.10:31:13.75#ibcon#about to read 3, iclass 20, count 2 2006.257.10:31:13.77#ibcon#read 3, iclass 20, count 2 2006.257.10:31:13.77#ibcon#about to read 4, iclass 20, count 2 2006.257.10:31:13.77#ibcon#read 4, iclass 20, count 2 2006.257.10:31:13.77#ibcon#about to read 5, iclass 20, count 2 2006.257.10:31:13.77#ibcon#read 5, iclass 20, count 2 2006.257.10:31:13.77#ibcon#about to read 6, iclass 20, count 2 2006.257.10:31:13.77#ibcon#read 6, iclass 20, count 2 2006.257.10:31:13.77#ibcon#end of sib2, iclass 20, count 2 2006.257.10:31:13.77#ibcon#*mode == 0, iclass 20, count 2 2006.257.10:31:13.77#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.10:31:13.77#ibcon#[27=AT06-04\r\n] 2006.257.10:31:13.77#ibcon#*before write, iclass 20, count 2 2006.257.10:31:13.77#ibcon#enter sib2, iclass 20, count 2 2006.257.10:31:13.77#ibcon#flushed, iclass 20, count 2 2006.257.10:31:13.77#ibcon#about to write, iclass 20, count 2 2006.257.10:31:13.77#ibcon#wrote, iclass 20, count 2 2006.257.10:31:13.77#ibcon#about to read 3, iclass 20, count 2 2006.257.10:31:13.80#ibcon#read 3, iclass 20, count 2 2006.257.10:31:13.80#ibcon#about to read 4, iclass 20, count 2 2006.257.10:31:13.80#ibcon#read 4, iclass 20, count 2 2006.257.10:31:13.80#ibcon#about to read 5, iclass 20, count 2 2006.257.10:31:13.80#ibcon#read 5, iclass 20, count 2 2006.257.10:31:13.80#ibcon#about to read 6, iclass 20, count 2 2006.257.10:31:13.80#ibcon#read 6, iclass 20, count 2 2006.257.10:31:13.80#ibcon#end of sib2, iclass 20, count 2 2006.257.10:31:13.80#ibcon#*after write, iclass 20, count 2 2006.257.10:31:13.80#ibcon#*before return 0, iclass 20, count 2 2006.257.10:31:13.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:13.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:31:13.80#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.10:31:13.80#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:13.80#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:13.92#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:13.92#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:13.92#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:31:13.92#ibcon#first serial, iclass 20, count 0 2006.257.10:31:13.92#ibcon#enter sib2, iclass 20, count 0 2006.257.10:31:13.92#ibcon#flushed, iclass 20, count 0 2006.257.10:31:13.92#ibcon#about to write, iclass 20, count 0 2006.257.10:31:13.92#ibcon#wrote, iclass 20, count 0 2006.257.10:31:13.92#ibcon#about to read 3, iclass 20, count 0 2006.257.10:31:13.94#ibcon#read 3, iclass 20, count 0 2006.257.10:31:13.94#ibcon#about to read 4, iclass 20, count 0 2006.257.10:31:13.94#ibcon#read 4, iclass 20, count 0 2006.257.10:31:13.94#ibcon#about to read 5, iclass 20, count 0 2006.257.10:31:13.94#ibcon#read 5, iclass 20, count 0 2006.257.10:31:13.94#ibcon#about to read 6, iclass 20, count 0 2006.257.10:31:13.94#ibcon#read 6, iclass 20, count 0 2006.257.10:31:13.94#ibcon#end of sib2, iclass 20, count 0 2006.257.10:31:13.94#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:31:13.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:31:13.94#ibcon#[27=USB\r\n] 2006.257.10:31:13.94#ibcon#*before write, iclass 20, count 0 2006.257.10:31:13.94#ibcon#enter sib2, iclass 20, count 0 2006.257.10:31:13.94#ibcon#flushed, iclass 20, count 0 2006.257.10:31:13.94#ibcon#about to write, iclass 20, count 0 2006.257.10:31:13.94#ibcon#wrote, iclass 20, count 0 2006.257.10:31:13.94#ibcon#about to read 3, iclass 20, count 0 2006.257.10:31:13.97#ibcon#read 3, iclass 20, count 0 2006.257.10:31:13.97#ibcon#about to read 4, iclass 20, count 0 2006.257.10:31:13.97#ibcon#read 4, iclass 20, count 0 2006.257.10:31:13.97#ibcon#about to read 5, iclass 20, count 0 2006.257.10:31:13.97#ibcon#read 5, iclass 20, count 0 2006.257.10:31:13.97#ibcon#about to read 6, iclass 20, count 0 2006.257.10:31:13.97#ibcon#read 6, iclass 20, count 0 2006.257.10:31:13.97#ibcon#end of sib2, iclass 20, count 0 2006.257.10:31:13.97#ibcon#*after write, iclass 20, count 0 2006.257.10:31:13.97#ibcon#*before return 0, iclass 20, count 0 2006.257.10:31:13.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:13.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:31:13.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:31:13.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:31:13.97$vck44/vblo=7,734.99 2006.257.10:31:13.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.10:31:13.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.10:31:13.97#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:13.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:13.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:13.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:13.97#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:31:13.97#ibcon#first serial, iclass 22, count 0 2006.257.10:31:13.97#ibcon#enter sib2, iclass 22, count 0 2006.257.10:31:13.97#ibcon#flushed, iclass 22, count 0 2006.257.10:31:13.97#ibcon#about to write, iclass 22, count 0 2006.257.10:31:13.97#ibcon#wrote, iclass 22, count 0 2006.257.10:31:13.97#ibcon#about to read 3, iclass 22, count 0 2006.257.10:31:13.99#ibcon#read 3, iclass 22, count 0 2006.257.10:31:13.99#ibcon#about to read 4, iclass 22, count 0 2006.257.10:31:13.99#ibcon#read 4, iclass 22, count 0 2006.257.10:31:13.99#ibcon#about to read 5, iclass 22, count 0 2006.257.10:31:13.99#ibcon#read 5, iclass 22, count 0 2006.257.10:31:13.99#ibcon#about to read 6, iclass 22, count 0 2006.257.10:31:13.99#ibcon#read 6, iclass 22, count 0 2006.257.10:31:13.99#ibcon#end of sib2, iclass 22, count 0 2006.257.10:31:13.99#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:31:13.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:31:13.99#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:31:13.99#ibcon#*before write, iclass 22, count 0 2006.257.10:31:13.99#ibcon#enter sib2, iclass 22, count 0 2006.257.10:31:13.99#ibcon#flushed, iclass 22, count 0 2006.257.10:31:13.99#ibcon#about to write, iclass 22, count 0 2006.257.10:31:13.99#ibcon#wrote, iclass 22, count 0 2006.257.10:31:13.99#ibcon#about to read 3, iclass 22, count 0 2006.257.10:31:14.03#ibcon#read 3, iclass 22, count 0 2006.257.10:31:14.03#ibcon#about to read 4, iclass 22, count 0 2006.257.10:31:14.03#ibcon#read 4, iclass 22, count 0 2006.257.10:31:14.03#ibcon#about to read 5, iclass 22, count 0 2006.257.10:31:14.03#ibcon#read 5, iclass 22, count 0 2006.257.10:31:14.03#ibcon#about to read 6, iclass 22, count 0 2006.257.10:31:14.03#ibcon#read 6, iclass 22, count 0 2006.257.10:31:14.03#ibcon#end of sib2, iclass 22, count 0 2006.257.10:31:14.03#ibcon#*after write, iclass 22, count 0 2006.257.10:31:14.03#ibcon#*before return 0, iclass 22, count 0 2006.257.10:31:14.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:14.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:31:14.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:31:14.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:31:14.03$vck44/vb=7,4 2006.257.10:31:14.03#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.10:31:14.03#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.10:31:14.03#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:14.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:14.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:14.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:14.09#ibcon#enter wrdev, iclass 24, count 2 2006.257.10:31:14.09#ibcon#first serial, iclass 24, count 2 2006.257.10:31:14.09#ibcon#enter sib2, iclass 24, count 2 2006.257.10:31:14.09#ibcon#flushed, iclass 24, count 2 2006.257.10:31:14.09#ibcon#about to write, iclass 24, count 2 2006.257.10:31:14.09#ibcon#wrote, iclass 24, count 2 2006.257.10:31:14.09#ibcon#about to read 3, iclass 24, count 2 2006.257.10:31:14.11#ibcon#read 3, iclass 24, count 2 2006.257.10:31:14.11#ibcon#about to read 4, iclass 24, count 2 2006.257.10:31:14.11#ibcon#read 4, iclass 24, count 2 2006.257.10:31:14.11#ibcon#about to read 5, iclass 24, count 2 2006.257.10:31:14.11#ibcon#read 5, iclass 24, count 2 2006.257.10:31:14.11#ibcon#about to read 6, iclass 24, count 2 2006.257.10:31:14.11#ibcon#read 6, iclass 24, count 2 2006.257.10:31:14.11#ibcon#end of sib2, iclass 24, count 2 2006.257.10:31:14.11#ibcon#*mode == 0, iclass 24, count 2 2006.257.10:31:14.11#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.10:31:14.11#ibcon#[27=AT07-04\r\n] 2006.257.10:31:14.11#ibcon#*before write, iclass 24, count 2 2006.257.10:31:14.11#ibcon#enter sib2, iclass 24, count 2 2006.257.10:31:14.11#ibcon#flushed, iclass 24, count 2 2006.257.10:31:14.11#ibcon#about to write, iclass 24, count 2 2006.257.10:31:14.11#ibcon#wrote, iclass 24, count 2 2006.257.10:31:14.11#ibcon#about to read 3, iclass 24, count 2 2006.257.10:31:14.14#ibcon#read 3, iclass 24, count 2 2006.257.10:31:14.14#ibcon#about to read 4, iclass 24, count 2 2006.257.10:31:14.14#ibcon#read 4, iclass 24, count 2 2006.257.10:31:14.14#ibcon#about to read 5, iclass 24, count 2 2006.257.10:31:14.14#ibcon#read 5, iclass 24, count 2 2006.257.10:31:14.14#ibcon#about to read 6, iclass 24, count 2 2006.257.10:31:14.14#ibcon#read 6, iclass 24, count 2 2006.257.10:31:14.14#ibcon#end of sib2, iclass 24, count 2 2006.257.10:31:14.14#ibcon#*after write, iclass 24, count 2 2006.257.10:31:14.14#ibcon#*before return 0, iclass 24, count 2 2006.257.10:31:14.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:14.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:31:14.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.10:31:14.14#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:14.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:14.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:14.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:14.26#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:31:14.26#ibcon#first serial, iclass 24, count 0 2006.257.10:31:14.26#ibcon#enter sib2, iclass 24, count 0 2006.257.10:31:14.26#ibcon#flushed, iclass 24, count 0 2006.257.10:31:14.26#ibcon#about to write, iclass 24, count 0 2006.257.10:31:14.26#ibcon#wrote, iclass 24, count 0 2006.257.10:31:14.26#ibcon#about to read 3, iclass 24, count 0 2006.257.10:31:14.28#ibcon#read 3, iclass 24, count 0 2006.257.10:31:14.28#ibcon#about to read 4, iclass 24, count 0 2006.257.10:31:14.28#ibcon#read 4, iclass 24, count 0 2006.257.10:31:14.28#ibcon#about to read 5, iclass 24, count 0 2006.257.10:31:14.28#ibcon#read 5, iclass 24, count 0 2006.257.10:31:14.28#ibcon#about to read 6, iclass 24, count 0 2006.257.10:31:14.28#ibcon#read 6, iclass 24, count 0 2006.257.10:31:14.28#ibcon#end of sib2, iclass 24, count 0 2006.257.10:31:14.28#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:31:14.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:31:14.28#ibcon#[27=USB\r\n] 2006.257.10:31:14.28#ibcon#*before write, iclass 24, count 0 2006.257.10:31:14.28#ibcon#enter sib2, iclass 24, count 0 2006.257.10:31:14.28#ibcon#flushed, iclass 24, count 0 2006.257.10:31:14.28#ibcon#about to write, iclass 24, count 0 2006.257.10:31:14.28#ibcon#wrote, iclass 24, count 0 2006.257.10:31:14.28#ibcon#about to read 3, iclass 24, count 0 2006.257.10:31:14.31#ibcon#read 3, iclass 24, count 0 2006.257.10:31:14.31#ibcon#about to read 4, iclass 24, count 0 2006.257.10:31:14.31#ibcon#read 4, iclass 24, count 0 2006.257.10:31:14.31#ibcon#about to read 5, iclass 24, count 0 2006.257.10:31:14.31#ibcon#read 5, iclass 24, count 0 2006.257.10:31:14.31#ibcon#about to read 6, iclass 24, count 0 2006.257.10:31:14.31#ibcon#read 6, iclass 24, count 0 2006.257.10:31:14.31#ibcon#end of sib2, iclass 24, count 0 2006.257.10:31:14.31#ibcon#*after write, iclass 24, count 0 2006.257.10:31:14.31#ibcon#*before return 0, iclass 24, count 0 2006.257.10:31:14.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:14.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:31:14.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:31:14.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:31:14.31$vck44/vblo=8,744.99 2006.257.10:31:14.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.10:31:14.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.10:31:14.31#ibcon#ireg 17 cls_cnt 0 2006.257.10:31:14.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:14.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:14.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:14.31#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:31:14.31#ibcon#first serial, iclass 26, count 0 2006.257.10:31:14.31#ibcon#enter sib2, iclass 26, count 0 2006.257.10:31:14.31#ibcon#flushed, iclass 26, count 0 2006.257.10:31:14.31#ibcon#about to write, iclass 26, count 0 2006.257.10:31:14.31#ibcon#wrote, iclass 26, count 0 2006.257.10:31:14.31#ibcon#about to read 3, iclass 26, count 0 2006.257.10:31:14.33#ibcon#read 3, iclass 26, count 0 2006.257.10:31:14.33#ibcon#about to read 4, iclass 26, count 0 2006.257.10:31:14.33#ibcon#read 4, iclass 26, count 0 2006.257.10:31:14.33#ibcon#about to read 5, iclass 26, count 0 2006.257.10:31:14.33#ibcon#read 5, iclass 26, count 0 2006.257.10:31:14.33#ibcon#about to read 6, iclass 26, count 0 2006.257.10:31:14.33#ibcon#read 6, iclass 26, count 0 2006.257.10:31:14.33#ibcon#end of sib2, iclass 26, count 0 2006.257.10:31:14.33#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:31:14.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:31:14.33#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:31:14.33#ibcon#*before write, iclass 26, count 0 2006.257.10:31:14.33#ibcon#enter sib2, iclass 26, count 0 2006.257.10:31:14.33#ibcon#flushed, iclass 26, count 0 2006.257.10:31:14.33#ibcon#about to write, iclass 26, count 0 2006.257.10:31:14.33#ibcon#wrote, iclass 26, count 0 2006.257.10:31:14.33#ibcon#about to read 3, iclass 26, count 0 2006.257.10:31:14.37#ibcon#read 3, iclass 26, count 0 2006.257.10:31:14.37#ibcon#about to read 4, iclass 26, count 0 2006.257.10:31:14.37#ibcon#read 4, iclass 26, count 0 2006.257.10:31:14.37#ibcon#about to read 5, iclass 26, count 0 2006.257.10:31:14.37#ibcon#read 5, iclass 26, count 0 2006.257.10:31:14.37#ibcon#about to read 6, iclass 26, count 0 2006.257.10:31:14.37#ibcon#read 6, iclass 26, count 0 2006.257.10:31:14.37#ibcon#end of sib2, iclass 26, count 0 2006.257.10:31:14.37#ibcon#*after write, iclass 26, count 0 2006.257.10:31:14.37#ibcon#*before return 0, iclass 26, count 0 2006.257.10:31:14.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:14.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:31:14.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:31:14.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:31:14.37$vck44/vb=8,4 2006.257.10:31:14.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.10:31:14.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.10:31:14.37#ibcon#ireg 11 cls_cnt 2 2006.257.10:31:14.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:14.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:14.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:14.43#ibcon#enter wrdev, iclass 28, count 2 2006.257.10:31:14.43#ibcon#first serial, iclass 28, count 2 2006.257.10:31:14.43#ibcon#enter sib2, iclass 28, count 2 2006.257.10:31:14.43#ibcon#flushed, iclass 28, count 2 2006.257.10:31:14.43#ibcon#about to write, iclass 28, count 2 2006.257.10:31:14.43#ibcon#wrote, iclass 28, count 2 2006.257.10:31:14.43#ibcon#about to read 3, iclass 28, count 2 2006.257.10:31:14.45#ibcon#read 3, iclass 28, count 2 2006.257.10:31:14.45#ibcon#about to read 4, iclass 28, count 2 2006.257.10:31:14.45#ibcon#read 4, iclass 28, count 2 2006.257.10:31:14.45#ibcon#about to read 5, iclass 28, count 2 2006.257.10:31:14.45#ibcon#read 5, iclass 28, count 2 2006.257.10:31:14.45#ibcon#about to read 6, iclass 28, count 2 2006.257.10:31:14.45#ibcon#read 6, iclass 28, count 2 2006.257.10:31:14.45#ibcon#end of sib2, iclass 28, count 2 2006.257.10:31:14.45#ibcon#*mode == 0, iclass 28, count 2 2006.257.10:31:14.45#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.10:31:14.45#ibcon#[27=AT08-04\r\n] 2006.257.10:31:14.45#ibcon#*before write, iclass 28, count 2 2006.257.10:31:14.45#ibcon#enter sib2, iclass 28, count 2 2006.257.10:31:14.45#ibcon#flushed, iclass 28, count 2 2006.257.10:31:14.45#ibcon#about to write, iclass 28, count 2 2006.257.10:31:14.45#ibcon#wrote, iclass 28, count 2 2006.257.10:31:14.45#ibcon#about to read 3, iclass 28, count 2 2006.257.10:31:14.48#ibcon#read 3, iclass 28, count 2 2006.257.10:31:14.48#ibcon#about to read 4, iclass 28, count 2 2006.257.10:31:14.48#ibcon#read 4, iclass 28, count 2 2006.257.10:31:14.48#ibcon#about to read 5, iclass 28, count 2 2006.257.10:31:14.48#ibcon#read 5, iclass 28, count 2 2006.257.10:31:14.48#ibcon#about to read 6, iclass 28, count 2 2006.257.10:31:14.48#ibcon#read 6, iclass 28, count 2 2006.257.10:31:14.48#ibcon#end of sib2, iclass 28, count 2 2006.257.10:31:14.48#ibcon#*after write, iclass 28, count 2 2006.257.10:31:14.48#ibcon#*before return 0, iclass 28, count 2 2006.257.10:31:14.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:14.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:31:14.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.10:31:14.48#ibcon#ireg 7 cls_cnt 0 2006.257.10:31:14.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:14.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:14.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:14.60#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:31:14.60#ibcon#first serial, iclass 28, count 0 2006.257.10:31:14.60#ibcon#enter sib2, iclass 28, count 0 2006.257.10:31:14.60#ibcon#flushed, iclass 28, count 0 2006.257.10:31:14.60#ibcon#about to write, iclass 28, count 0 2006.257.10:31:14.60#ibcon#wrote, iclass 28, count 0 2006.257.10:31:14.60#ibcon#about to read 3, iclass 28, count 0 2006.257.10:31:14.62#ibcon#read 3, iclass 28, count 0 2006.257.10:31:14.62#ibcon#about to read 4, iclass 28, count 0 2006.257.10:31:14.62#ibcon#read 4, iclass 28, count 0 2006.257.10:31:14.62#ibcon#about to read 5, iclass 28, count 0 2006.257.10:31:14.62#ibcon#read 5, iclass 28, count 0 2006.257.10:31:14.62#ibcon#about to read 6, iclass 28, count 0 2006.257.10:31:14.62#ibcon#read 6, iclass 28, count 0 2006.257.10:31:14.62#ibcon#end of sib2, iclass 28, count 0 2006.257.10:31:14.62#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:31:14.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:31:14.62#ibcon#[27=USB\r\n] 2006.257.10:31:14.62#ibcon#*before write, iclass 28, count 0 2006.257.10:31:14.62#ibcon#enter sib2, iclass 28, count 0 2006.257.10:31:14.62#ibcon#flushed, iclass 28, count 0 2006.257.10:31:14.62#ibcon#about to write, iclass 28, count 0 2006.257.10:31:14.62#ibcon#wrote, iclass 28, count 0 2006.257.10:31:14.62#ibcon#about to read 3, iclass 28, count 0 2006.257.10:31:14.65#ibcon#read 3, iclass 28, count 0 2006.257.10:31:14.65#ibcon#about to read 4, iclass 28, count 0 2006.257.10:31:14.65#ibcon#read 4, iclass 28, count 0 2006.257.10:31:14.65#ibcon#about to read 5, iclass 28, count 0 2006.257.10:31:14.65#ibcon#read 5, iclass 28, count 0 2006.257.10:31:14.65#ibcon#about to read 6, iclass 28, count 0 2006.257.10:31:14.65#ibcon#read 6, iclass 28, count 0 2006.257.10:31:14.65#ibcon#end of sib2, iclass 28, count 0 2006.257.10:31:14.65#ibcon#*after write, iclass 28, count 0 2006.257.10:31:14.65#ibcon#*before return 0, iclass 28, count 0 2006.257.10:31:14.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:14.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:31:14.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:31:14.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:31:14.65$vck44/vabw=wide 2006.257.10:31:14.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.10:31:14.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.10:31:14.65#ibcon#ireg 8 cls_cnt 0 2006.257.10:31:14.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:14.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:14.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:14.65#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:31:14.65#ibcon#first serial, iclass 30, count 0 2006.257.10:31:14.65#ibcon#enter sib2, iclass 30, count 0 2006.257.10:31:14.65#ibcon#flushed, iclass 30, count 0 2006.257.10:31:14.65#ibcon#about to write, iclass 30, count 0 2006.257.10:31:14.65#ibcon#wrote, iclass 30, count 0 2006.257.10:31:14.65#ibcon#about to read 3, iclass 30, count 0 2006.257.10:31:14.67#ibcon#read 3, iclass 30, count 0 2006.257.10:31:14.67#ibcon#about to read 4, iclass 30, count 0 2006.257.10:31:14.67#ibcon#read 4, iclass 30, count 0 2006.257.10:31:14.67#ibcon#about to read 5, iclass 30, count 0 2006.257.10:31:14.67#ibcon#read 5, iclass 30, count 0 2006.257.10:31:14.67#ibcon#about to read 6, iclass 30, count 0 2006.257.10:31:14.67#ibcon#read 6, iclass 30, count 0 2006.257.10:31:14.67#ibcon#end of sib2, iclass 30, count 0 2006.257.10:31:14.67#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:31:14.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:31:14.67#ibcon#[25=BW32\r\n] 2006.257.10:31:14.67#ibcon#*before write, iclass 30, count 0 2006.257.10:31:14.67#ibcon#enter sib2, iclass 30, count 0 2006.257.10:31:14.67#ibcon#flushed, iclass 30, count 0 2006.257.10:31:14.67#ibcon#about to write, iclass 30, count 0 2006.257.10:31:14.67#ibcon#wrote, iclass 30, count 0 2006.257.10:31:14.67#ibcon#about to read 3, iclass 30, count 0 2006.257.10:31:14.70#ibcon#read 3, iclass 30, count 0 2006.257.10:31:14.70#ibcon#about to read 4, iclass 30, count 0 2006.257.10:31:14.70#ibcon#read 4, iclass 30, count 0 2006.257.10:31:14.70#ibcon#about to read 5, iclass 30, count 0 2006.257.10:31:14.70#ibcon#read 5, iclass 30, count 0 2006.257.10:31:14.70#ibcon#about to read 6, iclass 30, count 0 2006.257.10:31:14.70#ibcon#read 6, iclass 30, count 0 2006.257.10:31:14.70#ibcon#end of sib2, iclass 30, count 0 2006.257.10:31:14.70#ibcon#*after write, iclass 30, count 0 2006.257.10:31:14.70#ibcon#*before return 0, iclass 30, count 0 2006.257.10:31:14.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:14.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:31:14.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:31:14.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:31:14.70$vck44/vbbw=wide 2006.257.10:31:14.70#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.10:31:14.70#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.10:31:14.70#ibcon#ireg 8 cls_cnt 0 2006.257.10:31:14.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:31:14.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:31:14.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:31:14.77#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:31:14.77#ibcon#first serial, iclass 32, count 0 2006.257.10:31:14.77#ibcon#enter sib2, iclass 32, count 0 2006.257.10:31:14.77#ibcon#flushed, iclass 32, count 0 2006.257.10:31:14.77#ibcon#about to write, iclass 32, count 0 2006.257.10:31:14.77#ibcon#wrote, iclass 32, count 0 2006.257.10:31:14.77#ibcon#about to read 3, iclass 32, count 0 2006.257.10:31:14.79#ibcon#read 3, iclass 32, count 0 2006.257.10:31:14.79#ibcon#about to read 4, iclass 32, count 0 2006.257.10:31:14.79#ibcon#read 4, iclass 32, count 0 2006.257.10:31:14.79#ibcon#about to read 5, iclass 32, count 0 2006.257.10:31:14.79#ibcon#read 5, iclass 32, count 0 2006.257.10:31:14.79#ibcon#about to read 6, iclass 32, count 0 2006.257.10:31:14.79#ibcon#read 6, iclass 32, count 0 2006.257.10:31:14.79#ibcon#end of sib2, iclass 32, count 0 2006.257.10:31:14.79#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:31:14.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:31:14.79#ibcon#[27=BW32\r\n] 2006.257.10:31:14.79#ibcon#*before write, iclass 32, count 0 2006.257.10:31:14.79#ibcon#enter sib2, iclass 32, count 0 2006.257.10:31:14.79#ibcon#flushed, iclass 32, count 0 2006.257.10:31:14.79#ibcon#about to write, iclass 32, count 0 2006.257.10:31:14.79#ibcon#wrote, iclass 32, count 0 2006.257.10:31:14.79#ibcon#about to read 3, iclass 32, count 0 2006.257.10:31:14.82#ibcon#read 3, iclass 32, count 0 2006.257.10:31:14.82#ibcon#about to read 4, iclass 32, count 0 2006.257.10:31:14.82#ibcon#read 4, iclass 32, count 0 2006.257.10:31:14.82#ibcon#about to read 5, iclass 32, count 0 2006.257.10:31:14.82#ibcon#read 5, iclass 32, count 0 2006.257.10:31:14.82#ibcon#about to read 6, iclass 32, count 0 2006.257.10:31:14.82#ibcon#read 6, iclass 32, count 0 2006.257.10:31:14.82#ibcon#end of sib2, iclass 32, count 0 2006.257.10:31:14.82#ibcon#*after write, iclass 32, count 0 2006.257.10:31:14.82#ibcon#*before return 0, iclass 32, count 0 2006.257.10:31:14.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:31:14.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:31:14.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:31:14.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:31:14.82$setupk4/ifdk4 2006.257.10:31:14.82$ifdk4/lo= 2006.257.10:31:14.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:31:14.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:31:14.82$ifdk4/patch= 2006.257.10:31:14.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:31:14.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:31:14.82$setupk4/!*+20s 2006.257.10:31:17.70#abcon#<5=/14 1.5 4.4 18.90 961013.9\r\n> 2006.257.10:31:17.72#abcon#{5=INTERFACE CLEAR} 2006.257.10:31:17.78#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:31:27.87#abcon#<5=/14 1.5 4.4 18.90 961013.9\r\n> 2006.257.10:31:27.89#abcon#{5=INTERFACE CLEAR} 2006.257.10:31:27.95#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:31:29.24$setupk4/"tpicd 2006.257.10:31:29.24$setupk4/echo=off 2006.257.10:31:29.24$setupk4/xlog=off 2006.257.10:31:29.24:!2006.257.10:32:39 2006.257.10:31:39.13#trakl#Source acquired 2006.257.10:31:40.13#flagr#flagr/antenna,acquired 2006.257.10:32:39.00:preob 2006.257.10:32:39.13/onsource/TRACKING 2006.257.10:32:39.13:!2006.257.10:32:49 2006.257.10:32:49.00:"tape 2006.257.10:32:49.00:"st=record 2006.257.10:32:49.00:data_valid=on 2006.257.10:32:49.00:midob 2006.257.10:32:49.13/onsource/TRACKING 2006.257.10:32:49.13/wx/18.90,1014.0,96 2006.257.10:32:49.24/cable/+6.4781E-03 2006.257.10:32:50.33/va/01,08,usb,yes,31,33 2006.257.10:32:50.33/va/02,07,usb,yes,33,34 2006.257.10:32:50.33/va/03,08,usb,yes,30,32 2006.257.10:32:50.33/va/04,07,usb,yes,34,36 2006.257.10:32:50.33/va/05,04,usb,yes,31,31 2006.257.10:32:50.33/va/06,04,usb,yes,34,34 2006.257.10:32:50.33/va/07,04,usb,yes,35,35 2006.257.10:32:50.33/va/08,04,usb,yes,29,36 2006.257.10:32:50.56/valo/01,524.99,yes,locked 2006.257.10:32:50.56/valo/02,534.99,yes,locked 2006.257.10:32:50.56/valo/03,564.99,yes,locked 2006.257.10:32:50.56/valo/04,624.99,yes,locked 2006.257.10:32:50.56/valo/05,734.99,yes,locked 2006.257.10:32:50.56/valo/06,814.99,yes,locked 2006.257.10:32:50.56/valo/07,864.99,yes,locked 2006.257.10:32:50.56/valo/08,884.99,yes,locked 2006.257.10:32:51.65/vb/01,04,usb,yes,30,28 2006.257.10:32:51.65/vb/02,05,usb,yes,29,29 2006.257.10:32:51.65/vb/03,04,usb,yes,30,33 2006.257.10:32:51.65/vb/04,05,usb,yes,30,29 2006.257.10:32:51.65/vb/05,04,usb,yes,26,29 2006.257.10:32:51.65/vb/06,04,usb,yes,31,27 2006.257.10:32:51.65/vb/07,04,usb,yes,31,31 2006.257.10:32:51.65/vb/08,04,usb,yes,28,32 2006.257.10:32:51.89/vblo/01,629.99,yes,locked 2006.257.10:32:51.89/vblo/02,634.99,yes,locked 2006.257.10:32:51.89/vblo/03,649.99,yes,locked 2006.257.10:32:51.89/vblo/04,679.99,yes,locked 2006.257.10:32:51.89/vblo/05,709.99,yes,locked 2006.257.10:32:51.89/vblo/06,719.99,yes,locked 2006.257.10:32:51.89/vblo/07,734.99,yes,locked 2006.257.10:32:51.89/vblo/08,744.99,yes,locked 2006.257.10:32:52.04/vabw/8 2006.257.10:32:52.19/vbbw/8 2006.257.10:32:52.28/xfe/off,on,15.0 2006.257.10:32:52.66/ifatt/23,28,28,28 2006.257.10:32:53.07/fmout-gps/S +4.62E-07 2006.257.10:32:53.11:!2006.257.10:33:29 2006.257.10:33:29.01:data_valid=off 2006.257.10:33:29.01:"et 2006.257.10:33:29.01:!+3s 2006.257.10:33:32.02:"tape 2006.257.10:33:32.02:postob 2006.257.10:33:32.15/cable/+6.4785E-03 2006.257.10:33:32.15/wx/18.90,1014.0,96 2006.257.10:33:32.21/fmout-gps/S +4.62E-07 2006.257.10:33:32.21:scan_name=257-1035,jd0609,170 2006.257.10:33:32.21:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.10:33:34.14#flagr#flagr/antenna,new-source 2006.257.10:33:34.14:checkk5 2006.257.10:33:34.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:33:34.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:33:35.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:33:35.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:33:36.16/chk_obsdata//k5ts1/T2571032??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.10:33:36.56/chk_obsdata//k5ts2/T2571032??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.10:33:36.97/chk_obsdata//k5ts3/T2571032??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.10:33:37.37/chk_obsdata//k5ts4/T2571032??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.10:33:38.10/k5log//k5ts1_log_newline 2006.257.10:33:38.83/k5log//k5ts2_log_newline 2006.257.10:33:39.53/k5log//k5ts3_log_newline 2006.257.10:33:40.23/k5log//k5ts4_log_newline 2006.257.10:33:40.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:33:40.26:setupk4=1 2006.257.10:33:40.26$setupk4/echo=on 2006.257.10:33:40.26$setupk4/pcalon 2006.257.10:33:40.26$pcalon/"no phase cal control is implemented here 2006.257.10:33:40.26$setupk4/"tpicd=stop 2006.257.10:33:40.26$setupk4/"rec=synch_on 2006.257.10:33:40.26$setupk4/"rec_mode=128 2006.257.10:33:40.26$setupk4/!* 2006.257.10:33:40.26$setupk4/recpk4 2006.257.10:33:40.26$recpk4/recpatch= 2006.257.10:33:40.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:33:40.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:33:40.26$setupk4/vck44 2006.257.10:33:40.26$vck44/valo=1,524.99 2006.257.10:33:40.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.10:33:40.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.10:33:40.26#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:40.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:33:40.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:33:40.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:33:40.26#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:33:40.26#ibcon#first serial, iclass 24, count 0 2006.257.10:33:40.26#ibcon#enter sib2, iclass 24, count 0 2006.257.10:33:40.26#ibcon#flushed, iclass 24, count 0 2006.257.10:33:40.26#ibcon#about to write, iclass 24, count 0 2006.257.10:33:40.26#ibcon#wrote, iclass 24, count 0 2006.257.10:33:40.26#ibcon#about to read 3, iclass 24, count 0 2006.257.10:33:40.28#ibcon#read 3, iclass 24, count 0 2006.257.10:33:40.28#ibcon#about to read 4, iclass 24, count 0 2006.257.10:33:40.28#ibcon#read 4, iclass 24, count 0 2006.257.10:33:40.28#ibcon#about to read 5, iclass 24, count 0 2006.257.10:33:40.28#ibcon#read 5, iclass 24, count 0 2006.257.10:33:40.28#ibcon#about to read 6, iclass 24, count 0 2006.257.10:33:40.28#ibcon#read 6, iclass 24, count 0 2006.257.10:33:40.28#ibcon#end of sib2, iclass 24, count 0 2006.257.10:33:40.28#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:33:40.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:33:40.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:33:40.28#ibcon#*before write, iclass 24, count 0 2006.257.10:33:40.28#ibcon#enter sib2, iclass 24, count 0 2006.257.10:33:40.28#ibcon#flushed, iclass 24, count 0 2006.257.10:33:40.28#ibcon#about to write, iclass 24, count 0 2006.257.10:33:40.28#ibcon#wrote, iclass 24, count 0 2006.257.10:33:40.28#ibcon#about to read 3, iclass 24, count 0 2006.257.10:33:40.31#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:33:40.33#ibcon#read 3, iclass 24, count 0 2006.257.10:33:40.33#ibcon#about to read 4, iclass 24, count 0 2006.257.10:33:40.33#ibcon#read 4, iclass 24, count 0 2006.257.10:33:40.33#ibcon#about to read 5, iclass 24, count 0 2006.257.10:33:40.33#ibcon#read 5, iclass 24, count 0 2006.257.10:33:40.33#ibcon#about to read 6, iclass 24, count 0 2006.257.10:33:40.33#ibcon#read 6, iclass 24, count 0 2006.257.10:33:40.33#ibcon#end of sib2, iclass 24, count 0 2006.257.10:33:40.33#ibcon#*after write, iclass 24, count 0 2006.257.10:33:40.33#ibcon#*before return 0, iclass 24, count 0 2006.257.10:33:40.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:33:40.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:33:40.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:33:40.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:33:40.33$vck44/va=1,8 2006.257.10:33:40.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.10:33:40.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.10:33:40.33#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:40.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:40.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:40.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:40.33#ibcon#enter wrdev, iclass 27, count 2 2006.257.10:33:40.33#ibcon#first serial, iclass 27, count 2 2006.257.10:33:40.33#ibcon#enter sib2, iclass 27, count 2 2006.257.10:33:40.33#ibcon#flushed, iclass 27, count 2 2006.257.10:33:40.33#ibcon#about to write, iclass 27, count 2 2006.257.10:33:40.33#ibcon#wrote, iclass 27, count 2 2006.257.10:33:40.33#ibcon#about to read 3, iclass 27, count 2 2006.257.10:33:40.35#ibcon#read 3, iclass 27, count 2 2006.257.10:33:40.35#ibcon#about to read 4, iclass 27, count 2 2006.257.10:33:40.35#ibcon#read 4, iclass 27, count 2 2006.257.10:33:40.35#ibcon#about to read 5, iclass 27, count 2 2006.257.10:33:40.35#ibcon#read 5, iclass 27, count 2 2006.257.10:33:40.35#ibcon#about to read 6, iclass 27, count 2 2006.257.10:33:40.35#ibcon#read 6, iclass 27, count 2 2006.257.10:33:40.35#ibcon#end of sib2, iclass 27, count 2 2006.257.10:33:40.35#ibcon#*mode == 0, iclass 27, count 2 2006.257.10:33:40.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.10:33:40.35#ibcon#[25=AT01-08\r\n] 2006.257.10:33:40.35#ibcon#*before write, iclass 27, count 2 2006.257.10:33:40.35#ibcon#enter sib2, iclass 27, count 2 2006.257.10:33:40.35#ibcon#flushed, iclass 27, count 2 2006.257.10:33:40.35#ibcon#about to write, iclass 27, count 2 2006.257.10:33:40.35#ibcon#wrote, iclass 27, count 2 2006.257.10:33:40.35#ibcon#about to read 3, iclass 27, count 2 2006.257.10:33:40.38#ibcon#read 3, iclass 27, count 2 2006.257.10:33:40.38#ibcon#about to read 4, iclass 27, count 2 2006.257.10:33:40.38#ibcon#read 4, iclass 27, count 2 2006.257.10:33:40.38#ibcon#about to read 5, iclass 27, count 2 2006.257.10:33:40.38#ibcon#read 5, iclass 27, count 2 2006.257.10:33:40.38#ibcon#about to read 6, iclass 27, count 2 2006.257.10:33:40.38#ibcon#read 6, iclass 27, count 2 2006.257.10:33:40.38#ibcon#end of sib2, iclass 27, count 2 2006.257.10:33:40.38#ibcon#*after write, iclass 27, count 2 2006.257.10:33:40.38#ibcon#*before return 0, iclass 27, count 2 2006.257.10:33:40.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:40.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:40.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.10:33:40.38#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:40.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:40.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:40.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:40.50#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:33:40.50#ibcon#first serial, iclass 27, count 0 2006.257.10:33:40.50#ibcon#enter sib2, iclass 27, count 0 2006.257.10:33:40.50#ibcon#flushed, iclass 27, count 0 2006.257.10:33:40.50#ibcon#about to write, iclass 27, count 0 2006.257.10:33:40.50#ibcon#wrote, iclass 27, count 0 2006.257.10:33:40.50#ibcon#about to read 3, iclass 27, count 0 2006.257.10:33:40.52#ibcon#read 3, iclass 27, count 0 2006.257.10:33:40.52#ibcon#about to read 4, iclass 27, count 0 2006.257.10:33:40.52#ibcon#read 4, iclass 27, count 0 2006.257.10:33:40.52#ibcon#about to read 5, iclass 27, count 0 2006.257.10:33:40.52#ibcon#read 5, iclass 27, count 0 2006.257.10:33:40.52#ibcon#about to read 6, iclass 27, count 0 2006.257.10:33:40.52#ibcon#read 6, iclass 27, count 0 2006.257.10:33:40.52#ibcon#end of sib2, iclass 27, count 0 2006.257.10:33:40.52#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:33:40.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:33:40.52#ibcon#[25=USB\r\n] 2006.257.10:33:40.52#ibcon#*before write, iclass 27, count 0 2006.257.10:33:40.52#ibcon#enter sib2, iclass 27, count 0 2006.257.10:33:40.52#ibcon#flushed, iclass 27, count 0 2006.257.10:33:40.52#ibcon#about to write, iclass 27, count 0 2006.257.10:33:40.52#ibcon#wrote, iclass 27, count 0 2006.257.10:33:40.52#ibcon#about to read 3, iclass 27, count 0 2006.257.10:33:40.55#ibcon#read 3, iclass 27, count 0 2006.257.10:33:40.55#ibcon#about to read 4, iclass 27, count 0 2006.257.10:33:40.55#ibcon#read 4, iclass 27, count 0 2006.257.10:33:40.55#ibcon#about to read 5, iclass 27, count 0 2006.257.10:33:40.55#ibcon#read 5, iclass 27, count 0 2006.257.10:33:40.55#ibcon#about to read 6, iclass 27, count 0 2006.257.10:33:40.55#ibcon#read 6, iclass 27, count 0 2006.257.10:33:40.55#ibcon#end of sib2, iclass 27, count 0 2006.257.10:33:40.55#ibcon#*after write, iclass 27, count 0 2006.257.10:33:40.55#ibcon#*before return 0, iclass 27, count 0 2006.257.10:33:40.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:40.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:40.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:33:40.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:33:40.55$vck44/valo=2,534.99 2006.257.10:33:40.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.10:33:40.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.10:33:40.55#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:40.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:40.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:40.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:40.55#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:33:40.55#ibcon#first serial, iclass 29, count 0 2006.257.10:33:40.55#ibcon#enter sib2, iclass 29, count 0 2006.257.10:33:40.55#ibcon#flushed, iclass 29, count 0 2006.257.10:33:40.55#ibcon#about to write, iclass 29, count 0 2006.257.10:33:40.55#ibcon#wrote, iclass 29, count 0 2006.257.10:33:40.55#ibcon#about to read 3, iclass 29, count 0 2006.257.10:33:40.57#ibcon#read 3, iclass 29, count 0 2006.257.10:33:40.57#ibcon#about to read 4, iclass 29, count 0 2006.257.10:33:40.57#ibcon#read 4, iclass 29, count 0 2006.257.10:33:40.57#ibcon#about to read 5, iclass 29, count 0 2006.257.10:33:40.57#ibcon#read 5, iclass 29, count 0 2006.257.10:33:40.57#ibcon#about to read 6, iclass 29, count 0 2006.257.10:33:40.57#ibcon#read 6, iclass 29, count 0 2006.257.10:33:40.57#ibcon#end of sib2, iclass 29, count 0 2006.257.10:33:40.57#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:33:40.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:33:40.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:33:40.57#ibcon#*before write, iclass 29, count 0 2006.257.10:33:40.57#ibcon#enter sib2, iclass 29, count 0 2006.257.10:33:40.57#ibcon#flushed, iclass 29, count 0 2006.257.10:33:40.57#ibcon#about to write, iclass 29, count 0 2006.257.10:33:40.57#ibcon#wrote, iclass 29, count 0 2006.257.10:33:40.57#ibcon#about to read 3, iclass 29, count 0 2006.257.10:33:40.61#ibcon#read 3, iclass 29, count 0 2006.257.10:33:40.61#ibcon#about to read 4, iclass 29, count 0 2006.257.10:33:40.61#ibcon#read 4, iclass 29, count 0 2006.257.10:33:40.61#ibcon#about to read 5, iclass 29, count 0 2006.257.10:33:40.61#ibcon#read 5, iclass 29, count 0 2006.257.10:33:40.61#ibcon#about to read 6, iclass 29, count 0 2006.257.10:33:40.61#ibcon#read 6, iclass 29, count 0 2006.257.10:33:40.61#ibcon#end of sib2, iclass 29, count 0 2006.257.10:33:40.61#ibcon#*after write, iclass 29, count 0 2006.257.10:33:40.61#ibcon#*before return 0, iclass 29, count 0 2006.257.10:33:40.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:40.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:40.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:33:40.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:33:40.61$vck44/va=2,7 2006.257.10:33:40.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.10:33:40.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.10:33:40.61#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:40.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:40.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:40.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:40.67#ibcon#enter wrdev, iclass 31, count 2 2006.257.10:33:40.67#ibcon#first serial, iclass 31, count 2 2006.257.10:33:40.67#ibcon#enter sib2, iclass 31, count 2 2006.257.10:33:40.67#ibcon#flushed, iclass 31, count 2 2006.257.10:33:40.67#ibcon#about to write, iclass 31, count 2 2006.257.10:33:40.67#ibcon#wrote, iclass 31, count 2 2006.257.10:33:40.67#ibcon#about to read 3, iclass 31, count 2 2006.257.10:33:40.69#ibcon#read 3, iclass 31, count 2 2006.257.10:33:40.69#ibcon#about to read 4, iclass 31, count 2 2006.257.10:33:40.69#ibcon#read 4, iclass 31, count 2 2006.257.10:33:40.69#ibcon#about to read 5, iclass 31, count 2 2006.257.10:33:40.69#ibcon#read 5, iclass 31, count 2 2006.257.10:33:40.69#ibcon#about to read 6, iclass 31, count 2 2006.257.10:33:40.69#ibcon#read 6, iclass 31, count 2 2006.257.10:33:40.69#ibcon#end of sib2, iclass 31, count 2 2006.257.10:33:40.69#ibcon#*mode == 0, iclass 31, count 2 2006.257.10:33:40.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.10:33:40.69#ibcon#[25=AT02-07\r\n] 2006.257.10:33:40.69#ibcon#*before write, iclass 31, count 2 2006.257.10:33:40.69#ibcon#enter sib2, iclass 31, count 2 2006.257.10:33:40.69#ibcon#flushed, iclass 31, count 2 2006.257.10:33:40.69#ibcon#about to write, iclass 31, count 2 2006.257.10:33:40.69#ibcon#wrote, iclass 31, count 2 2006.257.10:33:40.69#ibcon#about to read 3, iclass 31, count 2 2006.257.10:33:40.72#ibcon#read 3, iclass 31, count 2 2006.257.10:33:40.72#ibcon#about to read 4, iclass 31, count 2 2006.257.10:33:40.72#ibcon#read 4, iclass 31, count 2 2006.257.10:33:40.72#ibcon#about to read 5, iclass 31, count 2 2006.257.10:33:40.72#ibcon#read 5, iclass 31, count 2 2006.257.10:33:40.72#ibcon#about to read 6, iclass 31, count 2 2006.257.10:33:40.72#ibcon#read 6, iclass 31, count 2 2006.257.10:33:40.72#ibcon#end of sib2, iclass 31, count 2 2006.257.10:33:40.72#ibcon#*after write, iclass 31, count 2 2006.257.10:33:40.72#ibcon#*before return 0, iclass 31, count 2 2006.257.10:33:40.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:40.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:40.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.10:33:40.72#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:40.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:40.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:40.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:40.84#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:33:40.84#ibcon#first serial, iclass 31, count 0 2006.257.10:33:40.84#ibcon#enter sib2, iclass 31, count 0 2006.257.10:33:40.84#ibcon#flushed, iclass 31, count 0 2006.257.10:33:40.84#ibcon#about to write, iclass 31, count 0 2006.257.10:33:40.84#ibcon#wrote, iclass 31, count 0 2006.257.10:33:40.84#ibcon#about to read 3, iclass 31, count 0 2006.257.10:33:40.86#ibcon#read 3, iclass 31, count 0 2006.257.10:33:40.86#ibcon#about to read 4, iclass 31, count 0 2006.257.10:33:40.86#ibcon#read 4, iclass 31, count 0 2006.257.10:33:40.86#ibcon#about to read 5, iclass 31, count 0 2006.257.10:33:40.86#ibcon#read 5, iclass 31, count 0 2006.257.10:33:40.86#ibcon#about to read 6, iclass 31, count 0 2006.257.10:33:40.86#ibcon#read 6, iclass 31, count 0 2006.257.10:33:40.86#ibcon#end of sib2, iclass 31, count 0 2006.257.10:33:40.86#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:33:40.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:33:40.86#ibcon#[25=USB\r\n] 2006.257.10:33:40.86#ibcon#*before write, iclass 31, count 0 2006.257.10:33:40.86#ibcon#enter sib2, iclass 31, count 0 2006.257.10:33:40.86#ibcon#flushed, iclass 31, count 0 2006.257.10:33:40.86#ibcon#about to write, iclass 31, count 0 2006.257.10:33:40.86#ibcon#wrote, iclass 31, count 0 2006.257.10:33:40.86#ibcon#about to read 3, iclass 31, count 0 2006.257.10:33:40.89#ibcon#read 3, iclass 31, count 0 2006.257.10:33:40.89#ibcon#about to read 4, iclass 31, count 0 2006.257.10:33:40.89#ibcon#read 4, iclass 31, count 0 2006.257.10:33:40.89#ibcon#about to read 5, iclass 31, count 0 2006.257.10:33:40.89#ibcon#read 5, iclass 31, count 0 2006.257.10:33:40.89#ibcon#about to read 6, iclass 31, count 0 2006.257.10:33:40.89#ibcon#read 6, iclass 31, count 0 2006.257.10:33:40.89#ibcon#end of sib2, iclass 31, count 0 2006.257.10:33:40.89#ibcon#*after write, iclass 31, count 0 2006.257.10:33:40.89#ibcon#*before return 0, iclass 31, count 0 2006.257.10:33:40.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:40.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:40.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:33:40.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:33:40.89$vck44/valo=3,564.99 2006.257.10:33:40.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.10:33:40.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.10:33:40.89#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:40.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:40.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:40.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:40.89#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:33:40.89#ibcon#first serial, iclass 33, count 0 2006.257.10:33:40.89#ibcon#enter sib2, iclass 33, count 0 2006.257.10:33:40.89#ibcon#flushed, iclass 33, count 0 2006.257.10:33:40.89#ibcon#about to write, iclass 33, count 0 2006.257.10:33:40.89#ibcon#wrote, iclass 33, count 0 2006.257.10:33:40.89#ibcon#about to read 3, iclass 33, count 0 2006.257.10:33:40.91#ibcon#read 3, iclass 33, count 0 2006.257.10:33:40.91#ibcon#about to read 4, iclass 33, count 0 2006.257.10:33:40.91#ibcon#read 4, iclass 33, count 0 2006.257.10:33:40.91#ibcon#about to read 5, iclass 33, count 0 2006.257.10:33:40.91#ibcon#read 5, iclass 33, count 0 2006.257.10:33:40.91#ibcon#about to read 6, iclass 33, count 0 2006.257.10:33:40.91#ibcon#read 6, iclass 33, count 0 2006.257.10:33:40.91#ibcon#end of sib2, iclass 33, count 0 2006.257.10:33:40.91#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:33:40.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:33:40.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:33:40.91#ibcon#*before write, iclass 33, count 0 2006.257.10:33:40.91#ibcon#enter sib2, iclass 33, count 0 2006.257.10:33:40.91#ibcon#flushed, iclass 33, count 0 2006.257.10:33:40.91#ibcon#about to write, iclass 33, count 0 2006.257.10:33:40.91#ibcon#wrote, iclass 33, count 0 2006.257.10:33:40.91#ibcon#about to read 3, iclass 33, count 0 2006.257.10:33:40.95#ibcon#read 3, iclass 33, count 0 2006.257.10:33:40.95#ibcon#about to read 4, iclass 33, count 0 2006.257.10:33:40.95#ibcon#read 4, iclass 33, count 0 2006.257.10:33:40.95#ibcon#about to read 5, iclass 33, count 0 2006.257.10:33:40.95#ibcon#read 5, iclass 33, count 0 2006.257.10:33:40.95#ibcon#about to read 6, iclass 33, count 0 2006.257.10:33:40.95#ibcon#read 6, iclass 33, count 0 2006.257.10:33:40.95#ibcon#end of sib2, iclass 33, count 0 2006.257.10:33:40.95#ibcon#*after write, iclass 33, count 0 2006.257.10:33:40.95#ibcon#*before return 0, iclass 33, count 0 2006.257.10:33:40.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:40.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:40.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:33:40.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:33:40.95$vck44/va=3,8 2006.257.10:33:40.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.10:33:40.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.10:33:40.95#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:40.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:41.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:41.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:41.01#ibcon#enter wrdev, iclass 35, count 2 2006.257.10:33:41.01#ibcon#first serial, iclass 35, count 2 2006.257.10:33:41.01#ibcon#enter sib2, iclass 35, count 2 2006.257.10:33:41.01#ibcon#flushed, iclass 35, count 2 2006.257.10:33:41.01#ibcon#about to write, iclass 35, count 2 2006.257.10:33:41.01#ibcon#wrote, iclass 35, count 2 2006.257.10:33:41.01#ibcon#about to read 3, iclass 35, count 2 2006.257.10:33:41.03#ibcon#read 3, iclass 35, count 2 2006.257.10:33:41.03#ibcon#about to read 4, iclass 35, count 2 2006.257.10:33:41.03#ibcon#read 4, iclass 35, count 2 2006.257.10:33:41.03#ibcon#about to read 5, iclass 35, count 2 2006.257.10:33:41.03#ibcon#read 5, iclass 35, count 2 2006.257.10:33:41.03#ibcon#about to read 6, iclass 35, count 2 2006.257.10:33:41.03#ibcon#read 6, iclass 35, count 2 2006.257.10:33:41.03#ibcon#end of sib2, iclass 35, count 2 2006.257.10:33:41.03#ibcon#*mode == 0, iclass 35, count 2 2006.257.10:33:41.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.10:33:41.03#ibcon#[25=AT03-08\r\n] 2006.257.10:33:41.03#ibcon#*before write, iclass 35, count 2 2006.257.10:33:41.03#ibcon#enter sib2, iclass 35, count 2 2006.257.10:33:41.03#ibcon#flushed, iclass 35, count 2 2006.257.10:33:41.03#ibcon#about to write, iclass 35, count 2 2006.257.10:33:41.03#ibcon#wrote, iclass 35, count 2 2006.257.10:33:41.03#ibcon#about to read 3, iclass 35, count 2 2006.257.10:33:41.06#ibcon#read 3, iclass 35, count 2 2006.257.10:33:41.06#ibcon#about to read 4, iclass 35, count 2 2006.257.10:33:41.06#ibcon#read 4, iclass 35, count 2 2006.257.10:33:41.06#ibcon#about to read 5, iclass 35, count 2 2006.257.10:33:41.06#ibcon#read 5, iclass 35, count 2 2006.257.10:33:41.06#ibcon#about to read 6, iclass 35, count 2 2006.257.10:33:41.06#ibcon#read 6, iclass 35, count 2 2006.257.10:33:41.06#ibcon#end of sib2, iclass 35, count 2 2006.257.10:33:41.06#ibcon#*after write, iclass 35, count 2 2006.257.10:33:41.06#ibcon#*before return 0, iclass 35, count 2 2006.257.10:33:41.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:41.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:41.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.10:33:41.06#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:41.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:41.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:41.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:41.18#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:33:41.18#ibcon#first serial, iclass 35, count 0 2006.257.10:33:41.18#ibcon#enter sib2, iclass 35, count 0 2006.257.10:33:41.18#ibcon#flushed, iclass 35, count 0 2006.257.10:33:41.18#ibcon#about to write, iclass 35, count 0 2006.257.10:33:41.18#ibcon#wrote, iclass 35, count 0 2006.257.10:33:41.18#ibcon#about to read 3, iclass 35, count 0 2006.257.10:33:41.20#ibcon#read 3, iclass 35, count 0 2006.257.10:33:41.20#ibcon#about to read 4, iclass 35, count 0 2006.257.10:33:41.20#ibcon#read 4, iclass 35, count 0 2006.257.10:33:41.20#ibcon#about to read 5, iclass 35, count 0 2006.257.10:33:41.20#ibcon#read 5, iclass 35, count 0 2006.257.10:33:41.20#ibcon#about to read 6, iclass 35, count 0 2006.257.10:33:41.20#ibcon#read 6, iclass 35, count 0 2006.257.10:33:41.20#ibcon#end of sib2, iclass 35, count 0 2006.257.10:33:41.20#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:33:41.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:33:41.20#ibcon#[25=USB\r\n] 2006.257.10:33:41.20#ibcon#*before write, iclass 35, count 0 2006.257.10:33:41.20#ibcon#enter sib2, iclass 35, count 0 2006.257.10:33:41.20#ibcon#flushed, iclass 35, count 0 2006.257.10:33:41.20#ibcon#about to write, iclass 35, count 0 2006.257.10:33:41.20#ibcon#wrote, iclass 35, count 0 2006.257.10:33:41.20#ibcon#about to read 3, iclass 35, count 0 2006.257.10:33:41.23#ibcon#read 3, iclass 35, count 0 2006.257.10:33:41.23#ibcon#about to read 4, iclass 35, count 0 2006.257.10:33:41.23#ibcon#read 4, iclass 35, count 0 2006.257.10:33:41.23#ibcon#about to read 5, iclass 35, count 0 2006.257.10:33:41.23#ibcon#read 5, iclass 35, count 0 2006.257.10:33:41.23#ibcon#about to read 6, iclass 35, count 0 2006.257.10:33:41.23#ibcon#read 6, iclass 35, count 0 2006.257.10:33:41.23#ibcon#end of sib2, iclass 35, count 0 2006.257.10:33:41.23#ibcon#*after write, iclass 35, count 0 2006.257.10:33:41.23#ibcon#*before return 0, iclass 35, count 0 2006.257.10:33:41.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:41.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:41.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:33:41.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:33:41.23$vck44/valo=4,624.99 2006.257.10:33:41.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.10:33:41.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.10:33:41.23#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:41.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:41.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:41.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:41.23#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:33:41.23#ibcon#first serial, iclass 37, count 0 2006.257.10:33:41.23#ibcon#enter sib2, iclass 37, count 0 2006.257.10:33:41.23#ibcon#flushed, iclass 37, count 0 2006.257.10:33:41.23#ibcon#about to write, iclass 37, count 0 2006.257.10:33:41.23#ibcon#wrote, iclass 37, count 0 2006.257.10:33:41.23#ibcon#about to read 3, iclass 37, count 0 2006.257.10:33:41.25#ibcon#read 3, iclass 37, count 0 2006.257.10:33:41.25#ibcon#about to read 4, iclass 37, count 0 2006.257.10:33:41.25#ibcon#read 4, iclass 37, count 0 2006.257.10:33:41.25#ibcon#about to read 5, iclass 37, count 0 2006.257.10:33:41.25#ibcon#read 5, iclass 37, count 0 2006.257.10:33:41.25#ibcon#about to read 6, iclass 37, count 0 2006.257.10:33:41.25#ibcon#read 6, iclass 37, count 0 2006.257.10:33:41.25#ibcon#end of sib2, iclass 37, count 0 2006.257.10:33:41.25#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:33:41.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:33:41.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:33:41.25#ibcon#*before write, iclass 37, count 0 2006.257.10:33:41.25#ibcon#enter sib2, iclass 37, count 0 2006.257.10:33:41.25#ibcon#flushed, iclass 37, count 0 2006.257.10:33:41.25#ibcon#about to write, iclass 37, count 0 2006.257.10:33:41.25#ibcon#wrote, iclass 37, count 0 2006.257.10:33:41.25#ibcon#about to read 3, iclass 37, count 0 2006.257.10:33:41.29#ibcon#read 3, iclass 37, count 0 2006.257.10:33:41.29#ibcon#about to read 4, iclass 37, count 0 2006.257.10:33:41.29#ibcon#read 4, iclass 37, count 0 2006.257.10:33:41.29#ibcon#about to read 5, iclass 37, count 0 2006.257.10:33:41.29#ibcon#read 5, iclass 37, count 0 2006.257.10:33:41.29#ibcon#about to read 6, iclass 37, count 0 2006.257.10:33:41.29#ibcon#read 6, iclass 37, count 0 2006.257.10:33:41.29#ibcon#end of sib2, iclass 37, count 0 2006.257.10:33:41.29#ibcon#*after write, iclass 37, count 0 2006.257.10:33:41.29#ibcon#*before return 0, iclass 37, count 0 2006.257.10:33:41.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:41.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:41.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:33:41.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:33:41.29$vck44/va=4,7 2006.257.10:33:41.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.10:33:41.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.10:33:41.29#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:41.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:41.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:41.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:41.35#ibcon#enter wrdev, iclass 39, count 2 2006.257.10:33:41.35#ibcon#first serial, iclass 39, count 2 2006.257.10:33:41.35#ibcon#enter sib2, iclass 39, count 2 2006.257.10:33:41.35#ibcon#flushed, iclass 39, count 2 2006.257.10:33:41.35#ibcon#about to write, iclass 39, count 2 2006.257.10:33:41.35#ibcon#wrote, iclass 39, count 2 2006.257.10:33:41.35#ibcon#about to read 3, iclass 39, count 2 2006.257.10:33:41.37#ibcon#read 3, iclass 39, count 2 2006.257.10:33:41.37#ibcon#about to read 4, iclass 39, count 2 2006.257.10:33:41.37#ibcon#read 4, iclass 39, count 2 2006.257.10:33:41.37#ibcon#about to read 5, iclass 39, count 2 2006.257.10:33:41.37#ibcon#read 5, iclass 39, count 2 2006.257.10:33:41.37#ibcon#about to read 6, iclass 39, count 2 2006.257.10:33:41.37#ibcon#read 6, iclass 39, count 2 2006.257.10:33:41.37#ibcon#end of sib2, iclass 39, count 2 2006.257.10:33:41.37#ibcon#*mode == 0, iclass 39, count 2 2006.257.10:33:41.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.10:33:41.37#ibcon#[25=AT04-07\r\n] 2006.257.10:33:41.37#ibcon#*before write, iclass 39, count 2 2006.257.10:33:41.37#ibcon#enter sib2, iclass 39, count 2 2006.257.10:33:41.37#ibcon#flushed, iclass 39, count 2 2006.257.10:33:41.37#ibcon#about to write, iclass 39, count 2 2006.257.10:33:41.37#ibcon#wrote, iclass 39, count 2 2006.257.10:33:41.37#ibcon#about to read 3, iclass 39, count 2 2006.257.10:33:41.40#ibcon#read 3, iclass 39, count 2 2006.257.10:33:41.40#ibcon#about to read 4, iclass 39, count 2 2006.257.10:33:41.40#ibcon#read 4, iclass 39, count 2 2006.257.10:33:41.40#ibcon#about to read 5, iclass 39, count 2 2006.257.10:33:41.40#ibcon#read 5, iclass 39, count 2 2006.257.10:33:41.40#ibcon#about to read 6, iclass 39, count 2 2006.257.10:33:41.40#ibcon#read 6, iclass 39, count 2 2006.257.10:33:41.40#ibcon#end of sib2, iclass 39, count 2 2006.257.10:33:41.40#ibcon#*after write, iclass 39, count 2 2006.257.10:33:41.43#ibcon#*before return 0, iclass 39, count 2 2006.257.10:33:41.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:41.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:41.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.10:33:41.43#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:41.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:41.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:41.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:41.54#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:33:41.54#ibcon#first serial, iclass 39, count 0 2006.257.10:33:41.54#ibcon#enter sib2, iclass 39, count 0 2006.257.10:33:41.54#ibcon#flushed, iclass 39, count 0 2006.257.10:33:41.54#ibcon#about to write, iclass 39, count 0 2006.257.10:33:41.54#ibcon#wrote, iclass 39, count 0 2006.257.10:33:41.54#ibcon#about to read 3, iclass 39, count 0 2006.257.10:33:41.56#ibcon#read 3, iclass 39, count 0 2006.257.10:33:41.56#ibcon#about to read 4, iclass 39, count 0 2006.257.10:33:41.56#ibcon#read 4, iclass 39, count 0 2006.257.10:33:41.56#ibcon#about to read 5, iclass 39, count 0 2006.257.10:33:41.56#ibcon#read 5, iclass 39, count 0 2006.257.10:33:41.56#ibcon#about to read 6, iclass 39, count 0 2006.257.10:33:41.56#ibcon#read 6, iclass 39, count 0 2006.257.10:33:41.56#ibcon#end of sib2, iclass 39, count 0 2006.257.10:33:41.56#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:33:41.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:33:41.56#ibcon#[25=USB\r\n] 2006.257.10:33:41.56#ibcon#*before write, iclass 39, count 0 2006.257.10:33:41.56#ibcon#enter sib2, iclass 39, count 0 2006.257.10:33:41.56#ibcon#flushed, iclass 39, count 0 2006.257.10:33:41.56#ibcon#about to write, iclass 39, count 0 2006.257.10:33:41.56#ibcon#wrote, iclass 39, count 0 2006.257.10:33:41.56#ibcon#about to read 3, iclass 39, count 0 2006.257.10:33:41.59#ibcon#read 3, iclass 39, count 0 2006.257.10:33:41.59#ibcon#about to read 4, iclass 39, count 0 2006.257.10:33:41.59#ibcon#read 4, iclass 39, count 0 2006.257.10:33:41.59#ibcon#about to read 5, iclass 39, count 0 2006.257.10:33:41.59#ibcon#read 5, iclass 39, count 0 2006.257.10:33:41.59#ibcon#about to read 6, iclass 39, count 0 2006.257.10:33:41.59#ibcon#read 6, iclass 39, count 0 2006.257.10:33:41.59#ibcon#end of sib2, iclass 39, count 0 2006.257.10:33:41.59#ibcon#*after write, iclass 39, count 0 2006.257.10:33:41.59#ibcon#*before return 0, iclass 39, count 0 2006.257.10:33:41.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:41.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:41.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:33:41.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:33:41.59$vck44/valo=5,734.99 2006.257.10:33:41.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.10:33:41.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.10:33:41.59#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:41.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:41.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:41.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:41.59#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:33:41.59#ibcon#first serial, iclass 3, count 0 2006.257.10:33:41.59#ibcon#enter sib2, iclass 3, count 0 2006.257.10:33:41.59#ibcon#flushed, iclass 3, count 0 2006.257.10:33:41.59#ibcon#about to write, iclass 3, count 0 2006.257.10:33:41.59#ibcon#wrote, iclass 3, count 0 2006.257.10:33:41.59#ibcon#about to read 3, iclass 3, count 0 2006.257.10:33:41.61#ibcon#read 3, iclass 3, count 0 2006.257.10:33:41.61#ibcon#about to read 4, iclass 3, count 0 2006.257.10:33:41.61#ibcon#read 4, iclass 3, count 0 2006.257.10:33:41.61#ibcon#about to read 5, iclass 3, count 0 2006.257.10:33:41.61#ibcon#read 5, iclass 3, count 0 2006.257.10:33:41.61#ibcon#about to read 6, iclass 3, count 0 2006.257.10:33:41.61#ibcon#read 6, iclass 3, count 0 2006.257.10:33:41.61#ibcon#end of sib2, iclass 3, count 0 2006.257.10:33:41.61#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:33:41.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:33:41.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:33:41.61#ibcon#*before write, iclass 3, count 0 2006.257.10:33:41.61#ibcon#enter sib2, iclass 3, count 0 2006.257.10:33:41.61#ibcon#flushed, iclass 3, count 0 2006.257.10:33:41.61#ibcon#about to write, iclass 3, count 0 2006.257.10:33:41.61#ibcon#wrote, iclass 3, count 0 2006.257.10:33:41.61#ibcon#about to read 3, iclass 3, count 0 2006.257.10:33:41.65#ibcon#read 3, iclass 3, count 0 2006.257.10:33:41.65#ibcon#about to read 4, iclass 3, count 0 2006.257.10:33:41.65#ibcon#read 4, iclass 3, count 0 2006.257.10:33:41.65#ibcon#about to read 5, iclass 3, count 0 2006.257.10:33:41.65#ibcon#read 5, iclass 3, count 0 2006.257.10:33:41.65#ibcon#about to read 6, iclass 3, count 0 2006.257.10:33:41.65#ibcon#read 6, iclass 3, count 0 2006.257.10:33:41.65#ibcon#end of sib2, iclass 3, count 0 2006.257.10:33:41.65#ibcon#*after write, iclass 3, count 0 2006.257.10:33:41.65#ibcon#*before return 0, iclass 3, count 0 2006.257.10:33:41.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:41.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:41.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:33:41.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:33:41.65$vck44/va=5,4 2006.257.10:33:41.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.10:33:41.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.10:33:41.65#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:41.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:41.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:41.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:41.71#ibcon#enter wrdev, iclass 5, count 2 2006.257.10:33:41.71#ibcon#first serial, iclass 5, count 2 2006.257.10:33:41.71#ibcon#enter sib2, iclass 5, count 2 2006.257.10:33:41.71#ibcon#flushed, iclass 5, count 2 2006.257.10:33:41.71#ibcon#about to write, iclass 5, count 2 2006.257.10:33:41.71#ibcon#wrote, iclass 5, count 2 2006.257.10:33:41.71#ibcon#about to read 3, iclass 5, count 2 2006.257.10:33:41.73#ibcon#read 3, iclass 5, count 2 2006.257.10:33:41.73#ibcon#about to read 4, iclass 5, count 2 2006.257.10:33:41.73#ibcon#read 4, iclass 5, count 2 2006.257.10:33:41.73#ibcon#about to read 5, iclass 5, count 2 2006.257.10:33:41.73#ibcon#read 5, iclass 5, count 2 2006.257.10:33:41.73#ibcon#about to read 6, iclass 5, count 2 2006.257.10:33:41.73#ibcon#read 6, iclass 5, count 2 2006.257.10:33:41.73#ibcon#end of sib2, iclass 5, count 2 2006.257.10:33:41.73#ibcon#*mode == 0, iclass 5, count 2 2006.257.10:33:41.73#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.10:33:41.73#ibcon#[25=AT05-04\r\n] 2006.257.10:33:41.73#ibcon#*before write, iclass 5, count 2 2006.257.10:33:41.73#ibcon#enter sib2, iclass 5, count 2 2006.257.10:33:41.73#ibcon#flushed, iclass 5, count 2 2006.257.10:33:41.73#ibcon#about to write, iclass 5, count 2 2006.257.10:33:41.73#ibcon#wrote, iclass 5, count 2 2006.257.10:33:41.73#ibcon#about to read 3, iclass 5, count 2 2006.257.10:33:41.76#ibcon#read 3, iclass 5, count 2 2006.257.10:33:41.76#ibcon#about to read 4, iclass 5, count 2 2006.257.10:33:41.76#ibcon#read 4, iclass 5, count 2 2006.257.10:33:41.76#ibcon#about to read 5, iclass 5, count 2 2006.257.10:33:41.76#ibcon#read 5, iclass 5, count 2 2006.257.10:33:41.76#ibcon#about to read 6, iclass 5, count 2 2006.257.10:33:41.76#ibcon#read 6, iclass 5, count 2 2006.257.10:33:41.76#ibcon#end of sib2, iclass 5, count 2 2006.257.10:33:41.76#ibcon#*after write, iclass 5, count 2 2006.257.10:33:41.76#ibcon#*before return 0, iclass 5, count 2 2006.257.10:33:41.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:41.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:41.76#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.10:33:41.76#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:41.76#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:41.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:41.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:41.88#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:33:41.88#ibcon#first serial, iclass 5, count 0 2006.257.10:33:41.88#ibcon#enter sib2, iclass 5, count 0 2006.257.10:33:41.88#ibcon#flushed, iclass 5, count 0 2006.257.10:33:41.88#ibcon#about to write, iclass 5, count 0 2006.257.10:33:41.88#ibcon#wrote, iclass 5, count 0 2006.257.10:33:41.88#ibcon#about to read 3, iclass 5, count 0 2006.257.10:33:41.90#ibcon#read 3, iclass 5, count 0 2006.257.10:33:41.90#ibcon#about to read 4, iclass 5, count 0 2006.257.10:33:41.90#ibcon#read 4, iclass 5, count 0 2006.257.10:33:41.90#ibcon#about to read 5, iclass 5, count 0 2006.257.10:33:41.90#ibcon#read 5, iclass 5, count 0 2006.257.10:33:41.90#ibcon#about to read 6, iclass 5, count 0 2006.257.10:33:41.90#ibcon#read 6, iclass 5, count 0 2006.257.10:33:41.90#ibcon#end of sib2, iclass 5, count 0 2006.257.10:33:41.90#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:33:41.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:33:41.90#ibcon#[25=USB\r\n] 2006.257.10:33:41.90#ibcon#*before write, iclass 5, count 0 2006.257.10:33:41.90#ibcon#enter sib2, iclass 5, count 0 2006.257.10:33:41.90#ibcon#flushed, iclass 5, count 0 2006.257.10:33:41.90#ibcon#about to write, iclass 5, count 0 2006.257.10:33:41.90#ibcon#wrote, iclass 5, count 0 2006.257.10:33:41.90#ibcon#about to read 3, iclass 5, count 0 2006.257.10:33:41.93#ibcon#read 3, iclass 5, count 0 2006.257.10:33:41.93#ibcon#about to read 4, iclass 5, count 0 2006.257.10:33:41.93#ibcon#read 4, iclass 5, count 0 2006.257.10:33:41.93#ibcon#about to read 5, iclass 5, count 0 2006.257.10:33:41.93#ibcon#read 5, iclass 5, count 0 2006.257.10:33:41.93#ibcon#about to read 6, iclass 5, count 0 2006.257.10:33:41.93#ibcon#read 6, iclass 5, count 0 2006.257.10:33:41.93#ibcon#end of sib2, iclass 5, count 0 2006.257.10:33:41.93#ibcon#*after write, iclass 5, count 0 2006.257.10:33:41.93#ibcon#*before return 0, iclass 5, count 0 2006.257.10:33:41.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:41.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:41.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:33:41.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:33:41.93$vck44/valo=6,814.99 2006.257.10:33:41.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.10:33:41.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.10:33:41.93#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:41.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:41.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:41.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:41.93#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:33:41.93#ibcon#first serial, iclass 7, count 0 2006.257.10:33:41.93#ibcon#enter sib2, iclass 7, count 0 2006.257.10:33:41.93#ibcon#flushed, iclass 7, count 0 2006.257.10:33:41.93#ibcon#about to write, iclass 7, count 0 2006.257.10:33:41.93#ibcon#wrote, iclass 7, count 0 2006.257.10:33:41.93#ibcon#about to read 3, iclass 7, count 0 2006.257.10:33:41.95#ibcon#read 3, iclass 7, count 0 2006.257.10:33:41.95#ibcon#about to read 4, iclass 7, count 0 2006.257.10:33:41.95#ibcon#read 4, iclass 7, count 0 2006.257.10:33:41.95#ibcon#about to read 5, iclass 7, count 0 2006.257.10:33:41.95#ibcon#read 5, iclass 7, count 0 2006.257.10:33:41.95#ibcon#about to read 6, iclass 7, count 0 2006.257.10:33:41.95#ibcon#read 6, iclass 7, count 0 2006.257.10:33:41.95#ibcon#end of sib2, iclass 7, count 0 2006.257.10:33:41.95#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:33:41.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:33:41.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:33:41.95#ibcon#*before write, iclass 7, count 0 2006.257.10:33:41.95#ibcon#enter sib2, iclass 7, count 0 2006.257.10:33:41.95#ibcon#flushed, iclass 7, count 0 2006.257.10:33:41.95#ibcon#about to write, iclass 7, count 0 2006.257.10:33:41.95#ibcon#wrote, iclass 7, count 0 2006.257.10:33:41.95#ibcon#about to read 3, iclass 7, count 0 2006.257.10:33:41.99#ibcon#read 3, iclass 7, count 0 2006.257.10:33:41.99#ibcon#about to read 4, iclass 7, count 0 2006.257.10:33:41.99#ibcon#read 4, iclass 7, count 0 2006.257.10:33:41.99#ibcon#about to read 5, iclass 7, count 0 2006.257.10:33:41.99#ibcon#read 5, iclass 7, count 0 2006.257.10:33:41.99#ibcon#about to read 6, iclass 7, count 0 2006.257.10:33:41.99#ibcon#read 6, iclass 7, count 0 2006.257.10:33:41.99#ibcon#end of sib2, iclass 7, count 0 2006.257.10:33:41.99#ibcon#*after write, iclass 7, count 0 2006.257.10:33:41.99#ibcon#*before return 0, iclass 7, count 0 2006.257.10:33:41.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:41.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:41.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:33:41.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:33:41.99$vck44/va=6,4 2006.257.10:33:41.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.10:33:41.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.10:33:41.99#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:41.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:42.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:42.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:42.05#ibcon#enter wrdev, iclass 11, count 2 2006.257.10:33:42.05#ibcon#first serial, iclass 11, count 2 2006.257.10:33:42.05#ibcon#enter sib2, iclass 11, count 2 2006.257.10:33:42.05#ibcon#flushed, iclass 11, count 2 2006.257.10:33:42.05#ibcon#about to write, iclass 11, count 2 2006.257.10:33:42.05#ibcon#wrote, iclass 11, count 2 2006.257.10:33:42.05#ibcon#about to read 3, iclass 11, count 2 2006.257.10:33:42.07#ibcon#read 3, iclass 11, count 2 2006.257.10:33:42.07#ibcon#about to read 4, iclass 11, count 2 2006.257.10:33:42.07#ibcon#read 4, iclass 11, count 2 2006.257.10:33:42.07#ibcon#about to read 5, iclass 11, count 2 2006.257.10:33:42.07#ibcon#read 5, iclass 11, count 2 2006.257.10:33:42.07#ibcon#about to read 6, iclass 11, count 2 2006.257.10:33:42.07#ibcon#read 6, iclass 11, count 2 2006.257.10:33:42.07#ibcon#end of sib2, iclass 11, count 2 2006.257.10:33:42.07#ibcon#*mode == 0, iclass 11, count 2 2006.257.10:33:42.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.10:33:42.07#ibcon#[25=AT06-04\r\n] 2006.257.10:33:42.07#ibcon#*before write, iclass 11, count 2 2006.257.10:33:42.07#ibcon#enter sib2, iclass 11, count 2 2006.257.10:33:42.07#ibcon#flushed, iclass 11, count 2 2006.257.10:33:42.07#ibcon#about to write, iclass 11, count 2 2006.257.10:33:42.07#ibcon#wrote, iclass 11, count 2 2006.257.10:33:42.07#ibcon#about to read 3, iclass 11, count 2 2006.257.10:33:42.10#ibcon#read 3, iclass 11, count 2 2006.257.10:33:42.10#ibcon#about to read 4, iclass 11, count 2 2006.257.10:33:42.10#ibcon#read 4, iclass 11, count 2 2006.257.10:33:42.10#ibcon#about to read 5, iclass 11, count 2 2006.257.10:33:42.10#ibcon#read 5, iclass 11, count 2 2006.257.10:33:42.10#ibcon#about to read 6, iclass 11, count 2 2006.257.10:33:42.10#ibcon#read 6, iclass 11, count 2 2006.257.10:33:42.10#ibcon#end of sib2, iclass 11, count 2 2006.257.10:33:42.10#ibcon#*after write, iclass 11, count 2 2006.257.10:33:42.10#ibcon#*before return 0, iclass 11, count 2 2006.257.10:33:42.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:42.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:42.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.10:33:42.10#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:42.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:42.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:42.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:42.22#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:33:42.22#ibcon#first serial, iclass 11, count 0 2006.257.10:33:42.22#ibcon#enter sib2, iclass 11, count 0 2006.257.10:33:42.22#ibcon#flushed, iclass 11, count 0 2006.257.10:33:42.22#ibcon#about to write, iclass 11, count 0 2006.257.10:33:42.22#ibcon#wrote, iclass 11, count 0 2006.257.10:33:42.22#ibcon#about to read 3, iclass 11, count 0 2006.257.10:33:42.24#ibcon#read 3, iclass 11, count 0 2006.257.10:33:42.24#ibcon#about to read 4, iclass 11, count 0 2006.257.10:33:42.24#ibcon#read 4, iclass 11, count 0 2006.257.10:33:42.24#ibcon#about to read 5, iclass 11, count 0 2006.257.10:33:42.24#ibcon#read 5, iclass 11, count 0 2006.257.10:33:42.24#ibcon#about to read 6, iclass 11, count 0 2006.257.10:33:42.24#ibcon#read 6, iclass 11, count 0 2006.257.10:33:42.24#ibcon#end of sib2, iclass 11, count 0 2006.257.10:33:42.24#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:33:42.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:33:42.24#ibcon#[25=USB\r\n] 2006.257.10:33:42.24#ibcon#*before write, iclass 11, count 0 2006.257.10:33:42.24#ibcon#enter sib2, iclass 11, count 0 2006.257.10:33:42.24#ibcon#flushed, iclass 11, count 0 2006.257.10:33:42.24#ibcon#about to write, iclass 11, count 0 2006.257.10:33:42.24#ibcon#wrote, iclass 11, count 0 2006.257.10:33:42.24#ibcon#about to read 3, iclass 11, count 0 2006.257.10:33:42.27#ibcon#read 3, iclass 11, count 0 2006.257.10:33:42.27#ibcon#about to read 4, iclass 11, count 0 2006.257.10:33:42.27#ibcon#read 4, iclass 11, count 0 2006.257.10:33:42.27#ibcon#about to read 5, iclass 11, count 0 2006.257.10:33:42.27#ibcon#read 5, iclass 11, count 0 2006.257.10:33:42.27#ibcon#about to read 6, iclass 11, count 0 2006.257.10:33:42.27#ibcon#read 6, iclass 11, count 0 2006.257.10:33:42.27#ibcon#end of sib2, iclass 11, count 0 2006.257.10:33:42.27#ibcon#*after write, iclass 11, count 0 2006.257.10:33:42.27#ibcon#*before return 0, iclass 11, count 0 2006.257.10:33:42.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:42.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:42.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:33:42.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:33:42.27$vck44/valo=7,864.99 2006.257.10:33:42.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.10:33:42.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.10:33:42.27#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:42.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:42.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:42.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:42.27#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:33:42.27#ibcon#first serial, iclass 13, count 0 2006.257.10:33:42.27#ibcon#enter sib2, iclass 13, count 0 2006.257.10:33:42.27#ibcon#flushed, iclass 13, count 0 2006.257.10:33:42.27#ibcon#about to write, iclass 13, count 0 2006.257.10:33:42.27#ibcon#wrote, iclass 13, count 0 2006.257.10:33:42.27#ibcon#about to read 3, iclass 13, count 0 2006.257.10:33:42.29#ibcon#read 3, iclass 13, count 0 2006.257.10:33:42.29#ibcon#about to read 4, iclass 13, count 0 2006.257.10:33:42.29#ibcon#read 4, iclass 13, count 0 2006.257.10:33:42.29#ibcon#about to read 5, iclass 13, count 0 2006.257.10:33:42.29#ibcon#read 5, iclass 13, count 0 2006.257.10:33:42.29#ibcon#about to read 6, iclass 13, count 0 2006.257.10:33:42.29#ibcon#read 6, iclass 13, count 0 2006.257.10:33:42.29#ibcon#end of sib2, iclass 13, count 0 2006.257.10:33:42.29#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:33:42.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:33:42.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:33:42.29#ibcon#*before write, iclass 13, count 0 2006.257.10:33:42.29#ibcon#enter sib2, iclass 13, count 0 2006.257.10:33:42.29#ibcon#flushed, iclass 13, count 0 2006.257.10:33:42.29#ibcon#about to write, iclass 13, count 0 2006.257.10:33:42.29#ibcon#wrote, iclass 13, count 0 2006.257.10:33:42.29#ibcon#about to read 3, iclass 13, count 0 2006.257.10:33:42.33#ibcon#read 3, iclass 13, count 0 2006.257.10:33:42.33#ibcon#about to read 4, iclass 13, count 0 2006.257.10:33:42.33#ibcon#read 4, iclass 13, count 0 2006.257.10:33:42.33#ibcon#about to read 5, iclass 13, count 0 2006.257.10:33:42.33#ibcon#read 5, iclass 13, count 0 2006.257.10:33:42.33#ibcon#about to read 6, iclass 13, count 0 2006.257.10:33:42.33#ibcon#read 6, iclass 13, count 0 2006.257.10:33:42.33#ibcon#end of sib2, iclass 13, count 0 2006.257.10:33:42.33#ibcon#*after write, iclass 13, count 0 2006.257.10:33:42.33#ibcon#*before return 0, iclass 13, count 0 2006.257.10:33:42.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:42.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:42.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:33:42.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:33:42.33$vck44/va=7,4 2006.257.10:33:42.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.10:33:42.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.10:33:42.33#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:42.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:42.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:42.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:42.39#ibcon#enter wrdev, iclass 15, count 2 2006.257.10:33:42.39#ibcon#first serial, iclass 15, count 2 2006.257.10:33:42.39#ibcon#enter sib2, iclass 15, count 2 2006.257.10:33:42.39#ibcon#flushed, iclass 15, count 2 2006.257.10:33:42.39#ibcon#about to write, iclass 15, count 2 2006.257.10:33:42.39#ibcon#wrote, iclass 15, count 2 2006.257.10:33:42.39#ibcon#about to read 3, iclass 15, count 2 2006.257.10:33:42.41#ibcon#read 3, iclass 15, count 2 2006.257.10:33:42.41#ibcon#about to read 4, iclass 15, count 2 2006.257.10:33:42.41#ibcon#read 4, iclass 15, count 2 2006.257.10:33:42.41#ibcon#about to read 5, iclass 15, count 2 2006.257.10:33:42.41#ibcon#read 5, iclass 15, count 2 2006.257.10:33:42.41#ibcon#about to read 6, iclass 15, count 2 2006.257.10:33:42.41#ibcon#read 6, iclass 15, count 2 2006.257.10:33:42.41#ibcon#end of sib2, iclass 15, count 2 2006.257.10:33:42.41#ibcon#*mode == 0, iclass 15, count 2 2006.257.10:33:42.41#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.10:33:42.41#ibcon#[25=AT07-04\r\n] 2006.257.10:33:42.41#ibcon#*before write, iclass 15, count 2 2006.257.10:33:42.41#ibcon#enter sib2, iclass 15, count 2 2006.257.10:33:42.41#ibcon#flushed, iclass 15, count 2 2006.257.10:33:42.41#ibcon#about to write, iclass 15, count 2 2006.257.10:33:42.41#ibcon#wrote, iclass 15, count 2 2006.257.10:33:42.41#ibcon#about to read 3, iclass 15, count 2 2006.257.10:33:42.44#ibcon#read 3, iclass 15, count 2 2006.257.10:33:42.44#ibcon#about to read 4, iclass 15, count 2 2006.257.10:33:42.44#ibcon#read 4, iclass 15, count 2 2006.257.10:33:42.44#ibcon#about to read 5, iclass 15, count 2 2006.257.10:33:42.44#ibcon#read 5, iclass 15, count 2 2006.257.10:33:42.44#ibcon#about to read 6, iclass 15, count 2 2006.257.10:33:42.44#ibcon#read 6, iclass 15, count 2 2006.257.10:33:42.44#ibcon#end of sib2, iclass 15, count 2 2006.257.10:33:42.44#ibcon#*after write, iclass 15, count 2 2006.257.10:33:42.44#ibcon#*before return 0, iclass 15, count 2 2006.257.10:33:42.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:42.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:42.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.10:33:42.44#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:42.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:42.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:42.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:42.56#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:33:42.56#ibcon#first serial, iclass 15, count 0 2006.257.10:33:42.56#ibcon#enter sib2, iclass 15, count 0 2006.257.10:33:42.56#ibcon#flushed, iclass 15, count 0 2006.257.10:33:42.56#ibcon#about to write, iclass 15, count 0 2006.257.10:33:42.56#ibcon#wrote, iclass 15, count 0 2006.257.10:33:42.56#ibcon#about to read 3, iclass 15, count 0 2006.257.10:33:42.58#ibcon#read 3, iclass 15, count 0 2006.257.10:33:42.58#ibcon#about to read 4, iclass 15, count 0 2006.257.10:33:42.58#ibcon#read 4, iclass 15, count 0 2006.257.10:33:42.58#ibcon#about to read 5, iclass 15, count 0 2006.257.10:33:42.58#ibcon#read 5, iclass 15, count 0 2006.257.10:33:42.58#ibcon#about to read 6, iclass 15, count 0 2006.257.10:33:42.58#ibcon#read 6, iclass 15, count 0 2006.257.10:33:42.58#ibcon#end of sib2, iclass 15, count 0 2006.257.10:33:42.58#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:33:42.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:33:42.58#ibcon#[25=USB\r\n] 2006.257.10:33:42.58#ibcon#*before write, iclass 15, count 0 2006.257.10:33:42.58#ibcon#enter sib2, iclass 15, count 0 2006.257.10:33:42.58#ibcon#flushed, iclass 15, count 0 2006.257.10:33:42.58#ibcon#about to write, iclass 15, count 0 2006.257.10:33:42.58#ibcon#wrote, iclass 15, count 0 2006.257.10:33:42.58#ibcon#about to read 3, iclass 15, count 0 2006.257.10:33:42.61#ibcon#read 3, iclass 15, count 0 2006.257.10:33:42.61#ibcon#about to read 4, iclass 15, count 0 2006.257.10:33:42.61#ibcon#read 4, iclass 15, count 0 2006.257.10:33:42.61#ibcon#about to read 5, iclass 15, count 0 2006.257.10:33:42.61#ibcon#read 5, iclass 15, count 0 2006.257.10:33:42.61#ibcon#about to read 6, iclass 15, count 0 2006.257.10:33:42.61#ibcon#read 6, iclass 15, count 0 2006.257.10:33:42.61#ibcon#end of sib2, iclass 15, count 0 2006.257.10:33:42.61#ibcon#*after write, iclass 15, count 0 2006.257.10:33:42.61#ibcon#*before return 0, iclass 15, count 0 2006.257.10:33:42.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:42.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:42.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:33:42.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:33:42.61$vck44/valo=8,884.99 2006.257.10:33:42.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.10:33:42.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.10:33:42.61#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:42.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:42.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:42.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:42.61#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:33:42.61#ibcon#first serial, iclass 17, count 0 2006.257.10:33:42.61#ibcon#enter sib2, iclass 17, count 0 2006.257.10:33:42.61#ibcon#flushed, iclass 17, count 0 2006.257.10:33:42.61#ibcon#about to write, iclass 17, count 0 2006.257.10:33:42.61#ibcon#wrote, iclass 17, count 0 2006.257.10:33:42.61#ibcon#about to read 3, iclass 17, count 0 2006.257.10:33:42.63#ibcon#read 3, iclass 17, count 0 2006.257.10:33:42.63#ibcon#about to read 4, iclass 17, count 0 2006.257.10:33:42.63#ibcon#read 4, iclass 17, count 0 2006.257.10:33:42.63#ibcon#about to read 5, iclass 17, count 0 2006.257.10:33:42.63#ibcon#read 5, iclass 17, count 0 2006.257.10:33:42.63#ibcon#about to read 6, iclass 17, count 0 2006.257.10:33:42.63#ibcon#read 6, iclass 17, count 0 2006.257.10:33:42.63#ibcon#end of sib2, iclass 17, count 0 2006.257.10:33:42.63#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:33:42.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:33:42.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:33:42.63#ibcon#*before write, iclass 17, count 0 2006.257.10:33:42.63#ibcon#enter sib2, iclass 17, count 0 2006.257.10:33:42.63#ibcon#flushed, iclass 17, count 0 2006.257.10:33:42.63#ibcon#about to write, iclass 17, count 0 2006.257.10:33:42.63#ibcon#wrote, iclass 17, count 0 2006.257.10:33:42.63#ibcon#about to read 3, iclass 17, count 0 2006.257.10:33:42.67#ibcon#read 3, iclass 17, count 0 2006.257.10:33:42.67#ibcon#about to read 4, iclass 17, count 0 2006.257.10:33:42.67#ibcon#read 4, iclass 17, count 0 2006.257.10:33:42.67#ibcon#about to read 5, iclass 17, count 0 2006.257.10:33:42.67#ibcon#read 5, iclass 17, count 0 2006.257.10:33:42.67#ibcon#about to read 6, iclass 17, count 0 2006.257.10:33:42.67#ibcon#read 6, iclass 17, count 0 2006.257.10:33:42.67#ibcon#end of sib2, iclass 17, count 0 2006.257.10:33:42.67#ibcon#*after write, iclass 17, count 0 2006.257.10:33:42.67#ibcon#*before return 0, iclass 17, count 0 2006.257.10:33:42.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:42.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:42.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:33:42.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:33:42.67$vck44/va=8,4 2006.257.10:33:42.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.10:33:42.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.10:33:42.67#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:42.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:33:42.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:33:42.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:33:42.73#ibcon#enter wrdev, iclass 19, count 2 2006.257.10:33:42.73#ibcon#first serial, iclass 19, count 2 2006.257.10:33:42.73#ibcon#enter sib2, iclass 19, count 2 2006.257.10:33:42.73#ibcon#flushed, iclass 19, count 2 2006.257.10:33:42.73#ibcon#about to write, iclass 19, count 2 2006.257.10:33:42.73#ibcon#wrote, iclass 19, count 2 2006.257.10:33:42.73#ibcon#about to read 3, iclass 19, count 2 2006.257.10:33:42.75#ibcon#read 3, iclass 19, count 2 2006.257.10:33:42.75#ibcon#about to read 4, iclass 19, count 2 2006.257.10:33:42.75#ibcon#read 4, iclass 19, count 2 2006.257.10:33:42.75#ibcon#about to read 5, iclass 19, count 2 2006.257.10:33:42.75#ibcon#read 5, iclass 19, count 2 2006.257.10:33:42.75#ibcon#about to read 6, iclass 19, count 2 2006.257.10:33:42.75#ibcon#read 6, iclass 19, count 2 2006.257.10:33:42.75#ibcon#end of sib2, iclass 19, count 2 2006.257.10:33:42.75#ibcon#*mode == 0, iclass 19, count 2 2006.257.10:33:42.75#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.10:33:42.75#ibcon#[25=AT08-04\r\n] 2006.257.10:33:42.75#ibcon#*before write, iclass 19, count 2 2006.257.10:33:42.75#ibcon#enter sib2, iclass 19, count 2 2006.257.10:33:42.75#ibcon#flushed, iclass 19, count 2 2006.257.10:33:42.75#ibcon#about to write, iclass 19, count 2 2006.257.10:33:42.75#ibcon#wrote, iclass 19, count 2 2006.257.10:33:42.75#ibcon#about to read 3, iclass 19, count 2 2006.257.10:33:42.78#ibcon#read 3, iclass 19, count 2 2006.257.10:33:42.78#ibcon#about to read 4, iclass 19, count 2 2006.257.10:33:42.78#ibcon#read 4, iclass 19, count 2 2006.257.10:33:42.78#ibcon#about to read 5, iclass 19, count 2 2006.257.10:33:42.78#ibcon#read 5, iclass 19, count 2 2006.257.10:33:42.78#ibcon#about to read 6, iclass 19, count 2 2006.257.10:33:42.78#ibcon#read 6, iclass 19, count 2 2006.257.10:33:42.78#ibcon#end of sib2, iclass 19, count 2 2006.257.10:33:42.78#ibcon#*after write, iclass 19, count 2 2006.257.10:33:42.78#ibcon#*before return 0, iclass 19, count 2 2006.257.10:33:42.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:33:42.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:33:42.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.10:33:42.78#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:42.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:33:42.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:33:42.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:33:42.90#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:33:42.90#ibcon#first serial, iclass 19, count 0 2006.257.10:33:42.90#ibcon#enter sib2, iclass 19, count 0 2006.257.10:33:42.90#ibcon#flushed, iclass 19, count 0 2006.257.10:33:42.90#ibcon#about to write, iclass 19, count 0 2006.257.10:33:42.90#ibcon#wrote, iclass 19, count 0 2006.257.10:33:42.90#ibcon#about to read 3, iclass 19, count 0 2006.257.10:33:42.92#ibcon#read 3, iclass 19, count 0 2006.257.10:33:42.92#ibcon#about to read 4, iclass 19, count 0 2006.257.10:33:42.92#ibcon#read 4, iclass 19, count 0 2006.257.10:33:42.92#ibcon#about to read 5, iclass 19, count 0 2006.257.10:33:42.92#ibcon#read 5, iclass 19, count 0 2006.257.10:33:42.92#ibcon#about to read 6, iclass 19, count 0 2006.257.10:33:42.92#ibcon#read 6, iclass 19, count 0 2006.257.10:33:42.92#ibcon#end of sib2, iclass 19, count 0 2006.257.10:33:42.92#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:33:42.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:33:42.92#ibcon#[25=USB\r\n] 2006.257.10:33:42.92#ibcon#*before write, iclass 19, count 0 2006.257.10:33:42.92#ibcon#enter sib2, iclass 19, count 0 2006.257.10:33:42.92#ibcon#flushed, iclass 19, count 0 2006.257.10:33:42.92#ibcon#about to write, iclass 19, count 0 2006.257.10:33:42.92#ibcon#wrote, iclass 19, count 0 2006.257.10:33:42.92#ibcon#about to read 3, iclass 19, count 0 2006.257.10:33:42.95#ibcon#read 3, iclass 19, count 0 2006.257.10:33:42.95#ibcon#about to read 4, iclass 19, count 0 2006.257.10:33:42.95#ibcon#read 4, iclass 19, count 0 2006.257.10:33:42.95#ibcon#about to read 5, iclass 19, count 0 2006.257.10:33:42.95#ibcon#read 5, iclass 19, count 0 2006.257.10:33:42.95#ibcon#about to read 6, iclass 19, count 0 2006.257.10:33:42.95#ibcon#read 6, iclass 19, count 0 2006.257.10:33:42.95#ibcon#end of sib2, iclass 19, count 0 2006.257.10:33:42.95#ibcon#*after write, iclass 19, count 0 2006.257.10:33:42.95#ibcon#*before return 0, iclass 19, count 0 2006.257.10:33:42.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:33:42.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:33:42.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:33:42.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:33:42.95$vck44/vblo=1,629.99 2006.257.10:33:42.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.10:33:42.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.10:33:42.95#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:42.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:33:42.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:33:42.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:33:42.95#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:33:42.95#ibcon#first serial, iclass 21, count 0 2006.257.10:33:42.95#ibcon#enter sib2, iclass 21, count 0 2006.257.10:33:42.95#ibcon#flushed, iclass 21, count 0 2006.257.10:33:42.95#ibcon#about to write, iclass 21, count 0 2006.257.10:33:42.95#ibcon#wrote, iclass 21, count 0 2006.257.10:33:42.95#ibcon#about to read 3, iclass 21, count 0 2006.257.10:33:42.97#ibcon#read 3, iclass 21, count 0 2006.257.10:33:42.97#ibcon#about to read 4, iclass 21, count 0 2006.257.10:33:42.97#ibcon#read 4, iclass 21, count 0 2006.257.10:33:42.97#ibcon#about to read 5, iclass 21, count 0 2006.257.10:33:42.97#ibcon#read 5, iclass 21, count 0 2006.257.10:33:42.97#ibcon#about to read 6, iclass 21, count 0 2006.257.10:33:42.97#ibcon#read 6, iclass 21, count 0 2006.257.10:33:42.97#ibcon#end of sib2, iclass 21, count 0 2006.257.10:33:42.97#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:33:42.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:33:42.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:33:42.97#ibcon#*before write, iclass 21, count 0 2006.257.10:33:42.97#ibcon#enter sib2, iclass 21, count 0 2006.257.10:33:42.97#ibcon#flushed, iclass 21, count 0 2006.257.10:33:42.97#ibcon#about to write, iclass 21, count 0 2006.257.10:33:42.97#ibcon#wrote, iclass 21, count 0 2006.257.10:33:42.97#ibcon#about to read 3, iclass 21, count 0 2006.257.10:33:43.01#ibcon#read 3, iclass 21, count 0 2006.257.10:33:43.01#ibcon#about to read 4, iclass 21, count 0 2006.257.10:33:43.01#ibcon#read 4, iclass 21, count 0 2006.257.10:33:43.01#ibcon#about to read 5, iclass 21, count 0 2006.257.10:33:43.01#ibcon#read 5, iclass 21, count 0 2006.257.10:33:43.01#ibcon#about to read 6, iclass 21, count 0 2006.257.10:33:43.01#ibcon#read 6, iclass 21, count 0 2006.257.10:33:43.01#ibcon#end of sib2, iclass 21, count 0 2006.257.10:33:43.01#ibcon#*after write, iclass 21, count 0 2006.257.10:33:43.01#ibcon#*before return 0, iclass 21, count 0 2006.257.10:33:43.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:33:43.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:33:43.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:33:43.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:33:43.01$vck44/vb=1,4 2006.257.10:33:43.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.10:33:43.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.10:33:43.01#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:43.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:33:43.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:33:43.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:33:43.01#ibcon#enter wrdev, iclass 23, count 2 2006.257.10:33:43.01#ibcon#first serial, iclass 23, count 2 2006.257.10:33:43.01#ibcon#enter sib2, iclass 23, count 2 2006.257.10:33:43.01#ibcon#flushed, iclass 23, count 2 2006.257.10:33:43.01#ibcon#about to write, iclass 23, count 2 2006.257.10:33:43.01#ibcon#wrote, iclass 23, count 2 2006.257.10:33:43.01#ibcon#about to read 3, iclass 23, count 2 2006.257.10:33:43.03#ibcon#read 3, iclass 23, count 2 2006.257.10:33:43.03#ibcon#about to read 4, iclass 23, count 2 2006.257.10:33:43.03#ibcon#read 4, iclass 23, count 2 2006.257.10:33:43.03#ibcon#about to read 5, iclass 23, count 2 2006.257.10:33:43.03#ibcon#read 5, iclass 23, count 2 2006.257.10:33:43.03#ibcon#about to read 6, iclass 23, count 2 2006.257.10:33:43.03#ibcon#read 6, iclass 23, count 2 2006.257.10:33:43.03#ibcon#end of sib2, iclass 23, count 2 2006.257.10:33:43.03#ibcon#*mode == 0, iclass 23, count 2 2006.257.10:33:43.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.10:33:43.03#ibcon#[27=AT01-04\r\n] 2006.257.10:33:43.03#ibcon#*before write, iclass 23, count 2 2006.257.10:33:43.03#ibcon#enter sib2, iclass 23, count 2 2006.257.10:33:43.03#ibcon#flushed, iclass 23, count 2 2006.257.10:33:43.03#ibcon#about to write, iclass 23, count 2 2006.257.10:33:43.03#ibcon#wrote, iclass 23, count 2 2006.257.10:33:43.03#ibcon#about to read 3, iclass 23, count 2 2006.257.10:33:43.06#ibcon#read 3, iclass 23, count 2 2006.257.10:33:43.06#ibcon#about to read 4, iclass 23, count 2 2006.257.10:33:43.06#ibcon#read 4, iclass 23, count 2 2006.257.10:33:43.06#ibcon#about to read 5, iclass 23, count 2 2006.257.10:33:43.06#ibcon#read 5, iclass 23, count 2 2006.257.10:33:43.06#ibcon#about to read 6, iclass 23, count 2 2006.257.10:33:43.06#ibcon#read 6, iclass 23, count 2 2006.257.10:33:43.06#ibcon#end of sib2, iclass 23, count 2 2006.257.10:33:43.06#ibcon#*after write, iclass 23, count 2 2006.257.10:33:43.06#ibcon#*before return 0, iclass 23, count 2 2006.257.10:33:43.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:33:43.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:33:43.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.10:33:43.06#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:43.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:33:43.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:33:43.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:33:43.18#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:33:43.18#ibcon#first serial, iclass 23, count 0 2006.257.10:33:43.18#ibcon#enter sib2, iclass 23, count 0 2006.257.10:33:43.18#ibcon#flushed, iclass 23, count 0 2006.257.10:33:43.18#ibcon#about to write, iclass 23, count 0 2006.257.10:33:43.18#ibcon#wrote, iclass 23, count 0 2006.257.10:33:43.18#ibcon#about to read 3, iclass 23, count 0 2006.257.10:33:43.20#ibcon#read 3, iclass 23, count 0 2006.257.10:33:43.20#ibcon#about to read 4, iclass 23, count 0 2006.257.10:33:43.20#ibcon#read 4, iclass 23, count 0 2006.257.10:33:43.20#ibcon#about to read 5, iclass 23, count 0 2006.257.10:33:43.20#ibcon#read 5, iclass 23, count 0 2006.257.10:33:43.20#ibcon#about to read 6, iclass 23, count 0 2006.257.10:33:43.20#ibcon#read 6, iclass 23, count 0 2006.257.10:33:43.20#ibcon#end of sib2, iclass 23, count 0 2006.257.10:33:43.20#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:33:43.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:33:43.20#ibcon#[27=USB\r\n] 2006.257.10:33:43.20#ibcon#*before write, iclass 23, count 0 2006.257.10:33:43.20#ibcon#enter sib2, iclass 23, count 0 2006.257.10:33:43.20#ibcon#flushed, iclass 23, count 0 2006.257.10:33:43.20#ibcon#about to write, iclass 23, count 0 2006.257.10:33:43.20#ibcon#wrote, iclass 23, count 0 2006.257.10:33:43.20#ibcon#about to read 3, iclass 23, count 0 2006.257.10:33:43.23#ibcon#read 3, iclass 23, count 0 2006.257.10:33:43.23#ibcon#about to read 4, iclass 23, count 0 2006.257.10:33:43.23#ibcon#read 4, iclass 23, count 0 2006.257.10:33:43.23#ibcon#about to read 5, iclass 23, count 0 2006.257.10:33:43.23#ibcon#read 5, iclass 23, count 0 2006.257.10:33:43.23#ibcon#about to read 6, iclass 23, count 0 2006.257.10:33:43.23#ibcon#read 6, iclass 23, count 0 2006.257.10:33:43.23#ibcon#end of sib2, iclass 23, count 0 2006.257.10:33:43.23#ibcon#*after write, iclass 23, count 0 2006.257.10:33:43.23#ibcon#*before return 0, iclass 23, count 0 2006.257.10:33:43.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:33:43.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:33:43.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:33:43.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:33:43.23$vck44/vblo=2,634.99 2006.257.10:33:43.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.10:33:43.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.10:33:43.23#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:43.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:33:43.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:33:43.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:33:43.23#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:33:43.23#ibcon#first serial, iclass 25, count 0 2006.257.10:33:43.23#ibcon#enter sib2, iclass 25, count 0 2006.257.10:33:43.23#ibcon#flushed, iclass 25, count 0 2006.257.10:33:43.23#ibcon#about to write, iclass 25, count 0 2006.257.10:33:43.23#ibcon#wrote, iclass 25, count 0 2006.257.10:33:43.23#ibcon#about to read 3, iclass 25, count 0 2006.257.10:33:43.25#ibcon#read 3, iclass 25, count 0 2006.257.10:33:43.25#ibcon#about to read 4, iclass 25, count 0 2006.257.10:33:43.25#ibcon#read 4, iclass 25, count 0 2006.257.10:33:43.25#ibcon#about to read 5, iclass 25, count 0 2006.257.10:33:43.25#ibcon#read 5, iclass 25, count 0 2006.257.10:33:43.25#ibcon#about to read 6, iclass 25, count 0 2006.257.10:33:43.25#ibcon#read 6, iclass 25, count 0 2006.257.10:33:43.25#ibcon#end of sib2, iclass 25, count 0 2006.257.10:33:43.25#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:33:43.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:33:43.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:33:43.25#ibcon#*before write, iclass 25, count 0 2006.257.10:33:43.25#ibcon#enter sib2, iclass 25, count 0 2006.257.10:33:43.25#ibcon#flushed, iclass 25, count 0 2006.257.10:33:43.25#ibcon#about to write, iclass 25, count 0 2006.257.10:33:43.25#ibcon#wrote, iclass 25, count 0 2006.257.10:33:43.25#ibcon#about to read 3, iclass 25, count 0 2006.257.10:33:43.29#ibcon#read 3, iclass 25, count 0 2006.257.10:33:43.29#ibcon#about to read 4, iclass 25, count 0 2006.257.10:33:43.29#ibcon#read 4, iclass 25, count 0 2006.257.10:33:43.29#ibcon#about to read 5, iclass 25, count 0 2006.257.10:33:43.29#ibcon#read 5, iclass 25, count 0 2006.257.10:33:43.29#ibcon#about to read 6, iclass 25, count 0 2006.257.10:33:43.29#ibcon#read 6, iclass 25, count 0 2006.257.10:33:43.29#ibcon#end of sib2, iclass 25, count 0 2006.257.10:33:43.29#ibcon#*after write, iclass 25, count 0 2006.257.10:33:43.29#ibcon#*before return 0, iclass 25, count 0 2006.257.10:33:43.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:33:43.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:33:43.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:33:43.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:33:43.29$vck44/vb=2,5 2006.257.10:33:43.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.10:33:43.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.10:33:43.29#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:43.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:43.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:43.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:43.35#ibcon#enter wrdev, iclass 27, count 2 2006.257.10:33:43.35#ibcon#first serial, iclass 27, count 2 2006.257.10:33:43.35#ibcon#enter sib2, iclass 27, count 2 2006.257.10:33:43.35#ibcon#flushed, iclass 27, count 2 2006.257.10:33:43.35#ibcon#about to write, iclass 27, count 2 2006.257.10:33:43.35#ibcon#wrote, iclass 27, count 2 2006.257.10:33:43.35#ibcon#about to read 3, iclass 27, count 2 2006.257.10:33:43.37#ibcon#read 3, iclass 27, count 2 2006.257.10:33:43.37#ibcon#about to read 4, iclass 27, count 2 2006.257.10:33:43.37#ibcon#read 4, iclass 27, count 2 2006.257.10:33:43.37#ibcon#about to read 5, iclass 27, count 2 2006.257.10:33:43.37#ibcon#read 5, iclass 27, count 2 2006.257.10:33:43.37#ibcon#about to read 6, iclass 27, count 2 2006.257.10:33:43.37#ibcon#read 6, iclass 27, count 2 2006.257.10:33:43.37#ibcon#end of sib2, iclass 27, count 2 2006.257.10:33:43.37#ibcon#*mode == 0, iclass 27, count 2 2006.257.10:33:43.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.10:33:43.37#ibcon#[27=AT02-05\r\n] 2006.257.10:33:43.37#ibcon#*before write, iclass 27, count 2 2006.257.10:33:43.37#ibcon#enter sib2, iclass 27, count 2 2006.257.10:33:43.37#ibcon#flushed, iclass 27, count 2 2006.257.10:33:43.37#ibcon#about to write, iclass 27, count 2 2006.257.10:33:43.37#ibcon#wrote, iclass 27, count 2 2006.257.10:33:43.37#ibcon#about to read 3, iclass 27, count 2 2006.257.10:33:43.40#ibcon#read 3, iclass 27, count 2 2006.257.10:33:43.40#ibcon#about to read 4, iclass 27, count 2 2006.257.10:33:43.40#ibcon#read 4, iclass 27, count 2 2006.257.10:33:43.40#ibcon#about to read 5, iclass 27, count 2 2006.257.10:33:43.40#ibcon#read 5, iclass 27, count 2 2006.257.10:33:43.40#ibcon#about to read 6, iclass 27, count 2 2006.257.10:33:43.40#ibcon#read 6, iclass 27, count 2 2006.257.10:33:43.40#ibcon#end of sib2, iclass 27, count 2 2006.257.10:33:43.40#ibcon#*after write, iclass 27, count 2 2006.257.10:33:43.40#ibcon#*before return 0, iclass 27, count 2 2006.257.10:33:43.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:43.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:33:43.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.10:33:43.40#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:43.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:43.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:43.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:43.52#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:33:43.52#ibcon#first serial, iclass 27, count 0 2006.257.10:33:43.52#ibcon#enter sib2, iclass 27, count 0 2006.257.10:33:43.52#ibcon#flushed, iclass 27, count 0 2006.257.10:33:43.52#ibcon#about to write, iclass 27, count 0 2006.257.10:33:43.52#ibcon#wrote, iclass 27, count 0 2006.257.10:33:43.52#ibcon#about to read 3, iclass 27, count 0 2006.257.10:33:43.54#ibcon#read 3, iclass 27, count 0 2006.257.10:33:43.54#ibcon#about to read 4, iclass 27, count 0 2006.257.10:33:43.54#ibcon#read 4, iclass 27, count 0 2006.257.10:33:43.54#ibcon#about to read 5, iclass 27, count 0 2006.257.10:33:43.54#ibcon#read 5, iclass 27, count 0 2006.257.10:33:43.54#ibcon#about to read 6, iclass 27, count 0 2006.257.10:33:43.54#ibcon#read 6, iclass 27, count 0 2006.257.10:33:43.54#ibcon#end of sib2, iclass 27, count 0 2006.257.10:33:43.54#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:33:43.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:33:43.54#ibcon#[27=USB\r\n] 2006.257.10:33:43.54#ibcon#*before write, iclass 27, count 0 2006.257.10:33:43.54#ibcon#enter sib2, iclass 27, count 0 2006.257.10:33:43.54#ibcon#flushed, iclass 27, count 0 2006.257.10:33:43.54#ibcon#about to write, iclass 27, count 0 2006.257.10:33:43.54#ibcon#wrote, iclass 27, count 0 2006.257.10:33:43.54#ibcon#about to read 3, iclass 27, count 0 2006.257.10:33:43.57#ibcon#read 3, iclass 27, count 0 2006.257.10:33:43.57#ibcon#about to read 4, iclass 27, count 0 2006.257.10:33:43.57#ibcon#read 4, iclass 27, count 0 2006.257.10:33:43.57#ibcon#about to read 5, iclass 27, count 0 2006.257.10:33:43.57#ibcon#read 5, iclass 27, count 0 2006.257.10:33:43.57#ibcon#about to read 6, iclass 27, count 0 2006.257.10:33:43.57#ibcon#read 6, iclass 27, count 0 2006.257.10:33:43.57#ibcon#end of sib2, iclass 27, count 0 2006.257.10:33:43.57#ibcon#*after write, iclass 27, count 0 2006.257.10:33:43.57#ibcon#*before return 0, iclass 27, count 0 2006.257.10:33:43.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:43.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:33:43.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:33:43.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:33:43.57$vck44/vblo=3,649.99 2006.257.10:33:43.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.10:33:43.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.10:33:43.57#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:43.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:43.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:43.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:43.57#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:33:43.57#ibcon#first serial, iclass 29, count 0 2006.257.10:33:43.57#ibcon#enter sib2, iclass 29, count 0 2006.257.10:33:43.57#ibcon#flushed, iclass 29, count 0 2006.257.10:33:43.57#ibcon#about to write, iclass 29, count 0 2006.257.10:33:43.57#ibcon#wrote, iclass 29, count 0 2006.257.10:33:43.57#ibcon#about to read 3, iclass 29, count 0 2006.257.10:33:43.59#ibcon#read 3, iclass 29, count 0 2006.257.10:33:43.59#ibcon#about to read 4, iclass 29, count 0 2006.257.10:33:43.59#ibcon#read 4, iclass 29, count 0 2006.257.10:33:43.59#ibcon#about to read 5, iclass 29, count 0 2006.257.10:33:43.59#ibcon#read 5, iclass 29, count 0 2006.257.10:33:43.59#ibcon#about to read 6, iclass 29, count 0 2006.257.10:33:43.59#ibcon#read 6, iclass 29, count 0 2006.257.10:33:43.59#ibcon#end of sib2, iclass 29, count 0 2006.257.10:33:43.59#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:33:43.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:33:43.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:33:43.59#ibcon#*before write, iclass 29, count 0 2006.257.10:33:43.59#ibcon#enter sib2, iclass 29, count 0 2006.257.10:33:43.59#ibcon#flushed, iclass 29, count 0 2006.257.10:33:43.59#ibcon#about to write, iclass 29, count 0 2006.257.10:33:43.59#ibcon#wrote, iclass 29, count 0 2006.257.10:33:43.59#ibcon#about to read 3, iclass 29, count 0 2006.257.10:33:43.63#ibcon#read 3, iclass 29, count 0 2006.257.10:33:43.63#ibcon#about to read 4, iclass 29, count 0 2006.257.10:33:43.63#ibcon#read 4, iclass 29, count 0 2006.257.10:33:43.63#ibcon#about to read 5, iclass 29, count 0 2006.257.10:33:43.63#ibcon#read 5, iclass 29, count 0 2006.257.10:33:43.63#ibcon#about to read 6, iclass 29, count 0 2006.257.10:33:43.63#ibcon#read 6, iclass 29, count 0 2006.257.10:33:43.63#ibcon#end of sib2, iclass 29, count 0 2006.257.10:33:43.63#ibcon#*after write, iclass 29, count 0 2006.257.10:33:43.63#ibcon#*before return 0, iclass 29, count 0 2006.257.10:33:43.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:43.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:33:43.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:33:43.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:33:43.63$vck44/vb=3,4 2006.257.10:33:43.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.10:33:43.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.10:33:43.63#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:43.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:43.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:43.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:43.69#ibcon#enter wrdev, iclass 31, count 2 2006.257.10:33:43.69#ibcon#first serial, iclass 31, count 2 2006.257.10:33:43.69#ibcon#enter sib2, iclass 31, count 2 2006.257.10:33:43.69#ibcon#flushed, iclass 31, count 2 2006.257.10:33:43.69#ibcon#about to write, iclass 31, count 2 2006.257.10:33:43.69#ibcon#wrote, iclass 31, count 2 2006.257.10:33:43.69#ibcon#about to read 3, iclass 31, count 2 2006.257.10:33:43.71#ibcon#read 3, iclass 31, count 2 2006.257.10:33:43.71#ibcon#about to read 4, iclass 31, count 2 2006.257.10:33:43.71#ibcon#read 4, iclass 31, count 2 2006.257.10:33:43.71#ibcon#about to read 5, iclass 31, count 2 2006.257.10:33:43.71#ibcon#read 5, iclass 31, count 2 2006.257.10:33:43.71#ibcon#about to read 6, iclass 31, count 2 2006.257.10:33:43.71#ibcon#read 6, iclass 31, count 2 2006.257.10:33:43.71#ibcon#end of sib2, iclass 31, count 2 2006.257.10:33:43.71#ibcon#*mode == 0, iclass 31, count 2 2006.257.10:33:43.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.10:33:43.71#ibcon#[27=AT03-04\r\n] 2006.257.10:33:43.71#ibcon#*before write, iclass 31, count 2 2006.257.10:33:43.71#ibcon#enter sib2, iclass 31, count 2 2006.257.10:33:43.71#ibcon#flushed, iclass 31, count 2 2006.257.10:33:43.71#ibcon#about to write, iclass 31, count 2 2006.257.10:33:43.71#ibcon#wrote, iclass 31, count 2 2006.257.10:33:43.71#ibcon#about to read 3, iclass 31, count 2 2006.257.10:33:43.74#ibcon#read 3, iclass 31, count 2 2006.257.10:33:43.74#ibcon#about to read 4, iclass 31, count 2 2006.257.10:33:43.74#ibcon#read 4, iclass 31, count 2 2006.257.10:33:43.74#ibcon#about to read 5, iclass 31, count 2 2006.257.10:33:43.74#ibcon#read 5, iclass 31, count 2 2006.257.10:33:43.74#ibcon#about to read 6, iclass 31, count 2 2006.257.10:33:43.74#ibcon#read 6, iclass 31, count 2 2006.257.10:33:43.74#ibcon#end of sib2, iclass 31, count 2 2006.257.10:33:43.74#ibcon#*after write, iclass 31, count 2 2006.257.10:33:43.74#ibcon#*before return 0, iclass 31, count 2 2006.257.10:33:43.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:43.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:33:43.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.10:33:43.74#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:43.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:43.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:43.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:43.86#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:33:43.86#ibcon#first serial, iclass 31, count 0 2006.257.10:33:43.86#ibcon#enter sib2, iclass 31, count 0 2006.257.10:33:43.86#ibcon#flushed, iclass 31, count 0 2006.257.10:33:43.86#ibcon#about to write, iclass 31, count 0 2006.257.10:33:43.86#ibcon#wrote, iclass 31, count 0 2006.257.10:33:43.86#ibcon#about to read 3, iclass 31, count 0 2006.257.10:33:43.88#ibcon#read 3, iclass 31, count 0 2006.257.10:33:43.88#ibcon#about to read 4, iclass 31, count 0 2006.257.10:33:43.88#ibcon#read 4, iclass 31, count 0 2006.257.10:33:43.88#ibcon#about to read 5, iclass 31, count 0 2006.257.10:33:43.88#ibcon#read 5, iclass 31, count 0 2006.257.10:33:43.88#ibcon#about to read 6, iclass 31, count 0 2006.257.10:33:43.88#ibcon#read 6, iclass 31, count 0 2006.257.10:33:43.88#ibcon#end of sib2, iclass 31, count 0 2006.257.10:33:43.88#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:33:43.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:33:43.88#ibcon#[27=USB\r\n] 2006.257.10:33:43.88#ibcon#*before write, iclass 31, count 0 2006.257.10:33:43.88#ibcon#enter sib2, iclass 31, count 0 2006.257.10:33:43.88#ibcon#flushed, iclass 31, count 0 2006.257.10:33:43.88#ibcon#about to write, iclass 31, count 0 2006.257.10:33:43.88#ibcon#wrote, iclass 31, count 0 2006.257.10:33:43.88#ibcon#about to read 3, iclass 31, count 0 2006.257.10:33:43.91#ibcon#read 3, iclass 31, count 0 2006.257.10:33:43.91#ibcon#about to read 4, iclass 31, count 0 2006.257.10:33:43.91#ibcon#read 4, iclass 31, count 0 2006.257.10:33:43.91#ibcon#about to read 5, iclass 31, count 0 2006.257.10:33:43.91#ibcon#read 5, iclass 31, count 0 2006.257.10:33:43.91#ibcon#about to read 6, iclass 31, count 0 2006.257.10:33:43.91#ibcon#read 6, iclass 31, count 0 2006.257.10:33:43.91#ibcon#end of sib2, iclass 31, count 0 2006.257.10:33:43.91#ibcon#*after write, iclass 31, count 0 2006.257.10:33:43.91#ibcon#*before return 0, iclass 31, count 0 2006.257.10:33:43.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:43.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:33:43.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:33:43.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:33:43.91$vck44/vblo=4,679.99 2006.257.10:33:43.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.10:33:43.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.10:33:43.91#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:43.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:43.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:43.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:43.91#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:33:43.91#ibcon#first serial, iclass 33, count 0 2006.257.10:33:43.91#ibcon#enter sib2, iclass 33, count 0 2006.257.10:33:43.91#ibcon#flushed, iclass 33, count 0 2006.257.10:33:43.91#ibcon#about to write, iclass 33, count 0 2006.257.10:33:43.91#ibcon#wrote, iclass 33, count 0 2006.257.10:33:43.91#ibcon#about to read 3, iclass 33, count 0 2006.257.10:33:43.93#ibcon#read 3, iclass 33, count 0 2006.257.10:33:43.93#ibcon#about to read 4, iclass 33, count 0 2006.257.10:33:43.93#ibcon#read 4, iclass 33, count 0 2006.257.10:33:43.93#ibcon#about to read 5, iclass 33, count 0 2006.257.10:33:43.93#ibcon#read 5, iclass 33, count 0 2006.257.10:33:43.93#ibcon#about to read 6, iclass 33, count 0 2006.257.10:33:43.93#ibcon#read 6, iclass 33, count 0 2006.257.10:33:43.93#ibcon#end of sib2, iclass 33, count 0 2006.257.10:33:43.93#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:33:43.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:33:43.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:33:43.93#ibcon#*before write, iclass 33, count 0 2006.257.10:33:43.93#ibcon#enter sib2, iclass 33, count 0 2006.257.10:33:43.93#ibcon#flushed, iclass 33, count 0 2006.257.10:33:43.93#ibcon#about to write, iclass 33, count 0 2006.257.10:33:43.93#ibcon#wrote, iclass 33, count 0 2006.257.10:33:43.93#ibcon#about to read 3, iclass 33, count 0 2006.257.10:33:43.97#ibcon#read 3, iclass 33, count 0 2006.257.10:33:43.97#ibcon#about to read 4, iclass 33, count 0 2006.257.10:33:43.97#ibcon#read 4, iclass 33, count 0 2006.257.10:33:43.97#ibcon#about to read 5, iclass 33, count 0 2006.257.10:33:43.97#ibcon#read 5, iclass 33, count 0 2006.257.10:33:43.97#ibcon#about to read 6, iclass 33, count 0 2006.257.10:33:43.97#ibcon#read 6, iclass 33, count 0 2006.257.10:33:43.97#ibcon#end of sib2, iclass 33, count 0 2006.257.10:33:43.97#ibcon#*after write, iclass 33, count 0 2006.257.10:33:43.97#ibcon#*before return 0, iclass 33, count 0 2006.257.10:33:43.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:43.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:33:43.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:33:43.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:33:43.97$vck44/vb=4,5 2006.257.10:33:43.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.10:33:43.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.10:33:43.97#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:43.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:44.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:44.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:44.03#ibcon#enter wrdev, iclass 35, count 2 2006.257.10:33:44.03#ibcon#first serial, iclass 35, count 2 2006.257.10:33:44.03#ibcon#enter sib2, iclass 35, count 2 2006.257.10:33:44.03#ibcon#flushed, iclass 35, count 2 2006.257.10:33:44.03#ibcon#about to write, iclass 35, count 2 2006.257.10:33:44.03#ibcon#wrote, iclass 35, count 2 2006.257.10:33:44.03#ibcon#about to read 3, iclass 35, count 2 2006.257.10:33:44.05#ibcon#read 3, iclass 35, count 2 2006.257.10:33:44.05#ibcon#about to read 4, iclass 35, count 2 2006.257.10:33:44.05#ibcon#read 4, iclass 35, count 2 2006.257.10:33:44.05#ibcon#about to read 5, iclass 35, count 2 2006.257.10:33:44.05#ibcon#read 5, iclass 35, count 2 2006.257.10:33:44.05#ibcon#about to read 6, iclass 35, count 2 2006.257.10:33:44.05#ibcon#read 6, iclass 35, count 2 2006.257.10:33:44.05#ibcon#end of sib2, iclass 35, count 2 2006.257.10:33:44.05#ibcon#*mode == 0, iclass 35, count 2 2006.257.10:33:44.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.10:33:44.05#ibcon#[27=AT04-05\r\n] 2006.257.10:33:44.05#ibcon#*before write, iclass 35, count 2 2006.257.10:33:44.05#ibcon#enter sib2, iclass 35, count 2 2006.257.10:33:44.05#ibcon#flushed, iclass 35, count 2 2006.257.10:33:44.05#ibcon#about to write, iclass 35, count 2 2006.257.10:33:44.05#ibcon#wrote, iclass 35, count 2 2006.257.10:33:44.05#ibcon#about to read 3, iclass 35, count 2 2006.257.10:33:44.08#ibcon#read 3, iclass 35, count 2 2006.257.10:33:44.08#ibcon#about to read 4, iclass 35, count 2 2006.257.10:33:44.08#ibcon#read 4, iclass 35, count 2 2006.257.10:33:44.08#ibcon#about to read 5, iclass 35, count 2 2006.257.10:33:44.08#ibcon#read 5, iclass 35, count 2 2006.257.10:33:44.08#ibcon#about to read 6, iclass 35, count 2 2006.257.10:33:44.08#ibcon#read 6, iclass 35, count 2 2006.257.10:33:44.08#ibcon#end of sib2, iclass 35, count 2 2006.257.10:33:44.08#ibcon#*after write, iclass 35, count 2 2006.257.10:33:44.08#ibcon#*before return 0, iclass 35, count 2 2006.257.10:33:44.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:44.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:33:44.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.10:33:44.08#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:44.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:44.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:44.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:44.20#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:33:44.20#ibcon#first serial, iclass 35, count 0 2006.257.10:33:44.20#ibcon#enter sib2, iclass 35, count 0 2006.257.10:33:44.20#ibcon#flushed, iclass 35, count 0 2006.257.10:33:44.20#ibcon#about to write, iclass 35, count 0 2006.257.10:33:44.20#ibcon#wrote, iclass 35, count 0 2006.257.10:33:44.20#ibcon#about to read 3, iclass 35, count 0 2006.257.10:33:44.22#ibcon#read 3, iclass 35, count 0 2006.257.10:33:44.22#ibcon#about to read 4, iclass 35, count 0 2006.257.10:33:44.22#ibcon#read 4, iclass 35, count 0 2006.257.10:33:44.22#ibcon#about to read 5, iclass 35, count 0 2006.257.10:33:44.22#ibcon#read 5, iclass 35, count 0 2006.257.10:33:44.22#ibcon#about to read 6, iclass 35, count 0 2006.257.10:33:44.22#ibcon#read 6, iclass 35, count 0 2006.257.10:33:44.22#ibcon#end of sib2, iclass 35, count 0 2006.257.10:33:44.22#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:33:44.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:33:44.22#ibcon#[27=USB\r\n] 2006.257.10:33:44.22#ibcon#*before write, iclass 35, count 0 2006.257.10:33:44.22#ibcon#enter sib2, iclass 35, count 0 2006.257.10:33:44.22#ibcon#flushed, iclass 35, count 0 2006.257.10:33:44.22#ibcon#about to write, iclass 35, count 0 2006.257.10:33:44.22#ibcon#wrote, iclass 35, count 0 2006.257.10:33:44.22#ibcon#about to read 3, iclass 35, count 0 2006.257.10:33:44.25#ibcon#read 3, iclass 35, count 0 2006.257.10:33:44.25#ibcon#about to read 4, iclass 35, count 0 2006.257.10:33:44.25#ibcon#read 4, iclass 35, count 0 2006.257.10:33:44.25#ibcon#about to read 5, iclass 35, count 0 2006.257.10:33:44.25#ibcon#read 5, iclass 35, count 0 2006.257.10:33:44.25#ibcon#about to read 6, iclass 35, count 0 2006.257.10:33:44.25#ibcon#read 6, iclass 35, count 0 2006.257.10:33:44.25#ibcon#end of sib2, iclass 35, count 0 2006.257.10:33:44.25#ibcon#*after write, iclass 35, count 0 2006.257.10:33:44.25#ibcon#*before return 0, iclass 35, count 0 2006.257.10:33:44.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:44.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:33:44.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:33:44.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:33:44.25$vck44/vblo=5,709.99 2006.257.10:33:44.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.10:33:44.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.10:33:44.25#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:44.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:44.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:44.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:44.25#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:33:44.25#ibcon#first serial, iclass 37, count 0 2006.257.10:33:44.25#ibcon#enter sib2, iclass 37, count 0 2006.257.10:33:44.25#ibcon#flushed, iclass 37, count 0 2006.257.10:33:44.25#ibcon#about to write, iclass 37, count 0 2006.257.10:33:44.25#ibcon#wrote, iclass 37, count 0 2006.257.10:33:44.25#ibcon#about to read 3, iclass 37, count 0 2006.257.10:33:44.27#ibcon#read 3, iclass 37, count 0 2006.257.10:33:44.27#ibcon#about to read 4, iclass 37, count 0 2006.257.10:33:44.27#ibcon#read 4, iclass 37, count 0 2006.257.10:33:44.27#ibcon#about to read 5, iclass 37, count 0 2006.257.10:33:44.27#ibcon#read 5, iclass 37, count 0 2006.257.10:33:44.27#ibcon#about to read 6, iclass 37, count 0 2006.257.10:33:44.27#ibcon#read 6, iclass 37, count 0 2006.257.10:33:44.27#ibcon#end of sib2, iclass 37, count 0 2006.257.10:33:44.27#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:33:44.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:33:44.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:33:44.27#ibcon#*before write, iclass 37, count 0 2006.257.10:33:44.27#ibcon#enter sib2, iclass 37, count 0 2006.257.10:33:44.27#ibcon#flushed, iclass 37, count 0 2006.257.10:33:44.27#ibcon#about to write, iclass 37, count 0 2006.257.10:33:44.27#ibcon#wrote, iclass 37, count 0 2006.257.10:33:44.27#ibcon#about to read 3, iclass 37, count 0 2006.257.10:33:44.31#ibcon#read 3, iclass 37, count 0 2006.257.10:33:44.31#ibcon#about to read 4, iclass 37, count 0 2006.257.10:33:44.31#ibcon#read 4, iclass 37, count 0 2006.257.10:33:44.31#ibcon#about to read 5, iclass 37, count 0 2006.257.10:33:44.31#ibcon#read 5, iclass 37, count 0 2006.257.10:33:44.31#ibcon#about to read 6, iclass 37, count 0 2006.257.10:33:44.31#ibcon#read 6, iclass 37, count 0 2006.257.10:33:44.31#ibcon#end of sib2, iclass 37, count 0 2006.257.10:33:44.31#ibcon#*after write, iclass 37, count 0 2006.257.10:33:44.31#ibcon#*before return 0, iclass 37, count 0 2006.257.10:33:44.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:44.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:33:44.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:33:44.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:33:44.31$vck44/vb=5,4 2006.257.10:33:44.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.10:33:44.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.10:33:44.31#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:44.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:44.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:44.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:44.37#ibcon#enter wrdev, iclass 39, count 2 2006.257.10:33:44.37#ibcon#first serial, iclass 39, count 2 2006.257.10:33:44.37#ibcon#enter sib2, iclass 39, count 2 2006.257.10:33:44.37#ibcon#flushed, iclass 39, count 2 2006.257.10:33:44.37#ibcon#about to write, iclass 39, count 2 2006.257.10:33:44.37#ibcon#wrote, iclass 39, count 2 2006.257.10:33:44.37#ibcon#about to read 3, iclass 39, count 2 2006.257.10:33:44.39#ibcon#read 3, iclass 39, count 2 2006.257.10:33:44.39#ibcon#about to read 4, iclass 39, count 2 2006.257.10:33:44.39#ibcon#read 4, iclass 39, count 2 2006.257.10:33:44.39#ibcon#about to read 5, iclass 39, count 2 2006.257.10:33:44.39#ibcon#read 5, iclass 39, count 2 2006.257.10:33:44.39#ibcon#about to read 6, iclass 39, count 2 2006.257.10:33:44.39#ibcon#read 6, iclass 39, count 2 2006.257.10:33:44.39#ibcon#end of sib2, iclass 39, count 2 2006.257.10:33:44.39#ibcon#*mode == 0, iclass 39, count 2 2006.257.10:33:44.39#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.10:33:44.39#ibcon#[27=AT05-04\r\n] 2006.257.10:33:44.39#ibcon#*before write, iclass 39, count 2 2006.257.10:33:44.39#ibcon#enter sib2, iclass 39, count 2 2006.257.10:33:44.39#ibcon#flushed, iclass 39, count 2 2006.257.10:33:44.39#ibcon#about to write, iclass 39, count 2 2006.257.10:33:44.39#ibcon#wrote, iclass 39, count 2 2006.257.10:33:44.39#ibcon#about to read 3, iclass 39, count 2 2006.257.10:33:44.42#ibcon#read 3, iclass 39, count 2 2006.257.10:33:44.42#ibcon#about to read 4, iclass 39, count 2 2006.257.10:33:44.42#ibcon#read 4, iclass 39, count 2 2006.257.10:33:44.42#ibcon#about to read 5, iclass 39, count 2 2006.257.10:33:44.42#ibcon#read 5, iclass 39, count 2 2006.257.10:33:44.42#ibcon#about to read 6, iclass 39, count 2 2006.257.10:33:44.42#ibcon#read 6, iclass 39, count 2 2006.257.10:33:44.42#ibcon#end of sib2, iclass 39, count 2 2006.257.10:33:44.42#ibcon#*after write, iclass 39, count 2 2006.257.10:33:44.42#ibcon#*before return 0, iclass 39, count 2 2006.257.10:33:44.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:44.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:33:44.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.10:33:44.42#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:44.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:44.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:44.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:44.54#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:33:44.54#ibcon#first serial, iclass 39, count 0 2006.257.10:33:44.54#ibcon#enter sib2, iclass 39, count 0 2006.257.10:33:44.54#ibcon#flushed, iclass 39, count 0 2006.257.10:33:44.54#ibcon#about to write, iclass 39, count 0 2006.257.10:33:44.54#ibcon#wrote, iclass 39, count 0 2006.257.10:33:44.54#ibcon#about to read 3, iclass 39, count 0 2006.257.10:33:44.56#ibcon#read 3, iclass 39, count 0 2006.257.10:33:44.56#ibcon#about to read 4, iclass 39, count 0 2006.257.10:33:44.56#ibcon#read 4, iclass 39, count 0 2006.257.10:33:44.56#ibcon#about to read 5, iclass 39, count 0 2006.257.10:33:44.56#ibcon#read 5, iclass 39, count 0 2006.257.10:33:44.56#ibcon#about to read 6, iclass 39, count 0 2006.257.10:33:44.56#ibcon#read 6, iclass 39, count 0 2006.257.10:33:44.56#ibcon#end of sib2, iclass 39, count 0 2006.257.10:33:44.56#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:33:44.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:33:44.56#ibcon#[27=USB\r\n] 2006.257.10:33:44.56#ibcon#*before write, iclass 39, count 0 2006.257.10:33:44.56#ibcon#enter sib2, iclass 39, count 0 2006.257.10:33:44.56#ibcon#flushed, iclass 39, count 0 2006.257.10:33:44.56#ibcon#about to write, iclass 39, count 0 2006.257.10:33:44.56#ibcon#wrote, iclass 39, count 0 2006.257.10:33:44.56#ibcon#about to read 3, iclass 39, count 0 2006.257.10:33:44.59#ibcon#read 3, iclass 39, count 0 2006.257.10:33:44.59#ibcon#about to read 4, iclass 39, count 0 2006.257.10:33:44.59#ibcon#read 4, iclass 39, count 0 2006.257.10:33:44.59#ibcon#about to read 5, iclass 39, count 0 2006.257.10:33:44.59#ibcon#read 5, iclass 39, count 0 2006.257.10:33:44.59#ibcon#about to read 6, iclass 39, count 0 2006.257.10:33:44.59#ibcon#read 6, iclass 39, count 0 2006.257.10:33:44.59#ibcon#end of sib2, iclass 39, count 0 2006.257.10:33:44.59#ibcon#*after write, iclass 39, count 0 2006.257.10:33:44.59#ibcon#*before return 0, iclass 39, count 0 2006.257.10:33:44.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:44.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:33:44.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:33:44.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:33:44.59$vck44/vblo=6,719.99 2006.257.10:33:44.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.10:33:44.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.10:33:44.59#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:44.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:44.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:44.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:44.59#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:33:44.59#ibcon#first serial, iclass 3, count 0 2006.257.10:33:44.59#ibcon#enter sib2, iclass 3, count 0 2006.257.10:33:44.59#ibcon#flushed, iclass 3, count 0 2006.257.10:33:44.59#ibcon#about to write, iclass 3, count 0 2006.257.10:33:44.59#ibcon#wrote, iclass 3, count 0 2006.257.10:33:44.59#ibcon#about to read 3, iclass 3, count 0 2006.257.10:33:44.61#ibcon#read 3, iclass 3, count 0 2006.257.10:33:44.61#ibcon#about to read 4, iclass 3, count 0 2006.257.10:33:44.61#ibcon#read 4, iclass 3, count 0 2006.257.10:33:44.61#ibcon#about to read 5, iclass 3, count 0 2006.257.10:33:44.61#ibcon#read 5, iclass 3, count 0 2006.257.10:33:44.61#ibcon#about to read 6, iclass 3, count 0 2006.257.10:33:44.61#ibcon#read 6, iclass 3, count 0 2006.257.10:33:44.61#ibcon#end of sib2, iclass 3, count 0 2006.257.10:33:44.61#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:33:44.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:33:44.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:33:44.61#ibcon#*before write, iclass 3, count 0 2006.257.10:33:44.61#ibcon#enter sib2, iclass 3, count 0 2006.257.10:33:44.61#ibcon#flushed, iclass 3, count 0 2006.257.10:33:44.61#ibcon#about to write, iclass 3, count 0 2006.257.10:33:44.61#ibcon#wrote, iclass 3, count 0 2006.257.10:33:44.61#ibcon#about to read 3, iclass 3, count 0 2006.257.10:33:44.65#ibcon#read 3, iclass 3, count 0 2006.257.10:33:44.65#ibcon#about to read 4, iclass 3, count 0 2006.257.10:33:44.65#ibcon#read 4, iclass 3, count 0 2006.257.10:33:44.65#ibcon#about to read 5, iclass 3, count 0 2006.257.10:33:44.65#ibcon#read 5, iclass 3, count 0 2006.257.10:33:44.65#ibcon#about to read 6, iclass 3, count 0 2006.257.10:33:44.65#ibcon#read 6, iclass 3, count 0 2006.257.10:33:44.65#ibcon#end of sib2, iclass 3, count 0 2006.257.10:33:44.65#ibcon#*after write, iclass 3, count 0 2006.257.10:33:44.65#ibcon#*before return 0, iclass 3, count 0 2006.257.10:33:44.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:44.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:33:44.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:33:44.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:33:44.65$vck44/vb=6,4 2006.257.10:33:44.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.10:33:44.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.10:33:44.65#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:44.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:44.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:44.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:44.71#ibcon#enter wrdev, iclass 5, count 2 2006.257.10:33:44.71#ibcon#first serial, iclass 5, count 2 2006.257.10:33:44.71#ibcon#enter sib2, iclass 5, count 2 2006.257.10:33:44.71#ibcon#flushed, iclass 5, count 2 2006.257.10:33:44.71#ibcon#about to write, iclass 5, count 2 2006.257.10:33:44.71#ibcon#wrote, iclass 5, count 2 2006.257.10:33:44.71#ibcon#about to read 3, iclass 5, count 2 2006.257.10:33:44.73#ibcon#read 3, iclass 5, count 2 2006.257.10:33:44.73#ibcon#about to read 4, iclass 5, count 2 2006.257.10:33:44.73#ibcon#read 4, iclass 5, count 2 2006.257.10:33:44.73#ibcon#about to read 5, iclass 5, count 2 2006.257.10:33:44.73#ibcon#read 5, iclass 5, count 2 2006.257.10:33:44.73#ibcon#about to read 6, iclass 5, count 2 2006.257.10:33:44.73#ibcon#read 6, iclass 5, count 2 2006.257.10:33:44.73#ibcon#end of sib2, iclass 5, count 2 2006.257.10:33:44.73#ibcon#*mode == 0, iclass 5, count 2 2006.257.10:33:44.73#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.10:33:44.73#ibcon#[27=AT06-04\r\n] 2006.257.10:33:44.73#ibcon#*before write, iclass 5, count 2 2006.257.10:33:44.73#ibcon#enter sib2, iclass 5, count 2 2006.257.10:33:44.73#ibcon#flushed, iclass 5, count 2 2006.257.10:33:44.73#ibcon#about to write, iclass 5, count 2 2006.257.10:33:44.73#ibcon#wrote, iclass 5, count 2 2006.257.10:33:44.73#ibcon#about to read 3, iclass 5, count 2 2006.257.10:33:44.76#ibcon#read 3, iclass 5, count 2 2006.257.10:33:44.76#ibcon#about to read 4, iclass 5, count 2 2006.257.10:33:44.76#ibcon#read 4, iclass 5, count 2 2006.257.10:33:44.76#ibcon#about to read 5, iclass 5, count 2 2006.257.10:33:44.76#ibcon#read 5, iclass 5, count 2 2006.257.10:33:44.76#ibcon#about to read 6, iclass 5, count 2 2006.257.10:33:44.76#ibcon#read 6, iclass 5, count 2 2006.257.10:33:44.76#ibcon#end of sib2, iclass 5, count 2 2006.257.10:33:44.76#ibcon#*after write, iclass 5, count 2 2006.257.10:33:44.76#ibcon#*before return 0, iclass 5, count 2 2006.257.10:33:44.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:44.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:33:44.76#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.10:33:44.76#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:44.76#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:44.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:44.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:44.88#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:33:44.88#ibcon#first serial, iclass 5, count 0 2006.257.10:33:44.88#ibcon#enter sib2, iclass 5, count 0 2006.257.10:33:44.88#ibcon#flushed, iclass 5, count 0 2006.257.10:33:44.88#ibcon#about to write, iclass 5, count 0 2006.257.10:33:44.88#ibcon#wrote, iclass 5, count 0 2006.257.10:33:44.88#ibcon#about to read 3, iclass 5, count 0 2006.257.10:33:44.90#ibcon#read 3, iclass 5, count 0 2006.257.10:33:44.90#ibcon#about to read 4, iclass 5, count 0 2006.257.10:33:44.90#ibcon#read 4, iclass 5, count 0 2006.257.10:33:44.90#ibcon#about to read 5, iclass 5, count 0 2006.257.10:33:44.90#ibcon#read 5, iclass 5, count 0 2006.257.10:33:44.90#ibcon#about to read 6, iclass 5, count 0 2006.257.10:33:44.90#ibcon#read 6, iclass 5, count 0 2006.257.10:33:44.90#ibcon#end of sib2, iclass 5, count 0 2006.257.10:33:44.90#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:33:44.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:33:44.90#ibcon#[27=USB\r\n] 2006.257.10:33:44.90#ibcon#*before write, iclass 5, count 0 2006.257.10:33:44.90#ibcon#enter sib2, iclass 5, count 0 2006.257.10:33:44.90#ibcon#flushed, iclass 5, count 0 2006.257.10:33:44.90#ibcon#about to write, iclass 5, count 0 2006.257.10:33:44.90#ibcon#wrote, iclass 5, count 0 2006.257.10:33:44.90#ibcon#about to read 3, iclass 5, count 0 2006.257.10:33:44.93#ibcon#read 3, iclass 5, count 0 2006.257.10:33:44.93#ibcon#about to read 4, iclass 5, count 0 2006.257.10:33:44.93#ibcon#read 4, iclass 5, count 0 2006.257.10:33:44.93#ibcon#about to read 5, iclass 5, count 0 2006.257.10:33:44.93#ibcon#read 5, iclass 5, count 0 2006.257.10:33:44.93#ibcon#about to read 6, iclass 5, count 0 2006.257.10:33:44.93#ibcon#read 6, iclass 5, count 0 2006.257.10:33:44.93#ibcon#end of sib2, iclass 5, count 0 2006.257.10:33:44.93#ibcon#*after write, iclass 5, count 0 2006.257.10:33:44.93#ibcon#*before return 0, iclass 5, count 0 2006.257.10:33:44.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:44.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:33:44.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:33:44.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:33:44.93$vck44/vblo=7,734.99 2006.257.10:33:44.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.10:33:44.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.10:33:44.93#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:44.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:44.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:44.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:44.93#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:33:44.93#ibcon#first serial, iclass 7, count 0 2006.257.10:33:44.93#ibcon#enter sib2, iclass 7, count 0 2006.257.10:33:44.93#ibcon#flushed, iclass 7, count 0 2006.257.10:33:44.93#ibcon#about to write, iclass 7, count 0 2006.257.10:33:44.93#ibcon#wrote, iclass 7, count 0 2006.257.10:33:44.93#ibcon#about to read 3, iclass 7, count 0 2006.257.10:33:44.95#ibcon#read 3, iclass 7, count 0 2006.257.10:33:44.95#ibcon#about to read 4, iclass 7, count 0 2006.257.10:33:44.95#ibcon#read 4, iclass 7, count 0 2006.257.10:33:44.95#ibcon#about to read 5, iclass 7, count 0 2006.257.10:33:44.95#ibcon#read 5, iclass 7, count 0 2006.257.10:33:44.95#ibcon#about to read 6, iclass 7, count 0 2006.257.10:33:44.95#ibcon#read 6, iclass 7, count 0 2006.257.10:33:44.95#ibcon#end of sib2, iclass 7, count 0 2006.257.10:33:44.95#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:33:44.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:33:44.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:33:44.95#ibcon#*before write, iclass 7, count 0 2006.257.10:33:44.95#ibcon#enter sib2, iclass 7, count 0 2006.257.10:33:44.95#ibcon#flushed, iclass 7, count 0 2006.257.10:33:44.95#ibcon#about to write, iclass 7, count 0 2006.257.10:33:44.95#ibcon#wrote, iclass 7, count 0 2006.257.10:33:44.95#ibcon#about to read 3, iclass 7, count 0 2006.257.10:33:44.99#ibcon#read 3, iclass 7, count 0 2006.257.10:33:44.99#ibcon#about to read 4, iclass 7, count 0 2006.257.10:33:44.99#ibcon#read 4, iclass 7, count 0 2006.257.10:33:44.99#ibcon#about to read 5, iclass 7, count 0 2006.257.10:33:44.99#ibcon#read 5, iclass 7, count 0 2006.257.10:33:44.99#ibcon#about to read 6, iclass 7, count 0 2006.257.10:33:44.99#ibcon#read 6, iclass 7, count 0 2006.257.10:33:44.99#ibcon#end of sib2, iclass 7, count 0 2006.257.10:33:44.99#ibcon#*after write, iclass 7, count 0 2006.257.10:33:44.99#ibcon#*before return 0, iclass 7, count 0 2006.257.10:33:44.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:44.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:33:44.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:33:44.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:33:44.99$vck44/vb=7,4 2006.257.10:33:44.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.10:33:44.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.10:33:44.99#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:44.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:45.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:45.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:45.05#ibcon#enter wrdev, iclass 11, count 2 2006.257.10:33:45.05#ibcon#first serial, iclass 11, count 2 2006.257.10:33:45.05#ibcon#enter sib2, iclass 11, count 2 2006.257.10:33:45.05#ibcon#flushed, iclass 11, count 2 2006.257.10:33:45.05#ibcon#about to write, iclass 11, count 2 2006.257.10:33:45.05#ibcon#wrote, iclass 11, count 2 2006.257.10:33:45.05#ibcon#about to read 3, iclass 11, count 2 2006.257.10:33:45.07#ibcon#read 3, iclass 11, count 2 2006.257.10:33:45.07#ibcon#about to read 4, iclass 11, count 2 2006.257.10:33:45.07#ibcon#read 4, iclass 11, count 2 2006.257.10:33:45.07#ibcon#about to read 5, iclass 11, count 2 2006.257.10:33:45.07#ibcon#read 5, iclass 11, count 2 2006.257.10:33:45.07#ibcon#about to read 6, iclass 11, count 2 2006.257.10:33:45.07#ibcon#read 6, iclass 11, count 2 2006.257.10:33:45.07#ibcon#end of sib2, iclass 11, count 2 2006.257.10:33:45.07#ibcon#*mode == 0, iclass 11, count 2 2006.257.10:33:45.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.10:33:45.07#ibcon#[27=AT07-04\r\n] 2006.257.10:33:45.07#ibcon#*before write, iclass 11, count 2 2006.257.10:33:45.07#ibcon#enter sib2, iclass 11, count 2 2006.257.10:33:45.07#ibcon#flushed, iclass 11, count 2 2006.257.10:33:45.07#ibcon#about to write, iclass 11, count 2 2006.257.10:33:45.07#ibcon#wrote, iclass 11, count 2 2006.257.10:33:45.07#ibcon#about to read 3, iclass 11, count 2 2006.257.10:33:45.10#ibcon#read 3, iclass 11, count 2 2006.257.10:33:45.10#ibcon#about to read 4, iclass 11, count 2 2006.257.10:33:45.10#ibcon#read 4, iclass 11, count 2 2006.257.10:33:45.10#ibcon#about to read 5, iclass 11, count 2 2006.257.10:33:45.10#ibcon#read 5, iclass 11, count 2 2006.257.10:33:45.10#ibcon#about to read 6, iclass 11, count 2 2006.257.10:33:45.10#ibcon#read 6, iclass 11, count 2 2006.257.10:33:45.10#ibcon#end of sib2, iclass 11, count 2 2006.257.10:33:45.10#ibcon#*after write, iclass 11, count 2 2006.257.10:33:45.10#ibcon#*before return 0, iclass 11, count 2 2006.257.10:33:45.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:45.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:33:45.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.10:33:45.10#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:45.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:45.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:45.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:45.22#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:33:45.22#ibcon#first serial, iclass 11, count 0 2006.257.10:33:45.22#ibcon#enter sib2, iclass 11, count 0 2006.257.10:33:45.22#ibcon#flushed, iclass 11, count 0 2006.257.10:33:45.22#ibcon#about to write, iclass 11, count 0 2006.257.10:33:45.22#ibcon#wrote, iclass 11, count 0 2006.257.10:33:45.22#ibcon#about to read 3, iclass 11, count 0 2006.257.10:33:45.24#ibcon#read 3, iclass 11, count 0 2006.257.10:33:45.24#ibcon#about to read 4, iclass 11, count 0 2006.257.10:33:45.24#ibcon#read 4, iclass 11, count 0 2006.257.10:33:45.24#ibcon#about to read 5, iclass 11, count 0 2006.257.10:33:45.24#ibcon#read 5, iclass 11, count 0 2006.257.10:33:45.24#ibcon#about to read 6, iclass 11, count 0 2006.257.10:33:45.24#ibcon#read 6, iclass 11, count 0 2006.257.10:33:45.24#ibcon#end of sib2, iclass 11, count 0 2006.257.10:33:45.24#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:33:45.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:33:45.24#ibcon#[27=USB\r\n] 2006.257.10:33:45.24#ibcon#*before write, iclass 11, count 0 2006.257.10:33:45.24#ibcon#enter sib2, iclass 11, count 0 2006.257.10:33:45.24#ibcon#flushed, iclass 11, count 0 2006.257.10:33:45.24#ibcon#about to write, iclass 11, count 0 2006.257.10:33:45.24#ibcon#wrote, iclass 11, count 0 2006.257.10:33:45.24#ibcon#about to read 3, iclass 11, count 0 2006.257.10:33:45.27#ibcon#read 3, iclass 11, count 0 2006.257.10:33:45.27#ibcon#about to read 4, iclass 11, count 0 2006.257.10:33:45.27#ibcon#read 4, iclass 11, count 0 2006.257.10:33:45.27#ibcon#about to read 5, iclass 11, count 0 2006.257.10:33:45.27#ibcon#read 5, iclass 11, count 0 2006.257.10:33:45.27#ibcon#about to read 6, iclass 11, count 0 2006.257.10:33:45.27#ibcon#read 6, iclass 11, count 0 2006.257.10:33:45.27#ibcon#end of sib2, iclass 11, count 0 2006.257.10:33:45.27#ibcon#*after write, iclass 11, count 0 2006.257.10:33:45.27#ibcon#*before return 0, iclass 11, count 0 2006.257.10:33:45.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:45.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:33:45.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:33:45.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:33:45.27$vck44/vblo=8,744.99 2006.257.10:33:45.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.10:33:45.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.10:33:45.27#ibcon#ireg 17 cls_cnt 0 2006.257.10:33:45.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:45.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:45.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:45.27#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:33:45.27#ibcon#first serial, iclass 13, count 0 2006.257.10:33:45.27#ibcon#enter sib2, iclass 13, count 0 2006.257.10:33:45.27#ibcon#flushed, iclass 13, count 0 2006.257.10:33:45.27#ibcon#about to write, iclass 13, count 0 2006.257.10:33:45.27#ibcon#wrote, iclass 13, count 0 2006.257.10:33:45.27#ibcon#about to read 3, iclass 13, count 0 2006.257.10:33:45.29#ibcon#read 3, iclass 13, count 0 2006.257.10:33:45.29#ibcon#about to read 4, iclass 13, count 0 2006.257.10:33:45.29#ibcon#read 4, iclass 13, count 0 2006.257.10:33:45.29#ibcon#about to read 5, iclass 13, count 0 2006.257.10:33:45.29#ibcon#read 5, iclass 13, count 0 2006.257.10:33:45.29#ibcon#about to read 6, iclass 13, count 0 2006.257.10:33:45.29#ibcon#read 6, iclass 13, count 0 2006.257.10:33:45.29#ibcon#end of sib2, iclass 13, count 0 2006.257.10:33:45.29#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:33:45.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:33:45.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:33:45.29#ibcon#*before write, iclass 13, count 0 2006.257.10:33:45.29#ibcon#enter sib2, iclass 13, count 0 2006.257.10:33:45.29#ibcon#flushed, iclass 13, count 0 2006.257.10:33:45.29#ibcon#about to write, iclass 13, count 0 2006.257.10:33:45.29#ibcon#wrote, iclass 13, count 0 2006.257.10:33:45.29#ibcon#about to read 3, iclass 13, count 0 2006.257.10:33:45.33#ibcon#read 3, iclass 13, count 0 2006.257.10:33:45.33#ibcon#about to read 4, iclass 13, count 0 2006.257.10:33:45.33#ibcon#read 4, iclass 13, count 0 2006.257.10:33:45.33#ibcon#about to read 5, iclass 13, count 0 2006.257.10:33:45.33#ibcon#read 5, iclass 13, count 0 2006.257.10:33:45.33#ibcon#about to read 6, iclass 13, count 0 2006.257.10:33:45.33#ibcon#read 6, iclass 13, count 0 2006.257.10:33:45.33#ibcon#end of sib2, iclass 13, count 0 2006.257.10:33:45.33#ibcon#*after write, iclass 13, count 0 2006.257.10:33:45.33#ibcon#*before return 0, iclass 13, count 0 2006.257.10:33:45.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:45.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:33:45.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:33:45.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:33:45.33$vck44/vb=8,4 2006.257.10:33:45.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.10:33:45.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.10:33:45.33#ibcon#ireg 11 cls_cnt 2 2006.257.10:33:45.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:45.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:45.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:45.39#ibcon#enter wrdev, iclass 15, count 2 2006.257.10:33:45.39#ibcon#first serial, iclass 15, count 2 2006.257.10:33:45.39#ibcon#enter sib2, iclass 15, count 2 2006.257.10:33:45.39#ibcon#flushed, iclass 15, count 2 2006.257.10:33:45.39#ibcon#about to write, iclass 15, count 2 2006.257.10:33:45.39#ibcon#wrote, iclass 15, count 2 2006.257.10:33:45.39#ibcon#about to read 3, iclass 15, count 2 2006.257.10:33:45.41#ibcon#read 3, iclass 15, count 2 2006.257.10:33:45.41#ibcon#about to read 4, iclass 15, count 2 2006.257.10:33:45.41#ibcon#read 4, iclass 15, count 2 2006.257.10:33:45.41#ibcon#about to read 5, iclass 15, count 2 2006.257.10:33:45.41#ibcon#read 5, iclass 15, count 2 2006.257.10:33:45.41#ibcon#about to read 6, iclass 15, count 2 2006.257.10:33:45.41#ibcon#read 6, iclass 15, count 2 2006.257.10:33:45.41#ibcon#end of sib2, iclass 15, count 2 2006.257.10:33:45.41#ibcon#*mode == 0, iclass 15, count 2 2006.257.10:33:45.41#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.10:33:45.41#ibcon#[27=AT08-04\r\n] 2006.257.10:33:45.41#ibcon#*before write, iclass 15, count 2 2006.257.10:33:45.41#ibcon#enter sib2, iclass 15, count 2 2006.257.10:33:45.41#ibcon#flushed, iclass 15, count 2 2006.257.10:33:45.41#ibcon#about to write, iclass 15, count 2 2006.257.10:33:45.41#ibcon#wrote, iclass 15, count 2 2006.257.10:33:45.41#ibcon#about to read 3, iclass 15, count 2 2006.257.10:33:45.44#ibcon#read 3, iclass 15, count 2 2006.257.10:33:45.44#ibcon#about to read 4, iclass 15, count 2 2006.257.10:33:45.44#ibcon#read 4, iclass 15, count 2 2006.257.10:33:45.44#ibcon#about to read 5, iclass 15, count 2 2006.257.10:33:45.44#ibcon#read 5, iclass 15, count 2 2006.257.10:33:45.44#ibcon#about to read 6, iclass 15, count 2 2006.257.10:33:45.44#ibcon#read 6, iclass 15, count 2 2006.257.10:33:45.44#ibcon#end of sib2, iclass 15, count 2 2006.257.10:33:45.44#ibcon#*after write, iclass 15, count 2 2006.257.10:33:45.44#ibcon#*before return 0, iclass 15, count 2 2006.257.10:33:45.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:45.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:33:45.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.10:33:45.44#ibcon#ireg 7 cls_cnt 0 2006.257.10:33:45.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:45.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:45.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:45.56#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:33:45.56#ibcon#first serial, iclass 15, count 0 2006.257.10:33:45.56#ibcon#enter sib2, iclass 15, count 0 2006.257.10:33:45.56#ibcon#flushed, iclass 15, count 0 2006.257.10:33:45.56#ibcon#about to write, iclass 15, count 0 2006.257.10:33:45.56#ibcon#wrote, iclass 15, count 0 2006.257.10:33:45.56#ibcon#about to read 3, iclass 15, count 0 2006.257.10:33:45.58#ibcon#read 3, iclass 15, count 0 2006.257.10:33:45.58#ibcon#about to read 4, iclass 15, count 0 2006.257.10:33:45.58#ibcon#read 4, iclass 15, count 0 2006.257.10:33:45.58#ibcon#about to read 5, iclass 15, count 0 2006.257.10:33:45.58#ibcon#read 5, iclass 15, count 0 2006.257.10:33:45.58#ibcon#about to read 6, iclass 15, count 0 2006.257.10:33:45.58#ibcon#read 6, iclass 15, count 0 2006.257.10:33:45.58#ibcon#end of sib2, iclass 15, count 0 2006.257.10:33:45.58#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:33:45.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:33:45.58#ibcon#[27=USB\r\n] 2006.257.10:33:45.58#ibcon#*before write, iclass 15, count 0 2006.257.10:33:45.58#ibcon#enter sib2, iclass 15, count 0 2006.257.10:33:45.58#ibcon#flushed, iclass 15, count 0 2006.257.10:33:45.58#ibcon#about to write, iclass 15, count 0 2006.257.10:33:45.58#ibcon#wrote, iclass 15, count 0 2006.257.10:33:45.58#ibcon#about to read 3, iclass 15, count 0 2006.257.10:33:45.61#ibcon#read 3, iclass 15, count 0 2006.257.10:33:45.61#ibcon#about to read 4, iclass 15, count 0 2006.257.10:33:45.61#ibcon#read 4, iclass 15, count 0 2006.257.10:33:45.61#ibcon#about to read 5, iclass 15, count 0 2006.257.10:33:45.61#ibcon#read 5, iclass 15, count 0 2006.257.10:33:45.61#ibcon#about to read 6, iclass 15, count 0 2006.257.10:33:45.61#ibcon#read 6, iclass 15, count 0 2006.257.10:33:45.61#ibcon#end of sib2, iclass 15, count 0 2006.257.10:33:45.61#ibcon#*after write, iclass 15, count 0 2006.257.10:33:45.61#ibcon#*before return 0, iclass 15, count 0 2006.257.10:33:45.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:45.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:33:45.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:33:45.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:33:45.61$vck44/vabw=wide 2006.257.10:33:45.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.10:33:45.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.10:33:45.61#ibcon#ireg 8 cls_cnt 0 2006.257.10:33:45.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:45.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:45.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:45.61#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:33:45.61#ibcon#first serial, iclass 17, count 0 2006.257.10:33:45.61#ibcon#enter sib2, iclass 17, count 0 2006.257.10:33:45.61#ibcon#flushed, iclass 17, count 0 2006.257.10:33:45.61#ibcon#about to write, iclass 17, count 0 2006.257.10:33:45.61#ibcon#wrote, iclass 17, count 0 2006.257.10:33:45.61#ibcon#about to read 3, iclass 17, count 0 2006.257.10:33:45.63#ibcon#read 3, iclass 17, count 0 2006.257.10:33:45.63#ibcon#about to read 4, iclass 17, count 0 2006.257.10:33:45.63#ibcon#read 4, iclass 17, count 0 2006.257.10:33:45.63#ibcon#about to read 5, iclass 17, count 0 2006.257.10:33:45.63#ibcon#read 5, iclass 17, count 0 2006.257.10:33:45.63#ibcon#about to read 6, iclass 17, count 0 2006.257.10:33:45.63#ibcon#read 6, iclass 17, count 0 2006.257.10:33:45.63#ibcon#end of sib2, iclass 17, count 0 2006.257.10:33:45.63#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:33:45.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:33:45.63#ibcon#[25=BW32\r\n] 2006.257.10:33:45.63#ibcon#*before write, iclass 17, count 0 2006.257.10:33:45.63#ibcon#enter sib2, iclass 17, count 0 2006.257.10:33:45.63#ibcon#flushed, iclass 17, count 0 2006.257.10:33:45.63#ibcon#about to write, iclass 17, count 0 2006.257.10:33:45.63#ibcon#wrote, iclass 17, count 0 2006.257.10:33:45.63#ibcon#about to read 3, iclass 17, count 0 2006.257.10:33:45.66#ibcon#read 3, iclass 17, count 0 2006.257.10:33:45.66#ibcon#about to read 4, iclass 17, count 0 2006.257.10:33:45.66#ibcon#read 4, iclass 17, count 0 2006.257.10:33:45.66#ibcon#about to read 5, iclass 17, count 0 2006.257.10:33:45.66#ibcon#read 5, iclass 17, count 0 2006.257.10:33:45.66#ibcon#about to read 6, iclass 17, count 0 2006.257.10:33:45.66#ibcon#read 6, iclass 17, count 0 2006.257.10:33:45.66#ibcon#end of sib2, iclass 17, count 0 2006.257.10:33:45.66#ibcon#*after write, iclass 17, count 0 2006.257.10:33:45.66#ibcon#*before return 0, iclass 17, count 0 2006.257.10:33:45.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:45.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:33:45.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:33:45.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:33:45.66$vck44/vbbw=wide 2006.257.10:33:45.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.10:33:45.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.10:33:45.66#ibcon#ireg 8 cls_cnt 0 2006.257.10:33:45.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:33:45.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:33:45.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:33:45.73#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:33:45.73#ibcon#first serial, iclass 19, count 0 2006.257.10:33:45.73#ibcon#enter sib2, iclass 19, count 0 2006.257.10:33:45.73#ibcon#flushed, iclass 19, count 0 2006.257.10:33:45.73#ibcon#about to write, iclass 19, count 0 2006.257.10:33:45.73#ibcon#wrote, iclass 19, count 0 2006.257.10:33:45.73#ibcon#about to read 3, iclass 19, count 0 2006.257.10:33:45.75#ibcon#read 3, iclass 19, count 0 2006.257.10:33:45.75#ibcon#about to read 4, iclass 19, count 0 2006.257.10:33:45.75#ibcon#read 4, iclass 19, count 0 2006.257.10:33:45.75#ibcon#about to read 5, iclass 19, count 0 2006.257.10:33:45.75#ibcon#read 5, iclass 19, count 0 2006.257.10:33:45.75#ibcon#about to read 6, iclass 19, count 0 2006.257.10:33:45.75#ibcon#read 6, iclass 19, count 0 2006.257.10:33:45.75#ibcon#end of sib2, iclass 19, count 0 2006.257.10:33:45.75#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:33:45.75#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:33:45.75#ibcon#[27=BW32\r\n] 2006.257.10:33:45.75#ibcon#*before write, iclass 19, count 0 2006.257.10:33:45.75#ibcon#enter sib2, iclass 19, count 0 2006.257.10:33:45.75#ibcon#flushed, iclass 19, count 0 2006.257.10:33:45.75#ibcon#about to write, iclass 19, count 0 2006.257.10:33:45.75#ibcon#wrote, iclass 19, count 0 2006.257.10:33:45.75#ibcon#about to read 3, iclass 19, count 0 2006.257.10:33:45.78#ibcon#read 3, iclass 19, count 0 2006.257.10:33:45.78#ibcon#about to read 4, iclass 19, count 0 2006.257.10:33:45.78#ibcon#read 4, iclass 19, count 0 2006.257.10:33:45.78#ibcon#about to read 5, iclass 19, count 0 2006.257.10:33:45.78#ibcon#read 5, iclass 19, count 0 2006.257.10:33:45.78#ibcon#about to read 6, iclass 19, count 0 2006.257.10:33:45.78#ibcon#read 6, iclass 19, count 0 2006.257.10:33:45.78#ibcon#end of sib2, iclass 19, count 0 2006.257.10:33:45.78#ibcon#*after write, iclass 19, count 0 2006.257.10:33:45.78#ibcon#*before return 0, iclass 19, count 0 2006.257.10:33:45.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:33:45.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:33:45.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:33:45.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:33:45.78$setupk4/ifdk4 2006.257.10:33:45.78$ifdk4/lo= 2006.257.10:33:45.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:33:45.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:33:45.78$ifdk4/patch= 2006.257.10:33:45.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:33:45.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:33:45.78$setupk4/!*+20s 2006.257.10:33:50.40#abcon#<5=/14 1.3 4.5 18.89 961014.0\r\n> 2006.257.10:33:50.42#abcon#{5=INTERFACE CLEAR} 2006.257.10:33:50.48#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:34:00.27$setupk4/"tpicd 2006.257.10:34:00.27$setupk4/echo=off 2006.257.10:34:00.27$setupk4/xlog=off 2006.257.10:34:00.27:!2006.257.10:35:10 2006.257.10:34:12.14#trakl#Source acquired 2006.257.10:34:14.14#flagr#flagr/antenna,acquired 2006.257.10:35:10.00:preob 2006.257.10:35:10.14/onsource/TRACKING 2006.257.10:35:10.14:!2006.257.10:35:20 2006.257.10:35:20.00:"tape 2006.257.10:35:20.00:"st=record 2006.257.10:35:20.00:data_valid=on 2006.257.10:35:20.00:midob 2006.257.10:35:20.14/onsource/TRACKING 2006.257.10:35:20.14/wx/18.89,1014.0,96 2006.257.10:35:20.28/cable/+6.4750E-03 2006.257.10:35:21.37/va/01,08,usb,yes,31,34 2006.257.10:35:21.37/va/02,07,usb,yes,34,34 2006.257.10:35:21.37/va/03,08,usb,yes,30,32 2006.257.10:35:21.37/va/04,07,usb,yes,35,36 2006.257.10:35:21.37/va/05,04,usb,yes,31,32 2006.257.10:35:21.37/va/06,04,usb,yes,35,34 2006.257.10:35:21.37/va/07,04,usb,yes,36,36 2006.257.10:35:21.37/va/08,04,usb,yes,30,36 2006.257.10:35:21.60/valo/01,524.99,yes,locked 2006.257.10:35:21.60/valo/02,534.99,yes,locked 2006.257.10:35:21.60/valo/03,564.99,yes,locked 2006.257.10:35:21.60/valo/04,624.99,yes,locked 2006.257.10:35:21.60/valo/05,734.99,yes,locked 2006.257.10:35:21.60/valo/06,814.99,yes,locked 2006.257.10:35:21.60/valo/07,864.99,yes,locked 2006.257.10:35:21.60/valo/08,884.99,yes,locked 2006.257.10:35:22.69/vb/01,04,usb,yes,31,29 2006.257.10:35:22.69/vb/02,05,usb,yes,29,29 2006.257.10:35:22.69/vb/03,04,usb,yes,30,33 2006.257.10:35:22.69/vb/04,05,usb,yes,30,29 2006.257.10:35:22.69/vb/05,04,usb,yes,27,29 2006.257.10:35:22.69/vb/06,04,usb,yes,32,28 2006.257.10:35:22.69/vb/07,04,usb,yes,31,31 2006.257.10:35:22.69/vb/08,04,usb,yes,29,32 2006.257.10:35:22.92/vblo/01,629.99,yes,locked 2006.257.10:35:22.92/vblo/02,634.99,yes,locked 2006.257.10:35:22.92/vblo/03,649.99,yes,locked 2006.257.10:35:22.92/vblo/04,679.99,yes,locked 2006.257.10:35:22.92/vblo/05,709.99,yes,locked 2006.257.10:35:22.92/vblo/06,719.99,yes,locked 2006.257.10:35:22.92/vblo/07,734.99,yes,locked 2006.257.10:35:22.92/vblo/08,744.99,yes,locked 2006.257.10:35:23.07/vabw/8 2006.257.10:35:23.22/vbbw/8 2006.257.10:35:23.31/xfe/off,on,14.7 2006.257.10:35:23.68/ifatt/23,28,28,28 2006.257.10:35:24.07/fmout-gps/S +4.63E-07 2006.257.10:35:24.11:!2006.257.10:38:10 2006.257.10:38:10.00:data_valid=off 2006.257.10:38:10.00:"et 2006.257.10:38:10.01:!+3s 2006.257.10:38:13.02:"tape 2006.257.10:38:13.02:postob 2006.257.10:38:13.23/cable/+6.4760E-03 2006.257.10:38:13.23/wx/18.88,1013.9,96 2006.257.10:38:14.07/fmout-gps/S +4.63E-07 2006.257.10:38:14.07:scan_name=257-1040,jd0609,70 2006.257.10:38:14.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.10:38:15.14#flagr#flagr/antenna,new-source 2006.257.10:38:15.14:checkk5 2006.257.10:38:15.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:38:15.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:38:16.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:38:16.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:38:17.12/chk_obsdata//k5ts1/T2571035??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.10:38:17.54/chk_obsdata//k5ts2/T2571035??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.10:38:17.94/chk_obsdata//k5ts3/T2571035??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.10:38:18.33/chk_obsdata//k5ts4/T2571035??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.10:38:19.06/k5log//k5ts1_log_newline 2006.257.10:38:19.76/k5log//k5ts2_log_newline 2006.257.10:38:20.50/k5log//k5ts3_log_newline 2006.257.10:38:21.21/k5log//k5ts4_log_newline 2006.257.10:38:21.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:38:21.23:setupk4=1 2006.257.10:38:21.23$setupk4/echo=on 2006.257.10:38:21.23$setupk4/pcalon 2006.257.10:38:21.23$pcalon/"no phase cal control is implemented here 2006.257.10:38:21.23$setupk4/"tpicd=stop 2006.257.10:38:21.23$setupk4/"rec=synch_on 2006.257.10:38:21.23$setupk4/"rec_mode=128 2006.257.10:38:21.23$setupk4/!* 2006.257.10:38:21.23$setupk4/recpk4 2006.257.10:38:21.23$recpk4/recpatch= 2006.257.10:38:21.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:38:21.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:38:21.23$setupk4/vck44 2006.257.10:38:21.23$vck44/valo=1,524.99 2006.257.10:38:21.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.10:38:21.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.10:38:21.23#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:21.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:21.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:21.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:21.23#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:38:21.23#ibcon#first serial, iclass 24, count 0 2006.257.10:38:21.23#ibcon#enter sib2, iclass 24, count 0 2006.257.10:38:21.23#ibcon#flushed, iclass 24, count 0 2006.257.10:38:21.23#ibcon#about to write, iclass 24, count 0 2006.257.10:38:21.23#ibcon#wrote, iclass 24, count 0 2006.257.10:38:21.23#ibcon#about to read 3, iclass 24, count 0 2006.257.10:38:21.25#ibcon#read 3, iclass 24, count 0 2006.257.10:38:21.25#ibcon#about to read 4, iclass 24, count 0 2006.257.10:38:21.25#ibcon#read 4, iclass 24, count 0 2006.257.10:38:21.25#ibcon#about to read 5, iclass 24, count 0 2006.257.10:38:21.25#ibcon#read 5, iclass 24, count 0 2006.257.10:38:21.25#ibcon#about to read 6, iclass 24, count 0 2006.257.10:38:21.25#ibcon#read 6, iclass 24, count 0 2006.257.10:38:21.25#ibcon#end of sib2, iclass 24, count 0 2006.257.10:38:21.25#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:38:21.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:38:21.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:38:21.25#ibcon#*before write, iclass 24, count 0 2006.257.10:38:21.25#ibcon#enter sib2, iclass 24, count 0 2006.257.10:38:21.25#ibcon#flushed, iclass 24, count 0 2006.257.10:38:21.25#ibcon#about to write, iclass 24, count 0 2006.257.10:38:21.25#ibcon#wrote, iclass 24, count 0 2006.257.10:38:21.25#ibcon#about to read 3, iclass 24, count 0 2006.257.10:38:21.30#ibcon#read 3, iclass 24, count 0 2006.257.10:38:21.30#ibcon#about to read 4, iclass 24, count 0 2006.257.10:38:21.30#ibcon#read 4, iclass 24, count 0 2006.257.10:38:21.30#ibcon#about to read 5, iclass 24, count 0 2006.257.10:38:21.30#ibcon#read 5, iclass 24, count 0 2006.257.10:38:21.30#ibcon#about to read 6, iclass 24, count 0 2006.257.10:38:21.30#ibcon#read 6, iclass 24, count 0 2006.257.10:38:21.30#ibcon#end of sib2, iclass 24, count 0 2006.257.10:38:21.30#ibcon#*after write, iclass 24, count 0 2006.257.10:38:21.30#ibcon#*before return 0, iclass 24, count 0 2006.257.10:38:21.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:21.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:21.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:38:21.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:38:21.30$vck44/va=1,8 2006.257.10:38:21.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.10:38:21.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.10:38:21.30#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:21.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:21.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:21.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:21.30#ibcon#enter wrdev, iclass 26, count 2 2006.257.10:38:21.30#ibcon#first serial, iclass 26, count 2 2006.257.10:38:21.30#ibcon#enter sib2, iclass 26, count 2 2006.257.10:38:21.30#ibcon#flushed, iclass 26, count 2 2006.257.10:38:21.30#ibcon#about to write, iclass 26, count 2 2006.257.10:38:21.30#ibcon#wrote, iclass 26, count 2 2006.257.10:38:21.30#ibcon#about to read 3, iclass 26, count 2 2006.257.10:38:21.32#ibcon#read 3, iclass 26, count 2 2006.257.10:38:21.32#ibcon#about to read 4, iclass 26, count 2 2006.257.10:38:21.32#ibcon#read 4, iclass 26, count 2 2006.257.10:38:21.32#ibcon#about to read 5, iclass 26, count 2 2006.257.10:38:21.32#ibcon#read 5, iclass 26, count 2 2006.257.10:38:21.32#ibcon#about to read 6, iclass 26, count 2 2006.257.10:38:21.32#ibcon#read 6, iclass 26, count 2 2006.257.10:38:21.32#ibcon#end of sib2, iclass 26, count 2 2006.257.10:38:21.32#ibcon#*mode == 0, iclass 26, count 2 2006.257.10:38:21.32#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.10:38:21.32#ibcon#[25=AT01-08\r\n] 2006.257.10:38:21.32#ibcon#*before write, iclass 26, count 2 2006.257.10:38:21.32#ibcon#enter sib2, iclass 26, count 2 2006.257.10:38:21.32#ibcon#flushed, iclass 26, count 2 2006.257.10:38:21.32#ibcon#about to write, iclass 26, count 2 2006.257.10:38:21.32#ibcon#wrote, iclass 26, count 2 2006.257.10:38:21.32#ibcon#about to read 3, iclass 26, count 2 2006.257.10:38:21.35#ibcon#read 3, iclass 26, count 2 2006.257.10:38:21.35#ibcon#about to read 4, iclass 26, count 2 2006.257.10:38:21.35#ibcon#read 4, iclass 26, count 2 2006.257.10:38:21.35#ibcon#about to read 5, iclass 26, count 2 2006.257.10:38:21.35#ibcon#read 5, iclass 26, count 2 2006.257.10:38:21.35#ibcon#about to read 6, iclass 26, count 2 2006.257.10:38:21.35#ibcon#read 6, iclass 26, count 2 2006.257.10:38:21.35#ibcon#end of sib2, iclass 26, count 2 2006.257.10:38:21.35#ibcon#*after write, iclass 26, count 2 2006.257.10:38:21.35#ibcon#*before return 0, iclass 26, count 2 2006.257.10:38:21.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:21.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:21.35#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.10:38:21.35#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:21.35#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:21.47#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:21.47#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:21.47#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:38:21.47#ibcon#first serial, iclass 26, count 0 2006.257.10:38:21.47#ibcon#enter sib2, iclass 26, count 0 2006.257.10:38:21.47#ibcon#flushed, iclass 26, count 0 2006.257.10:38:21.47#ibcon#about to write, iclass 26, count 0 2006.257.10:38:21.47#ibcon#wrote, iclass 26, count 0 2006.257.10:38:21.47#ibcon#about to read 3, iclass 26, count 0 2006.257.10:38:21.49#ibcon#read 3, iclass 26, count 0 2006.257.10:38:21.49#ibcon#about to read 4, iclass 26, count 0 2006.257.10:38:21.49#ibcon#read 4, iclass 26, count 0 2006.257.10:38:21.49#ibcon#about to read 5, iclass 26, count 0 2006.257.10:38:21.49#ibcon#read 5, iclass 26, count 0 2006.257.10:38:21.49#ibcon#about to read 6, iclass 26, count 0 2006.257.10:38:21.49#ibcon#read 6, iclass 26, count 0 2006.257.10:38:21.49#ibcon#end of sib2, iclass 26, count 0 2006.257.10:38:21.49#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:38:21.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:38:21.49#ibcon#[25=USB\r\n] 2006.257.10:38:21.49#ibcon#*before write, iclass 26, count 0 2006.257.10:38:21.49#ibcon#enter sib2, iclass 26, count 0 2006.257.10:38:21.49#ibcon#flushed, iclass 26, count 0 2006.257.10:38:21.49#ibcon#about to write, iclass 26, count 0 2006.257.10:38:21.49#ibcon#wrote, iclass 26, count 0 2006.257.10:38:21.49#ibcon#about to read 3, iclass 26, count 0 2006.257.10:38:21.52#ibcon#read 3, iclass 26, count 0 2006.257.10:38:21.52#ibcon#about to read 4, iclass 26, count 0 2006.257.10:38:21.52#ibcon#read 4, iclass 26, count 0 2006.257.10:38:21.52#ibcon#about to read 5, iclass 26, count 0 2006.257.10:38:21.52#ibcon#read 5, iclass 26, count 0 2006.257.10:38:21.52#ibcon#about to read 6, iclass 26, count 0 2006.257.10:38:21.52#ibcon#read 6, iclass 26, count 0 2006.257.10:38:21.52#ibcon#end of sib2, iclass 26, count 0 2006.257.10:38:21.52#ibcon#*after write, iclass 26, count 0 2006.257.10:38:21.52#ibcon#*before return 0, iclass 26, count 0 2006.257.10:38:21.52#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:21.52#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:21.52#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:38:21.52#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:38:21.52$vck44/valo=2,534.99 2006.257.10:38:21.52#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.10:38:21.52#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.10:38:21.52#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:21.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:21.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:21.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:21.52#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:38:21.52#ibcon#first serial, iclass 28, count 0 2006.257.10:38:21.52#ibcon#enter sib2, iclass 28, count 0 2006.257.10:38:21.52#ibcon#flushed, iclass 28, count 0 2006.257.10:38:21.52#ibcon#about to write, iclass 28, count 0 2006.257.10:38:21.52#ibcon#wrote, iclass 28, count 0 2006.257.10:38:21.52#ibcon#about to read 3, iclass 28, count 0 2006.257.10:38:21.54#ibcon#read 3, iclass 28, count 0 2006.257.10:38:21.54#ibcon#about to read 4, iclass 28, count 0 2006.257.10:38:21.54#ibcon#read 4, iclass 28, count 0 2006.257.10:38:21.54#ibcon#about to read 5, iclass 28, count 0 2006.257.10:38:21.54#ibcon#read 5, iclass 28, count 0 2006.257.10:38:21.54#ibcon#about to read 6, iclass 28, count 0 2006.257.10:38:21.54#ibcon#read 6, iclass 28, count 0 2006.257.10:38:21.54#ibcon#end of sib2, iclass 28, count 0 2006.257.10:38:21.54#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:38:21.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:38:21.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:38:21.54#ibcon#*before write, iclass 28, count 0 2006.257.10:38:21.54#ibcon#enter sib2, iclass 28, count 0 2006.257.10:38:21.54#ibcon#flushed, iclass 28, count 0 2006.257.10:38:21.54#ibcon#about to write, iclass 28, count 0 2006.257.10:38:21.54#ibcon#wrote, iclass 28, count 0 2006.257.10:38:21.54#ibcon#about to read 3, iclass 28, count 0 2006.257.10:38:21.58#ibcon#read 3, iclass 28, count 0 2006.257.10:38:21.58#ibcon#about to read 4, iclass 28, count 0 2006.257.10:38:21.58#ibcon#read 4, iclass 28, count 0 2006.257.10:38:21.58#ibcon#about to read 5, iclass 28, count 0 2006.257.10:38:21.58#ibcon#read 5, iclass 28, count 0 2006.257.10:38:21.58#ibcon#about to read 6, iclass 28, count 0 2006.257.10:38:21.58#ibcon#read 6, iclass 28, count 0 2006.257.10:38:21.58#ibcon#end of sib2, iclass 28, count 0 2006.257.10:38:21.58#ibcon#*after write, iclass 28, count 0 2006.257.10:38:21.58#ibcon#*before return 0, iclass 28, count 0 2006.257.10:38:21.58#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:21.58#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:21.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:38:21.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:38:21.58$vck44/va=2,7 2006.257.10:38:21.58#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.10:38:21.58#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.10:38:21.58#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:21.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:21.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:21.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:21.64#ibcon#enter wrdev, iclass 30, count 2 2006.257.10:38:21.64#ibcon#first serial, iclass 30, count 2 2006.257.10:38:21.64#ibcon#enter sib2, iclass 30, count 2 2006.257.10:38:21.64#ibcon#flushed, iclass 30, count 2 2006.257.10:38:21.64#ibcon#about to write, iclass 30, count 2 2006.257.10:38:21.64#ibcon#wrote, iclass 30, count 2 2006.257.10:38:21.64#ibcon#about to read 3, iclass 30, count 2 2006.257.10:38:21.66#ibcon#read 3, iclass 30, count 2 2006.257.10:38:21.66#ibcon#about to read 4, iclass 30, count 2 2006.257.10:38:21.66#ibcon#read 4, iclass 30, count 2 2006.257.10:38:21.66#ibcon#about to read 5, iclass 30, count 2 2006.257.10:38:21.66#ibcon#read 5, iclass 30, count 2 2006.257.10:38:21.66#ibcon#about to read 6, iclass 30, count 2 2006.257.10:38:21.66#ibcon#read 6, iclass 30, count 2 2006.257.10:38:21.66#ibcon#end of sib2, iclass 30, count 2 2006.257.10:38:21.66#ibcon#*mode == 0, iclass 30, count 2 2006.257.10:38:21.66#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.10:38:21.66#ibcon#[25=AT02-07\r\n] 2006.257.10:38:21.66#ibcon#*before write, iclass 30, count 2 2006.257.10:38:21.66#ibcon#enter sib2, iclass 30, count 2 2006.257.10:38:21.66#ibcon#flushed, iclass 30, count 2 2006.257.10:38:21.66#ibcon#about to write, iclass 30, count 2 2006.257.10:38:21.66#ibcon#wrote, iclass 30, count 2 2006.257.10:38:21.66#ibcon#about to read 3, iclass 30, count 2 2006.257.10:38:21.69#ibcon#read 3, iclass 30, count 2 2006.257.10:38:21.69#ibcon#about to read 4, iclass 30, count 2 2006.257.10:38:21.69#ibcon#read 4, iclass 30, count 2 2006.257.10:38:21.69#ibcon#about to read 5, iclass 30, count 2 2006.257.10:38:21.69#ibcon#read 5, iclass 30, count 2 2006.257.10:38:21.69#ibcon#about to read 6, iclass 30, count 2 2006.257.10:38:21.69#ibcon#read 6, iclass 30, count 2 2006.257.10:38:21.69#ibcon#end of sib2, iclass 30, count 2 2006.257.10:38:21.69#ibcon#*after write, iclass 30, count 2 2006.257.10:38:21.69#ibcon#*before return 0, iclass 30, count 2 2006.257.10:38:21.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:21.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:21.69#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.10:38:21.69#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:21.69#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:21.81#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:21.81#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:21.81#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:38:21.81#ibcon#first serial, iclass 30, count 0 2006.257.10:38:21.81#ibcon#enter sib2, iclass 30, count 0 2006.257.10:38:21.81#ibcon#flushed, iclass 30, count 0 2006.257.10:38:21.81#ibcon#about to write, iclass 30, count 0 2006.257.10:38:21.81#ibcon#wrote, iclass 30, count 0 2006.257.10:38:21.81#ibcon#about to read 3, iclass 30, count 0 2006.257.10:38:21.83#ibcon#read 3, iclass 30, count 0 2006.257.10:38:21.83#ibcon#about to read 4, iclass 30, count 0 2006.257.10:38:21.83#ibcon#read 4, iclass 30, count 0 2006.257.10:38:21.83#ibcon#about to read 5, iclass 30, count 0 2006.257.10:38:21.83#ibcon#read 5, iclass 30, count 0 2006.257.10:38:21.83#ibcon#about to read 6, iclass 30, count 0 2006.257.10:38:21.83#ibcon#read 6, iclass 30, count 0 2006.257.10:38:21.83#ibcon#end of sib2, iclass 30, count 0 2006.257.10:38:21.83#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:38:21.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:38:21.83#ibcon#[25=USB\r\n] 2006.257.10:38:21.83#ibcon#*before write, iclass 30, count 0 2006.257.10:38:21.83#ibcon#enter sib2, iclass 30, count 0 2006.257.10:38:21.83#ibcon#flushed, iclass 30, count 0 2006.257.10:38:21.83#ibcon#about to write, iclass 30, count 0 2006.257.10:38:21.83#ibcon#wrote, iclass 30, count 0 2006.257.10:38:21.83#ibcon#about to read 3, iclass 30, count 0 2006.257.10:38:21.86#ibcon#read 3, iclass 30, count 0 2006.257.10:38:21.86#ibcon#about to read 4, iclass 30, count 0 2006.257.10:38:21.86#ibcon#read 4, iclass 30, count 0 2006.257.10:38:21.86#ibcon#about to read 5, iclass 30, count 0 2006.257.10:38:21.86#ibcon#read 5, iclass 30, count 0 2006.257.10:38:21.86#ibcon#about to read 6, iclass 30, count 0 2006.257.10:38:21.86#ibcon#read 6, iclass 30, count 0 2006.257.10:38:21.86#ibcon#end of sib2, iclass 30, count 0 2006.257.10:38:21.86#ibcon#*after write, iclass 30, count 0 2006.257.10:38:21.86#ibcon#*before return 0, iclass 30, count 0 2006.257.10:38:21.86#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:21.86#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:21.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:38:21.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:38:21.86$vck44/valo=3,564.99 2006.257.10:38:21.86#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.10:38:21.86#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.10:38:21.86#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:21.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:21.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:21.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:21.86#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:38:21.86#ibcon#first serial, iclass 32, count 0 2006.257.10:38:21.86#ibcon#enter sib2, iclass 32, count 0 2006.257.10:38:21.86#ibcon#flushed, iclass 32, count 0 2006.257.10:38:21.86#ibcon#about to write, iclass 32, count 0 2006.257.10:38:21.86#ibcon#wrote, iclass 32, count 0 2006.257.10:38:21.86#ibcon#about to read 3, iclass 32, count 0 2006.257.10:38:21.88#ibcon#read 3, iclass 32, count 0 2006.257.10:38:21.88#ibcon#about to read 4, iclass 32, count 0 2006.257.10:38:21.88#ibcon#read 4, iclass 32, count 0 2006.257.10:38:21.88#ibcon#about to read 5, iclass 32, count 0 2006.257.10:38:21.88#ibcon#read 5, iclass 32, count 0 2006.257.10:38:21.88#ibcon#about to read 6, iclass 32, count 0 2006.257.10:38:21.88#ibcon#read 6, iclass 32, count 0 2006.257.10:38:21.88#ibcon#end of sib2, iclass 32, count 0 2006.257.10:38:21.88#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:38:21.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:38:21.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:38:21.88#ibcon#*before write, iclass 32, count 0 2006.257.10:38:21.88#ibcon#enter sib2, iclass 32, count 0 2006.257.10:38:21.88#ibcon#flushed, iclass 32, count 0 2006.257.10:38:21.88#ibcon#about to write, iclass 32, count 0 2006.257.10:38:21.88#ibcon#wrote, iclass 32, count 0 2006.257.10:38:21.88#ibcon#about to read 3, iclass 32, count 0 2006.257.10:38:21.92#ibcon#read 3, iclass 32, count 0 2006.257.10:38:21.92#ibcon#about to read 4, iclass 32, count 0 2006.257.10:38:21.92#ibcon#read 4, iclass 32, count 0 2006.257.10:38:21.92#ibcon#about to read 5, iclass 32, count 0 2006.257.10:38:21.92#ibcon#read 5, iclass 32, count 0 2006.257.10:38:21.92#ibcon#about to read 6, iclass 32, count 0 2006.257.10:38:21.92#ibcon#read 6, iclass 32, count 0 2006.257.10:38:21.92#ibcon#end of sib2, iclass 32, count 0 2006.257.10:38:21.92#ibcon#*after write, iclass 32, count 0 2006.257.10:38:21.92#ibcon#*before return 0, iclass 32, count 0 2006.257.10:38:21.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:21.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:21.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:38:21.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:38:21.92$vck44/va=3,8 2006.257.10:38:21.92#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.10:38:21.92#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.10:38:21.92#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:21.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:21.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:21.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:21.98#ibcon#enter wrdev, iclass 34, count 2 2006.257.10:38:21.98#ibcon#first serial, iclass 34, count 2 2006.257.10:38:21.98#ibcon#enter sib2, iclass 34, count 2 2006.257.10:38:21.98#ibcon#flushed, iclass 34, count 2 2006.257.10:38:21.98#ibcon#about to write, iclass 34, count 2 2006.257.10:38:21.98#ibcon#wrote, iclass 34, count 2 2006.257.10:38:21.98#ibcon#about to read 3, iclass 34, count 2 2006.257.10:38:22.00#ibcon#read 3, iclass 34, count 2 2006.257.10:38:22.00#ibcon#about to read 4, iclass 34, count 2 2006.257.10:38:22.00#ibcon#read 4, iclass 34, count 2 2006.257.10:38:22.00#ibcon#about to read 5, iclass 34, count 2 2006.257.10:38:22.00#ibcon#read 5, iclass 34, count 2 2006.257.10:38:22.00#ibcon#about to read 6, iclass 34, count 2 2006.257.10:38:22.00#ibcon#read 6, iclass 34, count 2 2006.257.10:38:22.00#ibcon#end of sib2, iclass 34, count 2 2006.257.10:38:22.00#ibcon#*mode == 0, iclass 34, count 2 2006.257.10:38:22.00#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.10:38:22.00#ibcon#[25=AT03-08\r\n] 2006.257.10:38:22.00#ibcon#*before write, iclass 34, count 2 2006.257.10:38:22.00#ibcon#enter sib2, iclass 34, count 2 2006.257.10:38:22.00#ibcon#flushed, iclass 34, count 2 2006.257.10:38:22.00#ibcon#about to write, iclass 34, count 2 2006.257.10:38:22.00#ibcon#wrote, iclass 34, count 2 2006.257.10:38:22.00#ibcon#about to read 3, iclass 34, count 2 2006.257.10:38:22.03#ibcon#read 3, iclass 34, count 2 2006.257.10:38:22.03#ibcon#about to read 4, iclass 34, count 2 2006.257.10:38:22.03#ibcon#read 4, iclass 34, count 2 2006.257.10:38:22.03#ibcon#about to read 5, iclass 34, count 2 2006.257.10:38:22.03#ibcon#read 5, iclass 34, count 2 2006.257.10:38:22.03#ibcon#about to read 6, iclass 34, count 2 2006.257.10:38:22.03#ibcon#read 6, iclass 34, count 2 2006.257.10:38:22.03#ibcon#end of sib2, iclass 34, count 2 2006.257.10:38:22.03#ibcon#*after write, iclass 34, count 2 2006.257.10:38:22.03#ibcon#*before return 0, iclass 34, count 2 2006.257.10:38:22.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:22.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:22.03#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.10:38:22.03#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:22.03#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:22.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:22.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:22.15#ibcon#enter wrdev, iclass 34, count 0 2006.257.10:38:22.15#ibcon#first serial, iclass 34, count 0 2006.257.10:38:22.15#ibcon#enter sib2, iclass 34, count 0 2006.257.10:38:22.15#ibcon#flushed, iclass 34, count 0 2006.257.10:38:22.15#ibcon#about to write, iclass 34, count 0 2006.257.10:38:22.15#ibcon#wrote, iclass 34, count 0 2006.257.10:38:22.15#ibcon#about to read 3, iclass 34, count 0 2006.257.10:38:22.17#ibcon#read 3, iclass 34, count 0 2006.257.10:38:22.17#ibcon#about to read 4, iclass 34, count 0 2006.257.10:38:22.17#ibcon#read 4, iclass 34, count 0 2006.257.10:38:22.17#ibcon#about to read 5, iclass 34, count 0 2006.257.10:38:22.17#ibcon#read 5, iclass 34, count 0 2006.257.10:38:22.17#ibcon#about to read 6, iclass 34, count 0 2006.257.10:38:22.17#ibcon#read 6, iclass 34, count 0 2006.257.10:38:22.17#ibcon#end of sib2, iclass 34, count 0 2006.257.10:38:22.17#ibcon#*mode == 0, iclass 34, count 0 2006.257.10:38:22.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.10:38:22.17#ibcon#[25=USB\r\n] 2006.257.10:38:22.17#ibcon#*before write, iclass 34, count 0 2006.257.10:38:22.17#ibcon#enter sib2, iclass 34, count 0 2006.257.10:38:22.17#ibcon#flushed, iclass 34, count 0 2006.257.10:38:22.17#ibcon#about to write, iclass 34, count 0 2006.257.10:38:22.17#ibcon#wrote, iclass 34, count 0 2006.257.10:38:22.17#ibcon#about to read 3, iclass 34, count 0 2006.257.10:38:22.20#ibcon#read 3, iclass 34, count 0 2006.257.10:38:22.20#ibcon#about to read 4, iclass 34, count 0 2006.257.10:38:22.20#ibcon#read 4, iclass 34, count 0 2006.257.10:38:22.20#ibcon#about to read 5, iclass 34, count 0 2006.257.10:38:22.20#ibcon#read 5, iclass 34, count 0 2006.257.10:38:22.20#ibcon#about to read 6, iclass 34, count 0 2006.257.10:38:22.20#ibcon#read 6, iclass 34, count 0 2006.257.10:38:22.20#ibcon#end of sib2, iclass 34, count 0 2006.257.10:38:22.20#ibcon#*after write, iclass 34, count 0 2006.257.10:38:22.20#ibcon#*before return 0, iclass 34, count 0 2006.257.10:38:22.20#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:22.20#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:22.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.10:38:22.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.10:38:22.20$vck44/valo=4,624.99 2006.257.10:38:22.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.10:38:22.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.10:38:22.20#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:22.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:38:22.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:38:22.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:38:22.20#ibcon#enter wrdev, iclass 36, count 0 2006.257.10:38:22.20#ibcon#first serial, iclass 36, count 0 2006.257.10:38:22.20#ibcon#enter sib2, iclass 36, count 0 2006.257.10:38:22.20#ibcon#flushed, iclass 36, count 0 2006.257.10:38:22.20#ibcon#about to write, iclass 36, count 0 2006.257.10:38:22.20#ibcon#wrote, iclass 36, count 0 2006.257.10:38:22.20#ibcon#about to read 3, iclass 36, count 0 2006.257.10:38:22.22#ibcon#read 3, iclass 36, count 0 2006.257.10:38:22.22#ibcon#about to read 4, iclass 36, count 0 2006.257.10:38:22.22#ibcon#read 4, iclass 36, count 0 2006.257.10:38:22.22#ibcon#about to read 5, iclass 36, count 0 2006.257.10:38:22.22#ibcon#read 5, iclass 36, count 0 2006.257.10:38:22.22#ibcon#about to read 6, iclass 36, count 0 2006.257.10:38:22.22#ibcon#read 6, iclass 36, count 0 2006.257.10:38:22.22#ibcon#end of sib2, iclass 36, count 0 2006.257.10:38:22.22#ibcon#*mode == 0, iclass 36, count 0 2006.257.10:38:22.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.10:38:22.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:38:22.22#ibcon#*before write, iclass 36, count 0 2006.257.10:38:22.22#ibcon#enter sib2, iclass 36, count 0 2006.257.10:38:22.22#ibcon#flushed, iclass 36, count 0 2006.257.10:38:22.22#ibcon#about to write, iclass 36, count 0 2006.257.10:38:22.22#ibcon#wrote, iclass 36, count 0 2006.257.10:38:22.22#ibcon#about to read 3, iclass 36, count 0 2006.257.10:38:22.26#ibcon#read 3, iclass 36, count 0 2006.257.10:38:22.26#ibcon#about to read 4, iclass 36, count 0 2006.257.10:38:22.26#ibcon#read 4, iclass 36, count 0 2006.257.10:38:22.26#ibcon#about to read 5, iclass 36, count 0 2006.257.10:38:22.26#ibcon#read 5, iclass 36, count 0 2006.257.10:38:22.26#ibcon#about to read 6, iclass 36, count 0 2006.257.10:38:22.26#ibcon#read 6, iclass 36, count 0 2006.257.10:38:22.26#ibcon#end of sib2, iclass 36, count 0 2006.257.10:38:22.26#ibcon#*after write, iclass 36, count 0 2006.257.10:38:22.26#ibcon#*before return 0, iclass 36, count 0 2006.257.10:38:22.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:38:22.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.10:38:22.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.10:38:22.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.10:38:22.26$vck44/va=4,7 2006.257.10:38:22.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.10:38:22.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.10:38:22.26#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:22.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:38:22.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:38:22.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:38:22.32#ibcon#enter wrdev, iclass 38, count 2 2006.257.10:38:22.32#ibcon#first serial, iclass 38, count 2 2006.257.10:38:22.32#ibcon#enter sib2, iclass 38, count 2 2006.257.10:38:22.32#ibcon#flushed, iclass 38, count 2 2006.257.10:38:22.32#ibcon#about to write, iclass 38, count 2 2006.257.10:38:22.32#ibcon#wrote, iclass 38, count 2 2006.257.10:38:22.32#ibcon#about to read 3, iclass 38, count 2 2006.257.10:38:22.34#ibcon#read 3, iclass 38, count 2 2006.257.10:38:22.34#ibcon#about to read 4, iclass 38, count 2 2006.257.10:38:22.34#ibcon#read 4, iclass 38, count 2 2006.257.10:38:22.34#ibcon#about to read 5, iclass 38, count 2 2006.257.10:38:22.34#ibcon#read 5, iclass 38, count 2 2006.257.10:38:22.34#ibcon#about to read 6, iclass 38, count 2 2006.257.10:38:22.34#ibcon#read 6, iclass 38, count 2 2006.257.10:38:22.34#ibcon#end of sib2, iclass 38, count 2 2006.257.10:38:22.34#ibcon#*mode == 0, iclass 38, count 2 2006.257.10:38:22.34#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.10:38:22.34#ibcon#[25=AT04-07\r\n] 2006.257.10:38:22.34#ibcon#*before write, iclass 38, count 2 2006.257.10:38:22.34#ibcon#enter sib2, iclass 38, count 2 2006.257.10:38:22.34#ibcon#flushed, iclass 38, count 2 2006.257.10:38:22.34#ibcon#about to write, iclass 38, count 2 2006.257.10:38:22.34#ibcon#wrote, iclass 38, count 2 2006.257.10:38:22.34#ibcon#about to read 3, iclass 38, count 2 2006.257.10:38:22.37#ibcon#read 3, iclass 38, count 2 2006.257.10:38:22.39#ibcon#about to read 4, iclass 38, count 2 2006.257.10:38:22.39#ibcon#read 4, iclass 38, count 2 2006.257.10:38:22.39#ibcon#about to read 5, iclass 38, count 2 2006.257.10:38:22.39#ibcon#read 5, iclass 38, count 2 2006.257.10:38:22.39#ibcon#about to read 6, iclass 38, count 2 2006.257.10:38:22.39#ibcon#read 6, iclass 38, count 2 2006.257.10:38:22.39#ibcon#end of sib2, iclass 38, count 2 2006.257.10:38:22.40#ibcon#*after write, iclass 38, count 2 2006.257.10:38:22.40#ibcon#*before return 0, iclass 38, count 2 2006.257.10:38:22.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:38:22.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.10:38:22.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.10:38:22.40#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:22.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:38:22.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:38:22.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:38:22.51#ibcon#enter wrdev, iclass 38, count 0 2006.257.10:38:22.51#ibcon#first serial, iclass 38, count 0 2006.257.10:38:22.51#ibcon#enter sib2, iclass 38, count 0 2006.257.10:38:22.51#ibcon#flushed, iclass 38, count 0 2006.257.10:38:22.51#ibcon#about to write, iclass 38, count 0 2006.257.10:38:22.51#ibcon#wrote, iclass 38, count 0 2006.257.10:38:22.51#ibcon#about to read 3, iclass 38, count 0 2006.257.10:38:22.53#ibcon#read 3, iclass 38, count 0 2006.257.10:38:22.53#ibcon#about to read 4, iclass 38, count 0 2006.257.10:38:22.53#ibcon#read 4, iclass 38, count 0 2006.257.10:38:22.53#ibcon#about to read 5, iclass 38, count 0 2006.257.10:38:22.53#ibcon#read 5, iclass 38, count 0 2006.257.10:38:22.53#ibcon#about to read 6, iclass 38, count 0 2006.257.10:38:22.53#ibcon#read 6, iclass 38, count 0 2006.257.10:38:22.53#ibcon#end of sib2, iclass 38, count 0 2006.257.10:38:22.53#ibcon#*mode == 0, iclass 38, count 0 2006.257.10:38:22.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.10:38:22.53#ibcon#[25=USB\r\n] 2006.257.10:38:22.53#ibcon#*before write, iclass 38, count 0 2006.257.10:38:22.53#ibcon#enter sib2, iclass 38, count 0 2006.257.10:38:22.53#ibcon#flushed, iclass 38, count 0 2006.257.10:38:22.53#ibcon#about to write, iclass 38, count 0 2006.257.10:38:22.53#ibcon#wrote, iclass 38, count 0 2006.257.10:38:22.53#ibcon#about to read 3, iclass 38, count 0 2006.257.10:38:22.56#ibcon#read 3, iclass 38, count 0 2006.257.10:38:22.56#ibcon#about to read 4, iclass 38, count 0 2006.257.10:38:22.56#ibcon#read 4, iclass 38, count 0 2006.257.10:38:22.56#ibcon#about to read 5, iclass 38, count 0 2006.257.10:38:22.56#ibcon#read 5, iclass 38, count 0 2006.257.10:38:22.56#ibcon#about to read 6, iclass 38, count 0 2006.257.10:38:22.56#ibcon#read 6, iclass 38, count 0 2006.257.10:38:22.56#ibcon#end of sib2, iclass 38, count 0 2006.257.10:38:22.56#ibcon#*after write, iclass 38, count 0 2006.257.10:38:22.56#ibcon#*before return 0, iclass 38, count 0 2006.257.10:38:22.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:38:22.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.10:38:22.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.10:38:22.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.10:38:22.56$vck44/valo=5,734.99 2006.257.10:38:22.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.10:38:22.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.10:38:22.56#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:22.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:22.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:22.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:22.56#ibcon#enter wrdev, iclass 40, count 0 2006.257.10:38:22.56#ibcon#first serial, iclass 40, count 0 2006.257.10:38:22.56#ibcon#enter sib2, iclass 40, count 0 2006.257.10:38:22.56#ibcon#flushed, iclass 40, count 0 2006.257.10:38:22.56#ibcon#about to write, iclass 40, count 0 2006.257.10:38:22.56#ibcon#wrote, iclass 40, count 0 2006.257.10:38:22.56#ibcon#about to read 3, iclass 40, count 0 2006.257.10:38:22.58#ibcon#read 3, iclass 40, count 0 2006.257.10:38:22.58#ibcon#about to read 4, iclass 40, count 0 2006.257.10:38:22.58#ibcon#read 4, iclass 40, count 0 2006.257.10:38:22.58#ibcon#about to read 5, iclass 40, count 0 2006.257.10:38:22.58#ibcon#read 5, iclass 40, count 0 2006.257.10:38:22.58#ibcon#about to read 6, iclass 40, count 0 2006.257.10:38:22.58#ibcon#read 6, iclass 40, count 0 2006.257.10:38:22.58#ibcon#end of sib2, iclass 40, count 0 2006.257.10:38:22.58#ibcon#*mode == 0, iclass 40, count 0 2006.257.10:38:22.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.10:38:22.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:38:22.58#ibcon#*before write, iclass 40, count 0 2006.257.10:38:22.58#ibcon#enter sib2, iclass 40, count 0 2006.257.10:38:22.58#ibcon#flushed, iclass 40, count 0 2006.257.10:38:22.58#ibcon#about to write, iclass 40, count 0 2006.257.10:38:22.58#ibcon#wrote, iclass 40, count 0 2006.257.10:38:22.58#ibcon#about to read 3, iclass 40, count 0 2006.257.10:38:22.62#ibcon#read 3, iclass 40, count 0 2006.257.10:38:22.62#ibcon#about to read 4, iclass 40, count 0 2006.257.10:38:22.62#ibcon#read 4, iclass 40, count 0 2006.257.10:38:22.62#ibcon#about to read 5, iclass 40, count 0 2006.257.10:38:22.62#ibcon#read 5, iclass 40, count 0 2006.257.10:38:22.62#ibcon#about to read 6, iclass 40, count 0 2006.257.10:38:22.62#ibcon#read 6, iclass 40, count 0 2006.257.10:38:22.62#ibcon#end of sib2, iclass 40, count 0 2006.257.10:38:22.62#ibcon#*after write, iclass 40, count 0 2006.257.10:38:22.62#ibcon#*before return 0, iclass 40, count 0 2006.257.10:38:22.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:22.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:22.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.10:38:22.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.10:38:22.62$vck44/va=5,4 2006.257.10:38:22.62#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.10:38:22.62#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.10:38:22.62#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:22.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:22.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:22.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:22.68#ibcon#enter wrdev, iclass 4, count 2 2006.257.10:38:22.68#ibcon#first serial, iclass 4, count 2 2006.257.10:38:22.68#ibcon#enter sib2, iclass 4, count 2 2006.257.10:38:22.68#ibcon#flushed, iclass 4, count 2 2006.257.10:38:22.68#ibcon#about to write, iclass 4, count 2 2006.257.10:38:22.68#ibcon#wrote, iclass 4, count 2 2006.257.10:38:22.68#ibcon#about to read 3, iclass 4, count 2 2006.257.10:38:22.70#ibcon#read 3, iclass 4, count 2 2006.257.10:38:22.70#ibcon#about to read 4, iclass 4, count 2 2006.257.10:38:22.70#ibcon#read 4, iclass 4, count 2 2006.257.10:38:22.70#ibcon#about to read 5, iclass 4, count 2 2006.257.10:38:22.70#ibcon#read 5, iclass 4, count 2 2006.257.10:38:22.70#ibcon#about to read 6, iclass 4, count 2 2006.257.10:38:22.70#ibcon#read 6, iclass 4, count 2 2006.257.10:38:22.70#ibcon#end of sib2, iclass 4, count 2 2006.257.10:38:22.70#ibcon#*mode == 0, iclass 4, count 2 2006.257.10:38:22.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.10:38:22.70#ibcon#[25=AT05-04\r\n] 2006.257.10:38:22.70#ibcon#*before write, iclass 4, count 2 2006.257.10:38:22.70#ibcon#enter sib2, iclass 4, count 2 2006.257.10:38:22.70#ibcon#flushed, iclass 4, count 2 2006.257.10:38:22.70#ibcon#about to write, iclass 4, count 2 2006.257.10:38:22.70#ibcon#wrote, iclass 4, count 2 2006.257.10:38:22.70#ibcon#about to read 3, iclass 4, count 2 2006.257.10:38:22.73#ibcon#read 3, iclass 4, count 2 2006.257.10:38:22.73#ibcon#about to read 4, iclass 4, count 2 2006.257.10:38:22.73#ibcon#read 4, iclass 4, count 2 2006.257.10:38:22.73#ibcon#about to read 5, iclass 4, count 2 2006.257.10:38:22.73#ibcon#read 5, iclass 4, count 2 2006.257.10:38:22.73#ibcon#about to read 6, iclass 4, count 2 2006.257.10:38:22.73#ibcon#read 6, iclass 4, count 2 2006.257.10:38:22.73#ibcon#end of sib2, iclass 4, count 2 2006.257.10:38:22.73#ibcon#*after write, iclass 4, count 2 2006.257.10:38:22.73#ibcon#*before return 0, iclass 4, count 2 2006.257.10:38:22.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:22.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:22.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.10:38:22.73#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:22.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:22.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:22.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:22.85#ibcon#enter wrdev, iclass 4, count 0 2006.257.10:38:22.85#ibcon#first serial, iclass 4, count 0 2006.257.10:38:22.85#ibcon#enter sib2, iclass 4, count 0 2006.257.10:38:22.85#ibcon#flushed, iclass 4, count 0 2006.257.10:38:22.85#ibcon#about to write, iclass 4, count 0 2006.257.10:38:22.85#ibcon#wrote, iclass 4, count 0 2006.257.10:38:22.85#ibcon#about to read 3, iclass 4, count 0 2006.257.10:38:22.87#ibcon#read 3, iclass 4, count 0 2006.257.10:38:22.87#ibcon#about to read 4, iclass 4, count 0 2006.257.10:38:22.87#ibcon#read 4, iclass 4, count 0 2006.257.10:38:22.87#ibcon#about to read 5, iclass 4, count 0 2006.257.10:38:22.87#ibcon#read 5, iclass 4, count 0 2006.257.10:38:22.87#ibcon#about to read 6, iclass 4, count 0 2006.257.10:38:22.87#ibcon#read 6, iclass 4, count 0 2006.257.10:38:22.87#ibcon#end of sib2, iclass 4, count 0 2006.257.10:38:22.87#ibcon#*mode == 0, iclass 4, count 0 2006.257.10:38:22.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.10:38:22.87#ibcon#[25=USB\r\n] 2006.257.10:38:22.87#ibcon#*before write, iclass 4, count 0 2006.257.10:38:22.87#ibcon#enter sib2, iclass 4, count 0 2006.257.10:38:22.87#ibcon#flushed, iclass 4, count 0 2006.257.10:38:22.87#ibcon#about to write, iclass 4, count 0 2006.257.10:38:22.87#ibcon#wrote, iclass 4, count 0 2006.257.10:38:22.87#ibcon#about to read 3, iclass 4, count 0 2006.257.10:38:22.90#ibcon#read 3, iclass 4, count 0 2006.257.10:38:22.90#ibcon#about to read 4, iclass 4, count 0 2006.257.10:38:22.90#ibcon#read 4, iclass 4, count 0 2006.257.10:38:22.90#ibcon#about to read 5, iclass 4, count 0 2006.257.10:38:22.90#ibcon#read 5, iclass 4, count 0 2006.257.10:38:22.90#ibcon#about to read 6, iclass 4, count 0 2006.257.10:38:22.90#ibcon#read 6, iclass 4, count 0 2006.257.10:38:22.90#ibcon#end of sib2, iclass 4, count 0 2006.257.10:38:22.90#ibcon#*after write, iclass 4, count 0 2006.257.10:38:22.90#ibcon#*before return 0, iclass 4, count 0 2006.257.10:38:22.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:22.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:22.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.10:38:22.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.10:38:22.90$vck44/valo=6,814.99 2006.257.10:38:22.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.10:38:22.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.10:38:22.90#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:22.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:22.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:22.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:22.90#ibcon#enter wrdev, iclass 6, count 0 2006.257.10:38:22.90#ibcon#first serial, iclass 6, count 0 2006.257.10:38:22.90#ibcon#enter sib2, iclass 6, count 0 2006.257.10:38:22.90#ibcon#flushed, iclass 6, count 0 2006.257.10:38:22.90#ibcon#about to write, iclass 6, count 0 2006.257.10:38:22.90#ibcon#wrote, iclass 6, count 0 2006.257.10:38:22.90#ibcon#about to read 3, iclass 6, count 0 2006.257.10:38:22.92#ibcon#read 3, iclass 6, count 0 2006.257.10:38:22.92#ibcon#about to read 4, iclass 6, count 0 2006.257.10:38:22.92#ibcon#read 4, iclass 6, count 0 2006.257.10:38:22.92#ibcon#about to read 5, iclass 6, count 0 2006.257.10:38:22.92#ibcon#read 5, iclass 6, count 0 2006.257.10:38:22.92#ibcon#about to read 6, iclass 6, count 0 2006.257.10:38:22.92#ibcon#read 6, iclass 6, count 0 2006.257.10:38:22.92#ibcon#end of sib2, iclass 6, count 0 2006.257.10:38:22.92#ibcon#*mode == 0, iclass 6, count 0 2006.257.10:38:22.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.10:38:22.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:38:22.92#ibcon#*before write, iclass 6, count 0 2006.257.10:38:22.92#ibcon#enter sib2, iclass 6, count 0 2006.257.10:38:22.92#ibcon#flushed, iclass 6, count 0 2006.257.10:38:22.92#ibcon#about to write, iclass 6, count 0 2006.257.10:38:22.92#ibcon#wrote, iclass 6, count 0 2006.257.10:38:22.92#ibcon#about to read 3, iclass 6, count 0 2006.257.10:38:22.96#ibcon#read 3, iclass 6, count 0 2006.257.10:38:22.96#ibcon#about to read 4, iclass 6, count 0 2006.257.10:38:22.96#ibcon#read 4, iclass 6, count 0 2006.257.10:38:22.96#ibcon#about to read 5, iclass 6, count 0 2006.257.10:38:22.96#ibcon#read 5, iclass 6, count 0 2006.257.10:38:22.96#ibcon#about to read 6, iclass 6, count 0 2006.257.10:38:22.96#ibcon#read 6, iclass 6, count 0 2006.257.10:38:22.96#ibcon#end of sib2, iclass 6, count 0 2006.257.10:38:22.96#ibcon#*after write, iclass 6, count 0 2006.257.10:38:22.96#ibcon#*before return 0, iclass 6, count 0 2006.257.10:38:22.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:22.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:22.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.10:38:22.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.10:38:22.96$vck44/va=6,4 2006.257.10:38:22.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.10:38:22.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.10:38:22.96#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:22.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:23.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:23.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:23.02#ibcon#enter wrdev, iclass 10, count 2 2006.257.10:38:23.02#ibcon#first serial, iclass 10, count 2 2006.257.10:38:23.02#ibcon#enter sib2, iclass 10, count 2 2006.257.10:38:23.02#ibcon#flushed, iclass 10, count 2 2006.257.10:38:23.02#ibcon#about to write, iclass 10, count 2 2006.257.10:38:23.02#ibcon#wrote, iclass 10, count 2 2006.257.10:38:23.02#ibcon#about to read 3, iclass 10, count 2 2006.257.10:38:23.04#ibcon#read 3, iclass 10, count 2 2006.257.10:38:23.04#ibcon#about to read 4, iclass 10, count 2 2006.257.10:38:23.04#ibcon#read 4, iclass 10, count 2 2006.257.10:38:23.04#ibcon#about to read 5, iclass 10, count 2 2006.257.10:38:23.04#ibcon#read 5, iclass 10, count 2 2006.257.10:38:23.04#ibcon#about to read 6, iclass 10, count 2 2006.257.10:38:23.04#ibcon#read 6, iclass 10, count 2 2006.257.10:38:23.04#ibcon#end of sib2, iclass 10, count 2 2006.257.10:38:23.04#ibcon#*mode == 0, iclass 10, count 2 2006.257.10:38:23.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.10:38:23.04#ibcon#[25=AT06-04\r\n] 2006.257.10:38:23.04#ibcon#*before write, iclass 10, count 2 2006.257.10:38:23.04#ibcon#enter sib2, iclass 10, count 2 2006.257.10:38:23.04#ibcon#flushed, iclass 10, count 2 2006.257.10:38:23.04#ibcon#about to write, iclass 10, count 2 2006.257.10:38:23.04#ibcon#wrote, iclass 10, count 2 2006.257.10:38:23.04#ibcon#about to read 3, iclass 10, count 2 2006.257.10:38:23.07#ibcon#read 3, iclass 10, count 2 2006.257.10:38:23.07#ibcon#about to read 4, iclass 10, count 2 2006.257.10:38:23.07#ibcon#read 4, iclass 10, count 2 2006.257.10:38:23.07#ibcon#about to read 5, iclass 10, count 2 2006.257.10:38:23.07#ibcon#read 5, iclass 10, count 2 2006.257.10:38:23.07#ibcon#about to read 6, iclass 10, count 2 2006.257.10:38:23.07#ibcon#read 6, iclass 10, count 2 2006.257.10:38:23.07#ibcon#end of sib2, iclass 10, count 2 2006.257.10:38:23.07#ibcon#*after write, iclass 10, count 2 2006.257.10:38:23.07#ibcon#*before return 0, iclass 10, count 2 2006.257.10:38:23.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:23.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:23.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.10:38:23.07#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:23.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:23.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:23.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:23.19#ibcon#enter wrdev, iclass 10, count 0 2006.257.10:38:23.19#ibcon#first serial, iclass 10, count 0 2006.257.10:38:23.19#ibcon#enter sib2, iclass 10, count 0 2006.257.10:38:23.19#ibcon#flushed, iclass 10, count 0 2006.257.10:38:23.19#ibcon#about to write, iclass 10, count 0 2006.257.10:38:23.19#ibcon#wrote, iclass 10, count 0 2006.257.10:38:23.19#ibcon#about to read 3, iclass 10, count 0 2006.257.10:38:23.21#ibcon#read 3, iclass 10, count 0 2006.257.10:38:23.21#ibcon#about to read 4, iclass 10, count 0 2006.257.10:38:23.21#ibcon#read 4, iclass 10, count 0 2006.257.10:38:23.21#ibcon#about to read 5, iclass 10, count 0 2006.257.10:38:23.21#ibcon#read 5, iclass 10, count 0 2006.257.10:38:23.21#ibcon#about to read 6, iclass 10, count 0 2006.257.10:38:23.21#ibcon#read 6, iclass 10, count 0 2006.257.10:38:23.21#ibcon#end of sib2, iclass 10, count 0 2006.257.10:38:23.21#ibcon#*mode == 0, iclass 10, count 0 2006.257.10:38:23.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.10:38:23.21#ibcon#[25=USB\r\n] 2006.257.10:38:23.21#ibcon#*before write, iclass 10, count 0 2006.257.10:38:23.21#ibcon#enter sib2, iclass 10, count 0 2006.257.10:38:23.21#ibcon#flushed, iclass 10, count 0 2006.257.10:38:23.21#ibcon#about to write, iclass 10, count 0 2006.257.10:38:23.21#ibcon#wrote, iclass 10, count 0 2006.257.10:38:23.21#ibcon#about to read 3, iclass 10, count 0 2006.257.10:38:23.24#ibcon#read 3, iclass 10, count 0 2006.257.10:38:23.24#ibcon#about to read 4, iclass 10, count 0 2006.257.10:38:23.24#ibcon#read 4, iclass 10, count 0 2006.257.10:38:23.24#ibcon#about to read 5, iclass 10, count 0 2006.257.10:38:23.24#ibcon#read 5, iclass 10, count 0 2006.257.10:38:23.24#ibcon#about to read 6, iclass 10, count 0 2006.257.10:38:23.24#ibcon#read 6, iclass 10, count 0 2006.257.10:38:23.24#ibcon#end of sib2, iclass 10, count 0 2006.257.10:38:23.24#ibcon#*after write, iclass 10, count 0 2006.257.10:38:23.24#ibcon#*before return 0, iclass 10, count 0 2006.257.10:38:23.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:23.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:23.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.10:38:23.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.10:38:23.24$vck44/valo=7,864.99 2006.257.10:38:23.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.10:38:23.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.10:38:23.24#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:23.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:23.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:23.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:23.24#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:38:23.24#ibcon#first serial, iclass 12, count 0 2006.257.10:38:23.24#ibcon#enter sib2, iclass 12, count 0 2006.257.10:38:23.24#ibcon#flushed, iclass 12, count 0 2006.257.10:38:23.24#ibcon#about to write, iclass 12, count 0 2006.257.10:38:23.24#ibcon#wrote, iclass 12, count 0 2006.257.10:38:23.24#ibcon#about to read 3, iclass 12, count 0 2006.257.10:38:23.26#ibcon#read 3, iclass 12, count 0 2006.257.10:38:23.26#ibcon#about to read 4, iclass 12, count 0 2006.257.10:38:23.26#ibcon#read 4, iclass 12, count 0 2006.257.10:38:23.26#ibcon#about to read 5, iclass 12, count 0 2006.257.10:38:23.26#ibcon#read 5, iclass 12, count 0 2006.257.10:38:23.26#ibcon#about to read 6, iclass 12, count 0 2006.257.10:38:23.26#ibcon#read 6, iclass 12, count 0 2006.257.10:38:23.26#ibcon#end of sib2, iclass 12, count 0 2006.257.10:38:23.26#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:38:23.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:38:23.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:38:23.26#ibcon#*before write, iclass 12, count 0 2006.257.10:38:23.26#ibcon#enter sib2, iclass 12, count 0 2006.257.10:38:23.26#ibcon#flushed, iclass 12, count 0 2006.257.10:38:23.26#ibcon#about to write, iclass 12, count 0 2006.257.10:38:23.26#ibcon#wrote, iclass 12, count 0 2006.257.10:38:23.26#ibcon#about to read 3, iclass 12, count 0 2006.257.10:38:23.30#ibcon#read 3, iclass 12, count 0 2006.257.10:38:23.30#ibcon#about to read 4, iclass 12, count 0 2006.257.10:38:23.30#ibcon#read 4, iclass 12, count 0 2006.257.10:38:23.30#ibcon#about to read 5, iclass 12, count 0 2006.257.10:38:23.30#ibcon#read 5, iclass 12, count 0 2006.257.10:38:23.30#ibcon#about to read 6, iclass 12, count 0 2006.257.10:38:23.30#ibcon#read 6, iclass 12, count 0 2006.257.10:38:23.30#ibcon#end of sib2, iclass 12, count 0 2006.257.10:38:23.30#ibcon#*after write, iclass 12, count 0 2006.257.10:38:23.30#ibcon#*before return 0, iclass 12, count 0 2006.257.10:38:23.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:23.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:23.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:38:23.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:38:23.30$vck44/va=7,4 2006.257.10:38:23.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.10:38:23.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.10:38:23.30#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:23.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:23.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:23.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:23.36#ibcon#enter wrdev, iclass 14, count 2 2006.257.10:38:23.36#ibcon#first serial, iclass 14, count 2 2006.257.10:38:23.36#ibcon#enter sib2, iclass 14, count 2 2006.257.10:38:23.36#ibcon#flushed, iclass 14, count 2 2006.257.10:38:23.36#ibcon#about to write, iclass 14, count 2 2006.257.10:38:23.36#ibcon#wrote, iclass 14, count 2 2006.257.10:38:23.36#ibcon#about to read 3, iclass 14, count 2 2006.257.10:38:23.38#ibcon#read 3, iclass 14, count 2 2006.257.10:38:23.38#ibcon#about to read 4, iclass 14, count 2 2006.257.10:38:23.38#ibcon#read 4, iclass 14, count 2 2006.257.10:38:23.38#ibcon#about to read 5, iclass 14, count 2 2006.257.10:38:23.38#ibcon#read 5, iclass 14, count 2 2006.257.10:38:23.38#ibcon#about to read 6, iclass 14, count 2 2006.257.10:38:23.38#ibcon#read 6, iclass 14, count 2 2006.257.10:38:23.38#ibcon#end of sib2, iclass 14, count 2 2006.257.10:38:23.38#ibcon#*mode == 0, iclass 14, count 2 2006.257.10:38:23.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.10:38:23.38#ibcon#[25=AT07-04\r\n] 2006.257.10:38:23.38#ibcon#*before write, iclass 14, count 2 2006.257.10:38:23.38#ibcon#enter sib2, iclass 14, count 2 2006.257.10:38:23.38#ibcon#flushed, iclass 14, count 2 2006.257.10:38:23.38#ibcon#about to write, iclass 14, count 2 2006.257.10:38:23.38#ibcon#wrote, iclass 14, count 2 2006.257.10:38:23.38#ibcon#about to read 3, iclass 14, count 2 2006.257.10:38:23.41#ibcon#read 3, iclass 14, count 2 2006.257.10:38:23.41#ibcon#about to read 4, iclass 14, count 2 2006.257.10:38:23.41#ibcon#read 4, iclass 14, count 2 2006.257.10:38:23.41#ibcon#about to read 5, iclass 14, count 2 2006.257.10:38:23.41#ibcon#read 5, iclass 14, count 2 2006.257.10:38:23.41#ibcon#about to read 6, iclass 14, count 2 2006.257.10:38:23.41#ibcon#read 6, iclass 14, count 2 2006.257.10:38:23.41#ibcon#end of sib2, iclass 14, count 2 2006.257.10:38:23.41#ibcon#*after write, iclass 14, count 2 2006.257.10:38:23.41#ibcon#*before return 0, iclass 14, count 2 2006.257.10:38:23.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:23.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:23.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.10:38:23.41#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:23.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:23.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:23.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:23.53#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:38:23.53#ibcon#first serial, iclass 14, count 0 2006.257.10:38:23.53#ibcon#enter sib2, iclass 14, count 0 2006.257.10:38:23.53#ibcon#flushed, iclass 14, count 0 2006.257.10:38:23.53#ibcon#about to write, iclass 14, count 0 2006.257.10:38:23.53#ibcon#wrote, iclass 14, count 0 2006.257.10:38:23.53#ibcon#about to read 3, iclass 14, count 0 2006.257.10:38:23.55#ibcon#read 3, iclass 14, count 0 2006.257.10:38:23.55#ibcon#about to read 4, iclass 14, count 0 2006.257.10:38:23.55#ibcon#read 4, iclass 14, count 0 2006.257.10:38:23.55#ibcon#about to read 5, iclass 14, count 0 2006.257.10:38:23.55#ibcon#read 5, iclass 14, count 0 2006.257.10:38:23.55#ibcon#about to read 6, iclass 14, count 0 2006.257.10:38:23.55#ibcon#read 6, iclass 14, count 0 2006.257.10:38:23.55#ibcon#end of sib2, iclass 14, count 0 2006.257.10:38:23.55#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:38:23.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:38:23.55#ibcon#[25=USB\r\n] 2006.257.10:38:23.55#ibcon#*before write, iclass 14, count 0 2006.257.10:38:23.55#ibcon#enter sib2, iclass 14, count 0 2006.257.10:38:23.55#ibcon#flushed, iclass 14, count 0 2006.257.10:38:23.55#ibcon#about to write, iclass 14, count 0 2006.257.10:38:23.55#ibcon#wrote, iclass 14, count 0 2006.257.10:38:23.55#ibcon#about to read 3, iclass 14, count 0 2006.257.10:38:23.58#ibcon#read 3, iclass 14, count 0 2006.257.10:38:23.58#ibcon#about to read 4, iclass 14, count 0 2006.257.10:38:23.58#ibcon#read 4, iclass 14, count 0 2006.257.10:38:23.58#ibcon#about to read 5, iclass 14, count 0 2006.257.10:38:23.58#ibcon#read 5, iclass 14, count 0 2006.257.10:38:23.58#ibcon#about to read 6, iclass 14, count 0 2006.257.10:38:23.58#ibcon#read 6, iclass 14, count 0 2006.257.10:38:23.58#ibcon#end of sib2, iclass 14, count 0 2006.257.10:38:23.58#ibcon#*after write, iclass 14, count 0 2006.257.10:38:23.58#ibcon#*before return 0, iclass 14, count 0 2006.257.10:38:23.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:23.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:23.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:38:23.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:38:23.58$vck44/valo=8,884.99 2006.257.10:38:23.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.10:38:23.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.10:38:23.58#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:23.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:23.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:23.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:23.58#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:38:23.58#ibcon#first serial, iclass 16, count 0 2006.257.10:38:23.58#ibcon#enter sib2, iclass 16, count 0 2006.257.10:38:23.58#ibcon#flushed, iclass 16, count 0 2006.257.10:38:23.58#ibcon#about to write, iclass 16, count 0 2006.257.10:38:23.58#ibcon#wrote, iclass 16, count 0 2006.257.10:38:23.58#ibcon#about to read 3, iclass 16, count 0 2006.257.10:38:23.60#ibcon#read 3, iclass 16, count 0 2006.257.10:38:23.60#ibcon#about to read 4, iclass 16, count 0 2006.257.10:38:23.60#ibcon#read 4, iclass 16, count 0 2006.257.10:38:23.60#ibcon#about to read 5, iclass 16, count 0 2006.257.10:38:23.60#ibcon#read 5, iclass 16, count 0 2006.257.10:38:23.60#ibcon#about to read 6, iclass 16, count 0 2006.257.10:38:23.60#ibcon#read 6, iclass 16, count 0 2006.257.10:38:23.60#ibcon#end of sib2, iclass 16, count 0 2006.257.10:38:23.60#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:38:23.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:38:23.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:38:23.60#ibcon#*before write, iclass 16, count 0 2006.257.10:38:23.60#ibcon#enter sib2, iclass 16, count 0 2006.257.10:38:23.60#ibcon#flushed, iclass 16, count 0 2006.257.10:38:23.60#ibcon#about to write, iclass 16, count 0 2006.257.10:38:23.60#ibcon#wrote, iclass 16, count 0 2006.257.10:38:23.60#ibcon#about to read 3, iclass 16, count 0 2006.257.10:38:23.64#ibcon#read 3, iclass 16, count 0 2006.257.10:38:23.64#ibcon#about to read 4, iclass 16, count 0 2006.257.10:38:23.64#ibcon#read 4, iclass 16, count 0 2006.257.10:38:23.64#ibcon#about to read 5, iclass 16, count 0 2006.257.10:38:23.64#ibcon#read 5, iclass 16, count 0 2006.257.10:38:23.64#ibcon#about to read 6, iclass 16, count 0 2006.257.10:38:23.64#ibcon#read 6, iclass 16, count 0 2006.257.10:38:23.64#ibcon#end of sib2, iclass 16, count 0 2006.257.10:38:23.64#ibcon#*after write, iclass 16, count 0 2006.257.10:38:23.64#ibcon#*before return 0, iclass 16, count 0 2006.257.10:38:23.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:23.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:23.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:38:23.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:38:23.64$vck44/va=8,4 2006.257.10:38:23.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.10:38:23.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.10:38:23.64#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:23.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:23.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:23.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:23.70#ibcon#enter wrdev, iclass 18, count 2 2006.257.10:38:23.70#ibcon#first serial, iclass 18, count 2 2006.257.10:38:23.70#ibcon#enter sib2, iclass 18, count 2 2006.257.10:38:23.70#ibcon#flushed, iclass 18, count 2 2006.257.10:38:23.70#ibcon#about to write, iclass 18, count 2 2006.257.10:38:23.70#ibcon#wrote, iclass 18, count 2 2006.257.10:38:23.70#ibcon#about to read 3, iclass 18, count 2 2006.257.10:38:23.72#ibcon#read 3, iclass 18, count 2 2006.257.10:38:23.72#ibcon#about to read 4, iclass 18, count 2 2006.257.10:38:23.72#ibcon#read 4, iclass 18, count 2 2006.257.10:38:23.72#ibcon#about to read 5, iclass 18, count 2 2006.257.10:38:23.72#ibcon#read 5, iclass 18, count 2 2006.257.10:38:23.72#ibcon#about to read 6, iclass 18, count 2 2006.257.10:38:23.72#ibcon#read 6, iclass 18, count 2 2006.257.10:38:23.72#ibcon#end of sib2, iclass 18, count 2 2006.257.10:38:23.72#ibcon#*mode == 0, iclass 18, count 2 2006.257.10:38:23.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.10:38:23.72#ibcon#[25=AT08-04\r\n] 2006.257.10:38:23.72#ibcon#*before write, iclass 18, count 2 2006.257.10:38:23.72#ibcon#enter sib2, iclass 18, count 2 2006.257.10:38:23.72#ibcon#flushed, iclass 18, count 2 2006.257.10:38:23.72#ibcon#about to write, iclass 18, count 2 2006.257.10:38:23.72#ibcon#wrote, iclass 18, count 2 2006.257.10:38:23.72#ibcon#about to read 3, iclass 18, count 2 2006.257.10:38:23.75#ibcon#read 3, iclass 18, count 2 2006.257.10:38:23.75#ibcon#about to read 4, iclass 18, count 2 2006.257.10:38:23.75#ibcon#read 4, iclass 18, count 2 2006.257.10:38:23.75#ibcon#about to read 5, iclass 18, count 2 2006.257.10:38:23.75#ibcon#read 5, iclass 18, count 2 2006.257.10:38:23.75#ibcon#about to read 6, iclass 18, count 2 2006.257.10:38:23.75#ibcon#read 6, iclass 18, count 2 2006.257.10:38:23.75#ibcon#end of sib2, iclass 18, count 2 2006.257.10:38:23.75#ibcon#*after write, iclass 18, count 2 2006.257.10:38:23.75#ibcon#*before return 0, iclass 18, count 2 2006.257.10:38:23.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:23.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:23.75#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.10:38:23.75#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:23.75#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:23.87#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:23.87#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:23.87#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:38:23.87#ibcon#first serial, iclass 18, count 0 2006.257.10:38:23.87#ibcon#enter sib2, iclass 18, count 0 2006.257.10:38:23.87#ibcon#flushed, iclass 18, count 0 2006.257.10:38:23.87#ibcon#about to write, iclass 18, count 0 2006.257.10:38:23.87#ibcon#wrote, iclass 18, count 0 2006.257.10:38:23.87#ibcon#about to read 3, iclass 18, count 0 2006.257.10:38:23.89#ibcon#read 3, iclass 18, count 0 2006.257.10:38:23.89#ibcon#about to read 4, iclass 18, count 0 2006.257.10:38:23.89#ibcon#read 4, iclass 18, count 0 2006.257.10:38:23.89#ibcon#about to read 5, iclass 18, count 0 2006.257.10:38:23.89#ibcon#read 5, iclass 18, count 0 2006.257.10:38:23.89#ibcon#about to read 6, iclass 18, count 0 2006.257.10:38:23.89#ibcon#read 6, iclass 18, count 0 2006.257.10:38:23.89#ibcon#end of sib2, iclass 18, count 0 2006.257.10:38:23.89#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:38:23.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:38:23.89#ibcon#[25=USB\r\n] 2006.257.10:38:23.89#ibcon#*before write, iclass 18, count 0 2006.257.10:38:23.89#ibcon#enter sib2, iclass 18, count 0 2006.257.10:38:23.89#ibcon#flushed, iclass 18, count 0 2006.257.10:38:23.89#ibcon#about to write, iclass 18, count 0 2006.257.10:38:23.89#ibcon#wrote, iclass 18, count 0 2006.257.10:38:23.89#ibcon#about to read 3, iclass 18, count 0 2006.257.10:38:23.92#ibcon#read 3, iclass 18, count 0 2006.257.10:38:23.92#ibcon#about to read 4, iclass 18, count 0 2006.257.10:38:23.92#ibcon#read 4, iclass 18, count 0 2006.257.10:38:23.92#ibcon#about to read 5, iclass 18, count 0 2006.257.10:38:23.92#ibcon#read 5, iclass 18, count 0 2006.257.10:38:23.92#ibcon#about to read 6, iclass 18, count 0 2006.257.10:38:23.92#ibcon#read 6, iclass 18, count 0 2006.257.10:38:23.92#ibcon#end of sib2, iclass 18, count 0 2006.257.10:38:23.92#ibcon#*after write, iclass 18, count 0 2006.257.10:38:23.92#ibcon#*before return 0, iclass 18, count 0 2006.257.10:38:23.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:23.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:23.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:38:23.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:38:23.92$vck44/vblo=1,629.99 2006.257.10:38:23.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.10:38:23.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.10:38:23.92#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:23.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:23.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:23.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:23.92#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:38:23.92#ibcon#first serial, iclass 20, count 0 2006.257.10:38:23.92#ibcon#enter sib2, iclass 20, count 0 2006.257.10:38:23.92#ibcon#flushed, iclass 20, count 0 2006.257.10:38:23.92#ibcon#about to write, iclass 20, count 0 2006.257.10:38:23.92#ibcon#wrote, iclass 20, count 0 2006.257.10:38:23.92#ibcon#about to read 3, iclass 20, count 0 2006.257.10:38:23.94#ibcon#read 3, iclass 20, count 0 2006.257.10:38:23.94#ibcon#about to read 4, iclass 20, count 0 2006.257.10:38:23.94#ibcon#read 4, iclass 20, count 0 2006.257.10:38:23.94#ibcon#about to read 5, iclass 20, count 0 2006.257.10:38:23.94#ibcon#read 5, iclass 20, count 0 2006.257.10:38:23.94#ibcon#about to read 6, iclass 20, count 0 2006.257.10:38:23.94#ibcon#read 6, iclass 20, count 0 2006.257.10:38:23.94#ibcon#end of sib2, iclass 20, count 0 2006.257.10:38:23.94#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:38:23.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:38:23.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:38:23.94#ibcon#*before write, iclass 20, count 0 2006.257.10:38:23.94#ibcon#enter sib2, iclass 20, count 0 2006.257.10:38:23.94#ibcon#flushed, iclass 20, count 0 2006.257.10:38:23.94#ibcon#about to write, iclass 20, count 0 2006.257.10:38:23.94#ibcon#wrote, iclass 20, count 0 2006.257.10:38:23.94#ibcon#about to read 3, iclass 20, count 0 2006.257.10:38:23.98#ibcon#read 3, iclass 20, count 0 2006.257.10:38:23.98#ibcon#about to read 4, iclass 20, count 0 2006.257.10:38:23.98#ibcon#read 4, iclass 20, count 0 2006.257.10:38:23.98#ibcon#about to read 5, iclass 20, count 0 2006.257.10:38:23.98#ibcon#read 5, iclass 20, count 0 2006.257.10:38:23.98#ibcon#about to read 6, iclass 20, count 0 2006.257.10:38:23.98#ibcon#read 6, iclass 20, count 0 2006.257.10:38:23.98#ibcon#end of sib2, iclass 20, count 0 2006.257.10:38:23.98#ibcon#*after write, iclass 20, count 0 2006.257.10:38:23.98#ibcon#*before return 0, iclass 20, count 0 2006.257.10:38:23.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:23.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:23.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:38:23.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:38:23.98$vck44/vb=1,4 2006.257.10:38:23.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.10:38:23.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.10:38:23.98#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:23.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:38:23.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:38:23.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:38:23.98#ibcon#enter wrdev, iclass 22, count 2 2006.257.10:38:23.98#ibcon#first serial, iclass 22, count 2 2006.257.10:38:23.98#ibcon#enter sib2, iclass 22, count 2 2006.257.10:38:23.98#ibcon#flushed, iclass 22, count 2 2006.257.10:38:23.98#ibcon#about to write, iclass 22, count 2 2006.257.10:38:23.98#ibcon#wrote, iclass 22, count 2 2006.257.10:38:23.98#ibcon#about to read 3, iclass 22, count 2 2006.257.10:38:24.00#ibcon#read 3, iclass 22, count 2 2006.257.10:38:24.00#ibcon#about to read 4, iclass 22, count 2 2006.257.10:38:24.00#ibcon#read 4, iclass 22, count 2 2006.257.10:38:24.00#ibcon#about to read 5, iclass 22, count 2 2006.257.10:38:24.00#ibcon#read 5, iclass 22, count 2 2006.257.10:38:24.00#ibcon#about to read 6, iclass 22, count 2 2006.257.10:38:24.00#ibcon#read 6, iclass 22, count 2 2006.257.10:38:24.00#ibcon#end of sib2, iclass 22, count 2 2006.257.10:38:24.00#ibcon#*mode == 0, iclass 22, count 2 2006.257.10:38:24.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.10:38:24.00#ibcon#[27=AT01-04\r\n] 2006.257.10:38:24.00#ibcon#*before write, iclass 22, count 2 2006.257.10:38:24.00#ibcon#enter sib2, iclass 22, count 2 2006.257.10:38:24.00#ibcon#flushed, iclass 22, count 2 2006.257.10:38:24.00#ibcon#about to write, iclass 22, count 2 2006.257.10:38:24.00#ibcon#wrote, iclass 22, count 2 2006.257.10:38:24.00#ibcon#about to read 3, iclass 22, count 2 2006.257.10:38:24.03#ibcon#read 3, iclass 22, count 2 2006.257.10:38:24.03#ibcon#about to read 4, iclass 22, count 2 2006.257.10:38:24.03#ibcon#read 4, iclass 22, count 2 2006.257.10:38:24.03#ibcon#about to read 5, iclass 22, count 2 2006.257.10:38:24.03#ibcon#read 5, iclass 22, count 2 2006.257.10:38:24.03#ibcon#about to read 6, iclass 22, count 2 2006.257.10:38:24.03#ibcon#read 6, iclass 22, count 2 2006.257.10:38:24.03#ibcon#end of sib2, iclass 22, count 2 2006.257.10:38:24.03#ibcon#*after write, iclass 22, count 2 2006.257.10:38:24.03#ibcon#*before return 0, iclass 22, count 2 2006.257.10:38:24.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:38:24.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.10:38:24.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.10:38:24.03#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:24.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:38:24.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:38:24.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:38:24.15#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:38:24.15#ibcon#first serial, iclass 22, count 0 2006.257.10:38:24.15#ibcon#enter sib2, iclass 22, count 0 2006.257.10:38:24.15#ibcon#flushed, iclass 22, count 0 2006.257.10:38:24.15#ibcon#about to write, iclass 22, count 0 2006.257.10:38:24.15#ibcon#wrote, iclass 22, count 0 2006.257.10:38:24.15#ibcon#about to read 3, iclass 22, count 0 2006.257.10:38:24.17#ibcon#read 3, iclass 22, count 0 2006.257.10:38:24.17#ibcon#about to read 4, iclass 22, count 0 2006.257.10:38:24.17#ibcon#read 4, iclass 22, count 0 2006.257.10:38:24.17#ibcon#about to read 5, iclass 22, count 0 2006.257.10:38:24.17#ibcon#read 5, iclass 22, count 0 2006.257.10:38:24.17#ibcon#about to read 6, iclass 22, count 0 2006.257.10:38:24.17#ibcon#read 6, iclass 22, count 0 2006.257.10:38:24.17#ibcon#end of sib2, iclass 22, count 0 2006.257.10:38:24.17#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:38:24.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:38:24.17#ibcon#[27=USB\r\n] 2006.257.10:38:24.17#ibcon#*before write, iclass 22, count 0 2006.257.10:38:24.17#ibcon#enter sib2, iclass 22, count 0 2006.257.10:38:24.17#ibcon#flushed, iclass 22, count 0 2006.257.10:38:24.17#ibcon#about to write, iclass 22, count 0 2006.257.10:38:24.17#ibcon#wrote, iclass 22, count 0 2006.257.10:38:24.17#ibcon#about to read 3, iclass 22, count 0 2006.257.10:38:24.20#ibcon#read 3, iclass 22, count 0 2006.257.10:38:24.20#ibcon#about to read 4, iclass 22, count 0 2006.257.10:38:24.20#ibcon#read 4, iclass 22, count 0 2006.257.10:38:24.20#ibcon#about to read 5, iclass 22, count 0 2006.257.10:38:24.20#ibcon#read 5, iclass 22, count 0 2006.257.10:38:24.20#ibcon#about to read 6, iclass 22, count 0 2006.257.10:38:24.20#ibcon#read 6, iclass 22, count 0 2006.257.10:38:24.20#ibcon#end of sib2, iclass 22, count 0 2006.257.10:38:24.20#ibcon#*after write, iclass 22, count 0 2006.257.10:38:24.20#ibcon#*before return 0, iclass 22, count 0 2006.257.10:38:24.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:38:24.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.10:38:24.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:38:24.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:38:24.20$vck44/vblo=2,634.99 2006.257.10:38:24.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.10:38:24.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.10:38:24.20#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:24.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:24.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:24.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:24.20#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:38:24.20#ibcon#first serial, iclass 24, count 0 2006.257.10:38:24.20#ibcon#enter sib2, iclass 24, count 0 2006.257.10:38:24.20#ibcon#flushed, iclass 24, count 0 2006.257.10:38:24.20#ibcon#about to write, iclass 24, count 0 2006.257.10:38:24.20#ibcon#wrote, iclass 24, count 0 2006.257.10:38:24.20#ibcon#about to read 3, iclass 24, count 0 2006.257.10:38:24.22#ibcon#read 3, iclass 24, count 0 2006.257.10:38:24.22#ibcon#about to read 4, iclass 24, count 0 2006.257.10:38:24.22#ibcon#read 4, iclass 24, count 0 2006.257.10:38:24.22#ibcon#about to read 5, iclass 24, count 0 2006.257.10:38:24.22#ibcon#read 5, iclass 24, count 0 2006.257.10:38:24.22#ibcon#about to read 6, iclass 24, count 0 2006.257.10:38:24.22#ibcon#read 6, iclass 24, count 0 2006.257.10:38:24.22#ibcon#end of sib2, iclass 24, count 0 2006.257.10:38:24.22#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:38:24.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:38:24.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:38:24.22#ibcon#*before write, iclass 24, count 0 2006.257.10:38:24.22#ibcon#enter sib2, iclass 24, count 0 2006.257.10:38:24.22#ibcon#flushed, iclass 24, count 0 2006.257.10:38:24.22#ibcon#about to write, iclass 24, count 0 2006.257.10:38:24.22#ibcon#wrote, iclass 24, count 0 2006.257.10:38:24.22#ibcon#about to read 3, iclass 24, count 0 2006.257.10:38:24.26#ibcon#read 3, iclass 24, count 0 2006.257.10:38:24.26#ibcon#about to read 4, iclass 24, count 0 2006.257.10:38:24.26#ibcon#read 4, iclass 24, count 0 2006.257.10:38:24.26#ibcon#about to read 5, iclass 24, count 0 2006.257.10:38:24.26#ibcon#read 5, iclass 24, count 0 2006.257.10:38:24.26#ibcon#about to read 6, iclass 24, count 0 2006.257.10:38:24.26#ibcon#read 6, iclass 24, count 0 2006.257.10:38:24.26#ibcon#end of sib2, iclass 24, count 0 2006.257.10:38:24.26#ibcon#*after write, iclass 24, count 0 2006.257.10:38:24.26#ibcon#*before return 0, iclass 24, count 0 2006.257.10:38:24.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:24.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.10:38:24.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:38:24.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:38:24.26$vck44/vb=2,5 2006.257.10:38:24.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.10:38:24.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.10:38:24.26#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:24.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:24.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:24.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:24.32#ibcon#enter wrdev, iclass 26, count 2 2006.257.10:38:24.32#ibcon#first serial, iclass 26, count 2 2006.257.10:38:24.32#ibcon#enter sib2, iclass 26, count 2 2006.257.10:38:24.32#ibcon#flushed, iclass 26, count 2 2006.257.10:38:24.32#ibcon#about to write, iclass 26, count 2 2006.257.10:38:24.32#ibcon#wrote, iclass 26, count 2 2006.257.10:38:24.32#ibcon#about to read 3, iclass 26, count 2 2006.257.10:38:24.34#ibcon#read 3, iclass 26, count 2 2006.257.10:38:24.34#ibcon#about to read 4, iclass 26, count 2 2006.257.10:38:24.34#ibcon#read 4, iclass 26, count 2 2006.257.10:38:24.34#ibcon#about to read 5, iclass 26, count 2 2006.257.10:38:24.34#ibcon#read 5, iclass 26, count 2 2006.257.10:38:24.34#ibcon#about to read 6, iclass 26, count 2 2006.257.10:38:24.34#ibcon#read 6, iclass 26, count 2 2006.257.10:38:24.34#ibcon#end of sib2, iclass 26, count 2 2006.257.10:38:24.34#ibcon#*mode == 0, iclass 26, count 2 2006.257.10:38:24.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.10:38:24.34#ibcon#[27=AT02-05\r\n] 2006.257.10:38:24.34#ibcon#*before write, iclass 26, count 2 2006.257.10:38:24.34#ibcon#enter sib2, iclass 26, count 2 2006.257.10:38:24.34#ibcon#flushed, iclass 26, count 2 2006.257.10:38:24.34#ibcon#about to write, iclass 26, count 2 2006.257.10:38:24.34#ibcon#wrote, iclass 26, count 2 2006.257.10:38:24.34#ibcon#about to read 3, iclass 26, count 2 2006.257.10:38:24.37#ibcon#read 3, iclass 26, count 2 2006.257.10:38:24.37#ibcon#about to read 4, iclass 26, count 2 2006.257.10:38:24.37#ibcon#read 4, iclass 26, count 2 2006.257.10:38:24.37#ibcon#about to read 5, iclass 26, count 2 2006.257.10:38:24.37#ibcon#read 5, iclass 26, count 2 2006.257.10:38:24.37#ibcon#about to read 6, iclass 26, count 2 2006.257.10:38:24.37#ibcon#read 6, iclass 26, count 2 2006.257.10:38:24.37#ibcon#end of sib2, iclass 26, count 2 2006.257.10:38:24.37#ibcon#*after write, iclass 26, count 2 2006.257.10:38:24.37#ibcon#*before return 0, iclass 26, count 2 2006.257.10:38:24.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:24.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.10:38:24.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.10:38:24.37#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:24.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:24.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:24.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:24.49#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:38:24.49#ibcon#first serial, iclass 26, count 0 2006.257.10:38:24.49#ibcon#enter sib2, iclass 26, count 0 2006.257.10:38:24.49#ibcon#flushed, iclass 26, count 0 2006.257.10:38:24.49#ibcon#about to write, iclass 26, count 0 2006.257.10:38:24.49#ibcon#wrote, iclass 26, count 0 2006.257.10:38:24.49#ibcon#about to read 3, iclass 26, count 0 2006.257.10:38:24.51#ibcon#read 3, iclass 26, count 0 2006.257.10:38:24.51#ibcon#about to read 4, iclass 26, count 0 2006.257.10:38:24.51#ibcon#read 4, iclass 26, count 0 2006.257.10:38:24.51#ibcon#about to read 5, iclass 26, count 0 2006.257.10:38:24.51#ibcon#read 5, iclass 26, count 0 2006.257.10:38:24.51#ibcon#about to read 6, iclass 26, count 0 2006.257.10:38:24.51#ibcon#read 6, iclass 26, count 0 2006.257.10:38:24.51#ibcon#end of sib2, iclass 26, count 0 2006.257.10:38:24.51#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:38:24.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:38:24.51#ibcon#[27=USB\r\n] 2006.257.10:38:24.51#ibcon#*before write, iclass 26, count 0 2006.257.10:38:24.51#ibcon#enter sib2, iclass 26, count 0 2006.257.10:38:24.51#ibcon#flushed, iclass 26, count 0 2006.257.10:38:24.51#ibcon#about to write, iclass 26, count 0 2006.257.10:38:24.51#ibcon#wrote, iclass 26, count 0 2006.257.10:38:24.51#ibcon#about to read 3, iclass 26, count 0 2006.257.10:38:24.54#ibcon#read 3, iclass 26, count 0 2006.257.10:38:24.54#ibcon#about to read 4, iclass 26, count 0 2006.257.10:38:24.54#ibcon#read 4, iclass 26, count 0 2006.257.10:38:24.54#ibcon#about to read 5, iclass 26, count 0 2006.257.10:38:24.54#ibcon#read 5, iclass 26, count 0 2006.257.10:38:24.54#ibcon#about to read 6, iclass 26, count 0 2006.257.10:38:24.54#ibcon#read 6, iclass 26, count 0 2006.257.10:38:24.54#ibcon#end of sib2, iclass 26, count 0 2006.257.10:38:24.54#ibcon#*after write, iclass 26, count 0 2006.257.10:38:24.54#ibcon#*before return 0, iclass 26, count 0 2006.257.10:38:24.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:24.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.10:38:24.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:38:24.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:38:24.54$vck44/vblo=3,649.99 2006.257.10:38:24.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.10:38:24.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.10:38:24.54#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:24.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:24.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:24.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:24.54#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:38:24.54#ibcon#first serial, iclass 28, count 0 2006.257.10:38:24.54#ibcon#enter sib2, iclass 28, count 0 2006.257.10:38:24.54#ibcon#flushed, iclass 28, count 0 2006.257.10:38:24.54#ibcon#about to write, iclass 28, count 0 2006.257.10:38:24.54#ibcon#wrote, iclass 28, count 0 2006.257.10:38:24.54#ibcon#about to read 3, iclass 28, count 0 2006.257.10:38:24.56#ibcon#read 3, iclass 28, count 0 2006.257.10:38:24.56#ibcon#about to read 4, iclass 28, count 0 2006.257.10:38:24.56#ibcon#read 4, iclass 28, count 0 2006.257.10:38:24.56#ibcon#about to read 5, iclass 28, count 0 2006.257.10:38:24.56#ibcon#read 5, iclass 28, count 0 2006.257.10:38:24.56#ibcon#about to read 6, iclass 28, count 0 2006.257.10:38:24.56#ibcon#read 6, iclass 28, count 0 2006.257.10:38:24.56#ibcon#end of sib2, iclass 28, count 0 2006.257.10:38:24.56#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:38:24.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:38:24.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:38:24.56#ibcon#*before write, iclass 28, count 0 2006.257.10:38:24.56#ibcon#enter sib2, iclass 28, count 0 2006.257.10:38:24.56#ibcon#flushed, iclass 28, count 0 2006.257.10:38:24.56#ibcon#about to write, iclass 28, count 0 2006.257.10:38:24.56#ibcon#wrote, iclass 28, count 0 2006.257.10:38:24.56#ibcon#about to read 3, iclass 28, count 0 2006.257.10:38:24.60#ibcon#read 3, iclass 28, count 0 2006.257.10:38:24.60#ibcon#about to read 4, iclass 28, count 0 2006.257.10:38:24.60#ibcon#read 4, iclass 28, count 0 2006.257.10:38:24.60#ibcon#about to read 5, iclass 28, count 0 2006.257.10:38:24.60#ibcon#read 5, iclass 28, count 0 2006.257.10:38:24.60#ibcon#about to read 6, iclass 28, count 0 2006.257.10:38:24.60#ibcon#read 6, iclass 28, count 0 2006.257.10:38:24.60#ibcon#end of sib2, iclass 28, count 0 2006.257.10:38:24.60#ibcon#*after write, iclass 28, count 0 2006.257.10:38:24.60#ibcon#*before return 0, iclass 28, count 0 2006.257.10:38:24.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:24.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.10:38:24.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:38:24.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:38:24.60$vck44/vb=3,4 2006.257.10:38:24.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.10:38:24.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.10:38:24.60#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:24.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:24.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:24.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:24.66#ibcon#enter wrdev, iclass 30, count 2 2006.257.10:38:24.66#ibcon#first serial, iclass 30, count 2 2006.257.10:38:24.66#ibcon#enter sib2, iclass 30, count 2 2006.257.10:38:24.66#ibcon#flushed, iclass 30, count 2 2006.257.10:38:24.66#ibcon#about to write, iclass 30, count 2 2006.257.10:38:24.66#ibcon#wrote, iclass 30, count 2 2006.257.10:38:24.66#ibcon#about to read 3, iclass 30, count 2 2006.257.10:38:24.68#ibcon#read 3, iclass 30, count 2 2006.257.10:38:24.68#ibcon#about to read 4, iclass 30, count 2 2006.257.10:38:24.68#ibcon#read 4, iclass 30, count 2 2006.257.10:38:24.68#ibcon#about to read 5, iclass 30, count 2 2006.257.10:38:24.68#ibcon#read 5, iclass 30, count 2 2006.257.10:38:24.68#ibcon#about to read 6, iclass 30, count 2 2006.257.10:38:24.68#ibcon#read 6, iclass 30, count 2 2006.257.10:38:24.68#ibcon#end of sib2, iclass 30, count 2 2006.257.10:38:24.68#ibcon#*mode == 0, iclass 30, count 2 2006.257.10:38:24.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.10:38:24.68#ibcon#[27=AT03-04\r\n] 2006.257.10:38:24.68#ibcon#*before write, iclass 30, count 2 2006.257.10:38:24.68#ibcon#enter sib2, iclass 30, count 2 2006.257.10:38:24.68#ibcon#flushed, iclass 30, count 2 2006.257.10:38:24.68#ibcon#about to write, iclass 30, count 2 2006.257.10:38:24.68#ibcon#wrote, iclass 30, count 2 2006.257.10:38:24.68#ibcon#about to read 3, iclass 30, count 2 2006.257.10:38:24.71#ibcon#read 3, iclass 30, count 2 2006.257.10:38:24.71#ibcon#about to read 4, iclass 30, count 2 2006.257.10:38:24.71#ibcon#read 4, iclass 30, count 2 2006.257.10:38:24.71#ibcon#about to read 5, iclass 30, count 2 2006.257.10:38:24.71#ibcon#read 5, iclass 30, count 2 2006.257.10:38:24.71#ibcon#about to read 6, iclass 30, count 2 2006.257.10:38:24.71#ibcon#read 6, iclass 30, count 2 2006.257.10:38:24.71#ibcon#end of sib2, iclass 30, count 2 2006.257.10:38:24.71#ibcon#*after write, iclass 30, count 2 2006.257.10:38:24.71#ibcon#*before return 0, iclass 30, count 2 2006.257.10:38:24.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:24.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.10:38:24.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.10:38:24.71#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:24.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:24.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:24.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:24.83#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:38:24.83#ibcon#first serial, iclass 30, count 0 2006.257.10:38:24.83#ibcon#enter sib2, iclass 30, count 0 2006.257.10:38:24.83#ibcon#flushed, iclass 30, count 0 2006.257.10:38:24.83#ibcon#about to write, iclass 30, count 0 2006.257.10:38:24.83#ibcon#wrote, iclass 30, count 0 2006.257.10:38:24.83#ibcon#about to read 3, iclass 30, count 0 2006.257.10:38:24.85#ibcon#read 3, iclass 30, count 0 2006.257.10:38:24.85#ibcon#about to read 4, iclass 30, count 0 2006.257.10:38:24.85#ibcon#read 4, iclass 30, count 0 2006.257.10:38:24.85#ibcon#about to read 5, iclass 30, count 0 2006.257.10:38:24.85#ibcon#read 5, iclass 30, count 0 2006.257.10:38:24.85#ibcon#about to read 6, iclass 30, count 0 2006.257.10:38:24.85#ibcon#read 6, iclass 30, count 0 2006.257.10:38:24.85#ibcon#end of sib2, iclass 30, count 0 2006.257.10:38:24.85#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:38:24.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:38:24.85#ibcon#[27=USB\r\n] 2006.257.10:38:24.85#ibcon#*before write, iclass 30, count 0 2006.257.10:38:24.85#ibcon#enter sib2, iclass 30, count 0 2006.257.10:38:24.85#ibcon#flushed, iclass 30, count 0 2006.257.10:38:24.85#ibcon#about to write, iclass 30, count 0 2006.257.10:38:24.85#ibcon#wrote, iclass 30, count 0 2006.257.10:38:24.85#ibcon#about to read 3, iclass 30, count 0 2006.257.10:38:24.88#ibcon#read 3, iclass 30, count 0 2006.257.10:38:24.88#ibcon#about to read 4, iclass 30, count 0 2006.257.10:38:24.88#ibcon#read 4, iclass 30, count 0 2006.257.10:38:24.88#ibcon#about to read 5, iclass 30, count 0 2006.257.10:38:24.88#ibcon#read 5, iclass 30, count 0 2006.257.10:38:24.88#ibcon#about to read 6, iclass 30, count 0 2006.257.10:38:24.88#ibcon#read 6, iclass 30, count 0 2006.257.10:38:24.88#ibcon#end of sib2, iclass 30, count 0 2006.257.10:38:24.88#ibcon#*after write, iclass 30, count 0 2006.257.10:38:24.88#ibcon#*before return 0, iclass 30, count 0 2006.257.10:38:24.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:24.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.10:38:24.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:38:24.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:38:24.88$vck44/vblo=4,679.99 2006.257.10:38:24.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.10:38:24.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.10:38:24.88#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:24.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:24.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:24.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:24.88#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:38:24.88#ibcon#first serial, iclass 32, count 0 2006.257.10:38:24.88#ibcon#enter sib2, iclass 32, count 0 2006.257.10:38:24.88#ibcon#flushed, iclass 32, count 0 2006.257.10:38:24.88#ibcon#about to write, iclass 32, count 0 2006.257.10:38:24.88#ibcon#wrote, iclass 32, count 0 2006.257.10:38:24.88#ibcon#about to read 3, iclass 32, count 0 2006.257.10:38:24.90#ibcon#read 3, iclass 32, count 0 2006.257.10:38:24.90#ibcon#about to read 4, iclass 32, count 0 2006.257.10:38:24.90#ibcon#read 4, iclass 32, count 0 2006.257.10:38:24.90#ibcon#about to read 5, iclass 32, count 0 2006.257.10:38:24.90#ibcon#read 5, iclass 32, count 0 2006.257.10:38:24.90#ibcon#about to read 6, iclass 32, count 0 2006.257.10:38:24.90#ibcon#read 6, iclass 32, count 0 2006.257.10:38:24.90#ibcon#end of sib2, iclass 32, count 0 2006.257.10:38:24.90#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:38:24.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:38:24.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:38:24.90#ibcon#*before write, iclass 32, count 0 2006.257.10:38:24.90#ibcon#enter sib2, iclass 32, count 0 2006.257.10:38:24.90#ibcon#flushed, iclass 32, count 0 2006.257.10:38:24.90#ibcon#about to write, iclass 32, count 0 2006.257.10:38:24.90#ibcon#wrote, iclass 32, count 0 2006.257.10:38:24.90#ibcon#about to read 3, iclass 32, count 0 2006.257.10:38:24.94#ibcon#read 3, iclass 32, count 0 2006.257.10:38:24.94#ibcon#about to read 4, iclass 32, count 0 2006.257.10:38:24.94#ibcon#read 4, iclass 32, count 0 2006.257.10:38:24.94#ibcon#about to read 5, iclass 32, count 0 2006.257.10:38:24.94#ibcon#read 5, iclass 32, count 0 2006.257.10:38:24.94#ibcon#about to read 6, iclass 32, count 0 2006.257.10:38:24.94#ibcon#read 6, iclass 32, count 0 2006.257.10:38:24.94#ibcon#end of sib2, iclass 32, count 0 2006.257.10:38:24.94#ibcon#*after write, iclass 32, count 0 2006.257.10:38:24.94#ibcon#*before return 0, iclass 32, count 0 2006.257.10:38:24.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:24.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.10:38:24.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:38:24.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:38:24.94$vck44/vb=4,5 2006.257.10:38:24.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.10:38:24.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.10:38:24.94#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:24.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:25.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:25.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:25.00#ibcon#enter wrdev, iclass 34, count 2 2006.257.10:38:25.00#ibcon#first serial, iclass 34, count 2 2006.257.10:38:25.00#ibcon#enter sib2, iclass 34, count 2 2006.257.10:38:25.00#ibcon#flushed, iclass 34, count 2 2006.257.10:38:25.00#ibcon#about to write, iclass 34, count 2 2006.257.10:38:25.00#ibcon#wrote, iclass 34, count 2 2006.257.10:38:25.00#ibcon#about to read 3, iclass 34, count 2 2006.257.10:38:25.02#ibcon#read 3, iclass 34, count 2 2006.257.10:38:25.02#ibcon#about to read 4, iclass 34, count 2 2006.257.10:38:25.02#ibcon#read 4, iclass 34, count 2 2006.257.10:38:25.02#ibcon#about to read 5, iclass 34, count 2 2006.257.10:38:25.02#ibcon#read 5, iclass 34, count 2 2006.257.10:38:25.02#ibcon#about to read 6, iclass 34, count 2 2006.257.10:38:25.02#ibcon#read 6, iclass 34, count 2 2006.257.10:38:25.02#ibcon#end of sib2, iclass 34, count 2 2006.257.10:38:25.02#ibcon#*mode == 0, iclass 34, count 2 2006.257.10:38:25.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.10:38:25.02#ibcon#[27=AT04-05\r\n] 2006.257.10:38:25.02#ibcon#*before write, iclass 34, count 2 2006.257.10:38:25.02#ibcon#enter sib2, iclass 34, count 2 2006.257.10:38:25.02#ibcon#flushed, iclass 34, count 2 2006.257.10:38:25.02#ibcon#about to write, iclass 34, count 2 2006.257.10:38:25.02#ibcon#wrote, iclass 34, count 2 2006.257.10:38:25.02#ibcon#about to read 3, iclass 34, count 2 2006.257.10:38:25.05#ibcon#read 3, iclass 34, count 2 2006.257.10:38:25.05#ibcon#about to read 4, iclass 34, count 2 2006.257.10:38:25.05#ibcon#read 4, iclass 34, count 2 2006.257.10:38:25.05#ibcon#about to read 5, iclass 34, count 2 2006.257.10:38:25.05#ibcon#read 5, iclass 34, count 2 2006.257.10:38:25.05#ibcon#about to read 6, iclass 34, count 2 2006.257.10:38:25.05#ibcon#read 6, iclass 34, count 2 2006.257.10:38:25.05#ibcon#end of sib2, iclass 34, count 2 2006.257.10:38:25.05#ibcon#*after write, iclass 34, count 2 2006.257.10:38:25.05#ibcon#*before return 0, iclass 34, count 2 2006.257.10:38:25.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:25.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.10:38:25.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.10:38:25.05#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:25.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:25.08#abcon#<5=/14 1.4 3.7 18.88 961013.9\r\n> 2006.257.10:38:25.10#abcon#{5=INTERFACE CLEAR} 2006.257.10:38:25.16#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:38:25.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:25.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:25.17#ibcon#enter wrdev, iclass 34, count 0 2006.257.10:38:25.17#ibcon#first serial, iclass 34, count 0 2006.257.10:38:25.17#ibcon#enter sib2, iclass 34, count 0 2006.257.10:38:25.17#ibcon#flushed, iclass 34, count 0 2006.257.10:38:25.17#ibcon#about to write, iclass 34, count 0 2006.257.10:38:25.17#ibcon#wrote, iclass 34, count 0 2006.257.10:38:25.17#ibcon#about to read 3, iclass 34, count 0 2006.257.10:38:25.19#ibcon#read 3, iclass 34, count 0 2006.257.10:38:25.19#ibcon#about to read 4, iclass 34, count 0 2006.257.10:38:25.19#ibcon#read 4, iclass 34, count 0 2006.257.10:38:25.19#ibcon#about to read 5, iclass 34, count 0 2006.257.10:38:25.19#ibcon#read 5, iclass 34, count 0 2006.257.10:38:25.19#ibcon#about to read 6, iclass 34, count 0 2006.257.10:38:25.19#ibcon#read 6, iclass 34, count 0 2006.257.10:38:25.19#ibcon#end of sib2, iclass 34, count 0 2006.257.10:38:25.19#ibcon#*mode == 0, iclass 34, count 0 2006.257.10:38:25.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.10:38:25.19#ibcon#[27=USB\r\n] 2006.257.10:38:25.19#ibcon#*before write, iclass 34, count 0 2006.257.10:38:25.19#ibcon#enter sib2, iclass 34, count 0 2006.257.10:38:25.19#ibcon#flushed, iclass 34, count 0 2006.257.10:38:25.19#ibcon#about to write, iclass 34, count 0 2006.257.10:38:25.19#ibcon#wrote, iclass 34, count 0 2006.257.10:38:25.19#ibcon#about to read 3, iclass 34, count 0 2006.257.10:38:25.22#ibcon#read 3, iclass 34, count 0 2006.257.10:38:25.22#ibcon#about to read 4, iclass 34, count 0 2006.257.10:38:25.22#ibcon#read 4, iclass 34, count 0 2006.257.10:38:25.22#ibcon#about to read 5, iclass 34, count 0 2006.257.10:38:25.22#ibcon#read 5, iclass 34, count 0 2006.257.10:38:25.22#ibcon#about to read 6, iclass 34, count 0 2006.257.10:38:25.22#ibcon#read 6, iclass 34, count 0 2006.257.10:38:25.22#ibcon#end of sib2, iclass 34, count 0 2006.257.10:38:25.22#ibcon#*after write, iclass 34, count 0 2006.257.10:38:25.22#ibcon#*before return 0, iclass 34, count 0 2006.257.10:38:25.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:25.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.10:38:25.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.10:38:25.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.10:38:25.22$vck44/vblo=5,709.99 2006.257.10:38:25.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.10:38:25.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.10:38:25.22#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:25.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:25.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:25.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:25.22#ibcon#enter wrdev, iclass 40, count 0 2006.257.10:38:25.22#ibcon#first serial, iclass 40, count 0 2006.257.10:38:25.22#ibcon#enter sib2, iclass 40, count 0 2006.257.10:38:25.22#ibcon#flushed, iclass 40, count 0 2006.257.10:38:25.22#ibcon#about to write, iclass 40, count 0 2006.257.10:38:25.22#ibcon#wrote, iclass 40, count 0 2006.257.10:38:25.22#ibcon#about to read 3, iclass 40, count 0 2006.257.10:38:25.24#ibcon#read 3, iclass 40, count 0 2006.257.10:38:25.24#ibcon#about to read 4, iclass 40, count 0 2006.257.10:38:25.24#ibcon#read 4, iclass 40, count 0 2006.257.10:38:25.24#ibcon#about to read 5, iclass 40, count 0 2006.257.10:38:25.24#ibcon#read 5, iclass 40, count 0 2006.257.10:38:25.24#ibcon#about to read 6, iclass 40, count 0 2006.257.10:38:25.24#ibcon#read 6, iclass 40, count 0 2006.257.10:38:25.24#ibcon#end of sib2, iclass 40, count 0 2006.257.10:38:25.24#ibcon#*mode == 0, iclass 40, count 0 2006.257.10:38:25.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.10:38:25.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:38:25.24#ibcon#*before write, iclass 40, count 0 2006.257.10:38:25.24#ibcon#enter sib2, iclass 40, count 0 2006.257.10:38:25.24#ibcon#flushed, iclass 40, count 0 2006.257.10:38:25.24#ibcon#about to write, iclass 40, count 0 2006.257.10:38:25.24#ibcon#wrote, iclass 40, count 0 2006.257.10:38:25.24#ibcon#about to read 3, iclass 40, count 0 2006.257.10:38:25.28#ibcon#read 3, iclass 40, count 0 2006.257.10:38:25.28#ibcon#about to read 4, iclass 40, count 0 2006.257.10:38:25.28#ibcon#read 4, iclass 40, count 0 2006.257.10:38:25.28#ibcon#about to read 5, iclass 40, count 0 2006.257.10:38:25.28#ibcon#read 5, iclass 40, count 0 2006.257.10:38:25.28#ibcon#about to read 6, iclass 40, count 0 2006.257.10:38:25.28#ibcon#read 6, iclass 40, count 0 2006.257.10:38:25.28#ibcon#end of sib2, iclass 40, count 0 2006.257.10:38:25.28#ibcon#*after write, iclass 40, count 0 2006.257.10:38:25.28#ibcon#*before return 0, iclass 40, count 0 2006.257.10:38:25.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:25.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:38:25.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.10:38:25.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.10:38:25.28$vck44/vb=5,4 2006.257.10:38:25.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.10:38:25.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.10:38:25.28#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:25.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:25.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:25.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:25.34#ibcon#enter wrdev, iclass 4, count 2 2006.257.10:38:25.34#ibcon#first serial, iclass 4, count 2 2006.257.10:38:25.34#ibcon#enter sib2, iclass 4, count 2 2006.257.10:38:25.34#ibcon#flushed, iclass 4, count 2 2006.257.10:38:25.34#ibcon#about to write, iclass 4, count 2 2006.257.10:38:25.34#ibcon#wrote, iclass 4, count 2 2006.257.10:38:25.34#ibcon#about to read 3, iclass 4, count 2 2006.257.10:38:25.36#ibcon#read 3, iclass 4, count 2 2006.257.10:38:25.36#ibcon#about to read 4, iclass 4, count 2 2006.257.10:38:25.36#ibcon#read 4, iclass 4, count 2 2006.257.10:38:25.36#ibcon#about to read 5, iclass 4, count 2 2006.257.10:38:25.36#ibcon#read 5, iclass 4, count 2 2006.257.10:38:25.36#ibcon#about to read 6, iclass 4, count 2 2006.257.10:38:25.36#ibcon#read 6, iclass 4, count 2 2006.257.10:38:25.36#ibcon#end of sib2, iclass 4, count 2 2006.257.10:38:25.36#ibcon#*mode == 0, iclass 4, count 2 2006.257.10:38:25.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.10:38:25.36#ibcon#[27=AT05-04\r\n] 2006.257.10:38:25.36#ibcon#*before write, iclass 4, count 2 2006.257.10:38:25.36#ibcon#enter sib2, iclass 4, count 2 2006.257.10:38:25.36#ibcon#flushed, iclass 4, count 2 2006.257.10:38:25.36#ibcon#about to write, iclass 4, count 2 2006.257.10:38:25.36#ibcon#wrote, iclass 4, count 2 2006.257.10:38:25.36#ibcon#about to read 3, iclass 4, count 2 2006.257.10:38:25.39#ibcon#read 3, iclass 4, count 2 2006.257.10:38:25.39#ibcon#about to read 4, iclass 4, count 2 2006.257.10:38:25.39#ibcon#read 4, iclass 4, count 2 2006.257.10:38:25.39#ibcon#about to read 5, iclass 4, count 2 2006.257.10:38:25.39#ibcon#read 5, iclass 4, count 2 2006.257.10:38:25.39#ibcon#about to read 6, iclass 4, count 2 2006.257.10:38:25.39#ibcon#read 6, iclass 4, count 2 2006.257.10:38:25.39#ibcon#end of sib2, iclass 4, count 2 2006.257.10:38:25.39#ibcon#*after write, iclass 4, count 2 2006.257.10:38:25.39#ibcon#*before return 0, iclass 4, count 2 2006.257.10:38:25.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:25.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.10:38:25.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.10:38:25.39#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:25.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:25.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:25.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:25.51#ibcon#enter wrdev, iclass 4, count 0 2006.257.10:38:25.51#ibcon#first serial, iclass 4, count 0 2006.257.10:38:25.51#ibcon#enter sib2, iclass 4, count 0 2006.257.10:38:25.51#ibcon#flushed, iclass 4, count 0 2006.257.10:38:25.51#ibcon#about to write, iclass 4, count 0 2006.257.10:38:25.51#ibcon#wrote, iclass 4, count 0 2006.257.10:38:25.51#ibcon#about to read 3, iclass 4, count 0 2006.257.10:38:25.53#ibcon#read 3, iclass 4, count 0 2006.257.10:38:25.53#ibcon#about to read 4, iclass 4, count 0 2006.257.10:38:25.53#ibcon#read 4, iclass 4, count 0 2006.257.10:38:25.53#ibcon#about to read 5, iclass 4, count 0 2006.257.10:38:25.53#ibcon#read 5, iclass 4, count 0 2006.257.10:38:25.53#ibcon#about to read 6, iclass 4, count 0 2006.257.10:38:25.53#ibcon#read 6, iclass 4, count 0 2006.257.10:38:25.53#ibcon#end of sib2, iclass 4, count 0 2006.257.10:38:25.53#ibcon#*mode == 0, iclass 4, count 0 2006.257.10:38:25.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.10:38:25.53#ibcon#[27=USB\r\n] 2006.257.10:38:25.53#ibcon#*before write, iclass 4, count 0 2006.257.10:38:25.53#ibcon#enter sib2, iclass 4, count 0 2006.257.10:38:25.53#ibcon#flushed, iclass 4, count 0 2006.257.10:38:25.53#ibcon#about to write, iclass 4, count 0 2006.257.10:38:25.53#ibcon#wrote, iclass 4, count 0 2006.257.10:38:25.53#ibcon#about to read 3, iclass 4, count 0 2006.257.10:38:25.56#ibcon#read 3, iclass 4, count 0 2006.257.10:38:25.56#ibcon#about to read 4, iclass 4, count 0 2006.257.10:38:25.56#ibcon#read 4, iclass 4, count 0 2006.257.10:38:25.56#ibcon#about to read 5, iclass 4, count 0 2006.257.10:38:25.56#ibcon#read 5, iclass 4, count 0 2006.257.10:38:25.56#ibcon#about to read 6, iclass 4, count 0 2006.257.10:38:25.56#ibcon#read 6, iclass 4, count 0 2006.257.10:38:25.56#ibcon#end of sib2, iclass 4, count 0 2006.257.10:38:25.56#ibcon#*after write, iclass 4, count 0 2006.257.10:38:25.56#ibcon#*before return 0, iclass 4, count 0 2006.257.10:38:25.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:25.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.10:38:25.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.10:38:25.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.10:38:25.56$vck44/vblo=6,719.99 2006.257.10:38:25.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.10:38:25.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.10:38:25.56#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:25.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:25.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:25.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:25.56#ibcon#enter wrdev, iclass 6, count 0 2006.257.10:38:25.56#ibcon#first serial, iclass 6, count 0 2006.257.10:38:25.56#ibcon#enter sib2, iclass 6, count 0 2006.257.10:38:25.56#ibcon#flushed, iclass 6, count 0 2006.257.10:38:25.56#ibcon#about to write, iclass 6, count 0 2006.257.10:38:25.56#ibcon#wrote, iclass 6, count 0 2006.257.10:38:25.56#ibcon#about to read 3, iclass 6, count 0 2006.257.10:38:25.58#ibcon#read 3, iclass 6, count 0 2006.257.10:38:25.58#ibcon#about to read 4, iclass 6, count 0 2006.257.10:38:25.58#ibcon#read 4, iclass 6, count 0 2006.257.10:38:25.58#ibcon#about to read 5, iclass 6, count 0 2006.257.10:38:25.58#ibcon#read 5, iclass 6, count 0 2006.257.10:38:25.58#ibcon#about to read 6, iclass 6, count 0 2006.257.10:38:25.58#ibcon#read 6, iclass 6, count 0 2006.257.10:38:25.58#ibcon#end of sib2, iclass 6, count 0 2006.257.10:38:25.58#ibcon#*mode == 0, iclass 6, count 0 2006.257.10:38:25.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.10:38:25.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:38:25.58#ibcon#*before write, iclass 6, count 0 2006.257.10:38:25.58#ibcon#enter sib2, iclass 6, count 0 2006.257.10:38:25.58#ibcon#flushed, iclass 6, count 0 2006.257.10:38:25.58#ibcon#about to write, iclass 6, count 0 2006.257.10:38:25.58#ibcon#wrote, iclass 6, count 0 2006.257.10:38:25.58#ibcon#about to read 3, iclass 6, count 0 2006.257.10:38:25.62#ibcon#read 3, iclass 6, count 0 2006.257.10:38:25.62#ibcon#about to read 4, iclass 6, count 0 2006.257.10:38:25.62#ibcon#read 4, iclass 6, count 0 2006.257.10:38:25.62#ibcon#about to read 5, iclass 6, count 0 2006.257.10:38:25.62#ibcon#read 5, iclass 6, count 0 2006.257.10:38:25.62#ibcon#about to read 6, iclass 6, count 0 2006.257.10:38:25.62#ibcon#read 6, iclass 6, count 0 2006.257.10:38:25.62#ibcon#end of sib2, iclass 6, count 0 2006.257.10:38:25.62#ibcon#*after write, iclass 6, count 0 2006.257.10:38:25.62#ibcon#*before return 0, iclass 6, count 0 2006.257.10:38:25.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:25.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.10:38:25.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.10:38:25.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.10:38:25.62$vck44/vb=6,4 2006.257.10:38:25.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.10:38:25.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.10:38:25.62#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:25.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:25.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:25.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:25.68#ibcon#enter wrdev, iclass 10, count 2 2006.257.10:38:25.68#ibcon#first serial, iclass 10, count 2 2006.257.10:38:25.68#ibcon#enter sib2, iclass 10, count 2 2006.257.10:38:25.68#ibcon#flushed, iclass 10, count 2 2006.257.10:38:25.68#ibcon#about to write, iclass 10, count 2 2006.257.10:38:25.68#ibcon#wrote, iclass 10, count 2 2006.257.10:38:25.68#ibcon#about to read 3, iclass 10, count 2 2006.257.10:38:25.70#ibcon#read 3, iclass 10, count 2 2006.257.10:38:25.70#ibcon#about to read 4, iclass 10, count 2 2006.257.10:38:25.70#ibcon#read 4, iclass 10, count 2 2006.257.10:38:25.70#ibcon#about to read 5, iclass 10, count 2 2006.257.10:38:25.70#ibcon#read 5, iclass 10, count 2 2006.257.10:38:25.70#ibcon#about to read 6, iclass 10, count 2 2006.257.10:38:25.70#ibcon#read 6, iclass 10, count 2 2006.257.10:38:25.70#ibcon#end of sib2, iclass 10, count 2 2006.257.10:38:25.70#ibcon#*mode == 0, iclass 10, count 2 2006.257.10:38:25.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.10:38:25.70#ibcon#[27=AT06-04\r\n] 2006.257.10:38:25.70#ibcon#*before write, iclass 10, count 2 2006.257.10:38:25.70#ibcon#enter sib2, iclass 10, count 2 2006.257.10:38:25.70#ibcon#flushed, iclass 10, count 2 2006.257.10:38:25.70#ibcon#about to write, iclass 10, count 2 2006.257.10:38:25.70#ibcon#wrote, iclass 10, count 2 2006.257.10:38:25.70#ibcon#about to read 3, iclass 10, count 2 2006.257.10:38:25.73#ibcon#read 3, iclass 10, count 2 2006.257.10:38:25.73#ibcon#about to read 4, iclass 10, count 2 2006.257.10:38:25.73#ibcon#read 4, iclass 10, count 2 2006.257.10:38:25.73#ibcon#about to read 5, iclass 10, count 2 2006.257.10:38:25.73#ibcon#read 5, iclass 10, count 2 2006.257.10:38:25.73#ibcon#about to read 6, iclass 10, count 2 2006.257.10:38:25.73#ibcon#read 6, iclass 10, count 2 2006.257.10:38:25.73#ibcon#end of sib2, iclass 10, count 2 2006.257.10:38:25.73#ibcon#*after write, iclass 10, count 2 2006.257.10:38:25.73#ibcon#*before return 0, iclass 10, count 2 2006.257.10:38:25.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:25.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.10:38:25.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.10:38:25.73#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:25.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:25.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:25.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:25.85#ibcon#enter wrdev, iclass 10, count 0 2006.257.10:38:25.85#ibcon#first serial, iclass 10, count 0 2006.257.10:38:25.85#ibcon#enter sib2, iclass 10, count 0 2006.257.10:38:25.85#ibcon#flushed, iclass 10, count 0 2006.257.10:38:25.85#ibcon#about to write, iclass 10, count 0 2006.257.10:38:25.85#ibcon#wrote, iclass 10, count 0 2006.257.10:38:25.85#ibcon#about to read 3, iclass 10, count 0 2006.257.10:38:25.87#ibcon#read 3, iclass 10, count 0 2006.257.10:38:25.87#ibcon#about to read 4, iclass 10, count 0 2006.257.10:38:25.87#ibcon#read 4, iclass 10, count 0 2006.257.10:38:25.87#ibcon#about to read 5, iclass 10, count 0 2006.257.10:38:25.87#ibcon#read 5, iclass 10, count 0 2006.257.10:38:25.87#ibcon#about to read 6, iclass 10, count 0 2006.257.10:38:25.87#ibcon#read 6, iclass 10, count 0 2006.257.10:38:25.87#ibcon#end of sib2, iclass 10, count 0 2006.257.10:38:25.87#ibcon#*mode == 0, iclass 10, count 0 2006.257.10:38:25.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.10:38:25.87#ibcon#[27=USB\r\n] 2006.257.10:38:25.87#ibcon#*before write, iclass 10, count 0 2006.257.10:38:25.87#ibcon#enter sib2, iclass 10, count 0 2006.257.10:38:25.87#ibcon#flushed, iclass 10, count 0 2006.257.10:38:25.87#ibcon#about to write, iclass 10, count 0 2006.257.10:38:25.87#ibcon#wrote, iclass 10, count 0 2006.257.10:38:25.87#ibcon#about to read 3, iclass 10, count 0 2006.257.10:38:25.90#ibcon#read 3, iclass 10, count 0 2006.257.10:38:25.90#ibcon#about to read 4, iclass 10, count 0 2006.257.10:38:25.90#ibcon#read 4, iclass 10, count 0 2006.257.10:38:25.90#ibcon#about to read 5, iclass 10, count 0 2006.257.10:38:25.90#ibcon#read 5, iclass 10, count 0 2006.257.10:38:25.90#ibcon#about to read 6, iclass 10, count 0 2006.257.10:38:25.90#ibcon#read 6, iclass 10, count 0 2006.257.10:38:25.90#ibcon#end of sib2, iclass 10, count 0 2006.257.10:38:25.90#ibcon#*after write, iclass 10, count 0 2006.257.10:38:25.90#ibcon#*before return 0, iclass 10, count 0 2006.257.10:38:25.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:25.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.10:38:25.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.10:38:25.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.10:38:25.90$vck44/vblo=7,734.99 2006.257.10:38:25.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.10:38:25.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.10:38:25.90#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:25.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:25.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:25.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:25.90#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:38:25.90#ibcon#first serial, iclass 12, count 0 2006.257.10:38:25.90#ibcon#enter sib2, iclass 12, count 0 2006.257.10:38:25.90#ibcon#flushed, iclass 12, count 0 2006.257.10:38:25.90#ibcon#about to write, iclass 12, count 0 2006.257.10:38:25.90#ibcon#wrote, iclass 12, count 0 2006.257.10:38:25.90#ibcon#about to read 3, iclass 12, count 0 2006.257.10:38:25.92#ibcon#read 3, iclass 12, count 0 2006.257.10:38:25.92#ibcon#about to read 4, iclass 12, count 0 2006.257.10:38:25.92#ibcon#read 4, iclass 12, count 0 2006.257.10:38:25.92#ibcon#about to read 5, iclass 12, count 0 2006.257.10:38:25.92#ibcon#read 5, iclass 12, count 0 2006.257.10:38:25.92#ibcon#about to read 6, iclass 12, count 0 2006.257.10:38:25.92#ibcon#read 6, iclass 12, count 0 2006.257.10:38:25.92#ibcon#end of sib2, iclass 12, count 0 2006.257.10:38:25.92#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:38:25.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:38:25.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:38:25.92#ibcon#*before write, iclass 12, count 0 2006.257.10:38:25.92#ibcon#enter sib2, iclass 12, count 0 2006.257.10:38:25.92#ibcon#flushed, iclass 12, count 0 2006.257.10:38:25.92#ibcon#about to write, iclass 12, count 0 2006.257.10:38:25.92#ibcon#wrote, iclass 12, count 0 2006.257.10:38:25.92#ibcon#about to read 3, iclass 12, count 0 2006.257.10:38:25.96#ibcon#read 3, iclass 12, count 0 2006.257.10:38:25.96#ibcon#about to read 4, iclass 12, count 0 2006.257.10:38:25.96#ibcon#read 4, iclass 12, count 0 2006.257.10:38:25.96#ibcon#about to read 5, iclass 12, count 0 2006.257.10:38:25.96#ibcon#read 5, iclass 12, count 0 2006.257.10:38:25.96#ibcon#about to read 6, iclass 12, count 0 2006.257.10:38:25.96#ibcon#read 6, iclass 12, count 0 2006.257.10:38:25.96#ibcon#end of sib2, iclass 12, count 0 2006.257.10:38:25.96#ibcon#*after write, iclass 12, count 0 2006.257.10:38:25.96#ibcon#*before return 0, iclass 12, count 0 2006.257.10:38:25.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:25.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.10:38:25.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:38:25.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:38:25.96$vck44/vb=7,4 2006.257.10:38:25.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.10:38:25.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.10:38:25.96#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:25.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:26.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:26.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:26.02#ibcon#enter wrdev, iclass 14, count 2 2006.257.10:38:26.02#ibcon#first serial, iclass 14, count 2 2006.257.10:38:26.02#ibcon#enter sib2, iclass 14, count 2 2006.257.10:38:26.02#ibcon#flushed, iclass 14, count 2 2006.257.10:38:26.02#ibcon#about to write, iclass 14, count 2 2006.257.10:38:26.02#ibcon#wrote, iclass 14, count 2 2006.257.10:38:26.02#ibcon#about to read 3, iclass 14, count 2 2006.257.10:38:26.04#ibcon#read 3, iclass 14, count 2 2006.257.10:38:26.04#ibcon#about to read 4, iclass 14, count 2 2006.257.10:38:26.04#ibcon#read 4, iclass 14, count 2 2006.257.10:38:26.04#ibcon#about to read 5, iclass 14, count 2 2006.257.10:38:26.04#ibcon#read 5, iclass 14, count 2 2006.257.10:38:26.04#ibcon#about to read 6, iclass 14, count 2 2006.257.10:38:26.04#ibcon#read 6, iclass 14, count 2 2006.257.10:38:26.04#ibcon#end of sib2, iclass 14, count 2 2006.257.10:38:26.04#ibcon#*mode == 0, iclass 14, count 2 2006.257.10:38:26.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.10:38:26.04#ibcon#[27=AT07-04\r\n] 2006.257.10:38:26.04#ibcon#*before write, iclass 14, count 2 2006.257.10:38:26.04#ibcon#enter sib2, iclass 14, count 2 2006.257.10:38:26.04#ibcon#flushed, iclass 14, count 2 2006.257.10:38:26.04#ibcon#about to write, iclass 14, count 2 2006.257.10:38:26.04#ibcon#wrote, iclass 14, count 2 2006.257.10:38:26.04#ibcon#about to read 3, iclass 14, count 2 2006.257.10:38:26.07#ibcon#read 3, iclass 14, count 2 2006.257.10:38:26.07#ibcon#about to read 4, iclass 14, count 2 2006.257.10:38:26.07#ibcon#read 4, iclass 14, count 2 2006.257.10:38:26.07#ibcon#about to read 5, iclass 14, count 2 2006.257.10:38:26.07#ibcon#read 5, iclass 14, count 2 2006.257.10:38:26.07#ibcon#about to read 6, iclass 14, count 2 2006.257.10:38:26.07#ibcon#read 6, iclass 14, count 2 2006.257.10:38:26.07#ibcon#end of sib2, iclass 14, count 2 2006.257.10:38:26.07#ibcon#*after write, iclass 14, count 2 2006.257.10:38:26.07#ibcon#*before return 0, iclass 14, count 2 2006.257.10:38:26.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:26.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.10:38:26.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.10:38:26.07#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:26.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:26.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:26.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:26.19#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:38:26.19#ibcon#first serial, iclass 14, count 0 2006.257.10:38:26.19#ibcon#enter sib2, iclass 14, count 0 2006.257.10:38:26.19#ibcon#flushed, iclass 14, count 0 2006.257.10:38:26.19#ibcon#about to write, iclass 14, count 0 2006.257.10:38:26.19#ibcon#wrote, iclass 14, count 0 2006.257.10:38:26.19#ibcon#about to read 3, iclass 14, count 0 2006.257.10:38:26.21#ibcon#read 3, iclass 14, count 0 2006.257.10:38:26.21#ibcon#about to read 4, iclass 14, count 0 2006.257.10:38:26.21#ibcon#read 4, iclass 14, count 0 2006.257.10:38:26.21#ibcon#about to read 5, iclass 14, count 0 2006.257.10:38:26.21#ibcon#read 5, iclass 14, count 0 2006.257.10:38:26.21#ibcon#about to read 6, iclass 14, count 0 2006.257.10:38:26.21#ibcon#read 6, iclass 14, count 0 2006.257.10:38:26.21#ibcon#end of sib2, iclass 14, count 0 2006.257.10:38:26.21#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:38:26.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:38:26.21#ibcon#[27=USB\r\n] 2006.257.10:38:26.21#ibcon#*before write, iclass 14, count 0 2006.257.10:38:26.21#ibcon#enter sib2, iclass 14, count 0 2006.257.10:38:26.21#ibcon#flushed, iclass 14, count 0 2006.257.10:38:26.21#ibcon#about to write, iclass 14, count 0 2006.257.10:38:26.21#ibcon#wrote, iclass 14, count 0 2006.257.10:38:26.21#ibcon#about to read 3, iclass 14, count 0 2006.257.10:38:26.24#ibcon#read 3, iclass 14, count 0 2006.257.10:38:26.24#ibcon#about to read 4, iclass 14, count 0 2006.257.10:38:26.24#ibcon#read 4, iclass 14, count 0 2006.257.10:38:26.24#ibcon#about to read 5, iclass 14, count 0 2006.257.10:38:26.24#ibcon#read 5, iclass 14, count 0 2006.257.10:38:26.24#ibcon#about to read 6, iclass 14, count 0 2006.257.10:38:26.24#ibcon#read 6, iclass 14, count 0 2006.257.10:38:26.24#ibcon#end of sib2, iclass 14, count 0 2006.257.10:38:26.24#ibcon#*after write, iclass 14, count 0 2006.257.10:38:26.24#ibcon#*before return 0, iclass 14, count 0 2006.257.10:38:26.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:26.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.10:38:26.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:38:26.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:38:26.24$vck44/vblo=8,744.99 2006.257.10:38:26.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.10:38:26.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.10:38:26.24#ibcon#ireg 17 cls_cnt 0 2006.257.10:38:26.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:26.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:26.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:26.24#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:38:26.24#ibcon#first serial, iclass 16, count 0 2006.257.10:38:26.24#ibcon#enter sib2, iclass 16, count 0 2006.257.10:38:26.24#ibcon#flushed, iclass 16, count 0 2006.257.10:38:26.24#ibcon#about to write, iclass 16, count 0 2006.257.10:38:26.24#ibcon#wrote, iclass 16, count 0 2006.257.10:38:26.24#ibcon#about to read 3, iclass 16, count 0 2006.257.10:38:26.26#ibcon#read 3, iclass 16, count 0 2006.257.10:38:26.26#ibcon#about to read 4, iclass 16, count 0 2006.257.10:38:26.26#ibcon#read 4, iclass 16, count 0 2006.257.10:38:26.26#ibcon#about to read 5, iclass 16, count 0 2006.257.10:38:26.26#ibcon#read 5, iclass 16, count 0 2006.257.10:38:26.26#ibcon#about to read 6, iclass 16, count 0 2006.257.10:38:26.26#ibcon#read 6, iclass 16, count 0 2006.257.10:38:26.26#ibcon#end of sib2, iclass 16, count 0 2006.257.10:38:26.26#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:38:26.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:38:26.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:38:26.26#ibcon#*before write, iclass 16, count 0 2006.257.10:38:26.26#ibcon#enter sib2, iclass 16, count 0 2006.257.10:38:26.26#ibcon#flushed, iclass 16, count 0 2006.257.10:38:26.26#ibcon#about to write, iclass 16, count 0 2006.257.10:38:26.26#ibcon#wrote, iclass 16, count 0 2006.257.10:38:26.26#ibcon#about to read 3, iclass 16, count 0 2006.257.10:38:26.30#ibcon#read 3, iclass 16, count 0 2006.257.10:38:26.30#ibcon#about to read 4, iclass 16, count 0 2006.257.10:38:26.30#ibcon#read 4, iclass 16, count 0 2006.257.10:38:26.30#ibcon#about to read 5, iclass 16, count 0 2006.257.10:38:26.30#ibcon#read 5, iclass 16, count 0 2006.257.10:38:26.30#ibcon#about to read 6, iclass 16, count 0 2006.257.10:38:26.30#ibcon#read 6, iclass 16, count 0 2006.257.10:38:26.30#ibcon#end of sib2, iclass 16, count 0 2006.257.10:38:26.30#ibcon#*after write, iclass 16, count 0 2006.257.10:38:26.30#ibcon#*before return 0, iclass 16, count 0 2006.257.10:38:26.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:26.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.10:38:26.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:38:26.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:38:26.30$vck44/vb=8,4 2006.257.10:38:26.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.10:38:26.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.10:38:26.30#ibcon#ireg 11 cls_cnt 2 2006.257.10:38:26.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:26.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:26.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:26.36#ibcon#enter wrdev, iclass 18, count 2 2006.257.10:38:26.36#ibcon#first serial, iclass 18, count 2 2006.257.10:38:26.36#ibcon#enter sib2, iclass 18, count 2 2006.257.10:38:26.36#ibcon#flushed, iclass 18, count 2 2006.257.10:38:26.36#ibcon#about to write, iclass 18, count 2 2006.257.10:38:26.36#ibcon#wrote, iclass 18, count 2 2006.257.10:38:26.36#ibcon#about to read 3, iclass 18, count 2 2006.257.10:38:26.38#ibcon#read 3, iclass 18, count 2 2006.257.10:38:26.38#ibcon#about to read 4, iclass 18, count 2 2006.257.10:38:26.38#ibcon#read 4, iclass 18, count 2 2006.257.10:38:26.38#ibcon#about to read 5, iclass 18, count 2 2006.257.10:38:26.38#ibcon#read 5, iclass 18, count 2 2006.257.10:38:26.38#ibcon#about to read 6, iclass 18, count 2 2006.257.10:38:26.38#ibcon#read 6, iclass 18, count 2 2006.257.10:38:26.38#ibcon#end of sib2, iclass 18, count 2 2006.257.10:38:26.38#ibcon#*mode == 0, iclass 18, count 2 2006.257.10:38:26.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.10:38:26.38#ibcon#[27=AT08-04\r\n] 2006.257.10:38:26.38#ibcon#*before write, iclass 18, count 2 2006.257.10:38:26.38#ibcon#enter sib2, iclass 18, count 2 2006.257.10:38:26.38#ibcon#flushed, iclass 18, count 2 2006.257.10:38:26.38#ibcon#about to write, iclass 18, count 2 2006.257.10:38:26.38#ibcon#wrote, iclass 18, count 2 2006.257.10:38:26.38#ibcon#about to read 3, iclass 18, count 2 2006.257.10:38:26.41#ibcon#read 3, iclass 18, count 2 2006.257.10:38:26.41#ibcon#about to read 4, iclass 18, count 2 2006.257.10:38:26.41#ibcon#read 4, iclass 18, count 2 2006.257.10:38:26.41#ibcon#about to read 5, iclass 18, count 2 2006.257.10:38:26.41#ibcon#read 5, iclass 18, count 2 2006.257.10:38:26.41#ibcon#about to read 6, iclass 18, count 2 2006.257.10:38:26.41#ibcon#read 6, iclass 18, count 2 2006.257.10:38:26.41#ibcon#end of sib2, iclass 18, count 2 2006.257.10:38:26.41#ibcon#*after write, iclass 18, count 2 2006.257.10:38:26.41#ibcon#*before return 0, iclass 18, count 2 2006.257.10:38:26.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:26.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.10:38:26.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.10:38:26.41#ibcon#ireg 7 cls_cnt 0 2006.257.10:38:26.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:26.53#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:26.53#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:26.53#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:38:26.53#ibcon#first serial, iclass 18, count 0 2006.257.10:38:26.53#ibcon#enter sib2, iclass 18, count 0 2006.257.10:38:26.53#ibcon#flushed, iclass 18, count 0 2006.257.10:38:26.53#ibcon#about to write, iclass 18, count 0 2006.257.10:38:26.53#ibcon#wrote, iclass 18, count 0 2006.257.10:38:26.53#ibcon#about to read 3, iclass 18, count 0 2006.257.10:38:26.55#ibcon#read 3, iclass 18, count 0 2006.257.10:38:26.55#ibcon#about to read 4, iclass 18, count 0 2006.257.10:38:26.55#ibcon#read 4, iclass 18, count 0 2006.257.10:38:26.55#ibcon#about to read 5, iclass 18, count 0 2006.257.10:38:26.55#ibcon#read 5, iclass 18, count 0 2006.257.10:38:26.55#ibcon#about to read 6, iclass 18, count 0 2006.257.10:38:26.55#ibcon#read 6, iclass 18, count 0 2006.257.10:38:26.55#ibcon#end of sib2, iclass 18, count 0 2006.257.10:38:26.55#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:38:26.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:38:26.55#ibcon#[27=USB\r\n] 2006.257.10:38:26.55#ibcon#*before write, iclass 18, count 0 2006.257.10:38:26.55#ibcon#enter sib2, iclass 18, count 0 2006.257.10:38:26.55#ibcon#flushed, iclass 18, count 0 2006.257.10:38:26.55#ibcon#about to write, iclass 18, count 0 2006.257.10:38:26.55#ibcon#wrote, iclass 18, count 0 2006.257.10:38:26.55#ibcon#about to read 3, iclass 18, count 0 2006.257.10:38:26.58#ibcon#read 3, iclass 18, count 0 2006.257.10:38:26.58#ibcon#about to read 4, iclass 18, count 0 2006.257.10:38:26.58#ibcon#read 4, iclass 18, count 0 2006.257.10:38:26.58#ibcon#about to read 5, iclass 18, count 0 2006.257.10:38:26.58#ibcon#read 5, iclass 18, count 0 2006.257.10:38:26.58#ibcon#about to read 6, iclass 18, count 0 2006.257.10:38:26.58#ibcon#read 6, iclass 18, count 0 2006.257.10:38:26.58#ibcon#end of sib2, iclass 18, count 0 2006.257.10:38:26.58#ibcon#*after write, iclass 18, count 0 2006.257.10:38:26.58#ibcon#*before return 0, iclass 18, count 0 2006.257.10:38:26.58#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:26.58#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.10:38:26.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:38:26.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:38:26.58$vck44/vabw=wide 2006.257.10:38:26.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.10:38:26.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.10:38:26.58#ibcon#ireg 8 cls_cnt 0 2006.257.10:38:26.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:26.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:26.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:26.58#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:38:26.58#ibcon#first serial, iclass 20, count 0 2006.257.10:38:26.58#ibcon#enter sib2, iclass 20, count 0 2006.257.10:38:26.58#ibcon#flushed, iclass 20, count 0 2006.257.10:38:26.58#ibcon#about to write, iclass 20, count 0 2006.257.10:38:26.58#ibcon#wrote, iclass 20, count 0 2006.257.10:38:26.58#ibcon#about to read 3, iclass 20, count 0 2006.257.10:38:26.60#ibcon#read 3, iclass 20, count 0 2006.257.10:38:26.60#ibcon#about to read 4, iclass 20, count 0 2006.257.10:38:26.60#ibcon#read 4, iclass 20, count 0 2006.257.10:38:26.60#ibcon#about to read 5, iclass 20, count 0 2006.257.10:38:26.60#ibcon#read 5, iclass 20, count 0 2006.257.10:38:26.60#ibcon#about to read 6, iclass 20, count 0 2006.257.10:38:26.60#ibcon#read 6, iclass 20, count 0 2006.257.10:38:26.60#ibcon#end of sib2, iclass 20, count 0 2006.257.10:38:26.60#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:38:26.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:38:26.60#ibcon#[25=BW32\r\n] 2006.257.10:38:26.60#ibcon#*before write, iclass 20, count 0 2006.257.10:38:26.60#ibcon#enter sib2, iclass 20, count 0 2006.257.10:38:26.60#ibcon#flushed, iclass 20, count 0 2006.257.10:38:26.60#ibcon#about to write, iclass 20, count 0 2006.257.10:38:26.60#ibcon#wrote, iclass 20, count 0 2006.257.10:38:26.60#ibcon#about to read 3, iclass 20, count 0 2006.257.10:38:26.63#ibcon#read 3, iclass 20, count 0 2006.257.10:38:26.63#ibcon#about to read 4, iclass 20, count 0 2006.257.10:38:26.63#ibcon#read 4, iclass 20, count 0 2006.257.10:38:26.63#ibcon#about to read 5, iclass 20, count 0 2006.257.10:38:26.63#ibcon#read 5, iclass 20, count 0 2006.257.10:38:26.63#ibcon#about to read 6, iclass 20, count 0 2006.257.10:38:26.63#ibcon#read 6, iclass 20, count 0 2006.257.10:38:26.63#ibcon#end of sib2, iclass 20, count 0 2006.257.10:38:26.63#ibcon#*after write, iclass 20, count 0 2006.257.10:38:26.63#ibcon#*before return 0, iclass 20, count 0 2006.257.10:38:26.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:26.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.10:38:26.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:38:26.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:38:26.63$vck44/vbbw=wide 2006.257.10:38:26.63#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.10:38:26.63#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.10:38:26.63#ibcon#ireg 8 cls_cnt 0 2006.257.10:38:26.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:38:26.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:38:26.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:38:26.70#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:38:26.70#ibcon#first serial, iclass 22, count 0 2006.257.10:38:26.70#ibcon#enter sib2, iclass 22, count 0 2006.257.10:38:26.70#ibcon#flushed, iclass 22, count 0 2006.257.10:38:26.70#ibcon#about to write, iclass 22, count 0 2006.257.10:38:26.70#ibcon#wrote, iclass 22, count 0 2006.257.10:38:26.70#ibcon#about to read 3, iclass 22, count 0 2006.257.10:38:26.72#ibcon#read 3, iclass 22, count 0 2006.257.10:38:26.72#ibcon#about to read 4, iclass 22, count 0 2006.257.10:38:26.72#ibcon#read 4, iclass 22, count 0 2006.257.10:38:26.72#ibcon#about to read 5, iclass 22, count 0 2006.257.10:38:26.72#ibcon#read 5, iclass 22, count 0 2006.257.10:38:26.72#ibcon#about to read 6, iclass 22, count 0 2006.257.10:38:26.72#ibcon#read 6, iclass 22, count 0 2006.257.10:38:26.72#ibcon#end of sib2, iclass 22, count 0 2006.257.10:38:26.72#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:38:26.72#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:38:26.72#ibcon#[27=BW32\r\n] 2006.257.10:38:26.72#ibcon#*before write, iclass 22, count 0 2006.257.10:38:26.72#ibcon#enter sib2, iclass 22, count 0 2006.257.10:38:26.72#ibcon#flushed, iclass 22, count 0 2006.257.10:38:26.72#ibcon#about to write, iclass 22, count 0 2006.257.10:38:26.72#ibcon#wrote, iclass 22, count 0 2006.257.10:38:26.72#ibcon#about to read 3, iclass 22, count 0 2006.257.10:38:26.75#ibcon#read 3, iclass 22, count 0 2006.257.10:38:26.75#ibcon#about to read 4, iclass 22, count 0 2006.257.10:38:26.75#ibcon#read 4, iclass 22, count 0 2006.257.10:38:26.75#ibcon#about to read 5, iclass 22, count 0 2006.257.10:38:26.75#ibcon#read 5, iclass 22, count 0 2006.257.10:38:26.75#ibcon#about to read 6, iclass 22, count 0 2006.257.10:38:26.75#ibcon#read 6, iclass 22, count 0 2006.257.10:38:26.75#ibcon#end of sib2, iclass 22, count 0 2006.257.10:38:26.75#ibcon#*after write, iclass 22, count 0 2006.257.10:38:26.75#ibcon#*before return 0, iclass 22, count 0 2006.257.10:38:26.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:38:26.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:38:26.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:38:26.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:38:26.75$setupk4/ifdk4 2006.257.10:38:26.75$ifdk4/lo= 2006.257.10:38:26.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:38:26.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:38:26.75$ifdk4/patch= 2006.257.10:38:26.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:38:26.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:38:26.75$setupk4/!*+20s 2006.257.10:38:33.14#trakl#Source acquired 2006.257.10:38:35.14#flagr#flagr/antenna,acquired 2006.257.10:38:35.25#abcon#<5=/14 1.4 3.7 18.88 961013.9\r\n> 2006.257.10:38:35.27#abcon#{5=INTERFACE CLEAR} 2006.257.10:38:35.33#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:38:41.24$setupk4/"tpicd 2006.257.10:38:41.24$setupk4/echo=off 2006.257.10:38:41.24$setupk4/xlog=off 2006.257.10:38:41.24:!2006.257.10:40:37 2006.257.10:40:37.00:preob 2006.257.10:40:37.13/onsource/TRACKING 2006.257.10:40:37.13:!2006.257.10:40:47 2006.257.10:40:47.00:"tape 2006.257.10:40:47.00:"st=record 2006.257.10:40:47.00:data_valid=on 2006.257.10:40:47.00:midob 2006.257.10:40:47.13/onsource/TRACKING 2006.257.10:40:47.13/wx/18.86,1013.8,96 2006.257.10:40:47.19/cable/+6.4750E-03 2006.257.10:40:48.28/va/01,08,usb,yes,30,32 2006.257.10:40:48.28/va/02,07,usb,yes,33,33 2006.257.10:40:48.28/va/03,08,usb,yes,29,31 2006.257.10:40:48.28/va/04,07,usb,yes,34,35 2006.257.10:40:48.28/va/05,04,usb,yes,30,31 2006.257.10:40:48.28/va/06,04,usb,yes,34,33 2006.257.10:40:48.28/va/07,04,usb,yes,34,35 2006.257.10:40:48.28/va/08,04,usb,yes,29,35 2006.257.10:40:48.51/valo/01,524.99,yes,locked 2006.257.10:40:48.51/valo/02,534.99,yes,locked 2006.257.10:40:48.51/valo/03,564.99,yes,locked 2006.257.10:40:48.51/valo/04,624.99,yes,locked 2006.257.10:40:48.51/valo/05,734.99,yes,locked 2006.257.10:40:48.51/valo/06,814.99,yes,locked 2006.257.10:40:48.51/valo/07,864.99,yes,locked 2006.257.10:40:48.51/valo/08,884.99,yes,locked 2006.257.10:40:49.60/vb/01,04,usb,yes,30,28 2006.257.10:40:49.60/vb/02,05,usb,yes,28,28 2006.257.10:40:49.60/vb/03,04,usb,yes,29,32 2006.257.10:40:49.60/vb/04,05,usb,yes,29,28 2006.257.10:40:49.60/vb/05,04,usb,yes,26,28 2006.257.10:40:49.60/vb/06,04,usb,yes,30,27 2006.257.10:40:49.60/vb/07,04,usb,yes,30,30 2006.257.10:40:49.60/vb/08,04,usb,yes,28,31 2006.257.10:40:49.83/vblo/01,629.99,yes,locked 2006.257.10:40:49.83/vblo/02,634.99,yes,locked 2006.257.10:40:49.83/vblo/03,649.99,yes,locked 2006.257.10:40:49.83/vblo/04,679.99,yes,locked 2006.257.10:40:49.83/vblo/05,709.99,yes,locked 2006.257.10:40:49.83/vblo/06,719.99,yes,locked 2006.257.10:40:49.83/vblo/07,734.99,yes,locked 2006.257.10:40:49.83/vblo/08,744.99,yes,locked 2006.257.10:40:49.98/vabw/8 2006.257.10:40:50.13/vbbw/8 2006.257.10:40:50.22/xfe/off,on,15.2 2006.257.10:40:50.59/ifatt/23,28,28,28 2006.257.10:40:51.08/fmout-gps/S +4.62E-07 2006.257.10:40:51.12:!2006.257.10:41:57 2006.257.10:41:57.01:data_valid=off 2006.257.10:41:57.01:"et 2006.257.10:41:57.01:!+3s 2006.257.10:42:00.02:"tape 2006.257.10:42:00.02:postob 2006.257.10:42:00.24/cable/+6.4754E-03 2006.257.10:42:00.24/wx/18.85,1013.8,96 2006.257.10:42:00.30/fmout-gps/S +4.62E-07 2006.257.10:42:00.30:scan_name=257-1046,jd0609,110 2006.257.10:42:00.30:source=2128-123,213135.26,-120704.8,2000.0,ccw 2006.257.10:42:02.14#flagr#flagr/antenna,new-source 2006.257.10:42:02.14:checkk5 2006.257.10:42:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:42:02.91/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:42:03.33/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:42:03.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:42:04.12/chk_obsdata//k5ts1/T2571040??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.10:42:04.53/chk_obsdata//k5ts2/T2571040??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.10:42:04.94/chk_obsdata//k5ts3/T2571040??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.10:42:05.34/chk_obsdata//k5ts4/T2571040??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.10:42:06.07/k5log//k5ts1_log_newline 2006.257.10:42:06.78/k5log//k5ts2_log_newline 2006.257.10:42:07.51/k5log//k5ts3_log_newline 2006.257.10:42:08.22/k5log//k5ts4_log_newline 2006.257.10:42:08.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:42:08.25:setupk4=1 2006.257.10:42:08.25$setupk4/echo=on 2006.257.10:42:08.25$setupk4/pcalon 2006.257.10:42:08.25$pcalon/"no phase cal control is implemented here 2006.257.10:42:08.25$setupk4/"tpicd=stop 2006.257.10:42:08.25$setupk4/"rec=synch_on 2006.257.10:42:08.25$setupk4/"rec_mode=128 2006.257.10:42:08.25$setupk4/!* 2006.257.10:42:08.25$setupk4/recpk4 2006.257.10:42:08.25$recpk4/recpatch= 2006.257.10:42:08.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:42:08.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:42:08.25$setupk4/vck44 2006.257.10:42:08.25$vck44/valo=1,524.99 2006.257.10:42:08.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.10:42:08.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.10:42:08.25#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:08.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:08.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:08.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:08.25#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:42:08.25#ibcon#first serial, iclass 39, count 0 2006.257.10:42:08.25#ibcon#enter sib2, iclass 39, count 0 2006.257.10:42:08.25#ibcon#flushed, iclass 39, count 0 2006.257.10:42:08.25#ibcon#about to write, iclass 39, count 0 2006.257.10:42:08.25#ibcon#wrote, iclass 39, count 0 2006.257.10:42:08.25#ibcon#about to read 3, iclass 39, count 0 2006.257.10:42:08.27#ibcon#read 3, iclass 39, count 0 2006.257.10:42:08.27#ibcon#about to read 4, iclass 39, count 0 2006.257.10:42:08.27#ibcon#read 4, iclass 39, count 0 2006.257.10:42:08.27#ibcon#about to read 5, iclass 39, count 0 2006.257.10:42:08.27#ibcon#read 5, iclass 39, count 0 2006.257.10:42:08.27#ibcon#about to read 6, iclass 39, count 0 2006.257.10:42:08.27#ibcon#read 6, iclass 39, count 0 2006.257.10:42:08.27#ibcon#end of sib2, iclass 39, count 0 2006.257.10:42:08.27#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:42:08.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:42:08.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:42:08.27#ibcon#*before write, iclass 39, count 0 2006.257.10:42:08.27#ibcon#enter sib2, iclass 39, count 0 2006.257.10:42:08.27#ibcon#flushed, iclass 39, count 0 2006.257.10:42:08.27#ibcon#about to write, iclass 39, count 0 2006.257.10:42:08.27#ibcon#wrote, iclass 39, count 0 2006.257.10:42:08.27#ibcon#about to read 3, iclass 39, count 0 2006.257.10:42:08.32#ibcon#read 3, iclass 39, count 0 2006.257.10:42:08.32#ibcon#about to read 4, iclass 39, count 0 2006.257.10:42:08.32#ibcon#read 4, iclass 39, count 0 2006.257.10:42:08.32#ibcon#about to read 5, iclass 39, count 0 2006.257.10:42:08.32#ibcon#read 5, iclass 39, count 0 2006.257.10:42:08.32#ibcon#about to read 6, iclass 39, count 0 2006.257.10:42:08.32#ibcon#read 6, iclass 39, count 0 2006.257.10:42:08.32#ibcon#end of sib2, iclass 39, count 0 2006.257.10:42:08.32#ibcon#*after write, iclass 39, count 0 2006.257.10:42:08.32#ibcon#*before return 0, iclass 39, count 0 2006.257.10:42:08.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:08.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:08.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:42:08.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:42:08.32$vck44/va=1,8 2006.257.10:42:08.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.10:42:08.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.10:42:08.32#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:08.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:08.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:08.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:08.32#ibcon#enter wrdev, iclass 3, count 2 2006.257.10:42:08.32#ibcon#first serial, iclass 3, count 2 2006.257.10:42:08.32#ibcon#enter sib2, iclass 3, count 2 2006.257.10:42:08.32#ibcon#flushed, iclass 3, count 2 2006.257.10:42:08.32#ibcon#about to write, iclass 3, count 2 2006.257.10:42:08.32#ibcon#wrote, iclass 3, count 2 2006.257.10:42:08.32#ibcon#about to read 3, iclass 3, count 2 2006.257.10:42:08.34#ibcon#read 3, iclass 3, count 2 2006.257.10:42:08.34#ibcon#about to read 4, iclass 3, count 2 2006.257.10:42:08.34#ibcon#read 4, iclass 3, count 2 2006.257.10:42:08.34#ibcon#about to read 5, iclass 3, count 2 2006.257.10:42:08.34#ibcon#read 5, iclass 3, count 2 2006.257.10:42:08.34#ibcon#about to read 6, iclass 3, count 2 2006.257.10:42:08.34#ibcon#read 6, iclass 3, count 2 2006.257.10:42:08.34#ibcon#end of sib2, iclass 3, count 2 2006.257.10:42:08.34#ibcon#*mode == 0, iclass 3, count 2 2006.257.10:42:08.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.10:42:08.34#ibcon#[25=AT01-08\r\n] 2006.257.10:42:08.34#ibcon#*before write, iclass 3, count 2 2006.257.10:42:08.34#ibcon#enter sib2, iclass 3, count 2 2006.257.10:42:08.34#ibcon#flushed, iclass 3, count 2 2006.257.10:42:08.34#ibcon#about to write, iclass 3, count 2 2006.257.10:42:08.34#ibcon#wrote, iclass 3, count 2 2006.257.10:42:08.34#ibcon#about to read 3, iclass 3, count 2 2006.257.10:42:08.37#ibcon#read 3, iclass 3, count 2 2006.257.10:42:08.37#ibcon#about to read 4, iclass 3, count 2 2006.257.10:42:08.37#ibcon#read 4, iclass 3, count 2 2006.257.10:42:08.37#ibcon#about to read 5, iclass 3, count 2 2006.257.10:42:08.37#ibcon#read 5, iclass 3, count 2 2006.257.10:42:08.37#ibcon#about to read 6, iclass 3, count 2 2006.257.10:42:08.37#ibcon#read 6, iclass 3, count 2 2006.257.10:42:08.37#ibcon#end of sib2, iclass 3, count 2 2006.257.10:42:08.37#ibcon#*after write, iclass 3, count 2 2006.257.10:42:08.37#ibcon#*before return 0, iclass 3, count 2 2006.257.10:42:08.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:08.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:08.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.10:42:08.37#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:08.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:08.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:08.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:08.49#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:42:08.49#ibcon#first serial, iclass 3, count 0 2006.257.10:42:08.49#ibcon#enter sib2, iclass 3, count 0 2006.257.10:42:08.49#ibcon#flushed, iclass 3, count 0 2006.257.10:42:08.49#ibcon#about to write, iclass 3, count 0 2006.257.10:42:08.49#ibcon#wrote, iclass 3, count 0 2006.257.10:42:08.49#ibcon#about to read 3, iclass 3, count 0 2006.257.10:42:08.51#ibcon#read 3, iclass 3, count 0 2006.257.10:42:08.51#ibcon#about to read 4, iclass 3, count 0 2006.257.10:42:08.51#ibcon#read 4, iclass 3, count 0 2006.257.10:42:08.51#ibcon#about to read 5, iclass 3, count 0 2006.257.10:42:08.51#ibcon#read 5, iclass 3, count 0 2006.257.10:42:08.51#ibcon#about to read 6, iclass 3, count 0 2006.257.10:42:08.51#ibcon#read 6, iclass 3, count 0 2006.257.10:42:08.51#ibcon#end of sib2, iclass 3, count 0 2006.257.10:42:08.51#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:42:08.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:42:08.51#ibcon#[25=USB\r\n] 2006.257.10:42:08.51#ibcon#*before write, iclass 3, count 0 2006.257.10:42:08.51#ibcon#enter sib2, iclass 3, count 0 2006.257.10:42:08.51#ibcon#flushed, iclass 3, count 0 2006.257.10:42:08.51#ibcon#about to write, iclass 3, count 0 2006.257.10:42:08.51#ibcon#wrote, iclass 3, count 0 2006.257.10:42:08.51#ibcon#about to read 3, iclass 3, count 0 2006.257.10:42:08.54#ibcon#read 3, iclass 3, count 0 2006.257.10:42:08.54#ibcon#about to read 4, iclass 3, count 0 2006.257.10:42:08.54#ibcon#read 4, iclass 3, count 0 2006.257.10:42:08.54#ibcon#about to read 5, iclass 3, count 0 2006.257.10:42:08.54#ibcon#read 5, iclass 3, count 0 2006.257.10:42:08.54#ibcon#about to read 6, iclass 3, count 0 2006.257.10:42:08.54#ibcon#read 6, iclass 3, count 0 2006.257.10:42:08.54#ibcon#end of sib2, iclass 3, count 0 2006.257.10:42:08.54#ibcon#*after write, iclass 3, count 0 2006.257.10:42:08.54#ibcon#*before return 0, iclass 3, count 0 2006.257.10:42:08.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:08.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:08.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:42:08.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:42:08.54$vck44/valo=2,534.99 2006.257.10:42:08.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.10:42:08.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.10:42:08.54#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:08.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:08.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:08.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:08.54#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:42:08.54#ibcon#first serial, iclass 5, count 0 2006.257.10:42:08.54#ibcon#enter sib2, iclass 5, count 0 2006.257.10:42:08.54#ibcon#flushed, iclass 5, count 0 2006.257.10:42:08.54#ibcon#about to write, iclass 5, count 0 2006.257.10:42:08.54#ibcon#wrote, iclass 5, count 0 2006.257.10:42:08.54#ibcon#about to read 3, iclass 5, count 0 2006.257.10:42:08.56#ibcon#read 3, iclass 5, count 0 2006.257.10:42:08.56#ibcon#about to read 4, iclass 5, count 0 2006.257.10:42:08.56#ibcon#read 4, iclass 5, count 0 2006.257.10:42:08.56#ibcon#about to read 5, iclass 5, count 0 2006.257.10:42:08.56#ibcon#read 5, iclass 5, count 0 2006.257.10:42:08.56#ibcon#about to read 6, iclass 5, count 0 2006.257.10:42:08.56#ibcon#read 6, iclass 5, count 0 2006.257.10:42:08.56#ibcon#end of sib2, iclass 5, count 0 2006.257.10:42:08.56#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:42:08.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:42:08.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:42:08.56#ibcon#*before write, iclass 5, count 0 2006.257.10:42:08.56#ibcon#enter sib2, iclass 5, count 0 2006.257.10:42:08.56#ibcon#flushed, iclass 5, count 0 2006.257.10:42:08.56#ibcon#about to write, iclass 5, count 0 2006.257.10:42:08.56#ibcon#wrote, iclass 5, count 0 2006.257.10:42:08.56#ibcon#about to read 3, iclass 5, count 0 2006.257.10:42:08.60#ibcon#read 3, iclass 5, count 0 2006.257.10:42:08.60#ibcon#about to read 4, iclass 5, count 0 2006.257.10:42:08.60#ibcon#read 4, iclass 5, count 0 2006.257.10:42:08.60#ibcon#about to read 5, iclass 5, count 0 2006.257.10:42:08.60#ibcon#read 5, iclass 5, count 0 2006.257.10:42:08.60#ibcon#about to read 6, iclass 5, count 0 2006.257.10:42:08.60#ibcon#read 6, iclass 5, count 0 2006.257.10:42:08.60#ibcon#end of sib2, iclass 5, count 0 2006.257.10:42:08.60#ibcon#*after write, iclass 5, count 0 2006.257.10:42:08.60#ibcon#*before return 0, iclass 5, count 0 2006.257.10:42:08.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:08.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:08.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:42:08.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:42:08.60$vck44/va=2,7 2006.257.10:42:08.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.10:42:08.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.10:42:08.60#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:08.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:08.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:08.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:08.66#ibcon#enter wrdev, iclass 7, count 2 2006.257.10:42:08.66#ibcon#first serial, iclass 7, count 2 2006.257.10:42:08.66#ibcon#enter sib2, iclass 7, count 2 2006.257.10:42:08.66#ibcon#flushed, iclass 7, count 2 2006.257.10:42:08.66#ibcon#about to write, iclass 7, count 2 2006.257.10:42:08.66#ibcon#wrote, iclass 7, count 2 2006.257.10:42:08.66#ibcon#about to read 3, iclass 7, count 2 2006.257.10:42:08.68#ibcon#read 3, iclass 7, count 2 2006.257.10:42:08.68#ibcon#about to read 4, iclass 7, count 2 2006.257.10:42:08.68#ibcon#read 4, iclass 7, count 2 2006.257.10:42:08.68#ibcon#about to read 5, iclass 7, count 2 2006.257.10:42:08.68#ibcon#read 5, iclass 7, count 2 2006.257.10:42:08.68#ibcon#about to read 6, iclass 7, count 2 2006.257.10:42:08.68#ibcon#read 6, iclass 7, count 2 2006.257.10:42:08.68#ibcon#end of sib2, iclass 7, count 2 2006.257.10:42:08.68#ibcon#*mode == 0, iclass 7, count 2 2006.257.10:42:08.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.10:42:08.68#ibcon#[25=AT02-07\r\n] 2006.257.10:42:08.68#ibcon#*before write, iclass 7, count 2 2006.257.10:42:08.68#ibcon#enter sib2, iclass 7, count 2 2006.257.10:42:08.68#ibcon#flushed, iclass 7, count 2 2006.257.10:42:08.68#ibcon#about to write, iclass 7, count 2 2006.257.10:42:08.68#ibcon#wrote, iclass 7, count 2 2006.257.10:42:08.68#ibcon#about to read 3, iclass 7, count 2 2006.257.10:42:08.71#ibcon#read 3, iclass 7, count 2 2006.257.10:42:08.71#ibcon#about to read 4, iclass 7, count 2 2006.257.10:42:08.71#ibcon#read 4, iclass 7, count 2 2006.257.10:42:08.71#ibcon#about to read 5, iclass 7, count 2 2006.257.10:42:08.71#ibcon#read 5, iclass 7, count 2 2006.257.10:42:08.71#ibcon#about to read 6, iclass 7, count 2 2006.257.10:42:08.71#ibcon#read 6, iclass 7, count 2 2006.257.10:42:08.71#ibcon#end of sib2, iclass 7, count 2 2006.257.10:42:08.71#ibcon#*after write, iclass 7, count 2 2006.257.10:42:08.71#ibcon#*before return 0, iclass 7, count 2 2006.257.10:42:08.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:08.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:08.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.10:42:08.71#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:08.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:08.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:08.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:08.83#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:42:08.83#ibcon#first serial, iclass 7, count 0 2006.257.10:42:08.83#ibcon#enter sib2, iclass 7, count 0 2006.257.10:42:08.83#ibcon#flushed, iclass 7, count 0 2006.257.10:42:08.83#ibcon#about to write, iclass 7, count 0 2006.257.10:42:08.83#ibcon#wrote, iclass 7, count 0 2006.257.10:42:08.83#ibcon#about to read 3, iclass 7, count 0 2006.257.10:42:08.85#ibcon#read 3, iclass 7, count 0 2006.257.10:42:08.85#ibcon#about to read 4, iclass 7, count 0 2006.257.10:42:08.85#ibcon#read 4, iclass 7, count 0 2006.257.10:42:08.85#ibcon#about to read 5, iclass 7, count 0 2006.257.10:42:08.85#ibcon#read 5, iclass 7, count 0 2006.257.10:42:08.85#ibcon#about to read 6, iclass 7, count 0 2006.257.10:42:08.85#ibcon#read 6, iclass 7, count 0 2006.257.10:42:08.85#ibcon#end of sib2, iclass 7, count 0 2006.257.10:42:08.85#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:42:08.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:42:08.85#ibcon#[25=USB\r\n] 2006.257.10:42:08.85#ibcon#*before write, iclass 7, count 0 2006.257.10:42:08.85#ibcon#enter sib2, iclass 7, count 0 2006.257.10:42:08.85#ibcon#flushed, iclass 7, count 0 2006.257.10:42:08.85#ibcon#about to write, iclass 7, count 0 2006.257.10:42:08.85#ibcon#wrote, iclass 7, count 0 2006.257.10:42:08.85#ibcon#about to read 3, iclass 7, count 0 2006.257.10:42:08.86#abcon#<5=/14 1.6 4.4 18.84 961013.8\r\n> 2006.257.10:42:08.88#abcon#{5=INTERFACE CLEAR} 2006.257.10:42:08.88#ibcon#read 3, iclass 7, count 0 2006.257.10:42:08.88#ibcon#about to read 4, iclass 7, count 0 2006.257.10:42:08.88#ibcon#read 4, iclass 7, count 0 2006.257.10:42:08.88#ibcon#about to read 5, iclass 7, count 0 2006.257.10:42:08.88#ibcon#read 5, iclass 7, count 0 2006.257.10:42:08.88#ibcon#about to read 6, iclass 7, count 0 2006.257.10:42:08.88#ibcon#read 6, iclass 7, count 0 2006.257.10:42:08.88#ibcon#end of sib2, iclass 7, count 0 2006.257.10:42:08.88#ibcon#*after write, iclass 7, count 0 2006.257.10:42:08.88#ibcon#*before return 0, iclass 7, count 0 2006.257.10:42:08.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:08.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:08.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:42:08.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:42:08.88$vck44/valo=3,564.99 2006.257.10:42:08.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.10:42:08.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.10:42:08.88#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:08.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:42:08.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:42:08.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:42:08.88#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:42:08.88#ibcon#first serial, iclass 14, count 0 2006.257.10:42:08.88#ibcon#enter sib2, iclass 14, count 0 2006.257.10:42:08.88#ibcon#flushed, iclass 14, count 0 2006.257.10:42:08.88#ibcon#about to write, iclass 14, count 0 2006.257.10:42:08.88#ibcon#wrote, iclass 14, count 0 2006.257.10:42:08.88#ibcon#about to read 3, iclass 14, count 0 2006.257.10:42:08.90#ibcon#read 3, iclass 14, count 0 2006.257.10:42:08.90#ibcon#about to read 4, iclass 14, count 0 2006.257.10:42:08.90#ibcon#read 4, iclass 14, count 0 2006.257.10:42:08.90#ibcon#about to read 5, iclass 14, count 0 2006.257.10:42:08.90#ibcon#read 5, iclass 14, count 0 2006.257.10:42:08.90#ibcon#about to read 6, iclass 14, count 0 2006.257.10:42:08.90#ibcon#read 6, iclass 14, count 0 2006.257.10:42:08.90#ibcon#end of sib2, iclass 14, count 0 2006.257.10:42:08.90#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:42:08.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:42:08.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:42:08.90#ibcon#*before write, iclass 14, count 0 2006.257.10:42:08.90#ibcon#enter sib2, iclass 14, count 0 2006.257.10:42:08.90#ibcon#flushed, iclass 14, count 0 2006.257.10:42:08.90#ibcon#about to write, iclass 14, count 0 2006.257.10:42:08.90#ibcon#wrote, iclass 14, count 0 2006.257.10:42:08.90#ibcon#about to read 3, iclass 14, count 0 2006.257.10:42:08.94#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:42:08.94#ibcon#read 3, iclass 14, count 0 2006.257.10:42:08.94#ibcon#about to read 4, iclass 14, count 0 2006.257.10:42:08.94#ibcon#read 4, iclass 14, count 0 2006.257.10:42:08.94#ibcon#about to read 5, iclass 14, count 0 2006.257.10:42:08.94#ibcon#read 5, iclass 14, count 0 2006.257.10:42:08.94#ibcon#about to read 6, iclass 14, count 0 2006.257.10:42:08.94#ibcon#read 6, iclass 14, count 0 2006.257.10:42:08.94#ibcon#end of sib2, iclass 14, count 0 2006.257.10:42:08.94#ibcon#*after write, iclass 14, count 0 2006.257.10:42:08.94#ibcon#*before return 0, iclass 14, count 0 2006.257.10:42:08.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:42:08.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:42:08.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:42:08.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:42:08.94$vck44/va=3,8 2006.257.10:42:08.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.10:42:08.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.10:42:08.94#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:08.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:09.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:09.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:09.00#ibcon#enter wrdev, iclass 17, count 2 2006.257.10:42:09.00#ibcon#first serial, iclass 17, count 2 2006.257.10:42:09.00#ibcon#enter sib2, iclass 17, count 2 2006.257.10:42:09.00#ibcon#flushed, iclass 17, count 2 2006.257.10:42:09.00#ibcon#about to write, iclass 17, count 2 2006.257.10:42:09.00#ibcon#wrote, iclass 17, count 2 2006.257.10:42:09.00#ibcon#about to read 3, iclass 17, count 2 2006.257.10:42:09.02#ibcon#read 3, iclass 17, count 2 2006.257.10:42:09.02#ibcon#about to read 4, iclass 17, count 2 2006.257.10:42:09.02#ibcon#read 4, iclass 17, count 2 2006.257.10:42:09.02#ibcon#about to read 5, iclass 17, count 2 2006.257.10:42:09.02#ibcon#read 5, iclass 17, count 2 2006.257.10:42:09.02#ibcon#about to read 6, iclass 17, count 2 2006.257.10:42:09.02#ibcon#read 6, iclass 17, count 2 2006.257.10:42:09.02#ibcon#end of sib2, iclass 17, count 2 2006.257.10:42:09.02#ibcon#*mode == 0, iclass 17, count 2 2006.257.10:42:09.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.10:42:09.02#ibcon#[25=AT03-08\r\n] 2006.257.10:42:09.02#ibcon#*before write, iclass 17, count 2 2006.257.10:42:09.02#ibcon#enter sib2, iclass 17, count 2 2006.257.10:42:09.02#ibcon#flushed, iclass 17, count 2 2006.257.10:42:09.02#ibcon#about to write, iclass 17, count 2 2006.257.10:42:09.02#ibcon#wrote, iclass 17, count 2 2006.257.10:42:09.02#ibcon#about to read 3, iclass 17, count 2 2006.257.10:42:09.05#ibcon#read 3, iclass 17, count 2 2006.257.10:42:09.05#ibcon#about to read 4, iclass 17, count 2 2006.257.10:42:09.05#ibcon#read 4, iclass 17, count 2 2006.257.10:42:09.05#ibcon#about to read 5, iclass 17, count 2 2006.257.10:42:09.05#ibcon#read 5, iclass 17, count 2 2006.257.10:42:09.05#ibcon#about to read 6, iclass 17, count 2 2006.257.10:42:09.05#ibcon#read 6, iclass 17, count 2 2006.257.10:42:09.05#ibcon#end of sib2, iclass 17, count 2 2006.257.10:42:09.05#ibcon#*after write, iclass 17, count 2 2006.257.10:42:09.05#ibcon#*before return 0, iclass 17, count 2 2006.257.10:42:09.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:09.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:09.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.10:42:09.05#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:09.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:09.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:09.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:09.17#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:42:09.17#ibcon#first serial, iclass 17, count 0 2006.257.10:42:09.17#ibcon#enter sib2, iclass 17, count 0 2006.257.10:42:09.17#ibcon#flushed, iclass 17, count 0 2006.257.10:42:09.17#ibcon#about to write, iclass 17, count 0 2006.257.10:42:09.17#ibcon#wrote, iclass 17, count 0 2006.257.10:42:09.17#ibcon#about to read 3, iclass 17, count 0 2006.257.10:42:09.19#ibcon#read 3, iclass 17, count 0 2006.257.10:42:09.19#ibcon#about to read 4, iclass 17, count 0 2006.257.10:42:09.19#ibcon#read 4, iclass 17, count 0 2006.257.10:42:09.19#ibcon#about to read 5, iclass 17, count 0 2006.257.10:42:09.19#ibcon#read 5, iclass 17, count 0 2006.257.10:42:09.19#ibcon#about to read 6, iclass 17, count 0 2006.257.10:42:09.19#ibcon#read 6, iclass 17, count 0 2006.257.10:42:09.19#ibcon#end of sib2, iclass 17, count 0 2006.257.10:42:09.19#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:42:09.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:42:09.19#ibcon#[25=USB\r\n] 2006.257.10:42:09.19#ibcon#*before write, iclass 17, count 0 2006.257.10:42:09.19#ibcon#enter sib2, iclass 17, count 0 2006.257.10:42:09.19#ibcon#flushed, iclass 17, count 0 2006.257.10:42:09.19#ibcon#about to write, iclass 17, count 0 2006.257.10:42:09.19#ibcon#wrote, iclass 17, count 0 2006.257.10:42:09.19#ibcon#about to read 3, iclass 17, count 0 2006.257.10:42:09.22#ibcon#read 3, iclass 17, count 0 2006.257.10:42:09.22#ibcon#about to read 4, iclass 17, count 0 2006.257.10:42:09.22#ibcon#read 4, iclass 17, count 0 2006.257.10:42:09.22#ibcon#about to read 5, iclass 17, count 0 2006.257.10:42:09.22#ibcon#read 5, iclass 17, count 0 2006.257.10:42:09.22#ibcon#about to read 6, iclass 17, count 0 2006.257.10:42:09.22#ibcon#read 6, iclass 17, count 0 2006.257.10:42:09.22#ibcon#end of sib2, iclass 17, count 0 2006.257.10:42:09.22#ibcon#*after write, iclass 17, count 0 2006.257.10:42:09.22#ibcon#*before return 0, iclass 17, count 0 2006.257.10:42:09.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:09.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:09.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:42:09.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:42:09.22$vck44/valo=4,624.99 2006.257.10:42:09.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.10:42:09.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.10:42:09.22#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:09.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:09.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:09.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:09.22#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:42:09.22#ibcon#first serial, iclass 19, count 0 2006.257.10:42:09.22#ibcon#enter sib2, iclass 19, count 0 2006.257.10:42:09.22#ibcon#flushed, iclass 19, count 0 2006.257.10:42:09.22#ibcon#about to write, iclass 19, count 0 2006.257.10:42:09.22#ibcon#wrote, iclass 19, count 0 2006.257.10:42:09.22#ibcon#about to read 3, iclass 19, count 0 2006.257.10:42:09.24#ibcon#read 3, iclass 19, count 0 2006.257.10:42:09.24#ibcon#about to read 4, iclass 19, count 0 2006.257.10:42:09.24#ibcon#read 4, iclass 19, count 0 2006.257.10:42:09.24#ibcon#about to read 5, iclass 19, count 0 2006.257.10:42:09.24#ibcon#read 5, iclass 19, count 0 2006.257.10:42:09.24#ibcon#about to read 6, iclass 19, count 0 2006.257.10:42:09.24#ibcon#read 6, iclass 19, count 0 2006.257.10:42:09.24#ibcon#end of sib2, iclass 19, count 0 2006.257.10:42:09.24#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:42:09.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:42:09.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:42:09.24#ibcon#*before write, iclass 19, count 0 2006.257.10:42:09.24#ibcon#enter sib2, iclass 19, count 0 2006.257.10:42:09.24#ibcon#flushed, iclass 19, count 0 2006.257.10:42:09.24#ibcon#about to write, iclass 19, count 0 2006.257.10:42:09.24#ibcon#wrote, iclass 19, count 0 2006.257.10:42:09.24#ibcon#about to read 3, iclass 19, count 0 2006.257.10:42:09.28#ibcon#read 3, iclass 19, count 0 2006.257.10:42:09.28#ibcon#about to read 4, iclass 19, count 0 2006.257.10:42:09.28#ibcon#read 4, iclass 19, count 0 2006.257.10:42:09.28#ibcon#about to read 5, iclass 19, count 0 2006.257.10:42:09.28#ibcon#read 5, iclass 19, count 0 2006.257.10:42:09.28#ibcon#about to read 6, iclass 19, count 0 2006.257.10:42:09.28#ibcon#read 6, iclass 19, count 0 2006.257.10:42:09.28#ibcon#end of sib2, iclass 19, count 0 2006.257.10:42:09.28#ibcon#*after write, iclass 19, count 0 2006.257.10:42:09.28#ibcon#*before return 0, iclass 19, count 0 2006.257.10:42:09.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:09.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:09.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:42:09.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:42:09.28$vck44/va=4,7 2006.257.10:42:09.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.10:42:09.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.10:42:09.28#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:09.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:09.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:09.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:09.34#ibcon#enter wrdev, iclass 21, count 2 2006.257.10:42:09.34#ibcon#first serial, iclass 21, count 2 2006.257.10:42:09.34#ibcon#enter sib2, iclass 21, count 2 2006.257.10:42:09.34#ibcon#flushed, iclass 21, count 2 2006.257.10:42:09.34#ibcon#about to write, iclass 21, count 2 2006.257.10:42:09.34#ibcon#wrote, iclass 21, count 2 2006.257.10:42:09.34#ibcon#about to read 3, iclass 21, count 2 2006.257.10:42:09.36#ibcon#read 3, iclass 21, count 2 2006.257.10:42:09.36#ibcon#about to read 4, iclass 21, count 2 2006.257.10:42:09.36#ibcon#read 4, iclass 21, count 2 2006.257.10:42:09.36#ibcon#about to read 5, iclass 21, count 2 2006.257.10:42:09.36#ibcon#read 5, iclass 21, count 2 2006.257.10:42:09.36#ibcon#about to read 6, iclass 21, count 2 2006.257.10:42:09.36#ibcon#read 6, iclass 21, count 2 2006.257.10:42:09.36#ibcon#end of sib2, iclass 21, count 2 2006.257.10:42:09.36#ibcon#*mode == 0, iclass 21, count 2 2006.257.10:42:09.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.10:42:09.36#ibcon#[25=AT04-07\r\n] 2006.257.10:42:09.36#ibcon#*before write, iclass 21, count 2 2006.257.10:42:09.36#ibcon#enter sib2, iclass 21, count 2 2006.257.10:42:09.36#ibcon#flushed, iclass 21, count 2 2006.257.10:42:09.36#ibcon#about to write, iclass 21, count 2 2006.257.10:42:09.36#ibcon#wrote, iclass 21, count 2 2006.257.10:42:09.36#ibcon#about to read 3, iclass 21, count 2 2006.257.10:42:09.39#ibcon#read 3, iclass 21, count 2 2006.257.10:42:09.39#ibcon#about to read 4, iclass 21, count 2 2006.257.10:42:09.39#ibcon#read 4, iclass 21, count 2 2006.257.10:42:09.39#ibcon#about to read 5, iclass 21, count 2 2006.257.10:42:09.39#ibcon#read 5, iclass 21, count 2 2006.257.10:42:09.39#ibcon#about to read 6, iclass 21, count 2 2006.257.10:42:09.39#ibcon#read 6, iclass 21, count 2 2006.257.10:42:09.39#ibcon#end of sib2, iclass 21, count 2 2006.257.10:42:09.39#ibcon#*after write, iclass 21, count 2 2006.257.10:42:09.39#ibcon#*before return 0, iclass 21, count 2 2006.257.10:42:09.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:09.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:09.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.10:42:09.39#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:09.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:09.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:09.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:09.51#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:42:09.51#ibcon#first serial, iclass 21, count 0 2006.257.10:42:09.51#ibcon#enter sib2, iclass 21, count 0 2006.257.10:42:09.51#ibcon#flushed, iclass 21, count 0 2006.257.10:42:09.51#ibcon#about to write, iclass 21, count 0 2006.257.10:42:09.51#ibcon#wrote, iclass 21, count 0 2006.257.10:42:09.51#ibcon#about to read 3, iclass 21, count 0 2006.257.10:42:09.53#ibcon#read 3, iclass 21, count 0 2006.257.10:42:09.53#ibcon#about to read 4, iclass 21, count 0 2006.257.10:42:09.53#ibcon#read 4, iclass 21, count 0 2006.257.10:42:09.53#ibcon#about to read 5, iclass 21, count 0 2006.257.10:42:09.53#ibcon#read 5, iclass 21, count 0 2006.257.10:42:09.53#ibcon#about to read 6, iclass 21, count 0 2006.257.10:42:09.53#ibcon#read 6, iclass 21, count 0 2006.257.10:42:09.53#ibcon#end of sib2, iclass 21, count 0 2006.257.10:42:09.53#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:42:09.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:42:09.53#ibcon#[25=USB\r\n] 2006.257.10:42:09.53#ibcon#*before write, iclass 21, count 0 2006.257.10:42:09.53#ibcon#enter sib2, iclass 21, count 0 2006.257.10:42:09.53#ibcon#flushed, iclass 21, count 0 2006.257.10:42:09.53#ibcon#about to write, iclass 21, count 0 2006.257.10:42:09.53#ibcon#wrote, iclass 21, count 0 2006.257.10:42:09.53#ibcon#about to read 3, iclass 21, count 0 2006.257.10:42:09.56#ibcon#read 3, iclass 21, count 0 2006.257.10:42:09.56#ibcon#about to read 4, iclass 21, count 0 2006.257.10:42:09.56#ibcon#read 4, iclass 21, count 0 2006.257.10:42:09.56#ibcon#about to read 5, iclass 21, count 0 2006.257.10:42:09.56#ibcon#read 5, iclass 21, count 0 2006.257.10:42:09.56#ibcon#about to read 6, iclass 21, count 0 2006.257.10:42:09.56#ibcon#read 6, iclass 21, count 0 2006.257.10:42:09.56#ibcon#end of sib2, iclass 21, count 0 2006.257.10:42:09.56#ibcon#*after write, iclass 21, count 0 2006.257.10:42:09.56#ibcon#*before return 0, iclass 21, count 0 2006.257.10:42:09.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:09.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:09.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:42:09.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:42:09.56$vck44/valo=5,734.99 2006.257.10:42:09.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.10:42:09.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.10:42:09.56#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:09.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:09.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:09.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:09.56#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:42:09.56#ibcon#first serial, iclass 23, count 0 2006.257.10:42:09.56#ibcon#enter sib2, iclass 23, count 0 2006.257.10:42:09.56#ibcon#flushed, iclass 23, count 0 2006.257.10:42:09.56#ibcon#about to write, iclass 23, count 0 2006.257.10:42:09.56#ibcon#wrote, iclass 23, count 0 2006.257.10:42:09.56#ibcon#about to read 3, iclass 23, count 0 2006.257.10:42:09.58#ibcon#read 3, iclass 23, count 0 2006.257.10:42:09.58#ibcon#about to read 4, iclass 23, count 0 2006.257.10:42:09.58#ibcon#read 4, iclass 23, count 0 2006.257.10:42:09.58#ibcon#about to read 5, iclass 23, count 0 2006.257.10:42:09.58#ibcon#read 5, iclass 23, count 0 2006.257.10:42:09.58#ibcon#about to read 6, iclass 23, count 0 2006.257.10:42:09.58#ibcon#read 6, iclass 23, count 0 2006.257.10:42:09.58#ibcon#end of sib2, iclass 23, count 0 2006.257.10:42:09.58#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:42:09.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:42:09.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:42:09.58#ibcon#*before write, iclass 23, count 0 2006.257.10:42:09.58#ibcon#enter sib2, iclass 23, count 0 2006.257.10:42:09.58#ibcon#flushed, iclass 23, count 0 2006.257.10:42:09.58#ibcon#about to write, iclass 23, count 0 2006.257.10:42:09.58#ibcon#wrote, iclass 23, count 0 2006.257.10:42:09.58#ibcon#about to read 3, iclass 23, count 0 2006.257.10:42:09.62#ibcon#read 3, iclass 23, count 0 2006.257.10:42:09.62#ibcon#about to read 4, iclass 23, count 0 2006.257.10:42:09.62#ibcon#read 4, iclass 23, count 0 2006.257.10:42:09.62#ibcon#about to read 5, iclass 23, count 0 2006.257.10:42:09.62#ibcon#read 5, iclass 23, count 0 2006.257.10:42:09.62#ibcon#about to read 6, iclass 23, count 0 2006.257.10:42:09.62#ibcon#read 6, iclass 23, count 0 2006.257.10:42:09.62#ibcon#end of sib2, iclass 23, count 0 2006.257.10:42:09.62#ibcon#*after write, iclass 23, count 0 2006.257.10:42:09.62#ibcon#*before return 0, iclass 23, count 0 2006.257.10:42:09.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:09.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:09.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:42:09.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:42:09.62$vck44/va=5,4 2006.257.10:42:09.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.10:42:09.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.10:42:09.62#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:09.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:09.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:09.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:09.68#ibcon#enter wrdev, iclass 25, count 2 2006.257.10:42:09.68#ibcon#first serial, iclass 25, count 2 2006.257.10:42:09.68#ibcon#enter sib2, iclass 25, count 2 2006.257.10:42:09.68#ibcon#flushed, iclass 25, count 2 2006.257.10:42:09.68#ibcon#about to write, iclass 25, count 2 2006.257.10:42:09.68#ibcon#wrote, iclass 25, count 2 2006.257.10:42:09.68#ibcon#about to read 3, iclass 25, count 2 2006.257.10:42:09.70#ibcon#read 3, iclass 25, count 2 2006.257.10:42:09.70#ibcon#about to read 4, iclass 25, count 2 2006.257.10:42:09.70#ibcon#read 4, iclass 25, count 2 2006.257.10:42:09.70#ibcon#about to read 5, iclass 25, count 2 2006.257.10:42:09.70#ibcon#read 5, iclass 25, count 2 2006.257.10:42:09.70#ibcon#about to read 6, iclass 25, count 2 2006.257.10:42:09.70#ibcon#read 6, iclass 25, count 2 2006.257.10:42:09.70#ibcon#end of sib2, iclass 25, count 2 2006.257.10:42:09.70#ibcon#*mode == 0, iclass 25, count 2 2006.257.10:42:09.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.10:42:09.70#ibcon#[25=AT05-04\r\n] 2006.257.10:42:09.70#ibcon#*before write, iclass 25, count 2 2006.257.10:42:09.70#ibcon#enter sib2, iclass 25, count 2 2006.257.10:42:09.70#ibcon#flushed, iclass 25, count 2 2006.257.10:42:09.70#ibcon#about to write, iclass 25, count 2 2006.257.10:42:09.70#ibcon#wrote, iclass 25, count 2 2006.257.10:42:09.70#ibcon#about to read 3, iclass 25, count 2 2006.257.10:42:09.73#ibcon#read 3, iclass 25, count 2 2006.257.10:42:09.73#ibcon#about to read 4, iclass 25, count 2 2006.257.10:42:09.73#ibcon#read 4, iclass 25, count 2 2006.257.10:42:09.73#ibcon#about to read 5, iclass 25, count 2 2006.257.10:42:09.73#ibcon#read 5, iclass 25, count 2 2006.257.10:42:09.73#ibcon#about to read 6, iclass 25, count 2 2006.257.10:42:09.73#ibcon#read 6, iclass 25, count 2 2006.257.10:42:09.73#ibcon#end of sib2, iclass 25, count 2 2006.257.10:42:09.73#ibcon#*after write, iclass 25, count 2 2006.257.10:42:09.73#ibcon#*before return 0, iclass 25, count 2 2006.257.10:42:09.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:09.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:09.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.10:42:09.73#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:09.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:09.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:09.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:09.85#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:42:09.85#ibcon#first serial, iclass 25, count 0 2006.257.10:42:09.85#ibcon#enter sib2, iclass 25, count 0 2006.257.10:42:09.85#ibcon#flushed, iclass 25, count 0 2006.257.10:42:09.85#ibcon#about to write, iclass 25, count 0 2006.257.10:42:09.85#ibcon#wrote, iclass 25, count 0 2006.257.10:42:09.85#ibcon#about to read 3, iclass 25, count 0 2006.257.10:42:09.87#ibcon#read 3, iclass 25, count 0 2006.257.10:42:09.87#ibcon#about to read 4, iclass 25, count 0 2006.257.10:42:09.87#ibcon#read 4, iclass 25, count 0 2006.257.10:42:09.87#ibcon#about to read 5, iclass 25, count 0 2006.257.10:42:09.87#ibcon#read 5, iclass 25, count 0 2006.257.10:42:09.87#ibcon#about to read 6, iclass 25, count 0 2006.257.10:42:09.87#ibcon#read 6, iclass 25, count 0 2006.257.10:42:09.87#ibcon#end of sib2, iclass 25, count 0 2006.257.10:42:09.87#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:42:09.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:42:09.87#ibcon#[25=USB\r\n] 2006.257.10:42:09.87#ibcon#*before write, iclass 25, count 0 2006.257.10:42:09.87#ibcon#enter sib2, iclass 25, count 0 2006.257.10:42:09.87#ibcon#flushed, iclass 25, count 0 2006.257.10:42:09.87#ibcon#about to write, iclass 25, count 0 2006.257.10:42:09.87#ibcon#wrote, iclass 25, count 0 2006.257.10:42:09.87#ibcon#about to read 3, iclass 25, count 0 2006.257.10:42:09.90#ibcon#read 3, iclass 25, count 0 2006.257.10:42:09.90#ibcon#about to read 4, iclass 25, count 0 2006.257.10:42:09.90#ibcon#read 4, iclass 25, count 0 2006.257.10:42:09.90#ibcon#about to read 5, iclass 25, count 0 2006.257.10:42:09.90#ibcon#read 5, iclass 25, count 0 2006.257.10:42:09.90#ibcon#about to read 6, iclass 25, count 0 2006.257.10:42:09.90#ibcon#read 6, iclass 25, count 0 2006.257.10:42:09.90#ibcon#end of sib2, iclass 25, count 0 2006.257.10:42:09.90#ibcon#*after write, iclass 25, count 0 2006.257.10:42:09.90#ibcon#*before return 0, iclass 25, count 0 2006.257.10:42:09.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:09.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:09.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:42:09.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:42:09.90$vck44/valo=6,814.99 2006.257.10:42:09.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.10:42:09.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.10:42:09.90#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:09.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:09.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:09.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:09.90#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:42:09.90#ibcon#first serial, iclass 27, count 0 2006.257.10:42:09.90#ibcon#enter sib2, iclass 27, count 0 2006.257.10:42:09.90#ibcon#flushed, iclass 27, count 0 2006.257.10:42:09.90#ibcon#about to write, iclass 27, count 0 2006.257.10:42:09.90#ibcon#wrote, iclass 27, count 0 2006.257.10:42:09.90#ibcon#about to read 3, iclass 27, count 0 2006.257.10:42:09.92#ibcon#read 3, iclass 27, count 0 2006.257.10:42:09.92#ibcon#about to read 4, iclass 27, count 0 2006.257.10:42:09.92#ibcon#read 4, iclass 27, count 0 2006.257.10:42:09.92#ibcon#about to read 5, iclass 27, count 0 2006.257.10:42:09.92#ibcon#read 5, iclass 27, count 0 2006.257.10:42:09.92#ibcon#about to read 6, iclass 27, count 0 2006.257.10:42:09.92#ibcon#read 6, iclass 27, count 0 2006.257.10:42:09.92#ibcon#end of sib2, iclass 27, count 0 2006.257.10:42:09.92#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:42:09.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:42:09.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:42:09.92#ibcon#*before write, iclass 27, count 0 2006.257.10:42:09.92#ibcon#enter sib2, iclass 27, count 0 2006.257.10:42:09.92#ibcon#flushed, iclass 27, count 0 2006.257.10:42:09.92#ibcon#about to write, iclass 27, count 0 2006.257.10:42:09.92#ibcon#wrote, iclass 27, count 0 2006.257.10:42:09.92#ibcon#about to read 3, iclass 27, count 0 2006.257.10:42:09.96#ibcon#read 3, iclass 27, count 0 2006.257.10:42:09.96#ibcon#about to read 4, iclass 27, count 0 2006.257.10:42:09.96#ibcon#read 4, iclass 27, count 0 2006.257.10:42:09.96#ibcon#about to read 5, iclass 27, count 0 2006.257.10:42:09.96#ibcon#read 5, iclass 27, count 0 2006.257.10:42:09.96#ibcon#about to read 6, iclass 27, count 0 2006.257.10:42:09.96#ibcon#read 6, iclass 27, count 0 2006.257.10:42:09.96#ibcon#end of sib2, iclass 27, count 0 2006.257.10:42:09.96#ibcon#*after write, iclass 27, count 0 2006.257.10:42:09.96#ibcon#*before return 0, iclass 27, count 0 2006.257.10:42:09.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:09.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:09.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:42:09.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:42:09.96$vck44/va=6,4 2006.257.10:42:09.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.10:42:09.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.10:42:09.96#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:09.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:10.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:10.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:10.02#ibcon#enter wrdev, iclass 29, count 2 2006.257.10:42:10.02#ibcon#first serial, iclass 29, count 2 2006.257.10:42:10.02#ibcon#enter sib2, iclass 29, count 2 2006.257.10:42:10.02#ibcon#flushed, iclass 29, count 2 2006.257.10:42:10.02#ibcon#about to write, iclass 29, count 2 2006.257.10:42:10.02#ibcon#wrote, iclass 29, count 2 2006.257.10:42:10.02#ibcon#about to read 3, iclass 29, count 2 2006.257.10:42:10.04#ibcon#read 3, iclass 29, count 2 2006.257.10:42:10.04#ibcon#about to read 4, iclass 29, count 2 2006.257.10:42:10.04#ibcon#read 4, iclass 29, count 2 2006.257.10:42:10.04#ibcon#about to read 5, iclass 29, count 2 2006.257.10:42:10.04#ibcon#read 5, iclass 29, count 2 2006.257.10:42:10.04#ibcon#about to read 6, iclass 29, count 2 2006.257.10:42:10.04#ibcon#read 6, iclass 29, count 2 2006.257.10:42:10.04#ibcon#end of sib2, iclass 29, count 2 2006.257.10:42:10.04#ibcon#*mode == 0, iclass 29, count 2 2006.257.10:42:10.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.10:42:10.04#ibcon#[25=AT06-04\r\n] 2006.257.10:42:10.04#ibcon#*before write, iclass 29, count 2 2006.257.10:42:10.04#ibcon#enter sib2, iclass 29, count 2 2006.257.10:42:10.04#ibcon#flushed, iclass 29, count 2 2006.257.10:42:10.04#ibcon#about to write, iclass 29, count 2 2006.257.10:42:10.04#ibcon#wrote, iclass 29, count 2 2006.257.10:42:10.04#ibcon#about to read 3, iclass 29, count 2 2006.257.10:42:10.07#ibcon#read 3, iclass 29, count 2 2006.257.10:42:10.07#ibcon#about to read 4, iclass 29, count 2 2006.257.10:42:10.07#ibcon#read 4, iclass 29, count 2 2006.257.10:42:10.07#ibcon#about to read 5, iclass 29, count 2 2006.257.10:42:10.07#ibcon#read 5, iclass 29, count 2 2006.257.10:42:10.07#ibcon#about to read 6, iclass 29, count 2 2006.257.10:42:10.07#ibcon#read 6, iclass 29, count 2 2006.257.10:42:10.07#ibcon#end of sib2, iclass 29, count 2 2006.257.10:42:10.07#ibcon#*after write, iclass 29, count 2 2006.257.10:42:10.07#ibcon#*before return 0, iclass 29, count 2 2006.257.10:42:10.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:10.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:10.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.10:42:10.07#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:10.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:10.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:10.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:10.19#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:42:10.19#ibcon#first serial, iclass 29, count 0 2006.257.10:42:10.19#ibcon#enter sib2, iclass 29, count 0 2006.257.10:42:10.19#ibcon#flushed, iclass 29, count 0 2006.257.10:42:10.19#ibcon#about to write, iclass 29, count 0 2006.257.10:42:10.19#ibcon#wrote, iclass 29, count 0 2006.257.10:42:10.19#ibcon#about to read 3, iclass 29, count 0 2006.257.10:42:10.21#ibcon#read 3, iclass 29, count 0 2006.257.10:42:10.21#ibcon#about to read 4, iclass 29, count 0 2006.257.10:42:10.21#ibcon#read 4, iclass 29, count 0 2006.257.10:42:10.21#ibcon#about to read 5, iclass 29, count 0 2006.257.10:42:10.21#ibcon#read 5, iclass 29, count 0 2006.257.10:42:10.21#ibcon#about to read 6, iclass 29, count 0 2006.257.10:42:10.21#ibcon#read 6, iclass 29, count 0 2006.257.10:42:10.21#ibcon#end of sib2, iclass 29, count 0 2006.257.10:42:10.21#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:42:10.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:42:10.21#ibcon#[25=USB\r\n] 2006.257.10:42:10.21#ibcon#*before write, iclass 29, count 0 2006.257.10:42:10.21#ibcon#enter sib2, iclass 29, count 0 2006.257.10:42:10.21#ibcon#flushed, iclass 29, count 0 2006.257.10:42:10.21#ibcon#about to write, iclass 29, count 0 2006.257.10:42:10.21#ibcon#wrote, iclass 29, count 0 2006.257.10:42:10.21#ibcon#about to read 3, iclass 29, count 0 2006.257.10:42:10.24#ibcon#read 3, iclass 29, count 0 2006.257.10:42:10.24#ibcon#about to read 4, iclass 29, count 0 2006.257.10:42:10.24#ibcon#read 4, iclass 29, count 0 2006.257.10:42:10.24#ibcon#about to read 5, iclass 29, count 0 2006.257.10:42:10.24#ibcon#read 5, iclass 29, count 0 2006.257.10:42:10.24#ibcon#about to read 6, iclass 29, count 0 2006.257.10:42:10.24#ibcon#read 6, iclass 29, count 0 2006.257.10:42:10.24#ibcon#end of sib2, iclass 29, count 0 2006.257.10:42:10.24#ibcon#*after write, iclass 29, count 0 2006.257.10:42:10.24#ibcon#*before return 0, iclass 29, count 0 2006.257.10:42:10.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:10.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:10.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:42:10.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:42:10.24$vck44/valo=7,864.99 2006.257.10:42:10.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.10:42:10.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.10:42:10.24#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:10.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:10.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:10.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:10.24#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:42:10.24#ibcon#first serial, iclass 31, count 0 2006.257.10:42:10.24#ibcon#enter sib2, iclass 31, count 0 2006.257.10:42:10.24#ibcon#flushed, iclass 31, count 0 2006.257.10:42:10.24#ibcon#about to write, iclass 31, count 0 2006.257.10:42:10.24#ibcon#wrote, iclass 31, count 0 2006.257.10:42:10.24#ibcon#about to read 3, iclass 31, count 0 2006.257.10:42:10.26#ibcon#read 3, iclass 31, count 0 2006.257.10:42:10.26#ibcon#about to read 4, iclass 31, count 0 2006.257.10:42:10.26#ibcon#read 4, iclass 31, count 0 2006.257.10:42:10.26#ibcon#about to read 5, iclass 31, count 0 2006.257.10:42:10.26#ibcon#read 5, iclass 31, count 0 2006.257.10:42:10.26#ibcon#about to read 6, iclass 31, count 0 2006.257.10:42:10.26#ibcon#read 6, iclass 31, count 0 2006.257.10:42:10.26#ibcon#end of sib2, iclass 31, count 0 2006.257.10:42:10.26#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:42:10.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:42:10.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:42:10.26#ibcon#*before write, iclass 31, count 0 2006.257.10:42:10.26#ibcon#enter sib2, iclass 31, count 0 2006.257.10:42:10.26#ibcon#flushed, iclass 31, count 0 2006.257.10:42:10.26#ibcon#about to write, iclass 31, count 0 2006.257.10:42:10.26#ibcon#wrote, iclass 31, count 0 2006.257.10:42:10.26#ibcon#about to read 3, iclass 31, count 0 2006.257.10:42:10.30#ibcon#read 3, iclass 31, count 0 2006.257.10:42:10.30#ibcon#about to read 4, iclass 31, count 0 2006.257.10:42:10.30#ibcon#read 4, iclass 31, count 0 2006.257.10:42:10.30#ibcon#about to read 5, iclass 31, count 0 2006.257.10:42:10.30#ibcon#read 5, iclass 31, count 0 2006.257.10:42:10.30#ibcon#about to read 6, iclass 31, count 0 2006.257.10:42:10.30#ibcon#read 6, iclass 31, count 0 2006.257.10:42:10.30#ibcon#end of sib2, iclass 31, count 0 2006.257.10:42:10.30#ibcon#*after write, iclass 31, count 0 2006.257.10:42:10.30#ibcon#*before return 0, iclass 31, count 0 2006.257.10:42:10.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:10.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:10.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:42:10.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:42:10.30$vck44/va=7,4 2006.257.10:42:10.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.10:42:10.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.10:42:10.30#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:10.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:10.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:10.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:10.36#ibcon#enter wrdev, iclass 33, count 2 2006.257.10:42:10.36#ibcon#first serial, iclass 33, count 2 2006.257.10:42:10.36#ibcon#enter sib2, iclass 33, count 2 2006.257.10:42:10.36#ibcon#flushed, iclass 33, count 2 2006.257.10:42:10.36#ibcon#about to write, iclass 33, count 2 2006.257.10:42:10.36#ibcon#wrote, iclass 33, count 2 2006.257.10:42:10.36#ibcon#about to read 3, iclass 33, count 2 2006.257.10:42:10.38#ibcon#read 3, iclass 33, count 2 2006.257.10:42:10.38#ibcon#about to read 4, iclass 33, count 2 2006.257.10:42:10.38#ibcon#read 4, iclass 33, count 2 2006.257.10:42:10.38#ibcon#about to read 5, iclass 33, count 2 2006.257.10:42:10.38#ibcon#read 5, iclass 33, count 2 2006.257.10:42:10.38#ibcon#about to read 6, iclass 33, count 2 2006.257.10:42:10.38#ibcon#read 6, iclass 33, count 2 2006.257.10:42:10.38#ibcon#end of sib2, iclass 33, count 2 2006.257.10:42:10.38#ibcon#*mode == 0, iclass 33, count 2 2006.257.10:42:10.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.10:42:10.38#ibcon#[25=AT07-04\r\n] 2006.257.10:42:10.38#ibcon#*before write, iclass 33, count 2 2006.257.10:42:10.38#ibcon#enter sib2, iclass 33, count 2 2006.257.10:42:10.38#ibcon#flushed, iclass 33, count 2 2006.257.10:42:10.38#ibcon#about to write, iclass 33, count 2 2006.257.10:42:10.38#ibcon#wrote, iclass 33, count 2 2006.257.10:42:10.38#ibcon#about to read 3, iclass 33, count 2 2006.257.10:42:10.41#ibcon#read 3, iclass 33, count 2 2006.257.10:42:10.41#ibcon#about to read 4, iclass 33, count 2 2006.257.10:42:10.41#ibcon#read 4, iclass 33, count 2 2006.257.10:42:10.41#ibcon#about to read 5, iclass 33, count 2 2006.257.10:42:10.41#ibcon#read 5, iclass 33, count 2 2006.257.10:42:10.41#ibcon#about to read 6, iclass 33, count 2 2006.257.10:42:10.41#ibcon#read 6, iclass 33, count 2 2006.257.10:42:10.41#ibcon#end of sib2, iclass 33, count 2 2006.257.10:42:10.41#ibcon#*after write, iclass 33, count 2 2006.257.10:42:10.41#ibcon#*before return 0, iclass 33, count 2 2006.257.10:42:10.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:10.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:10.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.10:42:10.41#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:10.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:10.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:10.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:10.53#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:42:10.53#ibcon#first serial, iclass 33, count 0 2006.257.10:42:10.53#ibcon#enter sib2, iclass 33, count 0 2006.257.10:42:10.53#ibcon#flushed, iclass 33, count 0 2006.257.10:42:10.53#ibcon#about to write, iclass 33, count 0 2006.257.10:42:10.53#ibcon#wrote, iclass 33, count 0 2006.257.10:42:10.53#ibcon#about to read 3, iclass 33, count 0 2006.257.10:42:10.55#ibcon#read 3, iclass 33, count 0 2006.257.10:42:10.55#ibcon#about to read 4, iclass 33, count 0 2006.257.10:42:10.55#ibcon#read 4, iclass 33, count 0 2006.257.10:42:10.55#ibcon#about to read 5, iclass 33, count 0 2006.257.10:42:10.55#ibcon#read 5, iclass 33, count 0 2006.257.10:42:10.55#ibcon#about to read 6, iclass 33, count 0 2006.257.10:42:10.55#ibcon#read 6, iclass 33, count 0 2006.257.10:42:10.55#ibcon#end of sib2, iclass 33, count 0 2006.257.10:42:10.55#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:42:10.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:42:10.55#ibcon#[25=USB\r\n] 2006.257.10:42:10.55#ibcon#*before write, iclass 33, count 0 2006.257.10:42:10.55#ibcon#enter sib2, iclass 33, count 0 2006.257.10:42:10.55#ibcon#flushed, iclass 33, count 0 2006.257.10:42:10.55#ibcon#about to write, iclass 33, count 0 2006.257.10:42:10.55#ibcon#wrote, iclass 33, count 0 2006.257.10:42:10.55#ibcon#about to read 3, iclass 33, count 0 2006.257.10:42:10.58#ibcon#read 3, iclass 33, count 0 2006.257.10:42:10.58#ibcon#about to read 4, iclass 33, count 0 2006.257.10:42:10.58#ibcon#read 4, iclass 33, count 0 2006.257.10:42:10.58#ibcon#about to read 5, iclass 33, count 0 2006.257.10:42:10.58#ibcon#read 5, iclass 33, count 0 2006.257.10:42:10.58#ibcon#about to read 6, iclass 33, count 0 2006.257.10:42:10.58#ibcon#read 6, iclass 33, count 0 2006.257.10:42:10.58#ibcon#end of sib2, iclass 33, count 0 2006.257.10:42:10.58#ibcon#*after write, iclass 33, count 0 2006.257.10:42:10.58#ibcon#*before return 0, iclass 33, count 0 2006.257.10:42:10.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:10.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:10.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:42:10.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:42:10.58$vck44/valo=8,884.99 2006.257.10:42:10.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.10:42:10.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.10:42:10.58#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:10.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:10.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:10.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:10.58#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:42:10.58#ibcon#first serial, iclass 35, count 0 2006.257.10:42:10.58#ibcon#enter sib2, iclass 35, count 0 2006.257.10:42:10.58#ibcon#flushed, iclass 35, count 0 2006.257.10:42:10.58#ibcon#about to write, iclass 35, count 0 2006.257.10:42:10.58#ibcon#wrote, iclass 35, count 0 2006.257.10:42:10.58#ibcon#about to read 3, iclass 35, count 0 2006.257.10:42:10.60#ibcon#read 3, iclass 35, count 0 2006.257.10:42:10.60#ibcon#about to read 4, iclass 35, count 0 2006.257.10:42:10.60#ibcon#read 4, iclass 35, count 0 2006.257.10:42:10.60#ibcon#about to read 5, iclass 35, count 0 2006.257.10:42:10.60#ibcon#read 5, iclass 35, count 0 2006.257.10:42:10.60#ibcon#about to read 6, iclass 35, count 0 2006.257.10:42:10.60#ibcon#read 6, iclass 35, count 0 2006.257.10:42:10.60#ibcon#end of sib2, iclass 35, count 0 2006.257.10:42:10.60#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:42:10.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:42:10.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:42:10.60#ibcon#*before write, iclass 35, count 0 2006.257.10:42:10.60#ibcon#enter sib2, iclass 35, count 0 2006.257.10:42:10.60#ibcon#flushed, iclass 35, count 0 2006.257.10:42:10.60#ibcon#about to write, iclass 35, count 0 2006.257.10:42:10.60#ibcon#wrote, iclass 35, count 0 2006.257.10:42:10.60#ibcon#about to read 3, iclass 35, count 0 2006.257.10:42:10.64#ibcon#read 3, iclass 35, count 0 2006.257.10:42:10.64#ibcon#about to read 4, iclass 35, count 0 2006.257.10:42:10.64#ibcon#read 4, iclass 35, count 0 2006.257.10:42:10.64#ibcon#about to read 5, iclass 35, count 0 2006.257.10:42:10.64#ibcon#read 5, iclass 35, count 0 2006.257.10:42:10.64#ibcon#about to read 6, iclass 35, count 0 2006.257.10:42:10.64#ibcon#read 6, iclass 35, count 0 2006.257.10:42:10.64#ibcon#end of sib2, iclass 35, count 0 2006.257.10:42:10.64#ibcon#*after write, iclass 35, count 0 2006.257.10:42:10.64#ibcon#*before return 0, iclass 35, count 0 2006.257.10:42:10.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:10.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:10.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:42:10.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:42:10.64$vck44/va=8,4 2006.257.10:42:10.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.10:42:10.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.10:42:10.64#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:10.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:42:10.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:42:10.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:42:10.70#ibcon#enter wrdev, iclass 37, count 2 2006.257.10:42:10.70#ibcon#first serial, iclass 37, count 2 2006.257.10:42:10.70#ibcon#enter sib2, iclass 37, count 2 2006.257.10:42:10.70#ibcon#flushed, iclass 37, count 2 2006.257.10:42:10.70#ibcon#about to write, iclass 37, count 2 2006.257.10:42:10.70#ibcon#wrote, iclass 37, count 2 2006.257.10:42:10.70#ibcon#about to read 3, iclass 37, count 2 2006.257.10:42:10.72#ibcon#read 3, iclass 37, count 2 2006.257.10:42:10.72#ibcon#about to read 4, iclass 37, count 2 2006.257.10:42:10.72#ibcon#read 4, iclass 37, count 2 2006.257.10:42:10.72#ibcon#about to read 5, iclass 37, count 2 2006.257.10:42:10.72#ibcon#read 5, iclass 37, count 2 2006.257.10:42:10.72#ibcon#about to read 6, iclass 37, count 2 2006.257.10:42:10.72#ibcon#read 6, iclass 37, count 2 2006.257.10:42:10.72#ibcon#end of sib2, iclass 37, count 2 2006.257.10:42:10.72#ibcon#*mode == 0, iclass 37, count 2 2006.257.10:42:10.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.10:42:10.72#ibcon#[25=AT08-04\r\n] 2006.257.10:42:10.72#ibcon#*before write, iclass 37, count 2 2006.257.10:42:10.72#ibcon#enter sib2, iclass 37, count 2 2006.257.10:42:10.72#ibcon#flushed, iclass 37, count 2 2006.257.10:42:10.72#ibcon#about to write, iclass 37, count 2 2006.257.10:42:10.72#ibcon#wrote, iclass 37, count 2 2006.257.10:42:10.72#ibcon#about to read 3, iclass 37, count 2 2006.257.10:42:10.75#ibcon#read 3, iclass 37, count 2 2006.257.10:42:10.75#ibcon#about to read 4, iclass 37, count 2 2006.257.10:42:10.75#ibcon#read 4, iclass 37, count 2 2006.257.10:42:10.75#ibcon#about to read 5, iclass 37, count 2 2006.257.10:42:10.75#ibcon#read 5, iclass 37, count 2 2006.257.10:42:10.75#ibcon#about to read 6, iclass 37, count 2 2006.257.10:42:10.75#ibcon#read 6, iclass 37, count 2 2006.257.10:42:10.75#ibcon#end of sib2, iclass 37, count 2 2006.257.10:42:10.75#ibcon#*after write, iclass 37, count 2 2006.257.10:42:10.75#ibcon#*before return 0, iclass 37, count 2 2006.257.10:42:10.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:42:10.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.10:42:10.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.10:42:10.75#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:10.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:42:10.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:42:10.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:42:10.87#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:42:10.87#ibcon#first serial, iclass 37, count 0 2006.257.10:42:10.87#ibcon#enter sib2, iclass 37, count 0 2006.257.10:42:10.87#ibcon#flushed, iclass 37, count 0 2006.257.10:42:10.87#ibcon#about to write, iclass 37, count 0 2006.257.10:42:10.87#ibcon#wrote, iclass 37, count 0 2006.257.10:42:10.87#ibcon#about to read 3, iclass 37, count 0 2006.257.10:42:10.89#ibcon#read 3, iclass 37, count 0 2006.257.10:42:10.89#ibcon#about to read 4, iclass 37, count 0 2006.257.10:42:10.89#ibcon#read 4, iclass 37, count 0 2006.257.10:42:10.89#ibcon#about to read 5, iclass 37, count 0 2006.257.10:42:10.89#ibcon#read 5, iclass 37, count 0 2006.257.10:42:10.89#ibcon#about to read 6, iclass 37, count 0 2006.257.10:42:10.89#ibcon#read 6, iclass 37, count 0 2006.257.10:42:10.89#ibcon#end of sib2, iclass 37, count 0 2006.257.10:42:10.89#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:42:10.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:42:10.89#ibcon#[25=USB\r\n] 2006.257.10:42:10.89#ibcon#*before write, iclass 37, count 0 2006.257.10:42:10.89#ibcon#enter sib2, iclass 37, count 0 2006.257.10:42:10.89#ibcon#flushed, iclass 37, count 0 2006.257.10:42:10.89#ibcon#about to write, iclass 37, count 0 2006.257.10:42:10.89#ibcon#wrote, iclass 37, count 0 2006.257.10:42:10.89#ibcon#about to read 3, iclass 37, count 0 2006.257.10:42:10.92#ibcon#read 3, iclass 37, count 0 2006.257.10:42:10.92#ibcon#about to read 4, iclass 37, count 0 2006.257.10:42:10.92#ibcon#read 4, iclass 37, count 0 2006.257.10:42:10.92#ibcon#about to read 5, iclass 37, count 0 2006.257.10:42:10.92#ibcon#read 5, iclass 37, count 0 2006.257.10:42:10.92#ibcon#about to read 6, iclass 37, count 0 2006.257.10:42:10.92#ibcon#read 6, iclass 37, count 0 2006.257.10:42:10.92#ibcon#end of sib2, iclass 37, count 0 2006.257.10:42:10.92#ibcon#*after write, iclass 37, count 0 2006.257.10:42:10.92#ibcon#*before return 0, iclass 37, count 0 2006.257.10:42:10.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:42:10.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.10:42:10.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:42:10.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:42:10.92$vck44/vblo=1,629.99 2006.257.10:42:10.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.10:42:10.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.10:42:10.92#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:10.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:10.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:10.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:10.92#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:42:10.92#ibcon#first serial, iclass 39, count 0 2006.257.10:42:10.92#ibcon#enter sib2, iclass 39, count 0 2006.257.10:42:10.92#ibcon#flushed, iclass 39, count 0 2006.257.10:42:10.92#ibcon#about to write, iclass 39, count 0 2006.257.10:42:10.92#ibcon#wrote, iclass 39, count 0 2006.257.10:42:10.92#ibcon#about to read 3, iclass 39, count 0 2006.257.10:42:10.94#ibcon#read 3, iclass 39, count 0 2006.257.10:42:10.94#ibcon#about to read 4, iclass 39, count 0 2006.257.10:42:10.94#ibcon#read 4, iclass 39, count 0 2006.257.10:42:10.94#ibcon#about to read 5, iclass 39, count 0 2006.257.10:42:10.94#ibcon#read 5, iclass 39, count 0 2006.257.10:42:10.94#ibcon#about to read 6, iclass 39, count 0 2006.257.10:42:10.94#ibcon#read 6, iclass 39, count 0 2006.257.10:42:10.94#ibcon#end of sib2, iclass 39, count 0 2006.257.10:42:10.94#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:42:10.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:42:10.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:42:10.94#ibcon#*before write, iclass 39, count 0 2006.257.10:42:10.94#ibcon#enter sib2, iclass 39, count 0 2006.257.10:42:10.94#ibcon#flushed, iclass 39, count 0 2006.257.10:42:10.94#ibcon#about to write, iclass 39, count 0 2006.257.10:42:10.94#ibcon#wrote, iclass 39, count 0 2006.257.10:42:10.94#ibcon#about to read 3, iclass 39, count 0 2006.257.10:42:10.98#ibcon#read 3, iclass 39, count 0 2006.257.10:42:10.98#ibcon#about to read 4, iclass 39, count 0 2006.257.10:42:10.98#ibcon#read 4, iclass 39, count 0 2006.257.10:42:10.98#ibcon#about to read 5, iclass 39, count 0 2006.257.10:42:10.98#ibcon#read 5, iclass 39, count 0 2006.257.10:42:10.98#ibcon#about to read 6, iclass 39, count 0 2006.257.10:42:10.98#ibcon#read 6, iclass 39, count 0 2006.257.10:42:10.98#ibcon#end of sib2, iclass 39, count 0 2006.257.10:42:10.98#ibcon#*after write, iclass 39, count 0 2006.257.10:42:10.98#ibcon#*before return 0, iclass 39, count 0 2006.257.10:42:10.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:10.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.10:42:10.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:42:10.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:42:10.98$vck44/vb=1,4 2006.257.10:42:10.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.10:42:10.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.10:42:10.98#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:10.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:10.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:10.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:10.98#ibcon#enter wrdev, iclass 3, count 2 2006.257.10:42:10.98#ibcon#first serial, iclass 3, count 2 2006.257.10:42:10.98#ibcon#enter sib2, iclass 3, count 2 2006.257.10:42:10.98#ibcon#flushed, iclass 3, count 2 2006.257.10:42:10.98#ibcon#about to write, iclass 3, count 2 2006.257.10:42:10.98#ibcon#wrote, iclass 3, count 2 2006.257.10:42:10.98#ibcon#about to read 3, iclass 3, count 2 2006.257.10:42:11.00#ibcon#read 3, iclass 3, count 2 2006.257.10:42:11.00#ibcon#about to read 4, iclass 3, count 2 2006.257.10:42:11.00#ibcon#read 4, iclass 3, count 2 2006.257.10:42:11.00#ibcon#about to read 5, iclass 3, count 2 2006.257.10:42:11.00#ibcon#read 5, iclass 3, count 2 2006.257.10:42:11.00#ibcon#about to read 6, iclass 3, count 2 2006.257.10:42:11.00#ibcon#read 6, iclass 3, count 2 2006.257.10:42:11.00#ibcon#end of sib2, iclass 3, count 2 2006.257.10:42:11.00#ibcon#*mode == 0, iclass 3, count 2 2006.257.10:42:11.00#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.10:42:11.00#ibcon#[27=AT01-04\r\n] 2006.257.10:42:11.00#ibcon#*before write, iclass 3, count 2 2006.257.10:42:11.00#ibcon#enter sib2, iclass 3, count 2 2006.257.10:42:11.00#ibcon#flushed, iclass 3, count 2 2006.257.10:42:11.00#ibcon#about to write, iclass 3, count 2 2006.257.10:42:11.00#ibcon#wrote, iclass 3, count 2 2006.257.10:42:11.00#ibcon#about to read 3, iclass 3, count 2 2006.257.10:42:11.03#ibcon#read 3, iclass 3, count 2 2006.257.10:42:11.03#ibcon#about to read 4, iclass 3, count 2 2006.257.10:42:11.03#ibcon#read 4, iclass 3, count 2 2006.257.10:42:11.03#ibcon#about to read 5, iclass 3, count 2 2006.257.10:42:11.03#ibcon#read 5, iclass 3, count 2 2006.257.10:42:11.03#ibcon#about to read 6, iclass 3, count 2 2006.257.10:42:11.03#ibcon#read 6, iclass 3, count 2 2006.257.10:42:11.03#ibcon#end of sib2, iclass 3, count 2 2006.257.10:42:11.03#ibcon#*after write, iclass 3, count 2 2006.257.10:42:11.03#ibcon#*before return 0, iclass 3, count 2 2006.257.10:42:11.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:11.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.10:42:11.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.10:42:11.03#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:11.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:11.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:11.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:11.15#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:42:11.15#ibcon#first serial, iclass 3, count 0 2006.257.10:42:11.15#ibcon#enter sib2, iclass 3, count 0 2006.257.10:42:11.15#ibcon#flushed, iclass 3, count 0 2006.257.10:42:11.15#ibcon#about to write, iclass 3, count 0 2006.257.10:42:11.15#ibcon#wrote, iclass 3, count 0 2006.257.10:42:11.15#ibcon#about to read 3, iclass 3, count 0 2006.257.10:42:11.17#ibcon#read 3, iclass 3, count 0 2006.257.10:42:11.17#ibcon#about to read 4, iclass 3, count 0 2006.257.10:42:11.17#ibcon#read 4, iclass 3, count 0 2006.257.10:42:11.17#ibcon#about to read 5, iclass 3, count 0 2006.257.10:42:11.17#ibcon#read 5, iclass 3, count 0 2006.257.10:42:11.17#ibcon#about to read 6, iclass 3, count 0 2006.257.10:42:11.17#ibcon#read 6, iclass 3, count 0 2006.257.10:42:11.17#ibcon#end of sib2, iclass 3, count 0 2006.257.10:42:11.17#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:42:11.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:42:11.17#ibcon#[27=USB\r\n] 2006.257.10:42:11.17#ibcon#*before write, iclass 3, count 0 2006.257.10:42:11.17#ibcon#enter sib2, iclass 3, count 0 2006.257.10:42:11.17#ibcon#flushed, iclass 3, count 0 2006.257.10:42:11.17#ibcon#about to write, iclass 3, count 0 2006.257.10:42:11.17#ibcon#wrote, iclass 3, count 0 2006.257.10:42:11.17#ibcon#about to read 3, iclass 3, count 0 2006.257.10:42:11.20#ibcon#read 3, iclass 3, count 0 2006.257.10:42:11.20#ibcon#about to read 4, iclass 3, count 0 2006.257.10:42:11.20#ibcon#read 4, iclass 3, count 0 2006.257.10:42:11.20#ibcon#about to read 5, iclass 3, count 0 2006.257.10:42:11.20#ibcon#read 5, iclass 3, count 0 2006.257.10:42:11.20#ibcon#about to read 6, iclass 3, count 0 2006.257.10:42:11.20#ibcon#read 6, iclass 3, count 0 2006.257.10:42:11.20#ibcon#end of sib2, iclass 3, count 0 2006.257.10:42:11.20#ibcon#*after write, iclass 3, count 0 2006.257.10:42:11.20#ibcon#*before return 0, iclass 3, count 0 2006.257.10:42:11.20#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:11.20#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.10:42:11.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:42:11.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:42:11.20$vck44/vblo=2,634.99 2006.257.10:42:11.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.10:42:11.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.10:42:11.20#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:11.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:11.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:11.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:11.20#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:42:11.20#ibcon#first serial, iclass 5, count 0 2006.257.10:42:11.20#ibcon#enter sib2, iclass 5, count 0 2006.257.10:42:11.20#ibcon#flushed, iclass 5, count 0 2006.257.10:42:11.20#ibcon#about to write, iclass 5, count 0 2006.257.10:42:11.20#ibcon#wrote, iclass 5, count 0 2006.257.10:42:11.20#ibcon#about to read 3, iclass 5, count 0 2006.257.10:42:11.22#ibcon#read 3, iclass 5, count 0 2006.257.10:42:11.22#ibcon#about to read 4, iclass 5, count 0 2006.257.10:42:11.22#ibcon#read 4, iclass 5, count 0 2006.257.10:42:11.22#ibcon#about to read 5, iclass 5, count 0 2006.257.10:42:11.22#ibcon#read 5, iclass 5, count 0 2006.257.10:42:11.22#ibcon#about to read 6, iclass 5, count 0 2006.257.10:42:11.22#ibcon#read 6, iclass 5, count 0 2006.257.10:42:11.22#ibcon#end of sib2, iclass 5, count 0 2006.257.10:42:11.22#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:42:11.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:42:11.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:42:11.22#ibcon#*before write, iclass 5, count 0 2006.257.10:42:11.22#ibcon#enter sib2, iclass 5, count 0 2006.257.10:42:11.22#ibcon#flushed, iclass 5, count 0 2006.257.10:42:11.22#ibcon#about to write, iclass 5, count 0 2006.257.10:42:11.22#ibcon#wrote, iclass 5, count 0 2006.257.10:42:11.22#ibcon#about to read 3, iclass 5, count 0 2006.257.10:42:11.26#ibcon#read 3, iclass 5, count 0 2006.257.10:42:11.26#ibcon#about to read 4, iclass 5, count 0 2006.257.10:42:11.26#ibcon#read 4, iclass 5, count 0 2006.257.10:42:11.26#ibcon#about to read 5, iclass 5, count 0 2006.257.10:42:11.26#ibcon#read 5, iclass 5, count 0 2006.257.10:42:11.26#ibcon#about to read 6, iclass 5, count 0 2006.257.10:42:11.26#ibcon#read 6, iclass 5, count 0 2006.257.10:42:11.26#ibcon#end of sib2, iclass 5, count 0 2006.257.10:42:11.26#ibcon#*after write, iclass 5, count 0 2006.257.10:42:11.26#ibcon#*before return 0, iclass 5, count 0 2006.257.10:42:11.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:11.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.10:42:11.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:42:11.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:42:11.26$vck44/vb=2,5 2006.257.10:42:11.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.10:42:11.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.10:42:11.26#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:11.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:11.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:11.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:11.32#ibcon#enter wrdev, iclass 7, count 2 2006.257.10:42:11.32#ibcon#first serial, iclass 7, count 2 2006.257.10:42:11.32#ibcon#enter sib2, iclass 7, count 2 2006.257.10:42:11.32#ibcon#flushed, iclass 7, count 2 2006.257.10:42:11.32#ibcon#about to write, iclass 7, count 2 2006.257.10:42:11.32#ibcon#wrote, iclass 7, count 2 2006.257.10:42:11.32#ibcon#about to read 3, iclass 7, count 2 2006.257.10:42:11.34#ibcon#read 3, iclass 7, count 2 2006.257.10:42:11.34#ibcon#about to read 4, iclass 7, count 2 2006.257.10:42:11.34#ibcon#read 4, iclass 7, count 2 2006.257.10:42:11.34#ibcon#about to read 5, iclass 7, count 2 2006.257.10:42:11.34#ibcon#read 5, iclass 7, count 2 2006.257.10:42:11.34#ibcon#about to read 6, iclass 7, count 2 2006.257.10:42:11.34#ibcon#read 6, iclass 7, count 2 2006.257.10:42:11.34#ibcon#end of sib2, iclass 7, count 2 2006.257.10:42:11.34#ibcon#*mode == 0, iclass 7, count 2 2006.257.10:42:11.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.10:42:11.34#ibcon#[27=AT02-05\r\n] 2006.257.10:42:11.34#ibcon#*before write, iclass 7, count 2 2006.257.10:42:11.34#ibcon#enter sib2, iclass 7, count 2 2006.257.10:42:11.34#ibcon#flushed, iclass 7, count 2 2006.257.10:42:11.34#ibcon#about to write, iclass 7, count 2 2006.257.10:42:11.34#ibcon#wrote, iclass 7, count 2 2006.257.10:42:11.34#ibcon#about to read 3, iclass 7, count 2 2006.257.10:42:11.37#ibcon#read 3, iclass 7, count 2 2006.257.10:42:11.37#ibcon#about to read 4, iclass 7, count 2 2006.257.10:42:11.37#ibcon#read 4, iclass 7, count 2 2006.257.10:42:11.37#ibcon#about to read 5, iclass 7, count 2 2006.257.10:42:11.37#ibcon#read 5, iclass 7, count 2 2006.257.10:42:11.37#ibcon#about to read 6, iclass 7, count 2 2006.257.10:42:11.37#ibcon#read 6, iclass 7, count 2 2006.257.10:42:11.37#ibcon#end of sib2, iclass 7, count 2 2006.257.10:42:11.37#ibcon#*after write, iclass 7, count 2 2006.257.10:42:11.37#ibcon#*before return 0, iclass 7, count 2 2006.257.10:42:11.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:11.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.10:42:11.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.10:42:11.37#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:11.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:11.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:11.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:11.49#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:42:11.49#ibcon#first serial, iclass 7, count 0 2006.257.10:42:11.49#ibcon#enter sib2, iclass 7, count 0 2006.257.10:42:11.49#ibcon#flushed, iclass 7, count 0 2006.257.10:42:11.49#ibcon#about to write, iclass 7, count 0 2006.257.10:42:11.49#ibcon#wrote, iclass 7, count 0 2006.257.10:42:11.49#ibcon#about to read 3, iclass 7, count 0 2006.257.10:42:11.51#ibcon#read 3, iclass 7, count 0 2006.257.10:42:11.51#ibcon#about to read 4, iclass 7, count 0 2006.257.10:42:11.51#ibcon#read 4, iclass 7, count 0 2006.257.10:42:11.51#ibcon#about to read 5, iclass 7, count 0 2006.257.10:42:11.51#ibcon#read 5, iclass 7, count 0 2006.257.10:42:11.51#ibcon#about to read 6, iclass 7, count 0 2006.257.10:42:11.51#ibcon#read 6, iclass 7, count 0 2006.257.10:42:11.51#ibcon#end of sib2, iclass 7, count 0 2006.257.10:42:11.51#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:42:11.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:42:11.51#ibcon#[27=USB\r\n] 2006.257.10:42:11.51#ibcon#*before write, iclass 7, count 0 2006.257.10:42:11.51#ibcon#enter sib2, iclass 7, count 0 2006.257.10:42:11.51#ibcon#flushed, iclass 7, count 0 2006.257.10:42:11.51#ibcon#about to write, iclass 7, count 0 2006.257.10:42:11.51#ibcon#wrote, iclass 7, count 0 2006.257.10:42:11.51#ibcon#about to read 3, iclass 7, count 0 2006.257.10:42:11.54#ibcon#read 3, iclass 7, count 0 2006.257.10:42:11.54#ibcon#about to read 4, iclass 7, count 0 2006.257.10:42:11.54#ibcon#read 4, iclass 7, count 0 2006.257.10:42:11.54#ibcon#about to read 5, iclass 7, count 0 2006.257.10:42:11.54#ibcon#read 5, iclass 7, count 0 2006.257.10:42:11.54#ibcon#about to read 6, iclass 7, count 0 2006.257.10:42:11.54#ibcon#read 6, iclass 7, count 0 2006.257.10:42:11.54#ibcon#end of sib2, iclass 7, count 0 2006.257.10:42:11.54#ibcon#*after write, iclass 7, count 0 2006.257.10:42:11.54#ibcon#*before return 0, iclass 7, count 0 2006.257.10:42:11.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:11.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.10:42:11.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:42:11.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:42:11.54$vck44/vblo=3,649.99 2006.257.10:42:11.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.10:42:11.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.10:42:11.54#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:11.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:42:11.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:42:11.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:42:11.54#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:42:11.54#ibcon#first serial, iclass 11, count 0 2006.257.10:42:11.54#ibcon#enter sib2, iclass 11, count 0 2006.257.10:42:11.54#ibcon#flushed, iclass 11, count 0 2006.257.10:42:11.54#ibcon#about to write, iclass 11, count 0 2006.257.10:42:11.54#ibcon#wrote, iclass 11, count 0 2006.257.10:42:11.54#ibcon#about to read 3, iclass 11, count 0 2006.257.10:42:11.56#ibcon#read 3, iclass 11, count 0 2006.257.10:42:11.56#ibcon#about to read 4, iclass 11, count 0 2006.257.10:42:11.56#ibcon#read 4, iclass 11, count 0 2006.257.10:42:11.56#ibcon#about to read 5, iclass 11, count 0 2006.257.10:42:11.56#ibcon#read 5, iclass 11, count 0 2006.257.10:42:11.56#ibcon#about to read 6, iclass 11, count 0 2006.257.10:42:11.56#ibcon#read 6, iclass 11, count 0 2006.257.10:42:11.56#ibcon#end of sib2, iclass 11, count 0 2006.257.10:42:11.56#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:42:11.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:42:11.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:42:11.56#ibcon#*before write, iclass 11, count 0 2006.257.10:42:11.56#ibcon#enter sib2, iclass 11, count 0 2006.257.10:42:11.56#ibcon#flushed, iclass 11, count 0 2006.257.10:42:11.56#ibcon#about to write, iclass 11, count 0 2006.257.10:42:11.56#ibcon#wrote, iclass 11, count 0 2006.257.10:42:11.56#ibcon#about to read 3, iclass 11, count 0 2006.257.10:42:11.60#ibcon#read 3, iclass 11, count 0 2006.257.10:42:11.60#ibcon#about to read 4, iclass 11, count 0 2006.257.10:42:11.60#ibcon#read 4, iclass 11, count 0 2006.257.10:42:11.60#ibcon#about to read 5, iclass 11, count 0 2006.257.10:42:11.60#ibcon#read 5, iclass 11, count 0 2006.257.10:42:11.60#ibcon#about to read 6, iclass 11, count 0 2006.257.10:42:11.60#ibcon#read 6, iclass 11, count 0 2006.257.10:42:11.60#ibcon#end of sib2, iclass 11, count 0 2006.257.10:42:11.60#ibcon#*after write, iclass 11, count 0 2006.257.10:42:11.60#ibcon#*before return 0, iclass 11, count 0 2006.257.10:42:11.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:42:11.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.10:42:11.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:42:11.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:42:11.60$vck44/vb=3,4 2006.257.10:42:11.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.10:42:11.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.10:42:11.60#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:11.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:42:11.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:42:11.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:42:11.66#ibcon#enter wrdev, iclass 13, count 2 2006.257.10:42:11.66#ibcon#first serial, iclass 13, count 2 2006.257.10:42:11.66#ibcon#enter sib2, iclass 13, count 2 2006.257.10:42:11.66#ibcon#flushed, iclass 13, count 2 2006.257.10:42:11.66#ibcon#about to write, iclass 13, count 2 2006.257.10:42:11.66#ibcon#wrote, iclass 13, count 2 2006.257.10:42:11.66#ibcon#about to read 3, iclass 13, count 2 2006.257.10:42:11.68#ibcon#read 3, iclass 13, count 2 2006.257.10:42:11.68#ibcon#about to read 4, iclass 13, count 2 2006.257.10:42:11.68#ibcon#read 4, iclass 13, count 2 2006.257.10:42:11.68#ibcon#about to read 5, iclass 13, count 2 2006.257.10:42:11.68#ibcon#read 5, iclass 13, count 2 2006.257.10:42:11.68#ibcon#about to read 6, iclass 13, count 2 2006.257.10:42:11.68#ibcon#read 6, iclass 13, count 2 2006.257.10:42:11.68#ibcon#end of sib2, iclass 13, count 2 2006.257.10:42:11.68#ibcon#*mode == 0, iclass 13, count 2 2006.257.10:42:11.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.10:42:11.68#ibcon#[27=AT03-04\r\n] 2006.257.10:42:11.68#ibcon#*before write, iclass 13, count 2 2006.257.10:42:11.68#ibcon#enter sib2, iclass 13, count 2 2006.257.10:42:11.68#ibcon#flushed, iclass 13, count 2 2006.257.10:42:11.68#ibcon#about to write, iclass 13, count 2 2006.257.10:42:11.68#ibcon#wrote, iclass 13, count 2 2006.257.10:42:11.68#ibcon#about to read 3, iclass 13, count 2 2006.257.10:42:11.71#ibcon#read 3, iclass 13, count 2 2006.257.10:42:11.71#ibcon#about to read 4, iclass 13, count 2 2006.257.10:42:11.71#ibcon#read 4, iclass 13, count 2 2006.257.10:42:11.71#ibcon#about to read 5, iclass 13, count 2 2006.257.10:42:11.71#ibcon#read 5, iclass 13, count 2 2006.257.10:42:11.71#ibcon#about to read 6, iclass 13, count 2 2006.257.10:42:11.71#ibcon#read 6, iclass 13, count 2 2006.257.10:42:11.71#ibcon#end of sib2, iclass 13, count 2 2006.257.10:42:11.71#ibcon#*after write, iclass 13, count 2 2006.257.10:42:11.71#ibcon#*before return 0, iclass 13, count 2 2006.257.10:42:11.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:42:11.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.10:42:11.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.10:42:11.71#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:11.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:42:11.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:42:11.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:42:11.83#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:42:11.83#ibcon#first serial, iclass 13, count 0 2006.257.10:42:11.83#ibcon#enter sib2, iclass 13, count 0 2006.257.10:42:11.83#ibcon#flushed, iclass 13, count 0 2006.257.10:42:11.83#ibcon#about to write, iclass 13, count 0 2006.257.10:42:11.83#ibcon#wrote, iclass 13, count 0 2006.257.10:42:11.83#ibcon#about to read 3, iclass 13, count 0 2006.257.10:42:11.85#ibcon#read 3, iclass 13, count 0 2006.257.10:42:11.85#ibcon#about to read 4, iclass 13, count 0 2006.257.10:42:11.85#ibcon#read 4, iclass 13, count 0 2006.257.10:42:11.85#ibcon#about to read 5, iclass 13, count 0 2006.257.10:42:11.85#ibcon#read 5, iclass 13, count 0 2006.257.10:42:11.85#ibcon#about to read 6, iclass 13, count 0 2006.257.10:42:11.85#ibcon#read 6, iclass 13, count 0 2006.257.10:42:11.85#ibcon#end of sib2, iclass 13, count 0 2006.257.10:42:11.85#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:42:11.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:42:11.85#ibcon#[27=USB\r\n] 2006.257.10:42:11.85#ibcon#*before write, iclass 13, count 0 2006.257.10:42:11.85#ibcon#enter sib2, iclass 13, count 0 2006.257.10:42:11.85#ibcon#flushed, iclass 13, count 0 2006.257.10:42:11.85#ibcon#about to write, iclass 13, count 0 2006.257.10:42:11.85#ibcon#wrote, iclass 13, count 0 2006.257.10:42:11.85#ibcon#about to read 3, iclass 13, count 0 2006.257.10:42:11.88#ibcon#read 3, iclass 13, count 0 2006.257.10:42:11.88#ibcon#about to read 4, iclass 13, count 0 2006.257.10:42:11.88#ibcon#read 4, iclass 13, count 0 2006.257.10:42:11.88#ibcon#about to read 5, iclass 13, count 0 2006.257.10:42:11.88#ibcon#read 5, iclass 13, count 0 2006.257.10:42:11.88#ibcon#about to read 6, iclass 13, count 0 2006.257.10:42:11.88#ibcon#read 6, iclass 13, count 0 2006.257.10:42:11.88#ibcon#end of sib2, iclass 13, count 0 2006.257.10:42:11.88#ibcon#*after write, iclass 13, count 0 2006.257.10:42:11.88#ibcon#*before return 0, iclass 13, count 0 2006.257.10:42:11.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:42:11.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.10:42:11.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:42:11.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:42:11.88$vck44/vblo=4,679.99 2006.257.10:42:11.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.10:42:11.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.10:42:11.88#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:11.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:42:11.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:42:11.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:42:11.88#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:42:11.88#ibcon#first serial, iclass 15, count 0 2006.257.10:42:11.88#ibcon#enter sib2, iclass 15, count 0 2006.257.10:42:11.88#ibcon#flushed, iclass 15, count 0 2006.257.10:42:11.88#ibcon#about to write, iclass 15, count 0 2006.257.10:42:11.88#ibcon#wrote, iclass 15, count 0 2006.257.10:42:11.88#ibcon#about to read 3, iclass 15, count 0 2006.257.10:42:11.90#ibcon#read 3, iclass 15, count 0 2006.257.10:42:11.90#ibcon#about to read 4, iclass 15, count 0 2006.257.10:42:11.90#ibcon#read 4, iclass 15, count 0 2006.257.10:42:11.90#ibcon#about to read 5, iclass 15, count 0 2006.257.10:42:11.90#ibcon#read 5, iclass 15, count 0 2006.257.10:42:11.90#ibcon#about to read 6, iclass 15, count 0 2006.257.10:42:11.90#ibcon#read 6, iclass 15, count 0 2006.257.10:42:11.90#ibcon#end of sib2, iclass 15, count 0 2006.257.10:42:11.90#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:42:11.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:42:11.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:42:11.90#ibcon#*before write, iclass 15, count 0 2006.257.10:42:11.90#ibcon#enter sib2, iclass 15, count 0 2006.257.10:42:11.90#ibcon#flushed, iclass 15, count 0 2006.257.10:42:11.90#ibcon#about to write, iclass 15, count 0 2006.257.10:42:11.90#ibcon#wrote, iclass 15, count 0 2006.257.10:42:11.90#ibcon#about to read 3, iclass 15, count 0 2006.257.10:42:11.94#ibcon#read 3, iclass 15, count 0 2006.257.10:42:11.94#ibcon#about to read 4, iclass 15, count 0 2006.257.10:42:11.94#ibcon#read 4, iclass 15, count 0 2006.257.10:42:11.94#ibcon#about to read 5, iclass 15, count 0 2006.257.10:42:11.94#ibcon#read 5, iclass 15, count 0 2006.257.10:42:11.94#ibcon#about to read 6, iclass 15, count 0 2006.257.10:42:11.94#ibcon#read 6, iclass 15, count 0 2006.257.10:42:11.94#ibcon#end of sib2, iclass 15, count 0 2006.257.10:42:11.94#ibcon#*after write, iclass 15, count 0 2006.257.10:42:11.94#ibcon#*before return 0, iclass 15, count 0 2006.257.10:42:11.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:42:11.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.10:42:11.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:42:11.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:42:11.94$vck44/vb=4,5 2006.257.10:42:11.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.10:42:11.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.10:42:11.94#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:11.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:12.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:12.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:12.00#ibcon#enter wrdev, iclass 17, count 2 2006.257.10:42:12.00#ibcon#first serial, iclass 17, count 2 2006.257.10:42:12.00#ibcon#enter sib2, iclass 17, count 2 2006.257.10:42:12.00#ibcon#flushed, iclass 17, count 2 2006.257.10:42:12.00#ibcon#about to write, iclass 17, count 2 2006.257.10:42:12.00#ibcon#wrote, iclass 17, count 2 2006.257.10:42:12.00#ibcon#about to read 3, iclass 17, count 2 2006.257.10:42:12.02#ibcon#read 3, iclass 17, count 2 2006.257.10:42:12.02#ibcon#about to read 4, iclass 17, count 2 2006.257.10:42:12.02#ibcon#read 4, iclass 17, count 2 2006.257.10:42:12.02#ibcon#about to read 5, iclass 17, count 2 2006.257.10:42:12.02#ibcon#read 5, iclass 17, count 2 2006.257.10:42:12.02#ibcon#about to read 6, iclass 17, count 2 2006.257.10:42:12.02#ibcon#read 6, iclass 17, count 2 2006.257.10:42:12.02#ibcon#end of sib2, iclass 17, count 2 2006.257.10:42:12.02#ibcon#*mode == 0, iclass 17, count 2 2006.257.10:42:12.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.10:42:12.02#ibcon#[27=AT04-05\r\n] 2006.257.10:42:12.02#ibcon#*before write, iclass 17, count 2 2006.257.10:42:12.02#ibcon#enter sib2, iclass 17, count 2 2006.257.10:42:12.02#ibcon#flushed, iclass 17, count 2 2006.257.10:42:12.02#ibcon#about to write, iclass 17, count 2 2006.257.10:42:12.02#ibcon#wrote, iclass 17, count 2 2006.257.10:42:12.02#ibcon#about to read 3, iclass 17, count 2 2006.257.10:42:12.05#ibcon#read 3, iclass 17, count 2 2006.257.10:42:12.05#ibcon#about to read 4, iclass 17, count 2 2006.257.10:42:12.05#ibcon#read 4, iclass 17, count 2 2006.257.10:42:12.05#ibcon#about to read 5, iclass 17, count 2 2006.257.10:42:12.05#ibcon#read 5, iclass 17, count 2 2006.257.10:42:12.05#ibcon#about to read 6, iclass 17, count 2 2006.257.10:42:12.05#ibcon#read 6, iclass 17, count 2 2006.257.10:42:12.05#ibcon#end of sib2, iclass 17, count 2 2006.257.10:42:12.05#ibcon#*after write, iclass 17, count 2 2006.257.10:42:12.05#ibcon#*before return 0, iclass 17, count 2 2006.257.10:42:12.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:12.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.10:42:12.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.10:42:12.05#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:12.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:12.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:12.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:12.17#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:42:12.17#ibcon#first serial, iclass 17, count 0 2006.257.10:42:12.17#ibcon#enter sib2, iclass 17, count 0 2006.257.10:42:12.17#ibcon#flushed, iclass 17, count 0 2006.257.10:42:12.17#ibcon#about to write, iclass 17, count 0 2006.257.10:42:12.17#ibcon#wrote, iclass 17, count 0 2006.257.10:42:12.17#ibcon#about to read 3, iclass 17, count 0 2006.257.10:42:12.19#ibcon#read 3, iclass 17, count 0 2006.257.10:42:12.19#ibcon#about to read 4, iclass 17, count 0 2006.257.10:42:12.19#ibcon#read 4, iclass 17, count 0 2006.257.10:42:12.19#ibcon#about to read 5, iclass 17, count 0 2006.257.10:42:12.19#ibcon#read 5, iclass 17, count 0 2006.257.10:42:12.19#ibcon#about to read 6, iclass 17, count 0 2006.257.10:42:12.19#ibcon#read 6, iclass 17, count 0 2006.257.10:42:12.19#ibcon#end of sib2, iclass 17, count 0 2006.257.10:42:12.19#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:42:12.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:42:12.19#ibcon#[27=USB\r\n] 2006.257.10:42:12.19#ibcon#*before write, iclass 17, count 0 2006.257.10:42:12.19#ibcon#enter sib2, iclass 17, count 0 2006.257.10:42:12.19#ibcon#flushed, iclass 17, count 0 2006.257.10:42:12.19#ibcon#about to write, iclass 17, count 0 2006.257.10:42:12.19#ibcon#wrote, iclass 17, count 0 2006.257.10:42:12.19#ibcon#about to read 3, iclass 17, count 0 2006.257.10:42:12.22#ibcon#read 3, iclass 17, count 0 2006.257.10:42:12.22#ibcon#about to read 4, iclass 17, count 0 2006.257.10:42:12.22#ibcon#read 4, iclass 17, count 0 2006.257.10:42:12.22#ibcon#about to read 5, iclass 17, count 0 2006.257.10:42:12.22#ibcon#read 5, iclass 17, count 0 2006.257.10:42:12.22#ibcon#about to read 6, iclass 17, count 0 2006.257.10:42:12.22#ibcon#read 6, iclass 17, count 0 2006.257.10:42:12.22#ibcon#end of sib2, iclass 17, count 0 2006.257.10:42:12.22#ibcon#*after write, iclass 17, count 0 2006.257.10:42:12.22#ibcon#*before return 0, iclass 17, count 0 2006.257.10:42:12.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:12.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.10:42:12.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:42:12.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:42:12.22$vck44/vblo=5,709.99 2006.257.10:42:12.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.10:42:12.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.10:42:12.22#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:12.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:12.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:12.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:12.22#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:42:12.22#ibcon#first serial, iclass 19, count 0 2006.257.10:42:12.22#ibcon#enter sib2, iclass 19, count 0 2006.257.10:42:12.22#ibcon#flushed, iclass 19, count 0 2006.257.10:42:12.22#ibcon#about to write, iclass 19, count 0 2006.257.10:42:12.22#ibcon#wrote, iclass 19, count 0 2006.257.10:42:12.22#ibcon#about to read 3, iclass 19, count 0 2006.257.10:42:12.24#ibcon#read 3, iclass 19, count 0 2006.257.10:42:12.24#ibcon#about to read 4, iclass 19, count 0 2006.257.10:42:12.24#ibcon#read 4, iclass 19, count 0 2006.257.10:42:12.24#ibcon#about to read 5, iclass 19, count 0 2006.257.10:42:12.24#ibcon#read 5, iclass 19, count 0 2006.257.10:42:12.24#ibcon#about to read 6, iclass 19, count 0 2006.257.10:42:12.24#ibcon#read 6, iclass 19, count 0 2006.257.10:42:12.24#ibcon#end of sib2, iclass 19, count 0 2006.257.10:42:12.24#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:42:12.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:42:12.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:42:12.24#ibcon#*before write, iclass 19, count 0 2006.257.10:42:12.24#ibcon#enter sib2, iclass 19, count 0 2006.257.10:42:12.24#ibcon#flushed, iclass 19, count 0 2006.257.10:42:12.24#ibcon#about to write, iclass 19, count 0 2006.257.10:42:12.24#ibcon#wrote, iclass 19, count 0 2006.257.10:42:12.24#ibcon#about to read 3, iclass 19, count 0 2006.257.10:42:12.28#ibcon#read 3, iclass 19, count 0 2006.257.10:42:12.28#ibcon#about to read 4, iclass 19, count 0 2006.257.10:42:12.28#ibcon#read 4, iclass 19, count 0 2006.257.10:42:12.28#ibcon#about to read 5, iclass 19, count 0 2006.257.10:42:12.28#ibcon#read 5, iclass 19, count 0 2006.257.10:42:12.28#ibcon#about to read 6, iclass 19, count 0 2006.257.10:42:12.28#ibcon#read 6, iclass 19, count 0 2006.257.10:42:12.28#ibcon#end of sib2, iclass 19, count 0 2006.257.10:42:12.28#ibcon#*after write, iclass 19, count 0 2006.257.10:42:12.28#ibcon#*before return 0, iclass 19, count 0 2006.257.10:42:12.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:12.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.10:42:12.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:42:12.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:42:12.28$vck44/vb=5,4 2006.257.10:42:12.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.10:42:12.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.10:42:12.28#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:12.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:12.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:12.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:12.34#ibcon#enter wrdev, iclass 21, count 2 2006.257.10:42:12.34#ibcon#first serial, iclass 21, count 2 2006.257.10:42:12.34#ibcon#enter sib2, iclass 21, count 2 2006.257.10:42:12.34#ibcon#flushed, iclass 21, count 2 2006.257.10:42:12.34#ibcon#about to write, iclass 21, count 2 2006.257.10:42:12.34#ibcon#wrote, iclass 21, count 2 2006.257.10:42:12.34#ibcon#about to read 3, iclass 21, count 2 2006.257.10:42:12.36#ibcon#read 3, iclass 21, count 2 2006.257.10:42:12.36#ibcon#about to read 4, iclass 21, count 2 2006.257.10:42:12.36#ibcon#read 4, iclass 21, count 2 2006.257.10:42:12.36#ibcon#about to read 5, iclass 21, count 2 2006.257.10:42:12.36#ibcon#read 5, iclass 21, count 2 2006.257.10:42:12.36#ibcon#about to read 6, iclass 21, count 2 2006.257.10:42:12.36#ibcon#read 6, iclass 21, count 2 2006.257.10:42:12.36#ibcon#end of sib2, iclass 21, count 2 2006.257.10:42:12.36#ibcon#*mode == 0, iclass 21, count 2 2006.257.10:42:12.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.10:42:12.36#ibcon#[27=AT05-04\r\n] 2006.257.10:42:12.36#ibcon#*before write, iclass 21, count 2 2006.257.10:42:12.36#ibcon#enter sib2, iclass 21, count 2 2006.257.10:42:12.36#ibcon#flushed, iclass 21, count 2 2006.257.10:42:12.36#ibcon#about to write, iclass 21, count 2 2006.257.10:42:12.36#ibcon#wrote, iclass 21, count 2 2006.257.10:42:12.36#ibcon#about to read 3, iclass 21, count 2 2006.257.10:42:12.39#ibcon#read 3, iclass 21, count 2 2006.257.10:42:12.39#ibcon#about to read 4, iclass 21, count 2 2006.257.10:42:12.39#ibcon#read 4, iclass 21, count 2 2006.257.10:42:12.39#ibcon#about to read 5, iclass 21, count 2 2006.257.10:42:12.39#ibcon#read 5, iclass 21, count 2 2006.257.10:42:12.39#ibcon#about to read 6, iclass 21, count 2 2006.257.10:42:12.39#ibcon#read 6, iclass 21, count 2 2006.257.10:42:12.39#ibcon#end of sib2, iclass 21, count 2 2006.257.10:42:12.39#ibcon#*after write, iclass 21, count 2 2006.257.10:42:12.39#ibcon#*before return 0, iclass 21, count 2 2006.257.10:42:12.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:12.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.10:42:12.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.10:42:12.39#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:12.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:12.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:12.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:12.51#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:42:12.51#ibcon#first serial, iclass 21, count 0 2006.257.10:42:12.51#ibcon#enter sib2, iclass 21, count 0 2006.257.10:42:12.51#ibcon#flushed, iclass 21, count 0 2006.257.10:42:12.51#ibcon#about to write, iclass 21, count 0 2006.257.10:42:12.51#ibcon#wrote, iclass 21, count 0 2006.257.10:42:12.51#ibcon#about to read 3, iclass 21, count 0 2006.257.10:42:12.53#ibcon#read 3, iclass 21, count 0 2006.257.10:42:12.53#ibcon#about to read 4, iclass 21, count 0 2006.257.10:42:12.53#ibcon#read 4, iclass 21, count 0 2006.257.10:42:12.53#ibcon#about to read 5, iclass 21, count 0 2006.257.10:42:12.53#ibcon#read 5, iclass 21, count 0 2006.257.10:42:12.53#ibcon#about to read 6, iclass 21, count 0 2006.257.10:42:12.53#ibcon#read 6, iclass 21, count 0 2006.257.10:42:12.53#ibcon#end of sib2, iclass 21, count 0 2006.257.10:42:12.53#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:42:12.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:42:12.53#ibcon#[27=USB\r\n] 2006.257.10:42:12.53#ibcon#*before write, iclass 21, count 0 2006.257.10:42:12.53#ibcon#enter sib2, iclass 21, count 0 2006.257.10:42:12.53#ibcon#flushed, iclass 21, count 0 2006.257.10:42:12.53#ibcon#about to write, iclass 21, count 0 2006.257.10:42:12.53#ibcon#wrote, iclass 21, count 0 2006.257.10:42:12.53#ibcon#about to read 3, iclass 21, count 0 2006.257.10:42:12.56#ibcon#read 3, iclass 21, count 0 2006.257.10:42:12.56#ibcon#about to read 4, iclass 21, count 0 2006.257.10:42:12.56#ibcon#read 4, iclass 21, count 0 2006.257.10:42:12.56#ibcon#about to read 5, iclass 21, count 0 2006.257.10:42:12.56#ibcon#read 5, iclass 21, count 0 2006.257.10:42:12.56#ibcon#about to read 6, iclass 21, count 0 2006.257.10:42:12.56#ibcon#read 6, iclass 21, count 0 2006.257.10:42:12.56#ibcon#end of sib2, iclass 21, count 0 2006.257.10:42:12.56#ibcon#*after write, iclass 21, count 0 2006.257.10:42:12.56#ibcon#*before return 0, iclass 21, count 0 2006.257.10:42:12.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:12.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.10:42:12.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:42:12.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:42:12.56$vck44/vblo=6,719.99 2006.257.10:42:12.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.10:42:12.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.10:42:12.56#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:12.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:12.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:12.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:12.56#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:42:12.56#ibcon#first serial, iclass 23, count 0 2006.257.10:42:12.56#ibcon#enter sib2, iclass 23, count 0 2006.257.10:42:12.56#ibcon#flushed, iclass 23, count 0 2006.257.10:42:12.56#ibcon#about to write, iclass 23, count 0 2006.257.10:42:12.56#ibcon#wrote, iclass 23, count 0 2006.257.10:42:12.56#ibcon#about to read 3, iclass 23, count 0 2006.257.10:42:12.58#ibcon#read 3, iclass 23, count 0 2006.257.10:42:12.58#ibcon#about to read 4, iclass 23, count 0 2006.257.10:42:12.58#ibcon#read 4, iclass 23, count 0 2006.257.10:42:12.58#ibcon#about to read 5, iclass 23, count 0 2006.257.10:42:12.58#ibcon#read 5, iclass 23, count 0 2006.257.10:42:12.58#ibcon#about to read 6, iclass 23, count 0 2006.257.10:42:12.58#ibcon#read 6, iclass 23, count 0 2006.257.10:42:12.58#ibcon#end of sib2, iclass 23, count 0 2006.257.10:42:12.58#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:42:12.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:42:12.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:42:12.58#ibcon#*before write, iclass 23, count 0 2006.257.10:42:12.58#ibcon#enter sib2, iclass 23, count 0 2006.257.10:42:12.58#ibcon#flushed, iclass 23, count 0 2006.257.10:42:12.58#ibcon#about to write, iclass 23, count 0 2006.257.10:42:12.58#ibcon#wrote, iclass 23, count 0 2006.257.10:42:12.58#ibcon#about to read 3, iclass 23, count 0 2006.257.10:42:12.62#ibcon#read 3, iclass 23, count 0 2006.257.10:42:12.62#ibcon#about to read 4, iclass 23, count 0 2006.257.10:42:12.62#ibcon#read 4, iclass 23, count 0 2006.257.10:42:12.62#ibcon#about to read 5, iclass 23, count 0 2006.257.10:42:12.62#ibcon#read 5, iclass 23, count 0 2006.257.10:42:12.62#ibcon#about to read 6, iclass 23, count 0 2006.257.10:42:12.62#ibcon#read 6, iclass 23, count 0 2006.257.10:42:12.62#ibcon#end of sib2, iclass 23, count 0 2006.257.10:42:12.62#ibcon#*after write, iclass 23, count 0 2006.257.10:42:12.62#ibcon#*before return 0, iclass 23, count 0 2006.257.10:42:12.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:12.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.10:42:12.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:42:12.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:42:12.62$vck44/vb=6,4 2006.257.10:42:12.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.10:42:12.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.10:42:12.62#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:12.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:12.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:12.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:12.68#ibcon#enter wrdev, iclass 25, count 2 2006.257.10:42:12.68#ibcon#first serial, iclass 25, count 2 2006.257.10:42:12.68#ibcon#enter sib2, iclass 25, count 2 2006.257.10:42:12.68#ibcon#flushed, iclass 25, count 2 2006.257.10:42:12.68#ibcon#about to write, iclass 25, count 2 2006.257.10:42:12.68#ibcon#wrote, iclass 25, count 2 2006.257.10:42:12.68#ibcon#about to read 3, iclass 25, count 2 2006.257.10:42:12.70#ibcon#read 3, iclass 25, count 2 2006.257.10:42:12.70#ibcon#about to read 4, iclass 25, count 2 2006.257.10:42:12.70#ibcon#read 4, iclass 25, count 2 2006.257.10:42:12.70#ibcon#about to read 5, iclass 25, count 2 2006.257.10:42:12.70#ibcon#read 5, iclass 25, count 2 2006.257.10:42:12.70#ibcon#about to read 6, iclass 25, count 2 2006.257.10:42:12.70#ibcon#read 6, iclass 25, count 2 2006.257.10:42:12.70#ibcon#end of sib2, iclass 25, count 2 2006.257.10:42:12.70#ibcon#*mode == 0, iclass 25, count 2 2006.257.10:42:12.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.10:42:12.70#ibcon#[27=AT06-04\r\n] 2006.257.10:42:12.70#ibcon#*before write, iclass 25, count 2 2006.257.10:42:12.70#ibcon#enter sib2, iclass 25, count 2 2006.257.10:42:12.70#ibcon#flushed, iclass 25, count 2 2006.257.10:42:12.70#ibcon#about to write, iclass 25, count 2 2006.257.10:42:12.70#ibcon#wrote, iclass 25, count 2 2006.257.10:42:12.70#ibcon#about to read 3, iclass 25, count 2 2006.257.10:42:12.73#ibcon#read 3, iclass 25, count 2 2006.257.10:42:12.73#ibcon#about to read 4, iclass 25, count 2 2006.257.10:42:12.73#ibcon#read 4, iclass 25, count 2 2006.257.10:42:12.73#ibcon#about to read 5, iclass 25, count 2 2006.257.10:42:12.73#ibcon#read 5, iclass 25, count 2 2006.257.10:42:12.73#ibcon#about to read 6, iclass 25, count 2 2006.257.10:42:12.73#ibcon#read 6, iclass 25, count 2 2006.257.10:42:12.73#ibcon#end of sib2, iclass 25, count 2 2006.257.10:42:12.73#ibcon#*after write, iclass 25, count 2 2006.257.10:42:12.73#ibcon#*before return 0, iclass 25, count 2 2006.257.10:42:12.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:12.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.10:42:12.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.10:42:12.73#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:12.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:12.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:12.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:12.85#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:42:12.85#ibcon#first serial, iclass 25, count 0 2006.257.10:42:12.85#ibcon#enter sib2, iclass 25, count 0 2006.257.10:42:12.85#ibcon#flushed, iclass 25, count 0 2006.257.10:42:12.85#ibcon#about to write, iclass 25, count 0 2006.257.10:42:12.85#ibcon#wrote, iclass 25, count 0 2006.257.10:42:12.85#ibcon#about to read 3, iclass 25, count 0 2006.257.10:42:12.87#ibcon#read 3, iclass 25, count 0 2006.257.10:42:12.87#ibcon#about to read 4, iclass 25, count 0 2006.257.10:42:12.87#ibcon#read 4, iclass 25, count 0 2006.257.10:42:12.87#ibcon#about to read 5, iclass 25, count 0 2006.257.10:42:12.87#ibcon#read 5, iclass 25, count 0 2006.257.10:42:12.87#ibcon#about to read 6, iclass 25, count 0 2006.257.10:42:12.87#ibcon#read 6, iclass 25, count 0 2006.257.10:42:12.87#ibcon#end of sib2, iclass 25, count 0 2006.257.10:42:12.87#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:42:12.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:42:12.87#ibcon#[27=USB\r\n] 2006.257.10:42:12.87#ibcon#*before write, iclass 25, count 0 2006.257.10:42:12.87#ibcon#enter sib2, iclass 25, count 0 2006.257.10:42:12.87#ibcon#flushed, iclass 25, count 0 2006.257.10:42:12.87#ibcon#about to write, iclass 25, count 0 2006.257.10:42:12.87#ibcon#wrote, iclass 25, count 0 2006.257.10:42:12.87#ibcon#about to read 3, iclass 25, count 0 2006.257.10:42:12.90#ibcon#read 3, iclass 25, count 0 2006.257.10:42:12.90#ibcon#about to read 4, iclass 25, count 0 2006.257.10:42:12.90#ibcon#read 4, iclass 25, count 0 2006.257.10:42:12.90#ibcon#about to read 5, iclass 25, count 0 2006.257.10:42:12.90#ibcon#read 5, iclass 25, count 0 2006.257.10:42:12.90#ibcon#about to read 6, iclass 25, count 0 2006.257.10:42:12.90#ibcon#read 6, iclass 25, count 0 2006.257.10:42:12.90#ibcon#end of sib2, iclass 25, count 0 2006.257.10:42:12.90#ibcon#*after write, iclass 25, count 0 2006.257.10:42:12.90#ibcon#*before return 0, iclass 25, count 0 2006.257.10:42:12.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:12.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.10:42:12.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:42:12.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:42:12.90$vck44/vblo=7,734.99 2006.257.10:42:12.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.10:42:12.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.10:42:12.90#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:12.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:12.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:12.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:12.90#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:42:12.90#ibcon#first serial, iclass 27, count 0 2006.257.10:42:12.90#ibcon#enter sib2, iclass 27, count 0 2006.257.10:42:12.90#ibcon#flushed, iclass 27, count 0 2006.257.10:42:12.90#ibcon#about to write, iclass 27, count 0 2006.257.10:42:12.90#ibcon#wrote, iclass 27, count 0 2006.257.10:42:12.90#ibcon#about to read 3, iclass 27, count 0 2006.257.10:42:12.92#ibcon#read 3, iclass 27, count 0 2006.257.10:42:12.92#ibcon#about to read 4, iclass 27, count 0 2006.257.10:42:12.92#ibcon#read 4, iclass 27, count 0 2006.257.10:42:12.92#ibcon#about to read 5, iclass 27, count 0 2006.257.10:42:12.92#ibcon#read 5, iclass 27, count 0 2006.257.10:42:12.92#ibcon#about to read 6, iclass 27, count 0 2006.257.10:42:12.92#ibcon#read 6, iclass 27, count 0 2006.257.10:42:12.92#ibcon#end of sib2, iclass 27, count 0 2006.257.10:42:12.92#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:42:12.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:42:12.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:42:12.92#ibcon#*before write, iclass 27, count 0 2006.257.10:42:12.92#ibcon#enter sib2, iclass 27, count 0 2006.257.10:42:12.92#ibcon#flushed, iclass 27, count 0 2006.257.10:42:12.92#ibcon#about to write, iclass 27, count 0 2006.257.10:42:12.92#ibcon#wrote, iclass 27, count 0 2006.257.10:42:12.92#ibcon#about to read 3, iclass 27, count 0 2006.257.10:42:12.96#ibcon#read 3, iclass 27, count 0 2006.257.10:42:12.96#ibcon#about to read 4, iclass 27, count 0 2006.257.10:42:12.96#ibcon#read 4, iclass 27, count 0 2006.257.10:42:12.96#ibcon#about to read 5, iclass 27, count 0 2006.257.10:42:12.96#ibcon#read 5, iclass 27, count 0 2006.257.10:42:12.96#ibcon#about to read 6, iclass 27, count 0 2006.257.10:42:12.96#ibcon#read 6, iclass 27, count 0 2006.257.10:42:12.96#ibcon#end of sib2, iclass 27, count 0 2006.257.10:42:12.96#ibcon#*after write, iclass 27, count 0 2006.257.10:42:12.96#ibcon#*before return 0, iclass 27, count 0 2006.257.10:42:12.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:12.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.10:42:12.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:42:12.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:42:12.96$vck44/vb=7,4 2006.257.10:42:12.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.10:42:12.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.10:42:12.96#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:12.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:13.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:13.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:13.02#ibcon#enter wrdev, iclass 29, count 2 2006.257.10:42:13.02#ibcon#first serial, iclass 29, count 2 2006.257.10:42:13.02#ibcon#enter sib2, iclass 29, count 2 2006.257.10:42:13.02#ibcon#flushed, iclass 29, count 2 2006.257.10:42:13.02#ibcon#about to write, iclass 29, count 2 2006.257.10:42:13.02#ibcon#wrote, iclass 29, count 2 2006.257.10:42:13.02#ibcon#about to read 3, iclass 29, count 2 2006.257.10:42:13.04#ibcon#read 3, iclass 29, count 2 2006.257.10:42:13.04#ibcon#about to read 4, iclass 29, count 2 2006.257.10:42:13.04#ibcon#read 4, iclass 29, count 2 2006.257.10:42:13.04#ibcon#about to read 5, iclass 29, count 2 2006.257.10:42:13.04#ibcon#read 5, iclass 29, count 2 2006.257.10:42:13.04#ibcon#about to read 6, iclass 29, count 2 2006.257.10:42:13.04#ibcon#read 6, iclass 29, count 2 2006.257.10:42:13.04#ibcon#end of sib2, iclass 29, count 2 2006.257.10:42:13.04#ibcon#*mode == 0, iclass 29, count 2 2006.257.10:42:13.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.10:42:13.04#ibcon#[27=AT07-04\r\n] 2006.257.10:42:13.04#ibcon#*before write, iclass 29, count 2 2006.257.10:42:13.04#ibcon#enter sib2, iclass 29, count 2 2006.257.10:42:13.04#ibcon#flushed, iclass 29, count 2 2006.257.10:42:13.04#ibcon#about to write, iclass 29, count 2 2006.257.10:42:13.04#ibcon#wrote, iclass 29, count 2 2006.257.10:42:13.04#ibcon#about to read 3, iclass 29, count 2 2006.257.10:42:13.07#ibcon#read 3, iclass 29, count 2 2006.257.10:42:13.07#ibcon#about to read 4, iclass 29, count 2 2006.257.10:42:13.07#ibcon#read 4, iclass 29, count 2 2006.257.10:42:13.07#ibcon#about to read 5, iclass 29, count 2 2006.257.10:42:13.07#ibcon#read 5, iclass 29, count 2 2006.257.10:42:13.07#ibcon#about to read 6, iclass 29, count 2 2006.257.10:42:13.07#ibcon#read 6, iclass 29, count 2 2006.257.10:42:13.07#ibcon#end of sib2, iclass 29, count 2 2006.257.10:42:13.07#ibcon#*after write, iclass 29, count 2 2006.257.10:42:13.07#ibcon#*before return 0, iclass 29, count 2 2006.257.10:42:13.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:13.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.10:42:13.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.10:42:13.07#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:13.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:13.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:13.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:13.19#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:42:13.19#ibcon#first serial, iclass 29, count 0 2006.257.10:42:13.19#ibcon#enter sib2, iclass 29, count 0 2006.257.10:42:13.19#ibcon#flushed, iclass 29, count 0 2006.257.10:42:13.19#ibcon#about to write, iclass 29, count 0 2006.257.10:42:13.19#ibcon#wrote, iclass 29, count 0 2006.257.10:42:13.19#ibcon#about to read 3, iclass 29, count 0 2006.257.10:42:13.21#ibcon#read 3, iclass 29, count 0 2006.257.10:42:13.21#ibcon#about to read 4, iclass 29, count 0 2006.257.10:42:13.21#ibcon#read 4, iclass 29, count 0 2006.257.10:42:13.21#ibcon#about to read 5, iclass 29, count 0 2006.257.10:42:13.21#ibcon#read 5, iclass 29, count 0 2006.257.10:42:13.21#ibcon#about to read 6, iclass 29, count 0 2006.257.10:42:13.21#ibcon#read 6, iclass 29, count 0 2006.257.10:42:13.21#ibcon#end of sib2, iclass 29, count 0 2006.257.10:42:13.21#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:42:13.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:42:13.21#ibcon#[27=USB\r\n] 2006.257.10:42:13.21#ibcon#*before write, iclass 29, count 0 2006.257.10:42:13.21#ibcon#enter sib2, iclass 29, count 0 2006.257.10:42:13.21#ibcon#flushed, iclass 29, count 0 2006.257.10:42:13.21#ibcon#about to write, iclass 29, count 0 2006.257.10:42:13.21#ibcon#wrote, iclass 29, count 0 2006.257.10:42:13.21#ibcon#about to read 3, iclass 29, count 0 2006.257.10:42:13.24#ibcon#read 3, iclass 29, count 0 2006.257.10:42:13.24#ibcon#about to read 4, iclass 29, count 0 2006.257.10:42:13.24#ibcon#read 4, iclass 29, count 0 2006.257.10:42:13.24#ibcon#about to read 5, iclass 29, count 0 2006.257.10:42:13.24#ibcon#read 5, iclass 29, count 0 2006.257.10:42:13.24#ibcon#about to read 6, iclass 29, count 0 2006.257.10:42:13.24#ibcon#read 6, iclass 29, count 0 2006.257.10:42:13.24#ibcon#end of sib2, iclass 29, count 0 2006.257.10:42:13.24#ibcon#*after write, iclass 29, count 0 2006.257.10:42:13.24#ibcon#*before return 0, iclass 29, count 0 2006.257.10:42:13.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:13.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.10:42:13.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:42:13.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:42:13.24$vck44/vblo=8,744.99 2006.257.10:42:13.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.10:42:13.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.10:42:13.24#ibcon#ireg 17 cls_cnt 0 2006.257.10:42:13.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:13.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:13.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:13.24#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:42:13.24#ibcon#first serial, iclass 31, count 0 2006.257.10:42:13.24#ibcon#enter sib2, iclass 31, count 0 2006.257.10:42:13.24#ibcon#flushed, iclass 31, count 0 2006.257.10:42:13.24#ibcon#about to write, iclass 31, count 0 2006.257.10:42:13.24#ibcon#wrote, iclass 31, count 0 2006.257.10:42:13.24#ibcon#about to read 3, iclass 31, count 0 2006.257.10:42:13.26#ibcon#read 3, iclass 31, count 0 2006.257.10:42:13.26#ibcon#about to read 4, iclass 31, count 0 2006.257.10:42:13.26#ibcon#read 4, iclass 31, count 0 2006.257.10:42:13.26#ibcon#about to read 5, iclass 31, count 0 2006.257.10:42:13.26#ibcon#read 5, iclass 31, count 0 2006.257.10:42:13.26#ibcon#about to read 6, iclass 31, count 0 2006.257.10:42:13.26#ibcon#read 6, iclass 31, count 0 2006.257.10:42:13.26#ibcon#end of sib2, iclass 31, count 0 2006.257.10:42:13.26#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:42:13.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:42:13.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:42:13.26#ibcon#*before write, iclass 31, count 0 2006.257.10:42:13.26#ibcon#enter sib2, iclass 31, count 0 2006.257.10:42:13.26#ibcon#flushed, iclass 31, count 0 2006.257.10:42:13.26#ibcon#about to write, iclass 31, count 0 2006.257.10:42:13.26#ibcon#wrote, iclass 31, count 0 2006.257.10:42:13.26#ibcon#about to read 3, iclass 31, count 0 2006.257.10:42:13.30#ibcon#read 3, iclass 31, count 0 2006.257.10:42:13.30#ibcon#about to read 4, iclass 31, count 0 2006.257.10:42:13.30#ibcon#read 4, iclass 31, count 0 2006.257.10:42:13.30#ibcon#about to read 5, iclass 31, count 0 2006.257.10:42:13.30#ibcon#read 5, iclass 31, count 0 2006.257.10:42:13.30#ibcon#about to read 6, iclass 31, count 0 2006.257.10:42:13.30#ibcon#read 6, iclass 31, count 0 2006.257.10:42:13.30#ibcon#end of sib2, iclass 31, count 0 2006.257.10:42:13.30#ibcon#*after write, iclass 31, count 0 2006.257.10:42:13.30#ibcon#*before return 0, iclass 31, count 0 2006.257.10:42:13.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:13.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:42:13.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:42:13.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:42:13.30$vck44/vb=8,4 2006.257.10:42:13.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.10:42:13.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.10:42:13.30#ibcon#ireg 11 cls_cnt 2 2006.257.10:42:13.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:13.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:13.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:13.36#ibcon#enter wrdev, iclass 33, count 2 2006.257.10:42:13.36#ibcon#first serial, iclass 33, count 2 2006.257.10:42:13.36#ibcon#enter sib2, iclass 33, count 2 2006.257.10:42:13.36#ibcon#flushed, iclass 33, count 2 2006.257.10:42:13.36#ibcon#about to write, iclass 33, count 2 2006.257.10:42:13.36#ibcon#wrote, iclass 33, count 2 2006.257.10:42:13.36#ibcon#about to read 3, iclass 33, count 2 2006.257.10:42:13.38#ibcon#read 3, iclass 33, count 2 2006.257.10:42:13.38#ibcon#about to read 4, iclass 33, count 2 2006.257.10:42:13.38#ibcon#read 4, iclass 33, count 2 2006.257.10:42:13.38#ibcon#about to read 5, iclass 33, count 2 2006.257.10:42:13.38#ibcon#read 5, iclass 33, count 2 2006.257.10:42:13.38#ibcon#about to read 6, iclass 33, count 2 2006.257.10:42:13.38#ibcon#read 6, iclass 33, count 2 2006.257.10:42:13.38#ibcon#end of sib2, iclass 33, count 2 2006.257.10:42:13.38#ibcon#*mode == 0, iclass 33, count 2 2006.257.10:42:13.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.10:42:13.38#ibcon#[27=AT08-04\r\n] 2006.257.10:42:13.38#ibcon#*before write, iclass 33, count 2 2006.257.10:42:13.38#ibcon#enter sib2, iclass 33, count 2 2006.257.10:42:13.38#ibcon#flushed, iclass 33, count 2 2006.257.10:42:13.38#ibcon#about to write, iclass 33, count 2 2006.257.10:42:13.38#ibcon#wrote, iclass 33, count 2 2006.257.10:42:13.38#ibcon#about to read 3, iclass 33, count 2 2006.257.10:42:13.41#ibcon#read 3, iclass 33, count 2 2006.257.10:42:13.41#ibcon#about to read 4, iclass 33, count 2 2006.257.10:42:13.41#ibcon#read 4, iclass 33, count 2 2006.257.10:42:13.41#ibcon#about to read 5, iclass 33, count 2 2006.257.10:42:13.41#ibcon#read 5, iclass 33, count 2 2006.257.10:42:13.41#ibcon#about to read 6, iclass 33, count 2 2006.257.10:42:13.41#ibcon#read 6, iclass 33, count 2 2006.257.10:42:13.41#ibcon#end of sib2, iclass 33, count 2 2006.257.10:42:13.41#ibcon#*after write, iclass 33, count 2 2006.257.10:42:13.41#ibcon#*before return 0, iclass 33, count 2 2006.257.10:42:13.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:13.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.10:42:13.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.10:42:13.41#ibcon#ireg 7 cls_cnt 0 2006.257.10:42:13.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:13.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:13.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:13.53#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:42:13.53#ibcon#first serial, iclass 33, count 0 2006.257.10:42:13.53#ibcon#enter sib2, iclass 33, count 0 2006.257.10:42:13.53#ibcon#flushed, iclass 33, count 0 2006.257.10:42:13.53#ibcon#about to write, iclass 33, count 0 2006.257.10:42:13.53#ibcon#wrote, iclass 33, count 0 2006.257.10:42:13.53#ibcon#about to read 3, iclass 33, count 0 2006.257.10:42:13.55#ibcon#read 3, iclass 33, count 0 2006.257.10:42:13.55#ibcon#about to read 4, iclass 33, count 0 2006.257.10:42:13.55#ibcon#read 4, iclass 33, count 0 2006.257.10:42:13.55#ibcon#about to read 5, iclass 33, count 0 2006.257.10:42:13.55#ibcon#read 5, iclass 33, count 0 2006.257.10:42:13.55#ibcon#about to read 6, iclass 33, count 0 2006.257.10:42:13.55#ibcon#read 6, iclass 33, count 0 2006.257.10:42:13.55#ibcon#end of sib2, iclass 33, count 0 2006.257.10:42:13.55#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:42:13.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:42:13.55#ibcon#[27=USB\r\n] 2006.257.10:42:13.55#ibcon#*before write, iclass 33, count 0 2006.257.10:42:13.55#ibcon#enter sib2, iclass 33, count 0 2006.257.10:42:13.55#ibcon#flushed, iclass 33, count 0 2006.257.10:42:13.55#ibcon#about to write, iclass 33, count 0 2006.257.10:42:13.55#ibcon#wrote, iclass 33, count 0 2006.257.10:42:13.55#ibcon#about to read 3, iclass 33, count 0 2006.257.10:42:13.58#ibcon#read 3, iclass 33, count 0 2006.257.10:42:13.58#ibcon#about to read 4, iclass 33, count 0 2006.257.10:42:13.58#ibcon#read 4, iclass 33, count 0 2006.257.10:42:13.58#ibcon#about to read 5, iclass 33, count 0 2006.257.10:42:13.58#ibcon#read 5, iclass 33, count 0 2006.257.10:42:13.58#ibcon#about to read 6, iclass 33, count 0 2006.257.10:42:13.58#ibcon#read 6, iclass 33, count 0 2006.257.10:42:13.58#ibcon#end of sib2, iclass 33, count 0 2006.257.10:42:13.58#ibcon#*after write, iclass 33, count 0 2006.257.10:42:13.58#ibcon#*before return 0, iclass 33, count 0 2006.257.10:42:13.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:13.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.10:42:13.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:42:13.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:42:13.58$vck44/vabw=wide 2006.257.10:42:13.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.10:42:13.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.10:42:13.58#ibcon#ireg 8 cls_cnt 0 2006.257.10:42:13.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:13.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:13.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:13.58#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:42:13.58#ibcon#first serial, iclass 35, count 0 2006.257.10:42:13.58#ibcon#enter sib2, iclass 35, count 0 2006.257.10:42:13.58#ibcon#flushed, iclass 35, count 0 2006.257.10:42:13.58#ibcon#about to write, iclass 35, count 0 2006.257.10:42:13.58#ibcon#wrote, iclass 35, count 0 2006.257.10:42:13.58#ibcon#about to read 3, iclass 35, count 0 2006.257.10:42:13.60#ibcon#read 3, iclass 35, count 0 2006.257.10:42:13.60#ibcon#about to read 4, iclass 35, count 0 2006.257.10:42:13.60#ibcon#read 4, iclass 35, count 0 2006.257.10:42:13.60#ibcon#about to read 5, iclass 35, count 0 2006.257.10:42:13.60#ibcon#read 5, iclass 35, count 0 2006.257.10:42:13.60#ibcon#about to read 6, iclass 35, count 0 2006.257.10:42:13.60#ibcon#read 6, iclass 35, count 0 2006.257.10:42:13.60#ibcon#end of sib2, iclass 35, count 0 2006.257.10:42:13.60#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:42:13.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:42:13.60#ibcon#[25=BW32\r\n] 2006.257.10:42:13.60#ibcon#*before write, iclass 35, count 0 2006.257.10:42:13.60#ibcon#enter sib2, iclass 35, count 0 2006.257.10:42:13.60#ibcon#flushed, iclass 35, count 0 2006.257.10:42:13.60#ibcon#about to write, iclass 35, count 0 2006.257.10:42:13.60#ibcon#wrote, iclass 35, count 0 2006.257.10:42:13.60#ibcon#about to read 3, iclass 35, count 0 2006.257.10:42:13.63#ibcon#read 3, iclass 35, count 0 2006.257.10:42:13.63#ibcon#about to read 4, iclass 35, count 0 2006.257.10:42:13.63#ibcon#read 4, iclass 35, count 0 2006.257.10:42:13.63#ibcon#about to read 5, iclass 35, count 0 2006.257.10:42:13.63#ibcon#read 5, iclass 35, count 0 2006.257.10:42:13.63#ibcon#about to read 6, iclass 35, count 0 2006.257.10:42:13.63#ibcon#read 6, iclass 35, count 0 2006.257.10:42:13.63#ibcon#end of sib2, iclass 35, count 0 2006.257.10:42:13.63#ibcon#*after write, iclass 35, count 0 2006.257.10:42:13.63#ibcon#*before return 0, iclass 35, count 0 2006.257.10:42:13.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:13.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.10:42:13.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:42:13.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:42:13.63$vck44/vbbw=wide 2006.257.10:42:13.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.10:42:13.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.10:42:13.63#ibcon#ireg 8 cls_cnt 0 2006.257.10:42:13.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:42:13.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:42:13.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:42:13.70#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:42:13.70#ibcon#first serial, iclass 37, count 0 2006.257.10:42:13.70#ibcon#enter sib2, iclass 37, count 0 2006.257.10:42:13.70#ibcon#flushed, iclass 37, count 0 2006.257.10:42:13.70#ibcon#about to write, iclass 37, count 0 2006.257.10:42:13.70#ibcon#wrote, iclass 37, count 0 2006.257.10:42:13.70#ibcon#about to read 3, iclass 37, count 0 2006.257.10:42:13.72#ibcon#read 3, iclass 37, count 0 2006.257.10:42:13.72#ibcon#about to read 4, iclass 37, count 0 2006.257.10:42:13.72#ibcon#read 4, iclass 37, count 0 2006.257.10:42:13.72#ibcon#about to read 5, iclass 37, count 0 2006.257.10:42:13.72#ibcon#read 5, iclass 37, count 0 2006.257.10:42:13.72#ibcon#about to read 6, iclass 37, count 0 2006.257.10:42:13.72#ibcon#read 6, iclass 37, count 0 2006.257.10:42:13.72#ibcon#end of sib2, iclass 37, count 0 2006.257.10:42:13.72#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:42:13.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:42:13.72#ibcon#[27=BW32\r\n] 2006.257.10:42:13.72#ibcon#*before write, iclass 37, count 0 2006.257.10:42:13.72#ibcon#enter sib2, iclass 37, count 0 2006.257.10:42:13.72#ibcon#flushed, iclass 37, count 0 2006.257.10:42:13.72#ibcon#about to write, iclass 37, count 0 2006.257.10:42:13.72#ibcon#wrote, iclass 37, count 0 2006.257.10:42:13.72#ibcon#about to read 3, iclass 37, count 0 2006.257.10:42:13.75#ibcon#read 3, iclass 37, count 0 2006.257.10:42:13.75#ibcon#about to read 4, iclass 37, count 0 2006.257.10:42:13.75#ibcon#read 4, iclass 37, count 0 2006.257.10:42:13.75#ibcon#about to read 5, iclass 37, count 0 2006.257.10:42:13.75#ibcon#read 5, iclass 37, count 0 2006.257.10:42:13.75#ibcon#about to read 6, iclass 37, count 0 2006.257.10:42:13.75#ibcon#read 6, iclass 37, count 0 2006.257.10:42:13.75#ibcon#end of sib2, iclass 37, count 0 2006.257.10:42:13.75#ibcon#*after write, iclass 37, count 0 2006.257.10:42:13.75#ibcon#*before return 0, iclass 37, count 0 2006.257.10:42:13.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:42:13.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:42:13.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:42:13.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:42:13.75$setupk4/ifdk4 2006.257.10:42:13.75$ifdk4/lo= 2006.257.10:42:13.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:42:13.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:42:13.75$ifdk4/patch= 2006.257.10:42:13.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:42:13.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:42:13.75$setupk4/!*+20s 2006.257.10:42:19.03#abcon#<5=/14 1.6 4.4 18.84 961013.8\r\n> 2006.257.10:42:19.05#abcon#{5=INTERFACE CLEAR} 2006.257.10:42:19.11#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:42:22.14#trakl#Source acquired 2006.257.10:42:24.14#flagr#flagr/antenna,acquired 2006.257.10:42:28.26$setupk4/"tpicd 2006.257.10:42:28.26$setupk4/echo=off 2006.257.10:42:28.26$setupk4/xlog=off 2006.257.10:42:28.26:!2006.257.10:46:14 2006.257.10:46:14.00:preob 2006.257.10:46:14.14/onsource/TRACKING 2006.257.10:46:14.14:!2006.257.10:46:24 2006.257.10:46:24.00:"tape 2006.257.10:46:24.00:"st=record 2006.257.10:46:24.00:data_valid=on 2006.257.10:46:24.00:midob 2006.257.10:46:24.14/onsource/TRACKING 2006.257.10:46:24.14/wx/18.79,1014.0,96 2006.257.10:46:24.24/cable/+6.4781E-03 2006.257.10:46:25.33/va/01,08,usb,yes,31,33 2006.257.10:46:25.33/va/02,07,usb,yes,33,34 2006.257.10:46:25.33/va/03,08,usb,yes,30,31 2006.257.10:46:25.33/va/04,07,usb,yes,34,36 2006.257.10:46:25.33/va/05,04,usb,yes,31,31 2006.257.10:46:25.33/va/06,04,usb,yes,34,34 2006.257.10:46:25.33/va/07,04,usb,yes,35,35 2006.257.10:46:25.33/va/08,04,usb,yes,29,36 2006.257.10:46:25.56/valo/01,524.99,yes,locked 2006.257.10:46:25.56/valo/02,534.99,yes,locked 2006.257.10:46:25.56/valo/03,564.99,yes,locked 2006.257.10:46:25.56/valo/04,624.99,yes,locked 2006.257.10:46:25.56/valo/05,734.99,yes,locked 2006.257.10:46:25.56/valo/06,814.99,yes,locked 2006.257.10:46:25.56/valo/07,864.99,yes,locked 2006.257.10:46:25.56/valo/08,884.99,yes,locked 2006.257.10:46:26.65/vb/01,04,usb,yes,30,28 2006.257.10:46:26.65/vb/02,05,usb,yes,29,29 2006.257.10:46:26.65/vb/03,04,usb,yes,30,33 2006.257.10:46:26.65/vb/04,05,usb,yes,30,29 2006.257.10:46:26.65/vb/05,04,usb,yes,27,29 2006.257.10:46:26.65/vb/06,04,usb,yes,31,27 2006.257.10:46:26.65/vb/07,04,usb,yes,31,31 2006.257.10:46:26.65/vb/08,04,usb,yes,28,32 2006.257.10:46:26.89/vblo/01,629.99,yes,locked 2006.257.10:46:26.89/vblo/02,634.99,yes,locked 2006.257.10:46:26.89/vblo/03,649.99,yes,locked 2006.257.10:46:26.89/vblo/04,679.99,yes,locked 2006.257.10:46:26.89/vblo/05,709.99,yes,locked 2006.257.10:46:26.89/vblo/06,719.99,yes,locked 2006.257.10:46:26.89/vblo/07,734.99,yes,locked 2006.257.10:46:26.89/vblo/08,744.99,yes,locked 2006.257.10:46:27.04/vabw/8 2006.257.10:46:27.19/vbbw/8 2006.257.10:46:27.28/xfe/off,on,15.2 2006.257.10:46:27.66/ifatt/23,28,28,28 2006.257.10:46:28.08/fmout-gps/S +4.63E-07 2006.257.10:46:28.12:!2006.257.10:48:14 2006.257.10:48:14.00:data_valid=off 2006.257.10:48:14.00:"et 2006.257.10:48:14.00:!+3s 2006.257.10:48:17.02:"tape 2006.257.10:48:17.02:postob 2006.257.10:48:17.20/cable/+6.4766E-03 2006.257.10:48:17.20/wx/18.77,1014.0,96 2006.257.10:48:18.08/fmout-gps/S +4.64E-07 2006.257.10:48:18.08:scan_name=257-1052,jd0609,160 2006.257.10:48:18.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.257.10:48:19.13#flagr#flagr/antenna,new-source 2006.257.10:48:19.13:checkk5 2006.257.10:48:19.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:48:19.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:48:20.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:48:20.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:48:21.14/chk_obsdata//k5ts1/T2571046??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.257.10:48:21.53/chk_obsdata//k5ts2/T2571046??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.257.10:48:21.94/chk_obsdata//k5ts3/T2571046??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.257.10:48:22.34/chk_obsdata//k5ts4/T2571046??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.257.10:48:23.06/k5log//k5ts1_log_newline 2006.257.10:48:23.78/k5log//k5ts2_log_newline 2006.257.10:48:24.51/k5log//k5ts3_log_newline 2006.257.10:48:25.21/k5log//k5ts4_log_newline 2006.257.10:48:25.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:48:25.24:setupk4=1 2006.257.10:48:25.24$setupk4/echo=on 2006.257.10:48:25.24$setupk4/pcalon 2006.257.10:48:25.24$pcalon/"no phase cal control is implemented here 2006.257.10:48:25.24$setupk4/"tpicd=stop 2006.257.10:48:25.24$setupk4/"rec=synch_on 2006.257.10:48:25.24$setupk4/"rec_mode=128 2006.257.10:48:25.24$setupk4/!* 2006.257.10:48:25.24$setupk4/recpk4 2006.257.10:48:25.24$recpk4/recpatch= 2006.257.10:48:25.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:48:25.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:48:25.24$setupk4/vck44 2006.257.10:48:25.24$vck44/valo=1,524.99 2006.257.10:48:25.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.10:48:25.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.10:48:25.24#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:25.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:48:25.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:48:25.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:48:25.24#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:48:25.24#ibcon#first serial, iclass 7, count 0 2006.257.10:48:25.24#ibcon#enter sib2, iclass 7, count 0 2006.257.10:48:25.24#ibcon#flushed, iclass 7, count 0 2006.257.10:48:25.24#ibcon#about to write, iclass 7, count 0 2006.257.10:48:25.24#ibcon#wrote, iclass 7, count 0 2006.257.10:48:25.24#ibcon#about to read 3, iclass 7, count 0 2006.257.10:48:25.26#ibcon#read 3, iclass 7, count 0 2006.257.10:48:25.26#ibcon#about to read 4, iclass 7, count 0 2006.257.10:48:25.26#ibcon#read 4, iclass 7, count 0 2006.257.10:48:25.26#ibcon#about to read 5, iclass 7, count 0 2006.257.10:48:25.26#ibcon#read 5, iclass 7, count 0 2006.257.10:48:25.26#ibcon#about to read 6, iclass 7, count 0 2006.257.10:48:25.26#ibcon#read 6, iclass 7, count 0 2006.257.10:48:25.26#ibcon#end of sib2, iclass 7, count 0 2006.257.10:48:25.26#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:48:25.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:48:25.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:48:25.26#ibcon#*before write, iclass 7, count 0 2006.257.10:48:25.26#ibcon#enter sib2, iclass 7, count 0 2006.257.10:48:25.26#ibcon#flushed, iclass 7, count 0 2006.257.10:48:25.26#ibcon#about to write, iclass 7, count 0 2006.257.10:48:25.26#ibcon#wrote, iclass 7, count 0 2006.257.10:48:25.26#ibcon#about to read 3, iclass 7, count 0 2006.257.10:48:25.31#ibcon#read 3, iclass 7, count 0 2006.257.10:48:25.31#ibcon#about to read 4, iclass 7, count 0 2006.257.10:48:25.31#ibcon#read 4, iclass 7, count 0 2006.257.10:48:25.31#ibcon#about to read 5, iclass 7, count 0 2006.257.10:48:25.31#ibcon#read 5, iclass 7, count 0 2006.257.10:48:25.31#ibcon#about to read 6, iclass 7, count 0 2006.257.10:48:25.31#ibcon#read 6, iclass 7, count 0 2006.257.10:48:25.31#ibcon#end of sib2, iclass 7, count 0 2006.257.10:48:25.31#ibcon#*after write, iclass 7, count 0 2006.257.10:48:25.31#ibcon#*before return 0, iclass 7, count 0 2006.257.10:48:25.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:48:25.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:48:25.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:48:25.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:48:25.31$vck44/va=1,8 2006.257.10:48:25.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.10:48:25.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.10:48:25.31#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:25.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:25.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:25.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:25.31#ibcon#enter wrdev, iclass 12, count 2 2006.257.10:48:25.31#ibcon#first serial, iclass 12, count 2 2006.257.10:48:25.31#ibcon#enter sib2, iclass 12, count 2 2006.257.10:48:25.31#ibcon#flushed, iclass 12, count 2 2006.257.10:48:25.31#ibcon#about to write, iclass 12, count 2 2006.257.10:48:25.31#ibcon#wrote, iclass 12, count 2 2006.257.10:48:25.31#ibcon#about to read 3, iclass 12, count 2 2006.257.10:48:25.32#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:48:25.33#ibcon#read 3, iclass 12, count 2 2006.257.10:48:25.33#ibcon#about to read 4, iclass 12, count 2 2006.257.10:48:25.33#ibcon#read 4, iclass 12, count 2 2006.257.10:48:25.33#ibcon#about to read 5, iclass 12, count 2 2006.257.10:48:25.33#ibcon#read 5, iclass 12, count 2 2006.257.10:48:25.33#ibcon#about to read 6, iclass 12, count 2 2006.257.10:48:25.33#ibcon#read 6, iclass 12, count 2 2006.257.10:48:25.33#ibcon#end of sib2, iclass 12, count 2 2006.257.10:48:25.33#ibcon#*mode == 0, iclass 12, count 2 2006.257.10:48:25.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.10:48:25.33#ibcon#[25=AT01-08\r\n] 2006.257.10:48:25.33#ibcon#*before write, iclass 12, count 2 2006.257.10:48:25.33#ibcon#enter sib2, iclass 12, count 2 2006.257.10:48:25.33#ibcon#flushed, iclass 12, count 2 2006.257.10:48:25.33#ibcon#about to write, iclass 12, count 2 2006.257.10:48:25.33#ibcon#wrote, iclass 12, count 2 2006.257.10:48:25.33#ibcon#about to read 3, iclass 12, count 2 2006.257.10:48:25.36#ibcon#read 3, iclass 12, count 2 2006.257.10:48:25.36#ibcon#about to read 4, iclass 12, count 2 2006.257.10:48:25.36#ibcon#read 4, iclass 12, count 2 2006.257.10:48:25.36#ibcon#about to read 5, iclass 12, count 2 2006.257.10:48:25.36#ibcon#read 5, iclass 12, count 2 2006.257.10:48:25.36#ibcon#about to read 6, iclass 12, count 2 2006.257.10:48:25.36#ibcon#read 6, iclass 12, count 2 2006.257.10:48:25.36#ibcon#end of sib2, iclass 12, count 2 2006.257.10:48:25.36#ibcon#*after write, iclass 12, count 2 2006.257.10:48:25.36#ibcon#*before return 0, iclass 12, count 2 2006.257.10:48:25.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:25.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:25.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.10:48:25.36#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:25.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:25.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:25.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:25.48#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:48:25.48#ibcon#first serial, iclass 12, count 0 2006.257.10:48:25.48#ibcon#enter sib2, iclass 12, count 0 2006.257.10:48:25.48#ibcon#flushed, iclass 12, count 0 2006.257.10:48:25.48#ibcon#about to write, iclass 12, count 0 2006.257.10:48:25.48#ibcon#wrote, iclass 12, count 0 2006.257.10:48:25.48#ibcon#about to read 3, iclass 12, count 0 2006.257.10:48:25.50#ibcon#read 3, iclass 12, count 0 2006.257.10:48:25.50#ibcon#about to read 4, iclass 12, count 0 2006.257.10:48:25.50#ibcon#read 4, iclass 12, count 0 2006.257.10:48:25.50#ibcon#about to read 5, iclass 12, count 0 2006.257.10:48:25.50#ibcon#read 5, iclass 12, count 0 2006.257.10:48:25.50#ibcon#about to read 6, iclass 12, count 0 2006.257.10:48:25.50#ibcon#read 6, iclass 12, count 0 2006.257.10:48:25.50#ibcon#end of sib2, iclass 12, count 0 2006.257.10:48:25.50#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:48:25.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:48:25.50#ibcon#[25=USB\r\n] 2006.257.10:48:25.50#ibcon#*before write, iclass 12, count 0 2006.257.10:48:25.50#ibcon#enter sib2, iclass 12, count 0 2006.257.10:48:25.50#ibcon#flushed, iclass 12, count 0 2006.257.10:48:25.50#ibcon#about to write, iclass 12, count 0 2006.257.10:48:25.50#ibcon#wrote, iclass 12, count 0 2006.257.10:48:25.50#ibcon#about to read 3, iclass 12, count 0 2006.257.10:48:25.53#ibcon#read 3, iclass 12, count 0 2006.257.10:48:25.53#ibcon#about to read 4, iclass 12, count 0 2006.257.10:48:25.53#ibcon#read 4, iclass 12, count 0 2006.257.10:48:25.53#ibcon#about to read 5, iclass 12, count 0 2006.257.10:48:25.53#ibcon#read 5, iclass 12, count 0 2006.257.10:48:25.53#ibcon#about to read 6, iclass 12, count 0 2006.257.10:48:25.53#ibcon#read 6, iclass 12, count 0 2006.257.10:48:25.53#ibcon#end of sib2, iclass 12, count 0 2006.257.10:48:25.53#ibcon#*after write, iclass 12, count 0 2006.257.10:48:25.53#ibcon#*before return 0, iclass 12, count 0 2006.257.10:48:25.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:25.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:25.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:48:25.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:48:25.53$vck44/valo=2,534.99 2006.257.10:48:25.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.10:48:25.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.10:48:25.53#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:25.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:25.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:25.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:25.53#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:48:25.53#ibcon#first serial, iclass 14, count 0 2006.257.10:48:25.53#ibcon#enter sib2, iclass 14, count 0 2006.257.10:48:25.53#ibcon#flushed, iclass 14, count 0 2006.257.10:48:25.53#ibcon#about to write, iclass 14, count 0 2006.257.10:48:25.53#ibcon#wrote, iclass 14, count 0 2006.257.10:48:25.53#ibcon#about to read 3, iclass 14, count 0 2006.257.10:48:25.55#ibcon#read 3, iclass 14, count 0 2006.257.10:48:25.55#ibcon#about to read 4, iclass 14, count 0 2006.257.10:48:25.55#ibcon#read 4, iclass 14, count 0 2006.257.10:48:25.55#ibcon#about to read 5, iclass 14, count 0 2006.257.10:48:25.55#ibcon#read 5, iclass 14, count 0 2006.257.10:48:25.55#ibcon#about to read 6, iclass 14, count 0 2006.257.10:48:25.55#ibcon#read 6, iclass 14, count 0 2006.257.10:48:25.55#ibcon#end of sib2, iclass 14, count 0 2006.257.10:48:25.55#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:48:25.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:48:25.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:48:25.55#ibcon#*before write, iclass 14, count 0 2006.257.10:48:25.55#ibcon#enter sib2, iclass 14, count 0 2006.257.10:48:25.55#ibcon#flushed, iclass 14, count 0 2006.257.10:48:25.55#ibcon#about to write, iclass 14, count 0 2006.257.10:48:25.55#ibcon#wrote, iclass 14, count 0 2006.257.10:48:25.55#ibcon#about to read 3, iclass 14, count 0 2006.257.10:48:25.59#ibcon#read 3, iclass 14, count 0 2006.257.10:48:25.59#ibcon#about to read 4, iclass 14, count 0 2006.257.10:48:25.59#ibcon#read 4, iclass 14, count 0 2006.257.10:48:25.59#ibcon#about to read 5, iclass 14, count 0 2006.257.10:48:25.59#ibcon#read 5, iclass 14, count 0 2006.257.10:48:25.59#ibcon#about to read 6, iclass 14, count 0 2006.257.10:48:25.59#ibcon#read 6, iclass 14, count 0 2006.257.10:48:25.59#ibcon#end of sib2, iclass 14, count 0 2006.257.10:48:25.59#ibcon#*after write, iclass 14, count 0 2006.257.10:48:25.59#ibcon#*before return 0, iclass 14, count 0 2006.257.10:48:25.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:25.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:25.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:48:25.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:48:25.59$vck44/va=2,7 2006.257.10:48:25.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.10:48:25.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.10:48:25.59#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:25.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:25.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:25.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:25.65#ibcon#enter wrdev, iclass 16, count 2 2006.257.10:48:25.65#ibcon#first serial, iclass 16, count 2 2006.257.10:48:25.65#ibcon#enter sib2, iclass 16, count 2 2006.257.10:48:25.65#ibcon#flushed, iclass 16, count 2 2006.257.10:48:25.65#ibcon#about to write, iclass 16, count 2 2006.257.10:48:25.65#ibcon#wrote, iclass 16, count 2 2006.257.10:48:25.65#ibcon#about to read 3, iclass 16, count 2 2006.257.10:48:25.67#ibcon#read 3, iclass 16, count 2 2006.257.10:48:25.67#ibcon#about to read 4, iclass 16, count 2 2006.257.10:48:25.67#ibcon#read 4, iclass 16, count 2 2006.257.10:48:25.67#ibcon#about to read 5, iclass 16, count 2 2006.257.10:48:25.67#ibcon#read 5, iclass 16, count 2 2006.257.10:48:25.67#ibcon#about to read 6, iclass 16, count 2 2006.257.10:48:25.67#ibcon#read 6, iclass 16, count 2 2006.257.10:48:25.67#ibcon#end of sib2, iclass 16, count 2 2006.257.10:48:25.67#ibcon#*mode == 0, iclass 16, count 2 2006.257.10:48:25.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.10:48:25.67#ibcon#[25=AT02-07\r\n] 2006.257.10:48:25.67#ibcon#*before write, iclass 16, count 2 2006.257.10:48:25.67#ibcon#enter sib2, iclass 16, count 2 2006.257.10:48:25.67#ibcon#flushed, iclass 16, count 2 2006.257.10:48:25.67#ibcon#about to write, iclass 16, count 2 2006.257.10:48:25.67#ibcon#wrote, iclass 16, count 2 2006.257.10:48:25.67#ibcon#about to read 3, iclass 16, count 2 2006.257.10:48:25.70#ibcon#read 3, iclass 16, count 2 2006.257.10:48:25.70#ibcon#about to read 4, iclass 16, count 2 2006.257.10:48:25.70#ibcon#read 4, iclass 16, count 2 2006.257.10:48:25.70#ibcon#about to read 5, iclass 16, count 2 2006.257.10:48:25.70#ibcon#read 5, iclass 16, count 2 2006.257.10:48:25.70#ibcon#about to read 6, iclass 16, count 2 2006.257.10:48:25.70#ibcon#read 6, iclass 16, count 2 2006.257.10:48:25.70#ibcon#end of sib2, iclass 16, count 2 2006.257.10:48:25.70#ibcon#*after write, iclass 16, count 2 2006.257.10:48:25.70#ibcon#*before return 0, iclass 16, count 2 2006.257.10:48:25.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:25.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:25.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.10:48:25.70#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:25.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:25.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:25.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:25.82#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:48:25.82#ibcon#first serial, iclass 16, count 0 2006.257.10:48:25.82#ibcon#enter sib2, iclass 16, count 0 2006.257.10:48:25.82#ibcon#flushed, iclass 16, count 0 2006.257.10:48:25.82#ibcon#about to write, iclass 16, count 0 2006.257.10:48:25.82#ibcon#wrote, iclass 16, count 0 2006.257.10:48:25.82#ibcon#about to read 3, iclass 16, count 0 2006.257.10:48:25.84#ibcon#read 3, iclass 16, count 0 2006.257.10:48:25.84#ibcon#about to read 4, iclass 16, count 0 2006.257.10:48:25.84#ibcon#read 4, iclass 16, count 0 2006.257.10:48:25.84#ibcon#about to read 5, iclass 16, count 0 2006.257.10:48:25.84#ibcon#read 5, iclass 16, count 0 2006.257.10:48:25.84#ibcon#about to read 6, iclass 16, count 0 2006.257.10:48:25.84#ibcon#read 6, iclass 16, count 0 2006.257.10:48:25.84#ibcon#end of sib2, iclass 16, count 0 2006.257.10:48:25.84#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:48:25.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:48:25.84#ibcon#[25=USB\r\n] 2006.257.10:48:25.84#ibcon#*before write, iclass 16, count 0 2006.257.10:48:25.84#ibcon#enter sib2, iclass 16, count 0 2006.257.10:48:25.84#ibcon#flushed, iclass 16, count 0 2006.257.10:48:25.84#ibcon#about to write, iclass 16, count 0 2006.257.10:48:25.84#ibcon#wrote, iclass 16, count 0 2006.257.10:48:25.84#ibcon#about to read 3, iclass 16, count 0 2006.257.10:48:25.87#ibcon#read 3, iclass 16, count 0 2006.257.10:48:25.87#ibcon#about to read 4, iclass 16, count 0 2006.257.10:48:25.87#ibcon#read 4, iclass 16, count 0 2006.257.10:48:25.87#ibcon#about to read 5, iclass 16, count 0 2006.257.10:48:25.87#ibcon#read 5, iclass 16, count 0 2006.257.10:48:25.87#ibcon#about to read 6, iclass 16, count 0 2006.257.10:48:25.87#ibcon#read 6, iclass 16, count 0 2006.257.10:48:25.87#ibcon#end of sib2, iclass 16, count 0 2006.257.10:48:25.87#ibcon#*after write, iclass 16, count 0 2006.257.10:48:25.87#ibcon#*before return 0, iclass 16, count 0 2006.257.10:48:25.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:25.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:25.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:48:25.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:48:25.87$vck44/valo=3,564.99 2006.257.10:48:25.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.10:48:25.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.10:48:25.87#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:25.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:25.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:25.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:25.87#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:48:25.87#ibcon#first serial, iclass 18, count 0 2006.257.10:48:25.87#ibcon#enter sib2, iclass 18, count 0 2006.257.10:48:25.87#ibcon#flushed, iclass 18, count 0 2006.257.10:48:25.87#ibcon#about to write, iclass 18, count 0 2006.257.10:48:25.87#ibcon#wrote, iclass 18, count 0 2006.257.10:48:25.87#ibcon#about to read 3, iclass 18, count 0 2006.257.10:48:25.89#ibcon#read 3, iclass 18, count 0 2006.257.10:48:25.89#ibcon#about to read 4, iclass 18, count 0 2006.257.10:48:25.89#ibcon#read 4, iclass 18, count 0 2006.257.10:48:25.89#ibcon#about to read 5, iclass 18, count 0 2006.257.10:48:25.89#ibcon#read 5, iclass 18, count 0 2006.257.10:48:25.89#ibcon#about to read 6, iclass 18, count 0 2006.257.10:48:25.89#ibcon#read 6, iclass 18, count 0 2006.257.10:48:25.89#ibcon#end of sib2, iclass 18, count 0 2006.257.10:48:25.89#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:48:25.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:48:25.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:48:25.89#ibcon#*before write, iclass 18, count 0 2006.257.10:48:25.89#ibcon#enter sib2, iclass 18, count 0 2006.257.10:48:25.89#ibcon#flushed, iclass 18, count 0 2006.257.10:48:25.89#ibcon#about to write, iclass 18, count 0 2006.257.10:48:25.89#ibcon#wrote, iclass 18, count 0 2006.257.10:48:25.89#ibcon#about to read 3, iclass 18, count 0 2006.257.10:48:25.93#ibcon#read 3, iclass 18, count 0 2006.257.10:48:25.93#ibcon#about to read 4, iclass 18, count 0 2006.257.10:48:25.93#ibcon#read 4, iclass 18, count 0 2006.257.10:48:25.93#ibcon#about to read 5, iclass 18, count 0 2006.257.10:48:25.93#ibcon#read 5, iclass 18, count 0 2006.257.10:48:25.93#ibcon#about to read 6, iclass 18, count 0 2006.257.10:48:25.93#ibcon#read 6, iclass 18, count 0 2006.257.10:48:25.93#ibcon#end of sib2, iclass 18, count 0 2006.257.10:48:25.93#ibcon#*after write, iclass 18, count 0 2006.257.10:48:25.93#ibcon#*before return 0, iclass 18, count 0 2006.257.10:48:25.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:25.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:25.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:48:25.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:48:25.93$vck44/va=3,8 2006.257.10:48:25.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.10:48:25.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.10:48:25.93#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:25.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:25.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:25.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:25.99#ibcon#enter wrdev, iclass 20, count 2 2006.257.10:48:25.99#ibcon#first serial, iclass 20, count 2 2006.257.10:48:25.99#ibcon#enter sib2, iclass 20, count 2 2006.257.10:48:25.99#ibcon#flushed, iclass 20, count 2 2006.257.10:48:25.99#ibcon#about to write, iclass 20, count 2 2006.257.10:48:25.99#ibcon#wrote, iclass 20, count 2 2006.257.10:48:25.99#ibcon#about to read 3, iclass 20, count 2 2006.257.10:48:26.01#ibcon#read 3, iclass 20, count 2 2006.257.10:48:26.01#ibcon#about to read 4, iclass 20, count 2 2006.257.10:48:26.01#ibcon#read 4, iclass 20, count 2 2006.257.10:48:26.01#ibcon#about to read 5, iclass 20, count 2 2006.257.10:48:26.01#ibcon#read 5, iclass 20, count 2 2006.257.10:48:26.01#ibcon#about to read 6, iclass 20, count 2 2006.257.10:48:26.01#ibcon#read 6, iclass 20, count 2 2006.257.10:48:26.01#ibcon#end of sib2, iclass 20, count 2 2006.257.10:48:26.01#ibcon#*mode == 0, iclass 20, count 2 2006.257.10:48:26.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.10:48:26.01#ibcon#[25=AT03-08\r\n] 2006.257.10:48:26.01#ibcon#*before write, iclass 20, count 2 2006.257.10:48:26.01#ibcon#enter sib2, iclass 20, count 2 2006.257.10:48:26.01#ibcon#flushed, iclass 20, count 2 2006.257.10:48:26.01#ibcon#about to write, iclass 20, count 2 2006.257.10:48:26.01#ibcon#wrote, iclass 20, count 2 2006.257.10:48:26.01#ibcon#about to read 3, iclass 20, count 2 2006.257.10:48:26.04#ibcon#read 3, iclass 20, count 2 2006.257.10:48:26.04#ibcon#about to read 4, iclass 20, count 2 2006.257.10:48:26.04#ibcon#read 4, iclass 20, count 2 2006.257.10:48:26.04#ibcon#about to read 5, iclass 20, count 2 2006.257.10:48:26.04#ibcon#read 5, iclass 20, count 2 2006.257.10:48:26.04#ibcon#about to read 6, iclass 20, count 2 2006.257.10:48:26.04#ibcon#read 6, iclass 20, count 2 2006.257.10:48:26.04#ibcon#end of sib2, iclass 20, count 2 2006.257.10:48:26.04#ibcon#*after write, iclass 20, count 2 2006.257.10:48:26.04#ibcon#*before return 0, iclass 20, count 2 2006.257.10:48:26.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:26.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:26.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.10:48:26.04#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:26.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:26.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:26.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:26.16#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:48:26.16#ibcon#first serial, iclass 20, count 0 2006.257.10:48:26.16#ibcon#enter sib2, iclass 20, count 0 2006.257.10:48:26.16#ibcon#flushed, iclass 20, count 0 2006.257.10:48:26.16#ibcon#about to write, iclass 20, count 0 2006.257.10:48:26.16#ibcon#wrote, iclass 20, count 0 2006.257.10:48:26.16#ibcon#about to read 3, iclass 20, count 0 2006.257.10:48:26.18#ibcon#read 3, iclass 20, count 0 2006.257.10:48:26.18#ibcon#about to read 4, iclass 20, count 0 2006.257.10:48:26.18#ibcon#read 4, iclass 20, count 0 2006.257.10:48:26.18#ibcon#about to read 5, iclass 20, count 0 2006.257.10:48:26.18#ibcon#read 5, iclass 20, count 0 2006.257.10:48:26.18#ibcon#about to read 6, iclass 20, count 0 2006.257.10:48:26.18#ibcon#read 6, iclass 20, count 0 2006.257.10:48:26.18#ibcon#end of sib2, iclass 20, count 0 2006.257.10:48:26.18#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:48:26.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:48:26.18#ibcon#[25=USB\r\n] 2006.257.10:48:26.18#ibcon#*before write, iclass 20, count 0 2006.257.10:48:26.18#ibcon#enter sib2, iclass 20, count 0 2006.257.10:48:26.18#ibcon#flushed, iclass 20, count 0 2006.257.10:48:26.18#ibcon#about to write, iclass 20, count 0 2006.257.10:48:26.18#ibcon#wrote, iclass 20, count 0 2006.257.10:48:26.18#ibcon#about to read 3, iclass 20, count 0 2006.257.10:48:26.21#ibcon#read 3, iclass 20, count 0 2006.257.10:48:26.21#ibcon#about to read 4, iclass 20, count 0 2006.257.10:48:26.21#ibcon#read 4, iclass 20, count 0 2006.257.10:48:26.21#ibcon#about to read 5, iclass 20, count 0 2006.257.10:48:26.21#ibcon#read 5, iclass 20, count 0 2006.257.10:48:26.21#ibcon#about to read 6, iclass 20, count 0 2006.257.10:48:26.21#ibcon#read 6, iclass 20, count 0 2006.257.10:48:26.21#ibcon#end of sib2, iclass 20, count 0 2006.257.10:48:26.21#ibcon#*after write, iclass 20, count 0 2006.257.10:48:26.21#ibcon#*before return 0, iclass 20, count 0 2006.257.10:48:26.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:26.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:26.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:48:26.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:48:26.21$vck44/valo=4,624.99 2006.257.10:48:26.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.10:48:26.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.10:48:26.21#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:26.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:26.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:26.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:26.21#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:48:26.21#ibcon#first serial, iclass 22, count 0 2006.257.10:48:26.21#ibcon#enter sib2, iclass 22, count 0 2006.257.10:48:26.21#ibcon#flushed, iclass 22, count 0 2006.257.10:48:26.21#ibcon#about to write, iclass 22, count 0 2006.257.10:48:26.21#ibcon#wrote, iclass 22, count 0 2006.257.10:48:26.21#ibcon#about to read 3, iclass 22, count 0 2006.257.10:48:26.23#ibcon#read 3, iclass 22, count 0 2006.257.10:48:26.23#ibcon#about to read 4, iclass 22, count 0 2006.257.10:48:26.23#ibcon#read 4, iclass 22, count 0 2006.257.10:48:26.23#ibcon#about to read 5, iclass 22, count 0 2006.257.10:48:26.23#ibcon#read 5, iclass 22, count 0 2006.257.10:48:26.23#ibcon#about to read 6, iclass 22, count 0 2006.257.10:48:26.23#ibcon#read 6, iclass 22, count 0 2006.257.10:48:26.23#ibcon#end of sib2, iclass 22, count 0 2006.257.10:48:26.23#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:48:26.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:48:26.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:48:26.23#ibcon#*before write, iclass 22, count 0 2006.257.10:48:26.23#ibcon#enter sib2, iclass 22, count 0 2006.257.10:48:26.23#ibcon#flushed, iclass 22, count 0 2006.257.10:48:26.23#ibcon#about to write, iclass 22, count 0 2006.257.10:48:26.23#ibcon#wrote, iclass 22, count 0 2006.257.10:48:26.23#ibcon#about to read 3, iclass 22, count 0 2006.257.10:48:26.27#ibcon#read 3, iclass 22, count 0 2006.257.10:48:26.27#ibcon#about to read 4, iclass 22, count 0 2006.257.10:48:26.27#ibcon#read 4, iclass 22, count 0 2006.257.10:48:26.27#ibcon#about to read 5, iclass 22, count 0 2006.257.10:48:26.27#ibcon#read 5, iclass 22, count 0 2006.257.10:48:26.27#ibcon#about to read 6, iclass 22, count 0 2006.257.10:48:26.27#ibcon#read 6, iclass 22, count 0 2006.257.10:48:26.27#ibcon#end of sib2, iclass 22, count 0 2006.257.10:48:26.27#ibcon#*after write, iclass 22, count 0 2006.257.10:48:26.27#ibcon#*before return 0, iclass 22, count 0 2006.257.10:48:26.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:26.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:26.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:48:26.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:48:26.27$vck44/va=4,7 2006.257.10:48:26.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.10:48:26.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.10:48:26.27#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:26.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:26.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:26.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:26.33#ibcon#enter wrdev, iclass 24, count 2 2006.257.10:48:26.33#ibcon#first serial, iclass 24, count 2 2006.257.10:48:26.33#ibcon#enter sib2, iclass 24, count 2 2006.257.10:48:26.33#ibcon#flushed, iclass 24, count 2 2006.257.10:48:26.33#ibcon#about to write, iclass 24, count 2 2006.257.10:48:26.33#ibcon#wrote, iclass 24, count 2 2006.257.10:48:26.33#ibcon#about to read 3, iclass 24, count 2 2006.257.10:48:26.35#ibcon#read 3, iclass 24, count 2 2006.257.10:48:26.35#ibcon#about to read 4, iclass 24, count 2 2006.257.10:48:26.35#ibcon#read 4, iclass 24, count 2 2006.257.10:48:26.35#ibcon#about to read 5, iclass 24, count 2 2006.257.10:48:26.35#ibcon#read 5, iclass 24, count 2 2006.257.10:48:26.35#ibcon#about to read 6, iclass 24, count 2 2006.257.10:48:26.35#ibcon#read 6, iclass 24, count 2 2006.257.10:48:26.35#ibcon#end of sib2, iclass 24, count 2 2006.257.10:48:26.35#ibcon#*mode == 0, iclass 24, count 2 2006.257.10:48:26.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.10:48:26.35#ibcon#[25=AT04-07\r\n] 2006.257.10:48:26.35#ibcon#*before write, iclass 24, count 2 2006.257.10:48:26.35#ibcon#enter sib2, iclass 24, count 2 2006.257.10:48:26.35#ibcon#flushed, iclass 24, count 2 2006.257.10:48:26.35#ibcon#about to write, iclass 24, count 2 2006.257.10:48:26.35#ibcon#wrote, iclass 24, count 2 2006.257.10:48:26.35#ibcon#about to read 3, iclass 24, count 2 2006.257.10:48:26.38#ibcon#read 3, iclass 24, count 2 2006.257.10:48:26.40#ibcon#about to read 4, iclass 24, count 2 2006.257.10:48:26.40#ibcon#read 4, iclass 24, count 2 2006.257.10:48:26.40#ibcon#about to read 5, iclass 24, count 2 2006.257.10:48:26.40#ibcon#read 5, iclass 24, count 2 2006.257.10:48:26.40#ibcon#about to read 6, iclass 24, count 2 2006.257.10:48:26.40#ibcon#read 6, iclass 24, count 2 2006.257.10:48:26.40#ibcon#end of sib2, iclass 24, count 2 2006.257.10:48:26.40#ibcon#*after write, iclass 24, count 2 2006.257.10:48:26.40#ibcon#*before return 0, iclass 24, count 2 2006.257.10:48:26.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:26.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:26.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.10:48:26.40#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:26.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:26.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:26.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:26.52#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:48:26.52#ibcon#first serial, iclass 24, count 0 2006.257.10:48:26.52#ibcon#enter sib2, iclass 24, count 0 2006.257.10:48:26.52#ibcon#flushed, iclass 24, count 0 2006.257.10:48:26.52#ibcon#about to write, iclass 24, count 0 2006.257.10:48:26.52#ibcon#wrote, iclass 24, count 0 2006.257.10:48:26.52#ibcon#about to read 3, iclass 24, count 0 2006.257.10:48:26.54#ibcon#read 3, iclass 24, count 0 2006.257.10:48:26.54#ibcon#about to read 4, iclass 24, count 0 2006.257.10:48:26.54#ibcon#read 4, iclass 24, count 0 2006.257.10:48:26.54#ibcon#about to read 5, iclass 24, count 0 2006.257.10:48:26.54#ibcon#read 5, iclass 24, count 0 2006.257.10:48:26.54#ibcon#about to read 6, iclass 24, count 0 2006.257.10:48:26.54#ibcon#read 6, iclass 24, count 0 2006.257.10:48:26.54#ibcon#end of sib2, iclass 24, count 0 2006.257.10:48:26.54#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:48:26.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:48:26.54#ibcon#[25=USB\r\n] 2006.257.10:48:26.54#ibcon#*before write, iclass 24, count 0 2006.257.10:48:26.54#ibcon#enter sib2, iclass 24, count 0 2006.257.10:48:26.54#ibcon#flushed, iclass 24, count 0 2006.257.10:48:26.54#ibcon#about to write, iclass 24, count 0 2006.257.10:48:26.54#ibcon#wrote, iclass 24, count 0 2006.257.10:48:26.54#ibcon#about to read 3, iclass 24, count 0 2006.257.10:48:26.57#ibcon#read 3, iclass 24, count 0 2006.257.10:48:26.57#ibcon#about to read 4, iclass 24, count 0 2006.257.10:48:26.57#ibcon#read 4, iclass 24, count 0 2006.257.10:48:26.57#ibcon#about to read 5, iclass 24, count 0 2006.257.10:48:26.57#ibcon#read 5, iclass 24, count 0 2006.257.10:48:26.57#ibcon#about to read 6, iclass 24, count 0 2006.257.10:48:26.57#ibcon#read 6, iclass 24, count 0 2006.257.10:48:26.57#ibcon#end of sib2, iclass 24, count 0 2006.257.10:48:26.57#ibcon#*after write, iclass 24, count 0 2006.257.10:48:26.57#ibcon#*before return 0, iclass 24, count 0 2006.257.10:48:26.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:26.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:26.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:48:26.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:48:26.57$vck44/valo=5,734.99 2006.257.10:48:26.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.10:48:26.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.10:48:26.57#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:26.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:26.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:26.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:26.57#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:48:26.57#ibcon#first serial, iclass 26, count 0 2006.257.10:48:26.57#ibcon#enter sib2, iclass 26, count 0 2006.257.10:48:26.57#ibcon#flushed, iclass 26, count 0 2006.257.10:48:26.57#ibcon#about to write, iclass 26, count 0 2006.257.10:48:26.57#ibcon#wrote, iclass 26, count 0 2006.257.10:48:26.57#ibcon#about to read 3, iclass 26, count 0 2006.257.10:48:26.59#ibcon#read 3, iclass 26, count 0 2006.257.10:48:26.59#ibcon#about to read 4, iclass 26, count 0 2006.257.10:48:26.59#ibcon#read 4, iclass 26, count 0 2006.257.10:48:26.59#ibcon#about to read 5, iclass 26, count 0 2006.257.10:48:26.59#ibcon#read 5, iclass 26, count 0 2006.257.10:48:26.59#ibcon#about to read 6, iclass 26, count 0 2006.257.10:48:26.59#ibcon#read 6, iclass 26, count 0 2006.257.10:48:26.59#ibcon#end of sib2, iclass 26, count 0 2006.257.10:48:26.59#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:48:26.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:48:26.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:48:26.59#ibcon#*before write, iclass 26, count 0 2006.257.10:48:26.59#ibcon#enter sib2, iclass 26, count 0 2006.257.10:48:26.59#ibcon#flushed, iclass 26, count 0 2006.257.10:48:26.59#ibcon#about to write, iclass 26, count 0 2006.257.10:48:26.59#ibcon#wrote, iclass 26, count 0 2006.257.10:48:26.59#ibcon#about to read 3, iclass 26, count 0 2006.257.10:48:26.63#ibcon#read 3, iclass 26, count 0 2006.257.10:48:26.63#ibcon#about to read 4, iclass 26, count 0 2006.257.10:48:26.63#ibcon#read 4, iclass 26, count 0 2006.257.10:48:26.63#ibcon#about to read 5, iclass 26, count 0 2006.257.10:48:26.63#ibcon#read 5, iclass 26, count 0 2006.257.10:48:26.63#ibcon#about to read 6, iclass 26, count 0 2006.257.10:48:26.63#ibcon#read 6, iclass 26, count 0 2006.257.10:48:26.63#ibcon#end of sib2, iclass 26, count 0 2006.257.10:48:26.63#ibcon#*after write, iclass 26, count 0 2006.257.10:48:26.63#ibcon#*before return 0, iclass 26, count 0 2006.257.10:48:26.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:26.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:26.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:48:26.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:48:26.63$vck44/va=5,4 2006.257.10:48:26.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.10:48:26.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.10:48:26.63#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:26.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:26.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:26.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:26.69#ibcon#enter wrdev, iclass 28, count 2 2006.257.10:48:26.69#ibcon#first serial, iclass 28, count 2 2006.257.10:48:26.69#ibcon#enter sib2, iclass 28, count 2 2006.257.10:48:26.69#ibcon#flushed, iclass 28, count 2 2006.257.10:48:26.69#ibcon#about to write, iclass 28, count 2 2006.257.10:48:26.69#ibcon#wrote, iclass 28, count 2 2006.257.10:48:26.69#ibcon#about to read 3, iclass 28, count 2 2006.257.10:48:26.71#ibcon#read 3, iclass 28, count 2 2006.257.10:48:26.71#ibcon#about to read 4, iclass 28, count 2 2006.257.10:48:26.71#ibcon#read 4, iclass 28, count 2 2006.257.10:48:26.71#ibcon#about to read 5, iclass 28, count 2 2006.257.10:48:26.71#ibcon#read 5, iclass 28, count 2 2006.257.10:48:26.71#ibcon#about to read 6, iclass 28, count 2 2006.257.10:48:26.71#ibcon#read 6, iclass 28, count 2 2006.257.10:48:26.71#ibcon#end of sib2, iclass 28, count 2 2006.257.10:48:26.71#ibcon#*mode == 0, iclass 28, count 2 2006.257.10:48:26.71#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.10:48:26.71#ibcon#[25=AT05-04\r\n] 2006.257.10:48:26.71#ibcon#*before write, iclass 28, count 2 2006.257.10:48:26.71#ibcon#enter sib2, iclass 28, count 2 2006.257.10:48:26.71#ibcon#flushed, iclass 28, count 2 2006.257.10:48:26.71#ibcon#about to write, iclass 28, count 2 2006.257.10:48:26.71#ibcon#wrote, iclass 28, count 2 2006.257.10:48:26.71#ibcon#about to read 3, iclass 28, count 2 2006.257.10:48:26.74#ibcon#read 3, iclass 28, count 2 2006.257.10:48:26.74#ibcon#about to read 4, iclass 28, count 2 2006.257.10:48:26.74#ibcon#read 4, iclass 28, count 2 2006.257.10:48:26.74#ibcon#about to read 5, iclass 28, count 2 2006.257.10:48:26.74#ibcon#read 5, iclass 28, count 2 2006.257.10:48:26.74#ibcon#about to read 6, iclass 28, count 2 2006.257.10:48:26.74#ibcon#read 6, iclass 28, count 2 2006.257.10:48:26.74#ibcon#end of sib2, iclass 28, count 2 2006.257.10:48:26.74#ibcon#*after write, iclass 28, count 2 2006.257.10:48:26.74#ibcon#*before return 0, iclass 28, count 2 2006.257.10:48:26.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:26.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:26.74#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.10:48:26.74#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:26.74#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:26.86#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:26.86#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:26.86#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:48:26.86#ibcon#first serial, iclass 28, count 0 2006.257.10:48:26.86#ibcon#enter sib2, iclass 28, count 0 2006.257.10:48:26.86#ibcon#flushed, iclass 28, count 0 2006.257.10:48:26.86#ibcon#about to write, iclass 28, count 0 2006.257.10:48:26.86#ibcon#wrote, iclass 28, count 0 2006.257.10:48:26.86#ibcon#about to read 3, iclass 28, count 0 2006.257.10:48:26.88#ibcon#read 3, iclass 28, count 0 2006.257.10:48:26.88#ibcon#about to read 4, iclass 28, count 0 2006.257.10:48:26.88#ibcon#read 4, iclass 28, count 0 2006.257.10:48:26.88#ibcon#about to read 5, iclass 28, count 0 2006.257.10:48:26.88#ibcon#read 5, iclass 28, count 0 2006.257.10:48:26.88#ibcon#about to read 6, iclass 28, count 0 2006.257.10:48:26.88#ibcon#read 6, iclass 28, count 0 2006.257.10:48:26.88#ibcon#end of sib2, iclass 28, count 0 2006.257.10:48:26.88#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:48:26.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:48:26.88#ibcon#[25=USB\r\n] 2006.257.10:48:26.88#ibcon#*before write, iclass 28, count 0 2006.257.10:48:26.88#ibcon#enter sib2, iclass 28, count 0 2006.257.10:48:26.88#ibcon#flushed, iclass 28, count 0 2006.257.10:48:26.88#ibcon#about to write, iclass 28, count 0 2006.257.10:48:26.88#ibcon#wrote, iclass 28, count 0 2006.257.10:48:26.88#ibcon#about to read 3, iclass 28, count 0 2006.257.10:48:26.91#ibcon#read 3, iclass 28, count 0 2006.257.10:48:26.91#ibcon#about to read 4, iclass 28, count 0 2006.257.10:48:26.91#ibcon#read 4, iclass 28, count 0 2006.257.10:48:26.91#ibcon#about to read 5, iclass 28, count 0 2006.257.10:48:26.91#ibcon#read 5, iclass 28, count 0 2006.257.10:48:26.91#ibcon#about to read 6, iclass 28, count 0 2006.257.10:48:26.91#ibcon#read 6, iclass 28, count 0 2006.257.10:48:26.91#ibcon#end of sib2, iclass 28, count 0 2006.257.10:48:26.91#ibcon#*after write, iclass 28, count 0 2006.257.10:48:26.91#ibcon#*before return 0, iclass 28, count 0 2006.257.10:48:26.91#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:26.91#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:26.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:48:26.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:48:26.91$vck44/valo=6,814.99 2006.257.10:48:26.91#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.10:48:26.91#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.10:48:26.91#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:26.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:26.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:26.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:26.91#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:48:26.91#ibcon#first serial, iclass 30, count 0 2006.257.10:48:26.91#ibcon#enter sib2, iclass 30, count 0 2006.257.10:48:26.91#ibcon#flushed, iclass 30, count 0 2006.257.10:48:26.91#ibcon#about to write, iclass 30, count 0 2006.257.10:48:26.91#ibcon#wrote, iclass 30, count 0 2006.257.10:48:26.91#ibcon#about to read 3, iclass 30, count 0 2006.257.10:48:26.93#ibcon#read 3, iclass 30, count 0 2006.257.10:48:26.93#ibcon#about to read 4, iclass 30, count 0 2006.257.10:48:26.93#ibcon#read 4, iclass 30, count 0 2006.257.10:48:26.93#ibcon#about to read 5, iclass 30, count 0 2006.257.10:48:26.93#ibcon#read 5, iclass 30, count 0 2006.257.10:48:26.93#ibcon#about to read 6, iclass 30, count 0 2006.257.10:48:26.93#ibcon#read 6, iclass 30, count 0 2006.257.10:48:26.93#ibcon#end of sib2, iclass 30, count 0 2006.257.10:48:26.93#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:48:26.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:48:26.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:48:26.93#ibcon#*before write, iclass 30, count 0 2006.257.10:48:26.93#ibcon#enter sib2, iclass 30, count 0 2006.257.10:48:26.93#ibcon#flushed, iclass 30, count 0 2006.257.10:48:26.93#ibcon#about to write, iclass 30, count 0 2006.257.10:48:26.93#ibcon#wrote, iclass 30, count 0 2006.257.10:48:26.93#ibcon#about to read 3, iclass 30, count 0 2006.257.10:48:26.97#ibcon#read 3, iclass 30, count 0 2006.257.10:48:26.97#ibcon#about to read 4, iclass 30, count 0 2006.257.10:48:26.97#ibcon#read 4, iclass 30, count 0 2006.257.10:48:26.97#ibcon#about to read 5, iclass 30, count 0 2006.257.10:48:26.97#ibcon#read 5, iclass 30, count 0 2006.257.10:48:26.97#ibcon#about to read 6, iclass 30, count 0 2006.257.10:48:26.97#ibcon#read 6, iclass 30, count 0 2006.257.10:48:26.97#ibcon#end of sib2, iclass 30, count 0 2006.257.10:48:26.97#ibcon#*after write, iclass 30, count 0 2006.257.10:48:26.97#ibcon#*before return 0, iclass 30, count 0 2006.257.10:48:26.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:26.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:26.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:48:26.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:48:26.97$vck44/va=6,4 2006.257.10:48:26.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.10:48:26.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.10:48:26.97#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:26.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:27.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:27.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:27.03#ibcon#enter wrdev, iclass 32, count 2 2006.257.10:48:27.03#ibcon#first serial, iclass 32, count 2 2006.257.10:48:27.03#ibcon#enter sib2, iclass 32, count 2 2006.257.10:48:27.03#ibcon#flushed, iclass 32, count 2 2006.257.10:48:27.03#ibcon#about to write, iclass 32, count 2 2006.257.10:48:27.03#ibcon#wrote, iclass 32, count 2 2006.257.10:48:27.03#ibcon#about to read 3, iclass 32, count 2 2006.257.10:48:27.05#ibcon#read 3, iclass 32, count 2 2006.257.10:48:27.05#ibcon#about to read 4, iclass 32, count 2 2006.257.10:48:27.05#ibcon#read 4, iclass 32, count 2 2006.257.10:48:27.05#ibcon#about to read 5, iclass 32, count 2 2006.257.10:48:27.05#ibcon#read 5, iclass 32, count 2 2006.257.10:48:27.05#ibcon#about to read 6, iclass 32, count 2 2006.257.10:48:27.05#ibcon#read 6, iclass 32, count 2 2006.257.10:48:27.05#ibcon#end of sib2, iclass 32, count 2 2006.257.10:48:27.05#ibcon#*mode == 0, iclass 32, count 2 2006.257.10:48:27.05#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.10:48:27.05#ibcon#[25=AT06-04\r\n] 2006.257.10:48:27.05#ibcon#*before write, iclass 32, count 2 2006.257.10:48:27.05#ibcon#enter sib2, iclass 32, count 2 2006.257.10:48:27.05#ibcon#flushed, iclass 32, count 2 2006.257.10:48:27.05#ibcon#about to write, iclass 32, count 2 2006.257.10:48:27.05#ibcon#wrote, iclass 32, count 2 2006.257.10:48:27.05#ibcon#about to read 3, iclass 32, count 2 2006.257.10:48:27.08#ibcon#read 3, iclass 32, count 2 2006.257.10:48:27.08#ibcon#about to read 4, iclass 32, count 2 2006.257.10:48:27.08#ibcon#read 4, iclass 32, count 2 2006.257.10:48:27.08#ibcon#about to read 5, iclass 32, count 2 2006.257.10:48:27.08#ibcon#read 5, iclass 32, count 2 2006.257.10:48:27.08#ibcon#about to read 6, iclass 32, count 2 2006.257.10:48:27.08#ibcon#read 6, iclass 32, count 2 2006.257.10:48:27.08#ibcon#end of sib2, iclass 32, count 2 2006.257.10:48:27.08#ibcon#*after write, iclass 32, count 2 2006.257.10:48:27.08#ibcon#*before return 0, iclass 32, count 2 2006.257.10:48:27.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:27.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:27.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.10:48:27.08#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:27.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:27.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:27.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:27.20#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:48:27.20#ibcon#first serial, iclass 32, count 0 2006.257.10:48:27.20#ibcon#enter sib2, iclass 32, count 0 2006.257.10:48:27.20#ibcon#flushed, iclass 32, count 0 2006.257.10:48:27.20#ibcon#about to write, iclass 32, count 0 2006.257.10:48:27.20#ibcon#wrote, iclass 32, count 0 2006.257.10:48:27.20#ibcon#about to read 3, iclass 32, count 0 2006.257.10:48:27.22#ibcon#read 3, iclass 32, count 0 2006.257.10:48:27.22#ibcon#about to read 4, iclass 32, count 0 2006.257.10:48:27.22#ibcon#read 4, iclass 32, count 0 2006.257.10:48:27.22#ibcon#about to read 5, iclass 32, count 0 2006.257.10:48:27.22#ibcon#read 5, iclass 32, count 0 2006.257.10:48:27.22#ibcon#about to read 6, iclass 32, count 0 2006.257.10:48:27.22#ibcon#read 6, iclass 32, count 0 2006.257.10:48:27.22#ibcon#end of sib2, iclass 32, count 0 2006.257.10:48:27.22#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:48:27.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:48:27.22#ibcon#[25=USB\r\n] 2006.257.10:48:27.22#ibcon#*before write, iclass 32, count 0 2006.257.10:48:27.22#ibcon#enter sib2, iclass 32, count 0 2006.257.10:48:27.22#ibcon#flushed, iclass 32, count 0 2006.257.10:48:27.22#ibcon#about to write, iclass 32, count 0 2006.257.10:48:27.22#ibcon#wrote, iclass 32, count 0 2006.257.10:48:27.22#ibcon#about to read 3, iclass 32, count 0 2006.257.10:48:27.25#ibcon#read 3, iclass 32, count 0 2006.257.10:48:27.25#ibcon#about to read 4, iclass 32, count 0 2006.257.10:48:27.25#ibcon#read 4, iclass 32, count 0 2006.257.10:48:27.25#ibcon#about to read 5, iclass 32, count 0 2006.257.10:48:27.25#ibcon#read 5, iclass 32, count 0 2006.257.10:48:27.25#ibcon#about to read 6, iclass 32, count 0 2006.257.10:48:27.25#ibcon#read 6, iclass 32, count 0 2006.257.10:48:27.25#ibcon#end of sib2, iclass 32, count 0 2006.257.10:48:27.25#ibcon#*after write, iclass 32, count 0 2006.257.10:48:27.25#ibcon#*before return 0, iclass 32, count 0 2006.257.10:48:27.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:27.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:27.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:48:27.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:48:27.25$vck44/valo=7,864.99 2006.257.10:48:27.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.10:48:27.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.10:48:27.25#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:27.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:27.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:27.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:27.25#ibcon#enter wrdev, iclass 34, count 0 2006.257.10:48:27.25#ibcon#first serial, iclass 34, count 0 2006.257.10:48:27.25#ibcon#enter sib2, iclass 34, count 0 2006.257.10:48:27.25#ibcon#flushed, iclass 34, count 0 2006.257.10:48:27.25#ibcon#about to write, iclass 34, count 0 2006.257.10:48:27.25#ibcon#wrote, iclass 34, count 0 2006.257.10:48:27.25#ibcon#about to read 3, iclass 34, count 0 2006.257.10:48:27.27#ibcon#read 3, iclass 34, count 0 2006.257.10:48:27.27#ibcon#about to read 4, iclass 34, count 0 2006.257.10:48:27.27#ibcon#read 4, iclass 34, count 0 2006.257.10:48:27.27#ibcon#about to read 5, iclass 34, count 0 2006.257.10:48:27.27#ibcon#read 5, iclass 34, count 0 2006.257.10:48:27.27#ibcon#about to read 6, iclass 34, count 0 2006.257.10:48:27.27#ibcon#read 6, iclass 34, count 0 2006.257.10:48:27.27#ibcon#end of sib2, iclass 34, count 0 2006.257.10:48:27.27#ibcon#*mode == 0, iclass 34, count 0 2006.257.10:48:27.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.10:48:27.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:48:27.27#ibcon#*before write, iclass 34, count 0 2006.257.10:48:27.27#ibcon#enter sib2, iclass 34, count 0 2006.257.10:48:27.27#ibcon#flushed, iclass 34, count 0 2006.257.10:48:27.27#ibcon#about to write, iclass 34, count 0 2006.257.10:48:27.27#ibcon#wrote, iclass 34, count 0 2006.257.10:48:27.27#ibcon#about to read 3, iclass 34, count 0 2006.257.10:48:27.31#ibcon#read 3, iclass 34, count 0 2006.257.10:48:27.31#ibcon#about to read 4, iclass 34, count 0 2006.257.10:48:27.31#ibcon#read 4, iclass 34, count 0 2006.257.10:48:27.31#ibcon#about to read 5, iclass 34, count 0 2006.257.10:48:27.31#ibcon#read 5, iclass 34, count 0 2006.257.10:48:27.31#ibcon#about to read 6, iclass 34, count 0 2006.257.10:48:27.31#ibcon#read 6, iclass 34, count 0 2006.257.10:48:27.31#ibcon#end of sib2, iclass 34, count 0 2006.257.10:48:27.31#ibcon#*after write, iclass 34, count 0 2006.257.10:48:27.31#ibcon#*before return 0, iclass 34, count 0 2006.257.10:48:27.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:27.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:27.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.10:48:27.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.10:48:27.31$vck44/va=7,4 2006.257.10:48:27.31#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.10:48:27.31#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.10:48:27.31#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:27.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:27.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:27.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:27.37#ibcon#enter wrdev, iclass 36, count 2 2006.257.10:48:27.37#ibcon#first serial, iclass 36, count 2 2006.257.10:48:27.37#ibcon#enter sib2, iclass 36, count 2 2006.257.10:48:27.37#ibcon#flushed, iclass 36, count 2 2006.257.10:48:27.37#ibcon#about to write, iclass 36, count 2 2006.257.10:48:27.37#ibcon#wrote, iclass 36, count 2 2006.257.10:48:27.37#ibcon#about to read 3, iclass 36, count 2 2006.257.10:48:27.39#ibcon#read 3, iclass 36, count 2 2006.257.10:48:27.39#ibcon#about to read 4, iclass 36, count 2 2006.257.10:48:27.39#ibcon#read 4, iclass 36, count 2 2006.257.10:48:27.39#ibcon#about to read 5, iclass 36, count 2 2006.257.10:48:27.39#ibcon#read 5, iclass 36, count 2 2006.257.10:48:27.39#ibcon#about to read 6, iclass 36, count 2 2006.257.10:48:27.39#ibcon#read 6, iclass 36, count 2 2006.257.10:48:27.39#ibcon#end of sib2, iclass 36, count 2 2006.257.10:48:27.39#ibcon#*mode == 0, iclass 36, count 2 2006.257.10:48:27.39#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.10:48:27.39#ibcon#[25=AT07-04\r\n] 2006.257.10:48:27.39#ibcon#*before write, iclass 36, count 2 2006.257.10:48:27.39#ibcon#enter sib2, iclass 36, count 2 2006.257.10:48:27.39#ibcon#flushed, iclass 36, count 2 2006.257.10:48:27.39#ibcon#about to write, iclass 36, count 2 2006.257.10:48:27.39#ibcon#wrote, iclass 36, count 2 2006.257.10:48:27.39#ibcon#about to read 3, iclass 36, count 2 2006.257.10:48:27.42#ibcon#read 3, iclass 36, count 2 2006.257.10:48:27.42#ibcon#about to read 4, iclass 36, count 2 2006.257.10:48:27.42#ibcon#read 4, iclass 36, count 2 2006.257.10:48:27.42#ibcon#about to read 5, iclass 36, count 2 2006.257.10:48:27.42#ibcon#read 5, iclass 36, count 2 2006.257.10:48:27.42#ibcon#about to read 6, iclass 36, count 2 2006.257.10:48:27.42#ibcon#read 6, iclass 36, count 2 2006.257.10:48:27.42#ibcon#end of sib2, iclass 36, count 2 2006.257.10:48:27.42#ibcon#*after write, iclass 36, count 2 2006.257.10:48:27.43#ibcon#*before return 0, iclass 36, count 2 2006.257.10:48:27.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:27.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:27.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.10:48:27.43#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:27.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:27.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:27.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:27.55#ibcon#enter wrdev, iclass 36, count 0 2006.257.10:48:27.55#ibcon#first serial, iclass 36, count 0 2006.257.10:48:27.55#ibcon#enter sib2, iclass 36, count 0 2006.257.10:48:27.55#ibcon#flushed, iclass 36, count 0 2006.257.10:48:27.55#ibcon#about to write, iclass 36, count 0 2006.257.10:48:27.55#ibcon#wrote, iclass 36, count 0 2006.257.10:48:27.55#ibcon#about to read 3, iclass 36, count 0 2006.257.10:48:27.57#ibcon#read 3, iclass 36, count 0 2006.257.10:48:27.57#ibcon#about to read 4, iclass 36, count 0 2006.257.10:48:27.57#ibcon#read 4, iclass 36, count 0 2006.257.10:48:27.57#ibcon#about to read 5, iclass 36, count 0 2006.257.10:48:27.57#ibcon#read 5, iclass 36, count 0 2006.257.10:48:27.57#ibcon#about to read 6, iclass 36, count 0 2006.257.10:48:27.57#ibcon#read 6, iclass 36, count 0 2006.257.10:48:27.57#ibcon#end of sib2, iclass 36, count 0 2006.257.10:48:27.57#ibcon#*mode == 0, iclass 36, count 0 2006.257.10:48:27.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.10:48:27.57#ibcon#[25=USB\r\n] 2006.257.10:48:27.57#ibcon#*before write, iclass 36, count 0 2006.257.10:48:27.57#ibcon#enter sib2, iclass 36, count 0 2006.257.10:48:27.57#ibcon#flushed, iclass 36, count 0 2006.257.10:48:27.57#ibcon#about to write, iclass 36, count 0 2006.257.10:48:27.57#ibcon#wrote, iclass 36, count 0 2006.257.10:48:27.57#ibcon#about to read 3, iclass 36, count 0 2006.257.10:48:27.60#ibcon#read 3, iclass 36, count 0 2006.257.10:48:27.60#ibcon#about to read 4, iclass 36, count 0 2006.257.10:48:27.60#ibcon#read 4, iclass 36, count 0 2006.257.10:48:27.60#ibcon#about to read 5, iclass 36, count 0 2006.257.10:48:27.60#ibcon#read 5, iclass 36, count 0 2006.257.10:48:27.60#ibcon#about to read 6, iclass 36, count 0 2006.257.10:48:27.60#ibcon#read 6, iclass 36, count 0 2006.257.10:48:27.60#ibcon#end of sib2, iclass 36, count 0 2006.257.10:48:27.60#ibcon#*after write, iclass 36, count 0 2006.257.10:48:27.60#ibcon#*before return 0, iclass 36, count 0 2006.257.10:48:27.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:27.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:27.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.10:48:27.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.10:48:27.60$vck44/valo=8,884.99 2006.257.10:48:27.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.10:48:27.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.10:48:27.60#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:27.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:27.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:27.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:27.60#ibcon#enter wrdev, iclass 38, count 0 2006.257.10:48:27.60#ibcon#first serial, iclass 38, count 0 2006.257.10:48:27.60#ibcon#enter sib2, iclass 38, count 0 2006.257.10:48:27.60#ibcon#flushed, iclass 38, count 0 2006.257.10:48:27.60#ibcon#about to write, iclass 38, count 0 2006.257.10:48:27.60#ibcon#wrote, iclass 38, count 0 2006.257.10:48:27.60#ibcon#about to read 3, iclass 38, count 0 2006.257.10:48:27.62#ibcon#read 3, iclass 38, count 0 2006.257.10:48:27.62#ibcon#about to read 4, iclass 38, count 0 2006.257.10:48:27.62#ibcon#read 4, iclass 38, count 0 2006.257.10:48:27.62#ibcon#about to read 5, iclass 38, count 0 2006.257.10:48:27.62#ibcon#read 5, iclass 38, count 0 2006.257.10:48:27.62#ibcon#about to read 6, iclass 38, count 0 2006.257.10:48:27.62#ibcon#read 6, iclass 38, count 0 2006.257.10:48:27.62#ibcon#end of sib2, iclass 38, count 0 2006.257.10:48:27.62#ibcon#*mode == 0, iclass 38, count 0 2006.257.10:48:27.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.10:48:27.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:48:27.62#ibcon#*before write, iclass 38, count 0 2006.257.10:48:27.62#ibcon#enter sib2, iclass 38, count 0 2006.257.10:48:27.62#ibcon#flushed, iclass 38, count 0 2006.257.10:48:27.62#ibcon#about to write, iclass 38, count 0 2006.257.10:48:27.62#ibcon#wrote, iclass 38, count 0 2006.257.10:48:27.62#ibcon#about to read 3, iclass 38, count 0 2006.257.10:48:27.66#ibcon#read 3, iclass 38, count 0 2006.257.10:48:27.66#ibcon#about to read 4, iclass 38, count 0 2006.257.10:48:27.66#ibcon#read 4, iclass 38, count 0 2006.257.10:48:27.66#ibcon#about to read 5, iclass 38, count 0 2006.257.10:48:27.66#ibcon#read 5, iclass 38, count 0 2006.257.10:48:27.66#ibcon#about to read 6, iclass 38, count 0 2006.257.10:48:27.66#ibcon#read 6, iclass 38, count 0 2006.257.10:48:27.66#ibcon#end of sib2, iclass 38, count 0 2006.257.10:48:27.66#ibcon#*after write, iclass 38, count 0 2006.257.10:48:27.66#ibcon#*before return 0, iclass 38, count 0 2006.257.10:48:27.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:27.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:27.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.10:48:27.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.10:48:27.66$vck44/va=8,4 2006.257.10:48:27.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.10:48:27.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.10:48:27.66#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:27.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:48:27.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:48:27.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:48:27.72#ibcon#enter wrdev, iclass 40, count 2 2006.257.10:48:27.72#ibcon#first serial, iclass 40, count 2 2006.257.10:48:27.72#ibcon#enter sib2, iclass 40, count 2 2006.257.10:48:27.72#ibcon#flushed, iclass 40, count 2 2006.257.10:48:27.72#ibcon#about to write, iclass 40, count 2 2006.257.10:48:27.72#ibcon#wrote, iclass 40, count 2 2006.257.10:48:27.72#ibcon#about to read 3, iclass 40, count 2 2006.257.10:48:27.74#ibcon#read 3, iclass 40, count 2 2006.257.10:48:27.74#ibcon#about to read 4, iclass 40, count 2 2006.257.10:48:27.74#ibcon#read 4, iclass 40, count 2 2006.257.10:48:27.74#ibcon#about to read 5, iclass 40, count 2 2006.257.10:48:27.74#ibcon#read 5, iclass 40, count 2 2006.257.10:48:27.74#ibcon#about to read 6, iclass 40, count 2 2006.257.10:48:27.74#ibcon#read 6, iclass 40, count 2 2006.257.10:48:27.74#ibcon#end of sib2, iclass 40, count 2 2006.257.10:48:27.74#ibcon#*mode == 0, iclass 40, count 2 2006.257.10:48:27.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.10:48:27.74#ibcon#[25=AT08-04\r\n] 2006.257.10:48:27.74#ibcon#*before write, iclass 40, count 2 2006.257.10:48:27.74#ibcon#enter sib2, iclass 40, count 2 2006.257.10:48:27.74#ibcon#flushed, iclass 40, count 2 2006.257.10:48:27.74#ibcon#about to write, iclass 40, count 2 2006.257.10:48:27.74#ibcon#wrote, iclass 40, count 2 2006.257.10:48:27.74#ibcon#about to read 3, iclass 40, count 2 2006.257.10:48:27.77#ibcon#read 3, iclass 40, count 2 2006.257.10:48:27.77#ibcon#about to read 4, iclass 40, count 2 2006.257.10:48:27.77#ibcon#read 4, iclass 40, count 2 2006.257.10:48:27.77#ibcon#about to read 5, iclass 40, count 2 2006.257.10:48:27.77#ibcon#read 5, iclass 40, count 2 2006.257.10:48:27.77#ibcon#about to read 6, iclass 40, count 2 2006.257.10:48:27.77#ibcon#read 6, iclass 40, count 2 2006.257.10:48:27.77#ibcon#end of sib2, iclass 40, count 2 2006.257.10:48:27.77#ibcon#*after write, iclass 40, count 2 2006.257.10:48:27.77#ibcon#*before return 0, iclass 40, count 2 2006.257.10:48:27.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:48:27.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.10:48:27.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.10:48:27.77#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:27.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:48:27.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:48:27.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:48:27.89#ibcon#enter wrdev, iclass 40, count 0 2006.257.10:48:27.89#ibcon#first serial, iclass 40, count 0 2006.257.10:48:27.89#ibcon#enter sib2, iclass 40, count 0 2006.257.10:48:27.89#ibcon#flushed, iclass 40, count 0 2006.257.10:48:27.89#ibcon#about to write, iclass 40, count 0 2006.257.10:48:27.89#ibcon#wrote, iclass 40, count 0 2006.257.10:48:27.89#ibcon#about to read 3, iclass 40, count 0 2006.257.10:48:27.91#ibcon#read 3, iclass 40, count 0 2006.257.10:48:27.91#ibcon#about to read 4, iclass 40, count 0 2006.257.10:48:27.91#ibcon#read 4, iclass 40, count 0 2006.257.10:48:27.91#ibcon#about to read 5, iclass 40, count 0 2006.257.10:48:27.91#ibcon#read 5, iclass 40, count 0 2006.257.10:48:27.91#ibcon#about to read 6, iclass 40, count 0 2006.257.10:48:27.91#ibcon#read 6, iclass 40, count 0 2006.257.10:48:27.91#ibcon#end of sib2, iclass 40, count 0 2006.257.10:48:27.91#ibcon#*mode == 0, iclass 40, count 0 2006.257.10:48:27.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.10:48:27.91#ibcon#[25=USB\r\n] 2006.257.10:48:27.91#ibcon#*before write, iclass 40, count 0 2006.257.10:48:27.91#ibcon#enter sib2, iclass 40, count 0 2006.257.10:48:27.91#ibcon#flushed, iclass 40, count 0 2006.257.10:48:27.91#ibcon#about to write, iclass 40, count 0 2006.257.10:48:27.91#ibcon#wrote, iclass 40, count 0 2006.257.10:48:27.91#ibcon#about to read 3, iclass 40, count 0 2006.257.10:48:27.94#ibcon#read 3, iclass 40, count 0 2006.257.10:48:27.94#ibcon#about to read 4, iclass 40, count 0 2006.257.10:48:27.94#ibcon#read 4, iclass 40, count 0 2006.257.10:48:27.94#ibcon#about to read 5, iclass 40, count 0 2006.257.10:48:27.94#ibcon#read 5, iclass 40, count 0 2006.257.10:48:27.94#ibcon#about to read 6, iclass 40, count 0 2006.257.10:48:27.94#ibcon#read 6, iclass 40, count 0 2006.257.10:48:27.94#ibcon#end of sib2, iclass 40, count 0 2006.257.10:48:27.94#ibcon#*after write, iclass 40, count 0 2006.257.10:48:27.94#ibcon#*before return 0, iclass 40, count 0 2006.257.10:48:27.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:48:27.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.10:48:27.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.10:48:27.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.10:48:27.94$vck44/vblo=1,629.99 2006.257.10:48:27.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.10:48:27.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.10:48:27.94#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:27.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:48:27.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:48:27.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:48:27.94#ibcon#enter wrdev, iclass 4, count 0 2006.257.10:48:27.94#ibcon#first serial, iclass 4, count 0 2006.257.10:48:27.94#ibcon#enter sib2, iclass 4, count 0 2006.257.10:48:27.94#ibcon#flushed, iclass 4, count 0 2006.257.10:48:27.94#ibcon#about to write, iclass 4, count 0 2006.257.10:48:27.94#ibcon#wrote, iclass 4, count 0 2006.257.10:48:27.94#ibcon#about to read 3, iclass 4, count 0 2006.257.10:48:27.96#ibcon#read 3, iclass 4, count 0 2006.257.10:48:27.96#ibcon#about to read 4, iclass 4, count 0 2006.257.10:48:27.96#ibcon#read 4, iclass 4, count 0 2006.257.10:48:27.96#ibcon#about to read 5, iclass 4, count 0 2006.257.10:48:27.96#ibcon#read 5, iclass 4, count 0 2006.257.10:48:27.96#ibcon#about to read 6, iclass 4, count 0 2006.257.10:48:27.96#ibcon#read 6, iclass 4, count 0 2006.257.10:48:27.96#ibcon#end of sib2, iclass 4, count 0 2006.257.10:48:27.96#ibcon#*mode == 0, iclass 4, count 0 2006.257.10:48:27.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.10:48:27.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:48:27.96#ibcon#*before write, iclass 4, count 0 2006.257.10:48:27.96#ibcon#enter sib2, iclass 4, count 0 2006.257.10:48:27.96#ibcon#flushed, iclass 4, count 0 2006.257.10:48:27.96#ibcon#about to write, iclass 4, count 0 2006.257.10:48:27.96#ibcon#wrote, iclass 4, count 0 2006.257.10:48:27.96#ibcon#about to read 3, iclass 4, count 0 2006.257.10:48:28.00#ibcon#read 3, iclass 4, count 0 2006.257.10:48:28.00#ibcon#about to read 4, iclass 4, count 0 2006.257.10:48:28.00#ibcon#read 4, iclass 4, count 0 2006.257.10:48:28.00#ibcon#about to read 5, iclass 4, count 0 2006.257.10:48:28.00#ibcon#read 5, iclass 4, count 0 2006.257.10:48:28.00#ibcon#about to read 6, iclass 4, count 0 2006.257.10:48:28.00#ibcon#read 6, iclass 4, count 0 2006.257.10:48:28.00#ibcon#end of sib2, iclass 4, count 0 2006.257.10:48:28.00#ibcon#*after write, iclass 4, count 0 2006.257.10:48:28.00#ibcon#*before return 0, iclass 4, count 0 2006.257.10:48:28.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:48:28.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.10:48:28.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.10:48:28.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.10:48:28.00$vck44/vb=1,4 2006.257.10:48:28.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.10:48:28.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.10:48:28.00#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:28.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:48:28.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:48:28.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:48:28.00#ibcon#enter wrdev, iclass 6, count 2 2006.257.10:48:28.00#ibcon#first serial, iclass 6, count 2 2006.257.10:48:28.00#ibcon#enter sib2, iclass 6, count 2 2006.257.10:48:28.00#ibcon#flushed, iclass 6, count 2 2006.257.10:48:28.00#ibcon#about to write, iclass 6, count 2 2006.257.10:48:28.00#ibcon#wrote, iclass 6, count 2 2006.257.10:48:28.00#ibcon#about to read 3, iclass 6, count 2 2006.257.10:48:28.02#ibcon#read 3, iclass 6, count 2 2006.257.10:48:28.02#ibcon#about to read 4, iclass 6, count 2 2006.257.10:48:28.02#ibcon#read 4, iclass 6, count 2 2006.257.10:48:28.02#ibcon#about to read 5, iclass 6, count 2 2006.257.10:48:28.02#ibcon#read 5, iclass 6, count 2 2006.257.10:48:28.02#ibcon#about to read 6, iclass 6, count 2 2006.257.10:48:28.02#ibcon#read 6, iclass 6, count 2 2006.257.10:48:28.02#ibcon#end of sib2, iclass 6, count 2 2006.257.10:48:28.02#ibcon#*mode == 0, iclass 6, count 2 2006.257.10:48:28.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.10:48:28.02#ibcon#[27=AT01-04\r\n] 2006.257.10:48:28.02#ibcon#*before write, iclass 6, count 2 2006.257.10:48:28.02#ibcon#enter sib2, iclass 6, count 2 2006.257.10:48:28.02#ibcon#flushed, iclass 6, count 2 2006.257.10:48:28.02#ibcon#about to write, iclass 6, count 2 2006.257.10:48:28.02#ibcon#wrote, iclass 6, count 2 2006.257.10:48:28.02#ibcon#about to read 3, iclass 6, count 2 2006.257.10:48:28.05#ibcon#read 3, iclass 6, count 2 2006.257.10:48:28.05#ibcon#about to read 4, iclass 6, count 2 2006.257.10:48:28.05#ibcon#read 4, iclass 6, count 2 2006.257.10:48:28.05#ibcon#about to read 5, iclass 6, count 2 2006.257.10:48:28.05#ibcon#read 5, iclass 6, count 2 2006.257.10:48:28.05#ibcon#about to read 6, iclass 6, count 2 2006.257.10:48:28.05#ibcon#read 6, iclass 6, count 2 2006.257.10:48:28.05#ibcon#end of sib2, iclass 6, count 2 2006.257.10:48:28.05#ibcon#*after write, iclass 6, count 2 2006.257.10:48:28.05#ibcon#*before return 0, iclass 6, count 2 2006.257.10:48:28.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:48:28.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.10:48:28.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.10:48:28.05#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:28.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:48:28.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:48:28.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:48:28.17#ibcon#enter wrdev, iclass 6, count 0 2006.257.10:48:28.17#ibcon#first serial, iclass 6, count 0 2006.257.10:48:28.17#ibcon#enter sib2, iclass 6, count 0 2006.257.10:48:28.17#ibcon#flushed, iclass 6, count 0 2006.257.10:48:28.17#ibcon#about to write, iclass 6, count 0 2006.257.10:48:28.17#ibcon#wrote, iclass 6, count 0 2006.257.10:48:28.17#ibcon#about to read 3, iclass 6, count 0 2006.257.10:48:28.19#ibcon#read 3, iclass 6, count 0 2006.257.10:48:28.19#ibcon#about to read 4, iclass 6, count 0 2006.257.10:48:28.19#ibcon#read 4, iclass 6, count 0 2006.257.10:48:28.19#ibcon#about to read 5, iclass 6, count 0 2006.257.10:48:28.19#ibcon#read 5, iclass 6, count 0 2006.257.10:48:28.19#ibcon#about to read 6, iclass 6, count 0 2006.257.10:48:28.19#ibcon#read 6, iclass 6, count 0 2006.257.10:48:28.19#ibcon#end of sib2, iclass 6, count 0 2006.257.10:48:28.19#ibcon#*mode == 0, iclass 6, count 0 2006.257.10:48:28.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.10:48:28.19#ibcon#[27=USB\r\n] 2006.257.10:48:28.19#ibcon#*before write, iclass 6, count 0 2006.257.10:48:28.19#ibcon#enter sib2, iclass 6, count 0 2006.257.10:48:28.19#ibcon#flushed, iclass 6, count 0 2006.257.10:48:28.19#ibcon#about to write, iclass 6, count 0 2006.257.10:48:28.19#ibcon#wrote, iclass 6, count 0 2006.257.10:48:28.19#ibcon#about to read 3, iclass 6, count 0 2006.257.10:48:28.22#ibcon#read 3, iclass 6, count 0 2006.257.10:48:28.22#ibcon#about to read 4, iclass 6, count 0 2006.257.10:48:28.22#ibcon#read 4, iclass 6, count 0 2006.257.10:48:28.22#ibcon#about to read 5, iclass 6, count 0 2006.257.10:48:28.22#ibcon#read 5, iclass 6, count 0 2006.257.10:48:28.22#ibcon#about to read 6, iclass 6, count 0 2006.257.10:48:28.22#ibcon#read 6, iclass 6, count 0 2006.257.10:48:28.22#ibcon#end of sib2, iclass 6, count 0 2006.257.10:48:28.22#ibcon#*after write, iclass 6, count 0 2006.257.10:48:28.22#ibcon#*before return 0, iclass 6, count 0 2006.257.10:48:28.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:48:28.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.10:48:28.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.10:48:28.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.10:48:28.22$vck44/vblo=2,634.99 2006.257.10:48:28.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.10:48:28.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.10:48:28.22#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:28.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:48:28.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:48:28.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:48:28.22#ibcon#enter wrdev, iclass 10, count 0 2006.257.10:48:28.22#ibcon#first serial, iclass 10, count 0 2006.257.10:48:28.22#ibcon#enter sib2, iclass 10, count 0 2006.257.10:48:28.22#ibcon#flushed, iclass 10, count 0 2006.257.10:48:28.22#ibcon#about to write, iclass 10, count 0 2006.257.10:48:28.22#ibcon#wrote, iclass 10, count 0 2006.257.10:48:28.22#ibcon#about to read 3, iclass 10, count 0 2006.257.10:48:28.24#ibcon#read 3, iclass 10, count 0 2006.257.10:48:28.24#ibcon#about to read 4, iclass 10, count 0 2006.257.10:48:28.24#ibcon#read 4, iclass 10, count 0 2006.257.10:48:28.24#ibcon#about to read 5, iclass 10, count 0 2006.257.10:48:28.24#ibcon#read 5, iclass 10, count 0 2006.257.10:48:28.24#ibcon#about to read 6, iclass 10, count 0 2006.257.10:48:28.24#ibcon#read 6, iclass 10, count 0 2006.257.10:48:28.24#ibcon#end of sib2, iclass 10, count 0 2006.257.10:48:28.24#ibcon#*mode == 0, iclass 10, count 0 2006.257.10:48:28.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.10:48:28.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:48:28.24#ibcon#*before write, iclass 10, count 0 2006.257.10:48:28.24#ibcon#enter sib2, iclass 10, count 0 2006.257.10:48:28.24#ibcon#flushed, iclass 10, count 0 2006.257.10:48:28.24#ibcon#about to write, iclass 10, count 0 2006.257.10:48:28.24#ibcon#wrote, iclass 10, count 0 2006.257.10:48:28.24#ibcon#about to read 3, iclass 10, count 0 2006.257.10:48:28.28#ibcon#read 3, iclass 10, count 0 2006.257.10:48:28.28#ibcon#about to read 4, iclass 10, count 0 2006.257.10:48:28.28#ibcon#read 4, iclass 10, count 0 2006.257.10:48:28.28#ibcon#about to read 5, iclass 10, count 0 2006.257.10:48:28.28#ibcon#read 5, iclass 10, count 0 2006.257.10:48:28.28#ibcon#about to read 6, iclass 10, count 0 2006.257.10:48:28.28#ibcon#read 6, iclass 10, count 0 2006.257.10:48:28.28#ibcon#end of sib2, iclass 10, count 0 2006.257.10:48:28.28#ibcon#*after write, iclass 10, count 0 2006.257.10:48:28.28#ibcon#*before return 0, iclass 10, count 0 2006.257.10:48:28.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:48:28.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.10:48:28.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.10:48:28.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.10:48:28.28$vck44/vb=2,5 2006.257.10:48:28.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.10:48:28.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.10:48:28.28#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:28.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:28.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:28.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:28.34#ibcon#enter wrdev, iclass 12, count 2 2006.257.10:48:28.34#ibcon#first serial, iclass 12, count 2 2006.257.10:48:28.34#ibcon#enter sib2, iclass 12, count 2 2006.257.10:48:28.34#ibcon#flushed, iclass 12, count 2 2006.257.10:48:28.34#ibcon#about to write, iclass 12, count 2 2006.257.10:48:28.34#ibcon#wrote, iclass 12, count 2 2006.257.10:48:28.34#ibcon#about to read 3, iclass 12, count 2 2006.257.10:48:28.36#ibcon#read 3, iclass 12, count 2 2006.257.10:48:28.36#ibcon#about to read 4, iclass 12, count 2 2006.257.10:48:28.36#ibcon#read 4, iclass 12, count 2 2006.257.10:48:28.36#ibcon#about to read 5, iclass 12, count 2 2006.257.10:48:28.36#ibcon#read 5, iclass 12, count 2 2006.257.10:48:28.36#ibcon#about to read 6, iclass 12, count 2 2006.257.10:48:28.36#ibcon#read 6, iclass 12, count 2 2006.257.10:48:28.36#ibcon#end of sib2, iclass 12, count 2 2006.257.10:48:28.36#ibcon#*mode == 0, iclass 12, count 2 2006.257.10:48:28.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.10:48:28.36#ibcon#[27=AT02-05\r\n] 2006.257.10:48:28.36#ibcon#*before write, iclass 12, count 2 2006.257.10:48:28.36#ibcon#enter sib2, iclass 12, count 2 2006.257.10:48:28.36#ibcon#flushed, iclass 12, count 2 2006.257.10:48:28.36#ibcon#about to write, iclass 12, count 2 2006.257.10:48:28.36#ibcon#wrote, iclass 12, count 2 2006.257.10:48:28.36#ibcon#about to read 3, iclass 12, count 2 2006.257.10:48:28.39#ibcon#read 3, iclass 12, count 2 2006.257.10:48:28.39#ibcon#about to read 4, iclass 12, count 2 2006.257.10:48:28.39#ibcon#read 4, iclass 12, count 2 2006.257.10:48:28.39#ibcon#about to read 5, iclass 12, count 2 2006.257.10:48:28.39#ibcon#read 5, iclass 12, count 2 2006.257.10:48:28.39#ibcon#about to read 6, iclass 12, count 2 2006.257.10:48:28.39#ibcon#read 6, iclass 12, count 2 2006.257.10:48:28.39#ibcon#end of sib2, iclass 12, count 2 2006.257.10:48:28.39#ibcon#*after write, iclass 12, count 2 2006.257.10:48:28.39#ibcon#*before return 0, iclass 12, count 2 2006.257.10:48:28.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:28.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.10:48:28.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.10:48:28.49#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:28.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:28.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:28.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:28.61#ibcon#enter wrdev, iclass 12, count 0 2006.257.10:48:28.61#ibcon#first serial, iclass 12, count 0 2006.257.10:48:28.61#ibcon#enter sib2, iclass 12, count 0 2006.257.10:48:28.61#ibcon#flushed, iclass 12, count 0 2006.257.10:48:28.61#ibcon#about to write, iclass 12, count 0 2006.257.10:48:28.61#ibcon#wrote, iclass 12, count 0 2006.257.10:48:28.61#ibcon#about to read 3, iclass 12, count 0 2006.257.10:48:28.63#ibcon#read 3, iclass 12, count 0 2006.257.10:48:28.63#ibcon#about to read 4, iclass 12, count 0 2006.257.10:48:28.63#ibcon#read 4, iclass 12, count 0 2006.257.10:48:28.63#ibcon#about to read 5, iclass 12, count 0 2006.257.10:48:28.63#ibcon#read 5, iclass 12, count 0 2006.257.10:48:28.63#ibcon#about to read 6, iclass 12, count 0 2006.257.10:48:28.63#ibcon#read 6, iclass 12, count 0 2006.257.10:48:28.63#ibcon#end of sib2, iclass 12, count 0 2006.257.10:48:28.63#ibcon#*mode == 0, iclass 12, count 0 2006.257.10:48:28.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.10:48:28.63#ibcon#[27=USB\r\n] 2006.257.10:48:28.63#ibcon#*before write, iclass 12, count 0 2006.257.10:48:28.63#ibcon#enter sib2, iclass 12, count 0 2006.257.10:48:28.63#ibcon#flushed, iclass 12, count 0 2006.257.10:48:28.63#ibcon#about to write, iclass 12, count 0 2006.257.10:48:28.63#ibcon#wrote, iclass 12, count 0 2006.257.10:48:28.63#ibcon#about to read 3, iclass 12, count 0 2006.257.10:48:28.66#ibcon#read 3, iclass 12, count 0 2006.257.10:48:28.66#ibcon#about to read 4, iclass 12, count 0 2006.257.10:48:28.66#ibcon#read 4, iclass 12, count 0 2006.257.10:48:28.66#ibcon#about to read 5, iclass 12, count 0 2006.257.10:48:28.66#ibcon#read 5, iclass 12, count 0 2006.257.10:48:28.66#ibcon#about to read 6, iclass 12, count 0 2006.257.10:48:28.66#ibcon#read 6, iclass 12, count 0 2006.257.10:48:28.66#ibcon#end of sib2, iclass 12, count 0 2006.257.10:48:28.66#ibcon#*after write, iclass 12, count 0 2006.257.10:48:28.66#ibcon#*before return 0, iclass 12, count 0 2006.257.10:48:28.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:28.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.10:48:28.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.10:48:28.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.10:48:28.66$vck44/vblo=3,649.99 2006.257.10:48:28.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.10:48:28.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.10:48:28.66#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:28.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:28.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:28.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:28.66#ibcon#enter wrdev, iclass 14, count 0 2006.257.10:48:28.66#ibcon#first serial, iclass 14, count 0 2006.257.10:48:28.66#ibcon#enter sib2, iclass 14, count 0 2006.257.10:48:28.66#ibcon#flushed, iclass 14, count 0 2006.257.10:48:28.66#ibcon#about to write, iclass 14, count 0 2006.257.10:48:28.66#ibcon#wrote, iclass 14, count 0 2006.257.10:48:28.66#ibcon#about to read 3, iclass 14, count 0 2006.257.10:48:28.68#ibcon#read 3, iclass 14, count 0 2006.257.10:48:28.68#ibcon#about to read 4, iclass 14, count 0 2006.257.10:48:28.68#ibcon#read 4, iclass 14, count 0 2006.257.10:48:28.68#ibcon#about to read 5, iclass 14, count 0 2006.257.10:48:28.68#ibcon#read 5, iclass 14, count 0 2006.257.10:48:28.68#ibcon#about to read 6, iclass 14, count 0 2006.257.10:48:28.68#ibcon#read 6, iclass 14, count 0 2006.257.10:48:28.68#ibcon#end of sib2, iclass 14, count 0 2006.257.10:48:28.68#ibcon#*mode == 0, iclass 14, count 0 2006.257.10:48:28.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.10:48:28.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:48:28.68#ibcon#*before write, iclass 14, count 0 2006.257.10:48:28.68#ibcon#enter sib2, iclass 14, count 0 2006.257.10:48:28.68#ibcon#flushed, iclass 14, count 0 2006.257.10:48:28.68#ibcon#about to write, iclass 14, count 0 2006.257.10:48:28.68#ibcon#wrote, iclass 14, count 0 2006.257.10:48:28.68#ibcon#about to read 3, iclass 14, count 0 2006.257.10:48:28.72#ibcon#read 3, iclass 14, count 0 2006.257.10:48:28.72#ibcon#about to read 4, iclass 14, count 0 2006.257.10:48:28.72#ibcon#read 4, iclass 14, count 0 2006.257.10:48:28.72#ibcon#about to read 5, iclass 14, count 0 2006.257.10:48:28.72#ibcon#read 5, iclass 14, count 0 2006.257.10:48:28.72#ibcon#about to read 6, iclass 14, count 0 2006.257.10:48:28.72#ibcon#read 6, iclass 14, count 0 2006.257.10:48:28.72#ibcon#end of sib2, iclass 14, count 0 2006.257.10:48:28.72#ibcon#*after write, iclass 14, count 0 2006.257.10:48:28.72#ibcon#*before return 0, iclass 14, count 0 2006.257.10:48:28.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:28.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.10:48:28.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.10:48:28.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.10:48:28.72$vck44/vb=3,4 2006.257.10:48:28.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.10:48:28.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.10:48:28.72#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:28.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:28.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:28.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:28.78#ibcon#enter wrdev, iclass 16, count 2 2006.257.10:48:28.78#ibcon#first serial, iclass 16, count 2 2006.257.10:48:28.78#ibcon#enter sib2, iclass 16, count 2 2006.257.10:48:28.78#ibcon#flushed, iclass 16, count 2 2006.257.10:48:28.78#ibcon#about to write, iclass 16, count 2 2006.257.10:48:28.78#ibcon#wrote, iclass 16, count 2 2006.257.10:48:28.78#ibcon#about to read 3, iclass 16, count 2 2006.257.10:48:28.80#ibcon#read 3, iclass 16, count 2 2006.257.10:48:28.80#ibcon#about to read 4, iclass 16, count 2 2006.257.10:48:28.80#ibcon#read 4, iclass 16, count 2 2006.257.10:48:28.80#ibcon#about to read 5, iclass 16, count 2 2006.257.10:48:28.80#ibcon#read 5, iclass 16, count 2 2006.257.10:48:28.80#ibcon#about to read 6, iclass 16, count 2 2006.257.10:48:28.80#ibcon#read 6, iclass 16, count 2 2006.257.10:48:28.80#ibcon#end of sib2, iclass 16, count 2 2006.257.10:48:28.80#ibcon#*mode == 0, iclass 16, count 2 2006.257.10:48:28.80#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.10:48:28.80#ibcon#[27=AT03-04\r\n] 2006.257.10:48:28.80#ibcon#*before write, iclass 16, count 2 2006.257.10:48:28.80#ibcon#enter sib2, iclass 16, count 2 2006.257.10:48:28.80#ibcon#flushed, iclass 16, count 2 2006.257.10:48:28.80#ibcon#about to write, iclass 16, count 2 2006.257.10:48:28.80#ibcon#wrote, iclass 16, count 2 2006.257.10:48:28.80#ibcon#about to read 3, iclass 16, count 2 2006.257.10:48:28.83#ibcon#read 3, iclass 16, count 2 2006.257.10:48:28.83#ibcon#about to read 4, iclass 16, count 2 2006.257.10:48:28.83#ibcon#read 4, iclass 16, count 2 2006.257.10:48:28.83#ibcon#about to read 5, iclass 16, count 2 2006.257.10:48:28.83#ibcon#read 5, iclass 16, count 2 2006.257.10:48:28.83#ibcon#about to read 6, iclass 16, count 2 2006.257.10:48:28.83#ibcon#read 6, iclass 16, count 2 2006.257.10:48:28.83#ibcon#end of sib2, iclass 16, count 2 2006.257.10:48:28.83#ibcon#*after write, iclass 16, count 2 2006.257.10:48:28.83#ibcon#*before return 0, iclass 16, count 2 2006.257.10:48:28.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:28.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.10:48:28.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.10:48:28.83#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:28.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:28.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:28.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:28.95#ibcon#enter wrdev, iclass 16, count 0 2006.257.10:48:28.95#ibcon#first serial, iclass 16, count 0 2006.257.10:48:28.95#ibcon#enter sib2, iclass 16, count 0 2006.257.10:48:28.95#ibcon#flushed, iclass 16, count 0 2006.257.10:48:28.95#ibcon#about to write, iclass 16, count 0 2006.257.10:48:28.95#ibcon#wrote, iclass 16, count 0 2006.257.10:48:28.95#ibcon#about to read 3, iclass 16, count 0 2006.257.10:48:28.97#ibcon#read 3, iclass 16, count 0 2006.257.10:48:28.97#ibcon#about to read 4, iclass 16, count 0 2006.257.10:48:28.97#ibcon#read 4, iclass 16, count 0 2006.257.10:48:28.97#ibcon#about to read 5, iclass 16, count 0 2006.257.10:48:28.97#ibcon#read 5, iclass 16, count 0 2006.257.10:48:28.97#ibcon#about to read 6, iclass 16, count 0 2006.257.10:48:28.97#ibcon#read 6, iclass 16, count 0 2006.257.10:48:28.97#ibcon#end of sib2, iclass 16, count 0 2006.257.10:48:28.97#ibcon#*mode == 0, iclass 16, count 0 2006.257.10:48:28.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.10:48:28.97#ibcon#[27=USB\r\n] 2006.257.10:48:28.97#ibcon#*before write, iclass 16, count 0 2006.257.10:48:28.97#ibcon#enter sib2, iclass 16, count 0 2006.257.10:48:28.97#ibcon#flushed, iclass 16, count 0 2006.257.10:48:28.97#ibcon#about to write, iclass 16, count 0 2006.257.10:48:28.97#ibcon#wrote, iclass 16, count 0 2006.257.10:48:28.97#ibcon#about to read 3, iclass 16, count 0 2006.257.10:48:29.00#ibcon#read 3, iclass 16, count 0 2006.257.10:48:29.00#ibcon#about to read 4, iclass 16, count 0 2006.257.10:48:29.00#ibcon#read 4, iclass 16, count 0 2006.257.10:48:29.00#ibcon#about to read 5, iclass 16, count 0 2006.257.10:48:29.00#ibcon#read 5, iclass 16, count 0 2006.257.10:48:29.00#ibcon#about to read 6, iclass 16, count 0 2006.257.10:48:29.00#ibcon#read 6, iclass 16, count 0 2006.257.10:48:29.00#ibcon#end of sib2, iclass 16, count 0 2006.257.10:48:29.00#ibcon#*after write, iclass 16, count 0 2006.257.10:48:29.00#ibcon#*before return 0, iclass 16, count 0 2006.257.10:48:29.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:29.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.10:48:29.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.10:48:29.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.10:48:29.00$vck44/vblo=4,679.99 2006.257.10:48:29.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.10:48:29.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.10:48:29.00#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:29.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:29.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:29.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:29.00#ibcon#enter wrdev, iclass 18, count 0 2006.257.10:48:29.00#ibcon#first serial, iclass 18, count 0 2006.257.10:48:29.00#ibcon#enter sib2, iclass 18, count 0 2006.257.10:48:29.00#ibcon#flushed, iclass 18, count 0 2006.257.10:48:29.00#ibcon#about to write, iclass 18, count 0 2006.257.10:48:29.00#ibcon#wrote, iclass 18, count 0 2006.257.10:48:29.00#ibcon#about to read 3, iclass 18, count 0 2006.257.10:48:29.02#ibcon#read 3, iclass 18, count 0 2006.257.10:48:29.02#ibcon#about to read 4, iclass 18, count 0 2006.257.10:48:29.02#ibcon#read 4, iclass 18, count 0 2006.257.10:48:29.02#ibcon#about to read 5, iclass 18, count 0 2006.257.10:48:29.02#ibcon#read 5, iclass 18, count 0 2006.257.10:48:29.02#ibcon#about to read 6, iclass 18, count 0 2006.257.10:48:29.02#ibcon#read 6, iclass 18, count 0 2006.257.10:48:29.02#ibcon#end of sib2, iclass 18, count 0 2006.257.10:48:29.02#ibcon#*mode == 0, iclass 18, count 0 2006.257.10:48:29.02#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.10:48:29.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:48:29.02#ibcon#*before write, iclass 18, count 0 2006.257.10:48:29.02#ibcon#enter sib2, iclass 18, count 0 2006.257.10:48:29.02#ibcon#flushed, iclass 18, count 0 2006.257.10:48:29.02#ibcon#about to write, iclass 18, count 0 2006.257.10:48:29.02#ibcon#wrote, iclass 18, count 0 2006.257.10:48:29.02#ibcon#about to read 3, iclass 18, count 0 2006.257.10:48:29.06#ibcon#read 3, iclass 18, count 0 2006.257.10:48:29.06#ibcon#about to read 4, iclass 18, count 0 2006.257.10:48:29.06#ibcon#read 4, iclass 18, count 0 2006.257.10:48:29.06#ibcon#about to read 5, iclass 18, count 0 2006.257.10:48:29.06#ibcon#read 5, iclass 18, count 0 2006.257.10:48:29.06#ibcon#about to read 6, iclass 18, count 0 2006.257.10:48:29.06#ibcon#read 6, iclass 18, count 0 2006.257.10:48:29.06#ibcon#end of sib2, iclass 18, count 0 2006.257.10:48:29.06#ibcon#*after write, iclass 18, count 0 2006.257.10:48:29.06#ibcon#*before return 0, iclass 18, count 0 2006.257.10:48:29.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:29.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.10:48:29.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.10:48:29.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.10:48:29.06$vck44/vb=4,5 2006.257.10:48:29.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.10:48:29.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.10:48:29.06#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:29.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:29.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:29.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:29.12#ibcon#enter wrdev, iclass 20, count 2 2006.257.10:48:29.12#ibcon#first serial, iclass 20, count 2 2006.257.10:48:29.12#ibcon#enter sib2, iclass 20, count 2 2006.257.10:48:29.12#ibcon#flushed, iclass 20, count 2 2006.257.10:48:29.12#ibcon#about to write, iclass 20, count 2 2006.257.10:48:29.12#ibcon#wrote, iclass 20, count 2 2006.257.10:48:29.12#ibcon#about to read 3, iclass 20, count 2 2006.257.10:48:29.14#ibcon#read 3, iclass 20, count 2 2006.257.10:48:29.14#ibcon#about to read 4, iclass 20, count 2 2006.257.10:48:29.14#ibcon#read 4, iclass 20, count 2 2006.257.10:48:29.14#ibcon#about to read 5, iclass 20, count 2 2006.257.10:48:29.14#ibcon#read 5, iclass 20, count 2 2006.257.10:48:29.14#ibcon#about to read 6, iclass 20, count 2 2006.257.10:48:29.14#ibcon#read 6, iclass 20, count 2 2006.257.10:48:29.14#ibcon#end of sib2, iclass 20, count 2 2006.257.10:48:29.14#ibcon#*mode == 0, iclass 20, count 2 2006.257.10:48:29.14#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.10:48:29.14#ibcon#[27=AT04-05\r\n] 2006.257.10:48:29.14#ibcon#*before write, iclass 20, count 2 2006.257.10:48:29.14#ibcon#enter sib2, iclass 20, count 2 2006.257.10:48:29.14#ibcon#flushed, iclass 20, count 2 2006.257.10:48:29.14#ibcon#about to write, iclass 20, count 2 2006.257.10:48:29.14#ibcon#wrote, iclass 20, count 2 2006.257.10:48:29.14#ibcon#about to read 3, iclass 20, count 2 2006.257.10:48:29.17#ibcon#read 3, iclass 20, count 2 2006.257.10:48:29.17#ibcon#about to read 4, iclass 20, count 2 2006.257.10:48:29.17#ibcon#read 4, iclass 20, count 2 2006.257.10:48:29.17#ibcon#about to read 5, iclass 20, count 2 2006.257.10:48:29.17#ibcon#read 5, iclass 20, count 2 2006.257.10:48:29.17#ibcon#about to read 6, iclass 20, count 2 2006.257.10:48:29.17#ibcon#read 6, iclass 20, count 2 2006.257.10:48:29.17#ibcon#end of sib2, iclass 20, count 2 2006.257.10:48:29.17#ibcon#*after write, iclass 20, count 2 2006.257.10:48:29.17#ibcon#*before return 0, iclass 20, count 2 2006.257.10:48:29.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:29.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.10:48:29.17#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.10:48:29.17#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:29.17#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:29.29#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:29.29#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:29.29#ibcon#enter wrdev, iclass 20, count 0 2006.257.10:48:29.29#ibcon#first serial, iclass 20, count 0 2006.257.10:48:29.29#ibcon#enter sib2, iclass 20, count 0 2006.257.10:48:29.29#ibcon#flushed, iclass 20, count 0 2006.257.10:48:29.29#ibcon#about to write, iclass 20, count 0 2006.257.10:48:29.29#ibcon#wrote, iclass 20, count 0 2006.257.10:48:29.29#ibcon#about to read 3, iclass 20, count 0 2006.257.10:48:29.31#ibcon#read 3, iclass 20, count 0 2006.257.10:48:29.31#ibcon#about to read 4, iclass 20, count 0 2006.257.10:48:29.31#ibcon#read 4, iclass 20, count 0 2006.257.10:48:29.31#ibcon#about to read 5, iclass 20, count 0 2006.257.10:48:29.31#ibcon#read 5, iclass 20, count 0 2006.257.10:48:29.31#ibcon#about to read 6, iclass 20, count 0 2006.257.10:48:29.31#ibcon#read 6, iclass 20, count 0 2006.257.10:48:29.31#ibcon#end of sib2, iclass 20, count 0 2006.257.10:48:29.31#ibcon#*mode == 0, iclass 20, count 0 2006.257.10:48:29.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.10:48:29.31#ibcon#[27=USB\r\n] 2006.257.10:48:29.31#ibcon#*before write, iclass 20, count 0 2006.257.10:48:29.31#ibcon#enter sib2, iclass 20, count 0 2006.257.10:48:29.31#ibcon#flushed, iclass 20, count 0 2006.257.10:48:29.31#ibcon#about to write, iclass 20, count 0 2006.257.10:48:29.31#ibcon#wrote, iclass 20, count 0 2006.257.10:48:29.31#ibcon#about to read 3, iclass 20, count 0 2006.257.10:48:29.34#ibcon#read 3, iclass 20, count 0 2006.257.10:48:29.34#ibcon#about to read 4, iclass 20, count 0 2006.257.10:48:29.34#ibcon#read 4, iclass 20, count 0 2006.257.10:48:29.34#ibcon#about to read 5, iclass 20, count 0 2006.257.10:48:29.34#ibcon#read 5, iclass 20, count 0 2006.257.10:48:29.34#ibcon#about to read 6, iclass 20, count 0 2006.257.10:48:29.34#ibcon#read 6, iclass 20, count 0 2006.257.10:48:29.34#ibcon#end of sib2, iclass 20, count 0 2006.257.10:48:29.34#ibcon#*after write, iclass 20, count 0 2006.257.10:48:29.34#ibcon#*before return 0, iclass 20, count 0 2006.257.10:48:29.34#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:29.34#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.10:48:29.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.10:48:29.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.10:48:29.34$vck44/vblo=5,709.99 2006.257.10:48:29.34#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.10:48:29.34#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.10:48:29.34#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:29.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:29.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:29.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:29.34#ibcon#enter wrdev, iclass 22, count 0 2006.257.10:48:29.34#ibcon#first serial, iclass 22, count 0 2006.257.10:48:29.34#ibcon#enter sib2, iclass 22, count 0 2006.257.10:48:29.34#ibcon#flushed, iclass 22, count 0 2006.257.10:48:29.34#ibcon#about to write, iclass 22, count 0 2006.257.10:48:29.34#ibcon#wrote, iclass 22, count 0 2006.257.10:48:29.34#ibcon#about to read 3, iclass 22, count 0 2006.257.10:48:29.36#ibcon#read 3, iclass 22, count 0 2006.257.10:48:29.36#ibcon#about to read 4, iclass 22, count 0 2006.257.10:48:29.36#ibcon#read 4, iclass 22, count 0 2006.257.10:48:29.36#ibcon#about to read 5, iclass 22, count 0 2006.257.10:48:29.36#ibcon#read 5, iclass 22, count 0 2006.257.10:48:29.36#ibcon#about to read 6, iclass 22, count 0 2006.257.10:48:29.36#ibcon#read 6, iclass 22, count 0 2006.257.10:48:29.36#ibcon#end of sib2, iclass 22, count 0 2006.257.10:48:29.36#ibcon#*mode == 0, iclass 22, count 0 2006.257.10:48:29.36#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.10:48:29.36#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:48:29.36#ibcon#*before write, iclass 22, count 0 2006.257.10:48:29.36#ibcon#enter sib2, iclass 22, count 0 2006.257.10:48:29.36#ibcon#flushed, iclass 22, count 0 2006.257.10:48:29.36#ibcon#about to write, iclass 22, count 0 2006.257.10:48:29.36#ibcon#wrote, iclass 22, count 0 2006.257.10:48:29.36#ibcon#about to read 3, iclass 22, count 0 2006.257.10:48:29.40#ibcon#read 3, iclass 22, count 0 2006.257.10:48:29.40#ibcon#about to read 4, iclass 22, count 0 2006.257.10:48:29.40#ibcon#read 4, iclass 22, count 0 2006.257.10:48:29.40#ibcon#about to read 5, iclass 22, count 0 2006.257.10:48:29.40#ibcon#read 5, iclass 22, count 0 2006.257.10:48:29.40#ibcon#about to read 6, iclass 22, count 0 2006.257.10:48:29.40#ibcon#read 6, iclass 22, count 0 2006.257.10:48:29.40#ibcon#end of sib2, iclass 22, count 0 2006.257.10:48:29.40#ibcon#*after write, iclass 22, count 0 2006.257.10:48:29.40#ibcon#*before return 0, iclass 22, count 0 2006.257.10:48:29.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:29.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.10:48:29.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.10:48:29.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.10:48:29.40$vck44/vb=5,4 2006.257.10:48:29.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.10:48:29.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.10:48:29.40#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:29.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:29.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:29.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:29.46#ibcon#enter wrdev, iclass 24, count 2 2006.257.10:48:29.46#ibcon#first serial, iclass 24, count 2 2006.257.10:48:29.46#ibcon#enter sib2, iclass 24, count 2 2006.257.10:48:29.46#ibcon#flushed, iclass 24, count 2 2006.257.10:48:29.46#ibcon#about to write, iclass 24, count 2 2006.257.10:48:29.46#ibcon#wrote, iclass 24, count 2 2006.257.10:48:29.46#ibcon#about to read 3, iclass 24, count 2 2006.257.10:48:29.48#ibcon#read 3, iclass 24, count 2 2006.257.10:48:29.48#ibcon#about to read 4, iclass 24, count 2 2006.257.10:48:29.48#ibcon#read 4, iclass 24, count 2 2006.257.10:48:29.48#ibcon#about to read 5, iclass 24, count 2 2006.257.10:48:29.48#ibcon#read 5, iclass 24, count 2 2006.257.10:48:29.48#ibcon#about to read 6, iclass 24, count 2 2006.257.10:48:29.48#ibcon#read 6, iclass 24, count 2 2006.257.10:48:29.48#ibcon#end of sib2, iclass 24, count 2 2006.257.10:48:29.48#ibcon#*mode == 0, iclass 24, count 2 2006.257.10:48:29.48#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.10:48:29.48#ibcon#[27=AT05-04\r\n] 2006.257.10:48:29.48#ibcon#*before write, iclass 24, count 2 2006.257.10:48:29.48#ibcon#enter sib2, iclass 24, count 2 2006.257.10:48:29.48#ibcon#flushed, iclass 24, count 2 2006.257.10:48:29.48#ibcon#about to write, iclass 24, count 2 2006.257.10:48:29.48#ibcon#wrote, iclass 24, count 2 2006.257.10:48:29.48#ibcon#about to read 3, iclass 24, count 2 2006.257.10:48:29.51#ibcon#read 3, iclass 24, count 2 2006.257.10:48:29.52#ibcon#about to read 4, iclass 24, count 2 2006.257.10:48:29.52#ibcon#read 4, iclass 24, count 2 2006.257.10:48:29.52#ibcon#about to read 5, iclass 24, count 2 2006.257.10:48:29.52#ibcon#read 5, iclass 24, count 2 2006.257.10:48:29.52#ibcon#about to read 6, iclass 24, count 2 2006.257.10:48:29.52#ibcon#read 6, iclass 24, count 2 2006.257.10:48:29.52#ibcon#end of sib2, iclass 24, count 2 2006.257.10:48:29.52#ibcon#*after write, iclass 24, count 2 2006.257.10:48:29.52#ibcon#*before return 0, iclass 24, count 2 2006.257.10:48:29.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:29.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.10:48:29.52#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.10:48:29.52#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:29.52#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:29.64#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:29.64#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:29.64#ibcon#enter wrdev, iclass 24, count 0 2006.257.10:48:29.64#ibcon#first serial, iclass 24, count 0 2006.257.10:48:29.64#ibcon#enter sib2, iclass 24, count 0 2006.257.10:48:29.64#ibcon#flushed, iclass 24, count 0 2006.257.10:48:29.64#ibcon#about to write, iclass 24, count 0 2006.257.10:48:29.64#ibcon#wrote, iclass 24, count 0 2006.257.10:48:29.64#ibcon#about to read 3, iclass 24, count 0 2006.257.10:48:29.66#ibcon#read 3, iclass 24, count 0 2006.257.10:48:29.66#ibcon#about to read 4, iclass 24, count 0 2006.257.10:48:29.66#ibcon#read 4, iclass 24, count 0 2006.257.10:48:29.66#ibcon#about to read 5, iclass 24, count 0 2006.257.10:48:29.66#ibcon#read 5, iclass 24, count 0 2006.257.10:48:29.66#ibcon#about to read 6, iclass 24, count 0 2006.257.10:48:29.66#ibcon#read 6, iclass 24, count 0 2006.257.10:48:29.66#ibcon#end of sib2, iclass 24, count 0 2006.257.10:48:29.66#ibcon#*mode == 0, iclass 24, count 0 2006.257.10:48:29.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.10:48:29.66#ibcon#[27=USB\r\n] 2006.257.10:48:29.66#ibcon#*before write, iclass 24, count 0 2006.257.10:48:29.66#ibcon#enter sib2, iclass 24, count 0 2006.257.10:48:29.66#ibcon#flushed, iclass 24, count 0 2006.257.10:48:29.66#ibcon#about to write, iclass 24, count 0 2006.257.10:48:29.66#ibcon#wrote, iclass 24, count 0 2006.257.10:48:29.66#ibcon#about to read 3, iclass 24, count 0 2006.257.10:48:29.69#ibcon#read 3, iclass 24, count 0 2006.257.10:48:29.69#ibcon#about to read 4, iclass 24, count 0 2006.257.10:48:29.69#ibcon#read 4, iclass 24, count 0 2006.257.10:48:29.69#ibcon#about to read 5, iclass 24, count 0 2006.257.10:48:29.69#ibcon#read 5, iclass 24, count 0 2006.257.10:48:29.69#ibcon#about to read 6, iclass 24, count 0 2006.257.10:48:29.69#ibcon#read 6, iclass 24, count 0 2006.257.10:48:29.69#ibcon#end of sib2, iclass 24, count 0 2006.257.10:48:29.69#ibcon#*after write, iclass 24, count 0 2006.257.10:48:29.69#ibcon#*before return 0, iclass 24, count 0 2006.257.10:48:29.69#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:29.69#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.10:48:29.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.10:48:29.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.10:48:29.69$vck44/vblo=6,719.99 2006.257.10:48:29.69#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.10:48:29.69#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.10:48:29.69#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:29.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:29.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:29.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:29.69#ibcon#enter wrdev, iclass 26, count 0 2006.257.10:48:29.69#ibcon#first serial, iclass 26, count 0 2006.257.10:48:29.69#ibcon#enter sib2, iclass 26, count 0 2006.257.10:48:29.69#ibcon#flushed, iclass 26, count 0 2006.257.10:48:29.69#ibcon#about to write, iclass 26, count 0 2006.257.10:48:29.69#ibcon#wrote, iclass 26, count 0 2006.257.10:48:29.69#ibcon#about to read 3, iclass 26, count 0 2006.257.10:48:29.71#ibcon#read 3, iclass 26, count 0 2006.257.10:48:29.71#ibcon#about to read 4, iclass 26, count 0 2006.257.10:48:29.71#ibcon#read 4, iclass 26, count 0 2006.257.10:48:29.71#ibcon#about to read 5, iclass 26, count 0 2006.257.10:48:29.71#ibcon#read 5, iclass 26, count 0 2006.257.10:48:29.71#ibcon#about to read 6, iclass 26, count 0 2006.257.10:48:29.71#ibcon#read 6, iclass 26, count 0 2006.257.10:48:29.71#ibcon#end of sib2, iclass 26, count 0 2006.257.10:48:29.71#ibcon#*mode == 0, iclass 26, count 0 2006.257.10:48:29.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.10:48:29.71#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:48:29.71#ibcon#*before write, iclass 26, count 0 2006.257.10:48:29.71#ibcon#enter sib2, iclass 26, count 0 2006.257.10:48:29.71#ibcon#flushed, iclass 26, count 0 2006.257.10:48:29.71#ibcon#about to write, iclass 26, count 0 2006.257.10:48:29.71#ibcon#wrote, iclass 26, count 0 2006.257.10:48:29.71#ibcon#about to read 3, iclass 26, count 0 2006.257.10:48:29.75#ibcon#read 3, iclass 26, count 0 2006.257.10:48:29.75#ibcon#about to read 4, iclass 26, count 0 2006.257.10:48:29.75#ibcon#read 4, iclass 26, count 0 2006.257.10:48:29.75#ibcon#about to read 5, iclass 26, count 0 2006.257.10:48:29.75#ibcon#read 5, iclass 26, count 0 2006.257.10:48:29.75#ibcon#about to read 6, iclass 26, count 0 2006.257.10:48:29.75#ibcon#read 6, iclass 26, count 0 2006.257.10:48:29.75#ibcon#end of sib2, iclass 26, count 0 2006.257.10:48:29.75#ibcon#*after write, iclass 26, count 0 2006.257.10:48:29.75#ibcon#*before return 0, iclass 26, count 0 2006.257.10:48:29.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:29.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.10:48:29.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.10:48:29.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.10:48:29.75$vck44/vb=6,4 2006.257.10:48:29.75#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.10:48:29.75#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.10:48:29.75#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:29.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:29.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:29.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:29.81#ibcon#enter wrdev, iclass 28, count 2 2006.257.10:48:29.81#ibcon#first serial, iclass 28, count 2 2006.257.10:48:29.81#ibcon#enter sib2, iclass 28, count 2 2006.257.10:48:29.81#ibcon#flushed, iclass 28, count 2 2006.257.10:48:29.81#ibcon#about to write, iclass 28, count 2 2006.257.10:48:29.81#ibcon#wrote, iclass 28, count 2 2006.257.10:48:29.81#ibcon#about to read 3, iclass 28, count 2 2006.257.10:48:29.83#ibcon#read 3, iclass 28, count 2 2006.257.10:48:29.83#ibcon#about to read 4, iclass 28, count 2 2006.257.10:48:29.83#ibcon#read 4, iclass 28, count 2 2006.257.10:48:29.83#ibcon#about to read 5, iclass 28, count 2 2006.257.10:48:29.83#ibcon#read 5, iclass 28, count 2 2006.257.10:48:29.83#ibcon#about to read 6, iclass 28, count 2 2006.257.10:48:29.83#ibcon#read 6, iclass 28, count 2 2006.257.10:48:29.83#ibcon#end of sib2, iclass 28, count 2 2006.257.10:48:29.83#ibcon#*mode == 0, iclass 28, count 2 2006.257.10:48:29.83#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.10:48:29.83#ibcon#[27=AT06-04\r\n] 2006.257.10:48:29.83#ibcon#*before write, iclass 28, count 2 2006.257.10:48:29.83#ibcon#enter sib2, iclass 28, count 2 2006.257.10:48:29.83#ibcon#flushed, iclass 28, count 2 2006.257.10:48:29.83#ibcon#about to write, iclass 28, count 2 2006.257.10:48:29.83#ibcon#wrote, iclass 28, count 2 2006.257.10:48:29.83#ibcon#about to read 3, iclass 28, count 2 2006.257.10:48:29.86#ibcon#read 3, iclass 28, count 2 2006.257.10:48:29.86#ibcon#about to read 4, iclass 28, count 2 2006.257.10:48:29.86#ibcon#read 4, iclass 28, count 2 2006.257.10:48:29.86#ibcon#about to read 5, iclass 28, count 2 2006.257.10:48:29.86#ibcon#read 5, iclass 28, count 2 2006.257.10:48:29.86#ibcon#about to read 6, iclass 28, count 2 2006.257.10:48:29.86#ibcon#read 6, iclass 28, count 2 2006.257.10:48:29.86#ibcon#end of sib2, iclass 28, count 2 2006.257.10:48:29.86#ibcon#*after write, iclass 28, count 2 2006.257.10:48:29.86#ibcon#*before return 0, iclass 28, count 2 2006.257.10:48:29.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:29.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.10:48:29.86#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.10:48:29.86#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:29.86#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:29.98#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:29.98#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:29.98#ibcon#enter wrdev, iclass 28, count 0 2006.257.10:48:29.98#ibcon#first serial, iclass 28, count 0 2006.257.10:48:29.98#ibcon#enter sib2, iclass 28, count 0 2006.257.10:48:29.98#ibcon#flushed, iclass 28, count 0 2006.257.10:48:29.98#ibcon#about to write, iclass 28, count 0 2006.257.10:48:29.98#ibcon#wrote, iclass 28, count 0 2006.257.10:48:29.98#ibcon#about to read 3, iclass 28, count 0 2006.257.10:48:30.00#ibcon#read 3, iclass 28, count 0 2006.257.10:48:30.00#ibcon#about to read 4, iclass 28, count 0 2006.257.10:48:30.00#ibcon#read 4, iclass 28, count 0 2006.257.10:48:30.00#ibcon#about to read 5, iclass 28, count 0 2006.257.10:48:30.00#ibcon#read 5, iclass 28, count 0 2006.257.10:48:30.00#ibcon#about to read 6, iclass 28, count 0 2006.257.10:48:30.00#ibcon#read 6, iclass 28, count 0 2006.257.10:48:30.00#ibcon#end of sib2, iclass 28, count 0 2006.257.10:48:30.00#ibcon#*mode == 0, iclass 28, count 0 2006.257.10:48:30.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.10:48:30.00#ibcon#[27=USB\r\n] 2006.257.10:48:30.00#ibcon#*before write, iclass 28, count 0 2006.257.10:48:30.00#ibcon#enter sib2, iclass 28, count 0 2006.257.10:48:30.00#ibcon#flushed, iclass 28, count 0 2006.257.10:48:30.00#ibcon#about to write, iclass 28, count 0 2006.257.10:48:30.00#ibcon#wrote, iclass 28, count 0 2006.257.10:48:30.00#ibcon#about to read 3, iclass 28, count 0 2006.257.10:48:30.03#ibcon#read 3, iclass 28, count 0 2006.257.10:48:30.03#ibcon#about to read 4, iclass 28, count 0 2006.257.10:48:30.03#ibcon#read 4, iclass 28, count 0 2006.257.10:48:30.03#ibcon#about to read 5, iclass 28, count 0 2006.257.10:48:30.03#ibcon#read 5, iclass 28, count 0 2006.257.10:48:30.03#ibcon#about to read 6, iclass 28, count 0 2006.257.10:48:30.03#ibcon#read 6, iclass 28, count 0 2006.257.10:48:30.03#ibcon#end of sib2, iclass 28, count 0 2006.257.10:48:30.03#ibcon#*after write, iclass 28, count 0 2006.257.10:48:30.03#ibcon#*before return 0, iclass 28, count 0 2006.257.10:48:30.03#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:30.03#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.10:48:30.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.10:48:30.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.10:48:30.03$vck44/vblo=7,734.99 2006.257.10:48:30.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.10:48:30.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.10:48:30.03#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:30.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:30.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:30.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:30.03#ibcon#enter wrdev, iclass 30, count 0 2006.257.10:48:30.03#ibcon#first serial, iclass 30, count 0 2006.257.10:48:30.03#ibcon#enter sib2, iclass 30, count 0 2006.257.10:48:30.03#ibcon#flushed, iclass 30, count 0 2006.257.10:48:30.03#ibcon#about to write, iclass 30, count 0 2006.257.10:48:30.03#ibcon#wrote, iclass 30, count 0 2006.257.10:48:30.03#ibcon#about to read 3, iclass 30, count 0 2006.257.10:48:30.05#ibcon#read 3, iclass 30, count 0 2006.257.10:48:30.05#ibcon#about to read 4, iclass 30, count 0 2006.257.10:48:30.05#ibcon#read 4, iclass 30, count 0 2006.257.10:48:30.05#ibcon#about to read 5, iclass 30, count 0 2006.257.10:48:30.05#ibcon#read 5, iclass 30, count 0 2006.257.10:48:30.05#ibcon#about to read 6, iclass 30, count 0 2006.257.10:48:30.05#ibcon#read 6, iclass 30, count 0 2006.257.10:48:30.05#ibcon#end of sib2, iclass 30, count 0 2006.257.10:48:30.05#ibcon#*mode == 0, iclass 30, count 0 2006.257.10:48:30.05#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.10:48:30.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:48:30.05#ibcon#*before write, iclass 30, count 0 2006.257.10:48:30.05#ibcon#enter sib2, iclass 30, count 0 2006.257.10:48:30.05#ibcon#flushed, iclass 30, count 0 2006.257.10:48:30.05#ibcon#about to write, iclass 30, count 0 2006.257.10:48:30.05#ibcon#wrote, iclass 30, count 0 2006.257.10:48:30.05#ibcon#about to read 3, iclass 30, count 0 2006.257.10:48:30.09#ibcon#read 3, iclass 30, count 0 2006.257.10:48:30.09#ibcon#about to read 4, iclass 30, count 0 2006.257.10:48:30.09#ibcon#read 4, iclass 30, count 0 2006.257.10:48:30.09#ibcon#about to read 5, iclass 30, count 0 2006.257.10:48:30.09#ibcon#read 5, iclass 30, count 0 2006.257.10:48:30.09#ibcon#about to read 6, iclass 30, count 0 2006.257.10:48:30.09#ibcon#read 6, iclass 30, count 0 2006.257.10:48:30.09#ibcon#end of sib2, iclass 30, count 0 2006.257.10:48:30.09#ibcon#*after write, iclass 30, count 0 2006.257.10:48:30.09#ibcon#*before return 0, iclass 30, count 0 2006.257.10:48:30.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:30.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.10:48:30.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.10:48:30.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.10:48:30.09$vck44/vb=7,4 2006.257.10:48:30.09#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.10:48:30.09#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.10:48:30.09#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:30.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:30.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:30.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:30.15#ibcon#enter wrdev, iclass 32, count 2 2006.257.10:48:30.15#ibcon#first serial, iclass 32, count 2 2006.257.10:48:30.15#ibcon#enter sib2, iclass 32, count 2 2006.257.10:48:30.15#ibcon#flushed, iclass 32, count 2 2006.257.10:48:30.15#ibcon#about to write, iclass 32, count 2 2006.257.10:48:30.15#ibcon#wrote, iclass 32, count 2 2006.257.10:48:30.15#ibcon#about to read 3, iclass 32, count 2 2006.257.10:48:30.17#ibcon#read 3, iclass 32, count 2 2006.257.10:48:30.17#ibcon#about to read 4, iclass 32, count 2 2006.257.10:48:30.17#ibcon#read 4, iclass 32, count 2 2006.257.10:48:30.17#ibcon#about to read 5, iclass 32, count 2 2006.257.10:48:30.17#ibcon#read 5, iclass 32, count 2 2006.257.10:48:30.17#ibcon#about to read 6, iclass 32, count 2 2006.257.10:48:30.17#ibcon#read 6, iclass 32, count 2 2006.257.10:48:30.17#ibcon#end of sib2, iclass 32, count 2 2006.257.10:48:30.17#ibcon#*mode == 0, iclass 32, count 2 2006.257.10:48:30.17#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.10:48:30.17#ibcon#[27=AT07-04\r\n] 2006.257.10:48:30.17#ibcon#*before write, iclass 32, count 2 2006.257.10:48:30.17#ibcon#enter sib2, iclass 32, count 2 2006.257.10:48:30.17#ibcon#flushed, iclass 32, count 2 2006.257.10:48:30.17#ibcon#about to write, iclass 32, count 2 2006.257.10:48:30.17#ibcon#wrote, iclass 32, count 2 2006.257.10:48:30.17#ibcon#about to read 3, iclass 32, count 2 2006.257.10:48:30.20#ibcon#read 3, iclass 32, count 2 2006.257.10:48:30.20#ibcon#about to read 4, iclass 32, count 2 2006.257.10:48:30.20#ibcon#read 4, iclass 32, count 2 2006.257.10:48:30.20#ibcon#about to read 5, iclass 32, count 2 2006.257.10:48:30.20#ibcon#read 5, iclass 32, count 2 2006.257.10:48:30.20#ibcon#about to read 6, iclass 32, count 2 2006.257.10:48:30.20#ibcon#read 6, iclass 32, count 2 2006.257.10:48:30.20#ibcon#end of sib2, iclass 32, count 2 2006.257.10:48:30.20#ibcon#*after write, iclass 32, count 2 2006.257.10:48:30.20#ibcon#*before return 0, iclass 32, count 2 2006.257.10:48:30.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:30.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.10:48:30.20#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.10:48:30.20#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:30.20#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:30.32#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:30.32#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:30.32#ibcon#enter wrdev, iclass 32, count 0 2006.257.10:48:30.32#ibcon#first serial, iclass 32, count 0 2006.257.10:48:30.32#ibcon#enter sib2, iclass 32, count 0 2006.257.10:48:30.32#ibcon#flushed, iclass 32, count 0 2006.257.10:48:30.32#ibcon#about to write, iclass 32, count 0 2006.257.10:48:30.32#ibcon#wrote, iclass 32, count 0 2006.257.10:48:30.32#ibcon#about to read 3, iclass 32, count 0 2006.257.10:48:30.34#ibcon#read 3, iclass 32, count 0 2006.257.10:48:30.34#ibcon#about to read 4, iclass 32, count 0 2006.257.10:48:30.34#ibcon#read 4, iclass 32, count 0 2006.257.10:48:30.34#ibcon#about to read 5, iclass 32, count 0 2006.257.10:48:30.34#ibcon#read 5, iclass 32, count 0 2006.257.10:48:30.34#ibcon#about to read 6, iclass 32, count 0 2006.257.10:48:30.34#ibcon#read 6, iclass 32, count 0 2006.257.10:48:30.34#ibcon#end of sib2, iclass 32, count 0 2006.257.10:48:30.34#ibcon#*mode == 0, iclass 32, count 0 2006.257.10:48:30.34#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.10:48:30.34#ibcon#[27=USB\r\n] 2006.257.10:48:30.34#ibcon#*before write, iclass 32, count 0 2006.257.10:48:30.34#ibcon#enter sib2, iclass 32, count 0 2006.257.10:48:30.34#ibcon#flushed, iclass 32, count 0 2006.257.10:48:30.34#ibcon#about to write, iclass 32, count 0 2006.257.10:48:30.34#ibcon#wrote, iclass 32, count 0 2006.257.10:48:30.34#ibcon#about to read 3, iclass 32, count 0 2006.257.10:48:30.37#ibcon#read 3, iclass 32, count 0 2006.257.10:48:30.37#ibcon#about to read 4, iclass 32, count 0 2006.257.10:48:30.37#ibcon#read 4, iclass 32, count 0 2006.257.10:48:30.37#ibcon#about to read 5, iclass 32, count 0 2006.257.10:48:30.37#ibcon#read 5, iclass 32, count 0 2006.257.10:48:30.37#ibcon#about to read 6, iclass 32, count 0 2006.257.10:48:30.37#ibcon#read 6, iclass 32, count 0 2006.257.10:48:30.37#ibcon#end of sib2, iclass 32, count 0 2006.257.10:48:30.37#ibcon#*after write, iclass 32, count 0 2006.257.10:48:30.37#ibcon#*before return 0, iclass 32, count 0 2006.257.10:48:30.37#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:30.37#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.10:48:30.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.10:48:30.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.10:48:30.37$vck44/vblo=8,744.99 2006.257.10:48:30.37#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.10:48:30.37#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.10:48:30.37#ibcon#ireg 17 cls_cnt 0 2006.257.10:48:30.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:30.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:30.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:30.37#ibcon#enter wrdev, iclass 34, count 0 2006.257.10:48:30.37#ibcon#first serial, iclass 34, count 0 2006.257.10:48:30.37#ibcon#enter sib2, iclass 34, count 0 2006.257.10:48:30.37#ibcon#flushed, iclass 34, count 0 2006.257.10:48:30.37#ibcon#about to write, iclass 34, count 0 2006.257.10:48:30.37#ibcon#wrote, iclass 34, count 0 2006.257.10:48:30.37#ibcon#about to read 3, iclass 34, count 0 2006.257.10:48:30.39#ibcon#read 3, iclass 34, count 0 2006.257.10:48:30.39#ibcon#about to read 4, iclass 34, count 0 2006.257.10:48:30.39#ibcon#read 4, iclass 34, count 0 2006.257.10:48:30.39#ibcon#about to read 5, iclass 34, count 0 2006.257.10:48:30.39#ibcon#read 5, iclass 34, count 0 2006.257.10:48:30.39#ibcon#about to read 6, iclass 34, count 0 2006.257.10:48:30.39#ibcon#read 6, iclass 34, count 0 2006.257.10:48:30.39#ibcon#end of sib2, iclass 34, count 0 2006.257.10:48:30.39#ibcon#*mode == 0, iclass 34, count 0 2006.257.10:48:30.39#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.10:48:30.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:48:30.39#ibcon#*before write, iclass 34, count 0 2006.257.10:48:30.39#ibcon#enter sib2, iclass 34, count 0 2006.257.10:48:30.39#ibcon#flushed, iclass 34, count 0 2006.257.10:48:30.39#ibcon#about to write, iclass 34, count 0 2006.257.10:48:30.39#ibcon#wrote, iclass 34, count 0 2006.257.10:48:30.39#ibcon#about to read 3, iclass 34, count 0 2006.257.10:48:30.43#ibcon#read 3, iclass 34, count 0 2006.257.10:48:30.43#ibcon#about to read 4, iclass 34, count 0 2006.257.10:48:30.43#ibcon#read 4, iclass 34, count 0 2006.257.10:48:30.43#ibcon#about to read 5, iclass 34, count 0 2006.257.10:48:30.43#ibcon#read 5, iclass 34, count 0 2006.257.10:48:30.43#ibcon#about to read 6, iclass 34, count 0 2006.257.10:48:30.43#ibcon#read 6, iclass 34, count 0 2006.257.10:48:30.43#ibcon#end of sib2, iclass 34, count 0 2006.257.10:48:30.43#ibcon#*after write, iclass 34, count 0 2006.257.10:48:30.43#ibcon#*before return 0, iclass 34, count 0 2006.257.10:48:30.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:30.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.10:48:30.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.10:48:30.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.10:48:30.43$vck44/vb=8,4 2006.257.10:48:30.43#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.10:48:30.43#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.10:48:30.43#ibcon#ireg 11 cls_cnt 2 2006.257.10:48:30.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:30.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:30.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:30.49#ibcon#enter wrdev, iclass 36, count 2 2006.257.10:48:30.49#ibcon#first serial, iclass 36, count 2 2006.257.10:48:30.49#ibcon#enter sib2, iclass 36, count 2 2006.257.10:48:30.49#ibcon#flushed, iclass 36, count 2 2006.257.10:48:30.49#ibcon#about to write, iclass 36, count 2 2006.257.10:48:30.49#ibcon#wrote, iclass 36, count 2 2006.257.10:48:30.49#ibcon#about to read 3, iclass 36, count 2 2006.257.10:48:30.51#ibcon#read 3, iclass 36, count 2 2006.257.10:48:30.51#ibcon#about to read 4, iclass 36, count 2 2006.257.10:48:30.51#ibcon#read 4, iclass 36, count 2 2006.257.10:48:30.51#ibcon#about to read 5, iclass 36, count 2 2006.257.10:48:30.51#ibcon#read 5, iclass 36, count 2 2006.257.10:48:30.51#ibcon#about to read 6, iclass 36, count 2 2006.257.10:48:30.51#ibcon#read 6, iclass 36, count 2 2006.257.10:48:30.51#ibcon#end of sib2, iclass 36, count 2 2006.257.10:48:30.51#ibcon#*mode == 0, iclass 36, count 2 2006.257.10:48:30.51#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.10:48:30.51#ibcon#[27=AT08-04\r\n] 2006.257.10:48:30.51#ibcon#*before write, iclass 36, count 2 2006.257.10:48:30.51#ibcon#enter sib2, iclass 36, count 2 2006.257.10:48:30.51#ibcon#flushed, iclass 36, count 2 2006.257.10:48:30.51#ibcon#about to write, iclass 36, count 2 2006.257.10:48:30.51#ibcon#wrote, iclass 36, count 2 2006.257.10:48:30.51#ibcon#about to read 3, iclass 36, count 2 2006.257.10:48:30.54#ibcon#read 3, iclass 36, count 2 2006.257.10:48:30.54#ibcon#about to read 4, iclass 36, count 2 2006.257.10:48:30.54#ibcon#read 4, iclass 36, count 2 2006.257.10:48:30.54#ibcon#about to read 5, iclass 36, count 2 2006.257.10:48:30.54#ibcon#read 5, iclass 36, count 2 2006.257.10:48:30.54#ibcon#about to read 6, iclass 36, count 2 2006.257.10:48:30.54#ibcon#read 6, iclass 36, count 2 2006.257.10:48:30.54#ibcon#end of sib2, iclass 36, count 2 2006.257.10:48:30.54#ibcon#*after write, iclass 36, count 2 2006.257.10:48:30.54#ibcon#*before return 0, iclass 36, count 2 2006.257.10:48:30.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:30.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.10:48:30.54#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.10:48:30.54#ibcon#ireg 7 cls_cnt 0 2006.257.10:48:30.54#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:30.66#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:30.66#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:30.66#ibcon#enter wrdev, iclass 36, count 0 2006.257.10:48:30.66#ibcon#first serial, iclass 36, count 0 2006.257.10:48:30.66#ibcon#enter sib2, iclass 36, count 0 2006.257.10:48:30.66#ibcon#flushed, iclass 36, count 0 2006.257.10:48:30.66#ibcon#about to write, iclass 36, count 0 2006.257.10:48:30.66#ibcon#wrote, iclass 36, count 0 2006.257.10:48:30.66#ibcon#about to read 3, iclass 36, count 0 2006.257.10:48:30.68#ibcon#read 3, iclass 36, count 0 2006.257.10:48:30.68#ibcon#about to read 4, iclass 36, count 0 2006.257.10:48:30.68#ibcon#read 4, iclass 36, count 0 2006.257.10:48:30.68#ibcon#about to read 5, iclass 36, count 0 2006.257.10:48:30.68#ibcon#read 5, iclass 36, count 0 2006.257.10:48:30.68#ibcon#about to read 6, iclass 36, count 0 2006.257.10:48:30.68#ibcon#read 6, iclass 36, count 0 2006.257.10:48:30.68#ibcon#end of sib2, iclass 36, count 0 2006.257.10:48:30.68#ibcon#*mode == 0, iclass 36, count 0 2006.257.10:48:30.68#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.10:48:30.68#ibcon#[27=USB\r\n] 2006.257.10:48:30.68#ibcon#*before write, iclass 36, count 0 2006.257.10:48:30.68#ibcon#enter sib2, iclass 36, count 0 2006.257.10:48:30.68#ibcon#flushed, iclass 36, count 0 2006.257.10:48:30.68#ibcon#about to write, iclass 36, count 0 2006.257.10:48:30.68#ibcon#wrote, iclass 36, count 0 2006.257.10:48:30.68#ibcon#about to read 3, iclass 36, count 0 2006.257.10:48:30.71#ibcon#read 3, iclass 36, count 0 2006.257.10:48:30.71#ibcon#about to read 4, iclass 36, count 0 2006.257.10:48:30.71#ibcon#read 4, iclass 36, count 0 2006.257.10:48:30.71#ibcon#about to read 5, iclass 36, count 0 2006.257.10:48:30.71#ibcon#read 5, iclass 36, count 0 2006.257.10:48:30.71#ibcon#about to read 6, iclass 36, count 0 2006.257.10:48:30.71#ibcon#read 6, iclass 36, count 0 2006.257.10:48:30.71#ibcon#end of sib2, iclass 36, count 0 2006.257.10:48:30.71#ibcon#*after write, iclass 36, count 0 2006.257.10:48:30.71#ibcon#*before return 0, iclass 36, count 0 2006.257.10:48:30.71#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:30.71#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.10:48:30.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.10:48:30.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.10:48:30.71$vck44/vabw=wide 2006.257.10:48:30.71#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.10:48:30.71#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.10:48:30.71#ibcon#ireg 8 cls_cnt 0 2006.257.10:48:30.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:30.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:30.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:30.71#ibcon#enter wrdev, iclass 38, count 0 2006.257.10:48:30.71#ibcon#first serial, iclass 38, count 0 2006.257.10:48:30.71#ibcon#enter sib2, iclass 38, count 0 2006.257.10:48:30.71#ibcon#flushed, iclass 38, count 0 2006.257.10:48:30.71#ibcon#about to write, iclass 38, count 0 2006.257.10:48:30.71#ibcon#wrote, iclass 38, count 0 2006.257.10:48:30.71#ibcon#about to read 3, iclass 38, count 0 2006.257.10:48:30.73#ibcon#read 3, iclass 38, count 0 2006.257.10:48:30.73#ibcon#about to read 4, iclass 38, count 0 2006.257.10:48:30.73#ibcon#read 4, iclass 38, count 0 2006.257.10:48:30.73#ibcon#about to read 5, iclass 38, count 0 2006.257.10:48:30.73#ibcon#read 5, iclass 38, count 0 2006.257.10:48:30.73#ibcon#about to read 6, iclass 38, count 0 2006.257.10:48:30.73#ibcon#read 6, iclass 38, count 0 2006.257.10:48:30.73#ibcon#end of sib2, iclass 38, count 0 2006.257.10:48:30.73#ibcon#*mode == 0, iclass 38, count 0 2006.257.10:48:30.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.10:48:30.73#ibcon#[25=BW32\r\n] 2006.257.10:48:30.73#ibcon#*before write, iclass 38, count 0 2006.257.10:48:30.73#ibcon#enter sib2, iclass 38, count 0 2006.257.10:48:30.73#ibcon#flushed, iclass 38, count 0 2006.257.10:48:30.73#ibcon#about to write, iclass 38, count 0 2006.257.10:48:30.73#ibcon#wrote, iclass 38, count 0 2006.257.10:48:30.73#ibcon#about to read 3, iclass 38, count 0 2006.257.10:48:30.76#ibcon#read 3, iclass 38, count 0 2006.257.10:48:30.76#ibcon#about to read 4, iclass 38, count 0 2006.257.10:48:30.76#ibcon#read 4, iclass 38, count 0 2006.257.10:48:30.76#ibcon#about to read 5, iclass 38, count 0 2006.257.10:48:30.76#ibcon#read 5, iclass 38, count 0 2006.257.10:48:30.76#ibcon#about to read 6, iclass 38, count 0 2006.257.10:48:30.76#ibcon#read 6, iclass 38, count 0 2006.257.10:48:30.76#ibcon#end of sib2, iclass 38, count 0 2006.257.10:48:30.76#ibcon#*after write, iclass 38, count 0 2006.257.10:48:30.76#ibcon#*before return 0, iclass 38, count 0 2006.257.10:48:30.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:30.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.10:48:30.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.10:48:30.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.10:48:30.76$vck44/vbbw=wide 2006.257.10:48:30.76#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.10:48:30.76#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.10:48:30.76#ibcon#ireg 8 cls_cnt 0 2006.257.10:48:30.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:48:30.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:48:30.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:48:30.83#ibcon#enter wrdev, iclass 40, count 0 2006.257.10:48:30.83#ibcon#first serial, iclass 40, count 0 2006.257.10:48:30.83#ibcon#enter sib2, iclass 40, count 0 2006.257.10:48:30.83#ibcon#flushed, iclass 40, count 0 2006.257.10:48:30.83#ibcon#about to write, iclass 40, count 0 2006.257.10:48:30.83#ibcon#wrote, iclass 40, count 0 2006.257.10:48:30.83#ibcon#about to read 3, iclass 40, count 0 2006.257.10:48:30.85#ibcon#read 3, iclass 40, count 0 2006.257.10:48:30.85#ibcon#about to read 4, iclass 40, count 0 2006.257.10:48:30.85#ibcon#read 4, iclass 40, count 0 2006.257.10:48:30.85#ibcon#about to read 5, iclass 40, count 0 2006.257.10:48:30.85#ibcon#read 5, iclass 40, count 0 2006.257.10:48:30.85#ibcon#about to read 6, iclass 40, count 0 2006.257.10:48:30.85#ibcon#read 6, iclass 40, count 0 2006.257.10:48:30.85#ibcon#end of sib2, iclass 40, count 0 2006.257.10:48:30.85#ibcon#*mode == 0, iclass 40, count 0 2006.257.10:48:30.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.10:48:30.85#ibcon#[27=BW32\r\n] 2006.257.10:48:30.85#ibcon#*before write, iclass 40, count 0 2006.257.10:48:30.85#ibcon#enter sib2, iclass 40, count 0 2006.257.10:48:30.85#ibcon#flushed, iclass 40, count 0 2006.257.10:48:30.85#ibcon#about to write, iclass 40, count 0 2006.257.10:48:30.85#ibcon#wrote, iclass 40, count 0 2006.257.10:48:30.85#ibcon#about to read 3, iclass 40, count 0 2006.257.10:48:30.88#ibcon#read 3, iclass 40, count 0 2006.257.10:48:30.88#ibcon#about to read 4, iclass 40, count 0 2006.257.10:48:30.88#ibcon#read 4, iclass 40, count 0 2006.257.10:48:30.88#ibcon#about to read 5, iclass 40, count 0 2006.257.10:48:30.88#ibcon#read 5, iclass 40, count 0 2006.257.10:48:30.88#ibcon#about to read 6, iclass 40, count 0 2006.257.10:48:30.88#ibcon#read 6, iclass 40, count 0 2006.257.10:48:30.88#ibcon#end of sib2, iclass 40, count 0 2006.257.10:48:30.88#ibcon#*after write, iclass 40, count 0 2006.257.10:48:30.88#ibcon#*before return 0, iclass 40, count 0 2006.257.10:48:30.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:48:30.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.10:48:30.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.10:48:30.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.10:48:30.88$setupk4/ifdk4 2006.257.10:48:30.88$ifdk4/lo= 2006.257.10:48:30.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:48:30.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:48:30.88$ifdk4/patch= 2006.257.10:48:30.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:48:30.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:48:30.88$setupk4/!*+20s 2006.257.10:48:35.41#abcon#<5=/14 1.5 4.4 18.76 961014.0\r\n> 2006.257.10:48:35.43#abcon#{5=INTERFACE CLEAR} 2006.257.10:48:35.49#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:48:45.25$setupk4/"tpicd 2006.257.10:48:45.25$setupk4/echo=off 2006.257.10:48:45.25$setupk4/xlog=off 2006.257.10:48:45.25:!2006.257.10:52:45 2006.257.10:48:47.13#trakl#Source acquired 2006.257.10:48:48.13#flagr#flagr/antenna,acquired 2006.257.10:52:45.02:preob 2006.257.10:52:46.15/onsource/TRACKING 2006.257.10:52:46.15:!2006.257.10:52:55 2006.257.10:52:55.01:"tape 2006.257.10:52:55.02:"st=record 2006.257.10:52:55.02:data_valid=on 2006.257.10:52:55.02:midob 2006.257.10:52:56.15/onsource/TRACKING 2006.257.10:52:56.15/wx/18.71,1014.0,96 2006.257.10:52:56.31/cable/+6.4768E-03 2006.257.10:52:57.40/va/01,08,usb,yes,30,32 2006.257.10:52:57.40/va/02,07,usb,yes,33,33 2006.257.10:52:57.40/va/03,08,usb,yes,29,31 2006.257.10:52:57.40/va/04,07,usb,yes,34,35 2006.257.10:52:57.40/va/05,04,usb,yes,30,30 2006.257.10:52:57.40/va/06,04,usb,yes,33,33 2006.257.10:52:57.40/va/07,04,usb,yes,34,35 2006.257.10:52:57.40/va/08,04,usb,yes,28,35 2006.257.10:52:57.63/valo/01,524.99,yes,locked 2006.257.10:52:57.63/valo/02,534.99,yes,locked 2006.257.10:52:57.63/valo/03,564.99,yes,locked 2006.257.10:52:57.63/valo/04,624.99,yes,locked 2006.257.10:52:57.63/valo/05,734.99,yes,locked 2006.257.10:52:57.63/valo/06,814.99,yes,locked 2006.257.10:52:57.63/valo/07,864.99,yes,locked 2006.257.10:52:57.63/valo/08,884.99,yes,locked 2006.257.10:52:58.72/vb/01,04,usb,yes,30,28 2006.257.10:52:58.72/vb/02,05,usb,yes,28,28 2006.257.10:52:58.72/vb/03,04,usb,yes,29,32 2006.257.10:52:58.72/vb/04,05,usb,yes,30,28 2006.257.10:52:58.72/vb/05,04,usb,yes,26,28 2006.257.10:52:58.72/vb/06,04,usb,yes,30,27 2006.257.10:52:58.72/vb/07,04,usb,yes,30,30 2006.257.10:52:58.72/vb/08,04,usb,yes,28,31 2006.257.10:52:58.95/vblo/01,629.99,yes,locked 2006.257.10:52:58.95/vblo/02,634.99,yes,locked 2006.257.10:52:58.95/vblo/03,649.99,yes,locked 2006.257.10:52:58.95/vblo/04,679.99,yes,locked 2006.257.10:52:58.95/vblo/05,709.99,yes,locked 2006.257.10:52:58.95/vblo/06,719.99,yes,locked 2006.257.10:52:58.95/vblo/07,734.99,yes,locked 2006.257.10:52:58.95/vblo/08,744.99,yes,locked 2006.257.10:52:59.10/vabw/8 2006.257.10:52:59.25/vbbw/8 2006.257.10:52:59.34/xfe/off,on,15.2 2006.257.10:52:59.73/ifatt/23,28,28,28 2006.257.10:53:00.07/fmout-gps/S +4.64E-07 2006.257.10:53:00.11:!2006.257.10:55:35 2006.257.10:55:35.01:data_valid=off 2006.257.10:55:35.01:"et 2006.257.10:55:35.02:!+3s 2006.257.10:55:38.04:"tape 2006.257.10:55:38.04:postob 2006.257.10:55:38.14/cable/+6.4771E-03 2006.257.10:55:38.15/wx/18.68,1014.1,96 2006.257.10:55:38.20/fmout-gps/S +4.63E-07 2006.257.10:55:38.20:scan_name=257-1102,jd0609,50 2006.257.10:55:38.20:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.10:55:39.14#flagr#flagr/antenna,new-source 2006.257.10:55:39.14:checkk5 2006.257.10:55:39.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.10:55:39.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.10:55:40.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.10:55:40.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.10:55:41.15/chk_obsdata//k5ts1/T2571052??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.10:55:41.54/chk_obsdata//k5ts2/T2571052??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.10:55:41.94/chk_obsdata//k5ts3/T2571052??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.10:55:42.34/chk_obsdata//k5ts4/T2571052??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.10:55:43.06/k5log//k5ts1_log_newline 2006.257.10:55:43.76/k5log//k5ts2_log_newline 2006.257.10:55:44.49/k5log//k5ts3_log_newline 2006.257.10:55:45.21/k5log//k5ts4_log_newline 2006.257.10:55:45.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.10:55:45.23:setupk4=1 2006.257.10:55:45.23$setupk4/echo=on 2006.257.10:55:45.23$setupk4/pcalon 2006.257.10:55:45.23$pcalon/"no phase cal control is implemented here 2006.257.10:55:45.23$setupk4/"tpicd=stop 2006.257.10:55:45.23$setupk4/"rec=synch_on 2006.257.10:55:45.23$setupk4/"rec_mode=128 2006.257.10:55:45.23$setupk4/!* 2006.257.10:55:45.23$setupk4/recpk4 2006.257.10:55:45.23$recpk4/recpatch= 2006.257.10:55:45.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.10:55:45.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.10:55:45.24$setupk4/vck44 2006.257.10:55:45.24$vck44/valo=1,524.99 2006.257.10:55:45.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.10:55:45.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.10:55:45.24#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:45.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:45.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:45.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:45.24#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:55:45.24#ibcon#first serial, iclass 37, count 0 2006.257.10:55:45.24#ibcon#enter sib2, iclass 37, count 0 2006.257.10:55:45.24#ibcon#flushed, iclass 37, count 0 2006.257.10:55:45.24#ibcon#about to write, iclass 37, count 0 2006.257.10:55:45.24#ibcon#wrote, iclass 37, count 0 2006.257.10:55:45.24#ibcon#about to read 3, iclass 37, count 0 2006.257.10:55:45.25#ibcon#read 3, iclass 37, count 0 2006.257.10:55:45.25#ibcon#about to read 4, iclass 37, count 0 2006.257.10:55:45.25#ibcon#read 4, iclass 37, count 0 2006.257.10:55:45.25#ibcon#about to read 5, iclass 37, count 0 2006.257.10:55:45.25#ibcon#read 5, iclass 37, count 0 2006.257.10:55:45.25#ibcon#about to read 6, iclass 37, count 0 2006.257.10:55:45.25#ibcon#read 6, iclass 37, count 0 2006.257.10:55:45.25#ibcon#end of sib2, iclass 37, count 0 2006.257.10:55:45.25#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:55:45.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:55:45.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.10:55:45.25#ibcon#*before write, iclass 37, count 0 2006.257.10:55:45.25#ibcon#enter sib2, iclass 37, count 0 2006.257.10:55:45.25#ibcon#flushed, iclass 37, count 0 2006.257.10:55:45.25#ibcon#about to write, iclass 37, count 0 2006.257.10:55:45.25#ibcon#wrote, iclass 37, count 0 2006.257.10:55:45.25#ibcon#about to read 3, iclass 37, count 0 2006.257.10:55:45.30#ibcon#read 3, iclass 37, count 0 2006.257.10:55:45.30#ibcon#about to read 4, iclass 37, count 0 2006.257.10:55:45.30#ibcon#read 4, iclass 37, count 0 2006.257.10:55:45.30#ibcon#about to read 5, iclass 37, count 0 2006.257.10:55:45.30#ibcon#read 5, iclass 37, count 0 2006.257.10:55:45.30#ibcon#about to read 6, iclass 37, count 0 2006.257.10:55:45.30#ibcon#read 6, iclass 37, count 0 2006.257.10:55:45.30#ibcon#end of sib2, iclass 37, count 0 2006.257.10:55:45.30#ibcon#*after write, iclass 37, count 0 2006.257.10:55:45.30#ibcon#*before return 0, iclass 37, count 0 2006.257.10:55:45.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:45.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:45.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:55:45.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:55:45.30$vck44/va=1,8 2006.257.10:55:45.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.10:55:45.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.10:55:45.30#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:45.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:45.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:45.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:45.30#ibcon#enter wrdev, iclass 39, count 2 2006.257.10:55:45.30#ibcon#first serial, iclass 39, count 2 2006.257.10:55:45.30#ibcon#enter sib2, iclass 39, count 2 2006.257.10:55:45.30#ibcon#flushed, iclass 39, count 2 2006.257.10:55:45.30#ibcon#about to write, iclass 39, count 2 2006.257.10:55:45.30#ibcon#wrote, iclass 39, count 2 2006.257.10:55:45.30#ibcon#about to read 3, iclass 39, count 2 2006.257.10:55:45.32#ibcon#read 3, iclass 39, count 2 2006.257.10:55:45.32#ibcon#about to read 4, iclass 39, count 2 2006.257.10:55:45.32#ibcon#read 4, iclass 39, count 2 2006.257.10:55:45.32#ibcon#about to read 5, iclass 39, count 2 2006.257.10:55:45.32#ibcon#read 5, iclass 39, count 2 2006.257.10:55:45.32#ibcon#about to read 6, iclass 39, count 2 2006.257.10:55:45.32#ibcon#read 6, iclass 39, count 2 2006.257.10:55:45.32#ibcon#end of sib2, iclass 39, count 2 2006.257.10:55:45.32#ibcon#*mode == 0, iclass 39, count 2 2006.257.10:55:45.32#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.10:55:45.32#ibcon#[25=AT01-08\r\n] 2006.257.10:55:45.32#ibcon#*before write, iclass 39, count 2 2006.257.10:55:45.32#ibcon#enter sib2, iclass 39, count 2 2006.257.10:55:45.32#ibcon#flushed, iclass 39, count 2 2006.257.10:55:45.32#ibcon#about to write, iclass 39, count 2 2006.257.10:55:45.32#ibcon#wrote, iclass 39, count 2 2006.257.10:55:45.32#ibcon#about to read 3, iclass 39, count 2 2006.257.10:55:45.35#ibcon#read 3, iclass 39, count 2 2006.257.10:55:45.35#ibcon#about to read 4, iclass 39, count 2 2006.257.10:55:45.35#ibcon#read 4, iclass 39, count 2 2006.257.10:55:45.35#ibcon#about to read 5, iclass 39, count 2 2006.257.10:55:45.35#ibcon#read 5, iclass 39, count 2 2006.257.10:55:45.35#ibcon#about to read 6, iclass 39, count 2 2006.257.10:55:45.35#ibcon#read 6, iclass 39, count 2 2006.257.10:55:45.35#ibcon#end of sib2, iclass 39, count 2 2006.257.10:55:45.35#ibcon#*after write, iclass 39, count 2 2006.257.10:55:45.35#ibcon#*before return 0, iclass 39, count 2 2006.257.10:55:45.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:45.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:45.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.10:55:45.35#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:45.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:45.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:45.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:45.47#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:55:45.47#ibcon#first serial, iclass 39, count 0 2006.257.10:55:45.47#ibcon#enter sib2, iclass 39, count 0 2006.257.10:55:45.47#ibcon#flushed, iclass 39, count 0 2006.257.10:55:45.47#ibcon#about to write, iclass 39, count 0 2006.257.10:55:45.47#ibcon#wrote, iclass 39, count 0 2006.257.10:55:45.47#ibcon#about to read 3, iclass 39, count 0 2006.257.10:55:45.49#ibcon#read 3, iclass 39, count 0 2006.257.10:55:45.49#ibcon#about to read 4, iclass 39, count 0 2006.257.10:55:45.49#ibcon#read 4, iclass 39, count 0 2006.257.10:55:45.49#ibcon#about to read 5, iclass 39, count 0 2006.257.10:55:45.49#ibcon#read 5, iclass 39, count 0 2006.257.10:55:45.49#ibcon#about to read 6, iclass 39, count 0 2006.257.10:55:45.49#ibcon#read 6, iclass 39, count 0 2006.257.10:55:45.49#ibcon#end of sib2, iclass 39, count 0 2006.257.10:55:45.49#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:55:45.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:55:45.49#ibcon#[25=USB\r\n] 2006.257.10:55:45.49#ibcon#*before write, iclass 39, count 0 2006.257.10:55:45.49#ibcon#enter sib2, iclass 39, count 0 2006.257.10:55:45.49#ibcon#flushed, iclass 39, count 0 2006.257.10:55:45.49#ibcon#about to write, iclass 39, count 0 2006.257.10:55:45.49#ibcon#wrote, iclass 39, count 0 2006.257.10:55:45.49#ibcon#about to read 3, iclass 39, count 0 2006.257.10:55:45.52#ibcon#read 3, iclass 39, count 0 2006.257.10:55:45.52#ibcon#about to read 4, iclass 39, count 0 2006.257.10:55:45.52#ibcon#read 4, iclass 39, count 0 2006.257.10:55:45.52#ibcon#about to read 5, iclass 39, count 0 2006.257.10:55:45.52#ibcon#read 5, iclass 39, count 0 2006.257.10:55:45.52#ibcon#about to read 6, iclass 39, count 0 2006.257.10:55:45.52#ibcon#read 6, iclass 39, count 0 2006.257.10:55:45.52#ibcon#end of sib2, iclass 39, count 0 2006.257.10:55:45.52#ibcon#*after write, iclass 39, count 0 2006.257.10:55:45.52#ibcon#*before return 0, iclass 39, count 0 2006.257.10:55:45.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:45.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:45.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:55:45.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:55:45.52$vck44/valo=2,534.99 2006.257.10:55:45.52#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.10:55:45.52#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.10:55:45.52#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:45.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:45.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:45.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:45.52#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:55:45.52#ibcon#first serial, iclass 3, count 0 2006.257.10:55:45.52#ibcon#enter sib2, iclass 3, count 0 2006.257.10:55:45.52#ibcon#flushed, iclass 3, count 0 2006.257.10:55:45.52#ibcon#about to write, iclass 3, count 0 2006.257.10:55:45.52#ibcon#wrote, iclass 3, count 0 2006.257.10:55:45.52#ibcon#about to read 3, iclass 3, count 0 2006.257.10:55:45.54#ibcon#read 3, iclass 3, count 0 2006.257.10:55:45.54#ibcon#about to read 4, iclass 3, count 0 2006.257.10:55:45.54#ibcon#read 4, iclass 3, count 0 2006.257.10:55:45.54#ibcon#about to read 5, iclass 3, count 0 2006.257.10:55:45.54#ibcon#read 5, iclass 3, count 0 2006.257.10:55:45.54#ibcon#about to read 6, iclass 3, count 0 2006.257.10:55:45.54#ibcon#read 6, iclass 3, count 0 2006.257.10:55:45.54#ibcon#end of sib2, iclass 3, count 0 2006.257.10:55:45.54#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:55:45.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:55:45.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.10:55:45.54#ibcon#*before write, iclass 3, count 0 2006.257.10:55:45.54#ibcon#enter sib2, iclass 3, count 0 2006.257.10:55:45.54#ibcon#flushed, iclass 3, count 0 2006.257.10:55:45.54#ibcon#about to write, iclass 3, count 0 2006.257.10:55:45.54#ibcon#wrote, iclass 3, count 0 2006.257.10:55:45.54#ibcon#about to read 3, iclass 3, count 0 2006.257.10:55:45.58#ibcon#read 3, iclass 3, count 0 2006.257.10:55:45.58#ibcon#about to read 4, iclass 3, count 0 2006.257.10:55:45.58#ibcon#read 4, iclass 3, count 0 2006.257.10:55:45.58#ibcon#about to read 5, iclass 3, count 0 2006.257.10:55:45.58#ibcon#read 5, iclass 3, count 0 2006.257.10:55:45.58#ibcon#about to read 6, iclass 3, count 0 2006.257.10:55:45.58#ibcon#read 6, iclass 3, count 0 2006.257.10:55:45.58#ibcon#end of sib2, iclass 3, count 0 2006.257.10:55:45.58#ibcon#*after write, iclass 3, count 0 2006.257.10:55:45.58#ibcon#*before return 0, iclass 3, count 0 2006.257.10:55:45.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:45.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:45.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:55:45.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:55:45.58$vck44/va=2,7 2006.257.10:55:45.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.10:55:45.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.10:55:45.58#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:45.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:45.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:45.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:45.64#ibcon#enter wrdev, iclass 5, count 2 2006.257.10:55:45.64#ibcon#first serial, iclass 5, count 2 2006.257.10:55:45.64#ibcon#enter sib2, iclass 5, count 2 2006.257.10:55:45.64#ibcon#flushed, iclass 5, count 2 2006.257.10:55:45.64#ibcon#about to write, iclass 5, count 2 2006.257.10:55:45.64#ibcon#wrote, iclass 5, count 2 2006.257.10:55:45.64#ibcon#about to read 3, iclass 5, count 2 2006.257.10:55:45.66#ibcon#read 3, iclass 5, count 2 2006.257.10:55:45.66#ibcon#about to read 4, iclass 5, count 2 2006.257.10:55:45.66#ibcon#read 4, iclass 5, count 2 2006.257.10:55:45.66#ibcon#about to read 5, iclass 5, count 2 2006.257.10:55:45.66#ibcon#read 5, iclass 5, count 2 2006.257.10:55:45.66#ibcon#about to read 6, iclass 5, count 2 2006.257.10:55:45.66#ibcon#read 6, iclass 5, count 2 2006.257.10:55:45.66#ibcon#end of sib2, iclass 5, count 2 2006.257.10:55:45.66#ibcon#*mode == 0, iclass 5, count 2 2006.257.10:55:45.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.10:55:45.66#ibcon#[25=AT02-07\r\n] 2006.257.10:55:45.66#ibcon#*before write, iclass 5, count 2 2006.257.10:55:45.66#ibcon#enter sib2, iclass 5, count 2 2006.257.10:55:45.66#ibcon#flushed, iclass 5, count 2 2006.257.10:55:45.66#ibcon#about to write, iclass 5, count 2 2006.257.10:55:45.66#ibcon#wrote, iclass 5, count 2 2006.257.10:55:45.66#ibcon#about to read 3, iclass 5, count 2 2006.257.10:55:45.69#ibcon#read 3, iclass 5, count 2 2006.257.10:55:45.69#ibcon#about to read 4, iclass 5, count 2 2006.257.10:55:45.69#ibcon#read 4, iclass 5, count 2 2006.257.10:55:45.69#ibcon#about to read 5, iclass 5, count 2 2006.257.10:55:45.69#ibcon#read 5, iclass 5, count 2 2006.257.10:55:45.69#ibcon#about to read 6, iclass 5, count 2 2006.257.10:55:45.69#ibcon#read 6, iclass 5, count 2 2006.257.10:55:45.69#ibcon#end of sib2, iclass 5, count 2 2006.257.10:55:45.69#ibcon#*after write, iclass 5, count 2 2006.257.10:55:45.69#ibcon#*before return 0, iclass 5, count 2 2006.257.10:55:45.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:45.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:45.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.10:55:45.69#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:45.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:45.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:45.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:45.81#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:55:45.81#ibcon#first serial, iclass 5, count 0 2006.257.10:55:45.81#ibcon#enter sib2, iclass 5, count 0 2006.257.10:55:45.81#ibcon#flushed, iclass 5, count 0 2006.257.10:55:45.81#ibcon#about to write, iclass 5, count 0 2006.257.10:55:45.81#ibcon#wrote, iclass 5, count 0 2006.257.10:55:45.81#ibcon#about to read 3, iclass 5, count 0 2006.257.10:55:45.83#ibcon#read 3, iclass 5, count 0 2006.257.10:55:45.83#ibcon#about to read 4, iclass 5, count 0 2006.257.10:55:45.83#ibcon#read 4, iclass 5, count 0 2006.257.10:55:45.83#ibcon#about to read 5, iclass 5, count 0 2006.257.10:55:45.83#ibcon#read 5, iclass 5, count 0 2006.257.10:55:45.83#ibcon#about to read 6, iclass 5, count 0 2006.257.10:55:45.83#ibcon#read 6, iclass 5, count 0 2006.257.10:55:45.83#ibcon#end of sib2, iclass 5, count 0 2006.257.10:55:45.83#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:55:45.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:55:45.83#ibcon#[25=USB\r\n] 2006.257.10:55:45.83#ibcon#*before write, iclass 5, count 0 2006.257.10:55:45.83#ibcon#enter sib2, iclass 5, count 0 2006.257.10:55:45.83#ibcon#flushed, iclass 5, count 0 2006.257.10:55:45.83#ibcon#about to write, iclass 5, count 0 2006.257.10:55:45.83#ibcon#wrote, iclass 5, count 0 2006.257.10:55:45.83#ibcon#about to read 3, iclass 5, count 0 2006.257.10:55:45.86#ibcon#read 3, iclass 5, count 0 2006.257.10:55:45.86#ibcon#about to read 4, iclass 5, count 0 2006.257.10:55:45.86#ibcon#read 4, iclass 5, count 0 2006.257.10:55:45.86#ibcon#about to read 5, iclass 5, count 0 2006.257.10:55:45.86#ibcon#read 5, iclass 5, count 0 2006.257.10:55:45.86#ibcon#about to read 6, iclass 5, count 0 2006.257.10:55:45.86#ibcon#read 6, iclass 5, count 0 2006.257.10:55:45.86#ibcon#end of sib2, iclass 5, count 0 2006.257.10:55:45.86#ibcon#*after write, iclass 5, count 0 2006.257.10:55:45.86#ibcon#*before return 0, iclass 5, count 0 2006.257.10:55:45.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:45.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:45.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:55:45.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:55:45.86$vck44/valo=3,564.99 2006.257.10:55:45.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.10:55:45.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.10:55:45.86#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:45.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:45.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:45.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:45.86#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:55:45.86#ibcon#first serial, iclass 7, count 0 2006.257.10:55:45.86#ibcon#enter sib2, iclass 7, count 0 2006.257.10:55:45.86#ibcon#flushed, iclass 7, count 0 2006.257.10:55:45.86#ibcon#about to write, iclass 7, count 0 2006.257.10:55:45.86#ibcon#wrote, iclass 7, count 0 2006.257.10:55:45.86#ibcon#about to read 3, iclass 7, count 0 2006.257.10:55:45.88#ibcon#read 3, iclass 7, count 0 2006.257.10:55:45.88#ibcon#about to read 4, iclass 7, count 0 2006.257.10:55:45.88#ibcon#read 4, iclass 7, count 0 2006.257.10:55:45.88#ibcon#about to read 5, iclass 7, count 0 2006.257.10:55:45.88#ibcon#read 5, iclass 7, count 0 2006.257.10:55:45.88#ibcon#about to read 6, iclass 7, count 0 2006.257.10:55:45.88#ibcon#read 6, iclass 7, count 0 2006.257.10:55:45.88#ibcon#end of sib2, iclass 7, count 0 2006.257.10:55:45.88#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:55:45.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:55:45.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.10:55:45.88#ibcon#*before write, iclass 7, count 0 2006.257.10:55:45.88#ibcon#enter sib2, iclass 7, count 0 2006.257.10:55:45.88#ibcon#flushed, iclass 7, count 0 2006.257.10:55:45.88#ibcon#about to write, iclass 7, count 0 2006.257.10:55:45.88#ibcon#wrote, iclass 7, count 0 2006.257.10:55:45.88#ibcon#about to read 3, iclass 7, count 0 2006.257.10:55:45.92#ibcon#read 3, iclass 7, count 0 2006.257.10:55:45.92#ibcon#about to read 4, iclass 7, count 0 2006.257.10:55:45.92#ibcon#read 4, iclass 7, count 0 2006.257.10:55:45.92#ibcon#about to read 5, iclass 7, count 0 2006.257.10:55:45.92#ibcon#read 5, iclass 7, count 0 2006.257.10:55:45.92#ibcon#about to read 6, iclass 7, count 0 2006.257.10:55:45.92#ibcon#read 6, iclass 7, count 0 2006.257.10:55:45.92#ibcon#end of sib2, iclass 7, count 0 2006.257.10:55:45.92#ibcon#*after write, iclass 7, count 0 2006.257.10:55:45.92#ibcon#*before return 0, iclass 7, count 0 2006.257.10:55:45.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:45.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:45.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:55:45.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:55:45.92$vck44/va=3,8 2006.257.10:55:45.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.10:55:45.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.10:55:45.92#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:45.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:45.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:45.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:45.98#ibcon#enter wrdev, iclass 11, count 2 2006.257.10:55:45.98#ibcon#first serial, iclass 11, count 2 2006.257.10:55:45.98#ibcon#enter sib2, iclass 11, count 2 2006.257.10:55:45.98#ibcon#flushed, iclass 11, count 2 2006.257.10:55:45.98#ibcon#about to write, iclass 11, count 2 2006.257.10:55:45.98#ibcon#wrote, iclass 11, count 2 2006.257.10:55:45.98#ibcon#about to read 3, iclass 11, count 2 2006.257.10:55:46.00#ibcon#read 3, iclass 11, count 2 2006.257.10:55:46.00#ibcon#about to read 4, iclass 11, count 2 2006.257.10:55:46.00#ibcon#read 4, iclass 11, count 2 2006.257.10:55:46.00#ibcon#about to read 5, iclass 11, count 2 2006.257.10:55:46.00#ibcon#read 5, iclass 11, count 2 2006.257.10:55:46.00#ibcon#about to read 6, iclass 11, count 2 2006.257.10:55:46.00#ibcon#read 6, iclass 11, count 2 2006.257.10:55:46.00#ibcon#end of sib2, iclass 11, count 2 2006.257.10:55:46.00#ibcon#*mode == 0, iclass 11, count 2 2006.257.10:55:46.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.10:55:46.00#ibcon#[25=AT03-08\r\n] 2006.257.10:55:46.00#ibcon#*before write, iclass 11, count 2 2006.257.10:55:46.00#ibcon#enter sib2, iclass 11, count 2 2006.257.10:55:46.00#ibcon#flushed, iclass 11, count 2 2006.257.10:55:46.00#ibcon#about to write, iclass 11, count 2 2006.257.10:55:46.00#ibcon#wrote, iclass 11, count 2 2006.257.10:55:46.00#ibcon#about to read 3, iclass 11, count 2 2006.257.10:55:46.03#ibcon#read 3, iclass 11, count 2 2006.257.10:55:46.03#ibcon#about to read 4, iclass 11, count 2 2006.257.10:55:46.03#ibcon#read 4, iclass 11, count 2 2006.257.10:55:46.03#ibcon#about to read 5, iclass 11, count 2 2006.257.10:55:46.03#ibcon#read 5, iclass 11, count 2 2006.257.10:55:46.03#ibcon#about to read 6, iclass 11, count 2 2006.257.10:55:46.03#ibcon#read 6, iclass 11, count 2 2006.257.10:55:46.03#ibcon#end of sib2, iclass 11, count 2 2006.257.10:55:46.03#ibcon#*after write, iclass 11, count 2 2006.257.10:55:46.03#ibcon#*before return 0, iclass 11, count 2 2006.257.10:55:46.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:46.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:46.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.10:55:46.03#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:46.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:46.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:46.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:46.15#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:55:46.15#ibcon#first serial, iclass 11, count 0 2006.257.10:55:46.15#ibcon#enter sib2, iclass 11, count 0 2006.257.10:55:46.15#ibcon#flushed, iclass 11, count 0 2006.257.10:55:46.15#ibcon#about to write, iclass 11, count 0 2006.257.10:55:46.15#ibcon#wrote, iclass 11, count 0 2006.257.10:55:46.15#ibcon#about to read 3, iclass 11, count 0 2006.257.10:55:46.17#ibcon#read 3, iclass 11, count 0 2006.257.10:55:46.17#ibcon#about to read 4, iclass 11, count 0 2006.257.10:55:46.17#ibcon#read 4, iclass 11, count 0 2006.257.10:55:46.17#ibcon#about to read 5, iclass 11, count 0 2006.257.10:55:46.17#ibcon#read 5, iclass 11, count 0 2006.257.10:55:46.17#ibcon#about to read 6, iclass 11, count 0 2006.257.10:55:46.17#ibcon#read 6, iclass 11, count 0 2006.257.10:55:46.17#ibcon#end of sib2, iclass 11, count 0 2006.257.10:55:46.17#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:55:46.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:55:46.17#ibcon#[25=USB\r\n] 2006.257.10:55:46.17#ibcon#*before write, iclass 11, count 0 2006.257.10:55:46.17#ibcon#enter sib2, iclass 11, count 0 2006.257.10:55:46.17#ibcon#flushed, iclass 11, count 0 2006.257.10:55:46.17#ibcon#about to write, iclass 11, count 0 2006.257.10:55:46.17#ibcon#wrote, iclass 11, count 0 2006.257.10:55:46.17#ibcon#about to read 3, iclass 11, count 0 2006.257.10:55:46.20#ibcon#read 3, iclass 11, count 0 2006.257.10:55:46.20#ibcon#about to read 4, iclass 11, count 0 2006.257.10:55:46.20#ibcon#read 4, iclass 11, count 0 2006.257.10:55:46.20#ibcon#about to read 5, iclass 11, count 0 2006.257.10:55:46.20#ibcon#read 5, iclass 11, count 0 2006.257.10:55:46.20#ibcon#about to read 6, iclass 11, count 0 2006.257.10:55:46.20#ibcon#read 6, iclass 11, count 0 2006.257.10:55:46.20#ibcon#end of sib2, iclass 11, count 0 2006.257.10:55:46.20#ibcon#*after write, iclass 11, count 0 2006.257.10:55:46.20#ibcon#*before return 0, iclass 11, count 0 2006.257.10:55:46.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:46.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:46.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:55:46.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:55:46.20$vck44/valo=4,624.99 2006.257.10:55:46.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.10:55:46.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.10:55:46.20#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:46.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:46.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:46.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:46.20#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:55:46.20#ibcon#first serial, iclass 13, count 0 2006.257.10:55:46.20#ibcon#enter sib2, iclass 13, count 0 2006.257.10:55:46.20#ibcon#flushed, iclass 13, count 0 2006.257.10:55:46.20#ibcon#about to write, iclass 13, count 0 2006.257.10:55:46.20#ibcon#wrote, iclass 13, count 0 2006.257.10:55:46.20#ibcon#about to read 3, iclass 13, count 0 2006.257.10:55:46.22#ibcon#read 3, iclass 13, count 0 2006.257.10:55:46.22#ibcon#about to read 4, iclass 13, count 0 2006.257.10:55:46.22#ibcon#read 4, iclass 13, count 0 2006.257.10:55:46.22#ibcon#about to read 5, iclass 13, count 0 2006.257.10:55:46.22#ibcon#read 5, iclass 13, count 0 2006.257.10:55:46.22#ibcon#about to read 6, iclass 13, count 0 2006.257.10:55:46.22#ibcon#read 6, iclass 13, count 0 2006.257.10:55:46.22#ibcon#end of sib2, iclass 13, count 0 2006.257.10:55:46.22#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:55:46.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:55:46.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.10:55:46.22#ibcon#*before write, iclass 13, count 0 2006.257.10:55:46.22#ibcon#enter sib2, iclass 13, count 0 2006.257.10:55:46.22#ibcon#flushed, iclass 13, count 0 2006.257.10:55:46.22#ibcon#about to write, iclass 13, count 0 2006.257.10:55:46.22#ibcon#wrote, iclass 13, count 0 2006.257.10:55:46.22#ibcon#about to read 3, iclass 13, count 0 2006.257.10:55:46.26#ibcon#read 3, iclass 13, count 0 2006.257.10:55:46.26#ibcon#about to read 4, iclass 13, count 0 2006.257.10:55:46.26#ibcon#read 4, iclass 13, count 0 2006.257.10:55:46.26#ibcon#about to read 5, iclass 13, count 0 2006.257.10:55:46.26#ibcon#read 5, iclass 13, count 0 2006.257.10:55:46.26#ibcon#about to read 6, iclass 13, count 0 2006.257.10:55:46.26#ibcon#read 6, iclass 13, count 0 2006.257.10:55:46.26#ibcon#end of sib2, iclass 13, count 0 2006.257.10:55:46.26#ibcon#*after write, iclass 13, count 0 2006.257.10:55:46.26#ibcon#*before return 0, iclass 13, count 0 2006.257.10:55:46.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:46.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:46.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:55:46.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:55:46.26$vck44/va=4,7 2006.257.10:55:46.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.10:55:46.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.10:55:46.26#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:46.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:46.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:46.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:46.32#ibcon#enter wrdev, iclass 15, count 2 2006.257.10:55:46.32#ibcon#first serial, iclass 15, count 2 2006.257.10:55:46.32#ibcon#enter sib2, iclass 15, count 2 2006.257.10:55:46.32#ibcon#flushed, iclass 15, count 2 2006.257.10:55:46.32#ibcon#about to write, iclass 15, count 2 2006.257.10:55:46.32#ibcon#wrote, iclass 15, count 2 2006.257.10:55:46.32#ibcon#about to read 3, iclass 15, count 2 2006.257.10:55:46.34#ibcon#read 3, iclass 15, count 2 2006.257.10:55:46.34#ibcon#about to read 4, iclass 15, count 2 2006.257.10:55:46.34#ibcon#read 4, iclass 15, count 2 2006.257.10:55:46.34#ibcon#about to read 5, iclass 15, count 2 2006.257.10:55:46.34#ibcon#read 5, iclass 15, count 2 2006.257.10:55:46.34#ibcon#about to read 6, iclass 15, count 2 2006.257.10:55:46.34#ibcon#read 6, iclass 15, count 2 2006.257.10:55:46.34#ibcon#end of sib2, iclass 15, count 2 2006.257.10:55:46.34#ibcon#*mode == 0, iclass 15, count 2 2006.257.10:55:46.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.10:55:46.34#ibcon#[25=AT04-07\r\n] 2006.257.10:55:46.34#ibcon#*before write, iclass 15, count 2 2006.257.10:55:46.34#ibcon#enter sib2, iclass 15, count 2 2006.257.10:55:46.34#ibcon#flushed, iclass 15, count 2 2006.257.10:55:46.34#ibcon#about to write, iclass 15, count 2 2006.257.10:55:46.34#ibcon#wrote, iclass 15, count 2 2006.257.10:55:46.34#ibcon#about to read 3, iclass 15, count 2 2006.257.10:55:46.37#ibcon#read 3, iclass 15, count 2 2006.257.10:55:46.37#ibcon#about to read 4, iclass 15, count 2 2006.257.10:55:46.37#ibcon#read 4, iclass 15, count 2 2006.257.10:55:46.37#ibcon#about to read 5, iclass 15, count 2 2006.257.10:55:46.37#ibcon#read 5, iclass 15, count 2 2006.257.10:55:46.37#ibcon#about to read 6, iclass 15, count 2 2006.257.10:55:46.37#ibcon#read 6, iclass 15, count 2 2006.257.10:55:46.37#ibcon#end of sib2, iclass 15, count 2 2006.257.10:55:46.37#ibcon#*after write, iclass 15, count 2 2006.257.10:55:46.37#ibcon#*before return 0, iclass 15, count 2 2006.257.10:55:46.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:46.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:46.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.10:55:46.41#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:46.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:46.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:46.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:46.52#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:55:46.52#ibcon#first serial, iclass 15, count 0 2006.257.10:55:46.52#ibcon#enter sib2, iclass 15, count 0 2006.257.10:55:46.52#ibcon#flushed, iclass 15, count 0 2006.257.10:55:46.52#ibcon#about to write, iclass 15, count 0 2006.257.10:55:46.52#ibcon#wrote, iclass 15, count 0 2006.257.10:55:46.52#ibcon#about to read 3, iclass 15, count 0 2006.257.10:55:46.54#ibcon#read 3, iclass 15, count 0 2006.257.10:55:46.54#ibcon#about to read 4, iclass 15, count 0 2006.257.10:55:46.54#ibcon#read 4, iclass 15, count 0 2006.257.10:55:46.54#ibcon#about to read 5, iclass 15, count 0 2006.257.10:55:46.54#ibcon#read 5, iclass 15, count 0 2006.257.10:55:46.54#ibcon#about to read 6, iclass 15, count 0 2006.257.10:55:46.54#ibcon#read 6, iclass 15, count 0 2006.257.10:55:46.54#ibcon#end of sib2, iclass 15, count 0 2006.257.10:55:46.54#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:55:46.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:55:46.54#ibcon#[25=USB\r\n] 2006.257.10:55:46.54#ibcon#*before write, iclass 15, count 0 2006.257.10:55:46.54#ibcon#enter sib2, iclass 15, count 0 2006.257.10:55:46.54#ibcon#flushed, iclass 15, count 0 2006.257.10:55:46.54#ibcon#about to write, iclass 15, count 0 2006.257.10:55:46.54#ibcon#wrote, iclass 15, count 0 2006.257.10:55:46.54#ibcon#about to read 3, iclass 15, count 0 2006.257.10:55:46.57#ibcon#read 3, iclass 15, count 0 2006.257.10:55:46.57#ibcon#about to read 4, iclass 15, count 0 2006.257.10:55:46.57#ibcon#read 4, iclass 15, count 0 2006.257.10:55:46.57#ibcon#about to read 5, iclass 15, count 0 2006.257.10:55:46.57#ibcon#read 5, iclass 15, count 0 2006.257.10:55:46.57#ibcon#about to read 6, iclass 15, count 0 2006.257.10:55:46.57#ibcon#read 6, iclass 15, count 0 2006.257.10:55:46.57#ibcon#end of sib2, iclass 15, count 0 2006.257.10:55:46.57#ibcon#*after write, iclass 15, count 0 2006.257.10:55:46.57#ibcon#*before return 0, iclass 15, count 0 2006.257.10:55:46.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:46.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:46.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:55:46.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:55:46.57$vck44/valo=5,734.99 2006.257.10:55:46.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.10:55:46.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.10:55:46.57#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:46.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:46.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:46.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:46.57#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:55:46.57#ibcon#first serial, iclass 17, count 0 2006.257.10:55:46.57#ibcon#enter sib2, iclass 17, count 0 2006.257.10:55:46.57#ibcon#flushed, iclass 17, count 0 2006.257.10:55:46.57#ibcon#about to write, iclass 17, count 0 2006.257.10:55:46.57#ibcon#wrote, iclass 17, count 0 2006.257.10:55:46.57#ibcon#about to read 3, iclass 17, count 0 2006.257.10:55:46.59#ibcon#read 3, iclass 17, count 0 2006.257.10:55:46.59#ibcon#about to read 4, iclass 17, count 0 2006.257.10:55:46.59#ibcon#read 4, iclass 17, count 0 2006.257.10:55:46.59#ibcon#about to read 5, iclass 17, count 0 2006.257.10:55:46.59#ibcon#read 5, iclass 17, count 0 2006.257.10:55:46.59#ibcon#about to read 6, iclass 17, count 0 2006.257.10:55:46.59#ibcon#read 6, iclass 17, count 0 2006.257.10:55:46.59#ibcon#end of sib2, iclass 17, count 0 2006.257.10:55:46.59#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:55:46.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:55:46.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.10:55:46.59#ibcon#*before write, iclass 17, count 0 2006.257.10:55:46.59#ibcon#enter sib2, iclass 17, count 0 2006.257.10:55:46.59#ibcon#flushed, iclass 17, count 0 2006.257.10:55:46.59#ibcon#about to write, iclass 17, count 0 2006.257.10:55:46.59#ibcon#wrote, iclass 17, count 0 2006.257.10:55:46.59#ibcon#about to read 3, iclass 17, count 0 2006.257.10:55:46.63#ibcon#read 3, iclass 17, count 0 2006.257.10:55:46.63#ibcon#about to read 4, iclass 17, count 0 2006.257.10:55:46.63#ibcon#read 4, iclass 17, count 0 2006.257.10:55:46.63#ibcon#about to read 5, iclass 17, count 0 2006.257.10:55:46.63#ibcon#read 5, iclass 17, count 0 2006.257.10:55:46.63#ibcon#about to read 6, iclass 17, count 0 2006.257.10:55:46.63#ibcon#read 6, iclass 17, count 0 2006.257.10:55:46.63#ibcon#end of sib2, iclass 17, count 0 2006.257.10:55:46.63#ibcon#*after write, iclass 17, count 0 2006.257.10:55:46.63#ibcon#*before return 0, iclass 17, count 0 2006.257.10:55:46.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:46.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:46.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:55:46.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:55:46.63$vck44/va=5,4 2006.257.10:55:46.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.10:55:46.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.10:55:46.63#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:46.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:46.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:46.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:46.69#ibcon#enter wrdev, iclass 19, count 2 2006.257.10:55:46.69#ibcon#first serial, iclass 19, count 2 2006.257.10:55:46.69#ibcon#enter sib2, iclass 19, count 2 2006.257.10:55:46.69#ibcon#flushed, iclass 19, count 2 2006.257.10:55:46.69#ibcon#about to write, iclass 19, count 2 2006.257.10:55:46.69#ibcon#wrote, iclass 19, count 2 2006.257.10:55:46.69#ibcon#about to read 3, iclass 19, count 2 2006.257.10:55:46.71#ibcon#read 3, iclass 19, count 2 2006.257.10:55:46.71#ibcon#about to read 4, iclass 19, count 2 2006.257.10:55:46.71#ibcon#read 4, iclass 19, count 2 2006.257.10:55:46.71#ibcon#about to read 5, iclass 19, count 2 2006.257.10:55:46.71#ibcon#read 5, iclass 19, count 2 2006.257.10:55:46.71#ibcon#about to read 6, iclass 19, count 2 2006.257.10:55:46.71#ibcon#read 6, iclass 19, count 2 2006.257.10:55:46.71#ibcon#end of sib2, iclass 19, count 2 2006.257.10:55:46.71#ibcon#*mode == 0, iclass 19, count 2 2006.257.10:55:46.71#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.10:55:46.71#ibcon#[25=AT05-04\r\n] 2006.257.10:55:46.71#ibcon#*before write, iclass 19, count 2 2006.257.10:55:46.71#ibcon#enter sib2, iclass 19, count 2 2006.257.10:55:46.71#ibcon#flushed, iclass 19, count 2 2006.257.10:55:46.71#ibcon#about to write, iclass 19, count 2 2006.257.10:55:46.71#ibcon#wrote, iclass 19, count 2 2006.257.10:55:46.71#ibcon#about to read 3, iclass 19, count 2 2006.257.10:55:46.74#ibcon#read 3, iclass 19, count 2 2006.257.10:55:46.74#ibcon#about to read 4, iclass 19, count 2 2006.257.10:55:46.74#ibcon#read 4, iclass 19, count 2 2006.257.10:55:46.74#ibcon#about to read 5, iclass 19, count 2 2006.257.10:55:46.74#ibcon#read 5, iclass 19, count 2 2006.257.10:55:46.74#ibcon#about to read 6, iclass 19, count 2 2006.257.10:55:46.74#ibcon#read 6, iclass 19, count 2 2006.257.10:55:46.74#ibcon#end of sib2, iclass 19, count 2 2006.257.10:55:46.74#ibcon#*after write, iclass 19, count 2 2006.257.10:55:46.74#ibcon#*before return 0, iclass 19, count 2 2006.257.10:55:46.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:46.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:46.74#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.10:55:46.74#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:46.74#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:46.86#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:46.86#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:46.86#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:55:46.86#ibcon#first serial, iclass 19, count 0 2006.257.10:55:46.86#ibcon#enter sib2, iclass 19, count 0 2006.257.10:55:46.86#ibcon#flushed, iclass 19, count 0 2006.257.10:55:46.86#ibcon#about to write, iclass 19, count 0 2006.257.10:55:46.86#ibcon#wrote, iclass 19, count 0 2006.257.10:55:46.86#ibcon#about to read 3, iclass 19, count 0 2006.257.10:55:46.88#ibcon#read 3, iclass 19, count 0 2006.257.10:55:46.88#ibcon#about to read 4, iclass 19, count 0 2006.257.10:55:46.88#ibcon#read 4, iclass 19, count 0 2006.257.10:55:46.88#ibcon#about to read 5, iclass 19, count 0 2006.257.10:55:46.88#ibcon#read 5, iclass 19, count 0 2006.257.10:55:46.88#ibcon#about to read 6, iclass 19, count 0 2006.257.10:55:46.88#ibcon#read 6, iclass 19, count 0 2006.257.10:55:46.88#ibcon#end of sib2, iclass 19, count 0 2006.257.10:55:46.88#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:55:46.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:55:46.88#ibcon#[25=USB\r\n] 2006.257.10:55:46.88#ibcon#*before write, iclass 19, count 0 2006.257.10:55:46.88#ibcon#enter sib2, iclass 19, count 0 2006.257.10:55:46.88#ibcon#flushed, iclass 19, count 0 2006.257.10:55:46.88#ibcon#about to write, iclass 19, count 0 2006.257.10:55:46.88#ibcon#wrote, iclass 19, count 0 2006.257.10:55:46.88#ibcon#about to read 3, iclass 19, count 0 2006.257.10:55:46.91#ibcon#read 3, iclass 19, count 0 2006.257.10:55:46.91#ibcon#about to read 4, iclass 19, count 0 2006.257.10:55:46.91#ibcon#read 4, iclass 19, count 0 2006.257.10:55:46.91#ibcon#about to read 5, iclass 19, count 0 2006.257.10:55:46.91#ibcon#read 5, iclass 19, count 0 2006.257.10:55:46.91#ibcon#about to read 6, iclass 19, count 0 2006.257.10:55:46.91#ibcon#read 6, iclass 19, count 0 2006.257.10:55:46.91#ibcon#end of sib2, iclass 19, count 0 2006.257.10:55:46.91#ibcon#*after write, iclass 19, count 0 2006.257.10:55:46.91#ibcon#*before return 0, iclass 19, count 0 2006.257.10:55:46.91#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:46.91#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:46.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:55:46.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:55:46.91$vck44/valo=6,814.99 2006.257.10:55:46.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.10:55:46.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.10:55:46.91#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:46.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:46.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:46.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:46.91#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:55:46.91#ibcon#first serial, iclass 21, count 0 2006.257.10:55:46.91#ibcon#enter sib2, iclass 21, count 0 2006.257.10:55:46.91#ibcon#flushed, iclass 21, count 0 2006.257.10:55:46.91#ibcon#about to write, iclass 21, count 0 2006.257.10:55:46.91#ibcon#wrote, iclass 21, count 0 2006.257.10:55:46.91#ibcon#about to read 3, iclass 21, count 0 2006.257.10:55:46.93#ibcon#read 3, iclass 21, count 0 2006.257.10:55:46.93#ibcon#about to read 4, iclass 21, count 0 2006.257.10:55:46.93#ibcon#read 4, iclass 21, count 0 2006.257.10:55:46.93#ibcon#about to read 5, iclass 21, count 0 2006.257.10:55:46.93#ibcon#read 5, iclass 21, count 0 2006.257.10:55:46.93#ibcon#about to read 6, iclass 21, count 0 2006.257.10:55:46.93#ibcon#read 6, iclass 21, count 0 2006.257.10:55:46.93#ibcon#end of sib2, iclass 21, count 0 2006.257.10:55:46.93#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:55:46.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:55:46.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.10:55:46.93#ibcon#*before write, iclass 21, count 0 2006.257.10:55:46.93#ibcon#enter sib2, iclass 21, count 0 2006.257.10:55:46.93#ibcon#flushed, iclass 21, count 0 2006.257.10:55:46.93#ibcon#about to write, iclass 21, count 0 2006.257.10:55:46.93#ibcon#wrote, iclass 21, count 0 2006.257.10:55:46.93#ibcon#about to read 3, iclass 21, count 0 2006.257.10:55:46.97#ibcon#read 3, iclass 21, count 0 2006.257.10:55:46.97#ibcon#about to read 4, iclass 21, count 0 2006.257.10:55:46.97#ibcon#read 4, iclass 21, count 0 2006.257.10:55:46.97#ibcon#about to read 5, iclass 21, count 0 2006.257.10:55:46.97#ibcon#read 5, iclass 21, count 0 2006.257.10:55:46.97#ibcon#about to read 6, iclass 21, count 0 2006.257.10:55:46.97#ibcon#read 6, iclass 21, count 0 2006.257.10:55:46.97#ibcon#end of sib2, iclass 21, count 0 2006.257.10:55:46.97#ibcon#*after write, iclass 21, count 0 2006.257.10:55:46.97#ibcon#*before return 0, iclass 21, count 0 2006.257.10:55:46.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:46.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:46.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:55:46.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:55:46.97$vck44/va=6,4 2006.257.10:55:46.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.10:55:46.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.10:55:46.97#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:46.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:47.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:47.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:47.03#ibcon#enter wrdev, iclass 23, count 2 2006.257.10:55:47.03#ibcon#first serial, iclass 23, count 2 2006.257.10:55:47.03#ibcon#enter sib2, iclass 23, count 2 2006.257.10:55:47.03#ibcon#flushed, iclass 23, count 2 2006.257.10:55:47.03#ibcon#about to write, iclass 23, count 2 2006.257.10:55:47.03#ibcon#wrote, iclass 23, count 2 2006.257.10:55:47.03#ibcon#about to read 3, iclass 23, count 2 2006.257.10:55:47.05#ibcon#read 3, iclass 23, count 2 2006.257.10:55:47.05#ibcon#about to read 4, iclass 23, count 2 2006.257.10:55:47.05#ibcon#read 4, iclass 23, count 2 2006.257.10:55:47.05#ibcon#about to read 5, iclass 23, count 2 2006.257.10:55:47.05#ibcon#read 5, iclass 23, count 2 2006.257.10:55:47.05#ibcon#about to read 6, iclass 23, count 2 2006.257.10:55:47.05#ibcon#read 6, iclass 23, count 2 2006.257.10:55:47.05#ibcon#end of sib2, iclass 23, count 2 2006.257.10:55:47.05#ibcon#*mode == 0, iclass 23, count 2 2006.257.10:55:47.05#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.10:55:47.05#ibcon#[25=AT06-04\r\n] 2006.257.10:55:47.05#ibcon#*before write, iclass 23, count 2 2006.257.10:55:47.05#ibcon#enter sib2, iclass 23, count 2 2006.257.10:55:47.05#ibcon#flushed, iclass 23, count 2 2006.257.10:55:47.05#ibcon#about to write, iclass 23, count 2 2006.257.10:55:47.05#ibcon#wrote, iclass 23, count 2 2006.257.10:55:47.05#ibcon#about to read 3, iclass 23, count 2 2006.257.10:55:47.08#ibcon#read 3, iclass 23, count 2 2006.257.10:55:47.08#ibcon#about to read 4, iclass 23, count 2 2006.257.10:55:47.08#ibcon#read 4, iclass 23, count 2 2006.257.10:55:47.08#ibcon#about to read 5, iclass 23, count 2 2006.257.10:55:47.08#ibcon#read 5, iclass 23, count 2 2006.257.10:55:47.08#ibcon#about to read 6, iclass 23, count 2 2006.257.10:55:47.08#ibcon#read 6, iclass 23, count 2 2006.257.10:55:47.08#ibcon#end of sib2, iclass 23, count 2 2006.257.10:55:47.08#ibcon#*after write, iclass 23, count 2 2006.257.10:55:47.08#ibcon#*before return 0, iclass 23, count 2 2006.257.10:55:47.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:47.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:47.08#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.10:55:47.08#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:47.08#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:47.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:47.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:47.20#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:55:47.20#ibcon#first serial, iclass 23, count 0 2006.257.10:55:47.20#ibcon#enter sib2, iclass 23, count 0 2006.257.10:55:47.20#ibcon#flushed, iclass 23, count 0 2006.257.10:55:47.20#ibcon#about to write, iclass 23, count 0 2006.257.10:55:47.20#ibcon#wrote, iclass 23, count 0 2006.257.10:55:47.20#ibcon#about to read 3, iclass 23, count 0 2006.257.10:55:47.22#ibcon#read 3, iclass 23, count 0 2006.257.10:55:47.22#ibcon#about to read 4, iclass 23, count 0 2006.257.10:55:47.22#ibcon#read 4, iclass 23, count 0 2006.257.10:55:47.22#ibcon#about to read 5, iclass 23, count 0 2006.257.10:55:47.22#ibcon#read 5, iclass 23, count 0 2006.257.10:55:47.22#ibcon#about to read 6, iclass 23, count 0 2006.257.10:55:47.22#ibcon#read 6, iclass 23, count 0 2006.257.10:55:47.22#ibcon#end of sib2, iclass 23, count 0 2006.257.10:55:47.22#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:55:47.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:55:47.22#ibcon#[25=USB\r\n] 2006.257.10:55:47.22#ibcon#*before write, iclass 23, count 0 2006.257.10:55:47.22#ibcon#enter sib2, iclass 23, count 0 2006.257.10:55:47.22#ibcon#flushed, iclass 23, count 0 2006.257.10:55:47.22#ibcon#about to write, iclass 23, count 0 2006.257.10:55:47.22#ibcon#wrote, iclass 23, count 0 2006.257.10:55:47.22#ibcon#about to read 3, iclass 23, count 0 2006.257.10:55:47.25#ibcon#read 3, iclass 23, count 0 2006.257.10:55:47.25#ibcon#about to read 4, iclass 23, count 0 2006.257.10:55:47.25#ibcon#read 4, iclass 23, count 0 2006.257.10:55:47.25#ibcon#about to read 5, iclass 23, count 0 2006.257.10:55:47.25#ibcon#read 5, iclass 23, count 0 2006.257.10:55:47.25#ibcon#about to read 6, iclass 23, count 0 2006.257.10:55:47.25#ibcon#read 6, iclass 23, count 0 2006.257.10:55:47.25#ibcon#end of sib2, iclass 23, count 0 2006.257.10:55:47.25#ibcon#*after write, iclass 23, count 0 2006.257.10:55:47.25#ibcon#*before return 0, iclass 23, count 0 2006.257.10:55:47.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:47.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:47.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:55:47.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:55:47.25$vck44/valo=7,864.99 2006.257.10:55:47.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.10:55:47.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.10:55:47.25#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:47.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:47.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:47.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:47.25#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:55:47.25#ibcon#first serial, iclass 25, count 0 2006.257.10:55:47.25#ibcon#enter sib2, iclass 25, count 0 2006.257.10:55:47.25#ibcon#flushed, iclass 25, count 0 2006.257.10:55:47.25#ibcon#about to write, iclass 25, count 0 2006.257.10:55:47.25#ibcon#wrote, iclass 25, count 0 2006.257.10:55:47.25#ibcon#about to read 3, iclass 25, count 0 2006.257.10:55:47.27#ibcon#read 3, iclass 25, count 0 2006.257.10:55:47.27#ibcon#about to read 4, iclass 25, count 0 2006.257.10:55:47.27#ibcon#read 4, iclass 25, count 0 2006.257.10:55:47.27#ibcon#about to read 5, iclass 25, count 0 2006.257.10:55:47.27#ibcon#read 5, iclass 25, count 0 2006.257.10:55:47.27#ibcon#about to read 6, iclass 25, count 0 2006.257.10:55:47.27#ibcon#read 6, iclass 25, count 0 2006.257.10:55:47.27#ibcon#end of sib2, iclass 25, count 0 2006.257.10:55:47.27#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:55:47.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:55:47.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.10:55:47.27#ibcon#*before write, iclass 25, count 0 2006.257.10:55:47.27#ibcon#enter sib2, iclass 25, count 0 2006.257.10:55:47.27#ibcon#flushed, iclass 25, count 0 2006.257.10:55:47.27#ibcon#about to write, iclass 25, count 0 2006.257.10:55:47.27#ibcon#wrote, iclass 25, count 0 2006.257.10:55:47.27#ibcon#about to read 3, iclass 25, count 0 2006.257.10:55:47.31#ibcon#read 3, iclass 25, count 0 2006.257.10:55:47.31#ibcon#about to read 4, iclass 25, count 0 2006.257.10:55:47.31#ibcon#read 4, iclass 25, count 0 2006.257.10:55:47.31#ibcon#about to read 5, iclass 25, count 0 2006.257.10:55:47.31#ibcon#read 5, iclass 25, count 0 2006.257.10:55:47.31#ibcon#about to read 6, iclass 25, count 0 2006.257.10:55:47.31#ibcon#read 6, iclass 25, count 0 2006.257.10:55:47.31#ibcon#end of sib2, iclass 25, count 0 2006.257.10:55:47.31#ibcon#*after write, iclass 25, count 0 2006.257.10:55:47.31#ibcon#*before return 0, iclass 25, count 0 2006.257.10:55:47.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:47.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:47.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:55:47.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:55:47.31$vck44/va=7,4 2006.257.10:55:47.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.10:55:47.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.10:55:47.31#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:47.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:47.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:47.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:47.37#ibcon#enter wrdev, iclass 27, count 2 2006.257.10:55:47.37#ibcon#first serial, iclass 27, count 2 2006.257.10:55:47.37#ibcon#enter sib2, iclass 27, count 2 2006.257.10:55:47.37#ibcon#flushed, iclass 27, count 2 2006.257.10:55:47.37#ibcon#about to write, iclass 27, count 2 2006.257.10:55:47.37#ibcon#wrote, iclass 27, count 2 2006.257.10:55:47.37#ibcon#about to read 3, iclass 27, count 2 2006.257.10:55:47.39#ibcon#read 3, iclass 27, count 2 2006.257.10:55:47.39#ibcon#about to read 4, iclass 27, count 2 2006.257.10:55:47.39#ibcon#read 4, iclass 27, count 2 2006.257.10:55:47.39#ibcon#about to read 5, iclass 27, count 2 2006.257.10:55:47.39#ibcon#read 5, iclass 27, count 2 2006.257.10:55:47.39#ibcon#about to read 6, iclass 27, count 2 2006.257.10:55:47.39#ibcon#read 6, iclass 27, count 2 2006.257.10:55:47.39#ibcon#end of sib2, iclass 27, count 2 2006.257.10:55:47.39#ibcon#*mode == 0, iclass 27, count 2 2006.257.10:55:47.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.10:55:47.39#ibcon#[25=AT07-04\r\n] 2006.257.10:55:47.39#ibcon#*before write, iclass 27, count 2 2006.257.10:55:47.39#ibcon#enter sib2, iclass 27, count 2 2006.257.10:55:47.39#ibcon#flushed, iclass 27, count 2 2006.257.10:55:47.39#ibcon#about to write, iclass 27, count 2 2006.257.10:55:47.39#ibcon#wrote, iclass 27, count 2 2006.257.10:55:47.39#ibcon#about to read 3, iclass 27, count 2 2006.257.10:55:47.42#ibcon#read 3, iclass 27, count 2 2006.257.10:55:47.42#ibcon#about to read 4, iclass 27, count 2 2006.257.10:55:47.42#ibcon#read 4, iclass 27, count 2 2006.257.10:55:47.42#ibcon#about to read 5, iclass 27, count 2 2006.257.10:55:47.42#ibcon#read 5, iclass 27, count 2 2006.257.10:55:47.42#ibcon#about to read 6, iclass 27, count 2 2006.257.10:55:47.42#ibcon#read 6, iclass 27, count 2 2006.257.10:55:47.42#ibcon#end of sib2, iclass 27, count 2 2006.257.10:55:47.42#ibcon#*after write, iclass 27, count 2 2006.257.10:55:47.42#ibcon#*before return 0, iclass 27, count 2 2006.257.10:55:47.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:47.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:47.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.10:55:47.42#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:47.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:47.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:47.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:47.54#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:55:47.54#ibcon#first serial, iclass 27, count 0 2006.257.10:55:47.54#ibcon#enter sib2, iclass 27, count 0 2006.257.10:55:47.54#ibcon#flushed, iclass 27, count 0 2006.257.10:55:47.54#ibcon#about to write, iclass 27, count 0 2006.257.10:55:47.54#ibcon#wrote, iclass 27, count 0 2006.257.10:55:47.54#ibcon#about to read 3, iclass 27, count 0 2006.257.10:55:47.56#ibcon#read 3, iclass 27, count 0 2006.257.10:55:47.56#ibcon#about to read 4, iclass 27, count 0 2006.257.10:55:47.56#ibcon#read 4, iclass 27, count 0 2006.257.10:55:47.56#ibcon#about to read 5, iclass 27, count 0 2006.257.10:55:47.56#ibcon#read 5, iclass 27, count 0 2006.257.10:55:47.56#ibcon#about to read 6, iclass 27, count 0 2006.257.10:55:47.56#ibcon#read 6, iclass 27, count 0 2006.257.10:55:47.56#ibcon#end of sib2, iclass 27, count 0 2006.257.10:55:47.56#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:55:47.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:55:47.56#ibcon#[25=USB\r\n] 2006.257.10:55:47.56#ibcon#*before write, iclass 27, count 0 2006.257.10:55:47.56#ibcon#enter sib2, iclass 27, count 0 2006.257.10:55:47.56#ibcon#flushed, iclass 27, count 0 2006.257.10:55:47.56#ibcon#about to write, iclass 27, count 0 2006.257.10:55:47.56#ibcon#wrote, iclass 27, count 0 2006.257.10:55:47.56#ibcon#about to read 3, iclass 27, count 0 2006.257.10:55:47.59#ibcon#read 3, iclass 27, count 0 2006.257.10:55:47.59#ibcon#about to read 4, iclass 27, count 0 2006.257.10:55:47.59#ibcon#read 4, iclass 27, count 0 2006.257.10:55:47.59#ibcon#about to read 5, iclass 27, count 0 2006.257.10:55:47.59#ibcon#read 5, iclass 27, count 0 2006.257.10:55:47.59#ibcon#about to read 6, iclass 27, count 0 2006.257.10:55:47.59#ibcon#read 6, iclass 27, count 0 2006.257.10:55:47.59#ibcon#end of sib2, iclass 27, count 0 2006.257.10:55:47.59#ibcon#*after write, iclass 27, count 0 2006.257.10:55:47.59#ibcon#*before return 0, iclass 27, count 0 2006.257.10:55:47.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:47.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:47.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:55:47.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:55:47.59$vck44/valo=8,884.99 2006.257.10:55:47.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.10:55:47.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.10:55:47.59#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:47.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:47.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:47.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:47.59#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:55:47.59#ibcon#first serial, iclass 29, count 0 2006.257.10:55:47.59#ibcon#enter sib2, iclass 29, count 0 2006.257.10:55:47.59#ibcon#flushed, iclass 29, count 0 2006.257.10:55:47.59#ibcon#about to write, iclass 29, count 0 2006.257.10:55:47.59#ibcon#wrote, iclass 29, count 0 2006.257.10:55:47.59#ibcon#about to read 3, iclass 29, count 0 2006.257.10:55:47.61#ibcon#read 3, iclass 29, count 0 2006.257.10:55:47.61#ibcon#about to read 4, iclass 29, count 0 2006.257.10:55:47.61#ibcon#read 4, iclass 29, count 0 2006.257.10:55:47.61#ibcon#about to read 5, iclass 29, count 0 2006.257.10:55:47.61#ibcon#read 5, iclass 29, count 0 2006.257.10:55:47.61#ibcon#about to read 6, iclass 29, count 0 2006.257.10:55:47.61#ibcon#read 6, iclass 29, count 0 2006.257.10:55:47.61#ibcon#end of sib2, iclass 29, count 0 2006.257.10:55:47.61#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:55:47.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:55:47.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.10:55:47.61#ibcon#*before write, iclass 29, count 0 2006.257.10:55:47.61#ibcon#enter sib2, iclass 29, count 0 2006.257.10:55:47.61#ibcon#flushed, iclass 29, count 0 2006.257.10:55:47.61#ibcon#about to write, iclass 29, count 0 2006.257.10:55:47.61#ibcon#wrote, iclass 29, count 0 2006.257.10:55:47.61#ibcon#about to read 3, iclass 29, count 0 2006.257.10:55:47.65#ibcon#read 3, iclass 29, count 0 2006.257.10:55:47.65#ibcon#about to read 4, iclass 29, count 0 2006.257.10:55:47.65#ibcon#read 4, iclass 29, count 0 2006.257.10:55:47.65#ibcon#about to read 5, iclass 29, count 0 2006.257.10:55:47.65#ibcon#read 5, iclass 29, count 0 2006.257.10:55:47.65#ibcon#about to read 6, iclass 29, count 0 2006.257.10:55:47.65#ibcon#read 6, iclass 29, count 0 2006.257.10:55:47.65#ibcon#end of sib2, iclass 29, count 0 2006.257.10:55:47.65#ibcon#*after write, iclass 29, count 0 2006.257.10:55:47.65#ibcon#*before return 0, iclass 29, count 0 2006.257.10:55:47.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:47.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:47.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:55:47.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:55:47.65$vck44/va=8,4 2006.257.10:55:47.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.10:55:47.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.10:55:47.65#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:47.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:55:47.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:55:47.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:55:47.71#ibcon#enter wrdev, iclass 31, count 2 2006.257.10:55:47.71#ibcon#first serial, iclass 31, count 2 2006.257.10:55:47.71#ibcon#enter sib2, iclass 31, count 2 2006.257.10:55:47.71#ibcon#flushed, iclass 31, count 2 2006.257.10:55:47.71#ibcon#about to write, iclass 31, count 2 2006.257.10:55:47.71#ibcon#wrote, iclass 31, count 2 2006.257.10:55:47.71#ibcon#about to read 3, iclass 31, count 2 2006.257.10:55:47.73#ibcon#read 3, iclass 31, count 2 2006.257.10:55:47.73#ibcon#about to read 4, iclass 31, count 2 2006.257.10:55:47.73#ibcon#read 4, iclass 31, count 2 2006.257.10:55:47.73#ibcon#about to read 5, iclass 31, count 2 2006.257.10:55:47.73#ibcon#read 5, iclass 31, count 2 2006.257.10:55:47.73#ibcon#about to read 6, iclass 31, count 2 2006.257.10:55:47.73#ibcon#read 6, iclass 31, count 2 2006.257.10:55:47.73#ibcon#end of sib2, iclass 31, count 2 2006.257.10:55:47.73#ibcon#*mode == 0, iclass 31, count 2 2006.257.10:55:47.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.10:55:47.73#ibcon#[25=AT08-04\r\n] 2006.257.10:55:47.73#ibcon#*before write, iclass 31, count 2 2006.257.10:55:47.73#ibcon#enter sib2, iclass 31, count 2 2006.257.10:55:47.73#ibcon#flushed, iclass 31, count 2 2006.257.10:55:47.73#ibcon#about to write, iclass 31, count 2 2006.257.10:55:47.73#ibcon#wrote, iclass 31, count 2 2006.257.10:55:47.73#ibcon#about to read 3, iclass 31, count 2 2006.257.10:55:47.76#ibcon#read 3, iclass 31, count 2 2006.257.10:55:47.76#ibcon#about to read 4, iclass 31, count 2 2006.257.10:55:47.76#ibcon#read 4, iclass 31, count 2 2006.257.10:55:47.76#ibcon#about to read 5, iclass 31, count 2 2006.257.10:55:47.76#ibcon#read 5, iclass 31, count 2 2006.257.10:55:47.76#ibcon#about to read 6, iclass 31, count 2 2006.257.10:55:47.76#ibcon#read 6, iclass 31, count 2 2006.257.10:55:47.76#ibcon#end of sib2, iclass 31, count 2 2006.257.10:55:47.76#ibcon#*after write, iclass 31, count 2 2006.257.10:55:47.76#ibcon#*before return 0, iclass 31, count 2 2006.257.10:55:47.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:55:47.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.10:55:47.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.10:55:47.76#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:47.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:55:47.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:55:47.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:55:47.88#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:55:47.88#ibcon#first serial, iclass 31, count 0 2006.257.10:55:47.88#ibcon#enter sib2, iclass 31, count 0 2006.257.10:55:47.88#ibcon#flushed, iclass 31, count 0 2006.257.10:55:47.88#ibcon#about to write, iclass 31, count 0 2006.257.10:55:47.88#ibcon#wrote, iclass 31, count 0 2006.257.10:55:47.88#ibcon#about to read 3, iclass 31, count 0 2006.257.10:55:47.90#ibcon#read 3, iclass 31, count 0 2006.257.10:55:47.90#ibcon#about to read 4, iclass 31, count 0 2006.257.10:55:47.90#ibcon#read 4, iclass 31, count 0 2006.257.10:55:47.90#ibcon#about to read 5, iclass 31, count 0 2006.257.10:55:47.90#ibcon#read 5, iclass 31, count 0 2006.257.10:55:47.90#ibcon#about to read 6, iclass 31, count 0 2006.257.10:55:47.90#ibcon#read 6, iclass 31, count 0 2006.257.10:55:47.90#ibcon#end of sib2, iclass 31, count 0 2006.257.10:55:47.90#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:55:47.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:55:47.90#ibcon#[25=USB\r\n] 2006.257.10:55:47.90#ibcon#*before write, iclass 31, count 0 2006.257.10:55:47.90#ibcon#enter sib2, iclass 31, count 0 2006.257.10:55:47.90#ibcon#flushed, iclass 31, count 0 2006.257.10:55:47.90#ibcon#about to write, iclass 31, count 0 2006.257.10:55:47.90#ibcon#wrote, iclass 31, count 0 2006.257.10:55:47.90#ibcon#about to read 3, iclass 31, count 0 2006.257.10:55:47.93#ibcon#read 3, iclass 31, count 0 2006.257.10:55:47.93#ibcon#about to read 4, iclass 31, count 0 2006.257.10:55:47.93#ibcon#read 4, iclass 31, count 0 2006.257.10:55:47.93#ibcon#about to read 5, iclass 31, count 0 2006.257.10:55:47.93#ibcon#read 5, iclass 31, count 0 2006.257.10:55:47.93#ibcon#about to read 6, iclass 31, count 0 2006.257.10:55:47.93#ibcon#read 6, iclass 31, count 0 2006.257.10:55:47.93#ibcon#end of sib2, iclass 31, count 0 2006.257.10:55:47.93#ibcon#*after write, iclass 31, count 0 2006.257.10:55:47.93#ibcon#*before return 0, iclass 31, count 0 2006.257.10:55:47.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:55:47.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.10:55:47.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:55:47.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:55:47.93$vck44/vblo=1,629.99 2006.257.10:55:47.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.10:55:47.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.10:55:47.93#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:47.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:55:47.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:55:47.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:55:47.93#ibcon#enter wrdev, iclass 33, count 0 2006.257.10:55:47.93#ibcon#first serial, iclass 33, count 0 2006.257.10:55:47.93#ibcon#enter sib2, iclass 33, count 0 2006.257.10:55:47.93#ibcon#flushed, iclass 33, count 0 2006.257.10:55:47.93#ibcon#about to write, iclass 33, count 0 2006.257.10:55:47.93#ibcon#wrote, iclass 33, count 0 2006.257.10:55:47.93#ibcon#about to read 3, iclass 33, count 0 2006.257.10:55:47.95#ibcon#read 3, iclass 33, count 0 2006.257.10:55:47.95#ibcon#about to read 4, iclass 33, count 0 2006.257.10:55:47.95#ibcon#read 4, iclass 33, count 0 2006.257.10:55:47.95#ibcon#about to read 5, iclass 33, count 0 2006.257.10:55:47.95#ibcon#read 5, iclass 33, count 0 2006.257.10:55:47.95#ibcon#about to read 6, iclass 33, count 0 2006.257.10:55:47.95#ibcon#read 6, iclass 33, count 0 2006.257.10:55:47.95#ibcon#end of sib2, iclass 33, count 0 2006.257.10:55:47.95#ibcon#*mode == 0, iclass 33, count 0 2006.257.10:55:47.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.10:55:47.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.10:55:47.95#ibcon#*before write, iclass 33, count 0 2006.257.10:55:47.95#ibcon#enter sib2, iclass 33, count 0 2006.257.10:55:47.95#ibcon#flushed, iclass 33, count 0 2006.257.10:55:47.95#ibcon#about to write, iclass 33, count 0 2006.257.10:55:47.95#ibcon#wrote, iclass 33, count 0 2006.257.10:55:47.95#ibcon#about to read 3, iclass 33, count 0 2006.257.10:55:47.99#ibcon#read 3, iclass 33, count 0 2006.257.10:55:47.99#ibcon#about to read 4, iclass 33, count 0 2006.257.10:55:47.99#ibcon#read 4, iclass 33, count 0 2006.257.10:55:47.99#ibcon#about to read 5, iclass 33, count 0 2006.257.10:55:47.99#ibcon#read 5, iclass 33, count 0 2006.257.10:55:47.99#ibcon#about to read 6, iclass 33, count 0 2006.257.10:55:47.99#ibcon#read 6, iclass 33, count 0 2006.257.10:55:47.99#ibcon#end of sib2, iclass 33, count 0 2006.257.10:55:47.99#ibcon#*after write, iclass 33, count 0 2006.257.10:55:47.99#ibcon#*before return 0, iclass 33, count 0 2006.257.10:55:47.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:55:47.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.10:55:47.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.10:55:47.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.10:55:47.99$vck44/vb=1,4 2006.257.10:55:47.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.10:55:47.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.10:55:47.99#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:47.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:55:47.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:55:47.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:55:47.99#ibcon#enter wrdev, iclass 35, count 2 2006.257.10:55:47.99#ibcon#first serial, iclass 35, count 2 2006.257.10:55:47.99#ibcon#enter sib2, iclass 35, count 2 2006.257.10:55:47.99#ibcon#flushed, iclass 35, count 2 2006.257.10:55:47.99#ibcon#about to write, iclass 35, count 2 2006.257.10:55:47.99#ibcon#wrote, iclass 35, count 2 2006.257.10:55:47.99#ibcon#about to read 3, iclass 35, count 2 2006.257.10:55:48.01#ibcon#read 3, iclass 35, count 2 2006.257.10:55:48.01#ibcon#about to read 4, iclass 35, count 2 2006.257.10:55:48.01#ibcon#read 4, iclass 35, count 2 2006.257.10:55:48.01#ibcon#about to read 5, iclass 35, count 2 2006.257.10:55:48.01#ibcon#read 5, iclass 35, count 2 2006.257.10:55:48.01#ibcon#about to read 6, iclass 35, count 2 2006.257.10:55:48.01#ibcon#read 6, iclass 35, count 2 2006.257.10:55:48.01#ibcon#end of sib2, iclass 35, count 2 2006.257.10:55:48.01#ibcon#*mode == 0, iclass 35, count 2 2006.257.10:55:48.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.10:55:48.01#ibcon#[27=AT01-04\r\n] 2006.257.10:55:48.01#ibcon#*before write, iclass 35, count 2 2006.257.10:55:48.01#ibcon#enter sib2, iclass 35, count 2 2006.257.10:55:48.01#ibcon#flushed, iclass 35, count 2 2006.257.10:55:48.01#ibcon#about to write, iclass 35, count 2 2006.257.10:55:48.01#ibcon#wrote, iclass 35, count 2 2006.257.10:55:48.01#ibcon#about to read 3, iclass 35, count 2 2006.257.10:55:48.04#ibcon#read 3, iclass 35, count 2 2006.257.10:55:48.04#ibcon#about to read 4, iclass 35, count 2 2006.257.10:55:48.04#ibcon#read 4, iclass 35, count 2 2006.257.10:55:48.04#ibcon#about to read 5, iclass 35, count 2 2006.257.10:55:48.04#ibcon#read 5, iclass 35, count 2 2006.257.10:55:48.04#ibcon#about to read 6, iclass 35, count 2 2006.257.10:55:48.04#ibcon#read 6, iclass 35, count 2 2006.257.10:55:48.04#ibcon#end of sib2, iclass 35, count 2 2006.257.10:55:48.04#ibcon#*after write, iclass 35, count 2 2006.257.10:55:48.04#ibcon#*before return 0, iclass 35, count 2 2006.257.10:55:48.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:55:48.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.10:55:48.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.10:55:48.04#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:48.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:55:48.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:55:48.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:55:48.16#ibcon#enter wrdev, iclass 35, count 0 2006.257.10:55:48.16#ibcon#first serial, iclass 35, count 0 2006.257.10:55:48.16#ibcon#enter sib2, iclass 35, count 0 2006.257.10:55:48.16#ibcon#flushed, iclass 35, count 0 2006.257.10:55:48.16#ibcon#about to write, iclass 35, count 0 2006.257.10:55:48.16#ibcon#wrote, iclass 35, count 0 2006.257.10:55:48.16#ibcon#about to read 3, iclass 35, count 0 2006.257.10:55:48.18#ibcon#read 3, iclass 35, count 0 2006.257.10:55:48.18#ibcon#about to read 4, iclass 35, count 0 2006.257.10:55:48.18#ibcon#read 4, iclass 35, count 0 2006.257.10:55:48.18#ibcon#about to read 5, iclass 35, count 0 2006.257.10:55:48.18#ibcon#read 5, iclass 35, count 0 2006.257.10:55:48.18#ibcon#about to read 6, iclass 35, count 0 2006.257.10:55:48.18#ibcon#read 6, iclass 35, count 0 2006.257.10:55:48.18#ibcon#end of sib2, iclass 35, count 0 2006.257.10:55:48.18#ibcon#*mode == 0, iclass 35, count 0 2006.257.10:55:48.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.10:55:48.18#ibcon#[27=USB\r\n] 2006.257.10:55:48.18#ibcon#*before write, iclass 35, count 0 2006.257.10:55:48.18#ibcon#enter sib2, iclass 35, count 0 2006.257.10:55:48.18#ibcon#flushed, iclass 35, count 0 2006.257.10:55:48.18#ibcon#about to write, iclass 35, count 0 2006.257.10:55:48.18#ibcon#wrote, iclass 35, count 0 2006.257.10:55:48.18#ibcon#about to read 3, iclass 35, count 0 2006.257.10:55:48.21#ibcon#read 3, iclass 35, count 0 2006.257.10:55:48.21#ibcon#about to read 4, iclass 35, count 0 2006.257.10:55:48.21#ibcon#read 4, iclass 35, count 0 2006.257.10:55:48.21#ibcon#about to read 5, iclass 35, count 0 2006.257.10:55:48.21#ibcon#read 5, iclass 35, count 0 2006.257.10:55:48.21#ibcon#about to read 6, iclass 35, count 0 2006.257.10:55:48.21#ibcon#read 6, iclass 35, count 0 2006.257.10:55:48.21#ibcon#end of sib2, iclass 35, count 0 2006.257.10:55:48.21#ibcon#*after write, iclass 35, count 0 2006.257.10:55:48.21#ibcon#*before return 0, iclass 35, count 0 2006.257.10:55:48.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:55:48.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.10:55:48.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.10:55:48.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.10:55:48.21$vck44/vblo=2,634.99 2006.257.10:55:48.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.10:55:48.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.10:55:48.21#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:48.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:48.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:48.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:48.21#ibcon#enter wrdev, iclass 37, count 0 2006.257.10:55:48.21#ibcon#first serial, iclass 37, count 0 2006.257.10:55:48.21#ibcon#enter sib2, iclass 37, count 0 2006.257.10:55:48.21#ibcon#flushed, iclass 37, count 0 2006.257.10:55:48.21#ibcon#about to write, iclass 37, count 0 2006.257.10:55:48.21#ibcon#wrote, iclass 37, count 0 2006.257.10:55:48.21#ibcon#about to read 3, iclass 37, count 0 2006.257.10:55:48.23#ibcon#read 3, iclass 37, count 0 2006.257.10:55:48.23#ibcon#about to read 4, iclass 37, count 0 2006.257.10:55:48.23#ibcon#read 4, iclass 37, count 0 2006.257.10:55:48.23#ibcon#about to read 5, iclass 37, count 0 2006.257.10:55:48.23#ibcon#read 5, iclass 37, count 0 2006.257.10:55:48.23#ibcon#about to read 6, iclass 37, count 0 2006.257.10:55:48.23#ibcon#read 6, iclass 37, count 0 2006.257.10:55:48.23#ibcon#end of sib2, iclass 37, count 0 2006.257.10:55:48.23#ibcon#*mode == 0, iclass 37, count 0 2006.257.10:55:48.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.10:55:48.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.10:55:48.23#ibcon#*before write, iclass 37, count 0 2006.257.10:55:48.23#ibcon#enter sib2, iclass 37, count 0 2006.257.10:55:48.23#ibcon#flushed, iclass 37, count 0 2006.257.10:55:48.23#ibcon#about to write, iclass 37, count 0 2006.257.10:55:48.23#ibcon#wrote, iclass 37, count 0 2006.257.10:55:48.23#ibcon#about to read 3, iclass 37, count 0 2006.257.10:55:48.27#ibcon#read 3, iclass 37, count 0 2006.257.10:55:48.27#ibcon#about to read 4, iclass 37, count 0 2006.257.10:55:48.27#ibcon#read 4, iclass 37, count 0 2006.257.10:55:48.27#ibcon#about to read 5, iclass 37, count 0 2006.257.10:55:48.27#ibcon#read 5, iclass 37, count 0 2006.257.10:55:48.27#ibcon#about to read 6, iclass 37, count 0 2006.257.10:55:48.27#ibcon#read 6, iclass 37, count 0 2006.257.10:55:48.27#ibcon#end of sib2, iclass 37, count 0 2006.257.10:55:48.27#ibcon#*after write, iclass 37, count 0 2006.257.10:55:48.27#ibcon#*before return 0, iclass 37, count 0 2006.257.10:55:48.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:48.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.10:55:48.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.10:55:48.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.10:55:48.27$vck44/vb=2,5 2006.257.10:55:48.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.10:55:48.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.10:55:48.27#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:48.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:48.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:48.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:48.33#ibcon#enter wrdev, iclass 39, count 2 2006.257.10:55:48.33#ibcon#first serial, iclass 39, count 2 2006.257.10:55:48.33#ibcon#enter sib2, iclass 39, count 2 2006.257.10:55:48.33#ibcon#flushed, iclass 39, count 2 2006.257.10:55:48.33#ibcon#about to write, iclass 39, count 2 2006.257.10:55:48.33#ibcon#wrote, iclass 39, count 2 2006.257.10:55:48.33#ibcon#about to read 3, iclass 39, count 2 2006.257.10:55:48.35#ibcon#read 3, iclass 39, count 2 2006.257.10:55:48.35#ibcon#about to read 4, iclass 39, count 2 2006.257.10:55:48.35#ibcon#read 4, iclass 39, count 2 2006.257.10:55:48.35#ibcon#about to read 5, iclass 39, count 2 2006.257.10:55:48.35#ibcon#read 5, iclass 39, count 2 2006.257.10:55:48.35#ibcon#about to read 6, iclass 39, count 2 2006.257.10:55:48.35#ibcon#read 6, iclass 39, count 2 2006.257.10:55:48.35#ibcon#end of sib2, iclass 39, count 2 2006.257.10:55:48.35#ibcon#*mode == 0, iclass 39, count 2 2006.257.10:55:48.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.10:55:48.35#ibcon#[27=AT02-05\r\n] 2006.257.10:55:48.35#ibcon#*before write, iclass 39, count 2 2006.257.10:55:48.35#ibcon#enter sib2, iclass 39, count 2 2006.257.10:55:48.35#ibcon#flushed, iclass 39, count 2 2006.257.10:55:48.35#ibcon#about to write, iclass 39, count 2 2006.257.10:55:48.35#ibcon#wrote, iclass 39, count 2 2006.257.10:55:48.35#ibcon#about to read 3, iclass 39, count 2 2006.257.10:55:48.38#ibcon#read 3, iclass 39, count 2 2006.257.10:55:48.38#ibcon#about to read 4, iclass 39, count 2 2006.257.10:55:48.38#ibcon#read 4, iclass 39, count 2 2006.257.10:55:48.38#ibcon#about to read 5, iclass 39, count 2 2006.257.10:55:48.38#ibcon#read 5, iclass 39, count 2 2006.257.10:55:48.38#ibcon#about to read 6, iclass 39, count 2 2006.257.10:55:48.38#ibcon#read 6, iclass 39, count 2 2006.257.10:55:48.38#ibcon#end of sib2, iclass 39, count 2 2006.257.10:55:48.38#ibcon#*after write, iclass 39, count 2 2006.257.10:55:48.38#ibcon#*before return 0, iclass 39, count 2 2006.257.10:55:48.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:48.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.10:55:48.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.10:55:48.38#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:48.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:48.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:48.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:48.50#ibcon#enter wrdev, iclass 39, count 0 2006.257.10:55:48.50#ibcon#first serial, iclass 39, count 0 2006.257.10:55:48.50#ibcon#enter sib2, iclass 39, count 0 2006.257.10:55:48.50#ibcon#flushed, iclass 39, count 0 2006.257.10:55:48.50#ibcon#about to write, iclass 39, count 0 2006.257.10:55:48.50#ibcon#wrote, iclass 39, count 0 2006.257.10:55:48.50#ibcon#about to read 3, iclass 39, count 0 2006.257.10:55:48.52#ibcon#read 3, iclass 39, count 0 2006.257.10:55:48.52#ibcon#about to read 4, iclass 39, count 0 2006.257.10:55:48.52#ibcon#read 4, iclass 39, count 0 2006.257.10:55:48.52#ibcon#about to read 5, iclass 39, count 0 2006.257.10:55:48.52#ibcon#read 5, iclass 39, count 0 2006.257.10:55:48.52#ibcon#about to read 6, iclass 39, count 0 2006.257.10:55:48.52#ibcon#read 6, iclass 39, count 0 2006.257.10:55:48.52#ibcon#end of sib2, iclass 39, count 0 2006.257.10:55:48.52#ibcon#*mode == 0, iclass 39, count 0 2006.257.10:55:48.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.10:55:48.52#ibcon#[27=USB\r\n] 2006.257.10:55:48.52#ibcon#*before write, iclass 39, count 0 2006.257.10:55:48.52#ibcon#enter sib2, iclass 39, count 0 2006.257.10:55:48.52#ibcon#flushed, iclass 39, count 0 2006.257.10:55:48.52#ibcon#about to write, iclass 39, count 0 2006.257.10:55:48.52#ibcon#wrote, iclass 39, count 0 2006.257.10:55:48.52#ibcon#about to read 3, iclass 39, count 0 2006.257.10:55:48.55#ibcon#read 3, iclass 39, count 0 2006.257.10:55:48.55#ibcon#about to read 4, iclass 39, count 0 2006.257.10:55:48.55#ibcon#read 4, iclass 39, count 0 2006.257.10:55:48.55#ibcon#about to read 5, iclass 39, count 0 2006.257.10:55:48.55#ibcon#read 5, iclass 39, count 0 2006.257.10:55:48.55#ibcon#about to read 6, iclass 39, count 0 2006.257.10:55:48.55#ibcon#read 6, iclass 39, count 0 2006.257.10:55:48.55#ibcon#end of sib2, iclass 39, count 0 2006.257.10:55:48.55#ibcon#*after write, iclass 39, count 0 2006.257.10:55:48.55#ibcon#*before return 0, iclass 39, count 0 2006.257.10:55:48.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:48.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.10:55:48.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.10:55:48.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.10:55:48.55$vck44/vblo=3,649.99 2006.257.10:55:48.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.10:55:48.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.10:55:48.55#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:48.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:48.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:48.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:48.55#ibcon#enter wrdev, iclass 3, count 0 2006.257.10:55:48.55#ibcon#first serial, iclass 3, count 0 2006.257.10:55:48.55#ibcon#enter sib2, iclass 3, count 0 2006.257.10:55:48.55#ibcon#flushed, iclass 3, count 0 2006.257.10:55:48.55#ibcon#about to write, iclass 3, count 0 2006.257.10:55:48.55#ibcon#wrote, iclass 3, count 0 2006.257.10:55:48.55#ibcon#about to read 3, iclass 3, count 0 2006.257.10:55:48.57#ibcon#read 3, iclass 3, count 0 2006.257.10:55:48.57#ibcon#about to read 4, iclass 3, count 0 2006.257.10:55:48.57#ibcon#read 4, iclass 3, count 0 2006.257.10:55:48.57#ibcon#about to read 5, iclass 3, count 0 2006.257.10:55:48.57#ibcon#read 5, iclass 3, count 0 2006.257.10:55:48.57#ibcon#about to read 6, iclass 3, count 0 2006.257.10:55:48.57#ibcon#read 6, iclass 3, count 0 2006.257.10:55:48.57#ibcon#end of sib2, iclass 3, count 0 2006.257.10:55:48.57#ibcon#*mode == 0, iclass 3, count 0 2006.257.10:55:48.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.10:55:48.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.10:55:48.57#ibcon#*before write, iclass 3, count 0 2006.257.10:55:48.57#ibcon#enter sib2, iclass 3, count 0 2006.257.10:55:48.57#ibcon#flushed, iclass 3, count 0 2006.257.10:55:48.57#ibcon#about to write, iclass 3, count 0 2006.257.10:55:48.57#ibcon#wrote, iclass 3, count 0 2006.257.10:55:48.57#ibcon#about to read 3, iclass 3, count 0 2006.257.10:55:48.61#ibcon#read 3, iclass 3, count 0 2006.257.10:55:48.61#ibcon#about to read 4, iclass 3, count 0 2006.257.10:55:48.61#ibcon#read 4, iclass 3, count 0 2006.257.10:55:48.61#ibcon#about to read 5, iclass 3, count 0 2006.257.10:55:48.61#ibcon#read 5, iclass 3, count 0 2006.257.10:55:48.62#ibcon#about to read 6, iclass 3, count 0 2006.257.10:55:48.62#ibcon#read 6, iclass 3, count 0 2006.257.10:55:48.62#ibcon#end of sib2, iclass 3, count 0 2006.257.10:55:48.62#ibcon#*after write, iclass 3, count 0 2006.257.10:55:48.62#ibcon#*before return 0, iclass 3, count 0 2006.257.10:55:48.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:48.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.10:55:48.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.10:55:48.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.10:55:48.62$vck44/vb=3,4 2006.257.10:55:48.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.10:55:48.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.10:55:48.62#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:48.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:48.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:48.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:48.66#ibcon#enter wrdev, iclass 5, count 2 2006.257.10:55:48.66#ibcon#first serial, iclass 5, count 2 2006.257.10:55:48.66#ibcon#enter sib2, iclass 5, count 2 2006.257.10:55:48.66#ibcon#flushed, iclass 5, count 2 2006.257.10:55:48.66#ibcon#about to write, iclass 5, count 2 2006.257.10:55:48.66#ibcon#wrote, iclass 5, count 2 2006.257.10:55:48.66#ibcon#about to read 3, iclass 5, count 2 2006.257.10:55:48.68#ibcon#read 3, iclass 5, count 2 2006.257.10:55:48.68#ibcon#about to read 4, iclass 5, count 2 2006.257.10:55:48.68#ibcon#read 4, iclass 5, count 2 2006.257.10:55:48.68#ibcon#about to read 5, iclass 5, count 2 2006.257.10:55:48.68#ibcon#read 5, iclass 5, count 2 2006.257.10:55:48.68#ibcon#about to read 6, iclass 5, count 2 2006.257.10:55:48.68#ibcon#read 6, iclass 5, count 2 2006.257.10:55:48.68#ibcon#end of sib2, iclass 5, count 2 2006.257.10:55:48.68#ibcon#*mode == 0, iclass 5, count 2 2006.257.10:55:48.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.10:55:48.68#ibcon#[27=AT03-04\r\n] 2006.257.10:55:48.68#ibcon#*before write, iclass 5, count 2 2006.257.10:55:48.68#ibcon#enter sib2, iclass 5, count 2 2006.257.10:55:48.68#ibcon#flushed, iclass 5, count 2 2006.257.10:55:48.68#ibcon#about to write, iclass 5, count 2 2006.257.10:55:48.68#ibcon#wrote, iclass 5, count 2 2006.257.10:55:48.68#ibcon#about to read 3, iclass 5, count 2 2006.257.10:55:48.71#ibcon#read 3, iclass 5, count 2 2006.257.10:55:48.71#ibcon#about to read 4, iclass 5, count 2 2006.257.10:55:48.71#ibcon#read 4, iclass 5, count 2 2006.257.10:55:48.71#ibcon#about to read 5, iclass 5, count 2 2006.257.10:55:48.71#ibcon#read 5, iclass 5, count 2 2006.257.10:55:48.71#ibcon#about to read 6, iclass 5, count 2 2006.257.10:55:48.71#ibcon#read 6, iclass 5, count 2 2006.257.10:55:48.71#ibcon#end of sib2, iclass 5, count 2 2006.257.10:55:48.71#ibcon#*after write, iclass 5, count 2 2006.257.10:55:48.71#ibcon#*before return 0, iclass 5, count 2 2006.257.10:55:48.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:48.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.10:55:48.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.10:55:48.71#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:48.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:48.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:48.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:48.83#ibcon#enter wrdev, iclass 5, count 0 2006.257.10:55:48.83#ibcon#first serial, iclass 5, count 0 2006.257.10:55:48.83#ibcon#enter sib2, iclass 5, count 0 2006.257.10:55:48.83#ibcon#flushed, iclass 5, count 0 2006.257.10:55:48.83#ibcon#about to write, iclass 5, count 0 2006.257.10:55:48.83#ibcon#wrote, iclass 5, count 0 2006.257.10:55:48.83#ibcon#about to read 3, iclass 5, count 0 2006.257.10:55:48.85#ibcon#read 3, iclass 5, count 0 2006.257.10:55:48.85#ibcon#about to read 4, iclass 5, count 0 2006.257.10:55:48.85#ibcon#read 4, iclass 5, count 0 2006.257.10:55:48.85#ibcon#about to read 5, iclass 5, count 0 2006.257.10:55:48.85#ibcon#read 5, iclass 5, count 0 2006.257.10:55:48.85#ibcon#about to read 6, iclass 5, count 0 2006.257.10:55:48.85#ibcon#read 6, iclass 5, count 0 2006.257.10:55:48.85#ibcon#end of sib2, iclass 5, count 0 2006.257.10:55:48.85#ibcon#*mode == 0, iclass 5, count 0 2006.257.10:55:48.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.10:55:48.85#ibcon#[27=USB\r\n] 2006.257.10:55:48.85#ibcon#*before write, iclass 5, count 0 2006.257.10:55:48.85#ibcon#enter sib2, iclass 5, count 0 2006.257.10:55:48.85#ibcon#flushed, iclass 5, count 0 2006.257.10:55:48.85#ibcon#about to write, iclass 5, count 0 2006.257.10:55:48.85#ibcon#wrote, iclass 5, count 0 2006.257.10:55:48.85#ibcon#about to read 3, iclass 5, count 0 2006.257.10:55:48.88#ibcon#read 3, iclass 5, count 0 2006.257.10:55:48.88#ibcon#about to read 4, iclass 5, count 0 2006.257.10:55:48.88#ibcon#read 4, iclass 5, count 0 2006.257.10:55:48.88#ibcon#about to read 5, iclass 5, count 0 2006.257.10:55:48.88#ibcon#read 5, iclass 5, count 0 2006.257.10:55:48.88#ibcon#about to read 6, iclass 5, count 0 2006.257.10:55:48.88#ibcon#read 6, iclass 5, count 0 2006.257.10:55:48.88#ibcon#end of sib2, iclass 5, count 0 2006.257.10:55:48.88#ibcon#*after write, iclass 5, count 0 2006.257.10:55:48.88#ibcon#*before return 0, iclass 5, count 0 2006.257.10:55:48.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:48.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.10:55:48.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.10:55:48.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.10:55:48.88$vck44/vblo=4,679.99 2006.257.10:55:48.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.10:55:48.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.10:55:48.88#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:48.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:48.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:48.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:48.88#ibcon#enter wrdev, iclass 7, count 0 2006.257.10:55:48.88#ibcon#first serial, iclass 7, count 0 2006.257.10:55:48.88#ibcon#enter sib2, iclass 7, count 0 2006.257.10:55:48.88#ibcon#flushed, iclass 7, count 0 2006.257.10:55:48.88#ibcon#about to write, iclass 7, count 0 2006.257.10:55:48.88#ibcon#wrote, iclass 7, count 0 2006.257.10:55:48.88#ibcon#about to read 3, iclass 7, count 0 2006.257.10:55:48.90#ibcon#read 3, iclass 7, count 0 2006.257.10:55:48.90#ibcon#about to read 4, iclass 7, count 0 2006.257.10:55:48.90#ibcon#read 4, iclass 7, count 0 2006.257.10:55:48.90#ibcon#about to read 5, iclass 7, count 0 2006.257.10:55:48.90#ibcon#read 5, iclass 7, count 0 2006.257.10:55:48.90#ibcon#about to read 6, iclass 7, count 0 2006.257.10:55:48.90#ibcon#read 6, iclass 7, count 0 2006.257.10:55:48.90#ibcon#end of sib2, iclass 7, count 0 2006.257.10:55:48.90#ibcon#*mode == 0, iclass 7, count 0 2006.257.10:55:48.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.10:55:48.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.10:55:48.90#ibcon#*before write, iclass 7, count 0 2006.257.10:55:48.90#ibcon#enter sib2, iclass 7, count 0 2006.257.10:55:48.90#ibcon#flushed, iclass 7, count 0 2006.257.10:55:48.90#ibcon#about to write, iclass 7, count 0 2006.257.10:55:48.90#ibcon#wrote, iclass 7, count 0 2006.257.10:55:48.90#ibcon#about to read 3, iclass 7, count 0 2006.257.10:55:48.94#ibcon#read 3, iclass 7, count 0 2006.257.10:55:48.94#ibcon#about to read 4, iclass 7, count 0 2006.257.10:55:48.94#ibcon#read 4, iclass 7, count 0 2006.257.10:55:48.94#ibcon#about to read 5, iclass 7, count 0 2006.257.10:55:48.94#ibcon#read 5, iclass 7, count 0 2006.257.10:55:48.94#ibcon#about to read 6, iclass 7, count 0 2006.257.10:55:48.94#ibcon#read 6, iclass 7, count 0 2006.257.10:55:48.94#ibcon#end of sib2, iclass 7, count 0 2006.257.10:55:48.94#ibcon#*after write, iclass 7, count 0 2006.257.10:55:48.94#ibcon#*before return 0, iclass 7, count 0 2006.257.10:55:48.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:48.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.10:55:48.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.10:55:48.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.10:55:48.94$vck44/vb=4,5 2006.257.10:55:48.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.10:55:48.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.10:55:48.94#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:48.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:49.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:49.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:49.00#ibcon#enter wrdev, iclass 11, count 2 2006.257.10:55:49.00#ibcon#first serial, iclass 11, count 2 2006.257.10:55:49.00#ibcon#enter sib2, iclass 11, count 2 2006.257.10:55:49.00#ibcon#flushed, iclass 11, count 2 2006.257.10:55:49.00#ibcon#about to write, iclass 11, count 2 2006.257.10:55:49.00#ibcon#wrote, iclass 11, count 2 2006.257.10:55:49.00#ibcon#about to read 3, iclass 11, count 2 2006.257.10:55:49.02#ibcon#read 3, iclass 11, count 2 2006.257.10:55:49.02#ibcon#about to read 4, iclass 11, count 2 2006.257.10:55:49.02#ibcon#read 4, iclass 11, count 2 2006.257.10:55:49.02#ibcon#about to read 5, iclass 11, count 2 2006.257.10:55:49.02#ibcon#read 5, iclass 11, count 2 2006.257.10:55:49.02#ibcon#about to read 6, iclass 11, count 2 2006.257.10:55:49.02#ibcon#read 6, iclass 11, count 2 2006.257.10:55:49.02#ibcon#end of sib2, iclass 11, count 2 2006.257.10:55:49.02#ibcon#*mode == 0, iclass 11, count 2 2006.257.10:55:49.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.10:55:49.02#ibcon#[27=AT04-05\r\n] 2006.257.10:55:49.02#ibcon#*before write, iclass 11, count 2 2006.257.10:55:49.02#ibcon#enter sib2, iclass 11, count 2 2006.257.10:55:49.02#ibcon#flushed, iclass 11, count 2 2006.257.10:55:49.02#ibcon#about to write, iclass 11, count 2 2006.257.10:55:49.02#ibcon#wrote, iclass 11, count 2 2006.257.10:55:49.02#ibcon#about to read 3, iclass 11, count 2 2006.257.10:55:49.05#ibcon#read 3, iclass 11, count 2 2006.257.10:55:49.05#ibcon#about to read 4, iclass 11, count 2 2006.257.10:55:49.05#ibcon#read 4, iclass 11, count 2 2006.257.10:55:49.05#ibcon#about to read 5, iclass 11, count 2 2006.257.10:55:49.05#ibcon#read 5, iclass 11, count 2 2006.257.10:55:49.05#ibcon#about to read 6, iclass 11, count 2 2006.257.10:55:49.05#ibcon#read 6, iclass 11, count 2 2006.257.10:55:49.05#ibcon#end of sib2, iclass 11, count 2 2006.257.10:55:49.05#ibcon#*after write, iclass 11, count 2 2006.257.10:55:49.05#ibcon#*before return 0, iclass 11, count 2 2006.257.10:55:49.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:49.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.10:55:49.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.10:55:49.05#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:49.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:49.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:49.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:49.17#ibcon#enter wrdev, iclass 11, count 0 2006.257.10:55:49.17#ibcon#first serial, iclass 11, count 0 2006.257.10:55:49.17#ibcon#enter sib2, iclass 11, count 0 2006.257.10:55:49.17#ibcon#flushed, iclass 11, count 0 2006.257.10:55:49.17#ibcon#about to write, iclass 11, count 0 2006.257.10:55:49.17#ibcon#wrote, iclass 11, count 0 2006.257.10:55:49.17#ibcon#about to read 3, iclass 11, count 0 2006.257.10:55:49.19#ibcon#read 3, iclass 11, count 0 2006.257.10:55:49.19#ibcon#about to read 4, iclass 11, count 0 2006.257.10:55:49.19#ibcon#read 4, iclass 11, count 0 2006.257.10:55:49.19#ibcon#about to read 5, iclass 11, count 0 2006.257.10:55:49.19#ibcon#read 5, iclass 11, count 0 2006.257.10:55:49.19#ibcon#about to read 6, iclass 11, count 0 2006.257.10:55:49.19#ibcon#read 6, iclass 11, count 0 2006.257.10:55:49.19#ibcon#end of sib2, iclass 11, count 0 2006.257.10:55:49.19#ibcon#*mode == 0, iclass 11, count 0 2006.257.10:55:49.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.10:55:49.19#ibcon#[27=USB\r\n] 2006.257.10:55:49.19#ibcon#*before write, iclass 11, count 0 2006.257.10:55:49.19#ibcon#enter sib2, iclass 11, count 0 2006.257.10:55:49.19#ibcon#flushed, iclass 11, count 0 2006.257.10:55:49.19#ibcon#about to write, iclass 11, count 0 2006.257.10:55:49.19#ibcon#wrote, iclass 11, count 0 2006.257.10:55:49.19#ibcon#about to read 3, iclass 11, count 0 2006.257.10:55:49.22#ibcon#read 3, iclass 11, count 0 2006.257.10:55:49.22#ibcon#about to read 4, iclass 11, count 0 2006.257.10:55:49.22#ibcon#read 4, iclass 11, count 0 2006.257.10:55:49.22#ibcon#about to read 5, iclass 11, count 0 2006.257.10:55:49.22#ibcon#read 5, iclass 11, count 0 2006.257.10:55:49.22#ibcon#about to read 6, iclass 11, count 0 2006.257.10:55:49.22#ibcon#read 6, iclass 11, count 0 2006.257.10:55:49.22#ibcon#end of sib2, iclass 11, count 0 2006.257.10:55:49.22#ibcon#*after write, iclass 11, count 0 2006.257.10:55:49.22#ibcon#*before return 0, iclass 11, count 0 2006.257.10:55:49.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:49.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.10:55:49.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.10:55:49.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.10:55:49.22$vck44/vblo=5,709.99 2006.257.10:55:49.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.10:55:49.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.10:55:49.22#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:49.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:49.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:49.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:49.22#ibcon#enter wrdev, iclass 13, count 0 2006.257.10:55:49.22#ibcon#first serial, iclass 13, count 0 2006.257.10:55:49.22#ibcon#enter sib2, iclass 13, count 0 2006.257.10:55:49.22#ibcon#flushed, iclass 13, count 0 2006.257.10:55:49.22#ibcon#about to write, iclass 13, count 0 2006.257.10:55:49.22#ibcon#wrote, iclass 13, count 0 2006.257.10:55:49.22#ibcon#about to read 3, iclass 13, count 0 2006.257.10:55:49.24#ibcon#read 3, iclass 13, count 0 2006.257.10:55:49.24#ibcon#about to read 4, iclass 13, count 0 2006.257.10:55:49.24#ibcon#read 4, iclass 13, count 0 2006.257.10:55:49.24#ibcon#about to read 5, iclass 13, count 0 2006.257.10:55:49.24#ibcon#read 5, iclass 13, count 0 2006.257.10:55:49.24#ibcon#about to read 6, iclass 13, count 0 2006.257.10:55:49.24#ibcon#read 6, iclass 13, count 0 2006.257.10:55:49.24#ibcon#end of sib2, iclass 13, count 0 2006.257.10:55:49.24#ibcon#*mode == 0, iclass 13, count 0 2006.257.10:55:49.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.10:55:49.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.10:55:49.24#ibcon#*before write, iclass 13, count 0 2006.257.10:55:49.24#ibcon#enter sib2, iclass 13, count 0 2006.257.10:55:49.24#ibcon#flushed, iclass 13, count 0 2006.257.10:55:49.24#ibcon#about to write, iclass 13, count 0 2006.257.10:55:49.24#ibcon#wrote, iclass 13, count 0 2006.257.10:55:49.24#ibcon#about to read 3, iclass 13, count 0 2006.257.10:55:49.28#ibcon#read 3, iclass 13, count 0 2006.257.10:55:49.28#ibcon#about to read 4, iclass 13, count 0 2006.257.10:55:49.28#ibcon#read 4, iclass 13, count 0 2006.257.10:55:49.28#ibcon#about to read 5, iclass 13, count 0 2006.257.10:55:49.28#ibcon#read 5, iclass 13, count 0 2006.257.10:55:49.28#ibcon#about to read 6, iclass 13, count 0 2006.257.10:55:49.28#ibcon#read 6, iclass 13, count 0 2006.257.10:55:49.28#ibcon#end of sib2, iclass 13, count 0 2006.257.10:55:49.28#ibcon#*after write, iclass 13, count 0 2006.257.10:55:49.28#ibcon#*before return 0, iclass 13, count 0 2006.257.10:55:49.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:49.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.10:55:49.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.10:55:49.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.10:55:49.28$vck44/vb=5,4 2006.257.10:55:49.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.10:55:49.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.10:55:49.28#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:49.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:49.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:49.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:49.34#ibcon#enter wrdev, iclass 15, count 2 2006.257.10:55:49.34#ibcon#first serial, iclass 15, count 2 2006.257.10:55:49.34#ibcon#enter sib2, iclass 15, count 2 2006.257.10:55:49.34#ibcon#flushed, iclass 15, count 2 2006.257.10:55:49.34#ibcon#about to write, iclass 15, count 2 2006.257.10:55:49.34#ibcon#wrote, iclass 15, count 2 2006.257.10:55:49.34#ibcon#about to read 3, iclass 15, count 2 2006.257.10:55:49.36#ibcon#read 3, iclass 15, count 2 2006.257.10:55:49.36#ibcon#about to read 4, iclass 15, count 2 2006.257.10:55:49.36#ibcon#read 4, iclass 15, count 2 2006.257.10:55:49.36#ibcon#about to read 5, iclass 15, count 2 2006.257.10:55:49.36#ibcon#read 5, iclass 15, count 2 2006.257.10:55:49.36#ibcon#about to read 6, iclass 15, count 2 2006.257.10:55:49.36#ibcon#read 6, iclass 15, count 2 2006.257.10:55:49.36#ibcon#end of sib2, iclass 15, count 2 2006.257.10:55:49.36#ibcon#*mode == 0, iclass 15, count 2 2006.257.10:55:49.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.10:55:49.36#ibcon#[27=AT05-04\r\n] 2006.257.10:55:49.36#ibcon#*before write, iclass 15, count 2 2006.257.10:55:49.36#ibcon#enter sib2, iclass 15, count 2 2006.257.10:55:49.36#ibcon#flushed, iclass 15, count 2 2006.257.10:55:49.36#ibcon#about to write, iclass 15, count 2 2006.257.10:55:49.36#ibcon#wrote, iclass 15, count 2 2006.257.10:55:49.36#ibcon#about to read 3, iclass 15, count 2 2006.257.10:55:49.39#ibcon#read 3, iclass 15, count 2 2006.257.10:55:49.39#ibcon#about to read 4, iclass 15, count 2 2006.257.10:55:49.39#ibcon#read 4, iclass 15, count 2 2006.257.10:55:49.39#ibcon#about to read 5, iclass 15, count 2 2006.257.10:55:49.39#ibcon#read 5, iclass 15, count 2 2006.257.10:55:49.39#ibcon#about to read 6, iclass 15, count 2 2006.257.10:55:49.39#ibcon#read 6, iclass 15, count 2 2006.257.10:55:49.39#ibcon#end of sib2, iclass 15, count 2 2006.257.10:55:49.39#ibcon#*after write, iclass 15, count 2 2006.257.10:55:49.39#ibcon#*before return 0, iclass 15, count 2 2006.257.10:55:49.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:49.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.10:55:49.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.10:55:49.39#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:49.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:49.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:49.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:49.51#ibcon#enter wrdev, iclass 15, count 0 2006.257.10:55:49.51#ibcon#first serial, iclass 15, count 0 2006.257.10:55:49.51#ibcon#enter sib2, iclass 15, count 0 2006.257.10:55:49.51#ibcon#flushed, iclass 15, count 0 2006.257.10:55:49.51#ibcon#about to write, iclass 15, count 0 2006.257.10:55:49.51#ibcon#wrote, iclass 15, count 0 2006.257.10:55:49.51#ibcon#about to read 3, iclass 15, count 0 2006.257.10:55:49.53#ibcon#read 3, iclass 15, count 0 2006.257.10:55:49.53#ibcon#about to read 4, iclass 15, count 0 2006.257.10:55:49.53#ibcon#read 4, iclass 15, count 0 2006.257.10:55:49.53#ibcon#about to read 5, iclass 15, count 0 2006.257.10:55:49.53#ibcon#read 5, iclass 15, count 0 2006.257.10:55:49.53#ibcon#about to read 6, iclass 15, count 0 2006.257.10:55:49.53#ibcon#read 6, iclass 15, count 0 2006.257.10:55:49.53#ibcon#end of sib2, iclass 15, count 0 2006.257.10:55:49.53#ibcon#*mode == 0, iclass 15, count 0 2006.257.10:55:49.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.10:55:49.53#ibcon#[27=USB\r\n] 2006.257.10:55:49.53#ibcon#*before write, iclass 15, count 0 2006.257.10:55:49.53#ibcon#enter sib2, iclass 15, count 0 2006.257.10:55:49.53#ibcon#flushed, iclass 15, count 0 2006.257.10:55:49.53#ibcon#about to write, iclass 15, count 0 2006.257.10:55:49.53#ibcon#wrote, iclass 15, count 0 2006.257.10:55:49.53#ibcon#about to read 3, iclass 15, count 0 2006.257.10:55:49.56#ibcon#read 3, iclass 15, count 0 2006.257.10:55:49.56#ibcon#about to read 4, iclass 15, count 0 2006.257.10:55:49.56#ibcon#read 4, iclass 15, count 0 2006.257.10:55:49.56#ibcon#about to read 5, iclass 15, count 0 2006.257.10:55:49.56#ibcon#read 5, iclass 15, count 0 2006.257.10:55:49.56#ibcon#about to read 6, iclass 15, count 0 2006.257.10:55:49.56#ibcon#read 6, iclass 15, count 0 2006.257.10:55:49.56#ibcon#end of sib2, iclass 15, count 0 2006.257.10:55:49.56#ibcon#*after write, iclass 15, count 0 2006.257.10:55:49.56#ibcon#*before return 0, iclass 15, count 0 2006.257.10:55:49.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:49.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.10:55:49.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.10:55:49.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.10:55:49.56$vck44/vblo=6,719.99 2006.257.10:55:49.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.10:55:49.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.10:55:49.56#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:49.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:49.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:49.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:49.56#ibcon#enter wrdev, iclass 17, count 0 2006.257.10:55:49.56#ibcon#first serial, iclass 17, count 0 2006.257.10:55:49.56#ibcon#enter sib2, iclass 17, count 0 2006.257.10:55:49.56#ibcon#flushed, iclass 17, count 0 2006.257.10:55:49.56#ibcon#about to write, iclass 17, count 0 2006.257.10:55:49.56#ibcon#wrote, iclass 17, count 0 2006.257.10:55:49.56#ibcon#about to read 3, iclass 17, count 0 2006.257.10:55:49.58#ibcon#read 3, iclass 17, count 0 2006.257.10:55:49.58#ibcon#about to read 4, iclass 17, count 0 2006.257.10:55:49.58#ibcon#read 4, iclass 17, count 0 2006.257.10:55:49.58#ibcon#about to read 5, iclass 17, count 0 2006.257.10:55:49.58#ibcon#read 5, iclass 17, count 0 2006.257.10:55:49.58#ibcon#about to read 6, iclass 17, count 0 2006.257.10:55:49.58#ibcon#read 6, iclass 17, count 0 2006.257.10:55:49.58#ibcon#end of sib2, iclass 17, count 0 2006.257.10:55:49.58#ibcon#*mode == 0, iclass 17, count 0 2006.257.10:55:49.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.10:55:49.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.10:55:49.58#ibcon#*before write, iclass 17, count 0 2006.257.10:55:49.58#ibcon#enter sib2, iclass 17, count 0 2006.257.10:55:49.58#ibcon#flushed, iclass 17, count 0 2006.257.10:55:49.58#ibcon#about to write, iclass 17, count 0 2006.257.10:55:49.58#ibcon#wrote, iclass 17, count 0 2006.257.10:55:49.58#ibcon#about to read 3, iclass 17, count 0 2006.257.10:55:49.62#ibcon#read 3, iclass 17, count 0 2006.257.10:55:49.62#ibcon#about to read 4, iclass 17, count 0 2006.257.10:55:49.62#ibcon#read 4, iclass 17, count 0 2006.257.10:55:49.62#ibcon#about to read 5, iclass 17, count 0 2006.257.10:55:49.62#ibcon#read 5, iclass 17, count 0 2006.257.10:55:49.62#ibcon#about to read 6, iclass 17, count 0 2006.257.10:55:49.62#ibcon#read 6, iclass 17, count 0 2006.257.10:55:49.62#ibcon#end of sib2, iclass 17, count 0 2006.257.10:55:49.62#ibcon#*after write, iclass 17, count 0 2006.257.10:55:49.62#ibcon#*before return 0, iclass 17, count 0 2006.257.10:55:49.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:49.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.10:55:49.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.10:55:49.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.10:55:49.62$vck44/vb=6,4 2006.257.10:55:49.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.10:55:49.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.10:55:49.62#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:49.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:49.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:49.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:49.68#ibcon#enter wrdev, iclass 19, count 2 2006.257.10:55:49.68#ibcon#first serial, iclass 19, count 2 2006.257.10:55:49.68#ibcon#enter sib2, iclass 19, count 2 2006.257.10:55:49.68#ibcon#flushed, iclass 19, count 2 2006.257.10:55:49.68#ibcon#about to write, iclass 19, count 2 2006.257.10:55:49.68#ibcon#wrote, iclass 19, count 2 2006.257.10:55:49.68#ibcon#about to read 3, iclass 19, count 2 2006.257.10:55:49.70#ibcon#read 3, iclass 19, count 2 2006.257.10:55:49.70#ibcon#about to read 4, iclass 19, count 2 2006.257.10:55:49.70#ibcon#read 4, iclass 19, count 2 2006.257.10:55:49.70#ibcon#about to read 5, iclass 19, count 2 2006.257.10:55:49.70#ibcon#read 5, iclass 19, count 2 2006.257.10:55:49.70#ibcon#about to read 6, iclass 19, count 2 2006.257.10:55:49.70#ibcon#read 6, iclass 19, count 2 2006.257.10:55:49.70#ibcon#end of sib2, iclass 19, count 2 2006.257.10:55:49.70#ibcon#*mode == 0, iclass 19, count 2 2006.257.10:55:49.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.10:55:49.70#ibcon#[27=AT06-04\r\n] 2006.257.10:55:49.70#ibcon#*before write, iclass 19, count 2 2006.257.10:55:49.70#ibcon#enter sib2, iclass 19, count 2 2006.257.10:55:49.70#ibcon#flushed, iclass 19, count 2 2006.257.10:55:49.70#ibcon#about to write, iclass 19, count 2 2006.257.10:55:49.70#ibcon#wrote, iclass 19, count 2 2006.257.10:55:49.70#ibcon#about to read 3, iclass 19, count 2 2006.257.10:55:49.73#ibcon#read 3, iclass 19, count 2 2006.257.10:55:49.73#ibcon#about to read 4, iclass 19, count 2 2006.257.10:55:49.73#ibcon#read 4, iclass 19, count 2 2006.257.10:55:49.73#ibcon#about to read 5, iclass 19, count 2 2006.257.10:55:49.73#ibcon#read 5, iclass 19, count 2 2006.257.10:55:49.73#ibcon#about to read 6, iclass 19, count 2 2006.257.10:55:49.73#ibcon#read 6, iclass 19, count 2 2006.257.10:55:49.73#ibcon#end of sib2, iclass 19, count 2 2006.257.10:55:49.73#ibcon#*after write, iclass 19, count 2 2006.257.10:55:49.73#ibcon#*before return 0, iclass 19, count 2 2006.257.10:55:49.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:49.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.10:55:49.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.10:55:49.73#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:49.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:49.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:49.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:49.85#ibcon#enter wrdev, iclass 19, count 0 2006.257.10:55:49.85#ibcon#first serial, iclass 19, count 0 2006.257.10:55:49.85#ibcon#enter sib2, iclass 19, count 0 2006.257.10:55:49.85#ibcon#flushed, iclass 19, count 0 2006.257.10:55:49.85#ibcon#about to write, iclass 19, count 0 2006.257.10:55:49.85#ibcon#wrote, iclass 19, count 0 2006.257.10:55:49.85#ibcon#about to read 3, iclass 19, count 0 2006.257.10:55:49.87#ibcon#read 3, iclass 19, count 0 2006.257.10:55:49.87#ibcon#about to read 4, iclass 19, count 0 2006.257.10:55:49.87#ibcon#read 4, iclass 19, count 0 2006.257.10:55:49.87#ibcon#about to read 5, iclass 19, count 0 2006.257.10:55:49.87#ibcon#read 5, iclass 19, count 0 2006.257.10:55:49.87#ibcon#about to read 6, iclass 19, count 0 2006.257.10:55:49.87#ibcon#read 6, iclass 19, count 0 2006.257.10:55:49.87#ibcon#end of sib2, iclass 19, count 0 2006.257.10:55:49.87#ibcon#*mode == 0, iclass 19, count 0 2006.257.10:55:49.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.10:55:49.87#ibcon#[27=USB\r\n] 2006.257.10:55:49.87#ibcon#*before write, iclass 19, count 0 2006.257.10:55:49.87#ibcon#enter sib2, iclass 19, count 0 2006.257.10:55:49.87#ibcon#flushed, iclass 19, count 0 2006.257.10:55:49.87#ibcon#about to write, iclass 19, count 0 2006.257.10:55:49.87#ibcon#wrote, iclass 19, count 0 2006.257.10:55:49.87#ibcon#about to read 3, iclass 19, count 0 2006.257.10:55:49.90#ibcon#read 3, iclass 19, count 0 2006.257.10:55:49.90#ibcon#about to read 4, iclass 19, count 0 2006.257.10:55:49.90#ibcon#read 4, iclass 19, count 0 2006.257.10:55:49.90#ibcon#about to read 5, iclass 19, count 0 2006.257.10:55:49.90#ibcon#read 5, iclass 19, count 0 2006.257.10:55:49.90#ibcon#about to read 6, iclass 19, count 0 2006.257.10:55:49.90#ibcon#read 6, iclass 19, count 0 2006.257.10:55:49.90#ibcon#end of sib2, iclass 19, count 0 2006.257.10:55:49.90#ibcon#*after write, iclass 19, count 0 2006.257.10:55:49.90#ibcon#*before return 0, iclass 19, count 0 2006.257.10:55:49.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:49.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.10:55:49.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.10:55:49.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.10:55:49.90$vck44/vblo=7,734.99 2006.257.10:55:49.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.10:55:49.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.10:55:49.90#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:49.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:49.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:49.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:49.90#ibcon#enter wrdev, iclass 21, count 0 2006.257.10:55:49.90#ibcon#first serial, iclass 21, count 0 2006.257.10:55:49.90#ibcon#enter sib2, iclass 21, count 0 2006.257.10:55:49.90#ibcon#flushed, iclass 21, count 0 2006.257.10:55:49.90#ibcon#about to write, iclass 21, count 0 2006.257.10:55:49.90#ibcon#wrote, iclass 21, count 0 2006.257.10:55:49.90#ibcon#about to read 3, iclass 21, count 0 2006.257.10:55:49.92#ibcon#read 3, iclass 21, count 0 2006.257.10:55:49.92#ibcon#about to read 4, iclass 21, count 0 2006.257.10:55:49.92#ibcon#read 4, iclass 21, count 0 2006.257.10:55:49.92#ibcon#about to read 5, iclass 21, count 0 2006.257.10:55:49.92#ibcon#read 5, iclass 21, count 0 2006.257.10:55:49.92#ibcon#about to read 6, iclass 21, count 0 2006.257.10:55:49.92#ibcon#read 6, iclass 21, count 0 2006.257.10:55:49.92#ibcon#end of sib2, iclass 21, count 0 2006.257.10:55:49.92#ibcon#*mode == 0, iclass 21, count 0 2006.257.10:55:49.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.10:55:49.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.10:55:49.92#ibcon#*before write, iclass 21, count 0 2006.257.10:55:49.92#ibcon#enter sib2, iclass 21, count 0 2006.257.10:55:49.92#ibcon#flushed, iclass 21, count 0 2006.257.10:55:49.92#ibcon#about to write, iclass 21, count 0 2006.257.10:55:49.92#ibcon#wrote, iclass 21, count 0 2006.257.10:55:49.92#ibcon#about to read 3, iclass 21, count 0 2006.257.10:55:49.96#ibcon#read 3, iclass 21, count 0 2006.257.10:55:49.96#ibcon#about to read 4, iclass 21, count 0 2006.257.10:55:49.96#ibcon#read 4, iclass 21, count 0 2006.257.10:55:49.96#ibcon#about to read 5, iclass 21, count 0 2006.257.10:55:49.96#ibcon#read 5, iclass 21, count 0 2006.257.10:55:49.96#ibcon#about to read 6, iclass 21, count 0 2006.257.10:55:49.96#ibcon#read 6, iclass 21, count 0 2006.257.10:55:49.96#ibcon#end of sib2, iclass 21, count 0 2006.257.10:55:49.96#ibcon#*after write, iclass 21, count 0 2006.257.10:55:49.96#ibcon#*before return 0, iclass 21, count 0 2006.257.10:55:49.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:49.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.10:55:49.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.10:55:49.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.10:55:49.96$vck44/vb=7,4 2006.257.10:55:49.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.10:55:49.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.10:55:49.96#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:49.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:50.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:50.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:50.02#ibcon#enter wrdev, iclass 23, count 2 2006.257.10:55:50.02#ibcon#first serial, iclass 23, count 2 2006.257.10:55:50.02#ibcon#enter sib2, iclass 23, count 2 2006.257.10:55:50.02#ibcon#flushed, iclass 23, count 2 2006.257.10:55:50.02#ibcon#about to write, iclass 23, count 2 2006.257.10:55:50.02#ibcon#wrote, iclass 23, count 2 2006.257.10:55:50.02#ibcon#about to read 3, iclass 23, count 2 2006.257.10:55:50.04#ibcon#read 3, iclass 23, count 2 2006.257.10:55:50.04#ibcon#about to read 4, iclass 23, count 2 2006.257.10:55:50.04#ibcon#read 4, iclass 23, count 2 2006.257.10:55:50.04#ibcon#about to read 5, iclass 23, count 2 2006.257.10:55:50.04#ibcon#read 5, iclass 23, count 2 2006.257.10:55:50.04#ibcon#about to read 6, iclass 23, count 2 2006.257.10:55:50.04#ibcon#read 6, iclass 23, count 2 2006.257.10:55:50.04#ibcon#end of sib2, iclass 23, count 2 2006.257.10:55:50.04#ibcon#*mode == 0, iclass 23, count 2 2006.257.10:55:50.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.10:55:50.04#ibcon#[27=AT07-04\r\n] 2006.257.10:55:50.04#ibcon#*before write, iclass 23, count 2 2006.257.10:55:50.04#ibcon#enter sib2, iclass 23, count 2 2006.257.10:55:50.04#ibcon#flushed, iclass 23, count 2 2006.257.10:55:50.04#ibcon#about to write, iclass 23, count 2 2006.257.10:55:50.04#ibcon#wrote, iclass 23, count 2 2006.257.10:55:50.04#ibcon#about to read 3, iclass 23, count 2 2006.257.10:55:50.07#ibcon#read 3, iclass 23, count 2 2006.257.10:55:50.07#ibcon#about to read 4, iclass 23, count 2 2006.257.10:55:50.07#ibcon#read 4, iclass 23, count 2 2006.257.10:55:50.07#ibcon#about to read 5, iclass 23, count 2 2006.257.10:55:50.07#ibcon#read 5, iclass 23, count 2 2006.257.10:55:50.07#ibcon#about to read 6, iclass 23, count 2 2006.257.10:55:50.07#ibcon#read 6, iclass 23, count 2 2006.257.10:55:50.07#ibcon#end of sib2, iclass 23, count 2 2006.257.10:55:50.07#ibcon#*after write, iclass 23, count 2 2006.257.10:55:50.07#ibcon#*before return 0, iclass 23, count 2 2006.257.10:55:50.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:50.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.10:55:50.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.10:55:50.07#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:50.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:50.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:50.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:50.19#ibcon#enter wrdev, iclass 23, count 0 2006.257.10:55:50.19#ibcon#first serial, iclass 23, count 0 2006.257.10:55:50.19#ibcon#enter sib2, iclass 23, count 0 2006.257.10:55:50.19#ibcon#flushed, iclass 23, count 0 2006.257.10:55:50.19#ibcon#about to write, iclass 23, count 0 2006.257.10:55:50.19#ibcon#wrote, iclass 23, count 0 2006.257.10:55:50.19#ibcon#about to read 3, iclass 23, count 0 2006.257.10:55:50.21#ibcon#read 3, iclass 23, count 0 2006.257.10:55:50.21#ibcon#about to read 4, iclass 23, count 0 2006.257.10:55:50.21#ibcon#read 4, iclass 23, count 0 2006.257.10:55:50.21#ibcon#about to read 5, iclass 23, count 0 2006.257.10:55:50.21#ibcon#read 5, iclass 23, count 0 2006.257.10:55:50.21#ibcon#about to read 6, iclass 23, count 0 2006.257.10:55:50.21#ibcon#read 6, iclass 23, count 0 2006.257.10:55:50.21#ibcon#end of sib2, iclass 23, count 0 2006.257.10:55:50.21#ibcon#*mode == 0, iclass 23, count 0 2006.257.10:55:50.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.10:55:50.21#ibcon#[27=USB\r\n] 2006.257.10:55:50.21#ibcon#*before write, iclass 23, count 0 2006.257.10:55:50.21#ibcon#enter sib2, iclass 23, count 0 2006.257.10:55:50.21#ibcon#flushed, iclass 23, count 0 2006.257.10:55:50.21#ibcon#about to write, iclass 23, count 0 2006.257.10:55:50.21#ibcon#wrote, iclass 23, count 0 2006.257.10:55:50.21#ibcon#about to read 3, iclass 23, count 0 2006.257.10:55:50.24#ibcon#read 3, iclass 23, count 0 2006.257.10:55:50.24#ibcon#about to read 4, iclass 23, count 0 2006.257.10:55:50.24#ibcon#read 4, iclass 23, count 0 2006.257.10:55:50.24#ibcon#about to read 5, iclass 23, count 0 2006.257.10:55:50.24#ibcon#read 5, iclass 23, count 0 2006.257.10:55:50.24#ibcon#about to read 6, iclass 23, count 0 2006.257.10:55:50.24#ibcon#read 6, iclass 23, count 0 2006.257.10:55:50.24#ibcon#end of sib2, iclass 23, count 0 2006.257.10:55:50.24#ibcon#*after write, iclass 23, count 0 2006.257.10:55:50.24#ibcon#*before return 0, iclass 23, count 0 2006.257.10:55:50.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:50.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.10:55:50.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.10:55:50.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.10:55:50.24$vck44/vblo=8,744.99 2006.257.10:55:50.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.10:55:50.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.10:55:50.24#ibcon#ireg 17 cls_cnt 0 2006.257.10:55:50.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:50.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:50.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:50.24#ibcon#enter wrdev, iclass 25, count 0 2006.257.10:55:50.24#ibcon#first serial, iclass 25, count 0 2006.257.10:55:50.24#ibcon#enter sib2, iclass 25, count 0 2006.257.10:55:50.24#ibcon#flushed, iclass 25, count 0 2006.257.10:55:50.24#ibcon#about to write, iclass 25, count 0 2006.257.10:55:50.24#ibcon#wrote, iclass 25, count 0 2006.257.10:55:50.24#ibcon#about to read 3, iclass 25, count 0 2006.257.10:55:50.26#ibcon#read 3, iclass 25, count 0 2006.257.10:55:50.26#ibcon#about to read 4, iclass 25, count 0 2006.257.10:55:50.26#ibcon#read 4, iclass 25, count 0 2006.257.10:55:50.26#ibcon#about to read 5, iclass 25, count 0 2006.257.10:55:50.26#ibcon#read 5, iclass 25, count 0 2006.257.10:55:50.26#ibcon#about to read 6, iclass 25, count 0 2006.257.10:55:50.26#ibcon#read 6, iclass 25, count 0 2006.257.10:55:50.26#ibcon#end of sib2, iclass 25, count 0 2006.257.10:55:50.26#ibcon#*mode == 0, iclass 25, count 0 2006.257.10:55:50.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.10:55:50.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.10:55:50.26#ibcon#*before write, iclass 25, count 0 2006.257.10:55:50.26#ibcon#enter sib2, iclass 25, count 0 2006.257.10:55:50.26#ibcon#flushed, iclass 25, count 0 2006.257.10:55:50.26#ibcon#about to write, iclass 25, count 0 2006.257.10:55:50.26#ibcon#wrote, iclass 25, count 0 2006.257.10:55:50.26#ibcon#about to read 3, iclass 25, count 0 2006.257.10:55:50.30#ibcon#read 3, iclass 25, count 0 2006.257.10:55:50.30#ibcon#about to read 4, iclass 25, count 0 2006.257.10:55:50.30#ibcon#read 4, iclass 25, count 0 2006.257.10:55:50.30#ibcon#about to read 5, iclass 25, count 0 2006.257.10:55:50.30#ibcon#read 5, iclass 25, count 0 2006.257.10:55:50.30#ibcon#about to read 6, iclass 25, count 0 2006.257.10:55:50.30#ibcon#read 6, iclass 25, count 0 2006.257.10:55:50.30#ibcon#end of sib2, iclass 25, count 0 2006.257.10:55:50.30#ibcon#*after write, iclass 25, count 0 2006.257.10:55:50.30#ibcon#*before return 0, iclass 25, count 0 2006.257.10:55:50.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:50.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.10:55:50.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.10:55:50.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.10:55:50.30$vck44/vb=8,4 2006.257.10:55:50.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.10:55:50.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.10:55:50.30#ibcon#ireg 11 cls_cnt 2 2006.257.10:55:50.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:50.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:50.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:50.36#ibcon#enter wrdev, iclass 27, count 2 2006.257.10:55:50.36#ibcon#first serial, iclass 27, count 2 2006.257.10:55:50.36#ibcon#enter sib2, iclass 27, count 2 2006.257.10:55:50.36#ibcon#flushed, iclass 27, count 2 2006.257.10:55:50.36#ibcon#about to write, iclass 27, count 2 2006.257.10:55:50.36#ibcon#wrote, iclass 27, count 2 2006.257.10:55:50.36#ibcon#about to read 3, iclass 27, count 2 2006.257.10:55:50.38#ibcon#read 3, iclass 27, count 2 2006.257.10:55:50.38#ibcon#about to read 4, iclass 27, count 2 2006.257.10:55:50.38#ibcon#read 4, iclass 27, count 2 2006.257.10:55:50.38#ibcon#about to read 5, iclass 27, count 2 2006.257.10:55:50.38#ibcon#read 5, iclass 27, count 2 2006.257.10:55:50.38#ibcon#about to read 6, iclass 27, count 2 2006.257.10:55:50.38#ibcon#read 6, iclass 27, count 2 2006.257.10:55:50.38#ibcon#end of sib2, iclass 27, count 2 2006.257.10:55:50.38#ibcon#*mode == 0, iclass 27, count 2 2006.257.10:55:50.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.10:55:50.38#ibcon#[27=AT08-04\r\n] 2006.257.10:55:50.38#ibcon#*before write, iclass 27, count 2 2006.257.10:55:50.38#ibcon#enter sib2, iclass 27, count 2 2006.257.10:55:50.38#ibcon#flushed, iclass 27, count 2 2006.257.10:55:50.38#ibcon#about to write, iclass 27, count 2 2006.257.10:55:50.38#ibcon#wrote, iclass 27, count 2 2006.257.10:55:50.38#ibcon#about to read 3, iclass 27, count 2 2006.257.10:55:50.41#ibcon#read 3, iclass 27, count 2 2006.257.10:55:50.41#ibcon#about to read 4, iclass 27, count 2 2006.257.10:55:50.41#ibcon#read 4, iclass 27, count 2 2006.257.10:55:50.41#ibcon#about to read 5, iclass 27, count 2 2006.257.10:55:50.41#ibcon#read 5, iclass 27, count 2 2006.257.10:55:50.41#ibcon#about to read 6, iclass 27, count 2 2006.257.10:55:50.41#ibcon#read 6, iclass 27, count 2 2006.257.10:55:50.41#ibcon#end of sib2, iclass 27, count 2 2006.257.10:55:50.41#ibcon#*after write, iclass 27, count 2 2006.257.10:55:50.41#ibcon#*before return 0, iclass 27, count 2 2006.257.10:55:50.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:50.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.10:55:50.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.10:55:50.41#ibcon#ireg 7 cls_cnt 0 2006.257.10:55:50.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:50.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:50.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:50.53#ibcon#enter wrdev, iclass 27, count 0 2006.257.10:55:50.53#ibcon#first serial, iclass 27, count 0 2006.257.10:55:50.53#ibcon#enter sib2, iclass 27, count 0 2006.257.10:55:50.53#ibcon#flushed, iclass 27, count 0 2006.257.10:55:50.53#ibcon#about to write, iclass 27, count 0 2006.257.10:55:50.53#ibcon#wrote, iclass 27, count 0 2006.257.10:55:50.53#ibcon#about to read 3, iclass 27, count 0 2006.257.10:55:50.55#ibcon#read 3, iclass 27, count 0 2006.257.10:55:50.55#ibcon#about to read 4, iclass 27, count 0 2006.257.10:55:50.55#ibcon#read 4, iclass 27, count 0 2006.257.10:55:50.55#ibcon#about to read 5, iclass 27, count 0 2006.257.10:55:50.55#ibcon#read 5, iclass 27, count 0 2006.257.10:55:50.55#ibcon#about to read 6, iclass 27, count 0 2006.257.10:55:50.55#ibcon#read 6, iclass 27, count 0 2006.257.10:55:50.55#ibcon#end of sib2, iclass 27, count 0 2006.257.10:55:50.55#ibcon#*mode == 0, iclass 27, count 0 2006.257.10:55:50.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.10:55:50.55#ibcon#[27=USB\r\n] 2006.257.10:55:50.55#ibcon#*before write, iclass 27, count 0 2006.257.10:55:50.55#ibcon#enter sib2, iclass 27, count 0 2006.257.10:55:50.55#ibcon#flushed, iclass 27, count 0 2006.257.10:55:50.55#ibcon#about to write, iclass 27, count 0 2006.257.10:55:50.55#ibcon#wrote, iclass 27, count 0 2006.257.10:55:50.55#ibcon#about to read 3, iclass 27, count 0 2006.257.10:55:50.58#ibcon#read 3, iclass 27, count 0 2006.257.10:55:50.58#ibcon#about to read 4, iclass 27, count 0 2006.257.10:55:50.58#ibcon#read 4, iclass 27, count 0 2006.257.10:55:50.58#ibcon#about to read 5, iclass 27, count 0 2006.257.10:55:50.58#ibcon#read 5, iclass 27, count 0 2006.257.10:55:50.58#ibcon#about to read 6, iclass 27, count 0 2006.257.10:55:50.58#ibcon#read 6, iclass 27, count 0 2006.257.10:55:50.58#ibcon#end of sib2, iclass 27, count 0 2006.257.10:55:50.58#ibcon#*after write, iclass 27, count 0 2006.257.10:55:50.58#ibcon#*before return 0, iclass 27, count 0 2006.257.10:55:50.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:50.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.10:55:50.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.10:55:50.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.10:55:50.58$vck44/vabw=wide 2006.257.10:55:50.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.10:55:50.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.10:55:50.58#ibcon#ireg 8 cls_cnt 0 2006.257.10:55:50.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:50.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:50.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:50.58#ibcon#enter wrdev, iclass 29, count 0 2006.257.10:55:50.58#ibcon#first serial, iclass 29, count 0 2006.257.10:55:50.58#ibcon#enter sib2, iclass 29, count 0 2006.257.10:55:50.58#ibcon#flushed, iclass 29, count 0 2006.257.10:55:50.58#ibcon#about to write, iclass 29, count 0 2006.257.10:55:50.58#ibcon#wrote, iclass 29, count 0 2006.257.10:55:50.58#ibcon#about to read 3, iclass 29, count 0 2006.257.10:55:50.60#ibcon#read 3, iclass 29, count 0 2006.257.10:55:50.60#ibcon#about to read 4, iclass 29, count 0 2006.257.10:55:50.60#ibcon#read 4, iclass 29, count 0 2006.257.10:55:50.60#ibcon#about to read 5, iclass 29, count 0 2006.257.10:55:50.60#ibcon#read 5, iclass 29, count 0 2006.257.10:55:50.60#ibcon#about to read 6, iclass 29, count 0 2006.257.10:55:50.60#ibcon#read 6, iclass 29, count 0 2006.257.10:55:50.60#ibcon#end of sib2, iclass 29, count 0 2006.257.10:55:50.60#ibcon#*mode == 0, iclass 29, count 0 2006.257.10:55:50.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.10:55:50.60#ibcon#[25=BW32\r\n] 2006.257.10:55:50.60#ibcon#*before write, iclass 29, count 0 2006.257.10:55:50.60#ibcon#enter sib2, iclass 29, count 0 2006.257.10:55:50.60#ibcon#flushed, iclass 29, count 0 2006.257.10:55:50.60#ibcon#about to write, iclass 29, count 0 2006.257.10:55:50.60#ibcon#wrote, iclass 29, count 0 2006.257.10:55:50.60#ibcon#about to read 3, iclass 29, count 0 2006.257.10:55:50.63#ibcon#read 3, iclass 29, count 0 2006.257.10:55:50.63#ibcon#about to read 4, iclass 29, count 0 2006.257.10:55:50.63#ibcon#read 4, iclass 29, count 0 2006.257.10:55:50.63#ibcon#about to read 5, iclass 29, count 0 2006.257.10:55:50.63#ibcon#read 5, iclass 29, count 0 2006.257.10:55:50.63#ibcon#about to read 6, iclass 29, count 0 2006.257.10:55:50.63#ibcon#read 6, iclass 29, count 0 2006.257.10:55:50.63#ibcon#end of sib2, iclass 29, count 0 2006.257.10:55:50.63#ibcon#*after write, iclass 29, count 0 2006.257.10:55:50.63#ibcon#*before return 0, iclass 29, count 0 2006.257.10:55:50.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:50.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.10:55:50.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.10:55:50.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.10:55:50.63$vck44/vbbw=wide 2006.257.10:55:50.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.10:55:50.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.10:55:50.63#ibcon#ireg 8 cls_cnt 0 2006.257.10:55:50.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:55:50.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:55:50.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:55:50.70#ibcon#enter wrdev, iclass 31, count 0 2006.257.10:55:50.70#ibcon#first serial, iclass 31, count 0 2006.257.10:55:50.70#ibcon#enter sib2, iclass 31, count 0 2006.257.10:55:50.70#ibcon#flushed, iclass 31, count 0 2006.257.10:55:50.70#ibcon#about to write, iclass 31, count 0 2006.257.10:55:50.70#ibcon#wrote, iclass 31, count 0 2006.257.10:55:50.70#ibcon#about to read 3, iclass 31, count 0 2006.257.10:55:50.72#ibcon#read 3, iclass 31, count 0 2006.257.10:55:50.72#ibcon#about to read 4, iclass 31, count 0 2006.257.10:55:50.72#ibcon#read 4, iclass 31, count 0 2006.257.10:55:50.72#ibcon#about to read 5, iclass 31, count 0 2006.257.10:55:50.72#ibcon#read 5, iclass 31, count 0 2006.257.10:55:50.72#ibcon#about to read 6, iclass 31, count 0 2006.257.10:55:50.72#ibcon#read 6, iclass 31, count 0 2006.257.10:55:50.72#ibcon#end of sib2, iclass 31, count 0 2006.257.10:55:50.72#ibcon#*mode == 0, iclass 31, count 0 2006.257.10:55:50.72#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.10:55:50.72#ibcon#[27=BW32\r\n] 2006.257.10:55:50.72#ibcon#*before write, iclass 31, count 0 2006.257.10:55:50.72#ibcon#enter sib2, iclass 31, count 0 2006.257.10:55:50.72#ibcon#flushed, iclass 31, count 0 2006.257.10:55:50.72#ibcon#about to write, iclass 31, count 0 2006.257.10:55:50.72#ibcon#wrote, iclass 31, count 0 2006.257.10:55:50.72#ibcon#about to read 3, iclass 31, count 0 2006.257.10:55:50.75#ibcon#read 3, iclass 31, count 0 2006.257.10:55:50.75#ibcon#about to read 4, iclass 31, count 0 2006.257.10:55:50.75#ibcon#read 4, iclass 31, count 0 2006.257.10:55:50.75#ibcon#about to read 5, iclass 31, count 0 2006.257.10:55:50.75#ibcon#read 5, iclass 31, count 0 2006.257.10:55:50.75#ibcon#about to read 6, iclass 31, count 0 2006.257.10:55:50.75#ibcon#read 6, iclass 31, count 0 2006.257.10:55:50.75#ibcon#end of sib2, iclass 31, count 0 2006.257.10:55:50.75#ibcon#*after write, iclass 31, count 0 2006.257.10:55:50.75#ibcon#*before return 0, iclass 31, count 0 2006.257.10:55:50.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:55:50.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.10:55:50.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.10:55:50.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.10:55:50.75$setupk4/ifdk4 2006.257.10:55:50.75$ifdk4/lo= 2006.257.10:55:50.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.10:55:50.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.10:55:50.75$ifdk4/patch= 2006.257.10:55:50.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.10:55:50.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.10:55:50.76$setupk4/!*+20s 2006.257.10:55:52.77#abcon#<5=/14 1.6 4.3 18.68 961014.0\r\n> 2006.257.10:55:52.79#abcon#{5=INTERFACE CLEAR} 2006.257.10:55:52.85#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:56:03.03#abcon#<5=/14 1.6 4.3 18.68 961014.1\r\n> 2006.257.10:56:03.05#abcon#{5=INTERFACE CLEAR} 2006.257.10:56:03.11#abcon#[5=S1D000X0/0*\r\n] 2006.257.10:56:05.25$setupk4/"tpicd 2006.257.10:56:05.25$setupk4/echo=off 2006.257.10:56:05.25$setupk4/xlog=off 2006.257.10:56:05.25:!2006.257.11:01:55 2006.257.10:56:49.13#trakl#Source acquired 2006.257.10:56:50.13#flagr#flagr/antenna,acquired 2006.257.11:01:55.00:preob 2006.257.11:01:55.14/onsource/TRACKING 2006.257.11:01:55.14:!2006.257.11:02:05 2006.257.11:02:05.00:"tape 2006.257.11:02:05.00:"st=record 2006.257.11:02:05.00:data_valid=on 2006.257.11:02:05.00:midob 2006.257.11:02:05.14/onsource/TRACKING 2006.257.11:02:05.14/wx/18.61,1014.2,96 2006.257.11:02:05.20/cable/+6.4794E-03 2006.257.11:02:06.29/va/01,08,usb,yes,30,33 2006.257.11:02:06.29/va/02,07,usb,yes,33,33 2006.257.11:02:06.29/va/03,08,usb,yes,29,31 2006.257.11:02:06.29/va/04,07,usb,yes,34,35 2006.257.11:02:06.29/va/05,04,usb,yes,30,31 2006.257.11:02:06.29/va/06,04,usb,yes,34,33 2006.257.11:02:06.29/va/07,04,usb,yes,35,35 2006.257.11:02:06.29/va/08,04,usb,yes,29,35 2006.257.11:02:06.52/valo/01,524.99,yes,locked 2006.257.11:02:06.52/valo/02,534.99,yes,locked 2006.257.11:02:06.52/valo/03,564.99,yes,locked 2006.257.11:02:06.52/valo/04,624.99,yes,locked 2006.257.11:02:06.52/valo/05,734.99,yes,locked 2006.257.11:02:06.52/valo/06,814.99,yes,locked 2006.257.11:02:06.52/valo/07,864.99,yes,locked 2006.257.11:02:06.52/valo/08,884.99,yes,locked 2006.257.11:02:07.61/vb/01,04,usb,yes,31,29 2006.257.11:02:07.61/vb/02,05,usb,yes,29,29 2006.257.11:02:07.61/vb/03,04,usb,yes,30,33 2006.257.11:02:07.61/vb/04,05,usb,yes,30,29 2006.257.11:02:07.61/vb/05,04,usb,yes,27,29 2006.257.11:02:07.61/vb/06,04,usb,yes,31,27 2006.257.11:02:07.61/vb/07,04,usb,yes,31,31 2006.257.11:02:07.61/vb/08,04,usb,yes,28,32 2006.257.11:02:07.84/vblo/01,629.99,yes,locked 2006.257.11:02:07.84/vblo/02,634.99,yes,locked 2006.257.11:02:07.84/vblo/03,649.99,yes,locked 2006.257.11:02:07.84/vblo/04,679.99,yes,locked 2006.257.11:02:07.84/vblo/05,709.99,yes,locked 2006.257.11:02:07.84/vblo/06,719.99,yes,locked 2006.257.11:02:07.84/vblo/07,734.99,yes,locked 2006.257.11:02:07.84/vblo/08,744.99,yes,locked 2006.257.11:02:07.99/vabw/8 2006.257.11:02:08.14/vbbw/8 2006.257.11:02:08.32/xfe/off,on,15.2 2006.257.11:02:08.69/ifatt/23,28,28,28 2006.257.11:02:09.07/fmout-gps/S +4.62E-07 2006.257.11:02:09.11:!2006.257.11:02:55 2006.257.11:02:55.01:data_valid=off 2006.257.11:02:55.02:"et 2006.257.11:02:55.02:!+3s 2006.257.11:02:58.03:"tape 2006.257.11:02:58.04:postob 2006.257.11:02:58.16/cable/+6.4784E-03 2006.257.11:02:58.17/wx/18.60,1014.2,96 2006.257.11:02:58.22/fmout-gps/S +4.61E-07 2006.257.11:02:58.23:scan_name=257-1106,jd0609,80 2006.257.11:02:58.23:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.11:02:59.14#flagr#flagr/antenna,new-source 2006.257.11:02:59.15:checkk5 2006.257.11:02:59.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:02:59.98/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:03:00.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:03:00.80/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:03:01.19/chk_obsdata//k5ts1/T2571102??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.11:03:01.61/chk_obsdata//k5ts2/T2571102??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.11:03:02.02/chk_obsdata//k5ts3/T2571102??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.11:03:02.43/chk_obsdata//k5ts4/T2571102??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.11:03:03.16/k5log//k5ts1_log_newline 2006.257.11:03:03.86/k5log//k5ts2_log_newline 2006.257.11:03:04.60/k5log//k5ts3_log_newline 2006.257.11:03:05.32/k5log//k5ts4_log_newline 2006.257.11:03:05.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:03:05.34:setupk4=1 2006.257.11:03:05.34$setupk4/echo=on 2006.257.11:03:05.34$setupk4/pcalon 2006.257.11:03:05.34$pcalon/"no phase cal control is implemented here 2006.257.11:03:05.35$setupk4/"tpicd=stop 2006.257.11:03:05.35$setupk4/"rec=synch_on 2006.257.11:03:05.35$setupk4/"rec_mode=128 2006.257.11:03:05.35$setupk4/!* 2006.257.11:03:05.35$setupk4/recpk4 2006.257.11:03:05.35$recpk4/recpatch= 2006.257.11:03:05.35$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:03:05.35$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:03:05.35$setupk4/vck44 2006.257.11:03:05.35$vck44/valo=1,524.99 2006.257.11:03:05.35#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.11:03:05.35#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.11:03:05.35#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:05.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:05.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:05.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:05.35#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:03:05.35#ibcon#first serial, iclass 23, count 0 2006.257.11:03:05.35#ibcon#enter sib2, iclass 23, count 0 2006.257.11:03:05.35#ibcon#flushed, iclass 23, count 0 2006.257.11:03:05.35#ibcon#about to write, iclass 23, count 0 2006.257.11:03:05.35#ibcon#wrote, iclass 23, count 0 2006.257.11:03:05.35#ibcon#about to read 3, iclass 23, count 0 2006.257.11:03:05.36#ibcon#read 3, iclass 23, count 0 2006.257.11:03:05.36#ibcon#about to read 4, iclass 23, count 0 2006.257.11:03:05.36#ibcon#read 4, iclass 23, count 0 2006.257.11:03:05.36#ibcon#about to read 5, iclass 23, count 0 2006.257.11:03:05.36#ibcon#read 5, iclass 23, count 0 2006.257.11:03:05.36#ibcon#about to read 6, iclass 23, count 0 2006.257.11:03:05.36#ibcon#read 6, iclass 23, count 0 2006.257.11:03:05.36#ibcon#end of sib2, iclass 23, count 0 2006.257.11:03:05.36#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:03:05.36#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:03:05.36#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:03:05.36#ibcon#*before write, iclass 23, count 0 2006.257.11:03:05.36#ibcon#enter sib2, iclass 23, count 0 2006.257.11:03:05.36#ibcon#flushed, iclass 23, count 0 2006.257.11:03:05.36#ibcon#about to write, iclass 23, count 0 2006.257.11:03:05.36#ibcon#wrote, iclass 23, count 0 2006.257.11:03:05.36#ibcon#about to read 3, iclass 23, count 0 2006.257.11:03:05.41#ibcon#read 3, iclass 23, count 0 2006.257.11:03:05.41#ibcon#about to read 4, iclass 23, count 0 2006.257.11:03:05.41#ibcon#read 4, iclass 23, count 0 2006.257.11:03:05.41#ibcon#about to read 5, iclass 23, count 0 2006.257.11:03:05.41#ibcon#read 5, iclass 23, count 0 2006.257.11:03:05.41#ibcon#about to read 6, iclass 23, count 0 2006.257.11:03:05.41#ibcon#read 6, iclass 23, count 0 2006.257.11:03:05.41#ibcon#end of sib2, iclass 23, count 0 2006.257.11:03:05.41#ibcon#*after write, iclass 23, count 0 2006.257.11:03:05.41#ibcon#*before return 0, iclass 23, count 0 2006.257.11:03:05.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:05.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:05.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:03:05.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:03:05.41$vck44/va=1,8 2006.257.11:03:05.41#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.11:03:05.41#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.11:03:05.41#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:05.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:05.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:05.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:05.41#ibcon#enter wrdev, iclass 25, count 2 2006.257.11:03:05.41#ibcon#first serial, iclass 25, count 2 2006.257.11:03:05.41#ibcon#enter sib2, iclass 25, count 2 2006.257.11:03:05.41#ibcon#flushed, iclass 25, count 2 2006.257.11:03:05.41#ibcon#about to write, iclass 25, count 2 2006.257.11:03:05.41#ibcon#wrote, iclass 25, count 2 2006.257.11:03:05.41#ibcon#about to read 3, iclass 25, count 2 2006.257.11:03:05.43#ibcon#read 3, iclass 25, count 2 2006.257.11:03:05.43#ibcon#about to read 4, iclass 25, count 2 2006.257.11:03:05.43#ibcon#read 4, iclass 25, count 2 2006.257.11:03:05.43#ibcon#about to read 5, iclass 25, count 2 2006.257.11:03:05.43#ibcon#read 5, iclass 25, count 2 2006.257.11:03:05.43#ibcon#about to read 6, iclass 25, count 2 2006.257.11:03:05.43#ibcon#read 6, iclass 25, count 2 2006.257.11:03:05.43#ibcon#end of sib2, iclass 25, count 2 2006.257.11:03:05.43#ibcon#*mode == 0, iclass 25, count 2 2006.257.11:03:05.43#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.11:03:05.43#ibcon#[25=AT01-08\r\n] 2006.257.11:03:05.43#ibcon#*before write, iclass 25, count 2 2006.257.11:03:05.43#ibcon#enter sib2, iclass 25, count 2 2006.257.11:03:05.43#ibcon#flushed, iclass 25, count 2 2006.257.11:03:05.43#ibcon#about to write, iclass 25, count 2 2006.257.11:03:05.43#ibcon#wrote, iclass 25, count 2 2006.257.11:03:05.43#ibcon#about to read 3, iclass 25, count 2 2006.257.11:03:05.46#ibcon#read 3, iclass 25, count 2 2006.257.11:03:05.46#ibcon#about to read 4, iclass 25, count 2 2006.257.11:03:05.46#ibcon#read 4, iclass 25, count 2 2006.257.11:03:05.46#ibcon#about to read 5, iclass 25, count 2 2006.257.11:03:05.46#ibcon#read 5, iclass 25, count 2 2006.257.11:03:05.46#ibcon#about to read 6, iclass 25, count 2 2006.257.11:03:05.46#ibcon#read 6, iclass 25, count 2 2006.257.11:03:05.46#ibcon#end of sib2, iclass 25, count 2 2006.257.11:03:05.46#ibcon#*after write, iclass 25, count 2 2006.257.11:03:05.46#ibcon#*before return 0, iclass 25, count 2 2006.257.11:03:05.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:05.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:05.46#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.11:03:05.46#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:05.46#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:05.58#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:05.58#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:05.58#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:03:05.58#ibcon#first serial, iclass 25, count 0 2006.257.11:03:05.58#ibcon#enter sib2, iclass 25, count 0 2006.257.11:03:05.58#ibcon#flushed, iclass 25, count 0 2006.257.11:03:05.58#ibcon#about to write, iclass 25, count 0 2006.257.11:03:05.58#ibcon#wrote, iclass 25, count 0 2006.257.11:03:05.58#ibcon#about to read 3, iclass 25, count 0 2006.257.11:03:05.60#ibcon#read 3, iclass 25, count 0 2006.257.11:03:05.60#ibcon#about to read 4, iclass 25, count 0 2006.257.11:03:05.60#ibcon#read 4, iclass 25, count 0 2006.257.11:03:05.60#ibcon#about to read 5, iclass 25, count 0 2006.257.11:03:05.60#ibcon#read 5, iclass 25, count 0 2006.257.11:03:05.60#ibcon#about to read 6, iclass 25, count 0 2006.257.11:03:05.60#ibcon#read 6, iclass 25, count 0 2006.257.11:03:05.60#ibcon#end of sib2, iclass 25, count 0 2006.257.11:03:05.60#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:03:05.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:03:05.60#ibcon#[25=USB\r\n] 2006.257.11:03:05.60#ibcon#*before write, iclass 25, count 0 2006.257.11:03:05.60#ibcon#enter sib2, iclass 25, count 0 2006.257.11:03:05.60#ibcon#flushed, iclass 25, count 0 2006.257.11:03:05.60#ibcon#about to write, iclass 25, count 0 2006.257.11:03:05.60#ibcon#wrote, iclass 25, count 0 2006.257.11:03:05.60#ibcon#about to read 3, iclass 25, count 0 2006.257.11:03:05.63#ibcon#read 3, iclass 25, count 0 2006.257.11:03:05.63#ibcon#about to read 4, iclass 25, count 0 2006.257.11:03:05.63#ibcon#read 4, iclass 25, count 0 2006.257.11:03:05.63#ibcon#about to read 5, iclass 25, count 0 2006.257.11:03:05.63#ibcon#read 5, iclass 25, count 0 2006.257.11:03:05.63#ibcon#about to read 6, iclass 25, count 0 2006.257.11:03:05.63#ibcon#read 6, iclass 25, count 0 2006.257.11:03:05.63#ibcon#end of sib2, iclass 25, count 0 2006.257.11:03:05.63#ibcon#*after write, iclass 25, count 0 2006.257.11:03:05.63#ibcon#*before return 0, iclass 25, count 0 2006.257.11:03:05.63#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:05.63#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:05.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:03:05.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:03:05.63$vck44/valo=2,534.99 2006.257.11:03:05.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.11:03:05.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.11:03:05.63#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:05.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:05.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:05.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:05.63#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:03:05.63#ibcon#first serial, iclass 27, count 0 2006.257.11:03:05.63#ibcon#enter sib2, iclass 27, count 0 2006.257.11:03:05.63#ibcon#flushed, iclass 27, count 0 2006.257.11:03:05.63#ibcon#about to write, iclass 27, count 0 2006.257.11:03:05.63#ibcon#wrote, iclass 27, count 0 2006.257.11:03:05.63#ibcon#about to read 3, iclass 27, count 0 2006.257.11:03:05.65#ibcon#read 3, iclass 27, count 0 2006.257.11:03:05.65#ibcon#about to read 4, iclass 27, count 0 2006.257.11:03:05.65#ibcon#read 4, iclass 27, count 0 2006.257.11:03:05.65#ibcon#about to read 5, iclass 27, count 0 2006.257.11:03:05.65#ibcon#read 5, iclass 27, count 0 2006.257.11:03:05.65#ibcon#about to read 6, iclass 27, count 0 2006.257.11:03:05.65#ibcon#read 6, iclass 27, count 0 2006.257.11:03:05.65#ibcon#end of sib2, iclass 27, count 0 2006.257.11:03:05.65#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:03:05.65#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:03:05.65#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:03:05.65#ibcon#*before write, iclass 27, count 0 2006.257.11:03:05.65#ibcon#enter sib2, iclass 27, count 0 2006.257.11:03:05.65#ibcon#flushed, iclass 27, count 0 2006.257.11:03:05.65#ibcon#about to write, iclass 27, count 0 2006.257.11:03:05.65#ibcon#wrote, iclass 27, count 0 2006.257.11:03:05.65#ibcon#about to read 3, iclass 27, count 0 2006.257.11:03:05.69#ibcon#read 3, iclass 27, count 0 2006.257.11:03:05.69#ibcon#about to read 4, iclass 27, count 0 2006.257.11:03:05.69#ibcon#read 4, iclass 27, count 0 2006.257.11:03:05.69#ibcon#about to read 5, iclass 27, count 0 2006.257.11:03:05.69#ibcon#read 5, iclass 27, count 0 2006.257.11:03:05.69#ibcon#about to read 6, iclass 27, count 0 2006.257.11:03:05.69#ibcon#read 6, iclass 27, count 0 2006.257.11:03:05.69#ibcon#end of sib2, iclass 27, count 0 2006.257.11:03:05.69#ibcon#*after write, iclass 27, count 0 2006.257.11:03:05.69#ibcon#*before return 0, iclass 27, count 0 2006.257.11:03:05.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:05.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:05.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:03:05.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:03:05.69$vck44/va=2,7 2006.257.11:03:05.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.11:03:05.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.11:03:05.69#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:05.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:05.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:05.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:05.75#ibcon#enter wrdev, iclass 29, count 2 2006.257.11:03:05.75#ibcon#first serial, iclass 29, count 2 2006.257.11:03:05.75#ibcon#enter sib2, iclass 29, count 2 2006.257.11:03:05.75#ibcon#flushed, iclass 29, count 2 2006.257.11:03:05.75#ibcon#about to write, iclass 29, count 2 2006.257.11:03:05.75#ibcon#wrote, iclass 29, count 2 2006.257.11:03:05.75#ibcon#about to read 3, iclass 29, count 2 2006.257.11:03:05.77#ibcon#read 3, iclass 29, count 2 2006.257.11:03:05.77#ibcon#about to read 4, iclass 29, count 2 2006.257.11:03:05.77#ibcon#read 4, iclass 29, count 2 2006.257.11:03:05.77#ibcon#about to read 5, iclass 29, count 2 2006.257.11:03:05.77#ibcon#read 5, iclass 29, count 2 2006.257.11:03:05.77#ibcon#about to read 6, iclass 29, count 2 2006.257.11:03:05.77#ibcon#read 6, iclass 29, count 2 2006.257.11:03:05.77#ibcon#end of sib2, iclass 29, count 2 2006.257.11:03:05.77#ibcon#*mode == 0, iclass 29, count 2 2006.257.11:03:05.77#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.11:03:05.77#ibcon#[25=AT02-07\r\n] 2006.257.11:03:05.77#ibcon#*before write, iclass 29, count 2 2006.257.11:03:05.77#ibcon#enter sib2, iclass 29, count 2 2006.257.11:03:05.77#ibcon#flushed, iclass 29, count 2 2006.257.11:03:05.77#ibcon#about to write, iclass 29, count 2 2006.257.11:03:05.77#ibcon#wrote, iclass 29, count 2 2006.257.11:03:05.77#ibcon#about to read 3, iclass 29, count 2 2006.257.11:03:05.80#ibcon#read 3, iclass 29, count 2 2006.257.11:03:05.80#ibcon#about to read 4, iclass 29, count 2 2006.257.11:03:05.80#ibcon#read 4, iclass 29, count 2 2006.257.11:03:05.80#ibcon#about to read 5, iclass 29, count 2 2006.257.11:03:05.80#ibcon#read 5, iclass 29, count 2 2006.257.11:03:05.80#ibcon#about to read 6, iclass 29, count 2 2006.257.11:03:05.80#ibcon#read 6, iclass 29, count 2 2006.257.11:03:05.80#ibcon#end of sib2, iclass 29, count 2 2006.257.11:03:05.80#ibcon#*after write, iclass 29, count 2 2006.257.11:03:05.80#ibcon#*before return 0, iclass 29, count 2 2006.257.11:03:05.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:05.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:05.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.11:03:05.80#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:05.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:05.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:05.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:05.92#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:03:05.92#ibcon#first serial, iclass 29, count 0 2006.257.11:03:05.92#ibcon#enter sib2, iclass 29, count 0 2006.257.11:03:05.92#ibcon#flushed, iclass 29, count 0 2006.257.11:03:05.92#ibcon#about to write, iclass 29, count 0 2006.257.11:03:05.92#ibcon#wrote, iclass 29, count 0 2006.257.11:03:05.92#ibcon#about to read 3, iclass 29, count 0 2006.257.11:03:05.94#ibcon#read 3, iclass 29, count 0 2006.257.11:03:05.94#ibcon#about to read 4, iclass 29, count 0 2006.257.11:03:05.94#ibcon#read 4, iclass 29, count 0 2006.257.11:03:05.94#ibcon#about to read 5, iclass 29, count 0 2006.257.11:03:05.94#ibcon#read 5, iclass 29, count 0 2006.257.11:03:05.94#ibcon#about to read 6, iclass 29, count 0 2006.257.11:03:05.94#ibcon#read 6, iclass 29, count 0 2006.257.11:03:05.94#ibcon#end of sib2, iclass 29, count 0 2006.257.11:03:05.94#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:03:05.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:03:05.94#ibcon#[25=USB\r\n] 2006.257.11:03:05.94#ibcon#*before write, iclass 29, count 0 2006.257.11:03:05.94#ibcon#enter sib2, iclass 29, count 0 2006.257.11:03:05.94#ibcon#flushed, iclass 29, count 0 2006.257.11:03:05.94#ibcon#about to write, iclass 29, count 0 2006.257.11:03:05.94#ibcon#wrote, iclass 29, count 0 2006.257.11:03:05.94#ibcon#about to read 3, iclass 29, count 0 2006.257.11:03:05.97#ibcon#read 3, iclass 29, count 0 2006.257.11:03:05.97#ibcon#about to read 4, iclass 29, count 0 2006.257.11:03:05.97#ibcon#read 4, iclass 29, count 0 2006.257.11:03:05.97#ibcon#about to read 5, iclass 29, count 0 2006.257.11:03:05.97#ibcon#read 5, iclass 29, count 0 2006.257.11:03:05.97#ibcon#about to read 6, iclass 29, count 0 2006.257.11:03:05.97#ibcon#read 6, iclass 29, count 0 2006.257.11:03:05.97#ibcon#end of sib2, iclass 29, count 0 2006.257.11:03:05.97#ibcon#*after write, iclass 29, count 0 2006.257.11:03:05.97#ibcon#*before return 0, iclass 29, count 0 2006.257.11:03:05.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:05.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:05.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:03:05.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:03:05.97$vck44/valo=3,564.99 2006.257.11:03:05.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.11:03:05.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.11:03:05.97#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:05.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:05.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:05.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:05.97#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:03:05.97#ibcon#first serial, iclass 31, count 0 2006.257.11:03:05.97#ibcon#enter sib2, iclass 31, count 0 2006.257.11:03:05.97#ibcon#flushed, iclass 31, count 0 2006.257.11:03:05.97#ibcon#about to write, iclass 31, count 0 2006.257.11:03:05.97#ibcon#wrote, iclass 31, count 0 2006.257.11:03:05.97#ibcon#about to read 3, iclass 31, count 0 2006.257.11:03:05.99#ibcon#read 3, iclass 31, count 0 2006.257.11:03:05.99#ibcon#about to read 4, iclass 31, count 0 2006.257.11:03:05.99#ibcon#read 4, iclass 31, count 0 2006.257.11:03:05.99#ibcon#about to read 5, iclass 31, count 0 2006.257.11:03:05.99#ibcon#read 5, iclass 31, count 0 2006.257.11:03:05.99#ibcon#about to read 6, iclass 31, count 0 2006.257.11:03:05.99#ibcon#read 6, iclass 31, count 0 2006.257.11:03:05.99#ibcon#end of sib2, iclass 31, count 0 2006.257.11:03:05.99#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:03:05.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:03:05.99#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:03:05.99#ibcon#*before write, iclass 31, count 0 2006.257.11:03:05.99#ibcon#enter sib2, iclass 31, count 0 2006.257.11:03:05.99#ibcon#flushed, iclass 31, count 0 2006.257.11:03:05.99#ibcon#about to write, iclass 31, count 0 2006.257.11:03:05.99#ibcon#wrote, iclass 31, count 0 2006.257.11:03:05.99#ibcon#about to read 3, iclass 31, count 0 2006.257.11:03:06.03#ibcon#read 3, iclass 31, count 0 2006.257.11:03:06.03#ibcon#about to read 4, iclass 31, count 0 2006.257.11:03:06.03#ibcon#read 4, iclass 31, count 0 2006.257.11:03:06.03#ibcon#about to read 5, iclass 31, count 0 2006.257.11:03:06.03#ibcon#read 5, iclass 31, count 0 2006.257.11:03:06.03#ibcon#about to read 6, iclass 31, count 0 2006.257.11:03:06.03#ibcon#read 6, iclass 31, count 0 2006.257.11:03:06.03#ibcon#end of sib2, iclass 31, count 0 2006.257.11:03:06.03#ibcon#*after write, iclass 31, count 0 2006.257.11:03:06.03#ibcon#*before return 0, iclass 31, count 0 2006.257.11:03:06.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:06.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:06.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:03:06.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:03:06.03$vck44/va=3,8 2006.257.11:03:06.03#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.11:03:06.03#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.11:03:06.03#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:06.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:06.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:06.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:06.09#ibcon#enter wrdev, iclass 33, count 2 2006.257.11:03:06.09#ibcon#first serial, iclass 33, count 2 2006.257.11:03:06.09#ibcon#enter sib2, iclass 33, count 2 2006.257.11:03:06.09#ibcon#flushed, iclass 33, count 2 2006.257.11:03:06.09#ibcon#about to write, iclass 33, count 2 2006.257.11:03:06.09#ibcon#wrote, iclass 33, count 2 2006.257.11:03:06.09#ibcon#about to read 3, iclass 33, count 2 2006.257.11:03:06.11#ibcon#read 3, iclass 33, count 2 2006.257.11:03:06.11#ibcon#about to read 4, iclass 33, count 2 2006.257.11:03:06.11#ibcon#read 4, iclass 33, count 2 2006.257.11:03:06.11#ibcon#about to read 5, iclass 33, count 2 2006.257.11:03:06.11#ibcon#read 5, iclass 33, count 2 2006.257.11:03:06.11#ibcon#about to read 6, iclass 33, count 2 2006.257.11:03:06.11#ibcon#read 6, iclass 33, count 2 2006.257.11:03:06.11#ibcon#end of sib2, iclass 33, count 2 2006.257.11:03:06.11#ibcon#*mode == 0, iclass 33, count 2 2006.257.11:03:06.11#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.11:03:06.11#ibcon#[25=AT03-08\r\n] 2006.257.11:03:06.11#ibcon#*before write, iclass 33, count 2 2006.257.11:03:06.11#ibcon#enter sib2, iclass 33, count 2 2006.257.11:03:06.11#ibcon#flushed, iclass 33, count 2 2006.257.11:03:06.11#ibcon#about to write, iclass 33, count 2 2006.257.11:03:06.11#ibcon#wrote, iclass 33, count 2 2006.257.11:03:06.11#ibcon#about to read 3, iclass 33, count 2 2006.257.11:03:06.14#ibcon#read 3, iclass 33, count 2 2006.257.11:03:06.14#ibcon#about to read 4, iclass 33, count 2 2006.257.11:03:06.14#ibcon#read 4, iclass 33, count 2 2006.257.11:03:06.14#ibcon#about to read 5, iclass 33, count 2 2006.257.11:03:06.14#ibcon#read 5, iclass 33, count 2 2006.257.11:03:06.14#ibcon#about to read 6, iclass 33, count 2 2006.257.11:03:06.14#ibcon#read 6, iclass 33, count 2 2006.257.11:03:06.14#ibcon#end of sib2, iclass 33, count 2 2006.257.11:03:06.14#ibcon#*after write, iclass 33, count 2 2006.257.11:03:06.14#ibcon#*before return 0, iclass 33, count 2 2006.257.11:03:06.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:06.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:06.14#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.11:03:06.14#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:06.14#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:06.26#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:06.26#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:06.26#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:03:06.26#ibcon#first serial, iclass 33, count 0 2006.257.11:03:06.26#ibcon#enter sib2, iclass 33, count 0 2006.257.11:03:06.26#ibcon#flushed, iclass 33, count 0 2006.257.11:03:06.26#ibcon#about to write, iclass 33, count 0 2006.257.11:03:06.26#ibcon#wrote, iclass 33, count 0 2006.257.11:03:06.26#ibcon#about to read 3, iclass 33, count 0 2006.257.11:03:06.28#ibcon#read 3, iclass 33, count 0 2006.257.11:03:06.28#ibcon#about to read 4, iclass 33, count 0 2006.257.11:03:06.28#ibcon#read 4, iclass 33, count 0 2006.257.11:03:06.28#ibcon#about to read 5, iclass 33, count 0 2006.257.11:03:06.28#ibcon#read 5, iclass 33, count 0 2006.257.11:03:06.28#ibcon#about to read 6, iclass 33, count 0 2006.257.11:03:06.28#ibcon#read 6, iclass 33, count 0 2006.257.11:03:06.28#ibcon#end of sib2, iclass 33, count 0 2006.257.11:03:06.28#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:03:06.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:03:06.28#ibcon#[25=USB\r\n] 2006.257.11:03:06.28#ibcon#*before write, iclass 33, count 0 2006.257.11:03:06.28#ibcon#enter sib2, iclass 33, count 0 2006.257.11:03:06.28#ibcon#flushed, iclass 33, count 0 2006.257.11:03:06.28#ibcon#about to write, iclass 33, count 0 2006.257.11:03:06.28#ibcon#wrote, iclass 33, count 0 2006.257.11:03:06.28#ibcon#about to read 3, iclass 33, count 0 2006.257.11:03:06.31#ibcon#read 3, iclass 33, count 0 2006.257.11:03:06.31#ibcon#about to read 4, iclass 33, count 0 2006.257.11:03:06.31#ibcon#read 4, iclass 33, count 0 2006.257.11:03:06.31#ibcon#about to read 5, iclass 33, count 0 2006.257.11:03:06.31#ibcon#read 5, iclass 33, count 0 2006.257.11:03:06.31#ibcon#about to read 6, iclass 33, count 0 2006.257.11:03:06.31#ibcon#read 6, iclass 33, count 0 2006.257.11:03:06.31#ibcon#end of sib2, iclass 33, count 0 2006.257.11:03:06.31#ibcon#*after write, iclass 33, count 0 2006.257.11:03:06.31#ibcon#*before return 0, iclass 33, count 0 2006.257.11:03:06.31#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:06.31#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:06.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:03:06.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:03:06.31$vck44/valo=4,624.99 2006.257.11:03:06.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.11:03:06.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.11:03:06.31#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:06.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:06.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:06.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:06.31#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:03:06.31#ibcon#first serial, iclass 35, count 0 2006.257.11:03:06.31#ibcon#enter sib2, iclass 35, count 0 2006.257.11:03:06.31#ibcon#flushed, iclass 35, count 0 2006.257.11:03:06.31#ibcon#about to write, iclass 35, count 0 2006.257.11:03:06.31#ibcon#wrote, iclass 35, count 0 2006.257.11:03:06.31#ibcon#about to read 3, iclass 35, count 0 2006.257.11:03:06.33#ibcon#read 3, iclass 35, count 0 2006.257.11:03:06.33#ibcon#about to read 4, iclass 35, count 0 2006.257.11:03:06.33#ibcon#read 4, iclass 35, count 0 2006.257.11:03:06.33#ibcon#about to read 5, iclass 35, count 0 2006.257.11:03:06.33#ibcon#read 5, iclass 35, count 0 2006.257.11:03:06.33#ibcon#about to read 6, iclass 35, count 0 2006.257.11:03:06.33#ibcon#read 6, iclass 35, count 0 2006.257.11:03:06.33#ibcon#end of sib2, iclass 35, count 0 2006.257.11:03:06.33#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:03:06.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:03:06.33#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:03:06.33#ibcon#*before write, iclass 35, count 0 2006.257.11:03:06.33#ibcon#enter sib2, iclass 35, count 0 2006.257.11:03:06.33#ibcon#flushed, iclass 35, count 0 2006.257.11:03:06.33#ibcon#about to write, iclass 35, count 0 2006.257.11:03:06.33#ibcon#wrote, iclass 35, count 0 2006.257.11:03:06.33#ibcon#about to read 3, iclass 35, count 0 2006.257.11:03:06.37#ibcon#read 3, iclass 35, count 0 2006.257.11:03:06.37#ibcon#about to read 4, iclass 35, count 0 2006.257.11:03:06.37#ibcon#read 4, iclass 35, count 0 2006.257.11:03:06.37#ibcon#about to read 5, iclass 35, count 0 2006.257.11:03:06.37#ibcon#read 5, iclass 35, count 0 2006.257.11:03:06.37#ibcon#about to read 6, iclass 35, count 0 2006.257.11:03:06.37#ibcon#read 6, iclass 35, count 0 2006.257.11:03:06.37#ibcon#end of sib2, iclass 35, count 0 2006.257.11:03:06.37#ibcon#*after write, iclass 35, count 0 2006.257.11:03:06.37#ibcon#*before return 0, iclass 35, count 0 2006.257.11:03:06.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:06.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:06.37#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:03:06.37#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:03:06.37$vck44/va=4,7 2006.257.11:03:06.37#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.11:03:06.37#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.11:03:06.37#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:06.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:06.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:06.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:06.43#ibcon#enter wrdev, iclass 37, count 2 2006.257.11:03:06.43#ibcon#first serial, iclass 37, count 2 2006.257.11:03:06.43#ibcon#enter sib2, iclass 37, count 2 2006.257.11:03:06.43#ibcon#flushed, iclass 37, count 2 2006.257.11:03:06.43#ibcon#about to write, iclass 37, count 2 2006.257.11:03:06.43#ibcon#wrote, iclass 37, count 2 2006.257.11:03:06.43#ibcon#about to read 3, iclass 37, count 2 2006.257.11:03:06.45#ibcon#read 3, iclass 37, count 2 2006.257.11:03:06.45#ibcon#about to read 4, iclass 37, count 2 2006.257.11:03:06.45#ibcon#read 4, iclass 37, count 2 2006.257.11:03:06.45#ibcon#about to read 5, iclass 37, count 2 2006.257.11:03:06.45#ibcon#read 5, iclass 37, count 2 2006.257.11:03:06.45#ibcon#about to read 6, iclass 37, count 2 2006.257.11:03:06.45#ibcon#read 6, iclass 37, count 2 2006.257.11:03:06.45#ibcon#end of sib2, iclass 37, count 2 2006.257.11:03:06.45#ibcon#*mode == 0, iclass 37, count 2 2006.257.11:03:06.45#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.11:03:06.45#ibcon#[25=AT04-07\r\n] 2006.257.11:03:06.45#ibcon#*before write, iclass 37, count 2 2006.257.11:03:06.45#ibcon#enter sib2, iclass 37, count 2 2006.257.11:03:06.45#ibcon#flushed, iclass 37, count 2 2006.257.11:03:06.45#ibcon#about to write, iclass 37, count 2 2006.257.11:03:06.45#ibcon#wrote, iclass 37, count 2 2006.257.11:03:06.45#ibcon#about to read 3, iclass 37, count 2 2006.257.11:03:06.48#ibcon#read 3, iclass 37, count 2 2006.257.11:03:06.48#ibcon#about to read 4, iclass 37, count 2 2006.257.11:03:06.48#ibcon#read 4, iclass 37, count 2 2006.257.11:03:06.48#ibcon#about to read 5, iclass 37, count 2 2006.257.11:03:06.48#ibcon#read 5, iclass 37, count 2 2006.257.11:03:06.48#ibcon#about to read 6, iclass 37, count 2 2006.257.11:03:06.48#ibcon#read 6, iclass 37, count 2 2006.257.11:03:06.48#ibcon#end of sib2, iclass 37, count 2 2006.257.11:03:06.48#ibcon#*after write, iclass 37, count 2 2006.257.11:03:06.57#ibcon#*before return 0, iclass 37, count 2 2006.257.11:03:06.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:06.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:06.57#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.11:03:06.57#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:06.57#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:06.68#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:06.68#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:06.68#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:03:06.68#ibcon#first serial, iclass 37, count 0 2006.257.11:03:06.68#ibcon#enter sib2, iclass 37, count 0 2006.257.11:03:06.68#ibcon#flushed, iclass 37, count 0 2006.257.11:03:06.68#ibcon#about to write, iclass 37, count 0 2006.257.11:03:06.68#ibcon#wrote, iclass 37, count 0 2006.257.11:03:06.68#ibcon#about to read 3, iclass 37, count 0 2006.257.11:03:06.70#ibcon#read 3, iclass 37, count 0 2006.257.11:03:06.70#ibcon#about to read 4, iclass 37, count 0 2006.257.11:03:06.70#ibcon#read 4, iclass 37, count 0 2006.257.11:03:06.70#ibcon#about to read 5, iclass 37, count 0 2006.257.11:03:06.70#ibcon#read 5, iclass 37, count 0 2006.257.11:03:06.70#ibcon#about to read 6, iclass 37, count 0 2006.257.11:03:06.70#ibcon#read 6, iclass 37, count 0 2006.257.11:03:06.70#ibcon#end of sib2, iclass 37, count 0 2006.257.11:03:06.70#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:03:06.70#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:03:06.70#ibcon#[25=USB\r\n] 2006.257.11:03:06.70#ibcon#*before write, iclass 37, count 0 2006.257.11:03:06.70#ibcon#enter sib2, iclass 37, count 0 2006.257.11:03:06.70#ibcon#flushed, iclass 37, count 0 2006.257.11:03:06.70#ibcon#about to write, iclass 37, count 0 2006.257.11:03:06.70#ibcon#wrote, iclass 37, count 0 2006.257.11:03:06.70#ibcon#about to read 3, iclass 37, count 0 2006.257.11:03:06.73#ibcon#read 3, iclass 37, count 0 2006.257.11:03:06.73#ibcon#about to read 4, iclass 37, count 0 2006.257.11:03:06.73#ibcon#read 4, iclass 37, count 0 2006.257.11:03:06.73#ibcon#about to read 5, iclass 37, count 0 2006.257.11:03:06.73#ibcon#read 5, iclass 37, count 0 2006.257.11:03:06.73#ibcon#about to read 6, iclass 37, count 0 2006.257.11:03:06.73#ibcon#read 6, iclass 37, count 0 2006.257.11:03:06.73#ibcon#end of sib2, iclass 37, count 0 2006.257.11:03:06.73#ibcon#*after write, iclass 37, count 0 2006.257.11:03:06.73#ibcon#*before return 0, iclass 37, count 0 2006.257.11:03:06.73#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:06.73#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:06.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:03:06.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:03:06.73$vck44/valo=5,734.99 2006.257.11:03:06.73#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.11:03:06.73#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.11:03:06.73#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:06.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:06.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:06.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:06.73#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:03:06.73#ibcon#first serial, iclass 39, count 0 2006.257.11:03:06.73#ibcon#enter sib2, iclass 39, count 0 2006.257.11:03:06.73#ibcon#flushed, iclass 39, count 0 2006.257.11:03:06.73#ibcon#about to write, iclass 39, count 0 2006.257.11:03:06.73#ibcon#wrote, iclass 39, count 0 2006.257.11:03:06.73#ibcon#about to read 3, iclass 39, count 0 2006.257.11:03:06.75#ibcon#read 3, iclass 39, count 0 2006.257.11:03:06.75#ibcon#about to read 4, iclass 39, count 0 2006.257.11:03:06.75#ibcon#read 4, iclass 39, count 0 2006.257.11:03:06.75#ibcon#about to read 5, iclass 39, count 0 2006.257.11:03:06.75#ibcon#read 5, iclass 39, count 0 2006.257.11:03:06.75#ibcon#about to read 6, iclass 39, count 0 2006.257.11:03:06.75#ibcon#read 6, iclass 39, count 0 2006.257.11:03:06.75#ibcon#end of sib2, iclass 39, count 0 2006.257.11:03:06.75#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:03:06.75#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:03:06.75#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:03:06.75#ibcon#*before write, iclass 39, count 0 2006.257.11:03:06.75#ibcon#enter sib2, iclass 39, count 0 2006.257.11:03:06.75#ibcon#flushed, iclass 39, count 0 2006.257.11:03:06.75#ibcon#about to write, iclass 39, count 0 2006.257.11:03:06.75#ibcon#wrote, iclass 39, count 0 2006.257.11:03:06.75#ibcon#about to read 3, iclass 39, count 0 2006.257.11:03:06.79#ibcon#read 3, iclass 39, count 0 2006.257.11:03:06.79#ibcon#about to read 4, iclass 39, count 0 2006.257.11:03:06.79#ibcon#read 4, iclass 39, count 0 2006.257.11:03:06.79#ibcon#about to read 5, iclass 39, count 0 2006.257.11:03:06.79#ibcon#read 5, iclass 39, count 0 2006.257.11:03:06.79#ibcon#about to read 6, iclass 39, count 0 2006.257.11:03:06.79#ibcon#read 6, iclass 39, count 0 2006.257.11:03:06.79#ibcon#end of sib2, iclass 39, count 0 2006.257.11:03:06.79#ibcon#*after write, iclass 39, count 0 2006.257.11:03:06.79#ibcon#*before return 0, iclass 39, count 0 2006.257.11:03:06.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:06.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:06.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:03:06.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:03:06.79$vck44/va=5,4 2006.257.11:03:06.79#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.11:03:06.79#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.11:03:06.79#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:06.79#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:06.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:06.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:06.85#ibcon#enter wrdev, iclass 3, count 2 2006.257.11:03:06.85#ibcon#first serial, iclass 3, count 2 2006.257.11:03:06.85#ibcon#enter sib2, iclass 3, count 2 2006.257.11:03:06.85#ibcon#flushed, iclass 3, count 2 2006.257.11:03:06.85#ibcon#about to write, iclass 3, count 2 2006.257.11:03:06.85#ibcon#wrote, iclass 3, count 2 2006.257.11:03:06.85#ibcon#about to read 3, iclass 3, count 2 2006.257.11:03:06.87#ibcon#read 3, iclass 3, count 2 2006.257.11:03:06.87#ibcon#about to read 4, iclass 3, count 2 2006.257.11:03:06.87#ibcon#read 4, iclass 3, count 2 2006.257.11:03:06.87#ibcon#about to read 5, iclass 3, count 2 2006.257.11:03:06.87#ibcon#read 5, iclass 3, count 2 2006.257.11:03:06.87#ibcon#about to read 6, iclass 3, count 2 2006.257.11:03:06.87#ibcon#read 6, iclass 3, count 2 2006.257.11:03:06.87#ibcon#end of sib2, iclass 3, count 2 2006.257.11:03:06.87#ibcon#*mode == 0, iclass 3, count 2 2006.257.11:03:06.87#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.11:03:06.87#ibcon#[25=AT05-04\r\n] 2006.257.11:03:06.87#ibcon#*before write, iclass 3, count 2 2006.257.11:03:06.87#ibcon#enter sib2, iclass 3, count 2 2006.257.11:03:06.87#ibcon#flushed, iclass 3, count 2 2006.257.11:03:06.87#ibcon#about to write, iclass 3, count 2 2006.257.11:03:06.87#ibcon#wrote, iclass 3, count 2 2006.257.11:03:06.87#ibcon#about to read 3, iclass 3, count 2 2006.257.11:03:06.90#ibcon#read 3, iclass 3, count 2 2006.257.11:03:06.90#ibcon#about to read 4, iclass 3, count 2 2006.257.11:03:06.90#ibcon#read 4, iclass 3, count 2 2006.257.11:03:06.90#ibcon#about to read 5, iclass 3, count 2 2006.257.11:03:06.90#ibcon#read 5, iclass 3, count 2 2006.257.11:03:06.90#ibcon#about to read 6, iclass 3, count 2 2006.257.11:03:06.90#ibcon#read 6, iclass 3, count 2 2006.257.11:03:06.90#ibcon#end of sib2, iclass 3, count 2 2006.257.11:03:06.90#ibcon#*after write, iclass 3, count 2 2006.257.11:03:06.90#ibcon#*before return 0, iclass 3, count 2 2006.257.11:03:06.90#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:06.90#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:06.90#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.11:03:06.90#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:06.90#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:07.02#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:07.02#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:07.02#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:03:07.02#ibcon#first serial, iclass 3, count 0 2006.257.11:03:07.02#ibcon#enter sib2, iclass 3, count 0 2006.257.11:03:07.02#ibcon#flushed, iclass 3, count 0 2006.257.11:03:07.02#ibcon#about to write, iclass 3, count 0 2006.257.11:03:07.02#ibcon#wrote, iclass 3, count 0 2006.257.11:03:07.02#ibcon#about to read 3, iclass 3, count 0 2006.257.11:03:07.04#ibcon#read 3, iclass 3, count 0 2006.257.11:03:07.04#ibcon#about to read 4, iclass 3, count 0 2006.257.11:03:07.04#ibcon#read 4, iclass 3, count 0 2006.257.11:03:07.04#ibcon#about to read 5, iclass 3, count 0 2006.257.11:03:07.04#ibcon#read 5, iclass 3, count 0 2006.257.11:03:07.04#ibcon#about to read 6, iclass 3, count 0 2006.257.11:03:07.04#ibcon#read 6, iclass 3, count 0 2006.257.11:03:07.04#ibcon#end of sib2, iclass 3, count 0 2006.257.11:03:07.04#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:03:07.04#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:03:07.04#ibcon#[25=USB\r\n] 2006.257.11:03:07.04#ibcon#*before write, iclass 3, count 0 2006.257.11:03:07.04#ibcon#enter sib2, iclass 3, count 0 2006.257.11:03:07.04#ibcon#flushed, iclass 3, count 0 2006.257.11:03:07.04#ibcon#about to write, iclass 3, count 0 2006.257.11:03:07.04#ibcon#wrote, iclass 3, count 0 2006.257.11:03:07.04#ibcon#about to read 3, iclass 3, count 0 2006.257.11:03:07.07#ibcon#read 3, iclass 3, count 0 2006.257.11:03:07.07#ibcon#about to read 4, iclass 3, count 0 2006.257.11:03:07.07#ibcon#read 4, iclass 3, count 0 2006.257.11:03:07.07#ibcon#about to read 5, iclass 3, count 0 2006.257.11:03:07.07#ibcon#read 5, iclass 3, count 0 2006.257.11:03:07.07#ibcon#about to read 6, iclass 3, count 0 2006.257.11:03:07.07#ibcon#read 6, iclass 3, count 0 2006.257.11:03:07.07#ibcon#end of sib2, iclass 3, count 0 2006.257.11:03:07.07#ibcon#*after write, iclass 3, count 0 2006.257.11:03:07.07#ibcon#*before return 0, iclass 3, count 0 2006.257.11:03:07.07#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:07.07#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:07.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:03:07.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:03:07.07$vck44/valo=6,814.99 2006.257.11:03:07.07#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.11:03:07.07#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.11:03:07.07#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:07.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:07.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:07.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:07.07#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:03:07.07#ibcon#first serial, iclass 5, count 0 2006.257.11:03:07.07#ibcon#enter sib2, iclass 5, count 0 2006.257.11:03:07.07#ibcon#flushed, iclass 5, count 0 2006.257.11:03:07.07#ibcon#about to write, iclass 5, count 0 2006.257.11:03:07.07#ibcon#wrote, iclass 5, count 0 2006.257.11:03:07.07#ibcon#about to read 3, iclass 5, count 0 2006.257.11:03:07.09#ibcon#read 3, iclass 5, count 0 2006.257.11:03:07.09#ibcon#about to read 4, iclass 5, count 0 2006.257.11:03:07.09#ibcon#read 4, iclass 5, count 0 2006.257.11:03:07.09#ibcon#about to read 5, iclass 5, count 0 2006.257.11:03:07.09#ibcon#read 5, iclass 5, count 0 2006.257.11:03:07.09#ibcon#about to read 6, iclass 5, count 0 2006.257.11:03:07.09#ibcon#read 6, iclass 5, count 0 2006.257.11:03:07.09#ibcon#end of sib2, iclass 5, count 0 2006.257.11:03:07.09#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:03:07.09#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:03:07.09#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:03:07.09#ibcon#*before write, iclass 5, count 0 2006.257.11:03:07.09#ibcon#enter sib2, iclass 5, count 0 2006.257.11:03:07.09#ibcon#flushed, iclass 5, count 0 2006.257.11:03:07.09#ibcon#about to write, iclass 5, count 0 2006.257.11:03:07.09#ibcon#wrote, iclass 5, count 0 2006.257.11:03:07.09#ibcon#about to read 3, iclass 5, count 0 2006.257.11:03:07.13#ibcon#read 3, iclass 5, count 0 2006.257.11:03:07.13#ibcon#about to read 4, iclass 5, count 0 2006.257.11:03:07.13#ibcon#read 4, iclass 5, count 0 2006.257.11:03:07.13#ibcon#about to read 5, iclass 5, count 0 2006.257.11:03:07.13#ibcon#read 5, iclass 5, count 0 2006.257.11:03:07.13#ibcon#about to read 6, iclass 5, count 0 2006.257.11:03:07.13#ibcon#read 6, iclass 5, count 0 2006.257.11:03:07.13#ibcon#end of sib2, iclass 5, count 0 2006.257.11:03:07.13#ibcon#*after write, iclass 5, count 0 2006.257.11:03:07.13#ibcon#*before return 0, iclass 5, count 0 2006.257.11:03:07.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:07.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:07.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:03:07.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:03:07.13$vck44/va=6,4 2006.257.11:03:07.13#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.11:03:07.13#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.11:03:07.13#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:07.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:07.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:07.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:07.19#ibcon#enter wrdev, iclass 7, count 2 2006.257.11:03:07.19#ibcon#first serial, iclass 7, count 2 2006.257.11:03:07.19#ibcon#enter sib2, iclass 7, count 2 2006.257.11:03:07.19#ibcon#flushed, iclass 7, count 2 2006.257.11:03:07.19#ibcon#about to write, iclass 7, count 2 2006.257.11:03:07.19#ibcon#wrote, iclass 7, count 2 2006.257.11:03:07.19#ibcon#about to read 3, iclass 7, count 2 2006.257.11:03:07.21#ibcon#read 3, iclass 7, count 2 2006.257.11:03:07.21#ibcon#about to read 4, iclass 7, count 2 2006.257.11:03:07.21#ibcon#read 4, iclass 7, count 2 2006.257.11:03:07.21#ibcon#about to read 5, iclass 7, count 2 2006.257.11:03:07.21#ibcon#read 5, iclass 7, count 2 2006.257.11:03:07.21#ibcon#about to read 6, iclass 7, count 2 2006.257.11:03:07.21#ibcon#read 6, iclass 7, count 2 2006.257.11:03:07.21#ibcon#end of sib2, iclass 7, count 2 2006.257.11:03:07.21#ibcon#*mode == 0, iclass 7, count 2 2006.257.11:03:07.21#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.11:03:07.21#ibcon#[25=AT06-04\r\n] 2006.257.11:03:07.21#ibcon#*before write, iclass 7, count 2 2006.257.11:03:07.21#ibcon#enter sib2, iclass 7, count 2 2006.257.11:03:07.21#ibcon#flushed, iclass 7, count 2 2006.257.11:03:07.21#ibcon#about to write, iclass 7, count 2 2006.257.11:03:07.21#ibcon#wrote, iclass 7, count 2 2006.257.11:03:07.21#ibcon#about to read 3, iclass 7, count 2 2006.257.11:03:07.24#ibcon#read 3, iclass 7, count 2 2006.257.11:03:07.24#ibcon#about to read 4, iclass 7, count 2 2006.257.11:03:07.24#ibcon#read 4, iclass 7, count 2 2006.257.11:03:07.24#ibcon#about to read 5, iclass 7, count 2 2006.257.11:03:07.24#ibcon#read 5, iclass 7, count 2 2006.257.11:03:07.24#ibcon#about to read 6, iclass 7, count 2 2006.257.11:03:07.24#ibcon#read 6, iclass 7, count 2 2006.257.11:03:07.24#ibcon#end of sib2, iclass 7, count 2 2006.257.11:03:07.24#ibcon#*after write, iclass 7, count 2 2006.257.11:03:07.24#ibcon#*before return 0, iclass 7, count 2 2006.257.11:03:07.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:07.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:07.24#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.11:03:07.24#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:07.24#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:07.36#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:07.36#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:07.36#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:03:07.36#ibcon#first serial, iclass 7, count 0 2006.257.11:03:07.36#ibcon#enter sib2, iclass 7, count 0 2006.257.11:03:07.36#ibcon#flushed, iclass 7, count 0 2006.257.11:03:07.36#ibcon#about to write, iclass 7, count 0 2006.257.11:03:07.36#ibcon#wrote, iclass 7, count 0 2006.257.11:03:07.36#ibcon#about to read 3, iclass 7, count 0 2006.257.11:03:07.38#ibcon#read 3, iclass 7, count 0 2006.257.11:03:07.38#ibcon#about to read 4, iclass 7, count 0 2006.257.11:03:07.38#ibcon#read 4, iclass 7, count 0 2006.257.11:03:07.38#ibcon#about to read 5, iclass 7, count 0 2006.257.11:03:07.38#ibcon#read 5, iclass 7, count 0 2006.257.11:03:07.38#ibcon#about to read 6, iclass 7, count 0 2006.257.11:03:07.38#ibcon#read 6, iclass 7, count 0 2006.257.11:03:07.38#ibcon#end of sib2, iclass 7, count 0 2006.257.11:03:07.38#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:03:07.38#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:03:07.38#ibcon#[25=USB\r\n] 2006.257.11:03:07.38#ibcon#*before write, iclass 7, count 0 2006.257.11:03:07.38#ibcon#enter sib2, iclass 7, count 0 2006.257.11:03:07.38#ibcon#flushed, iclass 7, count 0 2006.257.11:03:07.38#ibcon#about to write, iclass 7, count 0 2006.257.11:03:07.38#ibcon#wrote, iclass 7, count 0 2006.257.11:03:07.38#ibcon#about to read 3, iclass 7, count 0 2006.257.11:03:07.41#ibcon#read 3, iclass 7, count 0 2006.257.11:03:07.41#ibcon#about to read 4, iclass 7, count 0 2006.257.11:03:07.41#ibcon#read 4, iclass 7, count 0 2006.257.11:03:07.41#ibcon#about to read 5, iclass 7, count 0 2006.257.11:03:07.41#ibcon#read 5, iclass 7, count 0 2006.257.11:03:07.41#ibcon#about to read 6, iclass 7, count 0 2006.257.11:03:07.41#ibcon#read 6, iclass 7, count 0 2006.257.11:03:07.41#ibcon#end of sib2, iclass 7, count 0 2006.257.11:03:07.41#ibcon#*after write, iclass 7, count 0 2006.257.11:03:07.41#ibcon#*before return 0, iclass 7, count 0 2006.257.11:03:07.41#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:07.41#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:07.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:03:07.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:03:07.41$vck44/valo=7,864.99 2006.257.11:03:07.41#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.11:03:07.41#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.11:03:07.41#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:07.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:07.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:07.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:07.41#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:03:07.41#ibcon#first serial, iclass 11, count 0 2006.257.11:03:07.41#ibcon#enter sib2, iclass 11, count 0 2006.257.11:03:07.41#ibcon#flushed, iclass 11, count 0 2006.257.11:03:07.41#ibcon#about to write, iclass 11, count 0 2006.257.11:03:07.41#ibcon#wrote, iclass 11, count 0 2006.257.11:03:07.41#ibcon#about to read 3, iclass 11, count 0 2006.257.11:03:07.43#ibcon#read 3, iclass 11, count 0 2006.257.11:03:07.43#ibcon#about to read 4, iclass 11, count 0 2006.257.11:03:07.43#ibcon#read 4, iclass 11, count 0 2006.257.11:03:07.43#ibcon#about to read 5, iclass 11, count 0 2006.257.11:03:07.43#ibcon#read 5, iclass 11, count 0 2006.257.11:03:07.43#ibcon#about to read 6, iclass 11, count 0 2006.257.11:03:07.43#ibcon#read 6, iclass 11, count 0 2006.257.11:03:07.43#ibcon#end of sib2, iclass 11, count 0 2006.257.11:03:07.43#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:03:07.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:03:07.43#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:03:07.43#ibcon#*before write, iclass 11, count 0 2006.257.11:03:07.43#ibcon#enter sib2, iclass 11, count 0 2006.257.11:03:07.43#ibcon#flushed, iclass 11, count 0 2006.257.11:03:07.43#ibcon#about to write, iclass 11, count 0 2006.257.11:03:07.43#ibcon#wrote, iclass 11, count 0 2006.257.11:03:07.43#ibcon#about to read 3, iclass 11, count 0 2006.257.11:03:07.47#ibcon#read 3, iclass 11, count 0 2006.257.11:03:07.47#ibcon#about to read 4, iclass 11, count 0 2006.257.11:03:07.47#ibcon#read 4, iclass 11, count 0 2006.257.11:03:07.47#ibcon#about to read 5, iclass 11, count 0 2006.257.11:03:07.47#ibcon#read 5, iclass 11, count 0 2006.257.11:03:07.47#ibcon#about to read 6, iclass 11, count 0 2006.257.11:03:07.47#ibcon#read 6, iclass 11, count 0 2006.257.11:03:07.47#ibcon#end of sib2, iclass 11, count 0 2006.257.11:03:07.47#ibcon#*after write, iclass 11, count 0 2006.257.11:03:07.47#ibcon#*before return 0, iclass 11, count 0 2006.257.11:03:07.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:07.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:07.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:03:07.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:03:07.47$vck44/va=7,4 2006.257.11:03:07.47#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.11:03:07.47#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.11:03:07.47#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:07.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:07.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:07.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:07.53#ibcon#enter wrdev, iclass 13, count 2 2006.257.11:03:07.53#ibcon#first serial, iclass 13, count 2 2006.257.11:03:07.53#ibcon#enter sib2, iclass 13, count 2 2006.257.11:03:07.53#ibcon#flushed, iclass 13, count 2 2006.257.11:03:07.53#ibcon#about to write, iclass 13, count 2 2006.257.11:03:07.53#ibcon#wrote, iclass 13, count 2 2006.257.11:03:07.53#ibcon#about to read 3, iclass 13, count 2 2006.257.11:03:07.55#ibcon#read 3, iclass 13, count 2 2006.257.11:03:07.55#ibcon#about to read 4, iclass 13, count 2 2006.257.11:03:07.55#ibcon#read 4, iclass 13, count 2 2006.257.11:03:07.55#ibcon#about to read 5, iclass 13, count 2 2006.257.11:03:07.55#ibcon#read 5, iclass 13, count 2 2006.257.11:03:07.55#ibcon#about to read 6, iclass 13, count 2 2006.257.11:03:07.55#ibcon#read 6, iclass 13, count 2 2006.257.11:03:07.55#ibcon#end of sib2, iclass 13, count 2 2006.257.11:03:07.55#ibcon#*mode == 0, iclass 13, count 2 2006.257.11:03:07.55#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.11:03:07.55#ibcon#[25=AT07-04\r\n] 2006.257.11:03:07.55#ibcon#*before write, iclass 13, count 2 2006.257.11:03:07.55#ibcon#enter sib2, iclass 13, count 2 2006.257.11:03:07.55#ibcon#flushed, iclass 13, count 2 2006.257.11:03:07.55#ibcon#about to write, iclass 13, count 2 2006.257.11:03:07.55#ibcon#wrote, iclass 13, count 2 2006.257.11:03:07.55#ibcon#about to read 3, iclass 13, count 2 2006.257.11:03:07.58#ibcon#read 3, iclass 13, count 2 2006.257.11:03:07.58#ibcon#about to read 4, iclass 13, count 2 2006.257.11:03:07.58#ibcon#read 4, iclass 13, count 2 2006.257.11:03:07.58#ibcon#about to read 5, iclass 13, count 2 2006.257.11:03:07.58#ibcon#read 5, iclass 13, count 2 2006.257.11:03:07.58#ibcon#about to read 6, iclass 13, count 2 2006.257.11:03:07.58#ibcon#read 6, iclass 13, count 2 2006.257.11:03:07.58#ibcon#end of sib2, iclass 13, count 2 2006.257.11:03:07.58#ibcon#*after write, iclass 13, count 2 2006.257.11:03:07.58#ibcon#*before return 0, iclass 13, count 2 2006.257.11:03:07.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:07.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:07.59#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.11:03:07.59#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:07.59#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:07.71#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:07.71#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:07.71#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:03:07.71#ibcon#first serial, iclass 13, count 0 2006.257.11:03:07.71#ibcon#enter sib2, iclass 13, count 0 2006.257.11:03:07.71#ibcon#flushed, iclass 13, count 0 2006.257.11:03:07.71#ibcon#about to write, iclass 13, count 0 2006.257.11:03:07.71#ibcon#wrote, iclass 13, count 0 2006.257.11:03:07.71#ibcon#about to read 3, iclass 13, count 0 2006.257.11:03:07.73#ibcon#read 3, iclass 13, count 0 2006.257.11:03:07.73#ibcon#about to read 4, iclass 13, count 0 2006.257.11:03:07.73#ibcon#read 4, iclass 13, count 0 2006.257.11:03:07.73#ibcon#about to read 5, iclass 13, count 0 2006.257.11:03:07.73#ibcon#read 5, iclass 13, count 0 2006.257.11:03:07.73#ibcon#about to read 6, iclass 13, count 0 2006.257.11:03:07.73#ibcon#read 6, iclass 13, count 0 2006.257.11:03:07.73#ibcon#end of sib2, iclass 13, count 0 2006.257.11:03:07.73#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:03:07.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:03:07.73#ibcon#[25=USB\r\n] 2006.257.11:03:07.73#ibcon#*before write, iclass 13, count 0 2006.257.11:03:07.73#ibcon#enter sib2, iclass 13, count 0 2006.257.11:03:07.73#ibcon#flushed, iclass 13, count 0 2006.257.11:03:07.73#ibcon#about to write, iclass 13, count 0 2006.257.11:03:07.73#ibcon#wrote, iclass 13, count 0 2006.257.11:03:07.73#ibcon#about to read 3, iclass 13, count 0 2006.257.11:03:07.76#ibcon#read 3, iclass 13, count 0 2006.257.11:03:07.76#ibcon#about to read 4, iclass 13, count 0 2006.257.11:03:07.76#ibcon#read 4, iclass 13, count 0 2006.257.11:03:07.76#ibcon#about to read 5, iclass 13, count 0 2006.257.11:03:07.76#ibcon#read 5, iclass 13, count 0 2006.257.11:03:07.76#ibcon#about to read 6, iclass 13, count 0 2006.257.11:03:07.76#ibcon#read 6, iclass 13, count 0 2006.257.11:03:07.76#ibcon#end of sib2, iclass 13, count 0 2006.257.11:03:07.76#ibcon#*after write, iclass 13, count 0 2006.257.11:03:07.76#ibcon#*before return 0, iclass 13, count 0 2006.257.11:03:07.76#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:07.76#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:07.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:03:07.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:03:07.76$vck44/valo=8,884.99 2006.257.11:03:07.76#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.11:03:07.76#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.11:03:07.76#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:07.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:07.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:07.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:07.76#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:03:07.76#ibcon#first serial, iclass 15, count 0 2006.257.11:03:07.76#ibcon#enter sib2, iclass 15, count 0 2006.257.11:03:07.76#ibcon#flushed, iclass 15, count 0 2006.257.11:03:07.76#ibcon#about to write, iclass 15, count 0 2006.257.11:03:07.76#ibcon#wrote, iclass 15, count 0 2006.257.11:03:07.76#ibcon#about to read 3, iclass 15, count 0 2006.257.11:03:07.78#ibcon#read 3, iclass 15, count 0 2006.257.11:03:07.78#ibcon#about to read 4, iclass 15, count 0 2006.257.11:03:07.78#ibcon#read 4, iclass 15, count 0 2006.257.11:03:07.78#ibcon#about to read 5, iclass 15, count 0 2006.257.11:03:07.78#ibcon#read 5, iclass 15, count 0 2006.257.11:03:07.78#ibcon#about to read 6, iclass 15, count 0 2006.257.11:03:07.78#ibcon#read 6, iclass 15, count 0 2006.257.11:03:07.78#ibcon#end of sib2, iclass 15, count 0 2006.257.11:03:07.78#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:03:07.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:03:07.78#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:03:07.78#ibcon#*before write, iclass 15, count 0 2006.257.11:03:07.78#ibcon#enter sib2, iclass 15, count 0 2006.257.11:03:07.78#ibcon#flushed, iclass 15, count 0 2006.257.11:03:07.78#ibcon#about to write, iclass 15, count 0 2006.257.11:03:07.78#ibcon#wrote, iclass 15, count 0 2006.257.11:03:07.78#ibcon#about to read 3, iclass 15, count 0 2006.257.11:03:07.82#ibcon#read 3, iclass 15, count 0 2006.257.11:03:07.82#ibcon#about to read 4, iclass 15, count 0 2006.257.11:03:07.82#ibcon#read 4, iclass 15, count 0 2006.257.11:03:07.82#ibcon#about to read 5, iclass 15, count 0 2006.257.11:03:07.82#ibcon#read 5, iclass 15, count 0 2006.257.11:03:07.82#ibcon#about to read 6, iclass 15, count 0 2006.257.11:03:07.82#ibcon#read 6, iclass 15, count 0 2006.257.11:03:07.82#ibcon#end of sib2, iclass 15, count 0 2006.257.11:03:07.82#ibcon#*after write, iclass 15, count 0 2006.257.11:03:07.82#ibcon#*before return 0, iclass 15, count 0 2006.257.11:03:07.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:07.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:07.82#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:03:07.82#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:03:07.82$vck44/va=8,4 2006.257.11:03:07.82#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.11:03:07.82#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.11:03:07.82#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:07.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:03:07.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:03:07.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:03:07.88#ibcon#enter wrdev, iclass 17, count 2 2006.257.11:03:07.88#ibcon#first serial, iclass 17, count 2 2006.257.11:03:07.88#ibcon#enter sib2, iclass 17, count 2 2006.257.11:03:07.88#ibcon#flushed, iclass 17, count 2 2006.257.11:03:07.88#ibcon#about to write, iclass 17, count 2 2006.257.11:03:07.88#ibcon#wrote, iclass 17, count 2 2006.257.11:03:07.88#ibcon#about to read 3, iclass 17, count 2 2006.257.11:03:07.90#ibcon#read 3, iclass 17, count 2 2006.257.11:03:07.90#ibcon#about to read 4, iclass 17, count 2 2006.257.11:03:07.90#ibcon#read 4, iclass 17, count 2 2006.257.11:03:07.90#ibcon#about to read 5, iclass 17, count 2 2006.257.11:03:07.90#ibcon#read 5, iclass 17, count 2 2006.257.11:03:07.90#ibcon#about to read 6, iclass 17, count 2 2006.257.11:03:07.90#ibcon#read 6, iclass 17, count 2 2006.257.11:03:07.90#ibcon#end of sib2, iclass 17, count 2 2006.257.11:03:07.90#ibcon#*mode == 0, iclass 17, count 2 2006.257.11:03:07.90#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.11:03:07.90#ibcon#[25=AT08-04\r\n] 2006.257.11:03:07.90#ibcon#*before write, iclass 17, count 2 2006.257.11:03:07.90#ibcon#enter sib2, iclass 17, count 2 2006.257.11:03:07.90#ibcon#flushed, iclass 17, count 2 2006.257.11:03:07.90#ibcon#about to write, iclass 17, count 2 2006.257.11:03:07.90#ibcon#wrote, iclass 17, count 2 2006.257.11:03:07.90#ibcon#about to read 3, iclass 17, count 2 2006.257.11:03:07.93#ibcon#read 3, iclass 17, count 2 2006.257.11:03:07.93#ibcon#about to read 4, iclass 17, count 2 2006.257.11:03:07.93#ibcon#read 4, iclass 17, count 2 2006.257.11:03:07.93#ibcon#about to read 5, iclass 17, count 2 2006.257.11:03:07.93#ibcon#read 5, iclass 17, count 2 2006.257.11:03:07.93#ibcon#about to read 6, iclass 17, count 2 2006.257.11:03:07.93#ibcon#read 6, iclass 17, count 2 2006.257.11:03:07.93#ibcon#end of sib2, iclass 17, count 2 2006.257.11:03:07.93#ibcon#*after write, iclass 17, count 2 2006.257.11:03:07.93#ibcon#*before return 0, iclass 17, count 2 2006.257.11:03:07.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:03:07.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:03:07.93#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.11:03:07.93#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:07.93#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:03:08.05#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:03:08.05#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:03:08.05#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:03:08.05#ibcon#first serial, iclass 17, count 0 2006.257.11:03:08.05#ibcon#enter sib2, iclass 17, count 0 2006.257.11:03:08.05#ibcon#flushed, iclass 17, count 0 2006.257.11:03:08.05#ibcon#about to write, iclass 17, count 0 2006.257.11:03:08.05#ibcon#wrote, iclass 17, count 0 2006.257.11:03:08.05#ibcon#about to read 3, iclass 17, count 0 2006.257.11:03:08.07#ibcon#read 3, iclass 17, count 0 2006.257.11:03:08.07#ibcon#about to read 4, iclass 17, count 0 2006.257.11:03:08.07#ibcon#read 4, iclass 17, count 0 2006.257.11:03:08.07#ibcon#about to read 5, iclass 17, count 0 2006.257.11:03:08.07#ibcon#read 5, iclass 17, count 0 2006.257.11:03:08.07#ibcon#about to read 6, iclass 17, count 0 2006.257.11:03:08.07#ibcon#read 6, iclass 17, count 0 2006.257.11:03:08.07#ibcon#end of sib2, iclass 17, count 0 2006.257.11:03:08.07#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:03:08.07#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:03:08.07#ibcon#[25=USB\r\n] 2006.257.11:03:08.07#ibcon#*before write, iclass 17, count 0 2006.257.11:03:08.07#ibcon#enter sib2, iclass 17, count 0 2006.257.11:03:08.07#ibcon#flushed, iclass 17, count 0 2006.257.11:03:08.07#ibcon#about to write, iclass 17, count 0 2006.257.11:03:08.07#ibcon#wrote, iclass 17, count 0 2006.257.11:03:08.07#ibcon#about to read 3, iclass 17, count 0 2006.257.11:03:08.10#ibcon#read 3, iclass 17, count 0 2006.257.11:03:08.10#ibcon#about to read 4, iclass 17, count 0 2006.257.11:03:08.10#ibcon#read 4, iclass 17, count 0 2006.257.11:03:08.10#ibcon#about to read 5, iclass 17, count 0 2006.257.11:03:08.10#ibcon#read 5, iclass 17, count 0 2006.257.11:03:08.10#ibcon#about to read 6, iclass 17, count 0 2006.257.11:03:08.10#ibcon#read 6, iclass 17, count 0 2006.257.11:03:08.10#ibcon#end of sib2, iclass 17, count 0 2006.257.11:03:08.10#ibcon#*after write, iclass 17, count 0 2006.257.11:03:08.10#ibcon#*before return 0, iclass 17, count 0 2006.257.11:03:08.10#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:03:08.10#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:03:08.10#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:03:08.10#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:03:08.10$vck44/vblo=1,629.99 2006.257.11:03:08.10#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.11:03:08.10#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.11:03:08.10#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:08.10#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:03:08.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:03:08.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:03:08.10#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:03:08.10#ibcon#first serial, iclass 19, count 0 2006.257.11:03:08.10#ibcon#enter sib2, iclass 19, count 0 2006.257.11:03:08.10#ibcon#flushed, iclass 19, count 0 2006.257.11:03:08.10#ibcon#about to write, iclass 19, count 0 2006.257.11:03:08.10#ibcon#wrote, iclass 19, count 0 2006.257.11:03:08.10#ibcon#about to read 3, iclass 19, count 0 2006.257.11:03:08.12#ibcon#read 3, iclass 19, count 0 2006.257.11:03:08.12#ibcon#about to read 4, iclass 19, count 0 2006.257.11:03:08.12#ibcon#read 4, iclass 19, count 0 2006.257.11:03:08.12#ibcon#about to read 5, iclass 19, count 0 2006.257.11:03:08.12#ibcon#read 5, iclass 19, count 0 2006.257.11:03:08.12#ibcon#about to read 6, iclass 19, count 0 2006.257.11:03:08.12#ibcon#read 6, iclass 19, count 0 2006.257.11:03:08.12#ibcon#end of sib2, iclass 19, count 0 2006.257.11:03:08.12#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:03:08.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:03:08.12#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:03:08.12#ibcon#*before write, iclass 19, count 0 2006.257.11:03:08.12#ibcon#enter sib2, iclass 19, count 0 2006.257.11:03:08.12#ibcon#flushed, iclass 19, count 0 2006.257.11:03:08.12#ibcon#about to write, iclass 19, count 0 2006.257.11:03:08.12#ibcon#wrote, iclass 19, count 0 2006.257.11:03:08.12#ibcon#about to read 3, iclass 19, count 0 2006.257.11:03:08.16#ibcon#read 3, iclass 19, count 0 2006.257.11:03:08.16#ibcon#about to read 4, iclass 19, count 0 2006.257.11:03:08.16#ibcon#read 4, iclass 19, count 0 2006.257.11:03:08.16#ibcon#about to read 5, iclass 19, count 0 2006.257.11:03:08.16#ibcon#read 5, iclass 19, count 0 2006.257.11:03:08.16#ibcon#about to read 6, iclass 19, count 0 2006.257.11:03:08.16#ibcon#read 6, iclass 19, count 0 2006.257.11:03:08.16#ibcon#end of sib2, iclass 19, count 0 2006.257.11:03:08.16#ibcon#*after write, iclass 19, count 0 2006.257.11:03:08.16#ibcon#*before return 0, iclass 19, count 0 2006.257.11:03:08.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:03:08.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:03:08.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:03:08.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:03:08.16$vck44/vb=1,4 2006.257.11:03:08.16#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.11:03:08.16#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.11:03:08.16#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:08.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:03:08.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:03:08.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:03:08.16#ibcon#enter wrdev, iclass 21, count 2 2006.257.11:03:08.16#ibcon#first serial, iclass 21, count 2 2006.257.11:03:08.16#ibcon#enter sib2, iclass 21, count 2 2006.257.11:03:08.16#ibcon#flushed, iclass 21, count 2 2006.257.11:03:08.16#ibcon#about to write, iclass 21, count 2 2006.257.11:03:08.16#ibcon#wrote, iclass 21, count 2 2006.257.11:03:08.16#ibcon#about to read 3, iclass 21, count 2 2006.257.11:03:08.18#ibcon#read 3, iclass 21, count 2 2006.257.11:03:08.18#ibcon#about to read 4, iclass 21, count 2 2006.257.11:03:08.18#ibcon#read 4, iclass 21, count 2 2006.257.11:03:08.18#ibcon#about to read 5, iclass 21, count 2 2006.257.11:03:08.18#ibcon#read 5, iclass 21, count 2 2006.257.11:03:08.18#ibcon#about to read 6, iclass 21, count 2 2006.257.11:03:08.18#ibcon#read 6, iclass 21, count 2 2006.257.11:03:08.18#ibcon#end of sib2, iclass 21, count 2 2006.257.11:03:08.18#ibcon#*mode == 0, iclass 21, count 2 2006.257.11:03:08.18#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.11:03:08.18#ibcon#[27=AT01-04\r\n] 2006.257.11:03:08.18#ibcon#*before write, iclass 21, count 2 2006.257.11:03:08.18#ibcon#enter sib2, iclass 21, count 2 2006.257.11:03:08.18#ibcon#flushed, iclass 21, count 2 2006.257.11:03:08.18#ibcon#about to write, iclass 21, count 2 2006.257.11:03:08.18#ibcon#wrote, iclass 21, count 2 2006.257.11:03:08.18#ibcon#about to read 3, iclass 21, count 2 2006.257.11:03:08.21#ibcon#read 3, iclass 21, count 2 2006.257.11:03:08.21#ibcon#about to read 4, iclass 21, count 2 2006.257.11:03:08.21#ibcon#read 4, iclass 21, count 2 2006.257.11:03:08.21#ibcon#about to read 5, iclass 21, count 2 2006.257.11:03:08.21#ibcon#read 5, iclass 21, count 2 2006.257.11:03:08.21#ibcon#about to read 6, iclass 21, count 2 2006.257.11:03:08.21#ibcon#read 6, iclass 21, count 2 2006.257.11:03:08.21#ibcon#end of sib2, iclass 21, count 2 2006.257.11:03:08.21#ibcon#*after write, iclass 21, count 2 2006.257.11:03:08.21#ibcon#*before return 0, iclass 21, count 2 2006.257.11:03:08.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:03:08.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:03:08.21#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.11:03:08.21#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:08.21#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:03:08.33#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:03:08.33#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:03:08.33#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:03:08.33#ibcon#first serial, iclass 21, count 0 2006.257.11:03:08.33#ibcon#enter sib2, iclass 21, count 0 2006.257.11:03:08.33#ibcon#flushed, iclass 21, count 0 2006.257.11:03:08.33#ibcon#about to write, iclass 21, count 0 2006.257.11:03:08.33#ibcon#wrote, iclass 21, count 0 2006.257.11:03:08.33#ibcon#about to read 3, iclass 21, count 0 2006.257.11:03:08.35#ibcon#read 3, iclass 21, count 0 2006.257.11:03:08.35#ibcon#about to read 4, iclass 21, count 0 2006.257.11:03:08.35#ibcon#read 4, iclass 21, count 0 2006.257.11:03:08.35#ibcon#about to read 5, iclass 21, count 0 2006.257.11:03:08.35#ibcon#read 5, iclass 21, count 0 2006.257.11:03:08.35#ibcon#about to read 6, iclass 21, count 0 2006.257.11:03:08.35#ibcon#read 6, iclass 21, count 0 2006.257.11:03:08.35#ibcon#end of sib2, iclass 21, count 0 2006.257.11:03:08.35#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:03:08.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:03:08.35#ibcon#[27=USB\r\n] 2006.257.11:03:08.35#ibcon#*before write, iclass 21, count 0 2006.257.11:03:08.35#ibcon#enter sib2, iclass 21, count 0 2006.257.11:03:08.35#ibcon#flushed, iclass 21, count 0 2006.257.11:03:08.35#ibcon#about to write, iclass 21, count 0 2006.257.11:03:08.35#ibcon#wrote, iclass 21, count 0 2006.257.11:03:08.35#ibcon#about to read 3, iclass 21, count 0 2006.257.11:03:08.38#ibcon#read 3, iclass 21, count 0 2006.257.11:03:08.38#ibcon#about to read 4, iclass 21, count 0 2006.257.11:03:08.38#ibcon#read 4, iclass 21, count 0 2006.257.11:03:08.38#ibcon#about to read 5, iclass 21, count 0 2006.257.11:03:08.38#ibcon#read 5, iclass 21, count 0 2006.257.11:03:08.38#ibcon#about to read 6, iclass 21, count 0 2006.257.11:03:08.38#ibcon#read 6, iclass 21, count 0 2006.257.11:03:08.38#ibcon#end of sib2, iclass 21, count 0 2006.257.11:03:08.38#ibcon#*after write, iclass 21, count 0 2006.257.11:03:08.38#ibcon#*before return 0, iclass 21, count 0 2006.257.11:03:08.38#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:03:08.38#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:03:08.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:03:08.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:03:08.38$vck44/vblo=2,634.99 2006.257.11:03:08.38#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.11:03:08.38#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.11:03:08.38#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:08.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:08.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:08.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:08.38#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:03:08.38#ibcon#first serial, iclass 23, count 0 2006.257.11:03:08.38#ibcon#enter sib2, iclass 23, count 0 2006.257.11:03:08.38#ibcon#flushed, iclass 23, count 0 2006.257.11:03:08.38#ibcon#about to write, iclass 23, count 0 2006.257.11:03:08.38#ibcon#wrote, iclass 23, count 0 2006.257.11:03:08.38#ibcon#about to read 3, iclass 23, count 0 2006.257.11:03:08.40#ibcon#read 3, iclass 23, count 0 2006.257.11:03:08.40#ibcon#about to read 4, iclass 23, count 0 2006.257.11:03:08.40#ibcon#read 4, iclass 23, count 0 2006.257.11:03:08.40#ibcon#about to read 5, iclass 23, count 0 2006.257.11:03:08.40#ibcon#read 5, iclass 23, count 0 2006.257.11:03:08.40#ibcon#about to read 6, iclass 23, count 0 2006.257.11:03:08.40#ibcon#read 6, iclass 23, count 0 2006.257.11:03:08.40#ibcon#end of sib2, iclass 23, count 0 2006.257.11:03:08.40#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:03:08.40#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:03:08.40#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:03:08.40#ibcon#*before write, iclass 23, count 0 2006.257.11:03:08.40#ibcon#enter sib2, iclass 23, count 0 2006.257.11:03:08.40#ibcon#flushed, iclass 23, count 0 2006.257.11:03:08.40#ibcon#about to write, iclass 23, count 0 2006.257.11:03:08.40#ibcon#wrote, iclass 23, count 0 2006.257.11:03:08.40#ibcon#about to read 3, iclass 23, count 0 2006.257.11:03:08.44#ibcon#read 3, iclass 23, count 0 2006.257.11:03:08.44#ibcon#about to read 4, iclass 23, count 0 2006.257.11:03:08.44#ibcon#read 4, iclass 23, count 0 2006.257.11:03:08.44#ibcon#about to read 5, iclass 23, count 0 2006.257.11:03:08.44#ibcon#read 5, iclass 23, count 0 2006.257.11:03:08.44#ibcon#about to read 6, iclass 23, count 0 2006.257.11:03:08.44#ibcon#read 6, iclass 23, count 0 2006.257.11:03:08.44#ibcon#end of sib2, iclass 23, count 0 2006.257.11:03:08.44#ibcon#*after write, iclass 23, count 0 2006.257.11:03:08.44#ibcon#*before return 0, iclass 23, count 0 2006.257.11:03:08.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:08.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:03:08.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:03:08.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:03:08.44$vck44/vb=2,5 2006.257.11:03:08.44#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.11:03:08.44#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.11:03:08.44#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:08.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:08.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:08.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:08.50#ibcon#enter wrdev, iclass 25, count 2 2006.257.11:03:08.50#ibcon#first serial, iclass 25, count 2 2006.257.11:03:08.50#ibcon#enter sib2, iclass 25, count 2 2006.257.11:03:08.50#ibcon#flushed, iclass 25, count 2 2006.257.11:03:08.50#ibcon#about to write, iclass 25, count 2 2006.257.11:03:08.50#ibcon#wrote, iclass 25, count 2 2006.257.11:03:08.50#ibcon#about to read 3, iclass 25, count 2 2006.257.11:03:08.52#ibcon#read 3, iclass 25, count 2 2006.257.11:03:08.52#ibcon#about to read 4, iclass 25, count 2 2006.257.11:03:08.52#ibcon#read 4, iclass 25, count 2 2006.257.11:03:08.52#ibcon#about to read 5, iclass 25, count 2 2006.257.11:03:08.52#ibcon#read 5, iclass 25, count 2 2006.257.11:03:08.52#ibcon#about to read 6, iclass 25, count 2 2006.257.11:03:08.52#ibcon#read 6, iclass 25, count 2 2006.257.11:03:08.52#ibcon#end of sib2, iclass 25, count 2 2006.257.11:03:08.52#ibcon#*mode == 0, iclass 25, count 2 2006.257.11:03:08.52#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.11:03:08.52#ibcon#[27=AT02-05\r\n] 2006.257.11:03:08.52#ibcon#*before write, iclass 25, count 2 2006.257.11:03:08.52#ibcon#enter sib2, iclass 25, count 2 2006.257.11:03:08.52#ibcon#flushed, iclass 25, count 2 2006.257.11:03:08.52#ibcon#about to write, iclass 25, count 2 2006.257.11:03:08.52#ibcon#wrote, iclass 25, count 2 2006.257.11:03:08.52#ibcon#about to read 3, iclass 25, count 2 2006.257.11:03:08.55#ibcon#read 3, iclass 25, count 2 2006.257.11:03:08.55#ibcon#about to read 4, iclass 25, count 2 2006.257.11:03:08.55#ibcon#read 4, iclass 25, count 2 2006.257.11:03:08.55#ibcon#about to read 5, iclass 25, count 2 2006.257.11:03:08.55#ibcon#read 5, iclass 25, count 2 2006.257.11:03:08.55#ibcon#about to read 6, iclass 25, count 2 2006.257.11:03:08.55#ibcon#read 6, iclass 25, count 2 2006.257.11:03:08.55#ibcon#end of sib2, iclass 25, count 2 2006.257.11:03:08.55#ibcon#*after write, iclass 25, count 2 2006.257.11:03:08.55#ibcon#*before return 0, iclass 25, count 2 2006.257.11:03:08.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:08.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:03:08.55#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.11:03:08.55#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:08.55#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:08.67#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:08.67#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:08.67#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:03:08.67#ibcon#first serial, iclass 25, count 0 2006.257.11:03:08.67#ibcon#enter sib2, iclass 25, count 0 2006.257.11:03:08.67#ibcon#flushed, iclass 25, count 0 2006.257.11:03:08.67#ibcon#about to write, iclass 25, count 0 2006.257.11:03:08.67#ibcon#wrote, iclass 25, count 0 2006.257.11:03:08.67#ibcon#about to read 3, iclass 25, count 0 2006.257.11:03:08.69#ibcon#read 3, iclass 25, count 0 2006.257.11:03:08.69#ibcon#about to read 4, iclass 25, count 0 2006.257.11:03:08.69#ibcon#read 4, iclass 25, count 0 2006.257.11:03:08.69#ibcon#about to read 5, iclass 25, count 0 2006.257.11:03:08.69#ibcon#read 5, iclass 25, count 0 2006.257.11:03:08.69#ibcon#about to read 6, iclass 25, count 0 2006.257.11:03:08.69#ibcon#read 6, iclass 25, count 0 2006.257.11:03:08.69#ibcon#end of sib2, iclass 25, count 0 2006.257.11:03:08.69#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:03:08.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:03:08.69#ibcon#[27=USB\r\n] 2006.257.11:03:08.69#ibcon#*before write, iclass 25, count 0 2006.257.11:03:08.69#ibcon#enter sib2, iclass 25, count 0 2006.257.11:03:08.69#ibcon#flushed, iclass 25, count 0 2006.257.11:03:08.69#ibcon#about to write, iclass 25, count 0 2006.257.11:03:08.69#ibcon#wrote, iclass 25, count 0 2006.257.11:03:08.69#ibcon#about to read 3, iclass 25, count 0 2006.257.11:03:08.72#ibcon#read 3, iclass 25, count 0 2006.257.11:03:08.72#ibcon#about to read 4, iclass 25, count 0 2006.257.11:03:08.72#ibcon#read 4, iclass 25, count 0 2006.257.11:03:08.72#ibcon#about to read 5, iclass 25, count 0 2006.257.11:03:08.72#ibcon#read 5, iclass 25, count 0 2006.257.11:03:08.72#ibcon#about to read 6, iclass 25, count 0 2006.257.11:03:08.72#ibcon#read 6, iclass 25, count 0 2006.257.11:03:08.72#ibcon#end of sib2, iclass 25, count 0 2006.257.11:03:08.72#ibcon#*after write, iclass 25, count 0 2006.257.11:03:08.72#ibcon#*before return 0, iclass 25, count 0 2006.257.11:03:08.72#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:08.72#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:03:08.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:03:08.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:03:08.72$vck44/vblo=3,649.99 2006.257.11:03:08.72#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.11:03:08.72#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.11:03:08.72#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:08.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:08.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:08.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:08.72#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:03:08.72#ibcon#first serial, iclass 27, count 0 2006.257.11:03:08.72#ibcon#enter sib2, iclass 27, count 0 2006.257.11:03:08.72#ibcon#flushed, iclass 27, count 0 2006.257.11:03:08.72#ibcon#about to write, iclass 27, count 0 2006.257.11:03:08.72#ibcon#wrote, iclass 27, count 0 2006.257.11:03:08.72#ibcon#about to read 3, iclass 27, count 0 2006.257.11:03:08.74#ibcon#read 3, iclass 27, count 0 2006.257.11:03:08.74#ibcon#about to read 4, iclass 27, count 0 2006.257.11:03:08.74#ibcon#read 4, iclass 27, count 0 2006.257.11:03:08.74#ibcon#about to read 5, iclass 27, count 0 2006.257.11:03:08.74#ibcon#read 5, iclass 27, count 0 2006.257.11:03:08.74#ibcon#about to read 6, iclass 27, count 0 2006.257.11:03:08.74#ibcon#read 6, iclass 27, count 0 2006.257.11:03:08.74#ibcon#end of sib2, iclass 27, count 0 2006.257.11:03:08.74#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:03:08.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:03:08.74#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:03:08.74#ibcon#*before write, iclass 27, count 0 2006.257.11:03:08.74#ibcon#enter sib2, iclass 27, count 0 2006.257.11:03:08.74#ibcon#flushed, iclass 27, count 0 2006.257.11:03:08.74#ibcon#about to write, iclass 27, count 0 2006.257.11:03:08.74#ibcon#wrote, iclass 27, count 0 2006.257.11:03:08.74#ibcon#about to read 3, iclass 27, count 0 2006.257.11:03:08.78#ibcon#read 3, iclass 27, count 0 2006.257.11:03:08.78#ibcon#about to read 4, iclass 27, count 0 2006.257.11:03:08.78#ibcon#read 4, iclass 27, count 0 2006.257.11:03:08.78#ibcon#about to read 5, iclass 27, count 0 2006.257.11:03:08.78#ibcon#read 5, iclass 27, count 0 2006.257.11:03:08.78#ibcon#about to read 6, iclass 27, count 0 2006.257.11:03:08.78#ibcon#read 6, iclass 27, count 0 2006.257.11:03:08.78#ibcon#end of sib2, iclass 27, count 0 2006.257.11:03:08.78#ibcon#*after write, iclass 27, count 0 2006.257.11:03:08.78#ibcon#*before return 0, iclass 27, count 0 2006.257.11:03:08.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:08.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:03:08.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:03:08.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:03:08.78$vck44/vb=3,4 2006.257.11:03:08.78#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.11:03:08.78#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.11:03:08.78#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:08.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:08.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:08.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:08.84#ibcon#enter wrdev, iclass 29, count 2 2006.257.11:03:08.84#ibcon#first serial, iclass 29, count 2 2006.257.11:03:08.84#ibcon#enter sib2, iclass 29, count 2 2006.257.11:03:08.84#ibcon#flushed, iclass 29, count 2 2006.257.11:03:08.84#ibcon#about to write, iclass 29, count 2 2006.257.11:03:08.84#ibcon#wrote, iclass 29, count 2 2006.257.11:03:08.84#ibcon#about to read 3, iclass 29, count 2 2006.257.11:03:08.86#ibcon#read 3, iclass 29, count 2 2006.257.11:03:08.86#ibcon#about to read 4, iclass 29, count 2 2006.257.11:03:08.86#ibcon#read 4, iclass 29, count 2 2006.257.11:03:08.86#ibcon#about to read 5, iclass 29, count 2 2006.257.11:03:08.86#ibcon#read 5, iclass 29, count 2 2006.257.11:03:08.86#ibcon#about to read 6, iclass 29, count 2 2006.257.11:03:08.86#ibcon#read 6, iclass 29, count 2 2006.257.11:03:08.86#ibcon#end of sib2, iclass 29, count 2 2006.257.11:03:08.86#ibcon#*mode == 0, iclass 29, count 2 2006.257.11:03:08.86#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.11:03:08.86#ibcon#[27=AT03-04\r\n] 2006.257.11:03:08.86#ibcon#*before write, iclass 29, count 2 2006.257.11:03:08.86#ibcon#enter sib2, iclass 29, count 2 2006.257.11:03:08.86#ibcon#flushed, iclass 29, count 2 2006.257.11:03:08.86#ibcon#about to write, iclass 29, count 2 2006.257.11:03:08.86#ibcon#wrote, iclass 29, count 2 2006.257.11:03:08.86#ibcon#about to read 3, iclass 29, count 2 2006.257.11:03:08.89#ibcon#read 3, iclass 29, count 2 2006.257.11:03:08.89#ibcon#about to read 4, iclass 29, count 2 2006.257.11:03:08.89#ibcon#read 4, iclass 29, count 2 2006.257.11:03:08.89#ibcon#about to read 5, iclass 29, count 2 2006.257.11:03:08.89#ibcon#read 5, iclass 29, count 2 2006.257.11:03:08.89#ibcon#about to read 6, iclass 29, count 2 2006.257.11:03:08.89#ibcon#read 6, iclass 29, count 2 2006.257.11:03:08.89#ibcon#end of sib2, iclass 29, count 2 2006.257.11:03:08.89#ibcon#*after write, iclass 29, count 2 2006.257.11:03:08.89#ibcon#*before return 0, iclass 29, count 2 2006.257.11:03:08.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:08.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:03:08.89#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.11:03:08.89#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:08.89#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:09.01#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:09.01#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:09.01#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:03:09.01#ibcon#first serial, iclass 29, count 0 2006.257.11:03:09.01#ibcon#enter sib2, iclass 29, count 0 2006.257.11:03:09.01#ibcon#flushed, iclass 29, count 0 2006.257.11:03:09.01#ibcon#about to write, iclass 29, count 0 2006.257.11:03:09.01#ibcon#wrote, iclass 29, count 0 2006.257.11:03:09.01#ibcon#about to read 3, iclass 29, count 0 2006.257.11:03:09.03#ibcon#read 3, iclass 29, count 0 2006.257.11:03:09.03#ibcon#about to read 4, iclass 29, count 0 2006.257.11:03:09.03#ibcon#read 4, iclass 29, count 0 2006.257.11:03:09.03#ibcon#about to read 5, iclass 29, count 0 2006.257.11:03:09.03#ibcon#read 5, iclass 29, count 0 2006.257.11:03:09.03#ibcon#about to read 6, iclass 29, count 0 2006.257.11:03:09.03#ibcon#read 6, iclass 29, count 0 2006.257.11:03:09.03#ibcon#end of sib2, iclass 29, count 0 2006.257.11:03:09.03#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:03:09.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:03:09.03#ibcon#[27=USB\r\n] 2006.257.11:03:09.03#ibcon#*before write, iclass 29, count 0 2006.257.11:03:09.03#ibcon#enter sib2, iclass 29, count 0 2006.257.11:03:09.03#ibcon#flushed, iclass 29, count 0 2006.257.11:03:09.03#ibcon#about to write, iclass 29, count 0 2006.257.11:03:09.03#ibcon#wrote, iclass 29, count 0 2006.257.11:03:09.03#ibcon#about to read 3, iclass 29, count 0 2006.257.11:03:09.06#ibcon#read 3, iclass 29, count 0 2006.257.11:03:09.06#ibcon#about to read 4, iclass 29, count 0 2006.257.11:03:09.06#ibcon#read 4, iclass 29, count 0 2006.257.11:03:09.06#ibcon#about to read 5, iclass 29, count 0 2006.257.11:03:09.06#ibcon#read 5, iclass 29, count 0 2006.257.11:03:09.06#ibcon#about to read 6, iclass 29, count 0 2006.257.11:03:09.06#ibcon#read 6, iclass 29, count 0 2006.257.11:03:09.06#ibcon#end of sib2, iclass 29, count 0 2006.257.11:03:09.06#ibcon#*after write, iclass 29, count 0 2006.257.11:03:09.06#ibcon#*before return 0, iclass 29, count 0 2006.257.11:03:09.06#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:09.06#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:03:09.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:03:09.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:03:09.06$vck44/vblo=4,679.99 2006.257.11:03:09.06#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.11:03:09.06#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.11:03:09.06#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:09.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:09.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:09.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:09.06#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:03:09.06#ibcon#first serial, iclass 31, count 0 2006.257.11:03:09.06#ibcon#enter sib2, iclass 31, count 0 2006.257.11:03:09.06#ibcon#flushed, iclass 31, count 0 2006.257.11:03:09.06#ibcon#about to write, iclass 31, count 0 2006.257.11:03:09.06#ibcon#wrote, iclass 31, count 0 2006.257.11:03:09.06#ibcon#about to read 3, iclass 31, count 0 2006.257.11:03:09.08#ibcon#read 3, iclass 31, count 0 2006.257.11:03:09.08#ibcon#about to read 4, iclass 31, count 0 2006.257.11:03:09.08#ibcon#read 4, iclass 31, count 0 2006.257.11:03:09.08#ibcon#about to read 5, iclass 31, count 0 2006.257.11:03:09.08#ibcon#read 5, iclass 31, count 0 2006.257.11:03:09.08#ibcon#about to read 6, iclass 31, count 0 2006.257.11:03:09.08#ibcon#read 6, iclass 31, count 0 2006.257.11:03:09.08#ibcon#end of sib2, iclass 31, count 0 2006.257.11:03:09.08#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:03:09.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:03:09.08#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:03:09.08#ibcon#*before write, iclass 31, count 0 2006.257.11:03:09.08#ibcon#enter sib2, iclass 31, count 0 2006.257.11:03:09.08#ibcon#flushed, iclass 31, count 0 2006.257.11:03:09.08#ibcon#about to write, iclass 31, count 0 2006.257.11:03:09.08#ibcon#wrote, iclass 31, count 0 2006.257.11:03:09.08#ibcon#about to read 3, iclass 31, count 0 2006.257.11:03:09.12#ibcon#read 3, iclass 31, count 0 2006.257.11:03:09.12#ibcon#about to read 4, iclass 31, count 0 2006.257.11:03:09.12#ibcon#read 4, iclass 31, count 0 2006.257.11:03:09.12#ibcon#about to read 5, iclass 31, count 0 2006.257.11:03:09.12#ibcon#read 5, iclass 31, count 0 2006.257.11:03:09.12#ibcon#about to read 6, iclass 31, count 0 2006.257.11:03:09.12#ibcon#read 6, iclass 31, count 0 2006.257.11:03:09.12#ibcon#end of sib2, iclass 31, count 0 2006.257.11:03:09.12#ibcon#*after write, iclass 31, count 0 2006.257.11:03:09.12#ibcon#*before return 0, iclass 31, count 0 2006.257.11:03:09.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:09.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:03:09.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:03:09.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:03:09.12$vck44/vb=4,5 2006.257.11:03:09.12#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.11:03:09.12#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.11:03:09.12#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:09.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:09.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:09.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:09.18#ibcon#enter wrdev, iclass 33, count 2 2006.257.11:03:09.18#ibcon#first serial, iclass 33, count 2 2006.257.11:03:09.18#ibcon#enter sib2, iclass 33, count 2 2006.257.11:03:09.18#ibcon#flushed, iclass 33, count 2 2006.257.11:03:09.18#ibcon#about to write, iclass 33, count 2 2006.257.11:03:09.18#ibcon#wrote, iclass 33, count 2 2006.257.11:03:09.18#ibcon#about to read 3, iclass 33, count 2 2006.257.11:03:09.20#ibcon#read 3, iclass 33, count 2 2006.257.11:03:09.20#ibcon#about to read 4, iclass 33, count 2 2006.257.11:03:09.20#ibcon#read 4, iclass 33, count 2 2006.257.11:03:09.20#ibcon#about to read 5, iclass 33, count 2 2006.257.11:03:09.20#ibcon#read 5, iclass 33, count 2 2006.257.11:03:09.20#ibcon#about to read 6, iclass 33, count 2 2006.257.11:03:09.20#ibcon#read 6, iclass 33, count 2 2006.257.11:03:09.20#ibcon#end of sib2, iclass 33, count 2 2006.257.11:03:09.20#ibcon#*mode == 0, iclass 33, count 2 2006.257.11:03:09.20#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.11:03:09.20#ibcon#[27=AT04-05\r\n] 2006.257.11:03:09.20#ibcon#*before write, iclass 33, count 2 2006.257.11:03:09.20#ibcon#enter sib2, iclass 33, count 2 2006.257.11:03:09.20#ibcon#flushed, iclass 33, count 2 2006.257.11:03:09.20#ibcon#about to write, iclass 33, count 2 2006.257.11:03:09.20#ibcon#wrote, iclass 33, count 2 2006.257.11:03:09.20#ibcon#about to read 3, iclass 33, count 2 2006.257.11:03:09.23#ibcon#read 3, iclass 33, count 2 2006.257.11:03:09.23#ibcon#about to read 4, iclass 33, count 2 2006.257.11:03:09.23#ibcon#read 4, iclass 33, count 2 2006.257.11:03:09.23#ibcon#about to read 5, iclass 33, count 2 2006.257.11:03:09.23#ibcon#read 5, iclass 33, count 2 2006.257.11:03:09.23#ibcon#about to read 6, iclass 33, count 2 2006.257.11:03:09.23#ibcon#read 6, iclass 33, count 2 2006.257.11:03:09.23#ibcon#end of sib2, iclass 33, count 2 2006.257.11:03:09.23#ibcon#*after write, iclass 33, count 2 2006.257.11:03:09.23#ibcon#*before return 0, iclass 33, count 2 2006.257.11:03:09.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:09.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:03:09.23#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.11:03:09.23#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:09.23#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:09.35#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:09.35#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:09.35#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:03:09.35#ibcon#first serial, iclass 33, count 0 2006.257.11:03:09.35#ibcon#enter sib2, iclass 33, count 0 2006.257.11:03:09.35#ibcon#flushed, iclass 33, count 0 2006.257.11:03:09.35#ibcon#about to write, iclass 33, count 0 2006.257.11:03:09.35#ibcon#wrote, iclass 33, count 0 2006.257.11:03:09.35#ibcon#about to read 3, iclass 33, count 0 2006.257.11:03:09.37#ibcon#read 3, iclass 33, count 0 2006.257.11:03:09.37#ibcon#about to read 4, iclass 33, count 0 2006.257.11:03:09.37#ibcon#read 4, iclass 33, count 0 2006.257.11:03:09.37#ibcon#about to read 5, iclass 33, count 0 2006.257.11:03:09.37#ibcon#read 5, iclass 33, count 0 2006.257.11:03:09.37#ibcon#about to read 6, iclass 33, count 0 2006.257.11:03:09.37#ibcon#read 6, iclass 33, count 0 2006.257.11:03:09.37#ibcon#end of sib2, iclass 33, count 0 2006.257.11:03:09.37#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:03:09.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:03:09.37#ibcon#[27=USB\r\n] 2006.257.11:03:09.37#ibcon#*before write, iclass 33, count 0 2006.257.11:03:09.37#ibcon#enter sib2, iclass 33, count 0 2006.257.11:03:09.37#ibcon#flushed, iclass 33, count 0 2006.257.11:03:09.37#ibcon#about to write, iclass 33, count 0 2006.257.11:03:09.37#ibcon#wrote, iclass 33, count 0 2006.257.11:03:09.37#ibcon#about to read 3, iclass 33, count 0 2006.257.11:03:09.40#ibcon#read 3, iclass 33, count 0 2006.257.11:03:09.40#ibcon#about to read 4, iclass 33, count 0 2006.257.11:03:09.40#ibcon#read 4, iclass 33, count 0 2006.257.11:03:09.40#ibcon#about to read 5, iclass 33, count 0 2006.257.11:03:09.40#ibcon#read 5, iclass 33, count 0 2006.257.11:03:09.40#ibcon#about to read 6, iclass 33, count 0 2006.257.11:03:09.40#ibcon#read 6, iclass 33, count 0 2006.257.11:03:09.40#ibcon#end of sib2, iclass 33, count 0 2006.257.11:03:09.40#ibcon#*after write, iclass 33, count 0 2006.257.11:03:09.40#ibcon#*before return 0, iclass 33, count 0 2006.257.11:03:09.40#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:09.40#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:03:09.40#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:03:09.40#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:03:09.40$vck44/vblo=5,709.99 2006.257.11:03:09.40#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.11:03:09.40#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.11:03:09.40#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:09.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:09.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:09.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:09.40#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:03:09.40#ibcon#first serial, iclass 35, count 0 2006.257.11:03:09.40#ibcon#enter sib2, iclass 35, count 0 2006.257.11:03:09.40#ibcon#flushed, iclass 35, count 0 2006.257.11:03:09.40#ibcon#about to write, iclass 35, count 0 2006.257.11:03:09.40#ibcon#wrote, iclass 35, count 0 2006.257.11:03:09.40#ibcon#about to read 3, iclass 35, count 0 2006.257.11:03:09.42#ibcon#read 3, iclass 35, count 0 2006.257.11:03:09.42#ibcon#about to read 4, iclass 35, count 0 2006.257.11:03:09.42#ibcon#read 4, iclass 35, count 0 2006.257.11:03:09.42#ibcon#about to read 5, iclass 35, count 0 2006.257.11:03:09.42#ibcon#read 5, iclass 35, count 0 2006.257.11:03:09.42#ibcon#about to read 6, iclass 35, count 0 2006.257.11:03:09.42#ibcon#read 6, iclass 35, count 0 2006.257.11:03:09.42#ibcon#end of sib2, iclass 35, count 0 2006.257.11:03:09.42#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:03:09.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:03:09.42#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:03:09.42#ibcon#*before write, iclass 35, count 0 2006.257.11:03:09.42#ibcon#enter sib2, iclass 35, count 0 2006.257.11:03:09.42#ibcon#flushed, iclass 35, count 0 2006.257.11:03:09.42#ibcon#about to write, iclass 35, count 0 2006.257.11:03:09.42#ibcon#wrote, iclass 35, count 0 2006.257.11:03:09.42#ibcon#about to read 3, iclass 35, count 0 2006.257.11:03:09.46#ibcon#read 3, iclass 35, count 0 2006.257.11:03:09.46#ibcon#about to read 4, iclass 35, count 0 2006.257.11:03:09.46#ibcon#read 4, iclass 35, count 0 2006.257.11:03:09.46#ibcon#about to read 5, iclass 35, count 0 2006.257.11:03:09.46#ibcon#read 5, iclass 35, count 0 2006.257.11:03:09.46#ibcon#about to read 6, iclass 35, count 0 2006.257.11:03:09.46#ibcon#read 6, iclass 35, count 0 2006.257.11:03:09.46#ibcon#end of sib2, iclass 35, count 0 2006.257.11:03:09.46#ibcon#*after write, iclass 35, count 0 2006.257.11:03:09.46#ibcon#*before return 0, iclass 35, count 0 2006.257.11:03:09.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:09.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:03:09.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:03:09.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:03:09.46$vck44/vb=5,4 2006.257.11:03:09.46#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.11:03:09.46#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.11:03:09.46#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:09.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:09.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:09.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:09.52#ibcon#enter wrdev, iclass 37, count 2 2006.257.11:03:09.52#ibcon#first serial, iclass 37, count 2 2006.257.11:03:09.52#ibcon#enter sib2, iclass 37, count 2 2006.257.11:03:09.52#ibcon#flushed, iclass 37, count 2 2006.257.11:03:09.52#ibcon#about to write, iclass 37, count 2 2006.257.11:03:09.52#ibcon#wrote, iclass 37, count 2 2006.257.11:03:09.52#ibcon#about to read 3, iclass 37, count 2 2006.257.11:03:09.54#ibcon#read 3, iclass 37, count 2 2006.257.11:03:09.54#ibcon#about to read 4, iclass 37, count 2 2006.257.11:03:09.54#ibcon#read 4, iclass 37, count 2 2006.257.11:03:09.54#ibcon#about to read 5, iclass 37, count 2 2006.257.11:03:09.54#ibcon#read 5, iclass 37, count 2 2006.257.11:03:09.54#ibcon#about to read 6, iclass 37, count 2 2006.257.11:03:09.54#ibcon#read 6, iclass 37, count 2 2006.257.11:03:09.54#ibcon#end of sib2, iclass 37, count 2 2006.257.11:03:09.54#ibcon#*mode == 0, iclass 37, count 2 2006.257.11:03:09.54#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.11:03:09.54#ibcon#[27=AT05-04\r\n] 2006.257.11:03:09.54#ibcon#*before write, iclass 37, count 2 2006.257.11:03:09.54#ibcon#enter sib2, iclass 37, count 2 2006.257.11:03:09.54#ibcon#flushed, iclass 37, count 2 2006.257.11:03:09.54#ibcon#about to write, iclass 37, count 2 2006.257.11:03:09.54#ibcon#wrote, iclass 37, count 2 2006.257.11:03:09.54#ibcon#about to read 3, iclass 37, count 2 2006.257.11:03:09.57#ibcon#read 3, iclass 37, count 2 2006.257.11:03:09.57#ibcon#about to read 4, iclass 37, count 2 2006.257.11:03:09.57#ibcon#read 4, iclass 37, count 2 2006.257.11:03:09.57#ibcon#about to read 5, iclass 37, count 2 2006.257.11:03:09.57#ibcon#read 5, iclass 37, count 2 2006.257.11:03:09.57#ibcon#about to read 6, iclass 37, count 2 2006.257.11:03:09.57#ibcon#read 6, iclass 37, count 2 2006.257.11:03:09.57#ibcon#end of sib2, iclass 37, count 2 2006.257.11:03:09.57#ibcon#*after write, iclass 37, count 2 2006.257.11:03:09.57#ibcon#*before return 0, iclass 37, count 2 2006.257.11:03:09.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:09.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:03:09.57#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.11:03:09.57#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:09.57#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:09.69#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:09.69#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:09.69#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:03:09.69#ibcon#first serial, iclass 37, count 0 2006.257.11:03:09.69#ibcon#enter sib2, iclass 37, count 0 2006.257.11:03:09.69#ibcon#flushed, iclass 37, count 0 2006.257.11:03:09.69#ibcon#about to write, iclass 37, count 0 2006.257.11:03:09.69#ibcon#wrote, iclass 37, count 0 2006.257.11:03:09.69#ibcon#about to read 3, iclass 37, count 0 2006.257.11:03:09.71#ibcon#read 3, iclass 37, count 0 2006.257.11:03:09.71#ibcon#about to read 4, iclass 37, count 0 2006.257.11:03:09.71#ibcon#read 4, iclass 37, count 0 2006.257.11:03:09.71#ibcon#about to read 5, iclass 37, count 0 2006.257.11:03:09.71#ibcon#read 5, iclass 37, count 0 2006.257.11:03:09.71#ibcon#about to read 6, iclass 37, count 0 2006.257.11:03:09.71#ibcon#read 6, iclass 37, count 0 2006.257.11:03:09.71#ibcon#end of sib2, iclass 37, count 0 2006.257.11:03:09.71#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:03:09.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:03:09.71#ibcon#[27=USB\r\n] 2006.257.11:03:09.71#ibcon#*before write, iclass 37, count 0 2006.257.11:03:09.71#ibcon#enter sib2, iclass 37, count 0 2006.257.11:03:09.71#ibcon#flushed, iclass 37, count 0 2006.257.11:03:09.71#ibcon#about to write, iclass 37, count 0 2006.257.11:03:09.71#ibcon#wrote, iclass 37, count 0 2006.257.11:03:09.71#ibcon#about to read 3, iclass 37, count 0 2006.257.11:03:09.74#ibcon#read 3, iclass 37, count 0 2006.257.11:03:09.74#ibcon#about to read 4, iclass 37, count 0 2006.257.11:03:09.74#ibcon#read 4, iclass 37, count 0 2006.257.11:03:09.74#ibcon#about to read 5, iclass 37, count 0 2006.257.11:03:09.74#ibcon#read 5, iclass 37, count 0 2006.257.11:03:09.74#ibcon#about to read 6, iclass 37, count 0 2006.257.11:03:09.74#ibcon#read 6, iclass 37, count 0 2006.257.11:03:09.74#ibcon#end of sib2, iclass 37, count 0 2006.257.11:03:09.74#ibcon#*after write, iclass 37, count 0 2006.257.11:03:09.74#ibcon#*before return 0, iclass 37, count 0 2006.257.11:03:09.74#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:09.74#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:03:09.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:03:09.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:03:09.74$vck44/vblo=6,719.99 2006.257.11:03:09.74#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.11:03:09.74#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.11:03:09.74#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:09.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:09.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:09.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:09.74#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:03:09.74#ibcon#first serial, iclass 39, count 0 2006.257.11:03:09.74#ibcon#enter sib2, iclass 39, count 0 2006.257.11:03:09.74#ibcon#flushed, iclass 39, count 0 2006.257.11:03:09.74#ibcon#about to write, iclass 39, count 0 2006.257.11:03:09.74#ibcon#wrote, iclass 39, count 0 2006.257.11:03:09.74#ibcon#about to read 3, iclass 39, count 0 2006.257.11:03:09.76#ibcon#read 3, iclass 39, count 0 2006.257.11:03:09.76#ibcon#about to read 4, iclass 39, count 0 2006.257.11:03:09.76#ibcon#read 4, iclass 39, count 0 2006.257.11:03:09.76#ibcon#about to read 5, iclass 39, count 0 2006.257.11:03:09.76#ibcon#read 5, iclass 39, count 0 2006.257.11:03:09.76#ibcon#about to read 6, iclass 39, count 0 2006.257.11:03:09.76#ibcon#read 6, iclass 39, count 0 2006.257.11:03:09.76#ibcon#end of sib2, iclass 39, count 0 2006.257.11:03:09.76#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:03:09.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:03:09.76#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:03:09.76#ibcon#*before write, iclass 39, count 0 2006.257.11:03:09.76#ibcon#enter sib2, iclass 39, count 0 2006.257.11:03:09.76#ibcon#flushed, iclass 39, count 0 2006.257.11:03:09.76#ibcon#about to write, iclass 39, count 0 2006.257.11:03:09.76#ibcon#wrote, iclass 39, count 0 2006.257.11:03:09.76#ibcon#about to read 3, iclass 39, count 0 2006.257.11:03:09.80#ibcon#read 3, iclass 39, count 0 2006.257.11:03:09.80#ibcon#about to read 4, iclass 39, count 0 2006.257.11:03:09.80#ibcon#read 4, iclass 39, count 0 2006.257.11:03:09.80#ibcon#about to read 5, iclass 39, count 0 2006.257.11:03:09.80#ibcon#read 5, iclass 39, count 0 2006.257.11:03:09.80#ibcon#about to read 6, iclass 39, count 0 2006.257.11:03:09.80#ibcon#read 6, iclass 39, count 0 2006.257.11:03:09.80#ibcon#end of sib2, iclass 39, count 0 2006.257.11:03:09.80#ibcon#*after write, iclass 39, count 0 2006.257.11:03:09.80#ibcon#*before return 0, iclass 39, count 0 2006.257.11:03:09.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:09.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:03:09.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:03:09.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:03:09.80$vck44/vb=6,4 2006.257.11:03:09.80#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.11:03:09.80#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.11:03:09.80#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:09.80#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:09.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:09.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:09.86#ibcon#enter wrdev, iclass 3, count 2 2006.257.11:03:09.86#ibcon#first serial, iclass 3, count 2 2006.257.11:03:09.86#ibcon#enter sib2, iclass 3, count 2 2006.257.11:03:09.86#ibcon#flushed, iclass 3, count 2 2006.257.11:03:09.86#ibcon#about to write, iclass 3, count 2 2006.257.11:03:09.86#ibcon#wrote, iclass 3, count 2 2006.257.11:03:09.86#ibcon#about to read 3, iclass 3, count 2 2006.257.11:03:09.88#ibcon#read 3, iclass 3, count 2 2006.257.11:03:09.88#ibcon#about to read 4, iclass 3, count 2 2006.257.11:03:09.88#ibcon#read 4, iclass 3, count 2 2006.257.11:03:09.88#ibcon#about to read 5, iclass 3, count 2 2006.257.11:03:09.88#ibcon#read 5, iclass 3, count 2 2006.257.11:03:09.88#ibcon#about to read 6, iclass 3, count 2 2006.257.11:03:09.88#ibcon#read 6, iclass 3, count 2 2006.257.11:03:09.88#ibcon#end of sib2, iclass 3, count 2 2006.257.11:03:09.88#ibcon#*mode == 0, iclass 3, count 2 2006.257.11:03:09.88#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.11:03:09.88#ibcon#[27=AT06-04\r\n] 2006.257.11:03:09.88#ibcon#*before write, iclass 3, count 2 2006.257.11:03:09.88#ibcon#enter sib2, iclass 3, count 2 2006.257.11:03:09.88#ibcon#flushed, iclass 3, count 2 2006.257.11:03:09.88#ibcon#about to write, iclass 3, count 2 2006.257.11:03:09.88#ibcon#wrote, iclass 3, count 2 2006.257.11:03:09.88#ibcon#about to read 3, iclass 3, count 2 2006.257.11:03:09.91#ibcon#read 3, iclass 3, count 2 2006.257.11:03:09.91#ibcon#about to read 4, iclass 3, count 2 2006.257.11:03:09.91#ibcon#read 4, iclass 3, count 2 2006.257.11:03:09.91#ibcon#about to read 5, iclass 3, count 2 2006.257.11:03:09.91#ibcon#read 5, iclass 3, count 2 2006.257.11:03:09.91#ibcon#about to read 6, iclass 3, count 2 2006.257.11:03:09.91#ibcon#read 6, iclass 3, count 2 2006.257.11:03:09.91#ibcon#end of sib2, iclass 3, count 2 2006.257.11:03:09.91#ibcon#*after write, iclass 3, count 2 2006.257.11:03:09.91#ibcon#*before return 0, iclass 3, count 2 2006.257.11:03:09.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:09.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:03:09.91#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.11:03:09.91#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:09.91#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:10.03#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:10.03#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:10.03#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:03:10.03#ibcon#first serial, iclass 3, count 0 2006.257.11:03:10.03#ibcon#enter sib2, iclass 3, count 0 2006.257.11:03:10.03#ibcon#flushed, iclass 3, count 0 2006.257.11:03:10.03#ibcon#about to write, iclass 3, count 0 2006.257.11:03:10.03#ibcon#wrote, iclass 3, count 0 2006.257.11:03:10.03#ibcon#about to read 3, iclass 3, count 0 2006.257.11:03:10.05#ibcon#read 3, iclass 3, count 0 2006.257.11:03:10.05#ibcon#about to read 4, iclass 3, count 0 2006.257.11:03:10.05#ibcon#read 4, iclass 3, count 0 2006.257.11:03:10.05#ibcon#about to read 5, iclass 3, count 0 2006.257.11:03:10.05#ibcon#read 5, iclass 3, count 0 2006.257.11:03:10.05#ibcon#about to read 6, iclass 3, count 0 2006.257.11:03:10.05#ibcon#read 6, iclass 3, count 0 2006.257.11:03:10.05#ibcon#end of sib2, iclass 3, count 0 2006.257.11:03:10.05#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:03:10.05#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:03:10.05#ibcon#[27=USB\r\n] 2006.257.11:03:10.05#ibcon#*before write, iclass 3, count 0 2006.257.11:03:10.05#ibcon#enter sib2, iclass 3, count 0 2006.257.11:03:10.05#ibcon#flushed, iclass 3, count 0 2006.257.11:03:10.05#ibcon#about to write, iclass 3, count 0 2006.257.11:03:10.05#ibcon#wrote, iclass 3, count 0 2006.257.11:03:10.05#ibcon#about to read 3, iclass 3, count 0 2006.257.11:03:10.08#ibcon#read 3, iclass 3, count 0 2006.257.11:03:10.08#ibcon#about to read 4, iclass 3, count 0 2006.257.11:03:10.08#ibcon#read 4, iclass 3, count 0 2006.257.11:03:10.08#ibcon#about to read 5, iclass 3, count 0 2006.257.11:03:10.08#ibcon#read 5, iclass 3, count 0 2006.257.11:03:10.08#ibcon#about to read 6, iclass 3, count 0 2006.257.11:03:10.08#ibcon#read 6, iclass 3, count 0 2006.257.11:03:10.08#ibcon#end of sib2, iclass 3, count 0 2006.257.11:03:10.08#ibcon#*after write, iclass 3, count 0 2006.257.11:03:10.08#ibcon#*before return 0, iclass 3, count 0 2006.257.11:03:10.08#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:10.08#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:03:10.08#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:03:10.08#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:03:10.08$vck44/vblo=7,734.99 2006.257.11:03:10.08#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.11:03:10.08#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.11:03:10.08#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:10.08#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:10.08#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:10.08#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:10.08#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:03:10.08#ibcon#first serial, iclass 5, count 0 2006.257.11:03:10.08#ibcon#enter sib2, iclass 5, count 0 2006.257.11:03:10.08#ibcon#flushed, iclass 5, count 0 2006.257.11:03:10.08#ibcon#about to write, iclass 5, count 0 2006.257.11:03:10.08#ibcon#wrote, iclass 5, count 0 2006.257.11:03:10.08#ibcon#about to read 3, iclass 5, count 0 2006.257.11:03:10.10#ibcon#read 3, iclass 5, count 0 2006.257.11:03:10.10#ibcon#about to read 4, iclass 5, count 0 2006.257.11:03:10.10#ibcon#read 4, iclass 5, count 0 2006.257.11:03:10.10#ibcon#about to read 5, iclass 5, count 0 2006.257.11:03:10.10#ibcon#read 5, iclass 5, count 0 2006.257.11:03:10.10#ibcon#about to read 6, iclass 5, count 0 2006.257.11:03:10.10#ibcon#read 6, iclass 5, count 0 2006.257.11:03:10.10#ibcon#end of sib2, iclass 5, count 0 2006.257.11:03:10.10#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:03:10.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:03:10.10#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:03:10.10#ibcon#*before write, iclass 5, count 0 2006.257.11:03:10.10#ibcon#enter sib2, iclass 5, count 0 2006.257.11:03:10.10#ibcon#flushed, iclass 5, count 0 2006.257.11:03:10.10#ibcon#about to write, iclass 5, count 0 2006.257.11:03:10.10#ibcon#wrote, iclass 5, count 0 2006.257.11:03:10.10#ibcon#about to read 3, iclass 5, count 0 2006.257.11:03:10.14#ibcon#read 3, iclass 5, count 0 2006.257.11:03:10.14#ibcon#about to read 4, iclass 5, count 0 2006.257.11:03:10.14#ibcon#read 4, iclass 5, count 0 2006.257.11:03:10.14#ibcon#about to read 5, iclass 5, count 0 2006.257.11:03:10.14#ibcon#read 5, iclass 5, count 0 2006.257.11:03:10.14#ibcon#about to read 6, iclass 5, count 0 2006.257.11:03:10.14#ibcon#read 6, iclass 5, count 0 2006.257.11:03:10.14#ibcon#end of sib2, iclass 5, count 0 2006.257.11:03:10.14#ibcon#*after write, iclass 5, count 0 2006.257.11:03:10.14#ibcon#*before return 0, iclass 5, count 0 2006.257.11:03:10.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:10.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:03:10.14#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:03:10.14#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:03:10.14$vck44/vb=7,4 2006.257.11:03:10.14#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.11:03:10.14#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.11:03:10.14#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:10.14#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:10.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:10.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:10.20#ibcon#enter wrdev, iclass 7, count 2 2006.257.11:03:10.20#ibcon#first serial, iclass 7, count 2 2006.257.11:03:10.20#ibcon#enter sib2, iclass 7, count 2 2006.257.11:03:10.20#ibcon#flushed, iclass 7, count 2 2006.257.11:03:10.20#ibcon#about to write, iclass 7, count 2 2006.257.11:03:10.20#ibcon#wrote, iclass 7, count 2 2006.257.11:03:10.20#ibcon#about to read 3, iclass 7, count 2 2006.257.11:03:10.22#ibcon#read 3, iclass 7, count 2 2006.257.11:03:10.22#ibcon#about to read 4, iclass 7, count 2 2006.257.11:03:10.22#ibcon#read 4, iclass 7, count 2 2006.257.11:03:10.22#ibcon#about to read 5, iclass 7, count 2 2006.257.11:03:10.22#ibcon#read 5, iclass 7, count 2 2006.257.11:03:10.22#ibcon#about to read 6, iclass 7, count 2 2006.257.11:03:10.22#ibcon#read 6, iclass 7, count 2 2006.257.11:03:10.22#ibcon#end of sib2, iclass 7, count 2 2006.257.11:03:10.22#ibcon#*mode == 0, iclass 7, count 2 2006.257.11:03:10.22#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.11:03:10.22#ibcon#[27=AT07-04\r\n] 2006.257.11:03:10.22#ibcon#*before write, iclass 7, count 2 2006.257.11:03:10.22#ibcon#enter sib2, iclass 7, count 2 2006.257.11:03:10.22#ibcon#flushed, iclass 7, count 2 2006.257.11:03:10.22#ibcon#about to write, iclass 7, count 2 2006.257.11:03:10.22#ibcon#wrote, iclass 7, count 2 2006.257.11:03:10.22#ibcon#about to read 3, iclass 7, count 2 2006.257.11:03:10.25#ibcon#read 3, iclass 7, count 2 2006.257.11:03:10.25#ibcon#about to read 4, iclass 7, count 2 2006.257.11:03:10.25#ibcon#read 4, iclass 7, count 2 2006.257.11:03:10.25#ibcon#about to read 5, iclass 7, count 2 2006.257.11:03:10.25#ibcon#read 5, iclass 7, count 2 2006.257.11:03:10.25#ibcon#about to read 6, iclass 7, count 2 2006.257.11:03:10.25#ibcon#read 6, iclass 7, count 2 2006.257.11:03:10.25#ibcon#end of sib2, iclass 7, count 2 2006.257.11:03:10.25#ibcon#*after write, iclass 7, count 2 2006.257.11:03:10.25#ibcon#*before return 0, iclass 7, count 2 2006.257.11:03:10.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:10.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:03:10.25#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.11:03:10.25#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:10.25#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:10.37#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:10.37#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:10.37#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:03:10.37#ibcon#first serial, iclass 7, count 0 2006.257.11:03:10.37#ibcon#enter sib2, iclass 7, count 0 2006.257.11:03:10.37#ibcon#flushed, iclass 7, count 0 2006.257.11:03:10.37#ibcon#about to write, iclass 7, count 0 2006.257.11:03:10.37#ibcon#wrote, iclass 7, count 0 2006.257.11:03:10.37#ibcon#about to read 3, iclass 7, count 0 2006.257.11:03:10.39#ibcon#read 3, iclass 7, count 0 2006.257.11:03:10.39#ibcon#about to read 4, iclass 7, count 0 2006.257.11:03:10.39#ibcon#read 4, iclass 7, count 0 2006.257.11:03:10.39#ibcon#about to read 5, iclass 7, count 0 2006.257.11:03:10.39#ibcon#read 5, iclass 7, count 0 2006.257.11:03:10.39#ibcon#about to read 6, iclass 7, count 0 2006.257.11:03:10.39#ibcon#read 6, iclass 7, count 0 2006.257.11:03:10.39#ibcon#end of sib2, iclass 7, count 0 2006.257.11:03:10.39#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:03:10.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:03:10.39#ibcon#[27=USB\r\n] 2006.257.11:03:10.39#ibcon#*before write, iclass 7, count 0 2006.257.11:03:10.39#ibcon#enter sib2, iclass 7, count 0 2006.257.11:03:10.39#ibcon#flushed, iclass 7, count 0 2006.257.11:03:10.39#ibcon#about to write, iclass 7, count 0 2006.257.11:03:10.39#ibcon#wrote, iclass 7, count 0 2006.257.11:03:10.39#ibcon#about to read 3, iclass 7, count 0 2006.257.11:03:10.42#ibcon#read 3, iclass 7, count 0 2006.257.11:03:10.42#ibcon#about to read 4, iclass 7, count 0 2006.257.11:03:10.42#ibcon#read 4, iclass 7, count 0 2006.257.11:03:10.42#ibcon#about to read 5, iclass 7, count 0 2006.257.11:03:10.42#ibcon#read 5, iclass 7, count 0 2006.257.11:03:10.42#ibcon#about to read 6, iclass 7, count 0 2006.257.11:03:10.42#ibcon#read 6, iclass 7, count 0 2006.257.11:03:10.42#ibcon#end of sib2, iclass 7, count 0 2006.257.11:03:10.42#ibcon#*after write, iclass 7, count 0 2006.257.11:03:10.42#ibcon#*before return 0, iclass 7, count 0 2006.257.11:03:10.42#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:10.42#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:03:10.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:03:10.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:03:10.42$vck44/vblo=8,744.99 2006.257.11:03:10.42#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.11:03:10.42#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.11:03:10.42#ibcon#ireg 17 cls_cnt 0 2006.257.11:03:10.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:10.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:10.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:10.42#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:03:10.42#ibcon#first serial, iclass 11, count 0 2006.257.11:03:10.42#ibcon#enter sib2, iclass 11, count 0 2006.257.11:03:10.42#ibcon#flushed, iclass 11, count 0 2006.257.11:03:10.42#ibcon#about to write, iclass 11, count 0 2006.257.11:03:10.42#ibcon#wrote, iclass 11, count 0 2006.257.11:03:10.42#ibcon#about to read 3, iclass 11, count 0 2006.257.11:03:10.44#ibcon#read 3, iclass 11, count 0 2006.257.11:03:10.44#ibcon#about to read 4, iclass 11, count 0 2006.257.11:03:10.44#ibcon#read 4, iclass 11, count 0 2006.257.11:03:10.44#ibcon#about to read 5, iclass 11, count 0 2006.257.11:03:10.44#ibcon#read 5, iclass 11, count 0 2006.257.11:03:10.44#ibcon#about to read 6, iclass 11, count 0 2006.257.11:03:10.44#ibcon#read 6, iclass 11, count 0 2006.257.11:03:10.44#ibcon#end of sib2, iclass 11, count 0 2006.257.11:03:10.44#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:03:10.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:03:10.44#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:03:10.44#ibcon#*before write, iclass 11, count 0 2006.257.11:03:10.44#ibcon#enter sib2, iclass 11, count 0 2006.257.11:03:10.44#ibcon#flushed, iclass 11, count 0 2006.257.11:03:10.44#ibcon#about to write, iclass 11, count 0 2006.257.11:03:10.44#ibcon#wrote, iclass 11, count 0 2006.257.11:03:10.44#ibcon#about to read 3, iclass 11, count 0 2006.257.11:03:10.48#ibcon#read 3, iclass 11, count 0 2006.257.11:03:10.48#ibcon#about to read 4, iclass 11, count 0 2006.257.11:03:10.48#ibcon#read 4, iclass 11, count 0 2006.257.11:03:10.48#ibcon#about to read 5, iclass 11, count 0 2006.257.11:03:10.48#ibcon#read 5, iclass 11, count 0 2006.257.11:03:10.48#ibcon#about to read 6, iclass 11, count 0 2006.257.11:03:10.48#ibcon#read 6, iclass 11, count 0 2006.257.11:03:10.48#ibcon#end of sib2, iclass 11, count 0 2006.257.11:03:10.48#ibcon#*after write, iclass 11, count 0 2006.257.11:03:10.48#ibcon#*before return 0, iclass 11, count 0 2006.257.11:03:10.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:10.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:03:10.48#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:03:10.48#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:03:10.48$vck44/vb=8,4 2006.257.11:03:10.48#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.11:03:10.48#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.11:03:10.48#ibcon#ireg 11 cls_cnt 2 2006.257.11:03:10.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:10.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:10.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:10.54#ibcon#enter wrdev, iclass 13, count 2 2006.257.11:03:10.54#ibcon#first serial, iclass 13, count 2 2006.257.11:03:10.54#ibcon#enter sib2, iclass 13, count 2 2006.257.11:03:10.54#ibcon#flushed, iclass 13, count 2 2006.257.11:03:10.54#ibcon#about to write, iclass 13, count 2 2006.257.11:03:10.54#ibcon#wrote, iclass 13, count 2 2006.257.11:03:10.54#ibcon#about to read 3, iclass 13, count 2 2006.257.11:03:10.56#ibcon#read 3, iclass 13, count 2 2006.257.11:03:10.56#ibcon#about to read 4, iclass 13, count 2 2006.257.11:03:10.56#ibcon#read 4, iclass 13, count 2 2006.257.11:03:10.56#ibcon#about to read 5, iclass 13, count 2 2006.257.11:03:10.56#ibcon#read 5, iclass 13, count 2 2006.257.11:03:10.56#ibcon#about to read 6, iclass 13, count 2 2006.257.11:03:10.56#ibcon#read 6, iclass 13, count 2 2006.257.11:03:10.56#ibcon#end of sib2, iclass 13, count 2 2006.257.11:03:10.56#ibcon#*mode == 0, iclass 13, count 2 2006.257.11:03:10.56#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.11:03:10.56#ibcon#[27=AT08-04\r\n] 2006.257.11:03:10.56#ibcon#*before write, iclass 13, count 2 2006.257.11:03:10.56#ibcon#enter sib2, iclass 13, count 2 2006.257.11:03:10.56#ibcon#flushed, iclass 13, count 2 2006.257.11:03:10.56#ibcon#about to write, iclass 13, count 2 2006.257.11:03:10.56#ibcon#wrote, iclass 13, count 2 2006.257.11:03:10.56#ibcon#about to read 3, iclass 13, count 2 2006.257.11:03:10.59#ibcon#read 3, iclass 13, count 2 2006.257.11:03:10.59#ibcon#about to read 4, iclass 13, count 2 2006.257.11:03:10.59#ibcon#read 4, iclass 13, count 2 2006.257.11:03:10.59#ibcon#about to read 5, iclass 13, count 2 2006.257.11:03:10.59#ibcon#read 5, iclass 13, count 2 2006.257.11:03:10.59#ibcon#about to read 6, iclass 13, count 2 2006.257.11:03:10.59#ibcon#read 6, iclass 13, count 2 2006.257.11:03:10.59#ibcon#end of sib2, iclass 13, count 2 2006.257.11:03:10.59#ibcon#*after write, iclass 13, count 2 2006.257.11:03:10.59#ibcon#*before return 0, iclass 13, count 2 2006.257.11:03:10.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:10.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:03:10.59#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.11:03:10.59#ibcon#ireg 7 cls_cnt 0 2006.257.11:03:10.59#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:10.71#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:10.71#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:10.71#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:03:10.71#ibcon#first serial, iclass 13, count 0 2006.257.11:03:10.71#ibcon#enter sib2, iclass 13, count 0 2006.257.11:03:10.71#ibcon#flushed, iclass 13, count 0 2006.257.11:03:10.71#ibcon#about to write, iclass 13, count 0 2006.257.11:03:10.71#ibcon#wrote, iclass 13, count 0 2006.257.11:03:10.71#ibcon#about to read 3, iclass 13, count 0 2006.257.11:03:10.73#ibcon#read 3, iclass 13, count 0 2006.257.11:03:10.73#ibcon#about to read 4, iclass 13, count 0 2006.257.11:03:10.73#ibcon#read 4, iclass 13, count 0 2006.257.11:03:10.73#ibcon#about to read 5, iclass 13, count 0 2006.257.11:03:10.73#ibcon#read 5, iclass 13, count 0 2006.257.11:03:10.73#ibcon#about to read 6, iclass 13, count 0 2006.257.11:03:10.73#ibcon#read 6, iclass 13, count 0 2006.257.11:03:10.73#ibcon#end of sib2, iclass 13, count 0 2006.257.11:03:10.73#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:03:10.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:03:10.73#ibcon#[27=USB\r\n] 2006.257.11:03:10.73#ibcon#*before write, iclass 13, count 0 2006.257.11:03:10.73#ibcon#enter sib2, iclass 13, count 0 2006.257.11:03:10.73#ibcon#flushed, iclass 13, count 0 2006.257.11:03:10.73#ibcon#about to write, iclass 13, count 0 2006.257.11:03:10.73#ibcon#wrote, iclass 13, count 0 2006.257.11:03:10.73#ibcon#about to read 3, iclass 13, count 0 2006.257.11:03:10.76#ibcon#read 3, iclass 13, count 0 2006.257.11:03:10.76#ibcon#about to read 4, iclass 13, count 0 2006.257.11:03:10.76#ibcon#read 4, iclass 13, count 0 2006.257.11:03:10.76#ibcon#about to read 5, iclass 13, count 0 2006.257.11:03:10.76#ibcon#read 5, iclass 13, count 0 2006.257.11:03:10.76#ibcon#about to read 6, iclass 13, count 0 2006.257.11:03:10.76#ibcon#read 6, iclass 13, count 0 2006.257.11:03:10.76#ibcon#end of sib2, iclass 13, count 0 2006.257.11:03:10.76#ibcon#*after write, iclass 13, count 0 2006.257.11:03:10.76#ibcon#*before return 0, iclass 13, count 0 2006.257.11:03:10.76#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:10.76#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:03:10.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:03:10.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:03:10.76$vck44/vabw=wide 2006.257.11:03:10.76#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.11:03:10.76#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.11:03:10.76#ibcon#ireg 8 cls_cnt 0 2006.257.11:03:10.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:10.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:10.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:10.76#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:03:10.76#ibcon#first serial, iclass 15, count 0 2006.257.11:03:10.76#ibcon#enter sib2, iclass 15, count 0 2006.257.11:03:10.76#ibcon#flushed, iclass 15, count 0 2006.257.11:03:10.76#ibcon#about to write, iclass 15, count 0 2006.257.11:03:10.76#ibcon#wrote, iclass 15, count 0 2006.257.11:03:10.76#ibcon#about to read 3, iclass 15, count 0 2006.257.11:03:10.78#ibcon#read 3, iclass 15, count 0 2006.257.11:03:10.78#ibcon#about to read 4, iclass 15, count 0 2006.257.11:03:10.78#ibcon#read 4, iclass 15, count 0 2006.257.11:03:10.78#ibcon#about to read 5, iclass 15, count 0 2006.257.11:03:10.78#ibcon#read 5, iclass 15, count 0 2006.257.11:03:10.78#ibcon#about to read 6, iclass 15, count 0 2006.257.11:03:10.78#ibcon#read 6, iclass 15, count 0 2006.257.11:03:10.78#ibcon#end of sib2, iclass 15, count 0 2006.257.11:03:10.78#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:03:10.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:03:10.78#ibcon#[25=BW32\r\n] 2006.257.11:03:10.78#ibcon#*before write, iclass 15, count 0 2006.257.11:03:10.78#ibcon#enter sib2, iclass 15, count 0 2006.257.11:03:10.78#ibcon#flushed, iclass 15, count 0 2006.257.11:03:10.78#ibcon#about to write, iclass 15, count 0 2006.257.11:03:10.78#ibcon#wrote, iclass 15, count 0 2006.257.11:03:10.78#ibcon#about to read 3, iclass 15, count 0 2006.257.11:03:10.81#ibcon#read 3, iclass 15, count 0 2006.257.11:03:10.81#ibcon#about to read 4, iclass 15, count 0 2006.257.11:03:10.81#ibcon#read 4, iclass 15, count 0 2006.257.11:03:10.81#ibcon#about to read 5, iclass 15, count 0 2006.257.11:03:10.81#ibcon#read 5, iclass 15, count 0 2006.257.11:03:10.81#ibcon#about to read 6, iclass 15, count 0 2006.257.11:03:10.81#ibcon#read 6, iclass 15, count 0 2006.257.11:03:10.81#ibcon#end of sib2, iclass 15, count 0 2006.257.11:03:10.81#ibcon#*after write, iclass 15, count 0 2006.257.11:03:10.81#ibcon#*before return 0, iclass 15, count 0 2006.257.11:03:10.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:10.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:03:10.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:03:10.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:03:10.81$vck44/vbbw=wide 2006.257.11:03:10.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.11:03:10.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.11:03:10.81#ibcon#ireg 8 cls_cnt 0 2006.257.11:03:10.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:03:10.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:03:10.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:03:10.88#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:03:10.88#ibcon#first serial, iclass 17, count 0 2006.257.11:03:10.88#ibcon#enter sib2, iclass 17, count 0 2006.257.11:03:10.88#ibcon#flushed, iclass 17, count 0 2006.257.11:03:10.88#ibcon#about to write, iclass 17, count 0 2006.257.11:03:10.88#ibcon#wrote, iclass 17, count 0 2006.257.11:03:10.88#ibcon#about to read 3, iclass 17, count 0 2006.257.11:03:10.90#ibcon#read 3, iclass 17, count 0 2006.257.11:03:10.90#ibcon#about to read 4, iclass 17, count 0 2006.257.11:03:10.90#ibcon#read 4, iclass 17, count 0 2006.257.11:03:10.90#ibcon#about to read 5, iclass 17, count 0 2006.257.11:03:10.90#ibcon#read 5, iclass 17, count 0 2006.257.11:03:10.90#ibcon#about to read 6, iclass 17, count 0 2006.257.11:03:10.90#ibcon#read 6, iclass 17, count 0 2006.257.11:03:10.90#ibcon#end of sib2, iclass 17, count 0 2006.257.11:03:10.90#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:03:10.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:03:10.90#ibcon#[27=BW32\r\n] 2006.257.11:03:10.90#ibcon#*before write, iclass 17, count 0 2006.257.11:03:10.90#ibcon#enter sib2, iclass 17, count 0 2006.257.11:03:10.90#ibcon#flushed, iclass 17, count 0 2006.257.11:03:10.90#ibcon#about to write, iclass 17, count 0 2006.257.11:03:10.90#ibcon#wrote, iclass 17, count 0 2006.257.11:03:10.90#ibcon#about to read 3, iclass 17, count 0 2006.257.11:03:10.93#ibcon#read 3, iclass 17, count 0 2006.257.11:03:10.93#ibcon#about to read 4, iclass 17, count 0 2006.257.11:03:10.93#ibcon#read 4, iclass 17, count 0 2006.257.11:03:10.93#ibcon#about to read 5, iclass 17, count 0 2006.257.11:03:10.93#ibcon#read 5, iclass 17, count 0 2006.257.11:03:10.93#ibcon#about to read 6, iclass 17, count 0 2006.257.11:03:10.93#ibcon#read 6, iclass 17, count 0 2006.257.11:03:10.93#ibcon#end of sib2, iclass 17, count 0 2006.257.11:03:10.93#ibcon#*after write, iclass 17, count 0 2006.257.11:03:10.93#ibcon#*before return 0, iclass 17, count 0 2006.257.11:03:10.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:03:10.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:03:10.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:03:10.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:03:10.93$setupk4/ifdk4 2006.257.11:03:10.93$ifdk4/lo= 2006.257.11:03:10.93$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:03:10.93$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:03:10.93$ifdk4/patch= 2006.257.11:03:10.93$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:03:10.93$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:03:10.93$setupk4/!*+20s 2006.257.11:03:13.00#abcon#<5=/14 1.6 4.1 18.59 961014.2\r\n> 2006.257.11:03:13.02#abcon#{5=INTERFACE CLEAR} 2006.257.11:03:13.08#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:03:23.17#abcon#<5=/14 1.6 4.1 18.59 961014.2\r\n> 2006.257.11:03:23.19#abcon#{5=INTERFACE CLEAR} 2006.257.11:03:23.25#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:03:25.36$setupk4/"tpicd 2006.257.11:03:25.36$setupk4/echo=off 2006.257.11:03:25.36$setupk4/xlog=off 2006.257.11:03:25.36:!2006.257.11:06:15 2006.257.11:03:53.14#trakl#Source acquired 2006.257.11:03:54.14#flagr#flagr/antenna,acquired 2006.257.11:06:15.00:preob 2006.257.11:06:16.13/onsource/TRACKING 2006.257.11:06:16.13:!2006.257.11:06:25 2006.257.11:06:25.00:"tape 2006.257.11:06:25.00:"st=record 2006.257.11:06:25.00:data_valid=on 2006.257.11:06:25.00:midob 2006.257.11:06:25.13/onsource/TRACKING 2006.257.11:06:25.13/wx/18.56,1014.1,96 2006.257.11:06:25.28/cable/+6.4781E-03 2006.257.11:06:26.37/va/01,08,usb,yes,30,32 2006.257.11:06:26.37/va/02,07,usb,yes,33,33 2006.257.11:06:26.37/va/03,08,usb,yes,29,31 2006.257.11:06:26.37/va/04,07,usb,yes,33,35 2006.257.11:06:26.37/va/05,04,usb,yes,30,30 2006.257.11:06:26.37/va/06,04,usb,yes,33,33 2006.257.11:06:26.37/va/07,04,usb,yes,34,35 2006.257.11:06:26.37/va/08,04,usb,yes,28,35 2006.257.11:06:26.60/valo/01,524.99,yes,locked 2006.257.11:06:26.60/valo/02,534.99,yes,locked 2006.257.11:06:26.60/valo/03,564.99,yes,locked 2006.257.11:06:26.60/valo/04,624.99,yes,locked 2006.257.11:06:26.60/valo/05,734.99,yes,locked 2006.257.11:06:26.60/valo/06,814.99,yes,locked 2006.257.11:06:26.60/valo/07,864.99,yes,locked 2006.257.11:06:26.60/valo/08,884.99,yes,locked 2006.257.11:06:27.69/vb/01,04,usb,yes,30,28 2006.257.11:06:27.69/vb/02,05,usb,yes,29,28 2006.257.11:06:27.69/vb/03,04,usb,yes,29,32 2006.257.11:06:27.69/vb/04,05,usb,yes,30,29 2006.257.11:06:27.69/vb/05,04,usb,yes,26,29 2006.257.11:06:27.69/vb/06,04,usb,yes,31,27 2006.257.11:06:27.69/vb/07,04,usb,yes,30,30 2006.257.11:06:27.69/vb/08,04,usb,yes,28,31 2006.257.11:06:27.92/vblo/01,629.99,yes,locked 2006.257.11:06:27.92/vblo/02,634.99,yes,locked 2006.257.11:06:27.92/vblo/03,649.99,yes,locked 2006.257.11:06:27.92/vblo/04,679.99,yes,locked 2006.257.11:06:27.92/vblo/05,709.99,yes,locked 2006.257.11:06:27.92/vblo/06,719.99,yes,locked 2006.257.11:06:27.92/vblo/07,734.99,yes,locked 2006.257.11:06:27.92/vblo/08,744.99,yes,locked 2006.257.11:06:28.07/vabw/8 2006.257.11:06:28.22/vbbw/8 2006.257.11:06:28.31/xfe/off,on,15.2 2006.257.11:06:28.68/ifatt/23,28,28,28 2006.257.11:06:29.07/fmout-gps/S +4.62E-07 2006.257.11:06:29.11:!2006.257.11:07:45 2006.257.11:07:45.01:data_valid=off 2006.257.11:07:45.01:"et 2006.257.11:07:45.02:!+3s 2006.257.11:07:48.03:"tape 2006.257.11:07:48.03:postob 2006.257.11:07:48.16/cable/+6.4782E-03 2006.257.11:07:48.16/wx/18.54,1014.1,96 2006.257.11:07:48.22/fmout-gps/S +4.62E-07 2006.257.11:07:48.22:scan_name=257-1109,jd0609,110 2006.257.11:07:48.23:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.257.11:07:49.14#flagr#flagr/antenna,new-source 2006.257.11:07:49.14:checkk5 2006.257.11:07:49.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:07:49.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:07:50.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:07:50.78/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:07:51.17/chk_obsdata//k5ts1/T2571106??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.11:07:51.58/chk_obsdata//k5ts2/T2571106??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.11:07:51.98/chk_obsdata//k5ts3/T2571106??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.11:07:52.40/chk_obsdata//k5ts4/T2571106??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.11:07:53.13/k5log//k5ts1_log_newline 2006.257.11:07:53.83/k5log//k5ts2_log_newline 2006.257.11:07:54.52/k5log//k5ts3_log_newline 2006.257.11:07:55.25/k5log//k5ts4_log_newline 2006.257.11:07:55.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:07:55.28:setupk4=1 2006.257.11:07:55.28$setupk4/echo=on 2006.257.11:07:55.28$setupk4/pcalon 2006.257.11:07:55.28$pcalon/"no phase cal control is implemented here 2006.257.11:07:55.28$setupk4/"tpicd=stop 2006.257.11:07:55.28$setupk4/"rec=synch_on 2006.257.11:07:55.28$setupk4/"rec_mode=128 2006.257.11:07:55.28$setupk4/!* 2006.257.11:07:55.28$setupk4/recpk4 2006.257.11:07:55.28$recpk4/recpatch= 2006.257.11:07:55.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:07:55.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:07:55.28$setupk4/vck44 2006.257.11:07:55.28$vck44/valo=1,524.99 2006.257.11:07:55.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.11:07:55.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.11:07:55.28#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:55.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:55.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:55.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:55.28#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:07:55.28#ibcon#first serial, iclass 26, count 0 2006.257.11:07:55.28#ibcon#enter sib2, iclass 26, count 0 2006.257.11:07:55.28#ibcon#flushed, iclass 26, count 0 2006.257.11:07:55.28#ibcon#about to write, iclass 26, count 0 2006.257.11:07:55.28#ibcon#wrote, iclass 26, count 0 2006.257.11:07:55.28#ibcon#about to read 3, iclass 26, count 0 2006.257.11:07:55.30#ibcon#read 3, iclass 26, count 0 2006.257.11:07:55.30#ibcon#about to read 4, iclass 26, count 0 2006.257.11:07:55.30#ibcon#read 4, iclass 26, count 0 2006.257.11:07:55.30#ibcon#about to read 5, iclass 26, count 0 2006.257.11:07:55.30#ibcon#read 5, iclass 26, count 0 2006.257.11:07:55.30#ibcon#about to read 6, iclass 26, count 0 2006.257.11:07:55.30#ibcon#read 6, iclass 26, count 0 2006.257.11:07:55.30#ibcon#end of sib2, iclass 26, count 0 2006.257.11:07:55.30#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:07:55.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:07:55.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:07:55.30#ibcon#*before write, iclass 26, count 0 2006.257.11:07:55.30#ibcon#enter sib2, iclass 26, count 0 2006.257.11:07:55.30#ibcon#flushed, iclass 26, count 0 2006.257.11:07:55.30#ibcon#about to write, iclass 26, count 0 2006.257.11:07:55.30#ibcon#wrote, iclass 26, count 0 2006.257.11:07:55.30#ibcon#about to read 3, iclass 26, count 0 2006.257.11:07:55.35#ibcon#read 3, iclass 26, count 0 2006.257.11:07:55.35#ibcon#about to read 4, iclass 26, count 0 2006.257.11:07:55.35#ibcon#read 4, iclass 26, count 0 2006.257.11:07:55.35#ibcon#about to read 5, iclass 26, count 0 2006.257.11:07:55.35#ibcon#read 5, iclass 26, count 0 2006.257.11:07:55.35#ibcon#about to read 6, iclass 26, count 0 2006.257.11:07:55.35#ibcon#read 6, iclass 26, count 0 2006.257.11:07:55.35#ibcon#end of sib2, iclass 26, count 0 2006.257.11:07:55.35#ibcon#*after write, iclass 26, count 0 2006.257.11:07:55.35#ibcon#*before return 0, iclass 26, count 0 2006.257.11:07:55.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:55.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:55.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:07:55.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:07:55.35$vck44/va=1,8 2006.257.11:07:55.35#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.11:07:55.35#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.11:07:55.35#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:55.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:55.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:55.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:55.35#ibcon#enter wrdev, iclass 28, count 2 2006.257.11:07:55.35#ibcon#first serial, iclass 28, count 2 2006.257.11:07:55.35#ibcon#enter sib2, iclass 28, count 2 2006.257.11:07:55.35#ibcon#flushed, iclass 28, count 2 2006.257.11:07:55.35#ibcon#about to write, iclass 28, count 2 2006.257.11:07:55.35#ibcon#wrote, iclass 28, count 2 2006.257.11:07:55.35#ibcon#about to read 3, iclass 28, count 2 2006.257.11:07:55.37#ibcon#read 3, iclass 28, count 2 2006.257.11:07:55.37#ibcon#about to read 4, iclass 28, count 2 2006.257.11:07:55.37#ibcon#read 4, iclass 28, count 2 2006.257.11:07:55.37#ibcon#about to read 5, iclass 28, count 2 2006.257.11:07:55.37#ibcon#read 5, iclass 28, count 2 2006.257.11:07:55.37#ibcon#about to read 6, iclass 28, count 2 2006.257.11:07:55.37#ibcon#read 6, iclass 28, count 2 2006.257.11:07:55.37#ibcon#end of sib2, iclass 28, count 2 2006.257.11:07:55.37#ibcon#*mode == 0, iclass 28, count 2 2006.257.11:07:55.37#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.11:07:55.37#ibcon#[25=AT01-08\r\n] 2006.257.11:07:55.37#ibcon#*before write, iclass 28, count 2 2006.257.11:07:55.37#ibcon#enter sib2, iclass 28, count 2 2006.257.11:07:55.37#ibcon#flushed, iclass 28, count 2 2006.257.11:07:55.37#ibcon#about to write, iclass 28, count 2 2006.257.11:07:55.37#ibcon#wrote, iclass 28, count 2 2006.257.11:07:55.37#ibcon#about to read 3, iclass 28, count 2 2006.257.11:07:55.40#ibcon#read 3, iclass 28, count 2 2006.257.11:07:55.40#ibcon#about to read 4, iclass 28, count 2 2006.257.11:07:55.40#ibcon#read 4, iclass 28, count 2 2006.257.11:07:55.40#ibcon#about to read 5, iclass 28, count 2 2006.257.11:07:55.40#ibcon#read 5, iclass 28, count 2 2006.257.11:07:55.40#ibcon#about to read 6, iclass 28, count 2 2006.257.11:07:55.40#ibcon#read 6, iclass 28, count 2 2006.257.11:07:55.40#ibcon#end of sib2, iclass 28, count 2 2006.257.11:07:55.40#ibcon#*after write, iclass 28, count 2 2006.257.11:07:55.40#ibcon#*before return 0, iclass 28, count 2 2006.257.11:07:55.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:55.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:55.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.11:07:55.40#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:55.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:55.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:55.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:55.52#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:07:55.52#ibcon#first serial, iclass 28, count 0 2006.257.11:07:55.52#ibcon#enter sib2, iclass 28, count 0 2006.257.11:07:55.52#ibcon#flushed, iclass 28, count 0 2006.257.11:07:55.52#ibcon#about to write, iclass 28, count 0 2006.257.11:07:55.52#ibcon#wrote, iclass 28, count 0 2006.257.11:07:55.52#ibcon#about to read 3, iclass 28, count 0 2006.257.11:07:55.54#ibcon#read 3, iclass 28, count 0 2006.257.11:07:55.54#ibcon#about to read 4, iclass 28, count 0 2006.257.11:07:55.54#ibcon#read 4, iclass 28, count 0 2006.257.11:07:55.54#ibcon#about to read 5, iclass 28, count 0 2006.257.11:07:55.54#ibcon#read 5, iclass 28, count 0 2006.257.11:07:55.54#ibcon#about to read 6, iclass 28, count 0 2006.257.11:07:55.54#ibcon#read 6, iclass 28, count 0 2006.257.11:07:55.54#ibcon#end of sib2, iclass 28, count 0 2006.257.11:07:55.54#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:07:55.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:07:55.54#ibcon#[25=USB\r\n] 2006.257.11:07:55.54#ibcon#*before write, iclass 28, count 0 2006.257.11:07:55.54#ibcon#enter sib2, iclass 28, count 0 2006.257.11:07:55.54#ibcon#flushed, iclass 28, count 0 2006.257.11:07:55.54#ibcon#about to write, iclass 28, count 0 2006.257.11:07:55.54#ibcon#wrote, iclass 28, count 0 2006.257.11:07:55.54#ibcon#about to read 3, iclass 28, count 0 2006.257.11:07:55.57#ibcon#read 3, iclass 28, count 0 2006.257.11:07:55.57#ibcon#about to read 4, iclass 28, count 0 2006.257.11:07:55.57#ibcon#read 4, iclass 28, count 0 2006.257.11:07:55.57#ibcon#about to read 5, iclass 28, count 0 2006.257.11:07:55.57#ibcon#read 5, iclass 28, count 0 2006.257.11:07:55.57#ibcon#about to read 6, iclass 28, count 0 2006.257.11:07:55.57#ibcon#read 6, iclass 28, count 0 2006.257.11:07:55.57#ibcon#end of sib2, iclass 28, count 0 2006.257.11:07:55.57#ibcon#*after write, iclass 28, count 0 2006.257.11:07:55.57#ibcon#*before return 0, iclass 28, count 0 2006.257.11:07:55.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:55.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:55.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:07:55.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:07:55.57$vck44/valo=2,534.99 2006.257.11:07:55.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.11:07:55.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.11:07:55.57#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:55.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:55.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:55.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:55.57#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:07:55.57#ibcon#first serial, iclass 30, count 0 2006.257.11:07:55.57#ibcon#enter sib2, iclass 30, count 0 2006.257.11:07:55.57#ibcon#flushed, iclass 30, count 0 2006.257.11:07:55.57#ibcon#about to write, iclass 30, count 0 2006.257.11:07:55.57#ibcon#wrote, iclass 30, count 0 2006.257.11:07:55.57#ibcon#about to read 3, iclass 30, count 0 2006.257.11:07:55.59#ibcon#read 3, iclass 30, count 0 2006.257.11:07:55.59#ibcon#about to read 4, iclass 30, count 0 2006.257.11:07:55.59#ibcon#read 4, iclass 30, count 0 2006.257.11:07:55.59#ibcon#about to read 5, iclass 30, count 0 2006.257.11:07:55.59#ibcon#read 5, iclass 30, count 0 2006.257.11:07:55.59#ibcon#about to read 6, iclass 30, count 0 2006.257.11:07:55.59#ibcon#read 6, iclass 30, count 0 2006.257.11:07:55.59#ibcon#end of sib2, iclass 30, count 0 2006.257.11:07:55.59#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:07:55.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:07:55.59#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:07:55.59#ibcon#*before write, iclass 30, count 0 2006.257.11:07:55.59#ibcon#enter sib2, iclass 30, count 0 2006.257.11:07:55.59#ibcon#flushed, iclass 30, count 0 2006.257.11:07:55.59#ibcon#about to write, iclass 30, count 0 2006.257.11:07:55.59#ibcon#wrote, iclass 30, count 0 2006.257.11:07:55.59#ibcon#about to read 3, iclass 30, count 0 2006.257.11:07:55.63#ibcon#read 3, iclass 30, count 0 2006.257.11:07:55.63#ibcon#about to read 4, iclass 30, count 0 2006.257.11:07:55.63#ibcon#read 4, iclass 30, count 0 2006.257.11:07:55.63#ibcon#about to read 5, iclass 30, count 0 2006.257.11:07:55.63#ibcon#read 5, iclass 30, count 0 2006.257.11:07:55.63#ibcon#about to read 6, iclass 30, count 0 2006.257.11:07:55.63#ibcon#read 6, iclass 30, count 0 2006.257.11:07:55.63#ibcon#end of sib2, iclass 30, count 0 2006.257.11:07:55.63#ibcon#*after write, iclass 30, count 0 2006.257.11:07:55.63#ibcon#*before return 0, iclass 30, count 0 2006.257.11:07:55.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:55.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:55.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:07:55.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:07:55.63$vck44/va=2,7 2006.257.11:07:55.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.11:07:55.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.11:07:55.63#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:55.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:55.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:55.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:55.69#ibcon#enter wrdev, iclass 32, count 2 2006.257.11:07:55.69#ibcon#first serial, iclass 32, count 2 2006.257.11:07:55.69#ibcon#enter sib2, iclass 32, count 2 2006.257.11:07:55.69#ibcon#flushed, iclass 32, count 2 2006.257.11:07:55.69#ibcon#about to write, iclass 32, count 2 2006.257.11:07:55.69#ibcon#wrote, iclass 32, count 2 2006.257.11:07:55.69#ibcon#about to read 3, iclass 32, count 2 2006.257.11:07:55.71#ibcon#read 3, iclass 32, count 2 2006.257.11:07:55.71#ibcon#about to read 4, iclass 32, count 2 2006.257.11:07:55.71#ibcon#read 4, iclass 32, count 2 2006.257.11:07:55.71#ibcon#about to read 5, iclass 32, count 2 2006.257.11:07:55.71#ibcon#read 5, iclass 32, count 2 2006.257.11:07:55.71#ibcon#about to read 6, iclass 32, count 2 2006.257.11:07:55.71#ibcon#read 6, iclass 32, count 2 2006.257.11:07:55.71#ibcon#end of sib2, iclass 32, count 2 2006.257.11:07:55.71#ibcon#*mode == 0, iclass 32, count 2 2006.257.11:07:55.71#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.11:07:55.71#ibcon#[25=AT02-07\r\n] 2006.257.11:07:55.71#ibcon#*before write, iclass 32, count 2 2006.257.11:07:55.71#ibcon#enter sib2, iclass 32, count 2 2006.257.11:07:55.71#ibcon#flushed, iclass 32, count 2 2006.257.11:07:55.71#ibcon#about to write, iclass 32, count 2 2006.257.11:07:55.71#ibcon#wrote, iclass 32, count 2 2006.257.11:07:55.71#ibcon#about to read 3, iclass 32, count 2 2006.257.11:07:55.74#ibcon#read 3, iclass 32, count 2 2006.257.11:07:55.74#ibcon#about to read 4, iclass 32, count 2 2006.257.11:07:55.74#ibcon#read 4, iclass 32, count 2 2006.257.11:07:55.74#ibcon#about to read 5, iclass 32, count 2 2006.257.11:07:55.74#ibcon#read 5, iclass 32, count 2 2006.257.11:07:55.74#ibcon#about to read 6, iclass 32, count 2 2006.257.11:07:55.74#ibcon#read 6, iclass 32, count 2 2006.257.11:07:55.74#ibcon#end of sib2, iclass 32, count 2 2006.257.11:07:55.74#ibcon#*after write, iclass 32, count 2 2006.257.11:07:55.74#ibcon#*before return 0, iclass 32, count 2 2006.257.11:07:55.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:55.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:55.74#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.11:07:55.74#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:55.74#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:55.86#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:55.86#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:55.86#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:07:55.86#ibcon#first serial, iclass 32, count 0 2006.257.11:07:55.86#ibcon#enter sib2, iclass 32, count 0 2006.257.11:07:55.86#ibcon#flushed, iclass 32, count 0 2006.257.11:07:55.86#ibcon#about to write, iclass 32, count 0 2006.257.11:07:55.86#ibcon#wrote, iclass 32, count 0 2006.257.11:07:55.86#ibcon#about to read 3, iclass 32, count 0 2006.257.11:07:55.88#ibcon#read 3, iclass 32, count 0 2006.257.11:07:55.88#ibcon#about to read 4, iclass 32, count 0 2006.257.11:07:55.88#ibcon#read 4, iclass 32, count 0 2006.257.11:07:55.88#ibcon#about to read 5, iclass 32, count 0 2006.257.11:07:55.88#ibcon#read 5, iclass 32, count 0 2006.257.11:07:55.88#ibcon#about to read 6, iclass 32, count 0 2006.257.11:07:55.88#ibcon#read 6, iclass 32, count 0 2006.257.11:07:55.88#ibcon#end of sib2, iclass 32, count 0 2006.257.11:07:55.88#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:07:55.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:07:55.88#ibcon#[25=USB\r\n] 2006.257.11:07:55.88#ibcon#*before write, iclass 32, count 0 2006.257.11:07:55.88#ibcon#enter sib2, iclass 32, count 0 2006.257.11:07:55.88#ibcon#flushed, iclass 32, count 0 2006.257.11:07:55.88#ibcon#about to write, iclass 32, count 0 2006.257.11:07:55.88#ibcon#wrote, iclass 32, count 0 2006.257.11:07:55.88#ibcon#about to read 3, iclass 32, count 0 2006.257.11:07:55.91#ibcon#read 3, iclass 32, count 0 2006.257.11:07:55.91#ibcon#about to read 4, iclass 32, count 0 2006.257.11:07:55.91#ibcon#read 4, iclass 32, count 0 2006.257.11:07:55.91#ibcon#about to read 5, iclass 32, count 0 2006.257.11:07:55.91#ibcon#read 5, iclass 32, count 0 2006.257.11:07:55.91#ibcon#about to read 6, iclass 32, count 0 2006.257.11:07:55.91#ibcon#read 6, iclass 32, count 0 2006.257.11:07:55.91#ibcon#end of sib2, iclass 32, count 0 2006.257.11:07:55.91#ibcon#*after write, iclass 32, count 0 2006.257.11:07:55.91#ibcon#*before return 0, iclass 32, count 0 2006.257.11:07:55.91#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:55.91#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:55.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:07:55.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:07:55.91$vck44/valo=3,564.99 2006.257.11:07:55.91#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.11:07:55.91#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.11:07:55.91#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:55.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:55.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:55.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:55.91#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:07:55.91#ibcon#first serial, iclass 34, count 0 2006.257.11:07:55.91#ibcon#enter sib2, iclass 34, count 0 2006.257.11:07:55.91#ibcon#flushed, iclass 34, count 0 2006.257.11:07:55.91#ibcon#about to write, iclass 34, count 0 2006.257.11:07:55.91#ibcon#wrote, iclass 34, count 0 2006.257.11:07:55.91#ibcon#about to read 3, iclass 34, count 0 2006.257.11:07:55.93#ibcon#read 3, iclass 34, count 0 2006.257.11:07:55.93#ibcon#about to read 4, iclass 34, count 0 2006.257.11:07:55.93#ibcon#read 4, iclass 34, count 0 2006.257.11:07:55.93#ibcon#about to read 5, iclass 34, count 0 2006.257.11:07:55.93#ibcon#read 5, iclass 34, count 0 2006.257.11:07:55.93#ibcon#about to read 6, iclass 34, count 0 2006.257.11:07:55.93#ibcon#read 6, iclass 34, count 0 2006.257.11:07:55.93#ibcon#end of sib2, iclass 34, count 0 2006.257.11:07:55.93#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:07:55.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:07:55.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:07:55.93#ibcon#*before write, iclass 34, count 0 2006.257.11:07:55.93#ibcon#enter sib2, iclass 34, count 0 2006.257.11:07:55.93#ibcon#flushed, iclass 34, count 0 2006.257.11:07:55.93#ibcon#about to write, iclass 34, count 0 2006.257.11:07:55.93#ibcon#wrote, iclass 34, count 0 2006.257.11:07:55.93#ibcon#about to read 3, iclass 34, count 0 2006.257.11:07:55.97#ibcon#read 3, iclass 34, count 0 2006.257.11:07:55.97#ibcon#about to read 4, iclass 34, count 0 2006.257.11:07:55.97#ibcon#read 4, iclass 34, count 0 2006.257.11:07:55.97#ibcon#about to read 5, iclass 34, count 0 2006.257.11:07:55.97#ibcon#read 5, iclass 34, count 0 2006.257.11:07:55.97#ibcon#about to read 6, iclass 34, count 0 2006.257.11:07:55.97#ibcon#read 6, iclass 34, count 0 2006.257.11:07:55.97#ibcon#end of sib2, iclass 34, count 0 2006.257.11:07:55.97#ibcon#*after write, iclass 34, count 0 2006.257.11:07:55.97#ibcon#*before return 0, iclass 34, count 0 2006.257.11:07:55.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:55.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:55.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:07:55.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:07:55.97$vck44/va=3,8 2006.257.11:07:55.97#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.11:07:55.97#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.11:07:55.97#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:55.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:56.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:56.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:56.03#ibcon#enter wrdev, iclass 36, count 2 2006.257.11:07:56.03#ibcon#first serial, iclass 36, count 2 2006.257.11:07:56.03#ibcon#enter sib2, iclass 36, count 2 2006.257.11:07:56.03#ibcon#flushed, iclass 36, count 2 2006.257.11:07:56.03#ibcon#about to write, iclass 36, count 2 2006.257.11:07:56.03#ibcon#wrote, iclass 36, count 2 2006.257.11:07:56.03#ibcon#about to read 3, iclass 36, count 2 2006.257.11:07:56.05#ibcon#read 3, iclass 36, count 2 2006.257.11:07:56.05#ibcon#about to read 4, iclass 36, count 2 2006.257.11:07:56.05#ibcon#read 4, iclass 36, count 2 2006.257.11:07:56.05#ibcon#about to read 5, iclass 36, count 2 2006.257.11:07:56.05#ibcon#read 5, iclass 36, count 2 2006.257.11:07:56.05#ibcon#about to read 6, iclass 36, count 2 2006.257.11:07:56.05#ibcon#read 6, iclass 36, count 2 2006.257.11:07:56.05#ibcon#end of sib2, iclass 36, count 2 2006.257.11:07:56.05#ibcon#*mode == 0, iclass 36, count 2 2006.257.11:07:56.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.11:07:56.05#ibcon#[25=AT03-08\r\n] 2006.257.11:07:56.05#ibcon#*before write, iclass 36, count 2 2006.257.11:07:56.05#ibcon#enter sib2, iclass 36, count 2 2006.257.11:07:56.05#ibcon#flushed, iclass 36, count 2 2006.257.11:07:56.05#ibcon#about to write, iclass 36, count 2 2006.257.11:07:56.05#ibcon#wrote, iclass 36, count 2 2006.257.11:07:56.05#ibcon#about to read 3, iclass 36, count 2 2006.257.11:07:56.08#ibcon#read 3, iclass 36, count 2 2006.257.11:07:56.08#ibcon#about to read 4, iclass 36, count 2 2006.257.11:07:56.08#ibcon#read 4, iclass 36, count 2 2006.257.11:07:56.08#ibcon#about to read 5, iclass 36, count 2 2006.257.11:07:56.08#ibcon#read 5, iclass 36, count 2 2006.257.11:07:56.08#ibcon#about to read 6, iclass 36, count 2 2006.257.11:07:56.08#ibcon#read 6, iclass 36, count 2 2006.257.11:07:56.08#ibcon#end of sib2, iclass 36, count 2 2006.257.11:07:56.08#ibcon#*after write, iclass 36, count 2 2006.257.11:07:56.08#ibcon#*before return 0, iclass 36, count 2 2006.257.11:07:56.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:56.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:56.08#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.11:07:56.08#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:56.08#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:56.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:56.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:56.20#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:07:56.20#ibcon#first serial, iclass 36, count 0 2006.257.11:07:56.20#ibcon#enter sib2, iclass 36, count 0 2006.257.11:07:56.20#ibcon#flushed, iclass 36, count 0 2006.257.11:07:56.20#ibcon#about to write, iclass 36, count 0 2006.257.11:07:56.20#ibcon#wrote, iclass 36, count 0 2006.257.11:07:56.20#ibcon#about to read 3, iclass 36, count 0 2006.257.11:07:56.22#ibcon#read 3, iclass 36, count 0 2006.257.11:07:56.22#ibcon#about to read 4, iclass 36, count 0 2006.257.11:07:56.22#ibcon#read 4, iclass 36, count 0 2006.257.11:07:56.22#ibcon#about to read 5, iclass 36, count 0 2006.257.11:07:56.22#ibcon#read 5, iclass 36, count 0 2006.257.11:07:56.22#ibcon#about to read 6, iclass 36, count 0 2006.257.11:07:56.22#ibcon#read 6, iclass 36, count 0 2006.257.11:07:56.22#ibcon#end of sib2, iclass 36, count 0 2006.257.11:07:56.22#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:07:56.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:07:56.22#ibcon#[25=USB\r\n] 2006.257.11:07:56.22#ibcon#*before write, iclass 36, count 0 2006.257.11:07:56.22#ibcon#enter sib2, iclass 36, count 0 2006.257.11:07:56.22#ibcon#flushed, iclass 36, count 0 2006.257.11:07:56.22#ibcon#about to write, iclass 36, count 0 2006.257.11:07:56.22#ibcon#wrote, iclass 36, count 0 2006.257.11:07:56.22#ibcon#about to read 3, iclass 36, count 0 2006.257.11:07:56.25#ibcon#read 3, iclass 36, count 0 2006.257.11:07:56.25#ibcon#about to read 4, iclass 36, count 0 2006.257.11:07:56.25#ibcon#read 4, iclass 36, count 0 2006.257.11:07:56.25#ibcon#about to read 5, iclass 36, count 0 2006.257.11:07:56.25#ibcon#read 5, iclass 36, count 0 2006.257.11:07:56.25#ibcon#about to read 6, iclass 36, count 0 2006.257.11:07:56.25#ibcon#read 6, iclass 36, count 0 2006.257.11:07:56.25#ibcon#end of sib2, iclass 36, count 0 2006.257.11:07:56.25#ibcon#*after write, iclass 36, count 0 2006.257.11:07:56.25#ibcon#*before return 0, iclass 36, count 0 2006.257.11:07:56.25#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:56.25#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:56.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:07:56.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:07:56.25$vck44/valo=4,624.99 2006.257.11:07:56.25#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.11:07:56.25#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.11:07:56.25#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:56.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:56.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:56.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:56.25#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:07:56.25#ibcon#first serial, iclass 38, count 0 2006.257.11:07:56.25#ibcon#enter sib2, iclass 38, count 0 2006.257.11:07:56.25#ibcon#flushed, iclass 38, count 0 2006.257.11:07:56.25#ibcon#about to write, iclass 38, count 0 2006.257.11:07:56.25#ibcon#wrote, iclass 38, count 0 2006.257.11:07:56.25#ibcon#about to read 3, iclass 38, count 0 2006.257.11:07:56.27#ibcon#read 3, iclass 38, count 0 2006.257.11:07:56.27#ibcon#about to read 4, iclass 38, count 0 2006.257.11:07:56.27#ibcon#read 4, iclass 38, count 0 2006.257.11:07:56.27#ibcon#about to read 5, iclass 38, count 0 2006.257.11:07:56.27#ibcon#read 5, iclass 38, count 0 2006.257.11:07:56.27#ibcon#about to read 6, iclass 38, count 0 2006.257.11:07:56.27#ibcon#read 6, iclass 38, count 0 2006.257.11:07:56.27#ibcon#end of sib2, iclass 38, count 0 2006.257.11:07:56.27#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:07:56.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:07:56.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:07:56.27#ibcon#*before write, iclass 38, count 0 2006.257.11:07:56.27#ibcon#enter sib2, iclass 38, count 0 2006.257.11:07:56.27#ibcon#flushed, iclass 38, count 0 2006.257.11:07:56.27#ibcon#about to write, iclass 38, count 0 2006.257.11:07:56.27#ibcon#wrote, iclass 38, count 0 2006.257.11:07:56.27#ibcon#about to read 3, iclass 38, count 0 2006.257.11:07:56.31#ibcon#read 3, iclass 38, count 0 2006.257.11:07:56.31#ibcon#about to read 4, iclass 38, count 0 2006.257.11:07:56.31#ibcon#read 4, iclass 38, count 0 2006.257.11:07:56.31#ibcon#about to read 5, iclass 38, count 0 2006.257.11:07:56.31#ibcon#read 5, iclass 38, count 0 2006.257.11:07:56.31#ibcon#about to read 6, iclass 38, count 0 2006.257.11:07:56.31#ibcon#read 6, iclass 38, count 0 2006.257.11:07:56.31#ibcon#end of sib2, iclass 38, count 0 2006.257.11:07:56.31#ibcon#*after write, iclass 38, count 0 2006.257.11:07:56.31#ibcon#*before return 0, iclass 38, count 0 2006.257.11:07:56.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:56.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:56.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:07:56.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:07:56.31$vck44/va=4,7 2006.257.11:07:56.31#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.11:07:56.31#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.11:07:56.31#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:56.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:56.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:56.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:56.37#ibcon#enter wrdev, iclass 40, count 2 2006.257.11:07:56.37#ibcon#first serial, iclass 40, count 2 2006.257.11:07:56.37#ibcon#enter sib2, iclass 40, count 2 2006.257.11:07:56.37#ibcon#flushed, iclass 40, count 2 2006.257.11:07:56.37#ibcon#about to write, iclass 40, count 2 2006.257.11:07:56.37#ibcon#wrote, iclass 40, count 2 2006.257.11:07:56.37#ibcon#about to read 3, iclass 40, count 2 2006.257.11:07:56.39#ibcon#read 3, iclass 40, count 2 2006.257.11:07:56.39#ibcon#about to read 4, iclass 40, count 2 2006.257.11:07:56.39#ibcon#read 4, iclass 40, count 2 2006.257.11:07:56.39#ibcon#about to read 5, iclass 40, count 2 2006.257.11:07:56.39#ibcon#read 5, iclass 40, count 2 2006.257.11:07:56.39#ibcon#about to read 6, iclass 40, count 2 2006.257.11:07:56.39#ibcon#read 6, iclass 40, count 2 2006.257.11:07:56.39#ibcon#end of sib2, iclass 40, count 2 2006.257.11:07:56.39#ibcon#*mode == 0, iclass 40, count 2 2006.257.11:07:56.39#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.11:07:56.39#ibcon#[25=AT04-07\r\n] 2006.257.11:07:56.39#ibcon#*before write, iclass 40, count 2 2006.257.11:07:56.39#ibcon#enter sib2, iclass 40, count 2 2006.257.11:07:56.39#ibcon#flushed, iclass 40, count 2 2006.257.11:07:56.39#ibcon#about to write, iclass 40, count 2 2006.257.11:07:56.39#ibcon#wrote, iclass 40, count 2 2006.257.11:07:56.39#ibcon#about to read 3, iclass 40, count 2 2006.257.11:07:56.42#ibcon#read 3, iclass 40, count 2 2006.257.11:07:56.42#ibcon#about to read 4, iclass 40, count 2 2006.257.11:07:56.42#ibcon#read 4, iclass 40, count 2 2006.257.11:07:56.42#ibcon#about to read 5, iclass 40, count 2 2006.257.11:07:56.42#ibcon#read 5, iclass 40, count 2 2006.257.11:07:56.42#ibcon#about to read 6, iclass 40, count 2 2006.257.11:07:56.42#ibcon#read 6, iclass 40, count 2 2006.257.11:07:56.42#ibcon#end of sib2, iclass 40, count 2 2006.257.11:07:56.42#ibcon#*after write, iclass 40, count 2 2006.257.11:07:56.42#ibcon#*before return 0, iclass 40, count 2 2006.257.11:07:56.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:56.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:56.42#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.11:07:56.42#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:56.42#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:56.54#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:56.54#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:56.54#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:07:56.54#ibcon#first serial, iclass 40, count 0 2006.257.11:07:56.54#ibcon#enter sib2, iclass 40, count 0 2006.257.11:07:56.54#ibcon#flushed, iclass 40, count 0 2006.257.11:07:56.54#ibcon#about to write, iclass 40, count 0 2006.257.11:07:56.54#ibcon#wrote, iclass 40, count 0 2006.257.11:07:56.54#ibcon#about to read 3, iclass 40, count 0 2006.257.11:07:56.56#ibcon#read 3, iclass 40, count 0 2006.257.11:07:56.56#ibcon#about to read 4, iclass 40, count 0 2006.257.11:07:56.56#ibcon#read 4, iclass 40, count 0 2006.257.11:07:56.56#ibcon#about to read 5, iclass 40, count 0 2006.257.11:07:56.56#ibcon#read 5, iclass 40, count 0 2006.257.11:07:56.56#ibcon#about to read 6, iclass 40, count 0 2006.257.11:07:56.56#ibcon#read 6, iclass 40, count 0 2006.257.11:07:56.56#ibcon#end of sib2, iclass 40, count 0 2006.257.11:07:56.56#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:07:56.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:07:56.56#ibcon#[25=USB\r\n] 2006.257.11:07:56.56#ibcon#*before write, iclass 40, count 0 2006.257.11:07:56.56#ibcon#enter sib2, iclass 40, count 0 2006.257.11:07:56.56#ibcon#flushed, iclass 40, count 0 2006.257.11:07:56.56#ibcon#about to write, iclass 40, count 0 2006.257.11:07:56.56#ibcon#wrote, iclass 40, count 0 2006.257.11:07:56.56#ibcon#about to read 3, iclass 40, count 0 2006.257.11:07:56.59#ibcon#read 3, iclass 40, count 0 2006.257.11:07:56.59#ibcon#about to read 4, iclass 40, count 0 2006.257.11:07:56.59#ibcon#read 4, iclass 40, count 0 2006.257.11:07:56.59#ibcon#about to read 5, iclass 40, count 0 2006.257.11:07:56.59#ibcon#read 5, iclass 40, count 0 2006.257.11:07:56.59#ibcon#about to read 6, iclass 40, count 0 2006.257.11:07:56.59#ibcon#read 6, iclass 40, count 0 2006.257.11:07:56.59#ibcon#end of sib2, iclass 40, count 0 2006.257.11:07:56.59#ibcon#*after write, iclass 40, count 0 2006.257.11:07:56.59#ibcon#*before return 0, iclass 40, count 0 2006.257.11:07:56.59#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:56.59#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:56.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:07:56.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:07:56.59$vck44/valo=5,734.99 2006.257.11:07:56.59#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.11:07:56.59#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.11:07:56.59#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:56.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:56.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:56.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:56.59#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:07:56.59#ibcon#first serial, iclass 4, count 0 2006.257.11:07:56.59#ibcon#enter sib2, iclass 4, count 0 2006.257.11:07:56.59#ibcon#flushed, iclass 4, count 0 2006.257.11:07:56.59#ibcon#about to write, iclass 4, count 0 2006.257.11:07:56.59#ibcon#wrote, iclass 4, count 0 2006.257.11:07:56.59#ibcon#about to read 3, iclass 4, count 0 2006.257.11:07:56.61#ibcon#read 3, iclass 4, count 0 2006.257.11:07:56.61#ibcon#about to read 4, iclass 4, count 0 2006.257.11:07:56.61#ibcon#read 4, iclass 4, count 0 2006.257.11:07:56.61#ibcon#about to read 5, iclass 4, count 0 2006.257.11:07:56.61#ibcon#read 5, iclass 4, count 0 2006.257.11:07:56.61#ibcon#about to read 6, iclass 4, count 0 2006.257.11:07:56.61#ibcon#read 6, iclass 4, count 0 2006.257.11:07:56.61#ibcon#end of sib2, iclass 4, count 0 2006.257.11:07:56.61#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:07:56.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:07:56.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:07:56.61#ibcon#*before write, iclass 4, count 0 2006.257.11:07:56.61#ibcon#enter sib2, iclass 4, count 0 2006.257.11:07:56.61#ibcon#flushed, iclass 4, count 0 2006.257.11:07:56.61#ibcon#about to write, iclass 4, count 0 2006.257.11:07:56.61#ibcon#wrote, iclass 4, count 0 2006.257.11:07:56.61#ibcon#about to read 3, iclass 4, count 0 2006.257.11:07:56.65#ibcon#read 3, iclass 4, count 0 2006.257.11:07:56.65#ibcon#about to read 4, iclass 4, count 0 2006.257.11:07:56.65#ibcon#read 4, iclass 4, count 0 2006.257.11:07:56.65#ibcon#about to read 5, iclass 4, count 0 2006.257.11:07:56.65#ibcon#read 5, iclass 4, count 0 2006.257.11:07:56.65#ibcon#about to read 6, iclass 4, count 0 2006.257.11:07:56.65#ibcon#read 6, iclass 4, count 0 2006.257.11:07:56.65#ibcon#end of sib2, iclass 4, count 0 2006.257.11:07:56.65#ibcon#*after write, iclass 4, count 0 2006.257.11:07:56.65#ibcon#*before return 0, iclass 4, count 0 2006.257.11:07:56.65#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:56.65#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:56.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:07:56.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:07:56.65$vck44/va=5,4 2006.257.11:07:56.65#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.11:07:56.65#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.11:07:56.65#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:56.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:56.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:56.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:56.71#ibcon#enter wrdev, iclass 6, count 2 2006.257.11:07:56.71#ibcon#first serial, iclass 6, count 2 2006.257.11:07:56.71#ibcon#enter sib2, iclass 6, count 2 2006.257.11:07:56.71#ibcon#flushed, iclass 6, count 2 2006.257.11:07:56.71#ibcon#about to write, iclass 6, count 2 2006.257.11:07:56.71#ibcon#wrote, iclass 6, count 2 2006.257.11:07:56.71#ibcon#about to read 3, iclass 6, count 2 2006.257.11:07:56.73#ibcon#read 3, iclass 6, count 2 2006.257.11:07:56.73#ibcon#about to read 4, iclass 6, count 2 2006.257.11:07:56.73#ibcon#read 4, iclass 6, count 2 2006.257.11:07:56.73#ibcon#about to read 5, iclass 6, count 2 2006.257.11:07:56.73#ibcon#read 5, iclass 6, count 2 2006.257.11:07:56.73#ibcon#about to read 6, iclass 6, count 2 2006.257.11:07:56.73#ibcon#read 6, iclass 6, count 2 2006.257.11:07:56.73#ibcon#end of sib2, iclass 6, count 2 2006.257.11:07:56.73#ibcon#*mode == 0, iclass 6, count 2 2006.257.11:07:56.73#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.11:07:56.73#ibcon#[25=AT05-04\r\n] 2006.257.11:07:56.73#ibcon#*before write, iclass 6, count 2 2006.257.11:07:56.73#ibcon#enter sib2, iclass 6, count 2 2006.257.11:07:56.73#ibcon#flushed, iclass 6, count 2 2006.257.11:07:56.73#ibcon#about to write, iclass 6, count 2 2006.257.11:07:56.73#ibcon#wrote, iclass 6, count 2 2006.257.11:07:56.73#ibcon#about to read 3, iclass 6, count 2 2006.257.11:07:56.76#ibcon#read 3, iclass 6, count 2 2006.257.11:07:56.76#ibcon#about to read 4, iclass 6, count 2 2006.257.11:07:56.76#ibcon#read 4, iclass 6, count 2 2006.257.11:07:56.76#ibcon#about to read 5, iclass 6, count 2 2006.257.11:07:56.76#ibcon#read 5, iclass 6, count 2 2006.257.11:07:56.76#ibcon#about to read 6, iclass 6, count 2 2006.257.11:07:56.76#ibcon#read 6, iclass 6, count 2 2006.257.11:07:56.76#ibcon#end of sib2, iclass 6, count 2 2006.257.11:07:56.76#ibcon#*after write, iclass 6, count 2 2006.257.11:07:56.76#ibcon#*before return 0, iclass 6, count 2 2006.257.11:07:56.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:56.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:56.76#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.11:07:56.76#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:56.76#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:56.88#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:56.88#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:56.88#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:07:56.88#ibcon#first serial, iclass 6, count 0 2006.257.11:07:56.88#ibcon#enter sib2, iclass 6, count 0 2006.257.11:07:56.88#ibcon#flushed, iclass 6, count 0 2006.257.11:07:56.88#ibcon#about to write, iclass 6, count 0 2006.257.11:07:56.88#ibcon#wrote, iclass 6, count 0 2006.257.11:07:56.88#ibcon#about to read 3, iclass 6, count 0 2006.257.11:07:56.90#ibcon#read 3, iclass 6, count 0 2006.257.11:07:56.90#ibcon#about to read 4, iclass 6, count 0 2006.257.11:07:56.90#ibcon#read 4, iclass 6, count 0 2006.257.11:07:56.90#ibcon#about to read 5, iclass 6, count 0 2006.257.11:07:56.90#ibcon#read 5, iclass 6, count 0 2006.257.11:07:56.90#ibcon#about to read 6, iclass 6, count 0 2006.257.11:07:56.90#ibcon#read 6, iclass 6, count 0 2006.257.11:07:56.90#ibcon#end of sib2, iclass 6, count 0 2006.257.11:07:56.90#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:07:56.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:07:56.90#ibcon#[25=USB\r\n] 2006.257.11:07:56.90#ibcon#*before write, iclass 6, count 0 2006.257.11:07:56.90#ibcon#enter sib2, iclass 6, count 0 2006.257.11:07:56.90#ibcon#flushed, iclass 6, count 0 2006.257.11:07:56.90#ibcon#about to write, iclass 6, count 0 2006.257.11:07:56.90#ibcon#wrote, iclass 6, count 0 2006.257.11:07:56.90#ibcon#about to read 3, iclass 6, count 0 2006.257.11:07:56.93#ibcon#read 3, iclass 6, count 0 2006.257.11:07:56.93#ibcon#about to read 4, iclass 6, count 0 2006.257.11:07:56.93#ibcon#read 4, iclass 6, count 0 2006.257.11:07:56.93#ibcon#about to read 5, iclass 6, count 0 2006.257.11:07:56.93#ibcon#read 5, iclass 6, count 0 2006.257.11:07:56.93#ibcon#about to read 6, iclass 6, count 0 2006.257.11:07:56.93#ibcon#read 6, iclass 6, count 0 2006.257.11:07:56.93#ibcon#end of sib2, iclass 6, count 0 2006.257.11:07:56.93#ibcon#*after write, iclass 6, count 0 2006.257.11:07:56.93#ibcon#*before return 0, iclass 6, count 0 2006.257.11:07:56.93#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:56.93#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:56.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:07:56.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:07:56.93$vck44/valo=6,814.99 2006.257.11:07:56.93#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.11:07:56.93#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.11:07:56.93#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:56.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:56.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:56.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:56.93#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:07:56.93#ibcon#first serial, iclass 10, count 0 2006.257.11:07:56.93#ibcon#enter sib2, iclass 10, count 0 2006.257.11:07:56.93#ibcon#flushed, iclass 10, count 0 2006.257.11:07:56.93#ibcon#about to write, iclass 10, count 0 2006.257.11:07:56.93#ibcon#wrote, iclass 10, count 0 2006.257.11:07:56.93#ibcon#about to read 3, iclass 10, count 0 2006.257.11:07:56.95#ibcon#read 3, iclass 10, count 0 2006.257.11:07:56.95#ibcon#about to read 4, iclass 10, count 0 2006.257.11:07:56.95#ibcon#read 4, iclass 10, count 0 2006.257.11:07:56.95#ibcon#about to read 5, iclass 10, count 0 2006.257.11:07:56.95#ibcon#read 5, iclass 10, count 0 2006.257.11:07:56.95#ibcon#about to read 6, iclass 10, count 0 2006.257.11:07:56.95#ibcon#read 6, iclass 10, count 0 2006.257.11:07:56.95#ibcon#end of sib2, iclass 10, count 0 2006.257.11:07:56.95#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:07:56.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:07:56.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:07:56.95#ibcon#*before write, iclass 10, count 0 2006.257.11:07:56.95#ibcon#enter sib2, iclass 10, count 0 2006.257.11:07:56.95#ibcon#flushed, iclass 10, count 0 2006.257.11:07:56.95#ibcon#about to write, iclass 10, count 0 2006.257.11:07:56.95#ibcon#wrote, iclass 10, count 0 2006.257.11:07:56.95#ibcon#about to read 3, iclass 10, count 0 2006.257.11:07:56.99#ibcon#read 3, iclass 10, count 0 2006.257.11:07:56.99#ibcon#about to read 4, iclass 10, count 0 2006.257.11:07:56.99#ibcon#read 4, iclass 10, count 0 2006.257.11:07:56.99#ibcon#about to read 5, iclass 10, count 0 2006.257.11:07:56.99#ibcon#read 5, iclass 10, count 0 2006.257.11:07:56.99#ibcon#about to read 6, iclass 10, count 0 2006.257.11:07:56.99#ibcon#read 6, iclass 10, count 0 2006.257.11:07:56.99#ibcon#end of sib2, iclass 10, count 0 2006.257.11:07:56.99#ibcon#*after write, iclass 10, count 0 2006.257.11:07:56.99#ibcon#*before return 0, iclass 10, count 0 2006.257.11:07:56.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:56.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:56.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:07:56.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:07:56.99$vck44/va=6,4 2006.257.11:07:56.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.11:07:56.99#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.11:07:56.99#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:56.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:57.05#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:57.05#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:57.05#ibcon#enter wrdev, iclass 12, count 2 2006.257.11:07:57.05#ibcon#first serial, iclass 12, count 2 2006.257.11:07:57.05#ibcon#enter sib2, iclass 12, count 2 2006.257.11:07:57.05#ibcon#flushed, iclass 12, count 2 2006.257.11:07:57.05#ibcon#about to write, iclass 12, count 2 2006.257.11:07:57.05#ibcon#wrote, iclass 12, count 2 2006.257.11:07:57.05#ibcon#about to read 3, iclass 12, count 2 2006.257.11:07:57.07#ibcon#read 3, iclass 12, count 2 2006.257.11:07:57.07#ibcon#about to read 4, iclass 12, count 2 2006.257.11:07:57.07#ibcon#read 4, iclass 12, count 2 2006.257.11:07:57.07#ibcon#about to read 5, iclass 12, count 2 2006.257.11:07:57.07#ibcon#read 5, iclass 12, count 2 2006.257.11:07:57.07#ibcon#about to read 6, iclass 12, count 2 2006.257.11:07:57.07#ibcon#read 6, iclass 12, count 2 2006.257.11:07:57.07#ibcon#end of sib2, iclass 12, count 2 2006.257.11:07:57.07#ibcon#*mode == 0, iclass 12, count 2 2006.257.11:07:57.07#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.11:07:57.07#ibcon#[25=AT06-04\r\n] 2006.257.11:07:57.07#ibcon#*before write, iclass 12, count 2 2006.257.11:07:57.07#ibcon#enter sib2, iclass 12, count 2 2006.257.11:07:57.07#ibcon#flushed, iclass 12, count 2 2006.257.11:07:57.07#ibcon#about to write, iclass 12, count 2 2006.257.11:07:57.07#ibcon#wrote, iclass 12, count 2 2006.257.11:07:57.07#ibcon#about to read 3, iclass 12, count 2 2006.257.11:07:57.10#ibcon#read 3, iclass 12, count 2 2006.257.11:07:57.10#ibcon#about to read 4, iclass 12, count 2 2006.257.11:07:57.10#ibcon#read 4, iclass 12, count 2 2006.257.11:07:57.10#ibcon#about to read 5, iclass 12, count 2 2006.257.11:07:57.10#ibcon#read 5, iclass 12, count 2 2006.257.11:07:57.10#ibcon#about to read 6, iclass 12, count 2 2006.257.11:07:57.10#ibcon#read 6, iclass 12, count 2 2006.257.11:07:57.10#ibcon#end of sib2, iclass 12, count 2 2006.257.11:07:57.10#ibcon#*after write, iclass 12, count 2 2006.257.11:07:57.10#ibcon#*before return 0, iclass 12, count 2 2006.257.11:07:57.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:57.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:57.10#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.11:07:57.10#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:57.10#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:57.22#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:57.22#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:57.22#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:07:57.22#ibcon#first serial, iclass 12, count 0 2006.257.11:07:57.22#ibcon#enter sib2, iclass 12, count 0 2006.257.11:07:57.22#ibcon#flushed, iclass 12, count 0 2006.257.11:07:57.22#ibcon#about to write, iclass 12, count 0 2006.257.11:07:57.22#ibcon#wrote, iclass 12, count 0 2006.257.11:07:57.22#ibcon#about to read 3, iclass 12, count 0 2006.257.11:07:57.24#ibcon#read 3, iclass 12, count 0 2006.257.11:07:57.24#ibcon#about to read 4, iclass 12, count 0 2006.257.11:07:57.24#ibcon#read 4, iclass 12, count 0 2006.257.11:07:57.24#ibcon#about to read 5, iclass 12, count 0 2006.257.11:07:57.24#ibcon#read 5, iclass 12, count 0 2006.257.11:07:57.24#ibcon#about to read 6, iclass 12, count 0 2006.257.11:07:57.24#ibcon#read 6, iclass 12, count 0 2006.257.11:07:57.24#ibcon#end of sib2, iclass 12, count 0 2006.257.11:07:57.24#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:07:57.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:07:57.24#ibcon#[25=USB\r\n] 2006.257.11:07:57.24#ibcon#*before write, iclass 12, count 0 2006.257.11:07:57.24#ibcon#enter sib2, iclass 12, count 0 2006.257.11:07:57.24#ibcon#flushed, iclass 12, count 0 2006.257.11:07:57.24#ibcon#about to write, iclass 12, count 0 2006.257.11:07:57.24#ibcon#wrote, iclass 12, count 0 2006.257.11:07:57.24#ibcon#about to read 3, iclass 12, count 0 2006.257.11:07:57.27#ibcon#read 3, iclass 12, count 0 2006.257.11:07:57.27#ibcon#about to read 4, iclass 12, count 0 2006.257.11:07:57.27#ibcon#read 4, iclass 12, count 0 2006.257.11:07:57.27#ibcon#about to read 5, iclass 12, count 0 2006.257.11:07:57.27#ibcon#read 5, iclass 12, count 0 2006.257.11:07:57.27#ibcon#about to read 6, iclass 12, count 0 2006.257.11:07:57.27#ibcon#read 6, iclass 12, count 0 2006.257.11:07:57.27#ibcon#end of sib2, iclass 12, count 0 2006.257.11:07:57.27#ibcon#*after write, iclass 12, count 0 2006.257.11:07:57.27#ibcon#*before return 0, iclass 12, count 0 2006.257.11:07:57.27#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:57.27#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:57.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:07:57.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:07:57.27$vck44/valo=7,864.99 2006.257.11:07:57.27#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.11:07:57.27#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.11:07:57.27#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:57.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:57.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:57.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:57.27#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:07:57.27#ibcon#first serial, iclass 14, count 0 2006.257.11:07:57.27#ibcon#enter sib2, iclass 14, count 0 2006.257.11:07:57.27#ibcon#flushed, iclass 14, count 0 2006.257.11:07:57.27#ibcon#about to write, iclass 14, count 0 2006.257.11:07:57.27#ibcon#wrote, iclass 14, count 0 2006.257.11:07:57.27#ibcon#about to read 3, iclass 14, count 0 2006.257.11:07:57.29#ibcon#read 3, iclass 14, count 0 2006.257.11:07:57.29#ibcon#about to read 4, iclass 14, count 0 2006.257.11:07:57.29#ibcon#read 4, iclass 14, count 0 2006.257.11:07:57.29#ibcon#about to read 5, iclass 14, count 0 2006.257.11:07:57.29#ibcon#read 5, iclass 14, count 0 2006.257.11:07:57.29#ibcon#about to read 6, iclass 14, count 0 2006.257.11:07:57.29#ibcon#read 6, iclass 14, count 0 2006.257.11:07:57.29#ibcon#end of sib2, iclass 14, count 0 2006.257.11:07:57.29#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:07:57.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:07:57.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:07:57.29#ibcon#*before write, iclass 14, count 0 2006.257.11:07:57.29#ibcon#enter sib2, iclass 14, count 0 2006.257.11:07:57.29#ibcon#flushed, iclass 14, count 0 2006.257.11:07:57.29#ibcon#about to write, iclass 14, count 0 2006.257.11:07:57.29#ibcon#wrote, iclass 14, count 0 2006.257.11:07:57.29#ibcon#about to read 3, iclass 14, count 0 2006.257.11:07:57.33#ibcon#read 3, iclass 14, count 0 2006.257.11:07:57.33#ibcon#about to read 4, iclass 14, count 0 2006.257.11:07:57.33#ibcon#read 4, iclass 14, count 0 2006.257.11:07:57.33#ibcon#about to read 5, iclass 14, count 0 2006.257.11:07:57.33#ibcon#read 5, iclass 14, count 0 2006.257.11:07:57.33#ibcon#about to read 6, iclass 14, count 0 2006.257.11:07:57.33#ibcon#read 6, iclass 14, count 0 2006.257.11:07:57.33#ibcon#end of sib2, iclass 14, count 0 2006.257.11:07:57.33#ibcon#*after write, iclass 14, count 0 2006.257.11:07:57.33#ibcon#*before return 0, iclass 14, count 0 2006.257.11:07:57.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:57.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:57.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:07:57.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:07:57.33$vck44/va=7,4 2006.257.11:07:57.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.11:07:57.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.11:07:57.33#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:57.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:07:57.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:07:57.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:07:57.39#ibcon#enter wrdev, iclass 16, count 2 2006.257.11:07:57.39#ibcon#first serial, iclass 16, count 2 2006.257.11:07:57.39#ibcon#enter sib2, iclass 16, count 2 2006.257.11:07:57.39#ibcon#flushed, iclass 16, count 2 2006.257.11:07:57.39#ibcon#about to write, iclass 16, count 2 2006.257.11:07:57.39#ibcon#wrote, iclass 16, count 2 2006.257.11:07:57.39#ibcon#about to read 3, iclass 16, count 2 2006.257.11:07:57.41#ibcon#read 3, iclass 16, count 2 2006.257.11:07:57.41#ibcon#about to read 4, iclass 16, count 2 2006.257.11:07:57.41#ibcon#read 4, iclass 16, count 2 2006.257.11:07:57.41#ibcon#about to read 5, iclass 16, count 2 2006.257.11:07:57.41#ibcon#read 5, iclass 16, count 2 2006.257.11:07:57.41#ibcon#about to read 6, iclass 16, count 2 2006.257.11:07:57.41#ibcon#read 6, iclass 16, count 2 2006.257.11:07:57.41#ibcon#end of sib2, iclass 16, count 2 2006.257.11:07:57.41#ibcon#*mode == 0, iclass 16, count 2 2006.257.11:07:57.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.11:07:57.41#ibcon#[25=AT07-04\r\n] 2006.257.11:07:57.41#ibcon#*before write, iclass 16, count 2 2006.257.11:07:57.41#ibcon#enter sib2, iclass 16, count 2 2006.257.11:07:57.41#ibcon#flushed, iclass 16, count 2 2006.257.11:07:57.41#ibcon#about to write, iclass 16, count 2 2006.257.11:07:57.41#ibcon#wrote, iclass 16, count 2 2006.257.11:07:57.41#ibcon#about to read 3, iclass 16, count 2 2006.257.11:07:57.44#ibcon#read 3, iclass 16, count 2 2006.257.11:07:57.44#ibcon#about to read 4, iclass 16, count 2 2006.257.11:07:57.44#ibcon#read 4, iclass 16, count 2 2006.257.11:07:57.44#ibcon#about to read 5, iclass 16, count 2 2006.257.11:07:57.44#ibcon#read 5, iclass 16, count 2 2006.257.11:07:57.44#ibcon#about to read 6, iclass 16, count 2 2006.257.11:07:57.44#ibcon#read 6, iclass 16, count 2 2006.257.11:07:57.44#ibcon#end of sib2, iclass 16, count 2 2006.257.11:07:57.44#ibcon#*after write, iclass 16, count 2 2006.257.11:07:57.44#ibcon#*before return 0, iclass 16, count 2 2006.257.11:07:57.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:07:57.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:07:57.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.11:07:57.44#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:57.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:07:57.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:07:57.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:07:57.56#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:07:57.56#ibcon#first serial, iclass 16, count 0 2006.257.11:07:57.56#ibcon#enter sib2, iclass 16, count 0 2006.257.11:07:57.56#ibcon#flushed, iclass 16, count 0 2006.257.11:07:57.56#ibcon#about to write, iclass 16, count 0 2006.257.11:07:57.56#ibcon#wrote, iclass 16, count 0 2006.257.11:07:57.56#ibcon#about to read 3, iclass 16, count 0 2006.257.11:07:57.58#ibcon#read 3, iclass 16, count 0 2006.257.11:07:57.58#ibcon#about to read 4, iclass 16, count 0 2006.257.11:07:57.58#ibcon#read 4, iclass 16, count 0 2006.257.11:07:57.58#ibcon#about to read 5, iclass 16, count 0 2006.257.11:07:57.58#ibcon#read 5, iclass 16, count 0 2006.257.11:07:57.58#ibcon#about to read 6, iclass 16, count 0 2006.257.11:07:57.58#ibcon#read 6, iclass 16, count 0 2006.257.11:07:57.58#ibcon#end of sib2, iclass 16, count 0 2006.257.11:07:57.58#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:07:57.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:07:57.58#ibcon#[25=USB\r\n] 2006.257.11:07:57.58#ibcon#*before write, iclass 16, count 0 2006.257.11:07:57.58#ibcon#enter sib2, iclass 16, count 0 2006.257.11:07:57.58#ibcon#flushed, iclass 16, count 0 2006.257.11:07:57.58#ibcon#about to write, iclass 16, count 0 2006.257.11:07:57.58#ibcon#wrote, iclass 16, count 0 2006.257.11:07:57.58#ibcon#about to read 3, iclass 16, count 0 2006.257.11:07:57.61#ibcon#read 3, iclass 16, count 0 2006.257.11:07:57.61#ibcon#about to read 4, iclass 16, count 0 2006.257.11:07:57.61#ibcon#read 4, iclass 16, count 0 2006.257.11:07:57.61#ibcon#about to read 5, iclass 16, count 0 2006.257.11:07:57.61#ibcon#read 5, iclass 16, count 0 2006.257.11:07:57.61#ibcon#about to read 6, iclass 16, count 0 2006.257.11:07:57.61#ibcon#read 6, iclass 16, count 0 2006.257.11:07:57.61#ibcon#end of sib2, iclass 16, count 0 2006.257.11:07:57.61#ibcon#*after write, iclass 16, count 0 2006.257.11:07:57.61#ibcon#*before return 0, iclass 16, count 0 2006.257.11:07:57.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:07:57.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:07:57.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:07:57.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:07:57.61$vck44/valo=8,884.99 2006.257.11:07:57.61#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.11:07:57.61#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.11:07:57.61#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:57.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:07:57.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:07:57.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:07:57.61#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:07:57.61#ibcon#first serial, iclass 18, count 0 2006.257.11:07:57.61#ibcon#enter sib2, iclass 18, count 0 2006.257.11:07:57.61#ibcon#flushed, iclass 18, count 0 2006.257.11:07:57.61#ibcon#about to write, iclass 18, count 0 2006.257.11:07:57.61#ibcon#wrote, iclass 18, count 0 2006.257.11:07:57.61#ibcon#about to read 3, iclass 18, count 0 2006.257.11:07:57.63#ibcon#read 3, iclass 18, count 0 2006.257.11:07:57.63#ibcon#about to read 4, iclass 18, count 0 2006.257.11:07:57.63#ibcon#read 4, iclass 18, count 0 2006.257.11:07:57.63#ibcon#about to read 5, iclass 18, count 0 2006.257.11:07:57.63#ibcon#read 5, iclass 18, count 0 2006.257.11:07:57.63#ibcon#about to read 6, iclass 18, count 0 2006.257.11:07:57.63#ibcon#read 6, iclass 18, count 0 2006.257.11:07:57.63#ibcon#end of sib2, iclass 18, count 0 2006.257.11:07:57.63#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:07:57.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:07:57.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:07:57.63#ibcon#*before write, iclass 18, count 0 2006.257.11:07:57.63#ibcon#enter sib2, iclass 18, count 0 2006.257.11:07:57.63#ibcon#flushed, iclass 18, count 0 2006.257.11:07:57.63#ibcon#about to write, iclass 18, count 0 2006.257.11:07:57.63#ibcon#wrote, iclass 18, count 0 2006.257.11:07:57.63#ibcon#about to read 3, iclass 18, count 0 2006.257.11:07:57.67#ibcon#read 3, iclass 18, count 0 2006.257.11:07:57.67#ibcon#about to read 4, iclass 18, count 0 2006.257.11:07:57.67#ibcon#read 4, iclass 18, count 0 2006.257.11:07:57.67#ibcon#about to read 5, iclass 18, count 0 2006.257.11:07:57.67#ibcon#read 5, iclass 18, count 0 2006.257.11:07:57.67#ibcon#about to read 6, iclass 18, count 0 2006.257.11:07:57.67#ibcon#read 6, iclass 18, count 0 2006.257.11:07:57.67#ibcon#end of sib2, iclass 18, count 0 2006.257.11:07:57.67#ibcon#*after write, iclass 18, count 0 2006.257.11:07:57.67#ibcon#*before return 0, iclass 18, count 0 2006.257.11:07:57.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:07:57.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:07:57.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:07:57.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:07:57.67$vck44/va=8,4 2006.257.11:07:57.67#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.11:07:57.67#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.11:07:57.67#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:57.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:07:57.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:07:57.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:07:57.73#ibcon#enter wrdev, iclass 20, count 2 2006.257.11:07:57.73#ibcon#first serial, iclass 20, count 2 2006.257.11:07:57.73#ibcon#enter sib2, iclass 20, count 2 2006.257.11:07:57.73#ibcon#flushed, iclass 20, count 2 2006.257.11:07:57.73#ibcon#about to write, iclass 20, count 2 2006.257.11:07:57.73#ibcon#wrote, iclass 20, count 2 2006.257.11:07:57.73#ibcon#about to read 3, iclass 20, count 2 2006.257.11:07:57.75#ibcon#read 3, iclass 20, count 2 2006.257.11:07:57.75#ibcon#about to read 4, iclass 20, count 2 2006.257.11:07:57.75#ibcon#read 4, iclass 20, count 2 2006.257.11:07:57.75#ibcon#about to read 5, iclass 20, count 2 2006.257.11:07:57.75#ibcon#read 5, iclass 20, count 2 2006.257.11:07:57.75#ibcon#about to read 6, iclass 20, count 2 2006.257.11:07:57.75#ibcon#read 6, iclass 20, count 2 2006.257.11:07:57.75#ibcon#end of sib2, iclass 20, count 2 2006.257.11:07:57.75#ibcon#*mode == 0, iclass 20, count 2 2006.257.11:07:57.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.11:07:57.75#ibcon#[25=AT08-04\r\n] 2006.257.11:07:57.75#ibcon#*before write, iclass 20, count 2 2006.257.11:07:57.75#ibcon#enter sib2, iclass 20, count 2 2006.257.11:07:57.75#ibcon#flushed, iclass 20, count 2 2006.257.11:07:57.75#ibcon#about to write, iclass 20, count 2 2006.257.11:07:57.75#ibcon#wrote, iclass 20, count 2 2006.257.11:07:57.75#ibcon#about to read 3, iclass 20, count 2 2006.257.11:07:57.76#abcon#<5=/14 1.6 4.1 18.54 961014.1\r\n> 2006.257.11:07:57.78#abcon#{5=INTERFACE CLEAR} 2006.257.11:07:57.78#ibcon#read 3, iclass 20, count 2 2006.257.11:07:57.78#ibcon#about to read 4, iclass 20, count 2 2006.257.11:07:57.78#ibcon#read 4, iclass 20, count 2 2006.257.11:07:57.78#ibcon#about to read 5, iclass 20, count 2 2006.257.11:07:57.78#ibcon#read 5, iclass 20, count 2 2006.257.11:07:57.78#ibcon#about to read 6, iclass 20, count 2 2006.257.11:07:57.78#ibcon#read 6, iclass 20, count 2 2006.257.11:07:57.78#ibcon#end of sib2, iclass 20, count 2 2006.257.11:07:57.78#ibcon#*after write, iclass 20, count 2 2006.257.11:07:57.78#ibcon#*before return 0, iclass 20, count 2 2006.257.11:07:57.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:07:57.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:07:57.78#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.11:07:57.78#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:57.78#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:07:57.84#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:07:57.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:07:57.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:07:57.90#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:07:57.90#ibcon#first serial, iclass 20, count 0 2006.257.11:07:57.90#ibcon#enter sib2, iclass 20, count 0 2006.257.11:07:57.90#ibcon#flushed, iclass 20, count 0 2006.257.11:07:57.90#ibcon#about to write, iclass 20, count 0 2006.257.11:07:57.90#ibcon#wrote, iclass 20, count 0 2006.257.11:07:57.90#ibcon#about to read 3, iclass 20, count 0 2006.257.11:07:57.92#ibcon#read 3, iclass 20, count 0 2006.257.11:07:57.92#ibcon#about to read 4, iclass 20, count 0 2006.257.11:07:57.92#ibcon#read 4, iclass 20, count 0 2006.257.11:07:57.92#ibcon#about to read 5, iclass 20, count 0 2006.257.11:07:57.92#ibcon#read 5, iclass 20, count 0 2006.257.11:07:57.92#ibcon#about to read 6, iclass 20, count 0 2006.257.11:07:57.92#ibcon#read 6, iclass 20, count 0 2006.257.11:07:57.92#ibcon#end of sib2, iclass 20, count 0 2006.257.11:07:57.92#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:07:57.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:07:57.92#ibcon#[25=USB\r\n] 2006.257.11:07:57.92#ibcon#*before write, iclass 20, count 0 2006.257.11:07:57.92#ibcon#enter sib2, iclass 20, count 0 2006.257.11:07:57.92#ibcon#flushed, iclass 20, count 0 2006.257.11:07:57.92#ibcon#about to write, iclass 20, count 0 2006.257.11:07:57.92#ibcon#wrote, iclass 20, count 0 2006.257.11:07:57.92#ibcon#about to read 3, iclass 20, count 0 2006.257.11:07:57.95#ibcon#read 3, iclass 20, count 0 2006.257.11:07:57.95#ibcon#about to read 4, iclass 20, count 0 2006.257.11:07:57.95#ibcon#read 4, iclass 20, count 0 2006.257.11:07:57.95#ibcon#about to read 5, iclass 20, count 0 2006.257.11:07:57.95#ibcon#read 5, iclass 20, count 0 2006.257.11:07:57.95#ibcon#about to read 6, iclass 20, count 0 2006.257.11:07:57.95#ibcon#read 6, iclass 20, count 0 2006.257.11:07:57.95#ibcon#end of sib2, iclass 20, count 0 2006.257.11:07:57.95#ibcon#*after write, iclass 20, count 0 2006.257.11:07:57.95#ibcon#*before return 0, iclass 20, count 0 2006.257.11:07:57.95#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:07:57.95#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:07:57.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:07:57.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:07:57.95$vck44/vblo=1,629.99 2006.257.11:07:57.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.11:07:57.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.11:07:57.95#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:57.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:57.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:57.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:57.95#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:07:57.95#ibcon#first serial, iclass 26, count 0 2006.257.11:07:57.95#ibcon#enter sib2, iclass 26, count 0 2006.257.11:07:57.95#ibcon#flushed, iclass 26, count 0 2006.257.11:07:57.95#ibcon#about to write, iclass 26, count 0 2006.257.11:07:57.95#ibcon#wrote, iclass 26, count 0 2006.257.11:07:57.95#ibcon#about to read 3, iclass 26, count 0 2006.257.11:07:57.97#ibcon#read 3, iclass 26, count 0 2006.257.11:07:57.97#ibcon#about to read 4, iclass 26, count 0 2006.257.11:07:57.97#ibcon#read 4, iclass 26, count 0 2006.257.11:07:57.97#ibcon#about to read 5, iclass 26, count 0 2006.257.11:07:57.97#ibcon#read 5, iclass 26, count 0 2006.257.11:07:57.97#ibcon#about to read 6, iclass 26, count 0 2006.257.11:07:57.97#ibcon#read 6, iclass 26, count 0 2006.257.11:07:57.97#ibcon#end of sib2, iclass 26, count 0 2006.257.11:07:57.97#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:07:57.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:07:57.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:07:57.97#ibcon#*before write, iclass 26, count 0 2006.257.11:07:57.97#ibcon#enter sib2, iclass 26, count 0 2006.257.11:07:57.97#ibcon#flushed, iclass 26, count 0 2006.257.11:07:57.97#ibcon#about to write, iclass 26, count 0 2006.257.11:07:57.97#ibcon#wrote, iclass 26, count 0 2006.257.11:07:57.97#ibcon#about to read 3, iclass 26, count 0 2006.257.11:07:58.01#ibcon#read 3, iclass 26, count 0 2006.257.11:07:58.01#ibcon#about to read 4, iclass 26, count 0 2006.257.11:07:58.01#ibcon#read 4, iclass 26, count 0 2006.257.11:07:58.01#ibcon#about to read 5, iclass 26, count 0 2006.257.11:07:58.01#ibcon#read 5, iclass 26, count 0 2006.257.11:07:58.01#ibcon#about to read 6, iclass 26, count 0 2006.257.11:07:58.01#ibcon#read 6, iclass 26, count 0 2006.257.11:07:58.01#ibcon#end of sib2, iclass 26, count 0 2006.257.11:07:58.01#ibcon#*after write, iclass 26, count 0 2006.257.11:07:58.01#ibcon#*before return 0, iclass 26, count 0 2006.257.11:07:58.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:58.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:07:58.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:07:58.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:07:58.01$vck44/vb=1,4 2006.257.11:07:58.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.11:07:58.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.11:07:58.01#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:58.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:58.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:58.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:58.01#ibcon#enter wrdev, iclass 28, count 2 2006.257.11:07:58.01#ibcon#first serial, iclass 28, count 2 2006.257.11:07:58.01#ibcon#enter sib2, iclass 28, count 2 2006.257.11:07:58.01#ibcon#flushed, iclass 28, count 2 2006.257.11:07:58.01#ibcon#about to write, iclass 28, count 2 2006.257.11:07:58.01#ibcon#wrote, iclass 28, count 2 2006.257.11:07:58.01#ibcon#about to read 3, iclass 28, count 2 2006.257.11:07:58.03#ibcon#read 3, iclass 28, count 2 2006.257.11:07:58.03#ibcon#about to read 4, iclass 28, count 2 2006.257.11:07:58.03#ibcon#read 4, iclass 28, count 2 2006.257.11:07:58.03#ibcon#about to read 5, iclass 28, count 2 2006.257.11:07:58.03#ibcon#read 5, iclass 28, count 2 2006.257.11:07:58.03#ibcon#about to read 6, iclass 28, count 2 2006.257.11:07:58.03#ibcon#read 6, iclass 28, count 2 2006.257.11:07:58.03#ibcon#end of sib2, iclass 28, count 2 2006.257.11:07:58.03#ibcon#*mode == 0, iclass 28, count 2 2006.257.11:07:58.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.11:07:58.03#ibcon#[27=AT01-04\r\n] 2006.257.11:07:58.03#ibcon#*before write, iclass 28, count 2 2006.257.11:07:58.03#ibcon#enter sib2, iclass 28, count 2 2006.257.11:07:58.03#ibcon#flushed, iclass 28, count 2 2006.257.11:07:58.03#ibcon#about to write, iclass 28, count 2 2006.257.11:07:58.03#ibcon#wrote, iclass 28, count 2 2006.257.11:07:58.03#ibcon#about to read 3, iclass 28, count 2 2006.257.11:07:58.06#ibcon#read 3, iclass 28, count 2 2006.257.11:07:58.06#ibcon#about to read 4, iclass 28, count 2 2006.257.11:07:58.06#ibcon#read 4, iclass 28, count 2 2006.257.11:07:58.06#ibcon#about to read 5, iclass 28, count 2 2006.257.11:07:58.06#ibcon#read 5, iclass 28, count 2 2006.257.11:07:58.06#ibcon#about to read 6, iclass 28, count 2 2006.257.11:07:58.06#ibcon#read 6, iclass 28, count 2 2006.257.11:07:58.06#ibcon#end of sib2, iclass 28, count 2 2006.257.11:07:58.06#ibcon#*after write, iclass 28, count 2 2006.257.11:07:58.06#ibcon#*before return 0, iclass 28, count 2 2006.257.11:07:58.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:58.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:07:58.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.11:07:58.06#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:58.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:58.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:58.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:58.18#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:07:58.18#ibcon#first serial, iclass 28, count 0 2006.257.11:07:58.18#ibcon#enter sib2, iclass 28, count 0 2006.257.11:07:58.18#ibcon#flushed, iclass 28, count 0 2006.257.11:07:58.18#ibcon#about to write, iclass 28, count 0 2006.257.11:07:58.18#ibcon#wrote, iclass 28, count 0 2006.257.11:07:58.18#ibcon#about to read 3, iclass 28, count 0 2006.257.11:07:58.20#ibcon#read 3, iclass 28, count 0 2006.257.11:07:58.20#ibcon#about to read 4, iclass 28, count 0 2006.257.11:07:58.20#ibcon#read 4, iclass 28, count 0 2006.257.11:07:58.20#ibcon#about to read 5, iclass 28, count 0 2006.257.11:07:58.20#ibcon#read 5, iclass 28, count 0 2006.257.11:07:58.20#ibcon#about to read 6, iclass 28, count 0 2006.257.11:07:58.20#ibcon#read 6, iclass 28, count 0 2006.257.11:07:58.20#ibcon#end of sib2, iclass 28, count 0 2006.257.11:07:58.20#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:07:58.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:07:58.20#ibcon#[27=USB\r\n] 2006.257.11:07:58.20#ibcon#*before write, iclass 28, count 0 2006.257.11:07:58.20#ibcon#enter sib2, iclass 28, count 0 2006.257.11:07:58.20#ibcon#flushed, iclass 28, count 0 2006.257.11:07:58.20#ibcon#about to write, iclass 28, count 0 2006.257.11:07:58.20#ibcon#wrote, iclass 28, count 0 2006.257.11:07:58.20#ibcon#about to read 3, iclass 28, count 0 2006.257.11:07:58.23#ibcon#read 3, iclass 28, count 0 2006.257.11:07:58.23#ibcon#about to read 4, iclass 28, count 0 2006.257.11:07:58.23#ibcon#read 4, iclass 28, count 0 2006.257.11:07:58.23#ibcon#about to read 5, iclass 28, count 0 2006.257.11:07:58.23#ibcon#read 5, iclass 28, count 0 2006.257.11:07:58.23#ibcon#about to read 6, iclass 28, count 0 2006.257.11:07:58.23#ibcon#read 6, iclass 28, count 0 2006.257.11:07:58.23#ibcon#end of sib2, iclass 28, count 0 2006.257.11:07:58.23#ibcon#*after write, iclass 28, count 0 2006.257.11:07:58.23#ibcon#*before return 0, iclass 28, count 0 2006.257.11:07:58.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:58.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:07:58.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:07:58.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:07:58.23$vck44/vblo=2,634.99 2006.257.11:07:58.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.11:07:58.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.11:07:58.23#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:58.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:58.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:58.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:58.23#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:07:58.23#ibcon#first serial, iclass 30, count 0 2006.257.11:07:58.23#ibcon#enter sib2, iclass 30, count 0 2006.257.11:07:58.23#ibcon#flushed, iclass 30, count 0 2006.257.11:07:58.23#ibcon#about to write, iclass 30, count 0 2006.257.11:07:58.23#ibcon#wrote, iclass 30, count 0 2006.257.11:07:58.23#ibcon#about to read 3, iclass 30, count 0 2006.257.11:07:58.25#ibcon#read 3, iclass 30, count 0 2006.257.11:07:58.25#ibcon#about to read 4, iclass 30, count 0 2006.257.11:07:58.25#ibcon#read 4, iclass 30, count 0 2006.257.11:07:58.25#ibcon#about to read 5, iclass 30, count 0 2006.257.11:07:58.25#ibcon#read 5, iclass 30, count 0 2006.257.11:07:58.25#ibcon#about to read 6, iclass 30, count 0 2006.257.11:07:58.25#ibcon#read 6, iclass 30, count 0 2006.257.11:07:58.25#ibcon#end of sib2, iclass 30, count 0 2006.257.11:07:58.25#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:07:58.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:07:58.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:07:58.25#ibcon#*before write, iclass 30, count 0 2006.257.11:07:58.25#ibcon#enter sib2, iclass 30, count 0 2006.257.11:07:58.25#ibcon#flushed, iclass 30, count 0 2006.257.11:07:58.25#ibcon#about to write, iclass 30, count 0 2006.257.11:07:58.25#ibcon#wrote, iclass 30, count 0 2006.257.11:07:58.25#ibcon#about to read 3, iclass 30, count 0 2006.257.11:07:58.29#ibcon#read 3, iclass 30, count 0 2006.257.11:07:58.29#ibcon#about to read 4, iclass 30, count 0 2006.257.11:07:58.29#ibcon#read 4, iclass 30, count 0 2006.257.11:07:58.29#ibcon#about to read 5, iclass 30, count 0 2006.257.11:07:58.29#ibcon#read 5, iclass 30, count 0 2006.257.11:07:58.29#ibcon#about to read 6, iclass 30, count 0 2006.257.11:07:58.29#ibcon#read 6, iclass 30, count 0 2006.257.11:07:58.29#ibcon#end of sib2, iclass 30, count 0 2006.257.11:07:58.29#ibcon#*after write, iclass 30, count 0 2006.257.11:07:58.29#ibcon#*before return 0, iclass 30, count 0 2006.257.11:07:58.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:58.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:07:58.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:07:58.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:07:58.29$vck44/vb=2,5 2006.257.11:07:58.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.11:07:58.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.11:07:58.29#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:58.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:58.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:58.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:58.35#ibcon#enter wrdev, iclass 32, count 2 2006.257.11:07:58.35#ibcon#first serial, iclass 32, count 2 2006.257.11:07:58.35#ibcon#enter sib2, iclass 32, count 2 2006.257.11:07:58.35#ibcon#flushed, iclass 32, count 2 2006.257.11:07:58.35#ibcon#about to write, iclass 32, count 2 2006.257.11:07:58.35#ibcon#wrote, iclass 32, count 2 2006.257.11:07:58.35#ibcon#about to read 3, iclass 32, count 2 2006.257.11:07:58.37#ibcon#read 3, iclass 32, count 2 2006.257.11:07:58.37#ibcon#about to read 4, iclass 32, count 2 2006.257.11:07:58.37#ibcon#read 4, iclass 32, count 2 2006.257.11:07:58.37#ibcon#about to read 5, iclass 32, count 2 2006.257.11:07:58.37#ibcon#read 5, iclass 32, count 2 2006.257.11:07:58.37#ibcon#about to read 6, iclass 32, count 2 2006.257.11:07:58.37#ibcon#read 6, iclass 32, count 2 2006.257.11:07:58.37#ibcon#end of sib2, iclass 32, count 2 2006.257.11:07:58.37#ibcon#*mode == 0, iclass 32, count 2 2006.257.11:07:58.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.11:07:58.37#ibcon#[27=AT02-05\r\n] 2006.257.11:07:58.37#ibcon#*before write, iclass 32, count 2 2006.257.11:07:58.37#ibcon#enter sib2, iclass 32, count 2 2006.257.11:07:58.37#ibcon#flushed, iclass 32, count 2 2006.257.11:07:58.37#ibcon#about to write, iclass 32, count 2 2006.257.11:07:58.37#ibcon#wrote, iclass 32, count 2 2006.257.11:07:58.37#ibcon#about to read 3, iclass 32, count 2 2006.257.11:07:58.40#ibcon#read 3, iclass 32, count 2 2006.257.11:07:58.40#ibcon#about to read 4, iclass 32, count 2 2006.257.11:07:58.40#ibcon#read 4, iclass 32, count 2 2006.257.11:07:58.40#ibcon#about to read 5, iclass 32, count 2 2006.257.11:07:58.40#ibcon#read 5, iclass 32, count 2 2006.257.11:07:58.40#ibcon#about to read 6, iclass 32, count 2 2006.257.11:07:58.40#ibcon#read 6, iclass 32, count 2 2006.257.11:07:58.40#ibcon#end of sib2, iclass 32, count 2 2006.257.11:07:58.40#ibcon#*after write, iclass 32, count 2 2006.257.11:07:58.40#ibcon#*before return 0, iclass 32, count 2 2006.257.11:07:58.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:58.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:07:58.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.11:07:58.40#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:58.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:58.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:58.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:58.52#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:07:58.52#ibcon#first serial, iclass 32, count 0 2006.257.11:07:58.52#ibcon#enter sib2, iclass 32, count 0 2006.257.11:07:58.52#ibcon#flushed, iclass 32, count 0 2006.257.11:07:58.52#ibcon#about to write, iclass 32, count 0 2006.257.11:07:58.52#ibcon#wrote, iclass 32, count 0 2006.257.11:07:58.52#ibcon#about to read 3, iclass 32, count 0 2006.257.11:07:58.54#ibcon#read 3, iclass 32, count 0 2006.257.11:07:58.54#ibcon#about to read 4, iclass 32, count 0 2006.257.11:07:58.54#ibcon#read 4, iclass 32, count 0 2006.257.11:07:58.54#ibcon#about to read 5, iclass 32, count 0 2006.257.11:07:58.54#ibcon#read 5, iclass 32, count 0 2006.257.11:07:58.54#ibcon#about to read 6, iclass 32, count 0 2006.257.11:07:58.54#ibcon#read 6, iclass 32, count 0 2006.257.11:07:58.54#ibcon#end of sib2, iclass 32, count 0 2006.257.11:07:58.54#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:07:58.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:07:58.54#ibcon#[27=USB\r\n] 2006.257.11:07:58.54#ibcon#*before write, iclass 32, count 0 2006.257.11:07:58.54#ibcon#enter sib2, iclass 32, count 0 2006.257.11:07:58.54#ibcon#flushed, iclass 32, count 0 2006.257.11:07:58.54#ibcon#about to write, iclass 32, count 0 2006.257.11:07:58.54#ibcon#wrote, iclass 32, count 0 2006.257.11:07:58.54#ibcon#about to read 3, iclass 32, count 0 2006.257.11:07:58.57#ibcon#read 3, iclass 32, count 0 2006.257.11:07:58.57#ibcon#about to read 4, iclass 32, count 0 2006.257.11:07:58.57#ibcon#read 4, iclass 32, count 0 2006.257.11:07:58.57#ibcon#about to read 5, iclass 32, count 0 2006.257.11:07:58.57#ibcon#read 5, iclass 32, count 0 2006.257.11:07:58.57#ibcon#about to read 6, iclass 32, count 0 2006.257.11:07:58.57#ibcon#read 6, iclass 32, count 0 2006.257.11:07:58.57#ibcon#end of sib2, iclass 32, count 0 2006.257.11:07:58.57#ibcon#*after write, iclass 32, count 0 2006.257.11:07:58.57#ibcon#*before return 0, iclass 32, count 0 2006.257.11:07:58.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:58.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:07:58.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:07:58.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:07:58.57$vck44/vblo=3,649.99 2006.257.11:07:58.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.11:07:58.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.11:07:58.57#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:58.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:58.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:58.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:58.57#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:07:58.57#ibcon#first serial, iclass 34, count 0 2006.257.11:07:58.57#ibcon#enter sib2, iclass 34, count 0 2006.257.11:07:58.57#ibcon#flushed, iclass 34, count 0 2006.257.11:07:58.57#ibcon#about to write, iclass 34, count 0 2006.257.11:07:58.57#ibcon#wrote, iclass 34, count 0 2006.257.11:07:58.57#ibcon#about to read 3, iclass 34, count 0 2006.257.11:07:58.59#ibcon#read 3, iclass 34, count 0 2006.257.11:07:58.59#ibcon#about to read 4, iclass 34, count 0 2006.257.11:07:58.59#ibcon#read 4, iclass 34, count 0 2006.257.11:07:58.59#ibcon#about to read 5, iclass 34, count 0 2006.257.11:07:58.59#ibcon#read 5, iclass 34, count 0 2006.257.11:07:58.59#ibcon#about to read 6, iclass 34, count 0 2006.257.11:07:58.59#ibcon#read 6, iclass 34, count 0 2006.257.11:07:58.59#ibcon#end of sib2, iclass 34, count 0 2006.257.11:07:58.59#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:07:58.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:07:58.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:07:58.59#ibcon#*before write, iclass 34, count 0 2006.257.11:07:58.59#ibcon#enter sib2, iclass 34, count 0 2006.257.11:07:58.59#ibcon#flushed, iclass 34, count 0 2006.257.11:07:58.59#ibcon#about to write, iclass 34, count 0 2006.257.11:07:58.59#ibcon#wrote, iclass 34, count 0 2006.257.11:07:58.59#ibcon#about to read 3, iclass 34, count 0 2006.257.11:07:58.63#ibcon#read 3, iclass 34, count 0 2006.257.11:07:58.63#ibcon#about to read 4, iclass 34, count 0 2006.257.11:07:58.63#ibcon#read 4, iclass 34, count 0 2006.257.11:07:58.63#ibcon#about to read 5, iclass 34, count 0 2006.257.11:07:58.63#ibcon#read 5, iclass 34, count 0 2006.257.11:07:58.63#ibcon#about to read 6, iclass 34, count 0 2006.257.11:07:58.63#ibcon#read 6, iclass 34, count 0 2006.257.11:07:58.63#ibcon#end of sib2, iclass 34, count 0 2006.257.11:07:58.63#ibcon#*after write, iclass 34, count 0 2006.257.11:07:58.63#ibcon#*before return 0, iclass 34, count 0 2006.257.11:07:58.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:58.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:07:58.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:07:58.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:07:58.63$vck44/vb=3,4 2006.257.11:07:58.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.11:07:58.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.11:07:58.63#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:58.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:58.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:58.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:58.69#ibcon#enter wrdev, iclass 36, count 2 2006.257.11:07:58.69#ibcon#first serial, iclass 36, count 2 2006.257.11:07:58.69#ibcon#enter sib2, iclass 36, count 2 2006.257.11:07:58.69#ibcon#flushed, iclass 36, count 2 2006.257.11:07:58.69#ibcon#about to write, iclass 36, count 2 2006.257.11:07:58.69#ibcon#wrote, iclass 36, count 2 2006.257.11:07:58.69#ibcon#about to read 3, iclass 36, count 2 2006.257.11:07:58.71#ibcon#read 3, iclass 36, count 2 2006.257.11:07:58.71#ibcon#about to read 4, iclass 36, count 2 2006.257.11:07:58.71#ibcon#read 4, iclass 36, count 2 2006.257.11:07:58.71#ibcon#about to read 5, iclass 36, count 2 2006.257.11:07:58.71#ibcon#read 5, iclass 36, count 2 2006.257.11:07:58.71#ibcon#about to read 6, iclass 36, count 2 2006.257.11:07:58.71#ibcon#read 6, iclass 36, count 2 2006.257.11:07:58.71#ibcon#end of sib2, iclass 36, count 2 2006.257.11:07:58.71#ibcon#*mode == 0, iclass 36, count 2 2006.257.11:07:58.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.11:07:58.71#ibcon#[27=AT03-04\r\n] 2006.257.11:07:58.71#ibcon#*before write, iclass 36, count 2 2006.257.11:07:58.71#ibcon#enter sib2, iclass 36, count 2 2006.257.11:07:58.71#ibcon#flushed, iclass 36, count 2 2006.257.11:07:58.71#ibcon#about to write, iclass 36, count 2 2006.257.11:07:58.71#ibcon#wrote, iclass 36, count 2 2006.257.11:07:58.71#ibcon#about to read 3, iclass 36, count 2 2006.257.11:07:58.74#ibcon#read 3, iclass 36, count 2 2006.257.11:07:58.74#ibcon#about to read 4, iclass 36, count 2 2006.257.11:07:58.74#ibcon#read 4, iclass 36, count 2 2006.257.11:07:58.74#ibcon#about to read 5, iclass 36, count 2 2006.257.11:07:58.74#ibcon#read 5, iclass 36, count 2 2006.257.11:07:58.74#ibcon#about to read 6, iclass 36, count 2 2006.257.11:07:58.74#ibcon#read 6, iclass 36, count 2 2006.257.11:07:58.74#ibcon#end of sib2, iclass 36, count 2 2006.257.11:07:58.74#ibcon#*after write, iclass 36, count 2 2006.257.11:07:58.74#ibcon#*before return 0, iclass 36, count 2 2006.257.11:07:58.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:58.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:07:58.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.11:07:58.74#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:58.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:58.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:58.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:58.86#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:07:58.86#ibcon#first serial, iclass 36, count 0 2006.257.11:07:58.86#ibcon#enter sib2, iclass 36, count 0 2006.257.11:07:58.86#ibcon#flushed, iclass 36, count 0 2006.257.11:07:58.86#ibcon#about to write, iclass 36, count 0 2006.257.11:07:58.86#ibcon#wrote, iclass 36, count 0 2006.257.11:07:58.86#ibcon#about to read 3, iclass 36, count 0 2006.257.11:07:58.88#ibcon#read 3, iclass 36, count 0 2006.257.11:07:58.88#ibcon#about to read 4, iclass 36, count 0 2006.257.11:07:58.88#ibcon#read 4, iclass 36, count 0 2006.257.11:07:58.88#ibcon#about to read 5, iclass 36, count 0 2006.257.11:07:58.88#ibcon#read 5, iclass 36, count 0 2006.257.11:07:58.88#ibcon#about to read 6, iclass 36, count 0 2006.257.11:07:58.88#ibcon#read 6, iclass 36, count 0 2006.257.11:07:58.88#ibcon#end of sib2, iclass 36, count 0 2006.257.11:07:58.88#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:07:58.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:07:58.88#ibcon#[27=USB\r\n] 2006.257.11:07:58.88#ibcon#*before write, iclass 36, count 0 2006.257.11:07:58.88#ibcon#enter sib2, iclass 36, count 0 2006.257.11:07:58.88#ibcon#flushed, iclass 36, count 0 2006.257.11:07:58.88#ibcon#about to write, iclass 36, count 0 2006.257.11:07:58.88#ibcon#wrote, iclass 36, count 0 2006.257.11:07:58.88#ibcon#about to read 3, iclass 36, count 0 2006.257.11:07:58.91#ibcon#read 3, iclass 36, count 0 2006.257.11:07:58.91#ibcon#about to read 4, iclass 36, count 0 2006.257.11:07:58.91#ibcon#read 4, iclass 36, count 0 2006.257.11:07:58.91#ibcon#about to read 5, iclass 36, count 0 2006.257.11:07:58.91#ibcon#read 5, iclass 36, count 0 2006.257.11:07:58.91#ibcon#about to read 6, iclass 36, count 0 2006.257.11:07:58.91#ibcon#read 6, iclass 36, count 0 2006.257.11:07:58.91#ibcon#end of sib2, iclass 36, count 0 2006.257.11:07:58.91#ibcon#*after write, iclass 36, count 0 2006.257.11:07:58.91#ibcon#*before return 0, iclass 36, count 0 2006.257.11:07:58.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:58.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:07:58.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:07:58.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:07:58.91$vck44/vblo=4,679.99 2006.257.11:07:58.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.11:07:58.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.11:07:58.91#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:58.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:58.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:58.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:58.91#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:07:58.91#ibcon#first serial, iclass 38, count 0 2006.257.11:07:58.91#ibcon#enter sib2, iclass 38, count 0 2006.257.11:07:58.91#ibcon#flushed, iclass 38, count 0 2006.257.11:07:58.91#ibcon#about to write, iclass 38, count 0 2006.257.11:07:58.91#ibcon#wrote, iclass 38, count 0 2006.257.11:07:58.91#ibcon#about to read 3, iclass 38, count 0 2006.257.11:07:58.93#ibcon#read 3, iclass 38, count 0 2006.257.11:07:58.93#ibcon#about to read 4, iclass 38, count 0 2006.257.11:07:58.93#ibcon#read 4, iclass 38, count 0 2006.257.11:07:58.93#ibcon#about to read 5, iclass 38, count 0 2006.257.11:07:58.93#ibcon#read 5, iclass 38, count 0 2006.257.11:07:58.93#ibcon#about to read 6, iclass 38, count 0 2006.257.11:07:58.93#ibcon#read 6, iclass 38, count 0 2006.257.11:07:58.93#ibcon#end of sib2, iclass 38, count 0 2006.257.11:07:58.93#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:07:58.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:07:58.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:07:58.93#ibcon#*before write, iclass 38, count 0 2006.257.11:07:58.93#ibcon#enter sib2, iclass 38, count 0 2006.257.11:07:58.93#ibcon#flushed, iclass 38, count 0 2006.257.11:07:58.93#ibcon#about to write, iclass 38, count 0 2006.257.11:07:58.93#ibcon#wrote, iclass 38, count 0 2006.257.11:07:58.93#ibcon#about to read 3, iclass 38, count 0 2006.257.11:07:58.97#ibcon#read 3, iclass 38, count 0 2006.257.11:07:58.97#ibcon#about to read 4, iclass 38, count 0 2006.257.11:07:58.97#ibcon#read 4, iclass 38, count 0 2006.257.11:07:58.97#ibcon#about to read 5, iclass 38, count 0 2006.257.11:07:58.97#ibcon#read 5, iclass 38, count 0 2006.257.11:07:58.97#ibcon#about to read 6, iclass 38, count 0 2006.257.11:07:58.97#ibcon#read 6, iclass 38, count 0 2006.257.11:07:58.97#ibcon#end of sib2, iclass 38, count 0 2006.257.11:07:58.97#ibcon#*after write, iclass 38, count 0 2006.257.11:07:58.97#ibcon#*before return 0, iclass 38, count 0 2006.257.11:07:58.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:58.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:07:58.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:07:58.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:07:58.97$vck44/vb=4,5 2006.257.11:07:58.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.11:07:58.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.11:07:58.97#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:58.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:59.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:59.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:59.03#ibcon#enter wrdev, iclass 40, count 2 2006.257.11:07:59.03#ibcon#first serial, iclass 40, count 2 2006.257.11:07:59.03#ibcon#enter sib2, iclass 40, count 2 2006.257.11:07:59.03#ibcon#flushed, iclass 40, count 2 2006.257.11:07:59.03#ibcon#about to write, iclass 40, count 2 2006.257.11:07:59.03#ibcon#wrote, iclass 40, count 2 2006.257.11:07:59.03#ibcon#about to read 3, iclass 40, count 2 2006.257.11:07:59.05#ibcon#read 3, iclass 40, count 2 2006.257.11:07:59.05#ibcon#about to read 4, iclass 40, count 2 2006.257.11:07:59.05#ibcon#read 4, iclass 40, count 2 2006.257.11:07:59.05#ibcon#about to read 5, iclass 40, count 2 2006.257.11:07:59.05#ibcon#read 5, iclass 40, count 2 2006.257.11:07:59.05#ibcon#about to read 6, iclass 40, count 2 2006.257.11:07:59.05#ibcon#read 6, iclass 40, count 2 2006.257.11:07:59.05#ibcon#end of sib2, iclass 40, count 2 2006.257.11:07:59.05#ibcon#*mode == 0, iclass 40, count 2 2006.257.11:07:59.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.11:07:59.05#ibcon#[27=AT04-05\r\n] 2006.257.11:07:59.05#ibcon#*before write, iclass 40, count 2 2006.257.11:07:59.05#ibcon#enter sib2, iclass 40, count 2 2006.257.11:07:59.05#ibcon#flushed, iclass 40, count 2 2006.257.11:07:59.05#ibcon#about to write, iclass 40, count 2 2006.257.11:07:59.05#ibcon#wrote, iclass 40, count 2 2006.257.11:07:59.05#ibcon#about to read 3, iclass 40, count 2 2006.257.11:07:59.08#ibcon#read 3, iclass 40, count 2 2006.257.11:07:59.08#ibcon#about to read 4, iclass 40, count 2 2006.257.11:07:59.08#ibcon#read 4, iclass 40, count 2 2006.257.11:07:59.08#ibcon#about to read 5, iclass 40, count 2 2006.257.11:07:59.08#ibcon#read 5, iclass 40, count 2 2006.257.11:07:59.08#ibcon#about to read 6, iclass 40, count 2 2006.257.11:07:59.08#ibcon#read 6, iclass 40, count 2 2006.257.11:07:59.08#ibcon#end of sib2, iclass 40, count 2 2006.257.11:07:59.08#ibcon#*after write, iclass 40, count 2 2006.257.11:07:59.08#ibcon#*before return 0, iclass 40, count 2 2006.257.11:07:59.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:59.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:07:59.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.11:07:59.08#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:59.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:59.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:59.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:59.20#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:07:59.20#ibcon#first serial, iclass 40, count 0 2006.257.11:07:59.20#ibcon#enter sib2, iclass 40, count 0 2006.257.11:07:59.20#ibcon#flushed, iclass 40, count 0 2006.257.11:07:59.20#ibcon#about to write, iclass 40, count 0 2006.257.11:07:59.20#ibcon#wrote, iclass 40, count 0 2006.257.11:07:59.20#ibcon#about to read 3, iclass 40, count 0 2006.257.11:07:59.22#ibcon#read 3, iclass 40, count 0 2006.257.11:07:59.22#ibcon#about to read 4, iclass 40, count 0 2006.257.11:07:59.22#ibcon#read 4, iclass 40, count 0 2006.257.11:07:59.22#ibcon#about to read 5, iclass 40, count 0 2006.257.11:07:59.22#ibcon#read 5, iclass 40, count 0 2006.257.11:07:59.22#ibcon#about to read 6, iclass 40, count 0 2006.257.11:07:59.22#ibcon#read 6, iclass 40, count 0 2006.257.11:07:59.22#ibcon#end of sib2, iclass 40, count 0 2006.257.11:07:59.22#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:07:59.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:07:59.22#ibcon#[27=USB\r\n] 2006.257.11:07:59.22#ibcon#*before write, iclass 40, count 0 2006.257.11:07:59.22#ibcon#enter sib2, iclass 40, count 0 2006.257.11:07:59.22#ibcon#flushed, iclass 40, count 0 2006.257.11:07:59.22#ibcon#about to write, iclass 40, count 0 2006.257.11:07:59.22#ibcon#wrote, iclass 40, count 0 2006.257.11:07:59.22#ibcon#about to read 3, iclass 40, count 0 2006.257.11:07:59.25#ibcon#read 3, iclass 40, count 0 2006.257.11:07:59.25#ibcon#about to read 4, iclass 40, count 0 2006.257.11:07:59.25#ibcon#read 4, iclass 40, count 0 2006.257.11:07:59.25#ibcon#about to read 5, iclass 40, count 0 2006.257.11:07:59.25#ibcon#read 5, iclass 40, count 0 2006.257.11:07:59.25#ibcon#about to read 6, iclass 40, count 0 2006.257.11:07:59.25#ibcon#read 6, iclass 40, count 0 2006.257.11:07:59.25#ibcon#end of sib2, iclass 40, count 0 2006.257.11:07:59.25#ibcon#*after write, iclass 40, count 0 2006.257.11:07:59.25#ibcon#*before return 0, iclass 40, count 0 2006.257.11:07:59.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:59.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:07:59.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:07:59.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:07:59.25$vck44/vblo=5,709.99 2006.257.11:07:59.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.11:07:59.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.11:07:59.25#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:59.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:59.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:59.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:59.25#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:07:59.25#ibcon#first serial, iclass 4, count 0 2006.257.11:07:59.25#ibcon#enter sib2, iclass 4, count 0 2006.257.11:07:59.25#ibcon#flushed, iclass 4, count 0 2006.257.11:07:59.25#ibcon#about to write, iclass 4, count 0 2006.257.11:07:59.25#ibcon#wrote, iclass 4, count 0 2006.257.11:07:59.25#ibcon#about to read 3, iclass 4, count 0 2006.257.11:07:59.27#ibcon#read 3, iclass 4, count 0 2006.257.11:07:59.27#ibcon#about to read 4, iclass 4, count 0 2006.257.11:07:59.27#ibcon#read 4, iclass 4, count 0 2006.257.11:07:59.27#ibcon#about to read 5, iclass 4, count 0 2006.257.11:07:59.27#ibcon#read 5, iclass 4, count 0 2006.257.11:07:59.27#ibcon#about to read 6, iclass 4, count 0 2006.257.11:07:59.27#ibcon#read 6, iclass 4, count 0 2006.257.11:07:59.27#ibcon#end of sib2, iclass 4, count 0 2006.257.11:07:59.27#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:07:59.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:07:59.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:07:59.27#ibcon#*before write, iclass 4, count 0 2006.257.11:07:59.27#ibcon#enter sib2, iclass 4, count 0 2006.257.11:07:59.27#ibcon#flushed, iclass 4, count 0 2006.257.11:07:59.27#ibcon#about to write, iclass 4, count 0 2006.257.11:07:59.27#ibcon#wrote, iclass 4, count 0 2006.257.11:07:59.27#ibcon#about to read 3, iclass 4, count 0 2006.257.11:07:59.31#ibcon#read 3, iclass 4, count 0 2006.257.11:07:59.31#ibcon#about to read 4, iclass 4, count 0 2006.257.11:07:59.31#ibcon#read 4, iclass 4, count 0 2006.257.11:07:59.31#ibcon#about to read 5, iclass 4, count 0 2006.257.11:07:59.31#ibcon#read 5, iclass 4, count 0 2006.257.11:07:59.31#ibcon#about to read 6, iclass 4, count 0 2006.257.11:07:59.31#ibcon#read 6, iclass 4, count 0 2006.257.11:07:59.31#ibcon#end of sib2, iclass 4, count 0 2006.257.11:07:59.31#ibcon#*after write, iclass 4, count 0 2006.257.11:07:59.31#ibcon#*before return 0, iclass 4, count 0 2006.257.11:07:59.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:59.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:07:59.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:07:59.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:07:59.31$vck44/vb=5,4 2006.257.11:07:59.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.11:07:59.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.11:07:59.31#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:59.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:59.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:59.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:59.37#ibcon#enter wrdev, iclass 6, count 2 2006.257.11:07:59.37#ibcon#first serial, iclass 6, count 2 2006.257.11:07:59.37#ibcon#enter sib2, iclass 6, count 2 2006.257.11:07:59.37#ibcon#flushed, iclass 6, count 2 2006.257.11:07:59.37#ibcon#about to write, iclass 6, count 2 2006.257.11:07:59.37#ibcon#wrote, iclass 6, count 2 2006.257.11:07:59.37#ibcon#about to read 3, iclass 6, count 2 2006.257.11:07:59.39#ibcon#read 3, iclass 6, count 2 2006.257.11:07:59.39#ibcon#about to read 4, iclass 6, count 2 2006.257.11:07:59.39#ibcon#read 4, iclass 6, count 2 2006.257.11:07:59.39#ibcon#about to read 5, iclass 6, count 2 2006.257.11:07:59.39#ibcon#read 5, iclass 6, count 2 2006.257.11:07:59.39#ibcon#about to read 6, iclass 6, count 2 2006.257.11:07:59.39#ibcon#read 6, iclass 6, count 2 2006.257.11:07:59.39#ibcon#end of sib2, iclass 6, count 2 2006.257.11:07:59.39#ibcon#*mode == 0, iclass 6, count 2 2006.257.11:07:59.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.11:07:59.39#ibcon#[27=AT05-04\r\n] 2006.257.11:07:59.39#ibcon#*before write, iclass 6, count 2 2006.257.11:07:59.39#ibcon#enter sib2, iclass 6, count 2 2006.257.11:07:59.39#ibcon#flushed, iclass 6, count 2 2006.257.11:07:59.39#ibcon#about to write, iclass 6, count 2 2006.257.11:07:59.39#ibcon#wrote, iclass 6, count 2 2006.257.11:07:59.39#ibcon#about to read 3, iclass 6, count 2 2006.257.11:07:59.42#ibcon#read 3, iclass 6, count 2 2006.257.11:07:59.42#ibcon#about to read 4, iclass 6, count 2 2006.257.11:07:59.42#ibcon#read 4, iclass 6, count 2 2006.257.11:07:59.42#ibcon#about to read 5, iclass 6, count 2 2006.257.11:07:59.42#ibcon#read 5, iclass 6, count 2 2006.257.11:07:59.42#ibcon#about to read 6, iclass 6, count 2 2006.257.11:07:59.42#ibcon#read 6, iclass 6, count 2 2006.257.11:07:59.42#ibcon#end of sib2, iclass 6, count 2 2006.257.11:07:59.42#ibcon#*after write, iclass 6, count 2 2006.257.11:07:59.42#ibcon#*before return 0, iclass 6, count 2 2006.257.11:07:59.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:59.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:07:59.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.11:07:59.42#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:59.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:59.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:59.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:59.54#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:07:59.54#ibcon#first serial, iclass 6, count 0 2006.257.11:07:59.54#ibcon#enter sib2, iclass 6, count 0 2006.257.11:07:59.54#ibcon#flushed, iclass 6, count 0 2006.257.11:07:59.54#ibcon#about to write, iclass 6, count 0 2006.257.11:07:59.54#ibcon#wrote, iclass 6, count 0 2006.257.11:07:59.54#ibcon#about to read 3, iclass 6, count 0 2006.257.11:07:59.56#ibcon#read 3, iclass 6, count 0 2006.257.11:07:59.56#ibcon#about to read 4, iclass 6, count 0 2006.257.11:07:59.56#ibcon#read 4, iclass 6, count 0 2006.257.11:07:59.56#ibcon#about to read 5, iclass 6, count 0 2006.257.11:07:59.56#ibcon#read 5, iclass 6, count 0 2006.257.11:07:59.56#ibcon#about to read 6, iclass 6, count 0 2006.257.11:07:59.56#ibcon#read 6, iclass 6, count 0 2006.257.11:07:59.56#ibcon#end of sib2, iclass 6, count 0 2006.257.11:07:59.56#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:07:59.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:07:59.56#ibcon#[27=USB\r\n] 2006.257.11:07:59.56#ibcon#*before write, iclass 6, count 0 2006.257.11:07:59.56#ibcon#enter sib2, iclass 6, count 0 2006.257.11:07:59.56#ibcon#flushed, iclass 6, count 0 2006.257.11:07:59.56#ibcon#about to write, iclass 6, count 0 2006.257.11:07:59.56#ibcon#wrote, iclass 6, count 0 2006.257.11:07:59.56#ibcon#about to read 3, iclass 6, count 0 2006.257.11:07:59.59#ibcon#read 3, iclass 6, count 0 2006.257.11:07:59.59#ibcon#about to read 4, iclass 6, count 0 2006.257.11:07:59.59#ibcon#read 4, iclass 6, count 0 2006.257.11:07:59.59#ibcon#about to read 5, iclass 6, count 0 2006.257.11:07:59.59#ibcon#read 5, iclass 6, count 0 2006.257.11:07:59.59#ibcon#about to read 6, iclass 6, count 0 2006.257.11:07:59.59#ibcon#read 6, iclass 6, count 0 2006.257.11:07:59.59#ibcon#end of sib2, iclass 6, count 0 2006.257.11:07:59.59#ibcon#*after write, iclass 6, count 0 2006.257.11:07:59.59#ibcon#*before return 0, iclass 6, count 0 2006.257.11:07:59.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:59.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:07:59.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:07:59.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:07:59.59$vck44/vblo=6,719.99 2006.257.11:07:59.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.11:07:59.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.11:07:59.59#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:59.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:59.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:59.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:59.59#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:07:59.59#ibcon#first serial, iclass 10, count 0 2006.257.11:07:59.59#ibcon#enter sib2, iclass 10, count 0 2006.257.11:07:59.59#ibcon#flushed, iclass 10, count 0 2006.257.11:07:59.59#ibcon#about to write, iclass 10, count 0 2006.257.11:07:59.59#ibcon#wrote, iclass 10, count 0 2006.257.11:07:59.59#ibcon#about to read 3, iclass 10, count 0 2006.257.11:07:59.61#ibcon#read 3, iclass 10, count 0 2006.257.11:07:59.61#ibcon#about to read 4, iclass 10, count 0 2006.257.11:07:59.61#ibcon#read 4, iclass 10, count 0 2006.257.11:07:59.61#ibcon#about to read 5, iclass 10, count 0 2006.257.11:07:59.61#ibcon#read 5, iclass 10, count 0 2006.257.11:07:59.61#ibcon#about to read 6, iclass 10, count 0 2006.257.11:07:59.61#ibcon#read 6, iclass 10, count 0 2006.257.11:07:59.61#ibcon#end of sib2, iclass 10, count 0 2006.257.11:07:59.61#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:07:59.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:07:59.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:07:59.61#ibcon#*before write, iclass 10, count 0 2006.257.11:07:59.61#ibcon#enter sib2, iclass 10, count 0 2006.257.11:07:59.61#ibcon#flushed, iclass 10, count 0 2006.257.11:07:59.61#ibcon#about to write, iclass 10, count 0 2006.257.11:07:59.61#ibcon#wrote, iclass 10, count 0 2006.257.11:07:59.61#ibcon#about to read 3, iclass 10, count 0 2006.257.11:07:59.65#ibcon#read 3, iclass 10, count 0 2006.257.11:07:59.65#ibcon#about to read 4, iclass 10, count 0 2006.257.11:07:59.65#ibcon#read 4, iclass 10, count 0 2006.257.11:07:59.65#ibcon#about to read 5, iclass 10, count 0 2006.257.11:07:59.65#ibcon#read 5, iclass 10, count 0 2006.257.11:07:59.65#ibcon#about to read 6, iclass 10, count 0 2006.257.11:07:59.65#ibcon#read 6, iclass 10, count 0 2006.257.11:07:59.65#ibcon#end of sib2, iclass 10, count 0 2006.257.11:07:59.65#ibcon#*after write, iclass 10, count 0 2006.257.11:07:59.65#ibcon#*before return 0, iclass 10, count 0 2006.257.11:07:59.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:59.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:07:59.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:07:59.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:07:59.65$vck44/vb=6,4 2006.257.11:07:59.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.11:07:59.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.11:07:59.65#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:59.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:59.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:59.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:59.71#ibcon#enter wrdev, iclass 12, count 2 2006.257.11:07:59.71#ibcon#first serial, iclass 12, count 2 2006.257.11:07:59.71#ibcon#enter sib2, iclass 12, count 2 2006.257.11:07:59.71#ibcon#flushed, iclass 12, count 2 2006.257.11:07:59.71#ibcon#about to write, iclass 12, count 2 2006.257.11:07:59.71#ibcon#wrote, iclass 12, count 2 2006.257.11:07:59.71#ibcon#about to read 3, iclass 12, count 2 2006.257.11:07:59.73#ibcon#read 3, iclass 12, count 2 2006.257.11:07:59.73#ibcon#about to read 4, iclass 12, count 2 2006.257.11:07:59.73#ibcon#read 4, iclass 12, count 2 2006.257.11:07:59.73#ibcon#about to read 5, iclass 12, count 2 2006.257.11:07:59.73#ibcon#read 5, iclass 12, count 2 2006.257.11:07:59.73#ibcon#about to read 6, iclass 12, count 2 2006.257.11:07:59.73#ibcon#read 6, iclass 12, count 2 2006.257.11:07:59.73#ibcon#end of sib2, iclass 12, count 2 2006.257.11:07:59.73#ibcon#*mode == 0, iclass 12, count 2 2006.257.11:07:59.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.11:07:59.73#ibcon#[27=AT06-04\r\n] 2006.257.11:07:59.73#ibcon#*before write, iclass 12, count 2 2006.257.11:07:59.73#ibcon#enter sib2, iclass 12, count 2 2006.257.11:07:59.73#ibcon#flushed, iclass 12, count 2 2006.257.11:07:59.73#ibcon#about to write, iclass 12, count 2 2006.257.11:07:59.73#ibcon#wrote, iclass 12, count 2 2006.257.11:07:59.73#ibcon#about to read 3, iclass 12, count 2 2006.257.11:07:59.76#ibcon#read 3, iclass 12, count 2 2006.257.11:07:59.76#ibcon#about to read 4, iclass 12, count 2 2006.257.11:07:59.76#ibcon#read 4, iclass 12, count 2 2006.257.11:07:59.76#ibcon#about to read 5, iclass 12, count 2 2006.257.11:07:59.76#ibcon#read 5, iclass 12, count 2 2006.257.11:07:59.76#ibcon#about to read 6, iclass 12, count 2 2006.257.11:07:59.76#ibcon#read 6, iclass 12, count 2 2006.257.11:07:59.76#ibcon#end of sib2, iclass 12, count 2 2006.257.11:07:59.76#ibcon#*after write, iclass 12, count 2 2006.257.11:07:59.76#ibcon#*before return 0, iclass 12, count 2 2006.257.11:07:59.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:59.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:07:59.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.11:07:59.76#ibcon#ireg 7 cls_cnt 0 2006.257.11:07:59.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:59.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:59.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:59.88#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:07:59.88#ibcon#first serial, iclass 12, count 0 2006.257.11:07:59.88#ibcon#enter sib2, iclass 12, count 0 2006.257.11:07:59.88#ibcon#flushed, iclass 12, count 0 2006.257.11:07:59.88#ibcon#about to write, iclass 12, count 0 2006.257.11:07:59.88#ibcon#wrote, iclass 12, count 0 2006.257.11:07:59.88#ibcon#about to read 3, iclass 12, count 0 2006.257.11:07:59.90#ibcon#read 3, iclass 12, count 0 2006.257.11:07:59.90#ibcon#about to read 4, iclass 12, count 0 2006.257.11:07:59.90#ibcon#read 4, iclass 12, count 0 2006.257.11:07:59.90#ibcon#about to read 5, iclass 12, count 0 2006.257.11:07:59.90#ibcon#read 5, iclass 12, count 0 2006.257.11:07:59.90#ibcon#about to read 6, iclass 12, count 0 2006.257.11:07:59.90#ibcon#read 6, iclass 12, count 0 2006.257.11:07:59.90#ibcon#end of sib2, iclass 12, count 0 2006.257.11:07:59.90#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:07:59.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:07:59.90#ibcon#[27=USB\r\n] 2006.257.11:07:59.90#ibcon#*before write, iclass 12, count 0 2006.257.11:07:59.90#ibcon#enter sib2, iclass 12, count 0 2006.257.11:07:59.90#ibcon#flushed, iclass 12, count 0 2006.257.11:07:59.90#ibcon#about to write, iclass 12, count 0 2006.257.11:07:59.90#ibcon#wrote, iclass 12, count 0 2006.257.11:07:59.90#ibcon#about to read 3, iclass 12, count 0 2006.257.11:07:59.93#ibcon#read 3, iclass 12, count 0 2006.257.11:07:59.93#ibcon#about to read 4, iclass 12, count 0 2006.257.11:07:59.93#ibcon#read 4, iclass 12, count 0 2006.257.11:07:59.93#ibcon#about to read 5, iclass 12, count 0 2006.257.11:07:59.93#ibcon#read 5, iclass 12, count 0 2006.257.11:07:59.93#ibcon#about to read 6, iclass 12, count 0 2006.257.11:07:59.93#ibcon#read 6, iclass 12, count 0 2006.257.11:07:59.93#ibcon#end of sib2, iclass 12, count 0 2006.257.11:07:59.93#ibcon#*after write, iclass 12, count 0 2006.257.11:07:59.93#ibcon#*before return 0, iclass 12, count 0 2006.257.11:07:59.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:59.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:07:59.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:07:59.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:07:59.93$vck44/vblo=7,734.99 2006.257.11:07:59.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.11:07:59.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.11:07:59.93#ibcon#ireg 17 cls_cnt 0 2006.257.11:07:59.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:59.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:59.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:59.93#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:07:59.93#ibcon#first serial, iclass 14, count 0 2006.257.11:07:59.93#ibcon#enter sib2, iclass 14, count 0 2006.257.11:07:59.93#ibcon#flushed, iclass 14, count 0 2006.257.11:07:59.93#ibcon#about to write, iclass 14, count 0 2006.257.11:07:59.93#ibcon#wrote, iclass 14, count 0 2006.257.11:07:59.93#ibcon#about to read 3, iclass 14, count 0 2006.257.11:07:59.95#ibcon#read 3, iclass 14, count 0 2006.257.11:07:59.95#ibcon#about to read 4, iclass 14, count 0 2006.257.11:07:59.95#ibcon#read 4, iclass 14, count 0 2006.257.11:07:59.95#ibcon#about to read 5, iclass 14, count 0 2006.257.11:07:59.95#ibcon#read 5, iclass 14, count 0 2006.257.11:07:59.95#ibcon#about to read 6, iclass 14, count 0 2006.257.11:07:59.95#ibcon#read 6, iclass 14, count 0 2006.257.11:07:59.95#ibcon#end of sib2, iclass 14, count 0 2006.257.11:07:59.95#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:07:59.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:07:59.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:07:59.95#ibcon#*before write, iclass 14, count 0 2006.257.11:07:59.95#ibcon#enter sib2, iclass 14, count 0 2006.257.11:07:59.95#ibcon#flushed, iclass 14, count 0 2006.257.11:07:59.95#ibcon#about to write, iclass 14, count 0 2006.257.11:07:59.95#ibcon#wrote, iclass 14, count 0 2006.257.11:07:59.95#ibcon#about to read 3, iclass 14, count 0 2006.257.11:07:59.99#ibcon#read 3, iclass 14, count 0 2006.257.11:07:59.99#ibcon#about to read 4, iclass 14, count 0 2006.257.11:07:59.99#ibcon#read 4, iclass 14, count 0 2006.257.11:07:59.99#ibcon#about to read 5, iclass 14, count 0 2006.257.11:07:59.99#ibcon#read 5, iclass 14, count 0 2006.257.11:07:59.99#ibcon#about to read 6, iclass 14, count 0 2006.257.11:07:59.99#ibcon#read 6, iclass 14, count 0 2006.257.11:07:59.99#ibcon#end of sib2, iclass 14, count 0 2006.257.11:07:59.99#ibcon#*after write, iclass 14, count 0 2006.257.11:07:59.99#ibcon#*before return 0, iclass 14, count 0 2006.257.11:07:59.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:59.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:07:59.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:07:59.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:07:59.99$vck44/vb=7,4 2006.257.11:07:59.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.11:07:59.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.11:07:59.99#ibcon#ireg 11 cls_cnt 2 2006.257.11:07:59.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:08:00.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:08:00.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:08:00.05#ibcon#enter wrdev, iclass 16, count 2 2006.257.11:08:00.05#ibcon#first serial, iclass 16, count 2 2006.257.11:08:00.05#ibcon#enter sib2, iclass 16, count 2 2006.257.11:08:00.05#ibcon#flushed, iclass 16, count 2 2006.257.11:08:00.05#ibcon#about to write, iclass 16, count 2 2006.257.11:08:00.05#ibcon#wrote, iclass 16, count 2 2006.257.11:08:00.05#ibcon#about to read 3, iclass 16, count 2 2006.257.11:08:00.07#ibcon#read 3, iclass 16, count 2 2006.257.11:08:00.07#ibcon#about to read 4, iclass 16, count 2 2006.257.11:08:00.07#ibcon#read 4, iclass 16, count 2 2006.257.11:08:00.07#ibcon#about to read 5, iclass 16, count 2 2006.257.11:08:00.07#ibcon#read 5, iclass 16, count 2 2006.257.11:08:00.07#ibcon#about to read 6, iclass 16, count 2 2006.257.11:08:00.07#ibcon#read 6, iclass 16, count 2 2006.257.11:08:00.07#ibcon#end of sib2, iclass 16, count 2 2006.257.11:08:00.07#ibcon#*mode == 0, iclass 16, count 2 2006.257.11:08:00.07#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.11:08:00.07#ibcon#[27=AT07-04\r\n] 2006.257.11:08:00.07#ibcon#*before write, iclass 16, count 2 2006.257.11:08:00.07#ibcon#enter sib2, iclass 16, count 2 2006.257.11:08:00.07#ibcon#flushed, iclass 16, count 2 2006.257.11:08:00.07#ibcon#about to write, iclass 16, count 2 2006.257.11:08:00.07#ibcon#wrote, iclass 16, count 2 2006.257.11:08:00.07#ibcon#about to read 3, iclass 16, count 2 2006.257.11:08:00.10#ibcon#read 3, iclass 16, count 2 2006.257.11:08:00.10#ibcon#about to read 4, iclass 16, count 2 2006.257.11:08:00.10#ibcon#read 4, iclass 16, count 2 2006.257.11:08:00.10#ibcon#about to read 5, iclass 16, count 2 2006.257.11:08:00.10#ibcon#read 5, iclass 16, count 2 2006.257.11:08:00.10#ibcon#about to read 6, iclass 16, count 2 2006.257.11:08:00.10#ibcon#read 6, iclass 16, count 2 2006.257.11:08:00.10#ibcon#end of sib2, iclass 16, count 2 2006.257.11:08:00.10#ibcon#*after write, iclass 16, count 2 2006.257.11:08:00.10#ibcon#*before return 0, iclass 16, count 2 2006.257.11:08:00.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:08:00.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:08:00.10#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.11:08:00.10#ibcon#ireg 7 cls_cnt 0 2006.257.11:08:00.10#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:08:00.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:08:00.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:08:00.22#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:08:00.22#ibcon#first serial, iclass 16, count 0 2006.257.11:08:00.22#ibcon#enter sib2, iclass 16, count 0 2006.257.11:08:00.22#ibcon#flushed, iclass 16, count 0 2006.257.11:08:00.22#ibcon#about to write, iclass 16, count 0 2006.257.11:08:00.22#ibcon#wrote, iclass 16, count 0 2006.257.11:08:00.22#ibcon#about to read 3, iclass 16, count 0 2006.257.11:08:00.24#ibcon#read 3, iclass 16, count 0 2006.257.11:08:00.24#ibcon#about to read 4, iclass 16, count 0 2006.257.11:08:00.24#ibcon#read 4, iclass 16, count 0 2006.257.11:08:00.24#ibcon#about to read 5, iclass 16, count 0 2006.257.11:08:00.24#ibcon#read 5, iclass 16, count 0 2006.257.11:08:00.24#ibcon#about to read 6, iclass 16, count 0 2006.257.11:08:00.24#ibcon#read 6, iclass 16, count 0 2006.257.11:08:00.24#ibcon#end of sib2, iclass 16, count 0 2006.257.11:08:00.24#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:08:00.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:08:00.24#ibcon#[27=USB\r\n] 2006.257.11:08:00.24#ibcon#*before write, iclass 16, count 0 2006.257.11:08:00.24#ibcon#enter sib2, iclass 16, count 0 2006.257.11:08:00.24#ibcon#flushed, iclass 16, count 0 2006.257.11:08:00.24#ibcon#about to write, iclass 16, count 0 2006.257.11:08:00.24#ibcon#wrote, iclass 16, count 0 2006.257.11:08:00.24#ibcon#about to read 3, iclass 16, count 0 2006.257.11:08:00.27#ibcon#read 3, iclass 16, count 0 2006.257.11:08:00.27#ibcon#about to read 4, iclass 16, count 0 2006.257.11:08:00.27#ibcon#read 4, iclass 16, count 0 2006.257.11:08:00.27#ibcon#about to read 5, iclass 16, count 0 2006.257.11:08:00.27#ibcon#read 5, iclass 16, count 0 2006.257.11:08:00.27#ibcon#about to read 6, iclass 16, count 0 2006.257.11:08:00.27#ibcon#read 6, iclass 16, count 0 2006.257.11:08:00.27#ibcon#end of sib2, iclass 16, count 0 2006.257.11:08:00.27#ibcon#*after write, iclass 16, count 0 2006.257.11:08:00.27#ibcon#*before return 0, iclass 16, count 0 2006.257.11:08:00.27#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:08:00.27#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:08:00.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:08:00.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:08:00.27$vck44/vblo=8,744.99 2006.257.11:08:00.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.11:08:00.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.11:08:00.27#ibcon#ireg 17 cls_cnt 0 2006.257.11:08:00.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:08:00.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:08:00.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:08:00.27#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:08:00.27#ibcon#first serial, iclass 18, count 0 2006.257.11:08:00.27#ibcon#enter sib2, iclass 18, count 0 2006.257.11:08:00.27#ibcon#flushed, iclass 18, count 0 2006.257.11:08:00.27#ibcon#about to write, iclass 18, count 0 2006.257.11:08:00.27#ibcon#wrote, iclass 18, count 0 2006.257.11:08:00.27#ibcon#about to read 3, iclass 18, count 0 2006.257.11:08:00.29#ibcon#read 3, iclass 18, count 0 2006.257.11:08:00.29#ibcon#about to read 4, iclass 18, count 0 2006.257.11:08:00.29#ibcon#read 4, iclass 18, count 0 2006.257.11:08:00.29#ibcon#about to read 5, iclass 18, count 0 2006.257.11:08:00.29#ibcon#read 5, iclass 18, count 0 2006.257.11:08:00.29#ibcon#about to read 6, iclass 18, count 0 2006.257.11:08:00.29#ibcon#read 6, iclass 18, count 0 2006.257.11:08:00.29#ibcon#end of sib2, iclass 18, count 0 2006.257.11:08:00.29#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:08:00.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:08:00.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:08:00.29#ibcon#*before write, iclass 18, count 0 2006.257.11:08:00.29#ibcon#enter sib2, iclass 18, count 0 2006.257.11:08:00.29#ibcon#flushed, iclass 18, count 0 2006.257.11:08:00.29#ibcon#about to write, iclass 18, count 0 2006.257.11:08:00.29#ibcon#wrote, iclass 18, count 0 2006.257.11:08:00.29#ibcon#about to read 3, iclass 18, count 0 2006.257.11:08:00.33#ibcon#read 3, iclass 18, count 0 2006.257.11:08:00.33#ibcon#about to read 4, iclass 18, count 0 2006.257.11:08:00.33#ibcon#read 4, iclass 18, count 0 2006.257.11:08:00.33#ibcon#about to read 5, iclass 18, count 0 2006.257.11:08:00.33#ibcon#read 5, iclass 18, count 0 2006.257.11:08:00.33#ibcon#about to read 6, iclass 18, count 0 2006.257.11:08:00.33#ibcon#read 6, iclass 18, count 0 2006.257.11:08:00.33#ibcon#end of sib2, iclass 18, count 0 2006.257.11:08:00.33#ibcon#*after write, iclass 18, count 0 2006.257.11:08:00.33#ibcon#*before return 0, iclass 18, count 0 2006.257.11:08:00.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:08:00.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:08:00.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:08:00.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:08:00.33$vck44/vb=8,4 2006.257.11:08:00.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.11:08:00.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.11:08:00.33#ibcon#ireg 11 cls_cnt 2 2006.257.11:08:00.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:08:00.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:08:00.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:08:00.39#ibcon#enter wrdev, iclass 20, count 2 2006.257.11:08:00.39#ibcon#first serial, iclass 20, count 2 2006.257.11:08:00.39#ibcon#enter sib2, iclass 20, count 2 2006.257.11:08:00.39#ibcon#flushed, iclass 20, count 2 2006.257.11:08:00.39#ibcon#about to write, iclass 20, count 2 2006.257.11:08:00.39#ibcon#wrote, iclass 20, count 2 2006.257.11:08:00.39#ibcon#about to read 3, iclass 20, count 2 2006.257.11:08:00.41#ibcon#read 3, iclass 20, count 2 2006.257.11:08:00.41#ibcon#about to read 4, iclass 20, count 2 2006.257.11:08:00.41#ibcon#read 4, iclass 20, count 2 2006.257.11:08:00.41#ibcon#about to read 5, iclass 20, count 2 2006.257.11:08:00.41#ibcon#read 5, iclass 20, count 2 2006.257.11:08:00.41#ibcon#about to read 6, iclass 20, count 2 2006.257.11:08:00.41#ibcon#read 6, iclass 20, count 2 2006.257.11:08:00.41#ibcon#end of sib2, iclass 20, count 2 2006.257.11:08:00.41#ibcon#*mode == 0, iclass 20, count 2 2006.257.11:08:00.41#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.11:08:00.41#ibcon#[27=AT08-04\r\n] 2006.257.11:08:00.41#ibcon#*before write, iclass 20, count 2 2006.257.11:08:00.41#ibcon#enter sib2, iclass 20, count 2 2006.257.11:08:00.41#ibcon#flushed, iclass 20, count 2 2006.257.11:08:00.41#ibcon#about to write, iclass 20, count 2 2006.257.11:08:00.41#ibcon#wrote, iclass 20, count 2 2006.257.11:08:00.41#ibcon#about to read 3, iclass 20, count 2 2006.257.11:08:00.44#ibcon#read 3, iclass 20, count 2 2006.257.11:08:00.44#ibcon#about to read 4, iclass 20, count 2 2006.257.11:08:00.44#ibcon#read 4, iclass 20, count 2 2006.257.11:08:00.44#ibcon#about to read 5, iclass 20, count 2 2006.257.11:08:00.44#ibcon#read 5, iclass 20, count 2 2006.257.11:08:00.44#ibcon#about to read 6, iclass 20, count 2 2006.257.11:08:00.44#ibcon#read 6, iclass 20, count 2 2006.257.11:08:00.44#ibcon#end of sib2, iclass 20, count 2 2006.257.11:08:00.44#ibcon#*after write, iclass 20, count 2 2006.257.11:08:00.44#ibcon#*before return 0, iclass 20, count 2 2006.257.11:08:00.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:08:00.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:08:00.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.11:08:00.44#ibcon#ireg 7 cls_cnt 0 2006.257.11:08:00.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:08:00.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:08:00.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:08:00.56#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:08:00.56#ibcon#first serial, iclass 20, count 0 2006.257.11:08:00.56#ibcon#enter sib2, iclass 20, count 0 2006.257.11:08:00.56#ibcon#flushed, iclass 20, count 0 2006.257.11:08:00.56#ibcon#about to write, iclass 20, count 0 2006.257.11:08:00.56#ibcon#wrote, iclass 20, count 0 2006.257.11:08:00.56#ibcon#about to read 3, iclass 20, count 0 2006.257.11:08:00.58#ibcon#read 3, iclass 20, count 0 2006.257.11:08:00.58#ibcon#about to read 4, iclass 20, count 0 2006.257.11:08:00.58#ibcon#read 4, iclass 20, count 0 2006.257.11:08:00.58#ibcon#about to read 5, iclass 20, count 0 2006.257.11:08:00.58#ibcon#read 5, iclass 20, count 0 2006.257.11:08:00.58#ibcon#about to read 6, iclass 20, count 0 2006.257.11:08:00.58#ibcon#read 6, iclass 20, count 0 2006.257.11:08:00.58#ibcon#end of sib2, iclass 20, count 0 2006.257.11:08:00.58#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:08:00.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:08:00.58#ibcon#[27=USB\r\n] 2006.257.11:08:00.58#ibcon#*before write, iclass 20, count 0 2006.257.11:08:00.58#ibcon#enter sib2, iclass 20, count 0 2006.257.11:08:00.58#ibcon#flushed, iclass 20, count 0 2006.257.11:08:00.58#ibcon#about to write, iclass 20, count 0 2006.257.11:08:00.58#ibcon#wrote, iclass 20, count 0 2006.257.11:08:00.58#ibcon#about to read 3, iclass 20, count 0 2006.257.11:08:00.61#ibcon#read 3, iclass 20, count 0 2006.257.11:08:00.61#ibcon#about to read 4, iclass 20, count 0 2006.257.11:08:00.61#ibcon#read 4, iclass 20, count 0 2006.257.11:08:00.61#ibcon#about to read 5, iclass 20, count 0 2006.257.11:08:00.61#ibcon#read 5, iclass 20, count 0 2006.257.11:08:00.61#ibcon#about to read 6, iclass 20, count 0 2006.257.11:08:00.61#ibcon#read 6, iclass 20, count 0 2006.257.11:08:00.61#ibcon#end of sib2, iclass 20, count 0 2006.257.11:08:00.61#ibcon#*after write, iclass 20, count 0 2006.257.11:08:00.61#ibcon#*before return 0, iclass 20, count 0 2006.257.11:08:00.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:08:00.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:08:00.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:08:00.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:08:00.61$vck44/vabw=wide 2006.257.11:08:00.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.11:08:00.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.11:08:00.61#ibcon#ireg 8 cls_cnt 0 2006.257.11:08:00.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:08:00.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:08:00.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:08:00.61#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:08:00.61#ibcon#first serial, iclass 22, count 0 2006.257.11:08:00.61#ibcon#enter sib2, iclass 22, count 0 2006.257.11:08:00.61#ibcon#flushed, iclass 22, count 0 2006.257.11:08:00.61#ibcon#about to write, iclass 22, count 0 2006.257.11:08:00.61#ibcon#wrote, iclass 22, count 0 2006.257.11:08:00.61#ibcon#about to read 3, iclass 22, count 0 2006.257.11:08:00.63#ibcon#read 3, iclass 22, count 0 2006.257.11:08:00.63#ibcon#about to read 4, iclass 22, count 0 2006.257.11:08:00.63#ibcon#read 4, iclass 22, count 0 2006.257.11:08:00.63#ibcon#about to read 5, iclass 22, count 0 2006.257.11:08:00.63#ibcon#read 5, iclass 22, count 0 2006.257.11:08:00.63#ibcon#about to read 6, iclass 22, count 0 2006.257.11:08:00.63#ibcon#read 6, iclass 22, count 0 2006.257.11:08:00.63#ibcon#end of sib2, iclass 22, count 0 2006.257.11:08:00.63#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:08:00.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:08:00.63#ibcon#[25=BW32\r\n] 2006.257.11:08:00.63#ibcon#*before write, iclass 22, count 0 2006.257.11:08:00.63#ibcon#enter sib2, iclass 22, count 0 2006.257.11:08:00.63#ibcon#flushed, iclass 22, count 0 2006.257.11:08:00.63#ibcon#about to write, iclass 22, count 0 2006.257.11:08:00.63#ibcon#wrote, iclass 22, count 0 2006.257.11:08:00.63#ibcon#about to read 3, iclass 22, count 0 2006.257.11:08:00.66#ibcon#read 3, iclass 22, count 0 2006.257.11:08:00.66#ibcon#about to read 4, iclass 22, count 0 2006.257.11:08:00.66#ibcon#read 4, iclass 22, count 0 2006.257.11:08:00.66#ibcon#about to read 5, iclass 22, count 0 2006.257.11:08:00.66#ibcon#read 5, iclass 22, count 0 2006.257.11:08:00.66#ibcon#about to read 6, iclass 22, count 0 2006.257.11:08:00.66#ibcon#read 6, iclass 22, count 0 2006.257.11:08:00.66#ibcon#end of sib2, iclass 22, count 0 2006.257.11:08:00.66#ibcon#*after write, iclass 22, count 0 2006.257.11:08:00.66#ibcon#*before return 0, iclass 22, count 0 2006.257.11:08:00.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:08:00.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:08:00.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:08:00.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:08:00.66$vck44/vbbw=wide 2006.257.11:08:00.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.11:08:00.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.11:08:00.66#ibcon#ireg 8 cls_cnt 0 2006.257.11:08:00.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:08:00.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:08:00.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:08:00.73#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:08:00.73#ibcon#first serial, iclass 24, count 0 2006.257.11:08:00.73#ibcon#enter sib2, iclass 24, count 0 2006.257.11:08:00.73#ibcon#flushed, iclass 24, count 0 2006.257.11:08:00.73#ibcon#about to write, iclass 24, count 0 2006.257.11:08:00.73#ibcon#wrote, iclass 24, count 0 2006.257.11:08:00.73#ibcon#about to read 3, iclass 24, count 0 2006.257.11:08:00.75#ibcon#read 3, iclass 24, count 0 2006.257.11:08:00.75#ibcon#about to read 4, iclass 24, count 0 2006.257.11:08:00.75#ibcon#read 4, iclass 24, count 0 2006.257.11:08:00.75#ibcon#about to read 5, iclass 24, count 0 2006.257.11:08:00.75#ibcon#read 5, iclass 24, count 0 2006.257.11:08:00.75#ibcon#about to read 6, iclass 24, count 0 2006.257.11:08:00.75#ibcon#read 6, iclass 24, count 0 2006.257.11:08:00.75#ibcon#end of sib2, iclass 24, count 0 2006.257.11:08:00.75#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:08:00.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:08:00.75#ibcon#[27=BW32\r\n] 2006.257.11:08:00.75#ibcon#*before write, iclass 24, count 0 2006.257.11:08:00.75#ibcon#enter sib2, iclass 24, count 0 2006.257.11:08:00.75#ibcon#flushed, iclass 24, count 0 2006.257.11:08:00.75#ibcon#about to write, iclass 24, count 0 2006.257.11:08:00.75#ibcon#wrote, iclass 24, count 0 2006.257.11:08:00.75#ibcon#about to read 3, iclass 24, count 0 2006.257.11:08:00.78#ibcon#read 3, iclass 24, count 0 2006.257.11:08:00.78#ibcon#about to read 4, iclass 24, count 0 2006.257.11:08:00.78#ibcon#read 4, iclass 24, count 0 2006.257.11:08:00.78#ibcon#about to read 5, iclass 24, count 0 2006.257.11:08:00.78#ibcon#read 5, iclass 24, count 0 2006.257.11:08:00.78#ibcon#about to read 6, iclass 24, count 0 2006.257.11:08:00.78#ibcon#read 6, iclass 24, count 0 2006.257.11:08:00.78#ibcon#end of sib2, iclass 24, count 0 2006.257.11:08:00.78#ibcon#*after write, iclass 24, count 0 2006.257.11:08:00.78#ibcon#*before return 0, iclass 24, count 0 2006.257.11:08:00.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:08:00.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:08:00.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:08:00.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:08:00.78$setupk4/ifdk4 2006.257.11:08:00.78$ifdk4/lo= 2006.257.11:08:00.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:08:00.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:08:00.78$ifdk4/patch= 2006.257.11:08:00.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:08:00.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:08:00.78$setupk4/!*+20s 2006.257.11:08:07.93#abcon#<5=/14 1.6 4.1 18.53 961014.1\r\n> 2006.257.11:08:07.95#abcon#{5=INTERFACE CLEAR} 2006.257.11:08:08.01#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:08:15.29$setupk4/"tpicd 2006.257.11:08:15.29$setupk4/echo=off 2006.257.11:08:15.29$setupk4/xlog=off 2006.257.11:08:15.29:!2006.257.11:09:48 2006.257.11:08:31.14#trakl#Source acquired 2006.257.11:08:32.14#flagr#flagr/antenna,acquired 2006.257.11:09:48.00:preob 2006.257.11:09:48.14/onsource/TRACKING 2006.257.11:09:48.14:!2006.257.11:09:58 2006.257.11:09:58.00:"tape 2006.257.11:09:58.00:"st=record 2006.257.11:09:58.00:data_valid=on 2006.257.11:09:58.00:midob 2006.257.11:09:59.14/onsource/TRACKING 2006.257.11:09:59.14/wx/18.50,1014.0,96 2006.257.11:09:59.28/cable/+6.4782E-03 2006.257.11:10:00.37/va/01,08,usb,yes,30,33 2006.257.11:10:00.37/va/02,07,usb,yes,33,33 2006.257.11:10:00.37/va/03,08,usb,yes,30,31 2006.257.11:10:00.37/va/04,07,usb,yes,34,36 2006.257.11:10:00.37/va/05,04,usb,yes,30,31 2006.257.11:10:00.37/va/06,04,usb,yes,34,33 2006.257.11:10:00.37/va/07,04,usb,yes,35,35 2006.257.11:10:00.37/va/08,04,usb,yes,29,36 2006.257.11:10:00.60/valo/01,524.99,yes,locked 2006.257.11:10:00.60/valo/02,534.99,yes,locked 2006.257.11:10:00.60/valo/03,564.99,yes,locked 2006.257.11:10:00.60/valo/04,624.99,yes,locked 2006.257.11:10:00.60/valo/05,734.99,yes,locked 2006.257.11:10:00.60/valo/06,814.99,yes,locked 2006.257.11:10:00.60/valo/07,864.99,yes,locked 2006.257.11:10:00.60/valo/08,884.99,yes,locked 2006.257.11:10:01.69/vb/01,04,usb,yes,30,28 2006.257.11:10:01.69/vb/02,05,usb,yes,28,28 2006.257.11:10:01.69/vb/03,04,usb,yes,29,32 2006.257.11:10:01.69/vb/04,05,usb,yes,29,28 2006.257.11:10:01.69/vb/05,04,usb,yes,26,29 2006.257.11:10:01.69/vb/06,04,usb,yes,31,27 2006.257.11:10:01.69/vb/07,04,usb,yes,30,30 2006.257.11:10:01.69/vb/08,04,usb,yes,28,31 2006.257.11:10:01.92/vblo/01,629.99,yes,locked 2006.257.11:10:01.92/vblo/02,634.99,yes,locked 2006.257.11:10:01.92/vblo/03,649.99,yes,locked 2006.257.11:10:01.92/vblo/04,679.99,yes,locked 2006.257.11:10:01.92/vblo/05,709.99,yes,locked 2006.257.11:10:01.92/vblo/06,719.99,yes,locked 2006.257.11:10:01.92/vblo/07,734.99,yes,locked 2006.257.11:10:01.92/vblo/08,744.99,yes,locked 2006.257.11:10:02.07/vabw/8 2006.257.11:10:02.22/vbbw/8 2006.257.11:10:02.31/xfe/off,on,15.2 2006.257.11:10:02.68/ifatt/23,28,28,28 2006.257.11:10:03.07/fmout-gps/S +4.62E-07 2006.257.11:10:03.11:!2006.257.11:11:48 2006.257.11:11:48.01:data_valid=off 2006.257.11:11:48.01:"et 2006.257.11:11:48.02:!+3s 2006.257.11:11:51.03:"tape 2006.257.11:11:51.03:postob 2006.257.11:11:51.25/cable/+6.4781E-03 2006.257.11:11:51.25/wx/18.47,1013.9,96 2006.257.11:11:51.31/fmout-gps/S +4.61E-07 2006.257.11:11:51.31:scan_name=257-1115,jd0609,170 2006.257.11:11:51.32:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.11:11:52.14#flagr#flagr/antenna,new-source 2006.257.11:11:52.14:checkk5 2006.257.11:11:52.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:11:52.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:11:53.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:11:53.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:11:54.11/chk_obsdata//k5ts1/T2571109??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.11:11:54.51/chk_obsdata//k5ts2/T2571109??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.11:11:54.91/chk_obsdata//k5ts3/T2571109??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.11:11:55.33/chk_obsdata//k5ts4/T2571109??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.11:11:56.05/k5log//k5ts1_log_newline 2006.257.11:11:56.76/k5log//k5ts2_log_newline 2006.257.11:11:57.49/k5log//k5ts3_log_newline 2006.257.11:11:58.20/k5log//k5ts4_log_newline 2006.257.11:11:58.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:11:58.23:setupk4=1 2006.257.11:11:58.23$setupk4/echo=on 2006.257.11:11:58.23$setupk4/pcalon 2006.257.11:11:58.23$pcalon/"no phase cal control is implemented here 2006.257.11:11:58.23$setupk4/"tpicd=stop 2006.257.11:11:58.23$setupk4/"rec=synch_on 2006.257.11:11:58.23$setupk4/"rec_mode=128 2006.257.11:11:58.23$setupk4/!* 2006.257.11:11:58.23$setupk4/recpk4 2006.257.11:11:58.23$recpk4/recpatch= 2006.257.11:11:58.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:11:58.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:11:58.24$setupk4/vck44 2006.257.11:11:58.24$vck44/valo=1,524.99 2006.257.11:11:58.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.11:11:58.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.11:11:58.24#ibcon#ireg 17 cls_cnt 0 2006.257.11:11:58.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:11:58.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:11:58.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:11:58.24#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:11:58.24#ibcon#first serial, iclass 13, count 0 2006.257.11:11:58.24#ibcon#enter sib2, iclass 13, count 0 2006.257.11:11:58.24#ibcon#flushed, iclass 13, count 0 2006.257.11:11:58.24#ibcon#about to write, iclass 13, count 0 2006.257.11:11:58.24#ibcon#wrote, iclass 13, count 0 2006.257.11:11:58.24#ibcon#about to read 3, iclass 13, count 0 2006.257.11:11:58.25#ibcon#read 3, iclass 13, count 0 2006.257.11:11:58.25#ibcon#about to read 4, iclass 13, count 0 2006.257.11:11:58.25#ibcon#read 4, iclass 13, count 0 2006.257.11:11:58.25#ibcon#about to read 5, iclass 13, count 0 2006.257.11:11:58.25#ibcon#read 5, iclass 13, count 0 2006.257.11:11:58.25#ibcon#about to read 6, iclass 13, count 0 2006.257.11:11:58.25#ibcon#read 6, iclass 13, count 0 2006.257.11:11:58.25#ibcon#end of sib2, iclass 13, count 0 2006.257.11:11:58.25#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:11:58.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:11:58.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:11:58.25#ibcon#*before write, iclass 13, count 0 2006.257.11:11:58.25#ibcon#enter sib2, iclass 13, count 0 2006.257.11:11:58.25#ibcon#flushed, iclass 13, count 0 2006.257.11:11:58.25#ibcon#about to write, iclass 13, count 0 2006.257.11:11:58.25#ibcon#wrote, iclass 13, count 0 2006.257.11:11:58.25#ibcon#about to read 3, iclass 13, count 0 2006.257.11:11:58.30#ibcon#read 3, iclass 13, count 0 2006.257.11:11:58.30#ibcon#about to read 4, iclass 13, count 0 2006.257.11:11:58.30#ibcon#read 4, iclass 13, count 0 2006.257.11:11:58.30#ibcon#about to read 5, iclass 13, count 0 2006.257.11:11:58.30#ibcon#read 5, iclass 13, count 0 2006.257.11:11:58.30#ibcon#about to read 6, iclass 13, count 0 2006.257.11:11:58.30#ibcon#read 6, iclass 13, count 0 2006.257.11:11:58.30#ibcon#end of sib2, iclass 13, count 0 2006.257.11:11:58.30#ibcon#*after write, iclass 13, count 0 2006.257.11:11:58.30#ibcon#*before return 0, iclass 13, count 0 2006.257.11:11:58.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:11:58.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:11:58.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:11:58.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:11:58.30$vck44/va=1,8 2006.257.11:11:58.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.11:11:58.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.11:11:58.30#ibcon#ireg 11 cls_cnt 2 2006.257.11:11:58.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:11:58.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:11:58.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:11:58.30#ibcon#enter wrdev, iclass 15, count 2 2006.257.11:11:58.30#ibcon#first serial, iclass 15, count 2 2006.257.11:11:58.30#ibcon#enter sib2, iclass 15, count 2 2006.257.11:11:58.30#ibcon#flushed, iclass 15, count 2 2006.257.11:11:58.30#ibcon#about to write, iclass 15, count 2 2006.257.11:11:58.30#ibcon#wrote, iclass 15, count 2 2006.257.11:11:58.30#ibcon#about to read 3, iclass 15, count 2 2006.257.11:11:58.32#ibcon#read 3, iclass 15, count 2 2006.257.11:11:58.32#ibcon#about to read 4, iclass 15, count 2 2006.257.11:11:58.32#ibcon#read 4, iclass 15, count 2 2006.257.11:11:58.32#ibcon#about to read 5, iclass 15, count 2 2006.257.11:11:58.32#ibcon#read 5, iclass 15, count 2 2006.257.11:11:58.32#ibcon#about to read 6, iclass 15, count 2 2006.257.11:11:58.32#ibcon#read 6, iclass 15, count 2 2006.257.11:11:58.32#ibcon#end of sib2, iclass 15, count 2 2006.257.11:11:58.32#ibcon#*mode == 0, iclass 15, count 2 2006.257.11:11:58.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.11:11:58.32#ibcon#[25=AT01-08\r\n] 2006.257.11:11:58.32#ibcon#*before write, iclass 15, count 2 2006.257.11:11:58.32#ibcon#enter sib2, iclass 15, count 2 2006.257.11:11:58.32#ibcon#flushed, iclass 15, count 2 2006.257.11:11:58.32#ibcon#about to write, iclass 15, count 2 2006.257.11:11:58.32#ibcon#wrote, iclass 15, count 2 2006.257.11:11:58.32#ibcon#about to read 3, iclass 15, count 2 2006.257.11:11:58.35#ibcon#read 3, iclass 15, count 2 2006.257.11:11:58.35#ibcon#about to read 4, iclass 15, count 2 2006.257.11:11:58.35#ibcon#read 4, iclass 15, count 2 2006.257.11:11:58.35#ibcon#about to read 5, iclass 15, count 2 2006.257.11:11:58.35#ibcon#read 5, iclass 15, count 2 2006.257.11:11:58.35#ibcon#about to read 6, iclass 15, count 2 2006.257.11:11:58.35#ibcon#read 6, iclass 15, count 2 2006.257.11:11:58.35#ibcon#end of sib2, iclass 15, count 2 2006.257.11:11:58.35#ibcon#*after write, iclass 15, count 2 2006.257.11:11:58.35#ibcon#*before return 0, iclass 15, count 2 2006.257.11:11:58.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:11:58.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:11:58.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.11:11:58.35#ibcon#ireg 7 cls_cnt 0 2006.257.11:11:58.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:11:58.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:11:58.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:11:58.47#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:11:58.47#ibcon#first serial, iclass 15, count 0 2006.257.11:11:58.47#ibcon#enter sib2, iclass 15, count 0 2006.257.11:11:58.47#ibcon#flushed, iclass 15, count 0 2006.257.11:11:58.47#ibcon#about to write, iclass 15, count 0 2006.257.11:11:58.47#ibcon#wrote, iclass 15, count 0 2006.257.11:11:58.47#ibcon#about to read 3, iclass 15, count 0 2006.257.11:11:58.49#ibcon#read 3, iclass 15, count 0 2006.257.11:11:58.49#ibcon#about to read 4, iclass 15, count 0 2006.257.11:11:58.49#ibcon#read 4, iclass 15, count 0 2006.257.11:11:58.49#ibcon#about to read 5, iclass 15, count 0 2006.257.11:11:58.49#ibcon#read 5, iclass 15, count 0 2006.257.11:11:58.49#ibcon#about to read 6, iclass 15, count 0 2006.257.11:11:58.49#ibcon#read 6, iclass 15, count 0 2006.257.11:11:58.49#ibcon#end of sib2, iclass 15, count 0 2006.257.11:11:58.49#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:11:58.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:11:58.49#ibcon#[25=USB\r\n] 2006.257.11:11:58.49#ibcon#*before write, iclass 15, count 0 2006.257.11:11:58.49#ibcon#enter sib2, iclass 15, count 0 2006.257.11:11:58.49#ibcon#flushed, iclass 15, count 0 2006.257.11:11:58.49#ibcon#about to write, iclass 15, count 0 2006.257.11:11:58.49#ibcon#wrote, iclass 15, count 0 2006.257.11:11:58.49#ibcon#about to read 3, iclass 15, count 0 2006.257.11:11:58.52#ibcon#read 3, iclass 15, count 0 2006.257.11:11:58.52#ibcon#about to read 4, iclass 15, count 0 2006.257.11:11:58.52#ibcon#read 4, iclass 15, count 0 2006.257.11:11:58.52#ibcon#about to read 5, iclass 15, count 0 2006.257.11:11:58.52#ibcon#read 5, iclass 15, count 0 2006.257.11:11:58.52#ibcon#about to read 6, iclass 15, count 0 2006.257.11:11:58.52#ibcon#read 6, iclass 15, count 0 2006.257.11:11:58.52#ibcon#end of sib2, iclass 15, count 0 2006.257.11:11:58.52#ibcon#*after write, iclass 15, count 0 2006.257.11:11:58.52#ibcon#*before return 0, iclass 15, count 0 2006.257.11:11:58.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:11:58.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:11:58.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:11:58.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:11:58.52$vck44/valo=2,534.99 2006.257.11:11:58.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.11:11:58.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.11:11:58.52#ibcon#ireg 17 cls_cnt 0 2006.257.11:11:58.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:11:58.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:11:58.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:11:58.52#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:11:58.52#ibcon#first serial, iclass 17, count 0 2006.257.11:11:58.52#ibcon#enter sib2, iclass 17, count 0 2006.257.11:11:58.52#ibcon#flushed, iclass 17, count 0 2006.257.11:11:58.52#ibcon#about to write, iclass 17, count 0 2006.257.11:11:58.52#ibcon#wrote, iclass 17, count 0 2006.257.11:11:58.52#ibcon#about to read 3, iclass 17, count 0 2006.257.11:11:58.54#ibcon#read 3, iclass 17, count 0 2006.257.11:11:58.54#ibcon#about to read 4, iclass 17, count 0 2006.257.11:11:58.54#ibcon#read 4, iclass 17, count 0 2006.257.11:11:58.54#ibcon#about to read 5, iclass 17, count 0 2006.257.11:11:58.54#ibcon#read 5, iclass 17, count 0 2006.257.11:11:58.54#ibcon#about to read 6, iclass 17, count 0 2006.257.11:11:58.54#ibcon#read 6, iclass 17, count 0 2006.257.11:11:58.54#ibcon#end of sib2, iclass 17, count 0 2006.257.11:11:58.54#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:11:58.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:11:58.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:11:58.54#ibcon#*before write, iclass 17, count 0 2006.257.11:11:58.54#ibcon#enter sib2, iclass 17, count 0 2006.257.11:11:58.54#ibcon#flushed, iclass 17, count 0 2006.257.11:11:58.54#ibcon#about to write, iclass 17, count 0 2006.257.11:11:58.54#ibcon#wrote, iclass 17, count 0 2006.257.11:11:58.54#ibcon#about to read 3, iclass 17, count 0 2006.257.11:11:58.58#ibcon#read 3, iclass 17, count 0 2006.257.11:11:58.58#ibcon#about to read 4, iclass 17, count 0 2006.257.11:11:58.58#ibcon#read 4, iclass 17, count 0 2006.257.11:11:58.58#ibcon#about to read 5, iclass 17, count 0 2006.257.11:11:58.58#ibcon#read 5, iclass 17, count 0 2006.257.11:11:58.58#ibcon#about to read 6, iclass 17, count 0 2006.257.11:11:58.58#ibcon#read 6, iclass 17, count 0 2006.257.11:11:58.58#ibcon#end of sib2, iclass 17, count 0 2006.257.11:11:58.58#ibcon#*after write, iclass 17, count 0 2006.257.11:11:58.58#ibcon#*before return 0, iclass 17, count 0 2006.257.11:11:58.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:11:58.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:11:58.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:11:58.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:11:58.58$vck44/va=2,7 2006.257.11:11:58.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.11:11:58.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.11:11:58.58#ibcon#ireg 11 cls_cnt 2 2006.257.11:11:58.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:11:58.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:11:58.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:11:58.64#ibcon#enter wrdev, iclass 19, count 2 2006.257.11:11:58.64#ibcon#first serial, iclass 19, count 2 2006.257.11:11:58.64#ibcon#enter sib2, iclass 19, count 2 2006.257.11:11:58.64#ibcon#flushed, iclass 19, count 2 2006.257.11:11:58.64#ibcon#about to write, iclass 19, count 2 2006.257.11:11:58.64#ibcon#wrote, iclass 19, count 2 2006.257.11:11:58.64#ibcon#about to read 3, iclass 19, count 2 2006.257.11:11:58.66#ibcon#read 3, iclass 19, count 2 2006.257.11:11:58.66#ibcon#about to read 4, iclass 19, count 2 2006.257.11:11:58.66#ibcon#read 4, iclass 19, count 2 2006.257.11:11:58.66#ibcon#about to read 5, iclass 19, count 2 2006.257.11:11:58.66#ibcon#read 5, iclass 19, count 2 2006.257.11:11:58.66#ibcon#about to read 6, iclass 19, count 2 2006.257.11:11:58.66#ibcon#read 6, iclass 19, count 2 2006.257.11:11:58.66#ibcon#end of sib2, iclass 19, count 2 2006.257.11:11:58.66#ibcon#*mode == 0, iclass 19, count 2 2006.257.11:11:58.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.11:11:58.66#ibcon#[25=AT02-07\r\n] 2006.257.11:11:58.66#ibcon#*before write, iclass 19, count 2 2006.257.11:11:58.66#ibcon#enter sib2, iclass 19, count 2 2006.257.11:11:58.66#ibcon#flushed, iclass 19, count 2 2006.257.11:11:58.66#ibcon#about to write, iclass 19, count 2 2006.257.11:11:58.66#ibcon#wrote, iclass 19, count 2 2006.257.11:11:58.66#ibcon#about to read 3, iclass 19, count 2 2006.257.11:11:58.69#ibcon#read 3, iclass 19, count 2 2006.257.11:11:58.69#ibcon#about to read 4, iclass 19, count 2 2006.257.11:11:58.69#ibcon#read 4, iclass 19, count 2 2006.257.11:11:58.69#ibcon#about to read 5, iclass 19, count 2 2006.257.11:11:58.69#ibcon#read 5, iclass 19, count 2 2006.257.11:11:58.69#ibcon#about to read 6, iclass 19, count 2 2006.257.11:11:58.69#ibcon#read 6, iclass 19, count 2 2006.257.11:11:58.69#ibcon#end of sib2, iclass 19, count 2 2006.257.11:11:58.69#ibcon#*after write, iclass 19, count 2 2006.257.11:11:58.69#ibcon#*before return 0, iclass 19, count 2 2006.257.11:11:58.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:11:58.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:11:58.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.11:11:58.69#ibcon#ireg 7 cls_cnt 0 2006.257.11:11:58.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:11:58.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:11:58.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:11:58.81#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:11:58.81#ibcon#first serial, iclass 19, count 0 2006.257.11:11:58.81#ibcon#enter sib2, iclass 19, count 0 2006.257.11:11:58.81#ibcon#flushed, iclass 19, count 0 2006.257.11:11:58.81#ibcon#about to write, iclass 19, count 0 2006.257.11:11:58.81#ibcon#wrote, iclass 19, count 0 2006.257.11:11:58.81#ibcon#about to read 3, iclass 19, count 0 2006.257.11:11:58.83#ibcon#read 3, iclass 19, count 0 2006.257.11:11:58.83#ibcon#about to read 4, iclass 19, count 0 2006.257.11:11:58.83#ibcon#read 4, iclass 19, count 0 2006.257.11:11:58.83#ibcon#about to read 5, iclass 19, count 0 2006.257.11:11:58.83#ibcon#read 5, iclass 19, count 0 2006.257.11:11:58.83#ibcon#about to read 6, iclass 19, count 0 2006.257.11:11:58.83#ibcon#read 6, iclass 19, count 0 2006.257.11:11:58.83#ibcon#end of sib2, iclass 19, count 0 2006.257.11:11:58.83#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:11:58.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:11:58.83#ibcon#[25=USB\r\n] 2006.257.11:11:58.83#ibcon#*before write, iclass 19, count 0 2006.257.11:11:58.83#ibcon#enter sib2, iclass 19, count 0 2006.257.11:11:58.83#ibcon#flushed, iclass 19, count 0 2006.257.11:11:58.83#ibcon#about to write, iclass 19, count 0 2006.257.11:11:58.83#ibcon#wrote, iclass 19, count 0 2006.257.11:11:58.83#ibcon#about to read 3, iclass 19, count 0 2006.257.11:11:58.86#ibcon#read 3, iclass 19, count 0 2006.257.11:11:58.86#ibcon#about to read 4, iclass 19, count 0 2006.257.11:11:58.86#ibcon#read 4, iclass 19, count 0 2006.257.11:11:58.86#ibcon#about to read 5, iclass 19, count 0 2006.257.11:11:58.86#ibcon#read 5, iclass 19, count 0 2006.257.11:11:58.86#ibcon#about to read 6, iclass 19, count 0 2006.257.11:11:58.86#ibcon#read 6, iclass 19, count 0 2006.257.11:11:58.86#ibcon#end of sib2, iclass 19, count 0 2006.257.11:11:58.86#ibcon#*after write, iclass 19, count 0 2006.257.11:11:58.86#ibcon#*before return 0, iclass 19, count 0 2006.257.11:11:58.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:11:58.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:11:58.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:11:58.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:11:58.86$vck44/valo=3,564.99 2006.257.11:11:58.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.11:11:58.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.11:11:58.86#ibcon#ireg 17 cls_cnt 0 2006.257.11:11:58.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:11:58.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:11:58.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:11:58.86#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:11:58.86#ibcon#first serial, iclass 21, count 0 2006.257.11:11:58.86#ibcon#enter sib2, iclass 21, count 0 2006.257.11:11:58.86#ibcon#flushed, iclass 21, count 0 2006.257.11:11:58.86#ibcon#about to write, iclass 21, count 0 2006.257.11:11:58.86#ibcon#wrote, iclass 21, count 0 2006.257.11:11:58.86#ibcon#about to read 3, iclass 21, count 0 2006.257.11:11:58.88#ibcon#read 3, iclass 21, count 0 2006.257.11:11:58.88#ibcon#about to read 4, iclass 21, count 0 2006.257.11:11:58.88#ibcon#read 4, iclass 21, count 0 2006.257.11:11:58.88#ibcon#about to read 5, iclass 21, count 0 2006.257.11:11:58.88#ibcon#read 5, iclass 21, count 0 2006.257.11:11:58.88#ibcon#about to read 6, iclass 21, count 0 2006.257.11:11:58.88#ibcon#read 6, iclass 21, count 0 2006.257.11:11:58.88#ibcon#end of sib2, iclass 21, count 0 2006.257.11:11:58.88#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:11:58.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:11:58.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:11:58.88#ibcon#*before write, iclass 21, count 0 2006.257.11:11:58.88#ibcon#enter sib2, iclass 21, count 0 2006.257.11:11:58.88#ibcon#flushed, iclass 21, count 0 2006.257.11:11:58.88#ibcon#about to write, iclass 21, count 0 2006.257.11:11:58.88#ibcon#wrote, iclass 21, count 0 2006.257.11:11:58.88#ibcon#about to read 3, iclass 21, count 0 2006.257.11:11:58.92#ibcon#read 3, iclass 21, count 0 2006.257.11:11:58.92#ibcon#about to read 4, iclass 21, count 0 2006.257.11:11:58.92#ibcon#read 4, iclass 21, count 0 2006.257.11:11:58.92#ibcon#about to read 5, iclass 21, count 0 2006.257.11:11:58.92#ibcon#read 5, iclass 21, count 0 2006.257.11:11:58.92#ibcon#about to read 6, iclass 21, count 0 2006.257.11:11:58.92#ibcon#read 6, iclass 21, count 0 2006.257.11:11:58.92#ibcon#end of sib2, iclass 21, count 0 2006.257.11:11:58.92#ibcon#*after write, iclass 21, count 0 2006.257.11:11:58.92#ibcon#*before return 0, iclass 21, count 0 2006.257.11:11:58.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:11:58.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:11:58.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:11:58.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:11:58.92$vck44/va=3,8 2006.257.11:11:58.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.11:11:58.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.11:11:58.92#ibcon#ireg 11 cls_cnt 2 2006.257.11:11:58.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:11:58.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:11:58.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:11:58.98#ibcon#enter wrdev, iclass 23, count 2 2006.257.11:11:58.98#ibcon#first serial, iclass 23, count 2 2006.257.11:11:58.98#ibcon#enter sib2, iclass 23, count 2 2006.257.11:11:58.98#ibcon#flushed, iclass 23, count 2 2006.257.11:11:58.98#ibcon#about to write, iclass 23, count 2 2006.257.11:11:58.98#ibcon#wrote, iclass 23, count 2 2006.257.11:11:58.98#ibcon#about to read 3, iclass 23, count 2 2006.257.11:11:59.00#ibcon#read 3, iclass 23, count 2 2006.257.11:11:59.00#ibcon#about to read 4, iclass 23, count 2 2006.257.11:11:59.00#ibcon#read 4, iclass 23, count 2 2006.257.11:11:59.00#ibcon#about to read 5, iclass 23, count 2 2006.257.11:11:59.00#ibcon#read 5, iclass 23, count 2 2006.257.11:11:59.00#ibcon#about to read 6, iclass 23, count 2 2006.257.11:11:59.00#ibcon#read 6, iclass 23, count 2 2006.257.11:11:59.00#ibcon#end of sib2, iclass 23, count 2 2006.257.11:11:59.00#ibcon#*mode == 0, iclass 23, count 2 2006.257.11:11:59.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.11:11:59.00#ibcon#[25=AT03-08\r\n] 2006.257.11:11:59.00#ibcon#*before write, iclass 23, count 2 2006.257.11:11:59.00#ibcon#enter sib2, iclass 23, count 2 2006.257.11:11:59.00#ibcon#flushed, iclass 23, count 2 2006.257.11:11:59.00#ibcon#about to write, iclass 23, count 2 2006.257.11:11:59.00#ibcon#wrote, iclass 23, count 2 2006.257.11:11:59.00#ibcon#about to read 3, iclass 23, count 2 2006.257.11:11:59.03#ibcon#read 3, iclass 23, count 2 2006.257.11:11:59.03#ibcon#about to read 4, iclass 23, count 2 2006.257.11:11:59.03#ibcon#read 4, iclass 23, count 2 2006.257.11:11:59.03#ibcon#about to read 5, iclass 23, count 2 2006.257.11:11:59.03#ibcon#read 5, iclass 23, count 2 2006.257.11:11:59.03#ibcon#about to read 6, iclass 23, count 2 2006.257.11:11:59.03#ibcon#read 6, iclass 23, count 2 2006.257.11:11:59.03#ibcon#end of sib2, iclass 23, count 2 2006.257.11:11:59.03#ibcon#*after write, iclass 23, count 2 2006.257.11:11:59.03#ibcon#*before return 0, iclass 23, count 2 2006.257.11:11:59.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:11:59.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:11:59.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.11:11:59.03#ibcon#ireg 7 cls_cnt 0 2006.257.11:11:59.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:11:59.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:11:59.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:11:59.15#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:11:59.15#ibcon#first serial, iclass 23, count 0 2006.257.11:11:59.15#ibcon#enter sib2, iclass 23, count 0 2006.257.11:11:59.15#ibcon#flushed, iclass 23, count 0 2006.257.11:11:59.15#ibcon#about to write, iclass 23, count 0 2006.257.11:11:59.15#ibcon#wrote, iclass 23, count 0 2006.257.11:11:59.15#ibcon#about to read 3, iclass 23, count 0 2006.257.11:11:59.17#ibcon#read 3, iclass 23, count 0 2006.257.11:11:59.17#ibcon#about to read 4, iclass 23, count 0 2006.257.11:11:59.17#ibcon#read 4, iclass 23, count 0 2006.257.11:11:59.17#ibcon#about to read 5, iclass 23, count 0 2006.257.11:11:59.17#ibcon#read 5, iclass 23, count 0 2006.257.11:11:59.17#ibcon#about to read 6, iclass 23, count 0 2006.257.11:11:59.17#ibcon#read 6, iclass 23, count 0 2006.257.11:11:59.17#ibcon#end of sib2, iclass 23, count 0 2006.257.11:11:59.17#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:11:59.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:11:59.17#ibcon#[25=USB\r\n] 2006.257.11:11:59.17#ibcon#*before write, iclass 23, count 0 2006.257.11:11:59.17#ibcon#enter sib2, iclass 23, count 0 2006.257.11:11:59.17#ibcon#flushed, iclass 23, count 0 2006.257.11:11:59.17#ibcon#about to write, iclass 23, count 0 2006.257.11:11:59.17#ibcon#wrote, iclass 23, count 0 2006.257.11:11:59.17#ibcon#about to read 3, iclass 23, count 0 2006.257.11:11:59.20#ibcon#read 3, iclass 23, count 0 2006.257.11:11:59.20#ibcon#about to read 4, iclass 23, count 0 2006.257.11:11:59.20#ibcon#read 4, iclass 23, count 0 2006.257.11:11:59.20#ibcon#about to read 5, iclass 23, count 0 2006.257.11:11:59.20#ibcon#read 5, iclass 23, count 0 2006.257.11:11:59.20#ibcon#about to read 6, iclass 23, count 0 2006.257.11:11:59.20#ibcon#read 6, iclass 23, count 0 2006.257.11:11:59.20#ibcon#end of sib2, iclass 23, count 0 2006.257.11:11:59.20#ibcon#*after write, iclass 23, count 0 2006.257.11:11:59.20#ibcon#*before return 0, iclass 23, count 0 2006.257.11:11:59.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:11:59.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:11:59.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:11:59.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:11:59.20$vck44/valo=4,624.99 2006.257.11:11:59.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.11:11:59.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.11:11:59.20#ibcon#ireg 17 cls_cnt 0 2006.257.11:11:59.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:11:59.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:11:59.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:11:59.20#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:11:59.20#ibcon#first serial, iclass 25, count 0 2006.257.11:11:59.20#ibcon#enter sib2, iclass 25, count 0 2006.257.11:11:59.20#ibcon#flushed, iclass 25, count 0 2006.257.11:11:59.20#ibcon#about to write, iclass 25, count 0 2006.257.11:11:59.20#ibcon#wrote, iclass 25, count 0 2006.257.11:11:59.20#ibcon#about to read 3, iclass 25, count 0 2006.257.11:11:59.22#ibcon#read 3, iclass 25, count 0 2006.257.11:11:59.22#ibcon#about to read 4, iclass 25, count 0 2006.257.11:11:59.22#ibcon#read 4, iclass 25, count 0 2006.257.11:11:59.22#ibcon#about to read 5, iclass 25, count 0 2006.257.11:11:59.22#ibcon#read 5, iclass 25, count 0 2006.257.11:11:59.22#ibcon#about to read 6, iclass 25, count 0 2006.257.11:11:59.22#ibcon#read 6, iclass 25, count 0 2006.257.11:11:59.22#ibcon#end of sib2, iclass 25, count 0 2006.257.11:11:59.22#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:11:59.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:11:59.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:11:59.22#ibcon#*before write, iclass 25, count 0 2006.257.11:11:59.22#ibcon#enter sib2, iclass 25, count 0 2006.257.11:11:59.22#ibcon#flushed, iclass 25, count 0 2006.257.11:11:59.22#ibcon#about to write, iclass 25, count 0 2006.257.11:11:59.22#ibcon#wrote, iclass 25, count 0 2006.257.11:11:59.22#ibcon#about to read 3, iclass 25, count 0 2006.257.11:11:59.26#ibcon#read 3, iclass 25, count 0 2006.257.11:11:59.26#ibcon#about to read 4, iclass 25, count 0 2006.257.11:11:59.26#ibcon#read 4, iclass 25, count 0 2006.257.11:11:59.26#ibcon#about to read 5, iclass 25, count 0 2006.257.11:11:59.26#ibcon#read 5, iclass 25, count 0 2006.257.11:11:59.26#ibcon#about to read 6, iclass 25, count 0 2006.257.11:11:59.26#ibcon#read 6, iclass 25, count 0 2006.257.11:11:59.26#ibcon#end of sib2, iclass 25, count 0 2006.257.11:11:59.26#ibcon#*after write, iclass 25, count 0 2006.257.11:11:59.26#ibcon#*before return 0, iclass 25, count 0 2006.257.11:11:59.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:11:59.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:11:59.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:11:59.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:11:59.26$vck44/va=4,7 2006.257.11:11:59.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.11:11:59.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.11:11:59.26#ibcon#ireg 11 cls_cnt 2 2006.257.11:11:59.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:11:59.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:11:59.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:11:59.32#ibcon#enter wrdev, iclass 27, count 2 2006.257.11:11:59.32#ibcon#first serial, iclass 27, count 2 2006.257.11:11:59.32#ibcon#enter sib2, iclass 27, count 2 2006.257.11:11:59.32#ibcon#flushed, iclass 27, count 2 2006.257.11:11:59.32#ibcon#about to write, iclass 27, count 2 2006.257.11:11:59.32#ibcon#wrote, iclass 27, count 2 2006.257.11:11:59.32#ibcon#about to read 3, iclass 27, count 2 2006.257.11:11:59.34#ibcon#read 3, iclass 27, count 2 2006.257.11:11:59.34#ibcon#about to read 4, iclass 27, count 2 2006.257.11:11:59.34#ibcon#read 4, iclass 27, count 2 2006.257.11:11:59.34#ibcon#about to read 5, iclass 27, count 2 2006.257.11:11:59.34#ibcon#read 5, iclass 27, count 2 2006.257.11:11:59.34#ibcon#about to read 6, iclass 27, count 2 2006.257.11:11:59.34#ibcon#read 6, iclass 27, count 2 2006.257.11:11:59.34#ibcon#end of sib2, iclass 27, count 2 2006.257.11:11:59.34#ibcon#*mode == 0, iclass 27, count 2 2006.257.11:11:59.34#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.11:11:59.34#ibcon#[25=AT04-07\r\n] 2006.257.11:11:59.34#ibcon#*before write, iclass 27, count 2 2006.257.11:11:59.34#ibcon#enter sib2, iclass 27, count 2 2006.257.11:11:59.34#ibcon#flushed, iclass 27, count 2 2006.257.11:11:59.34#ibcon#about to write, iclass 27, count 2 2006.257.11:11:59.34#ibcon#wrote, iclass 27, count 2 2006.257.11:11:59.34#ibcon#about to read 3, iclass 27, count 2 2006.257.11:11:59.37#ibcon#read 3, iclass 27, count 2 2006.257.11:11:59.37#ibcon#about to read 4, iclass 27, count 2 2006.257.11:11:59.37#ibcon#read 4, iclass 27, count 2 2006.257.11:11:59.37#ibcon#about to read 5, iclass 27, count 2 2006.257.11:11:59.37#ibcon#read 5, iclass 27, count 2 2006.257.11:11:59.37#ibcon#about to read 6, iclass 27, count 2 2006.257.11:11:59.37#ibcon#read 6, iclass 27, count 2 2006.257.11:11:59.37#ibcon#end of sib2, iclass 27, count 2 2006.257.11:11:59.37#ibcon#*after write, iclass 27, count 2 2006.257.11:11:59.37#ibcon#*before return 0, iclass 27, count 2 2006.257.11:11:59.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:11:59.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:11:59.37#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.11:11:59.37#ibcon#ireg 7 cls_cnt 0 2006.257.11:11:59.37#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:11:59.49#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:11:59.49#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:11:59.49#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:11:59.49#ibcon#first serial, iclass 27, count 0 2006.257.11:11:59.49#ibcon#enter sib2, iclass 27, count 0 2006.257.11:11:59.49#ibcon#flushed, iclass 27, count 0 2006.257.11:11:59.49#ibcon#about to write, iclass 27, count 0 2006.257.11:11:59.49#ibcon#wrote, iclass 27, count 0 2006.257.11:11:59.49#ibcon#about to read 3, iclass 27, count 0 2006.257.11:11:59.51#ibcon#read 3, iclass 27, count 0 2006.257.11:11:59.51#ibcon#about to read 4, iclass 27, count 0 2006.257.11:11:59.51#ibcon#read 4, iclass 27, count 0 2006.257.11:11:59.51#ibcon#about to read 5, iclass 27, count 0 2006.257.11:11:59.51#ibcon#read 5, iclass 27, count 0 2006.257.11:11:59.51#ibcon#about to read 6, iclass 27, count 0 2006.257.11:11:59.51#ibcon#read 6, iclass 27, count 0 2006.257.11:11:59.51#ibcon#end of sib2, iclass 27, count 0 2006.257.11:11:59.51#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:11:59.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:11:59.51#ibcon#[25=USB\r\n] 2006.257.11:11:59.51#ibcon#*before write, iclass 27, count 0 2006.257.11:11:59.51#ibcon#enter sib2, iclass 27, count 0 2006.257.11:11:59.51#ibcon#flushed, iclass 27, count 0 2006.257.11:11:59.51#ibcon#about to write, iclass 27, count 0 2006.257.11:11:59.51#ibcon#wrote, iclass 27, count 0 2006.257.11:11:59.51#ibcon#about to read 3, iclass 27, count 0 2006.257.11:11:59.54#ibcon#read 3, iclass 27, count 0 2006.257.11:11:59.54#ibcon#about to read 4, iclass 27, count 0 2006.257.11:11:59.54#ibcon#read 4, iclass 27, count 0 2006.257.11:11:59.54#ibcon#about to read 5, iclass 27, count 0 2006.257.11:11:59.54#ibcon#read 5, iclass 27, count 0 2006.257.11:11:59.54#ibcon#about to read 6, iclass 27, count 0 2006.257.11:11:59.54#ibcon#read 6, iclass 27, count 0 2006.257.11:11:59.54#ibcon#end of sib2, iclass 27, count 0 2006.257.11:11:59.54#ibcon#*after write, iclass 27, count 0 2006.257.11:11:59.54#ibcon#*before return 0, iclass 27, count 0 2006.257.11:11:59.54#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:11:59.54#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:11:59.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:11:59.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:11:59.54$vck44/valo=5,734.99 2006.257.11:11:59.54#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.11:11:59.54#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.11:11:59.54#ibcon#ireg 17 cls_cnt 0 2006.257.11:11:59.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:11:59.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:11:59.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:11:59.54#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:11:59.54#ibcon#first serial, iclass 29, count 0 2006.257.11:11:59.54#ibcon#enter sib2, iclass 29, count 0 2006.257.11:11:59.54#ibcon#flushed, iclass 29, count 0 2006.257.11:11:59.54#ibcon#about to write, iclass 29, count 0 2006.257.11:11:59.54#ibcon#wrote, iclass 29, count 0 2006.257.11:11:59.54#ibcon#about to read 3, iclass 29, count 0 2006.257.11:11:59.56#ibcon#read 3, iclass 29, count 0 2006.257.11:11:59.56#ibcon#about to read 4, iclass 29, count 0 2006.257.11:11:59.56#ibcon#read 4, iclass 29, count 0 2006.257.11:11:59.56#ibcon#about to read 5, iclass 29, count 0 2006.257.11:11:59.56#ibcon#read 5, iclass 29, count 0 2006.257.11:11:59.56#ibcon#about to read 6, iclass 29, count 0 2006.257.11:11:59.56#ibcon#read 6, iclass 29, count 0 2006.257.11:11:59.56#ibcon#end of sib2, iclass 29, count 0 2006.257.11:11:59.56#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:11:59.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:11:59.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:11:59.56#ibcon#*before write, iclass 29, count 0 2006.257.11:11:59.56#ibcon#enter sib2, iclass 29, count 0 2006.257.11:11:59.56#ibcon#flushed, iclass 29, count 0 2006.257.11:11:59.56#ibcon#about to write, iclass 29, count 0 2006.257.11:11:59.56#ibcon#wrote, iclass 29, count 0 2006.257.11:11:59.56#ibcon#about to read 3, iclass 29, count 0 2006.257.11:11:59.60#ibcon#read 3, iclass 29, count 0 2006.257.11:11:59.60#ibcon#about to read 4, iclass 29, count 0 2006.257.11:11:59.60#ibcon#read 4, iclass 29, count 0 2006.257.11:11:59.60#ibcon#about to read 5, iclass 29, count 0 2006.257.11:11:59.60#ibcon#read 5, iclass 29, count 0 2006.257.11:11:59.60#ibcon#about to read 6, iclass 29, count 0 2006.257.11:11:59.60#ibcon#read 6, iclass 29, count 0 2006.257.11:11:59.60#ibcon#end of sib2, iclass 29, count 0 2006.257.11:11:59.60#ibcon#*after write, iclass 29, count 0 2006.257.11:11:59.60#ibcon#*before return 0, iclass 29, count 0 2006.257.11:11:59.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:11:59.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:11:59.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:11:59.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:11:59.60$vck44/va=5,4 2006.257.11:11:59.60#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.11:11:59.60#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.11:11:59.60#ibcon#ireg 11 cls_cnt 2 2006.257.11:11:59.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:11:59.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:11:59.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:11:59.66#ibcon#enter wrdev, iclass 31, count 2 2006.257.11:11:59.66#ibcon#first serial, iclass 31, count 2 2006.257.11:11:59.66#ibcon#enter sib2, iclass 31, count 2 2006.257.11:11:59.66#ibcon#flushed, iclass 31, count 2 2006.257.11:11:59.66#ibcon#about to write, iclass 31, count 2 2006.257.11:11:59.66#ibcon#wrote, iclass 31, count 2 2006.257.11:11:59.66#ibcon#about to read 3, iclass 31, count 2 2006.257.11:11:59.68#ibcon#read 3, iclass 31, count 2 2006.257.11:11:59.68#ibcon#about to read 4, iclass 31, count 2 2006.257.11:11:59.68#ibcon#read 4, iclass 31, count 2 2006.257.11:11:59.68#ibcon#about to read 5, iclass 31, count 2 2006.257.11:11:59.68#ibcon#read 5, iclass 31, count 2 2006.257.11:11:59.68#ibcon#about to read 6, iclass 31, count 2 2006.257.11:11:59.68#ibcon#read 6, iclass 31, count 2 2006.257.11:11:59.68#ibcon#end of sib2, iclass 31, count 2 2006.257.11:11:59.68#ibcon#*mode == 0, iclass 31, count 2 2006.257.11:11:59.68#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.11:11:59.68#ibcon#[25=AT05-04\r\n] 2006.257.11:11:59.68#ibcon#*before write, iclass 31, count 2 2006.257.11:11:59.68#ibcon#enter sib2, iclass 31, count 2 2006.257.11:11:59.68#ibcon#flushed, iclass 31, count 2 2006.257.11:11:59.68#ibcon#about to write, iclass 31, count 2 2006.257.11:11:59.68#ibcon#wrote, iclass 31, count 2 2006.257.11:11:59.68#ibcon#about to read 3, iclass 31, count 2 2006.257.11:11:59.71#ibcon#read 3, iclass 31, count 2 2006.257.11:11:59.71#ibcon#about to read 4, iclass 31, count 2 2006.257.11:11:59.71#ibcon#read 4, iclass 31, count 2 2006.257.11:11:59.71#ibcon#about to read 5, iclass 31, count 2 2006.257.11:11:59.71#ibcon#read 5, iclass 31, count 2 2006.257.11:11:59.71#ibcon#about to read 6, iclass 31, count 2 2006.257.11:11:59.71#ibcon#read 6, iclass 31, count 2 2006.257.11:11:59.71#ibcon#end of sib2, iclass 31, count 2 2006.257.11:11:59.71#ibcon#*after write, iclass 31, count 2 2006.257.11:11:59.71#ibcon#*before return 0, iclass 31, count 2 2006.257.11:11:59.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:11:59.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:11:59.71#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.11:11:59.71#ibcon#ireg 7 cls_cnt 0 2006.257.11:11:59.71#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:11:59.83#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:11:59.83#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:11:59.83#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:11:59.83#ibcon#first serial, iclass 31, count 0 2006.257.11:11:59.83#ibcon#enter sib2, iclass 31, count 0 2006.257.11:11:59.83#ibcon#flushed, iclass 31, count 0 2006.257.11:11:59.83#ibcon#about to write, iclass 31, count 0 2006.257.11:11:59.83#ibcon#wrote, iclass 31, count 0 2006.257.11:11:59.83#ibcon#about to read 3, iclass 31, count 0 2006.257.11:11:59.85#ibcon#read 3, iclass 31, count 0 2006.257.11:11:59.85#ibcon#about to read 4, iclass 31, count 0 2006.257.11:11:59.85#ibcon#read 4, iclass 31, count 0 2006.257.11:11:59.85#ibcon#about to read 5, iclass 31, count 0 2006.257.11:11:59.85#ibcon#read 5, iclass 31, count 0 2006.257.11:11:59.85#ibcon#about to read 6, iclass 31, count 0 2006.257.11:11:59.85#ibcon#read 6, iclass 31, count 0 2006.257.11:11:59.85#ibcon#end of sib2, iclass 31, count 0 2006.257.11:11:59.85#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:11:59.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:11:59.85#ibcon#[25=USB\r\n] 2006.257.11:11:59.85#ibcon#*before write, iclass 31, count 0 2006.257.11:11:59.85#ibcon#enter sib2, iclass 31, count 0 2006.257.11:11:59.85#ibcon#flushed, iclass 31, count 0 2006.257.11:11:59.85#ibcon#about to write, iclass 31, count 0 2006.257.11:11:59.85#ibcon#wrote, iclass 31, count 0 2006.257.11:11:59.85#ibcon#about to read 3, iclass 31, count 0 2006.257.11:11:59.88#ibcon#read 3, iclass 31, count 0 2006.257.11:11:59.88#ibcon#about to read 4, iclass 31, count 0 2006.257.11:11:59.88#ibcon#read 4, iclass 31, count 0 2006.257.11:11:59.88#ibcon#about to read 5, iclass 31, count 0 2006.257.11:11:59.88#ibcon#read 5, iclass 31, count 0 2006.257.11:11:59.88#ibcon#about to read 6, iclass 31, count 0 2006.257.11:11:59.88#ibcon#read 6, iclass 31, count 0 2006.257.11:11:59.88#ibcon#end of sib2, iclass 31, count 0 2006.257.11:11:59.88#ibcon#*after write, iclass 31, count 0 2006.257.11:11:59.88#ibcon#*before return 0, iclass 31, count 0 2006.257.11:11:59.88#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:11:59.88#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:11:59.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:11:59.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:11:59.88$vck44/valo=6,814.99 2006.257.11:11:59.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.11:11:59.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.11:11:59.88#ibcon#ireg 17 cls_cnt 0 2006.257.11:11:59.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:11:59.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:11:59.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:11:59.88#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:11:59.88#ibcon#first serial, iclass 33, count 0 2006.257.11:11:59.88#ibcon#enter sib2, iclass 33, count 0 2006.257.11:11:59.88#ibcon#flushed, iclass 33, count 0 2006.257.11:11:59.88#ibcon#about to write, iclass 33, count 0 2006.257.11:11:59.88#ibcon#wrote, iclass 33, count 0 2006.257.11:11:59.88#ibcon#about to read 3, iclass 33, count 0 2006.257.11:11:59.90#ibcon#read 3, iclass 33, count 0 2006.257.11:11:59.90#ibcon#about to read 4, iclass 33, count 0 2006.257.11:11:59.90#ibcon#read 4, iclass 33, count 0 2006.257.11:11:59.90#ibcon#about to read 5, iclass 33, count 0 2006.257.11:11:59.90#ibcon#read 5, iclass 33, count 0 2006.257.11:11:59.90#ibcon#about to read 6, iclass 33, count 0 2006.257.11:11:59.90#ibcon#read 6, iclass 33, count 0 2006.257.11:11:59.90#ibcon#end of sib2, iclass 33, count 0 2006.257.11:11:59.90#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:11:59.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:11:59.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:11:59.90#ibcon#*before write, iclass 33, count 0 2006.257.11:11:59.90#ibcon#enter sib2, iclass 33, count 0 2006.257.11:11:59.90#ibcon#flushed, iclass 33, count 0 2006.257.11:11:59.90#ibcon#about to write, iclass 33, count 0 2006.257.11:11:59.90#ibcon#wrote, iclass 33, count 0 2006.257.11:11:59.90#ibcon#about to read 3, iclass 33, count 0 2006.257.11:11:59.94#ibcon#read 3, iclass 33, count 0 2006.257.11:11:59.94#ibcon#about to read 4, iclass 33, count 0 2006.257.11:11:59.94#ibcon#read 4, iclass 33, count 0 2006.257.11:11:59.94#ibcon#about to read 5, iclass 33, count 0 2006.257.11:11:59.94#ibcon#read 5, iclass 33, count 0 2006.257.11:11:59.94#ibcon#about to read 6, iclass 33, count 0 2006.257.11:11:59.94#ibcon#read 6, iclass 33, count 0 2006.257.11:11:59.94#ibcon#end of sib2, iclass 33, count 0 2006.257.11:11:59.94#ibcon#*after write, iclass 33, count 0 2006.257.11:11:59.94#ibcon#*before return 0, iclass 33, count 0 2006.257.11:11:59.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:11:59.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:11:59.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:11:59.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:11:59.94$vck44/va=6,4 2006.257.11:11:59.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.11:11:59.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.11:11:59.94#ibcon#ireg 11 cls_cnt 2 2006.257.11:11:59.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:00.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:00.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:00.00#ibcon#enter wrdev, iclass 35, count 2 2006.257.11:12:00.00#ibcon#first serial, iclass 35, count 2 2006.257.11:12:00.00#ibcon#enter sib2, iclass 35, count 2 2006.257.11:12:00.00#ibcon#flushed, iclass 35, count 2 2006.257.11:12:00.00#ibcon#about to write, iclass 35, count 2 2006.257.11:12:00.00#ibcon#wrote, iclass 35, count 2 2006.257.11:12:00.00#ibcon#about to read 3, iclass 35, count 2 2006.257.11:12:00.02#ibcon#read 3, iclass 35, count 2 2006.257.11:12:00.02#ibcon#about to read 4, iclass 35, count 2 2006.257.11:12:00.02#ibcon#read 4, iclass 35, count 2 2006.257.11:12:00.02#ibcon#about to read 5, iclass 35, count 2 2006.257.11:12:00.02#ibcon#read 5, iclass 35, count 2 2006.257.11:12:00.02#ibcon#about to read 6, iclass 35, count 2 2006.257.11:12:00.02#ibcon#read 6, iclass 35, count 2 2006.257.11:12:00.02#ibcon#end of sib2, iclass 35, count 2 2006.257.11:12:00.02#ibcon#*mode == 0, iclass 35, count 2 2006.257.11:12:00.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.11:12:00.02#ibcon#[25=AT06-04\r\n] 2006.257.11:12:00.02#ibcon#*before write, iclass 35, count 2 2006.257.11:12:00.02#ibcon#enter sib2, iclass 35, count 2 2006.257.11:12:00.02#ibcon#flushed, iclass 35, count 2 2006.257.11:12:00.02#ibcon#about to write, iclass 35, count 2 2006.257.11:12:00.02#ibcon#wrote, iclass 35, count 2 2006.257.11:12:00.02#ibcon#about to read 3, iclass 35, count 2 2006.257.11:12:00.05#ibcon#read 3, iclass 35, count 2 2006.257.11:12:00.05#ibcon#about to read 4, iclass 35, count 2 2006.257.11:12:00.05#ibcon#read 4, iclass 35, count 2 2006.257.11:12:00.05#ibcon#about to read 5, iclass 35, count 2 2006.257.11:12:00.05#ibcon#read 5, iclass 35, count 2 2006.257.11:12:00.05#ibcon#about to read 6, iclass 35, count 2 2006.257.11:12:00.05#ibcon#read 6, iclass 35, count 2 2006.257.11:12:00.05#ibcon#end of sib2, iclass 35, count 2 2006.257.11:12:00.05#ibcon#*after write, iclass 35, count 2 2006.257.11:12:00.05#ibcon#*before return 0, iclass 35, count 2 2006.257.11:12:00.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:00.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:00.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.11:12:00.05#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:00.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:00.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:00.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:00.17#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:12:00.17#ibcon#first serial, iclass 35, count 0 2006.257.11:12:00.17#ibcon#enter sib2, iclass 35, count 0 2006.257.11:12:00.17#ibcon#flushed, iclass 35, count 0 2006.257.11:12:00.17#ibcon#about to write, iclass 35, count 0 2006.257.11:12:00.17#ibcon#wrote, iclass 35, count 0 2006.257.11:12:00.17#ibcon#about to read 3, iclass 35, count 0 2006.257.11:12:00.19#ibcon#read 3, iclass 35, count 0 2006.257.11:12:00.19#ibcon#about to read 4, iclass 35, count 0 2006.257.11:12:00.19#ibcon#read 4, iclass 35, count 0 2006.257.11:12:00.19#ibcon#about to read 5, iclass 35, count 0 2006.257.11:12:00.19#ibcon#read 5, iclass 35, count 0 2006.257.11:12:00.19#ibcon#about to read 6, iclass 35, count 0 2006.257.11:12:00.19#ibcon#read 6, iclass 35, count 0 2006.257.11:12:00.19#ibcon#end of sib2, iclass 35, count 0 2006.257.11:12:00.19#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:12:00.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:12:00.19#ibcon#[25=USB\r\n] 2006.257.11:12:00.19#ibcon#*before write, iclass 35, count 0 2006.257.11:12:00.19#ibcon#enter sib2, iclass 35, count 0 2006.257.11:12:00.19#ibcon#flushed, iclass 35, count 0 2006.257.11:12:00.19#ibcon#about to write, iclass 35, count 0 2006.257.11:12:00.19#ibcon#wrote, iclass 35, count 0 2006.257.11:12:00.19#ibcon#about to read 3, iclass 35, count 0 2006.257.11:12:00.22#ibcon#read 3, iclass 35, count 0 2006.257.11:12:00.22#ibcon#about to read 4, iclass 35, count 0 2006.257.11:12:00.22#ibcon#read 4, iclass 35, count 0 2006.257.11:12:00.22#ibcon#about to read 5, iclass 35, count 0 2006.257.11:12:00.22#ibcon#read 5, iclass 35, count 0 2006.257.11:12:00.22#ibcon#about to read 6, iclass 35, count 0 2006.257.11:12:00.22#ibcon#read 6, iclass 35, count 0 2006.257.11:12:00.22#ibcon#end of sib2, iclass 35, count 0 2006.257.11:12:00.22#ibcon#*after write, iclass 35, count 0 2006.257.11:12:00.22#ibcon#*before return 0, iclass 35, count 0 2006.257.11:12:00.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:00.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:00.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:12:00.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:12:00.22$vck44/valo=7,864.99 2006.257.11:12:00.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.11:12:00.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.11:12:00.22#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:00.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:00.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:00.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:00.22#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:12:00.22#ibcon#first serial, iclass 37, count 0 2006.257.11:12:00.22#ibcon#enter sib2, iclass 37, count 0 2006.257.11:12:00.22#ibcon#flushed, iclass 37, count 0 2006.257.11:12:00.22#ibcon#about to write, iclass 37, count 0 2006.257.11:12:00.22#ibcon#wrote, iclass 37, count 0 2006.257.11:12:00.22#ibcon#about to read 3, iclass 37, count 0 2006.257.11:12:00.24#ibcon#read 3, iclass 37, count 0 2006.257.11:12:00.24#ibcon#about to read 4, iclass 37, count 0 2006.257.11:12:00.24#ibcon#read 4, iclass 37, count 0 2006.257.11:12:00.24#ibcon#about to read 5, iclass 37, count 0 2006.257.11:12:00.24#ibcon#read 5, iclass 37, count 0 2006.257.11:12:00.24#ibcon#about to read 6, iclass 37, count 0 2006.257.11:12:00.24#ibcon#read 6, iclass 37, count 0 2006.257.11:12:00.24#ibcon#end of sib2, iclass 37, count 0 2006.257.11:12:00.24#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:12:00.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:12:00.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:12:00.24#ibcon#*before write, iclass 37, count 0 2006.257.11:12:00.24#ibcon#enter sib2, iclass 37, count 0 2006.257.11:12:00.24#ibcon#flushed, iclass 37, count 0 2006.257.11:12:00.24#ibcon#about to write, iclass 37, count 0 2006.257.11:12:00.24#ibcon#wrote, iclass 37, count 0 2006.257.11:12:00.24#ibcon#about to read 3, iclass 37, count 0 2006.257.11:12:00.28#ibcon#read 3, iclass 37, count 0 2006.257.11:12:00.28#ibcon#about to read 4, iclass 37, count 0 2006.257.11:12:00.28#ibcon#read 4, iclass 37, count 0 2006.257.11:12:00.28#ibcon#about to read 5, iclass 37, count 0 2006.257.11:12:00.28#ibcon#read 5, iclass 37, count 0 2006.257.11:12:00.28#ibcon#about to read 6, iclass 37, count 0 2006.257.11:12:00.28#ibcon#read 6, iclass 37, count 0 2006.257.11:12:00.28#ibcon#end of sib2, iclass 37, count 0 2006.257.11:12:00.28#ibcon#*after write, iclass 37, count 0 2006.257.11:12:00.28#ibcon#*before return 0, iclass 37, count 0 2006.257.11:12:00.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:00.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:00.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:12:00.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:12:00.28$vck44/va=7,4 2006.257.11:12:00.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.11:12:00.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.11:12:00.28#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:00.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:00.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:00.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:00.34#ibcon#enter wrdev, iclass 39, count 2 2006.257.11:12:00.34#ibcon#first serial, iclass 39, count 2 2006.257.11:12:00.34#ibcon#enter sib2, iclass 39, count 2 2006.257.11:12:00.34#ibcon#flushed, iclass 39, count 2 2006.257.11:12:00.34#ibcon#about to write, iclass 39, count 2 2006.257.11:12:00.34#ibcon#wrote, iclass 39, count 2 2006.257.11:12:00.34#ibcon#about to read 3, iclass 39, count 2 2006.257.11:12:00.36#ibcon#read 3, iclass 39, count 2 2006.257.11:12:00.36#ibcon#about to read 4, iclass 39, count 2 2006.257.11:12:00.36#ibcon#read 4, iclass 39, count 2 2006.257.11:12:00.36#ibcon#about to read 5, iclass 39, count 2 2006.257.11:12:00.36#ibcon#read 5, iclass 39, count 2 2006.257.11:12:00.36#ibcon#about to read 6, iclass 39, count 2 2006.257.11:12:00.36#ibcon#read 6, iclass 39, count 2 2006.257.11:12:00.36#ibcon#end of sib2, iclass 39, count 2 2006.257.11:12:00.36#ibcon#*mode == 0, iclass 39, count 2 2006.257.11:12:00.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.11:12:00.36#ibcon#[25=AT07-04\r\n] 2006.257.11:12:00.36#ibcon#*before write, iclass 39, count 2 2006.257.11:12:00.36#ibcon#enter sib2, iclass 39, count 2 2006.257.11:12:00.36#ibcon#flushed, iclass 39, count 2 2006.257.11:12:00.36#ibcon#about to write, iclass 39, count 2 2006.257.11:12:00.36#ibcon#wrote, iclass 39, count 2 2006.257.11:12:00.36#ibcon#about to read 3, iclass 39, count 2 2006.257.11:12:00.39#ibcon#read 3, iclass 39, count 2 2006.257.11:12:00.39#ibcon#about to read 4, iclass 39, count 2 2006.257.11:12:00.39#ibcon#read 4, iclass 39, count 2 2006.257.11:12:00.39#ibcon#about to read 5, iclass 39, count 2 2006.257.11:12:00.39#ibcon#read 5, iclass 39, count 2 2006.257.11:12:00.39#ibcon#about to read 6, iclass 39, count 2 2006.257.11:12:00.39#ibcon#read 6, iclass 39, count 2 2006.257.11:12:00.39#ibcon#end of sib2, iclass 39, count 2 2006.257.11:12:00.39#ibcon#*after write, iclass 39, count 2 2006.257.11:12:00.39#ibcon#*before return 0, iclass 39, count 2 2006.257.11:12:00.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:00.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:00.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.11:12:00.39#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:00.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:00.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:00.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:00.51#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:12:00.51#ibcon#first serial, iclass 39, count 0 2006.257.11:12:00.51#ibcon#enter sib2, iclass 39, count 0 2006.257.11:12:00.51#ibcon#flushed, iclass 39, count 0 2006.257.11:12:00.51#ibcon#about to write, iclass 39, count 0 2006.257.11:12:00.51#ibcon#wrote, iclass 39, count 0 2006.257.11:12:00.51#ibcon#about to read 3, iclass 39, count 0 2006.257.11:12:00.53#ibcon#read 3, iclass 39, count 0 2006.257.11:12:00.53#ibcon#about to read 4, iclass 39, count 0 2006.257.11:12:00.53#ibcon#read 4, iclass 39, count 0 2006.257.11:12:00.53#ibcon#about to read 5, iclass 39, count 0 2006.257.11:12:00.53#ibcon#read 5, iclass 39, count 0 2006.257.11:12:00.53#ibcon#about to read 6, iclass 39, count 0 2006.257.11:12:00.53#ibcon#read 6, iclass 39, count 0 2006.257.11:12:00.53#ibcon#end of sib2, iclass 39, count 0 2006.257.11:12:00.53#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:12:00.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:12:00.53#ibcon#[25=USB\r\n] 2006.257.11:12:00.53#ibcon#*before write, iclass 39, count 0 2006.257.11:12:00.53#ibcon#enter sib2, iclass 39, count 0 2006.257.11:12:00.53#ibcon#flushed, iclass 39, count 0 2006.257.11:12:00.53#ibcon#about to write, iclass 39, count 0 2006.257.11:12:00.53#ibcon#wrote, iclass 39, count 0 2006.257.11:12:00.53#ibcon#about to read 3, iclass 39, count 0 2006.257.11:12:00.56#ibcon#read 3, iclass 39, count 0 2006.257.11:12:00.56#ibcon#about to read 4, iclass 39, count 0 2006.257.11:12:00.56#ibcon#read 4, iclass 39, count 0 2006.257.11:12:00.56#ibcon#about to read 5, iclass 39, count 0 2006.257.11:12:00.56#ibcon#read 5, iclass 39, count 0 2006.257.11:12:00.56#ibcon#about to read 6, iclass 39, count 0 2006.257.11:12:00.56#ibcon#read 6, iclass 39, count 0 2006.257.11:12:00.56#ibcon#end of sib2, iclass 39, count 0 2006.257.11:12:00.56#ibcon#*after write, iclass 39, count 0 2006.257.11:12:00.56#ibcon#*before return 0, iclass 39, count 0 2006.257.11:12:00.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:00.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:00.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:12:00.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:12:00.56$vck44/valo=8,884.99 2006.257.11:12:00.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.11:12:00.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.11:12:00.56#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:00.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:00.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:00.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:00.56#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:12:00.56#ibcon#first serial, iclass 3, count 0 2006.257.11:12:00.56#ibcon#enter sib2, iclass 3, count 0 2006.257.11:12:00.56#ibcon#flushed, iclass 3, count 0 2006.257.11:12:00.56#ibcon#about to write, iclass 3, count 0 2006.257.11:12:00.56#ibcon#wrote, iclass 3, count 0 2006.257.11:12:00.56#ibcon#about to read 3, iclass 3, count 0 2006.257.11:12:00.58#ibcon#read 3, iclass 3, count 0 2006.257.11:12:00.58#ibcon#about to read 4, iclass 3, count 0 2006.257.11:12:00.58#ibcon#read 4, iclass 3, count 0 2006.257.11:12:00.58#ibcon#about to read 5, iclass 3, count 0 2006.257.11:12:00.58#ibcon#read 5, iclass 3, count 0 2006.257.11:12:00.58#ibcon#about to read 6, iclass 3, count 0 2006.257.11:12:00.58#ibcon#read 6, iclass 3, count 0 2006.257.11:12:00.58#ibcon#end of sib2, iclass 3, count 0 2006.257.11:12:00.58#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:12:00.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:12:00.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:12:00.58#ibcon#*before write, iclass 3, count 0 2006.257.11:12:00.58#ibcon#enter sib2, iclass 3, count 0 2006.257.11:12:00.58#ibcon#flushed, iclass 3, count 0 2006.257.11:12:00.58#ibcon#about to write, iclass 3, count 0 2006.257.11:12:00.58#ibcon#wrote, iclass 3, count 0 2006.257.11:12:00.58#ibcon#about to read 3, iclass 3, count 0 2006.257.11:12:00.62#ibcon#read 3, iclass 3, count 0 2006.257.11:12:00.62#ibcon#about to read 4, iclass 3, count 0 2006.257.11:12:00.62#ibcon#read 4, iclass 3, count 0 2006.257.11:12:00.62#ibcon#about to read 5, iclass 3, count 0 2006.257.11:12:00.62#ibcon#read 5, iclass 3, count 0 2006.257.11:12:00.62#ibcon#about to read 6, iclass 3, count 0 2006.257.11:12:00.62#ibcon#read 6, iclass 3, count 0 2006.257.11:12:00.62#ibcon#end of sib2, iclass 3, count 0 2006.257.11:12:00.62#ibcon#*after write, iclass 3, count 0 2006.257.11:12:00.62#ibcon#*before return 0, iclass 3, count 0 2006.257.11:12:00.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:00.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:00.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:12:00.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:12:00.62$vck44/va=8,4 2006.257.11:12:00.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.11:12:00.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.11:12:00.62#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:00.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:00.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:00.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:00.68#ibcon#enter wrdev, iclass 5, count 2 2006.257.11:12:00.68#ibcon#first serial, iclass 5, count 2 2006.257.11:12:00.68#ibcon#enter sib2, iclass 5, count 2 2006.257.11:12:00.68#ibcon#flushed, iclass 5, count 2 2006.257.11:12:00.68#ibcon#about to write, iclass 5, count 2 2006.257.11:12:00.68#ibcon#wrote, iclass 5, count 2 2006.257.11:12:00.68#ibcon#about to read 3, iclass 5, count 2 2006.257.11:12:00.70#ibcon#read 3, iclass 5, count 2 2006.257.11:12:00.70#ibcon#about to read 4, iclass 5, count 2 2006.257.11:12:00.70#ibcon#read 4, iclass 5, count 2 2006.257.11:12:00.70#ibcon#about to read 5, iclass 5, count 2 2006.257.11:12:00.70#ibcon#read 5, iclass 5, count 2 2006.257.11:12:00.70#ibcon#about to read 6, iclass 5, count 2 2006.257.11:12:00.70#ibcon#read 6, iclass 5, count 2 2006.257.11:12:00.70#ibcon#end of sib2, iclass 5, count 2 2006.257.11:12:00.70#ibcon#*mode == 0, iclass 5, count 2 2006.257.11:12:00.70#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.11:12:00.70#ibcon#[25=AT08-04\r\n] 2006.257.11:12:00.70#ibcon#*before write, iclass 5, count 2 2006.257.11:12:00.70#ibcon#enter sib2, iclass 5, count 2 2006.257.11:12:00.70#ibcon#flushed, iclass 5, count 2 2006.257.11:12:00.70#ibcon#about to write, iclass 5, count 2 2006.257.11:12:00.70#ibcon#wrote, iclass 5, count 2 2006.257.11:12:00.70#ibcon#about to read 3, iclass 5, count 2 2006.257.11:12:00.73#ibcon#read 3, iclass 5, count 2 2006.257.11:12:00.73#ibcon#about to read 4, iclass 5, count 2 2006.257.11:12:00.73#ibcon#read 4, iclass 5, count 2 2006.257.11:12:00.73#ibcon#about to read 5, iclass 5, count 2 2006.257.11:12:00.73#ibcon#read 5, iclass 5, count 2 2006.257.11:12:00.73#ibcon#about to read 6, iclass 5, count 2 2006.257.11:12:00.73#ibcon#read 6, iclass 5, count 2 2006.257.11:12:00.73#ibcon#end of sib2, iclass 5, count 2 2006.257.11:12:00.73#ibcon#*after write, iclass 5, count 2 2006.257.11:12:00.73#ibcon#*before return 0, iclass 5, count 2 2006.257.11:12:00.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:00.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:00.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.11:12:00.73#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:00.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:00.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:00.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:00.85#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:12:00.85#ibcon#first serial, iclass 5, count 0 2006.257.11:12:00.85#ibcon#enter sib2, iclass 5, count 0 2006.257.11:12:00.85#ibcon#flushed, iclass 5, count 0 2006.257.11:12:00.85#ibcon#about to write, iclass 5, count 0 2006.257.11:12:00.85#ibcon#wrote, iclass 5, count 0 2006.257.11:12:00.85#ibcon#about to read 3, iclass 5, count 0 2006.257.11:12:00.87#ibcon#read 3, iclass 5, count 0 2006.257.11:12:00.87#ibcon#about to read 4, iclass 5, count 0 2006.257.11:12:00.87#ibcon#read 4, iclass 5, count 0 2006.257.11:12:00.87#ibcon#about to read 5, iclass 5, count 0 2006.257.11:12:00.87#ibcon#read 5, iclass 5, count 0 2006.257.11:12:00.87#ibcon#about to read 6, iclass 5, count 0 2006.257.11:12:00.87#ibcon#read 6, iclass 5, count 0 2006.257.11:12:00.87#ibcon#end of sib2, iclass 5, count 0 2006.257.11:12:00.87#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:12:00.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:12:00.87#ibcon#[25=USB\r\n] 2006.257.11:12:00.87#ibcon#*before write, iclass 5, count 0 2006.257.11:12:00.87#ibcon#enter sib2, iclass 5, count 0 2006.257.11:12:00.87#ibcon#flushed, iclass 5, count 0 2006.257.11:12:00.87#ibcon#about to write, iclass 5, count 0 2006.257.11:12:00.87#ibcon#wrote, iclass 5, count 0 2006.257.11:12:00.87#ibcon#about to read 3, iclass 5, count 0 2006.257.11:12:00.90#ibcon#read 3, iclass 5, count 0 2006.257.11:12:00.90#ibcon#about to read 4, iclass 5, count 0 2006.257.11:12:00.90#ibcon#read 4, iclass 5, count 0 2006.257.11:12:00.90#ibcon#about to read 5, iclass 5, count 0 2006.257.11:12:00.90#ibcon#read 5, iclass 5, count 0 2006.257.11:12:00.90#ibcon#about to read 6, iclass 5, count 0 2006.257.11:12:00.90#ibcon#read 6, iclass 5, count 0 2006.257.11:12:00.90#ibcon#end of sib2, iclass 5, count 0 2006.257.11:12:00.90#ibcon#*after write, iclass 5, count 0 2006.257.11:12:00.90#ibcon#*before return 0, iclass 5, count 0 2006.257.11:12:00.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:00.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:00.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:12:00.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:12:00.90$vck44/vblo=1,629.99 2006.257.11:12:00.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.11:12:00.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.11:12:00.90#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:00.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:00.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:00.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:00.90#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:12:00.90#ibcon#first serial, iclass 7, count 0 2006.257.11:12:00.90#ibcon#enter sib2, iclass 7, count 0 2006.257.11:12:00.90#ibcon#flushed, iclass 7, count 0 2006.257.11:12:00.90#ibcon#about to write, iclass 7, count 0 2006.257.11:12:00.90#ibcon#wrote, iclass 7, count 0 2006.257.11:12:00.90#ibcon#about to read 3, iclass 7, count 0 2006.257.11:12:00.92#ibcon#read 3, iclass 7, count 0 2006.257.11:12:00.92#ibcon#about to read 4, iclass 7, count 0 2006.257.11:12:00.92#ibcon#read 4, iclass 7, count 0 2006.257.11:12:00.92#ibcon#about to read 5, iclass 7, count 0 2006.257.11:12:00.92#ibcon#read 5, iclass 7, count 0 2006.257.11:12:00.92#ibcon#about to read 6, iclass 7, count 0 2006.257.11:12:00.92#ibcon#read 6, iclass 7, count 0 2006.257.11:12:00.92#ibcon#end of sib2, iclass 7, count 0 2006.257.11:12:00.92#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:12:00.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:12:00.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:12:00.92#ibcon#*before write, iclass 7, count 0 2006.257.11:12:00.92#ibcon#enter sib2, iclass 7, count 0 2006.257.11:12:00.92#ibcon#flushed, iclass 7, count 0 2006.257.11:12:00.92#ibcon#about to write, iclass 7, count 0 2006.257.11:12:00.92#ibcon#wrote, iclass 7, count 0 2006.257.11:12:00.92#ibcon#about to read 3, iclass 7, count 0 2006.257.11:12:00.96#ibcon#read 3, iclass 7, count 0 2006.257.11:12:00.96#ibcon#about to read 4, iclass 7, count 0 2006.257.11:12:00.96#ibcon#read 4, iclass 7, count 0 2006.257.11:12:00.96#ibcon#about to read 5, iclass 7, count 0 2006.257.11:12:00.96#ibcon#read 5, iclass 7, count 0 2006.257.11:12:00.96#ibcon#about to read 6, iclass 7, count 0 2006.257.11:12:00.96#ibcon#read 6, iclass 7, count 0 2006.257.11:12:00.96#ibcon#end of sib2, iclass 7, count 0 2006.257.11:12:00.96#ibcon#*after write, iclass 7, count 0 2006.257.11:12:00.96#ibcon#*before return 0, iclass 7, count 0 2006.257.11:12:00.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:00.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:00.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:12:00.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:12:00.96$vck44/vb=1,4 2006.257.11:12:00.96#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.11:12:00.96#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.11:12:00.96#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:00.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:12:00.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:12:00.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:12:00.96#ibcon#enter wrdev, iclass 11, count 2 2006.257.11:12:00.96#ibcon#first serial, iclass 11, count 2 2006.257.11:12:00.96#ibcon#enter sib2, iclass 11, count 2 2006.257.11:12:00.96#ibcon#flushed, iclass 11, count 2 2006.257.11:12:00.96#ibcon#about to write, iclass 11, count 2 2006.257.11:12:00.96#ibcon#wrote, iclass 11, count 2 2006.257.11:12:00.96#ibcon#about to read 3, iclass 11, count 2 2006.257.11:12:00.98#ibcon#read 3, iclass 11, count 2 2006.257.11:12:00.98#ibcon#about to read 4, iclass 11, count 2 2006.257.11:12:00.98#ibcon#read 4, iclass 11, count 2 2006.257.11:12:00.98#ibcon#about to read 5, iclass 11, count 2 2006.257.11:12:00.98#ibcon#read 5, iclass 11, count 2 2006.257.11:12:00.98#ibcon#about to read 6, iclass 11, count 2 2006.257.11:12:00.98#ibcon#read 6, iclass 11, count 2 2006.257.11:12:00.98#ibcon#end of sib2, iclass 11, count 2 2006.257.11:12:00.98#ibcon#*mode == 0, iclass 11, count 2 2006.257.11:12:00.98#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.11:12:00.98#ibcon#[27=AT01-04\r\n] 2006.257.11:12:00.98#ibcon#*before write, iclass 11, count 2 2006.257.11:12:00.98#ibcon#enter sib2, iclass 11, count 2 2006.257.11:12:00.98#ibcon#flushed, iclass 11, count 2 2006.257.11:12:00.98#ibcon#about to write, iclass 11, count 2 2006.257.11:12:00.98#ibcon#wrote, iclass 11, count 2 2006.257.11:12:00.98#ibcon#about to read 3, iclass 11, count 2 2006.257.11:12:01.01#ibcon#read 3, iclass 11, count 2 2006.257.11:12:01.01#ibcon#about to read 4, iclass 11, count 2 2006.257.11:12:01.01#ibcon#read 4, iclass 11, count 2 2006.257.11:12:01.01#ibcon#about to read 5, iclass 11, count 2 2006.257.11:12:01.01#ibcon#read 5, iclass 11, count 2 2006.257.11:12:01.01#ibcon#about to read 6, iclass 11, count 2 2006.257.11:12:01.01#ibcon#read 6, iclass 11, count 2 2006.257.11:12:01.01#ibcon#end of sib2, iclass 11, count 2 2006.257.11:12:01.01#ibcon#*after write, iclass 11, count 2 2006.257.11:12:01.01#ibcon#*before return 0, iclass 11, count 2 2006.257.11:12:01.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:12:01.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:12:01.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.11:12:01.01#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:01.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:12:01.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:12:01.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:12:01.13#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:12:01.13#ibcon#first serial, iclass 11, count 0 2006.257.11:12:01.13#ibcon#enter sib2, iclass 11, count 0 2006.257.11:12:01.13#ibcon#flushed, iclass 11, count 0 2006.257.11:12:01.13#ibcon#about to write, iclass 11, count 0 2006.257.11:12:01.13#ibcon#wrote, iclass 11, count 0 2006.257.11:12:01.13#ibcon#about to read 3, iclass 11, count 0 2006.257.11:12:01.15#ibcon#read 3, iclass 11, count 0 2006.257.11:12:01.15#ibcon#about to read 4, iclass 11, count 0 2006.257.11:12:01.15#ibcon#read 4, iclass 11, count 0 2006.257.11:12:01.15#ibcon#about to read 5, iclass 11, count 0 2006.257.11:12:01.15#ibcon#read 5, iclass 11, count 0 2006.257.11:12:01.15#ibcon#about to read 6, iclass 11, count 0 2006.257.11:12:01.15#ibcon#read 6, iclass 11, count 0 2006.257.11:12:01.15#ibcon#end of sib2, iclass 11, count 0 2006.257.11:12:01.15#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:12:01.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:12:01.15#ibcon#[27=USB\r\n] 2006.257.11:12:01.15#ibcon#*before write, iclass 11, count 0 2006.257.11:12:01.15#ibcon#enter sib2, iclass 11, count 0 2006.257.11:12:01.15#ibcon#flushed, iclass 11, count 0 2006.257.11:12:01.15#ibcon#about to write, iclass 11, count 0 2006.257.11:12:01.15#ibcon#wrote, iclass 11, count 0 2006.257.11:12:01.15#ibcon#about to read 3, iclass 11, count 0 2006.257.11:12:01.18#ibcon#read 3, iclass 11, count 0 2006.257.11:12:01.18#ibcon#about to read 4, iclass 11, count 0 2006.257.11:12:01.18#ibcon#read 4, iclass 11, count 0 2006.257.11:12:01.18#ibcon#about to read 5, iclass 11, count 0 2006.257.11:12:01.18#ibcon#read 5, iclass 11, count 0 2006.257.11:12:01.18#ibcon#about to read 6, iclass 11, count 0 2006.257.11:12:01.18#ibcon#read 6, iclass 11, count 0 2006.257.11:12:01.18#ibcon#end of sib2, iclass 11, count 0 2006.257.11:12:01.18#ibcon#*after write, iclass 11, count 0 2006.257.11:12:01.18#ibcon#*before return 0, iclass 11, count 0 2006.257.11:12:01.18#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:12:01.18#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:12:01.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:12:01.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:12:01.18$vck44/vblo=2,634.99 2006.257.11:12:01.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.11:12:01.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.11:12:01.18#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:01.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:12:01.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:12:01.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:12:01.18#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:12:01.18#ibcon#first serial, iclass 13, count 0 2006.257.11:12:01.18#ibcon#enter sib2, iclass 13, count 0 2006.257.11:12:01.18#ibcon#flushed, iclass 13, count 0 2006.257.11:12:01.18#ibcon#about to write, iclass 13, count 0 2006.257.11:12:01.18#ibcon#wrote, iclass 13, count 0 2006.257.11:12:01.18#ibcon#about to read 3, iclass 13, count 0 2006.257.11:12:01.20#ibcon#read 3, iclass 13, count 0 2006.257.11:12:01.20#ibcon#about to read 4, iclass 13, count 0 2006.257.11:12:01.20#ibcon#read 4, iclass 13, count 0 2006.257.11:12:01.20#ibcon#about to read 5, iclass 13, count 0 2006.257.11:12:01.20#ibcon#read 5, iclass 13, count 0 2006.257.11:12:01.20#ibcon#about to read 6, iclass 13, count 0 2006.257.11:12:01.20#ibcon#read 6, iclass 13, count 0 2006.257.11:12:01.20#ibcon#end of sib2, iclass 13, count 0 2006.257.11:12:01.20#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:12:01.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:12:01.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:12:01.20#ibcon#*before write, iclass 13, count 0 2006.257.11:12:01.20#ibcon#enter sib2, iclass 13, count 0 2006.257.11:12:01.20#ibcon#flushed, iclass 13, count 0 2006.257.11:12:01.20#ibcon#about to write, iclass 13, count 0 2006.257.11:12:01.20#ibcon#wrote, iclass 13, count 0 2006.257.11:12:01.20#ibcon#about to read 3, iclass 13, count 0 2006.257.11:12:01.24#ibcon#read 3, iclass 13, count 0 2006.257.11:12:01.24#ibcon#about to read 4, iclass 13, count 0 2006.257.11:12:01.24#ibcon#read 4, iclass 13, count 0 2006.257.11:12:01.24#ibcon#about to read 5, iclass 13, count 0 2006.257.11:12:01.24#ibcon#read 5, iclass 13, count 0 2006.257.11:12:01.24#ibcon#about to read 6, iclass 13, count 0 2006.257.11:12:01.24#ibcon#read 6, iclass 13, count 0 2006.257.11:12:01.24#ibcon#end of sib2, iclass 13, count 0 2006.257.11:12:01.24#ibcon#*after write, iclass 13, count 0 2006.257.11:12:01.24#ibcon#*before return 0, iclass 13, count 0 2006.257.11:12:01.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:12:01.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:12:01.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:12:01.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:12:01.24$vck44/vb=2,5 2006.257.11:12:01.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.11:12:01.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.11:12:01.24#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:01.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:12:01.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:12:01.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:12:01.30#ibcon#enter wrdev, iclass 15, count 2 2006.257.11:12:01.30#ibcon#first serial, iclass 15, count 2 2006.257.11:12:01.30#ibcon#enter sib2, iclass 15, count 2 2006.257.11:12:01.30#ibcon#flushed, iclass 15, count 2 2006.257.11:12:01.30#ibcon#about to write, iclass 15, count 2 2006.257.11:12:01.30#ibcon#wrote, iclass 15, count 2 2006.257.11:12:01.30#ibcon#about to read 3, iclass 15, count 2 2006.257.11:12:01.32#ibcon#read 3, iclass 15, count 2 2006.257.11:12:01.32#ibcon#about to read 4, iclass 15, count 2 2006.257.11:12:01.32#ibcon#read 4, iclass 15, count 2 2006.257.11:12:01.32#ibcon#about to read 5, iclass 15, count 2 2006.257.11:12:01.32#ibcon#read 5, iclass 15, count 2 2006.257.11:12:01.32#ibcon#about to read 6, iclass 15, count 2 2006.257.11:12:01.32#ibcon#read 6, iclass 15, count 2 2006.257.11:12:01.32#ibcon#end of sib2, iclass 15, count 2 2006.257.11:12:01.32#ibcon#*mode == 0, iclass 15, count 2 2006.257.11:12:01.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.11:12:01.32#ibcon#[27=AT02-05\r\n] 2006.257.11:12:01.32#ibcon#*before write, iclass 15, count 2 2006.257.11:12:01.32#ibcon#enter sib2, iclass 15, count 2 2006.257.11:12:01.32#ibcon#flushed, iclass 15, count 2 2006.257.11:12:01.32#ibcon#about to write, iclass 15, count 2 2006.257.11:12:01.32#ibcon#wrote, iclass 15, count 2 2006.257.11:12:01.32#ibcon#about to read 3, iclass 15, count 2 2006.257.11:12:01.35#ibcon#read 3, iclass 15, count 2 2006.257.11:12:01.35#ibcon#about to read 4, iclass 15, count 2 2006.257.11:12:01.35#ibcon#read 4, iclass 15, count 2 2006.257.11:12:01.35#ibcon#about to read 5, iclass 15, count 2 2006.257.11:12:01.35#ibcon#read 5, iclass 15, count 2 2006.257.11:12:01.35#ibcon#about to read 6, iclass 15, count 2 2006.257.11:12:01.35#ibcon#read 6, iclass 15, count 2 2006.257.11:12:01.35#ibcon#end of sib2, iclass 15, count 2 2006.257.11:12:01.35#ibcon#*after write, iclass 15, count 2 2006.257.11:12:01.35#ibcon#*before return 0, iclass 15, count 2 2006.257.11:12:01.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:12:01.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:12:01.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.11:12:01.35#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:01.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:12:01.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:12:01.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:12:01.47#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:12:01.47#ibcon#first serial, iclass 15, count 0 2006.257.11:12:01.47#ibcon#enter sib2, iclass 15, count 0 2006.257.11:12:01.47#ibcon#flushed, iclass 15, count 0 2006.257.11:12:01.47#ibcon#about to write, iclass 15, count 0 2006.257.11:12:01.47#ibcon#wrote, iclass 15, count 0 2006.257.11:12:01.47#ibcon#about to read 3, iclass 15, count 0 2006.257.11:12:01.49#ibcon#read 3, iclass 15, count 0 2006.257.11:12:01.49#ibcon#about to read 4, iclass 15, count 0 2006.257.11:12:01.49#ibcon#read 4, iclass 15, count 0 2006.257.11:12:01.49#ibcon#about to read 5, iclass 15, count 0 2006.257.11:12:01.49#ibcon#read 5, iclass 15, count 0 2006.257.11:12:01.49#ibcon#about to read 6, iclass 15, count 0 2006.257.11:12:01.49#ibcon#read 6, iclass 15, count 0 2006.257.11:12:01.49#ibcon#end of sib2, iclass 15, count 0 2006.257.11:12:01.49#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:12:01.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:12:01.49#ibcon#[27=USB\r\n] 2006.257.11:12:01.49#ibcon#*before write, iclass 15, count 0 2006.257.11:12:01.49#ibcon#enter sib2, iclass 15, count 0 2006.257.11:12:01.49#ibcon#flushed, iclass 15, count 0 2006.257.11:12:01.49#ibcon#about to write, iclass 15, count 0 2006.257.11:12:01.49#ibcon#wrote, iclass 15, count 0 2006.257.11:12:01.49#ibcon#about to read 3, iclass 15, count 0 2006.257.11:12:01.52#ibcon#read 3, iclass 15, count 0 2006.257.11:12:01.52#ibcon#about to read 4, iclass 15, count 0 2006.257.11:12:01.52#ibcon#read 4, iclass 15, count 0 2006.257.11:12:01.52#ibcon#about to read 5, iclass 15, count 0 2006.257.11:12:01.52#ibcon#read 5, iclass 15, count 0 2006.257.11:12:01.52#ibcon#about to read 6, iclass 15, count 0 2006.257.11:12:01.52#ibcon#read 6, iclass 15, count 0 2006.257.11:12:01.52#ibcon#end of sib2, iclass 15, count 0 2006.257.11:12:01.52#ibcon#*after write, iclass 15, count 0 2006.257.11:12:01.52#ibcon#*before return 0, iclass 15, count 0 2006.257.11:12:01.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:12:01.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:12:01.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:12:01.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:12:01.52$vck44/vblo=3,649.99 2006.257.11:12:01.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.11:12:01.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.11:12:01.52#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:01.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:12:01.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:12:01.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:12:01.52#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:12:01.52#ibcon#first serial, iclass 17, count 0 2006.257.11:12:01.52#ibcon#enter sib2, iclass 17, count 0 2006.257.11:12:01.52#ibcon#flushed, iclass 17, count 0 2006.257.11:12:01.52#ibcon#about to write, iclass 17, count 0 2006.257.11:12:01.52#ibcon#wrote, iclass 17, count 0 2006.257.11:12:01.52#ibcon#about to read 3, iclass 17, count 0 2006.257.11:12:01.54#ibcon#read 3, iclass 17, count 0 2006.257.11:12:01.54#ibcon#about to read 4, iclass 17, count 0 2006.257.11:12:01.54#ibcon#read 4, iclass 17, count 0 2006.257.11:12:01.54#ibcon#about to read 5, iclass 17, count 0 2006.257.11:12:01.54#ibcon#read 5, iclass 17, count 0 2006.257.11:12:01.54#ibcon#about to read 6, iclass 17, count 0 2006.257.11:12:01.54#ibcon#read 6, iclass 17, count 0 2006.257.11:12:01.54#ibcon#end of sib2, iclass 17, count 0 2006.257.11:12:01.54#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:12:01.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:12:01.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:12:01.54#ibcon#*before write, iclass 17, count 0 2006.257.11:12:01.54#ibcon#enter sib2, iclass 17, count 0 2006.257.11:12:01.54#ibcon#flushed, iclass 17, count 0 2006.257.11:12:01.54#ibcon#about to write, iclass 17, count 0 2006.257.11:12:01.54#ibcon#wrote, iclass 17, count 0 2006.257.11:12:01.54#ibcon#about to read 3, iclass 17, count 0 2006.257.11:12:01.58#ibcon#read 3, iclass 17, count 0 2006.257.11:12:01.58#ibcon#about to read 4, iclass 17, count 0 2006.257.11:12:01.58#ibcon#read 4, iclass 17, count 0 2006.257.11:12:01.58#ibcon#about to read 5, iclass 17, count 0 2006.257.11:12:01.58#ibcon#read 5, iclass 17, count 0 2006.257.11:12:01.58#ibcon#about to read 6, iclass 17, count 0 2006.257.11:12:01.58#ibcon#read 6, iclass 17, count 0 2006.257.11:12:01.58#ibcon#end of sib2, iclass 17, count 0 2006.257.11:12:01.58#ibcon#*after write, iclass 17, count 0 2006.257.11:12:01.58#ibcon#*before return 0, iclass 17, count 0 2006.257.11:12:01.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:12:01.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:12:01.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:12:01.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:12:01.58$vck44/vb=3,4 2006.257.11:12:01.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.11:12:01.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.11:12:01.58#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:01.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:12:01.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:12:01.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:12:01.64#ibcon#enter wrdev, iclass 19, count 2 2006.257.11:12:01.64#ibcon#first serial, iclass 19, count 2 2006.257.11:12:01.64#ibcon#enter sib2, iclass 19, count 2 2006.257.11:12:01.64#ibcon#flushed, iclass 19, count 2 2006.257.11:12:01.64#ibcon#about to write, iclass 19, count 2 2006.257.11:12:01.64#ibcon#wrote, iclass 19, count 2 2006.257.11:12:01.64#ibcon#about to read 3, iclass 19, count 2 2006.257.11:12:01.66#ibcon#read 3, iclass 19, count 2 2006.257.11:12:01.66#ibcon#about to read 4, iclass 19, count 2 2006.257.11:12:01.66#ibcon#read 4, iclass 19, count 2 2006.257.11:12:01.66#ibcon#about to read 5, iclass 19, count 2 2006.257.11:12:01.66#ibcon#read 5, iclass 19, count 2 2006.257.11:12:01.66#ibcon#about to read 6, iclass 19, count 2 2006.257.11:12:01.66#ibcon#read 6, iclass 19, count 2 2006.257.11:12:01.66#ibcon#end of sib2, iclass 19, count 2 2006.257.11:12:01.66#ibcon#*mode == 0, iclass 19, count 2 2006.257.11:12:01.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.11:12:01.66#ibcon#[27=AT03-04\r\n] 2006.257.11:12:01.66#ibcon#*before write, iclass 19, count 2 2006.257.11:12:01.66#ibcon#enter sib2, iclass 19, count 2 2006.257.11:12:01.66#ibcon#flushed, iclass 19, count 2 2006.257.11:12:01.66#ibcon#about to write, iclass 19, count 2 2006.257.11:12:01.66#ibcon#wrote, iclass 19, count 2 2006.257.11:12:01.66#ibcon#about to read 3, iclass 19, count 2 2006.257.11:12:01.69#ibcon#read 3, iclass 19, count 2 2006.257.11:12:01.69#ibcon#about to read 4, iclass 19, count 2 2006.257.11:12:01.69#ibcon#read 4, iclass 19, count 2 2006.257.11:12:01.69#ibcon#about to read 5, iclass 19, count 2 2006.257.11:12:01.69#ibcon#read 5, iclass 19, count 2 2006.257.11:12:01.69#ibcon#about to read 6, iclass 19, count 2 2006.257.11:12:01.69#ibcon#read 6, iclass 19, count 2 2006.257.11:12:01.69#ibcon#end of sib2, iclass 19, count 2 2006.257.11:12:01.69#ibcon#*after write, iclass 19, count 2 2006.257.11:12:01.69#ibcon#*before return 0, iclass 19, count 2 2006.257.11:12:01.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:12:01.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:12:01.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.11:12:01.69#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:01.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:12:01.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:12:01.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:12:01.81#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:12:01.81#ibcon#first serial, iclass 19, count 0 2006.257.11:12:01.81#ibcon#enter sib2, iclass 19, count 0 2006.257.11:12:01.81#ibcon#flushed, iclass 19, count 0 2006.257.11:12:01.81#ibcon#about to write, iclass 19, count 0 2006.257.11:12:01.81#ibcon#wrote, iclass 19, count 0 2006.257.11:12:01.81#ibcon#about to read 3, iclass 19, count 0 2006.257.11:12:01.83#ibcon#read 3, iclass 19, count 0 2006.257.11:12:01.83#ibcon#about to read 4, iclass 19, count 0 2006.257.11:12:01.83#ibcon#read 4, iclass 19, count 0 2006.257.11:12:01.83#ibcon#about to read 5, iclass 19, count 0 2006.257.11:12:01.83#ibcon#read 5, iclass 19, count 0 2006.257.11:12:01.83#ibcon#about to read 6, iclass 19, count 0 2006.257.11:12:01.83#ibcon#read 6, iclass 19, count 0 2006.257.11:12:01.83#ibcon#end of sib2, iclass 19, count 0 2006.257.11:12:01.83#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:12:01.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:12:01.83#ibcon#[27=USB\r\n] 2006.257.11:12:01.83#ibcon#*before write, iclass 19, count 0 2006.257.11:12:01.83#ibcon#enter sib2, iclass 19, count 0 2006.257.11:12:01.83#ibcon#flushed, iclass 19, count 0 2006.257.11:12:01.83#ibcon#about to write, iclass 19, count 0 2006.257.11:12:01.83#ibcon#wrote, iclass 19, count 0 2006.257.11:12:01.83#ibcon#about to read 3, iclass 19, count 0 2006.257.11:12:01.86#ibcon#read 3, iclass 19, count 0 2006.257.11:12:01.86#ibcon#about to read 4, iclass 19, count 0 2006.257.11:12:01.86#ibcon#read 4, iclass 19, count 0 2006.257.11:12:01.86#ibcon#about to read 5, iclass 19, count 0 2006.257.11:12:01.86#ibcon#read 5, iclass 19, count 0 2006.257.11:12:01.86#ibcon#about to read 6, iclass 19, count 0 2006.257.11:12:01.86#ibcon#read 6, iclass 19, count 0 2006.257.11:12:01.86#ibcon#end of sib2, iclass 19, count 0 2006.257.11:12:01.86#ibcon#*after write, iclass 19, count 0 2006.257.11:12:01.86#ibcon#*before return 0, iclass 19, count 0 2006.257.11:12:01.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:12:01.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:12:01.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:12:01.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:12:01.86$vck44/vblo=4,679.99 2006.257.11:12:01.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.11:12:01.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.11:12:01.86#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:01.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:12:01.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:12:01.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:12:01.86#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:12:01.86#ibcon#first serial, iclass 21, count 0 2006.257.11:12:01.86#ibcon#enter sib2, iclass 21, count 0 2006.257.11:12:01.86#ibcon#flushed, iclass 21, count 0 2006.257.11:12:01.86#ibcon#about to write, iclass 21, count 0 2006.257.11:12:01.86#ibcon#wrote, iclass 21, count 0 2006.257.11:12:01.86#ibcon#about to read 3, iclass 21, count 0 2006.257.11:12:01.88#ibcon#read 3, iclass 21, count 0 2006.257.11:12:01.88#ibcon#about to read 4, iclass 21, count 0 2006.257.11:12:01.88#ibcon#read 4, iclass 21, count 0 2006.257.11:12:01.88#ibcon#about to read 5, iclass 21, count 0 2006.257.11:12:01.88#ibcon#read 5, iclass 21, count 0 2006.257.11:12:01.88#ibcon#about to read 6, iclass 21, count 0 2006.257.11:12:01.88#ibcon#read 6, iclass 21, count 0 2006.257.11:12:01.88#ibcon#end of sib2, iclass 21, count 0 2006.257.11:12:01.88#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:12:01.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:12:01.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:12:01.88#ibcon#*before write, iclass 21, count 0 2006.257.11:12:01.88#ibcon#enter sib2, iclass 21, count 0 2006.257.11:12:01.88#ibcon#flushed, iclass 21, count 0 2006.257.11:12:01.88#ibcon#about to write, iclass 21, count 0 2006.257.11:12:01.88#ibcon#wrote, iclass 21, count 0 2006.257.11:12:01.88#ibcon#about to read 3, iclass 21, count 0 2006.257.11:12:01.92#ibcon#read 3, iclass 21, count 0 2006.257.11:12:01.92#ibcon#about to read 4, iclass 21, count 0 2006.257.11:12:01.92#ibcon#read 4, iclass 21, count 0 2006.257.11:12:01.92#ibcon#about to read 5, iclass 21, count 0 2006.257.11:12:01.92#ibcon#read 5, iclass 21, count 0 2006.257.11:12:01.92#ibcon#about to read 6, iclass 21, count 0 2006.257.11:12:01.92#ibcon#read 6, iclass 21, count 0 2006.257.11:12:01.92#ibcon#end of sib2, iclass 21, count 0 2006.257.11:12:01.92#ibcon#*after write, iclass 21, count 0 2006.257.11:12:01.92#ibcon#*before return 0, iclass 21, count 0 2006.257.11:12:01.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:12:01.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:12:01.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:12:01.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:12:01.92$vck44/vb=4,5 2006.257.11:12:01.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.11:12:01.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.11:12:01.92#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:01.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:12:01.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:12:01.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:12:01.98#ibcon#enter wrdev, iclass 23, count 2 2006.257.11:12:01.98#ibcon#first serial, iclass 23, count 2 2006.257.11:12:01.98#ibcon#enter sib2, iclass 23, count 2 2006.257.11:12:01.98#ibcon#flushed, iclass 23, count 2 2006.257.11:12:01.98#ibcon#about to write, iclass 23, count 2 2006.257.11:12:01.98#ibcon#wrote, iclass 23, count 2 2006.257.11:12:01.98#ibcon#about to read 3, iclass 23, count 2 2006.257.11:12:02.00#ibcon#read 3, iclass 23, count 2 2006.257.11:12:02.00#ibcon#about to read 4, iclass 23, count 2 2006.257.11:12:02.00#ibcon#read 4, iclass 23, count 2 2006.257.11:12:02.00#ibcon#about to read 5, iclass 23, count 2 2006.257.11:12:02.00#ibcon#read 5, iclass 23, count 2 2006.257.11:12:02.00#ibcon#about to read 6, iclass 23, count 2 2006.257.11:12:02.00#ibcon#read 6, iclass 23, count 2 2006.257.11:12:02.00#ibcon#end of sib2, iclass 23, count 2 2006.257.11:12:02.00#ibcon#*mode == 0, iclass 23, count 2 2006.257.11:12:02.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.11:12:02.00#ibcon#[27=AT04-05\r\n] 2006.257.11:12:02.00#ibcon#*before write, iclass 23, count 2 2006.257.11:12:02.00#ibcon#enter sib2, iclass 23, count 2 2006.257.11:12:02.00#ibcon#flushed, iclass 23, count 2 2006.257.11:12:02.00#ibcon#about to write, iclass 23, count 2 2006.257.11:12:02.00#ibcon#wrote, iclass 23, count 2 2006.257.11:12:02.00#ibcon#about to read 3, iclass 23, count 2 2006.257.11:12:02.01#abcon#<5=/15 1.6 3.5 18.47 961013.9\r\n> 2006.257.11:12:02.03#abcon#{5=INTERFACE CLEAR} 2006.257.11:12:02.03#ibcon#read 3, iclass 23, count 2 2006.257.11:12:02.03#ibcon#about to read 4, iclass 23, count 2 2006.257.11:12:02.03#ibcon#read 4, iclass 23, count 2 2006.257.11:12:02.03#ibcon#about to read 5, iclass 23, count 2 2006.257.11:12:02.03#ibcon#read 5, iclass 23, count 2 2006.257.11:12:02.03#ibcon#about to read 6, iclass 23, count 2 2006.257.11:12:02.03#ibcon#read 6, iclass 23, count 2 2006.257.11:12:02.03#ibcon#end of sib2, iclass 23, count 2 2006.257.11:12:02.03#ibcon#*after write, iclass 23, count 2 2006.257.11:12:02.03#ibcon#*before return 0, iclass 23, count 2 2006.257.11:12:02.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:12:02.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:12:02.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.11:12:02.03#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:02.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:12:02.09#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:12:02.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:12:02.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:12:02.15#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:12:02.15#ibcon#first serial, iclass 23, count 0 2006.257.11:12:02.15#ibcon#enter sib2, iclass 23, count 0 2006.257.11:12:02.15#ibcon#flushed, iclass 23, count 0 2006.257.11:12:02.15#ibcon#about to write, iclass 23, count 0 2006.257.11:12:02.15#ibcon#wrote, iclass 23, count 0 2006.257.11:12:02.15#ibcon#about to read 3, iclass 23, count 0 2006.257.11:12:02.17#ibcon#read 3, iclass 23, count 0 2006.257.11:12:02.17#ibcon#about to read 4, iclass 23, count 0 2006.257.11:12:02.17#ibcon#read 4, iclass 23, count 0 2006.257.11:12:02.17#ibcon#about to read 5, iclass 23, count 0 2006.257.11:12:02.17#ibcon#read 5, iclass 23, count 0 2006.257.11:12:02.17#ibcon#about to read 6, iclass 23, count 0 2006.257.11:12:02.17#ibcon#read 6, iclass 23, count 0 2006.257.11:12:02.17#ibcon#end of sib2, iclass 23, count 0 2006.257.11:12:02.17#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:12:02.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:12:02.17#ibcon#[27=USB\r\n] 2006.257.11:12:02.17#ibcon#*before write, iclass 23, count 0 2006.257.11:12:02.17#ibcon#enter sib2, iclass 23, count 0 2006.257.11:12:02.17#ibcon#flushed, iclass 23, count 0 2006.257.11:12:02.17#ibcon#about to write, iclass 23, count 0 2006.257.11:12:02.17#ibcon#wrote, iclass 23, count 0 2006.257.11:12:02.17#ibcon#about to read 3, iclass 23, count 0 2006.257.11:12:02.20#ibcon#read 3, iclass 23, count 0 2006.257.11:12:02.20#ibcon#about to read 4, iclass 23, count 0 2006.257.11:12:02.20#ibcon#read 4, iclass 23, count 0 2006.257.11:12:02.20#ibcon#about to read 5, iclass 23, count 0 2006.257.11:12:02.20#ibcon#read 5, iclass 23, count 0 2006.257.11:12:02.20#ibcon#about to read 6, iclass 23, count 0 2006.257.11:12:02.20#ibcon#read 6, iclass 23, count 0 2006.257.11:12:02.20#ibcon#end of sib2, iclass 23, count 0 2006.257.11:12:02.20#ibcon#*after write, iclass 23, count 0 2006.257.11:12:02.20#ibcon#*before return 0, iclass 23, count 0 2006.257.11:12:02.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:12:02.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:12:02.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:12:02.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:12:02.20$vck44/vblo=5,709.99 2006.257.11:12:02.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.11:12:02.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.11:12:02.20#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:02.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:12:02.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:12:02.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:12:02.20#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:12:02.20#ibcon#first serial, iclass 29, count 0 2006.257.11:12:02.20#ibcon#enter sib2, iclass 29, count 0 2006.257.11:12:02.20#ibcon#flushed, iclass 29, count 0 2006.257.11:12:02.20#ibcon#about to write, iclass 29, count 0 2006.257.11:12:02.20#ibcon#wrote, iclass 29, count 0 2006.257.11:12:02.20#ibcon#about to read 3, iclass 29, count 0 2006.257.11:12:02.22#ibcon#read 3, iclass 29, count 0 2006.257.11:12:02.22#ibcon#about to read 4, iclass 29, count 0 2006.257.11:12:02.22#ibcon#read 4, iclass 29, count 0 2006.257.11:12:02.22#ibcon#about to read 5, iclass 29, count 0 2006.257.11:12:02.22#ibcon#read 5, iclass 29, count 0 2006.257.11:12:02.22#ibcon#about to read 6, iclass 29, count 0 2006.257.11:12:02.22#ibcon#read 6, iclass 29, count 0 2006.257.11:12:02.22#ibcon#end of sib2, iclass 29, count 0 2006.257.11:12:02.22#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:12:02.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:12:02.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:12:02.22#ibcon#*before write, iclass 29, count 0 2006.257.11:12:02.22#ibcon#enter sib2, iclass 29, count 0 2006.257.11:12:02.22#ibcon#flushed, iclass 29, count 0 2006.257.11:12:02.22#ibcon#about to write, iclass 29, count 0 2006.257.11:12:02.22#ibcon#wrote, iclass 29, count 0 2006.257.11:12:02.22#ibcon#about to read 3, iclass 29, count 0 2006.257.11:12:02.26#ibcon#read 3, iclass 29, count 0 2006.257.11:12:02.26#ibcon#about to read 4, iclass 29, count 0 2006.257.11:12:02.26#ibcon#read 4, iclass 29, count 0 2006.257.11:12:02.26#ibcon#about to read 5, iclass 29, count 0 2006.257.11:12:02.26#ibcon#read 5, iclass 29, count 0 2006.257.11:12:02.26#ibcon#about to read 6, iclass 29, count 0 2006.257.11:12:02.26#ibcon#read 6, iclass 29, count 0 2006.257.11:12:02.26#ibcon#end of sib2, iclass 29, count 0 2006.257.11:12:02.26#ibcon#*after write, iclass 29, count 0 2006.257.11:12:02.26#ibcon#*before return 0, iclass 29, count 0 2006.257.11:12:02.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:12:02.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:12:02.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:12:02.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:12:02.26$vck44/vb=5,4 2006.257.11:12:02.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.11:12:02.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.11:12:02.26#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:02.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:12:02.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:12:02.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:12:02.32#ibcon#enter wrdev, iclass 31, count 2 2006.257.11:12:02.32#ibcon#first serial, iclass 31, count 2 2006.257.11:12:02.32#ibcon#enter sib2, iclass 31, count 2 2006.257.11:12:02.32#ibcon#flushed, iclass 31, count 2 2006.257.11:12:02.32#ibcon#about to write, iclass 31, count 2 2006.257.11:12:02.32#ibcon#wrote, iclass 31, count 2 2006.257.11:12:02.32#ibcon#about to read 3, iclass 31, count 2 2006.257.11:12:02.34#ibcon#read 3, iclass 31, count 2 2006.257.11:12:02.34#ibcon#about to read 4, iclass 31, count 2 2006.257.11:12:02.34#ibcon#read 4, iclass 31, count 2 2006.257.11:12:02.34#ibcon#about to read 5, iclass 31, count 2 2006.257.11:12:02.34#ibcon#read 5, iclass 31, count 2 2006.257.11:12:02.34#ibcon#about to read 6, iclass 31, count 2 2006.257.11:12:02.34#ibcon#read 6, iclass 31, count 2 2006.257.11:12:02.34#ibcon#end of sib2, iclass 31, count 2 2006.257.11:12:02.34#ibcon#*mode == 0, iclass 31, count 2 2006.257.11:12:02.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.11:12:02.34#ibcon#[27=AT05-04\r\n] 2006.257.11:12:02.34#ibcon#*before write, iclass 31, count 2 2006.257.11:12:02.34#ibcon#enter sib2, iclass 31, count 2 2006.257.11:12:02.34#ibcon#flushed, iclass 31, count 2 2006.257.11:12:02.34#ibcon#about to write, iclass 31, count 2 2006.257.11:12:02.34#ibcon#wrote, iclass 31, count 2 2006.257.11:12:02.34#ibcon#about to read 3, iclass 31, count 2 2006.257.11:12:02.37#ibcon#read 3, iclass 31, count 2 2006.257.11:12:02.37#ibcon#about to read 4, iclass 31, count 2 2006.257.11:12:02.37#ibcon#read 4, iclass 31, count 2 2006.257.11:12:02.37#ibcon#about to read 5, iclass 31, count 2 2006.257.11:12:02.37#ibcon#read 5, iclass 31, count 2 2006.257.11:12:02.37#ibcon#about to read 6, iclass 31, count 2 2006.257.11:12:02.37#ibcon#read 6, iclass 31, count 2 2006.257.11:12:02.37#ibcon#end of sib2, iclass 31, count 2 2006.257.11:12:02.37#ibcon#*after write, iclass 31, count 2 2006.257.11:12:02.37#ibcon#*before return 0, iclass 31, count 2 2006.257.11:12:02.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:12:02.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:12:02.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.11:12:02.37#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:02.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:12:02.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:12:02.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:12:02.49#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:12:02.49#ibcon#first serial, iclass 31, count 0 2006.257.11:12:02.49#ibcon#enter sib2, iclass 31, count 0 2006.257.11:12:02.49#ibcon#flushed, iclass 31, count 0 2006.257.11:12:02.49#ibcon#about to write, iclass 31, count 0 2006.257.11:12:02.49#ibcon#wrote, iclass 31, count 0 2006.257.11:12:02.49#ibcon#about to read 3, iclass 31, count 0 2006.257.11:12:02.51#ibcon#read 3, iclass 31, count 0 2006.257.11:12:02.51#ibcon#about to read 4, iclass 31, count 0 2006.257.11:12:02.51#ibcon#read 4, iclass 31, count 0 2006.257.11:12:02.51#ibcon#about to read 5, iclass 31, count 0 2006.257.11:12:02.51#ibcon#read 5, iclass 31, count 0 2006.257.11:12:02.51#ibcon#about to read 6, iclass 31, count 0 2006.257.11:12:02.51#ibcon#read 6, iclass 31, count 0 2006.257.11:12:02.51#ibcon#end of sib2, iclass 31, count 0 2006.257.11:12:02.51#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:12:02.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:12:02.51#ibcon#[27=USB\r\n] 2006.257.11:12:02.51#ibcon#*before write, iclass 31, count 0 2006.257.11:12:02.51#ibcon#enter sib2, iclass 31, count 0 2006.257.11:12:02.51#ibcon#flushed, iclass 31, count 0 2006.257.11:12:02.51#ibcon#about to write, iclass 31, count 0 2006.257.11:12:02.51#ibcon#wrote, iclass 31, count 0 2006.257.11:12:02.51#ibcon#about to read 3, iclass 31, count 0 2006.257.11:12:02.54#ibcon#read 3, iclass 31, count 0 2006.257.11:12:02.54#ibcon#about to read 4, iclass 31, count 0 2006.257.11:12:02.54#ibcon#read 4, iclass 31, count 0 2006.257.11:12:02.54#ibcon#about to read 5, iclass 31, count 0 2006.257.11:12:02.54#ibcon#read 5, iclass 31, count 0 2006.257.11:12:02.54#ibcon#about to read 6, iclass 31, count 0 2006.257.11:12:02.54#ibcon#read 6, iclass 31, count 0 2006.257.11:12:02.54#ibcon#end of sib2, iclass 31, count 0 2006.257.11:12:02.54#ibcon#*after write, iclass 31, count 0 2006.257.11:12:02.54#ibcon#*before return 0, iclass 31, count 0 2006.257.11:12:02.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:12:02.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:12:02.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:12:02.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:12:02.54$vck44/vblo=6,719.99 2006.257.11:12:02.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.11:12:02.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.11:12:02.54#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:02.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:12:02.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:12:02.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:12:02.54#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:12:02.54#ibcon#first serial, iclass 33, count 0 2006.257.11:12:02.54#ibcon#enter sib2, iclass 33, count 0 2006.257.11:12:02.54#ibcon#flushed, iclass 33, count 0 2006.257.11:12:02.54#ibcon#about to write, iclass 33, count 0 2006.257.11:12:02.54#ibcon#wrote, iclass 33, count 0 2006.257.11:12:02.54#ibcon#about to read 3, iclass 33, count 0 2006.257.11:12:02.56#ibcon#read 3, iclass 33, count 0 2006.257.11:12:02.56#ibcon#about to read 4, iclass 33, count 0 2006.257.11:12:02.56#ibcon#read 4, iclass 33, count 0 2006.257.11:12:02.56#ibcon#about to read 5, iclass 33, count 0 2006.257.11:12:02.56#ibcon#read 5, iclass 33, count 0 2006.257.11:12:02.56#ibcon#about to read 6, iclass 33, count 0 2006.257.11:12:02.56#ibcon#read 6, iclass 33, count 0 2006.257.11:12:02.56#ibcon#end of sib2, iclass 33, count 0 2006.257.11:12:02.56#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:12:02.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:12:02.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:12:02.56#ibcon#*before write, iclass 33, count 0 2006.257.11:12:02.56#ibcon#enter sib2, iclass 33, count 0 2006.257.11:12:02.56#ibcon#flushed, iclass 33, count 0 2006.257.11:12:02.56#ibcon#about to write, iclass 33, count 0 2006.257.11:12:02.56#ibcon#wrote, iclass 33, count 0 2006.257.11:12:02.56#ibcon#about to read 3, iclass 33, count 0 2006.257.11:12:02.60#ibcon#read 3, iclass 33, count 0 2006.257.11:12:02.60#ibcon#about to read 4, iclass 33, count 0 2006.257.11:12:02.60#ibcon#read 4, iclass 33, count 0 2006.257.11:12:02.60#ibcon#about to read 5, iclass 33, count 0 2006.257.11:12:02.60#ibcon#read 5, iclass 33, count 0 2006.257.11:12:02.60#ibcon#about to read 6, iclass 33, count 0 2006.257.11:12:02.60#ibcon#read 6, iclass 33, count 0 2006.257.11:12:02.60#ibcon#end of sib2, iclass 33, count 0 2006.257.11:12:02.60#ibcon#*after write, iclass 33, count 0 2006.257.11:12:02.60#ibcon#*before return 0, iclass 33, count 0 2006.257.11:12:02.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:12:02.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:12:02.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:12:02.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:12:02.60$vck44/vb=6,4 2006.257.11:12:02.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.11:12:02.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.11:12:02.60#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:02.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:02.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:02.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:02.66#ibcon#enter wrdev, iclass 35, count 2 2006.257.11:12:02.66#ibcon#first serial, iclass 35, count 2 2006.257.11:12:02.66#ibcon#enter sib2, iclass 35, count 2 2006.257.11:12:02.66#ibcon#flushed, iclass 35, count 2 2006.257.11:12:02.66#ibcon#about to write, iclass 35, count 2 2006.257.11:12:02.66#ibcon#wrote, iclass 35, count 2 2006.257.11:12:02.66#ibcon#about to read 3, iclass 35, count 2 2006.257.11:12:02.68#ibcon#read 3, iclass 35, count 2 2006.257.11:12:02.68#ibcon#about to read 4, iclass 35, count 2 2006.257.11:12:02.68#ibcon#read 4, iclass 35, count 2 2006.257.11:12:02.68#ibcon#about to read 5, iclass 35, count 2 2006.257.11:12:02.68#ibcon#read 5, iclass 35, count 2 2006.257.11:12:02.68#ibcon#about to read 6, iclass 35, count 2 2006.257.11:12:02.68#ibcon#read 6, iclass 35, count 2 2006.257.11:12:02.68#ibcon#end of sib2, iclass 35, count 2 2006.257.11:12:02.68#ibcon#*mode == 0, iclass 35, count 2 2006.257.11:12:02.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.11:12:02.68#ibcon#[27=AT06-04\r\n] 2006.257.11:12:02.68#ibcon#*before write, iclass 35, count 2 2006.257.11:12:02.68#ibcon#enter sib2, iclass 35, count 2 2006.257.11:12:02.68#ibcon#flushed, iclass 35, count 2 2006.257.11:12:02.68#ibcon#about to write, iclass 35, count 2 2006.257.11:12:02.68#ibcon#wrote, iclass 35, count 2 2006.257.11:12:02.68#ibcon#about to read 3, iclass 35, count 2 2006.257.11:12:02.71#ibcon#read 3, iclass 35, count 2 2006.257.11:12:02.71#ibcon#about to read 4, iclass 35, count 2 2006.257.11:12:02.71#ibcon#read 4, iclass 35, count 2 2006.257.11:12:02.71#ibcon#about to read 5, iclass 35, count 2 2006.257.11:12:02.71#ibcon#read 5, iclass 35, count 2 2006.257.11:12:02.71#ibcon#about to read 6, iclass 35, count 2 2006.257.11:12:02.71#ibcon#read 6, iclass 35, count 2 2006.257.11:12:02.71#ibcon#end of sib2, iclass 35, count 2 2006.257.11:12:02.71#ibcon#*after write, iclass 35, count 2 2006.257.11:12:02.71#ibcon#*before return 0, iclass 35, count 2 2006.257.11:12:02.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:02.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:12:02.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.11:12:02.71#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:02.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:02.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:02.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:02.83#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:12:02.83#ibcon#first serial, iclass 35, count 0 2006.257.11:12:02.83#ibcon#enter sib2, iclass 35, count 0 2006.257.11:12:02.83#ibcon#flushed, iclass 35, count 0 2006.257.11:12:02.83#ibcon#about to write, iclass 35, count 0 2006.257.11:12:02.83#ibcon#wrote, iclass 35, count 0 2006.257.11:12:02.83#ibcon#about to read 3, iclass 35, count 0 2006.257.11:12:02.85#ibcon#read 3, iclass 35, count 0 2006.257.11:12:02.85#ibcon#about to read 4, iclass 35, count 0 2006.257.11:12:02.85#ibcon#read 4, iclass 35, count 0 2006.257.11:12:02.85#ibcon#about to read 5, iclass 35, count 0 2006.257.11:12:02.85#ibcon#read 5, iclass 35, count 0 2006.257.11:12:02.85#ibcon#about to read 6, iclass 35, count 0 2006.257.11:12:02.85#ibcon#read 6, iclass 35, count 0 2006.257.11:12:02.85#ibcon#end of sib2, iclass 35, count 0 2006.257.11:12:02.85#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:12:02.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:12:02.85#ibcon#[27=USB\r\n] 2006.257.11:12:02.85#ibcon#*before write, iclass 35, count 0 2006.257.11:12:02.85#ibcon#enter sib2, iclass 35, count 0 2006.257.11:12:02.85#ibcon#flushed, iclass 35, count 0 2006.257.11:12:02.85#ibcon#about to write, iclass 35, count 0 2006.257.11:12:02.85#ibcon#wrote, iclass 35, count 0 2006.257.11:12:02.85#ibcon#about to read 3, iclass 35, count 0 2006.257.11:12:02.88#ibcon#read 3, iclass 35, count 0 2006.257.11:12:02.88#ibcon#about to read 4, iclass 35, count 0 2006.257.11:12:02.88#ibcon#read 4, iclass 35, count 0 2006.257.11:12:02.88#ibcon#about to read 5, iclass 35, count 0 2006.257.11:12:02.88#ibcon#read 5, iclass 35, count 0 2006.257.11:12:02.88#ibcon#about to read 6, iclass 35, count 0 2006.257.11:12:02.88#ibcon#read 6, iclass 35, count 0 2006.257.11:12:02.88#ibcon#end of sib2, iclass 35, count 0 2006.257.11:12:02.88#ibcon#*after write, iclass 35, count 0 2006.257.11:12:02.88#ibcon#*before return 0, iclass 35, count 0 2006.257.11:12:02.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:02.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:12:02.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:12:02.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:12:02.88$vck44/vblo=7,734.99 2006.257.11:12:02.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.11:12:02.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.11:12:02.88#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:02.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:02.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:02.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:02.88#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:12:02.88#ibcon#first serial, iclass 37, count 0 2006.257.11:12:02.88#ibcon#enter sib2, iclass 37, count 0 2006.257.11:12:02.88#ibcon#flushed, iclass 37, count 0 2006.257.11:12:02.88#ibcon#about to write, iclass 37, count 0 2006.257.11:12:02.88#ibcon#wrote, iclass 37, count 0 2006.257.11:12:02.88#ibcon#about to read 3, iclass 37, count 0 2006.257.11:12:02.90#ibcon#read 3, iclass 37, count 0 2006.257.11:12:02.90#ibcon#about to read 4, iclass 37, count 0 2006.257.11:12:02.90#ibcon#read 4, iclass 37, count 0 2006.257.11:12:02.90#ibcon#about to read 5, iclass 37, count 0 2006.257.11:12:02.90#ibcon#read 5, iclass 37, count 0 2006.257.11:12:02.90#ibcon#about to read 6, iclass 37, count 0 2006.257.11:12:02.90#ibcon#read 6, iclass 37, count 0 2006.257.11:12:02.90#ibcon#end of sib2, iclass 37, count 0 2006.257.11:12:02.90#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:12:02.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:12:02.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:12:02.90#ibcon#*before write, iclass 37, count 0 2006.257.11:12:02.90#ibcon#enter sib2, iclass 37, count 0 2006.257.11:12:02.90#ibcon#flushed, iclass 37, count 0 2006.257.11:12:02.90#ibcon#about to write, iclass 37, count 0 2006.257.11:12:02.90#ibcon#wrote, iclass 37, count 0 2006.257.11:12:02.90#ibcon#about to read 3, iclass 37, count 0 2006.257.11:12:02.94#ibcon#read 3, iclass 37, count 0 2006.257.11:12:02.94#ibcon#about to read 4, iclass 37, count 0 2006.257.11:12:02.94#ibcon#read 4, iclass 37, count 0 2006.257.11:12:02.94#ibcon#about to read 5, iclass 37, count 0 2006.257.11:12:02.94#ibcon#read 5, iclass 37, count 0 2006.257.11:12:02.94#ibcon#about to read 6, iclass 37, count 0 2006.257.11:12:02.94#ibcon#read 6, iclass 37, count 0 2006.257.11:12:02.94#ibcon#end of sib2, iclass 37, count 0 2006.257.11:12:02.94#ibcon#*after write, iclass 37, count 0 2006.257.11:12:02.94#ibcon#*before return 0, iclass 37, count 0 2006.257.11:12:02.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:02.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:12:02.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:12:02.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:12:02.94$vck44/vb=7,4 2006.257.11:12:02.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.11:12:02.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.11:12:02.94#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:02.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:03.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:03.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:03.00#ibcon#enter wrdev, iclass 39, count 2 2006.257.11:12:03.00#ibcon#first serial, iclass 39, count 2 2006.257.11:12:03.00#ibcon#enter sib2, iclass 39, count 2 2006.257.11:12:03.00#ibcon#flushed, iclass 39, count 2 2006.257.11:12:03.00#ibcon#about to write, iclass 39, count 2 2006.257.11:12:03.00#ibcon#wrote, iclass 39, count 2 2006.257.11:12:03.00#ibcon#about to read 3, iclass 39, count 2 2006.257.11:12:03.02#ibcon#read 3, iclass 39, count 2 2006.257.11:12:03.02#ibcon#about to read 4, iclass 39, count 2 2006.257.11:12:03.02#ibcon#read 4, iclass 39, count 2 2006.257.11:12:03.02#ibcon#about to read 5, iclass 39, count 2 2006.257.11:12:03.02#ibcon#read 5, iclass 39, count 2 2006.257.11:12:03.02#ibcon#about to read 6, iclass 39, count 2 2006.257.11:12:03.02#ibcon#read 6, iclass 39, count 2 2006.257.11:12:03.02#ibcon#end of sib2, iclass 39, count 2 2006.257.11:12:03.02#ibcon#*mode == 0, iclass 39, count 2 2006.257.11:12:03.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.11:12:03.02#ibcon#[27=AT07-04\r\n] 2006.257.11:12:03.02#ibcon#*before write, iclass 39, count 2 2006.257.11:12:03.02#ibcon#enter sib2, iclass 39, count 2 2006.257.11:12:03.02#ibcon#flushed, iclass 39, count 2 2006.257.11:12:03.02#ibcon#about to write, iclass 39, count 2 2006.257.11:12:03.02#ibcon#wrote, iclass 39, count 2 2006.257.11:12:03.02#ibcon#about to read 3, iclass 39, count 2 2006.257.11:12:03.05#ibcon#read 3, iclass 39, count 2 2006.257.11:12:03.05#ibcon#about to read 4, iclass 39, count 2 2006.257.11:12:03.05#ibcon#read 4, iclass 39, count 2 2006.257.11:12:03.05#ibcon#about to read 5, iclass 39, count 2 2006.257.11:12:03.05#ibcon#read 5, iclass 39, count 2 2006.257.11:12:03.05#ibcon#about to read 6, iclass 39, count 2 2006.257.11:12:03.05#ibcon#read 6, iclass 39, count 2 2006.257.11:12:03.05#ibcon#end of sib2, iclass 39, count 2 2006.257.11:12:03.05#ibcon#*after write, iclass 39, count 2 2006.257.11:12:03.05#ibcon#*before return 0, iclass 39, count 2 2006.257.11:12:03.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:03.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:12:03.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.11:12:03.05#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:03.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:03.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:03.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:03.17#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:12:03.17#ibcon#first serial, iclass 39, count 0 2006.257.11:12:03.17#ibcon#enter sib2, iclass 39, count 0 2006.257.11:12:03.17#ibcon#flushed, iclass 39, count 0 2006.257.11:12:03.17#ibcon#about to write, iclass 39, count 0 2006.257.11:12:03.17#ibcon#wrote, iclass 39, count 0 2006.257.11:12:03.17#ibcon#about to read 3, iclass 39, count 0 2006.257.11:12:03.19#ibcon#read 3, iclass 39, count 0 2006.257.11:12:03.19#ibcon#about to read 4, iclass 39, count 0 2006.257.11:12:03.19#ibcon#read 4, iclass 39, count 0 2006.257.11:12:03.19#ibcon#about to read 5, iclass 39, count 0 2006.257.11:12:03.19#ibcon#read 5, iclass 39, count 0 2006.257.11:12:03.19#ibcon#about to read 6, iclass 39, count 0 2006.257.11:12:03.19#ibcon#read 6, iclass 39, count 0 2006.257.11:12:03.19#ibcon#end of sib2, iclass 39, count 0 2006.257.11:12:03.19#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:12:03.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:12:03.19#ibcon#[27=USB\r\n] 2006.257.11:12:03.19#ibcon#*before write, iclass 39, count 0 2006.257.11:12:03.19#ibcon#enter sib2, iclass 39, count 0 2006.257.11:12:03.19#ibcon#flushed, iclass 39, count 0 2006.257.11:12:03.19#ibcon#about to write, iclass 39, count 0 2006.257.11:12:03.19#ibcon#wrote, iclass 39, count 0 2006.257.11:12:03.19#ibcon#about to read 3, iclass 39, count 0 2006.257.11:12:03.22#ibcon#read 3, iclass 39, count 0 2006.257.11:12:03.22#ibcon#about to read 4, iclass 39, count 0 2006.257.11:12:03.22#ibcon#read 4, iclass 39, count 0 2006.257.11:12:03.22#ibcon#about to read 5, iclass 39, count 0 2006.257.11:12:03.22#ibcon#read 5, iclass 39, count 0 2006.257.11:12:03.22#ibcon#about to read 6, iclass 39, count 0 2006.257.11:12:03.22#ibcon#read 6, iclass 39, count 0 2006.257.11:12:03.22#ibcon#end of sib2, iclass 39, count 0 2006.257.11:12:03.22#ibcon#*after write, iclass 39, count 0 2006.257.11:12:03.22#ibcon#*before return 0, iclass 39, count 0 2006.257.11:12:03.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:03.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:12:03.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:12:03.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:12:03.22$vck44/vblo=8,744.99 2006.257.11:12:03.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.11:12:03.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.11:12:03.22#ibcon#ireg 17 cls_cnt 0 2006.257.11:12:03.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:03.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:03.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:03.22#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:12:03.22#ibcon#first serial, iclass 3, count 0 2006.257.11:12:03.22#ibcon#enter sib2, iclass 3, count 0 2006.257.11:12:03.22#ibcon#flushed, iclass 3, count 0 2006.257.11:12:03.22#ibcon#about to write, iclass 3, count 0 2006.257.11:12:03.22#ibcon#wrote, iclass 3, count 0 2006.257.11:12:03.22#ibcon#about to read 3, iclass 3, count 0 2006.257.11:12:03.24#ibcon#read 3, iclass 3, count 0 2006.257.11:12:03.24#ibcon#about to read 4, iclass 3, count 0 2006.257.11:12:03.24#ibcon#read 4, iclass 3, count 0 2006.257.11:12:03.24#ibcon#about to read 5, iclass 3, count 0 2006.257.11:12:03.24#ibcon#read 5, iclass 3, count 0 2006.257.11:12:03.24#ibcon#about to read 6, iclass 3, count 0 2006.257.11:12:03.24#ibcon#read 6, iclass 3, count 0 2006.257.11:12:03.24#ibcon#end of sib2, iclass 3, count 0 2006.257.11:12:03.24#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:12:03.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:12:03.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:12:03.24#ibcon#*before write, iclass 3, count 0 2006.257.11:12:03.24#ibcon#enter sib2, iclass 3, count 0 2006.257.11:12:03.24#ibcon#flushed, iclass 3, count 0 2006.257.11:12:03.24#ibcon#about to write, iclass 3, count 0 2006.257.11:12:03.24#ibcon#wrote, iclass 3, count 0 2006.257.11:12:03.24#ibcon#about to read 3, iclass 3, count 0 2006.257.11:12:03.28#ibcon#read 3, iclass 3, count 0 2006.257.11:12:03.28#ibcon#about to read 4, iclass 3, count 0 2006.257.11:12:03.28#ibcon#read 4, iclass 3, count 0 2006.257.11:12:03.28#ibcon#about to read 5, iclass 3, count 0 2006.257.11:12:03.28#ibcon#read 5, iclass 3, count 0 2006.257.11:12:03.28#ibcon#about to read 6, iclass 3, count 0 2006.257.11:12:03.28#ibcon#read 6, iclass 3, count 0 2006.257.11:12:03.28#ibcon#end of sib2, iclass 3, count 0 2006.257.11:12:03.28#ibcon#*after write, iclass 3, count 0 2006.257.11:12:03.28#ibcon#*before return 0, iclass 3, count 0 2006.257.11:12:03.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:03.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:12:03.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:12:03.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:12:03.28$vck44/vb=8,4 2006.257.11:12:03.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.11:12:03.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.11:12:03.28#ibcon#ireg 11 cls_cnt 2 2006.257.11:12:03.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:03.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:03.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:03.34#ibcon#enter wrdev, iclass 5, count 2 2006.257.11:12:03.34#ibcon#first serial, iclass 5, count 2 2006.257.11:12:03.34#ibcon#enter sib2, iclass 5, count 2 2006.257.11:12:03.34#ibcon#flushed, iclass 5, count 2 2006.257.11:12:03.34#ibcon#about to write, iclass 5, count 2 2006.257.11:12:03.34#ibcon#wrote, iclass 5, count 2 2006.257.11:12:03.34#ibcon#about to read 3, iclass 5, count 2 2006.257.11:12:03.36#ibcon#read 3, iclass 5, count 2 2006.257.11:12:03.36#ibcon#about to read 4, iclass 5, count 2 2006.257.11:12:03.36#ibcon#read 4, iclass 5, count 2 2006.257.11:12:03.36#ibcon#about to read 5, iclass 5, count 2 2006.257.11:12:03.36#ibcon#read 5, iclass 5, count 2 2006.257.11:12:03.36#ibcon#about to read 6, iclass 5, count 2 2006.257.11:12:03.36#ibcon#read 6, iclass 5, count 2 2006.257.11:12:03.36#ibcon#end of sib2, iclass 5, count 2 2006.257.11:12:03.36#ibcon#*mode == 0, iclass 5, count 2 2006.257.11:12:03.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.11:12:03.36#ibcon#[27=AT08-04\r\n] 2006.257.11:12:03.36#ibcon#*before write, iclass 5, count 2 2006.257.11:12:03.36#ibcon#enter sib2, iclass 5, count 2 2006.257.11:12:03.36#ibcon#flushed, iclass 5, count 2 2006.257.11:12:03.36#ibcon#about to write, iclass 5, count 2 2006.257.11:12:03.36#ibcon#wrote, iclass 5, count 2 2006.257.11:12:03.36#ibcon#about to read 3, iclass 5, count 2 2006.257.11:12:03.39#ibcon#read 3, iclass 5, count 2 2006.257.11:12:03.39#ibcon#about to read 4, iclass 5, count 2 2006.257.11:12:03.39#ibcon#read 4, iclass 5, count 2 2006.257.11:12:03.39#ibcon#about to read 5, iclass 5, count 2 2006.257.11:12:03.39#ibcon#read 5, iclass 5, count 2 2006.257.11:12:03.39#ibcon#about to read 6, iclass 5, count 2 2006.257.11:12:03.39#ibcon#read 6, iclass 5, count 2 2006.257.11:12:03.39#ibcon#end of sib2, iclass 5, count 2 2006.257.11:12:03.39#ibcon#*after write, iclass 5, count 2 2006.257.11:12:03.39#ibcon#*before return 0, iclass 5, count 2 2006.257.11:12:03.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:03.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:12:03.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.11:12:03.39#ibcon#ireg 7 cls_cnt 0 2006.257.11:12:03.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:03.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:03.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:03.51#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:12:03.51#ibcon#first serial, iclass 5, count 0 2006.257.11:12:03.51#ibcon#enter sib2, iclass 5, count 0 2006.257.11:12:03.51#ibcon#flushed, iclass 5, count 0 2006.257.11:12:03.51#ibcon#about to write, iclass 5, count 0 2006.257.11:12:03.51#ibcon#wrote, iclass 5, count 0 2006.257.11:12:03.51#ibcon#about to read 3, iclass 5, count 0 2006.257.11:12:03.53#ibcon#read 3, iclass 5, count 0 2006.257.11:12:03.53#ibcon#about to read 4, iclass 5, count 0 2006.257.11:12:03.53#ibcon#read 4, iclass 5, count 0 2006.257.11:12:03.53#ibcon#about to read 5, iclass 5, count 0 2006.257.11:12:03.53#ibcon#read 5, iclass 5, count 0 2006.257.11:12:03.53#ibcon#about to read 6, iclass 5, count 0 2006.257.11:12:03.53#ibcon#read 6, iclass 5, count 0 2006.257.11:12:03.53#ibcon#end of sib2, iclass 5, count 0 2006.257.11:12:03.53#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:12:03.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:12:03.53#ibcon#[27=USB\r\n] 2006.257.11:12:03.53#ibcon#*before write, iclass 5, count 0 2006.257.11:12:03.53#ibcon#enter sib2, iclass 5, count 0 2006.257.11:12:03.53#ibcon#flushed, iclass 5, count 0 2006.257.11:12:03.53#ibcon#about to write, iclass 5, count 0 2006.257.11:12:03.53#ibcon#wrote, iclass 5, count 0 2006.257.11:12:03.53#ibcon#about to read 3, iclass 5, count 0 2006.257.11:12:03.56#ibcon#read 3, iclass 5, count 0 2006.257.11:12:03.56#ibcon#about to read 4, iclass 5, count 0 2006.257.11:12:03.56#ibcon#read 4, iclass 5, count 0 2006.257.11:12:03.56#ibcon#about to read 5, iclass 5, count 0 2006.257.11:12:03.56#ibcon#read 5, iclass 5, count 0 2006.257.11:12:03.56#ibcon#about to read 6, iclass 5, count 0 2006.257.11:12:03.56#ibcon#read 6, iclass 5, count 0 2006.257.11:12:03.56#ibcon#end of sib2, iclass 5, count 0 2006.257.11:12:03.56#ibcon#*after write, iclass 5, count 0 2006.257.11:12:03.56#ibcon#*before return 0, iclass 5, count 0 2006.257.11:12:03.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:03.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:12:03.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:12:03.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:12:03.56$vck44/vabw=wide 2006.257.11:12:03.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.11:12:03.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.11:12:03.56#ibcon#ireg 8 cls_cnt 0 2006.257.11:12:03.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:03.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:03.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:03.56#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:12:03.56#ibcon#first serial, iclass 7, count 0 2006.257.11:12:03.56#ibcon#enter sib2, iclass 7, count 0 2006.257.11:12:03.56#ibcon#flushed, iclass 7, count 0 2006.257.11:12:03.56#ibcon#about to write, iclass 7, count 0 2006.257.11:12:03.56#ibcon#wrote, iclass 7, count 0 2006.257.11:12:03.56#ibcon#about to read 3, iclass 7, count 0 2006.257.11:12:03.58#ibcon#read 3, iclass 7, count 0 2006.257.11:12:03.58#ibcon#about to read 4, iclass 7, count 0 2006.257.11:12:03.58#ibcon#read 4, iclass 7, count 0 2006.257.11:12:03.58#ibcon#about to read 5, iclass 7, count 0 2006.257.11:12:03.58#ibcon#read 5, iclass 7, count 0 2006.257.11:12:03.58#ibcon#about to read 6, iclass 7, count 0 2006.257.11:12:03.58#ibcon#read 6, iclass 7, count 0 2006.257.11:12:03.58#ibcon#end of sib2, iclass 7, count 0 2006.257.11:12:03.58#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:12:03.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:12:03.58#ibcon#[25=BW32\r\n] 2006.257.11:12:03.58#ibcon#*before write, iclass 7, count 0 2006.257.11:12:03.58#ibcon#enter sib2, iclass 7, count 0 2006.257.11:12:03.58#ibcon#flushed, iclass 7, count 0 2006.257.11:12:03.58#ibcon#about to write, iclass 7, count 0 2006.257.11:12:03.58#ibcon#wrote, iclass 7, count 0 2006.257.11:12:03.58#ibcon#about to read 3, iclass 7, count 0 2006.257.11:12:03.61#ibcon#read 3, iclass 7, count 0 2006.257.11:12:03.61#ibcon#about to read 4, iclass 7, count 0 2006.257.11:12:03.61#ibcon#read 4, iclass 7, count 0 2006.257.11:12:03.61#ibcon#about to read 5, iclass 7, count 0 2006.257.11:12:03.61#ibcon#read 5, iclass 7, count 0 2006.257.11:12:03.61#ibcon#about to read 6, iclass 7, count 0 2006.257.11:12:03.61#ibcon#read 6, iclass 7, count 0 2006.257.11:12:03.61#ibcon#end of sib2, iclass 7, count 0 2006.257.11:12:03.61#ibcon#*after write, iclass 7, count 0 2006.257.11:12:03.61#ibcon#*before return 0, iclass 7, count 0 2006.257.11:12:03.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:03.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:12:03.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:12:03.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:12:03.61$vck44/vbbw=wide 2006.257.11:12:03.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.11:12:03.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.11:12:03.61#ibcon#ireg 8 cls_cnt 0 2006.257.11:12:03.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:12:03.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:12:03.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:12:03.68#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:12:03.68#ibcon#first serial, iclass 11, count 0 2006.257.11:12:03.68#ibcon#enter sib2, iclass 11, count 0 2006.257.11:12:03.68#ibcon#flushed, iclass 11, count 0 2006.257.11:12:03.68#ibcon#about to write, iclass 11, count 0 2006.257.11:12:03.68#ibcon#wrote, iclass 11, count 0 2006.257.11:12:03.68#ibcon#about to read 3, iclass 11, count 0 2006.257.11:12:03.70#ibcon#read 3, iclass 11, count 0 2006.257.11:12:03.70#ibcon#about to read 4, iclass 11, count 0 2006.257.11:12:03.70#ibcon#read 4, iclass 11, count 0 2006.257.11:12:03.70#ibcon#about to read 5, iclass 11, count 0 2006.257.11:12:03.70#ibcon#read 5, iclass 11, count 0 2006.257.11:12:03.70#ibcon#about to read 6, iclass 11, count 0 2006.257.11:12:03.70#ibcon#read 6, iclass 11, count 0 2006.257.11:12:03.70#ibcon#end of sib2, iclass 11, count 0 2006.257.11:12:03.70#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:12:03.70#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:12:03.70#ibcon#[27=BW32\r\n] 2006.257.11:12:03.70#ibcon#*before write, iclass 11, count 0 2006.257.11:12:03.70#ibcon#enter sib2, iclass 11, count 0 2006.257.11:12:03.70#ibcon#flushed, iclass 11, count 0 2006.257.11:12:03.70#ibcon#about to write, iclass 11, count 0 2006.257.11:12:03.70#ibcon#wrote, iclass 11, count 0 2006.257.11:12:03.70#ibcon#about to read 3, iclass 11, count 0 2006.257.11:12:03.73#ibcon#read 3, iclass 11, count 0 2006.257.11:12:03.73#ibcon#about to read 4, iclass 11, count 0 2006.257.11:12:03.73#ibcon#read 4, iclass 11, count 0 2006.257.11:12:03.73#ibcon#about to read 5, iclass 11, count 0 2006.257.11:12:03.73#ibcon#read 5, iclass 11, count 0 2006.257.11:12:03.73#ibcon#about to read 6, iclass 11, count 0 2006.257.11:12:03.73#ibcon#read 6, iclass 11, count 0 2006.257.11:12:03.73#ibcon#end of sib2, iclass 11, count 0 2006.257.11:12:03.73#ibcon#*after write, iclass 11, count 0 2006.257.11:12:03.73#ibcon#*before return 0, iclass 11, count 0 2006.257.11:12:03.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:12:03.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:12:03.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:12:03.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:12:03.73$setupk4/ifdk4 2006.257.11:12:03.73$ifdk4/lo= 2006.257.11:12:03.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:12:03.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:12:03.73$ifdk4/patch= 2006.257.11:12:03.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:12:03.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:12:03.73$setupk4/!*+20s 2006.257.11:12:12.18#abcon#<5=/15 1.6 3.6 18.46 961013.9\r\n> 2006.257.11:12:12.20#abcon#{5=INTERFACE CLEAR} 2006.257.11:12:12.26#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:12:18.24$setupk4/"tpicd 2006.257.11:12:18.24$setupk4/echo=off 2006.257.11:12:18.24$setupk4/xlog=off 2006.257.11:12:18.24:!2006.257.11:15:16 2006.257.11:12:31.14#trakl#Source acquired 2006.257.11:12:32.14#flagr#flagr/antenna,acquired 2006.257.11:15:16.00:preob 2006.257.11:15:16.13/onsource/TRACKING 2006.257.11:15:16.13:!2006.257.11:15:26 2006.257.11:15:26.00:"tape 2006.257.11:15:26.00:"st=record 2006.257.11:15:26.00:data_valid=on 2006.257.11:15:26.00:midob 2006.257.11:15:26.14/onsource/TRACKING 2006.257.11:15:26.14/wx/18.40,1013.8,96 2006.257.11:15:26.19/cable/+6.4764E-03 2006.257.11:15:27.28/va/01,08,usb,yes,31,33 2006.257.11:15:27.28/va/02,07,usb,yes,33,34 2006.257.11:15:27.28/va/03,08,usb,yes,30,31 2006.257.11:15:27.28/va/04,07,usb,yes,34,36 2006.257.11:15:27.28/va/05,04,usb,yes,31,31 2006.257.11:15:27.28/va/06,04,usb,yes,34,34 2006.257.11:15:27.28/va/07,04,usb,yes,35,35 2006.257.11:15:27.28/va/08,04,usb,yes,29,36 2006.257.11:15:27.51/valo/01,524.99,yes,locked 2006.257.11:15:27.51/valo/02,534.99,yes,locked 2006.257.11:15:27.51/valo/03,564.99,yes,locked 2006.257.11:15:27.51/valo/04,624.99,yes,locked 2006.257.11:15:27.51/valo/05,734.99,yes,locked 2006.257.11:15:27.51/valo/06,814.99,yes,locked 2006.257.11:15:27.51/valo/07,864.99,yes,locked 2006.257.11:15:27.51/valo/08,884.99,yes,locked 2006.257.11:15:28.60/vb/01,04,usb,yes,31,28 2006.257.11:15:28.60/vb/02,05,usb,yes,29,29 2006.257.11:15:28.60/vb/03,04,usb,yes,30,33 2006.257.11:15:28.60/vb/04,05,usb,yes,30,29 2006.257.11:15:28.60/vb/05,04,usb,yes,27,29 2006.257.11:15:28.60/vb/06,04,usb,yes,31,27 2006.257.11:15:28.60/vb/07,04,usb,yes,31,31 2006.257.11:15:28.60/vb/08,04,usb,yes,28,32 2006.257.11:15:28.83/vblo/01,629.99,yes,locked 2006.257.11:15:28.83/vblo/02,634.99,yes,locked 2006.257.11:15:28.83/vblo/03,649.99,yes,locked 2006.257.11:15:28.83/vblo/04,679.99,yes,locked 2006.257.11:15:28.83/vblo/05,709.99,yes,locked 2006.257.11:15:28.83/vblo/06,719.99,yes,locked 2006.257.11:15:28.83/vblo/07,734.99,yes,locked 2006.257.11:15:28.83/vblo/08,744.99,yes,locked 2006.257.11:15:28.98/vabw/8 2006.257.11:15:29.13/vbbw/8 2006.257.11:15:29.22/xfe/off,on,15.2 2006.257.11:15:29.59/ifatt/23,28,28,28 2006.257.11:15:30.08/fmout-gps/S +4.60E-07 2006.257.11:15:30.12:!2006.257.11:18:16 2006.257.11:18:16.00:data_valid=off 2006.257.11:18:16.00:"et 2006.257.11:18:16.00:!+3s 2006.257.11:18:19.02:"tape 2006.257.11:18:19.02:postob 2006.257.11:18:19.15/cable/+6.4757E-03 2006.257.11:18:19.15/wx/18.35,1013.8,97 2006.257.11:18:20.08/fmout-gps/S +4.60E-07 2006.257.11:18:20.08:scan_name=257-1120,jd0609,130 2006.257.11:18:20.08:source=1958-179,200057.09,-174857.7,2000.0,ccw 2006.257.11:18:21.14#flagr#flagr/antenna,new-source 2006.257.11:18:21.14:checkk5 2006.257.11:18:21.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:18:21.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:18:22.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:18:22.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:18:23.15/chk_obsdata//k5ts1/T2571115??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.11:18:23.55/chk_obsdata//k5ts2/T2571115??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.11:18:23.95/chk_obsdata//k5ts3/T2571115??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.11:18:24.35/chk_obsdata//k5ts4/T2571115??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.11:18:25.06/k5log//k5ts1_log_newline 2006.257.11:18:25.76/k5log//k5ts2_log_newline 2006.257.11:18:26.49/k5log//k5ts3_log_newline 2006.257.11:18:27.20/k5log//k5ts4_log_newline 2006.257.11:18:27.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:18:27.22:setupk4=1 2006.257.11:18:27.22$setupk4/echo=on 2006.257.11:18:27.22$setupk4/pcalon 2006.257.11:18:27.22$pcalon/"no phase cal control is implemented here 2006.257.11:18:27.22$setupk4/"tpicd=stop 2006.257.11:18:27.22$setupk4/"rec=synch_on 2006.257.11:18:27.22$setupk4/"rec_mode=128 2006.257.11:18:27.22$setupk4/!* 2006.257.11:18:27.22$setupk4/recpk4 2006.257.11:18:27.22$recpk4/recpatch= 2006.257.11:18:27.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:18:27.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:18:27.22$setupk4/vck44 2006.257.11:18:27.22$vck44/valo=1,524.99 2006.257.11:18:27.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.11:18:27.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.11:18:27.22#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:27.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:27.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:27.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:27.22#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:18:27.22#ibcon#first serial, iclass 20, count 0 2006.257.11:18:27.22#ibcon#enter sib2, iclass 20, count 0 2006.257.11:18:27.22#ibcon#flushed, iclass 20, count 0 2006.257.11:18:27.22#ibcon#about to write, iclass 20, count 0 2006.257.11:18:27.22#ibcon#wrote, iclass 20, count 0 2006.257.11:18:27.22#ibcon#about to read 3, iclass 20, count 0 2006.257.11:18:27.24#ibcon#read 3, iclass 20, count 0 2006.257.11:18:27.24#ibcon#about to read 4, iclass 20, count 0 2006.257.11:18:27.24#ibcon#read 4, iclass 20, count 0 2006.257.11:18:27.24#ibcon#about to read 5, iclass 20, count 0 2006.257.11:18:27.24#ibcon#read 5, iclass 20, count 0 2006.257.11:18:27.24#ibcon#about to read 6, iclass 20, count 0 2006.257.11:18:27.24#ibcon#read 6, iclass 20, count 0 2006.257.11:18:27.24#ibcon#end of sib2, iclass 20, count 0 2006.257.11:18:27.24#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:18:27.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:18:27.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:18:27.24#ibcon#*before write, iclass 20, count 0 2006.257.11:18:27.24#ibcon#enter sib2, iclass 20, count 0 2006.257.11:18:27.24#ibcon#flushed, iclass 20, count 0 2006.257.11:18:27.24#ibcon#about to write, iclass 20, count 0 2006.257.11:18:27.24#ibcon#wrote, iclass 20, count 0 2006.257.11:18:27.24#ibcon#about to read 3, iclass 20, count 0 2006.257.11:18:27.29#ibcon#read 3, iclass 20, count 0 2006.257.11:18:27.29#ibcon#about to read 4, iclass 20, count 0 2006.257.11:18:27.29#ibcon#read 4, iclass 20, count 0 2006.257.11:18:27.29#ibcon#about to read 5, iclass 20, count 0 2006.257.11:18:27.29#ibcon#read 5, iclass 20, count 0 2006.257.11:18:27.29#ibcon#about to read 6, iclass 20, count 0 2006.257.11:18:27.29#ibcon#read 6, iclass 20, count 0 2006.257.11:18:27.29#ibcon#end of sib2, iclass 20, count 0 2006.257.11:18:27.29#ibcon#*after write, iclass 20, count 0 2006.257.11:18:27.29#ibcon#*before return 0, iclass 20, count 0 2006.257.11:18:27.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:27.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:27.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:18:27.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:18:27.29$vck44/va=1,8 2006.257.11:18:27.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.11:18:27.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.11:18:27.29#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:27.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:27.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:27.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:27.29#ibcon#enter wrdev, iclass 22, count 2 2006.257.11:18:27.29#ibcon#first serial, iclass 22, count 2 2006.257.11:18:27.29#ibcon#enter sib2, iclass 22, count 2 2006.257.11:18:27.29#ibcon#flushed, iclass 22, count 2 2006.257.11:18:27.29#ibcon#about to write, iclass 22, count 2 2006.257.11:18:27.29#ibcon#wrote, iclass 22, count 2 2006.257.11:18:27.29#ibcon#about to read 3, iclass 22, count 2 2006.257.11:18:27.31#ibcon#read 3, iclass 22, count 2 2006.257.11:18:27.31#ibcon#about to read 4, iclass 22, count 2 2006.257.11:18:27.31#ibcon#read 4, iclass 22, count 2 2006.257.11:18:27.31#ibcon#about to read 5, iclass 22, count 2 2006.257.11:18:27.31#ibcon#read 5, iclass 22, count 2 2006.257.11:18:27.31#ibcon#about to read 6, iclass 22, count 2 2006.257.11:18:27.31#ibcon#read 6, iclass 22, count 2 2006.257.11:18:27.31#ibcon#end of sib2, iclass 22, count 2 2006.257.11:18:27.31#ibcon#*mode == 0, iclass 22, count 2 2006.257.11:18:27.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.11:18:27.31#ibcon#[25=AT01-08\r\n] 2006.257.11:18:27.31#ibcon#*before write, iclass 22, count 2 2006.257.11:18:27.31#ibcon#enter sib2, iclass 22, count 2 2006.257.11:18:27.31#ibcon#flushed, iclass 22, count 2 2006.257.11:18:27.31#ibcon#about to write, iclass 22, count 2 2006.257.11:18:27.31#ibcon#wrote, iclass 22, count 2 2006.257.11:18:27.31#ibcon#about to read 3, iclass 22, count 2 2006.257.11:18:27.34#ibcon#read 3, iclass 22, count 2 2006.257.11:18:27.34#ibcon#about to read 4, iclass 22, count 2 2006.257.11:18:27.34#ibcon#read 4, iclass 22, count 2 2006.257.11:18:27.34#ibcon#about to read 5, iclass 22, count 2 2006.257.11:18:27.34#ibcon#read 5, iclass 22, count 2 2006.257.11:18:27.34#ibcon#about to read 6, iclass 22, count 2 2006.257.11:18:27.34#ibcon#read 6, iclass 22, count 2 2006.257.11:18:27.34#ibcon#end of sib2, iclass 22, count 2 2006.257.11:18:27.34#ibcon#*after write, iclass 22, count 2 2006.257.11:18:27.34#ibcon#*before return 0, iclass 22, count 2 2006.257.11:18:27.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:27.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:27.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.11:18:27.34#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:27.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:27.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:27.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:27.46#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:18:27.46#ibcon#first serial, iclass 22, count 0 2006.257.11:18:27.46#ibcon#enter sib2, iclass 22, count 0 2006.257.11:18:27.46#ibcon#flushed, iclass 22, count 0 2006.257.11:18:27.46#ibcon#about to write, iclass 22, count 0 2006.257.11:18:27.46#ibcon#wrote, iclass 22, count 0 2006.257.11:18:27.46#ibcon#about to read 3, iclass 22, count 0 2006.257.11:18:27.48#ibcon#read 3, iclass 22, count 0 2006.257.11:18:27.48#ibcon#about to read 4, iclass 22, count 0 2006.257.11:18:27.48#ibcon#read 4, iclass 22, count 0 2006.257.11:18:27.48#ibcon#about to read 5, iclass 22, count 0 2006.257.11:18:27.48#ibcon#read 5, iclass 22, count 0 2006.257.11:18:27.48#ibcon#about to read 6, iclass 22, count 0 2006.257.11:18:27.48#ibcon#read 6, iclass 22, count 0 2006.257.11:18:27.48#ibcon#end of sib2, iclass 22, count 0 2006.257.11:18:27.48#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:18:27.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:18:27.48#ibcon#[25=USB\r\n] 2006.257.11:18:27.48#ibcon#*before write, iclass 22, count 0 2006.257.11:18:27.48#ibcon#enter sib2, iclass 22, count 0 2006.257.11:18:27.48#ibcon#flushed, iclass 22, count 0 2006.257.11:18:27.48#ibcon#about to write, iclass 22, count 0 2006.257.11:18:27.48#ibcon#wrote, iclass 22, count 0 2006.257.11:18:27.48#ibcon#about to read 3, iclass 22, count 0 2006.257.11:18:27.51#ibcon#read 3, iclass 22, count 0 2006.257.11:18:27.51#ibcon#about to read 4, iclass 22, count 0 2006.257.11:18:27.51#ibcon#read 4, iclass 22, count 0 2006.257.11:18:27.51#ibcon#about to read 5, iclass 22, count 0 2006.257.11:18:27.51#ibcon#read 5, iclass 22, count 0 2006.257.11:18:27.51#ibcon#about to read 6, iclass 22, count 0 2006.257.11:18:27.51#ibcon#read 6, iclass 22, count 0 2006.257.11:18:27.51#ibcon#end of sib2, iclass 22, count 0 2006.257.11:18:27.51#ibcon#*after write, iclass 22, count 0 2006.257.11:18:27.51#ibcon#*before return 0, iclass 22, count 0 2006.257.11:18:27.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:27.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:27.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:18:27.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:18:27.51$vck44/valo=2,534.99 2006.257.11:18:27.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.11:18:27.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.11:18:27.51#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:27.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:27.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:27.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:27.51#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:18:27.51#ibcon#first serial, iclass 24, count 0 2006.257.11:18:27.51#ibcon#enter sib2, iclass 24, count 0 2006.257.11:18:27.51#ibcon#flushed, iclass 24, count 0 2006.257.11:18:27.51#ibcon#about to write, iclass 24, count 0 2006.257.11:18:27.51#ibcon#wrote, iclass 24, count 0 2006.257.11:18:27.51#ibcon#about to read 3, iclass 24, count 0 2006.257.11:18:27.53#ibcon#read 3, iclass 24, count 0 2006.257.11:18:27.53#ibcon#about to read 4, iclass 24, count 0 2006.257.11:18:27.53#ibcon#read 4, iclass 24, count 0 2006.257.11:18:27.53#ibcon#about to read 5, iclass 24, count 0 2006.257.11:18:27.53#ibcon#read 5, iclass 24, count 0 2006.257.11:18:27.53#ibcon#about to read 6, iclass 24, count 0 2006.257.11:18:27.53#ibcon#read 6, iclass 24, count 0 2006.257.11:18:27.53#ibcon#end of sib2, iclass 24, count 0 2006.257.11:18:27.53#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:18:27.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:18:27.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:18:27.53#ibcon#*before write, iclass 24, count 0 2006.257.11:18:27.53#ibcon#enter sib2, iclass 24, count 0 2006.257.11:18:27.53#ibcon#flushed, iclass 24, count 0 2006.257.11:18:27.53#ibcon#about to write, iclass 24, count 0 2006.257.11:18:27.53#ibcon#wrote, iclass 24, count 0 2006.257.11:18:27.53#ibcon#about to read 3, iclass 24, count 0 2006.257.11:18:27.57#ibcon#read 3, iclass 24, count 0 2006.257.11:18:27.57#ibcon#about to read 4, iclass 24, count 0 2006.257.11:18:27.57#ibcon#read 4, iclass 24, count 0 2006.257.11:18:27.57#ibcon#about to read 5, iclass 24, count 0 2006.257.11:18:27.57#ibcon#read 5, iclass 24, count 0 2006.257.11:18:27.57#ibcon#about to read 6, iclass 24, count 0 2006.257.11:18:27.57#ibcon#read 6, iclass 24, count 0 2006.257.11:18:27.57#ibcon#end of sib2, iclass 24, count 0 2006.257.11:18:27.57#ibcon#*after write, iclass 24, count 0 2006.257.11:18:27.57#ibcon#*before return 0, iclass 24, count 0 2006.257.11:18:27.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:27.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:27.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:18:27.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:18:27.57$vck44/va=2,7 2006.257.11:18:27.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.11:18:27.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.11:18:27.57#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:27.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:27.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:27.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:27.63#ibcon#enter wrdev, iclass 26, count 2 2006.257.11:18:27.63#ibcon#first serial, iclass 26, count 2 2006.257.11:18:27.63#ibcon#enter sib2, iclass 26, count 2 2006.257.11:18:27.63#ibcon#flushed, iclass 26, count 2 2006.257.11:18:27.63#ibcon#about to write, iclass 26, count 2 2006.257.11:18:27.63#ibcon#wrote, iclass 26, count 2 2006.257.11:18:27.63#ibcon#about to read 3, iclass 26, count 2 2006.257.11:18:27.65#ibcon#read 3, iclass 26, count 2 2006.257.11:18:27.65#ibcon#about to read 4, iclass 26, count 2 2006.257.11:18:27.65#ibcon#read 4, iclass 26, count 2 2006.257.11:18:27.65#ibcon#about to read 5, iclass 26, count 2 2006.257.11:18:27.65#ibcon#read 5, iclass 26, count 2 2006.257.11:18:27.65#ibcon#about to read 6, iclass 26, count 2 2006.257.11:18:27.65#ibcon#read 6, iclass 26, count 2 2006.257.11:18:27.65#ibcon#end of sib2, iclass 26, count 2 2006.257.11:18:27.65#ibcon#*mode == 0, iclass 26, count 2 2006.257.11:18:27.65#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.11:18:27.65#ibcon#[25=AT02-07\r\n] 2006.257.11:18:27.65#ibcon#*before write, iclass 26, count 2 2006.257.11:18:27.65#ibcon#enter sib2, iclass 26, count 2 2006.257.11:18:27.65#ibcon#flushed, iclass 26, count 2 2006.257.11:18:27.65#ibcon#about to write, iclass 26, count 2 2006.257.11:18:27.65#ibcon#wrote, iclass 26, count 2 2006.257.11:18:27.65#ibcon#about to read 3, iclass 26, count 2 2006.257.11:18:27.68#ibcon#read 3, iclass 26, count 2 2006.257.11:18:27.68#ibcon#about to read 4, iclass 26, count 2 2006.257.11:18:27.68#ibcon#read 4, iclass 26, count 2 2006.257.11:18:27.68#ibcon#about to read 5, iclass 26, count 2 2006.257.11:18:27.68#ibcon#read 5, iclass 26, count 2 2006.257.11:18:27.68#ibcon#about to read 6, iclass 26, count 2 2006.257.11:18:27.68#ibcon#read 6, iclass 26, count 2 2006.257.11:18:27.68#ibcon#end of sib2, iclass 26, count 2 2006.257.11:18:27.68#ibcon#*after write, iclass 26, count 2 2006.257.11:18:27.68#ibcon#*before return 0, iclass 26, count 2 2006.257.11:18:27.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:27.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:27.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.11:18:27.68#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:27.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:27.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:27.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:27.80#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:18:27.80#ibcon#first serial, iclass 26, count 0 2006.257.11:18:27.80#ibcon#enter sib2, iclass 26, count 0 2006.257.11:18:27.80#ibcon#flushed, iclass 26, count 0 2006.257.11:18:27.80#ibcon#about to write, iclass 26, count 0 2006.257.11:18:27.80#ibcon#wrote, iclass 26, count 0 2006.257.11:18:27.80#ibcon#about to read 3, iclass 26, count 0 2006.257.11:18:27.82#ibcon#read 3, iclass 26, count 0 2006.257.11:18:27.82#ibcon#about to read 4, iclass 26, count 0 2006.257.11:18:27.82#ibcon#read 4, iclass 26, count 0 2006.257.11:18:27.82#ibcon#about to read 5, iclass 26, count 0 2006.257.11:18:27.82#ibcon#read 5, iclass 26, count 0 2006.257.11:18:27.82#ibcon#about to read 6, iclass 26, count 0 2006.257.11:18:27.82#ibcon#read 6, iclass 26, count 0 2006.257.11:18:27.82#ibcon#end of sib2, iclass 26, count 0 2006.257.11:18:27.82#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:18:27.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:18:27.82#ibcon#[25=USB\r\n] 2006.257.11:18:27.82#ibcon#*before write, iclass 26, count 0 2006.257.11:18:27.82#ibcon#enter sib2, iclass 26, count 0 2006.257.11:18:27.82#ibcon#flushed, iclass 26, count 0 2006.257.11:18:27.82#ibcon#about to write, iclass 26, count 0 2006.257.11:18:27.82#ibcon#wrote, iclass 26, count 0 2006.257.11:18:27.82#ibcon#about to read 3, iclass 26, count 0 2006.257.11:18:27.85#ibcon#read 3, iclass 26, count 0 2006.257.11:18:27.85#ibcon#about to read 4, iclass 26, count 0 2006.257.11:18:27.85#ibcon#read 4, iclass 26, count 0 2006.257.11:18:27.85#ibcon#about to read 5, iclass 26, count 0 2006.257.11:18:27.85#ibcon#read 5, iclass 26, count 0 2006.257.11:18:27.85#ibcon#about to read 6, iclass 26, count 0 2006.257.11:18:27.85#ibcon#read 6, iclass 26, count 0 2006.257.11:18:27.85#ibcon#end of sib2, iclass 26, count 0 2006.257.11:18:27.85#ibcon#*after write, iclass 26, count 0 2006.257.11:18:27.85#ibcon#*before return 0, iclass 26, count 0 2006.257.11:18:27.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:27.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:27.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:18:27.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:18:27.85$vck44/valo=3,564.99 2006.257.11:18:27.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.11:18:27.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.11:18:27.85#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:27.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:27.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:27.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:27.85#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:18:27.85#ibcon#first serial, iclass 28, count 0 2006.257.11:18:27.85#ibcon#enter sib2, iclass 28, count 0 2006.257.11:18:27.85#ibcon#flushed, iclass 28, count 0 2006.257.11:18:27.85#ibcon#about to write, iclass 28, count 0 2006.257.11:18:27.85#ibcon#wrote, iclass 28, count 0 2006.257.11:18:27.85#ibcon#about to read 3, iclass 28, count 0 2006.257.11:18:27.87#ibcon#read 3, iclass 28, count 0 2006.257.11:18:27.87#ibcon#about to read 4, iclass 28, count 0 2006.257.11:18:27.87#ibcon#read 4, iclass 28, count 0 2006.257.11:18:27.87#ibcon#about to read 5, iclass 28, count 0 2006.257.11:18:27.87#ibcon#read 5, iclass 28, count 0 2006.257.11:18:27.87#ibcon#about to read 6, iclass 28, count 0 2006.257.11:18:27.87#ibcon#read 6, iclass 28, count 0 2006.257.11:18:27.87#ibcon#end of sib2, iclass 28, count 0 2006.257.11:18:27.87#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:18:27.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:18:27.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:18:27.87#ibcon#*before write, iclass 28, count 0 2006.257.11:18:27.87#ibcon#enter sib2, iclass 28, count 0 2006.257.11:18:27.87#ibcon#flushed, iclass 28, count 0 2006.257.11:18:27.87#ibcon#about to write, iclass 28, count 0 2006.257.11:18:27.87#ibcon#wrote, iclass 28, count 0 2006.257.11:18:27.87#ibcon#about to read 3, iclass 28, count 0 2006.257.11:18:27.91#ibcon#read 3, iclass 28, count 0 2006.257.11:18:27.91#ibcon#about to read 4, iclass 28, count 0 2006.257.11:18:27.91#ibcon#read 4, iclass 28, count 0 2006.257.11:18:27.91#ibcon#about to read 5, iclass 28, count 0 2006.257.11:18:27.91#ibcon#read 5, iclass 28, count 0 2006.257.11:18:27.91#ibcon#about to read 6, iclass 28, count 0 2006.257.11:18:27.91#ibcon#read 6, iclass 28, count 0 2006.257.11:18:27.91#ibcon#end of sib2, iclass 28, count 0 2006.257.11:18:27.91#ibcon#*after write, iclass 28, count 0 2006.257.11:18:27.91#ibcon#*before return 0, iclass 28, count 0 2006.257.11:18:27.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:27.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:27.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:18:27.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:18:27.91$vck44/va=3,8 2006.257.11:18:27.91#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.11:18:27.91#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.11:18:27.91#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:27.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:27.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:27.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:27.97#ibcon#enter wrdev, iclass 30, count 2 2006.257.11:18:27.97#ibcon#first serial, iclass 30, count 2 2006.257.11:18:27.97#ibcon#enter sib2, iclass 30, count 2 2006.257.11:18:27.97#ibcon#flushed, iclass 30, count 2 2006.257.11:18:27.97#ibcon#about to write, iclass 30, count 2 2006.257.11:18:27.97#ibcon#wrote, iclass 30, count 2 2006.257.11:18:27.97#ibcon#about to read 3, iclass 30, count 2 2006.257.11:18:27.99#ibcon#read 3, iclass 30, count 2 2006.257.11:18:27.99#ibcon#about to read 4, iclass 30, count 2 2006.257.11:18:27.99#ibcon#read 4, iclass 30, count 2 2006.257.11:18:27.99#ibcon#about to read 5, iclass 30, count 2 2006.257.11:18:27.99#ibcon#read 5, iclass 30, count 2 2006.257.11:18:27.99#ibcon#about to read 6, iclass 30, count 2 2006.257.11:18:27.99#ibcon#read 6, iclass 30, count 2 2006.257.11:18:27.99#ibcon#end of sib2, iclass 30, count 2 2006.257.11:18:27.99#ibcon#*mode == 0, iclass 30, count 2 2006.257.11:18:27.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.11:18:27.99#ibcon#[25=AT03-08\r\n] 2006.257.11:18:27.99#ibcon#*before write, iclass 30, count 2 2006.257.11:18:27.99#ibcon#enter sib2, iclass 30, count 2 2006.257.11:18:27.99#ibcon#flushed, iclass 30, count 2 2006.257.11:18:27.99#ibcon#about to write, iclass 30, count 2 2006.257.11:18:27.99#ibcon#wrote, iclass 30, count 2 2006.257.11:18:27.99#ibcon#about to read 3, iclass 30, count 2 2006.257.11:18:28.02#ibcon#read 3, iclass 30, count 2 2006.257.11:18:28.02#ibcon#about to read 4, iclass 30, count 2 2006.257.11:18:28.02#ibcon#read 4, iclass 30, count 2 2006.257.11:18:28.02#ibcon#about to read 5, iclass 30, count 2 2006.257.11:18:28.02#ibcon#read 5, iclass 30, count 2 2006.257.11:18:28.02#ibcon#about to read 6, iclass 30, count 2 2006.257.11:18:28.02#ibcon#read 6, iclass 30, count 2 2006.257.11:18:28.02#ibcon#end of sib2, iclass 30, count 2 2006.257.11:18:28.02#ibcon#*after write, iclass 30, count 2 2006.257.11:18:28.02#ibcon#*before return 0, iclass 30, count 2 2006.257.11:18:28.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:28.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:28.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.11:18:28.02#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:28.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:28.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:28.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:28.14#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:18:28.14#ibcon#first serial, iclass 30, count 0 2006.257.11:18:28.14#ibcon#enter sib2, iclass 30, count 0 2006.257.11:18:28.14#ibcon#flushed, iclass 30, count 0 2006.257.11:18:28.14#ibcon#about to write, iclass 30, count 0 2006.257.11:18:28.14#ibcon#wrote, iclass 30, count 0 2006.257.11:18:28.14#ibcon#about to read 3, iclass 30, count 0 2006.257.11:18:28.16#ibcon#read 3, iclass 30, count 0 2006.257.11:18:28.16#ibcon#about to read 4, iclass 30, count 0 2006.257.11:18:28.16#ibcon#read 4, iclass 30, count 0 2006.257.11:18:28.16#ibcon#about to read 5, iclass 30, count 0 2006.257.11:18:28.16#ibcon#read 5, iclass 30, count 0 2006.257.11:18:28.16#ibcon#about to read 6, iclass 30, count 0 2006.257.11:18:28.16#ibcon#read 6, iclass 30, count 0 2006.257.11:18:28.16#ibcon#end of sib2, iclass 30, count 0 2006.257.11:18:28.16#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:18:28.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:18:28.16#ibcon#[25=USB\r\n] 2006.257.11:18:28.16#ibcon#*before write, iclass 30, count 0 2006.257.11:18:28.16#ibcon#enter sib2, iclass 30, count 0 2006.257.11:18:28.16#ibcon#flushed, iclass 30, count 0 2006.257.11:18:28.16#ibcon#about to write, iclass 30, count 0 2006.257.11:18:28.16#ibcon#wrote, iclass 30, count 0 2006.257.11:18:28.16#ibcon#about to read 3, iclass 30, count 0 2006.257.11:18:28.19#ibcon#read 3, iclass 30, count 0 2006.257.11:18:28.19#ibcon#about to read 4, iclass 30, count 0 2006.257.11:18:28.19#ibcon#read 4, iclass 30, count 0 2006.257.11:18:28.19#ibcon#about to read 5, iclass 30, count 0 2006.257.11:18:28.19#ibcon#read 5, iclass 30, count 0 2006.257.11:18:28.19#ibcon#about to read 6, iclass 30, count 0 2006.257.11:18:28.19#ibcon#read 6, iclass 30, count 0 2006.257.11:18:28.19#ibcon#end of sib2, iclass 30, count 0 2006.257.11:18:28.19#ibcon#*after write, iclass 30, count 0 2006.257.11:18:28.19#ibcon#*before return 0, iclass 30, count 0 2006.257.11:18:28.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:28.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:28.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:18:28.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:18:28.19$vck44/valo=4,624.99 2006.257.11:18:28.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.11:18:28.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.11:18:28.19#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:28.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:28.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:28.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:28.19#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:18:28.19#ibcon#first serial, iclass 32, count 0 2006.257.11:18:28.19#ibcon#enter sib2, iclass 32, count 0 2006.257.11:18:28.19#ibcon#flushed, iclass 32, count 0 2006.257.11:18:28.19#ibcon#about to write, iclass 32, count 0 2006.257.11:18:28.19#ibcon#wrote, iclass 32, count 0 2006.257.11:18:28.19#ibcon#about to read 3, iclass 32, count 0 2006.257.11:18:28.21#ibcon#read 3, iclass 32, count 0 2006.257.11:18:28.21#ibcon#about to read 4, iclass 32, count 0 2006.257.11:18:28.21#ibcon#read 4, iclass 32, count 0 2006.257.11:18:28.21#ibcon#about to read 5, iclass 32, count 0 2006.257.11:18:28.21#ibcon#read 5, iclass 32, count 0 2006.257.11:18:28.21#ibcon#about to read 6, iclass 32, count 0 2006.257.11:18:28.21#ibcon#read 6, iclass 32, count 0 2006.257.11:18:28.21#ibcon#end of sib2, iclass 32, count 0 2006.257.11:18:28.21#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:18:28.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:18:28.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:18:28.21#ibcon#*before write, iclass 32, count 0 2006.257.11:18:28.21#ibcon#enter sib2, iclass 32, count 0 2006.257.11:18:28.21#ibcon#flushed, iclass 32, count 0 2006.257.11:18:28.21#ibcon#about to write, iclass 32, count 0 2006.257.11:18:28.21#ibcon#wrote, iclass 32, count 0 2006.257.11:18:28.21#ibcon#about to read 3, iclass 32, count 0 2006.257.11:18:28.25#ibcon#read 3, iclass 32, count 0 2006.257.11:18:28.25#ibcon#about to read 4, iclass 32, count 0 2006.257.11:18:28.25#ibcon#read 4, iclass 32, count 0 2006.257.11:18:28.25#ibcon#about to read 5, iclass 32, count 0 2006.257.11:18:28.25#ibcon#read 5, iclass 32, count 0 2006.257.11:18:28.25#ibcon#about to read 6, iclass 32, count 0 2006.257.11:18:28.25#ibcon#read 6, iclass 32, count 0 2006.257.11:18:28.25#ibcon#end of sib2, iclass 32, count 0 2006.257.11:18:28.25#ibcon#*after write, iclass 32, count 0 2006.257.11:18:28.25#ibcon#*before return 0, iclass 32, count 0 2006.257.11:18:28.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:28.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:28.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:18:28.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:18:28.25$vck44/va=4,7 2006.257.11:18:28.25#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.11:18:28.25#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.11:18:28.25#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:28.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:28.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:28.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:28.31#ibcon#enter wrdev, iclass 34, count 2 2006.257.11:18:28.31#ibcon#first serial, iclass 34, count 2 2006.257.11:18:28.31#ibcon#enter sib2, iclass 34, count 2 2006.257.11:18:28.31#ibcon#flushed, iclass 34, count 2 2006.257.11:18:28.31#ibcon#about to write, iclass 34, count 2 2006.257.11:18:28.31#ibcon#wrote, iclass 34, count 2 2006.257.11:18:28.31#ibcon#about to read 3, iclass 34, count 2 2006.257.11:18:28.33#ibcon#read 3, iclass 34, count 2 2006.257.11:18:28.33#ibcon#about to read 4, iclass 34, count 2 2006.257.11:18:28.33#ibcon#read 4, iclass 34, count 2 2006.257.11:18:28.33#ibcon#about to read 5, iclass 34, count 2 2006.257.11:18:28.33#ibcon#read 5, iclass 34, count 2 2006.257.11:18:28.33#ibcon#about to read 6, iclass 34, count 2 2006.257.11:18:28.33#ibcon#read 6, iclass 34, count 2 2006.257.11:18:28.33#ibcon#end of sib2, iclass 34, count 2 2006.257.11:18:28.33#ibcon#*mode == 0, iclass 34, count 2 2006.257.11:18:28.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.11:18:28.33#ibcon#[25=AT04-07\r\n] 2006.257.11:18:28.33#ibcon#*before write, iclass 34, count 2 2006.257.11:18:28.33#ibcon#enter sib2, iclass 34, count 2 2006.257.11:18:28.33#ibcon#flushed, iclass 34, count 2 2006.257.11:18:28.33#ibcon#about to write, iclass 34, count 2 2006.257.11:18:28.33#ibcon#wrote, iclass 34, count 2 2006.257.11:18:28.33#ibcon#about to read 3, iclass 34, count 2 2006.257.11:18:28.36#ibcon#read 3, iclass 34, count 2 2006.257.11:18:28.36#ibcon#about to read 4, iclass 34, count 2 2006.257.11:18:28.36#ibcon#read 4, iclass 34, count 2 2006.257.11:18:28.36#ibcon#about to read 5, iclass 34, count 2 2006.257.11:18:28.36#ibcon#read 5, iclass 34, count 2 2006.257.11:18:28.36#ibcon#about to read 6, iclass 34, count 2 2006.257.11:18:28.36#ibcon#read 6, iclass 34, count 2 2006.257.11:18:28.36#ibcon#end of sib2, iclass 34, count 2 2006.257.11:18:28.36#ibcon#*after write, iclass 34, count 2 2006.257.11:18:28.36#ibcon#*before return 0, iclass 34, count 2 2006.257.11:18:28.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:28.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:28.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.11:18:28.36#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:28.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:28.47#abcon#<5=/15 1.4 2.9 18.35 971013.8\r\n> 2006.257.11:18:28.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:28.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:28.48#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:18:28.48#ibcon#first serial, iclass 34, count 0 2006.257.11:18:28.48#ibcon#enter sib2, iclass 34, count 0 2006.257.11:18:28.48#ibcon#flushed, iclass 34, count 0 2006.257.11:18:28.48#ibcon#about to write, iclass 34, count 0 2006.257.11:18:28.48#ibcon#wrote, iclass 34, count 0 2006.257.11:18:28.48#ibcon#about to read 3, iclass 34, count 0 2006.257.11:18:28.49#abcon#{5=INTERFACE CLEAR} 2006.257.11:18:28.50#ibcon#read 3, iclass 34, count 0 2006.257.11:18:28.50#ibcon#about to read 4, iclass 34, count 0 2006.257.11:18:28.50#ibcon#read 4, iclass 34, count 0 2006.257.11:18:28.50#ibcon#about to read 5, iclass 34, count 0 2006.257.11:18:28.50#ibcon#read 5, iclass 34, count 0 2006.257.11:18:28.50#ibcon#about to read 6, iclass 34, count 0 2006.257.11:18:28.50#ibcon#read 6, iclass 34, count 0 2006.257.11:18:28.50#ibcon#end of sib2, iclass 34, count 0 2006.257.11:18:28.50#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:18:28.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:18:28.50#ibcon#[25=USB\r\n] 2006.257.11:18:28.50#ibcon#*before write, iclass 34, count 0 2006.257.11:18:28.50#ibcon#enter sib2, iclass 34, count 0 2006.257.11:18:28.50#ibcon#flushed, iclass 34, count 0 2006.257.11:18:28.50#ibcon#about to write, iclass 34, count 0 2006.257.11:18:28.50#ibcon#wrote, iclass 34, count 0 2006.257.11:18:28.50#ibcon#about to read 3, iclass 34, count 0 2006.257.11:18:28.53#ibcon#read 3, iclass 34, count 0 2006.257.11:18:28.53#ibcon#about to read 4, iclass 34, count 0 2006.257.11:18:28.53#ibcon#read 4, iclass 34, count 0 2006.257.11:18:28.53#ibcon#about to read 5, iclass 34, count 0 2006.257.11:18:28.53#ibcon#read 5, iclass 34, count 0 2006.257.11:18:28.53#ibcon#about to read 6, iclass 34, count 0 2006.257.11:18:28.53#ibcon#read 6, iclass 34, count 0 2006.257.11:18:28.53#ibcon#end of sib2, iclass 34, count 0 2006.257.11:18:28.53#ibcon#*after write, iclass 34, count 0 2006.257.11:18:28.53#ibcon#*before return 0, iclass 34, count 0 2006.257.11:18:28.53#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:28.53#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:28.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:18:28.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:18:28.53$vck44/valo=5,734.99 2006.257.11:18:28.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.11:18:28.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.11:18:28.53#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:28.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:18:28.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:18:28.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:18:28.53#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:18:28.53#ibcon#first serial, iclass 39, count 0 2006.257.11:18:28.53#ibcon#enter sib2, iclass 39, count 0 2006.257.11:18:28.53#ibcon#flushed, iclass 39, count 0 2006.257.11:18:28.53#ibcon#about to write, iclass 39, count 0 2006.257.11:18:28.53#ibcon#wrote, iclass 39, count 0 2006.257.11:18:28.53#ibcon#about to read 3, iclass 39, count 0 2006.257.11:18:28.55#ibcon#read 3, iclass 39, count 0 2006.257.11:18:28.55#ibcon#about to read 4, iclass 39, count 0 2006.257.11:18:28.55#ibcon#read 4, iclass 39, count 0 2006.257.11:18:28.55#ibcon#about to read 5, iclass 39, count 0 2006.257.11:18:28.55#ibcon#read 5, iclass 39, count 0 2006.257.11:18:28.55#ibcon#about to read 6, iclass 39, count 0 2006.257.11:18:28.55#ibcon#read 6, iclass 39, count 0 2006.257.11:18:28.55#ibcon#end of sib2, iclass 39, count 0 2006.257.11:18:28.55#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:18:28.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:18:28.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:18:28.55#ibcon#*before write, iclass 39, count 0 2006.257.11:18:28.55#ibcon#enter sib2, iclass 39, count 0 2006.257.11:18:28.55#ibcon#flushed, iclass 39, count 0 2006.257.11:18:28.55#ibcon#about to write, iclass 39, count 0 2006.257.11:18:28.55#ibcon#wrote, iclass 39, count 0 2006.257.11:18:28.55#ibcon#about to read 3, iclass 39, count 0 2006.257.11:18:28.55#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:18:28.59#ibcon#read 3, iclass 39, count 0 2006.257.11:18:28.59#ibcon#about to read 4, iclass 39, count 0 2006.257.11:18:28.59#ibcon#read 4, iclass 39, count 0 2006.257.11:18:28.59#ibcon#about to read 5, iclass 39, count 0 2006.257.11:18:28.59#ibcon#read 5, iclass 39, count 0 2006.257.11:18:28.59#ibcon#about to read 6, iclass 39, count 0 2006.257.11:18:28.59#ibcon#read 6, iclass 39, count 0 2006.257.11:18:28.59#ibcon#end of sib2, iclass 39, count 0 2006.257.11:18:28.59#ibcon#*after write, iclass 39, count 0 2006.257.11:18:28.59#ibcon#*before return 0, iclass 39, count 0 2006.257.11:18:28.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:18:28.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:18:28.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:18:28.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:18:28.59$vck44/va=5,4 2006.257.11:18:28.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.11:18:28.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.11:18:28.59#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:28.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:28.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:28.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:28.65#ibcon#enter wrdev, iclass 4, count 2 2006.257.11:18:28.65#ibcon#first serial, iclass 4, count 2 2006.257.11:18:28.65#ibcon#enter sib2, iclass 4, count 2 2006.257.11:18:28.65#ibcon#flushed, iclass 4, count 2 2006.257.11:18:28.65#ibcon#about to write, iclass 4, count 2 2006.257.11:18:28.65#ibcon#wrote, iclass 4, count 2 2006.257.11:18:28.65#ibcon#about to read 3, iclass 4, count 2 2006.257.11:18:28.67#ibcon#read 3, iclass 4, count 2 2006.257.11:18:28.67#ibcon#about to read 4, iclass 4, count 2 2006.257.11:18:28.67#ibcon#read 4, iclass 4, count 2 2006.257.11:18:28.67#ibcon#about to read 5, iclass 4, count 2 2006.257.11:18:28.67#ibcon#read 5, iclass 4, count 2 2006.257.11:18:28.67#ibcon#about to read 6, iclass 4, count 2 2006.257.11:18:28.67#ibcon#read 6, iclass 4, count 2 2006.257.11:18:28.67#ibcon#end of sib2, iclass 4, count 2 2006.257.11:18:28.67#ibcon#*mode == 0, iclass 4, count 2 2006.257.11:18:28.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.11:18:28.67#ibcon#[25=AT05-04\r\n] 2006.257.11:18:28.67#ibcon#*before write, iclass 4, count 2 2006.257.11:18:28.67#ibcon#enter sib2, iclass 4, count 2 2006.257.11:18:28.67#ibcon#flushed, iclass 4, count 2 2006.257.11:18:28.67#ibcon#about to write, iclass 4, count 2 2006.257.11:18:28.67#ibcon#wrote, iclass 4, count 2 2006.257.11:18:28.67#ibcon#about to read 3, iclass 4, count 2 2006.257.11:18:28.70#ibcon#read 3, iclass 4, count 2 2006.257.11:18:28.70#ibcon#about to read 4, iclass 4, count 2 2006.257.11:18:28.70#ibcon#read 4, iclass 4, count 2 2006.257.11:18:28.70#ibcon#about to read 5, iclass 4, count 2 2006.257.11:18:28.70#ibcon#read 5, iclass 4, count 2 2006.257.11:18:28.70#ibcon#about to read 6, iclass 4, count 2 2006.257.11:18:28.70#ibcon#read 6, iclass 4, count 2 2006.257.11:18:28.70#ibcon#end of sib2, iclass 4, count 2 2006.257.11:18:28.70#ibcon#*after write, iclass 4, count 2 2006.257.11:18:28.70#ibcon#*before return 0, iclass 4, count 2 2006.257.11:18:28.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:28.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:28.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.11:18:28.70#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:28.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:28.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:28.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:28.82#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:18:28.82#ibcon#first serial, iclass 4, count 0 2006.257.11:18:28.82#ibcon#enter sib2, iclass 4, count 0 2006.257.11:18:28.82#ibcon#flushed, iclass 4, count 0 2006.257.11:18:28.82#ibcon#about to write, iclass 4, count 0 2006.257.11:18:28.82#ibcon#wrote, iclass 4, count 0 2006.257.11:18:28.82#ibcon#about to read 3, iclass 4, count 0 2006.257.11:18:28.84#ibcon#read 3, iclass 4, count 0 2006.257.11:18:28.84#ibcon#about to read 4, iclass 4, count 0 2006.257.11:18:28.84#ibcon#read 4, iclass 4, count 0 2006.257.11:18:28.84#ibcon#about to read 5, iclass 4, count 0 2006.257.11:18:28.84#ibcon#read 5, iclass 4, count 0 2006.257.11:18:28.84#ibcon#about to read 6, iclass 4, count 0 2006.257.11:18:28.84#ibcon#read 6, iclass 4, count 0 2006.257.11:18:28.84#ibcon#end of sib2, iclass 4, count 0 2006.257.11:18:28.84#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:18:28.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:18:28.84#ibcon#[25=USB\r\n] 2006.257.11:18:28.84#ibcon#*before write, iclass 4, count 0 2006.257.11:18:28.84#ibcon#enter sib2, iclass 4, count 0 2006.257.11:18:28.84#ibcon#flushed, iclass 4, count 0 2006.257.11:18:28.84#ibcon#about to write, iclass 4, count 0 2006.257.11:18:28.84#ibcon#wrote, iclass 4, count 0 2006.257.11:18:28.84#ibcon#about to read 3, iclass 4, count 0 2006.257.11:18:28.87#ibcon#read 3, iclass 4, count 0 2006.257.11:18:28.87#ibcon#about to read 4, iclass 4, count 0 2006.257.11:18:28.87#ibcon#read 4, iclass 4, count 0 2006.257.11:18:28.87#ibcon#about to read 5, iclass 4, count 0 2006.257.11:18:28.87#ibcon#read 5, iclass 4, count 0 2006.257.11:18:28.87#ibcon#about to read 6, iclass 4, count 0 2006.257.11:18:28.87#ibcon#read 6, iclass 4, count 0 2006.257.11:18:28.87#ibcon#end of sib2, iclass 4, count 0 2006.257.11:18:28.87#ibcon#*after write, iclass 4, count 0 2006.257.11:18:28.87#ibcon#*before return 0, iclass 4, count 0 2006.257.11:18:28.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:28.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:28.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:18:28.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:18:28.87$vck44/valo=6,814.99 2006.257.11:18:28.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.11:18:28.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.11:18:28.87#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:28.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:28.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:28.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:28.87#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:18:28.87#ibcon#first serial, iclass 6, count 0 2006.257.11:18:28.87#ibcon#enter sib2, iclass 6, count 0 2006.257.11:18:28.87#ibcon#flushed, iclass 6, count 0 2006.257.11:18:28.87#ibcon#about to write, iclass 6, count 0 2006.257.11:18:28.87#ibcon#wrote, iclass 6, count 0 2006.257.11:18:28.87#ibcon#about to read 3, iclass 6, count 0 2006.257.11:18:28.89#ibcon#read 3, iclass 6, count 0 2006.257.11:18:28.89#ibcon#about to read 4, iclass 6, count 0 2006.257.11:18:28.89#ibcon#read 4, iclass 6, count 0 2006.257.11:18:28.89#ibcon#about to read 5, iclass 6, count 0 2006.257.11:18:28.89#ibcon#read 5, iclass 6, count 0 2006.257.11:18:28.89#ibcon#about to read 6, iclass 6, count 0 2006.257.11:18:28.89#ibcon#read 6, iclass 6, count 0 2006.257.11:18:28.89#ibcon#end of sib2, iclass 6, count 0 2006.257.11:18:28.89#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:18:28.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:18:28.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:18:28.89#ibcon#*before write, iclass 6, count 0 2006.257.11:18:28.89#ibcon#enter sib2, iclass 6, count 0 2006.257.11:18:28.89#ibcon#flushed, iclass 6, count 0 2006.257.11:18:28.89#ibcon#about to write, iclass 6, count 0 2006.257.11:18:28.89#ibcon#wrote, iclass 6, count 0 2006.257.11:18:28.89#ibcon#about to read 3, iclass 6, count 0 2006.257.11:18:28.93#ibcon#read 3, iclass 6, count 0 2006.257.11:18:28.93#ibcon#about to read 4, iclass 6, count 0 2006.257.11:18:28.93#ibcon#read 4, iclass 6, count 0 2006.257.11:18:28.93#ibcon#about to read 5, iclass 6, count 0 2006.257.11:18:28.93#ibcon#read 5, iclass 6, count 0 2006.257.11:18:28.93#ibcon#about to read 6, iclass 6, count 0 2006.257.11:18:28.93#ibcon#read 6, iclass 6, count 0 2006.257.11:18:28.93#ibcon#end of sib2, iclass 6, count 0 2006.257.11:18:28.93#ibcon#*after write, iclass 6, count 0 2006.257.11:18:28.93#ibcon#*before return 0, iclass 6, count 0 2006.257.11:18:28.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:28.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:28.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:18:28.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:18:28.93$vck44/va=6,4 2006.257.11:18:28.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.11:18:28.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.11:18:28.93#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:28.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:28.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:28.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:28.99#ibcon#enter wrdev, iclass 10, count 2 2006.257.11:18:28.99#ibcon#first serial, iclass 10, count 2 2006.257.11:18:28.99#ibcon#enter sib2, iclass 10, count 2 2006.257.11:18:28.99#ibcon#flushed, iclass 10, count 2 2006.257.11:18:28.99#ibcon#about to write, iclass 10, count 2 2006.257.11:18:28.99#ibcon#wrote, iclass 10, count 2 2006.257.11:18:28.99#ibcon#about to read 3, iclass 10, count 2 2006.257.11:18:29.01#ibcon#read 3, iclass 10, count 2 2006.257.11:18:29.01#ibcon#about to read 4, iclass 10, count 2 2006.257.11:18:29.01#ibcon#read 4, iclass 10, count 2 2006.257.11:18:29.01#ibcon#about to read 5, iclass 10, count 2 2006.257.11:18:29.01#ibcon#read 5, iclass 10, count 2 2006.257.11:18:29.01#ibcon#about to read 6, iclass 10, count 2 2006.257.11:18:29.01#ibcon#read 6, iclass 10, count 2 2006.257.11:18:29.01#ibcon#end of sib2, iclass 10, count 2 2006.257.11:18:29.01#ibcon#*mode == 0, iclass 10, count 2 2006.257.11:18:29.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.11:18:29.01#ibcon#[25=AT06-04\r\n] 2006.257.11:18:29.01#ibcon#*before write, iclass 10, count 2 2006.257.11:18:29.01#ibcon#enter sib2, iclass 10, count 2 2006.257.11:18:29.01#ibcon#flushed, iclass 10, count 2 2006.257.11:18:29.01#ibcon#about to write, iclass 10, count 2 2006.257.11:18:29.01#ibcon#wrote, iclass 10, count 2 2006.257.11:18:29.01#ibcon#about to read 3, iclass 10, count 2 2006.257.11:18:29.04#ibcon#read 3, iclass 10, count 2 2006.257.11:18:29.04#ibcon#about to read 4, iclass 10, count 2 2006.257.11:18:29.04#ibcon#read 4, iclass 10, count 2 2006.257.11:18:29.04#ibcon#about to read 5, iclass 10, count 2 2006.257.11:18:29.04#ibcon#read 5, iclass 10, count 2 2006.257.11:18:29.04#ibcon#about to read 6, iclass 10, count 2 2006.257.11:18:29.04#ibcon#read 6, iclass 10, count 2 2006.257.11:18:29.04#ibcon#end of sib2, iclass 10, count 2 2006.257.11:18:29.04#ibcon#*after write, iclass 10, count 2 2006.257.11:18:29.04#ibcon#*before return 0, iclass 10, count 2 2006.257.11:18:29.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:29.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:29.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.11:18:29.04#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:29.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:29.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:29.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:29.16#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:18:29.16#ibcon#first serial, iclass 10, count 0 2006.257.11:18:29.16#ibcon#enter sib2, iclass 10, count 0 2006.257.11:18:29.16#ibcon#flushed, iclass 10, count 0 2006.257.11:18:29.16#ibcon#about to write, iclass 10, count 0 2006.257.11:18:29.16#ibcon#wrote, iclass 10, count 0 2006.257.11:18:29.16#ibcon#about to read 3, iclass 10, count 0 2006.257.11:18:29.18#ibcon#read 3, iclass 10, count 0 2006.257.11:18:29.18#ibcon#about to read 4, iclass 10, count 0 2006.257.11:18:29.18#ibcon#read 4, iclass 10, count 0 2006.257.11:18:29.18#ibcon#about to read 5, iclass 10, count 0 2006.257.11:18:29.18#ibcon#read 5, iclass 10, count 0 2006.257.11:18:29.18#ibcon#about to read 6, iclass 10, count 0 2006.257.11:18:29.18#ibcon#read 6, iclass 10, count 0 2006.257.11:18:29.18#ibcon#end of sib2, iclass 10, count 0 2006.257.11:18:29.18#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:18:29.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:18:29.18#ibcon#[25=USB\r\n] 2006.257.11:18:29.18#ibcon#*before write, iclass 10, count 0 2006.257.11:18:29.18#ibcon#enter sib2, iclass 10, count 0 2006.257.11:18:29.18#ibcon#flushed, iclass 10, count 0 2006.257.11:18:29.18#ibcon#about to write, iclass 10, count 0 2006.257.11:18:29.18#ibcon#wrote, iclass 10, count 0 2006.257.11:18:29.18#ibcon#about to read 3, iclass 10, count 0 2006.257.11:18:29.21#ibcon#read 3, iclass 10, count 0 2006.257.11:18:29.21#ibcon#about to read 4, iclass 10, count 0 2006.257.11:18:29.21#ibcon#read 4, iclass 10, count 0 2006.257.11:18:29.21#ibcon#about to read 5, iclass 10, count 0 2006.257.11:18:29.21#ibcon#read 5, iclass 10, count 0 2006.257.11:18:29.21#ibcon#about to read 6, iclass 10, count 0 2006.257.11:18:29.21#ibcon#read 6, iclass 10, count 0 2006.257.11:18:29.21#ibcon#end of sib2, iclass 10, count 0 2006.257.11:18:29.21#ibcon#*after write, iclass 10, count 0 2006.257.11:18:29.21#ibcon#*before return 0, iclass 10, count 0 2006.257.11:18:29.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:29.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:29.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:18:29.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:18:29.21$vck44/valo=7,864.99 2006.257.11:18:29.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.11:18:29.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.11:18:29.21#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:29.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:29.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:29.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:29.21#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:18:29.21#ibcon#first serial, iclass 12, count 0 2006.257.11:18:29.21#ibcon#enter sib2, iclass 12, count 0 2006.257.11:18:29.21#ibcon#flushed, iclass 12, count 0 2006.257.11:18:29.21#ibcon#about to write, iclass 12, count 0 2006.257.11:18:29.21#ibcon#wrote, iclass 12, count 0 2006.257.11:18:29.21#ibcon#about to read 3, iclass 12, count 0 2006.257.11:18:29.23#ibcon#read 3, iclass 12, count 0 2006.257.11:18:29.23#ibcon#about to read 4, iclass 12, count 0 2006.257.11:18:29.23#ibcon#read 4, iclass 12, count 0 2006.257.11:18:29.23#ibcon#about to read 5, iclass 12, count 0 2006.257.11:18:29.23#ibcon#read 5, iclass 12, count 0 2006.257.11:18:29.23#ibcon#about to read 6, iclass 12, count 0 2006.257.11:18:29.23#ibcon#read 6, iclass 12, count 0 2006.257.11:18:29.23#ibcon#end of sib2, iclass 12, count 0 2006.257.11:18:29.23#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:18:29.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:18:29.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:18:29.23#ibcon#*before write, iclass 12, count 0 2006.257.11:18:29.23#ibcon#enter sib2, iclass 12, count 0 2006.257.11:18:29.23#ibcon#flushed, iclass 12, count 0 2006.257.11:18:29.23#ibcon#about to write, iclass 12, count 0 2006.257.11:18:29.23#ibcon#wrote, iclass 12, count 0 2006.257.11:18:29.23#ibcon#about to read 3, iclass 12, count 0 2006.257.11:18:29.27#ibcon#read 3, iclass 12, count 0 2006.257.11:18:29.27#ibcon#about to read 4, iclass 12, count 0 2006.257.11:18:29.27#ibcon#read 4, iclass 12, count 0 2006.257.11:18:29.27#ibcon#about to read 5, iclass 12, count 0 2006.257.11:18:29.27#ibcon#read 5, iclass 12, count 0 2006.257.11:18:29.27#ibcon#about to read 6, iclass 12, count 0 2006.257.11:18:29.27#ibcon#read 6, iclass 12, count 0 2006.257.11:18:29.27#ibcon#end of sib2, iclass 12, count 0 2006.257.11:18:29.27#ibcon#*after write, iclass 12, count 0 2006.257.11:18:29.27#ibcon#*before return 0, iclass 12, count 0 2006.257.11:18:29.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:29.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:29.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:18:29.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:18:29.27$vck44/va=7,4 2006.257.11:18:29.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.11:18:29.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.11:18:29.27#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:29.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:29.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:29.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:29.33#ibcon#enter wrdev, iclass 14, count 2 2006.257.11:18:29.33#ibcon#first serial, iclass 14, count 2 2006.257.11:18:29.33#ibcon#enter sib2, iclass 14, count 2 2006.257.11:18:29.33#ibcon#flushed, iclass 14, count 2 2006.257.11:18:29.33#ibcon#about to write, iclass 14, count 2 2006.257.11:18:29.33#ibcon#wrote, iclass 14, count 2 2006.257.11:18:29.33#ibcon#about to read 3, iclass 14, count 2 2006.257.11:18:29.35#ibcon#read 3, iclass 14, count 2 2006.257.11:18:29.35#ibcon#about to read 4, iclass 14, count 2 2006.257.11:18:29.35#ibcon#read 4, iclass 14, count 2 2006.257.11:18:29.35#ibcon#about to read 5, iclass 14, count 2 2006.257.11:18:29.35#ibcon#read 5, iclass 14, count 2 2006.257.11:18:29.35#ibcon#about to read 6, iclass 14, count 2 2006.257.11:18:29.35#ibcon#read 6, iclass 14, count 2 2006.257.11:18:29.35#ibcon#end of sib2, iclass 14, count 2 2006.257.11:18:29.35#ibcon#*mode == 0, iclass 14, count 2 2006.257.11:18:29.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.11:18:29.35#ibcon#[25=AT07-04\r\n] 2006.257.11:18:29.35#ibcon#*before write, iclass 14, count 2 2006.257.11:18:29.35#ibcon#enter sib2, iclass 14, count 2 2006.257.11:18:29.35#ibcon#flushed, iclass 14, count 2 2006.257.11:18:29.35#ibcon#about to write, iclass 14, count 2 2006.257.11:18:29.35#ibcon#wrote, iclass 14, count 2 2006.257.11:18:29.35#ibcon#about to read 3, iclass 14, count 2 2006.257.11:18:29.38#ibcon#read 3, iclass 14, count 2 2006.257.11:18:29.38#ibcon#about to read 4, iclass 14, count 2 2006.257.11:18:29.38#ibcon#read 4, iclass 14, count 2 2006.257.11:18:29.38#ibcon#about to read 5, iclass 14, count 2 2006.257.11:18:29.38#ibcon#read 5, iclass 14, count 2 2006.257.11:18:29.38#ibcon#about to read 6, iclass 14, count 2 2006.257.11:18:29.38#ibcon#read 6, iclass 14, count 2 2006.257.11:18:29.38#ibcon#end of sib2, iclass 14, count 2 2006.257.11:18:29.38#ibcon#*after write, iclass 14, count 2 2006.257.11:18:29.38#ibcon#*before return 0, iclass 14, count 2 2006.257.11:18:29.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:29.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:29.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.11:18:29.38#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:29.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:29.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:29.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:29.50#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:18:29.50#ibcon#first serial, iclass 14, count 0 2006.257.11:18:29.50#ibcon#enter sib2, iclass 14, count 0 2006.257.11:18:29.50#ibcon#flushed, iclass 14, count 0 2006.257.11:18:29.50#ibcon#about to write, iclass 14, count 0 2006.257.11:18:29.50#ibcon#wrote, iclass 14, count 0 2006.257.11:18:29.50#ibcon#about to read 3, iclass 14, count 0 2006.257.11:18:29.52#ibcon#read 3, iclass 14, count 0 2006.257.11:18:29.52#ibcon#about to read 4, iclass 14, count 0 2006.257.11:18:29.52#ibcon#read 4, iclass 14, count 0 2006.257.11:18:29.52#ibcon#about to read 5, iclass 14, count 0 2006.257.11:18:29.52#ibcon#read 5, iclass 14, count 0 2006.257.11:18:29.52#ibcon#about to read 6, iclass 14, count 0 2006.257.11:18:29.52#ibcon#read 6, iclass 14, count 0 2006.257.11:18:29.52#ibcon#end of sib2, iclass 14, count 0 2006.257.11:18:29.52#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:18:29.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:18:29.52#ibcon#[25=USB\r\n] 2006.257.11:18:29.52#ibcon#*before write, iclass 14, count 0 2006.257.11:18:29.52#ibcon#enter sib2, iclass 14, count 0 2006.257.11:18:29.52#ibcon#flushed, iclass 14, count 0 2006.257.11:18:29.52#ibcon#about to write, iclass 14, count 0 2006.257.11:18:29.52#ibcon#wrote, iclass 14, count 0 2006.257.11:18:29.52#ibcon#about to read 3, iclass 14, count 0 2006.257.11:18:29.55#ibcon#read 3, iclass 14, count 0 2006.257.11:18:29.55#ibcon#about to read 4, iclass 14, count 0 2006.257.11:18:29.55#ibcon#read 4, iclass 14, count 0 2006.257.11:18:29.55#ibcon#about to read 5, iclass 14, count 0 2006.257.11:18:29.55#ibcon#read 5, iclass 14, count 0 2006.257.11:18:29.55#ibcon#about to read 6, iclass 14, count 0 2006.257.11:18:29.55#ibcon#read 6, iclass 14, count 0 2006.257.11:18:29.55#ibcon#end of sib2, iclass 14, count 0 2006.257.11:18:29.55#ibcon#*after write, iclass 14, count 0 2006.257.11:18:29.55#ibcon#*before return 0, iclass 14, count 0 2006.257.11:18:29.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:29.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:29.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:18:29.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:18:29.55$vck44/valo=8,884.99 2006.257.11:18:29.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.11:18:29.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.11:18:29.55#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:29.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:29.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:29.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:29.55#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:18:29.55#ibcon#first serial, iclass 16, count 0 2006.257.11:18:29.55#ibcon#enter sib2, iclass 16, count 0 2006.257.11:18:29.55#ibcon#flushed, iclass 16, count 0 2006.257.11:18:29.55#ibcon#about to write, iclass 16, count 0 2006.257.11:18:29.55#ibcon#wrote, iclass 16, count 0 2006.257.11:18:29.55#ibcon#about to read 3, iclass 16, count 0 2006.257.11:18:29.57#ibcon#read 3, iclass 16, count 0 2006.257.11:18:29.57#ibcon#about to read 4, iclass 16, count 0 2006.257.11:18:29.57#ibcon#read 4, iclass 16, count 0 2006.257.11:18:29.57#ibcon#about to read 5, iclass 16, count 0 2006.257.11:18:29.57#ibcon#read 5, iclass 16, count 0 2006.257.11:18:29.57#ibcon#about to read 6, iclass 16, count 0 2006.257.11:18:29.57#ibcon#read 6, iclass 16, count 0 2006.257.11:18:29.57#ibcon#end of sib2, iclass 16, count 0 2006.257.11:18:29.57#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:18:29.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:18:29.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:18:29.57#ibcon#*before write, iclass 16, count 0 2006.257.11:18:29.57#ibcon#enter sib2, iclass 16, count 0 2006.257.11:18:29.57#ibcon#flushed, iclass 16, count 0 2006.257.11:18:29.57#ibcon#about to write, iclass 16, count 0 2006.257.11:18:29.57#ibcon#wrote, iclass 16, count 0 2006.257.11:18:29.57#ibcon#about to read 3, iclass 16, count 0 2006.257.11:18:29.61#ibcon#read 3, iclass 16, count 0 2006.257.11:18:29.61#ibcon#about to read 4, iclass 16, count 0 2006.257.11:18:29.61#ibcon#read 4, iclass 16, count 0 2006.257.11:18:29.61#ibcon#about to read 5, iclass 16, count 0 2006.257.11:18:29.61#ibcon#read 5, iclass 16, count 0 2006.257.11:18:29.61#ibcon#about to read 6, iclass 16, count 0 2006.257.11:18:29.61#ibcon#read 6, iclass 16, count 0 2006.257.11:18:29.61#ibcon#end of sib2, iclass 16, count 0 2006.257.11:18:29.61#ibcon#*after write, iclass 16, count 0 2006.257.11:18:29.61#ibcon#*before return 0, iclass 16, count 0 2006.257.11:18:29.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:29.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:29.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:18:29.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:18:29.61$vck44/va=8,4 2006.257.11:18:29.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.11:18:29.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.11:18:29.61#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:29.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:18:29.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:18:29.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:18:29.67#ibcon#enter wrdev, iclass 18, count 2 2006.257.11:18:29.67#ibcon#first serial, iclass 18, count 2 2006.257.11:18:29.67#ibcon#enter sib2, iclass 18, count 2 2006.257.11:18:29.67#ibcon#flushed, iclass 18, count 2 2006.257.11:18:29.67#ibcon#about to write, iclass 18, count 2 2006.257.11:18:29.67#ibcon#wrote, iclass 18, count 2 2006.257.11:18:29.67#ibcon#about to read 3, iclass 18, count 2 2006.257.11:18:29.69#ibcon#read 3, iclass 18, count 2 2006.257.11:18:29.69#ibcon#about to read 4, iclass 18, count 2 2006.257.11:18:29.69#ibcon#read 4, iclass 18, count 2 2006.257.11:18:29.69#ibcon#about to read 5, iclass 18, count 2 2006.257.11:18:29.69#ibcon#read 5, iclass 18, count 2 2006.257.11:18:29.69#ibcon#about to read 6, iclass 18, count 2 2006.257.11:18:29.69#ibcon#read 6, iclass 18, count 2 2006.257.11:18:29.69#ibcon#end of sib2, iclass 18, count 2 2006.257.11:18:29.69#ibcon#*mode == 0, iclass 18, count 2 2006.257.11:18:29.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.11:18:29.69#ibcon#[25=AT08-04\r\n] 2006.257.11:18:29.69#ibcon#*before write, iclass 18, count 2 2006.257.11:18:29.69#ibcon#enter sib2, iclass 18, count 2 2006.257.11:18:29.69#ibcon#flushed, iclass 18, count 2 2006.257.11:18:29.69#ibcon#about to write, iclass 18, count 2 2006.257.11:18:29.69#ibcon#wrote, iclass 18, count 2 2006.257.11:18:29.69#ibcon#about to read 3, iclass 18, count 2 2006.257.11:18:29.72#ibcon#read 3, iclass 18, count 2 2006.257.11:18:29.72#ibcon#about to read 4, iclass 18, count 2 2006.257.11:18:29.72#ibcon#read 4, iclass 18, count 2 2006.257.11:18:29.72#ibcon#about to read 5, iclass 18, count 2 2006.257.11:18:29.72#ibcon#read 5, iclass 18, count 2 2006.257.11:18:29.72#ibcon#about to read 6, iclass 18, count 2 2006.257.11:18:29.72#ibcon#read 6, iclass 18, count 2 2006.257.11:18:29.72#ibcon#end of sib2, iclass 18, count 2 2006.257.11:18:29.72#ibcon#*after write, iclass 18, count 2 2006.257.11:18:29.72#ibcon#*before return 0, iclass 18, count 2 2006.257.11:18:29.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:18:29.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:18:29.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.11:18:29.72#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:29.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:18:29.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:18:29.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:18:29.84#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:18:29.84#ibcon#first serial, iclass 18, count 0 2006.257.11:18:29.84#ibcon#enter sib2, iclass 18, count 0 2006.257.11:18:29.84#ibcon#flushed, iclass 18, count 0 2006.257.11:18:29.84#ibcon#about to write, iclass 18, count 0 2006.257.11:18:29.84#ibcon#wrote, iclass 18, count 0 2006.257.11:18:29.84#ibcon#about to read 3, iclass 18, count 0 2006.257.11:18:29.86#ibcon#read 3, iclass 18, count 0 2006.257.11:18:29.86#ibcon#about to read 4, iclass 18, count 0 2006.257.11:18:29.86#ibcon#read 4, iclass 18, count 0 2006.257.11:18:29.86#ibcon#about to read 5, iclass 18, count 0 2006.257.11:18:29.86#ibcon#read 5, iclass 18, count 0 2006.257.11:18:29.86#ibcon#about to read 6, iclass 18, count 0 2006.257.11:18:29.86#ibcon#read 6, iclass 18, count 0 2006.257.11:18:29.86#ibcon#end of sib2, iclass 18, count 0 2006.257.11:18:29.86#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:18:29.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:18:29.86#ibcon#[25=USB\r\n] 2006.257.11:18:29.86#ibcon#*before write, iclass 18, count 0 2006.257.11:18:29.86#ibcon#enter sib2, iclass 18, count 0 2006.257.11:18:29.86#ibcon#flushed, iclass 18, count 0 2006.257.11:18:29.86#ibcon#about to write, iclass 18, count 0 2006.257.11:18:29.86#ibcon#wrote, iclass 18, count 0 2006.257.11:18:29.86#ibcon#about to read 3, iclass 18, count 0 2006.257.11:18:29.89#ibcon#read 3, iclass 18, count 0 2006.257.11:18:29.89#ibcon#about to read 4, iclass 18, count 0 2006.257.11:18:29.89#ibcon#read 4, iclass 18, count 0 2006.257.11:18:29.89#ibcon#about to read 5, iclass 18, count 0 2006.257.11:18:29.89#ibcon#read 5, iclass 18, count 0 2006.257.11:18:29.89#ibcon#about to read 6, iclass 18, count 0 2006.257.11:18:29.89#ibcon#read 6, iclass 18, count 0 2006.257.11:18:29.89#ibcon#end of sib2, iclass 18, count 0 2006.257.11:18:29.89#ibcon#*after write, iclass 18, count 0 2006.257.11:18:29.89#ibcon#*before return 0, iclass 18, count 0 2006.257.11:18:29.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:18:29.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:18:29.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:18:29.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:18:29.89$vck44/vblo=1,629.99 2006.257.11:18:29.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.11:18:29.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.11:18:29.89#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:29.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:29.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:29.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:29.89#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:18:29.89#ibcon#first serial, iclass 20, count 0 2006.257.11:18:29.89#ibcon#enter sib2, iclass 20, count 0 2006.257.11:18:29.89#ibcon#flushed, iclass 20, count 0 2006.257.11:18:29.89#ibcon#about to write, iclass 20, count 0 2006.257.11:18:29.89#ibcon#wrote, iclass 20, count 0 2006.257.11:18:29.89#ibcon#about to read 3, iclass 20, count 0 2006.257.11:18:29.91#ibcon#read 3, iclass 20, count 0 2006.257.11:18:29.91#ibcon#about to read 4, iclass 20, count 0 2006.257.11:18:29.91#ibcon#read 4, iclass 20, count 0 2006.257.11:18:29.91#ibcon#about to read 5, iclass 20, count 0 2006.257.11:18:29.91#ibcon#read 5, iclass 20, count 0 2006.257.11:18:29.91#ibcon#about to read 6, iclass 20, count 0 2006.257.11:18:29.91#ibcon#read 6, iclass 20, count 0 2006.257.11:18:29.91#ibcon#end of sib2, iclass 20, count 0 2006.257.11:18:29.91#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:18:29.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:18:29.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:18:29.91#ibcon#*before write, iclass 20, count 0 2006.257.11:18:29.91#ibcon#enter sib2, iclass 20, count 0 2006.257.11:18:29.91#ibcon#flushed, iclass 20, count 0 2006.257.11:18:29.91#ibcon#about to write, iclass 20, count 0 2006.257.11:18:29.91#ibcon#wrote, iclass 20, count 0 2006.257.11:18:29.91#ibcon#about to read 3, iclass 20, count 0 2006.257.11:18:29.95#ibcon#read 3, iclass 20, count 0 2006.257.11:18:29.95#ibcon#about to read 4, iclass 20, count 0 2006.257.11:18:29.95#ibcon#read 4, iclass 20, count 0 2006.257.11:18:29.95#ibcon#about to read 5, iclass 20, count 0 2006.257.11:18:29.95#ibcon#read 5, iclass 20, count 0 2006.257.11:18:29.95#ibcon#about to read 6, iclass 20, count 0 2006.257.11:18:29.95#ibcon#read 6, iclass 20, count 0 2006.257.11:18:29.95#ibcon#end of sib2, iclass 20, count 0 2006.257.11:18:29.95#ibcon#*after write, iclass 20, count 0 2006.257.11:18:29.95#ibcon#*before return 0, iclass 20, count 0 2006.257.11:18:29.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:29.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:18:29.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:18:29.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:18:29.95$vck44/vb=1,4 2006.257.11:18:29.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.11:18:29.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.11:18:29.95#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:29.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:29.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:29.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:29.95#ibcon#enter wrdev, iclass 22, count 2 2006.257.11:18:29.95#ibcon#first serial, iclass 22, count 2 2006.257.11:18:29.95#ibcon#enter sib2, iclass 22, count 2 2006.257.11:18:29.95#ibcon#flushed, iclass 22, count 2 2006.257.11:18:29.95#ibcon#about to write, iclass 22, count 2 2006.257.11:18:29.95#ibcon#wrote, iclass 22, count 2 2006.257.11:18:29.95#ibcon#about to read 3, iclass 22, count 2 2006.257.11:18:29.97#ibcon#read 3, iclass 22, count 2 2006.257.11:18:29.97#ibcon#about to read 4, iclass 22, count 2 2006.257.11:18:29.97#ibcon#read 4, iclass 22, count 2 2006.257.11:18:29.97#ibcon#about to read 5, iclass 22, count 2 2006.257.11:18:29.97#ibcon#read 5, iclass 22, count 2 2006.257.11:18:29.97#ibcon#about to read 6, iclass 22, count 2 2006.257.11:18:29.97#ibcon#read 6, iclass 22, count 2 2006.257.11:18:29.97#ibcon#end of sib2, iclass 22, count 2 2006.257.11:18:29.97#ibcon#*mode == 0, iclass 22, count 2 2006.257.11:18:29.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.11:18:29.97#ibcon#[27=AT01-04\r\n] 2006.257.11:18:29.97#ibcon#*before write, iclass 22, count 2 2006.257.11:18:29.97#ibcon#enter sib2, iclass 22, count 2 2006.257.11:18:29.97#ibcon#flushed, iclass 22, count 2 2006.257.11:18:29.97#ibcon#about to write, iclass 22, count 2 2006.257.11:18:29.97#ibcon#wrote, iclass 22, count 2 2006.257.11:18:29.97#ibcon#about to read 3, iclass 22, count 2 2006.257.11:18:30.00#ibcon#read 3, iclass 22, count 2 2006.257.11:18:30.00#ibcon#about to read 4, iclass 22, count 2 2006.257.11:18:30.00#ibcon#read 4, iclass 22, count 2 2006.257.11:18:30.00#ibcon#about to read 5, iclass 22, count 2 2006.257.11:18:30.00#ibcon#read 5, iclass 22, count 2 2006.257.11:18:30.00#ibcon#about to read 6, iclass 22, count 2 2006.257.11:18:30.00#ibcon#read 6, iclass 22, count 2 2006.257.11:18:30.00#ibcon#end of sib2, iclass 22, count 2 2006.257.11:18:30.00#ibcon#*after write, iclass 22, count 2 2006.257.11:18:30.00#ibcon#*before return 0, iclass 22, count 2 2006.257.11:18:30.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:30.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:18:30.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.11:18:30.00#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:30.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:30.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:30.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:30.12#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:18:30.12#ibcon#first serial, iclass 22, count 0 2006.257.11:18:30.12#ibcon#enter sib2, iclass 22, count 0 2006.257.11:18:30.12#ibcon#flushed, iclass 22, count 0 2006.257.11:18:30.12#ibcon#about to write, iclass 22, count 0 2006.257.11:18:30.12#ibcon#wrote, iclass 22, count 0 2006.257.11:18:30.12#ibcon#about to read 3, iclass 22, count 0 2006.257.11:18:30.14#ibcon#read 3, iclass 22, count 0 2006.257.11:18:30.14#ibcon#about to read 4, iclass 22, count 0 2006.257.11:18:30.14#ibcon#read 4, iclass 22, count 0 2006.257.11:18:30.14#ibcon#about to read 5, iclass 22, count 0 2006.257.11:18:30.14#ibcon#read 5, iclass 22, count 0 2006.257.11:18:30.14#ibcon#about to read 6, iclass 22, count 0 2006.257.11:18:30.14#ibcon#read 6, iclass 22, count 0 2006.257.11:18:30.14#ibcon#end of sib2, iclass 22, count 0 2006.257.11:18:30.14#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:18:30.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:18:30.14#ibcon#[27=USB\r\n] 2006.257.11:18:30.14#ibcon#*before write, iclass 22, count 0 2006.257.11:18:30.14#ibcon#enter sib2, iclass 22, count 0 2006.257.11:18:30.14#ibcon#flushed, iclass 22, count 0 2006.257.11:18:30.14#ibcon#about to write, iclass 22, count 0 2006.257.11:18:30.14#ibcon#wrote, iclass 22, count 0 2006.257.11:18:30.14#ibcon#about to read 3, iclass 22, count 0 2006.257.11:18:30.17#ibcon#read 3, iclass 22, count 0 2006.257.11:18:30.17#ibcon#about to read 4, iclass 22, count 0 2006.257.11:18:30.17#ibcon#read 4, iclass 22, count 0 2006.257.11:18:30.17#ibcon#about to read 5, iclass 22, count 0 2006.257.11:18:30.17#ibcon#read 5, iclass 22, count 0 2006.257.11:18:30.17#ibcon#about to read 6, iclass 22, count 0 2006.257.11:18:30.17#ibcon#read 6, iclass 22, count 0 2006.257.11:18:30.17#ibcon#end of sib2, iclass 22, count 0 2006.257.11:18:30.17#ibcon#*after write, iclass 22, count 0 2006.257.11:18:30.17#ibcon#*before return 0, iclass 22, count 0 2006.257.11:18:30.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:30.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:18:30.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:18:30.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:18:30.17$vck44/vblo=2,634.99 2006.257.11:18:30.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.11:18:30.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.11:18:30.17#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:30.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:30.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:30.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:30.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:18:30.17#ibcon#first serial, iclass 24, count 0 2006.257.11:18:30.17#ibcon#enter sib2, iclass 24, count 0 2006.257.11:18:30.17#ibcon#flushed, iclass 24, count 0 2006.257.11:18:30.17#ibcon#about to write, iclass 24, count 0 2006.257.11:18:30.17#ibcon#wrote, iclass 24, count 0 2006.257.11:18:30.17#ibcon#about to read 3, iclass 24, count 0 2006.257.11:18:30.19#ibcon#read 3, iclass 24, count 0 2006.257.11:18:30.19#ibcon#about to read 4, iclass 24, count 0 2006.257.11:18:30.19#ibcon#read 4, iclass 24, count 0 2006.257.11:18:30.19#ibcon#about to read 5, iclass 24, count 0 2006.257.11:18:30.19#ibcon#read 5, iclass 24, count 0 2006.257.11:18:30.19#ibcon#about to read 6, iclass 24, count 0 2006.257.11:18:30.19#ibcon#read 6, iclass 24, count 0 2006.257.11:18:30.19#ibcon#end of sib2, iclass 24, count 0 2006.257.11:18:30.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:18:30.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:18:30.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:18:30.19#ibcon#*before write, iclass 24, count 0 2006.257.11:18:30.19#ibcon#enter sib2, iclass 24, count 0 2006.257.11:18:30.19#ibcon#flushed, iclass 24, count 0 2006.257.11:18:30.19#ibcon#about to write, iclass 24, count 0 2006.257.11:18:30.19#ibcon#wrote, iclass 24, count 0 2006.257.11:18:30.19#ibcon#about to read 3, iclass 24, count 0 2006.257.11:18:30.23#ibcon#read 3, iclass 24, count 0 2006.257.11:18:30.23#ibcon#about to read 4, iclass 24, count 0 2006.257.11:18:30.23#ibcon#read 4, iclass 24, count 0 2006.257.11:18:30.23#ibcon#about to read 5, iclass 24, count 0 2006.257.11:18:30.23#ibcon#read 5, iclass 24, count 0 2006.257.11:18:30.23#ibcon#about to read 6, iclass 24, count 0 2006.257.11:18:30.23#ibcon#read 6, iclass 24, count 0 2006.257.11:18:30.23#ibcon#end of sib2, iclass 24, count 0 2006.257.11:18:30.23#ibcon#*after write, iclass 24, count 0 2006.257.11:18:30.23#ibcon#*before return 0, iclass 24, count 0 2006.257.11:18:30.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:30.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:18:30.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:18:30.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:18:30.23$vck44/vb=2,5 2006.257.11:18:30.23#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.11:18:30.23#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.11:18:30.23#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:30.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:30.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:30.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:30.29#ibcon#enter wrdev, iclass 26, count 2 2006.257.11:18:30.29#ibcon#first serial, iclass 26, count 2 2006.257.11:18:30.29#ibcon#enter sib2, iclass 26, count 2 2006.257.11:18:30.29#ibcon#flushed, iclass 26, count 2 2006.257.11:18:30.29#ibcon#about to write, iclass 26, count 2 2006.257.11:18:30.29#ibcon#wrote, iclass 26, count 2 2006.257.11:18:30.29#ibcon#about to read 3, iclass 26, count 2 2006.257.11:18:30.31#ibcon#read 3, iclass 26, count 2 2006.257.11:18:30.31#ibcon#about to read 4, iclass 26, count 2 2006.257.11:18:30.31#ibcon#read 4, iclass 26, count 2 2006.257.11:18:30.31#ibcon#about to read 5, iclass 26, count 2 2006.257.11:18:30.31#ibcon#read 5, iclass 26, count 2 2006.257.11:18:30.31#ibcon#about to read 6, iclass 26, count 2 2006.257.11:18:30.31#ibcon#read 6, iclass 26, count 2 2006.257.11:18:30.31#ibcon#end of sib2, iclass 26, count 2 2006.257.11:18:30.31#ibcon#*mode == 0, iclass 26, count 2 2006.257.11:18:30.31#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.11:18:30.31#ibcon#[27=AT02-05\r\n] 2006.257.11:18:30.31#ibcon#*before write, iclass 26, count 2 2006.257.11:18:30.31#ibcon#enter sib2, iclass 26, count 2 2006.257.11:18:30.31#ibcon#flushed, iclass 26, count 2 2006.257.11:18:30.31#ibcon#about to write, iclass 26, count 2 2006.257.11:18:30.31#ibcon#wrote, iclass 26, count 2 2006.257.11:18:30.31#ibcon#about to read 3, iclass 26, count 2 2006.257.11:18:30.34#ibcon#read 3, iclass 26, count 2 2006.257.11:18:30.40#ibcon#about to read 4, iclass 26, count 2 2006.257.11:18:30.40#ibcon#read 4, iclass 26, count 2 2006.257.11:18:30.41#ibcon#about to read 5, iclass 26, count 2 2006.257.11:18:30.41#ibcon#read 5, iclass 26, count 2 2006.257.11:18:30.41#ibcon#about to read 6, iclass 26, count 2 2006.257.11:18:30.41#ibcon#read 6, iclass 26, count 2 2006.257.11:18:30.41#ibcon#end of sib2, iclass 26, count 2 2006.257.11:18:30.41#ibcon#*after write, iclass 26, count 2 2006.257.11:18:30.41#ibcon#*before return 0, iclass 26, count 2 2006.257.11:18:30.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:30.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:18:30.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.11:18:30.41#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:30.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:30.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:30.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:30.53#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:18:30.53#ibcon#first serial, iclass 26, count 0 2006.257.11:18:30.53#ibcon#enter sib2, iclass 26, count 0 2006.257.11:18:30.53#ibcon#flushed, iclass 26, count 0 2006.257.11:18:30.53#ibcon#about to write, iclass 26, count 0 2006.257.11:18:30.53#ibcon#wrote, iclass 26, count 0 2006.257.11:18:30.53#ibcon#about to read 3, iclass 26, count 0 2006.257.11:18:30.55#ibcon#read 3, iclass 26, count 0 2006.257.11:18:30.55#ibcon#about to read 4, iclass 26, count 0 2006.257.11:18:30.55#ibcon#read 4, iclass 26, count 0 2006.257.11:18:30.55#ibcon#about to read 5, iclass 26, count 0 2006.257.11:18:30.55#ibcon#read 5, iclass 26, count 0 2006.257.11:18:30.55#ibcon#about to read 6, iclass 26, count 0 2006.257.11:18:30.55#ibcon#read 6, iclass 26, count 0 2006.257.11:18:30.55#ibcon#end of sib2, iclass 26, count 0 2006.257.11:18:30.55#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:18:30.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:18:30.55#ibcon#[27=USB\r\n] 2006.257.11:18:30.55#ibcon#*before write, iclass 26, count 0 2006.257.11:18:30.55#ibcon#enter sib2, iclass 26, count 0 2006.257.11:18:30.55#ibcon#flushed, iclass 26, count 0 2006.257.11:18:30.55#ibcon#about to write, iclass 26, count 0 2006.257.11:18:30.55#ibcon#wrote, iclass 26, count 0 2006.257.11:18:30.55#ibcon#about to read 3, iclass 26, count 0 2006.257.11:18:30.58#ibcon#read 3, iclass 26, count 0 2006.257.11:18:30.58#ibcon#about to read 4, iclass 26, count 0 2006.257.11:18:30.58#ibcon#read 4, iclass 26, count 0 2006.257.11:18:30.58#ibcon#about to read 5, iclass 26, count 0 2006.257.11:18:30.58#ibcon#read 5, iclass 26, count 0 2006.257.11:18:30.58#ibcon#about to read 6, iclass 26, count 0 2006.257.11:18:30.58#ibcon#read 6, iclass 26, count 0 2006.257.11:18:30.58#ibcon#end of sib2, iclass 26, count 0 2006.257.11:18:30.58#ibcon#*after write, iclass 26, count 0 2006.257.11:18:30.58#ibcon#*before return 0, iclass 26, count 0 2006.257.11:18:30.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:30.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:18:30.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:18:30.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:18:30.58$vck44/vblo=3,649.99 2006.257.11:18:30.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.11:18:30.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.11:18:30.58#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:30.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:30.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:30.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:30.58#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:18:30.58#ibcon#first serial, iclass 28, count 0 2006.257.11:18:30.58#ibcon#enter sib2, iclass 28, count 0 2006.257.11:18:30.58#ibcon#flushed, iclass 28, count 0 2006.257.11:18:30.58#ibcon#about to write, iclass 28, count 0 2006.257.11:18:30.58#ibcon#wrote, iclass 28, count 0 2006.257.11:18:30.58#ibcon#about to read 3, iclass 28, count 0 2006.257.11:18:30.60#ibcon#read 3, iclass 28, count 0 2006.257.11:18:30.60#ibcon#about to read 4, iclass 28, count 0 2006.257.11:18:30.60#ibcon#read 4, iclass 28, count 0 2006.257.11:18:30.60#ibcon#about to read 5, iclass 28, count 0 2006.257.11:18:30.60#ibcon#read 5, iclass 28, count 0 2006.257.11:18:30.60#ibcon#about to read 6, iclass 28, count 0 2006.257.11:18:30.60#ibcon#read 6, iclass 28, count 0 2006.257.11:18:30.60#ibcon#end of sib2, iclass 28, count 0 2006.257.11:18:30.60#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:18:30.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:18:30.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:18:30.60#ibcon#*before write, iclass 28, count 0 2006.257.11:18:30.60#ibcon#enter sib2, iclass 28, count 0 2006.257.11:18:30.60#ibcon#flushed, iclass 28, count 0 2006.257.11:18:30.60#ibcon#about to write, iclass 28, count 0 2006.257.11:18:30.60#ibcon#wrote, iclass 28, count 0 2006.257.11:18:30.60#ibcon#about to read 3, iclass 28, count 0 2006.257.11:18:30.64#ibcon#read 3, iclass 28, count 0 2006.257.11:18:30.64#ibcon#about to read 4, iclass 28, count 0 2006.257.11:18:30.64#ibcon#read 4, iclass 28, count 0 2006.257.11:18:30.64#ibcon#about to read 5, iclass 28, count 0 2006.257.11:18:30.64#ibcon#read 5, iclass 28, count 0 2006.257.11:18:30.64#ibcon#about to read 6, iclass 28, count 0 2006.257.11:18:30.64#ibcon#read 6, iclass 28, count 0 2006.257.11:18:30.64#ibcon#end of sib2, iclass 28, count 0 2006.257.11:18:30.64#ibcon#*after write, iclass 28, count 0 2006.257.11:18:30.64#ibcon#*before return 0, iclass 28, count 0 2006.257.11:18:30.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:30.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:18:30.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:18:30.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:18:30.64$vck44/vb=3,4 2006.257.11:18:30.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.11:18:30.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.11:18:30.64#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:30.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:30.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:30.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:30.70#ibcon#enter wrdev, iclass 30, count 2 2006.257.11:18:30.70#ibcon#first serial, iclass 30, count 2 2006.257.11:18:30.70#ibcon#enter sib2, iclass 30, count 2 2006.257.11:18:30.70#ibcon#flushed, iclass 30, count 2 2006.257.11:18:30.70#ibcon#about to write, iclass 30, count 2 2006.257.11:18:30.70#ibcon#wrote, iclass 30, count 2 2006.257.11:18:30.70#ibcon#about to read 3, iclass 30, count 2 2006.257.11:18:30.72#ibcon#read 3, iclass 30, count 2 2006.257.11:18:30.72#ibcon#about to read 4, iclass 30, count 2 2006.257.11:18:30.72#ibcon#read 4, iclass 30, count 2 2006.257.11:18:30.72#ibcon#about to read 5, iclass 30, count 2 2006.257.11:18:30.72#ibcon#read 5, iclass 30, count 2 2006.257.11:18:30.72#ibcon#about to read 6, iclass 30, count 2 2006.257.11:18:30.72#ibcon#read 6, iclass 30, count 2 2006.257.11:18:30.72#ibcon#end of sib2, iclass 30, count 2 2006.257.11:18:30.72#ibcon#*mode == 0, iclass 30, count 2 2006.257.11:18:30.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.11:18:30.72#ibcon#[27=AT03-04\r\n] 2006.257.11:18:30.72#ibcon#*before write, iclass 30, count 2 2006.257.11:18:30.72#ibcon#enter sib2, iclass 30, count 2 2006.257.11:18:30.72#ibcon#flushed, iclass 30, count 2 2006.257.11:18:30.72#ibcon#about to write, iclass 30, count 2 2006.257.11:18:30.72#ibcon#wrote, iclass 30, count 2 2006.257.11:18:30.72#ibcon#about to read 3, iclass 30, count 2 2006.257.11:18:30.75#ibcon#read 3, iclass 30, count 2 2006.257.11:18:30.75#ibcon#about to read 4, iclass 30, count 2 2006.257.11:18:30.75#ibcon#read 4, iclass 30, count 2 2006.257.11:18:30.75#ibcon#about to read 5, iclass 30, count 2 2006.257.11:18:30.75#ibcon#read 5, iclass 30, count 2 2006.257.11:18:30.75#ibcon#about to read 6, iclass 30, count 2 2006.257.11:18:30.75#ibcon#read 6, iclass 30, count 2 2006.257.11:18:30.75#ibcon#end of sib2, iclass 30, count 2 2006.257.11:18:30.75#ibcon#*after write, iclass 30, count 2 2006.257.11:18:30.75#ibcon#*before return 0, iclass 30, count 2 2006.257.11:18:30.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:30.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:18:30.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.11:18:30.75#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:30.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:30.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:30.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:30.87#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:18:30.87#ibcon#first serial, iclass 30, count 0 2006.257.11:18:30.87#ibcon#enter sib2, iclass 30, count 0 2006.257.11:18:30.87#ibcon#flushed, iclass 30, count 0 2006.257.11:18:30.87#ibcon#about to write, iclass 30, count 0 2006.257.11:18:30.87#ibcon#wrote, iclass 30, count 0 2006.257.11:18:30.87#ibcon#about to read 3, iclass 30, count 0 2006.257.11:18:30.89#ibcon#read 3, iclass 30, count 0 2006.257.11:18:30.89#ibcon#about to read 4, iclass 30, count 0 2006.257.11:18:30.89#ibcon#read 4, iclass 30, count 0 2006.257.11:18:30.89#ibcon#about to read 5, iclass 30, count 0 2006.257.11:18:30.89#ibcon#read 5, iclass 30, count 0 2006.257.11:18:30.89#ibcon#about to read 6, iclass 30, count 0 2006.257.11:18:30.89#ibcon#read 6, iclass 30, count 0 2006.257.11:18:30.89#ibcon#end of sib2, iclass 30, count 0 2006.257.11:18:30.89#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:18:30.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:18:30.89#ibcon#[27=USB\r\n] 2006.257.11:18:30.89#ibcon#*before write, iclass 30, count 0 2006.257.11:18:30.89#ibcon#enter sib2, iclass 30, count 0 2006.257.11:18:30.89#ibcon#flushed, iclass 30, count 0 2006.257.11:18:30.89#ibcon#about to write, iclass 30, count 0 2006.257.11:18:30.89#ibcon#wrote, iclass 30, count 0 2006.257.11:18:30.89#ibcon#about to read 3, iclass 30, count 0 2006.257.11:18:30.92#ibcon#read 3, iclass 30, count 0 2006.257.11:18:30.92#ibcon#about to read 4, iclass 30, count 0 2006.257.11:18:30.92#ibcon#read 4, iclass 30, count 0 2006.257.11:18:30.92#ibcon#about to read 5, iclass 30, count 0 2006.257.11:18:30.92#ibcon#read 5, iclass 30, count 0 2006.257.11:18:30.92#ibcon#about to read 6, iclass 30, count 0 2006.257.11:18:30.92#ibcon#read 6, iclass 30, count 0 2006.257.11:18:30.92#ibcon#end of sib2, iclass 30, count 0 2006.257.11:18:30.92#ibcon#*after write, iclass 30, count 0 2006.257.11:18:30.92#ibcon#*before return 0, iclass 30, count 0 2006.257.11:18:30.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:30.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:18:30.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:18:30.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:18:30.92$vck44/vblo=4,679.99 2006.257.11:18:30.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.11:18:30.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.11:18:30.92#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:30.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:30.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:30.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:30.92#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:18:30.92#ibcon#first serial, iclass 32, count 0 2006.257.11:18:30.92#ibcon#enter sib2, iclass 32, count 0 2006.257.11:18:30.92#ibcon#flushed, iclass 32, count 0 2006.257.11:18:30.92#ibcon#about to write, iclass 32, count 0 2006.257.11:18:30.92#ibcon#wrote, iclass 32, count 0 2006.257.11:18:30.92#ibcon#about to read 3, iclass 32, count 0 2006.257.11:18:30.94#ibcon#read 3, iclass 32, count 0 2006.257.11:18:30.94#ibcon#about to read 4, iclass 32, count 0 2006.257.11:18:30.94#ibcon#read 4, iclass 32, count 0 2006.257.11:18:30.94#ibcon#about to read 5, iclass 32, count 0 2006.257.11:18:30.94#ibcon#read 5, iclass 32, count 0 2006.257.11:18:30.94#ibcon#about to read 6, iclass 32, count 0 2006.257.11:18:30.94#ibcon#read 6, iclass 32, count 0 2006.257.11:18:30.94#ibcon#end of sib2, iclass 32, count 0 2006.257.11:18:30.94#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:18:30.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:18:30.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:18:30.94#ibcon#*before write, iclass 32, count 0 2006.257.11:18:30.94#ibcon#enter sib2, iclass 32, count 0 2006.257.11:18:30.94#ibcon#flushed, iclass 32, count 0 2006.257.11:18:30.94#ibcon#about to write, iclass 32, count 0 2006.257.11:18:30.94#ibcon#wrote, iclass 32, count 0 2006.257.11:18:30.94#ibcon#about to read 3, iclass 32, count 0 2006.257.11:18:30.98#ibcon#read 3, iclass 32, count 0 2006.257.11:18:30.98#ibcon#about to read 4, iclass 32, count 0 2006.257.11:18:30.98#ibcon#read 4, iclass 32, count 0 2006.257.11:18:30.98#ibcon#about to read 5, iclass 32, count 0 2006.257.11:18:30.98#ibcon#read 5, iclass 32, count 0 2006.257.11:18:30.98#ibcon#about to read 6, iclass 32, count 0 2006.257.11:18:30.98#ibcon#read 6, iclass 32, count 0 2006.257.11:18:30.98#ibcon#end of sib2, iclass 32, count 0 2006.257.11:18:30.98#ibcon#*after write, iclass 32, count 0 2006.257.11:18:30.98#ibcon#*before return 0, iclass 32, count 0 2006.257.11:18:30.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:30.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:18:30.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:18:30.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:18:30.98$vck44/vb=4,5 2006.257.11:18:30.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.11:18:30.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.11:18:30.98#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:30.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:31.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:31.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:31.04#ibcon#enter wrdev, iclass 34, count 2 2006.257.11:18:31.04#ibcon#first serial, iclass 34, count 2 2006.257.11:18:31.04#ibcon#enter sib2, iclass 34, count 2 2006.257.11:18:31.04#ibcon#flushed, iclass 34, count 2 2006.257.11:18:31.04#ibcon#about to write, iclass 34, count 2 2006.257.11:18:31.04#ibcon#wrote, iclass 34, count 2 2006.257.11:18:31.04#ibcon#about to read 3, iclass 34, count 2 2006.257.11:18:31.06#ibcon#read 3, iclass 34, count 2 2006.257.11:18:31.06#ibcon#about to read 4, iclass 34, count 2 2006.257.11:18:31.06#ibcon#read 4, iclass 34, count 2 2006.257.11:18:31.06#ibcon#about to read 5, iclass 34, count 2 2006.257.11:18:31.06#ibcon#read 5, iclass 34, count 2 2006.257.11:18:31.06#ibcon#about to read 6, iclass 34, count 2 2006.257.11:18:31.06#ibcon#read 6, iclass 34, count 2 2006.257.11:18:31.06#ibcon#end of sib2, iclass 34, count 2 2006.257.11:18:31.06#ibcon#*mode == 0, iclass 34, count 2 2006.257.11:18:31.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.11:18:31.06#ibcon#[27=AT04-05\r\n] 2006.257.11:18:31.06#ibcon#*before write, iclass 34, count 2 2006.257.11:18:31.06#ibcon#enter sib2, iclass 34, count 2 2006.257.11:18:31.06#ibcon#flushed, iclass 34, count 2 2006.257.11:18:31.06#ibcon#about to write, iclass 34, count 2 2006.257.11:18:31.06#ibcon#wrote, iclass 34, count 2 2006.257.11:18:31.06#ibcon#about to read 3, iclass 34, count 2 2006.257.11:18:31.09#ibcon#read 3, iclass 34, count 2 2006.257.11:18:31.09#ibcon#about to read 4, iclass 34, count 2 2006.257.11:18:31.09#ibcon#read 4, iclass 34, count 2 2006.257.11:18:31.09#ibcon#about to read 5, iclass 34, count 2 2006.257.11:18:31.09#ibcon#read 5, iclass 34, count 2 2006.257.11:18:31.09#ibcon#about to read 6, iclass 34, count 2 2006.257.11:18:31.09#ibcon#read 6, iclass 34, count 2 2006.257.11:18:31.09#ibcon#end of sib2, iclass 34, count 2 2006.257.11:18:31.09#ibcon#*after write, iclass 34, count 2 2006.257.11:18:31.09#ibcon#*before return 0, iclass 34, count 2 2006.257.11:18:31.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:31.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:18:31.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.11:18:31.09#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:31.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:31.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:31.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:31.21#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:18:31.21#ibcon#first serial, iclass 34, count 0 2006.257.11:18:31.21#ibcon#enter sib2, iclass 34, count 0 2006.257.11:18:31.21#ibcon#flushed, iclass 34, count 0 2006.257.11:18:31.21#ibcon#about to write, iclass 34, count 0 2006.257.11:18:31.21#ibcon#wrote, iclass 34, count 0 2006.257.11:18:31.21#ibcon#about to read 3, iclass 34, count 0 2006.257.11:18:31.23#ibcon#read 3, iclass 34, count 0 2006.257.11:18:31.23#ibcon#about to read 4, iclass 34, count 0 2006.257.11:18:31.23#ibcon#read 4, iclass 34, count 0 2006.257.11:18:31.23#ibcon#about to read 5, iclass 34, count 0 2006.257.11:18:31.23#ibcon#read 5, iclass 34, count 0 2006.257.11:18:31.23#ibcon#about to read 6, iclass 34, count 0 2006.257.11:18:31.23#ibcon#read 6, iclass 34, count 0 2006.257.11:18:31.23#ibcon#end of sib2, iclass 34, count 0 2006.257.11:18:31.23#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:18:31.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:18:31.23#ibcon#[27=USB\r\n] 2006.257.11:18:31.23#ibcon#*before write, iclass 34, count 0 2006.257.11:18:31.23#ibcon#enter sib2, iclass 34, count 0 2006.257.11:18:31.23#ibcon#flushed, iclass 34, count 0 2006.257.11:18:31.23#ibcon#about to write, iclass 34, count 0 2006.257.11:18:31.23#ibcon#wrote, iclass 34, count 0 2006.257.11:18:31.23#ibcon#about to read 3, iclass 34, count 0 2006.257.11:18:31.26#ibcon#read 3, iclass 34, count 0 2006.257.11:18:31.26#ibcon#about to read 4, iclass 34, count 0 2006.257.11:18:31.26#ibcon#read 4, iclass 34, count 0 2006.257.11:18:31.26#ibcon#about to read 5, iclass 34, count 0 2006.257.11:18:31.26#ibcon#read 5, iclass 34, count 0 2006.257.11:18:31.26#ibcon#about to read 6, iclass 34, count 0 2006.257.11:18:31.26#ibcon#read 6, iclass 34, count 0 2006.257.11:18:31.26#ibcon#end of sib2, iclass 34, count 0 2006.257.11:18:31.26#ibcon#*after write, iclass 34, count 0 2006.257.11:18:31.26#ibcon#*before return 0, iclass 34, count 0 2006.257.11:18:31.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:31.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:18:31.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:18:31.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:18:31.26$vck44/vblo=5,709.99 2006.257.11:18:31.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.11:18:31.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.11:18:31.26#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:31.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:18:31.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:18:31.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:18:31.26#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:18:31.26#ibcon#first serial, iclass 36, count 0 2006.257.11:18:31.26#ibcon#enter sib2, iclass 36, count 0 2006.257.11:18:31.26#ibcon#flushed, iclass 36, count 0 2006.257.11:18:31.26#ibcon#about to write, iclass 36, count 0 2006.257.11:18:31.26#ibcon#wrote, iclass 36, count 0 2006.257.11:18:31.26#ibcon#about to read 3, iclass 36, count 0 2006.257.11:18:31.28#ibcon#read 3, iclass 36, count 0 2006.257.11:18:31.28#ibcon#about to read 4, iclass 36, count 0 2006.257.11:18:31.28#ibcon#read 4, iclass 36, count 0 2006.257.11:18:31.28#ibcon#about to read 5, iclass 36, count 0 2006.257.11:18:31.28#ibcon#read 5, iclass 36, count 0 2006.257.11:18:31.28#ibcon#about to read 6, iclass 36, count 0 2006.257.11:18:31.28#ibcon#read 6, iclass 36, count 0 2006.257.11:18:31.28#ibcon#end of sib2, iclass 36, count 0 2006.257.11:18:31.28#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:18:31.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:18:31.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:18:31.28#ibcon#*before write, iclass 36, count 0 2006.257.11:18:31.28#ibcon#enter sib2, iclass 36, count 0 2006.257.11:18:31.28#ibcon#flushed, iclass 36, count 0 2006.257.11:18:31.28#ibcon#about to write, iclass 36, count 0 2006.257.11:18:31.28#ibcon#wrote, iclass 36, count 0 2006.257.11:18:31.28#ibcon#about to read 3, iclass 36, count 0 2006.257.11:18:31.32#ibcon#read 3, iclass 36, count 0 2006.257.11:18:31.32#ibcon#about to read 4, iclass 36, count 0 2006.257.11:18:31.32#ibcon#read 4, iclass 36, count 0 2006.257.11:18:31.32#ibcon#about to read 5, iclass 36, count 0 2006.257.11:18:31.32#ibcon#read 5, iclass 36, count 0 2006.257.11:18:31.32#ibcon#about to read 6, iclass 36, count 0 2006.257.11:18:31.32#ibcon#read 6, iclass 36, count 0 2006.257.11:18:31.32#ibcon#end of sib2, iclass 36, count 0 2006.257.11:18:31.32#ibcon#*after write, iclass 36, count 0 2006.257.11:18:31.32#ibcon#*before return 0, iclass 36, count 0 2006.257.11:18:31.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:18:31.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:18:31.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:18:31.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:18:31.32$vck44/vb=5,4 2006.257.11:18:31.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.11:18:31.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.11:18:31.32#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:31.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:18:31.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:18:31.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:18:31.38#ibcon#enter wrdev, iclass 38, count 2 2006.257.11:18:31.38#ibcon#first serial, iclass 38, count 2 2006.257.11:18:31.38#ibcon#enter sib2, iclass 38, count 2 2006.257.11:18:31.38#ibcon#flushed, iclass 38, count 2 2006.257.11:18:31.38#ibcon#about to write, iclass 38, count 2 2006.257.11:18:31.38#ibcon#wrote, iclass 38, count 2 2006.257.11:18:31.38#ibcon#about to read 3, iclass 38, count 2 2006.257.11:18:31.40#ibcon#read 3, iclass 38, count 2 2006.257.11:18:31.40#ibcon#about to read 4, iclass 38, count 2 2006.257.11:18:31.40#ibcon#read 4, iclass 38, count 2 2006.257.11:18:31.40#ibcon#about to read 5, iclass 38, count 2 2006.257.11:18:31.40#ibcon#read 5, iclass 38, count 2 2006.257.11:18:31.40#ibcon#about to read 6, iclass 38, count 2 2006.257.11:18:31.40#ibcon#read 6, iclass 38, count 2 2006.257.11:18:31.40#ibcon#end of sib2, iclass 38, count 2 2006.257.11:18:31.40#ibcon#*mode == 0, iclass 38, count 2 2006.257.11:18:31.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.11:18:31.40#ibcon#[27=AT05-04\r\n] 2006.257.11:18:31.40#ibcon#*before write, iclass 38, count 2 2006.257.11:18:31.40#ibcon#enter sib2, iclass 38, count 2 2006.257.11:18:31.40#ibcon#flushed, iclass 38, count 2 2006.257.11:18:31.40#ibcon#about to write, iclass 38, count 2 2006.257.11:18:31.40#ibcon#wrote, iclass 38, count 2 2006.257.11:18:31.40#ibcon#about to read 3, iclass 38, count 2 2006.257.11:18:31.43#ibcon#read 3, iclass 38, count 2 2006.257.11:18:31.45#ibcon#about to read 4, iclass 38, count 2 2006.257.11:18:31.45#ibcon#read 4, iclass 38, count 2 2006.257.11:18:31.45#ibcon#about to read 5, iclass 38, count 2 2006.257.11:18:31.45#ibcon#read 5, iclass 38, count 2 2006.257.11:18:31.45#ibcon#about to read 6, iclass 38, count 2 2006.257.11:18:31.45#ibcon#read 6, iclass 38, count 2 2006.257.11:18:31.45#ibcon#end of sib2, iclass 38, count 2 2006.257.11:18:31.45#ibcon#*after write, iclass 38, count 2 2006.257.11:18:31.45#ibcon#*before return 0, iclass 38, count 2 2006.257.11:18:31.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:18:31.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:18:31.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.11:18:31.45#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:31.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:18:31.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:18:31.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:18:31.57#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:18:31.57#ibcon#first serial, iclass 38, count 0 2006.257.11:18:31.57#ibcon#enter sib2, iclass 38, count 0 2006.257.11:18:31.57#ibcon#flushed, iclass 38, count 0 2006.257.11:18:31.57#ibcon#about to write, iclass 38, count 0 2006.257.11:18:31.57#ibcon#wrote, iclass 38, count 0 2006.257.11:18:31.57#ibcon#about to read 3, iclass 38, count 0 2006.257.11:18:31.59#ibcon#read 3, iclass 38, count 0 2006.257.11:18:31.59#ibcon#about to read 4, iclass 38, count 0 2006.257.11:18:31.59#ibcon#read 4, iclass 38, count 0 2006.257.11:18:31.59#ibcon#about to read 5, iclass 38, count 0 2006.257.11:18:31.59#ibcon#read 5, iclass 38, count 0 2006.257.11:18:31.59#ibcon#about to read 6, iclass 38, count 0 2006.257.11:18:31.59#ibcon#read 6, iclass 38, count 0 2006.257.11:18:31.59#ibcon#end of sib2, iclass 38, count 0 2006.257.11:18:31.59#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:18:31.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:18:31.59#ibcon#[27=USB\r\n] 2006.257.11:18:31.59#ibcon#*before write, iclass 38, count 0 2006.257.11:18:31.59#ibcon#enter sib2, iclass 38, count 0 2006.257.11:18:31.59#ibcon#flushed, iclass 38, count 0 2006.257.11:18:31.59#ibcon#about to write, iclass 38, count 0 2006.257.11:18:31.59#ibcon#wrote, iclass 38, count 0 2006.257.11:18:31.59#ibcon#about to read 3, iclass 38, count 0 2006.257.11:18:31.62#ibcon#read 3, iclass 38, count 0 2006.257.11:18:31.62#ibcon#about to read 4, iclass 38, count 0 2006.257.11:18:31.62#ibcon#read 4, iclass 38, count 0 2006.257.11:18:31.62#ibcon#about to read 5, iclass 38, count 0 2006.257.11:18:31.62#ibcon#read 5, iclass 38, count 0 2006.257.11:18:31.62#ibcon#about to read 6, iclass 38, count 0 2006.257.11:18:31.62#ibcon#read 6, iclass 38, count 0 2006.257.11:18:31.62#ibcon#end of sib2, iclass 38, count 0 2006.257.11:18:31.62#ibcon#*after write, iclass 38, count 0 2006.257.11:18:31.62#ibcon#*before return 0, iclass 38, count 0 2006.257.11:18:31.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:18:31.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:18:31.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:18:31.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:18:31.62$vck44/vblo=6,719.99 2006.257.11:18:31.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.11:18:31.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.11:18:31.62#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:31.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:18:31.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:18:31.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:18:31.62#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:18:31.62#ibcon#first serial, iclass 40, count 0 2006.257.11:18:31.62#ibcon#enter sib2, iclass 40, count 0 2006.257.11:18:31.62#ibcon#flushed, iclass 40, count 0 2006.257.11:18:31.62#ibcon#about to write, iclass 40, count 0 2006.257.11:18:31.62#ibcon#wrote, iclass 40, count 0 2006.257.11:18:31.62#ibcon#about to read 3, iclass 40, count 0 2006.257.11:18:31.64#ibcon#read 3, iclass 40, count 0 2006.257.11:18:31.64#ibcon#about to read 4, iclass 40, count 0 2006.257.11:18:31.64#ibcon#read 4, iclass 40, count 0 2006.257.11:18:31.64#ibcon#about to read 5, iclass 40, count 0 2006.257.11:18:31.64#ibcon#read 5, iclass 40, count 0 2006.257.11:18:31.64#ibcon#about to read 6, iclass 40, count 0 2006.257.11:18:31.64#ibcon#read 6, iclass 40, count 0 2006.257.11:18:31.64#ibcon#end of sib2, iclass 40, count 0 2006.257.11:18:31.64#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:18:31.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:18:31.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:18:31.64#ibcon#*before write, iclass 40, count 0 2006.257.11:18:31.64#ibcon#enter sib2, iclass 40, count 0 2006.257.11:18:31.64#ibcon#flushed, iclass 40, count 0 2006.257.11:18:31.64#ibcon#about to write, iclass 40, count 0 2006.257.11:18:31.64#ibcon#wrote, iclass 40, count 0 2006.257.11:18:31.64#ibcon#about to read 3, iclass 40, count 0 2006.257.11:18:31.68#ibcon#read 3, iclass 40, count 0 2006.257.11:18:31.68#ibcon#about to read 4, iclass 40, count 0 2006.257.11:18:31.68#ibcon#read 4, iclass 40, count 0 2006.257.11:18:31.68#ibcon#about to read 5, iclass 40, count 0 2006.257.11:18:31.68#ibcon#read 5, iclass 40, count 0 2006.257.11:18:31.68#ibcon#about to read 6, iclass 40, count 0 2006.257.11:18:31.68#ibcon#read 6, iclass 40, count 0 2006.257.11:18:31.68#ibcon#end of sib2, iclass 40, count 0 2006.257.11:18:31.68#ibcon#*after write, iclass 40, count 0 2006.257.11:18:31.68#ibcon#*before return 0, iclass 40, count 0 2006.257.11:18:31.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:18:31.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:18:31.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:18:31.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:18:31.68$vck44/vb=6,4 2006.257.11:18:31.68#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.11:18:31.68#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.11:18:31.68#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:31.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:31.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:31.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:31.74#ibcon#enter wrdev, iclass 4, count 2 2006.257.11:18:31.74#ibcon#first serial, iclass 4, count 2 2006.257.11:18:31.74#ibcon#enter sib2, iclass 4, count 2 2006.257.11:18:31.74#ibcon#flushed, iclass 4, count 2 2006.257.11:18:31.74#ibcon#about to write, iclass 4, count 2 2006.257.11:18:31.74#ibcon#wrote, iclass 4, count 2 2006.257.11:18:31.74#ibcon#about to read 3, iclass 4, count 2 2006.257.11:18:31.76#ibcon#read 3, iclass 4, count 2 2006.257.11:18:31.76#ibcon#about to read 4, iclass 4, count 2 2006.257.11:18:31.76#ibcon#read 4, iclass 4, count 2 2006.257.11:18:31.76#ibcon#about to read 5, iclass 4, count 2 2006.257.11:18:31.76#ibcon#read 5, iclass 4, count 2 2006.257.11:18:31.76#ibcon#about to read 6, iclass 4, count 2 2006.257.11:18:31.76#ibcon#read 6, iclass 4, count 2 2006.257.11:18:31.76#ibcon#end of sib2, iclass 4, count 2 2006.257.11:18:31.76#ibcon#*mode == 0, iclass 4, count 2 2006.257.11:18:31.76#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.11:18:31.76#ibcon#[27=AT06-04\r\n] 2006.257.11:18:31.76#ibcon#*before write, iclass 4, count 2 2006.257.11:18:31.76#ibcon#enter sib2, iclass 4, count 2 2006.257.11:18:31.76#ibcon#flushed, iclass 4, count 2 2006.257.11:18:31.76#ibcon#about to write, iclass 4, count 2 2006.257.11:18:31.76#ibcon#wrote, iclass 4, count 2 2006.257.11:18:31.76#ibcon#about to read 3, iclass 4, count 2 2006.257.11:18:31.79#ibcon#read 3, iclass 4, count 2 2006.257.11:18:31.79#ibcon#about to read 4, iclass 4, count 2 2006.257.11:18:31.79#ibcon#read 4, iclass 4, count 2 2006.257.11:18:31.79#ibcon#about to read 5, iclass 4, count 2 2006.257.11:18:31.79#ibcon#read 5, iclass 4, count 2 2006.257.11:18:31.79#ibcon#about to read 6, iclass 4, count 2 2006.257.11:18:31.79#ibcon#read 6, iclass 4, count 2 2006.257.11:18:31.79#ibcon#end of sib2, iclass 4, count 2 2006.257.11:18:31.79#ibcon#*after write, iclass 4, count 2 2006.257.11:18:31.79#ibcon#*before return 0, iclass 4, count 2 2006.257.11:18:31.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:31.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:18:31.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.11:18:31.79#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:31.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:31.91#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:31.91#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:31.91#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:18:31.91#ibcon#first serial, iclass 4, count 0 2006.257.11:18:31.91#ibcon#enter sib2, iclass 4, count 0 2006.257.11:18:31.91#ibcon#flushed, iclass 4, count 0 2006.257.11:18:31.91#ibcon#about to write, iclass 4, count 0 2006.257.11:18:31.91#ibcon#wrote, iclass 4, count 0 2006.257.11:18:31.91#ibcon#about to read 3, iclass 4, count 0 2006.257.11:18:31.93#ibcon#read 3, iclass 4, count 0 2006.257.11:18:31.93#ibcon#about to read 4, iclass 4, count 0 2006.257.11:18:31.93#ibcon#read 4, iclass 4, count 0 2006.257.11:18:31.93#ibcon#about to read 5, iclass 4, count 0 2006.257.11:18:31.93#ibcon#read 5, iclass 4, count 0 2006.257.11:18:31.93#ibcon#about to read 6, iclass 4, count 0 2006.257.11:18:31.93#ibcon#read 6, iclass 4, count 0 2006.257.11:18:31.93#ibcon#end of sib2, iclass 4, count 0 2006.257.11:18:31.93#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:18:31.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:18:31.93#ibcon#[27=USB\r\n] 2006.257.11:18:31.93#ibcon#*before write, iclass 4, count 0 2006.257.11:18:31.93#ibcon#enter sib2, iclass 4, count 0 2006.257.11:18:31.93#ibcon#flushed, iclass 4, count 0 2006.257.11:18:31.93#ibcon#about to write, iclass 4, count 0 2006.257.11:18:31.93#ibcon#wrote, iclass 4, count 0 2006.257.11:18:31.93#ibcon#about to read 3, iclass 4, count 0 2006.257.11:18:31.96#ibcon#read 3, iclass 4, count 0 2006.257.11:18:31.96#ibcon#about to read 4, iclass 4, count 0 2006.257.11:18:31.96#ibcon#read 4, iclass 4, count 0 2006.257.11:18:31.96#ibcon#about to read 5, iclass 4, count 0 2006.257.11:18:31.96#ibcon#read 5, iclass 4, count 0 2006.257.11:18:31.96#ibcon#about to read 6, iclass 4, count 0 2006.257.11:18:31.96#ibcon#read 6, iclass 4, count 0 2006.257.11:18:31.96#ibcon#end of sib2, iclass 4, count 0 2006.257.11:18:31.96#ibcon#*after write, iclass 4, count 0 2006.257.11:18:31.96#ibcon#*before return 0, iclass 4, count 0 2006.257.11:18:31.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:31.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:18:31.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:18:31.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:18:31.96$vck44/vblo=7,734.99 2006.257.11:18:31.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.11:18:31.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.11:18:31.96#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:31.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:31.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:31.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:31.96#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:18:31.96#ibcon#first serial, iclass 6, count 0 2006.257.11:18:31.96#ibcon#enter sib2, iclass 6, count 0 2006.257.11:18:31.96#ibcon#flushed, iclass 6, count 0 2006.257.11:18:31.96#ibcon#about to write, iclass 6, count 0 2006.257.11:18:31.96#ibcon#wrote, iclass 6, count 0 2006.257.11:18:31.96#ibcon#about to read 3, iclass 6, count 0 2006.257.11:18:31.98#ibcon#read 3, iclass 6, count 0 2006.257.11:18:31.98#ibcon#about to read 4, iclass 6, count 0 2006.257.11:18:31.98#ibcon#read 4, iclass 6, count 0 2006.257.11:18:31.98#ibcon#about to read 5, iclass 6, count 0 2006.257.11:18:31.98#ibcon#read 5, iclass 6, count 0 2006.257.11:18:31.98#ibcon#about to read 6, iclass 6, count 0 2006.257.11:18:31.98#ibcon#read 6, iclass 6, count 0 2006.257.11:18:31.98#ibcon#end of sib2, iclass 6, count 0 2006.257.11:18:31.98#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:18:31.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:18:31.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:18:31.98#ibcon#*before write, iclass 6, count 0 2006.257.11:18:31.98#ibcon#enter sib2, iclass 6, count 0 2006.257.11:18:31.98#ibcon#flushed, iclass 6, count 0 2006.257.11:18:31.98#ibcon#about to write, iclass 6, count 0 2006.257.11:18:31.98#ibcon#wrote, iclass 6, count 0 2006.257.11:18:31.98#ibcon#about to read 3, iclass 6, count 0 2006.257.11:18:32.02#ibcon#read 3, iclass 6, count 0 2006.257.11:18:32.02#ibcon#about to read 4, iclass 6, count 0 2006.257.11:18:32.02#ibcon#read 4, iclass 6, count 0 2006.257.11:18:32.02#ibcon#about to read 5, iclass 6, count 0 2006.257.11:18:32.02#ibcon#read 5, iclass 6, count 0 2006.257.11:18:32.02#ibcon#about to read 6, iclass 6, count 0 2006.257.11:18:32.02#ibcon#read 6, iclass 6, count 0 2006.257.11:18:32.02#ibcon#end of sib2, iclass 6, count 0 2006.257.11:18:32.02#ibcon#*after write, iclass 6, count 0 2006.257.11:18:32.02#ibcon#*before return 0, iclass 6, count 0 2006.257.11:18:32.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:32.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:18:32.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:18:32.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:18:32.02$vck44/vb=7,4 2006.257.11:18:32.02#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.11:18:32.02#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.11:18:32.02#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:32.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:32.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:32.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:32.08#ibcon#enter wrdev, iclass 10, count 2 2006.257.11:18:32.08#ibcon#first serial, iclass 10, count 2 2006.257.11:18:32.08#ibcon#enter sib2, iclass 10, count 2 2006.257.11:18:32.08#ibcon#flushed, iclass 10, count 2 2006.257.11:18:32.08#ibcon#about to write, iclass 10, count 2 2006.257.11:18:32.08#ibcon#wrote, iclass 10, count 2 2006.257.11:18:32.08#ibcon#about to read 3, iclass 10, count 2 2006.257.11:18:32.10#ibcon#read 3, iclass 10, count 2 2006.257.11:18:32.10#ibcon#about to read 4, iclass 10, count 2 2006.257.11:18:32.10#ibcon#read 4, iclass 10, count 2 2006.257.11:18:32.10#ibcon#about to read 5, iclass 10, count 2 2006.257.11:18:32.10#ibcon#read 5, iclass 10, count 2 2006.257.11:18:32.10#ibcon#about to read 6, iclass 10, count 2 2006.257.11:18:32.10#ibcon#read 6, iclass 10, count 2 2006.257.11:18:32.10#ibcon#end of sib2, iclass 10, count 2 2006.257.11:18:32.10#ibcon#*mode == 0, iclass 10, count 2 2006.257.11:18:32.10#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.11:18:32.10#ibcon#[27=AT07-04\r\n] 2006.257.11:18:32.10#ibcon#*before write, iclass 10, count 2 2006.257.11:18:32.10#ibcon#enter sib2, iclass 10, count 2 2006.257.11:18:32.10#ibcon#flushed, iclass 10, count 2 2006.257.11:18:32.10#ibcon#about to write, iclass 10, count 2 2006.257.11:18:32.10#ibcon#wrote, iclass 10, count 2 2006.257.11:18:32.10#ibcon#about to read 3, iclass 10, count 2 2006.257.11:18:32.13#ibcon#read 3, iclass 10, count 2 2006.257.11:18:32.13#ibcon#about to read 4, iclass 10, count 2 2006.257.11:18:32.13#ibcon#read 4, iclass 10, count 2 2006.257.11:18:32.13#ibcon#about to read 5, iclass 10, count 2 2006.257.11:18:32.13#ibcon#read 5, iclass 10, count 2 2006.257.11:18:32.13#ibcon#about to read 6, iclass 10, count 2 2006.257.11:18:32.13#ibcon#read 6, iclass 10, count 2 2006.257.11:18:32.13#ibcon#end of sib2, iclass 10, count 2 2006.257.11:18:32.13#ibcon#*after write, iclass 10, count 2 2006.257.11:18:32.13#ibcon#*before return 0, iclass 10, count 2 2006.257.11:18:32.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:32.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:18:32.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.11:18:32.13#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:32.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:32.25#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:32.25#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:32.25#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:18:32.25#ibcon#first serial, iclass 10, count 0 2006.257.11:18:32.25#ibcon#enter sib2, iclass 10, count 0 2006.257.11:18:32.25#ibcon#flushed, iclass 10, count 0 2006.257.11:18:32.25#ibcon#about to write, iclass 10, count 0 2006.257.11:18:32.25#ibcon#wrote, iclass 10, count 0 2006.257.11:18:32.25#ibcon#about to read 3, iclass 10, count 0 2006.257.11:18:32.27#ibcon#read 3, iclass 10, count 0 2006.257.11:18:32.27#ibcon#about to read 4, iclass 10, count 0 2006.257.11:18:32.27#ibcon#read 4, iclass 10, count 0 2006.257.11:18:32.27#ibcon#about to read 5, iclass 10, count 0 2006.257.11:18:32.27#ibcon#read 5, iclass 10, count 0 2006.257.11:18:32.27#ibcon#about to read 6, iclass 10, count 0 2006.257.11:18:32.27#ibcon#read 6, iclass 10, count 0 2006.257.11:18:32.27#ibcon#end of sib2, iclass 10, count 0 2006.257.11:18:32.27#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:18:32.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:18:32.27#ibcon#[27=USB\r\n] 2006.257.11:18:32.27#ibcon#*before write, iclass 10, count 0 2006.257.11:18:32.27#ibcon#enter sib2, iclass 10, count 0 2006.257.11:18:32.27#ibcon#flushed, iclass 10, count 0 2006.257.11:18:32.27#ibcon#about to write, iclass 10, count 0 2006.257.11:18:32.27#ibcon#wrote, iclass 10, count 0 2006.257.11:18:32.27#ibcon#about to read 3, iclass 10, count 0 2006.257.11:18:32.30#ibcon#read 3, iclass 10, count 0 2006.257.11:18:32.30#ibcon#about to read 4, iclass 10, count 0 2006.257.11:18:32.30#ibcon#read 4, iclass 10, count 0 2006.257.11:18:32.30#ibcon#about to read 5, iclass 10, count 0 2006.257.11:18:32.30#ibcon#read 5, iclass 10, count 0 2006.257.11:18:32.30#ibcon#about to read 6, iclass 10, count 0 2006.257.11:18:32.30#ibcon#read 6, iclass 10, count 0 2006.257.11:18:32.30#ibcon#end of sib2, iclass 10, count 0 2006.257.11:18:32.30#ibcon#*after write, iclass 10, count 0 2006.257.11:18:32.30#ibcon#*before return 0, iclass 10, count 0 2006.257.11:18:32.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:32.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:18:32.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:18:32.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:18:32.30$vck44/vblo=8,744.99 2006.257.11:18:32.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.11:18:32.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.11:18:32.30#ibcon#ireg 17 cls_cnt 0 2006.257.11:18:32.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:32.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:32.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:32.30#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:18:32.30#ibcon#first serial, iclass 12, count 0 2006.257.11:18:32.30#ibcon#enter sib2, iclass 12, count 0 2006.257.11:18:32.30#ibcon#flushed, iclass 12, count 0 2006.257.11:18:32.30#ibcon#about to write, iclass 12, count 0 2006.257.11:18:32.30#ibcon#wrote, iclass 12, count 0 2006.257.11:18:32.30#ibcon#about to read 3, iclass 12, count 0 2006.257.11:18:32.32#ibcon#read 3, iclass 12, count 0 2006.257.11:18:32.32#ibcon#about to read 4, iclass 12, count 0 2006.257.11:18:32.32#ibcon#read 4, iclass 12, count 0 2006.257.11:18:32.32#ibcon#about to read 5, iclass 12, count 0 2006.257.11:18:32.32#ibcon#read 5, iclass 12, count 0 2006.257.11:18:32.32#ibcon#about to read 6, iclass 12, count 0 2006.257.11:18:32.32#ibcon#read 6, iclass 12, count 0 2006.257.11:18:32.32#ibcon#end of sib2, iclass 12, count 0 2006.257.11:18:32.32#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:18:32.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:18:32.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:18:32.32#ibcon#*before write, iclass 12, count 0 2006.257.11:18:32.32#ibcon#enter sib2, iclass 12, count 0 2006.257.11:18:32.32#ibcon#flushed, iclass 12, count 0 2006.257.11:18:32.32#ibcon#about to write, iclass 12, count 0 2006.257.11:18:32.32#ibcon#wrote, iclass 12, count 0 2006.257.11:18:32.32#ibcon#about to read 3, iclass 12, count 0 2006.257.11:18:32.36#ibcon#read 3, iclass 12, count 0 2006.257.11:18:32.36#ibcon#about to read 4, iclass 12, count 0 2006.257.11:18:32.36#ibcon#read 4, iclass 12, count 0 2006.257.11:18:32.36#ibcon#about to read 5, iclass 12, count 0 2006.257.11:18:32.36#ibcon#read 5, iclass 12, count 0 2006.257.11:18:32.36#ibcon#about to read 6, iclass 12, count 0 2006.257.11:18:32.36#ibcon#read 6, iclass 12, count 0 2006.257.11:18:32.36#ibcon#end of sib2, iclass 12, count 0 2006.257.11:18:32.36#ibcon#*after write, iclass 12, count 0 2006.257.11:18:32.36#ibcon#*before return 0, iclass 12, count 0 2006.257.11:18:32.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:32.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:18:32.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:18:32.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:18:32.36$vck44/vb=8,4 2006.257.11:18:32.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.11:18:32.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.11:18:32.36#ibcon#ireg 11 cls_cnt 2 2006.257.11:18:32.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:32.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:32.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:32.42#ibcon#enter wrdev, iclass 14, count 2 2006.257.11:18:32.42#ibcon#first serial, iclass 14, count 2 2006.257.11:18:32.42#ibcon#enter sib2, iclass 14, count 2 2006.257.11:18:32.42#ibcon#flushed, iclass 14, count 2 2006.257.11:18:32.42#ibcon#about to write, iclass 14, count 2 2006.257.11:18:32.42#ibcon#wrote, iclass 14, count 2 2006.257.11:18:32.42#ibcon#about to read 3, iclass 14, count 2 2006.257.11:18:32.44#ibcon#read 3, iclass 14, count 2 2006.257.11:18:32.44#ibcon#about to read 4, iclass 14, count 2 2006.257.11:18:32.44#ibcon#read 4, iclass 14, count 2 2006.257.11:18:32.44#ibcon#about to read 5, iclass 14, count 2 2006.257.11:18:32.44#ibcon#read 5, iclass 14, count 2 2006.257.11:18:32.44#ibcon#about to read 6, iclass 14, count 2 2006.257.11:18:32.44#ibcon#read 6, iclass 14, count 2 2006.257.11:18:32.44#ibcon#end of sib2, iclass 14, count 2 2006.257.11:18:32.44#ibcon#*mode == 0, iclass 14, count 2 2006.257.11:18:32.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.11:18:32.44#ibcon#[27=AT08-04\r\n] 2006.257.11:18:32.44#ibcon#*before write, iclass 14, count 2 2006.257.11:18:32.44#ibcon#enter sib2, iclass 14, count 2 2006.257.11:18:32.44#ibcon#flushed, iclass 14, count 2 2006.257.11:18:32.44#ibcon#about to write, iclass 14, count 2 2006.257.11:18:32.44#ibcon#wrote, iclass 14, count 2 2006.257.11:18:32.44#ibcon#about to read 3, iclass 14, count 2 2006.257.11:18:32.47#ibcon#read 3, iclass 14, count 2 2006.257.11:18:32.47#ibcon#about to read 4, iclass 14, count 2 2006.257.11:18:32.47#ibcon#read 4, iclass 14, count 2 2006.257.11:18:32.47#ibcon#about to read 5, iclass 14, count 2 2006.257.11:18:32.47#ibcon#read 5, iclass 14, count 2 2006.257.11:18:32.47#ibcon#about to read 6, iclass 14, count 2 2006.257.11:18:32.47#ibcon#read 6, iclass 14, count 2 2006.257.11:18:32.47#ibcon#end of sib2, iclass 14, count 2 2006.257.11:18:32.47#ibcon#*after write, iclass 14, count 2 2006.257.11:18:32.47#ibcon#*before return 0, iclass 14, count 2 2006.257.11:18:32.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:32.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:18:32.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.11:18:32.47#ibcon#ireg 7 cls_cnt 0 2006.257.11:18:32.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:32.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:32.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:32.59#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:18:32.59#ibcon#first serial, iclass 14, count 0 2006.257.11:18:32.59#ibcon#enter sib2, iclass 14, count 0 2006.257.11:18:32.59#ibcon#flushed, iclass 14, count 0 2006.257.11:18:32.59#ibcon#about to write, iclass 14, count 0 2006.257.11:18:32.59#ibcon#wrote, iclass 14, count 0 2006.257.11:18:32.59#ibcon#about to read 3, iclass 14, count 0 2006.257.11:18:32.61#ibcon#read 3, iclass 14, count 0 2006.257.11:18:32.61#ibcon#about to read 4, iclass 14, count 0 2006.257.11:18:32.61#ibcon#read 4, iclass 14, count 0 2006.257.11:18:32.61#ibcon#about to read 5, iclass 14, count 0 2006.257.11:18:32.61#ibcon#read 5, iclass 14, count 0 2006.257.11:18:32.61#ibcon#about to read 6, iclass 14, count 0 2006.257.11:18:32.61#ibcon#read 6, iclass 14, count 0 2006.257.11:18:32.61#ibcon#end of sib2, iclass 14, count 0 2006.257.11:18:32.61#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:18:32.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:18:32.61#ibcon#[27=USB\r\n] 2006.257.11:18:32.61#ibcon#*before write, iclass 14, count 0 2006.257.11:18:32.61#ibcon#enter sib2, iclass 14, count 0 2006.257.11:18:32.61#ibcon#flushed, iclass 14, count 0 2006.257.11:18:32.61#ibcon#about to write, iclass 14, count 0 2006.257.11:18:32.61#ibcon#wrote, iclass 14, count 0 2006.257.11:18:32.61#ibcon#about to read 3, iclass 14, count 0 2006.257.11:18:32.64#ibcon#read 3, iclass 14, count 0 2006.257.11:18:32.64#ibcon#about to read 4, iclass 14, count 0 2006.257.11:18:32.64#ibcon#read 4, iclass 14, count 0 2006.257.11:18:32.64#ibcon#about to read 5, iclass 14, count 0 2006.257.11:18:32.64#ibcon#read 5, iclass 14, count 0 2006.257.11:18:32.64#ibcon#about to read 6, iclass 14, count 0 2006.257.11:18:32.64#ibcon#read 6, iclass 14, count 0 2006.257.11:18:32.64#ibcon#end of sib2, iclass 14, count 0 2006.257.11:18:32.64#ibcon#*after write, iclass 14, count 0 2006.257.11:18:32.64#ibcon#*before return 0, iclass 14, count 0 2006.257.11:18:32.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:32.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:18:32.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:18:32.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:18:32.64$vck44/vabw=wide 2006.257.11:18:32.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.11:18:32.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.11:18:32.64#ibcon#ireg 8 cls_cnt 0 2006.257.11:18:32.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:32.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:32.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:32.64#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:18:32.64#ibcon#first serial, iclass 16, count 0 2006.257.11:18:32.64#ibcon#enter sib2, iclass 16, count 0 2006.257.11:18:32.64#ibcon#flushed, iclass 16, count 0 2006.257.11:18:32.64#ibcon#about to write, iclass 16, count 0 2006.257.11:18:32.64#ibcon#wrote, iclass 16, count 0 2006.257.11:18:32.64#ibcon#about to read 3, iclass 16, count 0 2006.257.11:18:32.66#ibcon#read 3, iclass 16, count 0 2006.257.11:18:32.66#ibcon#about to read 4, iclass 16, count 0 2006.257.11:18:32.66#ibcon#read 4, iclass 16, count 0 2006.257.11:18:32.66#ibcon#about to read 5, iclass 16, count 0 2006.257.11:18:32.66#ibcon#read 5, iclass 16, count 0 2006.257.11:18:32.66#ibcon#about to read 6, iclass 16, count 0 2006.257.11:18:32.66#ibcon#read 6, iclass 16, count 0 2006.257.11:18:32.66#ibcon#end of sib2, iclass 16, count 0 2006.257.11:18:32.66#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:18:32.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:18:32.66#ibcon#[25=BW32\r\n] 2006.257.11:18:32.66#ibcon#*before write, iclass 16, count 0 2006.257.11:18:32.66#ibcon#enter sib2, iclass 16, count 0 2006.257.11:18:32.66#ibcon#flushed, iclass 16, count 0 2006.257.11:18:32.66#ibcon#about to write, iclass 16, count 0 2006.257.11:18:32.66#ibcon#wrote, iclass 16, count 0 2006.257.11:18:32.66#ibcon#about to read 3, iclass 16, count 0 2006.257.11:18:32.69#ibcon#read 3, iclass 16, count 0 2006.257.11:18:32.69#ibcon#about to read 4, iclass 16, count 0 2006.257.11:18:32.69#ibcon#read 4, iclass 16, count 0 2006.257.11:18:32.69#ibcon#about to read 5, iclass 16, count 0 2006.257.11:18:32.69#ibcon#read 5, iclass 16, count 0 2006.257.11:18:32.69#ibcon#about to read 6, iclass 16, count 0 2006.257.11:18:32.69#ibcon#read 6, iclass 16, count 0 2006.257.11:18:32.69#ibcon#end of sib2, iclass 16, count 0 2006.257.11:18:32.69#ibcon#*after write, iclass 16, count 0 2006.257.11:18:32.69#ibcon#*before return 0, iclass 16, count 0 2006.257.11:18:32.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:32.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:18:32.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:18:32.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:18:32.69$vck44/vbbw=wide 2006.257.11:18:32.69#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.11:18:32.69#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.11:18:32.69#ibcon#ireg 8 cls_cnt 0 2006.257.11:18:32.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:18:32.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:18:32.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:18:32.76#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:18:32.76#ibcon#first serial, iclass 18, count 0 2006.257.11:18:32.76#ibcon#enter sib2, iclass 18, count 0 2006.257.11:18:32.76#ibcon#flushed, iclass 18, count 0 2006.257.11:18:32.76#ibcon#about to write, iclass 18, count 0 2006.257.11:18:32.76#ibcon#wrote, iclass 18, count 0 2006.257.11:18:32.76#ibcon#about to read 3, iclass 18, count 0 2006.257.11:18:32.78#ibcon#read 3, iclass 18, count 0 2006.257.11:18:32.78#ibcon#about to read 4, iclass 18, count 0 2006.257.11:18:32.78#ibcon#read 4, iclass 18, count 0 2006.257.11:18:32.78#ibcon#about to read 5, iclass 18, count 0 2006.257.11:18:32.78#ibcon#read 5, iclass 18, count 0 2006.257.11:18:32.78#ibcon#about to read 6, iclass 18, count 0 2006.257.11:18:32.78#ibcon#read 6, iclass 18, count 0 2006.257.11:18:32.78#ibcon#end of sib2, iclass 18, count 0 2006.257.11:18:32.78#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:18:32.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:18:32.78#ibcon#[27=BW32\r\n] 2006.257.11:18:32.78#ibcon#*before write, iclass 18, count 0 2006.257.11:18:32.78#ibcon#enter sib2, iclass 18, count 0 2006.257.11:18:32.78#ibcon#flushed, iclass 18, count 0 2006.257.11:18:32.78#ibcon#about to write, iclass 18, count 0 2006.257.11:18:32.78#ibcon#wrote, iclass 18, count 0 2006.257.11:18:32.78#ibcon#about to read 3, iclass 18, count 0 2006.257.11:18:32.81#ibcon#read 3, iclass 18, count 0 2006.257.11:18:32.81#ibcon#about to read 4, iclass 18, count 0 2006.257.11:18:32.81#ibcon#read 4, iclass 18, count 0 2006.257.11:18:32.81#ibcon#about to read 5, iclass 18, count 0 2006.257.11:18:32.81#ibcon#read 5, iclass 18, count 0 2006.257.11:18:32.81#ibcon#about to read 6, iclass 18, count 0 2006.257.11:18:32.81#ibcon#read 6, iclass 18, count 0 2006.257.11:18:32.81#ibcon#end of sib2, iclass 18, count 0 2006.257.11:18:32.81#ibcon#*after write, iclass 18, count 0 2006.257.11:18:32.81#ibcon#*before return 0, iclass 18, count 0 2006.257.11:18:32.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:18:32.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:18:32.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:18:32.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:18:32.81$setupk4/ifdk4 2006.257.11:18:32.81$ifdk4/lo= 2006.257.11:18:32.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:18:32.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:18:32.81$ifdk4/patch= 2006.257.11:18:32.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:18:32.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:18:32.81$setupk4/!*+20s 2006.257.11:18:45.14#trakl#Source acquired 2006.257.11:18:47.14#flagr#flagr/antenna,acquired 2006.257.11:18:47.23$setupk4/"tpicd 2006.257.11:18:47.23$setupk4/echo=off 2006.257.11:18:47.23$setupk4/xlog=off 2006.257.11:18:47.23:!2006.257.11:20:33 2006.257.11:20:33.00:preob 2006.257.11:20:33.14/onsource/TRACKING 2006.257.11:20:33.14:!2006.257.11:20:43 2006.257.11:20:43.00:"tape 2006.257.11:20:43.00:"st=record 2006.257.11:20:43.00:data_valid=on 2006.257.11:20:43.00:midob 2006.257.11:20:44.14/onsource/TRACKING 2006.257.11:20:44.14/wx/18.32,1013.8,97 2006.257.11:20:44.28/cable/+6.4769E-03 2006.257.11:20:45.37/va/01,08,usb,yes,30,33 2006.257.11:20:45.37/va/02,07,usb,yes,33,33 2006.257.11:20:45.37/va/03,08,usb,yes,29,31 2006.257.11:20:45.37/va/04,07,usb,yes,34,36 2006.257.11:20:45.37/va/05,04,usb,yes,30,31 2006.257.11:20:45.37/va/06,04,usb,yes,34,33 2006.257.11:20:45.37/va/07,04,usb,yes,35,35 2006.257.11:20:45.37/va/08,04,usb,yes,29,36 2006.257.11:20:45.60/valo/01,524.99,yes,locked 2006.257.11:20:45.60/valo/02,534.99,yes,locked 2006.257.11:20:45.60/valo/03,564.99,yes,locked 2006.257.11:20:45.60/valo/04,624.99,yes,locked 2006.257.11:20:45.60/valo/05,734.99,yes,locked 2006.257.11:20:45.60/valo/06,814.99,yes,locked 2006.257.11:20:45.60/valo/07,864.99,yes,locked 2006.257.11:20:45.60/valo/08,884.99,yes,locked 2006.257.11:20:46.69/vb/01,04,usb,yes,31,28 2006.257.11:20:46.69/vb/02,05,usb,yes,29,29 2006.257.11:20:46.69/vb/03,04,usb,yes,30,33 2006.257.11:20:46.69/vb/04,05,usb,yes,30,29 2006.257.11:20:46.69/vb/05,04,usb,yes,26,29 2006.257.11:20:46.69/vb/06,04,usb,yes,31,27 2006.257.11:20:46.69/vb/07,04,usb,yes,31,31 2006.257.11:20:46.69/vb/08,04,usb,yes,28,32 2006.257.11:20:46.92/vblo/01,629.99,yes,locked 2006.257.11:20:46.92/vblo/02,634.99,yes,locked 2006.257.11:20:46.92/vblo/03,649.99,yes,locked 2006.257.11:20:46.92/vblo/04,679.99,yes,locked 2006.257.11:20:46.92/vblo/05,709.99,yes,locked 2006.257.11:20:46.92/vblo/06,719.99,yes,locked 2006.257.11:20:46.92/vblo/07,734.99,yes,locked 2006.257.11:20:46.92/vblo/08,744.99,yes,locked 2006.257.11:20:47.07/vabw/8 2006.257.11:20:47.22/vbbw/8 2006.257.11:20:47.31/xfe/off,on,15.2 2006.257.11:20:47.68/ifatt/23,28,28,28 2006.257.11:20:48.08/fmout-gps/S +4.59E-07 2006.257.11:20:48.12:!2006.257.11:22:53 2006.257.11:22:53.00:data_valid=off 2006.257.11:22:53.00:"et 2006.257.11:22:53.00:!+3s 2006.257.11:22:56.01:"tape 2006.257.11:22:56.01:postob 2006.257.11:22:56.24/cable/+6.4799E-03 2006.257.11:22:56.24/wx/18.28,1013.8,97 2006.257.11:22:57.08/fmout-gps/S +4.61E-07 2006.257.11:22:57.08:scan_name=257-1125,jd0609,40 2006.257.11:22:57.08:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.11:22:58.13#flagr#flagr/antenna,new-source 2006.257.11:22:58.13:checkk5 2006.257.11:22:58.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:22:58.88/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:22:59.30/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:22:59.70/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:23:00.07/chk_obsdata//k5ts1/T2571120??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.11:23:00.47/chk_obsdata//k5ts2/T2571120??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.11:23:00.87/chk_obsdata//k5ts3/T2571120??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.11:23:01.27/chk_obsdata//k5ts4/T2571120??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.11:23:01.99/k5log//k5ts1_log_newline 2006.257.11:23:02.70/k5log//k5ts2_log_newline 2006.257.11:23:03.41/k5log//k5ts3_log_newline 2006.257.11:23:04.12/k5log//k5ts4_log_newline 2006.257.11:23:04.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:23:04.15:setupk4=1 2006.257.11:23:04.15$setupk4/echo=on 2006.257.11:23:04.15$setupk4/pcalon 2006.257.11:23:04.15$pcalon/"no phase cal control is implemented here 2006.257.11:23:04.15$setupk4/"tpicd=stop 2006.257.11:23:04.15$setupk4/"rec=synch_on 2006.257.11:23:04.15$setupk4/"rec_mode=128 2006.257.11:23:04.15$setupk4/!* 2006.257.11:23:04.15$setupk4/recpk4 2006.257.11:23:04.15$recpk4/recpatch= 2006.257.11:23:04.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:23:04.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:23:04.15$setupk4/vck44 2006.257.11:23:04.15$vck44/valo=1,524.99 2006.257.11:23:04.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.11:23:04.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.11:23:04.15#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:04.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:04.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:04.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:04.15#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:23:04.15#ibcon#first serial, iclass 14, count 0 2006.257.11:23:04.15#ibcon#enter sib2, iclass 14, count 0 2006.257.11:23:04.15#ibcon#flushed, iclass 14, count 0 2006.257.11:23:04.15#ibcon#about to write, iclass 14, count 0 2006.257.11:23:04.15#ibcon#wrote, iclass 14, count 0 2006.257.11:23:04.15#ibcon#about to read 3, iclass 14, count 0 2006.257.11:23:04.17#ibcon#read 3, iclass 14, count 0 2006.257.11:23:04.17#ibcon#about to read 4, iclass 14, count 0 2006.257.11:23:04.17#ibcon#read 4, iclass 14, count 0 2006.257.11:23:04.17#ibcon#about to read 5, iclass 14, count 0 2006.257.11:23:04.17#ibcon#read 5, iclass 14, count 0 2006.257.11:23:04.17#ibcon#about to read 6, iclass 14, count 0 2006.257.11:23:04.17#ibcon#read 6, iclass 14, count 0 2006.257.11:23:04.17#ibcon#end of sib2, iclass 14, count 0 2006.257.11:23:04.17#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:23:04.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:23:04.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:23:04.17#ibcon#*before write, iclass 14, count 0 2006.257.11:23:04.17#ibcon#enter sib2, iclass 14, count 0 2006.257.11:23:04.17#ibcon#flushed, iclass 14, count 0 2006.257.11:23:04.17#ibcon#about to write, iclass 14, count 0 2006.257.11:23:04.17#ibcon#wrote, iclass 14, count 0 2006.257.11:23:04.17#ibcon#about to read 3, iclass 14, count 0 2006.257.11:23:04.22#ibcon#read 3, iclass 14, count 0 2006.257.11:23:04.22#ibcon#about to read 4, iclass 14, count 0 2006.257.11:23:04.22#ibcon#read 4, iclass 14, count 0 2006.257.11:23:04.22#ibcon#about to read 5, iclass 14, count 0 2006.257.11:23:04.22#ibcon#read 5, iclass 14, count 0 2006.257.11:23:04.22#ibcon#about to read 6, iclass 14, count 0 2006.257.11:23:04.22#ibcon#read 6, iclass 14, count 0 2006.257.11:23:04.22#ibcon#end of sib2, iclass 14, count 0 2006.257.11:23:04.22#ibcon#*after write, iclass 14, count 0 2006.257.11:23:04.22#ibcon#*before return 0, iclass 14, count 0 2006.257.11:23:04.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:04.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:04.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:23:04.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:23:04.22$vck44/va=1,8 2006.257.11:23:04.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.11:23:04.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.11:23:04.22#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:04.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:04.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:04.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:04.22#ibcon#enter wrdev, iclass 16, count 2 2006.257.11:23:04.22#ibcon#first serial, iclass 16, count 2 2006.257.11:23:04.22#ibcon#enter sib2, iclass 16, count 2 2006.257.11:23:04.22#ibcon#flushed, iclass 16, count 2 2006.257.11:23:04.22#ibcon#about to write, iclass 16, count 2 2006.257.11:23:04.22#ibcon#wrote, iclass 16, count 2 2006.257.11:23:04.22#ibcon#about to read 3, iclass 16, count 2 2006.257.11:23:04.24#ibcon#read 3, iclass 16, count 2 2006.257.11:23:04.24#ibcon#about to read 4, iclass 16, count 2 2006.257.11:23:04.24#ibcon#read 4, iclass 16, count 2 2006.257.11:23:04.24#ibcon#about to read 5, iclass 16, count 2 2006.257.11:23:04.24#ibcon#read 5, iclass 16, count 2 2006.257.11:23:04.24#ibcon#about to read 6, iclass 16, count 2 2006.257.11:23:04.24#ibcon#read 6, iclass 16, count 2 2006.257.11:23:04.24#ibcon#end of sib2, iclass 16, count 2 2006.257.11:23:04.24#ibcon#*mode == 0, iclass 16, count 2 2006.257.11:23:04.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.11:23:04.24#ibcon#[25=AT01-08\r\n] 2006.257.11:23:04.24#ibcon#*before write, iclass 16, count 2 2006.257.11:23:04.24#ibcon#enter sib2, iclass 16, count 2 2006.257.11:23:04.24#ibcon#flushed, iclass 16, count 2 2006.257.11:23:04.24#ibcon#about to write, iclass 16, count 2 2006.257.11:23:04.24#ibcon#wrote, iclass 16, count 2 2006.257.11:23:04.24#ibcon#about to read 3, iclass 16, count 2 2006.257.11:23:04.27#ibcon#read 3, iclass 16, count 2 2006.257.11:23:04.27#ibcon#about to read 4, iclass 16, count 2 2006.257.11:23:04.27#ibcon#read 4, iclass 16, count 2 2006.257.11:23:04.27#ibcon#about to read 5, iclass 16, count 2 2006.257.11:23:04.27#ibcon#read 5, iclass 16, count 2 2006.257.11:23:04.27#ibcon#about to read 6, iclass 16, count 2 2006.257.11:23:04.27#ibcon#read 6, iclass 16, count 2 2006.257.11:23:04.27#ibcon#end of sib2, iclass 16, count 2 2006.257.11:23:04.27#ibcon#*after write, iclass 16, count 2 2006.257.11:23:04.27#ibcon#*before return 0, iclass 16, count 2 2006.257.11:23:04.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:04.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:04.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.11:23:04.27#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:04.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:04.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:04.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:04.39#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:23:04.39#ibcon#first serial, iclass 16, count 0 2006.257.11:23:04.39#ibcon#enter sib2, iclass 16, count 0 2006.257.11:23:04.39#ibcon#flushed, iclass 16, count 0 2006.257.11:23:04.39#ibcon#about to write, iclass 16, count 0 2006.257.11:23:04.39#ibcon#wrote, iclass 16, count 0 2006.257.11:23:04.39#ibcon#about to read 3, iclass 16, count 0 2006.257.11:23:04.41#ibcon#read 3, iclass 16, count 0 2006.257.11:23:04.41#ibcon#about to read 4, iclass 16, count 0 2006.257.11:23:04.41#ibcon#read 4, iclass 16, count 0 2006.257.11:23:04.41#ibcon#about to read 5, iclass 16, count 0 2006.257.11:23:04.41#ibcon#read 5, iclass 16, count 0 2006.257.11:23:04.41#ibcon#about to read 6, iclass 16, count 0 2006.257.11:23:04.41#ibcon#read 6, iclass 16, count 0 2006.257.11:23:04.41#ibcon#end of sib2, iclass 16, count 0 2006.257.11:23:04.41#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:23:04.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:23:04.41#ibcon#[25=USB\r\n] 2006.257.11:23:04.41#ibcon#*before write, iclass 16, count 0 2006.257.11:23:04.41#ibcon#enter sib2, iclass 16, count 0 2006.257.11:23:04.41#ibcon#flushed, iclass 16, count 0 2006.257.11:23:04.41#ibcon#about to write, iclass 16, count 0 2006.257.11:23:04.41#ibcon#wrote, iclass 16, count 0 2006.257.11:23:04.41#ibcon#about to read 3, iclass 16, count 0 2006.257.11:23:04.44#ibcon#read 3, iclass 16, count 0 2006.257.11:23:04.44#ibcon#about to read 4, iclass 16, count 0 2006.257.11:23:04.44#ibcon#read 4, iclass 16, count 0 2006.257.11:23:04.44#ibcon#about to read 5, iclass 16, count 0 2006.257.11:23:04.44#ibcon#read 5, iclass 16, count 0 2006.257.11:23:04.44#ibcon#about to read 6, iclass 16, count 0 2006.257.11:23:04.44#ibcon#read 6, iclass 16, count 0 2006.257.11:23:04.44#ibcon#end of sib2, iclass 16, count 0 2006.257.11:23:04.44#ibcon#*after write, iclass 16, count 0 2006.257.11:23:04.44#ibcon#*before return 0, iclass 16, count 0 2006.257.11:23:04.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:04.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:04.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:23:04.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:23:04.44$vck44/valo=2,534.99 2006.257.11:23:04.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.11:23:04.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.11:23:04.44#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:04.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:04.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:04.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:04.44#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:23:04.44#ibcon#first serial, iclass 18, count 0 2006.257.11:23:04.44#ibcon#enter sib2, iclass 18, count 0 2006.257.11:23:04.44#ibcon#flushed, iclass 18, count 0 2006.257.11:23:04.44#ibcon#about to write, iclass 18, count 0 2006.257.11:23:04.44#ibcon#wrote, iclass 18, count 0 2006.257.11:23:04.44#ibcon#about to read 3, iclass 18, count 0 2006.257.11:23:04.46#ibcon#read 3, iclass 18, count 0 2006.257.11:23:04.46#ibcon#about to read 4, iclass 18, count 0 2006.257.11:23:04.46#ibcon#read 4, iclass 18, count 0 2006.257.11:23:04.46#ibcon#about to read 5, iclass 18, count 0 2006.257.11:23:04.46#ibcon#read 5, iclass 18, count 0 2006.257.11:23:04.46#ibcon#about to read 6, iclass 18, count 0 2006.257.11:23:04.46#ibcon#read 6, iclass 18, count 0 2006.257.11:23:04.46#ibcon#end of sib2, iclass 18, count 0 2006.257.11:23:04.46#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:23:04.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:23:04.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:23:04.46#ibcon#*before write, iclass 18, count 0 2006.257.11:23:04.46#ibcon#enter sib2, iclass 18, count 0 2006.257.11:23:04.46#ibcon#flushed, iclass 18, count 0 2006.257.11:23:04.46#ibcon#about to write, iclass 18, count 0 2006.257.11:23:04.46#ibcon#wrote, iclass 18, count 0 2006.257.11:23:04.46#ibcon#about to read 3, iclass 18, count 0 2006.257.11:23:04.50#ibcon#read 3, iclass 18, count 0 2006.257.11:23:04.50#ibcon#about to read 4, iclass 18, count 0 2006.257.11:23:04.50#ibcon#read 4, iclass 18, count 0 2006.257.11:23:04.50#ibcon#about to read 5, iclass 18, count 0 2006.257.11:23:04.50#ibcon#read 5, iclass 18, count 0 2006.257.11:23:04.50#ibcon#about to read 6, iclass 18, count 0 2006.257.11:23:04.50#ibcon#read 6, iclass 18, count 0 2006.257.11:23:04.50#ibcon#end of sib2, iclass 18, count 0 2006.257.11:23:04.50#ibcon#*after write, iclass 18, count 0 2006.257.11:23:04.50#ibcon#*before return 0, iclass 18, count 0 2006.257.11:23:04.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:04.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:04.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:23:04.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:23:04.50$vck44/va=2,7 2006.257.11:23:04.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.11:23:04.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.11:23:04.50#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:04.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:04.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:04.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:04.56#ibcon#enter wrdev, iclass 20, count 2 2006.257.11:23:04.56#ibcon#first serial, iclass 20, count 2 2006.257.11:23:04.56#ibcon#enter sib2, iclass 20, count 2 2006.257.11:23:04.56#ibcon#flushed, iclass 20, count 2 2006.257.11:23:04.56#ibcon#about to write, iclass 20, count 2 2006.257.11:23:04.56#ibcon#wrote, iclass 20, count 2 2006.257.11:23:04.56#ibcon#about to read 3, iclass 20, count 2 2006.257.11:23:04.58#ibcon#read 3, iclass 20, count 2 2006.257.11:23:04.58#ibcon#about to read 4, iclass 20, count 2 2006.257.11:23:04.58#ibcon#read 4, iclass 20, count 2 2006.257.11:23:04.58#ibcon#about to read 5, iclass 20, count 2 2006.257.11:23:04.58#ibcon#read 5, iclass 20, count 2 2006.257.11:23:04.58#ibcon#about to read 6, iclass 20, count 2 2006.257.11:23:04.58#ibcon#read 6, iclass 20, count 2 2006.257.11:23:04.58#ibcon#end of sib2, iclass 20, count 2 2006.257.11:23:04.58#ibcon#*mode == 0, iclass 20, count 2 2006.257.11:23:04.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.11:23:04.58#ibcon#[25=AT02-07\r\n] 2006.257.11:23:04.58#ibcon#*before write, iclass 20, count 2 2006.257.11:23:04.58#ibcon#enter sib2, iclass 20, count 2 2006.257.11:23:04.58#ibcon#flushed, iclass 20, count 2 2006.257.11:23:04.58#ibcon#about to write, iclass 20, count 2 2006.257.11:23:04.58#ibcon#wrote, iclass 20, count 2 2006.257.11:23:04.58#ibcon#about to read 3, iclass 20, count 2 2006.257.11:23:04.61#ibcon#read 3, iclass 20, count 2 2006.257.11:23:04.61#ibcon#about to read 4, iclass 20, count 2 2006.257.11:23:04.61#ibcon#read 4, iclass 20, count 2 2006.257.11:23:04.61#ibcon#about to read 5, iclass 20, count 2 2006.257.11:23:04.61#ibcon#read 5, iclass 20, count 2 2006.257.11:23:04.61#ibcon#about to read 6, iclass 20, count 2 2006.257.11:23:04.61#ibcon#read 6, iclass 20, count 2 2006.257.11:23:04.61#ibcon#end of sib2, iclass 20, count 2 2006.257.11:23:04.61#ibcon#*after write, iclass 20, count 2 2006.257.11:23:04.61#ibcon#*before return 0, iclass 20, count 2 2006.257.11:23:04.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:04.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:04.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.11:23:04.61#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:04.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:04.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:04.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:04.73#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:23:04.73#ibcon#first serial, iclass 20, count 0 2006.257.11:23:04.73#ibcon#enter sib2, iclass 20, count 0 2006.257.11:23:04.73#ibcon#flushed, iclass 20, count 0 2006.257.11:23:04.73#ibcon#about to write, iclass 20, count 0 2006.257.11:23:04.73#ibcon#wrote, iclass 20, count 0 2006.257.11:23:04.73#ibcon#about to read 3, iclass 20, count 0 2006.257.11:23:04.75#ibcon#read 3, iclass 20, count 0 2006.257.11:23:04.75#ibcon#about to read 4, iclass 20, count 0 2006.257.11:23:04.75#ibcon#read 4, iclass 20, count 0 2006.257.11:23:04.75#ibcon#about to read 5, iclass 20, count 0 2006.257.11:23:04.75#ibcon#read 5, iclass 20, count 0 2006.257.11:23:04.75#ibcon#about to read 6, iclass 20, count 0 2006.257.11:23:04.75#ibcon#read 6, iclass 20, count 0 2006.257.11:23:04.75#ibcon#end of sib2, iclass 20, count 0 2006.257.11:23:04.75#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:23:04.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:23:04.75#ibcon#[25=USB\r\n] 2006.257.11:23:04.75#ibcon#*before write, iclass 20, count 0 2006.257.11:23:04.75#ibcon#enter sib2, iclass 20, count 0 2006.257.11:23:04.75#ibcon#flushed, iclass 20, count 0 2006.257.11:23:04.75#ibcon#about to write, iclass 20, count 0 2006.257.11:23:04.75#ibcon#wrote, iclass 20, count 0 2006.257.11:23:04.75#ibcon#about to read 3, iclass 20, count 0 2006.257.11:23:04.78#ibcon#read 3, iclass 20, count 0 2006.257.11:23:04.78#ibcon#about to read 4, iclass 20, count 0 2006.257.11:23:04.78#ibcon#read 4, iclass 20, count 0 2006.257.11:23:04.78#ibcon#about to read 5, iclass 20, count 0 2006.257.11:23:04.78#ibcon#read 5, iclass 20, count 0 2006.257.11:23:04.78#ibcon#about to read 6, iclass 20, count 0 2006.257.11:23:04.78#ibcon#read 6, iclass 20, count 0 2006.257.11:23:04.78#ibcon#end of sib2, iclass 20, count 0 2006.257.11:23:04.78#ibcon#*after write, iclass 20, count 0 2006.257.11:23:04.78#ibcon#*before return 0, iclass 20, count 0 2006.257.11:23:04.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:04.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:04.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:23:04.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:23:04.78$vck44/valo=3,564.99 2006.257.11:23:04.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.11:23:04.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.11:23:04.78#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:04.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:04.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:04.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:04.78#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:23:04.78#ibcon#first serial, iclass 22, count 0 2006.257.11:23:04.78#ibcon#enter sib2, iclass 22, count 0 2006.257.11:23:04.78#ibcon#flushed, iclass 22, count 0 2006.257.11:23:04.78#ibcon#about to write, iclass 22, count 0 2006.257.11:23:04.78#ibcon#wrote, iclass 22, count 0 2006.257.11:23:04.78#ibcon#about to read 3, iclass 22, count 0 2006.257.11:23:04.80#ibcon#read 3, iclass 22, count 0 2006.257.11:23:04.80#ibcon#about to read 4, iclass 22, count 0 2006.257.11:23:04.80#ibcon#read 4, iclass 22, count 0 2006.257.11:23:04.80#ibcon#about to read 5, iclass 22, count 0 2006.257.11:23:04.80#ibcon#read 5, iclass 22, count 0 2006.257.11:23:04.80#ibcon#about to read 6, iclass 22, count 0 2006.257.11:23:04.80#ibcon#read 6, iclass 22, count 0 2006.257.11:23:04.80#ibcon#end of sib2, iclass 22, count 0 2006.257.11:23:04.80#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:23:04.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:23:04.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:23:04.80#ibcon#*before write, iclass 22, count 0 2006.257.11:23:04.80#ibcon#enter sib2, iclass 22, count 0 2006.257.11:23:04.80#ibcon#flushed, iclass 22, count 0 2006.257.11:23:04.80#ibcon#about to write, iclass 22, count 0 2006.257.11:23:04.80#ibcon#wrote, iclass 22, count 0 2006.257.11:23:04.80#ibcon#about to read 3, iclass 22, count 0 2006.257.11:23:04.84#ibcon#read 3, iclass 22, count 0 2006.257.11:23:04.84#ibcon#about to read 4, iclass 22, count 0 2006.257.11:23:04.84#ibcon#read 4, iclass 22, count 0 2006.257.11:23:04.84#ibcon#about to read 5, iclass 22, count 0 2006.257.11:23:04.84#ibcon#read 5, iclass 22, count 0 2006.257.11:23:04.84#ibcon#about to read 6, iclass 22, count 0 2006.257.11:23:04.84#ibcon#read 6, iclass 22, count 0 2006.257.11:23:04.84#ibcon#end of sib2, iclass 22, count 0 2006.257.11:23:04.84#ibcon#*after write, iclass 22, count 0 2006.257.11:23:04.84#ibcon#*before return 0, iclass 22, count 0 2006.257.11:23:04.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:04.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:04.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:23:04.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:23:04.84$vck44/va=3,8 2006.257.11:23:04.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.11:23:04.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.11:23:04.84#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:04.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:04.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:04.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:04.90#ibcon#enter wrdev, iclass 24, count 2 2006.257.11:23:04.90#ibcon#first serial, iclass 24, count 2 2006.257.11:23:04.90#ibcon#enter sib2, iclass 24, count 2 2006.257.11:23:04.90#ibcon#flushed, iclass 24, count 2 2006.257.11:23:04.90#ibcon#about to write, iclass 24, count 2 2006.257.11:23:04.90#ibcon#wrote, iclass 24, count 2 2006.257.11:23:04.90#ibcon#about to read 3, iclass 24, count 2 2006.257.11:23:04.92#ibcon#read 3, iclass 24, count 2 2006.257.11:23:04.92#ibcon#about to read 4, iclass 24, count 2 2006.257.11:23:04.92#ibcon#read 4, iclass 24, count 2 2006.257.11:23:04.92#ibcon#about to read 5, iclass 24, count 2 2006.257.11:23:04.92#ibcon#read 5, iclass 24, count 2 2006.257.11:23:04.92#ibcon#about to read 6, iclass 24, count 2 2006.257.11:23:04.92#ibcon#read 6, iclass 24, count 2 2006.257.11:23:04.92#ibcon#end of sib2, iclass 24, count 2 2006.257.11:23:04.92#ibcon#*mode == 0, iclass 24, count 2 2006.257.11:23:04.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.11:23:04.92#ibcon#[25=AT03-08\r\n] 2006.257.11:23:04.92#ibcon#*before write, iclass 24, count 2 2006.257.11:23:04.92#ibcon#enter sib2, iclass 24, count 2 2006.257.11:23:04.92#ibcon#flushed, iclass 24, count 2 2006.257.11:23:04.92#ibcon#about to write, iclass 24, count 2 2006.257.11:23:04.92#ibcon#wrote, iclass 24, count 2 2006.257.11:23:04.92#ibcon#about to read 3, iclass 24, count 2 2006.257.11:23:04.95#ibcon#read 3, iclass 24, count 2 2006.257.11:23:04.95#ibcon#about to read 4, iclass 24, count 2 2006.257.11:23:04.95#ibcon#read 4, iclass 24, count 2 2006.257.11:23:04.95#ibcon#about to read 5, iclass 24, count 2 2006.257.11:23:04.95#ibcon#read 5, iclass 24, count 2 2006.257.11:23:04.95#ibcon#about to read 6, iclass 24, count 2 2006.257.11:23:04.95#ibcon#read 6, iclass 24, count 2 2006.257.11:23:04.95#ibcon#end of sib2, iclass 24, count 2 2006.257.11:23:04.95#ibcon#*after write, iclass 24, count 2 2006.257.11:23:04.95#ibcon#*before return 0, iclass 24, count 2 2006.257.11:23:04.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:04.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:04.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.11:23:04.95#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:04.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:05.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:05.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:05.07#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:23:05.07#ibcon#first serial, iclass 24, count 0 2006.257.11:23:05.07#ibcon#enter sib2, iclass 24, count 0 2006.257.11:23:05.07#ibcon#flushed, iclass 24, count 0 2006.257.11:23:05.07#ibcon#about to write, iclass 24, count 0 2006.257.11:23:05.07#ibcon#wrote, iclass 24, count 0 2006.257.11:23:05.07#ibcon#about to read 3, iclass 24, count 0 2006.257.11:23:05.09#ibcon#read 3, iclass 24, count 0 2006.257.11:23:05.09#ibcon#about to read 4, iclass 24, count 0 2006.257.11:23:05.09#ibcon#read 4, iclass 24, count 0 2006.257.11:23:05.09#ibcon#about to read 5, iclass 24, count 0 2006.257.11:23:05.09#ibcon#read 5, iclass 24, count 0 2006.257.11:23:05.09#ibcon#about to read 6, iclass 24, count 0 2006.257.11:23:05.09#ibcon#read 6, iclass 24, count 0 2006.257.11:23:05.09#ibcon#end of sib2, iclass 24, count 0 2006.257.11:23:05.09#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:23:05.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:23:05.09#ibcon#[25=USB\r\n] 2006.257.11:23:05.09#ibcon#*before write, iclass 24, count 0 2006.257.11:23:05.09#ibcon#enter sib2, iclass 24, count 0 2006.257.11:23:05.09#ibcon#flushed, iclass 24, count 0 2006.257.11:23:05.09#ibcon#about to write, iclass 24, count 0 2006.257.11:23:05.09#ibcon#wrote, iclass 24, count 0 2006.257.11:23:05.09#ibcon#about to read 3, iclass 24, count 0 2006.257.11:23:05.12#ibcon#read 3, iclass 24, count 0 2006.257.11:23:05.12#ibcon#about to read 4, iclass 24, count 0 2006.257.11:23:05.12#ibcon#read 4, iclass 24, count 0 2006.257.11:23:05.12#ibcon#about to read 5, iclass 24, count 0 2006.257.11:23:05.12#ibcon#read 5, iclass 24, count 0 2006.257.11:23:05.12#ibcon#about to read 6, iclass 24, count 0 2006.257.11:23:05.12#ibcon#read 6, iclass 24, count 0 2006.257.11:23:05.12#ibcon#end of sib2, iclass 24, count 0 2006.257.11:23:05.12#ibcon#*after write, iclass 24, count 0 2006.257.11:23:05.12#ibcon#*before return 0, iclass 24, count 0 2006.257.11:23:05.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:05.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:05.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:23:05.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:23:05.12$vck44/valo=4,624.99 2006.257.11:23:05.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.11:23:05.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.11:23:05.12#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:05.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:05.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:05.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:05.12#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:23:05.12#ibcon#first serial, iclass 26, count 0 2006.257.11:23:05.12#ibcon#enter sib2, iclass 26, count 0 2006.257.11:23:05.12#ibcon#flushed, iclass 26, count 0 2006.257.11:23:05.12#ibcon#about to write, iclass 26, count 0 2006.257.11:23:05.12#ibcon#wrote, iclass 26, count 0 2006.257.11:23:05.12#ibcon#about to read 3, iclass 26, count 0 2006.257.11:23:05.14#ibcon#read 3, iclass 26, count 0 2006.257.11:23:05.14#ibcon#about to read 4, iclass 26, count 0 2006.257.11:23:05.14#ibcon#read 4, iclass 26, count 0 2006.257.11:23:05.14#ibcon#about to read 5, iclass 26, count 0 2006.257.11:23:05.14#ibcon#read 5, iclass 26, count 0 2006.257.11:23:05.14#ibcon#about to read 6, iclass 26, count 0 2006.257.11:23:05.14#ibcon#read 6, iclass 26, count 0 2006.257.11:23:05.14#ibcon#end of sib2, iclass 26, count 0 2006.257.11:23:05.14#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:23:05.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:23:05.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:23:05.14#ibcon#*before write, iclass 26, count 0 2006.257.11:23:05.14#ibcon#enter sib2, iclass 26, count 0 2006.257.11:23:05.14#ibcon#flushed, iclass 26, count 0 2006.257.11:23:05.14#ibcon#about to write, iclass 26, count 0 2006.257.11:23:05.14#ibcon#wrote, iclass 26, count 0 2006.257.11:23:05.14#ibcon#about to read 3, iclass 26, count 0 2006.257.11:23:05.18#ibcon#read 3, iclass 26, count 0 2006.257.11:23:05.18#ibcon#about to read 4, iclass 26, count 0 2006.257.11:23:05.18#ibcon#read 4, iclass 26, count 0 2006.257.11:23:05.18#ibcon#about to read 5, iclass 26, count 0 2006.257.11:23:05.18#ibcon#read 5, iclass 26, count 0 2006.257.11:23:05.18#ibcon#about to read 6, iclass 26, count 0 2006.257.11:23:05.18#ibcon#read 6, iclass 26, count 0 2006.257.11:23:05.18#ibcon#end of sib2, iclass 26, count 0 2006.257.11:23:05.18#ibcon#*after write, iclass 26, count 0 2006.257.11:23:05.18#ibcon#*before return 0, iclass 26, count 0 2006.257.11:23:05.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:05.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:05.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:23:05.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:23:05.18$vck44/va=4,7 2006.257.11:23:05.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.11:23:05.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.11:23:05.18#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:05.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:05.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:05.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:05.24#ibcon#enter wrdev, iclass 28, count 2 2006.257.11:23:05.24#ibcon#first serial, iclass 28, count 2 2006.257.11:23:05.24#ibcon#enter sib2, iclass 28, count 2 2006.257.11:23:05.24#ibcon#flushed, iclass 28, count 2 2006.257.11:23:05.24#ibcon#about to write, iclass 28, count 2 2006.257.11:23:05.24#ibcon#wrote, iclass 28, count 2 2006.257.11:23:05.24#ibcon#about to read 3, iclass 28, count 2 2006.257.11:23:05.26#ibcon#read 3, iclass 28, count 2 2006.257.11:23:05.26#ibcon#about to read 4, iclass 28, count 2 2006.257.11:23:05.26#ibcon#read 4, iclass 28, count 2 2006.257.11:23:05.26#ibcon#about to read 5, iclass 28, count 2 2006.257.11:23:05.26#ibcon#read 5, iclass 28, count 2 2006.257.11:23:05.26#ibcon#about to read 6, iclass 28, count 2 2006.257.11:23:05.26#ibcon#read 6, iclass 28, count 2 2006.257.11:23:05.26#ibcon#end of sib2, iclass 28, count 2 2006.257.11:23:05.26#ibcon#*mode == 0, iclass 28, count 2 2006.257.11:23:05.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.11:23:05.26#ibcon#[25=AT04-07\r\n] 2006.257.11:23:05.26#ibcon#*before write, iclass 28, count 2 2006.257.11:23:05.26#ibcon#enter sib2, iclass 28, count 2 2006.257.11:23:05.26#ibcon#flushed, iclass 28, count 2 2006.257.11:23:05.26#ibcon#about to write, iclass 28, count 2 2006.257.11:23:05.26#ibcon#wrote, iclass 28, count 2 2006.257.11:23:05.26#ibcon#about to read 3, iclass 28, count 2 2006.257.11:23:05.29#ibcon#read 3, iclass 28, count 2 2006.257.11:23:05.29#ibcon#about to read 4, iclass 28, count 2 2006.257.11:23:05.29#ibcon#read 4, iclass 28, count 2 2006.257.11:23:05.29#ibcon#about to read 5, iclass 28, count 2 2006.257.11:23:05.29#ibcon#read 5, iclass 28, count 2 2006.257.11:23:05.29#ibcon#about to read 6, iclass 28, count 2 2006.257.11:23:05.29#ibcon#read 6, iclass 28, count 2 2006.257.11:23:05.29#ibcon#end of sib2, iclass 28, count 2 2006.257.11:23:05.29#ibcon#*after write, iclass 28, count 2 2006.257.11:23:05.29#ibcon#*before return 0, iclass 28, count 2 2006.257.11:23:05.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:05.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:05.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.11:23:05.29#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:05.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:05.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:05.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:05.41#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:23:05.41#ibcon#first serial, iclass 28, count 0 2006.257.11:23:05.41#ibcon#enter sib2, iclass 28, count 0 2006.257.11:23:05.41#ibcon#flushed, iclass 28, count 0 2006.257.11:23:05.41#ibcon#about to write, iclass 28, count 0 2006.257.11:23:05.41#ibcon#wrote, iclass 28, count 0 2006.257.11:23:05.41#ibcon#about to read 3, iclass 28, count 0 2006.257.11:23:05.43#ibcon#read 3, iclass 28, count 0 2006.257.11:23:05.43#ibcon#about to read 4, iclass 28, count 0 2006.257.11:23:05.43#ibcon#read 4, iclass 28, count 0 2006.257.11:23:05.43#ibcon#about to read 5, iclass 28, count 0 2006.257.11:23:05.43#ibcon#read 5, iclass 28, count 0 2006.257.11:23:05.43#ibcon#about to read 6, iclass 28, count 0 2006.257.11:23:05.43#ibcon#read 6, iclass 28, count 0 2006.257.11:23:05.43#ibcon#end of sib2, iclass 28, count 0 2006.257.11:23:05.43#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:23:05.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:23:05.43#ibcon#[25=USB\r\n] 2006.257.11:23:05.43#ibcon#*before write, iclass 28, count 0 2006.257.11:23:05.43#ibcon#enter sib2, iclass 28, count 0 2006.257.11:23:05.43#ibcon#flushed, iclass 28, count 0 2006.257.11:23:05.43#ibcon#about to write, iclass 28, count 0 2006.257.11:23:05.43#ibcon#wrote, iclass 28, count 0 2006.257.11:23:05.43#ibcon#about to read 3, iclass 28, count 0 2006.257.11:23:05.46#ibcon#read 3, iclass 28, count 0 2006.257.11:23:05.46#ibcon#about to read 4, iclass 28, count 0 2006.257.11:23:05.46#ibcon#read 4, iclass 28, count 0 2006.257.11:23:05.46#ibcon#about to read 5, iclass 28, count 0 2006.257.11:23:05.46#ibcon#read 5, iclass 28, count 0 2006.257.11:23:05.46#ibcon#about to read 6, iclass 28, count 0 2006.257.11:23:05.46#ibcon#read 6, iclass 28, count 0 2006.257.11:23:05.46#ibcon#end of sib2, iclass 28, count 0 2006.257.11:23:05.46#ibcon#*after write, iclass 28, count 0 2006.257.11:23:05.46#ibcon#*before return 0, iclass 28, count 0 2006.257.11:23:05.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:05.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:05.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:23:05.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:23:05.46$vck44/valo=5,734.99 2006.257.11:23:05.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.11:23:05.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.11:23:05.46#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:05.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:05.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:05.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:05.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:23:05.46#ibcon#first serial, iclass 30, count 0 2006.257.11:23:05.46#ibcon#enter sib2, iclass 30, count 0 2006.257.11:23:05.46#ibcon#flushed, iclass 30, count 0 2006.257.11:23:05.46#ibcon#about to write, iclass 30, count 0 2006.257.11:23:05.46#ibcon#wrote, iclass 30, count 0 2006.257.11:23:05.46#ibcon#about to read 3, iclass 30, count 0 2006.257.11:23:05.48#ibcon#read 3, iclass 30, count 0 2006.257.11:23:05.48#ibcon#about to read 4, iclass 30, count 0 2006.257.11:23:05.48#ibcon#read 4, iclass 30, count 0 2006.257.11:23:05.48#ibcon#about to read 5, iclass 30, count 0 2006.257.11:23:05.48#ibcon#read 5, iclass 30, count 0 2006.257.11:23:05.48#ibcon#about to read 6, iclass 30, count 0 2006.257.11:23:05.48#ibcon#read 6, iclass 30, count 0 2006.257.11:23:05.48#ibcon#end of sib2, iclass 30, count 0 2006.257.11:23:05.48#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:23:05.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:23:05.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:23:05.48#ibcon#*before write, iclass 30, count 0 2006.257.11:23:05.48#ibcon#enter sib2, iclass 30, count 0 2006.257.11:23:05.48#ibcon#flushed, iclass 30, count 0 2006.257.11:23:05.48#ibcon#about to write, iclass 30, count 0 2006.257.11:23:05.48#ibcon#wrote, iclass 30, count 0 2006.257.11:23:05.48#ibcon#about to read 3, iclass 30, count 0 2006.257.11:23:05.52#ibcon#read 3, iclass 30, count 0 2006.257.11:23:05.52#ibcon#about to read 4, iclass 30, count 0 2006.257.11:23:05.52#ibcon#read 4, iclass 30, count 0 2006.257.11:23:05.52#ibcon#about to read 5, iclass 30, count 0 2006.257.11:23:05.52#ibcon#read 5, iclass 30, count 0 2006.257.11:23:05.52#ibcon#about to read 6, iclass 30, count 0 2006.257.11:23:05.52#ibcon#read 6, iclass 30, count 0 2006.257.11:23:05.52#ibcon#end of sib2, iclass 30, count 0 2006.257.11:23:05.52#ibcon#*after write, iclass 30, count 0 2006.257.11:23:05.52#ibcon#*before return 0, iclass 30, count 0 2006.257.11:23:05.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:05.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:05.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:23:05.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:23:05.52$vck44/va=5,4 2006.257.11:23:05.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.11:23:05.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.11:23:05.52#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:05.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:05.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:05.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:05.58#ibcon#enter wrdev, iclass 32, count 2 2006.257.11:23:05.58#ibcon#first serial, iclass 32, count 2 2006.257.11:23:05.58#ibcon#enter sib2, iclass 32, count 2 2006.257.11:23:05.58#ibcon#flushed, iclass 32, count 2 2006.257.11:23:05.58#ibcon#about to write, iclass 32, count 2 2006.257.11:23:05.58#ibcon#wrote, iclass 32, count 2 2006.257.11:23:05.58#ibcon#about to read 3, iclass 32, count 2 2006.257.11:23:05.60#ibcon#read 3, iclass 32, count 2 2006.257.11:23:05.60#ibcon#about to read 4, iclass 32, count 2 2006.257.11:23:05.60#ibcon#read 4, iclass 32, count 2 2006.257.11:23:05.60#ibcon#about to read 5, iclass 32, count 2 2006.257.11:23:05.60#ibcon#read 5, iclass 32, count 2 2006.257.11:23:05.60#ibcon#about to read 6, iclass 32, count 2 2006.257.11:23:05.60#ibcon#read 6, iclass 32, count 2 2006.257.11:23:05.60#ibcon#end of sib2, iclass 32, count 2 2006.257.11:23:05.60#ibcon#*mode == 0, iclass 32, count 2 2006.257.11:23:05.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.11:23:05.60#ibcon#[25=AT05-04\r\n] 2006.257.11:23:05.60#ibcon#*before write, iclass 32, count 2 2006.257.11:23:05.60#ibcon#enter sib2, iclass 32, count 2 2006.257.11:23:05.60#ibcon#flushed, iclass 32, count 2 2006.257.11:23:05.60#ibcon#about to write, iclass 32, count 2 2006.257.11:23:05.60#ibcon#wrote, iclass 32, count 2 2006.257.11:23:05.60#ibcon#about to read 3, iclass 32, count 2 2006.257.11:23:05.63#ibcon#read 3, iclass 32, count 2 2006.257.11:23:05.63#ibcon#about to read 4, iclass 32, count 2 2006.257.11:23:05.63#ibcon#read 4, iclass 32, count 2 2006.257.11:23:05.63#ibcon#about to read 5, iclass 32, count 2 2006.257.11:23:05.63#ibcon#read 5, iclass 32, count 2 2006.257.11:23:05.63#ibcon#about to read 6, iclass 32, count 2 2006.257.11:23:05.63#ibcon#read 6, iclass 32, count 2 2006.257.11:23:05.63#ibcon#end of sib2, iclass 32, count 2 2006.257.11:23:05.63#ibcon#*after write, iclass 32, count 2 2006.257.11:23:05.63#ibcon#*before return 0, iclass 32, count 2 2006.257.11:23:05.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:05.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:05.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.11:23:05.63#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:05.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:05.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:05.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:05.75#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:23:05.75#ibcon#first serial, iclass 32, count 0 2006.257.11:23:05.75#ibcon#enter sib2, iclass 32, count 0 2006.257.11:23:05.75#ibcon#flushed, iclass 32, count 0 2006.257.11:23:05.75#ibcon#about to write, iclass 32, count 0 2006.257.11:23:05.75#ibcon#wrote, iclass 32, count 0 2006.257.11:23:05.75#ibcon#about to read 3, iclass 32, count 0 2006.257.11:23:05.77#ibcon#read 3, iclass 32, count 0 2006.257.11:23:05.77#ibcon#about to read 4, iclass 32, count 0 2006.257.11:23:05.77#ibcon#read 4, iclass 32, count 0 2006.257.11:23:05.77#ibcon#about to read 5, iclass 32, count 0 2006.257.11:23:05.77#ibcon#read 5, iclass 32, count 0 2006.257.11:23:05.77#ibcon#about to read 6, iclass 32, count 0 2006.257.11:23:05.77#ibcon#read 6, iclass 32, count 0 2006.257.11:23:05.77#ibcon#end of sib2, iclass 32, count 0 2006.257.11:23:05.77#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:23:05.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:23:05.77#ibcon#[25=USB\r\n] 2006.257.11:23:05.77#ibcon#*before write, iclass 32, count 0 2006.257.11:23:05.77#ibcon#enter sib2, iclass 32, count 0 2006.257.11:23:05.77#ibcon#flushed, iclass 32, count 0 2006.257.11:23:05.77#ibcon#about to write, iclass 32, count 0 2006.257.11:23:05.77#ibcon#wrote, iclass 32, count 0 2006.257.11:23:05.77#ibcon#about to read 3, iclass 32, count 0 2006.257.11:23:05.80#ibcon#read 3, iclass 32, count 0 2006.257.11:23:05.80#ibcon#about to read 4, iclass 32, count 0 2006.257.11:23:05.80#ibcon#read 4, iclass 32, count 0 2006.257.11:23:05.80#ibcon#about to read 5, iclass 32, count 0 2006.257.11:23:05.80#ibcon#read 5, iclass 32, count 0 2006.257.11:23:05.80#ibcon#about to read 6, iclass 32, count 0 2006.257.11:23:05.80#ibcon#read 6, iclass 32, count 0 2006.257.11:23:05.80#ibcon#end of sib2, iclass 32, count 0 2006.257.11:23:05.80#ibcon#*after write, iclass 32, count 0 2006.257.11:23:05.80#ibcon#*before return 0, iclass 32, count 0 2006.257.11:23:05.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:05.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:05.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:23:05.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:23:05.80$vck44/valo=6,814.99 2006.257.11:23:05.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.11:23:05.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.11:23:05.80#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:05.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:05.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:05.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:05.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:23:05.80#ibcon#first serial, iclass 34, count 0 2006.257.11:23:05.80#ibcon#enter sib2, iclass 34, count 0 2006.257.11:23:05.80#ibcon#flushed, iclass 34, count 0 2006.257.11:23:05.80#ibcon#about to write, iclass 34, count 0 2006.257.11:23:05.80#ibcon#wrote, iclass 34, count 0 2006.257.11:23:05.80#ibcon#about to read 3, iclass 34, count 0 2006.257.11:23:05.82#ibcon#read 3, iclass 34, count 0 2006.257.11:23:05.82#ibcon#about to read 4, iclass 34, count 0 2006.257.11:23:05.82#ibcon#read 4, iclass 34, count 0 2006.257.11:23:05.82#ibcon#about to read 5, iclass 34, count 0 2006.257.11:23:05.82#ibcon#read 5, iclass 34, count 0 2006.257.11:23:05.82#ibcon#about to read 6, iclass 34, count 0 2006.257.11:23:05.82#ibcon#read 6, iclass 34, count 0 2006.257.11:23:05.82#ibcon#end of sib2, iclass 34, count 0 2006.257.11:23:05.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:23:05.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:23:05.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:23:05.82#ibcon#*before write, iclass 34, count 0 2006.257.11:23:05.82#ibcon#enter sib2, iclass 34, count 0 2006.257.11:23:05.82#ibcon#flushed, iclass 34, count 0 2006.257.11:23:05.82#ibcon#about to write, iclass 34, count 0 2006.257.11:23:05.82#ibcon#wrote, iclass 34, count 0 2006.257.11:23:05.82#ibcon#about to read 3, iclass 34, count 0 2006.257.11:23:05.86#ibcon#read 3, iclass 34, count 0 2006.257.11:23:05.86#ibcon#about to read 4, iclass 34, count 0 2006.257.11:23:05.86#ibcon#read 4, iclass 34, count 0 2006.257.11:23:05.86#ibcon#about to read 5, iclass 34, count 0 2006.257.11:23:05.86#ibcon#read 5, iclass 34, count 0 2006.257.11:23:05.86#ibcon#about to read 6, iclass 34, count 0 2006.257.11:23:05.86#ibcon#read 6, iclass 34, count 0 2006.257.11:23:05.86#ibcon#end of sib2, iclass 34, count 0 2006.257.11:23:05.86#ibcon#*after write, iclass 34, count 0 2006.257.11:23:05.86#ibcon#*before return 0, iclass 34, count 0 2006.257.11:23:05.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:05.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:05.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:23:05.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:23:05.86$vck44/va=6,4 2006.257.11:23:05.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.11:23:05.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.11:23:05.86#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:05.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:23:05.89#abcon#<5=/14 1.2 2.6 18.28 971013.8\r\n> 2006.257.11:23:05.91#abcon#{5=INTERFACE CLEAR} 2006.257.11:23:05.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:23:05.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:23:05.92#ibcon#enter wrdev, iclass 37, count 2 2006.257.11:23:05.92#ibcon#first serial, iclass 37, count 2 2006.257.11:23:05.92#ibcon#enter sib2, iclass 37, count 2 2006.257.11:23:05.92#ibcon#flushed, iclass 37, count 2 2006.257.11:23:05.92#ibcon#about to write, iclass 37, count 2 2006.257.11:23:05.92#ibcon#wrote, iclass 37, count 2 2006.257.11:23:05.92#ibcon#about to read 3, iclass 37, count 2 2006.257.11:23:05.94#ibcon#read 3, iclass 37, count 2 2006.257.11:23:05.94#ibcon#about to read 4, iclass 37, count 2 2006.257.11:23:05.94#ibcon#read 4, iclass 37, count 2 2006.257.11:23:05.94#ibcon#about to read 5, iclass 37, count 2 2006.257.11:23:05.94#ibcon#read 5, iclass 37, count 2 2006.257.11:23:05.94#ibcon#about to read 6, iclass 37, count 2 2006.257.11:23:05.94#ibcon#read 6, iclass 37, count 2 2006.257.11:23:05.94#ibcon#end of sib2, iclass 37, count 2 2006.257.11:23:05.94#ibcon#*mode == 0, iclass 37, count 2 2006.257.11:23:05.94#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.11:23:05.94#ibcon#[25=AT06-04\r\n] 2006.257.11:23:05.94#ibcon#*before write, iclass 37, count 2 2006.257.11:23:05.94#ibcon#enter sib2, iclass 37, count 2 2006.257.11:23:05.94#ibcon#flushed, iclass 37, count 2 2006.257.11:23:05.94#ibcon#about to write, iclass 37, count 2 2006.257.11:23:05.94#ibcon#wrote, iclass 37, count 2 2006.257.11:23:05.94#ibcon#about to read 3, iclass 37, count 2 2006.257.11:23:05.97#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:23:05.97#ibcon#read 3, iclass 37, count 2 2006.257.11:23:05.97#ibcon#about to read 4, iclass 37, count 2 2006.257.11:23:05.97#ibcon#read 4, iclass 37, count 2 2006.257.11:23:05.97#ibcon#about to read 5, iclass 37, count 2 2006.257.11:23:05.97#ibcon#read 5, iclass 37, count 2 2006.257.11:23:05.97#ibcon#about to read 6, iclass 37, count 2 2006.257.11:23:05.97#ibcon#read 6, iclass 37, count 2 2006.257.11:23:05.97#ibcon#end of sib2, iclass 37, count 2 2006.257.11:23:05.97#ibcon#*after write, iclass 37, count 2 2006.257.11:23:05.97#ibcon#*before return 0, iclass 37, count 2 2006.257.11:23:05.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:23:05.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:23:05.97#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.11:23:05.97#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:05.97#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:23:06.09#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:23:06.09#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:23:06.09#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:23:06.09#ibcon#first serial, iclass 37, count 0 2006.257.11:23:06.09#ibcon#enter sib2, iclass 37, count 0 2006.257.11:23:06.09#ibcon#flushed, iclass 37, count 0 2006.257.11:23:06.09#ibcon#about to write, iclass 37, count 0 2006.257.11:23:06.09#ibcon#wrote, iclass 37, count 0 2006.257.11:23:06.09#ibcon#about to read 3, iclass 37, count 0 2006.257.11:23:06.11#ibcon#read 3, iclass 37, count 0 2006.257.11:23:06.11#ibcon#about to read 4, iclass 37, count 0 2006.257.11:23:06.11#ibcon#read 4, iclass 37, count 0 2006.257.11:23:06.11#ibcon#about to read 5, iclass 37, count 0 2006.257.11:23:06.11#ibcon#read 5, iclass 37, count 0 2006.257.11:23:06.11#ibcon#about to read 6, iclass 37, count 0 2006.257.11:23:06.11#ibcon#read 6, iclass 37, count 0 2006.257.11:23:06.11#ibcon#end of sib2, iclass 37, count 0 2006.257.11:23:06.11#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:23:06.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:23:06.11#ibcon#[25=USB\r\n] 2006.257.11:23:06.11#ibcon#*before write, iclass 37, count 0 2006.257.11:23:06.11#ibcon#enter sib2, iclass 37, count 0 2006.257.11:23:06.11#ibcon#flushed, iclass 37, count 0 2006.257.11:23:06.11#ibcon#about to write, iclass 37, count 0 2006.257.11:23:06.11#ibcon#wrote, iclass 37, count 0 2006.257.11:23:06.11#ibcon#about to read 3, iclass 37, count 0 2006.257.11:23:06.14#ibcon#read 3, iclass 37, count 0 2006.257.11:23:06.14#ibcon#about to read 4, iclass 37, count 0 2006.257.11:23:06.14#ibcon#read 4, iclass 37, count 0 2006.257.11:23:06.14#ibcon#about to read 5, iclass 37, count 0 2006.257.11:23:06.14#ibcon#read 5, iclass 37, count 0 2006.257.11:23:06.14#ibcon#about to read 6, iclass 37, count 0 2006.257.11:23:06.14#ibcon#read 6, iclass 37, count 0 2006.257.11:23:06.14#ibcon#end of sib2, iclass 37, count 0 2006.257.11:23:06.14#ibcon#*after write, iclass 37, count 0 2006.257.11:23:06.14#ibcon#*before return 0, iclass 37, count 0 2006.257.11:23:06.14#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:23:06.14#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:23:06.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:23:06.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:23:06.14$vck44/valo=7,864.99 2006.257.11:23:06.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.11:23:06.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.11:23:06.14#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:06.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:06.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:06.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:06.14#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:23:06.14#ibcon#first serial, iclass 4, count 0 2006.257.11:23:06.14#ibcon#enter sib2, iclass 4, count 0 2006.257.11:23:06.14#ibcon#flushed, iclass 4, count 0 2006.257.11:23:06.14#ibcon#about to write, iclass 4, count 0 2006.257.11:23:06.14#ibcon#wrote, iclass 4, count 0 2006.257.11:23:06.14#ibcon#about to read 3, iclass 4, count 0 2006.257.11:23:06.16#ibcon#read 3, iclass 4, count 0 2006.257.11:23:06.16#ibcon#about to read 4, iclass 4, count 0 2006.257.11:23:06.16#ibcon#read 4, iclass 4, count 0 2006.257.11:23:06.16#ibcon#about to read 5, iclass 4, count 0 2006.257.11:23:06.16#ibcon#read 5, iclass 4, count 0 2006.257.11:23:06.16#ibcon#about to read 6, iclass 4, count 0 2006.257.11:23:06.16#ibcon#read 6, iclass 4, count 0 2006.257.11:23:06.16#ibcon#end of sib2, iclass 4, count 0 2006.257.11:23:06.16#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:23:06.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:23:06.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:23:06.16#ibcon#*before write, iclass 4, count 0 2006.257.11:23:06.16#ibcon#enter sib2, iclass 4, count 0 2006.257.11:23:06.16#ibcon#flushed, iclass 4, count 0 2006.257.11:23:06.16#ibcon#about to write, iclass 4, count 0 2006.257.11:23:06.16#ibcon#wrote, iclass 4, count 0 2006.257.11:23:06.16#ibcon#about to read 3, iclass 4, count 0 2006.257.11:23:06.20#ibcon#read 3, iclass 4, count 0 2006.257.11:23:06.20#ibcon#about to read 4, iclass 4, count 0 2006.257.11:23:06.20#ibcon#read 4, iclass 4, count 0 2006.257.11:23:06.20#ibcon#about to read 5, iclass 4, count 0 2006.257.11:23:06.20#ibcon#read 5, iclass 4, count 0 2006.257.11:23:06.20#ibcon#about to read 6, iclass 4, count 0 2006.257.11:23:06.20#ibcon#read 6, iclass 4, count 0 2006.257.11:23:06.20#ibcon#end of sib2, iclass 4, count 0 2006.257.11:23:06.20#ibcon#*after write, iclass 4, count 0 2006.257.11:23:06.20#ibcon#*before return 0, iclass 4, count 0 2006.257.11:23:06.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:06.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:06.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:23:06.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:23:06.20$vck44/va=7,4 2006.257.11:23:06.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.11:23:06.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.11:23:06.20#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:06.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:06.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:06.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:06.26#ibcon#enter wrdev, iclass 6, count 2 2006.257.11:23:06.26#ibcon#first serial, iclass 6, count 2 2006.257.11:23:06.26#ibcon#enter sib2, iclass 6, count 2 2006.257.11:23:06.26#ibcon#flushed, iclass 6, count 2 2006.257.11:23:06.26#ibcon#about to write, iclass 6, count 2 2006.257.11:23:06.26#ibcon#wrote, iclass 6, count 2 2006.257.11:23:06.26#ibcon#about to read 3, iclass 6, count 2 2006.257.11:23:06.28#ibcon#read 3, iclass 6, count 2 2006.257.11:23:06.28#ibcon#about to read 4, iclass 6, count 2 2006.257.11:23:06.28#ibcon#read 4, iclass 6, count 2 2006.257.11:23:06.28#ibcon#about to read 5, iclass 6, count 2 2006.257.11:23:06.28#ibcon#read 5, iclass 6, count 2 2006.257.11:23:06.28#ibcon#about to read 6, iclass 6, count 2 2006.257.11:23:06.28#ibcon#read 6, iclass 6, count 2 2006.257.11:23:06.28#ibcon#end of sib2, iclass 6, count 2 2006.257.11:23:06.28#ibcon#*mode == 0, iclass 6, count 2 2006.257.11:23:06.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.11:23:06.28#ibcon#[25=AT07-04\r\n] 2006.257.11:23:06.28#ibcon#*before write, iclass 6, count 2 2006.257.11:23:06.28#ibcon#enter sib2, iclass 6, count 2 2006.257.11:23:06.28#ibcon#flushed, iclass 6, count 2 2006.257.11:23:06.28#ibcon#about to write, iclass 6, count 2 2006.257.11:23:06.28#ibcon#wrote, iclass 6, count 2 2006.257.11:23:06.28#ibcon#about to read 3, iclass 6, count 2 2006.257.11:23:06.31#ibcon#read 3, iclass 6, count 2 2006.257.11:23:06.31#ibcon#about to read 4, iclass 6, count 2 2006.257.11:23:06.31#ibcon#read 4, iclass 6, count 2 2006.257.11:23:06.31#ibcon#about to read 5, iclass 6, count 2 2006.257.11:23:06.31#ibcon#read 5, iclass 6, count 2 2006.257.11:23:06.31#ibcon#about to read 6, iclass 6, count 2 2006.257.11:23:06.31#ibcon#read 6, iclass 6, count 2 2006.257.11:23:06.31#ibcon#end of sib2, iclass 6, count 2 2006.257.11:23:06.31#ibcon#*after write, iclass 6, count 2 2006.257.11:23:06.31#ibcon#*before return 0, iclass 6, count 2 2006.257.11:23:06.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:06.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:06.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.11:23:06.31#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:06.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:06.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:06.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:06.43#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:23:06.43#ibcon#first serial, iclass 6, count 0 2006.257.11:23:06.43#ibcon#enter sib2, iclass 6, count 0 2006.257.11:23:06.43#ibcon#flushed, iclass 6, count 0 2006.257.11:23:06.43#ibcon#about to write, iclass 6, count 0 2006.257.11:23:06.43#ibcon#wrote, iclass 6, count 0 2006.257.11:23:06.43#ibcon#about to read 3, iclass 6, count 0 2006.257.11:23:06.45#ibcon#read 3, iclass 6, count 0 2006.257.11:23:06.45#ibcon#about to read 4, iclass 6, count 0 2006.257.11:23:06.45#ibcon#read 4, iclass 6, count 0 2006.257.11:23:06.45#ibcon#about to read 5, iclass 6, count 0 2006.257.11:23:06.45#ibcon#read 5, iclass 6, count 0 2006.257.11:23:06.45#ibcon#about to read 6, iclass 6, count 0 2006.257.11:23:06.45#ibcon#read 6, iclass 6, count 0 2006.257.11:23:06.45#ibcon#end of sib2, iclass 6, count 0 2006.257.11:23:06.45#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:23:06.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:23:06.45#ibcon#[25=USB\r\n] 2006.257.11:23:06.45#ibcon#*before write, iclass 6, count 0 2006.257.11:23:06.45#ibcon#enter sib2, iclass 6, count 0 2006.257.11:23:06.45#ibcon#flushed, iclass 6, count 0 2006.257.11:23:06.45#ibcon#about to write, iclass 6, count 0 2006.257.11:23:06.45#ibcon#wrote, iclass 6, count 0 2006.257.11:23:06.45#ibcon#about to read 3, iclass 6, count 0 2006.257.11:23:06.48#ibcon#read 3, iclass 6, count 0 2006.257.11:23:06.48#ibcon#about to read 4, iclass 6, count 0 2006.257.11:23:06.48#ibcon#read 4, iclass 6, count 0 2006.257.11:23:06.48#ibcon#about to read 5, iclass 6, count 0 2006.257.11:23:06.48#ibcon#read 5, iclass 6, count 0 2006.257.11:23:06.48#ibcon#about to read 6, iclass 6, count 0 2006.257.11:23:06.48#ibcon#read 6, iclass 6, count 0 2006.257.11:23:06.48#ibcon#end of sib2, iclass 6, count 0 2006.257.11:23:06.48#ibcon#*after write, iclass 6, count 0 2006.257.11:23:06.48#ibcon#*before return 0, iclass 6, count 0 2006.257.11:23:06.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:06.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:06.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:23:06.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:23:06.48$vck44/valo=8,884.99 2006.257.11:23:06.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.11:23:06.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.11:23:06.48#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:06.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:06.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:06.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:06.48#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:23:06.48#ibcon#first serial, iclass 10, count 0 2006.257.11:23:06.48#ibcon#enter sib2, iclass 10, count 0 2006.257.11:23:06.48#ibcon#flushed, iclass 10, count 0 2006.257.11:23:06.48#ibcon#about to write, iclass 10, count 0 2006.257.11:23:06.48#ibcon#wrote, iclass 10, count 0 2006.257.11:23:06.48#ibcon#about to read 3, iclass 10, count 0 2006.257.11:23:06.50#ibcon#read 3, iclass 10, count 0 2006.257.11:23:06.50#ibcon#about to read 4, iclass 10, count 0 2006.257.11:23:06.50#ibcon#read 4, iclass 10, count 0 2006.257.11:23:06.50#ibcon#about to read 5, iclass 10, count 0 2006.257.11:23:06.50#ibcon#read 5, iclass 10, count 0 2006.257.11:23:06.50#ibcon#about to read 6, iclass 10, count 0 2006.257.11:23:06.50#ibcon#read 6, iclass 10, count 0 2006.257.11:23:06.50#ibcon#end of sib2, iclass 10, count 0 2006.257.11:23:06.50#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:23:06.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:23:06.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:23:06.50#ibcon#*before write, iclass 10, count 0 2006.257.11:23:06.50#ibcon#enter sib2, iclass 10, count 0 2006.257.11:23:06.50#ibcon#flushed, iclass 10, count 0 2006.257.11:23:06.50#ibcon#about to write, iclass 10, count 0 2006.257.11:23:06.50#ibcon#wrote, iclass 10, count 0 2006.257.11:23:06.50#ibcon#about to read 3, iclass 10, count 0 2006.257.11:23:06.54#ibcon#read 3, iclass 10, count 0 2006.257.11:23:06.54#ibcon#about to read 4, iclass 10, count 0 2006.257.11:23:06.54#ibcon#read 4, iclass 10, count 0 2006.257.11:23:06.54#ibcon#about to read 5, iclass 10, count 0 2006.257.11:23:06.54#ibcon#read 5, iclass 10, count 0 2006.257.11:23:06.54#ibcon#about to read 6, iclass 10, count 0 2006.257.11:23:06.54#ibcon#read 6, iclass 10, count 0 2006.257.11:23:06.54#ibcon#end of sib2, iclass 10, count 0 2006.257.11:23:06.54#ibcon#*after write, iclass 10, count 0 2006.257.11:23:06.54#ibcon#*before return 0, iclass 10, count 0 2006.257.11:23:06.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:06.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:06.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:23:06.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:23:06.54$vck44/va=8,4 2006.257.11:23:06.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.11:23:06.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.11:23:06.54#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:06.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:23:06.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:23:06.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:23:06.60#ibcon#enter wrdev, iclass 12, count 2 2006.257.11:23:06.60#ibcon#first serial, iclass 12, count 2 2006.257.11:23:06.60#ibcon#enter sib2, iclass 12, count 2 2006.257.11:23:06.60#ibcon#flushed, iclass 12, count 2 2006.257.11:23:06.60#ibcon#about to write, iclass 12, count 2 2006.257.11:23:06.60#ibcon#wrote, iclass 12, count 2 2006.257.11:23:06.60#ibcon#about to read 3, iclass 12, count 2 2006.257.11:23:06.62#ibcon#read 3, iclass 12, count 2 2006.257.11:23:06.62#ibcon#about to read 4, iclass 12, count 2 2006.257.11:23:06.62#ibcon#read 4, iclass 12, count 2 2006.257.11:23:06.62#ibcon#about to read 5, iclass 12, count 2 2006.257.11:23:06.62#ibcon#read 5, iclass 12, count 2 2006.257.11:23:06.62#ibcon#about to read 6, iclass 12, count 2 2006.257.11:23:06.62#ibcon#read 6, iclass 12, count 2 2006.257.11:23:06.62#ibcon#end of sib2, iclass 12, count 2 2006.257.11:23:06.62#ibcon#*mode == 0, iclass 12, count 2 2006.257.11:23:06.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.11:23:06.62#ibcon#[25=AT08-04\r\n] 2006.257.11:23:06.62#ibcon#*before write, iclass 12, count 2 2006.257.11:23:06.62#ibcon#enter sib2, iclass 12, count 2 2006.257.11:23:06.62#ibcon#flushed, iclass 12, count 2 2006.257.11:23:06.62#ibcon#about to write, iclass 12, count 2 2006.257.11:23:06.62#ibcon#wrote, iclass 12, count 2 2006.257.11:23:06.62#ibcon#about to read 3, iclass 12, count 2 2006.257.11:23:06.65#ibcon#read 3, iclass 12, count 2 2006.257.11:23:06.65#ibcon#about to read 4, iclass 12, count 2 2006.257.11:23:06.65#ibcon#read 4, iclass 12, count 2 2006.257.11:23:06.65#ibcon#about to read 5, iclass 12, count 2 2006.257.11:23:06.65#ibcon#read 5, iclass 12, count 2 2006.257.11:23:06.65#ibcon#about to read 6, iclass 12, count 2 2006.257.11:23:06.65#ibcon#read 6, iclass 12, count 2 2006.257.11:23:06.65#ibcon#end of sib2, iclass 12, count 2 2006.257.11:23:06.65#ibcon#*after write, iclass 12, count 2 2006.257.11:23:06.65#ibcon#*before return 0, iclass 12, count 2 2006.257.11:23:06.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:23:06.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:23:06.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.11:23:06.65#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:06.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:23:06.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:23:06.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:23:06.77#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:23:06.77#ibcon#first serial, iclass 12, count 0 2006.257.11:23:06.77#ibcon#enter sib2, iclass 12, count 0 2006.257.11:23:06.77#ibcon#flushed, iclass 12, count 0 2006.257.11:23:06.77#ibcon#about to write, iclass 12, count 0 2006.257.11:23:06.77#ibcon#wrote, iclass 12, count 0 2006.257.11:23:06.77#ibcon#about to read 3, iclass 12, count 0 2006.257.11:23:06.79#ibcon#read 3, iclass 12, count 0 2006.257.11:23:06.79#ibcon#about to read 4, iclass 12, count 0 2006.257.11:23:06.79#ibcon#read 4, iclass 12, count 0 2006.257.11:23:06.79#ibcon#about to read 5, iclass 12, count 0 2006.257.11:23:06.79#ibcon#read 5, iclass 12, count 0 2006.257.11:23:06.79#ibcon#about to read 6, iclass 12, count 0 2006.257.11:23:06.79#ibcon#read 6, iclass 12, count 0 2006.257.11:23:06.79#ibcon#end of sib2, iclass 12, count 0 2006.257.11:23:06.79#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:23:06.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:23:06.79#ibcon#[25=USB\r\n] 2006.257.11:23:06.79#ibcon#*before write, iclass 12, count 0 2006.257.11:23:06.79#ibcon#enter sib2, iclass 12, count 0 2006.257.11:23:06.79#ibcon#flushed, iclass 12, count 0 2006.257.11:23:06.79#ibcon#about to write, iclass 12, count 0 2006.257.11:23:06.79#ibcon#wrote, iclass 12, count 0 2006.257.11:23:06.79#ibcon#about to read 3, iclass 12, count 0 2006.257.11:23:06.82#ibcon#read 3, iclass 12, count 0 2006.257.11:23:06.82#ibcon#about to read 4, iclass 12, count 0 2006.257.11:23:06.82#ibcon#read 4, iclass 12, count 0 2006.257.11:23:06.82#ibcon#about to read 5, iclass 12, count 0 2006.257.11:23:06.82#ibcon#read 5, iclass 12, count 0 2006.257.11:23:06.82#ibcon#about to read 6, iclass 12, count 0 2006.257.11:23:06.82#ibcon#read 6, iclass 12, count 0 2006.257.11:23:06.82#ibcon#end of sib2, iclass 12, count 0 2006.257.11:23:06.82#ibcon#*after write, iclass 12, count 0 2006.257.11:23:06.82#ibcon#*before return 0, iclass 12, count 0 2006.257.11:23:06.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:23:06.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:23:06.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:23:06.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:23:06.82$vck44/vblo=1,629.99 2006.257.11:23:06.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.11:23:06.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.11:23:06.82#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:06.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:06.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:06.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:06.82#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:23:06.82#ibcon#first serial, iclass 14, count 0 2006.257.11:23:06.82#ibcon#enter sib2, iclass 14, count 0 2006.257.11:23:06.82#ibcon#flushed, iclass 14, count 0 2006.257.11:23:06.82#ibcon#about to write, iclass 14, count 0 2006.257.11:23:06.82#ibcon#wrote, iclass 14, count 0 2006.257.11:23:06.82#ibcon#about to read 3, iclass 14, count 0 2006.257.11:23:06.84#ibcon#read 3, iclass 14, count 0 2006.257.11:23:06.84#ibcon#about to read 4, iclass 14, count 0 2006.257.11:23:06.84#ibcon#read 4, iclass 14, count 0 2006.257.11:23:06.84#ibcon#about to read 5, iclass 14, count 0 2006.257.11:23:06.84#ibcon#read 5, iclass 14, count 0 2006.257.11:23:06.84#ibcon#about to read 6, iclass 14, count 0 2006.257.11:23:06.84#ibcon#read 6, iclass 14, count 0 2006.257.11:23:06.84#ibcon#end of sib2, iclass 14, count 0 2006.257.11:23:06.84#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:23:06.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:23:06.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:23:06.84#ibcon#*before write, iclass 14, count 0 2006.257.11:23:06.84#ibcon#enter sib2, iclass 14, count 0 2006.257.11:23:06.84#ibcon#flushed, iclass 14, count 0 2006.257.11:23:06.84#ibcon#about to write, iclass 14, count 0 2006.257.11:23:06.84#ibcon#wrote, iclass 14, count 0 2006.257.11:23:06.84#ibcon#about to read 3, iclass 14, count 0 2006.257.11:23:06.88#ibcon#read 3, iclass 14, count 0 2006.257.11:23:06.88#ibcon#about to read 4, iclass 14, count 0 2006.257.11:23:06.88#ibcon#read 4, iclass 14, count 0 2006.257.11:23:06.88#ibcon#about to read 5, iclass 14, count 0 2006.257.11:23:06.88#ibcon#read 5, iclass 14, count 0 2006.257.11:23:06.88#ibcon#about to read 6, iclass 14, count 0 2006.257.11:23:06.88#ibcon#read 6, iclass 14, count 0 2006.257.11:23:06.88#ibcon#end of sib2, iclass 14, count 0 2006.257.11:23:06.88#ibcon#*after write, iclass 14, count 0 2006.257.11:23:06.88#ibcon#*before return 0, iclass 14, count 0 2006.257.11:23:06.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:06.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:23:06.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:23:06.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:23:06.88$vck44/vb=1,4 2006.257.11:23:06.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.11:23:06.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.11:23:06.88#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:06.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:06.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:06.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:06.88#ibcon#enter wrdev, iclass 16, count 2 2006.257.11:23:06.88#ibcon#first serial, iclass 16, count 2 2006.257.11:23:06.88#ibcon#enter sib2, iclass 16, count 2 2006.257.11:23:06.88#ibcon#flushed, iclass 16, count 2 2006.257.11:23:06.88#ibcon#about to write, iclass 16, count 2 2006.257.11:23:06.88#ibcon#wrote, iclass 16, count 2 2006.257.11:23:06.88#ibcon#about to read 3, iclass 16, count 2 2006.257.11:23:06.90#ibcon#read 3, iclass 16, count 2 2006.257.11:23:06.90#ibcon#about to read 4, iclass 16, count 2 2006.257.11:23:06.90#ibcon#read 4, iclass 16, count 2 2006.257.11:23:06.90#ibcon#about to read 5, iclass 16, count 2 2006.257.11:23:06.90#ibcon#read 5, iclass 16, count 2 2006.257.11:23:06.90#ibcon#about to read 6, iclass 16, count 2 2006.257.11:23:06.90#ibcon#read 6, iclass 16, count 2 2006.257.11:23:06.90#ibcon#end of sib2, iclass 16, count 2 2006.257.11:23:06.90#ibcon#*mode == 0, iclass 16, count 2 2006.257.11:23:06.90#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.11:23:06.90#ibcon#[27=AT01-04\r\n] 2006.257.11:23:06.90#ibcon#*before write, iclass 16, count 2 2006.257.11:23:06.90#ibcon#enter sib2, iclass 16, count 2 2006.257.11:23:06.90#ibcon#flushed, iclass 16, count 2 2006.257.11:23:06.90#ibcon#about to write, iclass 16, count 2 2006.257.11:23:06.90#ibcon#wrote, iclass 16, count 2 2006.257.11:23:06.90#ibcon#about to read 3, iclass 16, count 2 2006.257.11:23:06.93#ibcon#read 3, iclass 16, count 2 2006.257.11:23:06.93#ibcon#about to read 4, iclass 16, count 2 2006.257.11:23:06.93#ibcon#read 4, iclass 16, count 2 2006.257.11:23:06.93#ibcon#about to read 5, iclass 16, count 2 2006.257.11:23:06.93#ibcon#read 5, iclass 16, count 2 2006.257.11:23:06.93#ibcon#about to read 6, iclass 16, count 2 2006.257.11:23:06.93#ibcon#read 6, iclass 16, count 2 2006.257.11:23:06.93#ibcon#end of sib2, iclass 16, count 2 2006.257.11:23:06.93#ibcon#*after write, iclass 16, count 2 2006.257.11:23:06.93#ibcon#*before return 0, iclass 16, count 2 2006.257.11:23:06.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:06.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:23:06.93#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.11:23:06.93#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:06.93#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:07.05#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:07.05#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:07.05#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:23:07.05#ibcon#first serial, iclass 16, count 0 2006.257.11:23:07.05#ibcon#enter sib2, iclass 16, count 0 2006.257.11:23:07.05#ibcon#flushed, iclass 16, count 0 2006.257.11:23:07.05#ibcon#about to write, iclass 16, count 0 2006.257.11:23:07.05#ibcon#wrote, iclass 16, count 0 2006.257.11:23:07.05#ibcon#about to read 3, iclass 16, count 0 2006.257.11:23:07.07#ibcon#read 3, iclass 16, count 0 2006.257.11:23:07.07#ibcon#about to read 4, iclass 16, count 0 2006.257.11:23:07.07#ibcon#read 4, iclass 16, count 0 2006.257.11:23:07.07#ibcon#about to read 5, iclass 16, count 0 2006.257.11:23:07.07#ibcon#read 5, iclass 16, count 0 2006.257.11:23:07.07#ibcon#about to read 6, iclass 16, count 0 2006.257.11:23:07.07#ibcon#read 6, iclass 16, count 0 2006.257.11:23:07.07#ibcon#end of sib2, iclass 16, count 0 2006.257.11:23:07.07#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:23:07.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:23:07.07#ibcon#[27=USB\r\n] 2006.257.11:23:07.07#ibcon#*before write, iclass 16, count 0 2006.257.11:23:07.07#ibcon#enter sib2, iclass 16, count 0 2006.257.11:23:07.07#ibcon#flushed, iclass 16, count 0 2006.257.11:23:07.07#ibcon#about to write, iclass 16, count 0 2006.257.11:23:07.07#ibcon#wrote, iclass 16, count 0 2006.257.11:23:07.07#ibcon#about to read 3, iclass 16, count 0 2006.257.11:23:07.10#ibcon#read 3, iclass 16, count 0 2006.257.11:23:07.10#ibcon#about to read 4, iclass 16, count 0 2006.257.11:23:07.10#ibcon#read 4, iclass 16, count 0 2006.257.11:23:07.10#ibcon#about to read 5, iclass 16, count 0 2006.257.11:23:07.10#ibcon#read 5, iclass 16, count 0 2006.257.11:23:07.10#ibcon#about to read 6, iclass 16, count 0 2006.257.11:23:07.10#ibcon#read 6, iclass 16, count 0 2006.257.11:23:07.10#ibcon#end of sib2, iclass 16, count 0 2006.257.11:23:07.10#ibcon#*after write, iclass 16, count 0 2006.257.11:23:07.10#ibcon#*before return 0, iclass 16, count 0 2006.257.11:23:07.10#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:07.10#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:23:07.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:23:07.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:23:07.10$vck44/vblo=2,634.99 2006.257.11:23:07.10#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.11:23:07.10#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.11:23:07.10#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:07.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:07.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:07.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:07.10#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:23:07.10#ibcon#first serial, iclass 18, count 0 2006.257.11:23:07.10#ibcon#enter sib2, iclass 18, count 0 2006.257.11:23:07.10#ibcon#flushed, iclass 18, count 0 2006.257.11:23:07.10#ibcon#about to write, iclass 18, count 0 2006.257.11:23:07.10#ibcon#wrote, iclass 18, count 0 2006.257.11:23:07.10#ibcon#about to read 3, iclass 18, count 0 2006.257.11:23:07.12#ibcon#read 3, iclass 18, count 0 2006.257.11:23:07.12#ibcon#about to read 4, iclass 18, count 0 2006.257.11:23:07.12#ibcon#read 4, iclass 18, count 0 2006.257.11:23:07.12#ibcon#about to read 5, iclass 18, count 0 2006.257.11:23:07.12#ibcon#read 5, iclass 18, count 0 2006.257.11:23:07.12#ibcon#about to read 6, iclass 18, count 0 2006.257.11:23:07.12#ibcon#read 6, iclass 18, count 0 2006.257.11:23:07.12#ibcon#end of sib2, iclass 18, count 0 2006.257.11:23:07.12#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:23:07.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:23:07.12#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:23:07.12#ibcon#*before write, iclass 18, count 0 2006.257.11:23:07.12#ibcon#enter sib2, iclass 18, count 0 2006.257.11:23:07.12#ibcon#flushed, iclass 18, count 0 2006.257.11:23:07.12#ibcon#about to write, iclass 18, count 0 2006.257.11:23:07.12#ibcon#wrote, iclass 18, count 0 2006.257.11:23:07.12#ibcon#about to read 3, iclass 18, count 0 2006.257.11:23:07.16#ibcon#read 3, iclass 18, count 0 2006.257.11:23:07.16#ibcon#about to read 4, iclass 18, count 0 2006.257.11:23:07.16#ibcon#read 4, iclass 18, count 0 2006.257.11:23:07.16#ibcon#about to read 5, iclass 18, count 0 2006.257.11:23:07.16#ibcon#read 5, iclass 18, count 0 2006.257.11:23:07.16#ibcon#about to read 6, iclass 18, count 0 2006.257.11:23:07.16#ibcon#read 6, iclass 18, count 0 2006.257.11:23:07.16#ibcon#end of sib2, iclass 18, count 0 2006.257.11:23:07.16#ibcon#*after write, iclass 18, count 0 2006.257.11:23:07.16#ibcon#*before return 0, iclass 18, count 0 2006.257.11:23:07.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:07.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:23:07.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:23:07.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:23:07.16$vck44/vb=2,5 2006.257.11:23:07.16#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.11:23:07.16#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.11:23:07.16#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:07.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:07.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:07.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:07.22#ibcon#enter wrdev, iclass 20, count 2 2006.257.11:23:07.22#ibcon#first serial, iclass 20, count 2 2006.257.11:23:07.22#ibcon#enter sib2, iclass 20, count 2 2006.257.11:23:07.22#ibcon#flushed, iclass 20, count 2 2006.257.11:23:07.22#ibcon#about to write, iclass 20, count 2 2006.257.11:23:07.22#ibcon#wrote, iclass 20, count 2 2006.257.11:23:07.22#ibcon#about to read 3, iclass 20, count 2 2006.257.11:23:07.24#ibcon#read 3, iclass 20, count 2 2006.257.11:23:07.24#ibcon#about to read 4, iclass 20, count 2 2006.257.11:23:07.24#ibcon#read 4, iclass 20, count 2 2006.257.11:23:07.24#ibcon#about to read 5, iclass 20, count 2 2006.257.11:23:07.24#ibcon#read 5, iclass 20, count 2 2006.257.11:23:07.24#ibcon#about to read 6, iclass 20, count 2 2006.257.11:23:07.24#ibcon#read 6, iclass 20, count 2 2006.257.11:23:07.24#ibcon#end of sib2, iclass 20, count 2 2006.257.11:23:07.24#ibcon#*mode == 0, iclass 20, count 2 2006.257.11:23:07.24#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.11:23:07.24#ibcon#[27=AT02-05\r\n] 2006.257.11:23:07.24#ibcon#*before write, iclass 20, count 2 2006.257.11:23:07.24#ibcon#enter sib2, iclass 20, count 2 2006.257.11:23:07.24#ibcon#flushed, iclass 20, count 2 2006.257.11:23:07.24#ibcon#about to write, iclass 20, count 2 2006.257.11:23:07.24#ibcon#wrote, iclass 20, count 2 2006.257.11:23:07.24#ibcon#about to read 3, iclass 20, count 2 2006.257.11:23:07.27#ibcon#read 3, iclass 20, count 2 2006.257.11:23:07.27#ibcon#about to read 4, iclass 20, count 2 2006.257.11:23:07.27#ibcon#read 4, iclass 20, count 2 2006.257.11:23:07.27#ibcon#about to read 5, iclass 20, count 2 2006.257.11:23:07.27#ibcon#read 5, iclass 20, count 2 2006.257.11:23:07.27#ibcon#about to read 6, iclass 20, count 2 2006.257.11:23:07.27#ibcon#read 6, iclass 20, count 2 2006.257.11:23:07.27#ibcon#end of sib2, iclass 20, count 2 2006.257.11:23:07.27#ibcon#*after write, iclass 20, count 2 2006.257.11:23:07.27#ibcon#*before return 0, iclass 20, count 2 2006.257.11:23:07.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:07.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:23:07.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.11:23:07.27#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:07.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:07.39#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:07.39#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:07.39#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:23:07.39#ibcon#first serial, iclass 20, count 0 2006.257.11:23:07.39#ibcon#enter sib2, iclass 20, count 0 2006.257.11:23:07.39#ibcon#flushed, iclass 20, count 0 2006.257.11:23:07.39#ibcon#about to write, iclass 20, count 0 2006.257.11:23:07.39#ibcon#wrote, iclass 20, count 0 2006.257.11:23:07.39#ibcon#about to read 3, iclass 20, count 0 2006.257.11:23:07.41#ibcon#read 3, iclass 20, count 0 2006.257.11:23:07.41#ibcon#about to read 4, iclass 20, count 0 2006.257.11:23:07.41#ibcon#read 4, iclass 20, count 0 2006.257.11:23:07.41#ibcon#about to read 5, iclass 20, count 0 2006.257.11:23:07.41#ibcon#read 5, iclass 20, count 0 2006.257.11:23:07.41#ibcon#about to read 6, iclass 20, count 0 2006.257.11:23:07.41#ibcon#read 6, iclass 20, count 0 2006.257.11:23:07.41#ibcon#end of sib2, iclass 20, count 0 2006.257.11:23:07.41#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:23:07.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:23:07.41#ibcon#[27=USB\r\n] 2006.257.11:23:07.41#ibcon#*before write, iclass 20, count 0 2006.257.11:23:07.41#ibcon#enter sib2, iclass 20, count 0 2006.257.11:23:07.41#ibcon#flushed, iclass 20, count 0 2006.257.11:23:07.41#ibcon#about to write, iclass 20, count 0 2006.257.11:23:07.41#ibcon#wrote, iclass 20, count 0 2006.257.11:23:07.41#ibcon#about to read 3, iclass 20, count 0 2006.257.11:23:07.44#ibcon#read 3, iclass 20, count 0 2006.257.11:23:07.44#ibcon#about to read 4, iclass 20, count 0 2006.257.11:23:07.44#ibcon#read 4, iclass 20, count 0 2006.257.11:23:07.44#ibcon#about to read 5, iclass 20, count 0 2006.257.11:23:07.44#ibcon#read 5, iclass 20, count 0 2006.257.11:23:07.44#ibcon#about to read 6, iclass 20, count 0 2006.257.11:23:07.44#ibcon#read 6, iclass 20, count 0 2006.257.11:23:07.44#ibcon#end of sib2, iclass 20, count 0 2006.257.11:23:07.44#ibcon#*after write, iclass 20, count 0 2006.257.11:23:07.44#ibcon#*before return 0, iclass 20, count 0 2006.257.11:23:07.44#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:07.44#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:23:07.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:23:07.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:23:07.44$vck44/vblo=3,649.99 2006.257.11:23:07.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.11:23:07.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.11:23:07.44#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:07.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:07.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:07.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:07.44#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:23:07.44#ibcon#first serial, iclass 22, count 0 2006.257.11:23:07.44#ibcon#enter sib2, iclass 22, count 0 2006.257.11:23:07.44#ibcon#flushed, iclass 22, count 0 2006.257.11:23:07.44#ibcon#about to write, iclass 22, count 0 2006.257.11:23:07.44#ibcon#wrote, iclass 22, count 0 2006.257.11:23:07.44#ibcon#about to read 3, iclass 22, count 0 2006.257.11:23:07.46#ibcon#read 3, iclass 22, count 0 2006.257.11:23:07.46#ibcon#about to read 4, iclass 22, count 0 2006.257.11:23:07.46#ibcon#read 4, iclass 22, count 0 2006.257.11:23:07.46#ibcon#about to read 5, iclass 22, count 0 2006.257.11:23:07.46#ibcon#read 5, iclass 22, count 0 2006.257.11:23:07.46#ibcon#about to read 6, iclass 22, count 0 2006.257.11:23:07.46#ibcon#read 6, iclass 22, count 0 2006.257.11:23:07.46#ibcon#end of sib2, iclass 22, count 0 2006.257.11:23:07.46#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:23:07.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:23:07.46#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:23:07.46#ibcon#*before write, iclass 22, count 0 2006.257.11:23:07.46#ibcon#enter sib2, iclass 22, count 0 2006.257.11:23:07.46#ibcon#flushed, iclass 22, count 0 2006.257.11:23:07.46#ibcon#about to write, iclass 22, count 0 2006.257.11:23:07.46#ibcon#wrote, iclass 22, count 0 2006.257.11:23:07.46#ibcon#about to read 3, iclass 22, count 0 2006.257.11:23:07.50#ibcon#read 3, iclass 22, count 0 2006.257.11:23:07.50#ibcon#about to read 4, iclass 22, count 0 2006.257.11:23:07.50#ibcon#read 4, iclass 22, count 0 2006.257.11:23:07.50#ibcon#about to read 5, iclass 22, count 0 2006.257.11:23:07.50#ibcon#read 5, iclass 22, count 0 2006.257.11:23:07.50#ibcon#about to read 6, iclass 22, count 0 2006.257.11:23:07.50#ibcon#read 6, iclass 22, count 0 2006.257.11:23:07.50#ibcon#end of sib2, iclass 22, count 0 2006.257.11:23:07.50#ibcon#*after write, iclass 22, count 0 2006.257.11:23:07.50#ibcon#*before return 0, iclass 22, count 0 2006.257.11:23:07.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:07.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:23:07.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:23:07.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:23:07.50$vck44/vb=3,4 2006.257.11:23:07.50#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.11:23:07.50#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.11:23:07.50#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:07.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:07.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:07.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:07.56#ibcon#enter wrdev, iclass 24, count 2 2006.257.11:23:07.56#ibcon#first serial, iclass 24, count 2 2006.257.11:23:07.56#ibcon#enter sib2, iclass 24, count 2 2006.257.11:23:07.56#ibcon#flushed, iclass 24, count 2 2006.257.11:23:07.56#ibcon#about to write, iclass 24, count 2 2006.257.11:23:07.56#ibcon#wrote, iclass 24, count 2 2006.257.11:23:07.56#ibcon#about to read 3, iclass 24, count 2 2006.257.11:23:07.58#ibcon#read 3, iclass 24, count 2 2006.257.11:23:07.58#ibcon#about to read 4, iclass 24, count 2 2006.257.11:23:07.58#ibcon#read 4, iclass 24, count 2 2006.257.11:23:07.58#ibcon#about to read 5, iclass 24, count 2 2006.257.11:23:07.58#ibcon#read 5, iclass 24, count 2 2006.257.11:23:07.58#ibcon#about to read 6, iclass 24, count 2 2006.257.11:23:07.58#ibcon#read 6, iclass 24, count 2 2006.257.11:23:07.58#ibcon#end of sib2, iclass 24, count 2 2006.257.11:23:07.58#ibcon#*mode == 0, iclass 24, count 2 2006.257.11:23:07.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.11:23:07.58#ibcon#[27=AT03-04\r\n] 2006.257.11:23:07.58#ibcon#*before write, iclass 24, count 2 2006.257.11:23:07.58#ibcon#enter sib2, iclass 24, count 2 2006.257.11:23:07.58#ibcon#flushed, iclass 24, count 2 2006.257.11:23:07.58#ibcon#about to write, iclass 24, count 2 2006.257.11:23:07.58#ibcon#wrote, iclass 24, count 2 2006.257.11:23:07.58#ibcon#about to read 3, iclass 24, count 2 2006.257.11:23:07.61#ibcon#read 3, iclass 24, count 2 2006.257.11:23:07.61#ibcon#about to read 4, iclass 24, count 2 2006.257.11:23:07.61#ibcon#read 4, iclass 24, count 2 2006.257.11:23:07.61#ibcon#about to read 5, iclass 24, count 2 2006.257.11:23:07.61#ibcon#read 5, iclass 24, count 2 2006.257.11:23:07.61#ibcon#about to read 6, iclass 24, count 2 2006.257.11:23:07.61#ibcon#read 6, iclass 24, count 2 2006.257.11:23:07.61#ibcon#end of sib2, iclass 24, count 2 2006.257.11:23:07.61#ibcon#*after write, iclass 24, count 2 2006.257.11:23:07.61#ibcon#*before return 0, iclass 24, count 2 2006.257.11:23:07.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:07.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:23:07.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.11:23:07.61#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:07.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:07.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:07.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:07.73#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:23:07.73#ibcon#first serial, iclass 24, count 0 2006.257.11:23:07.73#ibcon#enter sib2, iclass 24, count 0 2006.257.11:23:07.73#ibcon#flushed, iclass 24, count 0 2006.257.11:23:07.73#ibcon#about to write, iclass 24, count 0 2006.257.11:23:07.73#ibcon#wrote, iclass 24, count 0 2006.257.11:23:07.73#ibcon#about to read 3, iclass 24, count 0 2006.257.11:23:07.75#ibcon#read 3, iclass 24, count 0 2006.257.11:23:07.75#ibcon#about to read 4, iclass 24, count 0 2006.257.11:23:07.75#ibcon#read 4, iclass 24, count 0 2006.257.11:23:07.75#ibcon#about to read 5, iclass 24, count 0 2006.257.11:23:07.75#ibcon#read 5, iclass 24, count 0 2006.257.11:23:07.75#ibcon#about to read 6, iclass 24, count 0 2006.257.11:23:07.75#ibcon#read 6, iclass 24, count 0 2006.257.11:23:07.75#ibcon#end of sib2, iclass 24, count 0 2006.257.11:23:07.75#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:23:07.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:23:07.75#ibcon#[27=USB\r\n] 2006.257.11:23:07.75#ibcon#*before write, iclass 24, count 0 2006.257.11:23:07.75#ibcon#enter sib2, iclass 24, count 0 2006.257.11:23:07.75#ibcon#flushed, iclass 24, count 0 2006.257.11:23:07.75#ibcon#about to write, iclass 24, count 0 2006.257.11:23:07.75#ibcon#wrote, iclass 24, count 0 2006.257.11:23:07.75#ibcon#about to read 3, iclass 24, count 0 2006.257.11:23:07.78#ibcon#read 3, iclass 24, count 0 2006.257.11:23:07.78#ibcon#about to read 4, iclass 24, count 0 2006.257.11:23:07.78#ibcon#read 4, iclass 24, count 0 2006.257.11:23:07.78#ibcon#about to read 5, iclass 24, count 0 2006.257.11:23:07.78#ibcon#read 5, iclass 24, count 0 2006.257.11:23:07.78#ibcon#about to read 6, iclass 24, count 0 2006.257.11:23:07.78#ibcon#read 6, iclass 24, count 0 2006.257.11:23:07.78#ibcon#end of sib2, iclass 24, count 0 2006.257.11:23:07.78#ibcon#*after write, iclass 24, count 0 2006.257.11:23:07.78#ibcon#*before return 0, iclass 24, count 0 2006.257.11:23:07.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:07.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:23:07.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:23:07.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:23:07.78$vck44/vblo=4,679.99 2006.257.11:23:07.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.11:23:07.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.11:23:07.78#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:07.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:07.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:07.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:07.78#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:23:07.78#ibcon#first serial, iclass 26, count 0 2006.257.11:23:07.78#ibcon#enter sib2, iclass 26, count 0 2006.257.11:23:07.78#ibcon#flushed, iclass 26, count 0 2006.257.11:23:07.78#ibcon#about to write, iclass 26, count 0 2006.257.11:23:07.78#ibcon#wrote, iclass 26, count 0 2006.257.11:23:07.78#ibcon#about to read 3, iclass 26, count 0 2006.257.11:23:07.80#ibcon#read 3, iclass 26, count 0 2006.257.11:23:07.80#ibcon#about to read 4, iclass 26, count 0 2006.257.11:23:07.80#ibcon#read 4, iclass 26, count 0 2006.257.11:23:07.80#ibcon#about to read 5, iclass 26, count 0 2006.257.11:23:07.80#ibcon#read 5, iclass 26, count 0 2006.257.11:23:07.80#ibcon#about to read 6, iclass 26, count 0 2006.257.11:23:07.80#ibcon#read 6, iclass 26, count 0 2006.257.11:23:07.80#ibcon#end of sib2, iclass 26, count 0 2006.257.11:23:07.80#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:23:07.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:23:07.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:23:07.80#ibcon#*before write, iclass 26, count 0 2006.257.11:23:07.80#ibcon#enter sib2, iclass 26, count 0 2006.257.11:23:07.80#ibcon#flushed, iclass 26, count 0 2006.257.11:23:07.80#ibcon#about to write, iclass 26, count 0 2006.257.11:23:07.80#ibcon#wrote, iclass 26, count 0 2006.257.11:23:07.80#ibcon#about to read 3, iclass 26, count 0 2006.257.11:23:07.84#ibcon#read 3, iclass 26, count 0 2006.257.11:23:07.84#ibcon#about to read 4, iclass 26, count 0 2006.257.11:23:07.84#ibcon#read 4, iclass 26, count 0 2006.257.11:23:07.84#ibcon#about to read 5, iclass 26, count 0 2006.257.11:23:07.84#ibcon#read 5, iclass 26, count 0 2006.257.11:23:07.84#ibcon#about to read 6, iclass 26, count 0 2006.257.11:23:07.84#ibcon#read 6, iclass 26, count 0 2006.257.11:23:07.84#ibcon#end of sib2, iclass 26, count 0 2006.257.11:23:07.84#ibcon#*after write, iclass 26, count 0 2006.257.11:23:07.84#ibcon#*before return 0, iclass 26, count 0 2006.257.11:23:07.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:07.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:23:07.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:23:07.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:23:07.84$vck44/vb=4,5 2006.257.11:23:07.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.11:23:07.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.11:23:07.84#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:07.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:07.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:07.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:07.90#ibcon#enter wrdev, iclass 28, count 2 2006.257.11:23:07.90#ibcon#first serial, iclass 28, count 2 2006.257.11:23:07.90#ibcon#enter sib2, iclass 28, count 2 2006.257.11:23:07.90#ibcon#flushed, iclass 28, count 2 2006.257.11:23:07.90#ibcon#about to write, iclass 28, count 2 2006.257.11:23:07.90#ibcon#wrote, iclass 28, count 2 2006.257.11:23:07.90#ibcon#about to read 3, iclass 28, count 2 2006.257.11:23:07.92#ibcon#read 3, iclass 28, count 2 2006.257.11:23:07.92#ibcon#about to read 4, iclass 28, count 2 2006.257.11:23:07.92#ibcon#read 4, iclass 28, count 2 2006.257.11:23:07.92#ibcon#about to read 5, iclass 28, count 2 2006.257.11:23:07.92#ibcon#read 5, iclass 28, count 2 2006.257.11:23:07.92#ibcon#about to read 6, iclass 28, count 2 2006.257.11:23:07.92#ibcon#read 6, iclass 28, count 2 2006.257.11:23:07.92#ibcon#end of sib2, iclass 28, count 2 2006.257.11:23:07.92#ibcon#*mode == 0, iclass 28, count 2 2006.257.11:23:07.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.11:23:07.92#ibcon#[27=AT04-05\r\n] 2006.257.11:23:07.92#ibcon#*before write, iclass 28, count 2 2006.257.11:23:07.92#ibcon#enter sib2, iclass 28, count 2 2006.257.11:23:07.92#ibcon#flushed, iclass 28, count 2 2006.257.11:23:07.92#ibcon#about to write, iclass 28, count 2 2006.257.11:23:07.92#ibcon#wrote, iclass 28, count 2 2006.257.11:23:07.92#ibcon#about to read 3, iclass 28, count 2 2006.257.11:23:07.95#ibcon#read 3, iclass 28, count 2 2006.257.11:23:07.95#ibcon#about to read 4, iclass 28, count 2 2006.257.11:23:07.95#ibcon#read 4, iclass 28, count 2 2006.257.11:23:07.95#ibcon#about to read 5, iclass 28, count 2 2006.257.11:23:07.95#ibcon#read 5, iclass 28, count 2 2006.257.11:23:07.95#ibcon#about to read 6, iclass 28, count 2 2006.257.11:23:07.95#ibcon#read 6, iclass 28, count 2 2006.257.11:23:07.95#ibcon#end of sib2, iclass 28, count 2 2006.257.11:23:07.95#ibcon#*after write, iclass 28, count 2 2006.257.11:23:07.95#ibcon#*before return 0, iclass 28, count 2 2006.257.11:23:07.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:07.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:23:07.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.11:23:07.95#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:07.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:08.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:08.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:08.07#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:23:08.07#ibcon#first serial, iclass 28, count 0 2006.257.11:23:08.07#ibcon#enter sib2, iclass 28, count 0 2006.257.11:23:08.07#ibcon#flushed, iclass 28, count 0 2006.257.11:23:08.07#ibcon#about to write, iclass 28, count 0 2006.257.11:23:08.07#ibcon#wrote, iclass 28, count 0 2006.257.11:23:08.07#ibcon#about to read 3, iclass 28, count 0 2006.257.11:23:08.09#ibcon#read 3, iclass 28, count 0 2006.257.11:23:08.09#ibcon#about to read 4, iclass 28, count 0 2006.257.11:23:08.09#ibcon#read 4, iclass 28, count 0 2006.257.11:23:08.09#ibcon#about to read 5, iclass 28, count 0 2006.257.11:23:08.09#ibcon#read 5, iclass 28, count 0 2006.257.11:23:08.09#ibcon#about to read 6, iclass 28, count 0 2006.257.11:23:08.09#ibcon#read 6, iclass 28, count 0 2006.257.11:23:08.09#ibcon#end of sib2, iclass 28, count 0 2006.257.11:23:08.09#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:23:08.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:23:08.09#ibcon#[27=USB\r\n] 2006.257.11:23:08.09#ibcon#*before write, iclass 28, count 0 2006.257.11:23:08.09#ibcon#enter sib2, iclass 28, count 0 2006.257.11:23:08.09#ibcon#flushed, iclass 28, count 0 2006.257.11:23:08.09#ibcon#about to write, iclass 28, count 0 2006.257.11:23:08.09#ibcon#wrote, iclass 28, count 0 2006.257.11:23:08.09#ibcon#about to read 3, iclass 28, count 0 2006.257.11:23:08.12#ibcon#read 3, iclass 28, count 0 2006.257.11:23:08.12#ibcon#about to read 4, iclass 28, count 0 2006.257.11:23:08.12#ibcon#read 4, iclass 28, count 0 2006.257.11:23:08.12#ibcon#about to read 5, iclass 28, count 0 2006.257.11:23:08.12#ibcon#read 5, iclass 28, count 0 2006.257.11:23:08.12#ibcon#about to read 6, iclass 28, count 0 2006.257.11:23:08.12#ibcon#read 6, iclass 28, count 0 2006.257.11:23:08.12#ibcon#end of sib2, iclass 28, count 0 2006.257.11:23:08.12#ibcon#*after write, iclass 28, count 0 2006.257.11:23:08.12#ibcon#*before return 0, iclass 28, count 0 2006.257.11:23:08.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:08.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:23:08.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:23:08.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:23:08.12$vck44/vblo=5,709.99 2006.257.11:23:08.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.11:23:08.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.11:23:08.12#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:08.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:08.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:08.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:08.12#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:23:08.12#ibcon#first serial, iclass 30, count 0 2006.257.11:23:08.12#ibcon#enter sib2, iclass 30, count 0 2006.257.11:23:08.12#ibcon#flushed, iclass 30, count 0 2006.257.11:23:08.12#ibcon#about to write, iclass 30, count 0 2006.257.11:23:08.12#ibcon#wrote, iclass 30, count 0 2006.257.11:23:08.12#ibcon#about to read 3, iclass 30, count 0 2006.257.11:23:08.14#ibcon#read 3, iclass 30, count 0 2006.257.11:23:08.14#ibcon#about to read 4, iclass 30, count 0 2006.257.11:23:08.14#ibcon#read 4, iclass 30, count 0 2006.257.11:23:08.14#ibcon#about to read 5, iclass 30, count 0 2006.257.11:23:08.14#ibcon#read 5, iclass 30, count 0 2006.257.11:23:08.14#ibcon#about to read 6, iclass 30, count 0 2006.257.11:23:08.14#ibcon#read 6, iclass 30, count 0 2006.257.11:23:08.14#ibcon#end of sib2, iclass 30, count 0 2006.257.11:23:08.14#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:23:08.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:23:08.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:23:08.14#ibcon#*before write, iclass 30, count 0 2006.257.11:23:08.14#ibcon#enter sib2, iclass 30, count 0 2006.257.11:23:08.14#ibcon#flushed, iclass 30, count 0 2006.257.11:23:08.14#ibcon#about to write, iclass 30, count 0 2006.257.11:23:08.14#ibcon#wrote, iclass 30, count 0 2006.257.11:23:08.14#ibcon#about to read 3, iclass 30, count 0 2006.257.11:23:08.18#ibcon#read 3, iclass 30, count 0 2006.257.11:23:08.18#ibcon#about to read 4, iclass 30, count 0 2006.257.11:23:08.18#ibcon#read 4, iclass 30, count 0 2006.257.11:23:08.18#ibcon#about to read 5, iclass 30, count 0 2006.257.11:23:08.18#ibcon#read 5, iclass 30, count 0 2006.257.11:23:08.18#ibcon#about to read 6, iclass 30, count 0 2006.257.11:23:08.18#ibcon#read 6, iclass 30, count 0 2006.257.11:23:08.18#ibcon#end of sib2, iclass 30, count 0 2006.257.11:23:08.18#ibcon#*after write, iclass 30, count 0 2006.257.11:23:08.18#ibcon#*before return 0, iclass 30, count 0 2006.257.11:23:08.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:08.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:23:08.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:23:08.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:23:08.18$vck44/vb=5,4 2006.257.11:23:08.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.11:23:08.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.11:23:08.18#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:08.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:08.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:08.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:08.24#ibcon#enter wrdev, iclass 32, count 2 2006.257.11:23:08.24#ibcon#first serial, iclass 32, count 2 2006.257.11:23:08.24#ibcon#enter sib2, iclass 32, count 2 2006.257.11:23:08.24#ibcon#flushed, iclass 32, count 2 2006.257.11:23:08.24#ibcon#about to write, iclass 32, count 2 2006.257.11:23:08.24#ibcon#wrote, iclass 32, count 2 2006.257.11:23:08.24#ibcon#about to read 3, iclass 32, count 2 2006.257.11:23:08.26#ibcon#read 3, iclass 32, count 2 2006.257.11:23:08.26#ibcon#about to read 4, iclass 32, count 2 2006.257.11:23:08.26#ibcon#read 4, iclass 32, count 2 2006.257.11:23:08.26#ibcon#about to read 5, iclass 32, count 2 2006.257.11:23:08.26#ibcon#read 5, iclass 32, count 2 2006.257.11:23:08.26#ibcon#about to read 6, iclass 32, count 2 2006.257.11:23:08.26#ibcon#read 6, iclass 32, count 2 2006.257.11:23:08.26#ibcon#end of sib2, iclass 32, count 2 2006.257.11:23:08.26#ibcon#*mode == 0, iclass 32, count 2 2006.257.11:23:08.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.11:23:08.26#ibcon#[27=AT05-04\r\n] 2006.257.11:23:08.26#ibcon#*before write, iclass 32, count 2 2006.257.11:23:08.26#ibcon#enter sib2, iclass 32, count 2 2006.257.11:23:08.26#ibcon#flushed, iclass 32, count 2 2006.257.11:23:08.26#ibcon#about to write, iclass 32, count 2 2006.257.11:23:08.26#ibcon#wrote, iclass 32, count 2 2006.257.11:23:08.26#ibcon#about to read 3, iclass 32, count 2 2006.257.11:23:08.29#ibcon#read 3, iclass 32, count 2 2006.257.11:23:08.29#ibcon#about to read 4, iclass 32, count 2 2006.257.11:23:08.29#ibcon#read 4, iclass 32, count 2 2006.257.11:23:08.29#ibcon#about to read 5, iclass 32, count 2 2006.257.11:23:08.29#ibcon#read 5, iclass 32, count 2 2006.257.11:23:08.29#ibcon#about to read 6, iclass 32, count 2 2006.257.11:23:08.29#ibcon#read 6, iclass 32, count 2 2006.257.11:23:08.29#ibcon#end of sib2, iclass 32, count 2 2006.257.11:23:08.29#ibcon#*after write, iclass 32, count 2 2006.257.11:23:08.29#ibcon#*before return 0, iclass 32, count 2 2006.257.11:23:08.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:08.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:23:08.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.11:23:08.29#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:08.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:08.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:08.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:08.41#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:23:08.41#ibcon#first serial, iclass 32, count 0 2006.257.11:23:08.41#ibcon#enter sib2, iclass 32, count 0 2006.257.11:23:08.41#ibcon#flushed, iclass 32, count 0 2006.257.11:23:08.41#ibcon#about to write, iclass 32, count 0 2006.257.11:23:08.41#ibcon#wrote, iclass 32, count 0 2006.257.11:23:08.41#ibcon#about to read 3, iclass 32, count 0 2006.257.11:23:08.43#ibcon#read 3, iclass 32, count 0 2006.257.11:23:08.43#ibcon#about to read 4, iclass 32, count 0 2006.257.11:23:08.43#ibcon#read 4, iclass 32, count 0 2006.257.11:23:08.43#ibcon#about to read 5, iclass 32, count 0 2006.257.11:23:08.43#ibcon#read 5, iclass 32, count 0 2006.257.11:23:08.43#ibcon#about to read 6, iclass 32, count 0 2006.257.11:23:08.43#ibcon#read 6, iclass 32, count 0 2006.257.11:23:08.43#ibcon#end of sib2, iclass 32, count 0 2006.257.11:23:08.43#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:23:08.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:23:08.43#ibcon#[27=USB\r\n] 2006.257.11:23:08.43#ibcon#*before write, iclass 32, count 0 2006.257.11:23:08.43#ibcon#enter sib2, iclass 32, count 0 2006.257.11:23:08.43#ibcon#flushed, iclass 32, count 0 2006.257.11:23:08.43#ibcon#about to write, iclass 32, count 0 2006.257.11:23:08.43#ibcon#wrote, iclass 32, count 0 2006.257.11:23:08.43#ibcon#about to read 3, iclass 32, count 0 2006.257.11:23:08.46#ibcon#read 3, iclass 32, count 0 2006.257.11:23:08.46#ibcon#about to read 4, iclass 32, count 0 2006.257.11:23:08.46#ibcon#read 4, iclass 32, count 0 2006.257.11:23:08.46#ibcon#about to read 5, iclass 32, count 0 2006.257.11:23:08.46#ibcon#read 5, iclass 32, count 0 2006.257.11:23:08.46#ibcon#about to read 6, iclass 32, count 0 2006.257.11:23:08.46#ibcon#read 6, iclass 32, count 0 2006.257.11:23:08.46#ibcon#end of sib2, iclass 32, count 0 2006.257.11:23:08.46#ibcon#*after write, iclass 32, count 0 2006.257.11:23:08.46#ibcon#*before return 0, iclass 32, count 0 2006.257.11:23:08.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:08.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:23:08.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:23:08.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:23:08.46$vck44/vblo=6,719.99 2006.257.11:23:08.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.11:23:08.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.11:23:08.46#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:08.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:08.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:08.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:08.46#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:23:08.46#ibcon#first serial, iclass 34, count 0 2006.257.11:23:08.46#ibcon#enter sib2, iclass 34, count 0 2006.257.11:23:08.46#ibcon#flushed, iclass 34, count 0 2006.257.11:23:08.46#ibcon#about to write, iclass 34, count 0 2006.257.11:23:08.46#ibcon#wrote, iclass 34, count 0 2006.257.11:23:08.46#ibcon#about to read 3, iclass 34, count 0 2006.257.11:23:08.48#ibcon#read 3, iclass 34, count 0 2006.257.11:23:08.48#ibcon#about to read 4, iclass 34, count 0 2006.257.11:23:08.48#ibcon#read 4, iclass 34, count 0 2006.257.11:23:08.48#ibcon#about to read 5, iclass 34, count 0 2006.257.11:23:08.48#ibcon#read 5, iclass 34, count 0 2006.257.11:23:08.48#ibcon#about to read 6, iclass 34, count 0 2006.257.11:23:08.48#ibcon#read 6, iclass 34, count 0 2006.257.11:23:08.48#ibcon#end of sib2, iclass 34, count 0 2006.257.11:23:08.48#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:23:08.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:23:08.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:23:08.48#ibcon#*before write, iclass 34, count 0 2006.257.11:23:08.48#ibcon#enter sib2, iclass 34, count 0 2006.257.11:23:08.48#ibcon#flushed, iclass 34, count 0 2006.257.11:23:08.48#ibcon#about to write, iclass 34, count 0 2006.257.11:23:08.48#ibcon#wrote, iclass 34, count 0 2006.257.11:23:08.48#ibcon#about to read 3, iclass 34, count 0 2006.257.11:23:08.52#ibcon#read 3, iclass 34, count 0 2006.257.11:23:08.52#ibcon#about to read 4, iclass 34, count 0 2006.257.11:23:08.52#ibcon#read 4, iclass 34, count 0 2006.257.11:23:08.52#ibcon#about to read 5, iclass 34, count 0 2006.257.11:23:08.52#ibcon#read 5, iclass 34, count 0 2006.257.11:23:08.52#ibcon#about to read 6, iclass 34, count 0 2006.257.11:23:08.52#ibcon#read 6, iclass 34, count 0 2006.257.11:23:08.52#ibcon#end of sib2, iclass 34, count 0 2006.257.11:23:08.52#ibcon#*after write, iclass 34, count 0 2006.257.11:23:08.52#ibcon#*before return 0, iclass 34, count 0 2006.257.11:23:08.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:08.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:23:08.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:23:08.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:23:08.52$vck44/vb=6,4 2006.257.11:23:08.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.11:23:08.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.11:23:08.52#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:08.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:23:08.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:23:08.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:23:08.58#ibcon#enter wrdev, iclass 36, count 2 2006.257.11:23:08.58#ibcon#first serial, iclass 36, count 2 2006.257.11:23:08.58#ibcon#enter sib2, iclass 36, count 2 2006.257.11:23:08.58#ibcon#flushed, iclass 36, count 2 2006.257.11:23:08.58#ibcon#about to write, iclass 36, count 2 2006.257.11:23:08.58#ibcon#wrote, iclass 36, count 2 2006.257.11:23:08.58#ibcon#about to read 3, iclass 36, count 2 2006.257.11:23:08.60#ibcon#read 3, iclass 36, count 2 2006.257.11:23:08.60#ibcon#about to read 4, iclass 36, count 2 2006.257.11:23:08.60#ibcon#read 4, iclass 36, count 2 2006.257.11:23:08.60#ibcon#about to read 5, iclass 36, count 2 2006.257.11:23:08.60#ibcon#read 5, iclass 36, count 2 2006.257.11:23:08.60#ibcon#about to read 6, iclass 36, count 2 2006.257.11:23:08.60#ibcon#read 6, iclass 36, count 2 2006.257.11:23:08.60#ibcon#end of sib2, iclass 36, count 2 2006.257.11:23:08.60#ibcon#*mode == 0, iclass 36, count 2 2006.257.11:23:08.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.11:23:08.60#ibcon#[27=AT06-04\r\n] 2006.257.11:23:08.60#ibcon#*before write, iclass 36, count 2 2006.257.11:23:08.60#ibcon#enter sib2, iclass 36, count 2 2006.257.11:23:08.60#ibcon#flushed, iclass 36, count 2 2006.257.11:23:08.60#ibcon#about to write, iclass 36, count 2 2006.257.11:23:08.60#ibcon#wrote, iclass 36, count 2 2006.257.11:23:08.60#ibcon#about to read 3, iclass 36, count 2 2006.257.11:23:08.63#ibcon#read 3, iclass 36, count 2 2006.257.11:23:08.63#ibcon#about to read 4, iclass 36, count 2 2006.257.11:23:08.63#ibcon#read 4, iclass 36, count 2 2006.257.11:23:08.63#ibcon#about to read 5, iclass 36, count 2 2006.257.11:23:08.63#ibcon#read 5, iclass 36, count 2 2006.257.11:23:08.63#ibcon#about to read 6, iclass 36, count 2 2006.257.11:23:08.63#ibcon#read 6, iclass 36, count 2 2006.257.11:23:08.63#ibcon#end of sib2, iclass 36, count 2 2006.257.11:23:08.63#ibcon#*after write, iclass 36, count 2 2006.257.11:23:08.63#ibcon#*before return 0, iclass 36, count 2 2006.257.11:23:08.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:23:08.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:23:08.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.11:23:08.63#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:08.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:23:08.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:23:08.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:23:08.75#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:23:08.75#ibcon#first serial, iclass 36, count 0 2006.257.11:23:08.75#ibcon#enter sib2, iclass 36, count 0 2006.257.11:23:08.75#ibcon#flushed, iclass 36, count 0 2006.257.11:23:08.75#ibcon#about to write, iclass 36, count 0 2006.257.11:23:08.75#ibcon#wrote, iclass 36, count 0 2006.257.11:23:08.75#ibcon#about to read 3, iclass 36, count 0 2006.257.11:23:08.77#ibcon#read 3, iclass 36, count 0 2006.257.11:23:08.77#ibcon#about to read 4, iclass 36, count 0 2006.257.11:23:08.77#ibcon#read 4, iclass 36, count 0 2006.257.11:23:08.77#ibcon#about to read 5, iclass 36, count 0 2006.257.11:23:08.77#ibcon#read 5, iclass 36, count 0 2006.257.11:23:08.77#ibcon#about to read 6, iclass 36, count 0 2006.257.11:23:08.77#ibcon#read 6, iclass 36, count 0 2006.257.11:23:08.77#ibcon#end of sib2, iclass 36, count 0 2006.257.11:23:08.77#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:23:08.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:23:08.77#ibcon#[27=USB\r\n] 2006.257.11:23:08.77#ibcon#*before write, iclass 36, count 0 2006.257.11:23:08.77#ibcon#enter sib2, iclass 36, count 0 2006.257.11:23:08.77#ibcon#flushed, iclass 36, count 0 2006.257.11:23:08.77#ibcon#about to write, iclass 36, count 0 2006.257.11:23:08.77#ibcon#wrote, iclass 36, count 0 2006.257.11:23:08.77#ibcon#about to read 3, iclass 36, count 0 2006.257.11:23:08.80#ibcon#read 3, iclass 36, count 0 2006.257.11:23:08.80#ibcon#about to read 4, iclass 36, count 0 2006.257.11:23:08.80#ibcon#read 4, iclass 36, count 0 2006.257.11:23:08.80#ibcon#about to read 5, iclass 36, count 0 2006.257.11:23:08.80#ibcon#read 5, iclass 36, count 0 2006.257.11:23:08.80#ibcon#about to read 6, iclass 36, count 0 2006.257.11:23:08.80#ibcon#read 6, iclass 36, count 0 2006.257.11:23:08.80#ibcon#end of sib2, iclass 36, count 0 2006.257.11:23:08.80#ibcon#*after write, iclass 36, count 0 2006.257.11:23:08.80#ibcon#*before return 0, iclass 36, count 0 2006.257.11:23:08.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:23:08.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:23:08.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:23:08.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:23:08.80$vck44/vblo=7,734.99 2006.257.11:23:08.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.11:23:08.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.11:23:08.80#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:08.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:23:08.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:23:08.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:23:08.80#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:23:08.80#ibcon#first serial, iclass 38, count 0 2006.257.11:23:08.80#ibcon#enter sib2, iclass 38, count 0 2006.257.11:23:08.80#ibcon#flushed, iclass 38, count 0 2006.257.11:23:08.80#ibcon#about to write, iclass 38, count 0 2006.257.11:23:08.80#ibcon#wrote, iclass 38, count 0 2006.257.11:23:08.80#ibcon#about to read 3, iclass 38, count 0 2006.257.11:23:08.82#ibcon#read 3, iclass 38, count 0 2006.257.11:23:08.82#ibcon#about to read 4, iclass 38, count 0 2006.257.11:23:08.82#ibcon#read 4, iclass 38, count 0 2006.257.11:23:08.82#ibcon#about to read 5, iclass 38, count 0 2006.257.11:23:08.82#ibcon#read 5, iclass 38, count 0 2006.257.11:23:08.82#ibcon#about to read 6, iclass 38, count 0 2006.257.11:23:08.82#ibcon#read 6, iclass 38, count 0 2006.257.11:23:08.82#ibcon#end of sib2, iclass 38, count 0 2006.257.11:23:08.82#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:23:08.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:23:08.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:23:08.82#ibcon#*before write, iclass 38, count 0 2006.257.11:23:08.82#ibcon#enter sib2, iclass 38, count 0 2006.257.11:23:08.82#ibcon#flushed, iclass 38, count 0 2006.257.11:23:08.82#ibcon#about to write, iclass 38, count 0 2006.257.11:23:08.82#ibcon#wrote, iclass 38, count 0 2006.257.11:23:08.82#ibcon#about to read 3, iclass 38, count 0 2006.257.11:23:08.86#ibcon#read 3, iclass 38, count 0 2006.257.11:23:08.86#ibcon#about to read 4, iclass 38, count 0 2006.257.11:23:08.86#ibcon#read 4, iclass 38, count 0 2006.257.11:23:08.86#ibcon#about to read 5, iclass 38, count 0 2006.257.11:23:08.86#ibcon#read 5, iclass 38, count 0 2006.257.11:23:08.86#ibcon#about to read 6, iclass 38, count 0 2006.257.11:23:08.86#ibcon#read 6, iclass 38, count 0 2006.257.11:23:08.86#ibcon#end of sib2, iclass 38, count 0 2006.257.11:23:08.86#ibcon#*after write, iclass 38, count 0 2006.257.11:23:08.86#ibcon#*before return 0, iclass 38, count 0 2006.257.11:23:08.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:23:08.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:23:08.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:23:08.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:23:08.86$vck44/vb=7,4 2006.257.11:23:08.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.11:23:08.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.11:23:08.86#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:08.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:23:08.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:23:08.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:23:08.92#ibcon#enter wrdev, iclass 40, count 2 2006.257.11:23:08.92#ibcon#first serial, iclass 40, count 2 2006.257.11:23:08.92#ibcon#enter sib2, iclass 40, count 2 2006.257.11:23:08.92#ibcon#flushed, iclass 40, count 2 2006.257.11:23:08.92#ibcon#about to write, iclass 40, count 2 2006.257.11:23:08.92#ibcon#wrote, iclass 40, count 2 2006.257.11:23:08.92#ibcon#about to read 3, iclass 40, count 2 2006.257.11:23:08.94#ibcon#read 3, iclass 40, count 2 2006.257.11:23:08.94#ibcon#about to read 4, iclass 40, count 2 2006.257.11:23:08.94#ibcon#read 4, iclass 40, count 2 2006.257.11:23:08.94#ibcon#about to read 5, iclass 40, count 2 2006.257.11:23:08.94#ibcon#read 5, iclass 40, count 2 2006.257.11:23:08.94#ibcon#about to read 6, iclass 40, count 2 2006.257.11:23:08.94#ibcon#read 6, iclass 40, count 2 2006.257.11:23:08.94#ibcon#end of sib2, iclass 40, count 2 2006.257.11:23:08.94#ibcon#*mode == 0, iclass 40, count 2 2006.257.11:23:08.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.11:23:08.94#ibcon#[27=AT07-04\r\n] 2006.257.11:23:08.94#ibcon#*before write, iclass 40, count 2 2006.257.11:23:08.94#ibcon#enter sib2, iclass 40, count 2 2006.257.11:23:08.94#ibcon#flushed, iclass 40, count 2 2006.257.11:23:08.94#ibcon#about to write, iclass 40, count 2 2006.257.11:23:08.94#ibcon#wrote, iclass 40, count 2 2006.257.11:23:08.94#ibcon#about to read 3, iclass 40, count 2 2006.257.11:23:08.97#ibcon#read 3, iclass 40, count 2 2006.257.11:23:08.97#ibcon#about to read 4, iclass 40, count 2 2006.257.11:23:08.97#ibcon#read 4, iclass 40, count 2 2006.257.11:23:08.97#ibcon#about to read 5, iclass 40, count 2 2006.257.11:23:08.97#ibcon#read 5, iclass 40, count 2 2006.257.11:23:08.97#ibcon#about to read 6, iclass 40, count 2 2006.257.11:23:08.97#ibcon#read 6, iclass 40, count 2 2006.257.11:23:08.97#ibcon#end of sib2, iclass 40, count 2 2006.257.11:23:08.97#ibcon#*after write, iclass 40, count 2 2006.257.11:23:08.97#ibcon#*before return 0, iclass 40, count 2 2006.257.11:23:08.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:23:08.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:23:08.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.11:23:08.97#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:08.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:23:09.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:23:09.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:23:09.09#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:23:09.09#ibcon#first serial, iclass 40, count 0 2006.257.11:23:09.09#ibcon#enter sib2, iclass 40, count 0 2006.257.11:23:09.09#ibcon#flushed, iclass 40, count 0 2006.257.11:23:09.09#ibcon#about to write, iclass 40, count 0 2006.257.11:23:09.09#ibcon#wrote, iclass 40, count 0 2006.257.11:23:09.09#ibcon#about to read 3, iclass 40, count 0 2006.257.11:23:09.11#ibcon#read 3, iclass 40, count 0 2006.257.11:23:09.11#ibcon#about to read 4, iclass 40, count 0 2006.257.11:23:09.11#ibcon#read 4, iclass 40, count 0 2006.257.11:23:09.11#ibcon#about to read 5, iclass 40, count 0 2006.257.11:23:09.11#ibcon#read 5, iclass 40, count 0 2006.257.11:23:09.11#ibcon#about to read 6, iclass 40, count 0 2006.257.11:23:09.11#ibcon#read 6, iclass 40, count 0 2006.257.11:23:09.11#ibcon#end of sib2, iclass 40, count 0 2006.257.11:23:09.11#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:23:09.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:23:09.11#ibcon#[27=USB\r\n] 2006.257.11:23:09.11#ibcon#*before write, iclass 40, count 0 2006.257.11:23:09.11#ibcon#enter sib2, iclass 40, count 0 2006.257.11:23:09.11#ibcon#flushed, iclass 40, count 0 2006.257.11:23:09.11#ibcon#about to write, iclass 40, count 0 2006.257.11:23:09.11#ibcon#wrote, iclass 40, count 0 2006.257.11:23:09.11#ibcon#about to read 3, iclass 40, count 0 2006.257.11:23:09.14#ibcon#read 3, iclass 40, count 0 2006.257.11:23:09.14#ibcon#about to read 4, iclass 40, count 0 2006.257.11:23:09.14#ibcon#read 4, iclass 40, count 0 2006.257.11:23:09.14#ibcon#about to read 5, iclass 40, count 0 2006.257.11:23:09.14#ibcon#read 5, iclass 40, count 0 2006.257.11:23:09.14#ibcon#about to read 6, iclass 40, count 0 2006.257.11:23:09.14#ibcon#read 6, iclass 40, count 0 2006.257.11:23:09.14#ibcon#end of sib2, iclass 40, count 0 2006.257.11:23:09.14#ibcon#*after write, iclass 40, count 0 2006.257.11:23:09.14#ibcon#*before return 0, iclass 40, count 0 2006.257.11:23:09.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:23:09.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:23:09.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:23:09.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:23:09.14$vck44/vblo=8,744.99 2006.257.11:23:09.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.11:23:09.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.11:23:09.14#ibcon#ireg 17 cls_cnt 0 2006.257.11:23:09.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:09.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:09.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:09.14#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:23:09.14#ibcon#first serial, iclass 4, count 0 2006.257.11:23:09.14#ibcon#enter sib2, iclass 4, count 0 2006.257.11:23:09.14#ibcon#flushed, iclass 4, count 0 2006.257.11:23:09.14#ibcon#about to write, iclass 4, count 0 2006.257.11:23:09.14#ibcon#wrote, iclass 4, count 0 2006.257.11:23:09.14#ibcon#about to read 3, iclass 4, count 0 2006.257.11:23:09.16#ibcon#read 3, iclass 4, count 0 2006.257.11:23:09.16#ibcon#about to read 4, iclass 4, count 0 2006.257.11:23:09.16#ibcon#read 4, iclass 4, count 0 2006.257.11:23:09.16#ibcon#about to read 5, iclass 4, count 0 2006.257.11:23:09.16#ibcon#read 5, iclass 4, count 0 2006.257.11:23:09.16#ibcon#about to read 6, iclass 4, count 0 2006.257.11:23:09.16#ibcon#read 6, iclass 4, count 0 2006.257.11:23:09.16#ibcon#end of sib2, iclass 4, count 0 2006.257.11:23:09.16#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:23:09.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:23:09.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:23:09.16#ibcon#*before write, iclass 4, count 0 2006.257.11:23:09.16#ibcon#enter sib2, iclass 4, count 0 2006.257.11:23:09.16#ibcon#flushed, iclass 4, count 0 2006.257.11:23:09.16#ibcon#about to write, iclass 4, count 0 2006.257.11:23:09.16#ibcon#wrote, iclass 4, count 0 2006.257.11:23:09.16#ibcon#about to read 3, iclass 4, count 0 2006.257.11:23:09.20#ibcon#read 3, iclass 4, count 0 2006.257.11:23:09.20#ibcon#about to read 4, iclass 4, count 0 2006.257.11:23:09.20#ibcon#read 4, iclass 4, count 0 2006.257.11:23:09.20#ibcon#about to read 5, iclass 4, count 0 2006.257.11:23:09.20#ibcon#read 5, iclass 4, count 0 2006.257.11:23:09.20#ibcon#about to read 6, iclass 4, count 0 2006.257.11:23:09.20#ibcon#read 6, iclass 4, count 0 2006.257.11:23:09.20#ibcon#end of sib2, iclass 4, count 0 2006.257.11:23:09.20#ibcon#*after write, iclass 4, count 0 2006.257.11:23:09.20#ibcon#*before return 0, iclass 4, count 0 2006.257.11:23:09.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:09.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:23:09.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:23:09.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:23:09.20$vck44/vb=8,4 2006.257.11:23:09.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.11:23:09.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.11:23:09.20#ibcon#ireg 11 cls_cnt 2 2006.257.11:23:09.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:09.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:09.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:09.26#ibcon#enter wrdev, iclass 6, count 2 2006.257.11:23:09.26#ibcon#first serial, iclass 6, count 2 2006.257.11:23:09.26#ibcon#enter sib2, iclass 6, count 2 2006.257.11:23:09.26#ibcon#flushed, iclass 6, count 2 2006.257.11:23:09.26#ibcon#about to write, iclass 6, count 2 2006.257.11:23:09.26#ibcon#wrote, iclass 6, count 2 2006.257.11:23:09.26#ibcon#about to read 3, iclass 6, count 2 2006.257.11:23:09.28#ibcon#read 3, iclass 6, count 2 2006.257.11:23:09.28#ibcon#about to read 4, iclass 6, count 2 2006.257.11:23:09.28#ibcon#read 4, iclass 6, count 2 2006.257.11:23:09.28#ibcon#about to read 5, iclass 6, count 2 2006.257.11:23:09.28#ibcon#read 5, iclass 6, count 2 2006.257.11:23:09.28#ibcon#about to read 6, iclass 6, count 2 2006.257.11:23:09.28#ibcon#read 6, iclass 6, count 2 2006.257.11:23:09.28#ibcon#end of sib2, iclass 6, count 2 2006.257.11:23:09.28#ibcon#*mode == 0, iclass 6, count 2 2006.257.11:23:09.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.11:23:09.28#ibcon#[27=AT08-04\r\n] 2006.257.11:23:09.28#ibcon#*before write, iclass 6, count 2 2006.257.11:23:09.28#ibcon#enter sib2, iclass 6, count 2 2006.257.11:23:09.28#ibcon#flushed, iclass 6, count 2 2006.257.11:23:09.28#ibcon#about to write, iclass 6, count 2 2006.257.11:23:09.28#ibcon#wrote, iclass 6, count 2 2006.257.11:23:09.28#ibcon#about to read 3, iclass 6, count 2 2006.257.11:23:09.31#ibcon#read 3, iclass 6, count 2 2006.257.11:23:09.31#ibcon#about to read 4, iclass 6, count 2 2006.257.11:23:09.31#ibcon#read 4, iclass 6, count 2 2006.257.11:23:09.31#ibcon#about to read 5, iclass 6, count 2 2006.257.11:23:09.31#ibcon#read 5, iclass 6, count 2 2006.257.11:23:09.31#ibcon#about to read 6, iclass 6, count 2 2006.257.11:23:09.31#ibcon#read 6, iclass 6, count 2 2006.257.11:23:09.31#ibcon#end of sib2, iclass 6, count 2 2006.257.11:23:09.31#ibcon#*after write, iclass 6, count 2 2006.257.11:23:09.31#ibcon#*before return 0, iclass 6, count 2 2006.257.11:23:09.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:09.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:23:09.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.11:23:09.31#ibcon#ireg 7 cls_cnt 0 2006.257.11:23:09.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:09.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:09.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:09.43#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:23:09.43#ibcon#first serial, iclass 6, count 0 2006.257.11:23:09.43#ibcon#enter sib2, iclass 6, count 0 2006.257.11:23:09.43#ibcon#flushed, iclass 6, count 0 2006.257.11:23:09.43#ibcon#about to write, iclass 6, count 0 2006.257.11:23:09.43#ibcon#wrote, iclass 6, count 0 2006.257.11:23:09.43#ibcon#about to read 3, iclass 6, count 0 2006.257.11:23:09.45#ibcon#read 3, iclass 6, count 0 2006.257.11:23:09.45#ibcon#about to read 4, iclass 6, count 0 2006.257.11:23:09.45#ibcon#read 4, iclass 6, count 0 2006.257.11:23:09.45#ibcon#about to read 5, iclass 6, count 0 2006.257.11:23:09.45#ibcon#read 5, iclass 6, count 0 2006.257.11:23:09.45#ibcon#about to read 6, iclass 6, count 0 2006.257.11:23:09.45#ibcon#read 6, iclass 6, count 0 2006.257.11:23:09.45#ibcon#end of sib2, iclass 6, count 0 2006.257.11:23:09.45#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:23:09.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:23:09.45#ibcon#[27=USB\r\n] 2006.257.11:23:09.45#ibcon#*before write, iclass 6, count 0 2006.257.11:23:09.45#ibcon#enter sib2, iclass 6, count 0 2006.257.11:23:09.45#ibcon#flushed, iclass 6, count 0 2006.257.11:23:09.45#ibcon#about to write, iclass 6, count 0 2006.257.11:23:09.45#ibcon#wrote, iclass 6, count 0 2006.257.11:23:09.45#ibcon#about to read 3, iclass 6, count 0 2006.257.11:23:09.48#ibcon#read 3, iclass 6, count 0 2006.257.11:23:09.48#ibcon#about to read 4, iclass 6, count 0 2006.257.11:23:09.48#ibcon#read 4, iclass 6, count 0 2006.257.11:23:09.48#ibcon#about to read 5, iclass 6, count 0 2006.257.11:23:09.48#ibcon#read 5, iclass 6, count 0 2006.257.11:23:09.48#ibcon#about to read 6, iclass 6, count 0 2006.257.11:23:09.48#ibcon#read 6, iclass 6, count 0 2006.257.11:23:09.48#ibcon#end of sib2, iclass 6, count 0 2006.257.11:23:09.48#ibcon#*after write, iclass 6, count 0 2006.257.11:23:09.48#ibcon#*before return 0, iclass 6, count 0 2006.257.11:23:09.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:09.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:23:09.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:23:09.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:23:09.48$vck44/vabw=wide 2006.257.11:23:09.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.11:23:09.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.11:23:09.48#ibcon#ireg 8 cls_cnt 0 2006.257.11:23:09.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:09.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:09.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:09.48#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:23:09.48#ibcon#first serial, iclass 10, count 0 2006.257.11:23:09.48#ibcon#enter sib2, iclass 10, count 0 2006.257.11:23:09.48#ibcon#flushed, iclass 10, count 0 2006.257.11:23:09.48#ibcon#about to write, iclass 10, count 0 2006.257.11:23:09.48#ibcon#wrote, iclass 10, count 0 2006.257.11:23:09.48#ibcon#about to read 3, iclass 10, count 0 2006.257.11:23:09.50#ibcon#read 3, iclass 10, count 0 2006.257.11:23:09.50#ibcon#about to read 4, iclass 10, count 0 2006.257.11:23:09.50#ibcon#read 4, iclass 10, count 0 2006.257.11:23:09.50#ibcon#about to read 5, iclass 10, count 0 2006.257.11:23:09.50#ibcon#read 5, iclass 10, count 0 2006.257.11:23:09.50#ibcon#about to read 6, iclass 10, count 0 2006.257.11:23:09.50#ibcon#read 6, iclass 10, count 0 2006.257.11:23:09.50#ibcon#end of sib2, iclass 10, count 0 2006.257.11:23:09.50#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:23:09.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:23:09.50#ibcon#[25=BW32\r\n] 2006.257.11:23:09.50#ibcon#*before write, iclass 10, count 0 2006.257.11:23:09.50#ibcon#enter sib2, iclass 10, count 0 2006.257.11:23:09.50#ibcon#flushed, iclass 10, count 0 2006.257.11:23:09.50#ibcon#about to write, iclass 10, count 0 2006.257.11:23:09.50#ibcon#wrote, iclass 10, count 0 2006.257.11:23:09.50#ibcon#about to read 3, iclass 10, count 0 2006.257.11:23:09.53#ibcon#read 3, iclass 10, count 0 2006.257.11:23:09.53#ibcon#about to read 4, iclass 10, count 0 2006.257.11:23:09.53#ibcon#read 4, iclass 10, count 0 2006.257.11:23:09.53#ibcon#about to read 5, iclass 10, count 0 2006.257.11:23:09.53#ibcon#read 5, iclass 10, count 0 2006.257.11:23:09.53#ibcon#about to read 6, iclass 10, count 0 2006.257.11:23:09.53#ibcon#read 6, iclass 10, count 0 2006.257.11:23:09.53#ibcon#end of sib2, iclass 10, count 0 2006.257.11:23:09.53#ibcon#*after write, iclass 10, count 0 2006.257.11:23:09.53#ibcon#*before return 0, iclass 10, count 0 2006.257.11:23:09.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:09.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:23:09.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:23:09.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:23:09.53$vck44/vbbw=wide 2006.257.11:23:09.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.11:23:09.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.11:23:09.53#ibcon#ireg 8 cls_cnt 0 2006.257.11:23:09.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:23:09.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:23:09.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:23:09.60#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:23:09.60#ibcon#first serial, iclass 12, count 0 2006.257.11:23:09.60#ibcon#enter sib2, iclass 12, count 0 2006.257.11:23:09.60#ibcon#flushed, iclass 12, count 0 2006.257.11:23:09.60#ibcon#about to write, iclass 12, count 0 2006.257.11:23:09.60#ibcon#wrote, iclass 12, count 0 2006.257.11:23:09.60#ibcon#about to read 3, iclass 12, count 0 2006.257.11:23:09.62#ibcon#read 3, iclass 12, count 0 2006.257.11:23:09.62#ibcon#about to read 4, iclass 12, count 0 2006.257.11:23:09.62#ibcon#read 4, iclass 12, count 0 2006.257.11:23:09.62#ibcon#about to read 5, iclass 12, count 0 2006.257.11:23:09.62#ibcon#read 5, iclass 12, count 0 2006.257.11:23:09.62#ibcon#about to read 6, iclass 12, count 0 2006.257.11:23:09.62#ibcon#read 6, iclass 12, count 0 2006.257.11:23:09.62#ibcon#end of sib2, iclass 12, count 0 2006.257.11:23:09.62#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:23:09.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:23:09.62#ibcon#[27=BW32\r\n] 2006.257.11:23:09.62#ibcon#*before write, iclass 12, count 0 2006.257.11:23:09.62#ibcon#enter sib2, iclass 12, count 0 2006.257.11:23:09.62#ibcon#flushed, iclass 12, count 0 2006.257.11:23:09.62#ibcon#about to write, iclass 12, count 0 2006.257.11:23:09.62#ibcon#wrote, iclass 12, count 0 2006.257.11:23:09.62#ibcon#about to read 3, iclass 12, count 0 2006.257.11:23:09.65#ibcon#read 3, iclass 12, count 0 2006.257.11:23:09.65#ibcon#about to read 4, iclass 12, count 0 2006.257.11:23:09.65#ibcon#read 4, iclass 12, count 0 2006.257.11:23:09.65#ibcon#about to read 5, iclass 12, count 0 2006.257.11:23:09.65#ibcon#read 5, iclass 12, count 0 2006.257.11:23:09.65#ibcon#about to read 6, iclass 12, count 0 2006.257.11:23:09.65#ibcon#read 6, iclass 12, count 0 2006.257.11:23:09.65#ibcon#end of sib2, iclass 12, count 0 2006.257.11:23:09.65#ibcon#*after write, iclass 12, count 0 2006.257.11:23:09.65#ibcon#*before return 0, iclass 12, count 0 2006.257.11:23:09.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:23:09.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:23:09.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:23:09.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:23:09.65$setupk4/ifdk4 2006.257.11:23:09.65$ifdk4/lo= 2006.257.11:23:09.65$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:23:09.65$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:23:09.65$ifdk4/patch= 2006.257.11:23:09.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:23:09.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:23:09.65$setupk4/!*+20s 2006.257.11:23:16.06#abcon#<5=/14 1.2 2.6 18.28 971013.8\r\n> 2006.257.11:23:16.08#abcon#{5=INTERFACE CLEAR} 2006.257.11:23:16.14#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:23:22.13#trakl#Source acquired 2006.257.11:23:23.13#flagr#flagr/antenna,acquired 2006.257.11:23:24.16$setupk4/"tpicd 2006.257.11:23:24.16$setupk4/echo=off 2006.257.11:23:24.16$setupk4/xlog=off 2006.257.11:23:24.16:!2006.257.11:25:10 2006.257.11:25:10.00:preob 2006.257.11:25:10.14/onsource/TRACKING 2006.257.11:25:10.14:!2006.257.11:25:20 2006.257.11:25:20.00:"tape 2006.257.11:25:20.00:"st=record 2006.257.11:25:20.00:data_valid=on 2006.257.11:25:20.00:midob 2006.257.11:25:20.14/onsource/TRACKING 2006.257.11:25:20.14/wx/18.25,1013.8,97 2006.257.11:25:20.19/cable/+6.4781E-03 2006.257.11:25:21.28/va/01,08,usb,yes,31,33 2006.257.11:25:21.28/va/02,07,usb,yes,33,34 2006.257.11:25:21.28/va/03,08,usb,yes,30,31 2006.257.11:25:21.28/va/04,07,usb,yes,34,36 2006.257.11:25:21.28/va/05,04,usb,yes,31,31 2006.257.11:25:21.28/va/06,04,usb,yes,34,34 2006.257.11:25:21.28/va/07,04,usb,yes,35,35 2006.257.11:25:21.28/va/08,04,usb,yes,29,36 2006.257.11:25:21.51/valo/01,524.99,yes,locked 2006.257.11:25:21.51/valo/02,534.99,yes,locked 2006.257.11:25:21.51/valo/03,564.99,yes,locked 2006.257.11:25:21.51/valo/04,624.99,yes,locked 2006.257.11:25:21.51/valo/05,734.99,yes,locked 2006.257.11:25:21.51/valo/06,814.99,yes,locked 2006.257.11:25:21.51/valo/07,864.99,yes,locked 2006.257.11:25:21.51/valo/08,884.99,yes,locked 2006.257.11:25:22.60/vb/01,04,usb,yes,31,28 2006.257.11:25:22.60/vb/02,05,usb,yes,29,29 2006.257.11:25:22.60/vb/03,04,usb,yes,30,33 2006.257.11:25:22.60/vb/04,05,usb,yes,30,29 2006.257.11:25:22.60/vb/05,04,usb,yes,27,29 2006.257.11:25:22.60/vb/06,04,usb,yes,31,27 2006.257.11:25:22.60/vb/07,04,usb,yes,31,31 2006.257.11:25:22.60/vb/08,04,usb,yes,28,32 2006.257.11:25:22.83/vblo/01,629.99,yes,locked 2006.257.11:25:22.83/vblo/02,634.99,yes,locked 2006.257.11:25:22.83/vblo/03,649.99,yes,locked 2006.257.11:25:22.83/vblo/04,679.99,yes,locked 2006.257.11:25:22.83/vblo/05,709.99,yes,locked 2006.257.11:25:22.83/vblo/06,719.99,yes,locked 2006.257.11:25:22.83/vblo/07,734.99,yes,locked 2006.257.11:25:22.83/vblo/08,744.99,yes,locked 2006.257.11:25:22.98/vabw/8 2006.257.11:25:23.13/vbbw/8 2006.257.11:25:23.22/xfe/off,on,15.2 2006.257.11:25:23.59/ifatt/23,28,28,28 2006.257.11:25:24.08/fmout-gps/S +4.62E-07 2006.257.11:25:24.12:!2006.257.11:26:00 2006.257.11:26:00.00:data_valid=off 2006.257.11:26:00.00:"et 2006.257.11:26:00.00:!+3s 2006.257.11:26:03.01:"tape 2006.257.11:26:03.01:postob 2006.257.11:26:03.07/cable/+6.4812E-03 2006.257.11:26:03.07/wx/18.24,1013.8,97 2006.257.11:26:04.08/fmout-gps/S +4.61E-07 2006.257.11:26:04.08:scan_name=257-1127,jd0609,40 2006.257.11:26:04.08:source=1954-388,195800.00,-384506.4,2000.0,ccw 2006.257.11:26:05.14#flagr#flagr/antenna,new-source 2006.257.11:26:05.14:checkk5 2006.257.11:26:05.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:26:05.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:26:06.30/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:26:06.72/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:26:07.09/chk_obsdata//k5ts1/T2571125??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.11:26:07.50/chk_obsdata//k5ts2/T2571125??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.11:26:07.89/chk_obsdata//k5ts3/T2571125??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.11:26:08.28/chk_obsdata//k5ts4/T2571125??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.11:26:09.00/k5log//k5ts1_log_newline 2006.257.11:26:09.72/k5log//k5ts2_log_newline 2006.257.11:26:10.44/k5log//k5ts3_log_newline 2006.257.11:26:11.14/k5log//k5ts4_log_newline 2006.257.11:26:11.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:26:11.17:setupk4=1 2006.257.11:26:11.17$setupk4/echo=on 2006.257.11:26:11.17$setupk4/pcalon 2006.257.11:26:11.17$pcalon/"no phase cal control is implemented here 2006.257.11:26:11.17$setupk4/"tpicd=stop 2006.257.11:26:11.17$setupk4/"rec=synch_on 2006.257.11:26:11.17$setupk4/"rec_mode=128 2006.257.11:26:11.17$setupk4/!* 2006.257.11:26:11.17$setupk4/recpk4 2006.257.11:26:11.17$recpk4/recpatch= 2006.257.11:26:11.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:26:11.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:26:11.17$setupk4/vck44 2006.257.11:26:11.17$vck44/valo=1,524.99 2006.257.11:26:11.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.11:26:11.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.11:26:11.17#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:11.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:11.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:11.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:11.17#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:26:11.17#ibcon#first serial, iclass 6, count 0 2006.257.11:26:11.17#ibcon#enter sib2, iclass 6, count 0 2006.257.11:26:11.17#ibcon#flushed, iclass 6, count 0 2006.257.11:26:11.17#ibcon#about to write, iclass 6, count 0 2006.257.11:26:11.17#ibcon#wrote, iclass 6, count 0 2006.257.11:26:11.17#ibcon#about to read 3, iclass 6, count 0 2006.257.11:26:11.18#ibcon#read 3, iclass 6, count 0 2006.257.11:26:11.19#ibcon#about to read 4, iclass 6, count 0 2006.257.11:26:11.19#ibcon#read 4, iclass 6, count 0 2006.257.11:26:11.19#ibcon#about to read 5, iclass 6, count 0 2006.257.11:26:11.19#ibcon#read 5, iclass 6, count 0 2006.257.11:26:11.19#ibcon#about to read 6, iclass 6, count 0 2006.257.11:26:11.19#ibcon#read 6, iclass 6, count 0 2006.257.11:26:11.19#ibcon#end of sib2, iclass 6, count 0 2006.257.11:26:11.19#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:26:11.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:26:11.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:26:11.19#ibcon#*before write, iclass 6, count 0 2006.257.11:26:11.19#ibcon#enter sib2, iclass 6, count 0 2006.257.11:26:11.19#ibcon#flushed, iclass 6, count 0 2006.257.11:26:11.19#ibcon#about to write, iclass 6, count 0 2006.257.11:26:11.19#ibcon#wrote, iclass 6, count 0 2006.257.11:26:11.19#ibcon#about to read 3, iclass 6, count 0 2006.257.11:26:11.24#ibcon#read 3, iclass 6, count 0 2006.257.11:26:11.24#ibcon#about to read 4, iclass 6, count 0 2006.257.11:26:11.24#ibcon#read 4, iclass 6, count 0 2006.257.11:26:11.24#ibcon#about to read 5, iclass 6, count 0 2006.257.11:26:11.24#ibcon#read 5, iclass 6, count 0 2006.257.11:26:11.24#ibcon#about to read 6, iclass 6, count 0 2006.257.11:26:11.24#ibcon#read 6, iclass 6, count 0 2006.257.11:26:11.24#ibcon#end of sib2, iclass 6, count 0 2006.257.11:26:11.24#ibcon#*after write, iclass 6, count 0 2006.257.11:26:11.24#ibcon#*before return 0, iclass 6, count 0 2006.257.11:26:11.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:11.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:11.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:26:11.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:26:11.24$vck44/va=1,8 2006.257.11:26:11.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.11:26:11.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.11:26:11.24#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:11.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:11.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:11.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:11.24#ibcon#enter wrdev, iclass 10, count 2 2006.257.11:26:11.24#ibcon#first serial, iclass 10, count 2 2006.257.11:26:11.24#ibcon#enter sib2, iclass 10, count 2 2006.257.11:26:11.24#ibcon#flushed, iclass 10, count 2 2006.257.11:26:11.24#ibcon#about to write, iclass 10, count 2 2006.257.11:26:11.24#ibcon#wrote, iclass 10, count 2 2006.257.11:26:11.24#ibcon#about to read 3, iclass 10, count 2 2006.257.11:26:11.26#ibcon#read 3, iclass 10, count 2 2006.257.11:26:11.26#ibcon#about to read 4, iclass 10, count 2 2006.257.11:26:11.26#ibcon#read 4, iclass 10, count 2 2006.257.11:26:11.26#ibcon#about to read 5, iclass 10, count 2 2006.257.11:26:11.26#ibcon#read 5, iclass 10, count 2 2006.257.11:26:11.26#ibcon#about to read 6, iclass 10, count 2 2006.257.11:26:11.26#ibcon#read 6, iclass 10, count 2 2006.257.11:26:11.26#ibcon#end of sib2, iclass 10, count 2 2006.257.11:26:11.26#ibcon#*mode == 0, iclass 10, count 2 2006.257.11:26:11.26#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.11:26:11.26#ibcon#[25=AT01-08\r\n] 2006.257.11:26:11.26#ibcon#*before write, iclass 10, count 2 2006.257.11:26:11.26#ibcon#enter sib2, iclass 10, count 2 2006.257.11:26:11.26#ibcon#flushed, iclass 10, count 2 2006.257.11:26:11.26#ibcon#about to write, iclass 10, count 2 2006.257.11:26:11.26#ibcon#wrote, iclass 10, count 2 2006.257.11:26:11.26#ibcon#about to read 3, iclass 10, count 2 2006.257.11:26:11.28#ibcon#read 3, iclass 10, count 2 2006.257.11:26:11.29#ibcon#about to read 4, iclass 10, count 2 2006.257.11:26:11.29#ibcon#read 4, iclass 10, count 2 2006.257.11:26:11.29#ibcon#about to read 5, iclass 10, count 2 2006.257.11:26:11.29#ibcon#read 5, iclass 10, count 2 2006.257.11:26:11.29#ibcon#about to read 6, iclass 10, count 2 2006.257.11:26:11.29#ibcon#read 6, iclass 10, count 2 2006.257.11:26:11.29#ibcon#end of sib2, iclass 10, count 2 2006.257.11:26:11.29#ibcon#*after write, iclass 10, count 2 2006.257.11:26:11.29#ibcon#*before return 0, iclass 10, count 2 2006.257.11:26:11.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:11.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:11.29#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.11:26:11.29#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:11.29#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:11.41#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:11.41#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:11.41#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:26:11.41#ibcon#first serial, iclass 10, count 0 2006.257.11:26:11.41#ibcon#enter sib2, iclass 10, count 0 2006.257.11:26:11.41#ibcon#flushed, iclass 10, count 0 2006.257.11:26:11.41#ibcon#about to write, iclass 10, count 0 2006.257.11:26:11.41#ibcon#wrote, iclass 10, count 0 2006.257.11:26:11.41#ibcon#about to read 3, iclass 10, count 0 2006.257.11:26:11.42#ibcon#read 3, iclass 10, count 0 2006.257.11:26:11.43#ibcon#about to read 4, iclass 10, count 0 2006.257.11:26:11.43#ibcon#read 4, iclass 10, count 0 2006.257.11:26:11.43#ibcon#about to read 5, iclass 10, count 0 2006.257.11:26:11.43#ibcon#read 5, iclass 10, count 0 2006.257.11:26:11.43#ibcon#about to read 6, iclass 10, count 0 2006.257.11:26:11.43#ibcon#read 6, iclass 10, count 0 2006.257.11:26:11.43#ibcon#end of sib2, iclass 10, count 0 2006.257.11:26:11.43#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:26:11.43#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:26:11.43#ibcon#[25=USB\r\n] 2006.257.11:26:11.43#ibcon#*before write, iclass 10, count 0 2006.257.11:26:11.43#ibcon#enter sib2, iclass 10, count 0 2006.257.11:26:11.43#ibcon#flushed, iclass 10, count 0 2006.257.11:26:11.43#ibcon#about to write, iclass 10, count 0 2006.257.11:26:11.43#ibcon#wrote, iclass 10, count 0 2006.257.11:26:11.43#ibcon#about to read 3, iclass 10, count 0 2006.257.11:26:11.45#ibcon#read 3, iclass 10, count 0 2006.257.11:26:11.46#ibcon#about to read 4, iclass 10, count 0 2006.257.11:26:11.46#ibcon#read 4, iclass 10, count 0 2006.257.11:26:11.46#ibcon#about to read 5, iclass 10, count 0 2006.257.11:26:11.46#ibcon#read 5, iclass 10, count 0 2006.257.11:26:11.46#ibcon#about to read 6, iclass 10, count 0 2006.257.11:26:11.46#ibcon#read 6, iclass 10, count 0 2006.257.11:26:11.46#ibcon#end of sib2, iclass 10, count 0 2006.257.11:26:11.46#ibcon#*after write, iclass 10, count 0 2006.257.11:26:11.46#ibcon#*before return 0, iclass 10, count 0 2006.257.11:26:11.46#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:11.46#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:11.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:26:11.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:26:11.46$vck44/valo=2,534.99 2006.257.11:26:11.46#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.11:26:11.46#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.11:26:11.46#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:11.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:11.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:11.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:11.46#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:26:11.46#ibcon#first serial, iclass 12, count 0 2006.257.11:26:11.46#ibcon#enter sib2, iclass 12, count 0 2006.257.11:26:11.46#ibcon#flushed, iclass 12, count 0 2006.257.11:26:11.46#ibcon#about to write, iclass 12, count 0 2006.257.11:26:11.46#ibcon#wrote, iclass 12, count 0 2006.257.11:26:11.46#ibcon#about to read 3, iclass 12, count 0 2006.257.11:26:11.47#ibcon#read 3, iclass 12, count 0 2006.257.11:26:11.48#ibcon#about to read 4, iclass 12, count 0 2006.257.11:26:11.48#ibcon#read 4, iclass 12, count 0 2006.257.11:26:11.48#ibcon#about to read 5, iclass 12, count 0 2006.257.11:26:11.48#ibcon#read 5, iclass 12, count 0 2006.257.11:26:11.48#ibcon#about to read 6, iclass 12, count 0 2006.257.11:26:11.48#ibcon#read 6, iclass 12, count 0 2006.257.11:26:11.48#ibcon#end of sib2, iclass 12, count 0 2006.257.11:26:11.48#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:26:11.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:26:11.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:26:11.48#ibcon#*before write, iclass 12, count 0 2006.257.11:26:11.48#ibcon#enter sib2, iclass 12, count 0 2006.257.11:26:11.48#ibcon#flushed, iclass 12, count 0 2006.257.11:26:11.48#ibcon#about to write, iclass 12, count 0 2006.257.11:26:11.48#ibcon#wrote, iclass 12, count 0 2006.257.11:26:11.48#ibcon#about to read 3, iclass 12, count 0 2006.257.11:26:11.51#ibcon#read 3, iclass 12, count 0 2006.257.11:26:11.52#ibcon#about to read 4, iclass 12, count 0 2006.257.11:26:11.52#ibcon#read 4, iclass 12, count 0 2006.257.11:26:11.52#ibcon#about to read 5, iclass 12, count 0 2006.257.11:26:11.52#ibcon#read 5, iclass 12, count 0 2006.257.11:26:11.52#ibcon#about to read 6, iclass 12, count 0 2006.257.11:26:11.52#ibcon#read 6, iclass 12, count 0 2006.257.11:26:11.52#ibcon#end of sib2, iclass 12, count 0 2006.257.11:26:11.52#ibcon#*after write, iclass 12, count 0 2006.257.11:26:11.52#ibcon#*before return 0, iclass 12, count 0 2006.257.11:26:11.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:11.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:11.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:26:11.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:26:11.52$vck44/va=2,7 2006.257.11:26:11.52#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.11:26:11.52#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.11:26:11.52#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:11.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:11.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:11.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:11.58#ibcon#enter wrdev, iclass 14, count 2 2006.257.11:26:11.58#ibcon#first serial, iclass 14, count 2 2006.257.11:26:11.58#ibcon#enter sib2, iclass 14, count 2 2006.257.11:26:11.58#ibcon#flushed, iclass 14, count 2 2006.257.11:26:11.58#ibcon#about to write, iclass 14, count 2 2006.257.11:26:11.58#ibcon#wrote, iclass 14, count 2 2006.257.11:26:11.58#ibcon#about to read 3, iclass 14, count 2 2006.257.11:26:11.59#ibcon#read 3, iclass 14, count 2 2006.257.11:26:11.60#ibcon#about to read 4, iclass 14, count 2 2006.257.11:26:11.60#ibcon#read 4, iclass 14, count 2 2006.257.11:26:11.60#ibcon#about to read 5, iclass 14, count 2 2006.257.11:26:11.60#ibcon#read 5, iclass 14, count 2 2006.257.11:26:11.60#ibcon#about to read 6, iclass 14, count 2 2006.257.11:26:11.60#ibcon#read 6, iclass 14, count 2 2006.257.11:26:11.60#ibcon#end of sib2, iclass 14, count 2 2006.257.11:26:11.60#ibcon#*mode == 0, iclass 14, count 2 2006.257.11:26:11.60#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.11:26:11.60#ibcon#[25=AT02-07\r\n] 2006.257.11:26:11.60#ibcon#*before write, iclass 14, count 2 2006.257.11:26:11.60#ibcon#enter sib2, iclass 14, count 2 2006.257.11:26:11.60#ibcon#flushed, iclass 14, count 2 2006.257.11:26:11.60#ibcon#about to write, iclass 14, count 2 2006.257.11:26:11.60#ibcon#wrote, iclass 14, count 2 2006.257.11:26:11.60#ibcon#about to read 3, iclass 14, count 2 2006.257.11:26:11.62#ibcon#read 3, iclass 14, count 2 2006.257.11:26:11.63#ibcon#about to read 4, iclass 14, count 2 2006.257.11:26:11.63#ibcon#read 4, iclass 14, count 2 2006.257.11:26:11.63#ibcon#about to read 5, iclass 14, count 2 2006.257.11:26:11.63#ibcon#read 5, iclass 14, count 2 2006.257.11:26:11.63#ibcon#about to read 6, iclass 14, count 2 2006.257.11:26:11.63#ibcon#read 6, iclass 14, count 2 2006.257.11:26:11.63#ibcon#end of sib2, iclass 14, count 2 2006.257.11:26:11.63#ibcon#*after write, iclass 14, count 2 2006.257.11:26:11.63#ibcon#*before return 0, iclass 14, count 2 2006.257.11:26:11.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:11.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:11.63#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.11:26:11.63#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:11.63#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:11.75#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:11.75#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:11.75#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:26:11.75#ibcon#first serial, iclass 14, count 0 2006.257.11:26:11.75#ibcon#enter sib2, iclass 14, count 0 2006.257.11:26:11.75#ibcon#flushed, iclass 14, count 0 2006.257.11:26:11.75#ibcon#about to write, iclass 14, count 0 2006.257.11:26:11.75#ibcon#wrote, iclass 14, count 0 2006.257.11:26:11.75#ibcon#about to read 3, iclass 14, count 0 2006.257.11:26:11.76#ibcon#read 3, iclass 14, count 0 2006.257.11:26:11.77#ibcon#about to read 4, iclass 14, count 0 2006.257.11:26:11.77#ibcon#read 4, iclass 14, count 0 2006.257.11:26:11.77#ibcon#about to read 5, iclass 14, count 0 2006.257.11:26:11.77#ibcon#read 5, iclass 14, count 0 2006.257.11:26:11.77#ibcon#about to read 6, iclass 14, count 0 2006.257.11:26:11.77#ibcon#read 6, iclass 14, count 0 2006.257.11:26:11.77#ibcon#end of sib2, iclass 14, count 0 2006.257.11:26:11.77#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:26:11.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:26:11.77#ibcon#[25=USB\r\n] 2006.257.11:26:11.77#ibcon#*before write, iclass 14, count 0 2006.257.11:26:11.77#ibcon#enter sib2, iclass 14, count 0 2006.257.11:26:11.77#ibcon#flushed, iclass 14, count 0 2006.257.11:26:11.77#ibcon#about to write, iclass 14, count 0 2006.257.11:26:11.77#ibcon#wrote, iclass 14, count 0 2006.257.11:26:11.77#ibcon#about to read 3, iclass 14, count 0 2006.257.11:26:11.78#abcon#<5=/14 1.1 2.5 18.23 971013.9\r\n> 2006.257.11:26:11.79#abcon#{5=INTERFACE CLEAR} 2006.257.11:26:11.80#ibcon#read 3, iclass 14, count 0 2006.257.11:26:11.80#ibcon#about to read 4, iclass 14, count 0 2006.257.11:26:11.80#ibcon#read 4, iclass 14, count 0 2006.257.11:26:11.80#ibcon#about to read 5, iclass 14, count 0 2006.257.11:26:11.80#ibcon#read 5, iclass 14, count 0 2006.257.11:26:11.80#ibcon#about to read 6, iclass 14, count 0 2006.257.11:26:11.80#ibcon#read 6, iclass 14, count 0 2006.257.11:26:11.80#ibcon#end of sib2, iclass 14, count 0 2006.257.11:26:11.80#ibcon#*after write, iclass 14, count 0 2006.257.11:26:11.80#ibcon#*before return 0, iclass 14, count 0 2006.257.11:26:11.80#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:11.80#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:11.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:26:11.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:26:11.80$vck44/valo=3,564.99 2006.257.11:26:11.80#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.11:26:11.80#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.11:26:11.80#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:11.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:26:11.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:26:11.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:26:11.80#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:26:11.80#ibcon#first serial, iclass 19, count 0 2006.257.11:26:11.80#ibcon#enter sib2, iclass 19, count 0 2006.257.11:26:11.80#ibcon#flushed, iclass 19, count 0 2006.257.11:26:11.80#ibcon#about to write, iclass 19, count 0 2006.257.11:26:11.80#ibcon#wrote, iclass 19, count 0 2006.257.11:26:11.80#ibcon#about to read 3, iclass 19, count 0 2006.257.11:26:11.81#ibcon#read 3, iclass 19, count 0 2006.257.11:26:11.82#ibcon#about to read 4, iclass 19, count 0 2006.257.11:26:11.82#ibcon#read 4, iclass 19, count 0 2006.257.11:26:11.82#ibcon#about to read 5, iclass 19, count 0 2006.257.11:26:11.82#ibcon#read 5, iclass 19, count 0 2006.257.11:26:11.82#ibcon#about to read 6, iclass 19, count 0 2006.257.11:26:11.82#ibcon#read 6, iclass 19, count 0 2006.257.11:26:11.82#ibcon#end of sib2, iclass 19, count 0 2006.257.11:26:11.82#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:26:11.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:26:11.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:26:11.82#ibcon#*before write, iclass 19, count 0 2006.257.11:26:11.82#ibcon#enter sib2, iclass 19, count 0 2006.257.11:26:11.82#ibcon#flushed, iclass 19, count 0 2006.257.11:26:11.82#ibcon#about to write, iclass 19, count 0 2006.257.11:26:11.82#ibcon#wrote, iclass 19, count 0 2006.257.11:26:11.82#ibcon#about to read 3, iclass 19, count 0 2006.257.11:26:11.86#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:26:11.86#ibcon#read 3, iclass 19, count 0 2006.257.11:26:11.86#ibcon#about to read 4, iclass 19, count 0 2006.257.11:26:11.86#ibcon#read 4, iclass 19, count 0 2006.257.11:26:11.86#ibcon#about to read 5, iclass 19, count 0 2006.257.11:26:11.86#ibcon#read 5, iclass 19, count 0 2006.257.11:26:11.86#ibcon#about to read 6, iclass 19, count 0 2006.257.11:26:11.86#ibcon#read 6, iclass 19, count 0 2006.257.11:26:11.86#ibcon#end of sib2, iclass 19, count 0 2006.257.11:26:11.86#ibcon#*after write, iclass 19, count 0 2006.257.11:26:11.86#ibcon#*before return 0, iclass 19, count 0 2006.257.11:26:11.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:26:11.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:26:11.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:26:11.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:26:11.86$vck44/va=3,8 2006.257.11:26:11.86#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.11:26:11.86#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.11:26:11.86#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:11.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:11.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:11.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:11.92#ibcon#enter wrdev, iclass 22, count 2 2006.257.11:26:11.92#ibcon#first serial, iclass 22, count 2 2006.257.11:26:11.92#ibcon#enter sib2, iclass 22, count 2 2006.257.11:26:11.92#ibcon#flushed, iclass 22, count 2 2006.257.11:26:11.92#ibcon#about to write, iclass 22, count 2 2006.257.11:26:11.92#ibcon#wrote, iclass 22, count 2 2006.257.11:26:11.92#ibcon#about to read 3, iclass 22, count 2 2006.257.11:26:11.93#ibcon#read 3, iclass 22, count 2 2006.257.11:26:11.94#ibcon#about to read 4, iclass 22, count 2 2006.257.11:26:11.94#ibcon#read 4, iclass 22, count 2 2006.257.11:26:11.94#ibcon#about to read 5, iclass 22, count 2 2006.257.11:26:11.94#ibcon#read 5, iclass 22, count 2 2006.257.11:26:11.94#ibcon#about to read 6, iclass 22, count 2 2006.257.11:26:11.94#ibcon#read 6, iclass 22, count 2 2006.257.11:26:11.94#ibcon#end of sib2, iclass 22, count 2 2006.257.11:26:11.94#ibcon#*mode == 0, iclass 22, count 2 2006.257.11:26:11.94#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.11:26:11.94#ibcon#[25=AT03-08\r\n] 2006.257.11:26:11.94#ibcon#*before write, iclass 22, count 2 2006.257.11:26:11.94#ibcon#enter sib2, iclass 22, count 2 2006.257.11:26:11.94#ibcon#flushed, iclass 22, count 2 2006.257.11:26:11.94#ibcon#about to write, iclass 22, count 2 2006.257.11:26:11.94#ibcon#wrote, iclass 22, count 2 2006.257.11:26:11.94#ibcon#about to read 3, iclass 22, count 2 2006.257.11:26:11.96#ibcon#read 3, iclass 22, count 2 2006.257.11:26:11.97#ibcon#about to read 4, iclass 22, count 2 2006.257.11:26:11.97#ibcon#read 4, iclass 22, count 2 2006.257.11:26:11.97#ibcon#about to read 5, iclass 22, count 2 2006.257.11:26:11.97#ibcon#read 5, iclass 22, count 2 2006.257.11:26:11.97#ibcon#about to read 6, iclass 22, count 2 2006.257.11:26:11.97#ibcon#read 6, iclass 22, count 2 2006.257.11:26:11.97#ibcon#end of sib2, iclass 22, count 2 2006.257.11:26:11.97#ibcon#*after write, iclass 22, count 2 2006.257.11:26:11.97#ibcon#*before return 0, iclass 22, count 2 2006.257.11:26:11.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:11.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:11.97#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.11:26:11.97#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:11.97#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:12.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:12.09#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:12.09#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:26:12.09#ibcon#first serial, iclass 22, count 0 2006.257.11:26:12.09#ibcon#enter sib2, iclass 22, count 0 2006.257.11:26:12.09#ibcon#flushed, iclass 22, count 0 2006.257.11:26:12.09#ibcon#about to write, iclass 22, count 0 2006.257.11:26:12.09#ibcon#wrote, iclass 22, count 0 2006.257.11:26:12.09#ibcon#about to read 3, iclass 22, count 0 2006.257.11:26:12.10#ibcon#read 3, iclass 22, count 0 2006.257.11:26:12.11#ibcon#about to read 4, iclass 22, count 0 2006.257.11:26:12.11#ibcon#read 4, iclass 22, count 0 2006.257.11:26:12.11#ibcon#about to read 5, iclass 22, count 0 2006.257.11:26:12.11#ibcon#read 5, iclass 22, count 0 2006.257.11:26:12.11#ibcon#about to read 6, iclass 22, count 0 2006.257.11:26:12.11#ibcon#read 6, iclass 22, count 0 2006.257.11:26:12.11#ibcon#end of sib2, iclass 22, count 0 2006.257.11:26:12.11#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:26:12.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:26:12.11#ibcon#[25=USB\r\n] 2006.257.11:26:12.11#ibcon#*before write, iclass 22, count 0 2006.257.11:26:12.11#ibcon#enter sib2, iclass 22, count 0 2006.257.11:26:12.11#ibcon#flushed, iclass 22, count 0 2006.257.11:26:12.11#ibcon#about to write, iclass 22, count 0 2006.257.11:26:12.11#ibcon#wrote, iclass 22, count 0 2006.257.11:26:12.11#ibcon#about to read 3, iclass 22, count 0 2006.257.11:26:12.13#ibcon#read 3, iclass 22, count 0 2006.257.11:26:12.14#ibcon#about to read 4, iclass 22, count 0 2006.257.11:26:12.14#ibcon#read 4, iclass 22, count 0 2006.257.11:26:12.14#ibcon#about to read 5, iclass 22, count 0 2006.257.11:26:12.14#ibcon#read 5, iclass 22, count 0 2006.257.11:26:12.14#ibcon#about to read 6, iclass 22, count 0 2006.257.11:26:12.14#ibcon#read 6, iclass 22, count 0 2006.257.11:26:12.14#ibcon#end of sib2, iclass 22, count 0 2006.257.11:26:12.14#ibcon#*after write, iclass 22, count 0 2006.257.11:26:12.14#ibcon#*before return 0, iclass 22, count 0 2006.257.11:26:12.14#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:12.14#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:12.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:26:12.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:26:12.14$vck44/valo=4,624.99 2006.257.11:26:12.14#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.11:26:12.14#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.11:26:12.14#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:12.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:12.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:12.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:12.14#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:26:12.14#ibcon#first serial, iclass 24, count 0 2006.257.11:26:12.14#ibcon#enter sib2, iclass 24, count 0 2006.257.11:26:12.14#ibcon#flushed, iclass 24, count 0 2006.257.11:26:12.14#ibcon#about to write, iclass 24, count 0 2006.257.11:26:12.14#ibcon#wrote, iclass 24, count 0 2006.257.11:26:12.14#ibcon#about to read 3, iclass 24, count 0 2006.257.11:26:12.15#ibcon#read 3, iclass 24, count 0 2006.257.11:26:12.16#ibcon#about to read 4, iclass 24, count 0 2006.257.11:26:12.16#ibcon#read 4, iclass 24, count 0 2006.257.11:26:12.16#ibcon#about to read 5, iclass 24, count 0 2006.257.11:26:12.16#ibcon#read 5, iclass 24, count 0 2006.257.11:26:12.16#ibcon#about to read 6, iclass 24, count 0 2006.257.11:26:12.16#ibcon#read 6, iclass 24, count 0 2006.257.11:26:12.16#ibcon#end of sib2, iclass 24, count 0 2006.257.11:26:12.16#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:26:12.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:26:12.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:26:12.16#ibcon#*before write, iclass 24, count 0 2006.257.11:26:12.16#ibcon#enter sib2, iclass 24, count 0 2006.257.11:26:12.16#ibcon#flushed, iclass 24, count 0 2006.257.11:26:12.16#ibcon#about to write, iclass 24, count 0 2006.257.11:26:12.16#ibcon#wrote, iclass 24, count 0 2006.257.11:26:12.16#ibcon#about to read 3, iclass 24, count 0 2006.257.11:26:12.19#ibcon#read 3, iclass 24, count 0 2006.257.11:26:12.20#ibcon#about to read 4, iclass 24, count 0 2006.257.11:26:12.20#ibcon#read 4, iclass 24, count 0 2006.257.11:26:12.20#ibcon#about to read 5, iclass 24, count 0 2006.257.11:26:12.20#ibcon#read 5, iclass 24, count 0 2006.257.11:26:12.20#ibcon#about to read 6, iclass 24, count 0 2006.257.11:26:12.20#ibcon#read 6, iclass 24, count 0 2006.257.11:26:12.20#ibcon#end of sib2, iclass 24, count 0 2006.257.11:26:12.20#ibcon#*after write, iclass 24, count 0 2006.257.11:26:12.20#ibcon#*before return 0, iclass 24, count 0 2006.257.11:26:12.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:12.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:12.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:26:12.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:26:12.20$vck44/va=4,7 2006.257.11:26:12.20#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.11:26:12.20#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.11:26:12.20#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:12.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:12.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:12.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:12.26#ibcon#enter wrdev, iclass 26, count 2 2006.257.11:26:12.26#ibcon#first serial, iclass 26, count 2 2006.257.11:26:12.26#ibcon#enter sib2, iclass 26, count 2 2006.257.11:26:12.26#ibcon#flushed, iclass 26, count 2 2006.257.11:26:12.26#ibcon#about to write, iclass 26, count 2 2006.257.11:26:12.26#ibcon#wrote, iclass 26, count 2 2006.257.11:26:12.26#ibcon#about to read 3, iclass 26, count 2 2006.257.11:26:12.27#ibcon#read 3, iclass 26, count 2 2006.257.11:26:12.28#ibcon#about to read 4, iclass 26, count 2 2006.257.11:26:12.28#ibcon#read 4, iclass 26, count 2 2006.257.11:26:12.28#ibcon#about to read 5, iclass 26, count 2 2006.257.11:26:12.28#ibcon#read 5, iclass 26, count 2 2006.257.11:26:12.28#ibcon#about to read 6, iclass 26, count 2 2006.257.11:26:12.28#ibcon#read 6, iclass 26, count 2 2006.257.11:26:12.28#ibcon#end of sib2, iclass 26, count 2 2006.257.11:26:12.28#ibcon#*mode == 0, iclass 26, count 2 2006.257.11:26:12.28#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.11:26:12.28#ibcon#[25=AT04-07\r\n] 2006.257.11:26:12.28#ibcon#*before write, iclass 26, count 2 2006.257.11:26:12.28#ibcon#enter sib2, iclass 26, count 2 2006.257.11:26:12.28#ibcon#flushed, iclass 26, count 2 2006.257.11:26:12.28#ibcon#about to write, iclass 26, count 2 2006.257.11:26:12.28#ibcon#wrote, iclass 26, count 2 2006.257.11:26:12.28#ibcon#about to read 3, iclass 26, count 2 2006.257.11:26:12.30#ibcon#read 3, iclass 26, count 2 2006.257.11:26:12.31#ibcon#about to read 4, iclass 26, count 2 2006.257.11:26:12.31#ibcon#read 4, iclass 26, count 2 2006.257.11:26:12.31#ibcon#about to read 5, iclass 26, count 2 2006.257.11:26:12.31#ibcon#read 5, iclass 26, count 2 2006.257.11:26:12.31#ibcon#about to read 6, iclass 26, count 2 2006.257.11:26:12.31#ibcon#read 6, iclass 26, count 2 2006.257.11:26:12.31#ibcon#end of sib2, iclass 26, count 2 2006.257.11:26:12.31#ibcon#*after write, iclass 26, count 2 2006.257.11:26:12.31#ibcon#*before return 0, iclass 26, count 2 2006.257.11:26:12.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:12.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:12.31#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.11:26:12.31#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:12.31#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:12.42#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:12.43#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:12.43#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:26:12.43#ibcon#first serial, iclass 26, count 0 2006.257.11:26:12.43#ibcon#enter sib2, iclass 26, count 0 2006.257.11:26:12.43#ibcon#flushed, iclass 26, count 0 2006.257.11:26:12.43#ibcon#about to write, iclass 26, count 0 2006.257.11:26:12.43#ibcon#wrote, iclass 26, count 0 2006.257.11:26:12.43#ibcon#about to read 3, iclass 26, count 0 2006.257.11:26:12.44#ibcon#read 3, iclass 26, count 0 2006.257.11:26:12.45#ibcon#about to read 4, iclass 26, count 0 2006.257.11:26:12.45#ibcon#read 4, iclass 26, count 0 2006.257.11:26:12.45#ibcon#about to read 5, iclass 26, count 0 2006.257.11:26:12.45#ibcon#read 5, iclass 26, count 0 2006.257.11:26:12.45#ibcon#about to read 6, iclass 26, count 0 2006.257.11:26:12.45#ibcon#read 6, iclass 26, count 0 2006.257.11:26:12.45#ibcon#end of sib2, iclass 26, count 0 2006.257.11:26:12.45#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:26:12.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:26:12.45#ibcon#[25=USB\r\n] 2006.257.11:26:12.45#ibcon#*before write, iclass 26, count 0 2006.257.11:26:12.45#ibcon#enter sib2, iclass 26, count 0 2006.257.11:26:12.45#ibcon#flushed, iclass 26, count 0 2006.257.11:26:12.45#ibcon#about to write, iclass 26, count 0 2006.257.11:26:12.45#ibcon#wrote, iclass 26, count 0 2006.257.11:26:12.45#ibcon#about to read 3, iclass 26, count 0 2006.257.11:26:12.47#ibcon#read 3, iclass 26, count 0 2006.257.11:26:12.48#ibcon#about to read 4, iclass 26, count 0 2006.257.11:26:12.48#ibcon#read 4, iclass 26, count 0 2006.257.11:26:12.48#ibcon#about to read 5, iclass 26, count 0 2006.257.11:26:12.48#ibcon#read 5, iclass 26, count 0 2006.257.11:26:12.48#ibcon#about to read 6, iclass 26, count 0 2006.257.11:26:12.48#ibcon#read 6, iclass 26, count 0 2006.257.11:26:12.48#ibcon#end of sib2, iclass 26, count 0 2006.257.11:26:12.48#ibcon#*after write, iclass 26, count 0 2006.257.11:26:12.48#ibcon#*before return 0, iclass 26, count 0 2006.257.11:26:12.48#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:12.48#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:12.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:26:12.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:26:12.48$vck44/valo=5,734.99 2006.257.11:26:12.48#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.11:26:12.48#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.11:26:12.48#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:12.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:12.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:12.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:12.48#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:26:12.48#ibcon#first serial, iclass 28, count 0 2006.257.11:26:12.48#ibcon#enter sib2, iclass 28, count 0 2006.257.11:26:12.48#ibcon#flushed, iclass 28, count 0 2006.257.11:26:12.48#ibcon#about to write, iclass 28, count 0 2006.257.11:26:12.48#ibcon#wrote, iclass 28, count 0 2006.257.11:26:12.48#ibcon#about to read 3, iclass 28, count 0 2006.257.11:26:12.49#ibcon#read 3, iclass 28, count 0 2006.257.11:26:12.50#ibcon#about to read 4, iclass 28, count 0 2006.257.11:26:12.50#ibcon#read 4, iclass 28, count 0 2006.257.11:26:12.50#ibcon#about to read 5, iclass 28, count 0 2006.257.11:26:12.50#ibcon#read 5, iclass 28, count 0 2006.257.11:26:12.50#ibcon#about to read 6, iclass 28, count 0 2006.257.11:26:12.50#ibcon#read 6, iclass 28, count 0 2006.257.11:26:12.50#ibcon#end of sib2, iclass 28, count 0 2006.257.11:26:12.50#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:26:12.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:26:12.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:26:12.50#ibcon#*before write, iclass 28, count 0 2006.257.11:26:12.50#ibcon#enter sib2, iclass 28, count 0 2006.257.11:26:12.50#ibcon#flushed, iclass 28, count 0 2006.257.11:26:12.50#ibcon#about to write, iclass 28, count 0 2006.257.11:26:12.50#ibcon#wrote, iclass 28, count 0 2006.257.11:26:12.50#ibcon#about to read 3, iclass 28, count 0 2006.257.11:26:12.53#ibcon#read 3, iclass 28, count 0 2006.257.11:26:12.54#ibcon#about to read 4, iclass 28, count 0 2006.257.11:26:12.54#ibcon#read 4, iclass 28, count 0 2006.257.11:26:12.54#ibcon#about to read 5, iclass 28, count 0 2006.257.11:26:12.54#ibcon#read 5, iclass 28, count 0 2006.257.11:26:12.54#ibcon#about to read 6, iclass 28, count 0 2006.257.11:26:12.54#ibcon#read 6, iclass 28, count 0 2006.257.11:26:12.54#ibcon#end of sib2, iclass 28, count 0 2006.257.11:26:12.54#ibcon#*after write, iclass 28, count 0 2006.257.11:26:12.54#ibcon#*before return 0, iclass 28, count 0 2006.257.11:26:12.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:12.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:12.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:26:12.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:26:12.54$vck44/va=5,4 2006.257.11:26:12.54#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.11:26:12.54#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.11:26:12.54#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:12.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:12.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:12.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:12.60#ibcon#enter wrdev, iclass 30, count 2 2006.257.11:26:12.60#ibcon#first serial, iclass 30, count 2 2006.257.11:26:12.60#ibcon#enter sib2, iclass 30, count 2 2006.257.11:26:12.60#ibcon#flushed, iclass 30, count 2 2006.257.11:26:12.60#ibcon#about to write, iclass 30, count 2 2006.257.11:26:12.60#ibcon#wrote, iclass 30, count 2 2006.257.11:26:12.60#ibcon#about to read 3, iclass 30, count 2 2006.257.11:26:12.61#ibcon#read 3, iclass 30, count 2 2006.257.11:26:12.62#ibcon#about to read 4, iclass 30, count 2 2006.257.11:26:12.62#ibcon#read 4, iclass 30, count 2 2006.257.11:26:12.62#ibcon#about to read 5, iclass 30, count 2 2006.257.11:26:12.62#ibcon#read 5, iclass 30, count 2 2006.257.11:26:12.62#ibcon#about to read 6, iclass 30, count 2 2006.257.11:26:12.62#ibcon#read 6, iclass 30, count 2 2006.257.11:26:12.62#ibcon#end of sib2, iclass 30, count 2 2006.257.11:26:12.62#ibcon#*mode == 0, iclass 30, count 2 2006.257.11:26:12.62#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.11:26:12.62#ibcon#[25=AT05-04\r\n] 2006.257.11:26:12.62#ibcon#*before write, iclass 30, count 2 2006.257.11:26:12.62#ibcon#enter sib2, iclass 30, count 2 2006.257.11:26:12.62#ibcon#flushed, iclass 30, count 2 2006.257.11:26:12.62#ibcon#about to write, iclass 30, count 2 2006.257.11:26:12.62#ibcon#wrote, iclass 30, count 2 2006.257.11:26:12.62#ibcon#about to read 3, iclass 30, count 2 2006.257.11:26:12.64#ibcon#read 3, iclass 30, count 2 2006.257.11:26:12.65#ibcon#about to read 4, iclass 30, count 2 2006.257.11:26:12.65#ibcon#read 4, iclass 30, count 2 2006.257.11:26:12.65#ibcon#about to read 5, iclass 30, count 2 2006.257.11:26:12.65#ibcon#read 5, iclass 30, count 2 2006.257.11:26:12.65#ibcon#about to read 6, iclass 30, count 2 2006.257.11:26:12.65#ibcon#read 6, iclass 30, count 2 2006.257.11:26:12.65#ibcon#end of sib2, iclass 30, count 2 2006.257.11:26:12.65#ibcon#*after write, iclass 30, count 2 2006.257.11:26:12.65#ibcon#*before return 0, iclass 30, count 2 2006.257.11:26:12.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:12.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:12.65#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.11:26:12.65#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:12.65#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:12.76#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:12.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:12.77#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:26:12.77#ibcon#first serial, iclass 30, count 0 2006.257.11:26:12.77#ibcon#enter sib2, iclass 30, count 0 2006.257.11:26:12.77#ibcon#flushed, iclass 30, count 0 2006.257.11:26:12.77#ibcon#about to write, iclass 30, count 0 2006.257.11:26:12.77#ibcon#wrote, iclass 30, count 0 2006.257.11:26:12.77#ibcon#about to read 3, iclass 30, count 0 2006.257.11:26:12.78#ibcon#read 3, iclass 30, count 0 2006.257.11:26:12.79#ibcon#about to read 4, iclass 30, count 0 2006.257.11:26:12.79#ibcon#read 4, iclass 30, count 0 2006.257.11:26:12.79#ibcon#about to read 5, iclass 30, count 0 2006.257.11:26:12.79#ibcon#read 5, iclass 30, count 0 2006.257.11:26:12.79#ibcon#about to read 6, iclass 30, count 0 2006.257.11:26:12.79#ibcon#read 6, iclass 30, count 0 2006.257.11:26:12.79#ibcon#end of sib2, iclass 30, count 0 2006.257.11:26:12.79#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:26:12.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:26:12.79#ibcon#[25=USB\r\n] 2006.257.11:26:12.79#ibcon#*before write, iclass 30, count 0 2006.257.11:26:12.79#ibcon#enter sib2, iclass 30, count 0 2006.257.11:26:12.79#ibcon#flushed, iclass 30, count 0 2006.257.11:26:12.79#ibcon#about to write, iclass 30, count 0 2006.257.11:26:12.79#ibcon#wrote, iclass 30, count 0 2006.257.11:26:12.79#ibcon#about to read 3, iclass 30, count 0 2006.257.11:26:12.81#ibcon#read 3, iclass 30, count 0 2006.257.11:26:12.81#ibcon#about to read 4, iclass 30, count 0 2006.257.11:26:12.82#ibcon#read 4, iclass 30, count 0 2006.257.11:26:12.82#ibcon#about to read 5, iclass 30, count 0 2006.257.11:26:12.82#ibcon#read 5, iclass 30, count 0 2006.257.11:26:12.82#ibcon#about to read 6, iclass 30, count 0 2006.257.11:26:12.82#ibcon#read 6, iclass 30, count 0 2006.257.11:26:12.82#ibcon#end of sib2, iclass 30, count 0 2006.257.11:26:12.82#ibcon#*after write, iclass 30, count 0 2006.257.11:26:12.82#ibcon#*before return 0, iclass 30, count 0 2006.257.11:26:12.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:12.82#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:12.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:26:12.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:26:12.82$vck44/valo=6,814.99 2006.257.11:26:12.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.11:26:12.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.11:26:12.82#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:12.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:12.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:12.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:12.82#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:26:12.82#ibcon#first serial, iclass 32, count 0 2006.257.11:26:12.82#ibcon#enter sib2, iclass 32, count 0 2006.257.11:26:12.82#ibcon#flushed, iclass 32, count 0 2006.257.11:26:12.82#ibcon#about to write, iclass 32, count 0 2006.257.11:26:12.82#ibcon#wrote, iclass 32, count 0 2006.257.11:26:12.82#ibcon#about to read 3, iclass 32, count 0 2006.257.11:26:12.83#ibcon#read 3, iclass 32, count 0 2006.257.11:26:12.83#ibcon#about to read 4, iclass 32, count 0 2006.257.11:26:12.84#ibcon#read 4, iclass 32, count 0 2006.257.11:26:12.84#ibcon#about to read 5, iclass 32, count 0 2006.257.11:26:12.84#ibcon#read 5, iclass 32, count 0 2006.257.11:26:12.84#ibcon#about to read 6, iclass 32, count 0 2006.257.11:26:12.84#ibcon#read 6, iclass 32, count 0 2006.257.11:26:12.84#ibcon#end of sib2, iclass 32, count 0 2006.257.11:26:12.84#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:26:12.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:26:12.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:26:12.84#ibcon#*before write, iclass 32, count 0 2006.257.11:26:12.84#ibcon#enter sib2, iclass 32, count 0 2006.257.11:26:12.84#ibcon#flushed, iclass 32, count 0 2006.257.11:26:12.84#ibcon#about to write, iclass 32, count 0 2006.257.11:26:12.84#ibcon#wrote, iclass 32, count 0 2006.257.11:26:12.84#ibcon#about to read 3, iclass 32, count 0 2006.257.11:26:12.87#ibcon#read 3, iclass 32, count 0 2006.257.11:26:12.88#ibcon#about to read 4, iclass 32, count 0 2006.257.11:26:12.88#ibcon#read 4, iclass 32, count 0 2006.257.11:26:12.88#ibcon#about to read 5, iclass 32, count 0 2006.257.11:26:12.88#ibcon#read 5, iclass 32, count 0 2006.257.11:26:12.88#ibcon#about to read 6, iclass 32, count 0 2006.257.11:26:12.88#ibcon#read 6, iclass 32, count 0 2006.257.11:26:12.88#ibcon#end of sib2, iclass 32, count 0 2006.257.11:26:12.88#ibcon#*after write, iclass 32, count 0 2006.257.11:26:12.88#ibcon#*before return 0, iclass 32, count 0 2006.257.11:26:12.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:12.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:12.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:26:12.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:26:12.88$vck44/va=6,4 2006.257.11:26:12.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.11:26:12.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.11:26:12.88#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:12.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:12.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:12.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:12.94#ibcon#enter wrdev, iclass 34, count 2 2006.257.11:26:12.94#ibcon#first serial, iclass 34, count 2 2006.257.11:26:12.94#ibcon#enter sib2, iclass 34, count 2 2006.257.11:26:12.94#ibcon#flushed, iclass 34, count 2 2006.257.11:26:12.94#ibcon#about to write, iclass 34, count 2 2006.257.11:26:12.94#ibcon#wrote, iclass 34, count 2 2006.257.11:26:12.94#ibcon#about to read 3, iclass 34, count 2 2006.257.11:26:12.95#ibcon#read 3, iclass 34, count 2 2006.257.11:26:12.96#ibcon#about to read 4, iclass 34, count 2 2006.257.11:26:12.96#ibcon#read 4, iclass 34, count 2 2006.257.11:26:12.96#ibcon#about to read 5, iclass 34, count 2 2006.257.11:26:12.96#ibcon#read 5, iclass 34, count 2 2006.257.11:26:12.96#ibcon#about to read 6, iclass 34, count 2 2006.257.11:26:12.96#ibcon#read 6, iclass 34, count 2 2006.257.11:26:12.96#ibcon#end of sib2, iclass 34, count 2 2006.257.11:26:12.96#ibcon#*mode == 0, iclass 34, count 2 2006.257.11:26:12.96#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.11:26:12.96#ibcon#[25=AT06-04\r\n] 2006.257.11:26:12.96#ibcon#*before write, iclass 34, count 2 2006.257.11:26:12.96#ibcon#enter sib2, iclass 34, count 2 2006.257.11:26:12.96#ibcon#flushed, iclass 34, count 2 2006.257.11:26:12.96#ibcon#about to write, iclass 34, count 2 2006.257.11:26:12.96#ibcon#wrote, iclass 34, count 2 2006.257.11:26:12.96#ibcon#about to read 3, iclass 34, count 2 2006.257.11:26:12.98#ibcon#read 3, iclass 34, count 2 2006.257.11:26:12.98#ibcon#about to read 4, iclass 34, count 2 2006.257.11:26:12.99#ibcon#read 4, iclass 34, count 2 2006.257.11:26:12.99#ibcon#about to read 5, iclass 34, count 2 2006.257.11:26:12.99#ibcon#read 5, iclass 34, count 2 2006.257.11:26:12.99#ibcon#about to read 6, iclass 34, count 2 2006.257.11:26:12.99#ibcon#read 6, iclass 34, count 2 2006.257.11:26:12.99#ibcon#end of sib2, iclass 34, count 2 2006.257.11:26:12.99#ibcon#*after write, iclass 34, count 2 2006.257.11:26:12.99#ibcon#*before return 0, iclass 34, count 2 2006.257.11:26:12.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:12.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:12.99#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.11:26:12.99#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:12.99#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:13.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:13.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:13.11#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:26:13.11#ibcon#first serial, iclass 34, count 0 2006.257.11:26:13.11#ibcon#enter sib2, iclass 34, count 0 2006.257.11:26:13.11#ibcon#flushed, iclass 34, count 0 2006.257.11:26:13.11#ibcon#about to write, iclass 34, count 0 2006.257.11:26:13.11#ibcon#wrote, iclass 34, count 0 2006.257.11:26:13.11#ibcon#about to read 3, iclass 34, count 0 2006.257.11:26:13.12#ibcon#read 3, iclass 34, count 0 2006.257.11:26:13.13#ibcon#about to read 4, iclass 34, count 0 2006.257.11:26:13.13#ibcon#read 4, iclass 34, count 0 2006.257.11:26:13.13#ibcon#about to read 5, iclass 34, count 0 2006.257.11:26:13.13#ibcon#read 5, iclass 34, count 0 2006.257.11:26:13.13#ibcon#about to read 6, iclass 34, count 0 2006.257.11:26:13.13#ibcon#read 6, iclass 34, count 0 2006.257.11:26:13.13#ibcon#end of sib2, iclass 34, count 0 2006.257.11:26:13.13#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:26:13.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:26:13.13#ibcon#[25=USB\r\n] 2006.257.11:26:13.13#ibcon#*before write, iclass 34, count 0 2006.257.11:26:13.13#ibcon#enter sib2, iclass 34, count 0 2006.257.11:26:13.13#ibcon#flushed, iclass 34, count 0 2006.257.11:26:13.13#ibcon#about to write, iclass 34, count 0 2006.257.11:26:13.13#ibcon#wrote, iclass 34, count 0 2006.257.11:26:13.13#ibcon#about to read 3, iclass 34, count 0 2006.257.11:26:13.15#ibcon#read 3, iclass 34, count 0 2006.257.11:26:13.16#ibcon#about to read 4, iclass 34, count 0 2006.257.11:26:13.16#ibcon#read 4, iclass 34, count 0 2006.257.11:26:13.16#ibcon#about to read 5, iclass 34, count 0 2006.257.11:26:13.16#ibcon#read 5, iclass 34, count 0 2006.257.11:26:13.16#ibcon#about to read 6, iclass 34, count 0 2006.257.11:26:13.16#ibcon#read 6, iclass 34, count 0 2006.257.11:26:13.16#ibcon#end of sib2, iclass 34, count 0 2006.257.11:26:13.16#ibcon#*after write, iclass 34, count 0 2006.257.11:26:13.16#ibcon#*before return 0, iclass 34, count 0 2006.257.11:26:13.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:13.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:13.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:26:13.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:26:13.16$vck44/valo=7,864.99 2006.257.11:26:13.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.11:26:13.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.11:26:13.16#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:13.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:13.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:13.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:13.16#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:26:13.16#ibcon#first serial, iclass 36, count 0 2006.257.11:26:13.16#ibcon#enter sib2, iclass 36, count 0 2006.257.11:26:13.16#ibcon#flushed, iclass 36, count 0 2006.257.11:26:13.16#ibcon#about to write, iclass 36, count 0 2006.257.11:26:13.16#ibcon#wrote, iclass 36, count 0 2006.257.11:26:13.16#ibcon#about to read 3, iclass 36, count 0 2006.257.11:26:13.17#ibcon#read 3, iclass 36, count 0 2006.257.11:26:13.18#ibcon#about to read 4, iclass 36, count 0 2006.257.11:26:13.18#ibcon#read 4, iclass 36, count 0 2006.257.11:26:13.18#ibcon#about to read 5, iclass 36, count 0 2006.257.11:26:13.18#ibcon#read 5, iclass 36, count 0 2006.257.11:26:13.18#ibcon#about to read 6, iclass 36, count 0 2006.257.11:26:13.18#ibcon#read 6, iclass 36, count 0 2006.257.11:26:13.18#ibcon#end of sib2, iclass 36, count 0 2006.257.11:26:13.18#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:26:13.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:26:13.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:26:13.18#ibcon#*before write, iclass 36, count 0 2006.257.11:26:13.18#ibcon#enter sib2, iclass 36, count 0 2006.257.11:26:13.18#ibcon#flushed, iclass 36, count 0 2006.257.11:26:13.18#ibcon#about to write, iclass 36, count 0 2006.257.11:26:13.18#ibcon#wrote, iclass 36, count 0 2006.257.11:26:13.18#ibcon#about to read 3, iclass 36, count 0 2006.257.11:26:13.21#ibcon#read 3, iclass 36, count 0 2006.257.11:26:13.22#ibcon#about to read 4, iclass 36, count 0 2006.257.11:26:13.22#ibcon#read 4, iclass 36, count 0 2006.257.11:26:13.22#ibcon#about to read 5, iclass 36, count 0 2006.257.11:26:13.22#ibcon#read 5, iclass 36, count 0 2006.257.11:26:13.22#ibcon#about to read 6, iclass 36, count 0 2006.257.11:26:13.22#ibcon#read 6, iclass 36, count 0 2006.257.11:26:13.22#ibcon#end of sib2, iclass 36, count 0 2006.257.11:26:13.22#ibcon#*after write, iclass 36, count 0 2006.257.11:26:13.22#ibcon#*before return 0, iclass 36, count 0 2006.257.11:26:13.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:13.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:13.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:26:13.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:26:13.22$vck44/va=7,4 2006.257.11:26:13.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.11:26:13.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.11:26:13.22#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:13.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:13.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:13.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:13.28#ibcon#enter wrdev, iclass 38, count 2 2006.257.11:26:13.28#ibcon#first serial, iclass 38, count 2 2006.257.11:26:13.28#ibcon#enter sib2, iclass 38, count 2 2006.257.11:26:13.28#ibcon#flushed, iclass 38, count 2 2006.257.11:26:13.28#ibcon#about to write, iclass 38, count 2 2006.257.11:26:13.28#ibcon#wrote, iclass 38, count 2 2006.257.11:26:13.28#ibcon#about to read 3, iclass 38, count 2 2006.257.11:26:13.29#ibcon#read 3, iclass 38, count 2 2006.257.11:26:13.30#ibcon#about to read 4, iclass 38, count 2 2006.257.11:26:13.30#ibcon#read 4, iclass 38, count 2 2006.257.11:26:13.30#ibcon#about to read 5, iclass 38, count 2 2006.257.11:26:13.30#ibcon#read 5, iclass 38, count 2 2006.257.11:26:13.30#ibcon#about to read 6, iclass 38, count 2 2006.257.11:26:13.30#ibcon#read 6, iclass 38, count 2 2006.257.11:26:13.30#ibcon#end of sib2, iclass 38, count 2 2006.257.11:26:13.30#ibcon#*mode == 0, iclass 38, count 2 2006.257.11:26:13.30#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.11:26:13.30#ibcon#[25=AT07-04\r\n] 2006.257.11:26:13.30#ibcon#*before write, iclass 38, count 2 2006.257.11:26:13.30#ibcon#enter sib2, iclass 38, count 2 2006.257.11:26:13.30#ibcon#flushed, iclass 38, count 2 2006.257.11:26:13.30#ibcon#about to write, iclass 38, count 2 2006.257.11:26:13.30#ibcon#wrote, iclass 38, count 2 2006.257.11:26:13.30#ibcon#about to read 3, iclass 38, count 2 2006.257.11:26:13.33#ibcon#read 3, iclass 38, count 2 2006.257.11:26:13.33#ibcon#about to read 4, iclass 38, count 2 2006.257.11:26:13.33#ibcon#read 4, iclass 38, count 2 2006.257.11:26:13.33#ibcon#about to read 5, iclass 38, count 2 2006.257.11:26:13.33#ibcon#read 5, iclass 38, count 2 2006.257.11:26:13.33#ibcon#about to read 6, iclass 38, count 2 2006.257.11:26:13.33#ibcon#read 6, iclass 38, count 2 2006.257.11:26:13.33#ibcon#end of sib2, iclass 38, count 2 2006.257.11:26:13.33#ibcon#*after write, iclass 38, count 2 2006.257.11:26:13.33#ibcon#*before return 0, iclass 38, count 2 2006.257.11:26:13.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:13.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:13.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.11:26:13.33#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:13.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:13.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:13.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:13.45#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:26:13.45#ibcon#first serial, iclass 38, count 0 2006.257.11:26:13.45#ibcon#enter sib2, iclass 38, count 0 2006.257.11:26:13.45#ibcon#flushed, iclass 38, count 0 2006.257.11:26:13.45#ibcon#about to write, iclass 38, count 0 2006.257.11:26:13.45#ibcon#wrote, iclass 38, count 0 2006.257.11:26:13.45#ibcon#about to read 3, iclass 38, count 0 2006.257.11:26:13.46#ibcon#read 3, iclass 38, count 0 2006.257.11:26:13.47#ibcon#about to read 4, iclass 38, count 0 2006.257.11:26:13.47#ibcon#read 4, iclass 38, count 0 2006.257.11:26:13.47#ibcon#about to read 5, iclass 38, count 0 2006.257.11:26:13.47#ibcon#read 5, iclass 38, count 0 2006.257.11:26:13.47#ibcon#about to read 6, iclass 38, count 0 2006.257.11:26:13.47#ibcon#read 6, iclass 38, count 0 2006.257.11:26:13.47#ibcon#end of sib2, iclass 38, count 0 2006.257.11:26:13.47#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:26:13.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:26:13.47#ibcon#[25=USB\r\n] 2006.257.11:26:13.47#ibcon#*before write, iclass 38, count 0 2006.257.11:26:13.47#ibcon#enter sib2, iclass 38, count 0 2006.257.11:26:13.47#ibcon#flushed, iclass 38, count 0 2006.257.11:26:13.47#ibcon#about to write, iclass 38, count 0 2006.257.11:26:13.47#ibcon#wrote, iclass 38, count 0 2006.257.11:26:13.47#ibcon#about to read 3, iclass 38, count 0 2006.257.11:26:13.49#ibcon#read 3, iclass 38, count 0 2006.257.11:26:13.50#ibcon#about to read 4, iclass 38, count 0 2006.257.11:26:13.50#ibcon#read 4, iclass 38, count 0 2006.257.11:26:13.50#ibcon#about to read 5, iclass 38, count 0 2006.257.11:26:13.50#ibcon#read 5, iclass 38, count 0 2006.257.11:26:13.50#ibcon#about to read 6, iclass 38, count 0 2006.257.11:26:13.50#ibcon#read 6, iclass 38, count 0 2006.257.11:26:13.50#ibcon#end of sib2, iclass 38, count 0 2006.257.11:26:13.50#ibcon#*after write, iclass 38, count 0 2006.257.11:26:13.50#ibcon#*before return 0, iclass 38, count 0 2006.257.11:26:13.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:13.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:13.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:26:13.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:26:13.50$vck44/valo=8,884.99 2006.257.11:26:13.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.11:26:13.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.11:26:13.50#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:13.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:13.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:13.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:13.50#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:26:13.50#ibcon#first serial, iclass 40, count 0 2006.257.11:26:13.50#ibcon#enter sib2, iclass 40, count 0 2006.257.11:26:13.50#ibcon#flushed, iclass 40, count 0 2006.257.11:26:13.50#ibcon#about to write, iclass 40, count 0 2006.257.11:26:13.50#ibcon#wrote, iclass 40, count 0 2006.257.11:26:13.50#ibcon#about to read 3, iclass 40, count 0 2006.257.11:26:13.52#ibcon#read 3, iclass 40, count 0 2006.257.11:26:13.52#ibcon#about to read 4, iclass 40, count 0 2006.257.11:26:13.52#ibcon#read 4, iclass 40, count 0 2006.257.11:26:13.52#ibcon#about to read 5, iclass 40, count 0 2006.257.11:26:13.52#ibcon#read 5, iclass 40, count 0 2006.257.11:26:13.52#ibcon#about to read 6, iclass 40, count 0 2006.257.11:26:13.52#ibcon#read 6, iclass 40, count 0 2006.257.11:26:13.52#ibcon#end of sib2, iclass 40, count 0 2006.257.11:26:13.52#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:26:13.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:26:13.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:26:13.52#ibcon#*before write, iclass 40, count 0 2006.257.11:26:13.52#ibcon#enter sib2, iclass 40, count 0 2006.257.11:26:13.52#ibcon#flushed, iclass 40, count 0 2006.257.11:26:13.52#ibcon#about to write, iclass 40, count 0 2006.257.11:26:13.52#ibcon#wrote, iclass 40, count 0 2006.257.11:26:13.52#ibcon#about to read 3, iclass 40, count 0 2006.257.11:26:13.55#ibcon#read 3, iclass 40, count 0 2006.257.11:26:13.56#ibcon#about to read 4, iclass 40, count 0 2006.257.11:26:13.56#ibcon#read 4, iclass 40, count 0 2006.257.11:26:13.56#ibcon#about to read 5, iclass 40, count 0 2006.257.11:26:13.56#ibcon#read 5, iclass 40, count 0 2006.257.11:26:13.56#ibcon#about to read 6, iclass 40, count 0 2006.257.11:26:13.56#ibcon#read 6, iclass 40, count 0 2006.257.11:26:13.56#ibcon#end of sib2, iclass 40, count 0 2006.257.11:26:13.56#ibcon#*after write, iclass 40, count 0 2006.257.11:26:13.56#ibcon#*before return 0, iclass 40, count 0 2006.257.11:26:13.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:13.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:13.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:26:13.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:26:13.56$vck44/va=8,4 2006.257.11:26:13.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.11:26:13.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.11:26:13.56#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:13.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:26:13.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:26:13.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:26:13.62#ibcon#enter wrdev, iclass 4, count 2 2006.257.11:26:13.62#ibcon#first serial, iclass 4, count 2 2006.257.11:26:13.62#ibcon#enter sib2, iclass 4, count 2 2006.257.11:26:13.62#ibcon#flushed, iclass 4, count 2 2006.257.11:26:13.62#ibcon#about to write, iclass 4, count 2 2006.257.11:26:13.62#ibcon#wrote, iclass 4, count 2 2006.257.11:26:13.62#ibcon#about to read 3, iclass 4, count 2 2006.257.11:26:13.63#ibcon#read 3, iclass 4, count 2 2006.257.11:26:13.64#ibcon#about to read 4, iclass 4, count 2 2006.257.11:26:13.64#ibcon#read 4, iclass 4, count 2 2006.257.11:26:13.64#ibcon#about to read 5, iclass 4, count 2 2006.257.11:26:13.64#ibcon#read 5, iclass 4, count 2 2006.257.11:26:13.64#ibcon#about to read 6, iclass 4, count 2 2006.257.11:26:13.64#ibcon#read 6, iclass 4, count 2 2006.257.11:26:13.64#ibcon#end of sib2, iclass 4, count 2 2006.257.11:26:13.64#ibcon#*mode == 0, iclass 4, count 2 2006.257.11:26:13.64#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.11:26:13.64#ibcon#[25=AT08-04\r\n] 2006.257.11:26:13.64#ibcon#*before write, iclass 4, count 2 2006.257.11:26:13.64#ibcon#enter sib2, iclass 4, count 2 2006.257.11:26:13.64#ibcon#flushed, iclass 4, count 2 2006.257.11:26:13.64#ibcon#about to write, iclass 4, count 2 2006.257.11:26:13.64#ibcon#wrote, iclass 4, count 2 2006.257.11:26:13.64#ibcon#about to read 3, iclass 4, count 2 2006.257.11:26:13.66#ibcon#read 3, iclass 4, count 2 2006.257.11:26:13.67#ibcon#about to read 4, iclass 4, count 2 2006.257.11:26:13.67#ibcon#read 4, iclass 4, count 2 2006.257.11:26:13.67#ibcon#about to read 5, iclass 4, count 2 2006.257.11:26:13.67#ibcon#read 5, iclass 4, count 2 2006.257.11:26:13.67#ibcon#about to read 6, iclass 4, count 2 2006.257.11:26:13.67#ibcon#read 6, iclass 4, count 2 2006.257.11:26:13.67#ibcon#end of sib2, iclass 4, count 2 2006.257.11:26:13.67#ibcon#*after write, iclass 4, count 2 2006.257.11:26:13.67#ibcon#*before return 0, iclass 4, count 2 2006.257.11:26:13.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:26:13.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:26:13.67#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.11:26:13.67#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:13.67#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:26:13.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:26:13.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:26:13.79#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:26:13.79#ibcon#first serial, iclass 4, count 0 2006.257.11:26:13.79#ibcon#enter sib2, iclass 4, count 0 2006.257.11:26:13.79#ibcon#flushed, iclass 4, count 0 2006.257.11:26:13.79#ibcon#about to write, iclass 4, count 0 2006.257.11:26:13.79#ibcon#wrote, iclass 4, count 0 2006.257.11:26:13.79#ibcon#about to read 3, iclass 4, count 0 2006.257.11:26:13.80#ibcon#read 3, iclass 4, count 0 2006.257.11:26:13.81#ibcon#about to read 4, iclass 4, count 0 2006.257.11:26:13.81#ibcon#read 4, iclass 4, count 0 2006.257.11:26:13.81#ibcon#about to read 5, iclass 4, count 0 2006.257.11:26:13.81#ibcon#read 5, iclass 4, count 0 2006.257.11:26:13.81#ibcon#about to read 6, iclass 4, count 0 2006.257.11:26:13.81#ibcon#read 6, iclass 4, count 0 2006.257.11:26:13.81#ibcon#end of sib2, iclass 4, count 0 2006.257.11:26:13.81#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:26:13.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:26:13.81#ibcon#[25=USB\r\n] 2006.257.11:26:13.81#ibcon#*before write, iclass 4, count 0 2006.257.11:26:13.81#ibcon#enter sib2, iclass 4, count 0 2006.257.11:26:13.81#ibcon#flushed, iclass 4, count 0 2006.257.11:26:13.81#ibcon#about to write, iclass 4, count 0 2006.257.11:26:13.81#ibcon#wrote, iclass 4, count 0 2006.257.11:26:13.81#ibcon#about to read 3, iclass 4, count 0 2006.257.11:26:13.83#ibcon#read 3, iclass 4, count 0 2006.257.11:26:13.83#ibcon#about to read 4, iclass 4, count 0 2006.257.11:26:13.84#ibcon#read 4, iclass 4, count 0 2006.257.11:26:13.84#ibcon#about to read 5, iclass 4, count 0 2006.257.11:26:13.84#ibcon#read 5, iclass 4, count 0 2006.257.11:26:13.84#ibcon#about to read 6, iclass 4, count 0 2006.257.11:26:13.84#ibcon#read 6, iclass 4, count 0 2006.257.11:26:13.84#ibcon#end of sib2, iclass 4, count 0 2006.257.11:26:13.84#ibcon#*after write, iclass 4, count 0 2006.257.11:26:13.84#ibcon#*before return 0, iclass 4, count 0 2006.257.11:26:13.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:26:13.84#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:26:13.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:26:13.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:26:13.84$vck44/vblo=1,629.99 2006.257.11:26:13.84#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.11:26:13.84#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.11:26:13.84#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:13.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:13.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:13.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:13.84#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:26:13.84#ibcon#first serial, iclass 6, count 0 2006.257.11:26:13.84#ibcon#enter sib2, iclass 6, count 0 2006.257.11:26:13.84#ibcon#flushed, iclass 6, count 0 2006.257.11:26:13.84#ibcon#about to write, iclass 6, count 0 2006.257.11:26:13.84#ibcon#wrote, iclass 6, count 0 2006.257.11:26:13.84#ibcon#about to read 3, iclass 6, count 0 2006.257.11:26:13.85#ibcon#read 3, iclass 6, count 0 2006.257.11:26:13.86#ibcon#about to read 4, iclass 6, count 0 2006.257.11:26:13.86#ibcon#read 4, iclass 6, count 0 2006.257.11:26:13.86#ibcon#about to read 5, iclass 6, count 0 2006.257.11:26:13.86#ibcon#read 5, iclass 6, count 0 2006.257.11:26:13.86#ibcon#about to read 6, iclass 6, count 0 2006.257.11:26:13.86#ibcon#read 6, iclass 6, count 0 2006.257.11:26:13.86#ibcon#end of sib2, iclass 6, count 0 2006.257.11:26:13.86#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:26:13.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:26:13.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:26:13.86#ibcon#*before write, iclass 6, count 0 2006.257.11:26:13.86#ibcon#enter sib2, iclass 6, count 0 2006.257.11:26:13.86#ibcon#flushed, iclass 6, count 0 2006.257.11:26:13.86#ibcon#about to write, iclass 6, count 0 2006.257.11:26:13.86#ibcon#wrote, iclass 6, count 0 2006.257.11:26:13.86#ibcon#about to read 3, iclass 6, count 0 2006.257.11:26:13.89#ibcon#read 3, iclass 6, count 0 2006.257.11:26:13.89#ibcon#about to read 4, iclass 6, count 0 2006.257.11:26:13.90#ibcon#read 4, iclass 6, count 0 2006.257.11:26:13.90#ibcon#about to read 5, iclass 6, count 0 2006.257.11:26:13.90#ibcon#read 5, iclass 6, count 0 2006.257.11:26:13.90#ibcon#about to read 6, iclass 6, count 0 2006.257.11:26:13.90#ibcon#read 6, iclass 6, count 0 2006.257.11:26:13.90#ibcon#end of sib2, iclass 6, count 0 2006.257.11:26:13.90#ibcon#*after write, iclass 6, count 0 2006.257.11:26:13.90#ibcon#*before return 0, iclass 6, count 0 2006.257.11:26:13.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:13.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:26:13.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:26:13.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:26:13.90$vck44/vb=1,4 2006.257.11:26:13.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.11:26:13.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.11:26:13.90#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:13.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:13.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:13.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:13.90#ibcon#enter wrdev, iclass 10, count 2 2006.257.11:26:13.90#ibcon#first serial, iclass 10, count 2 2006.257.11:26:13.90#ibcon#enter sib2, iclass 10, count 2 2006.257.11:26:13.90#ibcon#flushed, iclass 10, count 2 2006.257.11:26:13.90#ibcon#about to write, iclass 10, count 2 2006.257.11:26:13.90#ibcon#wrote, iclass 10, count 2 2006.257.11:26:13.90#ibcon#about to read 3, iclass 10, count 2 2006.257.11:26:13.91#ibcon#read 3, iclass 10, count 2 2006.257.11:26:13.92#ibcon#about to read 4, iclass 10, count 2 2006.257.11:26:13.92#ibcon#read 4, iclass 10, count 2 2006.257.11:26:13.92#ibcon#about to read 5, iclass 10, count 2 2006.257.11:26:13.92#ibcon#read 5, iclass 10, count 2 2006.257.11:26:13.92#ibcon#about to read 6, iclass 10, count 2 2006.257.11:26:13.92#ibcon#read 6, iclass 10, count 2 2006.257.11:26:13.92#ibcon#end of sib2, iclass 10, count 2 2006.257.11:26:13.92#ibcon#*mode == 0, iclass 10, count 2 2006.257.11:26:13.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.11:26:13.92#ibcon#[27=AT01-04\r\n] 2006.257.11:26:13.92#ibcon#*before write, iclass 10, count 2 2006.257.11:26:13.92#ibcon#enter sib2, iclass 10, count 2 2006.257.11:26:13.92#ibcon#flushed, iclass 10, count 2 2006.257.11:26:13.92#ibcon#about to write, iclass 10, count 2 2006.257.11:26:13.92#ibcon#wrote, iclass 10, count 2 2006.257.11:26:13.92#ibcon#about to read 3, iclass 10, count 2 2006.257.11:26:13.94#ibcon#read 3, iclass 10, count 2 2006.257.11:26:13.95#ibcon#about to read 4, iclass 10, count 2 2006.257.11:26:13.95#ibcon#read 4, iclass 10, count 2 2006.257.11:26:13.95#ibcon#about to read 5, iclass 10, count 2 2006.257.11:26:13.95#ibcon#read 5, iclass 10, count 2 2006.257.11:26:13.95#ibcon#about to read 6, iclass 10, count 2 2006.257.11:26:13.95#ibcon#read 6, iclass 10, count 2 2006.257.11:26:13.95#ibcon#end of sib2, iclass 10, count 2 2006.257.11:26:13.95#ibcon#*after write, iclass 10, count 2 2006.257.11:26:13.95#ibcon#*before return 0, iclass 10, count 2 2006.257.11:26:13.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:13.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:26:13.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.11:26:13.95#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:13.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:14.06#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:14.07#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:14.07#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:26:14.07#ibcon#first serial, iclass 10, count 0 2006.257.11:26:14.07#ibcon#enter sib2, iclass 10, count 0 2006.257.11:26:14.07#ibcon#flushed, iclass 10, count 0 2006.257.11:26:14.07#ibcon#about to write, iclass 10, count 0 2006.257.11:26:14.07#ibcon#wrote, iclass 10, count 0 2006.257.11:26:14.07#ibcon#about to read 3, iclass 10, count 0 2006.257.11:26:14.08#ibcon#read 3, iclass 10, count 0 2006.257.11:26:14.09#ibcon#about to read 4, iclass 10, count 0 2006.257.11:26:14.09#ibcon#read 4, iclass 10, count 0 2006.257.11:26:14.09#ibcon#about to read 5, iclass 10, count 0 2006.257.11:26:14.09#ibcon#read 5, iclass 10, count 0 2006.257.11:26:14.09#ibcon#about to read 6, iclass 10, count 0 2006.257.11:26:14.09#ibcon#read 6, iclass 10, count 0 2006.257.11:26:14.09#ibcon#end of sib2, iclass 10, count 0 2006.257.11:26:14.09#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:26:14.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:26:14.09#ibcon#[27=USB\r\n] 2006.257.11:26:14.09#ibcon#*before write, iclass 10, count 0 2006.257.11:26:14.09#ibcon#enter sib2, iclass 10, count 0 2006.257.11:26:14.09#ibcon#flushed, iclass 10, count 0 2006.257.11:26:14.09#ibcon#about to write, iclass 10, count 0 2006.257.11:26:14.09#ibcon#wrote, iclass 10, count 0 2006.257.11:26:14.09#ibcon#about to read 3, iclass 10, count 0 2006.257.11:26:14.12#ibcon#read 3, iclass 10, count 0 2006.257.11:26:14.12#ibcon#about to read 4, iclass 10, count 0 2006.257.11:26:14.12#ibcon#read 4, iclass 10, count 0 2006.257.11:26:14.12#ibcon#about to read 5, iclass 10, count 0 2006.257.11:26:14.12#ibcon#read 5, iclass 10, count 0 2006.257.11:26:14.12#ibcon#about to read 6, iclass 10, count 0 2006.257.11:26:14.12#ibcon#read 6, iclass 10, count 0 2006.257.11:26:14.12#ibcon#end of sib2, iclass 10, count 0 2006.257.11:26:14.12#ibcon#*after write, iclass 10, count 0 2006.257.11:26:14.12#ibcon#*before return 0, iclass 10, count 0 2006.257.11:26:14.12#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:14.12#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:26:14.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:26:14.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:26:14.12$vck44/vblo=2,634.99 2006.257.11:26:14.12#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.11:26:14.12#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.11:26:14.12#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:14.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:14.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:14.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:14.12#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:26:14.12#ibcon#first serial, iclass 12, count 0 2006.257.11:26:14.12#ibcon#enter sib2, iclass 12, count 0 2006.257.11:26:14.12#ibcon#flushed, iclass 12, count 0 2006.257.11:26:14.12#ibcon#about to write, iclass 12, count 0 2006.257.11:26:14.12#ibcon#wrote, iclass 12, count 0 2006.257.11:26:14.12#ibcon#about to read 3, iclass 12, count 0 2006.257.11:26:14.14#ibcon#read 3, iclass 12, count 0 2006.257.11:26:14.14#ibcon#about to read 4, iclass 12, count 0 2006.257.11:26:14.14#ibcon#read 4, iclass 12, count 0 2006.257.11:26:14.14#ibcon#about to read 5, iclass 12, count 0 2006.257.11:26:14.14#ibcon#read 5, iclass 12, count 0 2006.257.11:26:14.14#ibcon#about to read 6, iclass 12, count 0 2006.257.11:26:14.14#ibcon#read 6, iclass 12, count 0 2006.257.11:26:14.14#ibcon#end of sib2, iclass 12, count 0 2006.257.11:26:14.14#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:26:14.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:26:14.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:26:14.14#ibcon#*before write, iclass 12, count 0 2006.257.11:26:14.14#ibcon#enter sib2, iclass 12, count 0 2006.257.11:26:14.14#ibcon#flushed, iclass 12, count 0 2006.257.11:26:14.14#ibcon#about to write, iclass 12, count 0 2006.257.11:26:14.14#ibcon#wrote, iclass 12, count 0 2006.257.11:26:14.14#ibcon#about to read 3, iclass 12, count 0 2006.257.11:26:14.17#ibcon#read 3, iclass 12, count 0 2006.257.11:26:14.18#ibcon#about to read 4, iclass 12, count 0 2006.257.11:26:14.18#ibcon#read 4, iclass 12, count 0 2006.257.11:26:14.18#ibcon#about to read 5, iclass 12, count 0 2006.257.11:26:14.18#ibcon#read 5, iclass 12, count 0 2006.257.11:26:14.18#ibcon#about to read 6, iclass 12, count 0 2006.257.11:26:14.18#ibcon#read 6, iclass 12, count 0 2006.257.11:26:14.18#ibcon#end of sib2, iclass 12, count 0 2006.257.11:26:14.18#ibcon#*after write, iclass 12, count 0 2006.257.11:26:14.18#ibcon#*before return 0, iclass 12, count 0 2006.257.11:26:14.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:14.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:26:14.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:26:14.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:26:14.18$vck44/vb=2,5 2006.257.11:26:14.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.11:26:14.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.11:26:14.18#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:14.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:14.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:14.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:14.24#ibcon#enter wrdev, iclass 14, count 2 2006.257.11:26:14.24#ibcon#first serial, iclass 14, count 2 2006.257.11:26:14.24#ibcon#enter sib2, iclass 14, count 2 2006.257.11:26:14.24#ibcon#flushed, iclass 14, count 2 2006.257.11:26:14.24#ibcon#about to write, iclass 14, count 2 2006.257.11:26:14.24#ibcon#wrote, iclass 14, count 2 2006.257.11:26:14.24#ibcon#about to read 3, iclass 14, count 2 2006.257.11:26:14.25#ibcon#read 3, iclass 14, count 2 2006.257.11:26:14.26#ibcon#about to read 4, iclass 14, count 2 2006.257.11:26:14.26#ibcon#read 4, iclass 14, count 2 2006.257.11:26:14.26#ibcon#about to read 5, iclass 14, count 2 2006.257.11:26:14.26#ibcon#read 5, iclass 14, count 2 2006.257.11:26:14.26#ibcon#about to read 6, iclass 14, count 2 2006.257.11:26:14.26#ibcon#read 6, iclass 14, count 2 2006.257.11:26:14.26#ibcon#end of sib2, iclass 14, count 2 2006.257.11:26:14.26#ibcon#*mode == 0, iclass 14, count 2 2006.257.11:26:14.26#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.11:26:14.26#ibcon#[27=AT02-05\r\n] 2006.257.11:26:14.26#ibcon#*before write, iclass 14, count 2 2006.257.11:26:14.26#ibcon#enter sib2, iclass 14, count 2 2006.257.11:26:14.26#ibcon#flushed, iclass 14, count 2 2006.257.11:26:14.26#ibcon#about to write, iclass 14, count 2 2006.257.11:26:14.26#ibcon#wrote, iclass 14, count 2 2006.257.11:26:14.26#ibcon#about to read 3, iclass 14, count 2 2006.257.11:26:14.28#ibcon#read 3, iclass 14, count 2 2006.257.11:26:14.29#ibcon#about to read 4, iclass 14, count 2 2006.257.11:26:14.29#ibcon#read 4, iclass 14, count 2 2006.257.11:26:14.29#ibcon#about to read 5, iclass 14, count 2 2006.257.11:26:14.29#ibcon#read 5, iclass 14, count 2 2006.257.11:26:14.29#ibcon#about to read 6, iclass 14, count 2 2006.257.11:26:14.29#ibcon#read 6, iclass 14, count 2 2006.257.11:26:14.29#ibcon#end of sib2, iclass 14, count 2 2006.257.11:26:14.29#ibcon#*after write, iclass 14, count 2 2006.257.11:26:14.29#ibcon#*before return 0, iclass 14, count 2 2006.257.11:26:14.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:14.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:26:14.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.11:26:14.36#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:14.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:14.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:14.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:14.48#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:26:14.48#ibcon#first serial, iclass 14, count 0 2006.257.11:26:14.48#ibcon#enter sib2, iclass 14, count 0 2006.257.11:26:14.48#ibcon#flushed, iclass 14, count 0 2006.257.11:26:14.48#ibcon#about to write, iclass 14, count 0 2006.257.11:26:14.48#ibcon#wrote, iclass 14, count 0 2006.257.11:26:14.48#ibcon#about to read 3, iclass 14, count 0 2006.257.11:26:14.49#ibcon#read 3, iclass 14, count 0 2006.257.11:26:14.50#ibcon#about to read 4, iclass 14, count 0 2006.257.11:26:14.50#ibcon#read 4, iclass 14, count 0 2006.257.11:26:14.50#ibcon#about to read 5, iclass 14, count 0 2006.257.11:26:14.50#ibcon#read 5, iclass 14, count 0 2006.257.11:26:14.50#ibcon#about to read 6, iclass 14, count 0 2006.257.11:26:14.50#ibcon#read 6, iclass 14, count 0 2006.257.11:26:14.50#ibcon#end of sib2, iclass 14, count 0 2006.257.11:26:14.50#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:26:14.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:26:14.50#ibcon#[27=USB\r\n] 2006.257.11:26:14.50#ibcon#*before write, iclass 14, count 0 2006.257.11:26:14.50#ibcon#enter sib2, iclass 14, count 0 2006.257.11:26:14.50#ibcon#flushed, iclass 14, count 0 2006.257.11:26:14.50#ibcon#about to write, iclass 14, count 0 2006.257.11:26:14.50#ibcon#wrote, iclass 14, count 0 2006.257.11:26:14.50#ibcon#about to read 3, iclass 14, count 0 2006.257.11:26:14.52#ibcon#read 3, iclass 14, count 0 2006.257.11:26:14.53#ibcon#about to read 4, iclass 14, count 0 2006.257.11:26:14.53#ibcon#read 4, iclass 14, count 0 2006.257.11:26:14.53#ibcon#about to read 5, iclass 14, count 0 2006.257.11:26:14.53#ibcon#read 5, iclass 14, count 0 2006.257.11:26:14.53#ibcon#about to read 6, iclass 14, count 0 2006.257.11:26:14.53#ibcon#read 6, iclass 14, count 0 2006.257.11:26:14.53#ibcon#end of sib2, iclass 14, count 0 2006.257.11:26:14.53#ibcon#*after write, iclass 14, count 0 2006.257.11:26:14.53#ibcon#*before return 0, iclass 14, count 0 2006.257.11:26:14.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:14.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:26:14.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:26:14.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:26:14.53$vck44/vblo=3,649.99 2006.257.11:26:14.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.11:26:14.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.11:26:14.53#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:14.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:26:14.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:26:14.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:26:14.53#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:26:14.53#ibcon#first serial, iclass 16, count 0 2006.257.11:26:14.53#ibcon#enter sib2, iclass 16, count 0 2006.257.11:26:14.53#ibcon#flushed, iclass 16, count 0 2006.257.11:26:14.53#ibcon#about to write, iclass 16, count 0 2006.257.11:26:14.53#ibcon#wrote, iclass 16, count 0 2006.257.11:26:14.53#ibcon#about to read 3, iclass 16, count 0 2006.257.11:26:14.54#ibcon#read 3, iclass 16, count 0 2006.257.11:26:14.55#ibcon#about to read 4, iclass 16, count 0 2006.257.11:26:14.55#ibcon#read 4, iclass 16, count 0 2006.257.11:26:14.55#ibcon#about to read 5, iclass 16, count 0 2006.257.11:26:14.55#ibcon#read 5, iclass 16, count 0 2006.257.11:26:14.55#ibcon#about to read 6, iclass 16, count 0 2006.257.11:26:14.55#ibcon#read 6, iclass 16, count 0 2006.257.11:26:14.55#ibcon#end of sib2, iclass 16, count 0 2006.257.11:26:14.55#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:26:14.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:26:14.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:26:14.55#ibcon#*before write, iclass 16, count 0 2006.257.11:26:14.55#ibcon#enter sib2, iclass 16, count 0 2006.257.11:26:14.55#ibcon#flushed, iclass 16, count 0 2006.257.11:26:14.55#ibcon#about to write, iclass 16, count 0 2006.257.11:26:14.55#ibcon#wrote, iclass 16, count 0 2006.257.11:26:14.55#ibcon#about to read 3, iclass 16, count 0 2006.257.11:26:14.58#ibcon#read 3, iclass 16, count 0 2006.257.11:26:14.59#ibcon#about to read 4, iclass 16, count 0 2006.257.11:26:14.59#ibcon#read 4, iclass 16, count 0 2006.257.11:26:14.59#ibcon#about to read 5, iclass 16, count 0 2006.257.11:26:14.59#ibcon#read 5, iclass 16, count 0 2006.257.11:26:14.59#ibcon#about to read 6, iclass 16, count 0 2006.257.11:26:14.59#ibcon#read 6, iclass 16, count 0 2006.257.11:26:14.59#ibcon#end of sib2, iclass 16, count 0 2006.257.11:26:14.59#ibcon#*after write, iclass 16, count 0 2006.257.11:26:14.59#ibcon#*before return 0, iclass 16, count 0 2006.257.11:26:14.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:26:14.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:26:14.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:26:14.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:26:14.59$vck44/vb=3,4 2006.257.11:26:14.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.11:26:14.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.11:26:14.59#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:14.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:26:14.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:26:14.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:26:14.65#ibcon#enter wrdev, iclass 18, count 2 2006.257.11:26:14.65#ibcon#first serial, iclass 18, count 2 2006.257.11:26:14.65#ibcon#enter sib2, iclass 18, count 2 2006.257.11:26:14.65#ibcon#flushed, iclass 18, count 2 2006.257.11:26:14.65#ibcon#about to write, iclass 18, count 2 2006.257.11:26:14.65#ibcon#wrote, iclass 18, count 2 2006.257.11:26:14.65#ibcon#about to read 3, iclass 18, count 2 2006.257.11:26:14.66#ibcon#read 3, iclass 18, count 2 2006.257.11:26:14.66#ibcon#about to read 4, iclass 18, count 2 2006.257.11:26:14.67#ibcon#read 4, iclass 18, count 2 2006.257.11:26:14.67#ibcon#about to read 5, iclass 18, count 2 2006.257.11:26:14.67#ibcon#read 5, iclass 18, count 2 2006.257.11:26:14.67#ibcon#about to read 6, iclass 18, count 2 2006.257.11:26:14.67#ibcon#read 6, iclass 18, count 2 2006.257.11:26:14.67#ibcon#end of sib2, iclass 18, count 2 2006.257.11:26:14.67#ibcon#*mode == 0, iclass 18, count 2 2006.257.11:26:14.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.11:26:14.67#ibcon#[27=AT03-04\r\n] 2006.257.11:26:14.67#ibcon#*before write, iclass 18, count 2 2006.257.11:26:14.67#ibcon#enter sib2, iclass 18, count 2 2006.257.11:26:14.67#ibcon#flushed, iclass 18, count 2 2006.257.11:26:14.67#ibcon#about to write, iclass 18, count 2 2006.257.11:26:14.67#ibcon#wrote, iclass 18, count 2 2006.257.11:26:14.67#ibcon#about to read 3, iclass 18, count 2 2006.257.11:26:14.69#ibcon#read 3, iclass 18, count 2 2006.257.11:26:14.70#ibcon#about to read 4, iclass 18, count 2 2006.257.11:26:14.70#ibcon#read 4, iclass 18, count 2 2006.257.11:26:14.70#ibcon#about to read 5, iclass 18, count 2 2006.257.11:26:14.70#ibcon#read 5, iclass 18, count 2 2006.257.11:26:14.70#ibcon#about to read 6, iclass 18, count 2 2006.257.11:26:14.70#ibcon#read 6, iclass 18, count 2 2006.257.11:26:14.70#ibcon#end of sib2, iclass 18, count 2 2006.257.11:26:14.70#ibcon#*after write, iclass 18, count 2 2006.257.11:26:14.70#ibcon#*before return 0, iclass 18, count 2 2006.257.11:26:14.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:26:14.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:26:14.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.11:26:14.70#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:14.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:26:14.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:26:14.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:26:14.82#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:26:14.82#ibcon#first serial, iclass 18, count 0 2006.257.11:26:14.82#ibcon#enter sib2, iclass 18, count 0 2006.257.11:26:14.82#ibcon#flushed, iclass 18, count 0 2006.257.11:26:14.82#ibcon#about to write, iclass 18, count 0 2006.257.11:26:14.82#ibcon#wrote, iclass 18, count 0 2006.257.11:26:14.82#ibcon#about to read 3, iclass 18, count 0 2006.257.11:26:14.83#ibcon#read 3, iclass 18, count 0 2006.257.11:26:14.83#ibcon#about to read 4, iclass 18, count 0 2006.257.11:26:14.84#ibcon#read 4, iclass 18, count 0 2006.257.11:26:14.84#ibcon#about to read 5, iclass 18, count 0 2006.257.11:26:14.84#ibcon#read 5, iclass 18, count 0 2006.257.11:26:14.84#ibcon#about to read 6, iclass 18, count 0 2006.257.11:26:14.84#ibcon#read 6, iclass 18, count 0 2006.257.11:26:14.84#ibcon#end of sib2, iclass 18, count 0 2006.257.11:26:14.84#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:26:14.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:26:14.84#ibcon#[27=USB\r\n] 2006.257.11:26:14.84#ibcon#*before write, iclass 18, count 0 2006.257.11:26:14.84#ibcon#enter sib2, iclass 18, count 0 2006.257.11:26:14.84#ibcon#flushed, iclass 18, count 0 2006.257.11:26:14.84#ibcon#about to write, iclass 18, count 0 2006.257.11:26:14.84#ibcon#wrote, iclass 18, count 0 2006.257.11:26:14.84#ibcon#about to read 3, iclass 18, count 0 2006.257.11:26:14.86#ibcon#read 3, iclass 18, count 0 2006.257.11:26:14.86#ibcon#about to read 4, iclass 18, count 0 2006.257.11:26:14.87#ibcon#read 4, iclass 18, count 0 2006.257.11:26:14.87#ibcon#about to read 5, iclass 18, count 0 2006.257.11:26:14.87#ibcon#read 5, iclass 18, count 0 2006.257.11:26:14.87#ibcon#about to read 6, iclass 18, count 0 2006.257.11:26:14.87#ibcon#read 6, iclass 18, count 0 2006.257.11:26:14.87#ibcon#end of sib2, iclass 18, count 0 2006.257.11:26:14.87#ibcon#*after write, iclass 18, count 0 2006.257.11:26:14.87#ibcon#*before return 0, iclass 18, count 0 2006.257.11:26:14.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:26:14.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:26:14.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:26:14.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:26:14.87$vck44/vblo=4,679.99 2006.257.11:26:14.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.11:26:14.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.11:26:14.87#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:14.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:26:14.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:26:14.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:26:14.87#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:26:14.87#ibcon#first serial, iclass 20, count 0 2006.257.11:26:14.87#ibcon#enter sib2, iclass 20, count 0 2006.257.11:26:14.87#ibcon#flushed, iclass 20, count 0 2006.257.11:26:14.87#ibcon#about to write, iclass 20, count 0 2006.257.11:26:14.87#ibcon#wrote, iclass 20, count 0 2006.257.11:26:14.87#ibcon#about to read 3, iclass 20, count 0 2006.257.11:26:14.88#ibcon#read 3, iclass 20, count 0 2006.257.11:26:14.89#ibcon#about to read 4, iclass 20, count 0 2006.257.11:26:14.89#ibcon#read 4, iclass 20, count 0 2006.257.11:26:14.89#ibcon#about to read 5, iclass 20, count 0 2006.257.11:26:14.89#ibcon#read 5, iclass 20, count 0 2006.257.11:26:14.89#ibcon#about to read 6, iclass 20, count 0 2006.257.11:26:14.89#ibcon#read 6, iclass 20, count 0 2006.257.11:26:14.89#ibcon#end of sib2, iclass 20, count 0 2006.257.11:26:14.89#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:26:14.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:26:14.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:26:14.89#ibcon#*before write, iclass 20, count 0 2006.257.11:26:14.89#ibcon#enter sib2, iclass 20, count 0 2006.257.11:26:14.89#ibcon#flushed, iclass 20, count 0 2006.257.11:26:14.89#ibcon#about to write, iclass 20, count 0 2006.257.11:26:14.89#ibcon#wrote, iclass 20, count 0 2006.257.11:26:14.89#ibcon#about to read 3, iclass 20, count 0 2006.257.11:26:14.92#ibcon#read 3, iclass 20, count 0 2006.257.11:26:14.93#ibcon#about to read 4, iclass 20, count 0 2006.257.11:26:14.93#ibcon#read 4, iclass 20, count 0 2006.257.11:26:14.93#ibcon#about to read 5, iclass 20, count 0 2006.257.11:26:14.93#ibcon#read 5, iclass 20, count 0 2006.257.11:26:14.93#ibcon#about to read 6, iclass 20, count 0 2006.257.11:26:14.93#ibcon#read 6, iclass 20, count 0 2006.257.11:26:14.93#ibcon#end of sib2, iclass 20, count 0 2006.257.11:26:14.93#ibcon#*after write, iclass 20, count 0 2006.257.11:26:14.93#ibcon#*before return 0, iclass 20, count 0 2006.257.11:26:14.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:26:14.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:26:14.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:26:14.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:26:14.93$vck44/vb=4,5 2006.257.11:26:14.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.11:26:14.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.11:26:14.93#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:14.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:14.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:14.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:14.99#ibcon#enter wrdev, iclass 22, count 2 2006.257.11:26:14.99#ibcon#first serial, iclass 22, count 2 2006.257.11:26:14.99#ibcon#enter sib2, iclass 22, count 2 2006.257.11:26:14.99#ibcon#flushed, iclass 22, count 2 2006.257.11:26:14.99#ibcon#about to write, iclass 22, count 2 2006.257.11:26:14.99#ibcon#wrote, iclass 22, count 2 2006.257.11:26:14.99#ibcon#about to read 3, iclass 22, count 2 2006.257.11:26:15.00#ibcon#read 3, iclass 22, count 2 2006.257.11:26:15.00#ibcon#about to read 4, iclass 22, count 2 2006.257.11:26:15.01#ibcon#read 4, iclass 22, count 2 2006.257.11:26:15.01#ibcon#about to read 5, iclass 22, count 2 2006.257.11:26:15.01#ibcon#read 5, iclass 22, count 2 2006.257.11:26:15.01#ibcon#about to read 6, iclass 22, count 2 2006.257.11:26:15.01#ibcon#read 6, iclass 22, count 2 2006.257.11:26:15.01#ibcon#end of sib2, iclass 22, count 2 2006.257.11:26:15.01#ibcon#*mode == 0, iclass 22, count 2 2006.257.11:26:15.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.11:26:15.01#ibcon#[27=AT04-05\r\n] 2006.257.11:26:15.01#ibcon#*before write, iclass 22, count 2 2006.257.11:26:15.01#ibcon#enter sib2, iclass 22, count 2 2006.257.11:26:15.01#ibcon#flushed, iclass 22, count 2 2006.257.11:26:15.01#ibcon#about to write, iclass 22, count 2 2006.257.11:26:15.01#ibcon#wrote, iclass 22, count 2 2006.257.11:26:15.01#ibcon#about to read 3, iclass 22, count 2 2006.257.11:26:15.03#ibcon#read 3, iclass 22, count 2 2006.257.11:26:15.04#ibcon#about to read 4, iclass 22, count 2 2006.257.11:26:15.04#ibcon#read 4, iclass 22, count 2 2006.257.11:26:15.04#ibcon#about to read 5, iclass 22, count 2 2006.257.11:26:15.04#ibcon#read 5, iclass 22, count 2 2006.257.11:26:15.04#ibcon#about to read 6, iclass 22, count 2 2006.257.11:26:15.04#ibcon#read 6, iclass 22, count 2 2006.257.11:26:15.04#ibcon#end of sib2, iclass 22, count 2 2006.257.11:26:15.04#ibcon#*after write, iclass 22, count 2 2006.257.11:26:15.04#ibcon#*before return 0, iclass 22, count 2 2006.257.11:26:15.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:15.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:26:15.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.11:26:15.04#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:15.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:15.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:15.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:15.16#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:26:15.16#ibcon#first serial, iclass 22, count 0 2006.257.11:26:15.16#ibcon#enter sib2, iclass 22, count 0 2006.257.11:26:15.16#ibcon#flushed, iclass 22, count 0 2006.257.11:26:15.16#ibcon#about to write, iclass 22, count 0 2006.257.11:26:15.16#ibcon#wrote, iclass 22, count 0 2006.257.11:26:15.16#ibcon#about to read 3, iclass 22, count 0 2006.257.11:26:15.17#ibcon#read 3, iclass 22, count 0 2006.257.11:26:15.18#ibcon#about to read 4, iclass 22, count 0 2006.257.11:26:15.18#ibcon#read 4, iclass 22, count 0 2006.257.11:26:15.18#ibcon#about to read 5, iclass 22, count 0 2006.257.11:26:15.18#ibcon#read 5, iclass 22, count 0 2006.257.11:26:15.18#ibcon#about to read 6, iclass 22, count 0 2006.257.11:26:15.18#ibcon#read 6, iclass 22, count 0 2006.257.11:26:15.18#ibcon#end of sib2, iclass 22, count 0 2006.257.11:26:15.18#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:26:15.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:26:15.18#ibcon#[27=USB\r\n] 2006.257.11:26:15.18#ibcon#*before write, iclass 22, count 0 2006.257.11:26:15.18#ibcon#enter sib2, iclass 22, count 0 2006.257.11:26:15.18#ibcon#flushed, iclass 22, count 0 2006.257.11:26:15.18#ibcon#about to write, iclass 22, count 0 2006.257.11:26:15.18#ibcon#wrote, iclass 22, count 0 2006.257.11:26:15.18#ibcon#about to read 3, iclass 22, count 0 2006.257.11:26:15.20#ibcon#read 3, iclass 22, count 0 2006.257.11:26:15.21#ibcon#about to read 4, iclass 22, count 0 2006.257.11:26:15.21#ibcon#read 4, iclass 22, count 0 2006.257.11:26:15.21#ibcon#about to read 5, iclass 22, count 0 2006.257.11:26:15.21#ibcon#read 5, iclass 22, count 0 2006.257.11:26:15.21#ibcon#about to read 6, iclass 22, count 0 2006.257.11:26:15.21#ibcon#read 6, iclass 22, count 0 2006.257.11:26:15.21#ibcon#end of sib2, iclass 22, count 0 2006.257.11:26:15.21#ibcon#*after write, iclass 22, count 0 2006.257.11:26:15.21#ibcon#*before return 0, iclass 22, count 0 2006.257.11:26:15.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:15.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:26:15.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:26:15.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:26:15.21$vck44/vblo=5,709.99 2006.257.11:26:15.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.11:26:15.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.11:26:15.21#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:15.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:15.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:15.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:15.21#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:26:15.21#ibcon#first serial, iclass 24, count 0 2006.257.11:26:15.21#ibcon#enter sib2, iclass 24, count 0 2006.257.11:26:15.21#ibcon#flushed, iclass 24, count 0 2006.257.11:26:15.21#ibcon#about to write, iclass 24, count 0 2006.257.11:26:15.21#ibcon#wrote, iclass 24, count 0 2006.257.11:26:15.21#ibcon#about to read 3, iclass 24, count 0 2006.257.11:26:15.22#ibcon#read 3, iclass 24, count 0 2006.257.11:26:15.22#ibcon#about to read 4, iclass 24, count 0 2006.257.11:26:15.23#ibcon#read 4, iclass 24, count 0 2006.257.11:26:15.23#ibcon#about to read 5, iclass 24, count 0 2006.257.11:26:15.23#ibcon#read 5, iclass 24, count 0 2006.257.11:26:15.23#ibcon#about to read 6, iclass 24, count 0 2006.257.11:26:15.23#ibcon#read 6, iclass 24, count 0 2006.257.11:26:15.23#ibcon#end of sib2, iclass 24, count 0 2006.257.11:26:15.23#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:26:15.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:26:15.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:26:15.23#ibcon#*before write, iclass 24, count 0 2006.257.11:26:15.23#ibcon#enter sib2, iclass 24, count 0 2006.257.11:26:15.23#ibcon#flushed, iclass 24, count 0 2006.257.11:26:15.23#ibcon#about to write, iclass 24, count 0 2006.257.11:26:15.23#ibcon#wrote, iclass 24, count 0 2006.257.11:26:15.23#ibcon#about to read 3, iclass 24, count 0 2006.257.11:26:15.26#ibcon#read 3, iclass 24, count 0 2006.257.11:26:15.27#ibcon#about to read 4, iclass 24, count 0 2006.257.11:26:15.27#ibcon#read 4, iclass 24, count 0 2006.257.11:26:15.27#ibcon#about to read 5, iclass 24, count 0 2006.257.11:26:15.27#ibcon#read 5, iclass 24, count 0 2006.257.11:26:15.27#ibcon#about to read 6, iclass 24, count 0 2006.257.11:26:15.27#ibcon#read 6, iclass 24, count 0 2006.257.11:26:15.27#ibcon#end of sib2, iclass 24, count 0 2006.257.11:26:15.27#ibcon#*after write, iclass 24, count 0 2006.257.11:26:15.27#ibcon#*before return 0, iclass 24, count 0 2006.257.11:26:15.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:15.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:26:15.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:26:15.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:26:15.27$vck44/vb=5,4 2006.257.11:26:15.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.11:26:15.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.11:26:15.27#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:15.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:15.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:15.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:15.33#ibcon#enter wrdev, iclass 26, count 2 2006.257.11:26:15.33#ibcon#first serial, iclass 26, count 2 2006.257.11:26:15.33#ibcon#enter sib2, iclass 26, count 2 2006.257.11:26:15.33#ibcon#flushed, iclass 26, count 2 2006.257.11:26:15.33#ibcon#about to write, iclass 26, count 2 2006.257.11:26:15.33#ibcon#wrote, iclass 26, count 2 2006.257.11:26:15.33#ibcon#about to read 3, iclass 26, count 2 2006.257.11:26:15.34#ibcon#read 3, iclass 26, count 2 2006.257.11:26:15.34#ibcon#about to read 4, iclass 26, count 2 2006.257.11:26:15.35#ibcon#read 4, iclass 26, count 2 2006.257.11:26:15.35#ibcon#about to read 5, iclass 26, count 2 2006.257.11:26:15.35#ibcon#read 5, iclass 26, count 2 2006.257.11:26:15.35#ibcon#about to read 6, iclass 26, count 2 2006.257.11:26:15.35#ibcon#read 6, iclass 26, count 2 2006.257.11:26:15.35#ibcon#end of sib2, iclass 26, count 2 2006.257.11:26:15.35#ibcon#*mode == 0, iclass 26, count 2 2006.257.11:26:15.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.11:26:15.35#ibcon#[27=AT05-04\r\n] 2006.257.11:26:15.35#ibcon#*before write, iclass 26, count 2 2006.257.11:26:15.35#ibcon#enter sib2, iclass 26, count 2 2006.257.11:26:15.35#ibcon#flushed, iclass 26, count 2 2006.257.11:26:15.35#ibcon#about to write, iclass 26, count 2 2006.257.11:26:15.35#ibcon#wrote, iclass 26, count 2 2006.257.11:26:15.35#ibcon#about to read 3, iclass 26, count 2 2006.257.11:26:15.37#ibcon#read 3, iclass 26, count 2 2006.257.11:26:15.42#ibcon#about to read 4, iclass 26, count 2 2006.257.11:26:15.42#ibcon#read 4, iclass 26, count 2 2006.257.11:26:15.42#ibcon#about to read 5, iclass 26, count 2 2006.257.11:26:15.42#ibcon#read 5, iclass 26, count 2 2006.257.11:26:15.42#ibcon#about to read 6, iclass 26, count 2 2006.257.11:26:15.42#ibcon#read 6, iclass 26, count 2 2006.257.11:26:15.42#ibcon#end of sib2, iclass 26, count 2 2006.257.11:26:15.42#ibcon#*after write, iclass 26, count 2 2006.257.11:26:15.42#ibcon#*before return 0, iclass 26, count 2 2006.257.11:26:15.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:15.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:26:15.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.11:26:15.42#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:15.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:15.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:15.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:15.54#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:26:15.54#ibcon#first serial, iclass 26, count 0 2006.257.11:26:15.54#ibcon#enter sib2, iclass 26, count 0 2006.257.11:26:15.54#ibcon#flushed, iclass 26, count 0 2006.257.11:26:15.54#ibcon#about to write, iclass 26, count 0 2006.257.11:26:15.54#ibcon#wrote, iclass 26, count 0 2006.257.11:26:15.54#ibcon#about to read 3, iclass 26, count 0 2006.257.11:26:15.55#ibcon#read 3, iclass 26, count 0 2006.257.11:26:15.56#ibcon#about to read 4, iclass 26, count 0 2006.257.11:26:15.56#ibcon#read 4, iclass 26, count 0 2006.257.11:26:15.56#ibcon#about to read 5, iclass 26, count 0 2006.257.11:26:15.56#ibcon#read 5, iclass 26, count 0 2006.257.11:26:15.56#ibcon#about to read 6, iclass 26, count 0 2006.257.11:26:15.56#ibcon#read 6, iclass 26, count 0 2006.257.11:26:15.56#ibcon#end of sib2, iclass 26, count 0 2006.257.11:26:15.56#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:26:15.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:26:15.56#ibcon#[27=USB\r\n] 2006.257.11:26:15.56#ibcon#*before write, iclass 26, count 0 2006.257.11:26:15.56#ibcon#enter sib2, iclass 26, count 0 2006.257.11:26:15.56#ibcon#flushed, iclass 26, count 0 2006.257.11:26:15.56#ibcon#about to write, iclass 26, count 0 2006.257.11:26:15.56#ibcon#wrote, iclass 26, count 0 2006.257.11:26:15.56#ibcon#about to read 3, iclass 26, count 0 2006.257.11:26:15.58#ibcon#read 3, iclass 26, count 0 2006.257.11:26:15.58#ibcon#about to read 4, iclass 26, count 0 2006.257.11:26:15.59#ibcon#read 4, iclass 26, count 0 2006.257.11:26:15.59#ibcon#about to read 5, iclass 26, count 0 2006.257.11:26:15.59#ibcon#read 5, iclass 26, count 0 2006.257.11:26:15.59#ibcon#about to read 6, iclass 26, count 0 2006.257.11:26:15.59#ibcon#read 6, iclass 26, count 0 2006.257.11:26:15.59#ibcon#end of sib2, iclass 26, count 0 2006.257.11:26:15.59#ibcon#*after write, iclass 26, count 0 2006.257.11:26:15.59#ibcon#*before return 0, iclass 26, count 0 2006.257.11:26:15.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:15.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:26:15.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:26:15.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:26:15.59$vck44/vblo=6,719.99 2006.257.11:26:15.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.11:26:15.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.11:26:15.59#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:15.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:15.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:15.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:15.59#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:26:15.59#ibcon#first serial, iclass 28, count 0 2006.257.11:26:15.59#ibcon#enter sib2, iclass 28, count 0 2006.257.11:26:15.59#ibcon#flushed, iclass 28, count 0 2006.257.11:26:15.59#ibcon#about to write, iclass 28, count 0 2006.257.11:26:15.59#ibcon#wrote, iclass 28, count 0 2006.257.11:26:15.59#ibcon#about to read 3, iclass 28, count 0 2006.257.11:26:15.60#ibcon#read 3, iclass 28, count 0 2006.257.11:26:15.61#ibcon#about to read 4, iclass 28, count 0 2006.257.11:26:15.61#ibcon#read 4, iclass 28, count 0 2006.257.11:26:15.61#ibcon#about to read 5, iclass 28, count 0 2006.257.11:26:15.61#ibcon#read 5, iclass 28, count 0 2006.257.11:26:15.61#ibcon#about to read 6, iclass 28, count 0 2006.257.11:26:15.61#ibcon#read 6, iclass 28, count 0 2006.257.11:26:15.61#ibcon#end of sib2, iclass 28, count 0 2006.257.11:26:15.61#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:26:15.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:26:15.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:26:15.61#ibcon#*before write, iclass 28, count 0 2006.257.11:26:15.61#ibcon#enter sib2, iclass 28, count 0 2006.257.11:26:15.61#ibcon#flushed, iclass 28, count 0 2006.257.11:26:15.61#ibcon#about to write, iclass 28, count 0 2006.257.11:26:15.61#ibcon#wrote, iclass 28, count 0 2006.257.11:26:15.61#ibcon#about to read 3, iclass 28, count 0 2006.257.11:26:15.64#ibcon#read 3, iclass 28, count 0 2006.257.11:26:15.65#ibcon#about to read 4, iclass 28, count 0 2006.257.11:26:15.65#ibcon#read 4, iclass 28, count 0 2006.257.11:26:15.65#ibcon#about to read 5, iclass 28, count 0 2006.257.11:26:15.65#ibcon#read 5, iclass 28, count 0 2006.257.11:26:15.65#ibcon#about to read 6, iclass 28, count 0 2006.257.11:26:15.65#ibcon#read 6, iclass 28, count 0 2006.257.11:26:15.65#ibcon#end of sib2, iclass 28, count 0 2006.257.11:26:15.65#ibcon#*after write, iclass 28, count 0 2006.257.11:26:15.65#ibcon#*before return 0, iclass 28, count 0 2006.257.11:26:15.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:15.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:26:15.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:26:15.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:26:15.65$vck44/vb=6,4 2006.257.11:26:15.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.11:26:15.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.11:26:15.65#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:15.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:15.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:15.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:15.71#ibcon#enter wrdev, iclass 30, count 2 2006.257.11:26:15.71#ibcon#first serial, iclass 30, count 2 2006.257.11:26:15.71#ibcon#enter sib2, iclass 30, count 2 2006.257.11:26:15.71#ibcon#flushed, iclass 30, count 2 2006.257.11:26:15.71#ibcon#about to write, iclass 30, count 2 2006.257.11:26:15.71#ibcon#wrote, iclass 30, count 2 2006.257.11:26:15.71#ibcon#about to read 3, iclass 30, count 2 2006.257.11:26:15.72#ibcon#read 3, iclass 30, count 2 2006.257.11:26:15.73#ibcon#about to read 4, iclass 30, count 2 2006.257.11:26:15.73#ibcon#read 4, iclass 30, count 2 2006.257.11:26:15.73#ibcon#about to read 5, iclass 30, count 2 2006.257.11:26:15.73#ibcon#read 5, iclass 30, count 2 2006.257.11:26:15.73#ibcon#about to read 6, iclass 30, count 2 2006.257.11:26:15.73#ibcon#read 6, iclass 30, count 2 2006.257.11:26:15.73#ibcon#end of sib2, iclass 30, count 2 2006.257.11:26:15.73#ibcon#*mode == 0, iclass 30, count 2 2006.257.11:26:15.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.11:26:15.73#ibcon#[27=AT06-04\r\n] 2006.257.11:26:15.73#ibcon#*before write, iclass 30, count 2 2006.257.11:26:15.73#ibcon#enter sib2, iclass 30, count 2 2006.257.11:26:15.73#ibcon#flushed, iclass 30, count 2 2006.257.11:26:15.73#ibcon#about to write, iclass 30, count 2 2006.257.11:26:15.73#ibcon#wrote, iclass 30, count 2 2006.257.11:26:15.73#ibcon#about to read 3, iclass 30, count 2 2006.257.11:26:15.75#ibcon#read 3, iclass 30, count 2 2006.257.11:26:15.76#ibcon#about to read 4, iclass 30, count 2 2006.257.11:26:15.76#ibcon#read 4, iclass 30, count 2 2006.257.11:26:15.76#ibcon#about to read 5, iclass 30, count 2 2006.257.11:26:15.76#ibcon#read 5, iclass 30, count 2 2006.257.11:26:15.76#ibcon#about to read 6, iclass 30, count 2 2006.257.11:26:15.76#ibcon#read 6, iclass 30, count 2 2006.257.11:26:15.76#ibcon#end of sib2, iclass 30, count 2 2006.257.11:26:15.76#ibcon#*after write, iclass 30, count 2 2006.257.11:26:15.76#ibcon#*before return 0, iclass 30, count 2 2006.257.11:26:15.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:15.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:26:15.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.11:26:15.76#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:15.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:15.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:15.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:15.88#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:26:15.88#ibcon#first serial, iclass 30, count 0 2006.257.11:26:15.88#ibcon#enter sib2, iclass 30, count 0 2006.257.11:26:15.88#ibcon#flushed, iclass 30, count 0 2006.257.11:26:15.88#ibcon#about to write, iclass 30, count 0 2006.257.11:26:15.88#ibcon#wrote, iclass 30, count 0 2006.257.11:26:15.88#ibcon#about to read 3, iclass 30, count 0 2006.257.11:26:15.89#ibcon#read 3, iclass 30, count 0 2006.257.11:26:15.90#ibcon#about to read 4, iclass 30, count 0 2006.257.11:26:15.90#ibcon#read 4, iclass 30, count 0 2006.257.11:26:15.90#ibcon#about to read 5, iclass 30, count 0 2006.257.11:26:15.90#ibcon#read 5, iclass 30, count 0 2006.257.11:26:15.90#ibcon#about to read 6, iclass 30, count 0 2006.257.11:26:15.90#ibcon#read 6, iclass 30, count 0 2006.257.11:26:15.90#ibcon#end of sib2, iclass 30, count 0 2006.257.11:26:15.90#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:26:15.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:26:15.90#ibcon#[27=USB\r\n] 2006.257.11:26:15.90#ibcon#*before write, iclass 30, count 0 2006.257.11:26:15.90#ibcon#enter sib2, iclass 30, count 0 2006.257.11:26:15.90#ibcon#flushed, iclass 30, count 0 2006.257.11:26:15.90#ibcon#about to write, iclass 30, count 0 2006.257.11:26:15.90#ibcon#wrote, iclass 30, count 0 2006.257.11:26:15.90#ibcon#about to read 3, iclass 30, count 0 2006.257.11:26:15.92#ibcon#read 3, iclass 30, count 0 2006.257.11:26:15.93#ibcon#about to read 4, iclass 30, count 0 2006.257.11:26:15.93#ibcon#read 4, iclass 30, count 0 2006.257.11:26:15.93#ibcon#about to read 5, iclass 30, count 0 2006.257.11:26:15.93#ibcon#read 5, iclass 30, count 0 2006.257.11:26:15.93#ibcon#about to read 6, iclass 30, count 0 2006.257.11:26:15.93#ibcon#read 6, iclass 30, count 0 2006.257.11:26:15.93#ibcon#end of sib2, iclass 30, count 0 2006.257.11:26:15.93#ibcon#*after write, iclass 30, count 0 2006.257.11:26:15.93#ibcon#*before return 0, iclass 30, count 0 2006.257.11:26:15.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:15.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:26:15.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:26:15.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:26:15.93$vck44/vblo=7,734.99 2006.257.11:26:15.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.11:26:15.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.11:26:15.93#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:15.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:15.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:15.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:15.93#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:26:15.93#ibcon#first serial, iclass 32, count 0 2006.257.11:26:15.93#ibcon#enter sib2, iclass 32, count 0 2006.257.11:26:15.93#ibcon#flushed, iclass 32, count 0 2006.257.11:26:15.93#ibcon#about to write, iclass 32, count 0 2006.257.11:26:15.93#ibcon#wrote, iclass 32, count 0 2006.257.11:26:15.93#ibcon#about to read 3, iclass 32, count 0 2006.257.11:26:15.94#ibcon#read 3, iclass 32, count 0 2006.257.11:26:15.95#ibcon#about to read 4, iclass 32, count 0 2006.257.11:26:15.95#ibcon#read 4, iclass 32, count 0 2006.257.11:26:15.95#ibcon#about to read 5, iclass 32, count 0 2006.257.11:26:15.95#ibcon#read 5, iclass 32, count 0 2006.257.11:26:15.95#ibcon#about to read 6, iclass 32, count 0 2006.257.11:26:15.95#ibcon#read 6, iclass 32, count 0 2006.257.11:26:15.95#ibcon#end of sib2, iclass 32, count 0 2006.257.11:26:15.95#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:26:15.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:26:15.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:26:15.95#ibcon#*before write, iclass 32, count 0 2006.257.11:26:15.95#ibcon#enter sib2, iclass 32, count 0 2006.257.11:26:15.95#ibcon#flushed, iclass 32, count 0 2006.257.11:26:15.95#ibcon#about to write, iclass 32, count 0 2006.257.11:26:15.95#ibcon#wrote, iclass 32, count 0 2006.257.11:26:15.95#ibcon#about to read 3, iclass 32, count 0 2006.257.11:26:15.98#ibcon#read 3, iclass 32, count 0 2006.257.11:26:15.99#ibcon#about to read 4, iclass 32, count 0 2006.257.11:26:15.99#ibcon#read 4, iclass 32, count 0 2006.257.11:26:15.99#ibcon#about to read 5, iclass 32, count 0 2006.257.11:26:15.99#ibcon#read 5, iclass 32, count 0 2006.257.11:26:15.99#ibcon#about to read 6, iclass 32, count 0 2006.257.11:26:15.99#ibcon#read 6, iclass 32, count 0 2006.257.11:26:15.99#ibcon#end of sib2, iclass 32, count 0 2006.257.11:26:15.99#ibcon#*after write, iclass 32, count 0 2006.257.11:26:15.99#ibcon#*before return 0, iclass 32, count 0 2006.257.11:26:15.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:15.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:26:15.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:26:15.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:26:15.99$vck44/vb=7,4 2006.257.11:26:15.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.11:26:15.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.11:26:15.99#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:15.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:16.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:16.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:16.05#ibcon#enter wrdev, iclass 34, count 2 2006.257.11:26:16.05#ibcon#first serial, iclass 34, count 2 2006.257.11:26:16.05#ibcon#enter sib2, iclass 34, count 2 2006.257.11:26:16.05#ibcon#flushed, iclass 34, count 2 2006.257.11:26:16.05#ibcon#about to write, iclass 34, count 2 2006.257.11:26:16.05#ibcon#wrote, iclass 34, count 2 2006.257.11:26:16.05#ibcon#about to read 3, iclass 34, count 2 2006.257.11:26:16.06#ibcon#read 3, iclass 34, count 2 2006.257.11:26:16.07#ibcon#about to read 4, iclass 34, count 2 2006.257.11:26:16.07#ibcon#read 4, iclass 34, count 2 2006.257.11:26:16.07#ibcon#about to read 5, iclass 34, count 2 2006.257.11:26:16.07#ibcon#read 5, iclass 34, count 2 2006.257.11:26:16.07#ibcon#about to read 6, iclass 34, count 2 2006.257.11:26:16.07#ibcon#read 6, iclass 34, count 2 2006.257.11:26:16.07#ibcon#end of sib2, iclass 34, count 2 2006.257.11:26:16.07#ibcon#*mode == 0, iclass 34, count 2 2006.257.11:26:16.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.11:26:16.07#ibcon#[27=AT07-04\r\n] 2006.257.11:26:16.07#ibcon#*before write, iclass 34, count 2 2006.257.11:26:16.07#ibcon#enter sib2, iclass 34, count 2 2006.257.11:26:16.07#ibcon#flushed, iclass 34, count 2 2006.257.11:26:16.07#ibcon#about to write, iclass 34, count 2 2006.257.11:26:16.07#ibcon#wrote, iclass 34, count 2 2006.257.11:26:16.07#ibcon#about to read 3, iclass 34, count 2 2006.257.11:26:16.09#ibcon#read 3, iclass 34, count 2 2006.257.11:26:16.09#ibcon#about to read 4, iclass 34, count 2 2006.257.11:26:16.10#ibcon#read 4, iclass 34, count 2 2006.257.11:26:16.10#ibcon#about to read 5, iclass 34, count 2 2006.257.11:26:16.10#ibcon#read 5, iclass 34, count 2 2006.257.11:26:16.10#ibcon#about to read 6, iclass 34, count 2 2006.257.11:26:16.10#ibcon#read 6, iclass 34, count 2 2006.257.11:26:16.10#ibcon#end of sib2, iclass 34, count 2 2006.257.11:26:16.10#ibcon#*after write, iclass 34, count 2 2006.257.11:26:16.10#ibcon#*before return 0, iclass 34, count 2 2006.257.11:26:16.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:16.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:26:16.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.11:26:16.10#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:16.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:16.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:16.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:16.22#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:26:16.22#ibcon#first serial, iclass 34, count 0 2006.257.11:26:16.22#ibcon#enter sib2, iclass 34, count 0 2006.257.11:26:16.22#ibcon#flushed, iclass 34, count 0 2006.257.11:26:16.22#ibcon#about to write, iclass 34, count 0 2006.257.11:26:16.22#ibcon#wrote, iclass 34, count 0 2006.257.11:26:16.22#ibcon#about to read 3, iclass 34, count 0 2006.257.11:26:16.23#ibcon#read 3, iclass 34, count 0 2006.257.11:26:16.24#ibcon#about to read 4, iclass 34, count 0 2006.257.11:26:16.24#ibcon#read 4, iclass 34, count 0 2006.257.11:26:16.24#ibcon#about to read 5, iclass 34, count 0 2006.257.11:26:16.24#ibcon#read 5, iclass 34, count 0 2006.257.11:26:16.24#ibcon#about to read 6, iclass 34, count 0 2006.257.11:26:16.24#ibcon#read 6, iclass 34, count 0 2006.257.11:26:16.24#ibcon#end of sib2, iclass 34, count 0 2006.257.11:26:16.24#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:26:16.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:26:16.24#ibcon#[27=USB\r\n] 2006.257.11:26:16.24#ibcon#*before write, iclass 34, count 0 2006.257.11:26:16.24#ibcon#enter sib2, iclass 34, count 0 2006.257.11:26:16.24#ibcon#flushed, iclass 34, count 0 2006.257.11:26:16.24#ibcon#about to write, iclass 34, count 0 2006.257.11:26:16.24#ibcon#wrote, iclass 34, count 0 2006.257.11:26:16.24#ibcon#about to read 3, iclass 34, count 0 2006.257.11:26:16.26#ibcon#read 3, iclass 34, count 0 2006.257.11:26:16.27#ibcon#about to read 4, iclass 34, count 0 2006.257.11:26:16.27#ibcon#read 4, iclass 34, count 0 2006.257.11:26:16.27#ibcon#about to read 5, iclass 34, count 0 2006.257.11:26:16.27#ibcon#read 5, iclass 34, count 0 2006.257.11:26:16.27#ibcon#about to read 6, iclass 34, count 0 2006.257.11:26:16.27#ibcon#read 6, iclass 34, count 0 2006.257.11:26:16.27#ibcon#end of sib2, iclass 34, count 0 2006.257.11:26:16.27#ibcon#*after write, iclass 34, count 0 2006.257.11:26:16.27#ibcon#*before return 0, iclass 34, count 0 2006.257.11:26:16.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:16.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:26:16.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:26:16.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:26:16.27$vck44/vblo=8,744.99 2006.257.11:26:16.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.11:26:16.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.11:26:16.27#ibcon#ireg 17 cls_cnt 0 2006.257.11:26:16.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:16.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:16.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:16.27#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:26:16.27#ibcon#first serial, iclass 36, count 0 2006.257.11:26:16.27#ibcon#enter sib2, iclass 36, count 0 2006.257.11:26:16.27#ibcon#flushed, iclass 36, count 0 2006.257.11:26:16.27#ibcon#about to write, iclass 36, count 0 2006.257.11:26:16.27#ibcon#wrote, iclass 36, count 0 2006.257.11:26:16.27#ibcon#about to read 3, iclass 36, count 0 2006.257.11:26:16.28#ibcon#read 3, iclass 36, count 0 2006.257.11:26:16.28#ibcon#about to read 4, iclass 36, count 0 2006.257.11:26:16.29#ibcon#read 4, iclass 36, count 0 2006.257.11:26:16.29#ibcon#about to read 5, iclass 36, count 0 2006.257.11:26:16.29#ibcon#read 5, iclass 36, count 0 2006.257.11:26:16.29#ibcon#about to read 6, iclass 36, count 0 2006.257.11:26:16.29#ibcon#read 6, iclass 36, count 0 2006.257.11:26:16.29#ibcon#end of sib2, iclass 36, count 0 2006.257.11:26:16.29#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:26:16.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:26:16.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:26:16.29#ibcon#*before write, iclass 36, count 0 2006.257.11:26:16.29#ibcon#enter sib2, iclass 36, count 0 2006.257.11:26:16.29#ibcon#flushed, iclass 36, count 0 2006.257.11:26:16.29#ibcon#about to write, iclass 36, count 0 2006.257.11:26:16.29#ibcon#wrote, iclass 36, count 0 2006.257.11:26:16.29#ibcon#about to read 3, iclass 36, count 0 2006.257.11:26:16.32#ibcon#read 3, iclass 36, count 0 2006.257.11:26:16.33#ibcon#about to read 4, iclass 36, count 0 2006.257.11:26:16.33#ibcon#read 4, iclass 36, count 0 2006.257.11:26:16.33#ibcon#about to read 5, iclass 36, count 0 2006.257.11:26:16.33#ibcon#read 5, iclass 36, count 0 2006.257.11:26:16.33#ibcon#about to read 6, iclass 36, count 0 2006.257.11:26:16.33#ibcon#read 6, iclass 36, count 0 2006.257.11:26:16.33#ibcon#end of sib2, iclass 36, count 0 2006.257.11:26:16.33#ibcon#*after write, iclass 36, count 0 2006.257.11:26:16.33#ibcon#*before return 0, iclass 36, count 0 2006.257.11:26:16.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:16.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:26:16.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:26:16.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:26:16.33$vck44/vb=8,4 2006.257.11:26:16.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.11:26:16.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.11:26:16.33#ibcon#ireg 11 cls_cnt 2 2006.257.11:26:16.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:16.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:16.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:16.39#ibcon#enter wrdev, iclass 38, count 2 2006.257.11:26:16.39#ibcon#first serial, iclass 38, count 2 2006.257.11:26:16.39#ibcon#enter sib2, iclass 38, count 2 2006.257.11:26:16.39#ibcon#flushed, iclass 38, count 2 2006.257.11:26:16.39#ibcon#about to write, iclass 38, count 2 2006.257.11:26:16.39#ibcon#wrote, iclass 38, count 2 2006.257.11:26:16.39#ibcon#about to read 3, iclass 38, count 2 2006.257.11:26:16.40#ibcon#read 3, iclass 38, count 2 2006.257.11:26:16.41#ibcon#about to read 4, iclass 38, count 2 2006.257.11:26:16.41#ibcon#read 4, iclass 38, count 2 2006.257.11:26:16.41#ibcon#about to read 5, iclass 38, count 2 2006.257.11:26:16.41#ibcon#read 5, iclass 38, count 2 2006.257.11:26:16.41#ibcon#about to read 6, iclass 38, count 2 2006.257.11:26:16.41#ibcon#read 6, iclass 38, count 2 2006.257.11:26:16.41#ibcon#end of sib2, iclass 38, count 2 2006.257.11:26:16.41#ibcon#*mode == 0, iclass 38, count 2 2006.257.11:26:16.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.11:26:16.41#ibcon#[27=AT08-04\r\n] 2006.257.11:26:16.41#ibcon#*before write, iclass 38, count 2 2006.257.11:26:16.41#ibcon#enter sib2, iclass 38, count 2 2006.257.11:26:16.41#ibcon#flushed, iclass 38, count 2 2006.257.11:26:16.41#ibcon#about to write, iclass 38, count 2 2006.257.11:26:16.41#ibcon#wrote, iclass 38, count 2 2006.257.11:26:16.41#ibcon#about to read 3, iclass 38, count 2 2006.257.11:26:16.43#ibcon#read 3, iclass 38, count 2 2006.257.11:26:16.43#ibcon#about to read 4, iclass 38, count 2 2006.257.11:26:16.44#ibcon#read 4, iclass 38, count 2 2006.257.11:26:16.44#ibcon#about to read 5, iclass 38, count 2 2006.257.11:26:16.44#ibcon#read 5, iclass 38, count 2 2006.257.11:26:16.44#ibcon#about to read 6, iclass 38, count 2 2006.257.11:26:16.44#ibcon#read 6, iclass 38, count 2 2006.257.11:26:16.44#ibcon#end of sib2, iclass 38, count 2 2006.257.11:26:16.44#ibcon#*after write, iclass 38, count 2 2006.257.11:26:16.48#ibcon#*before return 0, iclass 38, count 2 2006.257.11:26:16.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:16.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:26:16.48#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.11:26:16.48#ibcon#ireg 7 cls_cnt 0 2006.257.11:26:16.48#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:16.59#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:16.60#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:16.60#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:26:16.60#ibcon#first serial, iclass 38, count 0 2006.257.11:26:16.60#ibcon#enter sib2, iclass 38, count 0 2006.257.11:26:16.60#ibcon#flushed, iclass 38, count 0 2006.257.11:26:16.60#ibcon#about to write, iclass 38, count 0 2006.257.11:26:16.60#ibcon#wrote, iclass 38, count 0 2006.257.11:26:16.60#ibcon#about to read 3, iclass 38, count 0 2006.257.11:26:16.61#ibcon#read 3, iclass 38, count 0 2006.257.11:26:16.62#ibcon#about to read 4, iclass 38, count 0 2006.257.11:26:16.62#ibcon#read 4, iclass 38, count 0 2006.257.11:26:16.62#ibcon#about to read 5, iclass 38, count 0 2006.257.11:26:16.62#ibcon#read 5, iclass 38, count 0 2006.257.11:26:16.62#ibcon#about to read 6, iclass 38, count 0 2006.257.11:26:16.62#ibcon#read 6, iclass 38, count 0 2006.257.11:26:16.62#ibcon#end of sib2, iclass 38, count 0 2006.257.11:26:16.62#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:26:16.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:26:16.62#ibcon#[27=USB\r\n] 2006.257.11:26:16.62#ibcon#*before write, iclass 38, count 0 2006.257.11:26:16.62#ibcon#enter sib2, iclass 38, count 0 2006.257.11:26:16.62#ibcon#flushed, iclass 38, count 0 2006.257.11:26:16.62#ibcon#about to write, iclass 38, count 0 2006.257.11:26:16.62#ibcon#wrote, iclass 38, count 0 2006.257.11:26:16.62#ibcon#about to read 3, iclass 38, count 0 2006.257.11:26:16.64#ibcon#read 3, iclass 38, count 0 2006.257.11:26:16.64#ibcon#about to read 4, iclass 38, count 0 2006.257.11:26:16.64#ibcon#read 4, iclass 38, count 0 2006.257.11:26:16.65#ibcon#about to read 5, iclass 38, count 0 2006.257.11:26:16.65#ibcon#read 5, iclass 38, count 0 2006.257.11:26:16.65#ibcon#about to read 6, iclass 38, count 0 2006.257.11:26:16.65#ibcon#read 6, iclass 38, count 0 2006.257.11:26:16.65#ibcon#end of sib2, iclass 38, count 0 2006.257.11:26:16.65#ibcon#*after write, iclass 38, count 0 2006.257.11:26:16.65#ibcon#*before return 0, iclass 38, count 0 2006.257.11:26:16.65#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:16.65#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:26:16.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:26:16.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:26:16.65$vck44/vabw=wide 2006.257.11:26:16.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.11:26:16.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.11:26:16.65#ibcon#ireg 8 cls_cnt 0 2006.257.11:26:16.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:16.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:16.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:16.65#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:26:16.65#ibcon#first serial, iclass 40, count 0 2006.257.11:26:16.65#ibcon#enter sib2, iclass 40, count 0 2006.257.11:26:16.65#ibcon#flushed, iclass 40, count 0 2006.257.11:26:16.65#ibcon#about to write, iclass 40, count 0 2006.257.11:26:16.65#ibcon#wrote, iclass 40, count 0 2006.257.11:26:16.65#ibcon#about to read 3, iclass 40, count 0 2006.257.11:26:16.66#ibcon#read 3, iclass 40, count 0 2006.257.11:26:16.67#ibcon#about to read 4, iclass 40, count 0 2006.257.11:26:16.67#ibcon#read 4, iclass 40, count 0 2006.257.11:26:16.67#ibcon#about to read 5, iclass 40, count 0 2006.257.11:26:16.67#ibcon#read 5, iclass 40, count 0 2006.257.11:26:16.67#ibcon#about to read 6, iclass 40, count 0 2006.257.11:26:16.67#ibcon#read 6, iclass 40, count 0 2006.257.11:26:16.67#ibcon#end of sib2, iclass 40, count 0 2006.257.11:26:16.67#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:26:16.67#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:26:16.67#ibcon#[25=BW32\r\n] 2006.257.11:26:16.67#ibcon#*before write, iclass 40, count 0 2006.257.11:26:16.67#ibcon#enter sib2, iclass 40, count 0 2006.257.11:26:16.67#ibcon#flushed, iclass 40, count 0 2006.257.11:26:16.67#ibcon#about to write, iclass 40, count 0 2006.257.11:26:16.67#ibcon#wrote, iclass 40, count 0 2006.257.11:26:16.67#ibcon#about to read 3, iclass 40, count 0 2006.257.11:26:16.69#ibcon#read 3, iclass 40, count 0 2006.257.11:26:16.70#ibcon#about to read 4, iclass 40, count 0 2006.257.11:26:16.70#ibcon#read 4, iclass 40, count 0 2006.257.11:26:16.70#ibcon#about to read 5, iclass 40, count 0 2006.257.11:26:16.70#ibcon#read 5, iclass 40, count 0 2006.257.11:26:16.70#ibcon#about to read 6, iclass 40, count 0 2006.257.11:26:16.70#ibcon#read 6, iclass 40, count 0 2006.257.11:26:16.70#ibcon#end of sib2, iclass 40, count 0 2006.257.11:26:16.70#ibcon#*after write, iclass 40, count 0 2006.257.11:26:16.70#ibcon#*before return 0, iclass 40, count 0 2006.257.11:26:16.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:16.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:26:16.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:26:16.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:26:16.70$vck44/vbbw=wide 2006.257.11:26:16.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.11:26:16.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.11:26:16.70#ibcon#ireg 8 cls_cnt 0 2006.257.11:26:16.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:26:16.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:26:16.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:26:16.77#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:26:16.77#ibcon#first serial, iclass 4, count 0 2006.257.11:26:16.77#ibcon#enter sib2, iclass 4, count 0 2006.257.11:26:16.77#ibcon#flushed, iclass 4, count 0 2006.257.11:26:16.77#ibcon#about to write, iclass 4, count 0 2006.257.11:26:16.77#ibcon#wrote, iclass 4, count 0 2006.257.11:26:16.77#ibcon#about to read 3, iclass 4, count 0 2006.257.11:26:16.78#ibcon#read 3, iclass 4, count 0 2006.257.11:26:16.79#ibcon#about to read 4, iclass 4, count 0 2006.257.11:26:16.79#ibcon#read 4, iclass 4, count 0 2006.257.11:26:16.79#ibcon#about to read 5, iclass 4, count 0 2006.257.11:26:16.79#ibcon#read 5, iclass 4, count 0 2006.257.11:26:16.79#ibcon#about to read 6, iclass 4, count 0 2006.257.11:26:16.79#ibcon#read 6, iclass 4, count 0 2006.257.11:26:16.79#ibcon#end of sib2, iclass 4, count 0 2006.257.11:26:16.79#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:26:16.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:26:16.79#ibcon#[27=BW32\r\n] 2006.257.11:26:16.79#ibcon#*before write, iclass 4, count 0 2006.257.11:26:16.79#ibcon#enter sib2, iclass 4, count 0 2006.257.11:26:16.79#ibcon#flushed, iclass 4, count 0 2006.257.11:26:16.79#ibcon#about to write, iclass 4, count 0 2006.257.11:26:16.79#ibcon#wrote, iclass 4, count 0 2006.257.11:26:16.79#ibcon#about to read 3, iclass 4, count 0 2006.257.11:26:16.81#ibcon#read 3, iclass 4, count 0 2006.257.11:26:16.82#ibcon#about to read 4, iclass 4, count 0 2006.257.11:26:16.82#ibcon#read 4, iclass 4, count 0 2006.257.11:26:16.82#ibcon#about to read 5, iclass 4, count 0 2006.257.11:26:16.82#ibcon#read 5, iclass 4, count 0 2006.257.11:26:16.82#ibcon#about to read 6, iclass 4, count 0 2006.257.11:26:16.82#ibcon#read 6, iclass 4, count 0 2006.257.11:26:16.82#ibcon#end of sib2, iclass 4, count 0 2006.257.11:26:16.82#ibcon#*after write, iclass 4, count 0 2006.257.11:26:16.82#ibcon#*before return 0, iclass 4, count 0 2006.257.11:26:16.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:26:16.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:26:16.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:26:16.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:26:16.82$setupk4/ifdk4 2006.257.11:26:16.82$ifdk4/lo= 2006.257.11:26:16.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:26:16.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:26:16.82$ifdk4/patch= 2006.257.11:26:16.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:26:16.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:26:16.82$setupk4/!*+20s 2006.257.11:26:21.94#abcon#<5=/14 1.1 2.5 18.23 971013.9\r\n> 2006.257.11:26:21.96#abcon#{5=INTERFACE CLEAR} 2006.257.11:26:22.02#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:26:29.13#trakl#Source acquired 2006.257.11:26:30.14#flagr#flagr/antenna,acquired 2006.257.11:26:31.20$setupk4/"tpicd 2006.257.11:26:31.20$setupk4/echo=off 2006.257.11:26:31.20$setupk4/xlog=off 2006.257.11:26:31.20:!2006.257.11:27:17 2006.257.11:27:17.02:preob 2006.257.11:27:18.15/onsource/TRACKING 2006.257.11:27:18.15:!2006.257.11:27:27 2006.257.11:27:27.02:"tape 2006.257.11:27:27.02:"st=record 2006.257.11:27:27.02:data_valid=on 2006.257.11:27:27.02:midob 2006.257.11:27:28.15/onsource/TRACKING 2006.257.11:27:28.15/wx/18.22,1013.9,97 2006.257.11:27:28.26/cable/+6.4771E-03 2006.257.11:27:29.35/va/01,08,usb,yes,33,35 2006.257.11:27:29.35/va/02,07,usb,yes,36,36 2006.257.11:27:29.35/va/03,08,usb,yes,32,34 2006.257.11:27:29.35/va/04,07,usb,yes,37,38 2006.257.11:27:29.35/va/05,04,usb,yes,33,33 2006.257.11:27:29.35/va/06,04,usb,yes,36,36 2006.257.11:27:29.35/va/07,04,usb,yes,37,38 2006.257.11:27:29.35/va/08,04,usb,yes,31,38 2006.257.11:27:29.58/valo/01,524.99,yes,locked 2006.257.11:27:29.58/valo/02,534.99,yes,locked 2006.257.11:27:29.58/valo/03,564.99,yes,locked 2006.257.11:27:29.58/valo/04,624.99,yes,locked 2006.257.11:27:29.58/valo/05,734.99,yes,locked 2006.257.11:27:29.58/valo/06,814.99,yes,locked 2006.257.11:27:29.58/valo/07,864.99,yes,locked 2006.257.11:27:29.58/valo/08,884.99,yes,locked 2006.257.11:27:30.67/vb/01,04,usb,yes,32,30 2006.257.11:27:30.67/vb/02,05,usb,yes,31,30 2006.257.11:27:30.67/vb/03,04,usb,yes,31,35 2006.257.11:27:30.67/vb/04,05,usb,yes,32,31 2006.257.11:27:30.67/vb/05,04,usb,yes,28,31 2006.257.11:27:30.67/vb/06,04,usb,yes,33,29 2006.257.11:27:30.67/vb/07,04,usb,yes,33,33 2006.257.11:27:30.67/vb/08,04,usb,yes,30,34 2006.257.11:27:30.90/vblo/01,629.99,yes,locked 2006.257.11:27:30.90/vblo/02,634.99,yes,locked 2006.257.11:27:30.90/vblo/03,649.99,yes,locked 2006.257.11:27:30.90/vblo/04,679.99,yes,locked 2006.257.11:27:30.90/vblo/05,709.99,yes,locked 2006.257.11:27:30.90/vblo/06,719.99,yes,locked 2006.257.11:27:30.90/vblo/07,734.99,yes,locked 2006.257.11:27:30.90/vblo/08,744.99,yes,locked 2006.257.11:27:31.05/vabw/8 2006.257.11:27:31.20/vbbw/8 2006.257.11:27:31.29/xfe/off,on,15.2 2006.257.11:27:31.66/ifatt/23,28,28,28 2006.257.11:27:32.07/fmout-gps/S +4.60E-07 2006.257.11:27:32.11:!2006.257.11:28:07 2006.257.11:28:07.02:data_valid=off 2006.257.11:28:07.02:"et 2006.257.11:28:07.02:!+3s 2006.257.11:28:10.04:"tape 2006.257.11:28:10.04:postob 2006.257.11:28:10.10/cable/+6.4768E-03 2006.257.11:28:10.11/wx/18.21,1014.0,97 2006.257.11:28:10.16/fmout-gps/S +4.60E-07 2006.257.11:28:10.17:scan_name=257-1132,jd0609,70 2006.257.11:28:10.17:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.11:28:11.15#flagr#flagr/antenna,new-source 2006.257.11:28:11.15:checkk5 2006.257.11:28:11.59/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:28:12.01/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:28:12.41/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:28:12.81/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:28:13.19/chk_obsdata//k5ts1/T2571127??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.11:28:13.57/chk_obsdata//k5ts2/T2571127??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.11:28:13.99/chk_obsdata//k5ts3/T2571127??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.11:28:14.39/chk_obsdata//k5ts4/T2571127??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.11:28:15.11/k5log//k5ts1_log_newline 2006.257.11:28:15.83/k5log//k5ts2_log_newline 2006.257.11:28:16.54/k5log//k5ts3_log_newline 2006.257.11:28:17.24/k5log//k5ts4_log_newline 2006.257.11:28:17.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:28:17.27:setupk4=1 2006.257.11:28:17.27$setupk4/echo=on 2006.257.11:28:17.27$setupk4/pcalon 2006.257.11:28:17.27$pcalon/"no phase cal control is implemented here 2006.257.11:28:17.27$setupk4/"tpicd=stop 2006.257.11:28:17.27$setupk4/"rec=synch_on 2006.257.11:28:17.27$setupk4/"rec_mode=128 2006.257.11:28:17.27$setupk4/!* 2006.257.11:28:17.27$setupk4/recpk4 2006.257.11:28:17.27$recpk4/recpatch= 2006.257.11:28:17.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:28:17.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:28:17.27$setupk4/vck44 2006.257.11:28:17.27$vck44/valo=1,524.99 2006.257.11:28:17.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.11:28:17.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.11:28:17.27#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:17.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:17.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:17.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:17.27#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:28:17.27#ibcon#first serial, iclass 23, count 0 2006.257.11:28:17.27#ibcon#enter sib2, iclass 23, count 0 2006.257.11:28:17.27#ibcon#flushed, iclass 23, count 0 2006.257.11:28:17.27#ibcon#about to write, iclass 23, count 0 2006.257.11:28:17.27#ibcon#wrote, iclass 23, count 0 2006.257.11:28:17.27#ibcon#about to read 3, iclass 23, count 0 2006.257.11:28:17.28#ibcon#read 3, iclass 23, count 0 2006.257.11:28:17.28#ibcon#about to read 4, iclass 23, count 0 2006.257.11:28:17.28#ibcon#read 4, iclass 23, count 0 2006.257.11:28:17.28#ibcon#about to read 5, iclass 23, count 0 2006.257.11:28:17.28#ibcon#read 5, iclass 23, count 0 2006.257.11:28:17.28#ibcon#about to read 6, iclass 23, count 0 2006.257.11:28:17.28#ibcon#read 6, iclass 23, count 0 2006.257.11:28:17.28#ibcon#end of sib2, iclass 23, count 0 2006.257.11:28:17.28#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:28:17.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:28:17.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:28:17.28#ibcon#*before write, iclass 23, count 0 2006.257.11:28:17.28#ibcon#enter sib2, iclass 23, count 0 2006.257.11:28:17.28#ibcon#flushed, iclass 23, count 0 2006.257.11:28:17.28#ibcon#about to write, iclass 23, count 0 2006.257.11:28:17.28#ibcon#wrote, iclass 23, count 0 2006.257.11:28:17.28#ibcon#about to read 3, iclass 23, count 0 2006.257.11:28:17.33#ibcon#read 3, iclass 23, count 0 2006.257.11:28:17.33#ibcon#about to read 4, iclass 23, count 0 2006.257.11:28:17.33#ibcon#read 4, iclass 23, count 0 2006.257.11:28:17.33#ibcon#about to read 5, iclass 23, count 0 2006.257.11:28:17.33#ibcon#read 5, iclass 23, count 0 2006.257.11:28:17.33#ibcon#about to read 6, iclass 23, count 0 2006.257.11:28:17.33#ibcon#read 6, iclass 23, count 0 2006.257.11:28:17.33#ibcon#end of sib2, iclass 23, count 0 2006.257.11:28:17.33#ibcon#*after write, iclass 23, count 0 2006.257.11:28:17.33#ibcon#*before return 0, iclass 23, count 0 2006.257.11:28:17.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:17.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:17.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:28:17.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:28:17.33$vck44/va=1,8 2006.257.11:28:17.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.11:28:17.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.11:28:17.34#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:17.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:17.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:17.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:17.34#ibcon#enter wrdev, iclass 25, count 2 2006.257.11:28:17.34#ibcon#first serial, iclass 25, count 2 2006.257.11:28:17.34#ibcon#enter sib2, iclass 25, count 2 2006.257.11:28:17.34#ibcon#flushed, iclass 25, count 2 2006.257.11:28:17.34#ibcon#about to write, iclass 25, count 2 2006.257.11:28:17.34#ibcon#wrote, iclass 25, count 2 2006.257.11:28:17.34#ibcon#about to read 3, iclass 25, count 2 2006.257.11:28:17.35#ibcon#read 3, iclass 25, count 2 2006.257.11:28:17.35#ibcon#about to read 4, iclass 25, count 2 2006.257.11:28:17.35#ibcon#read 4, iclass 25, count 2 2006.257.11:28:17.35#ibcon#about to read 5, iclass 25, count 2 2006.257.11:28:17.35#ibcon#read 5, iclass 25, count 2 2006.257.11:28:17.35#ibcon#about to read 6, iclass 25, count 2 2006.257.11:28:17.35#ibcon#read 6, iclass 25, count 2 2006.257.11:28:17.35#ibcon#end of sib2, iclass 25, count 2 2006.257.11:28:17.35#ibcon#*mode == 0, iclass 25, count 2 2006.257.11:28:17.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.11:28:17.35#ibcon#[25=AT01-08\r\n] 2006.257.11:28:17.35#ibcon#*before write, iclass 25, count 2 2006.257.11:28:17.35#ibcon#enter sib2, iclass 25, count 2 2006.257.11:28:17.35#ibcon#flushed, iclass 25, count 2 2006.257.11:28:17.35#ibcon#about to write, iclass 25, count 2 2006.257.11:28:17.35#ibcon#wrote, iclass 25, count 2 2006.257.11:28:17.35#ibcon#about to read 3, iclass 25, count 2 2006.257.11:28:17.38#ibcon#read 3, iclass 25, count 2 2006.257.11:28:17.38#ibcon#about to read 4, iclass 25, count 2 2006.257.11:28:17.38#ibcon#read 4, iclass 25, count 2 2006.257.11:28:17.38#ibcon#about to read 5, iclass 25, count 2 2006.257.11:28:17.38#ibcon#read 5, iclass 25, count 2 2006.257.11:28:17.38#ibcon#about to read 6, iclass 25, count 2 2006.257.11:28:17.38#ibcon#read 6, iclass 25, count 2 2006.257.11:28:17.38#ibcon#end of sib2, iclass 25, count 2 2006.257.11:28:17.38#ibcon#*after write, iclass 25, count 2 2006.257.11:28:17.38#ibcon#*before return 0, iclass 25, count 2 2006.257.11:28:17.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:17.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:17.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.11:28:17.38#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:17.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:17.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:17.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:17.50#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:28:17.50#ibcon#first serial, iclass 25, count 0 2006.257.11:28:17.50#ibcon#enter sib2, iclass 25, count 0 2006.257.11:28:17.50#ibcon#flushed, iclass 25, count 0 2006.257.11:28:17.50#ibcon#about to write, iclass 25, count 0 2006.257.11:28:17.50#ibcon#wrote, iclass 25, count 0 2006.257.11:28:17.50#ibcon#about to read 3, iclass 25, count 0 2006.257.11:28:17.52#ibcon#read 3, iclass 25, count 0 2006.257.11:28:17.52#ibcon#about to read 4, iclass 25, count 0 2006.257.11:28:17.52#ibcon#read 4, iclass 25, count 0 2006.257.11:28:17.52#ibcon#about to read 5, iclass 25, count 0 2006.257.11:28:17.52#ibcon#read 5, iclass 25, count 0 2006.257.11:28:17.52#ibcon#about to read 6, iclass 25, count 0 2006.257.11:28:17.52#ibcon#read 6, iclass 25, count 0 2006.257.11:28:17.52#ibcon#end of sib2, iclass 25, count 0 2006.257.11:28:17.52#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:28:17.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:28:17.52#ibcon#[25=USB\r\n] 2006.257.11:28:17.52#ibcon#*before write, iclass 25, count 0 2006.257.11:28:17.52#ibcon#enter sib2, iclass 25, count 0 2006.257.11:28:17.52#ibcon#flushed, iclass 25, count 0 2006.257.11:28:17.52#ibcon#about to write, iclass 25, count 0 2006.257.11:28:17.52#ibcon#wrote, iclass 25, count 0 2006.257.11:28:17.52#ibcon#about to read 3, iclass 25, count 0 2006.257.11:28:17.55#ibcon#read 3, iclass 25, count 0 2006.257.11:28:17.55#ibcon#about to read 4, iclass 25, count 0 2006.257.11:28:17.55#ibcon#read 4, iclass 25, count 0 2006.257.11:28:17.55#ibcon#about to read 5, iclass 25, count 0 2006.257.11:28:17.55#ibcon#read 5, iclass 25, count 0 2006.257.11:28:17.55#ibcon#about to read 6, iclass 25, count 0 2006.257.11:28:17.55#ibcon#read 6, iclass 25, count 0 2006.257.11:28:17.55#ibcon#end of sib2, iclass 25, count 0 2006.257.11:28:17.55#ibcon#*after write, iclass 25, count 0 2006.257.11:28:17.55#ibcon#*before return 0, iclass 25, count 0 2006.257.11:28:17.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:17.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:17.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:28:17.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:28:17.55$vck44/valo=2,534.99 2006.257.11:28:17.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.11:28:17.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.11:28:17.56#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:17.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:17.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:17.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:17.56#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:28:17.56#ibcon#first serial, iclass 27, count 0 2006.257.11:28:17.56#ibcon#enter sib2, iclass 27, count 0 2006.257.11:28:17.56#ibcon#flushed, iclass 27, count 0 2006.257.11:28:17.56#ibcon#about to write, iclass 27, count 0 2006.257.11:28:17.56#ibcon#wrote, iclass 27, count 0 2006.257.11:28:17.56#ibcon#about to read 3, iclass 27, count 0 2006.257.11:28:17.57#ibcon#read 3, iclass 27, count 0 2006.257.11:28:17.57#ibcon#about to read 4, iclass 27, count 0 2006.257.11:28:17.57#ibcon#read 4, iclass 27, count 0 2006.257.11:28:17.57#ibcon#about to read 5, iclass 27, count 0 2006.257.11:28:17.57#ibcon#read 5, iclass 27, count 0 2006.257.11:28:17.57#ibcon#about to read 6, iclass 27, count 0 2006.257.11:28:17.57#ibcon#read 6, iclass 27, count 0 2006.257.11:28:17.57#ibcon#end of sib2, iclass 27, count 0 2006.257.11:28:17.57#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:28:17.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:28:17.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:28:17.57#ibcon#*before write, iclass 27, count 0 2006.257.11:28:17.57#ibcon#enter sib2, iclass 27, count 0 2006.257.11:28:17.57#ibcon#flushed, iclass 27, count 0 2006.257.11:28:17.57#ibcon#about to write, iclass 27, count 0 2006.257.11:28:17.57#ibcon#wrote, iclass 27, count 0 2006.257.11:28:17.57#ibcon#about to read 3, iclass 27, count 0 2006.257.11:28:17.61#ibcon#read 3, iclass 27, count 0 2006.257.11:28:17.61#ibcon#about to read 4, iclass 27, count 0 2006.257.11:28:17.61#ibcon#read 4, iclass 27, count 0 2006.257.11:28:17.61#ibcon#about to read 5, iclass 27, count 0 2006.257.11:28:17.61#ibcon#read 5, iclass 27, count 0 2006.257.11:28:17.61#ibcon#about to read 6, iclass 27, count 0 2006.257.11:28:17.61#ibcon#read 6, iclass 27, count 0 2006.257.11:28:17.61#ibcon#end of sib2, iclass 27, count 0 2006.257.11:28:17.61#ibcon#*after write, iclass 27, count 0 2006.257.11:28:17.61#ibcon#*before return 0, iclass 27, count 0 2006.257.11:28:17.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:17.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:17.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:28:17.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:28:17.61$vck44/va=2,7 2006.257.11:28:17.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.11:28:17.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.11:28:17.62#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:17.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:17.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:17.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:17.66#ibcon#enter wrdev, iclass 29, count 2 2006.257.11:28:17.66#ibcon#first serial, iclass 29, count 2 2006.257.11:28:17.66#ibcon#enter sib2, iclass 29, count 2 2006.257.11:28:17.66#ibcon#flushed, iclass 29, count 2 2006.257.11:28:17.66#ibcon#about to write, iclass 29, count 2 2006.257.11:28:17.66#ibcon#wrote, iclass 29, count 2 2006.257.11:28:17.66#ibcon#about to read 3, iclass 29, count 2 2006.257.11:28:17.68#ibcon#read 3, iclass 29, count 2 2006.257.11:28:17.68#ibcon#about to read 4, iclass 29, count 2 2006.257.11:28:17.68#ibcon#read 4, iclass 29, count 2 2006.257.11:28:17.68#ibcon#about to read 5, iclass 29, count 2 2006.257.11:28:17.68#ibcon#read 5, iclass 29, count 2 2006.257.11:28:17.68#ibcon#about to read 6, iclass 29, count 2 2006.257.11:28:17.68#ibcon#read 6, iclass 29, count 2 2006.257.11:28:17.68#ibcon#end of sib2, iclass 29, count 2 2006.257.11:28:17.68#ibcon#*mode == 0, iclass 29, count 2 2006.257.11:28:17.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.11:28:17.68#ibcon#[25=AT02-07\r\n] 2006.257.11:28:17.68#ibcon#*before write, iclass 29, count 2 2006.257.11:28:17.68#ibcon#enter sib2, iclass 29, count 2 2006.257.11:28:17.68#ibcon#flushed, iclass 29, count 2 2006.257.11:28:17.68#ibcon#about to write, iclass 29, count 2 2006.257.11:28:17.68#ibcon#wrote, iclass 29, count 2 2006.257.11:28:17.68#ibcon#about to read 3, iclass 29, count 2 2006.257.11:28:17.71#ibcon#read 3, iclass 29, count 2 2006.257.11:28:17.71#ibcon#about to read 4, iclass 29, count 2 2006.257.11:28:17.71#ibcon#read 4, iclass 29, count 2 2006.257.11:28:17.71#ibcon#about to read 5, iclass 29, count 2 2006.257.11:28:17.71#ibcon#read 5, iclass 29, count 2 2006.257.11:28:17.71#ibcon#about to read 6, iclass 29, count 2 2006.257.11:28:17.71#ibcon#read 6, iclass 29, count 2 2006.257.11:28:17.71#ibcon#end of sib2, iclass 29, count 2 2006.257.11:28:17.71#ibcon#*after write, iclass 29, count 2 2006.257.11:28:17.71#ibcon#*before return 0, iclass 29, count 2 2006.257.11:28:17.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:17.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:17.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.11:28:17.71#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:17.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:17.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:17.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:17.83#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:28:17.83#ibcon#first serial, iclass 29, count 0 2006.257.11:28:17.83#ibcon#enter sib2, iclass 29, count 0 2006.257.11:28:17.83#ibcon#flushed, iclass 29, count 0 2006.257.11:28:17.83#ibcon#about to write, iclass 29, count 0 2006.257.11:28:17.83#ibcon#wrote, iclass 29, count 0 2006.257.11:28:17.83#ibcon#about to read 3, iclass 29, count 0 2006.257.11:28:17.85#ibcon#read 3, iclass 29, count 0 2006.257.11:28:17.85#ibcon#about to read 4, iclass 29, count 0 2006.257.11:28:17.85#ibcon#read 4, iclass 29, count 0 2006.257.11:28:17.85#ibcon#about to read 5, iclass 29, count 0 2006.257.11:28:17.85#ibcon#read 5, iclass 29, count 0 2006.257.11:28:17.85#ibcon#about to read 6, iclass 29, count 0 2006.257.11:28:17.85#ibcon#read 6, iclass 29, count 0 2006.257.11:28:17.85#ibcon#end of sib2, iclass 29, count 0 2006.257.11:28:17.85#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:28:17.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:28:17.85#ibcon#[25=USB\r\n] 2006.257.11:28:17.85#ibcon#*before write, iclass 29, count 0 2006.257.11:28:17.85#ibcon#enter sib2, iclass 29, count 0 2006.257.11:28:17.85#ibcon#flushed, iclass 29, count 0 2006.257.11:28:17.85#ibcon#about to write, iclass 29, count 0 2006.257.11:28:17.85#ibcon#wrote, iclass 29, count 0 2006.257.11:28:17.85#ibcon#about to read 3, iclass 29, count 0 2006.257.11:28:17.88#ibcon#read 3, iclass 29, count 0 2006.257.11:28:17.88#ibcon#about to read 4, iclass 29, count 0 2006.257.11:28:17.88#ibcon#read 4, iclass 29, count 0 2006.257.11:28:17.88#ibcon#about to read 5, iclass 29, count 0 2006.257.11:28:17.88#ibcon#read 5, iclass 29, count 0 2006.257.11:28:17.88#ibcon#about to read 6, iclass 29, count 0 2006.257.11:28:17.88#ibcon#read 6, iclass 29, count 0 2006.257.11:28:17.88#ibcon#end of sib2, iclass 29, count 0 2006.257.11:28:17.88#ibcon#*after write, iclass 29, count 0 2006.257.11:28:17.88#ibcon#*before return 0, iclass 29, count 0 2006.257.11:28:17.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:17.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:17.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:28:17.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:28:17.88$vck44/valo=3,564.99 2006.257.11:28:17.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.11:28:17.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.11:28:17.89#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:17.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:17.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:17.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:17.89#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:28:17.89#ibcon#first serial, iclass 31, count 0 2006.257.11:28:17.89#ibcon#enter sib2, iclass 31, count 0 2006.257.11:28:17.89#ibcon#flushed, iclass 31, count 0 2006.257.11:28:17.89#ibcon#about to write, iclass 31, count 0 2006.257.11:28:17.89#ibcon#wrote, iclass 31, count 0 2006.257.11:28:17.89#ibcon#about to read 3, iclass 31, count 0 2006.257.11:28:17.90#ibcon#read 3, iclass 31, count 0 2006.257.11:28:17.90#ibcon#about to read 4, iclass 31, count 0 2006.257.11:28:17.90#ibcon#read 4, iclass 31, count 0 2006.257.11:28:17.90#ibcon#about to read 5, iclass 31, count 0 2006.257.11:28:17.90#ibcon#read 5, iclass 31, count 0 2006.257.11:28:17.90#ibcon#about to read 6, iclass 31, count 0 2006.257.11:28:17.90#ibcon#read 6, iclass 31, count 0 2006.257.11:28:17.90#ibcon#end of sib2, iclass 31, count 0 2006.257.11:28:17.90#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:28:17.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:28:17.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:28:17.90#ibcon#*before write, iclass 31, count 0 2006.257.11:28:17.90#ibcon#enter sib2, iclass 31, count 0 2006.257.11:28:17.90#ibcon#flushed, iclass 31, count 0 2006.257.11:28:17.90#ibcon#about to write, iclass 31, count 0 2006.257.11:28:17.90#ibcon#wrote, iclass 31, count 0 2006.257.11:28:17.90#ibcon#about to read 3, iclass 31, count 0 2006.257.11:28:17.94#ibcon#read 3, iclass 31, count 0 2006.257.11:28:17.94#ibcon#about to read 4, iclass 31, count 0 2006.257.11:28:17.94#ibcon#read 4, iclass 31, count 0 2006.257.11:28:17.94#ibcon#about to read 5, iclass 31, count 0 2006.257.11:28:17.94#ibcon#read 5, iclass 31, count 0 2006.257.11:28:17.94#ibcon#about to read 6, iclass 31, count 0 2006.257.11:28:17.94#ibcon#read 6, iclass 31, count 0 2006.257.11:28:17.94#ibcon#end of sib2, iclass 31, count 0 2006.257.11:28:17.94#ibcon#*after write, iclass 31, count 0 2006.257.11:28:17.94#ibcon#*before return 0, iclass 31, count 0 2006.257.11:28:17.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:17.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:17.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:28:17.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:28:17.94$vck44/va=3,8 2006.257.11:28:17.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.11:28:17.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.11:28:17.95#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:17.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:17.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:17.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:17.99#ibcon#enter wrdev, iclass 33, count 2 2006.257.11:28:17.99#ibcon#first serial, iclass 33, count 2 2006.257.11:28:17.99#ibcon#enter sib2, iclass 33, count 2 2006.257.11:28:17.99#ibcon#flushed, iclass 33, count 2 2006.257.11:28:17.99#ibcon#about to write, iclass 33, count 2 2006.257.11:28:17.99#ibcon#wrote, iclass 33, count 2 2006.257.11:28:17.99#ibcon#about to read 3, iclass 33, count 2 2006.257.11:28:18.01#ibcon#read 3, iclass 33, count 2 2006.257.11:28:18.01#ibcon#about to read 4, iclass 33, count 2 2006.257.11:28:18.01#ibcon#read 4, iclass 33, count 2 2006.257.11:28:18.01#ibcon#about to read 5, iclass 33, count 2 2006.257.11:28:18.01#ibcon#read 5, iclass 33, count 2 2006.257.11:28:18.01#ibcon#about to read 6, iclass 33, count 2 2006.257.11:28:18.01#ibcon#read 6, iclass 33, count 2 2006.257.11:28:18.01#ibcon#end of sib2, iclass 33, count 2 2006.257.11:28:18.01#ibcon#*mode == 0, iclass 33, count 2 2006.257.11:28:18.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.11:28:18.01#ibcon#[25=AT03-08\r\n] 2006.257.11:28:18.01#ibcon#*before write, iclass 33, count 2 2006.257.11:28:18.01#ibcon#enter sib2, iclass 33, count 2 2006.257.11:28:18.01#ibcon#flushed, iclass 33, count 2 2006.257.11:28:18.01#ibcon#about to write, iclass 33, count 2 2006.257.11:28:18.01#ibcon#wrote, iclass 33, count 2 2006.257.11:28:18.01#ibcon#about to read 3, iclass 33, count 2 2006.257.11:28:18.04#ibcon#read 3, iclass 33, count 2 2006.257.11:28:18.04#ibcon#about to read 4, iclass 33, count 2 2006.257.11:28:18.04#ibcon#read 4, iclass 33, count 2 2006.257.11:28:18.04#ibcon#about to read 5, iclass 33, count 2 2006.257.11:28:18.04#ibcon#read 5, iclass 33, count 2 2006.257.11:28:18.04#ibcon#about to read 6, iclass 33, count 2 2006.257.11:28:18.04#ibcon#read 6, iclass 33, count 2 2006.257.11:28:18.04#ibcon#end of sib2, iclass 33, count 2 2006.257.11:28:18.04#ibcon#*after write, iclass 33, count 2 2006.257.11:28:18.04#ibcon#*before return 0, iclass 33, count 2 2006.257.11:28:18.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:18.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:18.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.11:28:18.04#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:18.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:18.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:18.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:18.16#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:28:18.16#ibcon#first serial, iclass 33, count 0 2006.257.11:28:18.16#ibcon#enter sib2, iclass 33, count 0 2006.257.11:28:18.16#ibcon#flushed, iclass 33, count 0 2006.257.11:28:18.16#ibcon#about to write, iclass 33, count 0 2006.257.11:28:18.16#ibcon#wrote, iclass 33, count 0 2006.257.11:28:18.16#ibcon#about to read 3, iclass 33, count 0 2006.257.11:28:18.18#ibcon#read 3, iclass 33, count 0 2006.257.11:28:18.18#ibcon#about to read 4, iclass 33, count 0 2006.257.11:28:18.18#ibcon#read 4, iclass 33, count 0 2006.257.11:28:18.18#ibcon#about to read 5, iclass 33, count 0 2006.257.11:28:18.18#ibcon#read 5, iclass 33, count 0 2006.257.11:28:18.18#ibcon#about to read 6, iclass 33, count 0 2006.257.11:28:18.18#ibcon#read 6, iclass 33, count 0 2006.257.11:28:18.18#ibcon#end of sib2, iclass 33, count 0 2006.257.11:28:18.18#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:28:18.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:28:18.18#ibcon#[25=USB\r\n] 2006.257.11:28:18.18#ibcon#*before write, iclass 33, count 0 2006.257.11:28:18.18#ibcon#enter sib2, iclass 33, count 0 2006.257.11:28:18.18#ibcon#flushed, iclass 33, count 0 2006.257.11:28:18.18#ibcon#about to write, iclass 33, count 0 2006.257.11:28:18.18#ibcon#wrote, iclass 33, count 0 2006.257.11:28:18.18#ibcon#about to read 3, iclass 33, count 0 2006.257.11:28:18.21#ibcon#read 3, iclass 33, count 0 2006.257.11:28:18.21#ibcon#about to read 4, iclass 33, count 0 2006.257.11:28:18.21#ibcon#read 4, iclass 33, count 0 2006.257.11:28:18.21#ibcon#about to read 5, iclass 33, count 0 2006.257.11:28:18.21#ibcon#read 5, iclass 33, count 0 2006.257.11:28:18.21#ibcon#about to read 6, iclass 33, count 0 2006.257.11:28:18.21#ibcon#read 6, iclass 33, count 0 2006.257.11:28:18.21#ibcon#end of sib2, iclass 33, count 0 2006.257.11:28:18.21#ibcon#*after write, iclass 33, count 0 2006.257.11:28:18.21#ibcon#*before return 0, iclass 33, count 0 2006.257.11:28:18.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:18.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:18.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:28:18.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:28:18.21$vck44/valo=4,624.99 2006.257.11:28:18.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.11:28:18.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.11:28:18.22#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:18.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:18.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:18.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:18.22#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:28:18.22#ibcon#first serial, iclass 35, count 0 2006.257.11:28:18.22#ibcon#enter sib2, iclass 35, count 0 2006.257.11:28:18.22#ibcon#flushed, iclass 35, count 0 2006.257.11:28:18.22#ibcon#about to write, iclass 35, count 0 2006.257.11:28:18.22#ibcon#wrote, iclass 35, count 0 2006.257.11:28:18.22#ibcon#about to read 3, iclass 35, count 0 2006.257.11:28:18.23#ibcon#read 3, iclass 35, count 0 2006.257.11:28:18.23#ibcon#about to read 4, iclass 35, count 0 2006.257.11:28:18.23#ibcon#read 4, iclass 35, count 0 2006.257.11:28:18.23#ibcon#about to read 5, iclass 35, count 0 2006.257.11:28:18.23#ibcon#read 5, iclass 35, count 0 2006.257.11:28:18.23#ibcon#about to read 6, iclass 35, count 0 2006.257.11:28:18.23#ibcon#read 6, iclass 35, count 0 2006.257.11:28:18.23#ibcon#end of sib2, iclass 35, count 0 2006.257.11:28:18.23#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:28:18.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:28:18.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:28:18.23#ibcon#*before write, iclass 35, count 0 2006.257.11:28:18.23#ibcon#enter sib2, iclass 35, count 0 2006.257.11:28:18.23#ibcon#flushed, iclass 35, count 0 2006.257.11:28:18.23#ibcon#about to write, iclass 35, count 0 2006.257.11:28:18.23#ibcon#wrote, iclass 35, count 0 2006.257.11:28:18.23#ibcon#about to read 3, iclass 35, count 0 2006.257.11:28:18.27#ibcon#read 3, iclass 35, count 0 2006.257.11:28:18.27#ibcon#about to read 4, iclass 35, count 0 2006.257.11:28:18.27#ibcon#read 4, iclass 35, count 0 2006.257.11:28:18.27#ibcon#about to read 5, iclass 35, count 0 2006.257.11:28:18.27#ibcon#read 5, iclass 35, count 0 2006.257.11:28:18.27#ibcon#about to read 6, iclass 35, count 0 2006.257.11:28:18.27#ibcon#read 6, iclass 35, count 0 2006.257.11:28:18.27#ibcon#end of sib2, iclass 35, count 0 2006.257.11:28:18.27#ibcon#*after write, iclass 35, count 0 2006.257.11:28:18.27#ibcon#*before return 0, iclass 35, count 0 2006.257.11:28:18.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:18.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:18.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:28:18.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:28:18.27$vck44/va=4,7 2006.257.11:28:18.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.11:28:18.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.11:28:18.28#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:18.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:18.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:18.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:18.32#ibcon#enter wrdev, iclass 37, count 2 2006.257.11:28:18.32#ibcon#first serial, iclass 37, count 2 2006.257.11:28:18.32#ibcon#enter sib2, iclass 37, count 2 2006.257.11:28:18.32#ibcon#flushed, iclass 37, count 2 2006.257.11:28:18.32#ibcon#about to write, iclass 37, count 2 2006.257.11:28:18.32#ibcon#wrote, iclass 37, count 2 2006.257.11:28:18.32#ibcon#about to read 3, iclass 37, count 2 2006.257.11:28:18.34#ibcon#read 3, iclass 37, count 2 2006.257.11:28:18.34#ibcon#about to read 4, iclass 37, count 2 2006.257.11:28:18.34#ibcon#read 4, iclass 37, count 2 2006.257.11:28:18.34#ibcon#about to read 5, iclass 37, count 2 2006.257.11:28:18.34#ibcon#read 5, iclass 37, count 2 2006.257.11:28:18.34#ibcon#about to read 6, iclass 37, count 2 2006.257.11:28:18.34#ibcon#read 6, iclass 37, count 2 2006.257.11:28:18.34#ibcon#end of sib2, iclass 37, count 2 2006.257.11:28:18.34#ibcon#*mode == 0, iclass 37, count 2 2006.257.11:28:18.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.11:28:18.34#ibcon#[25=AT04-07\r\n] 2006.257.11:28:18.34#ibcon#*before write, iclass 37, count 2 2006.257.11:28:18.34#ibcon#enter sib2, iclass 37, count 2 2006.257.11:28:18.34#ibcon#flushed, iclass 37, count 2 2006.257.11:28:18.34#ibcon#about to write, iclass 37, count 2 2006.257.11:28:18.34#ibcon#wrote, iclass 37, count 2 2006.257.11:28:18.34#ibcon#about to read 3, iclass 37, count 2 2006.257.11:28:18.37#ibcon#read 3, iclass 37, count 2 2006.257.11:28:18.37#ibcon#about to read 4, iclass 37, count 2 2006.257.11:28:18.37#ibcon#read 4, iclass 37, count 2 2006.257.11:28:18.37#ibcon#about to read 5, iclass 37, count 2 2006.257.11:28:18.37#ibcon#read 5, iclass 37, count 2 2006.257.11:28:18.37#ibcon#about to read 6, iclass 37, count 2 2006.257.11:28:18.37#ibcon#read 6, iclass 37, count 2 2006.257.11:28:18.37#ibcon#end of sib2, iclass 37, count 2 2006.257.11:28:18.37#ibcon#*after write, iclass 37, count 2 2006.257.11:28:18.41#ibcon#*before return 0, iclass 37, count 2 2006.257.11:28:18.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:18.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:18.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.11:28:18.42#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:18.42#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:18.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:18.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:18.52#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:28:18.52#ibcon#first serial, iclass 37, count 0 2006.257.11:28:18.52#ibcon#enter sib2, iclass 37, count 0 2006.257.11:28:18.52#ibcon#flushed, iclass 37, count 0 2006.257.11:28:18.52#ibcon#about to write, iclass 37, count 0 2006.257.11:28:18.52#ibcon#wrote, iclass 37, count 0 2006.257.11:28:18.52#ibcon#about to read 3, iclass 37, count 0 2006.257.11:28:18.54#ibcon#read 3, iclass 37, count 0 2006.257.11:28:18.54#ibcon#about to read 4, iclass 37, count 0 2006.257.11:28:18.54#ibcon#read 4, iclass 37, count 0 2006.257.11:28:18.54#ibcon#about to read 5, iclass 37, count 0 2006.257.11:28:18.54#ibcon#read 5, iclass 37, count 0 2006.257.11:28:18.54#ibcon#about to read 6, iclass 37, count 0 2006.257.11:28:18.54#ibcon#read 6, iclass 37, count 0 2006.257.11:28:18.54#ibcon#end of sib2, iclass 37, count 0 2006.257.11:28:18.54#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:28:18.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:28:18.54#ibcon#[25=USB\r\n] 2006.257.11:28:18.54#ibcon#*before write, iclass 37, count 0 2006.257.11:28:18.54#ibcon#enter sib2, iclass 37, count 0 2006.257.11:28:18.54#ibcon#flushed, iclass 37, count 0 2006.257.11:28:18.54#ibcon#about to write, iclass 37, count 0 2006.257.11:28:18.54#ibcon#wrote, iclass 37, count 0 2006.257.11:28:18.54#ibcon#about to read 3, iclass 37, count 0 2006.257.11:28:18.57#ibcon#read 3, iclass 37, count 0 2006.257.11:28:18.57#ibcon#about to read 4, iclass 37, count 0 2006.257.11:28:18.57#ibcon#read 4, iclass 37, count 0 2006.257.11:28:18.57#ibcon#about to read 5, iclass 37, count 0 2006.257.11:28:18.57#ibcon#read 5, iclass 37, count 0 2006.257.11:28:18.57#ibcon#about to read 6, iclass 37, count 0 2006.257.11:28:18.57#ibcon#read 6, iclass 37, count 0 2006.257.11:28:18.57#ibcon#end of sib2, iclass 37, count 0 2006.257.11:28:18.57#ibcon#*after write, iclass 37, count 0 2006.257.11:28:18.57#ibcon#*before return 0, iclass 37, count 0 2006.257.11:28:18.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:18.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:18.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:28:18.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:28:18.58$vck44/valo=5,734.99 2006.257.11:28:18.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.11:28:18.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.11:28:18.58#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:18.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:18.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:18.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:18.58#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:28:18.58#ibcon#first serial, iclass 39, count 0 2006.257.11:28:18.58#ibcon#enter sib2, iclass 39, count 0 2006.257.11:28:18.58#ibcon#flushed, iclass 39, count 0 2006.257.11:28:18.58#ibcon#about to write, iclass 39, count 0 2006.257.11:28:18.58#ibcon#wrote, iclass 39, count 0 2006.257.11:28:18.58#ibcon#about to read 3, iclass 39, count 0 2006.257.11:28:18.59#ibcon#read 3, iclass 39, count 0 2006.257.11:28:18.59#ibcon#about to read 4, iclass 39, count 0 2006.257.11:28:18.59#ibcon#read 4, iclass 39, count 0 2006.257.11:28:18.59#ibcon#about to read 5, iclass 39, count 0 2006.257.11:28:18.59#ibcon#read 5, iclass 39, count 0 2006.257.11:28:18.59#ibcon#about to read 6, iclass 39, count 0 2006.257.11:28:18.59#ibcon#read 6, iclass 39, count 0 2006.257.11:28:18.59#ibcon#end of sib2, iclass 39, count 0 2006.257.11:28:18.59#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:28:18.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:28:18.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:28:18.59#ibcon#*before write, iclass 39, count 0 2006.257.11:28:18.59#ibcon#enter sib2, iclass 39, count 0 2006.257.11:28:18.59#ibcon#flushed, iclass 39, count 0 2006.257.11:28:18.59#ibcon#about to write, iclass 39, count 0 2006.257.11:28:18.59#ibcon#wrote, iclass 39, count 0 2006.257.11:28:18.59#ibcon#about to read 3, iclass 39, count 0 2006.257.11:28:18.63#ibcon#read 3, iclass 39, count 0 2006.257.11:28:18.63#ibcon#about to read 4, iclass 39, count 0 2006.257.11:28:18.63#ibcon#read 4, iclass 39, count 0 2006.257.11:28:18.63#ibcon#about to read 5, iclass 39, count 0 2006.257.11:28:18.63#ibcon#read 5, iclass 39, count 0 2006.257.11:28:18.63#ibcon#about to read 6, iclass 39, count 0 2006.257.11:28:18.63#ibcon#read 6, iclass 39, count 0 2006.257.11:28:18.63#ibcon#end of sib2, iclass 39, count 0 2006.257.11:28:18.63#ibcon#*after write, iclass 39, count 0 2006.257.11:28:18.63#ibcon#*before return 0, iclass 39, count 0 2006.257.11:28:18.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:18.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:18.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:28:18.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:28:18.63$vck44/va=5,4 2006.257.11:28:18.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.11:28:18.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.11:28:18.64#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:18.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:18.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:18.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:18.68#ibcon#enter wrdev, iclass 3, count 2 2006.257.11:28:18.68#ibcon#first serial, iclass 3, count 2 2006.257.11:28:18.68#ibcon#enter sib2, iclass 3, count 2 2006.257.11:28:18.68#ibcon#flushed, iclass 3, count 2 2006.257.11:28:18.68#ibcon#about to write, iclass 3, count 2 2006.257.11:28:18.68#ibcon#wrote, iclass 3, count 2 2006.257.11:28:18.68#ibcon#about to read 3, iclass 3, count 2 2006.257.11:28:18.70#ibcon#read 3, iclass 3, count 2 2006.257.11:28:18.70#ibcon#about to read 4, iclass 3, count 2 2006.257.11:28:18.70#ibcon#read 4, iclass 3, count 2 2006.257.11:28:18.70#ibcon#about to read 5, iclass 3, count 2 2006.257.11:28:18.70#ibcon#read 5, iclass 3, count 2 2006.257.11:28:18.70#ibcon#about to read 6, iclass 3, count 2 2006.257.11:28:18.70#ibcon#read 6, iclass 3, count 2 2006.257.11:28:18.70#ibcon#end of sib2, iclass 3, count 2 2006.257.11:28:18.70#ibcon#*mode == 0, iclass 3, count 2 2006.257.11:28:18.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.11:28:18.70#ibcon#[25=AT05-04\r\n] 2006.257.11:28:18.70#ibcon#*before write, iclass 3, count 2 2006.257.11:28:18.70#ibcon#enter sib2, iclass 3, count 2 2006.257.11:28:18.70#ibcon#flushed, iclass 3, count 2 2006.257.11:28:18.70#ibcon#about to write, iclass 3, count 2 2006.257.11:28:18.70#ibcon#wrote, iclass 3, count 2 2006.257.11:28:18.70#ibcon#about to read 3, iclass 3, count 2 2006.257.11:28:18.73#ibcon#read 3, iclass 3, count 2 2006.257.11:28:18.73#ibcon#about to read 4, iclass 3, count 2 2006.257.11:28:18.73#ibcon#read 4, iclass 3, count 2 2006.257.11:28:18.73#ibcon#about to read 5, iclass 3, count 2 2006.257.11:28:18.73#ibcon#read 5, iclass 3, count 2 2006.257.11:28:18.73#ibcon#about to read 6, iclass 3, count 2 2006.257.11:28:18.73#ibcon#read 6, iclass 3, count 2 2006.257.11:28:18.73#ibcon#end of sib2, iclass 3, count 2 2006.257.11:28:18.73#ibcon#*after write, iclass 3, count 2 2006.257.11:28:18.73#ibcon#*before return 0, iclass 3, count 2 2006.257.11:28:18.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:18.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:18.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.11:28:18.73#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:18.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:18.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:18.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:18.85#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:28:18.85#ibcon#first serial, iclass 3, count 0 2006.257.11:28:18.85#ibcon#enter sib2, iclass 3, count 0 2006.257.11:28:18.85#ibcon#flushed, iclass 3, count 0 2006.257.11:28:18.85#ibcon#about to write, iclass 3, count 0 2006.257.11:28:18.85#ibcon#wrote, iclass 3, count 0 2006.257.11:28:18.85#ibcon#about to read 3, iclass 3, count 0 2006.257.11:28:18.87#ibcon#read 3, iclass 3, count 0 2006.257.11:28:18.87#ibcon#about to read 4, iclass 3, count 0 2006.257.11:28:18.87#ibcon#read 4, iclass 3, count 0 2006.257.11:28:18.87#ibcon#about to read 5, iclass 3, count 0 2006.257.11:28:18.87#ibcon#read 5, iclass 3, count 0 2006.257.11:28:18.87#ibcon#about to read 6, iclass 3, count 0 2006.257.11:28:18.87#ibcon#read 6, iclass 3, count 0 2006.257.11:28:18.87#ibcon#end of sib2, iclass 3, count 0 2006.257.11:28:18.87#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:28:18.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:28:18.87#ibcon#[25=USB\r\n] 2006.257.11:28:18.87#ibcon#*before write, iclass 3, count 0 2006.257.11:28:18.87#ibcon#enter sib2, iclass 3, count 0 2006.257.11:28:18.87#ibcon#flushed, iclass 3, count 0 2006.257.11:28:18.87#ibcon#about to write, iclass 3, count 0 2006.257.11:28:18.87#ibcon#wrote, iclass 3, count 0 2006.257.11:28:18.87#ibcon#about to read 3, iclass 3, count 0 2006.257.11:28:18.90#ibcon#read 3, iclass 3, count 0 2006.257.11:28:18.90#ibcon#about to read 4, iclass 3, count 0 2006.257.11:28:18.90#ibcon#read 4, iclass 3, count 0 2006.257.11:28:18.90#ibcon#about to read 5, iclass 3, count 0 2006.257.11:28:18.90#ibcon#read 5, iclass 3, count 0 2006.257.11:28:18.90#ibcon#about to read 6, iclass 3, count 0 2006.257.11:28:18.90#ibcon#read 6, iclass 3, count 0 2006.257.11:28:18.90#ibcon#end of sib2, iclass 3, count 0 2006.257.11:28:18.90#ibcon#*after write, iclass 3, count 0 2006.257.11:28:18.90#ibcon#*before return 0, iclass 3, count 0 2006.257.11:28:18.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:18.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:18.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:28:18.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:28:18.90$vck44/valo=6,814.99 2006.257.11:28:18.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.11:28:18.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.11:28:18.91#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:18.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:18.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:18.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:18.91#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:28:18.91#ibcon#first serial, iclass 5, count 0 2006.257.11:28:18.91#ibcon#enter sib2, iclass 5, count 0 2006.257.11:28:18.91#ibcon#flushed, iclass 5, count 0 2006.257.11:28:18.91#ibcon#about to write, iclass 5, count 0 2006.257.11:28:18.91#ibcon#wrote, iclass 5, count 0 2006.257.11:28:18.91#ibcon#about to read 3, iclass 5, count 0 2006.257.11:28:18.92#ibcon#read 3, iclass 5, count 0 2006.257.11:28:18.92#ibcon#about to read 4, iclass 5, count 0 2006.257.11:28:18.92#ibcon#read 4, iclass 5, count 0 2006.257.11:28:18.92#ibcon#about to read 5, iclass 5, count 0 2006.257.11:28:18.92#ibcon#read 5, iclass 5, count 0 2006.257.11:28:18.92#ibcon#about to read 6, iclass 5, count 0 2006.257.11:28:18.92#ibcon#read 6, iclass 5, count 0 2006.257.11:28:18.92#ibcon#end of sib2, iclass 5, count 0 2006.257.11:28:18.92#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:28:18.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:28:18.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:28:18.92#ibcon#*before write, iclass 5, count 0 2006.257.11:28:18.92#ibcon#enter sib2, iclass 5, count 0 2006.257.11:28:18.92#ibcon#flushed, iclass 5, count 0 2006.257.11:28:18.92#ibcon#about to write, iclass 5, count 0 2006.257.11:28:18.92#ibcon#wrote, iclass 5, count 0 2006.257.11:28:18.92#ibcon#about to read 3, iclass 5, count 0 2006.257.11:28:18.96#ibcon#read 3, iclass 5, count 0 2006.257.11:28:18.96#ibcon#about to read 4, iclass 5, count 0 2006.257.11:28:18.96#ibcon#read 4, iclass 5, count 0 2006.257.11:28:18.96#ibcon#about to read 5, iclass 5, count 0 2006.257.11:28:18.96#ibcon#read 5, iclass 5, count 0 2006.257.11:28:18.96#ibcon#about to read 6, iclass 5, count 0 2006.257.11:28:18.96#ibcon#read 6, iclass 5, count 0 2006.257.11:28:18.96#ibcon#end of sib2, iclass 5, count 0 2006.257.11:28:18.96#ibcon#*after write, iclass 5, count 0 2006.257.11:28:18.96#ibcon#*before return 0, iclass 5, count 0 2006.257.11:28:18.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:18.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:18.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:28:18.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:28:18.96$vck44/va=6,4 2006.257.11:28:18.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.11:28:18.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.11:28:18.97#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:18.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:19.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:19.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:19.01#ibcon#enter wrdev, iclass 7, count 2 2006.257.11:28:19.01#ibcon#first serial, iclass 7, count 2 2006.257.11:28:19.01#ibcon#enter sib2, iclass 7, count 2 2006.257.11:28:19.01#ibcon#flushed, iclass 7, count 2 2006.257.11:28:19.01#ibcon#about to write, iclass 7, count 2 2006.257.11:28:19.01#ibcon#wrote, iclass 7, count 2 2006.257.11:28:19.01#ibcon#about to read 3, iclass 7, count 2 2006.257.11:28:19.03#ibcon#read 3, iclass 7, count 2 2006.257.11:28:19.03#ibcon#about to read 4, iclass 7, count 2 2006.257.11:28:19.03#ibcon#read 4, iclass 7, count 2 2006.257.11:28:19.03#ibcon#about to read 5, iclass 7, count 2 2006.257.11:28:19.03#ibcon#read 5, iclass 7, count 2 2006.257.11:28:19.03#ibcon#about to read 6, iclass 7, count 2 2006.257.11:28:19.03#ibcon#read 6, iclass 7, count 2 2006.257.11:28:19.03#ibcon#end of sib2, iclass 7, count 2 2006.257.11:28:19.03#ibcon#*mode == 0, iclass 7, count 2 2006.257.11:28:19.03#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.11:28:19.03#ibcon#[25=AT06-04\r\n] 2006.257.11:28:19.03#ibcon#*before write, iclass 7, count 2 2006.257.11:28:19.03#ibcon#enter sib2, iclass 7, count 2 2006.257.11:28:19.03#ibcon#flushed, iclass 7, count 2 2006.257.11:28:19.03#ibcon#about to write, iclass 7, count 2 2006.257.11:28:19.03#ibcon#wrote, iclass 7, count 2 2006.257.11:28:19.03#ibcon#about to read 3, iclass 7, count 2 2006.257.11:28:19.06#ibcon#read 3, iclass 7, count 2 2006.257.11:28:19.06#ibcon#about to read 4, iclass 7, count 2 2006.257.11:28:19.06#ibcon#read 4, iclass 7, count 2 2006.257.11:28:19.06#ibcon#about to read 5, iclass 7, count 2 2006.257.11:28:19.06#ibcon#read 5, iclass 7, count 2 2006.257.11:28:19.06#ibcon#about to read 6, iclass 7, count 2 2006.257.11:28:19.06#ibcon#read 6, iclass 7, count 2 2006.257.11:28:19.06#ibcon#end of sib2, iclass 7, count 2 2006.257.11:28:19.06#ibcon#*after write, iclass 7, count 2 2006.257.11:28:19.06#ibcon#*before return 0, iclass 7, count 2 2006.257.11:28:19.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:19.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:19.06#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.11:28:19.06#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:19.06#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:19.18#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:19.18#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:19.18#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:28:19.18#ibcon#first serial, iclass 7, count 0 2006.257.11:28:19.18#ibcon#enter sib2, iclass 7, count 0 2006.257.11:28:19.18#ibcon#flushed, iclass 7, count 0 2006.257.11:28:19.18#ibcon#about to write, iclass 7, count 0 2006.257.11:28:19.18#ibcon#wrote, iclass 7, count 0 2006.257.11:28:19.18#ibcon#about to read 3, iclass 7, count 0 2006.257.11:28:19.20#ibcon#read 3, iclass 7, count 0 2006.257.11:28:19.20#ibcon#about to read 4, iclass 7, count 0 2006.257.11:28:19.20#ibcon#read 4, iclass 7, count 0 2006.257.11:28:19.20#ibcon#about to read 5, iclass 7, count 0 2006.257.11:28:19.20#ibcon#read 5, iclass 7, count 0 2006.257.11:28:19.20#ibcon#about to read 6, iclass 7, count 0 2006.257.11:28:19.20#ibcon#read 6, iclass 7, count 0 2006.257.11:28:19.20#ibcon#end of sib2, iclass 7, count 0 2006.257.11:28:19.20#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:28:19.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:28:19.20#ibcon#[25=USB\r\n] 2006.257.11:28:19.20#ibcon#*before write, iclass 7, count 0 2006.257.11:28:19.20#ibcon#enter sib2, iclass 7, count 0 2006.257.11:28:19.20#ibcon#flushed, iclass 7, count 0 2006.257.11:28:19.20#ibcon#about to write, iclass 7, count 0 2006.257.11:28:19.20#ibcon#wrote, iclass 7, count 0 2006.257.11:28:19.20#ibcon#about to read 3, iclass 7, count 0 2006.257.11:28:19.23#ibcon#read 3, iclass 7, count 0 2006.257.11:28:19.23#ibcon#about to read 4, iclass 7, count 0 2006.257.11:28:19.23#ibcon#read 4, iclass 7, count 0 2006.257.11:28:19.23#ibcon#about to read 5, iclass 7, count 0 2006.257.11:28:19.23#ibcon#read 5, iclass 7, count 0 2006.257.11:28:19.23#ibcon#about to read 6, iclass 7, count 0 2006.257.11:28:19.23#ibcon#read 6, iclass 7, count 0 2006.257.11:28:19.23#ibcon#end of sib2, iclass 7, count 0 2006.257.11:28:19.23#ibcon#*after write, iclass 7, count 0 2006.257.11:28:19.23#ibcon#*before return 0, iclass 7, count 0 2006.257.11:28:19.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:19.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:19.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:28:19.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:28:19.24$vck44/valo=7,864.99 2006.257.11:28:19.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.11:28:19.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.11:28:19.24#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:19.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:19.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:19.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:19.24#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:28:19.24#ibcon#first serial, iclass 11, count 0 2006.257.11:28:19.24#ibcon#enter sib2, iclass 11, count 0 2006.257.11:28:19.24#ibcon#flushed, iclass 11, count 0 2006.257.11:28:19.24#ibcon#about to write, iclass 11, count 0 2006.257.11:28:19.24#ibcon#wrote, iclass 11, count 0 2006.257.11:28:19.24#ibcon#about to read 3, iclass 11, count 0 2006.257.11:28:19.25#ibcon#read 3, iclass 11, count 0 2006.257.11:28:19.25#ibcon#about to read 4, iclass 11, count 0 2006.257.11:28:19.25#ibcon#read 4, iclass 11, count 0 2006.257.11:28:19.25#ibcon#about to read 5, iclass 11, count 0 2006.257.11:28:19.25#ibcon#read 5, iclass 11, count 0 2006.257.11:28:19.25#ibcon#about to read 6, iclass 11, count 0 2006.257.11:28:19.25#ibcon#read 6, iclass 11, count 0 2006.257.11:28:19.25#ibcon#end of sib2, iclass 11, count 0 2006.257.11:28:19.25#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:28:19.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:28:19.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:28:19.25#ibcon#*before write, iclass 11, count 0 2006.257.11:28:19.25#ibcon#enter sib2, iclass 11, count 0 2006.257.11:28:19.25#ibcon#flushed, iclass 11, count 0 2006.257.11:28:19.25#ibcon#about to write, iclass 11, count 0 2006.257.11:28:19.25#ibcon#wrote, iclass 11, count 0 2006.257.11:28:19.25#ibcon#about to read 3, iclass 11, count 0 2006.257.11:28:19.29#ibcon#read 3, iclass 11, count 0 2006.257.11:28:19.29#ibcon#about to read 4, iclass 11, count 0 2006.257.11:28:19.29#ibcon#read 4, iclass 11, count 0 2006.257.11:28:19.29#ibcon#about to read 5, iclass 11, count 0 2006.257.11:28:19.29#ibcon#read 5, iclass 11, count 0 2006.257.11:28:19.29#ibcon#about to read 6, iclass 11, count 0 2006.257.11:28:19.29#ibcon#read 6, iclass 11, count 0 2006.257.11:28:19.29#ibcon#end of sib2, iclass 11, count 0 2006.257.11:28:19.29#ibcon#*after write, iclass 11, count 0 2006.257.11:28:19.29#ibcon#*before return 0, iclass 11, count 0 2006.257.11:28:19.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:19.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:19.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:28:19.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:28:19.30$vck44/va=7,4 2006.257.11:28:19.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.11:28:19.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.11:28:19.30#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:19.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:19.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:19.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:19.34#ibcon#enter wrdev, iclass 13, count 2 2006.257.11:28:19.34#ibcon#first serial, iclass 13, count 2 2006.257.11:28:19.34#ibcon#enter sib2, iclass 13, count 2 2006.257.11:28:19.34#ibcon#flushed, iclass 13, count 2 2006.257.11:28:19.34#ibcon#about to write, iclass 13, count 2 2006.257.11:28:19.34#ibcon#wrote, iclass 13, count 2 2006.257.11:28:19.34#ibcon#about to read 3, iclass 13, count 2 2006.257.11:28:19.36#ibcon#read 3, iclass 13, count 2 2006.257.11:28:19.36#ibcon#about to read 4, iclass 13, count 2 2006.257.11:28:19.36#ibcon#read 4, iclass 13, count 2 2006.257.11:28:19.36#ibcon#about to read 5, iclass 13, count 2 2006.257.11:28:19.36#ibcon#read 5, iclass 13, count 2 2006.257.11:28:19.36#ibcon#about to read 6, iclass 13, count 2 2006.257.11:28:19.36#ibcon#read 6, iclass 13, count 2 2006.257.11:28:19.36#ibcon#end of sib2, iclass 13, count 2 2006.257.11:28:19.36#ibcon#*mode == 0, iclass 13, count 2 2006.257.11:28:19.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.11:28:19.36#ibcon#[25=AT07-04\r\n] 2006.257.11:28:19.36#ibcon#*before write, iclass 13, count 2 2006.257.11:28:19.36#ibcon#enter sib2, iclass 13, count 2 2006.257.11:28:19.36#ibcon#flushed, iclass 13, count 2 2006.257.11:28:19.36#ibcon#about to write, iclass 13, count 2 2006.257.11:28:19.36#ibcon#wrote, iclass 13, count 2 2006.257.11:28:19.36#ibcon#about to read 3, iclass 13, count 2 2006.257.11:28:19.39#ibcon#read 3, iclass 13, count 2 2006.257.11:28:19.39#ibcon#about to read 4, iclass 13, count 2 2006.257.11:28:19.39#ibcon#read 4, iclass 13, count 2 2006.257.11:28:19.39#ibcon#about to read 5, iclass 13, count 2 2006.257.11:28:19.39#ibcon#read 5, iclass 13, count 2 2006.257.11:28:19.39#ibcon#about to read 6, iclass 13, count 2 2006.257.11:28:19.39#ibcon#read 6, iclass 13, count 2 2006.257.11:28:19.39#ibcon#end of sib2, iclass 13, count 2 2006.257.11:28:19.39#ibcon#*after write, iclass 13, count 2 2006.257.11:28:19.39#ibcon#*before return 0, iclass 13, count 2 2006.257.11:28:19.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:19.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:19.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.11:28:19.39#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:19.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:19.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:19.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:19.51#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:28:19.51#ibcon#first serial, iclass 13, count 0 2006.257.11:28:19.51#ibcon#enter sib2, iclass 13, count 0 2006.257.11:28:19.51#ibcon#flushed, iclass 13, count 0 2006.257.11:28:19.51#ibcon#about to write, iclass 13, count 0 2006.257.11:28:19.51#ibcon#wrote, iclass 13, count 0 2006.257.11:28:19.51#ibcon#about to read 3, iclass 13, count 0 2006.257.11:28:19.53#ibcon#read 3, iclass 13, count 0 2006.257.11:28:19.53#ibcon#about to read 4, iclass 13, count 0 2006.257.11:28:19.53#ibcon#read 4, iclass 13, count 0 2006.257.11:28:19.53#ibcon#about to read 5, iclass 13, count 0 2006.257.11:28:19.53#ibcon#read 5, iclass 13, count 0 2006.257.11:28:19.53#ibcon#about to read 6, iclass 13, count 0 2006.257.11:28:19.53#ibcon#read 6, iclass 13, count 0 2006.257.11:28:19.53#ibcon#end of sib2, iclass 13, count 0 2006.257.11:28:19.53#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:28:19.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:28:19.53#ibcon#[25=USB\r\n] 2006.257.11:28:19.53#ibcon#*before write, iclass 13, count 0 2006.257.11:28:19.53#ibcon#enter sib2, iclass 13, count 0 2006.257.11:28:19.53#ibcon#flushed, iclass 13, count 0 2006.257.11:28:19.53#ibcon#about to write, iclass 13, count 0 2006.257.11:28:19.53#ibcon#wrote, iclass 13, count 0 2006.257.11:28:19.53#ibcon#about to read 3, iclass 13, count 0 2006.257.11:28:19.56#ibcon#read 3, iclass 13, count 0 2006.257.11:28:19.56#ibcon#about to read 4, iclass 13, count 0 2006.257.11:28:19.56#ibcon#read 4, iclass 13, count 0 2006.257.11:28:19.56#ibcon#about to read 5, iclass 13, count 0 2006.257.11:28:19.56#ibcon#read 5, iclass 13, count 0 2006.257.11:28:19.56#ibcon#about to read 6, iclass 13, count 0 2006.257.11:28:19.56#ibcon#read 6, iclass 13, count 0 2006.257.11:28:19.56#ibcon#end of sib2, iclass 13, count 0 2006.257.11:28:19.56#ibcon#*after write, iclass 13, count 0 2006.257.11:28:19.56#ibcon#*before return 0, iclass 13, count 0 2006.257.11:28:19.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:19.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:19.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:28:19.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:28:19.57$vck44/valo=8,884.99 2006.257.11:28:19.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.11:28:19.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.11:28:19.57#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:19.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:19.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:19.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:19.57#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:28:19.57#ibcon#first serial, iclass 15, count 0 2006.257.11:28:19.57#ibcon#enter sib2, iclass 15, count 0 2006.257.11:28:19.57#ibcon#flushed, iclass 15, count 0 2006.257.11:28:19.57#ibcon#about to write, iclass 15, count 0 2006.257.11:28:19.57#ibcon#wrote, iclass 15, count 0 2006.257.11:28:19.57#ibcon#about to read 3, iclass 15, count 0 2006.257.11:28:19.58#ibcon#read 3, iclass 15, count 0 2006.257.11:28:19.58#ibcon#about to read 4, iclass 15, count 0 2006.257.11:28:19.58#ibcon#read 4, iclass 15, count 0 2006.257.11:28:19.58#ibcon#about to read 5, iclass 15, count 0 2006.257.11:28:19.58#ibcon#read 5, iclass 15, count 0 2006.257.11:28:19.58#ibcon#about to read 6, iclass 15, count 0 2006.257.11:28:19.58#ibcon#read 6, iclass 15, count 0 2006.257.11:28:19.58#ibcon#end of sib2, iclass 15, count 0 2006.257.11:28:19.58#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:28:19.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:28:19.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:28:19.58#ibcon#*before write, iclass 15, count 0 2006.257.11:28:19.58#ibcon#enter sib2, iclass 15, count 0 2006.257.11:28:19.58#ibcon#flushed, iclass 15, count 0 2006.257.11:28:19.58#ibcon#about to write, iclass 15, count 0 2006.257.11:28:19.58#ibcon#wrote, iclass 15, count 0 2006.257.11:28:19.58#ibcon#about to read 3, iclass 15, count 0 2006.257.11:28:19.62#ibcon#read 3, iclass 15, count 0 2006.257.11:28:19.62#ibcon#about to read 4, iclass 15, count 0 2006.257.11:28:19.62#ibcon#read 4, iclass 15, count 0 2006.257.11:28:19.62#ibcon#about to read 5, iclass 15, count 0 2006.257.11:28:19.62#ibcon#read 5, iclass 15, count 0 2006.257.11:28:19.62#ibcon#about to read 6, iclass 15, count 0 2006.257.11:28:19.62#ibcon#read 6, iclass 15, count 0 2006.257.11:28:19.62#ibcon#end of sib2, iclass 15, count 0 2006.257.11:28:19.62#ibcon#*after write, iclass 15, count 0 2006.257.11:28:19.62#ibcon#*before return 0, iclass 15, count 0 2006.257.11:28:19.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:19.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:19.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:28:19.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:28:19.62$vck44/va=8,4 2006.257.11:28:19.63#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.11:28:19.63#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.11:28:19.63#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:19.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:28:19.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:28:19.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:28:19.67#ibcon#enter wrdev, iclass 17, count 2 2006.257.11:28:19.67#ibcon#first serial, iclass 17, count 2 2006.257.11:28:19.67#ibcon#enter sib2, iclass 17, count 2 2006.257.11:28:19.67#ibcon#flushed, iclass 17, count 2 2006.257.11:28:19.67#ibcon#about to write, iclass 17, count 2 2006.257.11:28:19.67#ibcon#wrote, iclass 17, count 2 2006.257.11:28:19.67#ibcon#about to read 3, iclass 17, count 2 2006.257.11:28:19.69#ibcon#read 3, iclass 17, count 2 2006.257.11:28:19.69#ibcon#about to read 4, iclass 17, count 2 2006.257.11:28:19.69#ibcon#read 4, iclass 17, count 2 2006.257.11:28:19.69#ibcon#about to read 5, iclass 17, count 2 2006.257.11:28:19.69#ibcon#read 5, iclass 17, count 2 2006.257.11:28:19.69#ibcon#about to read 6, iclass 17, count 2 2006.257.11:28:19.69#ibcon#read 6, iclass 17, count 2 2006.257.11:28:19.69#ibcon#end of sib2, iclass 17, count 2 2006.257.11:28:19.69#ibcon#*mode == 0, iclass 17, count 2 2006.257.11:28:19.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.11:28:19.69#ibcon#[25=AT08-04\r\n] 2006.257.11:28:19.69#ibcon#*before write, iclass 17, count 2 2006.257.11:28:19.69#ibcon#enter sib2, iclass 17, count 2 2006.257.11:28:19.69#ibcon#flushed, iclass 17, count 2 2006.257.11:28:19.69#ibcon#about to write, iclass 17, count 2 2006.257.11:28:19.69#ibcon#wrote, iclass 17, count 2 2006.257.11:28:19.69#ibcon#about to read 3, iclass 17, count 2 2006.257.11:28:19.72#ibcon#read 3, iclass 17, count 2 2006.257.11:28:19.72#ibcon#about to read 4, iclass 17, count 2 2006.257.11:28:19.72#ibcon#read 4, iclass 17, count 2 2006.257.11:28:19.72#ibcon#about to read 5, iclass 17, count 2 2006.257.11:28:19.72#ibcon#read 5, iclass 17, count 2 2006.257.11:28:19.72#ibcon#about to read 6, iclass 17, count 2 2006.257.11:28:19.72#ibcon#read 6, iclass 17, count 2 2006.257.11:28:19.72#ibcon#end of sib2, iclass 17, count 2 2006.257.11:28:19.72#ibcon#*after write, iclass 17, count 2 2006.257.11:28:19.72#ibcon#*before return 0, iclass 17, count 2 2006.257.11:28:19.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:28:19.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:28:19.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.11:28:19.72#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:19.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:28:19.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:28:19.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:28:19.84#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:28:19.84#ibcon#first serial, iclass 17, count 0 2006.257.11:28:19.84#ibcon#enter sib2, iclass 17, count 0 2006.257.11:28:19.84#ibcon#flushed, iclass 17, count 0 2006.257.11:28:19.84#ibcon#about to write, iclass 17, count 0 2006.257.11:28:19.84#ibcon#wrote, iclass 17, count 0 2006.257.11:28:19.84#ibcon#about to read 3, iclass 17, count 0 2006.257.11:28:19.86#ibcon#read 3, iclass 17, count 0 2006.257.11:28:19.86#ibcon#about to read 4, iclass 17, count 0 2006.257.11:28:19.86#ibcon#read 4, iclass 17, count 0 2006.257.11:28:19.86#ibcon#about to read 5, iclass 17, count 0 2006.257.11:28:19.86#ibcon#read 5, iclass 17, count 0 2006.257.11:28:19.86#ibcon#about to read 6, iclass 17, count 0 2006.257.11:28:19.86#ibcon#read 6, iclass 17, count 0 2006.257.11:28:19.86#ibcon#end of sib2, iclass 17, count 0 2006.257.11:28:19.86#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:28:19.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:28:19.86#ibcon#[25=USB\r\n] 2006.257.11:28:19.86#ibcon#*before write, iclass 17, count 0 2006.257.11:28:19.86#ibcon#enter sib2, iclass 17, count 0 2006.257.11:28:19.86#ibcon#flushed, iclass 17, count 0 2006.257.11:28:19.86#ibcon#about to write, iclass 17, count 0 2006.257.11:28:19.86#ibcon#wrote, iclass 17, count 0 2006.257.11:28:19.86#ibcon#about to read 3, iclass 17, count 0 2006.257.11:28:19.89#ibcon#read 3, iclass 17, count 0 2006.257.11:28:19.89#ibcon#about to read 4, iclass 17, count 0 2006.257.11:28:19.89#ibcon#read 4, iclass 17, count 0 2006.257.11:28:19.89#ibcon#about to read 5, iclass 17, count 0 2006.257.11:28:19.89#ibcon#read 5, iclass 17, count 0 2006.257.11:28:19.89#ibcon#about to read 6, iclass 17, count 0 2006.257.11:28:19.89#ibcon#read 6, iclass 17, count 0 2006.257.11:28:19.89#ibcon#end of sib2, iclass 17, count 0 2006.257.11:28:19.89#ibcon#*after write, iclass 17, count 0 2006.257.11:28:19.89#ibcon#*before return 0, iclass 17, count 0 2006.257.11:28:19.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:28:19.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:28:19.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:28:19.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:28:19.89$vck44/vblo=1,629.99 2006.257.11:28:19.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.11:28:19.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.11:28:19.90#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:19.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:28:19.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:28:19.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:28:19.90#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:28:19.90#ibcon#first serial, iclass 19, count 0 2006.257.11:28:19.90#ibcon#enter sib2, iclass 19, count 0 2006.257.11:28:19.90#ibcon#flushed, iclass 19, count 0 2006.257.11:28:19.90#ibcon#about to write, iclass 19, count 0 2006.257.11:28:19.90#ibcon#wrote, iclass 19, count 0 2006.257.11:28:19.90#ibcon#about to read 3, iclass 19, count 0 2006.257.11:28:19.91#ibcon#read 3, iclass 19, count 0 2006.257.11:28:19.91#ibcon#about to read 4, iclass 19, count 0 2006.257.11:28:19.91#ibcon#read 4, iclass 19, count 0 2006.257.11:28:19.91#ibcon#about to read 5, iclass 19, count 0 2006.257.11:28:19.91#ibcon#read 5, iclass 19, count 0 2006.257.11:28:19.91#ibcon#about to read 6, iclass 19, count 0 2006.257.11:28:19.91#ibcon#read 6, iclass 19, count 0 2006.257.11:28:19.91#ibcon#end of sib2, iclass 19, count 0 2006.257.11:28:19.91#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:28:19.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:28:19.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:28:19.91#ibcon#*before write, iclass 19, count 0 2006.257.11:28:19.91#ibcon#enter sib2, iclass 19, count 0 2006.257.11:28:19.91#ibcon#flushed, iclass 19, count 0 2006.257.11:28:19.91#ibcon#about to write, iclass 19, count 0 2006.257.11:28:19.91#ibcon#wrote, iclass 19, count 0 2006.257.11:28:19.91#ibcon#about to read 3, iclass 19, count 0 2006.257.11:28:19.95#ibcon#read 3, iclass 19, count 0 2006.257.11:28:19.95#ibcon#about to read 4, iclass 19, count 0 2006.257.11:28:19.95#ibcon#read 4, iclass 19, count 0 2006.257.11:28:19.95#ibcon#about to read 5, iclass 19, count 0 2006.257.11:28:19.95#ibcon#read 5, iclass 19, count 0 2006.257.11:28:19.95#ibcon#about to read 6, iclass 19, count 0 2006.257.11:28:19.95#ibcon#read 6, iclass 19, count 0 2006.257.11:28:19.95#ibcon#end of sib2, iclass 19, count 0 2006.257.11:28:19.95#ibcon#*after write, iclass 19, count 0 2006.257.11:28:19.95#ibcon#*before return 0, iclass 19, count 0 2006.257.11:28:19.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:28:19.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:28:19.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:28:19.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:28:19.95$vck44/vb=1,4 2006.257.11:28:19.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.11:28:19.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.11:28:19.96#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:19.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:28:19.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:28:19.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:28:19.96#ibcon#enter wrdev, iclass 21, count 2 2006.257.11:28:19.96#ibcon#first serial, iclass 21, count 2 2006.257.11:28:19.96#ibcon#enter sib2, iclass 21, count 2 2006.257.11:28:19.96#ibcon#flushed, iclass 21, count 2 2006.257.11:28:19.96#ibcon#about to write, iclass 21, count 2 2006.257.11:28:19.96#ibcon#wrote, iclass 21, count 2 2006.257.11:28:19.96#ibcon#about to read 3, iclass 21, count 2 2006.257.11:28:19.97#ibcon#read 3, iclass 21, count 2 2006.257.11:28:19.97#ibcon#about to read 4, iclass 21, count 2 2006.257.11:28:19.97#ibcon#read 4, iclass 21, count 2 2006.257.11:28:19.97#ibcon#about to read 5, iclass 21, count 2 2006.257.11:28:19.97#ibcon#read 5, iclass 21, count 2 2006.257.11:28:19.97#ibcon#about to read 6, iclass 21, count 2 2006.257.11:28:19.97#ibcon#read 6, iclass 21, count 2 2006.257.11:28:19.97#ibcon#end of sib2, iclass 21, count 2 2006.257.11:28:19.97#ibcon#*mode == 0, iclass 21, count 2 2006.257.11:28:19.97#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.11:28:19.97#ibcon#[27=AT01-04\r\n] 2006.257.11:28:19.97#ibcon#*before write, iclass 21, count 2 2006.257.11:28:19.97#ibcon#enter sib2, iclass 21, count 2 2006.257.11:28:19.97#ibcon#flushed, iclass 21, count 2 2006.257.11:28:19.97#ibcon#about to write, iclass 21, count 2 2006.257.11:28:19.97#ibcon#wrote, iclass 21, count 2 2006.257.11:28:19.97#ibcon#about to read 3, iclass 21, count 2 2006.257.11:28:20.00#ibcon#read 3, iclass 21, count 2 2006.257.11:28:20.00#ibcon#about to read 4, iclass 21, count 2 2006.257.11:28:20.00#ibcon#read 4, iclass 21, count 2 2006.257.11:28:20.00#ibcon#about to read 5, iclass 21, count 2 2006.257.11:28:20.00#ibcon#read 5, iclass 21, count 2 2006.257.11:28:20.00#ibcon#about to read 6, iclass 21, count 2 2006.257.11:28:20.00#ibcon#read 6, iclass 21, count 2 2006.257.11:28:20.00#ibcon#end of sib2, iclass 21, count 2 2006.257.11:28:20.00#ibcon#*after write, iclass 21, count 2 2006.257.11:28:20.00#ibcon#*before return 0, iclass 21, count 2 2006.257.11:28:20.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:28:20.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:28:20.00#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.11:28:20.00#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:20.00#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:28:20.12#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:28:20.12#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:28:20.12#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:28:20.12#ibcon#first serial, iclass 21, count 0 2006.257.11:28:20.12#ibcon#enter sib2, iclass 21, count 0 2006.257.11:28:20.12#ibcon#flushed, iclass 21, count 0 2006.257.11:28:20.12#ibcon#about to write, iclass 21, count 0 2006.257.11:28:20.12#ibcon#wrote, iclass 21, count 0 2006.257.11:28:20.12#ibcon#about to read 3, iclass 21, count 0 2006.257.11:28:20.14#ibcon#read 3, iclass 21, count 0 2006.257.11:28:20.14#ibcon#about to read 4, iclass 21, count 0 2006.257.11:28:20.14#ibcon#read 4, iclass 21, count 0 2006.257.11:28:20.14#ibcon#about to read 5, iclass 21, count 0 2006.257.11:28:20.14#ibcon#read 5, iclass 21, count 0 2006.257.11:28:20.14#ibcon#about to read 6, iclass 21, count 0 2006.257.11:28:20.14#ibcon#read 6, iclass 21, count 0 2006.257.11:28:20.14#ibcon#end of sib2, iclass 21, count 0 2006.257.11:28:20.14#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:28:20.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:28:20.14#ibcon#[27=USB\r\n] 2006.257.11:28:20.14#ibcon#*before write, iclass 21, count 0 2006.257.11:28:20.14#ibcon#enter sib2, iclass 21, count 0 2006.257.11:28:20.14#ibcon#flushed, iclass 21, count 0 2006.257.11:28:20.14#ibcon#about to write, iclass 21, count 0 2006.257.11:28:20.14#ibcon#wrote, iclass 21, count 0 2006.257.11:28:20.14#ibcon#about to read 3, iclass 21, count 0 2006.257.11:28:20.17#ibcon#read 3, iclass 21, count 0 2006.257.11:28:20.17#ibcon#about to read 4, iclass 21, count 0 2006.257.11:28:20.17#ibcon#read 4, iclass 21, count 0 2006.257.11:28:20.17#ibcon#about to read 5, iclass 21, count 0 2006.257.11:28:20.17#ibcon#read 5, iclass 21, count 0 2006.257.11:28:20.17#ibcon#about to read 6, iclass 21, count 0 2006.257.11:28:20.17#ibcon#read 6, iclass 21, count 0 2006.257.11:28:20.17#ibcon#end of sib2, iclass 21, count 0 2006.257.11:28:20.17#ibcon#*after write, iclass 21, count 0 2006.257.11:28:20.17#ibcon#*before return 0, iclass 21, count 0 2006.257.11:28:20.17#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:28:20.17#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:28:20.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:28:20.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:28:20.18$vck44/vblo=2,634.99 2006.257.11:28:20.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.11:28:20.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.11:28:20.18#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:20.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:20.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:20.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:20.18#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:28:20.18#ibcon#first serial, iclass 23, count 0 2006.257.11:28:20.18#ibcon#enter sib2, iclass 23, count 0 2006.257.11:28:20.18#ibcon#flushed, iclass 23, count 0 2006.257.11:28:20.18#ibcon#about to write, iclass 23, count 0 2006.257.11:28:20.18#ibcon#wrote, iclass 23, count 0 2006.257.11:28:20.18#ibcon#about to read 3, iclass 23, count 0 2006.257.11:28:20.19#ibcon#read 3, iclass 23, count 0 2006.257.11:28:20.19#ibcon#about to read 4, iclass 23, count 0 2006.257.11:28:20.19#ibcon#read 4, iclass 23, count 0 2006.257.11:28:20.19#ibcon#about to read 5, iclass 23, count 0 2006.257.11:28:20.19#ibcon#read 5, iclass 23, count 0 2006.257.11:28:20.19#ibcon#about to read 6, iclass 23, count 0 2006.257.11:28:20.19#ibcon#read 6, iclass 23, count 0 2006.257.11:28:20.19#ibcon#end of sib2, iclass 23, count 0 2006.257.11:28:20.19#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:28:20.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:28:20.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:28:20.19#ibcon#*before write, iclass 23, count 0 2006.257.11:28:20.19#ibcon#enter sib2, iclass 23, count 0 2006.257.11:28:20.19#ibcon#flushed, iclass 23, count 0 2006.257.11:28:20.19#ibcon#about to write, iclass 23, count 0 2006.257.11:28:20.19#ibcon#wrote, iclass 23, count 0 2006.257.11:28:20.19#ibcon#about to read 3, iclass 23, count 0 2006.257.11:28:20.23#ibcon#read 3, iclass 23, count 0 2006.257.11:28:20.23#ibcon#about to read 4, iclass 23, count 0 2006.257.11:28:20.23#ibcon#read 4, iclass 23, count 0 2006.257.11:28:20.23#ibcon#about to read 5, iclass 23, count 0 2006.257.11:28:20.23#ibcon#read 5, iclass 23, count 0 2006.257.11:28:20.23#ibcon#about to read 6, iclass 23, count 0 2006.257.11:28:20.23#ibcon#read 6, iclass 23, count 0 2006.257.11:28:20.23#ibcon#end of sib2, iclass 23, count 0 2006.257.11:28:20.23#ibcon#*after write, iclass 23, count 0 2006.257.11:28:20.23#ibcon#*before return 0, iclass 23, count 0 2006.257.11:28:20.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:20.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:28:20.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:28:20.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:28:20.23$vck44/vb=2,5 2006.257.11:28:20.24#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.11:28:20.24#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.11:28:20.24#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:20.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:20.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:20.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:20.28#ibcon#enter wrdev, iclass 25, count 2 2006.257.11:28:20.28#ibcon#first serial, iclass 25, count 2 2006.257.11:28:20.28#ibcon#enter sib2, iclass 25, count 2 2006.257.11:28:20.28#ibcon#flushed, iclass 25, count 2 2006.257.11:28:20.28#ibcon#about to write, iclass 25, count 2 2006.257.11:28:20.28#ibcon#wrote, iclass 25, count 2 2006.257.11:28:20.28#ibcon#about to read 3, iclass 25, count 2 2006.257.11:28:20.30#ibcon#read 3, iclass 25, count 2 2006.257.11:28:20.30#ibcon#about to read 4, iclass 25, count 2 2006.257.11:28:20.30#ibcon#read 4, iclass 25, count 2 2006.257.11:28:20.30#ibcon#about to read 5, iclass 25, count 2 2006.257.11:28:20.30#ibcon#read 5, iclass 25, count 2 2006.257.11:28:20.30#ibcon#about to read 6, iclass 25, count 2 2006.257.11:28:20.30#ibcon#read 6, iclass 25, count 2 2006.257.11:28:20.30#ibcon#end of sib2, iclass 25, count 2 2006.257.11:28:20.30#ibcon#*mode == 0, iclass 25, count 2 2006.257.11:28:20.30#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.11:28:20.30#ibcon#[27=AT02-05\r\n] 2006.257.11:28:20.30#ibcon#*before write, iclass 25, count 2 2006.257.11:28:20.30#ibcon#enter sib2, iclass 25, count 2 2006.257.11:28:20.30#ibcon#flushed, iclass 25, count 2 2006.257.11:28:20.30#ibcon#about to write, iclass 25, count 2 2006.257.11:28:20.30#ibcon#wrote, iclass 25, count 2 2006.257.11:28:20.30#ibcon#about to read 3, iclass 25, count 2 2006.257.11:28:20.33#ibcon#read 3, iclass 25, count 2 2006.257.11:28:20.33#ibcon#about to read 4, iclass 25, count 2 2006.257.11:28:20.33#ibcon#read 4, iclass 25, count 2 2006.257.11:28:20.33#ibcon#about to read 5, iclass 25, count 2 2006.257.11:28:20.33#ibcon#read 5, iclass 25, count 2 2006.257.11:28:20.33#ibcon#about to read 6, iclass 25, count 2 2006.257.11:28:20.33#ibcon#read 6, iclass 25, count 2 2006.257.11:28:20.33#ibcon#end of sib2, iclass 25, count 2 2006.257.11:28:20.33#ibcon#*after write, iclass 25, count 2 2006.257.11:28:20.33#ibcon#*before return 0, iclass 25, count 2 2006.257.11:28:20.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:20.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:28:20.33#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.11:28:20.33#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:20.33#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:20.45#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:20.45#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:20.45#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:28:20.45#ibcon#first serial, iclass 25, count 0 2006.257.11:28:20.45#ibcon#enter sib2, iclass 25, count 0 2006.257.11:28:20.45#ibcon#flushed, iclass 25, count 0 2006.257.11:28:20.45#ibcon#about to write, iclass 25, count 0 2006.257.11:28:20.45#ibcon#wrote, iclass 25, count 0 2006.257.11:28:20.45#ibcon#about to read 3, iclass 25, count 0 2006.257.11:28:20.47#ibcon#read 3, iclass 25, count 0 2006.257.11:28:20.47#ibcon#about to read 4, iclass 25, count 0 2006.257.11:28:20.47#ibcon#read 4, iclass 25, count 0 2006.257.11:28:20.47#ibcon#about to read 5, iclass 25, count 0 2006.257.11:28:20.47#ibcon#read 5, iclass 25, count 0 2006.257.11:28:20.47#ibcon#about to read 6, iclass 25, count 0 2006.257.11:28:20.47#ibcon#read 6, iclass 25, count 0 2006.257.11:28:20.47#ibcon#end of sib2, iclass 25, count 0 2006.257.11:28:20.47#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:28:20.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:28:20.47#ibcon#[27=USB\r\n] 2006.257.11:28:20.47#ibcon#*before write, iclass 25, count 0 2006.257.11:28:20.47#ibcon#enter sib2, iclass 25, count 0 2006.257.11:28:20.47#ibcon#flushed, iclass 25, count 0 2006.257.11:28:20.47#ibcon#about to write, iclass 25, count 0 2006.257.11:28:20.47#ibcon#wrote, iclass 25, count 0 2006.257.11:28:20.47#ibcon#about to read 3, iclass 25, count 0 2006.257.11:28:20.50#ibcon#read 3, iclass 25, count 0 2006.257.11:28:20.50#ibcon#about to read 4, iclass 25, count 0 2006.257.11:28:20.50#ibcon#read 4, iclass 25, count 0 2006.257.11:28:20.50#ibcon#about to read 5, iclass 25, count 0 2006.257.11:28:20.50#ibcon#read 5, iclass 25, count 0 2006.257.11:28:20.50#ibcon#about to read 6, iclass 25, count 0 2006.257.11:28:20.50#ibcon#read 6, iclass 25, count 0 2006.257.11:28:20.50#ibcon#end of sib2, iclass 25, count 0 2006.257.11:28:20.50#ibcon#*after write, iclass 25, count 0 2006.257.11:28:20.50#ibcon#*before return 0, iclass 25, count 0 2006.257.11:28:20.50#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:20.50#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:28:20.50#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:28:20.50#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:28:20.50$vck44/vblo=3,649.99 2006.257.11:28:20.51#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.11:28:20.51#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.11:28:20.51#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:20.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:20.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:20.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:20.51#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:28:20.51#ibcon#first serial, iclass 27, count 0 2006.257.11:28:20.51#ibcon#enter sib2, iclass 27, count 0 2006.257.11:28:20.51#ibcon#flushed, iclass 27, count 0 2006.257.11:28:20.51#ibcon#about to write, iclass 27, count 0 2006.257.11:28:20.51#ibcon#wrote, iclass 27, count 0 2006.257.11:28:20.51#ibcon#about to read 3, iclass 27, count 0 2006.257.11:28:20.52#ibcon#read 3, iclass 27, count 0 2006.257.11:28:20.52#ibcon#about to read 4, iclass 27, count 0 2006.257.11:28:20.52#ibcon#read 4, iclass 27, count 0 2006.257.11:28:20.52#ibcon#about to read 5, iclass 27, count 0 2006.257.11:28:20.52#ibcon#read 5, iclass 27, count 0 2006.257.11:28:20.52#ibcon#about to read 6, iclass 27, count 0 2006.257.11:28:20.52#ibcon#read 6, iclass 27, count 0 2006.257.11:28:20.52#ibcon#end of sib2, iclass 27, count 0 2006.257.11:28:20.52#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:28:20.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:28:20.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:28:20.52#ibcon#*before write, iclass 27, count 0 2006.257.11:28:20.52#ibcon#enter sib2, iclass 27, count 0 2006.257.11:28:20.52#ibcon#flushed, iclass 27, count 0 2006.257.11:28:20.52#ibcon#about to write, iclass 27, count 0 2006.257.11:28:20.52#ibcon#wrote, iclass 27, count 0 2006.257.11:28:20.56#ibcon#about to read 3, iclass 27, count 0 2006.257.11:28:20.56#ibcon#read 3, iclass 27, count 0 2006.257.11:28:20.56#ibcon#about to read 4, iclass 27, count 0 2006.257.11:28:20.57#ibcon#read 4, iclass 27, count 0 2006.257.11:28:20.57#ibcon#about to read 5, iclass 27, count 0 2006.257.11:28:20.57#ibcon#read 5, iclass 27, count 0 2006.257.11:28:20.57#ibcon#about to read 6, iclass 27, count 0 2006.257.11:28:20.57#ibcon#read 6, iclass 27, count 0 2006.257.11:28:20.57#ibcon#end of sib2, iclass 27, count 0 2006.257.11:28:20.57#ibcon#*after write, iclass 27, count 0 2006.257.11:28:20.57#ibcon#*before return 0, iclass 27, count 0 2006.257.11:28:20.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:20.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:28:20.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:28:20.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:28:20.57$vck44/vb=3,4 2006.257.11:28:20.57#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.11:28:20.57#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.11:28:20.57#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:20.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:20.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:20.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:20.61#ibcon#enter wrdev, iclass 29, count 2 2006.257.11:28:20.61#ibcon#first serial, iclass 29, count 2 2006.257.11:28:20.61#ibcon#enter sib2, iclass 29, count 2 2006.257.11:28:20.61#ibcon#flushed, iclass 29, count 2 2006.257.11:28:20.61#ibcon#about to write, iclass 29, count 2 2006.257.11:28:20.61#ibcon#wrote, iclass 29, count 2 2006.257.11:28:20.61#ibcon#about to read 3, iclass 29, count 2 2006.257.11:28:20.63#ibcon#read 3, iclass 29, count 2 2006.257.11:28:20.63#ibcon#about to read 4, iclass 29, count 2 2006.257.11:28:20.63#ibcon#read 4, iclass 29, count 2 2006.257.11:28:20.63#ibcon#about to read 5, iclass 29, count 2 2006.257.11:28:20.63#ibcon#read 5, iclass 29, count 2 2006.257.11:28:20.63#ibcon#about to read 6, iclass 29, count 2 2006.257.11:28:20.63#ibcon#read 6, iclass 29, count 2 2006.257.11:28:20.63#ibcon#end of sib2, iclass 29, count 2 2006.257.11:28:20.63#ibcon#*mode == 0, iclass 29, count 2 2006.257.11:28:20.63#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.11:28:20.63#ibcon#[27=AT03-04\r\n] 2006.257.11:28:20.63#ibcon#*before write, iclass 29, count 2 2006.257.11:28:20.63#ibcon#enter sib2, iclass 29, count 2 2006.257.11:28:20.63#ibcon#flushed, iclass 29, count 2 2006.257.11:28:20.63#ibcon#about to write, iclass 29, count 2 2006.257.11:28:20.63#ibcon#wrote, iclass 29, count 2 2006.257.11:28:20.63#ibcon#about to read 3, iclass 29, count 2 2006.257.11:28:20.66#ibcon#read 3, iclass 29, count 2 2006.257.11:28:20.66#ibcon#about to read 4, iclass 29, count 2 2006.257.11:28:20.66#ibcon#read 4, iclass 29, count 2 2006.257.11:28:20.66#ibcon#about to read 5, iclass 29, count 2 2006.257.11:28:20.66#ibcon#read 5, iclass 29, count 2 2006.257.11:28:20.66#ibcon#about to read 6, iclass 29, count 2 2006.257.11:28:20.66#ibcon#read 6, iclass 29, count 2 2006.257.11:28:20.66#ibcon#end of sib2, iclass 29, count 2 2006.257.11:28:20.66#ibcon#*after write, iclass 29, count 2 2006.257.11:28:20.66#ibcon#*before return 0, iclass 29, count 2 2006.257.11:28:20.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:20.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:28:20.66#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.11:28:20.66#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:20.66#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:20.78#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:20.78#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:20.78#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:28:20.78#ibcon#first serial, iclass 29, count 0 2006.257.11:28:20.78#ibcon#enter sib2, iclass 29, count 0 2006.257.11:28:20.78#ibcon#flushed, iclass 29, count 0 2006.257.11:28:20.78#ibcon#about to write, iclass 29, count 0 2006.257.11:28:20.78#ibcon#wrote, iclass 29, count 0 2006.257.11:28:20.78#ibcon#about to read 3, iclass 29, count 0 2006.257.11:28:20.80#ibcon#read 3, iclass 29, count 0 2006.257.11:28:20.80#ibcon#about to read 4, iclass 29, count 0 2006.257.11:28:20.80#ibcon#read 4, iclass 29, count 0 2006.257.11:28:20.80#ibcon#about to read 5, iclass 29, count 0 2006.257.11:28:20.80#ibcon#read 5, iclass 29, count 0 2006.257.11:28:20.80#ibcon#about to read 6, iclass 29, count 0 2006.257.11:28:20.80#ibcon#read 6, iclass 29, count 0 2006.257.11:28:20.80#ibcon#end of sib2, iclass 29, count 0 2006.257.11:28:20.80#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:28:20.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:28:20.80#ibcon#[27=USB\r\n] 2006.257.11:28:20.80#ibcon#*before write, iclass 29, count 0 2006.257.11:28:20.80#ibcon#enter sib2, iclass 29, count 0 2006.257.11:28:20.80#ibcon#flushed, iclass 29, count 0 2006.257.11:28:20.80#ibcon#about to write, iclass 29, count 0 2006.257.11:28:20.80#ibcon#wrote, iclass 29, count 0 2006.257.11:28:20.80#ibcon#about to read 3, iclass 29, count 0 2006.257.11:28:20.83#ibcon#read 3, iclass 29, count 0 2006.257.11:28:20.83#ibcon#about to read 4, iclass 29, count 0 2006.257.11:28:20.83#ibcon#read 4, iclass 29, count 0 2006.257.11:28:20.83#ibcon#about to read 5, iclass 29, count 0 2006.257.11:28:20.83#ibcon#read 5, iclass 29, count 0 2006.257.11:28:20.83#ibcon#about to read 6, iclass 29, count 0 2006.257.11:28:20.83#ibcon#read 6, iclass 29, count 0 2006.257.11:28:20.83#ibcon#end of sib2, iclass 29, count 0 2006.257.11:28:20.83#ibcon#*after write, iclass 29, count 0 2006.257.11:28:20.83#ibcon#*before return 0, iclass 29, count 0 2006.257.11:28:20.83#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:20.83#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:28:20.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:28:20.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:28:20.83$vck44/vblo=4,679.99 2006.257.11:28:20.84#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.11:28:20.84#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.11:28:20.84#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:20.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:20.84#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:20.84#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:20.84#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:28:20.84#ibcon#first serial, iclass 31, count 0 2006.257.11:28:20.84#ibcon#enter sib2, iclass 31, count 0 2006.257.11:28:20.84#ibcon#flushed, iclass 31, count 0 2006.257.11:28:20.84#ibcon#about to write, iclass 31, count 0 2006.257.11:28:20.84#ibcon#wrote, iclass 31, count 0 2006.257.11:28:20.84#ibcon#about to read 3, iclass 31, count 0 2006.257.11:28:20.85#ibcon#read 3, iclass 31, count 0 2006.257.11:28:20.85#ibcon#about to read 4, iclass 31, count 0 2006.257.11:28:20.85#ibcon#read 4, iclass 31, count 0 2006.257.11:28:20.85#ibcon#about to read 5, iclass 31, count 0 2006.257.11:28:20.85#ibcon#read 5, iclass 31, count 0 2006.257.11:28:20.85#ibcon#about to read 6, iclass 31, count 0 2006.257.11:28:20.85#ibcon#read 6, iclass 31, count 0 2006.257.11:28:20.85#ibcon#end of sib2, iclass 31, count 0 2006.257.11:28:20.85#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:28:20.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:28:20.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:28:20.85#ibcon#*before write, iclass 31, count 0 2006.257.11:28:20.85#ibcon#enter sib2, iclass 31, count 0 2006.257.11:28:20.85#ibcon#flushed, iclass 31, count 0 2006.257.11:28:20.85#ibcon#about to write, iclass 31, count 0 2006.257.11:28:20.85#ibcon#wrote, iclass 31, count 0 2006.257.11:28:20.85#ibcon#about to read 3, iclass 31, count 0 2006.257.11:28:20.89#ibcon#read 3, iclass 31, count 0 2006.257.11:28:20.89#ibcon#about to read 4, iclass 31, count 0 2006.257.11:28:20.89#ibcon#read 4, iclass 31, count 0 2006.257.11:28:20.89#ibcon#about to read 5, iclass 31, count 0 2006.257.11:28:20.89#ibcon#read 5, iclass 31, count 0 2006.257.11:28:20.89#ibcon#about to read 6, iclass 31, count 0 2006.257.11:28:20.89#ibcon#read 6, iclass 31, count 0 2006.257.11:28:20.89#ibcon#end of sib2, iclass 31, count 0 2006.257.11:28:20.89#ibcon#*after write, iclass 31, count 0 2006.257.11:28:20.89#ibcon#*before return 0, iclass 31, count 0 2006.257.11:28:20.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:20.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:28:20.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:28:20.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:28:20.89$vck44/vb=4,5 2006.257.11:28:20.90#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.11:28:20.90#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.11:28:20.90#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:20.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:20.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:20.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:20.94#ibcon#enter wrdev, iclass 33, count 2 2006.257.11:28:20.94#ibcon#first serial, iclass 33, count 2 2006.257.11:28:20.94#ibcon#enter sib2, iclass 33, count 2 2006.257.11:28:20.94#ibcon#flushed, iclass 33, count 2 2006.257.11:28:20.94#ibcon#about to write, iclass 33, count 2 2006.257.11:28:20.94#ibcon#wrote, iclass 33, count 2 2006.257.11:28:20.94#ibcon#about to read 3, iclass 33, count 2 2006.257.11:28:20.96#ibcon#read 3, iclass 33, count 2 2006.257.11:28:20.96#ibcon#about to read 4, iclass 33, count 2 2006.257.11:28:20.96#ibcon#read 4, iclass 33, count 2 2006.257.11:28:20.96#ibcon#about to read 5, iclass 33, count 2 2006.257.11:28:20.96#ibcon#read 5, iclass 33, count 2 2006.257.11:28:20.96#ibcon#about to read 6, iclass 33, count 2 2006.257.11:28:20.96#ibcon#read 6, iclass 33, count 2 2006.257.11:28:20.96#ibcon#end of sib2, iclass 33, count 2 2006.257.11:28:20.96#ibcon#*mode == 0, iclass 33, count 2 2006.257.11:28:20.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.11:28:20.96#ibcon#[27=AT04-05\r\n] 2006.257.11:28:20.96#ibcon#*before write, iclass 33, count 2 2006.257.11:28:20.96#ibcon#enter sib2, iclass 33, count 2 2006.257.11:28:20.96#ibcon#flushed, iclass 33, count 2 2006.257.11:28:20.96#ibcon#about to write, iclass 33, count 2 2006.257.11:28:20.96#ibcon#wrote, iclass 33, count 2 2006.257.11:28:20.96#ibcon#about to read 3, iclass 33, count 2 2006.257.11:28:20.99#ibcon#read 3, iclass 33, count 2 2006.257.11:28:20.99#ibcon#about to read 4, iclass 33, count 2 2006.257.11:28:20.99#ibcon#read 4, iclass 33, count 2 2006.257.11:28:20.99#ibcon#about to read 5, iclass 33, count 2 2006.257.11:28:20.99#ibcon#read 5, iclass 33, count 2 2006.257.11:28:20.99#ibcon#about to read 6, iclass 33, count 2 2006.257.11:28:20.99#ibcon#read 6, iclass 33, count 2 2006.257.11:28:20.99#ibcon#end of sib2, iclass 33, count 2 2006.257.11:28:20.99#ibcon#*after write, iclass 33, count 2 2006.257.11:28:20.99#ibcon#*before return 0, iclass 33, count 2 2006.257.11:28:20.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:20.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:28:20.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.11:28:20.99#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:20.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:21.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:21.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:21.11#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:28:21.11#ibcon#first serial, iclass 33, count 0 2006.257.11:28:21.11#ibcon#enter sib2, iclass 33, count 0 2006.257.11:28:21.11#ibcon#flushed, iclass 33, count 0 2006.257.11:28:21.11#ibcon#about to write, iclass 33, count 0 2006.257.11:28:21.11#ibcon#wrote, iclass 33, count 0 2006.257.11:28:21.11#ibcon#about to read 3, iclass 33, count 0 2006.257.11:28:21.13#ibcon#read 3, iclass 33, count 0 2006.257.11:28:21.13#ibcon#about to read 4, iclass 33, count 0 2006.257.11:28:21.13#ibcon#read 4, iclass 33, count 0 2006.257.11:28:21.13#ibcon#about to read 5, iclass 33, count 0 2006.257.11:28:21.13#ibcon#read 5, iclass 33, count 0 2006.257.11:28:21.13#ibcon#about to read 6, iclass 33, count 0 2006.257.11:28:21.13#ibcon#read 6, iclass 33, count 0 2006.257.11:28:21.13#ibcon#end of sib2, iclass 33, count 0 2006.257.11:28:21.13#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:28:21.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:28:21.13#ibcon#[27=USB\r\n] 2006.257.11:28:21.13#ibcon#*before write, iclass 33, count 0 2006.257.11:28:21.13#ibcon#enter sib2, iclass 33, count 0 2006.257.11:28:21.13#ibcon#flushed, iclass 33, count 0 2006.257.11:28:21.13#ibcon#about to write, iclass 33, count 0 2006.257.11:28:21.13#ibcon#wrote, iclass 33, count 0 2006.257.11:28:21.13#ibcon#about to read 3, iclass 33, count 0 2006.257.11:28:21.16#ibcon#read 3, iclass 33, count 0 2006.257.11:28:21.16#ibcon#about to read 4, iclass 33, count 0 2006.257.11:28:21.16#ibcon#read 4, iclass 33, count 0 2006.257.11:28:21.16#ibcon#about to read 5, iclass 33, count 0 2006.257.11:28:21.16#ibcon#read 5, iclass 33, count 0 2006.257.11:28:21.16#ibcon#about to read 6, iclass 33, count 0 2006.257.11:28:21.16#ibcon#read 6, iclass 33, count 0 2006.257.11:28:21.16#ibcon#end of sib2, iclass 33, count 0 2006.257.11:28:21.16#ibcon#*after write, iclass 33, count 0 2006.257.11:28:21.16#ibcon#*before return 0, iclass 33, count 0 2006.257.11:28:21.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:21.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:28:21.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:28:21.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:28:21.16$vck44/vblo=5,709.99 2006.257.11:28:21.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.11:28:21.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.11:28:21.17#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:21.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:21.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:21.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:21.17#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:28:21.17#ibcon#first serial, iclass 35, count 0 2006.257.11:28:21.17#ibcon#enter sib2, iclass 35, count 0 2006.257.11:28:21.17#ibcon#flushed, iclass 35, count 0 2006.257.11:28:21.17#ibcon#about to write, iclass 35, count 0 2006.257.11:28:21.17#ibcon#wrote, iclass 35, count 0 2006.257.11:28:21.17#ibcon#about to read 3, iclass 35, count 0 2006.257.11:28:21.18#ibcon#read 3, iclass 35, count 0 2006.257.11:28:21.18#ibcon#about to read 4, iclass 35, count 0 2006.257.11:28:21.18#ibcon#read 4, iclass 35, count 0 2006.257.11:28:21.18#ibcon#about to read 5, iclass 35, count 0 2006.257.11:28:21.18#ibcon#read 5, iclass 35, count 0 2006.257.11:28:21.18#ibcon#about to read 6, iclass 35, count 0 2006.257.11:28:21.18#ibcon#read 6, iclass 35, count 0 2006.257.11:28:21.18#ibcon#end of sib2, iclass 35, count 0 2006.257.11:28:21.18#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:28:21.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:28:21.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:28:21.18#ibcon#*before write, iclass 35, count 0 2006.257.11:28:21.18#ibcon#enter sib2, iclass 35, count 0 2006.257.11:28:21.18#ibcon#flushed, iclass 35, count 0 2006.257.11:28:21.18#ibcon#about to write, iclass 35, count 0 2006.257.11:28:21.18#ibcon#wrote, iclass 35, count 0 2006.257.11:28:21.18#ibcon#about to read 3, iclass 35, count 0 2006.257.11:28:21.22#ibcon#read 3, iclass 35, count 0 2006.257.11:28:21.22#ibcon#about to read 4, iclass 35, count 0 2006.257.11:28:21.22#ibcon#read 4, iclass 35, count 0 2006.257.11:28:21.22#ibcon#about to read 5, iclass 35, count 0 2006.257.11:28:21.22#ibcon#read 5, iclass 35, count 0 2006.257.11:28:21.22#ibcon#about to read 6, iclass 35, count 0 2006.257.11:28:21.22#ibcon#read 6, iclass 35, count 0 2006.257.11:28:21.22#ibcon#end of sib2, iclass 35, count 0 2006.257.11:28:21.22#ibcon#*after write, iclass 35, count 0 2006.257.11:28:21.22#ibcon#*before return 0, iclass 35, count 0 2006.257.11:28:21.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:21.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:28:21.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:28:21.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:28:21.22$vck44/vb=5,4 2006.257.11:28:21.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.11:28:21.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.11:28:21.23#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:21.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:21.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:21.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:21.27#ibcon#enter wrdev, iclass 37, count 2 2006.257.11:28:21.27#ibcon#first serial, iclass 37, count 2 2006.257.11:28:21.27#ibcon#enter sib2, iclass 37, count 2 2006.257.11:28:21.27#ibcon#flushed, iclass 37, count 2 2006.257.11:28:21.27#ibcon#about to write, iclass 37, count 2 2006.257.11:28:21.27#ibcon#wrote, iclass 37, count 2 2006.257.11:28:21.27#ibcon#about to read 3, iclass 37, count 2 2006.257.11:28:21.29#ibcon#read 3, iclass 37, count 2 2006.257.11:28:21.29#ibcon#about to read 4, iclass 37, count 2 2006.257.11:28:21.29#ibcon#read 4, iclass 37, count 2 2006.257.11:28:21.29#ibcon#about to read 5, iclass 37, count 2 2006.257.11:28:21.29#ibcon#read 5, iclass 37, count 2 2006.257.11:28:21.29#ibcon#about to read 6, iclass 37, count 2 2006.257.11:28:21.29#ibcon#read 6, iclass 37, count 2 2006.257.11:28:21.29#ibcon#end of sib2, iclass 37, count 2 2006.257.11:28:21.29#ibcon#*mode == 0, iclass 37, count 2 2006.257.11:28:21.29#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.11:28:21.29#ibcon#[27=AT05-04\r\n] 2006.257.11:28:21.29#ibcon#*before write, iclass 37, count 2 2006.257.11:28:21.29#ibcon#enter sib2, iclass 37, count 2 2006.257.11:28:21.29#ibcon#flushed, iclass 37, count 2 2006.257.11:28:21.29#ibcon#about to write, iclass 37, count 2 2006.257.11:28:21.29#ibcon#wrote, iclass 37, count 2 2006.257.11:28:21.29#ibcon#about to read 3, iclass 37, count 2 2006.257.11:28:21.32#ibcon#read 3, iclass 37, count 2 2006.257.11:28:21.32#ibcon#about to read 4, iclass 37, count 2 2006.257.11:28:21.32#ibcon#read 4, iclass 37, count 2 2006.257.11:28:21.32#ibcon#about to read 5, iclass 37, count 2 2006.257.11:28:21.32#ibcon#read 5, iclass 37, count 2 2006.257.11:28:21.32#ibcon#about to read 6, iclass 37, count 2 2006.257.11:28:21.32#ibcon#read 6, iclass 37, count 2 2006.257.11:28:21.32#ibcon#end of sib2, iclass 37, count 2 2006.257.11:28:21.32#ibcon#*after write, iclass 37, count 2 2006.257.11:28:21.32#ibcon#*before return 0, iclass 37, count 2 2006.257.11:28:21.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:21.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:28:21.32#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.11:28:21.32#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:21.32#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:21.44#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:21.44#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:21.44#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:28:21.44#ibcon#first serial, iclass 37, count 0 2006.257.11:28:21.44#ibcon#enter sib2, iclass 37, count 0 2006.257.11:28:21.44#ibcon#flushed, iclass 37, count 0 2006.257.11:28:21.44#ibcon#about to write, iclass 37, count 0 2006.257.11:28:21.44#ibcon#wrote, iclass 37, count 0 2006.257.11:28:21.44#ibcon#about to read 3, iclass 37, count 0 2006.257.11:28:21.46#ibcon#read 3, iclass 37, count 0 2006.257.11:28:21.46#ibcon#about to read 4, iclass 37, count 0 2006.257.11:28:21.46#ibcon#read 4, iclass 37, count 0 2006.257.11:28:21.46#ibcon#about to read 5, iclass 37, count 0 2006.257.11:28:21.46#ibcon#read 5, iclass 37, count 0 2006.257.11:28:21.46#ibcon#about to read 6, iclass 37, count 0 2006.257.11:28:21.46#ibcon#read 6, iclass 37, count 0 2006.257.11:28:21.46#ibcon#end of sib2, iclass 37, count 0 2006.257.11:28:21.46#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:28:21.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:28:21.46#ibcon#[27=USB\r\n] 2006.257.11:28:21.46#ibcon#*before write, iclass 37, count 0 2006.257.11:28:21.46#ibcon#enter sib2, iclass 37, count 0 2006.257.11:28:21.46#ibcon#flushed, iclass 37, count 0 2006.257.11:28:21.46#ibcon#about to write, iclass 37, count 0 2006.257.11:28:21.46#ibcon#wrote, iclass 37, count 0 2006.257.11:28:21.46#ibcon#about to read 3, iclass 37, count 0 2006.257.11:28:21.49#ibcon#read 3, iclass 37, count 0 2006.257.11:28:21.49#ibcon#about to read 4, iclass 37, count 0 2006.257.11:28:21.49#ibcon#read 4, iclass 37, count 0 2006.257.11:28:21.49#ibcon#about to read 5, iclass 37, count 0 2006.257.11:28:21.49#ibcon#read 5, iclass 37, count 0 2006.257.11:28:21.49#ibcon#about to read 6, iclass 37, count 0 2006.257.11:28:21.49#ibcon#read 6, iclass 37, count 0 2006.257.11:28:21.49#ibcon#end of sib2, iclass 37, count 0 2006.257.11:28:21.49#ibcon#*after write, iclass 37, count 0 2006.257.11:28:21.49#ibcon#*before return 0, iclass 37, count 0 2006.257.11:28:21.49#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:21.49#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:28:21.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:28:21.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:28:21.50$vck44/vblo=6,719.99 2006.257.11:28:21.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.11:28:21.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.11:28:21.50#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:21.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:21.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:21.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:21.50#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:28:21.50#ibcon#first serial, iclass 39, count 0 2006.257.11:28:21.50#ibcon#enter sib2, iclass 39, count 0 2006.257.11:28:21.50#ibcon#flushed, iclass 39, count 0 2006.257.11:28:21.50#ibcon#about to write, iclass 39, count 0 2006.257.11:28:21.50#ibcon#wrote, iclass 39, count 0 2006.257.11:28:21.50#ibcon#about to read 3, iclass 39, count 0 2006.257.11:28:21.51#ibcon#read 3, iclass 39, count 0 2006.257.11:28:21.51#ibcon#about to read 4, iclass 39, count 0 2006.257.11:28:21.51#ibcon#read 4, iclass 39, count 0 2006.257.11:28:21.51#ibcon#about to read 5, iclass 39, count 0 2006.257.11:28:21.51#ibcon#read 5, iclass 39, count 0 2006.257.11:28:21.51#ibcon#about to read 6, iclass 39, count 0 2006.257.11:28:21.51#ibcon#read 6, iclass 39, count 0 2006.257.11:28:21.51#ibcon#end of sib2, iclass 39, count 0 2006.257.11:28:21.51#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:28:21.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:28:21.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:28:21.51#ibcon#*before write, iclass 39, count 0 2006.257.11:28:21.51#ibcon#enter sib2, iclass 39, count 0 2006.257.11:28:21.51#ibcon#flushed, iclass 39, count 0 2006.257.11:28:21.51#ibcon#about to write, iclass 39, count 0 2006.257.11:28:21.51#ibcon#wrote, iclass 39, count 0 2006.257.11:28:21.51#ibcon#about to read 3, iclass 39, count 0 2006.257.11:28:21.55#ibcon#read 3, iclass 39, count 0 2006.257.11:28:21.55#ibcon#about to read 4, iclass 39, count 0 2006.257.11:28:21.55#ibcon#read 4, iclass 39, count 0 2006.257.11:28:21.55#ibcon#about to read 5, iclass 39, count 0 2006.257.11:28:21.55#ibcon#read 5, iclass 39, count 0 2006.257.11:28:21.55#ibcon#about to read 6, iclass 39, count 0 2006.257.11:28:21.55#ibcon#read 6, iclass 39, count 0 2006.257.11:28:21.55#ibcon#end of sib2, iclass 39, count 0 2006.257.11:28:21.55#ibcon#*after write, iclass 39, count 0 2006.257.11:28:21.55#ibcon#*before return 0, iclass 39, count 0 2006.257.11:28:21.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:21.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:28:21.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:28:21.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:28:21.56$vck44/vb=6,4 2006.257.11:28:21.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.11:28:21.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.11:28:21.56#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:21.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:21.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:21.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:21.60#ibcon#enter wrdev, iclass 3, count 2 2006.257.11:28:21.60#ibcon#first serial, iclass 3, count 2 2006.257.11:28:21.60#ibcon#enter sib2, iclass 3, count 2 2006.257.11:28:21.60#ibcon#flushed, iclass 3, count 2 2006.257.11:28:21.60#ibcon#about to write, iclass 3, count 2 2006.257.11:28:21.60#ibcon#wrote, iclass 3, count 2 2006.257.11:28:21.60#ibcon#about to read 3, iclass 3, count 2 2006.257.11:28:21.62#ibcon#read 3, iclass 3, count 2 2006.257.11:28:21.62#ibcon#about to read 4, iclass 3, count 2 2006.257.11:28:21.62#ibcon#read 4, iclass 3, count 2 2006.257.11:28:21.62#ibcon#about to read 5, iclass 3, count 2 2006.257.11:28:21.62#ibcon#read 5, iclass 3, count 2 2006.257.11:28:21.62#ibcon#about to read 6, iclass 3, count 2 2006.257.11:28:21.62#ibcon#read 6, iclass 3, count 2 2006.257.11:28:21.62#ibcon#end of sib2, iclass 3, count 2 2006.257.11:28:21.62#ibcon#*mode == 0, iclass 3, count 2 2006.257.11:28:21.62#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.11:28:21.62#ibcon#[27=AT06-04\r\n] 2006.257.11:28:21.62#ibcon#*before write, iclass 3, count 2 2006.257.11:28:21.62#ibcon#enter sib2, iclass 3, count 2 2006.257.11:28:21.62#ibcon#flushed, iclass 3, count 2 2006.257.11:28:21.62#ibcon#about to write, iclass 3, count 2 2006.257.11:28:21.62#ibcon#wrote, iclass 3, count 2 2006.257.11:28:21.62#ibcon#about to read 3, iclass 3, count 2 2006.257.11:28:21.65#ibcon#read 3, iclass 3, count 2 2006.257.11:28:21.65#ibcon#about to read 4, iclass 3, count 2 2006.257.11:28:21.65#ibcon#read 4, iclass 3, count 2 2006.257.11:28:21.65#ibcon#about to read 5, iclass 3, count 2 2006.257.11:28:21.66#ibcon#read 5, iclass 3, count 2 2006.257.11:28:21.66#ibcon#about to read 6, iclass 3, count 2 2006.257.11:28:21.66#ibcon#read 6, iclass 3, count 2 2006.257.11:28:21.66#ibcon#end of sib2, iclass 3, count 2 2006.257.11:28:21.66#ibcon#*after write, iclass 3, count 2 2006.257.11:28:21.66#ibcon#*before return 0, iclass 3, count 2 2006.257.11:28:21.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:21.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:28:21.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.11:28:21.66#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:21.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:21.77#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:21.77#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:21.77#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:28:21.77#ibcon#first serial, iclass 3, count 0 2006.257.11:28:21.77#ibcon#enter sib2, iclass 3, count 0 2006.257.11:28:21.77#ibcon#flushed, iclass 3, count 0 2006.257.11:28:21.77#ibcon#about to write, iclass 3, count 0 2006.257.11:28:21.77#ibcon#wrote, iclass 3, count 0 2006.257.11:28:21.77#ibcon#about to read 3, iclass 3, count 0 2006.257.11:28:21.79#ibcon#read 3, iclass 3, count 0 2006.257.11:28:21.79#ibcon#about to read 4, iclass 3, count 0 2006.257.11:28:21.79#ibcon#read 4, iclass 3, count 0 2006.257.11:28:21.79#ibcon#about to read 5, iclass 3, count 0 2006.257.11:28:21.79#ibcon#read 5, iclass 3, count 0 2006.257.11:28:21.79#ibcon#about to read 6, iclass 3, count 0 2006.257.11:28:21.79#ibcon#read 6, iclass 3, count 0 2006.257.11:28:21.79#ibcon#end of sib2, iclass 3, count 0 2006.257.11:28:21.79#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:28:21.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:28:21.79#ibcon#[27=USB\r\n] 2006.257.11:28:21.79#ibcon#*before write, iclass 3, count 0 2006.257.11:28:21.79#ibcon#enter sib2, iclass 3, count 0 2006.257.11:28:21.79#ibcon#flushed, iclass 3, count 0 2006.257.11:28:21.79#ibcon#about to write, iclass 3, count 0 2006.257.11:28:21.79#ibcon#wrote, iclass 3, count 0 2006.257.11:28:21.79#ibcon#about to read 3, iclass 3, count 0 2006.257.11:28:21.82#ibcon#read 3, iclass 3, count 0 2006.257.11:28:21.82#ibcon#about to read 4, iclass 3, count 0 2006.257.11:28:21.82#ibcon#read 4, iclass 3, count 0 2006.257.11:28:21.82#ibcon#about to read 5, iclass 3, count 0 2006.257.11:28:21.82#ibcon#read 5, iclass 3, count 0 2006.257.11:28:21.82#ibcon#about to read 6, iclass 3, count 0 2006.257.11:28:21.82#ibcon#read 6, iclass 3, count 0 2006.257.11:28:21.82#ibcon#end of sib2, iclass 3, count 0 2006.257.11:28:21.82#ibcon#*after write, iclass 3, count 0 2006.257.11:28:21.82#ibcon#*before return 0, iclass 3, count 0 2006.257.11:28:21.82#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:21.82#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:28:21.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:28:21.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:28:21.82$vck44/vblo=7,734.99 2006.257.11:28:21.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.11:28:21.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.11:28:21.83#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:21.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:21.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:21.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:21.83#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:28:21.83#ibcon#first serial, iclass 5, count 0 2006.257.11:28:21.83#ibcon#enter sib2, iclass 5, count 0 2006.257.11:28:21.83#ibcon#flushed, iclass 5, count 0 2006.257.11:28:21.83#ibcon#about to write, iclass 5, count 0 2006.257.11:28:21.83#ibcon#wrote, iclass 5, count 0 2006.257.11:28:21.83#ibcon#about to read 3, iclass 5, count 0 2006.257.11:28:21.84#ibcon#read 3, iclass 5, count 0 2006.257.11:28:21.84#ibcon#about to read 4, iclass 5, count 0 2006.257.11:28:21.84#ibcon#read 4, iclass 5, count 0 2006.257.11:28:21.84#ibcon#about to read 5, iclass 5, count 0 2006.257.11:28:21.84#ibcon#read 5, iclass 5, count 0 2006.257.11:28:21.84#ibcon#about to read 6, iclass 5, count 0 2006.257.11:28:21.84#ibcon#read 6, iclass 5, count 0 2006.257.11:28:21.84#ibcon#end of sib2, iclass 5, count 0 2006.257.11:28:21.84#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:28:21.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:28:21.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:28:21.84#ibcon#*before write, iclass 5, count 0 2006.257.11:28:21.84#ibcon#enter sib2, iclass 5, count 0 2006.257.11:28:21.84#ibcon#flushed, iclass 5, count 0 2006.257.11:28:21.84#ibcon#about to write, iclass 5, count 0 2006.257.11:28:21.84#ibcon#wrote, iclass 5, count 0 2006.257.11:28:21.84#ibcon#about to read 3, iclass 5, count 0 2006.257.11:28:21.88#ibcon#read 3, iclass 5, count 0 2006.257.11:28:21.88#ibcon#about to read 4, iclass 5, count 0 2006.257.11:28:21.88#ibcon#read 4, iclass 5, count 0 2006.257.11:28:21.88#ibcon#about to read 5, iclass 5, count 0 2006.257.11:28:21.88#ibcon#read 5, iclass 5, count 0 2006.257.11:28:21.88#ibcon#about to read 6, iclass 5, count 0 2006.257.11:28:21.88#ibcon#read 6, iclass 5, count 0 2006.257.11:28:21.88#ibcon#end of sib2, iclass 5, count 0 2006.257.11:28:21.88#ibcon#*after write, iclass 5, count 0 2006.257.11:28:21.88#ibcon#*before return 0, iclass 5, count 0 2006.257.11:28:21.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:21.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:28:21.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:28:21.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:28:21.88$vck44/vb=7,4 2006.257.11:28:21.89#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.11:28:21.89#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.11:28:21.89#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:21.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:21.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:21.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:21.93#ibcon#enter wrdev, iclass 7, count 2 2006.257.11:28:21.93#ibcon#first serial, iclass 7, count 2 2006.257.11:28:21.93#ibcon#enter sib2, iclass 7, count 2 2006.257.11:28:21.93#ibcon#flushed, iclass 7, count 2 2006.257.11:28:21.93#ibcon#about to write, iclass 7, count 2 2006.257.11:28:21.93#ibcon#wrote, iclass 7, count 2 2006.257.11:28:21.93#ibcon#about to read 3, iclass 7, count 2 2006.257.11:28:21.95#ibcon#read 3, iclass 7, count 2 2006.257.11:28:21.95#ibcon#about to read 4, iclass 7, count 2 2006.257.11:28:21.95#ibcon#read 4, iclass 7, count 2 2006.257.11:28:21.95#ibcon#about to read 5, iclass 7, count 2 2006.257.11:28:21.95#ibcon#read 5, iclass 7, count 2 2006.257.11:28:21.95#ibcon#about to read 6, iclass 7, count 2 2006.257.11:28:21.95#ibcon#read 6, iclass 7, count 2 2006.257.11:28:21.95#ibcon#end of sib2, iclass 7, count 2 2006.257.11:28:21.95#ibcon#*mode == 0, iclass 7, count 2 2006.257.11:28:21.95#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.11:28:21.95#ibcon#[27=AT07-04\r\n] 2006.257.11:28:21.95#ibcon#*before write, iclass 7, count 2 2006.257.11:28:21.95#ibcon#enter sib2, iclass 7, count 2 2006.257.11:28:21.95#ibcon#flushed, iclass 7, count 2 2006.257.11:28:21.95#ibcon#about to write, iclass 7, count 2 2006.257.11:28:21.95#ibcon#wrote, iclass 7, count 2 2006.257.11:28:21.95#ibcon#about to read 3, iclass 7, count 2 2006.257.11:28:21.98#ibcon#read 3, iclass 7, count 2 2006.257.11:28:21.98#ibcon#about to read 4, iclass 7, count 2 2006.257.11:28:21.98#ibcon#read 4, iclass 7, count 2 2006.257.11:28:21.98#ibcon#about to read 5, iclass 7, count 2 2006.257.11:28:21.98#ibcon#read 5, iclass 7, count 2 2006.257.11:28:21.98#ibcon#about to read 6, iclass 7, count 2 2006.257.11:28:21.98#ibcon#read 6, iclass 7, count 2 2006.257.11:28:21.98#ibcon#end of sib2, iclass 7, count 2 2006.257.11:28:21.98#ibcon#*after write, iclass 7, count 2 2006.257.11:28:21.98#ibcon#*before return 0, iclass 7, count 2 2006.257.11:28:21.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:21.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:28:21.98#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.11:28:21.98#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:21.98#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:22.10#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:22.10#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:22.10#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:28:22.10#ibcon#first serial, iclass 7, count 0 2006.257.11:28:22.10#ibcon#enter sib2, iclass 7, count 0 2006.257.11:28:22.10#ibcon#flushed, iclass 7, count 0 2006.257.11:28:22.10#ibcon#about to write, iclass 7, count 0 2006.257.11:28:22.10#ibcon#wrote, iclass 7, count 0 2006.257.11:28:22.10#ibcon#about to read 3, iclass 7, count 0 2006.257.11:28:22.12#ibcon#read 3, iclass 7, count 0 2006.257.11:28:22.12#ibcon#about to read 4, iclass 7, count 0 2006.257.11:28:22.12#ibcon#read 4, iclass 7, count 0 2006.257.11:28:22.12#ibcon#about to read 5, iclass 7, count 0 2006.257.11:28:22.12#ibcon#read 5, iclass 7, count 0 2006.257.11:28:22.12#ibcon#about to read 6, iclass 7, count 0 2006.257.11:28:22.12#ibcon#read 6, iclass 7, count 0 2006.257.11:28:22.12#ibcon#end of sib2, iclass 7, count 0 2006.257.11:28:22.12#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:28:22.12#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:28:22.12#ibcon#[27=USB\r\n] 2006.257.11:28:22.12#ibcon#*before write, iclass 7, count 0 2006.257.11:28:22.12#ibcon#enter sib2, iclass 7, count 0 2006.257.11:28:22.12#ibcon#flushed, iclass 7, count 0 2006.257.11:28:22.12#ibcon#about to write, iclass 7, count 0 2006.257.11:28:22.12#ibcon#wrote, iclass 7, count 0 2006.257.11:28:22.12#ibcon#about to read 3, iclass 7, count 0 2006.257.11:28:22.15#ibcon#read 3, iclass 7, count 0 2006.257.11:28:22.15#ibcon#about to read 4, iclass 7, count 0 2006.257.11:28:22.15#ibcon#read 4, iclass 7, count 0 2006.257.11:28:22.15#ibcon#about to read 5, iclass 7, count 0 2006.257.11:28:22.15#ibcon#read 5, iclass 7, count 0 2006.257.11:28:22.15#ibcon#about to read 6, iclass 7, count 0 2006.257.11:28:22.15#ibcon#read 6, iclass 7, count 0 2006.257.11:28:22.15#ibcon#end of sib2, iclass 7, count 0 2006.257.11:28:22.15#ibcon#*after write, iclass 7, count 0 2006.257.11:28:22.15#ibcon#*before return 0, iclass 7, count 0 2006.257.11:28:22.15#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:22.15#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:28:22.15#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:28:22.15#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:28:22.15$vck44/vblo=8,744.99 2006.257.11:28:22.16#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.11:28:22.16#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.11:28:22.16#ibcon#ireg 17 cls_cnt 0 2006.257.11:28:22.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:22.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:22.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:22.16#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:28:22.16#ibcon#first serial, iclass 11, count 0 2006.257.11:28:22.16#ibcon#enter sib2, iclass 11, count 0 2006.257.11:28:22.16#ibcon#flushed, iclass 11, count 0 2006.257.11:28:22.16#ibcon#about to write, iclass 11, count 0 2006.257.11:28:22.16#ibcon#wrote, iclass 11, count 0 2006.257.11:28:22.16#ibcon#about to read 3, iclass 11, count 0 2006.257.11:28:22.17#ibcon#read 3, iclass 11, count 0 2006.257.11:28:22.17#ibcon#about to read 4, iclass 11, count 0 2006.257.11:28:22.17#ibcon#read 4, iclass 11, count 0 2006.257.11:28:22.17#ibcon#about to read 5, iclass 11, count 0 2006.257.11:28:22.17#ibcon#read 5, iclass 11, count 0 2006.257.11:28:22.17#ibcon#about to read 6, iclass 11, count 0 2006.257.11:28:22.17#ibcon#read 6, iclass 11, count 0 2006.257.11:28:22.17#ibcon#end of sib2, iclass 11, count 0 2006.257.11:28:22.17#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:28:22.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:28:22.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:28:22.17#ibcon#*before write, iclass 11, count 0 2006.257.11:28:22.17#ibcon#enter sib2, iclass 11, count 0 2006.257.11:28:22.17#ibcon#flushed, iclass 11, count 0 2006.257.11:28:22.17#ibcon#about to write, iclass 11, count 0 2006.257.11:28:22.17#ibcon#wrote, iclass 11, count 0 2006.257.11:28:22.17#ibcon#about to read 3, iclass 11, count 0 2006.257.11:28:22.21#ibcon#read 3, iclass 11, count 0 2006.257.11:28:22.21#ibcon#about to read 4, iclass 11, count 0 2006.257.11:28:22.21#ibcon#read 4, iclass 11, count 0 2006.257.11:28:22.21#ibcon#about to read 5, iclass 11, count 0 2006.257.11:28:22.21#ibcon#read 5, iclass 11, count 0 2006.257.11:28:22.21#ibcon#about to read 6, iclass 11, count 0 2006.257.11:28:22.21#ibcon#read 6, iclass 11, count 0 2006.257.11:28:22.21#ibcon#end of sib2, iclass 11, count 0 2006.257.11:28:22.21#ibcon#*after write, iclass 11, count 0 2006.257.11:28:22.21#ibcon#*before return 0, iclass 11, count 0 2006.257.11:28:22.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:22.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:28:22.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:28:22.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:28:22.22$vck44/vb=8,4 2006.257.11:28:22.22#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.11:28:22.22#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.11:28:22.22#ibcon#ireg 11 cls_cnt 2 2006.257.11:28:22.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:22.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:22.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:22.26#ibcon#enter wrdev, iclass 13, count 2 2006.257.11:28:22.26#ibcon#first serial, iclass 13, count 2 2006.257.11:28:22.26#ibcon#enter sib2, iclass 13, count 2 2006.257.11:28:22.26#ibcon#flushed, iclass 13, count 2 2006.257.11:28:22.26#ibcon#about to write, iclass 13, count 2 2006.257.11:28:22.26#ibcon#wrote, iclass 13, count 2 2006.257.11:28:22.26#ibcon#about to read 3, iclass 13, count 2 2006.257.11:28:22.28#ibcon#read 3, iclass 13, count 2 2006.257.11:28:22.28#ibcon#about to read 4, iclass 13, count 2 2006.257.11:28:22.28#ibcon#read 4, iclass 13, count 2 2006.257.11:28:22.28#ibcon#about to read 5, iclass 13, count 2 2006.257.11:28:22.28#ibcon#read 5, iclass 13, count 2 2006.257.11:28:22.28#ibcon#about to read 6, iclass 13, count 2 2006.257.11:28:22.28#ibcon#read 6, iclass 13, count 2 2006.257.11:28:22.28#ibcon#end of sib2, iclass 13, count 2 2006.257.11:28:22.28#ibcon#*mode == 0, iclass 13, count 2 2006.257.11:28:22.28#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.11:28:22.28#ibcon#[27=AT08-04\r\n] 2006.257.11:28:22.28#ibcon#*before write, iclass 13, count 2 2006.257.11:28:22.28#ibcon#enter sib2, iclass 13, count 2 2006.257.11:28:22.28#ibcon#flushed, iclass 13, count 2 2006.257.11:28:22.28#ibcon#about to write, iclass 13, count 2 2006.257.11:28:22.28#ibcon#wrote, iclass 13, count 2 2006.257.11:28:22.28#ibcon#about to read 3, iclass 13, count 2 2006.257.11:28:22.31#ibcon#read 3, iclass 13, count 2 2006.257.11:28:22.31#ibcon#about to read 4, iclass 13, count 2 2006.257.11:28:22.31#ibcon#read 4, iclass 13, count 2 2006.257.11:28:22.31#ibcon#about to read 5, iclass 13, count 2 2006.257.11:28:22.31#ibcon#read 5, iclass 13, count 2 2006.257.11:28:22.31#ibcon#about to read 6, iclass 13, count 2 2006.257.11:28:22.31#ibcon#read 6, iclass 13, count 2 2006.257.11:28:22.31#ibcon#end of sib2, iclass 13, count 2 2006.257.11:28:22.31#ibcon#*after write, iclass 13, count 2 2006.257.11:28:22.31#ibcon#*before return 0, iclass 13, count 2 2006.257.11:28:22.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:22.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:28:22.31#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.11:28:22.31#ibcon#ireg 7 cls_cnt 0 2006.257.11:28:22.31#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:22.43#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:22.43#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:22.43#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:28:22.43#ibcon#first serial, iclass 13, count 0 2006.257.11:28:22.43#ibcon#enter sib2, iclass 13, count 0 2006.257.11:28:22.43#ibcon#flushed, iclass 13, count 0 2006.257.11:28:22.43#ibcon#about to write, iclass 13, count 0 2006.257.11:28:22.43#ibcon#wrote, iclass 13, count 0 2006.257.11:28:22.43#ibcon#about to read 3, iclass 13, count 0 2006.257.11:28:22.45#ibcon#read 3, iclass 13, count 0 2006.257.11:28:22.45#ibcon#about to read 4, iclass 13, count 0 2006.257.11:28:22.45#ibcon#read 4, iclass 13, count 0 2006.257.11:28:22.45#ibcon#about to read 5, iclass 13, count 0 2006.257.11:28:22.45#ibcon#read 5, iclass 13, count 0 2006.257.11:28:22.45#ibcon#about to read 6, iclass 13, count 0 2006.257.11:28:22.45#ibcon#read 6, iclass 13, count 0 2006.257.11:28:22.45#ibcon#end of sib2, iclass 13, count 0 2006.257.11:28:22.45#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:28:22.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:28:22.45#ibcon#[27=USB\r\n] 2006.257.11:28:22.45#ibcon#*before write, iclass 13, count 0 2006.257.11:28:22.45#ibcon#enter sib2, iclass 13, count 0 2006.257.11:28:22.45#ibcon#flushed, iclass 13, count 0 2006.257.11:28:22.45#ibcon#about to write, iclass 13, count 0 2006.257.11:28:22.45#ibcon#wrote, iclass 13, count 0 2006.257.11:28:22.45#ibcon#about to read 3, iclass 13, count 0 2006.257.11:28:22.48#ibcon#read 3, iclass 13, count 0 2006.257.11:28:22.48#ibcon#about to read 4, iclass 13, count 0 2006.257.11:28:22.48#ibcon#read 4, iclass 13, count 0 2006.257.11:28:22.48#ibcon#about to read 5, iclass 13, count 0 2006.257.11:28:22.48#ibcon#read 5, iclass 13, count 0 2006.257.11:28:22.48#ibcon#about to read 6, iclass 13, count 0 2006.257.11:28:22.48#ibcon#read 6, iclass 13, count 0 2006.257.11:28:22.48#ibcon#end of sib2, iclass 13, count 0 2006.257.11:28:22.48#ibcon#*after write, iclass 13, count 0 2006.257.11:28:22.48#ibcon#*before return 0, iclass 13, count 0 2006.257.11:28:22.48#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:22.48#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:28:22.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:28:22.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:28:22.49$vck44/vabw=wide 2006.257.11:28:22.49#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.11:28:22.49#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.11:28:22.49#ibcon#ireg 8 cls_cnt 0 2006.257.11:28:22.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:22.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:22.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:22.49#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:28:22.49#ibcon#first serial, iclass 15, count 0 2006.257.11:28:22.49#ibcon#enter sib2, iclass 15, count 0 2006.257.11:28:22.49#ibcon#flushed, iclass 15, count 0 2006.257.11:28:22.49#ibcon#about to write, iclass 15, count 0 2006.257.11:28:22.49#ibcon#wrote, iclass 15, count 0 2006.257.11:28:22.49#ibcon#about to read 3, iclass 15, count 0 2006.257.11:28:22.50#ibcon#read 3, iclass 15, count 0 2006.257.11:28:22.50#ibcon#about to read 4, iclass 15, count 0 2006.257.11:28:22.50#ibcon#read 4, iclass 15, count 0 2006.257.11:28:22.50#ibcon#about to read 5, iclass 15, count 0 2006.257.11:28:22.50#ibcon#read 5, iclass 15, count 0 2006.257.11:28:22.50#ibcon#about to read 6, iclass 15, count 0 2006.257.11:28:22.50#ibcon#read 6, iclass 15, count 0 2006.257.11:28:22.50#ibcon#end of sib2, iclass 15, count 0 2006.257.11:28:22.50#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:28:22.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:28:22.50#ibcon#[25=BW32\r\n] 2006.257.11:28:22.50#ibcon#*before write, iclass 15, count 0 2006.257.11:28:22.50#ibcon#enter sib2, iclass 15, count 0 2006.257.11:28:22.50#ibcon#flushed, iclass 15, count 0 2006.257.11:28:22.50#ibcon#about to write, iclass 15, count 0 2006.257.11:28:22.50#ibcon#wrote, iclass 15, count 0 2006.257.11:28:22.50#ibcon#about to read 3, iclass 15, count 0 2006.257.11:28:22.53#ibcon#read 3, iclass 15, count 0 2006.257.11:28:22.53#ibcon#about to read 4, iclass 15, count 0 2006.257.11:28:22.53#ibcon#read 4, iclass 15, count 0 2006.257.11:28:22.53#ibcon#about to read 5, iclass 15, count 0 2006.257.11:28:22.53#ibcon#read 5, iclass 15, count 0 2006.257.11:28:22.53#ibcon#about to read 6, iclass 15, count 0 2006.257.11:28:22.53#ibcon#read 6, iclass 15, count 0 2006.257.11:28:22.53#ibcon#end of sib2, iclass 15, count 0 2006.257.11:28:22.53#ibcon#*after write, iclass 15, count 0 2006.257.11:28:22.53#ibcon#*before return 0, iclass 15, count 0 2006.257.11:28:22.53#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:22.53#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:28:22.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:28:22.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:28:22.54$vck44/vbbw=wide 2006.257.11:28:22.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.11:28:22.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.11:28:22.54#ibcon#ireg 8 cls_cnt 0 2006.257.11:28:22.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:28:22.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:28:22.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:28:22.59#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:28:22.59#ibcon#first serial, iclass 17, count 0 2006.257.11:28:22.59#ibcon#enter sib2, iclass 17, count 0 2006.257.11:28:22.59#ibcon#flushed, iclass 17, count 0 2006.257.11:28:22.59#ibcon#about to write, iclass 17, count 0 2006.257.11:28:22.59#ibcon#wrote, iclass 17, count 0 2006.257.11:28:22.59#ibcon#about to read 3, iclass 17, count 0 2006.257.11:28:22.61#ibcon#read 3, iclass 17, count 0 2006.257.11:28:22.61#ibcon#about to read 4, iclass 17, count 0 2006.257.11:28:22.61#ibcon#read 4, iclass 17, count 0 2006.257.11:28:22.61#ibcon#about to read 5, iclass 17, count 0 2006.257.11:28:22.61#ibcon#read 5, iclass 17, count 0 2006.257.11:28:22.61#ibcon#about to read 6, iclass 17, count 0 2006.257.11:28:22.61#ibcon#read 6, iclass 17, count 0 2006.257.11:28:22.61#ibcon#end of sib2, iclass 17, count 0 2006.257.11:28:22.61#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:28:22.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:28:22.61#ibcon#[27=BW32\r\n] 2006.257.11:28:22.61#ibcon#*before write, iclass 17, count 0 2006.257.11:28:22.61#ibcon#enter sib2, iclass 17, count 0 2006.257.11:28:22.61#ibcon#flushed, iclass 17, count 0 2006.257.11:28:22.61#ibcon#about to write, iclass 17, count 0 2006.257.11:28:22.61#ibcon#wrote, iclass 17, count 0 2006.257.11:28:22.61#ibcon#about to read 3, iclass 17, count 0 2006.257.11:28:22.64#ibcon#read 3, iclass 17, count 0 2006.257.11:28:22.64#ibcon#about to read 4, iclass 17, count 0 2006.257.11:28:22.64#ibcon#read 4, iclass 17, count 0 2006.257.11:28:22.64#ibcon#about to read 5, iclass 17, count 0 2006.257.11:28:22.64#ibcon#read 5, iclass 17, count 0 2006.257.11:28:22.64#ibcon#about to read 6, iclass 17, count 0 2006.257.11:28:22.64#ibcon#read 6, iclass 17, count 0 2006.257.11:28:22.64#ibcon#end of sib2, iclass 17, count 0 2006.257.11:28:22.64#ibcon#*after write, iclass 17, count 0 2006.257.11:28:22.64#ibcon#*before return 0, iclass 17, count 0 2006.257.11:28:22.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:28:22.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:28:22.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:28:22.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:28:22.70$setupk4/ifdk4 2006.257.11:28:22.70$ifdk4/lo= 2006.257.11:28:22.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:28:22.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:28:22.70$ifdk4/patch= 2006.257.11:28:22.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:28:22.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:28:22.70$setupk4/!*+20s 2006.257.11:28:23.98#abcon#<5=/14 1.2 2.5 18.21 971014.0\r\n> 2006.257.11:28:24.00#abcon#{5=INTERFACE CLEAR} 2006.257.11:28:24.06#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:28:34.15#abcon#<5=/14 1.2 2.5 18.20 971014.0\r\n> 2006.257.11:28:34.17#abcon#{5=INTERFACE CLEAR} 2006.257.11:28:34.23#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:28:37.14#trakl#Source acquired 2006.257.11:28:37.15#flagr#flagr/antenna,acquired 2006.257.11:28:37.29$setupk4/"tpicd 2006.257.11:28:37.29$setupk4/echo=off 2006.257.11:28:37.29$setupk4/xlog=off 2006.257.11:28:37.29:!2006.257.11:32:44 2006.257.11:32:44.00:preob 2006.257.11:32:44.14/onsource/TRACKING 2006.257.11:32:44.14:!2006.257.11:32:54 2006.257.11:32:54.00:"tape 2006.257.11:32:54.00:"st=record 2006.257.11:32:54.00:data_valid=on 2006.257.11:32:54.00:midob 2006.257.11:32:55.14/onsource/TRACKING 2006.257.11:32:55.14/wx/18.17,1014.0,97 2006.257.11:32:55.20/cable/+6.4779E-03 2006.257.11:32:56.29/va/01,08,usb,yes,30,32 2006.257.11:32:56.29/va/02,07,usb,yes,32,33 2006.257.11:32:56.29/va/03,08,usb,yes,29,31 2006.257.11:32:56.29/va/04,07,usb,yes,33,35 2006.257.11:32:56.29/va/05,04,usb,yes,30,30 2006.257.11:32:56.29/va/06,04,usb,yes,33,33 2006.257.11:32:56.29/va/07,04,usb,yes,34,35 2006.257.11:32:56.29/va/08,04,usb,yes,28,35 2006.257.11:32:56.52/valo/01,524.99,yes,locked 2006.257.11:32:56.52/valo/02,534.99,yes,locked 2006.257.11:32:56.52/valo/03,564.99,yes,locked 2006.257.11:32:56.52/valo/04,624.99,yes,locked 2006.257.11:32:56.52/valo/05,734.99,yes,locked 2006.257.11:32:56.52/valo/06,814.99,yes,locked 2006.257.11:32:56.52/valo/07,864.99,yes,locked 2006.257.11:32:56.52/valo/08,884.99,yes,locked 2006.257.11:32:57.61/vb/01,04,usb,yes,30,28 2006.257.11:32:57.61/vb/02,05,usb,yes,28,28 2006.257.11:32:57.61/vb/03,04,usb,yes,29,32 2006.257.11:32:57.61/vb/04,05,usb,yes,30,29 2006.257.11:32:57.61/vb/05,04,usb,yes,26,28 2006.257.11:32:57.61/vb/06,04,usb,yes,31,27 2006.257.11:32:57.61/vb/07,04,usb,yes,30,30 2006.257.11:32:57.61/vb/08,04,usb,yes,28,31 2006.257.11:32:57.85/vblo/01,629.99,yes,locked 2006.257.11:32:57.85/vblo/02,634.99,yes,locked 2006.257.11:32:57.85/vblo/03,649.99,yes,locked 2006.257.11:32:57.85/vblo/04,679.99,yes,locked 2006.257.11:32:57.85/vblo/05,709.99,yes,locked 2006.257.11:32:57.85/vblo/06,719.99,yes,locked 2006.257.11:32:57.85/vblo/07,734.99,yes,locked 2006.257.11:32:57.85/vblo/08,744.99,yes,locked 2006.257.11:32:58.00/vabw/8 2006.257.11:32:58.15/vbbw/8 2006.257.11:32:58.24/xfe/off,on,15.2 2006.257.11:32:58.61/ifatt/23,28,28,28 2006.257.11:32:59.07/fmout-gps/S +4.64E-07 2006.257.11:32:59.11:!2006.257.11:34:04 2006.257.11:34:04.01:data_valid=off 2006.257.11:34:04.02:"et 2006.257.11:34:04.02:!+3s 2006.257.11:34:07.03:"tape 2006.257.11:34:07.04:postob 2006.257.11:34:07.15/cable/+6.4772E-03 2006.257.11:34:07.16/wx/18.16,1014.0,97 2006.257.11:34:07.21/fmout-gps/S +4.62E-07 2006.257.11:34:07.22:scan_name=257-1138,jd0609,160 2006.257.11:34:07.22:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.257.11:34:09.14#flagr#flagr/antenna,new-source 2006.257.11:34:09.15:checkk5 2006.257.11:34:09.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:34:09.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:34:10.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:34:10.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:34:11.18/chk_obsdata//k5ts1/T2571132??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.11:34:11.58/chk_obsdata//k5ts2/T2571132??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.11:34:11.98/chk_obsdata//k5ts3/T2571132??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.11:34:12.37/chk_obsdata//k5ts4/T2571132??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.11:34:13.08/k5log//k5ts1_log_newline 2006.257.11:34:13.80/k5log//k5ts2_log_newline 2006.257.11:34:14.50/k5log//k5ts3_log_newline 2006.257.11:34:15.21/k5log//k5ts4_log_newline 2006.257.11:34:15.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:34:15.24:setupk4=1 2006.257.11:34:15.24$setupk4/echo=on 2006.257.11:34:15.24$setupk4/pcalon 2006.257.11:34:15.24$pcalon/"no phase cal control is implemented here 2006.257.11:34:15.24$setupk4/"tpicd=stop 2006.257.11:34:15.24$setupk4/"rec=synch_on 2006.257.11:34:15.24$setupk4/"rec_mode=128 2006.257.11:34:15.24$setupk4/!* 2006.257.11:34:15.24$setupk4/recpk4 2006.257.11:34:15.24$recpk4/recpatch= 2006.257.11:34:15.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:34:15.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:34:15.25$setupk4/vck44 2006.257.11:34:15.25$vck44/valo=1,524.99 2006.257.11:34:15.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.11:34:15.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.11:34:15.25#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:15.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:15.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:15.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:15.25#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:34:15.25#ibcon#first serial, iclass 13, count 0 2006.257.11:34:15.25#ibcon#enter sib2, iclass 13, count 0 2006.257.11:34:15.25#ibcon#flushed, iclass 13, count 0 2006.257.11:34:15.25#ibcon#about to write, iclass 13, count 0 2006.257.11:34:15.25#ibcon#wrote, iclass 13, count 0 2006.257.11:34:15.25#ibcon#about to read 3, iclass 13, count 0 2006.257.11:34:15.26#ibcon#read 3, iclass 13, count 0 2006.257.11:34:15.26#ibcon#about to read 4, iclass 13, count 0 2006.257.11:34:15.26#ibcon#read 4, iclass 13, count 0 2006.257.11:34:15.26#ibcon#about to read 5, iclass 13, count 0 2006.257.11:34:15.26#ibcon#read 5, iclass 13, count 0 2006.257.11:34:15.26#ibcon#about to read 6, iclass 13, count 0 2006.257.11:34:15.26#ibcon#read 6, iclass 13, count 0 2006.257.11:34:15.26#ibcon#end of sib2, iclass 13, count 0 2006.257.11:34:15.26#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:34:15.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:34:15.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:34:15.26#ibcon#*before write, iclass 13, count 0 2006.257.11:34:15.26#ibcon#enter sib2, iclass 13, count 0 2006.257.11:34:15.26#ibcon#flushed, iclass 13, count 0 2006.257.11:34:15.26#ibcon#about to write, iclass 13, count 0 2006.257.11:34:15.26#ibcon#wrote, iclass 13, count 0 2006.257.11:34:15.26#ibcon#about to read 3, iclass 13, count 0 2006.257.11:34:15.31#ibcon#read 3, iclass 13, count 0 2006.257.11:34:15.31#ibcon#about to read 4, iclass 13, count 0 2006.257.11:34:15.31#ibcon#read 4, iclass 13, count 0 2006.257.11:34:15.31#ibcon#about to read 5, iclass 13, count 0 2006.257.11:34:15.31#ibcon#read 5, iclass 13, count 0 2006.257.11:34:15.31#ibcon#about to read 6, iclass 13, count 0 2006.257.11:34:15.31#ibcon#read 6, iclass 13, count 0 2006.257.11:34:15.31#ibcon#end of sib2, iclass 13, count 0 2006.257.11:34:15.31#ibcon#*after write, iclass 13, count 0 2006.257.11:34:15.31#ibcon#*before return 0, iclass 13, count 0 2006.257.11:34:15.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:15.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:15.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:34:15.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:34:15.31$vck44/va=1,8 2006.257.11:34:15.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.11:34:15.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.11:34:15.31#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:15.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:15.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:15.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:15.31#ibcon#enter wrdev, iclass 15, count 2 2006.257.11:34:15.31#ibcon#first serial, iclass 15, count 2 2006.257.11:34:15.31#ibcon#enter sib2, iclass 15, count 2 2006.257.11:34:15.31#ibcon#flushed, iclass 15, count 2 2006.257.11:34:15.31#ibcon#about to write, iclass 15, count 2 2006.257.11:34:15.31#ibcon#wrote, iclass 15, count 2 2006.257.11:34:15.31#ibcon#about to read 3, iclass 15, count 2 2006.257.11:34:15.33#ibcon#read 3, iclass 15, count 2 2006.257.11:34:15.33#ibcon#about to read 4, iclass 15, count 2 2006.257.11:34:15.33#ibcon#read 4, iclass 15, count 2 2006.257.11:34:15.33#ibcon#about to read 5, iclass 15, count 2 2006.257.11:34:15.33#ibcon#read 5, iclass 15, count 2 2006.257.11:34:15.33#ibcon#about to read 6, iclass 15, count 2 2006.257.11:34:15.33#ibcon#read 6, iclass 15, count 2 2006.257.11:34:15.33#ibcon#end of sib2, iclass 15, count 2 2006.257.11:34:15.33#ibcon#*mode == 0, iclass 15, count 2 2006.257.11:34:15.33#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.11:34:15.33#ibcon#[25=AT01-08\r\n] 2006.257.11:34:15.33#ibcon#*before write, iclass 15, count 2 2006.257.11:34:15.33#ibcon#enter sib2, iclass 15, count 2 2006.257.11:34:15.33#ibcon#flushed, iclass 15, count 2 2006.257.11:34:15.33#ibcon#about to write, iclass 15, count 2 2006.257.11:34:15.33#ibcon#wrote, iclass 15, count 2 2006.257.11:34:15.33#ibcon#about to read 3, iclass 15, count 2 2006.257.11:34:15.36#ibcon#read 3, iclass 15, count 2 2006.257.11:34:15.36#ibcon#about to read 4, iclass 15, count 2 2006.257.11:34:15.36#ibcon#read 4, iclass 15, count 2 2006.257.11:34:15.36#ibcon#about to read 5, iclass 15, count 2 2006.257.11:34:15.36#ibcon#read 5, iclass 15, count 2 2006.257.11:34:15.36#ibcon#about to read 6, iclass 15, count 2 2006.257.11:34:15.36#ibcon#read 6, iclass 15, count 2 2006.257.11:34:15.36#ibcon#end of sib2, iclass 15, count 2 2006.257.11:34:15.36#ibcon#*after write, iclass 15, count 2 2006.257.11:34:15.36#ibcon#*before return 0, iclass 15, count 2 2006.257.11:34:15.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:15.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:15.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.11:34:15.36#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:15.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:15.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:15.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:15.48#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:34:15.48#ibcon#first serial, iclass 15, count 0 2006.257.11:34:15.48#ibcon#enter sib2, iclass 15, count 0 2006.257.11:34:15.48#ibcon#flushed, iclass 15, count 0 2006.257.11:34:15.48#ibcon#about to write, iclass 15, count 0 2006.257.11:34:15.48#ibcon#wrote, iclass 15, count 0 2006.257.11:34:15.48#ibcon#about to read 3, iclass 15, count 0 2006.257.11:34:15.50#ibcon#read 3, iclass 15, count 0 2006.257.11:34:15.50#ibcon#about to read 4, iclass 15, count 0 2006.257.11:34:15.50#ibcon#read 4, iclass 15, count 0 2006.257.11:34:15.50#ibcon#about to read 5, iclass 15, count 0 2006.257.11:34:15.50#ibcon#read 5, iclass 15, count 0 2006.257.11:34:15.50#ibcon#about to read 6, iclass 15, count 0 2006.257.11:34:15.50#ibcon#read 6, iclass 15, count 0 2006.257.11:34:15.50#ibcon#end of sib2, iclass 15, count 0 2006.257.11:34:15.50#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:34:15.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:34:15.50#ibcon#[25=USB\r\n] 2006.257.11:34:15.50#ibcon#*before write, iclass 15, count 0 2006.257.11:34:15.50#ibcon#enter sib2, iclass 15, count 0 2006.257.11:34:15.50#ibcon#flushed, iclass 15, count 0 2006.257.11:34:15.50#ibcon#about to write, iclass 15, count 0 2006.257.11:34:15.50#ibcon#wrote, iclass 15, count 0 2006.257.11:34:15.50#ibcon#about to read 3, iclass 15, count 0 2006.257.11:34:15.53#ibcon#read 3, iclass 15, count 0 2006.257.11:34:15.53#ibcon#about to read 4, iclass 15, count 0 2006.257.11:34:15.53#ibcon#read 4, iclass 15, count 0 2006.257.11:34:15.53#ibcon#about to read 5, iclass 15, count 0 2006.257.11:34:15.53#ibcon#read 5, iclass 15, count 0 2006.257.11:34:15.53#ibcon#about to read 6, iclass 15, count 0 2006.257.11:34:15.53#ibcon#read 6, iclass 15, count 0 2006.257.11:34:15.53#ibcon#end of sib2, iclass 15, count 0 2006.257.11:34:15.53#ibcon#*after write, iclass 15, count 0 2006.257.11:34:15.53#ibcon#*before return 0, iclass 15, count 0 2006.257.11:34:15.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:15.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:15.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:34:15.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:34:15.53$vck44/valo=2,534.99 2006.257.11:34:15.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.11:34:15.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.11:34:15.53#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:15.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:15.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:15.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:15.53#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:34:15.53#ibcon#first serial, iclass 17, count 0 2006.257.11:34:15.53#ibcon#enter sib2, iclass 17, count 0 2006.257.11:34:15.53#ibcon#flushed, iclass 17, count 0 2006.257.11:34:15.53#ibcon#about to write, iclass 17, count 0 2006.257.11:34:15.53#ibcon#wrote, iclass 17, count 0 2006.257.11:34:15.53#ibcon#about to read 3, iclass 17, count 0 2006.257.11:34:15.55#ibcon#read 3, iclass 17, count 0 2006.257.11:34:15.55#ibcon#about to read 4, iclass 17, count 0 2006.257.11:34:15.55#ibcon#read 4, iclass 17, count 0 2006.257.11:34:15.55#ibcon#about to read 5, iclass 17, count 0 2006.257.11:34:15.55#ibcon#read 5, iclass 17, count 0 2006.257.11:34:15.55#ibcon#about to read 6, iclass 17, count 0 2006.257.11:34:15.55#ibcon#read 6, iclass 17, count 0 2006.257.11:34:15.55#ibcon#end of sib2, iclass 17, count 0 2006.257.11:34:15.55#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:34:15.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:34:15.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:34:15.55#ibcon#*before write, iclass 17, count 0 2006.257.11:34:15.55#ibcon#enter sib2, iclass 17, count 0 2006.257.11:34:15.55#ibcon#flushed, iclass 17, count 0 2006.257.11:34:15.55#ibcon#about to write, iclass 17, count 0 2006.257.11:34:15.55#ibcon#wrote, iclass 17, count 0 2006.257.11:34:15.55#ibcon#about to read 3, iclass 17, count 0 2006.257.11:34:15.59#ibcon#read 3, iclass 17, count 0 2006.257.11:34:15.59#ibcon#about to read 4, iclass 17, count 0 2006.257.11:34:15.59#ibcon#read 4, iclass 17, count 0 2006.257.11:34:15.59#ibcon#about to read 5, iclass 17, count 0 2006.257.11:34:15.59#ibcon#read 5, iclass 17, count 0 2006.257.11:34:15.59#ibcon#about to read 6, iclass 17, count 0 2006.257.11:34:15.59#ibcon#read 6, iclass 17, count 0 2006.257.11:34:15.59#ibcon#end of sib2, iclass 17, count 0 2006.257.11:34:15.59#ibcon#*after write, iclass 17, count 0 2006.257.11:34:15.59#ibcon#*before return 0, iclass 17, count 0 2006.257.11:34:15.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:15.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:15.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:34:15.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:34:15.59$vck44/va=2,7 2006.257.11:34:15.59#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.11:34:15.59#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.11:34:15.59#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:15.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:15.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:15.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:15.65#ibcon#enter wrdev, iclass 19, count 2 2006.257.11:34:15.65#ibcon#first serial, iclass 19, count 2 2006.257.11:34:15.65#ibcon#enter sib2, iclass 19, count 2 2006.257.11:34:15.65#ibcon#flushed, iclass 19, count 2 2006.257.11:34:15.65#ibcon#about to write, iclass 19, count 2 2006.257.11:34:15.65#ibcon#wrote, iclass 19, count 2 2006.257.11:34:15.65#ibcon#about to read 3, iclass 19, count 2 2006.257.11:34:15.67#ibcon#read 3, iclass 19, count 2 2006.257.11:34:15.67#ibcon#about to read 4, iclass 19, count 2 2006.257.11:34:15.67#ibcon#read 4, iclass 19, count 2 2006.257.11:34:15.67#ibcon#about to read 5, iclass 19, count 2 2006.257.11:34:15.67#ibcon#read 5, iclass 19, count 2 2006.257.11:34:15.67#ibcon#about to read 6, iclass 19, count 2 2006.257.11:34:15.67#ibcon#read 6, iclass 19, count 2 2006.257.11:34:15.67#ibcon#end of sib2, iclass 19, count 2 2006.257.11:34:15.67#ibcon#*mode == 0, iclass 19, count 2 2006.257.11:34:15.67#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.11:34:15.67#ibcon#[25=AT02-07\r\n] 2006.257.11:34:15.67#ibcon#*before write, iclass 19, count 2 2006.257.11:34:15.67#ibcon#enter sib2, iclass 19, count 2 2006.257.11:34:15.67#ibcon#flushed, iclass 19, count 2 2006.257.11:34:15.67#ibcon#about to write, iclass 19, count 2 2006.257.11:34:15.67#ibcon#wrote, iclass 19, count 2 2006.257.11:34:15.67#ibcon#about to read 3, iclass 19, count 2 2006.257.11:34:15.70#ibcon#read 3, iclass 19, count 2 2006.257.11:34:15.70#ibcon#about to read 4, iclass 19, count 2 2006.257.11:34:15.70#ibcon#read 4, iclass 19, count 2 2006.257.11:34:15.70#ibcon#about to read 5, iclass 19, count 2 2006.257.11:34:15.70#ibcon#read 5, iclass 19, count 2 2006.257.11:34:15.70#ibcon#about to read 6, iclass 19, count 2 2006.257.11:34:15.70#ibcon#read 6, iclass 19, count 2 2006.257.11:34:15.70#ibcon#end of sib2, iclass 19, count 2 2006.257.11:34:15.70#ibcon#*after write, iclass 19, count 2 2006.257.11:34:15.70#ibcon#*before return 0, iclass 19, count 2 2006.257.11:34:15.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:15.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:15.70#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.11:34:15.70#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:15.70#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:15.82#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:15.82#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:15.82#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:34:15.82#ibcon#first serial, iclass 19, count 0 2006.257.11:34:15.82#ibcon#enter sib2, iclass 19, count 0 2006.257.11:34:15.82#ibcon#flushed, iclass 19, count 0 2006.257.11:34:15.82#ibcon#about to write, iclass 19, count 0 2006.257.11:34:15.82#ibcon#wrote, iclass 19, count 0 2006.257.11:34:15.82#ibcon#about to read 3, iclass 19, count 0 2006.257.11:34:15.84#ibcon#read 3, iclass 19, count 0 2006.257.11:34:15.84#ibcon#about to read 4, iclass 19, count 0 2006.257.11:34:15.84#ibcon#read 4, iclass 19, count 0 2006.257.11:34:15.84#ibcon#about to read 5, iclass 19, count 0 2006.257.11:34:15.84#ibcon#read 5, iclass 19, count 0 2006.257.11:34:15.84#ibcon#about to read 6, iclass 19, count 0 2006.257.11:34:15.84#ibcon#read 6, iclass 19, count 0 2006.257.11:34:15.84#ibcon#end of sib2, iclass 19, count 0 2006.257.11:34:15.84#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:34:15.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:34:15.84#ibcon#[25=USB\r\n] 2006.257.11:34:15.84#ibcon#*before write, iclass 19, count 0 2006.257.11:34:15.84#ibcon#enter sib2, iclass 19, count 0 2006.257.11:34:15.84#ibcon#flushed, iclass 19, count 0 2006.257.11:34:15.84#ibcon#about to write, iclass 19, count 0 2006.257.11:34:15.84#ibcon#wrote, iclass 19, count 0 2006.257.11:34:15.84#ibcon#about to read 3, iclass 19, count 0 2006.257.11:34:15.87#ibcon#read 3, iclass 19, count 0 2006.257.11:34:15.87#ibcon#about to read 4, iclass 19, count 0 2006.257.11:34:15.87#ibcon#read 4, iclass 19, count 0 2006.257.11:34:15.87#ibcon#about to read 5, iclass 19, count 0 2006.257.11:34:15.87#ibcon#read 5, iclass 19, count 0 2006.257.11:34:15.87#ibcon#about to read 6, iclass 19, count 0 2006.257.11:34:15.87#ibcon#read 6, iclass 19, count 0 2006.257.11:34:15.87#ibcon#end of sib2, iclass 19, count 0 2006.257.11:34:15.87#ibcon#*after write, iclass 19, count 0 2006.257.11:34:15.87#ibcon#*before return 0, iclass 19, count 0 2006.257.11:34:15.87#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:15.87#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:15.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:34:15.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:34:15.87$vck44/valo=3,564.99 2006.257.11:34:15.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.11:34:15.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.11:34:15.87#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:15.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:15.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:15.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:15.87#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:34:15.87#ibcon#first serial, iclass 21, count 0 2006.257.11:34:15.87#ibcon#enter sib2, iclass 21, count 0 2006.257.11:34:15.87#ibcon#flushed, iclass 21, count 0 2006.257.11:34:15.87#ibcon#about to write, iclass 21, count 0 2006.257.11:34:15.87#ibcon#wrote, iclass 21, count 0 2006.257.11:34:15.87#ibcon#about to read 3, iclass 21, count 0 2006.257.11:34:15.89#ibcon#read 3, iclass 21, count 0 2006.257.11:34:15.89#ibcon#about to read 4, iclass 21, count 0 2006.257.11:34:15.89#ibcon#read 4, iclass 21, count 0 2006.257.11:34:15.89#ibcon#about to read 5, iclass 21, count 0 2006.257.11:34:15.89#ibcon#read 5, iclass 21, count 0 2006.257.11:34:15.89#ibcon#about to read 6, iclass 21, count 0 2006.257.11:34:15.89#ibcon#read 6, iclass 21, count 0 2006.257.11:34:15.89#ibcon#end of sib2, iclass 21, count 0 2006.257.11:34:15.89#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:34:15.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:34:15.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:34:15.89#ibcon#*before write, iclass 21, count 0 2006.257.11:34:15.89#ibcon#enter sib2, iclass 21, count 0 2006.257.11:34:15.89#ibcon#flushed, iclass 21, count 0 2006.257.11:34:15.89#ibcon#about to write, iclass 21, count 0 2006.257.11:34:15.89#ibcon#wrote, iclass 21, count 0 2006.257.11:34:15.89#ibcon#about to read 3, iclass 21, count 0 2006.257.11:34:15.93#ibcon#read 3, iclass 21, count 0 2006.257.11:34:15.93#ibcon#about to read 4, iclass 21, count 0 2006.257.11:34:15.93#ibcon#read 4, iclass 21, count 0 2006.257.11:34:15.93#ibcon#about to read 5, iclass 21, count 0 2006.257.11:34:15.93#ibcon#read 5, iclass 21, count 0 2006.257.11:34:15.93#ibcon#about to read 6, iclass 21, count 0 2006.257.11:34:15.93#ibcon#read 6, iclass 21, count 0 2006.257.11:34:15.93#ibcon#end of sib2, iclass 21, count 0 2006.257.11:34:15.93#ibcon#*after write, iclass 21, count 0 2006.257.11:34:15.93#ibcon#*before return 0, iclass 21, count 0 2006.257.11:34:15.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:15.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:15.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:34:15.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:34:15.93$vck44/va=3,8 2006.257.11:34:15.93#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.11:34:15.93#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.11:34:15.93#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:15.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:15.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:15.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:15.99#ibcon#enter wrdev, iclass 23, count 2 2006.257.11:34:15.99#ibcon#first serial, iclass 23, count 2 2006.257.11:34:15.99#ibcon#enter sib2, iclass 23, count 2 2006.257.11:34:15.99#ibcon#flushed, iclass 23, count 2 2006.257.11:34:15.99#ibcon#about to write, iclass 23, count 2 2006.257.11:34:15.99#ibcon#wrote, iclass 23, count 2 2006.257.11:34:15.99#ibcon#about to read 3, iclass 23, count 2 2006.257.11:34:16.01#ibcon#read 3, iclass 23, count 2 2006.257.11:34:16.01#ibcon#about to read 4, iclass 23, count 2 2006.257.11:34:16.01#ibcon#read 4, iclass 23, count 2 2006.257.11:34:16.01#ibcon#about to read 5, iclass 23, count 2 2006.257.11:34:16.01#ibcon#read 5, iclass 23, count 2 2006.257.11:34:16.01#ibcon#about to read 6, iclass 23, count 2 2006.257.11:34:16.01#ibcon#read 6, iclass 23, count 2 2006.257.11:34:16.01#ibcon#end of sib2, iclass 23, count 2 2006.257.11:34:16.01#ibcon#*mode == 0, iclass 23, count 2 2006.257.11:34:16.01#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.11:34:16.01#ibcon#[25=AT03-08\r\n] 2006.257.11:34:16.01#ibcon#*before write, iclass 23, count 2 2006.257.11:34:16.01#ibcon#enter sib2, iclass 23, count 2 2006.257.11:34:16.01#ibcon#flushed, iclass 23, count 2 2006.257.11:34:16.01#ibcon#about to write, iclass 23, count 2 2006.257.11:34:16.01#ibcon#wrote, iclass 23, count 2 2006.257.11:34:16.01#ibcon#about to read 3, iclass 23, count 2 2006.257.11:34:16.04#ibcon#read 3, iclass 23, count 2 2006.257.11:34:16.04#ibcon#about to read 4, iclass 23, count 2 2006.257.11:34:16.04#ibcon#read 4, iclass 23, count 2 2006.257.11:34:16.04#ibcon#about to read 5, iclass 23, count 2 2006.257.11:34:16.04#ibcon#read 5, iclass 23, count 2 2006.257.11:34:16.04#ibcon#about to read 6, iclass 23, count 2 2006.257.11:34:16.04#ibcon#read 6, iclass 23, count 2 2006.257.11:34:16.04#ibcon#end of sib2, iclass 23, count 2 2006.257.11:34:16.04#ibcon#*after write, iclass 23, count 2 2006.257.11:34:16.04#ibcon#*before return 0, iclass 23, count 2 2006.257.11:34:16.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:16.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:16.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.11:34:16.04#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:16.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:16.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:16.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:16.16#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:34:16.16#ibcon#first serial, iclass 23, count 0 2006.257.11:34:16.16#ibcon#enter sib2, iclass 23, count 0 2006.257.11:34:16.16#ibcon#flushed, iclass 23, count 0 2006.257.11:34:16.16#ibcon#about to write, iclass 23, count 0 2006.257.11:34:16.16#ibcon#wrote, iclass 23, count 0 2006.257.11:34:16.16#ibcon#about to read 3, iclass 23, count 0 2006.257.11:34:16.18#ibcon#read 3, iclass 23, count 0 2006.257.11:34:16.18#ibcon#about to read 4, iclass 23, count 0 2006.257.11:34:16.18#ibcon#read 4, iclass 23, count 0 2006.257.11:34:16.18#ibcon#about to read 5, iclass 23, count 0 2006.257.11:34:16.18#ibcon#read 5, iclass 23, count 0 2006.257.11:34:16.18#ibcon#about to read 6, iclass 23, count 0 2006.257.11:34:16.18#ibcon#read 6, iclass 23, count 0 2006.257.11:34:16.18#ibcon#end of sib2, iclass 23, count 0 2006.257.11:34:16.18#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:34:16.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:34:16.18#ibcon#[25=USB\r\n] 2006.257.11:34:16.18#ibcon#*before write, iclass 23, count 0 2006.257.11:34:16.18#ibcon#enter sib2, iclass 23, count 0 2006.257.11:34:16.18#ibcon#flushed, iclass 23, count 0 2006.257.11:34:16.18#ibcon#about to write, iclass 23, count 0 2006.257.11:34:16.18#ibcon#wrote, iclass 23, count 0 2006.257.11:34:16.18#ibcon#about to read 3, iclass 23, count 0 2006.257.11:34:16.21#ibcon#read 3, iclass 23, count 0 2006.257.11:34:16.21#ibcon#about to read 4, iclass 23, count 0 2006.257.11:34:16.21#ibcon#read 4, iclass 23, count 0 2006.257.11:34:16.21#ibcon#about to read 5, iclass 23, count 0 2006.257.11:34:16.21#ibcon#read 5, iclass 23, count 0 2006.257.11:34:16.21#ibcon#about to read 6, iclass 23, count 0 2006.257.11:34:16.21#ibcon#read 6, iclass 23, count 0 2006.257.11:34:16.21#ibcon#end of sib2, iclass 23, count 0 2006.257.11:34:16.21#ibcon#*after write, iclass 23, count 0 2006.257.11:34:16.21#ibcon#*before return 0, iclass 23, count 0 2006.257.11:34:16.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:16.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:16.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:34:16.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:34:16.21$vck44/valo=4,624.99 2006.257.11:34:16.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.11:34:16.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.11:34:16.21#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:16.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:16.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:16.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:16.21#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:34:16.21#ibcon#first serial, iclass 25, count 0 2006.257.11:34:16.21#ibcon#enter sib2, iclass 25, count 0 2006.257.11:34:16.21#ibcon#flushed, iclass 25, count 0 2006.257.11:34:16.21#ibcon#about to write, iclass 25, count 0 2006.257.11:34:16.21#ibcon#wrote, iclass 25, count 0 2006.257.11:34:16.21#ibcon#about to read 3, iclass 25, count 0 2006.257.11:34:16.23#ibcon#read 3, iclass 25, count 0 2006.257.11:34:16.23#ibcon#about to read 4, iclass 25, count 0 2006.257.11:34:16.23#ibcon#read 4, iclass 25, count 0 2006.257.11:34:16.23#ibcon#about to read 5, iclass 25, count 0 2006.257.11:34:16.23#ibcon#read 5, iclass 25, count 0 2006.257.11:34:16.23#ibcon#about to read 6, iclass 25, count 0 2006.257.11:34:16.23#ibcon#read 6, iclass 25, count 0 2006.257.11:34:16.23#ibcon#end of sib2, iclass 25, count 0 2006.257.11:34:16.23#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:34:16.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:34:16.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:34:16.23#ibcon#*before write, iclass 25, count 0 2006.257.11:34:16.23#ibcon#enter sib2, iclass 25, count 0 2006.257.11:34:16.23#ibcon#flushed, iclass 25, count 0 2006.257.11:34:16.23#ibcon#about to write, iclass 25, count 0 2006.257.11:34:16.23#ibcon#wrote, iclass 25, count 0 2006.257.11:34:16.23#ibcon#about to read 3, iclass 25, count 0 2006.257.11:34:16.27#ibcon#read 3, iclass 25, count 0 2006.257.11:34:16.27#ibcon#about to read 4, iclass 25, count 0 2006.257.11:34:16.27#ibcon#read 4, iclass 25, count 0 2006.257.11:34:16.27#ibcon#about to read 5, iclass 25, count 0 2006.257.11:34:16.27#ibcon#read 5, iclass 25, count 0 2006.257.11:34:16.27#ibcon#about to read 6, iclass 25, count 0 2006.257.11:34:16.27#ibcon#read 6, iclass 25, count 0 2006.257.11:34:16.27#ibcon#end of sib2, iclass 25, count 0 2006.257.11:34:16.27#ibcon#*after write, iclass 25, count 0 2006.257.11:34:16.27#ibcon#*before return 0, iclass 25, count 0 2006.257.11:34:16.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:16.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:16.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:34:16.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:34:16.27$vck44/va=4,7 2006.257.11:34:16.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.11:34:16.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.11:34:16.27#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:16.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:16.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:16.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:16.33#ibcon#enter wrdev, iclass 27, count 2 2006.257.11:34:16.33#ibcon#first serial, iclass 27, count 2 2006.257.11:34:16.33#ibcon#enter sib2, iclass 27, count 2 2006.257.11:34:16.33#ibcon#flushed, iclass 27, count 2 2006.257.11:34:16.33#ibcon#about to write, iclass 27, count 2 2006.257.11:34:16.33#ibcon#wrote, iclass 27, count 2 2006.257.11:34:16.33#ibcon#about to read 3, iclass 27, count 2 2006.257.11:34:16.35#ibcon#read 3, iclass 27, count 2 2006.257.11:34:16.35#ibcon#about to read 4, iclass 27, count 2 2006.257.11:34:16.35#ibcon#read 4, iclass 27, count 2 2006.257.11:34:16.35#ibcon#about to read 5, iclass 27, count 2 2006.257.11:34:16.35#ibcon#read 5, iclass 27, count 2 2006.257.11:34:16.35#ibcon#about to read 6, iclass 27, count 2 2006.257.11:34:16.35#ibcon#read 6, iclass 27, count 2 2006.257.11:34:16.35#ibcon#end of sib2, iclass 27, count 2 2006.257.11:34:16.35#ibcon#*mode == 0, iclass 27, count 2 2006.257.11:34:16.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.11:34:16.35#ibcon#[25=AT04-07\r\n] 2006.257.11:34:16.35#ibcon#*before write, iclass 27, count 2 2006.257.11:34:16.35#ibcon#enter sib2, iclass 27, count 2 2006.257.11:34:16.35#ibcon#flushed, iclass 27, count 2 2006.257.11:34:16.35#ibcon#about to write, iclass 27, count 2 2006.257.11:34:16.35#ibcon#wrote, iclass 27, count 2 2006.257.11:34:16.35#ibcon#about to read 3, iclass 27, count 2 2006.257.11:34:16.38#ibcon#read 3, iclass 27, count 2 2006.257.11:34:16.38#ibcon#about to read 4, iclass 27, count 2 2006.257.11:34:16.38#ibcon#read 4, iclass 27, count 2 2006.257.11:34:16.38#ibcon#about to read 5, iclass 27, count 2 2006.257.11:34:16.38#ibcon#read 5, iclass 27, count 2 2006.257.11:34:16.38#ibcon#about to read 6, iclass 27, count 2 2006.257.11:34:16.38#ibcon#read 6, iclass 27, count 2 2006.257.11:34:16.38#ibcon#end of sib2, iclass 27, count 2 2006.257.11:34:16.38#ibcon#*after write, iclass 27, count 2 2006.257.11:34:16.38#ibcon#*before return 0, iclass 27, count 2 2006.257.11:34:16.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:16.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:16.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.11:34:16.38#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:16.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:16.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:16.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:16.50#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:34:16.50#ibcon#first serial, iclass 27, count 0 2006.257.11:34:16.50#ibcon#enter sib2, iclass 27, count 0 2006.257.11:34:16.50#ibcon#flushed, iclass 27, count 0 2006.257.11:34:16.50#ibcon#about to write, iclass 27, count 0 2006.257.11:34:16.50#ibcon#wrote, iclass 27, count 0 2006.257.11:34:16.50#ibcon#about to read 3, iclass 27, count 0 2006.257.11:34:16.52#ibcon#read 3, iclass 27, count 0 2006.257.11:34:16.52#ibcon#about to read 4, iclass 27, count 0 2006.257.11:34:16.52#ibcon#read 4, iclass 27, count 0 2006.257.11:34:16.52#ibcon#about to read 5, iclass 27, count 0 2006.257.11:34:16.52#ibcon#read 5, iclass 27, count 0 2006.257.11:34:16.52#ibcon#about to read 6, iclass 27, count 0 2006.257.11:34:16.52#ibcon#read 6, iclass 27, count 0 2006.257.11:34:16.52#ibcon#end of sib2, iclass 27, count 0 2006.257.11:34:16.52#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:34:16.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:34:16.52#ibcon#[25=USB\r\n] 2006.257.11:34:16.52#ibcon#*before write, iclass 27, count 0 2006.257.11:34:16.52#ibcon#enter sib2, iclass 27, count 0 2006.257.11:34:16.52#ibcon#flushed, iclass 27, count 0 2006.257.11:34:16.52#ibcon#about to write, iclass 27, count 0 2006.257.11:34:16.52#ibcon#wrote, iclass 27, count 0 2006.257.11:34:16.52#ibcon#about to read 3, iclass 27, count 0 2006.257.11:34:16.55#ibcon#read 3, iclass 27, count 0 2006.257.11:34:16.55#ibcon#about to read 4, iclass 27, count 0 2006.257.11:34:16.55#ibcon#read 4, iclass 27, count 0 2006.257.11:34:16.55#ibcon#about to read 5, iclass 27, count 0 2006.257.11:34:16.55#ibcon#read 5, iclass 27, count 0 2006.257.11:34:16.55#ibcon#about to read 6, iclass 27, count 0 2006.257.11:34:16.55#ibcon#read 6, iclass 27, count 0 2006.257.11:34:16.55#ibcon#end of sib2, iclass 27, count 0 2006.257.11:34:16.55#ibcon#*after write, iclass 27, count 0 2006.257.11:34:16.55#ibcon#*before return 0, iclass 27, count 0 2006.257.11:34:16.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:16.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:16.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:34:16.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:34:16.55$vck44/valo=5,734.99 2006.257.11:34:16.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.11:34:16.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.11:34:16.55#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:16.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:16.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:16.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:16.55#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:34:16.55#ibcon#first serial, iclass 29, count 0 2006.257.11:34:16.55#ibcon#enter sib2, iclass 29, count 0 2006.257.11:34:16.55#ibcon#flushed, iclass 29, count 0 2006.257.11:34:16.55#ibcon#about to write, iclass 29, count 0 2006.257.11:34:16.55#ibcon#wrote, iclass 29, count 0 2006.257.11:34:16.55#ibcon#about to read 3, iclass 29, count 0 2006.257.11:34:16.57#ibcon#read 3, iclass 29, count 0 2006.257.11:34:16.57#ibcon#about to read 4, iclass 29, count 0 2006.257.11:34:16.57#ibcon#read 4, iclass 29, count 0 2006.257.11:34:16.57#ibcon#about to read 5, iclass 29, count 0 2006.257.11:34:16.57#ibcon#read 5, iclass 29, count 0 2006.257.11:34:16.57#ibcon#about to read 6, iclass 29, count 0 2006.257.11:34:16.57#ibcon#read 6, iclass 29, count 0 2006.257.11:34:16.57#ibcon#end of sib2, iclass 29, count 0 2006.257.11:34:16.57#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:34:16.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:34:16.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:34:16.57#ibcon#*before write, iclass 29, count 0 2006.257.11:34:16.57#ibcon#enter sib2, iclass 29, count 0 2006.257.11:34:16.57#ibcon#flushed, iclass 29, count 0 2006.257.11:34:16.57#ibcon#about to write, iclass 29, count 0 2006.257.11:34:16.57#ibcon#wrote, iclass 29, count 0 2006.257.11:34:16.57#ibcon#about to read 3, iclass 29, count 0 2006.257.11:34:16.61#ibcon#read 3, iclass 29, count 0 2006.257.11:34:16.61#ibcon#about to read 4, iclass 29, count 0 2006.257.11:34:16.61#ibcon#read 4, iclass 29, count 0 2006.257.11:34:16.61#ibcon#about to read 5, iclass 29, count 0 2006.257.11:34:16.61#ibcon#read 5, iclass 29, count 0 2006.257.11:34:16.61#ibcon#about to read 6, iclass 29, count 0 2006.257.11:34:16.61#ibcon#read 6, iclass 29, count 0 2006.257.11:34:16.61#ibcon#end of sib2, iclass 29, count 0 2006.257.11:34:16.61#ibcon#*after write, iclass 29, count 0 2006.257.11:34:16.61#ibcon#*before return 0, iclass 29, count 0 2006.257.11:34:16.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:16.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:16.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:34:16.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:34:16.61$vck44/va=5,4 2006.257.11:34:16.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.11:34:16.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.11:34:16.61#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:16.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:16.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:16.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:16.67#ibcon#enter wrdev, iclass 31, count 2 2006.257.11:34:16.67#ibcon#first serial, iclass 31, count 2 2006.257.11:34:16.67#ibcon#enter sib2, iclass 31, count 2 2006.257.11:34:16.67#ibcon#flushed, iclass 31, count 2 2006.257.11:34:16.67#ibcon#about to write, iclass 31, count 2 2006.257.11:34:16.67#ibcon#wrote, iclass 31, count 2 2006.257.11:34:16.67#ibcon#about to read 3, iclass 31, count 2 2006.257.11:34:16.69#ibcon#read 3, iclass 31, count 2 2006.257.11:34:16.69#ibcon#about to read 4, iclass 31, count 2 2006.257.11:34:16.69#ibcon#read 4, iclass 31, count 2 2006.257.11:34:16.69#ibcon#about to read 5, iclass 31, count 2 2006.257.11:34:16.69#ibcon#read 5, iclass 31, count 2 2006.257.11:34:16.69#ibcon#about to read 6, iclass 31, count 2 2006.257.11:34:16.69#ibcon#read 6, iclass 31, count 2 2006.257.11:34:16.69#ibcon#end of sib2, iclass 31, count 2 2006.257.11:34:16.69#ibcon#*mode == 0, iclass 31, count 2 2006.257.11:34:16.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.11:34:16.69#ibcon#[25=AT05-04\r\n] 2006.257.11:34:16.69#ibcon#*before write, iclass 31, count 2 2006.257.11:34:16.69#ibcon#enter sib2, iclass 31, count 2 2006.257.11:34:16.69#ibcon#flushed, iclass 31, count 2 2006.257.11:34:16.69#ibcon#about to write, iclass 31, count 2 2006.257.11:34:16.69#ibcon#wrote, iclass 31, count 2 2006.257.11:34:16.69#ibcon#about to read 3, iclass 31, count 2 2006.257.11:34:16.72#ibcon#read 3, iclass 31, count 2 2006.257.11:34:16.72#ibcon#about to read 4, iclass 31, count 2 2006.257.11:34:16.72#ibcon#read 4, iclass 31, count 2 2006.257.11:34:16.72#ibcon#about to read 5, iclass 31, count 2 2006.257.11:34:16.72#ibcon#read 5, iclass 31, count 2 2006.257.11:34:16.72#ibcon#about to read 6, iclass 31, count 2 2006.257.11:34:16.72#ibcon#read 6, iclass 31, count 2 2006.257.11:34:16.72#ibcon#end of sib2, iclass 31, count 2 2006.257.11:34:16.72#ibcon#*after write, iclass 31, count 2 2006.257.11:34:16.72#ibcon#*before return 0, iclass 31, count 2 2006.257.11:34:16.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:16.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:16.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.11:34:16.72#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:16.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:16.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:16.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:16.84#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:34:16.84#ibcon#first serial, iclass 31, count 0 2006.257.11:34:16.84#ibcon#enter sib2, iclass 31, count 0 2006.257.11:34:16.84#ibcon#flushed, iclass 31, count 0 2006.257.11:34:16.84#ibcon#about to write, iclass 31, count 0 2006.257.11:34:16.84#ibcon#wrote, iclass 31, count 0 2006.257.11:34:16.84#ibcon#about to read 3, iclass 31, count 0 2006.257.11:34:16.86#ibcon#read 3, iclass 31, count 0 2006.257.11:34:16.86#ibcon#about to read 4, iclass 31, count 0 2006.257.11:34:16.86#ibcon#read 4, iclass 31, count 0 2006.257.11:34:16.86#ibcon#about to read 5, iclass 31, count 0 2006.257.11:34:16.86#ibcon#read 5, iclass 31, count 0 2006.257.11:34:16.86#ibcon#about to read 6, iclass 31, count 0 2006.257.11:34:16.86#ibcon#read 6, iclass 31, count 0 2006.257.11:34:16.86#ibcon#end of sib2, iclass 31, count 0 2006.257.11:34:16.86#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:34:16.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:34:16.86#ibcon#[25=USB\r\n] 2006.257.11:34:16.86#ibcon#*before write, iclass 31, count 0 2006.257.11:34:16.86#ibcon#enter sib2, iclass 31, count 0 2006.257.11:34:16.86#ibcon#flushed, iclass 31, count 0 2006.257.11:34:16.86#ibcon#about to write, iclass 31, count 0 2006.257.11:34:16.86#ibcon#wrote, iclass 31, count 0 2006.257.11:34:16.86#ibcon#about to read 3, iclass 31, count 0 2006.257.11:34:16.89#ibcon#read 3, iclass 31, count 0 2006.257.11:34:16.89#ibcon#about to read 4, iclass 31, count 0 2006.257.11:34:16.89#ibcon#read 4, iclass 31, count 0 2006.257.11:34:16.89#ibcon#about to read 5, iclass 31, count 0 2006.257.11:34:16.89#ibcon#read 5, iclass 31, count 0 2006.257.11:34:16.89#ibcon#about to read 6, iclass 31, count 0 2006.257.11:34:16.89#ibcon#read 6, iclass 31, count 0 2006.257.11:34:16.89#ibcon#end of sib2, iclass 31, count 0 2006.257.11:34:16.89#ibcon#*after write, iclass 31, count 0 2006.257.11:34:16.89#ibcon#*before return 0, iclass 31, count 0 2006.257.11:34:16.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:16.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:16.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:34:16.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:34:16.89$vck44/valo=6,814.99 2006.257.11:34:16.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.11:34:16.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.11:34:16.89#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:16.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:16.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:16.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:16.89#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:34:16.89#ibcon#first serial, iclass 33, count 0 2006.257.11:34:16.89#ibcon#enter sib2, iclass 33, count 0 2006.257.11:34:16.89#ibcon#flushed, iclass 33, count 0 2006.257.11:34:16.89#ibcon#about to write, iclass 33, count 0 2006.257.11:34:16.89#ibcon#wrote, iclass 33, count 0 2006.257.11:34:16.89#ibcon#about to read 3, iclass 33, count 0 2006.257.11:34:16.91#ibcon#read 3, iclass 33, count 0 2006.257.11:34:16.91#ibcon#about to read 4, iclass 33, count 0 2006.257.11:34:16.91#ibcon#read 4, iclass 33, count 0 2006.257.11:34:16.91#ibcon#about to read 5, iclass 33, count 0 2006.257.11:34:16.91#ibcon#read 5, iclass 33, count 0 2006.257.11:34:16.91#ibcon#about to read 6, iclass 33, count 0 2006.257.11:34:16.91#ibcon#read 6, iclass 33, count 0 2006.257.11:34:16.91#ibcon#end of sib2, iclass 33, count 0 2006.257.11:34:16.91#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:34:16.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:34:16.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:34:16.91#ibcon#*before write, iclass 33, count 0 2006.257.11:34:16.91#ibcon#enter sib2, iclass 33, count 0 2006.257.11:34:16.91#ibcon#flushed, iclass 33, count 0 2006.257.11:34:16.91#ibcon#about to write, iclass 33, count 0 2006.257.11:34:16.91#ibcon#wrote, iclass 33, count 0 2006.257.11:34:16.91#ibcon#about to read 3, iclass 33, count 0 2006.257.11:34:16.95#ibcon#read 3, iclass 33, count 0 2006.257.11:34:16.95#ibcon#about to read 4, iclass 33, count 0 2006.257.11:34:16.95#ibcon#read 4, iclass 33, count 0 2006.257.11:34:16.95#ibcon#about to read 5, iclass 33, count 0 2006.257.11:34:16.95#ibcon#read 5, iclass 33, count 0 2006.257.11:34:16.95#ibcon#about to read 6, iclass 33, count 0 2006.257.11:34:16.95#ibcon#read 6, iclass 33, count 0 2006.257.11:34:16.95#ibcon#end of sib2, iclass 33, count 0 2006.257.11:34:16.95#ibcon#*after write, iclass 33, count 0 2006.257.11:34:16.95#ibcon#*before return 0, iclass 33, count 0 2006.257.11:34:16.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:16.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:16.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:34:16.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:34:16.95$vck44/va=6,4 2006.257.11:34:16.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.11:34:16.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.11:34:16.95#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:16.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:17.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:17.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:17.01#ibcon#enter wrdev, iclass 35, count 2 2006.257.11:34:17.01#ibcon#first serial, iclass 35, count 2 2006.257.11:34:17.01#ibcon#enter sib2, iclass 35, count 2 2006.257.11:34:17.01#ibcon#flushed, iclass 35, count 2 2006.257.11:34:17.01#ibcon#about to write, iclass 35, count 2 2006.257.11:34:17.01#ibcon#wrote, iclass 35, count 2 2006.257.11:34:17.01#ibcon#about to read 3, iclass 35, count 2 2006.257.11:34:17.03#ibcon#read 3, iclass 35, count 2 2006.257.11:34:17.03#ibcon#about to read 4, iclass 35, count 2 2006.257.11:34:17.03#ibcon#read 4, iclass 35, count 2 2006.257.11:34:17.03#ibcon#about to read 5, iclass 35, count 2 2006.257.11:34:17.03#ibcon#read 5, iclass 35, count 2 2006.257.11:34:17.03#ibcon#about to read 6, iclass 35, count 2 2006.257.11:34:17.03#ibcon#read 6, iclass 35, count 2 2006.257.11:34:17.03#ibcon#end of sib2, iclass 35, count 2 2006.257.11:34:17.03#ibcon#*mode == 0, iclass 35, count 2 2006.257.11:34:17.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.11:34:17.03#ibcon#[25=AT06-04\r\n] 2006.257.11:34:17.03#ibcon#*before write, iclass 35, count 2 2006.257.11:34:17.03#ibcon#enter sib2, iclass 35, count 2 2006.257.11:34:17.03#ibcon#flushed, iclass 35, count 2 2006.257.11:34:17.03#ibcon#about to write, iclass 35, count 2 2006.257.11:34:17.03#ibcon#wrote, iclass 35, count 2 2006.257.11:34:17.03#ibcon#about to read 3, iclass 35, count 2 2006.257.11:34:17.06#ibcon#read 3, iclass 35, count 2 2006.257.11:34:17.06#ibcon#about to read 4, iclass 35, count 2 2006.257.11:34:17.06#ibcon#read 4, iclass 35, count 2 2006.257.11:34:17.06#ibcon#about to read 5, iclass 35, count 2 2006.257.11:34:17.06#ibcon#read 5, iclass 35, count 2 2006.257.11:34:17.06#ibcon#about to read 6, iclass 35, count 2 2006.257.11:34:17.06#ibcon#read 6, iclass 35, count 2 2006.257.11:34:17.06#ibcon#end of sib2, iclass 35, count 2 2006.257.11:34:17.06#ibcon#*after write, iclass 35, count 2 2006.257.11:34:17.06#ibcon#*before return 0, iclass 35, count 2 2006.257.11:34:17.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:17.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:17.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.11:34:17.06#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:17.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:17.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:17.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:17.18#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:34:17.18#ibcon#first serial, iclass 35, count 0 2006.257.11:34:17.18#ibcon#enter sib2, iclass 35, count 0 2006.257.11:34:17.18#ibcon#flushed, iclass 35, count 0 2006.257.11:34:17.18#ibcon#about to write, iclass 35, count 0 2006.257.11:34:17.18#ibcon#wrote, iclass 35, count 0 2006.257.11:34:17.18#ibcon#about to read 3, iclass 35, count 0 2006.257.11:34:17.20#ibcon#read 3, iclass 35, count 0 2006.257.11:34:17.20#ibcon#about to read 4, iclass 35, count 0 2006.257.11:34:17.20#ibcon#read 4, iclass 35, count 0 2006.257.11:34:17.20#ibcon#about to read 5, iclass 35, count 0 2006.257.11:34:17.20#ibcon#read 5, iclass 35, count 0 2006.257.11:34:17.20#ibcon#about to read 6, iclass 35, count 0 2006.257.11:34:17.20#ibcon#read 6, iclass 35, count 0 2006.257.11:34:17.20#ibcon#end of sib2, iclass 35, count 0 2006.257.11:34:17.20#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:34:17.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:34:17.20#ibcon#[25=USB\r\n] 2006.257.11:34:17.20#ibcon#*before write, iclass 35, count 0 2006.257.11:34:17.20#ibcon#enter sib2, iclass 35, count 0 2006.257.11:34:17.20#ibcon#flushed, iclass 35, count 0 2006.257.11:34:17.20#ibcon#about to write, iclass 35, count 0 2006.257.11:34:17.20#ibcon#wrote, iclass 35, count 0 2006.257.11:34:17.20#ibcon#about to read 3, iclass 35, count 0 2006.257.11:34:17.23#ibcon#read 3, iclass 35, count 0 2006.257.11:34:17.23#ibcon#about to read 4, iclass 35, count 0 2006.257.11:34:17.23#ibcon#read 4, iclass 35, count 0 2006.257.11:34:17.23#ibcon#about to read 5, iclass 35, count 0 2006.257.11:34:17.23#ibcon#read 5, iclass 35, count 0 2006.257.11:34:17.23#ibcon#about to read 6, iclass 35, count 0 2006.257.11:34:17.23#ibcon#read 6, iclass 35, count 0 2006.257.11:34:17.23#ibcon#end of sib2, iclass 35, count 0 2006.257.11:34:17.23#ibcon#*after write, iclass 35, count 0 2006.257.11:34:17.23#ibcon#*before return 0, iclass 35, count 0 2006.257.11:34:17.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:17.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:17.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:34:17.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:34:17.23$vck44/valo=7,864.99 2006.257.11:34:17.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.11:34:17.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.11:34:17.23#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:17.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:17.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:17.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:17.23#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:34:17.23#ibcon#first serial, iclass 37, count 0 2006.257.11:34:17.23#ibcon#enter sib2, iclass 37, count 0 2006.257.11:34:17.23#ibcon#flushed, iclass 37, count 0 2006.257.11:34:17.23#ibcon#about to write, iclass 37, count 0 2006.257.11:34:17.23#ibcon#wrote, iclass 37, count 0 2006.257.11:34:17.23#ibcon#about to read 3, iclass 37, count 0 2006.257.11:34:17.25#ibcon#read 3, iclass 37, count 0 2006.257.11:34:17.25#ibcon#about to read 4, iclass 37, count 0 2006.257.11:34:17.25#ibcon#read 4, iclass 37, count 0 2006.257.11:34:17.25#ibcon#about to read 5, iclass 37, count 0 2006.257.11:34:17.25#ibcon#read 5, iclass 37, count 0 2006.257.11:34:17.25#ibcon#about to read 6, iclass 37, count 0 2006.257.11:34:17.25#ibcon#read 6, iclass 37, count 0 2006.257.11:34:17.25#ibcon#end of sib2, iclass 37, count 0 2006.257.11:34:17.25#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:34:17.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:34:17.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:34:17.25#ibcon#*before write, iclass 37, count 0 2006.257.11:34:17.25#ibcon#enter sib2, iclass 37, count 0 2006.257.11:34:17.25#ibcon#flushed, iclass 37, count 0 2006.257.11:34:17.25#ibcon#about to write, iclass 37, count 0 2006.257.11:34:17.25#ibcon#wrote, iclass 37, count 0 2006.257.11:34:17.25#ibcon#about to read 3, iclass 37, count 0 2006.257.11:34:17.29#ibcon#read 3, iclass 37, count 0 2006.257.11:34:17.29#ibcon#about to read 4, iclass 37, count 0 2006.257.11:34:17.29#ibcon#read 4, iclass 37, count 0 2006.257.11:34:17.29#ibcon#about to read 5, iclass 37, count 0 2006.257.11:34:17.29#ibcon#read 5, iclass 37, count 0 2006.257.11:34:17.29#ibcon#about to read 6, iclass 37, count 0 2006.257.11:34:17.29#ibcon#read 6, iclass 37, count 0 2006.257.11:34:17.29#ibcon#end of sib2, iclass 37, count 0 2006.257.11:34:17.29#ibcon#*after write, iclass 37, count 0 2006.257.11:34:17.29#ibcon#*before return 0, iclass 37, count 0 2006.257.11:34:17.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:17.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:17.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:34:17.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:34:17.29$vck44/va=7,4 2006.257.11:34:17.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.11:34:17.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.11:34:17.29#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:17.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:17.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:17.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:17.35#ibcon#enter wrdev, iclass 39, count 2 2006.257.11:34:17.35#ibcon#first serial, iclass 39, count 2 2006.257.11:34:17.35#ibcon#enter sib2, iclass 39, count 2 2006.257.11:34:17.35#ibcon#flushed, iclass 39, count 2 2006.257.11:34:17.35#ibcon#about to write, iclass 39, count 2 2006.257.11:34:17.35#ibcon#wrote, iclass 39, count 2 2006.257.11:34:17.35#ibcon#about to read 3, iclass 39, count 2 2006.257.11:34:17.37#ibcon#read 3, iclass 39, count 2 2006.257.11:34:17.37#ibcon#about to read 4, iclass 39, count 2 2006.257.11:34:17.37#ibcon#read 4, iclass 39, count 2 2006.257.11:34:17.37#ibcon#about to read 5, iclass 39, count 2 2006.257.11:34:17.37#ibcon#read 5, iclass 39, count 2 2006.257.11:34:17.37#ibcon#about to read 6, iclass 39, count 2 2006.257.11:34:17.37#ibcon#read 6, iclass 39, count 2 2006.257.11:34:17.37#ibcon#end of sib2, iclass 39, count 2 2006.257.11:34:17.37#ibcon#*mode == 0, iclass 39, count 2 2006.257.11:34:17.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.11:34:17.37#ibcon#[25=AT07-04\r\n] 2006.257.11:34:17.37#ibcon#*before write, iclass 39, count 2 2006.257.11:34:17.37#ibcon#enter sib2, iclass 39, count 2 2006.257.11:34:17.37#ibcon#flushed, iclass 39, count 2 2006.257.11:34:17.37#ibcon#about to write, iclass 39, count 2 2006.257.11:34:17.37#ibcon#wrote, iclass 39, count 2 2006.257.11:34:17.37#ibcon#about to read 3, iclass 39, count 2 2006.257.11:34:17.40#ibcon#read 3, iclass 39, count 2 2006.257.11:34:17.40#ibcon#about to read 4, iclass 39, count 2 2006.257.11:34:17.40#ibcon#read 4, iclass 39, count 2 2006.257.11:34:17.40#ibcon#about to read 5, iclass 39, count 2 2006.257.11:34:17.40#ibcon#read 5, iclass 39, count 2 2006.257.11:34:17.40#ibcon#about to read 6, iclass 39, count 2 2006.257.11:34:17.40#ibcon#read 6, iclass 39, count 2 2006.257.11:34:17.40#ibcon#end of sib2, iclass 39, count 2 2006.257.11:34:17.40#ibcon#*after write, iclass 39, count 2 2006.257.11:34:17.40#ibcon#*before return 0, iclass 39, count 2 2006.257.11:34:17.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:17.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:17.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.11:34:17.43#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:17.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:17.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:17.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:17.55#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:34:17.55#ibcon#first serial, iclass 39, count 0 2006.257.11:34:17.55#ibcon#enter sib2, iclass 39, count 0 2006.257.11:34:17.55#ibcon#flushed, iclass 39, count 0 2006.257.11:34:17.55#ibcon#about to write, iclass 39, count 0 2006.257.11:34:17.55#ibcon#wrote, iclass 39, count 0 2006.257.11:34:17.55#ibcon#about to read 3, iclass 39, count 0 2006.257.11:34:17.57#ibcon#read 3, iclass 39, count 0 2006.257.11:34:17.57#ibcon#about to read 4, iclass 39, count 0 2006.257.11:34:17.57#ibcon#read 4, iclass 39, count 0 2006.257.11:34:17.57#ibcon#about to read 5, iclass 39, count 0 2006.257.11:34:17.57#ibcon#read 5, iclass 39, count 0 2006.257.11:34:17.57#ibcon#about to read 6, iclass 39, count 0 2006.257.11:34:17.57#ibcon#read 6, iclass 39, count 0 2006.257.11:34:17.57#ibcon#end of sib2, iclass 39, count 0 2006.257.11:34:17.57#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:34:17.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:34:17.57#ibcon#[25=USB\r\n] 2006.257.11:34:17.57#ibcon#*before write, iclass 39, count 0 2006.257.11:34:17.57#ibcon#enter sib2, iclass 39, count 0 2006.257.11:34:17.57#ibcon#flushed, iclass 39, count 0 2006.257.11:34:17.57#ibcon#about to write, iclass 39, count 0 2006.257.11:34:17.57#ibcon#wrote, iclass 39, count 0 2006.257.11:34:17.57#ibcon#about to read 3, iclass 39, count 0 2006.257.11:34:17.60#ibcon#read 3, iclass 39, count 0 2006.257.11:34:17.60#ibcon#about to read 4, iclass 39, count 0 2006.257.11:34:17.60#ibcon#read 4, iclass 39, count 0 2006.257.11:34:17.60#ibcon#about to read 5, iclass 39, count 0 2006.257.11:34:17.60#ibcon#read 5, iclass 39, count 0 2006.257.11:34:17.60#ibcon#about to read 6, iclass 39, count 0 2006.257.11:34:17.60#ibcon#read 6, iclass 39, count 0 2006.257.11:34:17.60#ibcon#end of sib2, iclass 39, count 0 2006.257.11:34:17.60#ibcon#*after write, iclass 39, count 0 2006.257.11:34:17.60#ibcon#*before return 0, iclass 39, count 0 2006.257.11:34:17.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:17.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:17.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:34:17.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:34:17.60$vck44/valo=8,884.99 2006.257.11:34:17.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.11:34:17.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.11:34:17.60#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:17.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:17.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:17.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:17.60#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:34:17.60#ibcon#first serial, iclass 3, count 0 2006.257.11:34:17.60#ibcon#enter sib2, iclass 3, count 0 2006.257.11:34:17.60#ibcon#flushed, iclass 3, count 0 2006.257.11:34:17.60#ibcon#about to write, iclass 3, count 0 2006.257.11:34:17.60#ibcon#wrote, iclass 3, count 0 2006.257.11:34:17.60#ibcon#about to read 3, iclass 3, count 0 2006.257.11:34:17.62#ibcon#read 3, iclass 3, count 0 2006.257.11:34:17.62#ibcon#about to read 4, iclass 3, count 0 2006.257.11:34:17.62#ibcon#read 4, iclass 3, count 0 2006.257.11:34:17.62#ibcon#about to read 5, iclass 3, count 0 2006.257.11:34:17.62#ibcon#read 5, iclass 3, count 0 2006.257.11:34:17.62#ibcon#about to read 6, iclass 3, count 0 2006.257.11:34:17.62#ibcon#read 6, iclass 3, count 0 2006.257.11:34:17.62#ibcon#end of sib2, iclass 3, count 0 2006.257.11:34:17.62#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:34:17.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:34:17.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:34:17.62#ibcon#*before write, iclass 3, count 0 2006.257.11:34:17.62#ibcon#enter sib2, iclass 3, count 0 2006.257.11:34:17.62#ibcon#flushed, iclass 3, count 0 2006.257.11:34:17.62#ibcon#about to write, iclass 3, count 0 2006.257.11:34:17.62#ibcon#wrote, iclass 3, count 0 2006.257.11:34:17.62#ibcon#about to read 3, iclass 3, count 0 2006.257.11:34:17.66#ibcon#read 3, iclass 3, count 0 2006.257.11:34:17.66#ibcon#about to read 4, iclass 3, count 0 2006.257.11:34:17.66#ibcon#read 4, iclass 3, count 0 2006.257.11:34:17.66#ibcon#about to read 5, iclass 3, count 0 2006.257.11:34:17.66#ibcon#read 5, iclass 3, count 0 2006.257.11:34:17.66#ibcon#about to read 6, iclass 3, count 0 2006.257.11:34:17.66#ibcon#read 6, iclass 3, count 0 2006.257.11:34:17.66#ibcon#end of sib2, iclass 3, count 0 2006.257.11:34:17.66#ibcon#*after write, iclass 3, count 0 2006.257.11:34:17.66#ibcon#*before return 0, iclass 3, count 0 2006.257.11:34:17.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:17.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:17.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:34:17.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:34:17.66$vck44/va=8,4 2006.257.11:34:17.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.11:34:17.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.11:34:17.66#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:17.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:34:17.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:34:17.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:34:17.72#ibcon#enter wrdev, iclass 5, count 2 2006.257.11:34:17.72#ibcon#first serial, iclass 5, count 2 2006.257.11:34:17.72#ibcon#enter sib2, iclass 5, count 2 2006.257.11:34:17.72#ibcon#flushed, iclass 5, count 2 2006.257.11:34:17.72#ibcon#about to write, iclass 5, count 2 2006.257.11:34:17.72#ibcon#wrote, iclass 5, count 2 2006.257.11:34:17.72#ibcon#about to read 3, iclass 5, count 2 2006.257.11:34:17.74#ibcon#read 3, iclass 5, count 2 2006.257.11:34:17.74#ibcon#about to read 4, iclass 5, count 2 2006.257.11:34:17.74#ibcon#read 4, iclass 5, count 2 2006.257.11:34:17.74#ibcon#about to read 5, iclass 5, count 2 2006.257.11:34:17.74#ibcon#read 5, iclass 5, count 2 2006.257.11:34:17.74#ibcon#about to read 6, iclass 5, count 2 2006.257.11:34:17.74#ibcon#read 6, iclass 5, count 2 2006.257.11:34:17.74#ibcon#end of sib2, iclass 5, count 2 2006.257.11:34:17.74#ibcon#*mode == 0, iclass 5, count 2 2006.257.11:34:17.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.11:34:17.74#ibcon#[25=AT08-04\r\n] 2006.257.11:34:17.74#ibcon#*before write, iclass 5, count 2 2006.257.11:34:17.74#ibcon#enter sib2, iclass 5, count 2 2006.257.11:34:17.74#ibcon#flushed, iclass 5, count 2 2006.257.11:34:17.74#ibcon#about to write, iclass 5, count 2 2006.257.11:34:17.74#ibcon#wrote, iclass 5, count 2 2006.257.11:34:17.74#ibcon#about to read 3, iclass 5, count 2 2006.257.11:34:17.77#ibcon#read 3, iclass 5, count 2 2006.257.11:34:17.77#ibcon#about to read 4, iclass 5, count 2 2006.257.11:34:17.77#ibcon#read 4, iclass 5, count 2 2006.257.11:34:17.77#ibcon#about to read 5, iclass 5, count 2 2006.257.11:34:17.77#ibcon#read 5, iclass 5, count 2 2006.257.11:34:17.77#ibcon#about to read 6, iclass 5, count 2 2006.257.11:34:17.77#ibcon#read 6, iclass 5, count 2 2006.257.11:34:17.77#ibcon#end of sib2, iclass 5, count 2 2006.257.11:34:17.77#ibcon#*after write, iclass 5, count 2 2006.257.11:34:17.77#ibcon#*before return 0, iclass 5, count 2 2006.257.11:34:17.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:34:17.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:34:17.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.11:34:17.77#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:17.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:34:17.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:34:17.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:34:17.89#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:34:17.89#ibcon#first serial, iclass 5, count 0 2006.257.11:34:17.89#ibcon#enter sib2, iclass 5, count 0 2006.257.11:34:17.89#ibcon#flushed, iclass 5, count 0 2006.257.11:34:17.89#ibcon#about to write, iclass 5, count 0 2006.257.11:34:17.89#ibcon#wrote, iclass 5, count 0 2006.257.11:34:17.89#ibcon#about to read 3, iclass 5, count 0 2006.257.11:34:17.91#ibcon#read 3, iclass 5, count 0 2006.257.11:34:17.91#ibcon#about to read 4, iclass 5, count 0 2006.257.11:34:17.91#ibcon#read 4, iclass 5, count 0 2006.257.11:34:17.91#ibcon#about to read 5, iclass 5, count 0 2006.257.11:34:17.91#ibcon#read 5, iclass 5, count 0 2006.257.11:34:17.91#ibcon#about to read 6, iclass 5, count 0 2006.257.11:34:17.91#ibcon#read 6, iclass 5, count 0 2006.257.11:34:17.91#ibcon#end of sib2, iclass 5, count 0 2006.257.11:34:17.91#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:34:17.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:34:17.91#ibcon#[25=USB\r\n] 2006.257.11:34:17.91#ibcon#*before write, iclass 5, count 0 2006.257.11:34:17.91#ibcon#enter sib2, iclass 5, count 0 2006.257.11:34:17.91#ibcon#flushed, iclass 5, count 0 2006.257.11:34:17.91#ibcon#about to write, iclass 5, count 0 2006.257.11:34:17.91#ibcon#wrote, iclass 5, count 0 2006.257.11:34:17.91#ibcon#about to read 3, iclass 5, count 0 2006.257.11:34:17.94#ibcon#read 3, iclass 5, count 0 2006.257.11:34:17.94#ibcon#about to read 4, iclass 5, count 0 2006.257.11:34:17.94#ibcon#read 4, iclass 5, count 0 2006.257.11:34:17.94#ibcon#about to read 5, iclass 5, count 0 2006.257.11:34:17.94#ibcon#read 5, iclass 5, count 0 2006.257.11:34:17.94#ibcon#about to read 6, iclass 5, count 0 2006.257.11:34:17.94#ibcon#read 6, iclass 5, count 0 2006.257.11:34:17.94#ibcon#end of sib2, iclass 5, count 0 2006.257.11:34:17.94#ibcon#*after write, iclass 5, count 0 2006.257.11:34:17.94#ibcon#*before return 0, iclass 5, count 0 2006.257.11:34:17.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:34:17.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:34:17.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:34:17.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:34:17.94$vck44/vblo=1,629.99 2006.257.11:34:17.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.11:34:17.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.11:34:17.94#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:17.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:34:17.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:34:17.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:34:17.94#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:34:17.94#ibcon#first serial, iclass 7, count 0 2006.257.11:34:17.94#ibcon#enter sib2, iclass 7, count 0 2006.257.11:34:17.94#ibcon#flushed, iclass 7, count 0 2006.257.11:34:17.94#ibcon#about to write, iclass 7, count 0 2006.257.11:34:17.94#ibcon#wrote, iclass 7, count 0 2006.257.11:34:17.94#ibcon#about to read 3, iclass 7, count 0 2006.257.11:34:17.96#ibcon#read 3, iclass 7, count 0 2006.257.11:34:17.96#ibcon#about to read 4, iclass 7, count 0 2006.257.11:34:17.96#ibcon#read 4, iclass 7, count 0 2006.257.11:34:17.96#ibcon#about to read 5, iclass 7, count 0 2006.257.11:34:17.96#ibcon#read 5, iclass 7, count 0 2006.257.11:34:17.96#ibcon#about to read 6, iclass 7, count 0 2006.257.11:34:17.96#ibcon#read 6, iclass 7, count 0 2006.257.11:34:17.96#ibcon#end of sib2, iclass 7, count 0 2006.257.11:34:17.96#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:34:17.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:34:17.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:34:17.96#ibcon#*before write, iclass 7, count 0 2006.257.11:34:17.96#ibcon#enter sib2, iclass 7, count 0 2006.257.11:34:17.96#ibcon#flushed, iclass 7, count 0 2006.257.11:34:17.96#ibcon#about to write, iclass 7, count 0 2006.257.11:34:17.96#ibcon#wrote, iclass 7, count 0 2006.257.11:34:17.96#ibcon#about to read 3, iclass 7, count 0 2006.257.11:34:18.00#ibcon#read 3, iclass 7, count 0 2006.257.11:34:18.00#ibcon#about to read 4, iclass 7, count 0 2006.257.11:34:18.00#ibcon#read 4, iclass 7, count 0 2006.257.11:34:18.00#ibcon#about to read 5, iclass 7, count 0 2006.257.11:34:18.00#ibcon#read 5, iclass 7, count 0 2006.257.11:34:18.00#ibcon#about to read 6, iclass 7, count 0 2006.257.11:34:18.00#ibcon#read 6, iclass 7, count 0 2006.257.11:34:18.00#ibcon#end of sib2, iclass 7, count 0 2006.257.11:34:18.00#ibcon#*after write, iclass 7, count 0 2006.257.11:34:18.00#ibcon#*before return 0, iclass 7, count 0 2006.257.11:34:18.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:34:18.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:34:18.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:34:18.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:34:18.00$vck44/vb=1,4 2006.257.11:34:18.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.11:34:18.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.11:34:18.00#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:18.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:34:18.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:34:18.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:34:18.00#ibcon#enter wrdev, iclass 11, count 2 2006.257.11:34:18.00#ibcon#first serial, iclass 11, count 2 2006.257.11:34:18.00#ibcon#enter sib2, iclass 11, count 2 2006.257.11:34:18.00#ibcon#flushed, iclass 11, count 2 2006.257.11:34:18.00#ibcon#about to write, iclass 11, count 2 2006.257.11:34:18.00#ibcon#wrote, iclass 11, count 2 2006.257.11:34:18.00#ibcon#about to read 3, iclass 11, count 2 2006.257.11:34:18.02#ibcon#read 3, iclass 11, count 2 2006.257.11:34:18.02#ibcon#about to read 4, iclass 11, count 2 2006.257.11:34:18.02#ibcon#read 4, iclass 11, count 2 2006.257.11:34:18.02#ibcon#about to read 5, iclass 11, count 2 2006.257.11:34:18.02#ibcon#read 5, iclass 11, count 2 2006.257.11:34:18.02#ibcon#about to read 6, iclass 11, count 2 2006.257.11:34:18.02#ibcon#read 6, iclass 11, count 2 2006.257.11:34:18.02#ibcon#end of sib2, iclass 11, count 2 2006.257.11:34:18.02#ibcon#*mode == 0, iclass 11, count 2 2006.257.11:34:18.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.11:34:18.02#ibcon#[27=AT01-04\r\n] 2006.257.11:34:18.02#ibcon#*before write, iclass 11, count 2 2006.257.11:34:18.02#ibcon#enter sib2, iclass 11, count 2 2006.257.11:34:18.02#ibcon#flushed, iclass 11, count 2 2006.257.11:34:18.02#ibcon#about to write, iclass 11, count 2 2006.257.11:34:18.02#ibcon#wrote, iclass 11, count 2 2006.257.11:34:18.02#ibcon#about to read 3, iclass 11, count 2 2006.257.11:34:18.05#ibcon#read 3, iclass 11, count 2 2006.257.11:34:18.05#ibcon#about to read 4, iclass 11, count 2 2006.257.11:34:18.05#ibcon#read 4, iclass 11, count 2 2006.257.11:34:18.05#ibcon#about to read 5, iclass 11, count 2 2006.257.11:34:18.05#ibcon#read 5, iclass 11, count 2 2006.257.11:34:18.05#ibcon#about to read 6, iclass 11, count 2 2006.257.11:34:18.05#ibcon#read 6, iclass 11, count 2 2006.257.11:34:18.05#ibcon#end of sib2, iclass 11, count 2 2006.257.11:34:18.05#ibcon#*after write, iclass 11, count 2 2006.257.11:34:18.05#ibcon#*before return 0, iclass 11, count 2 2006.257.11:34:18.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:34:18.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:34:18.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.11:34:18.05#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:18.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:34:18.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:34:18.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:34:18.17#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:34:18.17#ibcon#first serial, iclass 11, count 0 2006.257.11:34:18.17#ibcon#enter sib2, iclass 11, count 0 2006.257.11:34:18.17#ibcon#flushed, iclass 11, count 0 2006.257.11:34:18.17#ibcon#about to write, iclass 11, count 0 2006.257.11:34:18.17#ibcon#wrote, iclass 11, count 0 2006.257.11:34:18.17#ibcon#about to read 3, iclass 11, count 0 2006.257.11:34:18.19#ibcon#read 3, iclass 11, count 0 2006.257.11:34:18.19#ibcon#about to read 4, iclass 11, count 0 2006.257.11:34:18.19#ibcon#read 4, iclass 11, count 0 2006.257.11:34:18.19#ibcon#about to read 5, iclass 11, count 0 2006.257.11:34:18.19#ibcon#read 5, iclass 11, count 0 2006.257.11:34:18.19#ibcon#about to read 6, iclass 11, count 0 2006.257.11:34:18.19#ibcon#read 6, iclass 11, count 0 2006.257.11:34:18.19#ibcon#end of sib2, iclass 11, count 0 2006.257.11:34:18.19#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:34:18.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:34:18.19#ibcon#[27=USB\r\n] 2006.257.11:34:18.19#ibcon#*before write, iclass 11, count 0 2006.257.11:34:18.19#ibcon#enter sib2, iclass 11, count 0 2006.257.11:34:18.19#ibcon#flushed, iclass 11, count 0 2006.257.11:34:18.19#ibcon#about to write, iclass 11, count 0 2006.257.11:34:18.19#ibcon#wrote, iclass 11, count 0 2006.257.11:34:18.19#ibcon#about to read 3, iclass 11, count 0 2006.257.11:34:18.22#ibcon#read 3, iclass 11, count 0 2006.257.11:34:18.22#ibcon#about to read 4, iclass 11, count 0 2006.257.11:34:18.22#ibcon#read 4, iclass 11, count 0 2006.257.11:34:18.22#ibcon#about to read 5, iclass 11, count 0 2006.257.11:34:18.22#ibcon#read 5, iclass 11, count 0 2006.257.11:34:18.22#ibcon#about to read 6, iclass 11, count 0 2006.257.11:34:18.22#ibcon#read 6, iclass 11, count 0 2006.257.11:34:18.22#ibcon#end of sib2, iclass 11, count 0 2006.257.11:34:18.22#ibcon#*after write, iclass 11, count 0 2006.257.11:34:18.22#ibcon#*before return 0, iclass 11, count 0 2006.257.11:34:18.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:34:18.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:34:18.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:34:18.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:34:18.22$vck44/vblo=2,634.99 2006.257.11:34:18.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.11:34:18.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.11:34:18.22#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:18.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:18.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:18.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:18.22#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:34:18.22#ibcon#first serial, iclass 13, count 0 2006.257.11:34:18.22#ibcon#enter sib2, iclass 13, count 0 2006.257.11:34:18.22#ibcon#flushed, iclass 13, count 0 2006.257.11:34:18.22#ibcon#about to write, iclass 13, count 0 2006.257.11:34:18.22#ibcon#wrote, iclass 13, count 0 2006.257.11:34:18.22#ibcon#about to read 3, iclass 13, count 0 2006.257.11:34:18.24#ibcon#read 3, iclass 13, count 0 2006.257.11:34:18.24#ibcon#about to read 4, iclass 13, count 0 2006.257.11:34:18.24#ibcon#read 4, iclass 13, count 0 2006.257.11:34:18.24#ibcon#about to read 5, iclass 13, count 0 2006.257.11:34:18.24#ibcon#read 5, iclass 13, count 0 2006.257.11:34:18.24#ibcon#about to read 6, iclass 13, count 0 2006.257.11:34:18.24#ibcon#read 6, iclass 13, count 0 2006.257.11:34:18.24#ibcon#end of sib2, iclass 13, count 0 2006.257.11:34:18.24#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:34:18.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:34:18.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:34:18.24#ibcon#*before write, iclass 13, count 0 2006.257.11:34:18.24#ibcon#enter sib2, iclass 13, count 0 2006.257.11:34:18.24#ibcon#flushed, iclass 13, count 0 2006.257.11:34:18.24#ibcon#about to write, iclass 13, count 0 2006.257.11:34:18.24#ibcon#wrote, iclass 13, count 0 2006.257.11:34:18.24#ibcon#about to read 3, iclass 13, count 0 2006.257.11:34:18.28#ibcon#read 3, iclass 13, count 0 2006.257.11:34:18.28#ibcon#about to read 4, iclass 13, count 0 2006.257.11:34:18.28#ibcon#read 4, iclass 13, count 0 2006.257.11:34:18.28#ibcon#about to read 5, iclass 13, count 0 2006.257.11:34:18.28#ibcon#read 5, iclass 13, count 0 2006.257.11:34:18.28#ibcon#about to read 6, iclass 13, count 0 2006.257.11:34:18.28#ibcon#read 6, iclass 13, count 0 2006.257.11:34:18.28#ibcon#end of sib2, iclass 13, count 0 2006.257.11:34:18.28#ibcon#*after write, iclass 13, count 0 2006.257.11:34:18.28#ibcon#*before return 0, iclass 13, count 0 2006.257.11:34:18.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:18.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:34:18.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:34:18.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:34:18.28$vck44/vb=2,5 2006.257.11:34:18.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.11:34:18.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.11:34:18.28#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:18.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:18.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:18.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:18.34#ibcon#enter wrdev, iclass 15, count 2 2006.257.11:34:18.34#ibcon#first serial, iclass 15, count 2 2006.257.11:34:18.34#ibcon#enter sib2, iclass 15, count 2 2006.257.11:34:18.34#ibcon#flushed, iclass 15, count 2 2006.257.11:34:18.34#ibcon#about to write, iclass 15, count 2 2006.257.11:34:18.34#ibcon#wrote, iclass 15, count 2 2006.257.11:34:18.34#ibcon#about to read 3, iclass 15, count 2 2006.257.11:34:18.36#ibcon#read 3, iclass 15, count 2 2006.257.11:34:18.36#ibcon#about to read 4, iclass 15, count 2 2006.257.11:34:18.36#ibcon#read 4, iclass 15, count 2 2006.257.11:34:18.36#ibcon#about to read 5, iclass 15, count 2 2006.257.11:34:18.36#ibcon#read 5, iclass 15, count 2 2006.257.11:34:18.36#ibcon#about to read 6, iclass 15, count 2 2006.257.11:34:18.36#ibcon#read 6, iclass 15, count 2 2006.257.11:34:18.36#ibcon#end of sib2, iclass 15, count 2 2006.257.11:34:18.36#ibcon#*mode == 0, iclass 15, count 2 2006.257.11:34:18.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.11:34:18.36#ibcon#[27=AT02-05\r\n] 2006.257.11:34:18.36#ibcon#*before write, iclass 15, count 2 2006.257.11:34:18.36#ibcon#enter sib2, iclass 15, count 2 2006.257.11:34:18.36#ibcon#flushed, iclass 15, count 2 2006.257.11:34:18.36#ibcon#about to write, iclass 15, count 2 2006.257.11:34:18.36#ibcon#wrote, iclass 15, count 2 2006.257.11:34:18.36#ibcon#about to read 3, iclass 15, count 2 2006.257.11:34:18.39#ibcon#read 3, iclass 15, count 2 2006.257.11:34:18.39#ibcon#about to read 4, iclass 15, count 2 2006.257.11:34:18.39#ibcon#read 4, iclass 15, count 2 2006.257.11:34:18.39#ibcon#about to read 5, iclass 15, count 2 2006.257.11:34:18.39#ibcon#read 5, iclass 15, count 2 2006.257.11:34:18.39#ibcon#about to read 6, iclass 15, count 2 2006.257.11:34:18.39#ibcon#read 6, iclass 15, count 2 2006.257.11:34:18.39#ibcon#end of sib2, iclass 15, count 2 2006.257.11:34:18.39#ibcon#*after write, iclass 15, count 2 2006.257.11:34:18.39#ibcon#*before return 0, iclass 15, count 2 2006.257.11:34:18.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:18.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:34:18.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.11:34:18.39#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:18.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:18.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:18.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:18.51#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:34:18.51#ibcon#first serial, iclass 15, count 0 2006.257.11:34:18.51#ibcon#enter sib2, iclass 15, count 0 2006.257.11:34:18.51#ibcon#flushed, iclass 15, count 0 2006.257.11:34:18.51#ibcon#about to write, iclass 15, count 0 2006.257.11:34:18.51#ibcon#wrote, iclass 15, count 0 2006.257.11:34:18.51#ibcon#about to read 3, iclass 15, count 0 2006.257.11:34:18.53#ibcon#read 3, iclass 15, count 0 2006.257.11:34:18.53#ibcon#about to read 4, iclass 15, count 0 2006.257.11:34:18.54#ibcon#read 4, iclass 15, count 0 2006.257.11:34:18.54#ibcon#about to read 5, iclass 15, count 0 2006.257.11:34:18.54#ibcon#read 5, iclass 15, count 0 2006.257.11:34:18.54#ibcon#about to read 6, iclass 15, count 0 2006.257.11:34:18.54#ibcon#read 6, iclass 15, count 0 2006.257.11:34:18.54#ibcon#end of sib2, iclass 15, count 0 2006.257.11:34:18.54#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:34:18.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:34:18.54#ibcon#[27=USB\r\n] 2006.257.11:34:18.55#ibcon#*before write, iclass 15, count 0 2006.257.11:34:18.55#ibcon#enter sib2, iclass 15, count 0 2006.257.11:34:18.55#ibcon#flushed, iclass 15, count 0 2006.257.11:34:18.55#ibcon#about to write, iclass 15, count 0 2006.257.11:34:18.55#ibcon#wrote, iclass 15, count 0 2006.257.11:34:18.55#ibcon#about to read 3, iclass 15, count 0 2006.257.11:34:18.57#ibcon#read 3, iclass 15, count 0 2006.257.11:34:18.57#ibcon#about to read 4, iclass 15, count 0 2006.257.11:34:18.57#ibcon#read 4, iclass 15, count 0 2006.257.11:34:18.57#ibcon#about to read 5, iclass 15, count 0 2006.257.11:34:18.57#ibcon#read 5, iclass 15, count 0 2006.257.11:34:18.57#ibcon#about to read 6, iclass 15, count 0 2006.257.11:34:18.57#ibcon#read 6, iclass 15, count 0 2006.257.11:34:18.57#ibcon#end of sib2, iclass 15, count 0 2006.257.11:34:18.57#ibcon#*after write, iclass 15, count 0 2006.257.11:34:18.57#ibcon#*before return 0, iclass 15, count 0 2006.257.11:34:18.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:18.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:34:18.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:34:18.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:34:18.57$vck44/vblo=3,649.99 2006.257.11:34:18.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.11:34:18.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.11:34:18.57#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:18.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:18.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:18.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:18.57#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:34:18.57#ibcon#first serial, iclass 17, count 0 2006.257.11:34:18.57#ibcon#enter sib2, iclass 17, count 0 2006.257.11:34:18.57#ibcon#flushed, iclass 17, count 0 2006.257.11:34:18.57#ibcon#about to write, iclass 17, count 0 2006.257.11:34:18.57#ibcon#wrote, iclass 17, count 0 2006.257.11:34:18.57#ibcon#about to read 3, iclass 17, count 0 2006.257.11:34:18.59#ibcon#read 3, iclass 17, count 0 2006.257.11:34:18.59#ibcon#about to read 4, iclass 17, count 0 2006.257.11:34:18.59#ibcon#read 4, iclass 17, count 0 2006.257.11:34:18.59#ibcon#about to read 5, iclass 17, count 0 2006.257.11:34:18.59#ibcon#read 5, iclass 17, count 0 2006.257.11:34:18.59#ibcon#about to read 6, iclass 17, count 0 2006.257.11:34:18.59#ibcon#read 6, iclass 17, count 0 2006.257.11:34:18.59#ibcon#end of sib2, iclass 17, count 0 2006.257.11:34:18.59#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:34:18.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:34:18.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:34:18.59#ibcon#*before write, iclass 17, count 0 2006.257.11:34:18.59#ibcon#enter sib2, iclass 17, count 0 2006.257.11:34:18.59#ibcon#flushed, iclass 17, count 0 2006.257.11:34:18.59#ibcon#about to write, iclass 17, count 0 2006.257.11:34:18.59#ibcon#wrote, iclass 17, count 0 2006.257.11:34:18.59#ibcon#about to read 3, iclass 17, count 0 2006.257.11:34:18.63#ibcon#read 3, iclass 17, count 0 2006.257.11:34:18.63#ibcon#about to read 4, iclass 17, count 0 2006.257.11:34:18.63#ibcon#read 4, iclass 17, count 0 2006.257.11:34:18.63#ibcon#about to read 5, iclass 17, count 0 2006.257.11:34:18.63#ibcon#read 5, iclass 17, count 0 2006.257.11:34:18.63#ibcon#about to read 6, iclass 17, count 0 2006.257.11:34:18.63#ibcon#read 6, iclass 17, count 0 2006.257.11:34:18.63#ibcon#end of sib2, iclass 17, count 0 2006.257.11:34:18.63#ibcon#*after write, iclass 17, count 0 2006.257.11:34:18.63#ibcon#*before return 0, iclass 17, count 0 2006.257.11:34:18.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:18.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:34:18.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:34:18.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:34:18.63$vck44/vb=3,4 2006.257.11:34:18.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.11:34:18.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.11:34:18.63#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:18.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:18.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:18.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:18.69#ibcon#enter wrdev, iclass 19, count 2 2006.257.11:34:18.69#ibcon#first serial, iclass 19, count 2 2006.257.11:34:18.69#ibcon#enter sib2, iclass 19, count 2 2006.257.11:34:18.69#ibcon#flushed, iclass 19, count 2 2006.257.11:34:18.69#ibcon#about to write, iclass 19, count 2 2006.257.11:34:18.69#ibcon#wrote, iclass 19, count 2 2006.257.11:34:18.69#ibcon#about to read 3, iclass 19, count 2 2006.257.11:34:18.71#ibcon#read 3, iclass 19, count 2 2006.257.11:34:18.71#ibcon#about to read 4, iclass 19, count 2 2006.257.11:34:18.71#ibcon#read 4, iclass 19, count 2 2006.257.11:34:18.71#ibcon#about to read 5, iclass 19, count 2 2006.257.11:34:18.71#ibcon#read 5, iclass 19, count 2 2006.257.11:34:18.71#ibcon#about to read 6, iclass 19, count 2 2006.257.11:34:18.71#ibcon#read 6, iclass 19, count 2 2006.257.11:34:18.71#ibcon#end of sib2, iclass 19, count 2 2006.257.11:34:18.71#ibcon#*mode == 0, iclass 19, count 2 2006.257.11:34:18.71#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.11:34:18.71#ibcon#[27=AT03-04\r\n] 2006.257.11:34:18.71#ibcon#*before write, iclass 19, count 2 2006.257.11:34:18.71#ibcon#enter sib2, iclass 19, count 2 2006.257.11:34:18.71#ibcon#flushed, iclass 19, count 2 2006.257.11:34:18.71#ibcon#about to write, iclass 19, count 2 2006.257.11:34:18.71#ibcon#wrote, iclass 19, count 2 2006.257.11:34:18.71#ibcon#about to read 3, iclass 19, count 2 2006.257.11:34:18.74#ibcon#read 3, iclass 19, count 2 2006.257.11:34:18.74#ibcon#about to read 4, iclass 19, count 2 2006.257.11:34:18.74#ibcon#read 4, iclass 19, count 2 2006.257.11:34:18.74#ibcon#about to read 5, iclass 19, count 2 2006.257.11:34:18.74#ibcon#read 5, iclass 19, count 2 2006.257.11:34:18.74#ibcon#about to read 6, iclass 19, count 2 2006.257.11:34:18.74#ibcon#read 6, iclass 19, count 2 2006.257.11:34:18.74#ibcon#end of sib2, iclass 19, count 2 2006.257.11:34:18.74#ibcon#*after write, iclass 19, count 2 2006.257.11:34:18.74#ibcon#*before return 0, iclass 19, count 2 2006.257.11:34:18.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:18.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:34:18.74#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.11:34:18.74#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:18.74#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:18.86#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:18.86#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:18.86#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:34:18.86#ibcon#first serial, iclass 19, count 0 2006.257.11:34:18.86#ibcon#enter sib2, iclass 19, count 0 2006.257.11:34:18.86#ibcon#flushed, iclass 19, count 0 2006.257.11:34:18.86#ibcon#about to write, iclass 19, count 0 2006.257.11:34:18.86#ibcon#wrote, iclass 19, count 0 2006.257.11:34:18.86#ibcon#about to read 3, iclass 19, count 0 2006.257.11:34:18.88#ibcon#read 3, iclass 19, count 0 2006.257.11:34:18.88#ibcon#about to read 4, iclass 19, count 0 2006.257.11:34:18.88#ibcon#read 4, iclass 19, count 0 2006.257.11:34:18.88#ibcon#about to read 5, iclass 19, count 0 2006.257.11:34:18.88#ibcon#read 5, iclass 19, count 0 2006.257.11:34:18.88#ibcon#about to read 6, iclass 19, count 0 2006.257.11:34:18.88#ibcon#read 6, iclass 19, count 0 2006.257.11:34:18.88#ibcon#end of sib2, iclass 19, count 0 2006.257.11:34:18.88#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:34:18.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:34:18.88#ibcon#[27=USB\r\n] 2006.257.11:34:18.88#ibcon#*before write, iclass 19, count 0 2006.257.11:34:18.88#ibcon#enter sib2, iclass 19, count 0 2006.257.11:34:18.88#ibcon#flushed, iclass 19, count 0 2006.257.11:34:18.88#ibcon#about to write, iclass 19, count 0 2006.257.11:34:18.88#ibcon#wrote, iclass 19, count 0 2006.257.11:34:18.88#ibcon#about to read 3, iclass 19, count 0 2006.257.11:34:18.91#ibcon#read 3, iclass 19, count 0 2006.257.11:34:18.91#ibcon#about to read 4, iclass 19, count 0 2006.257.11:34:18.91#ibcon#read 4, iclass 19, count 0 2006.257.11:34:18.91#ibcon#about to read 5, iclass 19, count 0 2006.257.11:34:18.91#ibcon#read 5, iclass 19, count 0 2006.257.11:34:18.91#ibcon#about to read 6, iclass 19, count 0 2006.257.11:34:18.91#ibcon#read 6, iclass 19, count 0 2006.257.11:34:18.91#ibcon#end of sib2, iclass 19, count 0 2006.257.11:34:18.91#ibcon#*after write, iclass 19, count 0 2006.257.11:34:18.91#ibcon#*before return 0, iclass 19, count 0 2006.257.11:34:18.91#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:18.91#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:34:18.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:34:18.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:34:18.91$vck44/vblo=4,679.99 2006.257.11:34:18.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.11:34:18.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.11:34:18.91#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:18.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:18.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:18.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:18.91#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:34:18.91#ibcon#first serial, iclass 21, count 0 2006.257.11:34:18.91#ibcon#enter sib2, iclass 21, count 0 2006.257.11:34:18.91#ibcon#flushed, iclass 21, count 0 2006.257.11:34:18.91#ibcon#about to write, iclass 21, count 0 2006.257.11:34:18.91#ibcon#wrote, iclass 21, count 0 2006.257.11:34:18.91#ibcon#about to read 3, iclass 21, count 0 2006.257.11:34:18.93#ibcon#read 3, iclass 21, count 0 2006.257.11:34:18.93#ibcon#about to read 4, iclass 21, count 0 2006.257.11:34:18.93#ibcon#read 4, iclass 21, count 0 2006.257.11:34:18.93#ibcon#about to read 5, iclass 21, count 0 2006.257.11:34:18.93#ibcon#read 5, iclass 21, count 0 2006.257.11:34:18.93#ibcon#about to read 6, iclass 21, count 0 2006.257.11:34:18.93#ibcon#read 6, iclass 21, count 0 2006.257.11:34:18.93#ibcon#end of sib2, iclass 21, count 0 2006.257.11:34:18.93#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:34:18.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:34:18.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:34:18.93#ibcon#*before write, iclass 21, count 0 2006.257.11:34:18.93#ibcon#enter sib2, iclass 21, count 0 2006.257.11:34:18.93#ibcon#flushed, iclass 21, count 0 2006.257.11:34:18.93#ibcon#about to write, iclass 21, count 0 2006.257.11:34:18.93#ibcon#wrote, iclass 21, count 0 2006.257.11:34:18.93#ibcon#about to read 3, iclass 21, count 0 2006.257.11:34:18.97#ibcon#read 3, iclass 21, count 0 2006.257.11:34:18.97#ibcon#about to read 4, iclass 21, count 0 2006.257.11:34:18.97#ibcon#read 4, iclass 21, count 0 2006.257.11:34:18.97#ibcon#about to read 5, iclass 21, count 0 2006.257.11:34:18.97#ibcon#read 5, iclass 21, count 0 2006.257.11:34:18.97#ibcon#about to read 6, iclass 21, count 0 2006.257.11:34:18.97#ibcon#read 6, iclass 21, count 0 2006.257.11:34:18.97#ibcon#end of sib2, iclass 21, count 0 2006.257.11:34:18.97#ibcon#*after write, iclass 21, count 0 2006.257.11:34:18.97#ibcon#*before return 0, iclass 21, count 0 2006.257.11:34:18.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:18.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:34:18.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:34:18.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:34:18.97$vck44/vb=4,5 2006.257.11:34:18.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.11:34:18.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.11:34:18.97#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:18.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:19.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:19.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:19.03#ibcon#enter wrdev, iclass 23, count 2 2006.257.11:34:19.03#ibcon#first serial, iclass 23, count 2 2006.257.11:34:19.03#ibcon#enter sib2, iclass 23, count 2 2006.257.11:34:19.03#ibcon#flushed, iclass 23, count 2 2006.257.11:34:19.03#ibcon#about to write, iclass 23, count 2 2006.257.11:34:19.03#ibcon#wrote, iclass 23, count 2 2006.257.11:34:19.03#ibcon#about to read 3, iclass 23, count 2 2006.257.11:34:19.05#ibcon#read 3, iclass 23, count 2 2006.257.11:34:19.05#ibcon#about to read 4, iclass 23, count 2 2006.257.11:34:19.05#ibcon#read 4, iclass 23, count 2 2006.257.11:34:19.05#ibcon#about to read 5, iclass 23, count 2 2006.257.11:34:19.05#ibcon#read 5, iclass 23, count 2 2006.257.11:34:19.05#ibcon#about to read 6, iclass 23, count 2 2006.257.11:34:19.05#ibcon#read 6, iclass 23, count 2 2006.257.11:34:19.05#ibcon#end of sib2, iclass 23, count 2 2006.257.11:34:19.05#ibcon#*mode == 0, iclass 23, count 2 2006.257.11:34:19.05#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.11:34:19.05#ibcon#[27=AT04-05\r\n] 2006.257.11:34:19.05#ibcon#*before write, iclass 23, count 2 2006.257.11:34:19.05#ibcon#enter sib2, iclass 23, count 2 2006.257.11:34:19.05#ibcon#flushed, iclass 23, count 2 2006.257.11:34:19.05#ibcon#about to write, iclass 23, count 2 2006.257.11:34:19.05#ibcon#wrote, iclass 23, count 2 2006.257.11:34:19.05#ibcon#about to read 3, iclass 23, count 2 2006.257.11:34:19.08#ibcon#read 3, iclass 23, count 2 2006.257.11:34:19.08#ibcon#about to read 4, iclass 23, count 2 2006.257.11:34:19.08#ibcon#read 4, iclass 23, count 2 2006.257.11:34:19.08#ibcon#about to read 5, iclass 23, count 2 2006.257.11:34:19.08#ibcon#read 5, iclass 23, count 2 2006.257.11:34:19.08#ibcon#about to read 6, iclass 23, count 2 2006.257.11:34:19.08#ibcon#read 6, iclass 23, count 2 2006.257.11:34:19.08#ibcon#end of sib2, iclass 23, count 2 2006.257.11:34:19.08#ibcon#*after write, iclass 23, count 2 2006.257.11:34:19.08#ibcon#*before return 0, iclass 23, count 2 2006.257.11:34:19.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:19.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:34:19.08#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.11:34:19.08#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:19.08#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:19.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:19.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:19.20#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:34:19.20#ibcon#first serial, iclass 23, count 0 2006.257.11:34:19.20#ibcon#enter sib2, iclass 23, count 0 2006.257.11:34:19.20#ibcon#flushed, iclass 23, count 0 2006.257.11:34:19.20#ibcon#about to write, iclass 23, count 0 2006.257.11:34:19.20#ibcon#wrote, iclass 23, count 0 2006.257.11:34:19.20#ibcon#about to read 3, iclass 23, count 0 2006.257.11:34:19.22#ibcon#read 3, iclass 23, count 0 2006.257.11:34:19.22#ibcon#about to read 4, iclass 23, count 0 2006.257.11:34:19.22#ibcon#read 4, iclass 23, count 0 2006.257.11:34:19.22#ibcon#about to read 5, iclass 23, count 0 2006.257.11:34:19.22#ibcon#read 5, iclass 23, count 0 2006.257.11:34:19.22#ibcon#about to read 6, iclass 23, count 0 2006.257.11:34:19.22#ibcon#read 6, iclass 23, count 0 2006.257.11:34:19.22#ibcon#end of sib2, iclass 23, count 0 2006.257.11:34:19.22#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:34:19.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:34:19.22#ibcon#[27=USB\r\n] 2006.257.11:34:19.22#ibcon#*before write, iclass 23, count 0 2006.257.11:34:19.22#ibcon#enter sib2, iclass 23, count 0 2006.257.11:34:19.22#ibcon#flushed, iclass 23, count 0 2006.257.11:34:19.22#ibcon#about to write, iclass 23, count 0 2006.257.11:34:19.22#ibcon#wrote, iclass 23, count 0 2006.257.11:34:19.22#ibcon#about to read 3, iclass 23, count 0 2006.257.11:34:19.25#ibcon#read 3, iclass 23, count 0 2006.257.11:34:19.25#ibcon#about to read 4, iclass 23, count 0 2006.257.11:34:19.25#ibcon#read 4, iclass 23, count 0 2006.257.11:34:19.25#ibcon#about to read 5, iclass 23, count 0 2006.257.11:34:19.25#ibcon#read 5, iclass 23, count 0 2006.257.11:34:19.25#ibcon#about to read 6, iclass 23, count 0 2006.257.11:34:19.25#ibcon#read 6, iclass 23, count 0 2006.257.11:34:19.25#ibcon#end of sib2, iclass 23, count 0 2006.257.11:34:19.25#ibcon#*after write, iclass 23, count 0 2006.257.11:34:19.25#ibcon#*before return 0, iclass 23, count 0 2006.257.11:34:19.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:19.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:34:19.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:34:19.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:34:19.25$vck44/vblo=5,709.99 2006.257.11:34:19.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.11:34:19.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.11:34:19.25#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:19.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:19.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:19.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:19.25#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:34:19.25#ibcon#first serial, iclass 25, count 0 2006.257.11:34:19.25#ibcon#enter sib2, iclass 25, count 0 2006.257.11:34:19.25#ibcon#flushed, iclass 25, count 0 2006.257.11:34:19.25#ibcon#about to write, iclass 25, count 0 2006.257.11:34:19.25#ibcon#wrote, iclass 25, count 0 2006.257.11:34:19.25#ibcon#about to read 3, iclass 25, count 0 2006.257.11:34:19.27#ibcon#read 3, iclass 25, count 0 2006.257.11:34:19.27#ibcon#about to read 4, iclass 25, count 0 2006.257.11:34:19.27#ibcon#read 4, iclass 25, count 0 2006.257.11:34:19.27#ibcon#about to read 5, iclass 25, count 0 2006.257.11:34:19.27#ibcon#read 5, iclass 25, count 0 2006.257.11:34:19.27#ibcon#about to read 6, iclass 25, count 0 2006.257.11:34:19.27#ibcon#read 6, iclass 25, count 0 2006.257.11:34:19.27#ibcon#end of sib2, iclass 25, count 0 2006.257.11:34:19.27#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:34:19.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:34:19.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:34:19.27#ibcon#*before write, iclass 25, count 0 2006.257.11:34:19.27#ibcon#enter sib2, iclass 25, count 0 2006.257.11:34:19.27#ibcon#flushed, iclass 25, count 0 2006.257.11:34:19.27#ibcon#about to write, iclass 25, count 0 2006.257.11:34:19.27#ibcon#wrote, iclass 25, count 0 2006.257.11:34:19.27#ibcon#about to read 3, iclass 25, count 0 2006.257.11:34:19.31#ibcon#read 3, iclass 25, count 0 2006.257.11:34:19.31#ibcon#about to read 4, iclass 25, count 0 2006.257.11:34:19.31#ibcon#read 4, iclass 25, count 0 2006.257.11:34:19.31#ibcon#about to read 5, iclass 25, count 0 2006.257.11:34:19.31#ibcon#read 5, iclass 25, count 0 2006.257.11:34:19.31#ibcon#about to read 6, iclass 25, count 0 2006.257.11:34:19.31#ibcon#read 6, iclass 25, count 0 2006.257.11:34:19.31#ibcon#end of sib2, iclass 25, count 0 2006.257.11:34:19.31#ibcon#*after write, iclass 25, count 0 2006.257.11:34:19.31#ibcon#*before return 0, iclass 25, count 0 2006.257.11:34:19.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:19.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:34:19.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:34:19.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:34:19.31$vck44/vb=5,4 2006.257.11:34:19.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.11:34:19.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.11:34:19.31#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:19.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:19.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:19.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:19.37#ibcon#enter wrdev, iclass 27, count 2 2006.257.11:34:19.37#ibcon#first serial, iclass 27, count 2 2006.257.11:34:19.37#ibcon#enter sib2, iclass 27, count 2 2006.257.11:34:19.37#ibcon#flushed, iclass 27, count 2 2006.257.11:34:19.37#ibcon#about to write, iclass 27, count 2 2006.257.11:34:19.37#ibcon#wrote, iclass 27, count 2 2006.257.11:34:19.37#ibcon#about to read 3, iclass 27, count 2 2006.257.11:34:19.39#ibcon#read 3, iclass 27, count 2 2006.257.11:34:19.39#ibcon#about to read 4, iclass 27, count 2 2006.257.11:34:19.39#ibcon#read 4, iclass 27, count 2 2006.257.11:34:19.39#ibcon#about to read 5, iclass 27, count 2 2006.257.11:34:19.39#ibcon#read 5, iclass 27, count 2 2006.257.11:34:19.39#ibcon#about to read 6, iclass 27, count 2 2006.257.11:34:19.39#ibcon#read 6, iclass 27, count 2 2006.257.11:34:19.39#ibcon#end of sib2, iclass 27, count 2 2006.257.11:34:19.39#ibcon#*mode == 0, iclass 27, count 2 2006.257.11:34:19.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.11:34:19.39#ibcon#[27=AT05-04\r\n] 2006.257.11:34:19.39#ibcon#*before write, iclass 27, count 2 2006.257.11:34:19.39#ibcon#enter sib2, iclass 27, count 2 2006.257.11:34:19.39#ibcon#flushed, iclass 27, count 2 2006.257.11:34:19.39#ibcon#about to write, iclass 27, count 2 2006.257.11:34:19.39#ibcon#wrote, iclass 27, count 2 2006.257.11:34:19.39#ibcon#about to read 3, iclass 27, count 2 2006.257.11:34:19.42#ibcon#read 3, iclass 27, count 2 2006.257.11:34:19.42#ibcon#about to read 4, iclass 27, count 2 2006.257.11:34:19.42#ibcon#read 4, iclass 27, count 2 2006.257.11:34:19.42#ibcon#about to read 5, iclass 27, count 2 2006.257.11:34:19.42#ibcon#read 5, iclass 27, count 2 2006.257.11:34:19.42#ibcon#about to read 6, iclass 27, count 2 2006.257.11:34:19.42#ibcon#read 6, iclass 27, count 2 2006.257.11:34:19.42#ibcon#end of sib2, iclass 27, count 2 2006.257.11:34:19.42#ibcon#*after write, iclass 27, count 2 2006.257.11:34:19.42#ibcon#*before return 0, iclass 27, count 2 2006.257.11:34:19.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:19.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:34:19.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.11:34:19.42#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:19.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:19.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:19.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:19.54#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:34:19.54#ibcon#first serial, iclass 27, count 0 2006.257.11:34:19.54#ibcon#enter sib2, iclass 27, count 0 2006.257.11:34:19.54#ibcon#flushed, iclass 27, count 0 2006.257.11:34:19.54#ibcon#about to write, iclass 27, count 0 2006.257.11:34:19.54#ibcon#wrote, iclass 27, count 0 2006.257.11:34:19.54#ibcon#about to read 3, iclass 27, count 0 2006.257.11:34:19.56#ibcon#read 3, iclass 27, count 0 2006.257.11:34:19.56#ibcon#about to read 4, iclass 27, count 0 2006.257.11:34:19.56#ibcon#read 4, iclass 27, count 0 2006.257.11:34:19.56#ibcon#about to read 5, iclass 27, count 0 2006.257.11:34:19.56#ibcon#read 5, iclass 27, count 0 2006.257.11:34:19.56#ibcon#about to read 6, iclass 27, count 0 2006.257.11:34:19.56#ibcon#read 6, iclass 27, count 0 2006.257.11:34:19.56#ibcon#end of sib2, iclass 27, count 0 2006.257.11:34:19.56#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:34:19.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:34:19.56#ibcon#[27=USB\r\n] 2006.257.11:34:19.56#ibcon#*before write, iclass 27, count 0 2006.257.11:34:19.56#ibcon#enter sib2, iclass 27, count 0 2006.257.11:34:19.56#ibcon#flushed, iclass 27, count 0 2006.257.11:34:19.56#ibcon#about to write, iclass 27, count 0 2006.257.11:34:19.56#ibcon#wrote, iclass 27, count 0 2006.257.11:34:19.56#ibcon#about to read 3, iclass 27, count 0 2006.257.11:34:19.59#ibcon#read 3, iclass 27, count 0 2006.257.11:34:19.59#ibcon#about to read 4, iclass 27, count 0 2006.257.11:34:19.59#ibcon#read 4, iclass 27, count 0 2006.257.11:34:19.59#ibcon#about to read 5, iclass 27, count 0 2006.257.11:34:19.59#ibcon#read 5, iclass 27, count 0 2006.257.11:34:19.59#ibcon#about to read 6, iclass 27, count 0 2006.257.11:34:19.59#ibcon#read 6, iclass 27, count 0 2006.257.11:34:19.59#ibcon#end of sib2, iclass 27, count 0 2006.257.11:34:19.59#ibcon#*after write, iclass 27, count 0 2006.257.11:34:19.59#ibcon#*before return 0, iclass 27, count 0 2006.257.11:34:19.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:19.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:34:19.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:34:19.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:34:19.59$vck44/vblo=6,719.99 2006.257.11:34:19.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.11:34:19.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.11:34:19.59#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:19.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:19.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:19.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:19.59#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:34:19.59#ibcon#first serial, iclass 29, count 0 2006.257.11:34:19.59#ibcon#enter sib2, iclass 29, count 0 2006.257.11:34:19.59#ibcon#flushed, iclass 29, count 0 2006.257.11:34:19.59#ibcon#about to write, iclass 29, count 0 2006.257.11:34:19.59#ibcon#wrote, iclass 29, count 0 2006.257.11:34:19.59#ibcon#about to read 3, iclass 29, count 0 2006.257.11:34:19.61#ibcon#read 3, iclass 29, count 0 2006.257.11:34:19.61#ibcon#about to read 4, iclass 29, count 0 2006.257.11:34:19.61#ibcon#read 4, iclass 29, count 0 2006.257.11:34:19.61#ibcon#about to read 5, iclass 29, count 0 2006.257.11:34:19.61#ibcon#read 5, iclass 29, count 0 2006.257.11:34:19.61#ibcon#about to read 6, iclass 29, count 0 2006.257.11:34:19.61#ibcon#read 6, iclass 29, count 0 2006.257.11:34:19.61#ibcon#end of sib2, iclass 29, count 0 2006.257.11:34:19.61#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:34:19.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:34:19.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:34:19.61#ibcon#*before write, iclass 29, count 0 2006.257.11:34:19.61#ibcon#enter sib2, iclass 29, count 0 2006.257.11:34:19.61#ibcon#flushed, iclass 29, count 0 2006.257.11:34:19.61#ibcon#about to write, iclass 29, count 0 2006.257.11:34:19.61#ibcon#wrote, iclass 29, count 0 2006.257.11:34:19.61#ibcon#about to read 3, iclass 29, count 0 2006.257.11:34:19.65#ibcon#read 3, iclass 29, count 0 2006.257.11:34:19.65#ibcon#about to read 4, iclass 29, count 0 2006.257.11:34:19.65#ibcon#read 4, iclass 29, count 0 2006.257.11:34:19.65#ibcon#about to read 5, iclass 29, count 0 2006.257.11:34:19.65#ibcon#read 5, iclass 29, count 0 2006.257.11:34:19.65#ibcon#about to read 6, iclass 29, count 0 2006.257.11:34:19.65#ibcon#read 6, iclass 29, count 0 2006.257.11:34:19.65#ibcon#end of sib2, iclass 29, count 0 2006.257.11:34:19.65#ibcon#*after write, iclass 29, count 0 2006.257.11:34:19.65#ibcon#*before return 0, iclass 29, count 0 2006.257.11:34:19.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:19.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:34:19.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:34:19.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:34:19.65$vck44/vb=6,4 2006.257.11:34:19.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.11:34:19.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.11:34:19.65#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:19.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:19.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:19.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:19.71#ibcon#enter wrdev, iclass 31, count 2 2006.257.11:34:19.71#ibcon#first serial, iclass 31, count 2 2006.257.11:34:19.71#ibcon#enter sib2, iclass 31, count 2 2006.257.11:34:19.71#ibcon#flushed, iclass 31, count 2 2006.257.11:34:19.71#ibcon#about to write, iclass 31, count 2 2006.257.11:34:19.71#ibcon#wrote, iclass 31, count 2 2006.257.11:34:19.71#ibcon#about to read 3, iclass 31, count 2 2006.257.11:34:19.73#ibcon#read 3, iclass 31, count 2 2006.257.11:34:19.73#ibcon#about to read 4, iclass 31, count 2 2006.257.11:34:19.73#ibcon#read 4, iclass 31, count 2 2006.257.11:34:19.73#ibcon#about to read 5, iclass 31, count 2 2006.257.11:34:19.73#ibcon#read 5, iclass 31, count 2 2006.257.11:34:19.73#ibcon#about to read 6, iclass 31, count 2 2006.257.11:34:19.73#ibcon#read 6, iclass 31, count 2 2006.257.11:34:19.73#ibcon#end of sib2, iclass 31, count 2 2006.257.11:34:19.73#ibcon#*mode == 0, iclass 31, count 2 2006.257.11:34:19.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.11:34:19.73#ibcon#[27=AT06-04\r\n] 2006.257.11:34:19.73#ibcon#*before write, iclass 31, count 2 2006.257.11:34:19.73#ibcon#enter sib2, iclass 31, count 2 2006.257.11:34:19.73#ibcon#flushed, iclass 31, count 2 2006.257.11:34:19.73#ibcon#about to write, iclass 31, count 2 2006.257.11:34:19.73#ibcon#wrote, iclass 31, count 2 2006.257.11:34:19.73#ibcon#about to read 3, iclass 31, count 2 2006.257.11:34:19.76#ibcon#read 3, iclass 31, count 2 2006.257.11:34:19.76#ibcon#about to read 4, iclass 31, count 2 2006.257.11:34:19.76#ibcon#read 4, iclass 31, count 2 2006.257.11:34:19.76#ibcon#about to read 5, iclass 31, count 2 2006.257.11:34:19.76#ibcon#read 5, iclass 31, count 2 2006.257.11:34:19.76#ibcon#about to read 6, iclass 31, count 2 2006.257.11:34:19.76#ibcon#read 6, iclass 31, count 2 2006.257.11:34:19.76#ibcon#end of sib2, iclass 31, count 2 2006.257.11:34:19.76#ibcon#*after write, iclass 31, count 2 2006.257.11:34:19.76#ibcon#*before return 0, iclass 31, count 2 2006.257.11:34:19.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:19.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:34:19.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.11:34:19.76#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:19.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:19.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:19.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:19.88#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:34:19.88#ibcon#first serial, iclass 31, count 0 2006.257.11:34:19.88#ibcon#enter sib2, iclass 31, count 0 2006.257.11:34:19.88#ibcon#flushed, iclass 31, count 0 2006.257.11:34:19.88#ibcon#about to write, iclass 31, count 0 2006.257.11:34:19.88#ibcon#wrote, iclass 31, count 0 2006.257.11:34:19.88#ibcon#about to read 3, iclass 31, count 0 2006.257.11:34:19.90#ibcon#read 3, iclass 31, count 0 2006.257.11:34:19.90#ibcon#about to read 4, iclass 31, count 0 2006.257.11:34:19.90#ibcon#read 4, iclass 31, count 0 2006.257.11:34:19.90#ibcon#about to read 5, iclass 31, count 0 2006.257.11:34:19.90#ibcon#read 5, iclass 31, count 0 2006.257.11:34:19.90#ibcon#about to read 6, iclass 31, count 0 2006.257.11:34:19.90#ibcon#read 6, iclass 31, count 0 2006.257.11:34:19.90#ibcon#end of sib2, iclass 31, count 0 2006.257.11:34:19.90#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:34:19.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:34:19.90#ibcon#[27=USB\r\n] 2006.257.11:34:19.90#ibcon#*before write, iclass 31, count 0 2006.257.11:34:19.90#ibcon#enter sib2, iclass 31, count 0 2006.257.11:34:19.90#ibcon#flushed, iclass 31, count 0 2006.257.11:34:19.90#ibcon#about to write, iclass 31, count 0 2006.257.11:34:19.90#ibcon#wrote, iclass 31, count 0 2006.257.11:34:19.90#ibcon#about to read 3, iclass 31, count 0 2006.257.11:34:19.93#ibcon#read 3, iclass 31, count 0 2006.257.11:34:19.93#ibcon#about to read 4, iclass 31, count 0 2006.257.11:34:19.93#ibcon#read 4, iclass 31, count 0 2006.257.11:34:19.93#ibcon#about to read 5, iclass 31, count 0 2006.257.11:34:19.93#ibcon#read 5, iclass 31, count 0 2006.257.11:34:19.93#ibcon#about to read 6, iclass 31, count 0 2006.257.11:34:19.93#ibcon#read 6, iclass 31, count 0 2006.257.11:34:19.93#ibcon#end of sib2, iclass 31, count 0 2006.257.11:34:19.93#ibcon#*after write, iclass 31, count 0 2006.257.11:34:19.93#ibcon#*before return 0, iclass 31, count 0 2006.257.11:34:19.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:19.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:34:19.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:34:19.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:34:19.93$vck44/vblo=7,734.99 2006.257.11:34:19.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.11:34:19.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.11:34:19.93#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:19.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:19.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:19.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:19.93#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:34:19.93#ibcon#first serial, iclass 33, count 0 2006.257.11:34:19.93#ibcon#enter sib2, iclass 33, count 0 2006.257.11:34:19.93#ibcon#flushed, iclass 33, count 0 2006.257.11:34:19.93#ibcon#about to write, iclass 33, count 0 2006.257.11:34:19.93#ibcon#wrote, iclass 33, count 0 2006.257.11:34:19.93#ibcon#about to read 3, iclass 33, count 0 2006.257.11:34:19.95#ibcon#read 3, iclass 33, count 0 2006.257.11:34:19.95#ibcon#about to read 4, iclass 33, count 0 2006.257.11:34:19.95#ibcon#read 4, iclass 33, count 0 2006.257.11:34:19.95#ibcon#about to read 5, iclass 33, count 0 2006.257.11:34:19.95#ibcon#read 5, iclass 33, count 0 2006.257.11:34:19.95#ibcon#about to read 6, iclass 33, count 0 2006.257.11:34:19.95#ibcon#read 6, iclass 33, count 0 2006.257.11:34:19.95#ibcon#end of sib2, iclass 33, count 0 2006.257.11:34:19.95#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:34:19.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:34:19.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:34:19.95#ibcon#*before write, iclass 33, count 0 2006.257.11:34:19.95#ibcon#enter sib2, iclass 33, count 0 2006.257.11:34:19.95#ibcon#flushed, iclass 33, count 0 2006.257.11:34:19.95#ibcon#about to write, iclass 33, count 0 2006.257.11:34:19.95#ibcon#wrote, iclass 33, count 0 2006.257.11:34:19.95#ibcon#about to read 3, iclass 33, count 0 2006.257.11:34:19.99#ibcon#read 3, iclass 33, count 0 2006.257.11:34:19.99#ibcon#about to read 4, iclass 33, count 0 2006.257.11:34:19.99#ibcon#read 4, iclass 33, count 0 2006.257.11:34:19.99#ibcon#about to read 5, iclass 33, count 0 2006.257.11:34:19.99#ibcon#read 5, iclass 33, count 0 2006.257.11:34:19.99#ibcon#about to read 6, iclass 33, count 0 2006.257.11:34:19.99#ibcon#read 6, iclass 33, count 0 2006.257.11:34:19.99#ibcon#end of sib2, iclass 33, count 0 2006.257.11:34:19.99#ibcon#*after write, iclass 33, count 0 2006.257.11:34:19.99#ibcon#*before return 0, iclass 33, count 0 2006.257.11:34:19.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:19.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:34:19.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:34:19.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:34:19.99$vck44/vb=7,4 2006.257.11:34:19.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.11:34:19.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.11:34:19.99#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:19.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:20.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:20.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:20.05#ibcon#enter wrdev, iclass 35, count 2 2006.257.11:34:20.05#ibcon#first serial, iclass 35, count 2 2006.257.11:34:20.05#ibcon#enter sib2, iclass 35, count 2 2006.257.11:34:20.05#ibcon#flushed, iclass 35, count 2 2006.257.11:34:20.05#ibcon#about to write, iclass 35, count 2 2006.257.11:34:20.05#ibcon#wrote, iclass 35, count 2 2006.257.11:34:20.05#ibcon#about to read 3, iclass 35, count 2 2006.257.11:34:20.07#ibcon#read 3, iclass 35, count 2 2006.257.11:34:20.07#ibcon#about to read 4, iclass 35, count 2 2006.257.11:34:20.07#ibcon#read 4, iclass 35, count 2 2006.257.11:34:20.07#ibcon#about to read 5, iclass 35, count 2 2006.257.11:34:20.07#ibcon#read 5, iclass 35, count 2 2006.257.11:34:20.07#ibcon#about to read 6, iclass 35, count 2 2006.257.11:34:20.07#ibcon#read 6, iclass 35, count 2 2006.257.11:34:20.07#ibcon#end of sib2, iclass 35, count 2 2006.257.11:34:20.07#ibcon#*mode == 0, iclass 35, count 2 2006.257.11:34:20.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.11:34:20.07#ibcon#[27=AT07-04\r\n] 2006.257.11:34:20.07#ibcon#*before write, iclass 35, count 2 2006.257.11:34:20.07#ibcon#enter sib2, iclass 35, count 2 2006.257.11:34:20.07#ibcon#flushed, iclass 35, count 2 2006.257.11:34:20.07#ibcon#about to write, iclass 35, count 2 2006.257.11:34:20.07#ibcon#wrote, iclass 35, count 2 2006.257.11:34:20.07#ibcon#about to read 3, iclass 35, count 2 2006.257.11:34:20.10#ibcon#read 3, iclass 35, count 2 2006.257.11:34:20.10#ibcon#about to read 4, iclass 35, count 2 2006.257.11:34:20.10#ibcon#read 4, iclass 35, count 2 2006.257.11:34:20.10#ibcon#about to read 5, iclass 35, count 2 2006.257.11:34:20.10#ibcon#read 5, iclass 35, count 2 2006.257.11:34:20.10#ibcon#about to read 6, iclass 35, count 2 2006.257.11:34:20.10#ibcon#read 6, iclass 35, count 2 2006.257.11:34:20.10#ibcon#end of sib2, iclass 35, count 2 2006.257.11:34:20.10#ibcon#*after write, iclass 35, count 2 2006.257.11:34:20.10#ibcon#*before return 0, iclass 35, count 2 2006.257.11:34:20.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:20.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:34:20.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.11:34:20.10#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:20.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:20.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:20.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:20.22#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:34:20.22#ibcon#first serial, iclass 35, count 0 2006.257.11:34:20.22#ibcon#enter sib2, iclass 35, count 0 2006.257.11:34:20.22#ibcon#flushed, iclass 35, count 0 2006.257.11:34:20.22#ibcon#about to write, iclass 35, count 0 2006.257.11:34:20.22#ibcon#wrote, iclass 35, count 0 2006.257.11:34:20.22#ibcon#about to read 3, iclass 35, count 0 2006.257.11:34:20.24#ibcon#read 3, iclass 35, count 0 2006.257.11:34:20.24#ibcon#about to read 4, iclass 35, count 0 2006.257.11:34:20.24#ibcon#read 4, iclass 35, count 0 2006.257.11:34:20.24#ibcon#about to read 5, iclass 35, count 0 2006.257.11:34:20.24#ibcon#read 5, iclass 35, count 0 2006.257.11:34:20.24#ibcon#about to read 6, iclass 35, count 0 2006.257.11:34:20.24#ibcon#read 6, iclass 35, count 0 2006.257.11:34:20.24#ibcon#end of sib2, iclass 35, count 0 2006.257.11:34:20.24#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:34:20.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:34:20.24#ibcon#[27=USB\r\n] 2006.257.11:34:20.24#ibcon#*before write, iclass 35, count 0 2006.257.11:34:20.24#ibcon#enter sib2, iclass 35, count 0 2006.257.11:34:20.24#ibcon#flushed, iclass 35, count 0 2006.257.11:34:20.24#ibcon#about to write, iclass 35, count 0 2006.257.11:34:20.24#ibcon#wrote, iclass 35, count 0 2006.257.11:34:20.24#ibcon#about to read 3, iclass 35, count 0 2006.257.11:34:20.27#ibcon#read 3, iclass 35, count 0 2006.257.11:34:20.27#ibcon#about to read 4, iclass 35, count 0 2006.257.11:34:20.27#ibcon#read 4, iclass 35, count 0 2006.257.11:34:20.27#ibcon#about to read 5, iclass 35, count 0 2006.257.11:34:20.27#ibcon#read 5, iclass 35, count 0 2006.257.11:34:20.27#ibcon#about to read 6, iclass 35, count 0 2006.257.11:34:20.27#ibcon#read 6, iclass 35, count 0 2006.257.11:34:20.27#ibcon#end of sib2, iclass 35, count 0 2006.257.11:34:20.27#ibcon#*after write, iclass 35, count 0 2006.257.11:34:20.27#ibcon#*before return 0, iclass 35, count 0 2006.257.11:34:20.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:20.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:34:20.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:34:20.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:34:20.27$vck44/vblo=8,744.99 2006.257.11:34:20.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.11:34:20.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.11:34:20.27#ibcon#ireg 17 cls_cnt 0 2006.257.11:34:20.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:20.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:20.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:20.27#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:34:20.27#ibcon#first serial, iclass 37, count 0 2006.257.11:34:20.27#ibcon#enter sib2, iclass 37, count 0 2006.257.11:34:20.27#ibcon#flushed, iclass 37, count 0 2006.257.11:34:20.27#ibcon#about to write, iclass 37, count 0 2006.257.11:34:20.27#ibcon#wrote, iclass 37, count 0 2006.257.11:34:20.27#ibcon#about to read 3, iclass 37, count 0 2006.257.11:34:20.29#ibcon#read 3, iclass 37, count 0 2006.257.11:34:20.29#ibcon#about to read 4, iclass 37, count 0 2006.257.11:34:20.29#ibcon#read 4, iclass 37, count 0 2006.257.11:34:20.29#ibcon#about to read 5, iclass 37, count 0 2006.257.11:34:20.29#ibcon#read 5, iclass 37, count 0 2006.257.11:34:20.29#ibcon#about to read 6, iclass 37, count 0 2006.257.11:34:20.29#ibcon#read 6, iclass 37, count 0 2006.257.11:34:20.29#ibcon#end of sib2, iclass 37, count 0 2006.257.11:34:20.29#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:34:20.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:34:20.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:34:20.29#ibcon#*before write, iclass 37, count 0 2006.257.11:34:20.29#ibcon#enter sib2, iclass 37, count 0 2006.257.11:34:20.29#ibcon#flushed, iclass 37, count 0 2006.257.11:34:20.29#ibcon#about to write, iclass 37, count 0 2006.257.11:34:20.29#ibcon#wrote, iclass 37, count 0 2006.257.11:34:20.29#ibcon#about to read 3, iclass 37, count 0 2006.257.11:34:20.33#ibcon#read 3, iclass 37, count 0 2006.257.11:34:20.33#ibcon#about to read 4, iclass 37, count 0 2006.257.11:34:20.33#ibcon#read 4, iclass 37, count 0 2006.257.11:34:20.33#ibcon#about to read 5, iclass 37, count 0 2006.257.11:34:20.33#ibcon#read 5, iclass 37, count 0 2006.257.11:34:20.33#ibcon#about to read 6, iclass 37, count 0 2006.257.11:34:20.33#ibcon#read 6, iclass 37, count 0 2006.257.11:34:20.33#ibcon#end of sib2, iclass 37, count 0 2006.257.11:34:20.33#ibcon#*after write, iclass 37, count 0 2006.257.11:34:20.33#ibcon#*before return 0, iclass 37, count 0 2006.257.11:34:20.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:20.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:34:20.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:34:20.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:34:20.33$vck44/vb=8,4 2006.257.11:34:20.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.11:34:20.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.11:34:20.33#ibcon#ireg 11 cls_cnt 2 2006.257.11:34:20.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:20.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:20.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:20.39#ibcon#enter wrdev, iclass 39, count 2 2006.257.11:34:20.39#ibcon#first serial, iclass 39, count 2 2006.257.11:34:20.39#ibcon#enter sib2, iclass 39, count 2 2006.257.11:34:20.39#ibcon#flushed, iclass 39, count 2 2006.257.11:34:20.39#ibcon#about to write, iclass 39, count 2 2006.257.11:34:20.39#ibcon#wrote, iclass 39, count 2 2006.257.11:34:20.39#ibcon#about to read 3, iclass 39, count 2 2006.257.11:34:20.41#ibcon#read 3, iclass 39, count 2 2006.257.11:34:20.41#ibcon#about to read 4, iclass 39, count 2 2006.257.11:34:20.41#ibcon#read 4, iclass 39, count 2 2006.257.11:34:20.41#ibcon#about to read 5, iclass 39, count 2 2006.257.11:34:20.41#ibcon#read 5, iclass 39, count 2 2006.257.11:34:20.41#ibcon#about to read 6, iclass 39, count 2 2006.257.11:34:20.41#ibcon#read 6, iclass 39, count 2 2006.257.11:34:20.41#ibcon#end of sib2, iclass 39, count 2 2006.257.11:34:20.41#ibcon#*mode == 0, iclass 39, count 2 2006.257.11:34:20.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.11:34:20.41#ibcon#[27=AT08-04\r\n] 2006.257.11:34:20.41#ibcon#*before write, iclass 39, count 2 2006.257.11:34:20.41#ibcon#enter sib2, iclass 39, count 2 2006.257.11:34:20.41#ibcon#flushed, iclass 39, count 2 2006.257.11:34:20.41#ibcon#about to write, iclass 39, count 2 2006.257.11:34:20.41#ibcon#wrote, iclass 39, count 2 2006.257.11:34:20.41#ibcon#about to read 3, iclass 39, count 2 2006.257.11:34:20.44#ibcon#read 3, iclass 39, count 2 2006.257.11:34:20.44#ibcon#about to read 4, iclass 39, count 2 2006.257.11:34:20.44#ibcon#read 4, iclass 39, count 2 2006.257.11:34:20.44#ibcon#about to read 5, iclass 39, count 2 2006.257.11:34:20.44#ibcon#read 5, iclass 39, count 2 2006.257.11:34:20.44#ibcon#about to read 6, iclass 39, count 2 2006.257.11:34:20.44#ibcon#read 6, iclass 39, count 2 2006.257.11:34:20.44#ibcon#end of sib2, iclass 39, count 2 2006.257.11:34:20.44#ibcon#*after write, iclass 39, count 2 2006.257.11:34:20.44#ibcon#*before return 0, iclass 39, count 2 2006.257.11:34:20.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:20.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:34:20.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.11:34:20.44#ibcon#ireg 7 cls_cnt 0 2006.257.11:34:20.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:20.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:20.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:20.56#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:34:20.56#ibcon#first serial, iclass 39, count 0 2006.257.11:34:20.56#ibcon#enter sib2, iclass 39, count 0 2006.257.11:34:20.56#ibcon#flushed, iclass 39, count 0 2006.257.11:34:20.56#ibcon#about to write, iclass 39, count 0 2006.257.11:34:20.56#ibcon#wrote, iclass 39, count 0 2006.257.11:34:20.56#ibcon#about to read 3, iclass 39, count 0 2006.257.11:34:20.58#ibcon#read 3, iclass 39, count 0 2006.257.11:34:20.58#ibcon#about to read 4, iclass 39, count 0 2006.257.11:34:20.58#ibcon#read 4, iclass 39, count 0 2006.257.11:34:20.58#ibcon#about to read 5, iclass 39, count 0 2006.257.11:34:20.58#ibcon#read 5, iclass 39, count 0 2006.257.11:34:20.58#ibcon#about to read 6, iclass 39, count 0 2006.257.11:34:20.58#ibcon#read 6, iclass 39, count 0 2006.257.11:34:20.58#ibcon#end of sib2, iclass 39, count 0 2006.257.11:34:20.58#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:34:20.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:34:20.58#ibcon#[27=USB\r\n] 2006.257.11:34:20.58#ibcon#*before write, iclass 39, count 0 2006.257.11:34:20.58#ibcon#enter sib2, iclass 39, count 0 2006.257.11:34:20.58#ibcon#flushed, iclass 39, count 0 2006.257.11:34:20.58#ibcon#about to write, iclass 39, count 0 2006.257.11:34:20.58#ibcon#wrote, iclass 39, count 0 2006.257.11:34:20.58#ibcon#about to read 3, iclass 39, count 0 2006.257.11:34:20.61#ibcon#read 3, iclass 39, count 0 2006.257.11:34:20.61#ibcon#about to read 4, iclass 39, count 0 2006.257.11:34:20.61#ibcon#read 4, iclass 39, count 0 2006.257.11:34:20.61#ibcon#about to read 5, iclass 39, count 0 2006.257.11:34:20.61#ibcon#read 5, iclass 39, count 0 2006.257.11:34:20.61#ibcon#about to read 6, iclass 39, count 0 2006.257.11:34:20.61#ibcon#read 6, iclass 39, count 0 2006.257.11:34:20.61#ibcon#end of sib2, iclass 39, count 0 2006.257.11:34:20.61#ibcon#*after write, iclass 39, count 0 2006.257.11:34:20.61#ibcon#*before return 0, iclass 39, count 0 2006.257.11:34:20.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:20.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:34:20.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:34:20.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:34:20.61$vck44/vabw=wide 2006.257.11:34:20.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.11:34:20.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.11:34:20.61#ibcon#ireg 8 cls_cnt 0 2006.257.11:34:20.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:20.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:20.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:20.61#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:34:20.61#ibcon#first serial, iclass 3, count 0 2006.257.11:34:20.61#ibcon#enter sib2, iclass 3, count 0 2006.257.11:34:20.61#ibcon#flushed, iclass 3, count 0 2006.257.11:34:20.61#ibcon#about to write, iclass 3, count 0 2006.257.11:34:20.61#ibcon#wrote, iclass 3, count 0 2006.257.11:34:20.61#ibcon#about to read 3, iclass 3, count 0 2006.257.11:34:20.63#ibcon#read 3, iclass 3, count 0 2006.257.11:34:20.63#ibcon#about to read 4, iclass 3, count 0 2006.257.11:34:20.63#ibcon#read 4, iclass 3, count 0 2006.257.11:34:20.63#ibcon#about to read 5, iclass 3, count 0 2006.257.11:34:20.63#ibcon#read 5, iclass 3, count 0 2006.257.11:34:20.63#ibcon#about to read 6, iclass 3, count 0 2006.257.11:34:20.63#ibcon#read 6, iclass 3, count 0 2006.257.11:34:20.63#ibcon#end of sib2, iclass 3, count 0 2006.257.11:34:20.63#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:34:20.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:34:20.63#ibcon#[25=BW32\r\n] 2006.257.11:34:20.63#ibcon#*before write, iclass 3, count 0 2006.257.11:34:20.63#ibcon#enter sib2, iclass 3, count 0 2006.257.11:34:20.63#ibcon#flushed, iclass 3, count 0 2006.257.11:34:20.63#ibcon#about to write, iclass 3, count 0 2006.257.11:34:20.63#ibcon#wrote, iclass 3, count 0 2006.257.11:34:20.63#ibcon#about to read 3, iclass 3, count 0 2006.257.11:34:20.66#ibcon#read 3, iclass 3, count 0 2006.257.11:34:20.66#ibcon#about to read 4, iclass 3, count 0 2006.257.11:34:20.66#ibcon#read 4, iclass 3, count 0 2006.257.11:34:20.66#ibcon#about to read 5, iclass 3, count 0 2006.257.11:34:20.66#ibcon#read 5, iclass 3, count 0 2006.257.11:34:20.66#ibcon#about to read 6, iclass 3, count 0 2006.257.11:34:20.66#ibcon#read 6, iclass 3, count 0 2006.257.11:34:20.66#ibcon#end of sib2, iclass 3, count 0 2006.257.11:34:20.66#ibcon#*after write, iclass 3, count 0 2006.257.11:34:20.66#ibcon#*before return 0, iclass 3, count 0 2006.257.11:34:20.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:20.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:34:20.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:34:20.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:34:20.66$vck44/vbbw=wide 2006.257.11:34:20.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.11:34:20.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.11:34:20.66#ibcon#ireg 8 cls_cnt 0 2006.257.11:34:20.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:34:20.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:34:20.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:34:20.73#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:34:20.73#ibcon#first serial, iclass 5, count 0 2006.257.11:34:20.73#ibcon#enter sib2, iclass 5, count 0 2006.257.11:34:20.73#ibcon#flushed, iclass 5, count 0 2006.257.11:34:20.73#ibcon#about to write, iclass 5, count 0 2006.257.11:34:20.73#ibcon#wrote, iclass 5, count 0 2006.257.11:34:20.73#ibcon#about to read 3, iclass 5, count 0 2006.257.11:34:20.75#ibcon#read 3, iclass 5, count 0 2006.257.11:34:20.75#ibcon#about to read 4, iclass 5, count 0 2006.257.11:34:20.75#ibcon#read 4, iclass 5, count 0 2006.257.11:34:20.75#ibcon#about to read 5, iclass 5, count 0 2006.257.11:34:20.75#ibcon#read 5, iclass 5, count 0 2006.257.11:34:20.75#ibcon#about to read 6, iclass 5, count 0 2006.257.11:34:20.75#ibcon#read 6, iclass 5, count 0 2006.257.11:34:20.75#ibcon#end of sib2, iclass 5, count 0 2006.257.11:34:20.75#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:34:20.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:34:20.75#ibcon#[27=BW32\r\n] 2006.257.11:34:20.75#ibcon#*before write, iclass 5, count 0 2006.257.11:34:20.75#ibcon#enter sib2, iclass 5, count 0 2006.257.11:34:20.75#ibcon#flushed, iclass 5, count 0 2006.257.11:34:20.75#ibcon#about to write, iclass 5, count 0 2006.257.11:34:20.75#ibcon#wrote, iclass 5, count 0 2006.257.11:34:20.75#ibcon#about to read 3, iclass 5, count 0 2006.257.11:34:20.78#ibcon#read 3, iclass 5, count 0 2006.257.11:34:20.78#ibcon#about to read 4, iclass 5, count 0 2006.257.11:34:20.78#ibcon#read 4, iclass 5, count 0 2006.257.11:34:20.78#ibcon#about to read 5, iclass 5, count 0 2006.257.11:34:20.78#ibcon#read 5, iclass 5, count 0 2006.257.11:34:20.78#ibcon#about to read 6, iclass 5, count 0 2006.257.11:34:20.78#ibcon#read 6, iclass 5, count 0 2006.257.11:34:20.78#ibcon#end of sib2, iclass 5, count 0 2006.257.11:34:20.78#ibcon#*after write, iclass 5, count 0 2006.257.11:34:20.78#ibcon#*before return 0, iclass 5, count 0 2006.257.11:34:20.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:34:20.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:34:20.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:34:20.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:34:20.78$setupk4/ifdk4 2006.257.11:34:20.78$ifdk4/lo= 2006.257.11:34:20.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:34:20.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:34:20.78$ifdk4/patch= 2006.257.11:34:20.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:34:20.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:34:20.78$setupk4/!*+20s 2006.257.11:34:22.85#abcon#<5=/14 1.3 2.6 18.16 971014.0\r\n> 2006.257.11:34:22.87#abcon#{5=INTERFACE CLEAR} 2006.257.11:34:22.93#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:34:32.14#trakl#Source acquired 2006.257.11:34:33.02#abcon#<5=/14 1.3 3.7 18.16 971014.0\r\n> 2006.257.11:34:33.04#abcon#{5=INTERFACE CLEAR} 2006.257.11:34:33.10#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:34:34.14#flagr#flagr/antenna,acquired 2006.257.11:34:35.25$setupk4/"tpicd 2006.257.11:34:35.25$setupk4/echo=off 2006.257.11:34:35.25$setupk4/xlog=off 2006.257.11:34:35.25:!2006.257.11:38:11 2006.257.11:38:11.00:preob 2006.257.11:38:11.14/onsource/TRACKING 2006.257.11:38:11.14:!2006.257.11:38:21 2006.257.11:38:21.00:"tape 2006.257.11:38:21.00:"st=record 2006.257.11:38:21.00:data_valid=on 2006.257.11:38:21.00:midob 2006.257.11:38:22.14/onsource/TRACKING 2006.257.11:38:22.14/wx/18.14,1014.0,96 2006.257.11:38:22.23/cable/+6.4784E-03 2006.257.11:38:23.32/va/01,08,usb,yes,30,32 2006.257.11:38:23.32/va/02,07,usb,yes,33,33 2006.257.11:38:23.32/va/03,08,usb,yes,29,31 2006.257.11:38:23.32/va/04,07,usb,yes,33,35 2006.257.11:38:23.32/va/05,04,usb,yes,30,30 2006.257.11:38:23.32/va/06,04,usb,yes,33,33 2006.257.11:38:23.32/va/07,04,usb,yes,34,35 2006.257.11:38:23.32/va/08,04,usb,yes,28,35 2006.257.11:38:23.55/valo/01,524.99,yes,locked 2006.257.11:38:23.55/valo/02,534.99,yes,locked 2006.257.11:38:23.55/valo/03,564.99,yes,locked 2006.257.11:38:23.55/valo/04,624.99,yes,locked 2006.257.11:38:23.55/valo/05,734.99,yes,locked 2006.257.11:38:23.55/valo/06,814.99,yes,locked 2006.257.11:38:23.55/valo/07,864.99,yes,locked 2006.257.11:38:23.55/valo/08,884.99,yes,locked 2006.257.11:38:24.64/vb/01,04,usb,yes,30,28 2006.257.11:38:24.64/vb/02,05,usb,yes,28,28 2006.257.11:38:24.64/vb/03,04,usb,yes,29,32 2006.257.11:38:24.64/vb/04,05,usb,yes,30,29 2006.257.11:38:24.64/vb/05,04,usb,yes,26,28 2006.257.11:38:24.64/vb/06,04,usb,yes,31,27 2006.257.11:38:24.64/vb/07,04,usb,yes,30,30 2006.257.11:38:24.64/vb/08,04,usb,yes,28,31 2006.257.11:38:24.88/vblo/01,629.99,yes,locked 2006.257.11:38:24.88/vblo/02,634.99,yes,locked 2006.257.11:38:24.88/vblo/03,649.99,yes,locked 2006.257.11:38:24.88/vblo/04,679.99,yes,locked 2006.257.11:38:24.88/vblo/05,709.99,yes,locked 2006.257.11:38:24.88/vblo/06,719.99,yes,locked 2006.257.11:38:24.88/vblo/07,734.99,yes,locked 2006.257.11:38:24.88/vblo/08,744.99,yes,locked 2006.257.11:38:25.03/vabw/8 2006.257.11:38:25.18/vbbw/8 2006.257.11:38:25.35/xfe/off,on,15.2 2006.257.11:38:25.73/ifatt/23,28,28,28 2006.257.11:38:26.07/fmout-gps/S +4.57E-07 2006.257.11:38:26.11:!2006.257.11:41:01 2006.257.11:41:01.01:data_valid=off 2006.257.11:41:01.02:"et 2006.257.11:41:01.02:!+3s 2006.257.11:41:04.03:"tape 2006.257.11:41:04.03:postob 2006.257.11:41:04.23/cable/+6.4782E-03 2006.257.11:41:04.23/wx/18.13,1014.1,96 2006.257.11:41:04.29/fmout-gps/S +4.58E-07 2006.257.11:41:04.29:scan_name=257-1146,jd0609,60 2006.257.11:41:04.30:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.257.11:41:06.14#flagr#flagr/antenna,new-source 2006.257.11:41:06.14:checkk5 2006.257.11:41:06.52/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:41:06.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:41:07.31/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:41:07.70/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:41:08.10/chk_obsdata//k5ts1/T2571138??a.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.11:41:08.51/chk_obsdata//k5ts2/T2571138??b.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.11:41:08.89/chk_obsdata//k5ts3/T2571138??c.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.11:41:09.29/chk_obsdata//k5ts4/T2571138??d.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.11:41:10.00/k5log//k5ts1_log_newline 2006.257.11:41:10.69/k5log//k5ts2_log_newline 2006.257.11:41:11.39/k5log//k5ts3_log_newline 2006.257.11:41:12.08/k5log//k5ts4_log_newline 2006.257.11:41:12.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:41:12.11:setupk4=1 2006.257.11:41:12.11$setupk4/echo=on 2006.257.11:41:12.11$setupk4/pcalon 2006.257.11:41:12.11$pcalon/"no phase cal control is implemented here 2006.257.11:41:12.11$setupk4/"tpicd=stop 2006.257.11:41:12.11$setupk4/"rec=synch_on 2006.257.11:41:12.11$setupk4/"rec_mode=128 2006.257.11:41:12.11$setupk4/!* 2006.257.11:41:12.11$setupk4/recpk4 2006.257.11:41:12.11$recpk4/recpatch= 2006.257.11:41:12.11$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:41:12.11$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:41:12.11$setupk4/vck44 2006.257.11:41:12.11$vck44/valo=1,524.99 2006.257.11:41:12.11#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.11:41:12.11#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.11:41:12.11#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:12.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:12.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:12.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:12.11#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:41:12.11#ibcon#first serial, iclass 23, count 0 2006.257.11:41:12.11#ibcon#enter sib2, iclass 23, count 0 2006.257.11:41:12.11#ibcon#flushed, iclass 23, count 0 2006.257.11:41:12.11#ibcon#about to write, iclass 23, count 0 2006.257.11:41:12.11#ibcon#wrote, iclass 23, count 0 2006.257.11:41:12.11#ibcon#about to read 3, iclass 23, count 0 2006.257.11:41:12.13#ibcon#read 3, iclass 23, count 0 2006.257.11:41:12.13#ibcon#about to read 4, iclass 23, count 0 2006.257.11:41:12.13#ibcon#read 4, iclass 23, count 0 2006.257.11:41:12.13#ibcon#about to read 5, iclass 23, count 0 2006.257.11:41:12.13#ibcon#read 5, iclass 23, count 0 2006.257.11:41:12.13#ibcon#about to read 6, iclass 23, count 0 2006.257.11:41:12.13#ibcon#read 6, iclass 23, count 0 2006.257.11:41:12.13#ibcon#end of sib2, iclass 23, count 0 2006.257.11:41:12.13#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:41:12.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:41:12.13#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:41:12.13#ibcon#*before write, iclass 23, count 0 2006.257.11:41:12.13#ibcon#enter sib2, iclass 23, count 0 2006.257.11:41:12.13#ibcon#flushed, iclass 23, count 0 2006.257.11:41:12.13#ibcon#about to write, iclass 23, count 0 2006.257.11:41:12.13#ibcon#wrote, iclass 23, count 0 2006.257.11:41:12.13#ibcon#about to read 3, iclass 23, count 0 2006.257.11:41:12.18#ibcon#read 3, iclass 23, count 0 2006.257.11:41:12.18#ibcon#about to read 4, iclass 23, count 0 2006.257.11:41:12.18#ibcon#read 4, iclass 23, count 0 2006.257.11:41:12.18#ibcon#about to read 5, iclass 23, count 0 2006.257.11:41:12.18#ibcon#read 5, iclass 23, count 0 2006.257.11:41:12.18#ibcon#about to read 6, iclass 23, count 0 2006.257.11:41:12.18#ibcon#read 6, iclass 23, count 0 2006.257.11:41:12.18#ibcon#end of sib2, iclass 23, count 0 2006.257.11:41:12.18#ibcon#*after write, iclass 23, count 0 2006.257.11:41:12.18#ibcon#*before return 0, iclass 23, count 0 2006.257.11:41:12.18#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:12.18#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:12.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:41:12.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:41:12.18$vck44/va=1,8 2006.257.11:41:12.18#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.11:41:12.18#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.11:41:12.18#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:12.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:12.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:12.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:12.18#ibcon#enter wrdev, iclass 25, count 2 2006.257.11:41:12.18#ibcon#first serial, iclass 25, count 2 2006.257.11:41:12.18#ibcon#enter sib2, iclass 25, count 2 2006.257.11:41:12.18#ibcon#flushed, iclass 25, count 2 2006.257.11:41:12.18#ibcon#about to write, iclass 25, count 2 2006.257.11:41:12.18#ibcon#wrote, iclass 25, count 2 2006.257.11:41:12.18#ibcon#about to read 3, iclass 25, count 2 2006.257.11:41:12.20#ibcon#read 3, iclass 25, count 2 2006.257.11:41:12.20#ibcon#about to read 4, iclass 25, count 2 2006.257.11:41:12.20#ibcon#read 4, iclass 25, count 2 2006.257.11:41:12.20#ibcon#about to read 5, iclass 25, count 2 2006.257.11:41:12.20#ibcon#read 5, iclass 25, count 2 2006.257.11:41:12.20#ibcon#about to read 6, iclass 25, count 2 2006.257.11:41:12.20#ibcon#read 6, iclass 25, count 2 2006.257.11:41:12.20#ibcon#end of sib2, iclass 25, count 2 2006.257.11:41:12.20#ibcon#*mode == 0, iclass 25, count 2 2006.257.11:41:12.20#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.11:41:12.20#ibcon#[25=AT01-08\r\n] 2006.257.11:41:12.20#ibcon#*before write, iclass 25, count 2 2006.257.11:41:12.20#ibcon#enter sib2, iclass 25, count 2 2006.257.11:41:12.20#ibcon#flushed, iclass 25, count 2 2006.257.11:41:12.20#ibcon#about to write, iclass 25, count 2 2006.257.11:41:12.20#ibcon#wrote, iclass 25, count 2 2006.257.11:41:12.20#ibcon#about to read 3, iclass 25, count 2 2006.257.11:41:12.23#ibcon#read 3, iclass 25, count 2 2006.257.11:41:12.23#ibcon#about to read 4, iclass 25, count 2 2006.257.11:41:12.23#ibcon#read 4, iclass 25, count 2 2006.257.11:41:12.23#ibcon#about to read 5, iclass 25, count 2 2006.257.11:41:12.23#ibcon#read 5, iclass 25, count 2 2006.257.11:41:12.23#ibcon#about to read 6, iclass 25, count 2 2006.257.11:41:12.23#ibcon#read 6, iclass 25, count 2 2006.257.11:41:12.23#ibcon#end of sib2, iclass 25, count 2 2006.257.11:41:12.23#ibcon#*after write, iclass 25, count 2 2006.257.11:41:12.23#ibcon#*before return 0, iclass 25, count 2 2006.257.11:41:12.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:12.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:12.23#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.11:41:12.23#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:12.23#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:12.35#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:12.35#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:12.35#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:41:12.35#ibcon#first serial, iclass 25, count 0 2006.257.11:41:12.35#ibcon#enter sib2, iclass 25, count 0 2006.257.11:41:12.35#ibcon#flushed, iclass 25, count 0 2006.257.11:41:12.35#ibcon#about to write, iclass 25, count 0 2006.257.11:41:12.35#ibcon#wrote, iclass 25, count 0 2006.257.11:41:12.35#ibcon#about to read 3, iclass 25, count 0 2006.257.11:41:12.37#ibcon#read 3, iclass 25, count 0 2006.257.11:41:12.37#ibcon#about to read 4, iclass 25, count 0 2006.257.11:41:12.37#ibcon#read 4, iclass 25, count 0 2006.257.11:41:12.37#ibcon#about to read 5, iclass 25, count 0 2006.257.11:41:12.37#ibcon#read 5, iclass 25, count 0 2006.257.11:41:12.37#ibcon#about to read 6, iclass 25, count 0 2006.257.11:41:12.37#ibcon#read 6, iclass 25, count 0 2006.257.11:41:12.37#ibcon#end of sib2, iclass 25, count 0 2006.257.11:41:12.37#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:41:12.37#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:41:12.37#ibcon#[25=USB\r\n] 2006.257.11:41:12.37#ibcon#*before write, iclass 25, count 0 2006.257.11:41:12.37#ibcon#enter sib2, iclass 25, count 0 2006.257.11:41:12.37#ibcon#flushed, iclass 25, count 0 2006.257.11:41:12.37#ibcon#about to write, iclass 25, count 0 2006.257.11:41:12.37#ibcon#wrote, iclass 25, count 0 2006.257.11:41:12.37#ibcon#about to read 3, iclass 25, count 0 2006.257.11:41:12.40#ibcon#read 3, iclass 25, count 0 2006.257.11:41:12.40#ibcon#about to read 4, iclass 25, count 0 2006.257.11:41:12.40#ibcon#read 4, iclass 25, count 0 2006.257.11:41:12.40#ibcon#about to read 5, iclass 25, count 0 2006.257.11:41:12.40#ibcon#read 5, iclass 25, count 0 2006.257.11:41:12.40#ibcon#about to read 6, iclass 25, count 0 2006.257.11:41:12.40#ibcon#read 6, iclass 25, count 0 2006.257.11:41:12.40#ibcon#end of sib2, iclass 25, count 0 2006.257.11:41:12.40#ibcon#*after write, iclass 25, count 0 2006.257.11:41:12.40#ibcon#*before return 0, iclass 25, count 0 2006.257.11:41:12.40#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:12.40#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:12.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:41:12.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:41:12.40$vck44/valo=2,534.99 2006.257.11:41:12.40#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.11:41:12.40#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.11:41:12.40#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:12.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:12.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:12.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:12.40#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:41:12.40#ibcon#first serial, iclass 27, count 0 2006.257.11:41:12.40#ibcon#enter sib2, iclass 27, count 0 2006.257.11:41:12.40#ibcon#flushed, iclass 27, count 0 2006.257.11:41:12.40#ibcon#about to write, iclass 27, count 0 2006.257.11:41:12.40#ibcon#wrote, iclass 27, count 0 2006.257.11:41:12.40#ibcon#about to read 3, iclass 27, count 0 2006.257.11:41:12.42#ibcon#read 3, iclass 27, count 0 2006.257.11:41:12.42#ibcon#about to read 4, iclass 27, count 0 2006.257.11:41:12.42#ibcon#read 4, iclass 27, count 0 2006.257.11:41:12.42#ibcon#about to read 5, iclass 27, count 0 2006.257.11:41:12.42#ibcon#read 5, iclass 27, count 0 2006.257.11:41:12.42#ibcon#about to read 6, iclass 27, count 0 2006.257.11:41:12.42#ibcon#read 6, iclass 27, count 0 2006.257.11:41:12.42#ibcon#end of sib2, iclass 27, count 0 2006.257.11:41:12.42#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:41:12.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:41:12.42#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:41:12.42#ibcon#*before write, iclass 27, count 0 2006.257.11:41:12.42#ibcon#enter sib2, iclass 27, count 0 2006.257.11:41:12.42#ibcon#flushed, iclass 27, count 0 2006.257.11:41:12.42#ibcon#about to write, iclass 27, count 0 2006.257.11:41:12.42#ibcon#wrote, iclass 27, count 0 2006.257.11:41:12.42#ibcon#about to read 3, iclass 27, count 0 2006.257.11:41:12.46#ibcon#read 3, iclass 27, count 0 2006.257.11:41:12.46#ibcon#about to read 4, iclass 27, count 0 2006.257.11:41:12.46#ibcon#read 4, iclass 27, count 0 2006.257.11:41:12.46#ibcon#about to read 5, iclass 27, count 0 2006.257.11:41:12.46#ibcon#read 5, iclass 27, count 0 2006.257.11:41:12.46#ibcon#about to read 6, iclass 27, count 0 2006.257.11:41:12.46#ibcon#read 6, iclass 27, count 0 2006.257.11:41:12.46#ibcon#end of sib2, iclass 27, count 0 2006.257.11:41:12.46#ibcon#*after write, iclass 27, count 0 2006.257.11:41:12.46#ibcon#*before return 0, iclass 27, count 0 2006.257.11:41:12.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:12.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:12.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:41:12.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:41:12.46$vck44/va=2,7 2006.257.11:41:12.46#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.11:41:12.46#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.11:41:12.46#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:12.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:41:12.48#abcon#<5=/14 1.3 3.9 18.13 961014.1\r\n> 2006.257.11:41:12.50#abcon#{5=INTERFACE CLEAR} 2006.257.11:41:12.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:41:12.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:41:12.52#ibcon#enter wrdev, iclass 30, count 2 2006.257.11:41:12.52#ibcon#first serial, iclass 30, count 2 2006.257.11:41:12.52#ibcon#enter sib2, iclass 30, count 2 2006.257.11:41:12.52#ibcon#flushed, iclass 30, count 2 2006.257.11:41:12.52#ibcon#about to write, iclass 30, count 2 2006.257.11:41:12.52#ibcon#wrote, iclass 30, count 2 2006.257.11:41:12.52#ibcon#about to read 3, iclass 30, count 2 2006.257.11:41:12.54#ibcon#read 3, iclass 30, count 2 2006.257.11:41:12.54#ibcon#about to read 4, iclass 30, count 2 2006.257.11:41:12.54#ibcon#read 4, iclass 30, count 2 2006.257.11:41:12.54#ibcon#about to read 5, iclass 30, count 2 2006.257.11:41:12.54#ibcon#read 5, iclass 30, count 2 2006.257.11:41:12.54#ibcon#about to read 6, iclass 30, count 2 2006.257.11:41:12.54#ibcon#read 6, iclass 30, count 2 2006.257.11:41:12.54#ibcon#end of sib2, iclass 30, count 2 2006.257.11:41:12.54#ibcon#*mode == 0, iclass 30, count 2 2006.257.11:41:12.54#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.11:41:12.54#ibcon#[25=AT02-07\r\n] 2006.257.11:41:12.54#ibcon#*before write, iclass 30, count 2 2006.257.11:41:12.54#ibcon#enter sib2, iclass 30, count 2 2006.257.11:41:12.54#ibcon#flushed, iclass 30, count 2 2006.257.11:41:12.54#ibcon#about to write, iclass 30, count 2 2006.257.11:41:12.54#ibcon#wrote, iclass 30, count 2 2006.257.11:41:12.54#ibcon#about to read 3, iclass 30, count 2 2006.257.11:41:12.56#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:41:12.57#ibcon#read 3, iclass 30, count 2 2006.257.11:41:12.57#ibcon#about to read 4, iclass 30, count 2 2006.257.11:41:12.57#ibcon#read 4, iclass 30, count 2 2006.257.11:41:12.57#ibcon#about to read 5, iclass 30, count 2 2006.257.11:41:12.57#ibcon#read 5, iclass 30, count 2 2006.257.11:41:12.57#ibcon#about to read 6, iclass 30, count 2 2006.257.11:41:12.57#ibcon#read 6, iclass 30, count 2 2006.257.11:41:12.57#ibcon#end of sib2, iclass 30, count 2 2006.257.11:41:12.57#ibcon#*after write, iclass 30, count 2 2006.257.11:41:12.57#ibcon#*before return 0, iclass 30, count 2 2006.257.11:41:12.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:41:12.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:41:12.57#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.11:41:12.57#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:12.57#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:41:12.69#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:41:12.69#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:41:12.69#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:41:12.69#ibcon#first serial, iclass 30, count 0 2006.257.11:41:12.69#ibcon#enter sib2, iclass 30, count 0 2006.257.11:41:12.69#ibcon#flushed, iclass 30, count 0 2006.257.11:41:12.69#ibcon#about to write, iclass 30, count 0 2006.257.11:41:12.69#ibcon#wrote, iclass 30, count 0 2006.257.11:41:12.69#ibcon#about to read 3, iclass 30, count 0 2006.257.11:41:12.71#ibcon#read 3, iclass 30, count 0 2006.257.11:41:12.71#ibcon#about to read 4, iclass 30, count 0 2006.257.11:41:12.71#ibcon#read 4, iclass 30, count 0 2006.257.11:41:12.71#ibcon#about to read 5, iclass 30, count 0 2006.257.11:41:12.71#ibcon#read 5, iclass 30, count 0 2006.257.11:41:12.71#ibcon#about to read 6, iclass 30, count 0 2006.257.11:41:12.71#ibcon#read 6, iclass 30, count 0 2006.257.11:41:12.71#ibcon#end of sib2, iclass 30, count 0 2006.257.11:41:12.71#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:41:12.71#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:41:12.71#ibcon#[25=USB\r\n] 2006.257.11:41:12.71#ibcon#*before write, iclass 30, count 0 2006.257.11:41:12.71#ibcon#enter sib2, iclass 30, count 0 2006.257.11:41:12.71#ibcon#flushed, iclass 30, count 0 2006.257.11:41:12.71#ibcon#about to write, iclass 30, count 0 2006.257.11:41:12.71#ibcon#wrote, iclass 30, count 0 2006.257.11:41:12.71#ibcon#about to read 3, iclass 30, count 0 2006.257.11:41:12.74#ibcon#read 3, iclass 30, count 0 2006.257.11:41:12.74#ibcon#about to read 4, iclass 30, count 0 2006.257.11:41:12.74#ibcon#read 4, iclass 30, count 0 2006.257.11:41:12.74#ibcon#about to read 5, iclass 30, count 0 2006.257.11:41:12.74#ibcon#read 5, iclass 30, count 0 2006.257.11:41:12.74#ibcon#about to read 6, iclass 30, count 0 2006.257.11:41:12.74#ibcon#read 6, iclass 30, count 0 2006.257.11:41:12.74#ibcon#end of sib2, iclass 30, count 0 2006.257.11:41:12.74#ibcon#*after write, iclass 30, count 0 2006.257.11:41:12.74#ibcon#*before return 0, iclass 30, count 0 2006.257.11:41:12.74#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:41:12.74#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:41:12.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:41:12.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:41:12.74$vck44/valo=3,564.99 2006.257.11:41:12.74#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.11:41:12.74#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.11:41:12.74#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:12.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:12.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:12.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:12.74#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:41:12.74#ibcon#first serial, iclass 35, count 0 2006.257.11:41:12.74#ibcon#enter sib2, iclass 35, count 0 2006.257.11:41:12.74#ibcon#flushed, iclass 35, count 0 2006.257.11:41:12.74#ibcon#about to write, iclass 35, count 0 2006.257.11:41:12.74#ibcon#wrote, iclass 35, count 0 2006.257.11:41:12.74#ibcon#about to read 3, iclass 35, count 0 2006.257.11:41:12.76#ibcon#read 3, iclass 35, count 0 2006.257.11:41:12.76#ibcon#about to read 4, iclass 35, count 0 2006.257.11:41:12.76#ibcon#read 4, iclass 35, count 0 2006.257.11:41:12.76#ibcon#about to read 5, iclass 35, count 0 2006.257.11:41:12.76#ibcon#read 5, iclass 35, count 0 2006.257.11:41:12.76#ibcon#about to read 6, iclass 35, count 0 2006.257.11:41:12.76#ibcon#read 6, iclass 35, count 0 2006.257.11:41:12.76#ibcon#end of sib2, iclass 35, count 0 2006.257.11:41:12.76#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:41:12.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:41:12.76#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:41:12.76#ibcon#*before write, iclass 35, count 0 2006.257.11:41:12.76#ibcon#enter sib2, iclass 35, count 0 2006.257.11:41:12.76#ibcon#flushed, iclass 35, count 0 2006.257.11:41:12.76#ibcon#about to write, iclass 35, count 0 2006.257.11:41:12.76#ibcon#wrote, iclass 35, count 0 2006.257.11:41:12.76#ibcon#about to read 3, iclass 35, count 0 2006.257.11:41:12.80#ibcon#read 3, iclass 35, count 0 2006.257.11:41:12.80#ibcon#about to read 4, iclass 35, count 0 2006.257.11:41:12.80#ibcon#read 4, iclass 35, count 0 2006.257.11:41:12.80#ibcon#about to read 5, iclass 35, count 0 2006.257.11:41:12.80#ibcon#read 5, iclass 35, count 0 2006.257.11:41:12.80#ibcon#about to read 6, iclass 35, count 0 2006.257.11:41:12.80#ibcon#read 6, iclass 35, count 0 2006.257.11:41:12.80#ibcon#end of sib2, iclass 35, count 0 2006.257.11:41:12.80#ibcon#*after write, iclass 35, count 0 2006.257.11:41:12.80#ibcon#*before return 0, iclass 35, count 0 2006.257.11:41:12.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:12.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:12.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:41:12.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:41:12.80$vck44/va=3,8 2006.257.11:41:12.80#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.11:41:12.80#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.11:41:12.80#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:12.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:12.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:12.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:12.86#ibcon#enter wrdev, iclass 37, count 2 2006.257.11:41:12.86#ibcon#first serial, iclass 37, count 2 2006.257.11:41:12.86#ibcon#enter sib2, iclass 37, count 2 2006.257.11:41:12.86#ibcon#flushed, iclass 37, count 2 2006.257.11:41:12.86#ibcon#about to write, iclass 37, count 2 2006.257.11:41:12.86#ibcon#wrote, iclass 37, count 2 2006.257.11:41:12.86#ibcon#about to read 3, iclass 37, count 2 2006.257.11:41:12.88#ibcon#read 3, iclass 37, count 2 2006.257.11:41:12.88#ibcon#about to read 4, iclass 37, count 2 2006.257.11:41:12.88#ibcon#read 4, iclass 37, count 2 2006.257.11:41:12.88#ibcon#about to read 5, iclass 37, count 2 2006.257.11:41:12.88#ibcon#read 5, iclass 37, count 2 2006.257.11:41:12.88#ibcon#about to read 6, iclass 37, count 2 2006.257.11:41:12.88#ibcon#read 6, iclass 37, count 2 2006.257.11:41:12.88#ibcon#end of sib2, iclass 37, count 2 2006.257.11:41:12.88#ibcon#*mode == 0, iclass 37, count 2 2006.257.11:41:12.88#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.11:41:12.88#ibcon#[25=AT03-08\r\n] 2006.257.11:41:12.88#ibcon#*before write, iclass 37, count 2 2006.257.11:41:12.88#ibcon#enter sib2, iclass 37, count 2 2006.257.11:41:12.88#ibcon#flushed, iclass 37, count 2 2006.257.11:41:12.88#ibcon#about to write, iclass 37, count 2 2006.257.11:41:12.88#ibcon#wrote, iclass 37, count 2 2006.257.11:41:12.88#ibcon#about to read 3, iclass 37, count 2 2006.257.11:41:12.91#ibcon#read 3, iclass 37, count 2 2006.257.11:41:12.91#ibcon#about to read 4, iclass 37, count 2 2006.257.11:41:12.91#ibcon#read 4, iclass 37, count 2 2006.257.11:41:12.91#ibcon#about to read 5, iclass 37, count 2 2006.257.11:41:12.91#ibcon#read 5, iclass 37, count 2 2006.257.11:41:12.91#ibcon#about to read 6, iclass 37, count 2 2006.257.11:41:12.91#ibcon#read 6, iclass 37, count 2 2006.257.11:41:12.91#ibcon#end of sib2, iclass 37, count 2 2006.257.11:41:12.91#ibcon#*after write, iclass 37, count 2 2006.257.11:41:12.91#ibcon#*before return 0, iclass 37, count 2 2006.257.11:41:12.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:12.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:12.91#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.11:41:12.91#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:12.91#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:13.03#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:13.03#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:13.03#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:41:13.03#ibcon#first serial, iclass 37, count 0 2006.257.11:41:13.03#ibcon#enter sib2, iclass 37, count 0 2006.257.11:41:13.03#ibcon#flushed, iclass 37, count 0 2006.257.11:41:13.03#ibcon#about to write, iclass 37, count 0 2006.257.11:41:13.03#ibcon#wrote, iclass 37, count 0 2006.257.11:41:13.03#ibcon#about to read 3, iclass 37, count 0 2006.257.11:41:13.05#ibcon#read 3, iclass 37, count 0 2006.257.11:41:13.05#ibcon#about to read 4, iclass 37, count 0 2006.257.11:41:13.05#ibcon#read 4, iclass 37, count 0 2006.257.11:41:13.05#ibcon#about to read 5, iclass 37, count 0 2006.257.11:41:13.05#ibcon#read 5, iclass 37, count 0 2006.257.11:41:13.05#ibcon#about to read 6, iclass 37, count 0 2006.257.11:41:13.05#ibcon#read 6, iclass 37, count 0 2006.257.11:41:13.05#ibcon#end of sib2, iclass 37, count 0 2006.257.11:41:13.05#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:41:13.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:41:13.05#ibcon#[25=USB\r\n] 2006.257.11:41:13.05#ibcon#*before write, iclass 37, count 0 2006.257.11:41:13.05#ibcon#enter sib2, iclass 37, count 0 2006.257.11:41:13.05#ibcon#flushed, iclass 37, count 0 2006.257.11:41:13.05#ibcon#about to write, iclass 37, count 0 2006.257.11:41:13.05#ibcon#wrote, iclass 37, count 0 2006.257.11:41:13.05#ibcon#about to read 3, iclass 37, count 0 2006.257.11:41:13.08#ibcon#read 3, iclass 37, count 0 2006.257.11:41:13.08#ibcon#about to read 4, iclass 37, count 0 2006.257.11:41:13.08#ibcon#read 4, iclass 37, count 0 2006.257.11:41:13.08#ibcon#about to read 5, iclass 37, count 0 2006.257.11:41:13.08#ibcon#read 5, iclass 37, count 0 2006.257.11:41:13.08#ibcon#about to read 6, iclass 37, count 0 2006.257.11:41:13.08#ibcon#read 6, iclass 37, count 0 2006.257.11:41:13.08#ibcon#end of sib2, iclass 37, count 0 2006.257.11:41:13.08#ibcon#*after write, iclass 37, count 0 2006.257.11:41:13.08#ibcon#*before return 0, iclass 37, count 0 2006.257.11:41:13.08#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:13.08#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:13.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:41:13.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:41:13.08$vck44/valo=4,624.99 2006.257.11:41:13.08#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.11:41:13.08#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.11:41:13.08#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:13.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:13.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:13.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:13.08#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:41:13.08#ibcon#first serial, iclass 39, count 0 2006.257.11:41:13.08#ibcon#enter sib2, iclass 39, count 0 2006.257.11:41:13.08#ibcon#flushed, iclass 39, count 0 2006.257.11:41:13.08#ibcon#about to write, iclass 39, count 0 2006.257.11:41:13.08#ibcon#wrote, iclass 39, count 0 2006.257.11:41:13.08#ibcon#about to read 3, iclass 39, count 0 2006.257.11:41:13.10#ibcon#read 3, iclass 39, count 0 2006.257.11:41:13.10#ibcon#about to read 4, iclass 39, count 0 2006.257.11:41:13.10#ibcon#read 4, iclass 39, count 0 2006.257.11:41:13.10#ibcon#about to read 5, iclass 39, count 0 2006.257.11:41:13.10#ibcon#read 5, iclass 39, count 0 2006.257.11:41:13.10#ibcon#about to read 6, iclass 39, count 0 2006.257.11:41:13.10#ibcon#read 6, iclass 39, count 0 2006.257.11:41:13.10#ibcon#end of sib2, iclass 39, count 0 2006.257.11:41:13.10#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:41:13.10#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:41:13.10#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:41:13.10#ibcon#*before write, iclass 39, count 0 2006.257.11:41:13.10#ibcon#enter sib2, iclass 39, count 0 2006.257.11:41:13.10#ibcon#flushed, iclass 39, count 0 2006.257.11:41:13.10#ibcon#about to write, iclass 39, count 0 2006.257.11:41:13.10#ibcon#wrote, iclass 39, count 0 2006.257.11:41:13.10#ibcon#about to read 3, iclass 39, count 0 2006.257.11:41:13.14#ibcon#read 3, iclass 39, count 0 2006.257.11:41:13.14#ibcon#about to read 4, iclass 39, count 0 2006.257.11:41:13.14#ibcon#read 4, iclass 39, count 0 2006.257.11:41:13.14#ibcon#about to read 5, iclass 39, count 0 2006.257.11:41:13.14#ibcon#read 5, iclass 39, count 0 2006.257.11:41:13.14#ibcon#about to read 6, iclass 39, count 0 2006.257.11:41:13.14#ibcon#read 6, iclass 39, count 0 2006.257.11:41:13.14#ibcon#end of sib2, iclass 39, count 0 2006.257.11:41:13.14#ibcon#*after write, iclass 39, count 0 2006.257.11:41:13.14#ibcon#*before return 0, iclass 39, count 0 2006.257.11:41:13.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:13.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:13.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:41:13.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:41:13.14$vck44/va=4,7 2006.257.11:41:13.14#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.11:41:13.14#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.11:41:13.14#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:13.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:13.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:13.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:13.20#ibcon#enter wrdev, iclass 3, count 2 2006.257.11:41:13.20#ibcon#first serial, iclass 3, count 2 2006.257.11:41:13.20#ibcon#enter sib2, iclass 3, count 2 2006.257.11:41:13.20#ibcon#flushed, iclass 3, count 2 2006.257.11:41:13.20#ibcon#about to write, iclass 3, count 2 2006.257.11:41:13.20#ibcon#wrote, iclass 3, count 2 2006.257.11:41:13.20#ibcon#about to read 3, iclass 3, count 2 2006.257.11:41:13.22#ibcon#read 3, iclass 3, count 2 2006.257.11:41:13.22#ibcon#about to read 4, iclass 3, count 2 2006.257.11:41:13.22#ibcon#read 4, iclass 3, count 2 2006.257.11:41:13.22#ibcon#about to read 5, iclass 3, count 2 2006.257.11:41:13.22#ibcon#read 5, iclass 3, count 2 2006.257.11:41:13.22#ibcon#about to read 6, iclass 3, count 2 2006.257.11:41:13.22#ibcon#read 6, iclass 3, count 2 2006.257.11:41:13.22#ibcon#end of sib2, iclass 3, count 2 2006.257.11:41:13.22#ibcon#*mode == 0, iclass 3, count 2 2006.257.11:41:13.22#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.11:41:13.22#ibcon#[25=AT04-07\r\n] 2006.257.11:41:13.22#ibcon#*before write, iclass 3, count 2 2006.257.11:41:13.22#ibcon#enter sib2, iclass 3, count 2 2006.257.11:41:13.22#ibcon#flushed, iclass 3, count 2 2006.257.11:41:13.22#ibcon#about to write, iclass 3, count 2 2006.257.11:41:13.22#ibcon#wrote, iclass 3, count 2 2006.257.11:41:13.22#ibcon#about to read 3, iclass 3, count 2 2006.257.11:41:13.25#ibcon#read 3, iclass 3, count 2 2006.257.11:41:13.25#ibcon#about to read 4, iclass 3, count 2 2006.257.11:41:13.25#ibcon#read 4, iclass 3, count 2 2006.257.11:41:13.25#ibcon#about to read 5, iclass 3, count 2 2006.257.11:41:13.25#ibcon#read 5, iclass 3, count 2 2006.257.11:41:13.25#ibcon#about to read 6, iclass 3, count 2 2006.257.11:41:13.25#ibcon#read 6, iclass 3, count 2 2006.257.11:41:13.25#ibcon#end of sib2, iclass 3, count 2 2006.257.11:41:13.25#ibcon#*after write, iclass 3, count 2 2006.257.11:41:13.25#ibcon#*before return 0, iclass 3, count 2 2006.257.11:41:13.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:13.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:13.25#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.11:41:13.25#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:13.25#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:13.37#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:13.37#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:13.37#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:41:13.37#ibcon#first serial, iclass 3, count 0 2006.257.11:41:13.37#ibcon#enter sib2, iclass 3, count 0 2006.257.11:41:13.37#ibcon#flushed, iclass 3, count 0 2006.257.11:41:13.37#ibcon#about to write, iclass 3, count 0 2006.257.11:41:13.37#ibcon#wrote, iclass 3, count 0 2006.257.11:41:13.37#ibcon#about to read 3, iclass 3, count 0 2006.257.11:41:13.39#ibcon#read 3, iclass 3, count 0 2006.257.11:41:13.39#ibcon#about to read 4, iclass 3, count 0 2006.257.11:41:13.39#ibcon#read 4, iclass 3, count 0 2006.257.11:41:13.39#ibcon#about to read 5, iclass 3, count 0 2006.257.11:41:13.39#ibcon#read 5, iclass 3, count 0 2006.257.11:41:13.39#ibcon#about to read 6, iclass 3, count 0 2006.257.11:41:13.39#ibcon#read 6, iclass 3, count 0 2006.257.11:41:13.39#ibcon#end of sib2, iclass 3, count 0 2006.257.11:41:13.39#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:41:13.39#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:41:13.39#ibcon#[25=USB\r\n] 2006.257.11:41:13.39#ibcon#*before write, iclass 3, count 0 2006.257.11:41:13.39#ibcon#enter sib2, iclass 3, count 0 2006.257.11:41:13.39#ibcon#flushed, iclass 3, count 0 2006.257.11:41:13.39#ibcon#about to write, iclass 3, count 0 2006.257.11:41:13.39#ibcon#wrote, iclass 3, count 0 2006.257.11:41:13.39#ibcon#about to read 3, iclass 3, count 0 2006.257.11:41:13.42#ibcon#read 3, iclass 3, count 0 2006.257.11:41:13.42#ibcon#about to read 4, iclass 3, count 0 2006.257.11:41:13.42#ibcon#read 4, iclass 3, count 0 2006.257.11:41:13.42#ibcon#about to read 5, iclass 3, count 0 2006.257.11:41:13.42#ibcon#read 5, iclass 3, count 0 2006.257.11:41:13.42#ibcon#about to read 6, iclass 3, count 0 2006.257.11:41:13.42#ibcon#read 6, iclass 3, count 0 2006.257.11:41:13.42#ibcon#end of sib2, iclass 3, count 0 2006.257.11:41:13.42#ibcon#*after write, iclass 3, count 0 2006.257.11:41:13.42#ibcon#*before return 0, iclass 3, count 0 2006.257.11:41:13.42#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:13.42#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:13.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:41:13.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:41:13.42$vck44/valo=5,734.99 2006.257.11:41:13.42#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.11:41:13.42#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.11:41:13.42#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:13.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:13.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:13.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:13.42#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:41:13.42#ibcon#first serial, iclass 5, count 0 2006.257.11:41:13.42#ibcon#enter sib2, iclass 5, count 0 2006.257.11:41:13.42#ibcon#flushed, iclass 5, count 0 2006.257.11:41:13.42#ibcon#about to write, iclass 5, count 0 2006.257.11:41:13.42#ibcon#wrote, iclass 5, count 0 2006.257.11:41:13.42#ibcon#about to read 3, iclass 5, count 0 2006.257.11:41:13.44#ibcon#read 3, iclass 5, count 0 2006.257.11:41:13.44#ibcon#about to read 4, iclass 5, count 0 2006.257.11:41:13.44#ibcon#read 4, iclass 5, count 0 2006.257.11:41:13.44#ibcon#about to read 5, iclass 5, count 0 2006.257.11:41:13.44#ibcon#read 5, iclass 5, count 0 2006.257.11:41:13.44#ibcon#about to read 6, iclass 5, count 0 2006.257.11:41:13.44#ibcon#read 6, iclass 5, count 0 2006.257.11:41:13.44#ibcon#end of sib2, iclass 5, count 0 2006.257.11:41:13.44#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:41:13.44#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:41:13.44#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:41:13.44#ibcon#*before write, iclass 5, count 0 2006.257.11:41:13.44#ibcon#enter sib2, iclass 5, count 0 2006.257.11:41:13.44#ibcon#flushed, iclass 5, count 0 2006.257.11:41:13.44#ibcon#about to write, iclass 5, count 0 2006.257.11:41:13.44#ibcon#wrote, iclass 5, count 0 2006.257.11:41:13.44#ibcon#about to read 3, iclass 5, count 0 2006.257.11:41:13.48#ibcon#read 3, iclass 5, count 0 2006.257.11:41:13.48#ibcon#about to read 4, iclass 5, count 0 2006.257.11:41:13.48#ibcon#read 4, iclass 5, count 0 2006.257.11:41:13.48#ibcon#about to read 5, iclass 5, count 0 2006.257.11:41:13.48#ibcon#read 5, iclass 5, count 0 2006.257.11:41:13.48#ibcon#about to read 6, iclass 5, count 0 2006.257.11:41:14.57#ibcon#read 6, iclass 5, count 0 2006.257.11:41:14.58#ibcon#end of sib2, iclass 5, count 0 2006.257.11:41:14.58#ibcon#*after write, iclass 5, count 0 2006.257.11:41:14.58#ibcon#*before return 0, iclass 5, count 0 2006.257.11:41:14.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:14.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:14.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:41:14.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:41:14.58$vck44/va=5,4 2006.257.11:41:14.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.11:41:14.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.11:41:14.58#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:14.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:14.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:14.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:14.58#ibcon#enter wrdev, iclass 7, count 2 2006.257.11:41:14.58#ibcon#first serial, iclass 7, count 2 2006.257.11:41:14.58#ibcon#enter sib2, iclass 7, count 2 2006.257.11:41:14.58#ibcon#flushed, iclass 7, count 2 2006.257.11:41:14.58#ibcon#about to write, iclass 7, count 2 2006.257.11:41:14.58#ibcon#wrote, iclass 7, count 2 2006.257.11:41:14.58#ibcon#about to read 3, iclass 7, count 2 2006.257.11:41:14.60#ibcon#read 3, iclass 7, count 2 2006.257.11:41:14.60#ibcon#about to read 4, iclass 7, count 2 2006.257.11:41:14.60#ibcon#read 4, iclass 7, count 2 2006.257.11:41:14.60#ibcon#about to read 5, iclass 7, count 2 2006.257.11:41:14.60#ibcon#read 5, iclass 7, count 2 2006.257.11:41:14.60#ibcon#about to read 6, iclass 7, count 2 2006.257.11:41:14.60#ibcon#read 6, iclass 7, count 2 2006.257.11:41:14.60#ibcon#end of sib2, iclass 7, count 2 2006.257.11:41:14.60#ibcon#*mode == 0, iclass 7, count 2 2006.257.11:41:14.60#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.11:41:14.60#ibcon#[25=AT05-04\r\n] 2006.257.11:41:14.60#ibcon#*before write, iclass 7, count 2 2006.257.11:41:14.60#ibcon#enter sib2, iclass 7, count 2 2006.257.11:41:14.60#ibcon#flushed, iclass 7, count 2 2006.257.11:41:14.60#ibcon#about to write, iclass 7, count 2 2006.257.11:41:14.60#ibcon#wrote, iclass 7, count 2 2006.257.11:41:14.60#ibcon#about to read 3, iclass 7, count 2 2006.257.11:41:14.63#ibcon#read 3, iclass 7, count 2 2006.257.11:41:14.63#ibcon#about to read 4, iclass 7, count 2 2006.257.11:41:14.63#ibcon#read 4, iclass 7, count 2 2006.257.11:41:14.63#ibcon#about to read 5, iclass 7, count 2 2006.257.11:41:14.63#ibcon#read 5, iclass 7, count 2 2006.257.11:41:14.63#ibcon#about to read 6, iclass 7, count 2 2006.257.11:41:14.63#ibcon#read 6, iclass 7, count 2 2006.257.11:41:14.63#ibcon#end of sib2, iclass 7, count 2 2006.257.11:41:14.63#ibcon#*after write, iclass 7, count 2 2006.257.11:41:14.63#ibcon#*before return 0, iclass 7, count 2 2006.257.11:41:14.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:14.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:14.63#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.11:41:14.63#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:14.63#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:14.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:14.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:14.75#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:41:14.75#ibcon#first serial, iclass 7, count 0 2006.257.11:41:14.75#ibcon#enter sib2, iclass 7, count 0 2006.257.11:41:14.75#ibcon#flushed, iclass 7, count 0 2006.257.11:41:14.75#ibcon#about to write, iclass 7, count 0 2006.257.11:41:14.75#ibcon#wrote, iclass 7, count 0 2006.257.11:41:14.75#ibcon#about to read 3, iclass 7, count 0 2006.257.11:41:14.77#ibcon#read 3, iclass 7, count 0 2006.257.11:41:14.77#ibcon#about to read 4, iclass 7, count 0 2006.257.11:41:14.77#ibcon#read 4, iclass 7, count 0 2006.257.11:41:14.77#ibcon#about to read 5, iclass 7, count 0 2006.257.11:41:14.77#ibcon#read 5, iclass 7, count 0 2006.257.11:41:14.77#ibcon#about to read 6, iclass 7, count 0 2006.257.11:41:14.77#ibcon#read 6, iclass 7, count 0 2006.257.11:41:14.77#ibcon#end of sib2, iclass 7, count 0 2006.257.11:41:14.77#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:41:14.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:41:14.77#ibcon#[25=USB\r\n] 2006.257.11:41:14.77#ibcon#*before write, iclass 7, count 0 2006.257.11:41:14.77#ibcon#enter sib2, iclass 7, count 0 2006.257.11:41:14.77#ibcon#flushed, iclass 7, count 0 2006.257.11:41:14.77#ibcon#about to write, iclass 7, count 0 2006.257.11:41:14.77#ibcon#wrote, iclass 7, count 0 2006.257.11:41:14.77#ibcon#about to read 3, iclass 7, count 0 2006.257.11:41:14.80#ibcon#read 3, iclass 7, count 0 2006.257.11:41:14.80#ibcon#about to read 4, iclass 7, count 0 2006.257.11:41:14.80#ibcon#read 4, iclass 7, count 0 2006.257.11:41:14.80#ibcon#about to read 5, iclass 7, count 0 2006.257.11:41:14.80#ibcon#read 5, iclass 7, count 0 2006.257.11:41:14.80#ibcon#about to read 6, iclass 7, count 0 2006.257.11:41:14.80#ibcon#read 6, iclass 7, count 0 2006.257.11:41:14.80#ibcon#end of sib2, iclass 7, count 0 2006.257.11:41:14.80#ibcon#*after write, iclass 7, count 0 2006.257.11:41:14.80#ibcon#*before return 0, iclass 7, count 0 2006.257.11:41:14.80#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:14.80#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:14.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:41:14.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:41:14.80$vck44/valo=6,814.99 2006.257.11:41:14.80#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.11:41:14.80#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.11:41:14.80#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:14.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:14.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:14.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:14.80#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:41:14.80#ibcon#first serial, iclass 11, count 0 2006.257.11:41:14.80#ibcon#enter sib2, iclass 11, count 0 2006.257.11:41:14.80#ibcon#flushed, iclass 11, count 0 2006.257.11:41:14.80#ibcon#about to write, iclass 11, count 0 2006.257.11:41:14.80#ibcon#wrote, iclass 11, count 0 2006.257.11:41:14.80#ibcon#about to read 3, iclass 11, count 0 2006.257.11:41:14.82#ibcon#read 3, iclass 11, count 0 2006.257.11:41:14.82#ibcon#about to read 4, iclass 11, count 0 2006.257.11:41:14.82#ibcon#read 4, iclass 11, count 0 2006.257.11:41:14.82#ibcon#about to read 5, iclass 11, count 0 2006.257.11:41:14.82#ibcon#read 5, iclass 11, count 0 2006.257.11:41:14.82#ibcon#about to read 6, iclass 11, count 0 2006.257.11:41:14.82#ibcon#read 6, iclass 11, count 0 2006.257.11:41:14.82#ibcon#end of sib2, iclass 11, count 0 2006.257.11:41:14.82#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:41:14.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:41:14.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:41:14.82#ibcon#*before write, iclass 11, count 0 2006.257.11:41:14.82#ibcon#enter sib2, iclass 11, count 0 2006.257.11:41:14.82#ibcon#flushed, iclass 11, count 0 2006.257.11:41:14.82#ibcon#about to write, iclass 11, count 0 2006.257.11:41:14.82#ibcon#wrote, iclass 11, count 0 2006.257.11:41:14.82#ibcon#about to read 3, iclass 11, count 0 2006.257.11:41:14.86#ibcon#read 3, iclass 11, count 0 2006.257.11:41:14.86#ibcon#about to read 4, iclass 11, count 0 2006.257.11:41:14.86#ibcon#read 4, iclass 11, count 0 2006.257.11:41:14.86#ibcon#about to read 5, iclass 11, count 0 2006.257.11:41:14.86#ibcon#read 5, iclass 11, count 0 2006.257.11:41:14.86#ibcon#about to read 6, iclass 11, count 0 2006.257.11:41:14.86#ibcon#read 6, iclass 11, count 0 2006.257.11:41:14.86#ibcon#end of sib2, iclass 11, count 0 2006.257.11:41:14.86#ibcon#*after write, iclass 11, count 0 2006.257.11:41:14.86#ibcon#*before return 0, iclass 11, count 0 2006.257.11:41:14.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:14.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:14.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:41:14.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:41:14.86$vck44/va=6,4 2006.257.11:41:14.86#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.11:41:14.86#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.11:41:14.86#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:14.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:14.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:14.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:14.92#ibcon#enter wrdev, iclass 13, count 2 2006.257.11:41:14.92#ibcon#first serial, iclass 13, count 2 2006.257.11:41:14.92#ibcon#enter sib2, iclass 13, count 2 2006.257.11:41:14.92#ibcon#flushed, iclass 13, count 2 2006.257.11:41:14.92#ibcon#about to write, iclass 13, count 2 2006.257.11:41:14.92#ibcon#wrote, iclass 13, count 2 2006.257.11:41:14.92#ibcon#about to read 3, iclass 13, count 2 2006.257.11:41:14.94#ibcon#read 3, iclass 13, count 2 2006.257.11:41:14.94#ibcon#about to read 4, iclass 13, count 2 2006.257.11:41:14.94#ibcon#read 4, iclass 13, count 2 2006.257.11:41:14.94#ibcon#about to read 5, iclass 13, count 2 2006.257.11:41:14.94#ibcon#read 5, iclass 13, count 2 2006.257.11:41:14.94#ibcon#about to read 6, iclass 13, count 2 2006.257.11:41:14.94#ibcon#read 6, iclass 13, count 2 2006.257.11:41:14.94#ibcon#end of sib2, iclass 13, count 2 2006.257.11:41:14.94#ibcon#*mode == 0, iclass 13, count 2 2006.257.11:41:14.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.11:41:14.94#ibcon#[25=AT06-04\r\n] 2006.257.11:41:14.94#ibcon#*before write, iclass 13, count 2 2006.257.11:41:14.94#ibcon#enter sib2, iclass 13, count 2 2006.257.11:41:14.94#ibcon#flushed, iclass 13, count 2 2006.257.11:41:14.94#ibcon#about to write, iclass 13, count 2 2006.257.11:41:14.94#ibcon#wrote, iclass 13, count 2 2006.257.11:41:14.94#ibcon#about to read 3, iclass 13, count 2 2006.257.11:41:14.97#ibcon#read 3, iclass 13, count 2 2006.257.11:41:14.97#ibcon#about to read 4, iclass 13, count 2 2006.257.11:41:14.97#ibcon#read 4, iclass 13, count 2 2006.257.11:41:14.97#ibcon#about to read 5, iclass 13, count 2 2006.257.11:41:14.97#ibcon#read 5, iclass 13, count 2 2006.257.11:41:14.97#ibcon#about to read 6, iclass 13, count 2 2006.257.11:41:14.97#ibcon#read 6, iclass 13, count 2 2006.257.11:41:14.97#ibcon#end of sib2, iclass 13, count 2 2006.257.11:41:14.97#ibcon#*after write, iclass 13, count 2 2006.257.11:41:14.97#ibcon#*before return 0, iclass 13, count 2 2006.257.11:41:14.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:14.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:14.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.11:41:14.97#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:14.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:15.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:15.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:15.09#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:41:15.09#ibcon#first serial, iclass 13, count 0 2006.257.11:41:15.09#ibcon#enter sib2, iclass 13, count 0 2006.257.11:41:15.09#ibcon#flushed, iclass 13, count 0 2006.257.11:41:15.09#ibcon#about to write, iclass 13, count 0 2006.257.11:41:15.09#ibcon#wrote, iclass 13, count 0 2006.257.11:41:15.09#ibcon#about to read 3, iclass 13, count 0 2006.257.11:41:15.11#ibcon#read 3, iclass 13, count 0 2006.257.11:41:15.11#ibcon#about to read 4, iclass 13, count 0 2006.257.11:41:15.11#ibcon#read 4, iclass 13, count 0 2006.257.11:41:15.11#ibcon#about to read 5, iclass 13, count 0 2006.257.11:41:15.11#ibcon#read 5, iclass 13, count 0 2006.257.11:41:15.11#ibcon#about to read 6, iclass 13, count 0 2006.257.11:41:15.11#ibcon#read 6, iclass 13, count 0 2006.257.11:41:15.11#ibcon#end of sib2, iclass 13, count 0 2006.257.11:41:15.11#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:41:15.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:41:15.11#ibcon#[25=USB\r\n] 2006.257.11:41:15.11#ibcon#*before write, iclass 13, count 0 2006.257.11:41:15.11#ibcon#enter sib2, iclass 13, count 0 2006.257.11:41:15.11#ibcon#flushed, iclass 13, count 0 2006.257.11:41:15.11#ibcon#about to write, iclass 13, count 0 2006.257.11:41:15.11#ibcon#wrote, iclass 13, count 0 2006.257.11:41:15.11#ibcon#about to read 3, iclass 13, count 0 2006.257.11:41:15.14#ibcon#read 3, iclass 13, count 0 2006.257.11:41:15.14#ibcon#about to read 4, iclass 13, count 0 2006.257.11:41:15.14#ibcon#read 4, iclass 13, count 0 2006.257.11:41:15.14#ibcon#about to read 5, iclass 13, count 0 2006.257.11:41:15.14#ibcon#read 5, iclass 13, count 0 2006.257.11:41:15.14#ibcon#about to read 6, iclass 13, count 0 2006.257.11:41:15.14#ibcon#read 6, iclass 13, count 0 2006.257.11:41:15.14#ibcon#end of sib2, iclass 13, count 0 2006.257.11:41:15.14#ibcon#*after write, iclass 13, count 0 2006.257.11:41:15.14#ibcon#*before return 0, iclass 13, count 0 2006.257.11:41:15.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:15.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:15.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:41:15.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:41:15.14$vck44/valo=7,864.99 2006.257.11:41:15.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.11:41:15.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.11:41:15.14#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:15.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:15.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:15.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:15.14#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:41:15.14#ibcon#first serial, iclass 15, count 0 2006.257.11:41:15.14#ibcon#enter sib2, iclass 15, count 0 2006.257.11:41:15.14#ibcon#flushed, iclass 15, count 0 2006.257.11:41:15.14#ibcon#about to write, iclass 15, count 0 2006.257.11:41:15.14#ibcon#wrote, iclass 15, count 0 2006.257.11:41:15.14#ibcon#about to read 3, iclass 15, count 0 2006.257.11:41:15.16#ibcon#read 3, iclass 15, count 0 2006.257.11:41:15.16#ibcon#about to read 4, iclass 15, count 0 2006.257.11:41:15.16#ibcon#read 4, iclass 15, count 0 2006.257.11:41:15.16#ibcon#about to read 5, iclass 15, count 0 2006.257.11:41:15.16#ibcon#read 5, iclass 15, count 0 2006.257.11:41:15.16#ibcon#about to read 6, iclass 15, count 0 2006.257.11:41:15.16#ibcon#read 6, iclass 15, count 0 2006.257.11:41:15.16#ibcon#end of sib2, iclass 15, count 0 2006.257.11:41:15.16#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:41:15.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:41:15.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:41:15.16#ibcon#*before write, iclass 15, count 0 2006.257.11:41:15.16#ibcon#enter sib2, iclass 15, count 0 2006.257.11:41:15.16#ibcon#flushed, iclass 15, count 0 2006.257.11:41:15.16#ibcon#about to write, iclass 15, count 0 2006.257.11:41:15.16#ibcon#wrote, iclass 15, count 0 2006.257.11:41:15.16#ibcon#about to read 3, iclass 15, count 0 2006.257.11:41:15.20#ibcon#read 3, iclass 15, count 0 2006.257.11:41:15.20#ibcon#about to read 4, iclass 15, count 0 2006.257.11:41:15.20#ibcon#read 4, iclass 15, count 0 2006.257.11:41:15.20#ibcon#about to read 5, iclass 15, count 0 2006.257.11:41:15.20#ibcon#read 5, iclass 15, count 0 2006.257.11:41:15.20#ibcon#about to read 6, iclass 15, count 0 2006.257.11:41:15.20#ibcon#read 6, iclass 15, count 0 2006.257.11:41:15.20#ibcon#end of sib2, iclass 15, count 0 2006.257.11:41:15.20#ibcon#*after write, iclass 15, count 0 2006.257.11:41:15.20#ibcon#*before return 0, iclass 15, count 0 2006.257.11:41:15.20#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:15.20#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:15.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:41:15.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:41:15.20$vck44/va=7,4 2006.257.11:41:15.20#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.11:41:15.20#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.11:41:15.20#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:15.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:15.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:15.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:15.26#ibcon#enter wrdev, iclass 17, count 2 2006.257.11:41:15.26#ibcon#first serial, iclass 17, count 2 2006.257.11:41:15.26#ibcon#enter sib2, iclass 17, count 2 2006.257.11:41:15.26#ibcon#flushed, iclass 17, count 2 2006.257.11:41:15.26#ibcon#about to write, iclass 17, count 2 2006.257.11:41:15.26#ibcon#wrote, iclass 17, count 2 2006.257.11:41:15.26#ibcon#about to read 3, iclass 17, count 2 2006.257.11:41:15.28#ibcon#read 3, iclass 17, count 2 2006.257.11:41:15.28#ibcon#about to read 4, iclass 17, count 2 2006.257.11:41:15.28#ibcon#read 4, iclass 17, count 2 2006.257.11:41:15.28#ibcon#about to read 5, iclass 17, count 2 2006.257.11:41:15.28#ibcon#read 5, iclass 17, count 2 2006.257.11:41:15.28#ibcon#about to read 6, iclass 17, count 2 2006.257.11:41:15.28#ibcon#read 6, iclass 17, count 2 2006.257.11:41:15.28#ibcon#end of sib2, iclass 17, count 2 2006.257.11:41:15.28#ibcon#*mode == 0, iclass 17, count 2 2006.257.11:41:15.28#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.11:41:15.28#ibcon#[25=AT07-04\r\n] 2006.257.11:41:15.28#ibcon#*before write, iclass 17, count 2 2006.257.11:41:15.28#ibcon#enter sib2, iclass 17, count 2 2006.257.11:41:15.28#ibcon#flushed, iclass 17, count 2 2006.257.11:41:15.28#ibcon#about to write, iclass 17, count 2 2006.257.11:41:15.28#ibcon#wrote, iclass 17, count 2 2006.257.11:41:15.28#ibcon#about to read 3, iclass 17, count 2 2006.257.11:41:15.31#ibcon#read 3, iclass 17, count 2 2006.257.11:41:15.31#ibcon#about to read 4, iclass 17, count 2 2006.257.11:41:15.31#ibcon#read 4, iclass 17, count 2 2006.257.11:41:15.31#ibcon#about to read 5, iclass 17, count 2 2006.257.11:41:15.31#ibcon#read 5, iclass 17, count 2 2006.257.11:41:15.31#ibcon#about to read 6, iclass 17, count 2 2006.257.11:41:15.31#ibcon#read 6, iclass 17, count 2 2006.257.11:41:15.31#ibcon#end of sib2, iclass 17, count 2 2006.257.11:41:15.31#ibcon#*after write, iclass 17, count 2 2006.257.11:41:15.31#ibcon#*before return 0, iclass 17, count 2 2006.257.11:41:15.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:15.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:15.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.11:41:15.31#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:15.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:15.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:15.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:15.43#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:41:15.43#ibcon#first serial, iclass 17, count 0 2006.257.11:41:15.43#ibcon#enter sib2, iclass 17, count 0 2006.257.11:41:15.43#ibcon#flushed, iclass 17, count 0 2006.257.11:41:15.43#ibcon#about to write, iclass 17, count 0 2006.257.11:41:15.43#ibcon#wrote, iclass 17, count 0 2006.257.11:41:15.43#ibcon#about to read 3, iclass 17, count 0 2006.257.11:41:15.45#ibcon#read 3, iclass 17, count 0 2006.257.11:41:15.45#ibcon#about to read 4, iclass 17, count 0 2006.257.11:41:15.45#ibcon#read 4, iclass 17, count 0 2006.257.11:41:15.45#ibcon#about to read 5, iclass 17, count 0 2006.257.11:41:15.45#ibcon#read 5, iclass 17, count 0 2006.257.11:41:15.45#ibcon#about to read 6, iclass 17, count 0 2006.257.11:41:15.45#ibcon#read 6, iclass 17, count 0 2006.257.11:41:15.45#ibcon#end of sib2, iclass 17, count 0 2006.257.11:41:15.45#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:41:15.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:41:15.45#ibcon#[25=USB\r\n] 2006.257.11:41:15.45#ibcon#*before write, iclass 17, count 0 2006.257.11:41:15.45#ibcon#enter sib2, iclass 17, count 0 2006.257.11:41:15.45#ibcon#flushed, iclass 17, count 0 2006.257.11:41:15.45#ibcon#about to write, iclass 17, count 0 2006.257.11:41:15.45#ibcon#wrote, iclass 17, count 0 2006.257.11:41:15.45#ibcon#about to read 3, iclass 17, count 0 2006.257.11:41:15.48#ibcon#read 3, iclass 17, count 0 2006.257.11:41:15.48#ibcon#about to read 4, iclass 17, count 0 2006.257.11:41:15.48#ibcon#read 4, iclass 17, count 0 2006.257.11:41:15.48#ibcon#about to read 5, iclass 17, count 0 2006.257.11:41:15.48#ibcon#read 5, iclass 17, count 0 2006.257.11:41:15.48#ibcon#about to read 6, iclass 17, count 0 2006.257.11:41:15.48#ibcon#read 6, iclass 17, count 0 2006.257.11:41:15.48#ibcon#end of sib2, iclass 17, count 0 2006.257.11:41:15.48#ibcon#*after write, iclass 17, count 0 2006.257.11:41:15.48#ibcon#*before return 0, iclass 17, count 0 2006.257.11:41:15.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:15.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:15.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:41:15.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:41:15.48$vck44/valo=8,884.99 2006.257.11:41:15.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.11:41:15.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.11:41:15.48#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:15.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:15.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:15.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:15.48#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:41:15.48#ibcon#first serial, iclass 19, count 0 2006.257.11:41:15.48#ibcon#enter sib2, iclass 19, count 0 2006.257.11:41:15.48#ibcon#flushed, iclass 19, count 0 2006.257.11:41:15.48#ibcon#about to write, iclass 19, count 0 2006.257.11:41:15.48#ibcon#wrote, iclass 19, count 0 2006.257.11:41:15.48#ibcon#about to read 3, iclass 19, count 0 2006.257.11:41:15.50#ibcon#read 3, iclass 19, count 0 2006.257.11:41:15.50#ibcon#about to read 4, iclass 19, count 0 2006.257.11:41:15.50#ibcon#read 4, iclass 19, count 0 2006.257.11:41:15.50#ibcon#about to read 5, iclass 19, count 0 2006.257.11:41:15.50#ibcon#read 5, iclass 19, count 0 2006.257.11:41:15.50#ibcon#about to read 6, iclass 19, count 0 2006.257.11:41:15.50#ibcon#read 6, iclass 19, count 0 2006.257.11:41:15.50#ibcon#end of sib2, iclass 19, count 0 2006.257.11:41:15.50#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:41:15.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:41:15.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:41:15.50#ibcon#*before write, iclass 19, count 0 2006.257.11:41:15.50#ibcon#enter sib2, iclass 19, count 0 2006.257.11:41:15.50#ibcon#flushed, iclass 19, count 0 2006.257.11:41:15.50#ibcon#about to write, iclass 19, count 0 2006.257.11:41:15.50#ibcon#wrote, iclass 19, count 0 2006.257.11:41:15.50#ibcon#about to read 3, iclass 19, count 0 2006.257.11:41:15.54#ibcon#read 3, iclass 19, count 0 2006.257.11:41:15.54#ibcon#about to read 4, iclass 19, count 0 2006.257.11:41:15.54#ibcon#read 4, iclass 19, count 0 2006.257.11:41:15.54#ibcon#about to read 5, iclass 19, count 0 2006.257.11:41:15.54#ibcon#read 5, iclass 19, count 0 2006.257.11:41:15.54#ibcon#about to read 6, iclass 19, count 0 2006.257.11:41:15.54#ibcon#read 6, iclass 19, count 0 2006.257.11:41:15.54#ibcon#end of sib2, iclass 19, count 0 2006.257.11:41:15.54#ibcon#*after write, iclass 19, count 0 2006.257.11:41:15.54#ibcon#*before return 0, iclass 19, count 0 2006.257.11:41:15.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:15.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:15.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:41:15.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:41:15.54$vck44/va=8,4 2006.257.11:41:15.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.11:41:15.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.11:41:15.54#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:15.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:41:15.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:41:15.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:41:15.60#ibcon#enter wrdev, iclass 21, count 2 2006.257.11:41:15.60#ibcon#first serial, iclass 21, count 2 2006.257.11:41:15.60#ibcon#enter sib2, iclass 21, count 2 2006.257.11:41:15.60#ibcon#flushed, iclass 21, count 2 2006.257.11:41:15.60#ibcon#about to write, iclass 21, count 2 2006.257.11:41:15.60#ibcon#wrote, iclass 21, count 2 2006.257.11:41:15.60#ibcon#about to read 3, iclass 21, count 2 2006.257.11:41:15.62#ibcon#read 3, iclass 21, count 2 2006.257.11:41:15.62#ibcon#about to read 4, iclass 21, count 2 2006.257.11:41:15.62#ibcon#read 4, iclass 21, count 2 2006.257.11:41:15.62#ibcon#about to read 5, iclass 21, count 2 2006.257.11:41:15.62#ibcon#read 5, iclass 21, count 2 2006.257.11:41:15.62#ibcon#about to read 6, iclass 21, count 2 2006.257.11:41:15.62#ibcon#read 6, iclass 21, count 2 2006.257.11:41:15.62#ibcon#end of sib2, iclass 21, count 2 2006.257.11:41:15.62#ibcon#*mode == 0, iclass 21, count 2 2006.257.11:41:15.62#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.11:41:15.62#ibcon#[25=AT08-04\r\n] 2006.257.11:41:15.62#ibcon#*before write, iclass 21, count 2 2006.257.11:41:15.62#ibcon#enter sib2, iclass 21, count 2 2006.257.11:41:15.62#ibcon#flushed, iclass 21, count 2 2006.257.11:41:15.62#ibcon#about to write, iclass 21, count 2 2006.257.11:41:15.62#ibcon#wrote, iclass 21, count 2 2006.257.11:41:15.62#ibcon#about to read 3, iclass 21, count 2 2006.257.11:41:15.65#ibcon#read 3, iclass 21, count 2 2006.257.11:41:15.65#ibcon#about to read 4, iclass 21, count 2 2006.257.11:41:15.65#ibcon#read 4, iclass 21, count 2 2006.257.11:41:15.65#ibcon#about to read 5, iclass 21, count 2 2006.257.11:41:15.65#ibcon#read 5, iclass 21, count 2 2006.257.11:41:15.65#ibcon#about to read 6, iclass 21, count 2 2006.257.11:41:15.65#ibcon#read 6, iclass 21, count 2 2006.257.11:41:15.65#ibcon#end of sib2, iclass 21, count 2 2006.257.11:41:15.65#ibcon#*after write, iclass 21, count 2 2006.257.11:41:15.65#ibcon#*before return 0, iclass 21, count 2 2006.257.11:41:16.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:41:16.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:41:16.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.11:41:16.83#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:16.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:41:16.94#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:41:16.94#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:41:16.94#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:41:16.94#ibcon#first serial, iclass 21, count 0 2006.257.11:41:16.94#ibcon#enter sib2, iclass 21, count 0 2006.257.11:41:16.94#ibcon#flushed, iclass 21, count 0 2006.257.11:41:16.94#ibcon#about to write, iclass 21, count 0 2006.257.11:41:16.94#ibcon#wrote, iclass 21, count 0 2006.257.11:41:16.94#ibcon#about to read 3, iclass 21, count 0 2006.257.11:41:16.96#ibcon#read 3, iclass 21, count 0 2006.257.11:41:16.96#ibcon#about to read 4, iclass 21, count 0 2006.257.11:41:16.96#ibcon#read 4, iclass 21, count 0 2006.257.11:41:16.96#ibcon#about to read 5, iclass 21, count 0 2006.257.11:41:16.96#ibcon#read 5, iclass 21, count 0 2006.257.11:41:16.96#ibcon#about to read 6, iclass 21, count 0 2006.257.11:41:16.96#ibcon#read 6, iclass 21, count 0 2006.257.11:41:16.96#ibcon#end of sib2, iclass 21, count 0 2006.257.11:41:16.96#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:41:16.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:41:16.96#ibcon#[25=USB\r\n] 2006.257.11:41:16.96#ibcon#*before write, iclass 21, count 0 2006.257.11:41:16.96#ibcon#enter sib2, iclass 21, count 0 2006.257.11:41:16.96#ibcon#flushed, iclass 21, count 0 2006.257.11:41:16.96#ibcon#about to write, iclass 21, count 0 2006.257.11:41:16.96#ibcon#wrote, iclass 21, count 0 2006.257.11:41:16.96#ibcon#about to read 3, iclass 21, count 0 2006.257.11:41:16.99#ibcon#read 3, iclass 21, count 0 2006.257.11:41:16.99#ibcon#about to read 4, iclass 21, count 0 2006.257.11:41:16.99#ibcon#read 4, iclass 21, count 0 2006.257.11:41:16.99#ibcon#about to read 5, iclass 21, count 0 2006.257.11:41:16.99#ibcon#read 5, iclass 21, count 0 2006.257.11:41:16.99#ibcon#about to read 6, iclass 21, count 0 2006.257.11:41:16.99#ibcon#read 6, iclass 21, count 0 2006.257.11:41:16.99#ibcon#end of sib2, iclass 21, count 0 2006.257.11:41:16.99#ibcon#*after write, iclass 21, count 0 2006.257.11:41:16.99#ibcon#*before return 0, iclass 21, count 0 2006.257.11:41:16.99#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:41:16.99#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:41:16.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:41:16.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:41:16.99$vck44/vblo=1,629.99 2006.257.11:41:16.99#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.11:41:16.99#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.11:41:16.99#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:16.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:16.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:16.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:16.99#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:41:16.99#ibcon#first serial, iclass 23, count 0 2006.257.11:41:16.99#ibcon#enter sib2, iclass 23, count 0 2006.257.11:41:16.99#ibcon#flushed, iclass 23, count 0 2006.257.11:41:16.99#ibcon#about to write, iclass 23, count 0 2006.257.11:41:16.99#ibcon#wrote, iclass 23, count 0 2006.257.11:41:16.99#ibcon#about to read 3, iclass 23, count 0 2006.257.11:41:17.01#ibcon#read 3, iclass 23, count 0 2006.257.11:41:17.01#ibcon#about to read 4, iclass 23, count 0 2006.257.11:41:17.01#ibcon#read 4, iclass 23, count 0 2006.257.11:41:17.01#ibcon#about to read 5, iclass 23, count 0 2006.257.11:41:17.01#ibcon#read 5, iclass 23, count 0 2006.257.11:41:17.01#ibcon#about to read 6, iclass 23, count 0 2006.257.11:41:17.01#ibcon#read 6, iclass 23, count 0 2006.257.11:41:17.01#ibcon#end of sib2, iclass 23, count 0 2006.257.11:41:17.01#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:41:17.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:41:17.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:41:17.01#ibcon#*before write, iclass 23, count 0 2006.257.11:41:17.01#ibcon#enter sib2, iclass 23, count 0 2006.257.11:41:17.01#ibcon#flushed, iclass 23, count 0 2006.257.11:41:17.01#ibcon#about to write, iclass 23, count 0 2006.257.11:41:17.01#ibcon#wrote, iclass 23, count 0 2006.257.11:41:17.01#ibcon#about to read 3, iclass 23, count 0 2006.257.11:41:17.05#ibcon#read 3, iclass 23, count 0 2006.257.11:41:17.05#ibcon#about to read 4, iclass 23, count 0 2006.257.11:41:17.05#ibcon#read 4, iclass 23, count 0 2006.257.11:41:17.05#ibcon#about to read 5, iclass 23, count 0 2006.257.11:41:17.05#ibcon#read 5, iclass 23, count 0 2006.257.11:41:17.05#ibcon#about to read 6, iclass 23, count 0 2006.257.11:41:17.05#ibcon#read 6, iclass 23, count 0 2006.257.11:41:17.05#ibcon#end of sib2, iclass 23, count 0 2006.257.11:41:17.05#ibcon#*after write, iclass 23, count 0 2006.257.11:41:17.05#ibcon#*before return 0, iclass 23, count 0 2006.257.11:41:17.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:17.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:41:17.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:41:17.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:41:17.05$vck44/vb=1,4 2006.257.11:41:17.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.11:41:17.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.11:41:17.05#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:17.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:17.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:17.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:17.05#ibcon#enter wrdev, iclass 25, count 2 2006.257.11:41:17.05#ibcon#first serial, iclass 25, count 2 2006.257.11:41:17.05#ibcon#enter sib2, iclass 25, count 2 2006.257.11:41:17.05#ibcon#flushed, iclass 25, count 2 2006.257.11:41:17.05#ibcon#about to write, iclass 25, count 2 2006.257.11:41:17.05#ibcon#wrote, iclass 25, count 2 2006.257.11:41:17.05#ibcon#about to read 3, iclass 25, count 2 2006.257.11:41:17.07#ibcon#read 3, iclass 25, count 2 2006.257.11:41:17.07#ibcon#about to read 4, iclass 25, count 2 2006.257.11:41:17.07#ibcon#read 4, iclass 25, count 2 2006.257.11:41:17.07#ibcon#about to read 5, iclass 25, count 2 2006.257.11:41:17.07#ibcon#read 5, iclass 25, count 2 2006.257.11:41:17.07#ibcon#about to read 6, iclass 25, count 2 2006.257.11:41:17.07#ibcon#read 6, iclass 25, count 2 2006.257.11:41:17.07#ibcon#end of sib2, iclass 25, count 2 2006.257.11:41:17.07#ibcon#*mode == 0, iclass 25, count 2 2006.257.11:41:17.07#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.11:41:17.07#ibcon#[27=AT01-04\r\n] 2006.257.11:41:17.07#ibcon#*before write, iclass 25, count 2 2006.257.11:41:17.07#ibcon#enter sib2, iclass 25, count 2 2006.257.11:41:17.07#ibcon#flushed, iclass 25, count 2 2006.257.11:41:17.07#ibcon#about to write, iclass 25, count 2 2006.257.11:41:17.07#ibcon#wrote, iclass 25, count 2 2006.257.11:41:17.07#ibcon#about to read 3, iclass 25, count 2 2006.257.11:41:17.10#ibcon#read 3, iclass 25, count 2 2006.257.11:41:17.10#ibcon#about to read 4, iclass 25, count 2 2006.257.11:41:17.10#ibcon#read 4, iclass 25, count 2 2006.257.11:41:17.10#ibcon#about to read 5, iclass 25, count 2 2006.257.11:41:17.10#ibcon#read 5, iclass 25, count 2 2006.257.11:41:17.10#ibcon#about to read 6, iclass 25, count 2 2006.257.11:41:17.10#ibcon#read 6, iclass 25, count 2 2006.257.11:41:17.10#ibcon#end of sib2, iclass 25, count 2 2006.257.11:41:17.10#ibcon#*after write, iclass 25, count 2 2006.257.11:41:17.10#ibcon#*before return 0, iclass 25, count 2 2006.257.11:41:17.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:17.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:41:17.10#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.11:41:17.10#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:17.10#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:17.22#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:17.22#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:17.22#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:41:17.22#ibcon#first serial, iclass 25, count 0 2006.257.11:41:17.22#ibcon#enter sib2, iclass 25, count 0 2006.257.11:41:17.22#ibcon#flushed, iclass 25, count 0 2006.257.11:41:17.22#ibcon#about to write, iclass 25, count 0 2006.257.11:41:17.22#ibcon#wrote, iclass 25, count 0 2006.257.11:41:17.22#ibcon#about to read 3, iclass 25, count 0 2006.257.11:41:17.24#ibcon#read 3, iclass 25, count 0 2006.257.11:41:17.24#ibcon#about to read 4, iclass 25, count 0 2006.257.11:41:17.24#ibcon#read 4, iclass 25, count 0 2006.257.11:41:17.24#ibcon#about to read 5, iclass 25, count 0 2006.257.11:41:17.24#ibcon#read 5, iclass 25, count 0 2006.257.11:41:17.24#ibcon#about to read 6, iclass 25, count 0 2006.257.11:41:17.24#ibcon#read 6, iclass 25, count 0 2006.257.11:41:17.24#ibcon#end of sib2, iclass 25, count 0 2006.257.11:41:17.24#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:41:17.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:41:17.24#ibcon#[27=USB\r\n] 2006.257.11:41:17.24#ibcon#*before write, iclass 25, count 0 2006.257.11:41:17.24#ibcon#enter sib2, iclass 25, count 0 2006.257.11:41:17.24#ibcon#flushed, iclass 25, count 0 2006.257.11:41:17.24#ibcon#about to write, iclass 25, count 0 2006.257.11:41:17.24#ibcon#wrote, iclass 25, count 0 2006.257.11:41:17.24#ibcon#about to read 3, iclass 25, count 0 2006.257.11:41:17.27#ibcon#read 3, iclass 25, count 0 2006.257.11:41:17.27#ibcon#about to read 4, iclass 25, count 0 2006.257.11:41:17.27#ibcon#read 4, iclass 25, count 0 2006.257.11:41:17.27#ibcon#about to read 5, iclass 25, count 0 2006.257.11:41:17.27#ibcon#read 5, iclass 25, count 0 2006.257.11:41:17.27#ibcon#about to read 6, iclass 25, count 0 2006.257.11:41:17.27#ibcon#read 6, iclass 25, count 0 2006.257.11:41:17.27#ibcon#end of sib2, iclass 25, count 0 2006.257.11:41:17.27#ibcon#*after write, iclass 25, count 0 2006.257.11:41:17.27#ibcon#*before return 0, iclass 25, count 0 2006.257.11:41:17.27#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:17.27#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:41:17.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:41:17.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:41:17.27$vck44/vblo=2,634.99 2006.257.11:41:17.27#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.11:41:17.27#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.11:41:17.27#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:17.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:17.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:17.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:17.27#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:41:17.27#ibcon#first serial, iclass 27, count 0 2006.257.11:41:17.27#ibcon#enter sib2, iclass 27, count 0 2006.257.11:41:17.27#ibcon#flushed, iclass 27, count 0 2006.257.11:41:17.27#ibcon#about to write, iclass 27, count 0 2006.257.11:41:17.27#ibcon#wrote, iclass 27, count 0 2006.257.11:41:17.27#ibcon#about to read 3, iclass 27, count 0 2006.257.11:41:17.29#ibcon#read 3, iclass 27, count 0 2006.257.11:41:17.29#ibcon#about to read 4, iclass 27, count 0 2006.257.11:41:17.29#ibcon#read 4, iclass 27, count 0 2006.257.11:41:17.29#ibcon#about to read 5, iclass 27, count 0 2006.257.11:41:17.29#ibcon#read 5, iclass 27, count 0 2006.257.11:41:17.29#ibcon#about to read 6, iclass 27, count 0 2006.257.11:41:17.29#ibcon#read 6, iclass 27, count 0 2006.257.11:41:17.29#ibcon#end of sib2, iclass 27, count 0 2006.257.11:41:17.29#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:41:17.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:41:17.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:41:17.29#ibcon#*before write, iclass 27, count 0 2006.257.11:41:17.29#ibcon#enter sib2, iclass 27, count 0 2006.257.11:41:17.29#ibcon#flushed, iclass 27, count 0 2006.257.11:41:17.29#ibcon#about to write, iclass 27, count 0 2006.257.11:41:17.29#ibcon#wrote, iclass 27, count 0 2006.257.11:41:17.29#ibcon#about to read 3, iclass 27, count 0 2006.257.11:41:17.33#ibcon#read 3, iclass 27, count 0 2006.257.11:41:17.33#ibcon#about to read 4, iclass 27, count 0 2006.257.11:41:17.33#ibcon#read 4, iclass 27, count 0 2006.257.11:41:17.33#ibcon#about to read 5, iclass 27, count 0 2006.257.11:41:17.33#ibcon#read 5, iclass 27, count 0 2006.257.11:41:17.33#ibcon#about to read 6, iclass 27, count 0 2006.257.11:41:17.33#ibcon#read 6, iclass 27, count 0 2006.257.11:41:17.33#ibcon#end of sib2, iclass 27, count 0 2006.257.11:41:17.33#ibcon#*after write, iclass 27, count 0 2006.257.11:41:17.33#ibcon#*before return 0, iclass 27, count 0 2006.257.11:41:17.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:17.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:41:17.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:41:17.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:41:17.33$vck44/vb=2,5 2006.257.11:41:17.33#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.11:41:17.33#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.11:41:17.33#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:17.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:41:17.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:41:17.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:41:17.39#ibcon#enter wrdev, iclass 29, count 2 2006.257.11:41:17.39#ibcon#first serial, iclass 29, count 2 2006.257.11:41:17.39#ibcon#enter sib2, iclass 29, count 2 2006.257.11:41:17.39#ibcon#flushed, iclass 29, count 2 2006.257.11:41:17.39#ibcon#about to write, iclass 29, count 2 2006.257.11:41:17.39#ibcon#wrote, iclass 29, count 2 2006.257.11:41:17.39#ibcon#about to read 3, iclass 29, count 2 2006.257.11:41:17.41#ibcon#read 3, iclass 29, count 2 2006.257.11:41:17.41#ibcon#about to read 4, iclass 29, count 2 2006.257.11:41:17.41#ibcon#read 4, iclass 29, count 2 2006.257.11:41:17.41#ibcon#about to read 5, iclass 29, count 2 2006.257.11:41:17.41#ibcon#read 5, iclass 29, count 2 2006.257.11:41:17.41#ibcon#about to read 6, iclass 29, count 2 2006.257.11:41:17.41#ibcon#read 6, iclass 29, count 2 2006.257.11:41:17.41#ibcon#end of sib2, iclass 29, count 2 2006.257.11:41:17.41#ibcon#*mode == 0, iclass 29, count 2 2006.257.11:41:17.41#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.11:41:17.41#ibcon#[27=AT02-05\r\n] 2006.257.11:41:17.41#ibcon#*before write, iclass 29, count 2 2006.257.11:41:17.41#ibcon#enter sib2, iclass 29, count 2 2006.257.11:41:17.41#ibcon#flushed, iclass 29, count 2 2006.257.11:41:17.41#ibcon#about to write, iclass 29, count 2 2006.257.11:41:17.41#ibcon#wrote, iclass 29, count 2 2006.257.11:41:17.41#ibcon#about to read 3, iclass 29, count 2 2006.257.11:41:17.44#ibcon#read 3, iclass 29, count 2 2006.257.11:41:17.44#ibcon#about to read 4, iclass 29, count 2 2006.257.11:41:17.44#ibcon#read 4, iclass 29, count 2 2006.257.11:41:17.44#ibcon#about to read 5, iclass 29, count 2 2006.257.11:41:17.44#ibcon#read 5, iclass 29, count 2 2006.257.11:41:17.44#ibcon#about to read 6, iclass 29, count 2 2006.257.11:41:17.44#ibcon#read 6, iclass 29, count 2 2006.257.11:41:17.44#ibcon#end of sib2, iclass 29, count 2 2006.257.11:41:17.44#ibcon#*after write, iclass 29, count 2 2006.257.11:41:17.44#ibcon#*before return 0, iclass 29, count 2 2006.257.11:41:17.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:41:17.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:41:17.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.11:41:17.44#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:17.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:41:17.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:41:17.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:41:17.56#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:41:17.56#ibcon#first serial, iclass 29, count 0 2006.257.11:41:17.56#ibcon#enter sib2, iclass 29, count 0 2006.257.11:41:17.56#ibcon#flushed, iclass 29, count 0 2006.257.11:41:17.56#ibcon#about to write, iclass 29, count 0 2006.257.11:41:17.56#ibcon#wrote, iclass 29, count 0 2006.257.11:41:17.56#ibcon#about to read 3, iclass 29, count 0 2006.257.11:41:17.58#ibcon#read 3, iclass 29, count 0 2006.257.11:41:17.58#ibcon#about to read 4, iclass 29, count 0 2006.257.11:41:17.58#ibcon#read 4, iclass 29, count 0 2006.257.11:41:17.58#ibcon#about to read 5, iclass 29, count 0 2006.257.11:41:17.58#ibcon#read 5, iclass 29, count 0 2006.257.11:41:17.58#ibcon#about to read 6, iclass 29, count 0 2006.257.11:41:17.58#ibcon#read 6, iclass 29, count 0 2006.257.11:41:17.58#ibcon#end of sib2, iclass 29, count 0 2006.257.11:41:17.58#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:41:17.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:41:17.58#ibcon#[27=USB\r\n] 2006.257.11:41:17.58#ibcon#*before write, iclass 29, count 0 2006.257.11:41:17.58#ibcon#enter sib2, iclass 29, count 0 2006.257.11:41:17.58#ibcon#flushed, iclass 29, count 0 2006.257.11:41:17.58#ibcon#about to write, iclass 29, count 0 2006.257.11:41:17.58#ibcon#wrote, iclass 29, count 0 2006.257.11:41:17.58#ibcon#about to read 3, iclass 29, count 0 2006.257.11:41:17.61#ibcon#read 3, iclass 29, count 0 2006.257.11:41:17.61#ibcon#about to read 4, iclass 29, count 0 2006.257.11:41:17.61#ibcon#read 4, iclass 29, count 0 2006.257.11:41:17.61#ibcon#about to read 5, iclass 29, count 0 2006.257.11:41:17.61#ibcon#read 5, iclass 29, count 0 2006.257.11:41:17.61#ibcon#about to read 6, iclass 29, count 0 2006.257.11:41:17.61#ibcon#read 6, iclass 29, count 0 2006.257.11:41:17.61#ibcon#end of sib2, iclass 29, count 0 2006.257.11:41:17.61#ibcon#*after write, iclass 29, count 0 2006.257.11:41:17.61#ibcon#*before return 0, iclass 29, count 0 2006.257.11:41:17.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:41:17.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:41:17.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:41:17.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:41:17.61$vck44/vblo=3,649.99 2006.257.11:41:17.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.11:41:17.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.11:41:17.61#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:17.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:41:17.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:41:17.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:41:17.61#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:41:17.61#ibcon#first serial, iclass 31, count 0 2006.257.11:41:17.61#ibcon#enter sib2, iclass 31, count 0 2006.257.11:41:17.61#ibcon#flushed, iclass 31, count 0 2006.257.11:41:17.61#ibcon#about to write, iclass 31, count 0 2006.257.11:41:17.61#ibcon#wrote, iclass 31, count 0 2006.257.11:41:17.61#ibcon#about to read 3, iclass 31, count 0 2006.257.11:41:17.63#ibcon#read 3, iclass 31, count 0 2006.257.11:41:17.63#ibcon#about to read 4, iclass 31, count 0 2006.257.11:41:17.63#ibcon#read 4, iclass 31, count 0 2006.257.11:41:17.63#ibcon#about to read 5, iclass 31, count 0 2006.257.11:41:17.63#ibcon#read 5, iclass 31, count 0 2006.257.11:41:17.63#ibcon#about to read 6, iclass 31, count 0 2006.257.11:41:17.63#ibcon#read 6, iclass 31, count 0 2006.257.11:41:17.63#ibcon#end of sib2, iclass 31, count 0 2006.257.11:41:17.63#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:41:17.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:41:17.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:41:17.63#ibcon#*before write, iclass 31, count 0 2006.257.11:41:17.63#ibcon#enter sib2, iclass 31, count 0 2006.257.11:41:17.63#ibcon#flushed, iclass 31, count 0 2006.257.11:41:17.63#ibcon#about to write, iclass 31, count 0 2006.257.11:41:17.63#ibcon#wrote, iclass 31, count 0 2006.257.11:41:17.63#ibcon#about to read 3, iclass 31, count 0 2006.257.11:41:17.67#ibcon#read 3, iclass 31, count 0 2006.257.11:41:17.67#ibcon#about to read 4, iclass 31, count 0 2006.257.11:41:17.67#ibcon#read 4, iclass 31, count 0 2006.257.11:41:17.67#ibcon#about to read 5, iclass 31, count 0 2006.257.11:41:17.67#ibcon#read 5, iclass 31, count 0 2006.257.11:41:17.67#ibcon#about to read 6, iclass 31, count 0 2006.257.11:41:17.67#ibcon#read 6, iclass 31, count 0 2006.257.11:41:17.67#ibcon#end of sib2, iclass 31, count 0 2006.257.11:41:17.67#ibcon#*after write, iclass 31, count 0 2006.257.11:41:17.67#ibcon#*before return 0, iclass 31, count 0 2006.257.11:41:17.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:41:17.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:41:17.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:41:17.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:41:17.67$vck44/vb=3,4 2006.257.11:41:17.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.11:41:17.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.11:41:17.67#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:17.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:41:17.73#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:41:17.73#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:41:17.73#ibcon#enter wrdev, iclass 33, count 2 2006.257.11:41:17.73#ibcon#first serial, iclass 33, count 2 2006.257.11:41:17.73#ibcon#enter sib2, iclass 33, count 2 2006.257.11:41:17.73#ibcon#flushed, iclass 33, count 2 2006.257.11:41:17.73#ibcon#about to write, iclass 33, count 2 2006.257.11:41:17.73#ibcon#wrote, iclass 33, count 2 2006.257.11:41:17.73#ibcon#about to read 3, iclass 33, count 2 2006.257.11:41:17.75#ibcon#read 3, iclass 33, count 2 2006.257.11:41:17.75#ibcon#about to read 4, iclass 33, count 2 2006.257.11:41:17.75#ibcon#read 4, iclass 33, count 2 2006.257.11:41:17.75#ibcon#about to read 5, iclass 33, count 2 2006.257.11:41:17.75#ibcon#read 5, iclass 33, count 2 2006.257.11:41:17.75#ibcon#about to read 6, iclass 33, count 2 2006.257.11:41:17.75#ibcon#read 6, iclass 33, count 2 2006.257.11:41:17.75#ibcon#end of sib2, iclass 33, count 2 2006.257.11:41:17.75#ibcon#*mode == 0, iclass 33, count 2 2006.257.11:41:17.75#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.11:41:17.75#ibcon#[27=AT03-04\r\n] 2006.257.11:41:17.75#ibcon#*before write, iclass 33, count 2 2006.257.11:41:17.75#ibcon#enter sib2, iclass 33, count 2 2006.257.11:41:17.75#ibcon#flushed, iclass 33, count 2 2006.257.11:41:17.75#ibcon#about to write, iclass 33, count 2 2006.257.11:41:17.75#ibcon#wrote, iclass 33, count 2 2006.257.11:41:17.75#ibcon#about to read 3, iclass 33, count 2 2006.257.11:41:17.78#ibcon#read 3, iclass 33, count 2 2006.257.11:41:17.78#ibcon#about to read 4, iclass 33, count 2 2006.257.11:41:17.78#ibcon#read 4, iclass 33, count 2 2006.257.11:41:17.78#ibcon#about to read 5, iclass 33, count 2 2006.257.11:41:17.78#ibcon#read 5, iclass 33, count 2 2006.257.11:41:17.78#ibcon#about to read 6, iclass 33, count 2 2006.257.11:41:17.78#ibcon#read 6, iclass 33, count 2 2006.257.11:41:17.78#ibcon#end of sib2, iclass 33, count 2 2006.257.11:41:17.78#ibcon#*after write, iclass 33, count 2 2006.257.11:41:17.78#ibcon#*before return 0, iclass 33, count 2 2006.257.11:41:17.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:41:17.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:41:17.78#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.11:41:17.78#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:17.78#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:41:17.90#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:41:17.90#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:41:17.90#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:41:17.90#ibcon#first serial, iclass 33, count 0 2006.257.11:41:17.90#ibcon#enter sib2, iclass 33, count 0 2006.257.11:41:17.90#ibcon#flushed, iclass 33, count 0 2006.257.11:41:17.90#ibcon#about to write, iclass 33, count 0 2006.257.11:41:17.90#ibcon#wrote, iclass 33, count 0 2006.257.11:41:17.90#ibcon#about to read 3, iclass 33, count 0 2006.257.11:41:17.92#ibcon#read 3, iclass 33, count 0 2006.257.11:41:17.92#ibcon#about to read 4, iclass 33, count 0 2006.257.11:41:17.92#ibcon#read 4, iclass 33, count 0 2006.257.11:41:17.92#ibcon#about to read 5, iclass 33, count 0 2006.257.11:41:17.92#ibcon#read 5, iclass 33, count 0 2006.257.11:41:17.92#ibcon#about to read 6, iclass 33, count 0 2006.257.11:41:17.92#ibcon#read 6, iclass 33, count 0 2006.257.11:41:17.92#ibcon#end of sib2, iclass 33, count 0 2006.257.11:41:17.92#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:41:17.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:41:17.92#ibcon#[27=USB\r\n] 2006.257.11:41:17.92#ibcon#*before write, iclass 33, count 0 2006.257.11:41:17.92#ibcon#enter sib2, iclass 33, count 0 2006.257.11:41:17.92#ibcon#flushed, iclass 33, count 0 2006.257.11:41:17.92#ibcon#about to write, iclass 33, count 0 2006.257.11:41:17.92#ibcon#wrote, iclass 33, count 0 2006.257.11:41:17.92#ibcon#about to read 3, iclass 33, count 0 2006.257.11:41:17.95#ibcon#read 3, iclass 33, count 0 2006.257.11:41:17.95#ibcon#about to read 4, iclass 33, count 0 2006.257.11:41:17.95#ibcon#read 4, iclass 33, count 0 2006.257.11:41:17.95#ibcon#about to read 5, iclass 33, count 0 2006.257.11:41:17.95#ibcon#read 5, iclass 33, count 0 2006.257.11:41:17.95#ibcon#about to read 6, iclass 33, count 0 2006.257.11:41:17.95#ibcon#read 6, iclass 33, count 0 2006.257.11:41:17.95#ibcon#end of sib2, iclass 33, count 0 2006.257.11:41:17.95#ibcon#*after write, iclass 33, count 0 2006.257.11:41:17.95#ibcon#*before return 0, iclass 33, count 0 2006.257.11:41:17.95#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:41:17.95#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:41:17.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:41:17.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:41:17.95$vck44/vblo=4,679.99 2006.257.11:41:17.95#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.11:41:17.95#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.11:41:17.95#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:17.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:17.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:17.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:17.95#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:41:17.95#ibcon#first serial, iclass 35, count 0 2006.257.11:41:17.95#ibcon#enter sib2, iclass 35, count 0 2006.257.11:41:17.95#ibcon#flushed, iclass 35, count 0 2006.257.11:41:19.08#ibcon#about to write, iclass 35, count 0 2006.257.11:41:19.08#ibcon#wrote, iclass 35, count 0 2006.257.11:41:19.08#ibcon#about to read 3, iclass 35, count 0 2006.257.11:41:19.09#ibcon#read 3, iclass 35, count 0 2006.257.11:41:19.09#ibcon#about to read 4, iclass 35, count 0 2006.257.11:41:19.09#ibcon#read 4, iclass 35, count 0 2006.257.11:41:19.09#ibcon#about to read 5, iclass 35, count 0 2006.257.11:41:19.09#ibcon#read 5, iclass 35, count 0 2006.257.11:41:19.09#ibcon#about to read 6, iclass 35, count 0 2006.257.11:41:19.09#ibcon#read 6, iclass 35, count 0 2006.257.11:41:19.09#ibcon#end of sib2, iclass 35, count 0 2006.257.11:41:19.09#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:41:19.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:41:19.09#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:41:19.09#ibcon#*before write, iclass 35, count 0 2006.257.11:41:19.09#ibcon#enter sib2, iclass 35, count 0 2006.257.11:41:19.09#ibcon#flushed, iclass 35, count 0 2006.257.11:41:19.09#ibcon#about to write, iclass 35, count 0 2006.257.11:41:19.09#ibcon#wrote, iclass 35, count 0 2006.257.11:41:19.09#ibcon#about to read 3, iclass 35, count 0 2006.257.11:41:19.13#ibcon#read 3, iclass 35, count 0 2006.257.11:41:19.13#ibcon#about to read 4, iclass 35, count 0 2006.257.11:41:19.13#ibcon#read 4, iclass 35, count 0 2006.257.11:41:19.13#ibcon#about to read 5, iclass 35, count 0 2006.257.11:41:19.13#ibcon#read 5, iclass 35, count 0 2006.257.11:41:19.13#ibcon#about to read 6, iclass 35, count 0 2006.257.11:41:19.13#ibcon#read 6, iclass 35, count 0 2006.257.11:41:19.13#ibcon#end of sib2, iclass 35, count 0 2006.257.11:41:19.13#ibcon#*after write, iclass 35, count 0 2006.257.11:41:19.13#ibcon#*before return 0, iclass 35, count 0 2006.257.11:41:19.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:19.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:41:19.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:41:19.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:41:19.13$vck44/vb=4,5 2006.257.11:41:19.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.11:41:19.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.11:41:19.13#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:19.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:19.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:19.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:19.13#ibcon#enter wrdev, iclass 37, count 2 2006.257.11:41:19.13#ibcon#first serial, iclass 37, count 2 2006.257.11:41:19.13#ibcon#enter sib2, iclass 37, count 2 2006.257.11:41:19.13#ibcon#flushed, iclass 37, count 2 2006.257.11:41:19.13#ibcon#about to write, iclass 37, count 2 2006.257.11:41:19.13#ibcon#wrote, iclass 37, count 2 2006.257.11:41:19.13#ibcon#about to read 3, iclass 37, count 2 2006.257.11:41:19.15#ibcon#read 3, iclass 37, count 2 2006.257.11:41:19.15#ibcon#about to read 4, iclass 37, count 2 2006.257.11:41:19.15#ibcon#read 4, iclass 37, count 2 2006.257.11:41:19.15#ibcon#about to read 5, iclass 37, count 2 2006.257.11:41:19.15#ibcon#read 5, iclass 37, count 2 2006.257.11:41:19.15#ibcon#about to read 6, iclass 37, count 2 2006.257.11:41:19.15#ibcon#read 6, iclass 37, count 2 2006.257.11:41:19.15#ibcon#end of sib2, iclass 37, count 2 2006.257.11:41:19.15#ibcon#*mode == 0, iclass 37, count 2 2006.257.11:41:19.15#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.11:41:19.15#ibcon#[27=AT04-05\r\n] 2006.257.11:41:19.15#ibcon#*before write, iclass 37, count 2 2006.257.11:41:19.15#ibcon#enter sib2, iclass 37, count 2 2006.257.11:41:19.15#ibcon#flushed, iclass 37, count 2 2006.257.11:41:19.15#ibcon#about to write, iclass 37, count 2 2006.257.11:41:19.15#ibcon#wrote, iclass 37, count 2 2006.257.11:41:19.15#ibcon#about to read 3, iclass 37, count 2 2006.257.11:41:19.18#ibcon#read 3, iclass 37, count 2 2006.257.11:41:19.18#ibcon#about to read 4, iclass 37, count 2 2006.257.11:41:19.18#ibcon#read 4, iclass 37, count 2 2006.257.11:41:19.18#ibcon#about to read 5, iclass 37, count 2 2006.257.11:41:19.18#ibcon#read 5, iclass 37, count 2 2006.257.11:41:19.18#ibcon#about to read 6, iclass 37, count 2 2006.257.11:41:19.18#ibcon#read 6, iclass 37, count 2 2006.257.11:41:19.18#ibcon#end of sib2, iclass 37, count 2 2006.257.11:41:19.18#ibcon#*after write, iclass 37, count 2 2006.257.11:41:19.18#ibcon#*before return 0, iclass 37, count 2 2006.257.11:41:19.18#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:19.18#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:41:19.18#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.11:41:19.18#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:19.18#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:19.30#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:19.30#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:19.30#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:41:19.30#ibcon#first serial, iclass 37, count 0 2006.257.11:41:19.30#ibcon#enter sib2, iclass 37, count 0 2006.257.11:41:19.30#ibcon#flushed, iclass 37, count 0 2006.257.11:41:19.30#ibcon#about to write, iclass 37, count 0 2006.257.11:41:19.30#ibcon#wrote, iclass 37, count 0 2006.257.11:41:19.30#ibcon#about to read 3, iclass 37, count 0 2006.257.11:41:19.32#ibcon#read 3, iclass 37, count 0 2006.257.11:41:19.32#ibcon#about to read 4, iclass 37, count 0 2006.257.11:41:19.32#ibcon#read 4, iclass 37, count 0 2006.257.11:41:19.32#ibcon#about to read 5, iclass 37, count 0 2006.257.11:41:19.32#ibcon#read 5, iclass 37, count 0 2006.257.11:41:19.32#ibcon#about to read 6, iclass 37, count 0 2006.257.11:41:19.32#ibcon#read 6, iclass 37, count 0 2006.257.11:41:19.32#ibcon#end of sib2, iclass 37, count 0 2006.257.11:41:19.32#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:41:19.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:41:19.32#ibcon#[27=USB\r\n] 2006.257.11:41:19.32#ibcon#*before write, iclass 37, count 0 2006.257.11:41:19.32#ibcon#enter sib2, iclass 37, count 0 2006.257.11:41:19.32#ibcon#flushed, iclass 37, count 0 2006.257.11:41:19.32#ibcon#about to write, iclass 37, count 0 2006.257.11:41:19.32#ibcon#wrote, iclass 37, count 0 2006.257.11:41:19.32#ibcon#about to read 3, iclass 37, count 0 2006.257.11:41:19.35#ibcon#read 3, iclass 37, count 0 2006.257.11:41:19.35#ibcon#about to read 4, iclass 37, count 0 2006.257.11:41:19.35#ibcon#read 4, iclass 37, count 0 2006.257.11:41:19.35#ibcon#about to read 5, iclass 37, count 0 2006.257.11:41:19.35#ibcon#read 5, iclass 37, count 0 2006.257.11:41:19.35#ibcon#about to read 6, iclass 37, count 0 2006.257.11:41:19.35#ibcon#read 6, iclass 37, count 0 2006.257.11:41:19.35#ibcon#end of sib2, iclass 37, count 0 2006.257.11:41:19.35#ibcon#*after write, iclass 37, count 0 2006.257.11:41:19.35#ibcon#*before return 0, iclass 37, count 0 2006.257.11:41:19.35#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:19.35#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:41:19.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:41:19.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:41:19.35$vck44/vblo=5,709.99 2006.257.11:41:19.35#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.11:41:19.35#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.11:41:19.35#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:19.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:19.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:19.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:19.35#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:41:19.35#ibcon#first serial, iclass 39, count 0 2006.257.11:41:19.35#ibcon#enter sib2, iclass 39, count 0 2006.257.11:41:19.35#ibcon#flushed, iclass 39, count 0 2006.257.11:41:19.35#ibcon#about to write, iclass 39, count 0 2006.257.11:41:19.35#ibcon#wrote, iclass 39, count 0 2006.257.11:41:19.35#ibcon#about to read 3, iclass 39, count 0 2006.257.11:41:19.37#ibcon#read 3, iclass 39, count 0 2006.257.11:41:19.37#ibcon#about to read 4, iclass 39, count 0 2006.257.11:41:19.37#ibcon#read 4, iclass 39, count 0 2006.257.11:41:19.37#ibcon#about to read 5, iclass 39, count 0 2006.257.11:41:19.37#ibcon#read 5, iclass 39, count 0 2006.257.11:41:19.37#ibcon#about to read 6, iclass 39, count 0 2006.257.11:41:19.37#ibcon#read 6, iclass 39, count 0 2006.257.11:41:19.37#ibcon#end of sib2, iclass 39, count 0 2006.257.11:41:19.37#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:41:19.37#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:41:19.37#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:41:19.37#ibcon#*before write, iclass 39, count 0 2006.257.11:41:19.37#ibcon#enter sib2, iclass 39, count 0 2006.257.11:41:19.37#ibcon#flushed, iclass 39, count 0 2006.257.11:41:19.37#ibcon#about to write, iclass 39, count 0 2006.257.11:41:19.37#ibcon#wrote, iclass 39, count 0 2006.257.11:41:19.37#ibcon#about to read 3, iclass 39, count 0 2006.257.11:41:19.41#ibcon#read 3, iclass 39, count 0 2006.257.11:41:19.41#ibcon#about to read 4, iclass 39, count 0 2006.257.11:41:19.41#ibcon#read 4, iclass 39, count 0 2006.257.11:41:19.41#ibcon#about to read 5, iclass 39, count 0 2006.257.11:41:19.41#ibcon#read 5, iclass 39, count 0 2006.257.11:41:19.41#ibcon#about to read 6, iclass 39, count 0 2006.257.11:41:19.41#ibcon#read 6, iclass 39, count 0 2006.257.11:41:19.41#ibcon#end of sib2, iclass 39, count 0 2006.257.11:41:19.41#ibcon#*after write, iclass 39, count 0 2006.257.11:41:19.41#ibcon#*before return 0, iclass 39, count 0 2006.257.11:41:19.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:19.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:41:19.41#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:41:19.41#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:41:19.41$vck44/vb=5,4 2006.257.11:41:19.41#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.11:41:19.41#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.11:41:19.41#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:19.41#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:19.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:19.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:19.47#ibcon#enter wrdev, iclass 3, count 2 2006.257.11:41:19.47#ibcon#first serial, iclass 3, count 2 2006.257.11:41:19.47#ibcon#enter sib2, iclass 3, count 2 2006.257.11:41:19.47#ibcon#flushed, iclass 3, count 2 2006.257.11:41:19.47#ibcon#about to write, iclass 3, count 2 2006.257.11:41:19.47#ibcon#wrote, iclass 3, count 2 2006.257.11:41:19.47#ibcon#about to read 3, iclass 3, count 2 2006.257.11:41:19.49#ibcon#read 3, iclass 3, count 2 2006.257.11:41:19.49#ibcon#about to read 4, iclass 3, count 2 2006.257.11:41:19.49#ibcon#read 4, iclass 3, count 2 2006.257.11:41:19.49#ibcon#about to read 5, iclass 3, count 2 2006.257.11:41:19.49#ibcon#read 5, iclass 3, count 2 2006.257.11:41:19.49#ibcon#about to read 6, iclass 3, count 2 2006.257.11:41:19.49#ibcon#read 6, iclass 3, count 2 2006.257.11:41:19.49#ibcon#end of sib2, iclass 3, count 2 2006.257.11:41:19.49#ibcon#*mode == 0, iclass 3, count 2 2006.257.11:41:19.49#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.11:41:19.49#ibcon#[27=AT05-04\r\n] 2006.257.11:41:19.49#ibcon#*before write, iclass 3, count 2 2006.257.11:41:19.49#ibcon#enter sib2, iclass 3, count 2 2006.257.11:41:19.49#ibcon#flushed, iclass 3, count 2 2006.257.11:41:19.49#ibcon#about to write, iclass 3, count 2 2006.257.11:41:19.49#ibcon#wrote, iclass 3, count 2 2006.257.11:41:19.49#ibcon#about to read 3, iclass 3, count 2 2006.257.11:41:19.52#ibcon#read 3, iclass 3, count 2 2006.257.11:41:19.52#ibcon#about to read 4, iclass 3, count 2 2006.257.11:41:19.52#ibcon#read 4, iclass 3, count 2 2006.257.11:41:19.52#ibcon#about to read 5, iclass 3, count 2 2006.257.11:41:19.52#ibcon#read 5, iclass 3, count 2 2006.257.11:41:19.52#ibcon#about to read 6, iclass 3, count 2 2006.257.11:41:19.52#ibcon#read 6, iclass 3, count 2 2006.257.11:41:19.52#ibcon#end of sib2, iclass 3, count 2 2006.257.11:41:19.52#ibcon#*after write, iclass 3, count 2 2006.257.11:41:19.52#ibcon#*before return 0, iclass 3, count 2 2006.257.11:41:19.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:19.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:41:19.52#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.11:41:19.52#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:19.52#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:19.64#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:19.64#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:19.64#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:41:19.64#ibcon#first serial, iclass 3, count 0 2006.257.11:41:19.64#ibcon#enter sib2, iclass 3, count 0 2006.257.11:41:19.64#ibcon#flushed, iclass 3, count 0 2006.257.11:41:19.64#ibcon#about to write, iclass 3, count 0 2006.257.11:41:19.64#ibcon#wrote, iclass 3, count 0 2006.257.11:41:19.64#ibcon#about to read 3, iclass 3, count 0 2006.257.11:41:19.66#ibcon#read 3, iclass 3, count 0 2006.257.11:41:19.66#ibcon#about to read 4, iclass 3, count 0 2006.257.11:41:19.66#ibcon#read 4, iclass 3, count 0 2006.257.11:41:19.66#ibcon#about to read 5, iclass 3, count 0 2006.257.11:41:19.66#ibcon#read 5, iclass 3, count 0 2006.257.11:41:19.66#ibcon#about to read 6, iclass 3, count 0 2006.257.11:41:19.66#ibcon#read 6, iclass 3, count 0 2006.257.11:41:19.66#ibcon#end of sib2, iclass 3, count 0 2006.257.11:41:19.66#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:41:19.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:41:19.66#ibcon#[27=USB\r\n] 2006.257.11:41:19.66#ibcon#*before write, iclass 3, count 0 2006.257.11:41:19.66#ibcon#enter sib2, iclass 3, count 0 2006.257.11:41:19.66#ibcon#flushed, iclass 3, count 0 2006.257.11:41:19.66#ibcon#about to write, iclass 3, count 0 2006.257.11:41:19.66#ibcon#wrote, iclass 3, count 0 2006.257.11:41:19.66#ibcon#about to read 3, iclass 3, count 0 2006.257.11:41:19.69#ibcon#read 3, iclass 3, count 0 2006.257.11:41:19.69#ibcon#about to read 4, iclass 3, count 0 2006.257.11:41:19.69#ibcon#read 4, iclass 3, count 0 2006.257.11:41:19.69#ibcon#about to read 5, iclass 3, count 0 2006.257.11:41:19.69#ibcon#read 5, iclass 3, count 0 2006.257.11:41:19.69#ibcon#about to read 6, iclass 3, count 0 2006.257.11:41:19.69#ibcon#read 6, iclass 3, count 0 2006.257.11:41:19.69#ibcon#end of sib2, iclass 3, count 0 2006.257.11:41:19.69#ibcon#*after write, iclass 3, count 0 2006.257.11:41:19.69#ibcon#*before return 0, iclass 3, count 0 2006.257.11:41:19.69#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:19.69#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:41:19.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:41:19.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:41:19.69$vck44/vblo=6,719.99 2006.257.11:41:19.69#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.11:41:19.69#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.11:41:19.69#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:19.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:19.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:19.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:19.69#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:41:19.69#ibcon#first serial, iclass 5, count 0 2006.257.11:41:19.69#ibcon#enter sib2, iclass 5, count 0 2006.257.11:41:19.69#ibcon#flushed, iclass 5, count 0 2006.257.11:41:19.69#ibcon#about to write, iclass 5, count 0 2006.257.11:41:19.69#ibcon#wrote, iclass 5, count 0 2006.257.11:41:19.69#ibcon#about to read 3, iclass 5, count 0 2006.257.11:41:19.71#ibcon#read 3, iclass 5, count 0 2006.257.11:41:19.71#ibcon#about to read 4, iclass 5, count 0 2006.257.11:41:19.71#ibcon#read 4, iclass 5, count 0 2006.257.11:41:19.71#ibcon#about to read 5, iclass 5, count 0 2006.257.11:41:19.71#ibcon#read 5, iclass 5, count 0 2006.257.11:41:19.71#ibcon#about to read 6, iclass 5, count 0 2006.257.11:41:19.71#ibcon#read 6, iclass 5, count 0 2006.257.11:41:19.71#ibcon#end of sib2, iclass 5, count 0 2006.257.11:41:19.71#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:41:19.71#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:41:19.71#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:41:19.71#ibcon#*before write, iclass 5, count 0 2006.257.11:41:19.71#ibcon#enter sib2, iclass 5, count 0 2006.257.11:41:19.71#ibcon#flushed, iclass 5, count 0 2006.257.11:41:19.71#ibcon#about to write, iclass 5, count 0 2006.257.11:41:19.71#ibcon#wrote, iclass 5, count 0 2006.257.11:41:19.71#ibcon#about to read 3, iclass 5, count 0 2006.257.11:41:19.75#ibcon#read 3, iclass 5, count 0 2006.257.11:41:19.75#ibcon#about to read 4, iclass 5, count 0 2006.257.11:41:19.75#ibcon#read 4, iclass 5, count 0 2006.257.11:41:19.75#ibcon#about to read 5, iclass 5, count 0 2006.257.11:41:19.75#ibcon#read 5, iclass 5, count 0 2006.257.11:41:19.75#ibcon#about to read 6, iclass 5, count 0 2006.257.11:41:19.75#ibcon#read 6, iclass 5, count 0 2006.257.11:41:19.75#ibcon#end of sib2, iclass 5, count 0 2006.257.11:41:19.75#ibcon#*after write, iclass 5, count 0 2006.257.11:41:19.75#ibcon#*before return 0, iclass 5, count 0 2006.257.11:41:19.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:19.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:41:19.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:41:19.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:41:19.75$vck44/vb=6,4 2006.257.11:41:19.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.11:41:19.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.11:41:19.75#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:19.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:19.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:19.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:19.81#ibcon#enter wrdev, iclass 7, count 2 2006.257.11:41:19.81#ibcon#first serial, iclass 7, count 2 2006.257.11:41:19.81#ibcon#enter sib2, iclass 7, count 2 2006.257.11:41:19.81#ibcon#flushed, iclass 7, count 2 2006.257.11:41:19.81#ibcon#about to write, iclass 7, count 2 2006.257.11:41:19.81#ibcon#wrote, iclass 7, count 2 2006.257.11:41:19.81#ibcon#about to read 3, iclass 7, count 2 2006.257.11:41:19.83#ibcon#read 3, iclass 7, count 2 2006.257.11:41:19.83#ibcon#about to read 4, iclass 7, count 2 2006.257.11:41:19.83#ibcon#read 4, iclass 7, count 2 2006.257.11:41:19.83#ibcon#about to read 5, iclass 7, count 2 2006.257.11:41:19.83#ibcon#read 5, iclass 7, count 2 2006.257.11:41:19.83#ibcon#about to read 6, iclass 7, count 2 2006.257.11:41:19.83#ibcon#read 6, iclass 7, count 2 2006.257.11:41:19.83#ibcon#end of sib2, iclass 7, count 2 2006.257.11:41:19.83#ibcon#*mode == 0, iclass 7, count 2 2006.257.11:41:19.83#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.11:41:19.83#ibcon#[27=AT06-04\r\n] 2006.257.11:41:19.83#ibcon#*before write, iclass 7, count 2 2006.257.11:41:19.83#ibcon#enter sib2, iclass 7, count 2 2006.257.11:41:19.83#ibcon#flushed, iclass 7, count 2 2006.257.11:41:19.83#ibcon#about to write, iclass 7, count 2 2006.257.11:41:19.83#ibcon#wrote, iclass 7, count 2 2006.257.11:41:19.83#ibcon#about to read 3, iclass 7, count 2 2006.257.11:41:19.86#ibcon#read 3, iclass 7, count 2 2006.257.11:41:19.86#ibcon#about to read 4, iclass 7, count 2 2006.257.11:41:19.86#ibcon#read 4, iclass 7, count 2 2006.257.11:41:19.86#ibcon#about to read 5, iclass 7, count 2 2006.257.11:41:19.86#ibcon#read 5, iclass 7, count 2 2006.257.11:41:19.86#ibcon#about to read 6, iclass 7, count 2 2006.257.11:41:19.86#ibcon#read 6, iclass 7, count 2 2006.257.11:41:19.86#ibcon#end of sib2, iclass 7, count 2 2006.257.11:41:19.86#ibcon#*after write, iclass 7, count 2 2006.257.11:41:19.86#ibcon#*before return 0, iclass 7, count 2 2006.257.11:41:19.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:19.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:41:19.86#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.11:41:19.86#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:19.86#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:19.98#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:19.98#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:19.98#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:41:19.98#ibcon#first serial, iclass 7, count 0 2006.257.11:41:19.98#ibcon#enter sib2, iclass 7, count 0 2006.257.11:41:19.98#ibcon#flushed, iclass 7, count 0 2006.257.11:41:19.98#ibcon#about to write, iclass 7, count 0 2006.257.11:41:19.98#ibcon#wrote, iclass 7, count 0 2006.257.11:41:19.98#ibcon#about to read 3, iclass 7, count 0 2006.257.11:41:20.00#ibcon#read 3, iclass 7, count 0 2006.257.11:41:20.00#ibcon#about to read 4, iclass 7, count 0 2006.257.11:41:20.00#ibcon#read 4, iclass 7, count 0 2006.257.11:41:20.00#ibcon#about to read 5, iclass 7, count 0 2006.257.11:41:20.00#ibcon#read 5, iclass 7, count 0 2006.257.11:41:20.00#ibcon#about to read 6, iclass 7, count 0 2006.257.11:41:20.00#ibcon#read 6, iclass 7, count 0 2006.257.11:41:20.00#ibcon#end of sib2, iclass 7, count 0 2006.257.11:41:20.00#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:41:20.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:41:20.00#ibcon#[27=USB\r\n] 2006.257.11:41:20.00#ibcon#*before write, iclass 7, count 0 2006.257.11:41:20.00#ibcon#enter sib2, iclass 7, count 0 2006.257.11:41:20.00#ibcon#flushed, iclass 7, count 0 2006.257.11:41:20.00#ibcon#about to write, iclass 7, count 0 2006.257.11:41:20.00#ibcon#wrote, iclass 7, count 0 2006.257.11:41:20.00#ibcon#about to read 3, iclass 7, count 0 2006.257.11:41:20.03#ibcon#read 3, iclass 7, count 0 2006.257.11:41:20.03#ibcon#about to read 4, iclass 7, count 0 2006.257.11:41:20.03#ibcon#read 4, iclass 7, count 0 2006.257.11:41:20.03#ibcon#about to read 5, iclass 7, count 0 2006.257.11:41:20.03#ibcon#read 5, iclass 7, count 0 2006.257.11:41:20.03#ibcon#about to read 6, iclass 7, count 0 2006.257.11:41:20.03#ibcon#read 6, iclass 7, count 0 2006.257.11:41:20.03#ibcon#end of sib2, iclass 7, count 0 2006.257.11:41:20.03#ibcon#*after write, iclass 7, count 0 2006.257.11:41:20.03#ibcon#*before return 0, iclass 7, count 0 2006.257.11:41:20.03#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:20.03#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:41:20.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:41:20.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:41:20.03$vck44/vblo=7,734.99 2006.257.11:41:20.03#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.11:41:20.03#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.11:41:20.03#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:20.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:20.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:20.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:20.03#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:41:20.03#ibcon#first serial, iclass 11, count 0 2006.257.11:41:20.03#ibcon#enter sib2, iclass 11, count 0 2006.257.11:41:20.03#ibcon#flushed, iclass 11, count 0 2006.257.11:41:20.03#ibcon#about to write, iclass 11, count 0 2006.257.11:41:20.03#ibcon#wrote, iclass 11, count 0 2006.257.11:41:20.03#ibcon#about to read 3, iclass 11, count 0 2006.257.11:41:20.05#ibcon#read 3, iclass 11, count 0 2006.257.11:41:20.05#ibcon#about to read 4, iclass 11, count 0 2006.257.11:41:20.05#ibcon#read 4, iclass 11, count 0 2006.257.11:41:20.05#ibcon#about to read 5, iclass 11, count 0 2006.257.11:41:20.05#ibcon#read 5, iclass 11, count 0 2006.257.11:41:20.05#ibcon#about to read 6, iclass 11, count 0 2006.257.11:41:20.05#ibcon#read 6, iclass 11, count 0 2006.257.11:41:20.05#ibcon#end of sib2, iclass 11, count 0 2006.257.11:41:20.05#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:41:20.05#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:41:20.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:41:20.05#ibcon#*before write, iclass 11, count 0 2006.257.11:41:20.05#ibcon#enter sib2, iclass 11, count 0 2006.257.11:41:20.05#ibcon#flushed, iclass 11, count 0 2006.257.11:41:20.05#ibcon#about to write, iclass 11, count 0 2006.257.11:41:20.05#ibcon#wrote, iclass 11, count 0 2006.257.11:41:20.05#ibcon#about to read 3, iclass 11, count 0 2006.257.11:41:20.09#ibcon#read 3, iclass 11, count 0 2006.257.11:41:20.09#ibcon#about to read 4, iclass 11, count 0 2006.257.11:41:20.09#ibcon#read 4, iclass 11, count 0 2006.257.11:41:20.09#ibcon#about to read 5, iclass 11, count 0 2006.257.11:41:20.09#ibcon#read 5, iclass 11, count 0 2006.257.11:41:20.09#ibcon#about to read 6, iclass 11, count 0 2006.257.11:41:20.09#ibcon#read 6, iclass 11, count 0 2006.257.11:41:20.09#ibcon#end of sib2, iclass 11, count 0 2006.257.11:41:20.09#ibcon#*after write, iclass 11, count 0 2006.257.11:41:20.09#ibcon#*before return 0, iclass 11, count 0 2006.257.11:41:20.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:20.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:41:20.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:41:20.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:41:20.09$vck44/vb=7,4 2006.257.11:41:20.09#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.11:41:20.09#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.11:41:20.09#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:20.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:20.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:20.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:20.15#ibcon#enter wrdev, iclass 13, count 2 2006.257.11:41:20.15#ibcon#first serial, iclass 13, count 2 2006.257.11:41:20.15#ibcon#enter sib2, iclass 13, count 2 2006.257.11:41:20.15#ibcon#flushed, iclass 13, count 2 2006.257.11:41:20.15#ibcon#about to write, iclass 13, count 2 2006.257.11:41:20.15#ibcon#wrote, iclass 13, count 2 2006.257.11:41:20.15#ibcon#about to read 3, iclass 13, count 2 2006.257.11:41:20.17#ibcon#read 3, iclass 13, count 2 2006.257.11:41:20.17#ibcon#about to read 4, iclass 13, count 2 2006.257.11:41:20.17#ibcon#read 4, iclass 13, count 2 2006.257.11:41:20.17#ibcon#about to read 5, iclass 13, count 2 2006.257.11:41:20.17#ibcon#read 5, iclass 13, count 2 2006.257.11:41:20.17#ibcon#about to read 6, iclass 13, count 2 2006.257.11:41:20.17#ibcon#read 6, iclass 13, count 2 2006.257.11:41:20.17#ibcon#end of sib2, iclass 13, count 2 2006.257.11:41:20.17#ibcon#*mode == 0, iclass 13, count 2 2006.257.11:41:20.17#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.11:41:20.17#ibcon#[27=AT07-04\r\n] 2006.257.11:41:20.17#ibcon#*before write, iclass 13, count 2 2006.257.11:41:20.17#ibcon#enter sib2, iclass 13, count 2 2006.257.11:41:20.17#ibcon#flushed, iclass 13, count 2 2006.257.11:41:20.17#ibcon#about to write, iclass 13, count 2 2006.257.11:41:20.17#ibcon#wrote, iclass 13, count 2 2006.257.11:41:20.17#ibcon#about to read 3, iclass 13, count 2 2006.257.11:41:20.20#ibcon#read 3, iclass 13, count 2 2006.257.11:41:20.20#ibcon#about to read 4, iclass 13, count 2 2006.257.11:41:20.20#ibcon#read 4, iclass 13, count 2 2006.257.11:41:21.36#ibcon#about to read 5, iclass 13, count 2 2006.257.11:41:21.36#ibcon#read 5, iclass 13, count 2 2006.257.11:41:21.36#ibcon#about to read 6, iclass 13, count 2 2006.257.11:41:21.36#ibcon#read 6, iclass 13, count 2 2006.257.11:41:21.36#ibcon#end of sib2, iclass 13, count 2 2006.257.11:41:21.36#ibcon#*after write, iclass 13, count 2 2006.257.11:41:21.36#ibcon#*before return 0, iclass 13, count 2 2006.257.11:41:21.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:21.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:41:21.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.11:41:21.36#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:21.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:21.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:21.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:21.48#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:41:21.48#ibcon#first serial, iclass 13, count 0 2006.257.11:41:21.48#ibcon#enter sib2, iclass 13, count 0 2006.257.11:41:21.48#ibcon#flushed, iclass 13, count 0 2006.257.11:41:21.48#ibcon#about to write, iclass 13, count 0 2006.257.11:41:21.48#ibcon#wrote, iclass 13, count 0 2006.257.11:41:21.48#ibcon#about to read 3, iclass 13, count 0 2006.257.11:41:21.50#ibcon#read 3, iclass 13, count 0 2006.257.11:41:21.50#ibcon#about to read 4, iclass 13, count 0 2006.257.11:41:21.50#ibcon#read 4, iclass 13, count 0 2006.257.11:41:21.50#ibcon#about to read 5, iclass 13, count 0 2006.257.11:41:21.50#ibcon#read 5, iclass 13, count 0 2006.257.11:41:21.50#ibcon#about to read 6, iclass 13, count 0 2006.257.11:41:21.50#ibcon#read 6, iclass 13, count 0 2006.257.11:41:21.50#ibcon#end of sib2, iclass 13, count 0 2006.257.11:41:21.50#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:41:21.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:41:21.50#ibcon#[27=USB\r\n] 2006.257.11:41:21.50#ibcon#*before write, iclass 13, count 0 2006.257.11:41:21.50#ibcon#enter sib2, iclass 13, count 0 2006.257.11:41:21.50#ibcon#flushed, iclass 13, count 0 2006.257.11:41:21.50#ibcon#about to write, iclass 13, count 0 2006.257.11:41:21.50#ibcon#wrote, iclass 13, count 0 2006.257.11:41:21.50#ibcon#about to read 3, iclass 13, count 0 2006.257.11:41:21.53#ibcon#read 3, iclass 13, count 0 2006.257.11:41:21.53#ibcon#about to read 4, iclass 13, count 0 2006.257.11:41:21.53#ibcon#read 4, iclass 13, count 0 2006.257.11:41:21.53#ibcon#about to read 5, iclass 13, count 0 2006.257.11:41:21.53#ibcon#read 5, iclass 13, count 0 2006.257.11:41:21.53#ibcon#about to read 6, iclass 13, count 0 2006.257.11:41:21.53#ibcon#read 6, iclass 13, count 0 2006.257.11:41:21.53#ibcon#end of sib2, iclass 13, count 0 2006.257.11:41:21.53#ibcon#*after write, iclass 13, count 0 2006.257.11:41:21.53#ibcon#*before return 0, iclass 13, count 0 2006.257.11:41:21.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:21.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:41:21.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:41:21.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:41:21.53$vck44/vblo=8,744.99 2006.257.11:41:21.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.11:41:21.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.11:41:21.53#ibcon#ireg 17 cls_cnt 0 2006.257.11:41:21.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:21.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:21.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:21.53#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:41:21.53#ibcon#first serial, iclass 15, count 0 2006.257.11:41:21.53#ibcon#enter sib2, iclass 15, count 0 2006.257.11:41:21.53#ibcon#flushed, iclass 15, count 0 2006.257.11:41:21.53#ibcon#about to write, iclass 15, count 0 2006.257.11:41:21.53#ibcon#wrote, iclass 15, count 0 2006.257.11:41:21.53#ibcon#about to read 3, iclass 15, count 0 2006.257.11:41:21.55#ibcon#read 3, iclass 15, count 0 2006.257.11:41:21.55#ibcon#about to read 4, iclass 15, count 0 2006.257.11:41:21.55#ibcon#read 4, iclass 15, count 0 2006.257.11:41:21.55#ibcon#about to read 5, iclass 15, count 0 2006.257.11:41:21.55#ibcon#read 5, iclass 15, count 0 2006.257.11:41:21.55#ibcon#about to read 6, iclass 15, count 0 2006.257.11:41:21.55#ibcon#read 6, iclass 15, count 0 2006.257.11:41:21.55#ibcon#end of sib2, iclass 15, count 0 2006.257.11:41:21.55#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:41:21.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:41:21.55#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:41:21.55#ibcon#*before write, iclass 15, count 0 2006.257.11:41:21.55#ibcon#enter sib2, iclass 15, count 0 2006.257.11:41:21.55#ibcon#flushed, iclass 15, count 0 2006.257.11:41:21.55#ibcon#about to write, iclass 15, count 0 2006.257.11:41:21.55#ibcon#wrote, iclass 15, count 0 2006.257.11:41:21.55#ibcon#about to read 3, iclass 15, count 0 2006.257.11:41:21.59#ibcon#read 3, iclass 15, count 0 2006.257.11:41:21.59#ibcon#about to read 4, iclass 15, count 0 2006.257.11:41:21.59#ibcon#read 4, iclass 15, count 0 2006.257.11:41:21.59#ibcon#about to read 5, iclass 15, count 0 2006.257.11:41:21.59#ibcon#read 5, iclass 15, count 0 2006.257.11:41:21.59#ibcon#about to read 6, iclass 15, count 0 2006.257.11:41:21.59#ibcon#read 6, iclass 15, count 0 2006.257.11:41:21.59#ibcon#end of sib2, iclass 15, count 0 2006.257.11:41:21.59#ibcon#*after write, iclass 15, count 0 2006.257.11:41:21.59#ibcon#*before return 0, iclass 15, count 0 2006.257.11:41:21.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:21.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:41:21.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:41:21.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:41:21.59$vck44/vb=8,4 2006.257.11:41:21.59#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.11:41:21.59#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.11:41:21.59#ibcon#ireg 11 cls_cnt 2 2006.257.11:41:21.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:21.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:21.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:21.65#ibcon#enter wrdev, iclass 17, count 2 2006.257.11:41:21.65#ibcon#first serial, iclass 17, count 2 2006.257.11:41:21.65#ibcon#enter sib2, iclass 17, count 2 2006.257.11:41:21.65#ibcon#flushed, iclass 17, count 2 2006.257.11:41:21.65#ibcon#about to write, iclass 17, count 2 2006.257.11:41:21.65#ibcon#wrote, iclass 17, count 2 2006.257.11:41:21.65#ibcon#about to read 3, iclass 17, count 2 2006.257.11:41:21.67#ibcon#read 3, iclass 17, count 2 2006.257.11:41:21.67#ibcon#about to read 4, iclass 17, count 2 2006.257.11:41:21.67#ibcon#read 4, iclass 17, count 2 2006.257.11:41:21.67#ibcon#about to read 5, iclass 17, count 2 2006.257.11:41:21.67#ibcon#read 5, iclass 17, count 2 2006.257.11:41:21.67#ibcon#about to read 6, iclass 17, count 2 2006.257.11:41:21.67#ibcon#read 6, iclass 17, count 2 2006.257.11:41:21.67#ibcon#end of sib2, iclass 17, count 2 2006.257.11:41:21.67#ibcon#*mode == 0, iclass 17, count 2 2006.257.11:41:21.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.11:41:21.67#ibcon#[27=AT08-04\r\n] 2006.257.11:41:21.67#ibcon#*before write, iclass 17, count 2 2006.257.11:41:21.67#ibcon#enter sib2, iclass 17, count 2 2006.257.11:41:21.67#ibcon#flushed, iclass 17, count 2 2006.257.11:41:21.67#ibcon#about to write, iclass 17, count 2 2006.257.11:41:21.67#ibcon#wrote, iclass 17, count 2 2006.257.11:41:21.67#ibcon#about to read 3, iclass 17, count 2 2006.257.11:41:21.70#ibcon#read 3, iclass 17, count 2 2006.257.11:41:21.70#ibcon#about to read 4, iclass 17, count 2 2006.257.11:41:21.70#ibcon#read 4, iclass 17, count 2 2006.257.11:41:21.70#ibcon#about to read 5, iclass 17, count 2 2006.257.11:41:21.70#ibcon#read 5, iclass 17, count 2 2006.257.11:41:21.70#ibcon#about to read 6, iclass 17, count 2 2006.257.11:41:21.70#ibcon#read 6, iclass 17, count 2 2006.257.11:41:21.70#ibcon#end of sib2, iclass 17, count 2 2006.257.11:41:21.70#ibcon#*after write, iclass 17, count 2 2006.257.11:41:21.70#ibcon#*before return 0, iclass 17, count 2 2006.257.11:41:21.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:21.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:41:21.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.11:41:21.70#ibcon#ireg 7 cls_cnt 0 2006.257.11:41:21.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:21.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:21.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:21.82#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:41:21.82#ibcon#first serial, iclass 17, count 0 2006.257.11:41:21.82#ibcon#enter sib2, iclass 17, count 0 2006.257.11:41:21.82#ibcon#flushed, iclass 17, count 0 2006.257.11:41:21.82#ibcon#about to write, iclass 17, count 0 2006.257.11:41:21.82#ibcon#wrote, iclass 17, count 0 2006.257.11:41:21.82#ibcon#about to read 3, iclass 17, count 0 2006.257.11:41:21.84#ibcon#read 3, iclass 17, count 0 2006.257.11:41:21.84#ibcon#about to read 4, iclass 17, count 0 2006.257.11:41:21.84#ibcon#read 4, iclass 17, count 0 2006.257.11:41:21.84#ibcon#about to read 5, iclass 17, count 0 2006.257.11:41:21.84#ibcon#read 5, iclass 17, count 0 2006.257.11:41:21.84#ibcon#about to read 6, iclass 17, count 0 2006.257.11:41:21.84#ibcon#read 6, iclass 17, count 0 2006.257.11:41:21.84#ibcon#end of sib2, iclass 17, count 0 2006.257.11:41:21.84#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:41:21.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:41:21.84#ibcon#[27=USB\r\n] 2006.257.11:41:21.84#ibcon#*before write, iclass 17, count 0 2006.257.11:41:21.84#ibcon#enter sib2, iclass 17, count 0 2006.257.11:41:21.84#ibcon#flushed, iclass 17, count 0 2006.257.11:41:21.84#ibcon#about to write, iclass 17, count 0 2006.257.11:41:21.84#ibcon#wrote, iclass 17, count 0 2006.257.11:41:21.84#ibcon#about to read 3, iclass 17, count 0 2006.257.11:41:21.87#ibcon#read 3, iclass 17, count 0 2006.257.11:41:21.87#ibcon#about to read 4, iclass 17, count 0 2006.257.11:41:21.87#ibcon#read 4, iclass 17, count 0 2006.257.11:41:21.87#ibcon#about to read 5, iclass 17, count 0 2006.257.11:41:21.87#ibcon#read 5, iclass 17, count 0 2006.257.11:41:21.87#ibcon#about to read 6, iclass 17, count 0 2006.257.11:41:21.87#ibcon#read 6, iclass 17, count 0 2006.257.11:41:21.87#ibcon#end of sib2, iclass 17, count 0 2006.257.11:41:21.87#ibcon#*after write, iclass 17, count 0 2006.257.11:41:21.87#ibcon#*before return 0, iclass 17, count 0 2006.257.11:41:21.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:21.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:41:21.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:41:21.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:41:21.87$vck44/vabw=wide 2006.257.11:41:21.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.11:41:21.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.11:41:21.87#ibcon#ireg 8 cls_cnt 0 2006.257.11:41:21.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:21.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:21.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:21.87#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:41:21.87#ibcon#first serial, iclass 19, count 0 2006.257.11:41:21.87#ibcon#enter sib2, iclass 19, count 0 2006.257.11:41:21.87#ibcon#flushed, iclass 19, count 0 2006.257.11:41:21.87#ibcon#about to write, iclass 19, count 0 2006.257.11:41:21.87#ibcon#wrote, iclass 19, count 0 2006.257.11:41:21.87#ibcon#about to read 3, iclass 19, count 0 2006.257.11:41:21.89#ibcon#read 3, iclass 19, count 0 2006.257.11:41:21.89#ibcon#about to read 4, iclass 19, count 0 2006.257.11:41:21.89#ibcon#read 4, iclass 19, count 0 2006.257.11:41:21.89#ibcon#about to read 5, iclass 19, count 0 2006.257.11:41:21.89#ibcon#read 5, iclass 19, count 0 2006.257.11:41:21.89#ibcon#about to read 6, iclass 19, count 0 2006.257.11:41:21.89#ibcon#read 6, iclass 19, count 0 2006.257.11:41:21.89#ibcon#end of sib2, iclass 19, count 0 2006.257.11:41:21.89#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:41:21.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:41:21.89#ibcon#[25=BW32\r\n] 2006.257.11:41:21.89#ibcon#*before write, iclass 19, count 0 2006.257.11:41:21.89#ibcon#enter sib2, iclass 19, count 0 2006.257.11:41:21.89#ibcon#flushed, iclass 19, count 0 2006.257.11:41:21.89#ibcon#about to write, iclass 19, count 0 2006.257.11:41:21.89#ibcon#wrote, iclass 19, count 0 2006.257.11:41:21.89#ibcon#about to read 3, iclass 19, count 0 2006.257.11:41:21.92#ibcon#read 3, iclass 19, count 0 2006.257.11:41:21.92#ibcon#about to read 4, iclass 19, count 0 2006.257.11:41:21.92#ibcon#read 4, iclass 19, count 0 2006.257.11:41:21.92#ibcon#about to read 5, iclass 19, count 0 2006.257.11:41:21.92#ibcon#read 5, iclass 19, count 0 2006.257.11:41:21.92#ibcon#about to read 6, iclass 19, count 0 2006.257.11:41:21.92#ibcon#read 6, iclass 19, count 0 2006.257.11:41:21.92#ibcon#end of sib2, iclass 19, count 0 2006.257.11:41:21.92#ibcon#*after write, iclass 19, count 0 2006.257.11:41:21.92#ibcon#*before return 0, iclass 19, count 0 2006.257.11:41:21.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:21.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:41:21.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:41:21.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:41:21.92$vck44/vbbw=wide 2006.257.11:41:21.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.11:41:21.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.11:41:21.92#ibcon#ireg 8 cls_cnt 0 2006.257.11:41:21.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:41:21.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:41:21.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:41:21.99#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:41:21.99#ibcon#first serial, iclass 21, count 0 2006.257.11:41:21.99#ibcon#enter sib2, iclass 21, count 0 2006.257.11:41:21.99#ibcon#flushed, iclass 21, count 0 2006.257.11:41:21.99#ibcon#about to write, iclass 21, count 0 2006.257.11:41:21.99#ibcon#wrote, iclass 21, count 0 2006.257.11:41:21.99#ibcon#about to read 3, iclass 21, count 0 2006.257.11:41:22.01#ibcon#read 3, iclass 21, count 0 2006.257.11:41:22.01#ibcon#about to read 4, iclass 21, count 0 2006.257.11:41:22.01#ibcon#read 4, iclass 21, count 0 2006.257.11:41:22.01#ibcon#about to read 5, iclass 21, count 0 2006.257.11:41:22.01#ibcon#read 5, iclass 21, count 0 2006.257.11:41:22.01#ibcon#about to read 6, iclass 21, count 0 2006.257.11:41:22.01#ibcon#read 6, iclass 21, count 0 2006.257.11:41:22.01#ibcon#end of sib2, iclass 21, count 0 2006.257.11:41:22.01#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:41:22.01#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:41:22.01#ibcon#[27=BW32\r\n] 2006.257.11:41:22.01#ibcon#*before write, iclass 21, count 0 2006.257.11:41:22.01#ibcon#enter sib2, iclass 21, count 0 2006.257.11:41:22.01#ibcon#flushed, iclass 21, count 0 2006.257.11:41:22.01#ibcon#about to write, iclass 21, count 0 2006.257.11:41:22.01#ibcon#wrote, iclass 21, count 0 2006.257.11:41:22.01#ibcon#about to read 3, iclass 21, count 0 2006.257.11:41:22.04#ibcon#read 3, iclass 21, count 0 2006.257.11:41:22.04#ibcon#about to read 4, iclass 21, count 0 2006.257.11:41:22.04#ibcon#read 4, iclass 21, count 0 2006.257.11:41:22.04#ibcon#about to read 5, iclass 21, count 0 2006.257.11:41:22.04#ibcon#read 5, iclass 21, count 0 2006.257.11:41:22.04#ibcon#about to read 6, iclass 21, count 0 2006.257.11:41:22.04#ibcon#read 6, iclass 21, count 0 2006.257.11:41:22.04#ibcon#end of sib2, iclass 21, count 0 2006.257.11:41:22.04#ibcon#*after write, iclass 21, count 0 2006.257.11:41:22.04#ibcon#*before return 0, iclass 21, count 0 2006.257.11:41:22.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:41:22.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:41:22.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:41:22.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:41:22.04$setupk4/ifdk4 2006.257.11:41:22.04$ifdk4/lo= 2006.257.11:41:22.04$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:41:22.04$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:41:22.04$ifdk4/patch= 2006.257.11:41:22.04$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:41:22.04$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:41:22.04$setupk4/!*+20s 2006.257.11:41:22.65#abcon#<5=/14 1.3 3.9 18.13 961014.1\r\n> 2006.257.11:41:22.67#abcon#{5=INTERFACE CLEAR} 2006.257.11:41:22.73#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:41:32.12$setupk4/"tpicd 2006.257.11:41:32.12$setupk4/echo=off 2006.257.11:41:32.12$setupk4/xlog=off 2006.257.11:41:32.12:!2006.257.11:46:34 2006.257.11:41:48.14#trakl#Source acquired 2006.257.11:41:49.14#flagr#flagr/antenna,acquired 2006.257.11:46:34.00:preob 2006.257.11:46:35.14/onsource/TRACKING 2006.257.11:46:35.14:!2006.257.11:46:44 2006.257.11:46:44.00:"tape 2006.257.11:46:44.00:"st=record 2006.257.11:46:44.00:data_valid=on 2006.257.11:46:44.00:midob 2006.257.11:46:44.14/onsource/TRACKING 2006.257.11:46:44.14/wx/18.15,1014.1,95 2006.257.11:46:44.23/cable/+6.4786E-03 2006.257.11:46:45.32/va/01,08,usb,yes,31,33 2006.257.11:46:45.32/va/02,07,usb,yes,34,34 2006.257.11:46:45.32/va/03,08,usb,yes,30,32 2006.257.11:46:45.32/va/04,07,usb,yes,35,36 2006.257.11:46:45.32/va/05,04,usb,yes,31,31 2006.257.11:46:45.32/va/06,04,usb,yes,35,34 2006.257.11:46:45.32/va/07,04,usb,yes,35,36 2006.257.11:46:45.32/va/08,04,usb,yes,29,36 2006.257.11:46:45.55/valo/01,524.99,yes,locked 2006.257.11:46:45.55/valo/02,534.99,yes,locked 2006.257.11:46:45.55/valo/03,564.99,yes,locked 2006.257.11:46:45.55/valo/04,624.99,yes,locked 2006.257.11:46:45.55/valo/05,734.99,yes,locked 2006.257.11:46:45.55/valo/06,814.99,yes,locked 2006.257.11:46:45.55/valo/07,864.99,yes,locked 2006.257.11:46:45.55/valo/08,884.99,yes,locked 2006.257.11:46:46.64/vb/01,04,usb,yes,31,29 2006.257.11:46:46.64/vb/02,05,usb,yes,29,29 2006.257.11:46:46.64/vb/03,04,usb,yes,30,33 2006.257.11:46:46.64/vb/04,05,usb,yes,30,29 2006.257.11:46:46.64/vb/05,04,usb,yes,27,29 2006.257.11:46:46.64/vb/06,04,usb,yes,31,27 2006.257.11:46:46.64/vb/07,04,usb,yes,31,31 2006.257.11:46:46.64/vb/08,04,usb,yes,29,32 2006.257.11:46:46.88/vblo/01,629.99,yes,locked 2006.257.11:46:46.88/vblo/02,634.99,yes,locked 2006.257.11:46:46.88/vblo/03,649.99,yes,locked 2006.257.11:46:46.88/vblo/04,679.99,yes,locked 2006.257.11:46:46.88/vblo/05,709.99,yes,locked 2006.257.11:46:46.88/vblo/06,719.99,yes,locked 2006.257.11:46:46.88/vblo/07,734.99,yes,locked 2006.257.11:46:46.88/vblo/08,744.99,yes,locked 2006.257.11:46:47.03/vabw/8 2006.257.11:46:47.18/vbbw/8 2006.257.11:46:47.27/xfe/off,on,15.2 2006.257.11:46:47.64/ifatt/23,28,28,28 2006.257.11:46:48.07/fmout-gps/S +4.61E-07 2006.257.11:46:48.11:!2006.257.11:47:44 2006.257.11:47:44.00:data_valid=off 2006.257.11:47:44.00:"et 2006.257.11:47:44.00:!+3s 2006.257.11:47:47.01:"tape 2006.257.11:47:47.01:postob 2006.257.11:47:47.08/cable/+6.4779E-03 2006.257.11:47:47.08/wx/18.16,1014.0,95 2006.257.11:47:48.07/fmout-gps/S +4.60E-07 2006.257.11:47:48.07:scan_name=257-1150,jd0609,70 2006.257.11:47:48.07:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.11:47:48.13#flagr#flagr/antenna,new-source 2006.257.11:47:49.13:checkk5 2006.257.11:47:49.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:47:49.88/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:47:50.27/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:47:50.65/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:47:51.03/chk_obsdata//k5ts1/T2571146??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.11:47:51.43/chk_obsdata//k5ts2/T2571146??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.11:47:51.81/chk_obsdata//k5ts3/T2571146??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.11:47:52.20/chk_obsdata//k5ts4/T2571146??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.11:47:52.89/k5log//k5ts1_log_newline 2006.257.11:47:53.61/k5log//k5ts2_log_newline 2006.257.11:47:54.33/k5log//k5ts3_log_newline 2006.257.11:47:55.03/k5log//k5ts4_log_newline 2006.257.11:47:55.06/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:47:55.06:setupk4=1 2006.257.11:47:55.06$setupk4/echo=on 2006.257.11:47:55.06$setupk4/pcalon 2006.257.11:47:55.06$pcalon/"no phase cal control is implemented here 2006.257.11:47:55.06$setupk4/"tpicd=stop 2006.257.11:47:55.06$setupk4/"rec=synch_on 2006.257.11:47:55.06$setupk4/"rec_mode=128 2006.257.11:47:55.06$setupk4/!* 2006.257.11:47:55.06$setupk4/recpk4 2006.257.11:47:55.06$recpk4/recpatch= 2006.257.11:47:55.07$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:47:55.07$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:47:55.07$setupk4/vck44 2006.257.11:47:55.07$vck44/valo=1,524.99 2006.257.11:47:55.07#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.11:47:55.07#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.11:47:55.07#ibcon#ireg 17 cls_cnt 0 2006.257.11:47:55.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:55.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:55.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:55.07#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:47:55.07#ibcon#first serial, iclass 38, count 0 2006.257.11:47:55.07#ibcon#enter sib2, iclass 38, count 0 2006.257.11:47:55.07#ibcon#flushed, iclass 38, count 0 2006.257.11:47:55.07#ibcon#about to write, iclass 38, count 0 2006.257.11:47:55.07#ibcon#wrote, iclass 38, count 0 2006.257.11:47:55.07#ibcon#about to read 3, iclass 38, count 0 2006.257.11:47:55.09#ibcon#read 3, iclass 38, count 0 2006.257.11:47:55.09#ibcon#about to read 4, iclass 38, count 0 2006.257.11:47:55.09#ibcon#read 4, iclass 38, count 0 2006.257.11:47:55.09#ibcon#about to read 5, iclass 38, count 0 2006.257.11:47:55.09#ibcon#read 5, iclass 38, count 0 2006.257.11:47:55.09#ibcon#about to read 6, iclass 38, count 0 2006.257.11:47:55.09#ibcon#read 6, iclass 38, count 0 2006.257.11:47:55.09#ibcon#end of sib2, iclass 38, count 0 2006.257.11:47:55.09#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:47:55.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:47:55.09#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:47:55.09#ibcon#*before write, iclass 38, count 0 2006.257.11:47:55.09#ibcon#enter sib2, iclass 38, count 0 2006.257.11:47:55.09#ibcon#flushed, iclass 38, count 0 2006.257.11:47:55.09#ibcon#about to write, iclass 38, count 0 2006.257.11:47:55.09#ibcon#wrote, iclass 38, count 0 2006.257.11:47:55.09#ibcon#about to read 3, iclass 38, count 0 2006.257.11:47:55.14#ibcon#read 3, iclass 38, count 0 2006.257.11:47:55.14#ibcon#about to read 4, iclass 38, count 0 2006.257.11:47:55.14#ibcon#read 4, iclass 38, count 0 2006.257.11:47:55.14#ibcon#about to read 5, iclass 38, count 0 2006.257.11:47:55.14#ibcon#read 5, iclass 38, count 0 2006.257.11:47:55.14#ibcon#about to read 6, iclass 38, count 0 2006.257.11:47:55.14#ibcon#read 6, iclass 38, count 0 2006.257.11:47:55.14#ibcon#end of sib2, iclass 38, count 0 2006.257.11:47:55.14#ibcon#*after write, iclass 38, count 0 2006.257.11:47:55.14#ibcon#*before return 0, iclass 38, count 0 2006.257.11:47:55.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:55.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:55.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:47:55.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:47:55.14$vck44/va=1,8 2006.257.11:47:55.14#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.11:47:55.14#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.11:47:55.14#ibcon#ireg 11 cls_cnt 2 2006.257.11:47:55.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:55.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:55.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:55.14#ibcon#enter wrdev, iclass 40, count 2 2006.257.11:47:55.14#ibcon#first serial, iclass 40, count 2 2006.257.11:47:55.14#ibcon#enter sib2, iclass 40, count 2 2006.257.11:47:55.14#ibcon#flushed, iclass 40, count 2 2006.257.11:47:55.14#ibcon#about to write, iclass 40, count 2 2006.257.11:47:55.14#ibcon#wrote, iclass 40, count 2 2006.257.11:47:55.14#ibcon#about to read 3, iclass 40, count 2 2006.257.11:47:55.16#ibcon#read 3, iclass 40, count 2 2006.257.11:47:55.16#ibcon#about to read 4, iclass 40, count 2 2006.257.11:47:55.16#ibcon#read 4, iclass 40, count 2 2006.257.11:47:55.16#ibcon#about to read 5, iclass 40, count 2 2006.257.11:47:55.16#ibcon#read 5, iclass 40, count 2 2006.257.11:47:55.16#ibcon#about to read 6, iclass 40, count 2 2006.257.11:47:55.16#ibcon#read 6, iclass 40, count 2 2006.257.11:47:55.16#ibcon#end of sib2, iclass 40, count 2 2006.257.11:47:55.16#ibcon#*mode == 0, iclass 40, count 2 2006.257.11:47:55.16#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.11:47:55.16#ibcon#[25=AT01-08\r\n] 2006.257.11:47:55.16#ibcon#*before write, iclass 40, count 2 2006.257.11:47:55.16#ibcon#enter sib2, iclass 40, count 2 2006.257.11:47:55.16#ibcon#flushed, iclass 40, count 2 2006.257.11:47:55.16#ibcon#about to write, iclass 40, count 2 2006.257.11:47:55.16#ibcon#wrote, iclass 40, count 2 2006.257.11:47:55.16#ibcon#about to read 3, iclass 40, count 2 2006.257.11:47:55.19#ibcon#read 3, iclass 40, count 2 2006.257.11:47:55.19#ibcon#about to read 4, iclass 40, count 2 2006.257.11:47:55.19#ibcon#read 4, iclass 40, count 2 2006.257.11:47:55.19#ibcon#about to read 5, iclass 40, count 2 2006.257.11:47:55.19#ibcon#read 5, iclass 40, count 2 2006.257.11:47:55.19#ibcon#about to read 6, iclass 40, count 2 2006.257.11:47:55.19#ibcon#read 6, iclass 40, count 2 2006.257.11:47:55.19#ibcon#end of sib2, iclass 40, count 2 2006.257.11:47:55.19#ibcon#*after write, iclass 40, count 2 2006.257.11:47:55.19#ibcon#*before return 0, iclass 40, count 2 2006.257.11:47:55.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:55.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:55.19#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.11:47:55.19#ibcon#ireg 7 cls_cnt 0 2006.257.11:47:55.19#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:47:55.31#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:47:55.31#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:47:55.31#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:47:55.31#ibcon#first serial, iclass 40, count 0 2006.257.11:47:55.31#ibcon#enter sib2, iclass 40, count 0 2006.257.11:47:55.31#ibcon#flushed, iclass 40, count 0 2006.257.11:47:55.31#ibcon#about to write, iclass 40, count 0 2006.257.11:47:55.31#ibcon#wrote, iclass 40, count 0 2006.257.11:47:55.31#ibcon#about to read 3, iclass 40, count 0 2006.257.11:47:55.33#ibcon#read 3, iclass 40, count 0 2006.257.11:47:55.33#ibcon#about to read 4, iclass 40, count 0 2006.257.11:47:55.33#ibcon#read 4, iclass 40, count 0 2006.257.11:47:55.33#ibcon#about to read 5, iclass 40, count 0 2006.257.11:47:55.33#ibcon#read 5, iclass 40, count 0 2006.257.11:47:55.33#ibcon#about to read 6, iclass 40, count 0 2006.257.11:47:55.33#ibcon#read 6, iclass 40, count 0 2006.257.11:47:55.33#ibcon#end of sib2, iclass 40, count 0 2006.257.11:47:55.33#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:47:55.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:47:55.33#ibcon#[25=USB\r\n] 2006.257.11:47:55.33#ibcon#*before write, iclass 40, count 0 2006.257.11:47:55.33#ibcon#enter sib2, iclass 40, count 0 2006.257.11:47:55.33#ibcon#flushed, iclass 40, count 0 2006.257.11:47:55.33#ibcon#about to write, iclass 40, count 0 2006.257.11:47:55.33#ibcon#wrote, iclass 40, count 0 2006.257.11:47:55.33#ibcon#about to read 3, iclass 40, count 0 2006.257.11:47:55.36#ibcon#read 3, iclass 40, count 0 2006.257.11:47:55.36#ibcon#about to read 4, iclass 40, count 0 2006.257.11:47:55.36#ibcon#read 4, iclass 40, count 0 2006.257.11:47:55.36#ibcon#about to read 5, iclass 40, count 0 2006.257.11:47:55.36#ibcon#read 5, iclass 40, count 0 2006.257.11:47:55.36#ibcon#about to read 6, iclass 40, count 0 2006.257.11:47:55.36#ibcon#read 6, iclass 40, count 0 2006.257.11:47:55.36#ibcon#end of sib2, iclass 40, count 0 2006.257.11:47:55.36#ibcon#*after write, iclass 40, count 0 2006.257.11:47:55.36#ibcon#*before return 0, iclass 40, count 0 2006.257.11:47:55.36#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:47:55.36#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:47:55.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:47:55.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:47:55.36$vck44/valo=2,534.99 2006.257.11:47:55.36#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.11:47:55.36#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.11:47:55.36#ibcon#ireg 17 cls_cnt 0 2006.257.11:47:55.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:47:55.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:47:55.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:47:55.36#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:47:55.36#ibcon#first serial, iclass 4, count 0 2006.257.11:47:55.36#ibcon#enter sib2, iclass 4, count 0 2006.257.11:47:55.36#ibcon#flushed, iclass 4, count 0 2006.257.11:47:55.36#ibcon#about to write, iclass 4, count 0 2006.257.11:47:55.36#ibcon#wrote, iclass 4, count 0 2006.257.11:47:55.36#ibcon#about to read 3, iclass 4, count 0 2006.257.11:47:55.38#ibcon#read 3, iclass 4, count 0 2006.257.11:47:55.38#ibcon#about to read 4, iclass 4, count 0 2006.257.11:47:55.38#ibcon#read 4, iclass 4, count 0 2006.257.11:47:55.38#ibcon#about to read 5, iclass 4, count 0 2006.257.11:47:55.38#ibcon#read 5, iclass 4, count 0 2006.257.11:47:55.38#ibcon#about to read 6, iclass 4, count 0 2006.257.11:47:55.38#ibcon#read 6, iclass 4, count 0 2006.257.11:47:55.38#ibcon#end of sib2, iclass 4, count 0 2006.257.11:47:55.38#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:47:55.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:47:55.38#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:47:55.38#ibcon#*before write, iclass 4, count 0 2006.257.11:47:55.38#ibcon#enter sib2, iclass 4, count 0 2006.257.11:47:55.38#ibcon#flushed, iclass 4, count 0 2006.257.11:47:55.38#ibcon#about to write, iclass 4, count 0 2006.257.11:47:55.38#ibcon#wrote, iclass 4, count 0 2006.257.11:47:55.38#ibcon#about to read 3, iclass 4, count 0 2006.257.11:47:55.42#ibcon#read 3, iclass 4, count 0 2006.257.11:47:55.42#ibcon#about to read 4, iclass 4, count 0 2006.257.11:47:55.42#ibcon#read 4, iclass 4, count 0 2006.257.11:47:55.42#ibcon#about to read 5, iclass 4, count 0 2006.257.11:47:55.42#ibcon#read 5, iclass 4, count 0 2006.257.11:47:55.42#ibcon#about to read 6, iclass 4, count 0 2006.257.11:47:55.42#ibcon#read 6, iclass 4, count 0 2006.257.11:47:55.42#ibcon#end of sib2, iclass 4, count 0 2006.257.11:47:55.42#ibcon#*after write, iclass 4, count 0 2006.257.11:47:55.42#ibcon#*before return 0, iclass 4, count 0 2006.257.11:47:55.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:47:55.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:47:55.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:47:55.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:47:55.42$vck44/va=2,7 2006.257.11:47:55.42#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.11:47:55.42#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.11:47:55.42#ibcon#ireg 11 cls_cnt 2 2006.257.11:47:55.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:47:55.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:47:55.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:47:55.48#ibcon#enter wrdev, iclass 6, count 2 2006.257.11:47:55.48#ibcon#first serial, iclass 6, count 2 2006.257.11:47:55.48#ibcon#enter sib2, iclass 6, count 2 2006.257.11:47:55.48#ibcon#flushed, iclass 6, count 2 2006.257.11:47:55.48#ibcon#about to write, iclass 6, count 2 2006.257.11:47:55.48#ibcon#wrote, iclass 6, count 2 2006.257.11:47:55.48#ibcon#about to read 3, iclass 6, count 2 2006.257.11:47:55.50#ibcon#read 3, iclass 6, count 2 2006.257.11:47:55.50#ibcon#about to read 4, iclass 6, count 2 2006.257.11:47:55.50#ibcon#read 4, iclass 6, count 2 2006.257.11:47:55.50#ibcon#about to read 5, iclass 6, count 2 2006.257.11:47:55.50#ibcon#read 5, iclass 6, count 2 2006.257.11:47:55.50#ibcon#about to read 6, iclass 6, count 2 2006.257.11:47:55.50#ibcon#read 6, iclass 6, count 2 2006.257.11:47:55.50#ibcon#end of sib2, iclass 6, count 2 2006.257.11:47:55.50#ibcon#*mode == 0, iclass 6, count 2 2006.257.11:47:55.50#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.11:47:55.50#ibcon#[25=AT02-07\r\n] 2006.257.11:47:55.50#ibcon#*before write, iclass 6, count 2 2006.257.11:47:55.50#ibcon#enter sib2, iclass 6, count 2 2006.257.11:47:55.50#ibcon#flushed, iclass 6, count 2 2006.257.11:47:55.50#ibcon#about to write, iclass 6, count 2 2006.257.11:47:55.50#ibcon#wrote, iclass 6, count 2 2006.257.11:47:55.50#ibcon#about to read 3, iclass 6, count 2 2006.257.11:47:55.53#ibcon#read 3, iclass 6, count 2 2006.257.11:47:55.53#ibcon#about to read 4, iclass 6, count 2 2006.257.11:47:55.53#ibcon#read 4, iclass 6, count 2 2006.257.11:47:55.53#ibcon#about to read 5, iclass 6, count 2 2006.257.11:47:55.53#ibcon#read 5, iclass 6, count 2 2006.257.11:47:55.53#ibcon#about to read 6, iclass 6, count 2 2006.257.11:47:55.53#ibcon#read 6, iclass 6, count 2 2006.257.11:47:55.53#ibcon#end of sib2, iclass 6, count 2 2006.257.11:47:55.53#ibcon#*after write, iclass 6, count 2 2006.257.11:47:55.53#ibcon#*before return 0, iclass 6, count 2 2006.257.11:47:55.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:47:55.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:47:55.53#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.11:47:55.53#ibcon#ireg 7 cls_cnt 0 2006.257.11:47:55.53#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:47:55.65#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:47:55.65#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:47:55.65#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:47:55.65#ibcon#first serial, iclass 6, count 0 2006.257.11:47:55.65#ibcon#enter sib2, iclass 6, count 0 2006.257.11:47:55.65#ibcon#flushed, iclass 6, count 0 2006.257.11:47:55.65#ibcon#about to write, iclass 6, count 0 2006.257.11:47:55.65#ibcon#wrote, iclass 6, count 0 2006.257.11:47:55.65#ibcon#about to read 3, iclass 6, count 0 2006.257.11:47:55.67#ibcon#read 3, iclass 6, count 0 2006.257.11:47:55.67#ibcon#about to read 4, iclass 6, count 0 2006.257.11:47:55.67#ibcon#read 4, iclass 6, count 0 2006.257.11:47:55.67#ibcon#about to read 5, iclass 6, count 0 2006.257.11:47:55.67#ibcon#read 5, iclass 6, count 0 2006.257.11:47:55.67#ibcon#about to read 6, iclass 6, count 0 2006.257.11:47:55.67#ibcon#read 6, iclass 6, count 0 2006.257.11:47:55.67#ibcon#end of sib2, iclass 6, count 0 2006.257.11:47:55.67#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:47:55.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:47:55.67#ibcon#[25=USB\r\n] 2006.257.11:47:55.67#ibcon#*before write, iclass 6, count 0 2006.257.11:47:55.67#ibcon#enter sib2, iclass 6, count 0 2006.257.11:47:55.67#ibcon#flushed, iclass 6, count 0 2006.257.11:47:55.67#ibcon#about to write, iclass 6, count 0 2006.257.11:47:55.67#ibcon#wrote, iclass 6, count 0 2006.257.11:47:55.67#ibcon#about to read 3, iclass 6, count 0 2006.257.11:47:55.70#ibcon#read 3, iclass 6, count 0 2006.257.11:47:55.70#ibcon#about to read 4, iclass 6, count 0 2006.257.11:47:55.70#ibcon#read 4, iclass 6, count 0 2006.257.11:47:55.70#ibcon#about to read 5, iclass 6, count 0 2006.257.11:47:55.70#ibcon#read 5, iclass 6, count 0 2006.257.11:47:55.70#ibcon#about to read 6, iclass 6, count 0 2006.257.11:47:55.70#ibcon#read 6, iclass 6, count 0 2006.257.11:47:55.70#ibcon#end of sib2, iclass 6, count 0 2006.257.11:47:55.70#ibcon#*after write, iclass 6, count 0 2006.257.11:47:55.70#ibcon#*before return 0, iclass 6, count 0 2006.257.11:47:55.70#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:47:55.70#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:47:55.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:47:55.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:47:55.70$vck44/valo=3,564.99 2006.257.11:47:55.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.11:47:55.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.11:47:55.70#ibcon#ireg 17 cls_cnt 0 2006.257.11:47:55.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:47:55.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:47:55.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:47:55.70#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:47:55.70#ibcon#first serial, iclass 10, count 0 2006.257.11:47:55.70#ibcon#enter sib2, iclass 10, count 0 2006.257.11:47:55.70#ibcon#flushed, iclass 10, count 0 2006.257.11:47:55.70#ibcon#about to write, iclass 10, count 0 2006.257.11:47:55.70#ibcon#wrote, iclass 10, count 0 2006.257.11:47:55.70#ibcon#about to read 3, iclass 10, count 0 2006.257.11:47:55.72#ibcon#read 3, iclass 10, count 0 2006.257.11:47:55.72#ibcon#about to read 4, iclass 10, count 0 2006.257.11:47:55.72#ibcon#read 4, iclass 10, count 0 2006.257.11:47:55.72#ibcon#about to read 5, iclass 10, count 0 2006.257.11:47:55.72#ibcon#read 5, iclass 10, count 0 2006.257.11:47:55.72#ibcon#about to read 6, iclass 10, count 0 2006.257.11:47:55.72#ibcon#read 6, iclass 10, count 0 2006.257.11:47:55.72#ibcon#end of sib2, iclass 10, count 0 2006.257.11:47:55.72#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:47:55.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:47:55.72#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:47:55.72#ibcon#*before write, iclass 10, count 0 2006.257.11:47:55.72#ibcon#enter sib2, iclass 10, count 0 2006.257.11:47:55.72#ibcon#flushed, iclass 10, count 0 2006.257.11:47:55.72#ibcon#about to write, iclass 10, count 0 2006.257.11:47:55.72#ibcon#wrote, iclass 10, count 0 2006.257.11:47:55.72#ibcon#about to read 3, iclass 10, count 0 2006.257.11:47:55.76#ibcon#read 3, iclass 10, count 0 2006.257.11:47:55.76#ibcon#about to read 4, iclass 10, count 0 2006.257.11:47:55.76#ibcon#read 4, iclass 10, count 0 2006.257.11:47:55.76#ibcon#about to read 5, iclass 10, count 0 2006.257.11:47:55.76#ibcon#read 5, iclass 10, count 0 2006.257.11:47:55.76#ibcon#about to read 6, iclass 10, count 0 2006.257.11:47:55.76#ibcon#read 6, iclass 10, count 0 2006.257.11:47:55.76#ibcon#end of sib2, iclass 10, count 0 2006.257.11:47:55.76#ibcon#*after write, iclass 10, count 0 2006.257.11:47:55.76#ibcon#*before return 0, iclass 10, count 0 2006.257.11:47:55.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:47:55.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:47:55.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:47:55.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:47:55.76$vck44/va=3,8 2006.257.11:47:55.76#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.11:47:55.76#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.11:47:55.76#ibcon#ireg 11 cls_cnt 2 2006.257.11:47:55.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:47:55.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:47:55.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:47:55.82#ibcon#enter wrdev, iclass 12, count 2 2006.257.11:47:55.82#ibcon#first serial, iclass 12, count 2 2006.257.11:47:55.82#ibcon#enter sib2, iclass 12, count 2 2006.257.11:47:55.82#ibcon#flushed, iclass 12, count 2 2006.257.11:47:55.82#ibcon#about to write, iclass 12, count 2 2006.257.11:47:55.82#ibcon#wrote, iclass 12, count 2 2006.257.11:47:55.82#ibcon#about to read 3, iclass 12, count 2 2006.257.11:47:55.84#ibcon#read 3, iclass 12, count 2 2006.257.11:47:55.84#ibcon#about to read 4, iclass 12, count 2 2006.257.11:47:55.84#ibcon#read 4, iclass 12, count 2 2006.257.11:47:55.84#ibcon#about to read 5, iclass 12, count 2 2006.257.11:47:55.84#ibcon#read 5, iclass 12, count 2 2006.257.11:47:55.84#ibcon#about to read 6, iclass 12, count 2 2006.257.11:47:55.84#ibcon#read 6, iclass 12, count 2 2006.257.11:47:55.84#ibcon#end of sib2, iclass 12, count 2 2006.257.11:47:55.84#ibcon#*mode == 0, iclass 12, count 2 2006.257.11:47:55.84#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.11:47:55.84#ibcon#[25=AT03-08\r\n] 2006.257.11:47:55.84#ibcon#*before write, iclass 12, count 2 2006.257.11:47:55.84#ibcon#enter sib2, iclass 12, count 2 2006.257.11:47:55.84#ibcon#flushed, iclass 12, count 2 2006.257.11:47:55.84#ibcon#about to write, iclass 12, count 2 2006.257.11:47:55.84#ibcon#wrote, iclass 12, count 2 2006.257.11:47:55.84#ibcon#about to read 3, iclass 12, count 2 2006.257.11:47:55.87#ibcon#read 3, iclass 12, count 2 2006.257.11:47:55.87#ibcon#about to read 4, iclass 12, count 2 2006.257.11:47:55.87#ibcon#read 4, iclass 12, count 2 2006.257.11:47:55.87#ibcon#about to read 5, iclass 12, count 2 2006.257.11:47:55.87#ibcon#read 5, iclass 12, count 2 2006.257.11:47:55.87#ibcon#about to read 6, iclass 12, count 2 2006.257.11:47:55.87#ibcon#read 6, iclass 12, count 2 2006.257.11:47:55.87#ibcon#end of sib2, iclass 12, count 2 2006.257.11:47:55.87#ibcon#*after write, iclass 12, count 2 2006.257.11:47:55.87#ibcon#*before return 0, iclass 12, count 2 2006.257.11:47:55.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:47:55.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:47:55.87#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.11:47:55.87#ibcon#ireg 7 cls_cnt 0 2006.257.11:47:55.87#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:47:55.99#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:47:55.99#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:47:55.99#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:47:55.99#ibcon#first serial, iclass 12, count 0 2006.257.11:47:55.99#ibcon#enter sib2, iclass 12, count 0 2006.257.11:47:55.99#ibcon#flushed, iclass 12, count 0 2006.257.11:47:55.99#ibcon#about to write, iclass 12, count 0 2006.257.11:47:55.99#ibcon#wrote, iclass 12, count 0 2006.257.11:47:55.99#ibcon#about to read 3, iclass 12, count 0 2006.257.11:47:56.01#ibcon#read 3, iclass 12, count 0 2006.257.11:47:56.01#ibcon#about to read 4, iclass 12, count 0 2006.257.11:47:56.01#ibcon#read 4, iclass 12, count 0 2006.257.11:47:56.01#ibcon#about to read 5, iclass 12, count 0 2006.257.11:47:56.01#ibcon#read 5, iclass 12, count 0 2006.257.11:47:56.01#ibcon#about to read 6, iclass 12, count 0 2006.257.11:47:56.01#ibcon#read 6, iclass 12, count 0 2006.257.11:47:56.01#ibcon#end of sib2, iclass 12, count 0 2006.257.11:47:56.01#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:47:56.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:47:56.01#ibcon#[25=USB\r\n] 2006.257.11:47:56.01#ibcon#*before write, iclass 12, count 0 2006.257.11:47:56.01#ibcon#enter sib2, iclass 12, count 0 2006.257.11:47:56.01#ibcon#flushed, iclass 12, count 0 2006.257.11:47:56.01#ibcon#about to write, iclass 12, count 0 2006.257.11:47:56.01#ibcon#wrote, iclass 12, count 0 2006.257.11:47:56.01#ibcon#about to read 3, iclass 12, count 0 2006.257.11:47:56.04#ibcon#read 3, iclass 12, count 0 2006.257.11:47:56.04#ibcon#about to read 4, iclass 12, count 0 2006.257.11:47:56.04#ibcon#read 4, iclass 12, count 0 2006.257.11:47:56.04#ibcon#about to read 5, iclass 12, count 0 2006.257.11:47:56.04#ibcon#read 5, iclass 12, count 0 2006.257.11:47:56.04#ibcon#about to read 6, iclass 12, count 0 2006.257.11:47:56.04#ibcon#read 6, iclass 12, count 0 2006.257.11:47:56.04#ibcon#end of sib2, iclass 12, count 0 2006.257.11:47:56.04#ibcon#*after write, iclass 12, count 0 2006.257.11:47:56.04#ibcon#*before return 0, iclass 12, count 0 2006.257.11:47:56.04#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:47:56.04#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:47:56.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:47:56.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:47:56.04$vck44/valo=4,624.99 2006.257.11:47:56.04#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.11:47:56.04#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.11:47:56.04#ibcon#ireg 17 cls_cnt 0 2006.257.11:47:56.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:47:56.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:47:56.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:47:56.04#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:47:56.04#ibcon#first serial, iclass 14, count 0 2006.257.11:47:56.04#ibcon#enter sib2, iclass 14, count 0 2006.257.11:47:56.04#ibcon#flushed, iclass 14, count 0 2006.257.11:47:56.04#ibcon#about to write, iclass 14, count 0 2006.257.11:47:56.04#ibcon#wrote, iclass 14, count 0 2006.257.11:47:56.04#ibcon#about to read 3, iclass 14, count 0 2006.257.11:47:56.06#ibcon#read 3, iclass 14, count 0 2006.257.11:47:56.99#ibcon#about to read 4, iclass 14, count 0 2006.257.11:47:56.99#ibcon#read 4, iclass 14, count 0 2006.257.11:47:56.99#ibcon#about to read 5, iclass 14, count 0 2006.257.11:47:56.99#ibcon#read 5, iclass 14, count 0 2006.257.11:47:56.99#ibcon#about to read 6, iclass 14, count 0 2006.257.11:47:56.99#ibcon#read 6, iclass 14, count 0 2006.257.11:47:56.99#ibcon#end of sib2, iclass 14, count 0 2006.257.11:47:56.99#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:47:56.99#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:47:56.99#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:47:56.99#ibcon#*before write, iclass 14, count 0 2006.257.11:47:56.99#ibcon#enter sib2, iclass 14, count 0 2006.257.11:47:56.99#ibcon#flushed, iclass 14, count 0 2006.257.11:47:56.99#ibcon#about to write, iclass 14, count 0 2006.257.11:47:56.99#ibcon#wrote, iclass 14, count 0 2006.257.11:47:56.99#ibcon#about to read 3, iclass 14, count 0 2006.257.11:47:57.04#ibcon#read 3, iclass 14, count 0 2006.257.11:47:57.04#ibcon#about to read 4, iclass 14, count 0 2006.257.11:47:57.04#ibcon#read 4, iclass 14, count 0 2006.257.11:47:57.04#ibcon#about to read 5, iclass 14, count 0 2006.257.11:47:57.04#ibcon#read 5, iclass 14, count 0 2006.257.11:47:57.04#ibcon#about to read 6, iclass 14, count 0 2006.257.11:47:57.04#ibcon#read 6, iclass 14, count 0 2006.257.11:47:57.04#ibcon#end of sib2, iclass 14, count 0 2006.257.11:47:57.04#ibcon#*after write, iclass 14, count 0 2006.257.11:47:57.04#ibcon#*before return 0, iclass 14, count 0 2006.257.11:47:57.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:47:57.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:47:57.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:47:57.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:47:57.04$vck44/va=4,7 2006.257.11:47:57.04#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.11:47:57.04#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.11:47:57.04#ibcon#ireg 11 cls_cnt 2 2006.257.11:47:57.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:47:57.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:47:57.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:47:57.04#ibcon#enter wrdev, iclass 16, count 2 2006.257.11:47:57.04#ibcon#first serial, iclass 16, count 2 2006.257.11:47:57.04#ibcon#enter sib2, iclass 16, count 2 2006.257.11:47:57.04#ibcon#flushed, iclass 16, count 2 2006.257.11:47:57.04#ibcon#about to write, iclass 16, count 2 2006.257.11:47:57.04#ibcon#wrote, iclass 16, count 2 2006.257.11:47:57.04#ibcon#about to read 3, iclass 16, count 2 2006.257.11:47:57.06#ibcon#read 3, iclass 16, count 2 2006.257.11:47:57.06#ibcon#about to read 4, iclass 16, count 2 2006.257.11:47:57.06#ibcon#read 4, iclass 16, count 2 2006.257.11:47:57.06#ibcon#about to read 5, iclass 16, count 2 2006.257.11:47:57.06#ibcon#read 5, iclass 16, count 2 2006.257.11:47:57.06#ibcon#about to read 6, iclass 16, count 2 2006.257.11:47:57.06#ibcon#read 6, iclass 16, count 2 2006.257.11:47:57.06#ibcon#end of sib2, iclass 16, count 2 2006.257.11:47:57.06#ibcon#*mode == 0, iclass 16, count 2 2006.257.11:47:57.06#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.11:47:57.06#ibcon#[25=AT04-07\r\n] 2006.257.11:47:57.06#ibcon#*before write, iclass 16, count 2 2006.257.11:47:57.06#ibcon#enter sib2, iclass 16, count 2 2006.257.11:47:57.06#ibcon#flushed, iclass 16, count 2 2006.257.11:47:57.06#ibcon#about to write, iclass 16, count 2 2006.257.11:47:57.06#ibcon#wrote, iclass 16, count 2 2006.257.11:47:57.06#ibcon#about to read 3, iclass 16, count 2 2006.257.11:47:57.09#ibcon#read 3, iclass 16, count 2 2006.257.11:47:57.09#ibcon#about to read 4, iclass 16, count 2 2006.257.11:47:57.09#ibcon#read 4, iclass 16, count 2 2006.257.11:47:57.09#ibcon#about to read 5, iclass 16, count 2 2006.257.11:47:57.09#ibcon#read 5, iclass 16, count 2 2006.257.11:47:57.09#ibcon#about to read 6, iclass 16, count 2 2006.257.11:47:57.09#ibcon#read 6, iclass 16, count 2 2006.257.11:47:57.09#ibcon#end of sib2, iclass 16, count 2 2006.257.11:47:57.09#ibcon#*after write, iclass 16, count 2 2006.257.11:47:57.09#ibcon#*before return 0, iclass 16, count 2 2006.257.11:47:57.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:47:57.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:47:57.09#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.11:47:57.09#ibcon#ireg 7 cls_cnt 0 2006.257.11:47:57.09#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:47:57.21#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:47:57.21#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:47:57.21#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:47:57.21#ibcon#first serial, iclass 16, count 0 2006.257.11:47:57.21#ibcon#enter sib2, iclass 16, count 0 2006.257.11:47:57.21#ibcon#flushed, iclass 16, count 0 2006.257.11:47:57.21#ibcon#about to write, iclass 16, count 0 2006.257.11:47:57.21#ibcon#wrote, iclass 16, count 0 2006.257.11:47:57.21#ibcon#about to read 3, iclass 16, count 0 2006.257.11:47:57.23#ibcon#read 3, iclass 16, count 0 2006.257.11:47:57.23#ibcon#about to read 4, iclass 16, count 0 2006.257.11:47:57.23#ibcon#read 4, iclass 16, count 0 2006.257.11:47:57.23#ibcon#about to read 5, iclass 16, count 0 2006.257.11:47:57.23#ibcon#read 5, iclass 16, count 0 2006.257.11:47:57.23#ibcon#about to read 6, iclass 16, count 0 2006.257.11:47:57.23#ibcon#read 6, iclass 16, count 0 2006.257.11:47:57.23#ibcon#end of sib2, iclass 16, count 0 2006.257.11:47:57.23#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:47:57.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:47:57.23#ibcon#[25=USB\r\n] 2006.257.11:47:57.23#ibcon#*before write, iclass 16, count 0 2006.257.11:47:57.23#ibcon#enter sib2, iclass 16, count 0 2006.257.11:47:57.23#ibcon#flushed, iclass 16, count 0 2006.257.11:47:57.23#ibcon#about to write, iclass 16, count 0 2006.257.11:47:57.23#ibcon#wrote, iclass 16, count 0 2006.257.11:47:57.23#ibcon#about to read 3, iclass 16, count 0 2006.257.11:47:57.26#ibcon#read 3, iclass 16, count 0 2006.257.11:47:57.26#ibcon#about to read 4, iclass 16, count 0 2006.257.11:47:57.26#ibcon#read 4, iclass 16, count 0 2006.257.11:47:57.26#ibcon#about to read 5, iclass 16, count 0 2006.257.11:47:57.26#ibcon#read 5, iclass 16, count 0 2006.257.11:47:57.26#ibcon#about to read 6, iclass 16, count 0 2006.257.11:47:57.26#ibcon#read 6, iclass 16, count 0 2006.257.11:47:57.26#ibcon#end of sib2, iclass 16, count 0 2006.257.11:47:57.26#ibcon#*after write, iclass 16, count 0 2006.257.11:47:57.26#ibcon#*before return 0, iclass 16, count 0 2006.257.11:47:57.26#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:47:57.26#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:47:57.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:47:57.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:47:57.26$vck44/valo=5,734.99 2006.257.11:47:57.26#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.11:47:57.26#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.11:47:57.26#ibcon#ireg 17 cls_cnt 0 2006.257.11:47:57.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:47:57.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:47:57.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:47:57.26#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:47:57.26#ibcon#first serial, iclass 18, count 0 2006.257.11:47:57.26#ibcon#enter sib2, iclass 18, count 0 2006.257.11:47:57.26#ibcon#flushed, iclass 18, count 0 2006.257.11:47:57.26#ibcon#about to write, iclass 18, count 0 2006.257.11:47:57.26#ibcon#wrote, iclass 18, count 0 2006.257.11:47:57.26#ibcon#about to read 3, iclass 18, count 0 2006.257.11:47:57.28#ibcon#read 3, iclass 18, count 0 2006.257.11:47:57.28#ibcon#about to read 4, iclass 18, count 0 2006.257.11:47:57.28#ibcon#read 4, iclass 18, count 0 2006.257.11:47:57.28#ibcon#about to read 5, iclass 18, count 0 2006.257.11:47:57.28#ibcon#read 5, iclass 18, count 0 2006.257.11:47:57.28#ibcon#about to read 6, iclass 18, count 0 2006.257.11:47:57.28#ibcon#read 6, iclass 18, count 0 2006.257.11:47:57.28#ibcon#end of sib2, iclass 18, count 0 2006.257.11:47:57.28#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:47:57.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:47:57.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:47:57.28#ibcon#*before write, iclass 18, count 0 2006.257.11:47:57.28#ibcon#enter sib2, iclass 18, count 0 2006.257.11:47:57.28#ibcon#flushed, iclass 18, count 0 2006.257.11:47:57.28#ibcon#about to write, iclass 18, count 0 2006.257.11:47:57.28#ibcon#wrote, iclass 18, count 0 2006.257.11:47:57.28#ibcon#about to read 3, iclass 18, count 0 2006.257.11:47:57.32#ibcon#read 3, iclass 18, count 0 2006.257.11:47:57.32#ibcon#about to read 4, iclass 18, count 0 2006.257.11:47:57.32#ibcon#read 4, iclass 18, count 0 2006.257.11:47:57.32#ibcon#about to read 5, iclass 18, count 0 2006.257.11:47:57.32#ibcon#read 5, iclass 18, count 0 2006.257.11:47:57.32#ibcon#about to read 6, iclass 18, count 0 2006.257.11:47:57.32#ibcon#read 6, iclass 18, count 0 2006.257.11:47:57.32#ibcon#end of sib2, iclass 18, count 0 2006.257.11:47:57.32#ibcon#*after write, iclass 18, count 0 2006.257.11:47:57.32#ibcon#*before return 0, iclass 18, count 0 2006.257.11:47:57.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:47:57.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:47:57.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:47:57.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:47:57.32$vck44/va=5,4 2006.257.11:47:57.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.11:47:57.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.11:47:57.32#ibcon#ireg 11 cls_cnt 2 2006.257.11:47:57.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:47:57.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:47:57.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:47:57.38#ibcon#enter wrdev, iclass 20, count 2 2006.257.11:47:57.38#ibcon#first serial, iclass 20, count 2 2006.257.11:47:57.38#ibcon#enter sib2, iclass 20, count 2 2006.257.11:47:57.38#ibcon#flushed, iclass 20, count 2 2006.257.11:47:57.38#ibcon#about to write, iclass 20, count 2 2006.257.11:47:57.38#ibcon#wrote, iclass 20, count 2 2006.257.11:47:57.38#ibcon#about to read 3, iclass 20, count 2 2006.257.11:47:57.40#ibcon#read 3, iclass 20, count 2 2006.257.11:47:57.40#ibcon#about to read 4, iclass 20, count 2 2006.257.11:47:57.40#ibcon#read 4, iclass 20, count 2 2006.257.11:47:57.40#ibcon#about to read 5, iclass 20, count 2 2006.257.11:47:57.40#ibcon#read 5, iclass 20, count 2 2006.257.11:47:57.40#ibcon#about to read 6, iclass 20, count 2 2006.257.11:47:57.40#ibcon#read 6, iclass 20, count 2 2006.257.11:47:57.40#ibcon#end of sib2, iclass 20, count 2 2006.257.11:47:57.40#ibcon#*mode == 0, iclass 20, count 2 2006.257.11:47:57.40#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.11:47:57.40#ibcon#[25=AT05-04\r\n] 2006.257.11:47:57.40#ibcon#*before write, iclass 20, count 2 2006.257.11:47:57.40#ibcon#enter sib2, iclass 20, count 2 2006.257.11:47:57.40#ibcon#flushed, iclass 20, count 2 2006.257.11:47:57.40#ibcon#about to write, iclass 20, count 2 2006.257.11:47:57.40#ibcon#wrote, iclass 20, count 2 2006.257.11:47:57.40#ibcon#about to read 3, iclass 20, count 2 2006.257.11:47:57.43#ibcon#read 3, iclass 20, count 2 2006.257.11:47:57.43#ibcon#about to read 4, iclass 20, count 2 2006.257.11:47:57.43#ibcon#read 4, iclass 20, count 2 2006.257.11:47:57.43#ibcon#about to read 5, iclass 20, count 2 2006.257.11:47:57.43#ibcon#read 5, iclass 20, count 2 2006.257.11:47:57.43#ibcon#about to read 6, iclass 20, count 2 2006.257.11:47:57.43#ibcon#read 6, iclass 20, count 2 2006.257.11:47:57.43#ibcon#end of sib2, iclass 20, count 2 2006.257.11:47:57.43#ibcon#*after write, iclass 20, count 2 2006.257.11:47:57.43#ibcon#*before return 0, iclass 20, count 2 2006.257.11:47:57.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:47:57.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:47:57.43#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.11:47:57.43#ibcon#ireg 7 cls_cnt 0 2006.257.11:47:57.43#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:47:57.55#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:47:57.55#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:47:57.55#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:47:57.55#ibcon#first serial, iclass 20, count 0 2006.257.11:47:57.55#ibcon#enter sib2, iclass 20, count 0 2006.257.11:47:57.55#ibcon#flushed, iclass 20, count 0 2006.257.11:47:57.55#ibcon#about to write, iclass 20, count 0 2006.257.11:47:57.55#ibcon#wrote, iclass 20, count 0 2006.257.11:47:57.55#ibcon#about to read 3, iclass 20, count 0 2006.257.11:47:57.57#ibcon#read 3, iclass 20, count 0 2006.257.11:47:57.57#ibcon#about to read 4, iclass 20, count 0 2006.257.11:47:57.57#ibcon#read 4, iclass 20, count 0 2006.257.11:47:57.57#ibcon#about to read 5, iclass 20, count 0 2006.257.11:47:57.57#ibcon#read 5, iclass 20, count 0 2006.257.11:47:57.57#ibcon#about to read 6, iclass 20, count 0 2006.257.11:47:57.57#ibcon#read 6, iclass 20, count 0 2006.257.11:47:57.57#ibcon#end of sib2, iclass 20, count 0 2006.257.11:47:57.57#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:47:57.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:47:57.57#ibcon#[25=USB\r\n] 2006.257.11:47:57.57#ibcon#*before write, iclass 20, count 0 2006.257.11:47:57.57#ibcon#enter sib2, iclass 20, count 0 2006.257.11:47:57.57#ibcon#flushed, iclass 20, count 0 2006.257.11:47:57.57#ibcon#about to write, iclass 20, count 0 2006.257.11:47:57.57#ibcon#wrote, iclass 20, count 0 2006.257.11:47:57.57#ibcon#about to read 3, iclass 20, count 0 2006.257.11:47:57.60#ibcon#read 3, iclass 20, count 0 2006.257.11:47:57.60#ibcon#about to read 4, iclass 20, count 0 2006.257.11:47:57.60#ibcon#read 4, iclass 20, count 0 2006.257.11:47:57.60#ibcon#about to read 5, iclass 20, count 0 2006.257.11:47:57.60#ibcon#read 5, iclass 20, count 0 2006.257.11:47:57.60#ibcon#about to read 6, iclass 20, count 0 2006.257.11:47:57.60#ibcon#read 6, iclass 20, count 0 2006.257.11:47:57.60#ibcon#end of sib2, iclass 20, count 0 2006.257.11:47:57.60#ibcon#*after write, iclass 20, count 0 2006.257.11:47:57.60#ibcon#*before return 0, iclass 20, count 0 2006.257.11:47:57.60#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:47:57.60#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:47:57.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:47:57.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:47:57.60$vck44/valo=6,814.99 2006.257.11:47:57.60#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.11:47:57.60#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.11:47:57.60#ibcon#ireg 17 cls_cnt 0 2006.257.11:47:57.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:47:57.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:47:57.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:47:57.60#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:47:57.60#ibcon#first serial, iclass 22, count 0 2006.257.11:47:57.60#ibcon#enter sib2, iclass 22, count 0 2006.257.11:47:57.60#ibcon#flushed, iclass 22, count 0 2006.257.11:47:57.60#ibcon#about to write, iclass 22, count 0 2006.257.11:47:57.60#ibcon#wrote, iclass 22, count 0 2006.257.11:47:57.60#ibcon#about to read 3, iclass 22, count 0 2006.257.11:47:57.62#ibcon#read 3, iclass 22, count 0 2006.257.11:47:57.62#ibcon#about to read 4, iclass 22, count 0 2006.257.11:47:57.62#ibcon#read 4, iclass 22, count 0 2006.257.11:47:57.62#ibcon#about to read 5, iclass 22, count 0 2006.257.11:47:57.62#ibcon#read 5, iclass 22, count 0 2006.257.11:47:57.62#ibcon#about to read 6, iclass 22, count 0 2006.257.11:47:57.62#ibcon#read 6, iclass 22, count 0 2006.257.11:47:57.62#ibcon#end of sib2, iclass 22, count 0 2006.257.11:47:57.62#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:47:57.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:47:57.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:47:57.62#ibcon#*before write, iclass 22, count 0 2006.257.11:47:57.62#ibcon#enter sib2, iclass 22, count 0 2006.257.11:47:57.62#ibcon#flushed, iclass 22, count 0 2006.257.11:47:57.62#ibcon#about to write, iclass 22, count 0 2006.257.11:47:57.62#ibcon#wrote, iclass 22, count 0 2006.257.11:47:57.62#ibcon#about to read 3, iclass 22, count 0 2006.257.11:47:57.66#ibcon#read 3, iclass 22, count 0 2006.257.11:47:57.66#ibcon#about to read 4, iclass 22, count 0 2006.257.11:47:57.66#ibcon#read 4, iclass 22, count 0 2006.257.11:47:57.66#ibcon#about to read 5, iclass 22, count 0 2006.257.11:47:57.66#ibcon#read 5, iclass 22, count 0 2006.257.11:47:57.66#ibcon#about to read 6, iclass 22, count 0 2006.257.11:47:57.66#ibcon#read 6, iclass 22, count 0 2006.257.11:47:57.66#ibcon#end of sib2, iclass 22, count 0 2006.257.11:47:57.66#ibcon#*after write, iclass 22, count 0 2006.257.11:47:57.66#ibcon#*before return 0, iclass 22, count 0 2006.257.11:47:57.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:47:57.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:47:57.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:47:57.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:47:57.66$vck44/va=6,4 2006.257.11:47:57.66#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.11:47:57.66#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.11:47:57.66#ibcon#ireg 11 cls_cnt 2 2006.257.11:47:57.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:47:57.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:47:57.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:47:57.72#ibcon#enter wrdev, iclass 24, count 2 2006.257.11:47:57.72#ibcon#first serial, iclass 24, count 2 2006.257.11:47:57.72#ibcon#enter sib2, iclass 24, count 2 2006.257.11:47:57.72#ibcon#flushed, iclass 24, count 2 2006.257.11:47:57.72#ibcon#about to write, iclass 24, count 2 2006.257.11:47:57.72#ibcon#wrote, iclass 24, count 2 2006.257.11:47:57.72#ibcon#about to read 3, iclass 24, count 2 2006.257.11:47:57.74#ibcon#read 3, iclass 24, count 2 2006.257.11:47:57.74#ibcon#about to read 4, iclass 24, count 2 2006.257.11:47:57.74#ibcon#read 4, iclass 24, count 2 2006.257.11:47:57.74#ibcon#about to read 5, iclass 24, count 2 2006.257.11:47:57.74#ibcon#read 5, iclass 24, count 2 2006.257.11:47:57.74#ibcon#about to read 6, iclass 24, count 2 2006.257.11:47:57.74#ibcon#read 6, iclass 24, count 2 2006.257.11:47:57.74#ibcon#end of sib2, iclass 24, count 2 2006.257.11:47:57.74#ibcon#*mode == 0, iclass 24, count 2 2006.257.11:47:57.74#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.11:47:57.74#ibcon#[25=AT06-04\r\n] 2006.257.11:47:57.74#ibcon#*before write, iclass 24, count 2 2006.257.11:47:57.74#ibcon#enter sib2, iclass 24, count 2 2006.257.11:47:57.74#ibcon#flushed, iclass 24, count 2 2006.257.11:47:57.74#ibcon#about to write, iclass 24, count 2 2006.257.11:47:57.74#ibcon#wrote, iclass 24, count 2 2006.257.11:47:57.74#ibcon#about to read 3, iclass 24, count 2 2006.257.11:47:57.77#ibcon#read 3, iclass 24, count 2 2006.257.11:47:57.77#ibcon#about to read 4, iclass 24, count 2 2006.257.11:47:57.77#ibcon#read 4, iclass 24, count 2 2006.257.11:47:57.77#ibcon#about to read 5, iclass 24, count 2 2006.257.11:47:57.77#ibcon#read 5, iclass 24, count 2 2006.257.11:47:57.77#ibcon#about to read 6, iclass 24, count 2 2006.257.11:47:57.77#ibcon#read 6, iclass 24, count 2 2006.257.11:47:57.77#ibcon#end of sib2, iclass 24, count 2 2006.257.11:47:57.77#ibcon#*after write, iclass 24, count 2 2006.257.11:47:57.77#ibcon#*before return 0, iclass 24, count 2 2006.257.11:47:57.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:47:57.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:47:57.77#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.11:47:57.77#ibcon#ireg 7 cls_cnt 0 2006.257.11:47:57.77#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:47:57.89#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:47:57.89#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:47:57.89#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:47:57.89#ibcon#first serial, iclass 24, count 0 2006.257.11:47:57.89#ibcon#enter sib2, iclass 24, count 0 2006.257.11:47:57.89#ibcon#flushed, iclass 24, count 0 2006.257.11:47:57.89#ibcon#about to write, iclass 24, count 0 2006.257.11:47:57.89#ibcon#wrote, iclass 24, count 0 2006.257.11:47:57.89#ibcon#about to read 3, iclass 24, count 0 2006.257.11:47:57.91#ibcon#read 3, iclass 24, count 0 2006.257.11:47:57.91#ibcon#about to read 4, iclass 24, count 0 2006.257.11:47:57.91#ibcon#read 4, iclass 24, count 0 2006.257.11:47:57.91#ibcon#about to read 5, iclass 24, count 0 2006.257.11:47:57.91#ibcon#read 5, iclass 24, count 0 2006.257.11:47:57.91#ibcon#about to read 6, iclass 24, count 0 2006.257.11:47:57.91#ibcon#read 6, iclass 24, count 0 2006.257.11:47:57.91#ibcon#end of sib2, iclass 24, count 0 2006.257.11:47:57.91#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:47:57.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:47:57.91#ibcon#[25=USB\r\n] 2006.257.11:47:57.91#ibcon#*before write, iclass 24, count 0 2006.257.11:47:57.91#ibcon#enter sib2, iclass 24, count 0 2006.257.11:47:57.91#ibcon#flushed, iclass 24, count 0 2006.257.11:47:57.91#ibcon#about to write, iclass 24, count 0 2006.257.11:47:57.91#ibcon#wrote, iclass 24, count 0 2006.257.11:47:57.91#ibcon#about to read 3, iclass 24, count 0 2006.257.11:47:57.94#ibcon#read 3, iclass 24, count 0 2006.257.11:47:57.94#ibcon#about to read 4, iclass 24, count 0 2006.257.11:47:57.94#ibcon#read 4, iclass 24, count 0 2006.257.11:47:57.94#ibcon#about to read 5, iclass 24, count 0 2006.257.11:47:57.94#ibcon#read 5, iclass 24, count 0 2006.257.11:47:57.94#ibcon#about to read 6, iclass 24, count 0 2006.257.11:47:57.94#ibcon#read 6, iclass 24, count 0 2006.257.11:47:57.94#ibcon#end of sib2, iclass 24, count 0 2006.257.11:47:57.94#ibcon#*after write, iclass 24, count 0 2006.257.11:47:57.94#ibcon#*before return 0, iclass 24, count 0 2006.257.11:47:57.94#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:47:57.94#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:47:57.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:47:57.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:47:57.94$vck44/valo=7,864.99 2006.257.11:47:57.94#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.11:47:57.94#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.11:47:57.94#ibcon#ireg 17 cls_cnt 0 2006.257.11:47:57.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:47:57.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:47:57.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:47:57.94#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:47:57.94#ibcon#first serial, iclass 26, count 0 2006.257.11:47:57.94#ibcon#enter sib2, iclass 26, count 0 2006.257.11:47:57.94#ibcon#flushed, iclass 26, count 0 2006.257.11:47:57.94#ibcon#about to write, iclass 26, count 0 2006.257.11:47:57.94#ibcon#wrote, iclass 26, count 0 2006.257.11:47:57.94#ibcon#about to read 3, iclass 26, count 0 2006.257.11:47:57.96#ibcon#read 3, iclass 26, count 0 2006.257.11:47:57.96#ibcon#about to read 4, iclass 26, count 0 2006.257.11:47:57.96#ibcon#read 4, iclass 26, count 0 2006.257.11:47:57.96#ibcon#about to read 5, iclass 26, count 0 2006.257.11:47:57.96#ibcon#read 5, iclass 26, count 0 2006.257.11:47:57.96#ibcon#about to read 6, iclass 26, count 0 2006.257.11:47:57.96#ibcon#read 6, iclass 26, count 0 2006.257.11:47:57.96#ibcon#end of sib2, iclass 26, count 0 2006.257.11:47:57.96#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:47:57.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:47:57.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:47:57.96#ibcon#*before write, iclass 26, count 0 2006.257.11:47:57.96#ibcon#enter sib2, iclass 26, count 0 2006.257.11:47:57.96#ibcon#flushed, iclass 26, count 0 2006.257.11:47:57.96#ibcon#about to write, iclass 26, count 0 2006.257.11:47:57.96#ibcon#wrote, iclass 26, count 0 2006.257.11:47:57.96#ibcon#about to read 3, iclass 26, count 0 2006.257.11:47:58.00#ibcon#read 3, iclass 26, count 0 2006.257.11:47:58.00#ibcon#about to read 4, iclass 26, count 0 2006.257.11:47:58.00#ibcon#read 4, iclass 26, count 0 2006.257.11:47:58.00#ibcon#about to read 5, iclass 26, count 0 2006.257.11:47:58.00#ibcon#read 5, iclass 26, count 0 2006.257.11:47:58.00#ibcon#about to read 6, iclass 26, count 0 2006.257.11:47:58.00#ibcon#read 6, iclass 26, count 0 2006.257.11:47:58.00#ibcon#end of sib2, iclass 26, count 0 2006.257.11:47:58.00#ibcon#*after write, iclass 26, count 0 2006.257.11:47:58.00#ibcon#*before return 0, iclass 26, count 0 2006.257.11:47:58.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:47:58.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:47:58.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:47:58.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:47:58.00$vck44/va=7,4 2006.257.11:47:58.00#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.11:47:58.00#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.11:47:58.00#ibcon#ireg 11 cls_cnt 2 2006.257.11:47:58.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:47:58.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:47:58.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:47:58.06#ibcon#enter wrdev, iclass 28, count 2 2006.257.11:47:58.06#ibcon#first serial, iclass 28, count 2 2006.257.11:47:58.06#ibcon#enter sib2, iclass 28, count 2 2006.257.11:47:58.06#ibcon#flushed, iclass 28, count 2 2006.257.11:47:58.06#ibcon#about to write, iclass 28, count 2 2006.257.11:47:58.06#ibcon#wrote, iclass 28, count 2 2006.257.11:47:58.06#ibcon#about to read 3, iclass 28, count 2 2006.257.11:47:58.08#ibcon#read 3, iclass 28, count 2 2006.257.11:47:58.08#ibcon#about to read 4, iclass 28, count 2 2006.257.11:47:58.08#ibcon#read 4, iclass 28, count 2 2006.257.11:47:58.08#ibcon#about to read 5, iclass 28, count 2 2006.257.11:47:58.08#ibcon#read 5, iclass 28, count 2 2006.257.11:47:58.08#ibcon#about to read 6, iclass 28, count 2 2006.257.11:47:58.08#ibcon#read 6, iclass 28, count 2 2006.257.11:47:58.08#ibcon#end of sib2, iclass 28, count 2 2006.257.11:47:58.08#ibcon#*mode == 0, iclass 28, count 2 2006.257.11:47:58.08#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.11:47:58.08#ibcon#[25=AT07-04\r\n] 2006.257.11:47:58.08#ibcon#*before write, iclass 28, count 2 2006.257.11:47:58.08#ibcon#enter sib2, iclass 28, count 2 2006.257.11:47:58.08#ibcon#flushed, iclass 28, count 2 2006.257.11:47:58.08#ibcon#about to write, iclass 28, count 2 2006.257.11:47:58.08#ibcon#wrote, iclass 28, count 2 2006.257.11:47:58.08#ibcon#about to read 3, iclass 28, count 2 2006.257.11:47:58.11#ibcon#read 3, iclass 28, count 2 2006.257.11:47:59.22#ibcon#about to read 4, iclass 28, count 2 2006.257.11:47:59.22#ibcon#read 4, iclass 28, count 2 2006.257.11:47:59.22#ibcon#about to read 5, iclass 28, count 2 2006.257.11:47:59.22#ibcon#read 5, iclass 28, count 2 2006.257.11:47:59.22#ibcon#about to read 6, iclass 28, count 2 2006.257.11:47:59.22#ibcon#read 6, iclass 28, count 2 2006.257.11:47:59.22#ibcon#end of sib2, iclass 28, count 2 2006.257.11:47:59.22#ibcon#*after write, iclass 28, count 2 2006.257.11:47:59.22#ibcon#*before return 0, iclass 28, count 2 2006.257.11:47:59.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:47:59.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:47:59.22#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.11:47:59.22#ibcon#ireg 7 cls_cnt 0 2006.257.11:47:59.22#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:47:59.34#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:47:59.34#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:47:59.34#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:47:59.34#ibcon#first serial, iclass 28, count 0 2006.257.11:47:59.34#ibcon#enter sib2, iclass 28, count 0 2006.257.11:47:59.34#ibcon#flushed, iclass 28, count 0 2006.257.11:47:59.34#ibcon#about to write, iclass 28, count 0 2006.257.11:47:59.34#ibcon#wrote, iclass 28, count 0 2006.257.11:47:59.34#ibcon#about to read 3, iclass 28, count 0 2006.257.11:47:59.36#ibcon#read 3, iclass 28, count 0 2006.257.11:47:59.36#ibcon#about to read 4, iclass 28, count 0 2006.257.11:47:59.36#ibcon#read 4, iclass 28, count 0 2006.257.11:47:59.36#ibcon#about to read 5, iclass 28, count 0 2006.257.11:47:59.36#ibcon#read 5, iclass 28, count 0 2006.257.11:47:59.36#ibcon#about to read 6, iclass 28, count 0 2006.257.11:47:59.36#ibcon#read 6, iclass 28, count 0 2006.257.11:47:59.36#ibcon#end of sib2, iclass 28, count 0 2006.257.11:47:59.36#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:47:59.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:47:59.36#ibcon#[25=USB\r\n] 2006.257.11:47:59.36#ibcon#*before write, iclass 28, count 0 2006.257.11:47:59.36#ibcon#enter sib2, iclass 28, count 0 2006.257.11:47:59.36#ibcon#flushed, iclass 28, count 0 2006.257.11:47:59.36#ibcon#about to write, iclass 28, count 0 2006.257.11:47:59.36#ibcon#wrote, iclass 28, count 0 2006.257.11:47:59.36#ibcon#about to read 3, iclass 28, count 0 2006.257.11:47:59.37#abcon#<5=/13 1.3 3.8 18.16 951014.0\r\n> 2006.257.11:47:59.39#abcon#{5=INTERFACE CLEAR} 2006.257.11:47:59.39#ibcon#read 3, iclass 28, count 0 2006.257.11:47:59.39#ibcon#about to read 4, iclass 28, count 0 2006.257.11:47:59.39#ibcon#read 4, iclass 28, count 0 2006.257.11:47:59.39#ibcon#about to read 5, iclass 28, count 0 2006.257.11:47:59.39#ibcon#read 5, iclass 28, count 0 2006.257.11:47:59.39#ibcon#about to read 6, iclass 28, count 0 2006.257.11:47:59.39#ibcon#read 6, iclass 28, count 0 2006.257.11:47:59.39#ibcon#end of sib2, iclass 28, count 0 2006.257.11:47:59.39#ibcon#*after write, iclass 28, count 0 2006.257.11:47:59.39#ibcon#*before return 0, iclass 28, count 0 2006.257.11:47:59.39#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:47:59.39#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:47:59.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:47:59.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:47:59.39$vck44/valo=8,884.99 2006.257.11:47:59.39#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.11:47:59.39#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.11:47:59.39#ibcon#ireg 17 cls_cnt 0 2006.257.11:47:59.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:47:59.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:47:59.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:47:59.39#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:47:59.39#ibcon#first serial, iclass 33, count 0 2006.257.11:47:59.39#ibcon#enter sib2, iclass 33, count 0 2006.257.11:47:59.39#ibcon#flushed, iclass 33, count 0 2006.257.11:47:59.39#ibcon#about to write, iclass 33, count 0 2006.257.11:47:59.39#ibcon#wrote, iclass 33, count 0 2006.257.11:47:59.39#ibcon#about to read 3, iclass 33, count 0 2006.257.11:47:59.41#ibcon#read 3, iclass 33, count 0 2006.257.11:47:59.41#ibcon#about to read 4, iclass 33, count 0 2006.257.11:47:59.41#ibcon#read 4, iclass 33, count 0 2006.257.11:47:59.41#ibcon#about to read 5, iclass 33, count 0 2006.257.11:47:59.41#ibcon#read 5, iclass 33, count 0 2006.257.11:47:59.41#ibcon#about to read 6, iclass 33, count 0 2006.257.11:47:59.41#ibcon#read 6, iclass 33, count 0 2006.257.11:47:59.41#ibcon#end of sib2, iclass 33, count 0 2006.257.11:47:59.41#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:47:59.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:47:59.41#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:47:59.41#ibcon#*before write, iclass 33, count 0 2006.257.11:47:59.41#ibcon#enter sib2, iclass 33, count 0 2006.257.11:47:59.41#ibcon#flushed, iclass 33, count 0 2006.257.11:47:59.41#ibcon#about to write, iclass 33, count 0 2006.257.11:47:59.41#ibcon#wrote, iclass 33, count 0 2006.257.11:47:59.41#ibcon#about to read 3, iclass 33, count 0 2006.257.11:47:59.45#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:47:59.45#ibcon#read 3, iclass 33, count 0 2006.257.11:47:59.45#ibcon#about to read 4, iclass 33, count 0 2006.257.11:47:59.45#ibcon#read 4, iclass 33, count 0 2006.257.11:47:59.45#ibcon#about to read 5, iclass 33, count 0 2006.257.11:47:59.45#ibcon#read 5, iclass 33, count 0 2006.257.11:47:59.45#ibcon#about to read 6, iclass 33, count 0 2006.257.11:47:59.45#ibcon#read 6, iclass 33, count 0 2006.257.11:47:59.45#ibcon#end of sib2, iclass 33, count 0 2006.257.11:47:59.45#ibcon#*after write, iclass 33, count 0 2006.257.11:47:59.45#ibcon#*before return 0, iclass 33, count 0 2006.257.11:47:59.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:47:59.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:47:59.45#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:47:59.45#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:47:59.45$vck44/va=8,4 2006.257.11:47:59.45#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.11:47:59.45#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.11:47:59.45#ibcon#ireg 11 cls_cnt 2 2006.257.11:47:59.45#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:47:59.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:47:59.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:47:59.51#ibcon#enter wrdev, iclass 36, count 2 2006.257.11:47:59.51#ibcon#first serial, iclass 36, count 2 2006.257.11:47:59.51#ibcon#enter sib2, iclass 36, count 2 2006.257.11:47:59.51#ibcon#flushed, iclass 36, count 2 2006.257.11:47:59.51#ibcon#about to write, iclass 36, count 2 2006.257.11:47:59.51#ibcon#wrote, iclass 36, count 2 2006.257.11:47:59.51#ibcon#about to read 3, iclass 36, count 2 2006.257.11:47:59.53#ibcon#read 3, iclass 36, count 2 2006.257.11:47:59.53#ibcon#about to read 4, iclass 36, count 2 2006.257.11:47:59.53#ibcon#read 4, iclass 36, count 2 2006.257.11:47:59.53#ibcon#about to read 5, iclass 36, count 2 2006.257.11:47:59.53#ibcon#read 5, iclass 36, count 2 2006.257.11:47:59.53#ibcon#about to read 6, iclass 36, count 2 2006.257.11:47:59.53#ibcon#read 6, iclass 36, count 2 2006.257.11:47:59.53#ibcon#end of sib2, iclass 36, count 2 2006.257.11:47:59.53#ibcon#*mode == 0, iclass 36, count 2 2006.257.11:47:59.53#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.11:47:59.53#ibcon#[25=AT08-04\r\n] 2006.257.11:47:59.53#ibcon#*before write, iclass 36, count 2 2006.257.11:47:59.53#ibcon#enter sib2, iclass 36, count 2 2006.257.11:47:59.53#ibcon#flushed, iclass 36, count 2 2006.257.11:47:59.53#ibcon#about to write, iclass 36, count 2 2006.257.11:47:59.53#ibcon#wrote, iclass 36, count 2 2006.257.11:47:59.53#ibcon#about to read 3, iclass 36, count 2 2006.257.11:47:59.56#ibcon#read 3, iclass 36, count 2 2006.257.11:47:59.56#ibcon#about to read 4, iclass 36, count 2 2006.257.11:47:59.56#ibcon#read 4, iclass 36, count 2 2006.257.11:47:59.56#ibcon#about to read 5, iclass 36, count 2 2006.257.11:47:59.56#ibcon#read 5, iclass 36, count 2 2006.257.11:47:59.56#ibcon#about to read 6, iclass 36, count 2 2006.257.11:47:59.56#ibcon#read 6, iclass 36, count 2 2006.257.11:47:59.56#ibcon#end of sib2, iclass 36, count 2 2006.257.11:47:59.56#ibcon#*after write, iclass 36, count 2 2006.257.11:47:59.56#ibcon#*before return 0, iclass 36, count 2 2006.257.11:47:59.56#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:47:59.56#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.11:47:59.56#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.11:47:59.56#ibcon#ireg 7 cls_cnt 0 2006.257.11:47:59.56#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:47:59.68#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:47:59.68#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:47:59.68#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:47:59.68#ibcon#first serial, iclass 36, count 0 2006.257.11:47:59.68#ibcon#enter sib2, iclass 36, count 0 2006.257.11:47:59.68#ibcon#flushed, iclass 36, count 0 2006.257.11:47:59.68#ibcon#about to write, iclass 36, count 0 2006.257.11:47:59.68#ibcon#wrote, iclass 36, count 0 2006.257.11:47:59.68#ibcon#about to read 3, iclass 36, count 0 2006.257.11:47:59.70#ibcon#read 3, iclass 36, count 0 2006.257.11:47:59.70#ibcon#about to read 4, iclass 36, count 0 2006.257.11:47:59.70#ibcon#read 4, iclass 36, count 0 2006.257.11:47:59.70#ibcon#about to read 5, iclass 36, count 0 2006.257.11:47:59.70#ibcon#read 5, iclass 36, count 0 2006.257.11:47:59.70#ibcon#about to read 6, iclass 36, count 0 2006.257.11:47:59.70#ibcon#read 6, iclass 36, count 0 2006.257.11:47:59.70#ibcon#end of sib2, iclass 36, count 0 2006.257.11:47:59.70#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:47:59.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:47:59.70#ibcon#[25=USB\r\n] 2006.257.11:47:59.70#ibcon#*before write, iclass 36, count 0 2006.257.11:47:59.70#ibcon#enter sib2, iclass 36, count 0 2006.257.11:47:59.70#ibcon#flushed, iclass 36, count 0 2006.257.11:47:59.70#ibcon#about to write, iclass 36, count 0 2006.257.11:47:59.70#ibcon#wrote, iclass 36, count 0 2006.257.11:47:59.70#ibcon#about to read 3, iclass 36, count 0 2006.257.11:47:59.73#ibcon#read 3, iclass 36, count 0 2006.257.11:47:59.73#ibcon#about to read 4, iclass 36, count 0 2006.257.11:47:59.73#ibcon#read 4, iclass 36, count 0 2006.257.11:47:59.73#ibcon#about to read 5, iclass 36, count 0 2006.257.11:47:59.73#ibcon#read 5, iclass 36, count 0 2006.257.11:47:59.73#ibcon#about to read 6, iclass 36, count 0 2006.257.11:47:59.73#ibcon#read 6, iclass 36, count 0 2006.257.11:47:59.73#ibcon#end of sib2, iclass 36, count 0 2006.257.11:47:59.73#ibcon#*after write, iclass 36, count 0 2006.257.11:47:59.73#ibcon#*before return 0, iclass 36, count 0 2006.257.11:47:59.73#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:47:59.73#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.11:47:59.73#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:47:59.73#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:47:59.73$vck44/vblo=1,629.99 2006.257.11:47:59.73#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.11:47:59.73#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.11:47:59.73#ibcon#ireg 17 cls_cnt 0 2006.257.11:47:59.73#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:59.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:59.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:59.73#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:47:59.73#ibcon#first serial, iclass 38, count 0 2006.257.11:47:59.73#ibcon#enter sib2, iclass 38, count 0 2006.257.11:47:59.73#ibcon#flushed, iclass 38, count 0 2006.257.11:47:59.73#ibcon#about to write, iclass 38, count 0 2006.257.11:47:59.73#ibcon#wrote, iclass 38, count 0 2006.257.11:47:59.73#ibcon#about to read 3, iclass 38, count 0 2006.257.11:47:59.75#ibcon#read 3, iclass 38, count 0 2006.257.11:47:59.75#ibcon#about to read 4, iclass 38, count 0 2006.257.11:47:59.75#ibcon#read 4, iclass 38, count 0 2006.257.11:47:59.75#ibcon#about to read 5, iclass 38, count 0 2006.257.11:47:59.75#ibcon#read 5, iclass 38, count 0 2006.257.11:47:59.75#ibcon#about to read 6, iclass 38, count 0 2006.257.11:47:59.75#ibcon#read 6, iclass 38, count 0 2006.257.11:47:59.75#ibcon#end of sib2, iclass 38, count 0 2006.257.11:47:59.75#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:47:59.75#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:47:59.75#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:47:59.75#ibcon#*before write, iclass 38, count 0 2006.257.11:47:59.75#ibcon#enter sib2, iclass 38, count 0 2006.257.11:47:59.75#ibcon#flushed, iclass 38, count 0 2006.257.11:47:59.75#ibcon#about to write, iclass 38, count 0 2006.257.11:47:59.75#ibcon#wrote, iclass 38, count 0 2006.257.11:47:59.75#ibcon#about to read 3, iclass 38, count 0 2006.257.11:47:59.79#ibcon#read 3, iclass 38, count 0 2006.257.11:47:59.79#ibcon#about to read 4, iclass 38, count 0 2006.257.11:47:59.79#ibcon#read 4, iclass 38, count 0 2006.257.11:47:59.79#ibcon#about to read 5, iclass 38, count 0 2006.257.11:47:59.79#ibcon#read 5, iclass 38, count 0 2006.257.11:47:59.79#ibcon#about to read 6, iclass 38, count 0 2006.257.11:47:59.79#ibcon#read 6, iclass 38, count 0 2006.257.11:47:59.79#ibcon#end of sib2, iclass 38, count 0 2006.257.11:47:59.79#ibcon#*after write, iclass 38, count 0 2006.257.11:47:59.79#ibcon#*before return 0, iclass 38, count 0 2006.257.11:47:59.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:59.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.11:47:59.79#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:47:59.79#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:47:59.79$vck44/vb=1,4 2006.257.11:47:59.79#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.11:47:59.79#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.11:47:59.79#ibcon#ireg 11 cls_cnt 2 2006.257.11:47:59.79#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:59.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:59.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:59.79#ibcon#enter wrdev, iclass 40, count 2 2006.257.11:47:59.79#ibcon#first serial, iclass 40, count 2 2006.257.11:47:59.79#ibcon#enter sib2, iclass 40, count 2 2006.257.11:47:59.79#ibcon#flushed, iclass 40, count 2 2006.257.11:47:59.79#ibcon#about to write, iclass 40, count 2 2006.257.11:47:59.79#ibcon#wrote, iclass 40, count 2 2006.257.11:47:59.79#ibcon#about to read 3, iclass 40, count 2 2006.257.11:47:59.81#ibcon#read 3, iclass 40, count 2 2006.257.11:47:59.81#ibcon#about to read 4, iclass 40, count 2 2006.257.11:47:59.81#ibcon#read 4, iclass 40, count 2 2006.257.11:47:59.81#ibcon#about to read 5, iclass 40, count 2 2006.257.11:47:59.81#ibcon#read 5, iclass 40, count 2 2006.257.11:47:59.81#ibcon#about to read 6, iclass 40, count 2 2006.257.11:47:59.81#ibcon#read 6, iclass 40, count 2 2006.257.11:47:59.81#ibcon#end of sib2, iclass 40, count 2 2006.257.11:47:59.81#ibcon#*mode == 0, iclass 40, count 2 2006.257.11:47:59.81#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.11:47:59.81#ibcon#[27=AT01-04\r\n] 2006.257.11:47:59.81#ibcon#*before write, iclass 40, count 2 2006.257.11:47:59.81#ibcon#enter sib2, iclass 40, count 2 2006.257.11:47:59.81#ibcon#flushed, iclass 40, count 2 2006.257.11:47:59.81#ibcon#about to write, iclass 40, count 2 2006.257.11:47:59.81#ibcon#wrote, iclass 40, count 2 2006.257.11:47:59.81#ibcon#about to read 3, iclass 40, count 2 2006.257.11:47:59.84#ibcon#read 3, iclass 40, count 2 2006.257.11:47:59.84#ibcon#about to read 4, iclass 40, count 2 2006.257.11:47:59.84#ibcon#read 4, iclass 40, count 2 2006.257.11:47:59.84#ibcon#about to read 5, iclass 40, count 2 2006.257.11:47:59.84#ibcon#read 5, iclass 40, count 2 2006.257.11:47:59.84#ibcon#about to read 6, iclass 40, count 2 2006.257.11:47:59.84#ibcon#read 6, iclass 40, count 2 2006.257.11:47:59.84#ibcon#end of sib2, iclass 40, count 2 2006.257.11:47:59.84#ibcon#*after write, iclass 40, count 2 2006.257.11:47:59.84#ibcon#*before return 0, iclass 40, count 2 2006.257.11:47:59.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:59.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.11:47:59.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.11:47:59.84#ibcon#ireg 7 cls_cnt 0 2006.257.11:47:59.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:47:59.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:47:59.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:47:59.96#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:47:59.96#ibcon#first serial, iclass 40, count 0 2006.257.11:47:59.96#ibcon#enter sib2, iclass 40, count 0 2006.257.11:47:59.96#ibcon#flushed, iclass 40, count 0 2006.257.11:47:59.96#ibcon#about to write, iclass 40, count 0 2006.257.11:47:59.96#ibcon#wrote, iclass 40, count 0 2006.257.11:47:59.96#ibcon#about to read 3, iclass 40, count 0 2006.257.11:47:59.98#ibcon#read 3, iclass 40, count 0 2006.257.11:47:59.98#ibcon#about to read 4, iclass 40, count 0 2006.257.11:47:59.98#ibcon#read 4, iclass 40, count 0 2006.257.11:47:59.98#ibcon#about to read 5, iclass 40, count 0 2006.257.11:47:59.98#ibcon#read 5, iclass 40, count 0 2006.257.11:47:59.98#ibcon#about to read 6, iclass 40, count 0 2006.257.11:47:59.98#ibcon#read 6, iclass 40, count 0 2006.257.11:47:59.98#ibcon#end of sib2, iclass 40, count 0 2006.257.11:47:59.98#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:47:59.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:47:59.98#ibcon#[27=USB\r\n] 2006.257.11:47:59.98#ibcon#*before write, iclass 40, count 0 2006.257.11:47:59.98#ibcon#enter sib2, iclass 40, count 0 2006.257.11:47:59.98#ibcon#flushed, iclass 40, count 0 2006.257.11:47:59.98#ibcon#about to write, iclass 40, count 0 2006.257.11:47:59.98#ibcon#wrote, iclass 40, count 0 2006.257.11:47:59.98#ibcon#about to read 3, iclass 40, count 0 2006.257.11:48:00.01#ibcon#read 3, iclass 40, count 0 2006.257.11:48:00.01#ibcon#about to read 4, iclass 40, count 0 2006.257.11:48:00.01#ibcon#read 4, iclass 40, count 0 2006.257.11:48:00.01#ibcon#about to read 5, iclass 40, count 0 2006.257.11:48:00.01#ibcon#read 5, iclass 40, count 0 2006.257.11:48:00.01#ibcon#about to read 6, iclass 40, count 0 2006.257.11:48:00.01#ibcon#read 6, iclass 40, count 0 2006.257.11:48:00.01#ibcon#end of sib2, iclass 40, count 0 2006.257.11:48:00.01#ibcon#*after write, iclass 40, count 0 2006.257.11:48:00.01#ibcon#*before return 0, iclass 40, count 0 2006.257.11:48:00.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:48:00.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.11:48:00.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:48:00.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:48:00.01$vck44/vblo=2,634.99 2006.257.11:48:00.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.11:48:00.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.11:48:00.01#ibcon#ireg 17 cls_cnt 0 2006.257.11:48:00.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:48:00.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:48:00.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:48:00.01#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:48:00.01#ibcon#first serial, iclass 4, count 0 2006.257.11:48:00.01#ibcon#enter sib2, iclass 4, count 0 2006.257.11:48:00.01#ibcon#flushed, iclass 4, count 0 2006.257.11:48:00.01#ibcon#about to write, iclass 4, count 0 2006.257.11:48:00.01#ibcon#wrote, iclass 4, count 0 2006.257.11:48:00.01#ibcon#about to read 3, iclass 4, count 0 2006.257.11:48:00.03#ibcon#read 3, iclass 4, count 0 2006.257.11:48:00.03#ibcon#about to read 4, iclass 4, count 0 2006.257.11:48:00.03#ibcon#read 4, iclass 4, count 0 2006.257.11:48:00.03#ibcon#about to read 5, iclass 4, count 0 2006.257.11:48:00.03#ibcon#read 5, iclass 4, count 0 2006.257.11:48:00.03#ibcon#about to read 6, iclass 4, count 0 2006.257.11:48:00.03#ibcon#read 6, iclass 4, count 0 2006.257.11:48:00.03#ibcon#end of sib2, iclass 4, count 0 2006.257.11:48:00.03#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:48:00.03#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:48:00.03#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:48:00.03#ibcon#*before write, iclass 4, count 0 2006.257.11:48:00.03#ibcon#enter sib2, iclass 4, count 0 2006.257.11:48:00.03#ibcon#flushed, iclass 4, count 0 2006.257.11:48:00.03#ibcon#about to write, iclass 4, count 0 2006.257.11:48:00.03#ibcon#wrote, iclass 4, count 0 2006.257.11:48:00.03#ibcon#about to read 3, iclass 4, count 0 2006.257.11:48:00.07#ibcon#read 3, iclass 4, count 0 2006.257.11:48:00.07#ibcon#about to read 4, iclass 4, count 0 2006.257.11:48:00.07#ibcon#read 4, iclass 4, count 0 2006.257.11:48:00.07#ibcon#about to read 5, iclass 4, count 0 2006.257.11:48:00.07#ibcon#read 5, iclass 4, count 0 2006.257.11:48:00.07#ibcon#about to read 6, iclass 4, count 0 2006.257.11:48:00.07#ibcon#read 6, iclass 4, count 0 2006.257.11:48:00.07#ibcon#end of sib2, iclass 4, count 0 2006.257.11:48:00.07#ibcon#*after write, iclass 4, count 0 2006.257.11:48:00.07#ibcon#*before return 0, iclass 4, count 0 2006.257.11:48:00.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:48:00.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:48:00.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:48:00.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:48:00.07$vck44/vb=2,5 2006.257.11:48:00.07#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.11:48:00.07#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.11:48:00.07#ibcon#ireg 11 cls_cnt 2 2006.257.11:48:00.07#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:48:00.13#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:48:00.13#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:48:00.13#ibcon#enter wrdev, iclass 6, count 2 2006.257.11:48:00.13#ibcon#first serial, iclass 6, count 2 2006.257.11:48:00.13#ibcon#enter sib2, iclass 6, count 2 2006.257.11:48:00.13#ibcon#flushed, iclass 6, count 2 2006.257.11:48:00.13#ibcon#about to write, iclass 6, count 2 2006.257.11:48:00.13#ibcon#wrote, iclass 6, count 2 2006.257.11:48:00.13#ibcon#about to read 3, iclass 6, count 2 2006.257.11:48:00.15#ibcon#read 3, iclass 6, count 2 2006.257.11:48:00.15#ibcon#about to read 4, iclass 6, count 2 2006.257.11:48:00.15#ibcon#read 4, iclass 6, count 2 2006.257.11:48:00.15#ibcon#about to read 5, iclass 6, count 2 2006.257.11:48:00.15#ibcon#read 5, iclass 6, count 2 2006.257.11:48:00.15#ibcon#about to read 6, iclass 6, count 2 2006.257.11:48:00.15#ibcon#read 6, iclass 6, count 2 2006.257.11:48:00.15#ibcon#end of sib2, iclass 6, count 2 2006.257.11:48:00.15#ibcon#*mode == 0, iclass 6, count 2 2006.257.11:48:00.15#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.11:48:00.15#ibcon#[27=AT02-05\r\n] 2006.257.11:48:00.15#ibcon#*before write, iclass 6, count 2 2006.257.11:48:00.15#ibcon#enter sib2, iclass 6, count 2 2006.257.11:48:00.15#ibcon#flushed, iclass 6, count 2 2006.257.11:48:00.15#ibcon#about to write, iclass 6, count 2 2006.257.11:48:00.15#ibcon#wrote, iclass 6, count 2 2006.257.11:48:00.15#ibcon#about to read 3, iclass 6, count 2 2006.257.11:48:00.18#ibcon#read 3, iclass 6, count 2 2006.257.11:48:00.18#ibcon#about to read 4, iclass 6, count 2 2006.257.11:48:00.18#ibcon#read 4, iclass 6, count 2 2006.257.11:48:00.18#ibcon#about to read 5, iclass 6, count 2 2006.257.11:48:00.18#ibcon#read 5, iclass 6, count 2 2006.257.11:48:00.18#ibcon#about to read 6, iclass 6, count 2 2006.257.11:48:00.18#ibcon#read 6, iclass 6, count 2 2006.257.11:48:00.18#ibcon#end of sib2, iclass 6, count 2 2006.257.11:48:00.18#ibcon#*after write, iclass 6, count 2 2006.257.11:48:00.18#ibcon#*before return 0, iclass 6, count 2 2006.257.11:48:00.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:48:00.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.11:48:00.18#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.11:48:00.18#ibcon#ireg 7 cls_cnt 0 2006.257.11:48:00.18#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:48:00.30#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:48:00.30#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:48:00.30#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:48:00.30#ibcon#first serial, iclass 6, count 0 2006.257.11:48:00.30#ibcon#enter sib2, iclass 6, count 0 2006.257.11:48:00.30#ibcon#flushed, iclass 6, count 0 2006.257.11:48:00.30#ibcon#about to write, iclass 6, count 0 2006.257.11:48:00.30#ibcon#wrote, iclass 6, count 0 2006.257.11:48:00.30#ibcon#about to read 3, iclass 6, count 0 2006.257.11:48:00.32#ibcon#read 3, iclass 6, count 0 2006.257.11:48:00.32#ibcon#about to read 4, iclass 6, count 0 2006.257.11:48:00.32#ibcon#read 4, iclass 6, count 0 2006.257.11:48:00.32#ibcon#about to read 5, iclass 6, count 0 2006.257.11:48:00.32#ibcon#read 5, iclass 6, count 0 2006.257.11:48:00.32#ibcon#about to read 6, iclass 6, count 0 2006.257.11:48:00.32#ibcon#read 6, iclass 6, count 0 2006.257.11:48:00.32#ibcon#end of sib2, iclass 6, count 0 2006.257.11:48:00.32#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:48:00.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:48:00.32#ibcon#[27=USB\r\n] 2006.257.11:48:00.32#ibcon#*before write, iclass 6, count 0 2006.257.11:48:00.32#ibcon#enter sib2, iclass 6, count 0 2006.257.11:48:00.32#ibcon#flushed, iclass 6, count 0 2006.257.11:48:00.32#ibcon#about to write, iclass 6, count 0 2006.257.11:48:00.32#ibcon#wrote, iclass 6, count 0 2006.257.11:48:00.32#ibcon#about to read 3, iclass 6, count 0 2006.257.11:48:00.35#ibcon#read 3, iclass 6, count 0 2006.257.11:48:00.35#ibcon#about to read 4, iclass 6, count 0 2006.257.11:48:00.35#ibcon#read 4, iclass 6, count 0 2006.257.11:48:00.35#ibcon#about to read 5, iclass 6, count 0 2006.257.11:48:00.35#ibcon#read 5, iclass 6, count 0 2006.257.11:48:00.35#ibcon#about to read 6, iclass 6, count 0 2006.257.11:48:00.35#ibcon#read 6, iclass 6, count 0 2006.257.11:48:00.35#ibcon#end of sib2, iclass 6, count 0 2006.257.11:48:00.35#ibcon#*after write, iclass 6, count 0 2006.257.11:48:00.35#ibcon#*before return 0, iclass 6, count 0 2006.257.11:48:00.35#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:48:00.35#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.11:48:01.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:48:01.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:48:01.49$vck44/vblo=3,649.99 2006.257.11:48:01.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.11:48:01.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.11:48:01.50#ibcon#ireg 17 cls_cnt 0 2006.257.11:48:01.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:48:01.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:48:01.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:48:01.50#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:48:01.50#ibcon#first serial, iclass 10, count 0 2006.257.11:48:01.50#ibcon#enter sib2, iclass 10, count 0 2006.257.11:48:01.50#ibcon#flushed, iclass 10, count 0 2006.257.11:48:01.50#ibcon#about to write, iclass 10, count 0 2006.257.11:48:01.50#ibcon#wrote, iclass 10, count 0 2006.257.11:48:01.50#ibcon#about to read 3, iclass 10, count 0 2006.257.11:48:01.52#ibcon#read 3, iclass 10, count 0 2006.257.11:48:01.52#ibcon#about to read 4, iclass 10, count 0 2006.257.11:48:01.52#ibcon#read 4, iclass 10, count 0 2006.257.11:48:01.52#ibcon#about to read 5, iclass 10, count 0 2006.257.11:48:01.52#ibcon#read 5, iclass 10, count 0 2006.257.11:48:01.52#ibcon#about to read 6, iclass 10, count 0 2006.257.11:48:01.52#ibcon#read 6, iclass 10, count 0 2006.257.11:48:01.52#ibcon#end of sib2, iclass 10, count 0 2006.257.11:48:01.52#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:48:01.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:48:01.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:48:01.52#ibcon#*before write, iclass 10, count 0 2006.257.11:48:01.52#ibcon#enter sib2, iclass 10, count 0 2006.257.11:48:01.52#ibcon#flushed, iclass 10, count 0 2006.257.11:48:01.52#ibcon#about to write, iclass 10, count 0 2006.257.11:48:01.52#ibcon#wrote, iclass 10, count 0 2006.257.11:48:01.52#ibcon#about to read 3, iclass 10, count 0 2006.257.11:48:01.56#ibcon#read 3, iclass 10, count 0 2006.257.11:48:01.56#ibcon#about to read 4, iclass 10, count 0 2006.257.11:48:01.56#ibcon#read 4, iclass 10, count 0 2006.257.11:48:01.56#ibcon#about to read 5, iclass 10, count 0 2006.257.11:48:01.56#ibcon#read 5, iclass 10, count 0 2006.257.11:48:01.56#ibcon#about to read 6, iclass 10, count 0 2006.257.11:48:01.56#ibcon#read 6, iclass 10, count 0 2006.257.11:48:01.56#ibcon#end of sib2, iclass 10, count 0 2006.257.11:48:01.56#ibcon#*after write, iclass 10, count 0 2006.257.11:48:01.56#ibcon#*before return 0, iclass 10, count 0 2006.257.11:48:01.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:48:01.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.11:48:01.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:48:01.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:48:01.56$vck44/vb=3,4 2006.257.11:48:01.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.11:48:01.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.11:48:01.56#ibcon#ireg 11 cls_cnt 2 2006.257.11:48:01.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:48:01.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:48:01.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:48:01.56#ibcon#enter wrdev, iclass 12, count 2 2006.257.11:48:01.56#ibcon#first serial, iclass 12, count 2 2006.257.11:48:01.56#ibcon#enter sib2, iclass 12, count 2 2006.257.11:48:01.56#ibcon#flushed, iclass 12, count 2 2006.257.11:48:01.56#ibcon#about to write, iclass 12, count 2 2006.257.11:48:01.56#ibcon#wrote, iclass 12, count 2 2006.257.11:48:01.56#ibcon#about to read 3, iclass 12, count 2 2006.257.11:48:01.58#ibcon#read 3, iclass 12, count 2 2006.257.11:48:01.58#ibcon#about to read 4, iclass 12, count 2 2006.257.11:48:01.58#ibcon#read 4, iclass 12, count 2 2006.257.11:48:01.58#ibcon#about to read 5, iclass 12, count 2 2006.257.11:48:01.58#ibcon#read 5, iclass 12, count 2 2006.257.11:48:01.58#ibcon#about to read 6, iclass 12, count 2 2006.257.11:48:01.58#ibcon#read 6, iclass 12, count 2 2006.257.11:48:01.58#ibcon#end of sib2, iclass 12, count 2 2006.257.11:48:01.58#ibcon#*mode == 0, iclass 12, count 2 2006.257.11:48:01.58#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.11:48:01.58#ibcon#[27=AT03-04\r\n] 2006.257.11:48:01.58#ibcon#*before write, iclass 12, count 2 2006.257.11:48:01.58#ibcon#enter sib2, iclass 12, count 2 2006.257.11:48:01.58#ibcon#flushed, iclass 12, count 2 2006.257.11:48:01.58#ibcon#about to write, iclass 12, count 2 2006.257.11:48:01.58#ibcon#wrote, iclass 12, count 2 2006.257.11:48:01.58#ibcon#about to read 3, iclass 12, count 2 2006.257.11:48:01.61#ibcon#read 3, iclass 12, count 2 2006.257.11:48:01.61#ibcon#about to read 4, iclass 12, count 2 2006.257.11:48:01.61#ibcon#read 4, iclass 12, count 2 2006.257.11:48:01.61#ibcon#about to read 5, iclass 12, count 2 2006.257.11:48:01.61#ibcon#read 5, iclass 12, count 2 2006.257.11:48:01.61#ibcon#about to read 6, iclass 12, count 2 2006.257.11:48:01.61#ibcon#read 6, iclass 12, count 2 2006.257.11:48:01.61#ibcon#end of sib2, iclass 12, count 2 2006.257.11:48:01.61#ibcon#*after write, iclass 12, count 2 2006.257.11:48:01.61#ibcon#*before return 0, iclass 12, count 2 2006.257.11:48:01.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:48:01.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.11:48:01.61#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.11:48:01.61#ibcon#ireg 7 cls_cnt 0 2006.257.11:48:01.61#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:48:01.73#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:48:01.73#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:48:01.73#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:48:01.73#ibcon#first serial, iclass 12, count 0 2006.257.11:48:01.73#ibcon#enter sib2, iclass 12, count 0 2006.257.11:48:01.73#ibcon#flushed, iclass 12, count 0 2006.257.11:48:01.73#ibcon#about to write, iclass 12, count 0 2006.257.11:48:01.73#ibcon#wrote, iclass 12, count 0 2006.257.11:48:01.73#ibcon#about to read 3, iclass 12, count 0 2006.257.11:48:01.75#ibcon#read 3, iclass 12, count 0 2006.257.11:48:01.75#ibcon#about to read 4, iclass 12, count 0 2006.257.11:48:01.75#ibcon#read 4, iclass 12, count 0 2006.257.11:48:01.75#ibcon#about to read 5, iclass 12, count 0 2006.257.11:48:01.75#ibcon#read 5, iclass 12, count 0 2006.257.11:48:01.75#ibcon#about to read 6, iclass 12, count 0 2006.257.11:48:01.75#ibcon#read 6, iclass 12, count 0 2006.257.11:48:01.75#ibcon#end of sib2, iclass 12, count 0 2006.257.11:48:01.75#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:48:01.75#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:48:01.75#ibcon#[27=USB\r\n] 2006.257.11:48:01.75#ibcon#*before write, iclass 12, count 0 2006.257.11:48:01.75#ibcon#enter sib2, iclass 12, count 0 2006.257.11:48:01.75#ibcon#flushed, iclass 12, count 0 2006.257.11:48:01.75#ibcon#about to write, iclass 12, count 0 2006.257.11:48:01.75#ibcon#wrote, iclass 12, count 0 2006.257.11:48:01.75#ibcon#about to read 3, iclass 12, count 0 2006.257.11:48:01.78#ibcon#read 3, iclass 12, count 0 2006.257.11:48:01.78#ibcon#about to read 4, iclass 12, count 0 2006.257.11:48:01.78#ibcon#read 4, iclass 12, count 0 2006.257.11:48:01.78#ibcon#about to read 5, iclass 12, count 0 2006.257.11:48:01.78#ibcon#read 5, iclass 12, count 0 2006.257.11:48:01.78#ibcon#about to read 6, iclass 12, count 0 2006.257.11:48:01.78#ibcon#read 6, iclass 12, count 0 2006.257.11:48:01.78#ibcon#end of sib2, iclass 12, count 0 2006.257.11:48:01.78#ibcon#*after write, iclass 12, count 0 2006.257.11:48:01.78#ibcon#*before return 0, iclass 12, count 0 2006.257.11:48:01.78#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:48:01.78#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.11:48:01.78#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:48:01.78#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:48:01.78$vck44/vblo=4,679.99 2006.257.11:48:01.78#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.11:48:01.78#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.11:48:01.78#ibcon#ireg 17 cls_cnt 0 2006.257.11:48:01.78#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:48:01.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:48:01.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:48:01.78#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:48:01.78#ibcon#first serial, iclass 14, count 0 2006.257.11:48:01.78#ibcon#enter sib2, iclass 14, count 0 2006.257.11:48:01.78#ibcon#flushed, iclass 14, count 0 2006.257.11:48:01.78#ibcon#about to write, iclass 14, count 0 2006.257.11:48:01.78#ibcon#wrote, iclass 14, count 0 2006.257.11:48:01.78#ibcon#about to read 3, iclass 14, count 0 2006.257.11:48:01.80#ibcon#read 3, iclass 14, count 0 2006.257.11:48:01.80#ibcon#about to read 4, iclass 14, count 0 2006.257.11:48:01.80#ibcon#read 4, iclass 14, count 0 2006.257.11:48:01.80#ibcon#about to read 5, iclass 14, count 0 2006.257.11:48:01.80#ibcon#read 5, iclass 14, count 0 2006.257.11:48:01.80#ibcon#about to read 6, iclass 14, count 0 2006.257.11:48:01.80#ibcon#read 6, iclass 14, count 0 2006.257.11:48:01.80#ibcon#end of sib2, iclass 14, count 0 2006.257.11:48:01.80#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:48:01.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:48:01.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:48:01.80#ibcon#*before write, iclass 14, count 0 2006.257.11:48:01.80#ibcon#enter sib2, iclass 14, count 0 2006.257.11:48:01.80#ibcon#flushed, iclass 14, count 0 2006.257.11:48:01.80#ibcon#about to write, iclass 14, count 0 2006.257.11:48:01.80#ibcon#wrote, iclass 14, count 0 2006.257.11:48:01.80#ibcon#about to read 3, iclass 14, count 0 2006.257.11:48:01.84#ibcon#read 3, iclass 14, count 0 2006.257.11:48:01.84#ibcon#about to read 4, iclass 14, count 0 2006.257.11:48:01.84#ibcon#read 4, iclass 14, count 0 2006.257.11:48:01.84#ibcon#about to read 5, iclass 14, count 0 2006.257.11:48:01.84#ibcon#read 5, iclass 14, count 0 2006.257.11:48:01.84#ibcon#about to read 6, iclass 14, count 0 2006.257.11:48:01.84#ibcon#read 6, iclass 14, count 0 2006.257.11:48:01.84#ibcon#end of sib2, iclass 14, count 0 2006.257.11:48:01.84#ibcon#*after write, iclass 14, count 0 2006.257.11:48:01.84#ibcon#*before return 0, iclass 14, count 0 2006.257.11:48:01.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:48:01.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.11:48:01.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:48:01.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:48:01.84$vck44/vb=4,5 2006.257.11:48:01.84#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.11:48:01.84#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.11:48:01.84#ibcon#ireg 11 cls_cnt 2 2006.257.11:48:01.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:48:01.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:48:01.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:48:01.90#ibcon#enter wrdev, iclass 16, count 2 2006.257.11:48:01.90#ibcon#first serial, iclass 16, count 2 2006.257.11:48:01.90#ibcon#enter sib2, iclass 16, count 2 2006.257.11:48:01.90#ibcon#flushed, iclass 16, count 2 2006.257.11:48:01.90#ibcon#about to write, iclass 16, count 2 2006.257.11:48:01.90#ibcon#wrote, iclass 16, count 2 2006.257.11:48:01.90#ibcon#about to read 3, iclass 16, count 2 2006.257.11:48:01.92#ibcon#read 3, iclass 16, count 2 2006.257.11:48:01.92#ibcon#about to read 4, iclass 16, count 2 2006.257.11:48:01.92#ibcon#read 4, iclass 16, count 2 2006.257.11:48:01.92#ibcon#about to read 5, iclass 16, count 2 2006.257.11:48:01.92#ibcon#read 5, iclass 16, count 2 2006.257.11:48:01.92#ibcon#about to read 6, iclass 16, count 2 2006.257.11:48:01.92#ibcon#read 6, iclass 16, count 2 2006.257.11:48:01.92#ibcon#end of sib2, iclass 16, count 2 2006.257.11:48:01.92#ibcon#*mode == 0, iclass 16, count 2 2006.257.11:48:01.92#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.11:48:01.92#ibcon#[27=AT04-05\r\n] 2006.257.11:48:01.92#ibcon#*before write, iclass 16, count 2 2006.257.11:48:01.92#ibcon#enter sib2, iclass 16, count 2 2006.257.11:48:01.92#ibcon#flushed, iclass 16, count 2 2006.257.11:48:01.92#ibcon#about to write, iclass 16, count 2 2006.257.11:48:01.92#ibcon#wrote, iclass 16, count 2 2006.257.11:48:01.92#ibcon#about to read 3, iclass 16, count 2 2006.257.11:48:01.95#ibcon#read 3, iclass 16, count 2 2006.257.11:48:01.95#ibcon#about to read 4, iclass 16, count 2 2006.257.11:48:01.95#ibcon#read 4, iclass 16, count 2 2006.257.11:48:01.95#ibcon#about to read 5, iclass 16, count 2 2006.257.11:48:01.95#ibcon#read 5, iclass 16, count 2 2006.257.11:48:01.95#ibcon#about to read 6, iclass 16, count 2 2006.257.11:48:01.95#ibcon#read 6, iclass 16, count 2 2006.257.11:48:01.95#ibcon#end of sib2, iclass 16, count 2 2006.257.11:48:01.95#ibcon#*after write, iclass 16, count 2 2006.257.11:48:01.95#ibcon#*before return 0, iclass 16, count 2 2006.257.11:48:01.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:48:01.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.11:48:01.95#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.11:48:01.95#ibcon#ireg 7 cls_cnt 0 2006.257.11:48:01.95#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:48:02.07#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:48:02.07#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:48:02.07#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:48:02.07#ibcon#first serial, iclass 16, count 0 2006.257.11:48:02.07#ibcon#enter sib2, iclass 16, count 0 2006.257.11:48:02.07#ibcon#flushed, iclass 16, count 0 2006.257.11:48:02.07#ibcon#about to write, iclass 16, count 0 2006.257.11:48:02.07#ibcon#wrote, iclass 16, count 0 2006.257.11:48:02.07#ibcon#about to read 3, iclass 16, count 0 2006.257.11:48:02.09#ibcon#read 3, iclass 16, count 0 2006.257.11:48:02.09#ibcon#about to read 4, iclass 16, count 0 2006.257.11:48:02.09#ibcon#read 4, iclass 16, count 0 2006.257.11:48:02.09#ibcon#about to read 5, iclass 16, count 0 2006.257.11:48:02.09#ibcon#read 5, iclass 16, count 0 2006.257.11:48:02.09#ibcon#about to read 6, iclass 16, count 0 2006.257.11:48:02.09#ibcon#read 6, iclass 16, count 0 2006.257.11:48:02.09#ibcon#end of sib2, iclass 16, count 0 2006.257.11:48:02.09#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:48:02.09#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:48:02.09#ibcon#[27=USB\r\n] 2006.257.11:48:02.09#ibcon#*before write, iclass 16, count 0 2006.257.11:48:02.09#ibcon#enter sib2, iclass 16, count 0 2006.257.11:48:02.09#ibcon#flushed, iclass 16, count 0 2006.257.11:48:02.09#ibcon#about to write, iclass 16, count 0 2006.257.11:48:02.09#ibcon#wrote, iclass 16, count 0 2006.257.11:48:02.09#ibcon#about to read 3, iclass 16, count 0 2006.257.11:48:02.12#ibcon#read 3, iclass 16, count 0 2006.257.11:48:02.12#ibcon#about to read 4, iclass 16, count 0 2006.257.11:48:02.12#ibcon#read 4, iclass 16, count 0 2006.257.11:48:02.12#ibcon#about to read 5, iclass 16, count 0 2006.257.11:48:02.12#ibcon#read 5, iclass 16, count 0 2006.257.11:48:02.12#ibcon#about to read 6, iclass 16, count 0 2006.257.11:48:02.12#ibcon#read 6, iclass 16, count 0 2006.257.11:48:02.12#ibcon#end of sib2, iclass 16, count 0 2006.257.11:48:02.12#ibcon#*after write, iclass 16, count 0 2006.257.11:48:02.12#ibcon#*before return 0, iclass 16, count 0 2006.257.11:48:02.12#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:48:02.12#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.11:48:02.12#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:48:02.12#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:48:02.12$vck44/vblo=5,709.99 2006.257.11:48:02.12#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.11:48:02.12#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.11:48:02.12#ibcon#ireg 17 cls_cnt 0 2006.257.11:48:02.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:48:02.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:48:02.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:48:02.12#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:48:02.12#ibcon#first serial, iclass 18, count 0 2006.257.11:48:02.12#ibcon#enter sib2, iclass 18, count 0 2006.257.11:48:02.12#ibcon#flushed, iclass 18, count 0 2006.257.11:48:02.12#ibcon#about to write, iclass 18, count 0 2006.257.11:48:02.12#ibcon#wrote, iclass 18, count 0 2006.257.11:48:02.12#ibcon#about to read 3, iclass 18, count 0 2006.257.11:48:02.14#ibcon#read 3, iclass 18, count 0 2006.257.11:48:02.14#ibcon#about to read 4, iclass 18, count 0 2006.257.11:48:02.14#ibcon#read 4, iclass 18, count 0 2006.257.11:48:02.14#ibcon#about to read 5, iclass 18, count 0 2006.257.11:48:02.14#ibcon#read 5, iclass 18, count 0 2006.257.11:48:02.14#ibcon#about to read 6, iclass 18, count 0 2006.257.11:48:02.14#ibcon#read 6, iclass 18, count 0 2006.257.11:48:02.14#ibcon#end of sib2, iclass 18, count 0 2006.257.11:48:02.14#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:48:02.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:48:02.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:48:02.14#ibcon#*before write, iclass 18, count 0 2006.257.11:48:02.14#ibcon#enter sib2, iclass 18, count 0 2006.257.11:48:02.14#ibcon#flushed, iclass 18, count 0 2006.257.11:48:02.14#ibcon#about to write, iclass 18, count 0 2006.257.11:48:02.14#ibcon#wrote, iclass 18, count 0 2006.257.11:48:02.14#ibcon#about to read 3, iclass 18, count 0 2006.257.11:48:02.18#ibcon#read 3, iclass 18, count 0 2006.257.11:48:02.18#ibcon#about to read 4, iclass 18, count 0 2006.257.11:48:02.18#ibcon#read 4, iclass 18, count 0 2006.257.11:48:02.18#ibcon#about to read 5, iclass 18, count 0 2006.257.11:48:02.18#ibcon#read 5, iclass 18, count 0 2006.257.11:48:02.18#ibcon#about to read 6, iclass 18, count 0 2006.257.11:48:02.18#ibcon#read 6, iclass 18, count 0 2006.257.11:48:02.18#ibcon#end of sib2, iclass 18, count 0 2006.257.11:48:02.18#ibcon#*after write, iclass 18, count 0 2006.257.11:48:02.18#ibcon#*before return 0, iclass 18, count 0 2006.257.11:48:02.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:48:02.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.11:48:02.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:48:02.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:48:02.18$vck44/vb=5,4 2006.257.11:48:02.18#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.11:48:02.18#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.11:48:02.18#ibcon#ireg 11 cls_cnt 2 2006.257.11:48:02.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:48:02.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:48:02.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:48:02.24#ibcon#enter wrdev, iclass 20, count 2 2006.257.11:48:02.24#ibcon#first serial, iclass 20, count 2 2006.257.11:48:02.24#ibcon#enter sib2, iclass 20, count 2 2006.257.11:48:02.24#ibcon#flushed, iclass 20, count 2 2006.257.11:48:02.24#ibcon#about to write, iclass 20, count 2 2006.257.11:48:02.24#ibcon#wrote, iclass 20, count 2 2006.257.11:48:02.24#ibcon#about to read 3, iclass 20, count 2 2006.257.11:48:02.26#ibcon#read 3, iclass 20, count 2 2006.257.11:48:02.26#ibcon#about to read 4, iclass 20, count 2 2006.257.11:48:02.26#ibcon#read 4, iclass 20, count 2 2006.257.11:48:02.26#ibcon#about to read 5, iclass 20, count 2 2006.257.11:48:02.26#ibcon#read 5, iclass 20, count 2 2006.257.11:48:02.26#ibcon#about to read 6, iclass 20, count 2 2006.257.11:48:02.26#ibcon#read 6, iclass 20, count 2 2006.257.11:48:02.26#ibcon#end of sib2, iclass 20, count 2 2006.257.11:48:02.26#ibcon#*mode == 0, iclass 20, count 2 2006.257.11:48:02.26#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.11:48:02.26#ibcon#[27=AT05-04\r\n] 2006.257.11:48:02.26#ibcon#*before write, iclass 20, count 2 2006.257.11:48:02.26#ibcon#enter sib2, iclass 20, count 2 2006.257.11:48:02.26#ibcon#flushed, iclass 20, count 2 2006.257.11:48:02.26#ibcon#about to write, iclass 20, count 2 2006.257.11:48:02.26#ibcon#wrote, iclass 20, count 2 2006.257.11:48:02.26#ibcon#about to read 3, iclass 20, count 2 2006.257.11:48:02.29#ibcon#read 3, iclass 20, count 2 2006.257.11:48:02.29#ibcon#about to read 4, iclass 20, count 2 2006.257.11:48:02.29#ibcon#read 4, iclass 20, count 2 2006.257.11:48:02.29#ibcon#about to read 5, iclass 20, count 2 2006.257.11:48:02.29#ibcon#read 5, iclass 20, count 2 2006.257.11:48:02.29#ibcon#about to read 6, iclass 20, count 2 2006.257.11:48:02.29#ibcon#read 6, iclass 20, count 2 2006.257.11:48:02.29#ibcon#end of sib2, iclass 20, count 2 2006.257.11:48:02.29#ibcon#*after write, iclass 20, count 2 2006.257.11:48:02.29#ibcon#*before return 0, iclass 20, count 2 2006.257.11:48:02.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:48:02.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.11:48:02.29#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.11:48:02.29#ibcon#ireg 7 cls_cnt 0 2006.257.11:48:02.29#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:48:02.41#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:48:02.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:48:02.41#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:48:02.41#ibcon#first serial, iclass 20, count 0 2006.257.11:48:02.41#ibcon#enter sib2, iclass 20, count 0 2006.257.11:48:02.41#ibcon#flushed, iclass 20, count 0 2006.257.11:48:02.41#ibcon#about to write, iclass 20, count 0 2006.257.11:48:02.41#ibcon#wrote, iclass 20, count 0 2006.257.11:48:02.41#ibcon#about to read 3, iclass 20, count 0 2006.257.11:48:02.43#ibcon#read 3, iclass 20, count 0 2006.257.11:48:02.43#ibcon#about to read 4, iclass 20, count 0 2006.257.11:48:02.43#ibcon#read 4, iclass 20, count 0 2006.257.11:48:02.43#ibcon#about to read 5, iclass 20, count 0 2006.257.11:48:02.43#ibcon#read 5, iclass 20, count 0 2006.257.11:48:02.43#ibcon#about to read 6, iclass 20, count 0 2006.257.11:48:02.43#ibcon#read 6, iclass 20, count 0 2006.257.11:48:02.43#ibcon#end of sib2, iclass 20, count 0 2006.257.11:48:02.43#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:48:02.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:48:02.43#ibcon#[27=USB\r\n] 2006.257.11:48:02.43#ibcon#*before write, iclass 20, count 0 2006.257.11:48:02.43#ibcon#enter sib2, iclass 20, count 0 2006.257.11:48:02.43#ibcon#flushed, iclass 20, count 0 2006.257.11:48:02.43#ibcon#about to write, iclass 20, count 0 2006.257.11:48:02.43#ibcon#wrote, iclass 20, count 0 2006.257.11:48:02.43#ibcon#about to read 3, iclass 20, count 0 2006.257.11:48:02.46#ibcon#read 3, iclass 20, count 0 2006.257.11:48:02.46#ibcon#about to read 4, iclass 20, count 0 2006.257.11:48:02.46#ibcon#read 4, iclass 20, count 0 2006.257.11:48:02.46#ibcon#about to read 5, iclass 20, count 0 2006.257.11:48:02.46#ibcon#read 5, iclass 20, count 0 2006.257.11:48:02.46#ibcon#about to read 6, iclass 20, count 0 2006.257.11:48:02.46#ibcon#read 6, iclass 20, count 0 2006.257.11:48:02.46#ibcon#end of sib2, iclass 20, count 0 2006.257.11:48:02.46#ibcon#*after write, iclass 20, count 0 2006.257.11:48:02.46#ibcon#*before return 0, iclass 20, count 0 2006.257.11:48:02.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:48:02.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.11:48:02.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:48:02.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:48:02.46$vck44/vblo=6,719.99 2006.257.11:48:02.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.11:48:02.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.11:48:02.46#ibcon#ireg 17 cls_cnt 0 2006.257.11:48:02.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:48:02.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:48:02.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:48:02.46#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:48:02.46#ibcon#first serial, iclass 22, count 0 2006.257.11:48:02.46#ibcon#enter sib2, iclass 22, count 0 2006.257.11:48:02.46#ibcon#flushed, iclass 22, count 0 2006.257.11:48:02.46#ibcon#about to write, iclass 22, count 0 2006.257.11:48:02.46#ibcon#wrote, iclass 22, count 0 2006.257.11:48:02.46#ibcon#about to read 3, iclass 22, count 0 2006.257.11:48:02.48#ibcon#read 3, iclass 22, count 0 2006.257.11:48:02.48#ibcon#about to read 4, iclass 22, count 0 2006.257.11:48:02.48#ibcon#read 4, iclass 22, count 0 2006.257.11:48:02.48#ibcon#about to read 5, iclass 22, count 0 2006.257.11:48:02.48#ibcon#read 5, iclass 22, count 0 2006.257.11:48:02.48#ibcon#about to read 6, iclass 22, count 0 2006.257.11:48:02.48#ibcon#read 6, iclass 22, count 0 2006.257.11:48:02.48#ibcon#end of sib2, iclass 22, count 0 2006.257.11:48:02.48#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:48:02.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:48:02.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:48:02.48#ibcon#*before write, iclass 22, count 0 2006.257.11:48:02.48#ibcon#enter sib2, iclass 22, count 0 2006.257.11:48:02.48#ibcon#flushed, iclass 22, count 0 2006.257.11:48:02.48#ibcon#about to write, iclass 22, count 0 2006.257.11:48:02.48#ibcon#wrote, iclass 22, count 0 2006.257.11:48:02.48#ibcon#about to read 3, iclass 22, count 0 2006.257.11:48:02.52#ibcon#read 3, iclass 22, count 0 2006.257.11:48:02.52#ibcon#about to read 4, iclass 22, count 0 2006.257.11:48:02.52#ibcon#read 4, iclass 22, count 0 2006.257.11:48:02.52#ibcon#about to read 5, iclass 22, count 0 2006.257.11:48:02.52#ibcon#read 5, iclass 22, count 0 2006.257.11:48:02.52#ibcon#about to read 6, iclass 22, count 0 2006.257.11:48:02.52#ibcon#read 6, iclass 22, count 0 2006.257.11:48:02.52#ibcon#end of sib2, iclass 22, count 0 2006.257.11:48:02.52#ibcon#*after write, iclass 22, count 0 2006.257.11:48:02.52#ibcon#*before return 0, iclass 22, count 0 2006.257.11:48:02.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:48:02.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.11:48:02.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:48:02.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:48:02.52$vck44/vb=6,4 2006.257.11:48:02.52#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.11:48:02.52#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.11:48:02.52#ibcon#ireg 11 cls_cnt 2 2006.257.11:48:02.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:48:02.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:48:02.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:48:02.58#ibcon#enter wrdev, iclass 24, count 2 2006.257.11:48:02.58#ibcon#first serial, iclass 24, count 2 2006.257.11:48:02.58#ibcon#enter sib2, iclass 24, count 2 2006.257.11:48:02.58#ibcon#flushed, iclass 24, count 2 2006.257.11:48:02.58#ibcon#about to write, iclass 24, count 2 2006.257.11:48:02.58#ibcon#wrote, iclass 24, count 2 2006.257.11:48:02.58#ibcon#about to read 3, iclass 24, count 2 2006.257.11:48:02.60#ibcon#read 3, iclass 24, count 2 2006.257.11:48:02.60#ibcon#about to read 4, iclass 24, count 2 2006.257.11:48:02.60#ibcon#read 4, iclass 24, count 2 2006.257.11:48:02.60#ibcon#about to read 5, iclass 24, count 2 2006.257.11:48:02.60#ibcon#read 5, iclass 24, count 2 2006.257.11:48:02.60#ibcon#about to read 6, iclass 24, count 2 2006.257.11:48:02.60#ibcon#read 6, iclass 24, count 2 2006.257.11:48:02.60#ibcon#end of sib2, iclass 24, count 2 2006.257.11:48:02.60#ibcon#*mode == 0, iclass 24, count 2 2006.257.11:48:02.60#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.11:48:02.60#ibcon#[27=AT06-04\r\n] 2006.257.11:48:02.60#ibcon#*before write, iclass 24, count 2 2006.257.11:48:02.60#ibcon#enter sib2, iclass 24, count 2 2006.257.11:48:02.60#ibcon#flushed, iclass 24, count 2 2006.257.11:48:02.60#ibcon#about to write, iclass 24, count 2 2006.257.11:48:02.60#ibcon#wrote, iclass 24, count 2 2006.257.11:48:02.60#ibcon#about to read 3, iclass 24, count 2 2006.257.11:48:02.63#ibcon#read 3, iclass 24, count 2 2006.257.11:48:02.63#ibcon#about to read 4, iclass 24, count 2 2006.257.11:48:02.63#ibcon#read 4, iclass 24, count 2 2006.257.11:48:02.63#ibcon#about to read 5, iclass 24, count 2 2006.257.11:48:02.63#ibcon#read 5, iclass 24, count 2 2006.257.11:48:02.63#ibcon#about to read 6, iclass 24, count 2 2006.257.11:48:02.63#ibcon#read 6, iclass 24, count 2 2006.257.11:48:02.63#ibcon#end of sib2, iclass 24, count 2 2006.257.11:48:02.63#ibcon#*after write, iclass 24, count 2 2006.257.11:48:02.63#ibcon#*before return 0, iclass 24, count 2 2006.257.11:48:02.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:48:02.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.11:48:02.63#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.11:48:02.63#ibcon#ireg 7 cls_cnt 0 2006.257.11:48:02.63#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:48:02.75#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:48:02.75#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:48:02.75#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:48:02.75#ibcon#first serial, iclass 24, count 0 2006.257.11:48:02.75#ibcon#enter sib2, iclass 24, count 0 2006.257.11:48:02.75#ibcon#flushed, iclass 24, count 0 2006.257.11:48:02.75#ibcon#about to write, iclass 24, count 0 2006.257.11:48:02.75#ibcon#wrote, iclass 24, count 0 2006.257.11:48:02.75#ibcon#about to read 3, iclass 24, count 0 2006.257.11:48:02.77#ibcon#read 3, iclass 24, count 0 2006.257.11:48:02.77#ibcon#about to read 4, iclass 24, count 0 2006.257.11:48:02.77#ibcon#read 4, iclass 24, count 0 2006.257.11:48:02.77#ibcon#about to read 5, iclass 24, count 0 2006.257.11:48:02.77#ibcon#read 5, iclass 24, count 0 2006.257.11:48:02.77#ibcon#about to read 6, iclass 24, count 0 2006.257.11:48:02.77#ibcon#read 6, iclass 24, count 0 2006.257.11:48:02.77#ibcon#end of sib2, iclass 24, count 0 2006.257.11:48:02.77#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:48:02.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:48:02.77#ibcon#[27=USB\r\n] 2006.257.11:48:02.77#ibcon#*before write, iclass 24, count 0 2006.257.11:48:02.77#ibcon#enter sib2, iclass 24, count 0 2006.257.11:48:02.77#ibcon#flushed, iclass 24, count 0 2006.257.11:48:02.77#ibcon#about to write, iclass 24, count 0 2006.257.11:48:02.77#ibcon#wrote, iclass 24, count 0 2006.257.11:48:02.77#ibcon#about to read 3, iclass 24, count 0 2006.257.11:48:03.84#ibcon#read 3, iclass 24, count 0 2006.257.11:48:03.84#ibcon#about to read 4, iclass 24, count 0 2006.257.11:48:03.84#ibcon#read 4, iclass 24, count 0 2006.257.11:48:03.85#ibcon#about to read 5, iclass 24, count 0 2006.257.11:48:03.85#ibcon#read 5, iclass 24, count 0 2006.257.11:48:03.85#ibcon#about to read 6, iclass 24, count 0 2006.257.11:48:03.85#ibcon#read 6, iclass 24, count 0 2006.257.11:48:03.85#ibcon#end of sib2, iclass 24, count 0 2006.257.11:48:03.85#ibcon#*after write, iclass 24, count 0 2006.257.11:48:03.85#ibcon#*before return 0, iclass 24, count 0 2006.257.11:48:03.85#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:48:03.85#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.11:48:03.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:48:03.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:48:03.85$vck44/vblo=7,734.99 2006.257.11:48:03.85#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.11:48:03.85#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.11:48:03.85#ibcon#ireg 17 cls_cnt 0 2006.257.11:48:03.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:48:03.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:48:03.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:48:03.85#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:48:03.85#ibcon#first serial, iclass 26, count 0 2006.257.11:48:03.85#ibcon#enter sib2, iclass 26, count 0 2006.257.11:48:03.85#ibcon#flushed, iclass 26, count 0 2006.257.11:48:03.85#ibcon#about to write, iclass 26, count 0 2006.257.11:48:03.85#ibcon#wrote, iclass 26, count 0 2006.257.11:48:03.85#ibcon#about to read 3, iclass 26, count 0 2006.257.11:48:03.87#ibcon#read 3, iclass 26, count 0 2006.257.11:48:03.87#ibcon#about to read 4, iclass 26, count 0 2006.257.11:48:03.87#ibcon#read 4, iclass 26, count 0 2006.257.11:48:03.87#ibcon#about to read 5, iclass 26, count 0 2006.257.11:48:03.87#ibcon#read 5, iclass 26, count 0 2006.257.11:48:03.87#ibcon#about to read 6, iclass 26, count 0 2006.257.11:48:03.87#ibcon#read 6, iclass 26, count 0 2006.257.11:48:03.87#ibcon#end of sib2, iclass 26, count 0 2006.257.11:48:03.87#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:48:03.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:48:03.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:48:03.87#ibcon#*before write, iclass 26, count 0 2006.257.11:48:03.87#ibcon#enter sib2, iclass 26, count 0 2006.257.11:48:03.87#ibcon#flushed, iclass 26, count 0 2006.257.11:48:03.87#ibcon#about to write, iclass 26, count 0 2006.257.11:48:03.87#ibcon#wrote, iclass 26, count 0 2006.257.11:48:03.87#ibcon#about to read 3, iclass 26, count 0 2006.257.11:48:03.91#ibcon#read 3, iclass 26, count 0 2006.257.11:48:03.91#ibcon#about to read 4, iclass 26, count 0 2006.257.11:48:03.91#ibcon#read 4, iclass 26, count 0 2006.257.11:48:03.91#ibcon#about to read 5, iclass 26, count 0 2006.257.11:48:03.91#ibcon#read 5, iclass 26, count 0 2006.257.11:48:03.91#ibcon#about to read 6, iclass 26, count 0 2006.257.11:48:03.91#ibcon#read 6, iclass 26, count 0 2006.257.11:48:03.91#ibcon#end of sib2, iclass 26, count 0 2006.257.11:48:03.91#ibcon#*after write, iclass 26, count 0 2006.257.11:48:03.91#ibcon#*before return 0, iclass 26, count 0 2006.257.11:48:03.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:48:03.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.11:48:03.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:48:03.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:48:03.91$vck44/vb=7,4 2006.257.11:48:03.91#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.11:48:03.91#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.11:48:03.91#ibcon#ireg 11 cls_cnt 2 2006.257.11:48:03.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:48:03.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:48:03.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:48:03.97#ibcon#enter wrdev, iclass 28, count 2 2006.257.11:48:03.97#ibcon#first serial, iclass 28, count 2 2006.257.11:48:03.97#ibcon#enter sib2, iclass 28, count 2 2006.257.11:48:03.97#ibcon#flushed, iclass 28, count 2 2006.257.11:48:03.97#ibcon#about to write, iclass 28, count 2 2006.257.11:48:03.97#ibcon#wrote, iclass 28, count 2 2006.257.11:48:03.97#ibcon#about to read 3, iclass 28, count 2 2006.257.11:48:03.99#ibcon#read 3, iclass 28, count 2 2006.257.11:48:03.99#ibcon#about to read 4, iclass 28, count 2 2006.257.11:48:03.99#ibcon#read 4, iclass 28, count 2 2006.257.11:48:03.99#ibcon#about to read 5, iclass 28, count 2 2006.257.11:48:03.99#ibcon#read 5, iclass 28, count 2 2006.257.11:48:03.99#ibcon#about to read 6, iclass 28, count 2 2006.257.11:48:03.99#ibcon#read 6, iclass 28, count 2 2006.257.11:48:03.99#ibcon#end of sib2, iclass 28, count 2 2006.257.11:48:03.99#ibcon#*mode == 0, iclass 28, count 2 2006.257.11:48:03.99#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.11:48:03.99#ibcon#[27=AT07-04\r\n] 2006.257.11:48:03.99#ibcon#*before write, iclass 28, count 2 2006.257.11:48:03.99#ibcon#enter sib2, iclass 28, count 2 2006.257.11:48:03.99#ibcon#flushed, iclass 28, count 2 2006.257.11:48:03.99#ibcon#about to write, iclass 28, count 2 2006.257.11:48:03.99#ibcon#wrote, iclass 28, count 2 2006.257.11:48:03.99#ibcon#about to read 3, iclass 28, count 2 2006.257.11:48:04.02#ibcon#read 3, iclass 28, count 2 2006.257.11:48:04.02#ibcon#about to read 4, iclass 28, count 2 2006.257.11:48:04.02#ibcon#read 4, iclass 28, count 2 2006.257.11:48:04.02#ibcon#about to read 5, iclass 28, count 2 2006.257.11:48:04.02#ibcon#read 5, iclass 28, count 2 2006.257.11:48:04.02#ibcon#about to read 6, iclass 28, count 2 2006.257.11:48:04.02#ibcon#read 6, iclass 28, count 2 2006.257.11:48:04.02#ibcon#end of sib2, iclass 28, count 2 2006.257.11:48:04.02#ibcon#*after write, iclass 28, count 2 2006.257.11:48:04.02#ibcon#*before return 0, iclass 28, count 2 2006.257.11:48:04.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:48:04.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.11:48:04.02#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.11:48:04.02#ibcon#ireg 7 cls_cnt 0 2006.257.11:48:04.02#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:48:04.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:48:04.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:48:04.14#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:48:04.14#ibcon#first serial, iclass 28, count 0 2006.257.11:48:04.14#ibcon#enter sib2, iclass 28, count 0 2006.257.11:48:04.14#ibcon#flushed, iclass 28, count 0 2006.257.11:48:04.14#ibcon#about to write, iclass 28, count 0 2006.257.11:48:04.14#ibcon#wrote, iclass 28, count 0 2006.257.11:48:04.14#ibcon#about to read 3, iclass 28, count 0 2006.257.11:48:04.16#ibcon#read 3, iclass 28, count 0 2006.257.11:48:04.16#ibcon#about to read 4, iclass 28, count 0 2006.257.11:48:04.16#ibcon#read 4, iclass 28, count 0 2006.257.11:48:04.16#ibcon#about to read 5, iclass 28, count 0 2006.257.11:48:04.16#ibcon#read 5, iclass 28, count 0 2006.257.11:48:04.16#ibcon#about to read 6, iclass 28, count 0 2006.257.11:48:04.16#ibcon#read 6, iclass 28, count 0 2006.257.11:48:04.16#ibcon#end of sib2, iclass 28, count 0 2006.257.11:48:04.16#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:48:04.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:48:04.16#ibcon#[27=USB\r\n] 2006.257.11:48:04.16#ibcon#*before write, iclass 28, count 0 2006.257.11:48:04.16#ibcon#enter sib2, iclass 28, count 0 2006.257.11:48:04.16#ibcon#flushed, iclass 28, count 0 2006.257.11:48:04.16#ibcon#about to write, iclass 28, count 0 2006.257.11:48:04.16#ibcon#wrote, iclass 28, count 0 2006.257.11:48:04.16#ibcon#about to read 3, iclass 28, count 0 2006.257.11:48:04.19#ibcon#read 3, iclass 28, count 0 2006.257.11:48:04.19#ibcon#about to read 4, iclass 28, count 0 2006.257.11:48:04.19#ibcon#read 4, iclass 28, count 0 2006.257.11:48:04.19#ibcon#about to read 5, iclass 28, count 0 2006.257.11:48:04.19#ibcon#read 5, iclass 28, count 0 2006.257.11:48:04.19#ibcon#about to read 6, iclass 28, count 0 2006.257.11:48:04.19#ibcon#read 6, iclass 28, count 0 2006.257.11:48:04.19#ibcon#end of sib2, iclass 28, count 0 2006.257.11:48:04.19#ibcon#*after write, iclass 28, count 0 2006.257.11:48:04.19#ibcon#*before return 0, iclass 28, count 0 2006.257.11:48:04.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:48:04.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.11:48:04.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:48:04.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:48:04.19$vck44/vblo=8,744.99 2006.257.11:48:04.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.11:48:04.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.11:48:04.19#ibcon#ireg 17 cls_cnt 0 2006.257.11:48:04.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:48:04.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:48:04.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:48:04.19#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:48:04.19#ibcon#first serial, iclass 30, count 0 2006.257.11:48:04.19#ibcon#enter sib2, iclass 30, count 0 2006.257.11:48:04.19#ibcon#flushed, iclass 30, count 0 2006.257.11:48:04.19#ibcon#about to write, iclass 30, count 0 2006.257.11:48:04.19#ibcon#wrote, iclass 30, count 0 2006.257.11:48:04.19#ibcon#about to read 3, iclass 30, count 0 2006.257.11:48:04.21#ibcon#read 3, iclass 30, count 0 2006.257.11:48:04.21#ibcon#about to read 4, iclass 30, count 0 2006.257.11:48:04.21#ibcon#read 4, iclass 30, count 0 2006.257.11:48:04.21#ibcon#about to read 5, iclass 30, count 0 2006.257.11:48:04.21#ibcon#read 5, iclass 30, count 0 2006.257.11:48:04.21#ibcon#about to read 6, iclass 30, count 0 2006.257.11:48:04.21#ibcon#read 6, iclass 30, count 0 2006.257.11:48:04.21#ibcon#end of sib2, iclass 30, count 0 2006.257.11:48:04.21#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:48:04.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:48:04.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:48:04.21#ibcon#*before write, iclass 30, count 0 2006.257.11:48:04.21#ibcon#enter sib2, iclass 30, count 0 2006.257.11:48:04.21#ibcon#flushed, iclass 30, count 0 2006.257.11:48:04.21#ibcon#about to write, iclass 30, count 0 2006.257.11:48:04.21#ibcon#wrote, iclass 30, count 0 2006.257.11:48:04.21#ibcon#about to read 3, iclass 30, count 0 2006.257.11:48:04.25#ibcon#read 3, iclass 30, count 0 2006.257.11:48:04.25#ibcon#about to read 4, iclass 30, count 0 2006.257.11:48:04.25#ibcon#read 4, iclass 30, count 0 2006.257.11:48:04.25#ibcon#about to read 5, iclass 30, count 0 2006.257.11:48:04.25#ibcon#read 5, iclass 30, count 0 2006.257.11:48:04.25#ibcon#about to read 6, iclass 30, count 0 2006.257.11:48:04.25#ibcon#read 6, iclass 30, count 0 2006.257.11:48:04.25#ibcon#end of sib2, iclass 30, count 0 2006.257.11:48:04.25#ibcon#*after write, iclass 30, count 0 2006.257.11:48:04.25#ibcon#*before return 0, iclass 30, count 0 2006.257.11:48:04.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:48:04.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.11:48:04.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:48:04.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:48:04.25$vck44/vb=8,4 2006.257.11:48:04.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.11:48:04.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.11:48:04.25#ibcon#ireg 11 cls_cnt 2 2006.257.11:48:04.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:48:04.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:48:04.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:48:04.31#ibcon#enter wrdev, iclass 32, count 2 2006.257.11:48:04.31#ibcon#first serial, iclass 32, count 2 2006.257.11:48:04.31#ibcon#enter sib2, iclass 32, count 2 2006.257.11:48:04.31#ibcon#flushed, iclass 32, count 2 2006.257.11:48:04.31#ibcon#about to write, iclass 32, count 2 2006.257.11:48:04.31#ibcon#wrote, iclass 32, count 2 2006.257.11:48:04.31#ibcon#about to read 3, iclass 32, count 2 2006.257.11:48:04.33#ibcon#read 3, iclass 32, count 2 2006.257.11:48:04.33#ibcon#about to read 4, iclass 32, count 2 2006.257.11:48:04.33#ibcon#read 4, iclass 32, count 2 2006.257.11:48:04.33#ibcon#about to read 5, iclass 32, count 2 2006.257.11:48:04.33#ibcon#read 5, iclass 32, count 2 2006.257.11:48:04.33#ibcon#about to read 6, iclass 32, count 2 2006.257.11:48:04.33#ibcon#read 6, iclass 32, count 2 2006.257.11:48:04.33#ibcon#end of sib2, iclass 32, count 2 2006.257.11:48:04.33#ibcon#*mode == 0, iclass 32, count 2 2006.257.11:48:04.33#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.11:48:04.33#ibcon#[27=AT08-04\r\n] 2006.257.11:48:04.33#ibcon#*before write, iclass 32, count 2 2006.257.11:48:04.33#ibcon#enter sib2, iclass 32, count 2 2006.257.11:48:04.33#ibcon#flushed, iclass 32, count 2 2006.257.11:48:04.33#ibcon#about to write, iclass 32, count 2 2006.257.11:48:04.33#ibcon#wrote, iclass 32, count 2 2006.257.11:48:04.33#ibcon#about to read 3, iclass 32, count 2 2006.257.11:48:04.36#ibcon#read 3, iclass 32, count 2 2006.257.11:48:04.36#ibcon#about to read 4, iclass 32, count 2 2006.257.11:48:04.36#ibcon#read 4, iclass 32, count 2 2006.257.11:48:04.36#ibcon#about to read 5, iclass 32, count 2 2006.257.11:48:04.36#ibcon#read 5, iclass 32, count 2 2006.257.11:48:04.36#ibcon#about to read 6, iclass 32, count 2 2006.257.11:48:04.36#ibcon#read 6, iclass 32, count 2 2006.257.11:48:04.36#ibcon#end of sib2, iclass 32, count 2 2006.257.11:48:04.36#ibcon#*after write, iclass 32, count 2 2006.257.11:48:04.36#ibcon#*before return 0, iclass 32, count 2 2006.257.11:48:04.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:48:04.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.11:48:04.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.11:48:04.36#ibcon#ireg 7 cls_cnt 0 2006.257.11:48:04.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:48:04.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:48:04.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:48:04.48#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:48:04.48#ibcon#first serial, iclass 32, count 0 2006.257.11:48:04.48#ibcon#enter sib2, iclass 32, count 0 2006.257.11:48:04.48#ibcon#flushed, iclass 32, count 0 2006.257.11:48:04.48#ibcon#about to write, iclass 32, count 0 2006.257.11:48:04.48#ibcon#wrote, iclass 32, count 0 2006.257.11:48:04.48#ibcon#about to read 3, iclass 32, count 0 2006.257.11:48:04.50#ibcon#read 3, iclass 32, count 0 2006.257.11:48:04.50#ibcon#about to read 4, iclass 32, count 0 2006.257.11:48:04.50#ibcon#read 4, iclass 32, count 0 2006.257.11:48:04.50#ibcon#about to read 5, iclass 32, count 0 2006.257.11:48:04.50#ibcon#read 5, iclass 32, count 0 2006.257.11:48:04.50#ibcon#about to read 6, iclass 32, count 0 2006.257.11:48:04.50#ibcon#read 6, iclass 32, count 0 2006.257.11:48:04.50#ibcon#end of sib2, iclass 32, count 0 2006.257.11:48:04.50#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:48:04.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:48:04.50#ibcon#[27=USB\r\n] 2006.257.11:48:04.50#ibcon#*before write, iclass 32, count 0 2006.257.11:48:04.50#ibcon#enter sib2, iclass 32, count 0 2006.257.11:48:04.50#ibcon#flushed, iclass 32, count 0 2006.257.11:48:04.50#ibcon#about to write, iclass 32, count 0 2006.257.11:48:04.50#ibcon#wrote, iclass 32, count 0 2006.257.11:48:04.50#ibcon#about to read 3, iclass 32, count 0 2006.257.11:48:04.53#ibcon#read 3, iclass 32, count 0 2006.257.11:48:04.53#ibcon#about to read 4, iclass 32, count 0 2006.257.11:48:04.53#ibcon#read 4, iclass 32, count 0 2006.257.11:48:04.53#ibcon#about to read 5, iclass 32, count 0 2006.257.11:48:04.53#ibcon#read 5, iclass 32, count 0 2006.257.11:48:04.53#ibcon#about to read 6, iclass 32, count 0 2006.257.11:48:04.53#ibcon#read 6, iclass 32, count 0 2006.257.11:48:04.53#ibcon#end of sib2, iclass 32, count 0 2006.257.11:48:04.53#ibcon#*after write, iclass 32, count 0 2006.257.11:48:04.53#ibcon#*before return 0, iclass 32, count 0 2006.257.11:48:04.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:48:04.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.11:48:04.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:48:04.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:48:04.53$vck44/vabw=wide 2006.257.11:48:04.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.11:48:04.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.11:48:04.53#ibcon#ireg 8 cls_cnt 0 2006.257.11:48:04.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:48:04.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:48:04.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:48:04.53#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:48:04.53#ibcon#first serial, iclass 34, count 0 2006.257.11:48:04.53#ibcon#enter sib2, iclass 34, count 0 2006.257.11:48:04.53#ibcon#flushed, iclass 34, count 0 2006.257.11:48:04.53#ibcon#about to write, iclass 34, count 0 2006.257.11:48:04.53#ibcon#wrote, iclass 34, count 0 2006.257.11:48:04.53#ibcon#about to read 3, iclass 34, count 0 2006.257.11:48:04.55#ibcon#read 3, iclass 34, count 0 2006.257.11:48:04.55#ibcon#about to read 4, iclass 34, count 0 2006.257.11:48:04.55#ibcon#read 4, iclass 34, count 0 2006.257.11:48:04.55#ibcon#about to read 5, iclass 34, count 0 2006.257.11:48:04.55#ibcon#read 5, iclass 34, count 0 2006.257.11:48:04.55#ibcon#about to read 6, iclass 34, count 0 2006.257.11:48:04.55#ibcon#read 6, iclass 34, count 0 2006.257.11:48:04.55#ibcon#end of sib2, iclass 34, count 0 2006.257.11:48:04.55#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:48:04.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:48:04.55#ibcon#[25=BW32\r\n] 2006.257.11:48:04.55#ibcon#*before write, iclass 34, count 0 2006.257.11:48:04.55#ibcon#enter sib2, iclass 34, count 0 2006.257.11:48:04.55#ibcon#flushed, iclass 34, count 0 2006.257.11:48:04.55#ibcon#about to write, iclass 34, count 0 2006.257.11:48:04.55#ibcon#wrote, iclass 34, count 0 2006.257.11:48:04.55#ibcon#about to read 3, iclass 34, count 0 2006.257.11:48:04.58#ibcon#read 3, iclass 34, count 0 2006.257.11:48:04.58#ibcon#about to read 4, iclass 34, count 0 2006.257.11:48:04.58#ibcon#read 4, iclass 34, count 0 2006.257.11:48:04.58#ibcon#about to read 5, iclass 34, count 0 2006.257.11:48:04.58#ibcon#read 5, iclass 34, count 0 2006.257.11:48:04.58#ibcon#about to read 6, iclass 34, count 0 2006.257.11:48:04.58#ibcon#read 6, iclass 34, count 0 2006.257.11:48:04.58#ibcon#end of sib2, iclass 34, count 0 2006.257.11:48:04.58#ibcon#*after write, iclass 34, count 0 2006.257.11:48:04.58#ibcon#*before return 0, iclass 34, count 0 2006.257.11:48:04.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:48:04.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.11:48:04.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:48:04.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:48:04.58$vck44/vbbw=wide 2006.257.11:48:04.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.11:48:04.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.11:48:04.58#ibcon#ireg 8 cls_cnt 0 2006.257.11:48:04.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:48:04.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:48:04.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:48:04.65#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:48:04.65#ibcon#first serial, iclass 36, count 0 2006.257.11:48:04.65#ibcon#enter sib2, iclass 36, count 0 2006.257.11:48:04.65#ibcon#flushed, iclass 36, count 0 2006.257.11:48:04.65#ibcon#about to write, iclass 36, count 0 2006.257.11:48:04.65#ibcon#wrote, iclass 36, count 0 2006.257.11:48:04.65#ibcon#about to read 3, iclass 36, count 0 2006.257.11:48:04.67#ibcon#read 3, iclass 36, count 0 2006.257.11:48:04.67#ibcon#about to read 4, iclass 36, count 0 2006.257.11:48:04.67#ibcon#read 4, iclass 36, count 0 2006.257.11:48:04.67#ibcon#about to read 5, iclass 36, count 0 2006.257.11:48:04.67#ibcon#read 5, iclass 36, count 0 2006.257.11:48:04.67#ibcon#about to read 6, iclass 36, count 0 2006.257.11:48:04.67#ibcon#read 6, iclass 36, count 0 2006.257.11:48:04.67#ibcon#end of sib2, iclass 36, count 0 2006.257.11:48:04.67#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:48:04.67#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:48:04.67#ibcon#[27=BW32\r\n] 2006.257.11:48:04.67#ibcon#*before write, iclass 36, count 0 2006.257.11:48:04.67#ibcon#enter sib2, iclass 36, count 0 2006.257.11:48:04.67#ibcon#flushed, iclass 36, count 0 2006.257.11:48:04.67#ibcon#about to write, iclass 36, count 0 2006.257.11:48:04.67#ibcon#wrote, iclass 36, count 0 2006.257.11:48:04.67#ibcon#about to read 3, iclass 36, count 0 2006.257.11:48:04.70#ibcon#read 3, iclass 36, count 0 2006.257.11:48:04.70#ibcon#about to read 4, iclass 36, count 0 2006.257.11:48:04.70#ibcon#read 4, iclass 36, count 0 2006.257.11:48:04.70#ibcon#about to read 5, iclass 36, count 0 2006.257.11:48:04.70#ibcon#read 5, iclass 36, count 0 2006.257.11:48:04.70#ibcon#about to read 6, iclass 36, count 0 2006.257.11:48:04.70#ibcon#read 6, iclass 36, count 0 2006.257.11:48:04.70#ibcon#end of sib2, iclass 36, count 0 2006.257.11:48:04.70#ibcon#*after write, iclass 36, count 0 2006.257.11:48:04.70#ibcon#*before return 0, iclass 36, count 0 2006.257.11:48:04.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:48:04.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:48:04.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:48:04.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:48:04.70$setupk4/ifdk4 2006.257.11:48:04.70$ifdk4/lo= 2006.257.11:48:04.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:48:04.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:48:04.70$ifdk4/patch= 2006.257.11:48:04.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:48:04.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:48:04.70$setupk4/!*+20s 2006.257.11:48:09.54#abcon#<5=/13 1.4 3.8 18.16 951014.0\r\n> 2006.257.11:48:09.56#abcon#{5=INTERFACE CLEAR} 2006.257.11:48:09.62#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:48:13.13#trakl#Source acquired 2006.257.11:48:15.07$setupk4/"tpicd 2006.257.11:48:15.07$setupk4/echo=off 2006.257.11:48:15.07$setupk4/xlog=off 2006.257.11:48:15.07:!2006.257.11:50:41 2006.257.11:48:15.13#flagr#flagr/antenna,acquired 2006.257.11:50:41.00:preob 2006.257.11:50:41.14/onsource/TRACKING 2006.257.11:50:41.14:!2006.257.11:50:51 2006.257.11:50:51.00:"tape 2006.257.11:50:51.00:"st=record 2006.257.11:50:51.00:data_valid=on 2006.257.11:50:51.00:midob 2006.257.11:50:51.14/onsource/TRACKING 2006.257.11:50:51.14/wx/18.18,1014.0,95 2006.257.11:50:51.19/cable/+6.4795E-03 2006.257.11:50:52.28/va/01,08,usb,yes,30,32 2006.257.11:50:52.28/va/02,07,usb,yes,33,33 2006.257.11:50:52.28/va/03,08,usb,yes,29,31 2006.257.11:50:52.28/va/04,07,usb,yes,33,35 2006.257.11:50:52.28/va/05,04,usb,yes,30,30 2006.257.11:50:52.28/va/06,04,usb,yes,33,33 2006.257.11:50:52.28/va/07,04,usb,yes,34,35 2006.257.11:50:52.28/va/08,04,usb,yes,28,35 2006.257.11:50:52.51/valo/01,524.99,yes,locked 2006.257.11:50:52.51/valo/02,534.99,yes,locked 2006.257.11:50:52.51/valo/03,564.99,yes,locked 2006.257.11:50:52.51/valo/04,624.99,yes,locked 2006.257.11:50:52.51/valo/05,734.99,yes,locked 2006.257.11:50:52.51/valo/06,814.99,yes,locked 2006.257.11:50:52.51/valo/07,864.99,yes,locked 2006.257.11:50:52.51/valo/08,884.99,yes,locked 2006.257.11:50:53.60/vb/01,04,usb,yes,30,28 2006.257.11:50:53.60/vb/02,05,usb,yes,29,28 2006.257.11:50:53.60/vb/03,04,usb,yes,29,32 2006.257.11:50:53.60/vb/04,05,usb,yes,30,29 2006.257.11:50:53.60/vb/05,04,usb,yes,26,29 2006.257.11:50:53.60/vb/06,04,usb,yes,31,27 2006.257.11:50:53.60/vb/07,04,usb,yes,30,30 2006.257.11:50:53.60/vb/08,04,usb,yes,28,31 2006.257.11:50:53.84/vblo/01,629.99,yes,locked 2006.257.11:50:53.84/vblo/02,634.99,yes,locked 2006.257.11:50:53.84/vblo/03,649.99,yes,locked 2006.257.11:50:53.84/vblo/04,679.99,yes,locked 2006.257.11:50:53.84/vblo/05,709.99,yes,locked 2006.257.11:50:53.84/vblo/06,719.99,yes,locked 2006.257.11:50:53.84/vblo/07,734.99,yes,locked 2006.257.11:50:53.84/vblo/08,744.99,yes,locked 2006.257.11:50:53.99/vabw/8 2006.257.11:50:54.14/vbbw/8 2006.257.11:50:54.23/xfe/off,on,15.2 2006.257.11:50:54.61/ifatt/23,28,28,28 2006.257.11:50:55.07/fmout-gps/S +4.59E-07 2006.257.11:50:55.11:!2006.257.11:52:01 2006.257.11:52:01.01:data_valid=off 2006.257.11:52:01.01:"et 2006.257.11:52:01.01:!+3s 2006.257.11:52:04.02:"tape 2006.257.11:52:04.02:postob 2006.257.11:52:04.23/cable/+6.4795E-03 2006.257.11:52:04.23/wx/18.19,1014.0,95 2006.257.11:52:04.29/fmout-gps/S +4.59E-07 2006.257.11:52:04.29:scan_name=257-1153,jd0609,40 2006.257.11:52:04.29:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.257.11:52:06.14#flagr#flagr/antenna,new-source 2006.257.11:52:06.14:checkk5 2006.257.11:52:06.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:52:06.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:52:07.32/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:52:07.72/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:52:08.11/chk_obsdata//k5ts1/T2571150??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.11:52:08.50/chk_obsdata//k5ts2/T2571150??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.11:52:08.90/chk_obsdata//k5ts3/T2571150??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.11:52:09.30/chk_obsdata//k5ts4/T2571150??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.11:52:10.02/k5log//k5ts1_log_newline 2006.257.11:52:10.73/k5log//k5ts2_log_newline 2006.257.11:52:11.44/k5log//k5ts3_log_newline 2006.257.11:52:12.15/k5log//k5ts4_log_newline 2006.257.11:52:12.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:52:12.17:setupk4=1 2006.257.11:52:12.17$setupk4/echo=on 2006.257.11:52:12.17$setupk4/pcalon 2006.257.11:52:12.17$pcalon/"no phase cal control is implemented here 2006.257.11:52:12.17$setupk4/"tpicd=stop 2006.257.11:52:12.17$setupk4/"rec=synch_on 2006.257.11:52:12.17$setupk4/"rec_mode=128 2006.257.11:52:12.17$setupk4/!* 2006.257.11:52:12.17$setupk4/recpk4 2006.257.11:52:12.17$recpk4/recpatch= 2006.257.11:52:12.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:52:12.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:52:12.17$setupk4/vck44 2006.257.11:52:12.17$vck44/valo=1,524.99 2006.257.11:52:12.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.11:52:12.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.11:52:12.17#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:12.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:12.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:12.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:12.17#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:52:12.17#ibcon#first serial, iclass 29, count 0 2006.257.11:52:12.17#ibcon#enter sib2, iclass 29, count 0 2006.257.11:52:12.17#ibcon#flushed, iclass 29, count 0 2006.257.11:52:12.17#ibcon#about to write, iclass 29, count 0 2006.257.11:52:12.17#ibcon#wrote, iclass 29, count 0 2006.257.11:52:12.17#ibcon#about to read 3, iclass 29, count 0 2006.257.11:52:12.19#ibcon#read 3, iclass 29, count 0 2006.257.11:52:12.19#ibcon#about to read 4, iclass 29, count 0 2006.257.11:52:12.19#ibcon#read 4, iclass 29, count 0 2006.257.11:52:12.19#ibcon#about to read 5, iclass 29, count 0 2006.257.11:52:12.19#ibcon#read 5, iclass 29, count 0 2006.257.11:52:12.19#ibcon#about to read 6, iclass 29, count 0 2006.257.11:52:12.19#ibcon#read 6, iclass 29, count 0 2006.257.11:52:12.19#ibcon#end of sib2, iclass 29, count 0 2006.257.11:52:12.19#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:52:12.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:52:12.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:52:12.19#ibcon#*before write, iclass 29, count 0 2006.257.11:52:12.19#ibcon#enter sib2, iclass 29, count 0 2006.257.11:52:12.19#ibcon#flushed, iclass 29, count 0 2006.257.11:52:12.19#ibcon#about to write, iclass 29, count 0 2006.257.11:52:12.19#ibcon#wrote, iclass 29, count 0 2006.257.11:52:12.19#ibcon#about to read 3, iclass 29, count 0 2006.257.11:52:12.24#ibcon#read 3, iclass 29, count 0 2006.257.11:52:12.24#ibcon#about to read 4, iclass 29, count 0 2006.257.11:52:12.24#ibcon#read 4, iclass 29, count 0 2006.257.11:52:12.24#ibcon#about to read 5, iclass 29, count 0 2006.257.11:52:12.24#ibcon#read 5, iclass 29, count 0 2006.257.11:52:12.24#ibcon#about to read 6, iclass 29, count 0 2006.257.11:52:12.24#ibcon#read 6, iclass 29, count 0 2006.257.11:52:12.24#ibcon#end of sib2, iclass 29, count 0 2006.257.11:52:12.24#ibcon#*after write, iclass 29, count 0 2006.257.11:52:12.24#ibcon#*before return 0, iclass 29, count 0 2006.257.11:52:12.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:12.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:12.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:52:12.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:52:12.24$vck44/va=1,8 2006.257.11:52:12.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.11:52:12.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.11:52:12.24#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:12.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:12.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:12.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:12.24#ibcon#enter wrdev, iclass 31, count 2 2006.257.11:52:12.24#ibcon#first serial, iclass 31, count 2 2006.257.11:52:12.24#ibcon#enter sib2, iclass 31, count 2 2006.257.11:52:12.24#ibcon#flushed, iclass 31, count 2 2006.257.11:52:12.24#ibcon#about to write, iclass 31, count 2 2006.257.11:52:12.24#ibcon#wrote, iclass 31, count 2 2006.257.11:52:12.24#ibcon#about to read 3, iclass 31, count 2 2006.257.11:52:12.26#ibcon#read 3, iclass 31, count 2 2006.257.11:52:12.26#ibcon#about to read 4, iclass 31, count 2 2006.257.11:52:12.26#ibcon#read 4, iclass 31, count 2 2006.257.11:52:12.26#ibcon#about to read 5, iclass 31, count 2 2006.257.11:52:12.26#ibcon#read 5, iclass 31, count 2 2006.257.11:52:12.26#ibcon#about to read 6, iclass 31, count 2 2006.257.11:52:12.26#ibcon#read 6, iclass 31, count 2 2006.257.11:52:12.26#ibcon#end of sib2, iclass 31, count 2 2006.257.11:52:12.26#ibcon#*mode == 0, iclass 31, count 2 2006.257.11:52:12.26#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.11:52:12.26#ibcon#[25=AT01-08\r\n] 2006.257.11:52:12.26#ibcon#*before write, iclass 31, count 2 2006.257.11:52:12.26#ibcon#enter sib2, iclass 31, count 2 2006.257.11:52:12.26#ibcon#flushed, iclass 31, count 2 2006.257.11:52:12.26#ibcon#about to write, iclass 31, count 2 2006.257.11:52:12.26#ibcon#wrote, iclass 31, count 2 2006.257.11:52:12.26#ibcon#about to read 3, iclass 31, count 2 2006.257.11:52:12.29#ibcon#read 3, iclass 31, count 2 2006.257.11:52:12.29#ibcon#about to read 4, iclass 31, count 2 2006.257.11:52:12.29#ibcon#read 4, iclass 31, count 2 2006.257.11:52:12.29#ibcon#about to read 5, iclass 31, count 2 2006.257.11:52:12.29#ibcon#read 5, iclass 31, count 2 2006.257.11:52:12.29#ibcon#about to read 6, iclass 31, count 2 2006.257.11:52:12.29#ibcon#read 6, iclass 31, count 2 2006.257.11:52:12.29#ibcon#end of sib2, iclass 31, count 2 2006.257.11:52:12.29#ibcon#*after write, iclass 31, count 2 2006.257.11:52:12.29#ibcon#*before return 0, iclass 31, count 2 2006.257.11:52:12.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:12.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:12.29#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.11:52:12.29#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:12.29#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:12.41#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:12.41#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:12.41#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:52:12.41#ibcon#first serial, iclass 31, count 0 2006.257.11:52:12.41#ibcon#enter sib2, iclass 31, count 0 2006.257.11:52:12.41#ibcon#flushed, iclass 31, count 0 2006.257.11:52:12.41#ibcon#about to write, iclass 31, count 0 2006.257.11:52:12.41#ibcon#wrote, iclass 31, count 0 2006.257.11:52:12.41#ibcon#about to read 3, iclass 31, count 0 2006.257.11:52:12.43#ibcon#read 3, iclass 31, count 0 2006.257.11:52:12.43#ibcon#about to read 4, iclass 31, count 0 2006.257.11:52:12.43#ibcon#read 4, iclass 31, count 0 2006.257.11:52:12.43#ibcon#about to read 5, iclass 31, count 0 2006.257.11:52:12.43#ibcon#read 5, iclass 31, count 0 2006.257.11:52:12.43#ibcon#about to read 6, iclass 31, count 0 2006.257.11:52:12.43#ibcon#read 6, iclass 31, count 0 2006.257.11:52:12.43#ibcon#end of sib2, iclass 31, count 0 2006.257.11:52:12.43#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:52:12.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:52:12.43#ibcon#[25=USB\r\n] 2006.257.11:52:12.43#ibcon#*before write, iclass 31, count 0 2006.257.11:52:12.43#ibcon#enter sib2, iclass 31, count 0 2006.257.11:52:12.43#ibcon#flushed, iclass 31, count 0 2006.257.11:52:12.43#ibcon#about to write, iclass 31, count 0 2006.257.11:52:12.43#ibcon#wrote, iclass 31, count 0 2006.257.11:52:12.43#ibcon#about to read 3, iclass 31, count 0 2006.257.11:52:12.46#ibcon#read 3, iclass 31, count 0 2006.257.11:52:12.46#ibcon#about to read 4, iclass 31, count 0 2006.257.11:52:12.46#ibcon#read 4, iclass 31, count 0 2006.257.11:52:12.46#ibcon#about to read 5, iclass 31, count 0 2006.257.11:52:12.46#ibcon#read 5, iclass 31, count 0 2006.257.11:52:12.46#ibcon#about to read 6, iclass 31, count 0 2006.257.11:52:12.46#ibcon#read 6, iclass 31, count 0 2006.257.11:52:12.46#ibcon#end of sib2, iclass 31, count 0 2006.257.11:52:12.46#ibcon#*after write, iclass 31, count 0 2006.257.11:52:12.46#ibcon#*before return 0, iclass 31, count 0 2006.257.11:52:12.46#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:12.46#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:12.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:52:12.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:52:12.46$vck44/valo=2,534.99 2006.257.11:52:12.46#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.11:52:12.46#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.11:52:12.46#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:12.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:12.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:12.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:12.46#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:52:12.46#ibcon#first serial, iclass 33, count 0 2006.257.11:52:12.46#ibcon#enter sib2, iclass 33, count 0 2006.257.11:52:12.46#ibcon#flushed, iclass 33, count 0 2006.257.11:52:12.46#ibcon#about to write, iclass 33, count 0 2006.257.11:52:12.46#ibcon#wrote, iclass 33, count 0 2006.257.11:52:12.46#ibcon#about to read 3, iclass 33, count 0 2006.257.11:52:12.48#ibcon#read 3, iclass 33, count 0 2006.257.11:52:12.48#ibcon#about to read 4, iclass 33, count 0 2006.257.11:52:12.48#ibcon#read 4, iclass 33, count 0 2006.257.11:52:12.48#ibcon#about to read 5, iclass 33, count 0 2006.257.11:52:12.48#ibcon#read 5, iclass 33, count 0 2006.257.11:52:12.48#ibcon#about to read 6, iclass 33, count 0 2006.257.11:52:12.48#ibcon#read 6, iclass 33, count 0 2006.257.11:52:12.48#ibcon#end of sib2, iclass 33, count 0 2006.257.11:52:12.48#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:52:12.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:52:12.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:52:12.48#ibcon#*before write, iclass 33, count 0 2006.257.11:52:12.48#ibcon#enter sib2, iclass 33, count 0 2006.257.11:52:12.48#ibcon#flushed, iclass 33, count 0 2006.257.11:52:12.48#ibcon#about to write, iclass 33, count 0 2006.257.11:52:12.48#ibcon#wrote, iclass 33, count 0 2006.257.11:52:12.48#ibcon#about to read 3, iclass 33, count 0 2006.257.11:52:12.52#ibcon#read 3, iclass 33, count 0 2006.257.11:52:12.52#ibcon#about to read 4, iclass 33, count 0 2006.257.11:52:12.52#ibcon#read 4, iclass 33, count 0 2006.257.11:52:12.52#ibcon#about to read 5, iclass 33, count 0 2006.257.11:52:12.52#ibcon#read 5, iclass 33, count 0 2006.257.11:52:12.52#ibcon#about to read 6, iclass 33, count 0 2006.257.11:52:12.52#ibcon#read 6, iclass 33, count 0 2006.257.11:52:12.52#ibcon#end of sib2, iclass 33, count 0 2006.257.11:52:12.52#ibcon#*after write, iclass 33, count 0 2006.257.11:52:12.52#ibcon#*before return 0, iclass 33, count 0 2006.257.11:52:12.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:12.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:12.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:52:12.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:52:12.52$vck44/va=2,7 2006.257.11:52:12.52#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.11:52:12.52#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.11:52:12.52#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:12.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:12.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:12.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:12.58#ibcon#enter wrdev, iclass 35, count 2 2006.257.11:52:12.58#ibcon#first serial, iclass 35, count 2 2006.257.11:52:12.58#ibcon#enter sib2, iclass 35, count 2 2006.257.11:52:12.58#ibcon#flushed, iclass 35, count 2 2006.257.11:52:12.58#ibcon#about to write, iclass 35, count 2 2006.257.11:52:12.58#ibcon#wrote, iclass 35, count 2 2006.257.11:52:12.58#ibcon#about to read 3, iclass 35, count 2 2006.257.11:52:12.60#ibcon#read 3, iclass 35, count 2 2006.257.11:52:12.60#ibcon#about to read 4, iclass 35, count 2 2006.257.11:52:12.60#ibcon#read 4, iclass 35, count 2 2006.257.11:52:12.60#ibcon#about to read 5, iclass 35, count 2 2006.257.11:52:12.60#ibcon#read 5, iclass 35, count 2 2006.257.11:52:12.60#ibcon#about to read 6, iclass 35, count 2 2006.257.11:52:12.60#ibcon#read 6, iclass 35, count 2 2006.257.11:52:12.60#ibcon#end of sib2, iclass 35, count 2 2006.257.11:52:12.60#ibcon#*mode == 0, iclass 35, count 2 2006.257.11:52:12.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.11:52:12.60#ibcon#[25=AT02-07\r\n] 2006.257.11:52:12.60#ibcon#*before write, iclass 35, count 2 2006.257.11:52:12.60#ibcon#enter sib2, iclass 35, count 2 2006.257.11:52:12.60#ibcon#flushed, iclass 35, count 2 2006.257.11:52:12.60#ibcon#about to write, iclass 35, count 2 2006.257.11:52:12.60#ibcon#wrote, iclass 35, count 2 2006.257.11:52:12.60#ibcon#about to read 3, iclass 35, count 2 2006.257.11:52:12.63#ibcon#read 3, iclass 35, count 2 2006.257.11:52:12.63#ibcon#about to read 4, iclass 35, count 2 2006.257.11:52:12.63#ibcon#read 4, iclass 35, count 2 2006.257.11:52:12.63#ibcon#about to read 5, iclass 35, count 2 2006.257.11:52:12.63#ibcon#read 5, iclass 35, count 2 2006.257.11:52:12.63#ibcon#about to read 6, iclass 35, count 2 2006.257.11:52:12.63#ibcon#read 6, iclass 35, count 2 2006.257.11:52:12.63#ibcon#end of sib2, iclass 35, count 2 2006.257.11:52:12.63#ibcon#*after write, iclass 35, count 2 2006.257.11:52:12.63#ibcon#*before return 0, iclass 35, count 2 2006.257.11:52:12.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:12.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:12.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.11:52:12.63#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:12.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:12.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:12.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:12.75#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:52:12.75#ibcon#first serial, iclass 35, count 0 2006.257.11:52:12.75#ibcon#enter sib2, iclass 35, count 0 2006.257.11:52:12.75#ibcon#flushed, iclass 35, count 0 2006.257.11:52:12.75#ibcon#about to write, iclass 35, count 0 2006.257.11:52:12.75#ibcon#wrote, iclass 35, count 0 2006.257.11:52:12.75#ibcon#about to read 3, iclass 35, count 0 2006.257.11:52:12.77#ibcon#read 3, iclass 35, count 0 2006.257.11:52:12.77#ibcon#about to read 4, iclass 35, count 0 2006.257.11:52:12.77#ibcon#read 4, iclass 35, count 0 2006.257.11:52:12.77#ibcon#about to read 5, iclass 35, count 0 2006.257.11:52:12.77#ibcon#read 5, iclass 35, count 0 2006.257.11:52:12.77#ibcon#about to read 6, iclass 35, count 0 2006.257.11:52:12.77#ibcon#read 6, iclass 35, count 0 2006.257.11:52:12.77#ibcon#end of sib2, iclass 35, count 0 2006.257.11:52:12.77#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:52:12.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:52:12.77#ibcon#[25=USB\r\n] 2006.257.11:52:12.77#ibcon#*before write, iclass 35, count 0 2006.257.11:52:12.77#ibcon#enter sib2, iclass 35, count 0 2006.257.11:52:12.77#ibcon#flushed, iclass 35, count 0 2006.257.11:52:12.77#ibcon#about to write, iclass 35, count 0 2006.257.11:52:12.77#ibcon#wrote, iclass 35, count 0 2006.257.11:52:12.77#ibcon#about to read 3, iclass 35, count 0 2006.257.11:52:12.80#ibcon#read 3, iclass 35, count 0 2006.257.11:52:12.80#ibcon#about to read 4, iclass 35, count 0 2006.257.11:52:12.80#ibcon#read 4, iclass 35, count 0 2006.257.11:52:12.80#ibcon#about to read 5, iclass 35, count 0 2006.257.11:52:12.80#ibcon#read 5, iclass 35, count 0 2006.257.11:52:12.80#ibcon#about to read 6, iclass 35, count 0 2006.257.11:52:12.80#ibcon#read 6, iclass 35, count 0 2006.257.11:52:12.80#ibcon#end of sib2, iclass 35, count 0 2006.257.11:52:12.80#ibcon#*after write, iclass 35, count 0 2006.257.11:52:12.80#ibcon#*before return 0, iclass 35, count 0 2006.257.11:52:12.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:12.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:12.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:52:12.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:52:12.80$vck44/valo=3,564.99 2006.257.11:52:12.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.11:52:12.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.11:52:12.80#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:12.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:12.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:12.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:12.80#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:52:12.80#ibcon#first serial, iclass 37, count 0 2006.257.11:52:12.80#ibcon#enter sib2, iclass 37, count 0 2006.257.11:52:12.80#ibcon#flushed, iclass 37, count 0 2006.257.11:52:12.80#ibcon#about to write, iclass 37, count 0 2006.257.11:52:12.80#ibcon#wrote, iclass 37, count 0 2006.257.11:52:12.80#ibcon#about to read 3, iclass 37, count 0 2006.257.11:52:12.82#ibcon#read 3, iclass 37, count 0 2006.257.11:52:12.82#ibcon#about to read 4, iclass 37, count 0 2006.257.11:52:12.82#ibcon#read 4, iclass 37, count 0 2006.257.11:52:12.82#ibcon#about to read 5, iclass 37, count 0 2006.257.11:52:12.82#ibcon#read 5, iclass 37, count 0 2006.257.11:52:12.82#ibcon#about to read 6, iclass 37, count 0 2006.257.11:52:12.82#ibcon#read 6, iclass 37, count 0 2006.257.11:52:12.82#ibcon#end of sib2, iclass 37, count 0 2006.257.11:52:12.82#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:52:12.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:52:12.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:52:12.82#ibcon#*before write, iclass 37, count 0 2006.257.11:52:12.82#ibcon#enter sib2, iclass 37, count 0 2006.257.11:52:12.82#ibcon#flushed, iclass 37, count 0 2006.257.11:52:12.82#ibcon#about to write, iclass 37, count 0 2006.257.11:52:12.82#ibcon#wrote, iclass 37, count 0 2006.257.11:52:12.82#ibcon#about to read 3, iclass 37, count 0 2006.257.11:52:12.86#ibcon#read 3, iclass 37, count 0 2006.257.11:52:12.86#ibcon#about to read 4, iclass 37, count 0 2006.257.11:52:12.86#ibcon#read 4, iclass 37, count 0 2006.257.11:52:12.86#ibcon#about to read 5, iclass 37, count 0 2006.257.11:52:12.86#ibcon#read 5, iclass 37, count 0 2006.257.11:52:12.86#ibcon#about to read 6, iclass 37, count 0 2006.257.11:52:12.86#ibcon#read 6, iclass 37, count 0 2006.257.11:52:12.86#ibcon#end of sib2, iclass 37, count 0 2006.257.11:52:12.86#ibcon#*after write, iclass 37, count 0 2006.257.11:52:12.86#ibcon#*before return 0, iclass 37, count 0 2006.257.11:52:12.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:12.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:12.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:52:12.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:52:12.86$vck44/va=3,8 2006.257.11:52:12.86#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.11:52:12.86#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.11:52:12.86#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:12.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:12.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:12.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:12.92#ibcon#enter wrdev, iclass 39, count 2 2006.257.11:52:12.92#ibcon#first serial, iclass 39, count 2 2006.257.11:52:12.92#ibcon#enter sib2, iclass 39, count 2 2006.257.11:52:12.92#ibcon#flushed, iclass 39, count 2 2006.257.11:52:12.92#ibcon#about to write, iclass 39, count 2 2006.257.11:52:12.92#ibcon#wrote, iclass 39, count 2 2006.257.11:52:12.92#ibcon#about to read 3, iclass 39, count 2 2006.257.11:52:12.94#ibcon#read 3, iclass 39, count 2 2006.257.11:52:12.94#ibcon#about to read 4, iclass 39, count 2 2006.257.11:52:12.94#ibcon#read 4, iclass 39, count 2 2006.257.11:52:12.94#ibcon#about to read 5, iclass 39, count 2 2006.257.11:52:12.94#ibcon#read 5, iclass 39, count 2 2006.257.11:52:12.94#ibcon#about to read 6, iclass 39, count 2 2006.257.11:52:12.94#ibcon#read 6, iclass 39, count 2 2006.257.11:52:12.94#ibcon#end of sib2, iclass 39, count 2 2006.257.11:52:12.94#ibcon#*mode == 0, iclass 39, count 2 2006.257.11:52:12.94#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.11:52:12.94#ibcon#[25=AT03-08\r\n] 2006.257.11:52:12.94#ibcon#*before write, iclass 39, count 2 2006.257.11:52:12.94#ibcon#enter sib2, iclass 39, count 2 2006.257.11:52:12.94#ibcon#flushed, iclass 39, count 2 2006.257.11:52:12.94#ibcon#about to write, iclass 39, count 2 2006.257.11:52:12.94#ibcon#wrote, iclass 39, count 2 2006.257.11:52:12.94#ibcon#about to read 3, iclass 39, count 2 2006.257.11:52:12.97#ibcon#read 3, iclass 39, count 2 2006.257.11:52:12.97#ibcon#about to read 4, iclass 39, count 2 2006.257.11:52:12.97#ibcon#read 4, iclass 39, count 2 2006.257.11:52:12.97#ibcon#about to read 5, iclass 39, count 2 2006.257.11:52:12.97#ibcon#read 5, iclass 39, count 2 2006.257.11:52:12.97#ibcon#about to read 6, iclass 39, count 2 2006.257.11:52:12.97#ibcon#read 6, iclass 39, count 2 2006.257.11:52:12.97#ibcon#end of sib2, iclass 39, count 2 2006.257.11:52:12.97#ibcon#*after write, iclass 39, count 2 2006.257.11:52:12.97#ibcon#*before return 0, iclass 39, count 2 2006.257.11:52:12.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:12.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:12.97#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.11:52:12.97#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:12.97#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:13.09#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:13.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:13.09#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:52:13.09#ibcon#first serial, iclass 39, count 0 2006.257.11:52:13.09#ibcon#enter sib2, iclass 39, count 0 2006.257.11:52:13.09#ibcon#flushed, iclass 39, count 0 2006.257.11:52:13.09#ibcon#about to write, iclass 39, count 0 2006.257.11:52:13.09#ibcon#wrote, iclass 39, count 0 2006.257.11:52:13.09#ibcon#about to read 3, iclass 39, count 0 2006.257.11:52:13.11#ibcon#read 3, iclass 39, count 0 2006.257.11:52:13.11#ibcon#about to read 4, iclass 39, count 0 2006.257.11:52:13.11#ibcon#read 4, iclass 39, count 0 2006.257.11:52:13.11#ibcon#about to read 5, iclass 39, count 0 2006.257.11:52:13.11#ibcon#read 5, iclass 39, count 0 2006.257.11:52:13.11#ibcon#about to read 6, iclass 39, count 0 2006.257.11:52:13.11#ibcon#read 6, iclass 39, count 0 2006.257.11:52:13.11#ibcon#end of sib2, iclass 39, count 0 2006.257.11:52:13.11#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:52:13.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:52:13.11#ibcon#[25=USB\r\n] 2006.257.11:52:13.11#ibcon#*before write, iclass 39, count 0 2006.257.11:52:13.11#ibcon#enter sib2, iclass 39, count 0 2006.257.11:52:13.11#ibcon#flushed, iclass 39, count 0 2006.257.11:52:13.11#ibcon#about to write, iclass 39, count 0 2006.257.11:52:13.11#ibcon#wrote, iclass 39, count 0 2006.257.11:52:13.11#ibcon#about to read 3, iclass 39, count 0 2006.257.11:52:13.14#ibcon#read 3, iclass 39, count 0 2006.257.11:52:13.14#ibcon#about to read 4, iclass 39, count 0 2006.257.11:52:13.14#ibcon#read 4, iclass 39, count 0 2006.257.11:52:13.14#ibcon#about to read 5, iclass 39, count 0 2006.257.11:52:13.14#ibcon#read 5, iclass 39, count 0 2006.257.11:52:13.14#ibcon#about to read 6, iclass 39, count 0 2006.257.11:52:13.14#ibcon#read 6, iclass 39, count 0 2006.257.11:52:13.14#ibcon#end of sib2, iclass 39, count 0 2006.257.11:52:13.14#ibcon#*after write, iclass 39, count 0 2006.257.11:52:13.14#ibcon#*before return 0, iclass 39, count 0 2006.257.11:52:13.14#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:13.14#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:13.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:52:13.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:52:13.14$vck44/valo=4,624.99 2006.257.11:52:13.14#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.11:52:13.14#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.11:52:13.14#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:13.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:13.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:13.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:13.14#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:52:13.14#ibcon#first serial, iclass 3, count 0 2006.257.11:52:13.14#ibcon#enter sib2, iclass 3, count 0 2006.257.11:52:13.14#ibcon#flushed, iclass 3, count 0 2006.257.11:52:13.14#ibcon#about to write, iclass 3, count 0 2006.257.11:52:13.14#ibcon#wrote, iclass 3, count 0 2006.257.11:52:13.14#ibcon#about to read 3, iclass 3, count 0 2006.257.11:52:13.16#ibcon#read 3, iclass 3, count 0 2006.257.11:52:13.16#ibcon#about to read 4, iclass 3, count 0 2006.257.11:52:13.16#ibcon#read 4, iclass 3, count 0 2006.257.11:52:13.16#ibcon#about to read 5, iclass 3, count 0 2006.257.11:52:13.16#ibcon#read 5, iclass 3, count 0 2006.257.11:52:13.16#ibcon#about to read 6, iclass 3, count 0 2006.257.11:52:13.16#ibcon#read 6, iclass 3, count 0 2006.257.11:52:13.16#ibcon#end of sib2, iclass 3, count 0 2006.257.11:52:13.16#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:52:13.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:52:13.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:52:13.16#ibcon#*before write, iclass 3, count 0 2006.257.11:52:13.16#ibcon#enter sib2, iclass 3, count 0 2006.257.11:52:13.16#ibcon#flushed, iclass 3, count 0 2006.257.11:52:13.16#ibcon#about to write, iclass 3, count 0 2006.257.11:52:13.16#ibcon#wrote, iclass 3, count 0 2006.257.11:52:13.16#ibcon#about to read 3, iclass 3, count 0 2006.257.11:52:13.20#ibcon#read 3, iclass 3, count 0 2006.257.11:52:13.20#ibcon#about to read 4, iclass 3, count 0 2006.257.11:52:13.20#ibcon#read 4, iclass 3, count 0 2006.257.11:52:13.20#ibcon#about to read 5, iclass 3, count 0 2006.257.11:52:13.20#ibcon#read 5, iclass 3, count 0 2006.257.11:52:13.20#ibcon#about to read 6, iclass 3, count 0 2006.257.11:52:13.20#ibcon#read 6, iclass 3, count 0 2006.257.11:52:13.20#ibcon#end of sib2, iclass 3, count 0 2006.257.11:52:13.20#ibcon#*after write, iclass 3, count 0 2006.257.11:52:13.20#ibcon#*before return 0, iclass 3, count 0 2006.257.11:52:13.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:13.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:13.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:52:13.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:52:13.20$vck44/va=4,7 2006.257.11:52:13.20#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.11:52:13.20#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.11:52:13.20#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:13.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:13.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:13.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:13.26#ibcon#enter wrdev, iclass 5, count 2 2006.257.11:52:13.26#ibcon#first serial, iclass 5, count 2 2006.257.11:52:13.26#ibcon#enter sib2, iclass 5, count 2 2006.257.11:52:13.26#ibcon#flushed, iclass 5, count 2 2006.257.11:52:13.26#ibcon#about to write, iclass 5, count 2 2006.257.11:52:13.26#ibcon#wrote, iclass 5, count 2 2006.257.11:52:13.26#ibcon#about to read 3, iclass 5, count 2 2006.257.11:52:13.28#ibcon#read 3, iclass 5, count 2 2006.257.11:52:13.28#ibcon#about to read 4, iclass 5, count 2 2006.257.11:52:13.28#ibcon#read 4, iclass 5, count 2 2006.257.11:52:13.28#ibcon#about to read 5, iclass 5, count 2 2006.257.11:52:13.28#ibcon#read 5, iclass 5, count 2 2006.257.11:52:13.28#ibcon#about to read 6, iclass 5, count 2 2006.257.11:52:13.28#ibcon#read 6, iclass 5, count 2 2006.257.11:52:13.28#ibcon#end of sib2, iclass 5, count 2 2006.257.11:52:13.28#ibcon#*mode == 0, iclass 5, count 2 2006.257.11:52:13.28#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.11:52:13.28#ibcon#[25=AT04-07\r\n] 2006.257.11:52:13.28#ibcon#*before write, iclass 5, count 2 2006.257.11:52:13.28#ibcon#enter sib2, iclass 5, count 2 2006.257.11:52:13.28#ibcon#flushed, iclass 5, count 2 2006.257.11:52:13.28#ibcon#about to write, iclass 5, count 2 2006.257.11:52:13.28#ibcon#wrote, iclass 5, count 2 2006.257.11:52:13.28#ibcon#about to read 3, iclass 5, count 2 2006.257.11:52:13.31#ibcon#read 3, iclass 5, count 2 2006.257.11:52:13.31#ibcon#about to read 4, iclass 5, count 2 2006.257.11:52:13.31#ibcon#read 4, iclass 5, count 2 2006.257.11:52:13.31#ibcon#about to read 5, iclass 5, count 2 2006.257.11:52:13.31#ibcon#read 5, iclass 5, count 2 2006.257.11:52:13.31#ibcon#about to read 6, iclass 5, count 2 2006.257.11:52:13.31#ibcon#read 6, iclass 5, count 2 2006.257.11:52:13.31#ibcon#end of sib2, iclass 5, count 2 2006.257.11:52:13.31#ibcon#*after write, iclass 5, count 2 2006.257.11:52:13.31#ibcon#*before return 0, iclass 5, count 2 2006.257.11:52:13.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:13.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:13.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.11:52:13.31#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:13.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:13.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:13.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:13.43#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:52:13.43#ibcon#first serial, iclass 5, count 0 2006.257.11:52:13.43#ibcon#enter sib2, iclass 5, count 0 2006.257.11:52:13.43#ibcon#flushed, iclass 5, count 0 2006.257.11:52:13.43#ibcon#about to write, iclass 5, count 0 2006.257.11:52:13.43#ibcon#wrote, iclass 5, count 0 2006.257.11:52:13.43#ibcon#about to read 3, iclass 5, count 0 2006.257.11:52:13.45#ibcon#read 3, iclass 5, count 0 2006.257.11:52:13.45#ibcon#about to read 4, iclass 5, count 0 2006.257.11:52:13.45#ibcon#read 4, iclass 5, count 0 2006.257.11:52:13.45#ibcon#about to read 5, iclass 5, count 0 2006.257.11:52:13.45#ibcon#read 5, iclass 5, count 0 2006.257.11:52:13.45#ibcon#about to read 6, iclass 5, count 0 2006.257.11:52:13.45#ibcon#read 6, iclass 5, count 0 2006.257.11:52:13.45#ibcon#end of sib2, iclass 5, count 0 2006.257.11:52:13.45#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:52:13.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:52:13.45#ibcon#[25=USB\r\n] 2006.257.11:52:13.45#ibcon#*before write, iclass 5, count 0 2006.257.11:52:13.45#ibcon#enter sib2, iclass 5, count 0 2006.257.11:52:13.45#ibcon#flushed, iclass 5, count 0 2006.257.11:52:13.45#ibcon#about to write, iclass 5, count 0 2006.257.11:52:13.45#ibcon#wrote, iclass 5, count 0 2006.257.11:52:13.45#ibcon#about to read 3, iclass 5, count 0 2006.257.11:52:13.48#ibcon#read 3, iclass 5, count 0 2006.257.11:52:13.48#ibcon#about to read 4, iclass 5, count 0 2006.257.11:52:13.48#ibcon#read 4, iclass 5, count 0 2006.257.11:52:13.48#ibcon#about to read 5, iclass 5, count 0 2006.257.11:52:13.48#ibcon#read 5, iclass 5, count 0 2006.257.11:52:13.48#ibcon#about to read 6, iclass 5, count 0 2006.257.11:52:13.48#ibcon#read 6, iclass 5, count 0 2006.257.11:52:13.48#ibcon#end of sib2, iclass 5, count 0 2006.257.11:52:13.48#ibcon#*after write, iclass 5, count 0 2006.257.11:52:13.48#ibcon#*before return 0, iclass 5, count 0 2006.257.11:52:13.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:13.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:13.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:52:13.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:52:13.48$vck44/valo=5,734.99 2006.257.11:52:13.48#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.11:52:13.48#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.11:52:13.48#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:13.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:13.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:13.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:13.48#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:52:13.48#ibcon#first serial, iclass 7, count 0 2006.257.11:52:13.48#ibcon#enter sib2, iclass 7, count 0 2006.257.11:52:13.48#ibcon#flushed, iclass 7, count 0 2006.257.11:52:13.48#ibcon#about to write, iclass 7, count 0 2006.257.11:52:13.48#ibcon#wrote, iclass 7, count 0 2006.257.11:52:13.48#ibcon#about to read 3, iclass 7, count 0 2006.257.11:52:13.50#ibcon#read 3, iclass 7, count 0 2006.257.11:52:13.50#ibcon#about to read 4, iclass 7, count 0 2006.257.11:52:13.50#ibcon#read 4, iclass 7, count 0 2006.257.11:52:13.50#ibcon#about to read 5, iclass 7, count 0 2006.257.11:52:13.50#ibcon#read 5, iclass 7, count 0 2006.257.11:52:13.50#ibcon#about to read 6, iclass 7, count 0 2006.257.11:52:13.50#ibcon#read 6, iclass 7, count 0 2006.257.11:52:13.50#ibcon#end of sib2, iclass 7, count 0 2006.257.11:52:13.50#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:52:13.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:52:13.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:52:13.50#ibcon#*before write, iclass 7, count 0 2006.257.11:52:13.50#ibcon#enter sib2, iclass 7, count 0 2006.257.11:52:13.50#ibcon#flushed, iclass 7, count 0 2006.257.11:52:13.50#ibcon#about to write, iclass 7, count 0 2006.257.11:52:13.50#ibcon#wrote, iclass 7, count 0 2006.257.11:52:13.50#ibcon#about to read 3, iclass 7, count 0 2006.257.11:52:13.54#ibcon#read 3, iclass 7, count 0 2006.257.11:52:13.54#ibcon#about to read 4, iclass 7, count 0 2006.257.11:52:13.54#ibcon#read 4, iclass 7, count 0 2006.257.11:52:13.54#ibcon#about to read 5, iclass 7, count 0 2006.257.11:52:13.54#ibcon#read 5, iclass 7, count 0 2006.257.11:52:13.54#ibcon#about to read 6, iclass 7, count 0 2006.257.11:52:13.54#ibcon#read 6, iclass 7, count 0 2006.257.11:52:13.54#ibcon#end of sib2, iclass 7, count 0 2006.257.11:52:13.54#ibcon#*after write, iclass 7, count 0 2006.257.11:52:13.54#ibcon#*before return 0, iclass 7, count 0 2006.257.11:52:13.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:13.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:13.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:52:13.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:52:13.54$vck44/va=5,4 2006.257.11:52:13.54#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.11:52:13.54#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.11:52:13.54#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:13.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:13.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:13.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:13.60#ibcon#enter wrdev, iclass 11, count 2 2006.257.11:52:13.60#ibcon#first serial, iclass 11, count 2 2006.257.11:52:13.60#ibcon#enter sib2, iclass 11, count 2 2006.257.11:52:13.60#ibcon#flushed, iclass 11, count 2 2006.257.11:52:13.60#ibcon#about to write, iclass 11, count 2 2006.257.11:52:13.60#ibcon#wrote, iclass 11, count 2 2006.257.11:52:13.60#ibcon#about to read 3, iclass 11, count 2 2006.257.11:52:13.62#ibcon#read 3, iclass 11, count 2 2006.257.11:52:13.62#ibcon#about to read 4, iclass 11, count 2 2006.257.11:52:13.62#ibcon#read 4, iclass 11, count 2 2006.257.11:52:13.62#ibcon#about to read 5, iclass 11, count 2 2006.257.11:52:13.62#ibcon#read 5, iclass 11, count 2 2006.257.11:52:13.62#ibcon#about to read 6, iclass 11, count 2 2006.257.11:52:13.62#ibcon#read 6, iclass 11, count 2 2006.257.11:52:13.62#ibcon#end of sib2, iclass 11, count 2 2006.257.11:52:13.62#ibcon#*mode == 0, iclass 11, count 2 2006.257.11:52:13.62#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.11:52:13.62#ibcon#[25=AT05-04\r\n] 2006.257.11:52:13.62#ibcon#*before write, iclass 11, count 2 2006.257.11:52:13.62#ibcon#enter sib2, iclass 11, count 2 2006.257.11:52:13.62#ibcon#flushed, iclass 11, count 2 2006.257.11:52:13.62#ibcon#about to write, iclass 11, count 2 2006.257.11:52:13.62#ibcon#wrote, iclass 11, count 2 2006.257.11:52:13.62#ibcon#about to read 3, iclass 11, count 2 2006.257.11:52:13.62#abcon#<5=/13 1.5 4.0 18.19 951014.0\r\n> 2006.257.11:52:13.64#abcon#{5=INTERFACE CLEAR} 2006.257.11:52:13.65#ibcon#read 3, iclass 11, count 2 2006.257.11:52:13.65#ibcon#about to read 4, iclass 11, count 2 2006.257.11:52:13.65#ibcon#read 4, iclass 11, count 2 2006.257.11:52:13.65#ibcon#about to read 5, iclass 11, count 2 2006.257.11:52:13.65#ibcon#read 5, iclass 11, count 2 2006.257.11:52:13.65#ibcon#about to read 6, iclass 11, count 2 2006.257.11:52:13.65#ibcon#read 6, iclass 11, count 2 2006.257.11:52:13.65#ibcon#end of sib2, iclass 11, count 2 2006.257.11:52:13.65#ibcon#*after write, iclass 11, count 2 2006.257.11:52:13.65#ibcon#*before return 0, iclass 11, count 2 2006.257.11:52:13.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:13.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:13.65#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.11:52:13.65#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:13.65#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:13.70#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:52:13.77#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:13.77#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:13.77#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:52:13.77#ibcon#first serial, iclass 11, count 0 2006.257.11:52:13.77#ibcon#enter sib2, iclass 11, count 0 2006.257.11:52:13.77#ibcon#flushed, iclass 11, count 0 2006.257.11:52:13.77#ibcon#about to write, iclass 11, count 0 2006.257.11:52:13.77#ibcon#wrote, iclass 11, count 0 2006.257.11:52:13.77#ibcon#about to read 3, iclass 11, count 0 2006.257.11:52:13.79#ibcon#read 3, iclass 11, count 0 2006.257.11:52:13.79#ibcon#about to read 4, iclass 11, count 0 2006.257.11:52:13.79#ibcon#read 4, iclass 11, count 0 2006.257.11:52:13.79#ibcon#about to read 5, iclass 11, count 0 2006.257.11:52:13.79#ibcon#read 5, iclass 11, count 0 2006.257.11:52:13.79#ibcon#about to read 6, iclass 11, count 0 2006.257.11:52:13.79#ibcon#read 6, iclass 11, count 0 2006.257.11:52:13.79#ibcon#end of sib2, iclass 11, count 0 2006.257.11:52:13.79#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:52:13.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:52:13.79#ibcon#[25=USB\r\n] 2006.257.11:52:13.79#ibcon#*before write, iclass 11, count 0 2006.257.11:52:13.79#ibcon#enter sib2, iclass 11, count 0 2006.257.11:52:13.79#ibcon#flushed, iclass 11, count 0 2006.257.11:52:13.79#ibcon#about to write, iclass 11, count 0 2006.257.11:52:13.79#ibcon#wrote, iclass 11, count 0 2006.257.11:52:13.79#ibcon#about to read 3, iclass 11, count 0 2006.257.11:52:13.82#ibcon#read 3, iclass 11, count 0 2006.257.11:52:13.82#ibcon#about to read 4, iclass 11, count 0 2006.257.11:52:13.82#ibcon#read 4, iclass 11, count 0 2006.257.11:52:13.82#ibcon#about to read 5, iclass 11, count 0 2006.257.11:52:13.82#ibcon#read 5, iclass 11, count 0 2006.257.11:52:13.82#ibcon#about to read 6, iclass 11, count 0 2006.257.11:52:13.82#ibcon#read 6, iclass 11, count 0 2006.257.11:52:13.82#ibcon#end of sib2, iclass 11, count 0 2006.257.11:52:13.82#ibcon#*after write, iclass 11, count 0 2006.257.11:52:13.82#ibcon#*before return 0, iclass 11, count 0 2006.257.11:52:13.82#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:13.82#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:13.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:52:13.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:52:13.82$vck44/valo=6,814.99 2006.257.11:52:13.82#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.11:52:13.82#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.11:52:13.82#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:13.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:13.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:13.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:13.82#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:52:13.82#ibcon#first serial, iclass 17, count 0 2006.257.11:52:13.82#ibcon#enter sib2, iclass 17, count 0 2006.257.11:52:13.82#ibcon#flushed, iclass 17, count 0 2006.257.11:52:13.82#ibcon#about to write, iclass 17, count 0 2006.257.11:52:13.82#ibcon#wrote, iclass 17, count 0 2006.257.11:52:13.82#ibcon#about to read 3, iclass 17, count 0 2006.257.11:52:13.84#ibcon#read 3, iclass 17, count 0 2006.257.11:52:13.84#ibcon#about to read 4, iclass 17, count 0 2006.257.11:52:13.84#ibcon#read 4, iclass 17, count 0 2006.257.11:52:13.84#ibcon#about to read 5, iclass 17, count 0 2006.257.11:52:13.84#ibcon#read 5, iclass 17, count 0 2006.257.11:52:13.84#ibcon#about to read 6, iclass 17, count 0 2006.257.11:52:13.84#ibcon#read 6, iclass 17, count 0 2006.257.11:52:13.84#ibcon#end of sib2, iclass 17, count 0 2006.257.11:52:13.84#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:52:13.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:52:13.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:52:13.84#ibcon#*before write, iclass 17, count 0 2006.257.11:52:13.84#ibcon#enter sib2, iclass 17, count 0 2006.257.11:52:13.84#ibcon#flushed, iclass 17, count 0 2006.257.11:52:13.84#ibcon#about to write, iclass 17, count 0 2006.257.11:52:13.84#ibcon#wrote, iclass 17, count 0 2006.257.11:52:13.84#ibcon#about to read 3, iclass 17, count 0 2006.257.11:52:13.88#ibcon#read 3, iclass 17, count 0 2006.257.11:52:13.88#ibcon#about to read 4, iclass 17, count 0 2006.257.11:52:13.88#ibcon#read 4, iclass 17, count 0 2006.257.11:52:13.88#ibcon#about to read 5, iclass 17, count 0 2006.257.11:52:13.88#ibcon#read 5, iclass 17, count 0 2006.257.11:52:13.88#ibcon#about to read 6, iclass 17, count 0 2006.257.11:52:13.88#ibcon#read 6, iclass 17, count 0 2006.257.11:52:13.88#ibcon#end of sib2, iclass 17, count 0 2006.257.11:52:13.88#ibcon#*after write, iclass 17, count 0 2006.257.11:52:13.88#ibcon#*before return 0, iclass 17, count 0 2006.257.11:52:13.88#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:13.88#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:13.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:52:13.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:52:13.88$vck44/va=6,4 2006.257.11:52:13.88#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.11:52:13.88#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.11:52:13.88#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:13.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:13.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:13.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:13.94#ibcon#enter wrdev, iclass 19, count 2 2006.257.11:52:13.94#ibcon#first serial, iclass 19, count 2 2006.257.11:52:13.94#ibcon#enter sib2, iclass 19, count 2 2006.257.11:52:13.94#ibcon#flushed, iclass 19, count 2 2006.257.11:52:13.94#ibcon#about to write, iclass 19, count 2 2006.257.11:52:13.94#ibcon#wrote, iclass 19, count 2 2006.257.11:52:13.94#ibcon#about to read 3, iclass 19, count 2 2006.257.11:52:13.96#ibcon#read 3, iclass 19, count 2 2006.257.11:52:13.96#ibcon#about to read 4, iclass 19, count 2 2006.257.11:52:13.96#ibcon#read 4, iclass 19, count 2 2006.257.11:52:13.96#ibcon#about to read 5, iclass 19, count 2 2006.257.11:52:13.96#ibcon#read 5, iclass 19, count 2 2006.257.11:52:13.96#ibcon#about to read 6, iclass 19, count 2 2006.257.11:52:13.96#ibcon#read 6, iclass 19, count 2 2006.257.11:52:13.96#ibcon#end of sib2, iclass 19, count 2 2006.257.11:52:13.96#ibcon#*mode == 0, iclass 19, count 2 2006.257.11:52:13.96#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.11:52:13.96#ibcon#[25=AT06-04\r\n] 2006.257.11:52:13.96#ibcon#*before write, iclass 19, count 2 2006.257.11:52:13.96#ibcon#enter sib2, iclass 19, count 2 2006.257.11:52:13.96#ibcon#flushed, iclass 19, count 2 2006.257.11:52:13.96#ibcon#about to write, iclass 19, count 2 2006.257.11:52:13.96#ibcon#wrote, iclass 19, count 2 2006.257.11:52:13.96#ibcon#about to read 3, iclass 19, count 2 2006.257.11:52:13.99#ibcon#read 3, iclass 19, count 2 2006.257.11:52:13.99#ibcon#about to read 4, iclass 19, count 2 2006.257.11:52:13.99#ibcon#read 4, iclass 19, count 2 2006.257.11:52:13.99#ibcon#about to read 5, iclass 19, count 2 2006.257.11:52:13.99#ibcon#read 5, iclass 19, count 2 2006.257.11:52:13.99#ibcon#about to read 6, iclass 19, count 2 2006.257.11:52:13.99#ibcon#read 6, iclass 19, count 2 2006.257.11:52:13.99#ibcon#end of sib2, iclass 19, count 2 2006.257.11:52:13.99#ibcon#*after write, iclass 19, count 2 2006.257.11:52:13.99#ibcon#*before return 0, iclass 19, count 2 2006.257.11:52:13.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:13.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:13.99#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.11:52:13.99#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:13.99#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:14.11#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:14.11#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:14.11#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:52:14.11#ibcon#first serial, iclass 19, count 0 2006.257.11:52:14.11#ibcon#enter sib2, iclass 19, count 0 2006.257.11:52:14.11#ibcon#flushed, iclass 19, count 0 2006.257.11:52:14.11#ibcon#about to write, iclass 19, count 0 2006.257.11:52:14.11#ibcon#wrote, iclass 19, count 0 2006.257.11:52:14.11#ibcon#about to read 3, iclass 19, count 0 2006.257.11:52:14.13#ibcon#read 3, iclass 19, count 0 2006.257.11:52:14.13#ibcon#about to read 4, iclass 19, count 0 2006.257.11:52:14.13#ibcon#read 4, iclass 19, count 0 2006.257.11:52:14.13#ibcon#about to read 5, iclass 19, count 0 2006.257.11:52:14.13#ibcon#read 5, iclass 19, count 0 2006.257.11:52:14.13#ibcon#about to read 6, iclass 19, count 0 2006.257.11:52:14.13#ibcon#read 6, iclass 19, count 0 2006.257.11:52:14.13#ibcon#end of sib2, iclass 19, count 0 2006.257.11:52:14.13#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:52:14.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:52:14.13#ibcon#[25=USB\r\n] 2006.257.11:52:14.13#ibcon#*before write, iclass 19, count 0 2006.257.11:52:14.13#ibcon#enter sib2, iclass 19, count 0 2006.257.11:52:14.13#ibcon#flushed, iclass 19, count 0 2006.257.11:52:14.13#ibcon#about to write, iclass 19, count 0 2006.257.11:52:14.13#ibcon#wrote, iclass 19, count 0 2006.257.11:52:14.13#ibcon#about to read 3, iclass 19, count 0 2006.257.11:52:14.16#ibcon#read 3, iclass 19, count 0 2006.257.11:52:14.16#ibcon#about to read 4, iclass 19, count 0 2006.257.11:52:14.16#ibcon#read 4, iclass 19, count 0 2006.257.11:52:14.16#ibcon#about to read 5, iclass 19, count 0 2006.257.11:52:14.16#ibcon#read 5, iclass 19, count 0 2006.257.11:52:14.16#ibcon#about to read 6, iclass 19, count 0 2006.257.11:52:14.16#ibcon#read 6, iclass 19, count 0 2006.257.11:52:14.16#ibcon#end of sib2, iclass 19, count 0 2006.257.11:52:14.16#ibcon#*after write, iclass 19, count 0 2006.257.11:52:14.16#ibcon#*before return 0, iclass 19, count 0 2006.257.11:52:14.16#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:14.16#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:14.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:52:14.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:52:14.16$vck44/valo=7,864.99 2006.257.11:52:14.16#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.11:52:14.16#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.11:52:14.16#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:14.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:14.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:14.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:14.16#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:52:14.16#ibcon#first serial, iclass 21, count 0 2006.257.11:52:14.16#ibcon#enter sib2, iclass 21, count 0 2006.257.11:52:14.16#ibcon#flushed, iclass 21, count 0 2006.257.11:52:14.16#ibcon#about to write, iclass 21, count 0 2006.257.11:52:14.16#ibcon#wrote, iclass 21, count 0 2006.257.11:52:14.16#ibcon#about to read 3, iclass 21, count 0 2006.257.11:52:14.18#ibcon#read 3, iclass 21, count 0 2006.257.11:52:14.18#ibcon#about to read 4, iclass 21, count 0 2006.257.11:52:14.18#ibcon#read 4, iclass 21, count 0 2006.257.11:52:14.18#ibcon#about to read 5, iclass 21, count 0 2006.257.11:52:14.18#ibcon#read 5, iclass 21, count 0 2006.257.11:52:14.18#ibcon#about to read 6, iclass 21, count 0 2006.257.11:52:14.18#ibcon#read 6, iclass 21, count 0 2006.257.11:52:14.18#ibcon#end of sib2, iclass 21, count 0 2006.257.11:52:14.18#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:52:14.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:52:14.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:52:14.18#ibcon#*before write, iclass 21, count 0 2006.257.11:52:14.18#ibcon#enter sib2, iclass 21, count 0 2006.257.11:52:14.18#ibcon#flushed, iclass 21, count 0 2006.257.11:52:14.18#ibcon#about to write, iclass 21, count 0 2006.257.11:52:14.18#ibcon#wrote, iclass 21, count 0 2006.257.11:52:14.18#ibcon#about to read 3, iclass 21, count 0 2006.257.11:52:14.22#ibcon#read 3, iclass 21, count 0 2006.257.11:52:14.22#ibcon#about to read 4, iclass 21, count 0 2006.257.11:52:14.22#ibcon#read 4, iclass 21, count 0 2006.257.11:52:14.22#ibcon#about to read 5, iclass 21, count 0 2006.257.11:52:14.22#ibcon#read 5, iclass 21, count 0 2006.257.11:52:14.22#ibcon#about to read 6, iclass 21, count 0 2006.257.11:52:14.22#ibcon#read 6, iclass 21, count 0 2006.257.11:52:14.22#ibcon#end of sib2, iclass 21, count 0 2006.257.11:52:14.22#ibcon#*after write, iclass 21, count 0 2006.257.11:52:14.22#ibcon#*before return 0, iclass 21, count 0 2006.257.11:52:14.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:14.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:14.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:52:14.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:52:14.22$vck44/va=7,4 2006.257.11:52:14.22#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.11:52:14.22#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.11:52:14.22#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:14.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:14.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:14.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:14.28#ibcon#enter wrdev, iclass 23, count 2 2006.257.11:52:14.28#ibcon#first serial, iclass 23, count 2 2006.257.11:52:14.28#ibcon#enter sib2, iclass 23, count 2 2006.257.11:52:14.28#ibcon#flushed, iclass 23, count 2 2006.257.11:52:14.28#ibcon#about to write, iclass 23, count 2 2006.257.11:52:14.28#ibcon#wrote, iclass 23, count 2 2006.257.11:52:14.28#ibcon#about to read 3, iclass 23, count 2 2006.257.11:52:14.30#ibcon#read 3, iclass 23, count 2 2006.257.11:52:14.30#ibcon#about to read 4, iclass 23, count 2 2006.257.11:52:14.30#ibcon#read 4, iclass 23, count 2 2006.257.11:52:14.30#ibcon#about to read 5, iclass 23, count 2 2006.257.11:52:14.30#ibcon#read 5, iclass 23, count 2 2006.257.11:52:14.30#ibcon#about to read 6, iclass 23, count 2 2006.257.11:52:14.30#ibcon#read 6, iclass 23, count 2 2006.257.11:52:14.30#ibcon#end of sib2, iclass 23, count 2 2006.257.11:52:14.30#ibcon#*mode == 0, iclass 23, count 2 2006.257.11:52:14.30#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.11:52:14.30#ibcon#[25=AT07-04\r\n] 2006.257.11:52:14.30#ibcon#*before write, iclass 23, count 2 2006.257.11:52:14.30#ibcon#enter sib2, iclass 23, count 2 2006.257.11:52:14.30#ibcon#flushed, iclass 23, count 2 2006.257.11:52:14.30#ibcon#about to write, iclass 23, count 2 2006.257.11:52:14.30#ibcon#wrote, iclass 23, count 2 2006.257.11:52:14.30#ibcon#about to read 3, iclass 23, count 2 2006.257.11:52:14.33#ibcon#read 3, iclass 23, count 2 2006.257.11:52:14.33#ibcon#about to read 4, iclass 23, count 2 2006.257.11:52:14.33#ibcon#read 4, iclass 23, count 2 2006.257.11:52:14.33#ibcon#about to read 5, iclass 23, count 2 2006.257.11:52:14.33#ibcon#read 5, iclass 23, count 2 2006.257.11:52:14.33#ibcon#about to read 6, iclass 23, count 2 2006.257.11:52:14.33#ibcon#read 6, iclass 23, count 2 2006.257.11:52:14.33#ibcon#end of sib2, iclass 23, count 2 2006.257.11:52:14.33#ibcon#*after write, iclass 23, count 2 2006.257.11:52:14.33#ibcon#*before return 0, iclass 23, count 2 2006.257.11:52:14.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:14.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:14.33#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.11:52:14.33#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:14.33#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:14.45#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:14.45#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:14.45#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:52:14.45#ibcon#first serial, iclass 23, count 0 2006.257.11:52:14.45#ibcon#enter sib2, iclass 23, count 0 2006.257.11:52:14.45#ibcon#flushed, iclass 23, count 0 2006.257.11:52:14.45#ibcon#about to write, iclass 23, count 0 2006.257.11:52:14.45#ibcon#wrote, iclass 23, count 0 2006.257.11:52:14.45#ibcon#about to read 3, iclass 23, count 0 2006.257.11:52:14.47#ibcon#read 3, iclass 23, count 0 2006.257.11:52:14.47#ibcon#about to read 4, iclass 23, count 0 2006.257.11:52:14.47#ibcon#read 4, iclass 23, count 0 2006.257.11:52:14.47#ibcon#about to read 5, iclass 23, count 0 2006.257.11:52:14.47#ibcon#read 5, iclass 23, count 0 2006.257.11:52:14.47#ibcon#about to read 6, iclass 23, count 0 2006.257.11:52:14.47#ibcon#read 6, iclass 23, count 0 2006.257.11:52:14.47#ibcon#end of sib2, iclass 23, count 0 2006.257.11:52:14.47#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:52:14.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:52:14.47#ibcon#[25=USB\r\n] 2006.257.11:52:14.47#ibcon#*before write, iclass 23, count 0 2006.257.11:52:14.47#ibcon#enter sib2, iclass 23, count 0 2006.257.11:52:14.47#ibcon#flushed, iclass 23, count 0 2006.257.11:52:14.47#ibcon#about to write, iclass 23, count 0 2006.257.11:52:14.47#ibcon#wrote, iclass 23, count 0 2006.257.11:52:14.47#ibcon#about to read 3, iclass 23, count 0 2006.257.11:52:14.50#ibcon#read 3, iclass 23, count 0 2006.257.11:52:14.50#ibcon#about to read 4, iclass 23, count 0 2006.257.11:52:14.50#ibcon#read 4, iclass 23, count 0 2006.257.11:52:14.50#ibcon#about to read 5, iclass 23, count 0 2006.257.11:52:14.50#ibcon#read 5, iclass 23, count 0 2006.257.11:52:14.50#ibcon#about to read 6, iclass 23, count 0 2006.257.11:52:14.50#ibcon#read 6, iclass 23, count 0 2006.257.11:52:14.50#ibcon#end of sib2, iclass 23, count 0 2006.257.11:52:14.50#ibcon#*after write, iclass 23, count 0 2006.257.11:52:14.50#ibcon#*before return 0, iclass 23, count 0 2006.257.11:52:14.50#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:14.50#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:14.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:52:14.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:52:14.50$vck44/valo=8,884.99 2006.257.11:52:14.50#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.11:52:14.50#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.11:52:14.50#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:14.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:14.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:14.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:14.50#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:52:14.50#ibcon#first serial, iclass 25, count 0 2006.257.11:52:14.50#ibcon#enter sib2, iclass 25, count 0 2006.257.11:52:14.50#ibcon#flushed, iclass 25, count 0 2006.257.11:52:14.50#ibcon#about to write, iclass 25, count 0 2006.257.11:52:14.50#ibcon#wrote, iclass 25, count 0 2006.257.11:52:14.50#ibcon#about to read 3, iclass 25, count 0 2006.257.11:52:14.52#ibcon#read 3, iclass 25, count 0 2006.257.11:52:14.52#ibcon#about to read 4, iclass 25, count 0 2006.257.11:52:14.52#ibcon#read 4, iclass 25, count 0 2006.257.11:52:14.52#ibcon#about to read 5, iclass 25, count 0 2006.257.11:52:14.52#ibcon#read 5, iclass 25, count 0 2006.257.11:52:14.52#ibcon#about to read 6, iclass 25, count 0 2006.257.11:52:14.52#ibcon#read 6, iclass 25, count 0 2006.257.11:52:14.52#ibcon#end of sib2, iclass 25, count 0 2006.257.11:52:14.52#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:52:14.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:52:14.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:52:14.52#ibcon#*before write, iclass 25, count 0 2006.257.11:52:14.52#ibcon#enter sib2, iclass 25, count 0 2006.257.11:52:14.52#ibcon#flushed, iclass 25, count 0 2006.257.11:52:14.52#ibcon#about to write, iclass 25, count 0 2006.257.11:52:14.52#ibcon#wrote, iclass 25, count 0 2006.257.11:52:14.52#ibcon#about to read 3, iclass 25, count 0 2006.257.11:52:14.56#ibcon#read 3, iclass 25, count 0 2006.257.11:52:14.56#ibcon#about to read 4, iclass 25, count 0 2006.257.11:52:14.56#ibcon#read 4, iclass 25, count 0 2006.257.11:52:14.56#ibcon#about to read 5, iclass 25, count 0 2006.257.11:52:14.56#ibcon#read 5, iclass 25, count 0 2006.257.11:52:14.56#ibcon#about to read 6, iclass 25, count 0 2006.257.11:52:14.56#ibcon#read 6, iclass 25, count 0 2006.257.11:52:14.56#ibcon#end of sib2, iclass 25, count 0 2006.257.11:52:14.56#ibcon#*after write, iclass 25, count 0 2006.257.11:52:14.56#ibcon#*before return 0, iclass 25, count 0 2006.257.11:52:14.56#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:14.56#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:14.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:52:14.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:52:14.56$vck44/va=8,4 2006.257.11:52:14.56#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.11:52:14.56#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.11:52:14.56#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:14.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:52:14.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:52:14.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:52:14.62#ibcon#enter wrdev, iclass 27, count 2 2006.257.11:52:14.62#ibcon#first serial, iclass 27, count 2 2006.257.11:52:14.62#ibcon#enter sib2, iclass 27, count 2 2006.257.11:52:14.62#ibcon#flushed, iclass 27, count 2 2006.257.11:52:14.62#ibcon#about to write, iclass 27, count 2 2006.257.11:52:14.62#ibcon#wrote, iclass 27, count 2 2006.257.11:52:14.62#ibcon#about to read 3, iclass 27, count 2 2006.257.11:52:14.64#ibcon#read 3, iclass 27, count 2 2006.257.11:52:14.64#ibcon#about to read 4, iclass 27, count 2 2006.257.11:52:14.64#ibcon#read 4, iclass 27, count 2 2006.257.11:52:14.64#ibcon#about to read 5, iclass 27, count 2 2006.257.11:52:14.64#ibcon#read 5, iclass 27, count 2 2006.257.11:52:14.64#ibcon#about to read 6, iclass 27, count 2 2006.257.11:52:14.64#ibcon#read 6, iclass 27, count 2 2006.257.11:52:14.64#ibcon#end of sib2, iclass 27, count 2 2006.257.11:52:14.64#ibcon#*mode == 0, iclass 27, count 2 2006.257.11:52:14.64#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.11:52:14.64#ibcon#[25=AT08-04\r\n] 2006.257.11:52:14.64#ibcon#*before write, iclass 27, count 2 2006.257.11:52:14.64#ibcon#enter sib2, iclass 27, count 2 2006.257.11:52:14.64#ibcon#flushed, iclass 27, count 2 2006.257.11:52:14.64#ibcon#about to write, iclass 27, count 2 2006.257.11:52:14.64#ibcon#wrote, iclass 27, count 2 2006.257.11:52:14.64#ibcon#about to read 3, iclass 27, count 2 2006.257.11:52:14.67#ibcon#read 3, iclass 27, count 2 2006.257.11:52:14.67#ibcon#about to read 4, iclass 27, count 2 2006.257.11:52:14.67#ibcon#read 4, iclass 27, count 2 2006.257.11:52:14.67#ibcon#about to read 5, iclass 27, count 2 2006.257.11:52:14.67#ibcon#read 5, iclass 27, count 2 2006.257.11:52:14.67#ibcon#about to read 6, iclass 27, count 2 2006.257.11:52:14.67#ibcon#read 6, iclass 27, count 2 2006.257.11:52:14.67#ibcon#end of sib2, iclass 27, count 2 2006.257.11:52:14.67#ibcon#*after write, iclass 27, count 2 2006.257.11:52:14.67#ibcon#*before return 0, iclass 27, count 2 2006.257.11:52:14.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:52:14.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.11:52:14.67#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.11:52:14.67#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:14.67#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:52:14.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:52:14.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:52:14.79#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:52:14.79#ibcon#first serial, iclass 27, count 0 2006.257.11:52:14.79#ibcon#enter sib2, iclass 27, count 0 2006.257.11:52:14.79#ibcon#flushed, iclass 27, count 0 2006.257.11:52:14.79#ibcon#about to write, iclass 27, count 0 2006.257.11:52:14.79#ibcon#wrote, iclass 27, count 0 2006.257.11:52:14.79#ibcon#about to read 3, iclass 27, count 0 2006.257.11:52:14.81#ibcon#read 3, iclass 27, count 0 2006.257.11:52:14.81#ibcon#about to read 4, iclass 27, count 0 2006.257.11:52:14.81#ibcon#read 4, iclass 27, count 0 2006.257.11:52:14.81#ibcon#about to read 5, iclass 27, count 0 2006.257.11:52:14.81#ibcon#read 5, iclass 27, count 0 2006.257.11:52:14.81#ibcon#about to read 6, iclass 27, count 0 2006.257.11:52:14.81#ibcon#read 6, iclass 27, count 0 2006.257.11:52:14.81#ibcon#end of sib2, iclass 27, count 0 2006.257.11:52:14.81#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:52:14.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:52:14.81#ibcon#[25=USB\r\n] 2006.257.11:52:14.81#ibcon#*before write, iclass 27, count 0 2006.257.11:52:14.81#ibcon#enter sib2, iclass 27, count 0 2006.257.11:52:14.81#ibcon#flushed, iclass 27, count 0 2006.257.11:52:14.81#ibcon#about to write, iclass 27, count 0 2006.257.11:52:14.81#ibcon#wrote, iclass 27, count 0 2006.257.11:52:14.81#ibcon#about to read 3, iclass 27, count 0 2006.257.11:52:14.84#ibcon#read 3, iclass 27, count 0 2006.257.11:52:14.84#ibcon#about to read 4, iclass 27, count 0 2006.257.11:52:14.84#ibcon#read 4, iclass 27, count 0 2006.257.11:52:14.84#ibcon#about to read 5, iclass 27, count 0 2006.257.11:52:14.84#ibcon#read 5, iclass 27, count 0 2006.257.11:52:14.84#ibcon#about to read 6, iclass 27, count 0 2006.257.11:52:14.84#ibcon#read 6, iclass 27, count 0 2006.257.11:52:14.84#ibcon#end of sib2, iclass 27, count 0 2006.257.11:52:14.84#ibcon#*after write, iclass 27, count 0 2006.257.11:52:14.84#ibcon#*before return 0, iclass 27, count 0 2006.257.11:52:14.84#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:52:14.84#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.11:52:14.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:52:14.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:52:14.84$vck44/vblo=1,629.99 2006.257.11:52:14.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.11:52:14.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.11:52:14.84#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:14.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:14.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:14.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:14.84#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:52:14.84#ibcon#first serial, iclass 29, count 0 2006.257.11:52:14.84#ibcon#enter sib2, iclass 29, count 0 2006.257.11:52:14.84#ibcon#flushed, iclass 29, count 0 2006.257.11:52:14.84#ibcon#about to write, iclass 29, count 0 2006.257.11:52:14.84#ibcon#wrote, iclass 29, count 0 2006.257.11:52:14.84#ibcon#about to read 3, iclass 29, count 0 2006.257.11:52:14.86#ibcon#read 3, iclass 29, count 0 2006.257.11:52:14.86#ibcon#about to read 4, iclass 29, count 0 2006.257.11:52:14.86#ibcon#read 4, iclass 29, count 0 2006.257.11:52:14.86#ibcon#about to read 5, iclass 29, count 0 2006.257.11:52:14.86#ibcon#read 5, iclass 29, count 0 2006.257.11:52:14.86#ibcon#about to read 6, iclass 29, count 0 2006.257.11:52:14.86#ibcon#read 6, iclass 29, count 0 2006.257.11:52:14.86#ibcon#end of sib2, iclass 29, count 0 2006.257.11:52:14.86#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:52:14.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:52:14.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:52:14.86#ibcon#*before write, iclass 29, count 0 2006.257.11:52:14.86#ibcon#enter sib2, iclass 29, count 0 2006.257.11:52:14.86#ibcon#flushed, iclass 29, count 0 2006.257.11:52:14.86#ibcon#about to write, iclass 29, count 0 2006.257.11:52:14.86#ibcon#wrote, iclass 29, count 0 2006.257.11:52:14.86#ibcon#about to read 3, iclass 29, count 0 2006.257.11:52:14.90#ibcon#read 3, iclass 29, count 0 2006.257.11:52:14.90#ibcon#about to read 4, iclass 29, count 0 2006.257.11:52:14.90#ibcon#read 4, iclass 29, count 0 2006.257.11:52:14.90#ibcon#about to read 5, iclass 29, count 0 2006.257.11:52:14.90#ibcon#read 5, iclass 29, count 0 2006.257.11:52:14.90#ibcon#about to read 6, iclass 29, count 0 2006.257.11:52:14.90#ibcon#read 6, iclass 29, count 0 2006.257.11:52:14.90#ibcon#end of sib2, iclass 29, count 0 2006.257.11:52:14.90#ibcon#*after write, iclass 29, count 0 2006.257.11:52:14.90#ibcon#*before return 0, iclass 29, count 0 2006.257.11:52:14.90#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:14.90#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.11:52:14.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:52:14.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:52:14.90$vck44/vb=1,4 2006.257.11:52:14.90#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.11:52:14.90#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.11:52:14.90#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:14.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:14.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:14.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:14.90#ibcon#enter wrdev, iclass 31, count 2 2006.257.11:52:14.90#ibcon#first serial, iclass 31, count 2 2006.257.11:52:14.90#ibcon#enter sib2, iclass 31, count 2 2006.257.11:52:14.90#ibcon#flushed, iclass 31, count 2 2006.257.11:52:14.90#ibcon#about to write, iclass 31, count 2 2006.257.11:52:14.90#ibcon#wrote, iclass 31, count 2 2006.257.11:52:14.90#ibcon#about to read 3, iclass 31, count 2 2006.257.11:52:14.92#ibcon#read 3, iclass 31, count 2 2006.257.11:52:14.92#ibcon#about to read 4, iclass 31, count 2 2006.257.11:52:14.92#ibcon#read 4, iclass 31, count 2 2006.257.11:52:14.92#ibcon#about to read 5, iclass 31, count 2 2006.257.11:52:14.92#ibcon#read 5, iclass 31, count 2 2006.257.11:52:14.92#ibcon#about to read 6, iclass 31, count 2 2006.257.11:52:14.92#ibcon#read 6, iclass 31, count 2 2006.257.11:52:14.92#ibcon#end of sib2, iclass 31, count 2 2006.257.11:52:14.92#ibcon#*mode == 0, iclass 31, count 2 2006.257.11:52:14.92#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.11:52:14.92#ibcon#[27=AT01-04\r\n] 2006.257.11:52:14.92#ibcon#*before write, iclass 31, count 2 2006.257.11:52:14.92#ibcon#enter sib2, iclass 31, count 2 2006.257.11:52:14.92#ibcon#flushed, iclass 31, count 2 2006.257.11:52:14.92#ibcon#about to write, iclass 31, count 2 2006.257.11:52:14.92#ibcon#wrote, iclass 31, count 2 2006.257.11:52:14.92#ibcon#about to read 3, iclass 31, count 2 2006.257.11:52:14.95#ibcon#read 3, iclass 31, count 2 2006.257.11:52:14.95#ibcon#about to read 4, iclass 31, count 2 2006.257.11:52:14.95#ibcon#read 4, iclass 31, count 2 2006.257.11:52:14.95#ibcon#about to read 5, iclass 31, count 2 2006.257.11:52:14.95#ibcon#read 5, iclass 31, count 2 2006.257.11:52:14.95#ibcon#about to read 6, iclass 31, count 2 2006.257.11:52:14.95#ibcon#read 6, iclass 31, count 2 2006.257.11:52:14.95#ibcon#end of sib2, iclass 31, count 2 2006.257.11:52:14.95#ibcon#*after write, iclass 31, count 2 2006.257.11:52:14.95#ibcon#*before return 0, iclass 31, count 2 2006.257.11:52:14.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:14.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.11:52:14.95#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.11:52:14.95#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:14.95#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:15.07#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:15.07#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:15.07#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:52:15.07#ibcon#first serial, iclass 31, count 0 2006.257.11:52:15.07#ibcon#enter sib2, iclass 31, count 0 2006.257.11:52:15.07#ibcon#flushed, iclass 31, count 0 2006.257.11:52:15.07#ibcon#about to write, iclass 31, count 0 2006.257.11:52:15.07#ibcon#wrote, iclass 31, count 0 2006.257.11:52:15.07#ibcon#about to read 3, iclass 31, count 0 2006.257.11:52:15.09#ibcon#read 3, iclass 31, count 0 2006.257.11:52:15.09#ibcon#about to read 4, iclass 31, count 0 2006.257.11:52:15.09#ibcon#read 4, iclass 31, count 0 2006.257.11:52:15.09#ibcon#about to read 5, iclass 31, count 0 2006.257.11:52:15.09#ibcon#read 5, iclass 31, count 0 2006.257.11:52:15.09#ibcon#about to read 6, iclass 31, count 0 2006.257.11:52:15.09#ibcon#read 6, iclass 31, count 0 2006.257.11:52:15.09#ibcon#end of sib2, iclass 31, count 0 2006.257.11:52:15.09#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:52:15.09#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:52:15.09#ibcon#[27=USB\r\n] 2006.257.11:52:15.09#ibcon#*before write, iclass 31, count 0 2006.257.11:52:15.09#ibcon#enter sib2, iclass 31, count 0 2006.257.11:52:15.09#ibcon#flushed, iclass 31, count 0 2006.257.11:52:15.09#ibcon#about to write, iclass 31, count 0 2006.257.11:52:15.09#ibcon#wrote, iclass 31, count 0 2006.257.11:52:15.09#ibcon#about to read 3, iclass 31, count 0 2006.257.11:52:15.12#ibcon#read 3, iclass 31, count 0 2006.257.11:52:15.12#ibcon#about to read 4, iclass 31, count 0 2006.257.11:52:15.12#ibcon#read 4, iclass 31, count 0 2006.257.11:52:15.12#ibcon#about to read 5, iclass 31, count 0 2006.257.11:52:15.12#ibcon#read 5, iclass 31, count 0 2006.257.11:52:15.12#ibcon#about to read 6, iclass 31, count 0 2006.257.11:52:15.12#ibcon#read 6, iclass 31, count 0 2006.257.11:52:15.12#ibcon#end of sib2, iclass 31, count 0 2006.257.11:52:15.12#ibcon#*after write, iclass 31, count 0 2006.257.11:52:15.12#ibcon#*before return 0, iclass 31, count 0 2006.257.11:52:15.12#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:15.12#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.11:52:15.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:52:15.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:52:15.12$vck44/vblo=2,634.99 2006.257.11:52:15.12#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.11:52:15.12#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.11:52:15.12#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:15.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:15.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:15.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:15.12#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:52:15.12#ibcon#first serial, iclass 33, count 0 2006.257.11:52:15.12#ibcon#enter sib2, iclass 33, count 0 2006.257.11:52:15.12#ibcon#flushed, iclass 33, count 0 2006.257.11:52:15.12#ibcon#about to write, iclass 33, count 0 2006.257.11:52:15.12#ibcon#wrote, iclass 33, count 0 2006.257.11:52:15.12#ibcon#about to read 3, iclass 33, count 0 2006.257.11:52:15.14#ibcon#read 3, iclass 33, count 0 2006.257.11:52:15.14#ibcon#about to read 4, iclass 33, count 0 2006.257.11:52:15.14#ibcon#read 4, iclass 33, count 0 2006.257.11:52:15.14#ibcon#about to read 5, iclass 33, count 0 2006.257.11:52:15.14#ibcon#read 5, iclass 33, count 0 2006.257.11:52:15.14#ibcon#about to read 6, iclass 33, count 0 2006.257.11:52:15.14#ibcon#read 6, iclass 33, count 0 2006.257.11:52:15.14#ibcon#end of sib2, iclass 33, count 0 2006.257.11:52:15.14#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:52:15.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:52:15.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:52:15.14#ibcon#*before write, iclass 33, count 0 2006.257.11:52:15.14#ibcon#enter sib2, iclass 33, count 0 2006.257.11:52:15.14#ibcon#flushed, iclass 33, count 0 2006.257.11:52:15.14#ibcon#about to write, iclass 33, count 0 2006.257.11:52:15.14#ibcon#wrote, iclass 33, count 0 2006.257.11:52:15.14#ibcon#about to read 3, iclass 33, count 0 2006.257.11:52:15.18#ibcon#read 3, iclass 33, count 0 2006.257.11:52:15.18#ibcon#about to read 4, iclass 33, count 0 2006.257.11:52:15.18#ibcon#read 4, iclass 33, count 0 2006.257.11:52:15.18#ibcon#about to read 5, iclass 33, count 0 2006.257.11:52:15.18#ibcon#read 5, iclass 33, count 0 2006.257.11:52:15.18#ibcon#about to read 6, iclass 33, count 0 2006.257.11:52:15.18#ibcon#read 6, iclass 33, count 0 2006.257.11:52:15.18#ibcon#end of sib2, iclass 33, count 0 2006.257.11:52:15.18#ibcon#*after write, iclass 33, count 0 2006.257.11:52:15.18#ibcon#*before return 0, iclass 33, count 0 2006.257.11:52:15.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:15.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.11:52:15.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:52:15.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:52:15.18$vck44/vb=2,5 2006.257.11:52:15.18#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.11:52:15.18#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.11:52:15.18#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:15.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:15.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:15.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:15.24#ibcon#enter wrdev, iclass 35, count 2 2006.257.11:52:15.24#ibcon#first serial, iclass 35, count 2 2006.257.11:52:15.24#ibcon#enter sib2, iclass 35, count 2 2006.257.11:52:15.24#ibcon#flushed, iclass 35, count 2 2006.257.11:52:15.24#ibcon#about to write, iclass 35, count 2 2006.257.11:52:15.24#ibcon#wrote, iclass 35, count 2 2006.257.11:52:15.24#ibcon#about to read 3, iclass 35, count 2 2006.257.11:52:15.26#ibcon#read 3, iclass 35, count 2 2006.257.11:52:15.26#ibcon#about to read 4, iclass 35, count 2 2006.257.11:52:15.26#ibcon#read 4, iclass 35, count 2 2006.257.11:52:15.26#ibcon#about to read 5, iclass 35, count 2 2006.257.11:52:15.26#ibcon#read 5, iclass 35, count 2 2006.257.11:52:15.26#ibcon#about to read 6, iclass 35, count 2 2006.257.11:52:15.26#ibcon#read 6, iclass 35, count 2 2006.257.11:52:15.26#ibcon#end of sib2, iclass 35, count 2 2006.257.11:52:15.26#ibcon#*mode == 0, iclass 35, count 2 2006.257.11:52:15.26#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.11:52:15.26#ibcon#[27=AT02-05\r\n] 2006.257.11:52:15.26#ibcon#*before write, iclass 35, count 2 2006.257.11:52:15.26#ibcon#enter sib2, iclass 35, count 2 2006.257.11:52:15.26#ibcon#flushed, iclass 35, count 2 2006.257.11:52:15.26#ibcon#about to write, iclass 35, count 2 2006.257.11:52:15.26#ibcon#wrote, iclass 35, count 2 2006.257.11:52:15.26#ibcon#about to read 3, iclass 35, count 2 2006.257.11:52:15.29#ibcon#read 3, iclass 35, count 2 2006.257.11:52:15.35#ibcon#about to read 4, iclass 35, count 2 2006.257.11:52:15.35#ibcon#read 4, iclass 35, count 2 2006.257.11:52:15.35#ibcon#about to read 5, iclass 35, count 2 2006.257.11:52:15.35#ibcon#read 5, iclass 35, count 2 2006.257.11:52:15.35#ibcon#about to read 6, iclass 35, count 2 2006.257.11:52:15.35#ibcon#read 6, iclass 35, count 2 2006.257.11:52:15.35#ibcon#end of sib2, iclass 35, count 2 2006.257.11:52:15.35#ibcon#*after write, iclass 35, count 2 2006.257.11:52:15.36#ibcon#*before return 0, iclass 35, count 2 2006.257.11:52:15.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:15.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.11:52:15.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.11:52:15.36#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:15.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:15.47#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:15.47#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:15.47#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:52:15.47#ibcon#first serial, iclass 35, count 0 2006.257.11:52:15.47#ibcon#enter sib2, iclass 35, count 0 2006.257.11:52:15.47#ibcon#flushed, iclass 35, count 0 2006.257.11:52:15.47#ibcon#about to write, iclass 35, count 0 2006.257.11:52:15.47#ibcon#wrote, iclass 35, count 0 2006.257.11:52:15.47#ibcon#about to read 3, iclass 35, count 0 2006.257.11:52:15.49#ibcon#read 3, iclass 35, count 0 2006.257.11:52:15.49#ibcon#about to read 4, iclass 35, count 0 2006.257.11:52:15.49#ibcon#read 4, iclass 35, count 0 2006.257.11:52:15.49#ibcon#about to read 5, iclass 35, count 0 2006.257.11:52:15.49#ibcon#read 5, iclass 35, count 0 2006.257.11:52:15.49#ibcon#about to read 6, iclass 35, count 0 2006.257.11:52:15.49#ibcon#read 6, iclass 35, count 0 2006.257.11:52:15.49#ibcon#end of sib2, iclass 35, count 0 2006.257.11:52:15.49#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:52:15.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:52:15.49#ibcon#[27=USB\r\n] 2006.257.11:52:15.49#ibcon#*before write, iclass 35, count 0 2006.257.11:52:15.49#ibcon#enter sib2, iclass 35, count 0 2006.257.11:52:15.49#ibcon#flushed, iclass 35, count 0 2006.257.11:52:15.49#ibcon#about to write, iclass 35, count 0 2006.257.11:52:15.49#ibcon#wrote, iclass 35, count 0 2006.257.11:52:15.49#ibcon#about to read 3, iclass 35, count 0 2006.257.11:52:15.52#ibcon#read 3, iclass 35, count 0 2006.257.11:52:15.52#ibcon#about to read 4, iclass 35, count 0 2006.257.11:52:15.52#ibcon#read 4, iclass 35, count 0 2006.257.11:52:15.52#ibcon#about to read 5, iclass 35, count 0 2006.257.11:52:15.52#ibcon#read 5, iclass 35, count 0 2006.257.11:52:15.52#ibcon#about to read 6, iclass 35, count 0 2006.257.11:52:15.52#ibcon#read 6, iclass 35, count 0 2006.257.11:52:15.52#ibcon#end of sib2, iclass 35, count 0 2006.257.11:52:15.52#ibcon#*after write, iclass 35, count 0 2006.257.11:52:15.52#ibcon#*before return 0, iclass 35, count 0 2006.257.11:52:15.52#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:15.52#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.11:52:15.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:52:15.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:52:15.52$vck44/vblo=3,649.99 2006.257.11:52:15.52#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.11:52:15.52#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.11:52:15.52#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:15.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:15.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:15.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:15.52#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:52:15.52#ibcon#first serial, iclass 37, count 0 2006.257.11:52:15.52#ibcon#enter sib2, iclass 37, count 0 2006.257.11:52:15.52#ibcon#flushed, iclass 37, count 0 2006.257.11:52:15.52#ibcon#about to write, iclass 37, count 0 2006.257.11:52:15.52#ibcon#wrote, iclass 37, count 0 2006.257.11:52:15.52#ibcon#about to read 3, iclass 37, count 0 2006.257.11:52:15.54#ibcon#read 3, iclass 37, count 0 2006.257.11:52:15.54#ibcon#about to read 4, iclass 37, count 0 2006.257.11:52:15.54#ibcon#read 4, iclass 37, count 0 2006.257.11:52:15.54#ibcon#about to read 5, iclass 37, count 0 2006.257.11:52:15.54#ibcon#read 5, iclass 37, count 0 2006.257.11:52:15.54#ibcon#about to read 6, iclass 37, count 0 2006.257.11:52:15.54#ibcon#read 6, iclass 37, count 0 2006.257.11:52:15.54#ibcon#end of sib2, iclass 37, count 0 2006.257.11:52:15.54#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:52:15.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:52:15.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:52:15.54#ibcon#*before write, iclass 37, count 0 2006.257.11:52:15.54#ibcon#enter sib2, iclass 37, count 0 2006.257.11:52:15.54#ibcon#flushed, iclass 37, count 0 2006.257.11:52:15.54#ibcon#about to write, iclass 37, count 0 2006.257.11:52:15.54#ibcon#wrote, iclass 37, count 0 2006.257.11:52:15.54#ibcon#about to read 3, iclass 37, count 0 2006.257.11:52:15.58#ibcon#read 3, iclass 37, count 0 2006.257.11:52:15.58#ibcon#about to read 4, iclass 37, count 0 2006.257.11:52:15.58#ibcon#read 4, iclass 37, count 0 2006.257.11:52:15.58#ibcon#about to read 5, iclass 37, count 0 2006.257.11:52:15.58#ibcon#read 5, iclass 37, count 0 2006.257.11:52:15.58#ibcon#about to read 6, iclass 37, count 0 2006.257.11:52:15.58#ibcon#read 6, iclass 37, count 0 2006.257.11:52:15.58#ibcon#end of sib2, iclass 37, count 0 2006.257.11:52:15.58#ibcon#*after write, iclass 37, count 0 2006.257.11:52:15.58#ibcon#*before return 0, iclass 37, count 0 2006.257.11:52:15.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:15.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.11:52:15.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:52:15.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:52:15.58$vck44/vb=3,4 2006.257.11:52:15.58#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.11:52:15.58#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.11:52:15.58#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:15.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:15.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:15.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:15.64#ibcon#enter wrdev, iclass 39, count 2 2006.257.11:52:15.64#ibcon#first serial, iclass 39, count 2 2006.257.11:52:15.64#ibcon#enter sib2, iclass 39, count 2 2006.257.11:52:15.64#ibcon#flushed, iclass 39, count 2 2006.257.11:52:15.64#ibcon#about to write, iclass 39, count 2 2006.257.11:52:15.64#ibcon#wrote, iclass 39, count 2 2006.257.11:52:15.64#ibcon#about to read 3, iclass 39, count 2 2006.257.11:52:15.66#ibcon#read 3, iclass 39, count 2 2006.257.11:52:15.66#ibcon#about to read 4, iclass 39, count 2 2006.257.11:52:15.66#ibcon#read 4, iclass 39, count 2 2006.257.11:52:15.66#ibcon#about to read 5, iclass 39, count 2 2006.257.11:52:15.66#ibcon#read 5, iclass 39, count 2 2006.257.11:52:15.66#ibcon#about to read 6, iclass 39, count 2 2006.257.11:52:15.66#ibcon#read 6, iclass 39, count 2 2006.257.11:52:15.66#ibcon#end of sib2, iclass 39, count 2 2006.257.11:52:15.66#ibcon#*mode == 0, iclass 39, count 2 2006.257.11:52:15.66#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.11:52:15.66#ibcon#[27=AT03-04\r\n] 2006.257.11:52:15.66#ibcon#*before write, iclass 39, count 2 2006.257.11:52:15.66#ibcon#enter sib2, iclass 39, count 2 2006.257.11:52:15.66#ibcon#flushed, iclass 39, count 2 2006.257.11:52:15.66#ibcon#about to write, iclass 39, count 2 2006.257.11:52:15.66#ibcon#wrote, iclass 39, count 2 2006.257.11:52:15.66#ibcon#about to read 3, iclass 39, count 2 2006.257.11:52:15.69#ibcon#read 3, iclass 39, count 2 2006.257.11:52:15.69#ibcon#about to read 4, iclass 39, count 2 2006.257.11:52:15.69#ibcon#read 4, iclass 39, count 2 2006.257.11:52:15.69#ibcon#about to read 5, iclass 39, count 2 2006.257.11:52:15.69#ibcon#read 5, iclass 39, count 2 2006.257.11:52:15.69#ibcon#about to read 6, iclass 39, count 2 2006.257.11:52:15.69#ibcon#read 6, iclass 39, count 2 2006.257.11:52:15.69#ibcon#end of sib2, iclass 39, count 2 2006.257.11:52:15.69#ibcon#*after write, iclass 39, count 2 2006.257.11:52:15.69#ibcon#*before return 0, iclass 39, count 2 2006.257.11:52:15.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:15.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.11:52:15.69#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.11:52:15.69#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:15.69#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:15.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:15.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:15.81#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:52:15.81#ibcon#first serial, iclass 39, count 0 2006.257.11:52:15.81#ibcon#enter sib2, iclass 39, count 0 2006.257.11:52:15.81#ibcon#flushed, iclass 39, count 0 2006.257.11:52:15.81#ibcon#about to write, iclass 39, count 0 2006.257.11:52:15.81#ibcon#wrote, iclass 39, count 0 2006.257.11:52:15.81#ibcon#about to read 3, iclass 39, count 0 2006.257.11:52:15.83#ibcon#read 3, iclass 39, count 0 2006.257.11:52:15.83#ibcon#about to read 4, iclass 39, count 0 2006.257.11:52:15.83#ibcon#read 4, iclass 39, count 0 2006.257.11:52:15.83#ibcon#about to read 5, iclass 39, count 0 2006.257.11:52:15.83#ibcon#read 5, iclass 39, count 0 2006.257.11:52:15.83#ibcon#about to read 6, iclass 39, count 0 2006.257.11:52:15.83#ibcon#read 6, iclass 39, count 0 2006.257.11:52:15.83#ibcon#end of sib2, iclass 39, count 0 2006.257.11:52:15.83#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:52:15.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:52:15.83#ibcon#[27=USB\r\n] 2006.257.11:52:15.83#ibcon#*before write, iclass 39, count 0 2006.257.11:52:15.83#ibcon#enter sib2, iclass 39, count 0 2006.257.11:52:15.83#ibcon#flushed, iclass 39, count 0 2006.257.11:52:15.83#ibcon#about to write, iclass 39, count 0 2006.257.11:52:15.83#ibcon#wrote, iclass 39, count 0 2006.257.11:52:15.83#ibcon#about to read 3, iclass 39, count 0 2006.257.11:52:15.86#ibcon#read 3, iclass 39, count 0 2006.257.11:52:15.86#ibcon#about to read 4, iclass 39, count 0 2006.257.11:52:15.86#ibcon#read 4, iclass 39, count 0 2006.257.11:52:15.86#ibcon#about to read 5, iclass 39, count 0 2006.257.11:52:15.86#ibcon#read 5, iclass 39, count 0 2006.257.11:52:15.86#ibcon#about to read 6, iclass 39, count 0 2006.257.11:52:15.86#ibcon#read 6, iclass 39, count 0 2006.257.11:52:15.86#ibcon#end of sib2, iclass 39, count 0 2006.257.11:52:15.86#ibcon#*after write, iclass 39, count 0 2006.257.11:52:15.86#ibcon#*before return 0, iclass 39, count 0 2006.257.11:52:15.86#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:15.86#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.11:52:15.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:52:15.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:52:15.86$vck44/vblo=4,679.99 2006.257.11:52:15.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.11:52:15.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.11:52:15.86#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:15.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:15.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:15.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:15.86#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:52:15.86#ibcon#first serial, iclass 3, count 0 2006.257.11:52:15.86#ibcon#enter sib2, iclass 3, count 0 2006.257.11:52:15.86#ibcon#flushed, iclass 3, count 0 2006.257.11:52:15.86#ibcon#about to write, iclass 3, count 0 2006.257.11:52:15.86#ibcon#wrote, iclass 3, count 0 2006.257.11:52:15.86#ibcon#about to read 3, iclass 3, count 0 2006.257.11:52:15.88#ibcon#read 3, iclass 3, count 0 2006.257.11:52:15.88#ibcon#about to read 4, iclass 3, count 0 2006.257.11:52:15.88#ibcon#read 4, iclass 3, count 0 2006.257.11:52:15.88#ibcon#about to read 5, iclass 3, count 0 2006.257.11:52:15.88#ibcon#read 5, iclass 3, count 0 2006.257.11:52:15.88#ibcon#about to read 6, iclass 3, count 0 2006.257.11:52:15.88#ibcon#read 6, iclass 3, count 0 2006.257.11:52:15.88#ibcon#end of sib2, iclass 3, count 0 2006.257.11:52:15.88#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:52:15.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:52:15.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:52:15.88#ibcon#*before write, iclass 3, count 0 2006.257.11:52:15.88#ibcon#enter sib2, iclass 3, count 0 2006.257.11:52:15.88#ibcon#flushed, iclass 3, count 0 2006.257.11:52:15.88#ibcon#about to write, iclass 3, count 0 2006.257.11:52:15.88#ibcon#wrote, iclass 3, count 0 2006.257.11:52:15.88#ibcon#about to read 3, iclass 3, count 0 2006.257.11:52:15.92#ibcon#read 3, iclass 3, count 0 2006.257.11:52:15.92#ibcon#about to read 4, iclass 3, count 0 2006.257.11:52:15.92#ibcon#read 4, iclass 3, count 0 2006.257.11:52:15.92#ibcon#about to read 5, iclass 3, count 0 2006.257.11:52:15.92#ibcon#read 5, iclass 3, count 0 2006.257.11:52:15.92#ibcon#about to read 6, iclass 3, count 0 2006.257.11:52:15.92#ibcon#read 6, iclass 3, count 0 2006.257.11:52:15.92#ibcon#end of sib2, iclass 3, count 0 2006.257.11:52:15.92#ibcon#*after write, iclass 3, count 0 2006.257.11:52:15.92#ibcon#*before return 0, iclass 3, count 0 2006.257.11:52:15.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:15.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:52:15.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:52:15.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:52:15.92$vck44/vb=4,5 2006.257.11:52:15.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.11:52:15.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.11:52:15.92#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:15.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:15.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:15.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:15.98#ibcon#enter wrdev, iclass 5, count 2 2006.257.11:52:15.98#ibcon#first serial, iclass 5, count 2 2006.257.11:52:15.98#ibcon#enter sib2, iclass 5, count 2 2006.257.11:52:15.98#ibcon#flushed, iclass 5, count 2 2006.257.11:52:15.98#ibcon#about to write, iclass 5, count 2 2006.257.11:52:15.98#ibcon#wrote, iclass 5, count 2 2006.257.11:52:15.98#ibcon#about to read 3, iclass 5, count 2 2006.257.11:52:16.00#ibcon#read 3, iclass 5, count 2 2006.257.11:52:16.00#ibcon#about to read 4, iclass 5, count 2 2006.257.11:52:16.00#ibcon#read 4, iclass 5, count 2 2006.257.11:52:16.00#ibcon#about to read 5, iclass 5, count 2 2006.257.11:52:16.00#ibcon#read 5, iclass 5, count 2 2006.257.11:52:16.00#ibcon#about to read 6, iclass 5, count 2 2006.257.11:52:16.00#ibcon#read 6, iclass 5, count 2 2006.257.11:52:16.00#ibcon#end of sib2, iclass 5, count 2 2006.257.11:52:16.00#ibcon#*mode == 0, iclass 5, count 2 2006.257.11:52:16.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.11:52:16.00#ibcon#[27=AT04-05\r\n] 2006.257.11:52:16.00#ibcon#*before write, iclass 5, count 2 2006.257.11:52:16.00#ibcon#enter sib2, iclass 5, count 2 2006.257.11:52:16.00#ibcon#flushed, iclass 5, count 2 2006.257.11:52:16.00#ibcon#about to write, iclass 5, count 2 2006.257.11:52:16.00#ibcon#wrote, iclass 5, count 2 2006.257.11:52:16.00#ibcon#about to read 3, iclass 5, count 2 2006.257.11:52:16.03#ibcon#read 3, iclass 5, count 2 2006.257.11:52:16.03#ibcon#about to read 4, iclass 5, count 2 2006.257.11:52:16.03#ibcon#read 4, iclass 5, count 2 2006.257.11:52:16.03#ibcon#about to read 5, iclass 5, count 2 2006.257.11:52:16.03#ibcon#read 5, iclass 5, count 2 2006.257.11:52:16.03#ibcon#about to read 6, iclass 5, count 2 2006.257.11:52:16.03#ibcon#read 6, iclass 5, count 2 2006.257.11:52:16.03#ibcon#end of sib2, iclass 5, count 2 2006.257.11:52:16.03#ibcon#*after write, iclass 5, count 2 2006.257.11:52:16.03#ibcon#*before return 0, iclass 5, count 2 2006.257.11:52:16.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:16.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.11:52:16.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.11:52:16.03#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:16.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:16.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:16.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:16.15#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:52:16.15#ibcon#first serial, iclass 5, count 0 2006.257.11:52:16.15#ibcon#enter sib2, iclass 5, count 0 2006.257.11:52:16.15#ibcon#flushed, iclass 5, count 0 2006.257.11:52:16.15#ibcon#about to write, iclass 5, count 0 2006.257.11:52:16.15#ibcon#wrote, iclass 5, count 0 2006.257.11:52:16.15#ibcon#about to read 3, iclass 5, count 0 2006.257.11:52:16.17#ibcon#read 3, iclass 5, count 0 2006.257.11:52:16.17#ibcon#about to read 4, iclass 5, count 0 2006.257.11:52:16.17#ibcon#read 4, iclass 5, count 0 2006.257.11:52:16.17#ibcon#about to read 5, iclass 5, count 0 2006.257.11:52:16.17#ibcon#read 5, iclass 5, count 0 2006.257.11:52:16.17#ibcon#about to read 6, iclass 5, count 0 2006.257.11:52:16.17#ibcon#read 6, iclass 5, count 0 2006.257.11:52:16.17#ibcon#end of sib2, iclass 5, count 0 2006.257.11:52:16.17#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:52:16.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:52:16.17#ibcon#[27=USB\r\n] 2006.257.11:52:16.17#ibcon#*before write, iclass 5, count 0 2006.257.11:52:16.17#ibcon#enter sib2, iclass 5, count 0 2006.257.11:52:16.17#ibcon#flushed, iclass 5, count 0 2006.257.11:52:16.17#ibcon#about to write, iclass 5, count 0 2006.257.11:52:16.17#ibcon#wrote, iclass 5, count 0 2006.257.11:52:16.17#ibcon#about to read 3, iclass 5, count 0 2006.257.11:52:16.20#ibcon#read 3, iclass 5, count 0 2006.257.11:52:16.20#ibcon#about to read 4, iclass 5, count 0 2006.257.11:52:16.20#ibcon#read 4, iclass 5, count 0 2006.257.11:52:16.20#ibcon#about to read 5, iclass 5, count 0 2006.257.11:52:16.20#ibcon#read 5, iclass 5, count 0 2006.257.11:52:16.20#ibcon#about to read 6, iclass 5, count 0 2006.257.11:52:16.20#ibcon#read 6, iclass 5, count 0 2006.257.11:52:16.20#ibcon#end of sib2, iclass 5, count 0 2006.257.11:52:16.20#ibcon#*after write, iclass 5, count 0 2006.257.11:52:16.20#ibcon#*before return 0, iclass 5, count 0 2006.257.11:52:16.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:16.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.11:52:16.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:52:16.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:52:16.20$vck44/vblo=5,709.99 2006.257.11:52:16.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.11:52:16.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.11:52:16.20#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:16.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:16.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:16.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:16.20#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:52:16.20#ibcon#first serial, iclass 7, count 0 2006.257.11:52:16.20#ibcon#enter sib2, iclass 7, count 0 2006.257.11:52:16.20#ibcon#flushed, iclass 7, count 0 2006.257.11:52:16.20#ibcon#about to write, iclass 7, count 0 2006.257.11:52:16.20#ibcon#wrote, iclass 7, count 0 2006.257.11:52:16.20#ibcon#about to read 3, iclass 7, count 0 2006.257.11:52:16.22#ibcon#read 3, iclass 7, count 0 2006.257.11:52:16.22#ibcon#about to read 4, iclass 7, count 0 2006.257.11:52:16.22#ibcon#read 4, iclass 7, count 0 2006.257.11:52:16.22#ibcon#about to read 5, iclass 7, count 0 2006.257.11:52:16.22#ibcon#read 5, iclass 7, count 0 2006.257.11:52:16.22#ibcon#about to read 6, iclass 7, count 0 2006.257.11:52:16.22#ibcon#read 6, iclass 7, count 0 2006.257.11:52:16.22#ibcon#end of sib2, iclass 7, count 0 2006.257.11:52:16.22#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:52:16.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:52:16.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:52:16.22#ibcon#*before write, iclass 7, count 0 2006.257.11:52:16.22#ibcon#enter sib2, iclass 7, count 0 2006.257.11:52:16.22#ibcon#flushed, iclass 7, count 0 2006.257.11:52:16.22#ibcon#about to write, iclass 7, count 0 2006.257.11:52:16.22#ibcon#wrote, iclass 7, count 0 2006.257.11:52:16.22#ibcon#about to read 3, iclass 7, count 0 2006.257.11:52:16.26#ibcon#read 3, iclass 7, count 0 2006.257.11:52:16.26#ibcon#about to read 4, iclass 7, count 0 2006.257.11:52:16.26#ibcon#read 4, iclass 7, count 0 2006.257.11:52:16.26#ibcon#about to read 5, iclass 7, count 0 2006.257.11:52:16.26#ibcon#read 5, iclass 7, count 0 2006.257.11:52:16.26#ibcon#about to read 6, iclass 7, count 0 2006.257.11:52:16.26#ibcon#read 6, iclass 7, count 0 2006.257.11:52:16.26#ibcon#end of sib2, iclass 7, count 0 2006.257.11:52:16.26#ibcon#*after write, iclass 7, count 0 2006.257.11:52:16.26#ibcon#*before return 0, iclass 7, count 0 2006.257.11:52:16.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:16.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.11:52:16.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:52:16.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:52:16.26$vck44/vb=5,4 2006.257.11:52:16.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.11:52:16.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.11:52:16.26#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:16.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:16.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:16.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:16.32#ibcon#enter wrdev, iclass 11, count 2 2006.257.11:52:16.32#ibcon#first serial, iclass 11, count 2 2006.257.11:52:16.32#ibcon#enter sib2, iclass 11, count 2 2006.257.11:52:16.32#ibcon#flushed, iclass 11, count 2 2006.257.11:52:16.32#ibcon#about to write, iclass 11, count 2 2006.257.11:52:16.32#ibcon#wrote, iclass 11, count 2 2006.257.11:52:16.32#ibcon#about to read 3, iclass 11, count 2 2006.257.11:52:16.34#ibcon#read 3, iclass 11, count 2 2006.257.11:52:16.34#ibcon#about to read 4, iclass 11, count 2 2006.257.11:52:16.34#ibcon#read 4, iclass 11, count 2 2006.257.11:52:16.34#ibcon#about to read 5, iclass 11, count 2 2006.257.11:52:16.34#ibcon#read 5, iclass 11, count 2 2006.257.11:52:16.34#ibcon#about to read 6, iclass 11, count 2 2006.257.11:52:16.34#ibcon#read 6, iclass 11, count 2 2006.257.11:52:16.34#ibcon#end of sib2, iclass 11, count 2 2006.257.11:52:16.34#ibcon#*mode == 0, iclass 11, count 2 2006.257.11:52:16.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.11:52:16.34#ibcon#[27=AT05-04\r\n] 2006.257.11:52:16.34#ibcon#*before write, iclass 11, count 2 2006.257.11:52:16.34#ibcon#enter sib2, iclass 11, count 2 2006.257.11:52:16.34#ibcon#flushed, iclass 11, count 2 2006.257.11:52:16.34#ibcon#about to write, iclass 11, count 2 2006.257.11:52:16.34#ibcon#wrote, iclass 11, count 2 2006.257.11:52:16.34#ibcon#about to read 3, iclass 11, count 2 2006.257.11:52:16.37#ibcon#read 3, iclass 11, count 2 2006.257.11:52:16.37#ibcon#about to read 4, iclass 11, count 2 2006.257.11:52:16.38#ibcon#read 4, iclass 11, count 2 2006.257.11:52:16.38#ibcon#about to read 5, iclass 11, count 2 2006.257.11:52:16.38#ibcon#read 5, iclass 11, count 2 2006.257.11:52:16.38#ibcon#about to read 6, iclass 11, count 2 2006.257.11:52:16.38#ibcon#read 6, iclass 11, count 2 2006.257.11:52:16.38#ibcon#end of sib2, iclass 11, count 2 2006.257.11:52:16.38#ibcon#*after write, iclass 11, count 2 2006.257.11:52:16.38#ibcon#*before return 0, iclass 11, count 2 2006.257.11:52:16.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:16.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.11:52:16.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.11:52:16.38#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:16.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:16.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:16.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:16.50#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:52:16.50#ibcon#first serial, iclass 11, count 0 2006.257.11:52:16.50#ibcon#enter sib2, iclass 11, count 0 2006.257.11:52:16.50#ibcon#flushed, iclass 11, count 0 2006.257.11:52:16.50#ibcon#about to write, iclass 11, count 0 2006.257.11:52:16.50#ibcon#wrote, iclass 11, count 0 2006.257.11:52:16.50#ibcon#about to read 3, iclass 11, count 0 2006.257.11:52:16.52#ibcon#read 3, iclass 11, count 0 2006.257.11:52:16.52#ibcon#about to read 4, iclass 11, count 0 2006.257.11:52:16.52#ibcon#read 4, iclass 11, count 0 2006.257.11:52:16.52#ibcon#about to read 5, iclass 11, count 0 2006.257.11:52:16.52#ibcon#read 5, iclass 11, count 0 2006.257.11:52:16.52#ibcon#about to read 6, iclass 11, count 0 2006.257.11:52:16.52#ibcon#read 6, iclass 11, count 0 2006.257.11:52:16.52#ibcon#end of sib2, iclass 11, count 0 2006.257.11:52:16.52#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:52:16.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:52:16.52#ibcon#[27=USB\r\n] 2006.257.11:52:16.52#ibcon#*before write, iclass 11, count 0 2006.257.11:52:16.52#ibcon#enter sib2, iclass 11, count 0 2006.257.11:52:16.52#ibcon#flushed, iclass 11, count 0 2006.257.11:52:16.52#ibcon#about to write, iclass 11, count 0 2006.257.11:52:16.52#ibcon#wrote, iclass 11, count 0 2006.257.11:52:16.52#ibcon#about to read 3, iclass 11, count 0 2006.257.11:52:16.55#ibcon#read 3, iclass 11, count 0 2006.257.11:52:16.55#ibcon#about to read 4, iclass 11, count 0 2006.257.11:52:16.55#ibcon#read 4, iclass 11, count 0 2006.257.11:52:16.55#ibcon#about to read 5, iclass 11, count 0 2006.257.11:52:16.55#ibcon#read 5, iclass 11, count 0 2006.257.11:52:16.55#ibcon#about to read 6, iclass 11, count 0 2006.257.11:52:16.55#ibcon#read 6, iclass 11, count 0 2006.257.11:52:16.55#ibcon#end of sib2, iclass 11, count 0 2006.257.11:52:16.55#ibcon#*after write, iclass 11, count 0 2006.257.11:52:16.55#ibcon#*before return 0, iclass 11, count 0 2006.257.11:52:16.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:16.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.11:52:16.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:52:16.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:52:16.55$vck44/vblo=6,719.99 2006.257.11:52:16.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.11:52:16.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.11:52:16.55#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:16.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:52:16.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:52:16.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:52:16.55#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:52:16.55#ibcon#first serial, iclass 13, count 0 2006.257.11:52:16.55#ibcon#enter sib2, iclass 13, count 0 2006.257.11:52:16.55#ibcon#flushed, iclass 13, count 0 2006.257.11:52:16.55#ibcon#about to write, iclass 13, count 0 2006.257.11:52:16.55#ibcon#wrote, iclass 13, count 0 2006.257.11:52:16.55#ibcon#about to read 3, iclass 13, count 0 2006.257.11:52:16.57#ibcon#read 3, iclass 13, count 0 2006.257.11:52:16.57#ibcon#about to read 4, iclass 13, count 0 2006.257.11:52:16.57#ibcon#read 4, iclass 13, count 0 2006.257.11:52:16.57#ibcon#about to read 5, iclass 13, count 0 2006.257.11:52:16.57#ibcon#read 5, iclass 13, count 0 2006.257.11:52:16.57#ibcon#about to read 6, iclass 13, count 0 2006.257.11:52:16.57#ibcon#read 6, iclass 13, count 0 2006.257.11:52:16.57#ibcon#end of sib2, iclass 13, count 0 2006.257.11:52:16.57#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:52:16.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:52:16.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:52:16.57#ibcon#*before write, iclass 13, count 0 2006.257.11:52:16.57#ibcon#enter sib2, iclass 13, count 0 2006.257.11:52:16.57#ibcon#flushed, iclass 13, count 0 2006.257.11:52:16.57#ibcon#about to write, iclass 13, count 0 2006.257.11:52:16.57#ibcon#wrote, iclass 13, count 0 2006.257.11:52:16.57#ibcon#about to read 3, iclass 13, count 0 2006.257.11:52:16.61#ibcon#read 3, iclass 13, count 0 2006.257.11:52:16.61#ibcon#about to read 4, iclass 13, count 0 2006.257.11:52:16.61#ibcon#read 4, iclass 13, count 0 2006.257.11:52:16.61#ibcon#about to read 5, iclass 13, count 0 2006.257.11:52:16.61#ibcon#read 5, iclass 13, count 0 2006.257.11:52:16.61#ibcon#about to read 6, iclass 13, count 0 2006.257.11:52:16.61#ibcon#read 6, iclass 13, count 0 2006.257.11:52:16.61#ibcon#end of sib2, iclass 13, count 0 2006.257.11:52:16.61#ibcon#*after write, iclass 13, count 0 2006.257.11:52:16.61#ibcon#*before return 0, iclass 13, count 0 2006.257.11:52:16.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:52:16.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.11:52:16.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:52:16.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:52:16.61$vck44/vb=6,4 2006.257.11:52:16.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.11:52:16.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.11:52:16.61#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:16.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:52:16.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:52:16.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:52:16.67#ibcon#enter wrdev, iclass 15, count 2 2006.257.11:52:16.67#ibcon#first serial, iclass 15, count 2 2006.257.11:52:16.67#ibcon#enter sib2, iclass 15, count 2 2006.257.11:52:16.67#ibcon#flushed, iclass 15, count 2 2006.257.11:52:16.67#ibcon#about to write, iclass 15, count 2 2006.257.11:52:16.67#ibcon#wrote, iclass 15, count 2 2006.257.11:52:16.67#ibcon#about to read 3, iclass 15, count 2 2006.257.11:52:16.69#ibcon#read 3, iclass 15, count 2 2006.257.11:52:16.69#ibcon#about to read 4, iclass 15, count 2 2006.257.11:52:16.69#ibcon#read 4, iclass 15, count 2 2006.257.11:52:16.69#ibcon#about to read 5, iclass 15, count 2 2006.257.11:52:16.69#ibcon#read 5, iclass 15, count 2 2006.257.11:52:16.69#ibcon#about to read 6, iclass 15, count 2 2006.257.11:52:16.69#ibcon#read 6, iclass 15, count 2 2006.257.11:52:16.69#ibcon#end of sib2, iclass 15, count 2 2006.257.11:52:16.69#ibcon#*mode == 0, iclass 15, count 2 2006.257.11:52:16.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.11:52:16.69#ibcon#[27=AT06-04\r\n] 2006.257.11:52:16.69#ibcon#*before write, iclass 15, count 2 2006.257.11:52:16.69#ibcon#enter sib2, iclass 15, count 2 2006.257.11:52:16.69#ibcon#flushed, iclass 15, count 2 2006.257.11:52:16.69#ibcon#about to write, iclass 15, count 2 2006.257.11:52:16.69#ibcon#wrote, iclass 15, count 2 2006.257.11:52:16.69#ibcon#about to read 3, iclass 15, count 2 2006.257.11:52:16.72#ibcon#read 3, iclass 15, count 2 2006.257.11:52:16.72#ibcon#about to read 4, iclass 15, count 2 2006.257.11:52:16.72#ibcon#read 4, iclass 15, count 2 2006.257.11:52:16.72#ibcon#about to read 5, iclass 15, count 2 2006.257.11:52:16.72#ibcon#read 5, iclass 15, count 2 2006.257.11:52:16.72#ibcon#about to read 6, iclass 15, count 2 2006.257.11:52:16.72#ibcon#read 6, iclass 15, count 2 2006.257.11:52:16.72#ibcon#end of sib2, iclass 15, count 2 2006.257.11:52:16.72#ibcon#*after write, iclass 15, count 2 2006.257.11:52:16.72#ibcon#*before return 0, iclass 15, count 2 2006.257.11:52:16.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:52:16.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.11:52:16.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.11:52:16.72#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:16.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:52:16.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:52:16.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:52:16.84#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:52:16.84#ibcon#first serial, iclass 15, count 0 2006.257.11:52:16.84#ibcon#enter sib2, iclass 15, count 0 2006.257.11:52:16.84#ibcon#flushed, iclass 15, count 0 2006.257.11:52:16.84#ibcon#about to write, iclass 15, count 0 2006.257.11:52:16.84#ibcon#wrote, iclass 15, count 0 2006.257.11:52:16.84#ibcon#about to read 3, iclass 15, count 0 2006.257.11:52:16.86#ibcon#read 3, iclass 15, count 0 2006.257.11:52:16.86#ibcon#about to read 4, iclass 15, count 0 2006.257.11:52:16.86#ibcon#read 4, iclass 15, count 0 2006.257.11:52:16.86#ibcon#about to read 5, iclass 15, count 0 2006.257.11:52:16.86#ibcon#read 5, iclass 15, count 0 2006.257.11:52:16.86#ibcon#about to read 6, iclass 15, count 0 2006.257.11:52:16.86#ibcon#read 6, iclass 15, count 0 2006.257.11:52:16.86#ibcon#end of sib2, iclass 15, count 0 2006.257.11:52:16.86#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:52:16.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:52:16.86#ibcon#[27=USB\r\n] 2006.257.11:52:16.86#ibcon#*before write, iclass 15, count 0 2006.257.11:52:16.86#ibcon#enter sib2, iclass 15, count 0 2006.257.11:52:16.86#ibcon#flushed, iclass 15, count 0 2006.257.11:52:16.86#ibcon#about to write, iclass 15, count 0 2006.257.11:52:16.86#ibcon#wrote, iclass 15, count 0 2006.257.11:52:16.86#ibcon#about to read 3, iclass 15, count 0 2006.257.11:52:16.89#ibcon#read 3, iclass 15, count 0 2006.257.11:52:16.89#ibcon#about to read 4, iclass 15, count 0 2006.257.11:52:16.89#ibcon#read 4, iclass 15, count 0 2006.257.11:52:16.89#ibcon#about to read 5, iclass 15, count 0 2006.257.11:52:16.89#ibcon#read 5, iclass 15, count 0 2006.257.11:52:16.89#ibcon#about to read 6, iclass 15, count 0 2006.257.11:52:16.89#ibcon#read 6, iclass 15, count 0 2006.257.11:52:16.89#ibcon#end of sib2, iclass 15, count 0 2006.257.11:52:16.89#ibcon#*after write, iclass 15, count 0 2006.257.11:52:16.89#ibcon#*before return 0, iclass 15, count 0 2006.257.11:52:16.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:52:16.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.11:52:16.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:52:16.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:52:16.89$vck44/vblo=7,734.99 2006.257.11:52:16.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.11:52:16.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.11:52:16.89#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:16.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:16.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:16.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:16.89#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:52:16.89#ibcon#first serial, iclass 17, count 0 2006.257.11:52:16.89#ibcon#enter sib2, iclass 17, count 0 2006.257.11:52:16.89#ibcon#flushed, iclass 17, count 0 2006.257.11:52:16.89#ibcon#about to write, iclass 17, count 0 2006.257.11:52:16.89#ibcon#wrote, iclass 17, count 0 2006.257.11:52:16.89#ibcon#about to read 3, iclass 17, count 0 2006.257.11:52:16.91#ibcon#read 3, iclass 17, count 0 2006.257.11:52:16.91#ibcon#about to read 4, iclass 17, count 0 2006.257.11:52:16.91#ibcon#read 4, iclass 17, count 0 2006.257.11:52:16.91#ibcon#about to read 5, iclass 17, count 0 2006.257.11:52:16.91#ibcon#read 5, iclass 17, count 0 2006.257.11:52:16.91#ibcon#about to read 6, iclass 17, count 0 2006.257.11:52:16.91#ibcon#read 6, iclass 17, count 0 2006.257.11:52:16.91#ibcon#end of sib2, iclass 17, count 0 2006.257.11:52:16.91#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:52:16.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:52:16.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:52:16.91#ibcon#*before write, iclass 17, count 0 2006.257.11:52:16.91#ibcon#enter sib2, iclass 17, count 0 2006.257.11:52:16.91#ibcon#flushed, iclass 17, count 0 2006.257.11:52:16.91#ibcon#about to write, iclass 17, count 0 2006.257.11:52:16.91#ibcon#wrote, iclass 17, count 0 2006.257.11:52:16.91#ibcon#about to read 3, iclass 17, count 0 2006.257.11:52:16.95#ibcon#read 3, iclass 17, count 0 2006.257.11:52:16.95#ibcon#about to read 4, iclass 17, count 0 2006.257.11:52:16.95#ibcon#read 4, iclass 17, count 0 2006.257.11:52:16.95#ibcon#about to read 5, iclass 17, count 0 2006.257.11:52:16.95#ibcon#read 5, iclass 17, count 0 2006.257.11:52:16.95#ibcon#about to read 6, iclass 17, count 0 2006.257.11:52:16.95#ibcon#read 6, iclass 17, count 0 2006.257.11:52:16.95#ibcon#end of sib2, iclass 17, count 0 2006.257.11:52:16.95#ibcon#*after write, iclass 17, count 0 2006.257.11:52:16.95#ibcon#*before return 0, iclass 17, count 0 2006.257.11:52:16.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:16.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.11:52:16.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:52:16.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:52:16.95$vck44/vb=7,4 2006.257.11:52:16.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.11:52:16.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.11:52:16.95#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:16.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:17.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:17.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:17.01#ibcon#enter wrdev, iclass 19, count 2 2006.257.11:52:17.01#ibcon#first serial, iclass 19, count 2 2006.257.11:52:17.01#ibcon#enter sib2, iclass 19, count 2 2006.257.11:52:17.01#ibcon#flushed, iclass 19, count 2 2006.257.11:52:17.01#ibcon#about to write, iclass 19, count 2 2006.257.11:52:17.01#ibcon#wrote, iclass 19, count 2 2006.257.11:52:17.01#ibcon#about to read 3, iclass 19, count 2 2006.257.11:52:17.03#ibcon#read 3, iclass 19, count 2 2006.257.11:52:17.03#ibcon#about to read 4, iclass 19, count 2 2006.257.11:52:17.03#ibcon#read 4, iclass 19, count 2 2006.257.11:52:17.03#ibcon#about to read 5, iclass 19, count 2 2006.257.11:52:17.03#ibcon#read 5, iclass 19, count 2 2006.257.11:52:17.03#ibcon#about to read 6, iclass 19, count 2 2006.257.11:52:17.03#ibcon#read 6, iclass 19, count 2 2006.257.11:52:17.03#ibcon#end of sib2, iclass 19, count 2 2006.257.11:52:17.03#ibcon#*mode == 0, iclass 19, count 2 2006.257.11:52:17.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.11:52:17.03#ibcon#[27=AT07-04\r\n] 2006.257.11:52:17.03#ibcon#*before write, iclass 19, count 2 2006.257.11:52:17.03#ibcon#enter sib2, iclass 19, count 2 2006.257.11:52:17.03#ibcon#flushed, iclass 19, count 2 2006.257.11:52:17.03#ibcon#about to write, iclass 19, count 2 2006.257.11:52:17.03#ibcon#wrote, iclass 19, count 2 2006.257.11:52:17.03#ibcon#about to read 3, iclass 19, count 2 2006.257.11:52:17.06#ibcon#read 3, iclass 19, count 2 2006.257.11:52:17.06#ibcon#about to read 4, iclass 19, count 2 2006.257.11:52:17.06#ibcon#read 4, iclass 19, count 2 2006.257.11:52:17.06#ibcon#about to read 5, iclass 19, count 2 2006.257.11:52:17.06#ibcon#read 5, iclass 19, count 2 2006.257.11:52:17.06#ibcon#about to read 6, iclass 19, count 2 2006.257.11:52:17.06#ibcon#read 6, iclass 19, count 2 2006.257.11:52:17.06#ibcon#end of sib2, iclass 19, count 2 2006.257.11:52:17.06#ibcon#*after write, iclass 19, count 2 2006.257.11:52:17.06#ibcon#*before return 0, iclass 19, count 2 2006.257.11:52:17.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:17.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.11:52:17.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.11:52:17.06#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:17.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:17.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:17.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:17.18#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:52:17.18#ibcon#first serial, iclass 19, count 0 2006.257.11:52:17.18#ibcon#enter sib2, iclass 19, count 0 2006.257.11:52:17.18#ibcon#flushed, iclass 19, count 0 2006.257.11:52:17.18#ibcon#about to write, iclass 19, count 0 2006.257.11:52:17.18#ibcon#wrote, iclass 19, count 0 2006.257.11:52:17.18#ibcon#about to read 3, iclass 19, count 0 2006.257.11:52:17.20#ibcon#read 3, iclass 19, count 0 2006.257.11:52:17.20#ibcon#about to read 4, iclass 19, count 0 2006.257.11:52:17.20#ibcon#read 4, iclass 19, count 0 2006.257.11:52:17.20#ibcon#about to read 5, iclass 19, count 0 2006.257.11:52:17.20#ibcon#read 5, iclass 19, count 0 2006.257.11:52:17.20#ibcon#about to read 6, iclass 19, count 0 2006.257.11:52:17.20#ibcon#read 6, iclass 19, count 0 2006.257.11:52:17.20#ibcon#end of sib2, iclass 19, count 0 2006.257.11:52:17.20#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:52:17.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:52:17.20#ibcon#[27=USB\r\n] 2006.257.11:52:17.20#ibcon#*before write, iclass 19, count 0 2006.257.11:52:17.20#ibcon#enter sib2, iclass 19, count 0 2006.257.11:52:17.20#ibcon#flushed, iclass 19, count 0 2006.257.11:52:17.20#ibcon#about to write, iclass 19, count 0 2006.257.11:52:17.20#ibcon#wrote, iclass 19, count 0 2006.257.11:52:17.20#ibcon#about to read 3, iclass 19, count 0 2006.257.11:52:17.23#ibcon#read 3, iclass 19, count 0 2006.257.11:52:17.23#ibcon#about to read 4, iclass 19, count 0 2006.257.11:52:17.23#ibcon#read 4, iclass 19, count 0 2006.257.11:52:17.23#ibcon#about to read 5, iclass 19, count 0 2006.257.11:52:17.23#ibcon#read 5, iclass 19, count 0 2006.257.11:52:17.23#ibcon#about to read 6, iclass 19, count 0 2006.257.11:52:17.23#ibcon#read 6, iclass 19, count 0 2006.257.11:52:17.23#ibcon#end of sib2, iclass 19, count 0 2006.257.11:52:17.23#ibcon#*after write, iclass 19, count 0 2006.257.11:52:17.23#ibcon#*before return 0, iclass 19, count 0 2006.257.11:52:17.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:17.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.11:52:17.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:52:17.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:52:17.23$vck44/vblo=8,744.99 2006.257.11:52:17.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.11:52:17.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.11:52:17.23#ibcon#ireg 17 cls_cnt 0 2006.257.11:52:17.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:17.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:17.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:17.23#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:52:17.23#ibcon#first serial, iclass 21, count 0 2006.257.11:52:17.23#ibcon#enter sib2, iclass 21, count 0 2006.257.11:52:17.23#ibcon#flushed, iclass 21, count 0 2006.257.11:52:17.23#ibcon#about to write, iclass 21, count 0 2006.257.11:52:17.23#ibcon#wrote, iclass 21, count 0 2006.257.11:52:17.23#ibcon#about to read 3, iclass 21, count 0 2006.257.11:52:17.25#ibcon#read 3, iclass 21, count 0 2006.257.11:52:17.25#ibcon#about to read 4, iclass 21, count 0 2006.257.11:52:17.25#ibcon#read 4, iclass 21, count 0 2006.257.11:52:17.25#ibcon#about to read 5, iclass 21, count 0 2006.257.11:52:17.25#ibcon#read 5, iclass 21, count 0 2006.257.11:52:17.25#ibcon#about to read 6, iclass 21, count 0 2006.257.11:52:17.25#ibcon#read 6, iclass 21, count 0 2006.257.11:52:17.25#ibcon#end of sib2, iclass 21, count 0 2006.257.11:52:17.25#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:52:17.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:52:17.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:52:17.25#ibcon#*before write, iclass 21, count 0 2006.257.11:52:17.25#ibcon#enter sib2, iclass 21, count 0 2006.257.11:52:17.25#ibcon#flushed, iclass 21, count 0 2006.257.11:52:17.25#ibcon#about to write, iclass 21, count 0 2006.257.11:52:17.25#ibcon#wrote, iclass 21, count 0 2006.257.11:52:17.25#ibcon#about to read 3, iclass 21, count 0 2006.257.11:52:17.29#ibcon#read 3, iclass 21, count 0 2006.257.11:52:17.29#ibcon#about to read 4, iclass 21, count 0 2006.257.11:52:17.29#ibcon#read 4, iclass 21, count 0 2006.257.11:52:17.29#ibcon#about to read 5, iclass 21, count 0 2006.257.11:52:17.29#ibcon#read 5, iclass 21, count 0 2006.257.11:52:17.29#ibcon#about to read 6, iclass 21, count 0 2006.257.11:52:17.29#ibcon#read 6, iclass 21, count 0 2006.257.11:52:17.29#ibcon#end of sib2, iclass 21, count 0 2006.257.11:52:17.29#ibcon#*after write, iclass 21, count 0 2006.257.11:52:17.29#ibcon#*before return 0, iclass 21, count 0 2006.257.11:52:17.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:17.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.11:52:17.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:52:17.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:52:17.29$vck44/vb=8,4 2006.257.11:52:17.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.11:52:17.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.11:52:17.29#ibcon#ireg 11 cls_cnt 2 2006.257.11:52:17.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:17.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:17.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:17.35#ibcon#enter wrdev, iclass 23, count 2 2006.257.11:52:17.35#ibcon#first serial, iclass 23, count 2 2006.257.11:52:17.35#ibcon#enter sib2, iclass 23, count 2 2006.257.11:52:17.35#ibcon#flushed, iclass 23, count 2 2006.257.11:52:17.35#ibcon#about to write, iclass 23, count 2 2006.257.11:52:17.35#ibcon#wrote, iclass 23, count 2 2006.257.11:52:17.35#ibcon#about to read 3, iclass 23, count 2 2006.257.11:52:17.37#ibcon#read 3, iclass 23, count 2 2006.257.11:52:17.37#ibcon#about to read 4, iclass 23, count 2 2006.257.11:52:17.37#ibcon#read 4, iclass 23, count 2 2006.257.11:52:17.37#ibcon#about to read 5, iclass 23, count 2 2006.257.11:52:17.37#ibcon#read 5, iclass 23, count 2 2006.257.11:52:17.37#ibcon#about to read 6, iclass 23, count 2 2006.257.11:52:17.37#ibcon#read 6, iclass 23, count 2 2006.257.11:52:17.37#ibcon#end of sib2, iclass 23, count 2 2006.257.11:52:17.37#ibcon#*mode == 0, iclass 23, count 2 2006.257.11:52:17.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.11:52:17.37#ibcon#[27=AT08-04\r\n] 2006.257.11:52:17.37#ibcon#*before write, iclass 23, count 2 2006.257.11:52:17.37#ibcon#enter sib2, iclass 23, count 2 2006.257.11:52:17.37#ibcon#flushed, iclass 23, count 2 2006.257.11:52:17.37#ibcon#about to write, iclass 23, count 2 2006.257.11:52:17.37#ibcon#wrote, iclass 23, count 2 2006.257.11:52:17.37#ibcon#about to read 3, iclass 23, count 2 2006.257.11:52:17.40#ibcon#read 3, iclass 23, count 2 2006.257.11:52:17.40#ibcon#about to read 4, iclass 23, count 2 2006.257.11:52:17.40#ibcon#read 4, iclass 23, count 2 2006.257.11:52:17.40#ibcon#about to read 5, iclass 23, count 2 2006.257.11:52:17.40#ibcon#read 5, iclass 23, count 2 2006.257.11:52:17.40#ibcon#about to read 6, iclass 23, count 2 2006.257.11:52:17.40#ibcon#read 6, iclass 23, count 2 2006.257.11:52:17.40#ibcon#end of sib2, iclass 23, count 2 2006.257.11:52:17.40#ibcon#*after write, iclass 23, count 2 2006.257.11:52:17.44#ibcon#*before return 0, iclass 23, count 2 2006.257.11:52:17.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:17.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.11:52:17.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.11:52:17.44#ibcon#ireg 7 cls_cnt 0 2006.257.11:52:17.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:17.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:17.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:17.56#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:52:17.56#ibcon#first serial, iclass 23, count 0 2006.257.11:52:17.56#ibcon#enter sib2, iclass 23, count 0 2006.257.11:52:17.56#ibcon#flushed, iclass 23, count 0 2006.257.11:52:17.56#ibcon#about to write, iclass 23, count 0 2006.257.11:52:17.56#ibcon#wrote, iclass 23, count 0 2006.257.11:52:17.56#ibcon#about to read 3, iclass 23, count 0 2006.257.11:52:17.58#ibcon#read 3, iclass 23, count 0 2006.257.11:52:17.58#ibcon#about to read 4, iclass 23, count 0 2006.257.11:52:17.58#ibcon#read 4, iclass 23, count 0 2006.257.11:52:17.58#ibcon#about to read 5, iclass 23, count 0 2006.257.11:52:17.58#ibcon#read 5, iclass 23, count 0 2006.257.11:52:17.58#ibcon#about to read 6, iclass 23, count 0 2006.257.11:52:17.58#ibcon#read 6, iclass 23, count 0 2006.257.11:52:17.58#ibcon#end of sib2, iclass 23, count 0 2006.257.11:52:17.58#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:52:17.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:52:17.58#ibcon#[27=USB\r\n] 2006.257.11:52:17.58#ibcon#*before write, iclass 23, count 0 2006.257.11:52:17.58#ibcon#enter sib2, iclass 23, count 0 2006.257.11:52:17.58#ibcon#flushed, iclass 23, count 0 2006.257.11:52:17.58#ibcon#about to write, iclass 23, count 0 2006.257.11:52:17.58#ibcon#wrote, iclass 23, count 0 2006.257.11:52:17.58#ibcon#about to read 3, iclass 23, count 0 2006.257.11:52:17.61#ibcon#read 3, iclass 23, count 0 2006.257.11:52:17.61#ibcon#about to read 4, iclass 23, count 0 2006.257.11:52:17.61#ibcon#read 4, iclass 23, count 0 2006.257.11:52:17.61#ibcon#about to read 5, iclass 23, count 0 2006.257.11:52:17.61#ibcon#read 5, iclass 23, count 0 2006.257.11:52:17.61#ibcon#about to read 6, iclass 23, count 0 2006.257.11:52:17.61#ibcon#read 6, iclass 23, count 0 2006.257.11:52:17.61#ibcon#end of sib2, iclass 23, count 0 2006.257.11:52:17.61#ibcon#*after write, iclass 23, count 0 2006.257.11:52:17.61#ibcon#*before return 0, iclass 23, count 0 2006.257.11:52:17.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:17.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.11:52:17.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:52:17.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:52:17.61$vck44/vabw=wide 2006.257.11:52:17.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.11:52:17.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.11:52:17.61#ibcon#ireg 8 cls_cnt 0 2006.257.11:52:17.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:17.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:17.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:17.61#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:52:17.61#ibcon#first serial, iclass 25, count 0 2006.257.11:52:17.61#ibcon#enter sib2, iclass 25, count 0 2006.257.11:52:17.61#ibcon#flushed, iclass 25, count 0 2006.257.11:52:17.61#ibcon#about to write, iclass 25, count 0 2006.257.11:52:17.61#ibcon#wrote, iclass 25, count 0 2006.257.11:52:17.61#ibcon#about to read 3, iclass 25, count 0 2006.257.11:52:17.63#ibcon#read 3, iclass 25, count 0 2006.257.11:52:17.63#ibcon#about to read 4, iclass 25, count 0 2006.257.11:52:17.63#ibcon#read 4, iclass 25, count 0 2006.257.11:52:17.63#ibcon#about to read 5, iclass 25, count 0 2006.257.11:52:17.63#ibcon#read 5, iclass 25, count 0 2006.257.11:52:17.63#ibcon#about to read 6, iclass 25, count 0 2006.257.11:52:17.63#ibcon#read 6, iclass 25, count 0 2006.257.11:52:17.63#ibcon#end of sib2, iclass 25, count 0 2006.257.11:52:17.63#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:52:17.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:52:17.63#ibcon#[25=BW32\r\n] 2006.257.11:52:17.63#ibcon#*before write, iclass 25, count 0 2006.257.11:52:17.63#ibcon#enter sib2, iclass 25, count 0 2006.257.11:52:17.63#ibcon#flushed, iclass 25, count 0 2006.257.11:52:17.63#ibcon#about to write, iclass 25, count 0 2006.257.11:52:17.63#ibcon#wrote, iclass 25, count 0 2006.257.11:52:17.63#ibcon#about to read 3, iclass 25, count 0 2006.257.11:52:17.66#ibcon#read 3, iclass 25, count 0 2006.257.11:52:17.66#ibcon#about to read 4, iclass 25, count 0 2006.257.11:52:17.66#ibcon#read 4, iclass 25, count 0 2006.257.11:52:17.66#ibcon#about to read 5, iclass 25, count 0 2006.257.11:52:17.66#ibcon#read 5, iclass 25, count 0 2006.257.11:52:17.66#ibcon#about to read 6, iclass 25, count 0 2006.257.11:52:17.66#ibcon#read 6, iclass 25, count 0 2006.257.11:52:17.66#ibcon#end of sib2, iclass 25, count 0 2006.257.11:52:17.66#ibcon#*after write, iclass 25, count 0 2006.257.11:52:17.66#ibcon#*before return 0, iclass 25, count 0 2006.257.11:52:17.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:17.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.11:52:17.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:52:17.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:52:17.66$vck44/vbbw=wide 2006.257.11:52:17.66#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.11:52:17.66#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.11:52:17.66#ibcon#ireg 8 cls_cnt 0 2006.257.11:52:17.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:52:17.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:52:17.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:52:17.73#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:52:17.73#ibcon#first serial, iclass 27, count 0 2006.257.11:52:17.73#ibcon#enter sib2, iclass 27, count 0 2006.257.11:52:17.73#ibcon#flushed, iclass 27, count 0 2006.257.11:52:17.73#ibcon#about to write, iclass 27, count 0 2006.257.11:52:17.73#ibcon#wrote, iclass 27, count 0 2006.257.11:52:17.73#ibcon#about to read 3, iclass 27, count 0 2006.257.11:52:17.75#ibcon#read 3, iclass 27, count 0 2006.257.11:52:17.75#ibcon#about to read 4, iclass 27, count 0 2006.257.11:52:17.75#ibcon#read 4, iclass 27, count 0 2006.257.11:52:17.75#ibcon#about to read 5, iclass 27, count 0 2006.257.11:52:17.75#ibcon#read 5, iclass 27, count 0 2006.257.11:52:17.75#ibcon#about to read 6, iclass 27, count 0 2006.257.11:52:17.75#ibcon#read 6, iclass 27, count 0 2006.257.11:52:17.75#ibcon#end of sib2, iclass 27, count 0 2006.257.11:52:17.75#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:52:17.75#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:52:17.75#ibcon#[27=BW32\r\n] 2006.257.11:52:17.75#ibcon#*before write, iclass 27, count 0 2006.257.11:52:17.75#ibcon#enter sib2, iclass 27, count 0 2006.257.11:52:17.75#ibcon#flushed, iclass 27, count 0 2006.257.11:52:17.75#ibcon#about to write, iclass 27, count 0 2006.257.11:52:17.75#ibcon#wrote, iclass 27, count 0 2006.257.11:52:17.75#ibcon#about to read 3, iclass 27, count 0 2006.257.11:52:17.78#ibcon#read 3, iclass 27, count 0 2006.257.11:52:17.78#ibcon#about to read 4, iclass 27, count 0 2006.257.11:52:17.78#ibcon#read 4, iclass 27, count 0 2006.257.11:52:17.78#ibcon#about to read 5, iclass 27, count 0 2006.257.11:52:17.78#ibcon#read 5, iclass 27, count 0 2006.257.11:52:17.78#ibcon#about to read 6, iclass 27, count 0 2006.257.11:52:17.78#ibcon#read 6, iclass 27, count 0 2006.257.11:52:17.78#ibcon#end of sib2, iclass 27, count 0 2006.257.11:52:17.78#ibcon#*after write, iclass 27, count 0 2006.257.11:52:17.78#ibcon#*before return 0, iclass 27, count 0 2006.257.11:52:17.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:52:17.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:52:17.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:52:17.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:52:17.78$setupk4/ifdk4 2006.257.11:52:17.78$ifdk4/lo= 2006.257.11:52:17.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:52:17.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:52:17.78$ifdk4/patch= 2006.257.11:52:17.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:52:17.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:52:17.78$setupk4/!*+20s 2006.257.11:52:23.79#abcon#<5=/13 1.5 3.9 18.19 951013.9\r\n> 2006.257.11:52:23.81#abcon#{5=INTERFACE CLEAR} 2006.257.11:52:23.87#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:52:30.14#trakl#Source acquired 2006.257.11:52:31.14#flagr#flagr/antenna,acquired 2006.257.11:52:32.18$setupk4/"tpicd 2006.257.11:52:32.18$setupk4/echo=off 2006.257.11:52:32.18$setupk4/xlog=off 2006.257.11:52:32.18:!2006.257.11:53:28 2006.257.11:53:28.00:preob 2006.257.11:53:29.14/onsource/TRACKING 2006.257.11:53:29.14:!2006.257.11:53:38 2006.257.11:53:38.00:"tape 2006.257.11:53:38.00:"st=record 2006.257.11:53:38.00:data_valid=on 2006.257.11:53:38.00:midob 2006.257.11:53:38.14/onsource/TRACKING 2006.257.11:53:38.14/wx/18.20,1013.9,95 2006.257.11:53:38.28/cable/+6.4809E-03 2006.257.11:53:39.37/va/01,08,usb,yes,32,35 2006.257.11:53:39.37/va/02,07,usb,yes,35,35 2006.257.11:53:39.37/va/03,08,usb,yes,31,33 2006.257.11:53:39.37/va/04,07,usb,yes,36,38 2006.257.11:53:39.37/va/05,04,usb,yes,32,33 2006.257.11:53:39.37/va/06,04,usb,yes,36,35 2006.257.11:53:39.37/va/07,04,usb,yes,37,37 2006.257.11:53:39.37/va/08,04,usb,yes,31,38 2006.257.11:53:39.60/valo/01,524.99,yes,locked 2006.257.11:53:39.60/valo/02,534.99,yes,locked 2006.257.11:53:39.60/valo/03,564.99,yes,locked 2006.257.11:53:39.60/valo/04,624.99,yes,locked 2006.257.11:53:39.60/valo/05,734.99,yes,locked 2006.257.11:53:39.60/valo/06,814.99,yes,locked 2006.257.11:53:39.60/valo/07,864.99,yes,locked 2006.257.11:53:39.60/valo/08,884.99,yes,locked 2006.257.11:53:40.69/vb/01,04,usb,yes,32,29 2006.257.11:53:40.69/vb/02,05,usb,yes,30,30 2006.257.11:53:40.69/vb/03,04,usb,yes,31,34 2006.257.11:53:40.69/vb/04,05,usb,yes,31,30 2006.257.11:53:40.69/vb/05,04,usb,yes,28,30 2006.257.11:53:40.69/vb/06,04,usb,yes,32,28 2006.257.11:53:40.69/vb/07,04,usb,yes,32,32 2006.257.11:53:40.69/vb/08,04,usb,yes,29,33 2006.257.11:53:40.92/vblo/01,629.99,yes,locked 2006.257.11:53:40.92/vblo/02,634.99,yes,locked 2006.257.11:53:40.92/vblo/03,649.99,yes,locked 2006.257.11:53:40.92/vblo/04,679.99,yes,locked 2006.257.11:53:40.92/vblo/05,709.99,yes,locked 2006.257.11:53:40.92/vblo/06,719.99,yes,locked 2006.257.11:53:40.92/vblo/07,734.99,yes,locked 2006.257.11:53:40.92/vblo/08,744.99,yes,locked 2006.257.11:53:41.07/vabw/8 2006.257.11:53:41.22/vbbw/8 2006.257.11:53:41.31/xfe/off,on,15.5 2006.257.11:53:41.68/ifatt/23,28,28,28 2006.257.11:53:42.07/fmout-gps/S +4.59E-07 2006.257.11:53:42.11:!2006.257.11:54:18 2006.257.11:54:18.00:data_valid=off 2006.257.11:54:18.00:"et 2006.257.11:54:18.00:!+3s 2006.257.11:54:21.01:"tape 2006.257.11:54:21.01:postob 2006.257.11:54:21.20/cable/+6.4806E-03 2006.257.11:54:21.20/wx/18.20,1013.9,95 2006.257.11:54:22.07/fmout-gps/S +4.60E-07 2006.257.11:54:22.07:scan_name=257-1156,jd0609,60 2006.257.11:54:22.07:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.11:54:23.14#flagr#flagr/antenna,new-source 2006.257.11:54:23.14:checkk5 2006.257.11:54:23.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:54:23.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:54:24.33/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:54:24.72/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:54:25.12/chk_obsdata//k5ts1/T2571153??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.11:54:25.53/chk_obsdata//k5ts2/T2571153??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.11:54:25.94/chk_obsdata//k5ts3/T2571153??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.11:54:26.34/chk_obsdata//k5ts4/T2571153??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.11:54:27.07/k5log//k5ts1_log_newline 2006.257.11:54:27.78/k5log//k5ts2_log_newline 2006.257.11:54:28.49/k5log//k5ts3_log_newline 2006.257.11:54:29.20/k5log//k5ts4_log_newline 2006.257.11:54:29.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:54:29.22:setupk4=1 2006.257.11:54:29.22$setupk4/echo=on 2006.257.11:54:29.22$setupk4/pcalon 2006.257.11:54:29.22$pcalon/"no phase cal control is implemented here 2006.257.11:54:29.22$setupk4/"tpicd=stop 2006.257.11:54:29.22$setupk4/"rec=synch_on 2006.257.11:54:29.22$setupk4/"rec_mode=128 2006.257.11:54:29.22$setupk4/!* 2006.257.11:54:29.22$setupk4/recpk4 2006.257.11:54:29.22$recpk4/recpatch= 2006.257.11:54:29.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:54:29.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:54:29.23$setupk4/vck44 2006.257.11:54:29.23$vck44/valo=1,524.99 2006.257.11:54:29.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.11:54:29.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.11:54:29.23#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:29.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:29.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:29.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:29.23#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:54:29.23#ibcon#first serial, iclass 12, count 0 2006.257.11:54:29.23#ibcon#enter sib2, iclass 12, count 0 2006.257.11:54:29.23#ibcon#flushed, iclass 12, count 0 2006.257.11:54:29.23#ibcon#about to write, iclass 12, count 0 2006.257.11:54:29.23#ibcon#wrote, iclass 12, count 0 2006.257.11:54:29.23#ibcon#about to read 3, iclass 12, count 0 2006.257.11:54:29.25#ibcon#read 3, iclass 12, count 0 2006.257.11:54:29.25#ibcon#about to read 4, iclass 12, count 0 2006.257.11:54:29.25#ibcon#read 4, iclass 12, count 0 2006.257.11:54:29.25#ibcon#about to read 5, iclass 12, count 0 2006.257.11:54:29.25#ibcon#read 5, iclass 12, count 0 2006.257.11:54:29.25#ibcon#about to read 6, iclass 12, count 0 2006.257.11:54:29.25#ibcon#read 6, iclass 12, count 0 2006.257.11:54:29.25#ibcon#end of sib2, iclass 12, count 0 2006.257.11:54:29.25#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:54:29.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:54:29.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:54:29.25#ibcon#*before write, iclass 12, count 0 2006.257.11:54:29.25#ibcon#enter sib2, iclass 12, count 0 2006.257.11:54:29.25#ibcon#flushed, iclass 12, count 0 2006.257.11:54:29.25#ibcon#about to write, iclass 12, count 0 2006.257.11:54:29.25#ibcon#wrote, iclass 12, count 0 2006.257.11:54:29.25#ibcon#about to read 3, iclass 12, count 0 2006.257.11:54:29.30#ibcon#read 3, iclass 12, count 0 2006.257.11:54:29.30#ibcon#about to read 4, iclass 12, count 0 2006.257.11:54:29.30#ibcon#read 4, iclass 12, count 0 2006.257.11:54:29.30#ibcon#about to read 5, iclass 12, count 0 2006.257.11:54:29.30#ibcon#read 5, iclass 12, count 0 2006.257.11:54:29.30#ibcon#about to read 6, iclass 12, count 0 2006.257.11:54:29.30#ibcon#read 6, iclass 12, count 0 2006.257.11:54:29.30#ibcon#end of sib2, iclass 12, count 0 2006.257.11:54:29.30#ibcon#*after write, iclass 12, count 0 2006.257.11:54:29.30#ibcon#*before return 0, iclass 12, count 0 2006.257.11:54:29.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:29.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:29.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:54:29.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:54:29.30$vck44/va=1,8 2006.257.11:54:29.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.11:54:29.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.11:54:29.30#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:29.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:29.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:29.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:29.30#ibcon#enter wrdev, iclass 14, count 2 2006.257.11:54:29.30#ibcon#first serial, iclass 14, count 2 2006.257.11:54:29.30#ibcon#enter sib2, iclass 14, count 2 2006.257.11:54:29.30#ibcon#flushed, iclass 14, count 2 2006.257.11:54:29.30#ibcon#about to write, iclass 14, count 2 2006.257.11:54:29.30#ibcon#wrote, iclass 14, count 2 2006.257.11:54:29.30#ibcon#about to read 3, iclass 14, count 2 2006.257.11:54:29.32#ibcon#read 3, iclass 14, count 2 2006.257.11:54:29.32#ibcon#about to read 4, iclass 14, count 2 2006.257.11:54:29.32#ibcon#read 4, iclass 14, count 2 2006.257.11:54:29.32#ibcon#about to read 5, iclass 14, count 2 2006.257.11:54:29.32#ibcon#read 5, iclass 14, count 2 2006.257.11:54:29.32#ibcon#about to read 6, iclass 14, count 2 2006.257.11:54:29.32#ibcon#read 6, iclass 14, count 2 2006.257.11:54:29.32#ibcon#end of sib2, iclass 14, count 2 2006.257.11:54:29.32#ibcon#*mode == 0, iclass 14, count 2 2006.257.11:54:29.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.11:54:29.32#ibcon#[25=AT01-08\r\n] 2006.257.11:54:29.32#ibcon#*before write, iclass 14, count 2 2006.257.11:54:29.32#ibcon#enter sib2, iclass 14, count 2 2006.257.11:54:29.32#ibcon#flushed, iclass 14, count 2 2006.257.11:54:29.32#ibcon#about to write, iclass 14, count 2 2006.257.11:54:29.32#ibcon#wrote, iclass 14, count 2 2006.257.11:54:29.32#ibcon#about to read 3, iclass 14, count 2 2006.257.11:54:29.35#ibcon#read 3, iclass 14, count 2 2006.257.11:54:29.35#ibcon#about to read 4, iclass 14, count 2 2006.257.11:54:29.35#ibcon#read 4, iclass 14, count 2 2006.257.11:54:29.35#ibcon#about to read 5, iclass 14, count 2 2006.257.11:54:29.35#ibcon#read 5, iclass 14, count 2 2006.257.11:54:29.35#ibcon#about to read 6, iclass 14, count 2 2006.257.11:54:29.35#ibcon#read 6, iclass 14, count 2 2006.257.11:54:29.35#ibcon#end of sib2, iclass 14, count 2 2006.257.11:54:29.35#ibcon#*after write, iclass 14, count 2 2006.257.11:54:29.35#ibcon#*before return 0, iclass 14, count 2 2006.257.11:54:29.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:29.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:29.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.11:54:29.35#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:29.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:29.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:29.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:29.47#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:54:29.47#ibcon#first serial, iclass 14, count 0 2006.257.11:54:29.47#ibcon#enter sib2, iclass 14, count 0 2006.257.11:54:29.47#ibcon#flushed, iclass 14, count 0 2006.257.11:54:29.47#ibcon#about to write, iclass 14, count 0 2006.257.11:54:29.47#ibcon#wrote, iclass 14, count 0 2006.257.11:54:29.47#ibcon#about to read 3, iclass 14, count 0 2006.257.11:54:29.49#ibcon#read 3, iclass 14, count 0 2006.257.11:54:29.49#ibcon#about to read 4, iclass 14, count 0 2006.257.11:54:29.49#ibcon#read 4, iclass 14, count 0 2006.257.11:54:29.49#ibcon#about to read 5, iclass 14, count 0 2006.257.11:54:29.49#ibcon#read 5, iclass 14, count 0 2006.257.11:54:29.49#ibcon#about to read 6, iclass 14, count 0 2006.257.11:54:29.49#ibcon#read 6, iclass 14, count 0 2006.257.11:54:29.49#ibcon#end of sib2, iclass 14, count 0 2006.257.11:54:29.49#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:54:29.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:54:29.49#ibcon#[25=USB\r\n] 2006.257.11:54:29.49#ibcon#*before write, iclass 14, count 0 2006.257.11:54:29.49#ibcon#enter sib2, iclass 14, count 0 2006.257.11:54:29.49#ibcon#flushed, iclass 14, count 0 2006.257.11:54:29.49#ibcon#about to write, iclass 14, count 0 2006.257.11:54:29.49#ibcon#wrote, iclass 14, count 0 2006.257.11:54:29.49#ibcon#about to read 3, iclass 14, count 0 2006.257.11:54:29.52#ibcon#read 3, iclass 14, count 0 2006.257.11:54:29.52#ibcon#about to read 4, iclass 14, count 0 2006.257.11:54:29.52#ibcon#read 4, iclass 14, count 0 2006.257.11:54:29.52#ibcon#about to read 5, iclass 14, count 0 2006.257.11:54:29.52#ibcon#read 5, iclass 14, count 0 2006.257.11:54:29.52#ibcon#about to read 6, iclass 14, count 0 2006.257.11:54:29.52#ibcon#read 6, iclass 14, count 0 2006.257.11:54:29.52#ibcon#end of sib2, iclass 14, count 0 2006.257.11:54:29.52#ibcon#*after write, iclass 14, count 0 2006.257.11:54:29.52#ibcon#*before return 0, iclass 14, count 0 2006.257.11:54:29.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:29.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:29.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:54:29.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:54:29.52$vck44/valo=2,534.99 2006.257.11:54:29.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.11:54:29.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.11:54:29.52#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:29.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:29.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:29.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:29.52#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:54:29.52#ibcon#first serial, iclass 16, count 0 2006.257.11:54:29.52#ibcon#enter sib2, iclass 16, count 0 2006.257.11:54:29.52#ibcon#flushed, iclass 16, count 0 2006.257.11:54:29.52#ibcon#about to write, iclass 16, count 0 2006.257.11:54:29.52#ibcon#wrote, iclass 16, count 0 2006.257.11:54:29.52#ibcon#about to read 3, iclass 16, count 0 2006.257.11:54:29.54#ibcon#read 3, iclass 16, count 0 2006.257.11:54:29.54#ibcon#about to read 4, iclass 16, count 0 2006.257.11:54:29.54#ibcon#read 4, iclass 16, count 0 2006.257.11:54:29.54#ibcon#about to read 5, iclass 16, count 0 2006.257.11:54:29.54#ibcon#read 5, iclass 16, count 0 2006.257.11:54:29.54#ibcon#about to read 6, iclass 16, count 0 2006.257.11:54:29.54#ibcon#read 6, iclass 16, count 0 2006.257.11:54:29.54#ibcon#end of sib2, iclass 16, count 0 2006.257.11:54:29.54#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:54:29.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:54:29.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:54:29.54#ibcon#*before write, iclass 16, count 0 2006.257.11:54:29.54#ibcon#enter sib2, iclass 16, count 0 2006.257.11:54:29.54#ibcon#flushed, iclass 16, count 0 2006.257.11:54:29.54#ibcon#about to write, iclass 16, count 0 2006.257.11:54:29.54#ibcon#wrote, iclass 16, count 0 2006.257.11:54:29.54#ibcon#about to read 3, iclass 16, count 0 2006.257.11:54:29.58#ibcon#read 3, iclass 16, count 0 2006.257.11:54:29.58#ibcon#about to read 4, iclass 16, count 0 2006.257.11:54:29.58#ibcon#read 4, iclass 16, count 0 2006.257.11:54:29.58#ibcon#about to read 5, iclass 16, count 0 2006.257.11:54:29.58#ibcon#read 5, iclass 16, count 0 2006.257.11:54:29.58#ibcon#about to read 6, iclass 16, count 0 2006.257.11:54:29.58#ibcon#read 6, iclass 16, count 0 2006.257.11:54:29.58#ibcon#end of sib2, iclass 16, count 0 2006.257.11:54:29.58#ibcon#*after write, iclass 16, count 0 2006.257.11:54:29.58#ibcon#*before return 0, iclass 16, count 0 2006.257.11:54:29.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:29.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:29.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:54:29.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:54:29.58$vck44/va=2,7 2006.257.11:54:29.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.11:54:29.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.11:54:29.58#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:29.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:29.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:29.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:29.64#ibcon#enter wrdev, iclass 18, count 2 2006.257.11:54:29.64#ibcon#first serial, iclass 18, count 2 2006.257.11:54:29.64#ibcon#enter sib2, iclass 18, count 2 2006.257.11:54:29.64#ibcon#flushed, iclass 18, count 2 2006.257.11:54:29.64#ibcon#about to write, iclass 18, count 2 2006.257.11:54:29.64#ibcon#wrote, iclass 18, count 2 2006.257.11:54:29.64#ibcon#about to read 3, iclass 18, count 2 2006.257.11:54:29.66#ibcon#read 3, iclass 18, count 2 2006.257.11:54:29.66#ibcon#about to read 4, iclass 18, count 2 2006.257.11:54:29.66#ibcon#read 4, iclass 18, count 2 2006.257.11:54:29.66#ibcon#about to read 5, iclass 18, count 2 2006.257.11:54:29.66#ibcon#read 5, iclass 18, count 2 2006.257.11:54:29.66#ibcon#about to read 6, iclass 18, count 2 2006.257.11:54:29.66#ibcon#read 6, iclass 18, count 2 2006.257.11:54:29.66#ibcon#end of sib2, iclass 18, count 2 2006.257.11:54:29.66#ibcon#*mode == 0, iclass 18, count 2 2006.257.11:54:29.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.11:54:29.66#ibcon#[25=AT02-07\r\n] 2006.257.11:54:29.66#ibcon#*before write, iclass 18, count 2 2006.257.11:54:29.66#ibcon#enter sib2, iclass 18, count 2 2006.257.11:54:29.66#ibcon#flushed, iclass 18, count 2 2006.257.11:54:29.66#ibcon#about to write, iclass 18, count 2 2006.257.11:54:29.66#ibcon#wrote, iclass 18, count 2 2006.257.11:54:29.66#ibcon#about to read 3, iclass 18, count 2 2006.257.11:54:29.69#ibcon#read 3, iclass 18, count 2 2006.257.11:54:29.69#ibcon#about to read 4, iclass 18, count 2 2006.257.11:54:29.69#ibcon#read 4, iclass 18, count 2 2006.257.11:54:29.69#ibcon#about to read 5, iclass 18, count 2 2006.257.11:54:29.69#ibcon#read 5, iclass 18, count 2 2006.257.11:54:29.69#ibcon#about to read 6, iclass 18, count 2 2006.257.11:54:29.69#ibcon#read 6, iclass 18, count 2 2006.257.11:54:29.69#ibcon#end of sib2, iclass 18, count 2 2006.257.11:54:29.69#ibcon#*after write, iclass 18, count 2 2006.257.11:54:29.69#ibcon#*before return 0, iclass 18, count 2 2006.257.11:54:29.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:29.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:29.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.11:54:29.69#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:29.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:29.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:29.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:29.81#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:54:29.81#ibcon#first serial, iclass 18, count 0 2006.257.11:54:29.81#ibcon#enter sib2, iclass 18, count 0 2006.257.11:54:29.81#ibcon#flushed, iclass 18, count 0 2006.257.11:54:29.81#ibcon#about to write, iclass 18, count 0 2006.257.11:54:29.81#ibcon#wrote, iclass 18, count 0 2006.257.11:54:29.81#ibcon#about to read 3, iclass 18, count 0 2006.257.11:54:29.83#ibcon#read 3, iclass 18, count 0 2006.257.11:54:29.83#ibcon#about to read 4, iclass 18, count 0 2006.257.11:54:29.83#ibcon#read 4, iclass 18, count 0 2006.257.11:54:29.83#ibcon#about to read 5, iclass 18, count 0 2006.257.11:54:29.83#ibcon#read 5, iclass 18, count 0 2006.257.11:54:29.83#ibcon#about to read 6, iclass 18, count 0 2006.257.11:54:29.83#ibcon#read 6, iclass 18, count 0 2006.257.11:54:29.83#ibcon#end of sib2, iclass 18, count 0 2006.257.11:54:29.83#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:54:29.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:54:29.83#ibcon#[25=USB\r\n] 2006.257.11:54:29.83#ibcon#*before write, iclass 18, count 0 2006.257.11:54:29.83#ibcon#enter sib2, iclass 18, count 0 2006.257.11:54:29.83#ibcon#flushed, iclass 18, count 0 2006.257.11:54:29.83#ibcon#about to write, iclass 18, count 0 2006.257.11:54:29.83#ibcon#wrote, iclass 18, count 0 2006.257.11:54:29.83#ibcon#about to read 3, iclass 18, count 0 2006.257.11:54:29.86#ibcon#read 3, iclass 18, count 0 2006.257.11:54:29.86#ibcon#about to read 4, iclass 18, count 0 2006.257.11:54:29.86#ibcon#read 4, iclass 18, count 0 2006.257.11:54:29.86#ibcon#about to read 5, iclass 18, count 0 2006.257.11:54:29.86#ibcon#read 5, iclass 18, count 0 2006.257.11:54:29.86#ibcon#about to read 6, iclass 18, count 0 2006.257.11:54:29.86#ibcon#read 6, iclass 18, count 0 2006.257.11:54:29.86#ibcon#end of sib2, iclass 18, count 0 2006.257.11:54:29.86#ibcon#*after write, iclass 18, count 0 2006.257.11:54:29.86#ibcon#*before return 0, iclass 18, count 0 2006.257.11:54:29.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:29.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:29.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:54:29.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:54:29.86$vck44/valo=3,564.99 2006.257.11:54:29.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.11:54:29.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.11:54:29.86#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:29.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:29.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:29.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:29.86#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:54:29.86#ibcon#first serial, iclass 20, count 0 2006.257.11:54:29.86#ibcon#enter sib2, iclass 20, count 0 2006.257.11:54:29.86#ibcon#flushed, iclass 20, count 0 2006.257.11:54:29.86#ibcon#about to write, iclass 20, count 0 2006.257.11:54:29.86#ibcon#wrote, iclass 20, count 0 2006.257.11:54:29.86#ibcon#about to read 3, iclass 20, count 0 2006.257.11:54:29.88#ibcon#read 3, iclass 20, count 0 2006.257.11:54:29.88#ibcon#about to read 4, iclass 20, count 0 2006.257.11:54:29.88#ibcon#read 4, iclass 20, count 0 2006.257.11:54:29.88#ibcon#about to read 5, iclass 20, count 0 2006.257.11:54:29.88#ibcon#read 5, iclass 20, count 0 2006.257.11:54:29.88#ibcon#about to read 6, iclass 20, count 0 2006.257.11:54:29.88#ibcon#read 6, iclass 20, count 0 2006.257.11:54:29.88#ibcon#end of sib2, iclass 20, count 0 2006.257.11:54:29.88#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:54:29.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:54:29.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:54:29.88#ibcon#*before write, iclass 20, count 0 2006.257.11:54:29.88#ibcon#enter sib2, iclass 20, count 0 2006.257.11:54:29.88#ibcon#flushed, iclass 20, count 0 2006.257.11:54:29.88#ibcon#about to write, iclass 20, count 0 2006.257.11:54:29.88#ibcon#wrote, iclass 20, count 0 2006.257.11:54:29.88#ibcon#about to read 3, iclass 20, count 0 2006.257.11:54:29.92#ibcon#read 3, iclass 20, count 0 2006.257.11:54:29.92#ibcon#about to read 4, iclass 20, count 0 2006.257.11:54:29.92#ibcon#read 4, iclass 20, count 0 2006.257.11:54:29.92#ibcon#about to read 5, iclass 20, count 0 2006.257.11:54:29.92#ibcon#read 5, iclass 20, count 0 2006.257.11:54:29.92#ibcon#about to read 6, iclass 20, count 0 2006.257.11:54:29.92#ibcon#read 6, iclass 20, count 0 2006.257.11:54:29.92#ibcon#end of sib2, iclass 20, count 0 2006.257.11:54:29.92#ibcon#*after write, iclass 20, count 0 2006.257.11:54:29.92#ibcon#*before return 0, iclass 20, count 0 2006.257.11:54:29.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:29.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:29.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:54:29.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:54:29.92$vck44/va=3,8 2006.257.11:54:29.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.11:54:29.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.11:54:29.92#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:29.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:29.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:29.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:29.98#ibcon#enter wrdev, iclass 22, count 2 2006.257.11:54:29.98#ibcon#first serial, iclass 22, count 2 2006.257.11:54:29.98#ibcon#enter sib2, iclass 22, count 2 2006.257.11:54:29.98#ibcon#flushed, iclass 22, count 2 2006.257.11:54:29.98#ibcon#about to write, iclass 22, count 2 2006.257.11:54:29.98#ibcon#wrote, iclass 22, count 2 2006.257.11:54:29.98#ibcon#about to read 3, iclass 22, count 2 2006.257.11:54:30.00#ibcon#read 3, iclass 22, count 2 2006.257.11:54:30.00#ibcon#about to read 4, iclass 22, count 2 2006.257.11:54:30.00#ibcon#read 4, iclass 22, count 2 2006.257.11:54:30.00#ibcon#about to read 5, iclass 22, count 2 2006.257.11:54:30.00#ibcon#read 5, iclass 22, count 2 2006.257.11:54:30.00#ibcon#about to read 6, iclass 22, count 2 2006.257.11:54:30.00#ibcon#read 6, iclass 22, count 2 2006.257.11:54:30.00#ibcon#end of sib2, iclass 22, count 2 2006.257.11:54:30.00#ibcon#*mode == 0, iclass 22, count 2 2006.257.11:54:30.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.11:54:30.00#ibcon#[25=AT03-08\r\n] 2006.257.11:54:30.00#ibcon#*before write, iclass 22, count 2 2006.257.11:54:30.00#ibcon#enter sib2, iclass 22, count 2 2006.257.11:54:30.00#ibcon#flushed, iclass 22, count 2 2006.257.11:54:30.00#ibcon#about to write, iclass 22, count 2 2006.257.11:54:30.00#ibcon#wrote, iclass 22, count 2 2006.257.11:54:30.00#ibcon#about to read 3, iclass 22, count 2 2006.257.11:54:30.03#ibcon#read 3, iclass 22, count 2 2006.257.11:54:30.03#ibcon#about to read 4, iclass 22, count 2 2006.257.11:54:30.03#ibcon#read 4, iclass 22, count 2 2006.257.11:54:30.03#ibcon#about to read 5, iclass 22, count 2 2006.257.11:54:30.03#ibcon#read 5, iclass 22, count 2 2006.257.11:54:30.03#ibcon#about to read 6, iclass 22, count 2 2006.257.11:54:30.03#ibcon#read 6, iclass 22, count 2 2006.257.11:54:30.03#ibcon#end of sib2, iclass 22, count 2 2006.257.11:54:30.03#ibcon#*after write, iclass 22, count 2 2006.257.11:54:30.03#ibcon#*before return 0, iclass 22, count 2 2006.257.11:54:30.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:30.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:30.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.11:54:30.03#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:30.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:30.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:30.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:30.15#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:54:30.15#ibcon#first serial, iclass 22, count 0 2006.257.11:54:30.15#ibcon#enter sib2, iclass 22, count 0 2006.257.11:54:30.15#ibcon#flushed, iclass 22, count 0 2006.257.11:54:30.15#ibcon#about to write, iclass 22, count 0 2006.257.11:54:30.15#ibcon#wrote, iclass 22, count 0 2006.257.11:54:30.15#ibcon#about to read 3, iclass 22, count 0 2006.257.11:54:30.17#ibcon#read 3, iclass 22, count 0 2006.257.11:54:30.17#ibcon#about to read 4, iclass 22, count 0 2006.257.11:54:30.17#ibcon#read 4, iclass 22, count 0 2006.257.11:54:30.17#ibcon#about to read 5, iclass 22, count 0 2006.257.11:54:30.17#ibcon#read 5, iclass 22, count 0 2006.257.11:54:30.17#ibcon#about to read 6, iclass 22, count 0 2006.257.11:54:30.17#ibcon#read 6, iclass 22, count 0 2006.257.11:54:30.17#ibcon#end of sib2, iclass 22, count 0 2006.257.11:54:30.17#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:54:30.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:54:30.17#ibcon#[25=USB\r\n] 2006.257.11:54:30.17#ibcon#*before write, iclass 22, count 0 2006.257.11:54:30.17#ibcon#enter sib2, iclass 22, count 0 2006.257.11:54:30.17#ibcon#flushed, iclass 22, count 0 2006.257.11:54:30.17#ibcon#about to write, iclass 22, count 0 2006.257.11:54:30.17#ibcon#wrote, iclass 22, count 0 2006.257.11:54:30.17#ibcon#about to read 3, iclass 22, count 0 2006.257.11:54:30.20#ibcon#read 3, iclass 22, count 0 2006.257.11:54:30.20#ibcon#about to read 4, iclass 22, count 0 2006.257.11:54:30.20#ibcon#read 4, iclass 22, count 0 2006.257.11:54:30.20#ibcon#about to read 5, iclass 22, count 0 2006.257.11:54:30.20#ibcon#read 5, iclass 22, count 0 2006.257.11:54:30.20#ibcon#about to read 6, iclass 22, count 0 2006.257.11:54:30.20#ibcon#read 6, iclass 22, count 0 2006.257.11:54:30.20#ibcon#end of sib2, iclass 22, count 0 2006.257.11:54:30.20#ibcon#*after write, iclass 22, count 0 2006.257.11:54:30.20#ibcon#*before return 0, iclass 22, count 0 2006.257.11:54:30.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:30.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:30.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:54:30.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:54:30.20$vck44/valo=4,624.99 2006.257.11:54:30.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.11:54:30.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.11:54:30.20#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:30.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:30.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:30.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:30.20#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:54:30.20#ibcon#first serial, iclass 24, count 0 2006.257.11:54:30.20#ibcon#enter sib2, iclass 24, count 0 2006.257.11:54:30.20#ibcon#flushed, iclass 24, count 0 2006.257.11:54:30.20#ibcon#about to write, iclass 24, count 0 2006.257.11:54:30.20#ibcon#wrote, iclass 24, count 0 2006.257.11:54:30.20#ibcon#about to read 3, iclass 24, count 0 2006.257.11:54:30.22#ibcon#read 3, iclass 24, count 0 2006.257.11:54:30.22#ibcon#about to read 4, iclass 24, count 0 2006.257.11:54:30.22#ibcon#read 4, iclass 24, count 0 2006.257.11:54:30.22#ibcon#about to read 5, iclass 24, count 0 2006.257.11:54:30.22#ibcon#read 5, iclass 24, count 0 2006.257.11:54:30.22#ibcon#about to read 6, iclass 24, count 0 2006.257.11:54:30.22#ibcon#read 6, iclass 24, count 0 2006.257.11:54:30.22#ibcon#end of sib2, iclass 24, count 0 2006.257.11:54:30.22#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:54:30.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:54:30.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:54:30.22#ibcon#*before write, iclass 24, count 0 2006.257.11:54:30.22#ibcon#enter sib2, iclass 24, count 0 2006.257.11:54:30.22#ibcon#flushed, iclass 24, count 0 2006.257.11:54:30.22#ibcon#about to write, iclass 24, count 0 2006.257.11:54:30.22#ibcon#wrote, iclass 24, count 0 2006.257.11:54:30.22#ibcon#about to read 3, iclass 24, count 0 2006.257.11:54:30.26#ibcon#read 3, iclass 24, count 0 2006.257.11:54:30.26#ibcon#about to read 4, iclass 24, count 0 2006.257.11:54:30.26#ibcon#read 4, iclass 24, count 0 2006.257.11:54:30.26#ibcon#about to read 5, iclass 24, count 0 2006.257.11:54:30.26#ibcon#read 5, iclass 24, count 0 2006.257.11:54:30.26#ibcon#about to read 6, iclass 24, count 0 2006.257.11:54:30.26#ibcon#read 6, iclass 24, count 0 2006.257.11:54:30.26#ibcon#end of sib2, iclass 24, count 0 2006.257.11:54:30.26#ibcon#*after write, iclass 24, count 0 2006.257.11:54:30.26#ibcon#*before return 0, iclass 24, count 0 2006.257.11:54:30.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:30.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:30.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:54:30.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:54:30.26$vck44/va=4,7 2006.257.11:54:30.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.11:54:30.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.11:54:30.26#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:30.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:30.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:30.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:30.32#ibcon#enter wrdev, iclass 26, count 2 2006.257.11:54:30.32#ibcon#first serial, iclass 26, count 2 2006.257.11:54:30.32#ibcon#enter sib2, iclass 26, count 2 2006.257.11:54:30.32#ibcon#flushed, iclass 26, count 2 2006.257.11:54:30.32#ibcon#about to write, iclass 26, count 2 2006.257.11:54:30.32#ibcon#wrote, iclass 26, count 2 2006.257.11:54:30.32#ibcon#about to read 3, iclass 26, count 2 2006.257.11:54:30.34#ibcon#read 3, iclass 26, count 2 2006.257.11:54:30.34#ibcon#about to read 4, iclass 26, count 2 2006.257.11:54:30.34#ibcon#read 4, iclass 26, count 2 2006.257.11:54:30.34#ibcon#about to read 5, iclass 26, count 2 2006.257.11:54:30.34#ibcon#read 5, iclass 26, count 2 2006.257.11:54:30.34#ibcon#about to read 6, iclass 26, count 2 2006.257.11:54:30.34#ibcon#read 6, iclass 26, count 2 2006.257.11:54:30.34#ibcon#end of sib2, iclass 26, count 2 2006.257.11:54:30.34#ibcon#*mode == 0, iclass 26, count 2 2006.257.11:54:30.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.11:54:30.34#ibcon#[25=AT04-07\r\n] 2006.257.11:54:30.34#ibcon#*before write, iclass 26, count 2 2006.257.11:54:30.34#ibcon#enter sib2, iclass 26, count 2 2006.257.11:54:30.34#ibcon#flushed, iclass 26, count 2 2006.257.11:54:30.34#ibcon#about to write, iclass 26, count 2 2006.257.11:54:30.34#ibcon#wrote, iclass 26, count 2 2006.257.11:54:30.34#ibcon#about to read 3, iclass 26, count 2 2006.257.11:54:30.37#ibcon#read 3, iclass 26, count 2 2006.257.11:54:30.37#ibcon#about to read 4, iclass 26, count 2 2006.257.11:54:30.37#ibcon#read 4, iclass 26, count 2 2006.257.11:54:30.37#ibcon#about to read 5, iclass 26, count 2 2006.257.11:54:30.37#ibcon#read 5, iclass 26, count 2 2006.257.11:54:30.37#ibcon#about to read 6, iclass 26, count 2 2006.257.11:54:30.37#ibcon#read 6, iclass 26, count 2 2006.257.11:54:30.37#ibcon#end of sib2, iclass 26, count 2 2006.257.11:54:30.37#ibcon#*after write, iclass 26, count 2 2006.257.11:54:30.37#ibcon#*before return 0, iclass 26, count 2 2006.257.11:54:30.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:30.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:30.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.11:54:30.37#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:30.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:30.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:30.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:30.49#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:54:30.49#ibcon#first serial, iclass 26, count 0 2006.257.11:54:30.49#ibcon#enter sib2, iclass 26, count 0 2006.257.11:54:30.49#ibcon#flushed, iclass 26, count 0 2006.257.11:54:30.49#ibcon#about to write, iclass 26, count 0 2006.257.11:54:30.49#ibcon#wrote, iclass 26, count 0 2006.257.11:54:30.49#ibcon#about to read 3, iclass 26, count 0 2006.257.11:54:30.51#ibcon#read 3, iclass 26, count 0 2006.257.11:54:30.51#ibcon#about to read 4, iclass 26, count 0 2006.257.11:54:30.51#ibcon#read 4, iclass 26, count 0 2006.257.11:54:30.51#ibcon#about to read 5, iclass 26, count 0 2006.257.11:54:30.51#ibcon#read 5, iclass 26, count 0 2006.257.11:54:30.51#ibcon#about to read 6, iclass 26, count 0 2006.257.11:54:30.51#ibcon#read 6, iclass 26, count 0 2006.257.11:54:30.51#ibcon#end of sib2, iclass 26, count 0 2006.257.11:54:30.51#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:54:30.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:54:30.51#ibcon#[25=USB\r\n] 2006.257.11:54:30.51#ibcon#*before write, iclass 26, count 0 2006.257.11:54:30.51#ibcon#enter sib2, iclass 26, count 0 2006.257.11:54:30.51#ibcon#flushed, iclass 26, count 0 2006.257.11:54:30.51#ibcon#about to write, iclass 26, count 0 2006.257.11:54:30.51#ibcon#wrote, iclass 26, count 0 2006.257.11:54:30.51#ibcon#about to read 3, iclass 26, count 0 2006.257.11:54:30.54#ibcon#read 3, iclass 26, count 0 2006.257.11:54:30.54#ibcon#about to read 4, iclass 26, count 0 2006.257.11:54:30.54#ibcon#read 4, iclass 26, count 0 2006.257.11:54:30.54#ibcon#about to read 5, iclass 26, count 0 2006.257.11:54:30.54#ibcon#read 5, iclass 26, count 0 2006.257.11:54:30.54#ibcon#about to read 6, iclass 26, count 0 2006.257.11:54:30.54#ibcon#read 6, iclass 26, count 0 2006.257.11:54:30.54#ibcon#end of sib2, iclass 26, count 0 2006.257.11:54:30.54#ibcon#*after write, iclass 26, count 0 2006.257.11:54:30.54#ibcon#*before return 0, iclass 26, count 0 2006.257.11:54:30.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:30.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:30.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:54:30.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:54:30.54$vck44/valo=5,734.99 2006.257.11:54:30.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.11:54:30.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.11:54:30.54#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:30.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:30.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:30.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:30.54#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:54:30.54#ibcon#first serial, iclass 28, count 0 2006.257.11:54:30.54#ibcon#enter sib2, iclass 28, count 0 2006.257.11:54:30.54#ibcon#flushed, iclass 28, count 0 2006.257.11:54:30.54#ibcon#about to write, iclass 28, count 0 2006.257.11:54:30.54#ibcon#wrote, iclass 28, count 0 2006.257.11:54:30.54#ibcon#about to read 3, iclass 28, count 0 2006.257.11:54:30.56#ibcon#read 3, iclass 28, count 0 2006.257.11:54:30.56#ibcon#about to read 4, iclass 28, count 0 2006.257.11:54:30.56#ibcon#read 4, iclass 28, count 0 2006.257.11:54:30.56#ibcon#about to read 5, iclass 28, count 0 2006.257.11:54:30.56#ibcon#read 5, iclass 28, count 0 2006.257.11:54:30.56#ibcon#about to read 6, iclass 28, count 0 2006.257.11:54:30.56#ibcon#read 6, iclass 28, count 0 2006.257.11:54:30.56#ibcon#end of sib2, iclass 28, count 0 2006.257.11:54:30.56#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:54:30.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:54:30.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:54:30.56#ibcon#*before write, iclass 28, count 0 2006.257.11:54:30.56#ibcon#enter sib2, iclass 28, count 0 2006.257.11:54:30.56#ibcon#flushed, iclass 28, count 0 2006.257.11:54:30.56#ibcon#about to write, iclass 28, count 0 2006.257.11:54:30.56#ibcon#wrote, iclass 28, count 0 2006.257.11:54:30.56#ibcon#about to read 3, iclass 28, count 0 2006.257.11:54:30.60#ibcon#read 3, iclass 28, count 0 2006.257.11:54:30.60#ibcon#about to read 4, iclass 28, count 0 2006.257.11:54:30.60#ibcon#read 4, iclass 28, count 0 2006.257.11:54:30.60#ibcon#about to read 5, iclass 28, count 0 2006.257.11:54:30.60#ibcon#read 5, iclass 28, count 0 2006.257.11:54:30.60#ibcon#about to read 6, iclass 28, count 0 2006.257.11:54:30.60#ibcon#read 6, iclass 28, count 0 2006.257.11:54:30.60#ibcon#end of sib2, iclass 28, count 0 2006.257.11:54:30.60#ibcon#*after write, iclass 28, count 0 2006.257.11:54:30.60#ibcon#*before return 0, iclass 28, count 0 2006.257.11:54:30.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:30.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:30.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:54:30.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:54:30.60$vck44/va=5,4 2006.257.11:54:30.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.11:54:30.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.11:54:30.60#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:30.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:30.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:30.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:30.66#ibcon#enter wrdev, iclass 30, count 2 2006.257.11:54:30.66#ibcon#first serial, iclass 30, count 2 2006.257.11:54:30.66#ibcon#enter sib2, iclass 30, count 2 2006.257.11:54:30.66#ibcon#flushed, iclass 30, count 2 2006.257.11:54:30.66#ibcon#about to write, iclass 30, count 2 2006.257.11:54:30.66#ibcon#wrote, iclass 30, count 2 2006.257.11:54:30.66#ibcon#about to read 3, iclass 30, count 2 2006.257.11:54:30.68#ibcon#read 3, iclass 30, count 2 2006.257.11:54:30.68#ibcon#about to read 4, iclass 30, count 2 2006.257.11:54:30.68#ibcon#read 4, iclass 30, count 2 2006.257.11:54:30.68#ibcon#about to read 5, iclass 30, count 2 2006.257.11:54:30.68#ibcon#read 5, iclass 30, count 2 2006.257.11:54:30.68#ibcon#about to read 6, iclass 30, count 2 2006.257.11:54:30.68#ibcon#read 6, iclass 30, count 2 2006.257.11:54:30.68#ibcon#end of sib2, iclass 30, count 2 2006.257.11:54:30.68#ibcon#*mode == 0, iclass 30, count 2 2006.257.11:54:30.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.11:54:30.68#ibcon#[25=AT05-04\r\n] 2006.257.11:54:30.68#ibcon#*before write, iclass 30, count 2 2006.257.11:54:30.68#ibcon#enter sib2, iclass 30, count 2 2006.257.11:54:30.68#ibcon#flushed, iclass 30, count 2 2006.257.11:54:30.68#ibcon#about to write, iclass 30, count 2 2006.257.11:54:30.68#ibcon#wrote, iclass 30, count 2 2006.257.11:54:30.68#ibcon#about to read 3, iclass 30, count 2 2006.257.11:54:30.71#ibcon#read 3, iclass 30, count 2 2006.257.11:54:30.71#ibcon#about to read 4, iclass 30, count 2 2006.257.11:54:30.71#ibcon#read 4, iclass 30, count 2 2006.257.11:54:30.71#ibcon#about to read 5, iclass 30, count 2 2006.257.11:54:30.71#ibcon#read 5, iclass 30, count 2 2006.257.11:54:30.71#ibcon#about to read 6, iclass 30, count 2 2006.257.11:54:30.71#ibcon#read 6, iclass 30, count 2 2006.257.11:54:30.71#ibcon#end of sib2, iclass 30, count 2 2006.257.11:54:30.71#ibcon#*after write, iclass 30, count 2 2006.257.11:54:30.71#ibcon#*before return 0, iclass 30, count 2 2006.257.11:54:30.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:30.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:30.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.11:54:30.71#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:30.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:30.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:30.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:30.83#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:54:30.83#ibcon#first serial, iclass 30, count 0 2006.257.11:54:30.83#ibcon#enter sib2, iclass 30, count 0 2006.257.11:54:30.83#ibcon#flushed, iclass 30, count 0 2006.257.11:54:30.83#ibcon#about to write, iclass 30, count 0 2006.257.11:54:30.83#ibcon#wrote, iclass 30, count 0 2006.257.11:54:30.83#ibcon#about to read 3, iclass 30, count 0 2006.257.11:54:30.85#ibcon#read 3, iclass 30, count 0 2006.257.11:54:30.85#ibcon#about to read 4, iclass 30, count 0 2006.257.11:54:30.85#ibcon#read 4, iclass 30, count 0 2006.257.11:54:30.85#ibcon#about to read 5, iclass 30, count 0 2006.257.11:54:30.85#ibcon#read 5, iclass 30, count 0 2006.257.11:54:30.85#ibcon#about to read 6, iclass 30, count 0 2006.257.11:54:30.85#ibcon#read 6, iclass 30, count 0 2006.257.11:54:30.85#ibcon#end of sib2, iclass 30, count 0 2006.257.11:54:30.85#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:54:30.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:54:30.85#ibcon#[25=USB\r\n] 2006.257.11:54:30.85#ibcon#*before write, iclass 30, count 0 2006.257.11:54:30.85#ibcon#enter sib2, iclass 30, count 0 2006.257.11:54:30.85#ibcon#flushed, iclass 30, count 0 2006.257.11:54:30.85#ibcon#about to write, iclass 30, count 0 2006.257.11:54:30.85#ibcon#wrote, iclass 30, count 0 2006.257.11:54:30.85#ibcon#about to read 3, iclass 30, count 0 2006.257.11:54:30.88#ibcon#read 3, iclass 30, count 0 2006.257.11:54:30.88#ibcon#about to read 4, iclass 30, count 0 2006.257.11:54:30.88#ibcon#read 4, iclass 30, count 0 2006.257.11:54:30.88#ibcon#about to read 5, iclass 30, count 0 2006.257.11:54:30.88#ibcon#read 5, iclass 30, count 0 2006.257.11:54:30.88#ibcon#about to read 6, iclass 30, count 0 2006.257.11:54:30.88#ibcon#read 6, iclass 30, count 0 2006.257.11:54:30.88#ibcon#end of sib2, iclass 30, count 0 2006.257.11:54:30.88#ibcon#*after write, iclass 30, count 0 2006.257.11:54:30.88#ibcon#*before return 0, iclass 30, count 0 2006.257.11:54:30.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:30.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:30.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:54:30.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:54:30.88$vck44/valo=6,814.99 2006.257.11:54:30.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.11:54:30.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.11:54:30.88#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:30.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:30.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:30.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:30.88#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:54:30.88#ibcon#first serial, iclass 32, count 0 2006.257.11:54:30.88#ibcon#enter sib2, iclass 32, count 0 2006.257.11:54:30.88#ibcon#flushed, iclass 32, count 0 2006.257.11:54:30.88#ibcon#about to write, iclass 32, count 0 2006.257.11:54:30.88#ibcon#wrote, iclass 32, count 0 2006.257.11:54:30.88#ibcon#about to read 3, iclass 32, count 0 2006.257.11:54:30.90#ibcon#read 3, iclass 32, count 0 2006.257.11:54:30.90#ibcon#about to read 4, iclass 32, count 0 2006.257.11:54:30.90#ibcon#read 4, iclass 32, count 0 2006.257.11:54:30.90#ibcon#about to read 5, iclass 32, count 0 2006.257.11:54:30.90#ibcon#read 5, iclass 32, count 0 2006.257.11:54:30.90#ibcon#about to read 6, iclass 32, count 0 2006.257.11:54:30.90#ibcon#read 6, iclass 32, count 0 2006.257.11:54:30.90#ibcon#end of sib2, iclass 32, count 0 2006.257.11:54:30.90#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:54:30.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:54:30.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:54:30.90#ibcon#*before write, iclass 32, count 0 2006.257.11:54:30.90#ibcon#enter sib2, iclass 32, count 0 2006.257.11:54:30.90#ibcon#flushed, iclass 32, count 0 2006.257.11:54:30.90#ibcon#about to write, iclass 32, count 0 2006.257.11:54:30.90#ibcon#wrote, iclass 32, count 0 2006.257.11:54:30.90#ibcon#about to read 3, iclass 32, count 0 2006.257.11:54:30.94#ibcon#read 3, iclass 32, count 0 2006.257.11:54:30.94#ibcon#about to read 4, iclass 32, count 0 2006.257.11:54:30.94#ibcon#read 4, iclass 32, count 0 2006.257.11:54:30.94#ibcon#about to read 5, iclass 32, count 0 2006.257.11:54:30.94#ibcon#read 5, iclass 32, count 0 2006.257.11:54:30.94#ibcon#about to read 6, iclass 32, count 0 2006.257.11:54:30.94#ibcon#read 6, iclass 32, count 0 2006.257.11:54:30.94#ibcon#end of sib2, iclass 32, count 0 2006.257.11:54:30.94#ibcon#*after write, iclass 32, count 0 2006.257.11:54:30.94#ibcon#*before return 0, iclass 32, count 0 2006.257.11:54:30.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:30.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:30.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:54:30.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:54:30.94$vck44/va=6,4 2006.257.11:54:30.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.11:54:30.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.11:54:30.94#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:30.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:31.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:31.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:31.00#ibcon#enter wrdev, iclass 34, count 2 2006.257.11:54:31.00#ibcon#first serial, iclass 34, count 2 2006.257.11:54:31.00#ibcon#enter sib2, iclass 34, count 2 2006.257.11:54:31.00#ibcon#flushed, iclass 34, count 2 2006.257.11:54:31.00#ibcon#about to write, iclass 34, count 2 2006.257.11:54:31.00#ibcon#wrote, iclass 34, count 2 2006.257.11:54:31.00#ibcon#about to read 3, iclass 34, count 2 2006.257.11:54:31.02#ibcon#read 3, iclass 34, count 2 2006.257.11:54:31.02#ibcon#about to read 4, iclass 34, count 2 2006.257.11:54:31.02#ibcon#read 4, iclass 34, count 2 2006.257.11:54:31.02#ibcon#about to read 5, iclass 34, count 2 2006.257.11:54:31.02#ibcon#read 5, iclass 34, count 2 2006.257.11:54:31.02#ibcon#about to read 6, iclass 34, count 2 2006.257.11:54:31.02#ibcon#read 6, iclass 34, count 2 2006.257.11:54:31.02#ibcon#end of sib2, iclass 34, count 2 2006.257.11:54:31.02#ibcon#*mode == 0, iclass 34, count 2 2006.257.11:54:31.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.11:54:31.02#ibcon#[25=AT06-04\r\n] 2006.257.11:54:31.02#ibcon#*before write, iclass 34, count 2 2006.257.11:54:31.02#ibcon#enter sib2, iclass 34, count 2 2006.257.11:54:31.02#ibcon#flushed, iclass 34, count 2 2006.257.11:54:31.02#ibcon#about to write, iclass 34, count 2 2006.257.11:54:31.02#ibcon#wrote, iclass 34, count 2 2006.257.11:54:31.02#ibcon#about to read 3, iclass 34, count 2 2006.257.11:54:31.05#ibcon#read 3, iclass 34, count 2 2006.257.11:54:31.05#ibcon#about to read 4, iclass 34, count 2 2006.257.11:54:31.05#ibcon#read 4, iclass 34, count 2 2006.257.11:54:31.05#ibcon#about to read 5, iclass 34, count 2 2006.257.11:54:31.05#ibcon#read 5, iclass 34, count 2 2006.257.11:54:31.05#ibcon#about to read 6, iclass 34, count 2 2006.257.11:54:31.05#ibcon#read 6, iclass 34, count 2 2006.257.11:54:31.05#ibcon#end of sib2, iclass 34, count 2 2006.257.11:54:31.05#ibcon#*after write, iclass 34, count 2 2006.257.11:54:31.05#ibcon#*before return 0, iclass 34, count 2 2006.257.11:54:31.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:31.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:31.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.11:54:31.05#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:31.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:31.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:31.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:31.17#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:54:31.17#ibcon#first serial, iclass 34, count 0 2006.257.11:54:31.17#ibcon#enter sib2, iclass 34, count 0 2006.257.11:54:31.17#ibcon#flushed, iclass 34, count 0 2006.257.11:54:31.17#ibcon#about to write, iclass 34, count 0 2006.257.11:54:31.17#ibcon#wrote, iclass 34, count 0 2006.257.11:54:31.17#ibcon#about to read 3, iclass 34, count 0 2006.257.11:54:31.19#ibcon#read 3, iclass 34, count 0 2006.257.11:54:31.19#ibcon#about to read 4, iclass 34, count 0 2006.257.11:54:31.19#ibcon#read 4, iclass 34, count 0 2006.257.11:54:31.19#ibcon#about to read 5, iclass 34, count 0 2006.257.11:54:31.19#ibcon#read 5, iclass 34, count 0 2006.257.11:54:31.19#ibcon#about to read 6, iclass 34, count 0 2006.257.11:54:31.19#ibcon#read 6, iclass 34, count 0 2006.257.11:54:31.19#ibcon#end of sib2, iclass 34, count 0 2006.257.11:54:31.19#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:54:31.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:54:31.19#ibcon#[25=USB\r\n] 2006.257.11:54:31.19#ibcon#*before write, iclass 34, count 0 2006.257.11:54:31.19#ibcon#enter sib2, iclass 34, count 0 2006.257.11:54:31.19#ibcon#flushed, iclass 34, count 0 2006.257.11:54:31.19#ibcon#about to write, iclass 34, count 0 2006.257.11:54:31.19#ibcon#wrote, iclass 34, count 0 2006.257.11:54:31.19#ibcon#about to read 3, iclass 34, count 0 2006.257.11:54:31.22#ibcon#read 3, iclass 34, count 0 2006.257.11:54:31.22#ibcon#about to read 4, iclass 34, count 0 2006.257.11:54:31.22#ibcon#read 4, iclass 34, count 0 2006.257.11:54:31.22#ibcon#about to read 5, iclass 34, count 0 2006.257.11:54:31.22#ibcon#read 5, iclass 34, count 0 2006.257.11:54:31.22#ibcon#about to read 6, iclass 34, count 0 2006.257.11:54:31.22#ibcon#read 6, iclass 34, count 0 2006.257.11:54:31.22#ibcon#end of sib2, iclass 34, count 0 2006.257.11:54:31.22#ibcon#*after write, iclass 34, count 0 2006.257.11:54:31.22#ibcon#*before return 0, iclass 34, count 0 2006.257.11:54:31.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:31.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:31.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:54:31.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:54:31.22$vck44/valo=7,864.99 2006.257.11:54:31.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.11:54:31.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.11:54:31.22#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:31.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:31.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:31.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:31.22#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:54:31.22#ibcon#first serial, iclass 36, count 0 2006.257.11:54:31.22#ibcon#enter sib2, iclass 36, count 0 2006.257.11:54:31.22#ibcon#flushed, iclass 36, count 0 2006.257.11:54:31.22#ibcon#about to write, iclass 36, count 0 2006.257.11:54:31.22#ibcon#wrote, iclass 36, count 0 2006.257.11:54:31.22#ibcon#about to read 3, iclass 36, count 0 2006.257.11:54:31.24#ibcon#read 3, iclass 36, count 0 2006.257.11:54:31.24#ibcon#about to read 4, iclass 36, count 0 2006.257.11:54:31.24#ibcon#read 4, iclass 36, count 0 2006.257.11:54:31.24#ibcon#about to read 5, iclass 36, count 0 2006.257.11:54:31.24#ibcon#read 5, iclass 36, count 0 2006.257.11:54:31.24#ibcon#about to read 6, iclass 36, count 0 2006.257.11:54:31.24#ibcon#read 6, iclass 36, count 0 2006.257.11:54:31.24#ibcon#end of sib2, iclass 36, count 0 2006.257.11:54:31.24#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:54:31.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:54:31.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:54:31.24#ibcon#*before write, iclass 36, count 0 2006.257.11:54:31.24#ibcon#enter sib2, iclass 36, count 0 2006.257.11:54:31.24#ibcon#flushed, iclass 36, count 0 2006.257.11:54:31.24#ibcon#about to write, iclass 36, count 0 2006.257.11:54:31.24#ibcon#wrote, iclass 36, count 0 2006.257.11:54:31.24#ibcon#about to read 3, iclass 36, count 0 2006.257.11:54:31.28#ibcon#read 3, iclass 36, count 0 2006.257.11:54:31.28#ibcon#about to read 4, iclass 36, count 0 2006.257.11:54:31.28#ibcon#read 4, iclass 36, count 0 2006.257.11:54:31.28#ibcon#about to read 5, iclass 36, count 0 2006.257.11:54:31.28#ibcon#read 5, iclass 36, count 0 2006.257.11:54:31.28#ibcon#about to read 6, iclass 36, count 0 2006.257.11:54:31.28#ibcon#read 6, iclass 36, count 0 2006.257.11:54:31.28#ibcon#end of sib2, iclass 36, count 0 2006.257.11:54:31.28#ibcon#*after write, iclass 36, count 0 2006.257.11:54:31.28#ibcon#*before return 0, iclass 36, count 0 2006.257.11:54:31.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:31.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:31.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:54:31.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:54:31.28$vck44/va=7,4 2006.257.11:54:31.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.11:54:31.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.11:54:31.28#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:31.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:31.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:31.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:31.34#ibcon#enter wrdev, iclass 38, count 2 2006.257.11:54:31.34#ibcon#first serial, iclass 38, count 2 2006.257.11:54:31.34#ibcon#enter sib2, iclass 38, count 2 2006.257.11:54:31.34#ibcon#flushed, iclass 38, count 2 2006.257.11:54:31.34#ibcon#about to write, iclass 38, count 2 2006.257.11:54:31.34#ibcon#wrote, iclass 38, count 2 2006.257.11:54:31.34#ibcon#about to read 3, iclass 38, count 2 2006.257.11:54:31.36#ibcon#read 3, iclass 38, count 2 2006.257.11:54:31.36#ibcon#about to read 4, iclass 38, count 2 2006.257.11:54:31.36#ibcon#read 4, iclass 38, count 2 2006.257.11:54:31.36#ibcon#about to read 5, iclass 38, count 2 2006.257.11:54:31.36#ibcon#read 5, iclass 38, count 2 2006.257.11:54:31.36#ibcon#about to read 6, iclass 38, count 2 2006.257.11:54:31.36#ibcon#read 6, iclass 38, count 2 2006.257.11:54:31.36#ibcon#end of sib2, iclass 38, count 2 2006.257.11:54:31.36#ibcon#*mode == 0, iclass 38, count 2 2006.257.11:54:31.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.11:54:31.36#ibcon#[25=AT07-04\r\n] 2006.257.11:54:31.36#ibcon#*before write, iclass 38, count 2 2006.257.11:54:31.36#ibcon#enter sib2, iclass 38, count 2 2006.257.11:54:31.36#ibcon#flushed, iclass 38, count 2 2006.257.11:54:31.36#ibcon#about to write, iclass 38, count 2 2006.257.11:54:31.36#ibcon#wrote, iclass 38, count 2 2006.257.11:54:31.36#ibcon#about to read 3, iclass 38, count 2 2006.257.11:54:31.39#ibcon#read 3, iclass 38, count 2 2006.257.11:54:31.40#ibcon#about to read 4, iclass 38, count 2 2006.257.11:54:31.40#ibcon#read 4, iclass 38, count 2 2006.257.11:54:31.40#ibcon#about to read 5, iclass 38, count 2 2006.257.11:54:31.40#ibcon#read 5, iclass 38, count 2 2006.257.11:54:31.40#ibcon#about to read 6, iclass 38, count 2 2006.257.11:54:31.40#ibcon#read 6, iclass 38, count 2 2006.257.11:54:31.40#ibcon#end of sib2, iclass 38, count 2 2006.257.11:54:31.40#ibcon#*after write, iclass 38, count 2 2006.257.11:54:31.40#ibcon#*before return 0, iclass 38, count 2 2006.257.11:54:31.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:31.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:31.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.11:54:31.40#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:31.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:31.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:31.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:31.52#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:54:31.52#ibcon#first serial, iclass 38, count 0 2006.257.11:54:31.52#ibcon#enter sib2, iclass 38, count 0 2006.257.11:54:31.52#ibcon#flushed, iclass 38, count 0 2006.257.11:54:31.52#ibcon#about to write, iclass 38, count 0 2006.257.11:54:31.52#ibcon#wrote, iclass 38, count 0 2006.257.11:54:31.52#ibcon#about to read 3, iclass 38, count 0 2006.257.11:54:31.54#ibcon#read 3, iclass 38, count 0 2006.257.11:54:31.54#ibcon#about to read 4, iclass 38, count 0 2006.257.11:54:31.54#ibcon#read 4, iclass 38, count 0 2006.257.11:54:31.54#ibcon#about to read 5, iclass 38, count 0 2006.257.11:54:31.54#ibcon#read 5, iclass 38, count 0 2006.257.11:54:31.54#ibcon#about to read 6, iclass 38, count 0 2006.257.11:54:31.54#ibcon#read 6, iclass 38, count 0 2006.257.11:54:31.54#ibcon#end of sib2, iclass 38, count 0 2006.257.11:54:31.54#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:54:31.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:54:31.54#ibcon#[25=USB\r\n] 2006.257.11:54:31.54#ibcon#*before write, iclass 38, count 0 2006.257.11:54:31.54#ibcon#enter sib2, iclass 38, count 0 2006.257.11:54:31.54#ibcon#flushed, iclass 38, count 0 2006.257.11:54:31.54#ibcon#about to write, iclass 38, count 0 2006.257.11:54:31.54#ibcon#wrote, iclass 38, count 0 2006.257.11:54:31.54#ibcon#about to read 3, iclass 38, count 0 2006.257.11:54:31.57#ibcon#read 3, iclass 38, count 0 2006.257.11:54:31.57#ibcon#about to read 4, iclass 38, count 0 2006.257.11:54:31.57#ibcon#read 4, iclass 38, count 0 2006.257.11:54:31.57#ibcon#about to read 5, iclass 38, count 0 2006.257.11:54:31.57#ibcon#read 5, iclass 38, count 0 2006.257.11:54:31.57#ibcon#about to read 6, iclass 38, count 0 2006.257.11:54:31.57#ibcon#read 6, iclass 38, count 0 2006.257.11:54:31.57#ibcon#end of sib2, iclass 38, count 0 2006.257.11:54:31.57#ibcon#*after write, iclass 38, count 0 2006.257.11:54:31.57#ibcon#*before return 0, iclass 38, count 0 2006.257.11:54:31.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:31.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:31.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:54:31.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:54:31.57$vck44/valo=8,884.99 2006.257.11:54:31.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.11:54:31.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.11:54:31.57#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:31.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:31.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:31.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:31.57#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:54:31.57#ibcon#first serial, iclass 40, count 0 2006.257.11:54:31.57#ibcon#enter sib2, iclass 40, count 0 2006.257.11:54:31.57#ibcon#flushed, iclass 40, count 0 2006.257.11:54:31.57#ibcon#about to write, iclass 40, count 0 2006.257.11:54:31.57#ibcon#wrote, iclass 40, count 0 2006.257.11:54:31.57#ibcon#about to read 3, iclass 40, count 0 2006.257.11:54:31.59#ibcon#read 3, iclass 40, count 0 2006.257.11:54:31.59#ibcon#about to read 4, iclass 40, count 0 2006.257.11:54:31.59#ibcon#read 4, iclass 40, count 0 2006.257.11:54:31.59#ibcon#about to read 5, iclass 40, count 0 2006.257.11:54:31.59#ibcon#read 5, iclass 40, count 0 2006.257.11:54:31.59#ibcon#about to read 6, iclass 40, count 0 2006.257.11:54:31.59#ibcon#read 6, iclass 40, count 0 2006.257.11:54:31.59#ibcon#end of sib2, iclass 40, count 0 2006.257.11:54:31.59#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:54:31.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:54:31.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:54:31.59#ibcon#*before write, iclass 40, count 0 2006.257.11:54:31.59#ibcon#enter sib2, iclass 40, count 0 2006.257.11:54:31.59#ibcon#flushed, iclass 40, count 0 2006.257.11:54:31.59#ibcon#about to write, iclass 40, count 0 2006.257.11:54:31.59#ibcon#wrote, iclass 40, count 0 2006.257.11:54:31.59#ibcon#about to read 3, iclass 40, count 0 2006.257.11:54:31.63#ibcon#read 3, iclass 40, count 0 2006.257.11:54:31.63#ibcon#about to read 4, iclass 40, count 0 2006.257.11:54:31.63#ibcon#read 4, iclass 40, count 0 2006.257.11:54:31.63#ibcon#about to read 5, iclass 40, count 0 2006.257.11:54:31.63#ibcon#read 5, iclass 40, count 0 2006.257.11:54:31.63#ibcon#about to read 6, iclass 40, count 0 2006.257.11:54:31.63#ibcon#read 6, iclass 40, count 0 2006.257.11:54:31.63#ibcon#end of sib2, iclass 40, count 0 2006.257.11:54:31.63#ibcon#*after write, iclass 40, count 0 2006.257.11:54:31.63#ibcon#*before return 0, iclass 40, count 0 2006.257.11:54:31.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:31.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:31.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:54:31.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:54:31.63$vck44/va=8,4 2006.257.11:54:31.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.11:54:31.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.11:54:31.63#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:31.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:54:31.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:54:31.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:54:31.69#ibcon#enter wrdev, iclass 4, count 2 2006.257.11:54:31.69#ibcon#first serial, iclass 4, count 2 2006.257.11:54:31.69#ibcon#enter sib2, iclass 4, count 2 2006.257.11:54:31.69#ibcon#flushed, iclass 4, count 2 2006.257.11:54:31.69#ibcon#about to write, iclass 4, count 2 2006.257.11:54:31.69#ibcon#wrote, iclass 4, count 2 2006.257.11:54:31.69#ibcon#about to read 3, iclass 4, count 2 2006.257.11:54:31.71#ibcon#read 3, iclass 4, count 2 2006.257.11:54:31.71#ibcon#about to read 4, iclass 4, count 2 2006.257.11:54:31.71#ibcon#read 4, iclass 4, count 2 2006.257.11:54:31.71#ibcon#about to read 5, iclass 4, count 2 2006.257.11:54:31.71#ibcon#read 5, iclass 4, count 2 2006.257.11:54:31.71#ibcon#about to read 6, iclass 4, count 2 2006.257.11:54:31.71#ibcon#read 6, iclass 4, count 2 2006.257.11:54:31.71#ibcon#end of sib2, iclass 4, count 2 2006.257.11:54:31.71#ibcon#*mode == 0, iclass 4, count 2 2006.257.11:54:31.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.11:54:31.71#ibcon#[25=AT08-04\r\n] 2006.257.11:54:31.71#ibcon#*before write, iclass 4, count 2 2006.257.11:54:31.71#ibcon#enter sib2, iclass 4, count 2 2006.257.11:54:31.71#ibcon#flushed, iclass 4, count 2 2006.257.11:54:31.71#ibcon#about to write, iclass 4, count 2 2006.257.11:54:31.71#ibcon#wrote, iclass 4, count 2 2006.257.11:54:31.71#ibcon#about to read 3, iclass 4, count 2 2006.257.11:54:31.74#ibcon#read 3, iclass 4, count 2 2006.257.11:54:31.74#ibcon#about to read 4, iclass 4, count 2 2006.257.11:54:31.74#ibcon#read 4, iclass 4, count 2 2006.257.11:54:31.74#ibcon#about to read 5, iclass 4, count 2 2006.257.11:54:31.74#ibcon#read 5, iclass 4, count 2 2006.257.11:54:31.74#ibcon#about to read 6, iclass 4, count 2 2006.257.11:54:31.74#ibcon#read 6, iclass 4, count 2 2006.257.11:54:31.74#ibcon#end of sib2, iclass 4, count 2 2006.257.11:54:31.74#ibcon#*after write, iclass 4, count 2 2006.257.11:54:31.74#ibcon#*before return 0, iclass 4, count 2 2006.257.11:54:31.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:54:31.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.11:54:31.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.11:54:31.74#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:31.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:54:31.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:54:31.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:54:31.86#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:54:31.86#ibcon#first serial, iclass 4, count 0 2006.257.11:54:31.86#ibcon#enter sib2, iclass 4, count 0 2006.257.11:54:31.86#ibcon#flushed, iclass 4, count 0 2006.257.11:54:31.86#ibcon#about to write, iclass 4, count 0 2006.257.11:54:31.86#ibcon#wrote, iclass 4, count 0 2006.257.11:54:31.86#ibcon#about to read 3, iclass 4, count 0 2006.257.11:54:31.88#ibcon#read 3, iclass 4, count 0 2006.257.11:54:31.88#ibcon#about to read 4, iclass 4, count 0 2006.257.11:54:31.88#ibcon#read 4, iclass 4, count 0 2006.257.11:54:31.88#ibcon#about to read 5, iclass 4, count 0 2006.257.11:54:31.88#ibcon#read 5, iclass 4, count 0 2006.257.11:54:31.88#ibcon#about to read 6, iclass 4, count 0 2006.257.11:54:31.88#ibcon#read 6, iclass 4, count 0 2006.257.11:54:31.88#ibcon#end of sib2, iclass 4, count 0 2006.257.11:54:31.88#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:54:31.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:54:31.88#ibcon#[25=USB\r\n] 2006.257.11:54:31.88#ibcon#*before write, iclass 4, count 0 2006.257.11:54:31.88#ibcon#enter sib2, iclass 4, count 0 2006.257.11:54:31.88#ibcon#flushed, iclass 4, count 0 2006.257.11:54:31.88#ibcon#about to write, iclass 4, count 0 2006.257.11:54:31.88#ibcon#wrote, iclass 4, count 0 2006.257.11:54:31.88#ibcon#about to read 3, iclass 4, count 0 2006.257.11:54:31.91#ibcon#read 3, iclass 4, count 0 2006.257.11:54:31.91#ibcon#about to read 4, iclass 4, count 0 2006.257.11:54:31.91#ibcon#read 4, iclass 4, count 0 2006.257.11:54:31.91#ibcon#about to read 5, iclass 4, count 0 2006.257.11:54:31.91#ibcon#read 5, iclass 4, count 0 2006.257.11:54:31.91#ibcon#about to read 6, iclass 4, count 0 2006.257.11:54:31.91#ibcon#read 6, iclass 4, count 0 2006.257.11:54:31.91#ibcon#end of sib2, iclass 4, count 0 2006.257.11:54:31.91#ibcon#*after write, iclass 4, count 0 2006.257.11:54:31.91#ibcon#*before return 0, iclass 4, count 0 2006.257.11:54:31.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:54:31.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.11:54:31.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:54:31.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:54:31.91$vck44/vblo=1,629.99 2006.257.11:54:31.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.11:54:31.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.11:54:31.91#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:31.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:54:31.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:54:31.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:54:31.91#ibcon#enter wrdev, iclass 6, count 0 2006.257.11:54:31.91#ibcon#first serial, iclass 6, count 0 2006.257.11:54:31.91#ibcon#enter sib2, iclass 6, count 0 2006.257.11:54:31.91#ibcon#flushed, iclass 6, count 0 2006.257.11:54:31.91#ibcon#about to write, iclass 6, count 0 2006.257.11:54:31.91#ibcon#wrote, iclass 6, count 0 2006.257.11:54:31.91#ibcon#about to read 3, iclass 6, count 0 2006.257.11:54:31.93#ibcon#read 3, iclass 6, count 0 2006.257.11:54:31.93#ibcon#about to read 4, iclass 6, count 0 2006.257.11:54:31.93#ibcon#read 4, iclass 6, count 0 2006.257.11:54:31.93#ibcon#about to read 5, iclass 6, count 0 2006.257.11:54:31.93#ibcon#read 5, iclass 6, count 0 2006.257.11:54:31.93#ibcon#about to read 6, iclass 6, count 0 2006.257.11:54:31.93#ibcon#read 6, iclass 6, count 0 2006.257.11:54:31.93#ibcon#end of sib2, iclass 6, count 0 2006.257.11:54:31.93#ibcon#*mode == 0, iclass 6, count 0 2006.257.11:54:31.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.11:54:31.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:54:31.93#ibcon#*before write, iclass 6, count 0 2006.257.11:54:31.93#ibcon#enter sib2, iclass 6, count 0 2006.257.11:54:31.93#ibcon#flushed, iclass 6, count 0 2006.257.11:54:31.93#ibcon#about to write, iclass 6, count 0 2006.257.11:54:31.93#ibcon#wrote, iclass 6, count 0 2006.257.11:54:31.93#ibcon#about to read 3, iclass 6, count 0 2006.257.11:54:31.97#ibcon#read 3, iclass 6, count 0 2006.257.11:54:31.97#ibcon#about to read 4, iclass 6, count 0 2006.257.11:54:31.97#ibcon#read 4, iclass 6, count 0 2006.257.11:54:31.97#ibcon#about to read 5, iclass 6, count 0 2006.257.11:54:31.97#ibcon#read 5, iclass 6, count 0 2006.257.11:54:31.97#ibcon#about to read 6, iclass 6, count 0 2006.257.11:54:31.97#ibcon#read 6, iclass 6, count 0 2006.257.11:54:31.97#ibcon#end of sib2, iclass 6, count 0 2006.257.11:54:31.97#ibcon#*after write, iclass 6, count 0 2006.257.11:54:31.97#ibcon#*before return 0, iclass 6, count 0 2006.257.11:54:31.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:54:31.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.11:54:31.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.11:54:31.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.11:54:31.97$vck44/vb=1,4 2006.257.11:54:31.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.11:54:31.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.11:54:31.97#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:31.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:54:31.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:54:31.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:54:31.97#ibcon#enter wrdev, iclass 10, count 2 2006.257.11:54:31.97#ibcon#first serial, iclass 10, count 2 2006.257.11:54:31.97#ibcon#enter sib2, iclass 10, count 2 2006.257.11:54:31.97#ibcon#flushed, iclass 10, count 2 2006.257.11:54:31.97#ibcon#about to write, iclass 10, count 2 2006.257.11:54:31.97#ibcon#wrote, iclass 10, count 2 2006.257.11:54:31.97#ibcon#about to read 3, iclass 10, count 2 2006.257.11:54:31.99#ibcon#read 3, iclass 10, count 2 2006.257.11:54:31.99#ibcon#about to read 4, iclass 10, count 2 2006.257.11:54:31.99#ibcon#read 4, iclass 10, count 2 2006.257.11:54:31.99#ibcon#about to read 5, iclass 10, count 2 2006.257.11:54:31.99#ibcon#read 5, iclass 10, count 2 2006.257.11:54:31.99#ibcon#about to read 6, iclass 10, count 2 2006.257.11:54:31.99#ibcon#read 6, iclass 10, count 2 2006.257.11:54:31.99#ibcon#end of sib2, iclass 10, count 2 2006.257.11:54:31.99#ibcon#*mode == 0, iclass 10, count 2 2006.257.11:54:31.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.11:54:31.99#ibcon#[27=AT01-04\r\n] 2006.257.11:54:31.99#ibcon#*before write, iclass 10, count 2 2006.257.11:54:31.99#ibcon#enter sib2, iclass 10, count 2 2006.257.11:54:31.99#ibcon#flushed, iclass 10, count 2 2006.257.11:54:31.99#ibcon#about to write, iclass 10, count 2 2006.257.11:54:31.99#ibcon#wrote, iclass 10, count 2 2006.257.11:54:31.99#ibcon#about to read 3, iclass 10, count 2 2006.257.11:54:32.02#ibcon#read 3, iclass 10, count 2 2006.257.11:54:32.02#ibcon#about to read 4, iclass 10, count 2 2006.257.11:54:32.02#ibcon#read 4, iclass 10, count 2 2006.257.11:54:32.02#ibcon#about to read 5, iclass 10, count 2 2006.257.11:54:32.02#ibcon#read 5, iclass 10, count 2 2006.257.11:54:32.02#ibcon#about to read 6, iclass 10, count 2 2006.257.11:54:32.02#ibcon#read 6, iclass 10, count 2 2006.257.11:54:32.02#ibcon#end of sib2, iclass 10, count 2 2006.257.11:54:32.02#ibcon#*after write, iclass 10, count 2 2006.257.11:54:32.02#ibcon#*before return 0, iclass 10, count 2 2006.257.11:54:32.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:54:32.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.11:54:32.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.11:54:32.02#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:32.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:54:32.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:54:32.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:54:32.14#ibcon#enter wrdev, iclass 10, count 0 2006.257.11:54:32.14#ibcon#first serial, iclass 10, count 0 2006.257.11:54:32.14#ibcon#enter sib2, iclass 10, count 0 2006.257.11:54:32.14#ibcon#flushed, iclass 10, count 0 2006.257.11:54:32.14#ibcon#about to write, iclass 10, count 0 2006.257.11:54:32.14#ibcon#wrote, iclass 10, count 0 2006.257.11:54:32.14#ibcon#about to read 3, iclass 10, count 0 2006.257.11:54:32.16#ibcon#read 3, iclass 10, count 0 2006.257.11:54:32.16#ibcon#about to read 4, iclass 10, count 0 2006.257.11:54:32.16#ibcon#read 4, iclass 10, count 0 2006.257.11:54:32.16#ibcon#about to read 5, iclass 10, count 0 2006.257.11:54:32.16#ibcon#read 5, iclass 10, count 0 2006.257.11:54:32.16#ibcon#about to read 6, iclass 10, count 0 2006.257.11:54:32.16#ibcon#read 6, iclass 10, count 0 2006.257.11:54:32.16#ibcon#end of sib2, iclass 10, count 0 2006.257.11:54:32.16#ibcon#*mode == 0, iclass 10, count 0 2006.257.11:54:32.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.11:54:32.16#ibcon#[27=USB\r\n] 2006.257.11:54:32.16#ibcon#*before write, iclass 10, count 0 2006.257.11:54:32.16#ibcon#enter sib2, iclass 10, count 0 2006.257.11:54:32.16#ibcon#flushed, iclass 10, count 0 2006.257.11:54:32.16#ibcon#about to write, iclass 10, count 0 2006.257.11:54:32.16#ibcon#wrote, iclass 10, count 0 2006.257.11:54:32.16#ibcon#about to read 3, iclass 10, count 0 2006.257.11:54:32.19#ibcon#read 3, iclass 10, count 0 2006.257.11:54:32.19#ibcon#about to read 4, iclass 10, count 0 2006.257.11:54:32.19#ibcon#read 4, iclass 10, count 0 2006.257.11:54:32.19#ibcon#about to read 5, iclass 10, count 0 2006.257.11:54:32.19#ibcon#read 5, iclass 10, count 0 2006.257.11:54:32.19#ibcon#about to read 6, iclass 10, count 0 2006.257.11:54:32.19#ibcon#read 6, iclass 10, count 0 2006.257.11:54:32.19#ibcon#end of sib2, iclass 10, count 0 2006.257.11:54:32.19#ibcon#*after write, iclass 10, count 0 2006.257.11:54:32.19#ibcon#*before return 0, iclass 10, count 0 2006.257.11:54:32.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:54:32.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.11:54:32.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.11:54:32.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.11:54:32.19$vck44/vblo=2,634.99 2006.257.11:54:32.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.11:54:32.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.11:54:32.19#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:32.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:32.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:32.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:32.19#ibcon#enter wrdev, iclass 12, count 0 2006.257.11:54:32.19#ibcon#first serial, iclass 12, count 0 2006.257.11:54:32.19#ibcon#enter sib2, iclass 12, count 0 2006.257.11:54:32.19#ibcon#flushed, iclass 12, count 0 2006.257.11:54:32.19#ibcon#about to write, iclass 12, count 0 2006.257.11:54:32.19#ibcon#wrote, iclass 12, count 0 2006.257.11:54:32.19#ibcon#about to read 3, iclass 12, count 0 2006.257.11:54:32.21#ibcon#read 3, iclass 12, count 0 2006.257.11:54:32.21#ibcon#about to read 4, iclass 12, count 0 2006.257.11:54:32.21#ibcon#read 4, iclass 12, count 0 2006.257.11:54:32.21#ibcon#about to read 5, iclass 12, count 0 2006.257.11:54:32.21#ibcon#read 5, iclass 12, count 0 2006.257.11:54:32.21#ibcon#about to read 6, iclass 12, count 0 2006.257.11:54:32.21#ibcon#read 6, iclass 12, count 0 2006.257.11:54:32.21#ibcon#end of sib2, iclass 12, count 0 2006.257.11:54:32.21#ibcon#*mode == 0, iclass 12, count 0 2006.257.11:54:32.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.11:54:32.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:54:32.21#ibcon#*before write, iclass 12, count 0 2006.257.11:54:32.21#ibcon#enter sib2, iclass 12, count 0 2006.257.11:54:32.21#ibcon#flushed, iclass 12, count 0 2006.257.11:54:32.21#ibcon#about to write, iclass 12, count 0 2006.257.11:54:32.21#ibcon#wrote, iclass 12, count 0 2006.257.11:54:32.21#ibcon#about to read 3, iclass 12, count 0 2006.257.11:54:32.25#ibcon#read 3, iclass 12, count 0 2006.257.11:54:32.25#ibcon#about to read 4, iclass 12, count 0 2006.257.11:54:32.25#ibcon#read 4, iclass 12, count 0 2006.257.11:54:32.25#ibcon#about to read 5, iclass 12, count 0 2006.257.11:54:32.25#ibcon#read 5, iclass 12, count 0 2006.257.11:54:32.25#ibcon#about to read 6, iclass 12, count 0 2006.257.11:54:32.25#ibcon#read 6, iclass 12, count 0 2006.257.11:54:32.25#ibcon#end of sib2, iclass 12, count 0 2006.257.11:54:32.25#ibcon#*after write, iclass 12, count 0 2006.257.11:54:32.25#ibcon#*before return 0, iclass 12, count 0 2006.257.11:54:32.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:32.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.11:54:32.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.11:54:32.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.11:54:32.25$vck44/vb=2,5 2006.257.11:54:32.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.11:54:32.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.11:54:32.25#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:32.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:32.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:32.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:32.31#ibcon#enter wrdev, iclass 14, count 2 2006.257.11:54:32.31#ibcon#first serial, iclass 14, count 2 2006.257.11:54:32.31#ibcon#enter sib2, iclass 14, count 2 2006.257.11:54:32.31#ibcon#flushed, iclass 14, count 2 2006.257.11:54:32.31#ibcon#about to write, iclass 14, count 2 2006.257.11:54:32.31#ibcon#wrote, iclass 14, count 2 2006.257.11:54:32.31#ibcon#about to read 3, iclass 14, count 2 2006.257.11:54:32.33#ibcon#read 3, iclass 14, count 2 2006.257.11:54:32.33#ibcon#about to read 4, iclass 14, count 2 2006.257.11:54:32.33#ibcon#read 4, iclass 14, count 2 2006.257.11:54:32.33#ibcon#about to read 5, iclass 14, count 2 2006.257.11:54:32.33#ibcon#read 5, iclass 14, count 2 2006.257.11:54:32.33#ibcon#about to read 6, iclass 14, count 2 2006.257.11:54:32.33#ibcon#read 6, iclass 14, count 2 2006.257.11:54:32.33#ibcon#end of sib2, iclass 14, count 2 2006.257.11:54:32.33#ibcon#*mode == 0, iclass 14, count 2 2006.257.11:54:32.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.11:54:32.33#ibcon#[27=AT02-05\r\n] 2006.257.11:54:32.33#ibcon#*before write, iclass 14, count 2 2006.257.11:54:32.33#ibcon#enter sib2, iclass 14, count 2 2006.257.11:54:32.33#ibcon#flushed, iclass 14, count 2 2006.257.11:54:32.33#ibcon#about to write, iclass 14, count 2 2006.257.11:54:32.33#ibcon#wrote, iclass 14, count 2 2006.257.11:54:32.33#ibcon#about to read 3, iclass 14, count 2 2006.257.11:54:32.36#ibcon#read 3, iclass 14, count 2 2006.257.11:54:32.36#ibcon#about to read 4, iclass 14, count 2 2006.257.11:54:32.36#ibcon#read 4, iclass 14, count 2 2006.257.11:54:32.36#ibcon#about to read 5, iclass 14, count 2 2006.257.11:54:32.36#ibcon#read 5, iclass 14, count 2 2006.257.11:54:32.36#ibcon#about to read 6, iclass 14, count 2 2006.257.11:54:32.36#ibcon#read 6, iclass 14, count 2 2006.257.11:54:32.36#ibcon#end of sib2, iclass 14, count 2 2006.257.11:54:32.36#ibcon#*after write, iclass 14, count 2 2006.257.11:54:32.36#ibcon#*before return 0, iclass 14, count 2 2006.257.11:54:32.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:32.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.11:54:32.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.11:54:32.36#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:32.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:32.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:32.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:32.48#ibcon#enter wrdev, iclass 14, count 0 2006.257.11:54:32.48#ibcon#first serial, iclass 14, count 0 2006.257.11:54:32.48#ibcon#enter sib2, iclass 14, count 0 2006.257.11:54:32.48#ibcon#flushed, iclass 14, count 0 2006.257.11:54:32.48#ibcon#about to write, iclass 14, count 0 2006.257.11:54:32.48#ibcon#wrote, iclass 14, count 0 2006.257.11:54:32.48#ibcon#about to read 3, iclass 14, count 0 2006.257.11:54:32.50#ibcon#read 3, iclass 14, count 0 2006.257.11:54:32.50#ibcon#about to read 4, iclass 14, count 0 2006.257.11:54:32.50#ibcon#read 4, iclass 14, count 0 2006.257.11:54:32.50#ibcon#about to read 5, iclass 14, count 0 2006.257.11:54:32.50#ibcon#read 5, iclass 14, count 0 2006.257.11:54:32.50#ibcon#about to read 6, iclass 14, count 0 2006.257.11:54:32.50#ibcon#read 6, iclass 14, count 0 2006.257.11:54:32.50#ibcon#end of sib2, iclass 14, count 0 2006.257.11:54:32.50#ibcon#*mode == 0, iclass 14, count 0 2006.257.11:54:32.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.11:54:32.50#ibcon#[27=USB\r\n] 2006.257.11:54:32.50#ibcon#*before write, iclass 14, count 0 2006.257.11:54:32.50#ibcon#enter sib2, iclass 14, count 0 2006.257.11:54:32.50#ibcon#flushed, iclass 14, count 0 2006.257.11:54:32.50#ibcon#about to write, iclass 14, count 0 2006.257.11:54:32.50#ibcon#wrote, iclass 14, count 0 2006.257.11:54:32.50#ibcon#about to read 3, iclass 14, count 0 2006.257.11:54:32.53#ibcon#read 3, iclass 14, count 0 2006.257.11:54:32.53#ibcon#about to read 4, iclass 14, count 0 2006.257.11:54:32.53#ibcon#read 4, iclass 14, count 0 2006.257.11:54:32.53#ibcon#about to read 5, iclass 14, count 0 2006.257.11:54:32.53#ibcon#read 5, iclass 14, count 0 2006.257.11:54:32.53#ibcon#about to read 6, iclass 14, count 0 2006.257.11:54:32.53#ibcon#read 6, iclass 14, count 0 2006.257.11:54:32.53#ibcon#end of sib2, iclass 14, count 0 2006.257.11:54:32.53#ibcon#*after write, iclass 14, count 0 2006.257.11:54:32.53#ibcon#*before return 0, iclass 14, count 0 2006.257.11:54:32.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:32.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.11:54:32.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.11:54:32.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.11:54:32.53$vck44/vblo=3,649.99 2006.257.11:54:32.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.11:54:32.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.11:54:32.53#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:32.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:32.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:32.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:32.53#ibcon#enter wrdev, iclass 16, count 0 2006.257.11:54:32.53#ibcon#first serial, iclass 16, count 0 2006.257.11:54:32.53#ibcon#enter sib2, iclass 16, count 0 2006.257.11:54:32.53#ibcon#flushed, iclass 16, count 0 2006.257.11:54:32.53#ibcon#about to write, iclass 16, count 0 2006.257.11:54:32.53#ibcon#wrote, iclass 16, count 0 2006.257.11:54:32.53#ibcon#about to read 3, iclass 16, count 0 2006.257.11:54:32.55#ibcon#read 3, iclass 16, count 0 2006.257.11:54:32.55#ibcon#about to read 4, iclass 16, count 0 2006.257.11:54:32.55#ibcon#read 4, iclass 16, count 0 2006.257.11:54:32.55#ibcon#about to read 5, iclass 16, count 0 2006.257.11:54:32.55#ibcon#read 5, iclass 16, count 0 2006.257.11:54:32.55#ibcon#about to read 6, iclass 16, count 0 2006.257.11:54:32.55#ibcon#read 6, iclass 16, count 0 2006.257.11:54:32.55#ibcon#end of sib2, iclass 16, count 0 2006.257.11:54:32.55#ibcon#*mode == 0, iclass 16, count 0 2006.257.11:54:32.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.11:54:32.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:54:32.55#ibcon#*before write, iclass 16, count 0 2006.257.11:54:32.55#ibcon#enter sib2, iclass 16, count 0 2006.257.11:54:32.55#ibcon#flushed, iclass 16, count 0 2006.257.11:54:32.55#ibcon#about to write, iclass 16, count 0 2006.257.11:54:32.55#ibcon#wrote, iclass 16, count 0 2006.257.11:54:32.55#ibcon#about to read 3, iclass 16, count 0 2006.257.11:54:32.59#ibcon#read 3, iclass 16, count 0 2006.257.11:54:32.59#ibcon#about to read 4, iclass 16, count 0 2006.257.11:54:32.59#ibcon#read 4, iclass 16, count 0 2006.257.11:54:32.59#ibcon#about to read 5, iclass 16, count 0 2006.257.11:54:32.59#ibcon#read 5, iclass 16, count 0 2006.257.11:54:32.59#ibcon#about to read 6, iclass 16, count 0 2006.257.11:54:32.59#ibcon#read 6, iclass 16, count 0 2006.257.11:54:32.59#ibcon#end of sib2, iclass 16, count 0 2006.257.11:54:32.59#ibcon#*after write, iclass 16, count 0 2006.257.11:54:32.59#ibcon#*before return 0, iclass 16, count 0 2006.257.11:54:32.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:32.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.11:54:32.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.11:54:32.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.11:54:32.59$vck44/vb=3,4 2006.257.11:54:32.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.11:54:32.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.11:54:32.59#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:32.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:32.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:32.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:32.65#ibcon#enter wrdev, iclass 18, count 2 2006.257.11:54:32.65#ibcon#first serial, iclass 18, count 2 2006.257.11:54:32.65#ibcon#enter sib2, iclass 18, count 2 2006.257.11:54:32.65#ibcon#flushed, iclass 18, count 2 2006.257.11:54:32.65#ibcon#about to write, iclass 18, count 2 2006.257.11:54:32.65#ibcon#wrote, iclass 18, count 2 2006.257.11:54:32.65#ibcon#about to read 3, iclass 18, count 2 2006.257.11:54:32.67#ibcon#read 3, iclass 18, count 2 2006.257.11:54:32.67#ibcon#about to read 4, iclass 18, count 2 2006.257.11:54:32.67#ibcon#read 4, iclass 18, count 2 2006.257.11:54:32.67#ibcon#about to read 5, iclass 18, count 2 2006.257.11:54:32.67#ibcon#read 5, iclass 18, count 2 2006.257.11:54:32.67#ibcon#about to read 6, iclass 18, count 2 2006.257.11:54:32.67#ibcon#read 6, iclass 18, count 2 2006.257.11:54:32.67#ibcon#end of sib2, iclass 18, count 2 2006.257.11:54:32.67#ibcon#*mode == 0, iclass 18, count 2 2006.257.11:54:32.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.11:54:32.67#ibcon#[27=AT03-04\r\n] 2006.257.11:54:32.67#ibcon#*before write, iclass 18, count 2 2006.257.11:54:32.67#ibcon#enter sib2, iclass 18, count 2 2006.257.11:54:32.67#ibcon#flushed, iclass 18, count 2 2006.257.11:54:32.67#ibcon#about to write, iclass 18, count 2 2006.257.11:54:32.67#ibcon#wrote, iclass 18, count 2 2006.257.11:54:32.67#ibcon#about to read 3, iclass 18, count 2 2006.257.11:54:32.70#ibcon#read 3, iclass 18, count 2 2006.257.11:54:32.70#ibcon#about to read 4, iclass 18, count 2 2006.257.11:54:32.70#ibcon#read 4, iclass 18, count 2 2006.257.11:54:32.70#ibcon#about to read 5, iclass 18, count 2 2006.257.11:54:32.70#ibcon#read 5, iclass 18, count 2 2006.257.11:54:32.70#ibcon#about to read 6, iclass 18, count 2 2006.257.11:54:32.70#ibcon#read 6, iclass 18, count 2 2006.257.11:54:32.70#ibcon#end of sib2, iclass 18, count 2 2006.257.11:54:32.70#ibcon#*after write, iclass 18, count 2 2006.257.11:54:32.70#ibcon#*before return 0, iclass 18, count 2 2006.257.11:54:32.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:32.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.11:54:32.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.11:54:32.70#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:32.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:32.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:32.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:32.82#ibcon#enter wrdev, iclass 18, count 0 2006.257.11:54:32.82#ibcon#first serial, iclass 18, count 0 2006.257.11:54:32.82#ibcon#enter sib2, iclass 18, count 0 2006.257.11:54:32.82#ibcon#flushed, iclass 18, count 0 2006.257.11:54:32.82#ibcon#about to write, iclass 18, count 0 2006.257.11:54:32.82#ibcon#wrote, iclass 18, count 0 2006.257.11:54:32.82#ibcon#about to read 3, iclass 18, count 0 2006.257.11:54:32.84#ibcon#read 3, iclass 18, count 0 2006.257.11:54:32.84#ibcon#about to read 4, iclass 18, count 0 2006.257.11:54:32.84#ibcon#read 4, iclass 18, count 0 2006.257.11:54:32.84#ibcon#about to read 5, iclass 18, count 0 2006.257.11:54:32.84#ibcon#read 5, iclass 18, count 0 2006.257.11:54:32.84#ibcon#about to read 6, iclass 18, count 0 2006.257.11:54:32.84#ibcon#read 6, iclass 18, count 0 2006.257.11:54:32.84#ibcon#end of sib2, iclass 18, count 0 2006.257.11:54:32.84#ibcon#*mode == 0, iclass 18, count 0 2006.257.11:54:32.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.11:54:32.84#ibcon#[27=USB\r\n] 2006.257.11:54:32.84#ibcon#*before write, iclass 18, count 0 2006.257.11:54:32.84#ibcon#enter sib2, iclass 18, count 0 2006.257.11:54:32.84#ibcon#flushed, iclass 18, count 0 2006.257.11:54:32.84#ibcon#about to write, iclass 18, count 0 2006.257.11:54:32.84#ibcon#wrote, iclass 18, count 0 2006.257.11:54:32.84#ibcon#about to read 3, iclass 18, count 0 2006.257.11:54:32.87#ibcon#read 3, iclass 18, count 0 2006.257.11:54:32.87#ibcon#about to read 4, iclass 18, count 0 2006.257.11:54:32.87#ibcon#read 4, iclass 18, count 0 2006.257.11:54:32.87#ibcon#about to read 5, iclass 18, count 0 2006.257.11:54:32.87#ibcon#read 5, iclass 18, count 0 2006.257.11:54:32.87#ibcon#about to read 6, iclass 18, count 0 2006.257.11:54:32.87#ibcon#read 6, iclass 18, count 0 2006.257.11:54:32.87#ibcon#end of sib2, iclass 18, count 0 2006.257.11:54:32.87#ibcon#*after write, iclass 18, count 0 2006.257.11:54:32.87#ibcon#*before return 0, iclass 18, count 0 2006.257.11:54:32.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:32.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.11:54:32.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.11:54:32.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.11:54:32.87$vck44/vblo=4,679.99 2006.257.11:54:32.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.11:54:32.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.11:54:32.87#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:32.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:32.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:32.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:32.87#ibcon#enter wrdev, iclass 20, count 0 2006.257.11:54:32.87#ibcon#first serial, iclass 20, count 0 2006.257.11:54:32.87#ibcon#enter sib2, iclass 20, count 0 2006.257.11:54:32.87#ibcon#flushed, iclass 20, count 0 2006.257.11:54:32.87#ibcon#about to write, iclass 20, count 0 2006.257.11:54:32.87#ibcon#wrote, iclass 20, count 0 2006.257.11:54:32.87#ibcon#about to read 3, iclass 20, count 0 2006.257.11:54:32.89#ibcon#read 3, iclass 20, count 0 2006.257.11:54:32.89#ibcon#about to read 4, iclass 20, count 0 2006.257.11:54:32.89#ibcon#read 4, iclass 20, count 0 2006.257.11:54:32.89#ibcon#about to read 5, iclass 20, count 0 2006.257.11:54:32.89#ibcon#read 5, iclass 20, count 0 2006.257.11:54:32.89#ibcon#about to read 6, iclass 20, count 0 2006.257.11:54:32.89#ibcon#read 6, iclass 20, count 0 2006.257.11:54:32.89#ibcon#end of sib2, iclass 20, count 0 2006.257.11:54:32.89#ibcon#*mode == 0, iclass 20, count 0 2006.257.11:54:32.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.11:54:32.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:54:32.89#ibcon#*before write, iclass 20, count 0 2006.257.11:54:32.89#ibcon#enter sib2, iclass 20, count 0 2006.257.11:54:32.89#ibcon#flushed, iclass 20, count 0 2006.257.11:54:32.89#ibcon#about to write, iclass 20, count 0 2006.257.11:54:32.89#ibcon#wrote, iclass 20, count 0 2006.257.11:54:32.89#ibcon#about to read 3, iclass 20, count 0 2006.257.11:54:32.93#ibcon#read 3, iclass 20, count 0 2006.257.11:54:32.93#ibcon#about to read 4, iclass 20, count 0 2006.257.11:54:32.93#ibcon#read 4, iclass 20, count 0 2006.257.11:54:32.93#ibcon#about to read 5, iclass 20, count 0 2006.257.11:54:32.93#ibcon#read 5, iclass 20, count 0 2006.257.11:54:32.93#ibcon#about to read 6, iclass 20, count 0 2006.257.11:54:32.93#ibcon#read 6, iclass 20, count 0 2006.257.11:54:32.93#ibcon#end of sib2, iclass 20, count 0 2006.257.11:54:32.93#ibcon#*after write, iclass 20, count 0 2006.257.11:54:32.93#ibcon#*before return 0, iclass 20, count 0 2006.257.11:54:32.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:32.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.11:54:32.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.11:54:32.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.11:54:32.93$vck44/vb=4,5 2006.257.11:54:32.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.11:54:32.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.11:54:32.93#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:32.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:32.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:32.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:32.99#ibcon#enter wrdev, iclass 22, count 2 2006.257.11:54:32.99#ibcon#first serial, iclass 22, count 2 2006.257.11:54:32.99#ibcon#enter sib2, iclass 22, count 2 2006.257.11:54:32.99#ibcon#flushed, iclass 22, count 2 2006.257.11:54:32.99#ibcon#about to write, iclass 22, count 2 2006.257.11:54:32.99#ibcon#wrote, iclass 22, count 2 2006.257.11:54:32.99#ibcon#about to read 3, iclass 22, count 2 2006.257.11:54:33.01#ibcon#read 3, iclass 22, count 2 2006.257.11:54:33.01#ibcon#about to read 4, iclass 22, count 2 2006.257.11:54:33.01#ibcon#read 4, iclass 22, count 2 2006.257.11:54:33.01#ibcon#about to read 5, iclass 22, count 2 2006.257.11:54:33.01#ibcon#read 5, iclass 22, count 2 2006.257.11:54:33.01#ibcon#about to read 6, iclass 22, count 2 2006.257.11:54:33.01#ibcon#read 6, iclass 22, count 2 2006.257.11:54:33.01#ibcon#end of sib2, iclass 22, count 2 2006.257.11:54:33.01#ibcon#*mode == 0, iclass 22, count 2 2006.257.11:54:33.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.11:54:33.01#ibcon#[27=AT04-05\r\n] 2006.257.11:54:33.01#ibcon#*before write, iclass 22, count 2 2006.257.11:54:33.01#ibcon#enter sib2, iclass 22, count 2 2006.257.11:54:33.01#ibcon#flushed, iclass 22, count 2 2006.257.11:54:33.01#ibcon#about to write, iclass 22, count 2 2006.257.11:54:33.01#ibcon#wrote, iclass 22, count 2 2006.257.11:54:33.01#ibcon#about to read 3, iclass 22, count 2 2006.257.11:54:33.04#ibcon#read 3, iclass 22, count 2 2006.257.11:54:33.04#ibcon#about to read 4, iclass 22, count 2 2006.257.11:54:33.04#ibcon#read 4, iclass 22, count 2 2006.257.11:54:33.04#ibcon#about to read 5, iclass 22, count 2 2006.257.11:54:33.04#ibcon#read 5, iclass 22, count 2 2006.257.11:54:33.04#ibcon#about to read 6, iclass 22, count 2 2006.257.11:54:33.04#ibcon#read 6, iclass 22, count 2 2006.257.11:54:33.04#ibcon#end of sib2, iclass 22, count 2 2006.257.11:54:33.04#ibcon#*after write, iclass 22, count 2 2006.257.11:54:33.04#ibcon#*before return 0, iclass 22, count 2 2006.257.11:54:33.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:33.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.11:54:33.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.11:54:33.04#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:33.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:33.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:33.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:33.16#ibcon#enter wrdev, iclass 22, count 0 2006.257.11:54:33.16#ibcon#first serial, iclass 22, count 0 2006.257.11:54:33.16#ibcon#enter sib2, iclass 22, count 0 2006.257.11:54:33.16#ibcon#flushed, iclass 22, count 0 2006.257.11:54:33.16#ibcon#about to write, iclass 22, count 0 2006.257.11:54:33.16#ibcon#wrote, iclass 22, count 0 2006.257.11:54:33.16#ibcon#about to read 3, iclass 22, count 0 2006.257.11:54:33.18#ibcon#read 3, iclass 22, count 0 2006.257.11:54:33.18#ibcon#about to read 4, iclass 22, count 0 2006.257.11:54:33.18#ibcon#read 4, iclass 22, count 0 2006.257.11:54:33.18#ibcon#about to read 5, iclass 22, count 0 2006.257.11:54:33.18#ibcon#read 5, iclass 22, count 0 2006.257.11:54:33.18#ibcon#about to read 6, iclass 22, count 0 2006.257.11:54:33.18#ibcon#read 6, iclass 22, count 0 2006.257.11:54:33.18#ibcon#end of sib2, iclass 22, count 0 2006.257.11:54:33.18#ibcon#*mode == 0, iclass 22, count 0 2006.257.11:54:33.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.11:54:33.18#ibcon#[27=USB\r\n] 2006.257.11:54:33.18#ibcon#*before write, iclass 22, count 0 2006.257.11:54:33.18#ibcon#enter sib2, iclass 22, count 0 2006.257.11:54:33.18#ibcon#flushed, iclass 22, count 0 2006.257.11:54:33.18#ibcon#about to write, iclass 22, count 0 2006.257.11:54:33.18#ibcon#wrote, iclass 22, count 0 2006.257.11:54:33.18#ibcon#about to read 3, iclass 22, count 0 2006.257.11:54:33.21#ibcon#read 3, iclass 22, count 0 2006.257.11:54:33.21#ibcon#about to read 4, iclass 22, count 0 2006.257.11:54:33.21#ibcon#read 4, iclass 22, count 0 2006.257.11:54:33.21#ibcon#about to read 5, iclass 22, count 0 2006.257.11:54:33.21#ibcon#read 5, iclass 22, count 0 2006.257.11:54:33.21#ibcon#about to read 6, iclass 22, count 0 2006.257.11:54:33.21#ibcon#read 6, iclass 22, count 0 2006.257.11:54:33.21#ibcon#end of sib2, iclass 22, count 0 2006.257.11:54:33.21#ibcon#*after write, iclass 22, count 0 2006.257.11:54:33.21#ibcon#*before return 0, iclass 22, count 0 2006.257.11:54:33.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:33.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.11:54:33.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.11:54:33.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.11:54:33.21$vck44/vblo=5,709.99 2006.257.11:54:33.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.11:54:33.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.11:54:33.21#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:33.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:33.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:33.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:33.21#ibcon#enter wrdev, iclass 24, count 0 2006.257.11:54:33.21#ibcon#first serial, iclass 24, count 0 2006.257.11:54:33.21#ibcon#enter sib2, iclass 24, count 0 2006.257.11:54:33.21#ibcon#flushed, iclass 24, count 0 2006.257.11:54:33.21#ibcon#about to write, iclass 24, count 0 2006.257.11:54:33.21#ibcon#wrote, iclass 24, count 0 2006.257.11:54:33.21#ibcon#about to read 3, iclass 24, count 0 2006.257.11:54:33.23#ibcon#read 3, iclass 24, count 0 2006.257.11:54:33.23#ibcon#about to read 4, iclass 24, count 0 2006.257.11:54:33.23#ibcon#read 4, iclass 24, count 0 2006.257.11:54:33.23#ibcon#about to read 5, iclass 24, count 0 2006.257.11:54:33.23#ibcon#read 5, iclass 24, count 0 2006.257.11:54:33.23#ibcon#about to read 6, iclass 24, count 0 2006.257.11:54:33.23#ibcon#read 6, iclass 24, count 0 2006.257.11:54:33.23#ibcon#end of sib2, iclass 24, count 0 2006.257.11:54:33.23#ibcon#*mode == 0, iclass 24, count 0 2006.257.11:54:33.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.11:54:33.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:54:33.23#ibcon#*before write, iclass 24, count 0 2006.257.11:54:33.23#ibcon#enter sib2, iclass 24, count 0 2006.257.11:54:33.23#ibcon#flushed, iclass 24, count 0 2006.257.11:54:33.23#ibcon#about to write, iclass 24, count 0 2006.257.11:54:33.23#ibcon#wrote, iclass 24, count 0 2006.257.11:54:33.23#ibcon#about to read 3, iclass 24, count 0 2006.257.11:54:33.27#ibcon#read 3, iclass 24, count 0 2006.257.11:54:33.27#ibcon#about to read 4, iclass 24, count 0 2006.257.11:54:33.27#ibcon#read 4, iclass 24, count 0 2006.257.11:54:33.27#ibcon#about to read 5, iclass 24, count 0 2006.257.11:54:33.27#ibcon#read 5, iclass 24, count 0 2006.257.11:54:33.27#ibcon#about to read 6, iclass 24, count 0 2006.257.11:54:33.27#ibcon#read 6, iclass 24, count 0 2006.257.11:54:33.27#ibcon#end of sib2, iclass 24, count 0 2006.257.11:54:33.27#ibcon#*after write, iclass 24, count 0 2006.257.11:54:33.27#ibcon#*before return 0, iclass 24, count 0 2006.257.11:54:33.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:33.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.11:54:33.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.11:54:33.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.11:54:33.27$vck44/vb=5,4 2006.257.11:54:33.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.11:54:33.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.11:54:33.27#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:33.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:33.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:33.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:33.33#ibcon#enter wrdev, iclass 26, count 2 2006.257.11:54:33.33#ibcon#first serial, iclass 26, count 2 2006.257.11:54:33.33#ibcon#enter sib2, iclass 26, count 2 2006.257.11:54:33.33#ibcon#flushed, iclass 26, count 2 2006.257.11:54:33.33#ibcon#about to write, iclass 26, count 2 2006.257.11:54:33.33#ibcon#wrote, iclass 26, count 2 2006.257.11:54:33.33#ibcon#about to read 3, iclass 26, count 2 2006.257.11:54:33.35#ibcon#read 3, iclass 26, count 2 2006.257.11:54:33.35#ibcon#about to read 4, iclass 26, count 2 2006.257.11:54:33.35#ibcon#read 4, iclass 26, count 2 2006.257.11:54:33.35#ibcon#about to read 5, iclass 26, count 2 2006.257.11:54:33.35#ibcon#read 5, iclass 26, count 2 2006.257.11:54:33.35#ibcon#about to read 6, iclass 26, count 2 2006.257.11:54:33.35#ibcon#read 6, iclass 26, count 2 2006.257.11:54:33.35#ibcon#end of sib2, iclass 26, count 2 2006.257.11:54:33.35#ibcon#*mode == 0, iclass 26, count 2 2006.257.11:54:33.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.11:54:33.35#ibcon#[27=AT05-04\r\n] 2006.257.11:54:33.35#ibcon#*before write, iclass 26, count 2 2006.257.11:54:33.35#ibcon#enter sib2, iclass 26, count 2 2006.257.11:54:33.35#ibcon#flushed, iclass 26, count 2 2006.257.11:54:33.35#ibcon#about to write, iclass 26, count 2 2006.257.11:54:33.35#ibcon#wrote, iclass 26, count 2 2006.257.11:54:33.35#ibcon#about to read 3, iclass 26, count 2 2006.257.11:54:33.38#ibcon#read 3, iclass 26, count 2 2006.257.11:54:33.38#ibcon#about to read 4, iclass 26, count 2 2006.257.11:54:33.38#ibcon#read 4, iclass 26, count 2 2006.257.11:54:33.38#ibcon#about to read 5, iclass 26, count 2 2006.257.11:54:33.38#ibcon#read 5, iclass 26, count 2 2006.257.11:54:33.38#ibcon#about to read 6, iclass 26, count 2 2006.257.11:54:33.38#ibcon#read 6, iclass 26, count 2 2006.257.11:54:33.38#ibcon#end of sib2, iclass 26, count 2 2006.257.11:54:33.38#ibcon#*after write, iclass 26, count 2 2006.257.11:54:33.38#ibcon#*before return 0, iclass 26, count 2 2006.257.11:54:33.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:33.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.11:54:33.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.11:54:33.38#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:33.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:33.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:33.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:33.50#ibcon#enter wrdev, iclass 26, count 0 2006.257.11:54:33.50#ibcon#first serial, iclass 26, count 0 2006.257.11:54:33.50#ibcon#enter sib2, iclass 26, count 0 2006.257.11:54:33.50#ibcon#flushed, iclass 26, count 0 2006.257.11:54:33.50#ibcon#about to write, iclass 26, count 0 2006.257.11:54:33.50#ibcon#wrote, iclass 26, count 0 2006.257.11:54:33.50#ibcon#about to read 3, iclass 26, count 0 2006.257.11:54:33.52#ibcon#read 3, iclass 26, count 0 2006.257.11:54:33.52#ibcon#about to read 4, iclass 26, count 0 2006.257.11:54:33.52#ibcon#read 4, iclass 26, count 0 2006.257.11:54:33.52#ibcon#about to read 5, iclass 26, count 0 2006.257.11:54:33.52#ibcon#read 5, iclass 26, count 0 2006.257.11:54:33.52#ibcon#about to read 6, iclass 26, count 0 2006.257.11:54:33.52#ibcon#read 6, iclass 26, count 0 2006.257.11:54:33.52#ibcon#end of sib2, iclass 26, count 0 2006.257.11:54:33.52#ibcon#*mode == 0, iclass 26, count 0 2006.257.11:54:33.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.11:54:33.52#ibcon#[27=USB\r\n] 2006.257.11:54:33.52#ibcon#*before write, iclass 26, count 0 2006.257.11:54:33.52#ibcon#enter sib2, iclass 26, count 0 2006.257.11:54:33.52#ibcon#flushed, iclass 26, count 0 2006.257.11:54:33.52#ibcon#about to write, iclass 26, count 0 2006.257.11:54:33.52#ibcon#wrote, iclass 26, count 0 2006.257.11:54:33.52#ibcon#about to read 3, iclass 26, count 0 2006.257.11:54:33.55#ibcon#read 3, iclass 26, count 0 2006.257.11:54:33.55#ibcon#about to read 4, iclass 26, count 0 2006.257.11:54:33.55#ibcon#read 4, iclass 26, count 0 2006.257.11:54:33.55#ibcon#about to read 5, iclass 26, count 0 2006.257.11:54:33.55#ibcon#read 5, iclass 26, count 0 2006.257.11:54:33.55#ibcon#about to read 6, iclass 26, count 0 2006.257.11:54:33.55#ibcon#read 6, iclass 26, count 0 2006.257.11:54:33.55#ibcon#end of sib2, iclass 26, count 0 2006.257.11:54:33.55#ibcon#*after write, iclass 26, count 0 2006.257.11:54:33.55#ibcon#*before return 0, iclass 26, count 0 2006.257.11:54:33.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:33.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.11:54:33.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.11:54:33.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.11:54:33.55$vck44/vblo=6,719.99 2006.257.11:54:33.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.11:54:33.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.11:54:33.55#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:33.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:33.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:33.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:33.55#ibcon#enter wrdev, iclass 28, count 0 2006.257.11:54:33.55#ibcon#first serial, iclass 28, count 0 2006.257.11:54:33.55#ibcon#enter sib2, iclass 28, count 0 2006.257.11:54:33.55#ibcon#flushed, iclass 28, count 0 2006.257.11:54:33.55#ibcon#about to write, iclass 28, count 0 2006.257.11:54:33.55#ibcon#wrote, iclass 28, count 0 2006.257.11:54:33.55#ibcon#about to read 3, iclass 28, count 0 2006.257.11:54:33.57#ibcon#read 3, iclass 28, count 0 2006.257.11:54:33.57#ibcon#about to read 4, iclass 28, count 0 2006.257.11:54:33.57#ibcon#read 4, iclass 28, count 0 2006.257.11:54:33.57#ibcon#about to read 5, iclass 28, count 0 2006.257.11:54:33.57#ibcon#read 5, iclass 28, count 0 2006.257.11:54:33.57#ibcon#about to read 6, iclass 28, count 0 2006.257.11:54:33.57#ibcon#read 6, iclass 28, count 0 2006.257.11:54:33.57#ibcon#end of sib2, iclass 28, count 0 2006.257.11:54:33.57#ibcon#*mode == 0, iclass 28, count 0 2006.257.11:54:33.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.11:54:33.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:54:33.57#ibcon#*before write, iclass 28, count 0 2006.257.11:54:33.57#ibcon#enter sib2, iclass 28, count 0 2006.257.11:54:33.57#ibcon#flushed, iclass 28, count 0 2006.257.11:54:33.57#ibcon#about to write, iclass 28, count 0 2006.257.11:54:33.57#ibcon#wrote, iclass 28, count 0 2006.257.11:54:33.57#ibcon#about to read 3, iclass 28, count 0 2006.257.11:54:33.61#ibcon#read 3, iclass 28, count 0 2006.257.11:54:33.61#ibcon#about to read 4, iclass 28, count 0 2006.257.11:54:33.61#ibcon#read 4, iclass 28, count 0 2006.257.11:54:33.61#ibcon#about to read 5, iclass 28, count 0 2006.257.11:54:33.61#ibcon#read 5, iclass 28, count 0 2006.257.11:54:33.61#ibcon#about to read 6, iclass 28, count 0 2006.257.11:54:33.61#ibcon#read 6, iclass 28, count 0 2006.257.11:54:33.61#ibcon#end of sib2, iclass 28, count 0 2006.257.11:54:33.61#ibcon#*after write, iclass 28, count 0 2006.257.11:54:33.61#ibcon#*before return 0, iclass 28, count 0 2006.257.11:54:33.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:33.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.11:54:33.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.11:54:33.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.11:54:33.61$vck44/vb=6,4 2006.257.11:54:33.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.11:54:33.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.11:54:33.61#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:33.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:33.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:33.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:33.67#ibcon#enter wrdev, iclass 30, count 2 2006.257.11:54:33.67#ibcon#first serial, iclass 30, count 2 2006.257.11:54:33.67#ibcon#enter sib2, iclass 30, count 2 2006.257.11:54:33.67#ibcon#flushed, iclass 30, count 2 2006.257.11:54:33.67#ibcon#about to write, iclass 30, count 2 2006.257.11:54:33.67#ibcon#wrote, iclass 30, count 2 2006.257.11:54:33.67#ibcon#about to read 3, iclass 30, count 2 2006.257.11:54:33.69#ibcon#read 3, iclass 30, count 2 2006.257.11:54:33.69#ibcon#about to read 4, iclass 30, count 2 2006.257.11:54:33.69#ibcon#read 4, iclass 30, count 2 2006.257.11:54:33.69#ibcon#about to read 5, iclass 30, count 2 2006.257.11:54:33.69#ibcon#read 5, iclass 30, count 2 2006.257.11:54:33.69#ibcon#about to read 6, iclass 30, count 2 2006.257.11:54:33.69#ibcon#read 6, iclass 30, count 2 2006.257.11:54:33.69#ibcon#end of sib2, iclass 30, count 2 2006.257.11:54:33.69#ibcon#*mode == 0, iclass 30, count 2 2006.257.11:54:33.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.11:54:33.69#ibcon#[27=AT06-04\r\n] 2006.257.11:54:33.69#ibcon#*before write, iclass 30, count 2 2006.257.11:54:33.69#ibcon#enter sib2, iclass 30, count 2 2006.257.11:54:33.69#ibcon#flushed, iclass 30, count 2 2006.257.11:54:33.69#ibcon#about to write, iclass 30, count 2 2006.257.11:54:33.69#ibcon#wrote, iclass 30, count 2 2006.257.11:54:33.69#ibcon#about to read 3, iclass 30, count 2 2006.257.11:54:33.72#ibcon#read 3, iclass 30, count 2 2006.257.11:54:33.72#ibcon#about to read 4, iclass 30, count 2 2006.257.11:54:33.72#ibcon#read 4, iclass 30, count 2 2006.257.11:54:33.72#ibcon#about to read 5, iclass 30, count 2 2006.257.11:54:33.72#ibcon#read 5, iclass 30, count 2 2006.257.11:54:33.72#ibcon#about to read 6, iclass 30, count 2 2006.257.11:54:33.72#ibcon#read 6, iclass 30, count 2 2006.257.11:54:33.72#ibcon#end of sib2, iclass 30, count 2 2006.257.11:54:33.72#ibcon#*after write, iclass 30, count 2 2006.257.11:54:33.72#ibcon#*before return 0, iclass 30, count 2 2006.257.11:54:33.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:33.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.11:54:33.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.11:54:33.72#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:33.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:33.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:33.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:33.84#ibcon#enter wrdev, iclass 30, count 0 2006.257.11:54:33.84#ibcon#first serial, iclass 30, count 0 2006.257.11:54:33.84#ibcon#enter sib2, iclass 30, count 0 2006.257.11:54:33.84#ibcon#flushed, iclass 30, count 0 2006.257.11:54:33.84#ibcon#about to write, iclass 30, count 0 2006.257.11:54:33.84#ibcon#wrote, iclass 30, count 0 2006.257.11:54:33.84#ibcon#about to read 3, iclass 30, count 0 2006.257.11:54:33.86#ibcon#read 3, iclass 30, count 0 2006.257.11:54:33.86#ibcon#about to read 4, iclass 30, count 0 2006.257.11:54:33.86#ibcon#read 4, iclass 30, count 0 2006.257.11:54:33.86#ibcon#about to read 5, iclass 30, count 0 2006.257.11:54:33.86#ibcon#read 5, iclass 30, count 0 2006.257.11:54:33.86#ibcon#about to read 6, iclass 30, count 0 2006.257.11:54:33.86#ibcon#read 6, iclass 30, count 0 2006.257.11:54:33.86#ibcon#end of sib2, iclass 30, count 0 2006.257.11:54:33.86#ibcon#*mode == 0, iclass 30, count 0 2006.257.11:54:33.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.11:54:33.86#ibcon#[27=USB\r\n] 2006.257.11:54:33.86#ibcon#*before write, iclass 30, count 0 2006.257.11:54:33.86#ibcon#enter sib2, iclass 30, count 0 2006.257.11:54:33.86#ibcon#flushed, iclass 30, count 0 2006.257.11:54:33.86#ibcon#about to write, iclass 30, count 0 2006.257.11:54:33.86#ibcon#wrote, iclass 30, count 0 2006.257.11:54:33.86#ibcon#about to read 3, iclass 30, count 0 2006.257.11:54:33.89#ibcon#read 3, iclass 30, count 0 2006.257.11:54:33.89#ibcon#about to read 4, iclass 30, count 0 2006.257.11:54:33.89#ibcon#read 4, iclass 30, count 0 2006.257.11:54:33.89#ibcon#about to read 5, iclass 30, count 0 2006.257.11:54:33.89#ibcon#read 5, iclass 30, count 0 2006.257.11:54:33.89#ibcon#about to read 6, iclass 30, count 0 2006.257.11:54:33.89#ibcon#read 6, iclass 30, count 0 2006.257.11:54:33.89#ibcon#end of sib2, iclass 30, count 0 2006.257.11:54:33.89#ibcon#*after write, iclass 30, count 0 2006.257.11:54:33.89#ibcon#*before return 0, iclass 30, count 0 2006.257.11:54:33.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:33.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.11:54:33.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.11:54:33.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.11:54:33.89$vck44/vblo=7,734.99 2006.257.11:54:33.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.11:54:33.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.11:54:33.89#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:33.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:33.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:33.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:33.89#ibcon#enter wrdev, iclass 32, count 0 2006.257.11:54:33.89#ibcon#first serial, iclass 32, count 0 2006.257.11:54:33.89#ibcon#enter sib2, iclass 32, count 0 2006.257.11:54:33.89#ibcon#flushed, iclass 32, count 0 2006.257.11:54:33.89#ibcon#about to write, iclass 32, count 0 2006.257.11:54:33.89#ibcon#wrote, iclass 32, count 0 2006.257.11:54:33.89#ibcon#about to read 3, iclass 32, count 0 2006.257.11:54:33.91#ibcon#read 3, iclass 32, count 0 2006.257.11:54:33.91#ibcon#about to read 4, iclass 32, count 0 2006.257.11:54:33.91#ibcon#read 4, iclass 32, count 0 2006.257.11:54:33.91#ibcon#about to read 5, iclass 32, count 0 2006.257.11:54:33.91#ibcon#read 5, iclass 32, count 0 2006.257.11:54:33.91#ibcon#about to read 6, iclass 32, count 0 2006.257.11:54:33.91#ibcon#read 6, iclass 32, count 0 2006.257.11:54:33.91#ibcon#end of sib2, iclass 32, count 0 2006.257.11:54:33.91#ibcon#*mode == 0, iclass 32, count 0 2006.257.11:54:33.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.11:54:33.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:54:33.91#ibcon#*before write, iclass 32, count 0 2006.257.11:54:33.91#ibcon#enter sib2, iclass 32, count 0 2006.257.11:54:33.91#ibcon#flushed, iclass 32, count 0 2006.257.11:54:33.91#ibcon#about to write, iclass 32, count 0 2006.257.11:54:33.91#ibcon#wrote, iclass 32, count 0 2006.257.11:54:33.91#ibcon#about to read 3, iclass 32, count 0 2006.257.11:54:33.95#ibcon#read 3, iclass 32, count 0 2006.257.11:54:33.95#ibcon#about to read 4, iclass 32, count 0 2006.257.11:54:33.95#ibcon#read 4, iclass 32, count 0 2006.257.11:54:33.95#ibcon#about to read 5, iclass 32, count 0 2006.257.11:54:33.95#ibcon#read 5, iclass 32, count 0 2006.257.11:54:33.95#ibcon#about to read 6, iclass 32, count 0 2006.257.11:54:33.95#ibcon#read 6, iclass 32, count 0 2006.257.11:54:33.95#ibcon#end of sib2, iclass 32, count 0 2006.257.11:54:33.95#ibcon#*after write, iclass 32, count 0 2006.257.11:54:33.95#ibcon#*before return 0, iclass 32, count 0 2006.257.11:54:33.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:33.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.11:54:33.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.11:54:33.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.11:54:33.95$vck44/vb=7,4 2006.257.11:54:33.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.11:54:33.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.11:54:33.95#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:33.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:34.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:34.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:34.01#ibcon#enter wrdev, iclass 34, count 2 2006.257.11:54:34.01#ibcon#first serial, iclass 34, count 2 2006.257.11:54:34.01#ibcon#enter sib2, iclass 34, count 2 2006.257.11:54:34.01#ibcon#flushed, iclass 34, count 2 2006.257.11:54:34.01#ibcon#about to write, iclass 34, count 2 2006.257.11:54:34.01#ibcon#wrote, iclass 34, count 2 2006.257.11:54:34.01#ibcon#about to read 3, iclass 34, count 2 2006.257.11:54:34.03#ibcon#read 3, iclass 34, count 2 2006.257.11:54:34.03#ibcon#about to read 4, iclass 34, count 2 2006.257.11:54:34.03#ibcon#read 4, iclass 34, count 2 2006.257.11:54:34.03#ibcon#about to read 5, iclass 34, count 2 2006.257.11:54:34.03#ibcon#read 5, iclass 34, count 2 2006.257.11:54:34.03#ibcon#about to read 6, iclass 34, count 2 2006.257.11:54:34.03#ibcon#read 6, iclass 34, count 2 2006.257.11:54:34.03#ibcon#end of sib2, iclass 34, count 2 2006.257.11:54:34.03#ibcon#*mode == 0, iclass 34, count 2 2006.257.11:54:34.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.11:54:34.03#ibcon#[27=AT07-04\r\n] 2006.257.11:54:34.03#ibcon#*before write, iclass 34, count 2 2006.257.11:54:34.03#ibcon#enter sib2, iclass 34, count 2 2006.257.11:54:34.03#ibcon#flushed, iclass 34, count 2 2006.257.11:54:34.03#ibcon#about to write, iclass 34, count 2 2006.257.11:54:34.03#ibcon#wrote, iclass 34, count 2 2006.257.11:54:34.03#ibcon#about to read 3, iclass 34, count 2 2006.257.11:54:34.06#ibcon#read 3, iclass 34, count 2 2006.257.11:54:34.06#ibcon#about to read 4, iclass 34, count 2 2006.257.11:54:34.06#ibcon#read 4, iclass 34, count 2 2006.257.11:54:34.06#ibcon#about to read 5, iclass 34, count 2 2006.257.11:54:34.06#ibcon#read 5, iclass 34, count 2 2006.257.11:54:34.06#ibcon#about to read 6, iclass 34, count 2 2006.257.11:54:34.06#ibcon#read 6, iclass 34, count 2 2006.257.11:54:34.06#ibcon#end of sib2, iclass 34, count 2 2006.257.11:54:34.06#ibcon#*after write, iclass 34, count 2 2006.257.11:54:34.06#ibcon#*before return 0, iclass 34, count 2 2006.257.11:54:34.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:34.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.11:54:34.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.11:54:34.06#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:34.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:34.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:34.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:34.18#ibcon#enter wrdev, iclass 34, count 0 2006.257.11:54:34.18#ibcon#first serial, iclass 34, count 0 2006.257.11:54:34.18#ibcon#enter sib2, iclass 34, count 0 2006.257.11:54:34.18#ibcon#flushed, iclass 34, count 0 2006.257.11:54:34.18#ibcon#about to write, iclass 34, count 0 2006.257.11:54:34.18#ibcon#wrote, iclass 34, count 0 2006.257.11:54:34.18#ibcon#about to read 3, iclass 34, count 0 2006.257.11:54:34.20#ibcon#read 3, iclass 34, count 0 2006.257.11:54:34.20#ibcon#about to read 4, iclass 34, count 0 2006.257.11:54:34.20#ibcon#read 4, iclass 34, count 0 2006.257.11:54:34.20#ibcon#about to read 5, iclass 34, count 0 2006.257.11:54:34.20#ibcon#read 5, iclass 34, count 0 2006.257.11:54:34.20#ibcon#about to read 6, iclass 34, count 0 2006.257.11:54:34.20#ibcon#read 6, iclass 34, count 0 2006.257.11:54:34.20#ibcon#end of sib2, iclass 34, count 0 2006.257.11:54:34.20#ibcon#*mode == 0, iclass 34, count 0 2006.257.11:54:34.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.11:54:34.20#ibcon#[27=USB\r\n] 2006.257.11:54:34.20#ibcon#*before write, iclass 34, count 0 2006.257.11:54:34.20#ibcon#enter sib2, iclass 34, count 0 2006.257.11:54:34.20#ibcon#flushed, iclass 34, count 0 2006.257.11:54:34.20#ibcon#about to write, iclass 34, count 0 2006.257.11:54:34.20#ibcon#wrote, iclass 34, count 0 2006.257.11:54:34.20#ibcon#about to read 3, iclass 34, count 0 2006.257.11:54:34.23#ibcon#read 3, iclass 34, count 0 2006.257.11:54:34.23#ibcon#about to read 4, iclass 34, count 0 2006.257.11:54:34.23#ibcon#read 4, iclass 34, count 0 2006.257.11:54:34.23#ibcon#about to read 5, iclass 34, count 0 2006.257.11:54:34.23#ibcon#read 5, iclass 34, count 0 2006.257.11:54:34.23#ibcon#about to read 6, iclass 34, count 0 2006.257.11:54:34.23#ibcon#read 6, iclass 34, count 0 2006.257.11:54:34.23#ibcon#end of sib2, iclass 34, count 0 2006.257.11:54:34.23#ibcon#*after write, iclass 34, count 0 2006.257.11:54:34.23#ibcon#*before return 0, iclass 34, count 0 2006.257.11:54:34.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:34.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.11:54:34.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.11:54:34.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.11:54:34.23$vck44/vblo=8,744.99 2006.257.11:54:34.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.11:54:34.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.11:54:34.23#ibcon#ireg 17 cls_cnt 0 2006.257.11:54:34.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:34.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:34.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:34.23#ibcon#enter wrdev, iclass 36, count 0 2006.257.11:54:34.23#ibcon#first serial, iclass 36, count 0 2006.257.11:54:34.23#ibcon#enter sib2, iclass 36, count 0 2006.257.11:54:34.23#ibcon#flushed, iclass 36, count 0 2006.257.11:54:34.23#ibcon#about to write, iclass 36, count 0 2006.257.11:54:34.23#ibcon#wrote, iclass 36, count 0 2006.257.11:54:34.23#ibcon#about to read 3, iclass 36, count 0 2006.257.11:54:34.25#ibcon#read 3, iclass 36, count 0 2006.257.11:54:34.25#ibcon#about to read 4, iclass 36, count 0 2006.257.11:54:34.25#ibcon#read 4, iclass 36, count 0 2006.257.11:54:34.25#ibcon#about to read 5, iclass 36, count 0 2006.257.11:54:34.25#ibcon#read 5, iclass 36, count 0 2006.257.11:54:34.25#ibcon#about to read 6, iclass 36, count 0 2006.257.11:54:34.25#ibcon#read 6, iclass 36, count 0 2006.257.11:54:34.25#ibcon#end of sib2, iclass 36, count 0 2006.257.11:54:34.25#ibcon#*mode == 0, iclass 36, count 0 2006.257.11:54:34.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.11:54:34.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:54:34.25#ibcon#*before write, iclass 36, count 0 2006.257.11:54:34.25#ibcon#enter sib2, iclass 36, count 0 2006.257.11:54:34.25#ibcon#flushed, iclass 36, count 0 2006.257.11:54:34.25#ibcon#about to write, iclass 36, count 0 2006.257.11:54:34.25#ibcon#wrote, iclass 36, count 0 2006.257.11:54:34.25#ibcon#about to read 3, iclass 36, count 0 2006.257.11:54:34.29#ibcon#read 3, iclass 36, count 0 2006.257.11:54:34.29#ibcon#about to read 4, iclass 36, count 0 2006.257.11:54:34.29#ibcon#read 4, iclass 36, count 0 2006.257.11:54:34.29#ibcon#about to read 5, iclass 36, count 0 2006.257.11:54:34.29#ibcon#read 5, iclass 36, count 0 2006.257.11:54:34.29#ibcon#about to read 6, iclass 36, count 0 2006.257.11:54:34.29#ibcon#read 6, iclass 36, count 0 2006.257.11:54:34.29#ibcon#end of sib2, iclass 36, count 0 2006.257.11:54:34.29#ibcon#*after write, iclass 36, count 0 2006.257.11:54:34.29#ibcon#*before return 0, iclass 36, count 0 2006.257.11:54:34.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:34.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.11:54:34.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.11:54:34.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.11:54:34.29$vck44/vb=8,4 2006.257.11:54:34.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.11:54:34.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.11:54:34.29#ibcon#ireg 11 cls_cnt 2 2006.257.11:54:34.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:34.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:34.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:34.35#ibcon#enter wrdev, iclass 38, count 2 2006.257.11:54:34.35#ibcon#first serial, iclass 38, count 2 2006.257.11:54:34.35#ibcon#enter sib2, iclass 38, count 2 2006.257.11:54:34.35#ibcon#flushed, iclass 38, count 2 2006.257.11:54:34.35#ibcon#about to write, iclass 38, count 2 2006.257.11:54:34.35#ibcon#wrote, iclass 38, count 2 2006.257.11:54:34.35#ibcon#about to read 3, iclass 38, count 2 2006.257.11:54:34.37#ibcon#read 3, iclass 38, count 2 2006.257.11:54:34.37#ibcon#about to read 4, iclass 38, count 2 2006.257.11:54:34.37#ibcon#read 4, iclass 38, count 2 2006.257.11:54:34.37#ibcon#about to read 5, iclass 38, count 2 2006.257.11:54:34.37#ibcon#read 5, iclass 38, count 2 2006.257.11:54:34.37#ibcon#about to read 6, iclass 38, count 2 2006.257.11:54:34.37#ibcon#read 6, iclass 38, count 2 2006.257.11:54:34.37#ibcon#end of sib2, iclass 38, count 2 2006.257.11:54:34.37#ibcon#*mode == 0, iclass 38, count 2 2006.257.11:54:34.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.11:54:34.37#ibcon#[27=AT08-04\r\n] 2006.257.11:54:34.37#ibcon#*before write, iclass 38, count 2 2006.257.11:54:34.37#ibcon#enter sib2, iclass 38, count 2 2006.257.11:54:34.37#ibcon#flushed, iclass 38, count 2 2006.257.11:54:34.37#ibcon#about to write, iclass 38, count 2 2006.257.11:54:34.37#ibcon#wrote, iclass 38, count 2 2006.257.11:54:34.37#ibcon#about to read 3, iclass 38, count 2 2006.257.11:54:34.40#ibcon#read 3, iclass 38, count 2 2006.257.11:54:34.40#ibcon#about to read 4, iclass 38, count 2 2006.257.11:54:34.40#ibcon#read 4, iclass 38, count 2 2006.257.11:54:34.40#ibcon#about to read 5, iclass 38, count 2 2006.257.11:54:34.40#ibcon#read 5, iclass 38, count 2 2006.257.11:54:34.40#ibcon#about to read 6, iclass 38, count 2 2006.257.11:54:34.40#ibcon#read 6, iclass 38, count 2 2006.257.11:54:34.40#ibcon#end of sib2, iclass 38, count 2 2006.257.11:54:34.40#ibcon#*after write, iclass 38, count 2 2006.257.11:54:34.40#ibcon#*before return 0, iclass 38, count 2 2006.257.11:54:34.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:34.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.11:54:34.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.11:54:34.40#ibcon#ireg 7 cls_cnt 0 2006.257.11:54:34.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:34.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:34.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:34.52#ibcon#enter wrdev, iclass 38, count 0 2006.257.11:54:34.52#ibcon#first serial, iclass 38, count 0 2006.257.11:54:34.52#ibcon#enter sib2, iclass 38, count 0 2006.257.11:54:34.52#ibcon#flushed, iclass 38, count 0 2006.257.11:54:34.52#ibcon#about to write, iclass 38, count 0 2006.257.11:54:34.52#ibcon#wrote, iclass 38, count 0 2006.257.11:54:34.52#ibcon#about to read 3, iclass 38, count 0 2006.257.11:54:34.54#ibcon#read 3, iclass 38, count 0 2006.257.11:54:34.54#ibcon#about to read 4, iclass 38, count 0 2006.257.11:54:34.54#ibcon#read 4, iclass 38, count 0 2006.257.11:54:34.54#ibcon#about to read 5, iclass 38, count 0 2006.257.11:54:34.54#ibcon#read 5, iclass 38, count 0 2006.257.11:54:34.54#ibcon#about to read 6, iclass 38, count 0 2006.257.11:54:34.54#ibcon#read 6, iclass 38, count 0 2006.257.11:54:34.54#ibcon#end of sib2, iclass 38, count 0 2006.257.11:54:34.54#ibcon#*mode == 0, iclass 38, count 0 2006.257.11:54:34.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.11:54:34.54#ibcon#[27=USB\r\n] 2006.257.11:54:34.54#ibcon#*before write, iclass 38, count 0 2006.257.11:54:34.54#ibcon#enter sib2, iclass 38, count 0 2006.257.11:54:34.54#ibcon#flushed, iclass 38, count 0 2006.257.11:54:34.54#ibcon#about to write, iclass 38, count 0 2006.257.11:54:34.54#ibcon#wrote, iclass 38, count 0 2006.257.11:54:34.54#ibcon#about to read 3, iclass 38, count 0 2006.257.11:54:34.57#ibcon#read 3, iclass 38, count 0 2006.257.11:54:34.57#ibcon#about to read 4, iclass 38, count 0 2006.257.11:54:34.57#ibcon#read 4, iclass 38, count 0 2006.257.11:54:34.57#ibcon#about to read 5, iclass 38, count 0 2006.257.11:54:34.57#ibcon#read 5, iclass 38, count 0 2006.257.11:54:34.57#ibcon#about to read 6, iclass 38, count 0 2006.257.11:54:34.57#ibcon#read 6, iclass 38, count 0 2006.257.11:54:34.57#ibcon#end of sib2, iclass 38, count 0 2006.257.11:54:34.57#ibcon#*after write, iclass 38, count 0 2006.257.11:54:34.57#ibcon#*before return 0, iclass 38, count 0 2006.257.11:54:34.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:34.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.11:54:34.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.11:54:34.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.11:54:34.57$vck44/vabw=wide 2006.257.11:54:34.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.11:54:34.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.11:54:34.57#ibcon#ireg 8 cls_cnt 0 2006.257.11:54:34.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:34.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:34.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:34.57#ibcon#enter wrdev, iclass 40, count 0 2006.257.11:54:34.57#ibcon#first serial, iclass 40, count 0 2006.257.11:54:34.57#ibcon#enter sib2, iclass 40, count 0 2006.257.11:54:34.57#ibcon#flushed, iclass 40, count 0 2006.257.11:54:34.57#ibcon#about to write, iclass 40, count 0 2006.257.11:54:34.57#ibcon#wrote, iclass 40, count 0 2006.257.11:54:34.57#ibcon#about to read 3, iclass 40, count 0 2006.257.11:54:34.59#ibcon#read 3, iclass 40, count 0 2006.257.11:54:34.59#ibcon#about to read 4, iclass 40, count 0 2006.257.11:54:34.59#ibcon#read 4, iclass 40, count 0 2006.257.11:54:34.59#ibcon#about to read 5, iclass 40, count 0 2006.257.11:54:34.59#ibcon#read 5, iclass 40, count 0 2006.257.11:54:34.59#ibcon#about to read 6, iclass 40, count 0 2006.257.11:54:34.59#ibcon#read 6, iclass 40, count 0 2006.257.11:54:34.59#ibcon#end of sib2, iclass 40, count 0 2006.257.11:54:34.59#ibcon#*mode == 0, iclass 40, count 0 2006.257.11:54:34.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.11:54:34.59#ibcon#[25=BW32\r\n] 2006.257.11:54:34.59#ibcon#*before write, iclass 40, count 0 2006.257.11:54:34.59#ibcon#enter sib2, iclass 40, count 0 2006.257.11:54:34.59#ibcon#flushed, iclass 40, count 0 2006.257.11:54:34.59#ibcon#about to write, iclass 40, count 0 2006.257.11:54:34.59#ibcon#wrote, iclass 40, count 0 2006.257.11:54:34.59#ibcon#about to read 3, iclass 40, count 0 2006.257.11:54:34.62#ibcon#read 3, iclass 40, count 0 2006.257.11:54:34.62#ibcon#about to read 4, iclass 40, count 0 2006.257.11:54:34.62#ibcon#read 4, iclass 40, count 0 2006.257.11:54:34.62#ibcon#about to read 5, iclass 40, count 0 2006.257.11:54:34.62#ibcon#read 5, iclass 40, count 0 2006.257.11:54:34.62#ibcon#about to read 6, iclass 40, count 0 2006.257.11:54:34.62#ibcon#read 6, iclass 40, count 0 2006.257.11:54:34.62#ibcon#end of sib2, iclass 40, count 0 2006.257.11:54:34.62#ibcon#*after write, iclass 40, count 0 2006.257.11:54:34.62#ibcon#*before return 0, iclass 40, count 0 2006.257.11:54:34.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:34.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.11:54:34.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.11:54:34.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.11:54:34.62$vck44/vbbw=wide 2006.257.11:54:34.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.11:54:34.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.11:54:34.62#ibcon#ireg 8 cls_cnt 0 2006.257.11:54:34.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:54:34.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:54:34.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:54:34.69#ibcon#enter wrdev, iclass 4, count 0 2006.257.11:54:34.69#ibcon#first serial, iclass 4, count 0 2006.257.11:54:34.69#ibcon#enter sib2, iclass 4, count 0 2006.257.11:54:34.69#ibcon#flushed, iclass 4, count 0 2006.257.11:54:34.69#ibcon#about to write, iclass 4, count 0 2006.257.11:54:34.69#ibcon#wrote, iclass 4, count 0 2006.257.11:54:34.69#ibcon#about to read 3, iclass 4, count 0 2006.257.11:54:34.71#ibcon#read 3, iclass 4, count 0 2006.257.11:54:34.71#ibcon#about to read 4, iclass 4, count 0 2006.257.11:54:34.71#ibcon#read 4, iclass 4, count 0 2006.257.11:54:34.71#ibcon#about to read 5, iclass 4, count 0 2006.257.11:54:34.71#ibcon#read 5, iclass 4, count 0 2006.257.11:54:34.71#ibcon#about to read 6, iclass 4, count 0 2006.257.11:54:34.71#ibcon#read 6, iclass 4, count 0 2006.257.11:54:34.71#ibcon#end of sib2, iclass 4, count 0 2006.257.11:54:34.71#ibcon#*mode == 0, iclass 4, count 0 2006.257.11:54:34.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.11:54:34.71#ibcon#[27=BW32\r\n] 2006.257.11:54:34.71#ibcon#*before write, iclass 4, count 0 2006.257.11:54:34.71#ibcon#enter sib2, iclass 4, count 0 2006.257.11:54:34.71#ibcon#flushed, iclass 4, count 0 2006.257.11:54:34.71#ibcon#about to write, iclass 4, count 0 2006.257.11:54:34.71#ibcon#wrote, iclass 4, count 0 2006.257.11:54:34.71#ibcon#about to read 3, iclass 4, count 0 2006.257.11:54:34.74#ibcon#read 3, iclass 4, count 0 2006.257.11:54:34.74#ibcon#about to read 4, iclass 4, count 0 2006.257.11:54:34.74#ibcon#read 4, iclass 4, count 0 2006.257.11:54:34.74#ibcon#about to read 5, iclass 4, count 0 2006.257.11:54:34.74#ibcon#read 5, iclass 4, count 0 2006.257.11:54:34.74#ibcon#about to read 6, iclass 4, count 0 2006.257.11:54:34.74#ibcon#read 6, iclass 4, count 0 2006.257.11:54:34.74#ibcon#end of sib2, iclass 4, count 0 2006.257.11:54:34.74#ibcon#*after write, iclass 4, count 0 2006.257.11:54:34.74#ibcon#*before return 0, iclass 4, count 0 2006.257.11:54:34.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:54:34.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.11:54:34.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.11:54:34.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.11:54:34.74$setupk4/ifdk4 2006.257.11:54:34.74$ifdk4/lo= 2006.257.11:54:34.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:54:34.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:54:34.74$ifdk4/patch= 2006.257.11:54:34.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:54:34.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:54:34.74$setupk4/!*+20s 2006.257.11:54:36.00#abcon#<5=/14 1.6 3.9 18.20 951013.9\r\n> 2006.257.11:54:36.02#abcon#{5=INTERFACE CLEAR} 2006.257.11:54:36.08#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:54:46.17#abcon#<5=/14 1.6 3.9 18.20 951013.9\r\n> 2006.257.11:54:46.19#abcon#{5=INTERFACE CLEAR} 2006.257.11:54:46.25#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:54:49.23$setupk4/"tpicd 2006.257.11:54:49.23$setupk4/echo=off 2006.257.11:54:49.23$setupk4/xlog=off 2006.257.11:54:49.23:!2006.257.11:56:07 2006.257.11:55:01.14#trakl#Source acquired 2006.257.11:55:03.14#flagr#flagr/antenna,acquired 2006.257.11:56:07.00:preob 2006.257.11:56:07.13/onsource/TRACKING 2006.257.11:56:07.13:!2006.257.11:56:17 2006.257.11:56:17.00:"tape 2006.257.11:56:17.00:"st=record 2006.257.11:56:17.00:data_valid=on 2006.257.11:56:17.00:midob 2006.257.11:56:18.13/onsource/TRACKING 2006.257.11:56:18.13/wx/18.20,1013.9,95 2006.257.11:56:18.28/cable/+6.4800E-03 2006.257.11:56:19.37/va/01,08,usb,yes,31,33 2006.257.11:56:19.37/va/02,07,usb,yes,33,34 2006.257.11:56:19.37/va/03,08,usb,yes,30,31 2006.257.11:56:19.37/va/04,07,usb,yes,34,36 2006.257.11:56:19.37/va/05,04,usb,yes,31,31 2006.257.11:56:19.37/va/06,04,usb,yes,34,34 2006.257.11:56:19.37/va/07,04,usb,yes,35,35 2006.257.11:56:19.37/va/08,04,usb,yes,29,36 2006.257.11:56:19.60/valo/01,524.99,yes,locked 2006.257.11:56:19.60/valo/02,534.99,yes,locked 2006.257.11:56:19.60/valo/03,564.99,yes,locked 2006.257.11:56:19.60/valo/04,624.99,yes,locked 2006.257.11:56:19.60/valo/05,734.99,yes,locked 2006.257.11:56:19.60/valo/06,814.99,yes,locked 2006.257.11:56:19.60/valo/07,864.99,yes,locked 2006.257.11:56:19.60/valo/08,884.99,yes,locked 2006.257.11:56:20.69/vb/01,04,usb,yes,31,29 2006.257.11:56:20.69/vb/02,05,usb,yes,29,29 2006.257.11:56:20.69/vb/03,04,usb,yes,30,33 2006.257.11:56:20.69/vb/04,05,usb,yes,31,30 2006.257.11:56:20.69/vb/05,04,usb,yes,27,29 2006.257.11:56:20.69/vb/06,04,usb,yes,32,28 2006.257.11:56:20.69/vb/07,04,usb,yes,31,31 2006.257.11:56:20.69/vb/08,04,usb,yes,29,32 2006.257.11:56:20.92/vblo/01,629.99,yes,locked 2006.257.11:56:20.92/vblo/02,634.99,yes,locked 2006.257.11:56:20.92/vblo/03,649.99,yes,locked 2006.257.11:56:20.92/vblo/04,679.99,yes,locked 2006.257.11:56:20.92/vblo/05,709.99,yes,locked 2006.257.11:56:20.92/vblo/06,719.99,yes,locked 2006.257.11:56:20.92/vblo/07,734.99,yes,locked 2006.257.11:56:20.92/vblo/08,744.99,yes,locked 2006.257.11:56:21.07/vabw/8 2006.257.11:56:21.22/vbbw/8 2006.257.11:56:21.31/xfe/off,on,15.5 2006.257.11:56:21.68/ifatt/23,28,28,28 2006.257.11:56:22.07/fmout-gps/S +4.59E-07 2006.257.11:56:22.11:!2006.257.11:57:17 2006.257.11:57:17.00:data_valid=off 2006.257.11:57:17.00:"et 2006.257.11:57:17.00:!+3s 2006.257.11:57:20.01:"tape 2006.257.11:57:20.01:postob 2006.257.11:57:20.20/cable/+6.4802E-03 2006.257.11:57:20.20/wx/18.21,1013.9,95 2006.257.11:57:21.08/fmout-gps/S +4.58E-07 2006.257.11:57:21.08:scan_name=257-1200,jd0609,40 2006.257.11:57:21.08:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.11:57:21.13#flagr#flagr/antenna,new-source 2006.257.11:57:22.13:checkk5 2006.257.11:57:22.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.11:57:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.257.11:57:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.257.11:57:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.257.11:57:24.09/chk_obsdata//k5ts1/T2571156??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.11:57:24.49/chk_obsdata//k5ts2/T2571156??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.11:57:24.88/chk_obsdata//k5ts3/T2571156??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.11:57:25.29/chk_obsdata//k5ts4/T2571156??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.11:57:26.01/k5log//k5ts1_log_newline 2006.257.11:57:26.74/k5log//k5ts2_log_newline 2006.257.11:57:27.44/k5log//k5ts3_log_newline 2006.257.11:57:28.16/k5log//k5ts4_log_newline 2006.257.11:57:28.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.11:57:28.18:setupk4=1 2006.257.11:57:28.19$setupk4/echo=on 2006.257.11:57:28.19$setupk4/pcalon 2006.257.11:57:28.19$pcalon/"no phase cal control is implemented here 2006.257.11:57:28.19$setupk4/"tpicd=stop 2006.257.11:57:28.19$setupk4/"rec=synch_on 2006.257.11:57:28.19$setupk4/"rec_mode=128 2006.257.11:57:28.19$setupk4/!* 2006.257.11:57:28.19$setupk4/recpk4 2006.257.11:57:28.19$recpk4/recpatch= 2006.257.11:57:28.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.11:57:28.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.11:57:28.19$setupk4/vck44 2006.257.11:57:28.19$vck44/valo=1,524.99 2006.257.11:57:28.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.11:57:28.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.11:57:28.19#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:28.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:28.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:28.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:28.19#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:57:28.20#ibcon#first serial, iclass 5, count 0 2006.257.11:57:28.20#ibcon#enter sib2, iclass 5, count 0 2006.257.11:57:28.20#ibcon#flushed, iclass 5, count 0 2006.257.11:57:28.20#ibcon#about to write, iclass 5, count 0 2006.257.11:57:28.20#ibcon#wrote, iclass 5, count 0 2006.257.11:57:28.20#ibcon#about to read 3, iclass 5, count 0 2006.257.11:57:28.21#ibcon#read 3, iclass 5, count 0 2006.257.11:57:28.21#ibcon#about to read 4, iclass 5, count 0 2006.257.11:57:28.21#ibcon#read 4, iclass 5, count 0 2006.257.11:57:28.21#ibcon#about to read 5, iclass 5, count 0 2006.257.11:57:28.21#ibcon#read 5, iclass 5, count 0 2006.257.11:57:28.21#ibcon#about to read 6, iclass 5, count 0 2006.257.11:57:28.21#ibcon#read 6, iclass 5, count 0 2006.257.11:57:28.21#ibcon#end of sib2, iclass 5, count 0 2006.257.11:57:28.21#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:57:28.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:57:28.21#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.11:57:28.21#ibcon#*before write, iclass 5, count 0 2006.257.11:57:28.21#ibcon#enter sib2, iclass 5, count 0 2006.257.11:57:28.21#ibcon#flushed, iclass 5, count 0 2006.257.11:57:28.21#ibcon#about to write, iclass 5, count 0 2006.257.11:57:28.21#ibcon#wrote, iclass 5, count 0 2006.257.11:57:28.21#ibcon#about to read 3, iclass 5, count 0 2006.257.11:57:28.26#ibcon#read 3, iclass 5, count 0 2006.257.11:57:28.26#ibcon#about to read 4, iclass 5, count 0 2006.257.11:57:28.26#ibcon#read 4, iclass 5, count 0 2006.257.11:57:28.26#ibcon#about to read 5, iclass 5, count 0 2006.257.11:57:28.26#ibcon#read 5, iclass 5, count 0 2006.257.11:57:28.26#ibcon#about to read 6, iclass 5, count 0 2006.257.11:57:28.26#ibcon#read 6, iclass 5, count 0 2006.257.11:57:28.26#ibcon#end of sib2, iclass 5, count 0 2006.257.11:57:28.26#ibcon#*after write, iclass 5, count 0 2006.257.11:57:28.26#ibcon#*before return 0, iclass 5, count 0 2006.257.11:57:28.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:28.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:28.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:57:28.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:57:28.26$vck44/va=1,8 2006.257.11:57:28.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.11:57:28.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.11:57:28.26#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:28.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:28.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:28.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:28.26#ibcon#enter wrdev, iclass 7, count 2 2006.257.11:57:28.26#ibcon#first serial, iclass 7, count 2 2006.257.11:57:28.26#ibcon#enter sib2, iclass 7, count 2 2006.257.11:57:28.26#ibcon#flushed, iclass 7, count 2 2006.257.11:57:28.26#ibcon#about to write, iclass 7, count 2 2006.257.11:57:28.26#ibcon#wrote, iclass 7, count 2 2006.257.11:57:28.26#ibcon#about to read 3, iclass 7, count 2 2006.257.11:57:28.28#ibcon#read 3, iclass 7, count 2 2006.257.11:57:28.28#ibcon#about to read 4, iclass 7, count 2 2006.257.11:57:28.28#ibcon#read 4, iclass 7, count 2 2006.257.11:57:28.28#ibcon#about to read 5, iclass 7, count 2 2006.257.11:57:28.28#ibcon#read 5, iclass 7, count 2 2006.257.11:57:28.28#ibcon#about to read 6, iclass 7, count 2 2006.257.11:57:28.28#ibcon#read 6, iclass 7, count 2 2006.257.11:57:28.28#ibcon#end of sib2, iclass 7, count 2 2006.257.11:57:28.28#ibcon#*mode == 0, iclass 7, count 2 2006.257.11:57:28.28#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.11:57:28.28#ibcon#[25=AT01-08\r\n] 2006.257.11:57:28.28#ibcon#*before write, iclass 7, count 2 2006.257.11:57:28.28#ibcon#enter sib2, iclass 7, count 2 2006.257.11:57:28.28#ibcon#flushed, iclass 7, count 2 2006.257.11:57:28.28#ibcon#about to write, iclass 7, count 2 2006.257.11:57:28.28#ibcon#wrote, iclass 7, count 2 2006.257.11:57:28.28#ibcon#about to read 3, iclass 7, count 2 2006.257.11:57:28.31#ibcon#read 3, iclass 7, count 2 2006.257.11:57:28.31#ibcon#about to read 4, iclass 7, count 2 2006.257.11:57:28.31#ibcon#read 4, iclass 7, count 2 2006.257.11:57:28.31#ibcon#about to read 5, iclass 7, count 2 2006.257.11:57:28.31#ibcon#read 5, iclass 7, count 2 2006.257.11:57:28.31#ibcon#about to read 6, iclass 7, count 2 2006.257.11:57:28.31#ibcon#read 6, iclass 7, count 2 2006.257.11:57:28.31#ibcon#end of sib2, iclass 7, count 2 2006.257.11:57:28.31#ibcon#*after write, iclass 7, count 2 2006.257.11:57:28.31#ibcon#*before return 0, iclass 7, count 2 2006.257.11:57:28.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:28.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:28.31#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.11:57:28.31#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:28.31#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:28.43#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:28.43#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:28.43#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:57:28.43#ibcon#first serial, iclass 7, count 0 2006.257.11:57:28.43#ibcon#enter sib2, iclass 7, count 0 2006.257.11:57:28.43#ibcon#flushed, iclass 7, count 0 2006.257.11:57:28.43#ibcon#about to write, iclass 7, count 0 2006.257.11:57:28.43#ibcon#wrote, iclass 7, count 0 2006.257.11:57:28.43#ibcon#about to read 3, iclass 7, count 0 2006.257.11:57:28.45#ibcon#read 3, iclass 7, count 0 2006.257.11:57:28.45#ibcon#about to read 4, iclass 7, count 0 2006.257.11:57:28.45#ibcon#read 4, iclass 7, count 0 2006.257.11:57:28.45#ibcon#about to read 5, iclass 7, count 0 2006.257.11:57:28.45#ibcon#read 5, iclass 7, count 0 2006.257.11:57:28.45#ibcon#about to read 6, iclass 7, count 0 2006.257.11:57:28.45#ibcon#read 6, iclass 7, count 0 2006.257.11:57:28.45#ibcon#end of sib2, iclass 7, count 0 2006.257.11:57:28.45#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:57:28.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:57:28.45#ibcon#[25=USB\r\n] 2006.257.11:57:28.45#ibcon#*before write, iclass 7, count 0 2006.257.11:57:28.45#ibcon#enter sib2, iclass 7, count 0 2006.257.11:57:28.45#ibcon#flushed, iclass 7, count 0 2006.257.11:57:28.45#ibcon#about to write, iclass 7, count 0 2006.257.11:57:28.45#ibcon#wrote, iclass 7, count 0 2006.257.11:57:28.45#ibcon#about to read 3, iclass 7, count 0 2006.257.11:57:28.48#ibcon#read 3, iclass 7, count 0 2006.257.11:57:28.48#ibcon#about to read 4, iclass 7, count 0 2006.257.11:57:28.48#ibcon#read 4, iclass 7, count 0 2006.257.11:57:28.48#ibcon#about to read 5, iclass 7, count 0 2006.257.11:57:28.48#ibcon#read 5, iclass 7, count 0 2006.257.11:57:28.48#ibcon#about to read 6, iclass 7, count 0 2006.257.11:57:28.48#ibcon#read 6, iclass 7, count 0 2006.257.11:57:28.48#ibcon#end of sib2, iclass 7, count 0 2006.257.11:57:28.48#ibcon#*after write, iclass 7, count 0 2006.257.11:57:28.48#ibcon#*before return 0, iclass 7, count 0 2006.257.11:57:28.48#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:28.48#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:28.48#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:57:28.48#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:57:28.48$vck44/valo=2,534.99 2006.257.11:57:28.48#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.11:57:28.48#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.11:57:28.48#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:28.48#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:28.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:28.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:28.48#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:57:28.48#ibcon#first serial, iclass 11, count 0 2006.257.11:57:28.48#ibcon#enter sib2, iclass 11, count 0 2006.257.11:57:28.48#ibcon#flushed, iclass 11, count 0 2006.257.11:57:28.48#ibcon#about to write, iclass 11, count 0 2006.257.11:57:28.48#ibcon#wrote, iclass 11, count 0 2006.257.11:57:28.48#ibcon#about to read 3, iclass 11, count 0 2006.257.11:57:28.50#ibcon#read 3, iclass 11, count 0 2006.257.11:57:28.50#ibcon#about to read 4, iclass 11, count 0 2006.257.11:57:28.50#ibcon#read 4, iclass 11, count 0 2006.257.11:57:28.50#ibcon#about to read 5, iclass 11, count 0 2006.257.11:57:28.50#ibcon#read 5, iclass 11, count 0 2006.257.11:57:28.50#ibcon#about to read 6, iclass 11, count 0 2006.257.11:57:28.50#ibcon#read 6, iclass 11, count 0 2006.257.11:57:28.50#ibcon#end of sib2, iclass 11, count 0 2006.257.11:57:28.50#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:57:28.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:57:28.50#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.11:57:28.50#ibcon#*before write, iclass 11, count 0 2006.257.11:57:28.50#ibcon#enter sib2, iclass 11, count 0 2006.257.11:57:28.50#ibcon#flushed, iclass 11, count 0 2006.257.11:57:28.50#ibcon#about to write, iclass 11, count 0 2006.257.11:57:28.50#ibcon#wrote, iclass 11, count 0 2006.257.11:57:28.50#ibcon#about to read 3, iclass 11, count 0 2006.257.11:57:28.54#ibcon#read 3, iclass 11, count 0 2006.257.11:57:28.54#ibcon#about to read 4, iclass 11, count 0 2006.257.11:57:28.54#ibcon#read 4, iclass 11, count 0 2006.257.11:57:28.54#ibcon#about to read 5, iclass 11, count 0 2006.257.11:57:28.54#ibcon#read 5, iclass 11, count 0 2006.257.11:57:28.54#ibcon#about to read 6, iclass 11, count 0 2006.257.11:57:28.54#ibcon#read 6, iclass 11, count 0 2006.257.11:57:28.54#ibcon#end of sib2, iclass 11, count 0 2006.257.11:57:28.54#ibcon#*after write, iclass 11, count 0 2006.257.11:57:28.54#ibcon#*before return 0, iclass 11, count 0 2006.257.11:57:28.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:28.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:28.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:57:28.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:57:28.54$vck44/va=2,7 2006.257.11:57:28.54#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.11:57:28.54#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.11:57:28.54#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:28.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:28.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:28.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:28.60#ibcon#enter wrdev, iclass 13, count 2 2006.257.11:57:28.60#ibcon#first serial, iclass 13, count 2 2006.257.11:57:28.60#ibcon#enter sib2, iclass 13, count 2 2006.257.11:57:28.60#ibcon#flushed, iclass 13, count 2 2006.257.11:57:28.60#ibcon#about to write, iclass 13, count 2 2006.257.11:57:28.60#ibcon#wrote, iclass 13, count 2 2006.257.11:57:28.60#ibcon#about to read 3, iclass 13, count 2 2006.257.11:57:28.62#ibcon#read 3, iclass 13, count 2 2006.257.11:57:28.62#ibcon#about to read 4, iclass 13, count 2 2006.257.11:57:28.62#ibcon#read 4, iclass 13, count 2 2006.257.11:57:28.62#ibcon#about to read 5, iclass 13, count 2 2006.257.11:57:28.62#ibcon#read 5, iclass 13, count 2 2006.257.11:57:28.62#ibcon#about to read 6, iclass 13, count 2 2006.257.11:57:28.62#ibcon#read 6, iclass 13, count 2 2006.257.11:57:28.62#ibcon#end of sib2, iclass 13, count 2 2006.257.11:57:28.62#ibcon#*mode == 0, iclass 13, count 2 2006.257.11:57:28.62#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.11:57:28.62#ibcon#[25=AT02-07\r\n] 2006.257.11:57:28.62#ibcon#*before write, iclass 13, count 2 2006.257.11:57:28.62#ibcon#enter sib2, iclass 13, count 2 2006.257.11:57:28.62#ibcon#flushed, iclass 13, count 2 2006.257.11:57:28.62#ibcon#about to write, iclass 13, count 2 2006.257.11:57:28.62#ibcon#wrote, iclass 13, count 2 2006.257.11:57:28.62#ibcon#about to read 3, iclass 13, count 2 2006.257.11:57:28.65#ibcon#read 3, iclass 13, count 2 2006.257.11:57:28.65#ibcon#about to read 4, iclass 13, count 2 2006.257.11:57:28.65#ibcon#read 4, iclass 13, count 2 2006.257.11:57:28.65#ibcon#about to read 5, iclass 13, count 2 2006.257.11:57:28.65#ibcon#read 5, iclass 13, count 2 2006.257.11:57:28.65#ibcon#about to read 6, iclass 13, count 2 2006.257.11:57:28.65#ibcon#read 6, iclass 13, count 2 2006.257.11:57:28.65#ibcon#end of sib2, iclass 13, count 2 2006.257.11:57:28.65#ibcon#*after write, iclass 13, count 2 2006.257.11:57:28.65#ibcon#*before return 0, iclass 13, count 2 2006.257.11:57:28.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:28.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:28.65#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.11:57:28.65#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:28.65#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:28.77#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:28.77#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:28.77#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:57:28.77#ibcon#first serial, iclass 13, count 0 2006.257.11:57:28.77#ibcon#enter sib2, iclass 13, count 0 2006.257.11:57:28.77#ibcon#flushed, iclass 13, count 0 2006.257.11:57:28.77#ibcon#about to write, iclass 13, count 0 2006.257.11:57:28.77#ibcon#wrote, iclass 13, count 0 2006.257.11:57:28.77#ibcon#about to read 3, iclass 13, count 0 2006.257.11:57:28.79#ibcon#read 3, iclass 13, count 0 2006.257.11:57:28.79#ibcon#about to read 4, iclass 13, count 0 2006.257.11:57:28.79#ibcon#read 4, iclass 13, count 0 2006.257.11:57:28.79#ibcon#about to read 5, iclass 13, count 0 2006.257.11:57:28.79#ibcon#read 5, iclass 13, count 0 2006.257.11:57:28.79#ibcon#about to read 6, iclass 13, count 0 2006.257.11:57:28.79#ibcon#read 6, iclass 13, count 0 2006.257.11:57:28.79#ibcon#end of sib2, iclass 13, count 0 2006.257.11:57:28.79#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:57:28.79#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:57:28.79#ibcon#[25=USB\r\n] 2006.257.11:57:28.79#ibcon#*before write, iclass 13, count 0 2006.257.11:57:28.79#ibcon#enter sib2, iclass 13, count 0 2006.257.11:57:28.79#ibcon#flushed, iclass 13, count 0 2006.257.11:57:28.79#ibcon#about to write, iclass 13, count 0 2006.257.11:57:28.79#ibcon#wrote, iclass 13, count 0 2006.257.11:57:28.79#ibcon#about to read 3, iclass 13, count 0 2006.257.11:57:28.82#ibcon#read 3, iclass 13, count 0 2006.257.11:57:28.82#ibcon#about to read 4, iclass 13, count 0 2006.257.11:57:28.82#ibcon#read 4, iclass 13, count 0 2006.257.11:57:28.82#ibcon#about to read 5, iclass 13, count 0 2006.257.11:57:28.82#ibcon#read 5, iclass 13, count 0 2006.257.11:57:28.82#ibcon#about to read 6, iclass 13, count 0 2006.257.11:57:28.82#ibcon#read 6, iclass 13, count 0 2006.257.11:57:28.82#ibcon#end of sib2, iclass 13, count 0 2006.257.11:57:28.82#ibcon#*after write, iclass 13, count 0 2006.257.11:57:28.82#ibcon#*before return 0, iclass 13, count 0 2006.257.11:57:28.82#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:28.82#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:28.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:57:28.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:57:28.82$vck44/valo=3,564.99 2006.257.11:57:28.82#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.11:57:28.82#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.11:57:28.82#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:28.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:28.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:28.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:28.82#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:57:28.82#ibcon#first serial, iclass 15, count 0 2006.257.11:57:28.82#ibcon#enter sib2, iclass 15, count 0 2006.257.11:57:28.82#ibcon#flushed, iclass 15, count 0 2006.257.11:57:28.82#ibcon#about to write, iclass 15, count 0 2006.257.11:57:28.82#ibcon#wrote, iclass 15, count 0 2006.257.11:57:28.82#ibcon#about to read 3, iclass 15, count 0 2006.257.11:57:28.84#ibcon#read 3, iclass 15, count 0 2006.257.11:57:28.84#ibcon#about to read 4, iclass 15, count 0 2006.257.11:57:28.84#ibcon#read 4, iclass 15, count 0 2006.257.11:57:28.84#ibcon#about to read 5, iclass 15, count 0 2006.257.11:57:28.84#ibcon#read 5, iclass 15, count 0 2006.257.11:57:28.84#ibcon#about to read 6, iclass 15, count 0 2006.257.11:57:28.84#ibcon#read 6, iclass 15, count 0 2006.257.11:57:28.84#ibcon#end of sib2, iclass 15, count 0 2006.257.11:57:28.84#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:57:28.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:57:28.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.11:57:28.84#ibcon#*before write, iclass 15, count 0 2006.257.11:57:28.84#ibcon#enter sib2, iclass 15, count 0 2006.257.11:57:28.84#ibcon#flushed, iclass 15, count 0 2006.257.11:57:28.84#ibcon#about to write, iclass 15, count 0 2006.257.11:57:28.84#ibcon#wrote, iclass 15, count 0 2006.257.11:57:28.84#ibcon#about to read 3, iclass 15, count 0 2006.257.11:57:28.88#ibcon#read 3, iclass 15, count 0 2006.257.11:57:28.88#ibcon#about to read 4, iclass 15, count 0 2006.257.11:57:28.88#ibcon#read 4, iclass 15, count 0 2006.257.11:57:28.88#ibcon#about to read 5, iclass 15, count 0 2006.257.11:57:28.88#ibcon#read 5, iclass 15, count 0 2006.257.11:57:28.88#ibcon#about to read 6, iclass 15, count 0 2006.257.11:57:28.88#ibcon#read 6, iclass 15, count 0 2006.257.11:57:28.88#ibcon#end of sib2, iclass 15, count 0 2006.257.11:57:28.88#ibcon#*after write, iclass 15, count 0 2006.257.11:57:28.88#ibcon#*before return 0, iclass 15, count 0 2006.257.11:57:28.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:28.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:28.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:57:28.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:57:28.88$vck44/va=3,8 2006.257.11:57:28.88#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.11:57:28.88#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.11:57:28.88#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:28.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:28.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:28.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:28.94#ibcon#enter wrdev, iclass 17, count 2 2006.257.11:57:28.94#ibcon#first serial, iclass 17, count 2 2006.257.11:57:28.94#ibcon#enter sib2, iclass 17, count 2 2006.257.11:57:28.94#ibcon#flushed, iclass 17, count 2 2006.257.11:57:28.94#ibcon#about to write, iclass 17, count 2 2006.257.11:57:28.94#ibcon#wrote, iclass 17, count 2 2006.257.11:57:28.94#ibcon#about to read 3, iclass 17, count 2 2006.257.11:57:28.96#ibcon#read 3, iclass 17, count 2 2006.257.11:57:28.96#ibcon#about to read 4, iclass 17, count 2 2006.257.11:57:28.96#ibcon#read 4, iclass 17, count 2 2006.257.11:57:28.96#ibcon#about to read 5, iclass 17, count 2 2006.257.11:57:28.96#ibcon#read 5, iclass 17, count 2 2006.257.11:57:28.96#ibcon#about to read 6, iclass 17, count 2 2006.257.11:57:28.96#ibcon#read 6, iclass 17, count 2 2006.257.11:57:28.96#ibcon#end of sib2, iclass 17, count 2 2006.257.11:57:28.96#ibcon#*mode == 0, iclass 17, count 2 2006.257.11:57:28.96#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.11:57:28.96#ibcon#[25=AT03-08\r\n] 2006.257.11:57:28.96#ibcon#*before write, iclass 17, count 2 2006.257.11:57:28.96#ibcon#enter sib2, iclass 17, count 2 2006.257.11:57:28.96#ibcon#flushed, iclass 17, count 2 2006.257.11:57:28.96#ibcon#about to write, iclass 17, count 2 2006.257.11:57:28.96#ibcon#wrote, iclass 17, count 2 2006.257.11:57:28.96#ibcon#about to read 3, iclass 17, count 2 2006.257.11:57:28.99#ibcon#read 3, iclass 17, count 2 2006.257.11:57:28.99#ibcon#about to read 4, iclass 17, count 2 2006.257.11:57:28.99#ibcon#read 4, iclass 17, count 2 2006.257.11:57:28.99#ibcon#about to read 5, iclass 17, count 2 2006.257.11:57:28.99#ibcon#read 5, iclass 17, count 2 2006.257.11:57:28.99#ibcon#about to read 6, iclass 17, count 2 2006.257.11:57:28.99#ibcon#read 6, iclass 17, count 2 2006.257.11:57:28.99#ibcon#end of sib2, iclass 17, count 2 2006.257.11:57:28.99#ibcon#*after write, iclass 17, count 2 2006.257.11:57:28.99#ibcon#*before return 0, iclass 17, count 2 2006.257.11:57:28.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:28.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:28.99#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.11:57:28.99#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:28.99#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:29.03#abcon#<5=/14 1.6 3.9 18.21 951013.9\r\n> 2006.257.11:57:29.05#abcon#{5=INTERFACE CLEAR} 2006.257.11:57:29.11#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:57:29.11#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:29.11#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:29.11#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:57:29.11#ibcon#first serial, iclass 17, count 0 2006.257.11:57:29.11#ibcon#enter sib2, iclass 17, count 0 2006.257.11:57:29.11#ibcon#flushed, iclass 17, count 0 2006.257.11:57:29.11#ibcon#about to write, iclass 17, count 0 2006.257.11:57:29.11#ibcon#wrote, iclass 17, count 0 2006.257.11:57:29.11#ibcon#about to read 3, iclass 17, count 0 2006.257.11:57:29.13#ibcon#read 3, iclass 17, count 0 2006.257.11:57:29.13#ibcon#about to read 4, iclass 17, count 0 2006.257.11:57:29.13#ibcon#read 4, iclass 17, count 0 2006.257.11:57:29.13#ibcon#about to read 5, iclass 17, count 0 2006.257.11:57:29.13#ibcon#read 5, iclass 17, count 0 2006.257.11:57:29.13#ibcon#about to read 6, iclass 17, count 0 2006.257.11:57:29.13#ibcon#read 6, iclass 17, count 0 2006.257.11:57:29.13#ibcon#end of sib2, iclass 17, count 0 2006.257.11:57:29.13#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:57:29.13#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:57:29.13#ibcon#[25=USB\r\n] 2006.257.11:57:29.13#ibcon#*before write, iclass 17, count 0 2006.257.11:57:29.13#ibcon#enter sib2, iclass 17, count 0 2006.257.11:57:29.13#ibcon#flushed, iclass 17, count 0 2006.257.11:57:29.13#ibcon#about to write, iclass 17, count 0 2006.257.11:57:29.13#ibcon#wrote, iclass 17, count 0 2006.257.11:57:29.13#ibcon#about to read 3, iclass 17, count 0 2006.257.11:57:29.16#ibcon#read 3, iclass 17, count 0 2006.257.11:57:29.16#ibcon#about to read 4, iclass 17, count 0 2006.257.11:57:29.16#ibcon#read 4, iclass 17, count 0 2006.257.11:57:29.16#ibcon#about to read 5, iclass 17, count 0 2006.257.11:57:29.16#ibcon#read 5, iclass 17, count 0 2006.257.11:57:29.16#ibcon#about to read 6, iclass 17, count 0 2006.257.11:57:29.16#ibcon#read 6, iclass 17, count 0 2006.257.11:57:29.16#ibcon#end of sib2, iclass 17, count 0 2006.257.11:57:29.16#ibcon#*after write, iclass 17, count 0 2006.257.11:57:29.16#ibcon#*before return 0, iclass 17, count 0 2006.257.11:57:29.16#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:29.16#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:29.16#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:57:29.16#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:57:29.16$vck44/valo=4,624.99 2006.257.11:57:29.16#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.11:57:29.16#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.11:57:29.16#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:29.16#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:29.16#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:29.16#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:29.16#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:57:29.16#ibcon#first serial, iclass 23, count 0 2006.257.11:57:29.16#ibcon#enter sib2, iclass 23, count 0 2006.257.11:57:29.16#ibcon#flushed, iclass 23, count 0 2006.257.11:57:29.16#ibcon#about to write, iclass 23, count 0 2006.257.11:57:29.16#ibcon#wrote, iclass 23, count 0 2006.257.11:57:29.16#ibcon#about to read 3, iclass 23, count 0 2006.257.11:57:29.18#ibcon#read 3, iclass 23, count 0 2006.257.11:57:29.18#ibcon#about to read 4, iclass 23, count 0 2006.257.11:57:29.18#ibcon#read 4, iclass 23, count 0 2006.257.11:57:29.18#ibcon#about to read 5, iclass 23, count 0 2006.257.11:57:29.18#ibcon#read 5, iclass 23, count 0 2006.257.11:57:29.18#ibcon#about to read 6, iclass 23, count 0 2006.257.11:57:29.18#ibcon#read 6, iclass 23, count 0 2006.257.11:57:29.18#ibcon#end of sib2, iclass 23, count 0 2006.257.11:57:29.18#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:57:29.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:57:29.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.11:57:29.18#ibcon#*before write, iclass 23, count 0 2006.257.11:57:29.18#ibcon#enter sib2, iclass 23, count 0 2006.257.11:57:29.18#ibcon#flushed, iclass 23, count 0 2006.257.11:57:29.18#ibcon#about to write, iclass 23, count 0 2006.257.11:57:29.18#ibcon#wrote, iclass 23, count 0 2006.257.11:57:29.18#ibcon#about to read 3, iclass 23, count 0 2006.257.11:57:29.22#ibcon#read 3, iclass 23, count 0 2006.257.11:57:29.22#ibcon#about to read 4, iclass 23, count 0 2006.257.11:57:29.22#ibcon#read 4, iclass 23, count 0 2006.257.11:57:29.22#ibcon#about to read 5, iclass 23, count 0 2006.257.11:57:29.22#ibcon#read 5, iclass 23, count 0 2006.257.11:57:29.22#ibcon#about to read 6, iclass 23, count 0 2006.257.11:57:29.22#ibcon#read 6, iclass 23, count 0 2006.257.11:57:29.22#ibcon#end of sib2, iclass 23, count 0 2006.257.11:57:29.22#ibcon#*after write, iclass 23, count 0 2006.257.11:57:29.22#ibcon#*before return 0, iclass 23, count 0 2006.257.11:57:29.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:29.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:29.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:57:29.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:57:29.22$vck44/va=4,7 2006.257.11:57:29.22#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.11:57:29.22#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.11:57:29.22#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:29.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:29.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:29.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:29.28#ibcon#enter wrdev, iclass 25, count 2 2006.257.11:57:29.28#ibcon#first serial, iclass 25, count 2 2006.257.11:57:29.28#ibcon#enter sib2, iclass 25, count 2 2006.257.11:57:29.28#ibcon#flushed, iclass 25, count 2 2006.257.11:57:29.28#ibcon#about to write, iclass 25, count 2 2006.257.11:57:29.28#ibcon#wrote, iclass 25, count 2 2006.257.11:57:29.28#ibcon#about to read 3, iclass 25, count 2 2006.257.11:57:29.30#ibcon#read 3, iclass 25, count 2 2006.257.11:57:29.30#ibcon#about to read 4, iclass 25, count 2 2006.257.11:57:29.30#ibcon#read 4, iclass 25, count 2 2006.257.11:57:29.30#ibcon#about to read 5, iclass 25, count 2 2006.257.11:57:29.30#ibcon#read 5, iclass 25, count 2 2006.257.11:57:29.30#ibcon#about to read 6, iclass 25, count 2 2006.257.11:57:29.30#ibcon#read 6, iclass 25, count 2 2006.257.11:57:29.30#ibcon#end of sib2, iclass 25, count 2 2006.257.11:57:29.30#ibcon#*mode == 0, iclass 25, count 2 2006.257.11:57:29.30#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.11:57:29.30#ibcon#[25=AT04-07\r\n] 2006.257.11:57:29.30#ibcon#*before write, iclass 25, count 2 2006.257.11:57:29.30#ibcon#enter sib2, iclass 25, count 2 2006.257.11:57:29.30#ibcon#flushed, iclass 25, count 2 2006.257.11:57:29.30#ibcon#about to write, iclass 25, count 2 2006.257.11:57:29.30#ibcon#wrote, iclass 25, count 2 2006.257.11:57:29.30#ibcon#about to read 3, iclass 25, count 2 2006.257.11:57:29.33#ibcon#read 3, iclass 25, count 2 2006.257.11:57:29.33#ibcon#about to read 4, iclass 25, count 2 2006.257.11:57:29.33#ibcon#read 4, iclass 25, count 2 2006.257.11:57:29.33#ibcon#about to read 5, iclass 25, count 2 2006.257.11:57:29.33#ibcon#read 5, iclass 25, count 2 2006.257.11:57:29.33#ibcon#about to read 6, iclass 25, count 2 2006.257.11:57:29.33#ibcon#read 6, iclass 25, count 2 2006.257.11:57:29.33#ibcon#end of sib2, iclass 25, count 2 2006.257.11:57:29.33#ibcon#*after write, iclass 25, count 2 2006.257.11:57:29.33#ibcon#*before return 0, iclass 25, count 2 2006.257.11:57:29.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:29.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:29.33#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.11:57:29.33#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:29.33#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:29.45#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:29.45#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:29.45#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:57:29.45#ibcon#first serial, iclass 25, count 0 2006.257.11:57:29.45#ibcon#enter sib2, iclass 25, count 0 2006.257.11:57:29.45#ibcon#flushed, iclass 25, count 0 2006.257.11:57:29.45#ibcon#about to write, iclass 25, count 0 2006.257.11:57:29.45#ibcon#wrote, iclass 25, count 0 2006.257.11:57:29.45#ibcon#about to read 3, iclass 25, count 0 2006.257.11:57:29.47#ibcon#read 3, iclass 25, count 0 2006.257.11:57:29.47#ibcon#about to read 4, iclass 25, count 0 2006.257.11:57:29.47#ibcon#read 4, iclass 25, count 0 2006.257.11:57:29.47#ibcon#about to read 5, iclass 25, count 0 2006.257.11:57:29.47#ibcon#read 5, iclass 25, count 0 2006.257.11:57:29.47#ibcon#about to read 6, iclass 25, count 0 2006.257.11:57:29.47#ibcon#read 6, iclass 25, count 0 2006.257.11:57:29.47#ibcon#end of sib2, iclass 25, count 0 2006.257.11:57:29.47#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:57:29.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:57:29.47#ibcon#[25=USB\r\n] 2006.257.11:57:29.47#ibcon#*before write, iclass 25, count 0 2006.257.11:57:29.47#ibcon#enter sib2, iclass 25, count 0 2006.257.11:57:29.47#ibcon#flushed, iclass 25, count 0 2006.257.11:57:29.47#ibcon#about to write, iclass 25, count 0 2006.257.11:57:29.47#ibcon#wrote, iclass 25, count 0 2006.257.11:57:29.47#ibcon#about to read 3, iclass 25, count 0 2006.257.11:57:29.50#ibcon#read 3, iclass 25, count 0 2006.257.11:57:29.50#ibcon#about to read 4, iclass 25, count 0 2006.257.11:57:29.50#ibcon#read 4, iclass 25, count 0 2006.257.11:57:29.50#ibcon#about to read 5, iclass 25, count 0 2006.257.11:57:29.50#ibcon#read 5, iclass 25, count 0 2006.257.11:57:29.50#ibcon#about to read 6, iclass 25, count 0 2006.257.11:57:29.50#ibcon#read 6, iclass 25, count 0 2006.257.11:57:29.50#ibcon#end of sib2, iclass 25, count 0 2006.257.11:57:29.50#ibcon#*after write, iclass 25, count 0 2006.257.11:57:29.50#ibcon#*before return 0, iclass 25, count 0 2006.257.11:57:29.50#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:29.50#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:29.50#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:57:29.50#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:57:29.50$vck44/valo=5,734.99 2006.257.11:57:29.50#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.11:57:29.50#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.11:57:29.50#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:29.50#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:29.50#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:29.50#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:29.50#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:57:29.50#ibcon#first serial, iclass 27, count 0 2006.257.11:57:29.50#ibcon#enter sib2, iclass 27, count 0 2006.257.11:57:29.50#ibcon#flushed, iclass 27, count 0 2006.257.11:57:29.50#ibcon#about to write, iclass 27, count 0 2006.257.11:57:29.50#ibcon#wrote, iclass 27, count 0 2006.257.11:57:29.50#ibcon#about to read 3, iclass 27, count 0 2006.257.11:57:29.52#ibcon#read 3, iclass 27, count 0 2006.257.11:57:29.52#ibcon#about to read 4, iclass 27, count 0 2006.257.11:57:29.52#ibcon#read 4, iclass 27, count 0 2006.257.11:57:29.52#ibcon#about to read 5, iclass 27, count 0 2006.257.11:57:29.52#ibcon#read 5, iclass 27, count 0 2006.257.11:57:29.52#ibcon#about to read 6, iclass 27, count 0 2006.257.11:57:29.52#ibcon#read 6, iclass 27, count 0 2006.257.11:57:29.52#ibcon#end of sib2, iclass 27, count 0 2006.257.11:57:29.52#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:57:29.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:57:29.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.11:57:29.52#ibcon#*before write, iclass 27, count 0 2006.257.11:57:29.52#ibcon#enter sib2, iclass 27, count 0 2006.257.11:57:29.52#ibcon#flushed, iclass 27, count 0 2006.257.11:57:29.52#ibcon#about to write, iclass 27, count 0 2006.257.11:57:29.52#ibcon#wrote, iclass 27, count 0 2006.257.11:57:29.52#ibcon#about to read 3, iclass 27, count 0 2006.257.11:57:29.56#ibcon#read 3, iclass 27, count 0 2006.257.11:57:29.56#ibcon#about to read 4, iclass 27, count 0 2006.257.11:57:29.56#ibcon#read 4, iclass 27, count 0 2006.257.11:57:29.56#ibcon#about to read 5, iclass 27, count 0 2006.257.11:57:29.56#ibcon#read 5, iclass 27, count 0 2006.257.11:57:29.56#ibcon#about to read 6, iclass 27, count 0 2006.257.11:57:29.56#ibcon#read 6, iclass 27, count 0 2006.257.11:57:29.56#ibcon#end of sib2, iclass 27, count 0 2006.257.11:57:29.56#ibcon#*after write, iclass 27, count 0 2006.257.11:57:29.56#ibcon#*before return 0, iclass 27, count 0 2006.257.11:57:29.56#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:29.56#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:29.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:57:29.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:57:29.56$vck44/va=5,4 2006.257.11:57:29.56#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.11:57:29.56#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.11:57:29.56#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:29.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:29.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:29.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:29.62#ibcon#enter wrdev, iclass 29, count 2 2006.257.11:57:29.62#ibcon#first serial, iclass 29, count 2 2006.257.11:57:29.62#ibcon#enter sib2, iclass 29, count 2 2006.257.11:57:29.62#ibcon#flushed, iclass 29, count 2 2006.257.11:57:29.62#ibcon#about to write, iclass 29, count 2 2006.257.11:57:29.62#ibcon#wrote, iclass 29, count 2 2006.257.11:57:29.62#ibcon#about to read 3, iclass 29, count 2 2006.257.11:57:29.64#ibcon#read 3, iclass 29, count 2 2006.257.11:57:29.64#ibcon#about to read 4, iclass 29, count 2 2006.257.11:57:29.64#ibcon#read 4, iclass 29, count 2 2006.257.11:57:29.64#ibcon#about to read 5, iclass 29, count 2 2006.257.11:57:29.64#ibcon#read 5, iclass 29, count 2 2006.257.11:57:29.64#ibcon#about to read 6, iclass 29, count 2 2006.257.11:57:29.64#ibcon#read 6, iclass 29, count 2 2006.257.11:57:29.64#ibcon#end of sib2, iclass 29, count 2 2006.257.11:57:29.64#ibcon#*mode == 0, iclass 29, count 2 2006.257.11:57:29.64#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.11:57:29.64#ibcon#[25=AT05-04\r\n] 2006.257.11:57:29.64#ibcon#*before write, iclass 29, count 2 2006.257.11:57:29.64#ibcon#enter sib2, iclass 29, count 2 2006.257.11:57:29.64#ibcon#flushed, iclass 29, count 2 2006.257.11:57:29.64#ibcon#about to write, iclass 29, count 2 2006.257.11:57:29.64#ibcon#wrote, iclass 29, count 2 2006.257.11:57:29.64#ibcon#about to read 3, iclass 29, count 2 2006.257.11:57:29.67#ibcon#read 3, iclass 29, count 2 2006.257.11:57:29.67#ibcon#about to read 4, iclass 29, count 2 2006.257.11:57:29.67#ibcon#read 4, iclass 29, count 2 2006.257.11:57:29.67#ibcon#about to read 5, iclass 29, count 2 2006.257.11:57:29.67#ibcon#read 5, iclass 29, count 2 2006.257.11:57:29.67#ibcon#about to read 6, iclass 29, count 2 2006.257.11:57:29.67#ibcon#read 6, iclass 29, count 2 2006.257.11:57:29.67#ibcon#end of sib2, iclass 29, count 2 2006.257.11:57:29.67#ibcon#*after write, iclass 29, count 2 2006.257.11:57:29.67#ibcon#*before return 0, iclass 29, count 2 2006.257.11:57:29.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:29.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:29.67#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.11:57:29.67#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:29.67#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:29.79#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:29.79#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:29.79#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:57:29.79#ibcon#first serial, iclass 29, count 0 2006.257.11:57:29.79#ibcon#enter sib2, iclass 29, count 0 2006.257.11:57:29.79#ibcon#flushed, iclass 29, count 0 2006.257.11:57:29.79#ibcon#about to write, iclass 29, count 0 2006.257.11:57:29.79#ibcon#wrote, iclass 29, count 0 2006.257.11:57:29.79#ibcon#about to read 3, iclass 29, count 0 2006.257.11:57:29.81#ibcon#read 3, iclass 29, count 0 2006.257.11:57:29.81#ibcon#about to read 4, iclass 29, count 0 2006.257.11:57:29.81#ibcon#read 4, iclass 29, count 0 2006.257.11:57:29.81#ibcon#about to read 5, iclass 29, count 0 2006.257.11:57:29.81#ibcon#read 5, iclass 29, count 0 2006.257.11:57:29.81#ibcon#about to read 6, iclass 29, count 0 2006.257.11:57:29.81#ibcon#read 6, iclass 29, count 0 2006.257.11:57:29.81#ibcon#end of sib2, iclass 29, count 0 2006.257.11:57:29.81#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:57:29.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:57:29.81#ibcon#[25=USB\r\n] 2006.257.11:57:29.81#ibcon#*before write, iclass 29, count 0 2006.257.11:57:29.81#ibcon#enter sib2, iclass 29, count 0 2006.257.11:57:29.81#ibcon#flushed, iclass 29, count 0 2006.257.11:57:29.81#ibcon#about to write, iclass 29, count 0 2006.257.11:57:29.81#ibcon#wrote, iclass 29, count 0 2006.257.11:57:29.81#ibcon#about to read 3, iclass 29, count 0 2006.257.11:57:29.84#ibcon#read 3, iclass 29, count 0 2006.257.11:57:29.84#ibcon#about to read 4, iclass 29, count 0 2006.257.11:57:29.84#ibcon#read 4, iclass 29, count 0 2006.257.11:57:29.84#ibcon#about to read 5, iclass 29, count 0 2006.257.11:57:29.84#ibcon#read 5, iclass 29, count 0 2006.257.11:57:29.84#ibcon#about to read 6, iclass 29, count 0 2006.257.11:57:29.84#ibcon#read 6, iclass 29, count 0 2006.257.11:57:29.84#ibcon#end of sib2, iclass 29, count 0 2006.257.11:57:29.84#ibcon#*after write, iclass 29, count 0 2006.257.11:57:29.84#ibcon#*before return 0, iclass 29, count 0 2006.257.11:57:29.84#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:29.84#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:29.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:57:29.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:57:29.84$vck44/valo=6,814.99 2006.257.11:57:29.84#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.11:57:29.84#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.11:57:29.84#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:29.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:29.84#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:29.84#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:29.84#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:57:29.84#ibcon#first serial, iclass 31, count 0 2006.257.11:57:29.84#ibcon#enter sib2, iclass 31, count 0 2006.257.11:57:29.84#ibcon#flushed, iclass 31, count 0 2006.257.11:57:29.84#ibcon#about to write, iclass 31, count 0 2006.257.11:57:29.84#ibcon#wrote, iclass 31, count 0 2006.257.11:57:29.84#ibcon#about to read 3, iclass 31, count 0 2006.257.11:57:29.86#ibcon#read 3, iclass 31, count 0 2006.257.11:57:29.86#ibcon#about to read 4, iclass 31, count 0 2006.257.11:57:29.86#ibcon#read 4, iclass 31, count 0 2006.257.11:57:29.86#ibcon#about to read 5, iclass 31, count 0 2006.257.11:57:29.86#ibcon#read 5, iclass 31, count 0 2006.257.11:57:29.86#ibcon#about to read 6, iclass 31, count 0 2006.257.11:57:29.86#ibcon#read 6, iclass 31, count 0 2006.257.11:57:29.86#ibcon#end of sib2, iclass 31, count 0 2006.257.11:57:29.86#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:57:29.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:57:29.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.11:57:29.86#ibcon#*before write, iclass 31, count 0 2006.257.11:57:29.86#ibcon#enter sib2, iclass 31, count 0 2006.257.11:57:29.86#ibcon#flushed, iclass 31, count 0 2006.257.11:57:29.86#ibcon#about to write, iclass 31, count 0 2006.257.11:57:29.86#ibcon#wrote, iclass 31, count 0 2006.257.11:57:29.86#ibcon#about to read 3, iclass 31, count 0 2006.257.11:57:29.90#ibcon#read 3, iclass 31, count 0 2006.257.11:57:29.90#ibcon#about to read 4, iclass 31, count 0 2006.257.11:57:29.90#ibcon#read 4, iclass 31, count 0 2006.257.11:57:29.90#ibcon#about to read 5, iclass 31, count 0 2006.257.11:57:29.90#ibcon#read 5, iclass 31, count 0 2006.257.11:57:29.90#ibcon#about to read 6, iclass 31, count 0 2006.257.11:57:29.90#ibcon#read 6, iclass 31, count 0 2006.257.11:57:29.90#ibcon#end of sib2, iclass 31, count 0 2006.257.11:57:29.90#ibcon#*after write, iclass 31, count 0 2006.257.11:57:29.90#ibcon#*before return 0, iclass 31, count 0 2006.257.11:57:29.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:29.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:29.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:57:29.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:57:29.90$vck44/va=6,4 2006.257.11:57:29.90#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.11:57:29.90#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.11:57:29.90#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:29.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:29.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:29.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:29.96#ibcon#enter wrdev, iclass 33, count 2 2006.257.11:57:29.96#ibcon#first serial, iclass 33, count 2 2006.257.11:57:29.96#ibcon#enter sib2, iclass 33, count 2 2006.257.11:57:29.96#ibcon#flushed, iclass 33, count 2 2006.257.11:57:29.96#ibcon#about to write, iclass 33, count 2 2006.257.11:57:29.96#ibcon#wrote, iclass 33, count 2 2006.257.11:57:29.96#ibcon#about to read 3, iclass 33, count 2 2006.257.11:57:29.98#ibcon#read 3, iclass 33, count 2 2006.257.11:57:29.98#ibcon#about to read 4, iclass 33, count 2 2006.257.11:57:29.98#ibcon#read 4, iclass 33, count 2 2006.257.11:57:29.98#ibcon#about to read 5, iclass 33, count 2 2006.257.11:57:29.98#ibcon#read 5, iclass 33, count 2 2006.257.11:57:29.98#ibcon#about to read 6, iclass 33, count 2 2006.257.11:57:29.98#ibcon#read 6, iclass 33, count 2 2006.257.11:57:29.98#ibcon#end of sib2, iclass 33, count 2 2006.257.11:57:29.98#ibcon#*mode == 0, iclass 33, count 2 2006.257.11:57:29.98#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.11:57:29.98#ibcon#[25=AT06-04\r\n] 2006.257.11:57:29.98#ibcon#*before write, iclass 33, count 2 2006.257.11:57:29.98#ibcon#enter sib2, iclass 33, count 2 2006.257.11:57:29.98#ibcon#flushed, iclass 33, count 2 2006.257.11:57:29.98#ibcon#about to write, iclass 33, count 2 2006.257.11:57:29.98#ibcon#wrote, iclass 33, count 2 2006.257.11:57:29.98#ibcon#about to read 3, iclass 33, count 2 2006.257.11:57:30.01#ibcon#read 3, iclass 33, count 2 2006.257.11:57:30.01#ibcon#about to read 4, iclass 33, count 2 2006.257.11:57:30.01#ibcon#read 4, iclass 33, count 2 2006.257.11:57:30.01#ibcon#about to read 5, iclass 33, count 2 2006.257.11:57:30.01#ibcon#read 5, iclass 33, count 2 2006.257.11:57:30.01#ibcon#about to read 6, iclass 33, count 2 2006.257.11:57:30.01#ibcon#read 6, iclass 33, count 2 2006.257.11:57:30.01#ibcon#end of sib2, iclass 33, count 2 2006.257.11:57:30.01#ibcon#*after write, iclass 33, count 2 2006.257.11:57:30.01#ibcon#*before return 0, iclass 33, count 2 2006.257.11:57:30.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:30.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:30.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.11:57:30.01#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:30.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:30.13#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:30.13#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:30.13#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:57:30.13#ibcon#first serial, iclass 33, count 0 2006.257.11:57:30.13#ibcon#enter sib2, iclass 33, count 0 2006.257.11:57:30.13#ibcon#flushed, iclass 33, count 0 2006.257.11:57:30.13#ibcon#about to write, iclass 33, count 0 2006.257.11:57:30.13#ibcon#wrote, iclass 33, count 0 2006.257.11:57:30.13#ibcon#about to read 3, iclass 33, count 0 2006.257.11:57:30.15#ibcon#read 3, iclass 33, count 0 2006.257.11:57:30.15#ibcon#about to read 4, iclass 33, count 0 2006.257.11:57:30.15#ibcon#read 4, iclass 33, count 0 2006.257.11:57:30.15#ibcon#about to read 5, iclass 33, count 0 2006.257.11:57:30.15#ibcon#read 5, iclass 33, count 0 2006.257.11:57:30.15#ibcon#about to read 6, iclass 33, count 0 2006.257.11:57:30.15#ibcon#read 6, iclass 33, count 0 2006.257.11:57:30.15#ibcon#end of sib2, iclass 33, count 0 2006.257.11:57:30.15#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:57:30.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:57:30.15#ibcon#[25=USB\r\n] 2006.257.11:57:30.15#ibcon#*before write, iclass 33, count 0 2006.257.11:57:30.15#ibcon#enter sib2, iclass 33, count 0 2006.257.11:57:30.15#ibcon#flushed, iclass 33, count 0 2006.257.11:57:30.15#ibcon#about to write, iclass 33, count 0 2006.257.11:57:30.15#ibcon#wrote, iclass 33, count 0 2006.257.11:57:30.15#ibcon#about to read 3, iclass 33, count 0 2006.257.11:57:30.18#ibcon#read 3, iclass 33, count 0 2006.257.11:57:30.18#ibcon#about to read 4, iclass 33, count 0 2006.257.11:57:30.18#ibcon#read 4, iclass 33, count 0 2006.257.11:57:30.18#ibcon#about to read 5, iclass 33, count 0 2006.257.11:57:30.18#ibcon#read 5, iclass 33, count 0 2006.257.11:57:30.18#ibcon#about to read 6, iclass 33, count 0 2006.257.11:57:30.18#ibcon#read 6, iclass 33, count 0 2006.257.11:57:30.18#ibcon#end of sib2, iclass 33, count 0 2006.257.11:57:30.18#ibcon#*after write, iclass 33, count 0 2006.257.11:57:30.18#ibcon#*before return 0, iclass 33, count 0 2006.257.11:57:30.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:30.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:30.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:57:30.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:57:30.18$vck44/valo=7,864.99 2006.257.11:57:30.18#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.11:57:30.18#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.11:57:30.18#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:30.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:30.18#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:30.18#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:30.18#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:57:30.18#ibcon#first serial, iclass 35, count 0 2006.257.11:57:30.18#ibcon#enter sib2, iclass 35, count 0 2006.257.11:57:30.18#ibcon#flushed, iclass 35, count 0 2006.257.11:57:30.18#ibcon#about to write, iclass 35, count 0 2006.257.11:57:30.18#ibcon#wrote, iclass 35, count 0 2006.257.11:57:30.18#ibcon#about to read 3, iclass 35, count 0 2006.257.11:57:30.20#ibcon#read 3, iclass 35, count 0 2006.257.11:57:30.20#ibcon#about to read 4, iclass 35, count 0 2006.257.11:57:30.20#ibcon#read 4, iclass 35, count 0 2006.257.11:57:30.20#ibcon#about to read 5, iclass 35, count 0 2006.257.11:57:30.20#ibcon#read 5, iclass 35, count 0 2006.257.11:57:30.20#ibcon#about to read 6, iclass 35, count 0 2006.257.11:57:30.20#ibcon#read 6, iclass 35, count 0 2006.257.11:57:30.20#ibcon#end of sib2, iclass 35, count 0 2006.257.11:57:30.20#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:57:30.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:57:30.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.11:57:30.20#ibcon#*before write, iclass 35, count 0 2006.257.11:57:30.20#ibcon#enter sib2, iclass 35, count 0 2006.257.11:57:30.20#ibcon#flushed, iclass 35, count 0 2006.257.11:57:30.20#ibcon#about to write, iclass 35, count 0 2006.257.11:57:30.20#ibcon#wrote, iclass 35, count 0 2006.257.11:57:30.20#ibcon#about to read 3, iclass 35, count 0 2006.257.11:57:30.24#ibcon#read 3, iclass 35, count 0 2006.257.11:57:30.24#ibcon#about to read 4, iclass 35, count 0 2006.257.11:57:30.24#ibcon#read 4, iclass 35, count 0 2006.257.11:57:30.24#ibcon#about to read 5, iclass 35, count 0 2006.257.11:57:30.24#ibcon#read 5, iclass 35, count 0 2006.257.11:57:30.24#ibcon#about to read 6, iclass 35, count 0 2006.257.11:57:30.24#ibcon#read 6, iclass 35, count 0 2006.257.11:57:30.24#ibcon#end of sib2, iclass 35, count 0 2006.257.11:57:30.24#ibcon#*after write, iclass 35, count 0 2006.257.11:57:30.24#ibcon#*before return 0, iclass 35, count 0 2006.257.11:57:30.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:30.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:30.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:57:30.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:57:30.24$vck44/va=7,4 2006.257.11:57:30.24#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.11:57:30.24#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.11:57:30.24#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:30.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:30.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:30.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:30.30#ibcon#enter wrdev, iclass 37, count 2 2006.257.11:57:30.30#ibcon#first serial, iclass 37, count 2 2006.257.11:57:30.30#ibcon#enter sib2, iclass 37, count 2 2006.257.11:57:30.30#ibcon#flushed, iclass 37, count 2 2006.257.11:57:30.30#ibcon#about to write, iclass 37, count 2 2006.257.11:57:30.30#ibcon#wrote, iclass 37, count 2 2006.257.11:57:30.30#ibcon#about to read 3, iclass 37, count 2 2006.257.11:57:30.32#ibcon#read 3, iclass 37, count 2 2006.257.11:57:30.32#ibcon#about to read 4, iclass 37, count 2 2006.257.11:57:30.32#ibcon#read 4, iclass 37, count 2 2006.257.11:57:30.32#ibcon#about to read 5, iclass 37, count 2 2006.257.11:57:30.32#ibcon#read 5, iclass 37, count 2 2006.257.11:57:30.32#ibcon#about to read 6, iclass 37, count 2 2006.257.11:57:30.32#ibcon#read 6, iclass 37, count 2 2006.257.11:57:30.32#ibcon#end of sib2, iclass 37, count 2 2006.257.11:57:30.32#ibcon#*mode == 0, iclass 37, count 2 2006.257.11:57:30.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.11:57:30.32#ibcon#[25=AT07-04\r\n] 2006.257.11:57:30.32#ibcon#*before write, iclass 37, count 2 2006.257.11:57:30.32#ibcon#enter sib2, iclass 37, count 2 2006.257.11:57:30.32#ibcon#flushed, iclass 37, count 2 2006.257.11:57:30.32#ibcon#about to write, iclass 37, count 2 2006.257.11:57:30.32#ibcon#wrote, iclass 37, count 2 2006.257.11:57:30.32#ibcon#about to read 3, iclass 37, count 2 2006.257.11:57:30.35#ibcon#read 3, iclass 37, count 2 2006.257.11:57:30.35#ibcon#about to read 4, iclass 37, count 2 2006.257.11:57:30.35#ibcon#read 4, iclass 37, count 2 2006.257.11:57:30.35#ibcon#about to read 5, iclass 37, count 2 2006.257.11:57:30.35#ibcon#read 5, iclass 37, count 2 2006.257.11:57:30.35#ibcon#about to read 6, iclass 37, count 2 2006.257.11:57:30.35#ibcon#read 6, iclass 37, count 2 2006.257.11:57:30.35#ibcon#end of sib2, iclass 37, count 2 2006.257.11:57:30.35#ibcon#*after write, iclass 37, count 2 2006.257.11:57:30.35#ibcon#*before return 0, iclass 37, count 2 2006.257.11:57:30.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:30.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:30.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.11:57:30.35#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:30.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:30.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:30.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:30.47#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:57:30.47#ibcon#first serial, iclass 37, count 0 2006.257.11:57:30.47#ibcon#enter sib2, iclass 37, count 0 2006.257.11:57:30.47#ibcon#flushed, iclass 37, count 0 2006.257.11:57:30.47#ibcon#about to write, iclass 37, count 0 2006.257.11:57:30.47#ibcon#wrote, iclass 37, count 0 2006.257.11:57:30.47#ibcon#about to read 3, iclass 37, count 0 2006.257.11:57:30.49#ibcon#read 3, iclass 37, count 0 2006.257.11:57:30.49#ibcon#about to read 4, iclass 37, count 0 2006.257.11:57:30.49#ibcon#read 4, iclass 37, count 0 2006.257.11:57:30.49#ibcon#about to read 5, iclass 37, count 0 2006.257.11:57:30.49#ibcon#read 5, iclass 37, count 0 2006.257.11:57:30.49#ibcon#about to read 6, iclass 37, count 0 2006.257.11:57:30.49#ibcon#read 6, iclass 37, count 0 2006.257.11:57:30.49#ibcon#end of sib2, iclass 37, count 0 2006.257.11:57:30.49#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:57:30.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:57:30.49#ibcon#[25=USB\r\n] 2006.257.11:57:30.49#ibcon#*before write, iclass 37, count 0 2006.257.11:57:30.49#ibcon#enter sib2, iclass 37, count 0 2006.257.11:57:30.49#ibcon#flushed, iclass 37, count 0 2006.257.11:57:30.49#ibcon#about to write, iclass 37, count 0 2006.257.11:57:30.49#ibcon#wrote, iclass 37, count 0 2006.257.11:57:30.49#ibcon#about to read 3, iclass 37, count 0 2006.257.11:57:30.52#ibcon#read 3, iclass 37, count 0 2006.257.11:57:30.52#ibcon#about to read 4, iclass 37, count 0 2006.257.11:57:30.52#ibcon#read 4, iclass 37, count 0 2006.257.11:57:30.52#ibcon#about to read 5, iclass 37, count 0 2006.257.11:57:30.52#ibcon#read 5, iclass 37, count 0 2006.257.11:57:30.52#ibcon#about to read 6, iclass 37, count 0 2006.257.11:57:30.52#ibcon#read 6, iclass 37, count 0 2006.257.11:57:30.52#ibcon#end of sib2, iclass 37, count 0 2006.257.11:57:30.52#ibcon#*after write, iclass 37, count 0 2006.257.11:57:30.52#ibcon#*before return 0, iclass 37, count 0 2006.257.11:57:30.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:30.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:30.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:57:30.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:57:30.52$vck44/valo=8,884.99 2006.257.11:57:30.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.11:57:30.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.11:57:30.52#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:30.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:30.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:30.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:30.52#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:57:30.52#ibcon#first serial, iclass 39, count 0 2006.257.11:57:30.52#ibcon#enter sib2, iclass 39, count 0 2006.257.11:57:30.52#ibcon#flushed, iclass 39, count 0 2006.257.11:57:30.52#ibcon#about to write, iclass 39, count 0 2006.257.11:57:30.52#ibcon#wrote, iclass 39, count 0 2006.257.11:57:30.52#ibcon#about to read 3, iclass 39, count 0 2006.257.11:57:30.54#ibcon#read 3, iclass 39, count 0 2006.257.11:57:30.54#ibcon#about to read 4, iclass 39, count 0 2006.257.11:57:30.54#ibcon#read 4, iclass 39, count 0 2006.257.11:57:30.54#ibcon#about to read 5, iclass 39, count 0 2006.257.11:57:30.54#ibcon#read 5, iclass 39, count 0 2006.257.11:57:30.54#ibcon#about to read 6, iclass 39, count 0 2006.257.11:57:30.54#ibcon#read 6, iclass 39, count 0 2006.257.11:57:30.54#ibcon#end of sib2, iclass 39, count 0 2006.257.11:57:30.54#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:57:30.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:57:30.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.11:57:30.54#ibcon#*before write, iclass 39, count 0 2006.257.11:57:30.54#ibcon#enter sib2, iclass 39, count 0 2006.257.11:57:30.54#ibcon#flushed, iclass 39, count 0 2006.257.11:57:30.54#ibcon#about to write, iclass 39, count 0 2006.257.11:57:30.54#ibcon#wrote, iclass 39, count 0 2006.257.11:57:30.54#ibcon#about to read 3, iclass 39, count 0 2006.257.11:57:30.58#ibcon#read 3, iclass 39, count 0 2006.257.11:57:30.58#ibcon#about to read 4, iclass 39, count 0 2006.257.11:57:30.58#ibcon#read 4, iclass 39, count 0 2006.257.11:57:30.58#ibcon#about to read 5, iclass 39, count 0 2006.257.11:57:30.58#ibcon#read 5, iclass 39, count 0 2006.257.11:57:30.58#ibcon#about to read 6, iclass 39, count 0 2006.257.11:57:30.58#ibcon#read 6, iclass 39, count 0 2006.257.11:57:30.58#ibcon#end of sib2, iclass 39, count 0 2006.257.11:57:30.58#ibcon#*after write, iclass 39, count 0 2006.257.11:57:30.58#ibcon#*before return 0, iclass 39, count 0 2006.257.11:57:30.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:30.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:30.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:57:30.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:57:30.58$vck44/va=8,4 2006.257.11:57:30.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.11:57:30.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.11:57:30.58#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:30.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:57:30.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:57:30.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:57:30.64#ibcon#enter wrdev, iclass 3, count 2 2006.257.11:57:30.64#ibcon#first serial, iclass 3, count 2 2006.257.11:57:30.64#ibcon#enter sib2, iclass 3, count 2 2006.257.11:57:30.64#ibcon#flushed, iclass 3, count 2 2006.257.11:57:30.64#ibcon#about to write, iclass 3, count 2 2006.257.11:57:30.64#ibcon#wrote, iclass 3, count 2 2006.257.11:57:30.64#ibcon#about to read 3, iclass 3, count 2 2006.257.11:57:30.66#ibcon#read 3, iclass 3, count 2 2006.257.11:57:30.66#ibcon#about to read 4, iclass 3, count 2 2006.257.11:57:30.66#ibcon#read 4, iclass 3, count 2 2006.257.11:57:30.66#ibcon#about to read 5, iclass 3, count 2 2006.257.11:57:30.66#ibcon#read 5, iclass 3, count 2 2006.257.11:57:30.66#ibcon#about to read 6, iclass 3, count 2 2006.257.11:57:30.66#ibcon#read 6, iclass 3, count 2 2006.257.11:57:30.66#ibcon#end of sib2, iclass 3, count 2 2006.257.11:57:30.66#ibcon#*mode == 0, iclass 3, count 2 2006.257.11:57:30.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.11:57:30.66#ibcon#[25=AT08-04\r\n] 2006.257.11:57:30.66#ibcon#*before write, iclass 3, count 2 2006.257.11:57:30.66#ibcon#enter sib2, iclass 3, count 2 2006.257.11:57:30.66#ibcon#flushed, iclass 3, count 2 2006.257.11:57:30.66#ibcon#about to write, iclass 3, count 2 2006.257.11:57:30.66#ibcon#wrote, iclass 3, count 2 2006.257.11:57:30.66#ibcon#about to read 3, iclass 3, count 2 2006.257.11:57:30.69#ibcon#read 3, iclass 3, count 2 2006.257.11:57:30.69#ibcon#about to read 4, iclass 3, count 2 2006.257.11:57:30.69#ibcon#read 4, iclass 3, count 2 2006.257.11:57:30.69#ibcon#about to read 5, iclass 3, count 2 2006.257.11:57:30.69#ibcon#read 5, iclass 3, count 2 2006.257.11:57:30.69#ibcon#about to read 6, iclass 3, count 2 2006.257.11:57:30.69#ibcon#read 6, iclass 3, count 2 2006.257.11:57:30.69#ibcon#end of sib2, iclass 3, count 2 2006.257.11:57:30.69#ibcon#*after write, iclass 3, count 2 2006.257.11:57:30.69#ibcon#*before return 0, iclass 3, count 2 2006.257.11:57:30.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:57:30.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.11:57:30.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.11:57:30.69#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:30.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:57:30.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:57:30.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:57:30.81#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:57:30.81#ibcon#first serial, iclass 3, count 0 2006.257.11:57:30.81#ibcon#enter sib2, iclass 3, count 0 2006.257.11:57:30.81#ibcon#flushed, iclass 3, count 0 2006.257.11:57:30.81#ibcon#about to write, iclass 3, count 0 2006.257.11:57:30.81#ibcon#wrote, iclass 3, count 0 2006.257.11:57:30.81#ibcon#about to read 3, iclass 3, count 0 2006.257.11:57:30.83#ibcon#read 3, iclass 3, count 0 2006.257.11:57:30.83#ibcon#about to read 4, iclass 3, count 0 2006.257.11:57:30.83#ibcon#read 4, iclass 3, count 0 2006.257.11:57:30.83#ibcon#about to read 5, iclass 3, count 0 2006.257.11:57:30.83#ibcon#read 5, iclass 3, count 0 2006.257.11:57:30.83#ibcon#about to read 6, iclass 3, count 0 2006.257.11:57:30.83#ibcon#read 6, iclass 3, count 0 2006.257.11:57:30.83#ibcon#end of sib2, iclass 3, count 0 2006.257.11:57:30.83#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:57:30.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:57:30.83#ibcon#[25=USB\r\n] 2006.257.11:57:30.83#ibcon#*before write, iclass 3, count 0 2006.257.11:57:30.83#ibcon#enter sib2, iclass 3, count 0 2006.257.11:57:30.83#ibcon#flushed, iclass 3, count 0 2006.257.11:57:30.83#ibcon#about to write, iclass 3, count 0 2006.257.11:57:30.83#ibcon#wrote, iclass 3, count 0 2006.257.11:57:30.83#ibcon#about to read 3, iclass 3, count 0 2006.257.11:57:30.86#ibcon#read 3, iclass 3, count 0 2006.257.11:57:30.86#ibcon#about to read 4, iclass 3, count 0 2006.257.11:57:30.86#ibcon#read 4, iclass 3, count 0 2006.257.11:57:30.86#ibcon#about to read 5, iclass 3, count 0 2006.257.11:57:30.86#ibcon#read 5, iclass 3, count 0 2006.257.11:57:30.86#ibcon#about to read 6, iclass 3, count 0 2006.257.11:57:30.86#ibcon#read 6, iclass 3, count 0 2006.257.11:57:30.86#ibcon#end of sib2, iclass 3, count 0 2006.257.11:57:30.86#ibcon#*after write, iclass 3, count 0 2006.257.11:57:30.86#ibcon#*before return 0, iclass 3, count 0 2006.257.11:57:30.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:57:30.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.11:57:30.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:57:30.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:57:30.86$vck44/vblo=1,629.99 2006.257.11:57:30.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.11:57:30.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.11:57:30.86#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:30.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:30.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:30.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:30.86#ibcon#enter wrdev, iclass 5, count 0 2006.257.11:57:30.86#ibcon#first serial, iclass 5, count 0 2006.257.11:57:30.86#ibcon#enter sib2, iclass 5, count 0 2006.257.11:57:30.86#ibcon#flushed, iclass 5, count 0 2006.257.11:57:30.86#ibcon#about to write, iclass 5, count 0 2006.257.11:57:30.86#ibcon#wrote, iclass 5, count 0 2006.257.11:57:30.86#ibcon#about to read 3, iclass 5, count 0 2006.257.11:57:30.88#ibcon#read 3, iclass 5, count 0 2006.257.11:57:30.88#ibcon#about to read 4, iclass 5, count 0 2006.257.11:57:30.88#ibcon#read 4, iclass 5, count 0 2006.257.11:57:30.88#ibcon#about to read 5, iclass 5, count 0 2006.257.11:57:30.88#ibcon#read 5, iclass 5, count 0 2006.257.11:57:30.88#ibcon#about to read 6, iclass 5, count 0 2006.257.11:57:30.88#ibcon#read 6, iclass 5, count 0 2006.257.11:57:30.88#ibcon#end of sib2, iclass 5, count 0 2006.257.11:57:30.88#ibcon#*mode == 0, iclass 5, count 0 2006.257.11:57:30.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.11:57:30.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.11:57:30.88#ibcon#*before write, iclass 5, count 0 2006.257.11:57:30.88#ibcon#enter sib2, iclass 5, count 0 2006.257.11:57:30.88#ibcon#flushed, iclass 5, count 0 2006.257.11:57:30.88#ibcon#about to write, iclass 5, count 0 2006.257.11:57:30.88#ibcon#wrote, iclass 5, count 0 2006.257.11:57:30.88#ibcon#about to read 3, iclass 5, count 0 2006.257.11:57:30.92#ibcon#read 3, iclass 5, count 0 2006.257.11:57:30.92#ibcon#about to read 4, iclass 5, count 0 2006.257.11:57:30.92#ibcon#read 4, iclass 5, count 0 2006.257.11:57:30.92#ibcon#about to read 5, iclass 5, count 0 2006.257.11:57:30.92#ibcon#read 5, iclass 5, count 0 2006.257.11:57:30.92#ibcon#about to read 6, iclass 5, count 0 2006.257.11:57:30.92#ibcon#read 6, iclass 5, count 0 2006.257.11:57:30.92#ibcon#end of sib2, iclass 5, count 0 2006.257.11:57:30.92#ibcon#*after write, iclass 5, count 0 2006.257.11:57:30.92#ibcon#*before return 0, iclass 5, count 0 2006.257.11:57:30.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:30.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.11:57:30.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.11:57:30.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.11:57:30.92$vck44/vb=1,4 2006.257.11:57:30.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.11:57:30.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.11:57:30.92#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:30.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:30.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:30.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:30.92#ibcon#enter wrdev, iclass 7, count 2 2006.257.11:57:30.92#ibcon#first serial, iclass 7, count 2 2006.257.11:57:30.92#ibcon#enter sib2, iclass 7, count 2 2006.257.11:57:30.92#ibcon#flushed, iclass 7, count 2 2006.257.11:57:30.92#ibcon#about to write, iclass 7, count 2 2006.257.11:57:30.92#ibcon#wrote, iclass 7, count 2 2006.257.11:57:30.92#ibcon#about to read 3, iclass 7, count 2 2006.257.11:57:30.94#ibcon#read 3, iclass 7, count 2 2006.257.11:57:30.94#ibcon#about to read 4, iclass 7, count 2 2006.257.11:57:30.94#ibcon#read 4, iclass 7, count 2 2006.257.11:57:30.94#ibcon#about to read 5, iclass 7, count 2 2006.257.11:57:30.94#ibcon#read 5, iclass 7, count 2 2006.257.11:57:30.94#ibcon#about to read 6, iclass 7, count 2 2006.257.11:57:30.94#ibcon#read 6, iclass 7, count 2 2006.257.11:57:30.94#ibcon#end of sib2, iclass 7, count 2 2006.257.11:57:30.94#ibcon#*mode == 0, iclass 7, count 2 2006.257.11:57:30.94#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.11:57:30.94#ibcon#[27=AT01-04\r\n] 2006.257.11:57:30.94#ibcon#*before write, iclass 7, count 2 2006.257.11:57:30.94#ibcon#enter sib2, iclass 7, count 2 2006.257.11:57:30.94#ibcon#flushed, iclass 7, count 2 2006.257.11:57:30.94#ibcon#about to write, iclass 7, count 2 2006.257.11:57:30.94#ibcon#wrote, iclass 7, count 2 2006.257.11:57:30.94#ibcon#about to read 3, iclass 7, count 2 2006.257.11:57:30.97#ibcon#read 3, iclass 7, count 2 2006.257.11:57:30.97#ibcon#about to read 4, iclass 7, count 2 2006.257.11:57:30.97#ibcon#read 4, iclass 7, count 2 2006.257.11:57:30.97#ibcon#about to read 5, iclass 7, count 2 2006.257.11:57:30.97#ibcon#read 5, iclass 7, count 2 2006.257.11:57:30.97#ibcon#about to read 6, iclass 7, count 2 2006.257.11:57:30.97#ibcon#read 6, iclass 7, count 2 2006.257.11:57:30.97#ibcon#end of sib2, iclass 7, count 2 2006.257.11:57:30.97#ibcon#*after write, iclass 7, count 2 2006.257.11:57:30.97#ibcon#*before return 0, iclass 7, count 2 2006.257.11:57:30.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:30.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.11:57:30.97#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.11:57:30.97#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:30.97#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:31.09#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:31.09#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:31.09#ibcon#enter wrdev, iclass 7, count 0 2006.257.11:57:31.09#ibcon#first serial, iclass 7, count 0 2006.257.11:57:31.09#ibcon#enter sib2, iclass 7, count 0 2006.257.11:57:31.09#ibcon#flushed, iclass 7, count 0 2006.257.11:57:31.09#ibcon#about to write, iclass 7, count 0 2006.257.11:57:31.09#ibcon#wrote, iclass 7, count 0 2006.257.11:57:31.09#ibcon#about to read 3, iclass 7, count 0 2006.257.11:57:31.11#ibcon#read 3, iclass 7, count 0 2006.257.11:57:31.11#ibcon#about to read 4, iclass 7, count 0 2006.257.11:57:31.11#ibcon#read 4, iclass 7, count 0 2006.257.11:57:31.11#ibcon#about to read 5, iclass 7, count 0 2006.257.11:57:31.11#ibcon#read 5, iclass 7, count 0 2006.257.11:57:31.11#ibcon#about to read 6, iclass 7, count 0 2006.257.11:57:31.11#ibcon#read 6, iclass 7, count 0 2006.257.11:57:31.11#ibcon#end of sib2, iclass 7, count 0 2006.257.11:57:31.11#ibcon#*mode == 0, iclass 7, count 0 2006.257.11:57:31.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.11:57:31.11#ibcon#[27=USB\r\n] 2006.257.11:57:31.11#ibcon#*before write, iclass 7, count 0 2006.257.11:57:31.11#ibcon#enter sib2, iclass 7, count 0 2006.257.11:57:31.11#ibcon#flushed, iclass 7, count 0 2006.257.11:57:31.11#ibcon#about to write, iclass 7, count 0 2006.257.11:57:31.11#ibcon#wrote, iclass 7, count 0 2006.257.11:57:31.11#ibcon#about to read 3, iclass 7, count 0 2006.257.11:57:31.14#ibcon#read 3, iclass 7, count 0 2006.257.11:57:31.14#ibcon#about to read 4, iclass 7, count 0 2006.257.11:57:31.14#ibcon#read 4, iclass 7, count 0 2006.257.11:57:31.14#ibcon#about to read 5, iclass 7, count 0 2006.257.11:57:31.14#ibcon#read 5, iclass 7, count 0 2006.257.11:57:31.14#ibcon#about to read 6, iclass 7, count 0 2006.257.11:57:31.14#ibcon#read 6, iclass 7, count 0 2006.257.11:57:31.14#ibcon#end of sib2, iclass 7, count 0 2006.257.11:57:31.14#ibcon#*after write, iclass 7, count 0 2006.257.11:57:31.14#ibcon#*before return 0, iclass 7, count 0 2006.257.11:57:31.14#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:31.14#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.11:57:31.14#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.11:57:31.14#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.11:57:31.14$vck44/vblo=2,634.99 2006.257.11:57:31.14#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.11:57:31.14#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.11:57:31.14#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:31.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:31.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:31.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:31.14#ibcon#enter wrdev, iclass 11, count 0 2006.257.11:57:31.14#ibcon#first serial, iclass 11, count 0 2006.257.11:57:31.14#ibcon#enter sib2, iclass 11, count 0 2006.257.11:57:31.14#ibcon#flushed, iclass 11, count 0 2006.257.11:57:31.14#ibcon#about to write, iclass 11, count 0 2006.257.11:57:31.14#ibcon#wrote, iclass 11, count 0 2006.257.11:57:31.14#ibcon#about to read 3, iclass 11, count 0 2006.257.11:57:31.16#ibcon#read 3, iclass 11, count 0 2006.257.11:57:31.16#ibcon#about to read 4, iclass 11, count 0 2006.257.11:57:31.16#ibcon#read 4, iclass 11, count 0 2006.257.11:57:31.16#ibcon#about to read 5, iclass 11, count 0 2006.257.11:57:31.16#ibcon#read 5, iclass 11, count 0 2006.257.11:57:31.16#ibcon#about to read 6, iclass 11, count 0 2006.257.11:57:31.16#ibcon#read 6, iclass 11, count 0 2006.257.11:57:31.16#ibcon#end of sib2, iclass 11, count 0 2006.257.11:57:31.16#ibcon#*mode == 0, iclass 11, count 0 2006.257.11:57:31.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.11:57:31.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.11:57:31.16#ibcon#*before write, iclass 11, count 0 2006.257.11:57:31.16#ibcon#enter sib2, iclass 11, count 0 2006.257.11:57:31.16#ibcon#flushed, iclass 11, count 0 2006.257.11:57:31.16#ibcon#about to write, iclass 11, count 0 2006.257.11:57:31.16#ibcon#wrote, iclass 11, count 0 2006.257.11:57:31.16#ibcon#about to read 3, iclass 11, count 0 2006.257.11:57:31.20#ibcon#read 3, iclass 11, count 0 2006.257.11:57:31.20#ibcon#about to read 4, iclass 11, count 0 2006.257.11:57:31.20#ibcon#read 4, iclass 11, count 0 2006.257.11:57:31.20#ibcon#about to read 5, iclass 11, count 0 2006.257.11:57:31.20#ibcon#read 5, iclass 11, count 0 2006.257.11:57:31.20#ibcon#about to read 6, iclass 11, count 0 2006.257.11:57:31.20#ibcon#read 6, iclass 11, count 0 2006.257.11:57:31.20#ibcon#end of sib2, iclass 11, count 0 2006.257.11:57:31.20#ibcon#*after write, iclass 11, count 0 2006.257.11:57:31.20#ibcon#*before return 0, iclass 11, count 0 2006.257.11:57:31.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:31.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.11:57:31.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.11:57:31.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.11:57:31.20$vck44/vb=2,5 2006.257.11:57:31.20#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.11:57:31.20#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.11:57:31.20#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:31.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:31.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:31.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:31.26#ibcon#enter wrdev, iclass 13, count 2 2006.257.11:57:31.26#ibcon#first serial, iclass 13, count 2 2006.257.11:57:31.26#ibcon#enter sib2, iclass 13, count 2 2006.257.11:57:31.26#ibcon#flushed, iclass 13, count 2 2006.257.11:57:31.26#ibcon#about to write, iclass 13, count 2 2006.257.11:57:31.26#ibcon#wrote, iclass 13, count 2 2006.257.11:57:31.26#ibcon#about to read 3, iclass 13, count 2 2006.257.11:57:31.28#ibcon#read 3, iclass 13, count 2 2006.257.11:57:31.28#ibcon#about to read 4, iclass 13, count 2 2006.257.11:57:31.28#ibcon#read 4, iclass 13, count 2 2006.257.11:57:31.28#ibcon#about to read 5, iclass 13, count 2 2006.257.11:57:31.28#ibcon#read 5, iclass 13, count 2 2006.257.11:57:31.28#ibcon#about to read 6, iclass 13, count 2 2006.257.11:57:31.28#ibcon#read 6, iclass 13, count 2 2006.257.11:57:31.28#ibcon#end of sib2, iclass 13, count 2 2006.257.11:57:31.28#ibcon#*mode == 0, iclass 13, count 2 2006.257.11:57:31.28#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.11:57:31.28#ibcon#[27=AT02-05\r\n] 2006.257.11:57:31.28#ibcon#*before write, iclass 13, count 2 2006.257.11:57:31.28#ibcon#enter sib2, iclass 13, count 2 2006.257.11:57:31.28#ibcon#flushed, iclass 13, count 2 2006.257.11:57:31.28#ibcon#about to write, iclass 13, count 2 2006.257.11:57:31.28#ibcon#wrote, iclass 13, count 2 2006.257.11:57:31.28#ibcon#about to read 3, iclass 13, count 2 2006.257.11:57:31.31#ibcon#read 3, iclass 13, count 2 2006.257.11:57:31.31#ibcon#about to read 4, iclass 13, count 2 2006.257.11:57:31.31#ibcon#read 4, iclass 13, count 2 2006.257.11:57:31.31#ibcon#about to read 5, iclass 13, count 2 2006.257.11:57:31.31#ibcon#read 5, iclass 13, count 2 2006.257.11:57:31.31#ibcon#about to read 6, iclass 13, count 2 2006.257.11:57:31.31#ibcon#read 6, iclass 13, count 2 2006.257.11:57:31.31#ibcon#end of sib2, iclass 13, count 2 2006.257.11:57:31.31#ibcon#*after write, iclass 13, count 2 2006.257.11:57:31.31#ibcon#*before return 0, iclass 13, count 2 2006.257.11:57:31.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:31.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.11:57:31.31#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.11:57:31.31#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:31.31#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:31.43#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:31.43#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:31.43#ibcon#enter wrdev, iclass 13, count 0 2006.257.11:57:31.43#ibcon#first serial, iclass 13, count 0 2006.257.11:57:31.43#ibcon#enter sib2, iclass 13, count 0 2006.257.11:57:31.43#ibcon#flushed, iclass 13, count 0 2006.257.11:57:31.43#ibcon#about to write, iclass 13, count 0 2006.257.11:57:31.43#ibcon#wrote, iclass 13, count 0 2006.257.11:57:31.43#ibcon#about to read 3, iclass 13, count 0 2006.257.11:57:31.45#ibcon#read 3, iclass 13, count 0 2006.257.11:57:31.45#ibcon#about to read 4, iclass 13, count 0 2006.257.11:57:31.45#ibcon#read 4, iclass 13, count 0 2006.257.11:57:31.45#ibcon#about to read 5, iclass 13, count 0 2006.257.11:57:31.45#ibcon#read 5, iclass 13, count 0 2006.257.11:57:31.45#ibcon#about to read 6, iclass 13, count 0 2006.257.11:57:31.45#ibcon#read 6, iclass 13, count 0 2006.257.11:57:31.45#ibcon#end of sib2, iclass 13, count 0 2006.257.11:57:31.45#ibcon#*mode == 0, iclass 13, count 0 2006.257.11:57:31.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.11:57:31.45#ibcon#[27=USB\r\n] 2006.257.11:57:31.45#ibcon#*before write, iclass 13, count 0 2006.257.11:57:31.45#ibcon#enter sib2, iclass 13, count 0 2006.257.11:57:31.45#ibcon#flushed, iclass 13, count 0 2006.257.11:57:31.45#ibcon#about to write, iclass 13, count 0 2006.257.11:57:31.45#ibcon#wrote, iclass 13, count 0 2006.257.11:57:31.45#ibcon#about to read 3, iclass 13, count 0 2006.257.11:57:31.48#ibcon#read 3, iclass 13, count 0 2006.257.11:57:31.48#ibcon#about to read 4, iclass 13, count 0 2006.257.11:57:31.48#ibcon#read 4, iclass 13, count 0 2006.257.11:57:31.48#ibcon#about to read 5, iclass 13, count 0 2006.257.11:57:31.48#ibcon#read 5, iclass 13, count 0 2006.257.11:57:31.48#ibcon#about to read 6, iclass 13, count 0 2006.257.11:57:31.48#ibcon#read 6, iclass 13, count 0 2006.257.11:57:31.48#ibcon#end of sib2, iclass 13, count 0 2006.257.11:57:31.48#ibcon#*after write, iclass 13, count 0 2006.257.11:57:31.48#ibcon#*before return 0, iclass 13, count 0 2006.257.11:57:31.48#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:31.48#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.11:57:31.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.11:57:31.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.11:57:31.48$vck44/vblo=3,649.99 2006.257.11:57:31.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.11:57:31.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.11:57:31.48#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:31.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:31.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:31.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:31.48#ibcon#enter wrdev, iclass 15, count 0 2006.257.11:57:31.48#ibcon#first serial, iclass 15, count 0 2006.257.11:57:31.48#ibcon#enter sib2, iclass 15, count 0 2006.257.11:57:31.48#ibcon#flushed, iclass 15, count 0 2006.257.11:57:31.48#ibcon#about to write, iclass 15, count 0 2006.257.11:57:31.48#ibcon#wrote, iclass 15, count 0 2006.257.11:57:31.48#ibcon#about to read 3, iclass 15, count 0 2006.257.11:57:31.50#ibcon#read 3, iclass 15, count 0 2006.257.11:57:31.50#ibcon#about to read 4, iclass 15, count 0 2006.257.11:57:31.50#ibcon#read 4, iclass 15, count 0 2006.257.11:57:31.50#ibcon#about to read 5, iclass 15, count 0 2006.257.11:57:31.50#ibcon#read 5, iclass 15, count 0 2006.257.11:57:31.50#ibcon#about to read 6, iclass 15, count 0 2006.257.11:57:31.50#ibcon#read 6, iclass 15, count 0 2006.257.11:57:31.50#ibcon#end of sib2, iclass 15, count 0 2006.257.11:57:31.50#ibcon#*mode == 0, iclass 15, count 0 2006.257.11:57:31.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.11:57:31.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.11:57:31.50#ibcon#*before write, iclass 15, count 0 2006.257.11:57:31.50#ibcon#enter sib2, iclass 15, count 0 2006.257.11:57:31.50#ibcon#flushed, iclass 15, count 0 2006.257.11:57:31.50#ibcon#about to write, iclass 15, count 0 2006.257.11:57:31.50#ibcon#wrote, iclass 15, count 0 2006.257.11:57:31.50#ibcon#about to read 3, iclass 15, count 0 2006.257.11:57:31.54#ibcon#read 3, iclass 15, count 0 2006.257.11:57:31.54#ibcon#about to read 4, iclass 15, count 0 2006.257.11:57:31.54#ibcon#read 4, iclass 15, count 0 2006.257.11:57:31.54#ibcon#about to read 5, iclass 15, count 0 2006.257.11:57:31.54#ibcon#read 5, iclass 15, count 0 2006.257.11:57:31.54#ibcon#about to read 6, iclass 15, count 0 2006.257.11:57:31.54#ibcon#read 6, iclass 15, count 0 2006.257.11:57:31.54#ibcon#end of sib2, iclass 15, count 0 2006.257.11:57:31.54#ibcon#*after write, iclass 15, count 0 2006.257.11:57:31.54#ibcon#*before return 0, iclass 15, count 0 2006.257.11:57:31.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:31.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.11:57:31.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.11:57:31.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.11:57:31.54$vck44/vb=3,4 2006.257.11:57:31.54#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.11:57:31.54#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.11:57:31.54#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:31.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:31.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:31.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:31.60#ibcon#enter wrdev, iclass 17, count 2 2006.257.11:57:31.60#ibcon#first serial, iclass 17, count 2 2006.257.11:57:31.60#ibcon#enter sib2, iclass 17, count 2 2006.257.11:57:31.60#ibcon#flushed, iclass 17, count 2 2006.257.11:57:31.60#ibcon#about to write, iclass 17, count 2 2006.257.11:57:31.60#ibcon#wrote, iclass 17, count 2 2006.257.11:57:31.60#ibcon#about to read 3, iclass 17, count 2 2006.257.11:57:31.62#ibcon#read 3, iclass 17, count 2 2006.257.11:57:31.62#ibcon#about to read 4, iclass 17, count 2 2006.257.11:57:31.62#ibcon#read 4, iclass 17, count 2 2006.257.11:57:31.62#ibcon#about to read 5, iclass 17, count 2 2006.257.11:57:31.62#ibcon#read 5, iclass 17, count 2 2006.257.11:57:31.62#ibcon#about to read 6, iclass 17, count 2 2006.257.11:57:31.62#ibcon#read 6, iclass 17, count 2 2006.257.11:57:31.62#ibcon#end of sib2, iclass 17, count 2 2006.257.11:57:31.62#ibcon#*mode == 0, iclass 17, count 2 2006.257.11:57:31.62#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.11:57:31.62#ibcon#[27=AT03-04\r\n] 2006.257.11:57:31.62#ibcon#*before write, iclass 17, count 2 2006.257.11:57:31.62#ibcon#enter sib2, iclass 17, count 2 2006.257.11:57:31.62#ibcon#flushed, iclass 17, count 2 2006.257.11:57:31.62#ibcon#about to write, iclass 17, count 2 2006.257.11:57:31.62#ibcon#wrote, iclass 17, count 2 2006.257.11:57:31.62#ibcon#about to read 3, iclass 17, count 2 2006.257.11:57:31.65#ibcon#read 3, iclass 17, count 2 2006.257.11:57:31.65#ibcon#about to read 4, iclass 17, count 2 2006.257.11:57:31.65#ibcon#read 4, iclass 17, count 2 2006.257.11:57:31.65#ibcon#about to read 5, iclass 17, count 2 2006.257.11:57:31.65#ibcon#read 5, iclass 17, count 2 2006.257.11:57:31.65#ibcon#about to read 6, iclass 17, count 2 2006.257.11:57:31.65#ibcon#read 6, iclass 17, count 2 2006.257.11:57:31.65#ibcon#end of sib2, iclass 17, count 2 2006.257.11:57:31.65#ibcon#*after write, iclass 17, count 2 2006.257.11:57:31.65#ibcon#*before return 0, iclass 17, count 2 2006.257.11:57:31.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:31.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.11:57:31.65#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.11:57:31.65#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:31.65#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:31.77#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:31.77#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:31.77#ibcon#enter wrdev, iclass 17, count 0 2006.257.11:57:31.77#ibcon#first serial, iclass 17, count 0 2006.257.11:57:31.77#ibcon#enter sib2, iclass 17, count 0 2006.257.11:57:31.77#ibcon#flushed, iclass 17, count 0 2006.257.11:57:31.77#ibcon#about to write, iclass 17, count 0 2006.257.11:57:31.77#ibcon#wrote, iclass 17, count 0 2006.257.11:57:31.77#ibcon#about to read 3, iclass 17, count 0 2006.257.11:57:31.79#ibcon#read 3, iclass 17, count 0 2006.257.11:57:31.79#ibcon#about to read 4, iclass 17, count 0 2006.257.11:57:31.79#ibcon#read 4, iclass 17, count 0 2006.257.11:57:31.79#ibcon#about to read 5, iclass 17, count 0 2006.257.11:57:31.79#ibcon#read 5, iclass 17, count 0 2006.257.11:57:31.79#ibcon#about to read 6, iclass 17, count 0 2006.257.11:57:31.79#ibcon#read 6, iclass 17, count 0 2006.257.11:57:31.79#ibcon#end of sib2, iclass 17, count 0 2006.257.11:57:31.79#ibcon#*mode == 0, iclass 17, count 0 2006.257.11:57:31.79#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.11:57:31.79#ibcon#[27=USB\r\n] 2006.257.11:57:31.79#ibcon#*before write, iclass 17, count 0 2006.257.11:57:31.79#ibcon#enter sib2, iclass 17, count 0 2006.257.11:57:31.79#ibcon#flushed, iclass 17, count 0 2006.257.11:57:31.79#ibcon#about to write, iclass 17, count 0 2006.257.11:57:31.79#ibcon#wrote, iclass 17, count 0 2006.257.11:57:31.79#ibcon#about to read 3, iclass 17, count 0 2006.257.11:57:31.82#ibcon#read 3, iclass 17, count 0 2006.257.11:57:31.82#ibcon#about to read 4, iclass 17, count 0 2006.257.11:57:31.82#ibcon#read 4, iclass 17, count 0 2006.257.11:57:31.82#ibcon#about to read 5, iclass 17, count 0 2006.257.11:57:31.82#ibcon#read 5, iclass 17, count 0 2006.257.11:57:31.82#ibcon#about to read 6, iclass 17, count 0 2006.257.11:57:31.82#ibcon#read 6, iclass 17, count 0 2006.257.11:57:31.82#ibcon#end of sib2, iclass 17, count 0 2006.257.11:57:31.82#ibcon#*after write, iclass 17, count 0 2006.257.11:57:31.82#ibcon#*before return 0, iclass 17, count 0 2006.257.11:57:31.82#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:31.82#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.11:57:31.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.11:57:31.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.11:57:31.82$vck44/vblo=4,679.99 2006.257.11:57:31.82#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.11:57:31.82#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.11:57:31.82#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:31.82#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:57:31.82#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:57:31.82#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:57:31.82#ibcon#enter wrdev, iclass 19, count 0 2006.257.11:57:31.82#ibcon#first serial, iclass 19, count 0 2006.257.11:57:31.82#ibcon#enter sib2, iclass 19, count 0 2006.257.11:57:31.82#ibcon#flushed, iclass 19, count 0 2006.257.11:57:31.82#ibcon#about to write, iclass 19, count 0 2006.257.11:57:31.82#ibcon#wrote, iclass 19, count 0 2006.257.11:57:31.82#ibcon#about to read 3, iclass 19, count 0 2006.257.11:57:31.84#ibcon#read 3, iclass 19, count 0 2006.257.11:57:31.84#ibcon#about to read 4, iclass 19, count 0 2006.257.11:57:31.84#ibcon#read 4, iclass 19, count 0 2006.257.11:57:31.84#ibcon#about to read 5, iclass 19, count 0 2006.257.11:57:31.84#ibcon#read 5, iclass 19, count 0 2006.257.11:57:31.84#ibcon#about to read 6, iclass 19, count 0 2006.257.11:57:31.84#ibcon#read 6, iclass 19, count 0 2006.257.11:57:31.84#ibcon#end of sib2, iclass 19, count 0 2006.257.11:57:31.84#ibcon#*mode == 0, iclass 19, count 0 2006.257.11:57:31.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.11:57:31.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.11:57:31.84#ibcon#*before write, iclass 19, count 0 2006.257.11:57:31.84#ibcon#enter sib2, iclass 19, count 0 2006.257.11:57:31.84#ibcon#flushed, iclass 19, count 0 2006.257.11:57:31.84#ibcon#about to write, iclass 19, count 0 2006.257.11:57:31.84#ibcon#wrote, iclass 19, count 0 2006.257.11:57:31.84#ibcon#about to read 3, iclass 19, count 0 2006.257.11:57:31.88#ibcon#read 3, iclass 19, count 0 2006.257.11:57:31.88#ibcon#about to read 4, iclass 19, count 0 2006.257.11:57:31.88#ibcon#read 4, iclass 19, count 0 2006.257.11:57:31.88#ibcon#about to read 5, iclass 19, count 0 2006.257.11:57:31.88#ibcon#read 5, iclass 19, count 0 2006.257.11:57:31.88#ibcon#about to read 6, iclass 19, count 0 2006.257.11:57:31.88#ibcon#read 6, iclass 19, count 0 2006.257.11:57:31.88#ibcon#end of sib2, iclass 19, count 0 2006.257.11:57:31.88#ibcon#*after write, iclass 19, count 0 2006.257.11:57:31.88#ibcon#*before return 0, iclass 19, count 0 2006.257.11:57:31.88#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:57:31.88#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.11:57:31.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.11:57:31.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.11:57:31.88$vck44/vb=4,5 2006.257.11:57:31.88#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.11:57:31.88#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.11:57:31.88#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:31.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:57:31.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:57:31.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:57:31.94#ibcon#enter wrdev, iclass 21, count 2 2006.257.11:57:31.94#ibcon#first serial, iclass 21, count 2 2006.257.11:57:31.94#ibcon#enter sib2, iclass 21, count 2 2006.257.11:57:31.94#ibcon#flushed, iclass 21, count 2 2006.257.11:57:31.94#ibcon#about to write, iclass 21, count 2 2006.257.11:57:31.94#ibcon#wrote, iclass 21, count 2 2006.257.11:57:31.94#ibcon#about to read 3, iclass 21, count 2 2006.257.11:57:31.96#ibcon#read 3, iclass 21, count 2 2006.257.11:57:31.96#ibcon#about to read 4, iclass 21, count 2 2006.257.11:57:31.96#ibcon#read 4, iclass 21, count 2 2006.257.11:57:31.96#ibcon#about to read 5, iclass 21, count 2 2006.257.11:57:31.96#ibcon#read 5, iclass 21, count 2 2006.257.11:57:31.96#ibcon#about to read 6, iclass 21, count 2 2006.257.11:57:31.96#ibcon#read 6, iclass 21, count 2 2006.257.11:57:31.96#ibcon#end of sib2, iclass 21, count 2 2006.257.11:57:31.96#ibcon#*mode == 0, iclass 21, count 2 2006.257.11:57:31.96#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.11:57:31.96#ibcon#[27=AT04-05\r\n] 2006.257.11:57:31.96#ibcon#*before write, iclass 21, count 2 2006.257.11:57:31.96#ibcon#enter sib2, iclass 21, count 2 2006.257.11:57:31.96#ibcon#flushed, iclass 21, count 2 2006.257.11:57:31.96#ibcon#about to write, iclass 21, count 2 2006.257.11:57:31.96#ibcon#wrote, iclass 21, count 2 2006.257.11:57:31.96#ibcon#about to read 3, iclass 21, count 2 2006.257.11:57:31.99#ibcon#read 3, iclass 21, count 2 2006.257.11:57:31.99#ibcon#about to read 4, iclass 21, count 2 2006.257.11:57:31.99#ibcon#read 4, iclass 21, count 2 2006.257.11:57:31.99#ibcon#about to read 5, iclass 21, count 2 2006.257.11:57:31.99#ibcon#read 5, iclass 21, count 2 2006.257.11:57:31.99#ibcon#about to read 6, iclass 21, count 2 2006.257.11:57:31.99#ibcon#read 6, iclass 21, count 2 2006.257.11:57:31.99#ibcon#end of sib2, iclass 21, count 2 2006.257.11:57:31.99#ibcon#*after write, iclass 21, count 2 2006.257.11:57:31.99#ibcon#*before return 0, iclass 21, count 2 2006.257.11:57:31.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:57:31.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.11:57:31.99#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.11:57:31.99#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:31.99#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:57:32.11#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:57:32.11#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:57:32.11#ibcon#enter wrdev, iclass 21, count 0 2006.257.11:57:32.11#ibcon#first serial, iclass 21, count 0 2006.257.11:57:32.11#ibcon#enter sib2, iclass 21, count 0 2006.257.11:57:32.11#ibcon#flushed, iclass 21, count 0 2006.257.11:57:32.11#ibcon#about to write, iclass 21, count 0 2006.257.11:57:32.11#ibcon#wrote, iclass 21, count 0 2006.257.11:57:32.11#ibcon#about to read 3, iclass 21, count 0 2006.257.11:57:32.13#ibcon#read 3, iclass 21, count 0 2006.257.11:57:32.13#ibcon#about to read 4, iclass 21, count 0 2006.257.11:57:32.13#ibcon#read 4, iclass 21, count 0 2006.257.11:57:32.13#ibcon#about to read 5, iclass 21, count 0 2006.257.11:57:32.13#ibcon#read 5, iclass 21, count 0 2006.257.11:57:32.13#ibcon#about to read 6, iclass 21, count 0 2006.257.11:57:32.13#ibcon#read 6, iclass 21, count 0 2006.257.11:57:32.13#ibcon#end of sib2, iclass 21, count 0 2006.257.11:57:32.13#ibcon#*mode == 0, iclass 21, count 0 2006.257.11:57:32.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.11:57:32.13#ibcon#[27=USB\r\n] 2006.257.11:57:32.13#ibcon#*before write, iclass 21, count 0 2006.257.11:57:32.13#ibcon#enter sib2, iclass 21, count 0 2006.257.11:57:32.13#ibcon#flushed, iclass 21, count 0 2006.257.11:57:32.13#ibcon#about to write, iclass 21, count 0 2006.257.11:57:32.13#ibcon#wrote, iclass 21, count 0 2006.257.11:57:32.13#ibcon#about to read 3, iclass 21, count 0 2006.257.11:57:32.16#ibcon#read 3, iclass 21, count 0 2006.257.11:57:32.16#ibcon#about to read 4, iclass 21, count 0 2006.257.11:57:32.16#ibcon#read 4, iclass 21, count 0 2006.257.11:57:32.16#ibcon#about to read 5, iclass 21, count 0 2006.257.11:57:32.16#ibcon#read 5, iclass 21, count 0 2006.257.11:57:32.16#ibcon#about to read 6, iclass 21, count 0 2006.257.11:57:32.16#ibcon#read 6, iclass 21, count 0 2006.257.11:57:32.16#ibcon#end of sib2, iclass 21, count 0 2006.257.11:57:32.16#ibcon#*after write, iclass 21, count 0 2006.257.11:57:32.16#ibcon#*before return 0, iclass 21, count 0 2006.257.11:57:32.16#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:57:32.16#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.11:57:32.16#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.11:57:32.16#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.11:57:32.16$vck44/vblo=5,709.99 2006.257.11:57:32.16#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.11:57:32.16#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.11:57:32.16#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:32.16#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:32.16#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:32.16#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:32.16#ibcon#enter wrdev, iclass 23, count 0 2006.257.11:57:32.16#ibcon#first serial, iclass 23, count 0 2006.257.11:57:32.16#ibcon#enter sib2, iclass 23, count 0 2006.257.11:57:32.16#ibcon#flushed, iclass 23, count 0 2006.257.11:57:32.16#ibcon#about to write, iclass 23, count 0 2006.257.11:57:32.16#ibcon#wrote, iclass 23, count 0 2006.257.11:57:32.16#ibcon#about to read 3, iclass 23, count 0 2006.257.11:57:32.18#ibcon#read 3, iclass 23, count 0 2006.257.11:57:32.18#ibcon#about to read 4, iclass 23, count 0 2006.257.11:57:32.18#ibcon#read 4, iclass 23, count 0 2006.257.11:57:32.18#ibcon#about to read 5, iclass 23, count 0 2006.257.11:57:32.18#ibcon#read 5, iclass 23, count 0 2006.257.11:57:32.18#ibcon#about to read 6, iclass 23, count 0 2006.257.11:57:32.18#ibcon#read 6, iclass 23, count 0 2006.257.11:57:32.18#ibcon#end of sib2, iclass 23, count 0 2006.257.11:57:32.18#ibcon#*mode == 0, iclass 23, count 0 2006.257.11:57:32.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.11:57:32.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.11:57:32.18#ibcon#*before write, iclass 23, count 0 2006.257.11:57:32.18#ibcon#enter sib2, iclass 23, count 0 2006.257.11:57:32.18#ibcon#flushed, iclass 23, count 0 2006.257.11:57:32.18#ibcon#about to write, iclass 23, count 0 2006.257.11:57:32.18#ibcon#wrote, iclass 23, count 0 2006.257.11:57:32.18#ibcon#about to read 3, iclass 23, count 0 2006.257.11:57:32.22#ibcon#read 3, iclass 23, count 0 2006.257.11:57:32.22#ibcon#about to read 4, iclass 23, count 0 2006.257.11:57:32.22#ibcon#read 4, iclass 23, count 0 2006.257.11:57:32.22#ibcon#about to read 5, iclass 23, count 0 2006.257.11:57:32.22#ibcon#read 5, iclass 23, count 0 2006.257.11:57:32.22#ibcon#about to read 6, iclass 23, count 0 2006.257.11:57:32.22#ibcon#read 6, iclass 23, count 0 2006.257.11:57:32.22#ibcon#end of sib2, iclass 23, count 0 2006.257.11:57:32.22#ibcon#*after write, iclass 23, count 0 2006.257.11:57:32.22#ibcon#*before return 0, iclass 23, count 0 2006.257.11:57:32.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:32.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.11:57:32.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.11:57:32.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.11:57:32.22$vck44/vb=5,4 2006.257.11:57:32.22#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.11:57:32.22#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.11:57:32.22#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:32.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:32.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:32.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:32.28#ibcon#enter wrdev, iclass 25, count 2 2006.257.11:57:32.28#ibcon#first serial, iclass 25, count 2 2006.257.11:57:32.28#ibcon#enter sib2, iclass 25, count 2 2006.257.11:57:32.28#ibcon#flushed, iclass 25, count 2 2006.257.11:57:32.28#ibcon#about to write, iclass 25, count 2 2006.257.11:57:32.28#ibcon#wrote, iclass 25, count 2 2006.257.11:57:32.28#ibcon#about to read 3, iclass 25, count 2 2006.257.11:57:32.30#ibcon#read 3, iclass 25, count 2 2006.257.11:57:32.30#ibcon#about to read 4, iclass 25, count 2 2006.257.11:57:32.30#ibcon#read 4, iclass 25, count 2 2006.257.11:57:32.30#ibcon#about to read 5, iclass 25, count 2 2006.257.11:57:32.30#ibcon#read 5, iclass 25, count 2 2006.257.11:57:32.30#ibcon#about to read 6, iclass 25, count 2 2006.257.11:57:32.30#ibcon#read 6, iclass 25, count 2 2006.257.11:57:32.30#ibcon#end of sib2, iclass 25, count 2 2006.257.11:57:32.30#ibcon#*mode == 0, iclass 25, count 2 2006.257.11:57:32.30#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.11:57:32.30#ibcon#[27=AT05-04\r\n] 2006.257.11:57:32.30#ibcon#*before write, iclass 25, count 2 2006.257.11:57:32.30#ibcon#enter sib2, iclass 25, count 2 2006.257.11:57:32.30#ibcon#flushed, iclass 25, count 2 2006.257.11:57:32.30#ibcon#about to write, iclass 25, count 2 2006.257.11:57:32.30#ibcon#wrote, iclass 25, count 2 2006.257.11:57:32.30#ibcon#about to read 3, iclass 25, count 2 2006.257.11:57:32.33#ibcon#read 3, iclass 25, count 2 2006.257.11:57:32.33#ibcon#about to read 4, iclass 25, count 2 2006.257.11:57:32.33#ibcon#read 4, iclass 25, count 2 2006.257.11:57:32.33#ibcon#about to read 5, iclass 25, count 2 2006.257.11:57:32.33#ibcon#read 5, iclass 25, count 2 2006.257.11:57:32.33#ibcon#about to read 6, iclass 25, count 2 2006.257.11:57:32.33#ibcon#read 6, iclass 25, count 2 2006.257.11:57:32.33#ibcon#end of sib2, iclass 25, count 2 2006.257.11:57:32.33#ibcon#*after write, iclass 25, count 2 2006.257.11:57:32.33#ibcon#*before return 0, iclass 25, count 2 2006.257.11:57:32.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:32.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.11:57:32.33#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.11:57:32.33#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:32.33#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:32.45#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:32.45#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:32.45#ibcon#enter wrdev, iclass 25, count 0 2006.257.11:57:32.45#ibcon#first serial, iclass 25, count 0 2006.257.11:57:32.45#ibcon#enter sib2, iclass 25, count 0 2006.257.11:57:32.45#ibcon#flushed, iclass 25, count 0 2006.257.11:57:32.45#ibcon#about to write, iclass 25, count 0 2006.257.11:57:32.45#ibcon#wrote, iclass 25, count 0 2006.257.11:57:32.45#ibcon#about to read 3, iclass 25, count 0 2006.257.11:57:32.47#ibcon#read 3, iclass 25, count 0 2006.257.11:57:32.47#ibcon#about to read 4, iclass 25, count 0 2006.257.11:57:32.47#ibcon#read 4, iclass 25, count 0 2006.257.11:57:32.47#ibcon#about to read 5, iclass 25, count 0 2006.257.11:57:32.47#ibcon#read 5, iclass 25, count 0 2006.257.11:57:32.47#ibcon#about to read 6, iclass 25, count 0 2006.257.11:57:32.47#ibcon#read 6, iclass 25, count 0 2006.257.11:57:32.47#ibcon#end of sib2, iclass 25, count 0 2006.257.11:57:32.47#ibcon#*mode == 0, iclass 25, count 0 2006.257.11:57:32.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.11:57:32.47#ibcon#[27=USB\r\n] 2006.257.11:57:32.47#ibcon#*before write, iclass 25, count 0 2006.257.11:57:32.47#ibcon#enter sib2, iclass 25, count 0 2006.257.11:57:32.47#ibcon#flushed, iclass 25, count 0 2006.257.11:57:32.47#ibcon#about to write, iclass 25, count 0 2006.257.11:57:32.47#ibcon#wrote, iclass 25, count 0 2006.257.11:57:32.47#ibcon#about to read 3, iclass 25, count 0 2006.257.11:57:32.50#ibcon#read 3, iclass 25, count 0 2006.257.11:57:32.50#ibcon#about to read 4, iclass 25, count 0 2006.257.11:57:32.50#ibcon#read 4, iclass 25, count 0 2006.257.11:57:32.50#ibcon#about to read 5, iclass 25, count 0 2006.257.11:57:32.50#ibcon#read 5, iclass 25, count 0 2006.257.11:57:32.50#ibcon#about to read 6, iclass 25, count 0 2006.257.11:57:32.50#ibcon#read 6, iclass 25, count 0 2006.257.11:57:32.50#ibcon#end of sib2, iclass 25, count 0 2006.257.11:57:32.50#ibcon#*after write, iclass 25, count 0 2006.257.11:57:32.50#ibcon#*before return 0, iclass 25, count 0 2006.257.11:57:32.50#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:32.50#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.11:57:32.50#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.11:57:32.50#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.11:57:32.50$vck44/vblo=6,719.99 2006.257.11:57:32.50#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.11:57:32.50#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.11:57:32.50#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:32.50#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:32.50#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:32.50#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:32.50#ibcon#enter wrdev, iclass 27, count 0 2006.257.11:57:32.50#ibcon#first serial, iclass 27, count 0 2006.257.11:57:32.50#ibcon#enter sib2, iclass 27, count 0 2006.257.11:57:32.50#ibcon#flushed, iclass 27, count 0 2006.257.11:57:32.50#ibcon#about to write, iclass 27, count 0 2006.257.11:57:32.50#ibcon#wrote, iclass 27, count 0 2006.257.11:57:32.50#ibcon#about to read 3, iclass 27, count 0 2006.257.11:57:32.52#ibcon#read 3, iclass 27, count 0 2006.257.11:57:32.52#ibcon#about to read 4, iclass 27, count 0 2006.257.11:57:32.52#ibcon#read 4, iclass 27, count 0 2006.257.11:57:32.52#ibcon#about to read 5, iclass 27, count 0 2006.257.11:57:32.52#ibcon#read 5, iclass 27, count 0 2006.257.11:57:32.52#ibcon#about to read 6, iclass 27, count 0 2006.257.11:57:32.52#ibcon#read 6, iclass 27, count 0 2006.257.11:57:32.52#ibcon#end of sib2, iclass 27, count 0 2006.257.11:57:32.52#ibcon#*mode == 0, iclass 27, count 0 2006.257.11:57:32.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.11:57:32.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.11:57:32.52#ibcon#*before write, iclass 27, count 0 2006.257.11:57:32.52#ibcon#enter sib2, iclass 27, count 0 2006.257.11:57:32.52#ibcon#flushed, iclass 27, count 0 2006.257.11:57:32.52#ibcon#about to write, iclass 27, count 0 2006.257.11:57:32.52#ibcon#wrote, iclass 27, count 0 2006.257.11:57:32.52#ibcon#about to read 3, iclass 27, count 0 2006.257.11:57:32.56#ibcon#read 3, iclass 27, count 0 2006.257.11:57:32.56#ibcon#about to read 4, iclass 27, count 0 2006.257.11:57:32.56#ibcon#read 4, iclass 27, count 0 2006.257.11:57:32.56#ibcon#about to read 5, iclass 27, count 0 2006.257.11:57:32.56#ibcon#read 5, iclass 27, count 0 2006.257.11:57:32.56#ibcon#about to read 6, iclass 27, count 0 2006.257.11:57:32.56#ibcon#read 6, iclass 27, count 0 2006.257.11:57:32.56#ibcon#end of sib2, iclass 27, count 0 2006.257.11:57:32.56#ibcon#*after write, iclass 27, count 0 2006.257.11:57:32.56#ibcon#*before return 0, iclass 27, count 0 2006.257.11:57:32.56#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:32.56#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.11:57:32.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.11:57:32.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.11:57:32.56$vck44/vb=6,4 2006.257.11:57:32.56#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.11:57:32.56#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.11:57:32.56#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:32.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:32.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:32.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:32.62#ibcon#enter wrdev, iclass 29, count 2 2006.257.11:57:32.62#ibcon#first serial, iclass 29, count 2 2006.257.11:57:32.62#ibcon#enter sib2, iclass 29, count 2 2006.257.11:57:32.62#ibcon#flushed, iclass 29, count 2 2006.257.11:57:32.62#ibcon#about to write, iclass 29, count 2 2006.257.11:57:32.62#ibcon#wrote, iclass 29, count 2 2006.257.11:57:32.62#ibcon#about to read 3, iclass 29, count 2 2006.257.11:57:32.64#ibcon#read 3, iclass 29, count 2 2006.257.11:57:32.64#ibcon#about to read 4, iclass 29, count 2 2006.257.11:57:32.64#ibcon#read 4, iclass 29, count 2 2006.257.11:57:32.64#ibcon#about to read 5, iclass 29, count 2 2006.257.11:57:32.64#ibcon#read 5, iclass 29, count 2 2006.257.11:57:32.64#ibcon#about to read 6, iclass 29, count 2 2006.257.11:57:32.64#ibcon#read 6, iclass 29, count 2 2006.257.11:57:32.64#ibcon#end of sib2, iclass 29, count 2 2006.257.11:57:32.64#ibcon#*mode == 0, iclass 29, count 2 2006.257.11:57:32.64#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.11:57:32.64#ibcon#[27=AT06-04\r\n] 2006.257.11:57:32.64#ibcon#*before write, iclass 29, count 2 2006.257.11:57:32.64#ibcon#enter sib2, iclass 29, count 2 2006.257.11:57:32.64#ibcon#flushed, iclass 29, count 2 2006.257.11:57:32.64#ibcon#about to write, iclass 29, count 2 2006.257.11:57:32.64#ibcon#wrote, iclass 29, count 2 2006.257.11:57:32.64#ibcon#about to read 3, iclass 29, count 2 2006.257.11:57:32.67#ibcon#read 3, iclass 29, count 2 2006.257.11:57:32.67#ibcon#about to read 4, iclass 29, count 2 2006.257.11:57:32.67#ibcon#read 4, iclass 29, count 2 2006.257.11:57:32.67#ibcon#about to read 5, iclass 29, count 2 2006.257.11:57:32.67#ibcon#read 5, iclass 29, count 2 2006.257.11:57:32.67#ibcon#about to read 6, iclass 29, count 2 2006.257.11:57:32.67#ibcon#read 6, iclass 29, count 2 2006.257.11:57:32.67#ibcon#end of sib2, iclass 29, count 2 2006.257.11:57:32.67#ibcon#*after write, iclass 29, count 2 2006.257.11:57:32.67#ibcon#*before return 0, iclass 29, count 2 2006.257.11:57:32.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:32.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.11:57:32.67#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.11:57:32.67#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:32.67#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:32.79#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:32.79#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:32.79#ibcon#enter wrdev, iclass 29, count 0 2006.257.11:57:32.79#ibcon#first serial, iclass 29, count 0 2006.257.11:57:32.79#ibcon#enter sib2, iclass 29, count 0 2006.257.11:57:32.79#ibcon#flushed, iclass 29, count 0 2006.257.11:57:32.79#ibcon#about to write, iclass 29, count 0 2006.257.11:57:32.79#ibcon#wrote, iclass 29, count 0 2006.257.11:57:32.79#ibcon#about to read 3, iclass 29, count 0 2006.257.11:57:32.81#ibcon#read 3, iclass 29, count 0 2006.257.11:57:32.81#ibcon#about to read 4, iclass 29, count 0 2006.257.11:57:32.81#ibcon#read 4, iclass 29, count 0 2006.257.11:57:32.81#ibcon#about to read 5, iclass 29, count 0 2006.257.11:57:32.81#ibcon#read 5, iclass 29, count 0 2006.257.11:57:32.81#ibcon#about to read 6, iclass 29, count 0 2006.257.11:57:32.81#ibcon#read 6, iclass 29, count 0 2006.257.11:57:32.81#ibcon#end of sib2, iclass 29, count 0 2006.257.11:57:32.81#ibcon#*mode == 0, iclass 29, count 0 2006.257.11:57:32.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.11:57:32.81#ibcon#[27=USB\r\n] 2006.257.11:57:32.81#ibcon#*before write, iclass 29, count 0 2006.257.11:57:32.81#ibcon#enter sib2, iclass 29, count 0 2006.257.11:57:32.81#ibcon#flushed, iclass 29, count 0 2006.257.11:57:32.81#ibcon#about to write, iclass 29, count 0 2006.257.11:57:32.81#ibcon#wrote, iclass 29, count 0 2006.257.11:57:32.81#ibcon#about to read 3, iclass 29, count 0 2006.257.11:57:32.84#ibcon#read 3, iclass 29, count 0 2006.257.11:57:32.84#ibcon#about to read 4, iclass 29, count 0 2006.257.11:57:32.84#ibcon#read 4, iclass 29, count 0 2006.257.11:57:32.84#ibcon#about to read 5, iclass 29, count 0 2006.257.11:57:32.84#ibcon#read 5, iclass 29, count 0 2006.257.11:57:32.84#ibcon#about to read 6, iclass 29, count 0 2006.257.11:57:32.84#ibcon#read 6, iclass 29, count 0 2006.257.11:57:32.84#ibcon#end of sib2, iclass 29, count 0 2006.257.11:57:32.84#ibcon#*after write, iclass 29, count 0 2006.257.11:57:32.84#ibcon#*before return 0, iclass 29, count 0 2006.257.11:57:32.84#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:32.84#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.11:57:32.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.11:57:32.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.11:57:32.84$vck44/vblo=7,734.99 2006.257.11:57:32.84#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.11:57:32.84#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.11:57:32.84#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:32.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:32.84#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:32.84#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:32.84#ibcon#enter wrdev, iclass 31, count 0 2006.257.11:57:32.84#ibcon#first serial, iclass 31, count 0 2006.257.11:57:32.84#ibcon#enter sib2, iclass 31, count 0 2006.257.11:57:32.84#ibcon#flushed, iclass 31, count 0 2006.257.11:57:32.84#ibcon#about to write, iclass 31, count 0 2006.257.11:57:32.84#ibcon#wrote, iclass 31, count 0 2006.257.11:57:32.84#ibcon#about to read 3, iclass 31, count 0 2006.257.11:57:32.86#ibcon#read 3, iclass 31, count 0 2006.257.11:57:32.86#ibcon#about to read 4, iclass 31, count 0 2006.257.11:57:32.86#ibcon#read 4, iclass 31, count 0 2006.257.11:57:32.86#ibcon#about to read 5, iclass 31, count 0 2006.257.11:57:32.86#ibcon#read 5, iclass 31, count 0 2006.257.11:57:32.86#ibcon#about to read 6, iclass 31, count 0 2006.257.11:57:32.86#ibcon#read 6, iclass 31, count 0 2006.257.11:57:32.86#ibcon#end of sib2, iclass 31, count 0 2006.257.11:57:32.86#ibcon#*mode == 0, iclass 31, count 0 2006.257.11:57:32.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.11:57:32.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.11:57:32.86#ibcon#*before write, iclass 31, count 0 2006.257.11:57:32.86#ibcon#enter sib2, iclass 31, count 0 2006.257.11:57:32.86#ibcon#flushed, iclass 31, count 0 2006.257.11:57:32.86#ibcon#about to write, iclass 31, count 0 2006.257.11:57:32.86#ibcon#wrote, iclass 31, count 0 2006.257.11:57:32.86#ibcon#about to read 3, iclass 31, count 0 2006.257.11:57:32.90#ibcon#read 3, iclass 31, count 0 2006.257.11:57:32.90#ibcon#about to read 4, iclass 31, count 0 2006.257.11:57:32.90#ibcon#read 4, iclass 31, count 0 2006.257.11:57:32.90#ibcon#about to read 5, iclass 31, count 0 2006.257.11:57:32.90#ibcon#read 5, iclass 31, count 0 2006.257.11:57:32.90#ibcon#about to read 6, iclass 31, count 0 2006.257.11:57:32.90#ibcon#read 6, iclass 31, count 0 2006.257.11:57:32.90#ibcon#end of sib2, iclass 31, count 0 2006.257.11:57:32.90#ibcon#*after write, iclass 31, count 0 2006.257.11:57:32.90#ibcon#*before return 0, iclass 31, count 0 2006.257.11:57:32.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:32.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.11:57:32.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.11:57:32.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.11:57:32.90$vck44/vb=7,4 2006.257.11:57:32.90#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.11:57:32.90#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.11:57:32.90#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:32.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:32.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:32.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:32.96#ibcon#enter wrdev, iclass 33, count 2 2006.257.11:57:32.96#ibcon#first serial, iclass 33, count 2 2006.257.11:57:32.96#ibcon#enter sib2, iclass 33, count 2 2006.257.11:57:32.96#ibcon#flushed, iclass 33, count 2 2006.257.11:57:32.96#ibcon#about to write, iclass 33, count 2 2006.257.11:57:32.96#ibcon#wrote, iclass 33, count 2 2006.257.11:57:32.96#ibcon#about to read 3, iclass 33, count 2 2006.257.11:57:32.98#ibcon#read 3, iclass 33, count 2 2006.257.11:57:32.98#ibcon#about to read 4, iclass 33, count 2 2006.257.11:57:32.98#ibcon#read 4, iclass 33, count 2 2006.257.11:57:32.98#ibcon#about to read 5, iclass 33, count 2 2006.257.11:57:32.98#ibcon#read 5, iclass 33, count 2 2006.257.11:57:32.98#ibcon#about to read 6, iclass 33, count 2 2006.257.11:57:32.98#ibcon#read 6, iclass 33, count 2 2006.257.11:57:32.98#ibcon#end of sib2, iclass 33, count 2 2006.257.11:57:32.98#ibcon#*mode == 0, iclass 33, count 2 2006.257.11:57:32.98#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.11:57:32.98#ibcon#[27=AT07-04\r\n] 2006.257.11:57:32.98#ibcon#*before write, iclass 33, count 2 2006.257.11:57:32.98#ibcon#enter sib2, iclass 33, count 2 2006.257.11:57:32.98#ibcon#flushed, iclass 33, count 2 2006.257.11:57:32.98#ibcon#about to write, iclass 33, count 2 2006.257.11:57:32.98#ibcon#wrote, iclass 33, count 2 2006.257.11:57:32.98#ibcon#about to read 3, iclass 33, count 2 2006.257.11:57:33.01#ibcon#read 3, iclass 33, count 2 2006.257.11:57:33.01#ibcon#about to read 4, iclass 33, count 2 2006.257.11:57:33.01#ibcon#read 4, iclass 33, count 2 2006.257.11:57:33.01#ibcon#about to read 5, iclass 33, count 2 2006.257.11:57:33.01#ibcon#read 5, iclass 33, count 2 2006.257.11:57:33.01#ibcon#about to read 6, iclass 33, count 2 2006.257.11:57:33.01#ibcon#read 6, iclass 33, count 2 2006.257.11:57:33.01#ibcon#end of sib2, iclass 33, count 2 2006.257.11:57:33.01#ibcon#*after write, iclass 33, count 2 2006.257.11:57:33.01#ibcon#*before return 0, iclass 33, count 2 2006.257.11:57:33.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:33.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.11:57:33.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.11:57:33.01#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:33.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:33.13#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:33.13#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:33.13#ibcon#enter wrdev, iclass 33, count 0 2006.257.11:57:33.13#ibcon#first serial, iclass 33, count 0 2006.257.11:57:33.13#ibcon#enter sib2, iclass 33, count 0 2006.257.11:57:33.13#ibcon#flushed, iclass 33, count 0 2006.257.11:57:33.13#ibcon#about to write, iclass 33, count 0 2006.257.11:57:33.13#ibcon#wrote, iclass 33, count 0 2006.257.11:57:33.13#ibcon#about to read 3, iclass 33, count 0 2006.257.11:57:33.15#ibcon#read 3, iclass 33, count 0 2006.257.11:57:33.15#ibcon#about to read 4, iclass 33, count 0 2006.257.11:57:33.15#ibcon#read 4, iclass 33, count 0 2006.257.11:57:33.15#ibcon#about to read 5, iclass 33, count 0 2006.257.11:57:33.15#ibcon#read 5, iclass 33, count 0 2006.257.11:57:33.15#ibcon#about to read 6, iclass 33, count 0 2006.257.11:57:33.15#ibcon#read 6, iclass 33, count 0 2006.257.11:57:33.15#ibcon#end of sib2, iclass 33, count 0 2006.257.11:57:33.15#ibcon#*mode == 0, iclass 33, count 0 2006.257.11:57:33.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.11:57:33.15#ibcon#[27=USB\r\n] 2006.257.11:57:33.15#ibcon#*before write, iclass 33, count 0 2006.257.11:57:33.15#ibcon#enter sib2, iclass 33, count 0 2006.257.11:57:33.15#ibcon#flushed, iclass 33, count 0 2006.257.11:57:33.15#ibcon#about to write, iclass 33, count 0 2006.257.11:57:33.15#ibcon#wrote, iclass 33, count 0 2006.257.11:57:33.15#ibcon#about to read 3, iclass 33, count 0 2006.257.11:57:33.18#ibcon#read 3, iclass 33, count 0 2006.257.11:57:33.18#ibcon#about to read 4, iclass 33, count 0 2006.257.11:57:33.18#ibcon#read 4, iclass 33, count 0 2006.257.11:57:33.18#ibcon#about to read 5, iclass 33, count 0 2006.257.11:57:33.18#ibcon#read 5, iclass 33, count 0 2006.257.11:57:33.18#ibcon#about to read 6, iclass 33, count 0 2006.257.11:57:33.18#ibcon#read 6, iclass 33, count 0 2006.257.11:57:33.18#ibcon#end of sib2, iclass 33, count 0 2006.257.11:57:33.18#ibcon#*after write, iclass 33, count 0 2006.257.11:57:33.18#ibcon#*before return 0, iclass 33, count 0 2006.257.11:57:33.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:33.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.11:57:33.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.11:57:33.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.11:57:33.18$vck44/vblo=8,744.99 2006.257.11:57:33.18#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.11:57:33.18#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.11:57:33.18#ibcon#ireg 17 cls_cnt 0 2006.257.11:57:33.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:33.18#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:33.18#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:33.18#ibcon#enter wrdev, iclass 35, count 0 2006.257.11:57:33.18#ibcon#first serial, iclass 35, count 0 2006.257.11:57:33.18#ibcon#enter sib2, iclass 35, count 0 2006.257.11:57:33.18#ibcon#flushed, iclass 35, count 0 2006.257.11:57:33.18#ibcon#about to write, iclass 35, count 0 2006.257.11:57:33.18#ibcon#wrote, iclass 35, count 0 2006.257.11:57:33.18#ibcon#about to read 3, iclass 35, count 0 2006.257.11:57:33.20#ibcon#read 3, iclass 35, count 0 2006.257.11:57:33.20#ibcon#about to read 4, iclass 35, count 0 2006.257.11:57:33.20#ibcon#read 4, iclass 35, count 0 2006.257.11:57:33.20#ibcon#about to read 5, iclass 35, count 0 2006.257.11:57:33.20#ibcon#read 5, iclass 35, count 0 2006.257.11:57:33.20#ibcon#about to read 6, iclass 35, count 0 2006.257.11:57:33.20#ibcon#read 6, iclass 35, count 0 2006.257.11:57:33.20#ibcon#end of sib2, iclass 35, count 0 2006.257.11:57:33.20#ibcon#*mode == 0, iclass 35, count 0 2006.257.11:57:33.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.11:57:33.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.11:57:33.20#ibcon#*before write, iclass 35, count 0 2006.257.11:57:33.20#ibcon#enter sib2, iclass 35, count 0 2006.257.11:57:33.20#ibcon#flushed, iclass 35, count 0 2006.257.11:57:33.20#ibcon#about to write, iclass 35, count 0 2006.257.11:57:33.20#ibcon#wrote, iclass 35, count 0 2006.257.11:57:33.20#ibcon#about to read 3, iclass 35, count 0 2006.257.11:57:33.24#ibcon#read 3, iclass 35, count 0 2006.257.11:57:33.24#ibcon#about to read 4, iclass 35, count 0 2006.257.11:57:33.24#ibcon#read 4, iclass 35, count 0 2006.257.11:57:33.24#ibcon#about to read 5, iclass 35, count 0 2006.257.11:57:33.24#ibcon#read 5, iclass 35, count 0 2006.257.11:57:33.24#ibcon#about to read 6, iclass 35, count 0 2006.257.11:57:33.24#ibcon#read 6, iclass 35, count 0 2006.257.11:57:33.24#ibcon#end of sib2, iclass 35, count 0 2006.257.11:57:33.24#ibcon#*after write, iclass 35, count 0 2006.257.11:57:33.24#ibcon#*before return 0, iclass 35, count 0 2006.257.11:57:33.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:33.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.11:57:33.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.11:57:33.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.11:57:33.24$vck44/vb=8,4 2006.257.11:57:33.24#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.11:57:33.24#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.11:57:33.24#ibcon#ireg 11 cls_cnt 2 2006.257.11:57:33.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:33.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:33.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:33.30#ibcon#enter wrdev, iclass 37, count 2 2006.257.11:57:33.30#ibcon#first serial, iclass 37, count 2 2006.257.11:57:33.30#ibcon#enter sib2, iclass 37, count 2 2006.257.11:57:33.30#ibcon#flushed, iclass 37, count 2 2006.257.11:57:33.30#ibcon#about to write, iclass 37, count 2 2006.257.11:57:33.30#ibcon#wrote, iclass 37, count 2 2006.257.11:57:33.30#ibcon#about to read 3, iclass 37, count 2 2006.257.11:57:33.32#ibcon#read 3, iclass 37, count 2 2006.257.11:57:33.32#ibcon#about to read 4, iclass 37, count 2 2006.257.11:57:33.32#ibcon#read 4, iclass 37, count 2 2006.257.11:57:33.32#ibcon#about to read 5, iclass 37, count 2 2006.257.11:57:33.32#ibcon#read 5, iclass 37, count 2 2006.257.11:57:33.32#ibcon#about to read 6, iclass 37, count 2 2006.257.11:57:33.32#ibcon#read 6, iclass 37, count 2 2006.257.11:57:33.32#ibcon#end of sib2, iclass 37, count 2 2006.257.11:57:33.32#ibcon#*mode == 0, iclass 37, count 2 2006.257.11:57:33.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.11:57:33.32#ibcon#[27=AT08-04\r\n] 2006.257.11:57:33.32#ibcon#*before write, iclass 37, count 2 2006.257.11:57:33.32#ibcon#enter sib2, iclass 37, count 2 2006.257.11:57:33.32#ibcon#flushed, iclass 37, count 2 2006.257.11:57:33.32#ibcon#about to write, iclass 37, count 2 2006.257.11:57:33.32#ibcon#wrote, iclass 37, count 2 2006.257.11:57:33.32#ibcon#about to read 3, iclass 37, count 2 2006.257.11:57:33.35#ibcon#read 3, iclass 37, count 2 2006.257.11:57:33.35#ibcon#about to read 4, iclass 37, count 2 2006.257.11:57:33.35#ibcon#read 4, iclass 37, count 2 2006.257.11:57:33.35#ibcon#about to read 5, iclass 37, count 2 2006.257.11:57:33.35#ibcon#read 5, iclass 37, count 2 2006.257.11:57:33.35#ibcon#about to read 6, iclass 37, count 2 2006.257.11:57:33.35#ibcon#read 6, iclass 37, count 2 2006.257.11:57:33.35#ibcon#end of sib2, iclass 37, count 2 2006.257.11:57:33.35#ibcon#*after write, iclass 37, count 2 2006.257.11:57:33.35#ibcon#*before return 0, iclass 37, count 2 2006.257.11:57:33.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:33.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.11:57:33.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.11:57:33.35#ibcon#ireg 7 cls_cnt 0 2006.257.11:57:33.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:33.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:33.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:33.47#ibcon#enter wrdev, iclass 37, count 0 2006.257.11:57:33.47#ibcon#first serial, iclass 37, count 0 2006.257.11:57:33.47#ibcon#enter sib2, iclass 37, count 0 2006.257.11:57:33.47#ibcon#flushed, iclass 37, count 0 2006.257.11:57:33.47#ibcon#about to write, iclass 37, count 0 2006.257.11:57:33.47#ibcon#wrote, iclass 37, count 0 2006.257.11:57:33.47#ibcon#about to read 3, iclass 37, count 0 2006.257.11:57:33.49#ibcon#read 3, iclass 37, count 0 2006.257.11:57:33.49#ibcon#about to read 4, iclass 37, count 0 2006.257.11:57:33.49#ibcon#read 4, iclass 37, count 0 2006.257.11:57:33.49#ibcon#about to read 5, iclass 37, count 0 2006.257.11:57:33.49#ibcon#read 5, iclass 37, count 0 2006.257.11:57:33.49#ibcon#about to read 6, iclass 37, count 0 2006.257.11:57:33.49#ibcon#read 6, iclass 37, count 0 2006.257.11:57:33.49#ibcon#end of sib2, iclass 37, count 0 2006.257.11:57:33.49#ibcon#*mode == 0, iclass 37, count 0 2006.257.11:57:33.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.11:57:33.49#ibcon#[27=USB\r\n] 2006.257.11:57:33.49#ibcon#*before write, iclass 37, count 0 2006.257.11:57:33.49#ibcon#enter sib2, iclass 37, count 0 2006.257.11:57:33.49#ibcon#flushed, iclass 37, count 0 2006.257.11:57:33.49#ibcon#about to write, iclass 37, count 0 2006.257.11:57:33.49#ibcon#wrote, iclass 37, count 0 2006.257.11:57:33.49#ibcon#about to read 3, iclass 37, count 0 2006.257.11:57:33.52#ibcon#read 3, iclass 37, count 0 2006.257.11:57:33.52#ibcon#about to read 4, iclass 37, count 0 2006.257.11:57:33.52#ibcon#read 4, iclass 37, count 0 2006.257.11:57:33.52#ibcon#about to read 5, iclass 37, count 0 2006.257.11:57:33.52#ibcon#read 5, iclass 37, count 0 2006.257.11:57:33.52#ibcon#about to read 6, iclass 37, count 0 2006.257.11:57:33.52#ibcon#read 6, iclass 37, count 0 2006.257.11:57:33.52#ibcon#end of sib2, iclass 37, count 0 2006.257.11:57:33.52#ibcon#*after write, iclass 37, count 0 2006.257.11:57:33.52#ibcon#*before return 0, iclass 37, count 0 2006.257.11:57:33.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:33.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.11:57:33.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.11:57:33.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.11:57:33.52$vck44/vabw=wide 2006.257.11:57:33.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.11:57:33.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.11:57:33.52#ibcon#ireg 8 cls_cnt 0 2006.257.11:57:33.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:33.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:33.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:33.52#ibcon#enter wrdev, iclass 39, count 0 2006.257.11:57:33.52#ibcon#first serial, iclass 39, count 0 2006.257.11:57:33.52#ibcon#enter sib2, iclass 39, count 0 2006.257.11:57:33.52#ibcon#flushed, iclass 39, count 0 2006.257.11:57:33.52#ibcon#about to write, iclass 39, count 0 2006.257.11:57:33.52#ibcon#wrote, iclass 39, count 0 2006.257.11:57:33.52#ibcon#about to read 3, iclass 39, count 0 2006.257.11:57:33.54#ibcon#read 3, iclass 39, count 0 2006.257.11:57:33.54#ibcon#about to read 4, iclass 39, count 0 2006.257.11:57:33.54#ibcon#read 4, iclass 39, count 0 2006.257.11:57:33.54#ibcon#about to read 5, iclass 39, count 0 2006.257.11:57:33.54#ibcon#read 5, iclass 39, count 0 2006.257.11:57:33.54#ibcon#about to read 6, iclass 39, count 0 2006.257.11:57:33.54#ibcon#read 6, iclass 39, count 0 2006.257.11:57:33.54#ibcon#end of sib2, iclass 39, count 0 2006.257.11:57:33.54#ibcon#*mode == 0, iclass 39, count 0 2006.257.11:57:33.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.11:57:33.54#ibcon#[25=BW32\r\n] 2006.257.11:57:33.54#ibcon#*before write, iclass 39, count 0 2006.257.11:57:33.54#ibcon#enter sib2, iclass 39, count 0 2006.257.11:57:33.54#ibcon#flushed, iclass 39, count 0 2006.257.11:57:33.54#ibcon#about to write, iclass 39, count 0 2006.257.11:57:33.54#ibcon#wrote, iclass 39, count 0 2006.257.11:57:33.54#ibcon#about to read 3, iclass 39, count 0 2006.257.11:57:33.57#ibcon#read 3, iclass 39, count 0 2006.257.11:57:33.57#ibcon#about to read 4, iclass 39, count 0 2006.257.11:57:33.57#ibcon#read 4, iclass 39, count 0 2006.257.11:57:33.57#ibcon#about to read 5, iclass 39, count 0 2006.257.11:57:33.57#ibcon#read 5, iclass 39, count 0 2006.257.11:57:33.57#ibcon#about to read 6, iclass 39, count 0 2006.257.11:57:33.57#ibcon#read 6, iclass 39, count 0 2006.257.11:57:33.57#ibcon#end of sib2, iclass 39, count 0 2006.257.11:57:33.57#ibcon#*after write, iclass 39, count 0 2006.257.11:57:33.57#ibcon#*before return 0, iclass 39, count 0 2006.257.11:57:33.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:33.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.11:57:33.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.11:57:33.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.11:57:33.57$vck44/vbbw=wide 2006.257.11:57:33.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.11:57:33.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.11:57:33.57#ibcon#ireg 8 cls_cnt 0 2006.257.11:57:33.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:57:33.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:57:33.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:57:33.64#ibcon#enter wrdev, iclass 3, count 0 2006.257.11:57:33.64#ibcon#first serial, iclass 3, count 0 2006.257.11:57:33.64#ibcon#enter sib2, iclass 3, count 0 2006.257.11:57:33.64#ibcon#flushed, iclass 3, count 0 2006.257.11:57:33.64#ibcon#about to write, iclass 3, count 0 2006.257.11:57:33.64#ibcon#wrote, iclass 3, count 0 2006.257.11:57:33.64#ibcon#about to read 3, iclass 3, count 0 2006.257.11:57:33.66#ibcon#read 3, iclass 3, count 0 2006.257.11:57:33.66#ibcon#about to read 4, iclass 3, count 0 2006.257.11:57:33.66#ibcon#read 4, iclass 3, count 0 2006.257.11:57:33.66#ibcon#about to read 5, iclass 3, count 0 2006.257.11:57:33.66#ibcon#read 5, iclass 3, count 0 2006.257.11:57:33.66#ibcon#about to read 6, iclass 3, count 0 2006.257.11:57:33.66#ibcon#read 6, iclass 3, count 0 2006.257.11:57:33.66#ibcon#end of sib2, iclass 3, count 0 2006.257.11:57:33.66#ibcon#*mode == 0, iclass 3, count 0 2006.257.11:57:33.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.11:57:33.66#ibcon#[27=BW32\r\n] 2006.257.11:57:33.66#ibcon#*before write, iclass 3, count 0 2006.257.11:57:33.66#ibcon#enter sib2, iclass 3, count 0 2006.257.11:57:33.66#ibcon#flushed, iclass 3, count 0 2006.257.11:57:33.66#ibcon#about to write, iclass 3, count 0 2006.257.11:57:33.66#ibcon#wrote, iclass 3, count 0 2006.257.11:57:33.66#ibcon#about to read 3, iclass 3, count 0 2006.257.11:57:33.69#ibcon#read 3, iclass 3, count 0 2006.257.11:57:33.69#ibcon#about to read 4, iclass 3, count 0 2006.257.11:57:33.69#ibcon#read 4, iclass 3, count 0 2006.257.11:57:33.69#ibcon#about to read 5, iclass 3, count 0 2006.257.11:57:33.69#ibcon#read 5, iclass 3, count 0 2006.257.11:57:33.69#ibcon#about to read 6, iclass 3, count 0 2006.257.11:57:33.69#ibcon#read 6, iclass 3, count 0 2006.257.11:57:33.69#ibcon#end of sib2, iclass 3, count 0 2006.257.11:57:33.69#ibcon#*after write, iclass 3, count 0 2006.257.11:57:33.69#ibcon#*before return 0, iclass 3, count 0 2006.257.11:57:33.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:57:33.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.11:57:33.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.11:57:33.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.11:57:33.69$setupk4/ifdk4 2006.257.11:57:33.69$ifdk4/lo= 2006.257.11:57:33.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.11:57:33.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.11:57:33.69$ifdk4/patch= 2006.257.11:57:33.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.11:57:33.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.11:57:33.69$setupk4/!*+20s 2006.257.11:57:39.20#abcon#<5=/14 1.5 3.9 18.21 951013.9\r\n> 2006.257.11:57:39.22#abcon#{5=INTERFACE CLEAR} 2006.257.11:57:39.28#abcon#[5=S1D000X0/0*\r\n] 2006.257.11:57:48.20$setupk4/"tpicd 2006.257.11:57:48.20$setupk4/echo=off 2006.257.11:57:48.20$setupk4/xlog=off 2006.257.11:57:48.20:!2006.257.12:00:04 2006.257.11:57:50.13#trakl#Source acquired 2006.257.11:57:51.13#flagr#flagr/antenna,acquired 2006.257.12:00:04.00:preob 2006.257.12:00:04.14/onsource/TRACKING 2006.257.12:00:04.14:!2006.257.12:00:14 2006.257.12:00:14.00:"tape 2006.257.12:00:14.00:"st=record 2006.257.12:00:14.00:data_valid=on 2006.257.12:00:14.00:midob 2006.257.12:00:15.14/onsource/TRACKING 2006.257.12:00:15.14/wx/18.21,1013.9,95 2006.257.12:00:15.29/cable/+6.4794E-03 2006.257.12:00:16.38/va/01,08,usb,yes,31,33 2006.257.12:00:16.38/va/02,07,usb,yes,34,34 2006.257.12:00:16.38/va/03,08,usb,yes,30,32 2006.257.12:00:16.38/va/04,07,usb,yes,35,36 2006.257.12:00:16.38/va/05,04,usb,yes,31,31 2006.257.12:00:16.38/va/06,04,usb,yes,35,34 2006.257.12:00:16.38/va/07,04,usb,yes,35,36 2006.257.12:00:16.38/va/08,04,usb,yes,29,36 2006.257.12:00:16.61/valo/01,524.99,yes,locked 2006.257.12:00:16.61/valo/02,534.99,yes,locked 2006.257.12:00:16.61/valo/03,564.99,yes,locked 2006.257.12:00:16.61/valo/04,624.99,yes,locked 2006.257.12:00:16.61/valo/05,734.99,yes,locked 2006.257.12:00:16.61/valo/06,814.99,yes,locked 2006.257.12:00:16.61/valo/07,864.99,yes,locked 2006.257.12:00:16.61/valo/08,884.99,yes,locked 2006.257.12:00:17.70/vb/01,04,usb,yes,31,29 2006.257.12:00:17.70/vb/02,05,usb,yes,29,29 2006.257.12:00:17.70/vb/03,04,usb,yes,30,33 2006.257.12:00:17.70/vb/04,05,usb,yes,31,29 2006.257.12:00:17.70/vb/05,04,usb,yes,27,29 2006.257.12:00:17.70/vb/06,04,usb,yes,32,28 2006.257.12:00:17.70/vb/07,04,usb,yes,31,31 2006.257.12:00:17.70/vb/08,04,usb,yes,29,32 2006.257.12:00:17.94/vblo/01,629.99,yes,locked 2006.257.12:00:17.94/vblo/02,634.99,yes,locked 2006.257.12:00:17.94/vblo/03,649.99,yes,locked 2006.257.12:00:17.94/vblo/04,679.99,yes,locked 2006.257.12:00:17.94/vblo/05,709.99,yes,locked 2006.257.12:00:17.94/vblo/06,719.99,yes,locked 2006.257.12:00:17.94/vblo/07,734.99,yes,locked 2006.257.12:00:17.94/vblo/08,744.99,yes,locked 2006.257.12:00:18.09/vabw/8 2006.257.12:00:18.24/vbbw/8 2006.257.12:00:18.40/xfe/off,on,15.2 2006.257.12:00:18.78/ifatt/23,28,28,28 2006.257.12:00:19.08/fmout-gps/S +4.61E-07 2006.257.12:00:19.12:!2006.257.12:00:54 2006.257.12:00:54.00:data_valid=off 2006.257.12:00:54.00:"et 2006.257.12:00:54.00:!+3s 2006.257.12:00:57.02:"tape 2006.257.12:00:57.02:postob 2006.257.12:00:57.11/cable/+6.4788E-03 2006.257.12:00:57.11/wx/18.20,1013.9,95 2006.257.12:00:58.07/fmout-gps/S +4.61E-07 2006.257.12:00:58.07:scan_name=257-1202,jd0609,160 2006.257.12:00:58.07:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.12:00:59.14#flagr#flagr/antenna,new-source 2006.257.12:00:59.14:checkk5 2006.257.12:00:59.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:00:59.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:01:00.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:01:00.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:01:01.13/chk_obsdata//k5ts1/T2571200??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.12:01:01.55/chk_obsdata//k5ts2/T2571200??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.12:01:01.97/chk_obsdata//k5ts3/T2571200??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.12:01:02.38/chk_obsdata//k5ts4/T2571200??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.12:01:03.10/k5log//k5ts1_log_newline 2006.257.12:01:03.82/k5log//k5ts2_log_newline 2006.257.12:01:04.52/k5log//k5ts3_log_newline 2006.257.12:01:05.23/k5log//k5ts4_log_newline 2006.257.12:01:05.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:01:05.25:setupk4=1 2006.257.12:01:05.25$setupk4/echo=on 2006.257.12:01:05.25$setupk4/pcalon 2006.257.12:01:05.25$pcalon/"no phase cal control is implemented here 2006.257.12:01:05.25$setupk4/"tpicd=stop 2006.257.12:01:05.25$setupk4/"rec=synch_on 2006.257.12:01:05.25$setupk4/"rec_mode=128 2006.257.12:01:05.25$setupk4/!* 2006.257.12:01:05.25$setupk4/recpk4 2006.257.12:01:05.25$recpk4/recpatch= 2006.257.12:01:05.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:01:05.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:01:05.25$setupk4/vck44 2006.257.12:01:05.25$vck44/valo=1,524.99 2006.257.12:01:05.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.12:01:05.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.12:01:05.25#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:05.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:05.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:05.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:05.25#ibcon#enter wrdev, iclass 22, count 0 2006.257.12:01:05.25#ibcon#first serial, iclass 22, count 0 2006.257.12:01:05.25#ibcon#enter sib2, iclass 22, count 0 2006.257.12:01:05.25#ibcon#flushed, iclass 22, count 0 2006.257.12:01:05.25#ibcon#about to write, iclass 22, count 0 2006.257.12:01:05.25#ibcon#wrote, iclass 22, count 0 2006.257.12:01:05.25#ibcon#about to read 3, iclass 22, count 0 2006.257.12:01:05.27#ibcon#read 3, iclass 22, count 0 2006.257.12:01:05.27#ibcon#about to read 4, iclass 22, count 0 2006.257.12:01:05.27#ibcon#read 4, iclass 22, count 0 2006.257.12:01:05.27#ibcon#about to read 5, iclass 22, count 0 2006.257.12:01:05.27#ibcon#read 5, iclass 22, count 0 2006.257.12:01:05.27#ibcon#about to read 6, iclass 22, count 0 2006.257.12:01:05.27#ibcon#read 6, iclass 22, count 0 2006.257.12:01:05.27#ibcon#end of sib2, iclass 22, count 0 2006.257.12:01:05.27#ibcon#*mode == 0, iclass 22, count 0 2006.257.12:01:05.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.12:01:05.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:01:05.27#ibcon#*before write, iclass 22, count 0 2006.257.12:01:05.27#ibcon#enter sib2, iclass 22, count 0 2006.257.12:01:05.27#ibcon#flushed, iclass 22, count 0 2006.257.12:01:05.27#ibcon#about to write, iclass 22, count 0 2006.257.12:01:05.27#ibcon#wrote, iclass 22, count 0 2006.257.12:01:05.27#ibcon#about to read 3, iclass 22, count 0 2006.257.12:01:05.32#ibcon#read 3, iclass 22, count 0 2006.257.12:01:05.32#ibcon#about to read 4, iclass 22, count 0 2006.257.12:01:05.32#ibcon#read 4, iclass 22, count 0 2006.257.12:01:05.32#ibcon#about to read 5, iclass 22, count 0 2006.257.12:01:05.32#ibcon#read 5, iclass 22, count 0 2006.257.12:01:05.32#ibcon#about to read 6, iclass 22, count 0 2006.257.12:01:05.32#ibcon#read 6, iclass 22, count 0 2006.257.12:01:05.32#ibcon#end of sib2, iclass 22, count 0 2006.257.12:01:05.32#ibcon#*after write, iclass 22, count 0 2006.257.12:01:05.32#ibcon#*before return 0, iclass 22, count 0 2006.257.12:01:05.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:05.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:05.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.12:01:05.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.12:01:05.32$vck44/va=1,8 2006.257.12:01:05.32#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.12:01:05.32#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.12:01:05.32#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:05.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:05.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:05.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:05.32#ibcon#enter wrdev, iclass 24, count 2 2006.257.12:01:05.32#ibcon#first serial, iclass 24, count 2 2006.257.12:01:05.32#ibcon#enter sib2, iclass 24, count 2 2006.257.12:01:05.32#ibcon#flushed, iclass 24, count 2 2006.257.12:01:05.32#ibcon#about to write, iclass 24, count 2 2006.257.12:01:05.32#ibcon#wrote, iclass 24, count 2 2006.257.12:01:05.32#ibcon#about to read 3, iclass 24, count 2 2006.257.12:01:05.34#ibcon#read 3, iclass 24, count 2 2006.257.12:01:05.34#ibcon#about to read 4, iclass 24, count 2 2006.257.12:01:05.34#ibcon#read 4, iclass 24, count 2 2006.257.12:01:05.34#ibcon#about to read 5, iclass 24, count 2 2006.257.12:01:05.34#ibcon#read 5, iclass 24, count 2 2006.257.12:01:05.34#ibcon#about to read 6, iclass 24, count 2 2006.257.12:01:05.34#ibcon#read 6, iclass 24, count 2 2006.257.12:01:05.34#ibcon#end of sib2, iclass 24, count 2 2006.257.12:01:05.34#ibcon#*mode == 0, iclass 24, count 2 2006.257.12:01:05.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.12:01:05.34#ibcon#[25=AT01-08\r\n] 2006.257.12:01:05.34#ibcon#*before write, iclass 24, count 2 2006.257.12:01:05.34#ibcon#enter sib2, iclass 24, count 2 2006.257.12:01:05.34#ibcon#flushed, iclass 24, count 2 2006.257.12:01:05.34#ibcon#about to write, iclass 24, count 2 2006.257.12:01:05.34#ibcon#wrote, iclass 24, count 2 2006.257.12:01:05.34#ibcon#about to read 3, iclass 24, count 2 2006.257.12:01:05.37#ibcon#read 3, iclass 24, count 2 2006.257.12:01:05.37#ibcon#about to read 4, iclass 24, count 2 2006.257.12:01:05.37#ibcon#read 4, iclass 24, count 2 2006.257.12:01:05.37#ibcon#about to read 5, iclass 24, count 2 2006.257.12:01:05.37#ibcon#read 5, iclass 24, count 2 2006.257.12:01:05.37#ibcon#about to read 6, iclass 24, count 2 2006.257.12:01:05.37#ibcon#read 6, iclass 24, count 2 2006.257.12:01:05.37#ibcon#end of sib2, iclass 24, count 2 2006.257.12:01:05.37#ibcon#*after write, iclass 24, count 2 2006.257.12:01:05.37#ibcon#*before return 0, iclass 24, count 2 2006.257.12:01:05.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:05.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:05.37#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.12:01:05.37#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:05.37#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:05.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:05.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:05.49#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:01:05.49#ibcon#first serial, iclass 24, count 0 2006.257.12:01:05.49#ibcon#enter sib2, iclass 24, count 0 2006.257.12:01:05.49#ibcon#flushed, iclass 24, count 0 2006.257.12:01:05.49#ibcon#about to write, iclass 24, count 0 2006.257.12:01:05.49#ibcon#wrote, iclass 24, count 0 2006.257.12:01:05.49#ibcon#about to read 3, iclass 24, count 0 2006.257.12:01:05.51#ibcon#read 3, iclass 24, count 0 2006.257.12:01:05.51#ibcon#about to read 4, iclass 24, count 0 2006.257.12:01:05.51#ibcon#read 4, iclass 24, count 0 2006.257.12:01:05.51#ibcon#about to read 5, iclass 24, count 0 2006.257.12:01:05.51#ibcon#read 5, iclass 24, count 0 2006.257.12:01:05.51#ibcon#about to read 6, iclass 24, count 0 2006.257.12:01:05.51#ibcon#read 6, iclass 24, count 0 2006.257.12:01:05.51#ibcon#end of sib2, iclass 24, count 0 2006.257.12:01:05.51#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:01:05.51#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:01:05.51#ibcon#[25=USB\r\n] 2006.257.12:01:05.51#ibcon#*before write, iclass 24, count 0 2006.257.12:01:05.51#ibcon#enter sib2, iclass 24, count 0 2006.257.12:01:05.51#ibcon#flushed, iclass 24, count 0 2006.257.12:01:05.51#ibcon#about to write, iclass 24, count 0 2006.257.12:01:05.51#ibcon#wrote, iclass 24, count 0 2006.257.12:01:05.51#ibcon#about to read 3, iclass 24, count 0 2006.257.12:01:05.54#ibcon#read 3, iclass 24, count 0 2006.257.12:01:05.54#ibcon#about to read 4, iclass 24, count 0 2006.257.12:01:05.54#ibcon#read 4, iclass 24, count 0 2006.257.12:01:05.54#ibcon#about to read 5, iclass 24, count 0 2006.257.12:01:05.54#ibcon#read 5, iclass 24, count 0 2006.257.12:01:05.54#ibcon#about to read 6, iclass 24, count 0 2006.257.12:01:05.54#ibcon#read 6, iclass 24, count 0 2006.257.12:01:05.54#ibcon#end of sib2, iclass 24, count 0 2006.257.12:01:05.54#ibcon#*after write, iclass 24, count 0 2006.257.12:01:05.54#ibcon#*before return 0, iclass 24, count 0 2006.257.12:01:05.54#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:05.54#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:05.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:01:05.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:01:05.54$vck44/valo=2,534.99 2006.257.12:01:05.54#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.12:01:05.54#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.12:01:05.54#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:05.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:05.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:05.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:05.54#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:01:05.54#ibcon#first serial, iclass 26, count 0 2006.257.12:01:05.54#ibcon#enter sib2, iclass 26, count 0 2006.257.12:01:05.54#ibcon#flushed, iclass 26, count 0 2006.257.12:01:05.54#ibcon#about to write, iclass 26, count 0 2006.257.12:01:05.54#ibcon#wrote, iclass 26, count 0 2006.257.12:01:05.54#ibcon#about to read 3, iclass 26, count 0 2006.257.12:01:05.56#ibcon#read 3, iclass 26, count 0 2006.257.12:01:05.56#ibcon#about to read 4, iclass 26, count 0 2006.257.12:01:05.56#ibcon#read 4, iclass 26, count 0 2006.257.12:01:05.56#ibcon#about to read 5, iclass 26, count 0 2006.257.12:01:05.56#ibcon#read 5, iclass 26, count 0 2006.257.12:01:05.56#ibcon#about to read 6, iclass 26, count 0 2006.257.12:01:05.56#ibcon#read 6, iclass 26, count 0 2006.257.12:01:05.56#ibcon#end of sib2, iclass 26, count 0 2006.257.12:01:05.56#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:01:05.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:01:05.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:01:05.56#ibcon#*before write, iclass 26, count 0 2006.257.12:01:05.56#ibcon#enter sib2, iclass 26, count 0 2006.257.12:01:05.56#ibcon#flushed, iclass 26, count 0 2006.257.12:01:05.56#ibcon#about to write, iclass 26, count 0 2006.257.12:01:05.56#ibcon#wrote, iclass 26, count 0 2006.257.12:01:05.56#ibcon#about to read 3, iclass 26, count 0 2006.257.12:01:05.60#ibcon#read 3, iclass 26, count 0 2006.257.12:01:05.60#ibcon#about to read 4, iclass 26, count 0 2006.257.12:01:05.60#ibcon#read 4, iclass 26, count 0 2006.257.12:01:05.60#ibcon#about to read 5, iclass 26, count 0 2006.257.12:01:05.60#ibcon#read 5, iclass 26, count 0 2006.257.12:01:05.60#ibcon#about to read 6, iclass 26, count 0 2006.257.12:01:05.60#ibcon#read 6, iclass 26, count 0 2006.257.12:01:05.60#ibcon#end of sib2, iclass 26, count 0 2006.257.12:01:05.60#ibcon#*after write, iclass 26, count 0 2006.257.12:01:05.60#ibcon#*before return 0, iclass 26, count 0 2006.257.12:01:05.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:05.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:05.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:01:05.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:01:05.60$vck44/va=2,7 2006.257.12:01:05.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.12:01:05.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.12:01:05.60#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:05.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:05.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:05.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:05.66#ibcon#enter wrdev, iclass 28, count 2 2006.257.12:01:05.66#ibcon#first serial, iclass 28, count 2 2006.257.12:01:05.66#ibcon#enter sib2, iclass 28, count 2 2006.257.12:01:05.66#ibcon#flushed, iclass 28, count 2 2006.257.12:01:05.66#ibcon#about to write, iclass 28, count 2 2006.257.12:01:05.66#ibcon#wrote, iclass 28, count 2 2006.257.12:01:05.66#ibcon#about to read 3, iclass 28, count 2 2006.257.12:01:05.68#ibcon#read 3, iclass 28, count 2 2006.257.12:01:05.68#ibcon#about to read 4, iclass 28, count 2 2006.257.12:01:05.68#ibcon#read 4, iclass 28, count 2 2006.257.12:01:05.68#ibcon#about to read 5, iclass 28, count 2 2006.257.12:01:05.68#ibcon#read 5, iclass 28, count 2 2006.257.12:01:05.68#ibcon#about to read 6, iclass 28, count 2 2006.257.12:01:05.68#ibcon#read 6, iclass 28, count 2 2006.257.12:01:05.68#ibcon#end of sib2, iclass 28, count 2 2006.257.12:01:05.68#ibcon#*mode == 0, iclass 28, count 2 2006.257.12:01:05.68#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.12:01:05.68#ibcon#[25=AT02-07\r\n] 2006.257.12:01:05.68#ibcon#*before write, iclass 28, count 2 2006.257.12:01:05.68#ibcon#enter sib2, iclass 28, count 2 2006.257.12:01:05.68#ibcon#flushed, iclass 28, count 2 2006.257.12:01:05.68#ibcon#about to write, iclass 28, count 2 2006.257.12:01:05.68#ibcon#wrote, iclass 28, count 2 2006.257.12:01:05.68#ibcon#about to read 3, iclass 28, count 2 2006.257.12:01:05.71#ibcon#read 3, iclass 28, count 2 2006.257.12:01:05.71#ibcon#about to read 4, iclass 28, count 2 2006.257.12:01:05.71#ibcon#read 4, iclass 28, count 2 2006.257.12:01:05.71#ibcon#about to read 5, iclass 28, count 2 2006.257.12:01:05.71#ibcon#read 5, iclass 28, count 2 2006.257.12:01:05.71#ibcon#about to read 6, iclass 28, count 2 2006.257.12:01:05.71#ibcon#read 6, iclass 28, count 2 2006.257.12:01:05.71#ibcon#end of sib2, iclass 28, count 2 2006.257.12:01:05.71#ibcon#*after write, iclass 28, count 2 2006.257.12:01:05.71#ibcon#*before return 0, iclass 28, count 2 2006.257.12:01:05.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:05.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:05.71#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.12:01:05.71#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:05.71#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:05.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:05.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:05.83#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:01:05.83#ibcon#first serial, iclass 28, count 0 2006.257.12:01:05.83#ibcon#enter sib2, iclass 28, count 0 2006.257.12:01:05.83#ibcon#flushed, iclass 28, count 0 2006.257.12:01:05.83#ibcon#about to write, iclass 28, count 0 2006.257.12:01:05.83#ibcon#wrote, iclass 28, count 0 2006.257.12:01:05.83#ibcon#about to read 3, iclass 28, count 0 2006.257.12:01:05.85#ibcon#read 3, iclass 28, count 0 2006.257.12:01:05.85#ibcon#about to read 4, iclass 28, count 0 2006.257.12:01:05.85#ibcon#read 4, iclass 28, count 0 2006.257.12:01:05.85#ibcon#about to read 5, iclass 28, count 0 2006.257.12:01:05.85#ibcon#read 5, iclass 28, count 0 2006.257.12:01:05.85#ibcon#about to read 6, iclass 28, count 0 2006.257.12:01:05.85#ibcon#read 6, iclass 28, count 0 2006.257.12:01:05.85#ibcon#end of sib2, iclass 28, count 0 2006.257.12:01:05.85#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:01:05.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:01:05.85#ibcon#[25=USB\r\n] 2006.257.12:01:05.85#ibcon#*before write, iclass 28, count 0 2006.257.12:01:05.85#ibcon#enter sib2, iclass 28, count 0 2006.257.12:01:05.85#ibcon#flushed, iclass 28, count 0 2006.257.12:01:05.85#ibcon#about to write, iclass 28, count 0 2006.257.12:01:05.85#ibcon#wrote, iclass 28, count 0 2006.257.12:01:05.85#ibcon#about to read 3, iclass 28, count 0 2006.257.12:01:05.88#ibcon#read 3, iclass 28, count 0 2006.257.12:01:05.88#ibcon#about to read 4, iclass 28, count 0 2006.257.12:01:05.88#ibcon#read 4, iclass 28, count 0 2006.257.12:01:05.88#ibcon#about to read 5, iclass 28, count 0 2006.257.12:01:05.88#ibcon#read 5, iclass 28, count 0 2006.257.12:01:05.88#ibcon#about to read 6, iclass 28, count 0 2006.257.12:01:05.88#ibcon#read 6, iclass 28, count 0 2006.257.12:01:05.88#ibcon#end of sib2, iclass 28, count 0 2006.257.12:01:05.88#ibcon#*after write, iclass 28, count 0 2006.257.12:01:05.88#ibcon#*before return 0, iclass 28, count 0 2006.257.12:01:05.88#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:05.88#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:05.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:01:05.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:01:05.88$vck44/valo=3,564.99 2006.257.12:01:05.88#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.12:01:05.88#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.12:01:05.88#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:05.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:05.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:05.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:05.88#ibcon#enter wrdev, iclass 30, count 0 2006.257.12:01:05.88#ibcon#first serial, iclass 30, count 0 2006.257.12:01:05.88#ibcon#enter sib2, iclass 30, count 0 2006.257.12:01:05.88#ibcon#flushed, iclass 30, count 0 2006.257.12:01:05.88#ibcon#about to write, iclass 30, count 0 2006.257.12:01:05.88#ibcon#wrote, iclass 30, count 0 2006.257.12:01:05.88#ibcon#about to read 3, iclass 30, count 0 2006.257.12:01:05.90#ibcon#read 3, iclass 30, count 0 2006.257.12:01:05.90#ibcon#about to read 4, iclass 30, count 0 2006.257.12:01:05.90#ibcon#read 4, iclass 30, count 0 2006.257.12:01:05.90#ibcon#about to read 5, iclass 30, count 0 2006.257.12:01:05.90#ibcon#read 5, iclass 30, count 0 2006.257.12:01:05.90#ibcon#about to read 6, iclass 30, count 0 2006.257.12:01:05.90#ibcon#read 6, iclass 30, count 0 2006.257.12:01:05.90#ibcon#end of sib2, iclass 30, count 0 2006.257.12:01:05.90#ibcon#*mode == 0, iclass 30, count 0 2006.257.12:01:05.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.12:01:05.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:01:05.90#ibcon#*before write, iclass 30, count 0 2006.257.12:01:05.90#ibcon#enter sib2, iclass 30, count 0 2006.257.12:01:05.90#ibcon#flushed, iclass 30, count 0 2006.257.12:01:05.90#ibcon#about to write, iclass 30, count 0 2006.257.12:01:05.90#ibcon#wrote, iclass 30, count 0 2006.257.12:01:05.90#ibcon#about to read 3, iclass 30, count 0 2006.257.12:01:05.94#ibcon#read 3, iclass 30, count 0 2006.257.12:01:05.94#ibcon#about to read 4, iclass 30, count 0 2006.257.12:01:05.94#ibcon#read 4, iclass 30, count 0 2006.257.12:01:05.94#ibcon#about to read 5, iclass 30, count 0 2006.257.12:01:05.94#ibcon#read 5, iclass 30, count 0 2006.257.12:01:05.94#ibcon#about to read 6, iclass 30, count 0 2006.257.12:01:05.94#ibcon#read 6, iclass 30, count 0 2006.257.12:01:05.94#ibcon#end of sib2, iclass 30, count 0 2006.257.12:01:05.94#ibcon#*after write, iclass 30, count 0 2006.257.12:01:05.94#ibcon#*before return 0, iclass 30, count 0 2006.257.12:01:05.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:05.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:05.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.12:01:05.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.12:01:05.94$vck44/va=3,8 2006.257.12:01:05.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.12:01:05.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.12:01:05.94#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:05.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:06.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:06.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:06.00#ibcon#enter wrdev, iclass 32, count 2 2006.257.12:01:06.00#ibcon#first serial, iclass 32, count 2 2006.257.12:01:06.00#ibcon#enter sib2, iclass 32, count 2 2006.257.12:01:06.00#ibcon#flushed, iclass 32, count 2 2006.257.12:01:06.00#ibcon#about to write, iclass 32, count 2 2006.257.12:01:06.00#ibcon#wrote, iclass 32, count 2 2006.257.12:01:06.00#ibcon#about to read 3, iclass 32, count 2 2006.257.12:01:06.02#ibcon#read 3, iclass 32, count 2 2006.257.12:01:06.02#ibcon#about to read 4, iclass 32, count 2 2006.257.12:01:06.02#ibcon#read 4, iclass 32, count 2 2006.257.12:01:06.02#ibcon#about to read 5, iclass 32, count 2 2006.257.12:01:06.02#ibcon#read 5, iclass 32, count 2 2006.257.12:01:06.02#ibcon#about to read 6, iclass 32, count 2 2006.257.12:01:06.02#ibcon#read 6, iclass 32, count 2 2006.257.12:01:06.02#ibcon#end of sib2, iclass 32, count 2 2006.257.12:01:06.02#ibcon#*mode == 0, iclass 32, count 2 2006.257.12:01:06.02#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.12:01:06.02#ibcon#[25=AT03-08\r\n] 2006.257.12:01:06.02#ibcon#*before write, iclass 32, count 2 2006.257.12:01:06.02#ibcon#enter sib2, iclass 32, count 2 2006.257.12:01:06.02#ibcon#flushed, iclass 32, count 2 2006.257.12:01:06.02#ibcon#about to write, iclass 32, count 2 2006.257.12:01:06.02#ibcon#wrote, iclass 32, count 2 2006.257.12:01:06.02#ibcon#about to read 3, iclass 32, count 2 2006.257.12:01:06.05#ibcon#read 3, iclass 32, count 2 2006.257.12:01:06.05#ibcon#about to read 4, iclass 32, count 2 2006.257.12:01:06.05#ibcon#read 4, iclass 32, count 2 2006.257.12:01:06.05#ibcon#about to read 5, iclass 32, count 2 2006.257.12:01:06.05#ibcon#read 5, iclass 32, count 2 2006.257.12:01:06.05#ibcon#about to read 6, iclass 32, count 2 2006.257.12:01:06.05#ibcon#read 6, iclass 32, count 2 2006.257.12:01:06.05#ibcon#end of sib2, iclass 32, count 2 2006.257.12:01:06.05#ibcon#*after write, iclass 32, count 2 2006.257.12:01:06.05#ibcon#*before return 0, iclass 32, count 2 2006.257.12:01:06.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:06.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:06.05#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.12:01:06.05#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:06.05#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:06.17#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:06.17#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:06.17#ibcon#enter wrdev, iclass 32, count 0 2006.257.12:01:06.17#ibcon#first serial, iclass 32, count 0 2006.257.12:01:06.17#ibcon#enter sib2, iclass 32, count 0 2006.257.12:01:06.17#ibcon#flushed, iclass 32, count 0 2006.257.12:01:06.17#ibcon#about to write, iclass 32, count 0 2006.257.12:01:06.17#ibcon#wrote, iclass 32, count 0 2006.257.12:01:06.17#ibcon#about to read 3, iclass 32, count 0 2006.257.12:01:06.19#ibcon#read 3, iclass 32, count 0 2006.257.12:01:06.19#ibcon#about to read 4, iclass 32, count 0 2006.257.12:01:06.19#ibcon#read 4, iclass 32, count 0 2006.257.12:01:06.19#ibcon#about to read 5, iclass 32, count 0 2006.257.12:01:06.19#ibcon#read 5, iclass 32, count 0 2006.257.12:01:06.19#ibcon#about to read 6, iclass 32, count 0 2006.257.12:01:06.19#ibcon#read 6, iclass 32, count 0 2006.257.12:01:06.19#ibcon#end of sib2, iclass 32, count 0 2006.257.12:01:06.19#ibcon#*mode == 0, iclass 32, count 0 2006.257.12:01:06.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.12:01:06.19#ibcon#[25=USB\r\n] 2006.257.12:01:06.19#ibcon#*before write, iclass 32, count 0 2006.257.12:01:06.19#ibcon#enter sib2, iclass 32, count 0 2006.257.12:01:06.19#ibcon#flushed, iclass 32, count 0 2006.257.12:01:06.19#ibcon#about to write, iclass 32, count 0 2006.257.12:01:06.19#ibcon#wrote, iclass 32, count 0 2006.257.12:01:06.19#ibcon#about to read 3, iclass 32, count 0 2006.257.12:01:06.22#ibcon#read 3, iclass 32, count 0 2006.257.12:01:06.22#ibcon#about to read 4, iclass 32, count 0 2006.257.12:01:06.22#ibcon#read 4, iclass 32, count 0 2006.257.12:01:06.22#ibcon#about to read 5, iclass 32, count 0 2006.257.12:01:06.22#ibcon#read 5, iclass 32, count 0 2006.257.12:01:06.22#ibcon#about to read 6, iclass 32, count 0 2006.257.12:01:06.22#ibcon#read 6, iclass 32, count 0 2006.257.12:01:06.22#ibcon#end of sib2, iclass 32, count 0 2006.257.12:01:06.22#ibcon#*after write, iclass 32, count 0 2006.257.12:01:06.22#ibcon#*before return 0, iclass 32, count 0 2006.257.12:01:06.22#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:06.22#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:06.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.12:01:06.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.12:01:06.22$vck44/valo=4,624.99 2006.257.12:01:06.22#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.12:01:06.22#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.12:01:06.22#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:06.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:06.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:06.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:06.22#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:01:06.22#ibcon#first serial, iclass 34, count 0 2006.257.12:01:06.22#ibcon#enter sib2, iclass 34, count 0 2006.257.12:01:06.22#ibcon#flushed, iclass 34, count 0 2006.257.12:01:06.22#ibcon#about to write, iclass 34, count 0 2006.257.12:01:06.22#ibcon#wrote, iclass 34, count 0 2006.257.12:01:06.22#ibcon#about to read 3, iclass 34, count 0 2006.257.12:01:06.24#ibcon#read 3, iclass 34, count 0 2006.257.12:01:06.24#ibcon#about to read 4, iclass 34, count 0 2006.257.12:01:06.24#ibcon#read 4, iclass 34, count 0 2006.257.12:01:06.24#ibcon#about to read 5, iclass 34, count 0 2006.257.12:01:06.24#ibcon#read 5, iclass 34, count 0 2006.257.12:01:06.24#ibcon#about to read 6, iclass 34, count 0 2006.257.12:01:06.24#ibcon#read 6, iclass 34, count 0 2006.257.12:01:06.24#ibcon#end of sib2, iclass 34, count 0 2006.257.12:01:06.24#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:01:06.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:01:06.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:01:06.24#ibcon#*before write, iclass 34, count 0 2006.257.12:01:06.24#ibcon#enter sib2, iclass 34, count 0 2006.257.12:01:06.24#ibcon#flushed, iclass 34, count 0 2006.257.12:01:06.24#ibcon#about to write, iclass 34, count 0 2006.257.12:01:06.24#ibcon#wrote, iclass 34, count 0 2006.257.12:01:06.24#ibcon#about to read 3, iclass 34, count 0 2006.257.12:01:06.28#ibcon#read 3, iclass 34, count 0 2006.257.12:01:06.28#ibcon#about to read 4, iclass 34, count 0 2006.257.12:01:06.28#ibcon#read 4, iclass 34, count 0 2006.257.12:01:06.28#ibcon#about to read 5, iclass 34, count 0 2006.257.12:01:06.28#ibcon#read 5, iclass 34, count 0 2006.257.12:01:06.28#ibcon#about to read 6, iclass 34, count 0 2006.257.12:01:06.28#ibcon#read 6, iclass 34, count 0 2006.257.12:01:06.28#ibcon#end of sib2, iclass 34, count 0 2006.257.12:01:06.28#ibcon#*after write, iclass 34, count 0 2006.257.12:01:06.28#ibcon#*before return 0, iclass 34, count 0 2006.257.12:01:06.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:06.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:06.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:01:06.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:01:06.28$vck44/va=4,7 2006.257.12:01:06.28#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.12:01:06.28#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.12:01:06.28#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:06.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:06.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:06.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:06.34#ibcon#enter wrdev, iclass 36, count 2 2006.257.12:01:06.34#ibcon#first serial, iclass 36, count 2 2006.257.12:01:06.34#ibcon#enter sib2, iclass 36, count 2 2006.257.12:01:06.34#ibcon#flushed, iclass 36, count 2 2006.257.12:01:06.34#ibcon#about to write, iclass 36, count 2 2006.257.12:01:06.34#ibcon#wrote, iclass 36, count 2 2006.257.12:01:06.34#ibcon#about to read 3, iclass 36, count 2 2006.257.12:01:06.36#ibcon#read 3, iclass 36, count 2 2006.257.12:01:06.36#ibcon#about to read 4, iclass 36, count 2 2006.257.12:01:06.36#ibcon#read 4, iclass 36, count 2 2006.257.12:01:06.36#ibcon#about to read 5, iclass 36, count 2 2006.257.12:01:06.36#ibcon#read 5, iclass 36, count 2 2006.257.12:01:06.36#ibcon#about to read 6, iclass 36, count 2 2006.257.12:01:06.36#ibcon#read 6, iclass 36, count 2 2006.257.12:01:06.36#ibcon#end of sib2, iclass 36, count 2 2006.257.12:01:06.36#ibcon#*mode == 0, iclass 36, count 2 2006.257.12:01:06.36#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.12:01:06.36#ibcon#[25=AT04-07\r\n] 2006.257.12:01:06.36#ibcon#*before write, iclass 36, count 2 2006.257.12:01:06.36#ibcon#enter sib2, iclass 36, count 2 2006.257.12:01:06.36#ibcon#flushed, iclass 36, count 2 2006.257.12:01:06.36#ibcon#about to write, iclass 36, count 2 2006.257.12:01:06.36#ibcon#wrote, iclass 36, count 2 2006.257.12:01:06.36#ibcon#about to read 3, iclass 36, count 2 2006.257.12:01:06.39#ibcon#read 3, iclass 36, count 2 2006.257.12:01:06.39#ibcon#about to read 4, iclass 36, count 2 2006.257.12:01:06.39#ibcon#read 4, iclass 36, count 2 2006.257.12:01:06.39#ibcon#about to read 5, iclass 36, count 2 2006.257.12:01:06.39#ibcon#read 5, iclass 36, count 2 2006.257.12:01:06.39#ibcon#about to read 6, iclass 36, count 2 2006.257.12:01:06.39#ibcon#read 6, iclass 36, count 2 2006.257.12:01:06.39#ibcon#end of sib2, iclass 36, count 2 2006.257.12:01:06.39#ibcon#*after write, iclass 36, count 2 2006.257.12:01:06.39#ibcon#*before return 0, iclass 36, count 2 2006.257.12:01:06.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:06.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:06.39#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.12:01:06.39#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:06.39#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:06.51#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:06.51#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:06.51#ibcon#enter wrdev, iclass 36, count 0 2006.257.12:01:06.51#ibcon#first serial, iclass 36, count 0 2006.257.12:01:06.51#ibcon#enter sib2, iclass 36, count 0 2006.257.12:01:06.51#ibcon#flushed, iclass 36, count 0 2006.257.12:01:06.51#ibcon#about to write, iclass 36, count 0 2006.257.12:01:06.51#ibcon#wrote, iclass 36, count 0 2006.257.12:01:06.51#ibcon#about to read 3, iclass 36, count 0 2006.257.12:01:06.53#ibcon#read 3, iclass 36, count 0 2006.257.12:01:06.53#ibcon#about to read 4, iclass 36, count 0 2006.257.12:01:06.53#ibcon#read 4, iclass 36, count 0 2006.257.12:01:06.53#ibcon#about to read 5, iclass 36, count 0 2006.257.12:01:06.53#ibcon#read 5, iclass 36, count 0 2006.257.12:01:06.53#ibcon#about to read 6, iclass 36, count 0 2006.257.12:01:06.53#ibcon#read 6, iclass 36, count 0 2006.257.12:01:06.53#ibcon#end of sib2, iclass 36, count 0 2006.257.12:01:06.53#ibcon#*mode == 0, iclass 36, count 0 2006.257.12:01:06.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.12:01:06.53#ibcon#[25=USB\r\n] 2006.257.12:01:06.53#ibcon#*before write, iclass 36, count 0 2006.257.12:01:06.53#ibcon#enter sib2, iclass 36, count 0 2006.257.12:01:06.53#ibcon#flushed, iclass 36, count 0 2006.257.12:01:06.53#ibcon#about to write, iclass 36, count 0 2006.257.12:01:06.53#ibcon#wrote, iclass 36, count 0 2006.257.12:01:06.53#ibcon#about to read 3, iclass 36, count 0 2006.257.12:01:06.56#ibcon#read 3, iclass 36, count 0 2006.257.12:01:06.56#ibcon#about to read 4, iclass 36, count 0 2006.257.12:01:06.56#ibcon#read 4, iclass 36, count 0 2006.257.12:01:06.56#ibcon#about to read 5, iclass 36, count 0 2006.257.12:01:06.56#ibcon#read 5, iclass 36, count 0 2006.257.12:01:06.56#ibcon#about to read 6, iclass 36, count 0 2006.257.12:01:06.56#ibcon#read 6, iclass 36, count 0 2006.257.12:01:06.56#ibcon#end of sib2, iclass 36, count 0 2006.257.12:01:06.56#ibcon#*after write, iclass 36, count 0 2006.257.12:01:06.56#ibcon#*before return 0, iclass 36, count 0 2006.257.12:01:06.56#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:06.56#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:06.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.12:01:06.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.12:01:06.56$vck44/valo=5,734.99 2006.257.12:01:06.56#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.12:01:06.56#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.12:01:06.56#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:06.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:06.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:06.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:06.56#ibcon#enter wrdev, iclass 38, count 0 2006.257.12:01:06.56#ibcon#first serial, iclass 38, count 0 2006.257.12:01:06.56#ibcon#enter sib2, iclass 38, count 0 2006.257.12:01:06.56#ibcon#flushed, iclass 38, count 0 2006.257.12:01:06.56#ibcon#about to write, iclass 38, count 0 2006.257.12:01:06.56#ibcon#wrote, iclass 38, count 0 2006.257.12:01:06.56#ibcon#about to read 3, iclass 38, count 0 2006.257.12:01:06.58#ibcon#read 3, iclass 38, count 0 2006.257.12:01:06.58#ibcon#about to read 4, iclass 38, count 0 2006.257.12:01:06.58#ibcon#read 4, iclass 38, count 0 2006.257.12:01:06.58#ibcon#about to read 5, iclass 38, count 0 2006.257.12:01:06.58#ibcon#read 5, iclass 38, count 0 2006.257.12:01:06.58#ibcon#about to read 6, iclass 38, count 0 2006.257.12:01:06.58#ibcon#read 6, iclass 38, count 0 2006.257.12:01:06.58#ibcon#end of sib2, iclass 38, count 0 2006.257.12:01:06.58#ibcon#*mode == 0, iclass 38, count 0 2006.257.12:01:06.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.12:01:06.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:01:06.58#ibcon#*before write, iclass 38, count 0 2006.257.12:01:06.58#ibcon#enter sib2, iclass 38, count 0 2006.257.12:01:06.58#ibcon#flushed, iclass 38, count 0 2006.257.12:01:06.58#ibcon#about to write, iclass 38, count 0 2006.257.12:01:06.58#ibcon#wrote, iclass 38, count 0 2006.257.12:01:06.58#ibcon#about to read 3, iclass 38, count 0 2006.257.12:01:06.62#ibcon#read 3, iclass 38, count 0 2006.257.12:01:06.62#ibcon#about to read 4, iclass 38, count 0 2006.257.12:01:06.62#ibcon#read 4, iclass 38, count 0 2006.257.12:01:06.62#ibcon#about to read 5, iclass 38, count 0 2006.257.12:01:06.62#ibcon#read 5, iclass 38, count 0 2006.257.12:01:06.62#ibcon#about to read 6, iclass 38, count 0 2006.257.12:01:06.62#ibcon#read 6, iclass 38, count 0 2006.257.12:01:06.62#ibcon#end of sib2, iclass 38, count 0 2006.257.12:01:06.62#ibcon#*after write, iclass 38, count 0 2006.257.12:01:06.62#ibcon#*before return 0, iclass 38, count 0 2006.257.12:01:06.62#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:06.62#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:06.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.12:01:06.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.12:01:06.62$vck44/va=5,4 2006.257.12:01:06.62#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.12:01:06.62#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.12:01:06.62#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:06.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:06.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:06.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:06.68#ibcon#enter wrdev, iclass 40, count 2 2006.257.12:01:06.68#ibcon#first serial, iclass 40, count 2 2006.257.12:01:06.68#ibcon#enter sib2, iclass 40, count 2 2006.257.12:01:06.68#ibcon#flushed, iclass 40, count 2 2006.257.12:01:06.68#ibcon#about to write, iclass 40, count 2 2006.257.12:01:06.68#ibcon#wrote, iclass 40, count 2 2006.257.12:01:06.68#ibcon#about to read 3, iclass 40, count 2 2006.257.12:01:06.70#ibcon#read 3, iclass 40, count 2 2006.257.12:01:06.70#ibcon#about to read 4, iclass 40, count 2 2006.257.12:01:06.70#ibcon#read 4, iclass 40, count 2 2006.257.12:01:06.70#ibcon#about to read 5, iclass 40, count 2 2006.257.12:01:06.70#ibcon#read 5, iclass 40, count 2 2006.257.12:01:06.70#ibcon#about to read 6, iclass 40, count 2 2006.257.12:01:06.70#ibcon#read 6, iclass 40, count 2 2006.257.12:01:06.70#ibcon#end of sib2, iclass 40, count 2 2006.257.12:01:06.70#ibcon#*mode == 0, iclass 40, count 2 2006.257.12:01:06.70#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.12:01:06.70#ibcon#[25=AT05-04\r\n] 2006.257.12:01:06.70#ibcon#*before write, iclass 40, count 2 2006.257.12:01:06.70#ibcon#enter sib2, iclass 40, count 2 2006.257.12:01:06.70#ibcon#flushed, iclass 40, count 2 2006.257.12:01:06.70#ibcon#about to write, iclass 40, count 2 2006.257.12:01:06.70#ibcon#wrote, iclass 40, count 2 2006.257.12:01:06.70#ibcon#about to read 3, iclass 40, count 2 2006.257.12:01:06.73#ibcon#read 3, iclass 40, count 2 2006.257.12:01:06.73#ibcon#about to read 4, iclass 40, count 2 2006.257.12:01:06.73#ibcon#read 4, iclass 40, count 2 2006.257.12:01:06.73#ibcon#about to read 5, iclass 40, count 2 2006.257.12:01:06.73#ibcon#read 5, iclass 40, count 2 2006.257.12:01:06.73#ibcon#about to read 6, iclass 40, count 2 2006.257.12:01:06.73#ibcon#read 6, iclass 40, count 2 2006.257.12:01:06.73#ibcon#end of sib2, iclass 40, count 2 2006.257.12:01:06.73#ibcon#*after write, iclass 40, count 2 2006.257.12:01:06.73#ibcon#*before return 0, iclass 40, count 2 2006.257.12:01:06.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:06.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:06.73#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.12:01:06.73#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:06.73#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:06.85#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:06.85#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:06.85#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:01:06.85#ibcon#first serial, iclass 40, count 0 2006.257.12:01:06.85#ibcon#enter sib2, iclass 40, count 0 2006.257.12:01:06.85#ibcon#flushed, iclass 40, count 0 2006.257.12:01:06.85#ibcon#about to write, iclass 40, count 0 2006.257.12:01:06.85#ibcon#wrote, iclass 40, count 0 2006.257.12:01:06.85#ibcon#about to read 3, iclass 40, count 0 2006.257.12:01:06.87#ibcon#read 3, iclass 40, count 0 2006.257.12:01:06.87#ibcon#about to read 4, iclass 40, count 0 2006.257.12:01:06.87#ibcon#read 4, iclass 40, count 0 2006.257.12:01:06.87#ibcon#about to read 5, iclass 40, count 0 2006.257.12:01:06.87#ibcon#read 5, iclass 40, count 0 2006.257.12:01:06.87#ibcon#about to read 6, iclass 40, count 0 2006.257.12:01:06.87#ibcon#read 6, iclass 40, count 0 2006.257.12:01:06.87#ibcon#end of sib2, iclass 40, count 0 2006.257.12:01:06.87#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:01:06.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:01:06.87#ibcon#[25=USB\r\n] 2006.257.12:01:06.87#ibcon#*before write, iclass 40, count 0 2006.257.12:01:06.87#ibcon#enter sib2, iclass 40, count 0 2006.257.12:01:06.87#ibcon#flushed, iclass 40, count 0 2006.257.12:01:06.87#ibcon#about to write, iclass 40, count 0 2006.257.12:01:06.87#ibcon#wrote, iclass 40, count 0 2006.257.12:01:06.87#ibcon#about to read 3, iclass 40, count 0 2006.257.12:01:06.90#ibcon#read 3, iclass 40, count 0 2006.257.12:01:06.90#ibcon#about to read 4, iclass 40, count 0 2006.257.12:01:06.90#ibcon#read 4, iclass 40, count 0 2006.257.12:01:06.90#ibcon#about to read 5, iclass 40, count 0 2006.257.12:01:06.90#ibcon#read 5, iclass 40, count 0 2006.257.12:01:06.90#ibcon#about to read 6, iclass 40, count 0 2006.257.12:01:06.90#ibcon#read 6, iclass 40, count 0 2006.257.12:01:06.90#ibcon#end of sib2, iclass 40, count 0 2006.257.12:01:06.90#ibcon#*after write, iclass 40, count 0 2006.257.12:01:06.90#ibcon#*before return 0, iclass 40, count 0 2006.257.12:01:06.90#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:06.90#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:06.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:01:06.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:01:06.90$vck44/valo=6,814.99 2006.257.12:01:06.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.12:01:06.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.12:01:06.90#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:06.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:06.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:06.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:06.90#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:01:06.90#ibcon#first serial, iclass 4, count 0 2006.257.12:01:06.90#ibcon#enter sib2, iclass 4, count 0 2006.257.12:01:06.90#ibcon#flushed, iclass 4, count 0 2006.257.12:01:06.90#ibcon#about to write, iclass 4, count 0 2006.257.12:01:06.90#ibcon#wrote, iclass 4, count 0 2006.257.12:01:06.90#ibcon#about to read 3, iclass 4, count 0 2006.257.12:01:06.92#ibcon#read 3, iclass 4, count 0 2006.257.12:01:06.92#ibcon#about to read 4, iclass 4, count 0 2006.257.12:01:06.92#ibcon#read 4, iclass 4, count 0 2006.257.12:01:06.92#ibcon#about to read 5, iclass 4, count 0 2006.257.12:01:06.92#ibcon#read 5, iclass 4, count 0 2006.257.12:01:06.92#ibcon#about to read 6, iclass 4, count 0 2006.257.12:01:06.92#ibcon#read 6, iclass 4, count 0 2006.257.12:01:06.92#ibcon#end of sib2, iclass 4, count 0 2006.257.12:01:06.92#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:01:06.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:01:06.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:01:06.92#ibcon#*before write, iclass 4, count 0 2006.257.12:01:06.92#ibcon#enter sib2, iclass 4, count 0 2006.257.12:01:06.92#ibcon#flushed, iclass 4, count 0 2006.257.12:01:06.92#ibcon#about to write, iclass 4, count 0 2006.257.12:01:06.92#ibcon#wrote, iclass 4, count 0 2006.257.12:01:06.92#ibcon#about to read 3, iclass 4, count 0 2006.257.12:01:06.96#ibcon#read 3, iclass 4, count 0 2006.257.12:01:06.96#ibcon#about to read 4, iclass 4, count 0 2006.257.12:01:06.96#ibcon#read 4, iclass 4, count 0 2006.257.12:01:06.96#ibcon#about to read 5, iclass 4, count 0 2006.257.12:01:06.96#ibcon#read 5, iclass 4, count 0 2006.257.12:01:06.96#ibcon#about to read 6, iclass 4, count 0 2006.257.12:01:06.96#ibcon#read 6, iclass 4, count 0 2006.257.12:01:06.96#ibcon#end of sib2, iclass 4, count 0 2006.257.12:01:06.96#ibcon#*after write, iclass 4, count 0 2006.257.12:01:06.96#ibcon#*before return 0, iclass 4, count 0 2006.257.12:01:06.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:06.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:06.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:01:06.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:01:06.96$vck44/va=6,4 2006.257.12:01:06.96#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.12:01:06.96#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.12:01:06.96#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:06.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:07.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:07.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:07.02#ibcon#enter wrdev, iclass 6, count 2 2006.257.12:01:07.02#ibcon#first serial, iclass 6, count 2 2006.257.12:01:07.02#ibcon#enter sib2, iclass 6, count 2 2006.257.12:01:07.02#ibcon#flushed, iclass 6, count 2 2006.257.12:01:07.02#ibcon#about to write, iclass 6, count 2 2006.257.12:01:07.02#ibcon#wrote, iclass 6, count 2 2006.257.12:01:07.02#ibcon#about to read 3, iclass 6, count 2 2006.257.12:01:07.04#ibcon#read 3, iclass 6, count 2 2006.257.12:01:07.04#ibcon#about to read 4, iclass 6, count 2 2006.257.12:01:07.04#ibcon#read 4, iclass 6, count 2 2006.257.12:01:07.04#ibcon#about to read 5, iclass 6, count 2 2006.257.12:01:07.04#ibcon#read 5, iclass 6, count 2 2006.257.12:01:07.04#ibcon#about to read 6, iclass 6, count 2 2006.257.12:01:07.04#ibcon#read 6, iclass 6, count 2 2006.257.12:01:07.04#ibcon#end of sib2, iclass 6, count 2 2006.257.12:01:07.04#ibcon#*mode == 0, iclass 6, count 2 2006.257.12:01:07.04#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.12:01:07.04#ibcon#[25=AT06-04\r\n] 2006.257.12:01:07.04#ibcon#*before write, iclass 6, count 2 2006.257.12:01:07.04#ibcon#enter sib2, iclass 6, count 2 2006.257.12:01:07.04#ibcon#flushed, iclass 6, count 2 2006.257.12:01:07.04#ibcon#about to write, iclass 6, count 2 2006.257.12:01:07.04#ibcon#wrote, iclass 6, count 2 2006.257.12:01:07.04#ibcon#about to read 3, iclass 6, count 2 2006.257.12:01:07.07#ibcon#read 3, iclass 6, count 2 2006.257.12:01:07.07#ibcon#about to read 4, iclass 6, count 2 2006.257.12:01:07.07#ibcon#read 4, iclass 6, count 2 2006.257.12:01:07.07#ibcon#about to read 5, iclass 6, count 2 2006.257.12:01:07.07#ibcon#read 5, iclass 6, count 2 2006.257.12:01:07.07#ibcon#about to read 6, iclass 6, count 2 2006.257.12:01:07.07#ibcon#read 6, iclass 6, count 2 2006.257.12:01:07.07#ibcon#end of sib2, iclass 6, count 2 2006.257.12:01:07.07#ibcon#*after write, iclass 6, count 2 2006.257.12:01:07.07#ibcon#*before return 0, iclass 6, count 2 2006.257.12:01:07.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:07.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:07.07#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.12:01:07.07#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:07.07#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:07.19#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:07.19#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:07.19#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:01:07.19#ibcon#first serial, iclass 6, count 0 2006.257.12:01:07.19#ibcon#enter sib2, iclass 6, count 0 2006.257.12:01:07.19#ibcon#flushed, iclass 6, count 0 2006.257.12:01:07.19#ibcon#about to write, iclass 6, count 0 2006.257.12:01:07.19#ibcon#wrote, iclass 6, count 0 2006.257.12:01:07.19#ibcon#about to read 3, iclass 6, count 0 2006.257.12:01:07.21#ibcon#read 3, iclass 6, count 0 2006.257.12:01:07.21#ibcon#about to read 4, iclass 6, count 0 2006.257.12:01:07.21#ibcon#read 4, iclass 6, count 0 2006.257.12:01:07.21#ibcon#about to read 5, iclass 6, count 0 2006.257.12:01:07.21#ibcon#read 5, iclass 6, count 0 2006.257.12:01:07.21#ibcon#about to read 6, iclass 6, count 0 2006.257.12:01:07.21#ibcon#read 6, iclass 6, count 0 2006.257.12:01:07.21#ibcon#end of sib2, iclass 6, count 0 2006.257.12:01:07.21#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:01:07.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:01:07.21#ibcon#[25=USB\r\n] 2006.257.12:01:07.21#ibcon#*before write, iclass 6, count 0 2006.257.12:01:07.21#ibcon#enter sib2, iclass 6, count 0 2006.257.12:01:07.21#ibcon#flushed, iclass 6, count 0 2006.257.12:01:07.21#ibcon#about to write, iclass 6, count 0 2006.257.12:01:07.21#ibcon#wrote, iclass 6, count 0 2006.257.12:01:07.21#ibcon#about to read 3, iclass 6, count 0 2006.257.12:01:07.24#ibcon#read 3, iclass 6, count 0 2006.257.12:01:07.24#ibcon#about to read 4, iclass 6, count 0 2006.257.12:01:07.24#ibcon#read 4, iclass 6, count 0 2006.257.12:01:07.24#ibcon#about to read 5, iclass 6, count 0 2006.257.12:01:07.24#ibcon#read 5, iclass 6, count 0 2006.257.12:01:07.24#ibcon#about to read 6, iclass 6, count 0 2006.257.12:01:07.24#ibcon#read 6, iclass 6, count 0 2006.257.12:01:07.24#ibcon#end of sib2, iclass 6, count 0 2006.257.12:01:07.24#ibcon#*after write, iclass 6, count 0 2006.257.12:01:07.24#ibcon#*before return 0, iclass 6, count 0 2006.257.12:01:07.24#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:07.24#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:07.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:01:07.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:01:07.24$vck44/valo=7,864.99 2006.257.12:01:07.24#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.12:01:07.24#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.12:01:07.24#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:07.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:07.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:07.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:07.24#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:01:07.24#ibcon#first serial, iclass 10, count 0 2006.257.12:01:07.24#ibcon#enter sib2, iclass 10, count 0 2006.257.12:01:07.24#ibcon#flushed, iclass 10, count 0 2006.257.12:01:07.24#ibcon#about to write, iclass 10, count 0 2006.257.12:01:07.24#ibcon#wrote, iclass 10, count 0 2006.257.12:01:07.24#ibcon#about to read 3, iclass 10, count 0 2006.257.12:01:07.26#ibcon#read 3, iclass 10, count 0 2006.257.12:01:07.26#ibcon#about to read 4, iclass 10, count 0 2006.257.12:01:07.26#ibcon#read 4, iclass 10, count 0 2006.257.12:01:07.26#ibcon#about to read 5, iclass 10, count 0 2006.257.12:01:07.26#ibcon#read 5, iclass 10, count 0 2006.257.12:01:07.26#ibcon#about to read 6, iclass 10, count 0 2006.257.12:01:07.26#ibcon#read 6, iclass 10, count 0 2006.257.12:01:07.26#ibcon#end of sib2, iclass 10, count 0 2006.257.12:01:07.26#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:01:07.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:01:07.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:01:07.26#ibcon#*before write, iclass 10, count 0 2006.257.12:01:07.26#ibcon#enter sib2, iclass 10, count 0 2006.257.12:01:07.26#ibcon#flushed, iclass 10, count 0 2006.257.12:01:07.26#ibcon#about to write, iclass 10, count 0 2006.257.12:01:07.26#ibcon#wrote, iclass 10, count 0 2006.257.12:01:07.26#ibcon#about to read 3, iclass 10, count 0 2006.257.12:01:07.30#ibcon#read 3, iclass 10, count 0 2006.257.12:01:07.30#ibcon#about to read 4, iclass 10, count 0 2006.257.12:01:07.30#ibcon#read 4, iclass 10, count 0 2006.257.12:01:07.30#ibcon#about to read 5, iclass 10, count 0 2006.257.12:01:07.30#ibcon#read 5, iclass 10, count 0 2006.257.12:01:07.30#ibcon#about to read 6, iclass 10, count 0 2006.257.12:01:07.30#ibcon#read 6, iclass 10, count 0 2006.257.12:01:07.30#ibcon#end of sib2, iclass 10, count 0 2006.257.12:01:07.30#ibcon#*after write, iclass 10, count 0 2006.257.12:01:07.30#ibcon#*before return 0, iclass 10, count 0 2006.257.12:01:07.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:07.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:07.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:01:07.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:01:07.30$vck44/va=7,4 2006.257.12:01:07.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.12:01:07.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.12:01:07.30#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:07.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:07.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:07.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:07.36#ibcon#enter wrdev, iclass 12, count 2 2006.257.12:01:07.36#ibcon#first serial, iclass 12, count 2 2006.257.12:01:07.36#ibcon#enter sib2, iclass 12, count 2 2006.257.12:01:07.36#ibcon#flushed, iclass 12, count 2 2006.257.12:01:07.36#ibcon#about to write, iclass 12, count 2 2006.257.12:01:07.36#ibcon#wrote, iclass 12, count 2 2006.257.12:01:07.36#ibcon#about to read 3, iclass 12, count 2 2006.257.12:01:07.38#ibcon#read 3, iclass 12, count 2 2006.257.12:01:07.38#ibcon#about to read 4, iclass 12, count 2 2006.257.12:01:07.38#ibcon#read 4, iclass 12, count 2 2006.257.12:01:07.38#ibcon#about to read 5, iclass 12, count 2 2006.257.12:01:07.38#ibcon#read 5, iclass 12, count 2 2006.257.12:01:07.38#ibcon#about to read 6, iclass 12, count 2 2006.257.12:01:07.38#ibcon#read 6, iclass 12, count 2 2006.257.12:01:07.38#ibcon#end of sib2, iclass 12, count 2 2006.257.12:01:07.38#ibcon#*mode == 0, iclass 12, count 2 2006.257.12:01:07.38#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.12:01:07.38#ibcon#[25=AT07-04\r\n] 2006.257.12:01:07.38#ibcon#*before write, iclass 12, count 2 2006.257.12:01:07.38#ibcon#enter sib2, iclass 12, count 2 2006.257.12:01:07.38#ibcon#flushed, iclass 12, count 2 2006.257.12:01:07.38#ibcon#about to write, iclass 12, count 2 2006.257.12:01:07.38#ibcon#wrote, iclass 12, count 2 2006.257.12:01:07.38#ibcon#about to read 3, iclass 12, count 2 2006.257.12:01:07.41#ibcon#read 3, iclass 12, count 2 2006.257.12:01:07.41#ibcon#about to read 4, iclass 12, count 2 2006.257.12:01:07.41#ibcon#read 4, iclass 12, count 2 2006.257.12:01:07.41#ibcon#about to read 5, iclass 12, count 2 2006.257.12:01:07.41#ibcon#read 5, iclass 12, count 2 2006.257.12:01:07.41#ibcon#about to read 6, iclass 12, count 2 2006.257.12:01:07.41#ibcon#read 6, iclass 12, count 2 2006.257.12:01:07.41#ibcon#end of sib2, iclass 12, count 2 2006.257.12:01:07.41#ibcon#*after write, iclass 12, count 2 2006.257.12:01:07.41#ibcon#*before return 0, iclass 12, count 2 2006.257.12:01:07.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:07.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:07.41#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.12:01:07.41#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:07.41#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:07.53#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:07.53#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:07.53#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:01:07.53#ibcon#first serial, iclass 12, count 0 2006.257.12:01:07.53#ibcon#enter sib2, iclass 12, count 0 2006.257.12:01:07.53#ibcon#flushed, iclass 12, count 0 2006.257.12:01:07.53#ibcon#about to write, iclass 12, count 0 2006.257.12:01:07.53#ibcon#wrote, iclass 12, count 0 2006.257.12:01:07.53#ibcon#about to read 3, iclass 12, count 0 2006.257.12:01:07.55#ibcon#read 3, iclass 12, count 0 2006.257.12:01:07.55#ibcon#about to read 4, iclass 12, count 0 2006.257.12:01:07.55#ibcon#read 4, iclass 12, count 0 2006.257.12:01:07.55#ibcon#about to read 5, iclass 12, count 0 2006.257.12:01:07.55#ibcon#read 5, iclass 12, count 0 2006.257.12:01:07.55#ibcon#about to read 6, iclass 12, count 0 2006.257.12:01:07.55#ibcon#read 6, iclass 12, count 0 2006.257.12:01:07.55#ibcon#end of sib2, iclass 12, count 0 2006.257.12:01:07.55#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:01:07.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:01:07.55#ibcon#[25=USB\r\n] 2006.257.12:01:07.55#ibcon#*before write, iclass 12, count 0 2006.257.12:01:07.55#ibcon#enter sib2, iclass 12, count 0 2006.257.12:01:07.55#ibcon#flushed, iclass 12, count 0 2006.257.12:01:07.55#ibcon#about to write, iclass 12, count 0 2006.257.12:01:07.55#ibcon#wrote, iclass 12, count 0 2006.257.12:01:07.55#ibcon#about to read 3, iclass 12, count 0 2006.257.12:01:07.58#ibcon#read 3, iclass 12, count 0 2006.257.12:01:07.58#ibcon#about to read 4, iclass 12, count 0 2006.257.12:01:07.58#ibcon#read 4, iclass 12, count 0 2006.257.12:01:07.58#ibcon#about to read 5, iclass 12, count 0 2006.257.12:01:07.58#ibcon#read 5, iclass 12, count 0 2006.257.12:01:07.58#ibcon#about to read 6, iclass 12, count 0 2006.257.12:01:07.58#ibcon#read 6, iclass 12, count 0 2006.257.12:01:07.58#ibcon#end of sib2, iclass 12, count 0 2006.257.12:01:07.58#ibcon#*after write, iclass 12, count 0 2006.257.12:01:07.58#ibcon#*before return 0, iclass 12, count 0 2006.257.12:01:07.58#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:07.58#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:07.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:01:07.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:01:07.58$vck44/valo=8,884.99 2006.257.12:01:07.58#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.12:01:07.58#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.12:01:07.58#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:07.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:07.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:07.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:07.58#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:01:07.58#ibcon#first serial, iclass 14, count 0 2006.257.12:01:07.58#ibcon#enter sib2, iclass 14, count 0 2006.257.12:01:07.58#ibcon#flushed, iclass 14, count 0 2006.257.12:01:07.58#ibcon#about to write, iclass 14, count 0 2006.257.12:01:07.58#ibcon#wrote, iclass 14, count 0 2006.257.12:01:07.58#ibcon#about to read 3, iclass 14, count 0 2006.257.12:01:07.60#ibcon#read 3, iclass 14, count 0 2006.257.12:01:07.60#ibcon#about to read 4, iclass 14, count 0 2006.257.12:01:07.60#ibcon#read 4, iclass 14, count 0 2006.257.12:01:07.60#ibcon#about to read 5, iclass 14, count 0 2006.257.12:01:07.60#ibcon#read 5, iclass 14, count 0 2006.257.12:01:07.60#ibcon#about to read 6, iclass 14, count 0 2006.257.12:01:07.60#ibcon#read 6, iclass 14, count 0 2006.257.12:01:07.60#ibcon#end of sib2, iclass 14, count 0 2006.257.12:01:07.60#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:01:07.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:01:07.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:01:07.60#ibcon#*before write, iclass 14, count 0 2006.257.12:01:07.60#ibcon#enter sib2, iclass 14, count 0 2006.257.12:01:07.60#ibcon#flushed, iclass 14, count 0 2006.257.12:01:07.60#ibcon#about to write, iclass 14, count 0 2006.257.12:01:07.60#ibcon#wrote, iclass 14, count 0 2006.257.12:01:07.60#ibcon#about to read 3, iclass 14, count 0 2006.257.12:01:07.64#ibcon#read 3, iclass 14, count 0 2006.257.12:01:07.64#ibcon#about to read 4, iclass 14, count 0 2006.257.12:01:07.64#ibcon#read 4, iclass 14, count 0 2006.257.12:01:07.64#ibcon#about to read 5, iclass 14, count 0 2006.257.12:01:07.64#ibcon#read 5, iclass 14, count 0 2006.257.12:01:07.64#ibcon#about to read 6, iclass 14, count 0 2006.257.12:01:07.64#ibcon#read 6, iclass 14, count 0 2006.257.12:01:07.64#ibcon#end of sib2, iclass 14, count 0 2006.257.12:01:07.64#ibcon#*after write, iclass 14, count 0 2006.257.12:01:07.64#ibcon#*before return 0, iclass 14, count 0 2006.257.12:01:07.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:07.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:07.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:01:07.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:01:07.64$vck44/va=8,4 2006.257.12:01:07.64#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.12:01:07.64#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.12:01:07.64#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:07.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:01:07.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:01:07.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:01:07.70#ibcon#enter wrdev, iclass 16, count 2 2006.257.12:01:07.70#ibcon#first serial, iclass 16, count 2 2006.257.12:01:07.70#ibcon#enter sib2, iclass 16, count 2 2006.257.12:01:07.70#ibcon#flushed, iclass 16, count 2 2006.257.12:01:07.70#ibcon#about to write, iclass 16, count 2 2006.257.12:01:07.70#ibcon#wrote, iclass 16, count 2 2006.257.12:01:07.70#ibcon#about to read 3, iclass 16, count 2 2006.257.12:01:07.72#ibcon#read 3, iclass 16, count 2 2006.257.12:01:07.72#ibcon#about to read 4, iclass 16, count 2 2006.257.12:01:07.72#ibcon#read 4, iclass 16, count 2 2006.257.12:01:07.72#ibcon#about to read 5, iclass 16, count 2 2006.257.12:01:07.72#ibcon#read 5, iclass 16, count 2 2006.257.12:01:07.72#ibcon#about to read 6, iclass 16, count 2 2006.257.12:01:07.72#ibcon#read 6, iclass 16, count 2 2006.257.12:01:07.72#ibcon#end of sib2, iclass 16, count 2 2006.257.12:01:07.72#ibcon#*mode == 0, iclass 16, count 2 2006.257.12:01:07.72#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.12:01:07.72#ibcon#[25=AT08-04\r\n] 2006.257.12:01:07.72#ibcon#*before write, iclass 16, count 2 2006.257.12:01:07.72#ibcon#enter sib2, iclass 16, count 2 2006.257.12:01:07.72#ibcon#flushed, iclass 16, count 2 2006.257.12:01:07.72#ibcon#about to write, iclass 16, count 2 2006.257.12:01:07.72#ibcon#wrote, iclass 16, count 2 2006.257.12:01:07.72#ibcon#about to read 3, iclass 16, count 2 2006.257.12:01:07.75#ibcon#read 3, iclass 16, count 2 2006.257.12:01:07.75#ibcon#about to read 4, iclass 16, count 2 2006.257.12:01:07.75#ibcon#read 4, iclass 16, count 2 2006.257.12:01:07.75#ibcon#about to read 5, iclass 16, count 2 2006.257.12:01:07.75#ibcon#read 5, iclass 16, count 2 2006.257.12:01:07.75#ibcon#about to read 6, iclass 16, count 2 2006.257.12:01:07.75#ibcon#read 6, iclass 16, count 2 2006.257.12:01:07.75#ibcon#end of sib2, iclass 16, count 2 2006.257.12:01:07.75#ibcon#*after write, iclass 16, count 2 2006.257.12:01:07.75#ibcon#*before return 0, iclass 16, count 2 2006.257.12:01:07.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:01:07.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:01:07.75#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.12:01:07.75#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:07.75#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:01:07.87#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:01:07.87#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:01:07.87#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:01:07.87#ibcon#first serial, iclass 16, count 0 2006.257.12:01:07.87#ibcon#enter sib2, iclass 16, count 0 2006.257.12:01:07.87#ibcon#flushed, iclass 16, count 0 2006.257.12:01:07.87#ibcon#about to write, iclass 16, count 0 2006.257.12:01:07.87#ibcon#wrote, iclass 16, count 0 2006.257.12:01:07.87#ibcon#about to read 3, iclass 16, count 0 2006.257.12:01:07.89#ibcon#read 3, iclass 16, count 0 2006.257.12:01:07.89#ibcon#about to read 4, iclass 16, count 0 2006.257.12:01:07.89#ibcon#read 4, iclass 16, count 0 2006.257.12:01:07.89#ibcon#about to read 5, iclass 16, count 0 2006.257.12:01:07.89#ibcon#read 5, iclass 16, count 0 2006.257.12:01:07.89#ibcon#about to read 6, iclass 16, count 0 2006.257.12:01:07.89#ibcon#read 6, iclass 16, count 0 2006.257.12:01:07.89#ibcon#end of sib2, iclass 16, count 0 2006.257.12:01:07.89#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:01:07.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:01:07.89#ibcon#[25=USB\r\n] 2006.257.12:01:07.89#ibcon#*before write, iclass 16, count 0 2006.257.12:01:07.89#ibcon#enter sib2, iclass 16, count 0 2006.257.12:01:07.89#ibcon#flushed, iclass 16, count 0 2006.257.12:01:07.89#ibcon#about to write, iclass 16, count 0 2006.257.12:01:07.89#ibcon#wrote, iclass 16, count 0 2006.257.12:01:07.89#ibcon#about to read 3, iclass 16, count 0 2006.257.12:01:07.92#ibcon#read 3, iclass 16, count 0 2006.257.12:01:07.92#ibcon#about to read 4, iclass 16, count 0 2006.257.12:01:07.92#ibcon#read 4, iclass 16, count 0 2006.257.12:01:07.92#ibcon#about to read 5, iclass 16, count 0 2006.257.12:01:07.92#ibcon#read 5, iclass 16, count 0 2006.257.12:01:07.92#ibcon#about to read 6, iclass 16, count 0 2006.257.12:01:07.92#ibcon#read 6, iclass 16, count 0 2006.257.12:01:07.92#ibcon#end of sib2, iclass 16, count 0 2006.257.12:01:07.92#ibcon#*after write, iclass 16, count 0 2006.257.12:01:07.92#ibcon#*before return 0, iclass 16, count 0 2006.257.12:01:07.92#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:01:07.92#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:01:07.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:01:07.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:01:07.92$vck44/vblo=1,629.99 2006.257.12:01:07.92#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.12:01:07.92#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.12:01:07.92#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:07.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:01:07.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:01:07.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:01:07.92#ibcon#enter wrdev, iclass 18, count 0 2006.257.12:01:07.92#ibcon#first serial, iclass 18, count 0 2006.257.12:01:07.92#ibcon#enter sib2, iclass 18, count 0 2006.257.12:01:07.92#ibcon#flushed, iclass 18, count 0 2006.257.12:01:07.92#ibcon#about to write, iclass 18, count 0 2006.257.12:01:07.92#ibcon#wrote, iclass 18, count 0 2006.257.12:01:07.92#ibcon#about to read 3, iclass 18, count 0 2006.257.12:01:07.94#ibcon#read 3, iclass 18, count 0 2006.257.12:01:07.94#ibcon#about to read 4, iclass 18, count 0 2006.257.12:01:07.94#ibcon#read 4, iclass 18, count 0 2006.257.12:01:07.94#ibcon#about to read 5, iclass 18, count 0 2006.257.12:01:07.94#ibcon#read 5, iclass 18, count 0 2006.257.12:01:07.94#ibcon#about to read 6, iclass 18, count 0 2006.257.12:01:07.94#ibcon#read 6, iclass 18, count 0 2006.257.12:01:07.94#ibcon#end of sib2, iclass 18, count 0 2006.257.12:01:07.94#ibcon#*mode == 0, iclass 18, count 0 2006.257.12:01:07.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.12:01:07.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:01:07.94#ibcon#*before write, iclass 18, count 0 2006.257.12:01:07.94#ibcon#enter sib2, iclass 18, count 0 2006.257.12:01:07.94#ibcon#flushed, iclass 18, count 0 2006.257.12:01:07.94#ibcon#about to write, iclass 18, count 0 2006.257.12:01:07.94#ibcon#wrote, iclass 18, count 0 2006.257.12:01:07.94#ibcon#about to read 3, iclass 18, count 0 2006.257.12:01:07.98#ibcon#read 3, iclass 18, count 0 2006.257.12:01:07.98#ibcon#about to read 4, iclass 18, count 0 2006.257.12:01:07.98#ibcon#read 4, iclass 18, count 0 2006.257.12:01:07.98#ibcon#about to read 5, iclass 18, count 0 2006.257.12:01:07.98#ibcon#read 5, iclass 18, count 0 2006.257.12:01:07.98#ibcon#about to read 6, iclass 18, count 0 2006.257.12:01:07.98#ibcon#read 6, iclass 18, count 0 2006.257.12:01:07.98#ibcon#end of sib2, iclass 18, count 0 2006.257.12:01:07.98#ibcon#*after write, iclass 18, count 0 2006.257.12:01:07.98#ibcon#*before return 0, iclass 18, count 0 2006.257.12:01:07.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:01:07.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:01:07.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.12:01:07.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.12:01:07.98$vck44/vb=1,4 2006.257.12:01:07.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.12:01:07.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.12:01:07.98#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:07.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:01:07.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:01:07.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:01:07.98#ibcon#enter wrdev, iclass 20, count 2 2006.257.12:01:07.98#ibcon#first serial, iclass 20, count 2 2006.257.12:01:07.98#ibcon#enter sib2, iclass 20, count 2 2006.257.12:01:07.98#ibcon#flushed, iclass 20, count 2 2006.257.12:01:07.98#ibcon#about to write, iclass 20, count 2 2006.257.12:01:07.98#ibcon#wrote, iclass 20, count 2 2006.257.12:01:07.98#ibcon#about to read 3, iclass 20, count 2 2006.257.12:01:08.00#ibcon#read 3, iclass 20, count 2 2006.257.12:01:08.00#ibcon#about to read 4, iclass 20, count 2 2006.257.12:01:08.00#ibcon#read 4, iclass 20, count 2 2006.257.12:01:08.00#ibcon#about to read 5, iclass 20, count 2 2006.257.12:01:08.00#ibcon#read 5, iclass 20, count 2 2006.257.12:01:08.00#ibcon#about to read 6, iclass 20, count 2 2006.257.12:01:08.00#ibcon#read 6, iclass 20, count 2 2006.257.12:01:08.00#ibcon#end of sib2, iclass 20, count 2 2006.257.12:01:08.00#ibcon#*mode == 0, iclass 20, count 2 2006.257.12:01:08.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.12:01:08.00#ibcon#[27=AT01-04\r\n] 2006.257.12:01:08.00#ibcon#*before write, iclass 20, count 2 2006.257.12:01:08.00#ibcon#enter sib2, iclass 20, count 2 2006.257.12:01:08.00#ibcon#flushed, iclass 20, count 2 2006.257.12:01:08.00#ibcon#about to write, iclass 20, count 2 2006.257.12:01:08.00#ibcon#wrote, iclass 20, count 2 2006.257.12:01:08.00#ibcon#about to read 3, iclass 20, count 2 2006.257.12:01:08.03#ibcon#read 3, iclass 20, count 2 2006.257.12:01:08.03#ibcon#about to read 4, iclass 20, count 2 2006.257.12:01:08.03#ibcon#read 4, iclass 20, count 2 2006.257.12:01:08.03#ibcon#about to read 5, iclass 20, count 2 2006.257.12:01:08.03#ibcon#read 5, iclass 20, count 2 2006.257.12:01:08.03#ibcon#about to read 6, iclass 20, count 2 2006.257.12:01:08.03#ibcon#read 6, iclass 20, count 2 2006.257.12:01:08.03#ibcon#end of sib2, iclass 20, count 2 2006.257.12:01:08.03#ibcon#*after write, iclass 20, count 2 2006.257.12:01:08.03#ibcon#*before return 0, iclass 20, count 2 2006.257.12:01:08.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:01:08.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:01:08.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.12:01:08.03#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:08.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:01:08.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:01:08.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:01:08.15#ibcon#enter wrdev, iclass 20, count 0 2006.257.12:01:08.15#ibcon#first serial, iclass 20, count 0 2006.257.12:01:08.15#ibcon#enter sib2, iclass 20, count 0 2006.257.12:01:08.15#ibcon#flushed, iclass 20, count 0 2006.257.12:01:08.15#ibcon#about to write, iclass 20, count 0 2006.257.12:01:08.15#ibcon#wrote, iclass 20, count 0 2006.257.12:01:08.15#ibcon#about to read 3, iclass 20, count 0 2006.257.12:01:08.17#ibcon#read 3, iclass 20, count 0 2006.257.12:01:08.17#ibcon#about to read 4, iclass 20, count 0 2006.257.12:01:08.17#ibcon#read 4, iclass 20, count 0 2006.257.12:01:08.17#ibcon#about to read 5, iclass 20, count 0 2006.257.12:01:08.17#ibcon#read 5, iclass 20, count 0 2006.257.12:01:08.17#ibcon#about to read 6, iclass 20, count 0 2006.257.12:01:08.17#ibcon#read 6, iclass 20, count 0 2006.257.12:01:08.17#ibcon#end of sib2, iclass 20, count 0 2006.257.12:01:08.17#ibcon#*mode == 0, iclass 20, count 0 2006.257.12:01:08.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.12:01:08.17#ibcon#[27=USB\r\n] 2006.257.12:01:08.17#ibcon#*before write, iclass 20, count 0 2006.257.12:01:08.17#ibcon#enter sib2, iclass 20, count 0 2006.257.12:01:08.17#ibcon#flushed, iclass 20, count 0 2006.257.12:01:08.17#ibcon#about to write, iclass 20, count 0 2006.257.12:01:08.17#ibcon#wrote, iclass 20, count 0 2006.257.12:01:08.17#ibcon#about to read 3, iclass 20, count 0 2006.257.12:01:08.20#ibcon#read 3, iclass 20, count 0 2006.257.12:01:08.20#ibcon#about to read 4, iclass 20, count 0 2006.257.12:01:08.20#ibcon#read 4, iclass 20, count 0 2006.257.12:01:08.20#ibcon#about to read 5, iclass 20, count 0 2006.257.12:01:08.20#ibcon#read 5, iclass 20, count 0 2006.257.12:01:08.20#ibcon#about to read 6, iclass 20, count 0 2006.257.12:01:08.20#ibcon#read 6, iclass 20, count 0 2006.257.12:01:08.20#ibcon#end of sib2, iclass 20, count 0 2006.257.12:01:08.20#ibcon#*after write, iclass 20, count 0 2006.257.12:01:08.20#ibcon#*before return 0, iclass 20, count 0 2006.257.12:01:08.20#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:01:08.20#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:01:08.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.12:01:08.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.12:01:08.20$vck44/vblo=2,634.99 2006.257.12:01:08.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.12:01:08.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.12:01:08.20#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:08.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:08.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:08.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:08.20#ibcon#enter wrdev, iclass 22, count 0 2006.257.12:01:08.20#ibcon#first serial, iclass 22, count 0 2006.257.12:01:08.20#ibcon#enter sib2, iclass 22, count 0 2006.257.12:01:08.20#ibcon#flushed, iclass 22, count 0 2006.257.12:01:08.20#ibcon#about to write, iclass 22, count 0 2006.257.12:01:08.20#ibcon#wrote, iclass 22, count 0 2006.257.12:01:08.20#ibcon#about to read 3, iclass 22, count 0 2006.257.12:01:08.22#ibcon#read 3, iclass 22, count 0 2006.257.12:01:08.22#ibcon#about to read 4, iclass 22, count 0 2006.257.12:01:08.22#ibcon#read 4, iclass 22, count 0 2006.257.12:01:08.22#ibcon#about to read 5, iclass 22, count 0 2006.257.12:01:08.22#ibcon#read 5, iclass 22, count 0 2006.257.12:01:08.22#ibcon#about to read 6, iclass 22, count 0 2006.257.12:01:08.22#ibcon#read 6, iclass 22, count 0 2006.257.12:01:08.22#ibcon#end of sib2, iclass 22, count 0 2006.257.12:01:08.22#ibcon#*mode == 0, iclass 22, count 0 2006.257.12:01:08.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.12:01:08.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:01:08.22#ibcon#*before write, iclass 22, count 0 2006.257.12:01:08.22#ibcon#enter sib2, iclass 22, count 0 2006.257.12:01:08.22#ibcon#flushed, iclass 22, count 0 2006.257.12:01:08.22#ibcon#about to write, iclass 22, count 0 2006.257.12:01:08.22#ibcon#wrote, iclass 22, count 0 2006.257.12:01:08.22#ibcon#about to read 3, iclass 22, count 0 2006.257.12:01:08.26#ibcon#read 3, iclass 22, count 0 2006.257.12:01:08.26#ibcon#about to read 4, iclass 22, count 0 2006.257.12:01:08.26#ibcon#read 4, iclass 22, count 0 2006.257.12:01:08.26#ibcon#about to read 5, iclass 22, count 0 2006.257.12:01:08.26#ibcon#read 5, iclass 22, count 0 2006.257.12:01:08.26#ibcon#about to read 6, iclass 22, count 0 2006.257.12:01:08.26#ibcon#read 6, iclass 22, count 0 2006.257.12:01:08.26#ibcon#end of sib2, iclass 22, count 0 2006.257.12:01:08.26#ibcon#*after write, iclass 22, count 0 2006.257.12:01:08.26#ibcon#*before return 0, iclass 22, count 0 2006.257.12:01:08.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:08.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:01:08.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.12:01:08.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.12:01:08.26$vck44/vb=2,5 2006.257.12:01:08.26#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.12:01:08.26#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.12:01:08.26#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:08.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:08.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:08.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:08.32#ibcon#enter wrdev, iclass 24, count 2 2006.257.12:01:08.32#ibcon#first serial, iclass 24, count 2 2006.257.12:01:08.32#ibcon#enter sib2, iclass 24, count 2 2006.257.12:01:08.32#ibcon#flushed, iclass 24, count 2 2006.257.12:01:08.32#ibcon#about to write, iclass 24, count 2 2006.257.12:01:08.32#ibcon#wrote, iclass 24, count 2 2006.257.12:01:08.32#ibcon#about to read 3, iclass 24, count 2 2006.257.12:01:08.34#ibcon#read 3, iclass 24, count 2 2006.257.12:01:08.34#ibcon#about to read 4, iclass 24, count 2 2006.257.12:01:08.34#ibcon#read 4, iclass 24, count 2 2006.257.12:01:08.34#ibcon#about to read 5, iclass 24, count 2 2006.257.12:01:08.34#ibcon#read 5, iclass 24, count 2 2006.257.12:01:08.34#ibcon#about to read 6, iclass 24, count 2 2006.257.12:01:08.34#ibcon#read 6, iclass 24, count 2 2006.257.12:01:08.34#ibcon#end of sib2, iclass 24, count 2 2006.257.12:01:08.34#ibcon#*mode == 0, iclass 24, count 2 2006.257.12:01:08.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.12:01:08.34#ibcon#[27=AT02-05\r\n] 2006.257.12:01:08.34#ibcon#*before write, iclass 24, count 2 2006.257.12:01:08.34#ibcon#enter sib2, iclass 24, count 2 2006.257.12:01:08.34#ibcon#flushed, iclass 24, count 2 2006.257.12:01:08.34#ibcon#about to write, iclass 24, count 2 2006.257.12:01:08.34#ibcon#wrote, iclass 24, count 2 2006.257.12:01:08.34#ibcon#about to read 3, iclass 24, count 2 2006.257.12:01:08.37#ibcon#read 3, iclass 24, count 2 2006.257.12:01:08.37#ibcon#about to read 4, iclass 24, count 2 2006.257.12:01:08.37#ibcon#read 4, iclass 24, count 2 2006.257.12:01:08.37#ibcon#about to read 5, iclass 24, count 2 2006.257.12:01:08.37#ibcon#read 5, iclass 24, count 2 2006.257.12:01:08.37#ibcon#about to read 6, iclass 24, count 2 2006.257.12:01:08.37#ibcon#read 6, iclass 24, count 2 2006.257.12:01:08.37#ibcon#end of sib2, iclass 24, count 2 2006.257.12:01:08.37#ibcon#*after write, iclass 24, count 2 2006.257.12:01:08.37#ibcon#*before return 0, iclass 24, count 2 2006.257.12:01:08.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:08.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:01:08.37#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.12:01:08.37#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:08.37#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:08.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:08.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:08.49#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:01:08.49#ibcon#first serial, iclass 24, count 0 2006.257.12:01:08.49#ibcon#enter sib2, iclass 24, count 0 2006.257.12:01:08.49#ibcon#flushed, iclass 24, count 0 2006.257.12:01:08.49#ibcon#about to write, iclass 24, count 0 2006.257.12:01:10.06#ibcon#wrote, iclass 24, count 0 2006.257.12:01:10.06#ibcon#about to read 3, iclass 24, count 0 2006.257.12:01:10.08#ibcon#read 3, iclass 24, count 0 2006.257.12:01:10.08#ibcon#about to read 4, iclass 24, count 0 2006.257.12:01:10.08#ibcon#read 4, iclass 24, count 0 2006.257.12:01:10.08#ibcon#about to read 5, iclass 24, count 0 2006.257.12:01:10.08#ibcon#read 5, iclass 24, count 0 2006.257.12:01:10.08#ibcon#about to read 6, iclass 24, count 0 2006.257.12:01:10.08#ibcon#read 6, iclass 24, count 0 2006.257.12:01:10.08#ibcon#end of sib2, iclass 24, count 0 2006.257.12:01:10.08#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:01:10.08#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:01:10.08#ibcon#[27=USB\r\n] 2006.257.12:01:10.08#ibcon#*before write, iclass 24, count 0 2006.257.12:01:10.08#ibcon#enter sib2, iclass 24, count 0 2006.257.12:01:10.08#ibcon#flushed, iclass 24, count 0 2006.257.12:01:10.08#ibcon#about to write, iclass 24, count 0 2006.257.12:01:10.08#ibcon#wrote, iclass 24, count 0 2006.257.12:01:10.08#ibcon#about to read 3, iclass 24, count 0 2006.257.12:01:10.11#ibcon#read 3, iclass 24, count 0 2006.257.12:01:10.11#ibcon#about to read 4, iclass 24, count 0 2006.257.12:01:10.11#ibcon#read 4, iclass 24, count 0 2006.257.12:01:10.11#ibcon#about to read 5, iclass 24, count 0 2006.257.12:01:10.11#ibcon#read 5, iclass 24, count 0 2006.257.12:01:10.11#ibcon#about to read 6, iclass 24, count 0 2006.257.12:01:10.11#ibcon#read 6, iclass 24, count 0 2006.257.12:01:10.11#ibcon#end of sib2, iclass 24, count 0 2006.257.12:01:10.11#ibcon#*after write, iclass 24, count 0 2006.257.12:01:10.11#ibcon#*before return 0, iclass 24, count 0 2006.257.12:01:10.11#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:10.11#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:01:10.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:01:10.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:01:10.11$vck44/vblo=3,649.99 2006.257.12:01:10.11#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.12:01:10.11#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.12:01:10.11#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:10.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:10.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:10.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:10.11#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:01:10.11#ibcon#first serial, iclass 26, count 0 2006.257.12:01:10.11#ibcon#enter sib2, iclass 26, count 0 2006.257.12:01:10.11#ibcon#flushed, iclass 26, count 0 2006.257.12:01:10.11#ibcon#about to write, iclass 26, count 0 2006.257.12:01:10.11#ibcon#wrote, iclass 26, count 0 2006.257.12:01:10.11#ibcon#about to read 3, iclass 26, count 0 2006.257.12:01:10.13#ibcon#read 3, iclass 26, count 0 2006.257.12:01:10.13#ibcon#about to read 4, iclass 26, count 0 2006.257.12:01:10.13#ibcon#read 4, iclass 26, count 0 2006.257.12:01:10.13#ibcon#about to read 5, iclass 26, count 0 2006.257.12:01:10.13#ibcon#read 5, iclass 26, count 0 2006.257.12:01:10.13#ibcon#about to read 6, iclass 26, count 0 2006.257.12:01:10.13#ibcon#read 6, iclass 26, count 0 2006.257.12:01:10.13#ibcon#end of sib2, iclass 26, count 0 2006.257.12:01:10.13#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:01:10.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:01:10.13#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:01:10.13#ibcon#*before write, iclass 26, count 0 2006.257.12:01:10.13#ibcon#enter sib2, iclass 26, count 0 2006.257.12:01:10.13#ibcon#flushed, iclass 26, count 0 2006.257.12:01:10.13#ibcon#about to write, iclass 26, count 0 2006.257.12:01:10.13#ibcon#wrote, iclass 26, count 0 2006.257.12:01:10.13#ibcon#about to read 3, iclass 26, count 0 2006.257.12:01:10.17#ibcon#read 3, iclass 26, count 0 2006.257.12:01:10.17#ibcon#about to read 4, iclass 26, count 0 2006.257.12:01:10.17#ibcon#read 4, iclass 26, count 0 2006.257.12:01:10.17#ibcon#about to read 5, iclass 26, count 0 2006.257.12:01:10.17#ibcon#read 5, iclass 26, count 0 2006.257.12:01:10.17#ibcon#about to read 6, iclass 26, count 0 2006.257.12:01:10.17#ibcon#read 6, iclass 26, count 0 2006.257.12:01:10.17#ibcon#end of sib2, iclass 26, count 0 2006.257.12:01:10.17#ibcon#*after write, iclass 26, count 0 2006.257.12:01:10.17#ibcon#*before return 0, iclass 26, count 0 2006.257.12:01:10.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:10.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:01:10.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:01:10.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:01:10.17$vck44/vb=3,4 2006.257.12:01:10.17#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.12:01:10.17#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.12:01:10.17#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:10.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:10.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:10.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:10.23#ibcon#enter wrdev, iclass 28, count 2 2006.257.12:01:10.23#ibcon#first serial, iclass 28, count 2 2006.257.12:01:10.23#ibcon#enter sib2, iclass 28, count 2 2006.257.12:01:10.23#ibcon#flushed, iclass 28, count 2 2006.257.12:01:10.23#ibcon#about to write, iclass 28, count 2 2006.257.12:01:10.23#ibcon#wrote, iclass 28, count 2 2006.257.12:01:10.23#ibcon#about to read 3, iclass 28, count 2 2006.257.12:01:10.25#ibcon#read 3, iclass 28, count 2 2006.257.12:01:10.25#ibcon#about to read 4, iclass 28, count 2 2006.257.12:01:10.25#ibcon#read 4, iclass 28, count 2 2006.257.12:01:10.25#ibcon#about to read 5, iclass 28, count 2 2006.257.12:01:10.25#ibcon#read 5, iclass 28, count 2 2006.257.12:01:10.25#ibcon#about to read 6, iclass 28, count 2 2006.257.12:01:10.25#ibcon#read 6, iclass 28, count 2 2006.257.12:01:10.25#ibcon#end of sib2, iclass 28, count 2 2006.257.12:01:10.25#ibcon#*mode == 0, iclass 28, count 2 2006.257.12:01:10.25#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.12:01:10.25#ibcon#[27=AT03-04\r\n] 2006.257.12:01:10.25#ibcon#*before write, iclass 28, count 2 2006.257.12:01:10.25#ibcon#enter sib2, iclass 28, count 2 2006.257.12:01:10.25#ibcon#flushed, iclass 28, count 2 2006.257.12:01:10.25#ibcon#about to write, iclass 28, count 2 2006.257.12:01:10.25#ibcon#wrote, iclass 28, count 2 2006.257.12:01:10.25#ibcon#about to read 3, iclass 28, count 2 2006.257.12:01:10.28#ibcon#read 3, iclass 28, count 2 2006.257.12:01:10.28#ibcon#about to read 4, iclass 28, count 2 2006.257.12:01:10.28#ibcon#read 4, iclass 28, count 2 2006.257.12:01:10.28#ibcon#about to read 5, iclass 28, count 2 2006.257.12:01:10.28#ibcon#read 5, iclass 28, count 2 2006.257.12:01:10.28#ibcon#about to read 6, iclass 28, count 2 2006.257.12:01:10.28#ibcon#read 6, iclass 28, count 2 2006.257.12:01:10.28#ibcon#end of sib2, iclass 28, count 2 2006.257.12:01:10.28#ibcon#*after write, iclass 28, count 2 2006.257.12:01:10.28#ibcon#*before return 0, iclass 28, count 2 2006.257.12:01:10.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:10.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:01:10.28#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.12:01:10.28#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:10.28#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:10.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:10.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:10.40#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:01:10.40#ibcon#first serial, iclass 28, count 0 2006.257.12:01:10.40#ibcon#enter sib2, iclass 28, count 0 2006.257.12:01:10.40#ibcon#flushed, iclass 28, count 0 2006.257.12:01:10.40#ibcon#about to write, iclass 28, count 0 2006.257.12:01:10.40#ibcon#wrote, iclass 28, count 0 2006.257.12:01:10.40#ibcon#about to read 3, iclass 28, count 0 2006.257.12:01:10.42#ibcon#read 3, iclass 28, count 0 2006.257.12:01:10.42#ibcon#about to read 4, iclass 28, count 0 2006.257.12:01:10.42#ibcon#read 4, iclass 28, count 0 2006.257.12:01:10.42#ibcon#about to read 5, iclass 28, count 0 2006.257.12:01:10.42#ibcon#read 5, iclass 28, count 0 2006.257.12:01:10.42#ibcon#about to read 6, iclass 28, count 0 2006.257.12:01:10.42#ibcon#read 6, iclass 28, count 0 2006.257.12:01:10.42#ibcon#end of sib2, iclass 28, count 0 2006.257.12:01:10.42#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:01:10.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:01:10.42#ibcon#[27=USB\r\n] 2006.257.12:01:10.42#ibcon#*before write, iclass 28, count 0 2006.257.12:01:10.42#ibcon#enter sib2, iclass 28, count 0 2006.257.12:01:10.42#ibcon#flushed, iclass 28, count 0 2006.257.12:01:10.42#ibcon#about to write, iclass 28, count 0 2006.257.12:01:10.42#ibcon#wrote, iclass 28, count 0 2006.257.12:01:10.42#ibcon#about to read 3, iclass 28, count 0 2006.257.12:01:10.45#ibcon#read 3, iclass 28, count 0 2006.257.12:01:10.45#ibcon#about to read 4, iclass 28, count 0 2006.257.12:01:10.45#ibcon#read 4, iclass 28, count 0 2006.257.12:01:10.45#ibcon#about to read 5, iclass 28, count 0 2006.257.12:01:10.45#ibcon#read 5, iclass 28, count 0 2006.257.12:01:10.45#ibcon#about to read 6, iclass 28, count 0 2006.257.12:01:10.45#ibcon#read 6, iclass 28, count 0 2006.257.12:01:10.45#ibcon#end of sib2, iclass 28, count 0 2006.257.12:01:10.45#ibcon#*after write, iclass 28, count 0 2006.257.12:01:10.45#ibcon#*before return 0, iclass 28, count 0 2006.257.12:01:10.45#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:10.45#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:01:10.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:01:10.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:01:10.45$vck44/vblo=4,679.99 2006.257.12:01:10.45#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.12:01:10.45#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.12:01:10.45#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:10.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:10.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:10.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:10.45#ibcon#enter wrdev, iclass 30, count 0 2006.257.12:01:10.45#ibcon#first serial, iclass 30, count 0 2006.257.12:01:10.45#ibcon#enter sib2, iclass 30, count 0 2006.257.12:01:10.45#ibcon#flushed, iclass 30, count 0 2006.257.12:01:10.45#ibcon#about to write, iclass 30, count 0 2006.257.12:01:10.45#ibcon#wrote, iclass 30, count 0 2006.257.12:01:10.45#ibcon#about to read 3, iclass 30, count 0 2006.257.12:01:10.47#ibcon#read 3, iclass 30, count 0 2006.257.12:01:10.47#ibcon#about to read 4, iclass 30, count 0 2006.257.12:01:10.47#ibcon#read 4, iclass 30, count 0 2006.257.12:01:10.47#ibcon#about to read 5, iclass 30, count 0 2006.257.12:01:10.47#ibcon#read 5, iclass 30, count 0 2006.257.12:01:10.47#ibcon#about to read 6, iclass 30, count 0 2006.257.12:01:10.47#ibcon#read 6, iclass 30, count 0 2006.257.12:01:10.47#ibcon#end of sib2, iclass 30, count 0 2006.257.12:01:10.47#ibcon#*mode == 0, iclass 30, count 0 2006.257.12:01:10.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.12:01:10.47#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:01:10.47#ibcon#*before write, iclass 30, count 0 2006.257.12:01:10.47#ibcon#enter sib2, iclass 30, count 0 2006.257.12:01:10.47#ibcon#flushed, iclass 30, count 0 2006.257.12:01:10.47#ibcon#about to write, iclass 30, count 0 2006.257.12:01:10.47#ibcon#wrote, iclass 30, count 0 2006.257.12:01:10.47#ibcon#about to read 3, iclass 30, count 0 2006.257.12:01:10.51#ibcon#read 3, iclass 30, count 0 2006.257.12:01:10.51#ibcon#about to read 4, iclass 30, count 0 2006.257.12:01:10.51#ibcon#read 4, iclass 30, count 0 2006.257.12:01:10.51#ibcon#about to read 5, iclass 30, count 0 2006.257.12:01:10.51#ibcon#read 5, iclass 30, count 0 2006.257.12:01:10.51#ibcon#about to read 6, iclass 30, count 0 2006.257.12:01:10.51#ibcon#read 6, iclass 30, count 0 2006.257.12:01:10.51#ibcon#end of sib2, iclass 30, count 0 2006.257.12:01:10.51#ibcon#*after write, iclass 30, count 0 2006.257.12:01:10.51#ibcon#*before return 0, iclass 30, count 0 2006.257.12:01:10.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:10.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:01:10.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.12:01:10.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.12:01:10.51$vck44/vb=4,5 2006.257.12:01:10.51#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.12:01:10.51#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.12:01:10.51#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:10.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:10.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:10.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:10.57#ibcon#enter wrdev, iclass 32, count 2 2006.257.12:01:10.57#ibcon#first serial, iclass 32, count 2 2006.257.12:01:10.57#ibcon#enter sib2, iclass 32, count 2 2006.257.12:01:10.57#ibcon#flushed, iclass 32, count 2 2006.257.12:01:10.57#ibcon#about to write, iclass 32, count 2 2006.257.12:01:10.57#ibcon#wrote, iclass 32, count 2 2006.257.12:01:10.57#ibcon#about to read 3, iclass 32, count 2 2006.257.12:01:10.59#ibcon#read 3, iclass 32, count 2 2006.257.12:01:10.59#ibcon#about to read 4, iclass 32, count 2 2006.257.12:01:10.59#ibcon#read 4, iclass 32, count 2 2006.257.12:01:10.59#ibcon#about to read 5, iclass 32, count 2 2006.257.12:01:10.59#ibcon#read 5, iclass 32, count 2 2006.257.12:01:10.59#ibcon#about to read 6, iclass 32, count 2 2006.257.12:01:10.59#ibcon#read 6, iclass 32, count 2 2006.257.12:01:10.59#ibcon#end of sib2, iclass 32, count 2 2006.257.12:01:10.59#ibcon#*mode == 0, iclass 32, count 2 2006.257.12:01:10.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.12:01:10.59#ibcon#[27=AT04-05\r\n] 2006.257.12:01:10.59#ibcon#*before write, iclass 32, count 2 2006.257.12:01:10.59#ibcon#enter sib2, iclass 32, count 2 2006.257.12:01:10.59#ibcon#flushed, iclass 32, count 2 2006.257.12:01:10.59#ibcon#about to write, iclass 32, count 2 2006.257.12:01:10.59#ibcon#wrote, iclass 32, count 2 2006.257.12:01:10.59#ibcon#about to read 3, iclass 32, count 2 2006.257.12:01:10.62#ibcon#read 3, iclass 32, count 2 2006.257.12:01:10.62#ibcon#about to read 4, iclass 32, count 2 2006.257.12:01:10.62#ibcon#read 4, iclass 32, count 2 2006.257.12:01:10.62#ibcon#about to read 5, iclass 32, count 2 2006.257.12:01:10.62#ibcon#read 5, iclass 32, count 2 2006.257.12:01:10.62#ibcon#about to read 6, iclass 32, count 2 2006.257.12:01:10.62#ibcon#read 6, iclass 32, count 2 2006.257.12:01:10.62#ibcon#end of sib2, iclass 32, count 2 2006.257.12:01:10.62#ibcon#*after write, iclass 32, count 2 2006.257.12:01:10.62#ibcon#*before return 0, iclass 32, count 2 2006.257.12:01:10.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:10.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:01:10.62#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.12:01:10.62#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:10.62#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:10.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:10.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:10.74#ibcon#enter wrdev, iclass 32, count 0 2006.257.12:01:10.74#ibcon#first serial, iclass 32, count 0 2006.257.12:01:10.74#ibcon#enter sib2, iclass 32, count 0 2006.257.12:01:10.74#ibcon#flushed, iclass 32, count 0 2006.257.12:01:10.74#ibcon#about to write, iclass 32, count 0 2006.257.12:01:10.74#ibcon#wrote, iclass 32, count 0 2006.257.12:01:10.74#ibcon#about to read 3, iclass 32, count 0 2006.257.12:01:10.76#ibcon#read 3, iclass 32, count 0 2006.257.12:01:10.76#ibcon#about to read 4, iclass 32, count 0 2006.257.12:01:10.76#ibcon#read 4, iclass 32, count 0 2006.257.12:01:10.76#ibcon#about to read 5, iclass 32, count 0 2006.257.12:01:10.76#ibcon#read 5, iclass 32, count 0 2006.257.12:01:10.76#ibcon#about to read 6, iclass 32, count 0 2006.257.12:01:10.76#ibcon#read 6, iclass 32, count 0 2006.257.12:01:10.76#ibcon#end of sib2, iclass 32, count 0 2006.257.12:01:10.76#ibcon#*mode == 0, iclass 32, count 0 2006.257.12:01:10.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.12:01:10.76#ibcon#[27=USB\r\n] 2006.257.12:01:10.76#ibcon#*before write, iclass 32, count 0 2006.257.12:01:10.76#ibcon#enter sib2, iclass 32, count 0 2006.257.12:01:10.76#ibcon#flushed, iclass 32, count 0 2006.257.12:01:10.76#ibcon#about to write, iclass 32, count 0 2006.257.12:01:10.76#ibcon#wrote, iclass 32, count 0 2006.257.12:01:10.76#ibcon#about to read 3, iclass 32, count 0 2006.257.12:01:10.79#ibcon#read 3, iclass 32, count 0 2006.257.12:01:10.79#ibcon#about to read 4, iclass 32, count 0 2006.257.12:01:10.79#ibcon#read 4, iclass 32, count 0 2006.257.12:01:10.79#ibcon#about to read 5, iclass 32, count 0 2006.257.12:01:10.79#ibcon#read 5, iclass 32, count 0 2006.257.12:01:10.79#ibcon#about to read 6, iclass 32, count 0 2006.257.12:01:10.79#ibcon#read 6, iclass 32, count 0 2006.257.12:01:10.79#ibcon#end of sib2, iclass 32, count 0 2006.257.12:01:10.79#ibcon#*after write, iclass 32, count 0 2006.257.12:01:10.79#ibcon#*before return 0, iclass 32, count 0 2006.257.12:01:10.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:10.79#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:01:10.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.12:01:10.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.12:01:10.79$vck44/vblo=5,709.99 2006.257.12:01:10.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.12:01:10.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.12:01:10.79#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:10.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:10.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:10.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:10.79#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:01:10.79#ibcon#first serial, iclass 34, count 0 2006.257.12:01:10.79#ibcon#enter sib2, iclass 34, count 0 2006.257.12:01:10.79#ibcon#flushed, iclass 34, count 0 2006.257.12:01:10.79#ibcon#about to write, iclass 34, count 0 2006.257.12:01:10.79#ibcon#wrote, iclass 34, count 0 2006.257.12:01:10.79#ibcon#about to read 3, iclass 34, count 0 2006.257.12:01:10.81#ibcon#read 3, iclass 34, count 0 2006.257.12:01:10.81#ibcon#about to read 4, iclass 34, count 0 2006.257.12:01:10.81#ibcon#read 4, iclass 34, count 0 2006.257.12:01:10.81#ibcon#about to read 5, iclass 34, count 0 2006.257.12:01:10.81#ibcon#read 5, iclass 34, count 0 2006.257.12:01:10.81#ibcon#about to read 6, iclass 34, count 0 2006.257.12:01:10.81#ibcon#read 6, iclass 34, count 0 2006.257.12:01:10.81#ibcon#end of sib2, iclass 34, count 0 2006.257.12:01:10.81#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:01:10.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:01:10.81#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:01:10.81#ibcon#*before write, iclass 34, count 0 2006.257.12:01:10.81#ibcon#enter sib2, iclass 34, count 0 2006.257.12:01:10.81#ibcon#flushed, iclass 34, count 0 2006.257.12:01:10.81#ibcon#about to write, iclass 34, count 0 2006.257.12:01:10.81#ibcon#wrote, iclass 34, count 0 2006.257.12:01:10.81#ibcon#about to read 3, iclass 34, count 0 2006.257.12:01:10.85#ibcon#read 3, iclass 34, count 0 2006.257.12:01:10.85#ibcon#about to read 4, iclass 34, count 0 2006.257.12:01:10.85#ibcon#read 4, iclass 34, count 0 2006.257.12:01:10.85#ibcon#about to read 5, iclass 34, count 0 2006.257.12:01:10.85#ibcon#read 5, iclass 34, count 0 2006.257.12:01:10.85#ibcon#about to read 6, iclass 34, count 0 2006.257.12:01:10.85#ibcon#read 6, iclass 34, count 0 2006.257.12:01:10.85#ibcon#end of sib2, iclass 34, count 0 2006.257.12:01:10.85#ibcon#*after write, iclass 34, count 0 2006.257.12:01:10.85#ibcon#*before return 0, iclass 34, count 0 2006.257.12:01:10.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:10.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:01:10.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:01:10.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:01:10.85$vck44/vb=5,4 2006.257.12:01:10.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.12:01:10.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.12:01:10.85#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:10.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:10.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:10.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:10.91#ibcon#enter wrdev, iclass 36, count 2 2006.257.12:01:10.91#ibcon#first serial, iclass 36, count 2 2006.257.12:01:10.91#ibcon#enter sib2, iclass 36, count 2 2006.257.12:01:10.91#ibcon#flushed, iclass 36, count 2 2006.257.12:01:10.91#ibcon#about to write, iclass 36, count 2 2006.257.12:01:10.91#ibcon#wrote, iclass 36, count 2 2006.257.12:01:10.91#ibcon#about to read 3, iclass 36, count 2 2006.257.12:01:10.93#ibcon#read 3, iclass 36, count 2 2006.257.12:01:10.93#ibcon#about to read 4, iclass 36, count 2 2006.257.12:01:10.93#ibcon#read 4, iclass 36, count 2 2006.257.12:01:10.93#ibcon#about to read 5, iclass 36, count 2 2006.257.12:01:10.93#ibcon#read 5, iclass 36, count 2 2006.257.12:01:10.93#ibcon#about to read 6, iclass 36, count 2 2006.257.12:01:10.93#ibcon#read 6, iclass 36, count 2 2006.257.12:01:10.93#ibcon#end of sib2, iclass 36, count 2 2006.257.12:01:10.93#ibcon#*mode == 0, iclass 36, count 2 2006.257.12:01:10.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.12:01:10.93#ibcon#[27=AT05-04\r\n] 2006.257.12:01:10.93#ibcon#*before write, iclass 36, count 2 2006.257.12:01:10.93#ibcon#enter sib2, iclass 36, count 2 2006.257.12:01:10.93#ibcon#flushed, iclass 36, count 2 2006.257.12:01:10.93#ibcon#about to write, iclass 36, count 2 2006.257.12:01:10.93#ibcon#wrote, iclass 36, count 2 2006.257.12:01:10.93#ibcon#about to read 3, iclass 36, count 2 2006.257.12:01:10.96#ibcon#read 3, iclass 36, count 2 2006.257.12:01:10.96#ibcon#about to read 4, iclass 36, count 2 2006.257.12:01:10.96#ibcon#read 4, iclass 36, count 2 2006.257.12:01:10.96#ibcon#about to read 5, iclass 36, count 2 2006.257.12:01:10.96#ibcon#read 5, iclass 36, count 2 2006.257.12:01:10.96#ibcon#about to read 6, iclass 36, count 2 2006.257.12:01:10.96#ibcon#read 6, iclass 36, count 2 2006.257.12:01:10.96#ibcon#end of sib2, iclass 36, count 2 2006.257.12:01:10.96#ibcon#*after write, iclass 36, count 2 2006.257.12:01:10.96#ibcon#*before return 0, iclass 36, count 2 2006.257.12:01:10.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:10.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:01:10.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.12:01:10.96#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:10.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:11.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:11.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:11.08#ibcon#enter wrdev, iclass 36, count 0 2006.257.12:01:11.08#ibcon#first serial, iclass 36, count 0 2006.257.12:01:11.08#ibcon#enter sib2, iclass 36, count 0 2006.257.12:01:11.08#ibcon#flushed, iclass 36, count 0 2006.257.12:01:11.08#ibcon#about to write, iclass 36, count 0 2006.257.12:01:11.08#ibcon#wrote, iclass 36, count 0 2006.257.12:01:11.08#ibcon#about to read 3, iclass 36, count 0 2006.257.12:01:11.10#ibcon#read 3, iclass 36, count 0 2006.257.12:01:11.10#ibcon#about to read 4, iclass 36, count 0 2006.257.12:01:11.10#ibcon#read 4, iclass 36, count 0 2006.257.12:01:11.10#ibcon#about to read 5, iclass 36, count 0 2006.257.12:01:11.10#ibcon#read 5, iclass 36, count 0 2006.257.12:01:11.10#ibcon#about to read 6, iclass 36, count 0 2006.257.12:01:11.10#ibcon#read 6, iclass 36, count 0 2006.257.12:01:11.10#ibcon#end of sib2, iclass 36, count 0 2006.257.12:01:11.10#ibcon#*mode == 0, iclass 36, count 0 2006.257.12:01:11.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.12:01:11.10#ibcon#[27=USB\r\n] 2006.257.12:01:11.10#ibcon#*before write, iclass 36, count 0 2006.257.12:01:11.10#ibcon#enter sib2, iclass 36, count 0 2006.257.12:01:11.10#ibcon#flushed, iclass 36, count 0 2006.257.12:01:11.10#ibcon#about to write, iclass 36, count 0 2006.257.12:01:11.10#ibcon#wrote, iclass 36, count 0 2006.257.12:01:11.10#ibcon#about to read 3, iclass 36, count 0 2006.257.12:01:11.13#ibcon#read 3, iclass 36, count 0 2006.257.12:01:11.13#ibcon#about to read 4, iclass 36, count 0 2006.257.12:01:11.13#ibcon#read 4, iclass 36, count 0 2006.257.12:01:11.13#ibcon#about to read 5, iclass 36, count 0 2006.257.12:01:11.13#ibcon#read 5, iclass 36, count 0 2006.257.12:01:11.13#ibcon#about to read 6, iclass 36, count 0 2006.257.12:01:11.13#ibcon#read 6, iclass 36, count 0 2006.257.12:01:11.13#ibcon#end of sib2, iclass 36, count 0 2006.257.12:01:11.13#ibcon#*after write, iclass 36, count 0 2006.257.12:01:11.13#ibcon#*before return 0, iclass 36, count 0 2006.257.12:01:11.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:11.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:01:11.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.12:01:11.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.12:01:11.13$vck44/vblo=6,719.99 2006.257.12:01:11.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.12:01:11.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.12:01:11.13#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:11.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:11.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:11.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:11.13#ibcon#enter wrdev, iclass 38, count 0 2006.257.12:01:11.13#ibcon#first serial, iclass 38, count 0 2006.257.12:01:11.13#ibcon#enter sib2, iclass 38, count 0 2006.257.12:01:11.13#ibcon#flushed, iclass 38, count 0 2006.257.12:01:11.13#ibcon#about to write, iclass 38, count 0 2006.257.12:01:11.13#ibcon#wrote, iclass 38, count 0 2006.257.12:01:11.13#ibcon#about to read 3, iclass 38, count 0 2006.257.12:01:11.15#ibcon#read 3, iclass 38, count 0 2006.257.12:01:11.15#ibcon#about to read 4, iclass 38, count 0 2006.257.12:01:11.15#ibcon#read 4, iclass 38, count 0 2006.257.12:01:11.15#ibcon#about to read 5, iclass 38, count 0 2006.257.12:01:11.15#ibcon#read 5, iclass 38, count 0 2006.257.12:01:11.15#ibcon#about to read 6, iclass 38, count 0 2006.257.12:01:11.15#ibcon#read 6, iclass 38, count 0 2006.257.12:01:11.15#ibcon#end of sib2, iclass 38, count 0 2006.257.12:01:11.15#ibcon#*mode == 0, iclass 38, count 0 2006.257.12:01:11.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.12:01:11.15#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:01:11.15#ibcon#*before write, iclass 38, count 0 2006.257.12:01:11.15#ibcon#enter sib2, iclass 38, count 0 2006.257.12:01:11.15#ibcon#flushed, iclass 38, count 0 2006.257.12:01:11.15#ibcon#about to write, iclass 38, count 0 2006.257.12:01:11.15#ibcon#wrote, iclass 38, count 0 2006.257.12:01:11.15#ibcon#about to read 3, iclass 38, count 0 2006.257.12:01:11.19#ibcon#read 3, iclass 38, count 0 2006.257.12:01:11.19#ibcon#about to read 4, iclass 38, count 0 2006.257.12:01:11.19#ibcon#read 4, iclass 38, count 0 2006.257.12:01:11.19#ibcon#about to read 5, iclass 38, count 0 2006.257.12:01:11.19#ibcon#read 5, iclass 38, count 0 2006.257.12:01:11.19#ibcon#about to read 6, iclass 38, count 0 2006.257.12:01:11.19#ibcon#read 6, iclass 38, count 0 2006.257.12:01:11.19#ibcon#end of sib2, iclass 38, count 0 2006.257.12:01:11.19#ibcon#*after write, iclass 38, count 0 2006.257.12:01:11.19#ibcon#*before return 0, iclass 38, count 0 2006.257.12:01:11.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:11.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:01:11.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.12:01:11.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.12:01:11.19$vck44/vb=6,4 2006.257.12:01:11.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.12:01:11.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.12:01:11.19#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:11.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:11.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:11.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:11.25#ibcon#enter wrdev, iclass 40, count 2 2006.257.12:01:11.25#ibcon#first serial, iclass 40, count 2 2006.257.12:01:11.25#ibcon#enter sib2, iclass 40, count 2 2006.257.12:01:11.25#ibcon#flushed, iclass 40, count 2 2006.257.12:01:11.25#ibcon#about to write, iclass 40, count 2 2006.257.12:01:11.25#ibcon#wrote, iclass 40, count 2 2006.257.12:01:11.25#ibcon#about to read 3, iclass 40, count 2 2006.257.12:01:11.27#ibcon#read 3, iclass 40, count 2 2006.257.12:01:11.27#ibcon#about to read 4, iclass 40, count 2 2006.257.12:01:11.27#ibcon#read 4, iclass 40, count 2 2006.257.12:01:11.27#ibcon#about to read 5, iclass 40, count 2 2006.257.12:01:11.27#ibcon#read 5, iclass 40, count 2 2006.257.12:01:11.27#ibcon#about to read 6, iclass 40, count 2 2006.257.12:01:11.27#ibcon#read 6, iclass 40, count 2 2006.257.12:01:11.27#ibcon#end of sib2, iclass 40, count 2 2006.257.12:01:11.27#ibcon#*mode == 0, iclass 40, count 2 2006.257.12:01:11.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.12:01:11.27#ibcon#[27=AT06-04\r\n] 2006.257.12:01:11.27#ibcon#*before write, iclass 40, count 2 2006.257.12:01:11.27#ibcon#enter sib2, iclass 40, count 2 2006.257.12:01:11.27#ibcon#flushed, iclass 40, count 2 2006.257.12:01:11.27#ibcon#about to write, iclass 40, count 2 2006.257.12:01:11.27#ibcon#wrote, iclass 40, count 2 2006.257.12:01:11.27#ibcon#about to read 3, iclass 40, count 2 2006.257.12:01:11.30#ibcon#read 3, iclass 40, count 2 2006.257.12:01:11.30#ibcon#about to read 4, iclass 40, count 2 2006.257.12:01:11.30#ibcon#read 4, iclass 40, count 2 2006.257.12:01:11.30#ibcon#about to read 5, iclass 40, count 2 2006.257.12:01:11.30#ibcon#read 5, iclass 40, count 2 2006.257.12:01:11.30#ibcon#about to read 6, iclass 40, count 2 2006.257.12:01:11.30#ibcon#read 6, iclass 40, count 2 2006.257.12:01:11.30#ibcon#end of sib2, iclass 40, count 2 2006.257.12:01:11.30#ibcon#*after write, iclass 40, count 2 2006.257.12:01:11.30#ibcon#*before return 0, iclass 40, count 2 2006.257.12:01:11.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:11.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:01:11.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.12:01:11.30#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:11.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:11.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:11.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:11.42#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:01:11.42#ibcon#first serial, iclass 40, count 0 2006.257.12:01:11.42#ibcon#enter sib2, iclass 40, count 0 2006.257.12:01:11.42#ibcon#flushed, iclass 40, count 0 2006.257.12:01:11.42#ibcon#about to write, iclass 40, count 0 2006.257.12:01:11.42#ibcon#wrote, iclass 40, count 0 2006.257.12:01:11.42#ibcon#about to read 3, iclass 40, count 0 2006.257.12:01:11.44#ibcon#read 3, iclass 40, count 0 2006.257.12:01:11.44#ibcon#about to read 4, iclass 40, count 0 2006.257.12:01:11.44#ibcon#read 4, iclass 40, count 0 2006.257.12:01:11.44#ibcon#about to read 5, iclass 40, count 0 2006.257.12:01:11.44#ibcon#read 5, iclass 40, count 0 2006.257.12:01:11.44#ibcon#about to read 6, iclass 40, count 0 2006.257.12:01:11.44#ibcon#read 6, iclass 40, count 0 2006.257.12:01:11.44#ibcon#end of sib2, iclass 40, count 0 2006.257.12:01:11.44#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:01:11.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:01:11.44#ibcon#[27=USB\r\n] 2006.257.12:01:11.44#ibcon#*before write, iclass 40, count 0 2006.257.12:01:11.44#ibcon#enter sib2, iclass 40, count 0 2006.257.12:01:11.44#ibcon#flushed, iclass 40, count 0 2006.257.12:01:11.44#ibcon#about to write, iclass 40, count 0 2006.257.12:01:11.44#ibcon#wrote, iclass 40, count 0 2006.257.12:01:11.44#ibcon#about to read 3, iclass 40, count 0 2006.257.12:01:11.47#ibcon#read 3, iclass 40, count 0 2006.257.12:01:11.47#ibcon#about to read 4, iclass 40, count 0 2006.257.12:01:11.47#ibcon#read 4, iclass 40, count 0 2006.257.12:01:11.47#ibcon#about to read 5, iclass 40, count 0 2006.257.12:01:11.47#ibcon#read 5, iclass 40, count 0 2006.257.12:01:11.47#ibcon#about to read 6, iclass 40, count 0 2006.257.12:01:11.47#ibcon#read 6, iclass 40, count 0 2006.257.12:01:11.47#ibcon#end of sib2, iclass 40, count 0 2006.257.12:01:11.47#ibcon#*after write, iclass 40, count 0 2006.257.12:01:11.47#ibcon#*before return 0, iclass 40, count 0 2006.257.12:01:11.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:11.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:01:11.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:01:11.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:01:11.47$vck44/vblo=7,734.99 2006.257.12:01:11.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.12:01:11.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.12:01:11.47#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:11.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:11.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:11.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:11.47#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:01:11.47#ibcon#first serial, iclass 4, count 0 2006.257.12:01:11.47#ibcon#enter sib2, iclass 4, count 0 2006.257.12:01:11.47#ibcon#flushed, iclass 4, count 0 2006.257.12:01:11.47#ibcon#about to write, iclass 4, count 0 2006.257.12:01:11.47#ibcon#wrote, iclass 4, count 0 2006.257.12:01:11.47#ibcon#about to read 3, iclass 4, count 0 2006.257.12:01:11.49#ibcon#read 3, iclass 4, count 0 2006.257.12:01:11.49#ibcon#about to read 4, iclass 4, count 0 2006.257.12:01:11.49#ibcon#read 4, iclass 4, count 0 2006.257.12:01:11.49#ibcon#about to read 5, iclass 4, count 0 2006.257.12:01:11.49#ibcon#read 5, iclass 4, count 0 2006.257.12:01:11.49#ibcon#about to read 6, iclass 4, count 0 2006.257.12:01:11.49#ibcon#read 6, iclass 4, count 0 2006.257.12:01:11.49#ibcon#end of sib2, iclass 4, count 0 2006.257.12:01:11.49#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:01:11.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:01:11.49#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:01:11.49#ibcon#*before write, iclass 4, count 0 2006.257.12:01:11.49#ibcon#enter sib2, iclass 4, count 0 2006.257.12:01:11.49#ibcon#flushed, iclass 4, count 0 2006.257.12:01:11.49#ibcon#about to write, iclass 4, count 0 2006.257.12:01:11.49#ibcon#wrote, iclass 4, count 0 2006.257.12:01:11.49#ibcon#about to read 3, iclass 4, count 0 2006.257.12:01:11.53#ibcon#read 3, iclass 4, count 0 2006.257.12:01:11.53#ibcon#about to read 4, iclass 4, count 0 2006.257.12:01:11.53#ibcon#read 4, iclass 4, count 0 2006.257.12:01:11.53#ibcon#about to read 5, iclass 4, count 0 2006.257.12:01:11.53#ibcon#read 5, iclass 4, count 0 2006.257.12:01:11.53#ibcon#about to read 6, iclass 4, count 0 2006.257.12:01:11.53#ibcon#read 6, iclass 4, count 0 2006.257.12:01:11.53#ibcon#end of sib2, iclass 4, count 0 2006.257.12:01:11.53#ibcon#*after write, iclass 4, count 0 2006.257.12:01:11.53#ibcon#*before return 0, iclass 4, count 0 2006.257.12:01:11.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:11.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:01:11.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:01:11.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:01:11.53$vck44/vb=7,4 2006.257.12:01:11.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.12:01:11.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.12:01:11.53#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:11.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:11.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:11.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:11.59#ibcon#enter wrdev, iclass 6, count 2 2006.257.12:01:11.59#ibcon#first serial, iclass 6, count 2 2006.257.12:01:11.59#ibcon#enter sib2, iclass 6, count 2 2006.257.12:01:11.59#ibcon#flushed, iclass 6, count 2 2006.257.12:01:11.59#ibcon#about to write, iclass 6, count 2 2006.257.12:01:11.59#ibcon#wrote, iclass 6, count 2 2006.257.12:01:11.59#ibcon#about to read 3, iclass 6, count 2 2006.257.12:01:11.61#ibcon#read 3, iclass 6, count 2 2006.257.12:01:11.61#ibcon#about to read 4, iclass 6, count 2 2006.257.12:01:11.61#ibcon#read 4, iclass 6, count 2 2006.257.12:01:11.61#ibcon#about to read 5, iclass 6, count 2 2006.257.12:01:11.61#ibcon#read 5, iclass 6, count 2 2006.257.12:01:11.61#ibcon#about to read 6, iclass 6, count 2 2006.257.12:01:11.61#ibcon#read 6, iclass 6, count 2 2006.257.12:01:11.61#ibcon#end of sib2, iclass 6, count 2 2006.257.12:01:11.61#ibcon#*mode == 0, iclass 6, count 2 2006.257.12:01:11.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.12:01:11.61#ibcon#[27=AT07-04\r\n] 2006.257.12:01:11.61#ibcon#*before write, iclass 6, count 2 2006.257.12:01:11.61#ibcon#enter sib2, iclass 6, count 2 2006.257.12:01:11.61#ibcon#flushed, iclass 6, count 2 2006.257.12:01:11.61#ibcon#about to write, iclass 6, count 2 2006.257.12:01:11.61#ibcon#wrote, iclass 6, count 2 2006.257.12:01:11.61#ibcon#about to read 3, iclass 6, count 2 2006.257.12:01:11.64#ibcon#read 3, iclass 6, count 2 2006.257.12:01:11.64#ibcon#about to read 4, iclass 6, count 2 2006.257.12:01:11.64#ibcon#read 4, iclass 6, count 2 2006.257.12:01:11.64#ibcon#about to read 5, iclass 6, count 2 2006.257.12:01:11.64#ibcon#read 5, iclass 6, count 2 2006.257.12:01:11.64#ibcon#about to read 6, iclass 6, count 2 2006.257.12:01:11.64#ibcon#read 6, iclass 6, count 2 2006.257.12:01:11.64#ibcon#end of sib2, iclass 6, count 2 2006.257.12:01:11.64#ibcon#*after write, iclass 6, count 2 2006.257.12:01:11.64#ibcon#*before return 0, iclass 6, count 2 2006.257.12:01:11.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:11.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:01:11.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.12:01:11.64#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:11.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:11.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:11.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:11.76#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:01:11.76#ibcon#first serial, iclass 6, count 0 2006.257.12:01:11.76#ibcon#enter sib2, iclass 6, count 0 2006.257.12:01:11.76#ibcon#flushed, iclass 6, count 0 2006.257.12:01:11.76#ibcon#about to write, iclass 6, count 0 2006.257.12:01:11.76#ibcon#wrote, iclass 6, count 0 2006.257.12:01:11.76#ibcon#about to read 3, iclass 6, count 0 2006.257.12:01:11.78#ibcon#read 3, iclass 6, count 0 2006.257.12:01:11.78#ibcon#about to read 4, iclass 6, count 0 2006.257.12:01:11.78#ibcon#read 4, iclass 6, count 0 2006.257.12:01:11.78#ibcon#about to read 5, iclass 6, count 0 2006.257.12:01:11.78#ibcon#read 5, iclass 6, count 0 2006.257.12:01:11.78#ibcon#about to read 6, iclass 6, count 0 2006.257.12:01:11.78#ibcon#read 6, iclass 6, count 0 2006.257.12:01:11.78#ibcon#end of sib2, iclass 6, count 0 2006.257.12:01:11.78#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:01:11.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:01:11.78#ibcon#[27=USB\r\n] 2006.257.12:01:11.78#ibcon#*before write, iclass 6, count 0 2006.257.12:01:11.78#ibcon#enter sib2, iclass 6, count 0 2006.257.12:01:11.78#ibcon#flushed, iclass 6, count 0 2006.257.12:01:11.78#ibcon#about to write, iclass 6, count 0 2006.257.12:01:11.78#ibcon#wrote, iclass 6, count 0 2006.257.12:01:11.78#ibcon#about to read 3, iclass 6, count 0 2006.257.12:01:11.81#ibcon#read 3, iclass 6, count 0 2006.257.12:01:11.81#ibcon#about to read 4, iclass 6, count 0 2006.257.12:01:11.81#ibcon#read 4, iclass 6, count 0 2006.257.12:01:11.81#ibcon#about to read 5, iclass 6, count 0 2006.257.12:01:11.81#ibcon#read 5, iclass 6, count 0 2006.257.12:01:11.81#ibcon#about to read 6, iclass 6, count 0 2006.257.12:01:11.81#ibcon#read 6, iclass 6, count 0 2006.257.12:01:11.81#ibcon#end of sib2, iclass 6, count 0 2006.257.12:01:11.81#ibcon#*after write, iclass 6, count 0 2006.257.12:01:11.81#ibcon#*before return 0, iclass 6, count 0 2006.257.12:01:11.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:11.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:01:11.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:01:11.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:01:11.81$vck44/vblo=8,744.99 2006.257.12:01:11.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.12:01:11.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.12:01:11.81#ibcon#ireg 17 cls_cnt 0 2006.257.12:01:11.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:11.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:11.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:11.81#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:01:11.81#ibcon#first serial, iclass 10, count 0 2006.257.12:01:11.81#ibcon#enter sib2, iclass 10, count 0 2006.257.12:01:11.81#ibcon#flushed, iclass 10, count 0 2006.257.12:01:11.81#ibcon#about to write, iclass 10, count 0 2006.257.12:01:11.81#ibcon#wrote, iclass 10, count 0 2006.257.12:01:11.81#ibcon#about to read 3, iclass 10, count 0 2006.257.12:01:11.83#ibcon#read 3, iclass 10, count 0 2006.257.12:01:11.83#ibcon#about to read 4, iclass 10, count 0 2006.257.12:01:11.83#ibcon#read 4, iclass 10, count 0 2006.257.12:01:11.83#ibcon#about to read 5, iclass 10, count 0 2006.257.12:01:11.83#ibcon#read 5, iclass 10, count 0 2006.257.12:01:11.83#ibcon#about to read 6, iclass 10, count 0 2006.257.12:01:11.83#ibcon#read 6, iclass 10, count 0 2006.257.12:01:11.83#ibcon#end of sib2, iclass 10, count 0 2006.257.12:01:11.83#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:01:11.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:01:11.83#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:01:11.83#ibcon#*before write, iclass 10, count 0 2006.257.12:01:11.83#ibcon#enter sib2, iclass 10, count 0 2006.257.12:01:11.83#ibcon#flushed, iclass 10, count 0 2006.257.12:01:11.83#ibcon#about to write, iclass 10, count 0 2006.257.12:01:11.83#ibcon#wrote, iclass 10, count 0 2006.257.12:01:11.83#ibcon#about to read 3, iclass 10, count 0 2006.257.12:01:11.87#ibcon#read 3, iclass 10, count 0 2006.257.12:01:11.87#ibcon#about to read 4, iclass 10, count 0 2006.257.12:01:11.87#ibcon#read 4, iclass 10, count 0 2006.257.12:01:11.87#ibcon#about to read 5, iclass 10, count 0 2006.257.12:01:11.87#ibcon#read 5, iclass 10, count 0 2006.257.12:01:11.87#ibcon#about to read 6, iclass 10, count 0 2006.257.12:01:11.87#ibcon#read 6, iclass 10, count 0 2006.257.12:01:11.87#ibcon#end of sib2, iclass 10, count 0 2006.257.12:01:11.87#ibcon#*after write, iclass 10, count 0 2006.257.12:01:11.87#ibcon#*before return 0, iclass 10, count 0 2006.257.12:01:11.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:11.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:01:11.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:01:11.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:01:11.87$vck44/vb=8,4 2006.257.12:01:11.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.12:01:11.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.12:01:11.87#ibcon#ireg 11 cls_cnt 2 2006.257.12:01:11.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:11.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:11.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:11.93#ibcon#enter wrdev, iclass 12, count 2 2006.257.12:01:11.93#ibcon#first serial, iclass 12, count 2 2006.257.12:01:11.93#ibcon#enter sib2, iclass 12, count 2 2006.257.12:01:11.93#ibcon#flushed, iclass 12, count 2 2006.257.12:01:11.93#ibcon#about to write, iclass 12, count 2 2006.257.12:01:11.93#ibcon#wrote, iclass 12, count 2 2006.257.12:01:11.93#ibcon#about to read 3, iclass 12, count 2 2006.257.12:01:11.95#ibcon#read 3, iclass 12, count 2 2006.257.12:01:11.95#ibcon#about to read 4, iclass 12, count 2 2006.257.12:01:11.95#ibcon#read 4, iclass 12, count 2 2006.257.12:01:11.95#ibcon#about to read 5, iclass 12, count 2 2006.257.12:01:11.95#ibcon#read 5, iclass 12, count 2 2006.257.12:01:11.95#ibcon#about to read 6, iclass 12, count 2 2006.257.12:01:11.95#ibcon#read 6, iclass 12, count 2 2006.257.12:01:11.95#ibcon#end of sib2, iclass 12, count 2 2006.257.12:01:11.95#ibcon#*mode == 0, iclass 12, count 2 2006.257.12:01:11.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.12:01:11.95#ibcon#[27=AT08-04\r\n] 2006.257.12:01:11.95#ibcon#*before write, iclass 12, count 2 2006.257.12:01:11.95#ibcon#enter sib2, iclass 12, count 2 2006.257.12:01:11.95#ibcon#flushed, iclass 12, count 2 2006.257.12:01:11.95#ibcon#about to write, iclass 12, count 2 2006.257.12:01:11.95#ibcon#wrote, iclass 12, count 2 2006.257.12:01:11.95#ibcon#about to read 3, iclass 12, count 2 2006.257.12:01:11.98#ibcon#read 3, iclass 12, count 2 2006.257.12:01:11.98#ibcon#about to read 4, iclass 12, count 2 2006.257.12:01:11.98#ibcon#read 4, iclass 12, count 2 2006.257.12:01:11.98#ibcon#about to read 5, iclass 12, count 2 2006.257.12:01:11.98#ibcon#read 5, iclass 12, count 2 2006.257.12:01:11.98#ibcon#about to read 6, iclass 12, count 2 2006.257.12:01:11.98#ibcon#read 6, iclass 12, count 2 2006.257.12:01:11.98#ibcon#end of sib2, iclass 12, count 2 2006.257.12:01:11.98#ibcon#*after write, iclass 12, count 2 2006.257.12:01:11.98#ibcon#*before return 0, iclass 12, count 2 2006.257.12:01:11.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:11.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:01:11.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.12:01:11.98#ibcon#ireg 7 cls_cnt 0 2006.257.12:01:11.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:12.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:12.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:12.10#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:01:12.10#ibcon#first serial, iclass 12, count 0 2006.257.12:01:12.10#ibcon#enter sib2, iclass 12, count 0 2006.257.12:01:12.10#ibcon#flushed, iclass 12, count 0 2006.257.12:01:12.10#ibcon#about to write, iclass 12, count 0 2006.257.12:01:12.10#ibcon#wrote, iclass 12, count 0 2006.257.12:01:12.10#ibcon#about to read 3, iclass 12, count 0 2006.257.12:01:12.12#ibcon#read 3, iclass 12, count 0 2006.257.12:01:12.12#ibcon#about to read 4, iclass 12, count 0 2006.257.12:01:12.12#ibcon#read 4, iclass 12, count 0 2006.257.12:01:12.12#ibcon#about to read 5, iclass 12, count 0 2006.257.12:01:12.12#ibcon#read 5, iclass 12, count 0 2006.257.12:01:12.12#ibcon#about to read 6, iclass 12, count 0 2006.257.12:01:12.12#ibcon#read 6, iclass 12, count 0 2006.257.12:01:12.12#ibcon#end of sib2, iclass 12, count 0 2006.257.12:01:12.12#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:01:12.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:01:12.12#ibcon#[27=USB\r\n] 2006.257.12:01:12.12#ibcon#*before write, iclass 12, count 0 2006.257.12:01:12.12#ibcon#enter sib2, iclass 12, count 0 2006.257.12:01:12.12#ibcon#flushed, iclass 12, count 0 2006.257.12:01:12.12#ibcon#about to write, iclass 12, count 0 2006.257.12:01:12.12#ibcon#wrote, iclass 12, count 0 2006.257.12:01:12.12#ibcon#about to read 3, iclass 12, count 0 2006.257.12:01:12.15#ibcon#read 3, iclass 12, count 0 2006.257.12:01:12.15#ibcon#about to read 4, iclass 12, count 0 2006.257.12:01:12.15#ibcon#read 4, iclass 12, count 0 2006.257.12:01:12.15#ibcon#about to read 5, iclass 12, count 0 2006.257.12:01:12.15#ibcon#read 5, iclass 12, count 0 2006.257.12:01:12.15#ibcon#about to read 6, iclass 12, count 0 2006.257.12:01:12.15#ibcon#read 6, iclass 12, count 0 2006.257.12:01:12.15#ibcon#end of sib2, iclass 12, count 0 2006.257.12:01:12.15#ibcon#*after write, iclass 12, count 0 2006.257.12:01:12.15#ibcon#*before return 0, iclass 12, count 0 2006.257.12:01:12.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:12.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:01:12.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:01:12.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:01:12.15$vck44/vabw=wide 2006.257.12:01:12.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.12:01:12.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.12:01:12.15#ibcon#ireg 8 cls_cnt 0 2006.257.12:01:12.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:12.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:12.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:12.15#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:01:12.15#ibcon#first serial, iclass 14, count 0 2006.257.12:01:12.15#ibcon#enter sib2, iclass 14, count 0 2006.257.12:01:12.15#ibcon#flushed, iclass 14, count 0 2006.257.12:01:12.15#ibcon#about to write, iclass 14, count 0 2006.257.12:01:12.15#ibcon#wrote, iclass 14, count 0 2006.257.12:01:12.15#ibcon#about to read 3, iclass 14, count 0 2006.257.12:01:12.17#ibcon#read 3, iclass 14, count 0 2006.257.12:01:12.17#ibcon#about to read 4, iclass 14, count 0 2006.257.12:01:12.17#ibcon#read 4, iclass 14, count 0 2006.257.12:01:12.17#ibcon#about to read 5, iclass 14, count 0 2006.257.12:01:12.17#ibcon#read 5, iclass 14, count 0 2006.257.12:01:12.17#ibcon#about to read 6, iclass 14, count 0 2006.257.12:01:12.17#ibcon#read 6, iclass 14, count 0 2006.257.12:01:12.17#ibcon#end of sib2, iclass 14, count 0 2006.257.12:01:12.17#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:01:12.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:01:12.17#ibcon#[25=BW32\r\n] 2006.257.12:01:12.17#ibcon#*before write, iclass 14, count 0 2006.257.12:01:12.17#ibcon#enter sib2, iclass 14, count 0 2006.257.12:01:12.17#ibcon#flushed, iclass 14, count 0 2006.257.12:01:12.17#ibcon#about to write, iclass 14, count 0 2006.257.12:01:12.17#ibcon#wrote, iclass 14, count 0 2006.257.12:01:12.17#ibcon#about to read 3, iclass 14, count 0 2006.257.12:01:12.20#ibcon#read 3, iclass 14, count 0 2006.257.12:01:12.20#ibcon#about to read 4, iclass 14, count 0 2006.257.12:01:12.20#ibcon#read 4, iclass 14, count 0 2006.257.12:01:12.20#ibcon#about to read 5, iclass 14, count 0 2006.257.12:01:12.20#ibcon#read 5, iclass 14, count 0 2006.257.12:01:12.20#ibcon#about to read 6, iclass 14, count 0 2006.257.12:01:12.20#ibcon#read 6, iclass 14, count 0 2006.257.12:01:12.20#ibcon#end of sib2, iclass 14, count 0 2006.257.12:01:12.20#ibcon#*after write, iclass 14, count 0 2006.257.12:01:12.20#ibcon#*before return 0, iclass 14, count 0 2006.257.12:01:12.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:12.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:01:12.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:01:12.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:01:12.20$vck44/vbbw=wide 2006.257.12:01:12.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.12:01:12.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.12:01:12.20#ibcon#ireg 8 cls_cnt 0 2006.257.12:01:12.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:01:12.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:01:12.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:01:12.27#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:01:12.27#ibcon#first serial, iclass 16, count 0 2006.257.12:01:12.27#ibcon#enter sib2, iclass 16, count 0 2006.257.12:01:12.27#ibcon#flushed, iclass 16, count 0 2006.257.12:01:12.27#ibcon#about to write, iclass 16, count 0 2006.257.12:01:12.27#ibcon#wrote, iclass 16, count 0 2006.257.12:01:12.27#ibcon#about to read 3, iclass 16, count 0 2006.257.12:01:12.29#ibcon#read 3, iclass 16, count 0 2006.257.12:01:12.29#ibcon#about to read 4, iclass 16, count 0 2006.257.12:01:12.29#ibcon#read 4, iclass 16, count 0 2006.257.12:01:12.29#ibcon#about to read 5, iclass 16, count 0 2006.257.12:01:12.29#ibcon#read 5, iclass 16, count 0 2006.257.12:01:12.29#ibcon#about to read 6, iclass 16, count 0 2006.257.12:01:12.29#ibcon#read 6, iclass 16, count 0 2006.257.12:01:12.29#ibcon#end of sib2, iclass 16, count 0 2006.257.12:01:12.29#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:01:12.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:01:12.29#ibcon#[27=BW32\r\n] 2006.257.12:01:12.29#ibcon#*before write, iclass 16, count 0 2006.257.12:01:12.29#ibcon#enter sib2, iclass 16, count 0 2006.257.12:01:12.29#ibcon#flushed, iclass 16, count 0 2006.257.12:01:12.29#ibcon#about to write, iclass 16, count 0 2006.257.12:01:12.29#ibcon#wrote, iclass 16, count 0 2006.257.12:01:12.29#ibcon#about to read 3, iclass 16, count 0 2006.257.12:01:12.32#ibcon#read 3, iclass 16, count 0 2006.257.12:01:12.32#ibcon#about to read 4, iclass 16, count 0 2006.257.12:01:12.32#ibcon#read 4, iclass 16, count 0 2006.257.12:01:12.32#ibcon#about to read 5, iclass 16, count 0 2006.257.12:01:12.32#ibcon#read 5, iclass 16, count 0 2006.257.12:01:12.32#ibcon#about to read 6, iclass 16, count 0 2006.257.12:01:12.32#ibcon#read 6, iclass 16, count 0 2006.257.12:01:12.32#ibcon#end of sib2, iclass 16, count 0 2006.257.12:01:12.32#ibcon#*after write, iclass 16, count 0 2006.257.12:01:12.32#ibcon#*before return 0, iclass 16, count 0 2006.257.12:01:12.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:01:12.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:01:12.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:01:12.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:01:12.32$setupk4/ifdk4 2006.257.12:01:12.32$ifdk4/lo= 2006.257.12:01:12.32$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:01:12.32$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:01:12.32$ifdk4/patch= 2006.257.12:01:12.32$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:01:12.32$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:01:12.32$setupk4/!*+20s 2006.257.12:01:12.77#abcon#<5=/14 1.6 3.5 18.20 951013.9\r\n> 2006.257.12:01:12.79#abcon#{5=INTERFACE CLEAR} 2006.257.12:01:12.85#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:01:22.94#abcon#<5=/14 1.6 3.5 18.20 951013.9\r\n> 2006.257.12:01:22.96#abcon#{5=INTERFACE CLEAR} 2006.257.12:01:23.02#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:01:25.26$setupk4/"tpicd 2006.257.12:01:25.26$setupk4/echo=off 2006.257.12:01:25.26$setupk4/xlog=off 2006.257.12:01:25.26:!2006.257.12:02:34 2006.257.12:01:37.14#trakl#Source acquired 2006.257.12:01:39.14#flagr#flagr/antenna,acquired 2006.257.12:02:34.02:preob 2006.257.12:02:35.14/onsource/TRACKING 2006.257.12:02:35.14:!2006.257.12:02:44 2006.257.12:02:44.01:"tape 2006.257.12:02:44.02:"st=record 2006.257.12:02:44.02:data_valid=on 2006.257.12:02:44.02:midob 2006.257.12:02:45.15/onsource/TRACKING 2006.257.12:02:45.15/wx/18.20,1013.9,95 2006.257.12:02:45.28/cable/+6.4797E-03 2006.257.12:02:46.37/va/01,08,usb,yes,30,33 2006.257.12:02:46.38/va/02,07,usb,yes,33,33 2006.257.12:02:46.38/va/03,08,usb,yes,29,31 2006.257.12:02:46.38/va/04,07,usb,yes,34,35 2006.257.12:02:46.38/va/05,04,usb,yes,30,31 2006.257.12:02:46.38/va/06,04,usb,yes,34,33 2006.257.12:02:46.38/va/07,04,usb,yes,35,35 2006.257.12:02:46.38/va/08,04,usb,yes,29,35 2006.257.12:02:46.61/valo/01,524.99,yes,locked 2006.257.12:02:46.61/valo/02,534.99,yes,locked 2006.257.12:02:46.61/valo/03,564.99,yes,locked 2006.257.12:02:46.61/valo/04,624.99,yes,locked 2006.257.12:02:46.61/valo/05,734.99,yes,locked 2006.257.12:02:46.61/valo/06,814.99,yes,locked 2006.257.12:02:46.61/valo/07,864.99,yes,locked 2006.257.12:02:46.61/valo/08,884.99,yes,locked 2006.257.12:02:47.69/vb/01,04,usb,yes,30,28 2006.257.12:02:47.70/vb/02,05,usb,yes,29,29 2006.257.12:02:47.70/vb/03,04,usb,yes,30,33 2006.257.12:02:47.70/vb/04,05,usb,yes,30,29 2006.257.12:02:47.70/vb/05,04,usb,yes,26,29 2006.257.12:02:47.70/vb/06,04,usb,yes,31,27 2006.257.12:02:47.70/vb/07,04,usb,yes,31,31 2006.257.12:02:47.70/vb/08,04,usb,yes,28,32 2006.257.12:02:47.93/vblo/01,629.99,yes,locked 2006.257.12:02:47.93/vblo/02,634.99,yes,locked 2006.257.12:02:47.93/vblo/03,649.99,yes,locked 2006.257.12:02:47.93/vblo/04,679.99,yes,locked 2006.257.12:02:47.93/vblo/05,709.99,yes,locked 2006.257.12:02:47.93/vblo/06,719.99,yes,locked 2006.257.12:02:47.93/vblo/07,734.99,yes,locked 2006.257.12:02:47.93/vblo/08,744.99,yes,locked 2006.257.12:02:48.07/vabw/8 2006.257.12:02:48.22/vbbw/8 2006.257.12:02:48.32/xfe/off,on,15.2 2006.257.12:02:48.69/ifatt/23,28,28,28 2006.257.12:02:49.07/fmout-gps/S +4.59E-07 2006.257.12:02:49.11:!2006.257.12:05:24 2006.257.12:05:24.01:data_valid=off 2006.257.12:05:24.02:"et 2006.257.12:05:24.02:!+3s 2006.257.12:05:27.04:"tape 2006.257.12:05:27.04:postob 2006.257.12:05:27.19/cable/+6.4804E-03 2006.257.12:05:27.20/wx/18.19,1013.9,95 2006.257.12:05:27.25/fmout-gps/S +4.60E-07 2006.257.12:05:27.25:scan_name=257-1208,jd0609,380 2006.257.12:05:27.26:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.257.12:05:28.13#flagr#flagr/antenna,new-source 2006.257.12:05:28.14:checkk5 2006.257.12:05:28.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:05:28.87/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:05:29.27/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:05:29.65/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:05:30.03/chk_obsdata//k5ts1/T2571202??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:05:30.40/chk_obsdata//k5ts2/T2571202??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:05:30.79/chk_obsdata//k5ts3/T2571202??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:05:31.17/chk_obsdata//k5ts4/T2571202??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:05:31.90/k5log//k5ts1_log_newline 2006.257.12:05:32.60/k5log//k5ts2_log_newline 2006.257.12:05:33.30/k5log//k5ts3_log_newline 2006.257.12:05:34.00/k5log//k5ts4_log_newline 2006.257.12:05:34.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:05:34.02:setupk4=1 2006.257.12:05:34.02$setupk4/echo=on 2006.257.12:05:34.02$setupk4/pcalon 2006.257.12:05:34.02$pcalon/"no phase cal control is implemented here 2006.257.12:05:34.02$setupk4/"tpicd=stop 2006.257.12:05:34.02$setupk4/"rec=synch_on 2006.257.12:05:34.02$setupk4/"rec_mode=128 2006.257.12:05:34.02$setupk4/!* 2006.257.12:05:34.02$setupk4/recpk4 2006.257.12:05:34.02$recpk4/recpatch= 2006.257.12:05:34.03$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:05:34.03$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:05:34.03$setupk4/vck44 2006.257.12:05:34.03$vck44/valo=1,524.99 2006.257.12:05:34.03#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.12:05:34.03#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.12:05:34.03#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:34.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:34.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:34.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:34.03#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:05:34.03#ibcon#first serial, iclass 17, count 0 2006.257.12:05:34.03#ibcon#enter sib2, iclass 17, count 0 2006.257.12:05:34.03#ibcon#flushed, iclass 17, count 0 2006.257.12:05:34.03#ibcon#about to write, iclass 17, count 0 2006.257.12:05:34.03#ibcon#wrote, iclass 17, count 0 2006.257.12:05:34.03#ibcon#about to read 3, iclass 17, count 0 2006.257.12:05:34.04#ibcon#read 3, iclass 17, count 0 2006.257.12:05:34.04#ibcon#about to read 4, iclass 17, count 0 2006.257.12:05:34.04#ibcon#read 4, iclass 17, count 0 2006.257.12:05:34.04#ibcon#about to read 5, iclass 17, count 0 2006.257.12:05:34.04#ibcon#read 5, iclass 17, count 0 2006.257.12:05:34.04#ibcon#about to read 6, iclass 17, count 0 2006.257.12:05:34.04#ibcon#read 6, iclass 17, count 0 2006.257.12:05:34.04#ibcon#end of sib2, iclass 17, count 0 2006.257.12:05:34.04#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:05:34.04#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:05:34.04#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:05:34.04#ibcon#*before write, iclass 17, count 0 2006.257.12:05:34.04#ibcon#enter sib2, iclass 17, count 0 2006.257.12:05:34.04#ibcon#flushed, iclass 17, count 0 2006.257.12:05:34.04#ibcon#about to write, iclass 17, count 0 2006.257.12:05:34.04#ibcon#wrote, iclass 17, count 0 2006.257.12:05:34.04#ibcon#about to read 3, iclass 17, count 0 2006.257.12:05:34.09#ibcon#read 3, iclass 17, count 0 2006.257.12:05:34.09#ibcon#about to read 4, iclass 17, count 0 2006.257.12:05:34.09#ibcon#read 4, iclass 17, count 0 2006.257.12:05:34.09#ibcon#about to read 5, iclass 17, count 0 2006.257.12:05:34.09#ibcon#read 5, iclass 17, count 0 2006.257.12:05:34.09#ibcon#about to read 6, iclass 17, count 0 2006.257.12:05:34.09#ibcon#read 6, iclass 17, count 0 2006.257.12:05:34.09#ibcon#end of sib2, iclass 17, count 0 2006.257.12:05:34.09#ibcon#*after write, iclass 17, count 0 2006.257.12:05:34.09#ibcon#*before return 0, iclass 17, count 0 2006.257.12:05:34.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:34.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:34.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:05:34.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:05:34.09$vck44/va=1,8 2006.257.12:05:34.09#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.12:05:34.09#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.12:05:34.09#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:34.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:34.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:34.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:34.09#ibcon#enter wrdev, iclass 19, count 2 2006.257.12:05:34.09#ibcon#first serial, iclass 19, count 2 2006.257.12:05:34.09#ibcon#enter sib2, iclass 19, count 2 2006.257.12:05:34.09#ibcon#flushed, iclass 19, count 2 2006.257.12:05:34.09#ibcon#about to write, iclass 19, count 2 2006.257.12:05:34.09#ibcon#wrote, iclass 19, count 2 2006.257.12:05:34.09#ibcon#about to read 3, iclass 19, count 2 2006.257.12:05:34.11#ibcon#read 3, iclass 19, count 2 2006.257.12:05:34.11#ibcon#about to read 4, iclass 19, count 2 2006.257.12:05:34.11#ibcon#read 4, iclass 19, count 2 2006.257.12:05:34.11#ibcon#about to read 5, iclass 19, count 2 2006.257.12:05:34.11#ibcon#read 5, iclass 19, count 2 2006.257.12:05:34.11#ibcon#about to read 6, iclass 19, count 2 2006.257.12:05:34.11#ibcon#read 6, iclass 19, count 2 2006.257.12:05:34.11#ibcon#end of sib2, iclass 19, count 2 2006.257.12:05:34.11#ibcon#*mode == 0, iclass 19, count 2 2006.257.12:05:34.11#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.12:05:34.11#ibcon#[25=AT01-08\r\n] 2006.257.12:05:34.11#ibcon#*before write, iclass 19, count 2 2006.257.12:05:34.11#ibcon#enter sib2, iclass 19, count 2 2006.257.12:05:34.11#ibcon#flushed, iclass 19, count 2 2006.257.12:05:34.11#ibcon#about to write, iclass 19, count 2 2006.257.12:05:34.11#ibcon#wrote, iclass 19, count 2 2006.257.12:05:34.11#ibcon#about to read 3, iclass 19, count 2 2006.257.12:05:34.14#ibcon#read 3, iclass 19, count 2 2006.257.12:05:34.14#ibcon#about to read 4, iclass 19, count 2 2006.257.12:05:34.14#ibcon#read 4, iclass 19, count 2 2006.257.12:05:34.14#ibcon#about to read 5, iclass 19, count 2 2006.257.12:05:34.14#ibcon#read 5, iclass 19, count 2 2006.257.12:05:34.14#ibcon#about to read 6, iclass 19, count 2 2006.257.12:05:34.14#ibcon#read 6, iclass 19, count 2 2006.257.12:05:34.14#ibcon#end of sib2, iclass 19, count 2 2006.257.12:05:34.14#ibcon#*after write, iclass 19, count 2 2006.257.12:05:34.14#ibcon#*before return 0, iclass 19, count 2 2006.257.12:05:34.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:34.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:34.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.12:05:34.14#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:34.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:34.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:34.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:34.26#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:05:34.26#ibcon#first serial, iclass 19, count 0 2006.257.12:05:34.26#ibcon#enter sib2, iclass 19, count 0 2006.257.12:05:34.26#ibcon#flushed, iclass 19, count 0 2006.257.12:05:34.26#ibcon#about to write, iclass 19, count 0 2006.257.12:05:34.26#ibcon#wrote, iclass 19, count 0 2006.257.12:05:34.26#ibcon#about to read 3, iclass 19, count 0 2006.257.12:05:34.28#ibcon#read 3, iclass 19, count 0 2006.257.12:05:34.28#ibcon#about to read 4, iclass 19, count 0 2006.257.12:05:34.28#ibcon#read 4, iclass 19, count 0 2006.257.12:05:34.28#ibcon#about to read 5, iclass 19, count 0 2006.257.12:05:34.28#ibcon#read 5, iclass 19, count 0 2006.257.12:05:34.28#ibcon#about to read 6, iclass 19, count 0 2006.257.12:05:34.28#ibcon#read 6, iclass 19, count 0 2006.257.12:05:34.28#ibcon#end of sib2, iclass 19, count 0 2006.257.12:05:34.28#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:05:34.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:05:34.28#ibcon#[25=USB\r\n] 2006.257.12:05:34.28#ibcon#*before write, iclass 19, count 0 2006.257.12:05:34.28#ibcon#enter sib2, iclass 19, count 0 2006.257.12:05:34.28#ibcon#flushed, iclass 19, count 0 2006.257.12:05:34.28#ibcon#about to write, iclass 19, count 0 2006.257.12:05:34.28#ibcon#wrote, iclass 19, count 0 2006.257.12:05:34.28#ibcon#about to read 3, iclass 19, count 0 2006.257.12:05:34.31#ibcon#read 3, iclass 19, count 0 2006.257.12:05:34.31#ibcon#about to read 4, iclass 19, count 0 2006.257.12:05:34.31#ibcon#read 4, iclass 19, count 0 2006.257.12:05:34.31#ibcon#about to read 5, iclass 19, count 0 2006.257.12:05:34.31#ibcon#read 5, iclass 19, count 0 2006.257.12:05:34.31#ibcon#about to read 6, iclass 19, count 0 2006.257.12:05:34.31#ibcon#read 6, iclass 19, count 0 2006.257.12:05:34.31#ibcon#end of sib2, iclass 19, count 0 2006.257.12:05:34.31#ibcon#*after write, iclass 19, count 0 2006.257.12:05:34.31#ibcon#*before return 0, iclass 19, count 0 2006.257.12:05:34.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:34.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:34.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:05:34.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:05:34.31$vck44/valo=2,534.99 2006.257.12:05:34.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.12:05:34.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.12:05:34.31#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:34.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:05:34.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:05:34.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:05:34.31#ibcon#enter wrdev, iclass 21, count 0 2006.257.12:05:34.31#ibcon#first serial, iclass 21, count 0 2006.257.12:05:34.31#ibcon#enter sib2, iclass 21, count 0 2006.257.12:05:34.31#ibcon#flushed, iclass 21, count 0 2006.257.12:05:34.31#ibcon#about to write, iclass 21, count 0 2006.257.12:05:34.31#ibcon#wrote, iclass 21, count 0 2006.257.12:05:34.31#ibcon#about to read 3, iclass 21, count 0 2006.257.12:05:34.33#ibcon#read 3, iclass 21, count 0 2006.257.12:05:34.33#ibcon#about to read 4, iclass 21, count 0 2006.257.12:05:34.33#ibcon#read 4, iclass 21, count 0 2006.257.12:05:34.33#ibcon#about to read 5, iclass 21, count 0 2006.257.12:05:34.33#ibcon#read 5, iclass 21, count 0 2006.257.12:05:34.33#ibcon#about to read 6, iclass 21, count 0 2006.257.12:05:34.33#ibcon#read 6, iclass 21, count 0 2006.257.12:05:34.33#ibcon#end of sib2, iclass 21, count 0 2006.257.12:05:34.33#ibcon#*mode == 0, iclass 21, count 0 2006.257.12:05:34.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.12:05:34.33#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:05:34.33#ibcon#*before write, iclass 21, count 0 2006.257.12:05:34.33#ibcon#enter sib2, iclass 21, count 0 2006.257.12:05:34.33#ibcon#flushed, iclass 21, count 0 2006.257.12:05:34.33#ibcon#about to write, iclass 21, count 0 2006.257.12:05:34.33#ibcon#wrote, iclass 21, count 0 2006.257.12:05:34.33#ibcon#about to read 3, iclass 21, count 0 2006.257.12:05:34.37#ibcon#read 3, iclass 21, count 0 2006.257.12:05:34.37#ibcon#about to read 4, iclass 21, count 0 2006.257.12:05:34.37#ibcon#read 4, iclass 21, count 0 2006.257.12:05:34.37#ibcon#about to read 5, iclass 21, count 0 2006.257.12:05:34.37#ibcon#read 5, iclass 21, count 0 2006.257.12:05:34.37#ibcon#about to read 6, iclass 21, count 0 2006.257.12:05:34.37#ibcon#read 6, iclass 21, count 0 2006.257.12:05:34.37#ibcon#end of sib2, iclass 21, count 0 2006.257.12:05:34.37#ibcon#*after write, iclass 21, count 0 2006.257.12:05:34.37#ibcon#*before return 0, iclass 21, count 0 2006.257.12:05:34.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:05:34.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:05:34.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.12:05:34.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.12:05:34.37$vck44/va=2,7 2006.257.12:05:34.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.12:05:34.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.12:05:34.37#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:34.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:05:34.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:05:34.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:05:34.43#ibcon#enter wrdev, iclass 23, count 2 2006.257.12:05:34.43#ibcon#first serial, iclass 23, count 2 2006.257.12:05:34.43#ibcon#enter sib2, iclass 23, count 2 2006.257.12:05:34.43#ibcon#flushed, iclass 23, count 2 2006.257.12:05:34.43#ibcon#about to write, iclass 23, count 2 2006.257.12:05:34.43#ibcon#wrote, iclass 23, count 2 2006.257.12:05:34.43#ibcon#about to read 3, iclass 23, count 2 2006.257.12:05:34.45#ibcon#read 3, iclass 23, count 2 2006.257.12:05:34.45#ibcon#about to read 4, iclass 23, count 2 2006.257.12:05:34.45#ibcon#read 4, iclass 23, count 2 2006.257.12:05:34.45#ibcon#about to read 5, iclass 23, count 2 2006.257.12:05:34.45#ibcon#read 5, iclass 23, count 2 2006.257.12:05:34.45#ibcon#about to read 6, iclass 23, count 2 2006.257.12:05:34.45#ibcon#read 6, iclass 23, count 2 2006.257.12:05:34.45#ibcon#end of sib2, iclass 23, count 2 2006.257.12:05:34.45#ibcon#*mode == 0, iclass 23, count 2 2006.257.12:05:34.45#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.12:05:34.45#ibcon#[25=AT02-07\r\n] 2006.257.12:05:34.45#ibcon#*before write, iclass 23, count 2 2006.257.12:05:34.45#ibcon#enter sib2, iclass 23, count 2 2006.257.12:05:34.45#ibcon#flushed, iclass 23, count 2 2006.257.12:05:34.45#ibcon#about to write, iclass 23, count 2 2006.257.12:05:34.45#ibcon#wrote, iclass 23, count 2 2006.257.12:05:34.45#ibcon#about to read 3, iclass 23, count 2 2006.257.12:05:34.48#ibcon#read 3, iclass 23, count 2 2006.257.12:05:34.48#ibcon#about to read 4, iclass 23, count 2 2006.257.12:05:34.48#ibcon#read 4, iclass 23, count 2 2006.257.12:05:34.48#ibcon#about to read 5, iclass 23, count 2 2006.257.12:05:34.48#ibcon#read 5, iclass 23, count 2 2006.257.12:05:34.48#ibcon#about to read 6, iclass 23, count 2 2006.257.12:05:34.48#ibcon#read 6, iclass 23, count 2 2006.257.12:05:34.48#ibcon#end of sib2, iclass 23, count 2 2006.257.12:05:34.48#ibcon#*after write, iclass 23, count 2 2006.257.12:05:34.48#ibcon#*before return 0, iclass 23, count 2 2006.257.12:05:34.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:05:34.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:05:34.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.12:05:34.48#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:34.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:05:34.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:05:34.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:05:34.60#ibcon#enter wrdev, iclass 23, count 0 2006.257.12:05:34.60#ibcon#first serial, iclass 23, count 0 2006.257.12:05:34.60#ibcon#enter sib2, iclass 23, count 0 2006.257.12:05:34.60#ibcon#flushed, iclass 23, count 0 2006.257.12:05:34.60#ibcon#about to write, iclass 23, count 0 2006.257.12:05:34.60#ibcon#wrote, iclass 23, count 0 2006.257.12:05:34.60#ibcon#about to read 3, iclass 23, count 0 2006.257.12:05:34.62#ibcon#read 3, iclass 23, count 0 2006.257.12:05:34.62#ibcon#about to read 4, iclass 23, count 0 2006.257.12:05:34.62#ibcon#read 4, iclass 23, count 0 2006.257.12:05:34.62#ibcon#about to read 5, iclass 23, count 0 2006.257.12:05:34.62#ibcon#read 5, iclass 23, count 0 2006.257.12:05:34.62#ibcon#about to read 6, iclass 23, count 0 2006.257.12:05:34.62#ibcon#read 6, iclass 23, count 0 2006.257.12:05:34.62#ibcon#end of sib2, iclass 23, count 0 2006.257.12:05:34.62#ibcon#*mode == 0, iclass 23, count 0 2006.257.12:05:34.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.12:05:34.62#ibcon#[25=USB\r\n] 2006.257.12:05:34.62#ibcon#*before write, iclass 23, count 0 2006.257.12:05:34.62#ibcon#enter sib2, iclass 23, count 0 2006.257.12:05:34.62#ibcon#flushed, iclass 23, count 0 2006.257.12:05:34.62#ibcon#about to write, iclass 23, count 0 2006.257.12:05:34.62#ibcon#wrote, iclass 23, count 0 2006.257.12:05:34.62#ibcon#about to read 3, iclass 23, count 0 2006.257.12:05:34.65#ibcon#read 3, iclass 23, count 0 2006.257.12:05:34.65#ibcon#about to read 4, iclass 23, count 0 2006.257.12:05:34.65#ibcon#read 4, iclass 23, count 0 2006.257.12:05:34.65#ibcon#about to read 5, iclass 23, count 0 2006.257.12:05:34.65#ibcon#read 5, iclass 23, count 0 2006.257.12:05:34.65#ibcon#about to read 6, iclass 23, count 0 2006.257.12:05:34.65#ibcon#read 6, iclass 23, count 0 2006.257.12:05:34.65#ibcon#end of sib2, iclass 23, count 0 2006.257.12:05:34.65#ibcon#*after write, iclass 23, count 0 2006.257.12:05:34.65#ibcon#*before return 0, iclass 23, count 0 2006.257.12:05:34.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:05:34.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:05:34.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.12:05:34.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.12:05:34.65$vck44/valo=3,564.99 2006.257.12:05:34.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.12:05:34.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.12:05:34.65#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:34.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:34.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:34.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:34.65#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:05:34.65#ibcon#first serial, iclass 25, count 0 2006.257.12:05:34.65#ibcon#enter sib2, iclass 25, count 0 2006.257.12:05:34.65#ibcon#flushed, iclass 25, count 0 2006.257.12:05:34.65#ibcon#about to write, iclass 25, count 0 2006.257.12:05:34.65#ibcon#wrote, iclass 25, count 0 2006.257.12:05:34.65#ibcon#about to read 3, iclass 25, count 0 2006.257.12:05:34.67#ibcon#read 3, iclass 25, count 0 2006.257.12:05:34.67#ibcon#about to read 4, iclass 25, count 0 2006.257.12:05:34.67#ibcon#read 4, iclass 25, count 0 2006.257.12:05:34.67#ibcon#about to read 5, iclass 25, count 0 2006.257.12:05:34.67#ibcon#read 5, iclass 25, count 0 2006.257.12:05:34.67#ibcon#about to read 6, iclass 25, count 0 2006.257.12:05:34.67#ibcon#read 6, iclass 25, count 0 2006.257.12:05:34.67#ibcon#end of sib2, iclass 25, count 0 2006.257.12:05:34.67#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:05:34.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:05:34.67#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:05:34.67#ibcon#*before write, iclass 25, count 0 2006.257.12:05:34.67#ibcon#enter sib2, iclass 25, count 0 2006.257.12:05:34.67#ibcon#flushed, iclass 25, count 0 2006.257.12:05:34.67#ibcon#about to write, iclass 25, count 0 2006.257.12:05:34.67#ibcon#wrote, iclass 25, count 0 2006.257.12:05:34.67#ibcon#about to read 3, iclass 25, count 0 2006.257.12:05:34.71#ibcon#read 3, iclass 25, count 0 2006.257.12:05:34.71#ibcon#about to read 4, iclass 25, count 0 2006.257.12:05:34.71#ibcon#read 4, iclass 25, count 0 2006.257.12:05:34.71#ibcon#about to read 5, iclass 25, count 0 2006.257.12:05:34.71#ibcon#read 5, iclass 25, count 0 2006.257.12:05:34.71#ibcon#about to read 6, iclass 25, count 0 2006.257.12:05:34.71#ibcon#read 6, iclass 25, count 0 2006.257.12:05:34.71#ibcon#end of sib2, iclass 25, count 0 2006.257.12:05:34.71#ibcon#*after write, iclass 25, count 0 2006.257.12:05:34.71#ibcon#*before return 0, iclass 25, count 0 2006.257.12:05:34.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:34.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:34.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:05:34.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:05:34.71$vck44/va=3,8 2006.257.12:05:34.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.12:05:34.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.12:05:34.71#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:34.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:34.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:34.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:34.77#ibcon#enter wrdev, iclass 27, count 2 2006.257.12:05:34.77#ibcon#first serial, iclass 27, count 2 2006.257.12:05:34.77#ibcon#enter sib2, iclass 27, count 2 2006.257.12:05:34.77#ibcon#flushed, iclass 27, count 2 2006.257.12:05:34.77#ibcon#about to write, iclass 27, count 2 2006.257.12:05:34.77#ibcon#wrote, iclass 27, count 2 2006.257.12:05:34.77#ibcon#about to read 3, iclass 27, count 2 2006.257.12:05:34.79#ibcon#read 3, iclass 27, count 2 2006.257.12:05:34.79#ibcon#about to read 4, iclass 27, count 2 2006.257.12:05:34.79#ibcon#read 4, iclass 27, count 2 2006.257.12:05:34.79#ibcon#about to read 5, iclass 27, count 2 2006.257.12:05:34.79#ibcon#read 5, iclass 27, count 2 2006.257.12:05:34.79#ibcon#about to read 6, iclass 27, count 2 2006.257.12:05:34.79#ibcon#read 6, iclass 27, count 2 2006.257.12:05:34.79#ibcon#end of sib2, iclass 27, count 2 2006.257.12:05:34.79#ibcon#*mode == 0, iclass 27, count 2 2006.257.12:05:34.79#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.12:05:34.79#ibcon#[25=AT03-08\r\n] 2006.257.12:05:34.79#ibcon#*before write, iclass 27, count 2 2006.257.12:05:34.79#ibcon#enter sib2, iclass 27, count 2 2006.257.12:05:34.79#ibcon#flushed, iclass 27, count 2 2006.257.12:05:34.79#ibcon#about to write, iclass 27, count 2 2006.257.12:05:34.79#ibcon#wrote, iclass 27, count 2 2006.257.12:05:34.79#ibcon#about to read 3, iclass 27, count 2 2006.257.12:05:34.82#ibcon#read 3, iclass 27, count 2 2006.257.12:05:34.82#ibcon#about to read 4, iclass 27, count 2 2006.257.12:05:34.82#ibcon#read 4, iclass 27, count 2 2006.257.12:05:34.82#ibcon#about to read 5, iclass 27, count 2 2006.257.12:05:34.82#ibcon#read 5, iclass 27, count 2 2006.257.12:05:34.82#ibcon#about to read 6, iclass 27, count 2 2006.257.12:05:34.82#ibcon#read 6, iclass 27, count 2 2006.257.12:05:34.82#ibcon#end of sib2, iclass 27, count 2 2006.257.12:05:34.82#ibcon#*after write, iclass 27, count 2 2006.257.12:05:34.82#ibcon#*before return 0, iclass 27, count 2 2006.257.12:05:34.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:34.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:34.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.12:05:34.82#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:34.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:34.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:34.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:34.94#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:05:34.94#ibcon#first serial, iclass 27, count 0 2006.257.12:05:34.94#ibcon#enter sib2, iclass 27, count 0 2006.257.12:05:34.94#ibcon#flushed, iclass 27, count 0 2006.257.12:05:34.94#ibcon#about to write, iclass 27, count 0 2006.257.12:05:34.94#ibcon#wrote, iclass 27, count 0 2006.257.12:05:34.94#ibcon#about to read 3, iclass 27, count 0 2006.257.12:05:34.96#ibcon#read 3, iclass 27, count 0 2006.257.12:05:34.96#ibcon#about to read 4, iclass 27, count 0 2006.257.12:05:34.96#ibcon#read 4, iclass 27, count 0 2006.257.12:05:34.96#ibcon#about to read 5, iclass 27, count 0 2006.257.12:05:34.96#ibcon#read 5, iclass 27, count 0 2006.257.12:05:34.96#ibcon#about to read 6, iclass 27, count 0 2006.257.12:05:34.96#ibcon#read 6, iclass 27, count 0 2006.257.12:05:34.96#ibcon#end of sib2, iclass 27, count 0 2006.257.12:05:34.96#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:05:34.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:05:34.96#ibcon#[25=USB\r\n] 2006.257.12:05:34.96#ibcon#*before write, iclass 27, count 0 2006.257.12:05:34.96#ibcon#enter sib2, iclass 27, count 0 2006.257.12:05:34.96#ibcon#flushed, iclass 27, count 0 2006.257.12:05:34.96#ibcon#about to write, iclass 27, count 0 2006.257.12:05:34.96#ibcon#wrote, iclass 27, count 0 2006.257.12:05:34.96#ibcon#about to read 3, iclass 27, count 0 2006.257.12:05:34.99#ibcon#read 3, iclass 27, count 0 2006.257.12:05:34.99#ibcon#about to read 4, iclass 27, count 0 2006.257.12:05:34.99#ibcon#read 4, iclass 27, count 0 2006.257.12:05:34.99#ibcon#about to read 5, iclass 27, count 0 2006.257.12:05:34.99#ibcon#read 5, iclass 27, count 0 2006.257.12:05:34.99#ibcon#about to read 6, iclass 27, count 0 2006.257.12:05:34.99#ibcon#read 6, iclass 27, count 0 2006.257.12:05:34.99#ibcon#end of sib2, iclass 27, count 0 2006.257.12:05:34.99#ibcon#*after write, iclass 27, count 0 2006.257.12:05:34.99#ibcon#*before return 0, iclass 27, count 0 2006.257.12:05:34.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:34.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:34.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:05:34.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:05:34.99$vck44/valo=4,624.99 2006.257.12:05:34.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.12:05:34.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.12:05:34.99#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:34.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:34.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:34.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:34.99#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:05:34.99#ibcon#first serial, iclass 29, count 0 2006.257.12:05:34.99#ibcon#enter sib2, iclass 29, count 0 2006.257.12:05:34.99#ibcon#flushed, iclass 29, count 0 2006.257.12:05:34.99#ibcon#about to write, iclass 29, count 0 2006.257.12:05:34.99#ibcon#wrote, iclass 29, count 0 2006.257.12:05:34.99#ibcon#about to read 3, iclass 29, count 0 2006.257.12:05:35.01#ibcon#read 3, iclass 29, count 0 2006.257.12:05:35.01#ibcon#about to read 4, iclass 29, count 0 2006.257.12:05:35.01#ibcon#read 4, iclass 29, count 0 2006.257.12:05:35.01#ibcon#about to read 5, iclass 29, count 0 2006.257.12:05:35.01#ibcon#read 5, iclass 29, count 0 2006.257.12:05:35.01#ibcon#about to read 6, iclass 29, count 0 2006.257.12:05:35.01#ibcon#read 6, iclass 29, count 0 2006.257.12:05:35.01#ibcon#end of sib2, iclass 29, count 0 2006.257.12:05:35.01#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:05:35.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:05:35.01#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:05:35.01#ibcon#*before write, iclass 29, count 0 2006.257.12:05:35.01#ibcon#enter sib2, iclass 29, count 0 2006.257.12:05:35.01#ibcon#flushed, iclass 29, count 0 2006.257.12:05:35.01#ibcon#about to write, iclass 29, count 0 2006.257.12:05:35.01#ibcon#wrote, iclass 29, count 0 2006.257.12:05:35.01#ibcon#about to read 3, iclass 29, count 0 2006.257.12:05:35.05#ibcon#read 3, iclass 29, count 0 2006.257.12:05:35.05#ibcon#about to read 4, iclass 29, count 0 2006.257.12:05:35.05#ibcon#read 4, iclass 29, count 0 2006.257.12:05:35.05#ibcon#about to read 5, iclass 29, count 0 2006.257.12:05:35.05#ibcon#read 5, iclass 29, count 0 2006.257.12:05:35.05#ibcon#about to read 6, iclass 29, count 0 2006.257.12:05:35.05#ibcon#read 6, iclass 29, count 0 2006.257.12:05:35.05#ibcon#end of sib2, iclass 29, count 0 2006.257.12:05:35.05#ibcon#*after write, iclass 29, count 0 2006.257.12:05:35.05#ibcon#*before return 0, iclass 29, count 0 2006.257.12:05:35.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:35.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:35.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:05:35.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:05:35.05$vck44/va=4,7 2006.257.12:05:35.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.12:05:35.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.12:05:35.05#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:35.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:35.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:35.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:35.11#ibcon#enter wrdev, iclass 31, count 2 2006.257.12:05:35.11#ibcon#first serial, iclass 31, count 2 2006.257.12:05:35.11#ibcon#enter sib2, iclass 31, count 2 2006.257.12:05:35.11#ibcon#flushed, iclass 31, count 2 2006.257.12:05:35.11#ibcon#about to write, iclass 31, count 2 2006.257.12:05:35.11#ibcon#wrote, iclass 31, count 2 2006.257.12:05:35.11#ibcon#about to read 3, iclass 31, count 2 2006.257.12:05:35.13#ibcon#read 3, iclass 31, count 2 2006.257.12:05:35.13#ibcon#about to read 4, iclass 31, count 2 2006.257.12:05:35.13#ibcon#read 4, iclass 31, count 2 2006.257.12:05:35.13#ibcon#about to read 5, iclass 31, count 2 2006.257.12:05:35.13#ibcon#read 5, iclass 31, count 2 2006.257.12:05:35.13#ibcon#about to read 6, iclass 31, count 2 2006.257.12:05:35.13#ibcon#read 6, iclass 31, count 2 2006.257.12:05:35.13#ibcon#end of sib2, iclass 31, count 2 2006.257.12:05:35.13#ibcon#*mode == 0, iclass 31, count 2 2006.257.12:05:35.13#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.12:05:35.13#ibcon#[25=AT04-07\r\n] 2006.257.12:05:35.13#ibcon#*before write, iclass 31, count 2 2006.257.12:05:35.13#ibcon#enter sib2, iclass 31, count 2 2006.257.12:05:35.13#ibcon#flushed, iclass 31, count 2 2006.257.12:05:35.13#ibcon#about to write, iclass 31, count 2 2006.257.12:05:35.13#ibcon#wrote, iclass 31, count 2 2006.257.12:05:35.13#ibcon#about to read 3, iclass 31, count 2 2006.257.12:05:35.16#ibcon#read 3, iclass 31, count 2 2006.257.12:05:35.16#ibcon#about to read 4, iclass 31, count 2 2006.257.12:05:35.16#ibcon#read 4, iclass 31, count 2 2006.257.12:05:35.16#ibcon#about to read 5, iclass 31, count 2 2006.257.12:05:35.16#ibcon#read 5, iclass 31, count 2 2006.257.12:05:35.16#ibcon#about to read 6, iclass 31, count 2 2006.257.12:05:35.16#ibcon#read 6, iclass 31, count 2 2006.257.12:05:35.16#ibcon#end of sib2, iclass 31, count 2 2006.257.12:05:35.16#ibcon#*after write, iclass 31, count 2 2006.257.12:05:35.16#ibcon#*before return 0, iclass 31, count 2 2006.257.12:05:35.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:35.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:35.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.12:05:35.16#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:35.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:35.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:35.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:35.28#ibcon#enter wrdev, iclass 31, count 0 2006.257.12:05:35.28#ibcon#first serial, iclass 31, count 0 2006.257.12:05:35.28#ibcon#enter sib2, iclass 31, count 0 2006.257.12:05:35.28#ibcon#flushed, iclass 31, count 0 2006.257.12:05:35.28#ibcon#about to write, iclass 31, count 0 2006.257.12:05:35.28#ibcon#wrote, iclass 31, count 0 2006.257.12:05:35.28#ibcon#about to read 3, iclass 31, count 0 2006.257.12:05:35.30#ibcon#read 3, iclass 31, count 0 2006.257.12:05:35.30#ibcon#about to read 4, iclass 31, count 0 2006.257.12:05:35.30#ibcon#read 4, iclass 31, count 0 2006.257.12:05:35.30#ibcon#about to read 5, iclass 31, count 0 2006.257.12:05:35.30#ibcon#read 5, iclass 31, count 0 2006.257.12:05:35.30#ibcon#about to read 6, iclass 31, count 0 2006.257.12:05:35.30#ibcon#read 6, iclass 31, count 0 2006.257.12:05:35.30#ibcon#end of sib2, iclass 31, count 0 2006.257.12:05:35.30#ibcon#*mode == 0, iclass 31, count 0 2006.257.12:05:35.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.12:05:35.30#ibcon#[25=USB\r\n] 2006.257.12:05:35.30#ibcon#*before write, iclass 31, count 0 2006.257.12:05:35.30#ibcon#enter sib2, iclass 31, count 0 2006.257.12:05:35.30#ibcon#flushed, iclass 31, count 0 2006.257.12:05:35.30#ibcon#about to write, iclass 31, count 0 2006.257.12:05:35.30#ibcon#wrote, iclass 31, count 0 2006.257.12:05:35.30#ibcon#about to read 3, iclass 31, count 0 2006.257.12:05:35.33#ibcon#read 3, iclass 31, count 0 2006.257.12:05:35.33#ibcon#about to read 4, iclass 31, count 0 2006.257.12:05:35.33#ibcon#read 4, iclass 31, count 0 2006.257.12:05:35.33#ibcon#about to read 5, iclass 31, count 0 2006.257.12:05:35.33#ibcon#read 5, iclass 31, count 0 2006.257.12:05:35.33#ibcon#about to read 6, iclass 31, count 0 2006.257.12:05:35.33#ibcon#read 6, iclass 31, count 0 2006.257.12:05:35.33#ibcon#end of sib2, iclass 31, count 0 2006.257.12:05:35.33#ibcon#*after write, iclass 31, count 0 2006.257.12:05:35.33#ibcon#*before return 0, iclass 31, count 0 2006.257.12:05:35.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:35.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:35.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.12:05:35.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.12:05:35.33$vck44/valo=5,734.99 2006.257.12:05:35.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.12:05:35.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.12:05:35.33#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:35.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:35.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:35.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:35.33#ibcon#enter wrdev, iclass 33, count 0 2006.257.12:05:35.33#ibcon#first serial, iclass 33, count 0 2006.257.12:05:35.33#ibcon#enter sib2, iclass 33, count 0 2006.257.12:05:35.33#ibcon#flushed, iclass 33, count 0 2006.257.12:05:35.33#ibcon#about to write, iclass 33, count 0 2006.257.12:05:35.33#ibcon#wrote, iclass 33, count 0 2006.257.12:05:35.33#ibcon#about to read 3, iclass 33, count 0 2006.257.12:05:35.35#ibcon#read 3, iclass 33, count 0 2006.257.12:05:35.35#ibcon#about to read 4, iclass 33, count 0 2006.257.12:05:35.35#ibcon#read 4, iclass 33, count 0 2006.257.12:05:35.35#ibcon#about to read 5, iclass 33, count 0 2006.257.12:05:35.35#ibcon#read 5, iclass 33, count 0 2006.257.12:05:35.35#ibcon#about to read 6, iclass 33, count 0 2006.257.12:05:35.35#ibcon#read 6, iclass 33, count 0 2006.257.12:05:35.35#ibcon#end of sib2, iclass 33, count 0 2006.257.12:05:35.35#ibcon#*mode == 0, iclass 33, count 0 2006.257.12:05:35.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.12:05:35.35#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:05:35.35#ibcon#*before write, iclass 33, count 0 2006.257.12:05:35.35#ibcon#enter sib2, iclass 33, count 0 2006.257.12:05:35.35#ibcon#flushed, iclass 33, count 0 2006.257.12:05:35.35#ibcon#about to write, iclass 33, count 0 2006.257.12:05:35.35#ibcon#wrote, iclass 33, count 0 2006.257.12:05:35.35#ibcon#about to read 3, iclass 33, count 0 2006.257.12:05:35.39#ibcon#read 3, iclass 33, count 0 2006.257.12:05:35.39#ibcon#about to read 4, iclass 33, count 0 2006.257.12:05:35.39#ibcon#read 4, iclass 33, count 0 2006.257.12:05:35.39#ibcon#about to read 5, iclass 33, count 0 2006.257.12:05:35.39#ibcon#read 5, iclass 33, count 0 2006.257.12:05:35.39#ibcon#about to read 6, iclass 33, count 0 2006.257.12:05:35.39#ibcon#read 6, iclass 33, count 0 2006.257.12:05:35.39#ibcon#end of sib2, iclass 33, count 0 2006.257.12:05:35.39#ibcon#*after write, iclass 33, count 0 2006.257.12:05:35.39#ibcon#*before return 0, iclass 33, count 0 2006.257.12:05:35.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:35.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:35.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.12:05:35.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.12:05:35.39$vck44/va=5,4 2006.257.12:05:35.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.12:05:35.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.12:05:35.39#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:35.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:35.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:35.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:35.45#ibcon#enter wrdev, iclass 35, count 2 2006.257.12:05:35.45#ibcon#first serial, iclass 35, count 2 2006.257.12:05:35.45#ibcon#enter sib2, iclass 35, count 2 2006.257.12:05:35.45#ibcon#flushed, iclass 35, count 2 2006.257.12:05:35.45#ibcon#about to write, iclass 35, count 2 2006.257.12:05:35.45#ibcon#wrote, iclass 35, count 2 2006.257.12:05:35.45#ibcon#about to read 3, iclass 35, count 2 2006.257.12:05:35.47#ibcon#read 3, iclass 35, count 2 2006.257.12:05:35.47#ibcon#about to read 4, iclass 35, count 2 2006.257.12:05:35.47#ibcon#read 4, iclass 35, count 2 2006.257.12:05:35.47#ibcon#about to read 5, iclass 35, count 2 2006.257.12:05:35.47#ibcon#read 5, iclass 35, count 2 2006.257.12:05:35.47#ibcon#about to read 6, iclass 35, count 2 2006.257.12:05:35.47#ibcon#read 6, iclass 35, count 2 2006.257.12:05:35.47#ibcon#end of sib2, iclass 35, count 2 2006.257.12:05:35.47#ibcon#*mode == 0, iclass 35, count 2 2006.257.12:05:35.47#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.12:05:35.47#ibcon#[25=AT05-04\r\n] 2006.257.12:05:35.47#ibcon#*before write, iclass 35, count 2 2006.257.12:05:35.47#ibcon#enter sib2, iclass 35, count 2 2006.257.12:05:35.47#ibcon#flushed, iclass 35, count 2 2006.257.12:05:35.47#ibcon#about to write, iclass 35, count 2 2006.257.12:05:35.47#ibcon#wrote, iclass 35, count 2 2006.257.12:05:35.47#ibcon#about to read 3, iclass 35, count 2 2006.257.12:05:35.50#ibcon#read 3, iclass 35, count 2 2006.257.12:05:35.50#ibcon#about to read 4, iclass 35, count 2 2006.257.12:05:35.50#ibcon#read 4, iclass 35, count 2 2006.257.12:05:35.50#ibcon#about to read 5, iclass 35, count 2 2006.257.12:05:35.50#ibcon#read 5, iclass 35, count 2 2006.257.12:05:35.50#ibcon#about to read 6, iclass 35, count 2 2006.257.12:05:35.50#ibcon#read 6, iclass 35, count 2 2006.257.12:05:35.50#ibcon#end of sib2, iclass 35, count 2 2006.257.12:05:35.50#ibcon#*after write, iclass 35, count 2 2006.257.12:05:35.50#ibcon#*before return 0, iclass 35, count 2 2006.257.12:05:35.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:35.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:35.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.12:05:35.50#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:35.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:35.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:35.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:35.62#ibcon#enter wrdev, iclass 35, count 0 2006.257.12:05:35.62#ibcon#first serial, iclass 35, count 0 2006.257.12:05:35.62#ibcon#enter sib2, iclass 35, count 0 2006.257.12:05:35.62#ibcon#flushed, iclass 35, count 0 2006.257.12:05:35.62#ibcon#about to write, iclass 35, count 0 2006.257.12:05:35.62#ibcon#wrote, iclass 35, count 0 2006.257.12:05:35.62#ibcon#about to read 3, iclass 35, count 0 2006.257.12:05:35.64#ibcon#read 3, iclass 35, count 0 2006.257.12:05:35.64#ibcon#about to read 4, iclass 35, count 0 2006.257.12:05:35.64#ibcon#read 4, iclass 35, count 0 2006.257.12:05:35.64#ibcon#about to read 5, iclass 35, count 0 2006.257.12:05:35.64#ibcon#read 5, iclass 35, count 0 2006.257.12:05:35.64#ibcon#about to read 6, iclass 35, count 0 2006.257.12:05:35.64#ibcon#read 6, iclass 35, count 0 2006.257.12:05:35.64#ibcon#end of sib2, iclass 35, count 0 2006.257.12:05:35.64#ibcon#*mode == 0, iclass 35, count 0 2006.257.12:05:35.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.12:05:35.64#ibcon#[25=USB\r\n] 2006.257.12:05:35.64#ibcon#*before write, iclass 35, count 0 2006.257.12:05:35.64#ibcon#enter sib2, iclass 35, count 0 2006.257.12:05:35.64#ibcon#flushed, iclass 35, count 0 2006.257.12:05:35.64#ibcon#about to write, iclass 35, count 0 2006.257.12:05:35.64#ibcon#wrote, iclass 35, count 0 2006.257.12:05:35.64#ibcon#about to read 3, iclass 35, count 0 2006.257.12:05:35.67#ibcon#read 3, iclass 35, count 0 2006.257.12:05:35.67#ibcon#about to read 4, iclass 35, count 0 2006.257.12:05:35.67#ibcon#read 4, iclass 35, count 0 2006.257.12:05:35.67#ibcon#about to read 5, iclass 35, count 0 2006.257.12:05:35.67#ibcon#read 5, iclass 35, count 0 2006.257.12:05:35.67#ibcon#about to read 6, iclass 35, count 0 2006.257.12:05:35.67#ibcon#read 6, iclass 35, count 0 2006.257.12:05:35.67#ibcon#end of sib2, iclass 35, count 0 2006.257.12:05:35.67#ibcon#*after write, iclass 35, count 0 2006.257.12:05:35.67#ibcon#*before return 0, iclass 35, count 0 2006.257.12:05:35.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:35.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:35.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.12:05:35.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.12:05:35.67$vck44/valo=6,814.99 2006.257.12:05:35.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.12:05:35.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.12:05:35.67#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:35.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:35.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:35.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:35.67#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:05:35.67#ibcon#first serial, iclass 37, count 0 2006.257.12:05:35.67#ibcon#enter sib2, iclass 37, count 0 2006.257.12:05:35.67#ibcon#flushed, iclass 37, count 0 2006.257.12:05:35.67#ibcon#about to write, iclass 37, count 0 2006.257.12:05:35.67#ibcon#wrote, iclass 37, count 0 2006.257.12:05:35.67#ibcon#about to read 3, iclass 37, count 0 2006.257.12:05:35.69#ibcon#read 3, iclass 37, count 0 2006.257.12:05:35.69#ibcon#about to read 4, iclass 37, count 0 2006.257.12:05:35.69#ibcon#read 4, iclass 37, count 0 2006.257.12:05:35.69#ibcon#about to read 5, iclass 37, count 0 2006.257.12:05:35.69#ibcon#read 5, iclass 37, count 0 2006.257.12:05:35.69#ibcon#about to read 6, iclass 37, count 0 2006.257.12:05:35.69#ibcon#read 6, iclass 37, count 0 2006.257.12:05:35.69#ibcon#end of sib2, iclass 37, count 0 2006.257.12:05:35.69#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:05:35.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:05:35.69#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:05:35.69#ibcon#*before write, iclass 37, count 0 2006.257.12:05:35.69#ibcon#enter sib2, iclass 37, count 0 2006.257.12:05:35.69#ibcon#flushed, iclass 37, count 0 2006.257.12:05:35.69#ibcon#about to write, iclass 37, count 0 2006.257.12:05:35.69#ibcon#wrote, iclass 37, count 0 2006.257.12:05:35.69#ibcon#about to read 3, iclass 37, count 0 2006.257.12:05:35.73#ibcon#read 3, iclass 37, count 0 2006.257.12:05:35.73#ibcon#about to read 4, iclass 37, count 0 2006.257.12:05:35.73#ibcon#read 4, iclass 37, count 0 2006.257.12:05:35.73#ibcon#about to read 5, iclass 37, count 0 2006.257.12:05:35.73#ibcon#read 5, iclass 37, count 0 2006.257.12:05:35.73#ibcon#about to read 6, iclass 37, count 0 2006.257.12:05:35.73#ibcon#read 6, iclass 37, count 0 2006.257.12:05:35.73#ibcon#end of sib2, iclass 37, count 0 2006.257.12:05:35.73#ibcon#*after write, iclass 37, count 0 2006.257.12:05:35.73#ibcon#*before return 0, iclass 37, count 0 2006.257.12:05:35.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:35.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:35.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:05:35.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:05:35.73$vck44/va=6,4 2006.257.12:05:35.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.12:05:35.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.12:05:35.73#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:35.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:35.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:35.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:35.79#ibcon#enter wrdev, iclass 39, count 2 2006.257.12:05:35.79#ibcon#first serial, iclass 39, count 2 2006.257.12:05:35.79#ibcon#enter sib2, iclass 39, count 2 2006.257.12:05:35.79#ibcon#flushed, iclass 39, count 2 2006.257.12:05:35.79#ibcon#about to write, iclass 39, count 2 2006.257.12:05:35.79#ibcon#wrote, iclass 39, count 2 2006.257.12:05:35.79#ibcon#about to read 3, iclass 39, count 2 2006.257.12:05:35.81#ibcon#read 3, iclass 39, count 2 2006.257.12:05:35.81#ibcon#about to read 4, iclass 39, count 2 2006.257.12:05:35.81#ibcon#read 4, iclass 39, count 2 2006.257.12:05:35.81#ibcon#about to read 5, iclass 39, count 2 2006.257.12:05:35.81#ibcon#read 5, iclass 39, count 2 2006.257.12:05:35.81#ibcon#about to read 6, iclass 39, count 2 2006.257.12:05:35.81#ibcon#read 6, iclass 39, count 2 2006.257.12:05:35.81#ibcon#end of sib2, iclass 39, count 2 2006.257.12:05:35.81#ibcon#*mode == 0, iclass 39, count 2 2006.257.12:05:35.81#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.12:05:35.81#ibcon#[25=AT06-04\r\n] 2006.257.12:05:35.81#ibcon#*before write, iclass 39, count 2 2006.257.12:05:35.81#ibcon#enter sib2, iclass 39, count 2 2006.257.12:05:35.81#ibcon#flushed, iclass 39, count 2 2006.257.12:05:35.81#ibcon#about to write, iclass 39, count 2 2006.257.12:05:35.81#ibcon#wrote, iclass 39, count 2 2006.257.12:05:35.81#ibcon#about to read 3, iclass 39, count 2 2006.257.12:05:35.84#ibcon#read 3, iclass 39, count 2 2006.257.12:05:35.84#ibcon#about to read 4, iclass 39, count 2 2006.257.12:05:35.84#ibcon#read 4, iclass 39, count 2 2006.257.12:05:35.84#ibcon#about to read 5, iclass 39, count 2 2006.257.12:05:35.84#ibcon#read 5, iclass 39, count 2 2006.257.12:05:35.84#ibcon#about to read 6, iclass 39, count 2 2006.257.12:05:35.84#ibcon#read 6, iclass 39, count 2 2006.257.12:05:35.84#ibcon#end of sib2, iclass 39, count 2 2006.257.12:05:35.84#ibcon#*after write, iclass 39, count 2 2006.257.12:05:35.84#ibcon#*before return 0, iclass 39, count 2 2006.257.12:05:35.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:35.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:35.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.12:05:35.84#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:35.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:35.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:35.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:35.96#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:05:35.96#ibcon#first serial, iclass 39, count 0 2006.257.12:05:35.96#ibcon#enter sib2, iclass 39, count 0 2006.257.12:05:35.96#ibcon#flushed, iclass 39, count 0 2006.257.12:05:35.96#ibcon#about to write, iclass 39, count 0 2006.257.12:05:35.96#ibcon#wrote, iclass 39, count 0 2006.257.12:05:35.96#ibcon#about to read 3, iclass 39, count 0 2006.257.12:05:35.98#ibcon#read 3, iclass 39, count 0 2006.257.12:05:35.98#ibcon#about to read 4, iclass 39, count 0 2006.257.12:05:35.98#ibcon#read 4, iclass 39, count 0 2006.257.12:05:35.98#ibcon#about to read 5, iclass 39, count 0 2006.257.12:05:35.98#ibcon#read 5, iclass 39, count 0 2006.257.12:05:35.98#ibcon#about to read 6, iclass 39, count 0 2006.257.12:05:35.98#ibcon#read 6, iclass 39, count 0 2006.257.12:05:35.98#ibcon#end of sib2, iclass 39, count 0 2006.257.12:05:35.98#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:05:35.98#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:05:35.98#ibcon#[25=USB\r\n] 2006.257.12:05:35.98#ibcon#*before write, iclass 39, count 0 2006.257.12:05:35.98#ibcon#enter sib2, iclass 39, count 0 2006.257.12:05:35.98#ibcon#flushed, iclass 39, count 0 2006.257.12:05:35.98#ibcon#about to write, iclass 39, count 0 2006.257.12:05:35.98#ibcon#wrote, iclass 39, count 0 2006.257.12:05:35.98#ibcon#about to read 3, iclass 39, count 0 2006.257.12:05:36.01#ibcon#read 3, iclass 39, count 0 2006.257.12:05:36.01#ibcon#about to read 4, iclass 39, count 0 2006.257.12:05:36.01#ibcon#read 4, iclass 39, count 0 2006.257.12:05:36.01#ibcon#about to read 5, iclass 39, count 0 2006.257.12:05:36.01#ibcon#read 5, iclass 39, count 0 2006.257.12:05:36.01#ibcon#about to read 6, iclass 39, count 0 2006.257.12:05:36.01#ibcon#read 6, iclass 39, count 0 2006.257.12:05:36.01#ibcon#end of sib2, iclass 39, count 0 2006.257.12:05:36.01#ibcon#*after write, iclass 39, count 0 2006.257.12:05:36.01#ibcon#*before return 0, iclass 39, count 0 2006.257.12:05:36.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:36.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:36.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:05:36.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:05:36.01$vck44/valo=7,864.99 2006.257.12:05:36.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.12:05:36.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.12:05:36.01#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:36.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:36.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:36.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:36.01#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:05:36.01#ibcon#first serial, iclass 3, count 0 2006.257.12:05:36.01#ibcon#enter sib2, iclass 3, count 0 2006.257.12:05:36.01#ibcon#flushed, iclass 3, count 0 2006.257.12:05:36.01#ibcon#about to write, iclass 3, count 0 2006.257.12:05:36.01#ibcon#wrote, iclass 3, count 0 2006.257.12:05:36.02#ibcon#about to read 3, iclass 3, count 0 2006.257.12:05:36.03#ibcon#read 3, iclass 3, count 0 2006.257.12:05:36.03#ibcon#about to read 4, iclass 3, count 0 2006.257.12:05:36.03#ibcon#read 4, iclass 3, count 0 2006.257.12:05:36.03#ibcon#about to read 5, iclass 3, count 0 2006.257.12:05:36.03#ibcon#read 5, iclass 3, count 0 2006.257.12:05:36.03#ibcon#about to read 6, iclass 3, count 0 2006.257.12:05:36.03#ibcon#read 6, iclass 3, count 0 2006.257.12:05:36.03#ibcon#end of sib2, iclass 3, count 0 2006.257.12:05:36.03#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:05:36.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:05:36.03#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:05:36.03#ibcon#*before write, iclass 3, count 0 2006.257.12:05:36.03#ibcon#enter sib2, iclass 3, count 0 2006.257.12:05:36.03#ibcon#flushed, iclass 3, count 0 2006.257.12:05:36.03#ibcon#about to write, iclass 3, count 0 2006.257.12:05:36.03#ibcon#wrote, iclass 3, count 0 2006.257.12:05:36.03#ibcon#about to read 3, iclass 3, count 0 2006.257.12:05:36.07#ibcon#read 3, iclass 3, count 0 2006.257.12:05:36.07#ibcon#about to read 4, iclass 3, count 0 2006.257.12:05:36.07#ibcon#read 4, iclass 3, count 0 2006.257.12:05:36.07#ibcon#about to read 5, iclass 3, count 0 2006.257.12:05:36.07#ibcon#read 5, iclass 3, count 0 2006.257.12:05:36.07#ibcon#about to read 6, iclass 3, count 0 2006.257.12:05:36.07#ibcon#read 6, iclass 3, count 0 2006.257.12:05:36.07#ibcon#end of sib2, iclass 3, count 0 2006.257.12:05:36.07#ibcon#*after write, iclass 3, count 0 2006.257.12:05:36.07#ibcon#*before return 0, iclass 3, count 0 2006.257.12:05:36.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:36.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:36.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:05:36.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:05:36.07$vck44/va=7,4 2006.257.12:05:36.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.12:05:36.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.12:05:36.07#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:36.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:36.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:36.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:36.13#ibcon#enter wrdev, iclass 5, count 2 2006.257.12:05:36.13#ibcon#first serial, iclass 5, count 2 2006.257.12:05:36.13#ibcon#enter sib2, iclass 5, count 2 2006.257.12:05:36.13#ibcon#flushed, iclass 5, count 2 2006.257.12:05:36.13#ibcon#about to write, iclass 5, count 2 2006.257.12:05:36.13#ibcon#wrote, iclass 5, count 2 2006.257.12:05:36.13#ibcon#about to read 3, iclass 5, count 2 2006.257.12:05:36.15#ibcon#read 3, iclass 5, count 2 2006.257.12:05:36.15#ibcon#about to read 4, iclass 5, count 2 2006.257.12:05:36.15#ibcon#read 4, iclass 5, count 2 2006.257.12:05:36.15#ibcon#about to read 5, iclass 5, count 2 2006.257.12:05:36.15#ibcon#read 5, iclass 5, count 2 2006.257.12:05:36.15#ibcon#about to read 6, iclass 5, count 2 2006.257.12:05:36.15#ibcon#read 6, iclass 5, count 2 2006.257.12:05:36.15#ibcon#end of sib2, iclass 5, count 2 2006.257.12:05:36.15#ibcon#*mode == 0, iclass 5, count 2 2006.257.12:05:36.15#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.12:05:36.15#ibcon#[25=AT07-04\r\n] 2006.257.12:05:36.15#ibcon#*before write, iclass 5, count 2 2006.257.12:05:36.15#ibcon#enter sib2, iclass 5, count 2 2006.257.12:05:36.15#ibcon#flushed, iclass 5, count 2 2006.257.12:05:36.15#ibcon#about to write, iclass 5, count 2 2006.257.12:05:36.15#ibcon#wrote, iclass 5, count 2 2006.257.12:05:36.15#ibcon#about to read 3, iclass 5, count 2 2006.257.12:05:36.18#ibcon#read 3, iclass 5, count 2 2006.257.12:05:36.18#ibcon#about to read 4, iclass 5, count 2 2006.257.12:05:36.18#ibcon#read 4, iclass 5, count 2 2006.257.12:05:36.18#ibcon#about to read 5, iclass 5, count 2 2006.257.12:05:36.18#ibcon#read 5, iclass 5, count 2 2006.257.12:05:36.18#ibcon#about to read 6, iclass 5, count 2 2006.257.12:05:36.18#ibcon#read 6, iclass 5, count 2 2006.257.12:05:36.18#ibcon#end of sib2, iclass 5, count 2 2006.257.12:05:36.18#ibcon#*after write, iclass 5, count 2 2006.257.12:05:36.18#ibcon#*before return 0, iclass 5, count 2 2006.257.12:05:36.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:36.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:36.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.12:05:36.18#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:36.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:36.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:36.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:36.30#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:05:36.30#ibcon#first serial, iclass 5, count 0 2006.257.12:05:36.30#ibcon#enter sib2, iclass 5, count 0 2006.257.12:05:36.30#ibcon#flushed, iclass 5, count 0 2006.257.12:05:36.30#ibcon#about to write, iclass 5, count 0 2006.257.12:05:36.30#ibcon#wrote, iclass 5, count 0 2006.257.12:05:36.30#ibcon#about to read 3, iclass 5, count 0 2006.257.12:05:36.32#ibcon#read 3, iclass 5, count 0 2006.257.12:05:36.32#ibcon#about to read 4, iclass 5, count 0 2006.257.12:05:36.32#ibcon#read 4, iclass 5, count 0 2006.257.12:05:36.32#ibcon#about to read 5, iclass 5, count 0 2006.257.12:05:36.32#ibcon#read 5, iclass 5, count 0 2006.257.12:05:36.32#ibcon#about to read 6, iclass 5, count 0 2006.257.12:05:36.32#ibcon#read 6, iclass 5, count 0 2006.257.12:05:36.32#ibcon#end of sib2, iclass 5, count 0 2006.257.12:05:36.32#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:05:36.32#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:05:36.32#ibcon#[25=USB\r\n] 2006.257.12:05:36.32#ibcon#*before write, iclass 5, count 0 2006.257.12:05:36.32#ibcon#enter sib2, iclass 5, count 0 2006.257.12:05:36.32#ibcon#flushed, iclass 5, count 0 2006.257.12:05:36.32#ibcon#about to write, iclass 5, count 0 2006.257.12:05:36.32#ibcon#wrote, iclass 5, count 0 2006.257.12:05:36.32#ibcon#about to read 3, iclass 5, count 0 2006.257.12:05:36.35#ibcon#read 3, iclass 5, count 0 2006.257.12:05:36.35#ibcon#about to read 4, iclass 5, count 0 2006.257.12:05:36.35#ibcon#read 4, iclass 5, count 0 2006.257.12:05:36.35#ibcon#about to read 5, iclass 5, count 0 2006.257.12:05:36.35#ibcon#read 5, iclass 5, count 0 2006.257.12:05:36.35#ibcon#about to read 6, iclass 5, count 0 2006.257.12:05:36.35#ibcon#read 6, iclass 5, count 0 2006.257.12:05:36.35#ibcon#end of sib2, iclass 5, count 0 2006.257.12:05:36.35#ibcon#*after write, iclass 5, count 0 2006.257.12:05:36.35#ibcon#*before return 0, iclass 5, count 0 2006.257.12:05:36.35#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:36.35#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:36.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:05:36.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:05:36.35$vck44/valo=8,884.99 2006.257.12:05:36.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.12:05:36.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.12:05:36.35#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:36.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:36.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:36.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:36.35#ibcon#enter wrdev, iclass 7, count 0 2006.257.12:05:36.35#ibcon#first serial, iclass 7, count 0 2006.257.12:05:36.35#ibcon#enter sib2, iclass 7, count 0 2006.257.12:05:36.35#ibcon#flushed, iclass 7, count 0 2006.257.12:05:36.35#ibcon#about to write, iclass 7, count 0 2006.257.12:05:36.35#ibcon#wrote, iclass 7, count 0 2006.257.12:05:36.35#ibcon#about to read 3, iclass 7, count 0 2006.257.12:05:36.37#ibcon#read 3, iclass 7, count 0 2006.257.12:05:36.37#ibcon#about to read 4, iclass 7, count 0 2006.257.12:05:36.37#ibcon#read 4, iclass 7, count 0 2006.257.12:05:36.37#ibcon#about to read 5, iclass 7, count 0 2006.257.12:05:36.37#ibcon#read 5, iclass 7, count 0 2006.257.12:05:36.37#ibcon#about to read 6, iclass 7, count 0 2006.257.12:05:36.37#ibcon#read 6, iclass 7, count 0 2006.257.12:05:36.37#ibcon#end of sib2, iclass 7, count 0 2006.257.12:05:36.37#ibcon#*mode == 0, iclass 7, count 0 2006.257.12:05:36.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.12:05:36.37#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:05:36.37#ibcon#*before write, iclass 7, count 0 2006.257.12:05:36.37#ibcon#enter sib2, iclass 7, count 0 2006.257.12:05:36.37#ibcon#flushed, iclass 7, count 0 2006.257.12:05:36.37#ibcon#about to write, iclass 7, count 0 2006.257.12:05:36.37#ibcon#wrote, iclass 7, count 0 2006.257.12:05:36.37#ibcon#about to read 3, iclass 7, count 0 2006.257.12:05:36.41#ibcon#read 3, iclass 7, count 0 2006.257.12:05:36.41#ibcon#about to read 4, iclass 7, count 0 2006.257.12:05:36.41#ibcon#read 4, iclass 7, count 0 2006.257.12:05:36.41#ibcon#about to read 5, iclass 7, count 0 2006.257.12:05:36.41#ibcon#read 5, iclass 7, count 0 2006.257.12:05:36.41#ibcon#about to read 6, iclass 7, count 0 2006.257.12:05:36.41#ibcon#read 6, iclass 7, count 0 2006.257.12:05:36.41#ibcon#end of sib2, iclass 7, count 0 2006.257.12:05:36.41#ibcon#*after write, iclass 7, count 0 2006.257.12:05:36.41#ibcon#*before return 0, iclass 7, count 0 2006.257.12:05:36.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:36.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:36.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.12:05:36.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.12:05:36.41$vck44/va=8,4 2006.257.12:05:36.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.12:05:36.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.12:05:36.41#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:36.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:36.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:36.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:36.47#ibcon#enter wrdev, iclass 11, count 2 2006.257.12:05:36.47#ibcon#first serial, iclass 11, count 2 2006.257.12:05:36.47#ibcon#enter sib2, iclass 11, count 2 2006.257.12:05:36.47#ibcon#flushed, iclass 11, count 2 2006.257.12:05:36.47#ibcon#about to write, iclass 11, count 2 2006.257.12:05:36.47#ibcon#wrote, iclass 11, count 2 2006.257.12:05:36.47#ibcon#about to read 3, iclass 11, count 2 2006.257.12:05:36.49#ibcon#read 3, iclass 11, count 2 2006.257.12:05:36.49#ibcon#about to read 4, iclass 11, count 2 2006.257.12:05:36.49#ibcon#read 4, iclass 11, count 2 2006.257.12:05:36.49#ibcon#about to read 5, iclass 11, count 2 2006.257.12:05:36.49#ibcon#read 5, iclass 11, count 2 2006.257.12:05:36.49#ibcon#about to read 6, iclass 11, count 2 2006.257.12:05:36.49#ibcon#read 6, iclass 11, count 2 2006.257.12:05:36.49#ibcon#end of sib2, iclass 11, count 2 2006.257.12:05:36.49#ibcon#*mode == 0, iclass 11, count 2 2006.257.12:05:36.49#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.12:05:36.49#ibcon#[25=AT08-04\r\n] 2006.257.12:05:36.49#ibcon#*before write, iclass 11, count 2 2006.257.12:05:36.49#ibcon#enter sib2, iclass 11, count 2 2006.257.12:05:36.49#ibcon#flushed, iclass 11, count 2 2006.257.12:05:36.49#ibcon#about to write, iclass 11, count 2 2006.257.12:05:36.49#ibcon#wrote, iclass 11, count 2 2006.257.12:05:36.49#ibcon#about to read 3, iclass 11, count 2 2006.257.12:05:36.52#ibcon#read 3, iclass 11, count 2 2006.257.12:05:36.52#ibcon#about to read 4, iclass 11, count 2 2006.257.12:05:36.52#ibcon#read 4, iclass 11, count 2 2006.257.12:05:36.52#ibcon#about to read 5, iclass 11, count 2 2006.257.12:05:36.52#ibcon#read 5, iclass 11, count 2 2006.257.12:05:36.52#ibcon#about to read 6, iclass 11, count 2 2006.257.12:05:36.52#ibcon#read 6, iclass 11, count 2 2006.257.12:05:36.52#ibcon#end of sib2, iclass 11, count 2 2006.257.12:05:36.52#ibcon#*after write, iclass 11, count 2 2006.257.12:05:36.52#ibcon#*before return 0, iclass 11, count 2 2006.257.12:05:36.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:36.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:36.52#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.12:05:36.52#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:36.52#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:36.64#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:36.64#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:36.64#ibcon#enter wrdev, iclass 11, count 0 2006.257.12:05:36.64#ibcon#first serial, iclass 11, count 0 2006.257.12:05:36.64#ibcon#enter sib2, iclass 11, count 0 2006.257.12:05:36.64#ibcon#flushed, iclass 11, count 0 2006.257.12:05:36.64#ibcon#about to write, iclass 11, count 0 2006.257.12:05:36.64#ibcon#wrote, iclass 11, count 0 2006.257.12:05:36.64#ibcon#about to read 3, iclass 11, count 0 2006.257.12:05:36.66#ibcon#read 3, iclass 11, count 0 2006.257.12:05:36.66#ibcon#about to read 4, iclass 11, count 0 2006.257.12:05:36.66#ibcon#read 4, iclass 11, count 0 2006.257.12:05:36.66#ibcon#about to read 5, iclass 11, count 0 2006.257.12:05:36.66#ibcon#read 5, iclass 11, count 0 2006.257.12:05:36.66#ibcon#about to read 6, iclass 11, count 0 2006.257.12:05:36.66#ibcon#read 6, iclass 11, count 0 2006.257.12:05:36.66#ibcon#end of sib2, iclass 11, count 0 2006.257.12:05:36.66#ibcon#*mode == 0, iclass 11, count 0 2006.257.12:05:36.66#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.12:05:36.66#ibcon#[25=USB\r\n] 2006.257.12:05:36.66#ibcon#*before write, iclass 11, count 0 2006.257.12:05:36.66#ibcon#enter sib2, iclass 11, count 0 2006.257.12:05:36.66#ibcon#flushed, iclass 11, count 0 2006.257.12:05:36.66#ibcon#about to write, iclass 11, count 0 2006.257.12:05:36.66#ibcon#wrote, iclass 11, count 0 2006.257.12:05:36.66#ibcon#about to read 3, iclass 11, count 0 2006.257.12:05:36.69#ibcon#read 3, iclass 11, count 0 2006.257.12:05:36.69#ibcon#about to read 4, iclass 11, count 0 2006.257.12:05:36.69#ibcon#read 4, iclass 11, count 0 2006.257.12:05:36.69#ibcon#about to read 5, iclass 11, count 0 2006.257.12:05:36.69#ibcon#read 5, iclass 11, count 0 2006.257.12:05:36.69#ibcon#about to read 6, iclass 11, count 0 2006.257.12:05:36.69#ibcon#read 6, iclass 11, count 0 2006.257.12:05:36.69#ibcon#end of sib2, iclass 11, count 0 2006.257.12:05:36.69#ibcon#*after write, iclass 11, count 0 2006.257.12:05:36.69#ibcon#*before return 0, iclass 11, count 0 2006.257.12:05:36.69#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:36.69#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:36.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.12:05:36.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.12:05:36.69$vck44/vblo=1,629.99 2006.257.12:05:36.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.12:05:36.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.12:05:36.69#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:36.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:36.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:36.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:36.69#ibcon#enter wrdev, iclass 13, count 0 2006.257.12:05:36.69#ibcon#first serial, iclass 13, count 0 2006.257.12:05:36.69#ibcon#enter sib2, iclass 13, count 0 2006.257.12:05:36.69#ibcon#flushed, iclass 13, count 0 2006.257.12:05:36.69#ibcon#about to write, iclass 13, count 0 2006.257.12:05:36.69#ibcon#wrote, iclass 13, count 0 2006.257.12:05:36.69#ibcon#about to read 3, iclass 13, count 0 2006.257.12:05:36.71#ibcon#read 3, iclass 13, count 0 2006.257.12:05:36.71#ibcon#about to read 4, iclass 13, count 0 2006.257.12:05:36.71#ibcon#read 4, iclass 13, count 0 2006.257.12:05:36.71#ibcon#about to read 5, iclass 13, count 0 2006.257.12:05:36.71#ibcon#read 5, iclass 13, count 0 2006.257.12:05:36.71#ibcon#about to read 6, iclass 13, count 0 2006.257.12:05:36.71#ibcon#read 6, iclass 13, count 0 2006.257.12:05:36.71#ibcon#end of sib2, iclass 13, count 0 2006.257.12:05:36.71#ibcon#*mode == 0, iclass 13, count 0 2006.257.12:05:36.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.12:05:36.71#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:05:36.71#ibcon#*before write, iclass 13, count 0 2006.257.12:05:36.71#ibcon#enter sib2, iclass 13, count 0 2006.257.12:05:36.71#ibcon#flushed, iclass 13, count 0 2006.257.12:05:36.71#ibcon#about to write, iclass 13, count 0 2006.257.12:05:36.71#ibcon#wrote, iclass 13, count 0 2006.257.12:05:36.71#ibcon#about to read 3, iclass 13, count 0 2006.257.12:05:36.75#ibcon#read 3, iclass 13, count 0 2006.257.12:05:36.75#ibcon#about to read 4, iclass 13, count 0 2006.257.12:05:36.75#ibcon#read 4, iclass 13, count 0 2006.257.12:05:36.75#ibcon#about to read 5, iclass 13, count 0 2006.257.12:05:36.75#ibcon#read 5, iclass 13, count 0 2006.257.12:05:36.75#ibcon#about to read 6, iclass 13, count 0 2006.257.12:05:36.75#ibcon#read 6, iclass 13, count 0 2006.257.12:05:36.75#ibcon#end of sib2, iclass 13, count 0 2006.257.12:05:36.75#ibcon#*after write, iclass 13, count 0 2006.257.12:05:36.75#ibcon#*before return 0, iclass 13, count 0 2006.257.12:05:36.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:36.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:36.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.12:05:36.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.12:05:36.75$vck44/vb=1,4 2006.257.12:05:36.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.12:05:36.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.12:05:36.75#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:36.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:05:36.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:05:36.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:05:36.75#ibcon#enter wrdev, iclass 15, count 2 2006.257.12:05:36.75#ibcon#first serial, iclass 15, count 2 2006.257.12:05:36.75#ibcon#enter sib2, iclass 15, count 2 2006.257.12:05:36.75#ibcon#flushed, iclass 15, count 2 2006.257.12:05:36.75#ibcon#about to write, iclass 15, count 2 2006.257.12:05:36.75#ibcon#wrote, iclass 15, count 2 2006.257.12:05:36.75#ibcon#about to read 3, iclass 15, count 2 2006.257.12:05:36.77#ibcon#read 3, iclass 15, count 2 2006.257.12:05:36.77#ibcon#about to read 4, iclass 15, count 2 2006.257.12:05:36.77#ibcon#read 4, iclass 15, count 2 2006.257.12:05:36.77#ibcon#about to read 5, iclass 15, count 2 2006.257.12:05:36.77#ibcon#read 5, iclass 15, count 2 2006.257.12:05:36.77#ibcon#about to read 6, iclass 15, count 2 2006.257.12:05:36.77#ibcon#read 6, iclass 15, count 2 2006.257.12:05:36.77#ibcon#end of sib2, iclass 15, count 2 2006.257.12:05:36.77#ibcon#*mode == 0, iclass 15, count 2 2006.257.12:05:36.77#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.12:05:36.77#ibcon#[27=AT01-04\r\n] 2006.257.12:05:36.77#ibcon#*before write, iclass 15, count 2 2006.257.12:05:36.77#ibcon#enter sib2, iclass 15, count 2 2006.257.12:05:36.77#ibcon#flushed, iclass 15, count 2 2006.257.12:05:36.77#ibcon#about to write, iclass 15, count 2 2006.257.12:05:36.77#ibcon#wrote, iclass 15, count 2 2006.257.12:05:36.77#ibcon#about to read 3, iclass 15, count 2 2006.257.12:05:36.80#ibcon#read 3, iclass 15, count 2 2006.257.12:05:36.80#ibcon#about to read 4, iclass 15, count 2 2006.257.12:05:36.80#ibcon#read 4, iclass 15, count 2 2006.257.12:05:36.80#ibcon#about to read 5, iclass 15, count 2 2006.257.12:05:36.80#ibcon#read 5, iclass 15, count 2 2006.257.12:05:36.80#ibcon#about to read 6, iclass 15, count 2 2006.257.12:05:36.80#ibcon#read 6, iclass 15, count 2 2006.257.12:05:36.80#ibcon#end of sib2, iclass 15, count 2 2006.257.12:05:36.80#ibcon#*after write, iclass 15, count 2 2006.257.12:05:36.80#ibcon#*before return 0, iclass 15, count 2 2006.257.12:05:36.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:05:36.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:05:36.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.12:05:36.80#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:36.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:05:36.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:05:36.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:05:36.92#ibcon#enter wrdev, iclass 15, count 0 2006.257.12:05:36.92#ibcon#first serial, iclass 15, count 0 2006.257.12:05:36.92#ibcon#enter sib2, iclass 15, count 0 2006.257.12:05:36.92#ibcon#flushed, iclass 15, count 0 2006.257.12:05:36.92#ibcon#about to write, iclass 15, count 0 2006.257.12:05:36.92#ibcon#wrote, iclass 15, count 0 2006.257.12:05:36.92#ibcon#about to read 3, iclass 15, count 0 2006.257.12:05:36.94#ibcon#read 3, iclass 15, count 0 2006.257.12:05:36.94#ibcon#about to read 4, iclass 15, count 0 2006.257.12:05:36.94#ibcon#read 4, iclass 15, count 0 2006.257.12:05:36.94#ibcon#about to read 5, iclass 15, count 0 2006.257.12:05:36.94#ibcon#read 5, iclass 15, count 0 2006.257.12:05:36.94#ibcon#about to read 6, iclass 15, count 0 2006.257.12:05:36.94#ibcon#read 6, iclass 15, count 0 2006.257.12:05:36.94#ibcon#end of sib2, iclass 15, count 0 2006.257.12:05:36.94#ibcon#*mode == 0, iclass 15, count 0 2006.257.12:05:36.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.12:05:36.94#ibcon#[27=USB\r\n] 2006.257.12:05:36.94#ibcon#*before write, iclass 15, count 0 2006.257.12:05:36.94#ibcon#enter sib2, iclass 15, count 0 2006.257.12:05:36.94#ibcon#flushed, iclass 15, count 0 2006.257.12:05:36.94#ibcon#about to write, iclass 15, count 0 2006.257.12:05:36.94#ibcon#wrote, iclass 15, count 0 2006.257.12:05:36.94#ibcon#about to read 3, iclass 15, count 0 2006.257.12:05:36.97#ibcon#read 3, iclass 15, count 0 2006.257.12:05:36.97#ibcon#about to read 4, iclass 15, count 0 2006.257.12:05:36.97#ibcon#read 4, iclass 15, count 0 2006.257.12:05:36.97#ibcon#about to read 5, iclass 15, count 0 2006.257.12:05:36.97#ibcon#read 5, iclass 15, count 0 2006.257.12:05:36.97#ibcon#about to read 6, iclass 15, count 0 2006.257.12:05:36.97#ibcon#read 6, iclass 15, count 0 2006.257.12:05:36.97#ibcon#end of sib2, iclass 15, count 0 2006.257.12:05:36.97#ibcon#*after write, iclass 15, count 0 2006.257.12:05:36.97#ibcon#*before return 0, iclass 15, count 0 2006.257.12:05:36.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:05:36.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:05:36.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.12:05:36.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.12:05:36.97$vck44/vblo=2,634.99 2006.257.12:05:36.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.12:05:36.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.12:05:36.97#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:36.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:36.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:36.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:36.97#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:05:36.97#ibcon#first serial, iclass 17, count 0 2006.257.12:05:36.97#ibcon#enter sib2, iclass 17, count 0 2006.257.12:05:36.97#ibcon#flushed, iclass 17, count 0 2006.257.12:05:36.97#ibcon#about to write, iclass 17, count 0 2006.257.12:05:36.97#ibcon#wrote, iclass 17, count 0 2006.257.12:05:36.97#ibcon#about to read 3, iclass 17, count 0 2006.257.12:05:36.99#ibcon#read 3, iclass 17, count 0 2006.257.12:05:36.99#ibcon#about to read 4, iclass 17, count 0 2006.257.12:05:36.99#ibcon#read 4, iclass 17, count 0 2006.257.12:05:36.99#ibcon#about to read 5, iclass 17, count 0 2006.257.12:05:36.99#ibcon#read 5, iclass 17, count 0 2006.257.12:05:36.99#ibcon#about to read 6, iclass 17, count 0 2006.257.12:05:36.99#ibcon#read 6, iclass 17, count 0 2006.257.12:05:36.99#ibcon#end of sib2, iclass 17, count 0 2006.257.12:05:36.99#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:05:36.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:05:36.99#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:05:36.99#ibcon#*before write, iclass 17, count 0 2006.257.12:05:36.99#ibcon#enter sib2, iclass 17, count 0 2006.257.12:05:36.99#ibcon#flushed, iclass 17, count 0 2006.257.12:05:36.99#ibcon#about to write, iclass 17, count 0 2006.257.12:05:36.99#ibcon#wrote, iclass 17, count 0 2006.257.12:05:36.99#ibcon#about to read 3, iclass 17, count 0 2006.257.12:05:37.03#ibcon#read 3, iclass 17, count 0 2006.257.12:05:37.03#ibcon#about to read 4, iclass 17, count 0 2006.257.12:05:37.03#ibcon#read 4, iclass 17, count 0 2006.257.12:05:37.03#ibcon#about to read 5, iclass 17, count 0 2006.257.12:05:37.03#ibcon#read 5, iclass 17, count 0 2006.257.12:05:37.03#ibcon#about to read 6, iclass 17, count 0 2006.257.12:05:37.03#ibcon#read 6, iclass 17, count 0 2006.257.12:05:37.03#ibcon#end of sib2, iclass 17, count 0 2006.257.12:05:37.03#ibcon#*after write, iclass 17, count 0 2006.257.12:05:37.03#ibcon#*before return 0, iclass 17, count 0 2006.257.12:05:37.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:37.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:05:37.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:05:37.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:05:37.03$vck44/vb=2,5 2006.257.12:05:37.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.12:05:37.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.12:05:37.03#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:37.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:37.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:37.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:37.09#ibcon#enter wrdev, iclass 19, count 2 2006.257.12:05:37.09#ibcon#first serial, iclass 19, count 2 2006.257.12:05:37.09#ibcon#enter sib2, iclass 19, count 2 2006.257.12:05:37.09#ibcon#flushed, iclass 19, count 2 2006.257.12:05:37.09#ibcon#about to write, iclass 19, count 2 2006.257.12:05:37.09#ibcon#wrote, iclass 19, count 2 2006.257.12:05:37.09#ibcon#about to read 3, iclass 19, count 2 2006.257.12:05:37.11#ibcon#read 3, iclass 19, count 2 2006.257.12:05:37.11#ibcon#about to read 4, iclass 19, count 2 2006.257.12:05:37.11#ibcon#read 4, iclass 19, count 2 2006.257.12:05:37.11#ibcon#about to read 5, iclass 19, count 2 2006.257.12:05:37.11#ibcon#read 5, iclass 19, count 2 2006.257.12:05:37.11#ibcon#about to read 6, iclass 19, count 2 2006.257.12:05:37.11#ibcon#read 6, iclass 19, count 2 2006.257.12:05:37.11#ibcon#end of sib2, iclass 19, count 2 2006.257.12:05:37.11#ibcon#*mode == 0, iclass 19, count 2 2006.257.12:05:37.11#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.12:05:37.11#ibcon#[27=AT02-05\r\n] 2006.257.12:05:37.11#ibcon#*before write, iclass 19, count 2 2006.257.12:05:37.11#ibcon#enter sib2, iclass 19, count 2 2006.257.12:05:37.11#ibcon#flushed, iclass 19, count 2 2006.257.12:05:37.11#ibcon#about to write, iclass 19, count 2 2006.257.12:05:37.11#ibcon#wrote, iclass 19, count 2 2006.257.12:05:37.11#ibcon#about to read 3, iclass 19, count 2 2006.257.12:05:37.14#ibcon#read 3, iclass 19, count 2 2006.257.12:05:37.14#ibcon#about to read 4, iclass 19, count 2 2006.257.12:05:37.14#ibcon#read 4, iclass 19, count 2 2006.257.12:05:37.14#ibcon#about to read 5, iclass 19, count 2 2006.257.12:05:37.14#ibcon#read 5, iclass 19, count 2 2006.257.12:05:37.14#ibcon#about to read 6, iclass 19, count 2 2006.257.12:05:37.14#ibcon#read 6, iclass 19, count 2 2006.257.12:05:37.14#ibcon#end of sib2, iclass 19, count 2 2006.257.12:05:37.14#ibcon#*after write, iclass 19, count 2 2006.257.12:05:37.14#ibcon#*before return 0, iclass 19, count 2 2006.257.12:05:37.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:37.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:05:37.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.12:05:37.14#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:37.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:37.18#abcon#<5=/14 1.4 3.4 18.19 951013.9\r\n> 2006.257.12:05:37.20#abcon#{5=INTERFACE CLEAR} 2006.257.12:05:37.26#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:05:37.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:37.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:37.26#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:05:37.26#ibcon#first serial, iclass 19, count 0 2006.257.12:05:37.26#ibcon#enter sib2, iclass 19, count 0 2006.257.12:05:37.26#ibcon#flushed, iclass 19, count 0 2006.257.12:05:37.26#ibcon#about to write, iclass 19, count 0 2006.257.12:05:37.26#ibcon#wrote, iclass 19, count 0 2006.257.12:05:37.26#ibcon#about to read 3, iclass 19, count 0 2006.257.12:05:37.28#ibcon#read 3, iclass 19, count 0 2006.257.12:05:37.28#ibcon#about to read 4, iclass 19, count 0 2006.257.12:05:37.28#ibcon#read 4, iclass 19, count 0 2006.257.12:05:37.28#ibcon#about to read 5, iclass 19, count 0 2006.257.12:05:37.28#ibcon#read 5, iclass 19, count 0 2006.257.12:05:37.28#ibcon#about to read 6, iclass 19, count 0 2006.257.12:05:37.28#ibcon#read 6, iclass 19, count 0 2006.257.12:05:37.28#ibcon#end of sib2, iclass 19, count 0 2006.257.12:05:37.28#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:05:37.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:05:37.28#ibcon#[27=USB\r\n] 2006.257.12:05:37.28#ibcon#*before write, iclass 19, count 0 2006.257.12:05:37.28#ibcon#enter sib2, iclass 19, count 0 2006.257.12:05:37.28#ibcon#flushed, iclass 19, count 0 2006.257.12:05:37.28#ibcon#about to write, iclass 19, count 0 2006.257.12:05:37.28#ibcon#wrote, iclass 19, count 0 2006.257.12:05:37.28#ibcon#about to read 3, iclass 19, count 0 2006.257.12:05:37.31#ibcon#read 3, iclass 19, count 0 2006.257.12:05:37.31#ibcon#about to read 4, iclass 19, count 0 2006.257.12:05:37.31#ibcon#read 4, iclass 19, count 0 2006.257.12:05:37.31#ibcon#about to read 5, iclass 19, count 0 2006.257.12:05:37.31#ibcon#read 5, iclass 19, count 0 2006.257.12:05:37.31#ibcon#about to read 6, iclass 19, count 0 2006.257.12:05:37.31#ibcon#read 6, iclass 19, count 0 2006.257.12:05:37.31#ibcon#end of sib2, iclass 19, count 0 2006.257.12:05:37.31#ibcon#*after write, iclass 19, count 0 2006.257.12:05:37.31#ibcon#*before return 0, iclass 19, count 0 2006.257.12:05:37.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:37.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:05:37.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:05:37.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:05:37.31$vck44/vblo=3,649.99 2006.257.12:05:37.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.12:05:37.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.12:05:37.31#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:37.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:37.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:37.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:37.31#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:05:37.31#ibcon#first serial, iclass 25, count 0 2006.257.12:05:37.31#ibcon#enter sib2, iclass 25, count 0 2006.257.12:05:37.31#ibcon#flushed, iclass 25, count 0 2006.257.12:05:37.31#ibcon#about to write, iclass 25, count 0 2006.257.12:05:37.31#ibcon#wrote, iclass 25, count 0 2006.257.12:05:37.31#ibcon#about to read 3, iclass 25, count 0 2006.257.12:05:37.33#ibcon#read 3, iclass 25, count 0 2006.257.12:05:37.33#ibcon#about to read 4, iclass 25, count 0 2006.257.12:05:37.33#ibcon#read 4, iclass 25, count 0 2006.257.12:05:37.33#ibcon#about to read 5, iclass 25, count 0 2006.257.12:05:37.33#ibcon#read 5, iclass 25, count 0 2006.257.12:05:37.33#ibcon#about to read 6, iclass 25, count 0 2006.257.12:05:37.33#ibcon#read 6, iclass 25, count 0 2006.257.12:05:37.33#ibcon#end of sib2, iclass 25, count 0 2006.257.12:05:37.33#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:05:37.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:05:37.33#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:05:37.33#ibcon#*before write, iclass 25, count 0 2006.257.12:05:37.33#ibcon#enter sib2, iclass 25, count 0 2006.257.12:05:37.33#ibcon#flushed, iclass 25, count 0 2006.257.12:05:37.33#ibcon#about to write, iclass 25, count 0 2006.257.12:05:37.33#ibcon#wrote, iclass 25, count 0 2006.257.12:05:37.33#ibcon#about to read 3, iclass 25, count 0 2006.257.12:05:37.37#ibcon#read 3, iclass 25, count 0 2006.257.12:05:37.37#ibcon#about to read 4, iclass 25, count 0 2006.257.12:05:37.37#ibcon#read 4, iclass 25, count 0 2006.257.12:05:37.37#ibcon#about to read 5, iclass 25, count 0 2006.257.12:05:37.37#ibcon#read 5, iclass 25, count 0 2006.257.12:05:37.37#ibcon#about to read 6, iclass 25, count 0 2006.257.12:05:37.37#ibcon#read 6, iclass 25, count 0 2006.257.12:05:37.37#ibcon#end of sib2, iclass 25, count 0 2006.257.12:05:37.37#ibcon#*after write, iclass 25, count 0 2006.257.12:05:37.37#ibcon#*before return 0, iclass 25, count 0 2006.257.12:05:37.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:37.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:05:37.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:05:37.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:05:37.37$vck44/vb=3,4 2006.257.12:05:37.37#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.12:05:37.37#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.12:05:37.37#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:37.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:37.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:37.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:37.43#ibcon#enter wrdev, iclass 27, count 2 2006.257.12:05:37.43#ibcon#first serial, iclass 27, count 2 2006.257.12:05:37.43#ibcon#enter sib2, iclass 27, count 2 2006.257.12:05:37.43#ibcon#flushed, iclass 27, count 2 2006.257.12:05:37.43#ibcon#about to write, iclass 27, count 2 2006.257.12:05:37.43#ibcon#wrote, iclass 27, count 2 2006.257.12:05:37.43#ibcon#about to read 3, iclass 27, count 2 2006.257.12:05:37.45#ibcon#read 3, iclass 27, count 2 2006.257.12:05:37.45#ibcon#about to read 4, iclass 27, count 2 2006.257.12:05:37.45#ibcon#read 4, iclass 27, count 2 2006.257.12:05:37.45#ibcon#about to read 5, iclass 27, count 2 2006.257.12:05:37.45#ibcon#read 5, iclass 27, count 2 2006.257.12:05:37.45#ibcon#about to read 6, iclass 27, count 2 2006.257.12:05:37.45#ibcon#read 6, iclass 27, count 2 2006.257.12:05:37.45#ibcon#end of sib2, iclass 27, count 2 2006.257.12:05:37.45#ibcon#*mode == 0, iclass 27, count 2 2006.257.12:05:37.45#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.12:05:37.45#ibcon#[27=AT03-04\r\n] 2006.257.12:05:37.45#ibcon#*before write, iclass 27, count 2 2006.257.12:05:37.45#ibcon#enter sib2, iclass 27, count 2 2006.257.12:05:37.45#ibcon#flushed, iclass 27, count 2 2006.257.12:05:37.45#ibcon#about to write, iclass 27, count 2 2006.257.12:05:37.45#ibcon#wrote, iclass 27, count 2 2006.257.12:05:37.45#ibcon#about to read 3, iclass 27, count 2 2006.257.12:05:37.48#ibcon#read 3, iclass 27, count 2 2006.257.12:05:37.48#ibcon#about to read 4, iclass 27, count 2 2006.257.12:05:37.48#ibcon#read 4, iclass 27, count 2 2006.257.12:05:37.48#ibcon#about to read 5, iclass 27, count 2 2006.257.12:05:37.48#ibcon#read 5, iclass 27, count 2 2006.257.12:05:37.48#ibcon#about to read 6, iclass 27, count 2 2006.257.12:05:37.48#ibcon#read 6, iclass 27, count 2 2006.257.12:05:37.48#ibcon#end of sib2, iclass 27, count 2 2006.257.12:05:37.48#ibcon#*after write, iclass 27, count 2 2006.257.12:05:37.48#ibcon#*before return 0, iclass 27, count 2 2006.257.12:05:37.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:37.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:05:37.48#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.12:05:37.48#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:37.48#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:37.60#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:37.60#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:37.60#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:05:37.60#ibcon#first serial, iclass 27, count 0 2006.257.12:05:37.60#ibcon#enter sib2, iclass 27, count 0 2006.257.12:05:37.60#ibcon#flushed, iclass 27, count 0 2006.257.12:05:37.60#ibcon#about to write, iclass 27, count 0 2006.257.12:05:37.60#ibcon#wrote, iclass 27, count 0 2006.257.12:05:37.60#ibcon#about to read 3, iclass 27, count 0 2006.257.12:05:37.62#ibcon#read 3, iclass 27, count 0 2006.257.12:05:37.62#ibcon#about to read 4, iclass 27, count 0 2006.257.12:05:37.62#ibcon#read 4, iclass 27, count 0 2006.257.12:05:37.62#ibcon#about to read 5, iclass 27, count 0 2006.257.12:05:37.62#ibcon#read 5, iclass 27, count 0 2006.257.12:05:37.62#ibcon#about to read 6, iclass 27, count 0 2006.257.12:05:37.62#ibcon#read 6, iclass 27, count 0 2006.257.12:05:37.62#ibcon#end of sib2, iclass 27, count 0 2006.257.12:05:37.62#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:05:37.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:05:37.62#ibcon#[27=USB\r\n] 2006.257.12:05:37.62#ibcon#*before write, iclass 27, count 0 2006.257.12:05:37.62#ibcon#enter sib2, iclass 27, count 0 2006.257.12:05:37.62#ibcon#flushed, iclass 27, count 0 2006.257.12:05:37.62#ibcon#about to write, iclass 27, count 0 2006.257.12:05:37.62#ibcon#wrote, iclass 27, count 0 2006.257.12:05:37.62#ibcon#about to read 3, iclass 27, count 0 2006.257.12:05:37.65#ibcon#read 3, iclass 27, count 0 2006.257.12:05:37.65#ibcon#about to read 4, iclass 27, count 0 2006.257.12:05:37.65#ibcon#read 4, iclass 27, count 0 2006.257.12:05:37.65#ibcon#about to read 5, iclass 27, count 0 2006.257.12:05:37.65#ibcon#read 5, iclass 27, count 0 2006.257.12:05:37.65#ibcon#about to read 6, iclass 27, count 0 2006.257.12:05:37.65#ibcon#read 6, iclass 27, count 0 2006.257.12:05:37.65#ibcon#end of sib2, iclass 27, count 0 2006.257.12:05:37.65#ibcon#*after write, iclass 27, count 0 2006.257.12:05:37.65#ibcon#*before return 0, iclass 27, count 0 2006.257.12:05:37.65#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:37.65#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:05:37.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:05:37.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:05:37.65$vck44/vblo=4,679.99 2006.257.12:05:37.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.12:05:37.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.12:05:37.65#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:37.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:37.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:37.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:37.65#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:05:37.65#ibcon#first serial, iclass 29, count 0 2006.257.12:05:37.65#ibcon#enter sib2, iclass 29, count 0 2006.257.12:05:37.65#ibcon#flushed, iclass 29, count 0 2006.257.12:05:37.65#ibcon#about to write, iclass 29, count 0 2006.257.12:05:37.65#ibcon#wrote, iclass 29, count 0 2006.257.12:05:37.65#ibcon#about to read 3, iclass 29, count 0 2006.257.12:05:37.67#ibcon#read 3, iclass 29, count 0 2006.257.12:05:37.67#ibcon#about to read 4, iclass 29, count 0 2006.257.12:05:37.67#ibcon#read 4, iclass 29, count 0 2006.257.12:05:37.67#ibcon#about to read 5, iclass 29, count 0 2006.257.12:05:37.67#ibcon#read 5, iclass 29, count 0 2006.257.12:05:37.67#ibcon#about to read 6, iclass 29, count 0 2006.257.12:05:37.67#ibcon#read 6, iclass 29, count 0 2006.257.12:05:37.67#ibcon#end of sib2, iclass 29, count 0 2006.257.12:05:37.67#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:05:37.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:05:37.67#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:05:37.67#ibcon#*before write, iclass 29, count 0 2006.257.12:05:37.67#ibcon#enter sib2, iclass 29, count 0 2006.257.12:05:37.67#ibcon#flushed, iclass 29, count 0 2006.257.12:05:37.67#ibcon#about to write, iclass 29, count 0 2006.257.12:05:37.67#ibcon#wrote, iclass 29, count 0 2006.257.12:05:37.67#ibcon#about to read 3, iclass 29, count 0 2006.257.12:05:37.71#ibcon#read 3, iclass 29, count 0 2006.257.12:05:37.71#ibcon#about to read 4, iclass 29, count 0 2006.257.12:05:37.71#ibcon#read 4, iclass 29, count 0 2006.257.12:05:37.71#ibcon#about to read 5, iclass 29, count 0 2006.257.12:05:37.71#ibcon#read 5, iclass 29, count 0 2006.257.12:05:37.71#ibcon#about to read 6, iclass 29, count 0 2006.257.12:05:37.71#ibcon#read 6, iclass 29, count 0 2006.257.12:05:37.71#ibcon#end of sib2, iclass 29, count 0 2006.257.12:05:37.71#ibcon#*after write, iclass 29, count 0 2006.257.12:05:37.71#ibcon#*before return 0, iclass 29, count 0 2006.257.12:05:37.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:37.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:05:37.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:05:37.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:05:37.71$vck44/vb=4,5 2006.257.12:05:37.71#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.12:05:37.71#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.12:05:37.71#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:37.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:37.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:37.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:37.77#ibcon#enter wrdev, iclass 31, count 2 2006.257.12:05:37.77#ibcon#first serial, iclass 31, count 2 2006.257.12:05:37.77#ibcon#enter sib2, iclass 31, count 2 2006.257.12:05:37.77#ibcon#flushed, iclass 31, count 2 2006.257.12:05:37.77#ibcon#about to write, iclass 31, count 2 2006.257.12:05:37.77#ibcon#wrote, iclass 31, count 2 2006.257.12:05:37.77#ibcon#about to read 3, iclass 31, count 2 2006.257.12:05:37.79#ibcon#read 3, iclass 31, count 2 2006.257.12:05:37.79#ibcon#about to read 4, iclass 31, count 2 2006.257.12:05:37.79#ibcon#read 4, iclass 31, count 2 2006.257.12:05:37.79#ibcon#about to read 5, iclass 31, count 2 2006.257.12:05:37.79#ibcon#read 5, iclass 31, count 2 2006.257.12:05:37.79#ibcon#about to read 6, iclass 31, count 2 2006.257.12:05:37.79#ibcon#read 6, iclass 31, count 2 2006.257.12:05:37.79#ibcon#end of sib2, iclass 31, count 2 2006.257.12:05:37.79#ibcon#*mode == 0, iclass 31, count 2 2006.257.12:05:37.79#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.12:05:37.79#ibcon#[27=AT04-05\r\n] 2006.257.12:05:37.79#ibcon#*before write, iclass 31, count 2 2006.257.12:05:37.79#ibcon#enter sib2, iclass 31, count 2 2006.257.12:05:37.79#ibcon#flushed, iclass 31, count 2 2006.257.12:05:37.79#ibcon#about to write, iclass 31, count 2 2006.257.12:05:37.79#ibcon#wrote, iclass 31, count 2 2006.257.12:05:37.79#ibcon#about to read 3, iclass 31, count 2 2006.257.12:05:37.82#ibcon#read 3, iclass 31, count 2 2006.257.12:05:37.82#ibcon#about to read 4, iclass 31, count 2 2006.257.12:05:37.82#ibcon#read 4, iclass 31, count 2 2006.257.12:05:37.82#ibcon#about to read 5, iclass 31, count 2 2006.257.12:05:37.82#ibcon#read 5, iclass 31, count 2 2006.257.12:05:37.82#ibcon#about to read 6, iclass 31, count 2 2006.257.12:05:37.82#ibcon#read 6, iclass 31, count 2 2006.257.12:05:37.82#ibcon#end of sib2, iclass 31, count 2 2006.257.12:05:37.82#ibcon#*after write, iclass 31, count 2 2006.257.12:05:37.82#ibcon#*before return 0, iclass 31, count 2 2006.257.12:05:37.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:37.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:05:37.82#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.12:05:37.82#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:37.82#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:37.94#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:37.94#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:37.94#ibcon#enter wrdev, iclass 31, count 0 2006.257.12:05:37.94#ibcon#first serial, iclass 31, count 0 2006.257.12:05:37.94#ibcon#enter sib2, iclass 31, count 0 2006.257.12:05:37.94#ibcon#flushed, iclass 31, count 0 2006.257.12:05:37.94#ibcon#about to write, iclass 31, count 0 2006.257.12:05:37.94#ibcon#wrote, iclass 31, count 0 2006.257.12:05:37.94#ibcon#about to read 3, iclass 31, count 0 2006.257.12:05:37.96#ibcon#read 3, iclass 31, count 0 2006.257.12:05:37.96#ibcon#about to read 4, iclass 31, count 0 2006.257.12:05:37.96#ibcon#read 4, iclass 31, count 0 2006.257.12:05:37.96#ibcon#about to read 5, iclass 31, count 0 2006.257.12:05:37.96#ibcon#read 5, iclass 31, count 0 2006.257.12:05:37.96#ibcon#about to read 6, iclass 31, count 0 2006.257.12:05:37.96#ibcon#read 6, iclass 31, count 0 2006.257.12:05:37.96#ibcon#end of sib2, iclass 31, count 0 2006.257.12:05:37.96#ibcon#*mode == 0, iclass 31, count 0 2006.257.12:05:37.96#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.12:05:37.96#ibcon#[27=USB\r\n] 2006.257.12:05:37.96#ibcon#*before write, iclass 31, count 0 2006.257.12:05:37.96#ibcon#enter sib2, iclass 31, count 0 2006.257.12:05:37.96#ibcon#flushed, iclass 31, count 0 2006.257.12:05:37.96#ibcon#about to write, iclass 31, count 0 2006.257.12:05:37.96#ibcon#wrote, iclass 31, count 0 2006.257.12:05:37.96#ibcon#about to read 3, iclass 31, count 0 2006.257.12:05:37.99#ibcon#read 3, iclass 31, count 0 2006.257.12:05:37.99#ibcon#about to read 4, iclass 31, count 0 2006.257.12:05:37.99#ibcon#read 4, iclass 31, count 0 2006.257.12:05:37.99#ibcon#about to read 5, iclass 31, count 0 2006.257.12:05:37.99#ibcon#read 5, iclass 31, count 0 2006.257.12:05:37.99#ibcon#about to read 6, iclass 31, count 0 2006.257.12:05:37.99#ibcon#read 6, iclass 31, count 0 2006.257.12:05:37.99#ibcon#end of sib2, iclass 31, count 0 2006.257.12:05:37.99#ibcon#*after write, iclass 31, count 0 2006.257.12:05:37.99#ibcon#*before return 0, iclass 31, count 0 2006.257.12:05:37.99#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:37.99#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:05:37.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.12:05:37.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.12:05:37.99$vck44/vblo=5,709.99 2006.257.12:05:37.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.12:05:37.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.12:05:37.99#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:37.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:37.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:37.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:37.99#ibcon#enter wrdev, iclass 33, count 0 2006.257.12:05:37.99#ibcon#first serial, iclass 33, count 0 2006.257.12:05:37.99#ibcon#enter sib2, iclass 33, count 0 2006.257.12:05:37.99#ibcon#flushed, iclass 33, count 0 2006.257.12:05:37.99#ibcon#about to write, iclass 33, count 0 2006.257.12:05:37.99#ibcon#wrote, iclass 33, count 0 2006.257.12:05:37.99#ibcon#about to read 3, iclass 33, count 0 2006.257.12:05:38.01#ibcon#read 3, iclass 33, count 0 2006.257.12:05:38.01#ibcon#about to read 4, iclass 33, count 0 2006.257.12:05:38.01#ibcon#read 4, iclass 33, count 0 2006.257.12:05:38.01#ibcon#about to read 5, iclass 33, count 0 2006.257.12:05:38.01#ibcon#read 5, iclass 33, count 0 2006.257.12:05:38.01#ibcon#about to read 6, iclass 33, count 0 2006.257.12:05:38.01#ibcon#read 6, iclass 33, count 0 2006.257.12:05:38.01#ibcon#end of sib2, iclass 33, count 0 2006.257.12:05:38.01#ibcon#*mode == 0, iclass 33, count 0 2006.257.12:05:38.01#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.12:05:38.01#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:05:38.01#ibcon#*before write, iclass 33, count 0 2006.257.12:05:38.01#ibcon#enter sib2, iclass 33, count 0 2006.257.12:05:38.01#ibcon#flushed, iclass 33, count 0 2006.257.12:05:38.01#ibcon#about to write, iclass 33, count 0 2006.257.12:05:38.01#ibcon#wrote, iclass 33, count 0 2006.257.12:05:38.01#ibcon#about to read 3, iclass 33, count 0 2006.257.12:05:38.05#ibcon#read 3, iclass 33, count 0 2006.257.12:05:38.05#ibcon#about to read 4, iclass 33, count 0 2006.257.12:05:38.05#ibcon#read 4, iclass 33, count 0 2006.257.12:05:38.05#ibcon#about to read 5, iclass 33, count 0 2006.257.12:05:38.05#ibcon#read 5, iclass 33, count 0 2006.257.12:05:38.05#ibcon#about to read 6, iclass 33, count 0 2006.257.12:05:38.05#ibcon#read 6, iclass 33, count 0 2006.257.12:05:38.05#ibcon#end of sib2, iclass 33, count 0 2006.257.12:05:38.05#ibcon#*after write, iclass 33, count 0 2006.257.12:05:38.05#ibcon#*before return 0, iclass 33, count 0 2006.257.12:05:38.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:38.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:05:38.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.12:05:38.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.12:05:38.05$vck44/vb=5,4 2006.257.12:05:38.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.12:05:38.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.12:05:38.05#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:38.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:38.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:38.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:38.11#ibcon#enter wrdev, iclass 35, count 2 2006.257.12:05:38.11#ibcon#first serial, iclass 35, count 2 2006.257.12:05:38.11#ibcon#enter sib2, iclass 35, count 2 2006.257.12:05:38.11#ibcon#flushed, iclass 35, count 2 2006.257.12:05:38.11#ibcon#about to write, iclass 35, count 2 2006.257.12:05:38.11#ibcon#wrote, iclass 35, count 2 2006.257.12:05:38.11#ibcon#about to read 3, iclass 35, count 2 2006.257.12:05:38.13#ibcon#read 3, iclass 35, count 2 2006.257.12:05:38.13#ibcon#about to read 4, iclass 35, count 2 2006.257.12:05:38.13#ibcon#read 4, iclass 35, count 2 2006.257.12:05:38.13#ibcon#about to read 5, iclass 35, count 2 2006.257.12:05:38.13#ibcon#read 5, iclass 35, count 2 2006.257.12:05:38.13#ibcon#about to read 6, iclass 35, count 2 2006.257.12:05:38.13#ibcon#read 6, iclass 35, count 2 2006.257.12:05:38.13#ibcon#end of sib2, iclass 35, count 2 2006.257.12:05:38.13#ibcon#*mode == 0, iclass 35, count 2 2006.257.12:05:38.13#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.12:05:38.13#ibcon#[27=AT05-04\r\n] 2006.257.12:05:38.13#ibcon#*before write, iclass 35, count 2 2006.257.12:05:38.13#ibcon#enter sib2, iclass 35, count 2 2006.257.12:05:38.13#ibcon#flushed, iclass 35, count 2 2006.257.12:05:38.13#ibcon#about to write, iclass 35, count 2 2006.257.12:05:38.13#ibcon#wrote, iclass 35, count 2 2006.257.12:05:38.13#ibcon#about to read 3, iclass 35, count 2 2006.257.12:05:38.16#ibcon#read 3, iclass 35, count 2 2006.257.12:05:38.16#ibcon#about to read 4, iclass 35, count 2 2006.257.12:05:38.16#ibcon#read 4, iclass 35, count 2 2006.257.12:05:38.16#ibcon#about to read 5, iclass 35, count 2 2006.257.12:05:38.16#ibcon#read 5, iclass 35, count 2 2006.257.12:05:38.16#ibcon#about to read 6, iclass 35, count 2 2006.257.12:05:38.16#ibcon#read 6, iclass 35, count 2 2006.257.12:05:38.16#ibcon#end of sib2, iclass 35, count 2 2006.257.12:05:38.16#ibcon#*after write, iclass 35, count 2 2006.257.12:05:38.16#ibcon#*before return 0, iclass 35, count 2 2006.257.12:05:38.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:38.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:05:38.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.12:05:38.16#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:38.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:38.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:38.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:38.28#ibcon#enter wrdev, iclass 35, count 0 2006.257.12:05:38.28#ibcon#first serial, iclass 35, count 0 2006.257.12:05:38.28#ibcon#enter sib2, iclass 35, count 0 2006.257.12:05:38.28#ibcon#flushed, iclass 35, count 0 2006.257.12:05:38.28#ibcon#about to write, iclass 35, count 0 2006.257.12:05:38.28#ibcon#wrote, iclass 35, count 0 2006.257.12:05:38.28#ibcon#about to read 3, iclass 35, count 0 2006.257.12:05:38.30#ibcon#read 3, iclass 35, count 0 2006.257.12:05:38.30#ibcon#about to read 4, iclass 35, count 0 2006.257.12:05:38.30#ibcon#read 4, iclass 35, count 0 2006.257.12:05:38.30#ibcon#about to read 5, iclass 35, count 0 2006.257.12:05:38.30#ibcon#read 5, iclass 35, count 0 2006.257.12:05:38.30#ibcon#about to read 6, iclass 35, count 0 2006.257.12:05:38.30#ibcon#read 6, iclass 35, count 0 2006.257.12:05:38.30#ibcon#end of sib2, iclass 35, count 0 2006.257.12:05:38.30#ibcon#*mode == 0, iclass 35, count 0 2006.257.12:05:38.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.12:05:38.30#ibcon#[27=USB\r\n] 2006.257.12:05:38.30#ibcon#*before write, iclass 35, count 0 2006.257.12:05:38.30#ibcon#enter sib2, iclass 35, count 0 2006.257.12:05:38.30#ibcon#flushed, iclass 35, count 0 2006.257.12:05:38.30#ibcon#about to write, iclass 35, count 0 2006.257.12:05:38.30#ibcon#wrote, iclass 35, count 0 2006.257.12:05:38.30#ibcon#about to read 3, iclass 35, count 0 2006.257.12:05:38.33#ibcon#read 3, iclass 35, count 0 2006.257.12:05:38.33#ibcon#about to read 4, iclass 35, count 0 2006.257.12:05:38.33#ibcon#read 4, iclass 35, count 0 2006.257.12:05:38.33#ibcon#about to read 5, iclass 35, count 0 2006.257.12:05:38.33#ibcon#read 5, iclass 35, count 0 2006.257.12:05:38.33#ibcon#about to read 6, iclass 35, count 0 2006.257.12:05:38.33#ibcon#read 6, iclass 35, count 0 2006.257.12:05:38.33#ibcon#end of sib2, iclass 35, count 0 2006.257.12:05:38.33#ibcon#*after write, iclass 35, count 0 2006.257.12:05:38.33#ibcon#*before return 0, iclass 35, count 0 2006.257.12:05:38.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:38.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:05:38.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.12:05:38.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.12:05:38.33$vck44/vblo=6,719.99 2006.257.12:05:38.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.12:05:38.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.12:05:38.33#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:38.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:38.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:38.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:38.33#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:05:38.33#ibcon#first serial, iclass 37, count 0 2006.257.12:05:38.33#ibcon#enter sib2, iclass 37, count 0 2006.257.12:05:38.33#ibcon#flushed, iclass 37, count 0 2006.257.12:05:38.33#ibcon#about to write, iclass 37, count 0 2006.257.12:05:38.33#ibcon#wrote, iclass 37, count 0 2006.257.12:05:38.33#ibcon#about to read 3, iclass 37, count 0 2006.257.12:05:38.35#ibcon#read 3, iclass 37, count 0 2006.257.12:05:38.35#ibcon#about to read 4, iclass 37, count 0 2006.257.12:05:38.35#ibcon#read 4, iclass 37, count 0 2006.257.12:05:38.35#ibcon#about to read 5, iclass 37, count 0 2006.257.12:05:38.35#ibcon#read 5, iclass 37, count 0 2006.257.12:05:38.35#ibcon#about to read 6, iclass 37, count 0 2006.257.12:05:38.35#ibcon#read 6, iclass 37, count 0 2006.257.12:05:38.35#ibcon#end of sib2, iclass 37, count 0 2006.257.12:05:38.35#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:05:38.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:05:38.35#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:05:38.35#ibcon#*before write, iclass 37, count 0 2006.257.12:05:38.35#ibcon#enter sib2, iclass 37, count 0 2006.257.12:05:38.35#ibcon#flushed, iclass 37, count 0 2006.257.12:05:38.35#ibcon#about to write, iclass 37, count 0 2006.257.12:05:38.35#ibcon#wrote, iclass 37, count 0 2006.257.12:05:38.35#ibcon#about to read 3, iclass 37, count 0 2006.257.12:05:38.39#ibcon#read 3, iclass 37, count 0 2006.257.12:05:38.39#ibcon#about to read 4, iclass 37, count 0 2006.257.12:05:38.39#ibcon#read 4, iclass 37, count 0 2006.257.12:05:38.39#ibcon#about to read 5, iclass 37, count 0 2006.257.12:05:38.39#ibcon#read 5, iclass 37, count 0 2006.257.12:05:38.39#ibcon#about to read 6, iclass 37, count 0 2006.257.12:05:38.39#ibcon#read 6, iclass 37, count 0 2006.257.12:05:38.39#ibcon#end of sib2, iclass 37, count 0 2006.257.12:05:38.39#ibcon#*after write, iclass 37, count 0 2006.257.12:05:38.39#ibcon#*before return 0, iclass 37, count 0 2006.257.12:05:38.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:38.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:05:38.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:05:38.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:05:38.39$vck44/vb=6,4 2006.257.12:05:38.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.12:05:38.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.12:05:38.39#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:38.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:38.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:38.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:38.45#ibcon#enter wrdev, iclass 39, count 2 2006.257.12:05:38.45#ibcon#first serial, iclass 39, count 2 2006.257.12:05:38.45#ibcon#enter sib2, iclass 39, count 2 2006.257.12:05:38.45#ibcon#flushed, iclass 39, count 2 2006.257.12:05:38.45#ibcon#about to write, iclass 39, count 2 2006.257.12:05:38.45#ibcon#wrote, iclass 39, count 2 2006.257.12:05:38.45#ibcon#about to read 3, iclass 39, count 2 2006.257.12:05:38.47#ibcon#read 3, iclass 39, count 2 2006.257.12:05:38.47#ibcon#about to read 4, iclass 39, count 2 2006.257.12:05:38.47#ibcon#read 4, iclass 39, count 2 2006.257.12:05:38.47#ibcon#about to read 5, iclass 39, count 2 2006.257.12:05:38.47#ibcon#read 5, iclass 39, count 2 2006.257.12:05:38.47#ibcon#about to read 6, iclass 39, count 2 2006.257.12:05:38.47#ibcon#read 6, iclass 39, count 2 2006.257.12:05:38.47#ibcon#end of sib2, iclass 39, count 2 2006.257.12:05:38.47#ibcon#*mode == 0, iclass 39, count 2 2006.257.12:05:38.47#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.12:05:38.47#ibcon#[27=AT06-04\r\n] 2006.257.12:05:38.47#ibcon#*before write, iclass 39, count 2 2006.257.12:05:38.47#ibcon#enter sib2, iclass 39, count 2 2006.257.12:05:38.47#ibcon#flushed, iclass 39, count 2 2006.257.12:05:38.47#ibcon#about to write, iclass 39, count 2 2006.257.12:05:38.47#ibcon#wrote, iclass 39, count 2 2006.257.12:05:38.47#ibcon#about to read 3, iclass 39, count 2 2006.257.12:05:38.50#ibcon#read 3, iclass 39, count 2 2006.257.12:05:38.50#ibcon#about to read 4, iclass 39, count 2 2006.257.12:05:38.50#ibcon#read 4, iclass 39, count 2 2006.257.12:05:38.50#ibcon#about to read 5, iclass 39, count 2 2006.257.12:05:38.50#ibcon#read 5, iclass 39, count 2 2006.257.12:05:38.50#ibcon#about to read 6, iclass 39, count 2 2006.257.12:05:38.50#ibcon#read 6, iclass 39, count 2 2006.257.12:05:38.50#ibcon#end of sib2, iclass 39, count 2 2006.257.12:05:38.50#ibcon#*after write, iclass 39, count 2 2006.257.12:05:38.50#ibcon#*before return 0, iclass 39, count 2 2006.257.12:05:38.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:38.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:05:38.50#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.12:05:38.50#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:38.50#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:38.62#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:38.62#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:38.62#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:05:38.62#ibcon#first serial, iclass 39, count 0 2006.257.12:05:38.62#ibcon#enter sib2, iclass 39, count 0 2006.257.12:05:38.62#ibcon#flushed, iclass 39, count 0 2006.257.12:05:38.62#ibcon#about to write, iclass 39, count 0 2006.257.12:05:38.62#ibcon#wrote, iclass 39, count 0 2006.257.12:05:38.62#ibcon#about to read 3, iclass 39, count 0 2006.257.12:05:38.64#ibcon#read 3, iclass 39, count 0 2006.257.12:05:38.64#ibcon#about to read 4, iclass 39, count 0 2006.257.12:05:38.64#ibcon#read 4, iclass 39, count 0 2006.257.12:05:38.64#ibcon#about to read 5, iclass 39, count 0 2006.257.12:05:38.64#ibcon#read 5, iclass 39, count 0 2006.257.12:05:38.64#ibcon#about to read 6, iclass 39, count 0 2006.257.12:05:38.64#ibcon#read 6, iclass 39, count 0 2006.257.12:05:38.64#ibcon#end of sib2, iclass 39, count 0 2006.257.12:05:38.64#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:05:38.64#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:05:38.64#ibcon#[27=USB\r\n] 2006.257.12:05:38.64#ibcon#*before write, iclass 39, count 0 2006.257.12:05:38.64#ibcon#enter sib2, iclass 39, count 0 2006.257.12:05:38.64#ibcon#flushed, iclass 39, count 0 2006.257.12:05:38.64#ibcon#about to write, iclass 39, count 0 2006.257.12:05:38.64#ibcon#wrote, iclass 39, count 0 2006.257.12:05:38.64#ibcon#about to read 3, iclass 39, count 0 2006.257.12:05:38.67#ibcon#read 3, iclass 39, count 0 2006.257.12:05:38.67#ibcon#about to read 4, iclass 39, count 0 2006.257.12:05:38.67#ibcon#read 4, iclass 39, count 0 2006.257.12:05:38.67#ibcon#about to read 5, iclass 39, count 0 2006.257.12:05:38.67#ibcon#read 5, iclass 39, count 0 2006.257.12:05:38.67#ibcon#about to read 6, iclass 39, count 0 2006.257.12:05:38.67#ibcon#read 6, iclass 39, count 0 2006.257.12:05:38.67#ibcon#end of sib2, iclass 39, count 0 2006.257.12:05:38.67#ibcon#*after write, iclass 39, count 0 2006.257.12:05:38.67#ibcon#*before return 0, iclass 39, count 0 2006.257.12:05:38.67#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:38.67#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:05:38.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:05:38.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:05:38.67$vck44/vblo=7,734.99 2006.257.12:05:38.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.12:05:38.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.12:05:38.67#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:38.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:38.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:38.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:38.67#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:05:38.67#ibcon#first serial, iclass 3, count 0 2006.257.12:05:38.67#ibcon#enter sib2, iclass 3, count 0 2006.257.12:05:38.67#ibcon#flushed, iclass 3, count 0 2006.257.12:05:38.67#ibcon#about to write, iclass 3, count 0 2006.257.12:05:38.67#ibcon#wrote, iclass 3, count 0 2006.257.12:05:38.67#ibcon#about to read 3, iclass 3, count 0 2006.257.12:05:38.69#ibcon#read 3, iclass 3, count 0 2006.257.12:05:38.69#ibcon#about to read 4, iclass 3, count 0 2006.257.12:05:38.69#ibcon#read 4, iclass 3, count 0 2006.257.12:05:38.69#ibcon#about to read 5, iclass 3, count 0 2006.257.12:05:38.69#ibcon#read 5, iclass 3, count 0 2006.257.12:05:38.69#ibcon#about to read 6, iclass 3, count 0 2006.257.12:05:38.69#ibcon#read 6, iclass 3, count 0 2006.257.12:05:38.69#ibcon#end of sib2, iclass 3, count 0 2006.257.12:05:38.69#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:05:38.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:05:38.69#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:05:38.69#ibcon#*before write, iclass 3, count 0 2006.257.12:05:38.69#ibcon#enter sib2, iclass 3, count 0 2006.257.12:05:38.69#ibcon#flushed, iclass 3, count 0 2006.257.12:05:38.69#ibcon#about to write, iclass 3, count 0 2006.257.12:05:38.69#ibcon#wrote, iclass 3, count 0 2006.257.12:05:38.69#ibcon#about to read 3, iclass 3, count 0 2006.257.12:05:38.73#ibcon#read 3, iclass 3, count 0 2006.257.12:05:38.73#ibcon#about to read 4, iclass 3, count 0 2006.257.12:05:38.73#ibcon#read 4, iclass 3, count 0 2006.257.12:05:38.73#ibcon#about to read 5, iclass 3, count 0 2006.257.12:05:38.73#ibcon#read 5, iclass 3, count 0 2006.257.12:05:38.73#ibcon#about to read 6, iclass 3, count 0 2006.257.12:05:38.73#ibcon#read 6, iclass 3, count 0 2006.257.12:05:38.73#ibcon#end of sib2, iclass 3, count 0 2006.257.12:05:38.73#ibcon#*after write, iclass 3, count 0 2006.257.12:05:38.73#ibcon#*before return 0, iclass 3, count 0 2006.257.12:05:38.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:38.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:05:38.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:05:38.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:05:38.73$vck44/vb=7,4 2006.257.12:05:38.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.12:05:38.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.12:05:38.73#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:38.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:38.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:38.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:38.79#ibcon#enter wrdev, iclass 5, count 2 2006.257.12:05:38.79#ibcon#first serial, iclass 5, count 2 2006.257.12:05:38.79#ibcon#enter sib2, iclass 5, count 2 2006.257.12:05:38.79#ibcon#flushed, iclass 5, count 2 2006.257.12:05:38.79#ibcon#about to write, iclass 5, count 2 2006.257.12:05:38.79#ibcon#wrote, iclass 5, count 2 2006.257.12:05:38.79#ibcon#about to read 3, iclass 5, count 2 2006.257.12:05:38.81#ibcon#read 3, iclass 5, count 2 2006.257.12:05:38.81#ibcon#about to read 4, iclass 5, count 2 2006.257.12:05:38.81#ibcon#read 4, iclass 5, count 2 2006.257.12:05:38.81#ibcon#about to read 5, iclass 5, count 2 2006.257.12:05:38.81#ibcon#read 5, iclass 5, count 2 2006.257.12:05:38.81#ibcon#about to read 6, iclass 5, count 2 2006.257.12:05:38.81#ibcon#read 6, iclass 5, count 2 2006.257.12:05:38.81#ibcon#end of sib2, iclass 5, count 2 2006.257.12:05:38.81#ibcon#*mode == 0, iclass 5, count 2 2006.257.12:05:38.81#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.12:05:38.81#ibcon#[27=AT07-04\r\n] 2006.257.12:05:38.81#ibcon#*before write, iclass 5, count 2 2006.257.12:05:38.81#ibcon#enter sib2, iclass 5, count 2 2006.257.12:05:38.81#ibcon#flushed, iclass 5, count 2 2006.257.12:05:38.81#ibcon#about to write, iclass 5, count 2 2006.257.12:05:38.81#ibcon#wrote, iclass 5, count 2 2006.257.12:05:38.81#ibcon#about to read 3, iclass 5, count 2 2006.257.12:05:38.84#ibcon#read 3, iclass 5, count 2 2006.257.12:05:38.84#ibcon#about to read 4, iclass 5, count 2 2006.257.12:05:38.84#ibcon#read 4, iclass 5, count 2 2006.257.12:05:38.84#ibcon#about to read 5, iclass 5, count 2 2006.257.12:05:38.84#ibcon#read 5, iclass 5, count 2 2006.257.12:05:38.84#ibcon#about to read 6, iclass 5, count 2 2006.257.12:05:38.84#ibcon#read 6, iclass 5, count 2 2006.257.12:05:38.84#ibcon#end of sib2, iclass 5, count 2 2006.257.12:05:38.84#ibcon#*after write, iclass 5, count 2 2006.257.12:05:38.84#ibcon#*before return 0, iclass 5, count 2 2006.257.12:05:38.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:38.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:05:38.84#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.12:05:38.84#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:38.84#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:38.96#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:38.96#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:38.96#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:05:38.96#ibcon#first serial, iclass 5, count 0 2006.257.12:05:38.96#ibcon#enter sib2, iclass 5, count 0 2006.257.12:05:38.96#ibcon#flushed, iclass 5, count 0 2006.257.12:05:38.96#ibcon#about to write, iclass 5, count 0 2006.257.12:05:38.96#ibcon#wrote, iclass 5, count 0 2006.257.12:05:38.96#ibcon#about to read 3, iclass 5, count 0 2006.257.12:05:38.98#ibcon#read 3, iclass 5, count 0 2006.257.12:05:38.98#ibcon#about to read 4, iclass 5, count 0 2006.257.12:05:38.98#ibcon#read 4, iclass 5, count 0 2006.257.12:05:38.98#ibcon#about to read 5, iclass 5, count 0 2006.257.12:05:38.98#ibcon#read 5, iclass 5, count 0 2006.257.12:05:38.98#ibcon#about to read 6, iclass 5, count 0 2006.257.12:05:38.98#ibcon#read 6, iclass 5, count 0 2006.257.12:05:38.98#ibcon#end of sib2, iclass 5, count 0 2006.257.12:05:38.98#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:05:38.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:05:38.98#ibcon#[27=USB\r\n] 2006.257.12:05:38.98#ibcon#*before write, iclass 5, count 0 2006.257.12:05:38.98#ibcon#enter sib2, iclass 5, count 0 2006.257.12:05:38.98#ibcon#flushed, iclass 5, count 0 2006.257.12:05:38.98#ibcon#about to write, iclass 5, count 0 2006.257.12:05:38.98#ibcon#wrote, iclass 5, count 0 2006.257.12:05:38.98#ibcon#about to read 3, iclass 5, count 0 2006.257.12:05:39.01#ibcon#read 3, iclass 5, count 0 2006.257.12:05:39.01#ibcon#about to read 4, iclass 5, count 0 2006.257.12:05:39.01#ibcon#read 4, iclass 5, count 0 2006.257.12:05:39.01#ibcon#about to read 5, iclass 5, count 0 2006.257.12:05:39.01#ibcon#read 5, iclass 5, count 0 2006.257.12:05:39.01#ibcon#about to read 6, iclass 5, count 0 2006.257.12:05:39.01#ibcon#read 6, iclass 5, count 0 2006.257.12:05:39.01#ibcon#end of sib2, iclass 5, count 0 2006.257.12:05:39.01#ibcon#*after write, iclass 5, count 0 2006.257.12:05:39.01#ibcon#*before return 0, iclass 5, count 0 2006.257.12:05:39.01#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:39.01#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:05:39.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:05:39.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:05:39.01$vck44/vblo=8,744.99 2006.257.12:05:39.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.12:05:39.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.12:05:39.01#ibcon#ireg 17 cls_cnt 0 2006.257.12:05:39.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:39.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:39.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:39.01#ibcon#enter wrdev, iclass 7, count 0 2006.257.12:05:39.01#ibcon#first serial, iclass 7, count 0 2006.257.12:05:39.01#ibcon#enter sib2, iclass 7, count 0 2006.257.12:05:39.01#ibcon#flushed, iclass 7, count 0 2006.257.12:05:39.01#ibcon#about to write, iclass 7, count 0 2006.257.12:05:39.01#ibcon#wrote, iclass 7, count 0 2006.257.12:05:39.01#ibcon#about to read 3, iclass 7, count 0 2006.257.12:05:39.03#ibcon#read 3, iclass 7, count 0 2006.257.12:05:39.03#ibcon#about to read 4, iclass 7, count 0 2006.257.12:05:39.03#ibcon#read 4, iclass 7, count 0 2006.257.12:05:39.03#ibcon#about to read 5, iclass 7, count 0 2006.257.12:05:39.03#ibcon#read 5, iclass 7, count 0 2006.257.12:05:39.03#ibcon#about to read 6, iclass 7, count 0 2006.257.12:05:39.03#ibcon#read 6, iclass 7, count 0 2006.257.12:05:39.03#ibcon#end of sib2, iclass 7, count 0 2006.257.12:05:39.03#ibcon#*mode == 0, iclass 7, count 0 2006.257.12:05:39.03#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.12:05:39.03#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:05:39.03#ibcon#*before write, iclass 7, count 0 2006.257.12:05:39.03#ibcon#enter sib2, iclass 7, count 0 2006.257.12:05:39.03#ibcon#flushed, iclass 7, count 0 2006.257.12:05:39.03#ibcon#about to write, iclass 7, count 0 2006.257.12:05:39.03#ibcon#wrote, iclass 7, count 0 2006.257.12:05:39.03#ibcon#about to read 3, iclass 7, count 0 2006.257.12:05:39.07#ibcon#read 3, iclass 7, count 0 2006.257.12:05:39.07#ibcon#about to read 4, iclass 7, count 0 2006.257.12:05:39.07#ibcon#read 4, iclass 7, count 0 2006.257.12:05:39.07#ibcon#about to read 5, iclass 7, count 0 2006.257.12:05:39.07#ibcon#read 5, iclass 7, count 0 2006.257.12:05:39.07#ibcon#about to read 6, iclass 7, count 0 2006.257.12:05:39.07#ibcon#read 6, iclass 7, count 0 2006.257.12:05:39.07#ibcon#end of sib2, iclass 7, count 0 2006.257.12:05:39.07#ibcon#*after write, iclass 7, count 0 2006.257.12:05:39.07#ibcon#*before return 0, iclass 7, count 0 2006.257.12:05:39.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:39.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:05:39.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.12:05:39.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.12:05:39.07$vck44/vb=8,4 2006.257.12:05:39.07#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.12:05:39.07#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.12:05:39.07#ibcon#ireg 11 cls_cnt 2 2006.257.12:05:39.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:39.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:39.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:39.13#ibcon#enter wrdev, iclass 11, count 2 2006.257.12:05:39.13#ibcon#first serial, iclass 11, count 2 2006.257.12:05:39.13#ibcon#enter sib2, iclass 11, count 2 2006.257.12:05:39.13#ibcon#flushed, iclass 11, count 2 2006.257.12:05:39.13#ibcon#about to write, iclass 11, count 2 2006.257.12:05:39.13#ibcon#wrote, iclass 11, count 2 2006.257.12:05:39.13#ibcon#about to read 3, iclass 11, count 2 2006.257.12:05:39.15#ibcon#read 3, iclass 11, count 2 2006.257.12:05:39.15#ibcon#about to read 4, iclass 11, count 2 2006.257.12:05:39.15#ibcon#read 4, iclass 11, count 2 2006.257.12:05:39.15#ibcon#about to read 5, iclass 11, count 2 2006.257.12:05:39.15#ibcon#read 5, iclass 11, count 2 2006.257.12:05:39.15#ibcon#about to read 6, iclass 11, count 2 2006.257.12:05:39.15#ibcon#read 6, iclass 11, count 2 2006.257.12:05:39.15#ibcon#end of sib2, iclass 11, count 2 2006.257.12:05:39.15#ibcon#*mode == 0, iclass 11, count 2 2006.257.12:05:39.15#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.12:05:39.15#ibcon#[27=AT08-04\r\n] 2006.257.12:05:39.15#ibcon#*before write, iclass 11, count 2 2006.257.12:05:39.15#ibcon#enter sib2, iclass 11, count 2 2006.257.12:05:39.15#ibcon#flushed, iclass 11, count 2 2006.257.12:05:39.15#ibcon#about to write, iclass 11, count 2 2006.257.12:05:39.15#ibcon#wrote, iclass 11, count 2 2006.257.12:05:39.15#ibcon#about to read 3, iclass 11, count 2 2006.257.12:05:39.18#ibcon#read 3, iclass 11, count 2 2006.257.12:05:39.18#ibcon#about to read 4, iclass 11, count 2 2006.257.12:05:39.18#ibcon#read 4, iclass 11, count 2 2006.257.12:05:39.18#ibcon#about to read 5, iclass 11, count 2 2006.257.12:05:39.18#ibcon#read 5, iclass 11, count 2 2006.257.12:05:39.18#ibcon#about to read 6, iclass 11, count 2 2006.257.12:05:39.18#ibcon#read 6, iclass 11, count 2 2006.257.12:05:39.18#ibcon#end of sib2, iclass 11, count 2 2006.257.12:05:39.18#ibcon#*after write, iclass 11, count 2 2006.257.12:05:39.18#ibcon#*before return 0, iclass 11, count 2 2006.257.12:05:39.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:39.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:05:39.18#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.12:05:39.18#ibcon#ireg 7 cls_cnt 0 2006.257.12:05:39.18#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:39.30#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:39.30#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:39.30#ibcon#enter wrdev, iclass 11, count 0 2006.257.12:05:39.30#ibcon#first serial, iclass 11, count 0 2006.257.12:05:39.30#ibcon#enter sib2, iclass 11, count 0 2006.257.12:05:39.30#ibcon#flushed, iclass 11, count 0 2006.257.12:05:39.30#ibcon#about to write, iclass 11, count 0 2006.257.12:05:39.30#ibcon#wrote, iclass 11, count 0 2006.257.12:05:39.30#ibcon#about to read 3, iclass 11, count 0 2006.257.12:05:39.32#ibcon#read 3, iclass 11, count 0 2006.257.12:05:39.32#ibcon#about to read 4, iclass 11, count 0 2006.257.12:05:39.32#ibcon#read 4, iclass 11, count 0 2006.257.12:05:39.32#ibcon#about to read 5, iclass 11, count 0 2006.257.12:05:39.32#ibcon#read 5, iclass 11, count 0 2006.257.12:05:39.32#ibcon#about to read 6, iclass 11, count 0 2006.257.12:05:39.32#ibcon#read 6, iclass 11, count 0 2006.257.12:05:39.32#ibcon#end of sib2, iclass 11, count 0 2006.257.12:05:39.32#ibcon#*mode == 0, iclass 11, count 0 2006.257.12:05:39.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.12:05:39.32#ibcon#[27=USB\r\n] 2006.257.12:05:39.32#ibcon#*before write, iclass 11, count 0 2006.257.12:05:39.32#ibcon#enter sib2, iclass 11, count 0 2006.257.12:05:39.32#ibcon#flushed, iclass 11, count 0 2006.257.12:05:39.32#ibcon#about to write, iclass 11, count 0 2006.257.12:05:39.32#ibcon#wrote, iclass 11, count 0 2006.257.12:05:39.32#ibcon#about to read 3, iclass 11, count 0 2006.257.12:05:39.35#ibcon#read 3, iclass 11, count 0 2006.257.12:05:39.35#ibcon#about to read 4, iclass 11, count 0 2006.257.12:05:39.35#ibcon#read 4, iclass 11, count 0 2006.257.12:05:39.35#ibcon#about to read 5, iclass 11, count 0 2006.257.12:05:39.35#ibcon#read 5, iclass 11, count 0 2006.257.12:05:39.35#ibcon#about to read 6, iclass 11, count 0 2006.257.12:05:39.35#ibcon#read 6, iclass 11, count 0 2006.257.12:05:39.35#ibcon#end of sib2, iclass 11, count 0 2006.257.12:05:39.35#ibcon#*after write, iclass 11, count 0 2006.257.12:05:39.35#ibcon#*before return 0, iclass 11, count 0 2006.257.12:05:39.35#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:39.35#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:05:39.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.12:05:39.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.12:05:39.35$vck44/vabw=wide 2006.257.12:05:39.35#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.12:05:39.35#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.12:05:39.35#ibcon#ireg 8 cls_cnt 0 2006.257.12:05:39.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:39.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:39.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:39.35#ibcon#enter wrdev, iclass 13, count 0 2006.257.12:05:39.35#ibcon#first serial, iclass 13, count 0 2006.257.12:05:39.35#ibcon#enter sib2, iclass 13, count 0 2006.257.12:05:39.35#ibcon#flushed, iclass 13, count 0 2006.257.12:05:39.35#ibcon#about to write, iclass 13, count 0 2006.257.12:05:39.35#ibcon#wrote, iclass 13, count 0 2006.257.12:05:39.35#ibcon#about to read 3, iclass 13, count 0 2006.257.12:05:39.37#ibcon#read 3, iclass 13, count 0 2006.257.12:05:39.37#ibcon#about to read 4, iclass 13, count 0 2006.257.12:05:39.37#ibcon#read 4, iclass 13, count 0 2006.257.12:05:39.37#ibcon#about to read 5, iclass 13, count 0 2006.257.12:05:39.37#ibcon#read 5, iclass 13, count 0 2006.257.12:05:39.37#ibcon#about to read 6, iclass 13, count 0 2006.257.12:05:39.37#ibcon#read 6, iclass 13, count 0 2006.257.12:05:39.37#ibcon#end of sib2, iclass 13, count 0 2006.257.12:05:39.37#ibcon#*mode == 0, iclass 13, count 0 2006.257.12:05:39.37#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.12:05:39.37#ibcon#[25=BW32\r\n] 2006.257.12:05:39.37#ibcon#*before write, iclass 13, count 0 2006.257.12:05:39.37#ibcon#enter sib2, iclass 13, count 0 2006.257.12:05:39.37#ibcon#flushed, iclass 13, count 0 2006.257.12:05:39.37#ibcon#about to write, iclass 13, count 0 2006.257.12:05:39.37#ibcon#wrote, iclass 13, count 0 2006.257.12:05:39.37#ibcon#about to read 3, iclass 13, count 0 2006.257.12:05:39.40#ibcon#read 3, iclass 13, count 0 2006.257.12:05:39.40#ibcon#about to read 4, iclass 13, count 0 2006.257.12:05:39.40#ibcon#read 4, iclass 13, count 0 2006.257.12:05:39.40#ibcon#about to read 5, iclass 13, count 0 2006.257.12:05:39.40#ibcon#read 5, iclass 13, count 0 2006.257.12:05:39.40#ibcon#about to read 6, iclass 13, count 0 2006.257.12:05:39.40#ibcon#read 6, iclass 13, count 0 2006.257.12:05:39.40#ibcon#end of sib2, iclass 13, count 0 2006.257.12:05:39.40#ibcon#*after write, iclass 13, count 0 2006.257.12:05:39.40#ibcon#*before return 0, iclass 13, count 0 2006.257.12:05:39.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:39.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:05:39.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.12:05:39.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.12:05:39.40$vck44/vbbw=wide 2006.257.12:05:39.40#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.12:05:39.40#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.12:05:39.40#ibcon#ireg 8 cls_cnt 0 2006.257.12:05:39.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:05:39.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:05:39.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:05:39.47#ibcon#enter wrdev, iclass 15, count 0 2006.257.12:05:39.47#ibcon#first serial, iclass 15, count 0 2006.257.12:05:39.47#ibcon#enter sib2, iclass 15, count 0 2006.257.12:05:39.47#ibcon#flushed, iclass 15, count 0 2006.257.12:05:39.47#ibcon#about to write, iclass 15, count 0 2006.257.12:05:39.47#ibcon#wrote, iclass 15, count 0 2006.257.12:05:39.47#ibcon#about to read 3, iclass 15, count 0 2006.257.12:05:39.49#ibcon#read 3, iclass 15, count 0 2006.257.12:05:39.49#ibcon#about to read 4, iclass 15, count 0 2006.257.12:05:39.49#ibcon#read 4, iclass 15, count 0 2006.257.12:05:39.49#ibcon#about to read 5, iclass 15, count 0 2006.257.12:05:39.49#ibcon#read 5, iclass 15, count 0 2006.257.12:05:39.49#ibcon#about to read 6, iclass 15, count 0 2006.257.12:05:39.49#ibcon#read 6, iclass 15, count 0 2006.257.12:05:39.49#ibcon#end of sib2, iclass 15, count 0 2006.257.12:05:39.49#ibcon#*mode == 0, iclass 15, count 0 2006.257.12:05:39.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.12:05:39.49#ibcon#[27=BW32\r\n] 2006.257.12:05:39.49#ibcon#*before write, iclass 15, count 0 2006.257.12:05:39.49#ibcon#enter sib2, iclass 15, count 0 2006.257.12:05:39.49#ibcon#flushed, iclass 15, count 0 2006.257.12:05:39.49#ibcon#about to write, iclass 15, count 0 2006.257.12:05:39.49#ibcon#wrote, iclass 15, count 0 2006.257.12:05:39.49#ibcon#about to read 3, iclass 15, count 0 2006.257.12:05:39.52#ibcon#read 3, iclass 15, count 0 2006.257.12:05:39.52#ibcon#about to read 4, iclass 15, count 0 2006.257.12:05:39.52#ibcon#read 4, iclass 15, count 0 2006.257.12:05:39.52#ibcon#about to read 5, iclass 15, count 0 2006.257.12:05:39.52#ibcon#read 5, iclass 15, count 0 2006.257.12:05:39.52#ibcon#about to read 6, iclass 15, count 0 2006.257.12:05:39.52#ibcon#read 6, iclass 15, count 0 2006.257.12:05:39.52#ibcon#end of sib2, iclass 15, count 0 2006.257.12:05:39.52#ibcon#*after write, iclass 15, count 0 2006.257.12:05:39.52#ibcon#*before return 0, iclass 15, count 0 2006.257.12:05:39.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:05:39.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:05:39.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.12:05:39.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.12:05:39.52$setupk4/ifdk4 2006.257.12:05:39.52$ifdk4/lo= 2006.257.12:05:39.53$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:05:39.53$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:05:39.53$ifdk4/patch= 2006.257.12:05:39.53$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:05:39.53$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:05:39.53$setupk4/!*+20s 2006.257.12:05:47.35#abcon#<5=/14 1.4 3.4 18.19 951013.9\r\n> 2006.257.12:05:47.37#abcon#{5=INTERFACE CLEAR} 2006.257.12:05:47.43#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:05:54.04$setupk4/"tpicd 2006.257.12:05:54.04$setupk4/echo=off 2006.257.12:05:54.04$setupk4/xlog=off 2006.257.12:05:54.04:!2006.257.12:08:06 2006.257.12:06:11.13#trakl#Source acquired 2006.257.12:06:12.13#flagr#flagr/antenna,acquired 2006.257.12:08:06.00:preob 2006.257.12:08:07.14/onsource/TRACKING 2006.257.12:08:07.14:!2006.257.12:08:16 2006.257.12:08:16.00:"tape 2006.257.12:08:16.00:"st=record 2006.257.12:08:16.00:data_valid=on 2006.257.12:08:16.00:midob 2006.257.12:08:16.14/onsource/TRACKING 2006.257.12:08:16.14/wx/18.18,1014.0,95 2006.257.12:08:16.22/cable/+6.4797E-03 2006.257.12:08:17.31/va/01,08,usb,yes,32,34 2006.257.12:08:17.31/va/02,07,usb,yes,35,35 2006.257.12:08:17.31/va/03,08,usb,yes,31,33 2006.257.12:08:17.31/va/04,07,usb,yes,36,37 2006.257.12:08:17.31/va/05,04,usb,yes,32,32 2006.257.12:08:17.31/va/06,04,usb,yes,36,35 2006.257.12:08:17.31/va/07,04,usb,yes,36,37 2006.257.12:08:17.31/va/08,04,usb,yes,30,37 2006.257.12:08:17.54/valo/01,524.99,yes,locked 2006.257.12:08:17.54/valo/02,534.99,yes,locked 2006.257.12:08:17.54/valo/03,564.99,yes,locked 2006.257.12:08:17.54/valo/04,624.99,yes,locked 2006.257.12:08:17.54/valo/05,734.99,yes,locked 2006.257.12:08:17.54/valo/06,814.99,yes,locked 2006.257.12:08:17.54/valo/07,864.99,yes,locked 2006.257.12:08:17.54/valo/08,884.99,yes,locked 2006.257.12:08:18.63/vb/01,04,usb,yes,31,29 2006.257.12:08:18.63/vb/02,05,usb,yes,30,30 2006.257.12:08:18.63/vb/03,04,usb,yes,31,34 2006.257.12:08:18.63/vb/04,05,usb,yes,31,30 2006.257.12:08:18.63/vb/05,04,usb,yes,27,30 2006.257.12:08:18.63/vb/06,04,usb,yes,32,28 2006.257.12:08:18.63/vb/07,04,usb,yes,32,32 2006.257.12:08:18.63/vb/08,04,usb,yes,29,33 2006.257.12:08:18.87/vblo/01,629.99,yes,locked 2006.257.12:08:18.87/vblo/02,634.99,yes,locked 2006.257.12:08:18.87/vblo/03,649.99,yes,locked 2006.257.12:08:18.87/vblo/04,679.99,yes,locked 2006.257.12:08:18.87/vblo/05,709.99,yes,locked 2006.257.12:08:18.87/vblo/06,719.99,yes,locked 2006.257.12:08:18.87/vblo/07,734.99,yes,locked 2006.257.12:08:18.87/vblo/08,744.99,yes,locked 2006.257.12:08:19.02/vabw/8 2006.257.12:08:19.17/vbbw/8 2006.257.12:08:19.26/xfe/off,on,15.5 2006.257.12:08:19.64/ifatt/23,28,28,28 2006.257.12:08:20.07/fmout-gps/S +4.60E-07 2006.257.12:08:20.11:!2006.257.12:14:36 2006.257.12:14:36.00:data_valid=off 2006.257.12:14:36.01:"et 2006.257.12:14:36.01:!+3s 2006.257.12:14:39.02:"tape 2006.257.12:14:39.03:postob 2006.257.12:14:39.08/cable/+6.4782E-03 2006.257.12:14:39.09/wx/18.16,1014.0,95 2006.257.12:14:39.14/fmout-gps/S +4.60E-07 2006.257.12:14:39.15:scan_name=257-1221,jd0609,70 2006.257.12:14:39.15:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.12:14:40.13#flagr#flagr/antenna,new-source 2006.257.12:14:40.14:checkk5 2006.257.12:14:40.58/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:14:40.99/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:14:41.40/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:14:41.82/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:14:42.20/chk_obsdata//k5ts1/T2571208??a.dat file size is correct (nominal:1520MB, actual:1516MB). 2006.257.12:14:42.61/chk_obsdata//k5ts2/T2571208??b.dat file size is correct (nominal:1520MB, actual:1516MB). 2006.257.12:14:43.01/chk_obsdata//k5ts3/T2571208??c.dat file size is correct (nominal:1520MB, actual:1516MB). 2006.257.12:14:43.41/chk_obsdata//k5ts4/T2571208??d.dat file size is correct (nominal:1520MB, actual:1516MB). 2006.257.12:14:44.14/k5log//k5ts1_log_newline 2006.257.12:14:44.84/k5log//k5ts2_log_newline 2006.257.12:14:45.57/k5log//k5ts3_log_newline 2006.257.12:14:46.28/k5log//k5ts4_log_newline 2006.257.12:14:46.30/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:14:46.30:setupk4=1 2006.257.12:14:46.30$setupk4/echo=on 2006.257.12:14:46.30$setupk4/pcalon 2006.257.12:14:46.30$pcalon/"no phase cal control is implemented here 2006.257.12:14:46.30$setupk4/"tpicd=stop 2006.257.12:14:46.30$setupk4/"rec=synch_on 2006.257.12:14:46.30$setupk4/"rec_mode=128 2006.257.12:14:46.30$setupk4/!* 2006.257.12:14:46.30$setupk4/recpk4 2006.257.12:14:46.30$recpk4/recpatch= 2006.257.12:14:46.30$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:14:46.30$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:14:46.30$setupk4/vck44 2006.257.12:14:46.30$vck44/valo=1,524.99 2006.257.12:14:46.30#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.12:14:46.30#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.12:14:46.30#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:46.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:46.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:46.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:46.30#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:14:46.30#ibcon#first serial, iclass 16, count 0 2006.257.12:14:46.30#ibcon#enter sib2, iclass 16, count 0 2006.257.12:14:46.30#ibcon#flushed, iclass 16, count 0 2006.257.12:14:46.31#ibcon#about to write, iclass 16, count 0 2006.257.12:14:46.31#ibcon#wrote, iclass 16, count 0 2006.257.12:14:46.31#ibcon#about to read 3, iclass 16, count 0 2006.257.12:14:46.32#ibcon#read 3, iclass 16, count 0 2006.257.12:14:46.32#ibcon#about to read 4, iclass 16, count 0 2006.257.12:14:46.32#ibcon#read 4, iclass 16, count 0 2006.257.12:14:46.32#ibcon#about to read 5, iclass 16, count 0 2006.257.12:14:46.32#ibcon#read 5, iclass 16, count 0 2006.257.12:14:46.32#ibcon#about to read 6, iclass 16, count 0 2006.257.12:14:46.32#ibcon#read 6, iclass 16, count 0 2006.257.12:14:46.32#ibcon#end of sib2, iclass 16, count 0 2006.257.12:14:46.32#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:14:46.32#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:14:46.32#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:14:46.32#ibcon#*before write, iclass 16, count 0 2006.257.12:14:46.32#ibcon#enter sib2, iclass 16, count 0 2006.257.12:14:46.32#ibcon#flushed, iclass 16, count 0 2006.257.12:14:46.32#ibcon#about to write, iclass 16, count 0 2006.257.12:14:46.32#ibcon#wrote, iclass 16, count 0 2006.257.12:14:46.32#ibcon#about to read 3, iclass 16, count 0 2006.257.12:14:46.37#ibcon#read 3, iclass 16, count 0 2006.257.12:14:46.37#ibcon#about to read 4, iclass 16, count 0 2006.257.12:14:46.37#ibcon#read 4, iclass 16, count 0 2006.257.12:14:46.37#ibcon#about to read 5, iclass 16, count 0 2006.257.12:14:46.37#ibcon#read 5, iclass 16, count 0 2006.257.12:14:46.37#ibcon#about to read 6, iclass 16, count 0 2006.257.12:14:46.37#ibcon#read 6, iclass 16, count 0 2006.257.12:14:46.37#ibcon#end of sib2, iclass 16, count 0 2006.257.12:14:46.37#ibcon#*after write, iclass 16, count 0 2006.257.12:14:46.37#ibcon#*before return 0, iclass 16, count 0 2006.257.12:14:46.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:46.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:46.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:14:46.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:14:46.37$vck44/va=1,8 2006.257.12:14:46.37#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.12:14:46.37#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.12:14:46.37#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:46.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:46.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:46.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:46.37#ibcon#enter wrdev, iclass 18, count 2 2006.257.12:14:46.37#ibcon#first serial, iclass 18, count 2 2006.257.12:14:46.37#ibcon#enter sib2, iclass 18, count 2 2006.257.12:14:46.37#ibcon#flushed, iclass 18, count 2 2006.257.12:14:46.37#ibcon#about to write, iclass 18, count 2 2006.257.12:14:46.37#ibcon#wrote, iclass 18, count 2 2006.257.12:14:46.37#ibcon#about to read 3, iclass 18, count 2 2006.257.12:14:46.39#ibcon#read 3, iclass 18, count 2 2006.257.12:14:46.39#ibcon#about to read 4, iclass 18, count 2 2006.257.12:14:46.39#ibcon#read 4, iclass 18, count 2 2006.257.12:14:46.39#ibcon#about to read 5, iclass 18, count 2 2006.257.12:14:46.39#ibcon#read 5, iclass 18, count 2 2006.257.12:14:46.39#ibcon#about to read 6, iclass 18, count 2 2006.257.12:14:46.39#ibcon#read 6, iclass 18, count 2 2006.257.12:14:46.39#ibcon#end of sib2, iclass 18, count 2 2006.257.12:14:46.39#ibcon#*mode == 0, iclass 18, count 2 2006.257.12:14:46.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.12:14:46.39#ibcon#[25=AT01-08\r\n] 2006.257.12:14:46.39#ibcon#*before write, iclass 18, count 2 2006.257.12:14:46.39#ibcon#enter sib2, iclass 18, count 2 2006.257.12:14:46.39#ibcon#flushed, iclass 18, count 2 2006.257.12:14:46.39#ibcon#about to write, iclass 18, count 2 2006.257.12:14:46.39#ibcon#wrote, iclass 18, count 2 2006.257.12:14:46.39#ibcon#about to read 3, iclass 18, count 2 2006.257.12:14:46.42#ibcon#read 3, iclass 18, count 2 2006.257.12:14:46.42#ibcon#about to read 4, iclass 18, count 2 2006.257.12:14:46.42#ibcon#read 4, iclass 18, count 2 2006.257.12:14:46.42#ibcon#about to read 5, iclass 18, count 2 2006.257.12:14:46.42#ibcon#read 5, iclass 18, count 2 2006.257.12:14:46.42#ibcon#about to read 6, iclass 18, count 2 2006.257.12:14:46.42#ibcon#read 6, iclass 18, count 2 2006.257.12:14:46.42#ibcon#end of sib2, iclass 18, count 2 2006.257.12:14:46.42#ibcon#*after write, iclass 18, count 2 2006.257.12:14:46.42#ibcon#*before return 0, iclass 18, count 2 2006.257.12:14:46.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:46.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:46.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.12:14:46.42#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:46.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:46.51#abcon#<5=/14 1.5 3.9 18.16 951014.0\r\n> 2006.257.12:14:46.53#abcon#{5=INTERFACE CLEAR} 2006.257.12:14:46.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:46.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:46.54#ibcon#enter wrdev, iclass 18, count 0 2006.257.12:14:46.54#ibcon#first serial, iclass 18, count 0 2006.257.12:14:46.54#ibcon#enter sib2, iclass 18, count 0 2006.257.12:14:46.54#ibcon#flushed, iclass 18, count 0 2006.257.12:14:46.54#ibcon#about to write, iclass 18, count 0 2006.257.12:14:46.54#ibcon#wrote, iclass 18, count 0 2006.257.12:14:46.54#ibcon#about to read 3, iclass 18, count 0 2006.257.12:14:46.56#ibcon#read 3, iclass 18, count 0 2006.257.12:14:46.56#ibcon#about to read 4, iclass 18, count 0 2006.257.12:14:46.56#ibcon#read 4, iclass 18, count 0 2006.257.12:14:46.56#ibcon#about to read 5, iclass 18, count 0 2006.257.12:14:46.56#ibcon#read 5, iclass 18, count 0 2006.257.12:14:46.56#ibcon#about to read 6, iclass 18, count 0 2006.257.12:14:46.56#ibcon#read 6, iclass 18, count 0 2006.257.12:14:46.56#ibcon#end of sib2, iclass 18, count 0 2006.257.12:14:46.56#ibcon#*mode == 0, iclass 18, count 0 2006.257.12:14:46.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.12:14:46.56#ibcon#[25=USB\r\n] 2006.257.12:14:46.56#ibcon#*before write, iclass 18, count 0 2006.257.12:14:46.56#ibcon#enter sib2, iclass 18, count 0 2006.257.12:14:46.56#ibcon#flushed, iclass 18, count 0 2006.257.12:14:46.56#ibcon#about to write, iclass 18, count 0 2006.257.12:14:46.56#ibcon#wrote, iclass 18, count 0 2006.257.12:14:46.56#ibcon#about to read 3, iclass 18, count 0 2006.257.12:14:46.59#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:14:46.59#ibcon#read 3, iclass 18, count 0 2006.257.12:14:46.59#ibcon#about to read 4, iclass 18, count 0 2006.257.12:14:46.59#ibcon#read 4, iclass 18, count 0 2006.257.12:14:46.59#ibcon#about to read 5, iclass 18, count 0 2006.257.12:14:46.59#ibcon#read 5, iclass 18, count 0 2006.257.12:14:46.59#ibcon#about to read 6, iclass 18, count 0 2006.257.12:14:46.59#ibcon#read 6, iclass 18, count 0 2006.257.12:14:46.59#ibcon#end of sib2, iclass 18, count 0 2006.257.12:14:46.59#ibcon#*after write, iclass 18, count 0 2006.257.12:14:46.59#ibcon#*before return 0, iclass 18, count 0 2006.257.12:14:46.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:46.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:46.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.12:14:46.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.12:14:46.59$vck44/valo=2,534.99 2006.257.12:14:46.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.12:14:46.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.12:14:46.59#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:46.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:46.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:46.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:46.59#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:14:46.59#ibcon#first serial, iclass 24, count 0 2006.257.12:14:46.59#ibcon#enter sib2, iclass 24, count 0 2006.257.12:14:46.59#ibcon#flushed, iclass 24, count 0 2006.257.12:14:46.59#ibcon#about to write, iclass 24, count 0 2006.257.12:14:46.59#ibcon#wrote, iclass 24, count 0 2006.257.12:14:46.59#ibcon#about to read 3, iclass 24, count 0 2006.257.12:14:46.61#ibcon#read 3, iclass 24, count 0 2006.257.12:14:46.61#ibcon#about to read 4, iclass 24, count 0 2006.257.12:14:46.61#ibcon#read 4, iclass 24, count 0 2006.257.12:14:46.61#ibcon#about to read 5, iclass 24, count 0 2006.257.12:14:46.61#ibcon#read 5, iclass 24, count 0 2006.257.12:14:46.61#ibcon#about to read 6, iclass 24, count 0 2006.257.12:14:46.61#ibcon#read 6, iclass 24, count 0 2006.257.12:14:46.61#ibcon#end of sib2, iclass 24, count 0 2006.257.12:14:46.61#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:14:46.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:14:46.61#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:14:46.61#ibcon#*before write, iclass 24, count 0 2006.257.12:14:46.61#ibcon#enter sib2, iclass 24, count 0 2006.257.12:14:46.61#ibcon#flushed, iclass 24, count 0 2006.257.12:14:46.61#ibcon#about to write, iclass 24, count 0 2006.257.12:14:46.61#ibcon#wrote, iclass 24, count 0 2006.257.12:14:46.61#ibcon#about to read 3, iclass 24, count 0 2006.257.12:14:46.65#ibcon#read 3, iclass 24, count 0 2006.257.12:14:46.65#ibcon#about to read 4, iclass 24, count 0 2006.257.12:14:46.65#ibcon#read 4, iclass 24, count 0 2006.257.12:14:46.65#ibcon#about to read 5, iclass 24, count 0 2006.257.12:14:46.65#ibcon#read 5, iclass 24, count 0 2006.257.12:14:46.65#ibcon#about to read 6, iclass 24, count 0 2006.257.12:14:46.65#ibcon#read 6, iclass 24, count 0 2006.257.12:14:46.65#ibcon#end of sib2, iclass 24, count 0 2006.257.12:14:46.65#ibcon#*after write, iclass 24, count 0 2006.257.12:14:46.65#ibcon#*before return 0, iclass 24, count 0 2006.257.12:14:46.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:46.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:46.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:14:46.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:14:46.65$vck44/va=2,7 2006.257.12:14:46.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.12:14:46.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.12:14:46.65#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:46.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:46.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:46.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:46.71#ibcon#enter wrdev, iclass 26, count 2 2006.257.12:14:46.71#ibcon#first serial, iclass 26, count 2 2006.257.12:14:46.71#ibcon#enter sib2, iclass 26, count 2 2006.257.12:14:46.71#ibcon#flushed, iclass 26, count 2 2006.257.12:14:46.71#ibcon#about to write, iclass 26, count 2 2006.257.12:14:46.71#ibcon#wrote, iclass 26, count 2 2006.257.12:14:46.71#ibcon#about to read 3, iclass 26, count 2 2006.257.12:14:46.73#ibcon#read 3, iclass 26, count 2 2006.257.12:14:46.73#ibcon#about to read 4, iclass 26, count 2 2006.257.12:14:46.73#ibcon#read 4, iclass 26, count 2 2006.257.12:14:46.73#ibcon#about to read 5, iclass 26, count 2 2006.257.12:14:46.73#ibcon#read 5, iclass 26, count 2 2006.257.12:14:46.73#ibcon#about to read 6, iclass 26, count 2 2006.257.12:14:46.73#ibcon#read 6, iclass 26, count 2 2006.257.12:14:46.73#ibcon#end of sib2, iclass 26, count 2 2006.257.12:14:46.73#ibcon#*mode == 0, iclass 26, count 2 2006.257.12:14:46.73#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.12:14:46.73#ibcon#[25=AT02-07\r\n] 2006.257.12:14:46.73#ibcon#*before write, iclass 26, count 2 2006.257.12:14:46.73#ibcon#enter sib2, iclass 26, count 2 2006.257.12:14:46.73#ibcon#flushed, iclass 26, count 2 2006.257.12:14:46.73#ibcon#about to write, iclass 26, count 2 2006.257.12:14:46.73#ibcon#wrote, iclass 26, count 2 2006.257.12:14:46.73#ibcon#about to read 3, iclass 26, count 2 2006.257.12:14:46.76#ibcon#read 3, iclass 26, count 2 2006.257.12:14:46.76#ibcon#about to read 4, iclass 26, count 2 2006.257.12:14:46.76#ibcon#read 4, iclass 26, count 2 2006.257.12:14:46.76#ibcon#about to read 5, iclass 26, count 2 2006.257.12:14:46.76#ibcon#read 5, iclass 26, count 2 2006.257.12:14:46.76#ibcon#about to read 6, iclass 26, count 2 2006.257.12:14:46.76#ibcon#read 6, iclass 26, count 2 2006.257.12:14:46.76#ibcon#end of sib2, iclass 26, count 2 2006.257.12:14:46.76#ibcon#*after write, iclass 26, count 2 2006.257.12:14:46.76#ibcon#*before return 0, iclass 26, count 2 2006.257.12:14:46.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:46.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:46.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.12:14:46.76#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:46.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:46.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:46.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:46.88#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:14:46.88#ibcon#first serial, iclass 26, count 0 2006.257.12:14:46.88#ibcon#enter sib2, iclass 26, count 0 2006.257.12:14:46.88#ibcon#flushed, iclass 26, count 0 2006.257.12:14:46.88#ibcon#about to write, iclass 26, count 0 2006.257.12:14:46.88#ibcon#wrote, iclass 26, count 0 2006.257.12:14:46.88#ibcon#about to read 3, iclass 26, count 0 2006.257.12:14:46.90#ibcon#read 3, iclass 26, count 0 2006.257.12:14:46.90#ibcon#about to read 4, iclass 26, count 0 2006.257.12:14:46.90#ibcon#read 4, iclass 26, count 0 2006.257.12:14:46.90#ibcon#about to read 5, iclass 26, count 0 2006.257.12:14:46.90#ibcon#read 5, iclass 26, count 0 2006.257.12:14:46.90#ibcon#about to read 6, iclass 26, count 0 2006.257.12:14:46.90#ibcon#read 6, iclass 26, count 0 2006.257.12:14:46.90#ibcon#end of sib2, iclass 26, count 0 2006.257.12:14:46.90#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:14:46.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:14:46.90#ibcon#[25=USB\r\n] 2006.257.12:14:46.90#ibcon#*before write, iclass 26, count 0 2006.257.12:14:46.90#ibcon#enter sib2, iclass 26, count 0 2006.257.12:14:46.90#ibcon#flushed, iclass 26, count 0 2006.257.12:14:46.90#ibcon#about to write, iclass 26, count 0 2006.257.12:14:46.90#ibcon#wrote, iclass 26, count 0 2006.257.12:14:46.90#ibcon#about to read 3, iclass 26, count 0 2006.257.12:14:46.93#ibcon#read 3, iclass 26, count 0 2006.257.12:14:46.93#ibcon#about to read 4, iclass 26, count 0 2006.257.12:14:46.93#ibcon#read 4, iclass 26, count 0 2006.257.12:14:46.93#ibcon#about to read 5, iclass 26, count 0 2006.257.12:14:46.93#ibcon#read 5, iclass 26, count 0 2006.257.12:14:46.93#ibcon#about to read 6, iclass 26, count 0 2006.257.12:14:46.93#ibcon#read 6, iclass 26, count 0 2006.257.12:14:46.93#ibcon#end of sib2, iclass 26, count 0 2006.257.12:14:46.93#ibcon#*after write, iclass 26, count 0 2006.257.12:14:46.93#ibcon#*before return 0, iclass 26, count 0 2006.257.12:14:46.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:46.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:46.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:14:46.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:14:46.93$vck44/valo=3,564.99 2006.257.12:14:46.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.12:14:46.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.12:14:46.93#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:46.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:46.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:46.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:46.93#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:14:46.93#ibcon#first serial, iclass 28, count 0 2006.257.12:14:46.93#ibcon#enter sib2, iclass 28, count 0 2006.257.12:14:46.93#ibcon#flushed, iclass 28, count 0 2006.257.12:14:46.93#ibcon#about to write, iclass 28, count 0 2006.257.12:14:46.93#ibcon#wrote, iclass 28, count 0 2006.257.12:14:46.93#ibcon#about to read 3, iclass 28, count 0 2006.257.12:14:46.95#ibcon#read 3, iclass 28, count 0 2006.257.12:14:46.95#ibcon#about to read 4, iclass 28, count 0 2006.257.12:14:46.95#ibcon#read 4, iclass 28, count 0 2006.257.12:14:46.95#ibcon#about to read 5, iclass 28, count 0 2006.257.12:14:46.95#ibcon#read 5, iclass 28, count 0 2006.257.12:14:46.95#ibcon#about to read 6, iclass 28, count 0 2006.257.12:14:46.95#ibcon#read 6, iclass 28, count 0 2006.257.12:14:46.95#ibcon#end of sib2, iclass 28, count 0 2006.257.12:14:46.95#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:14:46.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:14:46.95#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:14:46.95#ibcon#*before write, iclass 28, count 0 2006.257.12:14:46.95#ibcon#enter sib2, iclass 28, count 0 2006.257.12:14:46.95#ibcon#flushed, iclass 28, count 0 2006.257.12:14:46.95#ibcon#about to write, iclass 28, count 0 2006.257.12:14:46.95#ibcon#wrote, iclass 28, count 0 2006.257.12:14:46.95#ibcon#about to read 3, iclass 28, count 0 2006.257.12:14:46.99#ibcon#read 3, iclass 28, count 0 2006.257.12:14:46.99#ibcon#about to read 4, iclass 28, count 0 2006.257.12:14:46.99#ibcon#read 4, iclass 28, count 0 2006.257.12:14:46.99#ibcon#about to read 5, iclass 28, count 0 2006.257.12:14:46.99#ibcon#read 5, iclass 28, count 0 2006.257.12:14:46.99#ibcon#about to read 6, iclass 28, count 0 2006.257.12:14:46.99#ibcon#read 6, iclass 28, count 0 2006.257.12:14:46.99#ibcon#end of sib2, iclass 28, count 0 2006.257.12:14:46.99#ibcon#*after write, iclass 28, count 0 2006.257.12:14:46.99#ibcon#*before return 0, iclass 28, count 0 2006.257.12:14:46.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:46.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:46.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:14:46.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:14:46.99$vck44/va=3,8 2006.257.12:14:46.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.12:14:46.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.12:14:46.99#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:46.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:47.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:47.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:47.05#ibcon#enter wrdev, iclass 30, count 2 2006.257.12:14:47.05#ibcon#first serial, iclass 30, count 2 2006.257.12:14:47.05#ibcon#enter sib2, iclass 30, count 2 2006.257.12:14:47.05#ibcon#flushed, iclass 30, count 2 2006.257.12:14:47.05#ibcon#about to write, iclass 30, count 2 2006.257.12:14:47.05#ibcon#wrote, iclass 30, count 2 2006.257.12:14:47.05#ibcon#about to read 3, iclass 30, count 2 2006.257.12:14:47.07#ibcon#read 3, iclass 30, count 2 2006.257.12:14:47.07#ibcon#about to read 4, iclass 30, count 2 2006.257.12:14:47.07#ibcon#read 4, iclass 30, count 2 2006.257.12:14:47.07#ibcon#about to read 5, iclass 30, count 2 2006.257.12:14:47.07#ibcon#read 5, iclass 30, count 2 2006.257.12:14:47.07#ibcon#about to read 6, iclass 30, count 2 2006.257.12:14:47.07#ibcon#read 6, iclass 30, count 2 2006.257.12:14:47.07#ibcon#end of sib2, iclass 30, count 2 2006.257.12:14:47.07#ibcon#*mode == 0, iclass 30, count 2 2006.257.12:14:47.07#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.12:14:47.07#ibcon#[25=AT03-08\r\n] 2006.257.12:14:47.07#ibcon#*before write, iclass 30, count 2 2006.257.12:14:47.07#ibcon#enter sib2, iclass 30, count 2 2006.257.12:14:47.07#ibcon#flushed, iclass 30, count 2 2006.257.12:14:47.07#ibcon#about to write, iclass 30, count 2 2006.257.12:14:47.07#ibcon#wrote, iclass 30, count 2 2006.257.12:14:47.07#ibcon#about to read 3, iclass 30, count 2 2006.257.12:14:47.10#ibcon#read 3, iclass 30, count 2 2006.257.12:14:47.10#ibcon#about to read 4, iclass 30, count 2 2006.257.12:14:47.10#ibcon#read 4, iclass 30, count 2 2006.257.12:14:47.10#ibcon#about to read 5, iclass 30, count 2 2006.257.12:14:47.10#ibcon#read 5, iclass 30, count 2 2006.257.12:14:47.10#ibcon#about to read 6, iclass 30, count 2 2006.257.12:14:47.10#ibcon#read 6, iclass 30, count 2 2006.257.12:14:47.10#ibcon#end of sib2, iclass 30, count 2 2006.257.12:14:47.10#ibcon#*after write, iclass 30, count 2 2006.257.12:14:47.10#ibcon#*before return 0, iclass 30, count 2 2006.257.12:14:47.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:47.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:47.10#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.12:14:47.10#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:47.10#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:47.22#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:47.22#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:47.22#ibcon#enter wrdev, iclass 30, count 0 2006.257.12:14:47.22#ibcon#first serial, iclass 30, count 0 2006.257.12:14:47.22#ibcon#enter sib2, iclass 30, count 0 2006.257.12:14:47.22#ibcon#flushed, iclass 30, count 0 2006.257.12:14:47.22#ibcon#about to write, iclass 30, count 0 2006.257.12:14:47.22#ibcon#wrote, iclass 30, count 0 2006.257.12:14:47.22#ibcon#about to read 3, iclass 30, count 0 2006.257.12:14:47.24#ibcon#read 3, iclass 30, count 0 2006.257.12:14:47.24#ibcon#about to read 4, iclass 30, count 0 2006.257.12:14:47.24#ibcon#read 4, iclass 30, count 0 2006.257.12:14:47.24#ibcon#about to read 5, iclass 30, count 0 2006.257.12:14:47.24#ibcon#read 5, iclass 30, count 0 2006.257.12:14:47.24#ibcon#about to read 6, iclass 30, count 0 2006.257.12:14:47.24#ibcon#read 6, iclass 30, count 0 2006.257.12:14:47.24#ibcon#end of sib2, iclass 30, count 0 2006.257.12:14:47.24#ibcon#*mode == 0, iclass 30, count 0 2006.257.12:14:47.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.12:14:47.24#ibcon#[25=USB\r\n] 2006.257.12:14:47.24#ibcon#*before write, iclass 30, count 0 2006.257.12:14:47.24#ibcon#enter sib2, iclass 30, count 0 2006.257.12:14:47.24#ibcon#flushed, iclass 30, count 0 2006.257.12:14:47.24#ibcon#about to write, iclass 30, count 0 2006.257.12:14:47.24#ibcon#wrote, iclass 30, count 0 2006.257.12:14:47.24#ibcon#about to read 3, iclass 30, count 0 2006.257.12:14:47.27#ibcon#read 3, iclass 30, count 0 2006.257.12:14:47.27#ibcon#about to read 4, iclass 30, count 0 2006.257.12:14:47.27#ibcon#read 4, iclass 30, count 0 2006.257.12:14:47.27#ibcon#about to read 5, iclass 30, count 0 2006.257.12:14:47.27#ibcon#read 5, iclass 30, count 0 2006.257.12:14:47.27#ibcon#about to read 6, iclass 30, count 0 2006.257.12:14:47.27#ibcon#read 6, iclass 30, count 0 2006.257.12:14:47.27#ibcon#end of sib2, iclass 30, count 0 2006.257.12:14:47.27#ibcon#*after write, iclass 30, count 0 2006.257.12:14:47.27#ibcon#*before return 0, iclass 30, count 0 2006.257.12:14:47.27#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:47.27#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:47.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.12:14:47.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.12:14:47.27$vck44/valo=4,624.99 2006.257.12:14:47.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.12:14:47.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.12:14:47.27#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:47.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:47.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:47.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:47.27#ibcon#enter wrdev, iclass 32, count 0 2006.257.12:14:47.27#ibcon#first serial, iclass 32, count 0 2006.257.12:14:47.27#ibcon#enter sib2, iclass 32, count 0 2006.257.12:14:47.27#ibcon#flushed, iclass 32, count 0 2006.257.12:14:47.27#ibcon#about to write, iclass 32, count 0 2006.257.12:14:47.27#ibcon#wrote, iclass 32, count 0 2006.257.12:14:47.27#ibcon#about to read 3, iclass 32, count 0 2006.257.12:14:47.29#ibcon#read 3, iclass 32, count 0 2006.257.12:14:47.29#ibcon#about to read 4, iclass 32, count 0 2006.257.12:14:47.29#ibcon#read 4, iclass 32, count 0 2006.257.12:14:47.29#ibcon#about to read 5, iclass 32, count 0 2006.257.12:14:47.29#ibcon#read 5, iclass 32, count 0 2006.257.12:14:47.29#ibcon#about to read 6, iclass 32, count 0 2006.257.12:14:47.29#ibcon#read 6, iclass 32, count 0 2006.257.12:14:47.29#ibcon#end of sib2, iclass 32, count 0 2006.257.12:14:47.29#ibcon#*mode == 0, iclass 32, count 0 2006.257.12:14:47.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.12:14:47.29#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:14:47.29#ibcon#*before write, iclass 32, count 0 2006.257.12:14:47.29#ibcon#enter sib2, iclass 32, count 0 2006.257.12:14:47.29#ibcon#flushed, iclass 32, count 0 2006.257.12:14:47.29#ibcon#about to write, iclass 32, count 0 2006.257.12:14:47.29#ibcon#wrote, iclass 32, count 0 2006.257.12:14:47.29#ibcon#about to read 3, iclass 32, count 0 2006.257.12:14:47.33#ibcon#read 3, iclass 32, count 0 2006.257.12:14:47.33#ibcon#about to read 4, iclass 32, count 0 2006.257.12:14:47.33#ibcon#read 4, iclass 32, count 0 2006.257.12:14:47.33#ibcon#about to read 5, iclass 32, count 0 2006.257.12:14:47.33#ibcon#read 5, iclass 32, count 0 2006.257.12:14:47.33#ibcon#about to read 6, iclass 32, count 0 2006.257.12:14:47.33#ibcon#read 6, iclass 32, count 0 2006.257.12:14:47.33#ibcon#end of sib2, iclass 32, count 0 2006.257.12:14:47.33#ibcon#*after write, iclass 32, count 0 2006.257.12:14:47.33#ibcon#*before return 0, iclass 32, count 0 2006.257.12:14:47.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:47.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:47.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.12:14:47.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.12:14:47.33$vck44/va=4,7 2006.257.12:14:47.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.12:14:47.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.12:14:47.33#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:47.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:47.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:47.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:47.39#ibcon#enter wrdev, iclass 34, count 2 2006.257.12:14:47.39#ibcon#first serial, iclass 34, count 2 2006.257.12:14:47.39#ibcon#enter sib2, iclass 34, count 2 2006.257.12:14:47.39#ibcon#flushed, iclass 34, count 2 2006.257.12:14:47.39#ibcon#about to write, iclass 34, count 2 2006.257.12:14:47.39#ibcon#wrote, iclass 34, count 2 2006.257.12:14:47.39#ibcon#about to read 3, iclass 34, count 2 2006.257.12:14:47.41#ibcon#read 3, iclass 34, count 2 2006.257.12:14:47.41#ibcon#about to read 4, iclass 34, count 2 2006.257.12:14:47.41#ibcon#read 4, iclass 34, count 2 2006.257.12:14:47.41#ibcon#about to read 5, iclass 34, count 2 2006.257.12:14:47.41#ibcon#read 5, iclass 34, count 2 2006.257.12:14:47.41#ibcon#about to read 6, iclass 34, count 2 2006.257.12:14:47.41#ibcon#read 6, iclass 34, count 2 2006.257.12:14:47.41#ibcon#end of sib2, iclass 34, count 2 2006.257.12:14:47.41#ibcon#*mode == 0, iclass 34, count 2 2006.257.12:14:47.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.12:14:47.41#ibcon#[25=AT04-07\r\n] 2006.257.12:14:47.41#ibcon#*before write, iclass 34, count 2 2006.257.12:14:47.41#ibcon#enter sib2, iclass 34, count 2 2006.257.12:14:47.41#ibcon#flushed, iclass 34, count 2 2006.257.12:14:47.41#ibcon#about to write, iclass 34, count 2 2006.257.12:14:47.41#ibcon#wrote, iclass 34, count 2 2006.257.12:14:47.41#ibcon#about to read 3, iclass 34, count 2 2006.257.12:14:47.44#ibcon#read 3, iclass 34, count 2 2006.257.12:14:47.44#ibcon#about to read 4, iclass 34, count 2 2006.257.12:14:47.44#ibcon#read 4, iclass 34, count 2 2006.257.12:14:47.44#ibcon#about to read 5, iclass 34, count 2 2006.257.12:14:47.44#ibcon#read 5, iclass 34, count 2 2006.257.12:14:47.44#ibcon#about to read 6, iclass 34, count 2 2006.257.12:14:47.44#ibcon#read 6, iclass 34, count 2 2006.257.12:14:47.44#ibcon#end of sib2, iclass 34, count 2 2006.257.12:14:47.44#ibcon#*after write, iclass 34, count 2 2006.257.12:14:47.44#ibcon#*before return 0, iclass 34, count 2 2006.257.12:14:47.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:47.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:47.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.12:14:47.44#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:47.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:47.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:47.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:47.56#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:14:47.56#ibcon#first serial, iclass 34, count 0 2006.257.12:14:47.56#ibcon#enter sib2, iclass 34, count 0 2006.257.12:14:47.56#ibcon#flushed, iclass 34, count 0 2006.257.12:14:47.56#ibcon#about to write, iclass 34, count 0 2006.257.12:14:47.56#ibcon#wrote, iclass 34, count 0 2006.257.12:14:47.56#ibcon#about to read 3, iclass 34, count 0 2006.257.12:14:47.58#ibcon#read 3, iclass 34, count 0 2006.257.12:14:47.58#ibcon#about to read 4, iclass 34, count 0 2006.257.12:14:47.58#ibcon#read 4, iclass 34, count 0 2006.257.12:14:47.58#ibcon#about to read 5, iclass 34, count 0 2006.257.12:14:47.58#ibcon#read 5, iclass 34, count 0 2006.257.12:14:47.58#ibcon#about to read 6, iclass 34, count 0 2006.257.12:14:47.58#ibcon#read 6, iclass 34, count 0 2006.257.12:14:47.58#ibcon#end of sib2, iclass 34, count 0 2006.257.12:14:47.58#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:14:47.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:14:47.58#ibcon#[25=USB\r\n] 2006.257.12:14:47.58#ibcon#*before write, iclass 34, count 0 2006.257.12:14:47.58#ibcon#enter sib2, iclass 34, count 0 2006.257.12:14:47.58#ibcon#flushed, iclass 34, count 0 2006.257.12:14:47.58#ibcon#about to write, iclass 34, count 0 2006.257.12:14:47.58#ibcon#wrote, iclass 34, count 0 2006.257.12:14:47.58#ibcon#about to read 3, iclass 34, count 0 2006.257.12:14:47.61#ibcon#read 3, iclass 34, count 0 2006.257.12:14:47.61#ibcon#about to read 4, iclass 34, count 0 2006.257.12:14:47.61#ibcon#read 4, iclass 34, count 0 2006.257.12:14:47.61#ibcon#about to read 5, iclass 34, count 0 2006.257.12:14:47.61#ibcon#read 5, iclass 34, count 0 2006.257.12:14:47.61#ibcon#about to read 6, iclass 34, count 0 2006.257.12:14:47.61#ibcon#read 6, iclass 34, count 0 2006.257.12:14:47.61#ibcon#end of sib2, iclass 34, count 0 2006.257.12:14:47.61#ibcon#*after write, iclass 34, count 0 2006.257.12:14:47.61#ibcon#*before return 0, iclass 34, count 0 2006.257.12:14:47.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:47.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:47.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:14:47.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:14:47.61$vck44/valo=5,734.99 2006.257.12:14:47.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.12:14:47.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.12:14:47.61#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:47.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:47.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:47.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:47.61#ibcon#enter wrdev, iclass 36, count 0 2006.257.12:14:47.61#ibcon#first serial, iclass 36, count 0 2006.257.12:14:47.61#ibcon#enter sib2, iclass 36, count 0 2006.257.12:14:47.61#ibcon#flushed, iclass 36, count 0 2006.257.12:14:47.61#ibcon#about to write, iclass 36, count 0 2006.257.12:14:47.61#ibcon#wrote, iclass 36, count 0 2006.257.12:14:47.61#ibcon#about to read 3, iclass 36, count 0 2006.257.12:14:47.63#ibcon#read 3, iclass 36, count 0 2006.257.12:14:47.63#ibcon#about to read 4, iclass 36, count 0 2006.257.12:14:47.63#ibcon#read 4, iclass 36, count 0 2006.257.12:14:47.63#ibcon#about to read 5, iclass 36, count 0 2006.257.12:14:47.63#ibcon#read 5, iclass 36, count 0 2006.257.12:14:47.63#ibcon#about to read 6, iclass 36, count 0 2006.257.12:14:47.63#ibcon#read 6, iclass 36, count 0 2006.257.12:14:47.63#ibcon#end of sib2, iclass 36, count 0 2006.257.12:14:47.63#ibcon#*mode == 0, iclass 36, count 0 2006.257.12:14:47.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.12:14:47.63#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:14:47.63#ibcon#*before write, iclass 36, count 0 2006.257.12:14:47.63#ibcon#enter sib2, iclass 36, count 0 2006.257.12:14:47.63#ibcon#flushed, iclass 36, count 0 2006.257.12:14:47.63#ibcon#about to write, iclass 36, count 0 2006.257.12:14:47.63#ibcon#wrote, iclass 36, count 0 2006.257.12:14:47.63#ibcon#about to read 3, iclass 36, count 0 2006.257.12:14:47.67#ibcon#read 3, iclass 36, count 0 2006.257.12:14:47.67#ibcon#about to read 4, iclass 36, count 0 2006.257.12:14:47.67#ibcon#read 4, iclass 36, count 0 2006.257.12:14:47.67#ibcon#about to read 5, iclass 36, count 0 2006.257.12:14:47.67#ibcon#read 5, iclass 36, count 0 2006.257.12:14:47.67#ibcon#about to read 6, iclass 36, count 0 2006.257.12:14:47.67#ibcon#read 6, iclass 36, count 0 2006.257.12:14:47.67#ibcon#end of sib2, iclass 36, count 0 2006.257.12:14:47.67#ibcon#*after write, iclass 36, count 0 2006.257.12:14:47.67#ibcon#*before return 0, iclass 36, count 0 2006.257.12:14:47.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:47.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:47.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.12:14:47.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.12:14:47.67$vck44/va=5,4 2006.257.12:14:47.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.12:14:47.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.12:14:47.67#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:47.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:47.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:47.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:47.73#ibcon#enter wrdev, iclass 38, count 2 2006.257.12:14:47.73#ibcon#first serial, iclass 38, count 2 2006.257.12:14:47.73#ibcon#enter sib2, iclass 38, count 2 2006.257.12:14:47.73#ibcon#flushed, iclass 38, count 2 2006.257.12:14:47.73#ibcon#about to write, iclass 38, count 2 2006.257.12:14:47.73#ibcon#wrote, iclass 38, count 2 2006.257.12:14:47.73#ibcon#about to read 3, iclass 38, count 2 2006.257.12:14:47.75#ibcon#read 3, iclass 38, count 2 2006.257.12:14:47.75#ibcon#about to read 4, iclass 38, count 2 2006.257.12:14:47.75#ibcon#read 4, iclass 38, count 2 2006.257.12:14:47.75#ibcon#about to read 5, iclass 38, count 2 2006.257.12:14:47.75#ibcon#read 5, iclass 38, count 2 2006.257.12:14:47.75#ibcon#about to read 6, iclass 38, count 2 2006.257.12:14:47.75#ibcon#read 6, iclass 38, count 2 2006.257.12:14:47.75#ibcon#end of sib2, iclass 38, count 2 2006.257.12:14:47.75#ibcon#*mode == 0, iclass 38, count 2 2006.257.12:14:47.75#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.12:14:47.75#ibcon#[25=AT05-04\r\n] 2006.257.12:14:47.75#ibcon#*before write, iclass 38, count 2 2006.257.12:14:47.75#ibcon#enter sib2, iclass 38, count 2 2006.257.12:14:47.75#ibcon#flushed, iclass 38, count 2 2006.257.12:14:47.75#ibcon#about to write, iclass 38, count 2 2006.257.12:14:47.75#ibcon#wrote, iclass 38, count 2 2006.257.12:14:47.75#ibcon#about to read 3, iclass 38, count 2 2006.257.12:14:47.78#ibcon#read 3, iclass 38, count 2 2006.257.12:14:47.78#ibcon#about to read 4, iclass 38, count 2 2006.257.12:14:47.78#ibcon#read 4, iclass 38, count 2 2006.257.12:14:47.78#ibcon#about to read 5, iclass 38, count 2 2006.257.12:14:47.78#ibcon#read 5, iclass 38, count 2 2006.257.12:14:47.78#ibcon#about to read 6, iclass 38, count 2 2006.257.12:14:47.78#ibcon#read 6, iclass 38, count 2 2006.257.12:14:47.78#ibcon#end of sib2, iclass 38, count 2 2006.257.12:14:47.78#ibcon#*after write, iclass 38, count 2 2006.257.12:14:47.78#ibcon#*before return 0, iclass 38, count 2 2006.257.12:14:47.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:47.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:47.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.12:14:47.78#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:47.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:47.90#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:47.90#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:47.90#ibcon#enter wrdev, iclass 38, count 0 2006.257.12:14:47.90#ibcon#first serial, iclass 38, count 0 2006.257.12:14:47.90#ibcon#enter sib2, iclass 38, count 0 2006.257.12:14:47.90#ibcon#flushed, iclass 38, count 0 2006.257.12:14:47.90#ibcon#about to write, iclass 38, count 0 2006.257.12:14:47.90#ibcon#wrote, iclass 38, count 0 2006.257.12:14:47.90#ibcon#about to read 3, iclass 38, count 0 2006.257.12:14:47.92#ibcon#read 3, iclass 38, count 0 2006.257.12:14:47.92#ibcon#about to read 4, iclass 38, count 0 2006.257.12:14:47.92#ibcon#read 4, iclass 38, count 0 2006.257.12:14:47.92#ibcon#about to read 5, iclass 38, count 0 2006.257.12:14:47.92#ibcon#read 5, iclass 38, count 0 2006.257.12:14:47.92#ibcon#about to read 6, iclass 38, count 0 2006.257.12:14:47.92#ibcon#read 6, iclass 38, count 0 2006.257.12:14:47.92#ibcon#end of sib2, iclass 38, count 0 2006.257.12:14:47.92#ibcon#*mode == 0, iclass 38, count 0 2006.257.12:14:47.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.12:14:47.92#ibcon#[25=USB\r\n] 2006.257.12:14:47.92#ibcon#*before write, iclass 38, count 0 2006.257.12:14:47.92#ibcon#enter sib2, iclass 38, count 0 2006.257.12:14:47.92#ibcon#flushed, iclass 38, count 0 2006.257.12:14:47.92#ibcon#about to write, iclass 38, count 0 2006.257.12:14:47.92#ibcon#wrote, iclass 38, count 0 2006.257.12:14:47.92#ibcon#about to read 3, iclass 38, count 0 2006.257.12:14:47.95#ibcon#read 3, iclass 38, count 0 2006.257.12:14:47.95#ibcon#about to read 4, iclass 38, count 0 2006.257.12:14:47.95#ibcon#read 4, iclass 38, count 0 2006.257.12:14:47.95#ibcon#about to read 5, iclass 38, count 0 2006.257.12:14:47.95#ibcon#read 5, iclass 38, count 0 2006.257.12:14:47.95#ibcon#about to read 6, iclass 38, count 0 2006.257.12:14:47.95#ibcon#read 6, iclass 38, count 0 2006.257.12:14:47.95#ibcon#end of sib2, iclass 38, count 0 2006.257.12:14:47.95#ibcon#*after write, iclass 38, count 0 2006.257.12:14:47.95#ibcon#*before return 0, iclass 38, count 0 2006.257.12:14:47.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:47.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:47.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.12:14:47.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.12:14:47.95$vck44/valo=6,814.99 2006.257.12:14:47.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.12:14:47.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.12:14:47.95#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:47.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:47.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:47.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:47.95#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:14:47.95#ibcon#first serial, iclass 40, count 0 2006.257.12:14:47.95#ibcon#enter sib2, iclass 40, count 0 2006.257.12:14:47.95#ibcon#flushed, iclass 40, count 0 2006.257.12:14:47.95#ibcon#about to write, iclass 40, count 0 2006.257.12:14:47.95#ibcon#wrote, iclass 40, count 0 2006.257.12:14:47.95#ibcon#about to read 3, iclass 40, count 0 2006.257.12:14:47.97#ibcon#read 3, iclass 40, count 0 2006.257.12:14:47.97#ibcon#about to read 4, iclass 40, count 0 2006.257.12:14:47.97#ibcon#read 4, iclass 40, count 0 2006.257.12:14:47.97#ibcon#about to read 5, iclass 40, count 0 2006.257.12:14:47.97#ibcon#read 5, iclass 40, count 0 2006.257.12:14:47.97#ibcon#about to read 6, iclass 40, count 0 2006.257.12:14:47.97#ibcon#read 6, iclass 40, count 0 2006.257.12:14:47.97#ibcon#end of sib2, iclass 40, count 0 2006.257.12:14:47.97#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:14:47.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:14:47.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:14:47.97#ibcon#*before write, iclass 40, count 0 2006.257.12:14:47.97#ibcon#enter sib2, iclass 40, count 0 2006.257.12:14:47.97#ibcon#flushed, iclass 40, count 0 2006.257.12:14:47.97#ibcon#about to write, iclass 40, count 0 2006.257.12:14:47.97#ibcon#wrote, iclass 40, count 0 2006.257.12:14:47.97#ibcon#about to read 3, iclass 40, count 0 2006.257.12:14:48.01#ibcon#read 3, iclass 40, count 0 2006.257.12:14:48.01#ibcon#about to read 4, iclass 40, count 0 2006.257.12:14:48.01#ibcon#read 4, iclass 40, count 0 2006.257.12:14:48.01#ibcon#about to read 5, iclass 40, count 0 2006.257.12:14:48.01#ibcon#read 5, iclass 40, count 0 2006.257.12:14:48.01#ibcon#about to read 6, iclass 40, count 0 2006.257.12:14:48.01#ibcon#read 6, iclass 40, count 0 2006.257.12:14:48.01#ibcon#end of sib2, iclass 40, count 0 2006.257.12:14:48.01#ibcon#*after write, iclass 40, count 0 2006.257.12:14:48.01#ibcon#*before return 0, iclass 40, count 0 2006.257.12:14:48.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:48.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:48.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:14:48.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:14:48.01$vck44/va=6,4 2006.257.12:14:48.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.12:14:48.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.12:14:48.01#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:48.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:48.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:48.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:48.07#ibcon#enter wrdev, iclass 4, count 2 2006.257.12:14:48.07#ibcon#first serial, iclass 4, count 2 2006.257.12:14:48.07#ibcon#enter sib2, iclass 4, count 2 2006.257.12:14:48.07#ibcon#flushed, iclass 4, count 2 2006.257.12:14:48.07#ibcon#about to write, iclass 4, count 2 2006.257.12:14:48.07#ibcon#wrote, iclass 4, count 2 2006.257.12:14:48.07#ibcon#about to read 3, iclass 4, count 2 2006.257.12:14:48.09#ibcon#read 3, iclass 4, count 2 2006.257.12:14:48.09#ibcon#about to read 4, iclass 4, count 2 2006.257.12:14:48.09#ibcon#read 4, iclass 4, count 2 2006.257.12:14:48.09#ibcon#about to read 5, iclass 4, count 2 2006.257.12:14:48.09#ibcon#read 5, iclass 4, count 2 2006.257.12:14:48.09#ibcon#about to read 6, iclass 4, count 2 2006.257.12:14:48.09#ibcon#read 6, iclass 4, count 2 2006.257.12:14:48.09#ibcon#end of sib2, iclass 4, count 2 2006.257.12:14:48.09#ibcon#*mode == 0, iclass 4, count 2 2006.257.12:14:48.09#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.12:14:48.09#ibcon#[25=AT06-04\r\n] 2006.257.12:14:48.09#ibcon#*before write, iclass 4, count 2 2006.257.12:14:48.09#ibcon#enter sib2, iclass 4, count 2 2006.257.12:14:48.09#ibcon#flushed, iclass 4, count 2 2006.257.12:14:48.09#ibcon#about to write, iclass 4, count 2 2006.257.12:14:48.09#ibcon#wrote, iclass 4, count 2 2006.257.12:14:48.09#ibcon#about to read 3, iclass 4, count 2 2006.257.12:14:48.12#ibcon#read 3, iclass 4, count 2 2006.257.12:14:48.12#ibcon#about to read 4, iclass 4, count 2 2006.257.12:14:48.12#ibcon#read 4, iclass 4, count 2 2006.257.12:14:48.12#ibcon#about to read 5, iclass 4, count 2 2006.257.12:14:48.12#ibcon#read 5, iclass 4, count 2 2006.257.12:14:48.12#ibcon#about to read 6, iclass 4, count 2 2006.257.12:14:48.12#ibcon#read 6, iclass 4, count 2 2006.257.12:14:48.12#ibcon#end of sib2, iclass 4, count 2 2006.257.12:14:48.12#ibcon#*after write, iclass 4, count 2 2006.257.12:14:48.12#ibcon#*before return 0, iclass 4, count 2 2006.257.12:14:48.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:48.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:48.12#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.12:14:48.12#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:48.12#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:48.24#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:48.24#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:48.24#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:14:48.24#ibcon#first serial, iclass 4, count 0 2006.257.12:14:48.24#ibcon#enter sib2, iclass 4, count 0 2006.257.12:14:48.24#ibcon#flushed, iclass 4, count 0 2006.257.12:14:48.24#ibcon#about to write, iclass 4, count 0 2006.257.12:14:48.24#ibcon#wrote, iclass 4, count 0 2006.257.12:14:48.24#ibcon#about to read 3, iclass 4, count 0 2006.257.12:14:48.26#ibcon#read 3, iclass 4, count 0 2006.257.12:14:48.26#ibcon#about to read 4, iclass 4, count 0 2006.257.12:14:48.26#ibcon#read 4, iclass 4, count 0 2006.257.12:14:48.26#ibcon#about to read 5, iclass 4, count 0 2006.257.12:14:48.26#ibcon#read 5, iclass 4, count 0 2006.257.12:14:48.26#ibcon#about to read 6, iclass 4, count 0 2006.257.12:14:48.26#ibcon#read 6, iclass 4, count 0 2006.257.12:14:48.26#ibcon#end of sib2, iclass 4, count 0 2006.257.12:14:48.26#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:14:48.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:14:48.26#ibcon#[25=USB\r\n] 2006.257.12:14:48.26#ibcon#*before write, iclass 4, count 0 2006.257.12:14:48.26#ibcon#enter sib2, iclass 4, count 0 2006.257.12:14:48.26#ibcon#flushed, iclass 4, count 0 2006.257.12:14:48.26#ibcon#about to write, iclass 4, count 0 2006.257.12:14:48.26#ibcon#wrote, iclass 4, count 0 2006.257.12:14:48.26#ibcon#about to read 3, iclass 4, count 0 2006.257.12:14:48.29#ibcon#read 3, iclass 4, count 0 2006.257.12:14:48.29#ibcon#about to read 4, iclass 4, count 0 2006.257.12:14:48.29#ibcon#read 4, iclass 4, count 0 2006.257.12:14:48.29#ibcon#about to read 5, iclass 4, count 0 2006.257.12:14:48.29#ibcon#read 5, iclass 4, count 0 2006.257.12:14:48.29#ibcon#about to read 6, iclass 4, count 0 2006.257.12:14:48.29#ibcon#read 6, iclass 4, count 0 2006.257.12:14:48.29#ibcon#end of sib2, iclass 4, count 0 2006.257.12:14:48.29#ibcon#*after write, iclass 4, count 0 2006.257.12:14:48.29#ibcon#*before return 0, iclass 4, count 0 2006.257.12:14:48.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:48.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:48.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:14:48.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:14:48.29$vck44/valo=7,864.99 2006.257.12:14:48.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.12:14:48.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.12:14:48.29#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:48.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:48.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:48.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:48.29#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:14:48.29#ibcon#first serial, iclass 6, count 0 2006.257.12:14:48.29#ibcon#enter sib2, iclass 6, count 0 2006.257.12:14:48.29#ibcon#flushed, iclass 6, count 0 2006.257.12:14:48.29#ibcon#about to write, iclass 6, count 0 2006.257.12:14:48.29#ibcon#wrote, iclass 6, count 0 2006.257.12:14:48.29#ibcon#about to read 3, iclass 6, count 0 2006.257.12:14:48.31#ibcon#read 3, iclass 6, count 0 2006.257.12:14:48.31#ibcon#about to read 4, iclass 6, count 0 2006.257.12:14:48.31#ibcon#read 4, iclass 6, count 0 2006.257.12:14:48.31#ibcon#about to read 5, iclass 6, count 0 2006.257.12:14:48.31#ibcon#read 5, iclass 6, count 0 2006.257.12:14:48.31#ibcon#about to read 6, iclass 6, count 0 2006.257.12:14:48.31#ibcon#read 6, iclass 6, count 0 2006.257.12:14:48.31#ibcon#end of sib2, iclass 6, count 0 2006.257.12:14:48.31#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:14:48.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:14:48.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:14:48.31#ibcon#*before write, iclass 6, count 0 2006.257.12:14:48.31#ibcon#enter sib2, iclass 6, count 0 2006.257.12:14:48.31#ibcon#flushed, iclass 6, count 0 2006.257.12:14:48.31#ibcon#about to write, iclass 6, count 0 2006.257.12:14:48.31#ibcon#wrote, iclass 6, count 0 2006.257.12:14:48.31#ibcon#about to read 3, iclass 6, count 0 2006.257.12:14:48.35#ibcon#read 3, iclass 6, count 0 2006.257.12:14:48.35#ibcon#about to read 4, iclass 6, count 0 2006.257.12:14:48.35#ibcon#read 4, iclass 6, count 0 2006.257.12:14:48.35#ibcon#about to read 5, iclass 6, count 0 2006.257.12:14:48.35#ibcon#read 5, iclass 6, count 0 2006.257.12:14:48.35#ibcon#about to read 6, iclass 6, count 0 2006.257.12:14:48.35#ibcon#read 6, iclass 6, count 0 2006.257.12:14:48.35#ibcon#end of sib2, iclass 6, count 0 2006.257.12:14:48.35#ibcon#*after write, iclass 6, count 0 2006.257.12:14:48.35#ibcon#*before return 0, iclass 6, count 0 2006.257.12:14:48.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:48.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:48.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:14:48.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:14:48.35$vck44/va=7,4 2006.257.12:14:48.35#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.12:14:48.35#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.12:14:48.35#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:48.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:48.41#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:48.41#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:48.41#ibcon#enter wrdev, iclass 10, count 2 2006.257.12:14:48.41#ibcon#first serial, iclass 10, count 2 2006.257.12:14:48.41#ibcon#enter sib2, iclass 10, count 2 2006.257.12:14:48.41#ibcon#flushed, iclass 10, count 2 2006.257.12:14:48.41#ibcon#about to write, iclass 10, count 2 2006.257.12:14:48.41#ibcon#wrote, iclass 10, count 2 2006.257.12:14:48.41#ibcon#about to read 3, iclass 10, count 2 2006.257.12:14:48.43#ibcon#read 3, iclass 10, count 2 2006.257.12:14:48.43#ibcon#about to read 4, iclass 10, count 2 2006.257.12:14:48.43#ibcon#read 4, iclass 10, count 2 2006.257.12:14:48.43#ibcon#about to read 5, iclass 10, count 2 2006.257.12:14:48.43#ibcon#read 5, iclass 10, count 2 2006.257.12:14:48.43#ibcon#about to read 6, iclass 10, count 2 2006.257.12:14:48.43#ibcon#read 6, iclass 10, count 2 2006.257.12:14:48.43#ibcon#end of sib2, iclass 10, count 2 2006.257.12:14:48.43#ibcon#*mode == 0, iclass 10, count 2 2006.257.12:14:48.43#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.12:14:48.43#ibcon#[25=AT07-04\r\n] 2006.257.12:14:48.43#ibcon#*before write, iclass 10, count 2 2006.257.12:14:48.43#ibcon#enter sib2, iclass 10, count 2 2006.257.12:14:48.43#ibcon#flushed, iclass 10, count 2 2006.257.12:14:48.43#ibcon#about to write, iclass 10, count 2 2006.257.12:14:48.43#ibcon#wrote, iclass 10, count 2 2006.257.12:14:48.43#ibcon#about to read 3, iclass 10, count 2 2006.257.12:14:48.46#ibcon#read 3, iclass 10, count 2 2006.257.12:14:48.46#ibcon#about to read 4, iclass 10, count 2 2006.257.12:14:48.46#ibcon#read 4, iclass 10, count 2 2006.257.12:14:48.46#ibcon#about to read 5, iclass 10, count 2 2006.257.12:14:48.46#ibcon#read 5, iclass 10, count 2 2006.257.12:14:48.46#ibcon#about to read 6, iclass 10, count 2 2006.257.12:14:48.46#ibcon#read 6, iclass 10, count 2 2006.257.12:14:48.46#ibcon#end of sib2, iclass 10, count 2 2006.257.12:14:48.46#ibcon#*after write, iclass 10, count 2 2006.257.12:14:48.46#ibcon#*before return 0, iclass 10, count 2 2006.257.12:14:48.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:48.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:48.49#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.12:14:48.50#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:48.50#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:48.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:48.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:48.60#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:14:48.60#ibcon#first serial, iclass 10, count 0 2006.257.12:14:48.60#ibcon#enter sib2, iclass 10, count 0 2006.257.12:14:48.60#ibcon#flushed, iclass 10, count 0 2006.257.12:14:48.60#ibcon#about to write, iclass 10, count 0 2006.257.12:14:48.60#ibcon#wrote, iclass 10, count 0 2006.257.12:14:48.60#ibcon#about to read 3, iclass 10, count 0 2006.257.12:14:48.62#ibcon#read 3, iclass 10, count 0 2006.257.12:14:48.62#ibcon#about to read 4, iclass 10, count 0 2006.257.12:14:48.62#ibcon#read 4, iclass 10, count 0 2006.257.12:14:48.62#ibcon#about to read 5, iclass 10, count 0 2006.257.12:14:48.62#ibcon#read 5, iclass 10, count 0 2006.257.12:14:48.62#ibcon#about to read 6, iclass 10, count 0 2006.257.12:14:48.62#ibcon#read 6, iclass 10, count 0 2006.257.12:14:48.62#ibcon#end of sib2, iclass 10, count 0 2006.257.12:14:48.62#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:14:48.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:14:48.62#ibcon#[25=USB\r\n] 2006.257.12:14:48.62#ibcon#*before write, iclass 10, count 0 2006.257.12:14:48.62#ibcon#enter sib2, iclass 10, count 0 2006.257.12:14:48.62#ibcon#flushed, iclass 10, count 0 2006.257.12:14:48.62#ibcon#about to write, iclass 10, count 0 2006.257.12:14:48.62#ibcon#wrote, iclass 10, count 0 2006.257.12:14:48.62#ibcon#about to read 3, iclass 10, count 0 2006.257.12:14:48.65#ibcon#read 3, iclass 10, count 0 2006.257.12:14:48.65#ibcon#about to read 4, iclass 10, count 0 2006.257.12:14:48.65#ibcon#read 4, iclass 10, count 0 2006.257.12:14:48.65#ibcon#about to read 5, iclass 10, count 0 2006.257.12:14:48.65#ibcon#read 5, iclass 10, count 0 2006.257.12:14:48.65#ibcon#about to read 6, iclass 10, count 0 2006.257.12:14:48.65#ibcon#read 6, iclass 10, count 0 2006.257.12:14:48.65#ibcon#end of sib2, iclass 10, count 0 2006.257.12:14:48.65#ibcon#*after write, iclass 10, count 0 2006.257.12:14:48.65#ibcon#*before return 0, iclass 10, count 0 2006.257.12:14:48.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:48.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:48.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:14:48.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:14:48.65$vck44/valo=8,884.99 2006.257.12:14:48.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.12:14:48.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.12:14:48.65#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:48.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:48.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:48.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:48.65#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:14:48.65#ibcon#first serial, iclass 12, count 0 2006.257.12:14:48.65#ibcon#enter sib2, iclass 12, count 0 2006.257.12:14:48.65#ibcon#flushed, iclass 12, count 0 2006.257.12:14:48.65#ibcon#about to write, iclass 12, count 0 2006.257.12:14:48.65#ibcon#wrote, iclass 12, count 0 2006.257.12:14:48.65#ibcon#about to read 3, iclass 12, count 0 2006.257.12:14:48.67#ibcon#read 3, iclass 12, count 0 2006.257.12:14:48.67#ibcon#about to read 4, iclass 12, count 0 2006.257.12:14:48.67#ibcon#read 4, iclass 12, count 0 2006.257.12:14:48.67#ibcon#about to read 5, iclass 12, count 0 2006.257.12:14:48.67#ibcon#read 5, iclass 12, count 0 2006.257.12:14:48.67#ibcon#about to read 6, iclass 12, count 0 2006.257.12:14:48.67#ibcon#read 6, iclass 12, count 0 2006.257.12:14:48.67#ibcon#end of sib2, iclass 12, count 0 2006.257.12:14:48.67#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:14:48.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:14:48.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:14:48.67#ibcon#*before write, iclass 12, count 0 2006.257.12:14:48.67#ibcon#enter sib2, iclass 12, count 0 2006.257.12:14:48.67#ibcon#flushed, iclass 12, count 0 2006.257.12:14:48.67#ibcon#about to write, iclass 12, count 0 2006.257.12:14:48.67#ibcon#wrote, iclass 12, count 0 2006.257.12:14:48.67#ibcon#about to read 3, iclass 12, count 0 2006.257.12:14:48.71#ibcon#read 3, iclass 12, count 0 2006.257.12:14:48.71#ibcon#about to read 4, iclass 12, count 0 2006.257.12:14:48.71#ibcon#read 4, iclass 12, count 0 2006.257.12:14:48.71#ibcon#about to read 5, iclass 12, count 0 2006.257.12:14:48.71#ibcon#read 5, iclass 12, count 0 2006.257.12:14:48.71#ibcon#about to read 6, iclass 12, count 0 2006.257.12:14:48.71#ibcon#read 6, iclass 12, count 0 2006.257.12:14:48.71#ibcon#end of sib2, iclass 12, count 0 2006.257.12:14:48.71#ibcon#*after write, iclass 12, count 0 2006.257.12:14:48.71#ibcon#*before return 0, iclass 12, count 0 2006.257.12:14:48.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:48.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:48.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:14:48.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:14:48.71$vck44/va=8,4 2006.257.12:14:48.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.12:14:48.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.12:14:48.71#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:48.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:14:48.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:14:48.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:14:48.77#ibcon#enter wrdev, iclass 14, count 2 2006.257.12:14:48.77#ibcon#first serial, iclass 14, count 2 2006.257.12:14:48.77#ibcon#enter sib2, iclass 14, count 2 2006.257.12:14:48.77#ibcon#flushed, iclass 14, count 2 2006.257.12:14:48.77#ibcon#about to write, iclass 14, count 2 2006.257.12:14:48.77#ibcon#wrote, iclass 14, count 2 2006.257.12:14:48.77#ibcon#about to read 3, iclass 14, count 2 2006.257.12:14:48.79#ibcon#read 3, iclass 14, count 2 2006.257.12:14:48.79#ibcon#about to read 4, iclass 14, count 2 2006.257.12:14:48.79#ibcon#read 4, iclass 14, count 2 2006.257.12:14:48.79#ibcon#about to read 5, iclass 14, count 2 2006.257.12:14:48.79#ibcon#read 5, iclass 14, count 2 2006.257.12:14:48.79#ibcon#about to read 6, iclass 14, count 2 2006.257.12:14:48.79#ibcon#read 6, iclass 14, count 2 2006.257.12:14:48.79#ibcon#end of sib2, iclass 14, count 2 2006.257.12:14:48.79#ibcon#*mode == 0, iclass 14, count 2 2006.257.12:14:48.79#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.12:14:48.79#ibcon#[25=AT08-04\r\n] 2006.257.12:14:48.79#ibcon#*before write, iclass 14, count 2 2006.257.12:14:48.79#ibcon#enter sib2, iclass 14, count 2 2006.257.12:14:48.79#ibcon#flushed, iclass 14, count 2 2006.257.12:14:48.79#ibcon#about to write, iclass 14, count 2 2006.257.12:14:48.79#ibcon#wrote, iclass 14, count 2 2006.257.12:14:48.79#ibcon#about to read 3, iclass 14, count 2 2006.257.12:14:48.82#ibcon#read 3, iclass 14, count 2 2006.257.12:14:48.82#ibcon#about to read 4, iclass 14, count 2 2006.257.12:14:48.82#ibcon#read 4, iclass 14, count 2 2006.257.12:14:48.82#ibcon#about to read 5, iclass 14, count 2 2006.257.12:14:48.82#ibcon#read 5, iclass 14, count 2 2006.257.12:14:48.82#ibcon#about to read 6, iclass 14, count 2 2006.257.12:14:48.82#ibcon#read 6, iclass 14, count 2 2006.257.12:14:48.82#ibcon#end of sib2, iclass 14, count 2 2006.257.12:14:48.82#ibcon#*after write, iclass 14, count 2 2006.257.12:14:48.82#ibcon#*before return 0, iclass 14, count 2 2006.257.12:14:48.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:14:48.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:14:48.82#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.12:14:48.82#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:48.82#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:14:48.94#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:14:48.94#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:14:48.94#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:14:48.94#ibcon#first serial, iclass 14, count 0 2006.257.12:14:48.94#ibcon#enter sib2, iclass 14, count 0 2006.257.12:14:48.94#ibcon#flushed, iclass 14, count 0 2006.257.12:14:48.94#ibcon#about to write, iclass 14, count 0 2006.257.12:14:48.94#ibcon#wrote, iclass 14, count 0 2006.257.12:14:48.94#ibcon#about to read 3, iclass 14, count 0 2006.257.12:14:48.96#ibcon#read 3, iclass 14, count 0 2006.257.12:14:48.96#ibcon#about to read 4, iclass 14, count 0 2006.257.12:14:48.96#ibcon#read 4, iclass 14, count 0 2006.257.12:14:48.96#ibcon#about to read 5, iclass 14, count 0 2006.257.12:14:48.96#ibcon#read 5, iclass 14, count 0 2006.257.12:14:48.96#ibcon#about to read 6, iclass 14, count 0 2006.257.12:14:48.96#ibcon#read 6, iclass 14, count 0 2006.257.12:14:48.96#ibcon#end of sib2, iclass 14, count 0 2006.257.12:14:48.96#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:14:48.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:14:48.96#ibcon#[25=USB\r\n] 2006.257.12:14:48.96#ibcon#*before write, iclass 14, count 0 2006.257.12:14:48.96#ibcon#enter sib2, iclass 14, count 0 2006.257.12:14:48.96#ibcon#flushed, iclass 14, count 0 2006.257.12:14:48.96#ibcon#about to write, iclass 14, count 0 2006.257.12:14:48.96#ibcon#wrote, iclass 14, count 0 2006.257.12:14:48.96#ibcon#about to read 3, iclass 14, count 0 2006.257.12:14:48.99#ibcon#read 3, iclass 14, count 0 2006.257.12:14:48.99#ibcon#about to read 4, iclass 14, count 0 2006.257.12:14:48.99#ibcon#read 4, iclass 14, count 0 2006.257.12:14:48.99#ibcon#about to read 5, iclass 14, count 0 2006.257.12:14:48.99#ibcon#read 5, iclass 14, count 0 2006.257.12:14:48.99#ibcon#about to read 6, iclass 14, count 0 2006.257.12:14:48.99#ibcon#read 6, iclass 14, count 0 2006.257.12:14:48.99#ibcon#end of sib2, iclass 14, count 0 2006.257.12:14:48.99#ibcon#*after write, iclass 14, count 0 2006.257.12:14:48.99#ibcon#*before return 0, iclass 14, count 0 2006.257.12:14:48.99#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:14:48.99#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:14:48.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:14:48.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:14:48.99$vck44/vblo=1,629.99 2006.257.12:14:48.99#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.12:14:48.99#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.12:14:48.99#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:48.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:48.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:48.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:48.99#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:14:48.99#ibcon#first serial, iclass 16, count 0 2006.257.12:14:48.99#ibcon#enter sib2, iclass 16, count 0 2006.257.12:14:48.99#ibcon#flushed, iclass 16, count 0 2006.257.12:14:48.99#ibcon#about to write, iclass 16, count 0 2006.257.12:14:48.99#ibcon#wrote, iclass 16, count 0 2006.257.12:14:48.99#ibcon#about to read 3, iclass 16, count 0 2006.257.12:14:49.01#ibcon#read 3, iclass 16, count 0 2006.257.12:14:49.01#ibcon#about to read 4, iclass 16, count 0 2006.257.12:14:49.01#ibcon#read 4, iclass 16, count 0 2006.257.12:14:49.01#ibcon#about to read 5, iclass 16, count 0 2006.257.12:14:49.01#ibcon#read 5, iclass 16, count 0 2006.257.12:14:49.01#ibcon#about to read 6, iclass 16, count 0 2006.257.12:14:49.01#ibcon#read 6, iclass 16, count 0 2006.257.12:14:49.01#ibcon#end of sib2, iclass 16, count 0 2006.257.12:14:49.01#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:14:49.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:14:49.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:14:49.01#ibcon#*before write, iclass 16, count 0 2006.257.12:14:49.01#ibcon#enter sib2, iclass 16, count 0 2006.257.12:14:49.01#ibcon#flushed, iclass 16, count 0 2006.257.12:14:49.01#ibcon#about to write, iclass 16, count 0 2006.257.12:14:49.01#ibcon#wrote, iclass 16, count 0 2006.257.12:14:49.01#ibcon#about to read 3, iclass 16, count 0 2006.257.12:14:49.05#ibcon#read 3, iclass 16, count 0 2006.257.12:14:49.05#ibcon#about to read 4, iclass 16, count 0 2006.257.12:14:49.05#ibcon#read 4, iclass 16, count 0 2006.257.12:14:49.05#ibcon#about to read 5, iclass 16, count 0 2006.257.12:14:49.05#ibcon#read 5, iclass 16, count 0 2006.257.12:14:49.05#ibcon#about to read 6, iclass 16, count 0 2006.257.12:14:49.05#ibcon#read 6, iclass 16, count 0 2006.257.12:14:49.05#ibcon#end of sib2, iclass 16, count 0 2006.257.12:14:49.05#ibcon#*after write, iclass 16, count 0 2006.257.12:14:49.05#ibcon#*before return 0, iclass 16, count 0 2006.257.12:14:49.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:49.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:14:49.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:14:49.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:14:49.05$vck44/vb=1,4 2006.257.12:14:49.05#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.12:14:49.05#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.12:14:49.05#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:49.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:49.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:49.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:49.05#ibcon#enter wrdev, iclass 18, count 2 2006.257.12:14:49.05#ibcon#first serial, iclass 18, count 2 2006.257.12:14:49.05#ibcon#enter sib2, iclass 18, count 2 2006.257.12:14:49.05#ibcon#flushed, iclass 18, count 2 2006.257.12:14:49.05#ibcon#about to write, iclass 18, count 2 2006.257.12:14:49.05#ibcon#wrote, iclass 18, count 2 2006.257.12:14:49.05#ibcon#about to read 3, iclass 18, count 2 2006.257.12:14:49.07#ibcon#read 3, iclass 18, count 2 2006.257.12:14:49.07#ibcon#about to read 4, iclass 18, count 2 2006.257.12:14:49.07#ibcon#read 4, iclass 18, count 2 2006.257.12:14:49.07#ibcon#about to read 5, iclass 18, count 2 2006.257.12:14:49.07#ibcon#read 5, iclass 18, count 2 2006.257.12:14:49.07#ibcon#about to read 6, iclass 18, count 2 2006.257.12:14:49.07#ibcon#read 6, iclass 18, count 2 2006.257.12:14:49.07#ibcon#end of sib2, iclass 18, count 2 2006.257.12:14:49.07#ibcon#*mode == 0, iclass 18, count 2 2006.257.12:14:49.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.12:14:49.07#ibcon#[27=AT01-04\r\n] 2006.257.12:14:49.07#ibcon#*before write, iclass 18, count 2 2006.257.12:14:49.07#ibcon#enter sib2, iclass 18, count 2 2006.257.12:14:49.07#ibcon#flushed, iclass 18, count 2 2006.257.12:14:49.07#ibcon#about to write, iclass 18, count 2 2006.257.12:14:49.07#ibcon#wrote, iclass 18, count 2 2006.257.12:14:49.07#ibcon#about to read 3, iclass 18, count 2 2006.257.12:14:49.10#ibcon#read 3, iclass 18, count 2 2006.257.12:14:49.10#ibcon#about to read 4, iclass 18, count 2 2006.257.12:14:49.10#ibcon#read 4, iclass 18, count 2 2006.257.12:14:49.10#ibcon#about to read 5, iclass 18, count 2 2006.257.12:14:49.10#ibcon#read 5, iclass 18, count 2 2006.257.12:14:49.10#ibcon#about to read 6, iclass 18, count 2 2006.257.12:14:49.10#ibcon#read 6, iclass 18, count 2 2006.257.12:14:49.10#ibcon#end of sib2, iclass 18, count 2 2006.257.12:14:49.10#ibcon#*after write, iclass 18, count 2 2006.257.12:14:49.10#ibcon#*before return 0, iclass 18, count 2 2006.257.12:14:49.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:49.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:14:49.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.12:14:49.10#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:49.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:49.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:49.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:49.22#ibcon#enter wrdev, iclass 18, count 0 2006.257.12:14:49.22#ibcon#first serial, iclass 18, count 0 2006.257.12:14:49.22#ibcon#enter sib2, iclass 18, count 0 2006.257.12:14:49.22#ibcon#flushed, iclass 18, count 0 2006.257.12:14:49.22#ibcon#about to write, iclass 18, count 0 2006.257.12:14:49.22#ibcon#wrote, iclass 18, count 0 2006.257.12:14:49.22#ibcon#about to read 3, iclass 18, count 0 2006.257.12:14:49.24#ibcon#read 3, iclass 18, count 0 2006.257.12:14:49.24#ibcon#about to read 4, iclass 18, count 0 2006.257.12:14:49.24#ibcon#read 4, iclass 18, count 0 2006.257.12:14:49.24#ibcon#about to read 5, iclass 18, count 0 2006.257.12:14:49.24#ibcon#read 5, iclass 18, count 0 2006.257.12:14:49.24#ibcon#about to read 6, iclass 18, count 0 2006.257.12:14:49.24#ibcon#read 6, iclass 18, count 0 2006.257.12:14:49.24#ibcon#end of sib2, iclass 18, count 0 2006.257.12:14:49.24#ibcon#*mode == 0, iclass 18, count 0 2006.257.12:14:49.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.12:14:49.24#ibcon#[27=USB\r\n] 2006.257.12:14:49.24#ibcon#*before write, iclass 18, count 0 2006.257.12:14:49.24#ibcon#enter sib2, iclass 18, count 0 2006.257.12:14:49.24#ibcon#flushed, iclass 18, count 0 2006.257.12:14:49.24#ibcon#about to write, iclass 18, count 0 2006.257.12:14:49.24#ibcon#wrote, iclass 18, count 0 2006.257.12:14:49.24#ibcon#about to read 3, iclass 18, count 0 2006.257.12:14:49.27#ibcon#read 3, iclass 18, count 0 2006.257.12:14:49.27#ibcon#about to read 4, iclass 18, count 0 2006.257.12:14:49.27#ibcon#read 4, iclass 18, count 0 2006.257.12:14:49.27#ibcon#about to read 5, iclass 18, count 0 2006.257.12:14:49.27#ibcon#read 5, iclass 18, count 0 2006.257.12:14:49.27#ibcon#about to read 6, iclass 18, count 0 2006.257.12:14:49.27#ibcon#read 6, iclass 18, count 0 2006.257.12:14:49.27#ibcon#end of sib2, iclass 18, count 0 2006.257.12:14:49.27#ibcon#*after write, iclass 18, count 0 2006.257.12:14:49.27#ibcon#*before return 0, iclass 18, count 0 2006.257.12:14:49.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:49.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:14:49.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.12:14:49.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.12:14:49.27$vck44/vblo=2,634.99 2006.257.12:14:49.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.12:14:49.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.12:14:49.27#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:49.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:14:49.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:14:49.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:14:49.27#ibcon#enter wrdev, iclass 20, count 0 2006.257.12:14:49.27#ibcon#first serial, iclass 20, count 0 2006.257.12:14:49.27#ibcon#enter sib2, iclass 20, count 0 2006.257.12:14:49.27#ibcon#flushed, iclass 20, count 0 2006.257.12:14:49.27#ibcon#about to write, iclass 20, count 0 2006.257.12:14:49.27#ibcon#wrote, iclass 20, count 0 2006.257.12:14:49.27#ibcon#about to read 3, iclass 20, count 0 2006.257.12:14:49.29#ibcon#read 3, iclass 20, count 0 2006.257.12:14:49.29#ibcon#about to read 4, iclass 20, count 0 2006.257.12:14:49.29#ibcon#read 4, iclass 20, count 0 2006.257.12:14:49.29#ibcon#about to read 5, iclass 20, count 0 2006.257.12:14:49.29#ibcon#read 5, iclass 20, count 0 2006.257.12:14:49.29#ibcon#about to read 6, iclass 20, count 0 2006.257.12:14:49.29#ibcon#read 6, iclass 20, count 0 2006.257.12:14:49.29#ibcon#end of sib2, iclass 20, count 0 2006.257.12:14:49.29#ibcon#*mode == 0, iclass 20, count 0 2006.257.12:14:49.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.12:14:49.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:14:49.29#ibcon#*before write, iclass 20, count 0 2006.257.12:14:49.29#ibcon#enter sib2, iclass 20, count 0 2006.257.12:14:49.29#ibcon#flushed, iclass 20, count 0 2006.257.12:14:49.29#ibcon#about to write, iclass 20, count 0 2006.257.12:14:49.29#ibcon#wrote, iclass 20, count 0 2006.257.12:14:49.29#ibcon#about to read 3, iclass 20, count 0 2006.257.12:14:49.33#ibcon#read 3, iclass 20, count 0 2006.257.12:14:49.33#ibcon#about to read 4, iclass 20, count 0 2006.257.12:14:49.33#ibcon#read 4, iclass 20, count 0 2006.257.12:14:49.33#ibcon#about to read 5, iclass 20, count 0 2006.257.12:14:49.33#ibcon#read 5, iclass 20, count 0 2006.257.12:14:49.33#ibcon#about to read 6, iclass 20, count 0 2006.257.12:14:49.33#ibcon#read 6, iclass 20, count 0 2006.257.12:14:49.33#ibcon#end of sib2, iclass 20, count 0 2006.257.12:14:49.33#ibcon#*after write, iclass 20, count 0 2006.257.12:14:49.33#ibcon#*before return 0, iclass 20, count 0 2006.257.12:14:49.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:14:49.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:14:49.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.12:14:49.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.12:14:49.33$vck44/vb=2,5 2006.257.12:14:49.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.12:14:49.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.12:14:49.33#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:49.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:14:49.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:14:49.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:14:49.39#ibcon#enter wrdev, iclass 22, count 2 2006.257.12:14:49.39#ibcon#first serial, iclass 22, count 2 2006.257.12:14:49.39#ibcon#enter sib2, iclass 22, count 2 2006.257.12:14:49.39#ibcon#flushed, iclass 22, count 2 2006.257.12:14:49.39#ibcon#about to write, iclass 22, count 2 2006.257.12:14:49.39#ibcon#wrote, iclass 22, count 2 2006.257.12:14:49.39#ibcon#about to read 3, iclass 22, count 2 2006.257.12:14:49.41#ibcon#read 3, iclass 22, count 2 2006.257.12:14:49.41#ibcon#about to read 4, iclass 22, count 2 2006.257.12:14:49.41#ibcon#read 4, iclass 22, count 2 2006.257.12:14:49.41#ibcon#about to read 5, iclass 22, count 2 2006.257.12:14:49.41#ibcon#read 5, iclass 22, count 2 2006.257.12:14:49.41#ibcon#about to read 6, iclass 22, count 2 2006.257.12:14:49.41#ibcon#read 6, iclass 22, count 2 2006.257.12:14:49.41#ibcon#end of sib2, iclass 22, count 2 2006.257.12:14:49.41#ibcon#*mode == 0, iclass 22, count 2 2006.257.12:14:49.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.12:14:49.41#ibcon#[27=AT02-05\r\n] 2006.257.12:14:49.41#ibcon#*before write, iclass 22, count 2 2006.257.12:14:49.41#ibcon#enter sib2, iclass 22, count 2 2006.257.12:14:49.41#ibcon#flushed, iclass 22, count 2 2006.257.12:14:49.41#ibcon#about to write, iclass 22, count 2 2006.257.12:14:49.41#ibcon#wrote, iclass 22, count 2 2006.257.12:14:49.41#ibcon#about to read 3, iclass 22, count 2 2006.257.12:14:49.44#ibcon#read 3, iclass 22, count 2 2006.257.12:14:49.44#ibcon#about to read 4, iclass 22, count 2 2006.257.12:14:49.44#ibcon#read 4, iclass 22, count 2 2006.257.12:14:49.44#ibcon#about to read 5, iclass 22, count 2 2006.257.12:14:49.44#ibcon#read 5, iclass 22, count 2 2006.257.12:14:49.44#ibcon#about to read 6, iclass 22, count 2 2006.257.12:14:49.44#ibcon#read 6, iclass 22, count 2 2006.257.12:14:49.44#ibcon#end of sib2, iclass 22, count 2 2006.257.12:14:49.44#ibcon#*after write, iclass 22, count 2 2006.257.12:14:49.53#ibcon#*before return 0, iclass 22, count 2 2006.257.12:14:49.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:14:49.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:14:49.53#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.12:14:49.53#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:49.53#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:14:49.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:14:49.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:14:49.64#ibcon#enter wrdev, iclass 22, count 0 2006.257.12:14:49.64#ibcon#first serial, iclass 22, count 0 2006.257.12:14:49.64#ibcon#enter sib2, iclass 22, count 0 2006.257.12:14:49.64#ibcon#flushed, iclass 22, count 0 2006.257.12:14:49.64#ibcon#about to write, iclass 22, count 0 2006.257.12:14:49.64#ibcon#wrote, iclass 22, count 0 2006.257.12:14:49.64#ibcon#about to read 3, iclass 22, count 0 2006.257.12:14:49.66#ibcon#read 3, iclass 22, count 0 2006.257.12:14:49.66#ibcon#about to read 4, iclass 22, count 0 2006.257.12:14:49.66#ibcon#read 4, iclass 22, count 0 2006.257.12:14:49.66#ibcon#about to read 5, iclass 22, count 0 2006.257.12:14:49.66#ibcon#read 5, iclass 22, count 0 2006.257.12:14:49.66#ibcon#about to read 6, iclass 22, count 0 2006.257.12:14:49.66#ibcon#read 6, iclass 22, count 0 2006.257.12:14:49.66#ibcon#end of sib2, iclass 22, count 0 2006.257.12:14:49.66#ibcon#*mode == 0, iclass 22, count 0 2006.257.12:14:49.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.12:14:49.66#ibcon#[27=USB\r\n] 2006.257.12:14:49.66#ibcon#*before write, iclass 22, count 0 2006.257.12:14:49.66#ibcon#enter sib2, iclass 22, count 0 2006.257.12:14:49.66#ibcon#flushed, iclass 22, count 0 2006.257.12:14:49.66#ibcon#about to write, iclass 22, count 0 2006.257.12:14:49.66#ibcon#wrote, iclass 22, count 0 2006.257.12:14:49.66#ibcon#about to read 3, iclass 22, count 0 2006.257.12:14:49.69#ibcon#read 3, iclass 22, count 0 2006.257.12:14:49.69#ibcon#about to read 4, iclass 22, count 0 2006.257.12:14:49.69#ibcon#read 4, iclass 22, count 0 2006.257.12:14:49.69#ibcon#about to read 5, iclass 22, count 0 2006.257.12:14:49.69#ibcon#read 5, iclass 22, count 0 2006.257.12:14:49.69#ibcon#about to read 6, iclass 22, count 0 2006.257.12:14:49.69#ibcon#read 6, iclass 22, count 0 2006.257.12:14:49.69#ibcon#end of sib2, iclass 22, count 0 2006.257.12:14:49.69#ibcon#*after write, iclass 22, count 0 2006.257.12:14:49.69#ibcon#*before return 0, iclass 22, count 0 2006.257.12:14:49.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:14:49.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:14:49.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.12:14:49.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.12:14:49.69$vck44/vblo=3,649.99 2006.257.12:14:49.69#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.12:14:49.69#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.12:14:49.69#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:49.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:49.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:49.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:49.69#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:14:49.69#ibcon#first serial, iclass 24, count 0 2006.257.12:14:49.69#ibcon#enter sib2, iclass 24, count 0 2006.257.12:14:49.69#ibcon#flushed, iclass 24, count 0 2006.257.12:14:49.69#ibcon#about to write, iclass 24, count 0 2006.257.12:14:49.69#ibcon#wrote, iclass 24, count 0 2006.257.12:14:49.69#ibcon#about to read 3, iclass 24, count 0 2006.257.12:14:49.71#ibcon#read 3, iclass 24, count 0 2006.257.12:14:49.71#ibcon#about to read 4, iclass 24, count 0 2006.257.12:14:49.71#ibcon#read 4, iclass 24, count 0 2006.257.12:14:49.71#ibcon#about to read 5, iclass 24, count 0 2006.257.12:14:49.71#ibcon#read 5, iclass 24, count 0 2006.257.12:14:49.71#ibcon#about to read 6, iclass 24, count 0 2006.257.12:14:49.71#ibcon#read 6, iclass 24, count 0 2006.257.12:14:49.71#ibcon#end of sib2, iclass 24, count 0 2006.257.12:14:49.71#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:14:49.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:14:49.71#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:14:49.71#ibcon#*before write, iclass 24, count 0 2006.257.12:14:49.71#ibcon#enter sib2, iclass 24, count 0 2006.257.12:14:49.71#ibcon#flushed, iclass 24, count 0 2006.257.12:14:49.71#ibcon#about to write, iclass 24, count 0 2006.257.12:14:49.71#ibcon#wrote, iclass 24, count 0 2006.257.12:14:49.71#ibcon#about to read 3, iclass 24, count 0 2006.257.12:14:49.75#ibcon#read 3, iclass 24, count 0 2006.257.12:14:49.75#ibcon#about to read 4, iclass 24, count 0 2006.257.12:14:49.75#ibcon#read 4, iclass 24, count 0 2006.257.12:14:49.75#ibcon#about to read 5, iclass 24, count 0 2006.257.12:14:49.75#ibcon#read 5, iclass 24, count 0 2006.257.12:14:49.75#ibcon#about to read 6, iclass 24, count 0 2006.257.12:14:49.75#ibcon#read 6, iclass 24, count 0 2006.257.12:14:49.75#ibcon#end of sib2, iclass 24, count 0 2006.257.12:14:49.75#ibcon#*after write, iclass 24, count 0 2006.257.12:14:49.75#ibcon#*before return 0, iclass 24, count 0 2006.257.12:14:49.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:49.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:14:49.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:14:49.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:14:49.75$vck44/vb=3,4 2006.257.12:14:49.75#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.12:14:49.75#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.12:14:49.75#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:49.75#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:49.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:49.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:49.81#ibcon#enter wrdev, iclass 26, count 2 2006.257.12:14:49.81#ibcon#first serial, iclass 26, count 2 2006.257.12:14:49.81#ibcon#enter sib2, iclass 26, count 2 2006.257.12:14:49.81#ibcon#flushed, iclass 26, count 2 2006.257.12:14:49.81#ibcon#about to write, iclass 26, count 2 2006.257.12:14:49.81#ibcon#wrote, iclass 26, count 2 2006.257.12:14:49.81#ibcon#about to read 3, iclass 26, count 2 2006.257.12:14:49.83#ibcon#read 3, iclass 26, count 2 2006.257.12:14:49.83#ibcon#about to read 4, iclass 26, count 2 2006.257.12:14:49.83#ibcon#read 4, iclass 26, count 2 2006.257.12:14:49.83#ibcon#about to read 5, iclass 26, count 2 2006.257.12:14:49.83#ibcon#read 5, iclass 26, count 2 2006.257.12:14:49.83#ibcon#about to read 6, iclass 26, count 2 2006.257.12:14:49.83#ibcon#read 6, iclass 26, count 2 2006.257.12:14:49.83#ibcon#end of sib2, iclass 26, count 2 2006.257.12:14:49.83#ibcon#*mode == 0, iclass 26, count 2 2006.257.12:14:49.83#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.12:14:49.83#ibcon#[27=AT03-04\r\n] 2006.257.12:14:49.83#ibcon#*before write, iclass 26, count 2 2006.257.12:14:49.83#ibcon#enter sib2, iclass 26, count 2 2006.257.12:14:49.83#ibcon#flushed, iclass 26, count 2 2006.257.12:14:49.83#ibcon#about to write, iclass 26, count 2 2006.257.12:14:49.83#ibcon#wrote, iclass 26, count 2 2006.257.12:14:49.83#ibcon#about to read 3, iclass 26, count 2 2006.257.12:14:49.86#ibcon#read 3, iclass 26, count 2 2006.257.12:14:49.86#ibcon#about to read 4, iclass 26, count 2 2006.257.12:14:49.86#ibcon#read 4, iclass 26, count 2 2006.257.12:14:49.86#ibcon#about to read 5, iclass 26, count 2 2006.257.12:14:49.86#ibcon#read 5, iclass 26, count 2 2006.257.12:14:49.86#ibcon#about to read 6, iclass 26, count 2 2006.257.12:14:49.86#ibcon#read 6, iclass 26, count 2 2006.257.12:14:49.86#ibcon#end of sib2, iclass 26, count 2 2006.257.12:14:49.86#ibcon#*after write, iclass 26, count 2 2006.257.12:14:49.86#ibcon#*before return 0, iclass 26, count 2 2006.257.12:14:49.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:49.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:14:49.86#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.12:14:49.86#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:49.86#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:49.98#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:49.98#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:49.98#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:14:49.98#ibcon#first serial, iclass 26, count 0 2006.257.12:14:49.98#ibcon#enter sib2, iclass 26, count 0 2006.257.12:14:49.98#ibcon#flushed, iclass 26, count 0 2006.257.12:14:49.98#ibcon#about to write, iclass 26, count 0 2006.257.12:14:49.98#ibcon#wrote, iclass 26, count 0 2006.257.12:14:49.98#ibcon#about to read 3, iclass 26, count 0 2006.257.12:14:50.00#ibcon#read 3, iclass 26, count 0 2006.257.12:14:50.00#ibcon#about to read 4, iclass 26, count 0 2006.257.12:14:50.00#ibcon#read 4, iclass 26, count 0 2006.257.12:14:50.00#ibcon#about to read 5, iclass 26, count 0 2006.257.12:14:50.00#ibcon#read 5, iclass 26, count 0 2006.257.12:14:50.00#ibcon#about to read 6, iclass 26, count 0 2006.257.12:14:50.00#ibcon#read 6, iclass 26, count 0 2006.257.12:14:50.00#ibcon#end of sib2, iclass 26, count 0 2006.257.12:14:50.00#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:14:50.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:14:50.00#ibcon#[27=USB\r\n] 2006.257.12:14:50.00#ibcon#*before write, iclass 26, count 0 2006.257.12:14:50.00#ibcon#enter sib2, iclass 26, count 0 2006.257.12:14:50.00#ibcon#flushed, iclass 26, count 0 2006.257.12:14:50.00#ibcon#about to write, iclass 26, count 0 2006.257.12:14:50.00#ibcon#wrote, iclass 26, count 0 2006.257.12:14:50.00#ibcon#about to read 3, iclass 26, count 0 2006.257.12:14:50.03#ibcon#read 3, iclass 26, count 0 2006.257.12:14:50.03#ibcon#about to read 4, iclass 26, count 0 2006.257.12:14:50.03#ibcon#read 4, iclass 26, count 0 2006.257.12:14:50.03#ibcon#about to read 5, iclass 26, count 0 2006.257.12:14:50.03#ibcon#read 5, iclass 26, count 0 2006.257.12:14:50.03#ibcon#about to read 6, iclass 26, count 0 2006.257.12:14:50.03#ibcon#read 6, iclass 26, count 0 2006.257.12:14:50.03#ibcon#end of sib2, iclass 26, count 0 2006.257.12:14:50.03#ibcon#*after write, iclass 26, count 0 2006.257.12:14:50.03#ibcon#*before return 0, iclass 26, count 0 2006.257.12:14:50.03#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:50.03#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:14:50.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:14:50.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:14:50.03$vck44/vblo=4,679.99 2006.257.12:14:50.03#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.12:14:50.03#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.12:14:50.03#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:50.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:50.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:50.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:50.03#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:14:50.03#ibcon#first serial, iclass 28, count 0 2006.257.12:14:50.03#ibcon#enter sib2, iclass 28, count 0 2006.257.12:14:50.03#ibcon#flushed, iclass 28, count 0 2006.257.12:14:50.03#ibcon#about to write, iclass 28, count 0 2006.257.12:14:50.03#ibcon#wrote, iclass 28, count 0 2006.257.12:14:50.03#ibcon#about to read 3, iclass 28, count 0 2006.257.12:14:50.05#ibcon#read 3, iclass 28, count 0 2006.257.12:14:50.05#ibcon#about to read 4, iclass 28, count 0 2006.257.12:14:50.05#ibcon#read 4, iclass 28, count 0 2006.257.12:14:50.05#ibcon#about to read 5, iclass 28, count 0 2006.257.12:14:50.05#ibcon#read 5, iclass 28, count 0 2006.257.12:14:50.05#ibcon#about to read 6, iclass 28, count 0 2006.257.12:14:50.05#ibcon#read 6, iclass 28, count 0 2006.257.12:14:50.05#ibcon#end of sib2, iclass 28, count 0 2006.257.12:14:50.05#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:14:50.05#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:14:50.05#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:14:50.05#ibcon#*before write, iclass 28, count 0 2006.257.12:14:50.05#ibcon#enter sib2, iclass 28, count 0 2006.257.12:14:50.05#ibcon#flushed, iclass 28, count 0 2006.257.12:14:50.05#ibcon#about to write, iclass 28, count 0 2006.257.12:14:50.05#ibcon#wrote, iclass 28, count 0 2006.257.12:14:50.05#ibcon#about to read 3, iclass 28, count 0 2006.257.12:14:50.09#ibcon#read 3, iclass 28, count 0 2006.257.12:14:50.09#ibcon#about to read 4, iclass 28, count 0 2006.257.12:14:50.09#ibcon#read 4, iclass 28, count 0 2006.257.12:14:50.09#ibcon#about to read 5, iclass 28, count 0 2006.257.12:14:50.09#ibcon#read 5, iclass 28, count 0 2006.257.12:14:50.09#ibcon#about to read 6, iclass 28, count 0 2006.257.12:14:50.09#ibcon#read 6, iclass 28, count 0 2006.257.12:14:50.09#ibcon#end of sib2, iclass 28, count 0 2006.257.12:14:50.09#ibcon#*after write, iclass 28, count 0 2006.257.12:14:50.09#ibcon#*before return 0, iclass 28, count 0 2006.257.12:14:50.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:50.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:14:50.09#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:14:50.09#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:14:50.09$vck44/vb=4,5 2006.257.12:14:50.09#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.12:14:50.09#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.12:14:50.09#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:50.09#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:50.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:50.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:50.15#ibcon#enter wrdev, iclass 30, count 2 2006.257.12:14:50.15#ibcon#first serial, iclass 30, count 2 2006.257.12:14:50.15#ibcon#enter sib2, iclass 30, count 2 2006.257.12:14:50.15#ibcon#flushed, iclass 30, count 2 2006.257.12:14:50.15#ibcon#about to write, iclass 30, count 2 2006.257.12:14:50.15#ibcon#wrote, iclass 30, count 2 2006.257.12:14:50.15#ibcon#about to read 3, iclass 30, count 2 2006.257.12:14:50.17#ibcon#read 3, iclass 30, count 2 2006.257.12:14:50.17#ibcon#about to read 4, iclass 30, count 2 2006.257.12:14:50.17#ibcon#read 4, iclass 30, count 2 2006.257.12:14:50.17#ibcon#about to read 5, iclass 30, count 2 2006.257.12:14:50.17#ibcon#read 5, iclass 30, count 2 2006.257.12:14:50.17#ibcon#about to read 6, iclass 30, count 2 2006.257.12:14:50.17#ibcon#read 6, iclass 30, count 2 2006.257.12:14:50.17#ibcon#end of sib2, iclass 30, count 2 2006.257.12:14:50.17#ibcon#*mode == 0, iclass 30, count 2 2006.257.12:14:50.17#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.12:14:50.17#ibcon#[27=AT04-05\r\n] 2006.257.12:14:50.17#ibcon#*before write, iclass 30, count 2 2006.257.12:14:50.17#ibcon#enter sib2, iclass 30, count 2 2006.257.12:14:50.17#ibcon#flushed, iclass 30, count 2 2006.257.12:14:50.17#ibcon#about to write, iclass 30, count 2 2006.257.12:14:50.17#ibcon#wrote, iclass 30, count 2 2006.257.12:14:50.17#ibcon#about to read 3, iclass 30, count 2 2006.257.12:14:50.20#ibcon#read 3, iclass 30, count 2 2006.257.12:14:50.20#ibcon#about to read 4, iclass 30, count 2 2006.257.12:14:50.20#ibcon#read 4, iclass 30, count 2 2006.257.12:14:50.20#ibcon#about to read 5, iclass 30, count 2 2006.257.12:14:50.20#ibcon#read 5, iclass 30, count 2 2006.257.12:14:50.20#ibcon#about to read 6, iclass 30, count 2 2006.257.12:14:50.20#ibcon#read 6, iclass 30, count 2 2006.257.12:14:50.20#ibcon#end of sib2, iclass 30, count 2 2006.257.12:14:50.20#ibcon#*after write, iclass 30, count 2 2006.257.12:14:50.20#ibcon#*before return 0, iclass 30, count 2 2006.257.12:14:50.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:50.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:14:50.20#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.12:14:50.20#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:50.20#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:50.32#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:50.32#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:50.32#ibcon#enter wrdev, iclass 30, count 0 2006.257.12:14:50.32#ibcon#first serial, iclass 30, count 0 2006.257.12:14:50.32#ibcon#enter sib2, iclass 30, count 0 2006.257.12:14:50.32#ibcon#flushed, iclass 30, count 0 2006.257.12:14:50.32#ibcon#about to write, iclass 30, count 0 2006.257.12:14:50.32#ibcon#wrote, iclass 30, count 0 2006.257.12:14:50.32#ibcon#about to read 3, iclass 30, count 0 2006.257.12:14:50.34#ibcon#read 3, iclass 30, count 0 2006.257.12:14:50.34#ibcon#about to read 4, iclass 30, count 0 2006.257.12:14:50.34#ibcon#read 4, iclass 30, count 0 2006.257.12:14:50.34#ibcon#about to read 5, iclass 30, count 0 2006.257.12:14:50.34#ibcon#read 5, iclass 30, count 0 2006.257.12:14:50.34#ibcon#about to read 6, iclass 30, count 0 2006.257.12:14:50.34#ibcon#read 6, iclass 30, count 0 2006.257.12:14:50.34#ibcon#end of sib2, iclass 30, count 0 2006.257.12:14:50.34#ibcon#*mode == 0, iclass 30, count 0 2006.257.12:14:50.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.12:14:50.34#ibcon#[27=USB\r\n] 2006.257.12:14:50.34#ibcon#*before write, iclass 30, count 0 2006.257.12:14:50.34#ibcon#enter sib2, iclass 30, count 0 2006.257.12:14:50.34#ibcon#flushed, iclass 30, count 0 2006.257.12:14:50.34#ibcon#about to write, iclass 30, count 0 2006.257.12:14:50.34#ibcon#wrote, iclass 30, count 0 2006.257.12:14:50.34#ibcon#about to read 3, iclass 30, count 0 2006.257.12:14:50.37#ibcon#read 3, iclass 30, count 0 2006.257.12:14:50.37#ibcon#about to read 4, iclass 30, count 0 2006.257.12:14:50.37#ibcon#read 4, iclass 30, count 0 2006.257.12:14:50.37#ibcon#about to read 5, iclass 30, count 0 2006.257.12:14:50.37#ibcon#read 5, iclass 30, count 0 2006.257.12:14:50.37#ibcon#about to read 6, iclass 30, count 0 2006.257.12:14:50.37#ibcon#read 6, iclass 30, count 0 2006.257.12:14:50.37#ibcon#end of sib2, iclass 30, count 0 2006.257.12:14:50.37#ibcon#*after write, iclass 30, count 0 2006.257.12:14:50.37#ibcon#*before return 0, iclass 30, count 0 2006.257.12:14:50.37#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:50.37#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:14:50.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.12:14:50.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.12:14:50.37$vck44/vblo=5,709.99 2006.257.12:14:50.37#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.12:14:50.37#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.12:14:50.37#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:50.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:50.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:50.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:50.37#ibcon#enter wrdev, iclass 32, count 0 2006.257.12:14:50.37#ibcon#first serial, iclass 32, count 0 2006.257.12:14:50.37#ibcon#enter sib2, iclass 32, count 0 2006.257.12:14:50.37#ibcon#flushed, iclass 32, count 0 2006.257.12:14:50.37#ibcon#about to write, iclass 32, count 0 2006.257.12:14:50.37#ibcon#wrote, iclass 32, count 0 2006.257.12:14:50.37#ibcon#about to read 3, iclass 32, count 0 2006.257.12:14:50.39#ibcon#read 3, iclass 32, count 0 2006.257.12:14:50.39#ibcon#about to read 4, iclass 32, count 0 2006.257.12:14:50.39#ibcon#read 4, iclass 32, count 0 2006.257.12:14:50.39#ibcon#about to read 5, iclass 32, count 0 2006.257.12:14:50.39#ibcon#read 5, iclass 32, count 0 2006.257.12:14:50.39#ibcon#about to read 6, iclass 32, count 0 2006.257.12:14:50.39#ibcon#read 6, iclass 32, count 0 2006.257.12:14:50.39#ibcon#end of sib2, iclass 32, count 0 2006.257.12:14:50.39#ibcon#*mode == 0, iclass 32, count 0 2006.257.12:14:50.39#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.12:14:50.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:14:50.39#ibcon#*before write, iclass 32, count 0 2006.257.12:14:50.39#ibcon#enter sib2, iclass 32, count 0 2006.257.12:14:50.39#ibcon#flushed, iclass 32, count 0 2006.257.12:14:50.39#ibcon#about to write, iclass 32, count 0 2006.257.12:14:50.39#ibcon#wrote, iclass 32, count 0 2006.257.12:14:50.39#ibcon#about to read 3, iclass 32, count 0 2006.257.12:14:50.43#ibcon#read 3, iclass 32, count 0 2006.257.12:14:50.43#ibcon#about to read 4, iclass 32, count 0 2006.257.12:14:50.43#ibcon#read 4, iclass 32, count 0 2006.257.12:14:50.43#ibcon#about to read 5, iclass 32, count 0 2006.257.12:14:50.43#ibcon#read 5, iclass 32, count 0 2006.257.12:14:50.43#ibcon#about to read 6, iclass 32, count 0 2006.257.12:14:50.43#ibcon#read 6, iclass 32, count 0 2006.257.12:14:50.43#ibcon#end of sib2, iclass 32, count 0 2006.257.12:14:50.43#ibcon#*after write, iclass 32, count 0 2006.257.12:14:50.43#ibcon#*before return 0, iclass 32, count 0 2006.257.12:14:50.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:50.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:14:50.43#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.12:14:50.43#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.12:14:50.43$vck44/vb=5,4 2006.257.12:14:50.43#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.12:14:50.43#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.12:14:50.43#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:50.43#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:50.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:50.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:50.49#ibcon#enter wrdev, iclass 34, count 2 2006.257.12:14:50.49#ibcon#first serial, iclass 34, count 2 2006.257.12:14:50.49#ibcon#enter sib2, iclass 34, count 2 2006.257.12:14:50.49#ibcon#flushed, iclass 34, count 2 2006.257.12:14:50.49#ibcon#about to write, iclass 34, count 2 2006.257.12:14:50.49#ibcon#wrote, iclass 34, count 2 2006.257.12:14:50.49#ibcon#about to read 3, iclass 34, count 2 2006.257.12:14:50.51#ibcon#read 3, iclass 34, count 2 2006.257.12:14:50.51#ibcon#about to read 4, iclass 34, count 2 2006.257.12:14:50.51#ibcon#read 4, iclass 34, count 2 2006.257.12:14:50.51#ibcon#about to read 5, iclass 34, count 2 2006.257.12:14:50.51#ibcon#read 5, iclass 34, count 2 2006.257.12:14:50.51#ibcon#about to read 6, iclass 34, count 2 2006.257.12:14:50.51#ibcon#read 6, iclass 34, count 2 2006.257.12:14:50.51#ibcon#end of sib2, iclass 34, count 2 2006.257.12:14:50.51#ibcon#*mode == 0, iclass 34, count 2 2006.257.12:14:50.51#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.12:14:50.51#ibcon#[27=AT05-04\r\n] 2006.257.12:14:50.51#ibcon#*before write, iclass 34, count 2 2006.257.12:14:50.51#ibcon#enter sib2, iclass 34, count 2 2006.257.12:14:50.51#ibcon#flushed, iclass 34, count 2 2006.257.12:14:50.51#ibcon#about to write, iclass 34, count 2 2006.257.12:14:50.51#ibcon#wrote, iclass 34, count 2 2006.257.12:14:50.51#ibcon#about to read 3, iclass 34, count 2 2006.257.12:14:50.54#ibcon#read 3, iclass 34, count 2 2006.257.12:14:50.54#ibcon#about to read 4, iclass 34, count 2 2006.257.12:14:50.54#ibcon#read 4, iclass 34, count 2 2006.257.12:14:50.54#ibcon#about to read 5, iclass 34, count 2 2006.257.12:14:50.54#ibcon#read 5, iclass 34, count 2 2006.257.12:14:50.54#ibcon#about to read 6, iclass 34, count 2 2006.257.12:14:50.54#ibcon#read 6, iclass 34, count 2 2006.257.12:14:50.54#ibcon#end of sib2, iclass 34, count 2 2006.257.12:14:50.54#ibcon#*after write, iclass 34, count 2 2006.257.12:14:50.54#ibcon#*before return 0, iclass 34, count 2 2006.257.12:14:50.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:50.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:14:50.54#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.12:14:50.54#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:50.54#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:50.66#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:50.66#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:50.66#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:14:50.66#ibcon#first serial, iclass 34, count 0 2006.257.12:14:50.66#ibcon#enter sib2, iclass 34, count 0 2006.257.12:14:50.66#ibcon#flushed, iclass 34, count 0 2006.257.12:14:50.66#ibcon#about to write, iclass 34, count 0 2006.257.12:14:50.66#ibcon#wrote, iclass 34, count 0 2006.257.12:14:50.66#ibcon#about to read 3, iclass 34, count 0 2006.257.12:14:50.68#ibcon#read 3, iclass 34, count 0 2006.257.12:14:50.68#ibcon#about to read 4, iclass 34, count 0 2006.257.12:14:50.68#ibcon#read 4, iclass 34, count 0 2006.257.12:14:50.68#ibcon#about to read 5, iclass 34, count 0 2006.257.12:14:50.68#ibcon#read 5, iclass 34, count 0 2006.257.12:14:50.68#ibcon#about to read 6, iclass 34, count 0 2006.257.12:14:50.68#ibcon#read 6, iclass 34, count 0 2006.257.12:14:50.68#ibcon#end of sib2, iclass 34, count 0 2006.257.12:14:50.68#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:14:50.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:14:50.68#ibcon#[27=USB\r\n] 2006.257.12:14:50.68#ibcon#*before write, iclass 34, count 0 2006.257.12:14:50.68#ibcon#enter sib2, iclass 34, count 0 2006.257.12:14:50.68#ibcon#flushed, iclass 34, count 0 2006.257.12:14:50.68#ibcon#about to write, iclass 34, count 0 2006.257.12:14:50.68#ibcon#wrote, iclass 34, count 0 2006.257.12:14:50.68#ibcon#about to read 3, iclass 34, count 0 2006.257.12:14:50.71#ibcon#read 3, iclass 34, count 0 2006.257.12:14:50.71#ibcon#about to read 4, iclass 34, count 0 2006.257.12:14:50.71#ibcon#read 4, iclass 34, count 0 2006.257.12:14:50.71#ibcon#about to read 5, iclass 34, count 0 2006.257.12:14:50.71#ibcon#read 5, iclass 34, count 0 2006.257.12:14:50.71#ibcon#about to read 6, iclass 34, count 0 2006.257.12:14:50.71#ibcon#read 6, iclass 34, count 0 2006.257.12:14:50.71#ibcon#end of sib2, iclass 34, count 0 2006.257.12:14:50.71#ibcon#*after write, iclass 34, count 0 2006.257.12:14:50.71#ibcon#*before return 0, iclass 34, count 0 2006.257.12:14:50.71#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:50.71#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:14:50.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:14:50.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:14:50.71$vck44/vblo=6,719.99 2006.257.12:14:50.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.12:14:50.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.12:14:50.71#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:50.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:50.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:50.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:50.71#ibcon#enter wrdev, iclass 36, count 0 2006.257.12:14:50.71#ibcon#first serial, iclass 36, count 0 2006.257.12:14:50.71#ibcon#enter sib2, iclass 36, count 0 2006.257.12:14:50.71#ibcon#flushed, iclass 36, count 0 2006.257.12:14:50.71#ibcon#about to write, iclass 36, count 0 2006.257.12:14:50.71#ibcon#wrote, iclass 36, count 0 2006.257.12:14:50.71#ibcon#about to read 3, iclass 36, count 0 2006.257.12:14:50.73#ibcon#read 3, iclass 36, count 0 2006.257.12:14:50.73#ibcon#about to read 4, iclass 36, count 0 2006.257.12:14:50.73#ibcon#read 4, iclass 36, count 0 2006.257.12:14:50.73#ibcon#about to read 5, iclass 36, count 0 2006.257.12:14:50.73#ibcon#read 5, iclass 36, count 0 2006.257.12:14:50.73#ibcon#about to read 6, iclass 36, count 0 2006.257.12:14:50.73#ibcon#read 6, iclass 36, count 0 2006.257.12:14:50.73#ibcon#end of sib2, iclass 36, count 0 2006.257.12:14:50.73#ibcon#*mode == 0, iclass 36, count 0 2006.257.12:14:50.73#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.12:14:50.73#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:14:50.73#ibcon#*before write, iclass 36, count 0 2006.257.12:14:50.73#ibcon#enter sib2, iclass 36, count 0 2006.257.12:14:50.73#ibcon#flushed, iclass 36, count 0 2006.257.12:14:50.73#ibcon#about to write, iclass 36, count 0 2006.257.12:14:50.73#ibcon#wrote, iclass 36, count 0 2006.257.12:14:50.73#ibcon#about to read 3, iclass 36, count 0 2006.257.12:14:50.77#ibcon#read 3, iclass 36, count 0 2006.257.12:14:50.77#ibcon#about to read 4, iclass 36, count 0 2006.257.12:14:50.77#ibcon#read 4, iclass 36, count 0 2006.257.12:14:50.77#ibcon#about to read 5, iclass 36, count 0 2006.257.12:14:50.77#ibcon#read 5, iclass 36, count 0 2006.257.12:14:50.77#ibcon#about to read 6, iclass 36, count 0 2006.257.12:14:50.77#ibcon#read 6, iclass 36, count 0 2006.257.12:14:50.77#ibcon#end of sib2, iclass 36, count 0 2006.257.12:14:50.77#ibcon#*after write, iclass 36, count 0 2006.257.12:14:50.77#ibcon#*before return 0, iclass 36, count 0 2006.257.12:14:50.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:50.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:14:50.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.12:14:50.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.12:14:50.77$vck44/vb=6,4 2006.257.12:14:50.77#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.12:14:50.77#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.12:14:50.77#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:50.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:50.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:50.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:50.83#ibcon#enter wrdev, iclass 38, count 2 2006.257.12:14:50.83#ibcon#first serial, iclass 38, count 2 2006.257.12:14:50.83#ibcon#enter sib2, iclass 38, count 2 2006.257.12:14:50.83#ibcon#flushed, iclass 38, count 2 2006.257.12:14:50.83#ibcon#about to write, iclass 38, count 2 2006.257.12:14:50.83#ibcon#wrote, iclass 38, count 2 2006.257.12:14:50.83#ibcon#about to read 3, iclass 38, count 2 2006.257.12:14:50.85#ibcon#read 3, iclass 38, count 2 2006.257.12:14:50.85#ibcon#about to read 4, iclass 38, count 2 2006.257.12:14:50.85#ibcon#read 4, iclass 38, count 2 2006.257.12:14:50.85#ibcon#about to read 5, iclass 38, count 2 2006.257.12:14:50.85#ibcon#read 5, iclass 38, count 2 2006.257.12:14:50.85#ibcon#about to read 6, iclass 38, count 2 2006.257.12:14:50.85#ibcon#read 6, iclass 38, count 2 2006.257.12:14:50.85#ibcon#end of sib2, iclass 38, count 2 2006.257.12:14:50.85#ibcon#*mode == 0, iclass 38, count 2 2006.257.12:14:50.85#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.12:14:50.85#ibcon#[27=AT06-04\r\n] 2006.257.12:14:50.85#ibcon#*before write, iclass 38, count 2 2006.257.12:14:50.85#ibcon#enter sib2, iclass 38, count 2 2006.257.12:14:50.85#ibcon#flushed, iclass 38, count 2 2006.257.12:14:50.85#ibcon#about to write, iclass 38, count 2 2006.257.12:14:50.85#ibcon#wrote, iclass 38, count 2 2006.257.12:14:50.85#ibcon#about to read 3, iclass 38, count 2 2006.257.12:14:50.88#ibcon#read 3, iclass 38, count 2 2006.257.12:14:50.88#ibcon#about to read 4, iclass 38, count 2 2006.257.12:14:50.88#ibcon#read 4, iclass 38, count 2 2006.257.12:14:50.88#ibcon#about to read 5, iclass 38, count 2 2006.257.12:14:50.88#ibcon#read 5, iclass 38, count 2 2006.257.12:14:50.88#ibcon#about to read 6, iclass 38, count 2 2006.257.12:14:50.88#ibcon#read 6, iclass 38, count 2 2006.257.12:14:50.88#ibcon#end of sib2, iclass 38, count 2 2006.257.12:14:50.88#ibcon#*after write, iclass 38, count 2 2006.257.12:14:50.88#ibcon#*before return 0, iclass 38, count 2 2006.257.12:14:50.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:50.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:14:50.88#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.12:14:50.88#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:50.88#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:51.00#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:51.00#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:51.00#ibcon#enter wrdev, iclass 38, count 0 2006.257.12:14:51.00#ibcon#first serial, iclass 38, count 0 2006.257.12:14:51.00#ibcon#enter sib2, iclass 38, count 0 2006.257.12:14:51.00#ibcon#flushed, iclass 38, count 0 2006.257.12:14:51.00#ibcon#about to write, iclass 38, count 0 2006.257.12:14:51.00#ibcon#wrote, iclass 38, count 0 2006.257.12:14:51.00#ibcon#about to read 3, iclass 38, count 0 2006.257.12:14:51.02#ibcon#read 3, iclass 38, count 0 2006.257.12:14:51.02#ibcon#about to read 4, iclass 38, count 0 2006.257.12:14:51.02#ibcon#read 4, iclass 38, count 0 2006.257.12:14:51.02#ibcon#about to read 5, iclass 38, count 0 2006.257.12:14:51.02#ibcon#read 5, iclass 38, count 0 2006.257.12:14:51.02#ibcon#about to read 6, iclass 38, count 0 2006.257.12:14:51.02#ibcon#read 6, iclass 38, count 0 2006.257.12:14:51.02#ibcon#end of sib2, iclass 38, count 0 2006.257.12:14:51.02#ibcon#*mode == 0, iclass 38, count 0 2006.257.12:14:51.02#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.12:14:51.02#ibcon#[27=USB\r\n] 2006.257.12:14:51.02#ibcon#*before write, iclass 38, count 0 2006.257.12:14:51.02#ibcon#enter sib2, iclass 38, count 0 2006.257.12:14:51.02#ibcon#flushed, iclass 38, count 0 2006.257.12:14:51.02#ibcon#about to write, iclass 38, count 0 2006.257.12:14:51.02#ibcon#wrote, iclass 38, count 0 2006.257.12:14:51.02#ibcon#about to read 3, iclass 38, count 0 2006.257.12:14:51.05#ibcon#read 3, iclass 38, count 0 2006.257.12:14:51.05#ibcon#about to read 4, iclass 38, count 0 2006.257.12:14:51.05#ibcon#read 4, iclass 38, count 0 2006.257.12:14:51.05#ibcon#about to read 5, iclass 38, count 0 2006.257.12:14:51.05#ibcon#read 5, iclass 38, count 0 2006.257.12:14:51.05#ibcon#about to read 6, iclass 38, count 0 2006.257.12:14:51.05#ibcon#read 6, iclass 38, count 0 2006.257.12:14:51.05#ibcon#end of sib2, iclass 38, count 0 2006.257.12:14:51.05#ibcon#*after write, iclass 38, count 0 2006.257.12:14:51.05#ibcon#*before return 0, iclass 38, count 0 2006.257.12:14:51.05#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:51.05#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:14:51.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.12:14:51.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.12:14:51.05$vck44/vblo=7,734.99 2006.257.12:14:51.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.12:14:51.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.12:14:51.05#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:51.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:51.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:51.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:51.05#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:14:51.05#ibcon#first serial, iclass 40, count 0 2006.257.12:14:51.05#ibcon#enter sib2, iclass 40, count 0 2006.257.12:14:51.05#ibcon#flushed, iclass 40, count 0 2006.257.12:14:51.05#ibcon#about to write, iclass 40, count 0 2006.257.12:14:51.05#ibcon#wrote, iclass 40, count 0 2006.257.12:14:51.05#ibcon#about to read 3, iclass 40, count 0 2006.257.12:14:51.07#ibcon#read 3, iclass 40, count 0 2006.257.12:14:51.07#ibcon#about to read 4, iclass 40, count 0 2006.257.12:14:51.07#ibcon#read 4, iclass 40, count 0 2006.257.12:14:51.07#ibcon#about to read 5, iclass 40, count 0 2006.257.12:14:51.07#ibcon#read 5, iclass 40, count 0 2006.257.12:14:51.07#ibcon#about to read 6, iclass 40, count 0 2006.257.12:14:51.07#ibcon#read 6, iclass 40, count 0 2006.257.12:14:51.07#ibcon#end of sib2, iclass 40, count 0 2006.257.12:14:51.07#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:14:51.07#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:14:51.07#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:14:51.07#ibcon#*before write, iclass 40, count 0 2006.257.12:14:51.07#ibcon#enter sib2, iclass 40, count 0 2006.257.12:14:51.07#ibcon#flushed, iclass 40, count 0 2006.257.12:14:51.07#ibcon#about to write, iclass 40, count 0 2006.257.12:14:51.07#ibcon#wrote, iclass 40, count 0 2006.257.12:14:51.07#ibcon#about to read 3, iclass 40, count 0 2006.257.12:14:51.11#ibcon#read 3, iclass 40, count 0 2006.257.12:14:51.11#ibcon#about to read 4, iclass 40, count 0 2006.257.12:14:51.11#ibcon#read 4, iclass 40, count 0 2006.257.12:14:51.11#ibcon#about to read 5, iclass 40, count 0 2006.257.12:14:51.11#ibcon#read 5, iclass 40, count 0 2006.257.12:14:51.11#ibcon#about to read 6, iclass 40, count 0 2006.257.12:14:51.11#ibcon#read 6, iclass 40, count 0 2006.257.12:14:51.11#ibcon#end of sib2, iclass 40, count 0 2006.257.12:14:51.11#ibcon#*after write, iclass 40, count 0 2006.257.12:14:51.11#ibcon#*before return 0, iclass 40, count 0 2006.257.12:14:51.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:51.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:14:51.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:14:51.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:14:51.11$vck44/vb=7,4 2006.257.12:14:51.11#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.12:14:51.11#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.12:14:51.11#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:51.11#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:51.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:51.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:51.17#ibcon#enter wrdev, iclass 4, count 2 2006.257.12:14:51.17#ibcon#first serial, iclass 4, count 2 2006.257.12:14:51.17#ibcon#enter sib2, iclass 4, count 2 2006.257.12:14:51.17#ibcon#flushed, iclass 4, count 2 2006.257.12:14:51.17#ibcon#about to write, iclass 4, count 2 2006.257.12:14:51.17#ibcon#wrote, iclass 4, count 2 2006.257.12:14:51.17#ibcon#about to read 3, iclass 4, count 2 2006.257.12:14:51.19#ibcon#read 3, iclass 4, count 2 2006.257.12:14:51.19#ibcon#about to read 4, iclass 4, count 2 2006.257.12:14:51.19#ibcon#read 4, iclass 4, count 2 2006.257.12:14:51.19#ibcon#about to read 5, iclass 4, count 2 2006.257.12:14:51.19#ibcon#read 5, iclass 4, count 2 2006.257.12:14:51.19#ibcon#about to read 6, iclass 4, count 2 2006.257.12:14:51.19#ibcon#read 6, iclass 4, count 2 2006.257.12:14:51.19#ibcon#end of sib2, iclass 4, count 2 2006.257.12:14:51.19#ibcon#*mode == 0, iclass 4, count 2 2006.257.12:14:51.19#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.12:14:51.19#ibcon#[27=AT07-04\r\n] 2006.257.12:14:51.19#ibcon#*before write, iclass 4, count 2 2006.257.12:14:51.19#ibcon#enter sib2, iclass 4, count 2 2006.257.12:14:51.19#ibcon#flushed, iclass 4, count 2 2006.257.12:14:51.19#ibcon#about to write, iclass 4, count 2 2006.257.12:14:51.19#ibcon#wrote, iclass 4, count 2 2006.257.12:14:51.19#ibcon#about to read 3, iclass 4, count 2 2006.257.12:14:51.22#ibcon#read 3, iclass 4, count 2 2006.257.12:14:51.22#ibcon#about to read 4, iclass 4, count 2 2006.257.12:14:51.22#ibcon#read 4, iclass 4, count 2 2006.257.12:14:51.22#ibcon#about to read 5, iclass 4, count 2 2006.257.12:14:51.22#ibcon#read 5, iclass 4, count 2 2006.257.12:14:51.22#ibcon#about to read 6, iclass 4, count 2 2006.257.12:14:51.22#ibcon#read 6, iclass 4, count 2 2006.257.12:14:51.22#ibcon#end of sib2, iclass 4, count 2 2006.257.12:14:51.22#ibcon#*after write, iclass 4, count 2 2006.257.12:14:51.22#ibcon#*before return 0, iclass 4, count 2 2006.257.12:14:51.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:51.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:14:51.22#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.12:14:51.22#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:51.22#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:51.34#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:51.34#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:51.34#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:14:51.34#ibcon#first serial, iclass 4, count 0 2006.257.12:14:51.34#ibcon#enter sib2, iclass 4, count 0 2006.257.12:14:51.34#ibcon#flushed, iclass 4, count 0 2006.257.12:14:51.34#ibcon#about to write, iclass 4, count 0 2006.257.12:14:51.34#ibcon#wrote, iclass 4, count 0 2006.257.12:14:51.34#ibcon#about to read 3, iclass 4, count 0 2006.257.12:14:51.36#ibcon#read 3, iclass 4, count 0 2006.257.12:14:51.36#ibcon#about to read 4, iclass 4, count 0 2006.257.12:14:51.36#ibcon#read 4, iclass 4, count 0 2006.257.12:14:51.36#ibcon#about to read 5, iclass 4, count 0 2006.257.12:14:51.36#ibcon#read 5, iclass 4, count 0 2006.257.12:14:51.36#ibcon#about to read 6, iclass 4, count 0 2006.257.12:14:51.36#ibcon#read 6, iclass 4, count 0 2006.257.12:14:51.36#ibcon#end of sib2, iclass 4, count 0 2006.257.12:14:51.36#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:14:51.36#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:14:51.36#ibcon#[27=USB\r\n] 2006.257.12:14:51.36#ibcon#*before write, iclass 4, count 0 2006.257.12:14:51.36#ibcon#enter sib2, iclass 4, count 0 2006.257.12:14:51.36#ibcon#flushed, iclass 4, count 0 2006.257.12:14:51.36#ibcon#about to write, iclass 4, count 0 2006.257.12:14:51.36#ibcon#wrote, iclass 4, count 0 2006.257.12:14:51.36#ibcon#about to read 3, iclass 4, count 0 2006.257.12:14:51.39#ibcon#read 3, iclass 4, count 0 2006.257.12:14:51.39#ibcon#about to read 4, iclass 4, count 0 2006.257.12:14:51.39#ibcon#read 4, iclass 4, count 0 2006.257.12:14:51.39#ibcon#about to read 5, iclass 4, count 0 2006.257.12:14:51.39#ibcon#read 5, iclass 4, count 0 2006.257.12:14:51.39#ibcon#about to read 6, iclass 4, count 0 2006.257.12:14:51.39#ibcon#read 6, iclass 4, count 0 2006.257.12:14:51.39#ibcon#end of sib2, iclass 4, count 0 2006.257.12:14:51.39#ibcon#*after write, iclass 4, count 0 2006.257.12:14:51.39#ibcon#*before return 0, iclass 4, count 0 2006.257.12:14:51.39#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:51.39#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:14:51.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:14:51.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:14:51.39$vck44/vblo=8,744.99 2006.257.12:14:51.39#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.12:14:51.39#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.12:14:51.39#ibcon#ireg 17 cls_cnt 0 2006.257.12:14:51.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:51.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:51.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:51.39#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:14:51.39#ibcon#first serial, iclass 6, count 0 2006.257.12:14:51.39#ibcon#enter sib2, iclass 6, count 0 2006.257.12:14:51.39#ibcon#flushed, iclass 6, count 0 2006.257.12:14:51.39#ibcon#about to write, iclass 6, count 0 2006.257.12:14:51.39#ibcon#wrote, iclass 6, count 0 2006.257.12:14:51.39#ibcon#about to read 3, iclass 6, count 0 2006.257.12:14:51.41#ibcon#read 3, iclass 6, count 0 2006.257.12:14:51.41#ibcon#about to read 4, iclass 6, count 0 2006.257.12:14:51.41#ibcon#read 4, iclass 6, count 0 2006.257.12:14:51.41#ibcon#about to read 5, iclass 6, count 0 2006.257.12:14:51.41#ibcon#read 5, iclass 6, count 0 2006.257.12:14:51.41#ibcon#about to read 6, iclass 6, count 0 2006.257.12:14:51.41#ibcon#read 6, iclass 6, count 0 2006.257.12:14:51.41#ibcon#end of sib2, iclass 6, count 0 2006.257.12:14:51.41#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:14:51.41#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:14:51.41#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:14:51.41#ibcon#*before write, iclass 6, count 0 2006.257.12:14:51.41#ibcon#enter sib2, iclass 6, count 0 2006.257.12:14:51.41#ibcon#flushed, iclass 6, count 0 2006.257.12:14:51.41#ibcon#about to write, iclass 6, count 0 2006.257.12:14:51.41#ibcon#wrote, iclass 6, count 0 2006.257.12:14:51.41#ibcon#about to read 3, iclass 6, count 0 2006.257.12:14:51.45#ibcon#read 3, iclass 6, count 0 2006.257.12:14:51.45#ibcon#about to read 4, iclass 6, count 0 2006.257.12:14:51.45#ibcon#read 4, iclass 6, count 0 2006.257.12:14:51.45#ibcon#about to read 5, iclass 6, count 0 2006.257.12:14:51.45#ibcon#read 5, iclass 6, count 0 2006.257.12:14:51.45#ibcon#about to read 6, iclass 6, count 0 2006.257.12:14:51.45#ibcon#read 6, iclass 6, count 0 2006.257.12:14:51.45#ibcon#end of sib2, iclass 6, count 0 2006.257.12:14:51.45#ibcon#*after write, iclass 6, count 0 2006.257.12:14:51.45#ibcon#*before return 0, iclass 6, count 0 2006.257.12:14:51.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:51.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:14:51.45#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:14:51.45#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:14:51.45$vck44/vb=8,4 2006.257.12:14:51.45#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.12:14:51.45#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.12:14:51.45#ibcon#ireg 11 cls_cnt 2 2006.257.12:14:51.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:51.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:51.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:51.51#ibcon#enter wrdev, iclass 10, count 2 2006.257.12:14:51.51#ibcon#first serial, iclass 10, count 2 2006.257.12:14:51.51#ibcon#enter sib2, iclass 10, count 2 2006.257.12:14:51.51#ibcon#flushed, iclass 10, count 2 2006.257.12:14:51.51#ibcon#about to write, iclass 10, count 2 2006.257.12:14:51.51#ibcon#wrote, iclass 10, count 2 2006.257.12:14:51.51#ibcon#about to read 3, iclass 10, count 2 2006.257.12:14:51.53#ibcon#read 3, iclass 10, count 2 2006.257.12:14:51.53#ibcon#about to read 4, iclass 10, count 2 2006.257.12:14:51.53#ibcon#read 4, iclass 10, count 2 2006.257.12:14:51.53#ibcon#about to read 5, iclass 10, count 2 2006.257.12:14:51.53#ibcon#read 5, iclass 10, count 2 2006.257.12:14:51.53#ibcon#about to read 6, iclass 10, count 2 2006.257.12:14:51.53#ibcon#read 6, iclass 10, count 2 2006.257.12:14:51.53#ibcon#end of sib2, iclass 10, count 2 2006.257.12:14:51.53#ibcon#*mode == 0, iclass 10, count 2 2006.257.12:14:51.53#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.12:14:51.53#ibcon#[27=AT08-04\r\n] 2006.257.12:14:51.53#ibcon#*before write, iclass 10, count 2 2006.257.12:14:51.53#ibcon#enter sib2, iclass 10, count 2 2006.257.12:14:51.53#ibcon#flushed, iclass 10, count 2 2006.257.12:14:51.53#ibcon#about to write, iclass 10, count 2 2006.257.12:14:51.53#ibcon#wrote, iclass 10, count 2 2006.257.12:14:51.53#ibcon#about to read 3, iclass 10, count 2 2006.257.12:14:51.56#ibcon#read 3, iclass 10, count 2 2006.257.12:14:51.56#ibcon#about to read 4, iclass 10, count 2 2006.257.12:14:51.59#ibcon#read 4, iclass 10, count 2 2006.257.12:14:51.59#ibcon#about to read 5, iclass 10, count 2 2006.257.12:14:51.59#ibcon#read 5, iclass 10, count 2 2006.257.12:14:51.59#ibcon#about to read 6, iclass 10, count 2 2006.257.12:14:51.59#ibcon#read 6, iclass 10, count 2 2006.257.12:14:51.59#ibcon#end of sib2, iclass 10, count 2 2006.257.12:14:51.59#ibcon#*after write, iclass 10, count 2 2006.257.12:14:51.59#ibcon#*before return 0, iclass 10, count 2 2006.257.12:14:51.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:51.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:14:51.59#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.12:14:51.59#ibcon#ireg 7 cls_cnt 0 2006.257.12:14:51.59#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:51.70#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:51.70#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:51.70#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:14:51.70#ibcon#first serial, iclass 10, count 0 2006.257.12:14:51.70#ibcon#enter sib2, iclass 10, count 0 2006.257.12:14:51.70#ibcon#flushed, iclass 10, count 0 2006.257.12:14:51.70#ibcon#about to write, iclass 10, count 0 2006.257.12:14:51.70#ibcon#wrote, iclass 10, count 0 2006.257.12:14:51.70#ibcon#about to read 3, iclass 10, count 0 2006.257.12:14:51.72#ibcon#read 3, iclass 10, count 0 2006.257.12:14:51.72#ibcon#about to read 4, iclass 10, count 0 2006.257.12:14:51.72#ibcon#read 4, iclass 10, count 0 2006.257.12:14:51.72#ibcon#about to read 5, iclass 10, count 0 2006.257.12:14:51.72#ibcon#read 5, iclass 10, count 0 2006.257.12:14:51.72#ibcon#about to read 6, iclass 10, count 0 2006.257.12:14:51.72#ibcon#read 6, iclass 10, count 0 2006.257.12:14:51.72#ibcon#end of sib2, iclass 10, count 0 2006.257.12:14:51.72#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:14:51.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:14:51.72#ibcon#[27=USB\r\n] 2006.257.12:14:51.72#ibcon#*before write, iclass 10, count 0 2006.257.12:14:51.72#ibcon#enter sib2, iclass 10, count 0 2006.257.12:14:51.72#ibcon#flushed, iclass 10, count 0 2006.257.12:14:51.72#ibcon#about to write, iclass 10, count 0 2006.257.12:14:51.72#ibcon#wrote, iclass 10, count 0 2006.257.12:14:51.72#ibcon#about to read 3, iclass 10, count 0 2006.257.12:14:51.75#ibcon#read 3, iclass 10, count 0 2006.257.12:14:51.75#ibcon#about to read 4, iclass 10, count 0 2006.257.12:14:51.75#ibcon#read 4, iclass 10, count 0 2006.257.12:14:51.75#ibcon#about to read 5, iclass 10, count 0 2006.257.12:14:51.75#ibcon#read 5, iclass 10, count 0 2006.257.12:14:51.75#ibcon#about to read 6, iclass 10, count 0 2006.257.12:14:51.75#ibcon#read 6, iclass 10, count 0 2006.257.12:14:51.75#ibcon#end of sib2, iclass 10, count 0 2006.257.12:14:51.75#ibcon#*after write, iclass 10, count 0 2006.257.12:14:51.75#ibcon#*before return 0, iclass 10, count 0 2006.257.12:14:51.75#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:51.75#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:14:51.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:14:51.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:14:51.75$vck44/vabw=wide 2006.257.12:14:51.75#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.12:14:51.75#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.12:14:51.75#ibcon#ireg 8 cls_cnt 0 2006.257.12:14:51.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:51.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:51.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:51.75#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:14:51.75#ibcon#first serial, iclass 12, count 0 2006.257.12:14:51.75#ibcon#enter sib2, iclass 12, count 0 2006.257.12:14:51.75#ibcon#flushed, iclass 12, count 0 2006.257.12:14:51.75#ibcon#about to write, iclass 12, count 0 2006.257.12:14:51.75#ibcon#wrote, iclass 12, count 0 2006.257.12:14:51.75#ibcon#about to read 3, iclass 12, count 0 2006.257.12:14:51.77#ibcon#read 3, iclass 12, count 0 2006.257.12:14:51.77#ibcon#about to read 4, iclass 12, count 0 2006.257.12:14:51.77#ibcon#read 4, iclass 12, count 0 2006.257.12:14:51.77#ibcon#about to read 5, iclass 12, count 0 2006.257.12:14:51.77#ibcon#read 5, iclass 12, count 0 2006.257.12:14:51.77#ibcon#about to read 6, iclass 12, count 0 2006.257.12:14:51.77#ibcon#read 6, iclass 12, count 0 2006.257.12:14:51.77#ibcon#end of sib2, iclass 12, count 0 2006.257.12:14:51.77#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:14:51.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:14:51.77#ibcon#[25=BW32\r\n] 2006.257.12:14:51.77#ibcon#*before write, iclass 12, count 0 2006.257.12:14:51.77#ibcon#enter sib2, iclass 12, count 0 2006.257.12:14:51.77#ibcon#flushed, iclass 12, count 0 2006.257.12:14:51.77#ibcon#about to write, iclass 12, count 0 2006.257.12:14:51.77#ibcon#wrote, iclass 12, count 0 2006.257.12:14:51.77#ibcon#about to read 3, iclass 12, count 0 2006.257.12:14:51.80#ibcon#read 3, iclass 12, count 0 2006.257.12:14:51.80#ibcon#about to read 4, iclass 12, count 0 2006.257.12:14:51.80#ibcon#read 4, iclass 12, count 0 2006.257.12:14:51.80#ibcon#about to read 5, iclass 12, count 0 2006.257.12:14:51.80#ibcon#read 5, iclass 12, count 0 2006.257.12:14:51.80#ibcon#about to read 6, iclass 12, count 0 2006.257.12:14:51.80#ibcon#read 6, iclass 12, count 0 2006.257.12:14:51.80#ibcon#end of sib2, iclass 12, count 0 2006.257.12:14:51.80#ibcon#*after write, iclass 12, count 0 2006.257.12:14:51.80#ibcon#*before return 0, iclass 12, count 0 2006.257.12:14:51.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:51.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:14:51.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:14:51.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:14:51.80$vck44/vbbw=wide 2006.257.12:14:51.80#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.12:14:51.80#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.12:14:51.80#ibcon#ireg 8 cls_cnt 0 2006.257.12:14:51.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:14:51.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:14:51.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:14:51.87#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:14:51.87#ibcon#first serial, iclass 14, count 0 2006.257.12:14:51.87#ibcon#enter sib2, iclass 14, count 0 2006.257.12:14:51.87#ibcon#flushed, iclass 14, count 0 2006.257.12:14:51.87#ibcon#about to write, iclass 14, count 0 2006.257.12:14:51.87#ibcon#wrote, iclass 14, count 0 2006.257.12:14:51.87#ibcon#about to read 3, iclass 14, count 0 2006.257.12:14:51.89#ibcon#read 3, iclass 14, count 0 2006.257.12:14:51.89#ibcon#about to read 4, iclass 14, count 0 2006.257.12:14:51.89#ibcon#read 4, iclass 14, count 0 2006.257.12:14:51.89#ibcon#about to read 5, iclass 14, count 0 2006.257.12:14:51.89#ibcon#read 5, iclass 14, count 0 2006.257.12:14:51.89#ibcon#about to read 6, iclass 14, count 0 2006.257.12:14:51.89#ibcon#read 6, iclass 14, count 0 2006.257.12:14:51.89#ibcon#end of sib2, iclass 14, count 0 2006.257.12:14:51.89#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:14:51.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:14:51.89#ibcon#[27=BW32\r\n] 2006.257.12:14:51.89#ibcon#*before write, iclass 14, count 0 2006.257.12:14:51.89#ibcon#enter sib2, iclass 14, count 0 2006.257.12:14:51.89#ibcon#flushed, iclass 14, count 0 2006.257.12:14:51.89#ibcon#about to write, iclass 14, count 0 2006.257.12:14:51.89#ibcon#wrote, iclass 14, count 0 2006.257.12:14:51.89#ibcon#about to read 3, iclass 14, count 0 2006.257.12:14:51.92#ibcon#read 3, iclass 14, count 0 2006.257.12:14:51.92#ibcon#about to read 4, iclass 14, count 0 2006.257.12:14:51.92#ibcon#read 4, iclass 14, count 0 2006.257.12:14:51.92#ibcon#about to read 5, iclass 14, count 0 2006.257.12:14:51.92#ibcon#read 5, iclass 14, count 0 2006.257.12:14:51.92#ibcon#about to read 6, iclass 14, count 0 2006.257.12:14:51.92#ibcon#read 6, iclass 14, count 0 2006.257.12:14:51.92#ibcon#end of sib2, iclass 14, count 0 2006.257.12:14:51.92#ibcon#*after write, iclass 14, count 0 2006.257.12:14:51.92#ibcon#*before return 0, iclass 14, count 0 2006.257.12:14:51.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:14:51.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:14:51.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:14:51.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:14:51.92$setupk4/ifdk4 2006.257.12:14:51.92$ifdk4/lo= 2006.257.12:14:51.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:14:51.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:14:51.92$ifdk4/patch= 2006.257.12:14:51.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:14:51.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:14:51.92$setupk4/!*+20s 2006.257.12:14:56.68#abcon#<5=/14 1.5 3.8 18.16 951014.0\r\n> 2006.257.12:14:56.70#abcon#{5=INTERFACE CLEAR} 2006.257.12:14:56.76#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:15:06.31$setupk4/"tpicd 2006.257.12:15:06.31$setupk4/echo=off 2006.257.12:15:06.31$setupk4/xlog=off 2006.257.12:15:06.31:!2006.257.12:21:13 2006.257.12:15:26.14#trakl#Source acquired 2006.257.12:15:26.14#flagr#flagr/antenna,acquired 2006.257.12:21:13.00:preob 2006.257.12:21:13.14/onsource/TRACKING 2006.257.12:21:13.14:!2006.257.12:21:23 2006.257.12:21:23.00:"tape 2006.257.12:21:23.00:"st=record 2006.257.12:21:23.00:data_valid=on 2006.257.12:21:23.00:midob 2006.257.12:21:23.13/onsource/TRACKING 2006.257.12:21:23.13/wx/18.11,1013.9,96 2006.257.12:21:23.19/cable/+6.4788E-03 2006.257.12:21:24.28/va/01,08,usb,yes,30,32 2006.257.12:21:24.28/va/02,07,usb,yes,32,33 2006.257.12:21:24.28/va/03,08,usb,yes,29,31 2006.257.12:21:24.28/va/04,07,usb,yes,33,35 2006.257.12:21:24.28/va/05,04,usb,yes,30,30 2006.257.12:21:24.28/va/06,04,usb,yes,33,33 2006.257.12:21:24.28/va/07,04,usb,yes,34,34 2006.257.12:21:24.28/va/08,04,usb,yes,28,35 2006.257.12:21:24.51/valo/01,524.99,yes,locked 2006.257.12:21:24.51/valo/02,534.99,yes,locked 2006.257.12:21:24.51/valo/03,564.99,yes,locked 2006.257.12:21:24.51/valo/04,624.99,yes,locked 2006.257.12:21:24.51/valo/05,734.99,yes,locked 2006.257.12:21:24.51/valo/06,814.99,yes,locked 2006.257.12:21:24.51/valo/07,864.99,yes,locked 2006.257.12:21:24.51/valo/08,884.99,yes,locked 2006.257.12:21:25.60/vb/01,04,usb,yes,30,28 2006.257.12:21:25.60/vb/02,05,usb,yes,28,28 2006.257.12:21:25.60/vb/03,04,usb,yes,29,32 2006.257.12:21:25.60/vb/04,05,usb,yes,30,29 2006.257.12:21:25.60/vb/05,04,usb,yes,26,28 2006.257.12:21:25.60/vb/06,04,usb,yes,31,27 2006.257.12:21:25.60/vb/07,04,usb,yes,30,30 2006.257.12:21:25.60/vb/08,04,usb,yes,28,31 2006.257.12:21:25.84/vblo/01,629.99,yes,locked 2006.257.12:21:25.84/vblo/02,634.99,yes,locked 2006.257.12:21:25.84/vblo/03,649.99,yes,locked 2006.257.12:21:25.84/vblo/04,679.99,yes,locked 2006.257.12:21:25.84/vblo/05,709.99,yes,locked 2006.257.12:21:25.84/vblo/06,719.99,yes,locked 2006.257.12:21:25.84/vblo/07,734.99,yes,locked 2006.257.12:21:25.84/vblo/08,744.99,yes,locked 2006.257.12:21:25.99/vabw/8 2006.257.12:21:26.14/vbbw/8 2006.257.12:21:26.23/xfe/off,on,15.5 2006.257.12:21:26.61/ifatt/23,28,28,28 2006.257.12:21:27.07/fmout-gps/S +4.60E-07 2006.257.12:21:27.11:!2006.257.12:22:33 2006.257.12:22:33.00:data_valid=off 2006.257.12:22:33.00:"et 2006.257.12:22:33.00:!+3s 2006.257.12:22:36.01:"tape 2006.257.12:22:36.01:postob 2006.257.12:22:36.20/cable/+6.4794E-03 2006.257.12:22:36.20/wx/18.10,1013.9,96 2006.257.12:22:37.07/fmout-gps/S +4.60E-07 2006.257.12:22:37.07:scan_name=257-1227,jd0609,110 2006.257.12:22:37.07:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.257.12:22:38.13#flagr#flagr/antenna,new-source 2006.257.12:22:38.13:checkk5 2006.257.12:22:38.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:22:38.88/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:22:39.28/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:22:39.66/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:22:40.02/chk_obsdata//k5ts1/T2571221??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.12:22:40.43/chk_obsdata//k5ts2/T2571221??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.12:22:40.81/chk_obsdata//k5ts3/T2571221??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.12:22:41.19/chk_obsdata//k5ts4/T2571221??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.12:22:41.89/k5log//k5ts1_log_newline 2006.257.12:22:42.60/k5log//k5ts2_log_newline 2006.257.12:22:43.30/k5log//k5ts3_log_newline 2006.257.12:22:44.00/k5log//k5ts4_log_newline 2006.257.12:22:44.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:22:44.02:setupk4=1 2006.257.12:22:44.02$setupk4/echo=on 2006.257.12:22:44.02$setupk4/pcalon 2006.257.12:22:44.02$pcalon/"no phase cal control is implemented here 2006.257.12:22:44.02$setupk4/"tpicd=stop 2006.257.12:22:44.02$setupk4/"rec=synch_on 2006.257.12:22:44.02$setupk4/"rec_mode=128 2006.257.12:22:44.02$setupk4/!* 2006.257.12:22:44.02$setupk4/recpk4 2006.257.12:22:44.02$recpk4/recpatch= 2006.257.12:22:44.02$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:22:44.02$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:22:44.02$setupk4/vck44 2006.257.12:22:44.02$vck44/valo=1,524.99 2006.257.12:22:44.02#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.12:22:44.02#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.12:22:44.02#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:44.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:44.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:44.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:44.02#ibcon#enter wrdev, iclass 23, count 0 2006.257.12:22:44.02#ibcon#first serial, iclass 23, count 0 2006.257.12:22:44.02#ibcon#enter sib2, iclass 23, count 0 2006.257.12:22:44.02#ibcon#flushed, iclass 23, count 0 2006.257.12:22:44.02#ibcon#about to write, iclass 23, count 0 2006.257.12:22:44.02#ibcon#wrote, iclass 23, count 0 2006.257.12:22:44.02#ibcon#about to read 3, iclass 23, count 0 2006.257.12:22:44.04#ibcon#read 3, iclass 23, count 0 2006.257.12:22:44.04#ibcon#about to read 4, iclass 23, count 0 2006.257.12:22:44.04#ibcon#read 4, iclass 23, count 0 2006.257.12:22:44.04#ibcon#about to read 5, iclass 23, count 0 2006.257.12:22:44.04#ibcon#read 5, iclass 23, count 0 2006.257.12:22:44.04#ibcon#about to read 6, iclass 23, count 0 2006.257.12:22:44.04#ibcon#read 6, iclass 23, count 0 2006.257.12:22:44.04#ibcon#end of sib2, iclass 23, count 0 2006.257.12:22:44.04#ibcon#*mode == 0, iclass 23, count 0 2006.257.12:22:44.04#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.12:22:44.04#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:22:44.04#ibcon#*before write, iclass 23, count 0 2006.257.12:22:44.04#ibcon#enter sib2, iclass 23, count 0 2006.257.12:22:44.04#ibcon#flushed, iclass 23, count 0 2006.257.12:22:44.04#ibcon#about to write, iclass 23, count 0 2006.257.12:22:44.04#ibcon#wrote, iclass 23, count 0 2006.257.12:22:44.04#ibcon#about to read 3, iclass 23, count 0 2006.257.12:22:44.09#ibcon#read 3, iclass 23, count 0 2006.257.12:22:44.09#ibcon#about to read 4, iclass 23, count 0 2006.257.12:22:44.09#ibcon#read 4, iclass 23, count 0 2006.257.12:22:44.09#ibcon#about to read 5, iclass 23, count 0 2006.257.12:22:44.09#ibcon#read 5, iclass 23, count 0 2006.257.12:22:44.09#ibcon#about to read 6, iclass 23, count 0 2006.257.12:22:44.09#ibcon#read 6, iclass 23, count 0 2006.257.12:22:44.09#ibcon#end of sib2, iclass 23, count 0 2006.257.12:22:44.09#ibcon#*after write, iclass 23, count 0 2006.257.12:22:44.09#ibcon#*before return 0, iclass 23, count 0 2006.257.12:22:44.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:44.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:44.09#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.12:22:44.09#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.12:22:44.09$vck44/va=1,8 2006.257.12:22:44.09#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.12:22:44.09#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.12:22:44.09#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:44.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:44.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:44.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:44.09#ibcon#enter wrdev, iclass 25, count 2 2006.257.12:22:44.09#ibcon#first serial, iclass 25, count 2 2006.257.12:22:44.09#ibcon#enter sib2, iclass 25, count 2 2006.257.12:22:44.09#ibcon#flushed, iclass 25, count 2 2006.257.12:22:44.09#ibcon#about to write, iclass 25, count 2 2006.257.12:22:44.09#ibcon#wrote, iclass 25, count 2 2006.257.12:22:44.09#ibcon#about to read 3, iclass 25, count 2 2006.257.12:22:44.11#ibcon#read 3, iclass 25, count 2 2006.257.12:22:44.11#ibcon#about to read 4, iclass 25, count 2 2006.257.12:22:44.11#ibcon#read 4, iclass 25, count 2 2006.257.12:22:44.11#ibcon#about to read 5, iclass 25, count 2 2006.257.12:22:44.11#ibcon#read 5, iclass 25, count 2 2006.257.12:22:44.11#ibcon#about to read 6, iclass 25, count 2 2006.257.12:22:44.11#ibcon#read 6, iclass 25, count 2 2006.257.12:22:44.11#ibcon#end of sib2, iclass 25, count 2 2006.257.12:22:44.11#ibcon#*mode == 0, iclass 25, count 2 2006.257.12:22:44.11#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.12:22:44.11#ibcon#[25=AT01-08\r\n] 2006.257.12:22:44.11#ibcon#*before write, iclass 25, count 2 2006.257.12:22:44.11#ibcon#enter sib2, iclass 25, count 2 2006.257.12:22:44.11#ibcon#flushed, iclass 25, count 2 2006.257.12:22:44.11#ibcon#about to write, iclass 25, count 2 2006.257.12:22:44.11#ibcon#wrote, iclass 25, count 2 2006.257.12:22:44.11#ibcon#about to read 3, iclass 25, count 2 2006.257.12:22:44.14#ibcon#read 3, iclass 25, count 2 2006.257.12:22:44.14#ibcon#about to read 4, iclass 25, count 2 2006.257.12:22:44.14#ibcon#read 4, iclass 25, count 2 2006.257.12:22:44.14#ibcon#about to read 5, iclass 25, count 2 2006.257.12:22:44.14#ibcon#read 5, iclass 25, count 2 2006.257.12:22:44.14#ibcon#about to read 6, iclass 25, count 2 2006.257.12:22:44.14#ibcon#read 6, iclass 25, count 2 2006.257.12:22:44.14#ibcon#end of sib2, iclass 25, count 2 2006.257.12:22:44.14#ibcon#*after write, iclass 25, count 2 2006.257.12:22:44.14#ibcon#*before return 0, iclass 25, count 2 2006.257.12:22:44.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:44.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:44.14#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.12:22:44.14#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:44.14#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:44.26#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:44.26#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:44.26#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:22:44.26#ibcon#first serial, iclass 25, count 0 2006.257.12:22:44.26#ibcon#enter sib2, iclass 25, count 0 2006.257.12:22:44.26#ibcon#flushed, iclass 25, count 0 2006.257.12:22:44.26#ibcon#about to write, iclass 25, count 0 2006.257.12:22:44.26#ibcon#wrote, iclass 25, count 0 2006.257.12:22:44.26#ibcon#about to read 3, iclass 25, count 0 2006.257.12:22:44.28#ibcon#read 3, iclass 25, count 0 2006.257.12:22:44.28#ibcon#about to read 4, iclass 25, count 0 2006.257.12:22:44.28#ibcon#read 4, iclass 25, count 0 2006.257.12:22:44.28#ibcon#about to read 5, iclass 25, count 0 2006.257.12:22:44.28#ibcon#read 5, iclass 25, count 0 2006.257.12:22:44.28#ibcon#about to read 6, iclass 25, count 0 2006.257.12:22:44.28#ibcon#read 6, iclass 25, count 0 2006.257.12:22:44.28#ibcon#end of sib2, iclass 25, count 0 2006.257.12:22:44.28#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:22:44.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:22:44.28#ibcon#[25=USB\r\n] 2006.257.12:22:44.28#ibcon#*before write, iclass 25, count 0 2006.257.12:22:44.28#ibcon#enter sib2, iclass 25, count 0 2006.257.12:22:44.28#ibcon#flushed, iclass 25, count 0 2006.257.12:22:44.28#ibcon#about to write, iclass 25, count 0 2006.257.12:22:44.28#ibcon#wrote, iclass 25, count 0 2006.257.12:22:44.28#ibcon#about to read 3, iclass 25, count 0 2006.257.12:22:44.31#ibcon#read 3, iclass 25, count 0 2006.257.12:22:44.31#ibcon#about to read 4, iclass 25, count 0 2006.257.12:22:44.31#ibcon#read 4, iclass 25, count 0 2006.257.12:22:44.31#ibcon#about to read 5, iclass 25, count 0 2006.257.12:22:44.31#ibcon#read 5, iclass 25, count 0 2006.257.12:22:44.31#ibcon#about to read 6, iclass 25, count 0 2006.257.12:22:44.31#ibcon#read 6, iclass 25, count 0 2006.257.12:22:44.31#ibcon#end of sib2, iclass 25, count 0 2006.257.12:22:44.31#ibcon#*after write, iclass 25, count 0 2006.257.12:22:44.31#ibcon#*before return 0, iclass 25, count 0 2006.257.12:22:44.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:44.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:44.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:22:44.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:22:44.31$vck44/valo=2,534.99 2006.257.12:22:44.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.12:22:44.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.12:22:44.31#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:44.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:44.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:44.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:44.31#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:22:44.31#ibcon#first serial, iclass 27, count 0 2006.257.12:22:44.31#ibcon#enter sib2, iclass 27, count 0 2006.257.12:22:44.31#ibcon#flushed, iclass 27, count 0 2006.257.12:22:44.31#ibcon#about to write, iclass 27, count 0 2006.257.12:22:44.31#ibcon#wrote, iclass 27, count 0 2006.257.12:22:44.31#ibcon#about to read 3, iclass 27, count 0 2006.257.12:22:44.33#ibcon#read 3, iclass 27, count 0 2006.257.12:22:44.33#ibcon#about to read 4, iclass 27, count 0 2006.257.12:22:44.33#ibcon#read 4, iclass 27, count 0 2006.257.12:22:44.33#ibcon#about to read 5, iclass 27, count 0 2006.257.12:22:44.33#ibcon#read 5, iclass 27, count 0 2006.257.12:22:44.33#ibcon#about to read 6, iclass 27, count 0 2006.257.12:22:44.33#ibcon#read 6, iclass 27, count 0 2006.257.12:22:44.33#ibcon#end of sib2, iclass 27, count 0 2006.257.12:22:44.33#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:22:44.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:22:44.33#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:22:44.33#ibcon#*before write, iclass 27, count 0 2006.257.12:22:44.33#ibcon#enter sib2, iclass 27, count 0 2006.257.12:22:44.33#ibcon#flushed, iclass 27, count 0 2006.257.12:22:44.33#ibcon#about to write, iclass 27, count 0 2006.257.12:22:44.33#ibcon#wrote, iclass 27, count 0 2006.257.12:22:44.33#ibcon#about to read 3, iclass 27, count 0 2006.257.12:22:44.37#ibcon#read 3, iclass 27, count 0 2006.257.12:22:44.37#ibcon#about to read 4, iclass 27, count 0 2006.257.12:22:44.37#ibcon#read 4, iclass 27, count 0 2006.257.12:22:44.37#ibcon#about to read 5, iclass 27, count 0 2006.257.12:22:44.37#ibcon#read 5, iclass 27, count 0 2006.257.12:22:44.37#ibcon#about to read 6, iclass 27, count 0 2006.257.12:22:44.37#ibcon#read 6, iclass 27, count 0 2006.257.12:22:44.37#ibcon#end of sib2, iclass 27, count 0 2006.257.12:22:44.37#ibcon#*after write, iclass 27, count 0 2006.257.12:22:44.37#ibcon#*before return 0, iclass 27, count 0 2006.257.12:22:44.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:44.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:44.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:22:44.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:22:44.37$vck44/va=2,7 2006.257.12:22:44.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.12:22:44.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.12:22:44.37#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:44.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:44.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:44.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:44.43#ibcon#enter wrdev, iclass 29, count 2 2006.257.12:22:44.43#ibcon#first serial, iclass 29, count 2 2006.257.12:22:44.43#ibcon#enter sib2, iclass 29, count 2 2006.257.12:22:44.43#ibcon#flushed, iclass 29, count 2 2006.257.12:22:44.43#ibcon#about to write, iclass 29, count 2 2006.257.12:22:44.43#ibcon#wrote, iclass 29, count 2 2006.257.12:22:44.43#ibcon#about to read 3, iclass 29, count 2 2006.257.12:22:44.45#ibcon#read 3, iclass 29, count 2 2006.257.12:22:44.45#ibcon#about to read 4, iclass 29, count 2 2006.257.12:22:44.45#ibcon#read 4, iclass 29, count 2 2006.257.12:22:44.45#ibcon#about to read 5, iclass 29, count 2 2006.257.12:22:44.45#ibcon#read 5, iclass 29, count 2 2006.257.12:22:44.45#ibcon#about to read 6, iclass 29, count 2 2006.257.12:22:44.45#ibcon#read 6, iclass 29, count 2 2006.257.12:22:44.45#ibcon#end of sib2, iclass 29, count 2 2006.257.12:22:44.45#ibcon#*mode == 0, iclass 29, count 2 2006.257.12:22:44.45#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.12:22:44.45#ibcon#[25=AT02-07\r\n] 2006.257.12:22:44.45#ibcon#*before write, iclass 29, count 2 2006.257.12:22:44.45#ibcon#enter sib2, iclass 29, count 2 2006.257.12:22:44.45#ibcon#flushed, iclass 29, count 2 2006.257.12:22:44.45#ibcon#about to write, iclass 29, count 2 2006.257.12:22:44.45#ibcon#wrote, iclass 29, count 2 2006.257.12:22:44.45#ibcon#about to read 3, iclass 29, count 2 2006.257.12:22:44.48#ibcon#read 3, iclass 29, count 2 2006.257.12:22:44.48#ibcon#about to read 4, iclass 29, count 2 2006.257.12:22:44.48#ibcon#read 4, iclass 29, count 2 2006.257.12:22:44.48#ibcon#about to read 5, iclass 29, count 2 2006.257.12:22:44.48#ibcon#read 5, iclass 29, count 2 2006.257.12:22:44.48#ibcon#about to read 6, iclass 29, count 2 2006.257.12:22:44.48#ibcon#read 6, iclass 29, count 2 2006.257.12:22:44.48#ibcon#end of sib2, iclass 29, count 2 2006.257.12:22:44.48#ibcon#*after write, iclass 29, count 2 2006.257.12:22:44.48#ibcon#*before return 0, iclass 29, count 2 2006.257.12:22:44.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:44.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:44.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.12:22:44.48#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:44.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:44.60#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:44.60#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:44.60#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:22:44.60#ibcon#first serial, iclass 29, count 0 2006.257.12:22:44.60#ibcon#enter sib2, iclass 29, count 0 2006.257.12:22:44.60#ibcon#flushed, iclass 29, count 0 2006.257.12:22:44.60#ibcon#about to write, iclass 29, count 0 2006.257.12:22:44.60#ibcon#wrote, iclass 29, count 0 2006.257.12:22:44.60#ibcon#about to read 3, iclass 29, count 0 2006.257.12:22:44.62#ibcon#read 3, iclass 29, count 0 2006.257.12:22:44.62#ibcon#about to read 4, iclass 29, count 0 2006.257.12:22:44.62#ibcon#read 4, iclass 29, count 0 2006.257.12:22:44.62#ibcon#about to read 5, iclass 29, count 0 2006.257.12:22:44.62#ibcon#read 5, iclass 29, count 0 2006.257.12:22:44.62#ibcon#about to read 6, iclass 29, count 0 2006.257.12:22:44.62#ibcon#read 6, iclass 29, count 0 2006.257.12:22:44.62#ibcon#end of sib2, iclass 29, count 0 2006.257.12:22:44.62#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:22:44.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:22:44.62#ibcon#[25=USB\r\n] 2006.257.12:22:44.62#ibcon#*before write, iclass 29, count 0 2006.257.12:22:44.62#ibcon#enter sib2, iclass 29, count 0 2006.257.12:22:44.62#ibcon#flushed, iclass 29, count 0 2006.257.12:22:44.62#ibcon#about to write, iclass 29, count 0 2006.257.12:22:44.62#ibcon#wrote, iclass 29, count 0 2006.257.12:22:44.62#ibcon#about to read 3, iclass 29, count 0 2006.257.12:22:44.63#abcon#<5=/14 1.5 4.2 18.09 951013.9\r\n> 2006.257.12:22:44.65#abcon#{5=INTERFACE CLEAR} 2006.257.12:22:44.65#ibcon#read 3, iclass 29, count 0 2006.257.12:22:44.65#ibcon#about to read 4, iclass 29, count 0 2006.257.12:22:44.65#ibcon#read 4, iclass 29, count 0 2006.257.12:22:44.65#ibcon#about to read 5, iclass 29, count 0 2006.257.12:22:44.65#ibcon#read 5, iclass 29, count 0 2006.257.12:22:44.65#ibcon#about to read 6, iclass 29, count 0 2006.257.12:22:44.65#ibcon#read 6, iclass 29, count 0 2006.257.12:22:44.65#ibcon#end of sib2, iclass 29, count 0 2006.257.12:22:44.65#ibcon#*after write, iclass 29, count 0 2006.257.12:22:44.65#ibcon#*before return 0, iclass 29, count 0 2006.257.12:22:44.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:44.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:44.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:22:44.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:22:44.65$vck44/valo=3,564.99 2006.257.12:22:44.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.12:22:44.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.12:22:44.65#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:44.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:22:44.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:22:44.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:22:44.65#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:22:44.65#ibcon#first serial, iclass 34, count 0 2006.257.12:22:44.65#ibcon#enter sib2, iclass 34, count 0 2006.257.12:22:44.65#ibcon#flushed, iclass 34, count 0 2006.257.12:22:44.65#ibcon#about to write, iclass 34, count 0 2006.257.12:22:44.65#ibcon#wrote, iclass 34, count 0 2006.257.12:22:44.65#ibcon#about to read 3, iclass 34, count 0 2006.257.12:22:44.67#ibcon#read 3, iclass 34, count 0 2006.257.12:22:44.67#ibcon#about to read 4, iclass 34, count 0 2006.257.12:22:44.67#ibcon#read 4, iclass 34, count 0 2006.257.12:22:44.67#ibcon#about to read 5, iclass 34, count 0 2006.257.12:22:44.67#ibcon#read 5, iclass 34, count 0 2006.257.12:22:44.67#ibcon#about to read 6, iclass 34, count 0 2006.257.12:22:44.67#ibcon#read 6, iclass 34, count 0 2006.257.12:22:44.67#ibcon#end of sib2, iclass 34, count 0 2006.257.12:22:44.67#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:22:44.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:22:44.67#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:22:44.67#ibcon#*before write, iclass 34, count 0 2006.257.12:22:44.67#ibcon#enter sib2, iclass 34, count 0 2006.257.12:22:44.67#ibcon#flushed, iclass 34, count 0 2006.257.12:22:44.67#ibcon#about to write, iclass 34, count 0 2006.257.12:22:44.67#ibcon#wrote, iclass 34, count 0 2006.257.12:22:44.67#ibcon#about to read 3, iclass 34, count 0 2006.257.12:22:44.71#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:22:44.71#ibcon#read 3, iclass 34, count 0 2006.257.12:22:44.71#ibcon#about to read 4, iclass 34, count 0 2006.257.12:22:44.71#ibcon#read 4, iclass 34, count 0 2006.257.12:22:44.71#ibcon#about to read 5, iclass 34, count 0 2006.257.12:22:44.71#ibcon#read 5, iclass 34, count 0 2006.257.12:22:44.71#ibcon#about to read 6, iclass 34, count 0 2006.257.12:22:44.71#ibcon#read 6, iclass 34, count 0 2006.257.12:22:44.71#ibcon#end of sib2, iclass 34, count 0 2006.257.12:22:44.71#ibcon#*after write, iclass 34, count 0 2006.257.12:22:44.71#ibcon#*before return 0, iclass 34, count 0 2006.257.12:22:44.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:22:44.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:22:44.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:22:44.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:22:44.71$vck44/va=3,8 2006.257.12:22:44.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.12:22:44.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.12:22:44.71#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:44.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:44.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:44.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:44.77#ibcon#enter wrdev, iclass 37, count 2 2006.257.12:22:44.77#ibcon#first serial, iclass 37, count 2 2006.257.12:22:44.77#ibcon#enter sib2, iclass 37, count 2 2006.257.12:22:44.77#ibcon#flushed, iclass 37, count 2 2006.257.12:22:44.77#ibcon#about to write, iclass 37, count 2 2006.257.12:22:44.77#ibcon#wrote, iclass 37, count 2 2006.257.12:22:44.77#ibcon#about to read 3, iclass 37, count 2 2006.257.12:22:44.79#ibcon#read 3, iclass 37, count 2 2006.257.12:22:44.79#ibcon#about to read 4, iclass 37, count 2 2006.257.12:22:44.79#ibcon#read 4, iclass 37, count 2 2006.257.12:22:44.79#ibcon#about to read 5, iclass 37, count 2 2006.257.12:22:44.79#ibcon#read 5, iclass 37, count 2 2006.257.12:22:44.79#ibcon#about to read 6, iclass 37, count 2 2006.257.12:22:44.79#ibcon#read 6, iclass 37, count 2 2006.257.12:22:44.79#ibcon#end of sib2, iclass 37, count 2 2006.257.12:22:44.79#ibcon#*mode == 0, iclass 37, count 2 2006.257.12:22:44.79#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.12:22:44.79#ibcon#[25=AT03-08\r\n] 2006.257.12:22:44.79#ibcon#*before write, iclass 37, count 2 2006.257.12:22:44.79#ibcon#enter sib2, iclass 37, count 2 2006.257.12:22:44.79#ibcon#flushed, iclass 37, count 2 2006.257.12:22:44.79#ibcon#about to write, iclass 37, count 2 2006.257.12:22:44.79#ibcon#wrote, iclass 37, count 2 2006.257.12:22:44.79#ibcon#about to read 3, iclass 37, count 2 2006.257.12:22:44.82#ibcon#read 3, iclass 37, count 2 2006.257.12:22:44.82#ibcon#about to read 4, iclass 37, count 2 2006.257.12:22:44.82#ibcon#read 4, iclass 37, count 2 2006.257.12:22:44.82#ibcon#about to read 5, iclass 37, count 2 2006.257.12:22:44.82#ibcon#read 5, iclass 37, count 2 2006.257.12:22:44.82#ibcon#about to read 6, iclass 37, count 2 2006.257.12:22:44.82#ibcon#read 6, iclass 37, count 2 2006.257.12:22:44.82#ibcon#end of sib2, iclass 37, count 2 2006.257.12:22:44.82#ibcon#*after write, iclass 37, count 2 2006.257.12:22:44.82#ibcon#*before return 0, iclass 37, count 2 2006.257.12:22:44.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:44.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:44.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.12:22:44.82#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:44.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:44.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:44.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:44.94#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:22:44.94#ibcon#first serial, iclass 37, count 0 2006.257.12:22:44.94#ibcon#enter sib2, iclass 37, count 0 2006.257.12:22:44.94#ibcon#flushed, iclass 37, count 0 2006.257.12:22:44.94#ibcon#about to write, iclass 37, count 0 2006.257.12:22:44.94#ibcon#wrote, iclass 37, count 0 2006.257.12:22:44.94#ibcon#about to read 3, iclass 37, count 0 2006.257.12:22:44.96#ibcon#read 3, iclass 37, count 0 2006.257.12:22:44.96#ibcon#about to read 4, iclass 37, count 0 2006.257.12:22:44.96#ibcon#read 4, iclass 37, count 0 2006.257.12:22:44.96#ibcon#about to read 5, iclass 37, count 0 2006.257.12:22:44.96#ibcon#read 5, iclass 37, count 0 2006.257.12:22:44.96#ibcon#about to read 6, iclass 37, count 0 2006.257.12:22:44.96#ibcon#read 6, iclass 37, count 0 2006.257.12:22:44.96#ibcon#end of sib2, iclass 37, count 0 2006.257.12:22:44.96#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:22:44.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:22:44.96#ibcon#[25=USB\r\n] 2006.257.12:22:44.96#ibcon#*before write, iclass 37, count 0 2006.257.12:22:44.96#ibcon#enter sib2, iclass 37, count 0 2006.257.12:22:44.96#ibcon#flushed, iclass 37, count 0 2006.257.12:22:44.96#ibcon#about to write, iclass 37, count 0 2006.257.12:22:44.96#ibcon#wrote, iclass 37, count 0 2006.257.12:22:44.96#ibcon#about to read 3, iclass 37, count 0 2006.257.12:22:44.99#ibcon#read 3, iclass 37, count 0 2006.257.12:22:44.99#ibcon#about to read 4, iclass 37, count 0 2006.257.12:22:44.99#ibcon#read 4, iclass 37, count 0 2006.257.12:22:44.99#ibcon#about to read 5, iclass 37, count 0 2006.257.12:22:44.99#ibcon#read 5, iclass 37, count 0 2006.257.12:22:44.99#ibcon#about to read 6, iclass 37, count 0 2006.257.12:22:44.99#ibcon#read 6, iclass 37, count 0 2006.257.12:22:44.99#ibcon#end of sib2, iclass 37, count 0 2006.257.12:22:44.99#ibcon#*after write, iclass 37, count 0 2006.257.12:22:44.99#ibcon#*before return 0, iclass 37, count 0 2006.257.12:22:44.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:44.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:44.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:22:44.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:22:44.99$vck44/valo=4,624.99 2006.257.12:22:44.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.12:22:44.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.12:22:44.99#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:44.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:44.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:44.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:44.99#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:22:44.99#ibcon#first serial, iclass 39, count 0 2006.257.12:22:44.99#ibcon#enter sib2, iclass 39, count 0 2006.257.12:22:44.99#ibcon#flushed, iclass 39, count 0 2006.257.12:22:44.99#ibcon#about to write, iclass 39, count 0 2006.257.12:22:44.99#ibcon#wrote, iclass 39, count 0 2006.257.12:22:44.99#ibcon#about to read 3, iclass 39, count 0 2006.257.12:22:45.01#ibcon#read 3, iclass 39, count 0 2006.257.12:22:45.01#ibcon#about to read 4, iclass 39, count 0 2006.257.12:22:45.01#ibcon#read 4, iclass 39, count 0 2006.257.12:22:45.01#ibcon#about to read 5, iclass 39, count 0 2006.257.12:22:45.01#ibcon#read 5, iclass 39, count 0 2006.257.12:22:45.01#ibcon#about to read 6, iclass 39, count 0 2006.257.12:22:45.01#ibcon#read 6, iclass 39, count 0 2006.257.12:22:45.01#ibcon#end of sib2, iclass 39, count 0 2006.257.12:22:45.01#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:22:45.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:22:45.01#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:22:45.01#ibcon#*before write, iclass 39, count 0 2006.257.12:22:45.01#ibcon#enter sib2, iclass 39, count 0 2006.257.12:22:45.01#ibcon#flushed, iclass 39, count 0 2006.257.12:22:45.01#ibcon#about to write, iclass 39, count 0 2006.257.12:22:45.01#ibcon#wrote, iclass 39, count 0 2006.257.12:22:45.01#ibcon#about to read 3, iclass 39, count 0 2006.257.12:22:45.05#ibcon#read 3, iclass 39, count 0 2006.257.12:22:45.05#ibcon#about to read 4, iclass 39, count 0 2006.257.12:22:45.05#ibcon#read 4, iclass 39, count 0 2006.257.12:22:45.05#ibcon#about to read 5, iclass 39, count 0 2006.257.12:22:45.05#ibcon#read 5, iclass 39, count 0 2006.257.12:22:45.05#ibcon#about to read 6, iclass 39, count 0 2006.257.12:22:45.05#ibcon#read 6, iclass 39, count 0 2006.257.12:22:45.05#ibcon#end of sib2, iclass 39, count 0 2006.257.12:22:45.05#ibcon#*after write, iclass 39, count 0 2006.257.12:22:45.05#ibcon#*before return 0, iclass 39, count 0 2006.257.12:22:45.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:45.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:45.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:22:45.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:22:45.05$vck44/va=4,7 2006.257.12:22:45.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.12:22:45.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.12:22:45.05#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:45.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:45.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:45.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:45.11#ibcon#enter wrdev, iclass 3, count 2 2006.257.12:22:45.11#ibcon#first serial, iclass 3, count 2 2006.257.12:22:45.11#ibcon#enter sib2, iclass 3, count 2 2006.257.12:22:45.11#ibcon#flushed, iclass 3, count 2 2006.257.12:22:45.11#ibcon#about to write, iclass 3, count 2 2006.257.12:22:45.11#ibcon#wrote, iclass 3, count 2 2006.257.12:22:45.11#ibcon#about to read 3, iclass 3, count 2 2006.257.12:22:45.13#ibcon#read 3, iclass 3, count 2 2006.257.12:22:45.13#ibcon#about to read 4, iclass 3, count 2 2006.257.12:22:45.13#ibcon#read 4, iclass 3, count 2 2006.257.12:22:45.13#ibcon#about to read 5, iclass 3, count 2 2006.257.12:22:45.13#ibcon#read 5, iclass 3, count 2 2006.257.12:22:45.13#ibcon#about to read 6, iclass 3, count 2 2006.257.12:22:45.13#ibcon#read 6, iclass 3, count 2 2006.257.12:22:45.13#ibcon#end of sib2, iclass 3, count 2 2006.257.12:22:45.13#ibcon#*mode == 0, iclass 3, count 2 2006.257.12:22:45.13#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.12:22:45.13#ibcon#[25=AT04-07\r\n] 2006.257.12:22:45.13#ibcon#*before write, iclass 3, count 2 2006.257.12:22:45.13#ibcon#enter sib2, iclass 3, count 2 2006.257.12:22:45.13#ibcon#flushed, iclass 3, count 2 2006.257.12:22:45.13#ibcon#about to write, iclass 3, count 2 2006.257.12:22:45.13#ibcon#wrote, iclass 3, count 2 2006.257.12:22:45.13#ibcon#about to read 3, iclass 3, count 2 2006.257.12:22:45.16#ibcon#read 3, iclass 3, count 2 2006.257.12:22:45.16#ibcon#about to read 4, iclass 3, count 2 2006.257.12:22:45.16#ibcon#read 4, iclass 3, count 2 2006.257.12:22:45.16#ibcon#about to read 5, iclass 3, count 2 2006.257.12:22:45.16#ibcon#read 5, iclass 3, count 2 2006.257.12:22:45.16#ibcon#about to read 6, iclass 3, count 2 2006.257.12:22:45.16#ibcon#read 6, iclass 3, count 2 2006.257.12:22:45.16#ibcon#end of sib2, iclass 3, count 2 2006.257.12:22:45.16#ibcon#*after write, iclass 3, count 2 2006.257.12:22:45.16#ibcon#*before return 0, iclass 3, count 2 2006.257.12:22:45.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:45.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:45.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.12:22:45.16#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:45.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:45.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:45.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:45.28#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:22:45.28#ibcon#first serial, iclass 3, count 0 2006.257.12:22:45.28#ibcon#enter sib2, iclass 3, count 0 2006.257.12:22:45.28#ibcon#flushed, iclass 3, count 0 2006.257.12:22:45.28#ibcon#about to write, iclass 3, count 0 2006.257.12:22:45.28#ibcon#wrote, iclass 3, count 0 2006.257.12:22:45.28#ibcon#about to read 3, iclass 3, count 0 2006.257.12:22:45.30#ibcon#read 3, iclass 3, count 0 2006.257.12:22:45.30#ibcon#about to read 4, iclass 3, count 0 2006.257.12:22:45.30#ibcon#read 4, iclass 3, count 0 2006.257.12:22:45.30#ibcon#about to read 5, iclass 3, count 0 2006.257.12:22:45.30#ibcon#read 5, iclass 3, count 0 2006.257.12:22:45.30#ibcon#about to read 6, iclass 3, count 0 2006.257.12:22:45.30#ibcon#read 6, iclass 3, count 0 2006.257.12:22:45.30#ibcon#end of sib2, iclass 3, count 0 2006.257.12:22:45.30#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:22:45.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:22:45.30#ibcon#[25=USB\r\n] 2006.257.12:22:45.30#ibcon#*before write, iclass 3, count 0 2006.257.12:22:45.30#ibcon#enter sib2, iclass 3, count 0 2006.257.12:22:45.30#ibcon#flushed, iclass 3, count 0 2006.257.12:22:45.30#ibcon#about to write, iclass 3, count 0 2006.257.12:22:45.30#ibcon#wrote, iclass 3, count 0 2006.257.12:22:45.30#ibcon#about to read 3, iclass 3, count 0 2006.257.12:22:45.33#ibcon#read 3, iclass 3, count 0 2006.257.12:22:45.33#ibcon#about to read 4, iclass 3, count 0 2006.257.12:22:45.33#ibcon#read 4, iclass 3, count 0 2006.257.12:22:45.33#ibcon#about to read 5, iclass 3, count 0 2006.257.12:22:45.33#ibcon#read 5, iclass 3, count 0 2006.257.12:22:45.33#ibcon#about to read 6, iclass 3, count 0 2006.257.12:22:45.33#ibcon#read 6, iclass 3, count 0 2006.257.12:22:45.33#ibcon#end of sib2, iclass 3, count 0 2006.257.12:22:45.33#ibcon#*after write, iclass 3, count 0 2006.257.12:22:45.33#ibcon#*before return 0, iclass 3, count 0 2006.257.12:22:45.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:45.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:45.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:22:45.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:22:45.33$vck44/valo=5,734.99 2006.257.12:22:45.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.12:22:45.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.12:22:45.33#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:45.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:45.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:45.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:45.33#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:22:45.33#ibcon#first serial, iclass 5, count 0 2006.257.12:22:45.33#ibcon#enter sib2, iclass 5, count 0 2006.257.12:22:45.33#ibcon#flushed, iclass 5, count 0 2006.257.12:22:45.33#ibcon#about to write, iclass 5, count 0 2006.257.12:22:45.33#ibcon#wrote, iclass 5, count 0 2006.257.12:22:45.33#ibcon#about to read 3, iclass 5, count 0 2006.257.12:22:45.35#ibcon#read 3, iclass 5, count 0 2006.257.12:22:45.35#ibcon#about to read 4, iclass 5, count 0 2006.257.12:22:45.35#ibcon#read 4, iclass 5, count 0 2006.257.12:22:45.35#ibcon#about to read 5, iclass 5, count 0 2006.257.12:22:45.35#ibcon#read 5, iclass 5, count 0 2006.257.12:22:45.35#ibcon#about to read 6, iclass 5, count 0 2006.257.12:22:45.35#ibcon#read 6, iclass 5, count 0 2006.257.12:22:45.35#ibcon#end of sib2, iclass 5, count 0 2006.257.12:22:45.35#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:22:45.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:22:45.35#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:22:45.35#ibcon#*before write, iclass 5, count 0 2006.257.12:22:45.35#ibcon#enter sib2, iclass 5, count 0 2006.257.12:22:45.35#ibcon#flushed, iclass 5, count 0 2006.257.12:22:45.35#ibcon#about to write, iclass 5, count 0 2006.257.12:22:45.35#ibcon#wrote, iclass 5, count 0 2006.257.12:22:45.35#ibcon#about to read 3, iclass 5, count 0 2006.257.12:22:45.39#ibcon#read 3, iclass 5, count 0 2006.257.12:22:45.39#ibcon#about to read 4, iclass 5, count 0 2006.257.12:22:45.39#ibcon#read 4, iclass 5, count 0 2006.257.12:22:45.39#ibcon#about to read 5, iclass 5, count 0 2006.257.12:22:45.39#ibcon#read 5, iclass 5, count 0 2006.257.12:22:45.39#ibcon#about to read 6, iclass 5, count 0 2006.257.12:22:45.39#ibcon#read 6, iclass 5, count 0 2006.257.12:22:45.39#ibcon#end of sib2, iclass 5, count 0 2006.257.12:22:45.39#ibcon#*after write, iclass 5, count 0 2006.257.12:22:45.39#ibcon#*before return 0, iclass 5, count 0 2006.257.12:22:45.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:45.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:45.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:22:45.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:22:45.39$vck44/va=5,4 2006.257.12:22:45.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.12:22:45.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.12:22:45.39#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:45.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:45.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:45.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:45.45#ibcon#enter wrdev, iclass 7, count 2 2006.257.12:22:45.45#ibcon#first serial, iclass 7, count 2 2006.257.12:22:45.45#ibcon#enter sib2, iclass 7, count 2 2006.257.12:22:45.45#ibcon#flushed, iclass 7, count 2 2006.257.12:22:45.45#ibcon#about to write, iclass 7, count 2 2006.257.12:22:45.45#ibcon#wrote, iclass 7, count 2 2006.257.12:22:45.45#ibcon#about to read 3, iclass 7, count 2 2006.257.12:22:45.47#ibcon#read 3, iclass 7, count 2 2006.257.12:22:45.47#ibcon#about to read 4, iclass 7, count 2 2006.257.12:22:45.47#ibcon#read 4, iclass 7, count 2 2006.257.12:22:45.47#ibcon#about to read 5, iclass 7, count 2 2006.257.12:22:45.47#ibcon#read 5, iclass 7, count 2 2006.257.12:22:45.47#ibcon#about to read 6, iclass 7, count 2 2006.257.12:22:45.47#ibcon#read 6, iclass 7, count 2 2006.257.12:22:45.47#ibcon#end of sib2, iclass 7, count 2 2006.257.12:22:45.47#ibcon#*mode == 0, iclass 7, count 2 2006.257.12:22:45.47#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.12:22:45.47#ibcon#[25=AT05-04\r\n] 2006.257.12:22:45.47#ibcon#*before write, iclass 7, count 2 2006.257.12:22:45.47#ibcon#enter sib2, iclass 7, count 2 2006.257.12:22:45.47#ibcon#flushed, iclass 7, count 2 2006.257.12:22:45.47#ibcon#about to write, iclass 7, count 2 2006.257.12:22:45.47#ibcon#wrote, iclass 7, count 2 2006.257.12:22:45.47#ibcon#about to read 3, iclass 7, count 2 2006.257.12:22:45.50#ibcon#read 3, iclass 7, count 2 2006.257.12:22:45.50#ibcon#about to read 4, iclass 7, count 2 2006.257.12:22:45.50#ibcon#read 4, iclass 7, count 2 2006.257.12:22:45.50#ibcon#about to read 5, iclass 7, count 2 2006.257.12:22:45.50#ibcon#read 5, iclass 7, count 2 2006.257.12:22:45.50#ibcon#about to read 6, iclass 7, count 2 2006.257.12:22:45.50#ibcon#read 6, iclass 7, count 2 2006.257.12:22:45.50#ibcon#end of sib2, iclass 7, count 2 2006.257.12:22:45.50#ibcon#*after write, iclass 7, count 2 2006.257.12:22:45.50#ibcon#*before return 0, iclass 7, count 2 2006.257.12:22:45.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:45.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:45.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.12:22:45.50#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:45.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:45.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:45.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:45.62#ibcon#enter wrdev, iclass 7, count 0 2006.257.12:22:45.62#ibcon#first serial, iclass 7, count 0 2006.257.12:22:45.62#ibcon#enter sib2, iclass 7, count 0 2006.257.12:22:45.62#ibcon#flushed, iclass 7, count 0 2006.257.12:22:45.62#ibcon#about to write, iclass 7, count 0 2006.257.12:22:45.62#ibcon#wrote, iclass 7, count 0 2006.257.12:22:45.62#ibcon#about to read 3, iclass 7, count 0 2006.257.12:22:45.64#ibcon#read 3, iclass 7, count 0 2006.257.12:22:45.64#ibcon#about to read 4, iclass 7, count 0 2006.257.12:22:45.64#ibcon#read 4, iclass 7, count 0 2006.257.12:22:45.64#ibcon#about to read 5, iclass 7, count 0 2006.257.12:22:45.64#ibcon#read 5, iclass 7, count 0 2006.257.12:22:45.64#ibcon#about to read 6, iclass 7, count 0 2006.257.12:22:45.64#ibcon#read 6, iclass 7, count 0 2006.257.12:22:45.64#ibcon#end of sib2, iclass 7, count 0 2006.257.12:22:45.64#ibcon#*mode == 0, iclass 7, count 0 2006.257.12:22:45.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.12:22:45.64#ibcon#[25=USB\r\n] 2006.257.12:22:45.64#ibcon#*before write, iclass 7, count 0 2006.257.12:22:45.64#ibcon#enter sib2, iclass 7, count 0 2006.257.12:22:45.64#ibcon#flushed, iclass 7, count 0 2006.257.12:22:45.64#ibcon#about to write, iclass 7, count 0 2006.257.12:22:45.64#ibcon#wrote, iclass 7, count 0 2006.257.12:22:45.64#ibcon#about to read 3, iclass 7, count 0 2006.257.12:22:45.67#ibcon#read 3, iclass 7, count 0 2006.257.12:22:45.67#ibcon#about to read 4, iclass 7, count 0 2006.257.12:22:45.67#ibcon#read 4, iclass 7, count 0 2006.257.12:22:45.67#ibcon#about to read 5, iclass 7, count 0 2006.257.12:22:45.67#ibcon#read 5, iclass 7, count 0 2006.257.12:22:45.67#ibcon#about to read 6, iclass 7, count 0 2006.257.12:22:45.67#ibcon#read 6, iclass 7, count 0 2006.257.12:22:45.67#ibcon#end of sib2, iclass 7, count 0 2006.257.12:22:45.67#ibcon#*after write, iclass 7, count 0 2006.257.12:22:45.67#ibcon#*before return 0, iclass 7, count 0 2006.257.12:22:45.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:45.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:45.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.12:22:45.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.12:22:45.67$vck44/valo=6,814.99 2006.257.12:22:45.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.12:22:45.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.12:22:45.67#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:45.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:45.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:45.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:45.67#ibcon#enter wrdev, iclass 11, count 0 2006.257.12:22:45.67#ibcon#first serial, iclass 11, count 0 2006.257.12:22:45.67#ibcon#enter sib2, iclass 11, count 0 2006.257.12:22:45.67#ibcon#flushed, iclass 11, count 0 2006.257.12:22:45.67#ibcon#about to write, iclass 11, count 0 2006.257.12:22:45.67#ibcon#wrote, iclass 11, count 0 2006.257.12:22:45.67#ibcon#about to read 3, iclass 11, count 0 2006.257.12:22:45.69#ibcon#read 3, iclass 11, count 0 2006.257.12:22:45.69#ibcon#about to read 4, iclass 11, count 0 2006.257.12:22:45.69#ibcon#read 4, iclass 11, count 0 2006.257.12:22:45.69#ibcon#about to read 5, iclass 11, count 0 2006.257.12:22:45.69#ibcon#read 5, iclass 11, count 0 2006.257.12:22:45.69#ibcon#about to read 6, iclass 11, count 0 2006.257.12:22:45.69#ibcon#read 6, iclass 11, count 0 2006.257.12:22:45.69#ibcon#end of sib2, iclass 11, count 0 2006.257.12:22:45.69#ibcon#*mode == 0, iclass 11, count 0 2006.257.12:22:45.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.12:22:45.69#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:22:45.69#ibcon#*before write, iclass 11, count 0 2006.257.12:22:45.69#ibcon#enter sib2, iclass 11, count 0 2006.257.12:22:45.69#ibcon#flushed, iclass 11, count 0 2006.257.12:22:45.69#ibcon#about to write, iclass 11, count 0 2006.257.12:22:45.69#ibcon#wrote, iclass 11, count 0 2006.257.12:22:45.69#ibcon#about to read 3, iclass 11, count 0 2006.257.12:22:45.73#ibcon#read 3, iclass 11, count 0 2006.257.12:22:45.73#ibcon#about to read 4, iclass 11, count 0 2006.257.12:22:45.73#ibcon#read 4, iclass 11, count 0 2006.257.12:22:45.73#ibcon#about to read 5, iclass 11, count 0 2006.257.12:22:45.73#ibcon#read 5, iclass 11, count 0 2006.257.12:22:45.73#ibcon#about to read 6, iclass 11, count 0 2006.257.12:22:45.73#ibcon#read 6, iclass 11, count 0 2006.257.12:22:45.73#ibcon#end of sib2, iclass 11, count 0 2006.257.12:22:45.73#ibcon#*after write, iclass 11, count 0 2006.257.12:22:45.73#ibcon#*before return 0, iclass 11, count 0 2006.257.12:22:45.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:45.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:45.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.12:22:45.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.12:22:45.73$vck44/va=6,4 2006.257.12:22:45.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.12:22:45.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.12:22:45.73#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:45.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:45.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:45.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:45.79#ibcon#enter wrdev, iclass 13, count 2 2006.257.12:22:45.79#ibcon#first serial, iclass 13, count 2 2006.257.12:22:45.79#ibcon#enter sib2, iclass 13, count 2 2006.257.12:22:45.79#ibcon#flushed, iclass 13, count 2 2006.257.12:22:45.79#ibcon#about to write, iclass 13, count 2 2006.257.12:22:45.79#ibcon#wrote, iclass 13, count 2 2006.257.12:22:45.79#ibcon#about to read 3, iclass 13, count 2 2006.257.12:22:45.81#ibcon#read 3, iclass 13, count 2 2006.257.12:22:45.81#ibcon#about to read 4, iclass 13, count 2 2006.257.12:22:45.81#ibcon#read 4, iclass 13, count 2 2006.257.12:22:45.81#ibcon#about to read 5, iclass 13, count 2 2006.257.12:22:45.81#ibcon#read 5, iclass 13, count 2 2006.257.12:22:45.81#ibcon#about to read 6, iclass 13, count 2 2006.257.12:22:45.81#ibcon#read 6, iclass 13, count 2 2006.257.12:22:45.81#ibcon#end of sib2, iclass 13, count 2 2006.257.12:22:45.81#ibcon#*mode == 0, iclass 13, count 2 2006.257.12:22:45.81#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.12:22:45.81#ibcon#[25=AT06-04\r\n] 2006.257.12:22:45.81#ibcon#*before write, iclass 13, count 2 2006.257.12:22:45.81#ibcon#enter sib2, iclass 13, count 2 2006.257.12:22:45.81#ibcon#flushed, iclass 13, count 2 2006.257.12:22:45.81#ibcon#about to write, iclass 13, count 2 2006.257.12:22:45.81#ibcon#wrote, iclass 13, count 2 2006.257.12:22:45.81#ibcon#about to read 3, iclass 13, count 2 2006.257.12:22:45.84#ibcon#read 3, iclass 13, count 2 2006.257.12:22:45.84#ibcon#about to read 4, iclass 13, count 2 2006.257.12:22:45.84#ibcon#read 4, iclass 13, count 2 2006.257.12:22:45.84#ibcon#about to read 5, iclass 13, count 2 2006.257.12:22:45.84#ibcon#read 5, iclass 13, count 2 2006.257.12:22:45.84#ibcon#about to read 6, iclass 13, count 2 2006.257.12:22:45.84#ibcon#read 6, iclass 13, count 2 2006.257.12:22:45.84#ibcon#end of sib2, iclass 13, count 2 2006.257.12:22:45.84#ibcon#*after write, iclass 13, count 2 2006.257.12:22:45.84#ibcon#*before return 0, iclass 13, count 2 2006.257.12:22:45.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:45.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:45.84#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.12:22:45.84#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:45.84#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:45.96#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:45.96#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:45.96#ibcon#enter wrdev, iclass 13, count 0 2006.257.12:22:45.96#ibcon#first serial, iclass 13, count 0 2006.257.12:22:45.96#ibcon#enter sib2, iclass 13, count 0 2006.257.12:22:45.96#ibcon#flushed, iclass 13, count 0 2006.257.12:22:45.96#ibcon#about to write, iclass 13, count 0 2006.257.12:22:45.96#ibcon#wrote, iclass 13, count 0 2006.257.12:22:45.96#ibcon#about to read 3, iclass 13, count 0 2006.257.12:22:45.98#ibcon#read 3, iclass 13, count 0 2006.257.12:22:45.98#ibcon#about to read 4, iclass 13, count 0 2006.257.12:22:45.98#ibcon#read 4, iclass 13, count 0 2006.257.12:22:45.98#ibcon#about to read 5, iclass 13, count 0 2006.257.12:22:45.98#ibcon#read 5, iclass 13, count 0 2006.257.12:22:45.98#ibcon#about to read 6, iclass 13, count 0 2006.257.12:22:45.98#ibcon#read 6, iclass 13, count 0 2006.257.12:22:45.98#ibcon#end of sib2, iclass 13, count 0 2006.257.12:22:45.98#ibcon#*mode == 0, iclass 13, count 0 2006.257.12:22:45.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.12:22:45.98#ibcon#[25=USB\r\n] 2006.257.12:22:45.98#ibcon#*before write, iclass 13, count 0 2006.257.12:22:45.98#ibcon#enter sib2, iclass 13, count 0 2006.257.12:22:45.98#ibcon#flushed, iclass 13, count 0 2006.257.12:22:45.98#ibcon#about to write, iclass 13, count 0 2006.257.12:22:45.98#ibcon#wrote, iclass 13, count 0 2006.257.12:22:45.98#ibcon#about to read 3, iclass 13, count 0 2006.257.12:22:46.01#ibcon#read 3, iclass 13, count 0 2006.257.12:22:46.01#ibcon#about to read 4, iclass 13, count 0 2006.257.12:22:46.01#ibcon#read 4, iclass 13, count 0 2006.257.12:22:46.01#ibcon#about to read 5, iclass 13, count 0 2006.257.12:22:46.01#ibcon#read 5, iclass 13, count 0 2006.257.12:22:46.01#ibcon#about to read 6, iclass 13, count 0 2006.257.12:22:46.01#ibcon#read 6, iclass 13, count 0 2006.257.12:22:46.01#ibcon#end of sib2, iclass 13, count 0 2006.257.12:22:46.01#ibcon#*after write, iclass 13, count 0 2006.257.12:22:46.01#ibcon#*before return 0, iclass 13, count 0 2006.257.12:22:46.01#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:46.01#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:46.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.12:22:46.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.12:22:46.01$vck44/valo=7,864.99 2006.257.12:22:46.01#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.12:22:46.01#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.12:22:46.01#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:46.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:46.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:46.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:46.01#ibcon#enter wrdev, iclass 15, count 0 2006.257.12:22:46.01#ibcon#first serial, iclass 15, count 0 2006.257.12:22:46.01#ibcon#enter sib2, iclass 15, count 0 2006.257.12:22:46.01#ibcon#flushed, iclass 15, count 0 2006.257.12:22:46.01#ibcon#about to write, iclass 15, count 0 2006.257.12:22:46.01#ibcon#wrote, iclass 15, count 0 2006.257.12:22:46.01#ibcon#about to read 3, iclass 15, count 0 2006.257.12:22:46.03#ibcon#read 3, iclass 15, count 0 2006.257.12:22:46.03#ibcon#about to read 4, iclass 15, count 0 2006.257.12:22:46.03#ibcon#read 4, iclass 15, count 0 2006.257.12:22:46.03#ibcon#about to read 5, iclass 15, count 0 2006.257.12:22:46.03#ibcon#read 5, iclass 15, count 0 2006.257.12:22:46.03#ibcon#about to read 6, iclass 15, count 0 2006.257.12:22:46.03#ibcon#read 6, iclass 15, count 0 2006.257.12:22:46.03#ibcon#end of sib2, iclass 15, count 0 2006.257.12:22:46.03#ibcon#*mode == 0, iclass 15, count 0 2006.257.12:22:46.03#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.12:22:46.03#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:22:46.03#ibcon#*before write, iclass 15, count 0 2006.257.12:22:46.03#ibcon#enter sib2, iclass 15, count 0 2006.257.12:22:46.03#ibcon#flushed, iclass 15, count 0 2006.257.12:22:46.03#ibcon#about to write, iclass 15, count 0 2006.257.12:22:46.03#ibcon#wrote, iclass 15, count 0 2006.257.12:22:46.03#ibcon#about to read 3, iclass 15, count 0 2006.257.12:22:46.07#ibcon#read 3, iclass 15, count 0 2006.257.12:22:46.07#ibcon#about to read 4, iclass 15, count 0 2006.257.12:22:46.07#ibcon#read 4, iclass 15, count 0 2006.257.12:22:46.07#ibcon#about to read 5, iclass 15, count 0 2006.257.12:22:46.07#ibcon#read 5, iclass 15, count 0 2006.257.12:22:46.07#ibcon#about to read 6, iclass 15, count 0 2006.257.12:22:46.07#ibcon#read 6, iclass 15, count 0 2006.257.12:22:46.07#ibcon#end of sib2, iclass 15, count 0 2006.257.12:22:46.07#ibcon#*after write, iclass 15, count 0 2006.257.12:22:46.07#ibcon#*before return 0, iclass 15, count 0 2006.257.12:22:46.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:46.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:46.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.12:22:46.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.12:22:46.07$vck44/va=7,4 2006.257.12:22:46.07#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.12:22:46.07#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.12:22:46.07#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:46.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:46.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:46.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:46.13#ibcon#enter wrdev, iclass 17, count 2 2006.257.12:22:46.13#ibcon#first serial, iclass 17, count 2 2006.257.12:22:46.13#ibcon#enter sib2, iclass 17, count 2 2006.257.12:22:46.13#ibcon#flushed, iclass 17, count 2 2006.257.12:22:46.13#ibcon#about to write, iclass 17, count 2 2006.257.12:22:46.13#ibcon#wrote, iclass 17, count 2 2006.257.12:22:46.13#ibcon#about to read 3, iclass 17, count 2 2006.257.12:22:46.15#ibcon#read 3, iclass 17, count 2 2006.257.12:22:46.15#ibcon#about to read 4, iclass 17, count 2 2006.257.12:22:46.15#ibcon#read 4, iclass 17, count 2 2006.257.12:22:46.15#ibcon#about to read 5, iclass 17, count 2 2006.257.12:22:46.15#ibcon#read 5, iclass 17, count 2 2006.257.12:22:46.15#ibcon#about to read 6, iclass 17, count 2 2006.257.12:22:46.15#ibcon#read 6, iclass 17, count 2 2006.257.12:22:46.15#ibcon#end of sib2, iclass 17, count 2 2006.257.12:22:46.15#ibcon#*mode == 0, iclass 17, count 2 2006.257.12:22:46.15#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.12:22:46.15#ibcon#[25=AT07-04\r\n] 2006.257.12:22:46.15#ibcon#*before write, iclass 17, count 2 2006.257.12:22:46.15#ibcon#enter sib2, iclass 17, count 2 2006.257.12:22:46.15#ibcon#flushed, iclass 17, count 2 2006.257.12:22:46.15#ibcon#about to write, iclass 17, count 2 2006.257.12:22:46.15#ibcon#wrote, iclass 17, count 2 2006.257.12:22:46.15#ibcon#about to read 3, iclass 17, count 2 2006.257.12:22:46.18#ibcon#read 3, iclass 17, count 2 2006.257.12:22:46.18#ibcon#about to read 4, iclass 17, count 2 2006.257.12:22:46.18#ibcon#read 4, iclass 17, count 2 2006.257.12:22:46.18#ibcon#about to read 5, iclass 17, count 2 2006.257.12:22:46.18#ibcon#read 5, iclass 17, count 2 2006.257.12:22:46.18#ibcon#about to read 6, iclass 17, count 2 2006.257.12:22:46.18#ibcon#read 6, iclass 17, count 2 2006.257.12:22:46.18#ibcon#end of sib2, iclass 17, count 2 2006.257.12:22:46.18#ibcon#*after write, iclass 17, count 2 2006.257.12:22:46.18#ibcon#*before return 0, iclass 17, count 2 2006.257.12:22:46.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:46.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:46.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.12:22:46.18#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:46.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:46.30#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:46.30#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:46.30#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:22:46.30#ibcon#first serial, iclass 17, count 0 2006.257.12:22:46.30#ibcon#enter sib2, iclass 17, count 0 2006.257.12:22:46.30#ibcon#flushed, iclass 17, count 0 2006.257.12:22:46.30#ibcon#about to write, iclass 17, count 0 2006.257.12:22:46.30#ibcon#wrote, iclass 17, count 0 2006.257.12:22:46.30#ibcon#about to read 3, iclass 17, count 0 2006.257.12:22:46.32#ibcon#read 3, iclass 17, count 0 2006.257.12:22:46.32#ibcon#about to read 4, iclass 17, count 0 2006.257.12:22:46.32#ibcon#read 4, iclass 17, count 0 2006.257.12:22:46.32#ibcon#about to read 5, iclass 17, count 0 2006.257.12:22:46.32#ibcon#read 5, iclass 17, count 0 2006.257.12:22:46.32#ibcon#about to read 6, iclass 17, count 0 2006.257.12:22:46.32#ibcon#read 6, iclass 17, count 0 2006.257.12:22:46.32#ibcon#end of sib2, iclass 17, count 0 2006.257.12:22:46.32#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:22:46.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:22:46.32#ibcon#[25=USB\r\n] 2006.257.12:22:46.32#ibcon#*before write, iclass 17, count 0 2006.257.12:22:46.32#ibcon#enter sib2, iclass 17, count 0 2006.257.12:22:46.32#ibcon#flushed, iclass 17, count 0 2006.257.12:22:46.32#ibcon#about to write, iclass 17, count 0 2006.257.12:22:46.32#ibcon#wrote, iclass 17, count 0 2006.257.12:22:46.32#ibcon#about to read 3, iclass 17, count 0 2006.257.12:22:46.35#ibcon#read 3, iclass 17, count 0 2006.257.12:22:46.35#ibcon#about to read 4, iclass 17, count 0 2006.257.12:22:46.35#ibcon#read 4, iclass 17, count 0 2006.257.12:22:46.35#ibcon#about to read 5, iclass 17, count 0 2006.257.12:22:46.35#ibcon#read 5, iclass 17, count 0 2006.257.12:22:46.35#ibcon#about to read 6, iclass 17, count 0 2006.257.12:22:46.35#ibcon#read 6, iclass 17, count 0 2006.257.12:22:46.35#ibcon#end of sib2, iclass 17, count 0 2006.257.12:22:46.35#ibcon#*after write, iclass 17, count 0 2006.257.12:22:46.35#ibcon#*before return 0, iclass 17, count 0 2006.257.12:22:46.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:46.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:46.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:22:46.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:22:46.35$vck44/valo=8,884.99 2006.257.12:22:46.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.12:22:46.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.12:22:46.35#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:46.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:46.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:46.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:46.35#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:22:46.35#ibcon#first serial, iclass 19, count 0 2006.257.12:22:46.35#ibcon#enter sib2, iclass 19, count 0 2006.257.12:22:46.35#ibcon#flushed, iclass 19, count 0 2006.257.12:22:46.35#ibcon#about to write, iclass 19, count 0 2006.257.12:22:46.35#ibcon#wrote, iclass 19, count 0 2006.257.12:22:46.35#ibcon#about to read 3, iclass 19, count 0 2006.257.12:22:46.37#ibcon#read 3, iclass 19, count 0 2006.257.12:22:46.37#ibcon#about to read 4, iclass 19, count 0 2006.257.12:22:46.37#ibcon#read 4, iclass 19, count 0 2006.257.12:22:46.37#ibcon#about to read 5, iclass 19, count 0 2006.257.12:22:46.37#ibcon#read 5, iclass 19, count 0 2006.257.12:22:46.37#ibcon#about to read 6, iclass 19, count 0 2006.257.12:22:46.37#ibcon#read 6, iclass 19, count 0 2006.257.12:22:46.37#ibcon#end of sib2, iclass 19, count 0 2006.257.12:22:46.37#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:22:46.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:22:46.37#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:22:46.37#ibcon#*before write, iclass 19, count 0 2006.257.12:22:46.37#ibcon#enter sib2, iclass 19, count 0 2006.257.12:22:46.37#ibcon#flushed, iclass 19, count 0 2006.257.12:22:46.37#ibcon#about to write, iclass 19, count 0 2006.257.12:22:46.37#ibcon#wrote, iclass 19, count 0 2006.257.12:22:46.37#ibcon#about to read 3, iclass 19, count 0 2006.257.12:22:46.41#ibcon#read 3, iclass 19, count 0 2006.257.12:22:46.41#ibcon#about to read 4, iclass 19, count 0 2006.257.12:22:46.41#ibcon#read 4, iclass 19, count 0 2006.257.12:22:46.41#ibcon#about to read 5, iclass 19, count 0 2006.257.12:22:46.41#ibcon#read 5, iclass 19, count 0 2006.257.12:22:46.41#ibcon#about to read 6, iclass 19, count 0 2006.257.12:22:46.41#ibcon#read 6, iclass 19, count 0 2006.257.12:22:46.41#ibcon#end of sib2, iclass 19, count 0 2006.257.12:22:46.41#ibcon#*after write, iclass 19, count 0 2006.257.12:22:46.41#ibcon#*before return 0, iclass 19, count 0 2006.257.12:22:46.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:46.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:46.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:22:46.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:22:46.41$vck44/va=8,4 2006.257.12:22:46.41#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.12:22:46.41#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.12:22:46.41#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:46.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:22:46.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:22:46.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:22:46.47#ibcon#enter wrdev, iclass 21, count 2 2006.257.12:22:46.47#ibcon#first serial, iclass 21, count 2 2006.257.12:22:46.47#ibcon#enter sib2, iclass 21, count 2 2006.257.12:22:46.47#ibcon#flushed, iclass 21, count 2 2006.257.12:22:46.47#ibcon#about to write, iclass 21, count 2 2006.257.12:22:46.47#ibcon#wrote, iclass 21, count 2 2006.257.12:22:46.47#ibcon#about to read 3, iclass 21, count 2 2006.257.12:22:46.49#ibcon#read 3, iclass 21, count 2 2006.257.12:22:46.49#ibcon#about to read 4, iclass 21, count 2 2006.257.12:22:46.49#ibcon#read 4, iclass 21, count 2 2006.257.12:22:46.49#ibcon#about to read 5, iclass 21, count 2 2006.257.12:22:46.49#ibcon#read 5, iclass 21, count 2 2006.257.12:22:46.49#ibcon#about to read 6, iclass 21, count 2 2006.257.12:22:46.49#ibcon#read 6, iclass 21, count 2 2006.257.12:22:46.49#ibcon#end of sib2, iclass 21, count 2 2006.257.12:22:46.49#ibcon#*mode == 0, iclass 21, count 2 2006.257.12:22:46.49#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.12:22:46.49#ibcon#[25=AT08-04\r\n] 2006.257.12:22:46.49#ibcon#*before write, iclass 21, count 2 2006.257.12:22:46.49#ibcon#enter sib2, iclass 21, count 2 2006.257.12:22:46.49#ibcon#flushed, iclass 21, count 2 2006.257.12:22:46.49#ibcon#about to write, iclass 21, count 2 2006.257.12:22:46.49#ibcon#wrote, iclass 21, count 2 2006.257.12:22:46.49#ibcon#about to read 3, iclass 21, count 2 2006.257.12:22:46.52#ibcon#read 3, iclass 21, count 2 2006.257.12:22:46.52#ibcon#about to read 4, iclass 21, count 2 2006.257.12:22:46.52#ibcon#read 4, iclass 21, count 2 2006.257.12:22:46.52#ibcon#about to read 5, iclass 21, count 2 2006.257.12:22:46.52#ibcon#read 5, iclass 21, count 2 2006.257.12:22:46.52#ibcon#about to read 6, iclass 21, count 2 2006.257.12:22:46.52#ibcon#read 6, iclass 21, count 2 2006.257.12:22:46.52#ibcon#end of sib2, iclass 21, count 2 2006.257.12:22:46.52#ibcon#*after write, iclass 21, count 2 2006.257.12:22:46.52#ibcon#*before return 0, iclass 21, count 2 2006.257.12:22:46.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:22:46.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:22:46.52#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.12:22:46.52#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:46.52#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:22:46.64#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:22:46.64#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:22:46.64#ibcon#enter wrdev, iclass 21, count 0 2006.257.12:22:46.64#ibcon#first serial, iclass 21, count 0 2006.257.12:22:46.64#ibcon#enter sib2, iclass 21, count 0 2006.257.12:22:46.64#ibcon#flushed, iclass 21, count 0 2006.257.12:22:46.64#ibcon#about to write, iclass 21, count 0 2006.257.12:22:46.64#ibcon#wrote, iclass 21, count 0 2006.257.12:22:46.64#ibcon#about to read 3, iclass 21, count 0 2006.257.12:22:46.66#ibcon#read 3, iclass 21, count 0 2006.257.12:22:46.66#ibcon#about to read 4, iclass 21, count 0 2006.257.12:22:46.66#ibcon#read 4, iclass 21, count 0 2006.257.12:22:46.66#ibcon#about to read 5, iclass 21, count 0 2006.257.12:22:46.66#ibcon#read 5, iclass 21, count 0 2006.257.12:22:46.66#ibcon#about to read 6, iclass 21, count 0 2006.257.12:22:46.66#ibcon#read 6, iclass 21, count 0 2006.257.12:22:46.66#ibcon#end of sib2, iclass 21, count 0 2006.257.12:22:46.66#ibcon#*mode == 0, iclass 21, count 0 2006.257.12:22:46.66#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.12:22:46.66#ibcon#[25=USB\r\n] 2006.257.12:22:46.66#ibcon#*before write, iclass 21, count 0 2006.257.12:22:46.66#ibcon#enter sib2, iclass 21, count 0 2006.257.12:22:46.66#ibcon#flushed, iclass 21, count 0 2006.257.12:22:46.66#ibcon#about to write, iclass 21, count 0 2006.257.12:22:46.66#ibcon#wrote, iclass 21, count 0 2006.257.12:22:46.66#ibcon#about to read 3, iclass 21, count 0 2006.257.12:22:46.69#ibcon#read 3, iclass 21, count 0 2006.257.12:22:46.69#ibcon#about to read 4, iclass 21, count 0 2006.257.12:22:46.69#ibcon#read 4, iclass 21, count 0 2006.257.12:22:46.69#ibcon#about to read 5, iclass 21, count 0 2006.257.12:22:46.69#ibcon#read 5, iclass 21, count 0 2006.257.12:22:46.69#ibcon#about to read 6, iclass 21, count 0 2006.257.12:22:46.69#ibcon#read 6, iclass 21, count 0 2006.257.12:22:46.69#ibcon#end of sib2, iclass 21, count 0 2006.257.12:22:46.69#ibcon#*after write, iclass 21, count 0 2006.257.12:22:46.69#ibcon#*before return 0, iclass 21, count 0 2006.257.12:22:46.69#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:22:46.69#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:22:46.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.12:22:46.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.12:22:46.69$vck44/vblo=1,629.99 2006.257.12:22:46.69#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.12:22:46.69#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.12:22:46.69#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:46.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:46.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:46.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:46.69#ibcon#enter wrdev, iclass 23, count 0 2006.257.12:22:46.69#ibcon#first serial, iclass 23, count 0 2006.257.12:22:46.69#ibcon#enter sib2, iclass 23, count 0 2006.257.12:22:46.69#ibcon#flushed, iclass 23, count 0 2006.257.12:22:46.69#ibcon#about to write, iclass 23, count 0 2006.257.12:22:46.69#ibcon#wrote, iclass 23, count 0 2006.257.12:22:46.69#ibcon#about to read 3, iclass 23, count 0 2006.257.12:22:46.71#ibcon#read 3, iclass 23, count 0 2006.257.12:22:46.71#ibcon#about to read 4, iclass 23, count 0 2006.257.12:22:46.71#ibcon#read 4, iclass 23, count 0 2006.257.12:22:46.71#ibcon#about to read 5, iclass 23, count 0 2006.257.12:22:46.71#ibcon#read 5, iclass 23, count 0 2006.257.12:22:46.71#ibcon#about to read 6, iclass 23, count 0 2006.257.12:22:46.71#ibcon#read 6, iclass 23, count 0 2006.257.12:22:46.71#ibcon#end of sib2, iclass 23, count 0 2006.257.12:22:46.71#ibcon#*mode == 0, iclass 23, count 0 2006.257.12:22:46.71#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.12:22:46.71#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:22:46.71#ibcon#*before write, iclass 23, count 0 2006.257.12:22:46.71#ibcon#enter sib2, iclass 23, count 0 2006.257.12:22:46.71#ibcon#flushed, iclass 23, count 0 2006.257.12:22:46.71#ibcon#about to write, iclass 23, count 0 2006.257.12:22:46.71#ibcon#wrote, iclass 23, count 0 2006.257.12:22:46.71#ibcon#about to read 3, iclass 23, count 0 2006.257.12:22:46.75#ibcon#read 3, iclass 23, count 0 2006.257.12:22:46.75#ibcon#about to read 4, iclass 23, count 0 2006.257.12:22:46.75#ibcon#read 4, iclass 23, count 0 2006.257.12:22:46.75#ibcon#about to read 5, iclass 23, count 0 2006.257.12:22:46.75#ibcon#read 5, iclass 23, count 0 2006.257.12:22:46.75#ibcon#about to read 6, iclass 23, count 0 2006.257.12:22:46.75#ibcon#read 6, iclass 23, count 0 2006.257.12:22:46.75#ibcon#end of sib2, iclass 23, count 0 2006.257.12:22:46.75#ibcon#*after write, iclass 23, count 0 2006.257.12:22:46.75#ibcon#*before return 0, iclass 23, count 0 2006.257.12:22:46.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:46.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:22:46.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.12:22:46.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.12:22:46.75$vck44/vb=1,4 2006.257.12:22:46.75#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.12:22:46.75#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.12:22:46.75#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:46.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:46.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:46.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:46.75#ibcon#enter wrdev, iclass 25, count 2 2006.257.12:22:46.75#ibcon#first serial, iclass 25, count 2 2006.257.12:22:46.75#ibcon#enter sib2, iclass 25, count 2 2006.257.12:22:46.75#ibcon#flushed, iclass 25, count 2 2006.257.12:22:46.75#ibcon#about to write, iclass 25, count 2 2006.257.12:22:46.75#ibcon#wrote, iclass 25, count 2 2006.257.12:22:46.75#ibcon#about to read 3, iclass 25, count 2 2006.257.12:22:46.77#ibcon#read 3, iclass 25, count 2 2006.257.12:22:46.77#ibcon#about to read 4, iclass 25, count 2 2006.257.12:22:46.77#ibcon#read 4, iclass 25, count 2 2006.257.12:22:46.77#ibcon#about to read 5, iclass 25, count 2 2006.257.12:22:46.77#ibcon#read 5, iclass 25, count 2 2006.257.12:22:46.77#ibcon#about to read 6, iclass 25, count 2 2006.257.12:22:46.77#ibcon#read 6, iclass 25, count 2 2006.257.12:22:46.77#ibcon#end of sib2, iclass 25, count 2 2006.257.12:22:46.77#ibcon#*mode == 0, iclass 25, count 2 2006.257.12:22:46.77#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.12:22:46.77#ibcon#[27=AT01-04\r\n] 2006.257.12:22:46.77#ibcon#*before write, iclass 25, count 2 2006.257.12:22:46.77#ibcon#enter sib2, iclass 25, count 2 2006.257.12:22:46.77#ibcon#flushed, iclass 25, count 2 2006.257.12:22:46.77#ibcon#about to write, iclass 25, count 2 2006.257.12:22:46.77#ibcon#wrote, iclass 25, count 2 2006.257.12:22:46.77#ibcon#about to read 3, iclass 25, count 2 2006.257.12:22:46.80#ibcon#read 3, iclass 25, count 2 2006.257.12:22:46.80#ibcon#about to read 4, iclass 25, count 2 2006.257.12:22:46.80#ibcon#read 4, iclass 25, count 2 2006.257.12:22:46.80#ibcon#about to read 5, iclass 25, count 2 2006.257.12:22:46.80#ibcon#read 5, iclass 25, count 2 2006.257.12:22:46.80#ibcon#about to read 6, iclass 25, count 2 2006.257.12:22:46.80#ibcon#read 6, iclass 25, count 2 2006.257.12:22:46.80#ibcon#end of sib2, iclass 25, count 2 2006.257.12:22:46.80#ibcon#*after write, iclass 25, count 2 2006.257.12:22:46.80#ibcon#*before return 0, iclass 25, count 2 2006.257.12:22:46.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:46.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:22:46.80#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.12:22:46.80#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:46.80#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:46.92#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:46.92#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:46.92#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:22:46.92#ibcon#first serial, iclass 25, count 0 2006.257.12:22:46.92#ibcon#enter sib2, iclass 25, count 0 2006.257.12:22:46.92#ibcon#flushed, iclass 25, count 0 2006.257.12:22:46.92#ibcon#about to write, iclass 25, count 0 2006.257.12:22:46.92#ibcon#wrote, iclass 25, count 0 2006.257.12:22:46.92#ibcon#about to read 3, iclass 25, count 0 2006.257.12:22:46.94#ibcon#read 3, iclass 25, count 0 2006.257.12:22:46.94#ibcon#about to read 4, iclass 25, count 0 2006.257.12:22:46.94#ibcon#read 4, iclass 25, count 0 2006.257.12:22:46.94#ibcon#about to read 5, iclass 25, count 0 2006.257.12:22:46.94#ibcon#read 5, iclass 25, count 0 2006.257.12:22:46.94#ibcon#about to read 6, iclass 25, count 0 2006.257.12:22:46.94#ibcon#read 6, iclass 25, count 0 2006.257.12:22:46.94#ibcon#end of sib2, iclass 25, count 0 2006.257.12:22:46.94#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:22:46.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:22:46.94#ibcon#[27=USB\r\n] 2006.257.12:22:46.94#ibcon#*before write, iclass 25, count 0 2006.257.12:22:46.94#ibcon#enter sib2, iclass 25, count 0 2006.257.12:22:46.94#ibcon#flushed, iclass 25, count 0 2006.257.12:22:46.94#ibcon#about to write, iclass 25, count 0 2006.257.12:22:46.94#ibcon#wrote, iclass 25, count 0 2006.257.12:22:46.94#ibcon#about to read 3, iclass 25, count 0 2006.257.12:22:46.97#ibcon#read 3, iclass 25, count 0 2006.257.12:22:46.97#ibcon#about to read 4, iclass 25, count 0 2006.257.12:22:46.97#ibcon#read 4, iclass 25, count 0 2006.257.12:22:46.97#ibcon#about to read 5, iclass 25, count 0 2006.257.12:22:46.97#ibcon#read 5, iclass 25, count 0 2006.257.12:22:46.97#ibcon#about to read 6, iclass 25, count 0 2006.257.12:22:46.97#ibcon#read 6, iclass 25, count 0 2006.257.12:22:46.97#ibcon#end of sib2, iclass 25, count 0 2006.257.12:22:46.97#ibcon#*after write, iclass 25, count 0 2006.257.12:22:46.97#ibcon#*before return 0, iclass 25, count 0 2006.257.12:22:46.97#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:46.97#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:22:46.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:22:46.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:22:46.97$vck44/vblo=2,634.99 2006.257.12:22:46.97#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.12:22:46.97#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.12:22:46.97#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:46.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:46.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:46.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:46.97#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:22:46.97#ibcon#first serial, iclass 27, count 0 2006.257.12:22:46.97#ibcon#enter sib2, iclass 27, count 0 2006.257.12:22:46.97#ibcon#flushed, iclass 27, count 0 2006.257.12:22:46.97#ibcon#about to write, iclass 27, count 0 2006.257.12:22:46.97#ibcon#wrote, iclass 27, count 0 2006.257.12:22:46.97#ibcon#about to read 3, iclass 27, count 0 2006.257.12:22:46.99#ibcon#read 3, iclass 27, count 0 2006.257.12:22:46.99#ibcon#about to read 4, iclass 27, count 0 2006.257.12:22:46.99#ibcon#read 4, iclass 27, count 0 2006.257.12:22:46.99#ibcon#about to read 5, iclass 27, count 0 2006.257.12:22:46.99#ibcon#read 5, iclass 27, count 0 2006.257.12:22:46.99#ibcon#about to read 6, iclass 27, count 0 2006.257.12:22:46.99#ibcon#read 6, iclass 27, count 0 2006.257.12:22:46.99#ibcon#end of sib2, iclass 27, count 0 2006.257.12:22:46.99#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:22:46.99#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:22:46.99#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:22:46.99#ibcon#*before write, iclass 27, count 0 2006.257.12:22:46.99#ibcon#enter sib2, iclass 27, count 0 2006.257.12:22:46.99#ibcon#flushed, iclass 27, count 0 2006.257.12:22:46.99#ibcon#about to write, iclass 27, count 0 2006.257.12:22:46.99#ibcon#wrote, iclass 27, count 0 2006.257.12:22:46.99#ibcon#about to read 3, iclass 27, count 0 2006.257.12:22:47.03#ibcon#read 3, iclass 27, count 0 2006.257.12:22:47.03#ibcon#about to read 4, iclass 27, count 0 2006.257.12:22:47.03#ibcon#read 4, iclass 27, count 0 2006.257.12:22:47.03#ibcon#about to read 5, iclass 27, count 0 2006.257.12:22:47.03#ibcon#read 5, iclass 27, count 0 2006.257.12:22:47.03#ibcon#about to read 6, iclass 27, count 0 2006.257.12:22:47.03#ibcon#read 6, iclass 27, count 0 2006.257.12:22:47.03#ibcon#end of sib2, iclass 27, count 0 2006.257.12:22:47.03#ibcon#*after write, iclass 27, count 0 2006.257.12:22:47.03#ibcon#*before return 0, iclass 27, count 0 2006.257.12:22:47.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:47.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:22:47.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:22:47.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:22:47.03$vck44/vb=2,5 2006.257.12:22:47.03#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.12:22:47.03#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.12:22:47.03#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:47.03#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:47.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:47.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:47.09#ibcon#enter wrdev, iclass 29, count 2 2006.257.12:22:47.09#ibcon#first serial, iclass 29, count 2 2006.257.12:22:47.09#ibcon#enter sib2, iclass 29, count 2 2006.257.12:22:47.09#ibcon#flushed, iclass 29, count 2 2006.257.12:22:47.09#ibcon#about to write, iclass 29, count 2 2006.257.12:22:47.09#ibcon#wrote, iclass 29, count 2 2006.257.12:22:47.09#ibcon#about to read 3, iclass 29, count 2 2006.257.12:22:47.11#ibcon#read 3, iclass 29, count 2 2006.257.12:22:47.11#ibcon#about to read 4, iclass 29, count 2 2006.257.12:22:47.11#ibcon#read 4, iclass 29, count 2 2006.257.12:22:47.11#ibcon#about to read 5, iclass 29, count 2 2006.257.12:22:47.11#ibcon#read 5, iclass 29, count 2 2006.257.12:22:47.11#ibcon#about to read 6, iclass 29, count 2 2006.257.12:22:47.11#ibcon#read 6, iclass 29, count 2 2006.257.12:22:47.11#ibcon#end of sib2, iclass 29, count 2 2006.257.12:22:47.11#ibcon#*mode == 0, iclass 29, count 2 2006.257.12:22:47.11#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.12:22:47.11#ibcon#[27=AT02-05\r\n] 2006.257.12:22:47.11#ibcon#*before write, iclass 29, count 2 2006.257.12:22:47.11#ibcon#enter sib2, iclass 29, count 2 2006.257.12:22:47.11#ibcon#flushed, iclass 29, count 2 2006.257.12:22:47.11#ibcon#about to write, iclass 29, count 2 2006.257.12:22:47.11#ibcon#wrote, iclass 29, count 2 2006.257.12:22:47.11#ibcon#about to read 3, iclass 29, count 2 2006.257.12:22:47.14#ibcon#read 3, iclass 29, count 2 2006.257.12:22:47.14#ibcon#about to read 4, iclass 29, count 2 2006.257.12:22:47.14#ibcon#read 4, iclass 29, count 2 2006.257.12:22:47.14#ibcon#about to read 5, iclass 29, count 2 2006.257.12:22:47.14#ibcon#read 5, iclass 29, count 2 2006.257.12:22:47.14#ibcon#about to read 6, iclass 29, count 2 2006.257.12:22:47.14#ibcon#read 6, iclass 29, count 2 2006.257.12:22:47.14#ibcon#end of sib2, iclass 29, count 2 2006.257.12:22:47.14#ibcon#*after write, iclass 29, count 2 2006.257.12:22:47.14#ibcon#*before return 0, iclass 29, count 2 2006.257.12:22:47.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:47.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:22:47.14#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.12:22:47.14#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:47.14#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:47.26#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:47.26#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:47.26#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:22:47.26#ibcon#first serial, iclass 29, count 0 2006.257.12:22:47.26#ibcon#enter sib2, iclass 29, count 0 2006.257.12:22:47.26#ibcon#flushed, iclass 29, count 0 2006.257.12:22:47.26#ibcon#about to write, iclass 29, count 0 2006.257.12:22:47.26#ibcon#wrote, iclass 29, count 0 2006.257.12:22:47.26#ibcon#about to read 3, iclass 29, count 0 2006.257.12:22:47.28#ibcon#read 3, iclass 29, count 0 2006.257.12:22:47.28#ibcon#about to read 4, iclass 29, count 0 2006.257.12:22:47.28#ibcon#read 4, iclass 29, count 0 2006.257.12:22:47.28#ibcon#about to read 5, iclass 29, count 0 2006.257.12:22:47.28#ibcon#read 5, iclass 29, count 0 2006.257.12:22:47.28#ibcon#about to read 6, iclass 29, count 0 2006.257.12:22:47.28#ibcon#read 6, iclass 29, count 0 2006.257.12:22:47.28#ibcon#end of sib2, iclass 29, count 0 2006.257.12:22:47.28#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:22:47.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:22:47.28#ibcon#[27=USB\r\n] 2006.257.12:22:47.28#ibcon#*before write, iclass 29, count 0 2006.257.12:22:47.28#ibcon#enter sib2, iclass 29, count 0 2006.257.12:22:47.28#ibcon#flushed, iclass 29, count 0 2006.257.12:22:47.28#ibcon#about to write, iclass 29, count 0 2006.257.12:22:47.28#ibcon#wrote, iclass 29, count 0 2006.257.12:22:47.28#ibcon#about to read 3, iclass 29, count 0 2006.257.12:22:47.31#ibcon#read 3, iclass 29, count 0 2006.257.12:22:47.31#ibcon#about to read 4, iclass 29, count 0 2006.257.12:22:47.31#ibcon#read 4, iclass 29, count 0 2006.257.12:22:47.31#ibcon#about to read 5, iclass 29, count 0 2006.257.12:22:47.31#ibcon#read 5, iclass 29, count 0 2006.257.12:22:47.31#ibcon#about to read 6, iclass 29, count 0 2006.257.12:22:47.31#ibcon#read 6, iclass 29, count 0 2006.257.12:22:47.31#ibcon#end of sib2, iclass 29, count 0 2006.257.12:22:47.31#ibcon#*after write, iclass 29, count 0 2006.257.12:22:47.31#ibcon#*before return 0, iclass 29, count 0 2006.257.12:22:47.31#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:47.31#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:22:47.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:22:47.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:22:47.31$vck44/vblo=3,649.99 2006.257.12:22:47.31#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.12:22:47.31#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.12:22:47.31#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:47.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:22:47.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:22:47.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:22:47.31#ibcon#enter wrdev, iclass 31, count 0 2006.257.12:22:47.31#ibcon#first serial, iclass 31, count 0 2006.257.12:22:47.31#ibcon#enter sib2, iclass 31, count 0 2006.257.12:22:47.31#ibcon#flushed, iclass 31, count 0 2006.257.12:22:47.31#ibcon#about to write, iclass 31, count 0 2006.257.12:22:47.31#ibcon#wrote, iclass 31, count 0 2006.257.12:22:47.31#ibcon#about to read 3, iclass 31, count 0 2006.257.12:22:47.33#ibcon#read 3, iclass 31, count 0 2006.257.12:22:47.33#ibcon#about to read 4, iclass 31, count 0 2006.257.12:22:47.33#ibcon#read 4, iclass 31, count 0 2006.257.12:22:47.33#ibcon#about to read 5, iclass 31, count 0 2006.257.12:22:47.33#ibcon#read 5, iclass 31, count 0 2006.257.12:22:47.33#ibcon#about to read 6, iclass 31, count 0 2006.257.12:22:47.33#ibcon#read 6, iclass 31, count 0 2006.257.12:22:47.33#ibcon#end of sib2, iclass 31, count 0 2006.257.12:22:47.33#ibcon#*mode == 0, iclass 31, count 0 2006.257.12:22:47.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.12:22:47.33#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:22:47.33#ibcon#*before write, iclass 31, count 0 2006.257.12:22:47.33#ibcon#enter sib2, iclass 31, count 0 2006.257.12:22:47.33#ibcon#flushed, iclass 31, count 0 2006.257.12:22:47.33#ibcon#about to write, iclass 31, count 0 2006.257.12:22:47.33#ibcon#wrote, iclass 31, count 0 2006.257.12:22:47.33#ibcon#about to read 3, iclass 31, count 0 2006.257.12:22:47.37#ibcon#read 3, iclass 31, count 0 2006.257.12:22:47.37#ibcon#about to read 4, iclass 31, count 0 2006.257.12:22:47.37#ibcon#read 4, iclass 31, count 0 2006.257.12:22:47.37#ibcon#about to read 5, iclass 31, count 0 2006.257.12:22:47.37#ibcon#read 5, iclass 31, count 0 2006.257.12:22:47.37#ibcon#about to read 6, iclass 31, count 0 2006.257.12:22:47.37#ibcon#read 6, iclass 31, count 0 2006.257.12:22:47.37#ibcon#end of sib2, iclass 31, count 0 2006.257.12:22:47.37#ibcon#*after write, iclass 31, count 0 2006.257.12:22:47.37#ibcon#*before return 0, iclass 31, count 0 2006.257.12:22:47.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:22:47.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:22:47.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.12:22:47.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.12:22:47.37$vck44/vb=3,4 2006.257.12:22:47.37#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.12:22:47.37#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.12:22:47.37#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:47.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:22:47.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:22:47.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:22:47.43#ibcon#enter wrdev, iclass 33, count 2 2006.257.12:22:47.43#ibcon#first serial, iclass 33, count 2 2006.257.12:22:47.43#ibcon#enter sib2, iclass 33, count 2 2006.257.12:22:47.43#ibcon#flushed, iclass 33, count 2 2006.257.12:22:47.43#ibcon#about to write, iclass 33, count 2 2006.257.12:22:47.43#ibcon#wrote, iclass 33, count 2 2006.257.12:22:47.43#ibcon#about to read 3, iclass 33, count 2 2006.257.12:22:47.45#ibcon#read 3, iclass 33, count 2 2006.257.12:22:47.45#ibcon#about to read 4, iclass 33, count 2 2006.257.12:22:47.45#ibcon#read 4, iclass 33, count 2 2006.257.12:22:47.45#ibcon#about to read 5, iclass 33, count 2 2006.257.12:22:47.45#ibcon#read 5, iclass 33, count 2 2006.257.12:22:47.45#ibcon#about to read 6, iclass 33, count 2 2006.257.12:22:47.45#ibcon#read 6, iclass 33, count 2 2006.257.12:22:47.45#ibcon#end of sib2, iclass 33, count 2 2006.257.12:22:47.45#ibcon#*mode == 0, iclass 33, count 2 2006.257.12:22:47.45#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.12:22:47.45#ibcon#[27=AT03-04\r\n] 2006.257.12:22:47.45#ibcon#*before write, iclass 33, count 2 2006.257.12:22:47.45#ibcon#enter sib2, iclass 33, count 2 2006.257.12:22:47.45#ibcon#flushed, iclass 33, count 2 2006.257.12:22:47.45#ibcon#about to write, iclass 33, count 2 2006.257.12:22:47.45#ibcon#wrote, iclass 33, count 2 2006.257.12:22:47.45#ibcon#about to read 3, iclass 33, count 2 2006.257.12:22:47.48#ibcon#read 3, iclass 33, count 2 2006.257.12:22:47.48#ibcon#about to read 4, iclass 33, count 2 2006.257.12:22:47.48#ibcon#read 4, iclass 33, count 2 2006.257.12:22:47.48#ibcon#about to read 5, iclass 33, count 2 2006.257.12:22:47.48#ibcon#read 5, iclass 33, count 2 2006.257.12:22:47.48#ibcon#about to read 6, iclass 33, count 2 2006.257.12:22:47.48#ibcon#read 6, iclass 33, count 2 2006.257.12:22:47.48#ibcon#end of sib2, iclass 33, count 2 2006.257.12:22:47.48#ibcon#*after write, iclass 33, count 2 2006.257.12:22:47.48#ibcon#*before return 0, iclass 33, count 2 2006.257.12:22:47.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:22:47.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:22:47.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.12:22:47.48#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:47.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:22:47.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:22:47.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:22:47.60#ibcon#enter wrdev, iclass 33, count 0 2006.257.12:22:47.60#ibcon#first serial, iclass 33, count 0 2006.257.12:22:47.60#ibcon#enter sib2, iclass 33, count 0 2006.257.12:22:47.60#ibcon#flushed, iclass 33, count 0 2006.257.12:22:47.60#ibcon#about to write, iclass 33, count 0 2006.257.12:22:47.60#ibcon#wrote, iclass 33, count 0 2006.257.12:22:47.60#ibcon#about to read 3, iclass 33, count 0 2006.257.12:22:47.62#ibcon#read 3, iclass 33, count 0 2006.257.12:22:47.62#ibcon#about to read 4, iclass 33, count 0 2006.257.12:22:47.62#ibcon#read 4, iclass 33, count 0 2006.257.12:22:47.62#ibcon#about to read 5, iclass 33, count 0 2006.257.12:22:47.62#ibcon#read 5, iclass 33, count 0 2006.257.12:22:47.62#ibcon#about to read 6, iclass 33, count 0 2006.257.12:22:47.62#ibcon#read 6, iclass 33, count 0 2006.257.12:22:47.62#ibcon#end of sib2, iclass 33, count 0 2006.257.12:22:47.62#ibcon#*mode == 0, iclass 33, count 0 2006.257.12:22:47.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.12:22:47.62#ibcon#[27=USB\r\n] 2006.257.12:22:47.62#ibcon#*before write, iclass 33, count 0 2006.257.12:22:47.62#ibcon#enter sib2, iclass 33, count 0 2006.257.12:22:47.62#ibcon#flushed, iclass 33, count 0 2006.257.12:22:47.62#ibcon#about to write, iclass 33, count 0 2006.257.12:22:47.62#ibcon#wrote, iclass 33, count 0 2006.257.12:22:47.62#ibcon#about to read 3, iclass 33, count 0 2006.257.12:22:47.65#ibcon#read 3, iclass 33, count 0 2006.257.12:22:47.65#ibcon#about to read 4, iclass 33, count 0 2006.257.12:22:47.65#ibcon#read 4, iclass 33, count 0 2006.257.12:22:47.65#ibcon#about to read 5, iclass 33, count 0 2006.257.12:22:47.65#ibcon#read 5, iclass 33, count 0 2006.257.12:22:47.65#ibcon#about to read 6, iclass 33, count 0 2006.257.12:22:47.65#ibcon#read 6, iclass 33, count 0 2006.257.12:22:47.65#ibcon#end of sib2, iclass 33, count 0 2006.257.12:22:47.65#ibcon#*after write, iclass 33, count 0 2006.257.12:22:47.65#ibcon#*before return 0, iclass 33, count 0 2006.257.12:22:47.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:22:47.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:22:47.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.12:22:47.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.12:22:47.65$vck44/vblo=4,679.99 2006.257.12:22:47.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.12:22:47.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.12:22:47.65#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:47.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:22:47.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:22:47.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:22:47.65#ibcon#enter wrdev, iclass 35, count 0 2006.257.12:22:47.65#ibcon#first serial, iclass 35, count 0 2006.257.12:22:47.65#ibcon#enter sib2, iclass 35, count 0 2006.257.12:22:47.65#ibcon#flushed, iclass 35, count 0 2006.257.12:22:47.65#ibcon#about to write, iclass 35, count 0 2006.257.12:22:47.65#ibcon#wrote, iclass 35, count 0 2006.257.12:22:47.65#ibcon#about to read 3, iclass 35, count 0 2006.257.12:22:47.67#ibcon#read 3, iclass 35, count 0 2006.257.12:22:47.67#ibcon#about to read 4, iclass 35, count 0 2006.257.12:22:47.67#ibcon#read 4, iclass 35, count 0 2006.257.12:22:47.67#ibcon#about to read 5, iclass 35, count 0 2006.257.12:22:47.67#ibcon#read 5, iclass 35, count 0 2006.257.12:22:47.67#ibcon#about to read 6, iclass 35, count 0 2006.257.12:22:47.67#ibcon#read 6, iclass 35, count 0 2006.257.12:22:47.67#ibcon#end of sib2, iclass 35, count 0 2006.257.12:22:47.67#ibcon#*mode == 0, iclass 35, count 0 2006.257.12:22:47.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.12:22:47.67#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:22:47.67#ibcon#*before write, iclass 35, count 0 2006.257.12:22:47.67#ibcon#enter sib2, iclass 35, count 0 2006.257.12:22:47.67#ibcon#flushed, iclass 35, count 0 2006.257.12:22:47.67#ibcon#about to write, iclass 35, count 0 2006.257.12:22:47.67#ibcon#wrote, iclass 35, count 0 2006.257.12:22:47.67#ibcon#about to read 3, iclass 35, count 0 2006.257.12:22:47.71#ibcon#read 3, iclass 35, count 0 2006.257.12:22:47.71#ibcon#about to read 4, iclass 35, count 0 2006.257.12:22:47.71#ibcon#read 4, iclass 35, count 0 2006.257.12:22:47.71#ibcon#about to read 5, iclass 35, count 0 2006.257.12:22:47.71#ibcon#read 5, iclass 35, count 0 2006.257.12:22:47.71#ibcon#about to read 6, iclass 35, count 0 2006.257.12:22:47.71#ibcon#read 6, iclass 35, count 0 2006.257.12:22:47.71#ibcon#end of sib2, iclass 35, count 0 2006.257.12:22:47.71#ibcon#*after write, iclass 35, count 0 2006.257.12:22:47.71#ibcon#*before return 0, iclass 35, count 0 2006.257.12:22:47.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:22:47.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:22:47.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.12:22:47.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.12:22:47.71$vck44/vb=4,5 2006.257.12:22:47.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.12:22:47.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.12:22:47.71#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:47.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:47.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:47.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:47.77#ibcon#enter wrdev, iclass 37, count 2 2006.257.12:22:47.77#ibcon#first serial, iclass 37, count 2 2006.257.12:22:47.77#ibcon#enter sib2, iclass 37, count 2 2006.257.12:22:47.77#ibcon#flushed, iclass 37, count 2 2006.257.12:22:47.77#ibcon#about to write, iclass 37, count 2 2006.257.12:22:47.77#ibcon#wrote, iclass 37, count 2 2006.257.12:22:47.77#ibcon#about to read 3, iclass 37, count 2 2006.257.12:22:47.79#ibcon#read 3, iclass 37, count 2 2006.257.12:22:47.79#ibcon#about to read 4, iclass 37, count 2 2006.257.12:22:47.79#ibcon#read 4, iclass 37, count 2 2006.257.12:22:47.79#ibcon#about to read 5, iclass 37, count 2 2006.257.12:22:47.79#ibcon#read 5, iclass 37, count 2 2006.257.12:22:47.79#ibcon#about to read 6, iclass 37, count 2 2006.257.12:22:47.79#ibcon#read 6, iclass 37, count 2 2006.257.12:22:47.79#ibcon#end of sib2, iclass 37, count 2 2006.257.12:22:47.79#ibcon#*mode == 0, iclass 37, count 2 2006.257.12:22:47.79#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.12:22:47.79#ibcon#[27=AT04-05\r\n] 2006.257.12:22:47.79#ibcon#*before write, iclass 37, count 2 2006.257.12:22:47.79#ibcon#enter sib2, iclass 37, count 2 2006.257.12:22:47.79#ibcon#flushed, iclass 37, count 2 2006.257.12:22:47.79#ibcon#about to write, iclass 37, count 2 2006.257.12:22:47.79#ibcon#wrote, iclass 37, count 2 2006.257.12:22:47.79#ibcon#about to read 3, iclass 37, count 2 2006.257.12:22:47.82#ibcon#read 3, iclass 37, count 2 2006.257.12:22:47.82#ibcon#about to read 4, iclass 37, count 2 2006.257.12:22:47.82#ibcon#read 4, iclass 37, count 2 2006.257.12:22:47.82#ibcon#about to read 5, iclass 37, count 2 2006.257.12:22:47.82#ibcon#read 5, iclass 37, count 2 2006.257.12:22:47.82#ibcon#about to read 6, iclass 37, count 2 2006.257.12:22:47.82#ibcon#read 6, iclass 37, count 2 2006.257.12:22:47.82#ibcon#end of sib2, iclass 37, count 2 2006.257.12:22:47.82#ibcon#*after write, iclass 37, count 2 2006.257.12:22:47.82#ibcon#*before return 0, iclass 37, count 2 2006.257.12:22:47.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:47.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:22:47.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.12:22:47.82#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:47.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:47.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:47.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:47.94#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:22:47.94#ibcon#first serial, iclass 37, count 0 2006.257.12:22:47.94#ibcon#enter sib2, iclass 37, count 0 2006.257.12:22:47.94#ibcon#flushed, iclass 37, count 0 2006.257.12:22:47.94#ibcon#about to write, iclass 37, count 0 2006.257.12:22:47.94#ibcon#wrote, iclass 37, count 0 2006.257.12:22:47.94#ibcon#about to read 3, iclass 37, count 0 2006.257.12:22:47.96#ibcon#read 3, iclass 37, count 0 2006.257.12:22:47.96#ibcon#about to read 4, iclass 37, count 0 2006.257.12:22:47.96#ibcon#read 4, iclass 37, count 0 2006.257.12:22:47.96#ibcon#about to read 5, iclass 37, count 0 2006.257.12:22:47.96#ibcon#read 5, iclass 37, count 0 2006.257.12:22:47.96#ibcon#about to read 6, iclass 37, count 0 2006.257.12:22:47.96#ibcon#read 6, iclass 37, count 0 2006.257.12:22:47.96#ibcon#end of sib2, iclass 37, count 0 2006.257.12:22:47.96#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:22:47.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:22:47.96#ibcon#[27=USB\r\n] 2006.257.12:22:47.96#ibcon#*before write, iclass 37, count 0 2006.257.12:22:47.96#ibcon#enter sib2, iclass 37, count 0 2006.257.12:22:47.96#ibcon#flushed, iclass 37, count 0 2006.257.12:22:47.96#ibcon#about to write, iclass 37, count 0 2006.257.12:22:47.96#ibcon#wrote, iclass 37, count 0 2006.257.12:22:47.96#ibcon#about to read 3, iclass 37, count 0 2006.257.12:22:47.99#ibcon#read 3, iclass 37, count 0 2006.257.12:22:47.99#ibcon#about to read 4, iclass 37, count 0 2006.257.12:22:47.99#ibcon#read 4, iclass 37, count 0 2006.257.12:22:47.99#ibcon#about to read 5, iclass 37, count 0 2006.257.12:22:47.99#ibcon#read 5, iclass 37, count 0 2006.257.12:22:47.99#ibcon#about to read 6, iclass 37, count 0 2006.257.12:22:47.99#ibcon#read 6, iclass 37, count 0 2006.257.12:22:47.99#ibcon#end of sib2, iclass 37, count 0 2006.257.12:22:47.99#ibcon#*after write, iclass 37, count 0 2006.257.12:22:47.99#ibcon#*before return 0, iclass 37, count 0 2006.257.12:22:47.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:47.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:22:47.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:22:47.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:22:47.99$vck44/vblo=5,709.99 2006.257.12:22:47.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.12:22:47.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.12:22:47.99#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:47.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:47.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:47.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:47.99#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:22:47.99#ibcon#first serial, iclass 39, count 0 2006.257.12:22:47.99#ibcon#enter sib2, iclass 39, count 0 2006.257.12:22:47.99#ibcon#flushed, iclass 39, count 0 2006.257.12:22:47.99#ibcon#about to write, iclass 39, count 0 2006.257.12:22:47.99#ibcon#wrote, iclass 39, count 0 2006.257.12:22:47.99#ibcon#about to read 3, iclass 39, count 0 2006.257.12:22:48.01#ibcon#read 3, iclass 39, count 0 2006.257.12:22:48.01#ibcon#about to read 4, iclass 39, count 0 2006.257.12:22:48.01#ibcon#read 4, iclass 39, count 0 2006.257.12:22:48.01#ibcon#about to read 5, iclass 39, count 0 2006.257.12:22:48.01#ibcon#read 5, iclass 39, count 0 2006.257.12:22:48.01#ibcon#about to read 6, iclass 39, count 0 2006.257.12:22:48.01#ibcon#read 6, iclass 39, count 0 2006.257.12:22:48.01#ibcon#end of sib2, iclass 39, count 0 2006.257.12:22:48.01#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:22:48.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:22:48.01#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:22:48.01#ibcon#*before write, iclass 39, count 0 2006.257.12:22:48.01#ibcon#enter sib2, iclass 39, count 0 2006.257.12:22:48.01#ibcon#flushed, iclass 39, count 0 2006.257.12:22:48.01#ibcon#about to write, iclass 39, count 0 2006.257.12:22:48.01#ibcon#wrote, iclass 39, count 0 2006.257.12:22:48.01#ibcon#about to read 3, iclass 39, count 0 2006.257.12:22:48.05#ibcon#read 3, iclass 39, count 0 2006.257.12:22:48.05#ibcon#about to read 4, iclass 39, count 0 2006.257.12:22:48.05#ibcon#read 4, iclass 39, count 0 2006.257.12:22:48.05#ibcon#about to read 5, iclass 39, count 0 2006.257.12:22:48.05#ibcon#read 5, iclass 39, count 0 2006.257.12:22:48.05#ibcon#about to read 6, iclass 39, count 0 2006.257.12:22:48.05#ibcon#read 6, iclass 39, count 0 2006.257.12:22:48.05#ibcon#end of sib2, iclass 39, count 0 2006.257.12:22:48.05#ibcon#*after write, iclass 39, count 0 2006.257.12:22:48.05#ibcon#*before return 0, iclass 39, count 0 2006.257.12:22:48.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:48.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:22:48.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:22:48.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:22:48.05$vck44/vb=5,4 2006.257.12:22:48.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.12:22:48.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.12:22:48.05#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:48.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:48.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:48.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:48.11#ibcon#enter wrdev, iclass 3, count 2 2006.257.12:22:48.11#ibcon#first serial, iclass 3, count 2 2006.257.12:22:48.11#ibcon#enter sib2, iclass 3, count 2 2006.257.12:22:48.11#ibcon#flushed, iclass 3, count 2 2006.257.12:22:48.11#ibcon#about to write, iclass 3, count 2 2006.257.12:22:48.11#ibcon#wrote, iclass 3, count 2 2006.257.12:22:48.11#ibcon#about to read 3, iclass 3, count 2 2006.257.12:22:48.13#ibcon#read 3, iclass 3, count 2 2006.257.12:22:48.13#ibcon#about to read 4, iclass 3, count 2 2006.257.12:22:48.13#ibcon#read 4, iclass 3, count 2 2006.257.12:22:48.13#ibcon#about to read 5, iclass 3, count 2 2006.257.12:22:48.13#ibcon#read 5, iclass 3, count 2 2006.257.12:22:48.13#ibcon#about to read 6, iclass 3, count 2 2006.257.12:22:48.13#ibcon#read 6, iclass 3, count 2 2006.257.12:22:48.13#ibcon#end of sib2, iclass 3, count 2 2006.257.12:22:48.13#ibcon#*mode == 0, iclass 3, count 2 2006.257.12:22:48.13#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.12:22:48.13#ibcon#[27=AT05-04\r\n] 2006.257.12:22:48.13#ibcon#*before write, iclass 3, count 2 2006.257.12:22:48.13#ibcon#enter sib2, iclass 3, count 2 2006.257.12:22:48.13#ibcon#flushed, iclass 3, count 2 2006.257.12:22:48.13#ibcon#about to write, iclass 3, count 2 2006.257.12:22:48.13#ibcon#wrote, iclass 3, count 2 2006.257.12:22:48.13#ibcon#about to read 3, iclass 3, count 2 2006.257.12:22:48.16#ibcon#read 3, iclass 3, count 2 2006.257.12:22:48.16#ibcon#about to read 4, iclass 3, count 2 2006.257.12:22:48.16#ibcon#read 4, iclass 3, count 2 2006.257.12:22:48.16#ibcon#about to read 5, iclass 3, count 2 2006.257.12:22:48.16#ibcon#read 5, iclass 3, count 2 2006.257.12:22:48.16#ibcon#about to read 6, iclass 3, count 2 2006.257.12:22:48.16#ibcon#read 6, iclass 3, count 2 2006.257.12:22:48.16#ibcon#end of sib2, iclass 3, count 2 2006.257.12:22:48.16#ibcon#*after write, iclass 3, count 2 2006.257.12:22:48.16#ibcon#*before return 0, iclass 3, count 2 2006.257.12:22:48.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:48.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:22:48.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.12:22:48.16#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:48.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:48.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:48.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:48.28#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:22:48.28#ibcon#first serial, iclass 3, count 0 2006.257.12:22:48.28#ibcon#enter sib2, iclass 3, count 0 2006.257.12:22:48.28#ibcon#flushed, iclass 3, count 0 2006.257.12:22:48.28#ibcon#about to write, iclass 3, count 0 2006.257.12:22:48.28#ibcon#wrote, iclass 3, count 0 2006.257.12:22:48.28#ibcon#about to read 3, iclass 3, count 0 2006.257.12:22:48.30#ibcon#read 3, iclass 3, count 0 2006.257.12:22:48.30#ibcon#about to read 4, iclass 3, count 0 2006.257.12:22:48.30#ibcon#read 4, iclass 3, count 0 2006.257.12:22:48.30#ibcon#about to read 5, iclass 3, count 0 2006.257.12:22:48.30#ibcon#read 5, iclass 3, count 0 2006.257.12:22:48.30#ibcon#about to read 6, iclass 3, count 0 2006.257.12:22:48.30#ibcon#read 6, iclass 3, count 0 2006.257.12:22:48.30#ibcon#end of sib2, iclass 3, count 0 2006.257.12:22:48.30#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:22:48.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:22:48.30#ibcon#[27=USB\r\n] 2006.257.12:22:48.30#ibcon#*before write, iclass 3, count 0 2006.257.12:22:48.30#ibcon#enter sib2, iclass 3, count 0 2006.257.12:22:48.30#ibcon#flushed, iclass 3, count 0 2006.257.12:22:48.30#ibcon#about to write, iclass 3, count 0 2006.257.12:22:48.30#ibcon#wrote, iclass 3, count 0 2006.257.12:22:48.30#ibcon#about to read 3, iclass 3, count 0 2006.257.12:22:48.33#ibcon#read 3, iclass 3, count 0 2006.257.12:22:48.33#ibcon#about to read 4, iclass 3, count 0 2006.257.12:22:48.33#ibcon#read 4, iclass 3, count 0 2006.257.12:22:48.33#ibcon#about to read 5, iclass 3, count 0 2006.257.12:22:48.33#ibcon#read 5, iclass 3, count 0 2006.257.12:22:48.33#ibcon#about to read 6, iclass 3, count 0 2006.257.12:22:48.33#ibcon#read 6, iclass 3, count 0 2006.257.12:22:48.33#ibcon#end of sib2, iclass 3, count 0 2006.257.12:22:48.33#ibcon#*after write, iclass 3, count 0 2006.257.12:22:48.33#ibcon#*before return 0, iclass 3, count 0 2006.257.12:22:48.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:48.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:22:48.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:22:48.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:22:48.33$vck44/vblo=6,719.99 2006.257.12:22:48.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.12:22:48.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.12:22:48.33#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:48.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:48.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:48.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:48.33#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:22:48.33#ibcon#first serial, iclass 5, count 0 2006.257.12:22:48.33#ibcon#enter sib2, iclass 5, count 0 2006.257.12:22:48.33#ibcon#flushed, iclass 5, count 0 2006.257.12:22:48.33#ibcon#about to write, iclass 5, count 0 2006.257.12:22:48.33#ibcon#wrote, iclass 5, count 0 2006.257.12:22:48.33#ibcon#about to read 3, iclass 5, count 0 2006.257.12:22:48.35#ibcon#read 3, iclass 5, count 0 2006.257.12:22:48.35#ibcon#about to read 4, iclass 5, count 0 2006.257.12:22:48.35#ibcon#read 4, iclass 5, count 0 2006.257.12:22:48.35#ibcon#about to read 5, iclass 5, count 0 2006.257.12:22:48.35#ibcon#read 5, iclass 5, count 0 2006.257.12:22:48.35#ibcon#about to read 6, iclass 5, count 0 2006.257.12:22:48.35#ibcon#read 6, iclass 5, count 0 2006.257.12:22:48.35#ibcon#end of sib2, iclass 5, count 0 2006.257.12:22:48.35#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:22:48.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:22:48.35#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:22:48.35#ibcon#*before write, iclass 5, count 0 2006.257.12:22:48.35#ibcon#enter sib2, iclass 5, count 0 2006.257.12:22:48.35#ibcon#flushed, iclass 5, count 0 2006.257.12:22:48.35#ibcon#about to write, iclass 5, count 0 2006.257.12:22:48.35#ibcon#wrote, iclass 5, count 0 2006.257.12:22:48.35#ibcon#about to read 3, iclass 5, count 0 2006.257.12:22:48.39#ibcon#read 3, iclass 5, count 0 2006.257.12:22:48.39#ibcon#about to read 4, iclass 5, count 0 2006.257.12:22:48.39#ibcon#read 4, iclass 5, count 0 2006.257.12:22:48.39#ibcon#about to read 5, iclass 5, count 0 2006.257.12:22:48.39#ibcon#read 5, iclass 5, count 0 2006.257.12:22:48.39#ibcon#about to read 6, iclass 5, count 0 2006.257.12:22:48.39#ibcon#read 6, iclass 5, count 0 2006.257.12:22:48.39#ibcon#end of sib2, iclass 5, count 0 2006.257.12:22:48.39#ibcon#*after write, iclass 5, count 0 2006.257.12:22:48.39#ibcon#*before return 0, iclass 5, count 0 2006.257.12:22:48.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:48.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:22:48.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:22:48.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:22:48.39$vck44/vb=6,4 2006.257.12:22:48.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.12:22:48.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.12:22:48.39#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:48.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:48.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:48.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:48.45#ibcon#enter wrdev, iclass 7, count 2 2006.257.12:22:48.45#ibcon#first serial, iclass 7, count 2 2006.257.12:22:48.45#ibcon#enter sib2, iclass 7, count 2 2006.257.12:22:48.45#ibcon#flushed, iclass 7, count 2 2006.257.12:22:48.45#ibcon#about to write, iclass 7, count 2 2006.257.12:22:48.45#ibcon#wrote, iclass 7, count 2 2006.257.12:22:48.45#ibcon#about to read 3, iclass 7, count 2 2006.257.12:22:48.47#ibcon#read 3, iclass 7, count 2 2006.257.12:22:48.47#ibcon#about to read 4, iclass 7, count 2 2006.257.12:22:48.47#ibcon#read 4, iclass 7, count 2 2006.257.12:22:48.47#ibcon#about to read 5, iclass 7, count 2 2006.257.12:22:48.47#ibcon#read 5, iclass 7, count 2 2006.257.12:22:48.47#ibcon#about to read 6, iclass 7, count 2 2006.257.12:22:48.47#ibcon#read 6, iclass 7, count 2 2006.257.12:22:48.47#ibcon#end of sib2, iclass 7, count 2 2006.257.12:22:48.47#ibcon#*mode == 0, iclass 7, count 2 2006.257.12:22:48.47#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.12:22:48.47#ibcon#[27=AT06-04\r\n] 2006.257.12:22:48.47#ibcon#*before write, iclass 7, count 2 2006.257.12:22:48.47#ibcon#enter sib2, iclass 7, count 2 2006.257.12:22:48.47#ibcon#flushed, iclass 7, count 2 2006.257.12:22:48.47#ibcon#about to write, iclass 7, count 2 2006.257.12:22:48.47#ibcon#wrote, iclass 7, count 2 2006.257.12:22:48.47#ibcon#about to read 3, iclass 7, count 2 2006.257.12:22:48.50#ibcon#read 3, iclass 7, count 2 2006.257.12:22:48.50#ibcon#about to read 4, iclass 7, count 2 2006.257.12:22:48.50#ibcon#read 4, iclass 7, count 2 2006.257.12:22:48.50#ibcon#about to read 5, iclass 7, count 2 2006.257.12:22:48.50#ibcon#read 5, iclass 7, count 2 2006.257.12:22:48.50#ibcon#about to read 6, iclass 7, count 2 2006.257.12:22:48.50#ibcon#read 6, iclass 7, count 2 2006.257.12:22:48.50#ibcon#end of sib2, iclass 7, count 2 2006.257.12:22:48.50#ibcon#*after write, iclass 7, count 2 2006.257.12:22:48.50#ibcon#*before return 0, iclass 7, count 2 2006.257.12:22:48.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:48.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:22:48.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.12:22:48.50#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:48.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:48.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:48.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:48.62#ibcon#enter wrdev, iclass 7, count 0 2006.257.12:22:48.62#ibcon#first serial, iclass 7, count 0 2006.257.12:22:48.62#ibcon#enter sib2, iclass 7, count 0 2006.257.12:22:48.62#ibcon#flushed, iclass 7, count 0 2006.257.12:22:48.62#ibcon#about to write, iclass 7, count 0 2006.257.12:22:48.62#ibcon#wrote, iclass 7, count 0 2006.257.12:22:48.62#ibcon#about to read 3, iclass 7, count 0 2006.257.12:22:48.64#ibcon#read 3, iclass 7, count 0 2006.257.12:22:48.64#ibcon#about to read 4, iclass 7, count 0 2006.257.12:22:48.64#ibcon#read 4, iclass 7, count 0 2006.257.12:22:48.64#ibcon#about to read 5, iclass 7, count 0 2006.257.12:22:48.64#ibcon#read 5, iclass 7, count 0 2006.257.12:22:48.64#ibcon#about to read 6, iclass 7, count 0 2006.257.12:22:48.64#ibcon#read 6, iclass 7, count 0 2006.257.12:22:48.64#ibcon#end of sib2, iclass 7, count 0 2006.257.12:22:48.64#ibcon#*mode == 0, iclass 7, count 0 2006.257.12:22:48.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.12:22:48.64#ibcon#[27=USB\r\n] 2006.257.12:22:48.64#ibcon#*before write, iclass 7, count 0 2006.257.12:22:48.64#ibcon#enter sib2, iclass 7, count 0 2006.257.12:22:48.64#ibcon#flushed, iclass 7, count 0 2006.257.12:22:48.64#ibcon#about to write, iclass 7, count 0 2006.257.12:22:48.64#ibcon#wrote, iclass 7, count 0 2006.257.12:22:48.64#ibcon#about to read 3, iclass 7, count 0 2006.257.12:22:48.67#ibcon#read 3, iclass 7, count 0 2006.257.12:22:48.67#ibcon#about to read 4, iclass 7, count 0 2006.257.12:22:48.67#ibcon#read 4, iclass 7, count 0 2006.257.12:22:48.67#ibcon#about to read 5, iclass 7, count 0 2006.257.12:22:48.67#ibcon#read 5, iclass 7, count 0 2006.257.12:22:48.67#ibcon#about to read 6, iclass 7, count 0 2006.257.12:22:48.67#ibcon#read 6, iclass 7, count 0 2006.257.12:22:48.67#ibcon#end of sib2, iclass 7, count 0 2006.257.12:22:48.67#ibcon#*after write, iclass 7, count 0 2006.257.12:22:48.67#ibcon#*before return 0, iclass 7, count 0 2006.257.12:22:48.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:48.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:22:48.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.12:22:48.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.12:22:48.67$vck44/vblo=7,734.99 2006.257.12:22:48.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.12:22:48.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.12:22:48.67#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:48.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:48.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:48.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:48.67#ibcon#enter wrdev, iclass 11, count 0 2006.257.12:22:48.67#ibcon#first serial, iclass 11, count 0 2006.257.12:22:48.67#ibcon#enter sib2, iclass 11, count 0 2006.257.12:22:48.67#ibcon#flushed, iclass 11, count 0 2006.257.12:22:48.67#ibcon#about to write, iclass 11, count 0 2006.257.12:22:48.67#ibcon#wrote, iclass 11, count 0 2006.257.12:22:48.67#ibcon#about to read 3, iclass 11, count 0 2006.257.12:22:48.69#ibcon#read 3, iclass 11, count 0 2006.257.12:22:48.69#ibcon#about to read 4, iclass 11, count 0 2006.257.12:22:48.69#ibcon#read 4, iclass 11, count 0 2006.257.12:22:48.69#ibcon#about to read 5, iclass 11, count 0 2006.257.12:22:48.69#ibcon#read 5, iclass 11, count 0 2006.257.12:22:48.69#ibcon#about to read 6, iclass 11, count 0 2006.257.12:22:48.69#ibcon#read 6, iclass 11, count 0 2006.257.12:22:48.69#ibcon#end of sib2, iclass 11, count 0 2006.257.12:22:48.69#ibcon#*mode == 0, iclass 11, count 0 2006.257.12:22:48.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.12:22:48.69#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:22:48.69#ibcon#*before write, iclass 11, count 0 2006.257.12:22:48.69#ibcon#enter sib2, iclass 11, count 0 2006.257.12:22:48.69#ibcon#flushed, iclass 11, count 0 2006.257.12:22:48.69#ibcon#about to write, iclass 11, count 0 2006.257.12:22:48.69#ibcon#wrote, iclass 11, count 0 2006.257.12:22:48.69#ibcon#about to read 3, iclass 11, count 0 2006.257.12:22:48.73#ibcon#read 3, iclass 11, count 0 2006.257.12:22:48.73#ibcon#about to read 4, iclass 11, count 0 2006.257.12:22:48.73#ibcon#read 4, iclass 11, count 0 2006.257.12:22:48.73#ibcon#about to read 5, iclass 11, count 0 2006.257.12:22:48.73#ibcon#read 5, iclass 11, count 0 2006.257.12:22:48.73#ibcon#about to read 6, iclass 11, count 0 2006.257.12:22:48.73#ibcon#read 6, iclass 11, count 0 2006.257.12:22:48.73#ibcon#end of sib2, iclass 11, count 0 2006.257.12:22:48.73#ibcon#*after write, iclass 11, count 0 2006.257.12:22:48.73#ibcon#*before return 0, iclass 11, count 0 2006.257.12:22:48.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:48.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:22:48.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.12:22:48.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.12:22:48.73$vck44/vb=7,4 2006.257.12:22:48.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.12:22:48.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.12:22:48.73#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:48.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:48.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:48.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:48.79#ibcon#enter wrdev, iclass 13, count 2 2006.257.12:22:48.79#ibcon#first serial, iclass 13, count 2 2006.257.12:22:48.79#ibcon#enter sib2, iclass 13, count 2 2006.257.12:22:48.79#ibcon#flushed, iclass 13, count 2 2006.257.12:22:48.79#ibcon#about to write, iclass 13, count 2 2006.257.12:22:48.79#ibcon#wrote, iclass 13, count 2 2006.257.12:22:48.79#ibcon#about to read 3, iclass 13, count 2 2006.257.12:22:48.81#ibcon#read 3, iclass 13, count 2 2006.257.12:22:48.81#ibcon#about to read 4, iclass 13, count 2 2006.257.12:22:48.81#ibcon#read 4, iclass 13, count 2 2006.257.12:22:48.81#ibcon#about to read 5, iclass 13, count 2 2006.257.12:22:48.81#ibcon#read 5, iclass 13, count 2 2006.257.12:22:48.81#ibcon#about to read 6, iclass 13, count 2 2006.257.12:22:48.81#ibcon#read 6, iclass 13, count 2 2006.257.12:22:48.81#ibcon#end of sib2, iclass 13, count 2 2006.257.12:22:48.81#ibcon#*mode == 0, iclass 13, count 2 2006.257.12:22:48.81#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.12:22:48.81#ibcon#[27=AT07-04\r\n] 2006.257.12:22:48.81#ibcon#*before write, iclass 13, count 2 2006.257.12:22:48.81#ibcon#enter sib2, iclass 13, count 2 2006.257.12:22:48.81#ibcon#flushed, iclass 13, count 2 2006.257.12:22:48.81#ibcon#about to write, iclass 13, count 2 2006.257.12:22:48.81#ibcon#wrote, iclass 13, count 2 2006.257.12:22:48.81#ibcon#about to read 3, iclass 13, count 2 2006.257.12:22:48.84#ibcon#read 3, iclass 13, count 2 2006.257.12:22:48.84#ibcon#about to read 4, iclass 13, count 2 2006.257.12:22:48.84#ibcon#read 4, iclass 13, count 2 2006.257.12:22:48.84#ibcon#about to read 5, iclass 13, count 2 2006.257.12:22:48.84#ibcon#read 5, iclass 13, count 2 2006.257.12:22:48.84#ibcon#about to read 6, iclass 13, count 2 2006.257.12:22:48.84#ibcon#read 6, iclass 13, count 2 2006.257.12:22:48.84#ibcon#end of sib2, iclass 13, count 2 2006.257.12:22:48.84#ibcon#*after write, iclass 13, count 2 2006.257.12:22:48.84#ibcon#*before return 0, iclass 13, count 2 2006.257.12:22:48.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:48.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:22:48.84#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.12:22:48.84#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:48.84#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:48.96#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:48.96#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:48.96#ibcon#enter wrdev, iclass 13, count 0 2006.257.12:22:48.96#ibcon#first serial, iclass 13, count 0 2006.257.12:22:48.96#ibcon#enter sib2, iclass 13, count 0 2006.257.12:22:48.96#ibcon#flushed, iclass 13, count 0 2006.257.12:22:48.96#ibcon#about to write, iclass 13, count 0 2006.257.12:22:48.96#ibcon#wrote, iclass 13, count 0 2006.257.12:22:48.96#ibcon#about to read 3, iclass 13, count 0 2006.257.12:22:48.98#ibcon#read 3, iclass 13, count 0 2006.257.12:22:48.98#ibcon#about to read 4, iclass 13, count 0 2006.257.12:22:48.98#ibcon#read 4, iclass 13, count 0 2006.257.12:22:48.98#ibcon#about to read 5, iclass 13, count 0 2006.257.12:22:48.98#ibcon#read 5, iclass 13, count 0 2006.257.12:22:48.98#ibcon#about to read 6, iclass 13, count 0 2006.257.12:22:48.98#ibcon#read 6, iclass 13, count 0 2006.257.12:22:48.98#ibcon#end of sib2, iclass 13, count 0 2006.257.12:22:48.98#ibcon#*mode == 0, iclass 13, count 0 2006.257.12:22:48.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.12:22:48.98#ibcon#[27=USB\r\n] 2006.257.12:22:48.98#ibcon#*before write, iclass 13, count 0 2006.257.12:22:48.98#ibcon#enter sib2, iclass 13, count 0 2006.257.12:22:48.98#ibcon#flushed, iclass 13, count 0 2006.257.12:22:48.98#ibcon#about to write, iclass 13, count 0 2006.257.12:22:48.98#ibcon#wrote, iclass 13, count 0 2006.257.12:22:48.98#ibcon#about to read 3, iclass 13, count 0 2006.257.12:22:49.01#ibcon#read 3, iclass 13, count 0 2006.257.12:22:49.01#ibcon#about to read 4, iclass 13, count 0 2006.257.12:22:49.01#ibcon#read 4, iclass 13, count 0 2006.257.12:22:49.01#ibcon#about to read 5, iclass 13, count 0 2006.257.12:22:49.01#ibcon#read 5, iclass 13, count 0 2006.257.12:22:49.01#ibcon#about to read 6, iclass 13, count 0 2006.257.12:22:49.01#ibcon#read 6, iclass 13, count 0 2006.257.12:22:49.01#ibcon#end of sib2, iclass 13, count 0 2006.257.12:22:49.01#ibcon#*after write, iclass 13, count 0 2006.257.12:22:49.01#ibcon#*before return 0, iclass 13, count 0 2006.257.12:22:49.01#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:49.01#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:22:49.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.12:22:49.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.12:22:49.01$vck44/vblo=8,744.99 2006.257.12:22:49.01#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.12:22:49.01#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.12:22:49.01#ibcon#ireg 17 cls_cnt 0 2006.257.12:22:49.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:49.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:49.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:49.01#ibcon#enter wrdev, iclass 15, count 0 2006.257.12:22:49.01#ibcon#first serial, iclass 15, count 0 2006.257.12:22:49.01#ibcon#enter sib2, iclass 15, count 0 2006.257.12:22:49.01#ibcon#flushed, iclass 15, count 0 2006.257.12:22:49.01#ibcon#about to write, iclass 15, count 0 2006.257.12:22:49.01#ibcon#wrote, iclass 15, count 0 2006.257.12:22:49.01#ibcon#about to read 3, iclass 15, count 0 2006.257.12:22:49.03#ibcon#read 3, iclass 15, count 0 2006.257.12:22:49.03#ibcon#about to read 4, iclass 15, count 0 2006.257.12:22:49.03#ibcon#read 4, iclass 15, count 0 2006.257.12:22:49.03#ibcon#about to read 5, iclass 15, count 0 2006.257.12:22:49.03#ibcon#read 5, iclass 15, count 0 2006.257.12:22:49.03#ibcon#about to read 6, iclass 15, count 0 2006.257.12:22:49.03#ibcon#read 6, iclass 15, count 0 2006.257.12:22:49.03#ibcon#end of sib2, iclass 15, count 0 2006.257.12:22:49.03#ibcon#*mode == 0, iclass 15, count 0 2006.257.12:22:49.03#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.12:22:49.03#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:22:49.03#ibcon#*before write, iclass 15, count 0 2006.257.12:22:49.03#ibcon#enter sib2, iclass 15, count 0 2006.257.12:22:49.03#ibcon#flushed, iclass 15, count 0 2006.257.12:22:49.03#ibcon#about to write, iclass 15, count 0 2006.257.12:22:49.03#ibcon#wrote, iclass 15, count 0 2006.257.12:22:49.03#ibcon#about to read 3, iclass 15, count 0 2006.257.12:22:49.07#ibcon#read 3, iclass 15, count 0 2006.257.12:22:49.07#ibcon#about to read 4, iclass 15, count 0 2006.257.12:22:49.07#ibcon#read 4, iclass 15, count 0 2006.257.12:22:49.07#ibcon#about to read 5, iclass 15, count 0 2006.257.12:22:49.07#ibcon#read 5, iclass 15, count 0 2006.257.12:22:49.07#ibcon#about to read 6, iclass 15, count 0 2006.257.12:22:49.07#ibcon#read 6, iclass 15, count 0 2006.257.12:22:49.07#ibcon#end of sib2, iclass 15, count 0 2006.257.12:22:49.07#ibcon#*after write, iclass 15, count 0 2006.257.12:22:49.07#ibcon#*before return 0, iclass 15, count 0 2006.257.12:22:49.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:49.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:22:49.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.12:22:49.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.12:22:49.07$vck44/vb=8,4 2006.257.12:22:49.07#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.12:22:49.07#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.12:22:49.07#ibcon#ireg 11 cls_cnt 2 2006.257.12:22:49.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:49.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:49.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:49.13#ibcon#enter wrdev, iclass 17, count 2 2006.257.12:22:49.13#ibcon#first serial, iclass 17, count 2 2006.257.12:22:49.13#ibcon#enter sib2, iclass 17, count 2 2006.257.12:22:49.13#ibcon#flushed, iclass 17, count 2 2006.257.12:22:49.13#ibcon#about to write, iclass 17, count 2 2006.257.12:22:49.13#ibcon#wrote, iclass 17, count 2 2006.257.12:22:49.13#ibcon#about to read 3, iclass 17, count 2 2006.257.12:22:49.15#ibcon#read 3, iclass 17, count 2 2006.257.12:22:49.15#ibcon#about to read 4, iclass 17, count 2 2006.257.12:22:49.15#ibcon#read 4, iclass 17, count 2 2006.257.12:22:49.15#ibcon#about to read 5, iclass 17, count 2 2006.257.12:22:49.15#ibcon#read 5, iclass 17, count 2 2006.257.12:22:49.15#ibcon#about to read 6, iclass 17, count 2 2006.257.12:22:49.15#ibcon#read 6, iclass 17, count 2 2006.257.12:22:49.15#ibcon#end of sib2, iclass 17, count 2 2006.257.12:22:49.15#ibcon#*mode == 0, iclass 17, count 2 2006.257.12:22:49.15#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.12:22:49.15#ibcon#[27=AT08-04\r\n] 2006.257.12:22:49.15#ibcon#*before write, iclass 17, count 2 2006.257.12:22:49.15#ibcon#enter sib2, iclass 17, count 2 2006.257.12:22:49.15#ibcon#flushed, iclass 17, count 2 2006.257.12:22:49.15#ibcon#about to write, iclass 17, count 2 2006.257.12:22:49.15#ibcon#wrote, iclass 17, count 2 2006.257.12:22:49.15#ibcon#about to read 3, iclass 17, count 2 2006.257.12:22:49.18#ibcon#read 3, iclass 17, count 2 2006.257.12:22:49.18#ibcon#about to read 4, iclass 17, count 2 2006.257.12:22:49.18#ibcon#read 4, iclass 17, count 2 2006.257.12:22:49.18#ibcon#about to read 5, iclass 17, count 2 2006.257.12:22:49.18#ibcon#read 5, iclass 17, count 2 2006.257.12:22:49.18#ibcon#about to read 6, iclass 17, count 2 2006.257.12:22:49.18#ibcon#read 6, iclass 17, count 2 2006.257.12:22:49.18#ibcon#end of sib2, iclass 17, count 2 2006.257.12:22:49.18#ibcon#*after write, iclass 17, count 2 2006.257.12:22:49.18#ibcon#*before return 0, iclass 17, count 2 2006.257.12:22:49.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:49.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:22:49.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.12:22:49.18#ibcon#ireg 7 cls_cnt 0 2006.257.12:22:49.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:49.30#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:49.30#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:49.30#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:22:49.30#ibcon#first serial, iclass 17, count 0 2006.257.12:22:49.30#ibcon#enter sib2, iclass 17, count 0 2006.257.12:22:49.30#ibcon#flushed, iclass 17, count 0 2006.257.12:22:49.30#ibcon#about to write, iclass 17, count 0 2006.257.12:22:49.30#ibcon#wrote, iclass 17, count 0 2006.257.12:22:49.30#ibcon#about to read 3, iclass 17, count 0 2006.257.12:22:49.32#ibcon#read 3, iclass 17, count 0 2006.257.12:22:49.32#ibcon#about to read 4, iclass 17, count 0 2006.257.12:22:49.32#ibcon#read 4, iclass 17, count 0 2006.257.12:22:49.32#ibcon#about to read 5, iclass 17, count 0 2006.257.12:22:49.32#ibcon#read 5, iclass 17, count 0 2006.257.12:22:49.32#ibcon#about to read 6, iclass 17, count 0 2006.257.12:22:49.32#ibcon#read 6, iclass 17, count 0 2006.257.12:22:49.32#ibcon#end of sib2, iclass 17, count 0 2006.257.12:22:49.32#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:22:49.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:22:49.32#ibcon#[27=USB\r\n] 2006.257.12:22:49.32#ibcon#*before write, iclass 17, count 0 2006.257.12:22:49.32#ibcon#enter sib2, iclass 17, count 0 2006.257.12:22:49.32#ibcon#flushed, iclass 17, count 0 2006.257.12:22:49.32#ibcon#about to write, iclass 17, count 0 2006.257.12:22:49.32#ibcon#wrote, iclass 17, count 0 2006.257.12:22:49.32#ibcon#about to read 3, iclass 17, count 0 2006.257.12:22:49.35#ibcon#read 3, iclass 17, count 0 2006.257.12:22:49.35#ibcon#about to read 4, iclass 17, count 0 2006.257.12:22:49.35#ibcon#read 4, iclass 17, count 0 2006.257.12:22:49.35#ibcon#about to read 5, iclass 17, count 0 2006.257.12:22:49.35#ibcon#read 5, iclass 17, count 0 2006.257.12:22:49.35#ibcon#about to read 6, iclass 17, count 0 2006.257.12:22:49.35#ibcon#read 6, iclass 17, count 0 2006.257.12:22:49.35#ibcon#end of sib2, iclass 17, count 0 2006.257.12:22:49.35#ibcon#*after write, iclass 17, count 0 2006.257.12:22:49.35#ibcon#*before return 0, iclass 17, count 0 2006.257.12:22:49.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:49.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:22:49.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:22:49.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:22:49.35$vck44/vabw=wide 2006.257.12:22:49.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.12:22:49.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.12:22:49.35#ibcon#ireg 8 cls_cnt 0 2006.257.12:22:49.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:49.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:49.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:49.35#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:22:49.35#ibcon#first serial, iclass 19, count 0 2006.257.12:22:49.35#ibcon#enter sib2, iclass 19, count 0 2006.257.12:22:49.35#ibcon#flushed, iclass 19, count 0 2006.257.12:22:49.35#ibcon#about to write, iclass 19, count 0 2006.257.12:22:49.35#ibcon#wrote, iclass 19, count 0 2006.257.12:22:49.35#ibcon#about to read 3, iclass 19, count 0 2006.257.12:22:49.37#ibcon#read 3, iclass 19, count 0 2006.257.12:22:49.37#ibcon#about to read 4, iclass 19, count 0 2006.257.12:22:49.37#ibcon#read 4, iclass 19, count 0 2006.257.12:22:49.37#ibcon#about to read 5, iclass 19, count 0 2006.257.12:22:49.37#ibcon#read 5, iclass 19, count 0 2006.257.12:22:49.37#ibcon#about to read 6, iclass 19, count 0 2006.257.12:22:49.37#ibcon#read 6, iclass 19, count 0 2006.257.12:22:49.37#ibcon#end of sib2, iclass 19, count 0 2006.257.12:22:49.37#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:22:49.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:22:49.37#ibcon#[25=BW32\r\n] 2006.257.12:22:49.37#ibcon#*before write, iclass 19, count 0 2006.257.12:22:49.37#ibcon#enter sib2, iclass 19, count 0 2006.257.12:22:49.37#ibcon#flushed, iclass 19, count 0 2006.257.12:22:49.37#ibcon#about to write, iclass 19, count 0 2006.257.12:22:49.37#ibcon#wrote, iclass 19, count 0 2006.257.12:22:49.37#ibcon#about to read 3, iclass 19, count 0 2006.257.12:22:49.40#ibcon#read 3, iclass 19, count 0 2006.257.12:22:49.40#ibcon#about to read 4, iclass 19, count 0 2006.257.12:22:49.40#ibcon#read 4, iclass 19, count 0 2006.257.12:22:49.40#ibcon#about to read 5, iclass 19, count 0 2006.257.12:22:49.40#ibcon#read 5, iclass 19, count 0 2006.257.12:22:49.40#ibcon#about to read 6, iclass 19, count 0 2006.257.12:22:49.40#ibcon#read 6, iclass 19, count 0 2006.257.12:22:49.40#ibcon#end of sib2, iclass 19, count 0 2006.257.12:22:49.40#ibcon#*after write, iclass 19, count 0 2006.257.12:22:49.40#ibcon#*before return 0, iclass 19, count 0 2006.257.12:22:49.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:49.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:22:49.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:22:49.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:22:49.40$vck44/vbbw=wide 2006.257.12:22:49.40#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.12:22:49.40#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.12:22:49.40#ibcon#ireg 8 cls_cnt 0 2006.257.12:22:49.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:22:49.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:22:49.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:22:49.47#ibcon#enter wrdev, iclass 21, count 0 2006.257.12:22:49.47#ibcon#first serial, iclass 21, count 0 2006.257.12:22:49.47#ibcon#enter sib2, iclass 21, count 0 2006.257.12:22:49.47#ibcon#flushed, iclass 21, count 0 2006.257.12:22:49.47#ibcon#about to write, iclass 21, count 0 2006.257.12:22:49.47#ibcon#wrote, iclass 21, count 0 2006.257.12:22:49.47#ibcon#about to read 3, iclass 21, count 0 2006.257.12:22:49.49#ibcon#read 3, iclass 21, count 0 2006.257.12:22:49.49#ibcon#about to read 4, iclass 21, count 0 2006.257.12:22:49.49#ibcon#read 4, iclass 21, count 0 2006.257.12:22:49.49#ibcon#about to read 5, iclass 21, count 0 2006.257.12:22:49.49#ibcon#read 5, iclass 21, count 0 2006.257.12:22:49.49#ibcon#about to read 6, iclass 21, count 0 2006.257.12:22:49.49#ibcon#read 6, iclass 21, count 0 2006.257.12:22:49.49#ibcon#end of sib2, iclass 21, count 0 2006.257.12:22:49.49#ibcon#*mode == 0, iclass 21, count 0 2006.257.12:22:49.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.12:22:49.49#ibcon#[27=BW32\r\n] 2006.257.12:22:49.49#ibcon#*before write, iclass 21, count 0 2006.257.12:22:49.49#ibcon#enter sib2, iclass 21, count 0 2006.257.12:22:49.49#ibcon#flushed, iclass 21, count 0 2006.257.12:22:49.49#ibcon#about to write, iclass 21, count 0 2006.257.12:22:49.49#ibcon#wrote, iclass 21, count 0 2006.257.12:22:49.49#ibcon#about to read 3, iclass 21, count 0 2006.257.12:22:49.52#ibcon#read 3, iclass 21, count 0 2006.257.12:22:49.52#ibcon#about to read 4, iclass 21, count 0 2006.257.12:22:49.52#ibcon#read 4, iclass 21, count 0 2006.257.12:22:49.52#ibcon#about to read 5, iclass 21, count 0 2006.257.12:22:49.52#ibcon#read 5, iclass 21, count 0 2006.257.12:22:49.52#ibcon#about to read 6, iclass 21, count 0 2006.257.12:22:49.52#ibcon#read 6, iclass 21, count 0 2006.257.12:22:49.52#ibcon#end of sib2, iclass 21, count 0 2006.257.12:22:49.52#ibcon#*after write, iclass 21, count 0 2006.257.12:22:49.52#ibcon#*before return 0, iclass 21, count 0 2006.257.12:22:49.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:22:49.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:22:49.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.12:22:49.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.12:22:49.52$setupk4/ifdk4 2006.257.12:22:49.52$ifdk4/lo= 2006.257.12:22:49.52$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:22:49.52$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:22:49.52$ifdk4/patch= 2006.257.12:22:49.52$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:22:49.52$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:22:49.52$setupk4/!*+20s 2006.257.12:22:54.80#abcon#<5=/14 1.5 4.2 18.09 951013.9\r\n> 2006.257.12:22:54.82#abcon#{5=INTERFACE CLEAR} 2006.257.12:22:54.88#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:23:04.03$setupk4/"tpicd 2006.257.12:23:04.03$setupk4/echo=off 2006.257.12:23:04.03$setupk4/xlog=off 2006.257.12:23:04.03:!2006.257.12:27:04 2006.257.12:23:26.14#trakl#Source acquired 2006.257.12:23:27.14#flagr#flagr/antenna,acquired 2006.257.12:27:04.00:preob 2006.257.12:27:04.14/onsource/TRACKING 2006.257.12:27:04.14:!2006.257.12:27:14 2006.257.12:27:14.00:"tape 2006.257.12:27:14.00:"st=record 2006.257.12:27:14.00:data_valid=on 2006.257.12:27:14.00:midob 2006.257.12:27:15.14/onsource/TRACKING 2006.257.12:27:15.14/wx/18.04,1013.8,95 2006.257.12:27:15.27/cable/+6.4780E-03 2006.257.12:27:16.36/va/01,08,usb,yes,30,32 2006.257.12:27:16.36/va/02,07,usb,yes,33,33 2006.257.12:27:16.36/va/03,08,usb,yes,29,31 2006.257.12:27:16.36/va/04,07,usb,yes,34,35 2006.257.12:27:16.36/va/05,04,usb,yes,30,30 2006.257.12:27:16.36/va/06,04,usb,yes,33,33 2006.257.12:27:16.36/va/07,04,usb,yes,34,35 2006.257.12:27:16.36/va/08,04,usb,yes,29,35 2006.257.12:27:16.59/valo/01,524.99,yes,locked 2006.257.12:27:16.59/valo/02,534.99,yes,locked 2006.257.12:27:16.59/valo/03,564.99,yes,locked 2006.257.12:27:16.59/valo/04,624.99,yes,locked 2006.257.12:27:16.59/valo/05,734.99,yes,locked 2006.257.12:27:16.59/valo/06,814.99,yes,locked 2006.257.12:27:16.59/valo/07,864.99,yes,locked 2006.257.12:27:16.59/valo/08,884.99,yes,locked 2006.257.12:27:17.68/vb/01,04,usb,yes,30,28 2006.257.12:27:17.68/vb/02,05,usb,yes,29,28 2006.257.12:27:17.68/vb/03,04,usb,yes,29,32 2006.257.12:27:17.68/vb/04,05,usb,yes,30,29 2006.257.12:27:17.68/vb/05,04,usb,yes,26,28 2006.257.12:27:17.68/vb/06,04,usb,yes,31,27 2006.257.12:27:17.68/vb/07,04,usb,yes,30,30 2006.257.12:27:17.68/vb/08,04,usb,yes,28,31 2006.257.12:27:17.91/vblo/01,629.99,yes,locked 2006.257.12:27:17.91/vblo/02,634.99,yes,locked 2006.257.12:27:17.91/vblo/03,649.99,yes,locked 2006.257.12:27:17.91/vblo/04,679.99,yes,locked 2006.257.12:27:17.91/vblo/05,709.99,yes,locked 2006.257.12:27:17.91/vblo/06,719.99,yes,locked 2006.257.12:27:17.91/vblo/07,734.99,yes,locked 2006.257.12:27:17.91/vblo/08,744.99,yes,locked 2006.257.12:27:18.06/vabw/8 2006.257.12:27:18.21/vbbw/8 2006.257.12:27:18.30/xfe/off,on,16.0 2006.257.12:27:18.68/ifatt/23,28,28,28 2006.257.12:27:19.08/fmout-gps/S +4.59E-07 2006.257.12:27:19.12:!2006.257.12:29:04 2006.257.12:29:04.00:data_valid=off 2006.257.12:29:04.00:"et 2006.257.12:29:04.00:!+3s 2006.257.12:29:07.02:"tape 2006.257.12:29:07.02:postob 2006.257.12:29:07.21/cable/+6.4793E-03 2006.257.12:29:07.21/wx/18.02,1013.7,96 2006.257.12:29:07.27/fmout-gps/S +4.58E-07 2006.257.12:29:07.27:scan_name=257-1232,jd0609,70 2006.257.12:29:07.28:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.12:29:08.14#flagr#flagr/antenna,new-source 2006.257.12:29:08.14:checkk5 2006.257.12:29:08.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:29:08.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:29:09.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:29:09.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:29:10.16/chk_obsdata//k5ts1/T2571227??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.12:29:10.55/chk_obsdata//k5ts2/T2571227??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.12:29:10.92/chk_obsdata//k5ts3/T2571227??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.12:29:11.31/chk_obsdata//k5ts4/T2571227??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.12:29:12.03/k5log//k5ts1_log_newline 2006.257.12:29:12.72/k5log//k5ts2_log_newline 2006.257.12:29:13.42/k5log//k5ts3_log_newline 2006.257.12:29:14.12/k5log//k5ts4_log_newline 2006.257.12:29:14.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:29:14.15:setupk4=1 2006.257.12:29:14.15$setupk4/echo=on 2006.257.12:29:14.15$setupk4/pcalon 2006.257.12:29:14.15$pcalon/"no phase cal control is implemented here 2006.257.12:29:14.15$setupk4/"tpicd=stop 2006.257.12:29:14.15$setupk4/"rec=synch_on 2006.257.12:29:14.15$setupk4/"rec_mode=128 2006.257.12:29:14.15$setupk4/!* 2006.257.12:29:14.15$setupk4/recpk4 2006.257.12:29:14.15$recpk4/recpatch= 2006.257.12:29:14.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:29:14.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:29:14.16$setupk4/vck44 2006.257.12:29:14.16$vck44/valo=1,524.99 2006.257.12:29:14.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.12:29:14.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.12:29:14.16#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:14.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:14.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:14.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:14.16#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:29:14.16#ibcon#first serial, iclass 34, count 0 2006.257.12:29:14.16#ibcon#enter sib2, iclass 34, count 0 2006.257.12:29:14.16#ibcon#flushed, iclass 34, count 0 2006.257.12:29:14.16#ibcon#about to write, iclass 34, count 0 2006.257.12:29:14.16#ibcon#wrote, iclass 34, count 0 2006.257.12:29:14.16#ibcon#about to read 3, iclass 34, count 0 2006.257.12:29:14.17#ibcon#read 3, iclass 34, count 0 2006.257.12:29:14.17#ibcon#about to read 4, iclass 34, count 0 2006.257.12:29:14.17#ibcon#read 4, iclass 34, count 0 2006.257.12:29:14.17#ibcon#about to read 5, iclass 34, count 0 2006.257.12:29:14.17#ibcon#read 5, iclass 34, count 0 2006.257.12:29:14.17#ibcon#about to read 6, iclass 34, count 0 2006.257.12:29:14.17#ibcon#read 6, iclass 34, count 0 2006.257.12:29:14.17#ibcon#end of sib2, iclass 34, count 0 2006.257.12:29:14.17#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:29:14.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:29:14.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:29:14.17#ibcon#*before write, iclass 34, count 0 2006.257.12:29:14.17#ibcon#enter sib2, iclass 34, count 0 2006.257.12:29:14.17#ibcon#flushed, iclass 34, count 0 2006.257.12:29:14.17#ibcon#about to write, iclass 34, count 0 2006.257.12:29:14.17#ibcon#wrote, iclass 34, count 0 2006.257.12:29:14.17#ibcon#about to read 3, iclass 34, count 0 2006.257.12:29:14.22#ibcon#read 3, iclass 34, count 0 2006.257.12:29:14.22#ibcon#about to read 4, iclass 34, count 0 2006.257.12:29:14.22#ibcon#read 4, iclass 34, count 0 2006.257.12:29:14.22#ibcon#about to read 5, iclass 34, count 0 2006.257.12:29:14.22#ibcon#read 5, iclass 34, count 0 2006.257.12:29:14.22#ibcon#about to read 6, iclass 34, count 0 2006.257.12:29:14.22#ibcon#read 6, iclass 34, count 0 2006.257.12:29:14.22#ibcon#end of sib2, iclass 34, count 0 2006.257.12:29:14.22#ibcon#*after write, iclass 34, count 0 2006.257.12:29:14.22#ibcon#*before return 0, iclass 34, count 0 2006.257.12:29:14.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:14.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:14.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:29:14.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:29:14.22$vck44/va=1,8 2006.257.12:29:14.22#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.12:29:14.22#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.12:29:14.22#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:14.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:14.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:14.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:14.22#ibcon#enter wrdev, iclass 36, count 2 2006.257.12:29:14.22#ibcon#first serial, iclass 36, count 2 2006.257.12:29:14.22#ibcon#enter sib2, iclass 36, count 2 2006.257.12:29:14.22#ibcon#flushed, iclass 36, count 2 2006.257.12:29:14.22#ibcon#about to write, iclass 36, count 2 2006.257.12:29:14.22#ibcon#wrote, iclass 36, count 2 2006.257.12:29:14.22#ibcon#about to read 3, iclass 36, count 2 2006.257.12:29:14.24#ibcon#read 3, iclass 36, count 2 2006.257.12:29:14.24#ibcon#about to read 4, iclass 36, count 2 2006.257.12:29:14.24#ibcon#read 4, iclass 36, count 2 2006.257.12:29:14.24#ibcon#about to read 5, iclass 36, count 2 2006.257.12:29:14.24#ibcon#read 5, iclass 36, count 2 2006.257.12:29:14.24#ibcon#about to read 6, iclass 36, count 2 2006.257.12:29:14.24#ibcon#read 6, iclass 36, count 2 2006.257.12:29:14.24#ibcon#end of sib2, iclass 36, count 2 2006.257.12:29:14.24#ibcon#*mode == 0, iclass 36, count 2 2006.257.12:29:14.24#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.12:29:14.24#ibcon#[25=AT01-08\r\n] 2006.257.12:29:14.24#ibcon#*before write, iclass 36, count 2 2006.257.12:29:14.24#ibcon#enter sib2, iclass 36, count 2 2006.257.12:29:14.24#ibcon#flushed, iclass 36, count 2 2006.257.12:29:14.24#ibcon#about to write, iclass 36, count 2 2006.257.12:29:14.24#ibcon#wrote, iclass 36, count 2 2006.257.12:29:14.24#ibcon#about to read 3, iclass 36, count 2 2006.257.12:29:14.27#ibcon#read 3, iclass 36, count 2 2006.257.12:29:14.27#ibcon#about to read 4, iclass 36, count 2 2006.257.12:29:14.27#ibcon#read 4, iclass 36, count 2 2006.257.12:29:14.27#ibcon#about to read 5, iclass 36, count 2 2006.257.12:29:14.27#ibcon#read 5, iclass 36, count 2 2006.257.12:29:14.27#ibcon#about to read 6, iclass 36, count 2 2006.257.12:29:14.27#ibcon#read 6, iclass 36, count 2 2006.257.12:29:14.27#ibcon#end of sib2, iclass 36, count 2 2006.257.12:29:14.27#ibcon#*after write, iclass 36, count 2 2006.257.12:29:14.27#ibcon#*before return 0, iclass 36, count 2 2006.257.12:29:14.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:14.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:14.27#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.12:29:14.27#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:14.27#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:14.39#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:14.39#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:14.39#ibcon#enter wrdev, iclass 36, count 0 2006.257.12:29:14.39#ibcon#first serial, iclass 36, count 0 2006.257.12:29:14.39#ibcon#enter sib2, iclass 36, count 0 2006.257.12:29:14.39#ibcon#flushed, iclass 36, count 0 2006.257.12:29:14.39#ibcon#about to write, iclass 36, count 0 2006.257.12:29:14.39#ibcon#wrote, iclass 36, count 0 2006.257.12:29:14.39#ibcon#about to read 3, iclass 36, count 0 2006.257.12:29:14.41#ibcon#read 3, iclass 36, count 0 2006.257.12:29:14.41#ibcon#about to read 4, iclass 36, count 0 2006.257.12:29:14.41#ibcon#read 4, iclass 36, count 0 2006.257.12:29:14.41#ibcon#about to read 5, iclass 36, count 0 2006.257.12:29:14.41#ibcon#read 5, iclass 36, count 0 2006.257.12:29:14.41#ibcon#about to read 6, iclass 36, count 0 2006.257.12:29:14.41#ibcon#read 6, iclass 36, count 0 2006.257.12:29:14.41#ibcon#end of sib2, iclass 36, count 0 2006.257.12:29:14.41#ibcon#*mode == 0, iclass 36, count 0 2006.257.12:29:14.41#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.12:29:14.41#ibcon#[25=USB\r\n] 2006.257.12:29:14.41#ibcon#*before write, iclass 36, count 0 2006.257.12:29:14.41#ibcon#enter sib2, iclass 36, count 0 2006.257.12:29:14.41#ibcon#flushed, iclass 36, count 0 2006.257.12:29:14.41#ibcon#about to write, iclass 36, count 0 2006.257.12:29:14.41#ibcon#wrote, iclass 36, count 0 2006.257.12:29:14.41#ibcon#about to read 3, iclass 36, count 0 2006.257.12:29:14.44#ibcon#read 3, iclass 36, count 0 2006.257.12:29:14.44#ibcon#about to read 4, iclass 36, count 0 2006.257.12:29:14.44#ibcon#read 4, iclass 36, count 0 2006.257.12:29:14.44#ibcon#about to read 5, iclass 36, count 0 2006.257.12:29:14.44#ibcon#read 5, iclass 36, count 0 2006.257.12:29:14.44#ibcon#about to read 6, iclass 36, count 0 2006.257.12:29:14.44#ibcon#read 6, iclass 36, count 0 2006.257.12:29:14.44#ibcon#end of sib2, iclass 36, count 0 2006.257.12:29:14.44#ibcon#*after write, iclass 36, count 0 2006.257.12:29:14.44#ibcon#*before return 0, iclass 36, count 0 2006.257.12:29:14.44#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:14.44#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:14.44#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.12:29:14.44#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.12:29:14.44$vck44/valo=2,534.99 2006.257.12:29:14.44#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.12:29:14.44#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.12:29:14.44#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:14.44#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:14.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:14.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:14.44#ibcon#enter wrdev, iclass 38, count 0 2006.257.12:29:14.44#ibcon#first serial, iclass 38, count 0 2006.257.12:29:14.44#ibcon#enter sib2, iclass 38, count 0 2006.257.12:29:14.44#ibcon#flushed, iclass 38, count 0 2006.257.12:29:14.44#ibcon#about to write, iclass 38, count 0 2006.257.12:29:14.44#ibcon#wrote, iclass 38, count 0 2006.257.12:29:14.44#ibcon#about to read 3, iclass 38, count 0 2006.257.12:29:14.46#ibcon#read 3, iclass 38, count 0 2006.257.12:29:14.46#ibcon#about to read 4, iclass 38, count 0 2006.257.12:29:14.46#ibcon#read 4, iclass 38, count 0 2006.257.12:29:14.46#ibcon#about to read 5, iclass 38, count 0 2006.257.12:29:14.46#ibcon#read 5, iclass 38, count 0 2006.257.12:29:14.46#ibcon#about to read 6, iclass 38, count 0 2006.257.12:29:14.46#ibcon#read 6, iclass 38, count 0 2006.257.12:29:14.46#ibcon#end of sib2, iclass 38, count 0 2006.257.12:29:14.46#ibcon#*mode == 0, iclass 38, count 0 2006.257.12:29:14.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.12:29:14.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:29:14.46#ibcon#*before write, iclass 38, count 0 2006.257.12:29:14.46#ibcon#enter sib2, iclass 38, count 0 2006.257.12:29:14.46#ibcon#flushed, iclass 38, count 0 2006.257.12:29:14.46#ibcon#about to write, iclass 38, count 0 2006.257.12:29:14.46#ibcon#wrote, iclass 38, count 0 2006.257.12:29:14.46#ibcon#about to read 3, iclass 38, count 0 2006.257.12:29:14.50#ibcon#read 3, iclass 38, count 0 2006.257.12:29:14.50#ibcon#about to read 4, iclass 38, count 0 2006.257.12:29:14.50#ibcon#read 4, iclass 38, count 0 2006.257.12:29:14.50#ibcon#about to read 5, iclass 38, count 0 2006.257.12:29:14.50#ibcon#read 5, iclass 38, count 0 2006.257.12:29:14.50#ibcon#about to read 6, iclass 38, count 0 2006.257.12:29:14.50#ibcon#read 6, iclass 38, count 0 2006.257.12:29:14.50#ibcon#end of sib2, iclass 38, count 0 2006.257.12:29:14.50#ibcon#*after write, iclass 38, count 0 2006.257.12:29:14.50#ibcon#*before return 0, iclass 38, count 0 2006.257.12:29:14.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:14.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:14.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.12:29:14.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.12:29:14.50$vck44/va=2,7 2006.257.12:29:14.50#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.12:29:14.50#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.12:29:14.50#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:14.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:14.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:14.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:14.56#ibcon#enter wrdev, iclass 40, count 2 2006.257.12:29:14.56#ibcon#first serial, iclass 40, count 2 2006.257.12:29:14.56#ibcon#enter sib2, iclass 40, count 2 2006.257.12:29:14.56#ibcon#flushed, iclass 40, count 2 2006.257.12:29:14.56#ibcon#about to write, iclass 40, count 2 2006.257.12:29:14.56#ibcon#wrote, iclass 40, count 2 2006.257.12:29:14.56#ibcon#about to read 3, iclass 40, count 2 2006.257.12:29:14.58#ibcon#read 3, iclass 40, count 2 2006.257.12:29:14.58#ibcon#about to read 4, iclass 40, count 2 2006.257.12:29:14.58#ibcon#read 4, iclass 40, count 2 2006.257.12:29:14.58#ibcon#about to read 5, iclass 40, count 2 2006.257.12:29:14.58#ibcon#read 5, iclass 40, count 2 2006.257.12:29:14.58#ibcon#about to read 6, iclass 40, count 2 2006.257.12:29:14.58#ibcon#read 6, iclass 40, count 2 2006.257.12:29:14.58#ibcon#end of sib2, iclass 40, count 2 2006.257.12:29:14.58#ibcon#*mode == 0, iclass 40, count 2 2006.257.12:29:14.58#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.12:29:14.58#ibcon#[25=AT02-07\r\n] 2006.257.12:29:14.58#ibcon#*before write, iclass 40, count 2 2006.257.12:29:14.58#ibcon#enter sib2, iclass 40, count 2 2006.257.12:29:14.58#ibcon#flushed, iclass 40, count 2 2006.257.12:29:14.58#ibcon#about to write, iclass 40, count 2 2006.257.12:29:14.58#ibcon#wrote, iclass 40, count 2 2006.257.12:29:14.58#ibcon#about to read 3, iclass 40, count 2 2006.257.12:29:14.61#ibcon#read 3, iclass 40, count 2 2006.257.12:29:14.61#ibcon#about to read 4, iclass 40, count 2 2006.257.12:29:14.61#ibcon#read 4, iclass 40, count 2 2006.257.12:29:14.61#ibcon#about to read 5, iclass 40, count 2 2006.257.12:29:14.61#ibcon#read 5, iclass 40, count 2 2006.257.12:29:14.61#ibcon#about to read 6, iclass 40, count 2 2006.257.12:29:14.61#ibcon#read 6, iclass 40, count 2 2006.257.12:29:14.61#ibcon#end of sib2, iclass 40, count 2 2006.257.12:29:14.61#ibcon#*after write, iclass 40, count 2 2006.257.12:29:14.61#ibcon#*before return 0, iclass 40, count 2 2006.257.12:29:14.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:14.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:14.61#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.12:29:14.61#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:14.61#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:14.73#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:14.73#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:14.73#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:29:14.73#ibcon#first serial, iclass 40, count 0 2006.257.12:29:14.73#ibcon#enter sib2, iclass 40, count 0 2006.257.12:29:14.73#ibcon#flushed, iclass 40, count 0 2006.257.12:29:14.73#ibcon#about to write, iclass 40, count 0 2006.257.12:29:14.73#ibcon#wrote, iclass 40, count 0 2006.257.12:29:14.73#ibcon#about to read 3, iclass 40, count 0 2006.257.12:29:14.75#ibcon#read 3, iclass 40, count 0 2006.257.12:29:14.75#ibcon#about to read 4, iclass 40, count 0 2006.257.12:29:14.75#ibcon#read 4, iclass 40, count 0 2006.257.12:29:14.75#ibcon#about to read 5, iclass 40, count 0 2006.257.12:29:14.75#ibcon#read 5, iclass 40, count 0 2006.257.12:29:14.75#ibcon#about to read 6, iclass 40, count 0 2006.257.12:29:14.75#ibcon#read 6, iclass 40, count 0 2006.257.12:29:14.75#ibcon#end of sib2, iclass 40, count 0 2006.257.12:29:14.75#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:29:14.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:29:14.75#ibcon#[25=USB\r\n] 2006.257.12:29:14.75#ibcon#*before write, iclass 40, count 0 2006.257.12:29:14.75#ibcon#enter sib2, iclass 40, count 0 2006.257.12:29:14.75#ibcon#flushed, iclass 40, count 0 2006.257.12:29:14.75#ibcon#about to write, iclass 40, count 0 2006.257.12:29:14.75#ibcon#wrote, iclass 40, count 0 2006.257.12:29:14.75#ibcon#about to read 3, iclass 40, count 0 2006.257.12:29:14.78#ibcon#read 3, iclass 40, count 0 2006.257.12:29:14.78#ibcon#about to read 4, iclass 40, count 0 2006.257.12:29:14.78#ibcon#read 4, iclass 40, count 0 2006.257.12:29:14.78#ibcon#about to read 5, iclass 40, count 0 2006.257.12:29:14.78#ibcon#read 5, iclass 40, count 0 2006.257.12:29:14.78#ibcon#about to read 6, iclass 40, count 0 2006.257.12:29:14.78#ibcon#read 6, iclass 40, count 0 2006.257.12:29:14.78#ibcon#end of sib2, iclass 40, count 0 2006.257.12:29:14.78#ibcon#*after write, iclass 40, count 0 2006.257.12:29:14.78#ibcon#*before return 0, iclass 40, count 0 2006.257.12:29:14.78#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:14.78#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:14.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:29:14.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:29:14.78$vck44/valo=3,564.99 2006.257.12:29:14.78#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.12:29:14.78#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.12:29:14.78#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:14.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:14.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:14.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:14.78#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:29:14.78#ibcon#first serial, iclass 4, count 0 2006.257.12:29:14.78#ibcon#enter sib2, iclass 4, count 0 2006.257.12:29:14.78#ibcon#flushed, iclass 4, count 0 2006.257.12:29:14.78#ibcon#about to write, iclass 4, count 0 2006.257.12:29:14.78#ibcon#wrote, iclass 4, count 0 2006.257.12:29:14.78#ibcon#about to read 3, iclass 4, count 0 2006.257.12:29:14.80#ibcon#read 3, iclass 4, count 0 2006.257.12:29:14.80#ibcon#about to read 4, iclass 4, count 0 2006.257.12:29:14.80#ibcon#read 4, iclass 4, count 0 2006.257.12:29:14.80#ibcon#about to read 5, iclass 4, count 0 2006.257.12:29:14.80#ibcon#read 5, iclass 4, count 0 2006.257.12:29:14.80#ibcon#about to read 6, iclass 4, count 0 2006.257.12:29:14.80#ibcon#read 6, iclass 4, count 0 2006.257.12:29:14.80#ibcon#end of sib2, iclass 4, count 0 2006.257.12:29:14.80#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:29:14.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:29:14.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:29:14.80#ibcon#*before write, iclass 4, count 0 2006.257.12:29:14.80#ibcon#enter sib2, iclass 4, count 0 2006.257.12:29:14.80#ibcon#flushed, iclass 4, count 0 2006.257.12:29:14.80#ibcon#about to write, iclass 4, count 0 2006.257.12:29:14.80#ibcon#wrote, iclass 4, count 0 2006.257.12:29:14.80#ibcon#about to read 3, iclass 4, count 0 2006.257.12:29:14.84#ibcon#read 3, iclass 4, count 0 2006.257.12:29:14.84#ibcon#about to read 4, iclass 4, count 0 2006.257.12:29:14.84#ibcon#read 4, iclass 4, count 0 2006.257.12:29:14.84#ibcon#about to read 5, iclass 4, count 0 2006.257.12:29:14.84#ibcon#read 5, iclass 4, count 0 2006.257.12:29:14.84#ibcon#about to read 6, iclass 4, count 0 2006.257.12:29:14.84#ibcon#read 6, iclass 4, count 0 2006.257.12:29:14.84#ibcon#end of sib2, iclass 4, count 0 2006.257.12:29:14.84#ibcon#*after write, iclass 4, count 0 2006.257.12:29:14.84#ibcon#*before return 0, iclass 4, count 0 2006.257.12:29:14.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:14.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:14.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:29:14.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:29:14.84$vck44/va=3,8 2006.257.12:29:14.84#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.12:29:14.84#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.12:29:14.84#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:14.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:14.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:14.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:14.90#ibcon#enter wrdev, iclass 6, count 2 2006.257.12:29:14.90#ibcon#first serial, iclass 6, count 2 2006.257.12:29:14.90#ibcon#enter sib2, iclass 6, count 2 2006.257.12:29:14.90#ibcon#flushed, iclass 6, count 2 2006.257.12:29:14.90#ibcon#about to write, iclass 6, count 2 2006.257.12:29:14.90#ibcon#wrote, iclass 6, count 2 2006.257.12:29:14.90#ibcon#about to read 3, iclass 6, count 2 2006.257.12:29:14.92#ibcon#read 3, iclass 6, count 2 2006.257.12:29:14.92#ibcon#about to read 4, iclass 6, count 2 2006.257.12:29:14.92#ibcon#read 4, iclass 6, count 2 2006.257.12:29:14.92#ibcon#about to read 5, iclass 6, count 2 2006.257.12:29:14.92#ibcon#read 5, iclass 6, count 2 2006.257.12:29:14.92#ibcon#about to read 6, iclass 6, count 2 2006.257.12:29:14.92#ibcon#read 6, iclass 6, count 2 2006.257.12:29:14.92#ibcon#end of sib2, iclass 6, count 2 2006.257.12:29:14.92#ibcon#*mode == 0, iclass 6, count 2 2006.257.12:29:14.92#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.12:29:14.92#ibcon#[25=AT03-08\r\n] 2006.257.12:29:14.92#ibcon#*before write, iclass 6, count 2 2006.257.12:29:14.92#ibcon#enter sib2, iclass 6, count 2 2006.257.12:29:14.92#ibcon#flushed, iclass 6, count 2 2006.257.12:29:14.92#ibcon#about to write, iclass 6, count 2 2006.257.12:29:14.92#ibcon#wrote, iclass 6, count 2 2006.257.12:29:14.92#ibcon#about to read 3, iclass 6, count 2 2006.257.12:29:14.95#ibcon#read 3, iclass 6, count 2 2006.257.12:29:14.95#ibcon#about to read 4, iclass 6, count 2 2006.257.12:29:14.95#ibcon#read 4, iclass 6, count 2 2006.257.12:29:14.95#ibcon#about to read 5, iclass 6, count 2 2006.257.12:29:14.95#ibcon#read 5, iclass 6, count 2 2006.257.12:29:14.95#ibcon#about to read 6, iclass 6, count 2 2006.257.12:29:14.95#ibcon#read 6, iclass 6, count 2 2006.257.12:29:14.95#ibcon#end of sib2, iclass 6, count 2 2006.257.12:29:14.95#ibcon#*after write, iclass 6, count 2 2006.257.12:29:14.95#ibcon#*before return 0, iclass 6, count 2 2006.257.12:29:14.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:14.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:14.95#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.12:29:14.95#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:14.95#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:15.07#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:15.07#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:15.07#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:29:15.07#ibcon#first serial, iclass 6, count 0 2006.257.12:29:15.07#ibcon#enter sib2, iclass 6, count 0 2006.257.12:29:15.07#ibcon#flushed, iclass 6, count 0 2006.257.12:29:15.07#ibcon#about to write, iclass 6, count 0 2006.257.12:29:15.07#ibcon#wrote, iclass 6, count 0 2006.257.12:29:15.07#ibcon#about to read 3, iclass 6, count 0 2006.257.12:29:15.09#ibcon#read 3, iclass 6, count 0 2006.257.12:29:15.09#ibcon#about to read 4, iclass 6, count 0 2006.257.12:29:15.09#ibcon#read 4, iclass 6, count 0 2006.257.12:29:15.09#ibcon#about to read 5, iclass 6, count 0 2006.257.12:29:15.09#ibcon#read 5, iclass 6, count 0 2006.257.12:29:15.09#ibcon#about to read 6, iclass 6, count 0 2006.257.12:29:15.09#ibcon#read 6, iclass 6, count 0 2006.257.12:29:15.09#ibcon#end of sib2, iclass 6, count 0 2006.257.12:29:15.09#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:29:15.09#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:29:15.09#ibcon#[25=USB\r\n] 2006.257.12:29:15.09#ibcon#*before write, iclass 6, count 0 2006.257.12:29:15.09#ibcon#enter sib2, iclass 6, count 0 2006.257.12:29:15.09#ibcon#flushed, iclass 6, count 0 2006.257.12:29:15.09#ibcon#about to write, iclass 6, count 0 2006.257.12:29:15.09#ibcon#wrote, iclass 6, count 0 2006.257.12:29:15.09#ibcon#about to read 3, iclass 6, count 0 2006.257.12:29:15.12#ibcon#read 3, iclass 6, count 0 2006.257.12:29:15.12#ibcon#about to read 4, iclass 6, count 0 2006.257.12:29:15.12#ibcon#read 4, iclass 6, count 0 2006.257.12:29:15.12#ibcon#about to read 5, iclass 6, count 0 2006.257.12:29:15.12#ibcon#read 5, iclass 6, count 0 2006.257.12:29:15.12#ibcon#about to read 6, iclass 6, count 0 2006.257.12:29:15.12#ibcon#read 6, iclass 6, count 0 2006.257.12:29:15.12#ibcon#end of sib2, iclass 6, count 0 2006.257.12:29:15.12#ibcon#*after write, iclass 6, count 0 2006.257.12:29:15.12#ibcon#*before return 0, iclass 6, count 0 2006.257.12:29:15.12#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:15.12#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:15.12#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:29:15.12#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:29:15.12$vck44/valo=4,624.99 2006.257.12:29:15.12#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.12:29:15.12#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.12:29:15.12#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:15.12#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:15.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:15.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:15.12#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:29:15.12#ibcon#first serial, iclass 10, count 0 2006.257.12:29:15.12#ibcon#enter sib2, iclass 10, count 0 2006.257.12:29:15.12#ibcon#flushed, iclass 10, count 0 2006.257.12:29:15.12#ibcon#about to write, iclass 10, count 0 2006.257.12:29:15.12#ibcon#wrote, iclass 10, count 0 2006.257.12:29:15.12#ibcon#about to read 3, iclass 10, count 0 2006.257.12:29:15.14#ibcon#read 3, iclass 10, count 0 2006.257.12:29:15.14#ibcon#about to read 4, iclass 10, count 0 2006.257.12:29:15.14#ibcon#read 4, iclass 10, count 0 2006.257.12:29:15.14#ibcon#about to read 5, iclass 10, count 0 2006.257.12:29:15.14#ibcon#read 5, iclass 10, count 0 2006.257.12:29:15.14#ibcon#about to read 6, iclass 10, count 0 2006.257.12:29:15.14#ibcon#read 6, iclass 10, count 0 2006.257.12:29:15.14#ibcon#end of sib2, iclass 10, count 0 2006.257.12:29:15.14#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:29:15.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:29:15.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:29:15.14#ibcon#*before write, iclass 10, count 0 2006.257.12:29:15.14#ibcon#enter sib2, iclass 10, count 0 2006.257.12:29:15.14#ibcon#flushed, iclass 10, count 0 2006.257.12:29:15.14#ibcon#about to write, iclass 10, count 0 2006.257.12:29:15.14#ibcon#wrote, iclass 10, count 0 2006.257.12:29:15.14#ibcon#about to read 3, iclass 10, count 0 2006.257.12:29:15.18#ibcon#read 3, iclass 10, count 0 2006.257.12:29:15.18#ibcon#about to read 4, iclass 10, count 0 2006.257.12:29:15.18#ibcon#read 4, iclass 10, count 0 2006.257.12:29:15.18#ibcon#about to read 5, iclass 10, count 0 2006.257.12:29:15.18#ibcon#read 5, iclass 10, count 0 2006.257.12:29:15.18#ibcon#about to read 6, iclass 10, count 0 2006.257.12:29:15.18#ibcon#read 6, iclass 10, count 0 2006.257.12:29:15.18#ibcon#end of sib2, iclass 10, count 0 2006.257.12:29:15.18#ibcon#*after write, iclass 10, count 0 2006.257.12:29:15.18#ibcon#*before return 0, iclass 10, count 0 2006.257.12:29:15.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:15.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:15.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:29:15.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:29:15.18$vck44/va=4,7 2006.257.12:29:15.18#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.12:29:15.18#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.12:29:15.18#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:15.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:15.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:15.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:15.24#ibcon#enter wrdev, iclass 12, count 2 2006.257.12:29:15.24#ibcon#first serial, iclass 12, count 2 2006.257.12:29:15.24#ibcon#enter sib2, iclass 12, count 2 2006.257.12:29:15.24#ibcon#flushed, iclass 12, count 2 2006.257.12:29:15.24#ibcon#about to write, iclass 12, count 2 2006.257.12:29:15.24#ibcon#wrote, iclass 12, count 2 2006.257.12:29:15.24#ibcon#about to read 3, iclass 12, count 2 2006.257.12:29:15.26#ibcon#read 3, iclass 12, count 2 2006.257.12:29:15.26#ibcon#about to read 4, iclass 12, count 2 2006.257.12:29:15.26#ibcon#read 4, iclass 12, count 2 2006.257.12:29:15.26#ibcon#about to read 5, iclass 12, count 2 2006.257.12:29:15.26#ibcon#read 5, iclass 12, count 2 2006.257.12:29:15.26#ibcon#about to read 6, iclass 12, count 2 2006.257.12:29:15.26#ibcon#read 6, iclass 12, count 2 2006.257.12:29:15.26#ibcon#end of sib2, iclass 12, count 2 2006.257.12:29:15.26#ibcon#*mode == 0, iclass 12, count 2 2006.257.12:29:15.26#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.12:29:15.26#ibcon#[25=AT04-07\r\n] 2006.257.12:29:15.26#ibcon#*before write, iclass 12, count 2 2006.257.12:29:15.26#ibcon#enter sib2, iclass 12, count 2 2006.257.12:29:15.26#ibcon#flushed, iclass 12, count 2 2006.257.12:29:15.26#ibcon#about to write, iclass 12, count 2 2006.257.12:29:15.26#ibcon#wrote, iclass 12, count 2 2006.257.12:29:15.26#ibcon#about to read 3, iclass 12, count 2 2006.257.12:29:15.29#ibcon#read 3, iclass 12, count 2 2006.257.12:29:15.29#ibcon#about to read 4, iclass 12, count 2 2006.257.12:29:15.29#ibcon#read 4, iclass 12, count 2 2006.257.12:29:15.29#ibcon#about to read 5, iclass 12, count 2 2006.257.12:29:15.29#ibcon#read 5, iclass 12, count 2 2006.257.12:29:15.29#ibcon#about to read 6, iclass 12, count 2 2006.257.12:29:15.29#ibcon#read 6, iclass 12, count 2 2006.257.12:29:15.29#ibcon#end of sib2, iclass 12, count 2 2006.257.12:29:15.29#ibcon#*after write, iclass 12, count 2 2006.257.12:29:15.29#ibcon#*before return 0, iclass 12, count 2 2006.257.12:29:15.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:15.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:15.29#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.12:29:15.29#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:15.29#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:15.41#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:15.41#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:15.41#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:29:15.41#ibcon#first serial, iclass 12, count 0 2006.257.12:29:15.41#ibcon#enter sib2, iclass 12, count 0 2006.257.12:29:15.41#ibcon#flushed, iclass 12, count 0 2006.257.12:29:15.41#ibcon#about to write, iclass 12, count 0 2006.257.12:29:15.41#ibcon#wrote, iclass 12, count 0 2006.257.12:29:15.41#ibcon#about to read 3, iclass 12, count 0 2006.257.12:29:15.43#ibcon#read 3, iclass 12, count 0 2006.257.12:29:15.43#ibcon#about to read 4, iclass 12, count 0 2006.257.12:29:15.43#ibcon#read 4, iclass 12, count 0 2006.257.12:29:15.43#ibcon#about to read 5, iclass 12, count 0 2006.257.12:29:15.43#ibcon#read 5, iclass 12, count 0 2006.257.12:29:15.43#ibcon#about to read 6, iclass 12, count 0 2006.257.12:29:15.43#ibcon#read 6, iclass 12, count 0 2006.257.12:29:15.43#ibcon#end of sib2, iclass 12, count 0 2006.257.12:29:15.43#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:29:15.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:29:15.43#ibcon#[25=USB\r\n] 2006.257.12:29:15.43#ibcon#*before write, iclass 12, count 0 2006.257.12:29:15.43#ibcon#enter sib2, iclass 12, count 0 2006.257.12:29:15.43#ibcon#flushed, iclass 12, count 0 2006.257.12:29:15.43#ibcon#about to write, iclass 12, count 0 2006.257.12:29:15.43#ibcon#wrote, iclass 12, count 0 2006.257.12:29:15.43#ibcon#about to read 3, iclass 12, count 0 2006.257.12:29:15.46#ibcon#read 3, iclass 12, count 0 2006.257.12:29:15.46#ibcon#about to read 4, iclass 12, count 0 2006.257.12:29:15.46#ibcon#read 4, iclass 12, count 0 2006.257.12:29:15.46#ibcon#about to read 5, iclass 12, count 0 2006.257.12:29:15.46#ibcon#read 5, iclass 12, count 0 2006.257.12:29:15.46#ibcon#about to read 6, iclass 12, count 0 2006.257.12:29:15.46#ibcon#read 6, iclass 12, count 0 2006.257.12:29:15.46#ibcon#end of sib2, iclass 12, count 0 2006.257.12:29:15.46#ibcon#*after write, iclass 12, count 0 2006.257.12:29:15.46#ibcon#*before return 0, iclass 12, count 0 2006.257.12:29:15.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:15.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:15.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:29:15.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:29:15.46$vck44/valo=5,734.99 2006.257.12:29:15.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.12:29:15.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.12:29:15.46#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:15.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:15.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:15.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:15.46#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:29:15.46#ibcon#first serial, iclass 14, count 0 2006.257.12:29:15.46#ibcon#enter sib2, iclass 14, count 0 2006.257.12:29:15.46#ibcon#flushed, iclass 14, count 0 2006.257.12:29:15.46#ibcon#about to write, iclass 14, count 0 2006.257.12:29:15.46#ibcon#wrote, iclass 14, count 0 2006.257.12:29:15.46#ibcon#about to read 3, iclass 14, count 0 2006.257.12:29:15.48#ibcon#read 3, iclass 14, count 0 2006.257.12:29:15.48#ibcon#about to read 4, iclass 14, count 0 2006.257.12:29:15.48#ibcon#read 4, iclass 14, count 0 2006.257.12:29:15.48#ibcon#about to read 5, iclass 14, count 0 2006.257.12:29:15.48#ibcon#read 5, iclass 14, count 0 2006.257.12:29:15.48#ibcon#about to read 6, iclass 14, count 0 2006.257.12:29:15.48#ibcon#read 6, iclass 14, count 0 2006.257.12:29:15.48#ibcon#end of sib2, iclass 14, count 0 2006.257.12:29:15.48#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:29:15.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:29:15.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:29:15.48#ibcon#*before write, iclass 14, count 0 2006.257.12:29:15.48#ibcon#enter sib2, iclass 14, count 0 2006.257.12:29:15.48#ibcon#flushed, iclass 14, count 0 2006.257.12:29:15.48#ibcon#about to write, iclass 14, count 0 2006.257.12:29:15.48#ibcon#wrote, iclass 14, count 0 2006.257.12:29:15.48#ibcon#about to read 3, iclass 14, count 0 2006.257.12:29:15.52#ibcon#read 3, iclass 14, count 0 2006.257.12:29:15.52#ibcon#about to read 4, iclass 14, count 0 2006.257.12:29:15.52#ibcon#read 4, iclass 14, count 0 2006.257.12:29:15.52#ibcon#about to read 5, iclass 14, count 0 2006.257.12:29:15.52#ibcon#read 5, iclass 14, count 0 2006.257.12:29:15.52#ibcon#about to read 6, iclass 14, count 0 2006.257.12:29:15.52#ibcon#read 6, iclass 14, count 0 2006.257.12:29:15.52#ibcon#end of sib2, iclass 14, count 0 2006.257.12:29:15.52#ibcon#*after write, iclass 14, count 0 2006.257.12:29:15.52#ibcon#*before return 0, iclass 14, count 0 2006.257.12:29:15.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:15.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:15.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:29:15.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:29:15.52$vck44/va=5,4 2006.257.12:29:15.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.12:29:15.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.12:29:15.52#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:15.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:15.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:15.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:15.58#ibcon#enter wrdev, iclass 16, count 2 2006.257.12:29:15.58#ibcon#first serial, iclass 16, count 2 2006.257.12:29:15.58#ibcon#enter sib2, iclass 16, count 2 2006.257.12:29:15.58#ibcon#flushed, iclass 16, count 2 2006.257.12:29:15.58#ibcon#about to write, iclass 16, count 2 2006.257.12:29:15.58#ibcon#wrote, iclass 16, count 2 2006.257.12:29:15.58#ibcon#about to read 3, iclass 16, count 2 2006.257.12:29:15.60#ibcon#read 3, iclass 16, count 2 2006.257.12:29:15.60#ibcon#about to read 4, iclass 16, count 2 2006.257.12:29:15.60#ibcon#read 4, iclass 16, count 2 2006.257.12:29:15.60#ibcon#about to read 5, iclass 16, count 2 2006.257.12:29:15.60#ibcon#read 5, iclass 16, count 2 2006.257.12:29:15.60#ibcon#about to read 6, iclass 16, count 2 2006.257.12:29:15.60#ibcon#read 6, iclass 16, count 2 2006.257.12:29:15.60#ibcon#end of sib2, iclass 16, count 2 2006.257.12:29:15.60#ibcon#*mode == 0, iclass 16, count 2 2006.257.12:29:15.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.12:29:15.60#ibcon#[25=AT05-04\r\n] 2006.257.12:29:15.60#ibcon#*before write, iclass 16, count 2 2006.257.12:29:15.60#ibcon#enter sib2, iclass 16, count 2 2006.257.12:29:15.60#ibcon#flushed, iclass 16, count 2 2006.257.12:29:15.60#ibcon#about to write, iclass 16, count 2 2006.257.12:29:15.60#ibcon#wrote, iclass 16, count 2 2006.257.12:29:15.60#ibcon#about to read 3, iclass 16, count 2 2006.257.12:29:15.63#ibcon#read 3, iclass 16, count 2 2006.257.12:29:15.63#ibcon#about to read 4, iclass 16, count 2 2006.257.12:29:15.63#ibcon#read 4, iclass 16, count 2 2006.257.12:29:15.63#ibcon#about to read 5, iclass 16, count 2 2006.257.12:29:15.63#ibcon#read 5, iclass 16, count 2 2006.257.12:29:15.63#ibcon#about to read 6, iclass 16, count 2 2006.257.12:29:15.63#ibcon#read 6, iclass 16, count 2 2006.257.12:29:15.63#ibcon#end of sib2, iclass 16, count 2 2006.257.12:29:15.63#ibcon#*after write, iclass 16, count 2 2006.257.12:29:15.63#ibcon#*before return 0, iclass 16, count 2 2006.257.12:29:15.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:15.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:15.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.12:29:15.63#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:15.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:15.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:15.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:15.75#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:29:15.75#ibcon#first serial, iclass 16, count 0 2006.257.12:29:15.75#ibcon#enter sib2, iclass 16, count 0 2006.257.12:29:15.75#ibcon#flushed, iclass 16, count 0 2006.257.12:29:15.75#ibcon#about to write, iclass 16, count 0 2006.257.12:29:15.75#ibcon#wrote, iclass 16, count 0 2006.257.12:29:15.75#ibcon#about to read 3, iclass 16, count 0 2006.257.12:29:15.77#ibcon#read 3, iclass 16, count 0 2006.257.12:29:15.77#ibcon#about to read 4, iclass 16, count 0 2006.257.12:29:15.77#ibcon#read 4, iclass 16, count 0 2006.257.12:29:15.77#ibcon#about to read 5, iclass 16, count 0 2006.257.12:29:15.77#ibcon#read 5, iclass 16, count 0 2006.257.12:29:15.77#ibcon#about to read 6, iclass 16, count 0 2006.257.12:29:15.77#ibcon#read 6, iclass 16, count 0 2006.257.12:29:15.77#ibcon#end of sib2, iclass 16, count 0 2006.257.12:29:15.77#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:29:15.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:29:15.77#ibcon#[25=USB\r\n] 2006.257.12:29:15.77#ibcon#*before write, iclass 16, count 0 2006.257.12:29:15.77#ibcon#enter sib2, iclass 16, count 0 2006.257.12:29:15.77#ibcon#flushed, iclass 16, count 0 2006.257.12:29:15.77#ibcon#about to write, iclass 16, count 0 2006.257.12:29:15.77#ibcon#wrote, iclass 16, count 0 2006.257.12:29:15.77#ibcon#about to read 3, iclass 16, count 0 2006.257.12:29:15.80#ibcon#read 3, iclass 16, count 0 2006.257.12:29:15.80#ibcon#about to read 4, iclass 16, count 0 2006.257.12:29:15.80#ibcon#read 4, iclass 16, count 0 2006.257.12:29:15.80#ibcon#about to read 5, iclass 16, count 0 2006.257.12:29:15.80#ibcon#read 5, iclass 16, count 0 2006.257.12:29:15.80#ibcon#about to read 6, iclass 16, count 0 2006.257.12:29:15.80#ibcon#read 6, iclass 16, count 0 2006.257.12:29:15.80#ibcon#end of sib2, iclass 16, count 0 2006.257.12:29:15.80#ibcon#*after write, iclass 16, count 0 2006.257.12:29:15.80#ibcon#*before return 0, iclass 16, count 0 2006.257.12:29:15.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:15.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:15.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:29:15.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:29:15.80$vck44/valo=6,814.99 2006.257.12:29:15.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.12:29:15.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.12:29:15.80#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:15.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:15.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:15.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:15.80#ibcon#enter wrdev, iclass 18, count 0 2006.257.12:29:15.80#ibcon#first serial, iclass 18, count 0 2006.257.12:29:15.80#ibcon#enter sib2, iclass 18, count 0 2006.257.12:29:15.80#ibcon#flushed, iclass 18, count 0 2006.257.12:29:15.80#ibcon#about to write, iclass 18, count 0 2006.257.12:29:15.80#ibcon#wrote, iclass 18, count 0 2006.257.12:29:15.80#ibcon#about to read 3, iclass 18, count 0 2006.257.12:29:15.82#ibcon#read 3, iclass 18, count 0 2006.257.12:29:15.82#ibcon#about to read 4, iclass 18, count 0 2006.257.12:29:15.82#ibcon#read 4, iclass 18, count 0 2006.257.12:29:15.82#ibcon#about to read 5, iclass 18, count 0 2006.257.12:29:15.82#ibcon#read 5, iclass 18, count 0 2006.257.12:29:15.82#ibcon#about to read 6, iclass 18, count 0 2006.257.12:29:15.82#ibcon#read 6, iclass 18, count 0 2006.257.12:29:15.82#ibcon#end of sib2, iclass 18, count 0 2006.257.12:29:15.82#ibcon#*mode == 0, iclass 18, count 0 2006.257.12:29:15.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.12:29:15.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:29:15.82#ibcon#*before write, iclass 18, count 0 2006.257.12:29:15.82#ibcon#enter sib2, iclass 18, count 0 2006.257.12:29:15.82#ibcon#flushed, iclass 18, count 0 2006.257.12:29:15.82#ibcon#about to write, iclass 18, count 0 2006.257.12:29:15.82#ibcon#wrote, iclass 18, count 0 2006.257.12:29:15.82#ibcon#about to read 3, iclass 18, count 0 2006.257.12:29:15.86#ibcon#read 3, iclass 18, count 0 2006.257.12:29:15.86#ibcon#about to read 4, iclass 18, count 0 2006.257.12:29:15.86#ibcon#read 4, iclass 18, count 0 2006.257.12:29:15.86#ibcon#about to read 5, iclass 18, count 0 2006.257.12:29:15.86#ibcon#read 5, iclass 18, count 0 2006.257.12:29:15.86#ibcon#about to read 6, iclass 18, count 0 2006.257.12:29:15.86#ibcon#read 6, iclass 18, count 0 2006.257.12:29:15.86#ibcon#end of sib2, iclass 18, count 0 2006.257.12:29:15.86#ibcon#*after write, iclass 18, count 0 2006.257.12:29:15.86#ibcon#*before return 0, iclass 18, count 0 2006.257.12:29:15.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:15.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:15.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.12:29:15.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.12:29:15.86$vck44/va=6,4 2006.257.12:29:15.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.12:29:15.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.12:29:15.86#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:15.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:15.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:15.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:15.92#ibcon#enter wrdev, iclass 20, count 2 2006.257.12:29:15.92#ibcon#first serial, iclass 20, count 2 2006.257.12:29:15.92#ibcon#enter sib2, iclass 20, count 2 2006.257.12:29:15.92#ibcon#flushed, iclass 20, count 2 2006.257.12:29:15.92#ibcon#about to write, iclass 20, count 2 2006.257.12:29:15.92#ibcon#wrote, iclass 20, count 2 2006.257.12:29:15.92#ibcon#about to read 3, iclass 20, count 2 2006.257.12:29:15.94#ibcon#read 3, iclass 20, count 2 2006.257.12:29:15.94#ibcon#about to read 4, iclass 20, count 2 2006.257.12:29:15.94#ibcon#read 4, iclass 20, count 2 2006.257.12:29:15.94#ibcon#about to read 5, iclass 20, count 2 2006.257.12:29:15.94#ibcon#read 5, iclass 20, count 2 2006.257.12:29:15.94#ibcon#about to read 6, iclass 20, count 2 2006.257.12:29:15.94#ibcon#read 6, iclass 20, count 2 2006.257.12:29:15.94#ibcon#end of sib2, iclass 20, count 2 2006.257.12:29:15.94#ibcon#*mode == 0, iclass 20, count 2 2006.257.12:29:15.94#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.12:29:15.94#ibcon#[25=AT06-04\r\n] 2006.257.12:29:15.94#ibcon#*before write, iclass 20, count 2 2006.257.12:29:15.94#ibcon#enter sib2, iclass 20, count 2 2006.257.12:29:15.94#ibcon#flushed, iclass 20, count 2 2006.257.12:29:15.94#ibcon#about to write, iclass 20, count 2 2006.257.12:29:15.94#ibcon#wrote, iclass 20, count 2 2006.257.12:29:15.94#ibcon#about to read 3, iclass 20, count 2 2006.257.12:29:15.97#ibcon#read 3, iclass 20, count 2 2006.257.12:29:15.97#ibcon#about to read 4, iclass 20, count 2 2006.257.12:29:15.97#ibcon#read 4, iclass 20, count 2 2006.257.12:29:15.97#ibcon#about to read 5, iclass 20, count 2 2006.257.12:29:15.97#ibcon#read 5, iclass 20, count 2 2006.257.12:29:15.97#ibcon#about to read 6, iclass 20, count 2 2006.257.12:29:15.97#ibcon#read 6, iclass 20, count 2 2006.257.12:29:15.97#ibcon#end of sib2, iclass 20, count 2 2006.257.12:29:15.97#ibcon#*after write, iclass 20, count 2 2006.257.12:29:15.97#ibcon#*before return 0, iclass 20, count 2 2006.257.12:29:15.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:15.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:15.97#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.12:29:15.97#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:15.97#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:16.09#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:16.09#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:16.09#ibcon#enter wrdev, iclass 20, count 0 2006.257.12:29:16.09#ibcon#first serial, iclass 20, count 0 2006.257.12:29:16.09#ibcon#enter sib2, iclass 20, count 0 2006.257.12:29:16.09#ibcon#flushed, iclass 20, count 0 2006.257.12:29:16.09#ibcon#about to write, iclass 20, count 0 2006.257.12:29:16.09#ibcon#wrote, iclass 20, count 0 2006.257.12:29:16.09#ibcon#about to read 3, iclass 20, count 0 2006.257.12:29:16.11#ibcon#read 3, iclass 20, count 0 2006.257.12:29:16.11#ibcon#about to read 4, iclass 20, count 0 2006.257.12:29:16.11#ibcon#read 4, iclass 20, count 0 2006.257.12:29:16.11#ibcon#about to read 5, iclass 20, count 0 2006.257.12:29:16.11#ibcon#read 5, iclass 20, count 0 2006.257.12:29:16.11#ibcon#about to read 6, iclass 20, count 0 2006.257.12:29:16.11#ibcon#read 6, iclass 20, count 0 2006.257.12:29:16.11#ibcon#end of sib2, iclass 20, count 0 2006.257.12:29:16.11#ibcon#*mode == 0, iclass 20, count 0 2006.257.12:29:16.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.12:29:16.11#ibcon#[25=USB\r\n] 2006.257.12:29:16.11#ibcon#*before write, iclass 20, count 0 2006.257.12:29:16.11#ibcon#enter sib2, iclass 20, count 0 2006.257.12:29:16.11#ibcon#flushed, iclass 20, count 0 2006.257.12:29:16.11#ibcon#about to write, iclass 20, count 0 2006.257.12:29:16.11#ibcon#wrote, iclass 20, count 0 2006.257.12:29:16.11#ibcon#about to read 3, iclass 20, count 0 2006.257.12:29:16.14#ibcon#read 3, iclass 20, count 0 2006.257.12:29:16.14#ibcon#about to read 4, iclass 20, count 0 2006.257.12:29:16.14#ibcon#read 4, iclass 20, count 0 2006.257.12:29:16.14#ibcon#about to read 5, iclass 20, count 0 2006.257.12:29:16.14#ibcon#read 5, iclass 20, count 0 2006.257.12:29:16.14#ibcon#about to read 6, iclass 20, count 0 2006.257.12:29:16.14#ibcon#read 6, iclass 20, count 0 2006.257.12:29:16.14#ibcon#end of sib2, iclass 20, count 0 2006.257.12:29:16.14#ibcon#*after write, iclass 20, count 0 2006.257.12:29:16.14#ibcon#*before return 0, iclass 20, count 0 2006.257.12:29:16.14#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:16.14#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:16.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.12:29:16.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.12:29:16.14$vck44/valo=7,864.99 2006.257.12:29:16.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.12:29:16.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.12:29:16.14#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:16.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:16.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:16.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:16.14#ibcon#enter wrdev, iclass 22, count 0 2006.257.12:29:16.14#ibcon#first serial, iclass 22, count 0 2006.257.12:29:16.14#ibcon#enter sib2, iclass 22, count 0 2006.257.12:29:16.14#ibcon#flushed, iclass 22, count 0 2006.257.12:29:16.14#ibcon#about to write, iclass 22, count 0 2006.257.12:29:16.14#ibcon#wrote, iclass 22, count 0 2006.257.12:29:16.14#ibcon#about to read 3, iclass 22, count 0 2006.257.12:29:16.16#ibcon#read 3, iclass 22, count 0 2006.257.12:29:16.16#ibcon#about to read 4, iclass 22, count 0 2006.257.12:29:16.16#ibcon#read 4, iclass 22, count 0 2006.257.12:29:16.16#ibcon#about to read 5, iclass 22, count 0 2006.257.12:29:16.16#ibcon#read 5, iclass 22, count 0 2006.257.12:29:16.16#ibcon#about to read 6, iclass 22, count 0 2006.257.12:29:16.16#ibcon#read 6, iclass 22, count 0 2006.257.12:29:16.16#ibcon#end of sib2, iclass 22, count 0 2006.257.12:29:16.16#ibcon#*mode == 0, iclass 22, count 0 2006.257.12:29:16.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.12:29:16.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:29:16.16#ibcon#*before write, iclass 22, count 0 2006.257.12:29:16.16#ibcon#enter sib2, iclass 22, count 0 2006.257.12:29:16.16#ibcon#flushed, iclass 22, count 0 2006.257.12:29:16.16#ibcon#about to write, iclass 22, count 0 2006.257.12:29:16.16#ibcon#wrote, iclass 22, count 0 2006.257.12:29:16.16#ibcon#about to read 3, iclass 22, count 0 2006.257.12:29:16.20#ibcon#read 3, iclass 22, count 0 2006.257.12:29:16.20#ibcon#about to read 4, iclass 22, count 0 2006.257.12:29:16.20#ibcon#read 4, iclass 22, count 0 2006.257.12:29:16.20#ibcon#about to read 5, iclass 22, count 0 2006.257.12:29:16.20#ibcon#read 5, iclass 22, count 0 2006.257.12:29:16.20#ibcon#about to read 6, iclass 22, count 0 2006.257.12:29:16.20#ibcon#read 6, iclass 22, count 0 2006.257.12:29:16.20#ibcon#end of sib2, iclass 22, count 0 2006.257.12:29:16.20#ibcon#*after write, iclass 22, count 0 2006.257.12:29:16.20#ibcon#*before return 0, iclass 22, count 0 2006.257.12:29:16.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:16.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:16.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.12:29:16.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.12:29:16.20$vck44/va=7,4 2006.257.12:29:16.20#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.12:29:16.20#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.12:29:16.20#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:16.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:16.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:16.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:16.26#ibcon#enter wrdev, iclass 24, count 2 2006.257.12:29:16.26#ibcon#first serial, iclass 24, count 2 2006.257.12:29:16.26#ibcon#enter sib2, iclass 24, count 2 2006.257.12:29:16.26#ibcon#flushed, iclass 24, count 2 2006.257.12:29:16.26#ibcon#about to write, iclass 24, count 2 2006.257.12:29:16.26#ibcon#wrote, iclass 24, count 2 2006.257.12:29:16.26#ibcon#about to read 3, iclass 24, count 2 2006.257.12:29:16.28#ibcon#read 3, iclass 24, count 2 2006.257.12:29:16.28#ibcon#about to read 4, iclass 24, count 2 2006.257.12:29:16.28#ibcon#read 4, iclass 24, count 2 2006.257.12:29:16.28#ibcon#about to read 5, iclass 24, count 2 2006.257.12:29:16.28#ibcon#read 5, iclass 24, count 2 2006.257.12:29:16.28#ibcon#about to read 6, iclass 24, count 2 2006.257.12:29:16.28#ibcon#read 6, iclass 24, count 2 2006.257.12:29:16.28#ibcon#end of sib2, iclass 24, count 2 2006.257.12:29:16.28#ibcon#*mode == 0, iclass 24, count 2 2006.257.12:29:16.28#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.12:29:16.28#ibcon#[25=AT07-04\r\n] 2006.257.12:29:16.28#ibcon#*before write, iclass 24, count 2 2006.257.12:29:16.28#ibcon#enter sib2, iclass 24, count 2 2006.257.12:29:16.28#ibcon#flushed, iclass 24, count 2 2006.257.12:29:16.28#ibcon#about to write, iclass 24, count 2 2006.257.12:29:16.28#ibcon#wrote, iclass 24, count 2 2006.257.12:29:16.28#ibcon#about to read 3, iclass 24, count 2 2006.257.12:29:16.31#ibcon#read 3, iclass 24, count 2 2006.257.12:29:16.31#ibcon#about to read 4, iclass 24, count 2 2006.257.12:29:16.31#ibcon#read 4, iclass 24, count 2 2006.257.12:29:16.31#ibcon#about to read 5, iclass 24, count 2 2006.257.12:29:16.31#ibcon#read 5, iclass 24, count 2 2006.257.12:29:16.31#ibcon#about to read 6, iclass 24, count 2 2006.257.12:29:16.31#ibcon#read 6, iclass 24, count 2 2006.257.12:29:16.31#ibcon#end of sib2, iclass 24, count 2 2006.257.12:29:16.31#ibcon#*after write, iclass 24, count 2 2006.257.12:29:16.31#ibcon#*before return 0, iclass 24, count 2 2006.257.12:29:16.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:16.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:16.31#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.12:29:16.31#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:16.31#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:16.43#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:16.43#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:16.43#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:29:16.43#ibcon#first serial, iclass 24, count 0 2006.257.12:29:16.43#ibcon#enter sib2, iclass 24, count 0 2006.257.12:29:16.43#ibcon#flushed, iclass 24, count 0 2006.257.12:29:16.43#ibcon#about to write, iclass 24, count 0 2006.257.12:29:16.43#ibcon#wrote, iclass 24, count 0 2006.257.12:29:16.43#ibcon#about to read 3, iclass 24, count 0 2006.257.12:29:16.45#ibcon#read 3, iclass 24, count 0 2006.257.12:29:16.45#ibcon#about to read 4, iclass 24, count 0 2006.257.12:29:16.45#ibcon#read 4, iclass 24, count 0 2006.257.12:29:16.45#ibcon#about to read 5, iclass 24, count 0 2006.257.12:29:16.45#ibcon#read 5, iclass 24, count 0 2006.257.12:29:16.45#ibcon#about to read 6, iclass 24, count 0 2006.257.12:29:16.45#ibcon#read 6, iclass 24, count 0 2006.257.12:29:16.45#ibcon#end of sib2, iclass 24, count 0 2006.257.12:29:16.45#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:29:16.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:29:16.45#ibcon#[25=USB\r\n] 2006.257.12:29:16.45#ibcon#*before write, iclass 24, count 0 2006.257.12:29:16.45#ibcon#enter sib2, iclass 24, count 0 2006.257.12:29:16.45#ibcon#flushed, iclass 24, count 0 2006.257.12:29:16.45#ibcon#about to write, iclass 24, count 0 2006.257.12:29:16.45#ibcon#wrote, iclass 24, count 0 2006.257.12:29:16.45#ibcon#about to read 3, iclass 24, count 0 2006.257.12:29:16.48#ibcon#read 3, iclass 24, count 0 2006.257.12:29:16.48#ibcon#about to read 4, iclass 24, count 0 2006.257.12:29:16.48#ibcon#read 4, iclass 24, count 0 2006.257.12:29:16.48#ibcon#about to read 5, iclass 24, count 0 2006.257.12:29:16.48#ibcon#read 5, iclass 24, count 0 2006.257.12:29:16.48#ibcon#about to read 6, iclass 24, count 0 2006.257.12:29:16.48#ibcon#read 6, iclass 24, count 0 2006.257.12:29:16.48#ibcon#end of sib2, iclass 24, count 0 2006.257.12:29:16.48#ibcon#*after write, iclass 24, count 0 2006.257.12:29:16.48#ibcon#*before return 0, iclass 24, count 0 2006.257.12:29:16.48#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:16.48#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:16.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:29:16.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:29:16.48$vck44/valo=8,884.99 2006.257.12:29:16.48#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.12:29:16.48#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.12:29:16.48#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:16.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:16.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:16.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:16.48#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:29:16.48#ibcon#first serial, iclass 26, count 0 2006.257.12:29:16.48#ibcon#enter sib2, iclass 26, count 0 2006.257.12:29:16.48#ibcon#flushed, iclass 26, count 0 2006.257.12:29:16.48#ibcon#about to write, iclass 26, count 0 2006.257.12:29:16.48#ibcon#wrote, iclass 26, count 0 2006.257.12:29:16.48#ibcon#about to read 3, iclass 26, count 0 2006.257.12:29:16.50#ibcon#read 3, iclass 26, count 0 2006.257.12:29:16.50#ibcon#about to read 4, iclass 26, count 0 2006.257.12:29:16.50#ibcon#read 4, iclass 26, count 0 2006.257.12:29:16.50#ibcon#about to read 5, iclass 26, count 0 2006.257.12:29:16.50#ibcon#read 5, iclass 26, count 0 2006.257.12:29:16.50#ibcon#about to read 6, iclass 26, count 0 2006.257.12:29:16.50#ibcon#read 6, iclass 26, count 0 2006.257.12:29:16.50#ibcon#end of sib2, iclass 26, count 0 2006.257.12:29:16.50#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:29:16.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:29:16.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:29:16.50#ibcon#*before write, iclass 26, count 0 2006.257.12:29:16.50#ibcon#enter sib2, iclass 26, count 0 2006.257.12:29:16.50#ibcon#flushed, iclass 26, count 0 2006.257.12:29:16.50#ibcon#about to write, iclass 26, count 0 2006.257.12:29:16.50#ibcon#wrote, iclass 26, count 0 2006.257.12:29:16.50#ibcon#about to read 3, iclass 26, count 0 2006.257.12:29:16.54#ibcon#read 3, iclass 26, count 0 2006.257.12:29:16.54#ibcon#about to read 4, iclass 26, count 0 2006.257.12:29:16.54#ibcon#read 4, iclass 26, count 0 2006.257.12:29:16.54#ibcon#about to read 5, iclass 26, count 0 2006.257.12:29:16.54#ibcon#read 5, iclass 26, count 0 2006.257.12:29:16.54#ibcon#about to read 6, iclass 26, count 0 2006.257.12:29:16.54#ibcon#read 6, iclass 26, count 0 2006.257.12:29:16.54#ibcon#end of sib2, iclass 26, count 0 2006.257.12:29:16.54#ibcon#*after write, iclass 26, count 0 2006.257.12:29:16.54#ibcon#*before return 0, iclass 26, count 0 2006.257.12:29:16.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:16.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:16.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:29:16.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:29:16.54$vck44/va=8,4 2006.257.12:29:16.54#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.12:29:16.54#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.12:29:16.54#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:16.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:29:16.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:29:16.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:29:16.60#ibcon#enter wrdev, iclass 28, count 2 2006.257.12:29:16.60#ibcon#first serial, iclass 28, count 2 2006.257.12:29:16.60#ibcon#enter sib2, iclass 28, count 2 2006.257.12:29:16.60#ibcon#flushed, iclass 28, count 2 2006.257.12:29:16.60#ibcon#about to write, iclass 28, count 2 2006.257.12:29:16.60#ibcon#wrote, iclass 28, count 2 2006.257.12:29:16.60#ibcon#about to read 3, iclass 28, count 2 2006.257.12:29:16.62#ibcon#read 3, iclass 28, count 2 2006.257.12:29:16.62#ibcon#about to read 4, iclass 28, count 2 2006.257.12:29:16.62#ibcon#read 4, iclass 28, count 2 2006.257.12:29:16.62#ibcon#about to read 5, iclass 28, count 2 2006.257.12:29:16.62#ibcon#read 5, iclass 28, count 2 2006.257.12:29:16.62#ibcon#about to read 6, iclass 28, count 2 2006.257.12:29:16.62#ibcon#read 6, iclass 28, count 2 2006.257.12:29:16.62#ibcon#end of sib2, iclass 28, count 2 2006.257.12:29:16.62#ibcon#*mode == 0, iclass 28, count 2 2006.257.12:29:16.62#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.12:29:16.62#ibcon#[25=AT08-04\r\n] 2006.257.12:29:16.62#ibcon#*before write, iclass 28, count 2 2006.257.12:29:16.62#ibcon#enter sib2, iclass 28, count 2 2006.257.12:29:16.62#ibcon#flushed, iclass 28, count 2 2006.257.12:29:16.62#ibcon#about to write, iclass 28, count 2 2006.257.12:29:16.62#ibcon#wrote, iclass 28, count 2 2006.257.12:29:16.62#ibcon#about to read 3, iclass 28, count 2 2006.257.12:29:16.65#ibcon#read 3, iclass 28, count 2 2006.257.12:29:16.65#ibcon#about to read 4, iclass 28, count 2 2006.257.12:29:16.65#ibcon#read 4, iclass 28, count 2 2006.257.12:29:16.65#ibcon#about to read 5, iclass 28, count 2 2006.257.12:29:16.65#ibcon#read 5, iclass 28, count 2 2006.257.12:29:16.65#ibcon#about to read 6, iclass 28, count 2 2006.257.12:29:16.65#ibcon#read 6, iclass 28, count 2 2006.257.12:29:16.65#ibcon#end of sib2, iclass 28, count 2 2006.257.12:29:16.65#ibcon#*after write, iclass 28, count 2 2006.257.12:29:16.65#ibcon#*before return 0, iclass 28, count 2 2006.257.12:29:16.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:29:16.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:29:16.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.12:29:16.65#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:16.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:29:16.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:29:16.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:29:16.77#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:29:16.77#ibcon#first serial, iclass 28, count 0 2006.257.12:29:16.77#ibcon#enter sib2, iclass 28, count 0 2006.257.12:29:16.77#ibcon#flushed, iclass 28, count 0 2006.257.12:29:16.77#ibcon#about to write, iclass 28, count 0 2006.257.12:29:16.77#ibcon#wrote, iclass 28, count 0 2006.257.12:29:16.77#ibcon#about to read 3, iclass 28, count 0 2006.257.12:29:16.79#ibcon#read 3, iclass 28, count 0 2006.257.12:29:16.79#ibcon#about to read 4, iclass 28, count 0 2006.257.12:29:16.79#ibcon#read 4, iclass 28, count 0 2006.257.12:29:16.79#ibcon#about to read 5, iclass 28, count 0 2006.257.12:29:16.79#ibcon#read 5, iclass 28, count 0 2006.257.12:29:16.79#ibcon#about to read 6, iclass 28, count 0 2006.257.12:29:16.79#ibcon#read 6, iclass 28, count 0 2006.257.12:29:16.79#ibcon#end of sib2, iclass 28, count 0 2006.257.12:29:16.79#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:29:16.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:29:16.79#ibcon#[25=USB\r\n] 2006.257.12:29:16.79#ibcon#*before write, iclass 28, count 0 2006.257.12:29:16.79#ibcon#enter sib2, iclass 28, count 0 2006.257.12:29:16.79#ibcon#flushed, iclass 28, count 0 2006.257.12:29:16.79#ibcon#about to write, iclass 28, count 0 2006.257.12:29:16.79#ibcon#wrote, iclass 28, count 0 2006.257.12:29:16.79#ibcon#about to read 3, iclass 28, count 0 2006.257.12:29:16.82#ibcon#read 3, iclass 28, count 0 2006.257.12:29:16.82#ibcon#about to read 4, iclass 28, count 0 2006.257.12:29:16.82#ibcon#read 4, iclass 28, count 0 2006.257.12:29:16.82#ibcon#about to read 5, iclass 28, count 0 2006.257.12:29:16.82#ibcon#read 5, iclass 28, count 0 2006.257.12:29:16.82#ibcon#about to read 6, iclass 28, count 0 2006.257.12:29:16.82#ibcon#read 6, iclass 28, count 0 2006.257.12:29:16.82#ibcon#end of sib2, iclass 28, count 0 2006.257.12:29:16.82#ibcon#*after write, iclass 28, count 0 2006.257.12:29:16.82#ibcon#*before return 0, iclass 28, count 0 2006.257.12:29:16.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:29:16.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:29:16.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:29:16.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:29:16.82$vck44/vblo=1,629.99 2006.257.12:29:16.82#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.12:29:16.82#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.12:29:16.82#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:16.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:29:16.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:29:16.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:29:16.82#ibcon#enter wrdev, iclass 30, count 0 2006.257.12:29:16.82#ibcon#first serial, iclass 30, count 0 2006.257.12:29:16.82#ibcon#enter sib2, iclass 30, count 0 2006.257.12:29:16.82#ibcon#flushed, iclass 30, count 0 2006.257.12:29:16.82#ibcon#about to write, iclass 30, count 0 2006.257.12:29:16.82#ibcon#wrote, iclass 30, count 0 2006.257.12:29:16.82#ibcon#about to read 3, iclass 30, count 0 2006.257.12:29:16.84#ibcon#read 3, iclass 30, count 0 2006.257.12:29:16.84#ibcon#about to read 4, iclass 30, count 0 2006.257.12:29:16.84#ibcon#read 4, iclass 30, count 0 2006.257.12:29:16.84#ibcon#about to read 5, iclass 30, count 0 2006.257.12:29:16.84#ibcon#read 5, iclass 30, count 0 2006.257.12:29:16.84#ibcon#about to read 6, iclass 30, count 0 2006.257.12:29:16.84#ibcon#read 6, iclass 30, count 0 2006.257.12:29:16.84#ibcon#end of sib2, iclass 30, count 0 2006.257.12:29:16.84#ibcon#*mode == 0, iclass 30, count 0 2006.257.12:29:16.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.12:29:16.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:29:16.84#ibcon#*before write, iclass 30, count 0 2006.257.12:29:16.84#ibcon#enter sib2, iclass 30, count 0 2006.257.12:29:16.84#ibcon#flushed, iclass 30, count 0 2006.257.12:29:16.84#ibcon#about to write, iclass 30, count 0 2006.257.12:29:16.84#ibcon#wrote, iclass 30, count 0 2006.257.12:29:16.84#ibcon#about to read 3, iclass 30, count 0 2006.257.12:29:16.88#ibcon#read 3, iclass 30, count 0 2006.257.12:29:16.88#ibcon#about to read 4, iclass 30, count 0 2006.257.12:29:16.88#ibcon#read 4, iclass 30, count 0 2006.257.12:29:16.88#ibcon#about to read 5, iclass 30, count 0 2006.257.12:29:16.88#ibcon#read 5, iclass 30, count 0 2006.257.12:29:16.88#ibcon#about to read 6, iclass 30, count 0 2006.257.12:29:16.88#ibcon#read 6, iclass 30, count 0 2006.257.12:29:16.88#ibcon#end of sib2, iclass 30, count 0 2006.257.12:29:16.88#ibcon#*after write, iclass 30, count 0 2006.257.12:29:16.88#ibcon#*before return 0, iclass 30, count 0 2006.257.12:29:16.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:29:16.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:29:16.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.12:29:16.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.12:29:16.88$vck44/vb=1,4 2006.257.12:29:16.88#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.12:29:16.88#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.12:29:16.88#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:16.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:29:16.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:29:16.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:29:16.88#ibcon#enter wrdev, iclass 32, count 2 2006.257.12:29:16.88#ibcon#first serial, iclass 32, count 2 2006.257.12:29:16.88#ibcon#enter sib2, iclass 32, count 2 2006.257.12:29:16.88#ibcon#flushed, iclass 32, count 2 2006.257.12:29:16.88#ibcon#about to write, iclass 32, count 2 2006.257.12:29:16.88#ibcon#wrote, iclass 32, count 2 2006.257.12:29:16.88#ibcon#about to read 3, iclass 32, count 2 2006.257.12:29:16.90#ibcon#read 3, iclass 32, count 2 2006.257.12:29:16.90#ibcon#about to read 4, iclass 32, count 2 2006.257.12:29:16.90#ibcon#read 4, iclass 32, count 2 2006.257.12:29:16.90#ibcon#about to read 5, iclass 32, count 2 2006.257.12:29:16.90#ibcon#read 5, iclass 32, count 2 2006.257.12:29:16.90#ibcon#about to read 6, iclass 32, count 2 2006.257.12:29:16.90#ibcon#read 6, iclass 32, count 2 2006.257.12:29:16.90#ibcon#end of sib2, iclass 32, count 2 2006.257.12:29:16.90#ibcon#*mode == 0, iclass 32, count 2 2006.257.12:29:16.90#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.12:29:16.90#ibcon#[27=AT01-04\r\n] 2006.257.12:29:16.90#ibcon#*before write, iclass 32, count 2 2006.257.12:29:16.90#ibcon#enter sib2, iclass 32, count 2 2006.257.12:29:16.90#ibcon#flushed, iclass 32, count 2 2006.257.12:29:16.90#ibcon#about to write, iclass 32, count 2 2006.257.12:29:16.90#ibcon#wrote, iclass 32, count 2 2006.257.12:29:16.90#ibcon#about to read 3, iclass 32, count 2 2006.257.12:29:16.93#ibcon#read 3, iclass 32, count 2 2006.257.12:29:16.93#ibcon#about to read 4, iclass 32, count 2 2006.257.12:29:16.93#ibcon#read 4, iclass 32, count 2 2006.257.12:29:16.93#ibcon#about to read 5, iclass 32, count 2 2006.257.12:29:16.93#ibcon#read 5, iclass 32, count 2 2006.257.12:29:16.93#ibcon#about to read 6, iclass 32, count 2 2006.257.12:29:16.93#ibcon#read 6, iclass 32, count 2 2006.257.12:29:16.93#ibcon#end of sib2, iclass 32, count 2 2006.257.12:29:16.93#ibcon#*after write, iclass 32, count 2 2006.257.12:29:16.93#ibcon#*before return 0, iclass 32, count 2 2006.257.12:29:16.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:29:16.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:29:16.93#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.12:29:16.93#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:16.93#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:29:17.05#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:29:17.05#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:29:17.05#ibcon#enter wrdev, iclass 32, count 0 2006.257.12:29:17.05#ibcon#first serial, iclass 32, count 0 2006.257.12:29:17.05#ibcon#enter sib2, iclass 32, count 0 2006.257.12:29:17.05#ibcon#flushed, iclass 32, count 0 2006.257.12:29:17.05#ibcon#about to write, iclass 32, count 0 2006.257.12:29:17.05#ibcon#wrote, iclass 32, count 0 2006.257.12:29:17.05#ibcon#about to read 3, iclass 32, count 0 2006.257.12:29:17.07#ibcon#read 3, iclass 32, count 0 2006.257.12:29:17.07#ibcon#about to read 4, iclass 32, count 0 2006.257.12:29:17.07#ibcon#read 4, iclass 32, count 0 2006.257.12:29:17.07#ibcon#about to read 5, iclass 32, count 0 2006.257.12:29:17.07#ibcon#read 5, iclass 32, count 0 2006.257.12:29:17.07#ibcon#about to read 6, iclass 32, count 0 2006.257.12:29:17.07#ibcon#read 6, iclass 32, count 0 2006.257.12:29:17.07#ibcon#end of sib2, iclass 32, count 0 2006.257.12:29:17.07#ibcon#*mode == 0, iclass 32, count 0 2006.257.12:29:17.07#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.12:29:17.07#ibcon#[27=USB\r\n] 2006.257.12:29:17.07#ibcon#*before write, iclass 32, count 0 2006.257.12:29:17.07#ibcon#enter sib2, iclass 32, count 0 2006.257.12:29:17.07#ibcon#flushed, iclass 32, count 0 2006.257.12:29:17.07#ibcon#about to write, iclass 32, count 0 2006.257.12:29:17.07#ibcon#wrote, iclass 32, count 0 2006.257.12:29:17.07#ibcon#about to read 3, iclass 32, count 0 2006.257.12:29:17.10#ibcon#read 3, iclass 32, count 0 2006.257.12:29:17.10#ibcon#about to read 4, iclass 32, count 0 2006.257.12:29:17.10#ibcon#read 4, iclass 32, count 0 2006.257.12:29:17.10#ibcon#about to read 5, iclass 32, count 0 2006.257.12:29:17.10#ibcon#read 5, iclass 32, count 0 2006.257.12:29:17.10#ibcon#about to read 6, iclass 32, count 0 2006.257.12:29:17.10#ibcon#read 6, iclass 32, count 0 2006.257.12:29:17.10#ibcon#end of sib2, iclass 32, count 0 2006.257.12:29:17.10#ibcon#*after write, iclass 32, count 0 2006.257.12:29:17.10#ibcon#*before return 0, iclass 32, count 0 2006.257.12:29:17.10#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:29:17.10#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:29:17.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.12:29:17.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.12:29:17.10$vck44/vblo=2,634.99 2006.257.12:29:17.10#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.12:29:17.10#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.12:29:17.10#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:17.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:17.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:17.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:17.10#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:29:17.10#ibcon#first serial, iclass 34, count 0 2006.257.12:29:17.10#ibcon#enter sib2, iclass 34, count 0 2006.257.12:29:17.10#ibcon#flushed, iclass 34, count 0 2006.257.12:29:17.10#ibcon#about to write, iclass 34, count 0 2006.257.12:29:17.10#ibcon#wrote, iclass 34, count 0 2006.257.12:29:17.10#ibcon#about to read 3, iclass 34, count 0 2006.257.12:29:17.12#ibcon#read 3, iclass 34, count 0 2006.257.12:29:17.12#ibcon#about to read 4, iclass 34, count 0 2006.257.12:29:17.12#ibcon#read 4, iclass 34, count 0 2006.257.12:29:17.12#ibcon#about to read 5, iclass 34, count 0 2006.257.12:29:17.12#ibcon#read 5, iclass 34, count 0 2006.257.12:29:17.12#ibcon#about to read 6, iclass 34, count 0 2006.257.12:29:17.12#ibcon#read 6, iclass 34, count 0 2006.257.12:29:17.12#ibcon#end of sib2, iclass 34, count 0 2006.257.12:29:17.12#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:29:17.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:29:17.12#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:29:17.12#ibcon#*before write, iclass 34, count 0 2006.257.12:29:17.12#ibcon#enter sib2, iclass 34, count 0 2006.257.12:29:17.12#ibcon#flushed, iclass 34, count 0 2006.257.12:29:17.12#ibcon#about to write, iclass 34, count 0 2006.257.12:29:17.12#ibcon#wrote, iclass 34, count 0 2006.257.12:29:17.12#ibcon#about to read 3, iclass 34, count 0 2006.257.12:29:17.16#ibcon#read 3, iclass 34, count 0 2006.257.12:29:17.16#ibcon#about to read 4, iclass 34, count 0 2006.257.12:29:17.16#ibcon#read 4, iclass 34, count 0 2006.257.12:29:17.16#ibcon#about to read 5, iclass 34, count 0 2006.257.12:29:17.16#ibcon#read 5, iclass 34, count 0 2006.257.12:29:17.16#ibcon#about to read 6, iclass 34, count 0 2006.257.12:29:17.16#ibcon#read 6, iclass 34, count 0 2006.257.12:29:17.16#ibcon#end of sib2, iclass 34, count 0 2006.257.12:29:17.16#ibcon#*after write, iclass 34, count 0 2006.257.12:29:17.16#ibcon#*before return 0, iclass 34, count 0 2006.257.12:29:17.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:17.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:29:17.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:29:17.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:29:17.16$vck44/vb=2,5 2006.257.12:29:17.16#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.12:29:17.16#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.12:29:17.16#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:17.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:17.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:17.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:17.22#ibcon#enter wrdev, iclass 36, count 2 2006.257.12:29:17.22#ibcon#first serial, iclass 36, count 2 2006.257.12:29:17.22#ibcon#enter sib2, iclass 36, count 2 2006.257.12:29:17.22#ibcon#flushed, iclass 36, count 2 2006.257.12:29:17.22#ibcon#about to write, iclass 36, count 2 2006.257.12:29:17.22#ibcon#wrote, iclass 36, count 2 2006.257.12:29:17.22#ibcon#about to read 3, iclass 36, count 2 2006.257.12:29:17.24#ibcon#read 3, iclass 36, count 2 2006.257.12:29:17.24#ibcon#about to read 4, iclass 36, count 2 2006.257.12:29:17.24#ibcon#read 4, iclass 36, count 2 2006.257.12:29:17.24#ibcon#about to read 5, iclass 36, count 2 2006.257.12:29:17.24#ibcon#read 5, iclass 36, count 2 2006.257.12:29:17.24#ibcon#about to read 6, iclass 36, count 2 2006.257.12:29:17.24#ibcon#read 6, iclass 36, count 2 2006.257.12:29:17.24#ibcon#end of sib2, iclass 36, count 2 2006.257.12:29:17.24#ibcon#*mode == 0, iclass 36, count 2 2006.257.12:29:17.24#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.12:29:17.24#ibcon#[27=AT02-05\r\n] 2006.257.12:29:17.24#ibcon#*before write, iclass 36, count 2 2006.257.12:29:17.24#ibcon#enter sib2, iclass 36, count 2 2006.257.12:29:17.24#ibcon#flushed, iclass 36, count 2 2006.257.12:29:17.24#ibcon#about to write, iclass 36, count 2 2006.257.12:29:17.24#ibcon#wrote, iclass 36, count 2 2006.257.12:29:17.24#ibcon#about to read 3, iclass 36, count 2 2006.257.12:29:17.27#ibcon#read 3, iclass 36, count 2 2006.257.12:29:17.27#ibcon#about to read 4, iclass 36, count 2 2006.257.12:29:17.27#ibcon#read 4, iclass 36, count 2 2006.257.12:29:17.27#ibcon#about to read 5, iclass 36, count 2 2006.257.12:29:17.27#ibcon#read 5, iclass 36, count 2 2006.257.12:29:17.27#ibcon#about to read 6, iclass 36, count 2 2006.257.12:29:17.27#ibcon#read 6, iclass 36, count 2 2006.257.12:29:17.27#ibcon#end of sib2, iclass 36, count 2 2006.257.12:29:17.27#ibcon#*after write, iclass 36, count 2 2006.257.12:29:17.27#ibcon#*before return 0, iclass 36, count 2 2006.257.12:29:17.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:17.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:29:17.27#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.12:29:17.27#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:17.27#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:17.39#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:17.39#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:17.39#ibcon#enter wrdev, iclass 36, count 0 2006.257.12:29:17.39#ibcon#first serial, iclass 36, count 0 2006.257.12:29:17.39#ibcon#enter sib2, iclass 36, count 0 2006.257.12:29:17.39#ibcon#flushed, iclass 36, count 0 2006.257.12:29:17.39#ibcon#about to write, iclass 36, count 0 2006.257.12:29:17.39#ibcon#wrote, iclass 36, count 0 2006.257.12:29:17.39#ibcon#about to read 3, iclass 36, count 0 2006.257.12:29:17.41#ibcon#read 3, iclass 36, count 0 2006.257.12:29:17.41#ibcon#about to read 4, iclass 36, count 0 2006.257.12:29:17.41#ibcon#read 4, iclass 36, count 0 2006.257.12:29:17.41#ibcon#about to read 5, iclass 36, count 0 2006.257.12:29:17.41#ibcon#read 5, iclass 36, count 0 2006.257.12:29:17.41#ibcon#about to read 6, iclass 36, count 0 2006.257.12:29:17.41#ibcon#read 6, iclass 36, count 0 2006.257.12:29:17.41#ibcon#end of sib2, iclass 36, count 0 2006.257.12:29:17.41#ibcon#*mode == 0, iclass 36, count 0 2006.257.12:29:17.41#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.12:29:17.41#ibcon#[27=USB\r\n] 2006.257.12:29:17.41#ibcon#*before write, iclass 36, count 0 2006.257.12:29:17.41#ibcon#enter sib2, iclass 36, count 0 2006.257.12:29:17.41#ibcon#flushed, iclass 36, count 0 2006.257.12:29:17.41#ibcon#about to write, iclass 36, count 0 2006.257.12:29:17.41#ibcon#wrote, iclass 36, count 0 2006.257.12:29:17.41#ibcon#about to read 3, iclass 36, count 0 2006.257.12:29:17.44#ibcon#read 3, iclass 36, count 0 2006.257.12:29:17.44#ibcon#about to read 4, iclass 36, count 0 2006.257.12:29:17.44#ibcon#read 4, iclass 36, count 0 2006.257.12:29:17.44#ibcon#about to read 5, iclass 36, count 0 2006.257.12:29:17.44#ibcon#read 5, iclass 36, count 0 2006.257.12:29:17.44#ibcon#about to read 6, iclass 36, count 0 2006.257.12:29:17.44#ibcon#read 6, iclass 36, count 0 2006.257.12:29:17.44#ibcon#end of sib2, iclass 36, count 0 2006.257.12:29:17.44#ibcon#*after write, iclass 36, count 0 2006.257.12:29:17.44#ibcon#*before return 0, iclass 36, count 0 2006.257.12:29:17.44#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:17.44#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:29:17.44#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.12:29:17.44#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.12:29:17.44$vck44/vblo=3,649.99 2006.257.12:29:17.44#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.12:29:17.44#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.12:29:17.44#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:17.44#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:17.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:17.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:17.44#ibcon#enter wrdev, iclass 38, count 0 2006.257.12:29:17.44#ibcon#first serial, iclass 38, count 0 2006.257.12:29:17.44#ibcon#enter sib2, iclass 38, count 0 2006.257.12:29:17.44#ibcon#flushed, iclass 38, count 0 2006.257.12:29:17.44#ibcon#about to write, iclass 38, count 0 2006.257.12:29:17.44#ibcon#wrote, iclass 38, count 0 2006.257.12:29:17.44#ibcon#about to read 3, iclass 38, count 0 2006.257.12:29:17.46#ibcon#read 3, iclass 38, count 0 2006.257.12:29:17.46#ibcon#about to read 4, iclass 38, count 0 2006.257.12:29:17.46#ibcon#read 4, iclass 38, count 0 2006.257.12:29:17.46#ibcon#about to read 5, iclass 38, count 0 2006.257.12:29:17.46#ibcon#read 5, iclass 38, count 0 2006.257.12:29:17.46#ibcon#about to read 6, iclass 38, count 0 2006.257.12:29:17.46#ibcon#read 6, iclass 38, count 0 2006.257.12:29:17.46#ibcon#end of sib2, iclass 38, count 0 2006.257.12:29:17.46#ibcon#*mode == 0, iclass 38, count 0 2006.257.12:29:17.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.12:29:17.46#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:29:17.46#ibcon#*before write, iclass 38, count 0 2006.257.12:29:17.46#ibcon#enter sib2, iclass 38, count 0 2006.257.12:29:17.46#ibcon#flushed, iclass 38, count 0 2006.257.12:29:17.46#ibcon#about to write, iclass 38, count 0 2006.257.12:29:17.46#ibcon#wrote, iclass 38, count 0 2006.257.12:29:17.46#ibcon#about to read 3, iclass 38, count 0 2006.257.12:29:17.50#ibcon#read 3, iclass 38, count 0 2006.257.12:29:17.50#ibcon#about to read 4, iclass 38, count 0 2006.257.12:29:17.50#ibcon#read 4, iclass 38, count 0 2006.257.12:29:17.50#ibcon#about to read 5, iclass 38, count 0 2006.257.12:29:17.50#ibcon#read 5, iclass 38, count 0 2006.257.12:29:17.50#ibcon#about to read 6, iclass 38, count 0 2006.257.12:29:17.50#ibcon#read 6, iclass 38, count 0 2006.257.12:29:17.50#ibcon#end of sib2, iclass 38, count 0 2006.257.12:29:17.50#ibcon#*after write, iclass 38, count 0 2006.257.12:29:17.50#ibcon#*before return 0, iclass 38, count 0 2006.257.12:29:17.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:17.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:29:17.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.12:29:17.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.12:29:17.50$vck44/vb=3,4 2006.257.12:29:17.50#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.12:29:17.50#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.12:29:17.50#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:17.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:17.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:17.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:17.56#ibcon#enter wrdev, iclass 40, count 2 2006.257.12:29:17.56#ibcon#first serial, iclass 40, count 2 2006.257.12:29:17.56#ibcon#enter sib2, iclass 40, count 2 2006.257.12:29:17.56#ibcon#flushed, iclass 40, count 2 2006.257.12:29:17.56#ibcon#about to write, iclass 40, count 2 2006.257.12:29:17.56#ibcon#wrote, iclass 40, count 2 2006.257.12:29:17.56#ibcon#about to read 3, iclass 40, count 2 2006.257.12:29:17.58#ibcon#read 3, iclass 40, count 2 2006.257.12:29:17.58#ibcon#about to read 4, iclass 40, count 2 2006.257.12:29:17.58#ibcon#read 4, iclass 40, count 2 2006.257.12:29:17.58#ibcon#about to read 5, iclass 40, count 2 2006.257.12:29:17.58#ibcon#read 5, iclass 40, count 2 2006.257.12:29:17.58#ibcon#about to read 6, iclass 40, count 2 2006.257.12:29:17.58#ibcon#read 6, iclass 40, count 2 2006.257.12:29:17.58#ibcon#end of sib2, iclass 40, count 2 2006.257.12:29:17.58#ibcon#*mode == 0, iclass 40, count 2 2006.257.12:29:17.58#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.12:29:17.58#ibcon#[27=AT03-04\r\n] 2006.257.12:29:17.58#ibcon#*before write, iclass 40, count 2 2006.257.12:29:17.58#ibcon#enter sib2, iclass 40, count 2 2006.257.12:29:17.58#ibcon#flushed, iclass 40, count 2 2006.257.12:29:17.58#ibcon#about to write, iclass 40, count 2 2006.257.12:29:17.58#ibcon#wrote, iclass 40, count 2 2006.257.12:29:17.58#ibcon#about to read 3, iclass 40, count 2 2006.257.12:29:17.61#ibcon#read 3, iclass 40, count 2 2006.257.12:29:17.61#ibcon#about to read 4, iclass 40, count 2 2006.257.12:29:17.61#ibcon#read 4, iclass 40, count 2 2006.257.12:29:17.61#ibcon#about to read 5, iclass 40, count 2 2006.257.12:29:17.61#ibcon#read 5, iclass 40, count 2 2006.257.12:29:17.61#ibcon#about to read 6, iclass 40, count 2 2006.257.12:29:17.61#ibcon#read 6, iclass 40, count 2 2006.257.12:29:17.61#ibcon#end of sib2, iclass 40, count 2 2006.257.12:29:17.61#ibcon#*after write, iclass 40, count 2 2006.257.12:29:17.61#ibcon#*before return 0, iclass 40, count 2 2006.257.12:29:17.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:17.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:29:17.61#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.12:29:17.61#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:17.61#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:17.73#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:17.73#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:17.73#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:29:17.73#ibcon#first serial, iclass 40, count 0 2006.257.12:29:17.73#ibcon#enter sib2, iclass 40, count 0 2006.257.12:29:17.73#ibcon#flushed, iclass 40, count 0 2006.257.12:29:17.73#ibcon#about to write, iclass 40, count 0 2006.257.12:29:17.73#ibcon#wrote, iclass 40, count 0 2006.257.12:29:17.73#ibcon#about to read 3, iclass 40, count 0 2006.257.12:29:17.75#ibcon#read 3, iclass 40, count 0 2006.257.12:29:17.75#ibcon#about to read 4, iclass 40, count 0 2006.257.12:29:17.75#ibcon#read 4, iclass 40, count 0 2006.257.12:29:17.75#ibcon#about to read 5, iclass 40, count 0 2006.257.12:29:17.75#ibcon#read 5, iclass 40, count 0 2006.257.12:29:17.75#ibcon#about to read 6, iclass 40, count 0 2006.257.12:29:17.75#ibcon#read 6, iclass 40, count 0 2006.257.12:29:17.75#ibcon#end of sib2, iclass 40, count 0 2006.257.12:29:17.75#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:29:17.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:29:17.75#ibcon#[27=USB\r\n] 2006.257.12:29:17.75#ibcon#*before write, iclass 40, count 0 2006.257.12:29:17.75#ibcon#enter sib2, iclass 40, count 0 2006.257.12:29:17.75#ibcon#flushed, iclass 40, count 0 2006.257.12:29:17.75#ibcon#about to write, iclass 40, count 0 2006.257.12:29:17.75#ibcon#wrote, iclass 40, count 0 2006.257.12:29:17.75#ibcon#about to read 3, iclass 40, count 0 2006.257.12:29:17.78#ibcon#read 3, iclass 40, count 0 2006.257.12:29:17.78#ibcon#about to read 4, iclass 40, count 0 2006.257.12:29:17.78#ibcon#read 4, iclass 40, count 0 2006.257.12:29:17.78#ibcon#about to read 5, iclass 40, count 0 2006.257.12:29:17.78#ibcon#read 5, iclass 40, count 0 2006.257.12:29:17.78#ibcon#about to read 6, iclass 40, count 0 2006.257.12:29:17.78#ibcon#read 6, iclass 40, count 0 2006.257.12:29:17.78#ibcon#end of sib2, iclass 40, count 0 2006.257.12:29:17.78#ibcon#*after write, iclass 40, count 0 2006.257.12:29:17.78#ibcon#*before return 0, iclass 40, count 0 2006.257.12:29:17.78#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:17.78#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:29:17.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:29:17.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:29:17.78$vck44/vblo=4,679.99 2006.257.12:29:17.78#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.12:29:17.78#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.12:29:17.78#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:17.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:17.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:17.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:17.78#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:29:17.78#ibcon#first serial, iclass 4, count 0 2006.257.12:29:17.78#ibcon#enter sib2, iclass 4, count 0 2006.257.12:29:17.78#ibcon#flushed, iclass 4, count 0 2006.257.12:29:17.78#ibcon#about to write, iclass 4, count 0 2006.257.12:29:17.78#ibcon#wrote, iclass 4, count 0 2006.257.12:29:17.78#ibcon#about to read 3, iclass 4, count 0 2006.257.12:29:17.80#ibcon#read 3, iclass 4, count 0 2006.257.12:29:17.80#ibcon#about to read 4, iclass 4, count 0 2006.257.12:29:17.80#ibcon#read 4, iclass 4, count 0 2006.257.12:29:17.80#ibcon#about to read 5, iclass 4, count 0 2006.257.12:29:17.80#ibcon#read 5, iclass 4, count 0 2006.257.12:29:17.80#ibcon#about to read 6, iclass 4, count 0 2006.257.12:29:17.80#ibcon#read 6, iclass 4, count 0 2006.257.12:29:17.80#ibcon#end of sib2, iclass 4, count 0 2006.257.12:29:17.80#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:29:17.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:29:17.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:29:17.80#ibcon#*before write, iclass 4, count 0 2006.257.12:29:17.80#ibcon#enter sib2, iclass 4, count 0 2006.257.12:29:17.80#ibcon#flushed, iclass 4, count 0 2006.257.12:29:17.80#ibcon#about to write, iclass 4, count 0 2006.257.12:29:17.80#ibcon#wrote, iclass 4, count 0 2006.257.12:29:17.80#ibcon#about to read 3, iclass 4, count 0 2006.257.12:29:17.84#ibcon#read 3, iclass 4, count 0 2006.257.12:29:17.84#ibcon#about to read 4, iclass 4, count 0 2006.257.12:29:17.84#ibcon#read 4, iclass 4, count 0 2006.257.12:29:17.84#ibcon#about to read 5, iclass 4, count 0 2006.257.12:29:17.84#ibcon#read 5, iclass 4, count 0 2006.257.12:29:17.84#ibcon#about to read 6, iclass 4, count 0 2006.257.12:29:17.84#ibcon#read 6, iclass 4, count 0 2006.257.12:29:17.84#ibcon#end of sib2, iclass 4, count 0 2006.257.12:29:17.84#ibcon#*after write, iclass 4, count 0 2006.257.12:29:17.84#ibcon#*before return 0, iclass 4, count 0 2006.257.12:29:17.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:17.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:29:17.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:29:17.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:29:17.84$vck44/vb=4,5 2006.257.12:29:17.84#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.12:29:17.84#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.12:29:17.84#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:17.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:17.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:17.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:17.90#ibcon#enter wrdev, iclass 6, count 2 2006.257.12:29:17.90#ibcon#first serial, iclass 6, count 2 2006.257.12:29:17.90#ibcon#enter sib2, iclass 6, count 2 2006.257.12:29:17.90#ibcon#flushed, iclass 6, count 2 2006.257.12:29:17.90#ibcon#about to write, iclass 6, count 2 2006.257.12:29:17.90#ibcon#wrote, iclass 6, count 2 2006.257.12:29:17.90#ibcon#about to read 3, iclass 6, count 2 2006.257.12:29:17.92#ibcon#read 3, iclass 6, count 2 2006.257.12:29:17.92#ibcon#about to read 4, iclass 6, count 2 2006.257.12:29:17.92#ibcon#read 4, iclass 6, count 2 2006.257.12:29:17.92#ibcon#about to read 5, iclass 6, count 2 2006.257.12:29:17.92#ibcon#read 5, iclass 6, count 2 2006.257.12:29:17.92#ibcon#about to read 6, iclass 6, count 2 2006.257.12:29:17.92#ibcon#read 6, iclass 6, count 2 2006.257.12:29:17.92#ibcon#end of sib2, iclass 6, count 2 2006.257.12:29:17.92#ibcon#*mode == 0, iclass 6, count 2 2006.257.12:29:17.92#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.12:29:17.92#ibcon#[27=AT04-05\r\n] 2006.257.12:29:17.92#ibcon#*before write, iclass 6, count 2 2006.257.12:29:17.92#ibcon#enter sib2, iclass 6, count 2 2006.257.12:29:17.92#ibcon#flushed, iclass 6, count 2 2006.257.12:29:17.92#ibcon#about to write, iclass 6, count 2 2006.257.12:29:17.92#ibcon#wrote, iclass 6, count 2 2006.257.12:29:17.92#ibcon#about to read 3, iclass 6, count 2 2006.257.12:29:17.95#ibcon#read 3, iclass 6, count 2 2006.257.12:29:17.95#ibcon#about to read 4, iclass 6, count 2 2006.257.12:29:17.95#ibcon#read 4, iclass 6, count 2 2006.257.12:29:17.95#ibcon#about to read 5, iclass 6, count 2 2006.257.12:29:17.95#ibcon#read 5, iclass 6, count 2 2006.257.12:29:17.95#ibcon#about to read 6, iclass 6, count 2 2006.257.12:29:17.95#ibcon#read 6, iclass 6, count 2 2006.257.12:29:17.95#ibcon#end of sib2, iclass 6, count 2 2006.257.12:29:17.95#ibcon#*after write, iclass 6, count 2 2006.257.12:29:17.95#ibcon#*before return 0, iclass 6, count 2 2006.257.12:29:17.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:17.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:29:17.95#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.12:29:17.95#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:17.95#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:18.07#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:18.07#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:18.07#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:29:18.07#ibcon#first serial, iclass 6, count 0 2006.257.12:29:18.07#ibcon#enter sib2, iclass 6, count 0 2006.257.12:29:18.07#ibcon#flushed, iclass 6, count 0 2006.257.12:29:18.07#ibcon#about to write, iclass 6, count 0 2006.257.12:29:18.07#ibcon#wrote, iclass 6, count 0 2006.257.12:29:18.07#ibcon#about to read 3, iclass 6, count 0 2006.257.12:29:18.09#ibcon#read 3, iclass 6, count 0 2006.257.12:29:18.09#ibcon#about to read 4, iclass 6, count 0 2006.257.12:29:18.09#ibcon#read 4, iclass 6, count 0 2006.257.12:29:18.09#ibcon#about to read 5, iclass 6, count 0 2006.257.12:29:18.09#ibcon#read 5, iclass 6, count 0 2006.257.12:29:18.09#ibcon#about to read 6, iclass 6, count 0 2006.257.12:29:18.09#ibcon#read 6, iclass 6, count 0 2006.257.12:29:18.09#ibcon#end of sib2, iclass 6, count 0 2006.257.12:29:18.09#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:29:18.09#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:29:18.09#ibcon#[27=USB\r\n] 2006.257.12:29:18.09#ibcon#*before write, iclass 6, count 0 2006.257.12:29:18.09#ibcon#enter sib2, iclass 6, count 0 2006.257.12:29:18.09#ibcon#flushed, iclass 6, count 0 2006.257.12:29:18.09#ibcon#about to write, iclass 6, count 0 2006.257.12:29:18.09#ibcon#wrote, iclass 6, count 0 2006.257.12:29:18.09#ibcon#about to read 3, iclass 6, count 0 2006.257.12:29:18.12#ibcon#read 3, iclass 6, count 0 2006.257.12:29:18.12#ibcon#about to read 4, iclass 6, count 0 2006.257.12:29:18.12#ibcon#read 4, iclass 6, count 0 2006.257.12:29:18.12#ibcon#about to read 5, iclass 6, count 0 2006.257.12:29:18.12#ibcon#read 5, iclass 6, count 0 2006.257.12:29:18.12#ibcon#about to read 6, iclass 6, count 0 2006.257.12:29:18.12#ibcon#read 6, iclass 6, count 0 2006.257.12:29:18.12#ibcon#end of sib2, iclass 6, count 0 2006.257.12:29:18.12#ibcon#*after write, iclass 6, count 0 2006.257.12:29:18.12#ibcon#*before return 0, iclass 6, count 0 2006.257.12:29:18.12#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:18.12#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:29:18.12#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:29:18.12#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:29:18.12$vck44/vblo=5,709.99 2006.257.12:29:18.12#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.12:29:18.12#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.12:29:18.12#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:18.12#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:18.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:18.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:18.12#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:29:18.12#ibcon#first serial, iclass 10, count 0 2006.257.12:29:18.12#ibcon#enter sib2, iclass 10, count 0 2006.257.12:29:18.12#ibcon#flushed, iclass 10, count 0 2006.257.12:29:18.12#ibcon#about to write, iclass 10, count 0 2006.257.12:29:18.12#ibcon#wrote, iclass 10, count 0 2006.257.12:29:18.12#ibcon#about to read 3, iclass 10, count 0 2006.257.12:29:18.14#ibcon#read 3, iclass 10, count 0 2006.257.12:29:18.14#ibcon#about to read 4, iclass 10, count 0 2006.257.12:29:18.14#ibcon#read 4, iclass 10, count 0 2006.257.12:29:18.14#ibcon#about to read 5, iclass 10, count 0 2006.257.12:29:18.14#ibcon#read 5, iclass 10, count 0 2006.257.12:29:18.14#ibcon#about to read 6, iclass 10, count 0 2006.257.12:29:18.14#ibcon#read 6, iclass 10, count 0 2006.257.12:29:18.14#ibcon#end of sib2, iclass 10, count 0 2006.257.12:29:18.14#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:29:18.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:29:18.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:29:18.14#ibcon#*before write, iclass 10, count 0 2006.257.12:29:18.14#ibcon#enter sib2, iclass 10, count 0 2006.257.12:29:18.14#ibcon#flushed, iclass 10, count 0 2006.257.12:29:18.14#ibcon#about to write, iclass 10, count 0 2006.257.12:29:18.14#ibcon#wrote, iclass 10, count 0 2006.257.12:29:18.14#ibcon#about to read 3, iclass 10, count 0 2006.257.12:29:18.18#ibcon#read 3, iclass 10, count 0 2006.257.12:29:18.18#ibcon#about to read 4, iclass 10, count 0 2006.257.12:29:18.18#ibcon#read 4, iclass 10, count 0 2006.257.12:29:18.18#ibcon#about to read 5, iclass 10, count 0 2006.257.12:29:18.18#ibcon#read 5, iclass 10, count 0 2006.257.12:29:18.18#ibcon#about to read 6, iclass 10, count 0 2006.257.12:29:18.18#ibcon#read 6, iclass 10, count 0 2006.257.12:29:18.18#ibcon#end of sib2, iclass 10, count 0 2006.257.12:29:18.18#ibcon#*after write, iclass 10, count 0 2006.257.12:29:18.18#ibcon#*before return 0, iclass 10, count 0 2006.257.12:29:18.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:18.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:29:18.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:29:18.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:29:18.18$vck44/vb=5,4 2006.257.12:29:18.18#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.12:29:18.18#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.12:29:18.18#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:18.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:18.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:18.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:18.24#ibcon#enter wrdev, iclass 12, count 2 2006.257.12:29:18.24#ibcon#first serial, iclass 12, count 2 2006.257.12:29:18.24#ibcon#enter sib2, iclass 12, count 2 2006.257.12:29:18.24#ibcon#flushed, iclass 12, count 2 2006.257.12:29:18.24#ibcon#about to write, iclass 12, count 2 2006.257.12:29:18.24#ibcon#wrote, iclass 12, count 2 2006.257.12:29:18.24#ibcon#about to read 3, iclass 12, count 2 2006.257.12:29:18.26#ibcon#read 3, iclass 12, count 2 2006.257.12:29:18.26#ibcon#about to read 4, iclass 12, count 2 2006.257.12:29:18.26#ibcon#read 4, iclass 12, count 2 2006.257.12:29:18.26#ibcon#about to read 5, iclass 12, count 2 2006.257.12:29:18.26#ibcon#read 5, iclass 12, count 2 2006.257.12:29:18.26#ibcon#about to read 6, iclass 12, count 2 2006.257.12:29:18.26#ibcon#read 6, iclass 12, count 2 2006.257.12:29:18.26#ibcon#end of sib2, iclass 12, count 2 2006.257.12:29:18.26#ibcon#*mode == 0, iclass 12, count 2 2006.257.12:29:18.26#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.12:29:18.26#ibcon#[27=AT05-04\r\n] 2006.257.12:29:18.26#ibcon#*before write, iclass 12, count 2 2006.257.12:29:18.26#ibcon#enter sib2, iclass 12, count 2 2006.257.12:29:18.26#ibcon#flushed, iclass 12, count 2 2006.257.12:29:18.26#ibcon#about to write, iclass 12, count 2 2006.257.12:29:18.26#ibcon#wrote, iclass 12, count 2 2006.257.12:29:18.26#ibcon#about to read 3, iclass 12, count 2 2006.257.12:29:18.29#ibcon#read 3, iclass 12, count 2 2006.257.12:29:18.29#ibcon#about to read 4, iclass 12, count 2 2006.257.12:29:18.29#ibcon#read 4, iclass 12, count 2 2006.257.12:29:18.29#ibcon#about to read 5, iclass 12, count 2 2006.257.12:29:18.29#ibcon#read 5, iclass 12, count 2 2006.257.12:29:18.29#ibcon#about to read 6, iclass 12, count 2 2006.257.12:29:18.29#ibcon#read 6, iclass 12, count 2 2006.257.12:29:18.29#ibcon#end of sib2, iclass 12, count 2 2006.257.12:29:18.29#ibcon#*after write, iclass 12, count 2 2006.257.12:29:18.29#ibcon#*before return 0, iclass 12, count 2 2006.257.12:29:18.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:18.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:29:18.29#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.12:29:18.29#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:18.29#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:18.41#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:18.41#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:18.41#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:29:18.41#ibcon#first serial, iclass 12, count 0 2006.257.12:29:18.41#ibcon#enter sib2, iclass 12, count 0 2006.257.12:29:18.41#ibcon#flushed, iclass 12, count 0 2006.257.12:29:18.41#ibcon#about to write, iclass 12, count 0 2006.257.12:29:18.41#ibcon#wrote, iclass 12, count 0 2006.257.12:29:18.41#ibcon#about to read 3, iclass 12, count 0 2006.257.12:29:18.43#ibcon#read 3, iclass 12, count 0 2006.257.12:29:18.43#ibcon#about to read 4, iclass 12, count 0 2006.257.12:29:18.43#ibcon#read 4, iclass 12, count 0 2006.257.12:29:18.43#ibcon#about to read 5, iclass 12, count 0 2006.257.12:29:18.43#ibcon#read 5, iclass 12, count 0 2006.257.12:29:18.43#ibcon#about to read 6, iclass 12, count 0 2006.257.12:29:18.43#ibcon#read 6, iclass 12, count 0 2006.257.12:29:18.43#ibcon#end of sib2, iclass 12, count 0 2006.257.12:29:18.43#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:29:18.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:29:18.43#ibcon#[27=USB\r\n] 2006.257.12:29:18.43#ibcon#*before write, iclass 12, count 0 2006.257.12:29:18.43#ibcon#enter sib2, iclass 12, count 0 2006.257.12:29:18.43#ibcon#flushed, iclass 12, count 0 2006.257.12:29:18.43#ibcon#about to write, iclass 12, count 0 2006.257.12:29:18.43#ibcon#wrote, iclass 12, count 0 2006.257.12:29:18.43#ibcon#about to read 3, iclass 12, count 0 2006.257.12:29:18.46#ibcon#read 3, iclass 12, count 0 2006.257.12:29:18.46#ibcon#about to read 4, iclass 12, count 0 2006.257.12:29:18.46#ibcon#read 4, iclass 12, count 0 2006.257.12:29:18.46#ibcon#about to read 5, iclass 12, count 0 2006.257.12:29:18.46#ibcon#read 5, iclass 12, count 0 2006.257.12:29:18.46#ibcon#about to read 6, iclass 12, count 0 2006.257.12:29:18.46#ibcon#read 6, iclass 12, count 0 2006.257.12:29:18.46#ibcon#end of sib2, iclass 12, count 0 2006.257.12:29:18.46#ibcon#*after write, iclass 12, count 0 2006.257.12:29:18.46#ibcon#*before return 0, iclass 12, count 0 2006.257.12:29:18.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:18.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:29:18.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:29:18.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:29:18.46$vck44/vblo=6,719.99 2006.257.12:29:18.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.12:29:18.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.12:29:18.46#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:18.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:18.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:18.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:18.46#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:29:18.46#ibcon#first serial, iclass 14, count 0 2006.257.12:29:18.46#ibcon#enter sib2, iclass 14, count 0 2006.257.12:29:18.46#ibcon#flushed, iclass 14, count 0 2006.257.12:29:18.46#ibcon#about to write, iclass 14, count 0 2006.257.12:29:18.46#ibcon#wrote, iclass 14, count 0 2006.257.12:29:18.46#ibcon#about to read 3, iclass 14, count 0 2006.257.12:29:18.48#ibcon#read 3, iclass 14, count 0 2006.257.12:29:18.48#ibcon#about to read 4, iclass 14, count 0 2006.257.12:29:18.48#ibcon#read 4, iclass 14, count 0 2006.257.12:29:18.48#ibcon#about to read 5, iclass 14, count 0 2006.257.12:29:18.48#ibcon#read 5, iclass 14, count 0 2006.257.12:29:18.48#ibcon#about to read 6, iclass 14, count 0 2006.257.12:29:18.48#ibcon#read 6, iclass 14, count 0 2006.257.12:29:18.48#ibcon#end of sib2, iclass 14, count 0 2006.257.12:29:18.48#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:29:18.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:29:18.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:29:18.48#ibcon#*before write, iclass 14, count 0 2006.257.12:29:18.48#ibcon#enter sib2, iclass 14, count 0 2006.257.12:29:18.48#ibcon#flushed, iclass 14, count 0 2006.257.12:29:18.48#ibcon#about to write, iclass 14, count 0 2006.257.12:29:18.48#ibcon#wrote, iclass 14, count 0 2006.257.12:29:18.48#ibcon#about to read 3, iclass 14, count 0 2006.257.12:29:18.52#ibcon#read 3, iclass 14, count 0 2006.257.12:29:18.52#ibcon#about to read 4, iclass 14, count 0 2006.257.12:29:18.52#ibcon#read 4, iclass 14, count 0 2006.257.12:29:18.52#ibcon#about to read 5, iclass 14, count 0 2006.257.12:29:18.52#ibcon#read 5, iclass 14, count 0 2006.257.12:29:18.52#ibcon#about to read 6, iclass 14, count 0 2006.257.12:29:18.52#ibcon#read 6, iclass 14, count 0 2006.257.12:29:18.52#ibcon#end of sib2, iclass 14, count 0 2006.257.12:29:18.52#ibcon#*after write, iclass 14, count 0 2006.257.12:29:18.52#ibcon#*before return 0, iclass 14, count 0 2006.257.12:29:18.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:18.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:29:18.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:29:18.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:29:18.52$vck44/vb=6,4 2006.257.12:29:18.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.12:29:18.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.12:29:18.52#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:18.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:18.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:18.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:18.58#ibcon#enter wrdev, iclass 16, count 2 2006.257.12:29:18.58#ibcon#first serial, iclass 16, count 2 2006.257.12:29:18.58#ibcon#enter sib2, iclass 16, count 2 2006.257.12:29:18.58#ibcon#flushed, iclass 16, count 2 2006.257.12:29:18.58#ibcon#about to write, iclass 16, count 2 2006.257.12:29:18.58#ibcon#wrote, iclass 16, count 2 2006.257.12:29:18.58#ibcon#about to read 3, iclass 16, count 2 2006.257.12:29:18.60#ibcon#read 3, iclass 16, count 2 2006.257.12:29:18.60#ibcon#about to read 4, iclass 16, count 2 2006.257.12:29:18.60#ibcon#read 4, iclass 16, count 2 2006.257.12:29:18.60#ibcon#about to read 5, iclass 16, count 2 2006.257.12:29:18.60#ibcon#read 5, iclass 16, count 2 2006.257.12:29:18.60#ibcon#about to read 6, iclass 16, count 2 2006.257.12:29:18.60#ibcon#read 6, iclass 16, count 2 2006.257.12:29:18.60#ibcon#end of sib2, iclass 16, count 2 2006.257.12:29:18.60#ibcon#*mode == 0, iclass 16, count 2 2006.257.12:29:18.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.12:29:18.60#ibcon#[27=AT06-04\r\n] 2006.257.12:29:18.60#ibcon#*before write, iclass 16, count 2 2006.257.12:29:18.60#ibcon#enter sib2, iclass 16, count 2 2006.257.12:29:18.60#ibcon#flushed, iclass 16, count 2 2006.257.12:29:18.60#ibcon#about to write, iclass 16, count 2 2006.257.12:29:18.60#ibcon#wrote, iclass 16, count 2 2006.257.12:29:18.60#ibcon#about to read 3, iclass 16, count 2 2006.257.12:29:18.63#ibcon#read 3, iclass 16, count 2 2006.257.12:29:18.63#ibcon#about to read 4, iclass 16, count 2 2006.257.12:29:18.63#ibcon#read 4, iclass 16, count 2 2006.257.12:29:18.63#ibcon#about to read 5, iclass 16, count 2 2006.257.12:29:18.63#ibcon#read 5, iclass 16, count 2 2006.257.12:29:18.63#ibcon#about to read 6, iclass 16, count 2 2006.257.12:29:18.63#ibcon#read 6, iclass 16, count 2 2006.257.12:29:18.63#ibcon#end of sib2, iclass 16, count 2 2006.257.12:29:18.63#ibcon#*after write, iclass 16, count 2 2006.257.12:29:18.63#ibcon#*before return 0, iclass 16, count 2 2006.257.12:29:18.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:18.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:29:18.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.12:29:18.63#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:18.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:18.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:18.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:18.75#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:29:18.75#ibcon#first serial, iclass 16, count 0 2006.257.12:29:18.75#ibcon#enter sib2, iclass 16, count 0 2006.257.12:29:18.75#ibcon#flushed, iclass 16, count 0 2006.257.12:29:18.75#ibcon#about to write, iclass 16, count 0 2006.257.12:29:18.75#ibcon#wrote, iclass 16, count 0 2006.257.12:29:18.75#ibcon#about to read 3, iclass 16, count 0 2006.257.12:29:18.77#ibcon#read 3, iclass 16, count 0 2006.257.12:29:18.77#ibcon#about to read 4, iclass 16, count 0 2006.257.12:29:18.77#ibcon#read 4, iclass 16, count 0 2006.257.12:29:18.77#ibcon#about to read 5, iclass 16, count 0 2006.257.12:29:18.77#ibcon#read 5, iclass 16, count 0 2006.257.12:29:18.77#ibcon#about to read 6, iclass 16, count 0 2006.257.12:29:18.77#ibcon#read 6, iclass 16, count 0 2006.257.12:29:18.77#ibcon#end of sib2, iclass 16, count 0 2006.257.12:29:18.77#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:29:18.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:29:18.77#ibcon#[27=USB\r\n] 2006.257.12:29:18.77#ibcon#*before write, iclass 16, count 0 2006.257.12:29:18.77#ibcon#enter sib2, iclass 16, count 0 2006.257.12:29:18.77#ibcon#flushed, iclass 16, count 0 2006.257.12:29:18.77#ibcon#about to write, iclass 16, count 0 2006.257.12:29:18.77#ibcon#wrote, iclass 16, count 0 2006.257.12:29:18.77#ibcon#about to read 3, iclass 16, count 0 2006.257.12:29:18.80#ibcon#read 3, iclass 16, count 0 2006.257.12:29:18.80#ibcon#about to read 4, iclass 16, count 0 2006.257.12:29:18.80#ibcon#read 4, iclass 16, count 0 2006.257.12:29:18.80#ibcon#about to read 5, iclass 16, count 0 2006.257.12:29:18.80#ibcon#read 5, iclass 16, count 0 2006.257.12:29:18.80#ibcon#about to read 6, iclass 16, count 0 2006.257.12:29:18.80#ibcon#read 6, iclass 16, count 0 2006.257.12:29:18.80#ibcon#end of sib2, iclass 16, count 0 2006.257.12:29:18.80#ibcon#*after write, iclass 16, count 0 2006.257.12:29:18.80#ibcon#*before return 0, iclass 16, count 0 2006.257.12:29:18.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:18.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:29:18.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:29:18.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:29:18.80$vck44/vblo=7,734.99 2006.257.12:29:18.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.12:29:18.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.12:29:18.80#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:18.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:18.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:18.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:18.80#ibcon#enter wrdev, iclass 18, count 0 2006.257.12:29:18.80#ibcon#first serial, iclass 18, count 0 2006.257.12:29:18.80#ibcon#enter sib2, iclass 18, count 0 2006.257.12:29:18.80#ibcon#flushed, iclass 18, count 0 2006.257.12:29:18.80#ibcon#about to write, iclass 18, count 0 2006.257.12:29:18.80#ibcon#wrote, iclass 18, count 0 2006.257.12:29:18.80#ibcon#about to read 3, iclass 18, count 0 2006.257.12:29:18.82#ibcon#read 3, iclass 18, count 0 2006.257.12:29:18.82#ibcon#about to read 4, iclass 18, count 0 2006.257.12:29:18.82#ibcon#read 4, iclass 18, count 0 2006.257.12:29:18.82#ibcon#about to read 5, iclass 18, count 0 2006.257.12:29:18.82#ibcon#read 5, iclass 18, count 0 2006.257.12:29:18.82#ibcon#about to read 6, iclass 18, count 0 2006.257.12:29:18.82#ibcon#read 6, iclass 18, count 0 2006.257.12:29:18.82#ibcon#end of sib2, iclass 18, count 0 2006.257.12:29:18.82#ibcon#*mode == 0, iclass 18, count 0 2006.257.12:29:18.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.12:29:18.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:29:18.82#ibcon#*before write, iclass 18, count 0 2006.257.12:29:18.82#ibcon#enter sib2, iclass 18, count 0 2006.257.12:29:18.82#ibcon#flushed, iclass 18, count 0 2006.257.12:29:18.82#ibcon#about to write, iclass 18, count 0 2006.257.12:29:18.82#ibcon#wrote, iclass 18, count 0 2006.257.12:29:18.82#ibcon#about to read 3, iclass 18, count 0 2006.257.12:29:18.86#ibcon#read 3, iclass 18, count 0 2006.257.12:29:18.86#ibcon#about to read 4, iclass 18, count 0 2006.257.12:29:18.86#ibcon#read 4, iclass 18, count 0 2006.257.12:29:18.86#ibcon#about to read 5, iclass 18, count 0 2006.257.12:29:18.86#ibcon#read 5, iclass 18, count 0 2006.257.12:29:18.86#ibcon#about to read 6, iclass 18, count 0 2006.257.12:29:18.86#ibcon#read 6, iclass 18, count 0 2006.257.12:29:18.86#ibcon#end of sib2, iclass 18, count 0 2006.257.12:29:18.86#ibcon#*after write, iclass 18, count 0 2006.257.12:29:18.86#ibcon#*before return 0, iclass 18, count 0 2006.257.12:29:18.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:18.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:29:18.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.12:29:18.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.12:29:18.86$vck44/vb=7,4 2006.257.12:29:18.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.12:29:18.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.12:29:18.86#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:18.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:18.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:18.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:18.92#ibcon#enter wrdev, iclass 20, count 2 2006.257.12:29:18.92#ibcon#first serial, iclass 20, count 2 2006.257.12:29:18.92#ibcon#enter sib2, iclass 20, count 2 2006.257.12:29:18.92#ibcon#flushed, iclass 20, count 2 2006.257.12:29:18.92#ibcon#about to write, iclass 20, count 2 2006.257.12:29:18.92#ibcon#wrote, iclass 20, count 2 2006.257.12:29:18.92#ibcon#about to read 3, iclass 20, count 2 2006.257.12:29:18.94#ibcon#read 3, iclass 20, count 2 2006.257.12:29:18.94#ibcon#about to read 4, iclass 20, count 2 2006.257.12:29:18.94#ibcon#read 4, iclass 20, count 2 2006.257.12:29:18.94#ibcon#about to read 5, iclass 20, count 2 2006.257.12:29:18.94#ibcon#read 5, iclass 20, count 2 2006.257.12:29:18.94#ibcon#about to read 6, iclass 20, count 2 2006.257.12:29:18.94#ibcon#read 6, iclass 20, count 2 2006.257.12:29:18.94#ibcon#end of sib2, iclass 20, count 2 2006.257.12:29:18.94#ibcon#*mode == 0, iclass 20, count 2 2006.257.12:29:18.94#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.12:29:18.94#ibcon#[27=AT07-04\r\n] 2006.257.12:29:18.94#ibcon#*before write, iclass 20, count 2 2006.257.12:29:18.94#ibcon#enter sib2, iclass 20, count 2 2006.257.12:29:18.94#ibcon#flushed, iclass 20, count 2 2006.257.12:29:18.94#ibcon#about to write, iclass 20, count 2 2006.257.12:29:18.94#ibcon#wrote, iclass 20, count 2 2006.257.12:29:18.94#ibcon#about to read 3, iclass 20, count 2 2006.257.12:29:18.97#ibcon#read 3, iclass 20, count 2 2006.257.12:29:18.97#ibcon#about to read 4, iclass 20, count 2 2006.257.12:29:18.97#ibcon#read 4, iclass 20, count 2 2006.257.12:29:18.97#ibcon#about to read 5, iclass 20, count 2 2006.257.12:29:18.97#ibcon#read 5, iclass 20, count 2 2006.257.12:29:18.97#ibcon#about to read 6, iclass 20, count 2 2006.257.12:29:18.97#ibcon#read 6, iclass 20, count 2 2006.257.12:29:18.97#ibcon#end of sib2, iclass 20, count 2 2006.257.12:29:18.97#ibcon#*after write, iclass 20, count 2 2006.257.12:29:18.97#ibcon#*before return 0, iclass 20, count 2 2006.257.12:29:18.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:18.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.12:29:18.97#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.12:29:18.97#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:18.97#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:19.09#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:19.09#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:19.09#ibcon#enter wrdev, iclass 20, count 0 2006.257.12:29:19.09#ibcon#first serial, iclass 20, count 0 2006.257.12:29:19.09#ibcon#enter sib2, iclass 20, count 0 2006.257.12:29:19.09#ibcon#flushed, iclass 20, count 0 2006.257.12:29:19.09#ibcon#about to write, iclass 20, count 0 2006.257.12:29:19.09#ibcon#wrote, iclass 20, count 0 2006.257.12:29:19.09#ibcon#about to read 3, iclass 20, count 0 2006.257.12:29:19.11#ibcon#read 3, iclass 20, count 0 2006.257.12:29:19.11#ibcon#about to read 4, iclass 20, count 0 2006.257.12:29:19.11#ibcon#read 4, iclass 20, count 0 2006.257.12:29:19.11#ibcon#about to read 5, iclass 20, count 0 2006.257.12:29:19.11#ibcon#read 5, iclass 20, count 0 2006.257.12:29:19.11#ibcon#about to read 6, iclass 20, count 0 2006.257.12:29:19.11#ibcon#read 6, iclass 20, count 0 2006.257.12:29:19.11#ibcon#end of sib2, iclass 20, count 0 2006.257.12:29:19.11#ibcon#*mode == 0, iclass 20, count 0 2006.257.12:29:19.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.12:29:19.11#ibcon#[27=USB\r\n] 2006.257.12:29:19.11#ibcon#*before write, iclass 20, count 0 2006.257.12:29:19.11#ibcon#enter sib2, iclass 20, count 0 2006.257.12:29:19.11#ibcon#flushed, iclass 20, count 0 2006.257.12:29:19.11#ibcon#about to write, iclass 20, count 0 2006.257.12:29:19.11#ibcon#wrote, iclass 20, count 0 2006.257.12:29:19.11#ibcon#about to read 3, iclass 20, count 0 2006.257.12:29:19.14#ibcon#read 3, iclass 20, count 0 2006.257.12:29:19.14#ibcon#about to read 4, iclass 20, count 0 2006.257.12:29:19.14#ibcon#read 4, iclass 20, count 0 2006.257.12:29:19.14#ibcon#about to read 5, iclass 20, count 0 2006.257.12:29:19.14#ibcon#read 5, iclass 20, count 0 2006.257.12:29:19.14#ibcon#about to read 6, iclass 20, count 0 2006.257.12:29:19.14#ibcon#read 6, iclass 20, count 0 2006.257.12:29:19.14#ibcon#end of sib2, iclass 20, count 0 2006.257.12:29:19.14#ibcon#*after write, iclass 20, count 0 2006.257.12:29:19.14#ibcon#*before return 0, iclass 20, count 0 2006.257.12:29:19.14#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:19.14#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.12:29:19.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.12:29:19.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.12:29:19.14$vck44/vblo=8,744.99 2006.257.12:29:19.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.12:29:19.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.12:29:19.14#ibcon#ireg 17 cls_cnt 0 2006.257.12:29:19.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:19.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:19.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:19.14#ibcon#enter wrdev, iclass 22, count 0 2006.257.12:29:19.14#ibcon#first serial, iclass 22, count 0 2006.257.12:29:19.14#ibcon#enter sib2, iclass 22, count 0 2006.257.12:29:19.14#ibcon#flushed, iclass 22, count 0 2006.257.12:29:19.14#ibcon#about to write, iclass 22, count 0 2006.257.12:29:19.14#ibcon#wrote, iclass 22, count 0 2006.257.12:29:19.14#ibcon#about to read 3, iclass 22, count 0 2006.257.12:29:19.16#ibcon#read 3, iclass 22, count 0 2006.257.12:29:19.16#ibcon#about to read 4, iclass 22, count 0 2006.257.12:29:19.16#ibcon#read 4, iclass 22, count 0 2006.257.12:29:19.16#ibcon#about to read 5, iclass 22, count 0 2006.257.12:29:19.16#ibcon#read 5, iclass 22, count 0 2006.257.12:29:19.16#ibcon#about to read 6, iclass 22, count 0 2006.257.12:29:19.16#ibcon#read 6, iclass 22, count 0 2006.257.12:29:19.16#ibcon#end of sib2, iclass 22, count 0 2006.257.12:29:19.16#ibcon#*mode == 0, iclass 22, count 0 2006.257.12:29:19.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.12:29:19.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:29:19.16#ibcon#*before write, iclass 22, count 0 2006.257.12:29:19.16#ibcon#enter sib2, iclass 22, count 0 2006.257.12:29:19.16#ibcon#flushed, iclass 22, count 0 2006.257.12:29:19.16#ibcon#about to write, iclass 22, count 0 2006.257.12:29:19.16#ibcon#wrote, iclass 22, count 0 2006.257.12:29:19.16#ibcon#about to read 3, iclass 22, count 0 2006.257.12:29:19.20#ibcon#read 3, iclass 22, count 0 2006.257.12:29:19.20#ibcon#about to read 4, iclass 22, count 0 2006.257.12:29:19.20#ibcon#read 4, iclass 22, count 0 2006.257.12:29:19.20#ibcon#about to read 5, iclass 22, count 0 2006.257.12:29:19.20#ibcon#read 5, iclass 22, count 0 2006.257.12:29:19.20#ibcon#about to read 6, iclass 22, count 0 2006.257.12:29:19.20#ibcon#read 6, iclass 22, count 0 2006.257.12:29:19.20#ibcon#end of sib2, iclass 22, count 0 2006.257.12:29:19.20#ibcon#*after write, iclass 22, count 0 2006.257.12:29:19.20#ibcon#*before return 0, iclass 22, count 0 2006.257.12:29:19.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:19.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:29:19.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.12:29:19.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.12:29:19.20$vck44/vb=8,4 2006.257.12:29:19.20#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.12:29:19.20#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.12:29:19.20#ibcon#ireg 11 cls_cnt 2 2006.257.12:29:19.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:19.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:19.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:19.26#ibcon#enter wrdev, iclass 24, count 2 2006.257.12:29:19.26#ibcon#first serial, iclass 24, count 2 2006.257.12:29:19.26#ibcon#enter sib2, iclass 24, count 2 2006.257.12:29:19.26#ibcon#flushed, iclass 24, count 2 2006.257.12:29:19.26#ibcon#about to write, iclass 24, count 2 2006.257.12:29:19.26#ibcon#wrote, iclass 24, count 2 2006.257.12:29:19.26#ibcon#about to read 3, iclass 24, count 2 2006.257.12:29:19.28#ibcon#read 3, iclass 24, count 2 2006.257.12:29:19.28#ibcon#about to read 4, iclass 24, count 2 2006.257.12:29:19.28#ibcon#read 4, iclass 24, count 2 2006.257.12:29:19.28#ibcon#about to read 5, iclass 24, count 2 2006.257.12:29:19.28#ibcon#read 5, iclass 24, count 2 2006.257.12:29:19.28#ibcon#about to read 6, iclass 24, count 2 2006.257.12:29:19.28#ibcon#read 6, iclass 24, count 2 2006.257.12:29:19.28#ibcon#end of sib2, iclass 24, count 2 2006.257.12:29:19.28#ibcon#*mode == 0, iclass 24, count 2 2006.257.12:29:19.28#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.12:29:19.28#ibcon#[27=AT08-04\r\n] 2006.257.12:29:19.28#ibcon#*before write, iclass 24, count 2 2006.257.12:29:19.28#ibcon#enter sib2, iclass 24, count 2 2006.257.12:29:19.28#ibcon#flushed, iclass 24, count 2 2006.257.12:29:19.28#ibcon#about to write, iclass 24, count 2 2006.257.12:29:19.28#ibcon#wrote, iclass 24, count 2 2006.257.12:29:19.28#ibcon#about to read 3, iclass 24, count 2 2006.257.12:29:19.31#ibcon#read 3, iclass 24, count 2 2006.257.12:29:19.31#ibcon#about to read 4, iclass 24, count 2 2006.257.12:29:19.31#ibcon#read 4, iclass 24, count 2 2006.257.12:29:19.31#ibcon#about to read 5, iclass 24, count 2 2006.257.12:29:19.31#ibcon#read 5, iclass 24, count 2 2006.257.12:29:19.31#ibcon#about to read 6, iclass 24, count 2 2006.257.12:29:19.31#ibcon#read 6, iclass 24, count 2 2006.257.12:29:19.31#ibcon#end of sib2, iclass 24, count 2 2006.257.12:29:19.31#ibcon#*after write, iclass 24, count 2 2006.257.12:29:19.31#ibcon#*before return 0, iclass 24, count 2 2006.257.12:29:19.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:19.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:29:19.31#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.12:29:19.31#ibcon#ireg 7 cls_cnt 0 2006.257.12:29:19.31#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:19.43#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:19.43#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:19.43#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:29:19.43#ibcon#first serial, iclass 24, count 0 2006.257.12:29:19.43#ibcon#enter sib2, iclass 24, count 0 2006.257.12:29:19.43#ibcon#flushed, iclass 24, count 0 2006.257.12:29:19.43#ibcon#about to write, iclass 24, count 0 2006.257.12:29:19.43#ibcon#wrote, iclass 24, count 0 2006.257.12:29:19.43#ibcon#about to read 3, iclass 24, count 0 2006.257.12:29:19.45#ibcon#read 3, iclass 24, count 0 2006.257.12:29:19.45#ibcon#about to read 4, iclass 24, count 0 2006.257.12:29:19.45#ibcon#read 4, iclass 24, count 0 2006.257.12:29:19.45#ibcon#about to read 5, iclass 24, count 0 2006.257.12:29:19.45#ibcon#read 5, iclass 24, count 0 2006.257.12:29:19.45#ibcon#about to read 6, iclass 24, count 0 2006.257.12:29:19.45#ibcon#read 6, iclass 24, count 0 2006.257.12:29:19.45#ibcon#end of sib2, iclass 24, count 0 2006.257.12:29:19.45#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:29:19.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:29:19.45#ibcon#[27=USB\r\n] 2006.257.12:29:19.45#ibcon#*before write, iclass 24, count 0 2006.257.12:29:19.45#ibcon#enter sib2, iclass 24, count 0 2006.257.12:29:19.45#ibcon#flushed, iclass 24, count 0 2006.257.12:29:19.45#ibcon#about to write, iclass 24, count 0 2006.257.12:29:19.45#ibcon#wrote, iclass 24, count 0 2006.257.12:29:19.45#ibcon#about to read 3, iclass 24, count 0 2006.257.12:29:19.48#ibcon#read 3, iclass 24, count 0 2006.257.12:29:19.48#ibcon#about to read 4, iclass 24, count 0 2006.257.12:29:19.48#ibcon#read 4, iclass 24, count 0 2006.257.12:29:19.48#ibcon#about to read 5, iclass 24, count 0 2006.257.12:29:19.48#ibcon#read 5, iclass 24, count 0 2006.257.12:29:19.48#ibcon#about to read 6, iclass 24, count 0 2006.257.12:29:19.48#ibcon#read 6, iclass 24, count 0 2006.257.12:29:19.48#ibcon#end of sib2, iclass 24, count 0 2006.257.12:29:19.48#ibcon#*after write, iclass 24, count 0 2006.257.12:29:19.48#ibcon#*before return 0, iclass 24, count 0 2006.257.12:29:19.48#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:19.48#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:29:19.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:29:19.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:29:19.48$vck44/vabw=wide 2006.257.12:29:19.48#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.12:29:19.48#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.12:29:19.48#ibcon#ireg 8 cls_cnt 0 2006.257.12:29:19.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:19.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:19.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:19.48#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:29:19.48#ibcon#first serial, iclass 26, count 0 2006.257.12:29:19.48#ibcon#enter sib2, iclass 26, count 0 2006.257.12:29:19.48#ibcon#flushed, iclass 26, count 0 2006.257.12:29:19.48#ibcon#about to write, iclass 26, count 0 2006.257.12:29:19.48#ibcon#wrote, iclass 26, count 0 2006.257.12:29:19.48#ibcon#about to read 3, iclass 26, count 0 2006.257.12:29:19.50#ibcon#read 3, iclass 26, count 0 2006.257.12:29:19.50#ibcon#about to read 4, iclass 26, count 0 2006.257.12:29:19.50#ibcon#read 4, iclass 26, count 0 2006.257.12:29:19.50#ibcon#about to read 5, iclass 26, count 0 2006.257.12:29:19.50#ibcon#read 5, iclass 26, count 0 2006.257.12:29:19.50#ibcon#about to read 6, iclass 26, count 0 2006.257.12:29:19.50#ibcon#read 6, iclass 26, count 0 2006.257.12:29:19.50#ibcon#end of sib2, iclass 26, count 0 2006.257.12:29:19.50#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:29:19.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:29:19.50#ibcon#[25=BW32\r\n] 2006.257.12:29:19.50#ibcon#*before write, iclass 26, count 0 2006.257.12:29:19.50#ibcon#enter sib2, iclass 26, count 0 2006.257.12:29:19.50#ibcon#flushed, iclass 26, count 0 2006.257.12:29:19.50#ibcon#about to write, iclass 26, count 0 2006.257.12:29:19.50#ibcon#wrote, iclass 26, count 0 2006.257.12:29:19.50#ibcon#about to read 3, iclass 26, count 0 2006.257.12:29:19.53#ibcon#read 3, iclass 26, count 0 2006.257.12:29:19.53#ibcon#about to read 4, iclass 26, count 0 2006.257.12:29:19.53#ibcon#read 4, iclass 26, count 0 2006.257.12:29:19.53#ibcon#about to read 5, iclass 26, count 0 2006.257.12:29:19.53#ibcon#read 5, iclass 26, count 0 2006.257.12:29:19.53#ibcon#about to read 6, iclass 26, count 0 2006.257.12:29:19.53#ibcon#read 6, iclass 26, count 0 2006.257.12:29:19.53#ibcon#end of sib2, iclass 26, count 0 2006.257.12:29:19.53#ibcon#*after write, iclass 26, count 0 2006.257.12:29:19.53#ibcon#*before return 0, iclass 26, count 0 2006.257.12:29:19.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:19.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:29:19.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:29:19.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:29:19.53$vck44/vbbw=wide 2006.257.12:29:19.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.12:29:19.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.12:29:19.53#ibcon#ireg 8 cls_cnt 0 2006.257.12:29:19.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:29:19.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:29:19.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:29:19.60#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:29:19.60#ibcon#first serial, iclass 28, count 0 2006.257.12:29:19.60#ibcon#enter sib2, iclass 28, count 0 2006.257.12:29:19.60#ibcon#flushed, iclass 28, count 0 2006.257.12:29:19.60#ibcon#about to write, iclass 28, count 0 2006.257.12:29:19.60#ibcon#wrote, iclass 28, count 0 2006.257.12:29:19.60#ibcon#about to read 3, iclass 28, count 0 2006.257.12:29:19.62#ibcon#read 3, iclass 28, count 0 2006.257.12:29:19.62#ibcon#about to read 4, iclass 28, count 0 2006.257.12:29:19.62#ibcon#read 4, iclass 28, count 0 2006.257.12:29:19.62#ibcon#about to read 5, iclass 28, count 0 2006.257.12:29:19.62#ibcon#read 5, iclass 28, count 0 2006.257.12:29:19.62#ibcon#about to read 6, iclass 28, count 0 2006.257.12:29:19.62#ibcon#read 6, iclass 28, count 0 2006.257.12:29:19.62#ibcon#end of sib2, iclass 28, count 0 2006.257.12:29:19.62#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:29:19.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:29:19.62#ibcon#[27=BW32\r\n] 2006.257.12:29:19.62#ibcon#*before write, iclass 28, count 0 2006.257.12:29:19.62#ibcon#enter sib2, iclass 28, count 0 2006.257.12:29:19.62#ibcon#flushed, iclass 28, count 0 2006.257.12:29:19.62#ibcon#about to write, iclass 28, count 0 2006.257.12:29:19.62#ibcon#wrote, iclass 28, count 0 2006.257.12:29:19.62#ibcon#about to read 3, iclass 28, count 0 2006.257.12:29:19.65#ibcon#read 3, iclass 28, count 0 2006.257.12:29:19.65#ibcon#about to read 4, iclass 28, count 0 2006.257.12:29:19.65#ibcon#read 4, iclass 28, count 0 2006.257.12:29:19.65#ibcon#about to read 5, iclass 28, count 0 2006.257.12:29:19.65#ibcon#read 5, iclass 28, count 0 2006.257.12:29:19.65#ibcon#about to read 6, iclass 28, count 0 2006.257.12:29:19.65#ibcon#read 6, iclass 28, count 0 2006.257.12:29:19.65#ibcon#end of sib2, iclass 28, count 0 2006.257.12:29:19.65#ibcon#*after write, iclass 28, count 0 2006.257.12:29:19.65#ibcon#*before return 0, iclass 28, count 0 2006.257.12:29:19.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:29:19.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:29:19.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:29:19.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:29:19.65$setupk4/ifdk4 2006.257.12:29:19.65$ifdk4/lo= 2006.257.12:29:19.65$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:29:19.65$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:29:19.65$ifdk4/patch= 2006.257.12:29:19.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:29:19.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:29:19.65$setupk4/!*+20s 2006.257.12:29:21.41#abcon#<5=/14 1.6 5.0 18.01 961013.8\r\n> 2006.257.12:29:21.43#abcon#{5=INTERFACE CLEAR} 2006.257.12:29:21.49#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:29:31.58#abcon#<5=/14 1.6 5.0 18.01 961013.8\r\n> 2006.257.12:29:31.60#abcon#{5=INTERFACE CLEAR} 2006.257.12:29:31.66#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:29:34.16$setupk4/"tpicd 2006.257.12:29:34.16$setupk4/echo=off 2006.257.12:29:34.16$setupk4/xlog=off 2006.257.12:29:34.16:!2006.257.12:32:31 2006.257.12:30:01.13#trakl#Source acquired 2006.257.12:30:03.13#flagr#flagr/antenna,acquired 2006.257.12:32:31.00:preob 2006.257.12:32:31.14/onsource/TRACKING 2006.257.12:32:31.14:!2006.257.12:32:41 2006.257.12:32:41.00:"tape 2006.257.12:32:41.00:"st=record 2006.257.12:32:41.00:data_valid=on 2006.257.12:32:41.00:midob 2006.257.12:32:42.14/onsource/TRACKING 2006.257.12:32:42.14/wx/17.96,1013.8,96 2006.257.12:32:42.23/cable/+6.4800E-03 2006.257.12:32:43.32/va/01,08,usb,yes,30,32 2006.257.12:32:43.32/va/02,07,usb,yes,32,33 2006.257.12:32:43.32/va/03,08,usb,yes,29,31 2006.257.12:32:43.32/va/04,07,usb,yes,33,35 2006.257.12:32:43.32/va/05,04,usb,yes,30,30 2006.257.12:32:43.32/va/06,04,usb,yes,33,33 2006.257.12:32:43.32/va/07,04,usb,yes,34,34 2006.257.12:32:43.32/va/08,04,usb,yes,28,35 2006.257.12:32:43.55/valo/01,524.99,yes,locked 2006.257.12:32:43.55/valo/02,534.99,yes,locked 2006.257.12:32:43.55/valo/03,564.99,yes,locked 2006.257.12:32:43.55/valo/04,624.99,yes,locked 2006.257.12:32:43.55/valo/05,734.99,yes,locked 2006.257.12:32:43.55/valo/06,814.99,yes,locked 2006.257.12:32:43.55/valo/07,864.99,yes,locked 2006.257.12:32:43.55/valo/08,884.99,yes,locked 2006.257.12:32:44.64/vb/01,04,usb,yes,30,28 2006.257.12:32:44.64/vb/02,05,usb,yes,29,28 2006.257.12:32:44.64/vb/03,04,usb,yes,29,32 2006.257.12:32:44.64/vb/04,05,usb,yes,30,29 2006.257.12:32:44.64/vb/05,04,usb,yes,26,29 2006.257.12:32:44.64/vb/06,04,usb,yes,31,27 2006.257.12:32:44.64/vb/07,04,usb,yes,30,30 2006.257.12:32:44.64/vb/08,04,usb,yes,28,31 2006.257.12:32:44.87/vblo/01,629.99,yes,locked 2006.257.12:32:44.87/vblo/02,634.99,yes,locked 2006.257.12:32:44.87/vblo/03,649.99,yes,locked 2006.257.12:32:44.87/vblo/04,679.99,yes,locked 2006.257.12:32:44.87/vblo/05,709.99,yes,locked 2006.257.12:32:44.87/vblo/06,719.99,yes,locked 2006.257.12:32:44.87/vblo/07,734.99,yes,locked 2006.257.12:32:44.87/vblo/08,744.99,yes,locked 2006.257.12:32:45.02/vabw/8 2006.257.12:32:45.17/vbbw/8 2006.257.12:32:45.26/xfe/off,on,15.2 2006.257.12:32:45.63/ifatt/23,28,28,28 2006.257.12:32:46.08/fmout-gps/S +4.58E-07 2006.257.12:32:46.12:!2006.257.12:33:51 2006.257.12:33:51.00:data_valid=off 2006.257.12:33:51.00:"et 2006.257.12:33:51.00:!+3s 2006.257.12:33:54.02:"tape 2006.257.12:33:54.02:postob 2006.257.12:33:54.20/cable/+6.4787E-03 2006.257.12:33:54.20/wx/17.95,1013.9,96 2006.257.12:33:54.26/fmout-gps/S +4.57E-07 2006.257.12:33:54.26:scan_name=257-1235,jd0609,160 2006.257.12:33:54.26:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.257.12:33:56.14#flagr#flagr/antenna,new-source 2006.257.12:33:56.14:checkk5 2006.257.12:33:56.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:33:56.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:33:57.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:33:57.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:33:58.14/chk_obsdata//k5ts1/T2571232??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.12:33:58.55/chk_obsdata//k5ts2/T2571232??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.12:33:58.94/chk_obsdata//k5ts3/T2571232??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.12:33:59.33/chk_obsdata//k5ts4/T2571232??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.12:34:00.06/k5log//k5ts1_log_newline 2006.257.12:34:00.76/k5log//k5ts2_log_newline 2006.257.12:34:01.50/k5log//k5ts3_log_newline 2006.257.12:34:02.21/k5log//k5ts4_log_newline 2006.257.12:34:02.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:34:02.23:setupk4=1 2006.257.12:34:02.24$setupk4/echo=on 2006.257.12:34:02.24$setupk4/pcalon 2006.257.12:34:02.24$pcalon/"no phase cal control is implemented here 2006.257.12:34:02.24$setupk4/"tpicd=stop 2006.257.12:34:02.24$setupk4/"rec=synch_on 2006.257.12:34:02.24$setupk4/"rec_mode=128 2006.257.12:34:02.24$setupk4/!* 2006.257.12:34:02.24$setupk4/recpk4 2006.257.12:34:02.24$recpk4/recpatch= 2006.257.12:34:02.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:34:02.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:34:02.24$setupk4/vck44 2006.257.12:34:02.24$vck44/valo=1,524.99 2006.257.12:34:02.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.12:34:02.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.12:34:02.24#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:02.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:02.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:02.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:02.24#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:34:02.24#ibcon#first serial, iclass 37, count 0 2006.257.12:34:02.24#ibcon#enter sib2, iclass 37, count 0 2006.257.12:34:02.24#ibcon#flushed, iclass 37, count 0 2006.257.12:34:02.24#ibcon#about to write, iclass 37, count 0 2006.257.12:34:02.24#ibcon#wrote, iclass 37, count 0 2006.257.12:34:02.24#ibcon#about to read 3, iclass 37, count 0 2006.257.12:34:02.26#ibcon#read 3, iclass 37, count 0 2006.257.12:34:02.26#ibcon#about to read 4, iclass 37, count 0 2006.257.12:34:02.26#ibcon#read 4, iclass 37, count 0 2006.257.12:34:02.26#ibcon#about to read 5, iclass 37, count 0 2006.257.12:34:02.26#ibcon#read 5, iclass 37, count 0 2006.257.12:34:02.26#ibcon#about to read 6, iclass 37, count 0 2006.257.12:34:02.26#ibcon#read 6, iclass 37, count 0 2006.257.12:34:02.26#ibcon#end of sib2, iclass 37, count 0 2006.257.12:34:02.26#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:34:02.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:34:02.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:34:02.26#ibcon#*before write, iclass 37, count 0 2006.257.12:34:02.26#ibcon#enter sib2, iclass 37, count 0 2006.257.12:34:02.26#ibcon#flushed, iclass 37, count 0 2006.257.12:34:02.26#ibcon#about to write, iclass 37, count 0 2006.257.12:34:02.26#ibcon#wrote, iclass 37, count 0 2006.257.12:34:02.26#ibcon#about to read 3, iclass 37, count 0 2006.257.12:34:02.31#ibcon#read 3, iclass 37, count 0 2006.257.12:34:02.31#ibcon#about to read 4, iclass 37, count 0 2006.257.12:34:02.31#ibcon#read 4, iclass 37, count 0 2006.257.12:34:02.31#ibcon#about to read 5, iclass 37, count 0 2006.257.12:34:02.31#ibcon#read 5, iclass 37, count 0 2006.257.12:34:02.31#ibcon#about to read 6, iclass 37, count 0 2006.257.12:34:02.31#ibcon#read 6, iclass 37, count 0 2006.257.12:34:02.31#ibcon#end of sib2, iclass 37, count 0 2006.257.12:34:02.31#ibcon#*after write, iclass 37, count 0 2006.257.12:34:02.31#ibcon#*before return 0, iclass 37, count 0 2006.257.12:34:02.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:02.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:02.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:34:02.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:34:02.31$vck44/va=1,8 2006.257.12:34:02.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.12:34:02.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.12:34:02.31#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:02.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:02.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:02.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:02.31#ibcon#enter wrdev, iclass 39, count 2 2006.257.12:34:02.31#ibcon#first serial, iclass 39, count 2 2006.257.12:34:02.31#ibcon#enter sib2, iclass 39, count 2 2006.257.12:34:02.31#ibcon#flushed, iclass 39, count 2 2006.257.12:34:02.31#ibcon#about to write, iclass 39, count 2 2006.257.12:34:02.31#ibcon#wrote, iclass 39, count 2 2006.257.12:34:02.31#ibcon#about to read 3, iclass 39, count 2 2006.257.12:34:02.33#ibcon#read 3, iclass 39, count 2 2006.257.12:34:02.33#ibcon#about to read 4, iclass 39, count 2 2006.257.12:34:02.33#ibcon#read 4, iclass 39, count 2 2006.257.12:34:02.33#ibcon#about to read 5, iclass 39, count 2 2006.257.12:34:02.33#ibcon#read 5, iclass 39, count 2 2006.257.12:34:02.33#ibcon#about to read 6, iclass 39, count 2 2006.257.12:34:02.33#ibcon#read 6, iclass 39, count 2 2006.257.12:34:02.33#ibcon#end of sib2, iclass 39, count 2 2006.257.12:34:02.33#ibcon#*mode == 0, iclass 39, count 2 2006.257.12:34:02.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.12:34:02.33#ibcon#[25=AT01-08\r\n] 2006.257.12:34:02.33#ibcon#*before write, iclass 39, count 2 2006.257.12:34:02.33#ibcon#enter sib2, iclass 39, count 2 2006.257.12:34:02.33#ibcon#flushed, iclass 39, count 2 2006.257.12:34:02.33#ibcon#about to write, iclass 39, count 2 2006.257.12:34:02.33#ibcon#wrote, iclass 39, count 2 2006.257.12:34:02.33#ibcon#about to read 3, iclass 39, count 2 2006.257.12:34:02.36#ibcon#read 3, iclass 39, count 2 2006.257.12:34:02.36#ibcon#about to read 4, iclass 39, count 2 2006.257.12:34:02.36#ibcon#read 4, iclass 39, count 2 2006.257.12:34:02.36#ibcon#about to read 5, iclass 39, count 2 2006.257.12:34:02.36#ibcon#read 5, iclass 39, count 2 2006.257.12:34:02.36#ibcon#about to read 6, iclass 39, count 2 2006.257.12:34:02.36#ibcon#read 6, iclass 39, count 2 2006.257.12:34:02.36#ibcon#end of sib2, iclass 39, count 2 2006.257.12:34:02.36#ibcon#*after write, iclass 39, count 2 2006.257.12:34:02.36#ibcon#*before return 0, iclass 39, count 2 2006.257.12:34:02.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:02.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:02.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.12:34:02.36#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:02.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:02.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:02.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:02.48#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:34:02.48#ibcon#first serial, iclass 39, count 0 2006.257.12:34:02.48#ibcon#enter sib2, iclass 39, count 0 2006.257.12:34:02.48#ibcon#flushed, iclass 39, count 0 2006.257.12:34:02.48#ibcon#about to write, iclass 39, count 0 2006.257.12:34:02.48#ibcon#wrote, iclass 39, count 0 2006.257.12:34:02.48#ibcon#about to read 3, iclass 39, count 0 2006.257.12:34:02.50#ibcon#read 3, iclass 39, count 0 2006.257.12:34:02.50#ibcon#about to read 4, iclass 39, count 0 2006.257.12:34:02.50#ibcon#read 4, iclass 39, count 0 2006.257.12:34:02.50#ibcon#about to read 5, iclass 39, count 0 2006.257.12:34:02.50#ibcon#read 5, iclass 39, count 0 2006.257.12:34:02.50#ibcon#about to read 6, iclass 39, count 0 2006.257.12:34:02.50#ibcon#read 6, iclass 39, count 0 2006.257.12:34:02.50#ibcon#end of sib2, iclass 39, count 0 2006.257.12:34:02.50#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:34:02.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:34:02.50#ibcon#[25=USB\r\n] 2006.257.12:34:02.50#ibcon#*before write, iclass 39, count 0 2006.257.12:34:02.50#ibcon#enter sib2, iclass 39, count 0 2006.257.12:34:02.50#ibcon#flushed, iclass 39, count 0 2006.257.12:34:02.50#ibcon#about to write, iclass 39, count 0 2006.257.12:34:02.50#ibcon#wrote, iclass 39, count 0 2006.257.12:34:02.50#ibcon#about to read 3, iclass 39, count 0 2006.257.12:34:02.53#ibcon#read 3, iclass 39, count 0 2006.257.12:34:02.53#ibcon#about to read 4, iclass 39, count 0 2006.257.12:34:02.53#ibcon#read 4, iclass 39, count 0 2006.257.12:34:02.53#ibcon#about to read 5, iclass 39, count 0 2006.257.12:34:02.53#ibcon#read 5, iclass 39, count 0 2006.257.12:34:02.53#ibcon#about to read 6, iclass 39, count 0 2006.257.12:34:02.53#ibcon#read 6, iclass 39, count 0 2006.257.12:34:02.53#ibcon#end of sib2, iclass 39, count 0 2006.257.12:34:02.53#ibcon#*after write, iclass 39, count 0 2006.257.12:34:02.53#ibcon#*before return 0, iclass 39, count 0 2006.257.12:34:02.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:02.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:02.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:34:02.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:34:02.53$vck44/valo=2,534.99 2006.257.12:34:02.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.12:34:02.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.12:34:02.53#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:02.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:02.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:02.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:02.53#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:34:02.53#ibcon#first serial, iclass 3, count 0 2006.257.12:34:02.53#ibcon#enter sib2, iclass 3, count 0 2006.257.12:34:02.53#ibcon#flushed, iclass 3, count 0 2006.257.12:34:02.53#ibcon#about to write, iclass 3, count 0 2006.257.12:34:02.53#ibcon#wrote, iclass 3, count 0 2006.257.12:34:02.53#ibcon#about to read 3, iclass 3, count 0 2006.257.12:34:02.55#ibcon#read 3, iclass 3, count 0 2006.257.12:34:02.55#ibcon#about to read 4, iclass 3, count 0 2006.257.12:34:02.55#ibcon#read 4, iclass 3, count 0 2006.257.12:34:02.55#ibcon#about to read 5, iclass 3, count 0 2006.257.12:34:02.55#ibcon#read 5, iclass 3, count 0 2006.257.12:34:02.55#ibcon#about to read 6, iclass 3, count 0 2006.257.12:34:02.55#ibcon#read 6, iclass 3, count 0 2006.257.12:34:02.55#ibcon#end of sib2, iclass 3, count 0 2006.257.12:34:02.55#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:34:02.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:34:02.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:34:02.55#ibcon#*before write, iclass 3, count 0 2006.257.12:34:02.55#ibcon#enter sib2, iclass 3, count 0 2006.257.12:34:02.55#ibcon#flushed, iclass 3, count 0 2006.257.12:34:02.55#ibcon#about to write, iclass 3, count 0 2006.257.12:34:02.55#ibcon#wrote, iclass 3, count 0 2006.257.12:34:02.55#ibcon#about to read 3, iclass 3, count 0 2006.257.12:34:02.59#ibcon#read 3, iclass 3, count 0 2006.257.12:34:02.59#ibcon#about to read 4, iclass 3, count 0 2006.257.12:34:02.59#ibcon#read 4, iclass 3, count 0 2006.257.12:34:02.59#ibcon#about to read 5, iclass 3, count 0 2006.257.12:34:02.59#ibcon#read 5, iclass 3, count 0 2006.257.12:34:02.59#ibcon#about to read 6, iclass 3, count 0 2006.257.12:34:02.59#ibcon#read 6, iclass 3, count 0 2006.257.12:34:02.59#ibcon#end of sib2, iclass 3, count 0 2006.257.12:34:02.59#ibcon#*after write, iclass 3, count 0 2006.257.12:34:02.59#ibcon#*before return 0, iclass 3, count 0 2006.257.12:34:02.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:02.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:02.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:34:02.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:34:02.59$vck44/va=2,7 2006.257.12:34:02.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.12:34:02.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.12:34:02.59#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:02.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:02.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:02.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:02.65#ibcon#enter wrdev, iclass 5, count 2 2006.257.12:34:02.65#ibcon#first serial, iclass 5, count 2 2006.257.12:34:02.65#ibcon#enter sib2, iclass 5, count 2 2006.257.12:34:02.65#ibcon#flushed, iclass 5, count 2 2006.257.12:34:02.65#ibcon#about to write, iclass 5, count 2 2006.257.12:34:02.65#ibcon#wrote, iclass 5, count 2 2006.257.12:34:02.65#ibcon#about to read 3, iclass 5, count 2 2006.257.12:34:02.67#ibcon#read 3, iclass 5, count 2 2006.257.12:34:02.67#ibcon#about to read 4, iclass 5, count 2 2006.257.12:34:02.67#ibcon#read 4, iclass 5, count 2 2006.257.12:34:02.67#ibcon#about to read 5, iclass 5, count 2 2006.257.12:34:02.67#ibcon#read 5, iclass 5, count 2 2006.257.12:34:02.67#ibcon#about to read 6, iclass 5, count 2 2006.257.12:34:02.67#ibcon#read 6, iclass 5, count 2 2006.257.12:34:02.67#ibcon#end of sib2, iclass 5, count 2 2006.257.12:34:02.67#ibcon#*mode == 0, iclass 5, count 2 2006.257.12:34:02.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.12:34:02.67#ibcon#[25=AT02-07\r\n] 2006.257.12:34:02.67#ibcon#*before write, iclass 5, count 2 2006.257.12:34:02.67#ibcon#enter sib2, iclass 5, count 2 2006.257.12:34:02.67#ibcon#flushed, iclass 5, count 2 2006.257.12:34:02.67#ibcon#about to write, iclass 5, count 2 2006.257.12:34:02.67#ibcon#wrote, iclass 5, count 2 2006.257.12:34:02.67#ibcon#about to read 3, iclass 5, count 2 2006.257.12:34:02.70#ibcon#read 3, iclass 5, count 2 2006.257.12:34:02.70#ibcon#about to read 4, iclass 5, count 2 2006.257.12:34:02.70#ibcon#read 4, iclass 5, count 2 2006.257.12:34:02.70#ibcon#about to read 5, iclass 5, count 2 2006.257.12:34:02.70#ibcon#read 5, iclass 5, count 2 2006.257.12:34:02.70#ibcon#about to read 6, iclass 5, count 2 2006.257.12:34:02.70#ibcon#read 6, iclass 5, count 2 2006.257.12:34:02.70#ibcon#end of sib2, iclass 5, count 2 2006.257.12:34:02.70#ibcon#*after write, iclass 5, count 2 2006.257.12:34:02.70#ibcon#*before return 0, iclass 5, count 2 2006.257.12:34:02.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:02.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:02.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.12:34:02.70#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:02.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:02.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:02.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:02.82#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:34:02.82#ibcon#first serial, iclass 5, count 0 2006.257.12:34:02.82#ibcon#enter sib2, iclass 5, count 0 2006.257.12:34:02.82#ibcon#flushed, iclass 5, count 0 2006.257.12:34:02.82#ibcon#about to write, iclass 5, count 0 2006.257.12:34:02.82#ibcon#wrote, iclass 5, count 0 2006.257.12:34:02.82#ibcon#about to read 3, iclass 5, count 0 2006.257.12:34:02.84#ibcon#read 3, iclass 5, count 0 2006.257.12:34:02.84#ibcon#about to read 4, iclass 5, count 0 2006.257.12:34:02.84#ibcon#read 4, iclass 5, count 0 2006.257.12:34:02.84#ibcon#about to read 5, iclass 5, count 0 2006.257.12:34:02.84#ibcon#read 5, iclass 5, count 0 2006.257.12:34:02.84#ibcon#about to read 6, iclass 5, count 0 2006.257.12:34:02.84#ibcon#read 6, iclass 5, count 0 2006.257.12:34:02.84#ibcon#end of sib2, iclass 5, count 0 2006.257.12:34:02.84#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:34:02.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:34:02.84#ibcon#[25=USB\r\n] 2006.257.12:34:02.84#ibcon#*before write, iclass 5, count 0 2006.257.12:34:02.84#ibcon#enter sib2, iclass 5, count 0 2006.257.12:34:02.84#ibcon#flushed, iclass 5, count 0 2006.257.12:34:02.84#ibcon#about to write, iclass 5, count 0 2006.257.12:34:02.84#ibcon#wrote, iclass 5, count 0 2006.257.12:34:02.84#ibcon#about to read 3, iclass 5, count 0 2006.257.12:34:02.87#ibcon#read 3, iclass 5, count 0 2006.257.12:34:02.87#ibcon#about to read 4, iclass 5, count 0 2006.257.12:34:02.87#ibcon#read 4, iclass 5, count 0 2006.257.12:34:02.87#ibcon#about to read 5, iclass 5, count 0 2006.257.12:34:02.87#ibcon#read 5, iclass 5, count 0 2006.257.12:34:02.87#ibcon#about to read 6, iclass 5, count 0 2006.257.12:34:02.87#ibcon#read 6, iclass 5, count 0 2006.257.12:34:02.87#ibcon#end of sib2, iclass 5, count 0 2006.257.12:34:02.87#ibcon#*after write, iclass 5, count 0 2006.257.12:34:02.87#ibcon#*before return 0, iclass 5, count 0 2006.257.12:34:02.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:02.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:02.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:34:02.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:34:02.87$vck44/valo=3,564.99 2006.257.12:34:02.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.12:34:02.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.12:34:02.87#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:02.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:02.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:02.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:02.87#ibcon#enter wrdev, iclass 7, count 0 2006.257.12:34:02.87#ibcon#first serial, iclass 7, count 0 2006.257.12:34:02.87#ibcon#enter sib2, iclass 7, count 0 2006.257.12:34:02.87#ibcon#flushed, iclass 7, count 0 2006.257.12:34:02.87#ibcon#about to write, iclass 7, count 0 2006.257.12:34:02.87#ibcon#wrote, iclass 7, count 0 2006.257.12:34:02.87#ibcon#about to read 3, iclass 7, count 0 2006.257.12:34:02.89#ibcon#read 3, iclass 7, count 0 2006.257.12:34:02.89#ibcon#about to read 4, iclass 7, count 0 2006.257.12:34:02.89#ibcon#read 4, iclass 7, count 0 2006.257.12:34:02.89#ibcon#about to read 5, iclass 7, count 0 2006.257.12:34:02.89#ibcon#read 5, iclass 7, count 0 2006.257.12:34:02.89#ibcon#about to read 6, iclass 7, count 0 2006.257.12:34:02.89#ibcon#read 6, iclass 7, count 0 2006.257.12:34:02.89#ibcon#end of sib2, iclass 7, count 0 2006.257.12:34:02.89#ibcon#*mode == 0, iclass 7, count 0 2006.257.12:34:02.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.12:34:02.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:34:02.89#ibcon#*before write, iclass 7, count 0 2006.257.12:34:02.89#ibcon#enter sib2, iclass 7, count 0 2006.257.12:34:02.89#ibcon#flushed, iclass 7, count 0 2006.257.12:34:02.89#ibcon#about to write, iclass 7, count 0 2006.257.12:34:02.89#ibcon#wrote, iclass 7, count 0 2006.257.12:34:02.89#ibcon#about to read 3, iclass 7, count 0 2006.257.12:34:02.93#ibcon#read 3, iclass 7, count 0 2006.257.12:34:02.93#ibcon#about to read 4, iclass 7, count 0 2006.257.12:34:02.93#ibcon#read 4, iclass 7, count 0 2006.257.12:34:02.93#ibcon#about to read 5, iclass 7, count 0 2006.257.12:34:02.93#ibcon#read 5, iclass 7, count 0 2006.257.12:34:02.93#ibcon#about to read 6, iclass 7, count 0 2006.257.12:34:02.93#ibcon#read 6, iclass 7, count 0 2006.257.12:34:02.93#ibcon#end of sib2, iclass 7, count 0 2006.257.12:34:02.93#ibcon#*after write, iclass 7, count 0 2006.257.12:34:02.93#ibcon#*before return 0, iclass 7, count 0 2006.257.12:34:02.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:02.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:02.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.12:34:02.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.12:34:02.93$vck44/va=3,8 2006.257.12:34:02.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.12:34:02.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.12:34:02.93#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:02.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:02.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:02.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:02.99#ibcon#enter wrdev, iclass 11, count 2 2006.257.12:34:02.99#ibcon#first serial, iclass 11, count 2 2006.257.12:34:02.99#ibcon#enter sib2, iclass 11, count 2 2006.257.12:34:02.99#ibcon#flushed, iclass 11, count 2 2006.257.12:34:02.99#ibcon#about to write, iclass 11, count 2 2006.257.12:34:02.99#ibcon#wrote, iclass 11, count 2 2006.257.12:34:02.99#ibcon#about to read 3, iclass 11, count 2 2006.257.12:34:03.01#ibcon#read 3, iclass 11, count 2 2006.257.12:34:03.01#ibcon#about to read 4, iclass 11, count 2 2006.257.12:34:03.01#ibcon#read 4, iclass 11, count 2 2006.257.12:34:03.01#ibcon#about to read 5, iclass 11, count 2 2006.257.12:34:03.01#ibcon#read 5, iclass 11, count 2 2006.257.12:34:03.01#ibcon#about to read 6, iclass 11, count 2 2006.257.12:34:03.01#ibcon#read 6, iclass 11, count 2 2006.257.12:34:03.01#ibcon#end of sib2, iclass 11, count 2 2006.257.12:34:03.01#ibcon#*mode == 0, iclass 11, count 2 2006.257.12:34:03.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.12:34:03.01#ibcon#[25=AT03-08\r\n] 2006.257.12:34:03.01#ibcon#*before write, iclass 11, count 2 2006.257.12:34:03.01#ibcon#enter sib2, iclass 11, count 2 2006.257.12:34:03.01#ibcon#flushed, iclass 11, count 2 2006.257.12:34:03.01#ibcon#about to write, iclass 11, count 2 2006.257.12:34:03.01#ibcon#wrote, iclass 11, count 2 2006.257.12:34:03.01#ibcon#about to read 3, iclass 11, count 2 2006.257.12:34:03.04#ibcon#read 3, iclass 11, count 2 2006.257.12:34:03.04#ibcon#about to read 4, iclass 11, count 2 2006.257.12:34:03.04#ibcon#read 4, iclass 11, count 2 2006.257.12:34:03.04#ibcon#about to read 5, iclass 11, count 2 2006.257.12:34:03.04#ibcon#read 5, iclass 11, count 2 2006.257.12:34:03.04#ibcon#about to read 6, iclass 11, count 2 2006.257.12:34:03.04#ibcon#read 6, iclass 11, count 2 2006.257.12:34:03.04#ibcon#end of sib2, iclass 11, count 2 2006.257.12:34:03.04#ibcon#*after write, iclass 11, count 2 2006.257.12:34:03.04#ibcon#*before return 0, iclass 11, count 2 2006.257.12:34:03.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:03.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:03.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.12:34:03.04#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:03.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:03.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:03.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:03.16#ibcon#enter wrdev, iclass 11, count 0 2006.257.12:34:03.16#ibcon#first serial, iclass 11, count 0 2006.257.12:34:03.16#ibcon#enter sib2, iclass 11, count 0 2006.257.12:34:03.16#ibcon#flushed, iclass 11, count 0 2006.257.12:34:03.16#ibcon#about to write, iclass 11, count 0 2006.257.12:34:03.16#ibcon#wrote, iclass 11, count 0 2006.257.12:34:03.16#ibcon#about to read 3, iclass 11, count 0 2006.257.12:34:03.18#ibcon#read 3, iclass 11, count 0 2006.257.12:34:03.18#ibcon#about to read 4, iclass 11, count 0 2006.257.12:34:03.18#ibcon#read 4, iclass 11, count 0 2006.257.12:34:03.18#ibcon#about to read 5, iclass 11, count 0 2006.257.12:34:03.18#ibcon#read 5, iclass 11, count 0 2006.257.12:34:03.18#ibcon#about to read 6, iclass 11, count 0 2006.257.12:34:03.18#ibcon#read 6, iclass 11, count 0 2006.257.12:34:03.18#ibcon#end of sib2, iclass 11, count 0 2006.257.12:34:03.18#ibcon#*mode == 0, iclass 11, count 0 2006.257.12:34:03.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.12:34:03.18#ibcon#[25=USB\r\n] 2006.257.12:34:03.18#ibcon#*before write, iclass 11, count 0 2006.257.12:34:03.18#ibcon#enter sib2, iclass 11, count 0 2006.257.12:34:03.18#ibcon#flushed, iclass 11, count 0 2006.257.12:34:03.18#ibcon#about to write, iclass 11, count 0 2006.257.12:34:03.18#ibcon#wrote, iclass 11, count 0 2006.257.12:34:03.18#ibcon#about to read 3, iclass 11, count 0 2006.257.12:34:03.21#ibcon#read 3, iclass 11, count 0 2006.257.12:34:03.21#ibcon#about to read 4, iclass 11, count 0 2006.257.12:34:03.21#ibcon#read 4, iclass 11, count 0 2006.257.12:34:03.21#ibcon#about to read 5, iclass 11, count 0 2006.257.12:34:03.21#ibcon#read 5, iclass 11, count 0 2006.257.12:34:03.21#ibcon#about to read 6, iclass 11, count 0 2006.257.12:34:03.21#ibcon#read 6, iclass 11, count 0 2006.257.12:34:03.21#ibcon#end of sib2, iclass 11, count 0 2006.257.12:34:03.21#ibcon#*after write, iclass 11, count 0 2006.257.12:34:03.21#ibcon#*before return 0, iclass 11, count 0 2006.257.12:34:03.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:03.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:03.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.12:34:03.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.12:34:03.21$vck44/valo=4,624.99 2006.257.12:34:03.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.12:34:03.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.12:34:03.21#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:03.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:34:03.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:34:03.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:34:03.21#ibcon#enter wrdev, iclass 13, count 0 2006.257.12:34:03.21#ibcon#first serial, iclass 13, count 0 2006.257.12:34:03.21#ibcon#enter sib2, iclass 13, count 0 2006.257.12:34:03.21#ibcon#flushed, iclass 13, count 0 2006.257.12:34:03.21#ibcon#about to write, iclass 13, count 0 2006.257.12:34:03.21#ibcon#wrote, iclass 13, count 0 2006.257.12:34:03.21#ibcon#about to read 3, iclass 13, count 0 2006.257.12:34:03.23#ibcon#read 3, iclass 13, count 0 2006.257.12:34:03.23#ibcon#about to read 4, iclass 13, count 0 2006.257.12:34:03.23#ibcon#read 4, iclass 13, count 0 2006.257.12:34:03.23#ibcon#about to read 5, iclass 13, count 0 2006.257.12:34:03.23#ibcon#read 5, iclass 13, count 0 2006.257.12:34:03.23#ibcon#about to read 6, iclass 13, count 0 2006.257.12:34:03.23#ibcon#read 6, iclass 13, count 0 2006.257.12:34:03.23#ibcon#end of sib2, iclass 13, count 0 2006.257.12:34:03.23#ibcon#*mode == 0, iclass 13, count 0 2006.257.12:34:03.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.12:34:03.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:34:03.23#ibcon#*before write, iclass 13, count 0 2006.257.12:34:03.23#ibcon#enter sib2, iclass 13, count 0 2006.257.12:34:03.23#ibcon#flushed, iclass 13, count 0 2006.257.12:34:03.23#ibcon#about to write, iclass 13, count 0 2006.257.12:34:03.23#ibcon#wrote, iclass 13, count 0 2006.257.12:34:03.23#ibcon#about to read 3, iclass 13, count 0 2006.257.12:34:03.27#ibcon#read 3, iclass 13, count 0 2006.257.12:34:03.27#ibcon#about to read 4, iclass 13, count 0 2006.257.12:34:03.27#ibcon#read 4, iclass 13, count 0 2006.257.12:34:03.27#ibcon#about to read 5, iclass 13, count 0 2006.257.12:34:03.27#ibcon#read 5, iclass 13, count 0 2006.257.12:34:03.27#ibcon#about to read 6, iclass 13, count 0 2006.257.12:34:03.27#ibcon#read 6, iclass 13, count 0 2006.257.12:34:03.27#ibcon#end of sib2, iclass 13, count 0 2006.257.12:34:03.27#ibcon#*after write, iclass 13, count 0 2006.257.12:34:03.27#ibcon#*before return 0, iclass 13, count 0 2006.257.12:34:03.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:34:03.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:34:03.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.12:34:03.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.12:34:03.27$vck44/va=4,7 2006.257.12:34:03.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.12:34:03.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.12:34:03.27#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:03.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:34:03.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:34:03.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:34:03.33#ibcon#enter wrdev, iclass 15, count 2 2006.257.12:34:03.33#ibcon#first serial, iclass 15, count 2 2006.257.12:34:03.33#ibcon#enter sib2, iclass 15, count 2 2006.257.12:34:03.33#ibcon#flushed, iclass 15, count 2 2006.257.12:34:03.33#ibcon#about to write, iclass 15, count 2 2006.257.12:34:03.33#ibcon#wrote, iclass 15, count 2 2006.257.12:34:03.33#ibcon#about to read 3, iclass 15, count 2 2006.257.12:34:03.35#ibcon#read 3, iclass 15, count 2 2006.257.12:34:03.35#ibcon#about to read 4, iclass 15, count 2 2006.257.12:34:03.35#ibcon#read 4, iclass 15, count 2 2006.257.12:34:03.35#ibcon#about to read 5, iclass 15, count 2 2006.257.12:34:03.35#ibcon#read 5, iclass 15, count 2 2006.257.12:34:03.35#ibcon#about to read 6, iclass 15, count 2 2006.257.12:34:03.35#ibcon#read 6, iclass 15, count 2 2006.257.12:34:03.35#ibcon#end of sib2, iclass 15, count 2 2006.257.12:34:03.35#ibcon#*mode == 0, iclass 15, count 2 2006.257.12:34:03.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.12:34:03.35#ibcon#[25=AT04-07\r\n] 2006.257.12:34:03.35#ibcon#*before write, iclass 15, count 2 2006.257.12:34:03.35#ibcon#enter sib2, iclass 15, count 2 2006.257.12:34:03.35#ibcon#flushed, iclass 15, count 2 2006.257.12:34:03.35#ibcon#about to write, iclass 15, count 2 2006.257.12:34:03.35#ibcon#wrote, iclass 15, count 2 2006.257.12:34:03.35#ibcon#about to read 3, iclass 15, count 2 2006.257.12:34:03.38#ibcon#read 3, iclass 15, count 2 2006.257.12:34:03.38#ibcon#about to read 4, iclass 15, count 2 2006.257.12:34:03.38#ibcon#read 4, iclass 15, count 2 2006.257.12:34:03.38#ibcon#about to read 5, iclass 15, count 2 2006.257.12:34:03.38#ibcon#read 5, iclass 15, count 2 2006.257.12:34:03.38#ibcon#about to read 6, iclass 15, count 2 2006.257.12:34:03.38#ibcon#read 6, iclass 15, count 2 2006.257.12:34:03.38#ibcon#end of sib2, iclass 15, count 2 2006.257.12:34:03.38#ibcon#*after write, iclass 15, count 2 2006.257.12:34:03.38#ibcon#*before return 0, iclass 15, count 2 2006.257.12:34:03.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:34:03.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:34:03.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.12:34:03.45#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:03.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:34:03.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:34:03.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:34:03.57#ibcon#enter wrdev, iclass 15, count 0 2006.257.12:34:03.57#ibcon#first serial, iclass 15, count 0 2006.257.12:34:03.57#ibcon#enter sib2, iclass 15, count 0 2006.257.12:34:03.57#ibcon#flushed, iclass 15, count 0 2006.257.12:34:03.57#ibcon#about to write, iclass 15, count 0 2006.257.12:34:03.57#ibcon#wrote, iclass 15, count 0 2006.257.12:34:03.57#ibcon#about to read 3, iclass 15, count 0 2006.257.12:34:03.59#ibcon#read 3, iclass 15, count 0 2006.257.12:34:03.59#ibcon#about to read 4, iclass 15, count 0 2006.257.12:34:03.59#ibcon#read 4, iclass 15, count 0 2006.257.12:34:03.59#ibcon#about to read 5, iclass 15, count 0 2006.257.12:34:03.59#ibcon#read 5, iclass 15, count 0 2006.257.12:34:03.59#ibcon#about to read 6, iclass 15, count 0 2006.257.12:34:03.59#ibcon#read 6, iclass 15, count 0 2006.257.12:34:03.59#ibcon#end of sib2, iclass 15, count 0 2006.257.12:34:03.59#ibcon#*mode == 0, iclass 15, count 0 2006.257.12:34:03.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.12:34:03.59#ibcon#[25=USB\r\n] 2006.257.12:34:03.59#ibcon#*before write, iclass 15, count 0 2006.257.12:34:03.59#ibcon#enter sib2, iclass 15, count 0 2006.257.12:34:03.59#ibcon#flushed, iclass 15, count 0 2006.257.12:34:03.59#ibcon#about to write, iclass 15, count 0 2006.257.12:34:03.59#ibcon#wrote, iclass 15, count 0 2006.257.12:34:03.59#ibcon#about to read 3, iclass 15, count 0 2006.257.12:34:03.62#ibcon#read 3, iclass 15, count 0 2006.257.12:34:03.62#ibcon#about to read 4, iclass 15, count 0 2006.257.12:34:03.62#ibcon#read 4, iclass 15, count 0 2006.257.12:34:03.62#ibcon#about to read 5, iclass 15, count 0 2006.257.12:34:03.62#ibcon#read 5, iclass 15, count 0 2006.257.12:34:03.62#ibcon#about to read 6, iclass 15, count 0 2006.257.12:34:03.62#ibcon#read 6, iclass 15, count 0 2006.257.12:34:03.62#ibcon#end of sib2, iclass 15, count 0 2006.257.12:34:03.62#ibcon#*after write, iclass 15, count 0 2006.257.12:34:03.62#ibcon#*before return 0, iclass 15, count 0 2006.257.12:34:03.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:34:03.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:34:03.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.12:34:03.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.12:34:03.62$vck44/valo=5,734.99 2006.257.12:34:03.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.12:34:03.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.12:34:03.62#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:03.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:03.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:03.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:03.62#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:34:03.62#ibcon#first serial, iclass 17, count 0 2006.257.12:34:03.62#ibcon#enter sib2, iclass 17, count 0 2006.257.12:34:03.62#ibcon#flushed, iclass 17, count 0 2006.257.12:34:03.62#ibcon#about to write, iclass 17, count 0 2006.257.12:34:03.62#ibcon#wrote, iclass 17, count 0 2006.257.12:34:03.62#ibcon#about to read 3, iclass 17, count 0 2006.257.12:34:03.64#ibcon#read 3, iclass 17, count 0 2006.257.12:34:03.64#ibcon#about to read 4, iclass 17, count 0 2006.257.12:34:03.64#ibcon#read 4, iclass 17, count 0 2006.257.12:34:03.64#ibcon#about to read 5, iclass 17, count 0 2006.257.12:34:03.64#ibcon#read 5, iclass 17, count 0 2006.257.12:34:03.64#ibcon#about to read 6, iclass 17, count 0 2006.257.12:34:03.64#ibcon#read 6, iclass 17, count 0 2006.257.12:34:03.64#ibcon#end of sib2, iclass 17, count 0 2006.257.12:34:03.64#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:34:03.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:34:03.64#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:34:03.64#ibcon#*before write, iclass 17, count 0 2006.257.12:34:03.64#ibcon#enter sib2, iclass 17, count 0 2006.257.12:34:03.64#ibcon#flushed, iclass 17, count 0 2006.257.12:34:03.64#ibcon#about to write, iclass 17, count 0 2006.257.12:34:03.64#ibcon#wrote, iclass 17, count 0 2006.257.12:34:03.64#ibcon#about to read 3, iclass 17, count 0 2006.257.12:34:03.68#ibcon#read 3, iclass 17, count 0 2006.257.12:34:03.68#ibcon#about to read 4, iclass 17, count 0 2006.257.12:34:03.68#ibcon#read 4, iclass 17, count 0 2006.257.12:34:03.68#ibcon#about to read 5, iclass 17, count 0 2006.257.12:34:03.68#ibcon#read 5, iclass 17, count 0 2006.257.12:34:03.68#ibcon#about to read 6, iclass 17, count 0 2006.257.12:34:03.68#ibcon#read 6, iclass 17, count 0 2006.257.12:34:03.68#ibcon#end of sib2, iclass 17, count 0 2006.257.12:34:03.68#ibcon#*after write, iclass 17, count 0 2006.257.12:34:03.68#ibcon#*before return 0, iclass 17, count 0 2006.257.12:34:03.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:03.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:03.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:34:03.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:34:03.68$vck44/va=5,4 2006.257.12:34:03.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.12:34:03.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.12:34:03.68#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:03.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:03.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:03.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:03.74#ibcon#enter wrdev, iclass 19, count 2 2006.257.12:34:03.74#ibcon#first serial, iclass 19, count 2 2006.257.12:34:03.74#ibcon#enter sib2, iclass 19, count 2 2006.257.12:34:03.74#ibcon#flushed, iclass 19, count 2 2006.257.12:34:03.74#ibcon#about to write, iclass 19, count 2 2006.257.12:34:03.74#ibcon#wrote, iclass 19, count 2 2006.257.12:34:03.74#ibcon#about to read 3, iclass 19, count 2 2006.257.12:34:03.76#ibcon#read 3, iclass 19, count 2 2006.257.12:34:03.76#ibcon#about to read 4, iclass 19, count 2 2006.257.12:34:03.76#ibcon#read 4, iclass 19, count 2 2006.257.12:34:03.76#ibcon#about to read 5, iclass 19, count 2 2006.257.12:34:03.76#ibcon#read 5, iclass 19, count 2 2006.257.12:34:03.76#ibcon#about to read 6, iclass 19, count 2 2006.257.12:34:03.76#ibcon#read 6, iclass 19, count 2 2006.257.12:34:03.76#ibcon#end of sib2, iclass 19, count 2 2006.257.12:34:03.76#ibcon#*mode == 0, iclass 19, count 2 2006.257.12:34:03.76#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.12:34:03.76#ibcon#[25=AT05-04\r\n] 2006.257.12:34:03.76#ibcon#*before write, iclass 19, count 2 2006.257.12:34:03.76#ibcon#enter sib2, iclass 19, count 2 2006.257.12:34:03.76#ibcon#flushed, iclass 19, count 2 2006.257.12:34:03.76#ibcon#about to write, iclass 19, count 2 2006.257.12:34:03.76#ibcon#wrote, iclass 19, count 2 2006.257.12:34:03.76#ibcon#about to read 3, iclass 19, count 2 2006.257.12:34:03.79#ibcon#read 3, iclass 19, count 2 2006.257.12:34:03.79#ibcon#about to read 4, iclass 19, count 2 2006.257.12:34:03.79#ibcon#read 4, iclass 19, count 2 2006.257.12:34:03.79#ibcon#about to read 5, iclass 19, count 2 2006.257.12:34:03.79#ibcon#read 5, iclass 19, count 2 2006.257.12:34:03.79#ibcon#about to read 6, iclass 19, count 2 2006.257.12:34:03.79#ibcon#read 6, iclass 19, count 2 2006.257.12:34:03.79#ibcon#end of sib2, iclass 19, count 2 2006.257.12:34:03.79#ibcon#*after write, iclass 19, count 2 2006.257.12:34:03.79#ibcon#*before return 0, iclass 19, count 2 2006.257.12:34:03.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:03.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:03.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.12:34:03.79#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:03.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:03.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:03.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:03.91#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:34:03.91#ibcon#first serial, iclass 19, count 0 2006.257.12:34:03.91#ibcon#enter sib2, iclass 19, count 0 2006.257.12:34:03.91#ibcon#flushed, iclass 19, count 0 2006.257.12:34:03.91#ibcon#about to write, iclass 19, count 0 2006.257.12:34:03.91#ibcon#wrote, iclass 19, count 0 2006.257.12:34:03.91#ibcon#about to read 3, iclass 19, count 0 2006.257.12:34:03.93#ibcon#read 3, iclass 19, count 0 2006.257.12:34:03.93#ibcon#about to read 4, iclass 19, count 0 2006.257.12:34:03.93#ibcon#read 4, iclass 19, count 0 2006.257.12:34:03.93#ibcon#about to read 5, iclass 19, count 0 2006.257.12:34:03.93#ibcon#read 5, iclass 19, count 0 2006.257.12:34:03.93#ibcon#about to read 6, iclass 19, count 0 2006.257.12:34:03.93#ibcon#read 6, iclass 19, count 0 2006.257.12:34:03.93#ibcon#end of sib2, iclass 19, count 0 2006.257.12:34:03.93#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:34:03.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:34:03.93#ibcon#[25=USB\r\n] 2006.257.12:34:03.93#ibcon#*before write, iclass 19, count 0 2006.257.12:34:03.93#ibcon#enter sib2, iclass 19, count 0 2006.257.12:34:03.93#ibcon#flushed, iclass 19, count 0 2006.257.12:34:03.93#ibcon#about to write, iclass 19, count 0 2006.257.12:34:03.93#ibcon#wrote, iclass 19, count 0 2006.257.12:34:03.93#ibcon#about to read 3, iclass 19, count 0 2006.257.12:34:03.96#ibcon#read 3, iclass 19, count 0 2006.257.12:34:03.96#ibcon#about to read 4, iclass 19, count 0 2006.257.12:34:03.96#ibcon#read 4, iclass 19, count 0 2006.257.12:34:03.96#ibcon#about to read 5, iclass 19, count 0 2006.257.12:34:03.96#ibcon#read 5, iclass 19, count 0 2006.257.12:34:03.96#ibcon#about to read 6, iclass 19, count 0 2006.257.12:34:03.96#ibcon#read 6, iclass 19, count 0 2006.257.12:34:03.96#ibcon#end of sib2, iclass 19, count 0 2006.257.12:34:03.96#ibcon#*after write, iclass 19, count 0 2006.257.12:34:03.96#ibcon#*before return 0, iclass 19, count 0 2006.257.12:34:03.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:03.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:03.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:34:03.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:34:03.96$vck44/valo=6,814.99 2006.257.12:34:03.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.12:34:03.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.12:34:03.96#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:03.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:03.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:03.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:03.96#ibcon#enter wrdev, iclass 21, count 0 2006.257.12:34:03.96#ibcon#first serial, iclass 21, count 0 2006.257.12:34:03.96#ibcon#enter sib2, iclass 21, count 0 2006.257.12:34:03.96#ibcon#flushed, iclass 21, count 0 2006.257.12:34:03.96#ibcon#about to write, iclass 21, count 0 2006.257.12:34:03.96#ibcon#wrote, iclass 21, count 0 2006.257.12:34:03.96#ibcon#about to read 3, iclass 21, count 0 2006.257.12:34:03.98#ibcon#read 3, iclass 21, count 0 2006.257.12:34:03.98#ibcon#about to read 4, iclass 21, count 0 2006.257.12:34:03.98#ibcon#read 4, iclass 21, count 0 2006.257.12:34:03.98#ibcon#about to read 5, iclass 21, count 0 2006.257.12:34:03.98#ibcon#read 5, iclass 21, count 0 2006.257.12:34:03.98#ibcon#about to read 6, iclass 21, count 0 2006.257.12:34:03.98#ibcon#read 6, iclass 21, count 0 2006.257.12:34:03.98#ibcon#end of sib2, iclass 21, count 0 2006.257.12:34:03.98#ibcon#*mode == 0, iclass 21, count 0 2006.257.12:34:03.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.12:34:03.98#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:34:03.98#ibcon#*before write, iclass 21, count 0 2006.257.12:34:03.98#ibcon#enter sib2, iclass 21, count 0 2006.257.12:34:03.98#ibcon#flushed, iclass 21, count 0 2006.257.12:34:03.98#ibcon#about to write, iclass 21, count 0 2006.257.12:34:03.98#ibcon#wrote, iclass 21, count 0 2006.257.12:34:03.98#ibcon#about to read 3, iclass 21, count 0 2006.257.12:34:04.02#ibcon#read 3, iclass 21, count 0 2006.257.12:34:04.02#ibcon#about to read 4, iclass 21, count 0 2006.257.12:34:04.02#ibcon#read 4, iclass 21, count 0 2006.257.12:34:04.02#ibcon#about to read 5, iclass 21, count 0 2006.257.12:34:04.02#ibcon#read 5, iclass 21, count 0 2006.257.12:34:04.02#ibcon#about to read 6, iclass 21, count 0 2006.257.12:34:04.02#ibcon#read 6, iclass 21, count 0 2006.257.12:34:04.02#ibcon#end of sib2, iclass 21, count 0 2006.257.12:34:04.02#ibcon#*after write, iclass 21, count 0 2006.257.12:34:04.02#ibcon#*before return 0, iclass 21, count 0 2006.257.12:34:04.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:04.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:04.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.12:34:04.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.12:34:04.02$vck44/va=6,4 2006.257.12:34:04.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.12:34:04.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.12:34:04.02#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:04.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:04.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:04.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:04.08#ibcon#enter wrdev, iclass 23, count 2 2006.257.12:34:04.08#ibcon#first serial, iclass 23, count 2 2006.257.12:34:04.08#ibcon#enter sib2, iclass 23, count 2 2006.257.12:34:04.08#ibcon#flushed, iclass 23, count 2 2006.257.12:34:04.08#ibcon#about to write, iclass 23, count 2 2006.257.12:34:04.08#ibcon#wrote, iclass 23, count 2 2006.257.12:34:04.08#ibcon#about to read 3, iclass 23, count 2 2006.257.12:34:04.10#ibcon#read 3, iclass 23, count 2 2006.257.12:34:04.10#ibcon#about to read 4, iclass 23, count 2 2006.257.12:34:04.10#ibcon#read 4, iclass 23, count 2 2006.257.12:34:04.10#ibcon#about to read 5, iclass 23, count 2 2006.257.12:34:04.10#ibcon#read 5, iclass 23, count 2 2006.257.12:34:04.10#ibcon#about to read 6, iclass 23, count 2 2006.257.12:34:04.10#ibcon#read 6, iclass 23, count 2 2006.257.12:34:04.10#ibcon#end of sib2, iclass 23, count 2 2006.257.12:34:04.10#ibcon#*mode == 0, iclass 23, count 2 2006.257.12:34:04.10#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.12:34:04.10#ibcon#[25=AT06-04\r\n] 2006.257.12:34:04.10#ibcon#*before write, iclass 23, count 2 2006.257.12:34:04.10#ibcon#enter sib2, iclass 23, count 2 2006.257.12:34:04.10#ibcon#flushed, iclass 23, count 2 2006.257.12:34:04.10#ibcon#about to write, iclass 23, count 2 2006.257.12:34:04.10#ibcon#wrote, iclass 23, count 2 2006.257.12:34:04.10#ibcon#about to read 3, iclass 23, count 2 2006.257.12:34:04.13#ibcon#read 3, iclass 23, count 2 2006.257.12:34:04.13#ibcon#about to read 4, iclass 23, count 2 2006.257.12:34:04.13#ibcon#read 4, iclass 23, count 2 2006.257.12:34:04.13#ibcon#about to read 5, iclass 23, count 2 2006.257.12:34:04.13#ibcon#read 5, iclass 23, count 2 2006.257.12:34:04.13#ibcon#about to read 6, iclass 23, count 2 2006.257.12:34:04.13#ibcon#read 6, iclass 23, count 2 2006.257.12:34:04.13#ibcon#end of sib2, iclass 23, count 2 2006.257.12:34:04.13#ibcon#*after write, iclass 23, count 2 2006.257.12:34:04.13#ibcon#*before return 0, iclass 23, count 2 2006.257.12:34:04.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:04.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:04.13#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.12:34:04.13#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:04.13#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:04.25#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:04.25#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:04.25#ibcon#enter wrdev, iclass 23, count 0 2006.257.12:34:04.25#ibcon#first serial, iclass 23, count 0 2006.257.12:34:04.25#ibcon#enter sib2, iclass 23, count 0 2006.257.12:34:04.25#ibcon#flushed, iclass 23, count 0 2006.257.12:34:04.25#ibcon#about to write, iclass 23, count 0 2006.257.12:34:04.25#ibcon#wrote, iclass 23, count 0 2006.257.12:34:04.25#ibcon#about to read 3, iclass 23, count 0 2006.257.12:34:04.27#ibcon#read 3, iclass 23, count 0 2006.257.12:34:04.27#ibcon#about to read 4, iclass 23, count 0 2006.257.12:34:04.27#ibcon#read 4, iclass 23, count 0 2006.257.12:34:04.27#ibcon#about to read 5, iclass 23, count 0 2006.257.12:34:04.27#ibcon#read 5, iclass 23, count 0 2006.257.12:34:04.27#ibcon#about to read 6, iclass 23, count 0 2006.257.12:34:04.27#ibcon#read 6, iclass 23, count 0 2006.257.12:34:04.27#ibcon#end of sib2, iclass 23, count 0 2006.257.12:34:04.27#ibcon#*mode == 0, iclass 23, count 0 2006.257.12:34:04.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.12:34:04.27#ibcon#[25=USB\r\n] 2006.257.12:34:04.27#ibcon#*before write, iclass 23, count 0 2006.257.12:34:04.27#ibcon#enter sib2, iclass 23, count 0 2006.257.12:34:04.27#ibcon#flushed, iclass 23, count 0 2006.257.12:34:04.27#ibcon#about to write, iclass 23, count 0 2006.257.12:34:04.27#ibcon#wrote, iclass 23, count 0 2006.257.12:34:04.27#ibcon#about to read 3, iclass 23, count 0 2006.257.12:34:04.30#ibcon#read 3, iclass 23, count 0 2006.257.12:34:04.30#ibcon#about to read 4, iclass 23, count 0 2006.257.12:34:04.30#ibcon#read 4, iclass 23, count 0 2006.257.12:34:04.30#ibcon#about to read 5, iclass 23, count 0 2006.257.12:34:04.30#ibcon#read 5, iclass 23, count 0 2006.257.12:34:04.30#ibcon#about to read 6, iclass 23, count 0 2006.257.12:34:04.30#ibcon#read 6, iclass 23, count 0 2006.257.12:34:04.30#ibcon#end of sib2, iclass 23, count 0 2006.257.12:34:04.30#ibcon#*after write, iclass 23, count 0 2006.257.12:34:04.30#ibcon#*before return 0, iclass 23, count 0 2006.257.12:34:04.30#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:04.30#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:04.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.12:34:04.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.12:34:04.30$vck44/valo=7,864.99 2006.257.12:34:04.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.12:34:04.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.12:34:04.30#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:04.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:04.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:04.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:04.30#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:34:04.30#ibcon#first serial, iclass 25, count 0 2006.257.12:34:04.30#ibcon#enter sib2, iclass 25, count 0 2006.257.12:34:04.30#ibcon#flushed, iclass 25, count 0 2006.257.12:34:04.30#ibcon#about to write, iclass 25, count 0 2006.257.12:34:04.30#ibcon#wrote, iclass 25, count 0 2006.257.12:34:04.30#ibcon#about to read 3, iclass 25, count 0 2006.257.12:34:04.32#ibcon#read 3, iclass 25, count 0 2006.257.12:34:04.32#ibcon#about to read 4, iclass 25, count 0 2006.257.12:34:04.32#ibcon#read 4, iclass 25, count 0 2006.257.12:34:04.32#ibcon#about to read 5, iclass 25, count 0 2006.257.12:34:04.32#ibcon#read 5, iclass 25, count 0 2006.257.12:34:04.32#ibcon#about to read 6, iclass 25, count 0 2006.257.12:34:04.32#ibcon#read 6, iclass 25, count 0 2006.257.12:34:04.32#ibcon#end of sib2, iclass 25, count 0 2006.257.12:34:04.32#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:34:04.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:34:04.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:34:04.32#ibcon#*before write, iclass 25, count 0 2006.257.12:34:04.32#ibcon#enter sib2, iclass 25, count 0 2006.257.12:34:04.32#ibcon#flushed, iclass 25, count 0 2006.257.12:34:04.32#ibcon#about to write, iclass 25, count 0 2006.257.12:34:04.32#ibcon#wrote, iclass 25, count 0 2006.257.12:34:04.32#ibcon#about to read 3, iclass 25, count 0 2006.257.12:34:04.36#ibcon#read 3, iclass 25, count 0 2006.257.12:34:04.36#ibcon#about to read 4, iclass 25, count 0 2006.257.12:34:04.36#ibcon#read 4, iclass 25, count 0 2006.257.12:34:04.36#ibcon#about to read 5, iclass 25, count 0 2006.257.12:34:04.36#ibcon#read 5, iclass 25, count 0 2006.257.12:34:04.36#ibcon#about to read 6, iclass 25, count 0 2006.257.12:34:04.36#ibcon#read 6, iclass 25, count 0 2006.257.12:34:04.36#ibcon#end of sib2, iclass 25, count 0 2006.257.12:34:04.36#ibcon#*after write, iclass 25, count 0 2006.257.12:34:04.36#ibcon#*before return 0, iclass 25, count 0 2006.257.12:34:04.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:04.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:04.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:34:04.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:34:04.36$vck44/va=7,4 2006.257.12:34:04.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.12:34:04.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.12:34:04.36#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:04.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:04.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:04.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:04.42#ibcon#enter wrdev, iclass 27, count 2 2006.257.12:34:04.42#ibcon#first serial, iclass 27, count 2 2006.257.12:34:04.42#ibcon#enter sib2, iclass 27, count 2 2006.257.12:34:04.42#ibcon#flushed, iclass 27, count 2 2006.257.12:34:04.42#ibcon#about to write, iclass 27, count 2 2006.257.12:34:04.42#ibcon#wrote, iclass 27, count 2 2006.257.12:34:04.42#ibcon#about to read 3, iclass 27, count 2 2006.257.12:34:04.44#ibcon#read 3, iclass 27, count 2 2006.257.12:34:04.44#ibcon#about to read 4, iclass 27, count 2 2006.257.12:34:04.44#ibcon#read 4, iclass 27, count 2 2006.257.12:34:04.44#ibcon#about to read 5, iclass 27, count 2 2006.257.12:34:04.44#ibcon#read 5, iclass 27, count 2 2006.257.12:34:04.44#ibcon#about to read 6, iclass 27, count 2 2006.257.12:34:04.44#ibcon#read 6, iclass 27, count 2 2006.257.12:34:04.44#ibcon#end of sib2, iclass 27, count 2 2006.257.12:34:04.44#ibcon#*mode == 0, iclass 27, count 2 2006.257.12:34:04.44#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.12:34:04.44#ibcon#[25=AT07-04\r\n] 2006.257.12:34:04.44#ibcon#*before write, iclass 27, count 2 2006.257.12:34:04.44#ibcon#enter sib2, iclass 27, count 2 2006.257.12:34:04.44#ibcon#flushed, iclass 27, count 2 2006.257.12:34:04.44#ibcon#about to write, iclass 27, count 2 2006.257.12:34:04.44#ibcon#wrote, iclass 27, count 2 2006.257.12:34:04.44#ibcon#about to read 3, iclass 27, count 2 2006.257.12:34:04.47#ibcon#read 3, iclass 27, count 2 2006.257.12:34:04.47#ibcon#about to read 4, iclass 27, count 2 2006.257.12:34:04.47#ibcon#read 4, iclass 27, count 2 2006.257.12:34:04.47#ibcon#about to read 5, iclass 27, count 2 2006.257.12:34:04.47#ibcon#read 5, iclass 27, count 2 2006.257.12:34:04.47#ibcon#about to read 6, iclass 27, count 2 2006.257.12:34:04.47#ibcon#read 6, iclass 27, count 2 2006.257.12:34:04.47#ibcon#end of sib2, iclass 27, count 2 2006.257.12:34:04.47#ibcon#*after write, iclass 27, count 2 2006.257.12:34:04.47#ibcon#*before return 0, iclass 27, count 2 2006.257.12:34:04.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:04.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:04.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.12:34:04.47#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:04.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:04.59#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:04.59#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:04.59#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:34:04.59#ibcon#first serial, iclass 27, count 0 2006.257.12:34:04.59#ibcon#enter sib2, iclass 27, count 0 2006.257.12:34:04.59#ibcon#flushed, iclass 27, count 0 2006.257.12:34:04.59#ibcon#about to write, iclass 27, count 0 2006.257.12:34:04.59#ibcon#wrote, iclass 27, count 0 2006.257.12:34:04.59#ibcon#about to read 3, iclass 27, count 0 2006.257.12:34:04.61#ibcon#read 3, iclass 27, count 0 2006.257.12:34:04.61#ibcon#about to read 4, iclass 27, count 0 2006.257.12:34:04.61#ibcon#read 4, iclass 27, count 0 2006.257.12:34:04.61#ibcon#about to read 5, iclass 27, count 0 2006.257.12:34:04.61#ibcon#read 5, iclass 27, count 0 2006.257.12:34:04.61#ibcon#about to read 6, iclass 27, count 0 2006.257.12:34:04.61#ibcon#read 6, iclass 27, count 0 2006.257.12:34:04.61#ibcon#end of sib2, iclass 27, count 0 2006.257.12:34:04.61#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:34:04.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:34:04.61#ibcon#[25=USB\r\n] 2006.257.12:34:04.61#ibcon#*before write, iclass 27, count 0 2006.257.12:34:04.61#ibcon#enter sib2, iclass 27, count 0 2006.257.12:34:04.61#ibcon#flushed, iclass 27, count 0 2006.257.12:34:04.61#ibcon#about to write, iclass 27, count 0 2006.257.12:34:04.61#ibcon#wrote, iclass 27, count 0 2006.257.12:34:04.61#ibcon#about to read 3, iclass 27, count 0 2006.257.12:34:04.64#ibcon#read 3, iclass 27, count 0 2006.257.12:34:04.64#ibcon#about to read 4, iclass 27, count 0 2006.257.12:34:04.64#ibcon#read 4, iclass 27, count 0 2006.257.12:34:04.64#ibcon#about to read 5, iclass 27, count 0 2006.257.12:34:04.64#ibcon#read 5, iclass 27, count 0 2006.257.12:34:04.64#ibcon#about to read 6, iclass 27, count 0 2006.257.12:34:04.64#ibcon#read 6, iclass 27, count 0 2006.257.12:34:04.64#ibcon#end of sib2, iclass 27, count 0 2006.257.12:34:04.64#ibcon#*after write, iclass 27, count 0 2006.257.12:34:04.64#ibcon#*before return 0, iclass 27, count 0 2006.257.12:34:04.64#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:04.64#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:04.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:34:04.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:34:04.64$vck44/valo=8,884.99 2006.257.12:34:04.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.12:34:04.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.12:34:04.64#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:04.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:04.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:04.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:04.64#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:34:04.64#ibcon#first serial, iclass 29, count 0 2006.257.12:34:04.64#ibcon#enter sib2, iclass 29, count 0 2006.257.12:34:04.64#ibcon#flushed, iclass 29, count 0 2006.257.12:34:04.64#ibcon#about to write, iclass 29, count 0 2006.257.12:34:04.64#ibcon#wrote, iclass 29, count 0 2006.257.12:34:04.64#ibcon#about to read 3, iclass 29, count 0 2006.257.12:34:04.66#ibcon#read 3, iclass 29, count 0 2006.257.12:34:04.66#ibcon#about to read 4, iclass 29, count 0 2006.257.12:34:04.66#ibcon#read 4, iclass 29, count 0 2006.257.12:34:04.66#ibcon#about to read 5, iclass 29, count 0 2006.257.12:34:04.66#ibcon#read 5, iclass 29, count 0 2006.257.12:34:04.66#ibcon#about to read 6, iclass 29, count 0 2006.257.12:34:04.66#ibcon#read 6, iclass 29, count 0 2006.257.12:34:04.66#ibcon#end of sib2, iclass 29, count 0 2006.257.12:34:04.66#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:34:04.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:34:04.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:34:04.66#ibcon#*before write, iclass 29, count 0 2006.257.12:34:04.66#ibcon#enter sib2, iclass 29, count 0 2006.257.12:34:04.66#ibcon#flushed, iclass 29, count 0 2006.257.12:34:04.66#ibcon#about to write, iclass 29, count 0 2006.257.12:34:04.66#ibcon#wrote, iclass 29, count 0 2006.257.12:34:04.66#ibcon#about to read 3, iclass 29, count 0 2006.257.12:34:04.70#ibcon#read 3, iclass 29, count 0 2006.257.12:34:04.70#ibcon#about to read 4, iclass 29, count 0 2006.257.12:34:04.70#ibcon#read 4, iclass 29, count 0 2006.257.12:34:04.70#ibcon#about to read 5, iclass 29, count 0 2006.257.12:34:04.70#ibcon#read 5, iclass 29, count 0 2006.257.12:34:04.70#ibcon#about to read 6, iclass 29, count 0 2006.257.12:34:04.70#ibcon#read 6, iclass 29, count 0 2006.257.12:34:04.70#ibcon#end of sib2, iclass 29, count 0 2006.257.12:34:04.70#ibcon#*after write, iclass 29, count 0 2006.257.12:34:04.70#ibcon#*before return 0, iclass 29, count 0 2006.257.12:34:04.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:04.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:04.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:34:04.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:34:04.70$vck44/va=8,4 2006.257.12:34:04.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.12:34:04.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.12:34:04.70#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:04.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:04.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:04.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:04.76#ibcon#enter wrdev, iclass 31, count 2 2006.257.12:34:04.76#ibcon#first serial, iclass 31, count 2 2006.257.12:34:04.76#ibcon#enter sib2, iclass 31, count 2 2006.257.12:34:04.76#ibcon#flushed, iclass 31, count 2 2006.257.12:34:04.76#ibcon#about to write, iclass 31, count 2 2006.257.12:34:04.76#ibcon#wrote, iclass 31, count 2 2006.257.12:34:04.76#ibcon#about to read 3, iclass 31, count 2 2006.257.12:34:04.78#ibcon#read 3, iclass 31, count 2 2006.257.12:34:04.78#ibcon#about to read 4, iclass 31, count 2 2006.257.12:34:04.78#ibcon#read 4, iclass 31, count 2 2006.257.12:34:04.78#ibcon#about to read 5, iclass 31, count 2 2006.257.12:34:04.78#ibcon#read 5, iclass 31, count 2 2006.257.12:34:04.78#ibcon#about to read 6, iclass 31, count 2 2006.257.12:34:04.78#ibcon#read 6, iclass 31, count 2 2006.257.12:34:04.78#ibcon#end of sib2, iclass 31, count 2 2006.257.12:34:04.78#ibcon#*mode == 0, iclass 31, count 2 2006.257.12:34:04.78#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.12:34:04.78#ibcon#[25=AT08-04\r\n] 2006.257.12:34:04.78#ibcon#*before write, iclass 31, count 2 2006.257.12:34:04.78#ibcon#enter sib2, iclass 31, count 2 2006.257.12:34:04.78#ibcon#flushed, iclass 31, count 2 2006.257.12:34:04.78#ibcon#about to write, iclass 31, count 2 2006.257.12:34:04.78#ibcon#wrote, iclass 31, count 2 2006.257.12:34:04.78#ibcon#about to read 3, iclass 31, count 2 2006.257.12:34:04.81#ibcon#read 3, iclass 31, count 2 2006.257.12:34:04.81#ibcon#about to read 4, iclass 31, count 2 2006.257.12:34:04.81#ibcon#read 4, iclass 31, count 2 2006.257.12:34:04.81#ibcon#about to read 5, iclass 31, count 2 2006.257.12:34:04.81#ibcon#read 5, iclass 31, count 2 2006.257.12:34:04.81#ibcon#about to read 6, iclass 31, count 2 2006.257.12:34:04.81#ibcon#read 6, iclass 31, count 2 2006.257.12:34:04.81#ibcon#end of sib2, iclass 31, count 2 2006.257.12:34:04.81#ibcon#*after write, iclass 31, count 2 2006.257.12:34:04.81#ibcon#*before return 0, iclass 31, count 2 2006.257.12:34:04.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:04.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:04.81#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.12:34:04.81#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:04.81#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:04.93#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:04.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:04.93#ibcon#enter wrdev, iclass 31, count 0 2006.257.12:34:04.93#ibcon#first serial, iclass 31, count 0 2006.257.12:34:04.93#ibcon#enter sib2, iclass 31, count 0 2006.257.12:34:04.93#ibcon#flushed, iclass 31, count 0 2006.257.12:34:04.93#ibcon#about to write, iclass 31, count 0 2006.257.12:34:04.93#ibcon#wrote, iclass 31, count 0 2006.257.12:34:04.93#ibcon#about to read 3, iclass 31, count 0 2006.257.12:34:04.95#ibcon#read 3, iclass 31, count 0 2006.257.12:34:04.95#ibcon#about to read 4, iclass 31, count 0 2006.257.12:34:04.95#ibcon#read 4, iclass 31, count 0 2006.257.12:34:04.95#ibcon#about to read 5, iclass 31, count 0 2006.257.12:34:04.95#ibcon#read 5, iclass 31, count 0 2006.257.12:34:04.95#ibcon#about to read 6, iclass 31, count 0 2006.257.12:34:04.95#ibcon#read 6, iclass 31, count 0 2006.257.12:34:04.95#ibcon#end of sib2, iclass 31, count 0 2006.257.12:34:04.95#ibcon#*mode == 0, iclass 31, count 0 2006.257.12:34:04.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.12:34:04.95#ibcon#[25=USB\r\n] 2006.257.12:34:04.95#ibcon#*before write, iclass 31, count 0 2006.257.12:34:04.95#ibcon#enter sib2, iclass 31, count 0 2006.257.12:34:04.95#ibcon#flushed, iclass 31, count 0 2006.257.12:34:04.95#ibcon#about to write, iclass 31, count 0 2006.257.12:34:04.95#ibcon#wrote, iclass 31, count 0 2006.257.12:34:04.95#ibcon#about to read 3, iclass 31, count 0 2006.257.12:34:04.98#ibcon#read 3, iclass 31, count 0 2006.257.12:34:04.98#ibcon#about to read 4, iclass 31, count 0 2006.257.12:34:04.98#ibcon#read 4, iclass 31, count 0 2006.257.12:34:04.98#ibcon#about to read 5, iclass 31, count 0 2006.257.12:34:04.98#ibcon#read 5, iclass 31, count 0 2006.257.12:34:04.98#ibcon#about to read 6, iclass 31, count 0 2006.257.12:34:04.98#ibcon#read 6, iclass 31, count 0 2006.257.12:34:04.98#ibcon#end of sib2, iclass 31, count 0 2006.257.12:34:04.98#ibcon#*after write, iclass 31, count 0 2006.257.12:34:04.98#ibcon#*before return 0, iclass 31, count 0 2006.257.12:34:04.98#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:04.98#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:04.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.12:34:04.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.12:34:04.98$vck44/vblo=1,629.99 2006.257.12:34:04.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.12:34:04.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.12:34:04.98#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:04.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:04.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:04.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:04.98#ibcon#enter wrdev, iclass 33, count 0 2006.257.12:34:04.98#ibcon#first serial, iclass 33, count 0 2006.257.12:34:04.98#ibcon#enter sib2, iclass 33, count 0 2006.257.12:34:04.98#ibcon#flushed, iclass 33, count 0 2006.257.12:34:04.98#ibcon#about to write, iclass 33, count 0 2006.257.12:34:04.98#ibcon#wrote, iclass 33, count 0 2006.257.12:34:04.98#ibcon#about to read 3, iclass 33, count 0 2006.257.12:34:05.00#ibcon#read 3, iclass 33, count 0 2006.257.12:34:05.00#ibcon#about to read 4, iclass 33, count 0 2006.257.12:34:05.00#ibcon#read 4, iclass 33, count 0 2006.257.12:34:05.00#ibcon#about to read 5, iclass 33, count 0 2006.257.12:34:05.00#ibcon#read 5, iclass 33, count 0 2006.257.12:34:05.00#ibcon#about to read 6, iclass 33, count 0 2006.257.12:34:05.00#ibcon#read 6, iclass 33, count 0 2006.257.12:34:05.00#ibcon#end of sib2, iclass 33, count 0 2006.257.12:34:05.00#ibcon#*mode == 0, iclass 33, count 0 2006.257.12:34:05.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.12:34:05.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:34:05.00#ibcon#*before write, iclass 33, count 0 2006.257.12:34:05.00#ibcon#enter sib2, iclass 33, count 0 2006.257.12:34:05.00#ibcon#flushed, iclass 33, count 0 2006.257.12:34:05.00#ibcon#about to write, iclass 33, count 0 2006.257.12:34:05.00#ibcon#wrote, iclass 33, count 0 2006.257.12:34:05.00#ibcon#about to read 3, iclass 33, count 0 2006.257.12:34:05.04#ibcon#read 3, iclass 33, count 0 2006.257.12:34:05.04#ibcon#about to read 4, iclass 33, count 0 2006.257.12:34:05.04#ibcon#read 4, iclass 33, count 0 2006.257.12:34:05.04#ibcon#about to read 5, iclass 33, count 0 2006.257.12:34:05.04#ibcon#read 5, iclass 33, count 0 2006.257.12:34:05.04#ibcon#about to read 6, iclass 33, count 0 2006.257.12:34:05.04#ibcon#read 6, iclass 33, count 0 2006.257.12:34:05.04#ibcon#end of sib2, iclass 33, count 0 2006.257.12:34:05.04#ibcon#*after write, iclass 33, count 0 2006.257.12:34:05.04#ibcon#*before return 0, iclass 33, count 0 2006.257.12:34:05.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:05.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:05.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.12:34:05.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.12:34:05.04$vck44/vb=1,4 2006.257.12:34:05.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.12:34:05.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.12:34:05.04#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:05.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:34:05.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:34:05.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:34:05.04#ibcon#enter wrdev, iclass 35, count 2 2006.257.12:34:05.04#ibcon#first serial, iclass 35, count 2 2006.257.12:34:05.04#ibcon#enter sib2, iclass 35, count 2 2006.257.12:34:05.04#ibcon#flushed, iclass 35, count 2 2006.257.12:34:05.04#ibcon#about to write, iclass 35, count 2 2006.257.12:34:05.04#ibcon#wrote, iclass 35, count 2 2006.257.12:34:05.04#ibcon#about to read 3, iclass 35, count 2 2006.257.12:34:05.06#ibcon#read 3, iclass 35, count 2 2006.257.12:34:05.06#ibcon#about to read 4, iclass 35, count 2 2006.257.12:34:05.06#ibcon#read 4, iclass 35, count 2 2006.257.12:34:05.06#ibcon#about to read 5, iclass 35, count 2 2006.257.12:34:05.06#ibcon#read 5, iclass 35, count 2 2006.257.12:34:05.06#ibcon#about to read 6, iclass 35, count 2 2006.257.12:34:05.06#ibcon#read 6, iclass 35, count 2 2006.257.12:34:05.06#ibcon#end of sib2, iclass 35, count 2 2006.257.12:34:05.06#ibcon#*mode == 0, iclass 35, count 2 2006.257.12:34:05.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.12:34:05.06#ibcon#[27=AT01-04\r\n] 2006.257.12:34:05.06#ibcon#*before write, iclass 35, count 2 2006.257.12:34:05.06#ibcon#enter sib2, iclass 35, count 2 2006.257.12:34:05.06#ibcon#flushed, iclass 35, count 2 2006.257.12:34:05.06#ibcon#about to write, iclass 35, count 2 2006.257.12:34:05.06#ibcon#wrote, iclass 35, count 2 2006.257.12:34:05.06#ibcon#about to read 3, iclass 35, count 2 2006.257.12:34:05.09#ibcon#read 3, iclass 35, count 2 2006.257.12:34:05.09#ibcon#about to read 4, iclass 35, count 2 2006.257.12:34:05.09#ibcon#read 4, iclass 35, count 2 2006.257.12:34:05.09#ibcon#about to read 5, iclass 35, count 2 2006.257.12:34:05.09#ibcon#read 5, iclass 35, count 2 2006.257.12:34:05.09#ibcon#about to read 6, iclass 35, count 2 2006.257.12:34:05.09#ibcon#read 6, iclass 35, count 2 2006.257.12:34:05.09#ibcon#end of sib2, iclass 35, count 2 2006.257.12:34:05.09#ibcon#*after write, iclass 35, count 2 2006.257.12:34:05.09#ibcon#*before return 0, iclass 35, count 2 2006.257.12:34:05.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:34:05.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:34:05.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.12:34:05.09#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:05.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:34:05.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:34:05.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:34:05.21#ibcon#enter wrdev, iclass 35, count 0 2006.257.12:34:05.21#ibcon#first serial, iclass 35, count 0 2006.257.12:34:05.21#ibcon#enter sib2, iclass 35, count 0 2006.257.12:34:05.21#ibcon#flushed, iclass 35, count 0 2006.257.12:34:05.21#ibcon#about to write, iclass 35, count 0 2006.257.12:34:05.21#ibcon#wrote, iclass 35, count 0 2006.257.12:34:05.21#ibcon#about to read 3, iclass 35, count 0 2006.257.12:34:05.23#ibcon#read 3, iclass 35, count 0 2006.257.12:34:05.23#ibcon#about to read 4, iclass 35, count 0 2006.257.12:34:05.23#ibcon#read 4, iclass 35, count 0 2006.257.12:34:05.23#ibcon#about to read 5, iclass 35, count 0 2006.257.12:34:05.23#ibcon#read 5, iclass 35, count 0 2006.257.12:34:05.23#ibcon#about to read 6, iclass 35, count 0 2006.257.12:34:05.23#ibcon#read 6, iclass 35, count 0 2006.257.12:34:05.23#ibcon#end of sib2, iclass 35, count 0 2006.257.12:34:05.23#ibcon#*mode == 0, iclass 35, count 0 2006.257.12:34:05.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.12:34:05.23#ibcon#[27=USB\r\n] 2006.257.12:34:05.23#ibcon#*before write, iclass 35, count 0 2006.257.12:34:05.23#ibcon#enter sib2, iclass 35, count 0 2006.257.12:34:05.23#ibcon#flushed, iclass 35, count 0 2006.257.12:34:05.23#ibcon#about to write, iclass 35, count 0 2006.257.12:34:05.23#ibcon#wrote, iclass 35, count 0 2006.257.12:34:05.23#ibcon#about to read 3, iclass 35, count 0 2006.257.12:34:05.26#ibcon#read 3, iclass 35, count 0 2006.257.12:34:05.26#ibcon#about to read 4, iclass 35, count 0 2006.257.12:34:05.26#ibcon#read 4, iclass 35, count 0 2006.257.12:34:05.26#ibcon#about to read 5, iclass 35, count 0 2006.257.12:34:05.26#ibcon#read 5, iclass 35, count 0 2006.257.12:34:05.26#ibcon#about to read 6, iclass 35, count 0 2006.257.12:34:05.26#ibcon#read 6, iclass 35, count 0 2006.257.12:34:05.26#ibcon#end of sib2, iclass 35, count 0 2006.257.12:34:05.26#ibcon#*after write, iclass 35, count 0 2006.257.12:34:05.26#ibcon#*before return 0, iclass 35, count 0 2006.257.12:34:05.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:34:05.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:34:05.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.12:34:05.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.12:34:05.26$vck44/vblo=2,634.99 2006.257.12:34:05.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.12:34:05.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.12:34:05.26#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:05.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:05.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:05.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:05.26#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:34:05.26#ibcon#first serial, iclass 37, count 0 2006.257.12:34:05.26#ibcon#enter sib2, iclass 37, count 0 2006.257.12:34:05.26#ibcon#flushed, iclass 37, count 0 2006.257.12:34:05.26#ibcon#about to write, iclass 37, count 0 2006.257.12:34:05.26#ibcon#wrote, iclass 37, count 0 2006.257.12:34:05.26#ibcon#about to read 3, iclass 37, count 0 2006.257.12:34:05.28#ibcon#read 3, iclass 37, count 0 2006.257.12:34:05.28#ibcon#about to read 4, iclass 37, count 0 2006.257.12:34:05.28#ibcon#read 4, iclass 37, count 0 2006.257.12:34:05.28#ibcon#about to read 5, iclass 37, count 0 2006.257.12:34:05.28#ibcon#read 5, iclass 37, count 0 2006.257.12:34:05.28#ibcon#about to read 6, iclass 37, count 0 2006.257.12:34:05.28#ibcon#read 6, iclass 37, count 0 2006.257.12:34:05.28#ibcon#end of sib2, iclass 37, count 0 2006.257.12:34:05.28#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:34:05.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:34:05.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:34:05.28#ibcon#*before write, iclass 37, count 0 2006.257.12:34:05.28#ibcon#enter sib2, iclass 37, count 0 2006.257.12:34:05.28#ibcon#flushed, iclass 37, count 0 2006.257.12:34:05.28#ibcon#about to write, iclass 37, count 0 2006.257.12:34:05.28#ibcon#wrote, iclass 37, count 0 2006.257.12:34:05.28#ibcon#about to read 3, iclass 37, count 0 2006.257.12:34:05.32#ibcon#read 3, iclass 37, count 0 2006.257.12:34:05.32#ibcon#about to read 4, iclass 37, count 0 2006.257.12:34:05.32#ibcon#read 4, iclass 37, count 0 2006.257.12:34:05.32#ibcon#about to read 5, iclass 37, count 0 2006.257.12:34:05.32#ibcon#read 5, iclass 37, count 0 2006.257.12:34:05.32#ibcon#about to read 6, iclass 37, count 0 2006.257.12:34:05.32#ibcon#read 6, iclass 37, count 0 2006.257.12:34:05.32#ibcon#end of sib2, iclass 37, count 0 2006.257.12:34:05.32#ibcon#*after write, iclass 37, count 0 2006.257.12:34:05.32#ibcon#*before return 0, iclass 37, count 0 2006.257.12:34:05.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:05.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:34:05.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:34:05.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:34:05.32$vck44/vb=2,5 2006.257.12:34:05.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.12:34:05.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.12:34:05.32#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:05.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:05.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:05.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:05.38#ibcon#enter wrdev, iclass 39, count 2 2006.257.12:34:05.38#ibcon#first serial, iclass 39, count 2 2006.257.12:34:05.38#ibcon#enter sib2, iclass 39, count 2 2006.257.12:34:05.38#ibcon#flushed, iclass 39, count 2 2006.257.12:34:05.38#ibcon#about to write, iclass 39, count 2 2006.257.12:34:05.38#ibcon#wrote, iclass 39, count 2 2006.257.12:34:05.38#ibcon#about to read 3, iclass 39, count 2 2006.257.12:34:05.40#ibcon#read 3, iclass 39, count 2 2006.257.12:34:05.40#ibcon#about to read 4, iclass 39, count 2 2006.257.12:34:05.40#ibcon#read 4, iclass 39, count 2 2006.257.12:34:05.40#ibcon#about to read 5, iclass 39, count 2 2006.257.12:34:05.40#ibcon#read 5, iclass 39, count 2 2006.257.12:34:05.40#ibcon#about to read 6, iclass 39, count 2 2006.257.12:34:05.40#ibcon#read 6, iclass 39, count 2 2006.257.12:34:05.40#ibcon#end of sib2, iclass 39, count 2 2006.257.12:34:05.40#ibcon#*mode == 0, iclass 39, count 2 2006.257.12:34:05.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.12:34:05.40#ibcon#[27=AT02-05\r\n] 2006.257.12:34:05.40#ibcon#*before write, iclass 39, count 2 2006.257.12:34:05.40#ibcon#enter sib2, iclass 39, count 2 2006.257.12:34:05.40#ibcon#flushed, iclass 39, count 2 2006.257.12:34:05.40#ibcon#about to write, iclass 39, count 2 2006.257.12:34:05.40#ibcon#wrote, iclass 39, count 2 2006.257.12:34:05.40#ibcon#about to read 3, iclass 39, count 2 2006.257.12:34:05.43#ibcon#read 3, iclass 39, count 2 2006.257.12:34:05.43#ibcon#about to read 4, iclass 39, count 2 2006.257.12:34:05.43#ibcon#read 4, iclass 39, count 2 2006.257.12:34:05.43#ibcon#about to read 5, iclass 39, count 2 2006.257.12:34:05.43#ibcon#read 5, iclass 39, count 2 2006.257.12:34:05.43#ibcon#about to read 6, iclass 39, count 2 2006.257.12:34:05.43#ibcon#read 6, iclass 39, count 2 2006.257.12:34:05.43#ibcon#end of sib2, iclass 39, count 2 2006.257.12:34:05.43#ibcon#*after write, iclass 39, count 2 2006.257.12:34:05.43#ibcon#*before return 0, iclass 39, count 2 2006.257.12:34:05.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:05.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:34:05.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.12:34:05.43#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:05.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:05.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:05.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:05.55#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:34:05.55#ibcon#first serial, iclass 39, count 0 2006.257.12:34:05.55#ibcon#enter sib2, iclass 39, count 0 2006.257.12:34:05.55#ibcon#flushed, iclass 39, count 0 2006.257.12:34:05.55#ibcon#about to write, iclass 39, count 0 2006.257.12:34:05.55#ibcon#wrote, iclass 39, count 0 2006.257.12:34:05.55#ibcon#about to read 3, iclass 39, count 0 2006.257.12:34:05.57#ibcon#read 3, iclass 39, count 0 2006.257.12:34:05.57#ibcon#about to read 4, iclass 39, count 0 2006.257.12:34:05.57#ibcon#read 4, iclass 39, count 0 2006.257.12:34:05.57#ibcon#about to read 5, iclass 39, count 0 2006.257.12:34:05.57#ibcon#read 5, iclass 39, count 0 2006.257.12:34:05.57#ibcon#about to read 6, iclass 39, count 0 2006.257.12:34:05.57#ibcon#read 6, iclass 39, count 0 2006.257.12:34:05.57#ibcon#end of sib2, iclass 39, count 0 2006.257.12:34:05.57#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:34:05.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:34:05.57#ibcon#[27=USB\r\n] 2006.257.12:34:05.57#ibcon#*before write, iclass 39, count 0 2006.257.12:34:05.57#ibcon#enter sib2, iclass 39, count 0 2006.257.12:34:05.57#ibcon#flushed, iclass 39, count 0 2006.257.12:34:05.57#ibcon#about to write, iclass 39, count 0 2006.257.12:34:05.57#ibcon#wrote, iclass 39, count 0 2006.257.12:34:05.57#ibcon#about to read 3, iclass 39, count 0 2006.257.12:34:05.60#ibcon#read 3, iclass 39, count 0 2006.257.12:34:05.60#ibcon#about to read 4, iclass 39, count 0 2006.257.12:34:05.60#ibcon#read 4, iclass 39, count 0 2006.257.12:34:05.60#ibcon#about to read 5, iclass 39, count 0 2006.257.12:34:05.60#ibcon#read 5, iclass 39, count 0 2006.257.12:34:05.60#ibcon#about to read 6, iclass 39, count 0 2006.257.12:34:05.60#ibcon#read 6, iclass 39, count 0 2006.257.12:34:05.60#ibcon#end of sib2, iclass 39, count 0 2006.257.12:34:05.60#ibcon#*after write, iclass 39, count 0 2006.257.12:34:05.60#ibcon#*before return 0, iclass 39, count 0 2006.257.12:34:05.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:05.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:34:05.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:34:05.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:34:05.60$vck44/vblo=3,649.99 2006.257.12:34:05.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.12:34:05.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.12:34:05.60#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:05.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:05.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:05.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:05.60#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:34:05.60#ibcon#first serial, iclass 3, count 0 2006.257.12:34:05.60#ibcon#enter sib2, iclass 3, count 0 2006.257.12:34:05.60#ibcon#flushed, iclass 3, count 0 2006.257.12:34:05.60#ibcon#about to write, iclass 3, count 0 2006.257.12:34:05.60#ibcon#wrote, iclass 3, count 0 2006.257.12:34:05.60#ibcon#about to read 3, iclass 3, count 0 2006.257.12:34:05.62#ibcon#read 3, iclass 3, count 0 2006.257.12:34:05.62#ibcon#about to read 4, iclass 3, count 0 2006.257.12:34:05.62#ibcon#read 4, iclass 3, count 0 2006.257.12:34:05.62#ibcon#about to read 5, iclass 3, count 0 2006.257.12:34:05.62#ibcon#read 5, iclass 3, count 0 2006.257.12:34:05.62#ibcon#about to read 6, iclass 3, count 0 2006.257.12:34:05.62#ibcon#read 6, iclass 3, count 0 2006.257.12:34:05.62#ibcon#end of sib2, iclass 3, count 0 2006.257.12:34:05.62#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:34:05.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:34:05.62#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:34:05.62#ibcon#*before write, iclass 3, count 0 2006.257.12:34:05.62#ibcon#enter sib2, iclass 3, count 0 2006.257.12:34:05.62#ibcon#flushed, iclass 3, count 0 2006.257.12:34:05.62#ibcon#about to write, iclass 3, count 0 2006.257.12:34:05.62#ibcon#wrote, iclass 3, count 0 2006.257.12:34:05.62#ibcon#about to read 3, iclass 3, count 0 2006.257.12:34:05.66#ibcon#read 3, iclass 3, count 0 2006.257.12:34:05.66#ibcon#about to read 4, iclass 3, count 0 2006.257.12:34:05.66#ibcon#read 4, iclass 3, count 0 2006.257.12:34:05.66#ibcon#about to read 5, iclass 3, count 0 2006.257.12:34:05.66#ibcon#read 5, iclass 3, count 0 2006.257.12:34:05.66#ibcon#about to read 6, iclass 3, count 0 2006.257.12:34:05.66#ibcon#read 6, iclass 3, count 0 2006.257.12:34:05.66#ibcon#end of sib2, iclass 3, count 0 2006.257.12:34:05.66#ibcon#*after write, iclass 3, count 0 2006.257.12:34:05.66#ibcon#*before return 0, iclass 3, count 0 2006.257.12:34:05.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:05.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:34:05.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:34:05.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:34:05.66$vck44/vb=3,4 2006.257.12:34:05.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.12:34:05.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.12:34:05.66#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:05.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:05.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:05.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:05.72#ibcon#enter wrdev, iclass 5, count 2 2006.257.12:34:05.72#ibcon#first serial, iclass 5, count 2 2006.257.12:34:05.72#ibcon#enter sib2, iclass 5, count 2 2006.257.12:34:05.72#ibcon#flushed, iclass 5, count 2 2006.257.12:34:05.72#ibcon#about to write, iclass 5, count 2 2006.257.12:34:05.72#ibcon#wrote, iclass 5, count 2 2006.257.12:34:05.72#ibcon#about to read 3, iclass 5, count 2 2006.257.12:34:05.74#ibcon#read 3, iclass 5, count 2 2006.257.12:34:05.74#ibcon#about to read 4, iclass 5, count 2 2006.257.12:34:05.74#ibcon#read 4, iclass 5, count 2 2006.257.12:34:05.74#ibcon#about to read 5, iclass 5, count 2 2006.257.12:34:05.74#ibcon#read 5, iclass 5, count 2 2006.257.12:34:05.74#ibcon#about to read 6, iclass 5, count 2 2006.257.12:34:05.74#ibcon#read 6, iclass 5, count 2 2006.257.12:34:05.74#ibcon#end of sib2, iclass 5, count 2 2006.257.12:34:05.74#ibcon#*mode == 0, iclass 5, count 2 2006.257.12:34:05.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.12:34:05.74#ibcon#[27=AT03-04\r\n] 2006.257.12:34:05.74#ibcon#*before write, iclass 5, count 2 2006.257.12:34:05.74#ibcon#enter sib2, iclass 5, count 2 2006.257.12:34:05.74#ibcon#flushed, iclass 5, count 2 2006.257.12:34:05.74#ibcon#about to write, iclass 5, count 2 2006.257.12:34:05.74#ibcon#wrote, iclass 5, count 2 2006.257.12:34:05.74#ibcon#about to read 3, iclass 5, count 2 2006.257.12:34:05.77#ibcon#read 3, iclass 5, count 2 2006.257.12:34:05.77#ibcon#about to read 4, iclass 5, count 2 2006.257.12:34:05.77#ibcon#read 4, iclass 5, count 2 2006.257.12:34:05.77#ibcon#about to read 5, iclass 5, count 2 2006.257.12:34:05.77#ibcon#read 5, iclass 5, count 2 2006.257.12:34:05.77#ibcon#about to read 6, iclass 5, count 2 2006.257.12:34:05.77#ibcon#read 6, iclass 5, count 2 2006.257.12:34:05.77#ibcon#end of sib2, iclass 5, count 2 2006.257.12:34:05.77#ibcon#*after write, iclass 5, count 2 2006.257.12:34:05.77#ibcon#*before return 0, iclass 5, count 2 2006.257.12:34:05.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:05.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:34:05.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.12:34:05.77#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:05.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:05.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:05.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:05.89#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:34:05.89#ibcon#first serial, iclass 5, count 0 2006.257.12:34:05.89#ibcon#enter sib2, iclass 5, count 0 2006.257.12:34:05.89#ibcon#flushed, iclass 5, count 0 2006.257.12:34:05.89#ibcon#about to write, iclass 5, count 0 2006.257.12:34:05.89#ibcon#wrote, iclass 5, count 0 2006.257.12:34:05.89#ibcon#about to read 3, iclass 5, count 0 2006.257.12:34:05.91#ibcon#read 3, iclass 5, count 0 2006.257.12:34:05.91#ibcon#about to read 4, iclass 5, count 0 2006.257.12:34:05.91#ibcon#read 4, iclass 5, count 0 2006.257.12:34:05.91#ibcon#about to read 5, iclass 5, count 0 2006.257.12:34:05.91#ibcon#read 5, iclass 5, count 0 2006.257.12:34:05.91#ibcon#about to read 6, iclass 5, count 0 2006.257.12:34:05.91#ibcon#read 6, iclass 5, count 0 2006.257.12:34:05.91#ibcon#end of sib2, iclass 5, count 0 2006.257.12:34:05.91#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:34:05.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:34:05.91#ibcon#[27=USB\r\n] 2006.257.12:34:05.91#ibcon#*before write, iclass 5, count 0 2006.257.12:34:05.91#ibcon#enter sib2, iclass 5, count 0 2006.257.12:34:05.91#ibcon#flushed, iclass 5, count 0 2006.257.12:34:05.91#ibcon#about to write, iclass 5, count 0 2006.257.12:34:05.91#ibcon#wrote, iclass 5, count 0 2006.257.12:34:05.91#ibcon#about to read 3, iclass 5, count 0 2006.257.12:34:05.94#ibcon#read 3, iclass 5, count 0 2006.257.12:34:05.94#ibcon#about to read 4, iclass 5, count 0 2006.257.12:34:05.94#ibcon#read 4, iclass 5, count 0 2006.257.12:34:05.94#ibcon#about to read 5, iclass 5, count 0 2006.257.12:34:05.94#ibcon#read 5, iclass 5, count 0 2006.257.12:34:05.94#ibcon#about to read 6, iclass 5, count 0 2006.257.12:34:05.94#ibcon#read 6, iclass 5, count 0 2006.257.12:34:05.94#ibcon#end of sib2, iclass 5, count 0 2006.257.12:34:05.94#ibcon#*after write, iclass 5, count 0 2006.257.12:34:05.94#ibcon#*before return 0, iclass 5, count 0 2006.257.12:34:05.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:05.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:34:05.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:34:05.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:34:05.94$vck44/vblo=4,679.99 2006.257.12:34:05.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.12:34:05.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.12:34:05.94#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:05.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:05.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:05.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:05.94#ibcon#enter wrdev, iclass 7, count 0 2006.257.12:34:05.94#ibcon#first serial, iclass 7, count 0 2006.257.12:34:05.94#ibcon#enter sib2, iclass 7, count 0 2006.257.12:34:05.94#ibcon#flushed, iclass 7, count 0 2006.257.12:34:05.94#ibcon#about to write, iclass 7, count 0 2006.257.12:34:05.94#ibcon#wrote, iclass 7, count 0 2006.257.12:34:05.94#ibcon#about to read 3, iclass 7, count 0 2006.257.12:34:05.96#ibcon#read 3, iclass 7, count 0 2006.257.12:34:05.96#ibcon#about to read 4, iclass 7, count 0 2006.257.12:34:05.96#ibcon#read 4, iclass 7, count 0 2006.257.12:34:05.96#ibcon#about to read 5, iclass 7, count 0 2006.257.12:34:05.96#ibcon#read 5, iclass 7, count 0 2006.257.12:34:05.96#ibcon#about to read 6, iclass 7, count 0 2006.257.12:34:05.96#ibcon#read 6, iclass 7, count 0 2006.257.12:34:05.96#ibcon#end of sib2, iclass 7, count 0 2006.257.12:34:05.96#ibcon#*mode == 0, iclass 7, count 0 2006.257.12:34:05.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.12:34:05.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:34:05.96#ibcon#*before write, iclass 7, count 0 2006.257.12:34:05.96#ibcon#enter sib2, iclass 7, count 0 2006.257.12:34:05.96#ibcon#flushed, iclass 7, count 0 2006.257.12:34:05.96#ibcon#about to write, iclass 7, count 0 2006.257.12:34:05.96#ibcon#wrote, iclass 7, count 0 2006.257.12:34:05.96#ibcon#about to read 3, iclass 7, count 0 2006.257.12:34:06.00#ibcon#read 3, iclass 7, count 0 2006.257.12:34:06.00#ibcon#about to read 4, iclass 7, count 0 2006.257.12:34:06.00#ibcon#read 4, iclass 7, count 0 2006.257.12:34:06.00#ibcon#about to read 5, iclass 7, count 0 2006.257.12:34:06.00#ibcon#read 5, iclass 7, count 0 2006.257.12:34:06.00#ibcon#about to read 6, iclass 7, count 0 2006.257.12:34:06.00#ibcon#read 6, iclass 7, count 0 2006.257.12:34:06.00#ibcon#end of sib2, iclass 7, count 0 2006.257.12:34:06.00#ibcon#*after write, iclass 7, count 0 2006.257.12:34:06.00#ibcon#*before return 0, iclass 7, count 0 2006.257.12:34:06.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:06.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:34:06.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.12:34:06.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.12:34:06.00$vck44/vb=4,5 2006.257.12:34:06.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.12:34:06.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.12:34:06.00#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:06.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:06.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:06.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:06.06#ibcon#enter wrdev, iclass 11, count 2 2006.257.12:34:06.06#ibcon#first serial, iclass 11, count 2 2006.257.12:34:06.06#ibcon#enter sib2, iclass 11, count 2 2006.257.12:34:06.06#ibcon#flushed, iclass 11, count 2 2006.257.12:34:06.06#ibcon#about to write, iclass 11, count 2 2006.257.12:34:06.06#ibcon#wrote, iclass 11, count 2 2006.257.12:34:06.06#ibcon#about to read 3, iclass 11, count 2 2006.257.12:34:06.08#ibcon#read 3, iclass 11, count 2 2006.257.12:34:06.08#ibcon#about to read 4, iclass 11, count 2 2006.257.12:34:06.08#ibcon#read 4, iclass 11, count 2 2006.257.12:34:06.08#ibcon#about to read 5, iclass 11, count 2 2006.257.12:34:06.08#ibcon#read 5, iclass 11, count 2 2006.257.12:34:06.08#ibcon#about to read 6, iclass 11, count 2 2006.257.12:34:06.08#ibcon#read 6, iclass 11, count 2 2006.257.12:34:06.08#ibcon#end of sib2, iclass 11, count 2 2006.257.12:34:06.08#ibcon#*mode == 0, iclass 11, count 2 2006.257.12:34:06.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.12:34:06.08#ibcon#[27=AT04-05\r\n] 2006.257.12:34:06.08#ibcon#*before write, iclass 11, count 2 2006.257.12:34:06.08#ibcon#enter sib2, iclass 11, count 2 2006.257.12:34:06.08#ibcon#flushed, iclass 11, count 2 2006.257.12:34:06.08#ibcon#about to write, iclass 11, count 2 2006.257.12:34:06.08#ibcon#wrote, iclass 11, count 2 2006.257.12:34:06.08#ibcon#about to read 3, iclass 11, count 2 2006.257.12:34:06.11#ibcon#read 3, iclass 11, count 2 2006.257.12:34:06.11#ibcon#about to read 4, iclass 11, count 2 2006.257.12:34:06.11#ibcon#read 4, iclass 11, count 2 2006.257.12:34:06.11#ibcon#about to read 5, iclass 11, count 2 2006.257.12:34:06.11#ibcon#read 5, iclass 11, count 2 2006.257.12:34:06.11#ibcon#about to read 6, iclass 11, count 2 2006.257.12:34:06.11#ibcon#read 6, iclass 11, count 2 2006.257.12:34:06.11#ibcon#end of sib2, iclass 11, count 2 2006.257.12:34:06.11#ibcon#*after write, iclass 11, count 2 2006.257.12:34:06.11#ibcon#*before return 0, iclass 11, count 2 2006.257.12:34:06.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:06.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:34:06.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.12:34:06.11#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:06.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:06.17#abcon#<5=/14 1.8 5.0 17.95 961013.8\r\n> 2006.257.12:34:06.19#abcon#{5=INTERFACE CLEAR} 2006.257.12:34:06.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:06.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:06.23#ibcon#enter wrdev, iclass 11, count 0 2006.257.12:34:06.23#ibcon#first serial, iclass 11, count 0 2006.257.12:34:06.23#ibcon#enter sib2, iclass 11, count 0 2006.257.12:34:06.23#ibcon#flushed, iclass 11, count 0 2006.257.12:34:06.23#ibcon#about to write, iclass 11, count 0 2006.257.12:34:06.23#ibcon#wrote, iclass 11, count 0 2006.257.12:34:06.23#ibcon#about to read 3, iclass 11, count 0 2006.257.12:34:06.25#ibcon#read 3, iclass 11, count 0 2006.257.12:34:06.25#ibcon#about to read 4, iclass 11, count 0 2006.257.12:34:06.25#ibcon#read 4, iclass 11, count 0 2006.257.12:34:06.25#ibcon#about to read 5, iclass 11, count 0 2006.257.12:34:06.25#ibcon#read 5, iclass 11, count 0 2006.257.12:34:06.25#ibcon#about to read 6, iclass 11, count 0 2006.257.12:34:06.25#ibcon#read 6, iclass 11, count 0 2006.257.12:34:06.25#ibcon#end of sib2, iclass 11, count 0 2006.257.12:34:06.25#ibcon#*mode == 0, iclass 11, count 0 2006.257.12:34:06.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.12:34:06.25#ibcon#[27=USB\r\n] 2006.257.12:34:06.25#ibcon#*before write, iclass 11, count 0 2006.257.12:34:06.25#ibcon#enter sib2, iclass 11, count 0 2006.257.12:34:06.25#ibcon#flushed, iclass 11, count 0 2006.257.12:34:06.25#ibcon#about to write, iclass 11, count 0 2006.257.12:34:06.25#ibcon#wrote, iclass 11, count 0 2006.257.12:34:06.25#ibcon#about to read 3, iclass 11, count 0 2006.257.12:34:06.25#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:34:06.28#ibcon#read 3, iclass 11, count 0 2006.257.12:34:06.28#ibcon#about to read 4, iclass 11, count 0 2006.257.12:34:06.28#ibcon#read 4, iclass 11, count 0 2006.257.12:34:06.28#ibcon#about to read 5, iclass 11, count 0 2006.257.12:34:06.28#ibcon#read 5, iclass 11, count 0 2006.257.12:34:06.28#ibcon#about to read 6, iclass 11, count 0 2006.257.12:34:06.28#ibcon#read 6, iclass 11, count 0 2006.257.12:34:06.28#ibcon#end of sib2, iclass 11, count 0 2006.257.12:34:06.28#ibcon#*after write, iclass 11, count 0 2006.257.12:34:06.28#ibcon#*before return 0, iclass 11, count 0 2006.257.12:34:06.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:06.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:34:06.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.12:34:06.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.12:34:06.28$vck44/vblo=5,709.99 2006.257.12:34:06.28#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.12:34:06.28#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.12:34:06.28#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:06.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:06.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:06.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:06.28#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:34:06.28#ibcon#first serial, iclass 17, count 0 2006.257.12:34:06.28#ibcon#enter sib2, iclass 17, count 0 2006.257.12:34:06.28#ibcon#flushed, iclass 17, count 0 2006.257.12:34:06.28#ibcon#about to write, iclass 17, count 0 2006.257.12:34:06.28#ibcon#wrote, iclass 17, count 0 2006.257.12:34:06.28#ibcon#about to read 3, iclass 17, count 0 2006.257.12:34:06.30#ibcon#read 3, iclass 17, count 0 2006.257.12:34:06.30#ibcon#about to read 4, iclass 17, count 0 2006.257.12:34:06.30#ibcon#read 4, iclass 17, count 0 2006.257.12:34:06.30#ibcon#about to read 5, iclass 17, count 0 2006.257.12:34:06.30#ibcon#read 5, iclass 17, count 0 2006.257.12:34:06.30#ibcon#about to read 6, iclass 17, count 0 2006.257.12:34:06.30#ibcon#read 6, iclass 17, count 0 2006.257.12:34:06.30#ibcon#end of sib2, iclass 17, count 0 2006.257.12:34:06.30#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:34:06.30#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:34:06.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:34:06.30#ibcon#*before write, iclass 17, count 0 2006.257.12:34:06.30#ibcon#enter sib2, iclass 17, count 0 2006.257.12:34:06.30#ibcon#flushed, iclass 17, count 0 2006.257.12:34:06.30#ibcon#about to write, iclass 17, count 0 2006.257.12:34:06.30#ibcon#wrote, iclass 17, count 0 2006.257.12:34:06.30#ibcon#about to read 3, iclass 17, count 0 2006.257.12:34:06.34#ibcon#read 3, iclass 17, count 0 2006.257.12:34:06.34#ibcon#about to read 4, iclass 17, count 0 2006.257.12:34:06.34#ibcon#read 4, iclass 17, count 0 2006.257.12:34:06.34#ibcon#about to read 5, iclass 17, count 0 2006.257.12:34:06.34#ibcon#read 5, iclass 17, count 0 2006.257.12:34:06.34#ibcon#about to read 6, iclass 17, count 0 2006.257.12:34:06.34#ibcon#read 6, iclass 17, count 0 2006.257.12:34:06.34#ibcon#end of sib2, iclass 17, count 0 2006.257.12:34:06.34#ibcon#*after write, iclass 17, count 0 2006.257.12:34:06.34#ibcon#*before return 0, iclass 17, count 0 2006.257.12:34:06.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:06.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:34:06.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:34:06.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:34:06.34$vck44/vb=5,4 2006.257.12:34:06.34#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.12:34:06.34#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.12:34:06.34#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:06.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:06.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:06.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:06.40#ibcon#enter wrdev, iclass 19, count 2 2006.257.12:34:06.40#ibcon#first serial, iclass 19, count 2 2006.257.12:34:06.40#ibcon#enter sib2, iclass 19, count 2 2006.257.12:34:06.40#ibcon#flushed, iclass 19, count 2 2006.257.12:34:06.40#ibcon#about to write, iclass 19, count 2 2006.257.12:34:06.40#ibcon#wrote, iclass 19, count 2 2006.257.12:34:06.40#ibcon#about to read 3, iclass 19, count 2 2006.257.12:34:06.42#ibcon#read 3, iclass 19, count 2 2006.257.12:34:06.42#ibcon#about to read 4, iclass 19, count 2 2006.257.12:34:06.42#ibcon#read 4, iclass 19, count 2 2006.257.12:34:06.42#ibcon#about to read 5, iclass 19, count 2 2006.257.12:34:06.42#ibcon#read 5, iclass 19, count 2 2006.257.12:34:06.42#ibcon#about to read 6, iclass 19, count 2 2006.257.12:34:06.42#ibcon#read 6, iclass 19, count 2 2006.257.12:34:06.42#ibcon#end of sib2, iclass 19, count 2 2006.257.12:34:06.42#ibcon#*mode == 0, iclass 19, count 2 2006.257.12:34:06.42#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.12:34:06.42#ibcon#[27=AT05-04\r\n] 2006.257.12:34:06.42#ibcon#*before write, iclass 19, count 2 2006.257.12:34:06.42#ibcon#enter sib2, iclass 19, count 2 2006.257.12:34:06.42#ibcon#flushed, iclass 19, count 2 2006.257.12:34:06.42#ibcon#about to write, iclass 19, count 2 2006.257.12:34:06.42#ibcon#wrote, iclass 19, count 2 2006.257.12:34:06.42#ibcon#about to read 3, iclass 19, count 2 2006.257.12:34:06.45#ibcon#read 3, iclass 19, count 2 2006.257.12:34:06.45#ibcon#about to read 4, iclass 19, count 2 2006.257.12:34:06.45#ibcon#read 4, iclass 19, count 2 2006.257.12:34:06.45#ibcon#about to read 5, iclass 19, count 2 2006.257.12:34:06.45#ibcon#read 5, iclass 19, count 2 2006.257.12:34:06.45#ibcon#about to read 6, iclass 19, count 2 2006.257.12:34:06.45#ibcon#read 6, iclass 19, count 2 2006.257.12:34:06.45#ibcon#end of sib2, iclass 19, count 2 2006.257.12:34:06.45#ibcon#*after write, iclass 19, count 2 2006.257.12:34:06.45#ibcon#*before return 0, iclass 19, count 2 2006.257.12:34:06.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:06.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:34:06.45#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.12:34:06.45#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:06.45#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:06.57#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:06.57#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:06.57#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:34:06.57#ibcon#first serial, iclass 19, count 0 2006.257.12:34:06.57#ibcon#enter sib2, iclass 19, count 0 2006.257.12:34:06.57#ibcon#flushed, iclass 19, count 0 2006.257.12:34:06.57#ibcon#about to write, iclass 19, count 0 2006.257.12:34:06.57#ibcon#wrote, iclass 19, count 0 2006.257.12:34:06.57#ibcon#about to read 3, iclass 19, count 0 2006.257.12:34:06.59#ibcon#read 3, iclass 19, count 0 2006.257.12:34:06.59#ibcon#about to read 4, iclass 19, count 0 2006.257.12:34:06.59#ibcon#read 4, iclass 19, count 0 2006.257.12:34:06.59#ibcon#about to read 5, iclass 19, count 0 2006.257.12:34:06.59#ibcon#read 5, iclass 19, count 0 2006.257.12:34:06.59#ibcon#about to read 6, iclass 19, count 0 2006.257.12:34:06.59#ibcon#read 6, iclass 19, count 0 2006.257.12:34:06.59#ibcon#end of sib2, iclass 19, count 0 2006.257.12:34:06.59#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:34:06.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:34:06.59#ibcon#[27=USB\r\n] 2006.257.12:34:06.59#ibcon#*before write, iclass 19, count 0 2006.257.12:34:06.59#ibcon#enter sib2, iclass 19, count 0 2006.257.12:34:06.59#ibcon#flushed, iclass 19, count 0 2006.257.12:34:06.59#ibcon#about to write, iclass 19, count 0 2006.257.12:34:06.59#ibcon#wrote, iclass 19, count 0 2006.257.12:34:06.59#ibcon#about to read 3, iclass 19, count 0 2006.257.12:34:06.62#ibcon#read 3, iclass 19, count 0 2006.257.12:34:06.62#ibcon#about to read 4, iclass 19, count 0 2006.257.12:34:06.62#ibcon#read 4, iclass 19, count 0 2006.257.12:34:06.62#ibcon#about to read 5, iclass 19, count 0 2006.257.12:34:06.62#ibcon#read 5, iclass 19, count 0 2006.257.12:34:06.62#ibcon#about to read 6, iclass 19, count 0 2006.257.12:34:06.62#ibcon#read 6, iclass 19, count 0 2006.257.12:34:06.62#ibcon#end of sib2, iclass 19, count 0 2006.257.12:34:06.62#ibcon#*after write, iclass 19, count 0 2006.257.12:34:06.62#ibcon#*before return 0, iclass 19, count 0 2006.257.12:34:06.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:06.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:34:06.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:34:06.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:34:06.62$vck44/vblo=6,719.99 2006.257.12:34:06.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.12:34:06.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.12:34:06.62#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:06.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:06.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:06.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:06.62#ibcon#enter wrdev, iclass 21, count 0 2006.257.12:34:06.62#ibcon#first serial, iclass 21, count 0 2006.257.12:34:06.62#ibcon#enter sib2, iclass 21, count 0 2006.257.12:34:06.62#ibcon#flushed, iclass 21, count 0 2006.257.12:34:06.62#ibcon#about to write, iclass 21, count 0 2006.257.12:34:06.62#ibcon#wrote, iclass 21, count 0 2006.257.12:34:06.62#ibcon#about to read 3, iclass 21, count 0 2006.257.12:34:06.64#ibcon#read 3, iclass 21, count 0 2006.257.12:34:06.64#ibcon#about to read 4, iclass 21, count 0 2006.257.12:34:06.64#ibcon#read 4, iclass 21, count 0 2006.257.12:34:06.64#ibcon#about to read 5, iclass 21, count 0 2006.257.12:34:06.64#ibcon#read 5, iclass 21, count 0 2006.257.12:34:06.64#ibcon#about to read 6, iclass 21, count 0 2006.257.12:34:06.64#ibcon#read 6, iclass 21, count 0 2006.257.12:34:06.64#ibcon#end of sib2, iclass 21, count 0 2006.257.12:34:06.64#ibcon#*mode == 0, iclass 21, count 0 2006.257.12:34:06.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.12:34:06.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:34:06.64#ibcon#*before write, iclass 21, count 0 2006.257.12:34:06.64#ibcon#enter sib2, iclass 21, count 0 2006.257.12:34:06.64#ibcon#flushed, iclass 21, count 0 2006.257.12:34:06.64#ibcon#about to write, iclass 21, count 0 2006.257.12:34:06.64#ibcon#wrote, iclass 21, count 0 2006.257.12:34:06.64#ibcon#about to read 3, iclass 21, count 0 2006.257.12:34:06.68#ibcon#read 3, iclass 21, count 0 2006.257.12:34:06.68#ibcon#about to read 4, iclass 21, count 0 2006.257.12:34:06.68#ibcon#read 4, iclass 21, count 0 2006.257.12:34:06.68#ibcon#about to read 5, iclass 21, count 0 2006.257.12:34:06.68#ibcon#read 5, iclass 21, count 0 2006.257.12:34:06.68#ibcon#about to read 6, iclass 21, count 0 2006.257.12:34:06.68#ibcon#read 6, iclass 21, count 0 2006.257.12:34:06.68#ibcon#end of sib2, iclass 21, count 0 2006.257.12:34:06.68#ibcon#*after write, iclass 21, count 0 2006.257.12:34:06.68#ibcon#*before return 0, iclass 21, count 0 2006.257.12:34:06.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:06.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:34:06.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.12:34:06.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.12:34:06.68$vck44/vb=6,4 2006.257.12:34:06.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.12:34:06.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.12:34:06.68#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:06.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:06.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:06.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:06.74#ibcon#enter wrdev, iclass 23, count 2 2006.257.12:34:06.74#ibcon#first serial, iclass 23, count 2 2006.257.12:34:06.74#ibcon#enter sib2, iclass 23, count 2 2006.257.12:34:06.74#ibcon#flushed, iclass 23, count 2 2006.257.12:34:06.74#ibcon#about to write, iclass 23, count 2 2006.257.12:34:06.74#ibcon#wrote, iclass 23, count 2 2006.257.12:34:06.74#ibcon#about to read 3, iclass 23, count 2 2006.257.12:34:06.76#ibcon#read 3, iclass 23, count 2 2006.257.12:34:06.76#ibcon#about to read 4, iclass 23, count 2 2006.257.12:34:06.76#ibcon#read 4, iclass 23, count 2 2006.257.12:34:06.76#ibcon#about to read 5, iclass 23, count 2 2006.257.12:34:06.76#ibcon#read 5, iclass 23, count 2 2006.257.12:34:06.76#ibcon#about to read 6, iclass 23, count 2 2006.257.12:34:06.76#ibcon#read 6, iclass 23, count 2 2006.257.12:34:06.76#ibcon#end of sib2, iclass 23, count 2 2006.257.12:34:06.76#ibcon#*mode == 0, iclass 23, count 2 2006.257.12:34:06.76#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.12:34:06.76#ibcon#[27=AT06-04\r\n] 2006.257.12:34:06.76#ibcon#*before write, iclass 23, count 2 2006.257.12:34:06.76#ibcon#enter sib2, iclass 23, count 2 2006.257.12:34:06.76#ibcon#flushed, iclass 23, count 2 2006.257.12:34:06.76#ibcon#about to write, iclass 23, count 2 2006.257.12:34:06.76#ibcon#wrote, iclass 23, count 2 2006.257.12:34:06.76#ibcon#about to read 3, iclass 23, count 2 2006.257.12:34:06.79#ibcon#read 3, iclass 23, count 2 2006.257.12:34:06.79#ibcon#about to read 4, iclass 23, count 2 2006.257.12:34:06.79#ibcon#read 4, iclass 23, count 2 2006.257.12:34:06.79#ibcon#about to read 5, iclass 23, count 2 2006.257.12:34:06.79#ibcon#read 5, iclass 23, count 2 2006.257.12:34:06.79#ibcon#about to read 6, iclass 23, count 2 2006.257.12:34:06.79#ibcon#read 6, iclass 23, count 2 2006.257.12:34:06.79#ibcon#end of sib2, iclass 23, count 2 2006.257.12:34:06.79#ibcon#*after write, iclass 23, count 2 2006.257.12:34:06.79#ibcon#*before return 0, iclass 23, count 2 2006.257.12:34:06.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:06.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:34:06.79#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.12:34:06.79#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:06.79#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:06.91#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:06.91#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:06.91#ibcon#enter wrdev, iclass 23, count 0 2006.257.12:34:06.91#ibcon#first serial, iclass 23, count 0 2006.257.12:34:06.91#ibcon#enter sib2, iclass 23, count 0 2006.257.12:34:06.91#ibcon#flushed, iclass 23, count 0 2006.257.12:34:06.91#ibcon#about to write, iclass 23, count 0 2006.257.12:34:06.91#ibcon#wrote, iclass 23, count 0 2006.257.12:34:06.91#ibcon#about to read 3, iclass 23, count 0 2006.257.12:34:06.93#ibcon#read 3, iclass 23, count 0 2006.257.12:34:06.93#ibcon#about to read 4, iclass 23, count 0 2006.257.12:34:06.93#ibcon#read 4, iclass 23, count 0 2006.257.12:34:06.93#ibcon#about to read 5, iclass 23, count 0 2006.257.12:34:06.93#ibcon#read 5, iclass 23, count 0 2006.257.12:34:06.93#ibcon#about to read 6, iclass 23, count 0 2006.257.12:34:06.93#ibcon#read 6, iclass 23, count 0 2006.257.12:34:06.93#ibcon#end of sib2, iclass 23, count 0 2006.257.12:34:06.93#ibcon#*mode == 0, iclass 23, count 0 2006.257.12:34:06.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.12:34:06.93#ibcon#[27=USB\r\n] 2006.257.12:34:06.93#ibcon#*before write, iclass 23, count 0 2006.257.12:34:06.93#ibcon#enter sib2, iclass 23, count 0 2006.257.12:34:06.93#ibcon#flushed, iclass 23, count 0 2006.257.12:34:06.93#ibcon#about to write, iclass 23, count 0 2006.257.12:34:06.93#ibcon#wrote, iclass 23, count 0 2006.257.12:34:06.93#ibcon#about to read 3, iclass 23, count 0 2006.257.12:34:06.96#ibcon#read 3, iclass 23, count 0 2006.257.12:34:06.96#ibcon#about to read 4, iclass 23, count 0 2006.257.12:34:06.96#ibcon#read 4, iclass 23, count 0 2006.257.12:34:06.96#ibcon#about to read 5, iclass 23, count 0 2006.257.12:34:06.96#ibcon#read 5, iclass 23, count 0 2006.257.12:34:06.96#ibcon#about to read 6, iclass 23, count 0 2006.257.12:34:06.96#ibcon#read 6, iclass 23, count 0 2006.257.12:34:06.96#ibcon#end of sib2, iclass 23, count 0 2006.257.12:34:06.96#ibcon#*after write, iclass 23, count 0 2006.257.12:34:06.96#ibcon#*before return 0, iclass 23, count 0 2006.257.12:34:06.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:06.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:34:06.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.12:34:06.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.12:34:06.96$vck44/vblo=7,734.99 2006.257.12:34:06.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.12:34:06.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.12:34:06.96#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:06.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:06.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:06.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:06.96#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:34:06.96#ibcon#first serial, iclass 25, count 0 2006.257.12:34:06.96#ibcon#enter sib2, iclass 25, count 0 2006.257.12:34:06.96#ibcon#flushed, iclass 25, count 0 2006.257.12:34:06.96#ibcon#about to write, iclass 25, count 0 2006.257.12:34:06.96#ibcon#wrote, iclass 25, count 0 2006.257.12:34:06.96#ibcon#about to read 3, iclass 25, count 0 2006.257.12:34:06.98#ibcon#read 3, iclass 25, count 0 2006.257.12:34:06.98#ibcon#about to read 4, iclass 25, count 0 2006.257.12:34:06.98#ibcon#read 4, iclass 25, count 0 2006.257.12:34:06.98#ibcon#about to read 5, iclass 25, count 0 2006.257.12:34:06.98#ibcon#read 5, iclass 25, count 0 2006.257.12:34:06.98#ibcon#about to read 6, iclass 25, count 0 2006.257.12:34:06.98#ibcon#read 6, iclass 25, count 0 2006.257.12:34:06.98#ibcon#end of sib2, iclass 25, count 0 2006.257.12:34:06.98#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:34:06.98#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:34:06.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:34:06.98#ibcon#*before write, iclass 25, count 0 2006.257.12:34:06.98#ibcon#enter sib2, iclass 25, count 0 2006.257.12:34:06.98#ibcon#flushed, iclass 25, count 0 2006.257.12:34:06.98#ibcon#about to write, iclass 25, count 0 2006.257.12:34:06.98#ibcon#wrote, iclass 25, count 0 2006.257.12:34:06.98#ibcon#about to read 3, iclass 25, count 0 2006.257.12:34:07.02#ibcon#read 3, iclass 25, count 0 2006.257.12:34:07.02#ibcon#about to read 4, iclass 25, count 0 2006.257.12:34:07.02#ibcon#read 4, iclass 25, count 0 2006.257.12:34:07.02#ibcon#about to read 5, iclass 25, count 0 2006.257.12:34:07.02#ibcon#read 5, iclass 25, count 0 2006.257.12:34:07.02#ibcon#about to read 6, iclass 25, count 0 2006.257.12:34:07.02#ibcon#read 6, iclass 25, count 0 2006.257.12:34:07.02#ibcon#end of sib2, iclass 25, count 0 2006.257.12:34:07.02#ibcon#*after write, iclass 25, count 0 2006.257.12:34:07.02#ibcon#*before return 0, iclass 25, count 0 2006.257.12:34:07.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:07.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:34:07.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:34:07.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:34:07.02$vck44/vb=7,4 2006.257.12:34:07.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.12:34:07.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.12:34:07.02#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:07.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:07.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:07.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:07.08#ibcon#enter wrdev, iclass 27, count 2 2006.257.12:34:07.08#ibcon#first serial, iclass 27, count 2 2006.257.12:34:07.08#ibcon#enter sib2, iclass 27, count 2 2006.257.12:34:07.08#ibcon#flushed, iclass 27, count 2 2006.257.12:34:07.08#ibcon#about to write, iclass 27, count 2 2006.257.12:34:07.08#ibcon#wrote, iclass 27, count 2 2006.257.12:34:07.08#ibcon#about to read 3, iclass 27, count 2 2006.257.12:34:07.10#ibcon#read 3, iclass 27, count 2 2006.257.12:34:07.10#ibcon#about to read 4, iclass 27, count 2 2006.257.12:34:07.10#ibcon#read 4, iclass 27, count 2 2006.257.12:34:07.10#ibcon#about to read 5, iclass 27, count 2 2006.257.12:34:07.10#ibcon#read 5, iclass 27, count 2 2006.257.12:34:07.10#ibcon#about to read 6, iclass 27, count 2 2006.257.12:34:07.10#ibcon#read 6, iclass 27, count 2 2006.257.12:34:07.10#ibcon#end of sib2, iclass 27, count 2 2006.257.12:34:07.10#ibcon#*mode == 0, iclass 27, count 2 2006.257.12:34:07.10#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.12:34:07.10#ibcon#[27=AT07-04\r\n] 2006.257.12:34:07.10#ibcon#*before write, iclass 27, count 2 2006.257.12:34:07.10#ibcon#enter sib2, iclass 27, count 2 2006.257.12:34:07.10#ibcon#flushed, iclass 27, count 2 2006.257.12:34:07.10#ibcon#about to write, iclass 27, count 2 2006.257.12:34:07.10#ibcon#wrote, iclass 27, count 2 2006.257.12:34:07.10#ibcon#about to read 3, iclass 27, count 2 2006.257.12:34:07.13#ibcon#read 3, iclass 27, count 2 2006.257.12:34:07.13#ibcon#about to read 4, iclass 27, count 2 2006.257.12:34:07.13#ibcon#read 4, iclass 27, count 2 2006.257.12:34:07.13#ibcon#about to read 5, iclass 27, count 2 2006.257.12:34:07.13#ibcon#read 5, iclass 27, count 2 2006.257.12:34:07.13#ibcon#about to read 6, iclass 27, count 2 2006.257.12:34:07.13#ibcon#read 6, iclass 27, count 2 2006.257.12:34:07.13#ibcon#end of sib2, iclass 27, count 2 2006.257.12:34:07.13#ibcon#*after write, iclass 27, count 2 2006.257.12:34:07.13#ibcon#*before return 0, iclass 27, count 2 2006.257.12:34:07.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:07.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:34:07.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.12:34:07.13#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:07.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:07.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:07.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:07.25#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:34:07.25#ibcon#first serial, iclass 27, count 0 2006.257.12:34:07.25#ibcon#enter sib2, iclass 27, count 0 2006.257.12:34:07.25#ibcon#flushed, iclass 27, count 0 2006.257.12:34:07.25#ibcon#about to write, iclass 27, count 0 2006.257.12:34:07.25#ibcon#wrote, iclass 27, count 0 2006.257.12:34:07.25#ibcon#about to read 3, iclass 27, count 0 2006.257.12:34:07.27#ibcon#read 3, iclass 27, count 0 2006.257.12:34:07.27#ibcon#about to read 4, iclass 27, count 0 2006.257.12:34:07.27#ibcon#read 4, iclass 27, count 0 2006.257.12:34:07.27#ibcon#about to read 5, iclass 27, count 0 2006.257.12:34:07.27#ibcon#read 5, iclass 27, count 0 2006.257.12:34:07.27#ibcon#about to read 6, iclass 27, count 0 2006.257.12:34:07.27#ibcon#read 6, iclass 27, count 0 2006.257.12:34:07.27#ibcon#end of sib2, iclass 27, count 0 2006.257.12:34:07.27#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:34:07.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:34:07.27#ibcon#[27=USB\r\n] 2006.257.12:34:07.27#ibcon#*before write, iclass 27, count 0 2006.257.12:34:07.27#ibcon#enter sib2, iclass 27, count 0 2006.257.12:34:07.27#ibcon#flushed, iclass 27, count 0 2006.257.12:34:07.27#ibcon#about to write, iclass 27, count 0 2006.257.12:34:07.27#ibcon#wrote, iclass 27, count 0 2006.257.12:34:07.27#ibcon#about to read 3, iclass 27, count 0 2006.257.12:34:07.30#ibcon#read 3, iclass 27, count 0 2006.257.12:34:07.30#ibcon#about to read 4, iclass 27, count 0 2006.257.12:34:07.30#ibcon#read 4, iclass 27, count 0 2006.257.12:34:07.30#ibcon#about to read 5, iclass 27, count 0 2006.257.12:34:07.30#ibcon#read 5, iclass 27, count 0 2006.257.12:34:07.30#ibcon#about to read 6, iclass 27, count 0 2006.257.12:34:07.30#ibcon#read 6, iclass 27, count 0 2006.257.12:34:07.30#ibcon#end of sib2, iclass 27, count 0 2006.257.12:34:07.30#ibcon#*after write, iclass 27, count 0 2006.257.12:34:07.30#ibcon#*before return 0, iclass 27, count 0 2006.257.12:34:07.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:07.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:34:07.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:34:07.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:34:07.30$vck44/vblo=8,744.99 2006.257.12:34:07.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.12:34:07.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.12:34:07.30#ibcon#ireg 17 cls_cnt 0 2006.257.12:34:07.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:07.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:07.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:07.30#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:34:07.30#ibcon#first serial, iclass 29, count 0 2006.257.12:34:07.30#ibcon#enter sib2, iclass 29, count 0 2006.257.12:34:07.30#ibcon#flushed, iclass 29, count 0 2006.257.12:34:07.30#ibcon#about to write, iclass 29, count 0 2006.257.12:34:07.30#ibcon#wrote, iclass 29, count 0 2006.257.12:34:07.30#ibcon#about to read 3, iclass 29, count 0 2006.257.12:34:07.32#ibcon#read 3, iclass 29, count 0 2006.257.12:34:07.32#ibcon#about to read 4, iclass 29, count 0 2006.257.12:34:07.32#ibcon#read 4, iclass 29, count 0 2006.257.12:34:07.32#ibcon#about to read 5, iclass 29, count 0 2006.257.12:34:07.32#ibcon#read 5, iclass 29, count 0 2006.257.12:34:07.32#ibcon#about to read 6, iclass 29, count 0 2006.257.12:34:07.32#ibcon#read 6, iclass 29, count 0 2006.257.12:34:07.32#ibcon#end of sib2, iclass 29, count 0 2006.257.12:34:07.32#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:34:07.32#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:34:07.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:34:07.32#ibcon#*before write, iclass 29, count 0 2006.257.12:34:07.32#ibcon#enter sib2, iclass 29, count 0 2006.257.12:34:07.32#ibcon#flushed, iclass 29, count 0 2006.257.12:34:07.32#ibcon#about to write, iclass 29, count 0 2006.257.12:34:07.32#ibcon#wrote, iclass 29, count 0 2006.257.12:34:07.32#ibcon#about to read 3, iclass 29, count 0 2006.257.12:34:07.36#ibcon#read 3, iclass 29, count 0 2006.257.12:34:07.36#ibcon#about to read 4, iclass 29, count 0 2006.257.12:34:07.36#ibcon#read 4, iclass 29, count 0 2006.257.12:34:07.36#ibcon#about to read 5, iclass 29, count 0 2006.257.12:34:07.36#ibcon#read 5, iclass 29, count 0 2006.257.12:34:07.36#ibcon#about to read 6, iclass 29, count 0 2006.257.12:34:07.36#ibcon#read 6, iclass 29, count 0 2006.257.12:34:07.36#ibcon#end of sib2, iclass 29, count 0 2006.257.12:34:07.36#ibcon#*after write, iclass 29, count 0 2006.257.12:34:07.36#ibcon#*before return 0, iclass 29, count 0 2006.257.12:34:07.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:07.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:34:07.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:34:07.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:34:07.36$vck44/vb=8,4 2006.257.12:34:07.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.12:34:07.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.12:34:07.36#ibcon#ireg 11 cls_cnt 2 2006.257.12:34:07.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:07.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:07.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:07.42#ibcon#enter wrdev, iclass 31, count 2 2006.257.12:34:07.42#ibcon#first serial, iclass 31, count 2 2006.257.12:34:07.42#ibcon#enter sib2, iclass 31, count 2 2006.257.12:34:07.42#ibcon#flushed, iclass 31, count 2 2006.257.12:34:07.42#ibcon#about to write, iclass 31, count 2 2006.257.12:34:07.42#ibcon#wrote, iclass 31, count 2 2006.257.12:34:07.42#ibcon#about to read 3, iclass 31, count 2 2006.257.12:34:07.44#ibcon#read 3, iclass 31, count 2 2006.257.12:34:07.44#ibcon#about to read 4, iclass 31, count 2 2006.257.12:34:07.44#ibcon#read 4, iclass 31, count 2 2006.257.12:34:07.44#ibcon#about to read 5, iclass 31, count 2 2006.257.12:34:07.44#ibcon#read 5, iclass 31, count 2 2006.257.12:34:07.44#ibcon#about to read 6, iclass 31, count 2 2006.257.12:34:07.44#ibcon#read 6, iclass 31, count 2 2006.257.12:34:07.44#ibcon#end of sib2, iclass 31, count 2 2006.257.12:34:07.44#ibcon#*mode == 0, iclass 31, count 2 2006.257.12:34:07.44#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.12:34:07.44#ibcon#[27=AT08-04\r\n] 2006.257.12:34:07.44#ibcon#*before write, iclass 31, count 2 2006.257.12:34:07.44#ibcon#enter sib2, iclass 31, count 2 2006.257.12:34:07.44#ibcon#flushed, iclass 31, count 2 2006.257.12:34:07.44#ibcon#about to write, iclass 31, count 2 2006.257.12:34:07.44#ibcon#wrote, iclass 31, count 2 2006.257.12:34:07.44#ibcon#about to read 3, iclass 31, count 2 2006.257.12:34:07.47#ibcon#read 3, iclass 31, count 2 2006.257.12:34:07.47#ibcon#about to read 4, iclass 31, count 2 2006.257.12:34:07.47#ibcon#read 4, iclass 31, count 2 2006.257.12:34:07.47#ibcon#about to read 5, iclass 31, count 2 2006.257.12:34:07.47#ibcon#read 5, iclass 31, count 2 2006.257.12:34:07.47#ibcon#about to read 6, iclass 31, count 2 2006.257.12:34:07.47#ibcon#read 6, iclass 31, count 2 2006.257.12:34:07.47#ibcon#end of sib2, iclass 31, count 2 2006.257.12:34:07.47#ibcon#*after write, iclass 31, count 2 2006.257.12:34:07.47#ibcon#*before return 0, iclass 31, count 2 2006.257.12:34:07.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:07.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:34:07.47#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.12:34:07.47#ibcon#ireg 7 cls_cnt 0 2006.257.12:34:07.47#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:07.59#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:07.59#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:07.59#ibcon#enter wrdev, iclass 31, count 0 2006.257.12:34:07.59#ibcon#first serial, iclass 31, count 0 2006.257.12:34:07.59#ibcon#enter sib2, iclass 31, count 0 2006.257.12:34:07.59#ibcon#flushed, iclass 31, count 0 2006.257.12:34:07.59#ibcon#about to write, iclass 31, count 0 2006.257.12:34:07.59#ibcon#wrote, iclass 31, count 0 2006.257.12:34:07.59#ibcon#about to read 3, iclass 31, count 0 2006.257.12:34:07.61#ibcon#read 3, iclass 31, count 0 2006.257.12:34:07.61#ibcon#about to read 4, iclass 31, count 0 2006.257.12:34:07.61#ibcon#read 4, iclass 31, count 0 2006.257.12:34:07.61#ibcon#about to read 5, iclass 31, count 0 2006.257.12:34:07.61#ibcon#read 5, iclass 31, count 0 2006.257.12:34:07.61#ibcon#about to read 6, iclass 31, count 0 2006.257.12:34:07.61#ibcon#read 6, iclass 31, count 0 2006.257.12:34:07.61#ibcon#end of sib2, iclass 31, count 0 2006.257.12:34:07.61#ibcon#*mode == 0, iclass 31, count 0 2006.257.12:34:07.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.12:34:07.61#ibcon#[27=USB\r\n] 2006.257.12:34:07.61#ibcon#*before write, iclass 31, count 0 2006.257.12:34:07.61#ibcon#enter sib2, iclass 31, count 0 2006.257.12:34:07.61#ibcon#flushed, iclass 31, count 0 2006.257.12:34:07.61#ibcon#about to write, iclass 31, count 0 2006.257.12:34:07.61#ibcon#wrote, iclass 31, count 0 2006.257.12:34:07.61#ibcon#about to read 3, iclass 31, count 0 2006.257.12:34:07.64#ibcon#read 3, iclass 31, count 0 2006.257.12:34:07.64#ibcon#about to read 4, iclass 31, count 0 2006.257.12:34:07.64#ibcon#read 4, iclass 31, count 0 2006.257.12:34:07.64#ibcon#about to read 5, iclass 31, count 0 2006.257.12:34:07.64#ibcon#read 5, iclass 31, count 0 2006.257.12:34:07.64#ibcon#about to read 6, iclass 31, count 0 2006.257.12:34:07.64#ibcon#read 6, iclass 31, count 0 2006.257.12:34:07.64#ibcon#end of sib2, iclass 31, count 0 2006.257.12:34:07.64#ibcon#*after write, iclass 31, count 0 2006.257.12:34:07.64#ibcon#*before return 0, iclass 31, count 0 2006.257.12:34:07.64#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:07.64#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:34:07.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.12:34:07.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.12:34:07.64$vck44/vabw=wide 2006.257.12:34:07.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.12:34:07.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.12:34:07.64#ibcon#ireg 8 cls_cnt 0 2006.257.12:34:07.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:07.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:07.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:07.64#ibcon#enter wrdev, iclass 33, count 0 2006.257.12:34:07.64#ibcon#first serial, iclass 33, count 0 2006.257.12:34:07.64#ibcon#enter sib2, iclass 33, count 0 2006.257.12:34:07.64#ibcon#flushed, iclass 33, count 0 2006.257.12:34:07.64#ibcon#about to write, iclass 33, count 0 2006.257.12:34:07.64#ibcon#wrote, iclass 33, count 0 2006.257.12:34:07.64#ibcon#about to read 3, iclass 33, count 0 2006.257.12:34:07.66#ibcon#read 3, iclass 33, count 0 2006.257.12:34:07.66#ibcon#about to read 4, iclass 33, count 0 2006.257.12:34:07.66#ibcon#read 4, iclass 33, count 0 2006.257.12:34:07.66#ibcon#about to read 5, iclass 33, count 0 2006.257.12:34:07.66#ibcon#read 5, iclass 33, count 0 2006.257.12:34:07.66#ibcon#about to read 6, iclass 33, count 0 2006.257.12:34:07.66#ibcon#read 6, iclass 33, count 0 2006.257.12:34:07.66#ibcon#end of sib2, iclass 33, count 0 2006.257.12:34:07.66#ibcon#*mode == 0, iclass 33, count 0 2006.257.12:34:07.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.12:34:07.66#ibcon#[25=BW32\r\n] 2006.257.12:34:07.66#ibcon#*before write, iclass 33, count 0 2006.257.12:34:07.66#ibcon#enter sib2, iclass 33, count 0 2006.257.12:34:07.66#ibcon#flushed, iclass 33, count 0 2006.257.12:34:07.66#ibcon#about to write, iclass 33, count 0 2006.257.12:34:07.66#ibcon#wrote, iclass 33, count 0 2006.257.12:34:07.66#ibcon#about to read 3, iclass 33, count 0 2006.257.12:34:07.69#ibcon#read 3, iclass 33, count 0 2006.257.12:34:07.69#ibcon#about to read 4, iclass 33, count 0 2006.257.12:34:07.69#ibcon#read 4, iclass 33, count 0 2006.257.12:34:07.69#ibcon#about to read 5, iclass 33, count 0 2006.257.12:34:07.69#ibcon#read 5, iclass 33, count 0 2006.257.12:34:07.69#ibcon#about to read 6, iclass 33, count 0 2006.257.12:34:07.69#ibcon#read 6, iclass 33, count 0 2006.257.12:34:07.69#ibcon#end of sib2, iclass 33, count 0 2006.257.12:34:07.69#ibcon#*after write, iclass 33, count 0 2006.257.12:34:07.69#ibcon#*before return 0, iclass 33, count 0 2006.257.12:34:07.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:07.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:34:07.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.12:34:07.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.12:34:07.69$vck44/vbbw=wide 2006.257.12:34:07.69#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.12:34:07.69#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.12:34:07.69#ibcon#ireg 8 cls_cnt 0 2006.257.12:34:07.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:34:07.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:34:07.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:34:07.76#ibcon#enter wrdev, iclass 35, count 0 2006.257.12:34:07.76#ibcon#first serial, iclass 35, count 0 2006.257.12:34:07.76#ibcon#enter sib2, iclass 35, count 0 2006.257.12:34:07.76#ibcon#flushed, iclass 35, count 0 2006.257.12:34:07.76#ibcon#about to write, iclass 35, count 0 2006.257.12:34:07.76#ibcon#wrote, iclass 35, count 0 2006.257.12:34:07.76#ibcon#about to read 3, iclass 35, count 0 2006.257.12:34:07.78#ibcon#read 3, iclass 35, count 0 2006.257.12:34:07.78#ibcon#about to read 4, iclass 35, count 0 2006.257.12:34:07.78#ibcon#read 4, iclass 35, count 0 2006.257.12:34:07.78#ibcon#about to read 5, iclass 35, count 0 2006.257.12:34:07.78#ibcon#read 5, iclass 35, count 0 2006.257.12:34:07.78#ibcon#about to read 6, iclass 35, count 0 2006.257.12:34:07.78#ibcon#read 6, iclass 35, count 0 2006.257.12:34:07.78#ibcon#end of sib2, iclass 35, count 0 2006.257.12:34:07.78#ibcon#*mode == 0, iclass 35, count 0 2006.257.12:34:07.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.12:34:07.78#ibcon#[27=BW32\r\n] 2006.257.12:34:07.78#ibcon#*before write, iclass 35, count 0 2006.257.12:34:07.78#ibcon#enter sib2, iclass 35, count 0 2006.257.12:34:07.78#ibcon#flushed, iclass 35, count 0 2006.257.12:34:07.78#ibcon#about to write, iclass 35, count 0 2006.257.12:34:07.78#ibcon#wrote, iclass 35, count 0 2006.257.12:34:07.78#ibcon#about to read 3, iclass 35, count 0 2006.257.12:34:07.81#ibcon#read 3, iclass 35, count 0 2006.257.12:34:07.81#ibcon#about to read 4, iclass 35, count 0 2006.257.12:34:07.81#ibcon#read 4, iclass 35, count 0 2006.257.12:34:07.81#ibcon#about to read 5, iclass 35, count 0 2006.257.12:34:07.81#ibcon#read 5, iclass 35, count 0 2006.257.12:34:07.81#ibcon#about to read 6, iclass 35, count 0 2006.257.12:34:07.81#ibcon#read 6, iclass 35, count 0 2006.257.12:34:07.81#ibcon#end of sib2, iclass 35, count 0 2006.257.12:34:07.81#ibcon#*after write, iclass 35, count 0 2006.257.12:34:07.81#ibcon#*before return 0, iclass 35, count 0 2006.257.12:34:07.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:34:07.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:34:07.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.12:34:07.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.12:34:07.81$setupk4/ifdk4 2006.257.12:34:07.81$ifdk4/lo= 2006.257.12:34:07.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:34:07.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:34:07.81$ifdk4/patch= 2006.257.12:34:07.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:34:07.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:34:07.81$setupk4/!*+20s 2006.257.12:34:16.34#abcon#<5=/14 1.9 5.1 17.94 961013.8\r\n> 2006.257.12:34:16.36#abcon#{5=INTERFACE CLEAR} 2006.257.12:34:16.42#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:34:22.25$setupk4/"tpicd 2006.257.12:34:22.25$setupk4/echo=off 2006.257.12:34:22.25$setupk4/xlog=off 2006.257.12:34:22.25:!2006.257.12:35:44 2006.257.12:34:25.14#trakl#Source acquired 2006.257.12:34:27.14#flagr#flagr/antenna,acquired 2006.257.12:35:44.00:preob 2006.257.12:35:44.14/onsource/TRACKING 2006.257.12:35:44.14:!2006.257.12:35:54 2006.257.12:35:54.00:"tape 2006.257.12:35:54.00:"st=record 2006.257.12:35:54.00:data_valid=on 2006.257.12:35:54.00:midob 2006.257.12:35:54.14/onsource/TRACKING 2006.257.12:35:54.14/wx/17.93,1013.8,96 2006.257.12:35:54.29/cable/+6.4794E-03 2006.257.12:35:55.38/va/01,08,usb,yes,30,33 2006.257.12:35:55.38/va/02,07,usb,yes,33,33 2006.257.12:35:55.38/va/03,08,usb,yes,30,31 2006.257.12:35:55.38/va/04,07,usb,yes,34,36 2006.257.12:35:55.38/va/05,04,usb,yes,31,31 2006.257.12:35:55.38/va/06,04,usb,yes,34,34 2006.257.12:35:55.38/va/07,04,usb,yes,35,35 2006.257.12:35:55.38/va/08,04,usb,yes,29,36 2006.257.12:35:55.61/valo/01,524.99,yes,locked 2006.257.12:35:55.61/valo/02,534.99,yes,locked 2006.257.12:35:55.61/valo/03,564.99,yes,locked 2006.257.12:35:55.61/valo/04,624.99,yes,locked 2006.257.12:35:55.61/valo/05,734.99,yes,locked 2006.257.12:35:55.61/valo/06,814.99,yes,locked 2006.257.12:35:55.61/valo/07,864.99,yes,locked 2006.257.12:35:55.61/valo/08,884.99,yes,locked 2006.257.12:35:56.70/vb/01,04,usb,yes,30,28 2006.257.12:35:56.70/vb/02,05,usb,yes,28,28 2006.257.12:35:56.70/vb/03,04,usb,yes,29,32 2006.257.12:35:56.70/vb/04,05,usb,yes,29,28 2006.257.12:35:56.70/vb/05,04,usb,yes,26,28 2006.257.12:35:56.70/vb/06,04,usb,yes,30,27 2006.257.12:35:56.70/vb/07,04,usb,yes,30,30 2006.257.12:35:56.70/vb/08,04,usb,yes,28,31 2006.257.12:35:56.94/vblo/01,629.99,yes,locked 2006.257.12:35:56.94/vblo/02,634.99,yes,locked 2006.257.12:35:56.94/vblo/03,649.99,yes,locked 2006.257.12:35:56.94/vblo/04,679.99,yes,locked 2006.257.12:35:56.94/vblo/05,709.99,yes,locked 2006.257.12:35:56.94/vblo/06,719.99,yes,locked 2006.257.12:35:56.94/vblo/07,734.99,yes,locked 2006.257.12:35:56.94/vblo/08,744.99,yes,locked 2006.257.12:35:57.09/vabw/8 2006.257.12:35:57.24/vbbw/8 2006.257.12:35:57.33/xfe/off,on,15.2 2006.257.12:35:57.72/ifatt/23,28,28,28 2006.257.12:35:58.08/fmout-gps/S +4.55E-07 2006.257.12:35:58.12:!2006.257.12:38:34 2006.257.12:38:34.02:data_valid=off 2006.257.12:38:34.02:"et 2006.257.12:38:34.02:!+3s 2006.257.12:38:37.04:"tape 2006.257.12:38:37.05:postob 2006.257.12:38:37.28/cable/+6.4800E-03 2006.257.12:38:37.28/wx/17.90,1013.8,96 2006.257.12:38:37.34/fmout-gps/S +4.54E-07 2006.257.12:38:37.34:scan_name=257-1244,jd0609,160 2006.257.12:38:37.34:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.12:38:39.14#flagr#flagr/antenna,new-source 2006.257.12:38:39.14:checkk5 2006.257.12:38:39.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:38:39.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:38:40.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:38:40.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:38:41.12/chk_obsdata//k5ts1/T2571235??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:38:41.53/chk_obsdata//k5ts2/T2571235??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:38:41.94/chk_obsdata//k5ts3/T2571235??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:38:42.34/chk_obsdata//k5ts4/T2571235??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:38:43.06/k5log//k5ts1_log_newline 2006.257.12:38:43.76/k5log//k5ts2_log_newline 2006.257.12:38:44.49/k5log//k5ts3_log_newline 2006.257.12:38:45.21/k5log//k5ts4_log_newline 2006.257.12:38:45.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:38:45.23:setupk4=1 2006.257.12:38:45.23$setupk4/echo=on 2006.257.12:38:45.23$setupk4/pcalon 2006.257.12:38:45.23$pcalon/"no phase cal control is implemented here 2006.257.12:38:45.23$setupk4/"tpicd=stop 2006.257.12:38:45.23$setupk4/"rec=synch_on 2006.257.12:38:45.23$setupk4/"rec_mode=128 2006.257.12:38:45.23$setupk4/!* 2006.257.12:38:45.23$setupk4/recpk4 2006.257.12:38:45.23$recpk4/recpatch= 2006.257.12:38:45.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:38:45.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:38:45.23$setupk4/vck44 2006.257.12:38:45.23$vck44/valo=1,524.99 2006.257.12:38:45.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.12:38:45.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.12:38:45.23#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:45.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:45.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:45.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:45.23#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:38:45.23#ibcon#first serial, iclass 40, count 0 2006.257.12:38:45.23#ibcon#enter sib2, iclass 40, count 0 2006.257.12:38:45.23#ibcon#flushed, iclass 40, count 0 2006.257.12:38:45.23#ibcon#about to write, iclass 40, count 0 2006.257.12:38:45.23#ibcon#wrote, iclass 40, count 0 2006.257.12:38:45.23#ibcon#about to read 3, iclass 40, count 0 2006.257.12:38:45.24#ibcon#read 3, iclass 40, count 0 2006.257.12:38:45.24#ibcon#about to read 4, iclass 40, count 0 2006.257.12:38:45.24#ibcon#read 4, iclass 40, count 0 2006.257.12:38:45.24#ibcon#about to read 5, iclass 40, count 0 2006.257.12:38:45.24#ibcon#read 5, iclass 40, count 0 2006.257.12:38:45.24#ibcon#about to read 6, iclass 40, count 0 2006.257.12:38:45.24#ibcon#read 6, iclass 40, count 0 2006.257.12:38:45.25#ibcon#end of sib2, iclass 40, count 0 2006.257.12:38:45.25#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:38:45.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:38:45.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:38:45.25#ibcon#*before write, iclass 40, count 0 2006.257.12:38:45.25#ibcon#enter sib2, iclass 40, count 0 2006.257.12:38:45.25#ibcon#flushed, iclass 40, count 0 2006.257.12:38:45.25#ibcon#about to write, iclass 40, count 0 2006.257.12:38:45.25#ibcon#wrote, iclass 40, count 0 2006.257.12:38:45.25#ibcon#about to read 3, iclass 40, count 0 2006.257.12:38:45.29#ibcon#read 3, iclass 40, count 0 2006.257.12:38:45.29#ibcon#about to read 4, iclass 40, count 0 2006.257.12:38:45.29#ibcon#read 4, iclass 40, count 0 2006.257.12:38:45.29#ibcon#about to read 5, iclass 40, count 0 2006.257.12:38:45.29#ibcon#read 5, iclass 40, count 0 2006.257.12:38:45.29#ibcon#about to read 6, iclass 40, count 0 2006.257.12:38:45.29#ibcon#read 6, iclass 40, count 0 2006.257.12:38:45.29#ibcon#end of sib2, iclass 40, count 0 2006.257.12:38:45.29#ibcon#*after write, iclass 40, count 0 2006.257.12:38:45.30#ibcon#*before return 0, iclass 40, count 0 2006.257.12:38:45.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:45.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:45.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:38:45.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:38:45.30$vck44/va=1,8 2006.257.12:38:45.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.12:38:45.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.12:38:45.30#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:45.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:45.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:45.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:45.30#ibcon#enter wrdev, iclass 4, count 2 2006.257.12:38:45.30#ibcon#first serial, iclass 4, count 2 2006.257.12:38:45.30#ibcon#enter sib2, iclass 4, count 2 2006.257.12:38:45.30#ibcon#flushed, iclass 4, count 2 2006.257.12:38:45.30#ibcon#about to write, iclass 4, count 2 2006.257.12:38:45.30#ibcon#wrote, iclass 4, count 2 2006.257.12:38:45.30#ibcon#about to read 3, iclass 4, count 2 2006.257.12:38:45.31#ibcon#read 3, iclass 4, count 2 2006.257.12:38:45.31#ibcon#about to read 4, iclass 4, count 2 2006.257.12:38:45.31#ibcon#read 4, iclass 4, count 2 2006.257.12:38:45.31#ibcon#about to read 5, iclass 4, count 2 2006.257.12:38:45.31#ibcon#read 5, iclass 4, count 2 2006.257.12:38:45.31#ibcon#about to read 6, iclass 4, count 2 2006.257.12:38:45.31#ibcon#read 6, iclass 4, count 2 2006.257.12:38:45.31#ibcon#end of sib2, iclass 4, count 2 2006.257.12:38:45.31#ibcon#*mode == 0, iclass 4, count 2 2006.257.12:38:45.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.12:38:45.31#ibcon#[25=AT01-08\r\n] 2006.257.12:38:45.32#ibcon#*before write, iclass 4, count 2 2006.257.12:38:45.32#ibcon#enter sib2, iclass 4, count 2 2006.257.12:38:45.32#ibcon#flushed, iclass 4, count 2 2006.257.12:38:45.32#ibcon#about to write, iclass 4, count 2 2006.257.12:38:45.32#ibcon#wrote, iclass 4, count 2 2006.257.12:38:45.32#ibcon#about to read 3, iclass 4, count 2 2006.257.12:38:45.34#ibcon#read 3, iclass 4, count 2 2006.257.12:38:45.34#ibcon#about to read 4, iclass 4, count 2 2006.257.12:38:45.34#ibcon#read 4, iclass 4, count 2 2006.257.12:38:45.34#ibcon#about to read 5, iclass 4, count 2 2006.257.12:38:45.34#ibcon#read 5, iclass 4, count 2 2006.257.12:38:45.34#ibcon#about to read 6, iclass 4, count 2 2006.257.12:38:45.34#ibcon#read 6, iclass 4, count 2 2006.257.12:38:45.34#ibcon#end of sib2, iclass 4, count 2 2006.257.12:38:45.34#ibcon#*after write, iclass 4, count 2 2006.257.12:38:45.35#ibcon#*before return 0, iclass 4, count 2 2006.257.12:38:45.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:45.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:45.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.12:38:45.35#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:45.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:45.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:45.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:45.46#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:38:45.46#ibcon#first serial, iclass 4, count 0 2006.257.12:38:45.46#ibcon#enter sib2, iclass 4, count 0 2006.257.12:38:45.46#ibcon#flushed, iclass 4, count 0 2006.257.12:38:45.46#ibcon#about to write, iclass 4, count 0 2006.257.12:38:45.46#ibcon#wrote, iclass 4, count 0 2006.257.12:38:45.46#ibcon#about to read 3, iclass 4, count 0 2006.257.12:38:45.48#ibcon#read 3, iclass 4, count 0 2006.257.12:38:45.48#ibcon#about to read 4, iclass 4, count 0 2006.257.12:38:45.48#ibcon#read 4, iclass 4, count 0 2006.257.12:38:45.48#ibcon#about to read 5, iclass 4, count 0 2006.257.12:38:45.48#ibcon#read 5, iclass 4, count 0 2006.257.12:38:45.48#ibcon#about to read 6, iclass 4, count 0 2006.257.12:38:45.48#ibcon#read 6, iclass 4, count 0 2006.257.12:38:45.48#ibcon#end of sib2, iclass 4, count 0 2006.257.12:38:45.49#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:38:45.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:38:45.49#ibcon#[25=USB\r\n] 2006.257.12:38:45.49#ibcon#*before write, iclass 4, count 0 2006.257.12:38:45.49#ibcon#enter sib2, iclass 4, count 0 2006.257.12:38:45.49#ibcon#flushed, iclass 4, count 0 2006.257.12:38:45.49#ibcon#about to write, iclass 4, count 0 2006.257.12:38:45.49#ibcon#wrote, iclass 4, count 0 2006.257.12:38:45.49#ibcon#about to read 3, iclass 4, count 0 2006.257.12:38:45.51#ibcon#read 3, iclass 4, count 0 2006.257.12:38:45.51#ibcon#about to read 4, iclass 4, count 0 2006.257.12:38:45.51#ibcon#read 4, iclass 4, count 0 2006.257.12:38:45.51#ibcon#about to read 5, iclass 4, count 0 2006.257.12:38:45.51#ibcon#read 5, iclass 4, count 0 2006.257.12:38:45.51#ibcon#about to read 6, iclass 4, count 0 2006.257.12:38:45.51#ibcon#read 6, iclass 4, count 0 2006.257.12:38:45.51#ibcon#end of sib2, iclass 4, count 0 2006.257.12:38:45.51#ibcon#*after write, iclass 4, count 0 2006.257.12:38:45.51#ibcon#*before return 0, iclass 4, count 0 2006.257.12:38:45.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:45.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:45.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:38:45.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:38:45.52$vck44/valo=2,534.99 2006.257.12:38:45.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.12:38:45.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.12:38:45.52#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:45.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:45.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:45.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:45.52#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:38:45.52#ibcon#first serial, iclass 6, count 0 2006.257.12:38:45.52#ibcon#enter sib2, iclass 6, count 0 2006.257.12:38:45.52#ibcon#flushed, iclass 6, count 0 2006.257.12:38:45.52#ibcon#about to write, iclass 6, count 0 2006.257.12:38:45.52#ibcon#wrote, iclass 6, count 0 2006.257.12:38:45.52#ibcon#about to read 3, iclass 6, count 0 2006.257.12:38:45.53#ibcon#read 3, iclass 6, count 0 2006.257.12:38:45.53#ibcon#about to read 4, iclass 6, count 0 2006.257.12:38:45.53#ibcon#read 4, iclass 6, count 0 2006.257.12:38:45.53#ibcon#about to read 5, iclass 6, count 0 2006.257.12:38:45.53#ibcon#read 5, iclass 6, count 0 2006.257.12:38:45.53#ibcon#about to read 6, iclass 6, count 0 2006.257.12:38:45.53#ibcon#read 6, iclass 6, count 0 2006.257.12:38:45.53#ibcon#end of sib2, iclass 6, count 0 2006.257.12:38:45.53#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:38:45.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:38:45.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:38:45.54#ibcon#*before write, iclass 6, count 0 2006.257.12:38:45.54#ibcon#enter sib2, iclass 6, count 0 2006.257.12:38:45.54#ibcon#flushed, iclass 6, count 0 2006.257.12:38:45.54#ibcon#about to write, iclass 6, count 0 2006.257.12:38:45.54#ibcon#wrote, iclass 6, count 0 2006.257.12:38:45.54#ibcon#about to read 3, iclass 6, count 0 2006.257.12:38:45.57#ibcon#read 3, iclass 6, count 0 2006.257.12:38:45.57#ibcon#about to read 4, iclass 6, count 0 2006.257.12:38:45.57#ibcon#read 4, iclass 6, count 0 2006.257.12:38:45.57#ibcon#about to read 5, iclass 6, count 0 2006.257.12:38:45.57#ibcon#read 5, iclass 6, count 0 2006.257.12:38:45.57#ibcon#about to read 6, iclass 6, count 0 2006.257.12:38:45.57#ibcon#read 6, iclass 6, count 0 2006.257.12:38:45.57#ibcon#end of sib2, iclass 6, count 0 2006.257.12:38:45.57#ibcon#*after write, iclass 6, count 0 2006.257.12:38:45.57#ibcon#*before return 0, iclass 6, count 0 2006.257.12:38:45.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:45.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:45.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:38:45.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:38:45.58$vck44/va=2,7 2006.257.12:38:45.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.12:38:45.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.12:38:45.58#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:45.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:45.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:45.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:45.63#ibcon#enter wrdev, iclass 10, count 2 2006.257.12:38:45.63#ibcon#first serial, iclass 10, count 2 2006.257.12:38:45.63#ibcon#enter sib2, iclass 10, count 2 2006.257.12:38:45.63#ibcon#flushed, iclass 10, count 2 2006.257.12:38:45.63#ibcon#about to write, iclass 10, count 2 2006.257.12:38:45.64#ibcon#wrote, iclass 10, count 2 2006.257.12:38:45.64#ibcon#about to read 3, iclass 10, count 2 2006.257.12:38:45.65#ibcon#read 3, iclass 10, count 2 2006.257.12:38:45.65#ibcon#about to read 4, iclass 10, count 2 2006.257.12:38:45.65#ibcon#read 4, iclass 10, count 2 2006.257.12:38:45.65#ibcon#about to read 5, iclass 10, count 2 2006.257.12:38:45.65#ibcon#read 5, iclass 10, count 2 2006.257.12:38:45.65#ibcon#about to read 6, iclass 10, count 2 2006.257.12:38:45.65#ibcon#read 6, iclass 10, count 2 2006.257.12:38:45.65#ibcon#end of sib2, iclass 10, count 2 2006.257.12:38:45.65#ibcon#*mode == 0, iclass 10, count 2 2006.257.12:38:45.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.12:38:45.65#ibcon#[25=AT02-07\r\n] 2006.257.12:38:45.66#ibcon#*before write, iclass 10, count 2 2006.257.12:38:45.66#ibcon#enter sib2, iclass 10, count 2 2006.257.12:38:45.66#ibcon#flushed, iclass 10, count 2 2006.257.12:38:45.66#ibcon#about to write, iclass 10, count 2 2006.257.12:38:45.66#ibcon#wrote, iclass 10, count 2 2006.257.12:38:45.66#ibcon#about to read 3, iclass 10, count 2 2006.257.12:38:45.68#ibcon#read 3, iclass 10, count 2 2006.257.12:38:45.68#ibcon#about to read 4, iclass 10, count 2 2006.257.12:38:45.68#ibcon#read 4, iclass 10, count 2 2006.257.12:38:45.68#ibcon#about to read 5, iclass 10, count 2 2006.257.12:38:45.68#ibcon#read 5, iclass 10, count 2 2006.257.12:38:45.68#ibcon#about to read 6, iclass 10, count 2 2006.257.12:38:45.68#ibcon#read 6, iclass 10, count 2 2006.257.12:38:45.68#ibcon#end of sib2, iclass 10, count 2 2006.257.12:38:45.68#ibcon#*after write, iclass 10, count 2 2006.257.12:38:45.68#ibcon#*before return 0, iclass 10, count 2 2006.257.12:38:45.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:45.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:45.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.12:38:45.69#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:45.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:45.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:45.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:45.80#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:38:45.80#ibcon#first serial, iclass 10, count 0 2006.257.12:38:45.80#ibcon#enter sib2, iclass 10, count 0 2006.257.12:38:45.80#ibcon#flushed, iclass 10, count 0 2006.257.12:38:45.80#ibcon#about to write, iclass 10, count 0 2006.257.12:38:45.80#ibcon#wrote, iclass 10, count 0 2006.257.12:38:45.80#ibcon#about to read 3, iclass 10, count 0 2006.257.12:38:45.82#ibcon#read 3, iclass 10, count 0 2006.257.12:38:45.82#ibcon#about to read 4, iclass 10, count 0 2006.257.12:38:45.82#ibcon#read 4, iclass 10, count 0 2006.257.12:38:45.82#ibcon#about to read 5, iclass 10, count 0 2006.257.12:38:45.82#ibcon#read 5, iclass 10, count 0 2006.257.12:38:45.82#ibcon#about to read 6, iclass 10, count 0 2006.257.12:38:45.82#ibcon#read 6, iclass 10, count 0 2006.257.12:38:45.82#ibcon#end of sib2, iclass 10, count 0 2006.257.12:38:45.82#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:38:45.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:38:45.82#ibcon#[25=USB\r\n] 2006.257.12:38:45.82#ibcon#*before write, iclass 10, count 0 2006.257.12:38:45.83#ibcon#enter sib2, iclass 10, count 0 2006.257.12:38:45.83#ibcon#flushed, iclass 10, count 0 2006.257.12:38:45.83#ibcon#about to write, iclass 10, count 0 2006.257.12:38:45.83#ibcon#wrote, iclass 10, count 0 2006.257.12:38:45.83#ibcon#about to read 3, iclass 10, count 0 2006.257.12:38:45.85#ibcon#read 3, iclass 10, count 0 2006.257.12:38:45.85#ibcon#about to read 4, iclass 10, count 0 2006.257.12:38:45.85#ibcon#read 4, iclass 10, count 0 2006.257.12:38:45.85#ibcon#about to read 5, iclass 10, count 0 2006.257.12:38:45.85#ibcon#read 5, iclass 10, count 0 2006.257.12:38:45.85#ibcon#about to read 6, iclass 10, count 0 2006.257.12:38:45.85#ibcon#read 6, iclass 10, count 0 2006.257.12:38:45.85#ibcon#end of sib2, iclass 10, count 0 2006.257.12:38:45.85#ibcon#*after write, iclass 10, count 0 2006.257.12:38:45.85#ibcon#*before return 0, iclass 10, count 0 2006.257.12:38:45.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:45.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:45.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:38:45.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:38:45.86$vck44/valo=3,564.99 2006.257.12:38:45.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.12:38:45.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.12:38:45.86#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:45.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:45.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:45.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:45.86#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:38:45.86#ibcon#first serial, iclass 12, count 0 2006.257.12:38:45.86#ibcon#enter sib2, iclass 12, count 0 2006.257.12:38:45.86#ibcon#flushed, iclass 12, count 0 2006.257.12:38:45.86#ibcon#about to write, iclass 12, count 0 2006.257.12:38:45.86#ibcon#wrote, iclass 12, count 0 2006.257.12:38:45.86#ibcon#about to read 3, iclass 12, count 0 2006.257.12:38:45.87#ibcon#read 3, iclass 12, count 0 2006.257.12:38:45.87#ibcon#about to read 4, iclass 12, count 0 2006.257.12:38:45.87#ibcon#read 4, iclass 12, count 0 2006.257.12:38:45.87#ibcon#about to read 5, iclass 12, count 0 2006.257.12:38:45.87#ibcon#read 5, iclass 12, count 0 2006.257.12:38:45.87#ibcon#about to read 6, iclass 12, count 0 2006.257.12:38:45.87#ibcon#read 6, iclass 12, count 0 2006.257.12:38:45.87#ibcon#end of sib2, iclass 12, count 0 2006.257.12:38:45.87#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:38:45.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:38:45.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:38:45.87#ibcon#*before write, iclass 12, count 0 2006.257.12:38:45.87#ibcon#enter sib2, iclass 12, count 0 2006.257.12:38:45.88#ibcon#flushed, iclass 12, count 0 2006.257.12:38:45.88#ibcon#about to write, iclass 12, count 0 2006.257.12:38:45.88#ibcon#wrote, iclass 12, count 0 2006.257.12:38:45.88#ibcon#about to read 3, iclass 12, count 0 2006.257.12:38:45.91#ibcon#read 3, iclass 12, count 0 2006.257.12:38:45.91#ibcon#about to read 4, iclass 12, count 0 2006.257.12:38:45.91#ibcon#read 4, iclass 12, count 0 2006.257.12:38:45.91#ibcon#about to read 5, iclass 12, count 0 2006.257.12:38:45.91#ibcon#read 5, iclass 12, count 0 2006.257.12:38:45.91#ibcon#about to read 6, iclass 12, count 0 2006.257.12:38:45.91#ibcon#read 6, iclass 12, count 0 2006.257.12:38:45.91#ibcon#end of sib2, iclass 12, count 0 2006.257.12:38:45.91#ibcon#*after write, iclass 12, count 0 2006.257.12:38:45.91#ibcon#*before return 0, iclass 12, count 0 2006.257.12:38:45.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:45.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:45.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:38:45.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:38:45.92$vck44/va=3,8 2006.257.12:38:45.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.12:38:45.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.12:38:45.92#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:45.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:45.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:45.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:45.96#ibcon#enter wrdev, iclass 14, count 2 2006.257.12:38:45.96#ibcon#first serial, iclass 14, count 2 2006.257.12:38:45.96#ibcon#enter sib2, iclass 14, count 2 2006.257.12:38:45.96#ibcon#flushed, iclass 14, count 2 2006.257.12:38:45.96#ibcon#about to write, iclass 14, count 2 2006.257.12:38:45.96#ibcon#wrote, iclass 14, count 2 2006.257.12:38:45.96#ibcon#about to read 3, iclass 14, count 2 2006.257.12:38:45.98#ibcon#read 3, iclass 14, count 2 2006.257.12:38:45.98#ibcon#about to read 4, iclass 14, count 2 2006.257.12:38:45.98#ibcon#read 4, iclass 14, count 2 2006.257.12:38:45.98#ibcon#about to read 5, iclass 14, count 2 2006.257.12:38:45.98#ibcon#read 5, iclass 14, count 2 2006.257.12:38:45.98#ibcon#about to read 6, iclass 14, count 2 2006.257.12:38:45.98#ibcon#read 6, iclass 14, count 2 2006.257.12:38:45.98#ibcon#end of sib2, iclass 14, count 2 2006.257.12:38:45.98#ibcon#*mode == 0, iclass 14, count 2 2006.257.12:38:45.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.12:38:45.98#ibcon#[25=AT03-08\r\n] 2006.257.12:38:45.98#ibcon#*before write, iclass 14, count 2 2006.257.12:38:45.99#ibcon#enter sib2, iclass 14, count 2 2006.257.12:38:45.99#ibcon#flushed, iclass 14, count 2 2006.257.12:38:45.99#ibcon#about to write, iclass 14, count 2 2006.257.12:38:45.99#ibcon#wrote, iclass 14, count 2 2006.257.12:38:45.99#ibcon#about to read 3, iclass 14, count 2 2006.257.12:38:46.01#ibcon#read 3, iclass 14, count 2 2006.257.12:38:46.01#ibcon#about to read 4, iclass 14, count 2 2006.257.12:38:46.01#ibcon#read 4, iclass 14, count 2 2006.257.12:38:46.01#ibcon#about to read 5, iclass 14, count 2 2006.257.12:38:46.01#ibcon#read 5, iclass 14, count 2 2006.257.12:38:46.01#ibcon#about to read 6, iclass 14, count 2 2006.257.12:38:46.01#ibcon#read 6, iclass 14, count 2 2006.257.12:38:46.01#ibcon#end of sib2, iclass 14, count 2 2006.257.12:38:46.01#ibcon#*after write, iclass 14, count 2 2006.257.12:38:46.01#ibcon#*before return 0, iclass 14, count 2 2006.257.12:38:46.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:46.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:46.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.12:38:46.02#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:46.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:46.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:46.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:46.14#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:38:46.14#ibcon#first serial, iclass 14, count 0 2006.257.12:38:46.14#ibcon#enter sib2, iclass 14, count 0 2006.257.12:38:46.14#ibcon#flushed, iclass 14, count 0 2006.257.12:38:46.14#ibcon#about to write, iclass 14, count 0 2006.257.12:38:46.14#ibcon#wrote, iclass 14, count 0 2006.257.12:38:46.14#ibcon#about to read 3, iclass 14, count 0 2006.257.12:38:46.15#ibcon#read 3, iclass 14, count 0 2006.257.12:38:46.15#ibcon#about to read 4, iclass 14, count 0 2006.257.12:38:46.15#ibcon#read 4, iclass 14, count 0 2006.257.12:38:46.15#ibcon#about to read 5, iclass 14, count 0 2006.257.12:38:46.15#ibcon#read 5, iclass 14, count 0 2006.257.12:38:46.15#ibcon#about to read 6, iclass 14, count 0 2006.257.12:38:46.15#ibcon#read 6, iclass 14, count 0 2006.257.12:38:46.15#ibcon#end of sib2, iclass 14, count 0 2006.257.12:38:46.15#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:38:46.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:38:46.15#ibcon#[25=USB\r\n] 2006.257.12:38:46.15#ibcon#*before write, iclass 14, count 0 2006.257.12:38:46.16#ibcon#enter sib2, iclass 14, count 0 2006.257.12:38:46.16#ibcon#flushed, iclass 14, count 0 2006.257.12:38:46.16#ibcon#about to write, iclass 14, count 0 2006.257.12:38:46.16#ibcon#wrote, iclass 14, count 0 2006.257.12:38:46.16#ibcon#about to read 3, iclass 14, count 0 2006.257.12:38:46.18#ibcon#read 3, iclass 14, count 0 2006.257.12:38:46.18#ibcon#about to read 4, iclass 14, count 0 2006.257.12:38:46.18#ibcon#read 4, iclass 14, count 0 2006.257.12:38:46.18#ibcon#about to read 5, iclass 14, count 0 2006.257.12:38:46.18#ibcon#read 5, iclass 14, count 0 2006.257.12:38:46.18#ibcon#about to read 6, iclass 14, count 0 2006.257.12:38:46.18#ibcon#read 6, iclass 14, count 0 2006.257.12:38:46.18#ibcon#end of sib2, iclass 14, count 0 2006.257.12:38:46.18#ibcon#*after write, iclass 14, count 0 2006.257.12:38:46.18#ibcon#*before return 0, iclass 14, count 0 2006.257.12:38:46.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:46.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:46.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:38:46.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:38:46.19$vck44/valo=4,624.99 2006.257.12:38:46.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.12:38:46.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.12:38:46.19#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:46.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:46.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:46.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:46.19#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:38:46.19#ibcon#first serial, iclass 16, count 0 2006.257.12:38:46.19#ibcon#enter sib2, iclass 16, count 0 2006.257.12:38:46.19#ibcon#flushed, iclass 16, count 0 2006.257.12:38:46.19#ibcon#about to write, iclass 16, count 0 2006.257.12:38:46.19#ibcon#wrote, iclass 16, count 0 2006.257.12:38:46.19#ibcon#about to read 3, iclass 16, count 0 2006.257.12:38:46.20#ibcon#read 3, iclass 16, count 0 2006.257.12:38:46.20#ibcon#about to read 4, iclass 16, count 0 2006.257.12:38:46.20#ibcon#read 4, iclass 16, count 0 2006.257.12:38:46.20#ibcon#about to read 5, iclass 16, count 0 2006.257.12:38:46.20#ibcon#read 5, iclass 16, count 0 2006.257.12:38:46.20#ibcon#about to read 6, iclass 16, count 0 2006.257.12:38:46.20#ibcon#read 6, iclass 16, count 0 2006.257.12:38:46.20#ibcon#end of sib2, iclass 16, count 0 2006.257.12:38:46.20#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:38:46.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:38:46.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:38:46.20#ibcon#*before write, iclass 16, count 0 2006.257.12:38:46.21#ibcon#enter sib2, iclass 16, count 0 2006.257.12:38:46.21#ibcon#flushed, iclass 16, count 0 2006.257.12:38:46.21#ibcon#about to write, iclass 16, count 0 2006.257.12:38:46.21#ibcon#wrote, iclass 16, count 0 2006.257.12:38:46.21#ibcon#about to read 3, iclass 16, count 0 2006.257.12:38:46.24#ibcon#read 3, iclass 16, count 0 2006.257.12:38:46.24#ibcon#about to read 4, iclass 16, count 0 2006.257.12:38:46.24#ibcon#read 4, iclass 16, count 0 2006.257.12:38:46.24#ibcon#about to read 5, iclass 16, count 0 2006.257.12:38:46.24#ibcon#read 5, iclass 16, count 0 2006.257.12:38:46.24#ibcon#about to read 6, iclass 16, count 0 2006.257.12:38:46.24#ibcon#read 6, iclass 16, count 0 2006.257.12:38:46.24#ibcon#end of sib2, iclass 16, count 0 2006.257.12:38:46.24#ibcon#*after write, iclass 16, count 0 2006.257.12:38:46.24#ibcon#*before return 0, iclass 16, count 0 2006.257.12:38:46.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:46.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:46.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:38:46.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:38:46.25$vck44/va=4,7 2006.257.12:38:46.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.12:38:46.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.12:38:46.25#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:46.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:46.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:46.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:46.29#ibcon#enter wrdev, iclass 18, count 2 2006.257.12:38:46.29#ibcon#first serial, iclass 18, count 2 2006.257.12:38:46.29#ibcon#enter sib2, iclass 18, count 2 2006.257.12:38:46.29#ibcon#flushed, iclass 18, count 2 2006.257.12:38:46.29#ibcon#about to write, iclass 18, count 2 2006.257.12:38:46.29#ibcon#wrote, iclass 18, count 2 2006.257.12:38:46.29#ibcon#about to read 3, iclass 18, count 2 2006.257.12:38:46.31#ibcon#read 3, iclass 18, count 2 2006.257.12:38:46.31#ibcon#about to read 4, iclass 18, count 2 2006.257.12:38:46.31#ibcon#read 4, iclass 18, count 2 2006.257.12:38:46.31#ibcon#about to read 5, iclass 18, count 2 2006.257.12:38:46.31#ibcon#read 5, iclass 18, count 2 2006.257.12:38:46.31#ibcon#about to read 6, iclass 18, count 2 2006.257.12:38:46.31#ibcon#read 6, iclass 18, count 2 2006.257.12:38:46.31#ibcon#end of sib2, iclass 18, count 2 2006.257.12:38:46.31#ibcon#*mode == 0, iclass 18, count 2 2006.257.12:38:46.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.12:38:46.31#ibcon#[25=AT04-07\r\n] 2006.257.12:38:46.31#ibcon#*before write, iclass 18, count 2 2006.257.12:38:46.31#ibcon#enter sib2, iclass 18, count 2 2006.257.12:38:46.32#ibcon#flushed, iclass 18, count 2 2006.257.12:38:46.32#ibcon#about to write, iclass 18, count 2 2006.257.12:38:46.32#ibcon#wrote, iclass 18, count 2 2006.257.12:38:46.32#ibcon#about to read 3, iclass 18, count 2 2006.257.12:38:46.34#ibcon#read 3, iclass 18, count 2 2006.257.12:38:46.34#ibcon#about to read 4, iclass 18, count 2 2006.257.12:38:46.34#ibcon#read 4, iclass 18, count 2 2006.257.12:38:46.34#ibcon#about to read 5, iclass 18, count 2 2006.257.12:38:46.34#ibcon#read 5, iclass 18, count 2 2006.257.12:38:46.34#ibcon#about to read 6, iclass 18, count 2 2006.257.12:38:46.34#ibcon#read 6, iclass 18, count 2 2006.257.12:38:46.34#ibcon#end of sib2, iclass 18, count 2 2006.257.12:38:46.34#ibcon#*after write, iclass 18, count 2 2006.257.12:38:46.37#ibcon#*before return 0, iclass 18, count 2 2006.257.12:38:46.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:46.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:46.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.12:38:46.37#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:46.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:46.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:46.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:46.48#ibcon#enter wrdev, iclass 18, count 0 2006.257.12:38:46.48#ibcon#first serial, iclass 18, count 0 2006.257.12:38:46.48#ibcon#enter sib2, iclass 18, count 0 2006.257.12:38:46.48#ibcon#flushed, iclass 18, count 0 2006.257.12:38:46.48#ibcon#about to write, iclass 18, count 0 2006.257.12:38:46.48#ibcon#wrote, iclass 18, count 0 2006.257.12:38:46.48#ibcon#about to read 3, iclass 18, count 0 2006.257.12:38:46.50#ibcon#read 3, iclass 18, count 0 2006.257.12:38:46.50#ibcon#about to read 4, iclass 18, count 0 2006.257.12:38:46.50#ibcon#read 4, iclass 18, count 0 2006.257.12:38:46.50#ibcon#about to read 5, iclass 18, count 0 2006.257.12:38:46.50#ibcon#read 5, iclass 18, count 0 2006.257.12:38:46.50#ibcon#about to read 6, iclass 18, count 0 2006.257.12:38:46.50#ibcon#read 6, iclass 18, count 0 2006.257.12:38:46.50#ibcon#end of sib2, iclass 18, count 0 2006.257.12:38:46.50#ibcon#*mode == 0, iclass 18, count 0 2006.257.12:38:46.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.12:38:46.51#ibcon#[25=USB\r\n] 2006.257.12:38:46.51#ibcon#*before write, iclass 18, count 0 2006.257.12:38:46.51#ibcon#enter sib2, iclass 18, count 0 2006.257.12:38:46.51#ibcon#flushed, iclass 18, count 0 2006.257.12:38:46.51#ibcon#about to write, iclass 18, count 0 2006.257.12:38:46.51#ibcon#wrote, iclass 18, count 0 2006.257.12:38:46.51#ibcon#about to read 3, iclass 18, count 0 2006.257.12:38:46.53#ibcon#read 3, iclass 18, count 0 2006.257.12:38:46.53#ibcon#about to read 4, iclass 18, count 0 2006.257.12:38:46.53#ibcon#read 4, iclass 18, count 0 2006.257.12:38:46.53#ibcon#about to read 5, iclass 18, count 0 2006.257.12:38:46.53#ibcon#read 5, iclass 18, count 0 2006.257.12:38:46.53#ibcon#about to read 6, iclass 18, count 0 2006.257.12:38:46.53#ibcon#read 6, iclass 18, count 0 2006.257.12:38:46.53#ibcon#end of sib2, iclass 18, count 0 2006.257.12:38:46.53#ibcon#*after write, iclass 18, count 0 2006.257.12:38:46.54#ibcon#*before return 0, iclass 18, count 0 2006.257.12:38:46.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:46.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:46.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.12:38:46.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.12:38:46.54$vck44/valo=5,734.99 2006.257.12:38:46.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.12:38:46.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.12:38:46.54#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:46.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:46.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:46.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:46.54#ibcon#enter wrdev, iclass 20, count 0 2006.257.12:38:46.54#ibcon#first serial, iclass 20, count 0 2006.257.12:38:46.54#ibcon#enter sib2, iclass 20, count 0 2006.257.12:38:46.54#ibcon#flushed, iclass 20, count 0 2006.257.12:38:46.54#ibcon#about to write, iclass 20, count 0 2006.257.12:38:46.54#ibcon#wrote, iclass 20, count 0 2006.257.12:38:46.54#ibcon#about to read 3, iclass 20, count 0 2006.257.12:38:46.55#ibcon#read 3, iclass 20, count 0 2006.257.12:38:46.55#ibcon#about to read 4, iclass 20, count 0 2006.257.12:38:46.55#ibcon#read 4, iclass 20, count 0 2006.257.12:38:46.55#ibcon#about to read 5, iclass 20, count 0 2006.257.12:38:46.55#ibcon#read 5, iclass 20, count 0 2006.257.12:38:46.55#ibcon#about to read 6, iclass 20, count 0 2006.257.12:38:46.55#ibcon#read 6, iclass 20, count 0 2006.257.12:38:46.55#ibcon#end of sib2, iclass 20, count 0 2006.257.12:38:46.55#ibcon#*mode == 0, iclass 20, count 0 2006.257.12:38:46.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.12:38:46.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:38:46.56#ibcon#*before write, iclass 20, count 0 2006.257.12:38:46.56#ibcon#enter sib2, iclass 20, count 0 2006.257.12:38:46.56#ibcon#flushed, iclass 20, count 0 2006.257.12:38:46.56#ibcon#about to write, iclass 20, count 0 2006.257.12:38:46.56#ibcon#wrote, iclass 20, count 0 2006.257.12:38:46.56#ibcon#about to read 3, iclass 20, count 0 2006.257.12:38:46.59#ibcon#read 3, iclass 20, count 0 2006.257.12:38:46.59#ibcon#about to read 4, iclass 20, count 0 2006.257.12:38:46.59#ibcon#read 4, iclass 20, count 0 2006.257.12:38:46.59#ibcon#about to read 5, iclass 20, count 0 2006.257.12:38:46.59#ibcon#read 5, iclass 20, count 0 2006.257.12:38:46.59#ibcon#about to read 6, iclass 20, count 0 2006.257.12:38:46.59#ibcon#read 6, iclass 20, count 0 2006.257.12:38:46.59#ibcon#end of sib2, iclass 20, count 0 2006.257.12:38:46.59#ibcon#*after write, iclass 20, count 0 2006.257.12:38:46.59#ibcon#*before return 0, iclass 20, count 0 2006.257.12:38:46.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:46.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:46.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.12:38:46.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.12:38:46.60$vck44/va=5,4 2006.257.12:38:46.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.12:38:46.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.12:38:46.60#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:46.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:46.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:46.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:46.65#ibcon#enter wrdev, iclass 22, count 2 2006.257.12:38:46.65#ibcon#first serial, iclass 22, count 2 2006.257.12:38:46.65#ibcon#enter sib2, iclass 22, count 2 2006.257.12:38:46.65#ibcon#flushed, iclass 22, count 2 2006.257.12:38:46.65#ibcon#about to write, iclass 22, count 2 2006.257.12:38:46.65#ibcon#wrote, iclass 22, count 2 2006.257.12:38:46.65#ibcon#about to read 3, iclass 22, count 2 2006.257.12:38:46.67#ibcon#read 3, iclass 22, count 2 2006.257.12:38:46.67#ibcon#about to read 4, iclass 22, count 2 2006.257.12:38:46.67#ibcon#read 4, iclass 22, count 2 2006.257.12:38:46.67#ibcon#about to read 5, iclass 22, count 2 2006.257.12:38:46.67#ibcon#read 5, iclass 22, count 2 2006.257.12:38:46.67#ibcon#about to read 6, iclass 22, count 2 2006.257.12:38:46.67#ibcon#read 6, iclass 22, count 2 2006.257.12:38:46.67#ibcon#end of sib2, iclass 22, count 2 2006.257.12:38:46.67#ibcon#*mode == 0, iclass 22, count 2 2006.257.12:38:46.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.12:38:46.68#ibcon#[25=AT05-04\r\n] 2006.257.12:38:46.68#ibcon#*before write, iclass 22, count 2 2006.257.12:38:46.68#ibcon#enter sib2, iclass 22, count 2 2006.257.12:38:46.68#ibcon#flushed, iclass 22, count 2 2006.257.12:38:46.68#ibcon#about to write, iclass 22, count 2 2006.257.12:38:46.68#ibcon#wrote, iclass 22, count 2 2006.257.12:38:46.68#ibcon#about to read 3, iclass 22, count 2 2006.257.12:38:46.70#ibcon#read 3, iclass 22, count 2 2006.257.12:38:46.70#ibcon#about to read 4, iclass 22, count 2 2006.257.12:38:46.70#ibcon#read 4, iclass 22, count 2 2006.257.12:38:46.70#ibcon#about to read 5, iclass 22, count 2 2006.257.12:38:46.70#ibcon#read 5, iclass 22, count 2 2006.257.12:38:46.70#ibcon#about to read 6, iclass 22, count 2 2006.257.12:38:46.70#ibcon#read 6, iclass 22, count 2 2006.257.12:38:46.70#ibcon#end of sib2, iclass 22, count 2 2006.257.12:38:46.70#ibcon#*after write, iclass 22, count 2 2006.257.12:38:46.70#ibcon#*before return 0, iclass 22, count 2 2006.257.12:38:46.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:46.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:46.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.12:38:46.71#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:46.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:46.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:46.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:46.82#ibcon#enter wrdev, iclass 22, count 0 2006.257.12:38:46.82#ibcon#first serial, iclass 22, count 0 2006.257.12:38:46.82#ibcon#enter sib2, iclass 22, count 0 2006.257.12:38:46.82#ibcon#flushed, iclass 22, count 0 2006.257.12:38:46.82#ibcon#about to write, iclass 22, count 0 2006.257.12:38:46.82#ibcon#wrote, iclass 22, count 0 2006.257.12:38:46.82#ibcon#about to read 3, iclass 22, count 0 2006.257.12:38:46.84#ibcon#read 3, iclass 22, count 0 2006.257.12:38:46.84#ibcon#about to read 4, iclass 22, count 0 2006.257.12:38:46.84#ibcon#read 4, iclass 22, count 0 2006.257.12:38:46.84#ibcon#about to read 5, iclass 22, count 0 2006.257.12:38:46.84#ibcon#read 5, iclass 22, count 0 2006.257.12:38:46.84#ibcon#about to read 6, iclass 22, count 0 2006.257.12:38:46.84#ibcon#read 6, iclass 22, count 0 2006.257.12:38:46.84#ibcon#end of sib2, iclass 22, count 0 2006.257.12:38:46.84#ibcon#*mode == 0, iclass 22, count 0 2006.257.12:38:46.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.12:38:46.84#ibcon#[25=USB\r\n] 2006.257.12:38:46.84#ibcon#*before write, iclass 22, count 0 2006.257.12:38:46.84#ibcon#enter sib2, iclass 22, count 0 2006.257.12:38:46.84#ibcon#flushed, iclass 22, count 0 2006.257.12:38:46.85#ibcon#about to write, iclass 22, count 0 2006.257.12:38:46.85#ibcon#wrote, iclass 22, count 0 2006.257.12:38:46.85#ibcon#about to read 3, iclass 22, count 0 2006.257.12:38:46.87#ibcon#read 3, iclass 22, count 0 2006.257.12:38:46.87#ibcon#about to read 4, iclass 22, count 0 2006.257.12:38:46.87#ibcon#read 4, iclass 22, count 0 2006.257.12:38:46.87#ibcon#about to read 5, iclass 22, count 0 2006.257.12:38:46.87#ibcon#read 5, iclass 22, count 0 2006.257.12:38:46.87#ibcon#about to read 6, iclass 22, count 0 2006.257.12:38:46.87#ibcon#read 6, iclass 22, count 0 2006.257.12:38:46.87#ibcon#end of sib2, iclass 22, count 0 2006.257.12:38:46.87#ibcon#*after write, iclass 22, count 0 2006.257.12:38:46.87#ibcon#*before return 0, iclass 22, count 0 2006.257.12:38:46.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:46.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:46.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.12:38:46.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.12:38:46.88$vck44/valo=6,814.99 2006.257.12:38:46.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.12:38:46.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.12:38:46.88#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:46.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:46.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:46.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:46.88#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:38:46.88#ibcon#first serial, iclass 24, count 0 2006.257.12:38:46.88#ibcon#enter sib2, iclass 24, count 0 2006.257.12:38:46.88#ibcon#flushed, iclass 24, count 0 2006.257.12:38:46.88#ibcon#about to write, iclass 24, count 0 2006.257.12:38:46.88#ibcon#wrote, iclass 24, count 0 2006.257.12:38:46.88#ibcon#about to read 3, iclass 24, count 0 2006.257.12:38:46.89#ibcon#read 3, iclass 24, count 0 2006.257.12:38:46.89#ibcon#about to read 4, iclass 24, count 0 2006.257.12:38:46.89#ibcon#read 4, iclass 24, count 0 2006.257.12:38:46.89#ibcon#about to read 5, iclass 24, count 0 2006.257.12:38:46.89#ibcon#read 5, iclass 24, count 0 2006.257.12:38:46.89#ibcon#about to read 6, iclass 24, count 0 2006.257.12:38:46.89#ibcon#read 6, iclass 24, count 0 2006.257.12:38:46.89#ibcon#end of sib2, iclass 24, count 0 2006.257.12:38:46.89#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:38:46.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:38:46.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:38:46.89#ibcon#*before write, iclass 24, count 0 2006.257.12:38:46.89#ibcon#enter sib2, iclass 24, count 0 2006.257.12:38:46.90#ibcon#flushed, iclass 24, count 0 2006.257.12:38:46.90#ibcon#about to write, iclass 24, count 0 2006.257.12:38:46.90#ibcon#wrote, iclass 24, count 0 2006.257.12:38:46.90#ibcon#about to read 3, iclass 24, count 0 2006.257.12:38:46.93#ibcon#read 3, iclass 24, count 0 2006.257.12:38:46.93#ibcon#about to read 4, iclass 24, count 0 2006.257.12:38:46.93#ibcon#read 4, iclass 24, count 0 2006.257.12:38:46.93#ibcon#about to read 5, iclass 24, count 0 2006.257.12:38:46.93#ibcon#read 5, iclass 24, count 0 2006.257.12:38:46.93#ibcon#about to read 6, iclass 24, count 0 2006.257.12:38:46.93#ibcon#read 6, iclass 24, count 0 2006.257.12:38:46.93#ibcon#end of sib2, iclass 24, count 0 2006.257.12:38:46.93#ibcon#*after write, iclass 24, count 0 2006.257.12:38:46.93#ibcon#*before return 0, iclass 24, count 0 2006.257.12:38:46.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:46.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:46.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:38:46.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:38:46.94$vck44/va=6,4 2006.257.12:38:46.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.12:38:46.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.12:38:46.94#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:46.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:46.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:46.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:46.98#ibcon#enter wrdev, iclass 26, count 2 2006.257.12:38:46.98#ibcon#first serial, iclass 26, count 2 2006.257.12:38:46.98#ibcon#enter sib2, iclass 26, count 2 2006.257.12:38:46.98#ibcon#flushed, iclass 26, count 2 2006.257.12:38:46.98#ibcon#about to write, iclass 26, count 2 2006.257.12:38:46.98#ibcon#wrote, iclass 26, count 2 2006.257.12:38:46.98#ibcon#about to read 3, iclass 26, count 2 2006.257.12:38:47.00#ibcon#read 3, iclass 26, count 2 2006.257.12:38:47.00#ibcon#about to read 4, iclass 26, count 2 2006.257.12:38:47.00#ibcon#read 4, iclass 26, count 2 2006.257.12:38:47.00#ibcon#about to read 5, iclass 26, count 2 2006.257.12:38:47.00#ibcon#read 5, iclass 26, count 2 2006.257.12:38:47.00#ibcon#about to read 6, iclass 26, count 2 2006.257.12:38:47.00#ibcon#read 6, iclass 26, count 2 2006.257.12:38:47.00#ibcon#end of sib2, iclass 26, count 2 2006.257.12:38:47.00#ibcon#*mode == 0, iclass 26, count 2 2006.257.12:38:47.00#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.12:38:47.00#ibcon#[25=AT06-04\r\n] 2006.257.12:38:47.00#ibcon#*before write, iclass 26, count 2 2006.257.12:38:47.00#ibcon#enter sib2, iclass 26, count 2 2006.257.12:38:47.01#ibcon#flushed, iclass 26, count 2 2006.257.12:38:47.01#ibcon#about to write, iclass 26, count 2 2006.257.12:38:47.01#ibcon#wrote, iclass 26, count 2 2006.257.12:38:47.01#ibcon#about to read 3, iclass 26, count 2 2006.257.12:38:47.03#ibcon#read 3, iclass 26, count 2 2006.257.12:38:47.03#ibcon#about to read 4, iclass 26, count 2 2006.257.12:38:47.03#ibcon#read 4, iclass 26, count 2 2006.257.12:38:47.03#ibcon#about to read 5, iclass 26, count 2 2006.257.12:38:47.03#ibcon#read 5, iclass 26, count 2 2006.257.12:38:47.03#ibcon#about to read 6, iclass 26, count 2 2006.257.12:38:47.03#ibcon#read 6, iclass 26, count 2 2006.257.12:38:47.03#ibcon#end of sib2, iclass 26, count 2 2006.257.12:38:47.03#ibcon#*after write, iclass 26, count 2 2006.257.12:38:47.03#ibcon#*before return 0, iclass 26, count 2 2006.257.12:38:47.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:47.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:47.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.12:38:47.04#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:47.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:47.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:47.15#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:47.15#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:38:47.15#ibcon#first serial, iclass 26, count 0 2006.257.12:38:47.15#ibcon#enter sib2, iclass 26, count 0 2006.257.12:38:47.15#ibcon#flushed, iclass 26, count 0 2006.257.12:38:47.15#ibcon#about to write, iclass 26, count 0 2006.257.12:38:47.15#ibcon#wrote, iclass 26, count 0 2006.257.12:38:47.15#ibcon#about to read 3, iclass 26, count 0 2006.257.12:38:47.17#ibcon#read 3, iclass 26, count 0 2006.257.12:38:47.17#ibcon#about to read 4, iclass 26, count 0 2006.257.12:38:47.17#ibcon#read 4, iclass 26, count 0 2006.257.12:38:47.17#ibcon#about to read 5, iclass 26, count 0 2006.257.12:38:47.17#ibcon#read 5, iclass 26, count 0 2006.257.12:38:47.17#ibcon#about to read 6, iclass 26, count 0 2006.257.12:38:47.17#ibcon#read 6, iclass 26, count 0 2006.257.12:38:47.17#ibcon#end of sib2, iclass 26, count 0 2006.257.12:38:47.17#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:38:47.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:38:47.18#ibcon#[25=USB\r\n] 2006.257.12:38:47.18#ibcon#*before write, iclass 26, count 0 2006.257.12:38:47.18#ibcon#enter sib2, iclass 26, count 0 2006.257.12:38:47.18#ibcon#flushed, iclass 26, count 0 2006.257.12:38:47.18#ibcon#about to write, iclass 26, count 0 2006.257.12:38:47.18#ibcon#wrote, iclass 26, count 0 2006.257.12:38:47.18#ibcon#about to read 3, iclass 26, count 0 2006.257.12:38:47.20#ibcon#read 3, iclass 26, count 0 2006.257.12:38:47.20#ibcon#about to read 4, iclass 26, count 0 2006.257.12:38:47.20#ibcon#read 4, iclass 26, count 0 2006.257.12:38:47.20#ibcon#about to read 5, iclass 26, count 0 2006.257.12:38:47.20#ibcon#read 5, iclass 26, count 0 2006.257.12:38:47.20#ibcon#about to read 6, iclass 26, count 0 2006.257.12:38:47.20#ibcon#read 6, iclass 26, count 0 2006.257.12:38:47.20#ibcon#end of sib2, iclass 26, count 0 2006.257.12:38:47.20#ibcon#*after write, iclass 26, count 0 2006.257.12:38:47.20#ibcon#*before return 0, iclass 26, count 0 2006.257.12:38:47.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:47.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:47.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:38:47.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:38:47.21$vck44/valo=7,864.99 2006.257.12:38:47.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.12:38:47.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.12:38:47.21#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:47.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:47.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:47.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:47.21#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:38:47.21#ibcon#first serial, iclass 28, count 0 2006.257.12:38:47.21#ibcon#enter sib2, iclass 28, count 0 2006.257.12:38:47.21#ibcon#flushed, iclass 28, count 0 2006.257.12:38:47.21#ibcon#about to write, iclass 28, count 0 2006.257.12:38:47.21#ibcon#wrote, iclass 28, count 0 2006.257.12:38:47.21#ibcon#about to read 3, iclass 28, count 0 2006.257.12:38:47.22#ibcon#read 3, iclass 28, count 0 2006.257.12:38:47.22#ibcon#about to read 4, iclass 28, count 0 2006.257.12:38:47.22#ibcon#read 4, iclass 28, count 0 2006.257.12:38:47.22#ibcon#about to read 5, iclass 28, count 0 2006.257.12:38:47.22#ibcon#read 5, iclass 28, count 0 2006.257.12:38:47.22#ibcon#about to read 6, iclass 28, count 0 2006.257.12:38:47.22#ibcon#read 6, iclass 28, count 0 2006.257.12:38:47.22#ibcon#end of sib2, iclass 28, count 0 2006.257.12:38:47.22#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:38:47.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:38:47.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:38:47.22#ibcon#*before write, iclass 28, count 0 2006.257.12:38:47.22#ibcon#enter sib2, iclass 28, count 0 2006.257.12:38:47.23#ibcon#flushed, iclass 28, count 0 2006.257.12:38:47.23#ibcon#about to write, iclass 28, count 0 2006.257.12:38:47.23#ibcon#wrote, iclass 28, count 0 2006.257.12:38:47.23#ibcon#about to read 3, iclass 28, count 0 2006.257.12:38:47.26#ibcon#read 3, iclass 28, count 0 2006.257.12:38:47.26#ibcon#about to read 4, iclass 28, count 0 2006.257.12:38:47.26#ibcon#read 4, iclass 28, count 0 2006.257.12:38:47.26#ibcon#about to read 5, iclass 28, count 0 2006.257.12:38:47.26#ibcon#read 5, iclass 28, count 0 2006.257.12:38:47.26#ibcon#about to read 6, iclass 28, count 0 2006.257.12:38:47.26#ibcon#read 6, iclass 28, count 0 2006.257.12:38:47.26#ibcon#end of sib2, iclass 28, count 0 2006.257.12:38:47.26#ibcon#*after write, iclass 28, count 0 2006.257.12:38:47.26#ibcon#*before return 0, iclass 28, count 0 2006.257.12:38:47.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:47.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:47.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:38:47.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:38:47.27$vck44/va=7,4 2006.257.12:38:47.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.12:38:47.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.12:38:47.27#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:47.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:47.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:47.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:47.32#ibcon#enter wrdev, iclass 30, count 2 2006.257.12:38:47.32#ibcon#first serial, iclass 30, count 2 2006.257.12:38:47.32#ibcon#enter sib2, iclass 30, count 2 2006.257.12:38:47.32#ibcon#flushed, iclass 30, count 2 2006.257.12:38:47.32#ibcon#about to write, iclass 30, count 2 2006.257.12:38:47.32#ibcon#wrote, iclass 30, count 2 2006.257.12:38:47.32#ibcon#about to read 3, iclass 30, count 2 2006.257.12:38:47.34#ibcon#read 3, iclass 30, count 2 2006.257.12:38:47.34#ibcon#about to read 4, iclass 30, count 2 2006.257.12:38:47.34#ibcon#read 4, iclass 30, count 2 2006.257.12:38:47.34#ibcon#about to read 5, iclass 30, count 2 2006.257.12:38:47.34#ibcon#read 5, iclass 30, count 2 2006.257.12:38:47.34#ibcon#about to read 6, iclass 30, count 2 2006.257.12:38:47.34#ibcon#read 6, iclass 30, count 2 2006.257.12:38:47.34#ibcon#end of sib2, iclass 30, count 2 2006.257.12:38:47.34#ibcon#*mode == 0, iclass 30, count 2 2006.257.12:38:47.34#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.12:38:47.34#ibcon#[25=AT07-04\r\n] 2006.257.12:38:47.34#ibcon#*before write, iclass 30, count 2 2006.257.12:38:47.34#ibcon#enter sib2, iclass 30, count 2 2006.257.12:38:47.35#ibcon#flushed, iclass 30, count 2 2006.257.12:38:47.35#ibcon#about to write, iclass 30, count 2 2006.257.12:38:47.35#ibcon#wrote, iclass 30, count 2 2006.257.12:38:47.35#ibcon#about to read 3, iclass 30, count 2 2006.257.12:38:47.37#ibcon#read 3, iclass 30, count 2 2006.257.12:38:47.37#ibcon#about to read 4, iclass 30, count 2 2006.257.12:38:47.37#ibcon#read 4, iclass 30, count 2 2006.257.12:38:47.37#ibcon#about to read 5, iclass 30, count 2 2006.257.12:38:47.37#ibcon#read 5, iclass 30, count 2 2006.257.12:38:47.37#ibcon#about to read 6, iclass 30, count 2 2006.257.12:38:47.37#ibcon#read 6, iclass 30, count 2 2006.257.12:38:47.37#ibcon#end of sib2, iclass 30, count 2 2006.257.12:38:47.37#ibcon#*after write, iclass 30, count 2 2006.257.12:38:47.37#ibcon#*before return 0, iclass 30, count 2 2006.257.12:38:47.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:47.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:47.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.12:38:47.42#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:47.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:47.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:47.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:47.54#ibcon#enter wrdev, iclass 30, count 0 2006.257.12:38:47.54#ibcon#first serial, iclass 30, count 0 2006.257.12:38:47.54#ibcon#enter sib2, iclass 30, count 0 2006.257.12:38:47.54#ibcon#flushed, iclass 30, count 0 2006.257.12:38:47.54#ibcon#about to write, iclass 30, count 0 2006.257.12:38:47.54#ibcon#wrote, iclass 30, count 0 2006.257.12:38:47.54#ibcon#about to read 3, iclass 30, count 0 2006.257.12:38:47.55#ibcon#read 3, iclass 30, count 0 2006.257.12:38:47.55#ibcon#about to read 4, iclass 30, count 0 2006.257.12:38:47.55#ibcon#read 4, iclass 30, count 0 2006.257.12:38:47.55#ibcon#about to read 5, iclass 30, count 0 2006.257.12:38:47.55#ibcon#read 5, iclass 30, count 0 2006.257.12:38:47.55#ibcon#about to read 6, iclass 30, count 0 2006.257.12:38:47.55#ibcon#read 6, iclass 30, count 0 2006.257.12:38:47.55#ibcon#end of sib2, iclass 30, count 0 2006.257.12:38:47.55#ibcon#*mode == 0, iclass 30, count 0 2006.257.12:38:47.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.12:38:47.55#ibcon#[25=USB\r\n] 2006.257.12:38:47.56#ibcon#*before write, iclass 30, count 0 2006.257.12:38:47.56#ibcon#enter sib2, iclass 30, count 0 2006.257.12:38:47.56#ibcon#flushed, iclass 30, count 0 2006.257.12:38:47.56#ibcon#about to write, iclass 30, count 0 2006.257.12:38:47.56#ibcon#wrote, iclass 30, count 0 2006.257.12:38:47.56#ibcon#about to read 3, iclass 30, count 0 2006.257.12:38:47.58#ibcon#read 3, iclass 30, count 0 2006.257.12:38:47.58#ibcon#about to read 4, iclass 30, count 0 2006.257.12:38:47.58#ibcon#read 4, iclass 30, count 0 2006.257.12:38:47.58#ibcon#about to read 5, iclass 30, count 0 2006.257.12:38:47.58#ibcon#read 5, iclass 30, count 0 2006.257.12:38:47.58#ibcon#about to read 6, iclass 30, count 0 2006.257.12:38:47.58#ibcon#read 6, iclass 30, count 0 2006.257.12:38:47.58#ibcon#end of sib2, iclass 30, count 0 2006.257.12:38:47.58#ibcon#*after write, iclass 30, count 0 2006.257.12:38:47.58#ibcon#*before return 0, iclass 30, count 0 2006.257.12:38:47.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:47.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:47.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.12:38:47.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.12:38:47.59$vck44/valo=8,884.99 2006.257.12:38:47.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.12:38:47.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.12:38:47.59#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:47.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:47.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:47.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:47.59#ibcon#enter wrdev, iclass 32, count 0 2006.257.12:38:47.59#ibcon#first serial, iclass 32, count 0 2006.257.12:38:47.59#ibcon#enter sib2, iclass 32, count 0 2006.257.12:38:47.59#ibcon#flushed, iclass 32, count 0 2006.257.12:38:47.59#ibcon#about to write, iclass 32, count 0 2006.257.12:38:47.59#ibcon#wrote, iclass 32, count 0 2006.257.12:38:47.59#ibcon#about to read 3, iclass 32, count 0 2006.257.12:38:47.60#ibcon#read 3, iclass 32, count 0 2006.257.12:38:47.60#ibcon#about to read 4, iclass 32, count 0 2006.257.12:38:47.60#ibcon#read 4, iclass 32, count 0 2006.257.12:38:47.60#ibcon#about to read 5, iclass 32, count 0 2006.257.12:38:47.60#ibcon#read 5, iclass 32, count 0 2006.257.12:38:47.60#ibcon#about to read 6, iclass 32, count 0 2006.257.12:38:47.60#ibcon#read 6, iclass 32, count 0 2006.257.12:38:47.60#ibcon#end of sib2, iclass 32, count 0 2006.257.12:38:47.60#ibcon#*mode == 0, iclass 32, count 0 2006.257.12:38:47.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.12:38:47.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:38:47.61#ibcon#*before write, iclass 32, count 0 2006.257.12:38:47.61#ibcon#enter sib2, iclass 32, count 0 2006.257.12:38:47.61#ibcon#flushed, iclass 32, count 0 2006.257.12:38:47.61#ibcon#about to write, iclass 32, count 0 2006.257.12:38:47.61#ibcon#wrote, iclass 32, count 0 2006.257.12:38:47.61#ibcon#about to read 3, iclass 32, count 0 2006.257.12:38:47.64#ibcon#read 3, iclass 32, count 0 2006.257.12:38:47.64#ibcon#about to read 4, iclass 32, count 0 2006.257.12:38:47.64#ibcon#read 4, iclass 32, count 0 2006.257.12:38:47.64#ibcon#about to read 5, iclass 32, count 0 2006.257.12:38:47.64#ibcon#read 5, iclass 32, count 0 2006.257.12:38:47.64#ibcon#about to read 6, iclass 32, count 0 2006.257.12:38:47.64#ibcon#read 6, iclass 32, count 0 2006.257.12:38:47.64#ibcon#end of sib2, iclass 32, count 0 2006.257.12:38:47.64#ibcon#*after write, iclass 32, count 0 2006.257.12:38:47.64#ibcon#*before return 0, iclass 32, count 0 2006.257.12:38:47.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:47.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:47.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.12:38:47.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.12:38:47.65$vck44/va=8,4 2006.257.12:38:47.65#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.12:38:47.65#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.12:38:47.65#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:47.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:38:47.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:38:47.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:38:47.70#ibcon#enter wrdev, iclass 34, count 2 2006.257.12:38:47.70#ibcon#first serial, iclass 34, count 2 2006.257.12:38:47.70#ibcon#enter sib2, iclass 34, count 2 2006.257.12:38:47.70#ibcon#flushed, iclass 34, count 2 2006.257.12:38:47.70#ibcon#about to write, iclass 34, count 2 2006.257.12:38:47.70#ibcon#wrote, iclass 34, count 2 2006.257.12:38:47.70#ibcon#about to read 3, iclass 34, count 2 2006.257.12:38:47.72#ibcon#read 3, iclass 34, count 2 2006.257.12:38:47.72#ibcon#about to read 4, iclass 34, count 2 2006.257.12:38:47.72#ibcon#read 4, iclass 34, count 2 2006.257.12:38:47.72#ibcon#about to read 5, iclass 34, count 2 2006.257.12:38:47.72#ibcon#read 5, iclass 34, count 2 2006.257.12:38:47.72#ibcon#about to read 6, iclass 34, count 2 2006.257.12:38:47.72#ibcon#read 6, iclass 34, count 2 2006.257.12:38:47.72#ibcon#end of sib2, iclass 34, count 2 2006.257.12:38:47.72#ibcon#*mode == 0, iclass 34, count 2 2006.257.12:38:47.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.12:38:47.73#ibcon#[25=AT08-04\r\n] 2006.257.12:38:47.73#ibcon#*before write, iclass 34, count 2 2006.257.12:38:47.73#ibcon#enter sib2, iclass 34, count 2 2006.257.12:38:47.73#ibcon#flushed, iclass 34, count 2 2006.257.12:38:47.73#ibcon#about to write, iclass 34, count 2 2006.257.12:38:47.73#ibcon#wrote, iclass 34, count 2 2006.257.12:38:47.73#ibcon#about to read 3, iclass 34, count 2 2006.257.12:38:47.75#ibcon#read 3, iclass 34, count 2 2006.257.12:38:47.75#ibcon#about to read 4, iclass 34, count 2 2006.257.12:38:47.75#ibcon#read 4, iclass 34, count 2 2006.257.12:38:47.75#ibcon#about to read 5, iclass 34, count 2 2006.257.12:38:47.75#ibcon#read 5, iclass 34, count 2 2006.257.12:38:47.75#ibcon#about to read 6, iclass 34, count 2 2006.257.12:38:47.75#ibcon#read 6, iclass 34, count 2 2006.257.12:38:47.75#ibcon#end of sib2, iclass 34, count 2 2006.257.12:38:47.75#ibcon#*after write, iclass 34, count 2 2006.257.12:38:47.75#ibcon#*before return 0, iclass 34, count 2 2006.257.12:38:47.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:38:47.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.12:38:47.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.12:38:47.76#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:47.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:38:47.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:38:47.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:38:47.87#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:38:47.87#ibcon#first serial, iclass 34, count 0 2006.257.12:38:47.87#ibcon#enter sib2, iclass 34, count 0 2006.257.12:38:47.87#ibcon#flushed, iclass 34, count 0 2006.257.12:38:47.87#ibcon#about to write, iclass 34, count 0 2006.257.12:38:47.87#ibcon#wrote, iclass 34, count 0 2006.257.12:38:47.87#ibcon#about to read 3, iclass 34, count 0 2006.257.12:38:47.89#ibcon#read 3, iclass 34, count 0 2006.257.12:38:47.89#ibcon#about to read 4, iclass 34, count 0 2006.257.12:38:47.89#ibcon#read 4, iclass 34, count 0 2006.257.12:38:47.89#ibcon#about to read 5, iclass 34, count 0 2006.257.12:38:47.89#ibcon#read 5, iclass 34, count 0 2006.257.12:38:47.89#ibcon#about to read 6, iclass 34, count 0 2006.257.12:38:47.89#ibcon#read 6, iclass 34, count 0 2006.257.12:38:47.89#ibcon#end of sib2, iclass 34, count 0 2006.257.12:38:47.89#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:38:47.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:38:47.89#ibcon#[25=USB\r\n] 2006.257.12:38:47.89#ibcon#*before write, iclass 34, count 0 2006.257.12:38:47.89#ibcon#enter sib2, iclass 34, count 0 2006.257.12:38:47.90#ibcon#flushed, iclass 34, count 0 2006.257.12:38:47.90#ibcon#about to write, iclass 34, count 0 2006.257.12:38:47.90#ibcon#wrote, iclass 34, count 0 2006.257.12:38:47.90#ibcon#about to read 3, iclass 34, count 0 2006.257.12:38:47.92#ibcon#read 3, iclass 34, count 0 2006.257.12:38:47.92#ibcon#about to read 4, iclass 34, count 0 2006.257.12:38:47.92#ibcon#read 4, iclass 34, count 0 2006.257.12:38:47.92#ibcon#about to read 5, iclass 34, count 0 2006.257.12:38:47.92#ibcon#read 5, iclass 34, count 0 2006.257.12:38:47.92#ibcon#about to read 6, iclass 34, count 0 2006.257.12:38:47.92#ibcon#read 6, iclass 34, count 0 2006.257.12:38:47.92#ibcon#end of sib2, iclass 34, count 0 2006.257.12:38:47.92#ibcon#*after write, iclass 34, count 0 2006.257.12:38:47.92#ibcon#*before return 0, iclass 34, count 0 2006.257.12:38:47.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:38:47.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.12:38:47.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:38:47.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:38:47.93$vck44/vblo=1,629.99 2006.257.12:38:47.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.12:38:47.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.12:38:47.93#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:47.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:38:47.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:38:47.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:38:47.93#ibcon#enter wrdev, iclass 36, count 0 2006.257.12:38:47.93#ibcon#first serial, iclass 36, count 0 2006.257.12:38:47.93#ibcon#enter sib2, iclass 36, count 0 2006.257.12:38:47.93#ibcon#flushed, iclass 36, count 0 2006.257.12:38:47.93#ibcon#about to write, iclass 36, count 0 2006.257.12:38:47.93#ibcon#wrote, iclass 36, count 0 2006.257.12:38:47.93#ibcon#about to read 3, iclass 36, count 0 2006.257.12:38:47.94#ibcon#read 3, iclass 36, count 0 2006.257.12:38:47.94#ibcon#about to read 4, iclass 36, count 0 2006.257.12:38:47.94#ibcon#read 4, iclass 36, count 0 2006.257.12:38:47.94#ibcon#about to read 5, iclass 36, count 0 2006.257.12:38:47.94#ibcon#read 5, iclass 36, count 0 2006.257.12:38:47.94#ibcon#about to read 6, iclass 36, count 0 2006.257.12:38:47.94#ibcon#read 6, iclass 36, count 0 2006.257.12:38:47.94#ibcon#end of sib2, iclass 36, count 0 2006.257.12:38:47.94#ibcon#*mode == 0, iclass 36, count 0 2006.257.12:38:47.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.12:38:47.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:38:47.95#ibcon#*before write, iclass 36, count 0 2006.257.12:38:47.95#ibcon#enter sib2, iclass 36, count 0 2006.257.12:38:47.95#ibcon#flushed, iclass 36, count 0 2006.257.12:38:47.95#ibcon#about to write, iclass 36, count 0 2006.257.12:38:47.95#ibcon#wrote, iclass 36, count 0 2006.257.12:38:47.95#ibcon#about to read 3, iclass 36, count 0 2006.257.12:38:47.98#ibcon#read 3, iclass 36, count 0 2006.257.12:38:47.98#ibcon#about to read 4, iclass 36, count 0 2006.257.12:38:47.98#ibcon#read 4, iclass 36, count 0 2006.257.12:38:47.98#ibcon#about to read 5, iclass 36, count 0 2006.257.12:38:47.98#ibcon#read 5, iclass 36, count 0 2006.257.12:38:47.98#ibcon#about to read 6, iclass 36, count 0 2006.257.12:38:47.98#ibcon#read 6, iclass 36, count 0 2006.257.12:38:47.98#ibcon#end of sib2, iclass 36, count 0 2006.257.12:38:47.98#ibcon#*after write, iclass 36, count 0 2006.257.12:38:47.98#ibcon#*before return 0, iclass 36, count 0 2006.257.12:38:47.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:38:47.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.12:38:47.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.12:38:47.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.12:38:47.99$vck44/vb=1,4 2006.257.12:38:47.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.12:38:47.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.12:38:47.99#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:47.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:38:47.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:38:47.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:38:47.99#ibcon#enter wrdev, iclass 38, count 2 2006.257.12:38:47.99#ibcon#first serial, iclass 38, count 2 2006.257.12:38:47.99#ibcon#enter sib2, iclass 38, count 2 2006.257.12:38:47.99#ibcon#flushed, iclass 38, count 2 2006.257.12:38:47.99#ibcon#about to write, iclass 38, count 2 2006.257.12:38:47.99#ibcon#wrote, iclass 38, count 2 2006.257.12:38:47.99#ibcon#about to read 3, iclass 38, count 2 2006.257.12:38:48.00#ibcon#read 3, iclass 38, count 2 2006.257.12:38:48.00#ibcon#about to read 4, iclass 38, count 2 2006.257.12:38:48.00#ibcon#read 4, iclass 38, count 2 2006.257.12:38:48.00#ibcon#about to read 5, iclass 38, count 2 2006.257.12:38:48.00#ibcon#read 5, iclass 38, count 2 2006.257.12:38:48.00#ibcon#about to read 6, iclass 38, count 2 2006.257.12:38:48.00#ibcon#read 6, iclass 38, count 2 2006.257.12:38:48.00#ibcon#end of sib2, iclass 38, count 2 2006.257.12:38:48.00#ibcon#*mode == 0, iclass 38, count 2 2006.257.12:38:48.00#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.12:38:48.00#ibcon#[27=AT01-04\r\n] 2006.257.12:38:48.01#ibcon#*before write, iclass 38, count 2 2006.257.12:38:48.01#ibcon#enter sib2, iclass 38, count 2 2006.257.12:38:48.01#ibcon#flushed, iclass 38, count 2 2006.257.12:38:48.01#ibcon#about to write, iclass 38, count 2 2006.257.12:38:48.01#ibcon#wrote, iclass 38, count 2 2006.257.12:38:48.01#ibcon#about to read 3, iclass 38, count 2 2006.257.12:38:48.03#ibcon#read 3, iclass 38, count 2 2006.257.12:38:48.03#ibcon#about to read 4, iclass 38, count 2 2006.257.12:38:48.03#ibcon#read 4, iclass 38, count 2 2006.257.12:38:48.03#ibcon#about to read 5, iclass 38, count 2 2006.257.12:38:48.03#ibcon#read 5, iclass 38, count 2 2006.257.12:38:48.03#ibcon#about to read 6, iclass 38, count 2 2006.257.12:38:48.03#ibcon#read 6, iclass 38, count 2 2006.257.12:38:48.03#ibcon#end of sib2, iclass 38, count 2 2006.257.12:38:48.03#ibcon#*after write, iclass 38, count 2 2006.257.12:38:48.03#ibcon#*before return 0, iclass 38, count 2 2006.257.12:38:48.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:38:48.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.12:38:48.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.12:38:48.04#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:48.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:38:48.15#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:38:48.15#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:38:48.15#ibcon#enter wrdev, iclass 38, count 0 2006.257.12:38:48.15#ibcon#first serial, iclass 38, count 0 2006.257.12:38:48.15#ibcon#enter sib2, iclass 38, count 0 2006.257.12:38:48.15#ibcon#flushed, iclass 38, count 0 2006.257.12:38:48.15#ibcon#about to write, iclass 38, count 0 2006.257.12:38:48.15#ibcon#wrote, iclass 38, count 0 2006.257.12:38:48.15#ibcon#about to read 3, iclass 38, count 0 2006.257.12:38:48.17#ibcon#read 3, iclass 38, count 0 2006.257.12:38:48.17#ibcon#about to read 4, iclass 38, count 0 2006.257.12:38:48.17#ibcon#read 4, iclass 38, count 0 2006.257.12:38:48.17#ibcon#about to read 5, iclass 38, count 0 2006.257.12:38:48.17#ibcon#read 5, iclass 38, count 0 2006.257.12:38:48.17#ibcon#about to read 6, iclass 38, count 0 2006.257.12:38:48.17#ibcon#read 6, iclass 38, count 0 2006.257.12:38:48.17#ibcon#end of sib2, iclass 38, count 0 2006.257.12:38:48.17#ibcon#*mode == 0, iclass 38, count 0 2006.257.12:38:48.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.12:38:48.17#ibcon#[27=USB\r\n] 2006.257.12:38:48.18#ibcon#*before write, iclass 38, count 0 2006.257.12:38:48.18#ibcon#enter sib2, iclass 38, count 0 2006.257.12:38:48.18#ibcon#flushed, iclass 38, count 0 2006.257.12:38:48.18#ibcon#about to write, iclass 38, count 0 2006.257.12:38:48.18#ibcon#wrote, iclass 38, count 0 2006.257.12:38:48.18#ibcon#about to read 3, iclass 38, count 0 2006.257.12:38:48.20#ibcon#read 3, iclass 38, count 0 2006.257.12:38:48.20#ibcon#about to read 4, iclass 38, count 0 2006.257.12:38:48.20#ibcon#read 4, iclass 38, count 0 2006.257.12:38:48.20#ibcon#about to read 5, iclass 38, count 0 2006.257.12:38:48.20#ibcon#read 5, iclass 38, count 0 2006.257.12:38:48.20#ibcon#about to read 6, iclass 38, count 0 2006.257.12:38:48.20#ibcon#read 6, iclass 38, count 0 2006.257.12:38:48.20#ibcon#end of sib2, iclass 38, count 0 2006.257.12:38:48.20#ibcon#*after write, iclass 38, count 0 2006.257.12:38:48.20#ibcon#*before return 0, iclass 38, count 0 2006.257.12:38:48.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:38:48.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.12:38:48.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.12:38:48.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.12:38:48.21$vck44/vblo=2,634.99 2006.257.12:38:48.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.12:38:48.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.12:38:48.21#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:48.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:48.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:48.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:48.21#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:38:48.21#ibcon#first serial, iclass 40, count 0 2006.257.12:38:48.21#ibcon#enter sib2, iclass 40, count 0 2006.257.12:38:48.21#ibcon#flushed, iclass 40, count 0 2006.257.12:38:48.21#ibcon#about to write, iclass 40, count 0 2006.257.12:38:48.21#ibcon#wrote, iclass 40, count 0 2006.257.12:38:48.21#ibcon#about to read 3, iclass 40, count 0 2006.257.12:38:48.22#ibcon#read 3, iclass 40, count 0 2006.257.12:38:48.22#ibcon#about to read 4, iclass 40, count 0 2006.257.12:38:48.22#ibcon#read 4, iclass 40, count 0 2006.257.12:38:48.22#ibcon#about to read 5, iclass 40, count 0 2006.257.12:38:48.22#ibcon#read 5, iclass 40, count 0 2006.257.12:38:48.22#ibcon#about to read 6, iclass 40, count 0 2006.257.12:38:48.22#ibcon#read 6, iclass 40, count 0 2006.257.12:38:48.22#ibcon#end of sib2, iclass 40, count 0 2006.257.12:38:48.22#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:38:48.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:38:48.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:38:48.22#ibcon#*before write, iclass 40, count 0 2006.257.12:38:48.23#ibcon#enter sib2, iclass 40, count 0 2006.257.12:38:48.23#ibcon#flushed, iclass 40, count 0 2006.257.12:38:48.23#ibcon#about to write, iclass 40, count 0 2006.257.12:38:48.23#ibcon#wrote, iclass 40, count 0 2006.257.12:38:48.23#ibcon#about to read 3, iclass 40, count 0 2006.257.12:38:48.26#ibcon#read 3, iclass 40, count 0 2006.257.12:38:48.26#ibcon#about to read 4, iclass 40, count 0 2006.257.12:38:48.26#ibcon#read 4, iclass 40, count 0 2006.257.12:38:48.26#ibcon#about to read 5, iclass 40, count 0 2006.257.12:38:48.26#ibcon#read 5, iclass 40, count 0 2006.257.12:38:48.26#ibcon#about to read 6, iclass 40, count 0 2006.257.12:38:48.26#ibcon#read 6, iclass 40, count 0 2006.257.12:38:48.26#ibcon#end of sib2, iclass 40, count 0 2006.257.12:38:48.26#ibcon#*after write, iclass 40, count 0 2006.257.12:38:48.26#ibcon#*before return 0, iclass 40, count 0 2006.257.12:38:48.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:48.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.12:38:48.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:38:48.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:38:48.27$vck44/vb=2,5 2006.257.12:38:48.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.12:38:48.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.12:38:48.27#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:48.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:48.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:48.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:48.32#ibcon#enter wrdev, iclass 4, count 2 2006.257.12:38:48.32#ibcon#first serial, iclass 4, count 2 2006.257.12:38:48.32#ibcon#enter sib2, iclass 4, count 2 2006.257.12:38:48.32#ibcon#flushed, iclass 4, count 2 2006.257.12:38:48.32#ibcon#about to write, iclass 4, count 2 2006.257.12:38:48.32#ibcon#wrote, iclass 4, count 2 2006.257.12:38:48.32#ibcon#about to read 3, iclass 4, count 2 2006.257.12:38:48.34#ibcon#read 3, iclass 4, count 2 2006.257.12:38:48.34#ibcon#about to read 4, iclass 4, count 2 2006.257.12:38:48.34#ibcon#read 4, iclass 4, count 2 2006.257.12:38:48.34#ibcon#about to read 5, iclass 4, count 2 2006.257.12:38:48.34#ibcon#read 5, iclass 4, count 2 2006.257.12:38:48.34#ibcon#about to read 6, iclass 4, count 2 2006.257.12:38:48.34#ibcon#read 6, iclass 4, count 2 2006.257.12:38:48.34#ibcon#end of sib2, iclass 4, count 2 2006.257.12:38:48.34#ibcon#*mode == 0, iclass 4, count 2 2006.257.12:38:48.34#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.12:38:48.34#ibcon#[27=AT02-05\r\n] 2006.257.12:38:48.35#ibcon#*before write, iclass 4, count 2 2006.257.12:38:48.35#ibcon#enter sib2, iclass 4, count 2 2006.257.12:38:48.35#ibcon#flushed, iclass 4, count 2 2006.257.12:38:48.35#ibcon#about to write, iclass 4, count 2 2006.257.12:38:48.35#ibcon#wrote, iclass 4, count 2 2006.257.12:38:48.35#ibcon#about to read 3, iclass 4, count 2 2006.257.12:38:48.37#ibcon#read 3, iclass 4, count 2 2006.257.12:38:48.42#ibcon#about to read 4, iclass 4, count 2 2006.257.12:38:48.42#ibcon#read 4, iclass 4, count 2 2006.257.12:38:48.42#ibcon#about to read 5, iclass 4, count 2 2006.257.12:38:48.42#ibcon#read 5, iclass 4, count 2 2006.257.12:38:48.42#ibcon#about to read 6, iclass 4, count 2 2006.257.12:38:48.43#ibcon#read 6, iclass 4, count 2 2006.257.12:38:48.43#ibcon#end of sib2, iclass 4, count 2 2006.257.12:38:48.43#ibcon#*after write, iclass 4, count 2 2006.257.12:38:48.43#ibcon#*before return 0, iclass 4, count 2 2006.257.12:38:48.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:48.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.12:38:48.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.12:38:48.43#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:48.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:48.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:48.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:48.54#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:38:48.54#ibcon#first serial, iclass 4, count 0 2006.257.12:38:48.54#ibcon#enter sib2, iclass 4, count 0 2006.257.12:38:48.54#ibcon#flushed, iclass 4, count 0 2006.257.12:38:48.54#ibcon#about to write, iclass 4, count 0 2006.257.12:38:48.54#ibcon#wrote, iclass 4, count 0 2006.257.12:38:48.54#ibcon#about to read 3, iclass 4, count 0 2006.257.12:38:48.57#ibcon#read 3, iclass 4, count 0 2006.257.12:38:48.57#ibcon#about to read 4, iclass 4, count 0 2006.257.12:38:48.57#ibcon#read 4, iclass 4, count 0 2006.257.12:38:48.57#ibcon#about to read 5, iclass 4, count 0 2006.257.12:38:48.57#ibcon#read 5, iclass 4, count 0 2006.257.12:38:48.57#ibcon#about to read 6, iclass 4, count 0 2006.257.12:38:48.57#ibcon#read 6, iclass 4, count 0 2006.257.12:38:48.57#ibcon#end of sib2, iclass 4, count 0 2006.257.12:38:48.57#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:38:48.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:38:48.57#ibcon#[27=USB\r\n] 2006.257.12:38:48.57#ibcon#*before write, iclass 4, count 0 2006.257.12:38:48.57#ibcon#enter sib2, iclass 4, count 0 2006.257.12:38:48.57#ibcon#flushed, iclass 4, count 0 2006.257.12:38:48.57#ibcon#about to write, iclass 4, count 0 2006.257.12:38:48.57#ibcon#wrote, iclass 4, count 0 2006.257.12:38:48.57#ibcon#about to read 3, iclass 4, count 0 2006.257.12:38:48.59#ibcon#read 3, iclass 4, count 0 2006.257.12:38:48.59#ibcon#about to read 4, iclass 4, count 0 2006.257.12:38:48.59#ibcon#read 4, iclass 4, count 0 2006.257.12:38:48.59#ibcon#about to read 5, iclass 4, count 0 2006.257.12:38:48.59#ibcon#read 5, iclass 4, count 0 2006.257.12:38:48.59#ibcon#about to read 6, iclass 4, count 0 2006.257.12:38:48.59#ibcon#read 6, iclass 4, count 0 2006.257.12:38:48.59#ibcon#end of sib2, iclass 4, count 0 2006.257.12:38:48.59#ibcon#*after write, iclass 4, count 0 2006.257.12:38:48.60#ibcon#*before return 0, iclass 4, count 0 2006.257.12:38:48.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:48.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.12:38:48.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:38:48.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:38:48.60$vck44/vblo=3,649.99 2006.257.12:38:48.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.12:38:48.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.12:38:48.60#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:48.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:48.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:48.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:48.60#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:38:48.60#ibcon#first serial, iclass 6, count 0 2006.257.12:38:48.60#ibcon#enter sib2, iclass 6, count 0 2006.257.12:38:48.60#ibcon#flushed, iclass 6, count 0 2006.257.12:38:48.60#ibcon#about to write, iclass 6, count 0 2006.257.12:38:48.60#ibcon#wrote, iclass 6, count 0 2006.257.12:38:48.60#ibcon#about to read 3, iclass 6, count 0 2006.257.12:38:48.61#ibcon#read 3, iclass 6, count 0 2006.257.12:38:48.61#ibcon#about to read 4, iclass 6, count 0 2006.257.12:38:48.61#ibcon#read 4, iclass 6, count 0 2006.257.12:38:48.61#ibcon#about to read 5, iclass 6, count 0 2006.257.12:38:48.61#ibcon#read 5, iclass 6, count 0 2006.257.12:38:48.61#ibcon#about to read 6, iclass 6, count 0 2006.257.12:38:48.61#ibcon#read 6, iclass 6, count 0 2006.257.12:38:48.61#ibcon#end of sib2, iclass 6, count 0 2006.257.12:38:48.61#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:38:48.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:38:48.61#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:38:48.61#ibcon#*before write, iclass 6, count 0 2006.257.12:38:48.61#ibcon#enter sib2, iclass 6, count 0 2006.257.12:38:48.61#ibcon#flushed, iclass 6, count 0 2006.257.12:38:48.62#ibcon#about to write, iclass 6, count 0 2006.257.12:38:48.62#ibcon#wrote, iclass 6, count 0 2006.257.12:38:48.62#ibcon#about to read 3, iclass 6, count 0 2006.257.12:38:48.65#ibcon#read 3, iclass 6, count 0 2006.257.12:38:48.65#ibcon#about to read 4, iclass 6, count 0 2006.257.12:38:48.65#ibcon#read 4, iclass 6, count 0 2006.257.12:38:48.65#ibcon#about to read 5, iclass 6, count 0 2006.257.12:38:48.65#ibcon#read 5, iclass 6, count 0 2006.257.12:38:48.65#ibcon#about to read 6, iclass 6, count 0 2006.257.12:38:48.65#ibcon#read 6, iclass 6, count 0 2006.257.12:38:48.65#ibcon#end of sib2, iclass 6, count 0 2006.257.12:38:48.65#ibcon#*after write, iclass 6, count 0 2006.257.12:38:48.66#ibcon#*before return 0, iclass 6, count 0 2006.257.12:38:48.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:48.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.12:38:48.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:38:48.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:38:48.66$vck44/vb=3,4 2006.257.12:38:48.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.12:38:48.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.12:38:48.66#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:48.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:48.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:48.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:48.71#ibcon#enter wrdev, iclass 10, count 2 2006.257.12:38:48.71#ibcon#first serial, iclass 10, count 2 2006.257.12:38:48.71#ibcon#enter sib2, iclass 10, count 2 2006.257.12:38:48.71#ibcon#flushed, iclass 10, count 2 2006.257.12:38:48.71#ibcon#about to write, iclass 10, count 2 2006.257.12:38:48.71#ibcon#wrote, iclass 10, count 2 2006.257.12:38:48.71#ibcon#about to read 3, iclass 10, count 2 2006.257.12:38:48.73#ibcon#read 3, iclass 10, count 2 2006.257.12:38:48.73#ibcon#about to read 4, iclass 10, count 2 2006.257.12:38:48.73#ibcon#read 4, iclass 10, count 2 2006.257.12:38:48.73#ibcon#about to read 5, iclass 10, count 2 2006.257.12:38:48.73#ibcon#read 5, iclass 10, count 2 2006.257.12:38:48.73#ibcon#about to read 6, iclass 10, count 2 2006.257.12:38:48.73#ibcon#read 6, iclass 10, count 2 2006.257.12:38:48.73#ibcon#end of sib2, iclass 10, count 2 2006.257.12:38:48.73#ibcon#*mode == 0, iclass 10, count 2 2006.257.12:38:48.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.12:38:48.74#ibcon#[27=AT03-04\r\n] 2006.257.12:38:48.74#ibcon#*before write, iclass 10, count 2 2006.257.12:38:48.74#ibcon#enter sib2, iclass 10, count 2 2006.257.12:38:48.74#ibcon#flushed, iclass 10, count 2 2006.257.12:38:48.74#ibcon#about to write, iclass 10, count 2 2006.257.12:38:48.74#ibcon#wrote, iclass 10, count 2 2006.257.12:38:48.74#ibcon#about to read 3, iclass 10, count 2 2006.257.12:38:48.76#ibcon#read 3, iclass 10, count 2 2006.257.12:38:48.76#ibcon#about to read 4, iclass 10, count 2 2006.257.12:38:48.76#ibcon#read 4, iclass 10, count 2 2006.257.12:38:48.76#ibcon#about to read 5, iclass 10, count 2 2006.257.12:38:48.76#ibcon#read 5, iclass 10, count 2 2006.257.12:38:48.76#ibcon#about to read 6, iclass 10, count 2 2006.257.12:38:48.76#ibcon#read 6, iclass 10, count 2 2006.257.12:38:48.76#ibcon#end of sib2, iclass 10, count 2 2006.257.12:38:48.76#ibcon#*after write, iclass 10, count 2 2006.257.12:38:48.76#ibcon#*before return 0, iclass 10, count 2 2006.257.12:38:48.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:48.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.12:38:48.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.12:38:48.77#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:48.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:48.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:48.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:48.88#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:38:48.88#ibcon#first serial, iclass 10, count 0 2006.257.12:38:48.88#ibcon#enter sib2, iclass 10, count 0 2006.257.12:38:48.88#ibcon#flushed, iclass 10, count 0 2006.257.12:38:48.88#ibcon#about to write, iclass 10, count 0 2006.257.12:38:48.88#ibcon#wrote, iclass 10, count 0 2006.257.12:38:48.88#ibcon#about to read 3, iclass 10, count 0 2006.257.12:38:48.90#ibcon#read 3, iclass 10, count 0 2006.257.12:38:48.90#ibcon#about to read 4, iclass 10, count 0 2006.257.12:38:48.90#ibcon#read 4, iclass 10, count 0 2006.257.12:38:48.90#ibcon#about to read 5, iclass 10, count 0 2006.257.12:38:48.90#ibcon#read 5, iclass 10, count 0 2006.257.12:38:48.90#ibcon#about to read 6, iclass 10, count 0 2006.257.12:38:48.90#ibcon#read 6, iclass 10, count 0 2006.257.12:38:48.90#ibcon#end of sib2, iclass 10, count 0 2006.257.12:38:48.90#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:38:48.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:38:48.90#ibcon#[27=USB\r\n] 2006.257.12:38:48.90#ibcon#*before write, iclass 10, count 0 2006.257.12:38:48.90#ibcon#enter sib2, iclass 10, count 0 2006.257.12:38:48.90#ibcon#flushed, iclass 10, count 0 2006.257.12:38:48.90#ibcon#about to write, iclass 10, count 0 2006.257.12:38:48.91#ibcon#wrote, iclass 10, count 0 2006.257.12:38:48.91#ibcon#about to read 3, iclass 10, count 0 2006.257.12:38:48.93#ibcon#read 3, iclass 10, count 0 2006.257.12:38:48.93#ibcon#about to read 4, iclass 10, count 0 2006.257.12:38:48.93#ibcon#read 4, iclass 10, count 0 2006.257.12:38:48.93#ibcon#about to read 5, iclass 10, count 0 2006.257.12:38:48.93#ibcon#read 5, iclass 10, count 0 2006.257.12:38:48.93#ibcon#about to read 6, iclass 10, count 0 2006.257.12:38:48.93#ibcon#read 6, iclass 10, count 0 2006.257.12:38:48.93#ibcon#end of sib2, iclass 10, count 0 2006.257.12:38:48.93#ibcon#*after write, iclass 10, count 0 2006.257.12:38:48.93#ibcon#*before return 0, iclass 10, count 0 2006.257.12:38:48.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:48.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.12:38:48.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:38:48.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:38:48.94$vck44/vblo=4,679.99 2006.257.12:38:48.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.12:38:48.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.12:38:48.94#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:48.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:48.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:48.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:48.94#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:38:48.94#ibcon#first serial, iclass 12, count 0 2006.257.12:38:48.94#ibcon#enter sib2, iclass 12, count 0 2006.257.12:38:48.94#ibcon#flushed, iclass 12, count 0 2006.257.12:38:48.94#ibcon#about to write, iclass 12, count 0 2006.257.12:38:48.94#ibcon#wrote, iclass 12, count 0 2006.257.12:38:48.94#ibcon#about to read 3, iclass 12, count 0 2006.257.12:38:48.95#ibcon#read 3, iclass 12, count 0 2006.257.12:38:48.95#ibcon#about to read 4, iclass 12, count 0 2006.257.12:38:48.95#ibcon#read 4, iclass 12, count 0 2006.257.12:38:48.95#ibcon#about to read 5, iclass 12, count 0 2006.257.12:38:48.95#ibcon#read 5, iclass 12, count 0 2006.257.12:38:48.95#ibcon#about to read 6, iclass 12, count 0 2006.257.12:38:48.95#ibcon#read 6, iclass 12, count 0 2006.257.12:38:48.95#ibcon#end of sib2, iclass 12, count 0 2006.257.12:38:48.95#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:38:48.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:38:48.95#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:38:48.95#ibcon#*before write, iclass 12, count 0 2006.257.12:38:48.95#ibcon#enter sib2, iclass 12, count 0 2006.257.12:38:48.96#ibcon#flushed, iclass 12, count 0 2006.257.12:38:48.96#ibcon#about to write, iclass 12, count 0 2006.257.12:38:48.96#ibcon#wrote, iclass 12, count 0 2006.257.12:38:48.96#ibcon#about to read 3, iclass 12, count 0 2006.257.12:38:48.99#ibcon#read 3, iclass 12, count 0 2006.257.12:38:48.99#ibcon#about to read 4, iclass 12, count 0 2006.257.12:38:48.99#ibcon#read 4, iclass 12, count 0 2006.257.12:38:48.99#ibcon#about to read 5, iclass 12, count 0 2006.257.12:38:48.99#ibcon#read 5, iclass 12, count 0 2006.257.12:38:48.99#ibcon#about to read 6, iclass 12, count 0 2006.257.12:38:48.99#ibcon#read 6, iclass 12, count 0 2006.257.12:38:48.99#ibcon#end of sib2, iclass 12, count 0 2006.257.12:38:48.99#ibcon#*after write, iclass 12, count 0 2006.257.12:38:48.99#ibcon#*before return 0, iclass 12, count 0 2006.257.12:38:48.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:49.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.12:38:49.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:38:49.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:38:49.00$vck44/vb=4,5 2006.257.12:38:49.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.12:38:49.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.12:38:49.00#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:49.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:49.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:49.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:49.05#ibcon#enter wrdev, iclass 14, count 2 2006.257.12:38:49.05#ibcon#first serial, iclass 14, count 2 2006.257.12:38:49.05#ibcon#enter sib2, iclass 14, count 2 2006.257.12:38:49.05#ibcon#flushed, iclass 14, count 2 2006.257.12:38:49.05#ibcon#about to write, iclass 14, count 2 2006.257.12:38:49.05#ibcon#wrote, iclass 14, count 2 2006.257.12:38:49.05#ibcon#about to read 3, iclass 14, count 2 2006.257.12:38:49.07#ibcon#read 3, iclass 14, count 2 2006.257.12:38:49.07#ibcon#about to read 4, iclass 14, count 2 2006.257.12:38:49.07#ibcon#read 4, iclass 14, count 2 2006.257.12:38:49.07#ibcon#about to read 5, iclass 14, count 2 2006.257.12:38:49.07#ibcon#read 5, iclass 14, count 2 2006.257.12:38:49.07#ibcon#about to read 6, iclass 14, count 2 2006.257.12:38:49.07#ibcon#read 6, iclass 14, count 2 2006.257.12:38:49.07#ibcon#end of sib2, iclass 14, count 2 2006.257.12:38:49.07#ibcon#*mode == 0, iclass 14, count 2 2006.257.12:38:49.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.12:38:49.07#ibcon#[27=AT04-05\r\n] 2006.257.12:38:49.08#ibcon#*before write, iclass 14, count 2 2006.257.12:38:49.08#ibcon#enter sib2, iclass 14, count 2 2006.257.12:38:49.08#ibcon#flushed, iclass 14, count 2 2006.257.12:38:49.08#ibcon#about to write, iclass 14, count 2 2006.257.12:38:49.08#ibcon#wrote, iclass 14, count 2 2006.257.12:38:49.08#ibcon#about to read 3, iclass 14, count 2 2006.257.12:38:49.10#ibcon#read 3, iclass 14, count 2 2006.257.12:38:49.10#ibcon#about to read 4, iclass 14, count 2 2006.257.12:38:49.10#ibcon#read 4, iclass 14, count 2 2006.257.12:38:49.10#ibcon#about to read 5, iclass 14, count 2 2006.257.12:38:49.10#ibcon#read 5, iclass 14, count 2 2006.257.12:38:49.10#ibcon#about to read 6, iclass 14, count 2 2006.257.12:38:49.10#ibcon#read 6, iclass 14, count 2 2006.257.12:38:49.10#ibcon#end of sib2, iclass 14, count 2 2006.257.12:38:49.10#ibcon#*after write, iclass 14, count 2 2006.257.12:38:49.10#ibcon#*before return 0, iclass 14, count 2 2006.257.12:38:49.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:49.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.12:38:49.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.12:38:49.11#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:49.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:49.21#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:49.21#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:49.21#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:38:49.21#ibcon#first serial, iclass 14, count 0 2006.257.12:38:49.21#ibcon#enter sib2, iclass 14, count 0 2006.257.12:38:49.21#ibcon#flushed, iclass 14, count 0 2006.257.12:38:49.21#ibcon#about to write, iclass 14, count 0 2006.257.12:38:49.21#ibcon#wrote, iclass 14, count 0 2006.257.12:38:49.21#ibcon#about to read 3, iclass 14, count 0 2006.257.12:38:49.23#ibcon#read 3, iclass 14, count 0 2006.257.12:38:49.23#ibcon#about to read 4, iclass 14, count 0 2006.257.12:38:49.23#ibcon#read 4, iclass 14, count 0 2006.257.12:38:49.23#ibcon#about to read 5, iclass 14, count 0 2006.257.12:38:49.23#ibcon#read 5, iclass 14, count 0 2006.257.12:38:49.23#ibcon#about to read 6, iclass 14, count 0 2006.257.12:38:49.23#ibcon#read 6, iclass 14, count 0 2006.257.12:38:49.23#ibcon#end of sib2, iclass 14, count 0 2006.257.12:38:49.23#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:38:49.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:38:49.23#ibcon#[27=USB\r\n] 2006.257.12:38:49.23#ibcon#*before write, iclass 14, count 0 2006.257.12:38:49.23#ibcon#enter sib2, iclass 14, count 0 2006.257.12:38:49.24#ibcon#flushed, iclass 14, count 0 2006.257.12:38:49.24#ibcon#about to write, iclass 14, count 0 2006.257.12:38:49.24#ibcon#wrote, iclass 14, count 0 2006.257.12:38:49.24#ibcon#about to read 3, iclass 14, count 0 2006.257.12:38:49.26#ibcon#read 3, iclass 14, count 0 2006.257.12:38:49.26#ibcon#about to read 4, iclass 14, count 0 2006.257.12:38:49.26#ibcon#read 4, iclass 14, count 0 2006.257.12:38:49.26#ibcon#about to read 5, iclass 14, count 0 2006.257.12:38:49.26#ibcon#read 5, iclass 14, count 0 2006.257.12:38:49.26#ibcon#about to read 6, iclass 14, count 0 2006.257.12:38:49.26#ibcon#read 6, iclass 14, count 0 2006.257.12:38:49.26#ibcon#end of sib2, iclass 14, count 0 2006.257.12:38:49.26#ibcon#*after write, iclass 14, count 0 2006.257.12:38:49.26#ibcon#*before return 0, iclass 14, count 0 2006.257.12:38:49.26#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:49.26#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.12:38:49.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:38:49.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:38:49.27$vck44/vblo=5,709.99 2006.257.12:38:49.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.12:38:49.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.12:38:49.27#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:49.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:49.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:49.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:49.27#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:38:49.27#ibcon#first serial, iclass 16, count 0 2006.257.12:38:49.27#ibcon#enter sib2, iclass 16, count 0 2006.257.12:38:49.27#ibcon#flushed, iclass 16, count 0 2006.257.12:38:49.27#ibcon#about to write, iclass 16, count 0 2006.257.12:38:49.27#ibcon#wrote, iclass 16, count 0 2006.257.12:38:49.27#ibcon#about to read 3, iclass 16, count 0 2006.257.12:38:49.28#ibcon#read 3, iclass 16, count 0 2006.257.12:38:49.28#ibcon#about to read 4, iclass 16, count 0 2006.257.12:38:49.28#ibcon#read 4, iclass 16, count 0 2006.257.12:38:49.28#ibcon#about to read 5, iclass 16, count 0 2006.257.12:38:49.28#ibcon#read 5, iclass 16, count 0 2006.257.12:38:49.28#ibcon#about to read 6, iclass 16, count 0 2006.257.12:38:49.28#ibcon#read 6, iclass 16, count 0 2006.257.12:38:49.28#ibcon#end of sib2, iclass 16, count 0 2006.257.12:38:49.28#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:38:49.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:38:49.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:38:49.29#ibcon#*before write, iclass 16, count 0 2006.257.12:38:49.29#ibcon#enter sib2, iclass 16, count 0 2006.257.12:38:49.29#ibcon#flushed, iclass 16, count 0 2006.257.12:38:49.29#ibcon#about to write, iclass 16, count 0 2006.257.12:38:49.29#ibcon#wrote, iclass 16, count 0 2006.257.12:38:49.29#ibcon#about to read 3, iclass 16, count 0 2006.257.12:38:49.32#ibcon#read 3, iclass 16, count 0 2006.257.12:38:49.32#ibcon#about to read 4, iclass 16, count 0 2006.257.12:38:49.32#ibcon#read 4, iclass 16, count 0 2006.257.12:38:49.32#ibcon#about to read 5, iclass 16, count 0 2006.257.12:38:49.32#ibcon#read 5, iclass 16, count 0 2006.257.12:38:49.32#ibcon#about to read 6, iclass 16, count 0 2006.257.12:38:49.32#ibcon#read 6, iclass 16, count 0 2006.257.12:38:49.32#ibcon#end of sib2, iclass 16, count 0 2006.257.12:38:49.32#ibcon#*after write, iclass 16, count 0 2006.257.12:38:49.32#ibcon#*before return 0, iclass 16, count 0 2006.257.12:38:49.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:49.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.12:38:49.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:38:49.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:38:49.33$vck44/vb=5,4 2006.257.12:38:49.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.12:38:49.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.12:38:49.33#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:49.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:49.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:49.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:49.37#ibcon#enter wrdev, iclass 18, count 2 2006.257.12:38:49.37#ibcon#first serial, iclass 18, count 2 2006.257.12:38:49.37#ibcon#enter sib2, iclass 18, count 2 2006.257.12:38:49.37#ibcon#flushed, iclass 18, count 2 2006.257.12:38:49.37#ibcon#about to write, iclass 18, count 2 2006.257.12:38:49.37#ibcon#wrote, iclass 18, count 2 2006.257.12:38:49.37#ibcon#about to read 3, iclass 18, count 2 2006.257.12:38:49.39#ibcon#read 3, iclass 18, count 2 2006.257.12:38:49.39#ibcon#about to read 4, iclass 18, count 2 2006.257.12:38:49.39#ibcon#read 4, iclass 18, count 2 2006.257.12:38:49.39#ibcon#about to read 5, iclass 18, count 2 2006.257.12:38:49.39#ibcon#read 5, iclass 18, count 2 2006.257.12:38:49.39#ibcon#about to read 6, iclass 18, count 2 2006.257.12:38:49.39#ibcon#read 6, iclass 18, count 2 2006.257.12:38:49.39#ibcon#end of sib2, iclass 18, count 2 2006.257.12:38:49.39#ibcon#*mode == 0, iclass 18, count 2 2006.257.12:38:49.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.12:38:49.39#ibcon#[27=AT05-04\r\n] 2006.257.12:38:49.39#ibcon#*before write, iclass 18, count 2 2006.257.12:38:49.39#ibcon#enter sib2, iclass 18, count 2 2006.257.12:38:49.40#ibcon#flushed, iclass 18, count 2 2006.257.12:38:49.40#ibcon#about to write, iclass 18, count 2 2006.257.12:38:49.40#ibcon#wrote, iclass 18, count 2 2006.257.12:38:49.40#ibcon#about to read 3, iclass 18, count 2 2006.257.12:38:49.42#ibcon#read 3, iclass 18, count 2 2006.257.12:38:49.42#ibcon#about to read 4, iclass 18, count 2 2006.257.12:38:49.42#ibcon#read 4, iclass 18, count 2 2006.257.12:38:49.42#ibcon#about to read 5, iclass 18, count 2 2006.257.12:38:49.42#ibcon#read 5, iclass 18, count 2 2006.257.12:38:49.42#ibcon#about to read 6, iclass 18, count 2 2006.257.12:38:49.42#ibcon#read 6, iclass 18, count 2 2006.257.12:38:49.42#ibcon#end of sib2, iclass 18, count 2 2006.257.12:38:49.42#ibcon#*after write, iclass 18, count 2 2006.257.12:38:49.47#ibcon#*before return 0, iclass 18, count 2 2006.257.12:38:49.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:49.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.12:38:49.47#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.12:38:49.47#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:49.47#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:49.58#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:49.58#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:49.58#ibcon#enter wrdev, iclass 18, count 0 2006.257.12:38:49.58#ibcon#first serial, iclass 18, count 0 2006.257.12:38:49.58#ibcon#enter sib2, iclass 18, count 0 2006.257.12:38:49.58#ibcon#flushed, iclass 18, count 0 2006.257.12:38:49.58#ibcon#about to write, iclass 18, count 0 2006.257.12:38:49.58#ibcon#wrote, iclass 18, count 0 2006.257.12:38:49.58#ibcon#about to read 3, iclass 18, count 0 2006.257.12:38:49.60#ibcon#read 3, iclass 18, count 0 2006.257.12:38:49.60#ibcon#about to read 4, iclass 18, count 0 2006.257.12:38:49.60#ibcon#read 4, iclass 18, count 0 2006.257.12:38:49.60#ibcon#about to read 5, iclass 18, count 0 2006.257.12:38:49.60#ibcon#read 5, iclass 18, count 0 2006.257.12:38:49.60#ibcon#about to read 6, iclass 18, count 0 2006.257.12:38:49.60#ibcon#read 6, iclass 18, count 0 2006.257.12:38:49.60#ibcon#end of sib2, iclass 18, count 0 2006.257.12:38:49.60#ibcon#*mode == 0, iclass 18, count 0 2006.257.12:38:49.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.12:38:49.61#ibcon#[27=USB\r\n] 2006.257.12:38:49.61#ibcon#*before write, iclass 18, count 0 2006.257.12:38:49.61#ibcon#enter sib2, iclass 18, count 0 2006.257.12:38:49.61#ibcon#flushed, iclass 18, count 0 2006.257.12:38:49.61#ibcon#about to write, iclass 18, count 0 2006.257.12:38:49.61#ibcon#wrote, iclass 18, count 0 2006.257.12:38:49.61#ibcon#about to read 3, iclass 18, count 0 2006.257.12:38:49.63#ibcon#read 3, iclass 18, count 0 2006.257.12:38:49.63#ibcon#about to read 4, iclass 18, count 0 2006.257.12:38:49.63#ibcon#read 4, iclass 18, count 0 2006.257.12:38:49.63#ibcon#about to read 5, iclass 18, count 0 2006.257.12:38:49.63#ibcon#read 5, iclass 18, count 0 2006.257.12:38:49.63#ibcon#about to read 6, iclass 18, count 0 2006.257.12:38:49.63#ibcon#read 6, iclass 18, count 0 2006.257.12:38:49.63#ibcon#end of sib2, iclass 18, count 0 2006.257.12:38:49.63#ibcon#*after write, iclass 18, count 0 2006.257.12:38:49.63#ibcon#*before return 0, iclass 18, count 0 2006.257.12:38:49.64#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:49.64#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.12:38:49.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.12:38:49.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.12:38:49.64$vck44/vblo=6,719.99 2006.257.12:38:49.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.12:38:49.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.12:38:49.64#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:49.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:49.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:49.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:49.64#ibcon#enter wrdev, iclass 20, count 0 2006.257.12:38:49.64#ibcon#first serial, iclass 20, count 0 2006.257.12:38:49.64#ibcon#enter sib2, iclass 20, count 0 2006.257.12:38:49.64#ibcon#flushed, iclass 20, count 0 2006.257.12:38:49.64#ibcon#about to write, iclass 20, count 0 2006.257.12:38:49.64#ibcon#wrote, iclass 20, count 0 2006.257.12:38:49.64#ibcon#about to read 3, iclass 20, count 0 2006.257.12:38:49.65#ibcon#read 3, iclass 20, count 0 2006.257.12:38:49.65#ibcon#about to read 4, iclass 20, count 0 2006.257.12:38:49.65#ibcon#read 4, iclass 20, count 0 2006.257.12:38:49.65#ibcon#about to read 5, iclass 20, count 0 2006.257.12:38:49.65#ibcon#read 5, iclass 20, count 0 2006.257.12:38:49.65#ibcon#about to read 6, iclass 20, count 0 2006.257.12:38:49.65#ibcon#read 6, iclass 20, count 0 2006.257.12:38:49.65#ibcon#end of sib2, iclass 20, count 0 2006.257.12:38:49.65#ibcon#*mode == 0, iclass 20, count 0 2006.257.12:38:49.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.12:38:49.65#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:38:49.65#ibcon#*before write, iclass 20, count 0 2006.257.12:38:49.66#ibcon#enter sib2, iclass 20, count 0 2006.257.12:38:49.66#ibcon#flushed, iclass 20, count 0 2006.257.12:38:49.66#ibcon#about to write, iclass 20, count 0 2006.257.12:38:49.66#ibcon#wrote, iclass 20, count 0 2006.257.12:38:49.66#ibcon#about to read 3, iclass 20, count 0 2006.257.12:38:49.69#ibcon#read 3, iclass 20, count 0 2006.257.12:38:49.69#ibcon#about to read 4, iclass 20, count 0 2006.257.12:38:49.69#ibcon#read 4, iclass 20, count 0 2006.257.12:38:49.69#ibcon#about to read 5, iclass 20, count 0 2006.257.12:38:49.69#ibcon#read 5, iclass 20, count 0 2006.257.12:38:49.69#ibcon#about to read 6, iclass 20, count 0 2006.257.12:38:49.69#ibcon#read 6, iclass 20, count 0 2006.257.12:38:49.69#ibcon#end of sib2, iclass 20, count 0 2006.257.12:38:49.69#ibcon#*after write, iclass 20, count 0 2006.257.12:38:49.69#ibcon#*before return 0, iclass 20, count 0 2006.257.12:38:49.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:49.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:38:49.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.12:38:49.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.12:38:49.70$vck44/vb=6,4 2006.257.12:38:49.70#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.12:38:49.70#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.12:38:49.70#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:49.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:49.75#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:49.75#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:49.75#ibcon#enter wrdev, iclass 22, count 2 2006.257.12:38:49.75#ibcon#first serial, iclass 22, count 2 2006.257.12:38:49.75#ibcon#enter sib2, iclass 22, count 2 2006.257.12:38:49.75#ibcon#flushed, iclass 22, count 2 2006.257.12:38:49.75#ibcon#about to write, iclass 22, count 2 2006.257.12:38:49.75#ibcon#wrote, iclass 22, count 2 2006.257.12:38:49.75#ibcon#about to read 3, iclass 22, count 2 2006.257.12:38:49.77#ibcon#read 3, iclass 22, count 2 2006.257.12:38:49.77#ibcon#about to read 4, iclass 22, count 2 2006.257.12:38:49.77#ibcon#read 4, iclass 22, count 2 2006.257.12:38:49.77#ibcon#about to read 5, iclass 22, count 2 2006.257.12:38:49.77#ibcon#read 5, iclass 22, count 2 2006.257.12:38:49.77#ibcon#about to read 6, iclass 22, count 2 2006.257.12:38:49.77#ibcon#read 6, iclass 22, count 2 2006.257.12:38:49.77#ibcon#end of sib2, iclass 22, count 2 2006.257.12:38:49.77#ibcon#*mode == 0, iclass 22, count 2 2006.257.12:38:49.77#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.12:38:49.77#ibcon#[27=AT06-04\r\n] 2006.257.12:38:49.78#ibcon#*before write, iclass 22, count 2 2006.257.12:38:49.78#ibcon#enter sib2, iclass 22, count 2 2006.257.12:38:49.78#ibcon#flushed, iclass 22, count 2 2006.257.12:38:49.78#ibcon#about to write, iclass 22, count 2 2006.257.12:38:49.78#ibcon#wrote, iclass 22, count 2 2006.257.12:38:49.78#ibcon#about to read 3, iclass 22, count 2 2006.257.12:38:49.80#ibcon#read 3, iclass 22, count 2 2006.257.12:38:49.80#ibcon#about to read 4, iclass 22, count 2 2006.257.12:38:49.80#ibcon#read 4, iclass 22, count 2 2006.257.12:38:49.80#ibcon#about to read 5, iclass 22, count 2 2006.257.12:38:49.80#ibcon#read 5, iclass 22, count 2 2006.257.12:38:49.80#ibcon#about to read 6, iclass 22, count 2 2006.257.12:38:49.80#ibcon#read 6, iclass 22, count 2 2006.257.12:38:49.80#ibcon#end of sib2, iclass 22, count 2 2006.257.12:38:49.80#ibcon#*after write, iclass 22, count 2 2006.257.12:38:49.80#ibcon#*before return 0, iclass 22, count 2 2006.257.12:38:49.81#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:49.81#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.12:38:49.81#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.12:38:49.81#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:49.81#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:49.92#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:49.92#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:49.92#ibcon#enter wrdev, iclass 22, count 0 2006.257.12:38:49.92#ibcon#first serial, iclass 22, count 0 2006.257.12:38:49.92#ibcon#enter sib2, iclass 22, count 0 2006.257.12:38:49.92#ibcon#flushed, iclass 22, count 0 2006.257.12:38:49.92#ibcon#about to write, iclass 22, count 0 2006.257.12:38:49.92#ibcon#wrote, iclass 22, count 0 2006.257.12:38:49.92#ibcon#about to read 3, iclass 22, count 0 2006.257.12:38:49.94#ibcon#read 3, iclass 22, count 0 2006.257.12:38:49.94#ibcon#about to read 4, iclass 22, count 0 2006.257.12:38:49.94#ibcon#read 4, iclass 22, count 0 2006.257.12:38:49.94#ibcon#about to read 5, iclass 22, count 0 2006.257.12:38:49.94#ibcon#read 5, iclass 22, count 0 2006.257.12:38:49.94#ibcon#about to read 6, iclass 22, count 0 2006.257.12:38:49.94#ibcon#read 6, iclass 22, count 0 2006.257.12:38:49.94#ibcon#end of sib2, iclass 22, count 0 2006.257.12:38:49.94#ibcon#*mode == 0, iclass 22, count 0 2006.257.12:38:49.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.12:38:49.94#ibcon#[27=USB\r\n] 2006.257.12:38:49.94#ibcon#*before write, iclass 22, count 0 2006.257.12:38:49.94#ibcon#enter sib2, iclass 22, count 0 2006.257.12:38:49.94#ibcon#flushed, iclass 22, count 0 2006.257.12:38:49.95#ibcon#about to write, iclass 22, count 0 2006.257.12:38:49.95#ibcon#wrote, iclass 22, count 0 2006.257.12:38:49.95#ibcon#about to read 3, iclass 22, count 0 2006.257.12:38:49.97#ibcon#read 3, iclass 22, count 0 2006.257.12:38:49.97#ibcon#about to read 4, iclass 22, count 0 2006.257.12:38:49.97#ibcon#read 4, iclass 22, count 0 2006.257.12:38:49.97#ibcon#about to read 5, iclass 22, count 0 2006.257.12:38:49.97#ibcon#read 5, iclass 22, count 0 2006.257.12:38:49.97#ibcon#about to read 6, iclass 22, count 0 2006.257.12:38:49.97#ibcon#read 6, iclass 22, count 0 2006.257.12:38:49.97#ibcon#end of sib2, iclass 22, count 0 2006.257.12:38:49.97#ibcon#*after write, iclass 22, count 0 2006.257.12:38:49.97#ibcon#*before return 0, iclass 22, count 0 2006.257.12:38:49.97#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:49.97#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.12:38:49.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.12:38:49.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.12:38:49.98$vck44/vblo=7,734.99 2006.257.12:38:49.98#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.12:38:49.98#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.12:38:49.98#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:49.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:49.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:49.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:49.98#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:38:49.98#ibcon#first serial, iclass 24, count 0 2006.257.12:38:49.98#ibcon#enter sib2, iclass 24, count 0 2006.257.12:38:49.98#ibcon#flushed, iclass 24, count 0 2006.257.12:38:49.98#ibcon#about to write, iclass 24, count 0 2006.257.12:38:49.98#ibcon#wrote, iclass 24, count 0 2006.257.12:38:49.98#ibcon#about to read 3, iclass 24, count 0 2006.257.12:38:49.99#ibcon#read 3, iclass 24, count 0 2006.257.12:38:49.99#ibcon#about to read 4, iclass 24, count 0 2006.257.12:38:49.99#ibcon#read 4, iclass 24, count 0 2006.257.12:38:49.99#ibcon#about to read 5, iclass 24, count 0 2006.257.12:38:49.99#ibcon#read 5, iclass 24, count 0 2006.257.12:38:49.99#ibcon#about to read 6, iclass 24, count 0 2006.257.12:38:49.99#ibcon#read 6, iclass 24, count 0 2006.257.12:38:49.99#ibcon#end of sib2, iclass 24, count 0 2006.257.12:38:49.99#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:38:49.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:38:49.99#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:38:49.99#ibcon#*before write, iclass 24, count 0 2006.257.12:38:49.99#ibcon#enter sib2, iclass 24, count 0 2006.257.12:38:49.99#ibcon#flushed, iclass 24, count 0 2006.257.12:38:50.00#ibcon#about to write, iclass 24, count 0 2006.257.12:38:50.00#ibcon#wrote, iclass 24, count 0 2006.257.12:38:50.00#ibcon#about to read 3, iclass 24, count 0 2006.257.12:38:50.03#ibcon#read 3, iclass 24, count 0 2006.257.12:38:50.03#ibcon#about to read 4, iclass 24, count 0 2006.257.12:38:50.03#ibcon#read 4, iclass 24, count 0 2006.257.12:38:50.03#ibcon#about to read 5, iclass 24, count 0 2006.257.12:38:50.03#ibcon#read 5, iclass 24, count 0 2006.257.12:38:50.03#ibcon#about to read 6, iclass 24, count 0 2006.257.12:38:50.03#ibcon#read 6, iclass 24, count 0 2006.257.12:38:50.03#ibcon#end of sib2, iclass 24, count 0 2006.257.12:38:50.03#ibcon#*after write, iclass 24, count 0 2006.257.12:38:50.03#ibcon#*before return 0, iclass 24, count 0 2006.257.12:38:50.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:50.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.12:38:50.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:38:50.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:38:50.04$vck44/vb=7,4 2006.257.12:38:50.04#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.12:38:50.04#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.12:38:50.04#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:50.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:50.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:50.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:50.08#ibcon#enter wrdev, iclass 26, count 2 2006.257.12:38:50.08#ibcon#first serial, iclass 26, count 2 2006.257.12:38:50.08#ibcon#enter sib2, iclass 26, count 2 2006.257.12:38:50.08#ibcon#flushed, iclass 26, count 2 2006.257.12:38:50.08#ibcon#about to write, iclass 26, count 2 2006.257.12:38:50.08#ibcon#wrote, iclass 26, count 2 2006.257.12:38:50.08#ibcon#about to read 3, iclass 26, count 2 2006.257.12:38:50.10#ibcon#read 3, iclass 26, count 2 2006.257.12:38:50.10#ibcon#about to read 4, iclass 26, count 2 2006.257.12:38:50.10#ibcon#read 4, iclass 26, count 2 2006.257.12:38:50.10#ibcon#about to read 5, iclass 26, count 2 2006.257.12:38:50.10#ibcon#read 5, iclass 26, count 2 2006.257.12:38:50.10#ibcon#about to read 6, iclass 26, count 2 2006.257.12:38:50.10#ibcon#read 6, iclass 26, count 2 2006.257.12:38:50.10#ibcon#end of sib2, iclass 26, count 2 2006.257.12:38:50.10#ibcon#*mode == 0, iclass 26, count 2 2006.257.12:38:50.10#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.12:38:50.10#ibcon#[27=AT07-04\r\n] 2006.257.12:38:50.10#ibcon#*before write, iclass 26, count 2 2006.257.12:38:50.10#ibcon#enter sib2, iclass 26, count 2 2006.257.12:38:50.10#ibcon#flushed, iclass 26, count 2 2006.257.12:38:50.11#ibcon#about to write, iclass 26, count 2 2006.257.12:38:50.11#ibcon#wrote, iclass 26, count 2 2006.257.12:38:50.11#ibcon#about to read 3, iclass 26, count 2 2006.257.12:38:50.13#ibcon#read 3, iclass 26, count 2 2006.257.12:38:50.13#ibcon#about to read 4, iclass 26, count 2 2006.257.12:38:50.13#ibcon#read 4, iclass 26, count 2 2006.257.12:38:50.13#ibcon#about to read 5, iclass 26, count 2 2006.257.12:38:50.13#ibcon#read 5, iclass 26, count 2 2006.257.12:38:50.13#ibcon#about to read 6, iclass 26, count 2 2006.257.12:38:50.13#ibcon#read 6, iclass 26, count 2 2006.257.12:38:50.13#ibcon#end of sib2, iclass 26, count 2 2006.257.12:38:50.13#ibcon#*after write, iclass 26, count 2 2006.257.12:38:50.13#ibcon#*before return 0, iclass 26, count 2 2006.257.12:38:50.14#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:50.14#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.12:38:50.14#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.12:38:50.14#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:50.14#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:50.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:50.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:50.25#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:38:50.25#ibcon#first serial, iclass 26, count 0 2006.257.12:38:50.25#ibcon#enter sib2, iclass 26, count 0 2006.257.12:38:50.25#ibcon#flushed, iclass 26, count 0 2006.257.12:38:50.25#ibcon#about to write, iclass 26, count 0 2006.257.12:38:50.25#ibcon#wrote, iclass 26, count 0 2006.257.12:38:50.25#ibcon#about to read 3, iclass 26, count 0 2006.257.12:38:50.27#ibcon#read 3, iclass 26, count 0 2006.257.12:38:50.27#ibcon#about to read 4, iclass 26, count 0 2006.257.12:38:50.27#ibcon#read 4, iclass 26, count 0 2006.257.12:38:50.27#ibcon#about to read 5, iclass 26, count 0 2006.257.12:38:50.27#ibcon#read 5, iclass 26, count 0 2006.257.12:38:50.27#ibcon#about to read 6, iclass 26, count 0 2006.257.12:38:50.27#ibcon#read 6, iclass 26, count 0 2006.257.12:38:50.27#ibcon#end of sib2, iclass 26, count 0 2006.257.12:38:50.27#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:38:50.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:38:50.28#ibcon#[27=USB\r\n] 2006.257.12:38:50.28#ibcon#*before write, iclass 26, count 0 2006.257.12:38:50.28#ibcon#enter sib2, iclass 26, count 0 2006.257.12:38:50.28#ibcon#flushed, iclass 26, count 0 2006.257.12:38:50.28#ibcon#about to write, iclass 26, count 0 2006.257.12:38:50.28#ibcon#wrote, iclass 26, count 0 2006.257.12:38:50.28#ibcon#about to read 3, iclass 26, count 0 2006.257.12:38:50.30#ibcon#read 3, iclass 26, count 0 2006.257.12:38:50.30#ibcon#about to read 4, iclass 26, count 0 2006.257.12:38:50.30#ibcon#read 4, iclass 26, count 0 2006.257.12:38:50.30#ibcon#about to read 5, iclass 26, count 0 2006.257.12:38:50.30#ibcon#read 5, iclass 26, count 0 2006.257.12:38:50.30#ibcon#about to read 6, iclass 26, count 0 2006.257.12:38:50.30#ibcon#read 6, iclass 26, count 0 2006.257.12:38:50.30#ibcon#end of sib2, iclass 26, count 0 2006.257.12:38:50.30#ibcon#*after write, iclass 26, count 0 2006.257.12:38:50.30#ibcon#*before return 0, iclass 26, count 0 2006.257.12:38:50.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:50.31#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.12:38:50.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:38:50.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:38:50.31$vck44/vblo=8,744.99 2006.257.12:38:50.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.12:38:50.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.12:38:50.31#ibcon#ireg 17 cls_cnt 0 2006.257.12:38:50.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:50.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:50.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:50.31#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:38:50.31#ibcon#first serial, iclass 28, count 0 2006.257.12:38:50.31#ibcon#enter sib2, iclass 28, count 0 2006.257.12:38:50.31#ibcon#flushed, iclass 28, count 0 2006.257.12:38:50.31#ibcon#about to write, iclass 28, count 0 2006.257.12:38:50.31#ibcon#wrote, iclass 28, count 0 2006.257.12:38:50.31#ibcon#about to read 3, iclass 28, count 0 2006.257.12:38:50.32#ibcon#read 3, iclass 28, count 0 2006.257.12:38:50.32#ibcon#about to read 4, iclass 28, count 0 2006.257.12:38:50.32#ibcon#read 4, iclass 28, count 0 2006.257.12:38:50.32#ibcon#about to read 5, iclass 28, count 0 2006.257.12:38:50.32#ibcon#read 5, iclass 28, count 0 2006.257.12:38:50.32#ibcon#about to read 6, iclass 28, count 0 2006.257.12:38:50.32#ibcon#read 6, iclass 28, count 0 2006.257.12:38:50.32#ibcon#end of sib2, iclass 28, count 0 2006.257.12:38:50.32#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:38:50.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:38:50.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:38:50.32#ibcon#*before write, iclass 28, count 0 2006.257.12:38:50.32#ibcon#enter sib2, iclass 28, count 0 2006.257.12:38:50.32#ibcon#flushed, iclass 28, count 0 2006.257.12:38:50.33#ibcon#about to write, iclass 28, count 0 2006.257.12:38:50.33#ibcon#wrote, iclass 28, count 0 2006.257.12:38:50.33#ibcon#about to read 3, iclass 28, count 0 2006.257.12:38:50.36#ibcon#read 3, iclass 28, count 0 2006.257.12:38:50.36#ibcon#about to read 4, iclass 28, count 0 2006.257.12:38:50.36#ibcon#read 4, iclass 28, count 0 2006.257.12:38:50.36#ibcon#about to read 5, iclass 28, count 0 2006.257.12:38:50.36#ibcon#read 5, iclass 28, count 0 2006.257.12:38:50.36#ibcon#about to read 6, iclass 28, count 0 2006.257.12:38:50.36#ibcon#read 6, iclass 28, count 0 2006.257.12:38:50.36#ibcon#end of sib2, iclass 28, count 0 2006.257.12:38:50.36#ibcon#*after write, iclass 28, count 0 2006.257.12:38:50.36#ibcon#*before return 0, iclass 28, count 0 2006.257.12:38:50.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:50.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.12:38:50.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:38:50.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:38:50.37$vck44/vb=8,4 2006.257.12:38:50.37#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.12:38:50.37#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.12:38:50.37#ibcon#ireg 11 cls_cnt 2 2006.257.12:38:50.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:50.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:50.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:50.42#ibcon#enter wrdev, iclass 30, count 2 2006.257.12:38:50.42#ibcon#first serial, iclass 30, count 2 2006.257.12:38:50.42#ibcon#enter sib2, iclass 30, count 2 2006.257.12:38:50.42#ibcon#flushed, iclass 30, count 2 2006.257.12:38:50.42#ibcon#about to write, iclass 30, count 2 2006.257.12:38:50.42#ibcon#wrote, iclass 30, count 2 2006.257.12:38:50.42#ibcon#about to read 3, iclass 30, count 2 2006.257.12:38:50.44#ibcon#read 3, iclass 30, count 2 2006.257.12:38:50.44#ibcon#about to read 4, iclass 30, count 2 2006.257.12:38:50.44#ibcon#read 4, iclass 30, count 2 2006.257.12:38:50.44#ibcon#about to read 5, iclass 30, count 2 2006.257.12:38:50.44#ibcon#read 5, iclass 30, count 2 2006.257.12:38:50.44#ibcon#about to read 6, iclass 30, count 2 2006.257.12:38:50.44#ibcon#read 6, iclass 30, count 2 2006.257.12:38:50.44#ibcon#end of sib2, iclass 30, count 2 2006.257.12:38:50.44#ibcon#*mode == 0, iclass 30, count 2 2006.257.12:38:50.44#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.12:38:50.44#ibcon#[27=AT08-04\r\n] 2006.257.12:38:50.44#ibcon#*before write, iclass 30, count 2 2006.257.12:38:50.44#ibcon#enter sib2, iclass 30, count 2 2006.257.12:38:50.44#ibcon#flushed, iclass 30, count 2 2006.257.12:38:50.45#ibcon#about to write, iclass 30, count 2 2006.257.12:38:50.45#ibcon#wrote, iclass 30, count 2 2006.257.12:38:50.45#ibcon#about to read 3, iclass 30, count 2 2006.257.12:38:50.47#ibcon#read 3, iclass 30, count 2 2006.257.12:38:50.51#ibcon#about to read 4, iclass 30, count 2 2006.257.12:38:50.52#ibcon#read 4, iclass 30, count 2 2006.257.12:38:50.52#ibcon#about to read 5, iclass 30, count 2 2006.257.12:38:50.52#ibcon#read 5, iclass 30, count 2 2006.257.12:38:50.52#ibcon#about to read 6, iclass 30, count 2 2006.257.12:38:50.52#ibcon#read 6, iclass 30, count 2 2006.257.12:38:50.52#ibcon#end of sib2, iclass 30, count 2 2006.257.12:38:50.52#ibcon#*after write, iclass 30, count 2 2006.257.12:38:50.52#ibcon#*before return 0, iclass 30, count 2 2006.257.12:38:50.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:50.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.12:38:50.52#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.12:38:50.52#ibcon#ireg 7 cls_cnt 0 2006.257.12:38:50.52#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:50.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:50.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:50.63#ibcon#enter wrdev, iclass 30, count 0 2006.257.12:38:50.63#ibcon#first serial, iclass 30, count 0 2006.257.12:38:50.63#ibcon#enter sib2, iclass 30, count 0 2006.257.12:38:50.63#ibcon#flushed, iclass 30, count 0 2006.257.12:38:50.63#ibcon#about to write, iclass 30, count 0 2006.257.12:38:50.63#ibcon#wrote, iclass 30, count 0 2006.257.12:38:50.63#ibcon#about to read 3, iclass 30, count 0 2006.257.12:38:50.65#ibcon#read 3, iclass 30, count 0 2006.257.12:38:50.65#ibcon#about to read 4, iclass 30, count 0 2006.257.12:38:50.65#ibcon#read 4, iclass 30, count 0 2006.257.12:38:50.65#ibcon#about to read 5, iclass 30, count 0 2006.257.12:38:50.65#ibcon#read 5, iclass 30, count 0 2006.257.12:38:50.65#ibcon#about to read 6, iclass 30, count 0 2006.257.12:38:50.65#ibcon#read 6, iclass 30, count 0 2006.257.12:38:50.65#ibcon#end of sib2, iclass 30, count 0 2006.257.12:38:50.65#ibcon#*mode == 0, iclass 30, count 0 2006.257.12:38:50.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.12:38:50.65#ibcon#[27=USB\r\n] 2006.257.12:38:50.65#ibcon#*before write, iclass 30, count 0 2006.257.12:38:50.66#ibcon#enter sib2, iclass 30, count 0 2006.257.12:38:50.66#ibcon#flushed, iclass 30, count 0 2006.257.12:38:50.66#ibcon#about to write, iclass 30, count 0 2006.257.12:38:50.66#ibcon#wrote, iclass 30, count 0 2006.257.12:38:50.66#ibcon#about to read 3, iclass 30, count 0 2006.257.12:38:50.68#ibcon#read 3, iclass 30, count 0 2006.257.12:38:50.68#ibcon#about to read 4, iclass 30, count 0 2006.257.12:38:50.68#ibcon#read 4, iclass 30, count 0 2006.257.12:38:50.68#ibcon#about to read 5, iclass 30, count 0 2006.257.12:38:50.68#ibcon#read 5, iclass 30, count 0 2006.257.12:38:50.68#ibcon#about to read 6, iclass 30, count 0 2006.257.12:38:50.68#ibcon#read 6, iclass 30, count 0 2006.257.12:38:50.68#ibcon#end of sib2, iclass 30, count 0 2006.257.12:38:50.68#ibcon#*after write, iclass 30, count 0 2006.257.12:38:50.68#ibcon#*before return 0, iclass 30, count 0 2006.257.12:38:50.69#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:50.69#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.12:38:50.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.12:38:50.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.12:38:50.69$vck44/vabw=wide 2006.257.12:38:50.69#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.12:38:50.69#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.12:38:50.69#ibcon#ireg 8 cls_cnt 0 2006.257.12:38:50.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:50.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:50.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:50.69#ibcon#enter wrdev, iclass 32, count 0 2006.257.12:38:50.69#ibcon#first serial, iclass 32, count 0 2006.257.12:38:50.69#ibcon#enter sib2, iclass 32, count 0 2006.257.12:38:50.69#ibcon#flushed, iclass 32, count 0 2006.257.12:38:50.69#ibcon#about to write, iclass 32, count 0 2006.257.12:38:50.69#ibcon#wrote, iclass 32, count 0 2006.257.12:38:50.69#ibcon#about to read 3, iclass 32, count 0 2006.257.12:38:50.70#ibcon#read 3, iclass 32, count 0 2006.257.12:38:50.70#ibcon#about to read 4, iclass 32, count 0 2006.257.12:38:50.70#ibcon#read 4, iclass 32, count 0 2006.257.12:38:50.70#ibcon#about to read 5, iclass 32, count 0 2006.257.12:38:50.70#ibcon#read 5, iclass 32, count 0 2006.257.12:38:50.70#ibcon#about to read 6, iclass 32, count 0 2006.257.12:38:50.70#ibcon#read 6, iclass 32, count 0 2006.257.12:38:50.70#ibcon#end of sib2, iclass 32, count 0 2006.257.12:38:50.70#ibcon#*mode == 0, iclass 32, count 0 2006.257.12:38:50.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.12:38:50.71#ibcon#[25=BW32\r\n] 2006.257.12:38:50.71#ibcon#*before write, iclass 32, count 0 2006.257.12:38:50.71#ibcon#enter sib2, iclass 32, count 0 2006.257.12:38:50.71#ibcon#flushed, iclass 32, count 0 2006.257.12:38:50.71#ibcon#about to write, iclass 32, count 0 2006.257.12:38:50.71#ibcon#wrote, iclass 32, count 0 2006.257.12:38:50.71#ibcon#about to read 3, iclass 32, count 0 2006.257.12:38:50.73#ibcon#read 3, iclass 32, count 0 2006.257.12:38:50.73#ibcon#about to read 4, iclass 32, count 0 2006.257.12:38:50.73#ibcon#read 4, iclass 32, count 0 2006.257.12:38:50.73#ibcon#about to read 5, iclass 32, count 0 2006.257.12:38:50.73#ibcon#read 5, iclass 32, count 0 2006.257.12:38:50.73#ibcon#about to read 6, iclass 32, count 0 2006.257.12:38:50.73#ibcon#read 6, iclass 32, count 0 2006.257.12:38:50.73#ibcon#end of sib2, iclass 32, count 0 2006.257.12:38:50.73#ibcon#*after write, iclass 32, count 0 2006.257.12:38:50.73#ibcon#*before return 0, iclass 32, count 0 2006.257.12:38:50.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:50.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.12:38:50.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.12:38:50.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.12:38:50.74$vck44/vbbw=wide 2006.257.12:38:50.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.12:38:50.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.12:38:50.74#ibcon#ireg 8 cls_cnt 0 2006.257.12:38:50.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:38:50.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:38:50.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:38:50.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:38:50.80#ibcon#first serial, iclass 34, count 0 2006.257.12:38:50.80#ibcon#enter sib2, iclass 34, count 0 2006.257.12:38:50.80#ibcon#flushed, iclass 34, count 0 2006.257.12:38:50.80#ibcon#about to write, iclass 34, count 0 2006.257.12:38:50.80#ibcon#wrote, iclass 34, count 0 2006.257.12:38:50.80#ibcon#about to read 3, iclass 34, count 0 2006.257.12:38:50.82#ibcon#read 3, iclass 34, count 0 2006.257.12:38:50.82#ibcon#about to read 4, iclass 34, count 0 2006.257.12:38:50.82#ibcon#read 4, iclass 34, count 0 2006.257.12:38:50.82#ibcon#about to read 5, iclass 34, count 0 2006.257.12:38:50.82#ibcon#read 5, iclass 34, count 0 2006.257.12:38:50.82#ibcon#about to read 6, iclass 34, count 0 2006.257.12:38:50.82#ibcon#read 6, iclass 34, count 0 2006.257.12:38:50.82#ibcon#end of sib2, iclass 34, count 0 2006.257.12:38:50.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:38:50.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:38:50.82#ibcon#[27=BW32\r\n] 2006.257.12:38:50.83#ibcon#*before write, iclass 34, count 0 2006.257.12:38:50.83#ibcon#enter sib2, iclass 34, count 0 2006.257.12:38:50.83#ibcon#flushed, iclass 34, count 0 2006.257.12:38:50.83#ibcon#about to write, iclass 34, count 0 2006.257.12:38:50.83#ibcon#wrote, iclass 34, count 0 2006.257.12:38:50.83#ibcon#about to read 3, iclass 34, count 0 2006.257.12:38:50.85#ibcon#read 3, iclass 34, count 0 2006.257.12:38:50.85#ibcon#about to read 4, iclass 34, count 0 2006.257.12:38:50.85#ibcon#read 4, iclass 34, count 0 2006.257.12:38:50.85#ibcon#about to read 5, iclass 34, count 0 2006.257.12:38:50.85#ibcon#read 5, iclass 34, count 0 2006.257.12:38:50.85#ibcon#about to read 6, iclass 34, count 0 2006.257.12:38:50.85#ibcon#read 6, iclass 34, count 0 2006.257.12:38:50.85#ibcon#end of sib2, iclass 34, count 0 2006.257.12:38:50.85#ibcon#*after write, iclass 34, count 0 2006.257.12:38:50.85#ibcon#*before return 0, iclass 34, count 0 2006.257.12:38:50.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:38:50.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:38:50.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:38:50.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:38:50.86$setupk4/ifdk4 2006.257.12:38:50.86$ifdk4/lo= 2006.257.12:38:50.86$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:38:50.86$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:38:50.86$ifdk4/patch= 2006.257.12:38:50.86$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:38:50.86$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:38:50.86$setupk4/!*+20s 2006.257.12:38:51.05#abcon#<5=/14 1.7 4.2 17.90 961013.9\r\n> 2006.257.12:38:51.07#abcon#{5=INTERFACE CLEAR} 2006.257.12:38:51.13#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:39:01.22#abcon#<5=/14 1.7 4.2 17.90 961013.9\r\n> 2006.257.12:39:01.24#abcon#{5=INTERFACE CLEAR} 2006.257.12:39:01.30#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:39:03.13#trakl#Source acquired 2006.257.12:39:04.14#flagr#flagr/antenna,acquired 2006.257.12:39:05.25$setupk4/"tpicd 2006.257.12:39:05.25$setupk4/echo=off 2006.257.12:39:05.26$setupk4/xlog=off 2006.257.12:39:05.26:!2006.257.12:43:51 2006.257.12:43:51.01:preob 2006.257.12:43:52.14/onsource/TRACKING 2006.257.12:43:52.14:!2006.257.12:44:01 2006.257.12:44:01.00:"tape 2006.257.12:44:01.00:"st=record 2006.257.12:44:01.00:data_valid=on 2006.257.12:44:01.00:midob 2006.257.12:44:01.14/onsource/TRACKING 2006.257.12:44:01.14/wx/17.87,1013.9,96 2006.257.12:44:01.28/cable/+6.4800E-03 2006.257.12:44:02.37/va/01,08,usb,yes,30,33 2006.257.12:44:02.37/va/02,07,usb,yes,33,33 2006.257.12:44:02.37/va/03,08,usb,yes,30,31 2006.257.12:44:02.37/va/04,07,usb,yes,34,36 2006.257.12:44:02.37/va/05,04,usb,yes,30,31 2006.257.12:44:02.37/va/06,04,usb,yes,34,34 2006.257.12:44:02.37/va/07,04,usb,yes,35,35 2006.257.12:44:02.37/va/08,04,usb,yes,29,36 2006.257.12:44:02.60/valo/01,524.99,yes,locked 2006.257.12:44:02.60/valo/02,534.99,yes,locked 2006.257.12:44:02.60/valo/03,564.99,yes,locked 2006.257.12:44:02.60/valo/04,624.99,yes,locked 2006.257.12:44:02.60/valo/05,734.99,yes,locked 2006.257.12:44:02.60/valo/06,814.99,yes,locked 2006.257.12:44:02.60/valo/07,864.99,yes,locked 2006.257.12:44:02.60/valo/08,884.99,yes,locked 2006.257.12:44:03.69/vb/01,04,usb,yes,31,28 2006.257.12:44:03.69/vb/02,05,usb,yes,29,29 2006.257.12:44:03.69/vb/03,04,usb,yes,30,33 2006.257.12:44:03.69/vb/04,05,usb,yes,30,29 2006.257.12:44:03.69/vb/05,04,usb,yes,26,29 2006.257.12:44:03.69/vb/06,04,usb,yes,31,27 2006.257.12:44:03.69/vb/07,04,usb,yes,31,31 2006.257.12:44:03.69/vb/08,04,usb,yes,28,32 2006.257.12:44:03.93/vblo/01,629.99,yes,locked 2006.257.12:44:03.93/vblo/02,634.99,yes,locked 2006.257.12:44:03.93/vblo/03,649.99,yes,locked 2006.257.12:44:03.93/vblo/04,679.99,yes,locked 2006.257.12:44:03.93/vblo/05,709.99,yes,locked 2006.257.12:44:03.93/vblo/06,719.99,yes,locked 2006.257.12:44:03.93/vblo/07,734.99,yes,locked 2006.257.12:44:03.93/vblo/08,744.99,yes,locked 2006.257.12:44:04.08/vabw/8 2006.257.12:44:04.23/vbbw/8 2006.257.12:44:04.43/xfe/off,on,15.2 2006.257.12:44:04.81/ifatt/23,28,28,28 2006.257.12:44:05.07/fmout-gps/S +4.56E-07 2006.257.12:44:05.11:!2006.257.12:46:41 2006.257.12:46:41.01:data_valid=off 2006.257.12:46:41.02:"et 2006.257.12:46:41.02:!+3s 2006.257.12:46:44.03:"tape 2006.257.12:46:44.04:postob 2006.257.12:46:44.19/cable/+6.4791E-03 2006.257.12:46:44.20/wx/17.86,1013.9,96 2006.257.12:46:44.25/fmout-gps/S +4.58E-07 2006.257.12:46:44.26:scan_name=257-1249,jd0609,40 2006.257.12:46:44.26:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.12:46:45.13#flagr#flagr/antenna,new-source 2006.257.12:46:45.14:checkk5 2006.257.12:46:45.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:46:45.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:46:46.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:46:46.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:46:47.18/chk_obsdata//k5ts1/T2571244??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:46:47.61/chk_obsdata//k5ts2/T2571244??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:46:48.02/chk_obsdata//k5ts3/T2571244??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:46:48.43/chk_obsdata//k5ts4/T2571244??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.12:46:49.15/k5log//k5ts1_log_newline 2006.257.12:46:49.86/k5log//k5ts2_log_newline 2006.257.12:46:50.57/k5log//k5ts3_log_newline 2006.257.12:46:51.28/k5log//k5ts4_log_newline 2006.257.12:46:51.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:46:51.31:setupk4=1 2006.257.12:46:51.31$setupk4/echo=on 2006.257.12:46:51.31$setupk4/pcalon 2006.257.12:46:51.31$pcalon/"no phase cal control is implemented here 2006.257.12:46:51.31$setupk4/"tpicd=stop 2006.257.12:46:51.31$setupk4/"rec=synch_on 2006.257.12:46:51.31$setupk4/"rec_mode=128 2006.257.12:46:51.31$setupk4/!* 2006.257.12:46:51.31$setupk4/recpk4 2006.257.12:46:51.31$recpk4/recpatch= 2006.257.12:46:51.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:46:51.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:46:51.31$setupk4/vck44 2006.257.12:46:51.31$vck44/valo=1,524.99 2006.257.12:46:51.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.12:46:51.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.12:46:51.31#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:51.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:51.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:51.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:51.31#ibcon#enter wrdev, iclass 15, count 0 2006.257.12:46:51.31#ibcon#first serial, iclass 15, count 0 2006.257.12:46:51.31#ibcon#enter sib2, iclass 15, count 0 2006.257.12:46:51.31#ibcon#flushed, iclass 15, count 0 2006.257.12:46:51.31#ibcon#about to write, iclass 15, count 0 2006.257.12:46:51.31#ibcon#wrote, iclass 15, count 0 2006.257.12:46:51.31#ibcon#about to read 3, iclass 15, count 0 2006.257.12:46:51.33#ibcon#read 3, iclass 15, count 0 2006.257.12:46:51.33#ibcon#about to read 4, iclass 15, count 0 2006.257.12:46:51.33#ibcon#read 4, iclass 15, count 0 2006.257.12:46:51.33#ibcon#about to read 5, iclass 15, count 0 2006.257.12:46:51.33#ibcon#read 5, iclass 15, count 0 2006.257.12:46:51.33#ibcon#about to read 6, iclass 15, count 0 2006.257.12:46:51.33#ibcon#read 6, iclass 15, count 0 2006.257.12:46:51.33#ibcon#end of sib2, iclass 15, count 0 2006.257.12:46:51.33#ibcon#*mode == 0, iclass 15, count 0 2006.257.12:46:51.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.12:46:51.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:46:51.33#ibcon#*before write, iclass 15, count 0 2006.257.12:46:51.33#ibcon#enter sib2, iclass 15, count 0 2006.257.12:46:51.33#ibcon#flushed, iclass 15, count 0 2006.257.12:46:51.33#ibcon#about to write, iclass 15, count 0 2006.257.12:46:51.33#ibcon#wrote, iclass 15, count 0 2006.257.12:46:51.33#ibcon#about to read 3, iclass 15, count 0 2006.257.12:46:51.38#ibcon#read 3, iclass 15, count 0 2006.257.12:46:51.38#ibcon#about to read 4, iclass 15, count 0 2006.257.12:46:51.38#ibcon#read 4, iclass 15, count 0 2006.257.12:46:51.38#ibcon#about to read 5, iclass 15, count 0 2006.257.12:46:51.38#ibcon#read 5, iclass 15, count 0 2006.257.12:46:51.38#ibcon#about to read 6, iclass 15, count 0 2006.257.12:46:51.38#ibcon#read 6, iclass 15, count 0 2006.257.12:46:51.38#ibcon#end of sib2, iclass 15, count 0 2006.257.12:46:51.38#ibcon#*after write, iclass 15, count 0 2006.257.12:46:51.38#ibcon#*before return 0, iclass 15, count 0 2006.257.12:46:51.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:51.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:51.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.12:46:51.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.12:46:51.38$vck44/va=1,8 2006.257.12:46:51.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.12:46:51.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.12:46:51.38#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:51.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:51.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:51.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:51.38#ibcon#enter wrdev, iclass 17, count 2 2006.257.12:46:51.38#ibcon#first serial, iclass 17, count 2 2006.257.12:46:51.38#ibcon#enter sib2, iclass 17, count 2 2006.257.12:46:51.38#ibcon#flushed, iclass 17, count 2 2006.257.12:46:51.38#ibcon#about to write, iclass 17, count 2 2006.257.12:46:51.38#ibcon#wrote, iclass 17, count 2 2006.257.12:46:51.38#ibcon#about to read 3, iclass 17, count 2 2006.257.12:46:51.40#ibcon#read 3, iclass 17, count 2 2006.257.12:46:51.40#ibcon#about to read 4, iclass 17, count 2 2006.257.12:46:51.40#ibcon#read 4, iclass 17, count 2 2006.257.12:46:51.40#ibcon#about to read 5, iclass 17, count 2 2006.257.12:46:51.40#ibcon#read 5, iclass 17, count 2 2006.257.12:46:51.40#ibcon#about to read 6, iclass 17, count 2 2006.257.12:46:51.40#ibcon#read 6, iclass 17, count 2 2006.257.12:46:51.40#ibcon#end of sib2, iclass 17, count 2 2006.257.12:46:51.40#ibcon#*mode == 0, iclass 17, count 2 2006.257.12:46:51.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.12:46:51.40#ibcon#[25=AT01-08\r\n] 2006.257.12:46:51.40#ibcon#*before write, iclass 17, count 2 2006.257.12:46:51.40#ibcon#enter sib2, iclass 17, count 2 2006.257.12:46:51.40#ibcon#flushed, iclass 17, count 2 2006.257.12:46:51.40#ibcon#about to write, iclass 17, count 2 2006.257.12:46:51.40#ibcon#wrote, iclass 17, count 2 2006.257.12:46:51.40#ibcon#about to read 3, iclass 17, count 2 2006.257.12:46:51.43#ibcon#read 3, iclass 17, count 2 2006.257.12:46:51.43#ibcon#about to read 4, iclass 17, count 2 2006.257.12:46:51.43#ibcon#read 4, iclass 17, count 2 2006.257.12:46:51.43#ibcon#about to read 5, iclass 17, count 2 2006.257.12:46:51.43#ibcon#read 5, iclass 17, count 2 2006.257.12:46:51.43#ibcon#about to read 6, iclass 17, count 2 2006.257.12:46:51.43#ibcon#read 6, iclass 17, count 2 2006.257.12:46:51.43#ibcon#end of sib2, iclass 17, count 2 2006.257.12:46:51.43#ibcon#*after write, iclass 17, count 2 2006.257.12:46:51.43#ibcon#*before return 0, iclass 17, count 2 2006.257.12:46:51.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:51.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:51.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.12:46:51.43#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:51.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:51.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:51.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:51.55#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:46:51.55#ibcon#first serial, iclass 17, count 0 2006.257.12:46:51.55#ibcon#enter sib2, iclass 17, count 0 2006.257.12:46:51.55#ibcon#flushed, iclass 17, count 0 2006.257.12:46:51.55#ibcon#about to write, iclass 17, count 0 2006.257.12:46:51.55#ibcon#wrote, iclass 17, count 0 2006.257.12:46:51.55#ibcon#about to read 3, iclass 17, count 0 2006.257.12:46:51.57#ibcon#read 3, iclass 17, count 0 2006.257.12:46:51.57#ibcon#about to read 4, iclass 17, count 0 2006.257.12:46:51.57#ibcon#read 4, iclass 17, count 0 2006.257.12:46:51.57#ibcon#about to read 5, iclass 17, count 0 2006.257.12:46:51.57#ibcon#read 5, iclass 17, count 0 2006.257.12:46:51.57#ibcon#about to read 6, iclass 17, count 0 2006.257.12:46:51.57#ibcon#read 6, iclass 17, count 0 2006.257.12:46:51.57#ibcon#end of sib2, iclass 17, count 0 2006.257.12:46:51.57#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:46:51.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:46:51.57#ibcon#[25=USB\r\n] 2006.257.12:46:51.57#ibcon#*before write, iclass 17, count 0 2006.257.12:46:51.57#ibcon#enter sib2, iclass 17, count 0 2006.257.12:46:51.57#ibcon#flushed, iclass 17, count 0 2006.257.12:46:51.57#ibcon#about to write, iclass 17, count 0 2006.257.12:46:51.57#ibcon#wrote, iclass 17, count 0 2006.257.12:46:51.57#ibcon#about to read 3, iclass 17, count 0 2006.257.12:46:51.60#ibcon#read 3, iclass 17, count 0 2006.257.12:46:51.60#ibcon#about to read 4, iclass 17, count 0 2006.257.12:46:51.60#ibcon#read 4, iclass 17, count 0 2006.257.12:46:51.60#ibcon#about to read 5, iclass 17, count 0 2006.257.12:46:51.60#ibcon#read 5, iclass 17, count 0 2006.257.12:46:51.60#ibcon#about to read 6, iclass 17, count 0 2006.257.12:46:51.60#ibcon#read 6, iclass 17, count 0 2006.257.12:46:51.60#ibcon#end of sib2, iclass 17, count 0 2006.257.12:46:51.60#ibcon#*after write, iclass 17, count 0 2006.257.12:46:51.60#ibcon#*before return 0, iclass 17, count 0 2006.257.12:46:51.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:51.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:51.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:46:51.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:46:51.60$vck44/valo=2,534.99 2006.257.12:46:51.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.12:46:51.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.12:46:51.60#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:51.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:51.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:51.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:51.60#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:46:51.60#ibcon#first serial, iclass 19, count 0 2006.257.12:46:51.60#ibcon#enter sib2, iclass 19, count 0 2006.257.12:46:51.60#ibcon#flushed, iclass 19, count 0 2006.257.12:46:51.60#ibcon#about to write, iclass 19, count 0 2006.257.12:46:51.60#ibcon#wrote, iclass 19, count 0 2006.257.12:46:51.60#ibcon#about to read 3, iclass 19, count 0 2006.257.12:46:51.62#ibcon#read 3, iclass 19, count 0 2006.257.12:46:51.62#ibcon#about to read 4, iclass 19, count 0 2006.257.12:46:51.62#ibcon#read 4, iclass 19, count 0 2006.257.12:46:51.62#ibcon#about to read 5, iclass 19, count 0 2006.257.12:46:51.62#ibcon#read 5, iclass 19, count 0 2006.257.12:46:51.62#ibcon#about to read 6, iclass 19, count 0 2006.257.12:46:51.62#ibcon#read 6, iclass 19, count 0 2006.257.12:46:51.62#ibcon#end of sib2, iclass 19, count 0 2006.257.12:46:51.62#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:46:51.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:46:51.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:46:51.62#ibcon#*before write, iclass 19, count 0 2006.257.12:46:51.62#ibcon#enter sib2, iclass 19, count 0 2006.257.12:46:51.62#ibcon#flushed, iclass 19, count 0 2006.257.12:46:51.62#ibcon#about to write, iclass 19, count 0 2006.257.12:46:51.62#ibcon#wrote, iclass 19, count 0 2006.257.12:46:51.62#ibcon#about to read 3, iclass 19, count 0 2006.257.12:46:51.66#ibcon#read 3, iclass 19, count 0 2006.257.12:46:51.66#ibcon#about to read 4, iclass 19, count 0 2006.257.12:46:51.66#ibcon#read 4, iclass 19, count 0 2006.257.12:46:51.66#ibcon#about to read 5, iclass 19, count 0 2006.257.12:46:51.66#ibcon#read 5, iclass 19, count 0 2006.257.12:46:51.66#ibcon#about to read 6, iclass 19, count 0 2006.257.12:46:51.66#ibcon#read 6, iclass 19, count 0 2006.257.12:46:51.66#ibcon#end of sib2, iclass 19, count 0 2006.257.12:46:51.66#ibcon#*after write, iclass 19, count 0 2006.257.12:46:51.66#ibcon#*before return 0, iclass 19, count 0 2006.257.12:46:51.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:51.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:51.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:46:51.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:46:51.66$vck44/va=2,7 2006.257.12:46:51.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.12:46:51.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.12:46:51.66#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:51.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:51.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:51.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:51.72#ibcon#enter wrdev, iclass 21, count 2 2006.257.12:46:51.72#ibcon#first serial, iclass 21, count 2 2006.257.12:46:51.72#ibcon#enter sib2, iclass 21, count 2 2006.257.12:46:51.72#ibcon#flushed, iclass 21, count 2 2006.257.12:46:51.72#ibcon#about to write, iclass 21, count 2 2006.257.12:46:51.72#ibcon#wrote, iclass 21, count 2 2006.257.12:46:51.72#ibcon#about to read 3, iclass 21, count 2 2006.257.12:46:51.74#ibcon#read 3, iclass 21, count 2 2006.257.12:46:51.74#ibcon#about to read 4, iclass 21, count 2 2006.257.12:46:51.74#ibcon#read 4, iclass 21, count 2 2006.257.12:46:51.74#ibcon#about to read 5, iclass 21, count 2 2006.257.12:46:51.74#ibcon#read 5, iclass 21, count 2 2006.257.12:46:51.74#ibcon#about to read 6, iclass 21, count 2 2006.257.12:46:51.74#ibcon#read 6, iclass 21, count 2 2006.257.12:46:51.74#ibcon#end of sib2, iclass 21, count 2 2006.257.12:46:51.74#ibcon#*mode == 0, iclass 21, count 2 2006.257.12:46:51.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.12:46:51.74#ibcon#[25=AT02-07\r\n] 2006.257.12:46:51.74#ibcon#*before write, iclass 21, count 2 2006.257.12:46:51.74#ibcon#enter sib2, iclass 21, count 2 2006.257.12:46:51.74#ibcon#flushed, iclass 21, count 2 2006.257.12:46:51.74#ibcon#about to write, iclass 21, count 2 2006.257.12:46:51.74#ibcon#wrote, iclass 21, count 2 2006.257.12:46:51.74#ibcon#about to read 3, iclass 21, count 2 2006.257.12:46:51.77#ibcon#read 3, iclass 21, count 2 2006.257.12:46:51.77#ibcon#about to read 4, iclass 21, count 2 2006.257.12:46:51.77#ibcon#read 4, iclass 21, count 2 2006.257.12:46:51.77#ibcon#about to read 5, iclass 21, count 2 2006.257.12:46:51.77#ibcon#read 5, iclass 21, count 2 2006.257.12:46:51.77#ibcon#about to read 6, iclass 21, count 2 2006.257.12:46:51.77#ibcon#read 6, iclass 21, count 2 2006.257.12:46:51.77#ibcon#end of sib2, iclass 21, count 2 2006.257.12:46:51.77#ibcon#*after write, iclass 21, count 2 2006.257.12:46:51.77#ibcon#*before return 0, iclass 21, count 2 2006.257.12:46:51.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:51.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:51.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.12:46:51.77#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:51.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:51.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:51.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:51.89#ibcon#enter wrdev, iclass 21, count 0 2006.257.12:46:51.89#ibcon#first serial, iclass 21, count 0 2006.257.12:46:51.89#ibcon#enter sib2, iclass 21, count 0 2006.257.12:46:51.89#ibcon#flushed, iclass 21, count 0 2006.257.12:46:51.89#ibcon#about to write, iclass 21, count 0 2006.257.12:46:51.89#ibcon#wrote, iclass 21, count 0 2006.257.12:46:51.89#ibcon#about to read 3, iclass 21, count 0 2006.257.12:46:51.91#ibcon#read 3, iclass 21, count 0 2006.257.12:46:51.91#ibcon#about to read 4, iclass 21, count 0 2006.257.12:46:51.91#ibcon#read 4, iclass 21, count 0 2006.257.12:46:51.91#ibcon#about to read 5, iclass 21, count 0 2006.257.12:46:51.91#ibcon#read 5, iclass 21, count 0 2006.257.12:46:51.91#ibcon#about to read 6, iclass 21, count 0 2006.257.12:46:51.91#ibcon#read 6, iclass 21, count 0 2006.257.12:46:51.91#ibcon#end of sib2, iclass 21, count 0 2006.257.12:46:51.91#ibcon#*mode == 0, iclass 21, count 0 2006.257.12:46:51.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.12:46:51.91#ibcon#[25=USB\r\n] 2006.257.12:46:51.91#ibcon#*before write, iclass 21, count 0 2006.257.12:46:51.91#ibcon#enter sib2, iclass 21, count 0 2006.257.12:46:51.91#ibcon#flushed, iclass 21, count 0 2006.257.12:46:51.91#ibcon#about to write, iclass 21, count 0 2006.257.12:46:51.91#ibcon#wrote, iclass 21, count 0 2006.257.12:46:51.91#ibcon#about to read 3, iclass 21, count 0 2006.257.12:46:51.94#ibcon#read 3, iclass 21, count 0 2006.257.12:46:51.94#ibcon#about to read 4, iclass 21, count 0 2006.257.12:46:51.94#ibcon#read 4, iclass 21, count 0 2006.257.12:46:51.94#ibcon#about to read 5, iclass 21, count 0 2006.257.12:46:51.94#ibcon#read 5, iclass 21, count 0 2006.257.12:46:51.94#ibcon#about to read 6, iclass 21, count 0 2006.257.12:46:51.94#ibcon#read 6, iclass 21, count 0 2006.257.12:46:51.94#ibcon#end of sib2, iclass 21, count 0 2006.257.12:46:51.94#ibcon#*after write, iclass 21, count 0 2006.257.12:46:51.94#ibcon#*before return 0, iclass 21, count 0 2006.257.12:46:51.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:51.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:51.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.12:46:51.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.12:46:51.94$vck44/valo=3,564.99 2006.257.12:46:51.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.12:46:51.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.12:46:51.94#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:51.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:51.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:51.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:51.94#ibcon#enter wrdev, iclass 23, count 0 2006.257.12:46:51.94#ibcon#first serial, iclass 23, count 0 2006.257.12:46:51.94#ibcon#enter sib2, iclass 23, count 0 2006.257.12:46:51.94#ibcon#flushed, iclass 23, count 0 2006.257.12:46:51.94#ibcon#about to write, iclass 23, count 0 2006.257.12:46:51.94#ibcon#wrote, iclass 23, count 0 2006.257.12:46:51.94#ibcon#about to read 3, iclass 23, count 0 2006.257.12:46:51.96#ibcon#read 3, iclass 23, count 0 2006.257.12:46:51.96#ibcon#about to read 4, iclass 23, count 0 2006.257.12:46:51.96#ibcon#read 4, iclass 23, count 0 2006.257.12:46:51.96#ibcon#about to read 5, iclass 23, count 0 2006.257.12:46:51.96#ibcon#read 5, iclass 23, count 0 2006.257.12:46:51.96#ibcon#about to read 6, iclass 23, count 0 2006.257.12:46:51.96#ibcon#read 6, iclass 23, count 0 2006.257.12:46:51.96#ibcon#end of sib2, iclass 23, count 0 2006.257.12:46:51.96#ibcon#*mode == 0, iclass 23, count 0 2006.257.12:46:51.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.12:46:51.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:46:51.96#ibcon#*before write, iclass 23, count 0 2006.257.12:46:51.96#ibcon#enter sib2, iclass 23, count 0 2006.257.12:46:51.96#ibcon#flushed, iclass 23, count 0 2006.257.12:46:51.96#ibcon#about to write, iclass 23, count 0 2006.257.12:46:51.96#ibcon#wrote, iclass 23, count 0 2006.257.12:46:51.96#ibcon#about to read 3, iclass 23, count 0 2006.257.12:46:52.00#ibcon#read 3, iclass 23, count 0 2006.257.12:46:52.00#ibcon#about to read 4, iclass 23, count 0 2006.257.12:46:52.00#ibcon#read 4, iclass 23, count 0 2006.257.12:46:52.00#ibcon#about to read 5, iclass 23, count 0 2006.257.12:46:52.00#ibcon#read 5, iclass 23, count 0 2006.257.12:46:52.00#ibcon#about to read 6, iclass 23, count 0 2006.257.12:46:52.00#ibcon#read 6, iclass 23, count 0 2006.257.12:46:52.00#ibcon#end of sib2, iclass 23, count 0 2006.257.12:46:52.00#ibcon#*after write, iclass 23, count 0 2006.257.12:46:52.00#ibcon#*before return 0, iclass 23, count 0 2006.257.12:46:52.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:52.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:52.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.12:46:52.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.12:46:52.00$vck44/va=3,8 2006.257.12:46:52.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.12:46:52.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.12:46:52.00#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:52.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:52.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:52.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:52.06#ibcon#enter wrdev, iclass 25, count 2 2006.257.12:46:52.06#ibcon#first serial, iclass 25, count 2 2006.257.12:46:52.06#ibcon#enter sib2, iclass 25, count 2 2006.257.12:46:52.06#ibcon#flushed, iclass 25, count 2 2006.257.12:46:52.06#ibcon#about to write, iclass 25, count 2 2006.257.12:46:52.06#ibcon#wrote, iclass 25, count 2 2006.257.12:46:52.06#ibcon#about to read 3, iclass 25, count 2 2006.257.12:46:52.08#ibcon#read 3, iclass 25, count 2 2006.257.12:46:52.08#ibcon#about to read 4, iclass 25, count 2 2006.257.12:46:52.08#ibcon#read 4, iclass 25, count 2 2006.257.12:46:52.08#ibcon#about to read 5, iclass 25, count 2 2006.257.12:46:52.08#ibcon#read 5, iclass 25, count 2 2006.257.12:46:52.08#ibcon#about to read 6, iclass 25, count 2 2006.257.12:46:52.08#ibcon#read 6, iclass 25, count 2 2006.257.12:46:52.08#ibcon#end of sib2, iclass 25, count 2 2006.257.12:46:52.08#ibcon#*mode == 0, iclass 25, count 2 2006.257.12:46:52.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.12:46:52.08#ibcon#[25=AT03-08\r\n] 2006.257.12:46:52.08#ibcon#*before write, iclass 25, count 2 2006.257.12:46:52.08#ibcon#enter sib2, iclass 25, count 2 2006.257.12:46:52.08#ibcon#flushed, iclass 25, count 2 2006.257.12:46:52.08#ibcon#about to write, iclass 25, count 2 2006.257.12:46:52.08#ibcon#wrote, iclass 25, count 2 2006.257.12:46:52.08#ibcon#about to read 3, iclass 25, count 2 2006.257.12:46:52.11#ibcon#read 3, iclass 25, count 2 2006.257.12:46:52.11#ibcon#about to read 4, iclass 25, count 2 2006.257.12:46:52.11#ibcon#read 4, iclass 25, count 2 2006.257.12:46:52.11#ibcon#about to read 5, iclass 25, count 2 2006.257.12:46:52.11#ibcon#read 5, iclass 25, count 2 2006.257.12:46:52.11#ibcon#about to read 6, iclass 25, count 2 2006.257.12:46:52.11#ibcon#read 6, iclass 25, count 2 2006.257.12:46:52.11#ibcon#end of sib2, iclass 25, count 2 2006.257.12:46:52.11#ibcon#*after write, iclass 25, count 2 2006.257.12:46:52.11#ibcon#*before return 0, iclass 25, count 2 2006.257.12:46:52.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:52.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:52.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.12:46:52.11#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:52.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:52.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:52.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:52.23#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:46:52.23#ibcon#first serial, iclass 25, count 0 2006.257.12:46:52.23#ibcon#enter sib2, iclass 25, count 0 2006.257.12:46:52.23#ibcon#flushed, iclass 25, count 0 2006.257.12:46:52.23#ibcon#about to write, iclass 25, count 0 2006.257.12:46:52.23#ibcon#wrote, iclass 25, count 0 2006.257.12:46:52.23#ibcon#about to read 3, iclass 25, count 0 2006.257.12:46:52.25#ibcon#read 3, iclass 25, count 0 2006.257.12:46:52.25#ibcon#about to read 4, iclass 25, count 0 2006.257.12:46:52.25#ibcon#read 4, iclass 25, count 0 2006.257.12:46:52.25#ibcon#about to read 5, iclass 25, count 0 2006.257.12:46:52.25#ibcon#read 5, iclass 25, count 0 2006.257.12:46:52.25#ibcon#about to read 6, iclass 25, count 0 2006.257.12:46:52.25#ibcon#read 6, iclass 25, count 0 2006.257.12:46:52.25#ibcon#end of sib2, iclass 25, count 0 2006.257.12:46:52.25#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:46:52.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:46:52.25#ibcon#[25=USB\r\n] 2006.257.12:46:52.25#ibcon#*before write, iclass 25, count 0 2006.257.12:46:52.25#ibcon#enter sib2, iclass 25, count 0 2006.257.12:46:52.25#ibcon#flushed, iclass 25, count 0 2006.257.12:46:52.25#ibcon#about to write, iclass 25, count 0 2006.257.12:46:52.25#ibcon#wrote, iclass 25, count 0 2006.257.12:46:52.25#ibcon#about to read 3, iclass 25, count 0 2006.257.12:46:52.28#ibcon#read 3, iclass 25, count 0 2006.257.12:46:52.28#ibcon#about to read 4, iclass 25, count 0 2006.257.12:46:52.28#ibcon#read 4, iclass 25, count 0 2006.257.12:46:52.28#ibcon#about to read 5, iclass 25, count 0 2006.257.12:46:52.28#ibcon#read 5, iclass 25, count 0 2006.257.12:46:52.28#ibcon#about to read 6, iclass 25, count 0 2006.257.12:46:52.28#ibcon#read 6, iclass 25, count 0 2006.257.12:46:52.28#ibcon#end of sib2, iclass 25, count 0 2006.257.12:46:52.28#ibcon#*after write, iclass 25, count 0 2006.257.12:46:52.28#ibcon#*before return 0, iclass 25, count 0 2006.257.12:46:52.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:52.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:52.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:46:52.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:46:52.28$vck44/valo=4,624.99 2006.257.12:46:52.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.12:46:52.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.12:46:52.28#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:52.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:52.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:52.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:52.28#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:46:52.28#ibcon#first serial, iclass 27, count 0 2006.257.12:46:52.28#ibcon#enter sib2, iclass 27, count 0 2006.257.12:46:52.28#ibcon#flushed, iclass 27, count 0 2006.257.12:46:52.28#ibcon#about to write, iclass 27, count 0 2006.257.12:46:52.28#ibcon#wrote, iclass 27, count 0 2006.257.12:46:52.28#ibcon#about to read 3, iclass 27, count 0 2006.257.12:46:52.30#ibcon#read 3, iclass 27, count 0 2006.257.12:46:52.30#ibcon#about to read 4, iclass 27, count 0 2006.257.12:46:52.30#ibcon#read 4, iclass 27, count 0 2006.257.12:46:52.30#ibcon#about to read 5, iclass 27, count 0 2006.257.12:46:52.30#ibcon#read 5, iclass 27, count 0 2006.257.12:46:52.30#ibcon#about to read 6, iclass 27, count 0 2006.257.12:46:52.30#ibcon#read 6, iclass 27, count 0 2006.257.12:46:52.30#ibcon#end of sib2, iclass 27, count 0 2006.257.12:46:52.30#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:46:52.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:46:52.30#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:46:52.30#ibcon#*before write, iclass 27, count 0 2006.257.12:46:52.30#ibcon#enter sib2, iclass 27, count 0 2006.257.12:46:52.30#ibcon#flushed, iclass 27, count 0 2006.257.12:46:52.30#ibcon#about to write, iclass 27, count 0 2006.257.12:46:52.30#ibcon#wrote, iclass 27, count 0 2006.257.12:46:52.30#ibcon#about to read 3, iclass 27, count 0 2006.257.12:46:52.34#ibcon#read 3, iclass 27, count 0 2006.257.12:46:52.34#ibcon#about to read 4, iclass 27, count 0 2006.257.12:46:52.34#ibcon#read 4, iclass 27, count 0 2006.257.12:46:52.34#ibcon#about to read 5, iclass 27, count 0 2006.257.12:46:52.34#ibcon#read 5, iclass 27, count 0 2006.257.12:46:52.34#ibcon#about to read 6, iclass 27, count 0 2006.257.12:46:52.34#ibcon#read 6, iclass 27, count 0 2006.257.12:46:52.34#ibcon#end of sib2, iclass 27, count 0 2006.257.12:46:52.34#ibcon#*after write, iclass 27, count 0 2006.257.12:46:52.34#ibcon#*before return 0, iclass 27, count 0 2006.257.12:46:52.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:52.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:52.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:46:52.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:46:52.34$vck44/va=4,7 2006.257.12:46:52.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.12:46:52.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.12:46:52.34#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:52.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:52.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:52.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:52.40#ibcon#enter wrdev, iclass 29, count 2 2006.257.12:46:52.40#ibcon#first serial, iclass 29, count 2 2006.257.12:46:52.40#ibcon#enter sib2, iclass 29, count 2 2006.257.12:46:52.40#ibcon#flushed, iclass 29, count 2 2006.257.12:46:52.40#ibcon#about to write, iclass 29, count 2 2006.257.12:46:52.40#ibcon#wrote, iclass 29, count 2 2006.257.12:46:52.40#ibcon#about to read 3, iclass 29, count 2 2006.257.12:46:52.42#ibcon#read 3, iclass 29, count 2 2006.257.12:46:52.42#ibcon#about to read 4, iclass 29, count 2 2006.257.12:46:52.42#ibcon#read 4, iclass 29, count 2 2006.257.12:46:52.42#ibcon#about to read 5, iclass 29, count 2 2006.257.12:46:52.42#ibcon#read 5, iclass 29, count 2 2006.257.12:46:52.42#ibcon#about to read 6, iclass 29, count 2 2006.257.12:46:52.42#ibcon#read 6, iclass 29, count 2 2006.257.12:46:52.42#ibcon#end of sib2, iclass 29, count 2 2006.257.12:46:52.42#ibcon#*mode == 0, iclass 29, count 2 2006.257.12:46:52.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.12:46:52.42#ibcon#[25=AT04-07\r\n] 2006.257.12:46:52.42#ibcon#*before write, iclass 29, count 2 2006.257.12:46:52.42#ibcon#enter sib2, iclass 29, count 2 2006.257.12:46:52.42#ibcon#flushed, iclass 29, count 2 2006.257.12:46:52.42#ibcon#about to write, iclass 29, count 2 2006.257.12:46:52.42#ibcon#wrote, iclass 29, count 2 2006.257.12:46:52.42#ibcon#about to read 3, iclass 29, count 2 2006.257.12:46:52.45#ibcon#read 3, iclass 29, count 2 2006.257.12:46:52.45#ibcon#about to read 4, iclass 29, count 2 2006.257.12:46:52.45#ibcon#read 4, iclass 29, count 2 2006.257.12:46:52.45#ibcon#about to read 5, iclass 29, count 2 2006.257.12:46:52.45#ibcon#read 5, iclass 29, count 2 2006.257.12:46:52.45#ibcon#about to read 6, iclass 29, count 2 2006.257.12:46:52.45#ibcon#read 6, iclass 29, count 2 2006.257.12:46:52.45#ibcon#end of sib2, iclass 29, count 2 2006.257.12:46:52.45#ibcon#*after write, iclass 29, count 2 2006.257.12:46:52.45#ibcon#*before return 0, iclass 29, count 2 2006.257.12:46:52.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:52.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:52.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.12:46:52.45#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:52.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:52.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:52.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:52.57#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:46:52.57#ibcon#first serial, iclass 29, count 0 2006.257.12:46:52.57#ibcon#enter sib2, iclass 29, count 0 2006.257.12:46:52.57#ibcon#flushed, iclass 29, count 0 2006.257.12:46:52.57#ibcon#about to write, iclass 29, count 0 2006.257.12:46:52.57#ibcon#wrote, iclass 29, count 0 2006.257.12:46:52.57#ibcon#about to read 3, iclass 29, count 0 2006.257.12:46:52.59#ibcon#read 3, iclass 29, count 0 2006.257.12:46:52.59#ibcon#about to read 4, iclass 29, count 0 2006.257.12:46:52.59#ibcon#read 4, iclass 29, count 0 2006.257.12:46:52.59#ibcon#about to read 5, iclass 29, count 0 2006.257.12:46:52.59#ibcon#read 5, iclass 29, count 0 2006.257.12:46:52.59#ibcon#about to read 6, iclass 29, count 0 2006.257.12:46:52.59#ibcon#read 6, iclass 29, count 0 2006.257.12:46:52.59#ibcon#end of sib2, iclass 29, count 0 2006.257.12:46:52.59#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:46:52.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:46:52.59#ibcon#[25=USB\r\n] 2006.257.12:46:52.59#ibcon#*before write, iclass 29, count 0 2006.257.12:46:52.59#ibcon#enter sib2, iclass 29, count 0 2006.257.12:46:52.59#ibcon#flushed, iclass 29, count 0 2006.257.12:46:52.59#ibcon#about to write, iclass 29, count 0 2006.257.12:46:52.59#ibcon#wrote, iclass 29, count 0 2006.257.12:46:52.59#ibcon#about to read 3, iclass 29, count 0 2006.257.12:46:52.62#ibcon#read 3, iclass 29, count 0 2006.257.12:46:52.62#ibcon#about to read 4, iclass 29, count 0 2006.257.12:46:52.62#ibcon#read 4, iclass 29, count 0 2006.257.12:46:52.62#ibcon#about to read 5, iclass 29, count 0 2006.257.12:46:52.62#ibcon#read 5, iclass 29, count 0 2006.257.12:46:52.62#ibcon#about to read 6, iclass 29, count 0 2006.257.12:46:52.62#ibcon#read 6, iclass 29, count 0 2006.257.12:46:52.62#ibcon#end of sib2, iclass 29, count 0 2006.257.12:46:52.62#ibcon#*after write, iclass 29, count 0 2006.257.12:46:52.62#ibcon#*before return 0, iclass 29, count 0 2006.257.12:46:52.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:52.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:52.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:46:52.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:46:52.62$vck44/valo=5,734.99 2006.257.12:46:52.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.12:46:52.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.12:46:52.62#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:52.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:52.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:52.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:52.62#ibcon#enter wrdev, iclass 31, count 0 2006.257.12:46:52.62#ibcon#first serial, iclass 31, count 0 2006.257.12:46:52.62#ibcon#enter sib2, iclass 31, count 0 2006.257.12:46:52.62#ibcon#flushed, iclass 31, count 0 2006.257.12:46:52.62#ibcon#about to write, iclass 31, count 0 2006.257.12:46:52.62#ibcon#wrote, iclass 31, count 0 2006.257.12:46:52.62#ibcon#about to read 3, iclass 31, count 0 2006.257.12:46:52.64#ibcon#read 3, iclass 31, count 0 2006.257.12:46:52.64#ibcon#about to read 4, iclass 31, count 0 2006.257.12:46:52.64#ibcon#read 4, iclass 31, count 0 2006.257.12:46:52.64#ibcon#about to read 5, iclass 31, count 0 2006.257.12:46:52.64#ibcon#read 5, iclass 31, count 0 2006.257.12:46:52.64#ibcon#about to read 6, iclass 31, count 0 2006.257.12:46:52.64#ibcon#read 6, iclass 31, count 0 2006.257.12:46:52.64#ibcon#end of sib2, iclass 31, count 0 2006.257.12:46:52.64#ibcon#*mode == 0, iclass 31, count 0 2006.257.12:46:52.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.12:46:52.64#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:46:52.64#ibcon#*before write, iclass 31, count 0 2006.257.12:46:52.64#ibcon#enter sib2, iclass 31, count 0 2006.257.12:46:52.64#ibcon#flushed, iclass 31, count 0 2006.257.12:46:52.64#ibcon#about to write, iclass 31, count 0 2006.257.12:46:52.64#ibcon#wrote, iclass 31, count 0 2006.257.12:46:52.64#ibcon#about to read 3, iclass 31, count 0 2006.257.12:46:52.68#ibcon#read 3, iclass 31, count 0 2006.257.12:46:52.68#ibcon#about to read 4, iclass 31, count 0 2006.257.12:46:52.68#ibcon#read 4, iclass 31, count 0 2006.257.12:46:52.68#ibcon#about to read 5, iclass 31, count 0 2006.257.12:46:52.68#ibcon#read 5, iclass 31, count 0 2006.257.12:46:52.68#ibcon#about to read 6, iclass 31, count 0 2006.257.12:46:52.68#ibcon#read 6, iclass 31, count 0 2006.257.12:46:52.68#ibcon#end of sib2, iclass 31, count 0 2006.257.12:46:52.68#ibcon#*after write, iclass 31, count 0 2006.257.12:46:52.68#ibcon#*before return 0, iclass 31, count 0 2006.257.12:46:52.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:52.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:52.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.12:46:52.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.12:46:52.68$vck44/va=5,4 2006.257.12:46:52.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.12:46:52.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.12:46:52.68#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:52.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:52.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:52.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:52.74#ibcon#enter wrdev, iclass 33, count 2 2006.257.12:46:52.74#ibcon#first serial, iclass 33, count 2 2006.257.12:46:52.74#ibcon#enter sib2, iclass 33, count 2 2006.257.12:46:52.74#ibcon#flushed, iclass 33, count 2 2006.257.12:46:52.74#ibcon#about to write, iclass 33, count 2 2006.257.12:46:52.74#ibcon#wrote, iclass 33, count 2 2006.257.12:46:52.74#ibcon#about to read 3, iclass 33, count 2 2006.257.12:46:52.76#ibcon#read 3, iclass 33, count 2 2006.257.12:46:52.76#ibcon#about to read 4, iclass 33, count 2 2006.257.12:46:52.76#ibcon#read 4, iclass 33, count 2 2006.257.12:46:52.76#ibcon#about to read 5, iclass 33, count 2 2006.257.12:46:52.76#ibcon#read 5, iclass 33, count 2 2006.257.12:46:52.76#ibcon#about to read 6, iclass 33, count 2 2006.257.12:46:52.76#ibcon#read 6, iclass 33, count 2 2006.257.12:46:52.76#ibcon#end of sib2, iclass 33, count 2 2006.257.12:46:52.76#ibcon#*mode == 0, iclass 33, count 2 2006.257.12:46:52.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.12:46:52.76#ibcon#[25=AT05-04\r\n] 2006.257.12:46:52.76#ibcon#*before write, iclass 33, count 2 2006.257.12:46:52.76#ibcon#enter sib2, iclass 33, count 2 2006.257.12:46:52.76#ibcon#flushed, iclass 33, count 2 2006.257.12:46:52.76#ibcon#about to write, iclass 33, count 2 2006.257.12:46:52.76#ibcon#wrote, iclass 33, count 2 2006.257.12:46:52.76#ibcon#about to read 3, iclass 33, count 2 2006.257.12:46:52.79#ibcon#read 3, iclass 33, count 2 2006.257.12:46:52.79#ibcon#about to read 4, iclass 33, count 2 2006.257.12:46:52.79#ibcon#read 4, iclass 33, count 2 2006.257.12:46:52.79#ibcon#about to read 5, iclass 33, count 2 2006.257.12:46:52.79#ibcon#read 5, iclass 33, count 2 2006.257.12:46:52.79#ibcon#about to read 6, iclass 33, count 2 2006.257.12:46:52.79#ibcon#read 6, iclass 33, count 2 2006.257.12:46:52.79#ibcon#end of sib2, iclass 33, count 2 2006.257.12:46:52.79#ibcon#*after write, iclass 33, count 2 2006.257.12:46:52.79#ibcon#*before return 0, iclass 33, count 2 2006.257.12:46:52.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:52.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:52.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.12:46:52.79#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:52.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:52.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:52.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:52.91#ibcon#enter wrdev, iclass 33, count 0 2006.257.12:46:52.91#ibcon#first serial, iclass 33, count 0 2006.257.12:46:52.91#ibcon#enter sib2, iclass 33, count 0 2006.257.12:46:52.91#ibcon#flushed, iclass 33, count 0 2006.257.12:46:52.91#ibcon#about to write, iclass 33, count 0 2006.257.12:46:52.91#ibcon#wrote, iclass 33, count 0 2006.257.12:46:52.91#ibcon#about to read 3, iclass 33, count 0 2006.257.12:46:52.93#ibcon#read 3, iclass 33, count 0 2006.257.12:46:52.93#ibcon#about to read 4, iclass 33, count 0 2006.257.12:46:52.93#ibcon#read 4, iclass 33, count 0 2006.257.12:46:52.93#ibcon#about to read 5, iclass 33, count 0 2006.257.12:46:52.93#ibcon#read 5, iclass 33, count 0 2006.257.12:46:52.93#ibcon#about to read 6, iclass 33, count 0 2006.257.12:46:52.93#ibcon#read 6, iclass 33, count 0 2006.257.12:46:52.93#ibcon#end of sib2, iclass 33, count 0 2006.257.12:46:52.93#ibcon#*mode == 0, iclass 33, count 0 2006.257.12:46:52.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.12:46:52.93#ibcon#[25=USB\r\n] 2006.257.12:46:52.93#ibcon#*before write, iclass 33, count 0 2006.257.12:46:52.93#ibcon#enter sib2, iclass 33, count 0 2006.257.12:46:52.93#ibcon#flushed, iclass 33, count 0 2006.257.12:46:52.93#ibcon#about to write, iclass 33, count 0 2006.257.12:46:52.93#ibcon#wrote, iclass 33, count 0 2006.257.12:46:52.93#ibcon#about to read 3, iclass 33, count 0 2006.257.12:46:52.96#ibcon#read 3, iclass 33, count 0 2006.257.12:46:52.96#ibcon#about to read 4, iclass 33, count 0 2006.257.12:46:52.96#ibcon#read 4, iclass 33, count 0 2006.257.12:46:52.96#ibcon#about to read 5, iclass 33, count 0 2006.257.12:46:52.96#ibcon#read 5, iclass 33, count 0 2006.257.12:46:52.96#ibcon#about to read 6, iclass 33, count 0 2006.257.12:46:52.96#ibcon#read 6, iclass 33, count 0 2006.257.12:46:52.96#ibcon#end of sib2, iclass 33, count 0 2006.257.12:46:52.96#ibcon#*after write, iclass 33, count 0 2006.257.12:46:52.96#ibcon#*before return 0, iclass 33, count 0 2006.257.12:46:52.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:52.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:52.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.12:46:52.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.12:46:52.96$vck44/valo=6,814.99 2006.257.12:46:52.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.12:46:52.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.12:46:52.96#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:52.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:52.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:52.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:52.96#ibcon#enter wrdev, iclass 35, count 0 2006.257.12:46:52.96#ibcon#first serial, iclass 35, count 0 2006.257.12:46:52.96#ibcon#enter sib2, iclass 35, count 0 2006.257.12:46:52.96#ibcon#flushed, iclass 35, count 0 2006.257.12:46:52.96#ibcon#about to write, iclass 35, count 0 2006.257.12:46:52.96#ibcon#wrote, iclass 35, count 0 2006.257.12:46:52.96#ibcon#about to read 3, iclass 35, count 0 2006.257.12:46:52.98#ibcon#read 3, iclass 35, count 0 2006.257.12:46:52.98#ibcon#about to read 4, iclass 35, count 0 2006.257.12:46:52.98#ibcon#read 4, iclass 35, count 0 2006.257.12:46:52.98#ibcon#about to read 5, iclass 35, count 0 2006.257.12:46:52.98#ibcon#read 5, iclass 35, count 0 2006.257.12:46:52.98#ibcon#about to read 6, iclass 35, count 0 2006.257.12:46:52.98#ibcon#read 6, iclass 35, count 0 2006.257.12:46:52.98#ibcon#end of sib2, iclass 35, count 0 2006.257.12:46:52.98#ibcon#*mode == 0, iclass 35, count 0 2006.257.12:46:52.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.12:46:52.98#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:46:52.98#ibcon#*before write, iclass 35, count 0 2006.257.12:46:52.98#ibcon#enter sib2, iclass 35, count 0 2006.257.12:46:52.98#ibcon#flushed, iclass 35, count 0 2006.257.12:46:52.98#ibcon#about to write, iclass 35, count 0 2006.257.12:46:52.98#ibcon#wrote, iclass 35, count 0 2006.257.12:46:52.98#ibcon#about to read 3, iclass 35, count 0 2006.257.12:46:53.02#ibcon#read 3, iclass 35, count 0 2006.257.12:46:53.02#ibcon#about to read 4, iclass 35, count 0 2006.257.12:46:53.02#ibcon#read 4, iclass 35, count 0 2006.257.12:46:53.02#ibcon#about to read 5, iclass 35, count 0 2006.257.12:46:53.02#ibcon#read 5, iclass 35, count 0 2006.257.12:46:53.02#ibcon#about to read 6, iclass 35, count 0 2006.257.12:46:53.02#ibcon#read 6, iclass 35, count 0 2006.257.12:46:53.02#ibcon#end of sib2, iclass 35, count 0 2006.257.12:46:53.02#ibcon#*after write, iclass 35, count 0 2006.257.12:46:53.02#ibcon#*before return 0, iclass 35, count 0 2006.257.12:46:53.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:53.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:53.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.12:46:53.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.12:46:53.02$vck44/va=6,4 2006.257.12:46:53.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.12:46:53.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.12:46:53.02#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:53.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:53.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:53.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:53.08#ibcon#enter wrdev, iclass 37, count 2 2006.257.12:46:53.08#ibcon#first serial, iclass 37, count 2 2006.257.12:46:53.08#ibcon#enter sib2, iclass 37, count 2 2006.257.12:46:53.08#ibcon#flushed, iclass 37, count 2 2006.257.12:46:53.08#ibcon#about to write, iclass 37, count 2 2006.257.12:46:53.08#ibcon#wrote, iclass 37, count 2 2006.257.12:46:53.08#ibcon#about to read 3, iclass 37, count 2 2006.257.12:46:53.10#ibcon#read 3, iclass 37, count 2 2006.257.12:46:53.10#ibcon#about to read 4, iclass 37, count 2 2006.257.12:46:53.10#ibcon#read 4, iclass 37, count 2 2006.257.12:46:53.10#ibcon#about to read 5, iclass 37, count 2 2006.257.12:46:53.10#ibcon#read 5, iclass 37, count 2 2006.257.12:46:53.10#ibcon#about to read 6, iclass 37, count 2 2006.257.12:46:53.10#ibcon#read 6, iclass 37, count 2 2006.257.12:46:53.10#ibcon#end of sib2, iclass 37, count 2 2006.257.12:46:53.10#ibcon#*mode == 0, iclass 37, count 2 2006.257.12:46:53.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.12:46:53.10#ibcon#[25=AT06-04\r\n] 2006.257.12:46:53.10#ibcon#*before write, iclass 37, count 2 2006.257.12:46:53.10#ibcon#enter sib2, iclass 37, count 2 2006.257.12:46:53.10#ibcon#flushed, iclass 37, count 2 2006.257.12:46:53.10#ibcon#about to write, iclass 37, count 2 2006.257.12:46:53.10#ibcon#wrote, iclass 37, count 2 2006.257.12:46:53.10#ibcon#about to read 3, iclass 37, count 2 2006.257.12:46:53.13#ibcon#read 3, iclass 37, count 2 2006.257.12:46:53.13#ibcon#about to read 4, iclass 37, count 2 2006.257.12:46:53.13#ibcon#read 4, iclass 37, count 2 2006.257.12:46:53.13#ibcon#about to read 5, iclass 37, count 2 2006.257.12:46:53.13#ibcon#read 5, iclass 37, count 2 2006.257.12:46:53.13#ibcon#about to read 6, iclass 37, count 2 2006.257.12:46:53.13#ibcon#read 6, iclass 37, count 2 2006.257.12:46:53.13#ibcon#end of sib2, iclass 37, count 2 2006.257.12:46:53.13#ibcon#*after write, iclass 37, count 2 2006.257.12:46:53.13#ibcon#*before return 0, iclass 37, count 2 2006.257.12:46:53.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:53.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:53.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.12:46:53.13#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:53.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:53.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:53.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:53.25#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:46:53.25#ibcon#first serial, iclass 37, count 0 2006.257.12:46:53.25#ibcon#enter sib2, iclass 37, count 0 2006.257.12:46:53.25#ibcon#flushed, iclass 37, count 0 2006.257.12:46:53.25#ibcon#about to write, iclass 37, count 0 2006.257.12:46:53.25#ibcon#wrote, iclass 37, count 0 2006.257.12:46:53.25#ibcon#about to read 3, iclass 37, count 0 2006.257.12:46:53.27#ibcon#read 3, iclass 37, count 0 2006.257.12:46:53.27#ibcon#about to read 4, iclass 37, count 0 2006.257.12:46:53.27#ibcon#read 4, iclass 37, count 0 2006.257.12:46:53.27#ibcon#about to read 5, iclass 37, count 0 2006.257.12:46:53.27#ibcon#read 5, iclass 37, count 0 2006.257.12:46:53.27#ibcon#about to read 6, iclass 37, count 0 2006.257.12:46:53.27#ibcon#read 6, iclass 37, count 0 2006.257.12:46:53.27#ibcon#end of sib2, iclass 37, count 0 2006.257.12:46:53.27#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:46:53.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:46:53.27#ibcon#[25=USB\r\n] 2006.257.12:46:53.27#ibcon#*before write, iclass 37, count 0 2006.257.12:46:53.27#ibcon#enter sib2, iclass 37, count 0 2006.257.12:46:53.27#ibcon#flushed, iclass 37, count 0 2006.257.12:46:53.27#ibcon#about to write, iclass 37, count 0 2006.257.12:46:53.27#ibcon#wrote, iclass 37, count 0 2006.257.12:46:53.27#ibcon#about to read 3, iclass 37, count 0 2006.257.12:46:53.30#ibcon#read 3, iclass 37, count 0 2006.257.12:46:53.30#ibcon#about to read 4, iclass 37, count 0 2006.257.12:46:53.30#ibcon#read 4, iclass 37, count 0 2006.257.12:46:53.30#ibcon#about to read 5, iclass 37, count 0 2006.257.12:46:53.30#ibcon#read 5, iclass 37, count 0 2006.257.12:46:53.30#ibcon#about to read 6, iclass 37, count 0 2006.257.12:46:53.30#ibcon#read 6, iclass 37, count 0 2006.257.12:46:53.30#ibcon#end of sib2, iclass 37, count 0 2006.257.12:46:53.30#ibcon#*after write, iclass 37, count 0 2006.257.12:46:53.30#ibcon#*before return 0, iclass 37, count 0 2006.257.12:46:53.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:53.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:53.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:46:53.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:46:53.30$vck44/valo=7,864.99 2006.257.12:46:53.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.12:46:53.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.12:46:53.30#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:53.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:53.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:53.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:53.30#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:46:53.30#ibcon#first serial, iclass 39, count 0 2006.257.12:46:53.30#ibcon#enter sib2, iclass 39, count 0 2006.257.12:46:53.30#ibcon#flushed, iclass 39, count 0 2006.257.12:46:53.30#ibcon#about to write, iclass 39, count 0 2006.257.12:46:53.30#ibcon#wrote, iclass 39, count 0 2006.257.12:46:53.30#ibcon#about to read 3, iclass 39, count 0 2006.257.12:46:53.32#ibcon#read 3, iclass 39, count 0 2006.257.12:46:53.32#ibcon#about to read 4, iclass 39, count 0 2006.257.12:46:53.32#ibcon#read 4, iclass 39, count 0 2006.257.12:46:53.32#ibcon#about to read 5, iclass 39, count 0 2006.257.12:46:53.32#ibcon#read 5, iclass 39, count 0 2006.257.12:46:53.32#ibcon#about to read 6, iclass 39, count 0 2006.257.12:46:53.32#ibcon#read 6, iclass 39, count 0 2006.257.12:46:53.32#ibcon#end of sib2, iclass 39, count 0 2006.257.12:46:53.32#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:46:53.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:46:53.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:46:53.32#ibcon#*before write, iclass 39, count 0 2006.257.12:46:53.32#ibcon#enter sib2, iclass 39, count 0 2006.257.12:46:53.32#ibcon#flushed, iclass 39, count 0 2006.257.12:46:53.32#ibcon#about to write, iclass 39, count 0 2006.257.12:46:53.32#ibcon#wrote, iclass 39, count 0 2006.257.12:46:53.32#ibcon#about to read 3, iclass 39, count 0 2006.257.12:46:53.36#ibcon#read 3, iclass 39, count 0 2006.257.12:46:53.36#ibcon#about to read 4, iclass 39, count 0 2006.257.12:46:53.36#ibcon#read 4, iclass 39, count 0 2006.257.12:46:53.36#ibcon#about to read 5, iclass 39, count 0 2006.257.12:46:53.36#ibcon#read 5, iclass 39, count 0 2006.257.12:46:53.36#ibcon#about to read 6, iclass 39, count 0 2006.257.12:46:53.36#ibcon#read 6, iclass 39, count 0 2006.257.12:46:53.36#ibcon#end of sib2, iclass 39, count 0 2006.257.12:46:53.36#ibcon#*after write, iclass 39, count 0 2006.257.12:46:53.36#ibcon#*before return 0, iclass 39, count 0 2006.257.12:46:53.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:53.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:53.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:46:53.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:46:53.36$vck44/va=7,4 2006.257.12:46:53.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.12:46:53.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.12:46:53.36#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:53.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:53.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:53.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:53.42#ibcon#enter wrdev, iclass 3, count 2 2006.257.12:46:53.42#ibcon#first serial, iclass 3, count 2 2006.257.12:46:53.42#ibcon#enter sib2, iclass 3, count 2 2006.257.12:46:53.42#ibcon#flushed, iclass 3, count 2 2006.257.12:46:53.42#ibcon#about to write, iclass 3, count 2 2006.257.12:46:53.42#ibcon#wrote, iclass 3, count 2 2006.257.12:46:53.42#ibcon#about to read 3, iclass 3, count 2 2006.257.12:46:53.44#ibcon#read 3, iclass 3, count 2 2006.257.12:46:53.44#ibcon#about to read 4, iclass 3, count 2 2006.257.12:46:53.44#ibcon#read 4, iclass 3, count 2 2006.257.12:46:53.44#ibcon#about to read 5, iclass 3, count 2 2006.257.12:46:53.44#ibcon#read 5, iclass 3, count 2 2006.257.12:46:53.44#ibcon#about to read 6, iclass 3, count 2 2006.257.12:46:53.44#ibcon#read 6, iclass 3, count 2 2006.257.12:46:53.44#ibcon#end of sib2, iclass 3, count 2 2006.257.12:46:53.44#ibcon#*mode == 0, iclass 3, count 2 2006.257.12:46:53.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.12:46:53.44#ibcon#[25=AT07-04\r\n] 2006.257.12:46:53.44#ibcon#*before write, iclass 3, count 2 2006.257.12:46:53.44#ibcon#enter sib2, iclass 3, count 2 2006.257.12:46:53.44#ibcon#flushed, iclass 3, count 2 2006.257.12:46:53.44#ibcon#about to write, iclass 3, count 2 2006.257.12:46:53.44#ibcon#wrote, iclass 3, count 2 2006.257.12:46:53.44#ibcon#about to read 3, iclass 3, count 2 2006.257.12:46:53.47#ibcon#read 3, iclass 3, count 2 2006.257.12:46:53.47#ibcon#about to read 4, iclass 3, count 2 2006.257.12:46:53.47#ibcon#read 4, iclass 3, count 2 2006.257.12:46:53.47#ibcon#about to read 5, iclass 3, count 2 2006.257.12:46:53.47#ibcon#read 5, iclass 3, count 2 2006.257.12:46:53.47#ibcon#about to read 6, iclass 3, count 2 2006.257.12:46:53.47#ibcon#read 6, iclass 3, count 2 2006.257.12:46:53.47#ibcon#end of sib2, iclass 3, count 2 2006.257.12:46:53.47#ibcon#*after write, iclass 3, count 2 2006.257.12:46:53.47#ibcon#*before return 0, iclass 3, count 2 2006.257.12:46:53.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:53.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:53.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.12:46:53.47#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:53.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:53.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:53.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:53.59#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:46:53.59#ibcon#first serial, iclass 3, count 0 2006.257.12:46:53.59#ibcon#enter sib2, iclass 3, count 0 2006.257.12:46:53.59#ibcon#flushed, iclass 3, count 0 2006.257.12:46:53.59#ibcon#about to write, iclass 3, count 0 2006.257.12:46:53.59#ibcon#wrote, iclass 3, count 0 2006.257.12:46:53.59#ibcon#about to read 3, iclass 3, count 0 2006.257.12:46:53.61#ibcon#read 3, iclass 3, count 0 2006.257.12:46:53.61#ibcon#about to read 4, iclass 3, count 0 2006.257.12:46:53.61#ibcon#read 4, iclass 3, count 0 2006.257.12:46:53.61#ibcon#about to read 5, iclass 3, count 0 2006.257.12:46:53.61#ibcon#read 5, iclass 3, count 0 2006.257.12:46:53.61#ibcon#about to read 6, iclass 3, count 0 2006.257.12:46:53.61#ibcon#read 6, iclass 3, count 0 2006.257.12:46:53.61#ibcon#end of sib2, iclass 3, count 0 2006.257.12:46:53.61#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:46:53.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:46:53.61#ibcon#[25=USB\r\n] 2006.257.12:46:53.61#ibcon#*before write, iclass 3, count 0 2006.257.12:46:53.61#ibcon#enter sib2, iclass 3, count 0 2006.257.12:46:53.61#ibcon#flushed, iclass 3, count 0 2006.257.12:46:53.61#ibcon#about to write, iclass 3, count 0 2006.257.12:46:53.61#ibcon#wrote, iclass 3, count 0 2006.257.12:46:53.61#ibcon#about to read 3, iclass 3, count 0 2006.257.12:46:53.64#ibcon#read 3, iclass 3, count 0 2006.257.12:46:53.64#ibcon#about to read 4, iclass 3, count 0 2006.257.12:46:53.64#ibcon#read 4, iclass 3, count 0 2006.257.12:46:53.64#ibcon#about to read 5, iclass 3, count 0 2006.257.12:46:53.64#ibcon#read 5, iclass 3, count 0 2006.257.12:46:53.64#ibcon#about to read 6, iclass 3, count 0 2006.257.12:46:53.64#ibcon#read 6, iclass 3, count 0 2006.257.12:46:53.64#ibcon#end of sib2, iclass 3, count 0 2006.257.12:46:53.64#ibcon#*after write, iclass 3, count 0 2006.257.12:46:53.64#ibcon#*before return 0, iclass 3, count 0 2006.257.12:46:53.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:53.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:53.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:46:53.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:46:53.64$vck44/valo=8,884.99 2006.257.12:46:53.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.12:46:53.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.12:46:53.64#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:53.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:53.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:53.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:53.64#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:46:53.64#ibcon#first serial, iclass 5, count 0 2006.257.12:46:53.64#ibcon#enter sib2, iclass 5, count 0 2006.257.12:46:53.64#ibcon#flushed, iclass 5, count 0 2006.257.12:46:53.64#ibcon#about to write, iclass 5, count 0 2006.257.12:46:53.64#ibcon#wrote, iclass 5, count 0 2006.257.12:46:53.64#ibcon#about to read 3, iclass 5, count 0 2006.257.12:46:53.66#ibcon#read 3, iclass 5, count 0 2006.257.12:46:53.66#ibcon#about to read 4, iclass 5, count 0 2006.257.12:46:53.66#ibcon#read 4, iclass 5, count 0 2006.257.12:46:53.66#ibcon#about to read 5, iclass 5, count 0 2006.257.12:46:53.66#ibcon#read 5, iclass 5, count 0 2006.257.12:46:53.66#ibcon#about to read 6, iclass 5, count 0 2006.257.12:46:53.66#ibcon#read 6, iclass 5, count 0 2006.257.12:46:53.66#ibcon#end of sib2, iclass 5, count 0 2006.257.12:46:53.66#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:46:53.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:46:53.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:46:53.66#ibcon#*before write, iclass 5, count 0 2006.257.12:46:53.66#ibcon#enter sib2, iclass 5, count 0 2006.257.12:46:53.66#ibcon#flushed, iclass 5, count 0 2006.257.12:46:53.66#ibcon#about to write, iclass 5, count 0 2006.257.12:46:53.66#ibcon#wrote, iclass 5, count 0 2006.257.12:46:53.66#ibcon#about to read 3, iclass 5, count 0 2006.257.12:46:53.70#ibcon#read 3, iclass 5, count 0 2006.257.12:46:53.70#ibcon#about to read 4, iclass 5, count 0 2006.257.12:46:53.70#ibcon#read 4, iclass 5, count 0 2006.257.12:46:53.70#ibcon#about to read 5, iclass 5, count 0 2006.257.12:46:53.70#ibcon#read 5, iclass 5, count 0 2006.257.12:46:53.70#ibcon#about to read 6, iclass 5, count 0 2006.257.12:46:53.70#ibcon#read 6, iclass 5, count 0 2006.257.12:46:53.70#ibcon#end of sib2, iclass 5, count 0 2006.257.12:46:53.70#ibcon#*after write, iclass 5, count 0 2006.257.12:46:53.70#ibcon#*before return 0, iclass 5, count 0 2006.257.12:46:53.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:53.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:53.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:46:53.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:46:53.70$vck44/va=8,4 2006.257.12:46:53.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.12:46:53.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.12:46:53.70#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:53.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:46:53.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:46:53.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:46:53.76#ibcon#enter wrdev, iclass 7, count 2 2006.257.12:46:53.76#ibcon#first serial, iclass 7, count 2 2006.257.12:46:53.76#ibcon#enter sib2, iclass 7, count 2 2006.257.12:46:53.76#ibcon#flushed, iclass 7, count 2 2006.257.12:46:53.76#ibcon#about to write, iclass 7, count 2 2006.257.12:46:53.76#ibcon#wrote, iclass 7, count 2 2006.257.12:46:53.76#ibcon#about to read 3, iclass 7, count 2 2006.257.12:46:53.78#ibcon#read 3, iclass 7, count 2 2006.257.12:46:53.78#ibcon#about to read 4, iclass 7, count 2 2006.257.12:46:53.78#ibcon#read 4, iclass 7, count 2 2006.257.12:46:53.78#ibcon#about to read 5, iclass 7, count 2 2006.257.12:46:53.78#ibcon#read 5, iclass 7, count 2 2006.257.12:46:53.78#ibcon#about to read 6, iclass 7, count 2 2006.257.12:46:53.78#ibcon#read 6, iclass 7, count 2 2006.257.12:46:53.78#ibcon#end of sib2, iclass 7, count 2 2006.257.12:46:53.78#ibcon#*mode == 0, iclass 7, count 2 2006.257.12:46:53.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.12:46:53.78#ibcon#[25=AT08-04\r\n] 2006.257.12:46:53.78#ibcon#*before write, iclass 7, count 2 2006.257.12:46:53.78#ibcon#enter sib2, iclass 7, count 2 2006.257.12:46:53.78#ibcon#flushed, iclass 7, count 2 2006.257.12:46:53.78#ibcon#about to write, iclass 7, count 2 2006.257.12:46:53.78#ibcon#wrote, iclass 7, count 2 2006.257.12:46:53.78#ibcon#about to read 3, iclass 7, count 2 2006.257.12:46:53.81#ibcon#read 3, iclass 7, count 2 2006.257.12:46:53.81#ibcon#about to read 4, iclass 7, count 2 2006.257.12:46:53.81#ibcon#read 4, iclass 7, count 2 2006.257.12:46:53.81#ibcon#about to read 5, iclass 7, count 2 2006.257.12:46:53.81#ibcon#read 5, iclass 7, count 2 2006.257.12:46:53.81#ibcon#about to read 6, iclass 7, count 2 2006.257.12:46:53.81#ibcon#read 6, iclass 7, count 2 2006.257.12:46:53.81#ibcon#end of sib2, iclass 7, count 2 2006.257.12:46:53.81#ibcon#*after write, iclass 7, count 2 2006.257.12:46:53.81#ibcon#*before return 0, iclass 7, count 2 2006.257.12:46:53.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:46:53.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.12:46:53.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.12:46:53.81#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:53.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:46:53.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:46:53.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:46:53.93#ibcon#enter wrdev, iclass 7, count 0 2006.257.12:46:53.93#ibcon#first serial, iclass 7, count 0 2006.257.12:46:53.93#ibcon#enter sib2, iclass 7, count 0 2006.257.12:46:53.93#ibcon#flushed, iclass 7, count 0 2006.257.12:46:53.93#ibcon#about to write, iclass 7, count 0 2006.257.12:46:53.93#ibcon#wrote, iclass 7, count 0 2006.257.12:46:53.93#ibcon#about to read 3, iclass 7, count 0 2006.257.12:46:53.95#ibcon#read 3, iclass 7, count 0 2006.257.12:46:53.95#ibcon#about to read 4, iclass 7, count 0 2006.257.12:46:53.95#ibcon#read 4, iclass 7, count 0 2006.257.12:46:53.95#ibcon#about to read 5, iclass 7, count 0 2006.257.12:46:53.95#ibcon#read 5, iclass 7, count 0 2006.257.12:46:53.95#ibcon#about to read 6, iclass 7, count 0 2006.257.12:46:53.95#ibcon#read 6, iclass 7, count 0 2006.257.12:46:53.95#ibcon#end of sib2, iclass 7, count 0 2006.257.12:46:53.95#ibcon#*mode == 0, iclass 7, count 0 2006.257.12:46:53.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.12:46:53.95#ibcon#[25=USB\r\n] 2006.257.12:46:53.95#ibcon#*before write, iclass 7, count 0 2006.257.12:46:53.95#ibcon#enter sib2, iclass 7, count 0 2006.257.12:46:53.95#ibcon#flushed, iclass 7, count 0 2006.257.12:46:53.95#ibcon#about to write, iclass 7, count 0 2006.257.12:46:53.95#ibcon#wrote, iclass 7, count 0 2006.257.12:46:53.95#ibcon#about to read 3, iclass 7, count 0 2006.257.12:46:53.98#ibcon#read 3, iclass 7, count 0 2006.257.12:46:53.98#ibcon#about to read 4, iclass 7, count 0 2006.257.12:46:53.98#ibcon#read 4, iclass 7, count 0 2006.257.12:46:53.98#ibcon#about to read 5, iclass 7, count 0 2006.257.12:46:53.98#ibcon#read 5, iclass 7, count 0 2006.257.12:46:53.98#ibcon#about to read 6, iclass 7, count 0 2006.257.12:46:53.98#ibcon#read 6, iclass 7, count 0 2006.257.12:46:53.98#ibcon#end of sib2, iclass 7, count 0 2006.257.12:46:53.98#ibcon#*after write, iclass 7, count 0 2006.257.12:46:53.98#ibcon#*before return 0, iclass 7, count 0 2006.257.12:46:53.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:46:53.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.12:46:53.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.12:46:53.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.12:46:53.98$vck44/vblo=1,629.99 2006.257.12:46:53.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.12:46:53.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.12:46:53.98#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:53.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:46:53.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:46:53.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:46:53.98#ibcon#enter wrdev, iclass 11, count 0 2006.257.12:46:53.98#ibcon#first serial, iclass 11, count 0 2006.257.12:46:53.98#ibcon#enter sib2, iclass 11, count 0 2006.257.12:46:53.98#ibcon#flushed, iclass 11, count 0 2006.257.12:46:53.98#ibcon#about to write, iclass 11, count 0 2006.257.12:46:53.98#ibcon#wrote, iclass 11, count 0 2006.257.12:46:53.98#ibcon#about to read 3, iclass 11, count 0 2006.257.12:46:54.00#ibcon#read 3, iclass 11, count 0 2006.257.12:46:54.00#ibcon#about to read 4, iclass 11, count 0 2006.257.12:46:54.00#ibcon#read 4, iclass 11, count 0 2006.257.12:46:54.00#ibcon#about to read 5, iclass 11, count 0 2006.257.12:46:54.00#ibcon#read 5, iclass 11, count 0 2006.257.12:46:54.00#ibcon#about to read 6, iclass 11, count 0 2006.257.12:46:54.00#ibcon#read 6, iclass 11, count 0 2006.257.12:46:54.00#ibcon#end of sib2, iclass 11, count 0 2006.257.12:46:54.00#ibcon#*mode == 0, iclass 11, count 0 2006.257.12:46:54.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.12:46:54.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:46:54.00#ibcon#*before write, iclass 11, count 0 2006.257.12:46:54.00#ibcon#enter sib2, iclass 11, count 0 2006.257.12:46:54.00#ibcon#flushed, iclass 11, count 0 2006.257.12:46:54.00#ibcon#about to write, iclass 11, count 0 2006.257.12:46:54.00#ibcon#wrote, iclass 11, count 0 2006.257.12:46:54.00#ibcon#about to read 3, iclass 11, count 0 2006.257.12:46:54.04#ibcon#read 3, iclass 11, count 0 2006.257.12:46:54.04#ibcon#about to read 4, iclass 11, count 0 2006.257.12:46:54.04#ibcon#read 4, iclass 11, count 0 2006.257.12:46:54.04#ibcon#about to read 5, iclass 11, count 0 2006.257.12:46:54.04#ibcon#read 5, iclass 11, count 0 2006.257.12:46:54.04#ibcon#about to read 6, iclass 11, count 0 2006.257.12:46:54.04#ibcon#read 6, iclass 11, count 0 2006.257.12:46:54.04#ibcon#end of sib2, iclass 11, count 0 2006.257.12:46:54.04#ibcon#*after write, iclass 11, count 0 2006.257.12:46:54.04#ibcon#*before return 0, iclass 11, count 0 2006.257.12:46:54.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:46:54.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.12:46:54.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.12:46:54.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.12:46:54.04$vck44/vb=1,4 2006.257.12:46:54.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.12:46:54.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.12:46:54.04#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:54.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:46:54.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:46:54.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:46:54.04#ibcon#enter wrdev, iclass 13, count 2 2006.257.12:46:54.04#ibcon#first serial, iclass 13, count 2 2006.257.12:46:54.04#ibcon#enter sib2, iclass 13, count 2 2006.257.12:46:54.04#ibcon#flushed, iclass 13, count 2 2006.257.12:46:54.04#ibcon#about to write, iclass 13, count 2 2006.257.12:46:54.04#ibcon#wrote, iclass 13, count 2 2006.257.12:46:54.04#ibcon#about to read 3, iclass 13, count 2 2006.257.12:46:54.06#ibcon#read 3, iclass 13, count 2 2006.257.12:46:54.06#ibcon#about to read 4, iclass 13, count 2 2006.257.12:46:54.06#ibcon#read 4, iclass 13, count 2 2006.257.12:46:54.06#ibcon#about to read 5, iclass 13, count 2 2006.257.12:46:54.06#ibcon#read 5, iclass 13, count 2 2006.257.12:46:54.06#ibcon#about to read 6, iclass 13, count 2 2006.257.12:46:54.06#ibcon#read 6, iclass 13, count 2 2006.257.12:46:54.06#ibcon#end of sib2, iclass 13, count 2 2006.257.12:46:54.06#ibcon#*mode == 0, iclass 13, count 2 2006.257.12:46:54.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.12:46:54.06#ibcon#[27=AT01-04\r\n] 2006.257.12:46:54.06#ibcon#*before write, iclass 13, count 2 2006.257.12:46:54.06#ibcon#enter sib2, iclass 13, count 2 2006.257.12:46:54.06#ibcon#flushed, iclass 13, count 2 2006.257.12:46:54.06#ibcon#about to write, iclass 13, count 2 2006.257.12:46:54.06#ibcon#wrote, iclass 13, count 2 2006.257.12:46:54.06#ibcon#about to read 3, iclass 13, count 2 2006.257.12:46:54.09#ibcon#read 3, iclass 13, count 2 2006.257.12:46:54.09#ibcon#about to read 4, iclass 13, count 2 2006.257.12:46:54.09#ibcon#read 4, iclass 13, count 2 2006.257.12:46:54.09#ibcon#about to read 5, iclass 13, count 2 2006.257.12:46:54.09#ibcon#read 5, iclass 13, count 2 2006.257.12:46:54.09#ibcon#about to read 6, iclass 13, count 2 2006.257.12:46:54.09#ibcon#read 6, iclass 13, count 2 2006.257.12:46:54.09#ibcon#end of sib2, iclass 13, count 2 2006.257.12:46:54.09#ibcon#*after write, iclass 13, count 2 2006.257.12:46:54.09#ibcon#*before return 0, iclass 13, count 2 2006.257.12:46:54.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:46:54.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.12:46:54.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.12:46:54.09#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:54.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:46:54.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:46:54.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:46:54.21#ibcon#enter wrdev, iclass 13, count 0 2006.257.12:46:54.21#ibcon#first serial, iclass 13, count 0 2006.257.12:46:54.21#ibcon#enter sib2, iclass 13, count 0 2006.257.12:46:54.21#ibcon#flushed, iclass 13, count 0 2006.257.12:46:54.21#ibcon#about to write, iclass 13, count 0 2006.257.12:46:54.21#ibcon#wrote, iclass 13, count 0 2006.257.12:46:54.21#ibcon#about to read 3, iclass 13, count 0 2006.257.12:46:54.23#ibcon#read 3, iclass 13, count 0 2006.257.12:46:54.23#ibcon#about to read 4, iclass 13, count 0 2006.257.12:46:54.23#ibcon#read 4, iclass 13, count 0 2006.257.12:46:54.23#ibcon#about to read 5, iclass 13, count 0 2006.257.12:46:54.23#ibcon#read 5, iclass 13, count 0 2006.257.12:46:54.23#ibcon#about to read 6, iclass 13, count 0 2006.257.12:46:54.23#ibcon#read 6, iclass 13, count 0 2006.257.12:46:54.23#ibcon#end of sib2, iclass 13, count 0 2006.257.12:46:54.23#ibcon#*mode == 0, iclass 13, count 0 2006.257.12:46:54.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.12:46:54.23#ibcon#[27=USB\r\n] 2006.257.12:46:54.23#ibcon#*before write, iclass 13, count 0 2006.257.12:46:54.23#ibcon#enter sib2, iclass 13, count 0 2006.257.12:46:54.23#ibcon#flushed, iclass 13, count 0 2006.257.12:46:54.23#ibcon#about to write, iclass 13, count 0 2006.257.12:46:54.23#ibcon#wrote, iclass 13, count 0 2006.257.12:46:54.23#ibcon#about to read 3, iclass 13, count 0 2006.257.12:46:54.26#ibcon#read 3, iclass 13, count 0 2006.257.12:46:54.26#ibcon#about to read 4, iclass 13, count 0 2006.257.12:46:54.26#ibcon#read 4, iclass 13, count 0 2006.257.12:46:54.26#ibcon#about to read 5, iclass 13, count 0 2006.257.12:46:54.26#ibcon#read 5, iclass 13, count 0 2006.257.12:46:54.26#ibcon#about to read 6, iclass 13, count 0 2006.257.12:46:54.26#ibcon#read 6, iclass 13, count 0 2006.257.12:46:54.26#ibcon#end of sib2, iclass 13, count 0 2006.257.12:46:54.26#ibcon#*after write, iclass 13, count 0 2006.257.12:46:54.26#ibcon#*before return 0, iclass 13, count 0 2006.257.12:46:54.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:46:54.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.12:46:54.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.12:46:54.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.12:46:54.26$vck44/vblo=2,634.99 2006.257.12:46:54.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.12:46:54.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.12:46:54.26#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:54.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:54.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:54.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:54.26#ibcon#enter wrdev, iclass 15, count 0 2006.257.12:46:54.26#ibcon#first serial, iclass 15, count 0 2006.257.12:46:54.26#ibcon#enter sib2, iclass 15, count 0 2006.257.12:46:54.26#ibcon#flushed, iclass 15, count 0 2006.257.12:46:54.26#ibcon#about to write, iclass 15, count 0 2006.257.12:46:54.26#ibcon#wrote, iclass 15, count 0 2006.257.12:46:54.26#ibcon#about to read 3, iclass 15, count 0 2006.257.12:46:54.28#ibcon#read 3, iclass 15, count 0 2006.257.12:46:54.28#ibcon#about to read 4, iclass 15, count 0 2006.257.12:46:54.28#ibcon#read 4, iclass 15, count 0 2006.257.12:46:54.28#ibcon#about to read 5, iclass 15, count 0 2006.257.12:46:54.28#ibcon#read 5, iclass 15, count 0 2006.257.12:46:54.28#ibcon#about to read 6, iclass 15, count 0 2006.257.12:46:54.28#ibcon#read 6, iclass 15, count 0 2006.257.12:46:54.28#ibcon#end of sib2, iclass 15, count 0 2006.257.12:46:54.28#ibcon#*mode == 0, iclass 15, count 0 2006.257.12:46:54.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.12:46:54.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:46:54.28#ibcon#*before write, iclass 15, count 0 2006.257.12:46:54.28#ibcon#enter sib2, iclass 15, count 0 2006.257.12:46:54.28#ibcon#flushed, iclass 15, count 0 2006.257.12:46:54.28#ibcon#about to write, iclass 15, count 0 2006.257.12:46:54.28#ibcon#wrote, iclass 15, count 0 2006.257.12:46:54.28#ibcon#about to read 3, iclass 15, count 0 2006.257.12:46:54.32#ibcon#read 3, iclass 15, count 0 2006.257.12:46:54.32#ibcon#about to read 4, iclass 15, count 0 2006.257.12:46:54.32#ibcon#read 4, iclass 15, count 0 2006.257.12:46:54.32#ibcon#about to read 5, iclass 15, count 0 2006.257.12:46:54.32#ibcon#read 5, iclass 15, count 0 2006.257.12:46:54.32#ibcon#about to read 6, iclass 15, count 0 2006.257.12:46:54.32#ibcon#read 6, iclass 15, count 0 2006.257.12:46:54.32#ibcon#end of sib2, iclass 15, count 0 2006.257.12:46:54.32#ibcon#*after write, iclass 15, count 0 2006.257.12:46:54.32#ibcon#*before return 0, iclass 15, count 0 2006.257.12:46:54.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:54.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.12:46:54.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.12:46:54.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.12:46:54.32$vck44/vb=2,5 2006.257.12:46:54.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.12:46:54.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.12:46:54.32#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:54.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:54.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:54.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:54.38#ibcon#enter wrdev, iclass 17, count 2 2006.257.12:46:54.38#ibcon#first serial, iclass 17, count 2 2006.257.12:46:54.38#ibcon#enter sib2, iclass 17, count 2 2006.257.12:46:54.38#ibcon#flushed, iclass 17, count 2 2006.257.12:46:54.38#ibcon#about to write, iclass 17, count 2 2006.257.12:46:54.38#ibcon#wrote, iclass 17, count 2 2006.257.12:46:54.38#ibcon#about to read 3, iclass 17, count 2 2006.257.12:46:54.40#ibcon#read 3, iclass 17, count 2 2006.257.12:46:54.40#ibcon#about to read 4, iclass 17, count 2 2006.257.12:46:54.40#ibcon#read 4, iclass 17, count 2 2006.257.12:46:54.40#ibcon#about to read 5, iclass 17, count 2 2006.257.12:46:54.40#ibcon#read 5, iclass 17, count 2 2006.257.12:46:54.40#ibcon#about to read 6, iclass 17, count 2 2006.257.12:46:54.40#ibcon#read 6, iclass 17, count 2 2006.257.12:46:54.40#ibcon#end of sib2, iclass 17, count 2 2006.257.12:46:54.40#ibcon#*mode == 0, iclass 17, count 2 2006.257.12:46:54.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.12:46:54.40#ibcon#[27=AT02-05\r\n] 2006.257.12:46:54.40#ibcon#*before write, iclass 17, count 2 2006.257.12:46:54.40#ibcon#enter sib2, iclass 17, count 2 2006.257.12:46:54.40#ibcon#flushed, iclass 17, count 2 2006.257.12:46:54.40#ibcon#about to write, iclass 17, count 2 2006.257.12:46:54.40#ibcon#wrote, iclass 17, count 2 2006.257.12:46:54.40#ibcon#about to read 3, iclass 17, count 2 2006.257.12:46:54.43#ibcon#read 3, iclass 17, count 2 2006.257.12:46:54.43#ibcon#about to read 4, iclass 17, count 2 2006.257.12:46:54.43#ibcon#read 4, iclass 17, count 2 2006.257.12:46:54.43#ibcon#about to read 5, iclass 17, count 2 2006.257.12:46:54.43#ibcon#read 5, iclass 17, count 2 2006.257.12:46:54.43#ibcon#about to read 6, iclass 17, count 2 2006.257.12:46:54.43#ibcon#read 6, iclass 17, count 2 2006.257.12:46:54.43#ibcon#end of sib2, iclass 17, count 2 2006.257.12:46:54.43#ibcon#*after write, iclass 17, count 2 2006.257.12:46:54.43#ibcon#*before return 0, iclass 17, count 2 2006.257.12:46:54.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:54.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.12:46:54.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.12:46:54.43#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:54.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:54.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:54.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:54.55#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:46:54.55#ibcon#first serial, iclass 17, count 0 2006.257.12:46:54.55#ibcon#enter sib2, iclass 17, count 0 2006.257.12:46:54.55#ibcon#flushed, iclass 17, count 0 2006.257.12:46:54.55#ibcon#about to write, iclass 17, count 0 2006.257.12:46:54.55#ibcon#wrote, iclass 17, count 0 2006.257.12:46:54.55#ibcon#about to read 3, iclass 17, count 0 2006.257.12:46:54.57#ibcon#read 3, iclass 17, count 0 2006.257.12:46:54.57#ibcon#about to read 4, iclass 17, count 0 2006.257.12:46:54.57#ibcon#read 4, iclass 17, count 0 2006.257.12:46:54.57#ibcon#about to read 5, iclass 17, count 0 2006.257.12:46:54.57#ibcon#read 5, iclass 17, count 0 2006.257.12:46:54.57#ibcon#about to read 6, iclass 17, count 0 2006.257.12:46:54.57#ibcon#read 6, iclass 17, count 0 2006.257.12:46:54.57#ibcon#end of sib2, iclass 17, count 0 2006.257.12:46:54.57#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:46:54.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:46:54.57#ibcon#[27=USB\r\n] 2006.257.12:46:54.57#ibcon#*before write, iclass 17, count 0 2006.257.12:46:54.57#ibcon#enter sib2, iclass 17, count 0 2006.257.12:46:54.57#ibcon#flushed, iclass 17, count 0 2006.257.12:46:54.57#ibcon#about to write, iclass 17, count 0 2006.257.12:46:54.57#ibcon#wrote, iclass 17, count 0 2006.257.12:46:54.57#ibcon#about to read 3, iclass 17, count 0 2006.257.12:46:54.60#ibcon#read 3, iclass 17, count 0 2006.257.12:46:54.60#ibcon#about to read 4, iclass 17, count 0 2006.257.12:46:54.60#ibcon#read 4, iclass 17, count 0 2006.257.12:46:54.60#ibcon#about to read 5, iclass 17, count 0 2006.257.12:46:54.60#ibcon#read 5, iclass 17, count 0 2006.257.12:46:54.60#ibcon#about to read 6, iclass 17, count 0 2006.257.12:46:54.60#ibcon#read 6, iclass 17, count 0 2006.257.12:46:54.60#ibcon#end of sib2, iclass 17, count 0 2006.257.12:46:54.60#ibcon#*after write, iclass 17, count 0 2006.257.12:46:54.60#ibcon#*before return 0, iclass 17, count 0 2006.257.12:46:54.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:54.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.12:46:54.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:46:54.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:46:54.60$vck44/vblo=3,649.99 2006.257.12:46:54.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.12:46:54.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.12:46:54.60#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:54.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:54.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:54.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:54.60#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:46:54.60#ibcon#first serial, iclass 19, count 0 2006.257.12:46:54.60#ibcon#enter sib2, iclass 19, count 0 2006.257.12:46:54.60#ibcon#flushed, iclass 19, count 0 2006.257.12:46:54.60#ibcon#about to write, iclass 19, count 0 2006.257.12:46:54.60#ibcon#wrote, iclass 19, count 0 2006.257.12:46:54.60#ibcon#about to read 3, iclass 19, count 0 2006.257.12:46:54.62#ibcon#read 3, iclass 19, count 0 2006.257.12:46:54.62#ibcon#about to read 4, iclass 19, count 0 2006.257.12:46:54.62#ibcon#read 4, iclass 19, count 0 2006.257.12:46:54.62#ibcon#about to read 5, iclass 19, count 0 2006.257.12:46:54.62#ibcon#read 5, iclass 19, count 0 2006.257.12:46:54.62#ibcon#about to read 6, iclass 19, count 0 2006.257.12:46:54.62#ibcon#read 6, iclass 19, count 0 2006.257.12:46:54.62#ibcon#end of sib2, iclass 19, count 0 2006.257.12:46:54.62#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:46:54.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:46:54.62#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:46:54.62#ibcon#*before write, iclass 19, count 0 2006.257.12:46:54.62#ibcon#enter sib2, iclass 19, count 0 2006.257.12:46:54.62#ibcon#flushed, iclass 19, count 0 2006.257.12:46:54.62#ibcon#about to write, iclass 19, count 0 2006.257.12:46:54.62#ibcon#wrote, iclass 19, count 0 2006.257.12:46:54.62#ibcon#about to read 3, iclass 19, count 0 2006.257.12:46:54.66#ibcon#read 3, iclass 19, count 0 2006.257.12:46:54.66#ibcon#about to read 4, iclass 19, count 0 2006.257.12:46:54.66#ibcon#read 4, iclass 19, count 0 2006.257.12:46:54.66#ibcon#about to read 5, iclass 19, count 0 2006.257.12:46:54.66#ibcon#read 5, iclass 19, count 0 2006.257.12:46:54.66#ibcon#about to read 6, iclass 19, count 0 2006.257.12:46:54.66#ibcon#read 6, iclass 19, count 0 2006.257.12:46:54.66#ibcon#end of sib2, iclass 19, count 0 2006.257.12:46:54.66#ibcon#*after write, iclass 19, count 0 2006.257.12:46:54.66#ibcon#*before return 0, iclass 19, count 0 2006.257.12:46:54.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:54.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.12:46:54.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:46:54.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:46:54.66$vck44/vb=3,4 2006.257.12:46:54.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.12:46:54.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.12:46:54.66#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:54.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:54.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:54.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:54.72#ibcon#enter wrdev, iclass 21, count 2 2006.257.12:46:54.72#ibcon#first serial, iclass 21, count 2 2006.257.12:46:54.72#ibcon#enter sib2, iclass 21, count 2 2006.257.12:46:54.72#ibcon#flushed, iclass 21, count 2 2006.257.12:46:54.72#ibcon#about to write, iclass 21, count 2 2006.257.12:46:54.72#ibcon#wrote, iclass 21, count 2 2006.257.12:46:54.72#ibcon#about to read 3, iclass 21, count 2 2006.257.12:46:54.74#ibcon#read 3, iclass 21, count 2 2006.257.12:46:54.74#ibcon#about to read 4, iclass 21, count 2 2006.257.12:46:54.74#ibcon#read 4, iclass 21, count 2 2006.257.12:46:54.74#ibcon#about to read 5, iclass 21, count 2 2006.257.12:46:54.74#ibcon#read 5, iclass 21, count 2 2006.257.12:46:54.74#ibcon#about to read 6, iclass 21, count 2 2006.257.12:46:54.74#ibcon#read 6, iclass 21, count 2 2006.257.12:46:54.74#ibcon#end of sib2, iclass 21, count 2 2006.257.12:46:54.74#ibcon#*mode == 0, iclass 21, count 2 2006.257.12:46:54.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.12:46:54.74#ibcon#[27=AT03-04\r\n] 2006.257.12:46:54.74#ibcon#*before write, iclass 21, count 2 2006.257.12:46:54.74#ibcon#enter sib2, iclass 21, count 2 2006.257.12:46:54.74#ibcon#flushed, iclass 21, count 2 2006.257.12:46:54.74#ibcon#about to write, iclass 21, count 2 2006.257.12:46:54.74#ibcon#wrote, iclass 21, count 2 2006.257.12:46:54.74#ibcon#about to read 3, iclass 21, count 2 2006.257.12:46:54.77#ibcon#read 3, iclass 21, count 2 2006.257.12:46:54.77#ibcon#about to read 4, iclass 21, count 2 2006.257.12:46:54.77#ibcon#read 4, iclass 21, count 2 2006.257.12:46:54.77#ibcon#about to read 5, iclass 21, count 2 2006.257.12:46:54.77#ibcon#read 5, iclass 21, count 2 2006.257.12:46:54.77#ibcon#about to read 6, iclass 21, count 2 2006.257.12:46:54.77#ibcon#read 6, iclass 21, count 2 2006.257.12:46:54.77#ibcon#end of sib2, iclass 21, count 2 2006.257.12:46:54.77#ibcon#*after write, iclass 21, count 2 2006.257.12:46:54.77#ibcon#*before return 0, iclass 21, count 2 2006.257.12:46:54.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:54.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.12:46:54.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.12:46:54.77#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:54.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:54.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:54.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:54.89#ibcon#enter wrdev, iclass 21, count 0 2006.257.12:46:54.89#ibcon#first serial, iclass 21, count 0 2006.257.12:46:54.89#ibcon#enter sib2, iclass 21, count 0 2006.257.12:46:54.89#ibcon#flushed, iclass 21, count 0 2006.257.12:46:54.89#ibcon#about to write, iclass 21, count 0 2006.257.12:46:54.89#ibcon#wrote, iclass 21, count 0 2006.257.12:46:54.89#ibcon#about to read 3, iclass 21, count 0 2006.257.12:46:54.91#ibcon#read 3, iclass 21, count 0 2006.257.12:46:54.91#ibcon#about to read 4, iclass 21, count 0 2006.257.12:46:54.91#ibcon#read 4, iclass 21, count 0 2006.257.12:46:54.91#ibcon#about to read 5, iclass 21, count 0 2006.257.12:46:54.91#ibcon#read 5, iclass 21, count 0 2006.257.12:46:54.91#ibcon#about to read 6, iclass 21, count 0 2006.257.12:46:54.91#ibcon#read 6, iclass 21, count 0 2006.257.12:46:54.91#ibcon#end of sib2, iclass 21, count 0 2006.257.12:46:54.91#ibcon#*mode == 0, iclass 21, count 0 2006.257.12:46:54.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.12:46:54.91#ibcon#[27=USB\r\n] 2006.257.12:46:54.91#ibcon#*before write, iclass 21, count 0 2006.257.12:46:54.91#ibcon#enter sib2, iclass 21, count 0 2006.257.12:46:54.91#ibcon#flushed, iclass 21, count 0 2006.257.12:46:54.91#ibcon#about to write, iclass 21, count 0 2006.257.12:46:54.91#ibcon#wrote, iclass 21, count 0 2006.257.12:46:54.91#ibcon#about to read 3, iclass 21, count 0 2006.257.12:46:54.94#ibcon#read 3, iclass 21, count 0 2006.257.12:46:54.94#ibcon#about to read 4, iclass 21, count 0 2006.257.12:46:54.94#ibcon#read 4, iclass 21, count 0 2006.257.12:46:54.94#ibcon#about to read 5, iclass 21, count 0 2006.257.12:46:54.94#ibcon#read 5, iclass 21, count 0 2006.257.12:46:54.94#ibcon#about to read 6, iclass 21, count 0 2006.257.12:46:54.94#ibcon#read 6, iclass 21, count 0 2006.257.12:46:54.94#ibcon#end of sib2, iclass 21, count 0 2006.257.12:46:54.94#ibcon#*after write, iclass 21, count 0 2006.257.12:46:54.94#ibcon#*before return 0, iclass 21, count 0 2006.257.12:46:54.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:54.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.12:46:54.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.12:46:54.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.12:46:54.94$vck44/vblo=4,679.99 2006.257.12:46:54.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.12:46:54.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.12:46:54.94#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:54.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:54.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:54.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:54.94#ibcon#enter wrdev, iclass 23, count 0 2006.257.12:46:54.94#ibcon#first serial, iclass 23, count 0 2006.257.12:46:54.94#ibcon#enter sib2, iclass 23, count 0 2006.257.12:46:54.94#ibcon#flushed, iclass 23, count 0 2006.257.12:46:54.94#ibcon#about to write, iclass 23, count 0 2006.257.12:46:54.94#ibcon#wrote, iclass 23, count 0 2006.257.12:46:54.94#ibcon#about to read 3, iclass 23, count 0 2006.257.12:46:54.96#ibcon#read 3, iclass 23, count 0 2006.257.12:46:54.96#ibcon#about to read 4, iclass 23, count 0 2006.257.12:46:54.96#ibcon#read 4, iclass 23, count 0 2006.257.12:46:54.96#ibcon#about to read 5, iclass 23, count 0 2006.257.12:46:54.96#ibcon#read 5, iclass 23, count 0 2006.257.12:46:54.96#ibcon#about to read 6, iclass 23, count 0 2006.257.12:46:54.96#ibcon#read 6, iclass 23, count 0 2006.257.12:46:54.96#ibcon#end of sib2, iclass 23, count 0 2006.257.12:46:54.96#ibcon#*mode == 0, iclass 23, count 0 2006.257.12:46:54.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.12:46:54.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:46:54.96#ibcon#*before write, iclass 23, count 0 2006.257.12:46:54.96#ibcon#enter sib2, iclass 23, count 0 2006.257.12:46:54.96#ibcon#flushed, iclass 23, count 0 2006.257.12:46:54.96#ibcon#about to write, iclass 23, count 0 2006.257.12:46:54.96#ibcon#wrote, iclass 23, count 0 2006.257.12:46:54.96#ibcon#about to read 3, iclass 23, count 0 2006.257.12:46:55.00#ibcon#read 3, iclass 23, count 0 2006.257.12:46:55.00#ibcon#about to read 4, iclass 23, count 0 2006.257.12:46:55.00#ibcon#read 4, iclass 23, count 0 2006.257.12:46:55.00#ibcon#about to read 5, iclass 23, count 0 2006.257.12:46:55.00#ibcon#read 5, iclass 23, count 0 2006.257.12:46:55.00#ibcon#about to read 6, iclass 23, count 0 2006.257.12:46:55.00#ibcon#read 6, iclass 23, count 0 2006.257.12:46:55.00#ibcon#end of sib2, iclass 23, count 0 2006.257.12:46:55.00#ibcon#*after write, iclass 23, count 0 2006.257.12:46:55.00#ibcon#*before return 0, iclass 23, count 0 2006.257.12:46:55.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:55.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.12:46:55.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.12:46:55.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.12:46:55.00$vck44/vb=4,5 2006.257.12:46:55.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.12:46:55.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.12:46:55.00#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:55.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:55.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:55.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:55.06#ibcon#enter wrdev, iclass 25, count 2 2006.257.12:46:55.06#ibcon#first serial, iclass 25, count 2 2006.257.12:46:55.06#ibcon#enter sib2, iclass 25, count 2 2006.257.12:46:55.06#ibcon#flushed, iclass 25, count 2 2006.257.12:46:55.06#ibcon#about to write, iclass 25, count 2 2006.257.12:46:55.06#ibcon#wrote, iclass 25, count 2 2006.257.12:46:55.06#ibcon#about to read 3, iclass 25, count 2 2006.257.12:46:55.08#ibcon#read 3, iclass 25, count 2 2006.257.12:46:55.08#ibcon#about to read 4, iclass 25, count 2 2006.257.12:46:55.08#ibcon#read 4, iclass 25, count 2 2006.257.12:46:55.08#ibcon#about to read 5, iclass 25, count 2 2006.257.12:46:55.08#ibcon#read 5, iclass 25, count 2 2006.257.12:46:55.08#ibcon#about to read 6, iclass 25, count 2 2006.257.12:46:55.08#ibcon#read 6, iclass 25, count 2 2006.257.12:46:55.08#ibcon#end of sib2, iclass 25, count 2 2006.257.12:46:55.08#ibcon#*mode == 0, iclass 25, count 2 2006.257.12:46:55.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.12:46:55.08#ibcon#[27=AT04-05\r\n] 2006.257.12:46:55.08#ibcon#*before write, iclass 25, count 2 2006.257.12:46:55.08#ibcon#enter sib2, iclass 25, count 2 2006.257.12:46:55.08#ibcon#flushed, iclass 25, count 2 2006.257.12:46:55.08#ibcon#about to write, iclass 25, count 2 2006.257.12:46:55.08#ibcon#wrote, iclass 25, count 2 2006.257.12:46:55.08#ibcon#about to read 3, iclass 25, count 2 2006.257.12:46:55.11#ibcon#read 3, iclass 25, count 2 2006.257.12:46:55.11#ibcon#about to read 4, iclass 25, count 2 2006.257.12:46:55.11#ibcon#read 4, iclass 25, count 2 2006.257.12:46:55.11#ibcon#about to read 5, iclass 25, count 2 2006.257.12:46:55.11#ibcon#read 5, iclass 25, count 2 2006.257.12:46:55.11#ibcon#about to read 6, iclass 25, count 2 2006.257.12:46:55.11#ibcon#read 6, iclass 25, count 2 2006.257.12:46:55.11#ibcon#end of sib2, iclass 25, count 2 2006.257.12:46:55.11#ibcon#*after write, iclass 25, count 2 2006.257.12:46:55.11#ibcon#*before return 0, iclass 25, count 2 2006.257.12:46:55.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:55.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.12:46:55.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.12:46:55.11#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:55.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:55.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:55.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:55.23#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:46:55.23#ibcon#first serial, iclass 25, count 0 2006.257.12:46:55.23#ibcon#enter sib2, iclass 25, count 0 2006.257.12:46:55.23#ibcon#flushed, iclass 25, count 0 2006.257.12:46:55.23#ibcon#about to write, iclass 25, count 0 2006.257.12:46:55.23#ibcon#wrote, iclass 25, count 0 2006.257.12:46:55.23#ibcon#about to read 3, iclass 25, count 0 2006.257.12:46:55.25#ibcon#read 3, iclass 25, count 0 2006.257.12:46:55.25#ibcon#about to read 4, iclass 25, count 0 2006.257.12:46:55.25#ibcon#read 4, iclass 25, count 0 2006.257.12:46:55.25#ibcon#about to read 5, iclass 25, count 0 2006.257.12:46:55.25#ibcon#read 5, iclass 25, count 0 2006.257.12:46:55.25#ibcon#about to read 6, iclass 25, count 0 2006.257.12:46:55.25#ibcon#read 6, iclass 25, count 0 2006.257.12:46:55.25#ibcon#end of sib2, iclass 25, count 0 2006.257.12:46:55.25#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:46:55.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:46:55.25#ibcon#[27=USB\r\n] 2006.257.12:46:55.25#ibcon#*before write, iclass 25, count 0 2006.257.12:46:55.25#ibcon#enter sib2, iclass 25, count 0 2006.257.12:46:55.25#ibcon#flushed, iclass 25, count 0 2006.257.12:46:55.25#ibcon#about to write, iclass 25, count 0 2006.257.12:46:55.25#ibcon#wrote, iclass 25, count 0 2006.257.12:46:55.25#ibcon#about to read 3, iclass 25, count 0 2006.257.12:46:55.28#ibcon#read 3, iclass 25, count 0 2006.257.12:46:55.28#ibcon#about to read 4, iclass 25, count 0 2006.257.12:46:55.28#ibcon#read 4, iclass 25, count 0 2006.257.12:46:55.28#ibcon#about to read 5, iclass 25, count 0 2006.257.12:46:55.28#ibcon#read 5, iclass 25, count 0 2006.257.12:46:55.28#ibcon#about to read 6, iclass 25, count 0 2006.257.12:46:55.28#ibcon#read 6, iclass 25, count 0 2006.257.12:46:55.28#ibcon#end of sib2, iclass 25, count 0 2006.257.12:46:55.28#ibcon#*after write, iclass 25, count 0 2006.257.12:46:55.28#ibcon#*before return 0, iclass 25, count 0 2006.257.12:46:55.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:55.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.12:46:55.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:46:55.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:46:55.28$vck44/vblo=5,709.99 2006.257.12:46:55.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.12:46:55.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.12:46:55.28#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:55.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:55.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:55.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:55.28#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:46:55.28#ibcon#first serial, iclass 27, count 0 2006.257.12:46:55.28#ibcon#enter sib2, iclass 27, count 0 2006.257.12:46:55.28#ibcon#flushed, iclass 27, count 0 2006.257.12:46:55.28#ibcon#about to write, iclass 27, count 0 2006.257.12:46:55.28#ibcon#wrote, iclass 27, count 0 2006.257.12:46:55.28#ibcon#about to read 3, iclass 27, count 0 2006.257.12:46:55.30#ibcon#read 3, iclass 27, count 0 2006.257.12:46:55.30#ibcon#about to read 4, iclass 27, count 0 2006.257.12:46:55.30#ibcon#read 4, iclass 27, count 0 2006.257.12:46:55.30#ibcon#about to read 5, iclass 27, count 0 2006.257.12:46:55.30#ibcon#read 5, iclass 27, count 0 2006.257.12:46:55.30#ibcon#about to read 6, iclass 27, count 0 2006.257.12:46:55.30#ibcon#read 6, iclass 27, count 0 2006.257.12:46:55.30#ibcon#end of sib2, iclass 27, count 0 2006.257.12:46:55.30#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:46:55.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:46:55.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:46:55.30#ibcon#*before write, iclass 27, count 0 2006.257.12:46:55.30#ibcon#enter sib2, iclass 27, count 0 2006.257.12:46:55.30#ibcon#flushed, iclass 27, count 0 2006.257.12:46:55.30#ibcon#about to write, iclass 27, count 0 2006.257.12:46:55.30#ibcon#wrote, iclass 27, count 0 2006.257.12:46:55.30#ibcon#about to read 3, iclass 27, count 0 2006.257.12:46:55.34#ibcon#read 3, iclass 27, count 0 2006.257.12:46:55.34#ibcon#about to read 4, iclass 27, count 0 2006.257.12:46:55.34#ibcon#read 4, iclass 27, count 0 2006.257.12:46:55.34#ibcon#about to read 5, iclass 27, count 0 2006.257.12:46:55.34#ibcon#read 5, iclass 27, count 0 2006.257.12:46:55.34#ibcon#about to read 6, iclass 27, count 0 2006.257.12:46:55.34#ibcon#read 6, iclass 27, count 0 2006.257.12:46:55.34#ibcon#end of sib2, iclass 27, count 0 2006.257.12:46:55.34#ibcon#*after write, iclass 27, count 0 2006.257.12:46:55.34#ibcon#*before return 0, iclass 27, count 0 2006.257.12:46:55.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:55.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.12:46:55.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:46:55.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:46:55.34$vck44/vb=5,4 2006.257.12:46:55.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.12:46:55.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.12:46:55.34#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:55.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:55.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:55.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:55.40#ibcon#enter wrdev, iclass 29, count 2 2006.257.12:46:55.40#ibcon#first serial, iclass 29, count 2 2006.257.12:46:55.40#ibcon#enter sib2, iclass 29, count 2 2006.257.12:46:55.40#ibcon#flushed, iclass 29, count 2 2006.257.12:46:55.40#ibcon#about to write, iclass 29, count 2 2006.257.12:46:55.40#ibcon#wrote, iclass 29, count 2 2006.257.12:46:55.40#ibcon#about to read 3, iclass 29, count 2 2006.257.12:46:55.42#ibcon#read 3, iclass 29, count 2 2006.257.12:46:55.42#ibcon#about to read 4, iclass 29, count 2 2006.257.12:46:55.42#ibcon#read 4, iclass 29, count 2 2006.257.12:46:55.42#ibcon#about to read 5, iclass 29, count 2 2006.257.12:46:55.42#ibcon#read 5, iclass 29, count 2 2006.257.12:46:55.42#ibcon#about to read 6, iclass 29, count 2 2006.257.12:46:55.42#ibcon#read 6, iclass 29, count 2 2006.257.12:46:55.42#ibcon#end of sib2, iclass 29, count 2 2006.257.12:46:55.42#ibcon#*mode == 0, iclass 29, count 2 2006.257.12:46:55.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.12:46:55.42#ibcon#[27=AT05-04\r\n] 2006.257.12:46:55.42#ibcon#*before write, iclass 29, count 2 2006.257.12:46:55.42#ibcon#enter sib2, iclass 29, count 2 2006.257.12:46:55.42#ibcon#flushed, iclass 29, count 2 2006.257.12:46:55.42#ibcon#about to write, iclass 29, count 2 2006.257.12:46:55.42#ibcon#wrote, iclass 29, count 2 2006.257.12:46:55.42#ibcon#about to read 3, iclass 29, count 2 2006.257.12:46:55.45#ibcon#read 3, iclass 29, count 2 2006.257.12:46:55.45#ibcon#about to read 4, iclass 29, count 2 2006.257.12:46:55.45#ibcon#read 4, iclass 29, count 2 2006.257.12:46:55.45#ibcon#about to read 5, iclass 29, count 2 2006.257.12:46:55.45#ibcon#read 5, iclass 29, count 2 2006.257.12:46:55.45#ibcon#about to read 6, iclass 29, count 2 2006.257.12:46:55.45#ibcon#read 6, iclass 29, count 2 2006.257.12:46:55.45#ibcon#end of sib2, iclass 29, count 2 2006.257.12:46:55.45#ibcon#*after write, iclass 29, count 2 2006.257.12:46:55.45#ibcon#*before return 0, iclass 29, count 2 2006.257.12:46:55.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:55.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.12:46:55.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.12:46:55.45#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:55.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:55.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:55.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:55.57#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:46:55.57#ibcon#first serial, iclass 29, count 0 2006.257.12:46:55.57#ibcon#enter sib2, iclass 29, count 0 2006.257.12:46:55.57#ibcon#flushed, iclass 29, count 0 2006.257.12:46:55.57#ibcon#about to write, iclass 29, count 0 2006.257.12:46:55.57#ibcon#wrote, iclass 29, count 0 2006.257.12:46:55.57#ibcon#about to read 3, iclass 29, count 0 2006.257.12:46:55.59#ibcon#read 3, iclass 29, count 0 2006.257.12:46:55.59#ibcon#about to read 4, iclass 29, count 0 2006.257.12:46:55.59#ibcon#read 4, iclass 29, count 0 2006.257.12:46:55.59#ibcon#about to read 5, iclass 29, count 0 2006.257.12:46:55.59#ibcon#read 5, iclass 29, count 0 2006.257.12:46:55.59#ibcon#about to read 6, iclass 29, count 0 2006.257.12:46:55.59#ibcon#read 6, iclass 29, count 0 2006.257.12:46:55.59#ibcon#end of sib2, iclass 29, count 0 2006.257.12:46:55.59#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:46:55.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:46:55.59#ibcon#[27=USB\r\n] 2006.257.12:46:55.59#ibcon#*before write, iclass 29, count 0 2006.257.12:46:55.59#ibcon#enter sib2, iclass 29, count 0 2006.257.12:46:55.59#ibcon#flushed, iclass 29, count 0 2006.257.12:46:55.59#ibcon#about to write, iclass 29, count 0 2006.257.12:46:55.59#ibcon#wrote, iclass 29, count 0 2006.257.12:46:55.59#ibcon#about to read 3, iclass 29, count 0 2006.257.12:46:55.62#ibcon#read 3, iclass 29, count 0 2006.257.12:46:55.62#ibcon#about to read 4, iclass 29, count 0 2006.257.12:46:55.62#ibcon#read 4, iclass 29, count 0 2006.257.12:46:55.62#ibcon#about to read 5, iclass 29, count 0 2006.257.12:46:55.62#ibcon#read 5, iclass 29, count 0 2006.257.12:46:55.62#ibcon#about to read 6, iclass 29, count 0 2006.257.12:46:55.62#ibcon#read 6, iclass 29, count 0 2006.257.12:46:55.62#ibcon#end of sib2, iclass 29, count 0 2006.257.12:46:55.62#ibcon#*after write, iclass 29, count 0 2006.257.12:46:55.62#ibcon#*before return 0, iclass 29, count 0 2006.257.12:46:55.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:55.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.12:46:55.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:46:55.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:46:55.62$vck44/vblo=6,719.99 2006.257.12:46:55.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.12:46:55.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.12:46:55.62#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:55.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:55.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:55.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:55.62#ibcon#enter wrdev, iclass 31, count 0 2006.257.12:46:55.62#ibcon#first serial, iclass 31, count 0 2006.257.12:46:55.62#ibcon#enter sib2, iclass 31, count 0 2006.257.12:46:55.62#ibcon#flushed, iclass 31, count 0 2006.257.12:46:55.62#ibcon#about to write, iclass 31, count 0 2006.257.12:46:55.62#ibcon#wrote, iclass 31, count 0 2006.257.12:46:55.62#ibcon#about to read 3, iclass 31, count 0 2006.257.12:46:55.64#ibcon#read 3, iclass 31, count 0 2006.257.12:46:55.64#ibcon#about to read 4, iclass 31, count 0 2006.257.12:46:55.64#ibcon#read 4, iclass 31, count 0 2006.257.12:46:55.64#ibcon#about to read 5, iclass 31, count 0 2006.257.12:46:55.64#ibcon#read 5, iclass 31, count 0 2006.257.12:46:55.64#ibcon#about to read 6, iclass 31, count 0 2006.257.12:46:55.64#ibcon#read 6, iclass 31, count 0 2006.257.12:46:55.64#ibcon#end of sib2, iclass 31, count 0 2006.257.12:46:55.64#ibcon#*mode == 0, iclass 31, count 0 2006.257.12:46:55.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.12:46:55.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:46:55.64#ibcon#*before write, iclass 31, count 0 2006.257.12:46:55.64#ibcon#enter sib2, iclass 31, count 0 2006.257.12:46:55.64#ibcon#flushed, iclass 31, count 0 2006.257.12:46:55.64#ibcon#about to write, iclass 31, count 0 2006.257.12:46:55.64#ibcon#wrote, iclass 31, count 0 2006.257.12:46:55.64#ibcon#about to read 3, iclass 31, count 0 2006.257.12:46:55.68#ibcon#read 3, iclass 31, count 0 2006.257.12:46:55.68#ibcon#about to read 4, iclass 31, count 0 2006.257.12:46:55.68#ibcon#read 4, iclass 31, count 0 2006.257.12:46:55.68#ibcon#about to read 5, iclass 31, count 0 2006.257.12:46:55.68#ibcon#read 5, iclass 31, count 0 2006.257.12:46:55.68#ibcon#about to read 6, iclass 31, count 0 2006.257.12:46:55.68#ibcon#read 6, iclass 31, count 0 2006.257.12:46:55.68#ibcon#end of sib2, iclass 31, count 0 2006.257.12:46:55.68#ibcon#*after write, iclass 31, count 0 2006.257.12:46:55.68#ibcon#*before return 0, iclass 31, count 0 2006.257.12:46:55.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:55.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.12:46:55.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.12:46:55.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.12:46:55.68$vck44/vb=6,4 2006.257.12:46:55.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.12:46:55.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.12:46:55.68#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:55.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:55.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:55.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:55.74#ibcon#enter wrdev, iclass 33, count 2 2006.257.12:46:55.74#ibcon#first serial, iclass 33, count 2 2006.257.12:46:55.74#ibcon#enter sib2, iclass 33, count 2 2006.257.12:46:55.74#ibcon#flushed, iclass 33, count 2 2006.257.12:46:55.74#ibcon#about to write, iclass 33, count 2 2006.257.12:46:55.74#ibcon#wrote, iclass 33, count 2 2006.257.12:46:55.74#ibcon#about to read 3, iclass 33, count 2 2006.257.12:46:55.76#ibcon#read 3, iclass 33, count 2 2006.257.12:46:55.76#ibcon#about to read 4, iclass 33, count 2 2006.257.12:46:55.76#ibcon#read 4, iclass 33, count 2 2006.257.12:46:55.76#ibcon#about to read 5, iclass 33, count 2 2006.257.12:46:55.76#ibcon#read 5, iclass 33, count 2 2006.257.12:46:55.76#ibcon#about to read 6, iclass 33, count 2 2006.257.12:46:55.76#ibcon#read 6, iclass 33, count 2 2006.257.12:46:55.76#ibcon#end of sib2, iclass 33, count 2 2006.257.12:46:55.76#ibcon#*mode == 0, iclass 33, count 2 2006.257.12:46:55.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.12:46:55.76#ibcon#[27=AT06-04\r\n] 2006.257.12:46:55.76#ibcon#*before write, iclass 33, count 2 2006.257.12:46:55.76#ibcon#enter sib2, iclass 33, count 2 2006.257.12:46:55.76#ibcon#flushed, iclass 33, count 2 2006.257.12:46:55.76#ibcon#about to write, iclass 33, count 2 2006.257.12:46:55.76#ibcon#wrote, iclass 33, count 2 2006.257.12:46:55.76#ibcon#about to read 3, iclass 33, count 2 2006.257.12:46:55.79#ibcon#read 3, iclass 33, count 2 2006.257.12:46:55.79#ibcon#about to read 4, iclass 33, count 2 2006.257.12:46:55.79#ibcon#read 4, iclass 33, count 2 2006.257.12:46:55.79#ibcon#about to read 5, iclass 33, count 2 2006.257.12:46:55.79#ibcon#read 5, iclass 33, count 2 2006.257.12:46:55.79#ibcon#about to read 6, iclass 33, count 2 2006.257.12:46:55.79#ibcon#read 6, iclass 33, count 2 2006.257.12:46:55.79#ibcon#end of sib2, iclass 33, count 2 2006.257.12:46:55.79#ibcon#*after write, iclass 33, count 2 2006.257.12:46:55.79#ibcon#*before return 0, iclass 33, count 2 2006.257.12:46:55.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:55.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.12:46:55.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.12:46:55.79#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:55.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:55.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:55.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:55.91#ibcon#enter wrdev, iclass 33, count 0 2006.257.12:46:55.91#ibcon#first serial, iclass 33, count 0 2006.257.12:46:55.91#ibcon#enter sib2, iclass 33, count 0 2006.257.12:46:55.91#ibcon#flushed, iclass 33, count 0 2006.257.12:46:55.91#ibcon#about to write, iclass 33, count 0 2006.257.12:46:55.91#ibcon#wrote, iclass 33, count 0 2006.257.12:46:55.91#ibcon#about to read 3, iclass 33, count 0 2006.257.12:46:55.93#ibcon#read 3, iclass 33, count 0 2006.257.12:46:55.93#ibcon#about to read 4, iclass 33, count 0 2006.257.12:46:55.93#ibcon#read 4, iclass 33, count 0 2006.257.12:46:55.93#ibcon#about to read 5, iclass 33, count 0 2006.257.12:46:55.93#ibcon#read 5, iclass 33, count 0 2006.257.12:46:55.93#ibcon#about to read 6, iclass 33, count 0 2006.257.12:46:55.93#ibcon#read 6, iclass 33, count 0 2006.257.12:46:55.93#ibcon#end of sib2, iclass 33, count 0 2006.257.12:46:55.93#ibcon#*mode == 0, iclass 33, count 0 2006.257.12:46:55.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.12:46:55.93#ibcon#[27=USB\r\n] 2006.257.12:46:55.93#ibcon#*before write, iclass 33, count 0 2006.257.12:46:55.93#ibcon#enter sib2, iclass 33, count 0 2006.257.12:46:55.93#ibcon#flushed, iclass 33, count 0 2006.257.12:46:55.93#ibcon#about to write, iclass 33, count 0 2006.257.12:46:55.93#ibcon#wrote, iclass 33, count 0 2006.257.12:46:55.93#ibcon#about to read 3, iclass 33, count 0 2006.257.12:46:55.96#ibcon#read 3, iclass 33, count 0 2006.257.12:46:55.96#ibcon#about to read 4, iclass 33, count 0 2006.257.12:46:55.96#ibcon#read 4, iclass 33, count 0 2006.257.12:46:55.96#ibcon#about to read 5, iclass 33, count 0 2006.257.12:46:55.96#ibcon#read 5, iclass 33, count 0 2006.257.12:46:55.96#ibcon#about to read 6, iclass 33, count 0 2006.257.12:46:55.96#ibcon#read 6, iclass 33, count 0 2006.257.12:46:55.96#ibcon#end of sib2, iclass 33, count 0 2006.257.12:46:55.96#ibcon#*after write, iclass 33, count 0 2006.257.12:46:55.96#ibcon#*before return 0, iclass 33, count 0 2006.257.12:46:55.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:55.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.12:46:55.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.12:46:55.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.12:46:55.96$vck44/vblo=7,734.99 2006.257.12:46:55.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.12:46:55.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.12:46:55.96#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:55.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:55.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:55.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:55.96#ibcon#enter wrdev, iclass 35, count 0 2006.257.12:46:55.96#ibcon#first serial, iclass 35, count 0 2006.257.12:46:55.96#ibcon#enter sib2, iclass 35, count 0 2006.257.12:46:55.96#ibcon#flushed, iclass 35, count 0 2006.257.12:46:55.96#ibcon#about to write, iclass 35, count 0 2006.257.12:46:55.96#ibcon#wrote, iclass 35, count 0 2006.257.12:46:55.96#ibcon#about to read 3, iclass 35, count 0 2006.257.12:46:55.98#ibcon#read 3, iclass 35, count 0 2006.257.12:46:55.98#ibcon#about to read 4, iclass 35, count 0 2006.257.12:46:55.98#ibcon#read 4, iclass 35, count 0 2006.257.12:46:55.98#ibcon#about to read 5, iclass 35, count 0 2006.257.12:46:55.98#ibcon#read 5, iclass 35, count 0 2006.257.12:46:55.98#ibcon#about to read 6, iclass 35, count 0 2006.257.12:46:55.98#ibcon#read 6, iclass 35, count 0 2006.257.12:46:55.98#ibcon#end of sib2, iclass 35, count 0 2006.257.12:46:55.98#ibcon#*mode == 0, iclass 35, count 0 2006.257.12:46:55.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.12:46:55.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:46:55.98#ibcon#*before write, iclass 35, count 0 2006.257.12:46:55.98#ibcon#enter sib2, iclass 35, count 0 2006.257.12:46:55.98#ibcon#flushed, iclass 35, count 0 2006.257.12:46:55.98#ibcon#about to write, iclass 35, count 0 2006.257.12:46:55.98#ibcon#wrote, iclass 35, count 0 2006.257.12:46:55.98#ibcon#about to read 3, iclass 35, count 0 2006.257.12:46:56.02#ibcon#read 3, iclass 35, count 0 2006.257.12:46:56.02#ibcon#about to read 4, iclass 35, count 0 2006.257.12:46:56.02#ibcon#read 4, iclass 35, count 0 2006.257.12:46:56.02#ibcon#about to read 5, iclass 35, count 0 2006.257.12:46:56.02#ibcon#read 5, iclass 35, count 0 2006.257.12:46:56.02#ibcon#about to read 6, iclass 35, count 0 2006.257.12:46:56.02#ibcon#read 6, iclass 35, count 0 2006.257.12:46:56.02#ibcon#end of sib2, iclass 35, count 0 2006.257.12:46:56.02#ibcon#*after write, iclass 35, count 0 2006.257.12:46:56.02#ibcon#*before return 0, iclass 35, count 0 2006.257.12:46:56.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:56.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.12:46:56.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.12:46:56.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.12:46:56.02$vck44/vb=7,4 2006.257.12:46:56.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.12:46:56.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.12:46:56.02#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:56.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:56.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:56.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:56.08#ibcon#enter wrdev, iclass 37, count 2 2006.257.12:46:56.08#ibcon#first serial, iclass 37, count 2 2006.257.12:46:56.08#ibcon#enter sib2, iclass 37, count 2 2006.257.12:46:56.08#ibcon#flushed, iclass 37, count 2 2006.257.12:46:56.08#ibcon#about to write, iclass 37, count 2 2006.257.12:46:56.08#ibcon#wrote, iclass 37, count 2 2006.257.12:46:56.08#ibcon#about to read 3, iclass 37, count 2 2006.257.12:46:56.10#ibcon#read 3, iclass 37, count 2 2006.257.12:46:56.10#ibcon#about to read 4, iclass 37, count 2 2006.257.12:46:56.10#ibcon#read 4, iclass 37, count 2 2006.257.12:46:56.10#ibcon#about to read 5, iclass 37, count 2 2006.257.12:46:56.10#ibcon#read 5, iclass 37, count 2 2006.257.12:46:56.10#ibcon#about to read 6, iclass 37, count 2 2006.257.12:46:56.10#ibcon#read 6, iclass 37, count 2 2006.257.12:46:56.10#ibcon#end of sib2, iclass 37, count 2 2006.257.12:46:56.10#ibcon#*mode == 0, iclass 37, count 2 2006.257.12:46:56.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.12:46:56.10#ibcon#[27=AT07-04\r\n] 2006.257.12:46:56.10#ibcon#*before write, iclass 37, count 2 2006.257.12:46:56.10#ibcon#enter sib2, iclass 37, count 2 2006.257.12:46:56.10#ibcon#flushed, iclass 37, count 2 2006.257.12:46:56.10#ibcon#about to write, iclass 37, count 2 2006.257.12:46:56.10#ibcon#wrote, iclass 37, count 2 2006.257.12:46:56.10#ibcon#about to read 3, iclass 37, count 2 2006.257.12:46:56.13#ibcon#read 3, iclass 37, count 2 2006.257.12:46:56.13#ibcon#about to read 4, iclass 37, count 2 2006.257.12:46:56.13#ibcon#read 4, iclass 37, count 2 2006.257.12:46:56.13#ibcon#about to read 5, iclass 37, count 2 2006.257.12:46:56.13#ibcon#read 5, iclass 37, count 2 2006.257.12:46:56.13#ibcon#about to read 6, iclass 37, count 2 2006.257.12:46:56.13#ibcon#read 6, iclass 37, count 2 2006.257.12:46:56.13#ibcon#end of sib2, iclass 37, count 2 2006.257.12:46:56.13#ibcon#*after write, iclass 37, count 2 2006.257.12:46:56.13#ibcon#*before return 0, iclass 37, count 2 2006.257.12:46:56.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:56.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.12:46:56.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.12:46:56.13#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:56.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:56.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:56.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:56.25#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:46:56.25#ibcon#first serial, iclass 37, count 0 2006.257.12:46:56.25#ibcon#enter sib2, iclass 37, count 0 2006.257.12:46:56.25#ibcon#flushed, iclass 37, count 0 2006.257.12:46:56.25#ibcon#about to write, iclass 37, count 0 2006.257.12:46:56.25#ibcon#wrote, iclass 37, count 0 2006.257.12:46:56.25#ibcon#about to read 3, iclass 37, count 0 2006.257.12:46:56.27#ibcon#read 3, iclass 37, count 0 2006.257.12:46:56.27#ibcon#about to read 4, iclass 37, count 0 2006.257.12:46:56.27#ibcon#read 4, iclass 37, count 0 2006.257.12:46:56.27#ibcon#about to read 5, iclass 37, count 0 2006.257.12:46:56.27#ibcon#read 5, iclass 37, count 0 2006.257.12:46:56.27#ibcon#about to read 6, iclass 37, count 0 2006.257.12:46:56.27#ibcon#read 6, iclass 37, count 0 2006.257.12:46:56.27#ibcon#end of sib2, iclass 37, count 0 2006.257.12:46:56.27#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:46:56.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:46:56.27#ibcon#[27=USB\r\n] 2006.257.12:46:56.27#ibcon#*before write, iclass 37, count 0 2006.257.12:46:56.27#ibcon#enter sib2, iclass 37, count 0 2006.257.12:46:56.27#ibcon#flushed, iclass 37, count 0 2006.257.12:46:56.27#ibcon#about to write, iclass 37, count 0 2006.257.12:46:56.27#ibcon#wrote, iclass 37, count 0 2006.257.12:46:56.27#ibcon#about to read 3, iclass 37, count 0 2006.257.12:46:56.30#ibcon#read 3, iclass 37, count 0 2006.257.12:46:56.30#ibcon#about to read 4, iclass 37, count 0 2006.257.12:46:56.30#ibcon#read 4, iclass 37, count 0 2006.257.12:46:56.30#ibcon#about to read 5, iclass 37, count 0 2006.257.12:46:56.30#ibcon#read 5, iclass 37, count 0 2006.257.12:46:56.30#ibcon#about to read 6, iclass 37, count 0 2006.257.12:46:56.30#ibcon#read 6, iclass 37, count 0 2006.257.12:46:56.30#ibcon#end of sib2, iclass 37, count 0 2006.257.12:46:56.30#ibcon#*after write, iclass 37, count 0 2006.257.12:46:56.30#ibcon#*before return 0, iclass 37, count 0 2006.257.12:46:56.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:56.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.12:46:56.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:46:56.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:46:56.30$vck44/vblo=8,744.99 2006.257.12:46:56.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.12:46:56.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.12:46:56.30#ibcon#ireg 17 cls_cnt 0 2006.257.12:46:56.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:56.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:56.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:56.30#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:46:56.30#ibcon#first serial, iclass 39, count 0 2006.257.12:46:56.30#ibcon#enter sib2, iclass 39, count 0 2006.257.12:46:56.30#ibcon#flushed, iclass 39, count 0 2006.257.12:46:56.30#ibcon#about to write, iclass 39, count 0 2006.257.12:46:56.30#ibcon#wrote, iclass 39, count 0 2006.257.12:46:56.30#ibcon#about to read 3, iclass 39, count 0 2006.257.12:46:56.32#ibcon#read 3, iclass 39, count 0 2006.257.12:46:56.32#ibcon#about to read 4, iclass 39, count 0 2006.257.12:46:56.32#ibcon#read 4, iclass 39, count 0 2006.257.12:46:56.32#ibcon#about to read 5, iclass 39, count 0 2006.257.12:46:56.32#ibcon#read 5, iclass 39, count 0 2006.257.12:46:56.32#ibcon#about to read 6, iclass 39, count 0 2006.257.12:46:56.32#ibcon#read 6, iclass 39, count 0 2006.257.12:46:56.32#ibcon#end of sib2, iclass 39, count 0 2006.257.12:46:56.32#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:46:56.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:46:56.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:46:56.32#ibcon#*before write, iclass 39, count 0 2006.257.12:46:56.32#ibcon#enter sib2, iclass 39, count 0 2006.257.12:46:56.32#ibcon#flushed, iclass 39, count 0 2006.257.12:46:56.32#ibcon#about to write, iclass 39, count 0 2006.257.12:46:56.32#ibcon#wrote, iclass 39, count 0 2006.257.12:46:56.32#ibcon#about to read 3, iclass 39, count 0 2006.257.12:46:56.36#ibcon#read 3, iclass 39, count 0 2006.257.12:46:56.36#ibcon#about to read 4, iclass 39, count 0 2006.257.12:46:56.36#ibcon#read 4, iclass 39, count 0 2006.257.12:46:56.36#ibcon#about to read 5, iclass 39, count 0 2006.257.12:46:56.36#ibcon#read 5, iclass 39, count 0 2006.257.12:46:56.36#ibcon#about to read 6, iclass 39, count 0 2006.257.12:46:56.36#ibcon#read 6, iclass 39, count 0 2006.257.12:46:56.36#ibcon#end of sib2, iclass 39, count 0 2006.257.12:46:56.36#ibcon#*after write, iclass 39, count 0 2006.257.12:46:56.36#ibcon#*before return 0, iclass 39, count 0 2006.257.12:46:56.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:56.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.12:46:56.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:46:56.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:46:56.36$vck44/vb=8,4 2006.257.12:46:56.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.12:46:56.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.12:46:56.36#ibcon#ireg 11 cls_cnt 2 2006.257.12:46:56.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:56.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:56.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:56.42#ibcon#enter wrdev, iclass 3, count 2 2006.257.12:46:56.42#ibcon#first serial, iclass 3, count 2 2006.257.12:46:56.42#ibcon#enter sib2, iclass 3, count 2 2006.257.12:46:56.42#ibcon#flushed, iclass 3, count 2 2006.257.12:46:56.42#ibcon#about to write, iclass 3, count 2 2006.257.12:46:56.42#ibcon#wrote, iclass 3, count 2 2006.257.12:46:56.42#ibcon#about to read 3, iclass 3, count 2 2006.257.12:46:56.44#ibcon#read 3, iclass 3, count 2 2006.257.12:46:56.44#ibcon#about to read 4, iclass 3, count 2 2006.257.12:46:56.44#ibcon#read 4, iclass 3, count 2 2006.257.12:46:56.44#ibcon#about to read 5, iclass 3, count 2 2006.257.12:46:56.44#ibcon#read 5, iclass 3, count 2 2006.257.12:46:56.44#ibcon#about to read 6, iclass 3, count 2 2006.257.12:46:56.44#ibcon#read 6, iclass 3, count 2 2006.257.12:46:56.44#ibcon#end of sib2, iclass 3, count 2 2006.257.12:46:56.44#ibcon#*mode == 0, iclass 3, count 2 2006.257.12:46:56.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.12:46:56.44#ibcon#[27=AT08-04\r\n] 2006.257.12:46:56.44#ibcon#*before write, iclass 3, count 2 2006.257.12:46:56.44#ibcon#enter sib2, iclass 3, count 2 2006.257.12:46:56.44#ibcon#flushed, iclass 3, count 2 2006.257.12:46:56.44#ibcon#about to write, iclass 3, count 2 2006.257.12:46:56.44#ibcon#wrote, iclass 3, count 2 2006.257.12:46:56.44#ibcon#about to read 3, iclass 3, count 2 2006.257.12:46:56.47#ibcon#read 3, iclass 3, count 2 2006.257.12:46:56.47#ibcon#about to read 4, iclass 3, count 2 2006.257.12:46:56.47#ibcon#read 4, iclass 3, count 2 2006.257.12:46:56.47#ibcon#about to read 5, iclass 3, count 2 2006.257.12:46:56.47#ibcon#read 5, iclass 3, count 2 2006.257.12:46:56.47#ibcon#about to read 6, iclass 3, count 2 2006.257.12:46:56.47#ibcon#read 6, iclass 3, count 2 2006.257.12:46:56.47#ibcon#end of sib2, iclass 3, count 2 2006.257.12:46:56.47#ibcon#*after write, iclass 3, count 2 2006.257.12:46:56.47#ibcon#*before return 0, iclass 3, count 2 2006.257.12:46:56.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:56.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.12:46:56.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.12:46:56.47#ibcon#ireg 7 cls_cnt 0 2006.257.12:46:56.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:56.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:56.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:56.59#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:46:56.59#ibcon#first serial, iclass 3, count 0 2006.257.12:46:56.59#ibcon#enter sib2, iclass 3, count 0 2006.257.12:46:56.59#ibcon#flushed, iclass 3, count 0 2006.257.12:46:56.59#ibcon#about to write, iclass 3, count 0 2006.257.12:46:56.59#ibcon#wrote, iclass 3, count 0 2006.257.12:46:56.59#ibcon#about to read 3, iclass 3, count 0 2006.257.12:46:56.61#ibcon#read 3, iclass 3, count 0 2006.257.12:46:56.61#ibcon#about to read 4, iclass 3, count 0 2006.257.12:46:56.61#ibcon#read 4, iclass 3, count 0 2006.257.12:46:56.61#ibcon#about to read 5, iclass 3, count 0 2006.257.12:46:56.61#ibcon#read 5, iclass 3, count 0 2006.257.12:46:56.61#ibcon#about to read 6, iclass 3, count 0 2006.257.12:46:56.61#ibcon#read 6, iclass 3, count 0 2006.257.12:46:56.61#ibcon#end of sib2, iclass 3, count 0 2006.257.12:46:56.61#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:46:56.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:46:56.61#ibcon#[27=USB\r\n] 2006.257.12:46:56.61#ibcon#*before write, iclass 3, count 0 2006.257.12:46:56.61#ibcon#enter sib2, iclass 3, count 0 2006.257.12:46:56.61#ibcon#flushed, iclass 3, count 0 2006.257.12:46:56.61#ibcon#about to write, iclass 3, count 0 2006.257.12:46:56.61#ibcon#wrote, iclass 3, count 0 2006.257.12:46:56.61#ibcon#about to read 3, iclass 3, count 0 2006.257.12:46:56.64#ibcon#read 3, iclass 3, count 0 2006.257.12:46:56.64#ibcon#about to read 4, iclass 3, count 0 2006.257.12:46:56.64#ibcon#read 4, iclass 3, count 0 2006.257.12:46:56.64#ibcon#about to read 5, iclass 3, count 0 2006.257.12:46:56.64#ibcon#read 5, iclass 3, count 0 2006.257.12:46:56.64#ibcon#about to read 6, iclass 3, count 0 2006.257.12:46:56.64#ibcon#read 6, iclass 3, count 0 2006.257.12:46:56.64#ibcon#end of sib2, iclass 3, count 0 2006.257.12:46:56.64#ibcon#*after write, iclass 3, count 0 2006.257.12:46:56.64#ibcon#*before return 0, iclass 3, count 0 2006.257.12:46:56.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:56.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.12:46:56.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:46:56.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:46:56.64$vck44/vabw=wide 2006.257.12:46:56.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.12:46:56.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.12:46:56.64#ibcon#ireg 8 cls_cnt 0 2006.257.12:46:56.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:56.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:56.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:56.64#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:46:56.64#ibcon#first serial, iclass 5, count 0 2006.257.12:46:56.64#ibcon#enter sib2, iclass 5, count 0 2006.257.12:46:56.64#ibcon#flushed, iclass 5, count 0 2006.257.12:46:56.64#ibcon#about to write, iclass 5, count 0 2006.257.12:46:56.64#ibcon#wrote, iclass 5, count 0 2006.257.12:46:56.64#ibcon#about to read 3, iclass 5, count 0 2006.257.12:46:56.66#ibcon#read 3, iclass 5, count 0 2006.257.12:46:56.66#ibcon#about to read 4, iclass 5, count 0 2006.257.12:46:56.66#ibcon#read 4, iclass 5, count 0 2006.257.12:46:56.66#ibcon#about to read 5, iclass 5, count 0 2006.257.12:46:56.66#ibcon#read 5, iclass 5, count 0 2006.257.12:46:56.66#ibcon#about to read 6, iclass 5, count 0 2006.257.12:46:56.66#ibcon#read 6, iclass 5, count 0 2006.257.12:46:56.66#ibcon#end of sib2, iclass 5, count 0 2006.257.12:46:56.66#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:46:56.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:46:56.66#ibcon#[25=BW32\r\n] 2006.257.12:46:56.66#ibcon#*before write, iclass 5, count 0 2006.257.12:46:56.66#ibcon#enter sib2, iclass 5, count 0 2006.257.12:46:56.66#ibcon#flushed, iclass 5, count 0 2006.257.12:46:56.66#ibcon#about to write, iclass 5, count 0 2006.257.12:46:56.66#ibcon#wrote, iclass 5, count 0 2006.257.12:46:56.66#ibcon#about to read 3, iclass 5, count 0 2006.257.12:46:56.69#ibcon#read 3, iclass 5, count 0 2006.257.12:46:56.69#ibcon#about to read 4, iclass 5, count 0 2006.257.12:46:56.69#ibcon#read 4, iclass 5, count 0 2006.257.12:46:56.69#ibcon#about to read 5, iclass 5, count 0 2006.257.12:46:56.69#ibcon#read 5, iclass 5, count 0 2006.257.12:46:56.69#ibcon#about to read 6, iclass 5, count 0 2006.257.12:46:56.69#ibcon#read 6, iclass 5, count 0 2006.257.12:46:56.69#ibcon#end of sib2, iclass 5, count 0 2006.257.12:46:56.69#ibcon#*after write, iclass 5, count 0 2006.257.12:46:56.69#ibcon#*before return 0, iclass 5, count 0 2006.257.12:46:56.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:56.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:46:56.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:46:56.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:46:56.69$vck44/vbbw=wide 2006.257.12:46:56.69#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.12:46:56.69#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.12:46:56.69#ibcon#ireg 8 cls_cnt 0 2006.257.12:46:56.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:46:56.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:46:56.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:46:56.76#ibcon#enter wrdev, iclass 7, count 0 2006.257.12:46:56.76#ibcon#first serial, iclass 7, count 0 2006.257.12:46:56.76#ibcon#enter sib2, iclass 7, count 0 2006.257.12:46:56.76#ibcon#flushed, iclass 7, count 0 2006.257.12:46:56.76#ibcon#about to write, iclass 7, count 0 2006.257.12:46:56.76#ibcon#wrote, iclass 7, count 0 2006.257.12:46:56.76#ibcon#about to read 3, iclass 7, count 0 2006.257.12:46:56.78#ibcon#read 3, iclass 7, count 0 2006.257.12:46:56.78#ibcon#about to read 4, iclass 7, count 0 2006.257.12:46:56.78#ibcon#read 4, iclass 7, count 0 2006.257.12:46:56.78#ibcon#about to read 5, iclass 7, count 0 2006.257.12:46:56.78#ibcon#read 5, iclass 7, count 0 2006.257.12:46:56.78#ibcon#about to read 6, iclass 7, count 0 2006.257.12:46:56.78#ibcon#read 6, iclass 7, count 0 2006.257.12:46:56.78#ibcon#end of sib2, iclass 7, count 0 2006.257.12:46:56.78#ibcon#*mode == 0, iclass 7, count 0 2006.257.12:46:56.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.12:46:56.78#ibcon#[27=BW32\r\n] 2006.257.12:46:56.78#ibcon#*before write, iclass 7, count 0 2006.257.12:46:56.78#ibcon#enter sib2, iclass 7, count 0 2006.257.12:46:56.78#ibcon#flushed, iclass 7, count 0 2006.257.12:46:56.78#ibcon#about to write, iclass 7, count 0 2006.257.12:46:56.78#ibcon#wrote, iclass 7, count 0 2006.257.12:46:56.78#ibcon#about to read 3, iclass 7, count 0 2006.257.12:46:56.81#ibcon#read 3, iclass 7, count 0 2006.257.12:46:56.81#ibcon#about to read 4, iclass 7, count 0 2006.257.12:46:56.81#ibcon#read 4, iclass 7, count 0 2006.257.12:46:56.81#ibcon#about to read 5, iclass 7, count 0 2006.257.12:46:56.81#ibcon#read 5, iclass 7, count 0 2006.257.12:46:56.81#ibcon#about to read 6, iclass 7, count 0 2006.257.12:46:56.81#ibcon#read 6, iclass 7, count 0 2006.257.12:46:56.81#ibcon#end of sib2, iclass 7, count 0 2006.257.12:46:56.81#ibcon#*after write, iclass 7, count 0 2006.257.12:46:56.81#ibcon#*before return 0, iclass 7, count 0 2006.257.12:46:56.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:46:56.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:46:56.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.12:46:56.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.12:46:56.81$setupk4/ifdk4 2006.257.12:46:56.81$ifdk4/lo= 2006.257.12:46:56.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:46:56.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:46:56.81$ifdk4/patch= 2006.257.12:46:56.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:46:56.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:46:56.81$setupk4/!*+20s 2006.257.12:46:59.35#abcon#<5=/14 1.6 3.9 17.86 961013.9\r\n> 2006.257.12:46:59.37#abcon#{5=INTERFACE CLEAR} 2006.257.12:46:59.43#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:47:09.52#abcon#<5=/14 1.6 3.9 17.86 961013.9\r\n> 2006.257.12:47:09.54#abcon#{5=INTERFACE CLEAR} 2006.257.12:47:09.60#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:47:11.32$setupk4/"tpicd 2006.257.12:47:11.32$setupk4/echo=off 2006.257.12:47:11.32$setupk4/xlog=off 2006.257.12:47:11.32:!2006.257.12:49:19 2006.257.12:47:21.13#trakl#Source acquired 2006.257.12:47:22.13#flagr#flagr/antenna,acquired 2006.257.12:49:19.00:preob 2006.257.12:49:20.14/onsource/TRACKING 2006.257.12:49:20.14:!2006.257.12:49:29 2006.257.12:49:29.00:"tape 2006.257.12:49:29.00:"st=record 2006.257.12:49:29.00:data_valid=on 2006.257.12:49:29.00:midob 2006.257.12:49:29.14/onsource/TRACKING 2006.257.12:49:29.14/wx/17.84,1013.8,96 2006.257.12:49:29.20/cable/+6.4800E-03 2006.257.12:49:30.29/va/01,08,usb,yes,32,34 2006.257.12:49:30.29/va/02,07,usb,yes,34,35 2006.257.12:49:30.29/va/03,08,usb,yes,31,33 2006.257.12:49:30.29/va/04,07,usb,yes,36,37 2006.257.12:49:30.29/va/05,04,usb,yes,32,32 2006.257.12:49:30.29/va/06,04,usb,yes,35,35 2006.257.12:49:30.29/va/07,04,usb,yes,36,37 2006.257.12:49:30.29/va/08,04,usb,yes,30,37 2006.257.12:49:30.52/valo/01,524.99,yes,locked 2006.257.12:49:30.52/valo/02,534.99,yes,locked 2006.257.12:49:30.52/valo/03,564.99,yes,locked 2006.257.12:49:30.52/valo/04,624.99,yes,locked 2006.257.12:49:30.52/valo/05,734.99,yes,locked 2006.257.12:49:30.52/valo/06,814.99,yes,locked 2006.257.12:49:30.52/valo/07,864.99,yes,locked 2006.257.12:49:30.52/valo/08,884.99,yes,locked 2006.257.12:49:31.61/vb/01,04,usb,yes,31,29 2006.257.12:49:31.61/vb/02,05,usb,yes,30,29 2006.257.12:49:31.61/vb/03,04,usb,yes,31,34 2006.257.12:49:31.61/vb/04,05,usb,yes,31,30 2006.257.12:49:31.61/vb/05,04,usb,yes,27,30 2006.257.12:49:31.61/vb/06,04,usb,yes,32,28 2006.257.12:49:31.61/vb/07,04,usb,yes,32,31 2006.257.12:49:31.61/vb/08,04,usb,yes,29,32 2006.257.12:49:31.85/vblo/01,629.99,yes,locked 2006.257.12:49:31.85/vblo/02,634.99,yes,locked 2006.257.12:49:31.85/vblo/03,649.99,yes,locked 2006.257.12:49:31.85/vblo/04,679.99,yes,locked 2006.257.12:49:31.85/vblo/05,709.99,yes,locked 2006.257.12:49:31.85/vblo/06,719.99,yes,locked 2006.257.12:49:31.85/vblo/07,734.99,yes,locked 2006.257.12:49:31.85/vblo/08,744.99,yes,locked 2006.257.12:49:32.00/vabw/8 2006.257.12:49:32.15/vbbw/8 2006.257.12:49:32.36/xfe/off,on,15.5 2006.257.12:49:32.73/ifatt/23,28,28,28 2006.257.12:49:33.07/fmout-gps/S +4.58E-07 2006.257.12:49:33.11:!2006.257.12:50:09 2006.257.12:50:09.01:data_valid=off 2006.257.12:50:09.02:"et 2006.257.12:50:09.02:!+3s 2006.257.12:50:12.03:"tape 2006.257.12:50:12.04:postob 2006.257.12:50:12.15/cable/+6.4804E-03 2006.257.12:50:12.16/wx/17.84,1013.8,96 2006.257.12:50:12.21/fmout-gps/S +4.58E-07 2006.257.12:50:12.22:scan_name=257-1251,jd0609,60 2006.257.12:50:12.22:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.12:50:14.14#flagr#flagr/antenna,new-source 2006.257.12:50:14.15:checkk5 2006.257.12:50:14.59/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:50:14.98/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:50:15.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:50:15.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:50:16.15/chk_obsdata//k5ts1/T2571249??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.12:50:16.55/chk_obsdata//k5ts2/T2571249??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.12:50:16.94/chk_obsdata//k5ts3/T2571249??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.12:50:17.34/chk_obsdata//k5ts4/T2571249??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.12:50:18.07/k5log//k5ts1_log_newline 2006.257.12:50:18.78/k5log//k5ts2_log_newline 2006.257.12:50:19.51/k5log//k5ts3_log_newline 2006.257.12:50:20.21/k5log//k5ts4_log_newline 2006.257.12:50:20.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:50:20.24:setupk4=1 2006.257.12:50:20.24$setupk4/echo=on 2006.257.12:50:20.24$setupk4/pcalon 2006.257.12:50:20.24$pcalon/"no phase cal control is implemented here 2006.257.12:50:20.24$setupk4/"tpicd=stop 2006.257.12:50:20.24$setupk4/"rec=synch_on 2006.257.12:50:20.24$setupk4/"rec_mode=128 2006.257.12:50:20.24$setupk4/!* 2006.257.12:50:20.24$setupk4/recpk4 2006.257.12:50:20.24$recpk4/recpatch= 2006.257.12:50:20.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:50:20.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:50:20.24$setupk4/vck44 2006.257.12:50:20.24$vck44/valo=1,524.99 2006.257.12:50:20.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.12:50:20.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.12:50:20.25#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:20.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:20.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:20.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:20.25#ibcon#enter wrdev, iclass 22, count 0 2006.257.12:50:20.25#ibcon#first serial, iclass 22, count 0 2006.257.12:50:20.25#ibcon#enter sib2, iclass 22, count 0 2006.257.12:50:20.25#ibcon#flushed, iclass 22, count 0 2006.257.12:50:20.25#ibcon#about to write, iclass 22, count 0 2006.257.12:50:20.25#ibcon#wrote, iclass 22, count 0 2006.257.12:50:20.25#ibcon#about to read 3, iclass 22, count 0 2006.257.12:50:20.26#ibcon#read 3, iclass 22, count 0 2006.257.12:50:20.26#ibcon#about to read 4, iclass 22, count 0 2006.257.12:50:20.26#ibcon#read 4, iclass 22, count 0 2006.257.12:50:20.26#ibcon#about to read 5, iclass 22, count 0 2006.257.12:50:20.26#ibcon#read 5, iclass 22, count 0 2006.257.12:50:20.26#ibcon#about to read 6, iclass 22, count 0 2006.257.12:50:20.26#ibcon#read 6, iclass 22, count 0 2006.257.12:50:20.26#ibcon#end of sib2, iclass 22, count 0 2006.257.12:50:20.26#ibcon#*mode == 0, iclass 22, count 0 2006.257.12:50:20.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.12:50:20.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:50:20.26#ibcon#*before write, iclass 22, count 0 2006.257.12:50:20.26#ibcon#enter sib2, iclass 22, count 0 2006.257.12:50:20.26#ibcon#flushed, iclass 22, count 0 2006.257.12:50:20.26#ibcon#about to write, iclass 22, count 0 2006.257.12:50:20.26#ibcon#wrote, iclass 22, count 0 2006.257.12:50:20.26#ibcon#about to read 3, iclass 22, count 0 2006.257.12:50:20.31#ibcon#read 3, iclass 22, count 0 2006.257.12:50:20.31#ibcon#about to read 4, iclass 22, count 0 2006.257.12:50:20.31#ibcon#read 4, iclass 22, count 0 2006.257.12:50:20.31#ibcon#about to read 5, iclass 22, count 0 2006.257.12:50:20.31#ibcon#read 5, iclass 22, count 0 2006.257.12:50:20.31#ibcon#about to read 6, iclass 22, count 0 2006.257.12:50:20.31#ibcon#read 6, iclass 22, count 0 2006.257.12:50:20.31#ibcon#end of sib2, iclass 22, count 0 2006.257.12:50:20.31#ibcon#*after write, iclass 22, count 0 2006.257.12:50:20.31#ibcon#*before return 0, iclass 22, count 0 2006.257.12:50:20.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:20.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:20.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.12:50:20.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.12:50:20.31$vck44/va=1,8 2006.257.12:50:20.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.12:50:20.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.12:50:20.31#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:20.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:20.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:20.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:20.31#ibcon#enter wrdev, iclass 24, count 2 2006.257.12:50:20.31#ibcon#first serial, iclass 24, count 2 2006.257.12:50:20.31#ibcon#enter sib2, iclass 24, count 2 2006.257.12:50:20.31#ibcon#flushed, iclass 24, count 2 2006.257.12:50:20.31#ibcon#about to write, iclass 24, count 2 2006.257.12:50:20.31#ibcon#wrote, iclass 24, count 2 2006.257.12:50:20.31#ibcon#about to read 3, iclass 24, count 2 2006.257.12:50:20.33#ibcon#read 3, iclass 24, count 2 2006.257.12:50:20.33#ibcon#about to read 4, iclass 24, count 2 2006.257.12:50:20.33#ibcon#read 4, iclass 24, count 2 2006.257.12:50:20.33#ibcon#about to read 5, iclass 24, count 2 2006.257.12:50:20.33#ibcon#read 5, iclass 24, count 2 2006.257.12:50:20.33#ibcon#about to read 6, iclass 24, count 2 2006.257.12:50:20.33#ibcon#read 6, iclass 24, count 2 2006.257.12:50:20.33#ibcon#end of sib2, iclass 24, count 2 2006.257.12:50:20.33#ibcon#*mode == 0, iclass 24, count 2 2006.257.12:50:20.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.12:50:20.33#ibcon#[25=AT01-08\r\n] 2006.257.12:50:20.33#ibcon#*before write, iclass 24, count 2 2006.257.12:50:20.33#ibcon#enter sib2, iclass 24, count 2 2006.257.12:50:20.33#ibcon#flushed, iclass 24, count 2 2006.257.12:50:20.33#ibcon#about to write, iclass 24, count 2 2006.257.12:50:20.33#ibcon#wrote, iclass 24, count 2 2006.257.12:50:20.33#ibcon#about to read 3, iclass 24, count 2 2006.257.12:50:20.36#ibcon#read 3, iclass 24, count 2 2006.257.12:50:20.36#ibcon#about to read 4, iclass 24, count 2 2006.257.12:50:20.36#ibcon#read 4, iclass 24, count 2 2006.257.12:50:20.36#ibcon#about to read 5, iclass 24, count 2 2006.257.12:50:20.36#ibcon#read 5, iclass 24, count 2 2006.257.12:50:20.36#ibcon#about to read 6, iclass 24, count 2 2006.257.12:50:20.36#ibcon#read 6, iclass 24, count 2 2006.257.12:50:20.36#ibcon#end of sib2, iclass 24, count 2 2006.257.12:50:20.36#ibcon#*after write, iclass 24, count 2 2006.257.12:50:20.36#ibcon#*before return 0, iclass 24, count 2 2006.257.12:50:20.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:20.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:20.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.12:50:20.36#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:20.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:20.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:20.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:20.48#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:50:20.48#ibcon#first serial, iclass 24, count 0 2006.257.12:50:20.48#ibcon#enter sib2, iclass 24, count 0 2006.257.12:50:20.48#ibcon#flushed, iclass 24, count 0 2006.257.12:50:20.48#ibcon#about to write, iclass 24, count 0 2006.257.12:50:20.48#ibcon#wrote, iclass 24, count 0 2006.257.12:50:20.48#ibcon#about to read 3, iclass 24, count 0 2006.257.12:50:20.50#ibcon#read 3, iclass 24, count 0 2006.257.12:50:20.50#ibcon#about to read 4, iclass 24, count 0 2006.257.12:50:20.50#ibcon#read 4, iclass 24, count 0 2006.257.12:50:20.50#ibcon#about to read 5, iclass 24, count 0 2006.257.12:50:20.50#ibcon#read 5, iclass 24, count 0 2006.257.12:50:20.50#ibcon#about to read 6, iclass 24, count 0 2006.257.12:50:20.50#ibcon#read 6, iclass 24, count 0 2006.257.12:50:20.50#ibcon#end of sib2, iclass 24, count 0 2006.257.12:50:20.50#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:50:20.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:50:20.50#ibcon#[25=USB\r\n] 2006.257.12:50:20.50#ibcon#*before write, iclass 24, count 0 2006.257.12:50:20.50#ibcon#enter sib2, iclass 24, count 0 2006.257.12:50:20.50#ibcon#flushed, iclass 24, count 0 2006.257.12:50:20.50#ibcon#about to write, iclass 24, count 0 2006.257.12:50:20.50#ibcon#wrote, iclass 24, count 0 2006.257.12:50:20.50#ibcon#about to read 3, iclass 24, count 0 2006.257.12:50:20.53#ibcon#read 3, iclass 24, count 0 2006.257.12:50:20.53#ibcon#about to read 4, iclass 24, count 0 2006.257.12:50:20.53#ibcon#read 4, iclass 24, count 0 2006.257.12:50:20.53#ibcon#about to read 5, iclass 24, count 0 2006.257.12:50:20.53#ibcon#read 5, iclass 24, count 0 2006.257.12:50:20.53#ibcon#about to read 6, iclass 24, count 0 2006.257.12:50:20.53#ibcon#read 6, iclass 24, count 0 2006.257.12:50:20.53#ibcon#end of sib2, iclass 24, count 0 2006.257.12:50:20.53#ibcon#*after write, iclass 24, count 0 2006.257.12:50:20.53#ibcon#*before return 0, iclass 24, count 0 2006.257.12:50:20.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:20.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:20.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:50:20.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:50:20.53$vck44/valo=2,534.99 2006.257.12:50:20.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.12:50:20.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.12:50:20.53#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:20.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:20.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:20.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:20.53#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:50:20.53#ibcon#first serial, iclass 26, count 0 2006.257.12:50:20.53#ibcon#enter sib2, iclass 26, count 0 2006.257.12:50:20.53#ibcon#flushed, iclass 26, count 0 2006.257.12:50:20.53#ibcon#about to write, iclass 26, count 0 2006.257.12:50:20.53#ibcon#wrote, iclass 26, count 0 2006.257.12:50:20.53#ibcon#about to read 3, iclass 26, count 0 2006.257.12:50:20.55#ibcon#read 3, iclass 26, count 0 2006.257.12:50:20.55#ibcon#about to read 4, iclass 26, count 0 2006.257.12:50:20.55#ibcon#read 4, iclass 26, count 0 2006.257.12:50:20.55#ibcon#about to read 5, iclass 26, count 0 2006.257.12:50:20.55#ibcon#read 5, iclass 26, count 0 2006.257.12:50:20.55#ibcon#about to read 6, iclass 26, count 0 2006.257.12:50:20.55#ibcon#read 6, iclass 26, count 0 2006.257.12:50:20.55#ibcon#end of sib2, iclass 26, count 0 2006.257.12:50:20.55#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:50:20.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:50:20.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:50:20.55#ibcon#*before write, iclass 26, count 0 2006.257.12:50:20.55#ibcon#enter sib2, iclass 26, count 0 2006.257.12:50:20.55#ibcon#flushed, iclass 26, count 0 2006.257.12:50:20.55#ibcon#about to write, iclass 26, count 0 2006.257.12:50:20.55#ibcon#wrote, iclass 26, count 0 2006.257.12:50:20.55#ibcon#about to read 3, iclass 26, count 0 2006.257.12:50:20.59#ibcon#read 3, iclass 26, count 0 2006.257.12:50:20.59#ibcon#about to read 4, iclass 26, count 0 2006.257.12:50:20.59#ibcon#read 4, iclass 26, count 0 2006.257.12:50:20.59#ibcon#about to read 5, iclass 26, count 0 2006.257.12:50:20.59#ibcon#read 5, iclass 26, count 0 2006.257.12:50:20.59#ibcon#about to read 6, iclass 26, count 0 2006.257.12:50:20.59#ibcon#read 6, iclass 26, count 0 2006.257.12:50:20.59#ibcon#end of sib2, iclass 26, count 0 2006.257.12:50:20.59#ibcon#*after write, iclass 26, count 0 2006.257.12:50:20.59#ibcon#*before return 0, iclass 26, count 0 2006.257.12:50:20.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:20.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:20.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:50:20.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:50:20.59$vck44/va=2,7 2006.257.12:50:20.59#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.12:50:20.59#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.12:50:20.59#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:20.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:20.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:20.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:20.65#ibcon#enter wrdev, iclass 28, count 2 2006.257.12:50:20.65#ibcon#first serial, iclass 28, count 2 2006.257.12:50:20.65#ibcon#enter sib2, iclass 28, count 2 2006.257.12:50:20.65#ibcon#flushed, iclass 28, count 2 2006.257.12:50:20.65#ibcon#about to write, iclass 28, count 2 2006.257.12:50:20.65#ibcon#wrote, iclass 28, count 2 2006.257.12:50:20.65#ibcon#about to read 3, iclass 28, count 2 2006.257.12:50:20.67#ibcon#read 3, iclass 28, count 2 2006.257.12:50:20.67#ibcon#about to read 4, iclass 28, count 2 2006.257.12:50:20.67#ibcon#read 4, iclass 28, count 2 2006.257.12:50:20.67#ibcon#about to read 5, iclass 28, count 2 2006.257.12:50:20.67#ibcon#read 5, iclass 28, count 2 2006.257.12:50:20.67#ibcon#about to read 6, iclass 28, count 2 2006.257.12:50:20.67#ibcon#read 6, iclass 28, count 2 2006.257.12:50:20.67#ibcon#end of sib2, iclass 28, count 2 2006.257.12:50:20.67#ibcon#*mode == 0, iclass 28, count 2 2006.257.12:50:20.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.12:50:20.67#ibcon#[25=AT02-07\r\n] 2006.257.12:50:20.67#ibcon#*before write, iclass 28, count 2 2006.257.12:50:20.67#ibcon#enter sib2, iclass 28, count 2 2006.257.12:50:20.67#ibcon#flushed, iclass 28, count 2 2006.257.12:50:20.67#ibcon#about to write, iclass 28, count 2 2006.257.12:50:20.67#ibcon#wrote, iclass 28, count 2 2006.257.12:50:20.67#ibcon#about to read 3, iclass 28, count 2 2006.257.12:50:20.70#ibcon#read 3, iclass 28, count 2 2006.257.12:50:20.70#ibcon#about to read 4, iclass 28, count 2 2006.257.12:50:20.70#ibcon#read 4, iclass 28, count 2 2006.257.12:50:20.70#ibcon#about to read 5, iclass 28, count 2 2006.257.12:50:20.70#ibcon#read 5, iclass 28, count 2 2006.257.12:50:20.70#ibcon#about to read 6, iclass 28, count 2 2006.257.12:50:20.70#ibcon#read 6, iclass 28, count 2 2006.257.12:50:20.70#ibcon#end of sib2, iclass 28, count 2 2006.257.12:50:20.70#ibcon#*after write, iclass 28, count 2 2006.257.12:50:20.70#ibcon#*before return 0, iclass 28, count 2 2006.257.12:50:20.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:20.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:20.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.12:50:20.70#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:20.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:20.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:20.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:20.82#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:50:20.82#ibcon#first serial, iclass 28, count 0 2006.257.12:50:20.82#ibcon#enter sib2, iclass 28, count 0 2006.257.12:50:20.82#ibcon#flushed, iclass 28, count 0 2006.257.12:50:20.82#ibcon#about to write, iclass 28, count 0 2006.257.12:50:20.82#ibcon#wrote, iclass 28, count 0 2006.257.12:50:20.82#ibcon#about to read 3, iclass 28, count 0 2006.257.12:50:20.84#ibcon#read 3, iclass 28, count 0 2006.257.12:50:20.84#ibcon#about to read 4, iclass 28, count 0 2006.257.12:50:20.84#ibcon#read 4, iclass 28, count 0 2006.257.12:50:20.84#ibcon#about to read 5, iclass 28, count 0 2006.257.12:50:20.84#ibcon#read 5, iclass 28, count 0 2006.257.12:50:20.84#ibcon#about to read 6, iclass 28, count 0 2006.257.12:50:20.84#ibcon#read 6, iclass 28, count 0 2006.257.12:50:20.84#ibcon#end of sib2, iclass 28, count 0 2006.257.12:50:20.84#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:50:20.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:50:20.84#ibcon#[25=USB\r\n] 2006.257.12:50:20.84#ibcon#*before write, iclass 28, count 0 2006.257.12:50:20.84#ibcon#enter sib2, iclass 28, count 0 2006.257.12:50:20.84#ibcon#flushed, iclass 28, count 0 2006.257.12:50:20.84#ibcon#about to write, iclass 28, count 0 2006.257.12:50:20.84#ibcon#wrote, iclass 28, count 0 2006.257.12:50:20.84#ibcon#about to read 3, iclass 28, count 0 2006.257.12:50:20.87#ibcon#read 3, iclass 28, count 0 2006.257.12:50:20.87#ibcon#about to read 4, iclass 28, count 0 2006.257.12:50:20.87#ibcon#read 4, iclass 28, count 0 2006.257.12:50:20.87#ibcon#about to read 5, iclass 28, count 0 2006.257.12:50:20.87#ibcon#read 5, iclass 28, count 0 2006.257.12:50:20.87#ibcon#about to read 6, iclass 28, count 0 2006.257.12:50:20.87#ibcon#read 6, iclass 28, count 0 2006.257.12:50:20.87#ibcon#end of sib2, iclass 28, count 0 2006.257.12:50:20.87#ibcon#*after write, iclass 28, count 0 2006.257.12:50:20.87#ibcon#*before return 0, iclass 28, count 0 2006.257.12:50:20.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:20.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:20.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:50:20.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:50:20.87$vck44/valo=3,564.99 2006.257.12:50:20.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.12:50:20.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.12:50:20.87#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:20.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:20.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:20.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:20.87#ibcon#enter wrdev, iclass 30, count 0 2006.257.12:50:20.87#ibcon#first serial, iclass 30, count 0 2006.257.12:50:20.87#ibcon#enter sib2, iclass 30, count 0 2006.257.12:50:20.87#ibcon#flushed, iclass 30, count 0 2006.257.12:50:20.87#ibcon#about to write, iclass 30, count 0 2006.257.12:50:20.87#ibcon#wrote, iclass 30, count 0 2006.257.12:50:20.87#ibcon#about to read 3, iclass 30, count 0 2006.257.12:50:20.89#ibcon#read 3, iclass 30, count 0 2006.257.12:50:20.89#ibcon#about to read 4, iclass 30, count 0 2006.257.12:50:20.89#ibcon#read 4, iclass 30, count 0 2006.257.12:50:20.89#ibcon#about to read 5, iclass 30, count 0 2006.257.12:50:20.89#ibcon#read 5, iclass 30, count 0 2006.257.12:50:20.89#ibcon#about to read 6, iclass 30, count 0 2006.257.12:50:20.89#ibcon#read 6, iclass 30, count 0 2006.257.12:50:20.89#ibcon#end of sib2, iclass 30, count 0 2006.257.12:50:20.89#ibcon#*mode == 0, iclass 30, count 0 2006.257.12:50:20.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.12:50:20.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:50:20.89#ibcon#*before write, iclass 30, count 0 2006.257.12:50:20.89#ibcon#enter sib2, iclass 30, count 0 2006.257.12:50:20.89#ibcon#flushed, iclass 30, count 0 2006.257.12:50:20.89#ibcon#about to write, iclass 30, count 0 2006.257.12:50:20.89#ibcon#wrote, iclass 30, count 0 2006.257.12:50:20.89#ibcon#about to read 3, iclass 30, count 0 2006.257.12:50:20.93#ibcon#read 3, iclass 30, count 0 2006.257.12:50:20.93#ibcon#about to read 4, iclass 30, count 0 2006.257.12:50:20.93#ibcon#read 4, iclass 30, count 0 2006.257.12:50:20.93#ibcon#about to read 5, iclass 30, count 0 2006.257.12:50:20.93#ibcon#read 5, iclass 30, count 0 2006.257.12:50:20.93#ibcon#about to read 6, iclass 30, count 0 2006.257.12:50:20.93#ibcon#read 6, iclass 30, count 0 2006.257.12:50:20.93#ibcon#end of sib2, iclass 30, count 0 2006.257.12:50:20.93#ibcon#*after write, iclass 30, count 0 2006.257.12:50:20.93#ibcon#*before return 0, iclass 30, count 0 2006.257.12:50:20.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:20.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:20.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.12:50:20.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.12:50:20.93$vck44/va=3,8 2006.257.12:50:20.93#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.12:50:20.93#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.12:50:20.93#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:20.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:20.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:20.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:20.99#ibcon#enter wrdev, iclass 32, count 2 2006.257.12:50:20.99#ibcon#first serial, iclass 32, count 2 2006.257.12:50:20.99#ibcon#enter sib2, iclass 32, count 2 2006.257.12:50:20.99#ibcon#flushed, iclass 32, count 2 2006.257.12:50:20.99#ibcon#about to write, iclass 32, count 2 2006.257.12:50:20.99#ibcon#wrote, iclass 32, count 2 2006.257.12:50:20.99#ibcon#about to read 3, iclass 32, count 2 2006.257.12:50:21.01#ibcon#read 3, iclass 32, count 2 2006.257.12:50:21.01#ibcon#about to read 4, iclass 32, count 2 2006.257.12:50:21.01#ibcon#read 4, iclass 32, count 2 2006.257.12:50:21.01#ibcon#about to read 5, iclass 32, count 2 2006.257.12:50:21.01#ibcon#read 5, iclass 32, count 2 2006.257.12:50:21.01#ibcon#about to read 6, iclass 32, count 2 2006.257.12:50:21.01#ibcon#read 6, iclass 32, count 2 2006.257.12:50:21.01#ibcon#end of sib2, iclass 32, count 2 2006.257.12:50:21.01#ibcon#*mode == 0, iclass 32, count 2 2006.257.12:50:21.01#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.12:50:21.01#ibcon#[25=AT03-08\r\n] 2006.257.12:50:21.01#ibcon#*before write, iclass 32, count 2 2006.257.12:50:21.01#ibcon#enter sib2, iclass 32, count 2 2006.257.12:50:21.01#ibcon#flushed, iclass 32, count 2 2006.257.12:50:21.01#ibcon#about to write, iclass 32, count 2 2006.257.12:50:21.01#ibcon#wrote, iclass 32, count 2 2006.257.12:50:21.01#ibcon#about to read 3, iclass 32, count 2 2006.257.12:50:21.04#ibcon#read 3, iclass 32, count 2 2006.257.12:50:21.04#ibcon#about to read 4, iclass 32, count 2 2006.257.12:50:21.04#ibcon#read 4, iclass 32, count 2 2006.257.12:50:21.04#ibcon#about to read 5, iclass 32, count 2 2006.257.12:50:21.04#ibcon#read 5, iclass 32, count 2 2006.257.12:50:21.04#ibcon#about to read 6, iclass 32, count 2 2006.257.12:50:21.04#ibcon#read 6, iclass 32, count 2 2006.257.12:50:21.04#ibcon#end of sib2, iclass 32, count 2 2006.257.12:50:21.04#ibcon#*after write, iclass 32, count 2 2006.257.12:50:21.04#ibcon#*before return 0, iclass 32, count 2 2006.257.12:50:21.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:21.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:21.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.12:50:21.04#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:21.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:21.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:21.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:21.16#ibcon#enter wrdev, iclass 32, count 0 2006.257.12:50:21.16#ibcon#first serial, iclass 32, count 0 2006.257.12:50:21.16#ibcon#enter sib2, iclass 32, count 0 2006.257.12:50:21.16#ibcon#flushed, iclass 32, count 0 2006.257.12:50:21.16#ibcon#about to write, iclass 32, count 0 2006.257.12:50:21.16#ibcon#wrote, iclass 32, count 0 2006.257.12:50:21.16#ibcon#about to read 3, iclass 32, count 0 2006.257.12:50:21.18#ibcon#read 3, iclass 32, count 0 2006.257.12:50:21.18#ibcon#about to read 4, iclass 32, count 0 2006.257.12:50:21.18#ibcon#read 4, iclass 32, count 0 2006.257.12:50:21.18#ibcon#about to read 5, iclass 32, count 0 2006.257.12:50:21.18#ibcon#read 5, iclass 32, count 0 2006.257.12:50:21.18#ibcon#about to read 6, iclass 32, count 0 2006.257.12:50:21.18#ibcon#read 6, iclass 32, count 0 2006.257.12:50:21.18#ibcon#end of sib2, iclass 32, count 0 2006.257.12:50:21.18#ibcon#*mode == 0, iclass 32, count 0 2006.257.12:50:21.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.12:50:21.18#ibcon#[25=USB\r\n] 2006.257.12:50:21.18#ibcon#*before write, iclass 32, count 0 2006.257.12:50:21.18#ibcon#enter sib2, iclass 32, count 0 2006.257.12:50:21.18#ibcon#flushed, iclass 32, count 0 2006.257.12:50:21.18#ibcon#about to write, iclass 32, count 0 2006.257.12:50:21.18#ibcon#wrote, iclass 32, count 0 2006.257.12:50:21.18#ibcon#about to read 3, iclass 32, count 0 2006.257.12:50:21.21#ibcon#read 3, iclass 32, count 0 2006.257.12:50:21.21#ibcon#about to read 4, iclass 32, count 0 2006.257.12:50:21.21#ibcon#read 4, iclass 32, count 0 2006.257.12:50:21.21#ibcon#about to read 5, iclass 32, count 0 2006.257.12:50:21.21#ibcon#read 5, iclass 32, count 0 2006.257.12:50:21.21#ibcon#about to read 6, iclass 32, count 0 2006.257.12:50:21.21#ibcon#read 6, iclass 32, count 0 2006.257.12:50:21.21#ibcon#end of sib2, iclass 32, count 0 2006.257.12:50:21.21#ibcon#*after write, iclass 32, count 0 2006.257.12:50:21.21#ibcon#*before return 0, iclass 32, count 0 2006.257.12:50:21.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:21.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:21.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.12:50:21.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.12:50:21.21$vck44/valo=4,624.99 2006.257.12:50:21.21#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.12:50:21.21#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.12:50:21.21#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:21.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:21.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:21.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:21.21#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:50:21.21#ibcon#first serial, iclass 34, count 0 2006.257.12:50:21.21#ibcon#enter sib2, iclass 34, count 0 2006.257.12:50:21.21#ibcon#flushed, iclass 34, count 0 2006.257.12:50:21.21#ibcon#about to write, iclass 34, count 0 2006.257.12:50:21.21#ibcon#wrote, iclass 34, count 0 2006.257.12:50:21.21#ibcon#about to read 3, iclass 34, count 0 2006.257.12:50:21.23#ibcon#read 3, iclass 34, count 0 2006.257.12:50:21.23#ibcon#about to read 4, iclass 34, count 0 2006.257.12:50:21.23#ibcon#read 4, iclass 34, count 0 2006.257.12:50:21.23#ibcon#about to read 5, iclass 34, count 0 2006.257.12:50:21.23#ibcon#read 5, iclass 34, count 0 2006.257.12:50:21.23#ibcon#about to read 6, iclass 34, count 0 2006.257.12:50:21.23#ibcon#read 6, iclass 34, count 0 2006.257.12:50:21.23#ibcon#end of sib2, iclass 34, count 0 2006.257.12:50:21.23#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:50:21.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:50:21.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:50:21.23#ibcon#*before write, iclass 34, count 0 2006.257.12:50:21.23#ibcon#enter sib2, iclass 34, count 0 2006.257.12:50:21.23#ibcon#flushed, iclass 34, count 0 2006.257.12:50:21.23#ibcon#about to write, iclass 34, count 0 2006.257.12:50:21.23#ibcon#wrote, iclass 34, count 0 2006.257.12:50:21.23#ibcon#about to read 3, iclass 34, count 0 2006.257.12:50:21.27#ibcon#read 3, iclass 34, count 0 2006.257.12:50:21.27#ibcon#about to read 4, iclass 34, count 0 2006.257.12:50:21.27#ibcon#read 4, iclass 34, count 0 2006.257.12:50:21.27#ibcon#about to read 5, iclass 34, count 0 2006.257.12:50:21.27#ibcon#read 5, iclass 34, count 0 2006.257.12:50:21.27#ibcon#about to read 6, iclass 34, count 0 2006.257.12:50:21.27#ibcon#read 6, iclass 34, count 0 2006.257.12:50:21.27#ibcon#end of sib2, iclass 34, count 0 2006.257.12:50:21.27#ibcon#*after write, iclass 34, count 0 2006.257.12:50:21.27#ibcon#*before return 0, iclass 34, count 0 2006.257.12:50:21.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:21.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:21.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:50:21.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:50:21.27$vck44/va=4,7 2006.257.12:50:21.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.12:50:21.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.12:50:21.27#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:21.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:21.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:21.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:21.33#ibcon#enter wrdev, iclass 36, count 2 2006.257.12:50:21.33#ibcon#first serial, iclass 36, count 2 2006.257.12:50:21.33#ibcon#enter sib2, iclass 36, count 2 2006.257.12:50:21.33#ibcon#flushed, iclass 36, count 2 2006.257.12:50:21.33#ibcon#about to write, iclass 36, count 2 2006.257.12:50:21.33#ibcon#wrote, iclass 36, count 2 2006.257.12:50:21.33#ibcon#about to read 3, iclass 36, count 2 2006.257.12:50:21.35#ibcon#read 3, iclass 36, count 2 2006.257.12:50:21.35#ibcon#about to read 4, iclass 36, count 2 2006.257.12:50:21.35#ibcon#read 4, iclass 36, count 2 2006.257.12:50:21.35#ibcon#about to read 5, iclass 36, count 2 2006.257.12:50:21.35#ibcon#read 5, iclass 36, count 2 2006.257.12:50:21.35#ibcon#about to read 6, iclass 36, count 2 2006.257.12:50:21.35#ibcon#read 6, iclass 36, count 2 2006.257.12:50:21.35#ibcon#end of sib2, iclass 36, count 2 2006.257.12:50:21.35#ibcon#*mode == 0, iclass 36, count 2 2006.257.12:50:21.35#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.12:50:21.35#ibcon#[25=AT04-07\r\n] 2006.257.12:50:21.35#ibcon#*before write, iclass 36, count 2 2006.257.12:50:21.35#ibcon#enter sib2, iclass 36, count 2 2006.257.12:50:21.35#ibcon#flushed, iclass 36, count 2 2006.257.12:50:21.35#ibcon#about to write, iclass 36, count 2 2006.257.12:50:21.35#ibcon#wrote, iclass 36, count 2 2006.257.12:50:21.35#ibcon#about to read 3, iclass 36, count 2 2006.257.12:50:21.38#ibcon#read 3, iclass 36, count 2 2006.257.12:50:21.38#ibcon#about to read 4, iclass 36, count 2 2006.257.12:50:21.38#ibcon#read 4, iclass 36, count 2 2006.257.12:50:21.38#ibcon#about to read 5, iclass 36, count 2 2006.257.12:50:21.38#ibcon#read 5, iclass 36, count 2 2006.257.12:50:21.38#ibcon#about to read 6, iclass 36, count 2 2006.257.12:50:21.38#ibcon#read 6, iclass 36, count 2 2006.257.12:50:21.38#ibcon#end of sib2, iclass 36, count 2 2006.257.12:50:21.38#ibcon#*after write, iclass 36, count 2 2006.257.12:50:21.38#ibcon#*before return 0, iclass 36, count 2 2006.257.12:50:21.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:21.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:21.38#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.12:50:21.38#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:21.38#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:21.50#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:21.50#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:21.50#ibcon#enter wrdev, iclass 36, count 0 2006.257.12:50:21.50#ibcon#first serial, iclass 36, count 0 2006.257.12:50:21.50#ibcon#enter sib2, iclass 36, count 0 2006.257.12:50:21.50#ibcon#flushed, iclass 36, count 0 2006.257.12:50:21.50#ibcon#about to write, iclass 36, count 0 2006.257.12:50:21.50#ibcon#wrote, iclass 36, count 0 2006.257.12:50:21.50#ibcon#about to read 3, iclass 36, count 0 2006.257.12:50:21.52#ibcon#read 3, iclass 36, count 0 2006.257.12:50:21.52#ibcon#about to read 4, iclass 36, count 0 2006.257.12:50:21.52#ibcon#read 4, iclass 36, count 0 2006.257.12:50:21.52#ibcon#about to read 5, iclass 36, count 0 2006.257.12:50:21.52#ibcon#read 5, iclass 36, count 0 2006.257.12:50:21.52#ibcon#about to read 6, iclass 36, count 0 2006.257.12:50:21.52#ibcon#read 6, iclass 36, count 0 2006.257.12:50:21.52#ibcon#end of sib2, iclass 36, count 0 2006.257.12:50:21.52#ibcon#*mode == 0, iclass 36, count 0 2006.257.12:50:21.52#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.12:50:21.52#ibcon#[25=USB\r\n] 2006.257.12:50:21.52#ibcon#*before write, iclass 36, count 0 2006.257.12:50:21.52#ibcon#enter sib2, iclass 36, count 0 2006.257.12:50:21.52#ibcon#flushed, iclass 36, count 0 2006.257.12:50:21.52#ibcon#about to write, iclass 36, count 0 2006.257.12:50:21.52#ibcon#wrote, iclass 36, count 0 2006.257.12:50:21.52#ibcon#about to read 3, iclass 36, count 0 2006.257.12:50:21.55#ibcon#read 3, iclass 36, count 0 2006.257.12:50:21.55#ibcon#about to read 4, iclass 36, count 0 2006.257.12:50:21.55#ibcon#read 4, iclass 36, count 0 2006.257.12:50:21.55#ibcon#about to read 5, iclass 36, count 0 2006.257.12:50:21.55#ibcon#read 5, iclass 36, count 0 2006.257.12:50:21.55#ibcon#about to read 6, iclass 36, count 0 2006.257.12:50:21.55#ibcon#read 6, iclass 36, count 0 2006.257.12:50:21.55#ibcon#end of sib2, iclass 36, count 0 2006.257.12:50:21.55#ibcon#*after write, iclass 36, count 0 2006.257.12:50:21.55#ibcon#*before return 0, iclass 36, count 0 2006.257.12:50:21.55#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:21.55#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:21.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.12:50:21.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.12:50:21.55$vck44/valo=5,734.99 2006.257.12:50:21.55#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.12:50:21.55#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.12:50:21.55#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:21.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:21.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:21.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:21.55#ibcon#enter wrdev, iclass 38, count 0 2006.257.12:50:21.55#ibcon#first serial, iclass 38, count 0 2006.257.12:50:21.55#ibcon#enter sib2, iclass 38, count 0 2006.257.12:50:21.55#ibcon#flushed, iclass 38, count 0 2006.257.12:50:21.55#ibcon#about to write, iclass 38, count 0 2006.257.12:50:21.55#ibcon#wrote, iclass 38, count 0 2006.257.12:50:21.55#ibcon#about to read 3, iclass 38, count 0 2006.257.12:50:21.57#ibcon#read 3, iclass 38, count 0 2006.257.12:50:21.57#ibcon#about to read 4, iclass 38, count 0 2006.257.12:50:21.57#ibcon#read 4, iclass 38, count 0 2006.257.12:50:21.57#ibcon#about to read 5, iclass 38, count 0 2006.257.12:50:21.57#ibcon#read 5, iclass 38, count 0 2006.257.12:50:21.57#ibcon#about to read 6, iclass 38, count 0 2006.257.12:50:21.57#ibcon#read 6, iclass 38, count 0 2006.257.12:50:21.57#ibcon#end of sib2, iclass 38, count 0 2006.257.12:50:21.57#ibcon#*mode == 0, iclass 38, count 0 2006.257.12:50:21.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.12:50:21.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:50:21.57#ibcon#*before write, iclass 38, count 0 2006.257.12:50:21.57#ibcon#enter sib2, iclass 38, count 0 2006.257.12:50:21.57#ibcon#flushed, iclass 38, count 0 2006.257.12:50:21.57#ibcon#about to write, iclass 38, count 0 2006.257.12:50:21.57#ibcon#wrote, iclass 38, count 0 2006.257.12:50:21.57#ibcon#about to read 3, iclass 38, count 0 2006.257.12:50:21.61#ibcon#read 3, iclass 38, count 0 2006.257.12:50:21.61#ibcon#about to read 4, iclass 38, count 0 2006.257.12:50:21.61#ibcon#read 4, iclass 38, count 0 2006.257.12:50:21.61#ibcon#about to read 5, iclass 38, count 0 2006.257.12:50:21.61#ibcon#read 5, iclass 38, count 0 2006.257.12:50:21.61#ibcon#about to read 6, iclass 38, count 0 2006.257.12:50:21.61#ibcon#read 6, iclass 38, count 0 2006.257.12:50:21.61#ibcon#end of sib2, iclass 38, count 0 2006.257.12:50:21.61#ibcon#*after write, iclass 38, count 0 2006.257.12:50:21.61#ibcon#*before return 0, iclass 38, count 0 2006.257.12:50:21.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:21.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:21.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.12:50:21.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.12:50:21.61$vck44/va=5,4 2006.257.12:50:21.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.12:50:21.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.12:50:21.61#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:21.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:21.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:21.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:21.67#ibcon#enter wrdev, iclass 40, count 2 2006.257.12:50:21.67#ibcon#first serial, iclass 40, count 2 2006.257.12:50:21.67#ibcon#enter sib2, iclass 40, count 2 2006.257.12:50:21.67#ibcon#flushed, iclass 40, count 2 2006.257.12:50:21.67#ibcon#about to write, iclass 40, count 2 2006.257.12:50:21.67#ibcon#wrote, iclass 40, count 2 2006.257.12:50:21.67#ibcon#about to read 3, iclass 40, count 2 2006.257.12:50:21.69#ibcon#read 3, iclass 40, count 2 2006.257.12:50:21.69#ibcon#about to read 4, iclass 40, count 2 2006.257.12:50:21.69#ibcon#read 4, iclass 40, count 2 2006.257.12:50:21.69#ibcon#about to read 5, iclass 40, count 2 2006.257.12:50:21.69#ibcon#read 5, iclass 40, count 2 2006.257.12:50:21.69#ibcon#about to read 6, iclass 40, count 2 2006.257.12:50:21.69#ibcon#read 6, iclass 40, count 2 2006.257.12:50:21.69#ibcon#end of sib2, iclass 40, count 2 2006.257.12:50:21.69#ibcon#*mode == 0, iclass 40, count 2 2006.257.12:50:21.69#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.12:50:21.69#ibcon#[25=AT05-04\r\n] 2006.257.12:50:21.69#ibcon#*before write, iclass 40, count 2 2006.257.12:50:21.69#ibcon#enter sib2, iclass 40, count 2 2006.257.12:50:21.69#ibcon#flushed, iclass 40, count 2 2006.257.12:50:21.69#ibcon#about to write, iclass 40, count 2 2006.257.12:50:21.69#ibcon#wrote, iclass 40, count 2 2006.257.12:50:21.69#ibcon#about to read 3, iclass 40, count 2 2006.257.12:50:21.72#ibcon#read 3, iclass 40, count 2 2006.257.12:50:21.72#ibcon#about to read 4, iclass 40, count 2 2006.257.12:50:21.72#ibcon#read 4, iclass 40, count 2 2006.257.12:50:21.72#ibcon#about to read 5, iclass 40, count 2 2006.257.12:50:21.72#ibcon#read 5, iclass 40, count 2 2006.257.12:50:21.72#ibcon#about to read 6, iclass 40, count 2 2006.257.12:50:21.72#ibcon#read 6, iclass 40, count 2 2006.257.12:50:21.72#ibcon#end of sib2, iclass 40, count 2 2006.257.12:50:21.72#ibcon#*after write, iclass 40, count 2 2006.257.12:50:21.72#ibcon#*before return 0, iclass 40, count 2 2006.257.12:50:21.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:21.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:21.72#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.12:50:21.72#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:21.72#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:21.84#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:21.84#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:21.84#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:50:21.84#ibcon#first serial, iclass 40, count 0 2006.257.12:50:21.84#ibcon#enter sib2, iclass 40, count 0 2006.257.12:50:21.84#ibcon#flushed, iclass 40, count 0 2006.257.12:50:21.84#ibcon#about to write, iclass 40, count 0 2006.257.12:50:21.84#ibcon#wrote, iclass 40, count 0 2006.257.12:50:21.84#ibcon#about to read 3, iclass 40, count 0 2006.257.12:50:21.86#ibcon#read 3, iclass 40, count 0 2006.257.12:50:21.86#ibcon#about to read 4, iclass 40, count 0 2006.257.12:50:21.86#ibcon#read 4, iclass 40, count 0 2006.257.12:50:21.86#ibcon#about to read 5, iclass 40, count 0 2006.257.12:50:21.86#ibcon#read 5, iclass 40, count 0 2006.257.12:50:21.86#ibcon#about to read 6, iclass 40, count 0 2006.257.12:50:21.86#ibcon#read 6, iclass 40, count 0 2006.257.12:50:21.86#ibcon#end of sib2, iclass 40, count 0 2006.257.12:50:21.86#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:50:21.86#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:50:21.86#ibcon#[25=USB\r\n] 2006.257.12:50:21.86#ibcon#*before write, iclass 40, count 0 2006.257.12:50:21.86#ibcon#enter sib2, iclass 40, count 0 2006.257.12:50:21.86#ibcon#flushed, iclass 40, count 0 2006.257.12:50:21.86#ibcon#about to write, iclass 40, count 0 2006.257.12:50:21.86#ibcon#wrote, iclass 40, count 0 2006.257.12:50:21.86#ibcon#about to read 3, iclass 40, count 0 2006.257.12:50:21.89#ibcon#read 3, iclass 40, count 0 2006.257.12:50:21.89#ibcon#about to read 4, iclass 40, count 0 2006.257.12:50:21.89#ibcon#read 4, iclass 40, count 0 2006.257.12:50:21.89#ibcon#about to read 5, iclass 40, count 0 2006.257.12:50:21.89#ibcon#read 5, iclass 40, count 0 2006.257.12:50:21.89#ibcon#about to read 6, iclass 40, count 0 2006.257.12:50:21.89#ibcon#read 6, iclass 40, count 0 2006.257.12:50:21.89#ibcon#end of sib2, iclass 40, count 0 2006.257.12:50:21.89#ibcon#*after write, iclass 40, count 0 2006.257.12:50:21.89#ibcon#*before return 0, iclass 40, count 0 2006.257.12:50:21.89#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:21.89#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:21.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:50:21.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:50:21.89$vck44/valo=6,814.99 2006.257.12:50:21.89#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.12:50:21.89#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.12:50:21.89#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:21.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:21.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:21.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:21.89#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:50:21.89#ibcon#first serial, iclass 4, count 0 2006.257.12:50:21.89#ibcon#enter sib2, iclass 4, count 0 2006.257.12:50:21.89#ibcon#flushed, iclass 4, count 0 2006.257.12:50:21.89#ibcon#about to write, iclass 4, count 0 2006.257.12:50:21.89#ibcon#wrote, iclass 4, count 0 2006.257.12:50:21.89#ibcon#about to read 3, iclass 4, count 0 2006.257.12:50:21.91#ibcon#read 3, iclass 4, count 0 2006.257.12:50:21.91#ibcon#about to read 4, iclass 4, count 0 2006.257.12:50:21.91#ibcon#read 4, iclass 4, count 0 2006.257.12:50:21.91#ibcon#about to read 5, iclass 4, count 0 2006.257.12:50:21.91#ibcon#read 5, iclass 4, count 0 2006.257.12:50:21.91#ibcon#about to read 6, iclass 4, count 0 2006.257.12:50:21.91#ibcon#read 6, iclass 4, count 0 2006.257.12:50:21.91#ibcon#end of sib2, iclass 4, count 0 2006.257.12:50:21.91#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:50:21.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:50:21.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:50:21.91#ibcon#*before write, iclass 4, count 0 2006.257.12:50:21.91#ibcon#enter sib2, iclass 4, count 0 2006.257.12:50:21.91#ibcon#flushed, iclass 4, count 0 2006.257.12:50:21.91#ibcon#about to write, iclass 4, count 0 2006.257.12:50:21.91#ibcon#wrote, iclass 4, count 0 2006.257.12:50:21.91#ibcon#about to read 3, iclass 4, count 0 2006.257.12:50:21.95#ibcon#read 3, iclass 4, count 0 2006.257.12:50:21.95#ibcon#about to read 4, iclass 4, count 0 2006.257.12:50:21.95#ibcon#read 4, iclass 4, count 0 2006.257.12:50:21.95#ibcon#about to read 5, iclass 4, count 0 2006.257.12:50:21.95#ibcon#read 5, iclass 4, count 0 2006.257.12:50:21.95#ibcon#about to read 6, iclass 4, count 0 2006.257.12:50:21.95#ibcon#read 6, iclass 4, count 0 2006.257.12:50:21.95#ibcon#end of sib2, iclass 4, count 0 2006.257.12:50:21.95#ibcon#*after write, iclass 4, count 0 2006.257.12:50:21.95#ibcon#*before return 0, iclass 4, count 0 2006.257.12:50:21.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:21.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:21.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:50:21.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:50:21.95$vck44/va=6,4 2006.257.12:50:21.95#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.12:50:21.95#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.12:50:21.95#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:21.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:22.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:22.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:22.01#ibcon#enter wrdev, iclass 6, count 2 2006.257.12:50:22.01#ibcon#first serial, iclass 6, count 2 2006.257.12:50:22.01#ibcon#enter sib2, iclass 6, count 2 2006.257.12:50:22.01#ibcon#flushed, iclass 6, count 2 2006.257.12:50:22.01#ibcon#about to write, iclass 6, count 2 2006.257.12:50:22.01#ibcon#wrote, iclass 6, count 2 2006.257.12:50:22.01#ibcon#about to read 3, iclass 6, count 2 2006.257.12:50:22.03#ibcon#read 3, iclass 6, count 2 2006.257.12:50:22.03#ibcon#about to read 4, iclass 6, count 2 2006.257.12:50:22.03#ibcon#read 4, iclass 6, count 2 2006.257.12:50:22.03#ibcon#about to read 5, iclass 6, count 2 2006.257.12:50:22.03#ibcon#read 5, iclass 6, count 2 2006.257.12:50:22.03#ibcon#about to read 6, iclass 6, count 2 2006.257.12:50:22.03#ibcon#read 6, iclass 6, count 2 2006.257.12:50:22.03#ibcon#end of sib2, iclass 6, count 2 2006.257.12:50:22.03#ibcon#*mode == 0, iclass 6, count 2 2006.257.12:50:22.03#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.12:50:22.03#ibcon#[25=AT06-04\r\n] 2006.257.12:50:22.03#ibcon#*before write, iclass 6, count 2 2006.257.12:50:22.03#ibcon#enter sib2, iclass 6, count 2 2006.257.12:50:22.03#ibcon#flushed, iclass 6, count 2 2006.257.12:50:22.03#ibcon#about to write, iclass 6, count 2 2006.257.12:50:22.03#ibcon#wrote, iclass 6, count 2 2006.257.12:50:22.03#ibcon#about to read 3, iclass 6, count 2 2006.257.12:50:22.06#ibcon#read 3, iclass 6, count 2 2006.257.12:50:22.06#ibcon#about to read 4, iclass 6, count 2 2006.257.12:50:22.06#ibcon#read 4, iclass 6, count 2 2006.257.12:50:22.06#ibcon#about to read 5, iclass 6, count 2 2006.257.12:50:22.06#ibcon#read 5, iclass 6, count 2 2006.257.12:50:22.06#ibcon#about to read 6, iclass 6, count 2 2006.257.12:50:22.06#ibcon#read 6, iclass 6, count 2 2006.257.12:50:22.06#ibcon#end of sib2, iclass 6, count 2 2006.257.12:50:22.06#ibcon#*after write, iclass 6, count 2 2006.257.12:50:22.06#ibcon#*before return 0, iclass 6, count 2 2006.257.12:50:22.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:22.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:22.06#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.12:50:22.06#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:22.06#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:22.18#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:22.18#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:22.18#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:50:22.18#ibcon#first serial, iclass 6, count 0 2006.257.12:50:22.18#ibcon#enter sib2, iclass 6, count 0 2006.257.12:50:22.18#ibcon#flushed, iclass 6, count 0 2006.257.12:50:22.18#ibcon#about to write, iclass 6, count 0 2006.257.12:50:22.18#ibcon#wrote, iclass 6, count 0 2006.257.12:50:22.18#ibcon#about to read 3, iclass 6, count 0 2006.257.12:50:22.20#ibcon#read 3, iclass 6, count 0 2006.257.12:50:22.20#ibcon#about to read 4, iclass 6, count 0 2006.257.12:50:22.20#ibcon#read 4, iclass 6, count 0 2006.257.12:50:22.20#ibcon#about to read 5, iclass 6, count 0 2006.257.12:50:22.20#ibcon#read 5, iclass 6, count 0 2006.257.12:50:22.20#ibcon#about to read 6, iclass 6, count 0 2006.257.12:50:22.20#ibcon#read 6, iclass 6, count 0 2006.257.12:50:22.20#ibcon#end of sib2, iclass 6, count 0 2006.257.12:50:22.20#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:50:22.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:50:22.20#ibcon#[25=USB\r\n] 2006.257.12:50:22.20#ibcon#*before write, iclass 6, count 0 2006.257.12:50:22.20#ibcon#enter sib2, iclass 6, count 0 2006.257.12:50:22.20#ibcon#flushed, iclass 6, count 0 2006.257.12:50:22.20#ibcon#about to write, iclass 6, count 0 2006.257.12:50:22.20#ibcon#wrote, iclass 6, count 0 2006.257.12:50:22.20#ibcon#about to read 3, iclass 6, count 0 2006.257.12:50:22.23#ibcon#read 3, iclass 6, count 0 2006.257.12:50:22.23#ibcon#about to read 4, iclass 6, count 0 2006.257.12:50:22.23#ibcon#read 4, iclass 6, count 0 2006.257.12:50:22.23#ibcon#about to read 5, iclass 6, count 0 2006.257.12:50:22.23#ibcon#read 5, iclass 6, count 0 2006.257.12:50:22.23#ibcon#about to read 6, iclass 6, count 0 2006.257.12:50:22.23#ibcon#read 6, iclass 6, count 0 2006.257.12:50:22.23#ibcon#end of sib2, iclass 6, count 0 2006.257.12:50:22.23#ibcon#*after write, iclass 6, count 0 2006.257.12:50:22.23#ibcon#*before return 0, iclass 6, count 0 2006.257.12:50:22.23#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:22.23#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:22.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:50:22.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:50:22.23$vck44/valo=7,864.99 2006.257.12:50:22.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.12:50:22.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.12:50:22.23#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:22.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:22.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:22.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:22.23#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:50:22.23#ibcon#first serial, iclass 10, count 0 2006.257.12:50:22.23#ibcon#enter sib2, iclass 10, count 0 2006.257.12:50:22.23#ibcon#flushed, iclass 10, count 0 2006.257.12:50:22.23#ibcon#about to write, iclass 10, count 0 2006.257.12:50:22.23#ibcon#wrote, iclass 10, count 0 2006.257.12:50:22.23#ibcon#about to read 3, iclass 10, count 0 2006.257.12:50:22.25#ibcon#read 3, iclass 10, count 0 2006.257.12:50:22.25#ibcon#about to read 4, iclass 10, count 0 2006.257.12:50:22.25#ibcon#read 4, iclass 10, count 0 2006.257.12:50:22.25#ibcon#about to read 5, iclass 10, count 0 2006.257.12:50:22.25#ibcon#read 5, iclass 10, count 0 2006.257.12:50:22.25#ibcon#about to read 6, iclass 10, count 0 2006.257.12:50:22.25#ibcon#read 6, iclass 10, count 0 2006.257.12:50:22.25#ibcon#end of sib2, iclass 10, count 0 2006.257.12:50:22.25#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:50:22.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:50:22.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:50:22.25#ibcon#*before write, iclass 10, count 0 2006.257.12:50:22.25#ibcon#enter sib2, iclass 10, count 0 2006.257.12:50:22.25#ibcon#flushed, iclass 10, count 0 2006.257.12:50:22.25#ibcon#about to write, iclass 10, count 0 2006.257.12:50:22.25#ibcon#wrote, iclass 10, count 0 2006.257.12:50:22.25#ibcon#about to read 3, iclass 10, count 0 2006.257.12:50:22.29#ibcon#read 3, iclass 10, count 0 2006.257.12:50:22.29#ibcon#about to read 4, iclass 10, count 0 2006.257.12:50:22.29#ibcon#read 4, iclass 10, count 0 2006.257.12:50:22.29#ibcon#about to read 5, iclass 10, count 0 2006.257.12:50:22.29#ibcon#read 5, iclass 10, count 0 2006.257.12:50:22.29#ibcon#about to read 6, iclass 10, count 0 2006.257.12:50:22.29#ibcon#read 6, iclass 10, count 0 2006.257.12:50:22.29#ibcon#end of sib2, iclass 10, count 0 2006.257.12:50:22.29#ibcon#*after write, iclass 10, count 0 2006.257.12:50:22.29#ibcon#*before return 0, iclass 10, count 0 2006.257.12:50:22.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:22.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:22.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:50:22.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:50:22.29$vck44/va=7,4 2006.257.12:50:22.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.12:50:22.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.12:50:22.29#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:22.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:22.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:22.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:22.35#ibcon#enter wrdev, iclass 12, count 2 2006.257.12:50:22.35#ibcon#first serial, iclass 12, count 2 2006.257.12:50:22.35#ibcon#enter sib2, iclass 12, count 2 2006.257.12:50:22.35#ibcon#flushed, iclass 12, count 2 2006.257.12:50:22.35#ibcon#about to write, iclass 12, count 2 2006.257.12:50:22.35#ibcon#wrote, iclass 12, count 2 2006.257.12:50:22.35#ibcon#about to read 3, iclass 12, count 2 2006.257.12:50:22.37#ibcon#read 3, iclass 12, count 2 2006.257.12:50:22.37#ibcon#about to read 4, iclass 12, count 2 2006.257.12:50:22.37#ibcon#read 4, iclass 12, count 2 2006.257.12:50:22.37#ibcon#about to read 5, iclass 12, count 2 2006.257.12:50:22.37#ibcon#read 5, iclass 12, count 2 2006.257.12:50:22.37#ibcon#about to read 6, iclass 12, count 2 2006.257.12:50:22.37#ibcon#read 6, iclass 12, count 2 2006.257.12:50:22.37#ibcon#end of sib2, iclass 12, count 2 2006.257.12:50:22.37#ibcon#*mode == 0, iclass 12, count 2 2006.257.12:50:22.37#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.12:50:22.37#ibcon#[25=AT07-04\r\n] 2006.257.12:50:22.37#ibcon#*before write, iclass 12, count 2 2006.257.12:50:22.37#ibcon#enter sib2, iclass 12, count 2 2006.257.12:50:22.37#ibcon#flushed, iclass 12, count 2 2006.257.12:50:22.37#ibcon#about to write, iclass 12, count 2 2006.257.12:50:22.37#ibcon#wrote, iclass 12, count 2 2006.257.12:50:22.37#ibcon#about to read 3, iclass 12, count 2 2006.257.12:50:22.40#ibcon#read 3, iclass 12, count 2 2006.257.12:50:22.40#ibcon#about to read 4, iclass 12, count 2 2006.257.12:50:22.40#ibcon#read 4, iclass 12, count 2 2006.257.12:50:22.40#ibcon#about to read 5, iclass 12, count 2 2006.257.12:50:22.40#ibcon#read 5, iclass 12, count 2 2006.257.12:50:22.40#ibcon#about to read 6, iclass 12, count 2 2006.257.12:50:22.40#ibcon#read 6, iclass 12, count 2 2006.257.12:50:22.40#ibcon#end of sib2, iclass 12, count 2 2006.257.12:50:22.40#ibcon#*after write, iclass 12, count 2 2006.257.12:50:22.40#ibcon#*before return 0, iclass 12, count 2 2006.257.12:50:22.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:22.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:22.40#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.12:50:22.40#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:22.40#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:22.52#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:22.52#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:22.52#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:50:22.52#ibcon#first serial, iclass 12, count 0 2006.257.12:50:22.52#ibcon#enter sib2, iclass 12, count 0 2006.257.12:50:22.52#ibcon#flushed, iclass 12, count 0 2006.257.12:50:22.52#ibcon#about to write, iclass 12, count 0 2006.257.12:50:22.52#ibcon#wrote, iclass 12, count 0 2006.257.12:50:22.52#ibcon#about to read 3, iclass 12, count 0 2006.257.12:50:22.54#ibcon#read 3, iclass 12, count 0 2006.257.12:50:22.54#ibcon#about to read 4, iclass 12, count 0 2006.257.12:50:22.54#ibcon#read 4, iclass 12, count 0 2006.257.12:50:22.54#ibcon#about to read 5, iclass 12, count 0 2006.257.12:50:22.54#ibcon#read 5, iclass 12, count 0 2006.257.12:50:22.54#ibcon#about to read 6, iclass 12, count 0 2006.257.12:50:22.54#ibcon#read 6, iclass 12, count 0 2006.257.12:50:22.54#ibcon#end of sib2, iclass 12, count 0 2006.257.12:50:22.54#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:50:22.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:50:22.54#ibcon#[25=USB\r\n] 2006.257.12:50:22.54#ibcon#*before write, iclass 12, count 0 2006.257.12:50:22.54#ibcon#enter sib2, iclass 12, count 0 2006.257.12:50:22.54#ibcon#flushed, iclass 12, count 0 2006.257.12:50:22.54#ibcon#about to write, iclass 12, count 0 2006.257.12:50:22.54#ibcon#wrote, iclass 12, count 0 2006.257.12:50:22.54#ibcon#about to read 3, iclass 12, count 0 2006.257.12:50:22.57#ibcon#read 3, iclass 12, count 0 2006.257.12:50:22.57#ibcon#about to read 4, iclass 12, count 0 2006.257.12:50:22.57#ibcon#read 4, iclass 12, count 0 2006.257.12:50:22.57#ibcon#about to read 5, iclass 12, count 0 2006.257.12:50:22.57#ibcon#read 5, iclass 12, count 0 2006.257.12:50:22.57#ibcon#about to read 6, iclass 12, count 0 2006.257.12:50:22.57#ibcon#read 6, iclass 12, count 0 2006.257.12:50:22.57#ibcon#end of sib2, iclass 12, count 0 2006.257.12:50:22.57#ibcon#*after write, iclass 12, count 0 2006.257.12:50:22.57#ibcon#*before return 0, iclass 12, count 0 2006.257.12:50:22.57#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:22.57#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:22.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:50:22.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:50:22.57$vck44/valo=8,884.99 2006.257.12:50:22.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.12:50:22.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.12:50:22.57#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:22.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:22.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:22.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:22.57#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:50:22.57#ibcon#first serial, iclass 14, count 0 2006.257.12:50:22.57#ibcon#enter sib2, iclass 14, count 0 2006.257.12:50:22.57#ibcon#flushed, iclass 14, count 0 2006.257.12:50:22.57#ibcon#about to write, iclass 14, count 0 2006.257.12:50:22.57#ibcon#wrote, iclass 14, count 0 2006.257.12:50:22.57#ibcon#about to read 3, iclass 14, count 0 2006.257.12:50:22.59#ibcon#read 3, iclass 14, count 0 2006.257.12:50:22.59#ibcon#about to read 4, iclass 14, count 0 2006.257.12:50:22.59#ibcon#read 4, iclass 14, count 0 2006.257.12:50:22.59#ibcon#about to read 5, iclass 14, count 0 2006.257.12:50:22.59#ibcon#read 5, iclass 14, count 0 2006.257.12:50:22.59#ibcon#about to read 6, iclass 14, count 0 2006.257.12:50:22.59#ibcon#read 6, iclass 14, count 0 2006.257.12:50:22.59#ibcon#end of sib2, iclass 14, count 0 2006.257.12:50:22.59#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:50:22.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:50:22.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:50:22.59#ibcon#*before write, iclass 14, count 0 2006.257.12:50:22.59#ibcon#enter sib2, iclass 14, count 0 2006.257.12:50:22.59#ibcon#flushed, iclass 14, count 0 2006.257.12:50:22.59#ibcon#about to write, iclass 14, count 0 2006.257.12:50:22.59#ibcon#wrote, iclass 14, count 0 2006.257.12:50:22.59#ibcon#about to read 3, iclass 14, count 0 2006.257.12:50:22.63#ibcon#read 3, iclass 14, count 0 2006.257.12:50:22.63#ibcon#about to read 4, iclass 14, count 0 2006.257.12:50:22.63#ibcon#read 4, iclass 14, count 0 2006.257.12:50:22.63#ibcon#about to read 5, iclass 14, count 0 2006.257.12:50:22.63#ibcon#read 5, iclass 14, count 0 2006.257.12:50:22.63#ibcon#about to read 6, iclass 14, count 0 2006.257.12:50:22.63#ibcon#read 6, iclass 14, count 0 2006.257.12:50:22.63#ibcon#end of sib2, iclass 14, count 0 2006.257.12:50:22.63#ibcon#*after write, iclass 14, count 0 2006.257.12:50:22.63#ibcon#*before return 0, iclass 14, count 0 2006.257.12:50:22.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:22.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:22.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:50:22.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:50:22.63$vck44/va=8,4 2006.257.12:50:22.63#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.12:50:22.63#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.12:50:22.63#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:22.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:22.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:22.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:22.69#ibcon#enter wrdev, iclass 16, count 2 2006.257.12:50:22.69#ibcon#first serial, iclass 16, count 2 2006.257.12:50:22.69#ibcon#enter sib2, iclass 16, count 2 2006.257.12:50:22.69#ibcon#flushed, iclass 16, count 2 2006.257.12:50:22.69#ibcon#about to write, iclass 16, count 2 2006.257.12:50:22.69#ibcon#wrote, iclass 16, count 2 2006.257.12:50:22.69#ibcon#about to read 3, iclass 16, count 2 2006.257.12:50:22.71#ibcon#read 3, iclass 16, count 2 2006.257.12:50:22.71#ibcon#about to read 4, iclass 16, count 2 2006.257.12:50:22.71#ibcon#read 4, iclass 16, count 2 2006.257.12:50:22.71#ibcon#about to read 5, iclass 16, count 2 2006.257.12:50:22.71#ibcon#read 5, iclass 16, count 2 2006.257.12:50:22.71#ibcon#about to read 6, iclass 16, count 2 2006.257.12:50:22.71#ibcon#read 6, iclass 16, count 2 2006.257.12:50:22.71#ibcon#end of sib2, iclass 16, count 2 2006.257.12:50:22.71#ibcon#*mode == 0, iclass 16, count 2 2006.257.12:50:22.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.12:50:22.71#ibcon#[25=AT08-04\r\n] 2006.257.12:50:22.71#ibcon#*before write, iclass 16, count 2 2006.257.12:50:22.71#ibcon#enter sib2, iclass 16, count 2 2006.257.12:50:22.71#ibcon#flushed, iclass 16, count 2 2006.257.12:50:22.71#ibcon#about to write, iclass 16, count 2 2006.257.12:50:22.71#ibcon#wrote, iclass 16, count 2 2006.257.12:50:22.71#ibcon#about to read 3, iclass 16, count 2 2006.257.12:50:22.74#ibcon#read 3, iclass 16, count 2 2006.257.12:50:22.74#ibcon#about to read 4, iclass 16, count 2 2006.257.12:50:22.74#ibcon#read 4, iclass 16, count 2 2006.257.12:50:22.74#ibcon#about to read 5, iclass 16, count 2 2006.257.12:50:22.74#ibcon#read 5, iclass 16, count 2 2006.257.12:50:22.74#ibcon#about to read 6, iclass 16, count 2 2006.257.12:50:22.74#ibcon#read 6, iclass 16, count 2 2006.257.12:50:22.74#ibcon#end of sib2, iclass 16, count 2 2006.257.12:50:22.74#ibcon#*after write, iclass 16, count 2 2006.257.12:50:22.74#ibcon#*before return 0, iclass 16, count 2 2006.257.12:50:22.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:22.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:22.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.12:50:22.74#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:22.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:22.75#abcon#<5=/14 1.7 4.2 17.83 961013.8\r\n> 2006.257.12:50:22.77#abcon#{5=INTERFACE CLEAR} 2006.257.12:50:22.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:50:22.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:22.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:22.86#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:50:22.86#ibcon#first serial, iclass 16, count 0 2006.257.12:50:22.86#ibcon#enter sib2, iclass 16, count 0 2006.257.12:50:22.86#ibcon#flushed, iclass 16, count 0 2006.257.12:50:22.86#ibcon#about to write, iclass 16, count 0 2006.257.12:50:22.86#ibcon#wrote, iclass 16, count 0 2006.257.12:50:22.86#ibcon#about to read 3, iclass 16, count 0 2006.257.12:50:22.88#ibcon#read 3, iclass 16, count 0 2006.257.12:50:22.88#ibcon#about to read 4, iclass 16, count 0 2006.257.12:50:22.88#ibcon#read 4, iclass 16, count 0 2006.257.12:50:22.88#ibcon#about to read 5, iclass 16, count 0 2006.257.12:50:22.88#ibcon#read 5, iclass 16, count 0 2006.257.12:50:22.88#ibcon#about to read 6, iclass 16, count 0 2006.257.12:50:22.88#ibcon#read 6, iclass 16, count 0 2006.257.12:50:22.88#ibcon#end of sib2, iclass 16, count 0 2006.257.12:50:22.88#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:50:22.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:50:22.88#ibcon#[25=USB\r\n] 2006.257.12:50:22.88#ibcon#*before write, iclass 16, count 0 2006.257.12:50:22.88#ibcon#enter sib2, iclass 16, count 0 2006.257.12:50:22.88#ibcon#flushed, iclass 16, count 0 2006.257.12:50:22.88#ibcon#about to write, iclass 16, count 0 2006.257.12:50:22.88#ibcon#wrote, iclass 16, count 0 2006.257.12:50:22.88#ibcon#about to read 3, iclass 16, count 0 2006.257.12:50:22.91#ibcon#read 3, iclass 16, count 0 2006.257.12:50:22.91#ibcon#about to read 4, iclass 16, count 0 2006.257.12:50:22.91#ibcon#read 4, iclass 16, count 0 2006.257.12:50:22.91#ibcon#about to read 5, iclass 16, count 0 2006.257.12:50:22.91#ibcon#read 5, iclass 16, count 0 2006.257.12:50:22.91#ibcon#about to read 6, iclass 16, count 0 2006.257.12:50:22.91#ibcon#read 6, iclass 16, count 0 2006.257.12:50:22.91#ibcon#end of sib2, iclass 16, count 0 2006.257.12:50:22.91#ibcon#*after write, iclass 16, count 0 2006.257.12:50:22.91#ibcon#*before return 0, iclass 16, count 0 2006.257.12:50:22.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:22.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:22.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:50:22.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:50:22.91$vck44/vblo=1,629.99 2006.257.12:50:22.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.12:50:22.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.12:50:22.91#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:22.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:22.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:22.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:22.91#ibcon#enter wrdev, iclass 22, count 0 2006.257.12:50:22.91#ibcon#first serial, iclass 22, count 0 2006.257.12:50:22.91#ibcon#enter sib2, iclass 22, count 0 2006.257.12:50:22.91#ibcon#flushed, iclass 22, count 0 2006.257.12:50:22.91#ibcon#about to write, iclass 22, count 0 2006.257.12:50:22.91#ibcon#wrote, iclass 22, count 0 2006.257.12:50:22.91#ibcon#about to read 3, iclass 22, count 0 2006.257.12:50:22.93#ibcon#read 3, iclass 22, count 0 2006.257.12:50:22.93#ibcon#about to read 4, iclass 22, count 0 2006.257.12:50:22.93#ibcon#read 4, iclass 22, count 0 2006.257.12:50:22.93#ibcon#about to read 5, iclass 22, count 0 2006.257.12:50:22.93#ibcon#read 5, iclass 22, count 0 2006.257.12:50:22.93#ibcon#about to read 6, iclass 22, count 0 2006.257.12:50:22.93#ibcon#read 6, iclass 22, count 0 2006.257.12:50:22.93#ibcon#end of sib2, iclass 22, count 0 2006.257.12:50:22.93#ibcon#*mode == 0, iclass 22, count 0 2006.257.12:50:22.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.12:50:22.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:50:22.93#ibcon#*before write, iclass 22, count 0 2006.257.12:50:22.93#ibcon#enter sib2, iclass 22, count 0 2006.257.12:50:22.93#ibcon#flushed, iclass 22, count 0 2006.257.12:50:22.93#ibcon#about to write, iclass 22, count 0 2006.257.12:50:22.93#ibcon#wrote, iclass 22, count 0 2006.257.12:50:22.93#ibcon#about to read 3, iclass 22, count 0 2006.257.12:50:22.97#ibcon#read 3, iclass 22, count 0 2006.257.12:50:22.97#ibcon#about to read 4, iclass 22, count 0 2006.257.12:50:22.97#ibcon#read 4, iclass 22, count 0 2006.257.12:50:22.97#ibcon#about to read 5, iclass 22, count 0 2006.257.12:50:22.97#ibcon#read 5, iclass 22, count 0 2006.257.12:50:22.97#ibcon#about to read 6, iclass 22, count 0 2006.257.12:50:22.97#ibcon#read 6, iclass 22, count 0 2006.257.12:50:22.97#ibcon#end of sib2, iclass 22, count 0 2006.257.12:50:22.97#ibcon#*after write, iclass 22, count 0 2006.257.12:50:22.97#ibcon#*before return 0, iclass 22, count 0 2006.257.12:50:22.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:22.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.12:50:22.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.12:50:22.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.12:50:22.97$vck44/vb=1,4 2006.257.12:50:22.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.12:50:22.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.12:50:22.97#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:22.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:22.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:22.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:22.97#ibcon#enter wrdev, iclass 24, count 2 2006.257.12:50:22.97#ibcon#first serial, iclass 24, count 2 2006.257.12:50:22.97#ibcon#enter sib2, iclass 24, count 2 2006.257.12:50:22.97#ibcon#flushed, iclass 24, count 2 2006.257.12:50:22.97#ibcon#about to write, iclass 24, count 2 2006.257.12:50:22.97#ibcon#wrote, iclass 24, count 2 2006.257.12:50:22.97#ibcon#about to read 3, iclass 24, count 2 2006.257.12:50:22.99#ibcon#read 3, iclass 24, count 2 2006.257.12:50:22.99#ibcon#about to read 4, iclass 24, count 2 2006.257.12:50:22.99#ibcon#read 4, iclass 24, count 2 2006.257.12:50:22.99#ibcon#about to read 5, iclass 24, count 2 2006.257.12:50:22.99#ibcon#read 5, iclass 24, count 2 2006.257.12:50:22.99#ibcon#about to read 6, iclass 24, count 2 2006.257.12:50:22.99#ibcon#read 6, iclass 24, count 2 2006.257.12:50:22.99#ibcon#end of sib2, iclass 24, count 2 2006.257.12:50:22.99#ibcon#*mode == 0, iclass 24, count 2 2006.257.12:50:22.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.12:50:22.99#ibcon#[27=AT01-04\r\n] 2006.257.12:50:22.99#ibcon#*before write, iclass 24, count 2 2006.257.12:50:22.99#ibcon#enter sib2, iclass 24, count 2 2006.257.12:50:22.99#ibcon#flushed, iclass 24, count 2 2006.257.12:50:22.99#ibcon#about to write, iclass 24, count 2 2006.257.12:50:22.99#ibcon#wrote, iclass 24, count 2 2006.257.12:50:22.99#ibcon#about to read 3, iclass 24, count 2 2006.257.12:50:23.02#ibcon#read 3, iclass 24, count 2 2006.257.12:50:23.02#ibcon#about to read 4, iclass 24, count 2 2006.257.12:50:23.02#ibcon#read 4, iclass 24, count 2 2006.257.12:50:23.02#ibcon#about to read 5, iclass 24, count 2 2006.257.12:50:23.02#ibcon#read 5, iclass 24, count 2 2006.257.12:50:23.02#ibcon#about to read 6, iclass 24, count 2 2006.257.12:50:23.02#ibcon#read 6, iclass 24, count 2 2006.257.12:50:23.02#ibcon#end of sib2, iclass 24, count 2 2006.257.12:50:23.02#ibcon#*after write, iclass 24, count 2 2006.257.12:50:23.02#ibcon#*before return 0, iclass 24, count 2 2006.257.12:50:23.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:23.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.12:50:23.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.12:50:23.02#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:23.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:23.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:23.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:23.14#ibcon#enter wrdev, iclass 24, count 0 2006.257.12:50:23.14#ibcon#first serial, iclass 24, count 0 2006.257.12:50:23.14#ibcon#enter sib2, iclass 24, count 0 2006.257.12:50:23.14#ibcon#flushed, iclass 24, count 0 2006.257.12:50:23.14#ibcon#about to write, iclass 24, count 0 2006.257.12:50:23.14#ibcon#wrote, iclass 24, count 0 2006.257.12:50:23.14#ibcon#about to read 3, iclass 24, count 0 2006.257.12:50:23.16#ibcon#read 3, iclass 24, count 0 2006.257.12:50:23.16#ibcon#about to read 4, iclass 24, count 0 2006.257.12:50:23.16#ibcon#read 4, iclass 24, count 0 2006.257.12:50:23.16#ibcon#about to read 5, iclass 24, count 0 2006.257.12:50:23.16#ibcon#read 5, iclass 24, count 0 2006.257.12:50:23.16#ibcon#about to read 6, iclass 24, count 0 2006.257.12:50:23.16#ibcon#read 6, iclass 24, count 0 2006.257.12:50:23.16#ibcon#end of sib2, iclass 24, count 0 2006.257.12:50:23.16#ibcon#*mode == 0, iclass 24, count 0 2006.257.12:50:23.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.12:50:23.16#ibcon#[27=USB\r\n] 2006.257.12:50:23.16#ibcon#*before write, iclass 24, count 0 2006.257.12:50:23.16#ibcon#enter sib2, iclass 24, count 0 2006.257.12:50:23.16#ibcon#flushed, iclass 24, count 0 2006.257.12:50:23.16#ibcon#about to write, iclass 24, count 0 2006.257.12:50:23.16#ibcon#wrote, iclass 24, count 0 2006.257.12:50:23.16#ibcon#about to read 3, iclass 24, count 0 2006.257.12:50:23.19#ibcon#read 3, iclass 24, count 0 2006.257.12:50:23.19#ibcon#about to read 4, iclass 24, count 0 2006.257.12:50:23.19#ibcon#read 4, iclass 24, count 0 2006.257.12:50:23.19#ibcon#about to read 5, iclass 24, count 0 2006.257.12:50:23.19#ibcon#read 5, iclass 24, count 0 2006.257.12:50:23.19#ibcon#about to read 6, iclass 24, count 0 2006.257.12:50:23.19#ibcon#read 6, iclass 24, count 0 2006.257.12:50:23.19#ibcon#end of sib2, iclass 24, count 0 2006.257.12:50:23.19#ibcon#*after write, iclass 24, count 0 2006.257.12:50:23.19#ibcon#*before return 0, iclass 24, count 0 2006.257.12:50:23.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:23.19#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.12:50:23.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.12:50:23.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.12:50:23.19$vck44/vblo=2,634.99 2006.257.12:50:23.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.12:50:23.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.12:50:23.19#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:23.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:23.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:23.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:23.19#ibcon#enter wrdev, iclass 26, count 0 2006.257.12:50:23.19#ibcon#first serial, iclass 26, count 0 2006.257.12:50:23.19#ibcon#enter sib2, iclass 26, count 0 2006.257.12:50:23.19#ibcon#flushed, iclass 26, count 0 2006.257.12:50:23.19#ibcon#about to write, iclass 26, count 0 2006.257.12:50:23.19#ibcon#wrote, iclass 26, count 0 2006.257.12:50:23.19#ibcon#about to read 3, iclass 26, count 0 2006.257.12:50:23.21#ibcon#read 3, iclass 26, count 0 2006.257.12:50:23.21#ibcon#about to read 4, iclass 26, count 0 2006.257.12:50:23.21#ibcon#read 4, iclass 26, count 0 2006.257.12:50:23.21#ibcon#about to read 5, iclass 26, count 0 2006.257.12:50:23.21#ibcon#read 5, iclass 26, count 0 2006.257.12:50:23.21#ibcon#about to read 6, iclass 26, count 0 2006.257.12:50:23.21#ibcon#read 6, iclass 26, count 0 2006.257.12:50:23.21#ibcon#end of sib2, iclass 26, count 0 2006.257.12:50:23.21#ibcon#*mode == 0, iclass 26, count 0 2006.257.12:50:23.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.12:50:23.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:50:23.21#ibcon#*before write, iclass 26, count 0 2006.257.12:50:23.21#ibcon#enter sib2, iclass 26, count 0 2006.257.12:50:23.21#ibcon#flushed, iclass 26, count 0 2006.257.12:50:23.21#ibcon#about to write, iclass 26, count 0 2006.257.12:50:23.21#ibcon#wrote, iclass 26, count 0 2006.257.12:50:23.21#ibcon#about to read 3, iclass 26, count 0 2006.257.12:50:23.25#ibcon#read 3, iclass 26, count 0 2006.257.12:50:23.25#ibcon#about to read 4, iclass 26, count 0 2006.257.12:50:23.25#ibcon#read 4, iclass 26, count 0 2006.257.12:50:23.25#ibcon#about to read 5, iclass 26, count 0 2006.257.12:50:23.25#ibcon#read 5, iclass 26, count 0 2006.257.12:50:23.25#ibcon#about to read 6, iclass 26, count 0 2006.257.12:50:23.25#ibcon#read 6, iclass 26, count 0 2006.257.12:50:23.25#ibcon#end of sib2, iclass 26, count 0 2006.257.12:50:23.25#ibcon#*after write, iclass 26, count 0 2006.257.12:50:23.25#ibcon#*before return 0, iclass 26, count 0 2006.257.12:50:23.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:23.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.12:50:23.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.12:50:23.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.12:50:23.25$vck44/vb=2,5 2006.257.12:50:23.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.12:50:23.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.12:50:23.25#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:23.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:23.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:23.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:23.31#ibcon#enter wrdev, iclass 28, count 2 2006.257.12:50:23.31#ibcon#first serial, iclass 28, count 2 2006.257.12:50:23.31#ibcon#enter sib2, iclass 28, count 2 2006.257.12:50:23.31#ibcon#flushed, iclass 28, count 2 2006.257.12:50:23.31#ibcon#about to write, iclass 28, count 2 2006.257.12:50:23.31#ibcon#wrote, iclass 28, count 2 2006.257.12:50:23.31#ibcon#about to read 3, iclass 28, count 2 2006.257.12:50:23.33#ibcon#read 3, iclass 28, count 2 2006.257.12:50:23.33#ibcon#about to read 4, iclass 28, count 2 2006.257.12:50:23.33#ibcon#read 4, iclass 28, count 2 2006.257.12:50:23.33#ibcon#about to read 5, iclass 28, count 2 2006.257.12:50:23.33#ibcon#read 5, iclass 28, count 2 2006.257.12:50:23.33#ibcon#about to read 6, iclass 28, count 2 2006.257.12:50:23.33#ibcon#read 6, iclass 28, count 2 2006.257.12:50:23.33#ibcon#end of sib2, iclass 28, count 2 2006.257.12:50:23.33#ibcon#*mode == 0, iclass 28, count 2 2006.257.12:50:23.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.12:50:23.33#ibcon#[27=AT02-05\r\n] 2006.257.12:50:23.33#ibcon#*before write, iclass 28, count 2 2006.257.12:50:23.33#ibcon#enter sib2, iclass 28, count 2 2006.257.12:50:23.33#ibcon#flushed, iclass 28, count 2 2006.257.12:50:23.33#ibcon#about to write, iclass 28, count 2 2006.257.12:50:23.33#ibcon#wrote, iclass 28, count 2 2006.257.12:50:23.33#ibcon#about to read 3, iclass 28, count 2 2006.257.12:50:23.36#ibcon#read 3, iclass 28, count 2 2006.257.12:50:23.36#ibcon#about to read 4, iclass 28, count 2 2006.257.12:50:23.36#ibcon#read 4, iclass 28, count 2 2006.257.12:50:23.36#ibcon#about to read 5, iclass 28, count 2 2006.257.12:50:23.36#ibcon#read 5, iclass 28, count 2 2006.257.12:50:23.36#ibcon#about to read 6, iclass 28, count 2 2006.257.12:50:23.36#ibcon#read 6, iclass 28, count 2 2006.257.12:50:23.36#ibcon#end of sib2, iclass 28, count 2 2006.257.12:50:23.36#ibcon#*after write, iclass 28, count 2 2006.257.12:50:23.36#ibcon#*before return 0, iclass 28, count 2 2006.257.12:50:23.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:23.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.12:50:23.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.12:50:23.36#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:23.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:23.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:23.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:23.48#ibcon#enter wrdev, iclass 28, count 0 2006.257.12:50:23.48#ibcon#first serial, iclass 28, count 0 2006.257.12:50:23.48#ibcon#enter sib2, iclass 28, count 0 2006.257.12:50:23.48#ibcon#flushed, iclass 28, count 0 2006.257.12:50:23.48#ibcon#about to write, iclass 28, count 0 2006.257.12:50:23.48#ibcon#wrote, iclass 28, count 0 2006.257.12:50:23.48#ibcon#about to read 3, iclass 28, count 0 2006.257.12:50:23.50#ibcon#read 3, iclass 28, count 0 2006.257.12:50:23.50#ibcon#about to read 4, iclass 28, count 0 2006.257.12:50:23.50#ibcon#read 4, iclass 28, count 0 2006.257.12:50:23.50#ibcon#about to read 5, iclass 28, count 0 2006.257.12:50:23.50#ibcon#read 5, iclass 28, count 0 2006.257.12:50:23.50#ibcon#about to read 6, iclass 28, count 0 2006.257.12:50:23.50#ibcon#read 6, iclass 28, count 0 2006.257.12:50:23.50#ibcon#end of sib2, iclass 28, count 0 2006.257.12:50:23.50#ibcon#*mode == 0, iclass 28, count 0 2006.257.12:50:23.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.12:50:23.50#ibcon#[27=USB\r\n] 2006.257.12:50:23.50#ibcon#*before write, iclass 28, count 0 2006.257.12:50:23.50#ibcon#enter sib2, iclass 28, count 0 2006.257.12:50:23.50#ibcon#flushed, iclass 28, count 0 2006.257.12:50:23.50#ibcon#about to write, iclass 28, count 0 2006.257.12:50:23.50#ibcon#wrote, iclass 28, count 0 2006.257.12:50:23.50#ibcon#about to read 3, iclass 28, count 0 2006.257.12:50:23.53#ibcon#read 3, iclass 28, count 0 2006.257.12:50:23.53#ibcon#about to read 4, iclass 28, count 0 2006.257.12:50:23.53#ibcon#read 4, iclass 28, count 0 2006.257.12:50:23.53#ibcon#about to read 5, iclass 28, count 0 2006.257.12:50:23.53#ibcon#read 5, iclass 28, count 0 2006.257.12:50:23.53#ibcon#about to read 6, iclass 28, count 0 2006.257.12:50:23.53#ibcon#read 6, iclass 28, count 0 2006.257.12:50:23.53#ibcon#end of sib2, iclass 28, count 0 2006.257.12:50:23.53#ibcon#*after write, iclass 28, count 0 2006.257.12:50:23.53#ibcon#*before return 0, iclass 28, count 0 2006.257.12:50:23.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:23.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.12:50:23.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.12:50:23.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.12:50:23.53$vck44/vblo=3,649.99 2006.257.12:50:23.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.12:50:23.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.12:50:23.53#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:23.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:23.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:23.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:23.53#ibcon#enter wrdev, iclass 30, count 0 2006.257.12:50:23.53#ibcon#first serial, iclass 30, count 0 2006.257.12:50:23.53#ibcon#enter sib2, iclass 30, count 0 2006.257.12:50:23.53#ibcon#flushed, iclass 30, count 0 2006.257.12:50:23.53#ibcon#about to write, iclass 30, count 0 2006.257.12:50:23.53#ibcon#wrote, iclass 30, count 0 2006.257.12:50:23.53#ibcon#about to read 3, iclass 30, count 0 2006.257.12:50:23.55#ibcon#read 3, iclass 30, count 0 2006.257.12:50:23.55#ibcon#about to read 4, iclass 30, count 0 2006.257.12:50:23.55#ibcon#read 4, iclass 30, count 0 2006.257.12:50:23.55#ibcon#about to read 5, iclass 30, count 0 2006.257.12:50:23.55#ibcon#read 5, iclass 30, count 0 2006.257.12:50:23.55#ibcon#about to read 6, iclass 30, count 0 2006.257.12:50:23.55#ibcon#read 6, iclass 30, count 0 2006.257.12:50:23.55#ibcon#end of sib2, iclass 30, count 0 2006.257.12:50:23.55#ibcon#*mode == 0, iclass 30, count 0 2006.257.12:50:23.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.12:50:23.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:50:23.55#ibcon#*before write, iclass 30, count 0 2006.257.12:50:23.55#ibcon#enter sib2, iclass 30, count 0 2006.257.12:50:23.55#ibcon#flushed, iclass 30, count 0 2006.257.12:50:23.55#ibcon#about to write, iclass 30, count 0 2006.257.12:50:23.55#ibcon#wrote, iclass 30, count 0 2006.257.12:50:23.55#ibcon#about to read 3, iclass 30, count 0 2006.257.12:50:23.59#ibcon#read 3, iclass 30, count 0 2006.257.12:50:23.59#ibcon#about to read 4, iclass 30, count 0 2006.257.12:50:23.59#ibcon#read 4, iclass 30, count 0 2006.257.12:50:23.59#ibcon#about to read 5, iclass 30, count 0 2006.257.12:50:23.59#ibcon#read 5, iclass 30, count 0 2006.257.12:50:23.59#ibcon#about to read 6, iclass 30, count 0 2006.257.12:50:23.59#ibcon#read 6, iclass 30, count 0 2006.257.12:50:23.59#ibcon#end of sib2, iclass 30, count 0 2006.257.12:50:23.59#ibcon#*after write, iclass 30, count 0 2006.257.12:50:23.59#ibcon#*before return 0, iclass 30, count 0 2006.257.12:50:23.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:23.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.12:50:23.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.12:50:23.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.12:50:23.59$vck44/vb=3,4 2006.257.12:50:23.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.12:50:23.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.12:50:23.59#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:23.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:23.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:23.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:23.65#ibcon#enter wrdev, iclass 32, count 2 2006.257.12:50:23.65#ibcon#first serial, iclass 32, count 2 2006.257.12:50:23.65#ibcon#enter sib2, iclass 32, count 2 2006.257.12:50:23.65#ibcon#flushed, iclass 32, count 2 2006.257.12:50:23.65#ibcon#about to write, iclass 32, count 2 2006.257.12:50:23.65#ibcon#wrote, iclass 32, count 2 2006.257.12:50:23.65#ibcon#about to read 3, iclass 32, count 2 2006.257.12:50:23.67#ibcon#read 3, iclass 32, count 2 2006.257.12:50:23.67#ibcon#about to read 4, iclass 32, count 2 2006.257.12:50:23.67#ibcon#read 4, iclass 32, count 2 2006.257.12:50:23.67#ibcon#about to read 5, iclass 32, count 2 2006.257.12:50:23.67#ibcon#read 5, iclass 32, count 2 2006.257.12:50:23.67#ibcon#about to read 6, iclass 32, count 2 2006.257.12:50:23.67#ibcon#read 6, iclass 32, count 2 2006.257.12:50:23.67#ibcon#end of sib2, iclass 32, count 2 2006.257.12:50:23.67#ibcon#*mode == 0, iclass 32, count 2 2006.257.12:50:23.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.12:50:23.67#ibcon#[27=AT03-04\r\n] 2006.257.12:50:23.67#ibcon#*before write, iclass 32, count 2 2006.257.12:50:23.67#ibcon#enter sib2, iclass 32, count 2 2006.257.12:50:23.67#ibcon#flushed, iclass 32, count 2 2006.257.12:50:23.67#ibcon#about to write, iclass 32, count 2 2006.257.12:50:23.67#ibcon#wrote, iclass 32, count 2 2006.257.12:50:23.67#ibcon#about to read 3, iclass 32, count 2 2006.257.12:50:23.70#ibcon#read 3, iclass 32, count 2 2006.257.12:50:23.70#ibcon#about to read 4, iclass 32, count 2 2006.257.12:50:23.70#ibcon#read 4, iclass 32, count 2 2006.257.12:50:23.70#ibcon#about to read 5, iclass 32, count 2 2006.257.12:50:23.70#ibcon#read 5, iclass 32, count 2 2006.257.12:50:23.70#ibcon#about to read 6, iclass 32, count 2 2006.257.12:50:23.70#ibcon#read 6, iclass 32, count 2 2006.257.12:50:23.70#ibcon#end of sib2, iclass 32, count 2 2006.257.12:50:23.70#ibcon#*after write, iclass 32, count 2 2006.257.12:50:23.70#ibcon#*before return 0, iclass 32, count 2 2006.257.12:50:23.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:23.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.12:50:23.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.12:50:23.70#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:23.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:23.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:23.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:23.82#ibcon#enter wrdev, iclass 32, count 0 2006.257.12:50:23.82#ibcon#first serial, iclass 32, count 0 2006.257.12:50:23.82#ibcon#enter sib2, iclass 32, count 0 2006.257.12:50:23.82#ibcon#flushed, iclass 32, count 0 2006.257.12:50:23.82#ibcon#about to write, iclass 32, count 0 2006.257.12:50:23.82#ibcon#wrote, iclass 32, count 0 2006.257.12:50:23.82#ibcon#about to read 3, iclass 32, count 0 2006.257.12:50:23.84#ibcon#read 3, iclass 32, count 0 2006.257.12:50:23.84#ibcon#about to read 4, iclass 32, count 0 2006.257.12:50:23.84#ibcon#read 4, iclass 32, count 0 2006.257.12:50:23.84#ibcon#about to read 5, iclass 32, count 0 2006.257.12:50:23.84#ibcon#read 5, iclass 32, count 0 2006.257.12:50:23.84#ibcon#about to read 6, iclass 32, count 0 2006.257.12:50:23.84#ibcon#read 6, iclass 32, count 0 2006.257.12:50:23.84#ibcon#end of sib2, iclass 32, count 0 2006.257.12:50:23.84#ibcon#*mode == 0, iclass 32, count 0 2006.257.12:50:23.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.12:50:23.84#ibcon#[27=USB\r\n] 2006.257.12:50:23.84#ibcon#*before write, iclass 32, count 0 2006.257.12:50:23.84#ibcon#enter sib2, iclass 32, count 0 2006.257.12:50:23.84#ibcon#flushed, iclass 32, count 0 2006.257.12:50:23.84#ibcon#about to write, iclass 32, count 0 2006.257.12:50:23.84#ibcon#wrote, iclass 32, count 0 2006.257.12:50:23.84#ibcon#about to read 3, iclass 32, count 0 2006.257.12:50:23.87#ibcon#read 3, iclass 32, count 0 2006.257.12:50:23.87#ibcon#about to read 4, iclass 32, count 0 2006.257.12:50:23.87#ibcon#read 4, iclass 32, count 0 2006.257.12:50:23.87#ibcon#about to read 5, iclass 32, count 0 2006.257.12:50:23.87#ibcon#read 5, iclass 32, count 0 2006.257.12:50:23.87#ibcon#about to read 6, iclass 32, count 0 2006.257.12:50:23.87#ibcon#read 6, iclass 32, count 0 2006.257.12:50:23.87#ibcon#end of sib2, iclass 32, count 0 2006.257.12:50:23.87#ibcon#*after write, iclass 32, count 0 2006.257.12:50:23.87#ibcon#*before return 0, iclass 32, count 0 2006.257.12:50:23.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:23.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.12:50:23.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.12:50:23.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.12:50:23.87$vck44/vblo=4,679.99 2006.257.12:50:23.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.12:50:23.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.12:50:23.87#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:23.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:23.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:23.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:23.87#ibcon#enter wrdev, iclass 34, count 0 2006.257.12:50:23.87#ibcon#first serial, iclass 34, count 0 2006.257.12:50:23.87#ibcon#enter sib2, iclass 34, count 0 2006.257.12:50:23.87#ibcon#flushed, iclass 34, count 0 2006.257.12:50:23.87#ibcon#about to write, iclass 34, count 0 2006.257.12:50:23.87#ibcon#wrote, iclass 34, count 0 2006.257.12:50:23.87#ibcon#about to read 3, iclass 34, count 0 2006.257.12:50:23.89#ibcon#read 3, iclass 34, count 0 2006.257.12:50:23.89#ibcon#about to read 4, iclass 34, count 0 2006.257.12:50:23.89#ibcon#read 4, iclass 34, count 0 2006.257.12:50:23.89#ibcon#about to read 5, iclass 34, count 0 2006.257.12:50:23.89#ibcon#read 5, iclass 34, count 0 2006.257.12:50:23.89#ibcon#about to read 6, iclass 34, count 0 2006.257.12:50:23.89#ibcon#read 6, iclass 34, count 0 2006.257.12:50:23.89#ibcon#end of sib2, iclass 34, count 0 2006.257.12:50:23.89#ibcon#*mode == 0, iclass 34, count 0 2006.257.12:50:23.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.12:50:23.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:50:23.89#ibcon#*before write, iclass 34, count 0 2006.257.12:50:23.89#ibcon#enter sib2, iclass 34, count 0 2006.257.12:50:23.89#ibcon#flushed, iclass 34, count 0 2006.257.12:50:23.89#ibcon#about to write, iclass 34, count 0 2006.257.12:50:23.89#ibcon#wrote, iclass 34, count 0 2006.257.12:50:23.89#ibcon#about to read 3, iclass 34, count 0 2006.257.12:50:23.93#ibcon#read 3, iclass 34, count 0 2006.257.12:50:23.93#ibcon#about to read 4, iclass 34, count 0 2006.257.12:50:23.93#ibcon#read 4, iclass 34, count 0 2006.257.12:50:23.93#ibcon#about to read 5, iclass 34, count 0 2006.257.12:50:23.93#ibcon#read 5, iclass 34, count 0 2006.257.12:50:23.93#ibcon#about to read 6, iclass 34, count 0 2006.257.12:50:23.93#ibcon#read 6, iclass 34, count 0 2006.257.12:50:23.93#ibcon#end of sib2, iclass 34, count 0 2006.257.12:50:23.93#ibcon#*after write, iclass 34, count 0 2006.257.12:50:23.93#ibcon#*before return 0, iclass 34, count 0 2006.257.12:50:23.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:23.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.12:50:23.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.12:50:23.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.12:50:23.93$vck44/vb=4,5 2006.257.12:50:23.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.12:50:23.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.12:50:23.93#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:23.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:23.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:23.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:23.99#ibcon#enter wrdev, iclass 36, count 2 2006.257.12:50:23.99#ibcon#first serial, iclass 36, count 2 2006.257.12:50:23.99#ibcon#enter sib2, iclass 36, count 2 2006.257.12:50:23.99#ibcon#flushed, iclass 36, count 2 2006.257.12:50:23.99#ibcon#about to write, iclass 36, count 2 2006.257.12:50:23.99#ibcon#wrote, iclass 36, count 2 2006.257.12:50:23.99#ibcon#about to read 3, iclass 36, count 2 2006.257.12:50:24.01#ibcon#read 3, iclass 36, count 2 2006.257.12:50:24.01#ibcon#about to read 4, iclass 36, count 2 2006.257.12:50:24.01#ibcon#read 4, iclass 36, count 2 2006.257.12:50:24.01#ibcon#about to read 5, iclass 36, count 2 2006.257.12:50:24.01#ibcon#read 5, iclass 36, count 2 2006.257.12:50:24.01#ibcon#about to read 6, iclass 36, count 2 2006.257.12:50:24.01#ibcon#read 6, iclass 36, count 2 2006.257.12:50:24.01#ibcon#end of sib2, iclass 36, count 2 2006.257.12:50:24.01#ibcon#*mode == 0, iclass 36, count 2 2006.257.12:50:24.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.12:50:24.01#ibcon#[27=AT04-05\r\n] 2006.257.12:50:24.01#ibcon#*before write, iclass 36, count 2 2006.257.12:50:24.01#ibcon#enter sib2, iclass 36, count 2 2006.257.12:50:24.01#ibcon#flushed, iclass 36, count 2 2006.257.12:50:24.01#ibcon#about to write, iclass 36, count 2 2006.257.12:50:24.01#ibcon#wrote, iclass 36, count 2 2006.257.12:50:24.01#ibcon#about to read 3, iclass 36, count 2 2006.257.12:50:24.04#ibcon#read 3, iclass 36, count 2 2006.257.12:50:24.04#ibcon#about to read 4, iclass 36, count 2 2006.257.12:50:24.04#ibcon#read 4, iclass 36, count 2 2006.257.12:50:24.04#ibcon#about to read 5, iclass 36, count 2 2006.257.12:50:24.04#ibcon#read 5, iclass 36, count 2 2006.257.12:50:24.04#ibcon#about to read 6, iclass 36, count 2 2006.257.12:50:24.04#ibcon#read 6, iclass 36, count 2 2006.257.12:50:24.04#ibcon#end of sib2, iclass 36, count 2 2006.257.12:50:24.04#ibcon#*after write, iclass 36, count 2 2006.257.12:50:24.04#ibcon#*before return 0, iclass 36, count 2 2006.257.12:50:24.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:24.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.12:50:24.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.12:50:24.04#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:24.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:24.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:24.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:24.16#ibcon#enter wrdev, iclass 36, count 0 2006.257.12:50:24.16#ibcon#first serial, iclass 36, count 0 2006.257.12:50:24.16#ibcon#enter sib2, iclass 36, count 0 2006.257.12:50:24.16#ibcon#flushed, iclass 36, count 0 2006.257.12:50:24.16#ibcon#about to write, iclass 36, count 0 2006.257.12:50:24.16#ibcon#wrote, iclass 36, count 0 2006.257.12:50:24.16#ibcon#about to read 3, iclass 36, count 0 2006.257.12:50:24.18#ibcon#read 3, iclass 36, count 0 2006.257.12:50:24.18#ibcon#about to read 4, iclass 36, count 0 2006.257.12:50:24.18#ibcon#read 4, iclass 36, count 0 2006.257.12:50:24.18#ibcon#about to read 5, iclass 36, count 0 2006.257.12:50:24.18#ibcon#read 5, iclass 36, count 0 2006.257.12:50:24.18#ibcon#about to read 6, iclass 36, count 0 2006.257.12:50:24.18#ibcon#read 6, iclass 36, count 0 2006.257.12:50:24.18#ibcon#end of sib2, iclass 36, count 0 2006.257.12:50:24.18#ibcon#*mode == 0, iclass 36, count 0 2006.257.12:50:24.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.12:50:24.18#ibcon#[27=USB\r\n] 2006.257.12:50:24.18#ibcon#*before write, iclass 36, count 0 2006.257.12:50:24.18#ibcon#enter sib2, iclass 36, count 0 2006.257.12:50:24.18#ibcon#flushed, iclass 36, count 0 2006.257.12:50:24.18#ibcon#about to write, iclass 36, count 0 2006.257.12:50:24.18#ibcon#wrote, iclass 36, count 0 2006.257.12:50:24.18#ibcon#about to read 3, iclass 36, count 0 2006.257.12:50:24.21#ibcon#read 3, iclass 36, count 0 2006.257.12:50:24.21#ibcon#about to read 4, iclass 36, count 0 2006.257.12:50:24.21#ibcon#read 4, iclass 36, count 0 2006.257.12:50:24.21#ibcon#about to read 5, iclass 36, count 0 2006.257.12:50:24.21#ibcon#read 5, iclass 36, count 0 2006.257.12:50:24.21#ibcon#about to read 6, iclass 36, count 0 2006.257.12:50:24.21#ibcon#read 6, iclass 36, count 0 2006.257.12:50:24.21#ibcon#end of sib2, iclass 36, count 0 2006.257.12:50:24.21#ibcon#*after write, iclass 36, count 0 2006.257.12:50:24.21#ibcon#*before return 0, iclass 36, count 0 2006.257.12:50:24.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:24.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.12:50:24.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.12:50:24.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.12:50:24.21$vck44/vblo=5,709.99 2006.257.12:50:24.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.12:50:24.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.12:50:24.21#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:24.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:24.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:24.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:24.21#ibcon#enter wrdev, iclass 38, count 0 2006.257.12:50:24.21#ibcon#first serial, iclass 38, count 0 2006.257.12:50:24.21#ibcon#enter sib2, iclass 38, count 0 2006.257.12:50:24.21#ibcon#flushed, iclass 38, count 0 2006.257.12:50:24.21#ibcon#about to write, iclass 38, count 0 2006.257.12:50:24.21#ibcon#wrote, iclass 38, count 0 2006.257.12:50:24.21#ibcon#about to read 3, iclass 38, count 0 2006.257.12:50:24.23#ibcon#read 3, iclass 38, count 0 2006.257.12:50:24.23#ibcon#about to read 4, iclass 38, count 0 2006.257.12:50:24.23#ibcon#read 4, iclass 38, count 0 2006.257.12:50:24.23#ibcon#about to read 5, iclass 38, count 0 2006.257.12:50:24.23#ibcon#read 5, iclass 38, count 0 2006.257.12:50:24.23#ibcon#about to read 6, iclass 38, count 0 2006.257.12:50:24.23#ibcon#read 6, iclass 38, count 0 2006.257.12:50:24.23#ibcon#end of sib2, iclass 38, count 0 2006.257.12:50:24.23#ibcon#*mode == 0, iclass 38, count 0 2006.257.12:50:24.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.12:50:24.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:50:24.23#ibcon#*before write, iclass 38, count 0 2006.257.12:50:24.23#ibcon#enter sib2, iclass 38, count 0 2006.257.12:50:24.23#ibcon#flushed, iclass 38, count 0 2006.257.12:50:24.23#ibcon#about to write, iclass 38, count 0 2006.257.12:50:24.23#ibcon#wrote, iclass 38, count 0 2006.257.12:50:24.23#ibcon#about to read 3, iclass 38, count 0 2006.257.12:50:24.27#ibcon#read 3, iclass 38, count 0 2006.257.12:50:24.27#ibcon#about to read 4, iclass 38, count 0 2006.257.12:50:24.27#ibcon#read 4, iclass 38, count 0 2006.257.12:50:24.27#ibcon#about to read 5, iclass 38, count 0 2006.257.12:50:24.27#ibcon#read 5, iclass 38, count 0 2006.257.12:50:24.27#ibcon#about to read 6, iclass 38, count 0 2006.257.12:50:24.27#ibcon#read 6, iclass 38, count 0 2006.257.12:50:24.27#ibcon#end of sib2, iclass 38, count 0 2006.257.12:50:24.27#ibcon#*after write, iclass 38, count 0 2006.257.12:50:24.27#ibcon#*before return 0, iclass 38, count 0 2006.257.12:50:24.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:24.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.12:50:24.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.12:50:24.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.12:50:24.27$vck44/vb=5,4 2006.257.12:50:24.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.12:50:24.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.12:50:24.27#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:24.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:24.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:24.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:24.33#ibcon#enter wrdev, iclass 40, count 2 2006.257.12:50:24.33#ibcon#first serial, iclass 40, count 2 2006.257.12:50:24.33#ibcon#enter sib2, iclass 40, count 2 2006.257.12:50:24.33#ibcon#flushed, iclass 40, count 2 2006.257.12:50:24.33#ibcon#about to write, iclass 40, count 2 2006.257.12:50:24.33#ibcon#wrote, iclass 40, count 2 2006.257.12:50:24.33#ibcon#about to read 3, iclass 40, count 2 2006.257.12:50:24.35#ibcon#read 3, iclass 40, count 2 2006.257.12:50:24.35#ibcon#about to read 4, iclass 40, count 2 2006.257.12:50:24.35#ibcon#read 4, iclass 40, count 2 2006.257.12:50:24.35#ibcon#about to read 5, iclass 40, count 2 2006.257.12:50:24.35#ibcon#read 5, iclass 40, count 2 2006.257.12:50:24.35#ibcon#about to read 6, iclass 40, count 2 2006.257.12:50:24.35#ibcon#read 6, iclass 40, count 2 2006.257.12:50:24.35#ibcon#end of sib2, iclass 40, count 2 2006.257.12:50:24.35#ibcon#*mode == 0, iclass 40, count 2 2006.257.12:50:24.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.12:50:24.35#ibcon#[27=AT05-04\r\n] 2006.257.12:50:24.35#ibcon#*before write, iclass 40, count 2 2006.257.12:50:24.35#ibcon#enter sib2, iclass 40, count 2 2006.257.12:50:24.35#ibcon#flushed, iclass 40, count 2 2006.257.12:50:24.35#ibcon#about to write, iclass 40, count 2 2006.257.12:50:24.35#ibcon#wrote, iclass 40, count 2 2006.257.12:50:24.35#ibcon#about to read 3, iclass 40, count 2 2006.257.12:50:24.38#ibcon#read 3, iclass 40, count 2 2006.257.12:50:24.38#ibcon#about to read 4, iclass 40, count 2 2006.257.12:50:24.38#ibcon#read 4, iclass 40, count 2 2006.257.12:50:24.38#ibcon#about to read 5, iclass 40, count 2 2006.257.12:50:24.38#ibcon#read 5, iclass 40, count 2 2006.257.12:50:24.38#ibcon#about to read 6, iclass 40, count 2 2006.257.12:50:24.38#ibcon#read 6, iclass 40, count 2 2006.257.12:50:24.38#ibcon#end of sib2, iclass 40, count 2 2006.257.12:50:24.38#ibcon#*after write, iclass 40, count 2 2006.257.12:50:24.38#ibcon#*before return 0, iclass 40, count 2 2006.257.12:50:24.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:24.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.12:50:24.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.12:50:24.38#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:24.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:24.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:24.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:24.50#ibcon#enter wrdev, iclass 40, count 0 2006.257.12:50:24.50#ibcon#first serial, iclass 40, count 0 2006.257.12:50:24.50#ibcon#enter sib2, iclass 40, count 0 2006.257.12:50:24.50#ibcon#flushed, iclass 40, count 0 2006.257.12:50:24.50#ibcon#about to write, iclass 40, count 0 2006.257.12:50:24.50#ibcon#wrote, iclass 40, count 0 2006.257.12:50:24.50#ibcon#about to read 3, iclass 40, count 0 2006.257.12:50:24.52#ibcon#read 3, iclass 40, count 0 2006.257.12:50:24.52#ibcon#about to read 4, iclass 40, count 0 2006.257.12:50:24.52#ibcon#read 4, iclass 40, count 0 2006.257.12:50:24.52#ibcon#about to read 5, iclass 40, count 0 2006.257.12:50:24.52#ibcon#read 5, iclass 40, count 0 2006.257.12:50:24.52#ibcon#about to read 6, iclass 40, count 0 2006.257.12:50:24.52#ibcon#read 6, iclass 40, count 0 2006.257.12:50:24.52#ibcon#end of sib2, iclass 40, count 0 2006.257.12:50:24.52#ibcon#*mode == 0, iclass 40, count 0 2006.257.12:50:24.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.12:50:24.52#ibcon#[27=USB\r\n] 2006.257.12:50:24.52#ibcon#*before write, iclass 40, count 0 2006.257.12:50:24.52#ibcon#enter sib2, iclass 40, count 0 2006.257.12:50:24.52#ibcon#flushed, iclass 40, count 0 2006.257.12:50:24.52#ibcon#about to write, iclass 40, count 0 2006.257.12:50:24.52#ibcon#wrote, iclass 40, count 0 2006.257.12:50:24.52#ibcon#about to read 3, iclass 40, count 0 2006.257.12:50:24.55#ibcon#read 3, iclass 40, count 0 2006.257.12:50:24.55#ibcon#about to read 4, iclass 40, count 0 2006.257.12:50:24.55#ibcon#read 4, iclass 40, count 0 2006.257.12:50:24.55#ibcon#about to read 5, iclass 40, count 0 2006.257.12:50:24.55#ibcon#read 5, iclass 40, count 0 2006.257.12:50:24.55#ibcon#about to read 6, iclass 40, count 0 2006.257.12:50:24.55#ibcon#read 6, iclass 40, count 0 2006.257.12:50:24.55#ibcon#end of sib2, iclass 40, count 0 2006.257.12:50:24.55#ibcon#*after write, iclass 40, count 0 2006.257.12:50:24.55#ibcon#*before return 0, iclass 40, count 0 2006.257.12:50:24.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:24.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.12:50:24.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.12:50:24.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.12:50:24.55$vck44/vblo=6,719.99 2006.257.12:50:24.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.12:50:24.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.12:50:24.55#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:24.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:24.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:24.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:24.55#ibcon#enter wrdev, iclass 4, count 0 2006.257.12:50:24.55#ibcon#first serial, iclass 4, count 0 2006.257.12:50:24.55#ibcon#enter sib2, iclass 4, count 0 2006.257.12:50:24.55#ibcon#flushed, iclass 4, count 0 2006.257.12:50:24.55#ibcon#about to write, iclass 4, count 0 2006.257.12:50:24.55#ibcon#wrote, iclass 4, count 0 2006.257.12:50:24.55#ibcon#about to read 3, iclass 4, count 0 2006.257.12:50:24.57#ibcon#read 3, iclass 4, count 0 2006.257.12:50:24.57#ibcon#about to read 4, iclass 4, count 0 2006.257.12:50:24.57#ibcon#read 4, iclass 4, count 0 2006.257.12:50:24.57#ibcon#about to read 5, iclass 4, count 0 2006.257.12:50:24.57#ibcon#read 5, iclass 4, count 0 2006.257.12:50:24.57#ibcon#about to read 6, iclass 4, count 0 2006.257.12:50:24.57#ibcon#read 6, iclass 4, count 0 2006.257.12:50:24.57#ibcon#end of sib2, iclass 4, count 0 2006.257.12:50:24.57#ibcon#*mode == 0, iclass 4, count 0 2006.257.12:50:24.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.12:50:24.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:50:24.57#ibcon#*before write, iclass 4, count 0 2006.257.12:50:24.57#ibcon#enter sib2, iclass 4, count 0 2006.257.12:50:24.57#ibcon#flushed, iclass 4, count 0 2006.257.12:50:24.57#ibcon#about to write, iclass 4, count 0 2006.257.12:50:24.57#ibcon#wrote, iclass 4, count 0 2006.257.12:50:24.57#ibcon#about to read 3, iclass 4, count 0 2006.257.12:50:24.61#ibcon#read 3, iclass 4, count 0 2006.257.12:50:24.61#ibcon#about to read 4, iclass 4, count 0 2006.257.12:50:24.61#ibcon#read 4, iclass 4, count 0 2006.257.12:50:24.61#ibcon#about to read 5, iclass 4, count 0 2006.257.12:50:24.61#ibcon#read 5, iclass 4, count 0 2006.257.12:50:24.61#ibcon#about to read 6, iclass 4, count 0 2006.257.12:50:24.61#ibcon#read 6, iclass 4, count 0 2006.257.12:50:24.61#ibcon#end of sib2, iclass 4, count 0 2006.257.12:50:24.61#ibcon#*after write, iclass 4, count 0 2006.257.12:50:24.61#ibcon#*before return 0, iclass 4, count 0 2006.257.12:50:24.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:24.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.12:50:24.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.12:50:24.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.12:50:24.61$vck44/vb=6,4 2006.257.12:50:24.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.12:50:24.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.12:50:24.61#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:24.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:24.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:24.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:24.67#ibcon#enter wrdev, iclass 6, count 2 2006.257.12:50:24.67#ibcon#first serial, iclass 6, count 2 2006.257.12:50:24.67#ibcon#enter sib2, iclass 6, count 2 2006.257.12:50:24.67#ibcon#flushed, iclass 6, count 2 2006.257.12:50:24.67#ibcon#about to write, iclass 6, count 2 2006.257.12:50:24.67#ibcon#wrote, iclass 6, count 2 2006.257.12:50:24.67#ibcon#about to read 3, iclass 6, count 2 2006.257.12:50:24.69#ibcon#read 3, iclass 6, count 2 2006.257.12:50:24.69#ibcon#about to read 4, iclass 6, count 2 2006.257.12:50:24.69#ibcon#read 4, iclass 6, count 2 2006.257.12:50:24.69#ibcon#about to read 5, iclass 6, count 2 2006.257.12:50:24.69#ibcon#read 5, iclass 6, count 2 2006.257.12:50:24.69#ibcon#about to read 6, iclass 6, count 2 2006.257.12:50:24.69#ibcon#read 6, iclass 6, count 2 2006.257.12:50:24.69#ibcon#end of sib2, iclass 6, count 2 2006.257.12:50:24.69#ibcon#*mode == 0, iclass 6, count 2 2006.257.12:50:24.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.12:50:24.69#ibcon#[27=AT06-04\r\n] 2006.257.12:50:24.69#ibcon#*before write, iclass 6, count 2 2006.257.12:50:24.69#ibcon#enter sib2, iclass 6, count 2 2006.257.12:50:24.69#ibcon#flushed, iclass 6, count 2 2006.257.12:50:24.69#ibcon#about to write, iclass 6, count 2 2006.257.12:50:24.69#ibcon#wrote, iclass 6, count 2 2006.257.12:50:24.69#ibcon#about to read 3, iclass 6, count 2 2006.257.12:50:24.72#ibcon#read 3, iclass 6, count 2 2006.257.12:50:24.72#ibcon#about to read 4, iclass 6, count 2 2006.257.12:50:24.72#ibcon#read 4, iclass 6, count 2 2006.257.12:50:24.72#ibcon#about to read 5, iclass 6, count 2 2006.257.12:50:24.72#ibcon#read 5, iclass 6, count 2 2006.257.12:50:24.72#ibcon#about to read 6, iclass 6, count 2 2006.257.12:50:24.72#ibcon#read 6, iclass 6, count 2 2006.257.12:50:24.72#ibcon#end of sib2, iclass 6, count 2 2006.257.12:50:24.72#ibcon#*after write, iclass 6, count 2 2006.257.12:50:24.72#ibcon#*before return 0, iclass 6, count 2 2006.257.12:50:24.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:24.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.12:50:24.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.12:50:24.72#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:24.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:24.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:24.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:24.84#ibcon#enter wrdev, iclass 6, count 0 2006.257.12:50:24.84#ibcon#first serial, iclass 6, count 0 2006.257.12:50:24.84#ibcon#enter sib2, iclass 6, count 0 2006.257.12:50:24.84#ibcon#flushed, iclass 6, count 0 2006.257.12:50:24.84#ibcon#about to write, iclass 6, count 0 2006.257.12:50:24.84#ibcon#wrote, iclass 6, count 0 2006.257.12:50:24.84#ibcon#about to read 3, iclass 6, count 0 2006.257.12:50:24.86#ibcon#read 3, iclass 6, count 0 2006.257.12:50:24.86#ibcon#about to read 4, iclass 6, count 0 2006.257.12:50:24.86#ibcon#read 4, iclass 6, count 0 2006.257.12:50:24.86#ibcon#about to read 5, iclass 6, count 0 2006.257.12:50:24.86#ibcon#read 5, iclass 6, count 0 2006.257.12:50:24.86#ibcon#about to read 6, iclass 6, count 0 2006.257.12:50:24.86#ibcon#read 6, iclass 6, count 0 2006.257.12:50:24.86#ibcon#end of sib2, iclass 6, count 0 2006.257.12:50:24.86#ibcon#*mode == 0, iclass 6, count 0 2006.257.12:50:24.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.12:50:24.86#ibcon#[27=USB\r\n] 2006.257.12:50:24.86#ibcon#*before write, iclass 6, count 0 2006.257.12:50:24.86#ibcon#enter sib2, iclass 6, count 0 2006.257.12:50:24.86#ibcon#flushed, iclass 6, count 0 2006.257.12:50:24.86#ibcon#about to write, iclass 6, count 0 2006.257.12:50:24.86#ibcon#wrote, iclass 6, count 0 2006.257.12:50:24.86#ibcon#about to read 3, iclass 6, count 0 2006.257.12:50:24.89#ibcon#read 3, iclass 6, count 0 2006.257.12:50:24.89#ibcon#about to read 4, iclass 6, count 0 2006.257.12:50:24.89#ibcon#read 4, iclass 6, count 0 2006.257.12:50:24.89#ibcon#about to read 5, iclass 6, count 0 2006.257.12:50:24.89#ibcon#read 5, iclass 6, count 0 2006.257.12:50:24.89#ibcon#about to read 6, iclass 6, count 0 2006.257.12:50:24.89#ibcon#read 6, iclass 6, count 0 2006.257.12:50:24.89#ibcon#end of sib2, iclass 6, count 0 2006.257.12:50:24.89#ibcon#*after write, iclass 6, count 0 2006.257.12:50:24.89#ibcon#*before return 0, iclass 6, count 0 2006.257.12:50:24.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:24.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.12:50:24.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.12:50:24.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.12:50:24.89$vck44/vblo=7,734.99 2006.257.12:50:24.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.12:50:24.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.12:50:24.89#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:24.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:24.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:24.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:24.89#ibcon#enter wrdev, iclass 10, count 0 2006.257.12:50:24.89#ibcon#first serial, iclass 10, count 0 2006.257.12:50:24.89#ibcon#enter sib2, iclass 10, count 0 2006.257.12:50:24.89#ibcon#flushed, iclass 10, count 0 2006.257.12:50:24.89#ibcon#about to write, iclass 10, count 0 2006.257.12:50:24.89#ibcon#wrote, iclass 10, count 0 2006.257.12:50:24.89#ibcon#about to read 3, iclass 10, count 0 2006.257.12:50:24.91#ibcon#read 3, iclass 10, count 0 2006.257.12:50:24.91#ibcon#about to read 4, iclass 10, count 0 2006.257.12:50:24.91#ibcon#read 4, iclass 10, count 0 2006.257.12:50:24.91#ibcon#about to read 5, iclass 10, count 0 2006.257.12:50:24.91#ibcon#read 5, iclass 10, count 0 2006.257.12:50:24.91#ibcon#about to read 6, iclass 10, count 0 2006.257.12:50:24.91#ibcon#read 6, iclass 10, count 0 2006.257.12:50:24.91#ibcon#end of sib2, iclass 10, count 0 2006.257.12:50:24.91#ibcon#*mode == 0, iclass 10, count 0 2006.257.12:50:24.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.12:50:24.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:50:24.91#ibcon#*before write, iclass 10, count 0 2006.257.12:50:24.91#ibcon#enter sib2, iclass 10, count 0 2006.257.12:50:24.91#ibcon#flushed, iclass 10, count 0 2006.257.12:50:24.91#ibcon#about to write, iclass 10, count 0 2006.257.12:50:24.91#ibcon#wrote, iclass 10, count 0 2006.257.12:50:24.91#ibcon#about to read 3, iclass 10, count 0 2006.257.12:50:24.95#ibcon#read 3, iclass 10, count 0 2006.257.12:50:24.95#ibcon#about to read 4, iclass 10, count 0 2006.257.12:50:24.95#ibcon#read 4, iclass 10, count 0 2006.257.12:50:24.95#ibcon#about to read 5, iclass 10, count 0 2006.257.12:50:24.95#ibcon#read 5, iclass 10, count 0 2006.257.12:50:24.95#ibcon#about to read 6, iclass 10, count 0 2006.257.12:50:24.95#ibcon#read 6, iclass 10, count 0 2006.257.12:50:24.95#ibcon#end of sib2, iclass 10, count 0 2006.257.12:50:24.95#ibcon#*after write, iclass 10, count 0 2006.257.12:50:24.95#ibcon#*before return 0, iclass 10, count 0 2006.257.12:50:24.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:24.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.12:50:24.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.12:50:24.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.12:50:24.95$vck44/vb=7,4 2006.257.12:50:24.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.12:50:24.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.12:50:24.95#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:24.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:25.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:25.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:25.01#ibcon#enter wrdev, iclass 12, count 2 2006.257.12:50:25.01#ibcon#first serial, iclass 12, count 2 2006.257.12:50:25.01#ibcon#enter sib2, iclass 12, count 2 2006.257.12:50:25.01#ibcon#flushed, iclass 12, count 2 2006.257.12:50:25.01#ibcon#about to write, iclass 12, count 2 2006.257.12:50:25.01#ibcon#wrote, iclass 12, count 2 2006.257.12:50:25.01#ibcon#about to read 3, iclass 12, count 2 2006.257.12:50:25.03#ibcon#read 3, iclass 12, count 2 2006.257.12:50:25.03#ibcon#about to read 4, iclass 12, count 2 2006.257.12:50:25.03#ibcon#read 4, iclass 12, count 2 2006.257.12:50:25.03#ibcon#about to read 5, iclass 12, count 2 2006.257.12:50:25.03#ibcon#read 5, iclass 12, count 2 2006.257.12:50:25.03#ibcon#about to read 6, iclass 12, count 2 2006.257.12:50:25.03#ibcon#read 6, iclass 12, count 2 2006.257.12:50:25.03#ibcon#end of sib2, iclass 12, count 2 2006.257.12:50:25.03#ibcon#*mode == 0, iclass 12, count 2 2006.257.12:50:25.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.12:50:25.03#ibcon#[27=AT07-04\r\n] 2006.257.12:50:25.03#ibcon#*before write, iclass 12, count 2 2006.257.12:50:25.03#ibcon#enter sib2, iclass 12, count 2 2006.257.12:50:25.03#ibcon#flushed, iclass 12, count 2 2006.257.12:50:25.03#ibcon#about to write, iclass 12, count 2 2006.257.12:50:25.03#ibcon#wrote, iclass 12, count 2 2006.257.12:50:25.03#ibcon#about to read 3, iclass 12, count 2 2006.257.12:50:25.06#ibcon#read 3, iclass 12, count 2 2006.257.12:50:25.06#ibcon#about to read 4, iclass 12, count 2 2006.257.12:50:25.06#ibcon#read 4, iclass 12, count 2 2006.257.12:50:25.06#ibcon#about to read 5, iclass 12, count 2 2006.257.12:50:25.06#ibcon#read 5, iclass 12, count 2 2006.257.12:50:25.06#ibcon#about to read 6, iclass 12, count 2 2006.257.12:50:25.06#ibcon#read 6, iclass 12, count 2 2006.257.12:50:25.06#ibcon#end of sib2, iclass 12, count 2 2006.257.12:50:25.06#ibcon#*after write, iclass 12, count 2 2006.257.12:50:25.06#ibcon#*before return 0, iclass 12, count 2 2006.257.12:50:25.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:25.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.12:50:25.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.12:50:25.06#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:25.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:25.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:25.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:25.18#ibcon#enter wrdev, iclass 12, count 0 2006.257.12:50:25.18#ibcon#first serial, iclass 12, count 0 2006.257.12:50:25.18#ibcon#enter sib2, iclass 12, count 0 2006.257.12:50:25.18#ibcon#flushed, iclass 12, count 0 2006.257.12:50:25.18#ibcon#about to write, iclass 12, count 0 2006.257.12:50:25.18#ibcon#wrote, iclass 12, count 0 2006.257.12:50:25.18#ibcon#about to read 3, iclass 12, count 0 2006.257.12:50:25.20#ibcon#read 3, iclass 12, count 0 2006.257.12:50:25.20#ibcon#about to read 4, iclass 12, count 0 2006.257.12:50:25.20#ibcon#read 4, iclass 12, count 0 2006.257.12:50:25.20#ibcon#about to read 5, iclass 12, count 0 2006.257.12:50:25.20#ibcon#read 5, iclass 12, count 0 2006.257.12:50:25.20#ibcon#about to read 6, iclass 12, count 0 2006.257.12:50:25.20#ibcon#read 6, iclass 12, count 0 2006.257.12:50:25.20#ibcon#end of sib2, iclass 12, count 0 2006.257.12:50:25.20#ibcon#*mode == 0, iclass 12, count 0 2006.257.12:50:25.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.12:50:25.20#ibcon#[27=USB\r\n] 2006.257.12:50:25.20#ibcon#*before write, iclass 12, count 0 2006.257.12:50:25.20#ibcon#enter sib2, iclass 12, count 0 2006.257.12:50:25.20#ibcon#flushed, iclass 12, count 0 2006.257.12:50:25.20#ibcon#about to write, iclass 12, count 0 2006.257.12:50:25.20#ibcon#wrote, iclass 12, count 0 2006.257.12:50:25.20#ibcon#about to read 3, iclass 12, count 0 2006.257.12:50:25.23#ibcon#read 3, iclass 12, count 0 2006.257.12:50:25.23#ibcon#about to read 4, iclass 12, count 0 2006.257.12:50:25.23#ibcon#read 4, iclass 12, count 0 2006.257.12:50:25.23#ibcon#about to read 5, iclass 12, count 0 2006.257.12:50:25.23#ibcon#read 5, iclass 12, count 0 2006.257.12:50:25.23#ibcon#about to read 6, iclass 12, count 0 2006.257.12:50:25.23#ibcon#read 6, iclass 12, count 0 2006.257.12:50:25.23#ibcon#end of sib2, iclass 12, count 0 2006.257.12:50:25.23#ibcon#*after write, iclass 12, count 0 2006.257.12:50:25.23#ibcon#*before return 0, iclass 12, count 0 2006.257.12:50:25.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:25.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.12:50:25.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.12:50:25.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.12:50:25.23$vck44/vblo=8,744.99 2006.257.12:50:25.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.12:50:25.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.12:50:25.23#ibcon#ireg 17 cls_cnt 0 2006.257.12:50:25.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:25.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:25.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:25.23#ibcon#enter wrdev, iclass 14, count 0 2006.257.12:50:25.23#ibcon#first serial, iclass 14, count 0 2006.257.12:50:25.23#ibcon#enter sib2, iclass 14, count 0 2006.257.12:50:25.23#ibcon#flushed, iclass 14, count 0 2006.257.12:50:25.23#ibcon#about to write, iclass 14, count 0 2006.257.12:50:25.23#ibcon#wrote, iclass 14, count 0 2006.257.12:50:25.23#ibcon#about to read 3, iclass 14, count 0 2006.257.12:50:25.25#ibcon#read 3, iclass 14, count 0 2006.257.12:50:25.25#ibcon#about to read 4, iclass 14, count 0 2006.257.12:50:25.25#ibcon#read 4, iclass 14, count 0 2006.257.12:50:25.25#ibcon#about to read 5, iclass 14, count 0 2006.257.12:50:25.25#ibcon#read 5, iclass 14, count 0 2006.257.12:50:25.25#ibcon#about to read 6, iclass 14, count 0 2006.257.12:50:25.25#ibcon#read 6, iclass 14, count 0 2006.257.12:50:25.25#ibcon#end of sib2, iclass 14, count 0 2006.257.12:50:25.25#ibcon#*mode == 0, iclass 14, count 0 2006.257.12:50:25.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.12:50:25.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:50:25.25#ibcon#*before write, iclass 14, count 0 2006.257.12:50:25.25#ibcon#enter sib2, iclass 14, count 0 2006.257.12:50:25.25#ibcon#flushed, iclass 14, count 0 2006.257.12:50:25.25#ibcon#about to write, iclass 14, count 0 2006.257.12:50:25.25#ibcon#wrote, iclass 14, count 0 2006.257.12:50:25.25#ibcon#about to read 3, iclass 14, count 0 2006.257.12:50:25.29#ibcon#read 3, iclass 14, count 0 2006.257.12:50:25.29#ibcon#about to read 4, iclass 14, count 0 2006.257.12:50:25.29#ibcon#read 4, iclass 14, count 0 2006.257.12:50:25.29#ibcon#about to read 5, iclass 14, count 0 2006.257.12:50:25.29#ibcon#read 5, iclass 14, count 0 2006.257.12:50:25.29#ibcon#about to read 6, iclass 14, count 0 2006.257.12:50:25.29#ibcon#read 6, iclass 14, count 0 2006.257.12:50:25.29#ibcon#end of sib2, iclass 14, count 0 2006.257.12:50:25.29#ibcon#*after write, iclass 14, count 0 2006.257.12:50:25.29#ibcon#*before return 0, iclass 14, count 0 2006.257.12:50:25.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:25.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.12:50:25.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.12:50:25.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.12:50:25.29$vck44/vb=8,4 2006.257.12:50:25.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.12:50:25.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.12:50:25.29#ibcon#ireg 11 cls_cnt 2 2006.257.12:50:25.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:25.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:25.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:25.35#ibcon#enter wrdev, iclass 16, count 2 2006.257.12:50:25.35#ibcon#first serial, iclass 16, count 2 2006.257.12:50:25.35#ibcon#enter sib2, iclass 16, count 2 2006.257.12:50:25.35#ibcon#flushed, iclass 16, count 2 2006.257.12:50:25.35#ibcon#about to write, iclass 16, count 2 2006.257.12:50:25.35#ibcon#wrote, iclass 16, count 2 2006.257.12:50:25.35#ibcon#about to read 3, iclass 16, count 2 2006.257.12:50:25.37#ibcon#read 3, iclass 16, count 2 2006.257.12:50:25.37#ibcon#about to read 4, iclass 16, count 2 2006.257.12:50:25.37#ibcon#read 4, iclass 16, count 2 2006.257.12:50:25.37#ibcon#about to read 5, iclass 16, count 2 2006.257.12:50:25.37#ibcon#read 5, iclass 16, count 2 2006.257.12:50:25.37#ibcon#about to read 6, iclass 16, count 2 2006.257.12:50:25.37#ibcon#read 6, iclass 16, count 2 2006.257.12:50:25.37#ibcon#end of sib2, iclass 16, count 2 2006.257.12:50:25.37#ibcon#*mode == 0, iclass 16, count 2 2006.257.12:50:25.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.12:50:25.37#ibcon#[27=AT08-04\r\n] 2006.257.12:50:25.37#ibcon#*before write, iclass 16, count 2 2006.257.12:50:25.37#ibcon#enter sib2, iclass 16, count 2 2006.257.12:50:25.37#ibcon#flushed, iclass 16, count 2 2006.257.12:50:25.37#ibcon#about to write, iclass 16, count 2 2006.257.12:50:25.37#ibcon#wrote, iclass 16, count 2 2006.257.12:50:25.37#ibcon#about to read 3, iclass 16, count 2 2006.257.12:50:25.40#ibcon#read 3, iclass 16, count 2 2006.257.12:50:25.40#ibcon#about to read 4, iclass 16, count 2 2006.257.12:50:25.40#ibcon#read 4, iclass 16, count 2 2006.257.12:50:25.40#ibcon#about to read 5, iclass 16, count 2 2006.257.12:50:25.40#ibcon#read 5, iclass 16, count 2 2006.257.12:50:25.40#ibcon#about to read 6, iclass 16, count 2 2006.257.12:50:25.40#ibcon#read 6, iclass 16, count 2 2006.257.12:50:25.40#ibcon#end of sib2, iclass 16, count 2 2006.257.12:50:25.40#ibcon#*after write, iclass 16, count 2 2006.257.12:50:25.40#ibcon#*before return 0, iclass 16, count 2 2006.257.12:50:25.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:25.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.12:50:25.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.12:50:25.40#ibcon#ireg 7 cls_cnt 0 2006.257.12:50:25.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:25.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:25.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:25.52#ibcon#enter wrdev, iclass 16, count 0 2006.257.12:50:25.52#ibcon#first serial, iclass 16, count 0 2006.257.12:50:25.52#ibcon#enter sib2, iclass 16, count 0 2006.257.12:50:25.52#ibcon#flushed, iclass 16, count 0 2006.257.12:50:25.52#ibcon#about to write, iclass 16, count 0 2006.257.12:50:25.52#ibcon#wrote, iclass 16, count 0 2006.257.12:50:25.52#ibcon#about to read 3, iclass 16, count 0 2006.257.12:50:25.54#ibcon#read 3, iclass 16, count 0 2006.257.12:50:25.54#ibcon#about to read 4, iclass 16, count 0 2006.257.12:50:25.54#ibcon#read 4, iclass 16, count 0 2006.257.12:50:25.54#ibcon#about to read 5, iclass 16, count 0 2006.257.12:50:25.54#ibcon#read 5, iclass 16, count 0 2006.257.12:50:25.54#ibcon#about to read 6, iclass 16, count 0 2006.257.12:50:25.54#ibcon#read 6, iclass 16, count 0 2006.257.12:50:25.54#ibcon#end of sib2, iclass 16, count 0 2006.257.12:50:25.54#ibcon#*mode == 0, iclass 16, count 0 2006.257.12:50:25.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.12:50:25.54#ibcon#[27=USB\r\n] 2006.257.12:50:25.54#ibcon#*before write, iclass 16, count 0 2006.257.12:50:25.54#ibcon#enter sib2, iclass 16, count 0 2006.257.12:50:25.54#ibcon#flushed, iclass 16, count 0 2006.257.12:50:25.54#ibcon#about to write, iclass 16, count 0 2006.257.12:50:25.54#ibcon#wrote, iclass 16, count 0 2006.257.12:50:25.54#ibcon#about to read 3, iclass 16, count 0 2006.257.12:50:25.57#ibcon#read 3, iclass 16, count 0 2006.257.12:50:25.57#ibcon#about to read 4, iclass 16, count 0 2006.257.12:50:25.57#ibcon#read 4, iclass 16, count 0 2006.257.12:50:25.57#ibcon#about to read 5, iclass 16, count 0 2006.257.12:50:25.57#ibcon#read 5, iclass 16, count 0 2006.257.12:50:25.57#ibcon#about to read 6, iclass 16, count 0 2006.257.12:50:25.57#ibcon#read 6, iclass 16, count 0 2006.257.12:50:25.57#ibcon#end of sib2, iclass 16, count 0 2006.257.12:50:25.57#ibcon#*after write, iclass 16, count 0 2006.257.12:50:25.57#ibcon#*before return 0, iclass 16, count 0 2006.257.12:50:25.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:25.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.12:50:25.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.12:50:25.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.12:50:25.57$vck44/vabw=wide 2006.257.12:50:25.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.12:50:25.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.12:50:25.57#ibcon#ireg 8 cls_cnt 0 2006.257.12:50:25.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:50:25.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:50:25.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:50:25.57#ibcon#enter wrdev, iclass 18, count 0 2006.257.12:50:25.57#ibcon#first serial, iclass 18, count 0 2006.257.12:50:25.57#ibcon#enter sib2, iclass 18, count 0 2006.257.12:50:25.57#ibcon#flushed, iclass 18, count 0 2006.257.12:50:25.57#ibcon#about to write, iclass 18, count 0 2006.257.12:50:25.57#ibcon#wrote, iclass 18, count 0 2006.257.12:50:25.57#ibcon#about to read 3, iclass 18, count 0 2006.257.12:50:25.59#ibcon#read 3, iclass 18, count 0 2006.257.12:50:25.59#ibcon#about to read 4, iclass 18, count 0 2006.257.12:50:25.59#ibcon#read 4, iclass 18, count 0 2006.257.12:50:25.59#ibcon#about to read 5, iclass 18, count 0 2006.257.12:50:25.59#ibcon#read 5, iclass 18, count 0 2006.257.12:50:25.59#ibcon#about to read 6, iclass 18, count 0 2006.257.12:50:25.59#ibcon#read 6, iclass 18, count 0 2006.257.12:50:25.59#ibcon#end of sib2, iclass 18, count 0 2006.257.12:50:25.59#ibcon#*mode == 0, iclass 18, count 0 2006.257.12:50:25.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.12:50:25.59#ibcon#[25=BW32\r\n] 2006.257.12:50:25.59#ibcon#*before write, iclass 18, count 0 2006.257.12:50:25.59#ibcon#enter sib2, iclass 18, count 0 2006.257.12:50:25.59#ibcon#flushed, iclass 18, count 0 2006.257.12:50:25.59#ibcon#about to write, iclass 18, count 0 2006.257.12:50:25.59#ibcon#wrote, iclass 18, count 0 2006.257.12:50:25.59#ibcon#about to read 3, iclass 18, count 0 2006.257.12:50:25.62#ibcon#read 3, iclass 18, count 0 2006.257.12:50:25.62#ibcon#about to read 4, iclass 18, count 0 2006.257.12:50:25.62#ibcon#read 4, iclass 18, count 0 2006.257.12:50:25.62#ibcon#about to read 5, iclass 18, count 0 2006.257.12:50:25.62#ibcon#read 5, iclass 18, count 0 2006.257.12:50:25.62#ibcon#about to read 6, iclass 18, count 0 2006.257.12:50:25.62#ibcon#read 6, iclass 18, count 0 2006.257.12:50:25.62#ibcon#end of sib2, iclass 18, count 0 2006.257.12:50:25.62#ibcon#*after write, iclass 18, count 0 2006.257.12:50:25.62#ibcon#*before return 0, iclass 18, count 0 2006.257.12:50:25.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:50:25.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.12:50:25.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.12:50:25.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.12:50:25.62$vck44/vbbw=wide 2006.257.12:50:25.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.12:50:25.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.12:50:25.62#ibcon#ireg 8 cls_cnt 0 2006.257.12:50:25.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:50:25.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:50:25.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:50:25.69#ibcon#enter wrdev, iclass 20, count 0 2006.257.12:50:25.69#ibcon#first serial, iclass 20, count 0 2006.257.12:50:25.69#ibcon#enter sib2, iclass 20, count 0 2006.257.12:50:25.69#ibcon#flushed, iclass 20, count 0 2006.257.12:50:25.69#ibcon#about to write, iclass 20, count 0 2006.257.12:50:25.69#ibcon#wrote, iclass 20, count 0 2006.257.12:50:25.69#ibcon#about to read 3, iclass 20, count 0 2006.257.12:50:25.71#ibcon#read 3, iclass 20, count 0 2006.257.12:50:25.71#ibcon#about to read 4, iclass 20, count 0 2006.257.12:50:25.71#ibcon#read 4, iclass 20, count 0 2006.257.12:50:25.71#ibcon#about to read 5, iclass 20, count 0 2006.257.12:50:25.71#ibcon#read 5, iclass 20, count 0 2006.257.12:50:25.71#ibcon#about to read 6, iclass 20, count 0 2006.257.12:50:25.71#ibcon#read 6, iclass 20, count 0 2006.257.12:50:25.71#ibcon#end of sib2, iclass 20, count 0 2006.257.12:50:25.71#ibcon#*mode == 0, iclass 20, count 0 2006.257.12:50:25.71#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.12:50:25.71#ibcon#[27=BW32\r\n] 2006.257.12:50:25.71#ibcon#*before write, iclass 20, count 0 2006.257.12:50:25.71#ibcon#enter sib2, iclass 20, count 0 2006.257.12:50:25.71#ibcon#flushed, iclass 20, count 0 2006.257.12:50:25.71#ibcon#about to write, iclass 20, count 0 2006.257.12:50:25.71#ibcon#wrote, iclass 20, count 0 2006.257.12:50:25.71#ibcon#about to read 3, iclass 20, count 0 2006.257.12:50:25.74#ibcon#read 3, iclass 20, count 0 2006.257.12:50:25.74#ibcon#about to read 4, iclass 20, count 0 2006.257.12:50:25.74#ibcon#read 4, iclass 20, count 0 2006.257.12:50:25.74#ibcon#about to read 5, iclass 20, count 0 2006.257.12:50:25.74#ibcon#read 5, iclass 20, count 0 2006.257.12:50:25.74#ibcon#about to read 6, iclass 20, count 0 2006.257.12:50:25.74#ibcon#read 6, iclass 20, count 0 2006.257.12:50:25.74#ibcon#end of sib2, iclass 20, count 0 2006.257.12:50:25.74#ibcon#*after write, iclass 20, count 0 2006.257.12:50:25.74#ibcon#*before return 0, iclass 20, count 0 2006.257.12:50:25.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:50:25.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.12:50:25.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.12:50:25.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.12:50:25.74$setupk4/ifdk4 2006.257.12:50:25.74$ifdk4/lo= 2006.257.12:50:25.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:50:25.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:50:25.74$ifdk4/patch= 2006.257.12:50:25.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:50:25.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:50:25.74$setupk4/!*+20s 2006.257.12:50:32.92#abcon#<5=/14 1.6 4.2 17.83 961013.8\r\n> 2006.257.12:50:32.94#abcon#{5=INTERFACE CLEAR} 2006.257.12:50:33.00#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:50:38.14#trakl#Source acquired 2006.257.12:50:39.14#flagr#flagr/antenna,acquired 2006.257.12:50:40.25$setupk4/"tpicd 2006.257.12:50:40.25$setupk4/echo=off 2006.257.12:50:40.25$setupk4/xlog=off 2006.257.12:50:40.25:!2006.257.12:51:36 2006.257.12:51:36.00:preob 2006.257.12:51:37.14/onsource/TRACKING 2006.257.12:51:37.14:!2006.257.12:51:46 2006.257.12:51:46.00:"tape 2006.257.12:51:46.00:"st=record 2006.257.12:51:46.00:data_valid=on 2006.257.12:51:46.00:midob 2006.257.12:51:46.14/onsource/TRACKING 2006.257.12:51:46.14/wx/17.82,1013.8,96 2006.257.12:51:46.24/cable/+6.4818E-03 2006.257.12:51:47.33/va/01,08,usb,yes,31,34 2006.257.12:51:47.33/va/02,07,usb,yes,34,35 2006.257.12:51:47.33/va/03,08,usb,yes,31,32 2006.257.12:51:47.33/va/04,07,usb,yes,35,37 2006.257.12:51:47.33/va/05,04,usb,yes,31,32 2006.257.12:51:47.33/va/06,04,usb,yes,35,35 2006.257.12:51:47.33/va/07,04,usb,yes,36,36 2006.257.12:51:47.33/va/08,04,usb,yes,30,37 2006.257.12:51:47.56/valo/01,524.99,yes,locked 2006.257.12:51:47.56/valo/02,534.99,yes,locked 2006.257.12:51:47.56/valo/03,564.99,yes,locked 2006.257.12:51:47.56/valo/04,624.99,yes,locked 2006.257.12:51:47.56/valo/05,734.99,yes,locked 2006.257.12:51:47.56/valo/06,814.99,yes,locked 2006.257.12:51:47.56/valo/07,864.99,yes,locked 2006.257.12:51:47.56/valo/08,884.99,yes,locked 2006.257.12:51:48.65/vb/01,04,usb,yes,31,29 2006.257.12:51:48.65/vb/02,05,usb,yes,30,29 2006.257.12:51:48.65/vb/03,04,usb,yes,30,33 2006.257.12:51:48.65/vb/04,05,usb,yes,31,30 2006.257.12:51:48.65/vb/05,04,usb,yes,27,30 2006.257.12:51:48.65/vb/06,04,usb,yes,32,28 2006.257.12:51:48.65/vb/07,04,usb,yes,32,31 2006.257.12:51:48.65/vb/08,04,usb,yes,29,32 2006.257.12:51:48.88/vblo/01,629.99,yes,locked 2006.257.12:51:48.88/vblo/02,634.99,yes,locked 2006.257.12:51:48.88/vblo/03,649.99,yes,locked 2006.257.12:51:48.88/vblo/04,679.99,yes,locked 2006.257.12:51:48.88/vblo/05,709.99,yes,locked 2006.257.12:51:48.88/vblo/06,719.99,yes,locked 2006.257.12:51:48.88/vblo/07,734.99,yes,locked 2006.257.12:51:48.88/vblo/08,744.99,yes,locked 2006.257.12:51:49.03/vabw/8 2006.257.12:51:49.18/vbbw/8 2006.257.12:51:49.27/xfe/off,on,15.5 2006.257.12:51:49.64/ifatt/23,28,28,28 2006.257.12:51:50.07/fmout-gps/S +4.59E-07 2006.257.12:51:50.11:!2006.257.12:52:46 2006.257.12:52:46.01:data_valid=off 2006.257.12:52:46.01:"et 2006.257.12:52:46.01:!+3s 2006.257.12:52:49.02:"tape 2006.257.12:52:49.02:postob 2006.257.12:52:49.20/cable/+6.4827E-03 2006.257.12:52:49.20/wx/17.80,1013.7,96 2006.257.12:52:49.26/fmout-gps/S +4.59E-07 2006.257.12:52:49.26:scan_name=257-1256,jd0609,240 2006.257.12:52:49.26:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.257.12:52:50.14#flagr#flagr/antenna,new-source 2006.257.12:52:50.14:checkk5 2006.257.12:52:50.52/chk_autoobs//k5ts1/ autoobs is running! 2006.257.12:52:50.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.12:52:51.32/chk_autoobs//k5ts3/ autoobs is running! 2006.257.12:52:51.71/chk_autoobs//k5ts4/ autoobs is running! 2006.257.12:52:52.13/chk_obsdata//k5ts1/T2571251??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.12:52:52.51/chk_obsdata//k5ts2/T2571251??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.12:52:52.92/chk_obsdata//k5ts3/T2571251??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.12:52:53.33/chk_obsdata//k5ts4/T2571251??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.12:52:54.06/k5log//k5ts1_log_newline 2006.257.12:52:54.77/k5log//k5ts2_log_newline 2006.257.12:52:55.51/k5log//k5ts3_log_newline 2006.257.12:52:56.21/k5log//k5ts4_log_newline 2006.257.12:52:56.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.12:52:56.24:setupk4=1 2006.257.12:52:56.24$setupk4/echo=on 2006.257.12:52:56.24$setupk4/pcalon 2006.257.12:52:56.24$pcalon/"no phase cal control is implemented here 2006.257.12:52:56.24$setupk4/"tpicd=stop 2006.257.12:52:56.24$setupk4/"rec=synch_on 2006.257.12:52:56.24$setupk4/"rec_mode=128 2006.257.12:52:56.24$setupk4/!* 2006.257.12:52:56.24$setupk4/recpk4 2006.257.12:52:56.24$recpk4/recpatch= 2006.257.12:52:56.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.12:52:56.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.12:52:56.24$setupk4/vck44 2006.257.12:52:56.24$vck44/valo=1,524.99 2006.257.12:52:56.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.12:52:56.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.12:52:56.24#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:56.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:56.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:56.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:56.24#ibcon#enter wrdev, iclass 13, count 0 2006.257.12:52:56.24#ibcon#first serial, iclass 13, count 0 2006.257.12:52:56.24#ibcon#enter sib2, iclass 13, count 0 2006.257.12:52:56.24#ibcon#flushed, iclass 13, count 0 2006.257.12:52:56.24#ibcon#about to write, iclass 13, count 0 2006.257.12:52:56.24#ibcon#wrote, iclass 13, count 0 2006.257.12:52:56.24#ibcon#about to read 3, iclass 13, count 0 2006.257.12:52:56.26#ibcon#read 3, iclass 13, count 0 2006.257.12:52:56.26#ibcon#about to read 4, iclass 13, count 0 2006.257.12:52:56.26#ibcon#read 4, iclass 13, count 0 2006.257.12:52:56.26#ibcon#about to read 5, iclass 13, count 0 2006.257.12:52:56.26#ibcon#read 5, iclass 13, count 0 2006.257.12:52:56.26#ibcon#about to read 6, iclass 13, count 0 2006.257.12:52:56.26#ibcon#read 6, iclass 13, count 0 2006.257.12:52:56.26#ibcon#end of sib2, iclass 13, count 0 2006.257.12:52:56.26#ibcon#*mode == 0, iclass 13, count 0 2006.257.12:52:56.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.12:52:56.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.12:52:56.26#ibcon#*before write, iclass 13, count 0 2006.257.12:52:56.26#ibcon#enter sib2, iclass 13, count 0 2006.257.12:52:56.26#ibcon#flushed, iclass 13, count 0 2006.257.12:52:56.26#ibcon#about to write, iclass 13, count 0 2006.257.12:52:56.26#ibcon#wrote, iclass 13, count 0 2006.257.12:52:56.26#ibcon#about to read 3, iclass 13, count 0 2006.257.12:52:56.31#ibcon#read 3, iclass 13, count 0 2006.257.12:52:56.31#ibcon#about to read 4, iclass 13, count 0 2006.257.12:52:56.31#ibcon#read 4, iclass 13, count 0 2006.257.12:52:56.31#ibcon#about to read 5, iclass 13, count 0 2006.257.12:52:56.31#ibcon#read 5, iclass 13, count 0 2006.257.12:52:56.31#ibcon#about to read 6, iclass 13, count 0 2006.257.12:52:56.31#ibcon#read 6, iclass 13, count 0 2006.257.12:52:56.31#ibcon#end of sib2, iclass 13, count 0 2006.257.12:52:56.31#ibcon#*after write, iclass 13, count 0 2006.257.12:52:56.31#ibcon#*before return 0, iclass 13, count 0 2006.257.12:52:56.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:56.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:56.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.12:52:56.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.12:52:56.31$vck44/va=1,8 2006.257.12:52:56.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.12:52:56.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.12:52:56.31#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:56.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:56.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:56.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:56.31#ibcon#enter wrdev, iclass 15, count 2 2006.257.12:52:56.31#ibcon#first serial, iclass 15, count 2 2006.257.12:52:56.31#ibcon#enter sib2, iclass 15, count 2 2006.257.12:52:56.31#ibcon#flushed, iclass 15, count 2 2006.257.12:52:56.31#ibcon#about to write, iclass 15, count 2 2006.257.12:52:56.31#ibcon#wrote, iclass 15, count 2 2006.257.12:52:56.31#ibcon#about to read 3, iclass 15, count 2 2006.257.12:52:56.33#ibcon#read 3, iclass 15, count 2 2006.257.12:52:56.33#ibcon#about to read 4, iclass 15, count 2 2006.257.12:52:56.33#ibcon#read 4, iclass 15, count 2 2006.257.12:52:56.33#ibcon#about to read 5, iclass 15, count 2 2006.257.12:52:56.33#ibcon#read 5, iclass 15, count 2 2006.257.12:52:56.33#ibcon#about to read 6, iclass 15, count 2 2006.257.12:52:56.33#ibcon#read 6, iclass 15, count 2 2006.257.12:52:56.33#ibcon#end of sib2, iclass 15, count 2 2006.257.12:52:56.33#ibcon#*mode == 0, iclass 15, count 2 2006.257.12:52:56.33#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.12:52:56.33#ibcon#[25=AT01-08\r\n] 2006.257.12:52:56.33#ibcon#*before write, iclass 15, count 2 2006.257.12:52:56.33#ibcon#enter sib2, iclass 15, count 2 2006.257.12:52:56.33#ibcon#flushed, iclass 15, count 2 2006.257.12:52:56.33#ibcon#about to write, iclass 15, count 2 2006.257.12:52:56.33#ibcon#wrote, iclass 15, count 2 2006.257.12:52:56.33#ibcon#about to read 3, iclass 15, count 2 2006.257.12:52:56.36#ibcon#read 3, iclass 15, count 2 2006.257.12:52:56.36#ibcon#about to read 4, iclass 15, count 2 2006.257.12:52:56.36#ibcon#read 4, iclass 15, count 2 2006.257.12:52:56.36#ibcon#about to read 5, iclass 15, count 2 2006.257.12:52:56.36#ibcon#read 5, iclass 15, count 2 2006.257.12:52:56.36#ibcon#about to read 6, iclass 15, count 2 2006.257.12:52:56.36#ibcon#read 6, iclass 15, count 2 2006.257.12:52:56.36#ibcon#end of sib2, iclass 15, count 2 2006.257.12:52:56.36#ibcon#*after write, iclass 15, count 2 2006.257.12:52:56.36#ibcon#*before return 0, iclass 15, count 2 2006.257.12:52:56.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:56.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:56.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.12:52:56.36#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:56.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:56.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:56.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:56.48#ibcon#enter wrdev, iclass 15, count 0 2006.257.12:52:56.48#ibcon#first serial, iclass 15, count 0 2006.257.12:52:56.48#ibcon#enter sib2, iclass 15, count 0 2006.257.12:52:56.48#ibcon#flushed, iclass 15, count 0 2006.257.12:52:56.48#ibcon#about to write, iclass 15, count 0 2006.257.12:52:56.48#ibcon#wrote, iclass 15, count 0 2006.257.12:52:56.48#ibcon#about to read 3, iclass 15, count 0 2006.257.12:52:56.50#ibcon#read 3, iclass 15, count 0 2006.257.12:52:56.50#ibcon#about to read 4, iclass 15, count 0 2006.257.12:52:56.50#ibcon#read 4, iclass 15, count 0 2006.257.12:52:56.50#ibcon#about to read 5, iclass 15, count 0 2006.257.12:52:56.50#ibcon#read 5, iclass 15, count 0 2006.257.12:52:56.50#ibcon#about to read 6, iclass 15, count 0 2006.257.12:52:56.50#ibcon#read 6, iclass 15, count 0 2006.257.12:52:56.50#ibcon#end of sib2, iclass 15, count 0 2006.257.12:52:56.50#ibcon#*mode == 0, iclass 15, count 0 2006.257.12:52:56.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.12:52:56.50#ibcon#[25=USB\r\n] 2006.257.12:52:56.50#ibcon#*before write, iclass 15, count 0 2006.257.12:52:56.50#ibcon#enter sib2, iclass 15, count 0 2006.257.12:52:56.50#ibcon#flushed, iclass 15, count 0 2006.257.12:52:56.50#ibcon#about to write, iclass 15, count 0 2006.257.12:52:56.50#ibcon#wrote, iclass 15, count 0 2006.257.12:52:56.50#ibcon#about to read 3, iclass 15, count 0 2006.257.12:52:56.53#ibcon#read 3, iclass 15, count 0 2006.257.12:52:56.53#ibcon#about to read 4, iclass 15, count 0 2006.257.12:52:56.53#ibcon#read 4, iclass 15, count 0 2006.257.12:52:56.53#ibcon#about to read 5, iclass 15, count 0 2006.257.12:52:56.53#ibcon#read 5, iclass 15, count 0 2006.257.12:52:56.53#ibcon#about to read 6, iclass 15, count 0 2006.257.12:52:56.53#ibcon#read 6, iclass 15, count 0 2006.257.12:52:56.53#ibcon#end of sib2, iclass 15, count 0 2006.257.12:52:56.53#ibcon#*after write, iclass 15, count 0 2006.257.12:52:56.53#ibcon#*before return 0, iclass 15, count 0 2006.257.12:52:56.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:56.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:56.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.12:52:56.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.12:52:56.53$vck44/valo=2,534.99 2006.257.12:52:56.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.12:52:56.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.12:52:56.53#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:56.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:56.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:56.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:56.53#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:52:56.53#ibcon#first serial, iclass 17, count 0 2006.257.12:52:56.53#ibcon#enter sib2, iclass 17, count 0 2006.257.12:52:56.53#ibcon#flushed, iclass 17, count 0 2006.257.12:52:56.53#ibcon#about to write, iclass 17, count 0 2006.257.12:52:56.53#ibcon#wrote, iclass 17, count 0 2006.257.12:52:56.53#ibcon#about to read 3, iclass 17, count 0 2006.257.12:52:56.55#ibcon#read 3, iclass 17, count 0 2006.257.12:52:56.55#ibcon#about to read 4, iclass 17, count 0 2006.257.12:52:56.55#ibcon#read 4, iclass 17, count 0 2006.257.12:52:56.55#ibcon#about to read 5, iclass 17, count 0 2006.257.12:52:56.55#ibcon#read 5, iclass 17, count 0 2006.257.12:52:56.55#ibcon#about to read 6, iclass 17, count 0 2006.257.12:52:56.55#ibcon#read 6, iclass 17, count 0 2006.257.12:52:56.55#ibcon#end of sib2, iclass 17, count 0 2006.257.12:52:56.55#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:52:56.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:52:56.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.12:52:56.55#ibcon#*before write, iclass 17, count 0 2006.257.12:52:56.55#ibcon#enter sib2, iclass 17, count 0 2006.257.12:52:56.55#ibcon#flushed, iclass 17, count 0 2006.257.12:52:56.55#ibcon#about to write, iclass 17, count 0 2006.257.12:52:56.55#ibcon#wrote, iclass 17, count 0 2006.257.12:52:56.55#ibcon#about to read 3, iclass 17, count 0 2006.257.12:52:56.59#ibcon#read 3, iclass 17, count 0 2006.257.12:52:56.59#ibcon#about to read 4, iclass 17, count 0 2006.257.12:52:56.59#ibcon#read 4, iclass 17, count 0 2006.257.12:52:56.59#ibcon#about to read 5, iclass 17, count 0 2006.257.12:52:56.59#ibcon#read 5, iclass 17, count 0 2006.257.12:52:56.59#ibcon#about to read 6, iclass 17, count 0 2006.257.12:52:56.59#ibcon#read 6, iclass 17, count 0 2006.257.12:52:56.59#ibcon#end of sib2, iclass 17, count 0 2006.257.12:52:56.59#ibcon#*after write, iclass 17, count 0 2006.257.12:52:56.59#ibcon#*before return 0, iclass 17, count 0 2006.257.12:52:56.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:56.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:56.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:52:56.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:52:56.59$vck44/va=2,7 2006.257.12:52:56.59#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.12:52:56.59#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.12:52:56.59#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:56.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:56.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:56.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:56.65#ibcon#enter wrdev, iclass 19, count 2 2006.257.12:52:56.65#ibcon#first serial, iclass 19, count 2 2006.257.12:52:56.65#ibcon#enter sib2, iclass 19, count 2 2006.257.12:52:56.65#ibcon#flushed, iclass 19, count 2 2006.257.12:52:56.65#ibcon#about to write, iclass 19, count 2 2006.257.12:52:56.65#ibcon#wrote, iclass 19, count 2 2006.257.12:52:56.65#ibcon#about to read 3, iclass 19, count 2 2006.257.12:52:56.67#ibcon#read 3, iclass 19, count 2 2006.257.12:52:56.67#ibcon#about to read 4, iclass 19, count 2 2006.257.12:52:56.67#ibcon#read 4, iclass 19, count 2 2006.257.12:52:56.67#ibcon#about to read 5, iclass 19, count 2 2006.257.12:52:56.67#ibcon#read 5, iclass 19, count 2 2006.257.12:52:56.67#ibcon#about to read 6, iclass 19, count 2 2006.257.12:52:56.67#ibcon#read 6, iclass 19, count 2 2006.257.12:52:56.67#ibcon#end of sib2, iclass 19, count 2 2006.257.12:52:56.67#ibcon#*mode == 0, iclass 19, count 2 2006.257.12:52:56.67#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.12:52:56.67#ibcon#[25=AT02-07\r\n] 2006.257.12:52:56.67#ibcon#*before write, iclass 19, count 2 2006.257.12:52:56.67#ibcon#enter sib2, iclass 19, count 2 2006.257.12:52:56.67#ibcon#flushed, iclass 19, count 2 2006.257.12:52:56.67#ibcon#about to write, iclass 19, count 2 2006.257.12:52:56.67#ibcon#wrote, iclass 19, count 2 2006.257.12:52:56.67#ibcon#about to read 3, iclass 19, count 2 2006.257.12:52:56.70#ibcon#read 3, iclass 19, count 2 2006.257.12:52:56.70#ibcon#about to read 4, iclass 19, count 2 2006.257.12:52:56.70#ibcon#read 4, iclass 19, count 2 2006.257.12:52:56.70#ibcon#about to read 5, iclass 19, count 2 2006.257.12:52:56.70#ibcon#read 5, iclass 19, count 2 2006.257.12:52:56.70#ibcon#about to read 6, iclass 19, count 2 2006.257.12:52:56.70#ibcon#read 6, iclass 19, count 2 2006.257.12:52:56.70#ibcon#end of sib2, iclass 19, count 2 2006.257.12:52:56.70#ibcon#*after write, iclass 19, count 2 2006.257.12:52:56.70#ibcon#*before return 0, iclass 19, count 2 2006.257.12:52:56.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:56.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:56.70#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.12:52:56.70#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:56.70#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:56.82#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:56.82#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:56.82#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:52:56.82#ibcon#first serial, iclass 19, count 0 2006.257.12:52:56.82#ibcon#enter sib2, iclass 19, count 0 2006.257.12:52:56.82#ibcon#flushed, iclass 19, count 0 2006.257.12:52:56.82#ibcon#about to write, iclass 19, count 0 2006.257.12:52:56.82#ibcon#wrote, iclass 19, count 0 2006.257.12:52:56.82#ibcon#about to read 3, iclass 19, count 0 2006.257.12:52:56.84#ibcon#read 3, iclass 19, count 0 2006.257.12:52:56.84#ibcon#about to read 4, iclass 19, count 0 2006.257.12:52:56.84#ibcon#read 4, iclass 19, count 0 2006.257.12:52:56.84#ibcon#about to read 5, iclass 19, count 0 2006.257.12:52:56.84#ibcon#read 5, iclass 19, count 0 2006.257.12:52:56.84#ibcon#about to read 6, iclass 19, count 0 2006.257.12:52:56.84#ibcon#read 6, iclass 19, count 0 2006.257.12:52:56.84#ibcon#end of sib2, iclass 19, count 0 2006.257.12:52:56.84#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:52:56.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:52:56.84#ibcon#[25=USB\r\n] 2006.257.12:52:56.84#ibcon#*before write, iclass 19, count 0 2006.257.12:52:56.84#ibcon#enter sib2, iclass 19, count 0 2006.257.12:52:56.84#ibcon#flushed, iclass 19, count 0 2006.257.12:52:56.84#ibcon#about to write, iclass 19, count 0 2006.257.12:52:56.84#ibcon#wrote, iclass 19, count 0 2006.257.12:52:56.84#ibcon#about to read 3, iclass 19, count 0 2006.257.12:52:56.87#ibcon#read 3, iclass 19, count 0 2006.257.12:52:56.87#ibcon#about to read 4, iclass 19, count 0 2006.257.12:52:56.87#ibcon#read 4, iclass 19, count 0 2006.257.12:52:56.87#ibcon#about to read 5, iclass 19, count 0 2006.257.12:52:56.87#ibcon#read 5, iclass 19, count 0 2006.257.12:52:56.87#ibcon#about to read 6, iclass 19, count 0 2006.257.12:52:56.87#ibcon#read 6, iclass 19, count 0 2006.257.12:52:56.87#ibcon#end of sib2, iclass 19, count 0 2006.257.12:52:56.87#ibcon#*after write, iclass 19, count 0 2006.257.12:52:56.87#ibcon#*before return 0, iclass 19, count 0 2006.257.12:52:56.87#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:56.87#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:56.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:52:56.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:52:56.87$vck44/valo=3,564.99 2006.257.12:52:56.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.12:52:56.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.12:52:56.87#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:56.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:56.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:56.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:56.87#ibcon#enter wrdev, iclass 21, count 0 2006.257.12:52:56.87#ibcon#first serial, iclass 21, count 0 2006.257.12:52:56.87#ibcon#enter sib2, iclass 21, count 0 2006.257.12:52:56.87#ibcon#flushed, iclass 21, count 0 2006.257.12:52:56.87#ibcon#about to write, iclass 21, count 0 2006.257.12:52:56.87#ibcon#wrote, iclass 21, count 0 2006.257.12:52:56.87#ibcon#about to read 3, iclass 21, count 0 2006.257.12:52:56.89#ibcon#read 3, iclass 21, count 0 2006.257.12:52:56.89#ibcon#about to read 4, iclass 21, count 0 2006.257.12:52:56.89#ibcon#read 4, iclass 21, count 0 2006.257.12:52:56.89#ibcon#about to read 5, iclass 21, count 0 2006.257.12:52:56.89#ibcon#read 5, iclass 21, count 0 2006.257.12:52:56.89#ibcon#about to read 6, iclass 21, count 0 2006.257.12:52:56.89#ibcon#read 6, iclass 21, count 0 2006.257.12:52:56.89#ibcon#end of sib2, iclass 21, count 0 2006.257.12:52:56.89#ibcon#*mode == 0, iclass 21, count 0 2006.257.12:52:56.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.12:52:56.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.12:52:56.89#ibcon#*before write, iclass 21, count 0 2006.257.12:52:56.89#ibcon#enter sib2, iclass 21, count 0 2006.257.12:52:56.89#ibcon#flushed, iclass 21, count 0 2006.257.12:52:56.89#ibcon#about to write, iclass 21, count 0 2006.257.12:52:56.89#ibcon#wrote, iclass 21, count 0 2006.257.12:52:56.89#ibcon#about to read 3, iclass 21, count 0 2006.257.12:52:56.93#ibcon#read 3, iclass 21, count 0 2006.257.12:52:56.93#ibcon#about to read 4, iclass 21, count 0 2006.257.12:52:56.93#ibcon#read 4, iclass 21, count 0 2006.257.12:52:56.93#ibcon#about to read 5, iclass 21, count 0 2006.257.12:52:56.93#ibcon#read 5, iclass 21, count 0 2006.257.12:52:56.93#ibcon#about to read 6, iclass 21, count 0 2006.257.12:52:56.93#ibcon#read 6, iclass 21, count 0 2006.257.12:52:56.93#ibcon#end of sib2, iclass 21, count 0 2006.257.12:52:56.93#ibcon#*after write, iclass 21, count 0 2006.257.12:52:56.93#ibcon#*before return 0, iclass 21, count 0 2006.257.12:52:56.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:56.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:56.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.12:52:56.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.12:52:56.93$vck44/va=3,8 2006.257.12:52:56.93#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.12:52:56.93#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.12:52:56.93#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:56.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:52:56.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:52:56.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:52:56.99#ibcon#enter wrdev, iclass 23, count 2 2006.257.12:52:56.99#ibcon#first serial, iclass 23, count 2 2006.257.12:52:56.99#ibcon#enter sib2, iclass 23, count 2 2006.257.12:52:56.99#ibcon#flushed, iclass 23, count 2 2006.257.12:52:56.99#ibcon#about to write, iclass 23, count 2 2006.257.12:52:56.99#ibcon#wrote, iclass 23, count 2 2006.257.12:52:56.99#ibcon#about to read 3, iclass 23, count 2 2006.257.12:52:57.01#ibcon#read 3, iclass 23, count 2 2006.257.12:52:57.01#ibcon#about to read 4, iclass 23, count 2 2006.257.12:52:57.01#ibcon#read 4, iclass 23, count 2 2006.257.12:52:57.01#ibcon#about to read 5, iclass 23, count 2 2006.257.12:52:57.01#ibcon#read 5, iclass 23, count 2 2006.257.12:52:57.01#ibcon#about to read 6, iclass 23, count 2 2006.257.12:52:57.01#ibcon#read 6, iclass 23, count 2 2006.257.12:52:57.01#ibcon#end of sib2, iclass 23, count 2 2006.257.12:52:57.01#ibcon#*mode == 0, iclass 23, count 2 2006.257.12:52:57.01#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.12:52:57.01#ibcon#[25=AT03-08\r\n] 2006.257.12:52:57.01#ibcon#*before write, iclass 23, count 2 2006.257.12:52:57.01#ibcon#enter sib2, iclass 23, count 2 2006.257.12:52:57.01#ibcon#flushed, iclass 23, count 2 2006.257.12:52:57.01#ibcon#about to write, iclass 23, count 2 2006.257.12:52:57.01#ibcon#wrote, iclass 23, count 2 2006.257.12:52:57.01#ibcon#about to read 3, iclass 23, count 2 2006.257.12:52:57.04#ibcon#read 3, iclass 23, count 2 2006.257.12:52:57.04#ibcon#about to read 4, iclass 23, count 2 2006.257.12:52:57.04#ibcon#read 4, iclass 23, count 2 2006.257.12:52:57.04#ibcon#about to read 5, iclass 23, count 2 2006.257.12:52:57.04#ibcon#read 5, iclass 23, count 2 2006.257.12:52:57.04#ibcon#about to read 6, iclass 23, count 2 2006.257.12:52:57.04#ibcon#read 6, iclass 23, count 2 2006.257.12:52:57.04#ibcon#end of sib2, iclass 23, count 2 2006.257.12:52:57.04#ibcon#*after write, iclass 23, count 2 2006.257.12:52:57.04#ibcon#*before return 0, iclass 23, count 2 2006.257.12:52:57.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:52:57.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:52:57.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.12:52:57.04#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:57.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:52:57.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:52:57.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:52:57.16#ibcon#enter wrdev, iclass 23, count 0 2006.257.12:52:57.16#ibcon#first serial, iclass 23, count 0 2006.257.12:52:57.16#ibcon#enter sib2, iclass 23, count 0 2006.257.12:52:57.16#ibcon#flushed, iclass 23, count 0 2006.257.12:52:57.16#ibcon#about to write, iclass 23, count 0 2006.257.12:52:57.16#ibcon#wrote, iclass 23, count 0 2006.257.12:52:57.16#ibcon#about to read 3, iclass 23, count 0 2006.257.12:52:57.18#ibcon#read 3, iclass 23, count 0 2006.257.12:52:57.18#ibcon#about to read 4, iclass 23, count 0 2006.257.12:52:57.18#ibcon#read 4, iclass 23, count 0 2006.257.12:52:57.18#ibcon#about to read 5, iclass 23, count 0 2006.257.12:52:57.18#ibcon#read 5, iclass 23, count 0 2006.257.12:52:57.18#ibcon#about to read 6, iclass 23, count 0 2006.257.12:52:57.18#ibcon#read 6, iclass 23, count 0 2006.257.12:52:57.18#ibcon#end of sib2, iclass 23, count 0 2006.257.12:52:57.18#ibcon#*mode == 0, iclass 23, count 0 2006.257.12:52:57.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.12:52:57.18#ibcon#[25=USB\r\n] 2006.257.12:52:57.18#ibcon#*before write, iclass 23, count 0 2006.257.12:52:57.18#ibcon#enter sib2, iclass 23, count 0 2006.257.12:52:57.18#ibcon#flushed, iclass 23, count 0 2006.257.12:52:57.18#ibcon#about to write, iclass 23, count 0 2006.257.12:52:57.18#ibcon#wrote, iclass 23, count 0 2006.257.12:52:57.18#ibcon#about to read 3, iclass 23, count 0 2006.257.12:52:57.21#ibcon#read 3, iclass 23, count 0 2006.257.12:52:57.21#ibcon#about to read 4, iclass 23, count 0 2006.257.12:52:57.21#ibcon#read 4, iclass 23, count 0 2006.257.12:52:57.21#ibcon#about to read 5, iclass 23, count 0 2006.257.12:52:57.21#ibcon#read 5, iclass 23, count 0 2006.257.12:52:57.21#ibcon#about to read 6, iclass 23, count 0 2006.257.12:52:57.21#ibcon#read 6, iclass 23, count 0 2006.257.12:52:57.21#ibcon#end of sib2, iclass 23, count 0 2006.257.12:52:57.21#ibcon#*after write, iclass 23, count 0 2006.257.12:52:57.21#ibcon#*before return 0, iclass 23, count 0 2006.257.12:52:57.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:52:57.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:52:57.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.12:52:57.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.12:52:57.21$vck44/valo=4,624.99 2006.257.12:52:57.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.12:52:57.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.12:52:57.21#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:57.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:52:57.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:52:57.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:52:57.21#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:52:57.21#ibcon#first serial, iclass 25, count 0 2006.257.12:52:57.21#ibcon#enter sib2, iclass 25, count 0 2006.257.12:52:57.21#ibcon#flushed, iclass 25, count 0 2006.257.12:52:57.21#ibcon#about to write, iclass 25, count 0 2006.257.12:52:57.21#ibcon#wrote, iclass 25, count 0 2006.257.12:52:57.21#ibcon#about to read 3, iclass 25, count 0 2006.257.12:52:57.23#ibcon#read 3, iclass 25, count 0 2006.257.12:52:57.23#ibcon#about to read 4, iclass 25, count 0 2006.257.12:52:57.23#ibcon#read 4, iclass 25, count 0 2006.257.12:52:57.23#ibcon#about to read 5, iclass 25, count 0 2006.257.12:52:57.23#ibcon#read 5, iclass 25, count 0 2006.257.12:52:57.23#ibcon#about to read 6, iclass 25, count 0 2006.257.12:52:57.23#ibcon#read 6, iclass 25, count 0 2006.257.12:52:57.23#ibcon#end of sib2, iclass 25, count 0 2006.257.12:52:57.23#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:52:57.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:52:57.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.12:52:57.23#ibcon#*before write, iclass 25, count 0 2006.257.12:52:57.23#ibcon#enter sib2, iclass 25, count 0 2006.257.12:52:57.23#ibcon#flushed, iclass 25, count 0 2006.257.12:52:57.23#ibcon#about to write, iclass 25, count 0 2006.257.12:52:57.23#ibcon#wrote, iclass 25, count 0 2006.257.12:52:57.23#ibcon#about to read 3, iclass 25, count 0 2006.257.12:52:57.27#ibcon#read 3, iclass 25, count 0 2006.257.12:52:57.27#ibcon#about to read 4, iclass 25, count 0 2006.257.12:52:57.27#ibcon#read 4, iclass 25, count 0 2006.257.12:52:57.27#ibcon#about to read 5, iclass 25, count 0 2006.257.12:52:57.27#ibcon#read 5, iclass 25, count 0 2006.257.12:52:57.27#ibcon#about to read 6, iclass 25, count 0 2006.257.12:52:57.27#ibcon#read 6, iclass 25, count 0 2006.257.12:52:57.27#ibcon#end of sib2, iclass 25, count 0 2006.257.12:52:57.27#ibcon#*after write, iclass 25, count 0 2006.257.12:52:57.27#ibcon#*before return 0, iclass 25, count 0 2006.257.12:52:57.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:52:57.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:52:57.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:52:57.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:52:57.27$vck44/va=4,7 2006.257.12:52:57.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.12:52:57.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.12:52:57.27#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:57.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:52:57.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:52:57.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:52:57.33#ibcon#enter wrdev, iclass 27, count 2 2006.257.12:52:57.33#ibcon#first serial, iclass 27, count 2 2006.257.12:52:57.33#ibcon#enter sib2, iclass 27, count 2 2006.257.12:52:57.33#ibcon#flushed, iclass 27, count 2 2006.257.12:52:57.33#ibcon#about to write, iclass 27, count 2 2006.257.12:52:57.33#ibcon#wrote, iclass 27, count 2 2006.257.12:52:57.33#ibcon#about to read 3, iclass 27, count 2 2006.257.12:52:57.35#ibcon#read 3, iclass 27, count 2 2006.257.12:52:57.35#ibcon#about to read 4, iclass 27, count 2 2006.257.12:52:57.35#ibcon#read 4, iclass 27, count 2 2006.257.12:52:57.35#ibcon#about to read 5, iclass 27, count 2 2006.257.12:52:57.35#ibcon#read 5, iclass 27, count 2 2006.257.12:52:57.35#ibcon#about to read 6, iclass 27, count 2 2006.257.12:52:57.35#ibcon#read 6, iclass 27, count 2 2006.257.12:52:57.35#ibcon#end of sib2, iclass 27, count 2 2006.257.12:52:57.35#ibcon#*mode == 0, iclass 27, count 2 2006.257.12:52:57.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.12:52:57.35#ibcon#[25=AT04-07\r\n] 2006.257.12:52:57.35#ibcon#*before write, iclass 27, count 2 2006.257.12:52:57.35#ibcon#enter sib2, iclass 27, count 2 2006.257.12:52:57.35#ibcon#flushed, iclass 27, count 2 2006.257.12:52:57.35#ibcon#about to write, iclass 27, count 2 2006.257.12:52:57.35#ibcon#wrote, iclass 27, count 2 2006.257.12:52:57.35#ibcon#about to read 3, iclass 27, count 2 2006.257.12:52:57.38#ibcon#read 3, iclass 27, count 2 2006.257.12:52:57.38#ibcon#about to read 4, iclass 27, count 2 2006.257.12:52:57.38#ibcon#read 4, iclass 27, count 2 2006.257.12:52:57.38#ibcon#about to read 5, iclass 27, count 2 2006.257.12:52:57.38#ibcon#read 5, iclass 27, count 2 2006.257.12:52:57.38#ibcon#about to read 6, iclass 27, count 2 2006.257.12:52:57.38#ibcon#read 6, iclass 27, count 2 2006.257.12:52:57.38#ibcon#end of sib2, iclass 27, count 2 2006.257.12:52:57.38#ibcon#*after write, iclass 27, count 2 2006.257.12:52:57.39#ibcon#*before return 0, iclass 27, count 2 2006.257.12:52:57.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:52:57.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:52:57.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.12:52:57.39#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:57.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:52:57.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:52:57.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:52:57.51#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:52:57.51#ibcon#first serial, iclass 27, count 0 2006.257.12:52:57.51#ibcon#enter sib2, iclass 27, count 0 2006.257.12:52:57.51#ibcon#flushed, iclass 27, count 0 2006.257.12:52:57.51#ibcon#about to write, iclass 27, count 0 2006.257.12:52:57.51#ibcon#wrote, iclass 27, count 0 2006.257.12:52:57.51#ibcon#about to read 3, iclass 27, count 0 2006.257.12:52:57.53#ibcon#read 3, iclass 27, count 0 2006.257.12:52:57.53#ibcon#about to read 4, iclass 27, count 0 2006.257.12:52:57.53#ibcon#read 4, iclass 27, count 0 2006.257.12:52:57.53#ibcon#about to read 5, iclass 27, count 0 2006.257.12:52:57.53#ibcon#read 5, iclass 27, count 0 2006.257.12:52:57.53#ibcon#about to read 6, iclass 27, count 0 2006.257.12:52:57.53#ibcon#read 6, iclass 27, count 0 2006.257.12:52:57.53#ibcon#end of sib2, iclass 27, count 0 2006.257.12:52:57.53#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:52:57.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:52:57.53#ibcon#[25=USB\r\n] 2006.257.12:52:57.53#ibcon#*before write, iclass 27, count 0 2006.257.12:52:57.53#ibcon#enter sib2, iclass 27, count 0 2006.257.12:52:57.53#ibcon#flushed, iclass 27, count 0 2006.257.12:52:57.53#ibcon#about to write, iclass 27, count 0 2006.257.12:52:57.53#ibcon#wrote, iclass 27, count 0 2006.257.12:52:57.53#ibcon#about to read 3, iclass 27, count 0 2006.257.12:52:57.56#ibcon#read 3, iclass 27, count 0 2006.257.12:52:57.56#ibcon#about to read 4, iclass 27, count 0 2006.257.12:52:57.56#ibcon#read 4, iclass 27, count 0 2006.257.12:52:57.56#ibcon#about to read 5, iclass 27, count 0 2006.257.12:52:57.56#ibcon#read 5, iclass 27, count 0 2006.257.12:52:57.56#ibcon#about to read 6, iclass 27, count 0 2006.257.12:52:57.56#ibcon#read 6, iclass 27, count 0 2006.257.12:52:57.56#ibcon#end of sib2, iclass 27, count 0 2006.257.12:52:57.56#ibcon#*after write, iclass 27, count 0 2006.257.12:52:57.56#ibcon#*before return 0, iclass 27, count 0 2006.257.12:52:57.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:52:57.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:52:57.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:52:57.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:52:57.56$vck44/valo=5,734.99 2006.257.12:52:57.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.12:52:57.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.12:52:57.56#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:57.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:52:57.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:52:57.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:52:57.56#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:52:57.56#ibcon#first serial, iclass 29, count 0 2006.257.12:52:57.56#ibcon#enter sib2, iclass 29, count 0 2006.257.12:52:57.56#ibcon#flushed, iclass 29, count 0 2006.257.12:52:57.56#ibcon#about to write, iclass 29, count 0 2006.257.12:52:57.56#ibcon#wrote, iclass 29, count 0 2006.257.12:52:57.56#ibcon#about to read 3, iclass 29, count 0 2006.257.12:52:57.58#ibcon#read 3, iclass 29, count 0 2006.257.12:52:57.58#ibcon#about to read 4, iclass 29, count 0 2006.257.12:52:57.58#ibcon#read 4, iclass 29, count 0 2006.257.12:52:57.58#ibcon#about to read 5, iclass 29, count 0 2006.257.12:52:57.58#ibcon#read 5, iclass 29, count 0 2006.257.12:52:57.58#ibcon#about to read 6, iclass 29, count 0 2006.257.12:52:57.58#ibcon#read 6, iclass 29, count 0 2006.257.12:52:57.58#ibcon#end of sib2, iclass 29, count 0 2006.257.12:52:57.58#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:52:57.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:52:57.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.12:52:57.58#ibcon#*before write, iclass 29, count 0 2006.257.12:52:57.58#ibcon#enter sib2, iclass 29, count 0 2006.257.12:52:57.58#ibcon#flushed, iclass 29, count 0 2006.257.12:52:57.58#ibcon#about to write, iclass 29, count 0 2006.257.12:52:57.58#ibcon#wrote, iclass 29, count 0 2006.257.12:52:57.58#ibcon#about to read 3, iclass 29, count 0 2006.257.12:52:57.62#ibcon#read 3, iclass 29, count 0 2006.257.12:52:57.62#ibcon#about to read 4, iclass 29, count 0 2006.257.12:52:57.62#ibcon#read 4, iclass 29, count 0 2006.257.12:52:57.62#ibcon#about to read 5, iclass 29, count 0 2006.257.12:52:57.62#ibcon#read 5, iclass 29, count 0 2006.257.12:52:57.62#ibcon#about to read 6, iclass 29, count 0 2006.257.12:52:57.62#ibcon#read 6, iclass 29, count 0 2006.257.12:52:57.62#ibcon#end of sib2, iclass 29, count 0 2006.257.12:52:57.62#ibcon#*after write, iclass 29, count 0 2006.257.12:52:57.62#ibcon#*before return 0, iclass 29, count 0 2006.257.12:52:57.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:52:57.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:52:57.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:52:57.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:52:57.62$vck44/va=5,4 2006.257.12:52:57.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.12:52:57.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.12:52:57.62#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:57.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:52:57.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:52:57.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:52:57.68#ibcon#enter wrdev, iclass 31, count 2 2006.257.12:52:57.68#ibcon#first serial, iclass 31, count 2 2006.257.12:52:57.68#ibcon#enter sib2, iclass 31, count 2 2006.257.12:52:57.68#ibcon#flushed, iclass 31, count 2 2006.257.12:52:57.68#ibcon#about to write, iclass 31, count 2 2006.257.12:52:57.68#ibcon#wrote, iclass 31, count 2 2006.257.12:52:57.68#ibcon#about to read 3, iclass 31, count 2 2006.257.12:52:57.70#ibcon#read 3, iclass 31, count 2 2006.257.12:52:57.70#ibcon#about to read 4, iclass 31, count 2 2006.257.12:52:57.70#ibcon#read 4, iclass 31, count 2 2006.257.12:52:57.70#ibcon#about to read 5, iclass 31, count 2 2006.257.12:52:57.70#ibcon#read 5, iclass 31, count 2 2006.257.12:52:57.70#ibcon#about to read 6, iclass 31, count 2 2006.257.12:52:57.70#ibcon#read 6, iclass 31, count 2 2006.257.12:52:57.70#ibcon#end of sib2, iclass 31, count 2 2006.257.12:52:57.70#ibcon#*mode == 0, iclass 31, count 2 2006.257.12:52:57.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.12:52:57.70#ibcon#[25=AT05-04\r\n] 2006.257.12:52:57.70#ibcon#*before write, iclass 31, count 2 2006.257.12:52:57.70#ibcon#enter sib2, iclass 31, count 2 2006.257.12:52:57.70#ibcon#flushed, iclass 31, count 2 2006.257.12:52:57.70#ibcon#about to write, iclass 31, count 2 2006.257.12:52:57.70#ibcon#wrote, iclass 31, count 2 2006.257.12:52:57.70#ibcon#about to read 3, iclass 31, count 2 2006.257.12:52:57.73#ibcon#read 3, iclass 31, count 2 2006.257.12:52:57.73#ibcon#about to read 4, iclass 31, count 2 2006.257.12:52:57.73#ibcon#read 4, iclass 31, count 2 2006.257.12:52:57.73#ibcon#about to read 5, iclass 31, count 2 2006.257.12:52:57.73#ibcon#read 5, iclass 31, count 2 2006.257.12:52:57.73#ibcon#about to read 6, iclass 31, count 2 2006.257.12:52:57.73#ibcon#read 6, iclass 31, count 2 2006.257.12:52:57.73#ibcon#end of sib2, iclass 31, count 2 2006.257.12:52:57.73#ibcon#*after write, iclass 31, count 2 2006.257.12:52:57.73#ibcon#*before return 0, iclass 31, count 2 2006.257.12:52:57.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:52:57.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:52:57.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.12:52:57.73#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:57.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:52:57.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:52:57.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:52:57.85#ibcon#enter wrdev, iclass 31, count 0 2006.257.12:52:57.85#ibcon#first serial, iclass 31, count 0 2006.257.12:52:57.85#ibcon#enter sib2, iclass 31, count 0 2006.257.12:52:57.85#ibcon#flushed, iclass 31, count 0 2006.257.12:52:57.85#ibcon#about to write, iclass 31, count 0 2006.257.12:52:57.85#ibcon#wrote, iclass 31, count 0 2006.257.12:52:57.85#ibcon#about to read 3, iclass 31, count 0 2006.257.12:52:57.87#ibcon#read 3, iclass 31, count 0 2006.257.12:52:57.87#ibcon#about to read 4, iclass 31, count 0 2006.257.12:52:57.87#ibcon#read 4, iclass 31, count 0 2006.257.12:52:57.87#ibcon#about to read 5, iclass 31, count 0 2006.257.12:52:57.87#ibcon#read 5, iclass 31, count 0 2006.257.12:52:57.87#ibcon#about to read 6, iclass 31, count 0 2006.257.12:52:57.87#ibcon#read 6, iclass 31, count 0 2006.257.12:52:57.87#ibcon#end of sib2, iclass 31, count 0 2006.257.12:52:57.87#ibcon#*mode == 0, iclass 31, count 0 2006.257.12:52:57.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.12:52:57.87#ibcon#[25=USB\r\n] 2006.257.12:52:57.87#ibcon#*before write, iclass 31, count 0 2006.257.12:52:57.87#ibcon#enter sib2, iclass 31, count 0 2006.257.12:52:57.87#ibcon#flushed, iclass 31, count 0 2006.257.12:52:57.87#ibcon#about to write, iclass 31, count 0 2006.257.12:52:57.87#ibcon#wrote, iclass 31, count 0 2006.257.12:52:57.87#ibcon#about to read 3, iclass 31, count 0 2006.257.12:52:57.90#ibcon#read 3, iclass 31, count 0 2006.257.12:52:57.90#ibcon#about to read 4, iclass 31, count 0 2006.257.12:52:57.90#ibcon#read 4, iclass 31, count 0 2006.257.12:52:57.90#ibcon#about to read 5, iclass 31, count 0 2006.257.12:52:57.90#ibcon#read 5, iclass 31, count 0 2006.257.12:52:57.90#ibcon#about to read 6, iclass 31, count 0 2006.257.12:52:57.90#ibcon#read 6, iclass 31, count 0 2006.257.12:52:57.90#ibcon#end of sib2, iclass 31, count 0 2006.257.12:52:57.90#ibcon#*after write, iclass 31, count 0 2006.257.12:52:57.90#ibcon#*before return 0, iclass 31, count 0 2006.257.12:52:57.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:52:57.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:52:57.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.12:52:57.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.12:52:57.90$vck44/valo=6,814.99 2006.257.12:52:57.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.12:52:57.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.12:52:57.90#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:57.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:52:57.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:52:57.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:52:57.90#ibcon#enter wrdev, iclass 33, count 0 2006.257.12:52:57.90#ibcon#first serial, iclass 33, count 0 2006.257.12:52:57.90#ibcon#enter sib2, iclass 33, count 0 2006.257.12:52:57.90#ibcon#flushed, iclass 33, count 0 2006.257.12:52:57.90#ibcon#about to write, iclass 33, count 0 2006.257.12:52:57.90#ibcon#wrote, iclass 33, count 0 2006.257.12:52:57.90#ibcon#about to read 3, iclass 33, count 0 2006.257.12:52:57.92#ibcon#read 3, iclass 33, count 0 2006.257.12:52:57.92#ibcon#about to read 4, iclass 33, count 0 2006.257.12:52:57.92#ibcon#read 4, iclass 33, count 0 2006.257.12:52:57.92#ibcon#about to read 5, iclass 33, count 0 2006.257.12:52:57.92#ibcon#read 5, iclass 33, count 0 2006.257.12:52:57.92#ibcon#about to read 6, iclass 33, count 0 2006.257.12:52:57.92#ibcon#read 6, iclass 33, count 0 2006.257.12:52:57.92#ibcon#end of sib2, iclass 33, count 0 2006.257.12:52:57.92#ibcon#*mode == 0, iclass 33, count 0 2006.257.12:52:57.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.12:52:57.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.12:52:57.92#ibcon#*before write, iclass 33, count 0 2006.257.12:52:57.92#ibcon#enter sib2, iclass 33, count 0 2006.257.12:52:57.92#ibcon#flushed, iclass 33, count 0 2006.257.12:52:57.92#ibcon#about to write, iclass 33, count 0 2006.257.12:52:57.92#ibcon#wrote, iclass 33, count 0 2006.257.12:52:57.92#ibcon#about to read 3, iclass 33, count 0 2006.257.12:52:57.96#ibcon#read 3, iclass 33, count 0 2006.257.12:52:57.96#ibcon#about to read 4, iclass 33, count 0 2006.257.12:52:57.96#ibcon#read 4, iclass 33, count 0 2006.257.12:52:57.96#ibcon#about to read 5, iclass 33, count 0 2006.257.12:52:57.96#ibcon#read 5, iclass 33, count 0 2006.257.12:52:57.96#ibcon#about to read 6, iclass 33, count 0 2006.257.12:52:57.96#ibcon#read 6, iclass 33, count 0 2006.257.12:52:57.96#ibcon#end of sib2, iclass 33, count 0 2006.257.12:52:57.96#ibcon#*after write, iclass 33, count 0 2006.257.12:52:57.96#ibcon#*before return 0, iclass 33, count 0 2006.257.12:52:57.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:52:57.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:52:57.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.12:52:57.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.12:52:57.96$vck44/va=6,4 2006.257.12:52:57.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.12:52:57.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.12:52:57.96#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:57.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:52:58.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:52:58.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:52:58.02#ibcon#enter wrdev, iclass 35, count 2 2006.257.12:52:58.02#ibcon#first serial, iclass 35, count 2 2006.257.12:52:58.02#ibcon#enter sib2, iclass 35, count 2 2006.257.12:52:58.02#ibcon#flushed, iclass 35, count 2 2006.257.12:52:58.02#ibcon#about to write, iclass 35, count 2 2006.257.12:52:58.02#ibcon#wrote, iclass 35, count 2 2006.257.12:52:58.02#ibcon#about to read 3, iclass 35, count 2 2006.257.12:52:58.04#ibcon#read 3, iclass 35, count 2 2006.257.12:52:58.04#ibcon#about to read 4, iclass 35, count 2 2006.257.12:52:58.04#ibcon#read 4, iclass 35, count 2 2006.257.12:52:58.04#ibcon#about to read 5, iclass 35, count 2 2006.257.12:52:58.04#ibcon#read 5, iclass 35, count 2 2006.257.12:52:58.04#ibcon#about to read 6, iclass 35, count 2 2006.257.12:52:58.04#ibcon#read 6, iclass 35, count 2 2006.257.12:52:58.04#ibcon#end of sib2, iclass 35, count 2 2006.257.12:52:58.04#ibcon#*mode == 0, iclass 35, count 2 2006.257.12:52:58.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.12:52:58.04#ibcon#[25=AT06-04\r\n] 2006.257.12:52:58.04#ibcon#*before write, iclass 35, count 2 2006.257.12:52:58.04#ibcon#enter sib2, iclass 35, count 2 2006.257.12:52:58.04#ibcon#flushed, iclass 35, count 2 2006.257.12:52:58.04#ibcon#about to write, iclass 35, count 2 2006.257.12:52:58.04#ibcon#wrote, iclass 35, count 2 2006.257.12:52:58.04#ibcon#about to read 3, iclass 35, count 2 2006.257.12:52:58.07#ibcon#read 3, iclass 35, count 2 2006.257.12:52:58.07#ibcon#about to read 4, iclass 35, count 2 2006.257.12:52:58.07#ibcon#read 4, iclass 35, count 2 2006.257.12:52:58.07#ibcon#about to read 5, iclass 35, count 2 2006.257.12:52:58.07#ibcon#read 5, iclass 35, count 2 2006.257.12:52:58.07#ibcon#about to read 6, iclass 35, count 2 2006.257.12:52:58.07#ibcon#read 6, iclass 35, count 2 2006.257.12:52:58.07#ibcon#end of sib2, iclass 35, count 2 2006.257.12:52:58.07#ibcon#*after write, iclass 35, count 2 2006.257.12:52:58.07#ibcon#*before return 0, iclass 35, count 2 2006.257.12:52:58.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:52:58.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:52:58.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.12:52:58.07#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:58.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:52:58.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:52:58.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:52:58.19#ibcon#enter wrdev, iclass 35, count 0 2006.257.12:52:58.19#ibcon#first serial, iclass 35, count 0 2006.257.12:52:58.19#ibcon#enter sib2, iclass 35, count 0 2006.257.12:52:58.19#ibcon#flushed, iclass 35, count 0 2006.257.12:52:58.19#ibcon#about to write, iclass 35, count 0 2006.257.12:52:58.19#ibcon#wrote, iclass 35, count 0 2006.257.12:52:58.19#ibcon#about to read 3, iclass 35, count 0 2006.257.12:52:58.21#ibcon#read 3, iclass 35, count 0 2006.257.12:52:58.21#ibcon#about to read 4, iclass 35, count 0 2006.257.12:52:58.21#ibcon#read 4, iclass 35, count 0 2006.257.12:52:58.21#ibcon#about to read 5, iclass 35, count 0 2006.257.12:52:58.21#ibcon#read 5, iclass 35, count 0 2006.257.12:52:58.21#ibcon#about to read 6, iclass 35, count 0 2006.257.12:52:58.21#ibcon#read 6, iclass 35, count 0 2006.257.12:52:58.21#ibcon#end of sib2, iclass 35, count 0 2006.257.12:52:58.21#ibcon#*mode == 0, iclass 35, count 0 2006.257.12:52:58.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.12:52:58.21#ibcon#[25=USB\r\n] 2006.257.12:52:58.21#ibcon#*before write, iclass 35, count 0 2006.257.12:52:58.21#ibcon#enter sib2, iclass 35, count 0 2006.257.12:52:58.21#ibcon#flushed, iclass 35, count 0 2006.257.12:52:58.21#ibcon#about to write, iclass 35, count 0 2006.257.12:52:58.21#ibcon#wrote, iclass 35, count 0 2006.257.12:52:58.21#ibcon#about to read 3, iclass 35, count 0 2006.257.12:52:58.24#ibcon#read 3, iclass 35, count 0 2006.257.12:52:58.24#ibcon#about to read 4, iclass 35, count 0 2006.257.12:52:58.24#ibcon#read 4, iclass 35, count 0 2006.257.12:52:58.24#ibcon#about to read 5, iclass 35, count 0 2006.257.12:52:58.24#ibcon#read 5, iclass 35, count 0 2006.257.12:52:58.24#ibcon#about to read 6, iclass 35, count 0 2006.257.12:52:58.24#ibcon#read 6, iclass 35, count 0 2006.257.12:52:58.24#ibcon#end of sib2, iclass 35, count 0 2006.257.12:52:58.24#ibcon#*after write, iclass 35, count 0 2006.257.12:52:58.24#ibcon#*before return 0, iclass 35, count 0 2006.257.12:52:58.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:52:58.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:52:58.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.12:52:58.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.12:52:58.24$vck44/valo=7,864.99 2006.257.12:52:58.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.12:52:58.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.12:52:58.24#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:58.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:52:58.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:52:58.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:52:58.24#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:52:58.24#ibcon#first serial, iclass 37, count 0 2006.257.12:52:58.24#ibcon#enter sib2, iclass 37, count 0 2006.257.12:52:58.24#ibcon#flushed, iclass 37, count 0 2006.257.12:52:58.24#ibcon#about to write, iclass 37, count 0 2006.257.12:52:58.24#ibcon#wrote, iclass 37, count 0 2006.257.12:52:58.24#ibcon#about to read 3, iclass 37, count 0 2006.257.12:52:58.26#ibcon#read 3, iclass 37, count 0 2006.257.12:52:58.26#ibcon#about to read 4, iclass 37, count 0 2006.257.12:52:58.26#ibcon#read 4, iclass 37, count 0 2006.257.12:52:58.26#ibcon#about to read 5, iclass 37, count 0 2006.257.12:52:58.26#ibcon#read 5, iclass 37, count 0 2006.257.12:52:58.26#ibcon#about to read 6, iclass 37, count 0 2006.257.12:52:58.26#ibcon#read 6, iclass 37, count 0 2006.257.12:52:58.26#ibcon#end of sib2, iclass 37, count 0 2006.257.12:52:58.26#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:52:58.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:52:58.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.12:52:58.26#ibcon#*before write, iclass 37, count 0 2006.257.12:52:58.26#ibcon#enter sib2, iclass 37, count 0 2006.257.12:52:58.26#ibcon#flushed, iclass 37, count 0 2006.257.12:52:58.26#ibcon#about to write, iclass 37, count 0 2006.257.12:52:58.26#ibcon#wrote, iclass 37, count 0 2006.257.12:52:58.26#ibcon#about to read 3, iclass 37, count 0 2006.257.12:52:58.30#ibcon#read 3, iclass 37, count 0 2006.257.12:52:58.30#ibcon#about to read 4, iclass 37, count 0 2006.257.12:52:58.30#ibcon#read 4, iclass 37, count 0 2006.257.12:52:58.30#ibcon#about to read 5, iclass 37, count 0 2006.257.12:52:58.30#ibcon#read 5, iclass 37, count 0 2006.257.12:52:58.30#ibcon#about to read 6, iclass 37, count 0 2006.257.12:52:58.30#ibcon#read 6, iclass 37, count 0 2006.257.12:52:58.30#ibcon#end of sib2, iclass 37, count 0 2006.257.12:52:58.30#ibcon#*after write, iclass 37, count 0 2006.257.12:52:58.30#ibcon#*before return 0, iclass 37, count 0 2006.257.12:52:58.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:52:58.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:52:58.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:52:58.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:52:58.30$vck44/va=7,4 2006.257.12:52:58.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.12:52:58.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.12:52:58.30#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:58.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:52:58.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:52:58.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:52:58.36#ibcon#enter wrdev, iclass 39, count 2 2006.257.12:52:58.36#ibcon#first serial, iclass 39, count 2 2006.257.12:52:58.36#ibcon#enter sib2, iclass 39, count 2 2006.257.12:52:58.36#ibcon#flushed, iclass 39, count 2 2006.257.12:52:58.36#ibcon#about to write, iclass 39, count 2 2006.257.12:52:58.36#ibcon#wrote, iclass 39, count 2 2006.257.12:52:58.36#ibcon#about to read 3, iclass 39, count 2 2006.257.12:52:58.38#ibcon#read 3, iclass 39, count 2 2006.257.12:52:58.38#ibcon#about to read 4, iclass 39, count 2 2006.257.12:52:58.38#ibcon#read 4, iclass 39, count 2 2006.257.12:52:58.38#ibcon#about to read 5, iclass 39, count 2 2006.257.12:52:58.38#ibcon#read 5, iclass 39, count 2 2006.257.12:52:58.38#ibcon#about to read 6, iclass 39, count 2 2006.257.12:52:58.38#ibcon#read 6, iclass 39, count 2 2006.257.12:52:58.38#ibcon#end of sib2, iclass 39, count 2 2006.257.12:52:58.38#ibcon#*mode == 0, iclass 39, count 2 2006.257.12:52:58.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.12:52:58.38#ibcon#[25=AT07-04\r\n] 2006.257.12:52:58.38#ibcon#*before write, iclass 39, count 2 2006.257.12:52:58.38#ibcon#enter sib2, iclass 39, count 2 2006.257.12:52:58.38#ibcon#flushed, iclass 39, count 2 2006.257.12:52:58.38#ibcon#about to write, iclass 39, count 2 2006.257.12:52:58.38#ibcon#wrote, iclass 39, count 2 2006.257.12:52:58.38#ibcon#about to read 3, iclass 39, count 2 2006.257.12:52:58.41#ibcon#read 3, iclass 39, count 2 2006.257.12:52:58.41#ibcon#about to read 4, iclass 39, count 2 2006.257.12:52:58.41#ibcon#read 4, iclass 39, count 2 2006.257.12:52:58.41#ibcon#about to read 5, iclass 39, count 2 2006.257.12:52:58.41#ibcon#read 5, iclass 39, count 2 2006.257.12:52:58.41#ibcon#about to read 6, iclass 39, count 2 2006.257.12:52:58.41#ibcon#read 6, iclass 39, count 2 2006.257.12:52:58.41#ibcon#end of sib2, iclass 39, count 2 2006.257.12:52:58.41#ibcon#*after write, iclass 39, count 2 2006.257.12:52:58.41#ibcon#*before return 0, iclass 39, count 2 2006.257.12:52:58.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:52:58.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:52:58.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.12:52:58.41#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:58.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:52:58.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:52:58.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:52:58.53#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:52:58.53#ibcon#first serial, iclass 39, count 0 2006.257.12:52:58.53#ibcon#enter sib2, iclass 39, count 0 2006.257.12:52:58.53#ibcon#flushed, iclass 39, count 0 2006.257.12:52:58.53#ibcon#about to write, iclass 39, count 0 2006.257.12:52:58.53#ibcon#wrote, iclass 39, count 0 2006.257.12:52:58.53#ibcon#about to read 3, iclass 39, count 0 2006.257.12:52:58.55#ibcon#read 3, iclass 39, count 0 2006.257.12:52:58.55#ibcon#about to read 4, iclass 39, count 0 2006.257.12:52:58.55#ibcon#read 4, iclass 39, count 0 2006.257.12:52:58.55#ibcon#about to read 5, iclass 39, count 0 2006.257.12:52:58.55#ibcon#read 5, iclass 39, count 0 2006.257.12:52:58.55#ibcon#about to read 6, iclass 39, count 0 2006.257.12:52:58.55#ibcon#read 6, iclass 39, count 0 2006.257.12:52:58.55#ibcon#end of sib2, iclass 39, count 0 2006.257.12:52:58.55#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:52:58.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:52:58.55#ibcon#[25=USB\r\n] 2006.257.12:52:58.55#ibcon#*before write, iclass 39, count 0 2006.257.12:52:58.55#ibcon#enter sib2, iclass 39, count 0 2006.257.12:52:58.55#ibcon#flushed, iclass 39, count 0 2006.257.12:52:58.55#ibcon#about to write, iclass 39, count 0 2006.257.12:52:58.55#ibcon#wrote, iclass 39, count 0 2006.257.12:52:58.55#ibcon#about to read 3, iclass 39, count 0 2006.257.12:52:58.58#ibcon#read 3, iclass 39, count 0 2006.257.12:52:58.58#ibcon#about to read 4, iclass 39, count 0 2006.257.12:52:58.58#ibcon#read 4, iclass 39, count 0 2006.257.12:52:58.58#ibcon#about to read 5, iclass 39, count 0 2006.257.12:52:58.58#ibcon#read 5, iclass 39, count 0 2006.257.12:52:58.58#ibcon#about to read 6, iclass 39, count 0 2006.257.12:52:58.58#ibcon#read 6, iclass 39, count 0 2006.257.12:52:58.58#ibcon#end of sib2, iclass 39, count 0 2006.257.12:52:58.58#ibcon#*after write, iclass 39, count 0 2006.257.12:52:58.58#ibcon#*before return 0, iclass 39, count 0 2006.257.12:52:58.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:52:58.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:52:58.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:52:58.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:52:58.58$vck44/valo=8,884.99 2006.257.12:52:58.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.12:52:58.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.12:52:58.58#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:58.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:52:58.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:52:58.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:52:58.58#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:52:58.58#ibcon#first serial, iclass 3, count 0 2006.257.12:52:58.58#ibcon#enter sib2, iclass 3, count 0 2006.257.12:52:58.58#ibcon#flushed, iclass 3, count 0 2006.257.12:52:58.58#ibcon#about to write, iclass 3, count 0 2006.257.12:52:58.58#ibcon#wrote, iclass 3, count 0 2006.257.12:52:58.58#ibcon#about to read 3, iclass 3, count 0 2006.257.12:52:58.60#ibcon#read 3, iclass 3, count 0 2006.257.12:52:58.60#ibcon#about to read 4, iclass 3, count 0 2006.257.12:52:58.60#ibcon#read 4, iclass 3, count 0 2006.257.12:52:58.60#ibcon#about to read 5, iclass 3, count 0 2006.257.12:52:58.60#ibcon#read 5, iclass 3, count 0 2006.257.12:52:58.60#ibcon#about to read 6, iclass 3, count 0 2006.257.12:52:58.60#ibcon#read 6, iclass 3, count 0 2006.257.12:52:58.60#ibcon#end of sib2, iclass 3, count 0 2006.257.12:52:58.60#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:52:58.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:52:58.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.12:52:58.60#ibcon#*before write, iclass 3, count 0 2006.257.12:52:58.60#ibcon#enter sib2, iclass 3, count 0 2006.257.12:52:58.60#ibcon#flushed, iclass 3, count 0 2006.257.12:52:58.60#ibcon#about to write, iclass 3, count 0 2006.257.12:52:58.60#ibcon#wrote, iclass 3, count 0 2006.257.12:52:58.60#ibcon#about to read 3, iclass 3, count 0 2006.257.12:52:58.64#ibcon#read 3, iclass 3, count 0 2006.257.12:52:58.64#ibcon#about to read 4, iclass 3, count 0 2006.257.12:52:58.64#ibcon#read 4, iclass 3, count 0 2006.257.12:52:58.64#ibcon#about to read 5, iclass 3, count 0 2006.257.12:52:58.64#ibcon#read 5, iclass 3, count 0 2006.257.12:52:58.64#ibcon#about to read 6, iclass 3, count 0 2006.257.12:52:58.64#ibcon#read 6, iclass 3, count 0 2006.257.12:52:58.64#ibcon#end of sib2, iclass 3, count 0 2006.257.12:52:58.64#ibcon#*after write, iclass 3, count 0 2006.257.12:52:58.64#ibcon#*before return 0, iclass 3, count 0 2006.257.12:52:58.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:52:58.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:52:58.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:52:58.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:52:58.64$vck44/va=8,4 2006.257.12:52:58.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.12:52:58.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.12:52:58.64#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:58.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:52:58.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:52:58.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:52:58.70#ibcon#enter wrdev, iclass 5, count 2 2006.257.12:52:58.70#ibcon#first serial, iclass 5, count 2 2006.257.12:52:58.70#ibcon#enter sib2, iclass 5, count 2 2006.257.12:52:58.70#ibcon#flushed, iclass 5, count 2 2006.257.12:52:58.70#ibcon#about to write, iclass 5, count 2 2006.257.12:52:58.70#ibcon#wrote, iclass 5, count 2 2006.257.12:52:58.70#ibcon#about to read 3, iclass 5, count 2 2006.257.12:52:58.72#ibcon#read 3, iclass 5, count 2 2006.257.12:52:58.72#ibcon#about to read 4, iclass 5, count 2 2006.257.12:52:58.72#ibcon#read 4, iclass 5, count 2 2006.257.12:52:58.72#ibcon#about to read 5, iclass 5, count 2 2006.257.12:52:58.72#ibcon#read 5, iclass 5, count 2 2006.257.12:52:58.72#ibcon#about to read 6, iclass 5, count 2 2006.257.12:52:58.72#ibcon#read 6, iclass 5, count 2 2006.257.12:52:58.72#ibcon#end of sib2, iclass 5, count 2 2006.257.12:52:58.72#ibcon#*mode == 0, iclass 5, count 2 2006.257.12:52:58.72#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.12:52:58.72#ibcon#[25=AT08-04\r\n] 2006.257.12:52:58.72#ibcon#*before write, iclass 5, count 2 2006.257.12:52:58.72#ibcon#enter sib2, iclass 5, count 2 2006.257.12:52:58.72#ibcon#flushed, iclass 5, count 2 2006.257.12:52:58.72#ibcon#about to write, iclass 5, count 2 2006.257.12:52:58.72#ibcon#wrote, iclass 5, count 2 2006.257.12:52:58.72#ibcon#about to read 3, iclass 5, count 2 2006.257.12:52:58.75#ibcon#read 3, iclass 5, count 2 2006.257.12:52:58.75#ibcon#about to read 4, iclass 5, count 2 2006.257.12:52:58.75#ibcon#read 4, iclass 5, count 2 2006.257.12:52:58.75#ibcon#about to read 5, iclass 5, count 2 2006.257.12:52:58.75#ibcon#read 5, iclass 5, count 2 2006.257.12:52:58.75#ibcon#about to read 6, iclass 5, count 2 2006.257.12:52:58.75#ibcon#read 6, iclass 5, count 2 2006.257.12:52:58.75#ibcon#end of sib2, iclass 5, count 2 2006.257.12:52:58.75#ibcon#*after write, iclass 5, count 2 2006.257.12:52:58.75#ibcon#*before return 0, iclass 5, count 2 2006.257.12:52:58.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:52:58.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.12:52:58.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.12:52:58.75#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:58.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:52:58.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:52:58.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:52:58.87#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:52:58.87#ibcon#first serial, iclass 5, count 0 2006.257.12:52:58.87#ibcon#enter sib2, iclass 5, count 0 2006.257.12:52:58.87#ibcon#flushed, iclass 5, count 0 2006.257.12:52:58.87#ibcon#about to write, iclass 5, count 0 2006.257.12:52:58.87#ibcon#wrote, iclass 5, count 0 2006.257.12:52:58.87#ibcon#about to read 3, iclass 5, count 0 2006.257.12:52:58.89#ibcon#read 3, iclass 5, count 0 2006.257.12:52:58.89#ibcon#about to read 4, iclass 5, count 0 2006.257.12:52:58.89#ibcon#read 4, iclass 5, count 0 2006.257.12:52:58.89#ibcon#about to read 5, iclass 5, count 0 2006.257.12:52:58.89#ibcon#read 5, iclass 5, count 0 2006.257.12:52:58.89#ibcon#about to read 6, iclass 5, count 0 2006.257.12:52:58.89#ibcon#read 6, iclass 5, count 0 2006.257.12:52:58.89#ibcon#end of sib2, iclass 5, count 0 2006.257.12:52:58.89#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:52:58.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:52:58.89#ibcon#[25=USB\r\n] 2006.257.12:52:58.89#ibcon#*before write, iclass 5, count 0 2006.257.12:52:58.89#ibcon#enter sib2, iclass 5, count 0 2006.257.12:52:58.89#ibcon#flushed, iclass 5, count 0 2006.257.12:52:58.89#ibcon#about to write, iclass 5, count 0 2006.257.12:52:58.89#ibcon#wrote, iclass 5, count 0 2006.257.12:52:58.89#ibcon#about to read 3, iclass 5, count 0 2006.257.12:52:58.92#ibcon#read 3, iclass 5, count 0 2006.257.12:52:58.92#ibcon#about to read 4, iclass 5, count 0 2006.257.12:52:58.92#ibcon#read 4, iclass 5, count 0 2006.257.12:52:58.92#ibcon#about to read 5, iclass 5, count 0 2006.257.12:52:58.92#ibcon#read 5, iclass 5, count 0 2006.257.12:52:58.92#ibcon#about to read 6, iclass 5, count 0 2006.257.12:52:58.92#ibcon#read 6, iclass 5, count 0 2006.257.12:52:58.92#ibcon#end of sib2, iclass 5, count 0 2006.257.12:52:58.92#ibcon#*after write, iclass 5, count 0 2006.257.12:52:58.92#ibcon#*before return 0, iclass 5, count 0 2006.257.12:52:58.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:52:58.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.12:52:58.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:52:58.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:52:58.92$vck44/vblo=1,629.99 2006.257.12:52:58.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.12:52:58.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.12:52:58.92#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:58.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:52:58.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:52:58.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:52:58.92#ibcon#enter wrdev, iclass 7, count 0 2006.257.12:52:58.92#ibcon#first serial, iclass 7, count 0 2006.257.12:52:58.92#ibcon#enter sib2, iclass 7, count 0 2006.257.12:52:58.92#ibcon#flushed, iclass 7, count 0 2006.257.12:52:58.92#ibcon#about to write, iclass 7, count 0 2006.257.12:52:58.92#ibcon#wrote, iclass 7, count 0 2006.257.12:52:58.92#ibcon#about to read 3, iclass 7, count 0 2006.257.12:52:58.94#ibcon#read 3, iclass 7, count 0 2006.257.12:52:58.94#ibcon#about to read 4, iclass 7, count 0 2006.257.12:52:58.94#ibcon#read 4, iclass 7, count 0 2006.257.12:52:58.94#ibcon#about to read 5, iclass 7, count 0 2006.257.12:52:58.94#ibcon#read 5, iclass 7, count 0 2006.257.12:52:58.94#ibcon#about to read 6, iclass 7, count 0 2006.257.12:52:58.94#ibcon#read 6, iclass 7, count 0 2006.257.12:52:58.94#ibcon#end of sib2, iclass 7, count 0 2006.257.12:52:58.94#ibcon#*mode == 0, iclass 7, count 0 2006.257.12:52:58.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.12:52:58.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.12:52:58.94#ibcon#*before write, iclass 7, count 0 2006.257.12:52:58.94#ibcon#enter sib2, iclass 7, count 0 2006.257.12:52:58.94#ibcon#flushed, iclass 7, count 0 2006.257.12:52:58.94#ibcon#about to write, iclass 7, count 0 2006.257.12:52:58.94#ibcon#wrote, iclass 7, count 0 2006.257.12:52:58.94#ibcon#about to read 3, iclass 7, count 0 2006.257.12:52:58.98#ibcon#read 3, iclass 7, count 0 2006.257.12:52:58.98#ibcon#about to read 4, iclass 7, count 0 2006.257.12:52:58.98#ibcon#read 4, iclass 7, count 0 2006.257.12:52:58.98#ibcon#about to read 5, iclass 7, count 0 2006.257.12:52:58.98#ibcon#read 5, iclass 7, count 0 2006.257.12:52:58.98#ibcon#about to read 6, iclass 7, count 0 2006.257.12:52:58.98#ibcon#read 6, iclass 7, count 0 2006.257.12:52:58.98#ibcon#end of sib2, iclass 7, count 0 2006.257.12:52:58.98#ibcon#*after write, iclass 7, count 0 2006.257.12:52:58.98#ibcon#*before return 0, iclass 7, count 0 2006.257.12:52:58.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:52:58.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.12:52:58.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.12:52:58.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.12:52:58.98$vck44/vb=1,4 2006.257.12:52:58.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.12:52:58.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.12:52:58.98#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:58.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:52:58.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:52:58.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:52:58.98#ibcon#enter wrdev, iclass 11, count 2 2006.257.12:52:58.98#ibcon#first serial, iclass 11, count 2 2006.257.12:52:58.98#ibcon#enter sib2, iclass 11, count 2 2006.257.12:52:58.98#ibcon#flushed, iclass 11, count 2 2006.257.12:52:58.98#ibcon#about to write, iclass 11, count 2 2006.257.12:52:58.98#ibcon#wrote, iclass 11, count 2 2006.257.12:52:58.98#ibcon#about to read 3, iclass 11, count 2 2006.257.12:52:59.00#ibcon#read 3, iclass 11, count 2 2006.257.12:52:59.00#ibcon#about to read 4, iclass 11, count 2 2006.257.12:52:59.00#ibcon#read 4, iclass 11, count 2 2006.257.12:52:59.00#ibcon#about to read 5, iclass 11, count 2 2006.257.12:52:59.00#ibcon#read 5, iclass 11, count 2 2006.257.12:52:59.00#ibcon#about to read 6, iclass 11, count 2 2006.257.12:52:59.00#ibcon#read 6, iclass 11, count 2 2006.257.12:52:59.00#ibcon#end of sib2, iclass 11, count 2 2006.257.12:52:59.00#ibcon#*mode == 0, iclass 11, count 2 2006.257.12:52:59.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.12:52:59.00#ibcon#[27=AT01-04\r\n] 2006.257.12:52:59.00#ibcon#*before write, iclass 11, count 2 2006.257.12:52:59.00#ibcon#enter sib2, iclass 11, count 2 2006.257.12:52:59.00#ibcon#flushed, iclass 11, count 2 2006.257.12:52:59.00#ibcon#about to write, iclass 11, count 2 2006.257.12:52:59.00#ibcon#wrote, iclass 11, count 2 2006.257.12:52:59.00#ibcon#about to read 3, iclass 11, count 2 2006.257.12:52:59.03#ibcon#read 3, iclass 11, count 2 2006.257.12:52:59.03#ibcon#about to read 4, iclass 11, count 2 2006.257.12:52:59.03#ibcon#read 4, iclass 11, count 2 2006.257.12:52:59.03#ibcon#about to read 5, iclass 11, count 2 2006.257.12:52:59.03#ibcon#read 5, iclass 11, count 2 2006.257.12:52:59.03#ibcon#about to read 6, iclass 11, count 2 2006.257.12:52:59.03#ibcon#read 6, iclass 11, count 2 2006.257.12:52:59.03#ibcon#end of sib2, iclass 11, count 2 2006.257.12:52:59.03#ibcon#*after write, iclass 11, count 2 2006.257.12:52:59.03#ibcon#*before return 0, iclass 11, count 2 2006.257.12:52:59.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:52:59.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.12:52:59.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.12:52:59.03#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:59.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:52:59.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:52:59.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:52:59.15#ibcon#enter wrdev, iclass 11, count 0 2006.257.12:52:59.15#ibcon#first serial, iclass 11, count 0 2006.257.12:52:59.15#ibcon#enter sib2, iclass 11, count 0 2006.257.12:52:59.15#ibcon#flushed, iclass 11, count 0 2006.257.12:52:59.15#ibcon#about to write, iclass 11, count 0 2006.257.12:52:59.15#ibcon#wrote, iclass 11, count 0 2006.257.12:52:59.15#ibcon#about to read 3, iclass 11, count 0 2006.257.12:52:59.17#ibcon#read 3, iclass 11, count 0 2006.257.12:52:59.17#ibcon#about to read 4, iclass 11, count 0 2006.257.12:52:59.17#ibcon#read 4, iclass 11, count 0 2006.257.12:52:59.17#ibcon#about to read 5, iclass 11, count 0 2006.257.12:52:59.17#ibcon#read 5, iclass 11, count 0 2006.257.12:52:59.17#ibcon#about to read 6, iclass 11, count 0 2006.257.12:52:59.17#ibcon#read 6, iclass 11, count 0 2006.257.12:52:59.17#ibcon#end of sib2, iclass 11, count 0 2006.257.12:52:59.17#ibcon#*mode == 0, iclass 11, count 0 2006.257.12:52:59.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.12:52:59.17#ibcon#[27=USB\r\n] 2006.257.12:52:59.17#ibcon#*before write, iclass 11, count 0 2006.257.12:52:59.17#ibcon#enter sib2, iclass 11, count 0 2006.257.12:52:59.17#ibcon#flushed, iclass 11, count 0 2006.257.12:52:59.17#ibcon#about to write, iclass 11, count 0 2006.257.12:52:59.17#ibcon#wrote, iclass 11, count 0 2006.257.12:52:59.17#ibcon#about to read 3, iclass 11, count 0 2006.257.12:52:59.20#ibcon#read 3, iclass 11, count 0 2006.257.12:52:59.20#ibcon#about to read 4, iclass 11, count 0 2006.257.12:52:59.20#ibcon#read 4, iclass 11, count 0 2006.257.12:52:59.20#ibcon#about to read 5, iclass 11, count 0 2006.257.12:52:59.20#ibcon#read 5, iclass 11, count 0 2006.257.12:52:59.20#ibcon#about to read 6, iclass 11, count 0 2006.257.12:52:59.20#ibcon#read 6, iclass 11, count 0 2006.257.12:52:59.20#ibcon#end of sib2, iclass 11, count 0 2006.257.12:52:59.20#ibcon#*after write, iclass 11, count 0 2006.257.12:52:59.20#ibcon#*before return 0, iclass 11, count 0 2006.257.12:52:59.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:52:59.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.12:52:59.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.12:52:59.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.12:52:59.20$vck44/vblo=2,634.99 2006.257.12:52:59.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.12:52:59.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.12:52:59.20#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:59.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:59.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:59.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:59.20#ibcon#enter wrdev, iclass 13, count 0 2006.257.12:52:59.20#ibcon#first serial, iclass 13, count 0 2006.257.12:52:59.20#ibcon#enter sib2, iclass 13, count 0 2006.257.12:52:59.20#ibcon#flushed, iclass 13, count 0 2006.257.12:52:59.20#ibcon#about to write, iclass 13, count 0 2006.257.12:52:59.20#ibcon#wrote, iclass 13, count 0 2006.257.12:52:59.20#ibcon#about to read 3, iclass 13, count 0 2006.257.12:52:59.22#ibcon#read 3, iclass 13, count 0 2006.257.12:52:59.22#ibcon#about to read 4, iclass 13, count 0 2006.257.12:52:59.22#ibcon#read 4, iclass 13, count 0 2006.257.12:52:59.22#ibcon#about to read 5, iclass 13, count 0 2006.257.12:52:59.22#ibcon#read 5, iclass 13, count 0 2006.257.12:52:59.22#ibcon#about to read 6, iclass 13, count 0 2006.257.12:52:59.22#ibcon#read 6, iclass 13, count 0 2006.257.12:52:59.22#ibcon#end of sib2, iclass 13, count 0 2006.257.12:52:59.22#ibcon#*mode == 0, iclass 13, count 0 2006.257.12:52:59.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.12:52:59.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.12:52:59.22#ibcon#*before write, iclass 13, count 0 2006.257.12:52:59.22#ibcon#enter sib2, iclass 13, count 0 2006.257.12:52:59.22#ibcon#flushed, iclass 13, count 0 2006.257.12:52:59.22#ibcon#about to write, iclass 13, count 0 2006.257.12:52:59.22#ibcon#wrote, iclass 13, count 0 2006.257.12:52:59.22#ibcon#about to read 3, iclass 13, count 0 2006.257.12:52:59.26#ibcon#read 3, iclass 13, count 0 2006.257.12:52:59.26#ibcon#about to read 4, iclass 13, count 0 2006.257.12:52:59.26#ibcon#read 4, iclass 13, count 0 2006.257.12:52:59.26#ibcon#about to read 5, iclass 13, count 0 2006.257.12:52:59.26#ibcon#read 5, iclass 13, count 0 2006.257.12:52:59.26#ibcon#about to read 6, iclass 13, count 0 2006.257.12:52:59.26#ibcon#read 6, iclass 13, count 0 2006.257.12:52:59.26#ibcon#end of sib2, iclass 13, count 0 2006.257.12:52:59.26#ibcon#*after write, iclass 13, count 0 2006.257.12:52:59.26#ibcon#*before return 0, iclass 13, count 0 2006.257.12:52:59.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:59.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.12:52:59.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.12:52:59.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.12:52:59.26$vck44/vb=2,5 2006.257.12:52:59.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.12:52:59.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.12:52:59.26#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:59.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:59.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:59.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:59.32#ibcon#enter wrdev, iclass 15, count 2 2006.257.12:52:59.32#ibcon#first serial, iclass 15, count 2 2006.257.12:52:59.32#ibcon#enter sib2, iclass 15, count 2 2006.257.12:52:59.32#ibcon#flushed, iclass 15, count 2 2006.257.12:52:59.32#ibcon#about to write, iclass 15, count 2 2006.257.12:52:59.32#ibcon#wrote, iclass 15, count 2 2006.257.12:52:59.32#ibcon#about to read 3, iclass 15, count 2 2006.257.12:52:59.34#ibcon#read 3, iclass 15, count 2 2006.257.12:52:59.34#ibcon#about to read 4, iclass 15, count 2 2006.257.12:52:59.34#ibcon#read 4, iclass 15, count 2 2006.257.12:52:59.34#ibcon#about to read 5, iclass 15, count 2 2006.257.12:52:59.34#ibcon#read 5, iclass 15, count 2 2006.257.12:52:59.34#ibcon#about to read 6, iclass 15, count 2 2006.257.12:52:59.34#ibcon#read 6, iclass 15, count 2 2006.257.12:52:59.34#ibcon#end of sib2, iclass 15, count 2 2006.257.12:52:59.34#ibcon#*mode == 0, iclass 15, count 2 2006.257.12:52:59.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.12:52:59.34#ibcon#[27=AT02-05\r\n] 2006.257.12:52:59.34#ibcon#*before write, iclass 15, count 2 2006.257.12:52:59.34#ibcon#enter sib2, iclass 15, count 2 2006.257.12:52:59.34#ibcon#flushed, iclass 15, count 2 2006.257.12:52:59.34#ibcon#about to write, iclass 15, count 2 2006.257.12:52:59.34#ibcon#wrote, iclass 15, count 2 2006.257.12:52:59.34#ibcon#about to read 3, iclass 15, count 2 2006.257.12:52:59.37#ibcon#read 3, iclass 15, count 2 2006.257.12:52:59.37#ibcon#about to read 4, iclass 15, count 2 2006.257.12:52:59.37#ibcon#read 4, iclass 15, count 2 2006.257.12:52:59.37#ibcon#about to read 5, iclass 15, count 2 2006.257.12:52:59.37#ibcon#read 5, iclass 15, count 2 2006.257.12:52:59.37#ibcon#about to read 6, iclass 15, count 2 2006.257.12:52:59.37#ibcon#read 6, iclass 15, count 2 2006.257.12:52:59.37#ibcon#end of sib2, iclass 15, count 2 2006.257.12:52:59.37#ibcon#*after write, iclass 15, count 2 2006.257.12:52:59.37#ibcon#*before return 0, iclass 15, count 2 2006.257.12:52:59.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:59.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.12:52:59.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.12:52:59.37#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:59.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:59.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:59.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:59.49#ibcon#enter wrdev, iclass 15, count 0 2006.257.12:52:59.49#ibcon#first serial, iclass 15, count 0 2006.257.12:52:59.49#ibcon#enter sib2, iclass 15, count 0 2006.257.12:52:59.49#ibcon#flushed, iclass 15, count 0 2006.257.12:52:59.49#ibcon#about to write, iclass 15, count 0 2006.257.12:52:59.49#ibcon#wrote, iclass 15, count 0 2006.257.12:52:59.49#ibcon#about to read 3, iclass 15, count 0 2006.257.12:52:59.51#ibcon#read 3, iclass 15, count 0 2006.257.12:52:59.51#ibcon#about to read 4, iclass 15, count 0 2006.257.12:52:59.51#ibcon#read 4, iclass 15, count 0 2006.257.12:52:59.51#ibcon#about to read 5, iclass 15, count 0 2006.257.12:52:59.51#ibcon#read 5, iclass 15, count 0 2006.257.12:52:59.51#ibcon#about to read 6, iclass 15, count 0 2006.257.12:52:59.51#ibcon#read 6, iclass 15, count 0 2006.257.12:52:59.51#ibcon#end of sib2, iclass 15, count 0 2006.257.12:52:59.51#ibcon#*mode == 0, iclass 15, count 0 2006.257.12:52:59.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.12:52:59.51#ibcon#[27=USB\r\n] 2006.257.12:52:59.51#ibcon#*before write, iclass 15, count 0 2006.257.12:52:59.51#ibcon#enter sib2, iclass 15, count 0 2006.257.12:52:59.51#ibcon#flushed, iclass 15, count 0 2006.257.12:52:59.51#ibcon#about to write, iclass 15, count 0 2006.257.12:52:59.51#ibcon#wrote, iclass 15, count 0 2006.257.12:52:59.51#ibcon#about to read 3, iclass 15, count 0 2006.257.12:52:59.54#ibcon#read 3, iclass 15, count 0 2006.257.12:52:59.54#ibcon#about to read 4, iclass 15, count 0 2006.257.12:52:59.54#ibcon#read 4, iclass 15, count 0 2006.257.12:52:59.54#ibcon#about to read 5, iclass 15, count 0 2006.257.12:52:59.54#ibcon#read 5, iclass 15, count 0 2006.257.12:52:59.54#ibcon#about to read 6, iclass 15, count 0 2006.257.12:52:59.54#ibcon#read 6, iclass 15, count 0 2006.257.12:52:59.54#ibcon#end of sib2, iclass 15, count 0 2006.257.12:52:59.54#ibcon#*after write, iclass 15, count 0 2006.257.12:52:59.54#ibcon#*before return 0, iclass 15, count 0 2006.257.12:52:59.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:59.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.12:52:59.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.12:52:59.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.12:52:59.54$vck44/vblo=3,649.99 2006.257.12:52:59.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.12:52:59.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.12:52:59.54#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:59.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:59.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:59.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:59.54#ibcon#enter wrdev, iclass 17, count 0 2006.257.12:52:59.54#ibcon#first serial, iclass 17, count 0 2006.257.12:52:59.54#ibcon#enter sib2, iclass 17, count 0 2006.257.12:52:59.54#ibcon#flushed, iclass 17, count 0 2006.257.12:52:59.54#ibcon#about to write, iclass 17, count 0 2006.257.12:52:59.54#ibcon#wrote, iclass 17, count 0 2006.257.12:52:59.54#ibcon#about to read 3, iclass 17, count 0 2006.257.12:52:59.56#ibcon#read 3, iclass 17, count 0 2006.257.12:52:59.56#ibcon#about to read 4, iclass 17, count 0 2006.257.12:52:59.56#ibcon#read 4, iclass 17, count 0 2006.257.12:52:59.56#ibcon#about to read 5, iclass 17, count 0 2006.257.12:52:59.56#ibcon#read 5, iclass 17, count 0 2006.257.12:52:59.56#ibcon#about to read 6, iclass 17, count 0 2006.257.12:52:59.56#ibcon#read 6, iclass 17, count 0 2006.257.12:52:59.56#ibcon#end of sib2, iclass 17, count 0 2006.257.12:52:59.56#ibcon#*mode == 0, iclass 17, count 0 2006.257.12:52:59.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.12:52:59.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.12:52:59.56#ibcon#*before write, iclass 17, count 0 2006.257.12:52:59.56#ibcon#enter sib2, iclass 17, count 0 2006.257.12:52:59.56#ibcon#flushed, iclass 17, count 0 2006.257.12:52:59.56#ibcon#about to write, iclass 17, count 0 2006.257.12:52:59.56#ibcon#wrote, iclass 17, count 0 2006.257.12:52:59.56#ibcon#about to read 3, iclass 17, count 0 2006.257.12:52:59.60#ibcon#read 3, iclass 17, count 0 2006.257.12:52:59.60#ibcon#about to read 4, iclass 17, count 0 2006.257.12:52:59.60#ibcon#read 4, iclass 17, count 0 2006.257.12:52:59.60#ibcon#about to read 5, iclass 17, count 0 2006.257.12:52:59.60#ibcon#read 5, iclass 17, count 0 2006.257.12:52:59.60#ibcon#about to read 6, iclass 17, count 0 2006.257.12:52:59.60#ibcon#read 6, iclass 17, count 0 2006.257.12:52:59.60#ibcon#end of sib2, iclass 17, count 0 2006.257.12:52:59.60#ibcon#*after write, iclass 17, count 0 2006.257.12:52:59.60#ibcon#*before return 0, iclass 17, count 0 2006.257.12:52:59.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:59.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.12:52:59.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.12:52:59.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.12:52:59.60$vck44/vb=3,4 2006.257.12:52:59.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.12:52:59.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.12:52:59.60#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:59.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:59.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:59.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:59.66#ibcon#enter wrdev, iclass 19, count 2 2006.257.12:52:59.66#ibcon#first serial, iclass 19, count 2 2006.257.12:52:59.66#ibcon#enter sib2, iclass 19, count 2 2006.257.12:52:59.66#ibcon#flushed, iclass 19, count 2 2006.257.12:52:59.66#ibcon#about to write, iclass 19, count 2 2006.257.12:52:59.66#ibcon#wrote, iclass 19, count 2 2006.257.12:52:59.66#ibcon#about to read 3, iclass 19, count 2 2006.257.12:52:59.68#ibcon#read 3, iclass 19, count 2 2006.257.12:52:59.68#ibcon#about to read 4, iclass 19, count 2 2006.257.12:52:59.68#ibcon#read 4, iclass 19, count 2 2006.257.12:52:59.68#ibcon#about to read 5, iclass 19, count 2 2006.257.12:52:59.68#ibcon#read 5, iclass 19, count 2 2006.257.12:52:59.68#ibcon#about to read 6, iclass 19, count 2 2006.257.12:52:59.68#ibcon#read 6, iclass 19, count 2 2006.257.12:52:59.68#ibcon#end of sib2, iclass 19, count 2 2006.257.12:52:59.68#ibcon#*mode == 0, iclass 19, count 2 2006.257.12:52:59.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.12:52:59.68#ibcon#[27=AT03-04\r\n] 2006.257.12:52:59.68#ibcon#*before write, iclass 19, count 2 2006.257.12:52:59.68#ibcon#enter sib2, iclass 19, count 2 2006.257.12:52:59.68#ibcon#flushed, iclass 19, count 2 2006.257.12:52:59.68#ibcon#about to write, iclass 19, count 2 2006.257.12:52:59.68#ibcon#wrote, iclass 19, count 2 2006.257.12:52:59.68#ibcon#about to read 3, iclass 19, count 2 2006.257.12:52:59.71#ibcon#read 3, iclass 19, count 2 2006.257.12:52:59.71#ibcon#about to read 4, iclass 19, count 2 2006.257.12:52:59.71#ibcon#read 4, iclass 19, count 2 2006.257.12:52:59.71#ibcon#about to read 5, iclass 19, count 2 2006.257.12:52:59.71#ibcon#read 5, iclass 19, count 2 2006.257.12:52:59.71#ibcon#about to read 6, iclass 19, count 2 2006.257.12:52:59.71#ibcon#read 6, iclass 19, count 2 2006.257.12:52:59.71#ibcon#end of sib2, iclass 19, count 2 2006.257.12:52:59.71#ibcon#*after write, iclass 19, count 2 2006.257.12:52:59.71#ibcon#*before return 0, iclass 19, count 2 2006.257.12:52:59.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:59.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.12:52:59.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.12:52:59.71#ibcon#ireg 7 cls_cnt 0 2006.257.12:52:59.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:59.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:59.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:59.83#ibcon#enter wrdev, iclass 19, count 0 2006.257.12:52:59.83#ibcon#first serial, iclass 19, count 0 2006.257.12:52:59.83#ibcon#enter sib2, iclass 19, count 0 2006.257.12:52:59.83#ibcon#flushed, iclass 19, count 0 2006.257.12:52:59.83#ibcon#about to write, iclass 19, count 0 2006.257.12:52:59.83#ibcon#wrote, iclass 19, count 0 2006.257.12:52:59.83#ibcon#about to read 3, iclass 19, count 0 2006.257.12:52:59.85#ibcon#read 3, iclass 19, count 0 2006.257.12:52:59.85#ibcon#about to read 4, iclass 19, count 0 2006.257.12:52:59.85#ibcon#read 4, iclass 19, count 0 2006.257.12:52:59.85#ibcon#about to read 5, iclass 19, count 0 2006.257.12:52:59.85#ibcon#read 5, iclass 19, count 0 2006.257.12:52:59.85#ibcon#about to read 6, iclass 19, count 0 2006.257.12:52:59.85#ibcon#read 6, iclass 19, count 0 2006.257.12:52:59.85#ibcon#end of sib2, iclass 19, count 0 2006.257.12:52:59.85#ibcon#*mode == 0, iclass 19, count 0 2006.257.12:52:59.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.12:52:59.85#ibcon#[27=USB\r\n] 2006.257.12:52:59.85#ibcon#*before write, iclass 19, count 0 2006.257.12:52:59.85#ibcon#enter sib2, iclass 19, count 0 2006.257.12:52:59.85#ibcon#flushed, iclass 19, count 0 2006.257.12:52:59.85#ibcon#about to write, iclass 19, count 0 2006.257.12:52:59.85#ibcon#wrote, iclass 19, count 0 2006.257.12:52:59.85#ibcon#about to read 3, iclass 19, count 0 2006.257.12:52:59.88#ibcon#read 3, iclass 19, count 0 2006.257.12:52:59.88#ibcon#about to read 4, iclass 19, count 0 2006.257.12:52:59.88#ibcon#read 4, iclass 19, count 0 2006.257.12:52:59.88#ibcon#about to read 5, iclass 19, count 0 2006.257.12:52:59.88#ibcon#read 5, iclass 19, count 0 2006.257.12:52:59.88#ibcon#about to read 6, iclass 19, count 0 2006.257.12:52:59.88#ibcon#read 6, iclass 19, count 0 2006.257.12:52:59.88#ibcon#end of sib2, iclass 19, count 0 2006.257.12:52:59.88#ibcon#*after write, iclass 19, count 0 2006.257.12:52:59.88#ibcon#*before return 0, iclass 19, count 0 2006.257.12:52:59.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:59.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.12:52:59.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.12:52:59.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.12:52:59.88$vck44/vblo=4,679.99 2006.257.12:52:59.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.12:52:59.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.12:52:59.88#ibcon#ireg 17 cls_cnt 0 2006.257.12:52:59.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:59.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:59.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:59.88#ibcon#enter wrdev, iclass 21, count 0 2006.257.12:52:59.88#ibcon#first serial, iclass 21, count 0 2006.257.12:52:59.88#ibcon#enter sib2, iclass 21, count 0 2006.257.12:52:59.88#ibcon#flushed, iclass 21, count 0 2006.257.12:52:59.88#ibcon#about to write, iclass 21, count 0 2006.257.12:52:59.88#ibcon#wrote, iclass 21, count 0 2006.257.12:52:59.88#ibcon#about to read 3, iclass 21, count 0 2006.257.12:52:59.90#ibcon#read 3, iclass 21, count 0 2006.257.12:52:59.90#ibcon#about to read 4, iclass 21, count 0 2006.257.12:52:59.90#ibcon#read 4, iclass 21, count 0 2006.257.12:52:59.90#ibcon#about to read 5, iclass 21, count 0 2006.257.12:52:59.90#ibcon#read 5, iclass 21, count 0 2006.257.12:52:59.90#ibcon#about to read 6, iclass 21, count 0 2006.257.12:52:59.90#ibcon#read 6, iclass 21, count 0 2006.257.12:52:59.90#ibcon#end of sib2, iclass 21, count 0 2006.257.12:52:59.90#ibcon#*mode == 0, iclass 21, count 0 2006.257.12:52:59.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.12:52:59.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.12:52:59.90#ibcon#*before write, iclass 21, count 0 2006.257.12:52:59.90#ibcon#enter sib2, iclass 21, count 0 2006.257.12:52:59.90#ibcon#flushed, iclass 21, count 0 2006.257.12:52:59.90#ibcon#about to write, iclass 21, count 0 2006.257.12:52:59.90#ibcon#wrote, iclass 21, count 0 2006.257.12:52:59.90#ibcon#about to read 3, iclass 21, count 0 2006.257.12:52:59.94#ibcon#read 3, iclass 21, count 0 2006.257.12:52:59.94#ibcon#about to read 4, iclass 21, count 0 2006.257.12:52:59.94#ibcon#read 4, iclass 21, count 0 2006.257.12:52:59.94#ibcon#about to read 5, iclass 21, count 0 2006.257.12:52:59.94#ibcon#read 5, iclass 21, count 0 2006.257.12:52:59.94#ibcon#about to read 6, iclass 21, count 0 2006.257.12:52:59.94#ibcon#read 6, iclass 21, count 0 2006.257.12:52:59.94#ibcon#end of sib2, iclass 21, count 0 2006.257.12:52:59.94#ibcon#*after write, iclass 21, count 0 2006.257.12:52:59.94#ibcon#*before return 0, iclass 21, count 0 2006.257.12:52:59.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:59.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.12:52:59.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.12:52:59.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.12:52:59.94$vck44/vb=4,5 2006.257.12:52:59.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.12:52:59.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.12:52:59.94#ibcon#ireg 11 cls_cnt 2 2006.257.12:52:59.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:53:00.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:53:00.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:53:00.00#ibcon#enter wrdev, iclass 23, count 2 2006.257.12:53:00.00#ibcon#first serial, iclass 23, count 2 2006.257.12:53:00.00#ibcon#enter sib2, iclass 23, count 2 2006.257.12:53:00.00#ibcon#flushed, iclass 23, count 2 2006.257.12:53:00.00#ibcon#about to write, iclass 23, count 2 2006.257.12:53:00.00#ibcon#wrote, iclass 23, count 2 2006.257.12:53:00.00#ibcon#about to read 3, iclass 23, count 2 2006.257.12:53:00.02#ibcon#read 3, iclass 23, count 2 2006.257.12:53:00.02#ibcon#about to read 4, iclass 23, count 2 2006.257.12:53:00.02#ibcon#read 4, iclass 23, count 2 2006.257.12:53:00.02#ibcon#about to read 5, iclass 23, count 2 2006.257.12:53:00.02#ibcon#read 5, iclass 23, count 2 2006.257.12:53:00.02#ibcon#about to read 6, iclass 23, count 2 2006.257.12:53:00.02#ibcon#read 6, iclass 23, count 2 2006.257.12:53:00.02#ibcon#end of sib2, iclass 23, count 2 2006.257.12:53:00.02#ibcon#*mode == 0, iclass 23, count 2 2006.257.12:53:00.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.12:53:00.02#ibcon#[27=AT04-05\r\n] 2006.257.12:53:00.02#ibcon#*before write, iclass 23, count 2 2006.257.12:53:00.02#ibcon#enter sib2, iclass 23, count 2 2006.257.12:53:00.02#ibcon#flushed, iclass 23, count 2 2006.257.12:53:00.02#ibcon#about to write, iclass 23, count 2 2006.257.12:53:00.02#ibcon#wrote, iclass 23, count 2 2006.257.12:53:00.02#ibcon#about to read 3, iclass 23, count 2 2006.257.12:53:00.05#ibcon#read 3, iclass 23, count 2 2006.257.12:53:00.05#ibcon#about to read 4, iclass 23, count 2 2006.257.12:53:00.05#ibcon#read 4, iclass 23, count 2 2006.257.12:53:00.05#ibcon#about to read 5, iclass 23, count 2 2006.257.12:53:00.05#ibcon#read 5, iclass 23, count 2 2006.257.12:53:00.05#ibcon#about to read 6, iclass 23, count 2 2006.257.12:53:00.05#ibcon#read 6, iclass 23, count 2 2006.257.12:53:00.05#ibcon#end of sib2, iclass 23, count 2 2006.257.12:53:00.05#ibcon#*after write, iclass 23, count 2 2006.257.12:53:00.05#ibcon#*before return 0, iclass 23, count 2 2006.257.12:53:00.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:53:00.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.12:53:00.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.12:53:00.05#ibcon#ireg 7 cls_cnt 0 2006.257.12:53:00.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:53:00.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:53:00.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:53:00.17#ibcon#enter wrdev, iclass 23, count 0 2006.257.12:53:00.17#ibcon#first serial, iclass 23, count 0 2006.257.12:53:00.17#ibcon#enter sib2, iclass 23, count 0 2006.257.12:53:00.17#ibcon#flushed, iclass 23, count 0 2006.257.12:53:00.17#ibcon#about to write, iclass 23, count 0 2006.257.12:53:00.17#ibcon#wrote, iclass 23, count 0 2006.257.12:53:00.17#ibcon#about to read 3, iclass 23, count 0 2006.257.12:53:00.19#ibcon#read 3, iclass 23, count 0 2006.257.12:53:00.19#ibcon#about to read 4, iclass 23, count 0 2006.257.12:53:00.19#ibcon#read 4, iclass 23, count 0 2006.257.12:53:00.19#ibcon#about to read 5, iclass 23, count 0 2006.257.12:53:00.19#ibcon#read 5, iclass 23, count 0 2006.257.12:53:00.19#ibcon#about to read 6, iclass 23, count 0 2006.257.12:53:00.19#ibcon#read 6, iclass 23, count 0 2006.257.12:53:00.19#ibcon#end of sib2, iclass 23, count 0 2006.257.12:53:00.19#ibcon#*mode == 0, iclass 23, count 0 2006.257.12:53:00.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.12:53:00.19#ibcon#[27=USB\r\n] 2006.257.12:53:00.19#ibcon#*before write, iclass 23, count 0 2006.257.12:53:00.19#ibcon#enter sib2, iclass 23, count 0 2006.257.12:53:00.19#ibcon#flushed, iclass 23, count 0 2006.257.12:53:00.19#ibcon#about to write, iclass 23, count 0 2006.257.12:53:00.19#ibcon#wrote, iclass 23, count 0 2006.257.12:53:00.19#ibcon#about to read 3, iclass 23, count 0 2006.257.12:53:00.22#ibcon#read 3, iclass 23, count 0 2006.257.12:53:00.22#ibcon#about to read 4, iclass 23, count 0 2006.257.12:53:00.22#ibcon#read 4, iclass 23, count 0 2006.257.12:53:00.22#ibcon#about to read 5, iclass 23, count 0 2006.257.12:53:00.22#ibcon#read 5, iclass 23, count 0 2006.257.12:53:00.22#ibcon#about to read 6, iclass 23, count 0 2006.257.12:53:00.22#ibcon#read 6, iclass 23, count 0 2006.257.12:53:00.22#ibcon#end of sib2, iclass 23, count 0 2006.257.12:53:00.22#ibcon#*after write, iclass 23, count 0 2006.257.12:53:00.22#ibcon#*before return 0, iclass 23, count 0 2006.257.12:53:00.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:53:00.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.12:53:00.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.12:53:00.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.12:53:00.22$vck44/vblo=5,709.99 2006.257.12:53:00.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.12:53:00.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.12:53:00.22#ibcon#ireg 17 cls_cnt 0 2006.257.12:53:00.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:53:00.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:53:00.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:53:00.22#ibcon#enter wrdev, iclass 25, count 0 2006.257.12:53:00.22#ibcon#first serial, iclass 25, count 0 2006.257.12:53:00.22#ibcon#enter sib2, iclass 25, count 0 2006.257.12:53:00.22#ibcon#flushed, iclass 25, count 0 2006.257.12:53:00.22#ibcon#about to write, iclass 25, count 0 2006.257.12:53:00.22#ibcon#wrote, iclass 25, count 0 2006.257.12:53:00.22#ibcon#about to read 3, iclass 25, count 0 2006.257.12:53:00.24#ibcon#read 3, iclass 25, count 0 2006.257.12:53:00.24#ibcon#about to read 4, iclass 25, count 0 2006.257.12:53:00.24#ibcon#read 4, iclass 25, count 0 2006.257.12:53:00.24#ibcon#about to read 5, iclass 25, count 0 2006.257.12:53:00.24#ibcon#read 5, iclass 25, count 0 2006.257.12:53:00.24#ibcon#about to read 6, iclass 25, count 0 2006.257.12:53:00.24#ibcon#read 6, iclass 25, count 0 2006.257.12:53:00.24#ibcon#end of sib2, iclass 25, count 0 2006.257.12:53:00.24#ibcon#*mode == 0, iclass 25, count 0 2006.257.12:53:00.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.12:53:00.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.12:53:00.24#ibcon#*before write, iclass 25, count 0 2006.257.12:53:00.24#ibcon#enter sib2, iclass 25, count 0 2006.257.12:53:00.24#ibcon#flushed, iclass 25, count 0 2006.257.12:53:00.24#ibcon#about to write, iclass 25, count 0 2006.257.12:53:00.24#ibcon#wrote, iclass 25, count 0 2006.257.12:53:00.24#ibcon#about to read 3, iclass 25, count 0 2006.257.12:53:00.28#ibcon#read 3, iclass 25, count 0 2006.257.12:53:00.28#ibcon#about to read 4, iclass 25, count 0 2006.257.12:53:00.28#ibcon#read 4, iclass 25, count 0 2006.257.12:53:00.28#ibcon#about to read 5, iclass 25, count 0 2006.257.12:53:00.28#ibcon#read 5, iclass 25, count 0 2006.257.12:53:00.28#ibcon#about to read 6, iclass 25, count 0 2006.257.12:53:00.28#ibcon#read 6, iclass 25, count 0 2006.257.12:53:00.28#ibcon#end of sib2, iclass 25, count 0 2006.257.12:53:00.28#ibcon#*after write, iclass 25, count 0 2006.257.12:53:00.28#ibcon#*before return 0, iclass 25, count 0 2006.257.12:53:00.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:53:00.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.12:53:00.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.12:53:00.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.12:53:00.28$vck44/vb=5,4 2006.257.12:53:00.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.12:53:00.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.12:53:00.28#ibcon#ireg 11 cls_cnt 2 2006.257.12:53:00.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:53:00.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:53:00.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:53:00.34#ibcon#enter wrdev, iclass 27, count 2 2006.257.12:53:00.34#ibcon#first serial, iclass 27, count 2 2006.257.12:53:00.34#ibcon#enter sib2, iclass 27, count 2 2006.257.12:53:00.34#ibcon#flushed, iclass 27, count 2 2006.257.12:53:00.34#ibcon#about to write, iclass 27, count 2 2006.257.12:53:00.34#ibcon#wrote, iclass 27, count 2 2006.257.12:53:00.34#ibcon#about to read 3, iclass 27, count 2 2006.257.12:53:00.36#ibcon#read 3, iclass 27, count 2 2006.257.12:53:00.36#ibcon#about to read 4, iclass 27, count 2 2006.257.12:53:00.36#ibcon#read 4, iclass 27, count 2 2006.257.12:53:00.36#ibcon#about to read 5, iclass 27, count 2 2006.257.12:53:00.36#ibcon#read 5, iclass 27, count 2 2006.257.12:53:00.36#ibcon#about to read 6, iclass 27, count 2 2006.257.12:53:00.36#ibcon#read 6, iclass 27, count 2 2006.257.12:53:00.36#ibcon#end of sib2, iclass 27, count 2 2006.257.12:53:00.36#ibcon#*mode == 0, iclass 27, count 2 2006.257.12:53:00.36#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.12:53:00.36#ibcon#[27=AT05-04\r\n] 2006.257.12:53:00.36#ibcon#*before write, iclass 27, count 2 2006.257.12:53:00.36#ibcon#enter sib2, iclass 27, count 2 2006.257.12:53:00.36#ibcon#flushed, iclass 27, count 2 2006.257.12:53:00.36#ibcon#about to write, iclass 27, count 2 2006.257.12:53:00.36#ibcon#wrote, iclass 27, count 2 2006.257.12:53:00.36#ibcon#about to read 3, iclass 27, count 2 2006.257.12:53:00.39#ibcon#read 3, iclass 27, count 2 2006.257.12:53:00.39#ibcon#about to read 4, iclass 27, count 2 2006.257.12:53:00.39#ibcon#read 4, iclass 27, count 2 2006.257.12:53:00.39#ibcon#about to read 5, iclass 27, count 2 2006.257.12:53:00.39#ibcon#read 5, iclass 27, count 2 2006.257.12:53:00.39#ibcon#about to read 6, iclass 27, count 2 2006.257.12:53:00.39#ibcon#read 6, iclass 27, count 2 2006.257.12:53:00.39#ibcon#end of sib2, iclass 27, count 2 2006.257.12:53:00.39#ibcon#*after write, iclass 27, count 2 2006.257.12:53:00.39#ibcon#*before return 0, iclass 27, count 2 2006.257.12:53:00.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:53:00.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.12:53:00.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.12:53:00.39#ibcon#ireg 7 cls_cnt 0 2006.257.12:53:00.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:53:00.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:53:00.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:53:00.51#ibcon#enter wrdev, iclass 27, count 0 2006.257.12:53:00.51#ibcon#first serial, iclass 27, count 0 2006.257.12:53:00.51#ibcon#enter sib2, iclass 27, count 0 2006.257.12:53:00.51#ibcon#flushed, iclass 27, count 0 2006.257.12:53:00.51#ibcon#about to write, iclass 27, count 0 2006.257.12:53:00.51#ibcon#wrote, iclass 27, count 0 2006.257.12:53:00.51#ibcon#about to read 3, iclass 27, count 0 2006.257.12:53:00.53#ibcon#read 3, iclass 27, count 0 2006.257.12:53:00.53#ibcon#about to read 4, iclass 27, count 0 2006.257.12:53:00.53#ibcon#read 4, iclass 27, count 0 2006.257.12:53:00.53#ibcon#about to read 5, iclass 27, count 0 2006.257.12:53:00.53#ibcon#read 5, iclass 27, count 0 2006.257.12:53:00.53#ibcon#about to read 6, iclass 27, count 0 2006.257.12:53:00.53#ibcon#read 6, iclass 27, count 0 2006.257.12:53:00.53#ibcon#end of sib2, iclass 27, count 0 2006.257.12:53:00.53#ibcon#*mode == 0, iclass 27, count 0 2006.257.12:53:00.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.12:53:00.53#ibcon#[27=USB\r\n] 2006.257.12:53:00.53#ibcon#*before write, iclass 27, count 0 2006.257.12:53:00.53#ibcon#enter sib2, iclass 27, count 0 2006.257.12:53:00.53#ibcon#flushed, iclass 27, count 0 2006.257.12:53:00.53#ibcon#about to write, iclass 27, count 0 2006.257.12:53:00.53#ibcon#wrote, iclass 27, count 0 2006.257.12:53:00.53#ibcon#about to read 3, iclass 27, count 0 2006.257.12:53:00.56#ibcon#read 3, iclass 27, count 0 2006.257.12:53:00.56#ibcon#about to read 4, iclass 27, count 0 2006.257.12:53:00.56#ibcon#read 4, iclass 27, count 0 2006.257.12:53:00.56#ibcon#about to read 5, iclass 27, count 0 2006.257.12:53:00.56#ibcon#read 5, iclass 27, count 0 2006.257.12:53:00.56#ibcon#about to read 6, iclass 27, count 0 2006.257.12:53:00.56#ibcon#read 6, iclass 27, count 0 2006.257.12:53:00.56#ibcon#end of sib2, iclass 27, count 0 2006.257.12:53:00.56#ibcon#*after write, iclass 27, count 0 2006.257.12:53:00.56#ibcon#*before return 0, iclass 27, count 0 2006.257.12:53:00.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:53:00.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.12:53:00.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.12:53:00.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.12:53:00.56$vck44/vblo=6,719.99 2006.257.12:53:00.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.12:53:00.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.12:53:00.56#ibcon#ireg 17 cls_cnt 0 2006.257.12:53:00.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:53:00.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:53:00.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:53:00.56#ibcon#enter wrdev, iclass 29, count 0 2006.257.12:53:00.56#ibcon#first serial, iclass 29, count 0 2006.257.12:53:00.56#ibcon#enter sib2, iclass 29, count 0 2006.257.12:53:00.56#ibcon#flushed, iclass 29, count 0 2006.257.12:53:00.56#ibcon#about to write, iclass 29, count 0 2006.257.12:53:00.56#ibcon#wrote, iclass 29, count 0 2006.257.12:53:00.56#ibcon#about to read 3, iclass 29, count 0 2006.257.12:53:00.58#ibcon#read 3, iclass 29, count 0 2006.257.12:53:00.58#ibcon#about to read 4, iclass 29, count 0 2006.257.12:53:00.58#ibcon#read 4, iclass 29, count 0 2006.257.12:53:00.58#ibcon#about to read 5, iclass 29, count 0 2006.257.12:53:00.58#ibcon#read 5, iclass 29, count 0 2006.257.12:53:00.58#ibcon#about to read 6, iclass 29, count 0 2006.257.12:53:00.58#ibcon#read 6, iclass 29, count 0 2006.257.12:53:00.58#ibcon#end of sib2, iclass 29, count 0 2006.257.12:53:00.58#ibcon#*mode == 0, iclass 29, count 0 2006.257.12:53:00.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.12:53:00.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.12:53:00.58#ibcon#*before write, iclass 29, count 0 2006.257.12:53:00.58#ibcon#enter sib2, iclass 29, count 0 2006.257.12:53:00.58#ibcon#flushed, iclass 29, count 0 2006.257.12:53:00.58#ibcon#about to write, iclass 29, count 0 2006.257.12:53:00.58#ibcon#wrote, iclass 29, count 0 2006.257.12:53:00.58#ibcon#about to read 3, iclass 29, count 0 2006.257.12:53:00.62#ibcon#read 3, iclass 29, count 0 2006.257.12:53:00.62#ibcon#about to read 4, iclass 29, count 0 2006.257.12:53:00.62#ibcon#read 4, iclass 29, count 0 2006.257.12:53:00.62#ibcon#about to read 5, iclass 29, count 0 2006.257.12:53:00.62#ibcon#read 5, iclass 29, count 0 2006.257.12:53:00.62#ibcon#about to read 6, iclass 29, count 0 2006.257.12:53:00.62#ibcon#read 6, iclass 29, count 0 2006.257.12:53:00.62#ibcon#end of sib2, iclass 29, count 0 2006.257.12:53:00.62#ibcon#*after write, iclass 29, count 0 2006.257.12:53:00.62#ibcon#*before return 0, iclass 29, count 0 2006.257.12:53:00.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:53:00.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.12:53:00.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.12:53:00.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.12:53:00.62$vck44/vb=6,4 2006.257.12:53:00.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.12:53:00.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.12:53:00.62#ibcon#ireg 11 cls_cnt 2 2006.257.12:53:00.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:53:00.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:53:00.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:53:00.68#ibcon#enter wrdev, iclass 31, count 2 2006.257.12:53:00.68#ibcon#first serial, iclass 31, count 2 2006.257.12:53:00.68#ibcon#enter sib2, iclass 31, count 2 2006.257.12:53:00.68#ibcon#flushed, iclass 31, count 2 2006.257.12:53:00.68#ibcon#about to write, iclass 31, count 2 2006.257.12:53:00.68#ibcon#wrote, iclass 31, count 2 2006.257.12:53:00.68#ibcon#about to read 3, iclass 31, count 2 2006.257.12:53:00.70#ibcon#read 3, iclass 31, count 2 2006.257.12:53:00.70#ibcon#about to read 4, iclass 31, count 2 2006.257.12:53:00.70#ibcon#read 4, iclass 31, count 2 2006.257.12:53:00.70#ibcon#about to read 5, iclass 31, count 2 2006.257.12:53:00.70#ibcon#read 5, iclass 31, count 2 2006.257.12:53:00.70#ibcon#about to read 6, iclass 31, count 2 2006.257.12:53:00.70#ibcon#read 6, iclass 31, count 2 2006.257.12:53:00.70#ibcon#end of sib2, iclass 31, count 2 2006.257.12:53:00.70#ibcon#*mode == 0, iclass 31, count 2 2006.257.12:53:00.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.12:53:00.70#ibcon#[27=AT06-04\r\n] 2006.257.12:53:00.70#ibcon#*before write, iclass 31, count 2 2006.257.12:53:00.70#ibcon#enter sib2, iclass 31, count 2 2006.257.12:53:00.70#ibcon#flushed, iclass 31, count 2 2006.257.12:53:00.70#ibcon#about to write, iclass 31, count 2 2006.257.12:53:00.70#ibcon#wrote, iclass 31, count 2 2006.257.12:53:00.70#ibcon#about to read 3, iclass 31, count 2 2006.257.12:53:00.73#ibcon#read 3, iclass 31, count 2 2006.257.12:53:00.73#ibcon#about to read 4, iclass 31, count 2 2006.257.12:53:00.73#ibcon#read 4, iclass 31, count 2 2006.257.12:53:00.73#ibcon#about to read 5, iclass 31, count 2 2006.257.12:53:00.73#ibcon#read 5, iclass 31, count 2 2006.257.12:53:00.73#ibcon#about to read 6, iclass 31, count 2 2006.257.12:53:00.73#ibcon#read 6, iclass 31, count 2 2006.257.12:53:00.73#ibcon#end of sib2, iclass 31, count 2 2006.257.12:53:00.73#ibcon#*after write, iclass 31, count 2 2006.257.12:53:00.73#ibcon#*before return 0, iclass 31, count 2 2006.257.12:53:00.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:53:00.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.12:53:00.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.12:53:00.73#ibcon#ireg 7 cls_cnt 0 2006.257.12:53:00.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:53:00.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:53:00.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:53:00.85#ibcon#enter wrdev, iclass 31, count 0 2006.257.12:53:00.85#ibcon#first serial, iclass 31, count 0 2006.257.12:53:00.85#ibcon#enter sib2, iclass 31, count 0 2006.257.12:53:00.85#ibcon#flushed, iclass 31, count 0 2006.257.12:53:00.85#ibcon#about to write, iclass 31, count 0 2006.257.12:53:00.85#ibcon#wrote, iclass 31, count 0 2006.257.12:53:00.85#ibcon#about to read 3, iclass 31, count 0 2006.257.12:53:00.87#ibcon#read 3, iclass 31, count 0 2006.257.12:53:00.87#ibcon#about to read 4, iclass 31, count 0 2006.257.12:53:00.87#ibcon#read 4, iclass 31, count 0 2006.257.12:53:00.87#ibcon#about to read 5, iclass 31, count 0 2006.257.12:53:00.87#ibcon#read 5, iclass 31, count 0 2006.257.12:53:00.87#ibcon#about to read 6, iclass 31, count 0 2006.257.12:53:00.87#ibcon#read 6, iclass 31, count 0 2006.257.12:53:00.87#ibcon#end of sib2, iclass 31, count 0 2006.257.12:53:00.87#ibcon#*mode == 0, iclass 31, count 0 2006.257.12:53:00.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.12:53:00.87#ibcon#[27=USB\r\n] 2006.257.12:53:00.87#ibcon#*before write, iclass 31, count 0 2006.257.12:53:00.87#ibcon#enter sib2, iclass 31, count 0 2006.257.12:53:00.87#ibcon#flushed, iclass 31, count 0 2006.257.12:53:00.87#ibcon#about to write, iclass 31, count 0 2006.257.12:53:00.87#ibcon#wrote, iclass 31, count 0 2006.257.12:53:00.87#ibcon#about to read 3, iclass 31, count 0 2006.257.12:53:00.90#ibcon#read 3, iclass 31, count 0 2006.257.12:53:00.90#ibcon#about to read 4, iclass 31, count 0 2006.257.12:53:00.90#ibcon#read 4, iclass 31, count 0 2006.257.12:53:00.90#ibcon#about to read 5, iclass 31, count 0 2006.257.12:53:00.90#ibcon#read 5, iclass 31, count 0 2006.257.12:53:00.90#ibcon#about to read 6, iclass 31, count 0 2006.257.12:53:00.90#ibcon#read 6, iclass 31, count 0 2006.257.12:53:00.90#ibcon#end of sib2, iclass 31, count 0 2006.257.12:53:00.90#ibcon#*after write, iclass 31, count 0 2006.257.12:53:00.90#ibcon#*before return 0, iclass 31, count 0 2006.257.12:53:00.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:53:00.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.12:53:00.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.12:53:00.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.12:53:00.90$vck44/vblo=7,734.99 2006.257.12:53:00.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.12:53:00.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.12:53:00.90#ibcon#ireg 17 cls_cnt 0 2006.257.12:53:00.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:53:00.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:53:00.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:53:00.90#ibcon#enter wrdev, iclass 33, count 0 2006.257.12:53:00.90#ibcon#first serial, iclass 33, count 0 2006.257.12:53:00.90#ibcon#enter sib2, iclass 33, count 0 2006.257.12:53:00.90#ibcon#flushed, iclass 33, count 0 2006.257.12:53:00.90#ibcon#about to write, iclass 33, count 0 2006.257.12:53:00.90#ibcon#wrote, iclass 33, count 0 2006.257.12:53:00.90#ibcon#about to read 3, iclass 33, count 0 2006.257.12:53:00.92#ibcon#read 3, iclass 33, count 0 2006.257.12:53:00.92#ibcon#about to read 4, iclass 33, count 0 2006.257.12:53:00.92#ibcon#read 4, iclass 33, count 0 2006.257.12:53:00.92#ibcon#about to read 5, iclass 33, count 0 2006.257.12:53:00.92#ibcon#read 5, iclass 33, count 0 2006.257.12:53:00.92#ibcon#about to read 6, iclass 33, count 0 2006.257.12:53:00.92#ibcon#read 6, iclass 33, count 0 2006.257.12:53:00.92#ibcon#end of sib2, iclass 33, count 0 2006.257.12:53:00.92#ibcon#*mode == 0, iclass 33, count 0 2006.257.12:53:00.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.12:53:00.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.12:53:00.92#ibcon#*before write, iclass 33, count 0 2006.257.12:53:00.92#ibcon#enter sib2, iclass 33, count 0 2006.257.12:53:00.92#ibcon#flushed, iclass 33, count 0 2006.257.12:53:00.92#ibcon#about to write, iclass 33, count 0 2006.257.12:53:00.92#ibcon#wrote, iclass 33, count 0 2006.257.12:53:00.92#ibcon#about to read 3, iclass 33, count 0 2006.257.12:53:00.96#ibcon#read 3, iclass 33, count 0 2006.257.12:53:00.96#ibcon#about to read 4, iclass 33, count 0 2006.257.12:53:00.96#ibcon#read 4, iclass 33, count 0 2006.257.12:53:00.96#ibcon#about to read 5, iclass 33, count 0 2006.257.12:53:00.96#ibcon#read 5, iclass 33, count 0 2006.257.12:53:00.96#ibcon#about to read 6, iclass 33, count 0 2006.257.12:53:00.96#ibcon#read 6, iclass 33, count 0 2006.257.12:53:00.96#ibcon#end of sib2, iclass 33, count 0 2006.257.12:53:00.96#ibcon#*after write, iclass 33, count 0 2006.257.12:53:00.96#ibcon#*before return 0, iclass 33, count 0 2006.257.12:53:00.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:53:00.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.12:53:00.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.12:53:00.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.12:53:00.96$vck44/vb=7,4 2006.257.12:53:00.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.12:53:00.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.12:53:00.96#ibcon#ireg 11 cls_cnt 2 2006.257.12:53:00.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:53:01.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:53:01.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:53:01.02#ibcon#enter wrdev, iclass 35, count 2 2006.257.12:53:01.02#ibcon#first serial, iclass 35, count 2 2006.257.12:53:01.02#ibcon#enter sib2, iclass 35, count 2 2006.257.12:53:01.02#ibcon#flushed, iclass 35, count 2 2006.257.12:53:01.02#ibcon#about to write, iclass 35, count 2 2006.257.12:53:01.02#ibcon#wrote, iclass 35, count 2 2006.257.12:53:01.02#ibcon#about to read 3, iclass 35, count 2 2006.257.12:53:01.04#ibcon#read 3, iclass 35, count 2 2006.257.12:53:01.04#ibcon#about to read 4, iclass 35, count 2 2006.257.12:53:01.04#ibcon#read 4, iclass 35, count 2 2006.257.12:53:01.04#ibcon#about to read 5, iclass 35, count 2 2006.257.12:53:01.04#ibcon#read 5, iclass 35, count 2 2006.257.12:53:01.04#ibcon#about to read 6, iclass 35, count 2 2006.257.12:53:01.04#ibcon#read 6, iclass 35, count 2 2006.257.12:53:01.04#ibcon#end of sib2, iclass 35, count 2 2006.257.12:53:01.04#ibcon#*mode == 0, iclass 35, count 2 2006.257.12:53:01.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.12:53:01.04#ibcon#[27=AT07-04\r\n] 2006.257.12:53:01.04#ibcon#*before write, iclass 35, count 2 2006.257.12:53:01.04#ibcon#enter sib2, iclass 35, count 2 2006.257.12:53:01.04#ibcon#flushed, iclass 35, count 2 2006.257.12:53:01.04#ibcon#about to write, iclass 35, count 2 2006.257.12:53:01.04#ibcon#wrote, iclass 35, count 2 2006.257.12:53:01.04#ibcon#about to read 3, iclass 35, count 2 2006.257.12:53:01.07#ibcon#read 3, iclass 35, count 2 2006.257.12:53:01.07#ibcon#about to read 4, iclass 35, count 2 2006.257.12:53:01.07#ibcon#read 4, iclass 35, count 2 2006.257.12:53:01.07#ibcon#about to read 5, iclass 35, count 2 2006.257.12:53:01.07#ibcon#read 5, iclass 35, count 2 2006.257.12:53:01.07#ibcon#about to read 6, iclass 35, count 2 2006.257.12:53:01.07#ibcon#read 6, iclass 35, count 2 2006.257.12:53:01.07#ibcon#end of sib2, iclass 35, count 2 2006.257.12:53:01.07#ibcon#*after write, iclass 35, count 2 2006.257.12:53:01.07#ibcon#*before return 0, iclass 35, count 2 2006.257.12:53:01.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:53:01.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.12:53:01.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.12:53:01.07#ibcon#ireg 7 cls_cnt 0 2006.257.12:53:01.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:53:01.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:53:01.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:53:01.19#ibcon#enter wrdev, iclass 35, count 0 2006.257.12:53:01.19#ibcon#first serial, iclass 35, count 0 2006.257.12:53:01.19#ibcon#enter sib2, iclass 35, count 0 2006.257.12:53:01.19#ibcon#flushed, iclass 35, count 0 2006.257.12:53:01.19#ibcon#about to write, iclass 35, count 0 2006.257.12:53:01.19#ibcon#wrote, iclass 35, count 0 2006.257.12:53:01.19#ibcon#about to read 3, iclass 35, count 0 2006.257.12:53:01.21#ibcon#read 3, iclass 35, count 0 2006.257.12:53:01.21#ibcon#about to read 4, iclass 35, count 0 2006.257.12:53:01.21#ibcon#read 4, iclass 35, count 0 2006.257.12:53:01.21#ibcon#about to read 5, iclass 35, count 0 2006.257.12:53:01.21#ibcon#read 5, iclass 35, count 0 2006.257.12:53:01.21#ibcon#about to read 6, iclass 35, count 0 2006.257.12:53:01.21#ibcon#read 6, iclass 35, count 0 2006.257.12:53:01.21#ibcon#end of sib2, iclass 35, count 0 2006.257.12:53:01.21#ibcon#*mode == 0, iclass 35, count 0 2006.257.12:53:01.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.12:53:01.21#ibcon#[27=USB\r\n] 2006.257.12:53:01.21#ibcon#*before write, iclass 35, count 0 2006.257.12:53:01.21#ibcon#enter sib2, iclass 35, count 0 2006.257.12:53:01.21#ibcon#flushed, iclass 35, count 0 2006.257.12:53:01.21#ibcon#about to write, iclass 35, count 0 2006.257.12:53:01.21#ibcon#wrote, iclass 35, count 0 2006.257.12:53:01.21#ibcon#about to read 3, iclass 35, count 0 2006.257.12:53:01.24#ibcon#read 3, iclass 35, count 0 2006.257.12:53:01.24#ibcon#about to read 4, iclass 35, count 0 2006.257.12:53:01.24#ibcon#read 4, iclass 35, count 0 2006.257.12:53:01.24#ibcon#about to read 5, iclass 35, count 0 2006.257.12:53:01.24#ibcon#read 5, iclass 35, count 0 2006.257.12:53:01.24#ibcon#about to read 6, iclass 35, count 0 2006.257.12:53:01.24#ibcon#read 6, iclass 35, count 0 2006.257.12:53:01.24#ibcon#end of sib2, iclass 35, count 0 2006.257.12:53:01.24#ibcon#*after write, iclass 35, count 0 2006.257.12:53:01.24#ibcon#*before return 0, iclass 35, count 0 2006.257.12:53:01.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:53:01.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.12:53:01.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.12:53:01.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.12:53:01.24$vck44/vblo=8,744.99 2006.257.12:53:01.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.12:53:01.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.12:53:01.24#ibcon#ireg 17 cls_cnt 0 2006.257.12:53:01.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:53:01.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:53:01.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:53:01.24#ibcon#enter wrdev, iclass 37, count 0 2006.257.12:53:01.24#ibcon#first serial, iclass 37, count 0 2006.257.12:53:01.24#ibcon#enter sib2, iclass 37, count 0 2006.257.12:53:01.24#ibcon#flushed, iclass 37, count 0 2006.257.12:53:01.24#ibcon#about to write, iclass 37, count 0 2006.257.12:53:01.24#ibcon#wrote, iclass 37, count 0 2006.257.12:53:01.24#ibcon#about to read 3, iclass 37, count 0 2006.257.12:53:01.26#ibcon#read 3, iclass 37, count 0 2006.257.12:53:01.26#ibcon#about to read 4, iclass 37, count 0 2006.257.12:53:01.26#ibcon#read 4, iclass 37, count 0 2006.257.12:53:01.26#ibcon#about to read 5, iclass 37, count 0 2006.257.12:53:01.26#ibcon#read 5, iclass 37, count 0 2006.257.12:53:01.26#ibcon#about to read 6, iclass 37, count 0 2006.257.12:53:01.26#ibcon#read 6, iclass 37, count 0 2006.257.12:53:01.26#ibcon#end of sib2, iclass 37, count 0 2006.257.12:53:01.26#ibcon#*mode == 0, iclass 37, count 0 2006.257.12:53:01.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.12:53:01.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.12:53:01.26#ibcon#*before write, iclass 37, count 0 2006.257.12:53:01.26#ibcon#enter sib2, iclass 37, count 0 2006.257.12:53:01.26#ibcon#flushed, iclass 37, count 0 2006.257.12:53:01.26#ibcon#about to write, iclass 37, count 0 2006.257.12:53:01.26#ibcon#wrote, iclass 37, count 0 2006.257.12:53:01.26#ibcon#about to read 3, iclass 37, count 0 2006.257.12:53:01.30#ibcon#read 3, iclass 37, count 0 2006.257.12:53:01.30#ibcon#about to read 4, iclass 37, count 0 2006.257.12:53:01.30#ibcon#read 4, iclass 37, count 0 2006.257.12:53:01.30#ibcon#about to read 5, iclass 37, count 0 2006.257.12:53:01.30#ibcon#read 5, iclass 37, count 0 2006.257.12:53:01.30#ibcon#about to read 6, iclass 37, count 0 2006.257.12:53:01.30#ibcon#read 6, iclass 37, count 0 2006.257.12:53:01.30#ibcon#end of sib2, iclass 37, count 0 2006.257.12:53:01.30#ibcon#*after write, iclass 37, count 0 2006.257.12:53:01.30#ibcon#*before return 0, iclass 37, count 0 2006.257.12:53:01.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:53:01.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.12:53:01.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.12:53:01.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.12:53:01.30$vck44/vb=8,4 2006.257.12:53:01.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.12:53:01.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.12:53:01.30#ibcon#ireg 11 cls_cnt 2 2006.257.12:53:01.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:53:01.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:53:01.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:53:01.36#ibcon#enter wrdev, iclass 39, count 2 2006.257.12:53:01.36#ibcon#first serial, iclass 39, count 2 2006.257.12:53:01.36#ibcon#enter sib2, iclass 39, count 2 2006.257.12:53:01.36#ibcon#flushed, iclass 39, count 2 2006.257.12:53:01.36#ibcon#about to write, iclass 39, count 2 2006.257.12:53:01.36#ibcon#wrote, iclass 39, count 2 2006.257.12:53:01.36#ibcon#about to read 3, iclass 39, count 2 2006.257.12:53:01.38#ibcon#read 3, iclass 39, count 2 2006.257.12:53:01.38#ibcon#about to read 4, iclass 39, count 2 2006.257.12:53:01.38#ibcon#read 4, iclass 39, count 2 2006.257.12:53:01.38#ibcon#about to read 5, iclass 39, count 2 2006.257.12:53:01.38#ibcon#read 5, iclass 39, count 2 2006.257.12:53:01.38#ibcon#about to read 6, iclass 39, count 2 2006.257.12:53:01.38#ibcon#read 6, iclass 39, count 2 2006.257.12:53:01.38#ibcon#end of sib2, iclass 39, count 2 2006.257.12:53:01.38#ibcon#*mode == 0, iclass 39, count 2 2006.257.12:53:01.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.12:53:01.38#ibcon#[27=AT08-04\r\n] 2006.257.12:53:01.38#ibcon#*before write, iclass 39, count 2 2006.257.12:53:01.38#ibcon#enter sib2, iclass 39, count 2 2006.257.12:53:01.38#ibcon#flushed, iclass 39, count 2 2006.257.12:53:01.38#ibcon#about to write, iclass 39, count 2 2006.257.12:53:01.38#ibcon#wrote, iclass 39, count 2 2006.257.12:53:01.38#ibcon#about to read 3, iclass 39, count 2 2006.257.12:53:01.41#ibcon#read 3, iclass 39, count 2 2006.257.12:53:01.41#ibcon#about to read 4, iclass 39, count 2 2006.257.12:53:01.41#ibcon#read 4, iclass 39, count 2 2006.257.12:53:01.41#ibcon#about to read 5, iclass 39, count 2 2006.257.12:53:01.41#ibcon#read 5, iclass 39, count 2 2006.257.12:53:01.41#ibcon#about to read 6, iclass 39, count 2 2006.257.12:53:01.41#ibcon#read 6, iclass 39, count 2 2006.257.12:53:01.41#ibcon#end of sib2, iclass 39, count 2 2006.257.12:53:01.41#ibcon#*after write, iclass 39, count 2 2006.257.12:53:01.41#ibcon#*before return 0, iclass 39, count 2 2006.257.12:53:01.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:53:01.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.12:53:01.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.12:53:01.41#ibcon#ireg 7 cls_cnt 0 2006.257.12:53:01.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:53:01.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:53:01.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:53:01.53#ibcon#enter wrdev, iclass 39, count 0 2006.257.12:53:01.53#ibcon#first serial, iclass 39, count 0 2006.257.12:53:01.53#ibcon#enter sib2, iclass 39, count 0 2006.257.12:53:01.53#ibcon#flushed, iclass 39, count 0 2006.257.12:53:01.53#ibcon#about to write, iclass 39, count 0 2006.257.12:53:01.53#ibcon#wrote, iclass 39, count 0 2006.257.12:53:01.53#ibcon#about to read 3, iclass 39, count 0 2006.257.12:53:01.55#ibcon#read 3, iclass 39, count 0 2006.257.12:53:01.55#ibcon#about to read 4, iclass 39, count 0 2006.257.12:53:01.55#ibcon#read 4, iclass 39, count 0 2006.257.12:53:01.55#ibcon#about to read 5, iclass 39, count 0 2006.257.12:53:01.55#ibcon#read 5, iclass 39, count 0 2006.257.12:53:01.55#ibcon#about to read 6, iclass 39, count 0 2006.257.12:53:01.55#ibcon#read 6, iclass 39, count 0 2006.257.12:53:01.55#ibcon#end of sib2, iclass 39, count 0 2006.257.12:53:01.55#ibcon#*mode == 0, iclass 39, count 0 2006.257.12:53:01.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.12:53:01.55#ibcon#[27=USB\r\n] 2006.257.12:53:01.55#ibcon#*before write, iclass 39, count 0 2006.257.12:53:01.55#ibcon#enter sib2, iclass 39, count 0 2006.257.12:53:01.55#ibcon#flushed, iclass 39, count 0 2006.257.12:53:01.55#ibcon#about to write, iclass 39, count 0 2006.257.12:53:01.55#ibcon#wrote, iclass 39, count 0 2006.257.12:53:01.55#ibcon#about to read 3, iclass 39, count 0 2006.257.12:53:01.58#ibcon#read 3, iclass 39, count 0 2006.257.12:53:01.58#ibcon#about to read 4, iclass 39, count 0 2006.257.12:53:01.58#ibcon#read 4, iclass 39, count 0 2006.257.12:53:01.58#ibcon#about to read 5, iclass 39, count 0 2006.257.12:53:01.58#ibcon#read 5, iclass 39, count 0 2006.257.12:53:01.58#ibcon#about to read 6, iclass 39, count 0 2006.257.12:53:01.58#ibcon#read 6, iclass 39, count 0 2006.257.12:53:01.58#ibcon#end of sib2, iclass 39, count 0 2006.257.12:53:01.58#ibcon#*after write, iclass 39, count 0 2006.257.12:53:01.58#ibcon#*before return 0, iclass 39, count 0 2006.257.12:53:01.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:53:01.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.12:53:01.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.12:53:01.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.12:53:01.58$vck44/vabw=wide 2006.257.12:53:01.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.12:53:01.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.12:53:01.58#ibcon#ireg 8 cls_cnt 0 2006.257.12:53:01.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:53:01.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:53:01.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:53:01.58#ibcon#enter wrdev, iclass 3, count 0 2006.257.12:53:01.58#ibcon#first serial, iclass 3, count 0 2006.257.12:53:01.58#ibcon#enter sib2, iclass 3, count 0 2006.257.12:53:01.58#ibcon#flushed, iclass 3, count 0 2006.257.12:53:01.58#ibcon#about to write, iclass 3, count 0 2006.257.12:53:01.58#ibcon#wrote, iclass 3, count 0 2006.257.12:53:01.58#ibcon#about to read 3, iclass 3, count 0 2006.257.12:53:01.60#ibcon#read 3, iclass 3, count 0 2006.257.12:53:01.60#ibcon#about to read 4, iclass 3, count 0 2006.257.12:53:01.60#ibcon#read 4, iclass 3, count 0 2006.257.12:53:01.60#ibcon#about to read 5, iclass 3, count 0 2006.257.12:53:01.60#ibcon#read 5, iclass 3, count 0 2006.257.12:53:01.60#ibcon#about to read 6, iclass 3, count 0 2006.257.12:53:01.60#ibcon#read 6, iclass 3, count 0 2006.257.12:53:01.60#ibcon#end of sib2, iclass 3, count 0 2006.257.12:53:01.60#ibcon#*mode == 0, iclass 3, count 0 2006.257.12:53:01.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.12:53:01.60#ibcon#[25=BW32\r\n] 2006.257.12:53:01.60#ibcon#*before write, iclass 3, count 0 2006.257.12:53:01.60#ibcon#enter sib2, iclass 3, count 0 2006.257.12:53:01.60#ibcon#flushed, iclass 3, count 0 2006.257.12:53:01.60#ibcon#about to write, iclass 3, count 0 2006.257.12:53:01.60#ibcon#wrote, iclass 3, count 0 2006.257.12:53:01.60#ibcon#about to read 3, iclass 3, count 0 2006.257.12:53:01.63#ibcon#read 3, iclass 3, count 0 2006.257.12:53:01.63#ibcon#about to read 4, iclass 3, count 0 2006.257.12:53:01.63#ibcon#read 4, iclass 3, count 0 2006.257.12:53:01.63#ibcon#about to read 5, iclass 3, count 0 2006.257.12:53:01.63#ibcon#read 5, iclass 3, count 0 2006.257.12:53:01.63#ibcon#about to read 6, iclass 3, count 0 2006.257.12:53:01.63#ibcon#read 6, iclass 3, count 0 2006.257.12:53:01.63#ibcon#end of sib2, iclass 3, count 0 2006.257.12:53:01.63#ibcon#*after write, iclass 3, count 0 2006.257.12:53:01.63#ibcon#*before return 0, iclass 3, count 0 2006.257.12:53:01.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:53:01.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.12:53:01.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.12:53:01.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.12:53:01.63$vck44/vbbw=wide 2006.257.12:53:01.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.12:53:01.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.12:53:01.63#ibcon#ireg 8 cls_cnt 0 2006.257.12:53:01.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:53:01.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:53:01.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:53:01.70#ibcon#enter wrdev, iclass 5, count 0 2006.257.12:53:01.70#ibcon#first serial, iclass 5, count 0 2006.257.12:53:01.70#ibcon#enter sib2, iclass 5, count 0 2006.257.12:53:01.70#ibcon#flushed, iclass 5, count 0 2006.257.12:53:01.70#ibcon#about to write, iclass 5, count 0 2006.257.12:53:01.70#ibcon#wrote, iclass 5, count 0 2006.257.12:53:01.70#ibcon#about to read 3, iclass 5, count 0 2006.257.12:53:01.72#ibcon#read 3, iclass 5, count 0 2006.257.12:53:01.72#ibcon#about to read 4, iclass 5, count 0 2006.257.12:53:01.72#ibcon#read 4, iclass 5, count 0 2006.257.12:53:01.72#ibcon#about to read 5, iclass 5, count 0 2006.257.12:53:01.72#ibcon#read 5, iclass 5, count 0 2006.257.12:53:01.72#ibcon#about to read 6, iclass 5, count 0 2006.257.12:53:01.72#ibcon#read 6, iclass 5, count 0 2006.257.12:53:01.72#ibcon#end of sib2, iclass 5, count 0 2006.257.12:53:01.72#ibcon#*mode == 0, iclass 5, count 0 2006.257.12:53:01.72#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.12:53:01.72#ibcon#[27=BW32\r\n] 2006.257.12:53:01.72#ibcon#*before write, iclass 5, count 0 2006.257.12:53:01.72#ibcon#enter sib2, iclass 5, count 0 2006.257.12:53:01.72#ibcon#flushed, iclass 5, count 0 2006.257.12:53:01.72#ibcon#about to write, iclass 5, count 0 2006.257.12:53:01.72#ibcon#wrote, iclass 5, count 0 2006.257.12:53:01.72#ibcon#about to read 3, iclass 5, count 0 2006.257.12:53:01.75#ibcon#read 3, iclass 5, count 0 2006.257.12:53:01.75#ibcon#about to read 4, iclass 5, count 0 2006.257.12:53:01.75#ibcon#read 4, iclass 5, count 0 2006.257.12:53:01.75#ibcon#about to read 5, iclass 5, count 0 2006.257.12:53:01.75#ibcon#read 5, iclass 5, count 0 2006.257.12:53:01.75#ibcon#about to read 6, iclass 5, count 0 2006.257.12:53:01.75#ibcon#read 6, iclass 5, count 0 2006.257.12:53:01.75#ibcon#end of sib2, iclass 5, count 0 2006.257.12:53:01.75#ibcon#*after write, iclass 5, count 0 2006.257.12:53:01.75#ibcon#*before return 0, iclass 5, count 0 2006.257.12:53:01.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:53:01.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.12:53:01.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.12:53:01.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.12:53:01.75$setupk4/ifdk4 2006.257.12:53:01.75$ifdk4/lo= 2006.257.12:53:01.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.12:53:01.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.12:53:01.75$ifdk4/patch= 2006.257.12:53:01.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.12:53:01.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.12:53:01.75$setupk4/!*+20s 2006.257.12:53:05.47#abcon#<5=/14 1.7 4.3 17.80 961013.7\r\n> 2006.257.12:53:05.49#abcon#{5=INTERFACE CLEAR} 2006.257.12:53:05.55#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:53:15.64#abcon#<5=/14 1.7 4.2 17.80 961013.7\r\n> 2006.257.12:53:15.66#abcon#{5=INTERFACE CLEAR} 2006.257.12:53:15.72#abcon#[5=S1D000X0/0*\r\n] 2006.257.12:53:16.25$setupk4/"tpicd 2006.257.12:53:16.25$setupk4/echo=off 2006.257.12:53:16.25$setupk4/xlog=off 2006.257.12:53:16.25:!2006.257.12:56:13 2006.257.12:53:18.14#trakl#Source acquired 2006.257.12:53:19.14#flagr#flagr/antenna,acquired 2006.257.12:56:13.00:preob 2006.257.12:56:14.13/onsource/TRACKING 2006.257.12:56:14.13:!2006.257.12:56:23 2006.257.12:56:23.00:"tape 2006.257.12:56:23.00:"st=record 2006.257.12:56:23.00:data_valid=on 2006.257.12:56:23.00:midob 2006.257.12:56:23.13/onsource/TRACKING 2006.257.12:56:23.13/wx/17.75,1013.7,96 2006.257.12:56:23.20/cable/+6.4801E-03 2006.257.12:56:24.29/va/01,08,usb,yes,32,35 2006.257.12:56:24.29/va/02,07,usb,yes,35,35 2006.257.12:56:24.29/va/03,08,usb,yes,31,33 2006.257.12:56:24.29/va/04,07,usb,yes,36,38 2006.257.12:56:24.29/va/05,04,usb,yes,32,33 2006.257.12:56:24.29/va/06,04,usb,yes,36,35 2006.257.12:56:24.29/va/07,04,usb,yes,37,37 2006.257.12:56:24.29/va/08,04,usb,yes,31,38 2006.257.12:56:24.52/valo/01,524.99,yes,locked 2006.257.12:56:24.52/valo/02,534.99,yes,locked 2006.257.12:56:24.52/valo/03,564.99,yes,locked 2006.257.12:56:24.52/valo/04,624.99,yes,locked 2006.257.12:56:24.52/valo/05,734.99,yes,locked 2006.257.12:56:24.52/valo/06,814.99,yes,locked 2006.257.12:56:24.52/valo/07,864.99,yes,locked 2006.257.12:56:24.52/valo/08,884.99,yes,locked 2006.257.12:56:25.61/vb/01,04,usb,yes,30,34 2006.257.12:56:25.61/vb/02,05,usb,yes,29,32 2006.257.12:56:25.61/vb/03,04,usb,yes,31,34 2006.257.12:56:25.61/vb/04,05,usb,yes,30,29 2006.257.12:56:25.61/vb/05,04,usb,yes,27,30 2006.257.12:56:25.61/vb/06,04,usb,yes,32,28 2006.257.12:56:25.61/vb/07,04,usb,yes,31,31 2006.257.12:56:25.61/vb/08,04,usb,yes,29,32 2006.257.12:56:25.85/vblo/01,629.99,yes,locked 2006.257.12:56:25.85/vblo/02,634.99,yes,locked 2006.257.12:56:25.85/vblo/03,649.99,yes,locked 2006.257.12:56:25.85/vblo/04,679.99,yes,locked 2006.257.12:56:25.85/vblo/05,709.99,yes,locked 2006.257.12:56:25.85/vblo/06,719.99,yes,locked 2006.257.12:56:25.85/vblo/07,734.99,yes,locked 2006.257.12:56:25.85/vblo/08,744.99,yes,locked 2006.257.12:56:26.00/vabw/8 2006.257.12:56:26.15/vbbw/8 2006.257.12:56:26.24/xfe/off,on,15.5 2006.257.12:56:26.61/ifatt/23,28,28,28 2006.257.12:56:27.07/fmout-gps/S +4.58E-07 2006.257.12:56:27.11:!2006.257.13:00:23 2006.257.13:00:23.01:data_valid=off 2006.257.13:00:23.01:"et 2006.257.13:00:23.01:!+3s 2006.257.13:00:26.02:"tape 2006.257.13:00:26.02:postob 2006.257.13:00:26.12/cable/+6.4809E-03 2006.257.13:00:26.12/wx/17.72,1013.9,96 2006.257.13:00:26.18/fmout-gps/S +4.57E-07 2006.257.13:00:26.18:scan_name=257-1301,jd0609,40 2006.257.13:00:26.18:source=1954-388,195800.00,-384506.4,2000.0,ccw 2006.257.13:00:27.14#flagr#flagr/antenna,new-source 2006.257.13:00:27.14:checkk5 2006.257.13:00:27.64/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:00:28.03/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:00:28.43/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:00:28.83/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:00:29.23/chk_obsdata//k5ts1/T2571256??a.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.13:00:29.63/chk_obsdata//k5ts2/T2571256??b.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.13:00:30.04/chk_obsdata//k5ts3/T2571256??c.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.13:00:30.44/chk_obsdata//k5ts4/T2571256??d.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.13:00:31.21/k5log//k5ts1_log_newline 2006.257.13:00:31.91/k5log//k5ts2_log_newline 2006.257.13:00:32.64/k5log//k5ts3_log_newline 2006.257.13:00:33.34/k5log//k5ts4_log_newline 2006.257.13:00:33.37/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:00:33.37:setupk4=1 2006.257.13:00:33.37$setupk4/echo=on 2006.257.13:00:33.37$setupk4/pcalon 2006.257.13:00:33.37$pcalon/"no phase cal control is implemented here 2006.257.13:00:33.37$setupk4/"tpicd=stop 2006.257.13:00:33.37$setupk4/"rec=synch_on 2006.257.13:00:33.37$setupk4/"rec_mode=128 2006.257.13:00:33.37$setupk4/!* 2006.257.13:00:33.37$setupk4/recpk4 2006.257.13:00:33.37$recpk4/recpatch= 2006.257.13:00:33.38$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:00:33.38$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:00:33.38$setupk4/vck44 2006.257.13:00:33.38$vck44/valo=1,524.99 2006.257.13:00:33.38#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.13:00:33.38#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.13:00:33.38#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:33.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:33.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:33.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:33.38#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:00:33.38#ibcon#first serial, iclass 12, count 0 2006.257.13:00:33.38#ibcon#enter sib2, iclass 12, count 0 2006.257.13:00:33.38#ibcon#flushed, iclass 12, count 0 2006.257.13:00:33.38#ibcon#about to write, iclass 12, count 0 2006.257.13:00:33.38#ibcon#wrote, iclass 12, count 0 2006.257.13:00:33.38#ibcon#about to read 3, iclass 12, count 0 2006.257.13:00:33.39#ibcon#read 3, iclass 12, count 0 2006.257.13:00:33.39#ibcon#about to read 4, iclass 12, count 0 2006.257.13:00:33.39#ibcon#read 4, iclass 12, count 0 2006.257.13:00:33.39#ibcon#about to read 5, iclass 12, count 0 2006.257.13:00:33.39#ibcon#read 5, iclass 12, count 0 2006.257.13:00:33.39#ibcon#about to read 6, iclass 12, count 0 2006.257.13:00:33.39#ibcon#read 6, iclass 12, count 0 2006.257.13:00:33.39#ibcon#end of sib2, iclass 12, count 0 2006.257.13:00:33.39#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:00:33.39#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:00:33.39#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:00:33.39#ibcon#*before write, iclass 12, count 0 2006.257.13:00:33.39#ibcon#enter sib2, iclass 12, count 0 2006.257.13:00:33.39#ibcon#flushed, iclass 12, count 0 2006.257.13:00:33.39#ibcon#about to write, iclass 12, count 0 2006.257.13:00:33.39#ibcon#wrote, iclass 12, count 0 2006.257.13:00:33.39#ibcon#about to read 3, iclass 12, count 0 2006.257.13:00:33.44#ibcon#read 3, iclass 12, count 0 2006.257.13:00:33.44#ibcon#about to read 4, iclass 12, count 0 2006.257.13:00:33.44#ibcon#read 4, iclass 12, count 0 2006.257.13:00:33.44#ibcon#about to read 5, iclass 12, count 0 2006.257.13:00:33.44#ibcon#read 5, iclass 12, count 0 2006.257.13:00:33.44#ibcon#about to read 6, iclass 12, count 0 2006.257.13:00:33.44#ibcon#read 6, iclass 12, count 0 2006.257.13:00:33.44#ibcon#end of sib2, iclass 12, count 0 2006.257.13:00:33.44#ibcon#*after write, iclass 12, count 0 2006.257.13:00:33.44#ibcon#*before return 0, iclass 12, count 0 2006.257.13:00:33.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:33.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:33.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:00:33.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:00:33.44$vck44/va=1,8 2006.257.13:00:33.44#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.13:00:33.44#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.13:00:33.44#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:33.44#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:33.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:33.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:33.44#ibcon#enter wrdev, iclass 14, count 2 2006.257.13:00:33.44#ibcon#first serial, iclass 14, count 2 2006.257.13:00:33.44#ibcon#enter sib2, iclass 14, count 2 2006.257.13:00:33.44#ibcon#flushed, iclass 14, count 2 2006.257.13:00:33.44#ibcon#about to write, iclass 14, count 2 2006.257.13:00:33.44#ibcon#wrote, iclass 14, count 2 2006.257.13:00:33.44#ibcon#about to read 3, iclass 14, count 2 2006.257.13:00:33.46#ibcon#read 3, iclass 14, count 2 2006.257.13:00:33.46#ibcon#about to read 4, iclass 14, count 2 2006.257.13:00:33.46#ibcon#read 4, iclass 14, count 2 2006.257.13:00:33.46#ibcon#about to read 5, iclass 14, count 2 2006.257.13:00:33.46#ibcon#read 5, iclass 14, count 2 2006.257.13:00:33.46#ibcon#about to read 6, iclass 14, count 2 2006.257.13:00:33.46#ibcon#read 6, iclass 14, count 2 2006.257.13:00:33.46#ibcon#end of sib2, iclass 14, count 2 2006.257.13:00:33.46#ibcon#*mode == 0, iclass 14, count 2 2006.257.13:00:33.46#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.13:00:33.46#ibcon#[25=AT01-08\r\n] 2006.257.13:00:33.46#ibcon#*before write, iclass 14, count 2 2006.257.13:00:33.46#ibcon#enter sib2, iclass 14, count 2 2006.257.13:00:33.46#ibcon#flushed, iclass 14, count 2 2006.257.13:00:33.46#ibcon#about to write, iclass 14, count 2 2006.257.13:00:33.46#ibcon#wrote, iclass 14, count 2 2006.257.13:00:33.46#ibcon#about to read 3, iclass 14, count 2 2006.257.13:00:33.49#ibcon#read 3, iclass 14, count 2 2006.257.13:00:33.49#ibcon#about to read 4, iclass 14, count 2 2006.257.13:00:33.49#ibcon#read 4, iclass 14, count 2 2006.257.13:00:33.49#ibcon#about to read 5, iclass 14, count 2 2006.257.13:00:33.49#ibcon#read 5, iclass 14, count 2 2006.257.13:00:33.49#ibcon#about to read 6, iclass 14, count 2 2006.257.13:00:33.49#ibcon#read 6, iclass 14, count 2 2006.257.13:00:33.49#ibcon#end of sib2, iclass 14, count 2 2006.257.13:00:33.49#ibcon#*after write, iclass 14, count 2 2006.257.13:00:33.49#ibcon#*before return 0, iclass 14, count 2 2006.257.13:00:33.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:33.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:33.49#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.13:00:33.49#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:33.49#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:33.61#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:33.61#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:33.61#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:00:33.61#ibcon#first serial, iclass 14, count 0 2006.257.13:00:33.61#ibcon#enter sib2, iclass 14, count 0 2006.257.13:00:33.61#ibcon#flushed, iclass 14, count 0 2006.257.13:00:33.61#ibcon#about to write, iclass 14, count 0 2006.257.13:00:33.61#ibcon#wrote, iclass 14, count 0 2006.257.13:00:33.61#ibcon#about to read 3, iclass 14, count 0 2006.257.13:00:33.63#ibcon#read 3, iclass 14, count 0 2006.257.13:00:33.63#ibcon#about to read 4, iclass 14, count 0 2006.257.13:00:33.63#ibcon#read 4, iclass 14, count 0 2006.257.13:00:33.63#ibcon#about to read 5, iclass 14, count 0 2006.257.13:00:33.63#ibcon#read 5, iclass 14, count 0 2006.257.13:00:33.63#ibcon#about to read 6, iclass 14, count 0 2006.257.13:00:33.63#ibcon#read 6, iclass 14, count 0 2006.257.13:00:33.63#ibcon#end of sib2, iclass 14, count 0 2006.257.13:00:33.63#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:00:33.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:00:33.63#ibcon#[25=USB\r\n] 2006.257.13:00:33.63#ibcon#*before write, iclass 14, count 0 2006.257.13:00:33.63#ibcon#enter sib2, iclass 14, count 0 2006.257.13:00:33.63#ibcon#flushed, iclass 14, count 0 2006.257.13:00:33.63#ibcon#about to write, iclass 14, count 0 2006.257.13:00:33.63#ibcon#wrote, iclass 14, count 0 2006.257.13:00:33.63#ibcon#about to read 3, iclass 14, count 0 2006.257.13:00:33.66#ibcon#read 3, iclass 14, count 0 2006.257.13:00:33.66#ibcon#about to read 4, iclass 14, count 0 2006.257.13:00:33.66#ibcon#read 4, iclass 14, count 0 2006.257.13:00:33.66#ibcon#about to read 5, iclass 14, count 0 2006.257.13:00:33.66#ibcon#read 5, iclass 14, count 0 2006.257.13:00:33.66#ibcon#about to read 6, iclass 14, count 0 2006.257.13:00:33.66#ibcon#read 6, iclass 14, count 0 2006.257.13:00:33.66#ibcon#end of sib2, iclass 14, count 0 2006.257.13:00:33.66#ibcon#*after write, iclass 14, count 0 2006.257.13:00:33.66#ibcon#*before return 0, iclass 14, count 0 2006.257.13:00:33.66#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:33.66#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:33.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:00:33.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:00:33.66$vck44/valo=2,534.99 2006.257.13:00:33.66#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.13:00:33.66#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.13:00:33.66#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:33.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:33.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:33.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:33.66#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:00:33.66#ibcon#first serial, iclass 16, count 0 2006.257.13:00:33.66#ibcon#enter sib2, iclass 16, count 0 2006.257.13:00:33.66#ibcon#flushed, iclass 16, count 0 2006.257.13:00:33.66#ibcon#about to write, iclass 16, count 0 2006.257.13:00:33.66#ibcon#wrote, iclass 16, count 0 2006.257.13:00:33.66#ibcon#about to read 3, iclass 16, count 0 2006.257.13:00:33.68#ibcon#read 3, iclass 16, count 0 2006.257.13:00:33.68#ibcon#about to read 4, iclass 16, count 0 2006.257.13:00:33.68#ibcon#read 4, iclass 16, count 0 2006.257.13:00:33.68#ibcon#about to read 5, iclass 16, count 0 2006.257.13:00:33.68#ibcon#read 5, iclass 16, count 0 2006.257.13:00:33.68#ibcon#about to read 6, iclass 16, count 0 2006.257.13:00:33.68#ibcon#read 6, iclass 16, count 0 2006.257.13:00:33.68#ibcon#end of sib2, iclass 16, count 0 2006.257.13:00:33.68#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:00:33.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:00:33.68#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:00:33.68#ibcon#*before write, iclass 16, count 0 2006.257.13:00:33.68#ibcon#enter sib2, iclass 16, count 0 2006.257.13:00:33.68#ibcon#flushed, iclass 16, count 0 2006.257.13:00:33.68#ibcon#about to write, iclass 16, count 0 2006.257.13:00:33.68#ibcon#wrote, iclass 16, count 0 2006.257.13:00:33.68#ibcon#about to read 3, iclass 16, count 0 2006.257.13:00:33.72#ibcon#read 3, iclass 16, count 0 2006.257.13:00:33.72#ibcon#about to read 4, iclass 16, count 0 2006.257.13:00:33.72#ibcon#read 4, iclass 16, count 0 2006.257.13:00:33.72#ibcon#about to read 5, iclass 16, count 0 2006.257.13:00:33.72#ibcon#read 5, iclass 16, count 0 2006.257.13:00:33.72#ibcon#about to read 6, iclass 16, count 0 2006.257.13:00:33.72#ibcon#read 6, iclass 16, count 0 2006.257.13:00:33.72#ibcon#end of sib2, iclass 16, count 0 2006.257.13:00:33.72#ibcon#*after write, iclass 16, count 0 2006.257.13:00:33.72#ibcon#*before return 0, iclass 16, count 0 2006.257.13:00:33.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:33.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:33.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:00:33.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:00:33.72$vck44/va=2,7 2006.257.13:00:33.72#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.13:00:33.72#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.13:00:33.72#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:33.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:33.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:33.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:33.78#ibcon#enter wrdev, iclass 18, count 2 2006.257.13:00:33.78#ibcon#first serial, iclass 18, count 2 2006.257.13:00:33.78#ibcon#enter sib2, iclass 18, count 2 2006.257.13:00:33.78#ibcon#flushed, iclass 18, count 2 2006.257.13:00:33.78#ibcon#about to write, iclass 18, count 2 2006.257.13:00:33.78#ibcon#wrote, iclass 18, count 2 2006.257.13:00:33.78#ibcon#about to read 3, iclass 18, count 2 2006.257.13:00:33.80#ibcon#read 3, iclass 18, count 2 2006.257.13:00:33.80#ibcon#about to read 4, iclass 18, count 2 2006.257.13:00:33.80#ibcon#read 4, iclass 18, count 2 2006.257.13:00:33.80#ibcon#about to read 5, iclass 18, count 2 2006.257.13:00:33.80#ibcon#read 5, iclass 18, count 2 2006.257.13:00:33.80#ibcon#about to read 6, iclass 18, count 2 2006.257.13:00:33.80#ibcon#read 6, iclass 18, count 2 2006.257.13:00:33.80#ibcon#end of sib2, iclass 18, count 2 2006.257.13:00:33.80#ibcon#*mode == 0, iclass 18, count 2 2006.257.13:00:33.80#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.13:00:33.80#ibcon#[25=AT02-07\r\n] 2006.257.13:00:33.80#ibcon#*before write, iclass 18, count 2 2006.257.13:00:33.80#ibcon#enter sib2, iclass 18, count 2 2006.257.13:00:33.80#ibcon#flushed, iclass 18, count 2 2006.257.13:00:33.80#ibcon#about to write, iclass 18, count 2 2006.257.13:00:33.80#ibcon#wrote, iclass 18, count 2 2006.257.13:00:33.80#ibcon#about to read 3, iclass 18, count 2 2006.257.13:00:33.83#ibcon#read 3, iclass 18, count 2 2006.257.13:00:33.83#ibcon#about to read 4, iclass 18, count 2 2006.257.13:00:33.83#ibcon#read 4, iclass 18, count 2 2006.257.13:00:33.83#ibcon#about to read 5, iclass 18, count 2 2006.257.13:00:33.83#ibcon#read 5, iclass 18, count 2 2006.257.13:00:33.83#ibcon#about to read 6, iclass 18, count 2 2006.257.13:00:33.83#ibcon#read 6, iclass 18, count 2 2006.257.13:00:33.83#ibcon#end of sib2, iclass 18, count 2 2006.257.13:00:33.83#ibcon#*after write, iclass 18, count 2 2006.257.13:00:33.83#ibcon#*before return 0, iclass 18, count 2 2006.257.13:00:33.83#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:33.83#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:33.83#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.13:00:33.83#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:33.83#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:33.95#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:33.95#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:33.95#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:00:33.95#ibcon#first serial, iclass 18, count 0 2006.257.13:00:33.95#ibcon#enter sib2, iclass 18, count 0 2006.257.13:00:33.95#ibcon#flushed, iclass 18, count 0 2006.257.13:00:33.95#ibcon#about to write, iclass 18, count 0 2006.257.13:00:33.95#ibcon#wrote, iclass 18, count 0 2006.257.13:00:33.95#ibcon#about to read 3, iclass 18, count 0 2006.257.13:00:33.97#ibcon#read 3, iclass 18, count 0 2006.257.13:00:33.97#ibcon#about to read 4, iclass 18, count 0 2006.257.13:00:33.97#ibcon#read 4, iclass 18, count 0 2006.257.13:00:33.97#ibcon#about to read 5, iclass 18, count 0 2006.257.13:00:33.97#ibcon#read 5, iclass 18, count 0 2006.257.13:00:33.97#ibcon#about to read 6, iclass 18, count 0 2006.257.13:00:33.97#ibcon#read 6, iclass 18, count 0 2006.257.13:00:33.97#ibcon#end of sib2, iclass 18, count 0 2006.257.13:00:33.97#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:00:33.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:00:33.97#ibcon#[25=USB\r\n] 2006.257.13:00:33.97#ibcon#*before write, iclass 18, count 0 2006.257.13:00:33.97#ibcon#enter sib2, iclass 18, count 0 2006.257.13:00:33.97#ibcon#flushed, iclass 18, count 0 2006.257.13:00:33.97#ibcon#about to write, iclass 18, count 0 2006.257.13:00:33.97#ibcon#wrote, iclass 18, count 0 2006.257.13:00:33.97#ibcon#about to read 3, iclass 18, count 0 2006.257.13:00:34.00#ibcon#read 3, iclass 18, count 0 2006.257.13:00:34.00#ibcon#about to read 4, iclass 18, count 0 2006.257.13:00:34.00#ibcon#read 4, iclass 18, count 0 2006.257.13:00:34.00#ibcon#about to read 5, iclass 18, count 0 2006.257.13:00:34.00#ibcon#read 5, iclass 18, count 0 2006.257.13:00:34.00#ibcon#about to read 6, iclass 18, count 0 2006.257.13:00:34.00#ibcon#read 6, iclass 18, count 0 2006.257.13:00:34.00#ibcon#end of sib2, iclass 18, count 0 2006.257.13:00:34.00#ibcon#*after write, iclass 18, count 0 2006.257.13:00:34.00#ibcon#*before return 0, iclass 18, count 0 2006.257.13:00:34.00#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:34.00#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:34.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:00:34.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:00:34.00$vck44/valo=3,564.99 2006.257.13:00:34.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.13:00:34.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.13:00:34.00#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:34.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:34.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:34.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:34.00#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:00:34.00#ibcon#first serial, iclass 20, count 0 2006.257.13:00:34.00#ibcon#enter sib2, iclass 20, count 0 2006.257.13:00:34.00#ibcon#flushed, iclass 20, count 0 2006.257.13:00:34.00#ibcon#about to write, iclass 20, count 0 2006.257.13:00:34.00#ibcon#wrote, iclass 20, count 0 2006.257.13:00:34.00#ibcon#about to read 3, iclass 20, count 0 2006.257.13:00:34.02#ibcon#read 3, iclass 20, count 0 2006.257.13:00:34.02#ibcon#about to read 4, iclass 20, count 0 2006.257.13:00:34.02#ibcon#read 4, iclass 20, count 0 2006.257.13:00:34.02#ibcon#about to read 5, iclass 20, count 0 2006.257.13:00:34.02#ibcon#read 5, iclass 20, count 0 2006.257.13:00:34.02#ibcon#about to read 6, iclass 20, count 0 2006.257.13:00:34.02#ibcon#read 6, iclass 20, count 0 2006.257.13:00:34.02#ibcon#end of sib2, iclass 20, count 0 2006.257.13:00:34.02#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:00:34.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:00:34.02#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:00:34.02#ibcon#*before write, iclass 20, count 0 2006.257.13:00:34.02#ibcon#enter sib2, iclass 20, count 0 2006.257.13:00:34.02#ibcon#flushed, iclass 20, count 0 2006.257.13:00:34.02#ibcon#about to write, iclass 20, count 0 2006.257.13:00:34.02#ibcon#wrote, iclass 20, count 0 2006.257.13:00:34.02#ibcon#about to read 3, iclass 20, count 0 2006.257.13:00:34.06#ibcon#read 3, iclass 20, count 0 2006.257.13:00:34.06#ibcon#about to read 4, iclass 20, count 0 2006.257.13:00:34.06#ibcon#read 4, iclass 20, count 0 2006.257.13:00:34.06#ibcon#about to read 5, iclass 20, count 0 2006.257.13:00:34.06#ibcon#read 5, iclass 20, count 0 2006.257.13:00:34.06#ibcon#about to read 6, iclass 20, count 0 2006.257.13:00:34.06#ibcon#read 6, iclass 20, count 0 2006.257.13:00:34.06#ibcon#end of sib2, iclass 20, count 0 2006.257.13:00:34.06#ibcon#*after write, iclass 20, count 0 2006.257.13:00:34.06#ibcon#*before return 0, iclass 20, count 0 2006.257.13:00:34.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:34.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:34.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:00:34.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:00:34.06$vck44/va=3,8 2006.257.13:00:34.06#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.13:00:34.06#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.13:00:34.06#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:34.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:34.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:34.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:34.12#ibcon#enter wrdev, iclass 22, count 2 2006.257.13:00:34.12#ibcon#first serial, iclass 22, count 2 2006.257.13:00:34.12#ibcon#enter sib2, iclass 22, count 2 2006.257.13:00:34.12#ibcon#flushed, iclass 22, count 2 2006.257.13:00:34.12#ibcon#about to write, iclass 22, count 2 2006.257.13:00:34.12#ibcon#wrote, iclass 22, count 2 2006.257.13:00:34.12#ibcon#about to read 3, iclass 22, count 2 2006.257.13:00:34.14#ibcon#read 3, iclass 22, count 2 2006.257.13:00:34.14#ibcon#about to read 4, iclass 22, count 2 2006.257.13:00:34.14#ibcon#read 4, iclass 22, count 2 2006.257.13:00:34.14#ibcon#about to read 5, iclass 22, count 2 2006.257.13:00:34.14#ibcon#read 5, iclass 22, count 2 2006.257.13:00:34.14#ibcon#about to read 6, iclass 22, count 2 2006.257.13:00:34.14#ibcon#read 6, iclass 22, count 2 2006.257.13:00:34.14#ibcon#end of sib2, iclass 22, count 2 2006.257.13:00:34.14#ibcon#*mode == 0, iclass 22, count 2 2006.257.13:00:34.14#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.13:00:34.14#ibcon#[25=AT03-08\r\n] 2006.257.13:00:34.14#ibcon#*before write, iclass 22, count 2 2006.257.13:00:34.14#ibcon#enter sib2, iclass 22, count 2 2006.257.13:00:34.14#ibcon#flushed, iclass 22, count 2 2006.257.13:00:34.14#ibcon#about to write, iclass 22, count 2 2006.257.13:00:34.14#ibcon#wrote, iclass 22, count 2 2006.257.13:00:34.14#ibcon#about to read 3, iclass 22, count 2 2006.257.13:00:34.17#ibcon#read 3, iclass 22, count 2 2006.257.13:00:34.17#ibcon#about to read 4, iclass 22, count 2 2006.257.13:00:34.17#ibcon#read 4, iclass 22, count 2 2006.257.13:00:34.17#ibcon#about to read 5, iclass 22, count 2 2006.257.13:00:34.17#ibcon#read 5, iclass 22, count 2 2006.257.13:00:34.17#ibcon#about to read 6, iclass 22, count 2 2006.257.13:00:34.17#ibcon#read 6, iclass 22, count 2 2006.257.13:00:34.17#ibcon#end of sib2, iclass 22, count 2 2006.257.13:00:34.17#ibcon#*after write, iclass 22, count 2 2006.257.13:00:34.17#ibcon#*before return 0, iclass 22, count 2 2006.257.13:00:34.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:34.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:34.17#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.13:00:34.17#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:34.17#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:34.29#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:34.29#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:34.29#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:00:34.29#ibcon#first serial, iclass 22, count 0 2006.257.13:00:34.29#ibcon#enter sib2, iclass 22, count 0 2006.257.13:00:34.29#ibcon#flushed, iclass 22, count 0 2006.257.13:00:34.29#ibcon#about to write, iclass 22, count 0 2006.257.13:00:34.29#ibcon#wrote, iclass 22, count 0 2006.257.13:00:34.29#ibcon#about to read 3, iclass 22, count 0 2006.257.13:00:34.31#ibcon#read 3, iclass 22, count 0 2006.257.13:00:34.31#ibcon#about to read 4, iclass 22, count 0 2006.257.13:00:34.31#ibcon#read 4, iclass 22, count 0 2006.257.13:00:34.31#ibcon#about to read 5, iclass 22, count 0 2006.257.13:00:34.31#ibcon#read 5, iclass 22, count 0 2006.257.13:00:34.31#ibcon#about to read 6, iclass 22, count 0 2006.257.13:00:34.31#ibcon#read 6, iclass 22, count 0 2006.257.13:00:34.31#ibcon#end of sib2, iclass 22, count 0 2006.257.13:00:34.31#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:00:34.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:00:34.31#ibcon#[25=USB\r\n] 2006.257.13:00:34.31#ibcon#*before write, iclass 22, count 0 2006.257.13:00:34.31#ibcon#enter sib2, iclass 22, count 0 2006.257.13:00:34.31#ibcon#flushed, iclass 22, count 0 2006.257.13:00:34.31#ibcon#about to write, iclass 22, count 0 2006.257.13:00:34.31#ibcon#wrote, iclass 22, count 0 2006.257.13:00:34.31#ibcon#about to read 3, iclass 22, count 0 2006.257.13:00:34.34#ibcon#read 3, iclass 22, count 0 2006.257.13:00:34.34#ibcon#about to read 4, iclass 22, count 0 2006.257.13:00:34.34#ibcon#read 4, iclass 22, count 0 2006.257.13:00:34.34#ibcon#about to read 5, iclass 22, count 0 2006.257.13:00:34.34#ibcon#read 5, iclass 22, count 0 2006.257.13:00:34.34#ibcon#about to read 6, iclass 22, count 0 2006.257.13:00:34.34#ibcon#read 6, iclass 22, count 0 2006.257.13:00:34.34#ibcon#end of sib2, iclass 22, count 0 2006.257.13:00:34.34#ibcon#*after write, iclass 22, count 0 2006.257.13:00:34.34#ibcon#*before return 0, iclass 22, count 0 2006.257.13:00:34.34#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:34.34#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:34.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:00:34.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:00:34.34$vck44/valo=4,624.99 2006.257.13:00:34.34#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.13:00:34.34#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.13:00:34.34#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:34.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:34.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:34.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:34.34#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:00:34.34#ibcon#first serial, iclass 24, count 0 2006.257.13:00:34.34#ibcon#enter sib2, iclass 24, count 0 2006.257.13:00:34.34#ibcon#flushed, iclass 24, count 0 2006.257.13:00:34.34#ibcon#about to write, iclass 24, count 0 2006.257.13:00:34.34#ibcon#wrote, iclass 24, count 0 2006.257.13:00:34.34#ibcon#about to read 3, iclass 24, count 0 2006.257.13:00:34.36#ibcon#read 3, iclass 24, count 0 2006.257.13:00:34.36#ibcon#about to read 4, iclass 24, count 0 2006.257.13:00:34.36#ibcon#read 4, iclass 24, count 0 2006.257.13:00:34.36#ibcon#about to read 5, iclass 24, count 0 2006.257.13:00:34.36#ibcon#read 5, iclass 24, count 0 2006.257.13:00:34.36#ibcon#about to read 6, iclass 24, count 0 2006.257.13:00:34.36#ibcon#read 6, iclass 24, count 0 2006.257.13:00:34.36#ibcon#end of sib2, iclass 24, count 0 2006.257.13:00:34.36#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:00:34.36#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:00:34.36#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:00:34.36#ibcon#*before write, iclass 24, count 0 2006.257.13:00:34.36#ibcon#enter sib2, iclass 24, count 0 2006.257.13:00:34.36#ibcon#flushed, iclass 24, count 0 2006.257.13:00:34.36#ibcon#about to write, iclass 24, count 0 2006.257.13:00:34.36#ibcon#wrote, iclass 24, count 0 2006.257.13:00:34.36#ibcon#about to read 3, iclass 24, count 0 2006.257.13:00:34.40#ibcon#read 3, iclass 24, count 0 2006.257.13:00:34.40#ibcon#about to read 4, iclass 24, count 0 2006.257.13:00:34.40#ibcon#read 4, iclass 24, count 0 2006.257.13:00:34.40#ibcon#about to read 5, iclass 24, count 0 2006.257.13:00:34.40#ibcon#read 5, iclass 24, count 0 2006.257.13:00:34.40#ibcon#about to read 6, iclass 24, count 0 2006.257.13:00:34.40#ibcon#read 6, iclass 24, count 0 2006.257.13:00:34.40#ibcon#end of sib2, iclass 24, count 0 2006.257.13:00:34.40#ibcon#*after write, iclass 24, count 0 2006.257.13:00:34.40#ibcon#*before return 0, iclass 24, count 0 2006.257.13:00:34.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:34.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:34.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:00:34.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:00:34.40$vck44/va=4,7 2006.257.13:00:34.40#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.13:00:34.40#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.13:00:34.40#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:34.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:34.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:34.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:34.46#ibcon#enter wrdev, iclass 26, count 2 2006.257.13:00:34.46#ibcon#first serial, iclass 26, count 2 2006.257.13:00:34.46#ibcon#enter sib2, iclass 26, count 2 2006.257.13:00:34.46#ibcon#flushed, iclass 26, count 2 2006.257.13:00:34.46#ibcon#about to write, iclass 26, count 2 2006.257.13:00:34.46#ibcon#wrote, iclass 26, count 2 2006.257.13:00:34.46#ibcon#about to read 3, iclass 26, count 2 2006.257.13:00:34.48#ibcon#read 3, iclass 26, count 2 2006.257.13:00:34.48#ibcon#about to read 4, iclass 26, count 2 2006.257.13:00:34.48#ibcon#read 4, iclass 26, count 2 2006.257.13:00:34.48#ibcon#about to read 5, iclass 26, count 2 2006.257.13:00:34.48#ibcon#read 5, iclass 26, count 2 2006.257.13:00:34.48#ibcon#about to read 6, iclass 26, count 2 2006.257.13:00:34.48#ibcon#read 6, iclass 26, count 2 2006.257.13:00:34.48#ibcon#end of sib2, iclass 26, count 2 2006.257.13:00:34.48#ibcon#*mode == 0, iclass 26, count 2 2006.257.13:00:34.48#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.13:00:34.48#ibcon#[25=AT04-07\r\n] 2006.257.13:00:34.48#ibcon#*before write, iclass 26, count 2 2006.257.13:00:34.48#ibcon#enter sib2, iclass 26, count 2 2006.257.13:00:34.48#ibcon#flushed, iclass 26, count 2 2006.257.13:00:34.48#ibcon#about to write, iclass 26, count 2 2006.257.13:00:34.48#ibcon#wrote, iclass 26, count 2 2006.257.13:00:34.48#ibcon#about to read 3, iclass 26, count 2 2006.257.13:00:34.51#ibcon#read 3, iclass 26, count 2 2006.257.13:00:34.51#ibcon#about to read 4, iclass 26, count 2 2006.257.13:00:34.51#ibcon#read 4, iclass 26, count 2 2006.257.13:00:34.51#ibcon#about to read 5, iclass 26, count 2 2006.257.13:00:34.51#ibcon#read 5, iclass 26, count 2 2006.257.13:00:34.51#ibcon#about to read 6, iclass 26, count 2 2006.257.13:00:34.51#ibcon#read 6, iclass 26, count 2 2006.257.13:00:34.51#ibcon#end of sib2, iclass 26, count 2 2006.257.13:00:34.51#ibcon#*after write, iclass 26, count 2 2006.257.13:00:34.51#ibcon#*before return 0, iclass 26, count 2 2006.257.13:00:34.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:34.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:34.51#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.13:00:34.51#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:34.51#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:34.63#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:34.63#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:34.63#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:00:34.63#ibcon#first serial, iclass 26, count 0 2006.257.13:00:34.63#ibcon#enter sib2, iclass 26, count 0 2006.257.13:00:34.63#ibcon#flushed, iclass 26, count 0 2006.257.13:00:34.63#ibcon#about to write, iclass 26, count 0 2006.257.13:00:34.63#ibcon#wrote, iclass 26, count 0 2006.257.13:00:34.63#ibcon#about to read 3, iclass 26, count 0 2006.257.13:00:34.65#ibcon#read 3, iclass 26, count 0 2006.257.13:00:34.65#ibcon#about to read 4, iclass 26, count 0 2006.257.13:00:34.65#ibcon#read 4, iclass 26, count 0 2006.257.13:00:34.65#ibcon#about to read 5, iclass 26, count 0 2006.257.13:00:34.65#ibcon#read 5, iclass 26, count 0 2006.257.13:00:34.65#ibcon#about to read 6, iclass 26, count 0 2006.257.13:00:34.65#ibcon#read 6, iclass 26, count 0 2006.257.13:00:34.65#ibcon#end of sib2, iclass 26, count 0 2006.257.13:00:34.65#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:00:34.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:00:34.65#ibcon#[25=USB\r\n] 2006.257.13:00:34.65#ibcon#*before write, iclass 26, count 0 2006.257.13:00:34.65#ibcon#enter sib2, iclass 26, count 0 2006.257.13:00:34.65#ibcon#flushed, iclass 26, count 0 2006.257.13:00:34.65#ibcon#about to write, iclass 26, count 0 2006.257.13:00:34.65#ibcon#wrote, iclass 26, count 0 2006.257.13:00:34.65#ibcon#about to read 3, iclass 26, count 0 2006.257.13:00:34.68#ibcon#read 3, iclass 26, count 0 2006.257.13:00:34.68#ibcon#about to read 4, iclass 26, count 0 2006.257.13:00:34.68#ibcon#read 4, iclass 26, count 0 2006.257.13:00:34.68#ibcon#about to read 5, iclass 26, count 0 2006.257.13:00:34.68#ibcon#read 5, iclass 26, count 0 2006.257.13:00:34.68#ibcon#about to read 6, iclass 26, count 0 2006.257.13:00:34.68#ibcon#read 6, iclass 26, count 0 2006.257.13:00:34.68#ibcon#end of sib2, iclass 26, count 0 2006.257.13:00:34.68#ibcon#*after write, iclass 26, count 0 2006.257.13:00:34.68#ibcon#*before return 0, iclass 26, count 0 2006.257.13:00:34.68#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:34.68#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:34.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:00:34.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:00:34.68$vck44/valo=5,734.99 2006.257.13:00:34.68#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.13:00:34.68#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.13:00:34.68#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:34.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:34.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:34.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:34.68#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:00:34.68#ibcon#first serial, iclass 28, count 0 2006.257.13:00:34.68#ibcon#enter sib2, iclass 28, count 0 2006.257.13:00:34.68#ibcon#flushed, iclass 28, count 0 2006.257.13:00:34.68#ibcon#about to write, iclass 28, count 0 2006.257.13:00:34.68#ibcon#wrote, iclass 28, count 0 2006.257.13:00:34.68#ibcon#about to read 3, iclass 28, count 0 2006.257.13:00:34.70#ibcon#read 3, iclass 28, count 0 2006.257.13:00:34.70#ibcon#about to read 4, iclass 28, count 0 2006.257.13:00:34.70#ibcon#read 4, iclass 28, count 0 2006.257.13:00:34.70#ibcon#about to read 5, iclass 28, count 0 2006.257.13:00:34.70#ibcon#read 5, iclass 28, count 0 2006.257.13:00:34.70#ibcon#about to read 6, iclass 28, count 0 2006.257.13:00:34.70#ibcon#read 6, iclass 28, count 0 2006.257.13:00:34.70#ibcon#end of sib2, iclass 28, count 0 2006.257.13:00:34.70#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:00:34.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:00:34.70#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:00:34.70#ibcon#*before write, iclass 28, count 0 2006.257.13:00:34.70#ibcon#enter sib2, iclass 28, count 0 2006.257.13:00:34.70#ibcon#flushed, iclass 28, count 0 2006.257.13:00:34.70#ibcon#about to write, iclass 28, count 0 2006.257.13:00:34.70#ibcon#wrote, iclass 28, count 0 2006.257.13:00:34.70#ibcon#about to read 3, iclass 28, count 0 2006.257.13:00:34.74#ibcon#read 3, iclass 28, count 0 2006.257.13:00:34.74#ibcon#about to read 4, iclass 28, count 0 2006.257.13:00:34.74#ibcon#read 4, iclass 28, count 0 2006.257.13:00:34.74#ibcon#about to read 5, iclass 28, count 0 2006.257.13:00:34.74#ibcon#read 5, iclass 28, count 0 2006.257.13:00:34.74#ibcon#about to read 6, iclass 28, count 0 2006.257.13:00:34.74#ibcon#read 6, iclass 28, count 0 2006.257.13:00:34.74#ibcon#end of sib2, iclass 28, count 0 2006.257.13:00:34.74#ibcon#*after write, iclass 28, count 0 2006.257.13:00:34.74#ibcon#*before return 0, iclass 28, count 0 2006.257.13:00:34.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:34.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:34.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:00:34.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:00:34.74$vck44/va=5,4 2006.257.13:00:34.74#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.13:00:34.74#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.13:00:34.74#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:34.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:34.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:34.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:34.80#ibcon#enter wrdev, iclass 30, count 2 2006.257.13:00:34.80#ibcon#first serial, iclass 30, count 2 2006.257.13:00:34.80#ibcon#enter sib2, iclass 30, count 2 2006.257.13:00:34.80#ibcon#flushed, iclass 30, count 2 2006.257.13:00:34.80#ibcon#about to write, iclass 30, count 2 2006.257.13:00:34.80#ibcon#wrote, iclass 30, count 2 2006.257.13:00:34.80#ibcon#about to read 3, iclass 30, count 2 2006.257.13:00:34.82#ibcon#read 3, iclass 30, count 2 2006.257.13:00:34.82#ibcon#about to read 4, iclass 30, count 2 2006.257.13:00:34.82#ibcon#read 4, iclass 30, count 2 2006.257.13:00:34.82#ibcon#about to read 5, iclass 30, count 2 2006.257.13:00:34.82#ibcon#read 5, iclass 30, count 2 2006.257.13:00:34.82#ibcon#about to read 6, iclass 30, count 2 2006.257.13:00:34.82#ibcon#read 6, iclass 30, count 2 2006.257.13:00:34.82#ibcon#end of sib2, iclass 30, count 2 2006.257.13:00:34.82#ibcon#*mode == 0, iclass 30, count 2 2006.257.13:00:34.82#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.13:00:34.82#ibcon#[25=AT05-04\r\n] 2006.257.13:00:34.82#ibcon#*before write, iclass 30, count 2 2006.257.13:00:34.82#ibcon#enter sib2, iclass 30, count 2 2006.257.13:00:34.82#ibcon#flushed, iclass 30, count 2 2006.257.13:00:34.82#ibcon#about to write, iclass 30, count 2 2006.257.13:00:34.82#ibcon#wrote, iclass 30, count 2 2006.257.13:00:34.82#ibcon#about to read 3, iclass 30, count 2 2006.257.13:00:34.85#ibcon#read 3, iclass 30, count 2 2006.257.13:00:34.85#ibcon#about to read 4, iclass 30, count 2 2006.257.13:00:34.85#ibcon#read 4, iclass 30, count 2 2006.257.13:00:34.85#ibcon#about to read 5, iclass 30, count 2 2006.257.13:00:34.85#ibcon#read 5, iclass 30, count 2 2006.257.13:00:34.85#ibcon#about to read 6, iclass 30, count 2 2006.257.13:00:34.85#ibcon#read 6, iclass 30, count 2 2006.257.13:00:34.85#ibcon#end of sib2, iclass 30, count 2 2006.257.13:00:34.85#ibcon#*after write, iclass 30, count 2 2006.257.13:00:34.85#ibcon#*before return 0, iclass 30, count 2 2006.257.13:00:34.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:34.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:34.85#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.13:00:34.85#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:34.85#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:34.97#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:34.97#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:34.97#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:00:34.97#ibcon#first serial, iclass 30, count 0 2006.257.13:00:34.97#ibcon#enter sib2, iclass 30, count 0 2006.257.13:00:34.97#ibcon#flushed, iclass 30, count 0 2006.257.13:00:34.97#ibcon#about to write, iclass 30, count 0 2006.257.13:00:34.97#ibcon#wrote, iclass 30, count 0 2006.257.13:00:34.97#ibcon#about to read 3, iclass 30, count 0 2006.257.13:00:34.99#ibcon#read 3, iclass 30, count 0 2006.257.13:00:34.99#ibcon#about to read 4, iclass 30, count 0 2006.257.13:00:34.99#ibcon#read 4, iclass 30, count 0 2006.257.13:00:34.99#ibcon#about to read 5, iclass 30, count 0 2006.257.13:00:34.99#ibcon#read 5, iclass 30, count 0 2006.257.13:00:34.99#ibcon#about to read 6, iclass 30, count 0 2006.257.13:00:34.99#ibcon#read 6, iclass 30, count 0 2006.257.13:00:34.99#ibcon#end of sib2, iclass 30, count 0 2006.257.13:00:34.99#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:00:34.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:00:34.99#ibcon#[25=USB\r\n] 2006.257.13:00:34.99#ibcon#*before write, iclass 30, count 0 2006.257.13:00:34.99#ibcon#enter sib2, iclass 30, count 0 2006.257.13:00:34.99#ibcon#flushed, iclass 30, count 0 2006.257.13:00:34.99#ibcon#about to write, iclass 30, count 0 2006.257.13:00:34.99#ibcon#wrote, iclass 30, count 0 2006.257.13:00:34.99#ibcon#about to read 3, iclass 30, count 0 2006.257.13:00:35.02#ibcon#read 3, iclass 30, count 0 2006.257.13:00:35.02#ibcon#about to read 4, iclass 30, count 0 2006.257.13:00:35.02#ibcon#read 4, iclass 30, count 0 2006.257.13:00:35.02#ibcon#about to read 5, iclass 30, count 0 2006.257.13:00:35.02#ibcon#read 5, iclass 30, count 0 2006.257.13:00:35.02#ibcon#about to read 6, iclass 30, count 0 2006.257.13:00:35.02#ibcon#read 6, iclass 30, count 0 2006.257.13:00:35.02#ibcon#end of sib2, iclass 30, count 0 2006.257.13:00:35.02#ibcon#*after write, iclass 30, count 0 2006.257.13:00:35.02#ibcon#*before return 0, iclass 30, count 0 2006.257.13:00:35.02#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:35.02#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:35.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:00:35.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:00:35.02$vck44/valo=6,814.99 2006.257.13:00:35.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.13:00:35.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.13:00:35.02#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:35.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:35.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:35.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:35.02#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:00:35.02#ibcon#first serial, iclass 32, count 0 2006.257.13:00:35.02#ibcon#enter sib2, iclass 32, count 0 2006.257.13:00:35.02#ibcon#flushed, iclass 32, count 0 2006.257.13:00:35.02#ibcon#about to write, iclass 32, count 0 2006.257.13:00:35.02#ibcon#wrote, iclass 32, count 0 2006.257.13:00:35.02#ibcon#about to read 3, iclass 32, count 0 2006.257.13:00:35.04#ibcon#read 3, iclass 32, count 0 2006.257.13:00:35.04#ibcon#about to read 4, iclass 32, count 0 2006.257.13:00:35.04#ibcon#read 4, iclass 32, count 0 2006.257.13:00:35.04#ibcon#about to read 5, iclass 32, count 0 2006.257.13:00:35.04#ibcon#read 5, iclass 32, count 0 2006.257.13:00:35.04#ibcon#about to read 6, iclass 32, count 0 2006.257.13:00:35.04#ibcon#read 6, iclass 32, count 0 2006.257.13:00:35.04#ibcon#end of sib2, iclass 32, count 0 2006.257.13:00:35.04#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:00:35.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:00:35.04#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:00:35.04#ibcon#*before write, iclass 32, count 0 2006.257.13:00:35.04#ibcon#enter sib2, iclass 32, count 0 2006.257.13:00:35.04#ibcon#flushed, iclass 32, count 0 2006.257.13:00:35.04#ibcon#about to write, iclass 32, count 0 2006.257.13:00:35.04#ibcon#wrote, iclass 32, count 0 2006.257.13:00:35.04#ibcon#about to read 3, iclass 32, count 0 2006.257.13:00:35.08#ibcon#read 3, iclass 32, count 0 2006.257.13:00:35.08#ibcon#about to read 4, iclass 32, count 0 2006.257.13:00:35.08#ibcon#read 4, iclass 32, count 0 2006.257.13:00:35.08#ibcon#about to read 5, iclass 32, count 0 2006.257.13:00:35.08#ibcon#read 5, iclass 32, count 0 2006.257.13:00:35.08#ibcon#about to read 6, iclass 32, count 0 2006.257.13:00:35.08#ibcon#read 6, iclass 32, count 0 2006.257.13:00:35.08#ibcon#end of sib2, iclass 32, count 0 2006.257.13:00:35.08#ibcon#*after write, iclass 32, count 0 2006.257.13:00:35.08#ibcon#*before return 0, iclass 32, count 0 2006.257.13:00:35.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:35.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:35.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:00:35.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:00:35.08$vck44/va=6,4 2006.257.13:00:35.08#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.13:00:35.08#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.13:00:35.08#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:35.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:35.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:35.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:35.14#ibcon#enter wrdev, iclass 34, count 2 2006.257.13:00:35.14#ibcon#first serial, iclass 34, count 2 2006.257.13:00:35.14#ibcon#enter sib2, iclass 34, count 2 2006.257.13:00:35.14#ibcon#flushed, iclass 34, count 2 2006.257.13:00:35.14#ibcon#about to write, iclass 34, count 2 2006.257.13:00:35.14#ibcon#wrote, iclass 34, count 2 2006.257.13:00:35.14#ibcon#about to read 3, iclass 34, count 2 2006.257.13:00:35.16#ibcon#read 3, iclass 34, count 2 2006.257.13:00:35.16#ibcon#about to read 4, iclass 34, count 2 2006.257.13:00:35.16#ibcon#read 4, iclass 34, count 2 2006.257.13:00:35.16#ibcon#about to read 5, iclass 34, count 2 2006.257.13:00:35.16#ibcon#read 5, iclass 34, count 2 2006.257.13:00:35.16#ibcon#about to read 6, iclass 34, count 2 2006.257.13:00:35.16#ibcon#read 6, iclass 34, count 2 2006.257.13:00:35.16#ibcon#end of sib2, iclass 34, count 2 2006.257.13:00:35.16#ibcon#*mode == 0, iclass 34, count 2 2006.257.13:00:35.16#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.13:00:35.16#ibcon#[25=AT06-04\r\n] 2006.257.13:00:35.16#ibcon#*before write, iclass 34, count 2 2006.257.13:00:35.16#ibcon#enter sib2, iclass 34, count 2 2006.257.13:00:35.16#ibcon#flushed, iclass 34, count 2 2006.257.13:00:35.16#ibcon#about to write, iclass 34, count 2 2006.257.13:00:35.16#ibcon#wrote, iclass 34, count 2 2006.257.13:00:35.16#ibcon#about to read 3, iclass 34, count 2 2006.257.13:00:35.19#ibcon#read 3, iclass 34, count 2 2006.257.13:00:35.19#ibcon#about to read 4, iclass 34, count 2 2006.257.13:00:35.19#ibcon#read 4, iclass 34, count 2 2006.257.13:00:35.19#ibcon#about to read 5, iclass 34, count 2 2006.257.13:00:35.19#ibcon#read 5, iclass 34, count 2 2006.257.13:00:35.19#ibcon#about to read 6, iclass 34, count 2 2006.257.13:00:35.19#ibcon#read 6, iclass 34, count 2 2006.257.13:00:35.19#ibcon#end of sib2, iclass 34, count 2 2006.257.13:00:35.19#ibcon#*after write, iclass 34, count 2 2006.257.13:00:35.19#ibcon#*before return 0, iclass 34, count 2 2006.257.13:00:35.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:35.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:35.19#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.13:00:35.19#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:35.19#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:35.31#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:35.31#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:35.31#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:00:35.31#ibcon#first serial, iclass 34, count 0 2006.257.13:00:35.31#ibcon#enter sib2, iclass 34, count 0 2006.257.13:00:35.31#ibcon#flushed, iclass 34, count 0 2006.257.13:00:35.31#ibcon#about to write, iclass 34, count 0 2006.257.13:00:35.31#ibcon#wrote, iclass 34, count 0 2006.257.13:00:35.31#ibcon#about to read 3, iclass 34, count 0 2006.257.13:00:35.33#ibcon#read 3, iclass 34, count 0 2006.257.13:00:35.33#ibcon#about to read 4, iclass 34, count 0 2006.257.13:00:35.33#ibcon#read 4, iclass 34, count 0 2006.257.13:00:35.33#ibcon#about to read 5, iclass 34, count 0 2006.257.13:00:35.33#ibcon#read 5, iclass 34, count 0 2006.257.13:00:35.33#ibcon#about to read 6, iclass 34, count 0 2006.257.13:00:35.33#ibcon#read 6, iclass 34, count 0 2006.257.13:00:35.33#ibcon#end of sib2, iclass 34, count 0 2006.257.13:00:35.33#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:00:35.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:00:35.33#ibcon#[25=USB\r\n] 2006.257.13:00:35.33#ibcon#*before write, iclass 34, count 0 2006.257.13:00:35.33#ibcon#enter sib2, iclass 34, count 0 2006.257.13:00:35.33#ibcon#flushed, iclass 34, count 0 2006.257.13:00:35.33#ibcon#about to write, iclass 34, count 0 2006.257.13:00:35.33#ibcon#wrote, iclass 34, count 0 2006.257.13:00:35.33#ibcon#about to read 3, iclass 34, count 0 2006.257.13:00:35.36#ibcon#read 3, iclass 34, count 0 2006.257.13:00:35.36#ibcon#about to read 4, iclass 34, count 0 2006.257.13:00:35.36#ibcon#read 4, iclass 34, count 0 2006.257.13:00:35.36#ibcon#about to read 5, iclass 34, count 0 2006.257.13:00:35.36#ibcon#read 5, iclass 34, count 0 2006.257.13:00:35.36#ibcon#about to read 6, iclass 34, count 0 2006.257.13:00:35.36#ibcon#read 6, iclass 34, count 0 2006.257.13:00:35.36#ibcon#end of sib2, iclass 34, count 0 2006.257.13:00:35.36#ibcon#*after write, iclass 34, count 0 2006.257.13:00:35.36#ibcon#*before return 0, iclass 34, count 0 2006.257.13:00:35.36#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:35.36#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:35.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:00:35.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:00:35.36$vck44/valo=7,864.99 2006.257.13:00:35.36#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.13:00:35.36#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.13:00:35.36#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:35.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:35.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:35.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:35.36#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:00:35.36#ibcon#first serial, iclass 36, count 0 2006.257.13:00:35.36#ibcon#enter sib2, iclass 36, count 0 2006.257.13:00:35.36#ibcon#flushed, iclass 36, count 0 2006.257.13:00:35.36#ibcon#about to write, iclass 36, count 0 2006.257.13:00:35.36#ibcon#wrote, iclass 36, count 0 2006.257.13:00:35.36#ibcon#about to read 3, iclass 36, count 0 2006.257.13:00:35.38#ibcon#read 3, iclass 36, count 0 2006.257.13:00:35.38#ibcon#about to read 4, iclass 36, count 0 2006.257.13:00:35.38#ibcon#read 4, iclass 36, count 0 2006.257.13:00:35.38#ibcon#about to read 5, iclass 36, count 0 2006.257.13:00:35.38#ibcon#read 5, iclass 36, count 0 2006.257.13:00:35.38#ibcon#about to read 6, iclass 36, count 0 2006.257.13:00:35.38#ibcon#read 6, iclass 36, count 0 2006.257.13:00:35.38#ibcon#end of sib2, iclass 36, count 0 2006.257.13:00:35.38#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:00:35.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:00:35.38#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:00:35.38#ibcon#*before write, iclass 36, count 0 2006.257.13:00:35.38#ibcon#enter sib2, iclass 36, count 0 2006.257.13:00:35.38#ibcon#flushed, iclass 36, count 0 2006.257.13:00:35.38#ibcon#about to write, iclass 36, count 0 2006.257.13:00:35.38#ibcon#wrote, iclass 36, count 0 2006.257.13:00:35.38#ibcon#about to read 3, iclass 36, count 0 2006.257.13:00:35.42#ibcon#read 3, iclass 36, count 0 2006.257.13:00:35.42#ibcon#about to read 4, iclass 36, count 0 2006.257.13:00:35.42#ibcon#read 4, iclass 36, count 0 2006.257.13:00:35.42#ibcon#about to read 5, iclass 36, count 0 2006.257.13:00:35.42#ibcon#read 5, iclass 36, count 0 2006.257.13:00:35.42#ibcon#about to read 6, iclass 36, count 0 2006.257.13:00:35.42#ibcon#read 6, iclass 36, count 0 2006.257.13:00:35.42#ibcon#end of sib2, iclass 36, count 0 2006.257.13:00:35.42#ibcon#*after write, iclass 36, count 0 2006.257.13:00:35.42#ibcon#*before return 0, iclass 36, count 0 2006.257.13:00:35.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:35.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:35.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:00:35.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:00:35.42$vck44/va=7,4 2006.257.13:00:35.42#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.13:00:35.42#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.13:00:35.42#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:35.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:35.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:35.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:35.48#ibcon#enter wrdev, iclass 38, count 2 2006.257.13:00:35.48#ibcon#first serial, iclass 38, count 2 2006.257.13:00:35.48#ibcon#enter sib2, iclass 38, count 2 2006.257.13:00:35.48#ibcon#flushed, iclass 38, count 2 2006.257.13:00:35.48#ibcon#about to write, iclass 38, count 2 2006.257.13:00:35.48#ibcon#wrote, iclass 38, count 2 2006.257.13:00:35.48#ibcon#about to read 3, iclass 38, count 2 2006.257.13:00:35.50#ibcon#read 3, iclass 38, count 2 2006.257.13:00:35.50#ibcon#about to read 4, iclass 38, count 2 2006.257.13:00:35.50#ibcon#read 4, iclass 38, count 2 2006.257.13:00:35.50#ibcon#about to read 5, iclass 38, count 2 2006.257.13:00:35.50#ibcon#read 5, iclass 38, count 2 2006.257.13:00:35.50#ibcon#about to read 6, iclass 38, count 2 2006.257.13:00:35.50#ibcon#read 6, iclass 38, count 2 2006.257.13:00:35.50#ibcon#end of sib2, iclass 38, count 2 2006.257.13:00:35.50#ibcon#*mode == 0, iclass 38, count 2 2006.257.13:00:35.50#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.13:00:35.50#ibcon#[25=AT07-04\r\n] 2006.257.13:00:35.50#ibcon#*before write, iclass 38, count 2 2006.257.13:00:35.50#ibcon#enter sib2, iclass 38, count 2 2006.257.13:00:35.50#ibcon#flushed, iclass 38, count 2 2006.257.13:00:35.50#ibcon#about to write, iclass 38, count 2 2006.257.13:00:35.50#ibcon#wrote, iclass 38, count 2 2006.257.13:00:35.50#ibcon#about to read 3, iclass 38, count 2 2006.257.13:00:35.53#ibcon#read 3, iclass 38, count 2 2006.257.13:00:35.53#ibcon#about to read 4, iclass 38, count 2 2006.257.13:00:35.53#ibcon#read 4, iclass 38, count 2 2006.257.13:00:35.53#ibcon#about to read 5, iclass 38, count 2 2006.257.13:00:35.53#ibcon#read 5, iclass 38, count 2 2006.257.13:00:35.53#ibcon#about to read 6, iclass 38, count 2 2006.257.13:00:35.53#ibcon#read 6, iclass 38, count 2 2006.257.13:00:35.53#ibcon#end of sib2, iclass 38, count 2 2006.257.13:00:35.53#ibcon#*after write, iclass 38, count 2 2006.257.13:00:35.53#ibcon#*before return 0, iclass 38, count 2 2006.257.13:00:35.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:35.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:35.53#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.13:00:35.53#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:35.53#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:35.65#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:35.65#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:35.65#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:00:35.65#ibcon#first serial, iclass 38, count 0 2006.257.13:00:35.65#ibcon#enter sib2, iclass 38, count 0 2006.257.13:00:35.65#ibcon#flushed, iclass 38, count 0 2006.257.13:00:35.65#ibcon#about to write, iclass 38, count 0 2006.257.13:00:35.65#ibcon#wrote, iclass 38, count 0 2006.257.13:00:35.65#ibcon#about to read 3, iclass 38, count 0 2006.257.13:00:35.67#ibcon#read 3, iclass 38, count 0 2006.257.13:00:35.67#ibcon#about to read 4, iclass 38, count 0 2006.257.13:00:35.67#ibcon#read 4, iclass 38, count 0 2006.257.13:00:35.67#ibcon#about to read 5, iclass 38, count 0 2006.257.13:00:35.67#ibcon#read 5, iclass 38, count 0 2006.257.13:00:35.67#ibcon#about to read 6, iclass 38, count 0 2006.257.13:00:35.67#ibcon#read 6, iclass 38, count 0 2006.257.13:00:35.67#ibcon#end of sib2, iclass 38, count 0 2006.257.13:00:35.67#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:00:35.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:00:35.67#ibcon#[25=USB\r\n] 2006.257.13:00:35.67#ibcon#*before write, iclass 38, count 0 2006.257.13:00:35.67#ibcon#enter sib2, iclass 38, count 0 2006.257.13:00:35.67#ibcon#flushed, iclass 38, count 0 2006.257.13:00:35.67#ibcon#about to write, iclass 38, count 0 2006.257.13:00:35.67#ibcon#wrote, iclass 38, count 0 2006.257.13:00:35.67#ibcon#about to read 3, iclass 38, count 0 2006.257.13:00:35.70#ibcon#read 3, iclass 38, count 0 2006.257.13:00:35.70#ibcon#about to read 4, iclass 38, count 0 2006.257.13:00:35.70#ibcon#read 4, iclass 38, count 0 2006.257.13:00:35.70#ibcon#about to read 5, iclass 38, count 0 2006.257.13:00:35.70#ibcon#read 5, iclass 38, count 0 2006.257.13:00:35.70#ibcon#about to read 6, iclass 38, count 0 2006.257.13:00:35.70#ibcon#read 6, iclass 38, count 0 2006.257.13:00:35.70#ibcon#end of sib2, iclass 38, count 0 2006.257.13:00:35.70#ibcon#*after write, iclass 38, count 0 2006.257.13:00:35.70#ibcon#*before return 0, iclass 38, count 0 2006.257.13:00:35.70#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:35.70#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:35.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:00:35.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:00:35.70$vck44/valo=8,884.99 2006.257.13:00:35.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.13:00:35.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.13:00:35.70#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:35.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:35.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:35.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:35.70#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:00:35.70#ibcon#first serial, iclass 40, count 0 2006.257.13:00:35.70#ibcon#enter sib2, iclass 40, count 0 2006.257.13:00:35.70#ibcon#flushed, iclass 40, count 0 2006.257.13:00:35.70#ibcon#about to write, iclass 40, count 0 2006.257.13:00:35.70#ibcon#wrote, iclass 40, count 0 2006.257.13:00:35.70#ibcon#about to read 3, iclass 40, count 0 2006.257.13:00:35.72#ibcon#read 3, iclass 40, count 0 2006.257.13:00:35.72#ibcon#about to read 4, iclass 40, count 0 2006.257.13:00:35.72#ibcon#read 4, iclass 40, count 0 2006.257.13:00:35.72#ibcon#about to read 5, iclass 40, count 0 2006.257.13:00:35.72#ibcon#read 5, iclass 40, count 0 2006.257.13:00:35.72#ibcon#about to read 6, iclass 40, count 0 2006.257.13:00:35.72#ibcon#read 6, iclass 40, count 0 2006.257.13:00:35.72#ibcon#end of sib2, iclass 40, count 0 2006.257.13:00:35.72#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:00:35.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:00:35.72#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:00:35.72#ibcon#*before write, iclass 40, count 0 2006.257.13:00:35.72#ibcon#enter sib2, iclass 40, count 0 2006.257.13:00:35.72#ibcon#flushed, iclass 40, count 0 2006.257.13:00:35.72#ibcon#about to write, iclass 40, count 0 2006.257.13:00:35.72#ibcon#wrote, iclass 40, count 0 2006.257.13:00:35.72#ibcon#about to read 3, iclass 40, count 0 2006.257.13:00:35.76#ibcon#read 3, iclass 40, count 0 2006.257.13:00:35.76#ibcon#about to read 4, iclass 40, count 0 2006.257.13:00:35.76#ibcon#read 4, iclass 40, count 0 2006.257.13:00:35.76#ibcon#about to read 5, iclass 40, count 0 2006.257.13:00:35.76#ibcon#read 5, iclass 40, count 0 2006.257.13:00:35.76#ibcon#about to read 6, iclass 40, count 0 2006.257.13:00:35.76#ibcon#read 6, iclass 40, count 0 2006.257.13:00:35.76#ibcon#end of sib2, iclass 40, count 0 2006.257.13:00:35.76#ibcon#*after write, iclass 40, count 0 2006.257.13:00:35.76#ibcon#*before return 0, iclass 40, count 0 2006.257.13:00:35.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:35.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:35.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:00:35.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:00:35.76$vck44/va=8,4 2006.257.13:00:35.76#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.13:00:35.76#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.13:00:35.76#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:35.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:00:35.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:00:35.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:00:35.82#ibcon#enter wrdev, iclass 4, count 2 2006.257.13:00:35.82#ibcon#first serial, iclass 4, count 2 2006.257.13:00:35.82#ibcon#enter sib2, iclass 4, count 2 2006.257.13:00:35.82#ibcon#flushed, iclass 4, count 2 2006.257.13:00:35.82#ibcon#about to write, iclass 4, count 2 2006.257.13:00:35.82#ibcon#wrote, iclass 4, count 2 2006.257.13:00:35.82#ibcon#about to read 3, iclass 4, count 2 2006.257.13:00:35.84#ibcon#read 3, iclass 4, count 2 2006.257.13:00:35.84#ibcon#about to read 4, iclass 4, count 2 2006.257.13:00:35.84#ibcon#read 4, iclass 4, count 2 2006.257.13:00:35.84#ibcon#about to read 5, iclass 4, count 2 2006.257.13:00:35.84#ibcon#read 5, iclass 4, count 2 2006.257.13:00:35.84#ibcon#about to read 6, iclass 4, count 2 2006.257.13:00:35.84#ibcon#read 6, iclass 4, count 2 2006.257.13:00:35.84#ibcon#end of sib2, iclass 4, count 2 2006.257.13:00:35.84#ibcon#*mode == 0, iclass 4, count 2 2006.257.13:00:35.84#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.13:00:35.84#ibcon#[25=AT08-04\r\n] 2006.257.13:00:35.84#ibcon#*before write, iclass 4, count 2 2006.257.13:00:35.84#ibcon#enter sib2, iclass 4, count 2 2006.257.13:00:35.84#ibcon#flushed, iclass 4, count 2 2006.257.13:00:35.84#ibcon#about to write, iclass 4, count 2 2006.257.13:00:35.84#ibcon#wrote, iclass 4, count 2 2006.257.13:00:35.84#ibcon#about to read 3, iclass 4, count 2 2006.257.13:00:35.87#ibcon#read 3, iclass 4, count 2 2006.257.13:00:35.87#ibcon#about to read 4, iclass 4, count 2 2006.257.13:00:35.87#ibcon#read 4, iclass 4, count 2 2006.257.13:00:35.87#ibcon#about to read 5, iclass 4, count 2 2006.257.13:00:35.87#ibcon#read 5, iclass 4, count 2 2006.257.13:00:35.87#ibcon#about to read 6, iclass 4, count 2 2006.257.13:00:35.87#ibcon#read 6, iclass 4, count 2 2006.257.13:00:35.87#ibcon#end of sib2, iclass 4, count 2 2006.257.13:00:35.87#ibcon#*after write, iclass 4, count 2 2006.257.13:00:35.87#ibcon#*before return 0, iclass 4, count 2 2006.257.13:00:35.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:00:35.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:00:35.87#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.13:00:35.87#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:35.87#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:00:35.99#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:00:35.99#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:00:35.99#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:00:35.99#ibcon#first serial, iclass 4, count 0 2006.257.13:00:35.99#ibcon#enter sib2, iclass 4, count 0 2006.257.13:00:35.99#ibcon#flushed, iclass 4, count 0 2006.257.13:00:35.99#ibcon#about to write, iclass 4, count 0 2006.257.13:00:35.99#ibcon#wrote, iclass 4, count 0 2006.257.13:00:35.99#ibcon#about to read 3, iclass 4, count 0 2006.257.13:00:36.01#ibcon#read 3, iclass 4, count 0 2006.257.13:00:36.01#ibcon#about to read 4, iclass 4, count 0 2006.257.13:00:36.01#ibcon#read 4, iclass 4, count 0 2006.257.13:00:36.01#ibcon#about to read 5, iclass 4, count 0 2006.257.13:00:36.01#ibcon#read 5, iclass 4, count 0 2006.257.13:00:36.01#ibcon#about to read 6, iclass 4, count 0 2006.257.13:00:36.01#ibcon#read 6, iclass 4, count 0 2006.257.13:00:36.01#ibcon#end of sib2, iclass 4, count 0 2006.257.13:00:36.01#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:00:36.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:00:36.01#ibcon#[25=USB\r\n] 2006.257.13:00:36.01#ibcon#*before write, iclass 4, count 0 2006.257.13:00:36.01#ibcon#enter sib2, iclass 4, count 0 2006.257.13:00:36.01#ibcon#flushed, iclass 4, count 0 2006.257.13:00:36.01#ibcon#about to write, iclass 4, count 0 2006.257.13:00:36.01#ibcon#wrote, iclass 4, count 0 2006.257.13:00:36.01#ibcon#about to read 3, iclass 4, count 0 2006.257.13:00:36.04#ibcon#read 3, iclass 4, count 0 2006.257.13:00:36.04#ibcon#about to read 4, iclass 4, count 0 2006.257.13:00:36.04#ibcon#read 4, iclass 4, count 0 2006.257.13:00:36.04#ibcon#about to read 5, iclass 4, count 0 2006.257.13:00:36.04#ibcon#read 5, iclass 4, count 0 2006.257.13:00:36.04#ibcon#about to read 6, iclass 4, count 0 2006.257.13:00:36.04#ibcon#read 6, iclass 4, count 0 2006.257.13:00:36.04#ibcon#end of sib2, iclass 4, count 0 2006.257.13:00:36.04#ibcon#*after write, iclass 4, count 0 2006.257.13:00:36.04#ibcon#*before return 0, iclass 4, count 0 2006.257.13:00:36.04#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:00:36.04#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:00:36.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:00:36.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:00:36.04$vck44/vblo=1,629.99 2006.257.13:00:36.04#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.13:00:36.04#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.13:00:36.04#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:36.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:00:36.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:00:36.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:00:36.04#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:00:36.04#ibcon#first serial, iclass 6, count 0 2006.257.13:00:36.04#ibcon#enter sib2, iclass 6, count 0 2006.257.13:00:36.04#ibcon#flushed, iclass 6, count 0 2006.257.13:00:36.04#ibcon#about to write, iclass 6, count 0 2006.257.13:00:36.04#ibcon#wrote, iclass 6, count 0 2006.257.13:00:36.04#ibcon#about to read 3, iclass 6, count 0 2006.257.13:00:36.06#ibcon#read 3, iclass 6, count 0 2006.257.13:00:36.06#ibcon#about to read 4, iclass 6, count 0 2006.257.13:00:36.06#ibcon#read 4, iclass 6, count 0 2006.257.13:00:36.06#ibcon#about to read 5, iclass 6, count 0 2006.257.13:00:36.06#ibcon#read 5, iclass 6, count 0 2006.257.13:00:36.06#ibcon#about to read 6, iclass 6, count 0 2006.257.13:00:36.06#ibcon#read 6, iclass 6, count 0 2006.257.13:00:36.06#ibcon#end of sib2, iclass 6, count 0 2006.257.13:00:36.06#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:00:36.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:00:36.06#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:00:36.06#ibcon#*before write, iclass 6, count 0 2006.257.13:00:36.06#ibcon#enter sib2, iclass 6, count 0 2006.257.13:00:36.06#ibcon#flushed, iclass 6, count 0 2006.257.13:00:36.06#ibcon#about to write, iclass 6, count 0 2006.257.13:00:36.06#ibcon#wrote, iclass 6, count 0 2006.257.13:00:36.06#ibcon#about to read 3, iclass 6, count 0 2006.257.13:00:36.10#ibcon#read 3, iclass 6, count 0 2006.257.13:00:36.10#ibcon#about to read 4, iclass 6, count 0 2006.257.13:00:36.10#ibcon#read 4, iclass 6, count 0 2006.257.13:00:36.10#ibcon#about to read 5, iclass 6, count 0 2006.257.13:00:36.10#ibcon#read 5, iclass 6, count 0 2006.257.13:00:36.10#ibcon#about to read 6, iclass 6, count 0 2006.257.13:00:36.10#ibcon#read 6, iclass 6, count 0 2006.257.13:00:36.10#ibcon#end of sib2, iclass 6, count 0 2006.257.13:00:36.10#ibcon#*after write, iclass 6, count 0 2006.257.13:00:36.10#ibcon#*before return 0, iclass 6, count 0 2006.257.13:00:36.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:00:36.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:00:36.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:00:36.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:00:36.10$vck44/vb=1,4 2006.257.13:00:36.10#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.13:00:36.10#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.13:00:36.10#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:36.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:00:36.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:00:36.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:00:36.10#ibcon#enter wrdev, iclass 10, count 2 2006.257.13:00:36.10#ibcon#first serial, iclass 10, count 2 2006.257.13:00:36.10#ibcon#enter sib2, iclass 10, count 2 2006.257.13:00:36.10#ibcon#flushed, iclass 10, count 2 2006.257.13:00:36.10#ibcon#about to write, iclass 10, count 2 2006.257.13:00:36.10#ibcon#wrote, iclass 10, count 2 2006.257.13:00:36.10#ibcon#about to read 3, iclass 10, count 2 2006.257.13:00:36.12#ibcon#read 3, iclass 10, count 2 2006.257.13:00:36.12#ibcon#about to read 4, iclass 10, count 2 2006.257.13:00:36.12#ibcon#read 4, iclass 10, count 2 2006.257.13:00:36.12#ibcon#about to read 5, iclass 10, count 2 2006.257.13:00:36.12#ibcon#read 5, iclass 10, count 2 2006.257.13:00:36.12#ibcon#about to read 6, iclass 10, count 2 2006.257.13:00:36.12#ibcon#read 6, iclass 10, count 2 2006.257.13:00:36.12#ibcon#end of sib2, iclass 10, count 2 2006.257.13:00:36.12#ibcon#*mode == 0, iclass 10, count 2 2006.257.13:00:36.12#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.13:00:36.12#ibcon#[27=AT01-04\r\n] 2006.257.13:00:36.12#ibcon#*before write, iclass 10, count 2 2006.257.13:00:36.12#ibcon#enter sib2, iclass 10, count 2 2006.257.13:00:36.12#ibcon#flushed, iclass 10, count 2 2006.257.13:00:36.12#ibcon#about to write, iclass 10, count 2 2006.257.13:00:36.12#ibcon#wrote, iclass 10, count 2 2006.257.13:00:36.12#ibcon#about to read 3, iclass 10, count 2 2006.257.13:00:36.15#ibcon#read 3, iclass 10, count 2 2006.257.13:00:36.15#ibcon#about to read 4, iclass 10, count 2 2006.257.13:00:36.15#ibcon#read 4, iclass 10, count 2 2006.257.13:00:36.15#ibcon#about to read 5, iclass 10, count 2 2006.257.13:00:36.15#ibcon#read 5, iclass 10, count 2 2006.257.13:00:36.15#ibcon#about to read 6, iclass 10, count 2 2006.257.13:00:36.15#ibcon#read 6, iclass 10, count 2 2006.257.13:00:36.15#ibcon#end of sib2, iclass 10, count 2 2006.257.13:00:36.15#ibcon#*after write, iclass 10, count 2 2006.257.13:00:36.15#ibcon#*before return 0, iclass 10, count 2 2006.257.13:00:36.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:00:36.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:00:36.15#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.13:00:36.15#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:36.15#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:00:36.27#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:00:36.27#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:00:36.27#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:00:36.27#ibcon#first serial, iclass 10, count 0 2006.257.13:00:36.27#ibcon#enter sib2, iclass 10, count 0 2006.257.13:00:36.27#ibcon#flushed, iclass 10, count 0 2006.257.13:00:36.27#ibcon#about to write, iclass 10, count 0 2006.257.13:00:36.27#ibcon#wrote, iclass 10, count 0 2006.257.13:00:36.27#ibcon#about to read 3, iclass 10, count 0 2006.257.13:00:36.29#ibcon#read 3, iclass 10, count 0 2006.257.13:00:36.29#ibcon#about to read 4, iclass 10, count 0 2006.257.13:00:36.29#ibcon#read 4, iclass 10, count 0 2006.257.13:00:36.29#ibcon#about to read 5, iclass 10, count 0 2006.257.13:00:36.29#ibcon#read 5, iclass 10, count 0 2006.257.13:00:36.29#ibcon#about to read 6, iclass 10, count 0 2006.257.13:00:36.29#ibcon#read 6, iclass 10, count 0 2006.257.13:00:36.29#ibcon#end of sib2, iclass 10, count 0 2006.257.13:00:36.29#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:00:36.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:00:36.29#ibcon#[27=USB\r\n] 2006.257.13:00:36.29#ibcon#*before write, iclass 10, count 0 2006.257.13:00:36.29#ibcon#enter sib2, iclass 10, count 0 2006.257.13:00:36.29#ibcon#flushed, iclass 10, count 0 2006.257.13:00:36.29#ibcon#about to write, iclass 10, count 0 2006.257.13:00:36.29#ibcon#wrote, iclass 10, count 0 2006.257.13:00:36.29#ibcon#about to read 3, iclass 10, count 0 2006.257.13:00:36.32#ibcon#read 3, iclass 10, count 0 2006.257.13:00:36.32#ibcon#about to read 4, iclass 10, count 0 2006.257.13:00:36.32#ibcon#read 4, iclass 10, count 0 2006.257.13:00:36.32#ibcon#about to read 5, iclass 10, count 0 2006.257.13:00:36.32#ibcon#read 5, iclass 10, count 0 2006.257.13:00:36.32#ibcon#about to read 6, iclass 10, count 0 2006.257.13:00:36.32#ibcon#read 6, iclass 10, count 0 2006.257.13:00:36.32#ibcon#end of sib2, iclass 10, count 0 2006.257.13:00:36.32#ibcon#*after write, iclass 10, count 0 2006.257.13:00:36.32#ibcon#*before return 0, iclass 10, count 0 2006.257.13:00:36.32#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:00:36.32#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:00:36.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:00:36.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:00:36.32$vck44/vblo=2,634.99 2006.257.13:00:36.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.13:00:36.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.13:00:36.32#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:36.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:36.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:36.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:36.32#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:00:36.32#ibcon#first serial, iclass 12, count 0 2006.257.13:00:36.32#ibcon#enter sib2, iclass 12, count 0 2006.257.13:00:36.32#ibcon#flushed, iclass 12, count 0 2006.257.13:00:36.32#ibcon#about to write, iclass 12, count 0 2006.257.13:00:36.32#ibcon#wrote, iclass 12, count 0 2006.257.13:00:36.32#ibcon#about to read 3, iclass 12, count 0 2006.257.13:00:36.34#ibcon#read 3, iclass 12, count 0 2006.257.13:00:36.34#ibcon#about to read 4, iclass 12, count 0 2006.257.13:00:36.34#ibcon#read 4, iclass 12, count 0 2006.257.13:00:36.34#ibcon#about to read 5, iclass 12, count 0 2006.257.13:00:36.34#ibcon#read 5, iclass 12, count 0 2006.257.13:00:36.34#ibcon#about to read 6, iclass 12, count 0 2006.257.13:00:36.34#ibcon#read 6, iclass 12, count 0 2006.257.13:00:36.34#ibcon#end of sib2, iclass 12, count 0 2006.257.13:00:36.34#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:00:36.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:00:36.34#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:00:36.34#ibcon#*before write, iclass 12, count 0 2006.257.13:00:36.34#ibcon#enter sib2, iclass 12, count 0 2006.257.13:00:36.34#ibcon#flushed, iclass 12, count 0 2006.257.13:00:36.34#ibcon#about to write, iclass 12, count 0 2006.257.13:00:36.34#ibcon#wrote, iclass 12, count 0 2006.257.13:00:36.34#ibcon#about to read 3, iclass 12, count 0 2006.257.13:00:36.38#ibcon#read 3, iclass 12, count 0 2006.257.13:00:36.38#ibcon#about to read 4, iclass 12, count 0 2006.257.13:00:36.38#ibcon#read 4, iclass 12, count 0 2006.257.13:00:36.38#ibcon#about to read 5, iclass 12, count 0 2006.257.13:00:36.38#ibcon#read 5, iclass 12, count 0 2006.257.13:00:36.38#ibcon#about to read 6, iclass 12, count 0 2006.257.13:00:36.38#ibcon#read 6, iclass 12, count 0 2006.257.13:00:36.38#ibcon#end of sib2, iclass 12, count 0 2006.257.13:00:36.38#ibcon#*after write, iclass 12, count 0 2006.257.13:00:36.38#ibcon#*before return 0, iclass 12, count 0 2006.257.13:00:36.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:36.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:00:36.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:00:36.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:00:36.38$vck44/vb=2,5 2006.257.13:00:36.38#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.13:00:36.38#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.13:00:36.38#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:36.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:36.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:36.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:36.44#ibcon#enter wrdev, iclass 14, count 2 2006.257.13:00:36.44#ibcon#first serial, iclass 14, count 2 2006.257.13:00:36.44#ibcon#enter sib2, iclass 14, count 2 2006.257.13:00:36.44#ibcon#flushed, iclass 14, count 2 2006.257.13:00:36.44#ibcon#about to write, iclass 14, count 2 2006.257.13:00:36.44#ibcon#wrote, iclass 14, count 2 2006.257.13:00:36.44#ibcon#about to read 3, iclass 14, count 2 2006.257.13:00:36.46#ibcon#read 3, iclass 14, count 2 2006.257.13:00:36.46#ibcon#about to read 4, iclass 14, count 2 2006.257.13:00:36.46#ibcon#read 4, iclass 14, count 2 2006.257.13:00:36.46#ibcon#about to read 5, iclass 14, count 2 2006.257.13:00:36.46#ibcon#read 5, iclass 14, count 2 2006.257.13:00:36.46#ibcon#about to read 6, iclass 14, count 2 2006.257.13:00:36.46#ibcon#read 6, iclass 14, count 2 2006.257.13:00:36.46#ibcon#end of sib2, iclass 14, count 2 2006.257.13:00:36.46#ibcon#*mode == 0, iclass 14, count 2 2006.257.13:00:36.46#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.13:00:36.46#ibcon#[27=AT02-05\r\n] 2006.257.13:00:36.46#ibcon#*before write, iclass 14, count 2 2006.257.13:00:36.46#ibcon#enter sib2, iclass 14, count 2 2006.257.13:00:36.46#ibcon#flushed, iclass 14, count 2 2006.257.13:00:36.46#ibcon#about to write, iclass 14, count 2 2006.257.13:00:36.46#ibcon#wrote, iclass 14, count 2 2006.257.13:00:36.46#ibcon#about to read 3, iclass 14, count 2 2006.257.13:00:36.49#ibcon#read 3, iclass 14, count 2 2006.257.13:00:36.49#ibcon#about to read 4, iclass 14, count 2 2006.257.13:00:36.56#ibcon#read 4, iclass 14, count 2 2006.257.13:00:36.56#ibcon#about to read 5, iclass 14, count 2 2006.257.13:00:36.56#ibcon#read 5, iclass 14, count 2 2006.257.13:00:36.56#ibcon#about to read 6, iclass 14, count 2 2006.257.13:00:36.56#ibcon#read 6, iclass 14, count 2 2006.257.13:00:36.56#ibcon#end of sib2, iclass 14, count 2 2006.257.13:00:36.56#ibcon#*after write, iclass 14, count 2 2006.257.13:00:36.56#ibcon#*before return 0, iclass 14, count 2 2006.257.13:00:36.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:36.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:00:36.56#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.13:00:36.56#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:36.56#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:36.68#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:36.68#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:36.68#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:00:36.68#ibcon#first serial, iclass 14, count 0 2006.257.13:00:36.68#ibcon#enter sib2, iclass 14, count 0 2006.257.13:00:36.68#ibcon#flushed, iclass 14, count 0 2006.257.13:00:36.68#ibcon#about to write, iclass 14, count 0 2006.257.13:00:36.68#ibcon#wrote, iclass 14, count 0 2006.257.13:00:36.68#ibcon#about to read 3, iclass 14, count 0 2006.257.13:00:36.70#ibcon#read 3, iclass 14, count 0 2006.257.13:00:36.70#ibcon#about to read 4, iclass 14, count 0 2006.257.13:00:36.70#ibcon#read 4, iclass 14, count 0 2006.257.13:00:36.70#ibcon#about to read 5, iclass 14, count 0 2006.257.13:00:36.70#ibcon#read 5, iclass 14, count 0 2006.257.13:00:36.70#ibcon#about to read 6, iclass 14, count 0 2006.257.13:00:36.70#ibcon#read 6, iclass 14, count 0 2006.257.13:00:36.70#ibcon#end of sib2, iclass 14, count 0 2006.257.13:00:36.70#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:00:36.70#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:00:36.70#ibcon#[27=USB\r\n] 2006.257.13:00:36.70#ibcon#*before write, iclass 14, count 0 2006.257.13:00:36.70#ibcon#enter sib2, iclass 14, count 0 2006.257.13:00:36.70#ibcon#flushed, iclass 14, count 0 2006.257.13:00:36.70#ibcon#about to write, iclass 14, count 0 2006.257.13:00:36.70#ibcon#wrote, iclass 14, count 0 2006.257.13:00:36.70#ibcon#about to read 3, iclass 14, count 0 2006.257.13:00:36.73#ibcon#read 3, iclass 14, count 0 2006.257.13:00:36.73#ibcon#about to read 4, iclass 14, count 0 2006.257.13:00:36.73#ibcon#read 4, iclass 14, count 0 2006.257.13:00:36.73#ibcon#about to read 5, iclass 14, count 0 2006.257.13:00:36.73#ibcon#read 5, iclass 14, count 0 2006.257.13:00:36.73#ibcon#about to read 6, iclass 14, count 0 2006.257.13:00:36.73#ibcon#read 6, iclass 14, count 0 2006.257.13:00:36.73#ibcon#end of sib2, iclass 14, count 0 2006.257.13:00:36.73#ibcon#*after write, iclass 14, count 0 2006.257.13:00:36.73#ibcon#*before return 0, iclass 14, count 0 2006.257.13:00:36.73#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:36.73#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:00:36.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:00:36.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:00:36.73$vck44/vblo=3,649.99 2006.257.13:00:36.73#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.13:00:36.73#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.13:00:36.73#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:36.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:36.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:36.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:36.73#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:00:36.73#ibcon#first serial, iclass 16, count 0 2006.257.13:00:36.73#ibcon#enter sib2, iclass 16, count 0 2006.257.13:00:36.73#ibcon#flushed, iclass 16, count 0 2006.257.13:00:36.73#ibcon#about to write, iclass 16, count 0 2006.257.13:00:36.73#ibcon#wrote, iclass 16, count 0 2006.257.13:00:36.73#ibcon#about to read 3, iclass 16, count 0 2006.257.13:00:36.75#ibcon#read 3, iclass 16, count 0 2006.257.13:00:36.75#ibcon#about to read 4, iclass 16, count 0 2006.257.13:00:36.75#ibcon#read 4, iclass 16, count 0 2006.257.13:00:36.75#ibcon#about to read 5, iclass 16, count 0 2006.257.13:00:36.75#ibcon#read 5, iclass 16, count 0 2006.257.13:00:36.75#ibcon#about to read 6, iclass 16, count 0 2006.257.13:00:36.75#ibcon#read 6, iclass 16, count 0 2006.257.13:00:36.75#ibcon#end of sib2, iclass 16, count 0 2006.257.13:00:36.75#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:00:36.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:00:36.75#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:00:36.75#ibcon#*before write, iclass 16, count 0 2006.257.13:00:36.75#ibcon#enter sib2, iclass 16, count 0 2006.257.13:00:36.75#ibcon#flushed, iclass 16, count 0 2006.257.13:00:36.75#ibcon#about to write, iclass 16, count 0 2006.257.13:00:36.75#ibcon#wrote, iclass 16, count 0 2006.257.13:00:36.75#ibcon#about to read 3, iclass 16, count 0 2006.257.13:00:36.79#ibcon#read 3, iclass 16, count 0 2006.257.13:00:36.79#ibcon#about to read 4, iclass 16, count 0 2006.257.13:00:36.79#ibcon#read 4, iclass 16, count 0 2006.257.13:00:36.79#ibcon#about to read 5, iclass 16, count 0 2006.257.13:00:36.79#ibcon#read 5, iclass 16, count 0 2006.257.13:00:36.79#ibcon#about to read 6, iclass 16, count 0 2006.257.13:00:36.79#ibcon#read 6, iclass 16, count 0 2006.257.13:00:36.79#ibcon#end of sib2, iclass 16, count 0 2006.257.13:00:36.79#ibcon#*after write, iclass 16, count 0 2006.257.13:00:36.79#ibcon#*before return 0, iclass 16, count 0 2006.257.13:00:36.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:36.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:00:36.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:00:36.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:00:36.79$vck44/vb=3,4 2006.257.13:00:36.79#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.13:00:36.79#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.13:00:36.79#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:36.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:36.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:36.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:36.85#ibcon#enter wrdev, iclass 18, count 2 2006.257.13:00:36.85#ibcon#first serial, iclass 18, count 2 2006.257.13:00:36.85#ibcon#enter sib2, iclass 18, count 2 2006.257.13:00:36.85#ibcon#flushed, iclass 18, count 2 2006.257.13:00:36.85#ibcon#about to write, iclass 18, count 2 2006.257.13:00:36.85#ibcon#wrote, iclass 18, count 2 2006.257.13:00:36.85#ibcon#about to read 3, iclass 18, count 2 2006.257.13:00:36.87#ibcon#read 3, iclass 18, count 2 2006.257.13:00:36.87#ibcon#about to read 4, iclass 18, count 2 2006.257.13:00:36.87#ibcon#read 4, iclass 18, count 2 2006.257.13:00:36.87#ibcon#about to read 5, iclass 18, count 2 2006.257.13:00:36.87#ibcon#read 5, iclass 18, count 2 2006.257.13:00:36.87#ibcon#about to read 6, iclass 18, count 2 2006.257.13:00:36.87#ibcon#read 6, iclass 18, count 2 2006.257.13:00:36.87#ibcon#end of sib2, iclass 18, count 2 2006.257.13:00:36.87#ibcon#*mode == 0, iclass 18, count 2 2006.257.13:00:36.87#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.13:00:36.87#ibcon#[27=AT03-04\r\n] 2006.257.13:00:36.87#ibcon#*before write, iclass 18, count 2 2006.257.13:00:36.87#ibcon#enter sib2, iclass 18, count 2 2006.257.13:00:36.87#ibcon#flushed, iclass 18, count 2 2006.257.13:00:36.87#ibcon#about to write, iclass 18, count 2 2006.257.13:00:36.87#ibcon#wrote, iclass 18, count 2 2006.257.13:00:36.87#ibcon#about to read 3, iclass 18, count 2 2006.257.13:00:36.90#ibcon#read 3, iclass 18, count 2 2006.257.13:00:36.90#ibcon#about to read 4, iclass 18, count 2 2006.257.13:00:36.90#ibcon#read 4, iclass 18, count 2 2006.257.13:00:36.90#ibcon#about to read 5, iclass 18, count 2 2006.257.13:00:36.90#ibcon#read 5, iclass 18, count 2 2006.257.13:00:36.90#ibcon#about to read 6, iclass 18, count 2 2006.257.13:00:36.90#ibcon#read 6, iclass 18, count 2 2006.257.13:00:36.90#ibcon#end of sib2, iclass 18, count 2 2006.257.13:00:36.90#ibcon#*after write, iclass 18, count 2 2006.257.13:00:36.90#ibcon#*before return 0, iclass 18, count 2 2006.257.13:00:36.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:36.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:00:36.90#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.13:00:36.90#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:36.90#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:37.02#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:37.02#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:37.02#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:00:37.02#ibcon#first serial, iclass 18, count 0 2006.257.13:00:37.02#ibcon#enter sib2, iclass 18, count 0 2006.257.13:00:37.02#ibcon#flushed, iclass 18, count 0 2006.257.13:00:37.02#ibcon#about to write, iclass 18, count 0 2006.257.13:00:37.02#ibcon#wrote, iclass 18, count 0 2006.257.13:00:37.02#ibcon#about to read 3, iclass 18, count 0 2006.257.13:00:37.04#ibcon#read 3, iclass 18, count 0 2006.257.13:00:37.04#ibcon#about to read 4, iclass 18, count 0 2006.257.13:00:37.04#ibcon#read 4, iclass 18, count 0 2006.257.13:00:37.04#ibcon#about to read 5, iclass 18, count 0 2006.257.13:00:37.04#ibcon#read 5, iclass 18, count 0 2006.257.13:00:37.04#ibcon#about to read 6, iclass 18, count 0 2006.257.13:00:37.04#ibcon#read 6, iclass 18, count 0 2006.257.13:00:37.04#ibcon#end of sib2, iclass 18, count 0 2006.257.13:00:37.04#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:00:37.04#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:00:37.04#ibcon#[27=USB\r\n] 2006.257.13:00:37.04#ibcon#*before write, iclass 18, count 0 2006.257.13:00:37.04#ibcon#enter sib2, iclass 18, count 0 2006.257.13:00:37.04#ibcon#flushed, iclass 18, count 0 2006.257.13:00:37.04#ibcon#about to write, iclass 18, count 0 2006.257.13:00:37.04#ibcon#wrote, iclass 18, count 0 2006.257.13:00:37.04#ibcon#about to read 3, iclass 18, count 0 2006.257.13:00:37.07#ibcon#read 3, iclass 18, count 0 2006.257.13:00:37.07#ibcon#about to read 4, iclass 18, count 0 2006.257.13:00:37.07#ibcon#read 4, iclass 18, count 0 2006.257.13:00:37.07#ibcon#about to read 5, iclass 18, count 0 2006.257.13:00:37.07#ibcon#read 5, iclass 18, count 0 2006.257.13:00:37.07#ibcon#about to read 6, iclass 18, count 0 2006.257.13:00:37.07#ibcon#read 6, iclass 18, count 0 2006.257.13:00:37.07#ibcon#end of sib2, iclass 18, count 0 2006.257.13:00:37.07#ibcon#*after write, iclass 18, count 0 2006.257.13:00:37.07#ibcon#*before return 0, iclass 18, count 0 2006.257.13:00:37.07#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:37.07#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:00:37.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:00:37.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:00:37.07$vck44/vblo=4,679.99 2006.257.13:00:37.07#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.13:00:37.07#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.13:00:37.07#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:37.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:37.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:37.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:37.07#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:00:37.07#ibcon#first serial, iclass 20, count 0 2006.257.13:00:37.07#ibcon#enter sib2, iclass 20, count 0 2006.257.13:00:37.07#ibcon#flushed, iclass 20, count 0 2006.257.13:00:37.07#ibcon#about to write, iclass 20, count 0 2006.257.13:00:37.07#ibcon#wrote, iclass 20, count 0 2006.257.13:00:37.07#ibcon#about to read 3, iclass 20, count 0 2006.257.13:00:37.09#ibcon#read 3, iclass 20, count 0 2006.257.13:00:37.09#ibcon#about to read 4, iclass 20, count 0 2006.257.13:00:37.09#ibcon#read 4, iclass 20, count 0 2006.257.13:00:37.09#ibcon#about to read 5, iclass 20, count 0 2006.257.13:00:37.09#ibcon#read 5, iclass 20, count 0 2006.257.13:00:37.09#ibcon#about to read 6, iclass 20, count 0 2006.257.13:00:37.09#ibcon#read 6, iclass 20, count 0 2006.257.13:00:37.09#ibcon#end of sib2, iclass 20, count 0 2006.257.13:00:37.09#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:00:37.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:00:37.09#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:00:37.09#ibcon#*before write, iclass 20, count 0 2006.257.13:00:37.09#ibcon#enter sib2, iclass 20, count 0 2006.257.13:00:37.09#ibcon#flushed, iclass 20, count 0 2006.257.13:00:37.09#ibcon#about to write, iclass 20, count 0 2006.257.13:00:37.09#ibcon#wrote, iclass 20, count 0 2006.257.13:00:37.09#ibcon#about to read 3, iclass 20, count 0 2006.257.13:00:37.13#ibcon#read 3, iclass 20, count 0 2006.257.13:00:37.13#ibcon#about to read 4, iclass 20, count 0 2006.257.13:00:37.13#ibcon#read 4, iclass 20, count 0 2006.257.13:00:37.13#ibcon#about to read 5, iclass 20, count 0 2006.257.13:00:37.13#ibcon#read 5, iclass 20, count 0 2006.257.13:00:37.13#ibcon#about to read 6, iclass 20, count 0 2006.257.13:00:37.13#ibcon#read 6, iclass 20, count 0 2006.257.13:00:37.13#ibcon#end of sib2, iclass 20, count 0 2006.257.13:00:37.13#ibcon#*after write, iclass 20, count 0 2006.257.13:00:37.13#ibcon#*before return 0, iclass 20, count 0 2006.257.13:00:37.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:37.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:00:37.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:00:37.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:00:37.13$vck44/vb=4,5 2006.257.13:00:37.13#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.13:00:37.13#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.13:00:37.13#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:37.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:37.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:37.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:37.19#ibcon#enter wrdev, iclass 22, count 2 2006.257.13:00:37.19#ibcon#first serial, iclass 22, count 2 2006.257.13:00:37.19#ibcon#enter sib2, iclass 22, count 2 2006.257.13:00:37.19#ibcon#flushed, iclass 22, count 2 2006.257.13:00:37.19#ibcon#about to write, iclass 22, count 2 2006.257.13:00:37.19#ibcon#wrote, iclass 22, count 2 2006.257.13:00:37.19#ibcon#about to read 3, iclass 22, count 2 2006.257.13:00:37.21#ibcon#read 3, iclass 22, count 2 2006.257.13:00:37.21#ibcon#about to read 4, iclass 22, count 2 2006.257.13:00:37.21#ibcon#read 4, iclass 22, count 2 2006.257.13:00:37.21#ibcon#about to read 5, iclass 22, count 2 2006.257.13:00:37.21#ibcon#read 5, iclass 22, count 2 2006.257.13:00:37.21#ibcon#about to read 6, iclass 22, count 2 2006.257.13:00:37.21#ibcon#read 6, iclass 22, count 2 2006.257.13:00:37.21#ibcon#end of sib2, iclass 22, count 2 2006.257.13:00:37.21#ibcon#*mode == 0, iclass 22, count 2 2006.257.13:00:37.21#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.13:00:37.21#ibcon#[27=AT04-05\r\n] 2006.257.13:00:37.21#ibcon#*before write, iclass 22, count 2 2006.257.13:00:37.21#ibcon#enter sib2, iclass 22, count 2 2006.257.13:00:37.21#ibcon#flushed, iclass 22, count 2 2006.257.13:00:37.21#ibcon#about to write, iclass 22, count 2 2006.257.13:00:37.21#ibcon#wrote, iclass 22, count 2 2006.257.13:00:37.21#ibcon#about to read 3, iclass 22, count 2 2006.257.13:00:37.24#ibcon#read 3, iclass 22, count 2 2006.257.13:00:37.24#ibcon#about to read 4, iclass 22, count 2 2006.257.13:00:37.24#ibcon#read 4, iclass 22, count 2 2006.257.13:00:37.24#ibcon#about to read 5, iclass 22, count 2 2006.257.13:00:37.24#ibcon#read 5, iclass 22, count 2 2006.257.13:00:37.24#ibcon#about to read 6, iclass 22, count 2 2006.257.13:00:37.24#ibcon#read 6, iclass 22, count 2 2006.257.13:00:37.24#ibcon#end of sib2, iclass 22, count 2 2006.257.13:00:37.24#ibcon#*after write, iclass 22, count 2 2006.257.13:00:37.24#ibcon#*before return 0, iclass 22, count 2 2006.257.13:00:37.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:37.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:00:37.24#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.13:00:37.24#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:37.24#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:37.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:37.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:37.36#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:00:37.36#ibcon#first serial, iclass 22, count 0 2006.257.13:00:37.36#ibcon#enter sib2, iclass 22, count 0 2006.257.13:00:37.36#ibcon#flushed, iclass 22, count 0 2006.257.13:00:37.36#ibcon#about to write, iclass 22, count 0 2006.257.13:00:37.36#ibcon#wrote, iclass 22, count 0 2006.257.13:00:37.36#ibcon#about to read 3, iclass 22, count 0 2006.257.13:00:37.38#ibcon#read 3, iclass 22, count 0 2006.257.13:00:37.38#ibcon#about to read 4, iclass 22, count 0 2006.257.13:00:37.38#ibcon#read 4, iclass 22, count 0 2006.257.13:00:37.38#ibcon#about to read 5, iclass 22, count 0 2006.257.13:00:37.38#ibcon#read 5, iclass 22, count 0 2006.257.13:00:37.38#ibcon#about to read 6, iclass 22, count 0 2006.257.13:00:37.38#ibcon#read 6, iclass 22, count 0 2006.257.13:00:37.38#ibcon#end of sib2, iclass 22, count 0 2006.257.13:00:37.38#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:00:37.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:00:37.38#ibcon#[27=USB\r\n] 2006.257.13:00:37.38#ibcon#*before write, iclass 22, count 0 2006.257.13:00:37.38#ibcon#enter sib2, iclass 22, count 0 2006.257.13:00:37.38#ibcon#flushed, iclass 22, count 0 2006.257.13:00:37.38#ibcon#about to write, iclass 22, count 0 2006.257.13:00:37.38#ibcon#wrote, iclass 22, count 0 2006.257.13:00:37.38#ibcon#about to read 3, iclass 22, count 0 2006.257.13:00:37.41#ibcon#read 3, iclass 22, count 0 2006.257.13:00:37.41#ibcon#about to read 4, iclass 22, count 0 2006.257.13:00:37.41#ibcon#read 4, iclass 22, count 0 2006.257.13:00:37.41#ibcon#about to read 5, iclass 22, count 0 2006.257.13:00:37.41#ibcon#read 5, iclass 22, count 0 2006.257.13:00:37.41#ibcon#about to read 6, iclass 22, count 0 2006.257.13:00:37.41#ibcon#read 6, iclass 22, count 0 2006.257.13:00:37.41#ibcon#end of sib2, iclass 22, count 0 2006.257.13:00:37.41#ibcon#*after write, iclass 22, count 0 2006.257.13:00:37.41#ibcon#*before return 0, iclass 22, count 0 2006.257.13:00:37.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:37.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:00:37.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:00:37.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:00:37.41$vck44/vblo=5,709.99 2006.257.13:00:37.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.13:00:37.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.13:00:37.41#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:37.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:37.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:37.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:37.41#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:00:37.41#ibcon#first serial, iclass 24, count 0 2006.257.13:00:37.41#ibcon#enter sib2, iclass 24, count 0 2006.257.13:00:37.41#ibcon#flushed, iclass 24, count 0 2006.257.13:00:37.41#ibcon#about to write, iclass 24, count 0 2006.257.13:00:37.41#ibcon#wrote, iclass 24, count 0 2006.257.13:00:37.41#ibcon#about to read 3, iclass 24, count 0 2006.257.13:00:37.43#ibcon#read 3, iclass 24, count 0 2006.257.13:00:37.43#ibcon#about to read 4, iclass 24, count 0 2006.257.13:00:37.43#ibcon#read 4, iclass 24, count 0 2006.257.13:00:37.43#ibcon#about to read 5, iclass 24, count 0 2006.257.13:00:37.43#ibcon#read 5, iclass 24, count 0 2006.257.13:00:37.43#ibcon#about to read 6, iclass 24, count 0 2006.257.13:00:37.43#ibcon#read 6, iclass 24, count 0 2006.257.13:00:37.43#ibcon#end of sib2, iclass 24, count 0 2006.257.13:00:37.43#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:00:37.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:00:37.43#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:00:37.43#ibcon#*before write, iclass 24, count 0 2006.257.13:00:37.43#ibcon#enter sib2, iclass 24, count 0 2006.257.13:00:37.43#ibcon#flushed, iclass 24, count 0 2006.257.13:00:37.43#ibcon#about to write, iclass 24, count 0 2006.257.13:00:37.43#ibcon#wrote, iclass 24, count 0 2006.257.13:00:37.43#ibcon#about to read 3, iclass 24, count 0 2006.257.13:00:37.47#ibcon#read 3, iclass 24, count 0 2006.257.13:00:37.47#ibcon#about to read 4, iclass 24, count 0 2006.257.13:00:37.47#ibcon#read 4, iclass 24, count 0 2006.257.13:00:37.47#ibcon#about to read 5, iclass 24, count 0 2006.257.13:00:37.47#ibcon#read 5, iclass 24, count 0 2006.257.13:00:37.47#ibcon#about to read 6, iclass 24, count 0 2006.257.13:00:37.47#ibcon#read 6, iclass 24, count 0 2006.257.13:00:37.47#ibcon#end of sib2, iclass 24, count 0 2006.257.13:00:37.47#ibcon#*after write, iclass 24, count 0 2006.257.13:00:37.47#ibcon#*before return 0, iclass 24, count 0 2006.257.13:00:37.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:37.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:00:37.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:00:37.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:00:37.47$vck44/vb=5,4 2006.257.13:00:37.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.13:00:37.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.13:00:37.47#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:37.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:37.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:37.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:37.53#ibcon#enter wrdev, iclass 26, count 2 2006.257.13:00:37.53#ibcon#first serial, iclass 26, count 2 2006.257.13:00:37.53#ibcon#enter sib2, iclass 26, count 2 2006.257.13:00:37.53#ibcon#flushed, iclass 26, count 2 2006.257.13:00:37.53#ibcon#about to write, iclass 26, count 2 2006.257.13:00:37.53#ibcon#wrote, iclass 26, count 2 2006.257.13:00:37.53#ibcon#about to read 3, iclass 26, count 2 2006.257.13:00:37.55#ibcon#read 3, iclass 26, count 2 2006.257.13:00:37.55#ibcon#about to read 4, iclass 26, count 2 2006.257.13:00:37.55#ibcon#read 4, iclass 26, count 2 2006.257.13:00:37.55#ibcon#about to read 5, iclass 26, count 2 2006.257.13:00:37.55#ibcon#read 5, iclass 26, count 2 2006.257.13:00:37.55#ibcon#about to read 6, iclass 26, count 2 2006.257.13:00:37.55#ibcon#read 6, iclass 26, count 2 2006.257.13:00:37.55#ibcon#end of sib2, iclass 26, count 2 2006.257.13:00:37.55#ibcon#*mode == 0, iclass 26, count 2 2006.257.13:00:37.55#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.13:00:37.55#ibcon#[27=AT05-04\r\n] 2006.257.13:00:37.55#ibcon#*before write, iclass 26, count 2 2006.257.13:00:37.55#ibcon#enter sib2, iclass 26, count 2 2006.257.13:00:37.55#ibcon#flushed, iclass 26, count 2 2006.257.13:00:37.55#ibcon#about to write, iclass 26, count 2 2006.257.13:00:37.55#ibcon#wrote, iclass 26, count 2 2006.257.13:00:37.55#ibcon#about to read 3, iclass 26, count 2 2006.257.13:00:37.58#ibcon#read 3, iclass 26, count 2 2006.257.13:00:37.58#ibcon#about to read 4, iclass 26, count 2 2006.257.13:00:37.58#ibcon#read 4, iclass 26, count 2 2006.257.13:00:37.58#ibcon#about to read 5, iclass 26, count 2 2006.257.13:00:37.58#ibcon#read 5, iclass 26, count 2 2006.257.13:00:37.58#ibcon#about to read 6, iclass 26, count 2 2006.257.13:00:37.58#ibcon#read 6, iclass 26, count 2 2006.257.13:00:37.58#ibcon#end of sib2, iclass 26, count 2 2006.257.13:00:37.58#ibcon#*after write, iclass 26, count 2 2006.257.13:00:37.58#ibcon#*before return 0, iclass 26, count 2 2006.257.13:00:37.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:37.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:00:37.58#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.13:00:37.58#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:37.58#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:37.70#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:37.70#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:37.70#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:00:37.70#ibcon#first serial, iclass 26, count 0 2006.257.13:00:37.70#ibcon#enter sib2, iclass 26, count 0 2006.257.13:00:37.70#ibcon#flushed, iclass 26, count 0 2006.257.13:00:37.70#ibcon#about to write, iclass 26, count 0 2006.257.13:00:37.70#ibcon#wrote, iclass 26, count 0 2006.257.13:00:37.70#ibcon#about to read 3, iclass 26, count 0 2006.257.13:00:37.72#ibcon#read 3, iclass 26, count 0 2006.257.13:00:37.72#ibcon#about to read 4, iclass 26, count 0 2006.257.13:00:37.72#ibcon#read 4, iclass 26, count 0 2006.257.13:00:37.72#ibcon#about to read 5, iclass 26, count 0 2006.257.13:00:37.72#ibcon#read 5, iclass 26, count 0 2006.257.13:00:37.72#ibcon#about to read 6, iclass 26, count 0 2006.257.13:00:37.72#ibcon#read 6, iclass 26, count 0 2006.257.13:00:37.72#ibcon#end of sib2, iclass 26, count 0 2006.257.13:00:37.72#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:00:37.72#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:00:37.72#ibcon#[27=USB\r\n] 2006.257.13:00:37.72#ibcon#*before write, iclass 26, count 0 2006.257.13:00:37.72#ibcon#enter sib2, iclass 26, count 0 2006.257.13:00:37.72#ibcon#flushed, iclass 26, count 0 2006.257.13:00:37.72#ibcon#about to write, iclass 26, count 0 2006.257.13:00:37.72#ibcon#wrote, iclass 26, count 0 2006.257.13:00:37.72#ibcon#about to read 3, iclass 26, count 0 2006.257.13:00:37.75#ibcon#read 3, iclass 26, count 0 2006.257.13:00:37.75#ibcon#about to read 4, iclass 26, count 0 2006.257.13:00:37.75#ibcon#read 4, iclass 26, count 0 2006.257.13:00:37.75#ibcon#about to read 5, iclass 26, count 0 2006.257.13:00:37.75#ibcon#read 5, iclass 26, count 0 2006.257.13:00:37.75#ibcon#about to read 6, iclass 26, count 0 2006.257.13:00:37.75#ibcon#read 6, iclass 26, count 0 2006.257.13:00:37.75#ibcon#end of sib2, iclass 26, count 0 2006.257.13:00:37.75#ibcon#*after write, iclass 26, count 0 2006.257.13:00:37.75#ibcon#*before return 0, iclass 26, count 0 2006.257.13:00:37.75#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:37.75#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:00:37.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:00:37.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:00:37.75$vck44/vblo=6,719.99 2006.257.13:00:37.75#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.13:00:37.75#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.13:00:37.75#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:37.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:37.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:37.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:37.75#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:00:37.75#ibcon#first serial, iclass 28, count 0 2006.257.13:00:37.75#ibcon#enter sib2, iclass 28, count 0 2006.257.13:00:37.75#ibcon#flushed, iclass 28, count 0 2006.257.13:00:37.75#ibcon#about to write, iclass 28, count 0 2006.257.13:00:37.75#ibcon#wrote, iclass 28, count 0 2006.257.13:00:37.75#ibcon#about to read 3, iclass 28, count 0 2006.257.13:00:37.77#ibcon#read 3, iclass 28, count 0 2006.257.13:00:37.77#ibcon#about to read 4, iclass 28, count 0 2006.257.13:00:37.77#ibcon#read 4, iclass 28, count 0 2006.257.13:00:37.77#ibcon#about to read 5, iclass 28, count 0 2006.257.13:00:37.77#ibcon#read 5, iclass 28, count 0 2006.257.13:00:37.77#ibcon#about to read 6, iclass 28, count 0 2006.257.13:00:37.77#ibcon#read 6, iclass 28, count 0 2006.257.13:00:37.77#ibcon#end of sib2, iclass 28, count 0 2006.257.13:00:37.77#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:00:37.77#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:00:37.77#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:00:37.77#ibcon#*before write, iclass 28, count 0 2006.257.13:00:37.77#ibcon#enter sib2, iclass 28, count 0 2006.257.13:00:37.77#ibcon#flushed, iclass 28, count 0 2006.257.13:00:37.77#ibcon#about to write, iclass 28, count 0 2006.257.13:00:37.77#ibcon#wrote, iclass 28, count 0 2006.257.13:00:37.77#ibcon#about to read 3, iclass 28, count 0 2006.257.13:00:37.81#ibcon#read 3, iclass 28, count 0 2006.257.13:00:37.81#ibcon#about to read 4, iclass 28, count 0 2006.257.13:00:37.81#ibcon#read 4, iclass 28, count 0 2006.257.13:00:37.81#ibcon#about to read 5, iclass 28, count 0 2006.257.13:00:37.81#ibcon#read 5, iclass 28, count 0 2006.257.13:00:37.81#ibcon#about to read 6, iclass 28, count 0 2006.257.13:00:37.81#ibcon#read 6, iclass 28, count 0 2006.257.13:00:37.81#ibcon#end of sib2, iclass 28, count 0 2006.257.13:00:37.81#ibcon#*after write, iclass 28, count 0 2006.257.13:00:37.81#ibcon#*before return 0, iclass 28, count 0 2006.257.13:00:37.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:37.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:00:37.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:00:37.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:00:37.81$vck44/vb=6,4 2006.257.13:00:37.81#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.13:00:37.81#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.13:00:37.81#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:37.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:37.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:37.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:37.87#ibcon#enter wrdev, iclass 30, count 2 2006.257.13:00:37.87#ibcon#first serial, iclass 30, count 2 2006.257.13:00:37.87#ibcon#enter sib2, iclass 30, count 2 2006.257.13:00:37.87#ibcon#flushed, iclass 30, count 2 2006.257.13:00:37.87#ibcon#about to write, iclass 30, count 2 2006.257.13:00:37.87#ibcon#wrote, iclass 30, count 2 2006.257.13:00:37.87#ibcon#about to read 3, iclass 30, count 2 2006.257.13:00:37.89#ibcon#read 3, iclass 30, count 2 2006.257.13:00:37.89#ibcon#about to read 4, iclass 30, count 2 2006.257.13:00:37.89#ibcon#read 4, iclass 30, count 2 2006.257.13:00:37.89#ibcon#about to read 5, iclass 30, count 2 2006.257.13:00:37.89#ibcon#read 5, iclass 30, count 2 2006.257.13:00:37.89#ibcon#about to read 6, iclass 30, count 2 2006.257.13:00:37.89#ibcon#read 6, iclass 30, count 2 2006.257.13:00:37.89#ibcon#end of sib2, iclass 30, count 2 2006.257.13:00:37.89#ibcon#*mode == 0, iclass 30, count 2 2006.257.13:00:37.89#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.13:00:37.89#ibcon#[27=AT06-04\r\n] 2006.257.13:00:37.89#ibcon#*before write, iclass 30, count 2 2006.257.13:00:37.89#ibcon#enter sib2, iclass 30, count 2 2006.257.13:00:37.89#ibcon#flushed, iclass 30, count 2 2006.257.13:00:37.89#ibcon#about to write, iclass 30, count 2 2006.257.13:00:37.89#ibcon#wrote, iclass 30, count 2 2006.257.13:00:37.89#ibcon#about to read 3, iclass 30, count 2 2006.257.13:00:37.92#ibcon#read 3, iclass 30, count 2 2006.257.13:00:37.92#ibcon#about to read 4, iclass 30, count 2 2006.257.13:00:37.92#ibcon#read 4, iclass 30, count 2 2006.257.13:00:37.92#ibcon#about to read 5, iclass 30, count 2 2006.257.13:00:37.92#ibcon#read 5, iclass 30, count 2 2006.257.13:00:37.92#ibcon#about to read 6, iclass 30, count 2 2006.257.13:00:37.92#ibcon#read 6, iclass 30, count 2 2006.257.13:00:37.92#ibcon#end of sib2, iclass 30, count 2 2006.257.13:00:37.92#ibcon#*after write, iclass 30, count 2 2006.257.13:00:37.92#ibcon#*before return 0, iclass 30, count 2 2006.257.13:00:37.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:37.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:00:37.92#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.13:00:37.92#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:37.92#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:38.04#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:38.04#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:38.04#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:00:38.04#ibcon#first serial, iclass 30, count 0 2006.257.13:00:38.04#ibcon#enter sib2, iclass 30, count 0 2006.257.13:00:38.04#ibcon#flushed, iclass 30, count 0 2006.257.13:00:38.04#ibcon#about to write, iclass 30, count 0 2006.257.13:00:38.04#ibcon#wrote, iclass 30, count 0 2006.257.13:00:38.04#ibcon#about to read 3, iclass 30, count 0 2006.257.13:00:38.06#ibcon#read 3, iclass 30, count 0 2006.257.13:00:38.06#ibcon#about to read 4, iclass 30, count 0 2006.257.13:00:38.06#ibcon#read 4, iclass 30, count 0 2006.257.13:00:38.06#ibcon#about to read 5, iclass 30, count 0 2006.257.13:00:38.06#ibcon#read 5, iclass 30, count 0 2006.257.13:00:38.06#ibcon#about to read 6, iclass 30, count 0 2006.257.13:00:38.06#ibcon#read 6, iclass 30, count 0 2006.257.13:00:38.06#ibcon#end of sib2, iclass 30, count 0 2006.257.13:00:38.06#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:00:38.06#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:00:38.06#ibcon#[27=USB\r\n] 2006.257.13:00:38.06#ibcon#*before write, iclass 30, count 0 2006.257.13:00:38.06#ibcon#enter sib2, iclass 30, count 0 2006.257.13:00:38.06#ibcon#flushed, iclass 30, count 0 2006.257.13:00:38.06#ibcon#about to write, iclass 30, count 0 2006.257.13:00:38.06#ibcon#wrote, iclass 30, count 0 2006.257.13:00:38.06#ibcon#about to read 3, iclass 30, count 0 2006.257.13:00:38.09#ibcon#read 3, iclass 30, count 0 2006.257.13:00:38.09#ibcon#about to read 4, iclass 30, count 0 2006.257.13:00:38.09#ibcon#read 4, iclass 30, count 0 2006.257.13:00:38.09#ibcon#about to read 5, iclass 30, count 0 2006.257.13:00:38.09#ibcon#read 5, iclass 30, count 0 2006.257.13:00:38.09#ibcon#about to read 6, iclass 30, count 0 2006.257.13:00:38.09#ibcon#read 6, iclass 30, count 0 2006.257.13:00:38.09#ibcon#end of sib2, iclass 30, count 0 2006.257.13:00:38.09#ibcon#*after write, iclass 30, count 0 2006.257.13:00:38.09#ibcon#*before return 0, iclass 30, count 0 2006.257.13:00:38.09#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:38.09#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:00:38.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:00:38.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:00:38.09$vck44/vblo=7,734.99 2006.257.13:00:38.09#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.13:00:38.09#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.13:00:38.09#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:38.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:38.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:38.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:38.09#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:00:38.09#ibcon#first serial, iclass 32, count 0 2006.257.13:00:38.09#ibcon#enter sib2, iclass 32, count 0 2006.257.13:00:38.09#ibcon#flushed, iclass 32, count 0 2006.257.13:00:38.09#ibcon#about to write, iclass 32, count 0 2006.257.13:00:38.09#ibcon#wrote, iclass 32, count 0 2006.257.13:00:38.09#ibcon#about to read 3, iclass 32, count 0 2006.257.13:00:38.11#ibcon#read 3, iclass 32, count 0 2006.257.13:00:38.11#ibcon#about to read 4, iclass 32, count 0 2006.257.13:00:38.11#ibcon#read 4, iclass 32, count 0 2006.257.13:00:38.11#ibcon#about to read 5, iclass 32, count 0 2006.257.13:00:38.11#ibcon#read 5, iclass 32, count 0 2006.257.13:00:38.11#ibcon#about to read 6, iclass 32, count 0 2006.257.13:00:38.11#ibcon#read 6, iclass 32, count 0 2006.257.13:00:38.11#ibcon#end of sib2, iclass 32, count 0 2006.257.13:00:38.11#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:00:38.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:00:38.11#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:00:38.11#ibcon#*before write, iclass 32, count 0 2006.257.13:00:38.11#ibcon#enter sib2, iclass 32, count 0 2006.257.13:00:38.11#ibcon#flushed, iclass 32, count 0 2006.257.13:00:38.11#ibcon#about to write, iclass 32, count 0 2006.257.13:00:38.11#ibcon#wrote, iclass 32, count 0 2006.257.13:00:38.11#ibcon#about to read 3, iclass 32, count 0 2006.257.13:00:38.15#ibcon#read 3, iclass 32, count 0 2006.257.13:00:38.15#ibcon#about to read 4, iclass 32, count 0 2006.257.13:00:38.15#ibcon#read 4, iclass 32, count 0 2006.257.13:00:38.15#ibcon#about to read 5, iclass 32, count 0 2006.257.13:00:38.15#ibcon#read 5, iclass 32, count 0 2006.257.13:00:38.15#ibcon#about to read 6, iclass 32, count 0 2006.257.13:00:38.15#ibcon#read 6, iclass 32, count 0 2006.257.13:00:38.15#ibcon#end of sib2, iclass 32, count 0 2006.257.13:00:38.15#ibcon#*after write, iclass 32, count 0 2006.257.13:00:38.15#ibcon#*before return 0, iclass 32, count 0 2006.257.13:00:38.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:38.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:00:38.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:00:38.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:00:38.15$vck44/vb=7,4 2006.257.13:00:38.15#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.13:00:38.15#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.13:00:38.15#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:38.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:38.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:38.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:38.21#ibcon#enter wrdev, iclass 34, count 2 2006.257.13:00:38.21#ibcon#first serial, iclass 34, count 2 2006.257.13:00:38.21#ibcon#enter sib2, iclass 34, count 2 2006.257.13:00:38.21#ibcon#flushed, iclass 34, count 2 2006.257.13:00:38.21#ibcon#about to write, iclass 34, count 2 2006.257.13:00:38.21#ibcon#wrote, iclass 34, count 2 2006.257.13:00:38.21#ibcon#about to read 3, iclass 34, count 2 2006.257.13:00:38.23#ibcon#read 3, iclass 34, count 2 2006.257.13:00:38.23#ibcon#about to read 4, iclass 34, count 2 2006.257.13:00:38.23#ibcon#read 4, iclass 34, count 2 2006.257.13:00:38.23#ibcon#about to read 5, iclass 34, count 2 2006.257.13:00:38.23#ibcon#read 5, iclass 34, count 2 2006.257.13:00:38.23#ibcon#about to read 6, iclass 34, count 2 2006.257.13:00:38.23#ibcon#read 6, iclass 34, count 2 2006.257.13:00:38.23#ibcon#end of sib2, iclass 34, count 2 2006.257.13:00:38.23#ibcon#*mode == 0, iclass 34, count 2 2006.257.13:00:38.23#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.13:00:38.23#ibcon#[27=AT07-04\r\n] 2006.257.13:00:38.23#ibcon#*before write, iclass 34, count 2 2006.257.13:00:38.23#ibcon#enter sib2, iclass 34, count 2 2006.257.13:00:38.23#ibcon#flushed, iclass 34, count 2 2006.257.13:00:38.23#ibcon#about to write, iclass 34, count 2 2006.257.13:00:38.23#ibcon#wrote, iclass 34, count 2 2006.257.13:00:38.23#ibcon#about to read 3, iclass 34, count 2 2006.257.13:00:38.26#ibcon#read 3, iclass 34, count 2 2006.257.13:00:38.26#ibcon#about to read 4, iclass 34, count 2 2006.257.13:00:38.26#ibcon#read 4, iclass 34, count 2 2006.257.13:00:38.26#ibcon#about to read 5, iclass 34, count 2 2006.257.13:00:38.26#ibcon#read 5, iclass 34, count 2 2006.257.13:00:38.26#ibcon#about to read 6, iclass 34, count 2 2006.257.13:00:38.26#ibcon#read 6, iclass 34, count 2 2006.257.13:00:38.26#ibcon#end of sib2, iclass 34, count 2 2006.257.13:00:38.26#ibcon#*after write, iclass 34, count 2 2006.257.13:00:38.26#ibcon#*before return 0, iclass 34, count 2 2006.257.13:00:38.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:38.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:00:38.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.13:00:38.26#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:38.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:38.38#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:38.38#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:38.38#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:00:38.38#ibcon#first serial, iclass 34, count 0 2006.257.13:00:38.38#ibcon#enter sib2, iclass 34, count 0 2006.257.13:00:38.38#ibcon#flushed, iclass 34, count 0 2006.257.13:00:38.38#ibcon#about to write, iclass 34, count 0 2006.257.13:00:38.38#ibcon#wrote, iclass 34, count 0 2006.257.13:00:38.38#ibcon#about to read 3, iclass 34, count 0 2006.257.13:00:38.40#ibcon#read 3, iclass 34, count 0 2006.257.13:00:38.40#ibcon#about to read 4, iclass 34, count 0 2006.257.13:00:38.40#ibcon#read 4, iclass 34, count 0 2006.257.13:00:38.40#ibcon#about to read 5, iclass 34, count 0 2006.257.13:00:38.40#ibcon#read 5, iclass 34, count 0 2006.257.13:00:38.40#ibcon#about to read 6, iclass 34, count 0 2006.257.13:00:38.40#ibcon#read 6, iclass 34, count 0 2006.257.13:00:38.40#ibcon#end of sib2, iclass 34, count 0 2006.257.13:00:38.40#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:00:38.40#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:00:38.40#ibcon#[27=USB\r\n] 2006.257.13:00:38.40#ibcon#*before write, iclass 34, count 0 2006.257.13:00:38.40#ibcon#enter sib2, iclass 34, count 0 2006.257.13:00:38.40#ibcon#flushed, iclass 34, count 0 2006.257.13:00:38.40#ibcon#about to write, iclass 34, count 0 2006.257.13:00:38.40#ibcon#wrote, iclass 34, count 0 2006.257.13:00:38.40#ibcon#about to read 3, iclass 34, count 0 2006.257.13:00:38.43#ibcon#read 3, iclass 34, count 0 2006.257.13:00:38.43#ibcon#about to read 4, iclass 34, count 0 2006.257.13:00:38.43#ibcon#read 4, iclass 34, count 0 2006.257.13:00:38.43#ibcon#about to read 5, iclass 34, count 0 2006.257.13:00:38.43#ibcon#read 5, iclass 34, count 0 2006.257.13:00:38.43#ibcon#about to read 6, iclass 34, count 0 2006.257.13:00:38.43#ibcon#read 6, iclass 34, count 0 2006.257.13:00:38.43#ibcon#end of sib2, iclass 34, count 0 2006.257.13:00:38.43#ibcon#*after write, iclass 34, count 0 2006.257.13:00:38.43#ibcon#*before return 0, iclass 34, count 0 2006.257.13:00:38.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:38.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:00:38.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:00:38.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:00:38.43$vck44/vblo=8,744.99 2006.257.13:00:38.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.13:00:38.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.13:00:38.43#ibcon#ireg 17 cls_cnt 0 2006.257.13:00:38.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:38.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:38.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:38.43#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:00:38.43#ibcon#first serial, iclass 36, count 0 2006.257.13:00:38.43#ibcon#enter sib2, iclass 36, count 0 2006.257.13:00:38.43#ibcon#flushed, iclass 36, count 0 2006.257.13:00:38.43#ibcon#about to write, iclass 36, count 0 2006.257.13:00:38.43#ibcon#wrote, iclass 36, count 0 2006.257.13:00:38.43#ibcon#about to read 3, iclass 36, count 0 2006.257.13:00:38.45#ibcon#read 3, iclass 36, count 0 2006.257.13:00:38.45#ibcon#about to read 4, iclass 36, count 0 2006.257.13:00:38.45#ibcon#read 4, iclass 36, count 0 2006.257.13:00:38.45#ibcon#about to read 5, iclass 36, count 0 2006.257.13:00:38.45#ibcon#read 5, iclass 36, count 0 2006.257.13:00:38.45#ibcon#about to read 6, iclass 36, count 0 2006.257.13:00:38.45#ibcon#read 6, iclass 36, count 0 2006.257.13:00:38.45#ibcon#end of sib2, iclass 36, count 0 2006.257.13:00:38.45#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:00:38.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:00:38.45#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:00:38.45#ibcon#*before write, iclass 36, count 0 2006.257.13:00:38.45#ibcon#enter sib2, iclass 36, count 0 2006.257.13:00:38.45#ibcon#flushed, iclass 36, count 0 2006.257.13:00:38.45#ibcon#about to write, iclass 36, count 0 2006.257.13:00:38.45#ibcon#wrote, iclass 36, count 0 2006.257.13:00:38.45#ibcon#about to read 3, iclass 36, count 0 2006.257.13:00:38.49#ibcon#read 3, iclass 36, count 0 2006.257.13:00:38.49#ibcon#about to read 4, iclass 36, count 0 2006.257.13:00:38.49#ibcon#read 4, iclass 36, count 0 2006.257.13:00:38.49#ibcon#about to read 5, iclass 36, count 0 2006.257.13:00:38.49#ibcon#read 5, iclass 36, count 0 2006.257.13:00:38.49#ibcon#about to read 6, iclass 36, count 0 2006.257.13:00:38.49#ibcon#read 6, iclass 36, count 0 2006.257.13:00:38.49#ibcon#end of sib2, iclass 36, count 0 2006.257.13:00:38.49#ibcon#*after write, iclass 36, count 0 2006.257.13:00:38.49#ibcon#*before return 0, iclass 36, count 0 2006.257.13:00:38.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:38.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:00:38.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:00:38.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:00:38.49$vck44/vb=8,4 2006.257.13:00:38.49#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.13:00:38.49#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.13:00:38.49#ibcon#ireg 11 cls_cnt 2 2006.257.13:00:38.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:38.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:38.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:38.55#ibcon#enter wrdev, iclass 38, count 2 2006.257.13:00:38.55#ibcon#first serial, iclass 38, count 2 2006.257.13:00:38.55#ibcon#enter sib2, iclass 38, count 2 2006.257.13:00:38.55#ibcon#flushed, iclass 38, count 2 2006.257.13:00:38.55#ibcon#about to write, iclass 38, count 2 2006.257.13:00:38.55#ibcon#wrote, iclass 38, count 2 2006.257.13:00:38.55#ibcon#about to read 3, iclass 38, count 2 2006.257.13:00:38.57#ibcon#read 3, iclass 38, count 2 2006.257.13:00:38.57#ibcon#about to read 4, iclass 38, count 2 2006.257.13:00:38.57#ibcon#read 4, iclass 38, count 2 2006.257.13:00:38.57#ibcon#about to read 5, iclass 38, count 2 2006.257.13:00:38.57#ibcon#read 5, iclass 38, count 2 2006.257.13:00:38.57#ibcon#about to read 6, iclass 38, count 2 2006.257.13:00:38.57#ibcon#read 6, iclass 38, count 2 2006.257.13:00:38.57#ibcon#end of sib2, iclass 38, count 2 2006.257.13:00:38.57#ibcon#*mode == 0, iclass 38, count 2 2006.257.13:00:38.57#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.13:00:38.57#ibcon#[27=AT08-04\r\n] 2006.257.13:00:38.57#ibcon#*before write, iclass 38, count 2 2006.257.13:00:38.57#ibcon#enter sib2, iclass 38, count 2 2006.257.13:00:38.57#ibcon#flushed, iclass 38, count 2 2006.257.13:00:38.57#ibcon#about to write, iclass 38, count 2 2006.257.13:00:38.57#ibcon#wrote, iclass 38, count 2 2006.257.13:00:38.57#ibcon#about to read 3, iclass 38, count 2 2006.257.13:00:38.60#ibcon#read 3, iclass 38, count 2 2006.257.13:00:38.60#ibcon#about to read 4, iclass 38, count 2 2006.257.13:00:38.60#ibcon#read 4, iclass 38, count 2 2006.257.13:00:38.60#ibcon#about to read 5, iclass 38, count 2 2006.257.13:00:38.60#ibcon#read 5, iclass 38, count 2 2006.257.13:00:38.60#ibcon#about to read 6, iclass 38, count 2 2006.257.13:00:38.60#ibcon#read 6, iclass 38, count 2 2006.257.13:00:38.60#ibcon#end of sib2, iclass 38, count 2 2006.257.13:00:38.60#ibcon#*after write, iclass 38, count 2 2006.257.13:00:38.60#ibcon#*before return 0, iclass 38, count 2 2006.257.13:00:38.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:38.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:00:38.60#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.13:00:38.60#ibcon#ireg 7 cls_cnt 0 2006.257.13:00:38.60#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:38.72#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:38.72#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:38.72#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:00:38.72#ibcon#first serial, iclass 38, count 0 2006.257.13:00:38.72#ibcon#enter sib2, iclass 38, count 0 2006.257.13:00:38.72#ibcon#flushed, iclass 38, count 0 2006.257.13:00:38.72#ibcon#about to write, iclass 38, count 0 2006.257.13:00:38.72#ibcon#wrote, iclass 38, count 0 2006.257.13:00:38.72#ibcon#about to read 3, iclass 38, count 0 2006.257.13:00:38.74#ibcon#read 3, iclass 38, count 0 2006.257.13:00:38.74#ibcon#about to read 4, iclass 38, count 0 2006.257.13:00:38.74#ibcon#read 4, iclass 38, count 0 2006.257.13:00:38.74#ibcon#about to read 5, iclass 38, count 0 2006.257.13:00:38.74#ibcon#read 5, iclass 38, count 0 2006.257.13:00:38.74#ibcon#about to read 6, iclass 38, count 0 2006.257.13:00:38.74#ibcon#read 6, iclass 38, count 0 2006.257.13:00:38.74#ibcon#end of sib2, iclass 38, count 0 2006.257.13:00:38.74#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:00:38.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:00:38.74#ibcon#[27=USB\r\n] 2006.257.13:00:38.74#ibcon#*before write, iclass 38, count 0 2006.257.13:00:38.74#ibcon#enter sib2, iclass 38, count 0 2006.257.13:00:38.74#ibcon#flushed, iclass 38, count 0 2006.257.13:00:38.74#ibcon#about to write, iclass 38, count 0 2006.257.13:00:38.74#ibcon#wrote, iclass 38, count 0 2006.257.13:00:38.74#ibcon#about to read 3, iclass 38, count 0 2006.257.13:00:38.77#ibcon#read 3, iclass 38, count 0 2006.257.13:00:38.77#ibcon#about to read 4, iclass 38, count 0 2006.257.13:00:38.77#ibcon#read 4, iclass 38, count 0 2006.257.13:00:38.77#ibcon#about to read 5, iclass 38, count 0 2006.257.13:00:38.77#ibcon#read 5, iclass 38, count 0 2006.257.13:00:38.77#ibcon#about to read 6, iclass 38, count 0 2006.257.13:00:38.77#ibcon#read 6, iclass 38, count 0 2006.257.13:00:38.77#ibcon#end of sib2, iclass 38, count 0 2006.257.13:00:38.77#ibcon#*after write, iclass 38, count 0 2006.257.13:00:38.77#ibcon#*before return 0, iclass 38, count 0 2006.257.13:00:38.77#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:38.77#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:00:38.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:00:38.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:00:38.77$vck44/vabw=wide 2006.257.13:00:38.77#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.13:00:38.77#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.13:00:38.77#ibcon#ireg 8 cls_cnt 0 2006.257.13:00:38.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:38.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:38.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:38.77#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:00:38.77#ibcon#first serial, iclass 40, count 0 2006.257.13:00:38.77#ibcon#enter sib2, iclass 40, count 0 2006.257.13:00:38.77#ibcon#flushed, iclass 40, count 0 2006.257.13:00:38.77#ibcon#about to write, iclass 40, count 0 2006.257.13:00:38.77#ibcon#wrote, iclass 40, count 0 2006.257.13:00:38.77#ibcon#about to read 3, iclass 40, count 0 2006.257.13:00:38.79#ibcon#read 3, iclass 40, count 0 2006.257.13:00:38.79#ibcon#about to read 4, iclass 40, count 0 2006.257.13:00:38.79#ibcon#read 4, iclass 40, count 0 2006.257.13:00:38.79#ibcon#about to read 5, iclass 40, count 0 2006.257.13:00:38.79#ibcon#read 5, iclass 40, count 0 2006.257.13:00:38.79#ibcon#about to read 6, iclass 40, count 0 2006.257.13:00:38.79#ibcon#read 6, iclass 40, count 0 2006.257.13:00:38.79#ibcon#end of sib2, iclass 40, count 0 2006.257.13:00:38.79#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:00:38.79#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:00:38.79#ibcon#[25=BW32\r\n] 2006.257.13:00:38.79#ibcon#*before write, iclass 40, count 0 2006.257.13:00:38.79#ibcon#enter sib2, iclass 40, count 0 2006.257.13:00:38.79#ibcon#flushed, iclass 40, count 0 2006.257.13:00:38.79#ibcon#about to write, iclass 40, count 0 2006.257.13:00:38.79#ibcon#wrote, iclass 40, count 0 2006.257.13:00:38.79#ibcon#about to read 3, iclass 40, count 0 2006.257.13:00:38.82#ibcon#read 3, iclass 40, count 0 2006.257.13:00:38.82#ibcon#about to read 4, iclass 40, count 0 2006.257.13:00:38.82#ibcon#read 4, iclass 40, count 0 2006.257.13:00:38.82#ibcon#about to read 5, iclass 40, count 0 2006.257.13:00:38.82#ibcon#read 5, iclass 40, count 0 2006.257.13:00:38.82#ibcon#about to read 6, iclass 40, count 0 2006.257.13:00:38.82#ibcon#read 6, iclass 40, count 0 2006.257.13:00:38.82#ibcon#end of sib2, iclass 40, count 0 2006.257.13:00:38.82#ibcon#*after write, iclass 40, count 0 2006.257.13:00:38.82#ibcon#*before return 0, iclass 40, count 0 2006.257.13:00:38.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:38.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:00:38.82#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:00:38.82#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:00:38.82$vck44/vbbw=wide 2006.257.13:00:38.82#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.13:00:38.82#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.13:00:38.82#ibcon#ireg 8 cls_cnt 0 2006.257.13:00:38.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:00:38.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:00:38.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:00:38.89#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:00:38.89#ibcon#first serial, iclass 4, count 0 2006.257.13:00:38.89#ibcon#enter sib2, iclass 4, count 0 2006.257.13:00:38.89#ibcon#flushed, iclass 4, count 0 2006.257.13:00:38.89#ibcon#about to write, iclass 4, count 0 2006.257.13:00:38.89#ibcon#wrote, iclass 4, count 0 2006.257.13:00:38.89#ibcon#about to read 3, iclass 4, count 0 2006.257.13:00:38.91#ibcon#read 3, iclass 4, count 0 2006.257.13:00:38.91#ibcon#about to read 4, iclass 4, count 0 2006.257.13:00:38.91#ibcon#read 4, iclass 4, count 0 2006.257.13:00:38.91#ibcon#about to read 5, iclass 4, count 0 2006.257.13:00:38.91#ibcon#read 5, iclass 4, count 0 2006.257.13:00:38.91#ibcon#about to read 6, iclass 4, count 0 2006.257.13:00:38.91#ibcon#read 6, iclass 4, count 0 2006.257.13:00:38.91#ibcon#end of sib2, iclass 4, count 0 2006.257.13:00:38.91#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:00:38.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:00:38.91#ibcon#[27=BW32\r\n] 2006.257.13:00:38.91#ibcon#*before write, iclass 4, count 0 2006.257.13:00:38.91#ibcon#enter sib2, iclass 4, count 0 2006.257.13:00:38.91#ibcon#flushed, iclass 4, count 0 2006.257.13:00:38.91#ibcon#about to write, iclass 4, count 0 2006.257.13:00:38.91#ibcon#wrote, iclass 4, count 0 2006.257.13:00:38.91#ibcon#about to read 3, iclass 4, count 0 2006.257.13:00:38.94#ibcon#read 3, iclass 4, count 0 2006.257.13:00:38.94#ibcon#about to read 4, iclass 4, count 0 2006.257.13:00:38.94#ibcon#read 4, iclass 4, count 0 2006.257.13:00:38.94#ibcon#about to read 5, iclass 4, count 0 2006.257.13:00:38.94#ibcon#read 5, iclass 4, count 0 2006.257.13:00:38.94#ibcon#about to read 6, iclass 4, count 0 2006.257.13:00:38.94#ibcon#read 6, iclass 4, count 0 2006.257.13:00:38.94#ibcon#end of sib2, iclass 4, count 0 2006.257.13:00:38.94#ibcon#*after write, iclass 4, count 0 2006.257.13:00:38.94#ibcon#*before return 0, iclass 4, count 0 2006.257.13:00:38.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:00:38.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:00:38.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:00:38.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:00:38.94$setupk4/ifdk4 2006.257.13:00:38.94$ifdk4/lo= 2006.257.13:00:38.94$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:00:38.94$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:00:38.94$ifdk4/patch= 2006.257.13:00:38.94$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:00:38.94$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:00:38.94$setupk4/!*+20s 2006.257.13:00:43.26#abcon#<5=/14 2.1 5.0 17.72 961013.9\r\n> 2006.257.13:00:43.28#abcon#{5=INTERFACE CLEAR} 2006.257.13:00:43.34#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:00:53.38$setupk4/"tpicd 2006.257.13:00:53.38$setupk4/echo=off 2006.257.13:00:53.38$setupk4/xlog=off 2006.257.13:00:53.38:!2006.257.13:01:44 2006.257.13:01:26.14#trakl#Source acquired 2006.257.13:01:26.14#flagr#flagr/antenna,acquired 2006.257.13:01:44.00:preob 2006.257.13:01:45.14/onsource/TRACKING 2006.257.13:01:45.14:!2006.257.13:01:54 2006.257.13:01:54.00:"tape 2006.257.13:01:54.00:"st=record 2006.257.13:01:54.00:data_valid=on 2006.257.13:01:54.00:midob 2006.257.13:01:54.14/onsource/TRACKING 2006.257.13:01:54.14/wx/17.72,1013.8,96 2006.257.13:01:54.31/cable/+6.4823E-03 2006.257.13:01:55.40/va/01,08,usb,yes,35,37 2006.257.13:01:55.40/va/02,07,usb,yes,37,38 2006.257.13:01:55.40/va/03,08,usb,yes,34,36 2006.257.13:01:55.40/va/04,07,usb,yes,39,40 2006.257.13:01:55.40/va/05,04,usb,yes,34,35 2006.257.13:01:55.40/va/06,04,usb,yes,38,38 2006.257.13:01:55.40/va/07,04,usb,yes,39,40 2006.257.13:01:55.40/va/08,04,usb,yes,33,40 2006.257.13:01:55.63/valo/01,524.99,yes,locked 2006.257.13:01:55.63/valo/02,534.99,yes,locked 2006.257.13:01:55.63/valo/03,564.99,yes,locked 2006.257.13:01:55.63/valo/04,624.99,yes,locked 2006.257.13:01:55.63/valo/05,734.99,yes,locked 2006.257.13:01:55.63/valo/06,814.99,yes,locked 2006.257.13:01:55.63/valo/07,864.99,yes,locked 2006.257.13:01:55.63/valo/08,884.99,yes,locked 2006.257.13:01:56.72/vb/01,04,usb,yes,33,31 2006.257.13:01:56.72/vb/02,05,usb,yes,32,31 2006.257.13:01:56.72/vb/03,04,usb,yes,33,36 2006.257.13:01:56.72/vb/04,05,usb,yes,33,32 2006.257.13:01:56.72/vb/05,04,usb,yes,29,32 2006.257.13:01:56.72/vb/06,04,usb,yes,34,30 2006.257.13:01:56.72/vb/07,04,usb,yes,34,34 2006.257.13:01:56.72/vb/08,04,usb,yes,31,35 2006.257.13:01:56.96/vblo/01,629.99,yes,locked 2006.257.13:01:56.96/vblo/02,634.99,yes,locked 2006.257.13:01:56.96/vblo/03,649.99,yes,locked 2006.257.13:01:56.96/vblo/04,679.99,yes,locked 2006.257.13:01:56.96/vblo/05,709.99,yes,locked 2006.257.13:01:56.96/vblo/06,719.99,yes,locked 2006.257.13:01:56.96/vblo/07,734.99,yes,locked 2006.257.13:01:56.96/vblo/08,744.99,yes,locked 2006.257.13:01:57.11/vabw/8 2006.257.13:01:57.26/vbbw/8 2006.257.13:01:57.35/xfe/off,on,15.5 2006.257.13:01:57.72/ifatt/23,28,28,28 2006.257.13:01:58.07/fmout-gps/S +4.59E-07 2006.257.13:01:58.11:!2006.257.13:02:34 2006.257.13:02:34.00:data_valid=off 2006.257.13:02:34.00:"et 2006.257.13:02:34.01:!+3s 2006.257.13:02:37.02:"tape 2006.257.13:02:37.02:postob 2006.257.13:02:37.12/cable/+6.4814E-03 2006.257.13:02:37.12/wx/17.71,1013.8,96 2006.257.13:02:37.18/fmout-gps/S +4.59E-07 2006.257.13:02:37.18:scan_name=257-1307,jd0609,140 2006.257.13:02:37.19:source=1958-179,200057.09,-174857.7,2000.0,ccw 2006.257.13:02:39.14#flagr#flagr/antenna,new-source 2006.257.13:02:39.14:checkk5 2006.257.13:02:39.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:02:39.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:02:40.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:02:40.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:02:41.13/chk_obsdata//k5ts1/T2571301??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.13:02:41.54/chk_obsdata//k5ts2/T2571301??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.13:02:41.94/chk_obsdata//k5ts3/T2571301??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.13:02:42.33/chk_obsdata//k5ts4/T2571301??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.13:02:43.04/k5log//k5ts1_log_newline 2006.257.13:02:43.74/k5log//k5ts2_log_newline 2006.257.13:02:44.44/k5log//k5ts3_log_newline 2006.257.13:02:45.16/k5log//k5ts4_log_newline 2006.257.13:02:45.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:02:45.18:setupk4=1 2006.257.13:02:45.18$setupk4/echo=on 2006.257.13:02:45.18$setupk4/pcalon 2006.257.13:02:45.18$pcalon/"no phase cal control is implemented here 2006.257.13:02:45.18$setupk4/"tpicd=stop 2006.257.13:02:45.18$setupk4/"rec=synch_on 2006.257.13:02:45.18$setupk4/"rec_mode=128 2006.257.13:02:45.18$setupk4/!* 2006.257.13:02:45.18$setupk4/recpk4 2006.257.13:02:45.18$recpk4/recpatch= 2006.257.13:02:45.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:02:45.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:02:45.18$setupk4/vck44 2006.257.13:02:45.18$vck44/valo=1,524.99 2006.257.13:02:45.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.13:02:45.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.13:02:45.18#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:45.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:45.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:45.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:45.18#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:02:45.18#ibcon#first serial, iclass 23, count 0 2006.257.13:02:45.18#ibcon#enter sib2, iclass 23, count 0 2006.257.13:02:45.18#ibcon#flushed, iclass 23, count 0 2006.257.13:02:45.18#ibcon#about to write, iclass 23, count 0 2006.257.13:02:45.18#ibcon#wrote, iclass 23, count 0 2006.257.13:02:45.18#ibcon#about to read 3, iclass 23, count 0 2006.257.13:02:45.20#ibcon#read 3, iclass 23, count 0 2006.257.13:02:45.20#ibcon#about to read 4, iclass 23, count 0 2006.257.13:02:45.20#ibcon#read 4, iclass 23, count 0 2006.257.13:02:45.20#ibcon#about to read 5, iclass 23, count 0 2006.257.13:02:45.20#ibcon#read 5, iclass 23, count 0 2006.257.13:02:45.20#ibcon#about to read 6, iclass 23, count 0 2006.257.13:02:45.20#ibcon#read 6, iclass 23, count 0 2006.257.13:02:45.20#ibcon#end of sib2, iclass 23, count 0 2006.257.13:02:45.20#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:02:45.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:02:45.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:02:45.20#ibcon#*before write, iclass 23, count 0 2006.257.13:02:45.20#ibcon#enter sib2, iclass 23, count 0 2006.257.13:02:45.20#ibcon#flushed, iclass 23, count 0 2006.257.13:02:45.20#ibcon#about to write, iclass 23, count 0 2006.257.13:02:45.20#ibcon#wrote, iclass 23, count 0 2006.257.13:02:45.20#ibcon#about to read 3, iclass 23, count 0 2006.257.13:02:45.25#ibcon#read 3, iclass 23, count 0 2006.257.13:02:45.25#ibcon#about to read 4, iclass 23, count 0 2006.257.13:02:45.25#ibcon#read 4, iclass 23, count 0 2006.257.13:02:45.25#ibcon#about to read 5, iclass 23, count 0 2006.257.13:02:45.25#ibcon#read 5, iclass 23, count 0 2006.257.13:02:45.25#ibcon#about to read 6, iclass 23, count 0 2006.257.13:02:45.25#ibcon#read 6, iclass 23, count 0 2006.257.13:02:45.25#ibcon#end of sib2, iclass 23, count 0 2006.257.13:02:45.25#ibcon#*after write, iclass 23, count 0 2006.257.13:02:45.25#ibcon#*before return 0, iclass 23, count 0 2006.257.13:02:45.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:45.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:45.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:02:45.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:02:45.25$vck44/va=1,8 2006.257.13:02:45.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.13:02:45.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.13:02:45.25#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:45.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:45.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:45.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:45.25#ibcon#enter wrdev, iclass 25, count 2 2006.257.13:02:45.25#ibcon#first serial, iclass 25, count 2 2006.257.13:02:45.25#ibcon#enter sib2, iclass 25, count 2 2006.257.13:02:45.25#ibcon#flushed, iclass 25, count 2 2006.257.13:02:45.25#ibcon#about to write, iclass 25, count 2 2006.257.13:02:45.25#ibcon#wrote, iclass 25, count 2 2006.257.13:02:45.25#ibcon#about to read 3, iclass 25, count 2 2006.257.13:02:45.27#ibcon#read 3, iclass 25, count 2 2006.257.13:02:45.27#ibcon#about to read 4, iclass 25, count 2 2006.257.13:02:45.27#ibcon#read 4, iclass 25, count 2 2006.257.13:02:45.27#ibcon#about to read 5, iclass 25, count 2 2006.257.13:02:45.27#ibcon#read 5, iclass 25, count 2 2006.257.13:02:45.27#ibcon#about to read 6, iclass 25, count 2 2006.257.13:02:45.27#ibcon#read 6, iclass 25, count 2 2006.257.13:02:45.27#ibcon#end of sib2, iclass 25, count 2 2006.257.13:02:45.27#ibcon#*mode == 0, iclass 25, count 2 2006.257.13:02:45.27#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.13:02:45.27#ibcon#[25=AT01-08\r\n] 2006.257.13:02:45.27#ibcon#*before write, iclass 25, count 2 2006.257.13:02:45.27#ibcon#enter sib2, iclass 25, count 2 2006.257.13:02:45.27#ibcon#flushed, iclass 25, count 2 2006.257.13:02:45.27#ibcon#about to write, iclass 25, count 2 2006.257.13:02:45.27#ibcon#wrote, iclass 25, count 2 2006.257.13:02:45.27#ibcon#about to read 3, iclass 25, count 2 2006.257.13:02:45.30#abcon#<5=/14 1.9 5.0 17.72 961013.8\r\n> 2006.257.13:02:45.30#ibcon#read 3, iclass 25, count 2 2006.257.13:02:45.30#ibcon#about to read 4, iclass 25, count 2 2006.257.13:02:45.30#ibcon#read 4, iclass 25, count 2 2006.257.13:02:45.30#ibcon#about to read 5, iclass 25, count 2 2006.257.13:02:45.30#ibcon#read 5, iclass 25, count 2 2006.257.13:02:45.30#ibcon#about to read 6, iclass 25, count 2 2006.257.13:02:45.30#ibcon#read 6, iclass 25, count 2 2006.257.13:02:45.30#ibcon#end of sib2, iclass 25, count 2 2006.257.13:02:45.30#ibcon#*after write, iclass 25, count 2 2006.257.13:02:45.30#ibcon#*before return 0, iclass 25, count 2 2006.257.13:02:45.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:45.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:45.30#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.13:02:45.30#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:45.30#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:45.32#abcon#{5=INTERFACE CLEAR} 2006.257.13:02:45.38#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:02:45.42#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:45.42#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:45.42#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:02:45.42#ibcon#first serial, iclass 25, count 0 2006.257.13:02:45.42#ibcon#enter sib2, iclass 25, count 0 2006.257.13:02:45.42#ibcon#flushed, iclass 25, count 0 2006.257.13:02:45.42#ibcon#about to write, iclass 25, count 0 2006.257.13:02:45.42#ibcon#wrote, iclass 25, count 0 2006.257.13:02:45.42#ibcon#about to read 3, iclass 25, count 0 2006.257.13:02:45.44#ibcon#read 3, iclass 25, count 0 2006.257.13:02:45.44#ibcon#about to read 4, iclass 25, count 0 2006.257.13:02:45.44#ibcon#read 4, iclass 25, count 0 2006.257.13:02:45.44#ibcon#about to read 5, iclass 25, count 0 2006.257.13:02:45.44#ibcon#read 5, iclass 25, count 0 2006.257.13:02:45.44#ibcon#about to read 6, iclass 25, count 0 2006.257.13:02:45.44#ibcon#read 6, iclass 25, count 0 2006.257.13:02:45.44#ibcon#end of sib2, iclass 25, count 0 2006.257.13:02:45.44#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:02:45.44#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:02:45.44#ibcon#[25=USB\r\n] 2006.257.13:02:45.44#ibcon#*before write, iclass 25, count 0 2006.257.13:02:45.44#ibcon#enter sib2, iclass 25, count 0 2006.257.13:02:45.44#ibcon#flushed, iclass 25, count 0 2006.257.13:02:45.44#ibcon#about to write, iclass 25, count 0 2006.257.13:02:45.44#ibcon#wrote, iclass 25, count 0 2006.257.13:02:45.44#ibcon#about to read 3, iclass 25, count 0 2006.257.13:02:45.47#ibcon#read 3, iclass 25, count 0 2006.257.13:02:45.47#ibcon#about to read 4, iclass 25, count 0 2006.257.13:02:45.47#ibcon#read 4, iclass 25, count 0 2006.257.13:02:45.47#ibcon#about to read 5, iclass 25, count 0 2006.257.13:02:45.47#ibcon#read 5, iclass 25, count 0 2006.257.13:02:45.47#ibcon#about to read 6, iclass 25, count 0 2006.257.13:02:45.47#ibcon#read 6, iclass 25, count 0 2006.257.13:02:45.47#ibcon#end of sib2, iclass 25, count 0 2006.257.13:02:45.47#ibcon#*after write, iclass 25, count 0 2006.257.13:02:45.47#ibcon#*before return 0, iclass 25, count 0 2006.257.13:02:45.47#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:45.47#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:45.47#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:02:45.47#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:02:45.47$vck44/valo=2,534.99 2006.257.13:02:45.47#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.13:02:45.47#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.13:02:45.47#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:45.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:45.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:45.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:45.47#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:02:45.47#ibcon#first serial, iclass 31, count 0 2006.257.13:02:45.47#ibcon#enter sib2, iclass 31, count 0 2006.257.13:02:45.47#ibcon#flushed, iclass 31, count 0 2006.257.13:02:45.47#ibcon#about to write, iclass 31, count 0 2006.257.13:02:45.47#ibcon#wrote, iclass 31, count 0 2006.257.13:02:45.47#ibcon#about to read 3, iclass 31, count 0 2006.257.13:02:45.49#ibcon#read 3, iclass 31, count 0 2006.257.13:02:45.49#ibcon#about to read 4, iclass 31, count 0 2006.257.13:02:45.49#ibcon#read 4, iclass 31, count 0 2006.257.13:02:45.49#ibcon#about to read 5, iclass 31, count 0 2006.257.13:02:45.49#ibcon#read 5, iclass 31, count 0 2006.257.13:02:45.49#ibcon#about to read 6, iclass 31, count 0 2006.257.13:02:45.49#ibcon#read 6, iclass 31, count 0 2006.257.13:02:45.49#ibcon#end of sib2, iclass 31, count 0 2006.257.13:02:45.49#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:02:45.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:02:45.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:02:45.49#ibcon#*before write, iclass 31, count 0 2006.257.13:02:45.49#ibcon#enter sib2, iclass 31, count 0 2006.257.13:02:45.49#ibcon#flushed, iclass 31, count 0 2006.257.13:02:45.49#ibcon#about to write, iclass 31, count 0 2006.257.13:02:45.49#ibcon#wrote, iclass 31, count 0 2006.257.13:02:45.49#ibcon#about to read 3, iclass 31, count 0 2006.257.13:02:45.53#ibcon#read 3, iclass 31, count 0 2006.257.13:02:45.53#ibcon#about to read 4, iclass 31, count 0 2006.257.13:02:45.53#ibcon#read 4, iclass 31, count 0 2006.257.13:02:45.53#ibcon#about to read 5, iclass 31, count 0 2006.257.13:02:45.53#ibcon#read 5, iclass 31, count 0 2006.257.13:02:45.53#ibcon#about to read 6, iclass 31, count 0 2006.257.13:02:45.53#ibcon#read 6, iclass 31, count 0 2006.257.13:02:45.53#ibcon#end of sib2, iclass 31, count 0 2006.257.13:02:45.53#ibcon#*after write, iclass 31, count 0 2006.257.13:02:45.53#ibcon#*before return 0, iclass 31, count 0 2006.257.13:02:45.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:45.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:45.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:02:45.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:02:45.53$vck44/va=2,7 2006.257.13:02:45.53#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.13:02:45.53#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.13:02:45.53#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:45.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:45.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:45.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:45.59#ibcon#enter wrdev, iclass 33, count 2 2006.257.13:02:45.59#ibcon#first serial, iclass 33, count 2 2006.257.13:02:45.59#ibcon#enter sib2, iclass 33, count 2 2006.257.13:02:45.59#ibcon#flushed, iclass 33, count 2 2006.257.13:02:45.59#ibcon#about to write, iclass 33, count 2 2006.257.13:02:45.59#ibcon#wrote, iclass 33, count 2 2006.257.13:02:45.59#ibcon#about to read 3, iclass 33, count 2 2006.257.13:02:45.61#ibcon#read 3, iclass 33, count 2 2006.257.13:02:45.61#ibcon#about to read 4, iclass 33, count 2 2006.257.13:02:45.61#ibcon#read 4, iclass 33, count 2 2006.257.13:02:45.61#ibcon#about to read 5, iclass 33, count 2 2006.257.13:02:45.61#ibcon#read 5, iclass 33, count 2 2006.257.13:02:45.61#ibcon#about to read 6, iclass 33, count 2 2006.257.13:02:45.61#ibcon#read 6, iclass 33, count 2 2006.257.13:02:45.61#ibcon#end of sib2, iclass 33, count 2 2006.257.13:02:45.61#ibcon#*mode == 0, iclass 33, count 2 2006.257.13:02:45.61#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.13:02:45.61#ibcon#[25=AT02-07\r\n] 2006.257.13:02:45.61#ibcon#*before write, iclass 33, count 2 2006.257.13:02:45.61#ibcon#enter sib2, iclass 33, count 2 2006.257.13:02:45.61#ibcon#flushed, iclass 33, count 2 2006.257.13:02:45.61#ibcon#about to write, iclass 33, count 2 2006.257.13:02:45.61#ibcon#wrote, iclass 33, count 2 2006.257.13:02:45.61#ibcon#about to read 3, iclass 33, count 2 2006.257.13:02:45.64#ibcon#read 3, iclass 33, count 2 2006.257.13:02:45.64#ibcon#about to read 4, iclass 33, count 2 2006.257.13:02:45.64#ibcon#read 4, iclass 33, count 2 2006.257.13:02:45.64#ibcon#about to read 5, iclass 33, count 2 2006.257.13:02:45.64#ibcon#read 5, iclass 33, count 2 2006.257.13:02:45.64#ibcon#about to read 6, iclass 33, count 2 2006.257.13:02:45.64#ibcon#read 6, iclass 33, count 2 2006.257.13:02:45.64#ibcon#end of sib2, iclass 33, count 2 2006.257.13:02:45.64#ibcon#*after write, iclass 33, count 2 2006.257.13:02:45.64#ibcon#*before return 0, iclass 33, count 2 2006.257.13:02:45.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:45.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:45.64#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.13:02:45.64#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:45.64#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:45.76#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:45.76#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:45.76#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:02:45.76#ibcon#first serial, iclass 33, count 0 2006.257.13:02:45.76#ibcon#enter sib2, iclass 33, count 0 2006.257.13:02:45.76#ibcon#flushed, iclass 33, count 0 2006.257.13:02:45.76#ibcon#about to write, iclass 33, count 0 2006.257.13:02:45.76#ibcon#wrote, iclass 33, count 0 2006.257.13:02:45.76#ibcon#about to read 3, iclass 33, count 0 2006.257.13:02:45.78#ibcon#read 3, iclass 33, count 0 2006.257.13:02:45.78#ibcon#about to read 4, iclass 33, count 0 2006.257.13:02:45.78#ibcon#read 4, iclass 33, count 0 2006.257.13:02:45.78#ibcon#about to read 5, iclass 33, count 0 2006.257.13:02:45.78#ibcon#read 5, iclass 33, count 0 2006.257.13:02:45.78#ibcon#about to read 6, iclass 33, count 0 2006.257.13:02:45.78#ibcon#read 6, iclass 33, count 0 2006.257.13:02:45.78#ibcon#end of sib2, iclass 33, count 0 2006.257.13:02:45.78#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:02:45.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:02:45.78#ibcon#[25=USB\r\n] 2006.257.13:02:45.78#ibcon#*before write, iclass 33, count 0 2006.257.13:02:45.78#ibcon#enter sib2, iclass 33, count 0 2006.257.13:02:45.78#ibcon#flushed, iclass 33, count 0 2006.257.13:02:45.78#ibcon#about to write, iclass 33, count 0 2006.257.13:02:45.78#ibcon#wrote, iclass 33, count 0 2006.257.13:02:45.78#ibcon#about to read 3, iclass 33, count 0 2006.257.13:02:45.81#ibcon#read 3, iclass 33, count 0 2006.257.13:02:45.81#ibcon#about to read 4, iclass 33, count 0 2006.257.13:02:45.81#ibcon#read 4, iclass 33, count 0 2006.257.13:02:45.81#ibcon#about to read 5, iclass 33, count 0 2006.257.13:02:45.81#ibcon#read 5, iclass 33, count 0 2006.257.13:02:45.81#ibcon#about to read 6, iclass 33, count 0 2006.257.13:02:45.81#ibcon#read 6, iclass 33, count 0 2006.257.13:02:45.81#ibcon#end of sib2, iclass 33, count 0 2006.257.13:02:45.81#ibcon#*after write, iclass 33, count 0 2006.257.13:02:45.81#ibcon#*before return 0, iclass 33, count 0 2006.257.13:02:45.81#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:45.81#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:45.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:02:45.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:02:45.81$vck44/valo=3,564.99 2006.257.13:02:45.81#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.13:02:45.81#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.13:02:45.81#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:45.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:45.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:45.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:45.81#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:02:45.81#ibcon#first serial, iclass 35, count 0 2006.257.13:02:45.81#ibcon#enter sib2, iclass 35, count 0 2006.257.13:02:45.81#ibcon#flushed, iclass 35, count 0 2006.257.13:02:45.81#ibcon#about to write, iclass 35, count 0 2006.257.13:02:45.81#ibcon#wrote, iclass 35, count 0 2006.257.13:02:45.81#ibcon#about to read 3, iclass 35, count 0 2006.257.13:02:45.83#ibcon#read 3, iclass 35, count 0 2006.257.13:02:45.83#ibcon#about to read 4, iclass 35, count 0 2006.257.13:02:45.83#ibcon#read 4, iclass 35, count 0 2006.257.13:02:45.83#ibcon#about to read 5, iclass 35, count 0 2006.257.13:02:45.83#ibcon#read 5, iclass 35, count 0 2006.257.13:02:45.83#ibcon#about to read 6, iclass 35, count 0 2006.257.13:02:45.83#ibcon#read 6, iclass 35, count 0 2006.257.13:02:45.83#ibcon#end of sib2, iclass 35, count 0 2006.257.13:02:45.83#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:02:45.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:02:45.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:02:45.83#ibcon#*before write, iclass 35, count 0 2006.257.13:02:45.83#ibcon#enter sib2, iclass 35, count 0 2006.257.13:02:45.83#ibcon#flushed, iclass 35, count 0 2006.257.13:02:45.83#ibcon#about to write, iclass 35, count 0 2006.257.13:02:45.83#ibcon#wrote, iclass 35, count 0 2006.257.13:02:45.83#ibcon#about to read 3, iclass 35, count 0 2006.257.13:02:45.87#ibcon#read 3, iclass 35, count 0 2006.257.13:02:45.87#ibcon#about to read 4, iclass 35, count 0 2006.257.13:02:45.87#ibcon#read 4, iclass 35, count 0 2006.257.13:02:45.87#ibcon#about to read 5, iclass 35, count 0 2006.257.13:02:45.87#ibcon#read 5, iclass 35, count 0 2006.257.13:02:45.87#ibcon#about to read 6, iclass 35, count 0 2006.257.13:02:45.87#ibcon#read 6, iclass 35, count 0 2006.257.13:02:45.87#ibcon#end of sib2, iclass 35, count 0 2006.257.13:02:45.87#ibcon#*after write, iclass 35, count 0 2006.257.13:02:45.87#ibcon#*before return 0, iclass 35, count 0 2006.257.13:02:45.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:45.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:45.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:02:45.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:02:45.87$vck44/va=3,8 2006.257.13:02:45.87#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.13:02:45.87#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.13:02:45.87#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:45.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:45.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:45.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:45.93#ibcon#enter wrdev, iclass 37, count 2 2006.257.13:02:45.93#ibcon#first serial, iclass 37, count 2 2006.257.13:02:45.93#ibcon#enter sib2, iclass 37, count 2 2006.257.13:02:45.93#ibcon#flushed, iclass 37, count 2 2006.257.13:02:45.93#ibcon#about to write, iclass 37, count 2 2006.257.13:02:45.93#ibcon#wrote, iclass 37, count 2 2006.257.13:02:45.93#ibcon#about to read 3, iclass 37, count 2 2006.257.13:02:45.95#ibcon#read 3, iclass 37, count 2 2006.257.13:02:45.95#ibcon#about to read 4, iclass 37, count 2 2006.257.13:02:45.95#ibcon#read 4, iclass 37, count 2 2006.257.13:02:45.95#ibcon#about to read 5, iclass 37, count 2 2006.257.13:02:45.95#ibcon#read 5, iclass 37, count 2 2006.257.13:02:45.95#ibcon#about to read 6, iclass 37, count 2 2006.257.13:02:45.95#ibcon#read 6, iclass 37, count 2 2006.257.13:02:45.95#ibcon#end of sib2, iclass 37, count 2 2006.257.13:02:45.95#ibcon#*mode == 0, iclass 37, count 2 2006.257.13:02:45.95#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.13:02:45.95#ibcon#[25=AT03-08\r\n] 2006.257.13:02:45.95#ibcon#*before write, iclass 37, count 2 2006.257.13:02:45.95#ibcon#enter sib2, iclass 37, count 2 2006.257.13:02:45.95#ibcon#flushed, iclass 37, count 2 2006.257.13:02:45.95#ibcon#about to write, iclass 37, count 2 2006.257.13:02:45.95#ibcon#wrote, iclass 37, count 2 2006.257.13:02:45.95#ibcon#about to read 3, iclass 37, count 2 2006.257.13:02:45.98#ibcon#read 3, iclass 37, count 2 2006.257.13:02:45.98#ibcon#about to read 4, iclass 37, count 2 2006.257.13:02:45.98#ibcon#read 4, iclass 37, count 2 2006.257.13:02:45.98#ibcon#about to read 5, iclass 37, count 2 2006.257.13:02:45.98#ibcon#read 5, iclass 37, count 2 2006.257.13:02:45.98#ibcon#about to read 6, iclass 37, count 2 2006.257.13:02:45.98#ibcon#read 6, iclass 37, count 2 2006.257.13:02:45.98#ibcon#end of sib2, iclass 37, count 2 2006.257.13:02:45.98#ibcon#*after write, iclass 37, count 2 2006.257.13:02:45.98#ibcon#*before return 0, iclass 37, count 2 2006.257.13:02:45.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:45.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:45.98#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.13:02:45.98#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:45.98#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:46.10#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:46.10#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:46.10#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:02:46.10#ibcon#first serial, iclass 37, count 0 2006.257.13:02:46.10#ibcon#enter sib2, iclass 37, count 0 2006.257.13:02:46.10#ibcon#flushed, iclass 37, count 0 2006.257.13:02:46.10#ibcon#about to write, iclass 37, count 0 2006.257.13:02:46.10#ibcon#wrote, iclass 37, count 0 2006.257.13:02:46.10#ibcon#about to read 3, iclass 37, count 0 2006.257.13:02:46.12#ibcon#read 3, iclass 37, count 0 2006.257.13:02:46.12#ibcon#about to read 4, iclass 37, count 0 2006.257.13:02:46.12#ibcon#read 4, iclass 37, count 0 2006.257.13:02:46.12#ibcon#about to read 5, iclass 37, count 0 2006.257.13:02:46.12#ibcon#read 5, iclass 37, count 0 2006.257.13:02:46.12#ibcon#about to read 6, iclass 37, count 0 2006.257.13:02:46.12#ibcon#read 6, iclass 37, count 0 2006.257.13:02:46.12#ibcon#end of sib2, iclass 37, count 0 2006.257.13:02:46.12#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:02:46.12#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:02:46.12#ibcon#[25=USB\r\n] 2006.257.13:02:46.12#ibcon#*before write, iclass 37, count 0 2006.257.13:02:46.12#ibcon#enter sib2, iclass 37, count 0 2006.257.13:02:46.12#ibcon#flushed, iclass 37, count 0 2006.257.13:02:46.12#ibcon#about to write, iclass 37, count 0 2006.257.13:02:46.12#ibcon#wrote, iclass 37, count 0 2006.257.13:02:46.12#ibcon#about to read 3, iclass 37, count 0 2006.257.13:02:46.15#ibcon#read 3, iclass 37, count 0 2006.257.13:02:46.15#ibcon#about to read 4, iclass 37, count 0 2006.257.13:02:46.15#ibcon#read 4, iclass 37, count 0 2006.257.13:02:46.15#ibcon#about to read 5, iclass 37, count 0 2006.257.13:02:46.15#ibcon#read 5, iclass 37, count 0 2006.257.13:02:46.15#ibcon#about to read 6, iclass 37, count 0 2006.257.13:02:46.15#ibcon#read 6, iclass 37, count 0 2006.257.13:02:46.15#ibcon#end of sib2, iclass 37, count 0 2006.257.13:02:46.15#ibcon#*after write, iclass 37, count 0 2006.257.13:02:46.15#ibcon#*before return 0, iclass 37, count 0 2006.257.13:02:46.15#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:46.15#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:46.15#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:02:46.15#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:02:46.15$vck44/valo=4,624.99 2006.257.13:02:46.15#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:02:46.15#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:02:46.15#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:46.15#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:46.15#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:46.15#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:46.15#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:02:46.15#ibcon#first serial, iclass 39, count 0 2006.257.13:02:46.15#ibcon#enter sib2, iclass 39, count 0 2006.257.13:02:46.15#ibcon#flushed, iclass 39, count 0 2006.257.13:02:46.15#ibcon#about to write, iclass 39, count 0 2006.257.13:02:46.15#ibcon#wrote, iclass 39, count 0 2006.257.13:02:46.15#ibcon#about to read 3, iclass 39, count 0 2006.257.13:02:46.17#ibcon#read 3, iclass 39, count 0 2006.257.13:02:46.17#ibcon#about to read 4, iclass 39, count 0 2006.257.13:02:46.17#ibcon#read 4, iclass 39, count 0 2006.257.13:02:46.17#ibcon#about to read 5, iclass 39, count 0 2006.257.13:02:46.17#ibcon#read 5, iclass 39, count 0 2006.257.13:02:46.17#ibcon#about to read 6, iclass 39, count 0 2006.257.13:02:46.17#ibcon#read 6, iclass 39, count 0 2006.257.13:02:46.17#ibcon#end of sib2, iclass 39, count 0 2006.257.13:02:46.17#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:02:46.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:02:46.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:02:46.17#ibcon#*before write, iclass 39, count 0 2006.257.13:02:46.17#ibcon#enter sib2, iclass 39, count 0 2006.257.13:02:46.17#ibcon#flushed, iclass 39, count 0 2006.257.13:02:46.17#ibcon#about to write, iclass 39, count 0 2006.257.13:02:46.17#ibcon#wrote, iclass 39, count 0 2006.257.13:02:46.17#ibcon#about to read 3, iclass 39, count 0 2006.257.13:02:46.21#ibcon#read 3, iclass 39, count 0 2006.257.13:02:46.21#ibcon#about to read 4, iclass 39, count 0 2006.257.13:02:46.21#ibcon#read 4, iclass 39, count 0 2006.257.13:02:46.21#ibcon#about to read 5, iclass 39, count 0 2006.257.13:02:46.21#ibcon#read 5, iclass 39, count 0 2006.257.13:02:46.21#ibcon#about to read 6, iclass 39, count 0 2006.257.13:02:46.21#ibcon#read 6, iclass 39, count 0 2006.257.13:02:46.21#ibcon#end of sib2, iclass 39, count 0 2006.257.13:02:46.21#ibcon#*after write, iclass 39, count 0 2006.257.13:02:46.21#ibcon#*before return 0, iclass 39, count 0 2006.257.13:02:46.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:46.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:46.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:02:46.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:02:46.21$vck44/va=4,7 2006.257.13:02:46.21#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.13:02:46.21#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.13:02:46.21#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:46.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:46.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:46.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:46.27#ibcon#enter wrdev, iclass 3, count 2 2006.257.13:02:46.27#ibcon#first serial, iclass 3, count 2 2006.257.13:02:46.27#ibcon#enter sib2, iclass 3, count 2 2006.257.13:02:46.27#ibcon#flushed, iclass 3, count 2 2006.257.13:02:46.27#ibcon#about to write, iclass 3, count 2 2006.257.13:02:46.27#ibcon#wrote, iclass 3, count 2 2006.257.13:02:46.27#ibcon#about to read 3, iclass 3, count 2 2006.257.13:02:46.29#ibcon#read 3, iclass 3, count 2 2006.257.13:02:46.29#ibcon#about to read 4, iclass 3, count 2 2006.257.13:02:46.29#ibcon#read 4, iclass 3, count 2 2006.257.13:02:46.29#ibcon#about to read 5, iclass 3, count 2 2006.257.13:02:46.29#ibcon#read 5, iclass 3, count 2 2006.257.13:02:46.29#ibcon#about to read 6, iclass 3, count 2 2006.257.13:02:46.29#ibcon#read 6, iclass 3, count 2 2006.257.13:02:46.29#ibcon#end of sib2, iclass 3, count 2 2006.257.13:02:46.29#ibcon#*mode == 0, iclass 3, count 2 2006.257.13:02:46.29#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.13:02:46.29#ibcon#[25=AT04-07\r\n] 2006.257.13:02:46.29#ibcon#*before write, iclass 3, count 2 2006.257.13:02:46.29#ibcon#enter sib2, iclass 3, count 2 2006.257.13:02:46.29#ibcon#flushed, iclass 3, count 2 2006.257.13:02:46.29#ibcon#about to write, iclass 3, count 2 2006.257.13:02:46.29#ibcon#wrote, iclass 3, count 2 2006.257.13:02:46.29#ibcon#about to read 3, iclass 3, count 2 2006.257.13:02:46.32#ibcon#read 3, iclass 3, count 2 2006.257.13:02:46.32#ibcon#about to read 4, iclass 3, count 2 2006.257.13:02:46.32#ibcon#read 4, iclass 3, count 2 2006.257.13:02:46.32#ibcon#about to read 5, iclass 3, count 2 2006.257.13:02:46.32#ibcon#read 5, iclass 3, count 2 2006.257.13:02:46.32#ibcon#about to read 6, iclass 3, count 2 2006.257.13:02:46.32#ibcon#read 6, iclass 3, count 2 2006.257.13:02:46.32#ibcon#end of sib2, iclass 3, count 2 2006.257.13:02:46.32#ibcon#*after write, iclass 3, count 2 2006.257.13:02:46.32#ibcon#*before return 0, iclass 3, count 2 2006.257.13:02:46.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:46.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:46.32#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.13:02:46.32#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:46.32#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:46.44#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:46.44#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:46.44#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:02:46.44#ibcon#first serial, iclass 3, count 0 2006.257.13:02:46.44#ibcon#enter sib2, iclass 3, count 0 2006.257.13:02:46.44#ibcon#flushed, iclass 3, count 0 2006.257.13:02:46.44#ibcon#about to write, iclass 3, count 0 2006.257.13:02:46.44#ibcon#wrote, iclass 3, count 0 2006.257.13:02:46.44#ibcon#about to read 3, iclass 3, count 0 2006.257.13:02:46.46#ibcon#read 3, iclass 3, count 0 2006.257.13:02:46.46#ibcon#about to read 4, iclass 3, count 0 2006.257.13:02:46.46#ibcon#read 4, iclass 3, count 0 2006.257.13:02:46.46#ibcon#about to read 5, iclass 3, count 0 2006.257.13:02:46.46#ibcon#read 5, iclass 3, count 0 2006.257.13:02:46.46#ibcon#about to read 6, iclass 3, count 0 2006.257.13:02:46.46#ibcon#read 6, iclass 3, count 0 2006.257.13:02:46.46#ibcon#end of sib2, iclass 3, count 0 2006.257.13:02:46.46#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:02:46.46#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:02:46.46#ibcon#[25=USB\r\n] 2006.257.13:02:46.46#ibcon#*before write, iclass 3, count 0 2006.257.13:02:46.46#ibcon#enter sib2, iclass 3, count 0 2006.257.13:02:46.46#ibcon#flushed, iclass 3, count 0 2006.257.13:02:46.46#ibcon#about to write, iclass 3, count 0 2006.257.13:02:46.46#ibcon#wrote, iclass 3, count 0 2006.257.13:02:46.46#ibcon#about to read 3, iclass 3, count 0 2006.257.13:02:46.49#ibcon#read 3, iclass 3, count 0 2006.257.13:02:46.49#ibcon#about to read 4, iclass 3, count 0 2006.257.13:02:46.49#ibcon#read 4, iclass 3, count 0 2006.257.13:02:46.49#ibcon#about to read 5, iclass 3, count 0 2006.257.13:02:46.49#ibcon#read 5, iclass 3, count 0 2006.257.13:02:46.49#ibcon#about to read 6, iclass 3, count 0 2006.257.13:02:46.49#ibcon#read 6, iclass 3, count 0 2006.257.13:02:46.49#ibcon#end of sib2, iclass 3, count 0 2006.257.13:02:46.49#ibcon#*after write, iclass 3, count 0 2006.257.13:02:46.49#ibcon#*before return 0, iclass 3, count 0 2006.257.13:02:46.49#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:46.49#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:46.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:02:46.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:02:46.49$vck44/valo=5,734.99 2006.257.13:02:46.49#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.13:02:46.49#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.13:02:46.49#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:46.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:46.49#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:46.49#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:46.49#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:02:46.49#ibcon#first serial, iclass 5, count 0 2006.257.13:02:46.49#ibcon#enter sib2, iclass 5, count 0 2006.257.13:02:46.49#ibcon#flushed, iclass 5, count 0 2006.257.13:02:46.49#ibcon#about to write, iclass 5, count 0 2006.257.13:02:46.49#ibcon#wrote, iclass 5, count 0 2006.257.13:02:46.49#ibcon#about to read 3, iclass 5, count 0 2006.257.13:02:46.51#ibcon#read 3, iclass 5, count 0 2006.257.13:02:46.51#ibcon#about to read 4, iclass 5, count 0 2006.257.13:02:46.51#ibcon#read 4, iclass 5, count 0 2006.257.13:02:46.51#ibcon#about to read 5, iclass 5, count 0 2006.257.13:02:46.51#ibcon#read 5, iclass 5, count 0 2006.257.13:02:46.51#ibcon#about to read 6, iclass 5, count 0 2006.257.13:02:46.51#ibcon#read 6, iclass 5, count 0 2006.257.13:02:46.51#ibcon#end of sib2, iclass 5, count 0 2006.257.13:02:46.51#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:02:46.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:02:46.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:02:46.51#ibcon#*before write, iclass 5, count 0 2006.257.13:02:46.51#ibcon#enter sib2, iclass 5, count 0 2006.257.13:02:46.51#ibcon#flushed, iclass 5, count 0 2006.257.13:02:46.51#ibcon#about to write, iclass 5, count 0 2006.257.13:02:46.51#ibcon#wrote, iclass 5, count 0 2006.257.13:02:46.51#ibcon#about to read 3, iclass 5, count 0 2006.257.13:02:46.55#ibcon#read 3, iclass 5, count 0 2006.257.13:02:46.55#ibcon#about to read 4, iclass 5, count 0 2006.257.13:02:46.55#ibcon#read 4, iclass 5, count 0 2006.257.13:02:46.55#ibcon#about to read 5, iclass 5, count 0 2006.257.13:02:46.55#ibcon#read 5, iclass 5, count 0 2006.257.13:02:46.55#ibcon#about to read 6, iclass 5, count 0 2006.257.13:02:46.55#ibcon#read 6, iclass 5, count 0 2006.257.13:02:46.55#ibcon#end of sib2, iclass 5, count 0 2006.257.13:02:46.55#ibcon#*after write, iclass 5, count 0 2006.257.13:02:46.55#ibcon#*before return 0, iclass 5, count 0 2006.257.13:02:46.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:46.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:46.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:02:46.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:02:46.55$vck44/va=5,4 2006.257.13:02:46.55#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.13:02:46.55#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.13:02:46.55#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:46.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:46.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:46.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:46.61#ibcon#enter wrdev, iclass 7, count 2 2006.257.13:02:46.61#ibcon#first serial, iclass 7, count 2 2006.257.13:02:46.61#ibcon#enter sib2, iclass 7, count 2 2006.257.13:02:46.61#ibcon#flushed, iclass 7, count 2 2006.257.13:02:46.61#ibcon#about to write, iclass 7, count 2 2006.257.13:02:46.61#ibcon#wrote, iclass 7, count 2 2006.257.13:02:46.61#ibcon#about to read 3, iclass 7, count 2 2006.257.13:02:46.63#ibcon#read 3, iclass 7, count 2 2006.257.13:02:46.63#ibcon#about to read 4, iclass 7, count 2 2006.257.13:02:46.63#ibcon#read 4, iclass 7, count 2 2006.257.13:02:46.63#ibcon#about to read 5, iclass 7, count 2 2006.257.13:02:46.63#ibcon#read 5, iclass 7, count 2 2006.257.13:02:46.63#ibcon#about to read 6, iclass 7, count 2 2006.257.13:02:46.63#ibcon#read 6, iclass 7, count 2 2006.257.13:02:46.63#ibcon#end of sib2, iclass 7, count 2 2006.257.13:02:46.63#ibcon#*mode == 0, iclass 7, count 2 2006.257.13:02:46.63#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.13:02:46.63#ibcon#[25=AT05-04\r\n] 2006.257.13:02:46.63#ibcon#*before write, iclass 7, count 2 2006.257.13:02:46.63#ibcon#enter sib2, iclass 7, count 2 2006.257.13:02:46.63#ibcon#flushed, iclass 7, count 2 2006.257.13:02:46.63#ibcon#about to write, iclass 7, count 2 2006.257.13:02:46.63#ibcon#wrote, iclass 7, count 2 2006.257.13:02:46.63#ibcon#about to read 3, iclass 7, count 2 2006.257.13:02:46.66#ibcon#read 3, iclass 7, count 2 2006.257.13:02:46.66#ibcon#about to read 4, iclass 7, count 2 2006.257.13:02:46.66#ibcon#read 4, iclass 7, count 2 2006.257.13:02:46.66#ibcon#about to read 5, iclass 7, count 2 2006.257.13:02:46.66#ibcon#read 5, iclass 7, count 2 2006.257.13:02:46.66#ibcon#about to read 6, iclass 7, count 2 2006.257.13:02:46.66#ibcon#read 6, iclass 7, count 2 2006.257.13:02:46.66#ibcon#end of sib2, iclass 7, count 2 2006.257.13:02:46.66#ibcon#*after write, iclass 7, count 2 2006.257.13:02:46.66#ibcon#*before return 0, iclass 7, count 2 2006.257.13:02:46.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:46.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:46.66#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.13:02:46.66#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:46.66#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:46.78#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:46.78#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:46.78#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:02:46.78#ibcon#first serial, iclass 7, count 0 2006.257.13:02:46.78#ibcon#enter sib2, iclass 7, count 0 2006.257.13:02:46.78#ibcon#flushed, iclass 7, count 0 2006.257.13:02:46.78#ibcon#about to write, iclass 7, count 0 2006.257.13:02:46.78#ibcon#wrote, iclass 7, count 0 2006.257.13:02:46.78#ibcon#about to read 3, iclass 7, count 0 2006.257.13:02:46.80#ibcon#read 3, iclass 7, count 0 2006.257.13:02:46.80#ibcon#about to read 4, iclass 7, count 0 2006.257.13:02:46.80#ibcon#read 4, iclass 7, count 0 2006.257.13:02:46.80#ibcon#about to read 5, iclass 7, count 0 2006.257.13:02:46.80#ibcon#read 5, iclass 7, count 0 2006.257.13:02:46.80#ibcon#about to read 6, iclass 7, count 0 2006.257.13:02:46.80#ibcon#read 6, iclass 7, count 0 2006.257.13:02:46.80#ibcon#end of sib2, iclass 7, count 0 2006.257.13:02:46.80#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:02:46.80#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:02:46.80#ibcon#[25=USB\r\n] 2006.257.13:02:46.80#ibcon#*before write, iclass 7, count 0 2006.257.13:02:46.80#ibcon#enter sib2, iclass 7, count 0 2006.257.13:02:46.80#ibcon#flushed, iclass 7, count 0 2006.257.13:02:46.80#ibcon#about to write, iclass 7, count 0 2006.257.13:02:46.80#ibcon#wrote, iclass 7, count 0 2006.257.13:02:46.80#ibcon#about to read 3, iclass 7, count 0 2006.257.13:02:46.83#ibcon#read 3, iclass 7, count 0 2006.257.13:02:46.83#ibcon#about to read 4, iclass 7, count 0 2006.257.13:02:46.83#ibcon#read 4, iclass 7, count 0 2006.257.13:02:46.83#ibcon#about to read 5, iclass 7, count 0 2006.257.13:02:46.83#ibcon#read 5, iclass 7, count 0 2006.257.13:02:46.83#ibcon#about to read 6, iclass 7, count 0 2006.257.13:02:46.83#ibcon#read 6, iclass 7, count 0 2006.257.13:02:46.83#ibcon#end of sib2, iclass 7, count 0 2006.257.13:02:46.83#ibcon#*after write, iclass 7, count 0 2006.257.13:02:46.83#ibcon#*before return 0, iclass 7, count 0 2006.257.13:02:46.83#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:46.83#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:46.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:02:46.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:02:46.83$vck44/valo=6,814.99 2006.257.13:02:46.83#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.13:02:46.83#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.13:02:46.83#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:46.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:46.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:46.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:46.83#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:02:46.83#ibcon#first serial, iclass 11, count 0 2006.257.13:02:46.83#ibcon#enter sib2, iclass 11, count 0 2006.257.13:02:46.83#ibcon#flushed, iclass 11, count 0 2006.257.13:02:46.83#ibcon#about to write, iclass 11, count 0 2006.257.13:02:46.83#ibcon#wrote, iclass 11, count 0 2006.257.13:02:46.83#ibcon#about to read 3, iclass 11, count 0 2006.257.13:02:46.85#ibcon#read 3, iclass 11, count 0 2006.257.13:02:46.85#ibcon#about to read 4, iclass 11, count 0 2006.257.13:02:46.85#ibcon#read 4, iclass 11, count 0 2006.257.13:02:46.85#ibcon#about to read 5, iclass 11, count 0 2006.257.13:02:46.85#ibcon#read 5, iclass 11, count 0 2006.257.13:02:46.85#ibcon#about to read 6, iclass 11, count 0 2006.257.13:02:46.85#ibcon#read 6, iclass 11, count 0 2006.257.13:02:46.85#ibcon#end of sib2, iclass 11, count 0 2006.257.13:02:46.85#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:02:46.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:02:46.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:02:46.85#ibcon#*before write, iclass 11, count 0 2006.257.13:02:46.85#ibcon#enter sib2, iclass 11, count 0 2006.257.13:02:46.85#ibcon#flushed, iclass 11, count 0 2006.257.13:02:46.85#ibcon#about to write, iclass 11, count 0 2006.257.13:02:46.85#ibcon#wrote, iclass 11, count 0 2006.257.13:02:46.85#ibcon#about to read 3, iclass 11, count 0 2006.257.13:02:46.89#ibcon#read 3, iclass 11, count 0 2006.257.13:02:46.89#ibcon#about to read 4, iclass 11, count 0 2006.257.13:02:46.89#ibcon#read 4, iclass 11, count 0 2006.257.13:02:46.89#ibcon#about to read 5, iclass 11, count 0 2006.257.13:02:46.89#ibcon#read 5, iclass 11, count 0 2006.257.13:02:46.89#ibcon#about to read 6, iclass 11, count 0 2006.257.13:02:46.89#ibcon#read 6, iclass 11, count 0 2006.257.13:02:46.89#ibcon#end of sib2, iclass 11, count 0 2006.257.13:02:46.89#ibcon#*after write, iclass 11, count 0 2006.257.13:02:46.89#ibcon#*before return 0, iclass 11, count 0 2006.257.13:02:46.89#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:46.89#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:46.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:02:46.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:02:46.89$vck44/va=6,4 2006.257.13:02:46.89#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.13:02:46.89#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.13:02:46.89#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:46.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:46.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:46.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:46.95#ibcon#enter wrdev, iclass 13, count 2 2006.257.13:02:46.95#ibcon#first serial, iclass 13, count 2 2006.257.13:02:46.95#ibcon#enter sib2, iclass 13, count 2 2006.257.13:02:46.95#ibcon#flushed, iclass 13, count 2 2006.257.13:02:46.95#ibcon#about to write, iclass 13, count 2 2006.257.13:02:46.95#ibcon#wrote, iclass 13, count 2 2006.257.13:02:46.95#ibcon#about to read 3, iclass 13, count 2 2006.257.13:02:46.97#ibcon#read 3, iclass 13, count 2 2006.257.13:02:46.97#ibcon#about to read 4, iclass 13, count 2 2006.257.13:02:46.97#ibcon#read 4, iclass 13, count 2 2006.257.13:02:46.97#ibcon#about to read 5, iclass 13, count 2 2006.257.13:02:46.97#ibcon#read 5, iclass 13, count 2 2006.257.13:02:46.97#ibcon#about to read 6, iclass 13, count 2 2006.257.13:02:46.97#ibcon#read 6, iclass 13, count 2 2006.257.13:02:46.97#ibcon#end of sib2, iclass 13, count 2 2006.257.13:02:46.97#ibcon#*mode == 0, iclass 13, count 2 2006.257.13:02:46.97#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.13:02:46.97#ibcon#[25=AT06-04\r\n] 2006.257.13:02:46.97#ibcon#*before write, iclass 13, count 2 2006.257.13:02:46.97#ibcon#enter sib2, iclass 13, count 2 2006.257.13:02:46.97#ibcon#flushed, iclass 13, count 2 2006.257.13:02:46.97#ibcon#about to write, iclass 13, count 2 2006.257.13:02:46.97#ibcon#wrote, iclass 13, count 2 2006.257.13:02:46.97#ibcon#about to read 3, iclass 13, count 2 2006.257.13:02:47.00#ibcon#read 3, iclass 13, count 2 2006.257.13:02:47.00#ibcon#about to read 4, iclass 13, count 2 2006.257.13:02:47.00#ibcon#read 4, iclass 13, count 2 2006.257.13:02:47.00#ibcon#about to read 5, iclass 13, count 2 2006.257.13:02:47.00#ibcon#read 5, iclass 13, count 2 2006.257.13:02:47.00#ibcon#about to read 6, iclass 13, count 2 2006.257.13:02:47.00#ibcon#read 6, iclass 13, count 2 2006.257.13:02:47.00#ibcon#end of sib2, iclass 13, count 2 2006.257.13:02:47.00#ibcon#*after write, iclass 13, count 2 2006.257.13:02:47.00#ibcon#*before return 0, iclass 13, count 2 2006.257.13:02:47.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:47.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:47.00#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.13:02:47.00#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:47.00#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:47.12#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:47.12#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:47.12#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:02:47.12#ibcon#first serial, iclass 13, count 0 2006.257.13:02:47.12#ibcon#enter sib2, iclass 13, count 0 2006.257.13:02:47.12#ibcon#flushed, iclass 13, count 0 2006.257.13:02:47.12#ibcon#about to write, iclass 13, count 0 2006.257.13:02:47.12#ibcon#wrote, iclass 13, count 0 2006.257.13:02:47.12#ibcon#about to read 3, iclass 13, count 0 2006.257.13:02:47.14#ibcon#read 3, iclass 13, count 0 2006.257.13:02:47.14#ibcon#about to read 4, iclass 13, count 0 2006.257.13:02:47.14#ibcon#read 4, iclass 13, count 0 2006.257.13:02:47.14#ibcon#about to read 5, iclass 13, count 0 2006.257.13:02:47.14#ibcon#read 5, iclass 13, count 0 2006.257.13:02:47.14#ibcon#about to read 6, iclass 13, count 0 2006.257.13:02:47.14#ibcon#read 6, iclass 13, count 0 2006.257.13:02:47.14#ibcon#end of sib2, iclass 13, count 0 2006.257.13:02:47.14#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:02:47.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:02:47.14#ibcon#[25=USB\r\n] 2006.257.13:02:47.14#ibcon#*before write, iclass 13, count 0 2006.257.13:02:47.14#ibcon#enter sib2, iclass 13, count 0 2006.257.13:02:47.14#ibcon#flushed, iclass 13, count 0 2006.257.13:02:47.14#ibcon#about to write, iclass 13, count 0 2006.257.13:02:47.14#ibcon#wrote, iclass 13, count 0 2006.257.13:02:47.14#ibcon#about to read 3, iclass 13, count 0 2006.257.13:02:47.17#ibcon#read 3, iclass 13, count 0 2006.257.13:02:47.17#ibcon#about to read 4, iclass 13, count 0 2006.257.13:02:47.17#ibcon#read 4, iclass 13, count 0 2006.257.13:02:47.17#ibcon#about to read 5, iclass 13, count 0 2006.257.13:02:47.17#ibcon#read 5, iclass 13, count 0 2006.257.13:02:47.17#ibcon#about to read 6, iclass 13, count 0 2006.257.13:02:47.17#ibcon#read 6, iclass 13, count 0 2006.257.13:02:47.17#ibcon#end of sib2, iclass 13, count 0 2006.257.13:02:47.17#ibcon#*after write, iclass 13, count 0 2006.257.13:02:47.17#ibcon#*before return 0, iclass 13, count 0 2006.257.13:02:47.17#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:47.17#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:47.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:02:47.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:02:47.17$vck44/valo=7,864.99 2006.257.13:02:47.17#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.13:02:47.17#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.13:02:47.17#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:47.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:47.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:47.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:47.17#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:02:47.17#ibcon#first serial, iclass 15, count 0 2006.257.13:02:47.17#ibcon#enter sib2, iclass 15, count 0 2006.257.13:02:47.17#ibcon#flushed, iclass 15, count 0 2006.257.13:02:47.17#ibcon#about to write, iclass 15, count 0 2006.257.13:02:47.17#ibcon#wrote, iclass 15, count 0 2006.257.13:02:47.17#ibcon#about to read 3, iclass 15, count 0 2006.257.13:02:47.19#ibcon#read 3, iclass 15, count 0 2006.257.13:02:47.19#ibcon#about to read 4, iclass 15, count 0 2006.257.13:02:47.19#ibcon#read 4, iclass 15, count 0 2006.257.13:02:47.19#ibcon#about to read 5, iclass 15, count 0 2006.257.13:02:47.19#ibcon#read 5, iclass 15, count 0 2006.257.13:02:47.19#ibcon#about to read 6, iclass 15, count 0 2006.257.13:02:47.19#ibcon#read 6, iclass 15, count 0 2006.257.13:02:47.19#ibcon#end of sib2, iclass 15, count 0 2006.257.13:02:47.19#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:02:47.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:02:47.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:02:47.19#ibcon#*before write, iclass 15, count 0 2006.257.13:02:47.19#ibcon#enter sib2, iclass 15, count 0 2006.257.13:02:47.19#ibcon#flushed, iclass 15, count 0 2006.257.13:02:47.19#ibcon#about to write, iclass 15, count 0 2006.257.13:02:47.19#ibcon#wrote, iclass 15, count 0 2006.257.13:02:47.19#ibcon#about to read 3, iclass 15, count 0 2006.257.13:02:47.23#ibcon#read 3, iclass 15, count 0 2006.257.13:02:47.23#ibcon#about to read 4, iclass 15, count 0 2006.257.13:02:47.23#ibcon#read 4, iclass 15, count 0 2006.257.13:02:47.23#ibcon#about to read 5, iclass 15, count 0 2006.257.13:02:47.23#ibcon#read 5, iclass 15, count 0 2006.257.13:02:47.23#ibcon#about to read 6, iclass 15, count 0 2006.257.13:02:47.23#ibcon#read 6, iclass 15, count 0 2006.257.13:02:47.23#ibcon#end of sib2, iclass 15, count 0 2006.257.13:02:47.23#ibcon#*after write, iclass 15, count 0 2006.257.13:02:47.23#ibcon#*before return 0, iclass 15, count 0 2006.257.13:02:47.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:47.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:47.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:02:47.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:02:47.23$vck44/va=7,4 2006.257.13:02:47.23#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.13:02:47.23#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.13:02:47.23#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:47.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:47.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:47.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:47.29#ibcon#enter wrdev, iclass 17, count 2 2006.257.13:02:47.29#ibcon#first serial, iclass 17, count 2 2006.257.13:02:47.29#ibcon#enter sib2, iclass 17, count 2 2006.257.13:02:47.29#ibcon#flushed, iclass 17, count 2 2006.257.13:02:47.29#ibcon#about to write, iclass 17, count 2 2006.257.13:02:47.29#ibcon#wrote, iclass 17, count 2 2006.257.13:02:47.29#ibcon#about to read 3, iclass 17, count 2 2006.257.13:02:47.31#ibcon#read 3, iclass 17, count 2 2006.257.13:02:47.31#ibcon#about to read 4, iclass 17, count 2 2006.257.13:02:47.31#ibcon#read 4, iclass 17, count 2 2006.257.13:02:47.31#ibcon#about to read 5, iclass 17, count 2 2006.257.13:02:47.31#ibcon#read 5, iclass 17, count 2 2006.257.13:02:47.31#ibcon#about to read 6, iclass 17, count 2 2006.257.13:02:47.31#ibcon#read 6, iclass 17, count 2 2006.257.13:02:47.31#ibcon#end of sib2, iclass 17, count 2 2006.257.13:02:47.31#ibcon#*mode == 0, iclass 17, count 2 2006.257.13:02:47.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.13:02:47.31#ibcon#[25=AT07-04\r\n] 2006.257.13:02:47.31#ibcon#*before write, iclass 17, count 2 2006.257.13:02:47.31#ibcon#enter sib2, iclass 17, count 2 2006.257.13:02:47.31#ibcon#flushed, iclass 17, count 2 2006.257.13:02:47.31#ibcon#about to write, iclass 17, count 2 2006.257.13:02:47.31#ibcon#wrote, iclass 17, count 2 2006.257.13:02:47.31#ibcon#about to read 3, iclass 17, count 2 2006.257.13:02:47.34#ibcon#read 3, iclass 17, count 2 2006.257.13:02:47.34#ibcon#about to read 4, iclass 17, count 2 2006.257.13:02:47.34#ibcon#read 4, iclass 17, count 2 2006.257.13:02:47.34#ibcon#about to read 5, iclass 17, count 2 2006.257.13:02:47.34#ibcon#read 5, iclass 17, count 2 2006.257.13:02:47.34#ibcon#about to read 6, iclass 17, count 2 2006.257.13:02:47.34#ibcon#read 6, iclass 17, count 2 2006.257.13:02:47.34#ibcon#end of sib2, iclass 17, count 2 2006.257.13:02:47.34#ibcon#*after write, iclass 17, count 2 2006.257.13:02:47.34#ibcon#*before return 0, iclass 17, count 2 2006.257.13:02:47.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:47.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:47.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.13:02:47.34#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:47.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:47.46#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:47.46#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:47.46#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:02:47.46#ibcon#first serial, iclass 17, count 0 2006.257.13:02:47.46#ibcon#enter sib2, iclass 17, count 0 2006.257.13:02:47.46#ibcon#flushed, iclass 17, count 0 2006.257.13:02:47.46#ibcon#about to write, iclass 17, count 0 2006.257.13:02:47.46#ibcon#wrote, iclass 17, count 0 2006.257.13:02:47.46#ibcon#about to read 3, iclass 17, count 0 2006.257.13:02:47.48#ibcon#read 3, iclass 17, count 0 2006.257.13:02:47.48#ibcon#about to read 4, iclass 17, count 0 2006.257.13:02:47.48#ibcon#read 4, iclass 17, count 0 2006.257.13:02:47.48#ibcon#about to read 5, iclass 17, count 0 2006.257.13:02:47.48#ibcon#read 5, iclass 17, count 0 2006.257.13:02:47.48#ibcon#about to read 6, iclass 17, count 0 2006.257.13:02:47.48#ibcon#read 6, iclass 17, count 0 2006.257.13:02:47.48#ibcon#end of sib2, iclass 17, count 0 2006.257.13:02:47.48#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:02:47.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:02:47.48#ibcon#[25=USB\r\n] 2006.257.13:02:47.48#ibcon#*before write, iclass 17, count 0 2006.257.13:02:47.48#ibcon#enter sib2, iclass 17, count 0 2006.257.13:02:47.48#ibcon#flushed, iclass 17, count 0 2006.257.13:02:47.48#ibcon#about to write, iclass 17, count 0 2006.257.13:02:47.48#ibcon#wrote, iclass 17, count 0 2006.257.13:02:47.48#ibcon#about to read 3, iclass 17, count 0 2006.257.13:02:47.51#ibcon#read 3, iclass 17, count 0 2006.257.13:02:47.51#ibcon#about to read 4, iclass 17, count 0 2006.257.13:02:47.51#ibcon#read 4, iclass 17, count 0 2006.257.13:02:47.51#ibcon#about to read 5, iclass 17, count 0 2006.257.13:02:47.51#ibcon#read 5, iclass 17, count 0 2006.257.13:02:47.51#ibcon#about to read 6, iclass 17, count 0 2006.257.13:02:47.51#ibcon#read 6, iclass 17, count 0 2006.257.13:02:47.51#ibcon#end of sib2, iclass 17, count 0 2006.257.13:02:47.51#ibcon#*after write, iclass 17, count 0 2006.257.13:02:47.51#ibcon#*before return 0, iclass 17, count 0 2006.257.13:02:47.51#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:47.51#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:47.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:02:47.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:02:47.51$vck44/valo=8,884.99 2006.257.13:02:47.51#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.13:02:47.51#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.13:02:47.51#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:47.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:47.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:47.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:47.51#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:02:47.51#ibcon#first serial, iclass 19, count 0 2006.257.13:02:47.51#ibcon#enter sib2, iclass 19, count 0 2006.257.13:02:47.51#ibcon#flushed, iclass 19, count 0 2006.257.13:02:47.51#ibcon#about to write, iclass 19, count 0 2006.257.13:02:47.51#ibcon#wrote, iclass 19, count 0 2006.257.13:02:47.51#ibcon#about to read 3, iclass 19, count 0 2006.257.13:02:47.53#ibcon#read 3, iclass 19, count 0 2006.257.13:02:47.53#ibcon#about to read 4, iclass 19, count 0 2006.257.13:02:47.53#ibcon#read 4, iclass 19, count 0 2006.257.13:02:47.53#ibcon#about to read 5, iclass 19, count 0 2006.257.13:02:47.53#ibcon#read 5, iclass 19, count 0 2006.257.13:02:47.53#ibcon#about to read 6, iclass 19, count 0 2006.257.13:02:47.53#ibcon#read 6, iclass 19, count 0 2006.257.13:02:47.53#ibcon#end of sib2, iclass 19, count 0 2006.257.13:02:47.53#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:02:47.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:02:47.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:02:47.53#ibcon#*before write, iclass 19, count 0 2006.257.13:02:47.53#ibcon#enter sib2, iclass 19, count 0 2006.257.13:02:47.53#ibcon#flushed, iclass 19, count 0 2006.257.13:02:47.53#ibcon#about to write, iclass 19, count 0 2006.257.13:02:47.53#ibcon#wrote, iclass 19, count 0 2006.257.13:02:47.53#ibcon#about to read 3, iclass 19, count 0 2006.257.13:02:47.57#ibcon#read 3, iclass 19, count 0 2006.257.13:02:47.57#ibcon#about to read 4, iclass 19, count 0 2006.257.13:02:47.57#ibcon#read 4, iclass 19, count 0 2006.257.13:02:47.57#ibcon#about to read 5, iclass 19, count 0 2006.257.13:02:47.57#ibcon#read 5, iclass 19, count 0 2006.257.13:02:47.57#ibcon#about to read 6, iclass 19, count 0 2006.257.13:02:47.57#ibcon#read 6, iclass 19, count 0 2006.257.13:02:47.57#ibcon#end of sib2, iclass 19, count 0 2006.257.13:02:47.57#ibcon#*after write, iclass 19, count 0 2006.257.13:02:47.57#ibcon#*before return 0, iclass 19, count 0 2006.257.13:02:47.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:47.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:47.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:02:47.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:02:47.57$vck44/va=8,4 2006.257.13:02:47.57#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.13:02:47.57#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.13:02:47.57#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:47.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:02:47.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:02:47.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:02:47.63#ibcon#enter wrdev, iclass 21, count 2 2006.257.13:02:47.63#ibcon#first serial, iclass 21, count 2 2006.257.13:02:47.63#ibcon#enter sib2, iclass 21, count 2 2006.257.13:02:47.63#ibcon#flushed, iclass 21, count 2 2006.257.13:02:47.63#ibcon#about to write, iclass 21, count 2 2006.257.13:02:47.63#ibcon#wrote, iclass 21, count 2 2006.257.13:02:47.63#ibcon#about to read 3, iclass 21, count 2 2006.257.13:02:47.65#ibcon#read 3, iclass 21, count 2 2006.257.13:02:47.65#ibcon#about to read 4, iclass 21, count 2 2006.257.13:02:47.65#ibcon#read 4, iclass 21, count 2 2006.257.13:02:47.65#ibcon#about to read 5, iclass 21, count 2 2006.257.13:02:47.65#ibcon#read 5, iclass 21, count 2 2006.257.13:02:47.65#ibcon#about to read 6, iclass 21, count 2 2006.257.13:02:47.65#ibcon#read 6, iclass 21, count 2 2006.257.13:02:47.65#ibcon#end of sib2, iclass 21, count 2 2006.257.13:02:47.65#ibcon#*mode == 0, iclass 21, count 2 2006.257.13:02:47.65#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.13:02:47.65#ibcon#[25=AT08-04\r\n] 2006.257.13:02:47.65#ibcon#*before write, iclass 21, count 2 2006.257.13:02:47.65#ibcon#enter sib2, iclass 21, count 2 2006.257.13:02:47.65#ibcon#flushed, iclass 21, count 2 2006.257.13:02:47.65#ibcon#about to write, iclass 21, count 2 2006.257.13:02:47.65#ibcon#wrote, iclass 21, count 2 2006.257.13:02:47.65#ibcon#about to read 3, iclass 21, count 2 2006.257.13:02:47.68#ibcon#read 3, iclass 21, count 2 2006.257.13:02:47.68#ibcon#about to read 4, iclass 21, count 2 2006.257.13:02:47.68#ibcon#read 4, iclass 21, count 2 2006.257.13:02:47.68#ibcon#about to read 5, iclass 21, count 2 2006.257.13:02:47.68#ibcon#read 5, iclass 21, count 2 2006.257.13:02:47.68#ibcon#about to read 6, iclass 21, count 2 2006.257.13:02:47.68#ibcon#read 6, iclass 21, count 2 2006.257.13:02:47.68#ibcon#end of sib2, iclass 21, count 2 2006.257.13:02:47.68#ibcon#*after write, iclass 21, count 2 2006.257.13:02:47.68#ibcon#*before return 0, iclass 21, count 2 2006.257.13:02:47.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:02:47.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:02:47.68#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.13:02:47.68#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:47.68#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:02:47.80#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:02:47.80#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:02:47.80#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:02:47.80#ibcon#first serial, iclass 21, count 0 2006.257.13:02:47.80#ibcon#enter sib2, iclass 21, count 0 2006.257.13:02:47.80#ibcon#flushed, iclass 21, count 0 2006.257.13:02:47.80#ibcon#about to write, iclass 21, count 0 2006.257.13:02:47.80#ibcon#wrote, iclass 21, count 0 2006.257.13:02:47.80#ibcon#about to read 3, iclass 21, count 0 2006.257.13:02:47.82#ibcon#read 3, iclass 21, count 0 2006.257.13:02:47.82#ibcon#about to read 4, iclass 21, count 0 2006.257.13:02:47.82#ibcon#read 4, iclass 21, count 0 2006.257.13:02:47.82#ibcon#about to read 5, iclass 21, count 0 2006.257.13:02:47.82#ibcon#read 5, iclass 21, count 0 2006.257.13:02:47.82#ibcon#about to read 6, iclass 21, count 0 2006.257.13:02:47.82#ibcon#read 6, iclass 21, count 0 2006.257.13:02:47.82#ibcon#end of sib2, iclass 21, count 0 2006.257.13:02:47.82#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:02:47.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:02:47.82#ibcon#[25=USB\r\n] 2006.257.13:02:47.82#ibcon#*before write, iclass 21, count 0 2006.257.13:02:47.82#ibcon#enter sib2, iclass 21, count 0 2006.257.13:02:47.82#ibcon#flushed, iclass 21, count 0 2006.257.13:02:47.82#ibcon#about to write, iclass 21, count 0 2006.257.13:02:47.82#ibcon#wrote, iclass 21, count 0 2006.257.13:02:47.82#ibcon#about to read 3, iclass 21, count 0 2006.257.13:02:47.85#ibcon#read 3, iclass 21, count 0 2006.257.13:02:47.85#ibcon#about to read 4, iclass 21, count 0 2006.257.13:02:47.85#ibcon#read 4, iclass 21, count 0 2006.257.13:02:47.85#ibcon#about to read 5, iclass 21, count 0 2006.257.13:02:47.85#ibcon#read 5, iclass 21, count 0 2006.257.13:02:47.85#ibcon#about to read 6, iclass 21, count 0 2006.257.13:02:47.85#ibcon#read 6, iclass 21, count 0 2006.257.13:02:47.85#ibcon#end of sib2, iclass 21, count 0 2006.257.13:02:47.85#ibcon#*after write, iclass 21, count 0 2006.257.13:02:47.85#ibcon#*before return 0, iclass 21, count 0 2006.257.13:02:47.85#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:02:47.85#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:02:47.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:02:47.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:02:47.85$vck44/vblo=1,629.99 2006.257.13:02:47.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.13:02:47.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.13:02:47.85#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:47.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:47.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:47.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:47.85#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:02:47.85#ibcon#first serial, iclass 23, count 0 2006.257.13:02:47.85#ibcon#enter sib2, iclass 23, count 0 2006.257.13:02:47.85#ibcon#flushed, iclass 23, count 0 2006.257.13:02:47.85#ibcon#about to write, iclass 23, count 0 2006.257.13:02:47.85#ibcon#wrote, iclass 23, count 0 2006.257.13:02:47.85#ibcon#about to read 3, iclass 23, count 0 2006.257.13:02:47.87#ibcon#read 3, iclass 23, count 0 2006.257.13:02:47.87#ibcon#about to read 4, iclass 23, count 0 2006.257.13:02:47.87#ibcon#read 4, iclass 23, count 0 2006.257.13:02:47.87#ibcon#about to read 5, iclass 23, count 0 2006.257.13:02:47.87#ibcon#read 5, iclass 23, count 0 2006.257.13:02:47.87#ibcon#about to read 6, iclass 23, count 0 2006.257.13:02:47.87#ibcon#read 6, iclass 23, count 0 2006.257.13:02:47.87#ibcon#end of sib2, iclass 23, count 0 2006.257.13:02:47.87#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:02:47.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:02:47.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:02:47.87#ibcon#*before write, iclass 23, count 0 2006.257.13:02:47.87#ibcon#enter sib2, iclass 23, count 0 2006.257.13:02:47.87#ibcon#flushed, iclass 23, count 0 2006.257.13:02:47.87#ibcon#about to write, iclass 23, count 0 2006.257.13:02:47.87#ibcon#wrote, iclass 23, count 0 2006.257.13:02:47.87#ibcon#about to read 3, iclass 23, count 0 2006.257.13:02:47.91#ibcon#read 3, iclass 23, count 0 2006.257.13:02:47.91#ibcon#about to read 4, iclass 23, count 0 2006.257.13:02:47.91#ibcon#read 4, iclass 23, count 0 2006.257.13:02:47.91#ibcon#about to read 5, iclass 23, count 0 2006.257.13:02:47.91#ibcon#read 5, iclass 23, count 0 2006.257.13:02:47.91#ibcon#about to read 6, iclass 23, count 0 2006.257.13:02:47.91#ibcon#read 6, iclass 23, count 0 2006.257.13:02:47.91#ibcon#end of sib2, iclass 23, count 0 2006.257.13:02:47.91#ibcon#*after write, iclass 23, count 0 2006.257.13:02:47.91#ibcon#*before return 0, iclass 23, count 0 2006.257.13:02:47.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:47.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:02:47.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:02:47.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:02:47.91$vck44/vb=1,4 2006.257.13:02:47.91#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.13:02:47.91#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.13:02:47.91#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:47.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:47.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:47.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:47.91#ibcon#enter wrdev, iclass 25, count 2 2006.257.13:02:47.91#ibcon#first serial, iclass 25, count 2 2006.257.13:02:47.91#ibcon#enter sib2, iclass 25, count 2 2006.257.13:02:47.91#ibcon#flushed, iclass 25, count 2 2006.257.13:02:47.91#ibcon#about to write, iclass 25, count 2 2006.257.13:02:47.91#ibcon#wrote, iclass 25, count 2 2006.257.13:02:47.91#ibcon#about to read 3, iclass 25, count 2 2006.257.13:02:47.93#ibcon#read 3, iclass 25, count 2 2006.257.13:02:47.93#ibcon#about to read 4, iclass 25, count 2 2006.257.13:02:47.93#ibcon#read 4, iclass 25, count 2 2006.257.13:02:47.93#ibcon#about to read 5, iclass 25, count 2 2006.257.13:02:47.93#ibcon#read 5, iclass 25, count 2 2006.257.13:02:47.93#ibcon#about to read 6, iclass 25, count 2 2006.257.13:02:47.93#ibcon#read 6, iclass 25, count 2 2006.257.13:02:47.93#ibcon#end of sib2, iclass 25, count 2 2006.257.13:02:47.93#ibcon#*mode == 0, iclass 25, count 2 2006.257.13:02:47.93#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.13:02:47.93#ibcon#[27=AT01-04\r\n] 2006.257.13:02:47.93#ibcon#*before write, iclass 25, count 2 2006.257.13:02:47.93#ibcon#enter sib2, iclass 25, count 2 2006.257.13:02:47.93#ibcon#flushed, iclass 25, count 2 2006.257.13:02:47.93#ibcon#about to write, iclass 25, count 2 2006.257.13:02:47.93#ibcon#wrote, iclass 25, count 2 2006.257.13:02:47.93#ibcon#about to read 3, iclass 25, count 2 2006.257.13:02:47.96#ibcon#read 3, iclass 25, count 2 2006.257.13:02:47.96#ibcon#about to read 4, iclass 25, count 2 2006.257.13:02:47.96#ibcon#read 4, iclass 25, count 2 2006.257.13:02:47.96#ibcon#about to read 5, iclass 25, count 2 2006.257.13:02:47.96#ibcon#read 5, iclass 25, count 2 2006.257.13:02:47.96#ibcon#about to read 6, iclass 25, count 2 2006.257.13:02:47.96#ibcon#read 6, iclass 25, count 2 2006.257.13:02:47.96#ibcon#end of sib2, iclass 25, count 2 2006.257.13:02:47.96#ibcon#*after write, iclass 25, count 2 2006.257.13:02:47.96#ibcon#*before return 0, iclass 25, count 2 2006.257.13:02:47.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:47.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:02:47.96#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.13:02:47.96#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:47.96#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:48.08#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:48.08#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:48.08#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:02:48.08#ibcon#first serial, iclass 25, count 0 2006.257.13:02:48.08#ibcon#enter sib2, iclass 25, count 0 2006.257.13:02:48.08#ibcon#flushed, iclass 25, count 0 2006.257.13:02:48.08#ibcon#about to write, iclass 25, count 0 2006.257.13:02:48.08#ibcon#wrote, iclass 25, count 0 2006.257.13:02:48.08#ibcon#about to read 3, iclass 25, count 0 2006.257.13:02:48.10#ibcon#read 3, iclass 25, count 0 2006.257.13:02:48.10#ibcon#about to read 4, iclass 25, count 0 2006.257.13:02:48.10#ibcon#read 4, iclass 25, count 0 2006.257.13:02:48.10#ibcon#about to read 5, iclass 25, count 0 2006.257.13:02:48.10#ibcon#read 5, iclass 25, count 0 2006.257.13:02:48.10#ibcon#about to read 6, iclass 25, count 0 2006.257.13:02:48.10#ibcon#read 6, iclass 25, count 0 2006.257.13:02:48.10#ibcon#end of sib2, iclass 25, count 0 2006.257.13:02:48.10#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:02:48.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:02:48.10#ibcon#[27=USB\r\n] 2006.257.13:02:48.10#ibcon#*before write, iclass 25, count 0 2006.257.13:02:48.10#ibcon#enter sib2, iclass 25, count 0 2006.257.13:02:48.10#ibcon#flushed, iclass 25, count 0 2006.257.13:02:48.10#ibcon#about to write, iclass 25, count 0 2006.257.13:02:48.10#ibcon#wrote, iclass 25, count 0 2006.257.13:02:48.10#ibcon#about to read 3, iclass 25, count 0 2006.257.13:02:48.13#ibcon#read 3, iclass 25, count 0 2006.257.13:02:48.13#ibcon#about to read 4, iclass 25, count 0 2006.257.13:02:48.13#ibcon#read 4, iclass 25, count 0 2006.257.13:02:48.13#ibcon#about to read 5, iclass 25, count 0 2006.257.13:02:48.13#ibcon#read 5, iclass 25, count 0 2006.257.13:02:48.13#ibcon#about to read 6, iclass 25, count 0 2006.257.13:02:48.13#ibcon#read 6, iclass 25, count 0 2006.257.13:02:48.13#ibcon#end of sib2, iclass 25, count 0 2006.257.13:02:48.13#ibcon#*after write, iclass 25, count 0 2006.257.13:02:48.13#ibcon#*before return 0, iclass 25, count 0 2006.257.13:02:48.13#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:48.13#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:02:48.13#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:02:48.13#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:02:48.13$vck44/vblo=2,634.99 2006.257.13:02:48.13#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.13:02:48.13#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.13:02:48.13#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:48.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:02:48.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:02:48.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:02:48.13#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:02:48.13#ibcon#first serial, iclass 27, count 0 2006.257.13:02:48.13#ibcon#enter sib2, iclass 27, count 0 2006.257.13:02:48.13#ibcon#flushed, iclass 27, count 0 2006.257.13:02:48.13#ibcon#about to write, iclass 27, count 0 2006.257.13:02:48.13#ibcon#wrote, iclass 27, count 0 2006.257.13:02:48.13#ibcon#about to read 3, iclass 27, count 0 2006.257.13:02:48.15#ibcon#read 3, iclass 27, count 0 2006.257.13:02:48.15#ibcon#about to read 4, iclass 27, count 0 2006.257.13:02:48.15#ibcon#read 4, iclass 27, count 0 2006.257.13:02:48.15#ibcon#about to read 5, iclass 27, count 0 2006.257.13:02:48.15#ibcon#read 5, iclass 27, count 0 2006.257.13:02:48.15#ibcon#about to read 6, iclass 27, count 0 2006.257.13:02:48.15#ibcon#read 6, iclass 27, count 0 2006.257.13:02:48.15#ibcon#end of sib2, iclass 27, count 0 2006.257.13:02:48.15#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:02:48.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:02:48.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:02:48.15#ibcon#*before write, iclass 27, count 0 2006.257.13:02:48.15#ibcon#enter sib2, iclass 27, count 0 2006.257.13:02:48.15#ibcon#flushed, iclass 27, count 0 2006.257.13:02:48.15#ibcon#about to write, iclass 27, count 0 2006.257.13:02:48.15#ibcon#wrote, iclass 27, count 0 2006.257.13:02:48.15#ibcon#about to read 3, iclass 27, count 0 2006.257.13:02:48.19#ibcon#read 3, iclass 27, count 0 2006.257.13:02:48.19#ibcon#about to read 4, iclass 27, count 0 2006.257.13:02:48.19#ibcon#read 4, iclass 27, count 0 2006.257.13:02:48.19#ibcon#about to read 5, iclass 27, count 0 2006.257.13:02:48.19#ibcon#read 5, iclass 27, count 0 2006.257.13:02:48.19#ibcon#about to read 6, iclass 27, count 0 2006.257.13:02:48.19#ibcon#read 6, iclass 27, count 0 2006.257.13:02:48.19#ibcon#end of sib2, iclass 27, count 0 2006.257.13:02:48.19#ibcon#*after write, iclass 27, count 0 2006.257.13:02:48.19#ibcon#*before return 0, iclass 27, count 0 2006.257.13:02:48.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:02:48.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:02:48.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:02:48.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:02:48.19$vck44/vb=2,5 2006.257.13:02:48.19#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.13:02:48.19#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.13:02:48.19#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:48.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:02:48.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:02:48.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:02:48.25#ibcon#enter wrdev, iclass 29, count 2 2006.257.13:02:48.25#ibcon#first serial, iclass 29, count 2 2006.257.13:02:48.25#ibcon#enter sib2, iclass 29, count 2 2006.257.13:02:48.25#ibcon#flushed, iclass 29, count 2 2006.257.13:02:48.25#ibcon#about to write, iclass 29, count 2 2006.257.13:02:48.25#ibcon#wrote, iclass 29, count 2 2006.257.13:02:48.25#ibcon#about to read 3, iclass 29, count 2 2006.257.13:02:48.27#ibcon#read 3, iclass 29, count 2 2006.257.13:02:48.27#ibcon#about to read 4, iclass 29, count 2 2006.257.13:02:48.27#ibcon#read 4, iclass 29, count 2 2006.257.13:02:48.27#ibcon#about to read 5, iclass 29, count 2 2006.257.13:02:48.27#ibcon#read 5, iclass 29, count 2 2006.257.13:02:48.27#ibcon#about to read 6, iclass 29, count 2 2006.257.13:02:48.27#ibcon#read 6, iclass 29, count 2 2006.257.13:02:48.27#ibcon#end of sib2, iclass 29, count 2 2006.257.13:02:48.27#ibcon#*mode == 0, iclass 29, count 2 2006.257.13:02:48.27#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.13:02:48.27#ibcon#[27=AT02-05\r\n] 2006.257.13:02:48.27#ibcon#*before write, iclass 29, count 2 2006.257.13:02:48.27#ibcon#enter sib2, iclass 29, count 2 2006.257.13:02:48.27#ibcon#flushed, iclass 29, count 2 2006.257.13:02:48.27#ibcon#about to write, iclass 29, count 2 2006.257.13:02:48.27#ibcon#wrote, iclass 29, count 2 2006.257.13:02:48.27#ibcon#about to read 3, iclass 29, count 2 2006.257.13:02:48.30#ibcon#read 3, iclass 29, count 2 2006.257.13:02:48.30#ibcon#about to read 4, iclass 29, count 2 2006.257.13:02:48.30#ibcon#read 4, iclass 29, count 2 2006.257.13:02:48.30#ibcon#about to read 5, iclass 29, count 2 2006.257.13:02:48.30#ibcon#read 5, iclass 29, count 2 2006.257.13:02:48.30#ibcon#about to read 6, iclass 29, count 2 2006.257.13:02:48.30#ibcon#read 6, iclass 29, count 2 2006.257.13:02:48.30#ibcon#end of sib2, iclass 29, count 2 2006.257.13:02:48.30#ibcon#*after write, iclass 29, count 2 2006.257.13:02:48.30#ibcon#*before return 0, iclass 29, count 2 2006.257.13:02:48.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:02:48.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:02:48.30#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.13:02:48.30#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:48.30#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:02:48.42#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:02:48.42#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:02:48.42#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:02:48.42#ibcon#first serial, iclass 29, count 0 2006.257.13:02:48.42#ibcon#enter sib2, iclass 29, count 0 2006.257.13:02:48.42#ibcon#flushed, iclass 29, count 0 2006.257.13:02:48.42#ibcon#about to write, iclass 29, count 0 2006.257.13:02:48.42#ibcon#wrote, iclass 29, count 0 2006.257.13:02:48.42#ibcon#about to read 3, iclass 29, count 0 2006.257.13:02:48.44#ibcon#read 3, iclass 29, count 0 2006.257.13:02:48.44#ibcon#about to read 4, iclass 29, count 0 2006.257.13:02:48.44#ibcon#read 4, iclass 29, count 0 2006.257.13:02:48.44#ibcon#about to read 5, iclass 29, count 0 2006.257.13:02:48.44#ibcon#read 5, iclass 29, count 0 2006.257.13:02:48.44#ibcon#about to read 6, iclass 29, count 0 2006.257.13:02:48.44#ibcon#read 6, iclass 29, count 0 2006.257.13:02:48.44#ibcon#end of sib2, iclass 29, count 0 2006.257.13:02:48.44#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:02:48.44#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:02:48.44#ibcon#[27=USB\r\n] 2006.257.13:02:48.44#ibcon#*before write, iclass 29, count 0 2006.257.13:02:48.44#ibcon#enter sib2, iclass 29, count 0 2006.257.13:02:48.44#ibcon#flushed, iclass 29, count 0 2006.257.13:02:48.44#ibcon#about to write, iclass 29, count 0 2006.257.13:02:48.44#ibcon#wrote, iclass 29, count 0 2006.257.13:02:48.44#ibcon#about to read 3, iclass 29, count 0 2006.257.13:02:48.47#ibcon#read 3, iclass 29, count 0 2006.257.13:02:48.47#ibcon#about to read 4, iclass 29, count 0 2006.257.13:02:48.47#ibcon#read 4, iclass 29, count 0 2006.257.13:02:48.47#ibcon#about to read 5, iclass 29, count 0 2006.257.13:02:48.47#ibcon#read 5, iclass 29, count 0 2006.257.13:02:48.47#ibcon#about to read 6, iclass 29, count 0 2006.257.13:02:48.47#ibcon#read 6, iclass 29, count 0 2006.257.13:02:48.47#ibcon#end of sib2, iclass 29, count 0 2006.257.13:02:48.47#ibcon#*after write, iclass 29, count 0 2006.257.13:02:48.47#ibcon#*before return 0, iclass 29, count 0 2006.257.13:02:48.47#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:02:48.47#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:02:48.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:02:48.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:02:48.47$vck44/vblo=3,649.99 2006.257.13:02:48.47#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.13:02:48.47#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.13:02:48.47#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:48.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:48.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:48.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:48.47#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:02:48.47#ibcon#first serial, iclass 31, count 0 2006.257.13:02:48.47#ibcon#enter sib2, iclass 31, count 0 2006.257.13:02:48.47#ibcon#flushed, iclass 31, count 0 2006.257.13:02:48.47#ibcon#about to write, iclass 31, count 0 2006.257.13:02:48.47#ibcon#wrote, iclass 31, count 0 2006.257.13:02:48.47#ibcon#about to read 3, iclass 31, count 0 2006.257.13:02:48.49#ibcon#read 3, iclass 31, count 0 2006.257.13:02:48.49#ibcon#about to read 4, iclass 31, count 0 2006.257.13:02:48.49#ibcon#read 4, iclass 31, count 0 2006.257.13:02:48.49#ibcon#about to read 5, iclass 31, count 0 2006.257.13:02:48.49#ibcon#read 5, iclass 31, count 0 2006.257.13:02:48.49#ibcon#about to read 6, iclass 31, count 0 2006.257.13:02:48.49#ibcon#read 6, iclass 31, count 0 2006.257.13:02:48.49#ibcon#end of sib2, iclass 31, count 0 2006.257.13:02:48.49#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:02:48.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:02:48.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:02:48.49#ibcon#*before write, iclass 31, count 0 2006.257.13:02:48.49#ibcon#enter sib2, iclass 31, count 0 2006.257.13:02:48.49#ibcon#flushed, iclass 31, count 0 2006.257.13:02:48.49#ibcon#about to write, iclass 31, count 0 2006.257.13:02:48.49#ibcon#wrote, iclass 31, count 0 2006.257.13:02:48.49#ibcon#about to read 3, iclass 31, count 0 2006.257.13:02:48.53#ibcon#read 3, iclass 31, count 0 2006.257.13:02:48.53#ibcon#about to read 4, iclass 31, count 0 2006.257.13:02:48.53#ibcon#read 4, iclass 31, count 0 2006.257.13:02:48.53#ibcon#about to read 5, iclass 31, count 0 2006.257.13:02:48.53#ibcon#read 5, iclass 31, count 0 2006.257.13:02:48.53#ibcon#about to read 6, iclass 31, count 0 2006.257.13:02:48.53#ibcon#read 6, iclass 31, count 0 2006.257.13:02:48.53#ibcon#end of sib2, iclass 31, count 0 2006.257.13:02:48.53#ibcon#*after write, iclass 31, count 0 2006.257.13:02:48.53#ibcon#*before return 0, iclass 31, count 0 2006.257.13:02:48.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:48.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:02:48.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:02:48.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:02:48.53$vck44/vb=3,4 2006.257.13:02:48.53#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.13:02:48.53#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.13:02:48.53#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:48.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:48.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:48.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:48.59#ibcon#enter wrdev, iclass 33, count 2 2006.257.13:02:48.59#ibcon#first serial, iclass 33, count 2 2006.257.13:02:48.59#ibcon#enter sib2, iclass 33, count 2 2006.257.13:02:48.59#ibcon#flushed, iclass 33, count 2 2006.257.13:02:48.59#ibcon#about to write, iclass 33, count 2 2006.257.13:02:48.59#ibcon#wrote, iclass 33, count 2 2006.257.13:02:48.59#ibcon#about to read 3, iclass 33, count 2 2006.257.13:02:48.61#ibcon#read 3, iclass 33, count 2 2006.257.13:02:48.61#ibcon#about to read 4, iclass 33, count 2 2006.257.13:02:48.61#ibcon#read 4, iclass 33, count 2 2006.257.13:02:48.61#ibcon#about to read 5, iclass 33, count 2 2006.257.13:02:48.61#ibcon#read 5, iclass 33, count 2 2006.257.13:02:48.61#ibcon#about to read 6, iclass 33, count 2 2006.257.13:02:48.61#ibcon#read 6, iclass 33, count 2 2006.257.13:02:48.61#ibcon#end of sib2, iclass 33, count 2 2006.257.13:02:48.61#ibcon#*mode == 0, iclass 33, count 2 2006.257.13:02:48.61#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.13:02:48.61#ibcon#[27=AT03-04\r\n] 2006.257.13:02:48.61#ibcon#*before write, iclass 33, count 2 2006.257.13:02:48.61#ibcon#enter sib2, iclass 33, count 2 2006.257.13:02:48.61#ibcon#flushed, iclass 33, count 2 2006.257.13:02:48.61#ibcon#about to write, iclass 33, count 2 2006.257.13:02:48.61#ibcon#wrote, iclass 33, count 2 2006.257.13:02:48.61#ibcon#about to read 3, iclass 33, count 2 2006.257.13:02:48.64#ibcon#read 3, iclass 33, count 2 2006.257.13:02:48.64#ibcon#about to read 4, iclass 33, count 2 2006.257.13:02:48.64#ibcon#read 4, iclass 33, count 2 2006.257.13:02:48.64#ibcon#about to read 5, iclass 33, count 2 2006.257.13:02:48.64#ibcon#read 5, iclass 33, count 2 2006.257.13:02:48.64#ibcon#about to read 6, iclass 33, count 2 2006.257.13:02:48.64#ibcon#read 6, iclass 33, count 2 2006.257.13:02:48.64#ibcon#end of sib2, iclass 33, count 2 2006.257.13:02:48.64#ibcon#*after write, iclass 33, count 2 2006.257.13:02:48.64#ibcon#*before return 0, iclass 33, count 2 2006.257.13:02:48.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:48.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:02:48.64#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.13:02:48.64#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:48.64#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:48.76#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:48.76#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:48.76#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:02:48.76#ibcon#first serial, iclass 33, count 0 2006.257.13:02:48.76#ibcon#enter sib2, iclass 33, count 0 2006.257.13:02:48.76#ibcon#flushed, iclass 33, count 0 2006.257.13:02:48.76#ibcon#about to write, iclass 33, count 0 2006.257.13:02:48.76#ibcon#wrote, iclass 33, count 0 2006.257.13:02:48.76#ibcon#about to read 3, iclass 33, count 0 2006.257.13:02:48.78#ibcon#read 3, iclass 33, count 0 2006.257.13:02:48.78#ibcon#about to read 4, iclass 33, count 0 2006.257.13:02:48.78#ibcon#read 4, iclass 33, count 0 2006.257.13:02:48.78#ibcon#about to read 5, iclass 33, count 0 2006.257.13:02:48.78#ibcon#read 5, iclass 33, count 0 2006.257.13:02:48.78#ibcon#about to read 6, iclass 33, count 0 2006.257.13:02:48.78#ibcon#read 6, iclass 33, count 0 2006.257.13:02:48.78#ibcon#end of sib2, iclass 33, count 0 2006.257.13:02:48.78#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:02:48.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:02:48.78#ibcon#[27=USB\r\n] 2006.257.13:02:48.78#ibcon#*before write, iclass 33, count 0 2006.257.13:02:48.78#ibcon#enter sib2, iclass 33, count 0 2006.257.13:02:48.78#ibcon#flushed, iclass 33, count 0 2006.257.13:02:48.78#ibcon#about to write, iclass 33, count 0 2006.257.13:02:48.78#ibcon#wrote, iclass 33, count 0 2006.257.13:02:48.78#ibcon#about to read 3, iclass 33, count 0 2006.257.13:02:48.81#ibcon#read 3, iclass 33, count 0 2006.257.13:02:48.81#ibcon#about to read 4, iclass 33, count 0 2006.257.13:02:48.81#ibcon#read 4, iclass 33, count 0 2006.257.13:02:48.81#ibcon#about to read 5, iclass 33, count 0 2006.257.13:02:48.81#ibcon#read 5, iclass 33, count 0 2006.257.13:02:48.81#ibcon#about to read 6, iclass 33, count 0 2006.257.13:02:48.81#ibcon#read 6, iclass 33, count 0 2006.257.13:02:48.81#ibcon#end of sib2, iclass 33, count 0 2006.257.13:02:48.81#ibcon#*after write, iclass 33, count 0 2006.257.13:02:48.81#ibcon#*before return 0, iclass 33, count 0 2006.257.13:02:48.81#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:48.81#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:02:48.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:02:48.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:02:48.81$vck44/vblo=4,679.99 2006.257.13:02:48.81#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.13:02:48.81#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.13:02:48.81#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:48.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:48.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:48.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:48.81#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:02:48.81#ibcon#first serial, iclass 35, count 0 2006.257.13:02:48.81#ibcon#enter sib2, iclass 35, count 0 2006.257.13:02:48.81#ibcon#flushed, iclass 35, count 0 2006.257.13:02:48.81#ibcon#about to write, iclass 35, count 0 2006.257.13:02:48.81#ibcon#wrote, iclass 35, count 0 2006.257.13:02:48.81#ibcon#about to read 3, iclass 35, count 0 2006.257.13:02:48.83#ibcon#read 3, iclass 35, count 0 2006.257.13:02:48.83#ibcon#about to read 4, iclass 35, count 0 2006.257.13:02:48.83#ibcon#read 4, iclass 35, count 0 2006.257.13:02:48.83#ibcon#about to read 5, iclass 35, count 0 2006.257.13:02:48.83#ibcon#read 5, iclass 35, count 0 2006.257.13:02:48.83#ibcon#about to read 6, iclass 35, count 0 2006.257.13:02:48.83#ibcon#read 6, iclass 35, count 0 2006.257.13:02:48.83#ibcon#end of sib2, iclass 35, count 0 2006.257.13:02:48.83#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:02:48.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:02:48.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:02:48.83#ibcon#*before write, iclass 35, count 0 2006.257.13:02:48.83#ibcon#enter sib2, iclass 35, count 0 2006.257.13:02:48.83#ibcon#flushed, iclass 35, count 0 2006.257.13:02:48.83#ibcon#about to write, iclass 35, count 0 2006.257.13:02:48.83#ibcon#wrote, iclass 35, count 0 2006.257.13:02:48.83#ibcon#about to read 3, iclass 35, count 0 2006.257.13:02:48.87#ibcon#read 3, iclass 35, count 0 2006.257.13:02:48.87#ibcon#about to read 4, iclass 35, count 0 2006.257.13:02:48.87#ibcon#read 4, iclass 35, count 0 2006.257.13:02:48.87#ibcon#about to read 5, iclass 35, count 0 2006.257.13:02:48.87#ibcon#read 5, iclass 35, count 0 2006.257.13:02:48.87#ibcon#about to read 6, iclass 35, count 0 2006.257.13:02:48.87#ibcon#read 6, iclass 35, count 0 2006.257.13:02:48.87#ibcon#end of sib2, iclass 35, count 0 2006.257.13:02:48.87#ibcon#*after write, iclass 35, count 0 2006.257.13:02:48.87#ibcon#*before return 0, iclass 35, count 0 2006.257.13:02:48.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:48.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:02:48.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:02:48.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:02:48.87$vck44/vb=4,5 2006.257.13:02:48.87#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.13:02:48.87#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.13:02:48.87#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:48.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:48.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:48.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:48.93#ibcon#enter wrdev, iclass 37, count 2 2006.257.13:02:48.93#ibcon#first serial, iclass 37, count 2 2006.257.13:02:48.93#ibcon#enter sib2, iclass 37, count 2 2006.257.13:02:48.93#ibcon#flushed, iclass 37, count 2 2006.257.13:02:48.93#ibcon#about to write, iclass 37, count 2 2006.257.13:02:48.93#ibcon#wrote, iclass 37, count 2 2006.257.13:02:48.93#ibcon#about to read 3, iclass 37, count 2 2006.257.13:02:48.95#ibcon#read 3, iclass 37, count 2 2006.257.13:02:48.95#ibcon#about to read 4, iclass 37, count 2 2006.257.13:02:48.95#ibcon#read 4, iclass 37, count 2 2006.257.13:02:48.95#ibcon#about to read 5, iclass 37, count 2 2006.257.13:02:48.95#ibcon#read 5, iclass 37, count 2 2006.257.13:02:48.95#ibcon#about to read 6, iclass 37, count 2 2006.257.13:02:48.95#ibcon#read 6, iclass 37, count 2 2006.257.13:02:48.95#ibcon#end of sib2, iclass 37, count 2 2006.257.13:02:48.95#ibcon#*mode == 0, iclass 37, count 2 2006.257.13:02:48.95#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.13:02:48.95#ibcon#[27=AT04-05\r\n] 2006.257.13:02:48.95#ibcon#*before write, iclass 37, count 2 2006.257.13:02:48.95#ibcon#enter sib2, iclass 37, count 2 2006.257.13:02:48.95#ibcon#flushed, iclass 37, count 2 2006.257.13:02:48.95#ibcon#about to write, iclass 37, count 2 2006.257.13:02:48.95#ibcon#wrote, iclass 37, count 2 2006.257.13:02:48.95#ibcon#about to read 3, iclass 37, count 2 2006.257.13:02:48.98#ibcon#read 3, iclass 37, count 2 2006.257.13:02:48.98#ibcon#about to read 4, iclass 37, count 2 2006.257.13:02:48.98#ibcon#read 4, iclass 37, count 2 2006.257.13:02:48.98#ibcon#about to read 5, iclass 37, count 2 2006.257.13:02:48.98#ibcon#read 5, iclass 37, count 2 2006.257.13:02:48.98#ibcon#about to read 6, iclass 37, count 2 2006.257.13:02:48.98#ibcon#read 6, iclass 37, count 2 2006.257.13:02:48.98#ibcon#end of sib2, iclass 37, count 2 2006.257.13:02:48.98#ibcon#*after write, iclass 37, count 2 2006.257.13:02:48.98#ibcon#*before return 0, iclass 37, count 2 2006.257.13:02:48.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:48.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:02:48.98#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.13:02:48.98#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:48.98#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:49.10#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:49.10#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:49.10#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:02:49.10#ibcon#first serial, iclass 37, count 0 2006.257.13:02:49.10#ibcon#enter sib2, iclass 37, count 0 2006.257.13:02:49.10#ibcon#flushed, iclass 37, count 0 2006.257.13:02:49.10#ibcon#about to write, iclass 37, count 0 2006.257.13:02:49.10#ibcon#wrote, iclass 37, count 0 2006.257.13:02:49.10#ibcon#about to read 3, iclass 37, count 0 2006.257.13:02:49.12#ibcon#read 3, iclass 37, count 0 2006.257.13:02:49.12#ibcon#about to read 4, iclass 37, count 0 2006.257.13:02:49.12#ibcon#read 4, iclass 37, count 0 2006.257.13:02:49.12#ibcon#about to read 5, iclass 37, count 0 2006.257.13:02:49.12#ibcon#read 5, iclass 37, count 0 2006.257.13:02:49.12#ibcon#about to read 6, iclass 37, count 0 2006.257.13:02:49.12#ibcon#read 6, iclass 37, count 0 2006.257.13:02:49.12#ibcon#end of sib2, iclass 37, count 0 2006.257.13:02:49.12#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:02:49.12#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:02:49.12#ibcon#[27=USB\r\n] 2006.257.13:02:49.12#ibcon#*before write, iclass 37, count 0 2006.257.13:02:49.12#ibcon#enter sib2, iclass 37, count 0 2006.257.13:02:49.12#ibcon#flushed, iclass 37, count 0 2006.257.13:02:49.12#ibcon#about to write, iclass 37, count 0 2006.257.13:02:49.12#ibcon#wrote, iclass 37, count 0 2006.257.13:02:49.12#ibcon#about to read 3, iclass 37, count 0 2006.257.13:02:49.15#ibcon#read 3, iclass 37, count 0 2006.257.13:02:49.15#ibcon#about to read 4, iclass 37, count 0 2006.257.13:02:49.15#ibcon#read 4, iclass 37, count 0 2006.257.13:02:49.15#ibcon#about to read 5, iclass 37, count 0 2006.257.13:02:49.15#ibcon#read 5, iclass 37, count 0 2006.257.13:02:49.15#ibcon#about to read 6, iclass 37, count 0 2006.257.13:02:49.15#ibcon#read 6, iclass 37, count 0 2006.257.13:02:49.15#ibcon#end of sib2, iclass 37, count 0 2006.257.13:02:49.15#ibcon#*after write, iclass 37, count 0 2006.257.13:02:49.15#ibcon#*before return 0, iclass 37, count 0 2006.257.13:02:49.15#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:49.15#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:02:49.15#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:02:49.15#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:02:49.15$vck44/vblo=5,709.99 2006.257.13:02:49.15#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:02:49.15#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:02:49.15#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:49.15#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:49.15#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:49.15#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:49.15#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:02:49.15#ibcon#first serial, iclass 39, count 0 2006.257.13:02:49.15#ibcon#enter sib2, iclass 39, count 0 2006.257.13:02:49.15#ibcon#flushed, iclass 39, count 0 2006.257.13:02:49.15#ibcon#about to write, iclass 39, count 0 2006.257.13:02:49.15#ibcon#wrote, iclass 39, count 0 2006.257.13:02:49.15#ibcon#about to read 3, iclass 39, count 0 2006.257.13:02:49.17#ibcon#read 3, iclass 39, count 0 2006.257.13:02:49.17#ibcon#about to read 4, iclass 39, count 0 2006.257.13:02:49.17#ibcon#read 4, iclass 39, count 0 2006.257.13:02:49.17#ibcon#about to read 5, iclass 39, count 0 2006.257.13:02:49.17#ibcon#read 5, iclass 39, count 0 2006.257.13:02:49.17#ibcon#about to read 6, iclass 39, count 0 2006.257.13:02:49.17#ibcon#read 6, iclass 39, count 0 2006.257.13:02:49.17#ibcon#end of sib2, iclass 39, count 0 2006.257.13:02:49.17#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:02:49.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:02:49.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:02:49.17#ibcon#*before write, iclass 39, count 0 2006.257.13:02:49.17#ibcon#enter sib2, iclass 39, count 0 2006.257.13:02:49.17#ibcon#flushed, iclass 39, count 0 2006.257.13:02:49.17#ibcon#about to write, iclass 39, count 0 2006.257.13:02:49.17#ibcon#wrote, iclass 39, count 0 2006.257.13:02:49.17#ibcon#about to read 3, iclass 39, count 0 2006.257.13:02:49.21#ibcon#read 3, iclass 39, count 0 2006.257.13:02:49.21#ibcon#about to read 4, iclass 39, count 0 2006.257.13:02:49.21#ibcon#read 4, iclass 39, count 0 2006.257.13:02:49.21#ibcon#about to read 5, iclass 39, count 0 2006.257.13:02:49.21#ibcon#read 5, iclass 39, count 0 2006.257.13:02:49.21#ibcon#about to read 6, iclass 39, count 0 2006.257.13:02:49.21#ibcon#read 6, iclass 39, count 0 2006.257.13:02:49.21#ibcon#end of sib2, iclass 39, count 0 2006.257.13:02:49.21#ibcon#*after write, iclass 39, count 0 2006.257.13:02:49.21#ibcon#*before return 0, iclass 39, count 0 2006.257.13:02:49.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:49.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:02:49.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:02:49.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:02:49.21$vck44/vb=5,4 2006.257.13:02:49.21#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.13:02:49.21#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.13:02:49.21#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:49.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:49.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:49.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:49.27#ibcon#enter wrdev, iclass 3, count 2 2006.257.13:02:49.27#ibcon#first serial, iclass 3, count 2 2006.257.13:02:49.27#ibcon#enter sib2, iclass 3, count 2 2006.257.13:02:49.27#ibcon#flushed, iclass 3, count 2 2006.257.13:02:49.27#ibcon#about to write, iclass 3, count 2 2006.257.13:02:49.27#ibcon#wrote, iclass 3, count 2 2006.257.13:02:49.27#ibcon#about to read 3, iclass 3, count 2 2006.257.13:02:49.29#ibcon#read 3, iclass 3, count 2 2006.257.13:02:49.29#ibcon#about to read 4, iclass 3, count 2 2006.257.13:02:49.29#ibcon#read 4, iclass 3, count 2 2006.257.13:02:49.29#ibcon#about to read 5, iclass 3, count 2 2006.257.13:02:49.29#ibcon#read 5, iclass 3, count 2 2006.257.13:02:49.29#ibcon#about to read 6, iclass 3, count 2 2006.257.13:02:49.29#ibcon#read 6, iclass 3, count 2 2006.257.13:02:49.29#ibcon#end of sib2, iclass 3, count 2 2006.257.13:02:49.29#ibcon#*mode == 0, iclass 3, count 2 2006.257.13:02:49.29#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.13:02:49.29#ibcon#[27=AT05-04\r\n] 2006.257.13:02:49.29#ibcon#*before write, iclass 3, count 2 2006.257.13:02:49.29#ibcon#enter sib2, iclass 3, count 2 2006.257.13:02:49.29#ibcon#flushed, iclass 3, count 2 2006.257.13:02:49.29#ibcon#about to write, iclass 3, count 2 2006.257.13:02:49.29#ibcon#wrote, iclass 3, count 2 2006.257.13:02:49.29#ibcon#about to read 3, iclass 3, count 2 2006.257.13:02:49.32#ibcon#read 3, iclass 3, count 2 2006.257.13:02:49.32#ibcon#about to read 4, iclass 3, count 2 2006.257.13:02:49.32#ibcon#read 4, iclass 3, count 2 2006.257.13:02:49.32#ibcon#about to read 5, iclass 3, count 2 2006.257.13:02:49.32#ibcon#read 5, iclass 3, count 2 2006.257.13:02:49.32#ibcon#about to read 6, iclass 3, count 2 2006.257.13:02:49.32#ibcon#read 6, iclass 3, count 2 2006.257.13:02:49.32#ibcon#end of sib2, iclass 3, count 2 2006.257.13:02:49.32#ibcon#*after write, iclass 3, count 2 2006.257.13:02:49.32#ibcon#*before return 0, iclass 3, count 2 2006.257.13:02:49.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:49.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:02:49.32#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.13:02:49.32#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:49.32#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:49.44#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:49.44#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:49.44#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:02:49.44#ibcon#first serial, iclass 3, count 0 2006.257.13:02:49.44#ibcon#enter sib2, iclass 3, count 0 2006.257.13:02:49.44#ibcon#flushed, iclass 3, count 0 2006.257.13:02:49.44#ibcon#about to write, iclass 3, count 0 2006.257.13:02:49.44#ibcon#wrote, iclass 3, count 0 2006.257.13:02:49.44#ibcon#about to read 3, iclass 3, count 0 2006.257.13:02:49.46#ibcon#read 3, iclass 3, count 0 2006.257.13:02:49.46#ibcon#about to read 4, iclass 3, count 0 2006.257.13:02:49.46#ibcon#read 4, iclass 3, count 0 2006.257.13:02:49.46#ibcon#about to read 5, iclass 3, count 0 2006.257.13:02:49.46#ibcon#read 5, iclass 3, count 0 2006.257.13:02:49.46#ibcon#about to read 6, iclass 3, count 0 2006.257.13:02:49.46#ibcon#read 6, iclass 3, count 0 2006.257.13:02:49.46#ibcon#end of sib2, iclass 3, count 0 2006.257.13:02:49.46#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:02:49.46#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:02:49.46#ibcon#[27=USB\r\n] 2006.257.13:02:49.46#ibcon#*before write, iclass 3, count 0 2006.257.13:02:49.46#ibcon#enter sib2, iclass 3, count 0 2006.257.13:02:49.46#ibcon#flushed, iclass 3, count 0 2006.257.13:02:49.46#ibcon#about to write, iclass 3, count 0 2006.257.13:02:49.46#ibcon#wrote, iclass 3, count 0 2006.257.13:02:49.46#ibcon#about to read 3, iclass 3, count 0 2006.257.13:02:49.49#ibcon#read 3, iclass 3, count 0 2006.257.13:02:49.49#ibcon#about to read 4, iclass 3, count 0 2006.257.13:02:49.49#ibcon#read 4, iclass 3, count 0 2006.257.13:02:49.49#ibcon#about to read 5, iclass 3, count 0 2006.257.13:02:49.49#ibcon#read 5, iclass 3, count 0 2006.257.13:02:49.49#ibcon#about to read 6, iclass 3, count 0 2006.257.13:02:49.49#ibcon#read 6, iclass 3, count 0 2006.257.13:02:49.49#ibcon#end of sib2, iclass 3, count 0 2006.257.13:02:49.49#ibcon#*after write, iclass 3, count 0 2006.257.13:02:49.49#ibcon#*before return 0, iclass 3, count 0 2006.257.13:02:49.49#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:49.49#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:02:49.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:02:49.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:02:49.49$vck44/vblo=6,719.99 2006.257.13:02:49.49#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.13:02:49.49#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.13:02:49.49#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:49.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:49.49#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:49.49#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:49.49#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:02:49.49#ibcon#first serial, iclass 5, count 0 2006.257.13:02:49.49#ibcon#enter sib2, iclass 5, count 0 2006.257.13:02:49.49#ibcon#flushed, iclass 5, count 0 2006.257.13:02:49.49#ibcon#about to write, iclass 5, count 0 2006.257.13:02:49.49#ibcon#wrote, iclass 5, count 0 2006.257.13:02:49.49#ibcon#about to read 3, iclass 5, count 0 2006.257.13:02:49.51#ibcon#read 3, iclass 5, count 0 2006.257.13:02:49.51#ibcon#about to read 4, iclass 5, count 0 2006.257.13:02:49.51#ibcon#read 4, iclass 5, count 0 2006.257.13:02:49.51#ibcon#about to read 5, iclass 5, count 0 2006.257.13:02:49.51#ibcon#read 5, iclass 5, count 0 2006.257.13:02:49.51#ibcon#about to read 6, iclass 5, count 0 2006.257.13:02:49.51#ibcon#read 6, iclass 5, count 0 2006.257.13:02:49.51#ibcon#end of sib2, iclass 5, count 0 2006.257.13:02:49.51#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:02:49.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:02:49.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:02:49.51#ibcon#*before write, iclass 5, count 0 2006.257.13:02:49.51#ibcon#enter sib2, iclass 5, count 0 2006.257.13:02:49.51#ibcon#flushed, iclass 5, count 0 2006.257.13:02:49.51#ibcon#about to write, iclass 5, count 0 2006.257.13:02:49.51#ibcon#wrote, iclass 5, count 0 2006.257.13:02:49.51#ibcon#about to read 3, iclass 5, count 0 2006.257.13:02:49.55#ibcon#read 3, iclass 5, count 0 2006.257.13:02:49.55#ibcon#about to read 4, iclass 5, count 0 2006.257.13:02:49.55#ibcon#read 4, iclass 5, count 0 2006.257.13:02:49.55#ibcon#about to read 5, iclass 5, count 0 2006.257.13:02:49.55#ibcon#read 5, iclass 5, count 0 2006.257.13:02:49.55#ibcon#about to read 6, iclass 5, count 0 2006.257.13:02:49.55#ibcon#read 6, iclass 5, count 0 2006.257.13:02:49.55#ibcon#end of sib2, iclass 5, count 0 2006.257.13:02:49.55#ibcon#*after write, iclass 5, count 0 2006.257.13:02:49.55#ibcon#*before return 0, iclass 5, count 0 2006.257.13:02:49.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:49.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:02:49.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:02:49.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:02:49.55$vck44/vb=6,4 2006.257.13:02:49.55#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.13:02:49.55#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.13:02:49.55#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:49.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:49.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:49.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:49.61#ibcon#enter wrdev, iclass 7, count 2 2006.257.13:02:49.61#ibcon#first serial, iclass 7, count 2 2006.257.13:02:49.61#ibcon#enter sib2, iclass 7, count 2 2006.257.13:02:49.61#ibcon#flushed, iclass 7, count 2 2006.257.13:02:49.61#ibcon#about to write, iclass 7, count 2 2006.257.13:02:49.61#ibcon#wrote, iclass 7, count 2 2006.257.13:02:49.61#ibcon#about to read 3, iclass 7, count 2 2006.257.13:02:49.63#ibcon#read 3, iclass 7, count 2 2006.257.13:02:49.63#ibcon#about to read 4, iclass 7, count 2 2006.257.13:02:49.63#ibcon#read 4, iclass 7, count 2 2006.257.13:02:49.63#ibcon#about to read 5, iclass 7, count 2 2006.257.13:02:49.63#ibcon#read 5, iclass 7, count 2 2006.257.13:02:49.63#ibcon#about to read 6, iclass 7, count 2 2006.257.13:02:49.63#ibcon#read 6, iclass 7, count 2 2006.257.13:02:49.63#ibcon#end of sib2, iclass 7, count 2 2006.257.13:02:49.63#ibcon#*mode == 0, iclass 7, count 2 2006.257.13:02:49.63#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.13:02:49.63#ibcon#[27=AT06-04\r\n] 2006.257.13:02:49.63#ibcon#*before write, iclass 7, count 2 2006.257.13:02:49.63#ibcon#enter sib2, iclass 7, count 2 2006.257.13:02:49.63#ibcon#flushed, iclass 7, count 2 2006.257.13:02:49.63#ibcon#about to write, iclass 7, count 2 2006.257.13:02:49.63#ibcon#wrote, iclass 7, count 2 2006.257.13:02:49.63#ibcon#about to read 3, iclass 7, count 2 2006.257.13:02:49.66#ibcon#read 3, iclass 7, count 2 2006.257.13:02:49.66#ibcon#about to read 4, iclass 7, count 2 2006.257.13:02:49.66#ibcon#read 4, iclass 7, count 2 2006.257.13:02:49.66#ibcon#about to read 5, iclass 7, count 2 2006.257.13:02:49.66#ibcon#read 5, iclass 7, count 2 2006.257.13:02:49.66#ibcon#about to read 6, iclass 7, count 2 2006.257.13:02:49.66#ibcon#read 6, iclass 7, count 2 2006.257.13:02:49.66#ibcon#end of sib2, iclass 7, count 2 2006.257.13:02:49.66#ibcon#*after write, iclass 7, count 2 2006.257.13:02:49.66#ibcon#*before return 0, iclass 7, count 2 2006.257.13:02:49.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:49.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:02:49.66#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.13:02:49.66#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:49.66#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:49.78#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:49.78#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:49.78#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:02:49.78#ibcon#first serial, iclass 7, count 0 2006.257.13:02:49.78#ibcon#enter sib2, iclass 7, count 0 2006.257.13:02:49.78#ibcon#flushed, iclass 7, count 0 2006.257.13:02:49.78#ibcon#about to write, iclass 7, count 0 2006.257.13:02:49.78#ibcon#wrote, iclass 7, count 0 2006.257.13:02:49.78#ibcon#about to read 3, iclass 7, count 0 2006.257.13:02:49.80#ibcon#read 3, iclass 7, count 0 2006.257.13:02:49.80#ibcon#about to read 4, iclass 7, count 0 2006.257.13:02:49.80#ibcon#read 4, iclass 7, count 0 2006.257.13:02:49.80#ibcon#about to read 5, iclass 7, count 0 2006.257.13:02:49.80#ibcon#read 5, iclass 7, count 0 2006.257.13:02:49.80#ibcon#about to read 6, iclass 7, count 0 2006.257.13:02:49.80#ibcon#read 6, iclass 7, count 0 2006.257.13:02:49.80#ibcon#end of sib2, iclass 7, count 0 2006.257.13:02:49.80#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:02:49.80#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:02:49.80#ibcon#[27=USB\r\n] 2006.257.13:02:49.80#ibcon#*before write, iclass 7, count 0 2006.257.13:02:49.80#ibcon#enter sib2, iclass 7, count 0 2006.257.13:02:49.80#ibcon#flushed, iclass 7, count 0 2006.257.13:02:49.80#ibcon#about to write, iclass 7, count 0 2006.257.13:02:49.80#ibcon#wrote, iclass 7, count 0 2006.257.13:02:49.80#ibcon#about to read 3, iclass 7, count 0 2006.257.13:02:49.83#ibcon#read 3, iclass 7, count 0 2006.257.13:02:49.83#ibcon#about to read 4, iclass 7, count 0 2006.257.13:02:49.83#ibcon#read 4, iclass 7, count 0 2006.257.13:02:49.83#ibcon#about to read 5, iclass 7, count 0 2006.257.13:02:49.83#ibcon#read 5, iclass 7, count 0 2006.257.13:02:49.83#ibcon#about to read 6, iclass 7, count 0 2006.257.13:02:49.83#ibcon#read 6, iclass 7, count 0 2006.257.13:02:49.83#ibcon#end of sib2, iclass 7, count 0 2006.257.13:02:49.83#ibcon#*after write, iclass 7, count 0 2006.257.13:02:49.83#ibcon#*before return 0, iclass 7, count 0 2006.257.13:02:49.83#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:49.83#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:02:49.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:02:49.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:02:49.83$vck44/vblo=7,734.99 2006.257.13:02:49.83#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.13:02:49.83#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.13:02:49.83#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:49.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:49.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:49.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:49.83#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:02:49.83#ibcon#first serial, iclass 11, count 0 2006.257.13:02:49.83#ibcon#enter sib2, iclass 11, count 0 2006.257.13:02:49.83#ibcon#flushed, iclass 11, count 0 2006.257.13:02:49.83#ibcon#about to write, iclass 11, count 0 2006.257.13:02:49.83#ibcon#wrote, iclass 11, count 0 2006.257.13:02:49.83#ibcon#about to read 3, iclass 11, count 0 2006.257.13:02:49.85#ibcon#read 3, iclass 11, count 0 2006.257.13:02:49.85#ibcon#about to read 4, iclass 11, count 0 2006.257.13:02:49.85#ibcon#read 4, iclass 11, count 0 2006.257.13:02:49.85#ibcon#about to read 5, iclass 11, count 0 2006.257.13:02:49.85#ibcon#read 5, iclass 11, count 0 2006.257.13:02:49.85#ibcon#about to read 6, iclass 11, count 0 2006.257.13:02:49.85#ibcon#read 6, iclass 11, count 0 2006.257.13:02:49.85#ibcon#end of sib2, iclass 11, count 0 2006.257.13:02:49.85#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:02:49.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:02:49.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:02:49.85#ibcon#*before write, iclass 11, count 0 2006.257.13:02:49.85#ibcon#enter sib2, iclass 11, count 0 2006.257.13:02:49.85#ibcon#flushed, iclass 11, count 0 2006.257.13:02:49.85#ibcon#about to write, iclass 11, count 0 2006.257.13:02:49.85#ibcon#wrote, iclass 11, count 0 2006.257.13:02:49.85#ibcon#about to read 3, iclass 11, count 0 2006.257.13:02:49.89#ibcon#read 3, iclass 11, count 0 2006.257.13:02:49.89#ibcon#about to read 4, iclass 11, count 0 2006.257.13:02:49.89#ibcon#read 4, iclass 11, count 0 2006.257.13:02:49.89#ibcon#about to read 5, iclass 11, count 0 2006.257.13:02:49.89#ibcon#read 5, iclass 11, count 0 2006.257.13:02:49.89#ibcon#about to read 6, iclass 11, count 0 2006.257.13:02:49.89#ibcon#read 6, iclass 11, count 0 2006.257.13:02:49.89#ibcon#end of sib2, iclass 11, count 0 2006.257.13:02:49.89#ibcon#*after write, iclass 11, count 0 2006.257.13:02:49.89#ibcon#*before return 0, iclass 11, count 0 2006.257.13:02:49.89#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:49.89#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:02:49.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:02:49.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:02:49.89$vck44/vb=7,4 2006.257.13:02:49.89#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.13:02:49.89#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.13:02:49.89#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:49.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:49.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:49.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:49.95#ibcon#enter wrdev, iclass 13, count 2 2006.257.13:02:49.95#ibcon#first serial, iclass 13, count 2 2006.257.13:02:49.95#ibcon#enter sib2, iclass 13, count 2 2006.257.13:02:49.95#ibcon#flushed, iclass 13, count 2 2006.257.13:02:49.95#ibcon#about to write, iclass 13, count 2 2006.257.13:02:49.95#ibcon#wrote, iclass 13, count 2 2006.257.13:02:49.95#ibcon#about to read 3, iclass 13, count 2 2006.257.13:02:49.97#ibcon#read 3, iclass 13, count 2 2006.257.13:02:49.97#ibcon#about to read 4, iclass 13, count 2 2006.257.13:02:49.97#ibcon#read 4, iclass 13, count 2 2006.257.13:02:49.97#ibcon#about to read 5, iclass 13, count 2 2006.257.13:02:49.97#ibcon#read 5, iclass 13, count 2 2006.257.13:02:49.97#ibcon#about to read 6, iclass 13, count 2 2006.257.13:02:49.97#ibcon#read 6, iclass 13, count 2 2006.257.13:02:49.97#ibcon#end of sib2, iclass 13, count 2 2006.257.13:02:49.97#ibcon#*mode == 0, iclass 13, count 2 2006.257.13:02:49.97#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.13:02:49.97#ibcon#[27=AT07-04\r\n] 2006.257.13:02:49.97#ibcon#*before write, iclass 13, count 2 2006.257.13:02:49.97#ibcon#enter sib2, iclass 13, count 2 2006.257.13:02:49.97#ibcon#flushed, iclass 13, count 2 2006.257.13:02:49.97#ibcon#about to write, iclass 13, count 2 2006.257.13:02:49.97#ibcon#wrote, iclass 13, count 2 2006.257.13:02:49.97#ibcon#about to read 3, iclass 13, count 2 2006.257.13:02:50.00#ibcon#read 3, iclass 13, count 2 2006.257.13:02:50.00#ibcon#about to read 4, iclass 13, count 2 2006.257.13:02:50.00#ibcon#read 4, iclass 13, count 2 2006.257.13:02:50.00#ibcon#about to read 5, iclass 13, count 2 2006.257.13:02:50.00#ibcon#read 5, iclass 13, count 2 2006.257.13:02:50.00#ibcon#about to read 6, iclass 13, count 2 2006.257.13:02:50.00#ibcon#read 6, iclass 13, count 2 2006.257.13:02:50.00#ibcon#end of sib2, iclass 13, count 2 2006.257.13:02:50.00#ibcon#*after write, iclass 13, count 2 2006.257.13:02:50.00#ibcon#*before return 0, iclass 13, count 2 2006.257.13:02:50.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:50.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:02:50.00#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.13:02:50.00#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:50.00#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:50.12#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:50.12#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:50.12#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:02:50.12#ibcon#first serial, iclass 13, count 0 2006.257.13:02:50.12#ibcon#enter sib2, iclass 13, count 0 2006.257.13:02:50.12#ibcon#flushed, iclass 13, count 0 2006.257.13:02:50.12#ibcon#about to write, iclass 13, count 0 2006.257.13:02:50.12#ibcon#wrote, iclass 13, count 0 2006.257.13:02:50.12#ibcon#about to read 3, iclass 13, count 0 2006.257.13:02:50.14#ibcon#read 3, iclass 13, count 0 2006.257.13:02:50.14#ibcon#about to read 4, iclass 13, count 0 2006.257.13:02:50.14#ibcon#read 4, iclass 13, count 0 2006.257.13:02:50.14#ibcon#about to read 5, iclass 13, count 0 2006.257.13:02:50.14#ibcon#read 5, iclass 13, count 0 2006.257.13:02:50.14#ibcon#about to read 6, iclass 13, count 0 2006.257.13:02:50.14#ibcon#read 6, iclass 13, count 0 2006.257.13:02:50.14#ibcon#end of sib2, iclass 13, count 0 2006.257.13:02:50.14#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:02:50.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:02:50.14#ibcon#[27=USB\r\n] 2006.257.13:02:50.14#ibcon#*before write, iclass 13, count 0 2006.257.13:02:50.14#ibcon#enter sib2, iclass 13, count 0 2006.257.13:02:50.14#ibcon#flushed, iclass 13, count 0 2006.257.13:02:50.14#ibcon#about to write, iclass 13, count 0 2006.257.13:02:50.14#ibcon#wrote, iclass 13, count 0 2006.257.13:02:50.14#ibcon#about to read 3, iclass 13, count 0 2006.257.13:02:50.17#ibcon#read 3, iclass 13, count 0 2006.257.13:02:50.17#ibcon#about to read 4, iclass 13, count 0 2006.257.13:02:50.17#ibcon#read 4, iclass 13, count 0 2006.257.13:02:50.17#ibcon#about to read 5, iclass 13, count 0 2006.257.13:02:50.17#ibcon#read 5, iclass 13, count 0 2006.257.13:02:50.17#ibcon#about to read 6, iclass 13, count 0 2006.257.13:02:50.17#ibcon#read 6, iclass 13, count 0 2006.257.13:02:50.17#ibcon#end of sib2, iclass 13, count 0 2006.257.13:02:50.17#ibcon#*after write, iclass 13, count 0 2006.257.13:02:50.17#ibcon#*before return 0, iclass 13, count 0 2006.257.13:02:50.17#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:50.17#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:02:50.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:02:50.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:02:50.17$vck44/vblo=8,744.99 2006.257.13:02:50.17#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.13:02:50.17#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.13:02:50.17#ibcon#ireg 17 cls_cnt 0 2006.257.13:02:50.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:50.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:50.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:50.17#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:02:50.17#ibcon#first serial, iclass 15, count 0 2006.257.13:02:50.17#ibcon#enter sib2, iclass 15, count 0 2006.257.13:02:50.17#ibcon#flushed, iclass 15, count 0 2006.257.13:02:50.17#ibcon#about to write, iclass 15, count 0 2006.257.13:02:50.17#ibcon#wrote, iclass 15, count 0 2006.257.13:02:50.17#ibcon#about to read 3, iclass 15, count 0 2006.257.13:02:50.19#ibcon#read 3, iclass 15, count 0 2006.257.13:02:50.19#ibcon#about to read 4, iclass 15, count 0 2006.257.13:02:50.19#ibcon#read 4, iclass 15, count 0 2006.257.13:02:50.19#ibcon#about to read 5, iclass 15, count 0 2006.257.13:02:50.19#ibcon#read 5, iclass 15, count 0 2006.257.13:02:50.19#ibcon#about to read 6, iclass 15, count 0 2006.257.13:02:50.19#ibcon#read 6, iclass 15, count 0 2006.257.13:02:50.19#ibcon#end of sib2, iclass 15, count 0 2006.257.13:02:50.19#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:02:50.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:02:50.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:02:50.19#ibcon#*before write, iclass 15, count 0 2006.257.13:02:50.19#ibcon#enter sib2, iclass 15, count 0 2006.257.13:02:50.19#ibcon#flushed, iclass 15, count 0 2006.257.13:02:50.19#ibcon#about to write, iclass 15, count 0 2006.257.13:02:50.19#ibcon#wrote, iclass 15, count 0 2006.257.13:02:50.19#ibcon#about to read 3, iclass 15, count 0 2006.257.13:02:50.23#ibcon#read 3, iclass 15, count 0 2006.257.13:02:50.23#ibcon#about to read 4, iclass 15, count 0 2006.257.13:02:50.23#ibcon#read 4, iclass 15, count 0 2006.257.13:02:50.23#ibcon#about to read 5, iclass 15, count 0 2006.257.13:02:50.23#ibcon#read 5, iclass 15, count 0 2006.257.13:02:50.23#ibcon#about to read 6, iclass 15, count 0 2006.257.13:02:50.23#ibcon#read 6, iclass 15, count 0 2006.257.13:02:50.23#ibcon#end of sib2, iclass 15, count 0 2006.257.13:02:50.23#ibcon#*after write, iclass 15, count 0 2006.257.13:02:50.23#ibcon#*before return 0, iclass 15, count 0 2006.257.13:02:50.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:50.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:02:50.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:02:50.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:02:50.23$vck44/vb=8,4 2006.257.13:02:50.23#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.13:02:50.23#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.13:02:50.23#ibcon#ireg 11 cls_cnt 2 2006.257.13:02:50.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:50.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:50.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:50.29#ibcon#enter wrdev, iclass 17, count 2 2006.257.13:02:50.29#ibcon#first serial, iclass 17, count 2 2006.257.13:02:50.29#ibcon#enter sib2, iclass 17, count 2 2006.257.13:02:50.29#ibcon#flushed, iclass 17, count 2 2006.257.13:02:50.29#ibcon#about to write, iclass 17, count 2 2006.257.13:02:50.29#ibcon#wrote, iclass 17, count 2 2006.257.13:02:50.29#ibcon#about to read 3, iclass 17, count 2 2006.257.13:02:50.31#ibcon#read 3, iclass 17, count 2 2006.257.13:02:50.31#ibcon#about to read 4, iclass 17, count 2 2006.257.13:02:50.31#ibcon#read 4, iclass 17, count 2 2006.257.13:02:50.31#ibcon#about to read 5, iclass 17, count 2 2006.257.13:02:50.31#ibcon#read 5, iclass 17, count 2 2006.257.13:02:50.31#ibcon#about to read 6, iclass 17, count 2 2006.257.13:02:50.31#ibcon#read 6, iclass 17, count 2 2006.257.13:02:50.31#ibcon#end of sib2, iclass 17, count 2 2006.257.13:02:50.31#ibcon#*mode == 0, iclass 17, count 2 2006.257.13:02:50.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.13:02:50.31#ibcon#[27=AT08-04\r\n] 2006.257.13:02:50.31#ibcon#*before write, iclass 17, count 2 2006.257.13:02:50.31#ibcon#enter sib2, iclass 17, count 2 2006.257.13:02:50.31#ibcon#flushed, iclass 17, count 2 2006.257.13:02:50.31#ibcon#about to write, iclass 17, count 2 2006.257.13:02:50.31#ibcon#wrote, iclass 17, count 2 2006.257.13:02:50.31#ibcon#about to read 3, iclass 17, count 2 2006.257.13:02:50.34#ibcon#read 3, iclass 17, count 2 2006.257.13:02:50.34#ibcon#about to read 4, iclass 17, count 2 2006.257.13:02:50.34#ibcon#read 4, iclass 17, count 2 2006.257.13:02:50.34#ibcon#about to read 5, iclass 17, count 2 2006.257.13:02:50.34#ibcon#read 5, iclass 17, count 2 2006.257.13:02:50.34#ibcon#about to read 6, iclass 17, count 2 2006.257.13:02:50.34#ibcon#read 6, iclass 17, count 2 2006.257.13:02:50.34#ibcon#end of sib2, iclass 17, count 2 2006.257.13:02:50.34#ibcon#*after write, iclass 17, count 2 2006.257.13:02:50.34#ibcon#*before return 0, iclass 17, count 2 2006.257.13:02:50.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:50.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:02:50.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.13:02:50.34#ibcon#ireg 7 cls_cnt 0 2006.257.13:02:50.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:50.46#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:50.46#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:50.46#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:02:50.46#ibcon#first serial, iclass 17, count 0 2006.257.13:02:50.46#ibcon#enter sib2, iclass 17, count 0 2006.257.13:02:50.46#ibcon#flushed, iclass 17, count 0 2006.257.13:02:50.46#ibcon#about to write, iclass 17, count 0 2006.257.13:02:50.46#ibcon#wrote, iclass 17, count 0 2006.257.13:02:50.46#ibcon#about to read 3, iclass 17, count 0 2006.257.13:02:50.48#ibcon#read 3, iclass 17, count 0 2006.257.13:02:50.48#ibcon#about to read 4, iclass 17, count 0 2006.257.13:02:50.48#ibcon#read 4, iclass 17, count 0 2006.257.13:02:50.48#ibcon#about to read 5, iclass 17, count 0 2006.257.13:02:50.48#ibcon#read 5, iclass 17, count 0 2006.257.13:02:50.48#ibcon#about to read 6, iclass 17, count 0 2006.257.13:02:50.48#ibcon#read 6, iclass 17, count 0 2006.257.13:02:50.48#ibcon#end of sib2, iclass 17, count 0 2006.257.13:02:50.48#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:02:50.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:02:50.48#ibcon#[27=USB\r\n] 2006.257.13:02:50.48#ibcon#*before write, iclass 17, count 0 2006.257.13:02:50.48#ibcon#enter sib2, iclass 17, count 0 2006.257.13:02:50.48#ibcon#flushed, iclass 17, count 0 2006.257.13:02:50.48#ibcon#about to write, iclass 17, count 0 2006.257.13:02:50.48#ibcon#wrote, iclass 17, count 0 2006.257.13:02:50.48#ibcon#about to read 3, iclass 17, count 0 2006.257.13:02:50.51#ibcon#read 3, iclass 17, count 0 2006.257.13:02:50.51#ibcon#about to read 4, iclass 17, count 0 2006.257.13:02:50.51#ibcon#read 4, iclass 17, count 0 2006.257.13:02:50.51#ibcon#about to read 5, iclass 17, count 0 2006.257.13:02:50.51#ibcon#read 5, iclass 17, count 0 2006.257.13:02:50.51#ibcon#about to read 6, iclass 17, count 0 2006.257.13:02:50.51#ibcon#read 6, iclass 17, count 0 2006.257.13:02:50.51#ibcon#end of sib2, iclass 17, count 0 2006.257.13:02:50.51#ibcon#*after write, iclass 17, count 0 2006.257.13:02:50.51#ibcon#*before return 0, iclass 17, count 0 2006.257.13:02:50.51#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:50.51#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:02:50.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:02:50.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:02:50.51$vck44/vabw=wide 2006.257.13:02:50.51#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.13:02:50.51#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.13:02:50.51#ibcon#ireg 8 cls_cnt 0 2006.257.13:02:50.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:50.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:50.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:50.51#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:02:50.51#ibcon#first serial, iclass 19, count 0 2006.257.13:02:50.51#ibcon#enter sib2, iclass 19, count 0 2006.257.13:02:50.51#ibcon#flushed, iclass 19, count 0 2006.257.13:02:50.51#ibcon#about to write, iclass 19, count 0 2006.257.13:02:50.51#ibcon#wrote, iclass 19, count 0 2006.257.13:02:50.51#ibcon#about to read 3, iclass 19, count 0 2006.257.13:02:50.53#ibcon#read 3, iclass 19, count 0 2006.257.13:02:50.53#ibcon#about to read 4, iclass 19, count 0 2006.257.13:02:50.53#ibcon#read 4, iclass 19, count 0 2006.257.13:02:50.53#ibcon#about to read 5, iclass 19, count 0 2006.257.13:02:50.53#ibcon#read 5, iclass 19, count 0 2006.257.13:02:50.53#ibcon#about to read 6, iclass 19, count 0 2006.257.13:02:50.53#ibcon#read 6, iclass 19, count 0 2006.257.13:02:50.53#ibcon#end of sib2, iclass 19, count 0 2006.257.13:02:50.53#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:02:50.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:02:50.53#ibcon#[25=BW32\r\n] 2006.257.13:02:50.53#ibcon#*before write, iclass 19, count 0 2006.257.13:02:50.53#ibcon#enter sib2, iclass 19, count 0 2006.257.13:02:50.53#ibcon#flushed, iclass 19, count 0 2006.257.13:02:50.53#ibcon#about to write, iclass 19, count 0 2006.257.13:02:50.53#ibcon#wrote, iclass 19, count 0 2006.257.13:02:50.53#ibcon#about to read 3, iclass 19, count 0 2006.257.13:02:50.56#ibcon#read 3, iclass 19, count 0 2006.257.13:02:50.56#ibcon#about to read 4, iclass 19, count 0 2006.257.13:02:50.56#ibcon#read 4, iclass 19, count 0 2006.257.13:02:50.56#ibcon#about to read 5, iclass 19, count 0 2006.257.13:02:50.56#ibcon#read 5, iclass 19, count 0 2006.257.13:02:50.56#ibcon#about to read 6, iclass 19, count 0 2006.257.13:02:50.56#ibcon#read 6, iclass 19, count 0 2006.257.13:02:50.56#ibcon#end of sib2, iclass 19, count 0 2006.257.13:02:50.56#ibcon#*after write, iclass 19, count 0 2006.257.13:02:50.56#ibcon#*before return 0, iclass 19, count 0 2006.257.13:02:50.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:50.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:02:50.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:02:50.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:02:50.56$vck44/vbbw=wide 2006.257.13:02:50.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.13:02:50.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.13:02:50.56#ibcon#ireg 8 cls_cnt 0 2006.257.13:02:50.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:02:50.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:02:50.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:02:50.63#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:02:50.63#ibcon#first serial, iclass 21, count 0 2006.257.13:02:50.63#ibcon#enter sib2, iclass 21, count 0 2006.257.13:02:50.63#ibcon#flushed, iclass 21, count 0 2006.257.13:02:50.63#ibcon#about to write, iclass 21, count 0 2006.257.13:02:50.63#ibcon#wrote, iclass 21, count 0 2006.257.13:02:50.63#ibcon#about to read 3, iclass 21, count 0 2006.257.13:02:50.65#ibcon#read 3, iclass 21, count 0 2006.257.13:02:50.65#ibcon#about to read 4, iclass 21, count 0 2006.257.13:02:50.65#ibcon#read 4, iclass 21, count 0 2006.257.13:02:50.65#ibcon#about to read 5, iclass 21, count 0 2006.257.13:02:50.65#ibcon#read 5, iclass 21, count 0 2006.257.13:02:50.65#ibcon#about to read 6, iclass 21, count 0 2006.257.13:02:50.65#ibcon#read 6, iclass 21, count 0 2006.257.13:02:50.65#ibcon#end of sib2, iclass 21, count 0 2006.257.13:02:50.65#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:02:50.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:02:50.65#ibcon#[27=BW32\r\n] 2006.257.13:02:50.65#ibcon#*before write, iclass 21, count 0 2006.257.13:02:50.65#ibcon#enter sib2, iclass 21, count 0 2006.257.13:02:50.65#ibcon#flushed, iclass 21, count 0 2006.257.13:02:50.65#ibcon#about to write, iclass 21, count 0 2006.257.13:02:50.65#ibcon#wrote, iclass 21, count 0 2006.257.13:02:50.65#ibcon#about to read 3, iclass 21, count 0 2006.257.13:02:50.68#ibcon#read 3, iclass 21, count 0 2006.257.13:02:50.68#ibcon#about to read 4, iclass 21, count 0 2006.257.13:02:50.68#ibcon#read 4, iclass 21, count 0 2006.257.13:02:50.68#ibcon#about to read 5, iclass 21, count 0 2006.257.13:02:50.68#ibcon#read 5, iclass 21, count 0 2006.257.13:02:50.68#ibcon#about to read 6, iclass 21, count 0 2006.257.13:02:50.68#ibcon#read 6, iclass 21, count 0 2006.257.13:02:50.68#ibcon#end of sib2, iclass 21, count 0 2006.257.13:02:50.68#ibcon#*after write, iclass 21, count 0 2006.257.13:02:50.68#ibcon#*before return 0, iclass 21, count 0 2006.257.13:02:50.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:02:50.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:02:50.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:02:50.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:02:50.68$setupk4/ifdk4 2006.257.13:02:50.68$ifdk4/lo= 2006.257.13:02:50.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:02:50.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:02:50.68$ifdk4/patch= 2006.257.13:02:50.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:02:50.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:02:50.68$setupk4/!*+20s 2006.257.13:02:55.47#abcon#<5=/14 1.9 5.0 17.72 961013.8\r\n> 2006.257.13:02:55.49#abcon#{5=INTERFACE CLEAR} 2006.257.13:02:55.55#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:02:56.14#trakl#Source acquired 2006.257.13:02:58.14#flagr#flagr/antenna,acquired 2006.257.13:03:05.19$setupk4/"tpicd 2006.257.13:03:05.19$setupk4/echo=off 2006.257.13:03:05.19$setupk4/xlog=off 2006.257.13:03:05.19:!2006.257.13:07:41 2006.257.13:07:41.00:preob 2006.257.13:07:41.14/onsource/TRACKING 2006.257.13:07:41.14:!2006.257.13:07:51 2006.257.13:07:51.00:"tape 2006.257.13:07:51.00:"st=record 2006.257.13:07:51.00:data_valid=on 2006.257.13:07:51.00:midob 2006.257.13:07:52.14/onsource/TRACKING 2006.257.13:07:52.14/wx/17.71,1013.8,96 2006.257.13:07:52.19/cable/+6.4799E-03 2006.257.13:07:53.28/va/01,08,usb,yes,31,33 2006.257.13:07:53.28/va/02,07,usb,yes,33,34 2006.257.13:07:53.28/va/03,08,usb,yes,30,32 2006.257.13:07:53.28/va/04,07,usb,yes,34,36 2006.257.13:07:53.28/va/05,04,usb,yes,31,31 2006.257.13:07:53.28/va/06,04,usb,yes,34,34 2006.257.13:07:53.28/va/07,04,usb,yes,35,36 2006.257.13:07:53.28/va/08,04,usb,yes,29,36 2006.257.13:07:53.51/valo/01,524.99,yes,locked 2006.257.13:07:53.51/valo/02,534.99,yes,locked 2006.257.13:07:53.51/valo/03,564.99,yes,locked 2006.257.13:07:53.51/valo/04,624.99,yes,locked 2006.257.13:07:53.51/valo/05,734.99,yes,locked 2006.257.13:07:53.51/valo/06,814.99,yes,locked 2006.257.13:07:53.51/valo/07,864.99,yes,locked 2006.257.13:07:53.51/valo/08,884.99,yes,locked 2006.257.13:07:54.60/vb/01,04,usb,yes,31,28 2006.257.13:07:54.60/vb/02,05,usb,yes,29,29 2006.257.13:07:54.60/vb/03,04,usb,yes,30,33 2006.257.13:07:54.60/vb/04,05,usb,yes,30,29 2006.257.13:07:54.60/vb/05,04,usb,yes,27,29 2006.257.13:07:54.60/vb/06,04,usb,yes,31,27 2006.257.13:07:54.60/vb/07,04,usb,yes,31,31 2006.257.13:07:54.60/vb/08,04,usb,yes,28,32 2006.257.13:07:54.83/vblo/01,629.99,yes,locked 2006.257.13:07:54.83/vblo/02,634.99,yes,locked 2006.257.13:07:54.83/vblo/03,649.99,yes,locked 2006.257.13:07:54.83/vblo/04,679.99,yes,locked 2006.257.13:07:54.83/vblo/05,709.99,yes,locked 2006.257.13:07:54.83/vblo/06,719.99,yes,locked 2006.257.13:07:54.83/vblo/07,734.99,yes,locked 2006.257.13:07:54.83/vblo/08,744.99,yes,locked 2006.257.13:07:54.98/vabw/8 2006.257.13:07:55.13/vbbw/8 2006.257.13:07:55.27/xfe/off,on,15.5 2006.257.13:07:55.64/ifatt/23,28,28,28 2006.257.13:07:56.07/fmout-gps/S +4.60E-07 2006.257.13:07:56.11:!2006.257.13:10:11 2006.257.13:10:11.00:data_valid=off 2006.257.13:10:11.00:"et 2006.257.13:10:11.00:!+3s 2006.257.13:10:14.01:"tape 2006.257.13:10:14.01:postob 2006.257.13:10:14.24/cable/+6.4825E-03 2006.257.13:10:14.24/wx/17.70,1013.7,97 2006.257.13:10:15.07/fmout-gps/S +4.63E-07 2006.257.13:10:15.07:scan_name=257-1312,jd0609,40 2006.257.13:10:15.07:source=2134+00,213638.59,004154.2,2000.0,ccw 2006.257.13:10:16.14#flagr#flagr/antenna,new-source 2006.257.13:10:16.14:checkk5 2006.257.13:10:16.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:10:17.03/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:10:17.42/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:10:17.83/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:10:18.21/chk_obsdata//k5ts1/T2571307??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.13:10:18.60/chk_obsdata//k5ts2/T2571307??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.13:10:19.00/chk_obsdata//k5ts3/T2571307??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.13:10:19.42/chk_obsdata//k5ts4/T2571307??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.13:10:20.13/k5log//k5ts1_log_newline 2006.257.13:10:20.85/k5log//k5ts2_log_newline 2006.257.13:10:21.57/k5log//k5ts3_log_newline 2006.257.13:10:22.28/k5log//k5ts4_log_newline 2006.257.13:10:22.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:10:22.31:setupk4=1 2006.257.13:10:22.31$setupk4/echo=on 2006.257.13:10:22.31$setupk4/pcalon 2006.257.13:10:22.31$pcalon/"no phase cal control is implemented here 2006.257.13:10:22.31$setupk4/"tpicd=stop 2006.257.13:10:22.31$setupk4/"rec=synch_on 2006.257.13:10:22.31$setupk4/"rec_mode=128 2006.257.13:10:22.31$setupk4/!* 2006.257.13:10:22.31$setupk4/recpk4 2006.257.13:10:22.31$recpk4/recpatch= 2006.257.13:10:22.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:10:22.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:10:22.31$setupk4/vck44 2006.257.13:10:22.31$vck44/valo=1,524.99 2006.257.13:10:22.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.13:10:22.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.13:10:22.31#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:22.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:22.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:22.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:22.31#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:10:22.31#ibcon#first serial, iclass 22, count 0 2006.257.13:10:22.31#ibcon#enter sib2, iclass 22, count 0 2006.257.13:10:22.31#ibcon#flushed, iclass 22, count 0 2006.257.13:10:22.31#ibcon#about to write, iclass 22, count 0 2006.257.13:10:22.31#ibcon#wrote, iclass 22, count 0 2006.257.13:10:22.31#ibcon#about to read 3, iclass 22, count 0 2006.257.13:10:22.33#ibcon#read 3, iclass 22, count 0 2006.257.13:10:22.33#ibcon#about to read 4, iclass 22, count 0 2006.257.13:10:22.33#ibcon#read 4, iclass 22, count 0 2006.257.13:10:22.33#ibcon#about to read 5, iclass 22, count 0 2006.257.13:10:22.33#ibcon#read 5, iclass 22, count 0 2006.257.13:10:22.33#ibcon#about to read 6, iclass 22, count 0 2006.257.13:10:22.33#ibcon#read 6, iclass 22, count 0 2006.257.13:10:22.33#ibcon#end of sib2, iclass 22, count 0 2006.257.13:10:22.33#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:10:22.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:10:22.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:10:22.33#ibcon#*before write, iclass 22, count 0 2006.257.13:10:22.33#ibcon#enter sib2, iclass 22, count 0 2006.257.13:10:22.33#ibcon#flushed, iclass 22, count 0 2006.257.13:10:22.33#ibcon#about to write, iclass 22, count 0 2006.257.13:10:22.33#ibcon#wrote, iclass 22, count 0 2006.257.13:10:22.33#ibcon#about to read 3, iclass 22, count 0 2006.257.13:10:22.38#ibcon#read 3, iclass 22, count 0 2006.257.13:10:22.38#ibcon#about to read 4, iclass 22, count 0 2006.257.13:10:22.38#ibcon#read 4, iclass 22, count 0 2006.257.13:10:22.38#ibcon#about to read 5, iclass 22, count 0 2006.257.13:10:22.38#ibcon#read 5, iclass 22, count 0 2006.257.13:10:22.38#ibcon#about to read 6, iclass 22, count 0 2006.257.13:10:22.38#ibcon#read 6, iclass 22, count 0 2006.257.13:10:22.38#ibcon#end of sib2, iclass 22, count 0 2006.257.13:10:22.38#ibcon#*after write, iclass 22, count 0 2006.257.13:10:22.38#ibcon#*before return 0, iclass 22, count 0 2006.257.13:10:22.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:22.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:22.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:10:22.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:10:22.38$vck44/va=1,8 2006.257.13:10:22.38#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.13:10:22.38#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.13:10:22.38#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:22.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:22.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:22.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:22.38#ibcon#enter wrdev, iclass 24, count 2 2006.257.13:10:22.38#ibcon#first serial, iclass 24, count 2 2006.257.13:10:22.38#ibcon#enter sib2, iclass 24, count 2 2006.257.13:10:22.38#ibcon#flushed, iclass 24, count 2 2006.257.13:10:22.38#ibcon#about to write, iclass 24, count 2 2006.257.13:10:22.38#ibcon#wrote, iclass 24, count 2 2006.257.13:10:22.38#ibcon#about to read 3, iclass 24, count 2 2006.257.13:10:22.40#ibcon#read 3, iclass 24, count 2 2006.257.13:10:22.40#ibcon#about to read 4, iclass 24, count 2 2006.257.13:10:22.40#ibcon#read 4, iclass 24, count 2 2006.257.13:10:22.40#ibcon#about to read 5, iclass 24, count 2 2006.257.13:10:22.40#ibcon#read 5, iclass 24, count 2 2006.257.13:10:22.40#ibcon#about to read 6, iclass 24, count 2 2006.257.13:10:22.40#ibcon#read 6, iclass 24, count 2 2006.257.13:10:22.40#ibcon#end of sib2, iclass 24, count 2 2006.257.13:10:22.40#ibcon#*mode == 0, iclass 24, count 2 2006.257.13:10:22.40#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.13:10:22.40#ibcon#[25=AT01-08\r\n] 2006.257.13:10:22.40#ibcon#*before write, iclass 24, count 2 2006.257.13:10:22.40#ibcon#enter sib2, iclass 24, count 2 2006.257.13:10:22.40#ibcon#flushed, iclass 24, count 2 2006.257.13:10:22.40#ibcon#about to write, iclass 24, count 2 2006.257.13:10:22.40#ibcon#wrote, iclass 24, count 2 2006.257.13:10:22.40#ibcon#about to read 3, iclass 24, count 2 2006.257.13:10:22.43#ibcon#read 3, iclass 24, count 2 2006.257.13:10:22.43#ibcon#about to read 4, iclass 24, count 2 2006.257.13:10:22.43#ibcon#read 4, iclass 24, count 2 2006.257.13:10:22.43#ibcon#about to read 5, iclass 24, count 2 2006.257.13:10:22.43#ibcon#read 5, iclass 24, count 2 2006.257.13:10:22.43#ibcon#about to read 6, iclass 24, count 2 2006.257.13:10:22.43#ibcon#read 6, iclass 24, count 2 2006.257.13:10:22.43#ibcon#end of sib2, iclass 24, count 2 2006.257.13:10:22.43#ibcon#*after write, iclass 24, count 2 2006.257.13:10:22.43#ibcon#*before return 0, iclass 24, count 2 2006.257.13:10:22.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:22.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:22.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.13:10:22.43#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:22.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:22.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:22.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:22.55#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:10:22.55#ibcon#first serial, iclass 24, count 0 2006.257.13:10:22.55#ibcon#enter sib2, iclass 24, count 0 2006.257.13:10:22.55#ibcon#flushed, iclass 24, count 0 2006.257.13:10:22.55#ibcon#about to write, iclass 24, count 0 2006.257.13:10:22.55#ibcon#wrote, iclass 24, count 0 2006.257.13:10:22.55#ibcon#about to read 3, iclass 24, count 0 2006.257.13:10:22.57#ibcon#read 3, iclass 24, count 0 2006.257.13:10:22.57#ibcon#about to read 4, iclass 24, count 0 2006.257.13:10:22.57#ibcon#read 4, iclass 24, count 0 2006.257.13:10:22.57#ibcon#about to read 5, iclass 24, count 0 2006.257.13:10:22.57#ibcon#read 5, iclass 24, count 0 2006.257.13:10:22.57#ibcon#about to read 6, iclass 24, count 0 2006.257.13:10:22.57#ibcon#read 6, iclass 24, count 0 2006.257.13:10:22.57#ibcon#end of sib2, iclass 24, count 0 2006.257.13:10:22.57#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:10:22.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:10:22.57#ibcon#[25=USB\r\n] 2006.257.13:10:22.57#ibcon#*before write, iclass 24, count 0 2006.257.13:10:22.57#ibcon#enter sib2, iclass 24, count 0 2006.257.13:10:22.57#ibcon#flushed, iclass 24, count 0 2006.257.13:10:22.57#ibcon#about to write, iclass 24, count 0 2006.257.13:10:22.57#ibcon#wrote, iclass 24, count 0 2006.257.13:10:22.57#ibcon#about to read 3, iclass 24, count 0 2006.257.13:10:22.60#ibcon#read 3, iclass 24, count 0 2006.257.13:10:22.60#ibcon#about to read 4, iclass 24, count 0 2006.257.13:10:22.60#ibcon#read 4, iclass 24, count 0 2006.257.13:10:22.60#ibcon#about to read 5, iclass 24, count 0 2006.257.13:10:22.60#ibcon#read 5, iclass 24, count 0 2006.257.13:10:22.60#ibcon#about to read 6, iclass 24, count 0 2006.257.13:10:22.60#ibcon#read 6, iclass 24, count 0 2006.257.13:10:22.60#ibcon#end of sib2, iclass 24, count 0 2006.257.13:10:22.60#ibcon#*after write, iclass 24, count 0 2006.257.13:10:22.60#ibcon#*before return 0, iclass 24, count 0 2006.257.13:10:22.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:22.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:22.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:10:22.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:10:22.60$vck44/valo=2,534.99 2006.257.13:10:22.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.13:10:22.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.13:10:22.60#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:22.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:22.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:22.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:22.60#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:10:22.60#ibcon#first serial, iclass 26, count 0 2006.257.13:10:22.60#ibcon#enter sib2, iclass 26, count 0 2006.257.13:10:22.60#ibcon#flushed, iclass 26, count 0 2006.257.13:10:22.60#ibcon#about to write, iclass 26, count 0 2006.257.13:10:22.60#ibcon#wrote, iclass 26, count 0 2006.257.13:10:22.60#ibcon#about to read 3, iclass 26, count 0 2006.257.13:10:22.62#ibcon#read 3, iclass 26, count 0 2006.257.13:10:22.62#ibcon#about to read 4, iclass 26, count 0 2006.257.13:10:22.62#ibcon#read 4, iclass 26, count 0 2006.257.13:10:22.62#ibcon#about to read 5, iclass 26, count 0 2006.257.13:10:22.62#ibcon#read 5, iclass 26, count 0 2006.257.13:10:22.62#ibcon#about to read 6, iclass 26, count 0 2006.257.13:10:22.62#ibcon#read 6, iclass 26, count 0 2006.257.13:10:22.62#ibcon#end of sib2, iclass 26, count 0 2006.257.13:10:22.62#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:10:22.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:10:22.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:10:22.62#ibcon#*before write, iclass 26, count 0 2006.257.13:10:22.62#ibcon#enter sib2, iclass 26, count 0 2006.257.13:10:22.62#ibcon#flushed, iclass 26, count 0 2006.257.13:10:22.62#ibcon#about to write, iclass 26, count 0 2006.257.13:10:22.62#ibcon#wrote, iclass 26, count 0 2006.257.13:10:22.62#ibcon#about to read 3, iclass 26, count 0 2006.257.13:10:22.66#ibcon#read 3, iclass 26, count 0 2006.257.13:10:22.66#ibcon#about to read 4, iclass 26, count 0 2006.257.13:10:22.66#ibcon#read 4, iclass 26, count 0 2006.257.13:10:22.66#ibcon#about to read 5, iclass 26, count 0 2006.257.13:10:22.66#ibcon#read 5, iclass 26, count 0 2006.257.13:10:22.66#ibcon#about to read 6, iclass 26, count 0 2006.257.13:10:22.66#ibcon#read 6, iclass 26, count 0 2006.257.13:10:22.66#ibcon#end of sib2, iclass 26, count 0 2006.257.13:10:22.66#ibcon#*after write, iclass 26, count 0 2006.257.13:10:22.66#ibcon#*before return 0, iclass 26, count 0 2006.257.13:10:22.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:22.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:22.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:10:22.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:10:22.66$vck44/va=2,7 2006.257.13:10:22.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.13:10:22.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.13:10:22.66#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:22.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:22.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:22.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:22.72#ibcon#enter wrdev, iclass 28, count 2 2006.257.13:10:22.72#ibcon#first serial, iclass 28, count 2 2006.257.13:10:22.72#ibcon#enter sib2, iclass 28, count 2 2006.257.13:10:22.72#ibcon#flushed, iclass 28, count 2 2006.257.13:10:22.72#ibcon#about to write, iclass 28, count 2 2006.257.13:10:22.72#ibcon#wrote, iclass 28, count 2 2006.257.13:10:22.72#ibcon#about to read 3, iclass 28, count 2 2006.257.13:10:22.74#ibcon#read 3, iclass 28, count 2 2006.257.13:10:22.74#ibcon#about to read 4, iclass 28, count 2 2006.257.13:10:22.74#ibcon#read 4, iclass 28, count 2 2006.257.13:10:22.74#ibcon#about to read 5, iclass 28, count 2 2006.257.13:10:22.74#ibcon#read 5, iclass 28, count 2 2006.257.13:10:22.74#ibcon#about to read 6, iclass 28, count 2 2006.257.13:10:22.74#ibcon#read 6, iclass 28, count 2 2006.257.13:10:22.74#ibcon#end of sib2, iclass 28, count 2 2006.257.13:10:22.74#ibcon#*mode == 0, iclass 28, count 2 2006.257.13:10:22.74#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.13:10:22.74#ibcon#[25=AT02-07\r\n] 2006.257.13:10:22.74#ibcon#*before write, iclass 28, count 2 2006.257.13:10:22.74#ibcon#enter sib2, iclass 28, count 2 2006.257.13:10:22.74#ibcon#flushed, iclass 28, count 2 2006.257.13:10:22.74#ibcon#about to write, iclass 28, count 2 2006.257.13:10:22.74#ibcon#wrote, iclass 28, count 2 2006.257.13:10:22.74#ibcon#about to read 3, iclass 28, count 2 2006.257.13:10:22.77#ibcon#read 3, iclass 28, count 2 2006.257.13:10:22.77#ibcon#about to read 4, iclass 28, count 2 2006.257.13:10:22.77#ibcon#read 4, iclass 28, count 2 2006.257.13:10:22.77#ibcon#about to read 5, iclass 28, count 2 2006.257.13:10:22.77#ibcon#read 5, iclass 28, count 2 2006.257.13:10:22.77#ibcon#about to read 6, iclass 28, count 2 2006.257.13:10:22.77#ibcon#read 6, iclass 28, count 2 2006.257.13:10:22.77#ibcon#end of sib2, iclass 28, count 2 2006.257.13:10:22.77#ibcon#*after write, iclass 28, count 2 2006.257.13:10:22.77#ibcon#*before return 0, iclass 28, count 2 2006.257.13:10:22.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:22.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:22.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.13:10:22.77#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:22.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:22.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:22.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:22.89#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:10:22.89#ibcon#first serial, iclass 28, count 0 2006.257.13:10:22.89#ibcon#enter sib2, iclass 28, count 0 2006.257.13:10:22.89#ibcon#flushed, iclass 28, count 0 2006.257.13:10:22.89#ibcon#about to write, iclass 28, count 0 2006.257.13:10:22.89#ibcon#wrote, iclass 28, count 0 2006.257.13:10:22.89#ibcon#about to read 3, iclass 28, count 0 2006.257.13:10:22.91#ibcon#read 3, iclass 28, count 0 2006.257.13:10:22.91#ibcon#about to read 4, iclass 28, count 0 2006.257.13:10:22.91#ibcon#read 4, iclass 28, count 0 2006.257.13:10:22.91#ibcon#about to read 5, iclass 28, count 0 2006.257.13:10:22.91#ibcon#read 5, iclass 28, count 0 2006.257.13:10:22.91#ibcon#about to read 6, iclass 28, count 0 2006.257.13:10:22.91#ibcon#read 6, iclass 28, count 0 2006.257.13:10:22.91#ibcon#end of sib2, iclass 28, count 0 2006.257.13:10:22.91#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:10:22.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:10:22.91#ibcon#[25=USB\r\n] 2006.257.13:10:22.91#ibcon#*before write, iclass 28, count 0 2006.257.13:10:22.91#ibcon#enter sib2, iclass 28, count 0 2006.257.13:10:22.91#ibcon#flushed, iclass 28, count 0 2006.257.13:10:22.91#ibcon#about to write, iclass 28, count 0 2006.257.13:10:22.91#ibcon#wrote, iclass 28, count 0 2006.257.13:10:22.91#ibcon#about to read 3, iclass 28, count 0 2006.257.13:10:22.94#ibcon#read 3, iclass 28, count 0 2006.257.13:10:22.94#ibcon#about to read 4, iclass 28, count 0 2006.257.13:10:22.94#ibcon#read 4, iclass 28, count 0 2006.257.13:10:22.94#ibcon#about to read 5, iclass 28, count 0 2006.257.13:10:22.94#ibcon#read 5, iclass 28, count 0 2006.257.13:10:22.94#ibcon#about to read 6, iclass 28, count 0 2006.257.13:10:22.94#ibcon#read 6, iclass 28, count 0 2006.257.13:10:22.94#ibcon#end of sib2, iclass 28, count 0 2006.257.13:10:22.94#ibcon#*after write, iclass 28, count 0 2006.257.13:10:22.94#ibcon#*before return 0, iclass 28, count 0 2006.257.13:10:22.94#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:22.94#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:22.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:10:22.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:10:22.94$vck44/valo=3,564.99 2006.257.13:10:22.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.13:10:22.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.13:10:22.94#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:22.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:22.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:22.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:22.94#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:10:22.94#ibcon#first serial, iclass 30, count 0 2006.257.13:10:22.94#ibcon#enter sib2, iclass 30, count 0 2006.257.13:10:22.94#ibcon#flushed, iclass 30, count 0 2006.257.13:10:22.94#ibcon#about to write, iclass 30, count 0 2006.257.13:10:22.94#ibcon#wrote, iclass 30, count 0 2006.257.13:10:22.94#ibcon#about to read 3, iclass 30, count 0 2006.257.13:10:22.96#ibcon#read 3, iclass 30, count 0 2006.257.13:10:22.96#ibcon#about to read 4, iclass 30, count 0 2006.257.13:10:22.96#ibcon#read 4, iclass 30, count 0 2006.257.13:10:22.96#ibcon#about to read 5, iclass 30, count 0 2006.257.13:10:22.96#ibcon#read 5, iclass 30, count 0 2006.257.13:10:22.96#ibcon#about to read 6, iclass 30, count 0 2006.257.13:10:22.96#ibcon#read 6, iclass 30, count 0 2006.257.13:10:22.96#ibcon#end of sib2, iclass 30, count 0 2006.257.13:10:22.96#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:10:22.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:10:22.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:10:22.96#ibcon#*before write, iclass 30, count 0 2006.257.13:10:22.96#ibcon#enter sib2, iclass 30, count 0 2006.257.13:10:22.96#ibcon#flushed, iclass 30, count 0 2006.257.13:10:22.96#ibcon#about to write, iclass 30, count 0 2006.257.13:10:22.96#ibcon#wrote, iclass 30, count 0 2006.257.13:10:22.96#ibcon#about to read 3, iclass 30, count 0 2006.257.13:10:23.00#ibcon#read 3, iclass 30, count 0 2006.257.13:10:23.00#ibcon#about to read 4, iclass 30, count 0 2006.257.13:10:23.00#ibcon#read 4, iclass 30, count 0 2006.257.13:10:23.00#ibcon#about to read 5, iclass 30, count 0 2006.257.13:10:23.00#ibcon#read 5, iclass 30, count 0 2006.257.13:10:23.00#ibcon#about to read 6, iclass 30, count 0 2006.257.13:10:23.00#ibcon#read 6, iclass 30, count 0 2006.257.13:10:23.00#ibcon#end of sib2, iclass 30, count 0 2006.257.13:10:23.00#ibcon#*after write, iclass 30, count 0 2006.257.13:10:23.00#ibcon#*before return 0, iclass 30, count 0 2006.257.13:10:23.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:23.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:23.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:10:23.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:10:23.00$vck44/va=3,8 2006.257.13:10:23.00#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.13:10:23.00#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.13:10:23.00#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:23.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:23.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:23.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:23.06#ibcon#enter wrdev, iclass 32, count 2 2006.257.13:10:23.06#ibcon#first serial, iclass 32, count 2 2006.257.13:10:23.06#ibcon#enter sib2, iclass 32, count 2 2006.257.13:10:23.06#ibcon#flushed, iclass 32, count 2 2006.257.13:10:23.06#ibcon#about to write, iclass 32, count 2 2006.257.13:10:23.06#ibcon#wrote, iclass 32, count 2 2006.257.13:10:23.06#ibcon#about to read 3, iclass 32, count 2 2006.257.13:10:23.08#ibcon#read 3, iclass 32, count 2 2006.257.13:10:23.08#ibcon#about to read 4, iclass 32, count 2 2006.257.13:10:23.08#ibcon#read 4, iclass 32, count 2 2006.257.13:10:23.08#ibcon#about to read 5, iclass 32, count 2 2006.257.13:10:23.08#ibcon#read 5, iclass 32, count 2 2006.257.13:10:23.08#ibcon#about to read 6, iclass 32, count 2 2006.257.13:10:23.08#ibcon#read 6, iclass 32, count 2 2006.257.13:10:23.08#ibcon#end of sib2, iclass 32, count 2 2006.257.13:10:23.08#ibcon#*mode == 0, iclass 32, count 2 2006.257.13:10:23.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.13:10:23.08#ibcon#[25=AT03-08\r\n] 2006.257.13:10:23.08#ibcon#*before write, iclass 32, count 2 2006.257.13:10:23.08#ibcon#enter sib2, iclass 32, count 2 2006.257.13:10:23.08#ibcon#flushed, iclass 32, count 2 2006.257.13:10:23.08#ibcon#about to write, iclass 32, count 2 2006.257.13:10:23.08#ibcon#wrote, iclass 32, count 2 2006.257.13:10:23.08#ibcon#about to read 3, iclass 32, count 2 2006.257.13:10:23.09#abcon#<5=/14 1.4 3.8 17.70 971013.7\r\n> 2006.257.13:10:23.11#abcon#{5=INTERFACE CLEAR} 2006.257.13:10:23.11#ibcon#read 3, iclass 32, count 2 2006.257.13:10:23.11#ibcon#about to read 4, iclass 32, count 2 2006.257.13:10:23.11#ibcon#read 4, iclass 32, count 2 2006.257.13:10:23.11#ibcon#about to read 5, iclass 32, count 2 2006.257.13:10:23.11#ibcon#read 5, iclass 32, count 2 2006.257.13:10:23.11#ibcon#about to read 6, iclass 32, count 2 2006.257.13:10:23.11#ibcon#read 6, iclass 32, count 2 2006.257.13:10:23.11#ibcon#end of sib2, iclass 32, count 2 2006.257.13:10:23.11#ibcon#*after write, iclass 32, count 2 2006.257.13:10:23.11#ibcon#*before return 0, iclass 32, count 2 2006.257.13:10:23.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:23.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:23.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.13:10:23.11#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:23.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:23.17#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:10:23.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:23.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:23.23#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:10:23.23#ibcon#first serial, iclass 32, count 0 2006.257.13:10:23.23#ibcon#enter sib2, iclass 32, count 0 2006.257.13:10:23.23#ibcon#flushed, iclass 32, count 0 2006.257.13:10:23.23#ibcon#about to write, iclass 32, count 0 2006.257.13:10:23.23#ibcon#wrote, iclass 32, count 0 2006.257.13:10:23.23#ibcon#about to read 3, iclass 32, count 0 2006.257.13:10:23.25#ibcon#read 3, iclass 32, count 0 2006.257.13:10:23.25#ibcon#about to read 4, iclass 32, count 0 2006.257.13:10:23.25#ibcon#read 4, iclass 32, count 0 2006.257.13:10:23.25#ibcon#about to read 5, iclass 32, count 0 2006.257.13:10:23.25#ibcon#read 5, iclass 32, count 0 2006.257.13:10:23.25#ibcon#about to read 6, iclass 32, count 0 2006.257.13:10:23.25#ibcon#read 6, iclass 32, count 0 2006.257.13:10:23.25#ibcon#end of sib2, iclass 32, count 0 2006.257.13:10:23.25#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:10:23.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:10:23.25#ibcon#[25=USB\r\n] 2006.257.13:10:23.25#ibcon#*before write, iclass 32, count 0 2006.257.13:10:23.25#ibcon#enter sib2, iclass 32, count 0 2006.257.13:10:23.25#ibcon#flushed, iclass 32, count 0 2006.257.13:10:23.25#ibcon#about to write, iclass 32, count 0 2006.257.13:10:23.25#ibcon#wrote, iclass 32, count 0 2006.257.13:10:23.25#ibcon#about to read 3, iclass 32, count 0 2006.257.13:10:23.28#ibcon#read 3, iclass 32, count 0 2006.257.13:10:23.28#ibcon#about to read 4, iclass 32, count 0 2006.257.13:10:23.28#ibcon#read 4, iclass 32, count 0 2006.257.13:10:23.28#ibcon#about to read 5, iclass 32, count 0 2006.257.13:10:23.28#ibcon#read 5, iclass 32, count 0 2006.257.13:10:23.28#ibcon#about to read 6, iclass 32, count 0 2006.257.13:10:23.28#ibcon#read 6, iclass 32, count 0 2006.257.13:10:23.28#ibcon#end of sib2, iclass 32, count 0 2006.257.13:10:23.28#ibcon#*after write, iclass 32, count 0 2006.257.13:10:23.28#ibcon#*before return 0, iclass 32, count 0 2006.257.13:10:23.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:23.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:23.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:10:23.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:10:23.28$vck44/valo=4,624.99 2006.257.13:10:23.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.13:10:23.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.13:10:23.28#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:23.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:23.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:23.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:23.28#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:10:23.28#ibcon#first serial, iclass 38, count 0 2006.257.13:10:23.28#ibcon#enter sib2, iclass 38, count 0 2006.257.13:10:23.28#ibcon#flushed, iclass 38, count 0 2006.257.13:10:23.28#ibcon#about to write, iclass 38, count 0 2006.257.13:10:23.28#ibcon#wrote, iclass 38, count 0 2006.257.13:10:23.28#ibcon#about to read 3, iclass 38, count 0 2006.257.13:10:23.30#ibcon#read 3, iclass 38, count 0 2006.257.13:10:23.30#ibcon#about to read 4, iclass 38, count 0 2006.257.13:10:23.30#ibcon#read 4, iclass 38, count 0 2006.257.13:10:23.30#ibcon#about to read 5, iclass 38, count 0 2006.257.13:10:23.30#ibcon#read 5, iclass 38, count 0 2006.257.13:10:23.30#ibcon#about to read 6, iclass 38, count 0 2006.257.13:10:23.30#ibcon#read 6, iclass 38, count 0 2006.257.13:10:23.30#ibcon#end of sib2, iclass 38, count 0 2006.257.13:10:23.30#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:10:23.30#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:10:23.30#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:10:23.30#ibcon#*before write, iclass 38, count 0 2006.257.13:10:23.30#ibcon#enter sib2, iclass 38, count 0 2006.257.13:10:23.30#ibcon#flushed, iclass 38, count 0 2006.257.13:10:23.30#ibcon#about to write, iclass 38, count 0 2006.257.13:10:23.30#ibcon#wrote, iclass 38, count 0 2006.257.13:10:23.30#ibcon#about to read 3, iclass 38, count 0 2006.257.13:10:23.34#ibcon#read 3, iclass 38, count 0 2006.257.13:10:23.34#ibcon#about to read 4, iclass 38, count 0 2006.257.13:10:23.34#ibcon#read 4, iclass 38, count 0 2006.257.13:10:23.34#ibcon#about to read 5, iclass 38, count 0 2006.257.13:10:23.34#ibcon#read 5, iclass 38, count 0 2006.257.13:10:23.34#ibcon#about to read 6, iclass 38, count 0 2006.257.13:10:23.34#ibcon#read 6, iclass 38, count 0 2006.257.13:10:23.34#ibcon#end of sib2, iclass 38, count 0 2006.257.13:10:23.34#ibcon#*after write, iclass 38, count 0 2006.257.13:10:23.34#ibcon#*before return 0, iclass 38, count 0 2006.257.13:10:23.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:23.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:23.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:10:23.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:10:23.34$vck44/va=4,7 2006.257.13:10:23.34#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.13:10:23.34#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.13:10:23.34#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:23.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:23.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:23.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:23.40#ibcon#enter wrdev, iclass 40, count 2 2006.257.13:10:23.40#ibcon#first serial, iclass 40, count 2 2006.257.13:10:23.40#ibcon#enter sib2, iclass 40, count 2 2006.257.13:10:23.40#ibcon#flushed, iclass 40, count 2 2006.257.13:10:23.40#ibcon#about to write, iclass 40, count 2 2006.257.13:10:23.40#ibcon#wrote, iclass 40, count 2 2006.257.13:10:23.40#ibcon#about to read 3, iclass 40, count 2 2006.257.13:10:23.42#ibcon#read 3, iclass 40, count 2 2006.257.13:10:23.42#ibcon#about to read 4, iclass 40, count 2 2006.257.13:10:23.42#ibcon#read 4, iclass 40, count 2 2006.257.13:10:23.42#ibcon#about to read 5, iclass 40, count 2 2006.257.13:10:23.42#ibcon#read 5, iclass 40, count 2 2006.257.13:10:23.42#ibcon#about to read 6, iclass 40, count 2 2006.257.13:10:23.42#ibcon#read 6, iclass 40, count 2 2006.257.13:10:23.42#ibcon#end of sib2, iclass 40, count 2 2006.257.13:10:23.42#ibcon#*mode == 0, iclass 40, count 2 2006.257.13:10:23.42#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.13:10:23.42#ibcon#[25=AT04-07\r\n] 2006.257.13:10:23.42#ibcon#*before write, iclass 40, count 2 2006.257.13:10:23.42#ibcon#enter sib2, iclass 40, count 2 2006.257.13:10:23.42#ibcon#flushed, iclass 40, count 2 2006.257.13:10:23.42#ibcon#about to write, iclass 40, count 2 2006.257.13:10:23.42#ibcon#wrote, iclass 40, count 2 2006.257.13:10:23.42#ibcon#about to read 3, iclass 40, count 2 2006.257.13:10:23.45#ibcon#read 3, iclass 40, count 2 2006.257.13:10:23.45#ibcon#about to read 4, iclass 40, count 2 2006.257.13:10:23.45#ibcon#read 4, iclass 40, count 2 2006.257.13:10:23.45#ibcon#about to read 5, iclass 40, count 2 2006.257.13:10:23.45#ibcon#read 5, iclass 40, count 2 2006.257.13:10:23.45#ibcon#about to read 6, iclass 40, count 2 2006.257.13:10:23.45#ibcon#read 6, iclass 40, count 2 2006.257.13:10:23.45#ibcon#end of sib2, iclass 40, count 2 2006.257.13:10:23.47#ibcon#*after write, iclass 40, count 2 2006.257.13:10:23.47#ibcon#*before return 0, iclass 40, count 2 2006.257.13:10:23.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:23.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:23.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.13:10:23.47#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:23.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:23.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:23.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:23.59#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:10:23.59#ibcon#first serial, iclass 40, count 0 2006.257.13:10:23.59#ibcon#enter sib2, iclass 40, count 0 2006.257.13:10:23.59#ibcon#flushed, iclass 40, count 0 2006.257.13:10:23.59#ibcon#about to write, iclass 40, count 0 2006.257.13:10:23.59#ibcon#wrote, iclass 40, count 0 2006.257.13:10:23.59#ibcon#about to read 3, iclass 40, count 0 2006.257.13:10:23.61#ibcon#read 3, iclass 40, count 0 2006.257.13:10:23.61#ibcon#about to read 4, iclass 40, count 0 2006.257.13:10:23.61#ibcon#read 4, iclass 40, count 0 2006.257.13:10:23.61#ibcon#about to read 5, iclass 40, count 0 2006.257.13:10:23.61#ibcon#read 5, iclass 40, count 0 2006.257.13:10:23.61#ibcon#about to read 6, iclass 40, count 0 2006.257.13:10:23.61#ibcon#read 6, iclass 40, count 0 2006.257.13:10:23.61#ibcon#end of sib2, iclass 40, count 0 2006.257.13:10:23.61#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:10:23.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:10:23.61#ibcon#[25=USB\r\n] 2006.257.13:10:23.61#ibcon#*before write, iclass 40, count 0 2006.257.13:10:23.61#ibcon#enter sib2, iclass 40, count 0 2006.257.13:10:23.61#ibcon#flushed, iclass 40, count 0 2006.257.13:10:23.61#ibcon#about to write, iclass 40, count 0 2006.257.13:10:23.61#ibcon#wrote, iclass 40, count 0 2006.257.13:10:23.61#ibcon#about to read 3, iclass 40, count 0 2006.257.13:10:23.64#ibcon#read 3, iclass 40, count 0 2006.257.13:10:23.64#ibcon#about to read 4, iclass 40, count 0 2006.257.13:10:23.64#ibcon#read 4, iclass 40, count 0 2006.257.13:10:23.64#ibcon#about to read 5, iclass 40, count 0 2006.257.13:10:23.64#ibcon#read 5, iclass 40, count 0 2006.257.13:10:23.64#ibcon#about to read 6, iclass 40, count 0 2006.257.13:10:23.64#ibcon#read 6, iclass 40, count 0 2006.257.13:10:23.64#ibcon#end of sib2, iclass 40, count 0 2006.257.13:10:23.64#ibcon#*after write, iclass 40, count 0 2006.257.13:10:23.64#ibcon#*before return 0, iclass 40, count 0 2006.257.13:10:23.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:23.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:23.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:10:23.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:10:23.64$vck44/valo=5,734.99 2006.257.13:10:23.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.13:10:23.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.13:10:23.64#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:23.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:23.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:23.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:23.64#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:10:23.64#ibcon#first serial, iclass 4, count 0 2006.257.13:10:23.64#ibcon#enter sib2, iclass 4, count 0 2006.257.13:10:23.64#ibcon#flushed, iclass 4, count 0 2006.257.13:10:23.64#ibcon#about to write, iclass 4, count 0 2006.257.13:10:23.64#ibcon#wrote, iclass 4, count 0 2006.257.13:10:23.64#ibcon#about to read 3, iclass 4, count 0 2006.257.13:10:23.66#ibcon#read 3, iclass 4, count 0 2006.257.13:10:23.66#ibcon#about to read 4, iclass 4, count 0 2006.257.13:10:23.66#ibcon#read 4, iclass 4, count 0 2006.257.13:10:23.66#ibcon#about to read 5, iclass 4, count 0 2006.257.13:10:23.66#ibcon#read 5, iclass 4, count 0 2006.257.13:10:23.66#ibcon#about to read 6, iclass 4, count 0 2006.257.13:10:23.66#ibcon#read 6, iclass 4, count 0 2006.257.13:10:23.66#ibcon#end of sib2, iclass 4, count 0 2006.257.13:10:23.66#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:10:23.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:10:23.66#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:10:23.66#ibcon#*before write, iclass 4, count 0 2006.257.13:10:23.66#ibcon#enter sib2, iclass 4, count 0 2006.257.13:10:23.66#ibcon#flushed, iclass 4, count 0 2006.257.13:10:23.66#ibcon#about to write, iclass 4, count 0 2006.257.13:10:23.66#ibcon#wrote, iclass 4, count 0 2006.257.13:10:23.66#ibcon#about to read 3, iclass 4, count 0 2006.257.13:10:23.70#ibcon#read 3, iclass 4, count 0 2006.257.13:10:23.70#ibcon#about to read 4, iclass 4, count 0 2006.257.13:10:23.70#ibcon#read 4, iclass 4, count 0 2006.257.13:10:23.70#ibcon#about to read 5, iclass 4, count 0 2006.257.13:10:23.70#ibcon#read 5, iclass 4, count 0 2006.257.13:10:23.70#ibcon#about to read 6, iclass 4, count 0 2006.257.13:10:23.70#ibcon#read 6, iclass 4, count 0 2006.257.13:10:23.70#ibcon#end of sib2, iclass 4, count 0 2006.257.13:10:23.70#ibcon#*after write, iclass 4, count 0 2006.257.13:10:23.70#ibcon#*before return 0, iclass 4, count 0 2006.257.13:10:23.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:23.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:23.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:10:23.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:10:23.70$vck44/va=5,4 2006.257.13:10:23.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.13:10:23.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.13:10:23.70#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:23.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:23.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:23.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:23.76#ibcon#enter wrdev, iclass 6, count 2 2006.257.13:10:23.76#ibcon#first serial, iclass 6, count 2 2006.257.13:10:23.76#ibcon#enter sib2, iclass 6, count 2 2006.257.13:10:23.76#ibcon#flushed, iclass 6, count 2 2006.257.13:10:23.76#ibcon#about to write, iclass 6, count 2 2006.257.13:10:23.76#ibcon#wrote, iclass 6, count 2 2006.257.13:10:23.76#ibcon#about to read 3, iclass 6, count 2 2006.257.13:10:23.78#ibcon#read 3, iclass 6, count 2 2006.257.13:10:23.78#ibcon#about to read 4, iclass 6, count 2 2006.257.13:10:23.78#ibcon#read 4, iclass 6, count 2 2006.257.13:10:23.78#ibcon#about to read 5, iclass 6, count 2 2006.257.13:10:23.78#ibcon#read 5, iclass 6, count 2 2006.257.13:10:23.78#ibcon#about to read 6, iclass 6, count 2 2006.257.13:10:23.78#ibcon#read 6, iclass 6, count 2 2006.257.13:10:23.78#ibcon#end of sib2, iclass 6, count 2 2006.257.13:10:23.78#ibcon#*mode == 0, iclass 6, count 2 2006.257.13:10:23.78#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.13:10:23.78#ibcon#[25=AT05-04\r\n] 2006.257.13:10:23.78#ibcon#*before write, iclass 6, count 2 2006.257.13:10:23.78#ibcon#enter sib2, iclass 6, count 2 2006.257.13:10:23.78#ibcon#flushed, iclass 6, count 2 2006.257.13:10:23.78#ibcon#about to write, iclass 6, count 2 2006.257.13:10:23.78#ibcon#wrote, iclass 6, count 2 2006.257.13:10:23.78#ibcon#about to read 3, iclass 6, count 2 2006.257.13:10:23.81#ibcon#read 3, iclass 6, count 2 2006.257.13:10:23.81#ibcon#about to read 4, iclass 6, count 2 2006.257.13:10:23.81#ibcon#read 4, iclass 6, count 2 2006.257.13:10:23.81#ibcon#about to read 5, iclass 6, count 2 2006.257.13:10:23.81#ibcon#read 5, iclass 6, count 2 2006.257.13:10:23.81#ibcon#about to read 6, iclass 6, count 2 2006.257.13:10:23.81#ibcon#read 6, iclass 6, count 2 2006.257.13:10:23.81#ibcon#end of sib2, iclass 6, count 2 2006.257.13:10:23.81#ibcon#*after write, iclass 6, count 2 2006.257.13:10:23.81#ibcon#*before return 0, iclass 6, count 2 2006.257.13:10:23.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:23.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:23.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.13:10:23.81#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:23.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:23.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:23.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:23.93#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:10:23.93#ibcon#first serial, iclass 6, count 0 2006.257.13:10:23.93#ibcon#enter sib2, iclass 6, count 0 2006.257.13:10:23.93#ibcon#flushed, iclass 6, count 0 2006.257.13:10:23.93#ibcon#about to write, iclass 6, count 0 2006.257.13:10:23.93#ibcon#wrote, iclass 6, count 0 2006.257.13:10:23.93#ibcon#about to read 3, iclass 6, count 0 2006.257.13:10:23.95#ibcon#read 3, iclass 6, count 0 2006.257.13:10:23.95#ibcon#about to read 4, iclass 6, count 0 2006.257.13:10:23.95#ibcon#read 4, iclass 6, count 0 2006.257.13:10:23.95#ibcon#about to read 5, iclass 6, count 0 2006.257.13:10:23.95#ibcon#read 5, iclass 6, count 0 2006.257.13:10:23.95#ibcon#about to read 6, iclass 6, count 0 2006.257.13:10:23.95#ibcon#read 6, iclass 6, count 0 2006.257.13:10:23.95#ibcon#end of sib2, iclass 6, count 0 2006.257.13:10:23.95#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:10:23.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:10:23.95#ibcon#[25=USB\r\n] 2006.257.13:10:23.95#ibcon#*before write, iclass 6, count 0 2006.257.13:10:23.95#ibcon#enter sib2, iclass 6, count 0 2006.257.13:10:23.95#ibcon#flushed, iclass 6, count 0 2006.257.13:10:23.95#ibcon#about to write, iclass 6, count 0 2006.257.13:10:23.95#ibcon#wrote, iclass 6, count 0 2006.257.13:10:23.95#ibcon#about to read 3, iclass 6, count 0 2006.257.13:10:23.98#ibcon#read 3, iclass 6, count 0 2006.257.13:10:23.98#ibcon#about to read 4, iclass 6, count 0 2006.257.13:10:23.98#ibcon#read 4, iclass 6, count 0 2006.257.13:10:23.98#ibcon#about to read 5, iclass 6, count 0 2006.257.13:10:23.98#ibcon#read 5, iclass 6, count 0 2006.257.13:10:23.98#ibcon#about to read 6, iclass 6, count 0 2006.257.13:10:23.98#ibcon#read 6, iclass 6, count 0 2006.257.13:10:23.98#ibcon#end of sib2, iclass 6, count 0 2006.257.13:10:23.98#ibcon#*after write, iclass 6, count 0 2006.257.13:10:23.98#ibcon#*before return 0, iclass 6, count 0 2006.257.13:10:23.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:23.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:23.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:10:23.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:10:23.98$vck44/valo=6,814.99 2006.257.13:10:23.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.13:10:23.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.13:10:23.98#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:23.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:23.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:23.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:23.98#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:10:23.98#ibcon#first serial, iclass 10, count 0 2006.257.13:10:23.98#ibcon#enter sib2, iclass 10, count 0 2006.257.13:10:23.98#ibcon#flushed, iclass 10, count 0 2006.257.13:10:23.98#ibcon#about to write, iclass 10, count 0 2006.257.13:10:23.98#ibcon#wrote, iclass 10, count 0 2006.257.13:10:23.98#ibcon#about to read 3, iclass 10, count 0 2006.257.13:10:24.00#ibcon#read 3, iclass 10, count 0 2006.257.13:10:24.00#ibcon#about to read 4, iclass 10, count 0 2006.257.13:10:24.00#ibcon#read 4, iclass 10, count 0 2006.257.13:10:24.00#ibcon#about to read 5, iclass 10, count 0 2006.257.13:10:24.00#ibcon#read 5, iclass 10, count 0 2006.257.13:10:24.00#ibcon#about to read 6, iclass 10, count 0 2006.257.13:10:24.00#ibcon#read 6, iclass 10, count 0 2006.257.13:10:24.00#ibcon#end of sib2, iclass 10, count 0 2006.257.13:10:24.00#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:10:24.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:10:24.00#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:10:24.00#ibcon#*before write, iclass 10, count 0 2006.257.13:10:24.00#ibcon#enter sib2, iclass 10, count 0 2006.257.13:10:24.00#ibcon#flushed, iclass 10, count 0 2006.257.13:10:24.00#ibcon#about to write, iclass 10, count 0 2006.257.13:10:24.00#ibcon#wrote, iclass 10, count 0 2006.257.13:10:24.00#ibcon#about to read 3, iclass 10, count 0 2006.257.13:10:24.04#ibcon#read 3, iclass 10, count 0 2006.257.13:10:24.04#ibcon#about to read 4, iclass 10, count 0 2006.257.13:10:24.04#ibcon#read 4, iclass 10, count 0 2006.257.13:10:24.04#ibcon#about to read 5, iclass 10, count 0 2006.257.13:10:24.04#ibcon#read 5, iclass 10, count 0 2006.257.13:10:24.04#ibcon#about to read 6, iclass 10, count 0 2006.257.13:10:24.04#ibcon#read 6, iclass 10, count 0 2006.257.13:10:24.04#ibcon#end of sib2, iclass 10, count 0 2006.257.13:10:24.04#ibcon#*after write, iclass 10, count 0 2006.257.13:10:24.04#ibcon#*before return 0, iclass 10, count 0 2006.257.13:10:24.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:24.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:24.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:10:24.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:10:24.04$vck44/va=6,4 2006.257.13:10:24.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.13:10:24.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.13:10:24.04#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:24.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:24.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:24.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:24.10#ibcon#enter wrdev, iclass 12, count 2 2006.257.13:10:24.10#ibcon#first serial, iclass 12, count 2 2006.257.13:10:24.10#ibcon#enter sib2, iclass 12, count 2 2006.257.13:10:24.10#ibcon#flushed, iclass 12, count 2 2006.257.13:10:24.10#ibcon#about to write, iclass 12, count 2 2006.257.13:10:24.10#ibcon#wrote, iclass 12, count 2 2006.257.13:10:24.10#ibcon#about to read 3, iclass 12, count 2 2006.257.13:10:24.12#ibcon#read 3, iclass 12, count 2 2006.257.13:10:24.12#ibcon#about to read 4, iclass 12, count 2 2006.257.13:10:24.12#ibcon#read 4, iclass 12, count 2 2006.257.13:10:24.12#ibcon#about to read 5, iclass 12, count 2 2006.257.13:10:24.12#ibcon#read 5, iclass 12, count 2 2006.257.13:10:24.12#ibcon#about to read 6, iclass 12, count 2 2006.257.13:10:24.12#ibcon#read 6, iclass 12, count 2 2006.257.13:10:24.12#ibcon#end of sib2, iclass 12, count 2 2006.257.13:10:24.12#ibcon#*mode == 0, iclass 12, count 2 2006.257.13:10:24.12#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.13:10:24.12#ibcon#[25=AT06-04\r\n] 2006.257.13:10:24.12#ibcon#*before write, iclass 12, count 2 2006.257.13:10:24.12#ibcon#enter sib2, iclass 12, count 2 2006.257.13:10:24.12#ibcon#flushed, iclass 12, count 2 2006.257.13:10:24.12#ibcon#about to write, iclass 12, count 2 2006.257.13:10:24.12#ibcon#wrote, iclass 12, count 2 2006.257.13:10:24.12#ibcon#about to read 3, iclass 12, count 2 2006.257.13:10:24.15#ibcon#read 3, iclass 12, count 2 2006.257.13:10:24.15#ibcon#about to read 4, iclass 12, count 2 2006.257.13:10:24.15#ibcon#read 4, iclass 12, count 2 2006.257.13:10:24.15#ibcon#about to read 5, iclass 12, count 2 2006.257.13:10:24.15#ibcon#read 5, iclass 12, count 2 2006.257.13:10:24.15#ibcon#about to read 6, iclass 12, count 2 2006.257.13:10:24.15#ibcon#read 6, iclass 12, count 2 2006.257.13:10:24.15#ibcon#end of sib2, iclass 12, count 2 2006.257.13:10:24.15#ibcon#*after write, iclass 12, count 2 2006.257.13:10:24.15#ibcon#*before return 0, iclass 12, count 2 2006.257.13:10:24.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:24.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:24.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.13:10:24.15#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:24.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:24.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:24.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:24.27#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:10:24.27#ibcon#first serial, iclass 12, count 0 2006.257.13:10:24.27#ibcon#enter sib2, iclass 12, count 0 2006.257.13:10:24.27#ibcon#flushed, iclass 12, count 0 2006.257.13:10:24.27#ibcon#about to write, iclass 12, count 0 2006.257.13:10:24.27#ibcon#wrote, iclass 12, count 0 2006.257.13:10:24.27#ibcon#about to read 3, iclass 12, count 0 2006.257.13:10:24.29#ibcon#read 3, iclass 12, count 0 2006.257.13:10:24.29#ibcon#about to read 4, iclass 12, count 0 2006.257.13:10:24.29#ibcon#read 4, iclass 12, count 0 2006.257.13:10:24.29#ibcon#about to read 5, iclass 12, count 0 2006.257.13:10:24.29#ibcon#read 5, iclass 12, count 0 2006.257.13:10:24.29#ibcon#about to read 6, iclass 12, count 0 2006.257.13:10:24.29#ibcon#read 6, iclass 12, count 0 2006.257.13:10:24.29#ibcon#end of sib2, iclass 12, count 0 2006.257.13:10:24.29#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:10:24.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:10:24.29#ibcon#[25=USB\r\n] 2006.257.13:10:24.29#ibcon#*before write, iclass 12, count 0 2006.257.13:10:24.29#ibcon#enter sib2, iclass 12, count 0 2006.257.13:10:24.29#ibcon#flushed, iclass 12, count 0 2006.257.13:10:24.29#ibcon#about to write, iclass 12, count 0 2006.257.13:10:24.29#ibcon#wrote, iclass 12, count 0 2006.257.13:10:24.29#ibcon#about to read 3, iclass 12, count 0 2006.257.13:10:24.32#ibcon#read 3, iclass 12, count 0 2006.257.13:10:24.32#ibcon#about to read 4, iclass 12, count 0 2006.257.13:10:24.32#ibcon#read 4, iclass 12, count 0 2006.257.13:10:24.32#ibcon#about to read 5, iclass 12, count 0 2006.257.13:10:24.32#ibcon#read 5, iclass 12, count 0 2006.257.13:10:24.32#ibcon#about to read 6, iclass 12, count 0 2006.257.13:10:24.32#ibcon#read 6, iclass 12, count 0 2006.257.13:10:24.32#ibcon#end of sib2, iclass 12, count 0 2006.257.13:10:24.32#ibcon#*after write, iclass 12, count 0 2006.257.13:10:24.32#ibcon#*before return 0, iclass 12, count 0 2006.257.13:10:24.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:24.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:24.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:10:24.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:10:24.32$vck44/valo=7,864.99 2006.257.13:10:24.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.13:10:24.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.13:10:24.32#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:24.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:24.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:24.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:24.32#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:10:24.32#ibcon#first serial, iclass 14, count 0 2006.257.13:10:24.32#ibcon#enter sib2, iclass 14, count 0 2006.257.13:10:24.32#ibcon#flushed, iclass 14, count 0 2006.257.13:10:24.32#ibcon#about to write, iclass 14, count 0 2006.257.13:10:24.32#ibcon#wrote, iclass 14, count 0 2006.257.13:10:24.32#ibcon#about to read 3, iclass 14, count 0 2006.257.13:10:24.34#ibcon#read 3, iclass 14, count 0 2006.257.13:10:24.34#ibcon#about to read 4, iclass 14, count 0 2006.257.13:10:24.34#ibcon#read 4, iclass 14, count 0 2006.257.13:10:24.34#ibcon#about to read 5, iclass 14, count 0 2006.257.13:10:24.34#ibcon#read 5, iclass 14, count 0 2006.257.13:10:24.34#ibcon#about to read 6, iclass 14, count 0 2006.257.13:10:24.34#ibcon#read 6, iclass 14, count 0 2006.257.13:10:24.34#ibcon#end of sib2, iclass 14, count 0 2006.257.13:10:24.34#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:10:24.34#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:10:24.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:10:24.34#ibcon#*before write, iclass 14, count 0 2006.257.13:10:24.34#ibcon#enter sib2, iclass 14, count 0 2006.257.13:10:24.34#ibcon#flushed, iclass 14, count 0 2006.257.13:10:24.34#ibcon#about to write, iclass 14, count 0 2006.257.13:10:24.34#ibcon#wrote, iclass 14, count 0 2006.257.13:10:24.34#ibcon#about to read 3, iclass 14, count 0 2006.257.13:10:24.38#ibcon#read 3, iclass 14, count 0 2006.257.13:10:24.38#ibcon#about to read 4, iclass 14, count 0 2006.257.13:10:24.38#ibcon#read 4, iclass 14, count 0 2006.257.13:10:24.38#ibcon#about to read 5, iclass 14, count 0 2006.257.13:10:24.38#ibcon#read 5, iclass 14, count 0 2006.257.13:10:24.38#ibcon#about to read 6, iclass 14, count 0 2006.257.13:10:24.38#ibcon#read 6, iclass 14, count 0 2006.257.13:10:24.38#ibcon#end of sib2, iclass 14, count 0 2006.257.13:10:24.38#ibcon#*after write, iclass 14, count 0 2006.257.13:10:24.38#ibcon#*before return 0, iclass 14, count 0 2006.257.13:10:24.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:24.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:24.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:10:24.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:10:24.38$vck44/va=7,4 2006.257.13:10:24.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.13:10:24.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.13:10:24.38#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:24.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:24.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:24.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:24.44#ibcon#enter wrdev, iclass 16, count 2 2006.257.13:10:24.44#ibcon#first serial, iclass 16, count 2 2006.257.13:10:24.44#ibcon#enter sib2, iclass 16, count 2 2006.257.13:10:24.44#ibcon#flushed, iclass 16, count 2 2006.257.13:10:24.44#ibcon#about to write, iclass 16, count 2 2006.257.13:10:24.44#ibcon#wrote, iclass 16, count 2 2006.257.13:10:24.44#ibcon#about to read 3, iclass 16, count 2 2006.257.13:10:24.46#ibcon#read 3, iclass 16, count 2 2006.257.13:10:24.46#ibcon#about to read 4, iclass 16, count 2 2006.257.13:10:24.46#ibcon#read 4, iclass 16, count 2 2006.257.13:10:24.46#ibcon#about to read 5, iclass 16, count 2 2006.257.13:10:24.46#ibcon#read 5, iclass 16, count 2 2006.257.13:10:24.46#ibcon#about to read 6, iclass 16, count 2 2006.257.13:10:24.46#ibcon#read 6, iclass 16, count 2 2006.257.13:10:24.46#ibcon#end of sib2, iclass 16, count 2 2006.257.13:10:24.46#ibcon#*mode == 0, iclass 16, count 2 2006.257.13:10:24.46#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.13:10:24.46#ibcon#[25=AT07-04\r\n] 2006.257.13:10:24.46#ibcon#*before write, iclass 16, count 2 2006.257.13:10:24.46#ibcon#enter sib2, iclass 16, count 2 2006.257.13:10:24.46#ibcon#flushed, iclass 16, count 2 2006.257.13:10:24.46#ibcon#about to write, iclass 16, count 2 2006.257.13:10:24.46#ibcon#wrote, iclass 16, count 2 2006.257.13:10:24.46#ibcon#about to read 3, iclass 16, count 2 2006.257.13:10:24.49#ibcon#read 3, iclass 16, count 2 2006.257.13:10:24.49#ibcon#about to read 4, iclass 16, count 2 2006.257.13:10:24.49#ibcon#read 4, iclass 16, count 2 2006.257.13:10:24.49#ibcon#about to read 5, iclass 16, count 2 2006.257.13:10:24.49#ibcon#read 5, iclass 16, count 2 2006.257.13:10:24.49#ibcon#about to read 6, iclass 16, count 2 2006.257.13:10:24.49#ibcon#read 6, iclass 16, count 2 2006.257.13:10:24.49#ibcon#end of sib2, iclass 16, count 2 2006.257.13:10:24.49#ibcon#*after write, iclass 16, count 2 2006.257.13:10:24.49#ibcon#*before return 0, iclass 16, count 2 2006.257.13:10:24.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:24.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:24.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.13:10:24.49#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:24.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:24.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:24.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:24.61#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:10:24.61#ibcon#first serial, iclass 16, count 0 2006.257.13:10:24.61#ibcon#enter sib2, iclass 16, count 0 2006.257.13:10:24.61#ibcon#flushed, iclass 16, count 0 2006.257.13:10:24.61#ibcon#about to write, iclass 16, count 0 2006.257.13:10:24.61#ibcon#wrote, iclass 16, count 0 2006.257.13:10:24.61#ibcon#about to read 3, iclass 16, count 0 2006.257.13:10:24.63#ibcon#read 3, iclass 16, count 0 2006.257.13:10:24.63#ibcon#about to read 4, iclass 16, count 0 2006.257.13:10:24.63#ibcon#read 4, iclass 16, count 0 2006.257.13:10:24.63#ibcon#about to read 5, iclass 16, count 0 2006.257.13:10:24.63#ibcon#read 5, iclass 16, count 0 2006.257.13:10:24.63#ibcon#about to read 6, iclass 16, count 0 2006.257.13:10:24.63#ibcon#read 6, iclass 16, count 0 2006.257.13:10:24.63#ibcon#end of sib2, iclass 16, count 0 2006.257.13:10:24.63#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:10:24.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:10:24.63#ibcon#[25=USB\r\n] 2006.257.13:10:24.63#ibcon#*before write, iclass 16, count 0 2006.257.13:10:24.63#ibcon#enter sib2, iclass 16, count 0 2006.257.13:10:24.63#ibcon#flushed, iclass 16, count 0 2006.257.13:10:24.63#ibcon#about to write, iclass 16, count 0 2006.257.13:10:24.63#ibcon#wrote, iclass 16, count 0 2006.257.13:10:24.63#ibcon#about to read 3, iclass 16, count 0 2006.257.13:10:24.66#ibcon#read 3, iclass 16, count 0 2006.257.13:10:24.66#ibcon#about to read 4, iclass 16, count 0 2006.257.13:10:24.66#ibcon#read 4, iclass 16, count 0 2006.257.13:10:24.66#ibcon#about to read 5, iclass 16, count 0 2006.257.13:10:24.66#ibcon#read 5, iclass 16, count 0 2006.257.13:10:24.66#ibcon#about to read 6, iclass 16, count 0 2006.257.13:10:24.66#ibcon#read 6, iclass 16, count 0 2006.257.13:10:24.66#ibcon#end of sib2, iclass 16, count 0 2006.257.13:10:24.66#ibcon#*after write, iclass 16, count 0 2006.257.13:10:24.66#ibcon#*before return 0, iclass 16, count 0 2006.257.13:10:24.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:24.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:24.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:10:24.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:10:24.66$vck44/valo=8,884.99 2006.257.13:10:24.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.13:10:24.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.13:10:24.66#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:24.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:24.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:24.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:24.66#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:10:24.66#ibcon#first serial, iclass 18, count 0 2006.257.13:10:24.66#ibcon#enter sib2, iclass 18, count 0 2006.257.13:10:24.66#ibcon#flushed, iclass 18, count 0 2006.257.13:10:24.66#ibcon#about to write, iclass 18, count 0 2006.257.13:10:24.66#ibcon#wrote, iclass 18, count 0 2006.257.13:10:24.66#ibcon#about to read 3, iclass 18, count 0 2006.257.13:10:24.68#ibcon#read 3, iclass 18, count 0 2006.257.13:10:24.68#ibcon#about to read 4, iclass 18, count 0 2006.257.13:10:24.68#ibcon#read 4, iclass 18, count 0 2006.257.13:10:24.68#ibcon#about to read 5, iclass 18, count 0 2006.257.13:10:24.68#ibcon#read 5, iclass 18, count 0 2006.257.13:10:24.68#ibcon#about to read 6, iclass 18, count 0 2006.257.13:10:24.68#ibcon#read 6, iclass 18, count 0 2006.257.13:10:24.68#ibcon#end of sib2, iclass 18, count 0 2006.257.13:10:24.68#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:10:24.68#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:10:24.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:10:24.68#ibcon#*before write, iclass 18, count 0 2006.257.13:10:24.68#ibcon#enter sib2, iclass 18, count 0 2006.257.13:10:24.68#ibcon#flushed, iclass 18, count 0 2006.257.13:10:24.68#ibcon#about to write, iclass 18, count 0 2006.257.13:10:24.68#ibcon#wrote, iclass 18, count 0 2006.257.13:10:24.68#ibcon#about to read 3, iclass 18, count 0 2006.257.13:10:24.72#ibcon#read 3, iclass 18, count 0 2006.257.13:10:24.72#ibcon#about to read 4, iclass 18, count 0 2006.257.13:10:24.72#ibcon#read 4, iclass 18, count 0 2006.257.13:10:24.72#ibcon#about to read 5, iclass 18, count 0 2006.257.13:10:24.72#ibcon#read 5, iclass 18, count 0 2006.257.13:10:24.72#ibcon#about to read 6, iclass 18, count 0 2006.257.13:10:24.72#ibcon#read 6, iclass 18, count 0 2006.257.13:10:24.72#ibcon#end of sib2, iclass 18, count 0 2006.257.13:10:24.72#ibcon#*after write, iclass 18, count 0 2006.257.13:10:24.72#ibcon#*before return 0, iclass 18, count 0 2006.257.13:10:24.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:24.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:24.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:10:24.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:10:24.72$vck44/va=8,4 2006.257.13:10:24.72#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.13:10:24.72#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.13:10:24.72#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:24.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:10:24.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:10:24.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:10:24.78#ibcon#enter wrdev, iclass 20, count 2 2006.257.13:10:24.78#ibcon#first serial, iclass 20, count 2 2006.257.13:10:24.78#ibcon#enter sib2, iclass 20, count 2 2006.257.13:10:24.78#ibcon#flushed, iclass 20, count 2 2006.257.13:10:24.78#ibcon#about to write, iclass 20, count 2 2006.257.13:10:24.78#ibcon#wrote, iclass 20, count 2 2006.257.13:10:24.78#ibcon#about to read 3, iclass 20, count 2 2006.257.13:10:24.80#ibcon#read 3, iclass 20, count 2 2006.257.13:10:24.80#ibcon#about to read 4, iclass 20, count 2 2006.257.13:10:24.80#ibcon#read 4, iclass 20, count 2 2006.257.13:10:24.80#ibcon#about to read 5, iclass 20, count 2 2006.257.13:10:24.80#ibcon#read 5, iclass 20, count 2 2006.257.13:10:24.80#ibcon#about to read 6, iclass 20, count 2 2006.257.13:10:24.80#ibcon#read 6, iclass 20, count 2 2006.257.13:10:24.80#ibcon#end of sib2, iclass 20, count 2 2006.257.13:10:24.80#ibcon#*mode == 0, iclass 20, count 2 2006.257.13:10:24.80#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.13:10:24.80#ibcon#[25=AT08-04\r\n] 2006.257.13:10:24.80#ibcon#*before write, iclass 20, count 2 2006.257.13:10:24.80#ibcon#enter sib2, iclass 20, count 2 2006.257.13:10:24.80#ibcon#flushed, iclass 20, count 2 2006.257.13:10:24.80#ibcon#about to write, iclass 20, count 2 2006.257.13:10:24.80#ibcon#wrote, iclass 20, count 2 2006.257.13:10:24.80#ibcon#about to read 3, iclass 20, count 2 2006.257.13:10:24.83#ibcon#read 3, iclass 20, count 2 2006.257.13:10:24.83#ibcon#about to read 4, iclass 20, count 2 2006.257.13:10:24.83#ibcon#read 4, iclass 20, count 2 2006.257.13:10:24.83#ibcon#about to read 5, iclass 20, count 2 2006.257.13:10:24.83#ibcon#read 5, iclass 20, count 2 2006.257.13:10:24.83#ibcon#about to read 6, iclass 20, count 2 2006.257.13:10:24.83#ibcon#read 6, iclass 20, count 2 2006.257.13:10:24.83#ibcon#end of sib2, iclass 20, count 2 2006.257.13:10:24.83#ibcon#*after write, iclass 20, count 2 2006.257.13:10:24.83#ibcon#*before return 0, iclass 20, count 2 2006.257.13:10:24.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:10:24.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:10:24.83#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.13:10:24.83#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:24.83#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:10:24.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:10:24.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:10:24.95#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:10:24.95#ibcon#first serial, iclass 20, count 0 2006.257.13:10:24.95#ibcon#enter sib2, iclass 20, count 0 2006.257.13:10:24.95#ibcon#flushed, iclass 20, count 0 2006.257.13:10:24.95#ibcon#about to write, iclass 20, count 0 2006.257.13:10:24.95#ibcon#wrote, iclass 20, count 0 2006.257.13:10:24.95#ibcon#about to read 3, iclass 20, count 0 2006.257.13:10:24.97#ibcon#read 3, iclass 20, count 0 2006.257.13:10:24.97#ibcon#about to read 4, iclass 20, count 0 2006.257.13:10:24.97#ibcon#read 4, iclass 20, count 0 2006.257.13:10:24.97#ibcon#about to read 5, iclass 20, count 0 2006.257.13:10:24.97#ibcon#read 5, iclass 20, count 0 2006.257.13:10:24.97#ibcon#about to read 6, iclass 20, count 0 2006.257.13:10:24.97#ibcon#read 6, iclass 20, count 0 2006.257.13:10:24.97#ibcon#end of sib2, iclass 20, count 0 2006.257.13:10:24.97#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:10:24.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:10:24.97#ibcon#[25=USB\r\n] 2006.257.13:10:24.97#ibcon#*before write, iclass 20, count 0 2006.257.13:10:24.97#ibcon#enter sib2, iclass 20, count 0 2006.257.13:10:24.97#ibcon#flushed, iclass 20, count 0 2006.257.13:10:24.97#ibcon#about to write, iclass 20, count 0 2006.257.13:10:24.97#ibcon#wrote, iclass 20, count 0 2006.257.13:10:24.97#ibcon#about to read 3, iclass 20, count 0 2006.257.13:10:25.00#ibcon#read 3, iclass 20, count 0 2006.257.13:10:25.00#ibcon#about to read 4, iclass 20, count 0 2006.257.13:10:25.00#ibcon#read 4, iclass 20, count 0 2006.257.13:10:25.00#ibcon#about to read 5, iclass 20, count 0 2006.257.13:10:25.00#ibcon#read 5, iclass 20, count 0 2006.257.13:10:25.00#ibcon#about to read 6, iclass 20, count 0 2006.257.13:10:25.00#ibcon#read 6, iclass 20, count 0 2006.257.13:10:25.00#ibcon#end of sib2, iclass 20, count 0 2006.257.13:10:25.00#ibcon#*after write, iclass 20, count 0 2006.257.13:10:25.00#ibcon#*before return 0, iclass 20, count 0 2006.257.13:10:25.00#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:10:25.00#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:10:25.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:10:25.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:10:25.00$vck44/vblo=1,629.99 2006.257.13:10:25.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.13:10:25.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.13:10:25.00#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:25.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:25.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:25.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:25.00#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:10:25.00#ibcon#first serial, iclass 22, count 0 2006.257.13:10:25.00#ibcon#enter sib2, iclass 22, count 0 2006.257.13:10:25.00#ibcon#flushed, iclass 22, count 0 2006.257.13:10:25.00#ibcon#about to write, iclass 22, count 0 2006.257.13:10:25.00#ibcon#wrote, iclass 22, count 0 2006.257.13:10:25.00#ibcon#about to read 3, iclass 22, count 0 2006.257.13:10:25.02#ibcon#read 3, iclass 22, count 0 2006.257.13:10:25.02#ibcon#about to read 4, iclass 22, count 0 2006.257.13:10:25.02#ibcon#read 4, iclass 22, count 0 2006.257.13:10:25.02#ibcon#about to read 5, iclass 22, count 0 2006.257.13:10:25.02#ibcon#read 5, iclass 22, count 0 2006.257.13:10:25.02#ibcon#about to read 6, iclass 22, count 0 2006.257.13:10:25.02#ibcon#read 6, iclass 22, count 0 2006.257.13:10:25.02#ibcon#end of sib2, iclass 22, count 0 2006.257.13:10:25.02#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:10:25.02#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:10:25.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:10:25.02#ibcon#*before write, iclass 22, count 0 2006.257.13:10:25.02#ibcon#enter sib2, iclass 22, count 0 2006.257.13:10:25.02#ibcon#flushed, iclass 22, count 0 2006.257.13:10:25.02#ibcon#about to write, iclass 22, count 0 2006.257.13:10:25.02#ibcon#wrote, iclass 22, count 0 2006.257.13:10:25.02#ibcon#about to read 3, iclass 22, count 0 2006.257.13:10:25.06#ibcon#read 3, iclass 22, count 0 2006.257.13:10:25.06#ibcon#about to read 4, iclass 22, count 0 2006.257.13:10:25.06#ibcon#read 4, iclass 22, count 0 2006.257.13:10:25.06#ibcon#about to read 5, iclass 22, count 0 2006.257.13:10:25.06#ibcon#read 5, iclass 22, count 0 2006.257.13:10:25.06#ibcon#about to read 6, iclass 22, count 0 2006.257.13:10:25.06#ibcon#read 6, iclass 22, count 0 2006.257.13:10:25.06#ibcon#end of sib2, iclass 22, count 0 2006.257.13:10:25.06#ibcon#*after write, iclass 22, count 0 2006.257.13:10:25.06#ibcon#*before return 0, iclass 22, count 0 2006.257.13:10:25.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:25.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:10:25.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:10:25.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:10:25.06$vck44/vb=1,4 2006.257.13:10:25.06#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.13:10:25.06#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.13:10:25.06#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:25.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:25.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:25.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:25.06#ibcon#enter wrdev, iclass 24, count 2 2006.257.13:10:25.06#ibcon#first serial, iclass 24, count 2 2006.257.13:10:25.06#ibcon#enter sib2, iclass 24, count 2 2006.257.13:10:25.06#ibcon#flushed, iclass 24, count 2 2006.257.13:10:25.06#ibcon#about to write, iclass 24, count 2 2006.257.13:10:25.06#ibcon#wrote, iclass 24, count 2 2006.257.13:10:25.06#ibcon#about to read 3, iclass 24, count 2 2006.257.13:10:25.08#ibcon#read 3, iclass 24, count 2 2006.257.13:10:25.08#ibcon#about to read 4, iclass 24, count 2 2006.257.13:10:25.08#ibcon#read 4, iclass 24, count 2 2006.257.13:10:25.08#ibcon#about to read 5, iclass 24, count 2 2006.257.13:10:25.08#ibcon#read 5, iclass 24, count 2 2006.257.13:10:25.08#ibcon#about to read 6, iclass 24, count 2 2006.257.13:10:25.08#ibcon#read 6, iclass 24, count 2 2006.257.13:10:25.08#ibcon#end of sib2, iclass 24, count 2 2006.257.13:10:25.08#ibcon#*mode == 0, iclass 24, count 2 2006.257.13:10:25.08#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.13:10:25.08#ibcon#[27=AT01-04\r\n] 2006.257.13:10:25.08#ibcon#*before write, iclass 24, count 2 2006.257.13:10:25.08#ibcon#enter sib2, iclass 24, count 2 2006.257.13:10:25.08#ibcon#flushed, iclass 24, count 2 2006.257.13:10:25.08#ibcon#about to write, iclass 24, count 2 2006.257.13:10:25.08#ibcon#wrote, iclass 24, count 2 2006.257.13:10:25.08#ibcon#about to read 3, iclass 24, count 2 2006.257.13:10:25.11#ibcon#read 3, iclass 24, count 2 2006.257.13:10:25.11#ibcon#about to read 4, iclass 24, count 2 2006.257.13:10:25.11#ibcon#read 4, iclass 24, count 2 2006.257.13:10:25.11#ibcon#about to read 5, iclass 24, count 2 2006.257.13:10:25.11#ibcon#read 5, iclass 24, count 2 2006.257.13:10:25.11#ibcon#about to read 6, iclass 24, count 2 2006.257.13:10:25.11#ibcon#read 6, iclass 24, count 2 2006.257.13:10:25.11#ibcon#end of sib2, iclass 24, count 2 2006.257.13:10:25.11#ibcon#*after write, iclass 24, count 2 2006.257.13:10:25.11#ibcon#*before return 0, iclass 24, count 2 2006.257.13:10:25.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:25.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:10:25.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.13:10:25.11#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:25.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:25.23#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:25.23#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:25.23#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:10:25.23#ibcon#first serial, iclass 24, count 0 2006.257.13:10:25.23#ibcon#enter sib2, iclass 24, count 0 2006.257.13:10:25.23#ibcon#flushed, iclass 24, count 0 2006.257.13:10:25.23#ibcon#about to write, iclass 24, count 0 2006.257.13:10:25.23#ibcon#wrote, iclass 24, count 0 2006.257.13:10:25.23#ibcon#about to read 3, iclass 24, count 0 2006.257.13:10:25.25#ibcon#read 3, iclass 24, count 0 2006.257.13:10:25.25#ibcon#about to read 4, iclass 24, count 0 2006.257.13:10:25.25#ibcon#read 4, iclass 24, count 0 2006.257.13:10:25.25#ibcon#about to read 5, iclass 24, count 0 2006.257.13:10:25.25#ibcon#read 5, iclass 24, count 0 2006.257.13:10:25.25#ibcon#about to read 6, iclass 24, count 0 2006.257.13:10:25.25#ibcon#read 6, iclass 24, count 0 2006.257.13:10:25.25#ibcon#end of sib2, iclass 24, count 0 2006.257.13:10:25.25#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:10:25.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:10:25.25#ibcon#[27=USB\r\n] 2006.257.13:10:25.25#ibcon#*before write, iclass 24, count 0 2006.257.13:10:25.25#ibcon#enter sib2, iclass 24, count 0 2006.257.13:10:25.25#ibcon#flushed, iclass 24, count 0 2006.257.13:10:25.25#ibcon#about to write, iclass 24, count 0 2006.257.13:10:25.25#ibcon#wrote, iclass 24, count 0 2006.257.13:10:25.25#ibcon#about to read 3, iclass 24, count 0 2006.257.13:10:25.28#ibcon#read 3, iclass 24, count 0 2006.257.13:10:25.28#ibcon#about to read 4, iclass 24, count 0 2006.257.13:10:25.28#ibcon#read 4, iclass 24, count 0 2006.257.13:10:25.28#ibcon#about to read 5, iclass 24, count 0 2006.257.13:10:25.28#ibcon#read 5, iclass 24, count 0 2006.257.13:10:25.28#ibcon#about to read 6, iclass 24, count 0 2006.257.13:10:25.28#ibcon#read 6, iclass 24, count 0 2006.257.13:10:25.28#ibcon#end of sib2, iclass 24, count 0 2006.257.13:10:25.28#ibcon#*after write, iclass 24, count 0 2006.257.13:10:25.28#ibcon#*before return 0, iclass 24, count 0 2006.257.13:10:25.28#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:25.28#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:10:25.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:10:25.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:10:25.28$vck44/vblo=2,634.99 2006.257.13:10:25.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.13:10:25.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.13:10:25.28#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:25.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:25.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:25.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:25.28#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:10:25.28#ibcon#first serial, iclass 26, count 0 2006.257.13:10:25.28#ibcon#enter sib2, iclass 26, count 0 2006.257.13:10:25.28#ibcon#flushed, iclass 26, count 0 2006.257.13:10:25.28#ibcon#about to write, iclass 26, count 0 2006.257.13:10:25.28#ibcon#wrote, iclass 26, count 0 2006.257.13:10:25.28#ibcon#about to read 3, iclass 26, count 0 2006.257.13:10:25.30#ibcon#read 3, iclass 26, count 0 2006.257.13:10:25.30#ibcon#about to read 4, iclass 26, count 0 2006.257.13:10:25.30#ibcon#read 4, iclass 26, count 0 2006.257.13:10:25.30#ibcon#about to read 5, iclass 26, count 0 2006.257.13:10:25.30#ibcon#read 5, iclass 26, count 0 2006.257.13:10:25.30#ibcon#about to read 6, iclass 26, count 0 2006.257.13:10:25.30#ibcon#read 6, iclass 26, count 0 2006.257.13:10:25.30#ibcon#end of sib2, iclass 26, count 0 2006.257.13:10:25.30#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:10:25.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:10:25.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:10:25.30#ibcon#*before write, iclass 26, count 0 2006.257.13:10:25.30#ibcon#enter sib2, iclass 26, count 0 2006.257.13:10:25.30#ibcon#flushed, iclass 26, count 0 2006.257.13:10:25.30#ibcon#about to write, iclass 26, count 0 2006.257.13:10:25.30#ibcon#wrote, iclass 26, count 0 2006.257.13:10:25.30#ibcon#about to read 3, iclass 26, count 0 2006.257.13:10:25.34#ibcon#read 3, iclass 26, count 0 2006.257.13:10:25.34#ibcon#about to read 4, iclass 26, count 0 2006.257.13:10:25.34#ibcon#read 4, iclass 26, count 0 2006.257.13:10:25.34#ibcon#about to read 5, iclass 26, count 0 2006.257.13:10:25.34#ibcon#read 5, iclass 26, count 0 2006.257.13:10:25.34#ibcon#about to read 6, iclass 26, count 0 2006.257.13:10:25.34#ibcon#read 6, iclass 26, count 0 2006.257.13:10:25.34#ibcon#end of sib2, iclass 26, count 0 2006.257.13:10:25.34#ibcon#*after write, iclass 26, count 0 2006.257.13:10:25.34#ibcon#*before return 0, iclass 26, count 0 2006.257.13:10:25.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:25.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:10:25.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:10:25.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:10:25.34$vck44/vb=2,5 2006.257.13:10:25.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.13:10:25.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.13:10:25.34#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:25.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:25.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:25.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:25.40#ibcon#enter wrdev, iclass 28, count 2 2006.257.13:10:25.40#ibcon#first serial, iclass 28, count 2 2006.257.13:10:25.40#ibcon#enter sib2, iclass 28, count 2 2006.257.13:10:25.40#ibcon#flushed, iclass 28, count 2 2006.257.13:10:25.40#ibcon#about to write, iclass 28, count 2 2006.257.13:10:25.40#ibcon#wrote, iclass 28, count 2 2006.257.13:10:25.40#ibcon#about to read 3, iclass 28, count 2 2006.257.13:10:25.42#ibcon#read 3, iclass 28, count 2 2006.257.13:10:25.42#ibcon#about to read 4, iclass 28, count 2 2006.257.13:10:25.42#ibcon#read 4, iclass 28, count 2 2006.257.13:10:25.42#ibcon#about to read 5, iclass 28, count 2 2006.257.13:10:25.42#ibcon#read 5, iclass 28, count 2 2006.257.13:10:25.42#ibcon#about to read 6, iclass 28, count 2 2006.257.13:10:25.42#ibcon#read 6, iclass 28, count 2 2006.257.13:10:25.42#ibcon#end of sib2, iclass 28, count 2 2006.257.13:10:25.42#ibcon#*mode == 0, iclass 28, count 2 2006.257.13:10:25.42#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.13:10:25.42#ibcon#[27=AT02-05\r\n] 2006.257.13:10:25.42#ibcon#*before write, iclass 28, count 2 2006.257.13:10:25.42#ibcon#enter sib2, iclass 28, count 2 2006.257.13:10:25.42#ibcon#flushed, iclass 28, count 2 2006.257.13:10:25.42#ibcon#about to write, iclass 28, count 2 2006.257.13:10:25.42#ibcon#wrote, iclass 28, count 2 2006.257.13:10:25.42#ibcon#about to read 3, iclass 28, count 2 2006.257.13:10:25.45#ibcon#read 3, iclass 28, count 2 2006.257.13:10:25.45#ibcon#about to read 4, iclass 28, count 2 2006.257.13:10:25.45#ibcon#read 4, iclass 28, count 2 2006.257.13:10:25.45#ibcon#about to read 5, iclass 28, count 2 2006.257.13:10:25.45#ibcon#read 5, iclass 28, count 2 2006.257.13:10:25.45#ibcon#about to read 6, iclass 28, count 2 2006.257.13:10:25.45#ibcon#read 6, iclass 28, count 2 2006.257.13:10:25.45#ibcon#end of sib2, iclass 28, count 2 2006.257.13:10:25.45#ibcon#*after write, iclass 28, count 2 2006.257.13:10:25.45#ibcon#*before return 0, iclass 28, count 2 2006.257.13:10:25.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:25.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:10:25.45#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.13:10:25.45#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:25.45#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:25.57#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:25.57#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:25.57#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:10:25.57#ibcon#first serial, iclass 28, count 0 2006.257.13:10:25.57#ibcon#enter sib2, iclass 28, count 0 2006.257.13:10:25.57#ibcon#flushed, iclass 28, count 0 2006.257.13:10:25.57#ibcon#about to write, iclass 28, count 0 2006.257.13:10:25.57#ibcon#wrote, iclass 28, count 0 2006.257.13:10:25.57#ibcon#about to read 3, iclass 28, count 0 2006.257.13:10:25.59#ibcon#read 3, iclass 28, count 0 2006.257.13:10:25.59#ibcon#about to read 4, iclass 28, count 0 2006.257.13:10:25.59#ibcon#read 4, iclass 28, count 0 2006.257.13:10:25.59#ibcon#about to read 5, iclass 28, count 0 2006.257.13:10:25.59#ibcon#read 5, iclass 28, count 0 2006.257.13:10:25.59#ibcon#about to read 6, iclass 28, count 0 2006.257.13:10:25.59#ibcon#read 6, iclass 28, count 0 2006.257.13:10:25.59#ibcon#end of sib2, iclass 28, count 0 2006.257.13:10:25.59#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:10:25.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:10:25.59#ibcon#[27=USB\r\n] 2006.257.13:10:25.59#ibcon#*before write, iclass 28, count 0 2006.257.13:10:25.59#ibcon#enter sib2, iclass 28, count 0 2006.257.13:10:25.59#ibcon#flushed, iclass 28, count 0 2006.257.13:10:25.59#ibcon#about to write, iclass 28, count 0 2006.257.13:10:25.59#ibcon#wrote, iclass 28, count 0 2006.257.13:10:25.59#ibcon#about to read 3, iclass 28, count 0 2006.257.13:10:25.62#ibcon#read 3, iclass 28, count 0 2006.257.13:10:25.62#ibcon#about to read 4, iclass 28, count 0 2006.257.13:10:25.62#ibcon#read 4, iclass 28, count 0 2006.257.13:10:25.62#ibcon#about to read 5, iclass 28, count 0 2006.257.13:10:25.62#ibcon#read 5, iclass 28, count 0 2006.257.13:10:25.62#ibcon#about to read 6, iclass 28, count 0 2006.257.13:10:25.62#ibcon#read 6, iclass 28, count 0 2006.257.13:10:25.62#ibcon#end of sib2, iclass 28, count 0 2006.257.13:10:25.62#ibcon#*after write, iclass 28, count 0 2006.257.13:10:25.62#ibcon#*before return 0, iclass 28, count 0 2006.257.13:10:25.62#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:25.62#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:10:25.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:10:25.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:10:25.62$vck44/vblo=3,649.99 2006.257.13:10:25.62#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.13:10:25.62#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.13:10:25.62#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:25.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:25.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:25.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:25.62#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:10:25.62#ibcon#first serial, iclass 30, count 0 2006.257.13:10:25.62#ibcon#enter sib2, iclass 30, count 0 2006.257.13:10:25.62#ibcon#flushed, iclass 30, count 0 2006.257.13:10:25.62#ibcon#about to write, iclass 30, count 0 2006.257.13:10:25.62#ibcon#wrote, iclass 30, count 0 2006.257.13:10:25.62#ibcon#about to read 3, iclass 30, count 0 2006.257.13:10:25.64#ibcon#read 3, iclass 30, count 0 2006.257.13:10:25.64#ibcon#about to read 4, iclass 30, count 0 2006.257.13:10:25.64#ibcon#read 4, iclass 30, count 0 2006.257.13:10:25.64#ibcon#about to read 5, iclass 30, count 0 2006.257.13:10:25.64#ibcon#read 5, iclass 30, count 0 2006.257.13:10:25.64#ibcon#about to read 6, iclass 30, count 0 2006.257.13:10:25.64#ibcon#read 6, iclass 30, count 0 2006.257.13:10:25.64#ibcon#end of sib2, iclass 30, count 0 2006.257.13:10:25.64#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:10:25.64#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:10:25.64#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:10:25.64#ibcon#*before write, iclass 30, count 0 2006.257.13:10:25.64#ibcon#enter sib2, iclass 30, count 0 2006.257.13:10:25.64#ibcon#flushed, iclass 30, count 0 2006.257.13:10:25.64#ibcon#about to write, iclass 30, count 0 2006.257.13:10:25.64#ibcon#wrote, iclass 30, count 0 2006.257.13:10:25.64#ibcon#about to read 3, iclass 30, count 0 2006.257.13:10:25.68#ibcon#read 3, iclass 30, count 0 2006.257.13:10:25.68#ibcon#about to read 4, iclass 30, count 0 2006.257.13:10:25.68#ibcon#read 4, iclass 30, count 0 2006.257.13:10:25.68#ibcon#about to read 5, iclass 30, count 0 2006.257.13:10:25.68#ibcon#read 5, iclass 30, count 0 2006.257.13:10:25.68#ibcon#about to read 6, iclass 30, count 0 2006.257.13:10:25.68#ibcon#read 6, iclass 30, count 0 2006.257.13:10:25.68#ibcon#end of sib2, iclass 30, count 0 2006.257.13:10:25.68#ibcon#*after write, iclass 30, count 0 2006.257.13:10:25.68#ibcon#*before return 0, iclass 30, count 0 2006.257.13:10:25.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:25.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:10:25.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:10:25.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:10:25.68$vck44/vb=3,4 2006.257.13:10:25.68#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.13:10:25.68#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.13:10:25.68#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:25.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:25.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:25.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:25.74#ibcon#enter wrdev, iclass 32, count 2 2006.257.13:10:25.74#ibcon#first serial, iclass 32, count 2 2006.257.13:10:25.74#ibcon#enter sib2, iclass 32, count 2 2006.257.13:10:25.74#ibcon#flushed, iclass 32, count 2 2006.257.13:10:25.74#ibcon#about to write, iclass 32, count 2 2006.257.13:10:25.74#ibcon#wrote, iclass 32, count 2 2006.257.13:10:25.74#ibcon#about to read 3, iclass 32, count 2 2006.257.13:10:25.76#ibcon#read 3, iclass 32, count 2 2006.257.13:10:25.76#ibcon#about to read 4, iclass 32, count 2 2006.257.13:10:25.76#ibcon#read 4, iclass 32, count 2 2006.257.13:10:25.76#ibcon#about to read 5, iclass 32, count 2 2006.257.13:10:25.76#ibcon#read 5, iclass 32, count 2 2006.257.13:10:25.76#ibcon#about to read 6, iclass 32, count 2 2006.257.13:10:25.76#ibcon#read 6, iclass 32, count 2 2006.257.13:10:25.76#ibcon#end of sib2, iclass 32, count 2 2006.257.13:10:25.76#ibcon#*mode == 0, iclass 32, count 2 2006.257.13:10:25.76#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.13:10:25.76#ibcon#[27=AT03-04\r\n] 2006.257.13:10:25.76#ibcon#*before write, iclass 32, count 2 2006.257.13:10:25.76#ibcon#enter sib2, iclass 32, count 2 2006.257.13:10:25.76#ibcon#flushed, iclass 32, count 2 2006.257.13:10:25.76#ibcon#about to write, iclass 32, count 2 2006.257.13:10:25.76#ibcon#wrote, iclass 32, count 2 2006.257.13:10:25.76#ibcon#about to read 3, iclass 32, count 2 2006.257.13:10:25.79#ibcon#read 3, iclass 32, count 2 2006.257.13:10:25.79#ibcon#about to read 4, iclass 32, count 2 2006.257.13:10:25.79#ibcon#read 4, iclass 32, count 2 2006.257.13:10:25.79#ibcon#about to read 5, iclass 32, count 2 2006.257.13:10:25.79#ibcon#read 5, iclass 32, count 2 2006.257.13:10:25.79#ibcon#about to read 6, iclass 32, count 2 2006.257.13:10:25.79#ibcon#read 6, iclass 32, count 2 2006.257.13:10:25.79#ibcon#end of sib2, iclass 32, count 2 2006.257.13:10:25.79#ibcon#*after write, iclass 32, count 2 2006.257.13:10:25.79#ibcon#*before return 0, iclass 32, count 2 2006.257.13:10:25.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:25.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:10:25.79#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.13:10:25.79#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:25.79#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:25.91#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:25.91#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:25.91#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:10:25.91#ibcon#first serial, iclass 32, count 0 2006.257.13:10:25.91#ibcon#enter sib2, iclass 32, count 0 2006.257.13:10:25.91#ibcon#flushed, iclass 32, count 0 2006.257.13:10:25.91#ibcon#about to write, iclass 32, count 0 2006.257.13:10:25.91#ibcon#wrote, iclass 32, count 0 2006.257.13:10:25.91#ibcon#about to read 3, iclass 32, count 0 2006.257.13:10:25.93#ibcon#read 3, iclass 32, count 0 2006.257.13:10:25.93#ibcon#about to read 4, iclass 32, count 0 2006.257.13:10:25.93#ibcon#read 4, iclass 32, count 0 2006.257.13:10:25.93#ibcon#about to read 5, iclass 32, count 0 2006.257.13:10:25.93#ibcon#read 5, iclass 32, count 0 2006.257.13:10:25.93#ibcon#about to read 6, iclass 32, count 0 2006.257.13:10:25.93#ibcon#read 6, iclass 32, count 0 2006.257.13:10:25.93#ibcon#end of sib2, iclass 32, count 0 2006.257.13:10:25.93#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:10:25.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:10:25.93#ibcon#[27=USB\r\n] 2006.257.13:10:25.93#ibcon#*before write, iclass 32, count 0 2006.257.13:10:25.93#ibcon#enter sib2, iclass 32, count 0 2006.257.13:10:25.93#ibcon#flushed, iclass 32, count 0 2006.257.13:10:25.93#ibcon#about to write, iclass 32, count 0 2006.257.13:10:25.93#ibcon#wrote, iclass 32, count 0 2006.257.13:10:25.93#ibcon#about to read 3, iclass 32, count 0 2006.257.13:10:25.96#ibcon#read 3, iclass 32, count 0 2006.257.13:10:25.96#ibcon#about to read 4, iclass 32, count 0 2006.257.13:10:25.96#ibcon#read 4, iclass 32, count 0 2006.257.13:10:25.96#ibcon#about to read 5, iclass 32, count 0 2006.257.13:10:25.96#ibcon#read 5, iclass 32, count 0 2006.257.13:10:25.96#ibcon#about to read 6, iclass 32, count 0 2006.257.13:10:25.96#ibcon#read 6, iclass 32, count 0 2006.257.13:10:25.96#ibcon#end of sib2, iclass 32, count 0 2006.257.13:10:25.96#ibcon#*after write, iclass 32, count 0 2006.257.13:10:25.96#ibcon#*before return 0, iclass 32, count 0 2006.257.13:10:25.96#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:25.96#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:10:25.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:10:25.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:10:25.96$vck44/vblo=4,679.99 2006.257.13:10:25.96#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.13:10:25.96#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.13:10:25.96#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:25.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:10:25.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:10:25.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:10:25.96#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:10:25.96#ibcon#first serial, iclass 34, count 0 2006.257.13:10:25.96#ibcon#enter sib2, iclass 34, count 0 2006.257.13:10:25.96#ibcon#flushed, iclass 34, count 0 2006.257.13:10:25.96#ibcon#about to write, iclass 34, count 0 2006.257.13:10:25.96#ibcon#wrote, iclass 34, count 0 2006.257.13:10:25.96#ibcon#about to read 3, iclass 34, count 0 2006.257.13:10:25.98#ibcon#read 3, iclass 34, count 0 2006.257.13:10:25.98#ibcon#about to read 4, iclass 34, count 0 2006.257.13:10:25.98#ibcon#read 4, iclass 34, count 0 2006.257.13:10:25.98#ibcon#about to read 5, iclass 34, count 0 2006.257.13:10:25.98#ibcon#read 5, iclass 34, count 0 2006.257.13:10:25.98#ibcon#about to read 6, iclass 34, count 0 2006.257.13:10:25.98#ibcon#read 6, iclass 34, count 0 2006.257.13:10:25.98#ibcon#end of sib2, iclass 34, count 0 2006.257.13:10:25.98#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:10:25.98#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:10:25.98#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:10:25.98#ibcon#*before write, iclass 34, count 0 2006.257.13:10:25.98#ibcon#enter sib2, iclass 34, count 0 2006.257.13:10:25.98#ibcon#flushed, iclass 34, count 0 2006.257.13:10:25.98#ibcon#about to write, iclass 34, count 0 2006.257.13:10:25.98#ibcon#wrote, iclass 34, count 0 2006.257.13:10:25.98#ibcon#about to read 3, iclass 34, count 0 2006.257.13:10:26.02#ibcon#read 3, iclass 34, count 0 2006.257.13:10:26.02#ibcon#about to read 4, iclass 34, count 0 2006.257.13:10:26.02#ibcon#read 4, iclass 34, count 0 2006.257.13:10:26.02#ibcon#about to read 5, iclass 34, count 0 2006.257.13:10:26.02#ibcon#read 5, iclass 34, count 0 2006.257.13:10:26.02#ibcon#about to read 6, iclass 34, count 0 2006.257.13:10:26.02#ibcon#read 6, iclass 34, count 0 2006.257.13:10:26.02#ibcon#end of sib2, iclass 34, count 0 2006.257.13:10:26.02#ibcon#*after write, iclass 34, count 0 2006.257.13:10:26.02#ibcon#*before return 0, iclass 34, count 0 2006.257.13:10:26.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:10:26.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:10:26.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:10:26.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:10:26.02$vck44/vb=4,5 2006.257.13:10:26.02#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.13:10:26.02#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.13:10:26.02#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:26.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:10:26.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:10:26.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:10:26.08#ibcon#enter wrdev, iclass 36, count 2 2006.257.13:10:26.08#ibcon#first serial, iclass 36, count 2 2006.257.13:10:26.08#ibcon#enter sib2, iclass 36, count 2 2006.257.13:10:26.08#ibcon#flushed, iclass 36, count 2 2006.257.13:10:26.08#ibcon#about to write, iclass 36, count 2 2006.257.13:10:26.08#ibcon#wrote, iclass 36, count 2 2006.257.13:10:26.08#ibcon#about to read 3, iclass 36, count 2 2006.257.13:10:26.10#ibcon#read 3, iclass 36, count 2 2006.257.13:10:26.10#ibcon#about to read 4, iclass 36, count 2 2006.257.13:10:26.10#ibcon#read 4, iclass 36, count 2 2006.257.13:10:26.10#ibcon#about to read 5, iclass 36, count 2 2006.257.13:10:26.10#ibcon#read 5, iclass 36, count 2 2006.257.13:10:26.10#ibcon#about to read 6, iclass 36, count 2 2006.257.13:10:26.10#ibcon#read 6, iclass 36, count 2 2006.257.13:10:26.10#ibcon#end of sib2, iclass 36, count 2 2006.257.13:10:26.10#ibcon#*mode == 0, iclass 36, count 2 2006.257.13:10:26.10#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.13:10:26.10#ibcon#[27=AT04-05\r\n] 2006.257.13:10:26.10#ibcon#*before write, iclass 36, count 2 2006.257.13:10:26.10#ibcon#enter sib2, iclass 36, count 2 2006.257.13:10:26.10#ibcon#flushed, iclass 36, count 2 2006.257.13:10:26.10#ibcon#about to write, iclass 36, count 2 2006.257.13:10:26.10#ibcon#wrote, iclass 36, count 2 2006.257.13:10:26.10#ibcon#about to read 3, iclass 36, count 2 2006.257.13:10:26.13#ibcon#read 3, iclass 36, count 2 2006.257.13:10:26.13#ibcon#about to read 4, iclass 36, count 2 2006.257.13:10:26.13#ibcon#read 4, iclass 36, count 2 2006.257.13:10:26.13#ibcon#about to read 5, iclass 36, count 2 2006.257.13:10:26.13#ibcon#read 5, iclass 36, count 2 2006.257.13:10:26.13#ibcon#about to read 6, iclass 36, count 2 2006.257.13:10:26.13#ibcon#read 6, iclass 36, count 2 2006.257.13:10:26.13#ibcon#end of sib2, iclass 36, count 2 2006.257.13:10:26.13#ibcon#*after write, iclass 36, count 2 2006.257.13:10:26.13#ibcon#*before return 0, iclass 36, count 2 2006.257.13:10:26.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:10:26.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:10:26.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.13:10:26.13#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:26.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:10:26.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:10:26.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:10:26.25#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:10:26.25#ibcon#first serial, iclass 36, count 0 2006.257.13:10:26.25#ibcon#enter sib2, iclass 36, count 0 2006.257.13:10:26.25#ibcon#flushed, iclass 36, count 0 2006.257.13:10:26.25#ibcon#about to write, iclass 36, count 0 2006.257.13:10:26.25#ibcon#wrote, iclass 36, count 0 2006.257.13:10:26.25#ibcon#about to read 3, iclass 36, count 0 2006.257.13:10:26.27#ibcon#read 3, iclass 36, count 0 2006.257.13:10:26.27#ibcon#about to read 4, iclass 36, count 0 2006.257.13:10:26.27#ibcon#read 4, iclass 36, count 0 2006.257.13:10:26.27#ibcon#about to read 5, iclass 36, count 0 2006.257.13:10:26.27#ibcon#read 5, iclass 36, count 0 2006.257.13:10:26.27#ibcon#about to read 6, iclass 36, count 0 2006.257.13:10:26.27#ibcon#read 6, iclass 36, count 0 2006.257.13:10:26.27#ibcon#end of sib2, iclass 36, count 0 2006.257.13:10:26.27#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:10:26.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:10:26.27#ibcon#[27=USB\r\n] 2006.257.13:10:26.27#ibcon#*before write, iclass 36, count 0 2006.257.13:10:26.27#ibcon#enter sib2, iclass 36, count 0 2006.257.13:10:26.27#ibcon#flushed, iclass 36, count 0 2006.257.13:10:26.27#ibcon#about to write, iclass 36, count 0 2006.257.13:10:26.27#ibcon#wrote, iclass 36, count 0 2006.257.13:10:26.27#ibcon#about to read 3, iclass 36, count 0 2006.257.13:10:26.30#ibcon#read 3, iclass 36, count 0 2006.257.13:10:26.30#ibcon#about to read 4, iclass 36, count 0 2006.257.13:10:26.30#ibcon#read 4, iclass 36, count 0 2006.257.13:10:26.30#ibcon#about to read 5, iclass 36, count 0 2006.257.13:10:26.30#ibcon#read 5, iclass 36, count 0 2006.257.13:10:26.30#ibcon#about to read 6, iclass 36, count 0 2006.257.13:10:26.30#ibcon#read 6, iclass 36, count 0 2006.257.13:10:26.30#ibcon#end of sib2, iclass 36, count 0 2006.257.13:10:26.30#ibcon#*after write, iclass 36, count 0 2006.257.13:10:26.30#ibcon#*before return 0, iclass 36, count 0 2006.257.13:10:26.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:10:26.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:10:26.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:10:26.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:10:26.30$vck44/vblo=5,709.99 2006.257.13:10:26.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.13:10:26.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.13:10:26.30#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:26.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:26.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:26.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:26.30#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:10:26.30#ibcon#first serial, iclass 38, count 0 2006.257.13:10:26.30#ibcon#enter sib2, iclass 38, count 0 2006.257.13:10:26.30#ibcon#flushed, iclass 38, count 0 2006.257.13:10:26.30#ibcon#about to write, iclass 38, count 0 2006.257.13:10:26.30#ibcon#wrote, iclass 38, count 0 2006.257.13:10:26.30#ibcon#about to read 3, iclass 38, count 0 2006.257.13:10:26.32#ibcon#read 3, iclass 38, count 0 2006.257.13:10:26.32#ibcon#about to read 4, iclass 38, count 0 2006.257.13:10:26.32#ibcon#read 4, iclass 38, count 0 2006.257.13:10:26.32#ibcon#about to read 5, iclass 38, count 0 2006.257.13:10:26.32#ibcon#read 5, iclass 38, count 0 2006.257.13:10:26.32#ibcon#about to read 6, iclass 38, count 0 2006.257.13:10:26.32#ibcon#read 6, iclass 38, count 0 2006.257.13:10:26.32#ibcon#end of sib2, iclass 38, count 0 2006.257.13:10:26.32#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:10:26.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:10:26.32#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:10:26.32#ibcon#*before write, iclass 38, count 0 2006.257.13:10:26.32#ibcon#enter sib2, iclass 38, count 0 2006.257.13:10:26.32#ibcon#flushed, iclass 38, count 0 2006.257.13:10:26.32#ibcon#about to write, iclass 38, count 0 2006.257.13:10:26.32#ibcon#wrote, iclass 38, count 0 2006.257.13:10:26.32#ibcon#about to read 3, iclass 38, count 0 2006.257.13:10:26.36#ibcon#read 3, iclass 38, count 0 2006.257.13:10:26.36#ibcon#about to read 4, iclass 38, count 0 2006.257.13:10:26.36#ibcon#read 4, iclass 38, count 0 2006.257.13:10:26.36#ibcon#about to read 5, iclass 38, count 0 2006.257.13:10:26.36#ibcon#read 5, iclass 38, count 0 2006.257.13:10:26.36#ibcon#about to read 6, iclass 38, count 0 2006.257.13:10:26.36#ibcon#read 6, iclass 38, count 0 2006.257.13:10:26.36#ibcon#end of sib2, iclass 38, count 0 2006.257.13:10:26.36#ibcon#*after write, iclass 38, count 0 2006.257.13:10:26.36#ibcon#*before return 0, iclass 38, count 0 2006.257.13:10:26.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:26.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:10:26.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:10:26.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:10:26.36$vck44/vb=5,4 2006.257.13:10:26.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.13:10:26.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.13:10:26.36#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:26.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:26.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:26.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:26.42#ibcon#enter wrdev, iclass 40, count 2 2006.257.13:10:26.42#ibcon#first serial, iclass 40, count 2 2006.257.13:10:26.42#ibcon#enter sib2, iclass 40, count 2 2006.257.13:10:26.42#ibcon#flushed, iclass 40, count 2 2006.257.13:10:26.42#ibcon#about to write, iclass 40, count 2 2006.257.13:10:26.42#ibcon#wrote, iclass 40, count 2 2006.257.13:10:26.42#ibcon#about to read 3, iclass 40, count 2 2006.257.13:10:26.44#ibcon#read 3, iclass 40, count 2 2006.257.13:10:26.44#ibcon#about to read 4, iclass 40, count 2 2006.257.13:10:26.44#ibcon#read 4, iclass 40, count 2 2006.257.13:10:26.44#ibcon#about to read 5, iclass 40, count 2 2006.257.13:10:26.44#ibcon#read 5, iclass 40, count 2 2006.257.13:10:26.44#ibcon#about to read 6, iclass 40, count 2 2006.257.13:10:26.44#ibcon#read 6, iclass 40, count 2 2006.257.13:10:26.44#ibcon#end of sib2, iclass 40, count 2 2006.257.13:10:26.44#ibcon#*mode == 0, iclass 40, count 2 2006.257.13:10:26.44#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.13:10:26.44#ibcon#[27=AT05-04\r\n] 2006.257.13:10:26.44#ibcon#*before write, iclass 40, count 2 2006.257.13:10:26.44#ibcon#enter sib2, iclass 40, count 2 2006.257.13:10:26.44#ibcon#flushed, iclass 40, count 2 2006.257.13:10:26.44#ibcon#about to write, iclass 40, count 2 2006.257.13:10:26.44#ibcon#wrote, iclass 40, count 2 2006.257.13:10:26.44#ibcon#about to read 3, iclass 40, count 2 2006.257.13:10:26.47#ibcon#read 3, iclass 40, count 2 2006.257.13:10:26.47#ibcon#about to read 4, iclass 40, count 2 2006.257.13:10:26.47#ibcon#read 4, iclass 40, count 2 2006.257.13:10:26.47#ibcon#about to read 5, iclass 40, count 2 2006.257.13:10:26.47#ibcon#read 5, iclass 40, count 2 2006.257.13:10:26.47#ibcon#about to read 6, iclass 40, count 2 2006.257.13:10:26.47#ibcon#read 6, iclass 40, count 2 2006.257.13:10:26.47#ibcon#end of sib2, iclass 40, count 2 2006.257.13:10:26.47#ibcon#*after write, iclass 40, count 2 2006.257.13:10:26.47#ibcon#*before return 0, iclass 40, count 2 2006.257.13:10:26.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:26.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:10:26.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.13:10:26.47#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:26.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:26.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:26.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:26.59#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:10:26.59#ibcon#first serial, iclass 40, count 0 2006.257.13:10:26.59#ibcon#enter sib2, iclass 40, count 0 2006.257.13:10:26.59#ibcon#flushed, iclass 40, count 0 2006.257.13:10:26.59#ibcon#about to write, iclass 40, count 0 2006.257.13:10:26.59#ibcon#wrote, iclass 40, count 0 2006.257.13:10:26.59#ibcon#about to read 3, iclass 40, count 0 2006.257.13:10:26.61#ibcon#read 3, iclass 40, count 0 2006.257.13:10:26.61#ibcon#about to read 4, iclass 40, count 0 2006.257.13:10:26.61#ibcon#read 4, iclass 40, count 0 2006.257.13:10:26.61#ibcon#about to read 5, iclass 40, count 0 2006.257.13:10:26.61#ibcon#read 5, iclass 40, count 0 2006.257.13:10:26.61#ibcon#about to read 6, iclass 40, count 0 2006.257.13:10:26.61#ibcon#read 6, iclass 40, count 0 2006.257.13:10:26.61#ibcon#end of sib2, iclass 40, count 0 2006.257.13:10:26.61#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:10:26.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:10:26.61#ibcon#[27=USB\r\n] 2006.257.13:10:26.61#ibcon#*before write, iclass 40, count 0 2006.257.13:10:26.61#ibcon#enter sib2, iclass 40, count 0 2006.257.13:10:26.61#ibcon#flushed, iclass 40, count 0 2006.257.13:10:26.61#ibcon#about to write, iclass 40, count 0 2006.257.13:10:26.61#ibcon#wrote, iclass 40, count 0 2006.257.13:10:26.61#ibcon#about to read 3, iclass 40, count 0 2006.257.13:10:26.64#ibcon#read 3, iclass 40, count 0 2006.257.13:10:26.64#ibcon#about to read 4, iclass 40, count 0 2006.257.13:10:26.64#ibcon#read 4, iclass 40, count 0 2006.257.13:10:26.64#ibcon#about to read 5, iclass 40, count 0 2006.257.13:10:26.64#ibcon#read 5, iclass 40, count 0 2006.257.13:10:26.64#ibcon#about to read 6, iclass 40, count 0 2006.257.13:10:26.64#ibcon#read 6, iclass 40, count 0 2006.257.13:10:26.64#ibcon#end of sib2, iclass 40, count 0 2006.257.13:10:26.64#ibcon#*after write, iclass 40, count 0 2006.257.13:10:26.64#ibcon#*before return 0, iclass 40, count 0 2006.257.13:10:26.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:26.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:10:26.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:10:26.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:10:26.64$vck44/vblo=6,719.99 2006.257.13:10:26.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.13:10:26.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.13:10:26.64#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:26.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:26.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:26.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:26.64#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:10:26.64#ibcon#first serial, iclass 4, count 0 2006.257.13:10:26.64#ibcon#enter sib2, iclass 4, count 0 2006.257.13:10:26.64#ibcon#flushed, iclass 4, count 0 2006.257.13:10:26.64#ibcon#about to write, iclass 4, count 0 2006.257.13:10:26.64#ibcon#wrote, iclass 4, count 0 2006.257.13:10:26.64#ibcon#about to read 3, iclass 4, count 0 2006.257.13:10:26.66#ibcon#read 3, iclass 4, count 0 2006.257.13:10:26.66#ibcon#about to read 4, iclass 4, count 0 2006.257.13:10:26.66#ibcon#read 4, iclass 4, count 0 2006.257.13:10:26.66#ibcon#about to read 5, iclass 4, count 0 2006.257.13:10:26.66#ibcon#read 5, iclass 4, count 0 2006.257.13:10:26.66#ibcon#about to read 6, iclass 4, count 0 2006.257.13:10:26.66#ibcon#read 6, iclass 4, count 0 2006.257.13:10:26.66#ibcon#end of sib2, iclass 4, count 0 2006.257.13:10:26.66#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:10:26.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:10:26.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:10:26.66#ibcon#*before write, iclass 4, count 0 2006.257.13:10:26.66#ibcon#enter sib2, iclass 4, count 0 2006.257.13:10:26.66#ibcon#flushed, iclass 4, count 0 2006.257.13:10:26.66#ibcon#about to write, iclass 4, count 0 2006.257.13:10:26.66#ibcon#wrote, iclass 4, count 0 2006.257.13:10:26.66#ibcon#about to read 3, iclass 4, count 0 2006.257.13:10:26.70#ibcon#read 3, iclass 4, count 0 2006.257.13:10:26.70#ibcon#about to read 4, iclass 4, count 0 2006.257.13:10:26.70#ibcon#read 4, iclass 4, count 0 2006.257.13:10:26.70#ibcon#about to read 5, iclass 4, count 0 2006.257.13:10:26.70#ibcon#read 5, iclass 4, count 0 2006.257.13:10:26.70#ibcon#about to read 6, iclass 4, count 0 2006.257.13:10:26.70#ibcon#read 6, iclass 4, count 0 2006.257.13:10:26.70#ibcon#end of sib2, iclass 4, count 0 2006.257.13:10:26.70#ibcon#*after write, iclass 4, count 0 2006.257.13:10:26.70#ibcon#*before return 0, iclass 4, count 0 2006.257.13:10:26.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:26.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:10:26.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:10:26.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:10:26.70$vck44/vb=6,4 2006.257.13:10:26.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.13:10:26.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.13:10:26.70#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:26.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:26.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:26.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:26.76#ibcon#enter wrdev, iclass 6, count 2 2006.257.13:10:26.76#ibcon#first serial, iclass 6, count 2 2006.257.13:10:26.76#ibcon#enter sib2, iclass 6, count 2 2006.257.13:10:26.76#ibcon#flushed, iclass 6, count 2 2006.257.13:10:26.76#ibcon#about to write, iclass 6, count 2 2006.257.13:10:26.76#ibcon#wrote, iclass 6, count 2 2006.257.13:10:26.76#ibcon#about to read 3, iclass 6, count 2 2006.257.13:10:26.78#ibcon#read 3, iclass 6, count 2 2006.257.13:10:26.78#ibcon#about to read 4, iclass 6, count 2 2006.257.13:10:26.78#ibcon#read 4, iclass 6, count 2 2006.257.13:10:26.78#ibcon#about to read 5, iclass 6, count 2 2006.257.13:10:26.78#ibcon#read 5, iclass 6, count 2 2006.257.13:10:26.78#ibcon#about to read 6, iclass 6, count 2 2006.257.13:10:26.78#ibcon#read 6, iclass 6, count 2 2006.257.13:10:26.78#ibcon#end of sib2, iclass 6, count 2 2006.257.13:10:26.78#ibcon#*mode == 0, iclass 6, count 2 2006.257.13:10:26.78#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.13:10:26.78#ibcon#[27=AT06-04\r\n] 2006.257.13:10:26.78#ibcon#*before write, iclass 6, count 2 2006.257.13:10:26.78#ibcon#enter sib2, iclass 6, count 2 2006.257.13:10:26.78#ibcon#flushed, iclass 6, count 2 2006.257.13:10:26.78#ibcon#about to write, iclass 6, count 2 2006.257.13:10:26.78#ibcon#wrote, iclass 6, count 2 2006.257.13:10:26.78#ibcon#about to read 3, iclass 6, count 2 2006.257.13:10:26.81#ibcon#read 3, iclass 6, count 2 2006.257.13:10:26.81#ibcon#about to read 4, iclass 6, count 2 2006.257.13:10:26.81#ibcon#read 4, iclass 6, count 2 2006.257.13:10:26.81#ibcon#about to read 5, iclass 6, count 2 2006.257.13:10:26.81#ibcon#read 5, iclass 6, count 2 2006.257.13:10:26.81#ibcon#about to read 6, iclass 6, count 2 2006.257.13:10:26.81#ibcon#read 6, iclass 6, count 2 2006.257.13:10:26.81#ibcon#end of sib2, iclass 6, count 2 2006.257.13:10:26.81#ibcon#*after write, iclass 6, count 2 2006.257.13:10:26.81#ibcon#*before return 0, iclass 6, count 2 2006.257.13:10:26.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:26.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:10:26.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.13:10:26.81#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:26.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:26.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:26.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:26.93#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:10:26.93#ibcon#first serial, iclass 6, count 0 2006.257.13:10:26.93#ibcon#enter sib2, iclass 6, count 0 2006.257.13:10:26.93#ibcon#flushed, iclass 6, count 0 2006.257.13:10:26.93#ibcon#about to write, iclass 6, count 0 2006.257.13:10:26.93#ibcon#wrote, iclass 6, count 0 2006.257.13:10:26.93#ibcon#about to read 3, iclass 6, count 0 2006.257.13:10:26.95#ibcon#read 3, iclass 6, count 0 2006.257.13:10:26.95#ibcon#about to read 4, iclass 6, count 0 2006.257.13:10:26.95#ibcon#read 4, iclass 6, count 0 2006.257.13:10:26.95#ibcon#about to read 5, iclass 6, count 0 2006.257.13:10:26.95#ibcon#read 5, iclass 6, count 0 2006.257.13:10:26.95#ibcon#about to read 6, iclass 6, count 0 2006.257.13:10:26.95#ibcon#read 6, iclass 6, count 0 2006.257.13:10:26.95#ibcon#end of sib2, iclass 6, count 0 2006.257.13:10:26.95#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:10:26.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:10:26.95#ibcon#[27=USB\r\n] 2006.257.13:10:26.95#ibcon#*before write, iclass 6, count 0 2006.257.13:10:26.95#ibcon#enter sib2, iclass 6, count 0 2006.257.13:10:26.95#ibcon#flushed, iclass 6, count 0 2006.257.13:10:26.95#ibcon#about to write, iclass 6, count 0 2006.257.13:10:26.95#ibcon#wrote, iclass 6, count 0 2006.257.13:10:26.95#ibcon#about to read 3, iclass 6, count 0 2006.257.13:10:26.98#ibcon#read 3, iclass 6, count 0 2006.257.13:10:26.98#ibcon#about to read 4, iclass 6, count 0 2006.257.13:10:26.98#ibcon#read 4, iclass 6, count 0 2006.257.13:10:26.98#ibcon#about to read 5, iclass 6, count 0 2006.257.13:10:26.98#ibcon#read 5, iclass 6, count 0 2006.257.13:10:26.98#ibcon#about to read 6, iclass 6, count 0 2006.257.13:10:26.98#ibcon#read 6, iclass 6, count 0 2006.257.13:10:26.98#ibcon#end of sib2, iclass 6, count 0 2006.257.13:10:26.98#ibcon#*after write, iclass 6, count 0 2006.257.13:10:26.98#ibcon#*before return 0, iclass 6, count 0 2006.257.13:10:26.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:26.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:10:26.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:10:26.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:10:26.98$vck44/vblo=7,734.99 2006.257.13:10:26.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.13:10:26.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.13:10:26.98#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:26.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:26.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:26.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:26.98#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:10:26.98#ibcon#first serial, iclass 10, count 0 2006.257.13:10:26.98#ibcon#enter sib2, iclass 10, count 0 2006.257.13:10:26.98#ibcon#flushed, iclass 10, count 0 2006.257.13:10:26.98#ibcon#about to write, iclass 10, count 0 2006.257.13:10:26.98#ibcon#wrote, iclass 10, count 0 2006.257.13:10:26.98#ibcon#about to read 3, iclass 10, count 0 2006.257.13:10:27.00#ibcon#read 3, iclass 10, count 0 2006.257.13:10:27.00#ibcon#about to read 4, iclass 10, count 0 2006.257.13:10:27.00#ibcon#read 4, iclass 10, count 0 2006.257.13:10:27.00#ibcon#about to read 5, iclass 10, count 0 2006.257.13:10:27.00#ibcon#read 5, iclass 10, count 0 2006.257.13:10:27.00#ibcon#about to read 6, iclass 10, count 0 2006.257.13:10:27.00#ibcon#read 6, iclass 10, count 0 2006.257.13:10:27.00#ibcon#end of sib2, iclass 10, count 0 2006.257.13:10:27.00#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:10:27.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:10:27.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:10:27.00#ibcon#*before write, iclass 10, count 0 2006.257.13:10:27.00#ibcon#enter sib2, iclass 10, count 0 2006.257.13:10:27.00#ibcon#flushed, iclass 10, count 0 2006.257.13:10:27.00#ibcon#about to write, iclass 10, count 0 2006.257.13:10:27.00#ibcon#wrote, iclass 10, count 0 2006.257.13:10:27.00#ibcon#about to read 3, iclass 10, count 0 2006.257.13:10:27.04#ibcon#read 3, iclass 10, count 0 2006.257.13:10:27.04#ibcon#about to read 4, iclass 10, count 0 2006.257.13:10:27.04#ibcon#read 4, iclass 10, count 0 2006.257.13:10:27.04#ibcon#about to read 5, iclass 10, count 0 2006.257.13:10:27.04#ibcon#read 5, iclass 10, count 0 2006.257.13:10:27.04#ibcon#about to read 6, iclass 10, count 0 2006.257.13:10:27.04#ibcon#read 6, iclass 10, count 0 2006.257.13:10:27.04#ibcon#end of sib2, iclass 10, count 0 2006.257.13:10:27.04#ibcon#*after write, iclass 10, count 0 2006.257.13:10:27.04#ibcon#*before return 0, iclass 10, count 0 2006.257.13:10:27.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:27.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:10:27.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:10:27.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:10:27.04$vck44/vb=7,4 2006.257.13:10:27.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.13:10:27.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.13:10:27.04#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:27.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:27.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:27.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:27.10#ibcon#enter wrdev, iclass 12, count 2 2006.257.13:10:27.10#ibcon#first serial, iclass 12, count 2 2006.257.13:10:27.10#ibcon#enter sib2, iclass 12, count 2 2006.257.13:10:27.10#ibcon#flushed, iclass 12, count 2 2006.257.13:10:27.10#ibcon#about to write, iclass 12, count 2 2006.257.13:10:27.10#ibcon#wrote, iclass 12, count 2 2006.257.13:10:27.10#ibcon#about to read 3, iclass 12, count 2 2006.257.13:10:27.12#ibcon#read 3, iclass 12, count 2 2006.257.13:10:27.12#ibcon#about to read 4, iclass 12, count 2 2006.257.13:10:27.12#ibcon#read 4, iclass 12, count 2 2006.257.13:10:27.12#ibcon#about to read 5, iclass 12, count 2 2006.257.13:10:27.12#ibcon#read 5, iclass 12, count 2 2006.257.13:10:27.12#ibcon#about to read 6, iclass 12, count 2 2006.257.13:10:27.12#ibcon#read 6, iclass 12, count 2 2006.257.13:10:27.12#ibcon#end of sib2, iclass 12, count 2 2006.257.13:10:27.12#ibcon#*mode == 0, iclass 12, count 2 2006.257.13:10:27.12#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.13:10:27.12#ibcon#[27=AT07-04\r\n] 2006.257.13:10:27.12#ibcon#*before write, iclass 12, count 2 2006.257.13:10:27.12#ibcon#enter sib2, iclass 12, count 2 2006.257.13:10:27.12#ibcon#flushed, iclass 12, count 2 2006.257.13:10:27.12#ibcon#about to write, iclass 12, count 2 2006.257.13:10:27.12#ibcon#wrote, iclass 12, count 2 2006.257.13:10:27.12#ibcon#about to read 3, iclass 12, count 2 2006.257.13:10:27.15#ibcon#read 3, iclass 12, count 2 2006.257.13:10:27.15#ibcon#about to read 4, iclass 12, count 2 2006.257.13:10:27.15#ibcon#read 4, iclass 12, count 2 2006.257.13:10:27.15#ibcon#about to read 5, iclass 12, count 2 2006.257.13:10:27.15#ibcon#read 5, iclass 12, count 2 2006.257.13:10:27.15#ibcon#about to read 6, iclass 12, count 2 2006.257.13:10:27.15#ibcon#read 6, iclass 12, count 2 2006.257.13:10:27.15#ibcon#end of sib2, iclass 12, count 2 2006.257.13:10:27.15#ibcon#*after write, iclass 12, count 2 2006.257.13:10:27.15#ibcon#*before return 0, iclass 12, count 2 2006.257.13:10:27.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:27.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:10:27.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.13:10:27.15#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:27.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:27.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:27.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:27.27#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:10:27.27#ibcon#first serial, iclass 12, count 0 2006.257.13:10:27.27#ibcon#enter sib2, iclass 12, count 0 2006.257.13:10:27.27#ibcon#flushed, iclass 12, count 0 2006.257.13:10:27.27#ibcon#about to write, iclass 12, count 0 2006.257.13:10:27.27#ibcon#wrote, iclass 12, count 0 2006.257.13:10:27.27#ibcon#about to read 3, iclass 12, count 0 2006.257.13:10:27.29#ibcon#read 3, iclass 12, count 0 2006.257.13:10:27.29#ibcon#about to read 4, iclass 12, count 0 2006.257.13:10:27.29#ibcon#read 4, iclass 12, count 0 2006.257.13:10:27.29#ibcon#about to read 5, iclass 12, count 0 2006.257.13:10:27.29#ibcon#read 5, iclass 12, count 0 2006.257.13:10:27.29#ibcon#about to read 6, iclass 12, count 0 2006.257.13:10:27.29#ibcon#read 6, iclass 12, count 0 2006.257.13:10:27.29#ibcon#end of sib2, iclass 12, count 0 2006.257.13:10:27.29#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:10:27.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:10:27.29#ibcon#[27=USB\r\n] 2006.257.13:10:27.29#ibcon#*before write, iclass 12, count 0 2006.257.13:10:27.29#ibcon#enter sib2, iclass 12, count 0 2006.257.13:10:27.29#ibcon#flushed, iclass 12, count 0 2006.257.13:10:27.29#ibcon#about to write, iclass 12, count 0 2006.257.13:10:27.29#ibcon#wrote, iclass 12, count 0 2006.257.13:10:27.29#ibcon#about to read 3, iclass 12, count 0 2006.257.13:10:27.32#ibcon#read 3, iclass 12, count 0 2006.257.13:10:27.32#ibcon#about to read 4, iclass 12, count 0 2006.257.13:10:27.32#ibcon#read 4, iclass 12, count 0 2006.257.13:10:27.32#ibcon#about to read 5, iclass 12, count 0 2006.257.13:10:27.32#ibcon#read 5, iclass 12, count 0 2006.257.13:10:27.32#ibcon#about to read 6, iclass 12, count 0 2006.257.13:10:27.32#ibcon#read 6, iclass 12, count 0 2006.257.13:10:27.32#ibcon#end of sib2, iclass 12, count 0 2006.257.13:10:27.32#ibcon#*after write, iclass 12, count 0 2006.257.13:10:27.32#ibcon#*before return 0, iclass 12, count 0 2006.257.13:10:27.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:27.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:10:27.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:10:27.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:10:27.32$vck44/vblo=8,744.99 2006.257.13:10:27.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.13:10:27.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.13:10:27.32#ibcon#ireg 17 cls_cnt 0 2006.257.13:10:27.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:27.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:27.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:27.32#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:10:27.32#ibcon#first serial, iclass 14, count 0 2006.257.13:10:27.32#ibcon#enter sib2, iclass 14, count 0 2006.257.13:10:27.32#ibcon#flushed, iclass 14, count 0 2006.257.13:10:27.32#ibcon#about to write, iclass 14, count 0 2006.257.13:10:27.32#ibcon#wrote, iclass 14, count 0 2006.257.13:10:27.32#ibcon#about to read 3, iclass 14, count 0 2006.257.13:10:27.34#ibcon#read 3, iclass 14, count 0 2006.257.13:10:27.34#ibcon#about to read 4, iclass 14, count 0 2006.257.13:10:27.34#ibcon#read 4, iclass 14, count 0 2006.257.13:10:27.34#ibcon#about to read 5, iclass 14, count 0 2006.257.13:10:27.34#ibcon#read 5, iclass 14, count 0 2006.257.13:10:27.34#ibcon#about to read 6, iclass 14, count 0 2006.257.13:10:27.34#ibcon#read 6, iclass 14, count 0 2006.257.13:10:27.34#ibcon#end of sib2, iclass 14, count 0 2006.257.13:10:27.34#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:10:27.34#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:10:27.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:10:27.34#ibcon#*before write, iclass 14, count 0 2006.257.13:10:27.34#ibcon#enter sib2, iclass 14, count 0 2006.257.13:10:27.34#ibcon#flushed, iclass 14, count 0 2006.257.13:10:27.34#ibcon#about to write, iclass 14, count 0 2006.257.13:10:27.34#ibcon#wrote, iclass 14, count 0 2006.257.13:10:27.34#ibcon#about to read 3, iclass 14, count 0 2006.257.13:10:27.38#ibcon#read 3, iclass 14, count 0 2006.257.13:10:27.38#ibcon#about to read 4, iclass 14, count 0 2006.257.13:10:27.38#ibcon#read 4, iclass 14, count 0 2006.257.13:10:27.38#ibcon#about to read 5, iclass 14, count 0 2006.257.13:10:27.38#ibcon#read 5, iclass 14, count 0 2006.257.13:10:27.38#ibcon#about to read 6, iclass 14, count 0 2006.257.13:10:27.38#ibcon#read 6, iclass 14, count 0 2006.257.13:10:27.38#ibcon#end of sib2, iclass 14, count 0 2006.257.13:10:27.38#ibcon#*after write, iclass 14, count 0 2006.257.13:10:27.38#ibcon#*before return 0, iclass 14, count 0 2006.257.13:10:27.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:27.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:10:27.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:10:27.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:10:27.38$vck44/vb=8,4 2006.257.13:10:27.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.13:10:27.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.13:10:27.38#ibcon#ireg 11 cls_cnt 2 2006.257.13:10:27.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:27.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:27.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:27.44#ibcon#enter wrdev, iclass 16, count 2 2006.257.13:10:27.44#ibcon#first serial, iclass 16, count 2 2006.257.13:10:27.44#ibcon#enter sib2, iclass 16, count 2 2006.257.13:10:27.44#ibcon#flushed, iclass 16, count 2 2006.257.13:10:27.44#ibcon#about to write, iclass 16, count 2 2006.257.13:10:27.44#ibcon#wrote, iclass 16, count 2 2006.257.13:10:27.44#ibcon#about to read 3, iclass 16, count 2 2006.257.13:10:27.46#ibcon#read 3, iclass 16, count 2 2006.257.13:10:27.46#ibcon#about to read 4, iclass 16, count 2 2006.257.13:10:27.46#ibcon#read 4, iclass 16, count 2 2006.257.13:10:27.46#ibcon#about to read 5, iclass 16, count 2 2006.257.13:10:27.46#ibcon#read 5, iclass 16, count 2 2006.257.13:10:27.46#ibcon#about to read 6, iclass 16, count 2 2006.257.13:10:27.46#ibcon#read 6, iclass 16, count 2 2006.257.13:10:27.46#ibcon#end of sib2, iclass 16, count 2 2006.257.13:10:27.46#ibcon#*mode == 0, iclass 16, count 2 2006.257.13:10:27.46#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.13:10:27.46#ibcon#[27=AT08-04\r\n] 2006.257.13:10:27.46#ibcon#*before write, iclass 16, count 2 2006.257.13:10:27.46#ibcon#enter sib2, iclass 16, count 2 2006.257.13:10:27.46#ibcon#flushed, iclass 16, count 2 2006.257.13:10:27.46#ibcon#about to write, iclass 16, count 2 2006.257.13:10:27.46#ibcon#wrote, iclass 16, count 2 2006.257.13:10:27.46#ibcon#about to read 3, iclass 16, count 2 2006.257.13:10:27.49#ibcon#read 3, iclass 16, count 2 2006.257.13:10:27.49#ibcon#about to read 4, iclass 16, count 2 2006.257.13:10:27.49#ibcon#read 4, iclass 16, count 2 2006.257.13:10:27.49#ibcon#about to read 5, iclass 16, count 2 2006.257.13:10:27.49#ibcon#read 5, iclass 16, count 2 2006.257.13:10:27.49#ibcon#about to read 6, iclass 16, count 2 2006.257.13:10:27.49#ibcon#read 6, iclass 16, count 2 2006.257.13:10:27.49#ibcon#end of sib2, iclass 16, count 2 2006.257.13:10:27.49#ibcon#*after write, iclass 16, count 2 2006.257.13:10:27.49#ibcon#*before return 0, iclass 16, count 2 2006.257.13:10:27.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:27.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:10:27.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.13:10:27.49#ibcon#ireg 7 cls_cnt 0 2006.257.13:10:27.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:27.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:27.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:27.61#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:10:27.61#ibcon#first serial, iclass 16, count 0 2006.257.13:10:27.61#ibcon#enter sib2, iclass 16, count 0 2006.257.13:10:27.61#ibcon#flushed, iclass 16, count 0 2006.257.13:10:27.61#ibcon#about to write, iclass 16, count 0 2006.257.13:10:27.61#ibcon#wrote, iclass 16, count 0 2006.257.13:10:27.61#ibcon#about to read 3, iclass 16, count 0 2006.257.13:10:27.63#ibcon#read 3, iclass 16, count 0 2006.257.13:10:27.63#ibcon#about to read 4, iclass 16, count 0 2006.257.13:10:27.63#ibcon#read 4, iclass 16, count 0 2006.257.13:10:27.63#ibcon#about to read 5, iclass 16, count 0 2006.257.13:10:27.63#ibcon#read 5, iclass 16, count 0 2006.257.13:10:27.63#ibcon#about to read 6, iclass 16, count 0 2006.257.13:10:27.63#ibcon#read 6, iclass 16, count 0 2006.257.13:10:27.63#ibcon#end of sib2, iclass 16, count 0 2006.257.13:10:27.63#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:10:27.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:10:27.63#ibcon#[27=USB\r\n] 2006.257.13:10:27.63#ibcon#*before write, iclass 16, count 0 2006.257.13:10:27.63#ibcon#enter sib2, iclass 16, count 0 2006.257.13:10:27.63#ibcon#flushed, iclass 16, count 0 2006.257.13:10:27.63#ibcon#about to write, iclass 16, count 0 2006.257.13:10:27.63#ibcon#wrote, iclass 16, count 0 2006.257.13:10:27.63#ibcon#about to read 3, iclass 16, count 0 2006.257.13:10:27.66#ibcon#read 3, iclass 16, count 0 2006.257.13:10:27.66#ibcon#about to read 4, iclass 16, count 0 2006.257.13:10:27.66#ibcon#read 4, iclass 16, count 0 2006.257.13:10:27.66#ibcon#about to read 5, iclass 16, count 0 2006.257.13:10:27.66#ibcon#read 5, iclass 16, count 0 2006.257.13:10:27.66#ibcon#about to read 6, iclass 16, count 0 2006.257.13:10:27.66#ibcon#read 6, iclass 16, count 0 2006.257.13:10:27.66#ibcon#end of sib2, iclass 16, count 0 2006.257.13:10:27.66#ibcon#*after write, iclass 16, count 0 2006.257.13:10:27.66#ibcon#*before return 0, iclass 16, count 0 2006.257.13:10:27.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:27.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:10:27.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:10:27.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:10:27.66$vck44/vabw=wide 2006.257.13:10:27.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.13:10:27.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.13:10:27.66#ibcon#ireg 8 cls_cnt 0 2006.257.13:10:27.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:27.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:27.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:27.66#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:10:27.66#ibcon#first serial, iclass 18, count 0 2006.257.13:10:27.66#ibcon#enter sib2, iclass 18, count 0 2006.257.13:10:27.66#ibcon#flushed, iclass 18, count 0 2006.257.13:10:27.66#ibcon#about to write, iclass 18, count 0 2006.257.13:10:27.66#ibcon#wrote, iclass 18, count 0 2006.257.13:10:27.66#ibcon#about to read 3, iclass 18, count 0 2006.257.13:10:27.68#ibcon#read 3, iclass 18, count 0 2006.257.13:10:27.68#ibcon#about to read 4, iclass 18, count 0 2006.257.13:10:27.68#ibcon#read 4, iclass 18, count 0 2006.257.13:10:27.68#ibcon#about to read 5, iclass 18, count 0 2006.257.13:10:27.68#ibcon#read 5, iclass 18, count 0 2006.257.13:10:27.68#ibcon#about to read 6, iclass 18, count 0 2006.257.13:10:27.68#ibcon#read 6, iclass 18, count 0 2006.257.13:10:27.68#ibcon#end of sib2, iclass 18, count 0 2006.257.13:10:27.68#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:10:27.68#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:10:27.68#ibcon#[25=BW32\r\n] 2006.257.13:10:27.68#ibcon#*before write, iclass 18, count 0 2006.257.13:10:27.68#ibcon#enter sib2, iclass 18, count 0 2006.257.13:10:27.68#ibcon#flushed, iclass 18, count 0 2006.257.13:10:27.68#ibcon#about to write, iclass 18, count 0 2006.257.13:10:27.68#ibcon#wrote, iclass 18, count 0 2006.257.13:10:27.68#ibcon#about to read 3, iclass 18, count 0 2006.257.13:10:27.71#ibcon#read 3, iclass 18, count 0 2006.257.13:10:27.71#ibcon#about to read 4, iclass 18, count 0 2006.257.13:10:27.71#ibcon#read 4, iclass 18, count 0 2006.257.13:10:27.71#ibcon#about to read 5, iclass 18, count 0 2006.257.13:10:27.71#ibcon#read 5, iclass 18, count 0 2006.257.13:10:27.71#ibcon#about to read 6, iclass 18, count 0 2006.257.13:10:27.71#ibcon#read 6, iclass 18, count 0 2006.257.13:10:27.71#ibcon#end of sib2, iclass 18, count 0 2006.257.13:10:27.71#ibcon#*after write, iclass 18, count 0 2006.257.13:10:27.71#ibcon#*before return 0, iclass 18, count 0 2006.257.13:10:27.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:27.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:10:27.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:10:27.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:10:27.71$vck44/vbbw=wide 2006.257.13:10:27.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.13:10:27.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.13:10:27.71#ibcon#ireg 8 cls_cnt 0 2006.257.13:10:27.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:10:27.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:10:27.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:10:27.78#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:10:27.78#ibcon#first serial, iclass 20, count 0 2006.257.13:10:27.78#ibcon#enter sib2, iclass 20, count 0 2006.257.13:10:27.78#ibcon#flushed, iclass 20, count 0 2006.257.13:10:27.78#ibcon#about to write, iclass 20, count 0 2006.257.13:10:27.78#ibcon#wrote, iclass 20, count 0 2006.257.13:10:27.78#ibcon#about to read 3, iclass 20, count 0 2006.257.13:10:27.80#ibcon#read 3, iclass 20, count 0 2006.257.13:10:27.80#ibcon#about to read 4, iclass 20, count 0 2006.257.13:10:27.80#ibcon#read 4, iclass 20, count 0 2006.257.13:10:27.80#ibcon#about to read 5, iclass 20, count 0 2006.257.13:10:27.80#ibcon#read 5, iclass 20, count 0 2006.257.13:10:27.80#ibcon#about to read 6, iclass 20, count 0 2006.257.13:10:27.80#ibcon#read 6, iclass 20, count 0 2006.257.13:10:27.80#ibcon#end of sib2, iclass 20, count 0 2006.257.13:10:27.80#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:10:27.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:10:27.80#ibcon#[27=BW32\r\n] 2006.257.13:10:27.80#ibcon#*before write, iclass 20, count 0 2006.257.13:10:27.80#ibcon#enter sib2, iclass 20, count 0 2006.257.13:10:27.80#ibcon#flushed, iclass 20, count 0 2006.257.13:10:27.80#ibcon#about to write, iclass 20, count 0 2006.257.13:10:27.80#ibcon#wrote, iclass 20, count 0 2006.257.13:10:27.80#ibcon#about to read 3, iclass 20, count 0 2006.257.13:10:27.83#ibcon#read 3, iclass 20, count 0 2006.257.13:10:27.83#ibcon#about to read 4, iclass 20, count 0 2006.257.13:10:27.83#ibcon#read 4, iclass 20, count 0 2006.257.13:10:27.83#ibcon#about to read 5, iclass 20, count 0 2006.257.13:10:27.83#ibcon#read 5, iclass 20, count 0 2006.257.13:10:27.83#ibcon#about to read 6, iclass 20, count 0 2006.257.13:10:27.83#ibcon#read 6, iclass 20, count 0 2006.257.13:10:27.83#ibcon#end of sib2, iclass 20, count 0 2006.257.13:10:27.83#ibcon#*after write, iclass 20, count 0 2006.257.13:10:27.83#ibcon#*before return 0, iclass 20, count 0 2006.257.13:10:27.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:10:27.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:10:27.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:10:27.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:10:27.83$setupk4/ifdk4 2006.257.13:10:27.83$ifdk4/lo= 2006.257.13:10:27.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:10:27.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:10:27.83$ifdk4/patch= 2006.257.13:10:27.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:10:27.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:10:27.83$setupk4/!*+20s 2006.257.13:10:33.26#abcon#<5=/14 1.4 3.6 17.70 971013.7\r\n> 2006.257.13:10:33.28#abcon#{5=INTERFACE CLEAR} 2006.257.13:10:33.34#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:10:35.14#trakl#Source acquired 2006.257.13:10:36.14#flagr#flagr/antenna,acquired 2006.257.13:10:42.32$setupk4/"tpicd 2006.257.13:10:42.32$setupk4/echo=off 2006.257.13:10:42.32$setupk4/xlog=off 2006.257.13:10:42.32:!2006.257.13:12:28 2006.257.13:12:28.00:preob 2006.257.13:12:28.13/onsource/TRACKING 2006.257.13:12:28.13:!2006.257.13:12:38 2006.257.13:12:38.00:"tape 2006.257.13:12:38.00:"st=record 2006.257.13:12:38.00:data_valid=on 2006.257.13:12:38.00:midob 2006.257.13:12:39.13/onsource/TRACKING 2006.257.13:12:39.13/wx/17.69,1013.7,97 2006.257.13:12:39.25/cable/+6.4819E-03 2006.257.13:12:40.34/va/01,08,usb,yes,30,33 2006.257.13:12:40.34/va/02,07,usb,yes,33,33 2006.257.13:12:40.34/va/03,08,usb,yes,29,31 2006.257.13:12:40.34/va/04,07,usb,yes,34,35 2006.257.13:12:40.34/va/05,04,usb,yes,30,31 2006.257.13:12:40.34/va/06,04,usb,yes,34,33 2006.257.13:12:40.34/va/07,04,usb,yes,35,35 2006.257.13:12:40.34/va/08,04,usb,yes,29,35 2006.257.13:12:40.57/valo/01,524.99,yes,locked 2006.257.13:12:40.57/valo/02,534.99,yes,locked 2006.257.13:12:40.57/valo/03,564.99,yes,locked 2006.257.13:12:40.57/valo/04,624.99,yes,locked 2006.257.13:12:40.57/valo/05,734.99,yes,locked 2006.257.13:12:40.57/valo/06,814.99,yes,locked 2006.257.13:12:40.57/valo/07,864.99,yes,locked 2006.257.13:12:40.57/valo/08,884.99,yes,locked 2006.257.13:12:41.66/vb/01,04,usb,yes,30,28 2006.257.13:12:41.66/vb/02,05,usb,yes,29,29 2006.257.13:12:41.66/vb/03,04,usb,yes,30,33 2006.257.13:12:41.66/vb/04,05,usb,yes,30,29 2006.257.13:12:41.66/vb/05,04,usb,yes,26,29 2006.257.13:12:41.66/vb/06,04,usb,yes,31,27 2006.257.13:12:41.66/vb/07,04,usb,yes,31,31 2006.257.13:12:41.66/vb/08,04,usb,yes,28,32 2006.257.13:12:41.89/vblo/01,629.99,yes,locked 2006.257.13:12:41.89/vblo/02,634.99,yes,locked 2006.257.13:12:41.89/vblo/03,649.99,yes,locked 2006.257.13:12:41.89/vblo/04,679.99,yes,locked 2006.257.13:12:41.89/vblo/05,709.99,yes,locked 2006.257.13:12:41.89/vblo/06,719.99,yes,locked 2006.257.13:12:41.89/vblo/07,734.99,yes,locked 2006.257.13:12:41.89/vblo/08,744.99,yes,locked 2006.257.13:12:42.04/vabw/8 2006.257.13:12:42.19/vbbw/8 2006.257.13:12:42.36/xfe/off,on,15.5 2006.257.13:12:42.74/ifatt/23,28,28,28 2006.257.13:12:43.07/fmout-gps/S +4.61E-07 2006.257.13:12:43.11:!2006.257.13:13:18 2006.257.13:13:18.00:data_valid=off 2006.257.13:13:18.00:"et 2006.257.13:13:18.00:!+3s 2006.257.13:13:21.02:"tape 2006.257.13:13:21.02:postob 2006.257.13:13:21.17/cable/+6.4827E-03 2006.257.13:13:21.17/wx/17.69,1013.7,97 2006.257.13:13:21.23/fmout-gps/S +4.61E-07 2006.257.13:13:21.23:scan_name=257-1314,jd0609,70 2006.257.13:13:21.23:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.13:13:23.13#flagr#flagr/antenna,new-source 2006.257.13:13:23.13:checkk5 2006.257.13:13:23.53/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:13:23.91/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:13:24.32/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:13:24.71/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:13:25.11/chk_obsdata//k5ts1/T2571312??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:13:25.51/chk_obsdata//k5ts2/T2571312??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:13:25.90/chk_obsdata//k5ts3/T2571312??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:13:26.31/chk_obsdata//k5ts4/T2571312??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:13:27.05/k5log//k5ts1_log_newline 2006.257.13:13:27.76/k5log//k5ts2_log_newline 2006.257.13:13:28.48/k5log//k5ts3_log_newline 2006.257.13:13:29.19/k5log//k5ts4_log_newline 2006.257.13:13:29.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:13:29.21:setupk4=1 2006.257.13:13:29.21$setupk4/echo=on 2006.257.13:13:29.21$setupk4/pcalon 2006.257.13:13:29.21$pcalon/"no phase cal control is implemented here 2006.257.13:13:29.21$setupk4/"tpicd=stop 2006.257.13:13:29.21$setupk4/"rec=synch_on 2006.257.13:13:29.21$setupk4/"rec_mode=128 2006.257.13:13:29.21$setupk4/!* 2006.257.13:13:29.21$setupk4/recpk4 2006.257.13:13:29.21$recpk4/recpatch= 2006.257.13:13:29.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:13:29.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:13:29.22$setupk4/vck44 2006.257.13:13:29.22$vck44/valo=1,524.99 2006.257.13:13:29.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.13:13:29.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.13:13:29.22#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:29.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:29.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:29.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:29.22#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:13:29.22#ibcon#first serial, iclass 25, count 0 2006.257.13:13:29.22#ibcon#enter sib2, iclass 25, count 0 2006.257.13:13:29.22#ibcon#flushed, iclass 25, count 0 2006.257.13:13:29.22#ibcon#about to write, iclass 25, count 0 2006.257.13:13:29.22#ibcon#wrote, iclass 25, count 0 2006.257.13:13:29.22#ibcon#about to read 3, iclass 25, count 0 2006.257.13:13:29.24#ibcon#read 3, iclass 25, count 0 2006.257.13:13:29.24#ibcon#about to read 4, iclass 25, count 0 2006.257.13:13:29.24#ibcon#read 4, iclass 25, count 0 2006.257.13:13:29.24#ibcon#about to read 5, iclass 25, count 0 2006.257.13:13:29.24#ibcon#read 5, iclass 25, count 0 2006.257.13:13:29.24#ibcon#about to read 6, iclass 25, count 0 2006.257.13:13:29.24#ibcon#read 6, iclass 25, count 0 2006.257.13:13:29.24#ibcon#end of sib2, iclass 25, count 0 2006.257.13:13:29.24#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:13:29.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:13:29.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:13:29.24#ibcon#*before write, iclass 25, count 0 2006.257.13:13:29.24#ibcon#enter sib2, iclass 25, count 0 2006.257.13:13:29.24#ibcon#flushed, iclass 25, count 0 2006.257.13:13:29.24#ibcon#about to write, iclass 25, count 0 2006.257.13:13:29.24#ibcon#wrote, iclass 25, count 0 2006.257.13:13:29.24#ibcon#about to read 3, iclass 25, count 0 2006.257.13:13:29.29#ibcon#read 3, iclass 25, count 0 2006.257.13:13:29.29#ibcon#about to read 4, iclass 25, count 0 2006.257.13:13:29.29#ibcon#read 4, iclass 25, count 0 2006.257.13:13:29.29#ibcon#about to read 5, iclass 25, count 0 2006.257.13:13:29.29#ibcon#read 5, iclass 25, count 0 2006.257.13:13:29.29#ibcon#about to read 6, iclass 25, count 0 2006.257.13:13:29.29#ibcon#read 6, iclass 25, count 0 2006.257.13:13:29.29#ibcon#end of sib2, iclass 25, count 0 2006.257.13:13:29.29#ibcon#*after write, iclass 25, count 0 2006.257.13:13:29.29#ibcon#*before return 0, iclass 25, count 0 2006.257.13:13:29.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:29.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:29.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:13:29.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:13:29.29$vck44/va=1,8 2006.257.13:13:29.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.13:13:29.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.13:13:29.29#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:29.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:29.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:29.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:29.29#ibcon#enter wrdev, iclass 27, count 2 2006.257.13:13:29.29#ibcon#first serial, iclass 27, count 2 2006.257.13:13:29.29#ibcon#enter sib2, iclass 27, count 2 2006.257.13:13:29.29#ibcon#flushed, iclass 27, count 2 2006.257.13:13:29.29#ibcon#about to write, iclass 27, count 2 2006.257.13:13:29.29#ibcon#wrote, iclass 27, count 2 2006.257.13:13:29.29#ibcon#about to read 3, iclass 27, count 2 2006.257.13:13:29.31#ibcon#read 3, iclass 27, count 2 2006.257.13:13:29.31#ibcon#about to read 4, iclass 27, count 2 2006.257.13:13:29.31#ibcon#read 4, iclass 27, count 2 2006.257.13:13:29.31#ibcon#about to read 5, iclass 27, count 2 2006.257.13:13:29.31#ibcon#read 5, iclass 27, count 2 2006.257.13:13:29.31#ibcon#about to read 6, iclass 27, count 2 2006.257.13:13:29.31#ibcon#read 6, iclass 27, count 2 2006.257.13:13:29.31#ibcon#end of sib2, iclass 27, count 2 2006.257.13:13:29.31#ibcon#*mode == 0, iclass 27, count 2 2006.257.13:13:29.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.13:13:29.31#ibcon#[25=AT01-08\r\n] 2006.257.13:13:29.31#ibcon#*before write, iclass 27, count 2 2006.257.13:13:29.31#ibcon#enter sib2, iclass 27, count 2 2006.257.13:13:29.31#ibcon#flushed, iclass 27, count 2 2006.257.13:13:29.31#ibcon#about to write, iclass 27, count 2 2006.257.13:13:29.31#ibcon#wrote, iclass 27, count 2 2006.257.13:13:29.31#ibcon#about to read 3, iclass 27, count 2 2006.257.13:13:29.34#ibcon#read 3, iclass 27, count 2 2006.257.13:13:29.34#ibcon#about to read 4, iclass 27, count 2 2006.257.13:13:29.34#ibcon#read 4, iclass 27, count 2 2006.257.13:13:29.34#ibcon#about to read 5, iclass 27, count 2 2006.257.13:13:29.34#ibcon#read 5, iclass 27, count 2 2006.257.13:13:29.34#ibcon#about to read 6, iclass 27, count 2 2006.257.13:13:29.34#ibcon#read 6, iclass 27, count 2 2006.257.13:13:29.34#ibcon#end of sib2, iclass 27, count 2 2006.257.13:13:29.34#ibcon#*after write, iclass 27, count 2 2006.257.13:13:29.34#ibcon#*before return 0, iclass 27, count 2 2006.257.13:13:29.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:29.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:29.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.13:13:29.34#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:29.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:29.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:29.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:29.46#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:13:29.46#ibcon#first serial, iclass 27, count 0 2006.257.13:13:29.46#ibcon#enter sib2, iclass 27, count 0 2006.257.13:13:29.46#ibcon#flushed, iclass 27, count 0 2006.257.13:13:29.46#ibcon#about to write, iclass 27, count 0 2006.257.13:13:29.46#ibcon#wrote, iclass 27, count 0 2006.257.13:13:29.46#ibcon#about to read 3, iclass 27, count 0 2006.257.13:13:29.48#ibcon#read 3, iclass 27, count 0 2006.257.13:13:29.48#ibcon#about to read 4, iclass 27, count 0 2006.257.13:13:29.48#ibcon#read 4, iclass 27, count 0 2006.257.13:13:29.48#ibcon#about to read 5, iclass 27, count 0 2006.257.13:13:29.48#ibcon#read 5, iclass 27, count 0 2006.257.13:13:29.48#ibcon#about to read 6, iclass 27, count 0 2006.257.13:13:29.48#ibcon#read 6, iclass 27, count 0 2006.257.13:13:29.48#ibcon#end of sib2, iclass 27, count 0 2006.257.13:13:29.48#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:13:29.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:13:29.48#ibcon#[25=USB\r\n] 2006.257.13:13:29.48#ibcon#*before write, iclass 27, count 0 2006.257.13:13:29.48#ibcon#enter sib2, iclass 27, count 0 2006.257.13:13:29.48#ibcon#flushed, iclass 27, count 0 2006.257.13:13:29.48#ibcon#about to write, iclass 27, count 0 2006.257.13:13:29.48#ibcon#wrote, iclass 27, count 0 2006.257.13:13:29.48#ibcon#about to read 3, iclass 27, count 0 2006.257.13:13:29.51#ibcon#read 3, iclass 27, count 0 2006.257.13:13:29.51#ibcon#about to read 4, iclass 27, count 0 2006.257.13:13:29.51#ibcon#read 4, iclass 27, count 0 2006.257.13:13:29.51#ibcon#about to read 5, iclass 27, count 0 2006.257.13:13:29.51#ibcon#read 5, iclass 27, count 0 2006.257.13:13:29.51#ibcon#about to read 6, iclass 27, count 0 2006.257.13:13:29.51#ibcon#read 6, iclass 27, count 0 2006.257.13:13:29.51#ibcon#end of sib2, iclass 27, count 0 2006.257.13:13:29.51#ibcon#*after write, iclass 27, count 0 2006.257.13:13:29.51#ibcon#*before return 0, iclass 27, count 0 2006.257.13:13:29.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:29.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:29.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:13:29.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:13:29.51$vck44/valo=2,534.99 2006.257.13:13:29.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.13:13:29.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.13:13:29.51#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:29.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:29.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:29.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:29.51#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:13:29.51#ibcon#first serial, iclass 29, count 0 2006.257.13:13:29.51#ibcon#enter sib2, iclass 29, count 0 2006.257.13:13:29.51#ibcon#flushed, iclass 29, count 0 2006.257.13:13:29.51#ibcon#about to write, iclass 29, count 0 2006.257.13:13:29.51#ibcon#wrote, iclass 29, count 0 2006.257.13:13:29.51#ibcon#about to read 3, iclass 29, count 0 2006.257.13:13:29.53#ibcon#read 3, iclass 29, count 0 2006.257.13:13:29.53#ibcon#about to read 4, iclass 29, count 0 2006.257.13:13:29.53#ibcon#read 4, iclass 29, count 0 2006.257.13:13:29.53#ibcon#about to read 5, iclass 29, count 0 2006.257.13:13:29.53#ibcon#read 5, iclass 29, count 0 2006.257.13:13:29.53#ibcon#about to read 6, iclass 29, count 0 2006.257.13:13:29.53#ibcon#read 6, iclass 29, count 0 2006.257.13:13:29.53#ibcon#end of sib2, iclass 29, count 0 2006.257.13:13:29.53#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:13:29.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:13:29.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:13:29.53#ibcon#*before write, iclass 29, count 0 2006.257.13:13:29.53#ibcon#enter sib2, iclass 29, count 0 2006.257.13:13:29.53#ibcon#flushed, iclass 29, count 0 2006.257.13:13:29.53#ibcon#about to write, iclass 29, count 0 2006.257.13:13:29.53#ibcon#wrote, iclass 29, count 0 2006.257.13:13:29.53#ibcon#about to read 3, iclass 29, count 0 2006.257.13:13:29.57#ibcon#read 3, iclass 29, count 0 2006.257.13:13:29.57#ibcon#about to read 4, iclass 29, count 0 2006.257.13:13:29.57#ibcon#read 4, iclass 29, count 0 2006.257.13:13:29.57#ibcon#about to read 5, iclass 29, count 0 2006.257.13:13:29.57#ibcon#read 5, iclass 29, count 0 2006.257.13:13:29.57#ibcon#about to read 6, iclass 29, count 0 2006.257.13:13:29.57#ibcon#read 6, iclass 29, count 0 2006.257.13:13:29.57#ibcon#end of sib2, iclass 29, count 0 2006.257.13:13:29.57#ibcon#*after write, iclass 29, count 0 2006.257.13:13:29.57#ibcon#*before return 0, iclass 29, count 0 2006.257.13:13:29.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:29.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:29.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:13:29.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:13:29.57$vck44/va=2,7 2006.257.13:13:29.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.13:13:29.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.13:13:29.57#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:29.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:29.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:29.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:29.63#ibcon#enter wrdev, iclass 31, count 2 2006.257.13:13:29.63#ibcon#first serial, iclass 31, count 2 2006.257.13:13:29.63#ibcon#enter sib2, iclass 31, count 2 2006.257.13:13:29.63#ibcon#flushed, iclass 31, count 2 2006.257.13:13:29.63#ibcon#about to write, iclass 31, count 2 2006.257.13:13:29.63#ibcon#wrote, iclass 31, count 2 2006.257.13:13:29.63#ibcon#about to read 3, iclass 31, count 2 2006.257.13:13:29.65#ibcon#read 3, iclass 31, count 2 2006.257.13:13:29.65#ibcon#about to read 4, iclass 31, count 2 2006.257.13:13:29.65#ibcon#read 4, iclass 31, count 2 2006.257.13:13:29.65#ibcon#about to read 5, iclass 31, count 2 2006.257.13:13:29.65#ibcon#read 5, iclass 31, count 2 2006.257.13:13:29.65#ibcon#about to read 6, iclass 31, count 2 2006.257.13:13:29.65#ibcon#read 6, iclass 31, count 2 2006.257.13:13:29.65#ibcon#end of sib2, iclass 31, count 2 2006.257.13:13:29.65#ibcon#*mode == 0, iclass 31, count 2 2006.257.13:13:29.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.13:13:29.65#ibcon#[25=AT02-07\r\n] 2006.257.13:13:29.65#ibcon#*before write, iclass 31, count 2 2006.257.13:13:29.65#ibcon#enter sib2, iclass 31, count 2 2006.257.13:13:29.65#ibcon#flushed, iclass 31, count 2 2006.257.13:13:29.65#ibcon#about to write, iclass 31, count 2 2006.257.13:13:29.65#ibcon#wrote, iclass 31, count 2 2006.257.13:13:29.65#ibcon#about to read 3, iclass 31, count 2 2006.257.13:13:29.68#ibcon#read 3, iclass 31, count 2 2006.257.13:13:29.68#ibcon#about to read 4, iclass 31, count 2 2006.257.13:13:29.68#ibcon#read 4, iclass 31, count 2 2006.257.13:13:29.68#ibcon#about to read 5, iclass 31, count 2 2006.257.13:13:29.68#ibcon#read 5, iclass 31, count 2 2006.257.13:13:29.68#ibcon#about to read 6, iclass 31, count 2 2006.257.13:13:29.68#ibcon#read 6, iclass 31, count 2 2006.257.13:13:29.68#ibcon#end of sib2, iclass 31, count 2 2006.257.13:13:29.68#ibcon#*after write, iclass 31, count 2 2006.257.13:13:29.68#ibcon#*before return 0, iclass 31, count 2 2006.257.13:13:29.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:29.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:29.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.13:13:29.68#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:29.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:29.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:29.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:29.80#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:13:29.80#ibcon#first serial, iclass 31, count 0 2006.257.13:13:29.80#ibcon#enter sib2, iclass 31, count 0 2006.257.13:13:29.80#ibcon#flushed, iclass 31, count 0 2006.257.13:13:29.80#ibcon#about to write, iclass 31, count 0 2006.257.13:13:29.80#ibcon#wrote, iclass 31, count 0 2006.257.13:13:29.80#ibcon#about to read 3, iclass 31, count 0 2006.257.13:13:29.82#ibcon#read 3, iclass 31, count 0 2006.257.13:13:29.82#ibcon#about to read 4, iclass 31, count 0 2006.257.13:13:29.82#ibcon#read 4, iclass 31, count 0 2006.257.13:13:29.82#ibcon#about to read 5, iclass 31, count 0 2006.257.13:13:29.82#ibcon#read 5, iclass 31, count 0 2006.257.13:13:29.82#ibcon#about to read 6, iclass 31, count 0 2006.257.13:13:29.82#ibcon#read 6, iclass 31, count 0 2006.257.13:13:29.82#ibcon#end of sib2, iclass 31, count 0 2006.257.13:13:29.82#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:13:29.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:13:29.82#ibcon#[25=USB\r\n] 2006.257.13:13:29.82#ibcon#*before write, iclass 31, count 0 2006.257.13:13:29.82#ibcon#enter sib2, iclass 31, count 0 2006.257.13:13:29.82#ibcon#flushed, iclass 31, count 0 2006.257.13:13:29.82#ibcon#about to write, iclass 31, count 0 2006.257.13:13:29.82#ibcon#wrote, iclass 31, count 0 2006.257.13:13:29.82#ibcon#about to read 3, iclass 31, count 0 2006.257.13:13:29.85#ibcon#read 3, iclass 31, count 0 2006.257.13:13:29.85#ibcon#about to read 4, iclass 31, count 0 2006.257.13:13:29.85#ibcon#read 4, iclass 31, count 0 2006.257.13:13:29.85#ibcon#about to read 5, iclass 31, count 0 2006.257.13:13:29.85#ibcon#read 5, iclass 31, count 0 2006.257.13:13:29.85#ibcon#about to read 6, iclass 31, count 0 2006.257.13:13:29.85#ibcon#read 6, iclass 31, count 0 2006.257.13:13:29.85#ibcon#end of sib2, iclass 31, count 0 2006.257.13:13:29.85#ibcon#*after write, iclass 31, count 0 2006.257.13:13:29.85#ibcon#*before return 0, iclass 31, count 0 2006.257.13:13:29.85#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:29.85#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:29.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:13:29.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:13:29.85$vck44/valo=3,564.99 2006.257.13:13:29.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.13:13:29.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.13:13:29.85#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:29.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:29.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:29.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:29.85#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:13:29.85#ibcon#first serial, iclass 33, count 0 2006.257.13:13:29.85#ibcon#enter sib2, iclass 33, count 0 2006.257.13:13:29.85#ibcon#flushed, iclass 33, count 0 2006.257.13:13:29.85#ibcon#about to write, iclass 33, count 0 2006.257.13:13:29.85#ibcon#wrote, iclass 33, count 0 2006.257.13:13:29.85#ibcon#about to read 3, iclass 33, count 0 2006.257.13:13:29.87#ibcon#read 3, iclass 33, count 0 2006.257.13:13:29.87#ibcon#about to read 4, iclass 33, count 0 2006.257.13:13:29.87#ibcon#read 4, iclass 33, count 0 2006.257.13:13:29.87#ibcon#about to read 5, iclass 33, count 0 2006.257.13:13:29.87#ibcon#read 5, iclass 33, count 0 2006.257.13:13:29.87#ibcon#about to read 6, iclass 33, count 0 2006.257.13:13:29.87#ibcon#read 6, iclass 33, count 0 2006.257.13:13:29.87#ibcon#end of sib2, iclass 33, count 0 2006.257.13:13:29.87#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:13:29.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:13:29.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:13:29.87#ibcon#*before write, iclass 33, count 0 2006.257.13:13:29.87#ibcon#enter sib2, iclass 33, count 0 2006.257.13:13:29.87#ibcon#flushed, iclass 33, count 0 2006.257.13:13:29.87#ibcon#about to write, iclass 33, count 0 2006.257.13:13:29.87#ibcon#wrote, iclass 33, count 0 2006.257.13:13:29.87#ibcon#about to read 3, iclass 33, count 0 2006.257.13:13:29.91#ibcon#read 3, iclass 33, count 0 2006.257.13:13:29.91#ibcon#about to read 4, iclass 33, count 0 2006.257.13:13:29.91#ibcon#read 4, iclass 33, count 0 2006.257.13:13:29.91#ibcon#about to read 5, iclass 33, count 0 2006.257.13:13:29.91#ibcon#read 5, iclass 33, count 0 2006.257.13:13:29.91#ibcon#about to read 6, iclass 33, count 0 2006.257.13:13:29.91#ibcon#read 6, iclass 33, count 0 2006.257.13:13:29.91#ibcon#end of sib2, iclass 33, count 0 2006.257.13:13:29.91#ibcon#*after write, iclass 33, count 0 2006.257.13:13:29.91#ibcon#*before return 0, iclass 33, count 0 2006.257.13:13:29.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:29.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:29.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:13:29.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:13:29.91$vck44/va=3,8 2006.257.13:13:29.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.13:13:29.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.13:13:29.91#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:29.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:29.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:29.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:29.97#ibcon#enter wrdev, iclass 35, count 2 2006.257.13:13:29.97#ibcon#first serial, iclass 35, count 2 2006.257.13:13:29.97#ibcon#enter sib2, iclass 35, count 2 2006.257.13:13:29.97#ibcon#flushed, iclass 35, count 2 2006.257.13:13:29.97#ibcon#about to write, iclass 35, count 2 2006.257.13:13:29.97#ibcon#wrote, iclass 35, count 2 2006.257.13:13:29.97#ibcon#about to read 3, iclass 35, count 2 2006.257.13:13:29.99#ibcon#read 3, iclass 35, count 2 2006.257.13:13:29.99#ibcon#about to read 4, iclass 35, count 2 2006.257.13:13:29.99#ibcon#read 4, iclass 35, count 2 2006.257.13:13:29.99#ibcon#about to read 5, iclass 35, count 2 2006.257.13:13:29.99#ibcon#read 5, iclass 35, count 2 2006.257.13:13:29.99#ibcon#about to read 6, iclass 35, count 2 2006.257.13:13:29.99#ibcon#read 6, iclass 35, count 2 2006.257.13:13:29.99#ibcon#end of sib2, iclass 35, count 2 2006.257.13:13:29.99#ibcon#*mode == 0, iclass 35, count 2 2006.257.13:13:29.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.13:13:29.99#ibcon#[25=AT03-08\r\n] 2006.257.13:13:29.99#ibcon#*before write, iclass 35, count 2 2006.257.13:13:29.99#ibcon#enter sib2, iclass 35, count 2 2006.257.13:13:29.99#ibcon#flushed, iclass 35, count 2 2006.257.13:13:29.99#ibcon#about to write, iclass 35, count 2 2006.257.13:13:29.99#ibcon#wrote, iclass 35, count 2 2006.257.13:13:29.99#ibcon#about to read 3, iclass 35, count 2 2006.257.13:13:30.02#ibcon#read 3, iclass 35, count 2 2006.257.13:13:30.02#ibcon#about to read 4, iclass 35, count 2 2006.257.13:13:30.02#ibcon#read 4, iclass 35, count 2 2006.257.13:13:30.02#ibcon#about to read 5, iclass 35, count 2 2006.257.13:13:30.02#ibcon#read 5, iclass 35, count 2 2006.257.13:13:30.02#ibcon#about to read 6, iclass 35, count 2 2006.257.13:13:30.02#ibcon#read 6, iclass 35, count 2 2006.257.13:13:30.02#ibcon#end of sib2, iclass 35, count 2 2006.257.13:13:30.02#ibcon#*after write, iclass 35, count 2 2006.257.13:13:30.02#ibcon#*before return 0, iclass 35, count 2 2006.257.13:13:30.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:30.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:30.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.13:13:30.02#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:30.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:30.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:30.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:30.14#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:13:30.14#ibcon#first serial, iclass 35, count 0 2006.257.13:13:30.14#ibcon#enter sib2, iclass 35, count 0 2006.257.13:13:30.14#ibcon#flushed, iclass 35, count 0 2006.257.13:13:30.14#ibcon#about to write, iclass 35, count 0 2006.257.13:13:30.14#ibcon#wrote, iclass 35, count 0 2006.257.13:13:30.14#ibcon#about to read 3, iclass 35, count 0 2006.257.13:13:30.16#ibcon#read 3, iclass 35, count 0 2006.257.13:13:30.16#ibcon#about to read 4, iclass 35, count 0 2006.257.13:13:30.16#ibcon#read 4, iclass 35, count 0 2006.257.13:13:30.16#ibcon#about to read 5, iclass 35, count 0 2006.257.13:13:30.16#ibcon#read 5, iclass 35, count 0 2006.257.13:13:30.16#ibcon#about to read 6, iclass 35, count 0 2006.257.13:13:30.16#ibcon#read 6, iclass 35, count 0 2006.257.13:13:30.16#ibcon#end of sib2, iclass 35, count 0 2006.257.13:13:30.16#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:13:30.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:13:30.16#ibcon#[25=USB\r\n] 2006.257.13:13:30.16#ibcon#*before write, iclass 35, count 0 2006.257.13:13:30.16#ibcon#enter sib2, iclass 35, count 0 2006.257.13:13:30.16#ibcon#flushed, iclass 35, count 0 2006.257.13:13:30.16#ibcon#about to write, iclass 35, count 0 2006.257.13:13:30.16#ibcon#wrote, iclass 35, count 0 2006.257.13:13:30.16#ibcon#about to read 3, iclass 35, count 0 2006.257.13:13:30.19#ibcon#read 3, iclass 35, count 0 2006.257.13:13:30.19#ibcon#about to read 4, iclass 35, count 0 2006.257.13:13:30.19#ibcon#read 4, iclass 35, count 0 2006.257.13:13:30.19#ibcon#about to read 5, iclass 35, count 0 2006.257.13:13:30.19#ibcon#read 5, iclass 35, count 0 2006.257.13:13:30.19#ibcon#about to read 6, iclass 35, count 0 2006.257.13:13:30.19#ibcon#read 6, iclass 35, count 0 2006.257.13:13:30.19#ibcon#end of sib2, iclass 35, count 0 2006.257.13:13:30.19#ibcon#*after write, iclass 35, count 0 2006.257.13:13:30.19#ibcon#*before return 0, iclass 35, count 0 2006.257.13:13:30.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:30.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:30.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:13:30.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:13:30.19$vck44/valo=4,624.99 2006.257.13:13:30.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.13:13:30.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.13:13:30.19#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:30.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:30.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:30.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:30.19#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:13:30.19#ibcon#first serial, iclass 37, count 0 2006.257.13:13:30.19#ibcon#enter sib2, iclass 37, count 0 2006.257.13:13:30.19#ibcon#flushed, iclass 37, count 0 2006.257.13:13:30.19#ibcon#about to write, iclass 37, count 0 2006.257.13:13:30.19#ibcon#wrote, iclass 37, count 0 2006.257.13:13:30.19#ibcon#about to read 3, iclass 37, count 0 2006.257.13:13:30.21#ibcon#read 3, iclass 37, count 0 2006.257.13:13:30.21#ibcon#about to read 4, iclass 37, count 0 2006.257.13:13:30.21#ibcon#read 4, iclass 37, count 0 2006.257.13:13:30.21#ibcon#about to read 5, iclass 37, count 0 2006.257.13:13:30.21#ibcon#read 5, iclass 37, count 0 2006.257.13:13:30.21#ibcon#about to read 6, iclass 37, count 0 2006.257.13:13:30.21#ibcon#read 6, iclass 37, count 0 2006.257.13:13:30.21#ibcon#end of sib2, iclass 37, count 0 2006.257.13:13:30.21#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:13:30.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:13:30.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:13:30.21#ibcon#*before write, iclass 37, count 0 2006.257.13:13:30.21#ibcon#enter sib2, iclass 37, count 0 2006.257.13:13:30.21#ibcon#flushed, iclass 37, count 0 2006.257.13:13:30.21#ibcon#about to write, iclass 37, count 0 2006.257.13:13:30.21#ibcon#wrote, iclass 37, count 0 2006.257.13:13:30.21#ibcon#about to read 3, iclass 37, count 0 2006.257.13:13:30.25#ibcon#read 3, iclass 37, count 0 2006.257.13:13:30.25#ibcon#about to read 4, iclass 37, count 0 2006.257.13:13:30.25#ibcon#read 4, iclass 37, count 0 2006.257.13:13:30.25#ibcon#about to read 5, iclass 37, count 0 2006.257.13:13:30.25#ibcon#read 5, iclass 37, count 0 2006.257.13:13:30.25#ibcon#about to read 6, iclass 37, count 0 2006.257.13:13:30.25#ibcon#read 6, iclass 37, count 0 2006.257.13:13:30.25#ibcon#end of sib2, iclass 37, count 0 2006.257.13:13:30.25#ibcon#*after write, iclass 37, count 0 2006.257.13:13:30.25#ibcon#*before return 0, iclass 37, count 0 2006.257.13:13:30.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:30.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:30.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:13:30.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:13:30.25$vck44/va=4,7 2006.257.13:13:30.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.13:13:30.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.13:13:30.25#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:30.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:30.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:30.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:30.31#ibcon#enter wrdev, iclass 39, count 2 2006.257.13:13:30.31#ibcon#first serial, iclass 39, count 2 2006.257.13:13:30.31#ibcon#enter sib2, iclass 39, count 2 2006.257.13:13:30.31#ibcon#flushed, iclass 39, count 2 2006.257.13:13:30.31#ibcon#about to write, iclass 39, count 2 2006.257.13:13:30.31#ibcon#wrote, iclass 39, count 2 2006.257.13:13:30.31#ibcon#about to read 3, iclass 39, count 2 2006.257.13:13:30.33#ibcon#read 3, iclass 39, count 2 2006.257.13:13:30.33#ibcon#about to read 4, iclass 39, count 2 2006.257.13:13:30.33#ibcon#read 4, iclass 39, count 2 2006.257.13:13:30.33#ibcon#about to read 5, iclass 39, count 2 2006.257.13:13:30.33#ibcon#read 5, iclass 39, count 2 2006.257.13:13:30.33#ibcon#about to read 6, iclass 39, count 2 2006.257.13:13:30.33#ibcon#read 6, iclass 39, count 2 2006.257.13:13:30.33#ibcon#end of sib2, iclass 39, count 2 2006.257.13:13:30.33#ibcon#*mode == 0, iclass 39, count 2 2006.257.13:13:30.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.13:13:30.33#ibcon#[25=AT04-07\r\n] 2006.257.13:13:30.33#ibcon#*before write, iclass 39, count 2 2006.257.13:13:30.33#ibcon#enter sib2, iclass 39, count 2 2006.257.13:13:30.33#ibcon#flushed, iclass 39, count 2 2006.257.13:13:30.33#ibcon#about to write, iclass 39, count 2 2006.257.13:13:30.33#ibcon#wrote, iclass 39, count 2 2006.257.13:13:30.33#ibcon#about to read 3, iclass 39, count 2 2006.257.13:13:30.36#ibcon#read 3, iclass 39, count 2 2006.257.13:13:30.36#ibcon#about to read 4, iclass 39, count 2 2006.257.13:13:30.36#ibcon#read 4, iclass 39, count 2 2006.257.13:13:30.36#ibcon#about to read 5, iclass 39, count 2 2006.257.13:13:30.36#ibcon#read 5, iclass 39, count 2 2006.257.13:13:30.36#ibcon#about to read 6, iclass 39, count 2 2006.257.13:13:30.36#ibcon#read 6, iclass 39, count 2 2006.257.13:13:30.36#ibcon#end of sib2, iclass 39, count 2 2006.257.13:13:30.36#ibcon#*after write, iclass 39, count 2 2006.257.13:13:30.36#ibcon#*before return 0, iclass 39, count 2 2006.257.13:13:30.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:30.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:30.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.13:13:30.36#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:30.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:30.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:30.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:30.48#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:13:30.48#ibcon#first serial, iclass 39, count 0 2006.257.13:13:30.48#ibcon#enter sib2, iclass 39, count 0 2006.257.13:13:30.48#ibcon#flushed, iclass 39, count 0 2006.257.13:13:30.48#ibcon#about to write, iclass 39, count 0 2006.257.13:13:30.48#ibcon#wrote, iclass 39, count 0 2006.257.13:13:30.48#ibcon#about to read 3, iclass 39, count 0 2006.257.13:13:30.50#ibcon#read 3, iclass 39, count 0 2006.257.13:13:30.50#ibcon#about to read 4, iclass 39, count 0 2006.257.13:13:30.50#ibcon#read 4, iclass 39, count 0 2006.257.13:13:30.50#ibcon#about to read 5, iclass 39, count 0 2006.257.13:13:30.50#ibcon#read 5, iclass 39, count 0 2006.257.13:13:30.50#ibcon#about to read 6, iclass 39, count 0 2006.257.13:13:30.50#ibcon#read 6, iclass 39, count 0 2006.257.13:13:30.50#ibcon#end of sib2, iclass 39, count 0 2006.257.13:13:30.50#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:13:30.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:13:30.50#ibcon#[25=USB\r\n] 2006.257.13:13:30.50#ibcon#*before write, iclass 39, count 0 2006.257.13:13:30.50#ibcon#enter sib2, iclass 39, count 0 2006.257.13:13:30.50#ibcon#flushed, iclass 39, count 0 2006.257.13:13:30.50#ibcon#about to write, iclass 39, count 0 2006.257.13:13:30.50#ibcon#wrote, iclass 39, count 0 2006.257.13:13:30.50#ibcon#about to read 3, iclass 39, count 0 2006.257.13:13:30.53#ibcon#read 3, iclass 39, count 0 2006.257.13:13:30.53#ibcon#about to read 4, iclass 39, count 0 2006.257.13:13:30.53#ibcon#read 4, iclass 39, count 0 2006.257.13:13:30.53#ibcon#about to read 5, iclass 39, count 0 2006.257.13:13:30.53#ibcon#read 5, iclass 39, count 0 2006.257.13:13:30.53#ibcon#about to read 6, iclass 39, count 0 2006.257.13:13:30.53#ibcon#read 6, iclass 39, count 0 2006.257.13:13:30.53#ibcon#end of sib2, iclass 39, count 0 2006.257.13:13:30.53#ibcon#*after write, iclass 39, count 0 2006.257.13:13:30.53#ibcon#*before return 0, iclass 39, count 0 2006.257.13:13:30.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:30.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:30.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:13:30.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:13:30.53$vck44/valo=5,734.99 2006.257.13:13:30.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.13:13:30.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.13:13:30.53#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:30.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:30.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:30.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:30.53#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:13:30.53#ibcon#first serial, iclass 3, count 0 2006.257.13:13:30.53#ibcon#enter sib2, iclass 3, count 0 2006.257.13:13:30.53#ibcon#flushed, iclass 3, count 0 2006.257.13:13:30.53#ibcon#about to write, iclass 3, count 0 2006.257.13:13:30.53#ibcon#wrote, iclass 3, count 0 2006.257.13:13:30.53#ibcon#about to read 3, iclass 3, count 0 2006.257.13:13:30.55#ibcon#read 3, iclass 3, count 0 2006.257.13:13:30.55#ibcon#about to read 4, iclass 3, count 0 2006.257.13:13:30.55#ibcon#read 4, iclass 3, count 0 2006.257.13:13:30.55#ibcon#about to read 5, iclass 3, count 0 2006.257.13:13:30.55#ibcon#read 5, iclass 3, count 0 2006.257.13:13:30.55#ibcon#about to read 6, iclass 3, count 0 2006.257.13:13:30.55#ibcon#read 6, iclass 3, count 0 2006.257.13:13:30.55#ibcon#end of sib2, iclass 3, count 0 2006.257.13:13:30.55#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:13:30.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:13:30.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:13:30.55#ibcon#*before write, iclass 3, count 0 2006.257.13:13:30.55#ibcon#enter sib2, iclass 3, count 0 2006.257.13:13:30.55#ibcon#flushed, iclass 3, count 0 2006.257.13:13:30.55#ibcon#about to write, iclass 3, count 0 2006.257.13:13:30.55#ibcon#wrote, iclass 3, count 0 2006.257.13:13:30.55#ibcon#about to read 3, iclass 3, count 0 2006.257.13:13:30.59#ibcon#read 3, iclass 3, count 0 2006.257.13:13:30.59#ibcon#about to read 4, iclass 3, count 0 2006.257.13:13:30.59#ibcon#read 4, iclass 3, count 0 2006.257.13:13:30.59#ibcon#about to read 5, iclass 3, count 0 2006.257.13:13:30.59#ibcon#read 5, iclass 3, count 0 2006.257.13:13:30.59#ibcon#about to read 6, iclass 3, count 0 2006.257.13:13:30.59#ibcon#read 6, iclass 3, count 0 2006.257.13:13:30.59#ibcon#end of sib2, iclass 3, count 0 2006.257.13:13:30.59#ibcon#*after write, iclass 3, count 0 2006.257.13:13:30.59#ibcon#*before return 0, iclass 3, count 0 2006.257.13:13:30.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:30.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:30.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:13:30.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:13:30.59$vck44/va=5,4 2006.257.13:13:30.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.13:13:30.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.13:13:30.59#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:30.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:30.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:30.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:30.65#ibcon#enter wrdev, iclass 5, count 2 2006.257.13:13:30.65#ibcon#first serial, iclass 5, count 2 2006.257.13:13:30.65#ibcon#enter sib2, iclass 5, count 2 2006.257.13:13:30.65#ibcon#flushed, iclass 5, count 2 2006.257.13:13:30.65#ibcon#about to write, iclass 5, count 2 2006.257.13:13:30.65#ibcon#wrote, iclass 5, count 2 2006.257.13:13:30.65#ibcon#about to read 3, iclass 5, count 2 2006.257.13:13:30.67#ibcon#read 3, iclass 5, count 2 2006.257.13:13:30.67#ibcon#about to read 4, iclass 5, count 2 2006.257.13:13:30.67#ibcon#read 4, iclass 5, count 2 2006.257.13:13:30.67#ibcon#about to read 5, iclass 5, count 2 2006.257.13:13:30.67#ibcon#read 5, iclass 5, count 2 2006.257.13:13:30.67#ibcon#about to read 6, iclass 5, count 2 2006.257.13:13:30.67#ibcon#read 6, iclass 5, count 2 2006.257.13:13:30.67#ibcon#end of sib2, iclass 5, count 2 2006.257.13:13:30.67#ibcon#*mode == 0, iclass 5, count 2 2006.257.13:13:30.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.13:13:30.67#ibcon#[25=AT05-04\r\n] 2006.257.13:13:30.67#ibcon#*before write, iclass 5, count 2 2006.257.13:13:30.67#ibcon#enter sib2, iclass 5, count 2 2006.257.13:13:30.67#ibcon#flushed, iclass 5, count 2 2006.257.13:13:30.67#ibcon#about to write, iclass 5, count 2 2006.257.13:13:30.67#ibcon#wrote, iclass 5, count 2 2006.257.13:13:30.67#ibcon#about to read 3, iclass 5, count 2 2006.257.13:13:30.70#ibcon#read 3, iclass 5, count 2 2006.257.13:13:30.70#ibcon#about to read 4, iclass 5, count 2 2006.257.13:13:30.70#ibcon#read 4, iclass 5, count 2 2006.257.13:13:30.70#ibcon#about to read 5, iclass 5, count 2 2006.257.13:13:30.70#ibcon#read 5, iclass 5, count 2 2006.257.13:13:30.70#ibcon#about to read 6, iclass 5, count 2 2006.257.13:13:30.70#ibcon#read 6, iclass 5, count 2 2006.257.13:13:30.70#ibcon#end of sib2, iclass 5, count 2 2006.257.13:13:30.70#ibcon#*after write, iclass 5, count 2 2006.257.13:13:30.70#ibcon#*before return 0, iclass 5, count 2 2006.257.13:13:30.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:30.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:30.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.13:13:30.70#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:30.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:30.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:30.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:30.82#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:13:30.82#ibcon#first serial, iclass 5, count 0 2006.257.13:13:30.82#ibcon#enter sib2, iclass 5, count 0 2006.257.13:13:30.82#ibcon#flushed, iclass 5, count 0 2006.257.13:13:30.82#ibcon#about to write, iclass 5, count 0 2006.257.13:13:30.82#ibcon#wrote, iclass 5, count 0 2006.257.13:13:30.82#ibcon#about to read 3, iclass 5, count 0 2006.257.13:13:30.84#ibcon#read 3, iclass 5, count 0 2006.257.13:13:30.84#ibcon#about to read 4, iclass 5, count 0 2006.257.13:13:30.84#ibcon#read 4, iclass 5, count 0 2006.257.13:13:30.84#ibcon#about to read 5, iclass 5, count 0 2006.257.13:13:30.84#ibcon#read 5, iclass 5, count 0 2006.257.13:13:30.84#ibcon#about to read 6, iclass 5, count 0 2006.257.13:13:30.84#ibcon#read 6, iclass 5, count 0 2006.257.13:13:30.84#ibcon#end of sib2, iclass 5, count 0 2006.257.13:13:30.84#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:13:30.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:13:30.84#ibcon#[25=USB\r\n] 2006.257.13:13:30.84#ibcon#*before write, iclass 5, count 0 2006.257.13:13:30.84#ibcon#enter sib2, iclass 5, count 0 2006.257.13:13:30.84#ibcon#flushed, iclass 5, count 0 2006.257.13:13:30.84#ibcon#about to write, iclass 5, count 0 2006.257.13:13:30.84#ibcon#wrote, iclass 5, count 0 2006.257.13:13:30.84#ibcon#about to read 3, iclass 5, count 0 2006.257.13:13:30.87#ibcon#read 3, iclass 5, count 0 2006.257.13:13:30.87#ibcon#about to read 4, iclass 5, count 0 2006.257.13:13:30.87#ibcon#read 4, iclass 5, count 0 2006.257.13:13:30.87#ibcon#about to read 5, iclass 5, count 0 2006.257.13:13:30.87#ibcon#read 5, iclass 5, count 0 2006.257.13:13:30.87#ibcon#about to read 6, iclass 5, count 0 2006.257.13:13:30.87#ibcon#read 6, iclass 5, count 0 2006.257.13:13:30.87#ibcon#end of sib2, iclass 5, count 0 2006.257.13:13:30.87#ibcon#*after write, iclass 5, count 0 2006.257.13:13:30.87#ibcon#*before return 0, iclass 5, count 0 2006.257.13:13:30.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:30.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:30.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:13:30.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:13:30.87$vck44/valo=6,814.99 2006.257.13:13:30.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.13:13:30.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.13:13:30.87#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:30.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:30.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:30.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:30.87#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:13:30.87#ibcon#first serial, iclass 7, count 0 2006.257.13:13:30.87#ibcon#enter sib2, iclass 7, count 0 2006.257.13:13:30.87#ibcon#flushed, iclass 7, count 0 2006.257.13:13:30.87#ibcon#about to write, iclass 7, count 0 2006.257.13:13:30.87#ibcon#wrote, iclass 7, count 0 2006.257.13:13:30.87#ibcon#about to read 3, iclass 7, count 0 2006.257.13:13:30.89#ibcon#read 3, iclass 7, count 0 2006.257.13:13:30.89#ibcon#about to read 4, iclass 7, count 0 2006.257.13:13:30.89#ibcon#read 4, iclass 7, count 0 2006.257.13:13:30.89#ibcon#about to read 5, iclass 7, count 0 2006.257.13:13:30.89#ibcon#read 5, iclass 7, count 0 2006.257.13:13:30.89#ibcon#about to read 6, iclass 7, count 0 2006.257.13:13:30.89#ibcon#read 6, iclass 7, count 0 2006.257.13:13:30.89#ibcon#end of sib2, iclass 7, count 0 2006.257.13:13:30.89#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:13:30.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:13:30.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:13:30.89#ibcon#*before write, iclass 7, count 0 2006.257.13:13:30.89#ibcon#enter sib2, iclass 7, count 0 2006.257.13:13:30.89#ibcon#flushed, iclass 7, count 0 2006.257.13:13:30.89#ibcon#about to write, iclass 7, count 0 2006.257.13:13:30.89#ibcon#wrote, iclass 7, count 0 2006.257.13:13:30.89#ibcon#about to read 3, iclass 7, count 0 2006.257.13:13:30.93#ibcon#read 3, iclass 7, count 0 2006.257.13:13:30.93#ibcon#about to read 4, iclass 7, count 0 2006.257.13:13:30.93#ibcon#read 4, iclass 7, count 0 2006.257.13:13:30.93#ibcon#about to read 5, iclass 7, count 0 2006.257.13:13:30.93#ibcon#read 5, iclass 7, count 0 2006.257.13:13:30.93#ibcon#about to read 6, iclass 7, count 0 2006.257.13:13:30.93#ibcon#read 6, iclass 7, count 0 2006.257.13:13:30.93#ibcon#end of sib2, iclass 7, count 0 2006.257.13:13:30.93#ibcon#*after write, iclass 7, count 0 2006.257.13:13:30.93#ibcon#*before return 0, iclass 7, count 0 2006.257.13:13:30.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:30.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:30.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:13:30.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:13:30.93$vck44/va=6,4 2006.257.13:13:30.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.13:13:30.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.13:13:30.93#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:30.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:30.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:30.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:30.99#ibcon#enter wrdev, iclass 11, count 2 2006.257.13:13:30.99#ibcon#first serial, iclass 11, count 2 2006.257.13:13:30.99#ibcon#enter sib2, iclass 11, count 2 2006.257.13:13:30.99#ibcon#flushed, iclass 11, count 2 2006.257.13:13:30.99#ibcon#about to write, iclass 11, count 2 2006.257.13:13:30.99#ibcon#wrote, iclass 11, count 2 2006.257.13:13:30.99#ibcon#about to read 3, iclass 11, count 2 2006.257.13:13:31.01#ibcon#read 3, iclass 11, count 2 2006.257.13:13:31.01#ibcon#about to read 4, iclass 11, count 2 2006.257.13:13:31.01#ibcon#read 4, iclass 11, count 2 2006.257.13:13:31.01#ibcon#about to read 5, iclass 11, count 2 2006.257.13:13:31.01#ibcon#read 5, iclass 11, count 2 2006.257.13:13:31.01#ibcon#about to read 6, iclass 11, count 2 2006.257.13:13:31.01#ibcon#read 6, iclass 11, count 2 2006.257.13:13:31.01#ibcon#end of sib2, iclass 11, count 2 2006.257.13:13:31.01#ibcon#*mode == 0, iclass 11, count 2 2006.257.13:13:31.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.13:13:31.01#ibcon#[25=AT06-04\r\n] 2006.257.13:13:31.01#ibcon#*before write, iclass 11, count 2 2006.257.13:13:31.01#ibcon#enter sib2, iclass 11, count 2 2006.257.13:13:31.01#ibcon#flushed, iclass 11, count 2 2006.257.13:13:31.01#ibcon#about to write, iclass 11, count 2 2006.257.13:13:31.01#ibcon#wrote, iclass 11, count 2 2006.257.13:13:31.01#ibcon#about to read 3, iclass 11, count 2 2006.257.13:13:31.04#ibcon#read 3, iclass 11, count 2 2006.257.13:13:31.04#ibcon#about to read 4, iclass 11, count 2 2006.257.13:13:31.04#ibcon#read 4, iclass 11, count 2 2006.257.13:13:31.04#ibcon#about to read 5, iclass 11, count 2 2006.257.13:13:31.04#ibcon#read 5, iclass 11, count 2 2006.257.13:13:31.04#ibcon#about to read 6, iclass 11, count 2 2006.257.13:13:31.04#ibcon#read 6, iclass 11, count 2 2006.257.13:13:31.04#ibcon#end of sib2, iclass 11, count 2 2006.257.13:13:31.04#ibcon#*after write, iclass 11, count 2 2006.257.13:13:31.04#ibcon#*before return 0, iclass 11, count 2 2006.257.13:13:31.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:31.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:31.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.13:13:31.04#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:31.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:31.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:31.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:31.16#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:13:31.16#ibcon#first serial, iclass 11, count 0 2006.257.13:13:31.16#ibcon#enter sib2, iclass 11, count 0 2006.257.13:13:31.16#ibcon#flushed, iclass 11, count 0 2006.257.13:13:31.16#ibcon#about to write, iclass 11, count 0 2006.257.13:13:31.16#ibcon#wrote, iclass 11, count 0 2006.257.13:13:31.16#ibcon#about to read 3, iclass 11, count 0 2006.257.13:13:31.18#ibcon#read 3, iclass 11, count 0 2006.257.13:13:31.18#ibcon#about to read 4, iclass 11, count 0 2006.257.13:13:31.18#ibcon#read 4, iclass 11, count 0 2006.257.13:13:31.18#ibcon#about to read 5, iclass 11, count 0 2006.257.13:13:31.18#ibcon#read 5, iclass 11, count 0 2006.257.13:13:31.18#ibcon#about to read 6, iclass 11, count 0 2006.257.13:13:31.18#ibcon#read 6, iclass 11, count 0 2006.257.13:13:31.18#ibcon#end of sib2, iclass 11, count 0 2006.257.13:13:31.18#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:13:31.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:13:31.18#ibcon#[25=USB\r\n] 2006.257.13:13:31.18#ibcon#*before write, iclass 11, count 0 2006.257.13:13:31.18#ibcon#enter sib2, iclass 11, count 0 2006.257.13:13:31.18#ibcon#flushed, iclass 11, count 0 2006.257.13:13:31.18#ibcon#about to write, iclass 11, count 0 2006.257.13:13:31.18#ibcon#wrote, iclass 11, count 0 2006.257.13:13:31.18#ibcon#about to read 3, iclass 11, count 0 2006.257.13:13:31.21#ibcon#read 3, iclass 11, count 0 2006.257.13:13:31.21#ibcon#about to read 4, iclass 11, count 0 2006.257.13:13:31.21#ibcon#read 4, iclass 11, count 0 2006.257.13:13:31.21#ibcon#about to read 5, iclass 11, count 0 2006.257.13:13:31.21#ibcon#read 5, iclass 11, count 0 2006.257.13:13:31.21#ibcon#about to read 6, iclass 11, count 0 2006.257.13:13:31.21#ibcon#read 6, iclass 11, count 0 2006.257.13:13:31.21#ibcon#end of sib2, iclass 11, count 0 2006.257.13:13:31.21#ibcon#*after write, iclass 11, count 0 2006.257.13:13:31.21#ibcon#*before return 0, iclass 11, count 0 2006.257.13:13:31.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:31.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:31.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:13:31.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:13:31.21$vck44/valo=7,864.99 2006.257.13:13:31.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:13:31.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:13:31.21#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:31.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:31.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:31.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:31.21#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:13:31.21#ibcon#first serial, iclass 13, count 0 2006.257.13:13:31.21#ibcon#enter sib2, iclass 13, count 0 2006.257.13:13:31.21#ibcon#flushed, iclass 13, count 0 2006.257.13:13:31.21#ibcon#about to write, iclass 13, count 0 2006.257.13:13:31.21#ibcon#wrote, iclass 13, count 0 2006.257.13:13:31.21#ibcon#about to read 3, iclass 13, count 0 2006.257.13:13:31.23#ibcon#read 3, iclass 13, count 0 2006.257.13:13:31.23#ibcon#about to read 4, iclass 13, count 0 2006.257.13:13:31.23#ibcon#read 4, iclass 13, count 0 2006.257.13:13:31.23#ibcon#about to read 5, iclass 13, count 0 2006.257.13:13:31.23#ibcon#read 5, iclass 13, count 0 2006.257.13:13:31.23#ibcon#about to read 6, iclass 13, count 0 2006.257.13:13:31.23#ibcon#read 6, iclass 13, count 0 2006.257.13:13:31.23#ibcon#end of sib2, iclass 13, count 0 2006.257.13:13:31.23#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:13:31.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:13:31.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:13:31.23#ibcon#*before write, iclass 13, count 0 2006.257.13:13:31.23#ibcon#enter sib2, iclass 13, count 0 2006.257.13:13:31.23#ibcon#flushed, iclass 13, count 0 2006.257.13:13:31.23#ibcon#about to write, iclass 13, count 0 2006.257.13:13:31.23#ibcon#wrote, iclass 13, count 0 2006.257.13:13:31.23#ibcon#about to read 3, iclass 13, count 0 2006.257.13:13:31.27#ibcon#read 3, iclass 13, count 0 2006.257.13:13:31.27#ibcon#about to read 4, iclass 13, count 0 2006.257.13:13:31.27#ibcon#read 4, iclass 13, count 0 2006.257.13:13:31.27#ibcon#about to read 5, iclass 13, count 0 2006.257.13:13:31.27#ibcon#read 5, iclass 13, count 0 2006.257.13:13:31.27#ibcon#about to read 6, iclass 13, count 0 2006.257.13:13:31.27#ibcon#read 6, iclass 13, count 0 2006.257.13:13:31.27#ibcon#end of sib2, iclass 13, count 0 2006.257.13:13:31.27#ibcon#*after write, iclass 13, count 0 2006.257.13:13:31.27#ibcon#*before return 0, iclass 13, count 0 2006.257.13:13:31.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:31.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:31.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:13:31.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:13:31.27$vck44/va=7,4 2006.257.13:13:31.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.13:13:31.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.13:13:31.27#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:31.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:31.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:31.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:31.33#ibcon#enter wrdev, iclass 15, count 2 2006.257.13:13:31.33#ibcon#first serial, iclass 15, count 2 2006.257.13:13:31.33#ibcon#enter sib2, iclass 15, count 2 2006.257.13:13:31.33#ibcon#flushed, iclass 15, count 2 2006.257.13:13:31.33#ibcon#about to write, iclass 15, count 2 2006.257.13:13:31.33#ibcon#wrote, iclass 15, count 2 2006.257.13:13:31.33#ibcon#about to read 3, iclass 15, count 2 2006.257.13:13:31.35#ibcon#read 3, iclass 15, count 2 2006.257.13:13:31.35#ibcon#about to read 4, iclass 15, count 2 2006.257.13:13:31.35#ibcon#read 4, iclass 15, count 2 2006.257.13:13:31.35#ibcon#about to read 5, iclass 15, count 2 2006.257.13:13:31.35#ibcon#read 5, iclass 15, count 2 2006.257.13:13:31.35#ibcon#about to read 6, iclass 15, count 2 2006.257.13:13:31.35#ibcon#read 6, iclass 15, count 2 2006.257.13:13:31.35#ibcon#end of sib2, iclass 15, count 2 2006.257.13:13:31.35#ibcon#*mode == 0, iclass 15, count 2 2006.257.13:13:31.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.13:13:31.35#ibcon#[25=AT07-04\r\n] 2006.257.13:13:31.35#ibcon#*before write, iclass 15, count 2 2006.257.13:13:31.35#ibcon#enter sib2, iclass 15, count 2 2006.257.13:13:31.35#ibcon#flushed, iclass 15, count 2 2006.257.13:13:31.35#ibcon#about to write, iclass 15, count 2 2006.257.13:13:31.35#ibcon#wrote, iclass 15, count 2 2006.257.13:13:31.35#ibcon#about to read 3, iclass 15, count 2 2006.257.13:13:31.38#ibcon#read 3, iclass 15, count 2 2006.257.13:13:31.38#ibcon#about to read 4, iclass 15, count 2 2006.257.13:13:31.38#ibcon#read 4, iclass 15, count 2 2006.257.13:13:31.38#ibcon#about to read 5, iclass 15, count 2 2006.257.13:13:31.38#ibcon#read 5, iclass 15, count 2 2006.257.13:13:31.38#ibcon#about to read 6, iclass 15, count 2 2006.257.13:13:31.38#ibcon#read 6, iclass 15, count 2 2006.257.13:13:31.38#ibcon#end of sib2, iclass 15, count 2 2006.257.13:13:31.38#ibcon#*after write, iclass 15, count 2 2006.257.13:13:31.38#ibcon#*before return 0, iclass 15, count 2 2006.257.13:13:31.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:31.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:31.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.13:13:31.38#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:31.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:31.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:31.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:31.50#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:13:31.50#ibcon#first serial, iclass 15, count 0 2006.257.13:13:31.50#ibcon#enter sib2, iclass 15, count 0 2006.257.13:13:31.50#ibcon#flushed, iclass 15, count 0 2006.257.13:13:31.50#ibcon#about to write, iclass 15, count 0 2006.257.13:13:31.50#ibcon#wrote, iclass 15, count 0 2006.257.13:13:31.50#ibcon#about to read 3, iclass 15, count 0 2006.257.13:13:31.52#ibcon#read 3, iclass 15, count 0 2006.257.13:13:31.52#ibcon#about to read 4, iclass 15, count 0 2006.257.13:13:31.52#ibcon#read 4, iclass 15, count 0 2006.257.13:13:31.52#ibcon#about to read 5, iclass 15, count 0 2006.257.13:13:31.52#ibcon#read 5, iclass 15, count 0 2006.257.13:13:31.52#ibcon#about to read 6, iclass 15, count 0 2006.257.13:13:31.52#ibcon#read 6, iclass 15, count 0 2006.257.13:13:31.52#ibcon#end of sib2, iclass 15, count 0 2006.257.13:13:31.52#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:13:31.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:13:31.52#ibcon#[25=USB\r\n] 2006.257.13:13:31.52#ibcon#*before write, iclass 15, count 0 2006.257.13:13:31.52#ibcon#enter sib2, iclass 15, count 0 2006.257.13:13:31.52#ibcon#flushed, iclass 15, count 0 2006.257.13:13:31.52#ibcon#about to write, iclass 15, count 0 2006.257.13:13:31.52#ibcon#wrote, iclass 15, count 0 2006.257.13:13:31.52#ibcon#about to read 3, iclass 15, count 0 2006.257.13:13:31.55#ibcon#read 3, iclass 15, count 0 2006.257.13:13:31.55#ibcon#about to read 4, iclass 15, count 0 2006.257.13:13:31.55#ibcon#read 4, iclass 15, count 0 2006.257.13:13:31.55#ibcon#about to read 5, iclass 15, count 0 2006.257.13:13:31.55#ibcon#read 5, iclass 15, count 0 2006.257.13:13:31.55#ibcon#about to read 6, iclass 15, count 0 2006.257.13:13:31.55#ibcon#read 6, iclass 15, count 0 2006.257.13:13:31.55#ibcon#end of sib2, iclass 15, count 0 2006.257.13:13:31.55#ibcon#*after write, iclass 15, count 0 2006.257.13:13:31.55#ibcon#*before return 0, iclass 15, count 0 2006.257.13:13:31.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:31.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:31.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:13:31.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:13:31.55$vck44/valo=8,884.99 2006.257.13:13:31.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.13:13:31.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.13:13:31.55#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:31.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:31.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:31.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:31.55#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:13:31.55#ibcon#first serial, iclass 17, count 0 2006.257.13:13:31.55#ibcon#enter sib2, iclass 17, count 0 2006.257.13:13:31.55#ibcon#flushed, iclass 17, count 0 2006.257.13:13:31.55#ibcon#about to write, iclass 17, count 0 2006.257.13:13:31.55#ibcon#wrote, iclass 17, count 0 2006.257.13:13:31.55#ibcon#about to read 3, iclass 17, count 0 2006.257.13:13:31.57#ibcon#read 3, iclass 17, count 0 2006.257.13:13:31.57#ibcon#about to read 4, iclass 17, count 0 2006.257.13:13:31.57#ibcon#read 4, iclass 17, count 0 2006.257.13:13:31.57#ibcon#about to read 5, iclass 17, count 0 2006.257.13:13:31.57#ibcon#read 5, iclass 17, count 0 2006.257.13:13:31.57#ibcon#about to read 6, iclass 17, count 0 2006.257.13:13:31.57#ibcon#read 6, iclass 17, count 0 2006.257.13:13:31.57#ibcon#end of sib2, iclass 17, count 0 2006.257.13:13:31.57#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:13:31.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:13:31.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:13:31.57#ibcon#*before write, iclass 17, count 0 2006.257.13:13:31.57#ibcon#enter sib2, iclass 17, count 0 2006.257.13:13:31.57#ibcon#flushed, iclass 17, count 0 2006.257.13:13:31.57#ibcon#about to write, iclass 17, count 0 2006.257.13:13:31.57#ibcon#wrote, iclass 17, count 0 2006.257.13:13:31.57#ibcon#about to read 3, iclass 17, count 0 2006.257.13:13:31.61#ibcon#read 3, iclass 17, count 0 2006.257.13:13:31.61#ibcon#about to read 4, iclass 17, count 0 2006.257.13:13:31.61#ibcon#read 4, iclass 17, count 0 2006.257.13:13:31.61#ibcon#about to read 5, iclass 17, count 0 2006.257.13:13:31.61#ibcon#read 5, iclass 17, count 0 2006.257.13:13:31.61#ibcon#about to read 6, iclass 17, count 0 2006.257.13:13:31.61#ibcon#read 6, iclass 17, count 0 2006.257.13:13:31.61#ibcon#end of sib2, iclass 17, count 0 2006.257.13:13:31.61#ibcon#*after write, iclass 17, count 0 2006.257.13:13:31.61#ibcon#*before return 0, iclass 17, count 0 2006.257.13:13:31.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:31.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:31.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:13:31.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:13:31.61$vck44/va=8,4 2006.257.13:13:31.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.13:13:31.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.13:13:31.61#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:31.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:13:31.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:13:31.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:13:31.67#ibcon#enter wrdev, iclass 19, count 2 2006.257.13:13:31.67#ibcon#first serial, iclass 19, count 2 2006.257.13:13:31.67#ibcon#enter sib2, iclass 19, count 2 2006.257.13:13:31.67#ibcon#flushed, iclass 19, count 2 2006.257.13:13:31.67#ibcon#about to write, iclass 19, count 2 2006.257.13:13:31.67#ibcon#wrote, iclass 19, count 2 2006.257.13:13:31.67#ibcon#about to read 3, iclass 19, count 2 2006.257.13:13:31.69#ibcon#read 3, iclass 19, count 2 2006.257.13:13:31.69#ibcon#about to read 4, iclass 19, count 2 2006.257.13:13:31.69#ibcon#read 4, iclass 19, count 2 2006.257.13:13:31.69#ibcon#about to read 5, iclass 19, count 2 2006.257.13:13:31.69#ibcon#read 5, iclass 19, count 2 2006.257.13:13:31.69#ibcon#about to read 6, iclass 19, count 2 2006.257.13:13:31.69#ibcon#read 6, iclass 19, count 2 2006.257.13:13:31.69#ibcon#end of sib2, iclass 19, count 2 2006.257.13:13:31.69#ibcon#*mode == 0, iclass 19, count 2 2006.257.13:13:31.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.13:13:31.69#ibcon#[25=AT08-04\r\n] 2006.257.13:13:31.69#ibcon#*before write, iclass 19, count 2 2006.257.13:13:31.69#ibcon#enter sib2, iclass 19, count 2 2006.257.13:13:31.69#ibcon#flushed, iclass 19, count 2 2006.257.13:13:31.69#ibcon#about to write, iclass 19, count 2 2006.257.13:13:31.69#ibcon#wrote, iclass 19, count 2 2006.257.13:13:31.69#ibcon#about to read 3, iclass 19, count 2 2006.257.13:13:31.72#ibcon#read 3, iclass 19, count 2 2006.257.13:13:31.72#ibcon#about to read 4, iclass 19, count 2 2006.257.13:13:31.72#ibcon#read 4, iclass 19, count 2 2006.257.13:13:31.72#ibcon#about to read 5, iclass 19, count 2 2006.257.13:13:31.72#ibcon#read 5, iclass 19, count 2 2006.257.13:13:31.72#ibcon#about to read 6, iclass 19, count 2 2006.257.13:13:31.72#ibcon#read 6, iclass 19, count 2 2006.257.13:13:31.72#ibcon#end of sib2, iclass 19, count 2 2006.257.13:13:31.72#ibcon#*after write, iclass 19, count 2 2006.257.13:13:31.72#ibcon#*before return 0, iclass 19, count 2 2006.257.13:13:31.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:13:31.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:13:31.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.13:13:31.72#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:31.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:13:31.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:13:31.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:13:31.84#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:13:31.84#ibcon#first serial, iclass 19, count 0 2006.257.13:13:31.84#ibcon#enter sib2, iclass 19, count 0 2006.257.13:13:31.84#ibcon#flushed, iclass 19, count 0 2006.257.13:13:31.84#ibcon#about to write, iclass 19, count 0 2006.257.13:13:31.84#ibcon#wrote, iclass 19, count 0 2006.257.13:13:31.84#ibcon#about to read 3, iclass 19, count 0 2006.257.13:13:31.86#ibcon#read 3, iclass 19, count 0 2006.257.13:13:31.86#ibcon#about to read 4, iclass 19, count 0 2006.257.13:13:31.86#ibcon#read 4, iclass 19, count 0 2006.257.13:13:31.86#ibcon#about to read 5, iclass 19, count 0 2006.257.13:13:31.86#ibcon#read 5, iclass 19, count 0 2006.257.13:13:31.86#ibcon#about to read 6, iclass 19, count 0 2006.257.13:13:31.86#ibcon#read 6, iclass 19, count 0 2006.257.13:13:31.86#ibcon#end of sib2, iclass 19, count 0 2006.257.13:13:31.86#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:13:31.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:13:31.86#ibcon#[25=USB\r\n] 2006.257.13:13:31.86#ibcon#*before write, iclass 19, count 0 2006.257.13:13:31.86#ibcon#enter sib2, iclass 19, count 0 2006.257.13:13:31.86#ibcon#flushed, iclass 19, count 0 2006.257.13:13:31.86#ibcon#about to write, iclass 19, count 0 2006.257.13:13:31.86#ibcon#wrote, iclass 19, count 0 2006.257.13:13:31.86#ibcon#about to read 3, iclass 19, count 0 2006.257.13:13:31.89#ibcon#read 3, iclass 19, count 0 2006.257.13:13:31.89#ibcon#about to read 4, iclass 19, count 0 2006.257.13:13:31.89#ibcon#read 4, iclass 19, count 0 2006.257.13:13:31.89#ibcon#about to read 5, iclass 19, count 0 2006.257.13:13:31.89#ibcon#read 5, iclass 19, count 0 2006.257.13:13:31.89#ibcon#about to read 6, iclass 19, count 0 2006.257.13:13:31.89#ibcon#read 6, iclass 19, count 0 2006.257.13:13:31.89#ibcon#end of sib2, iclass 19, count 0 2006.257.13:13:31.89#ibcon#*after write, iclass 19, count 0 2006.257.13:13:31.89#ibcon#*before return 0, iclass 19, count 0 2006.257.13:13:31.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:13:31.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:13:31.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:13:31.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:13:31.89$vck44/vblo=1,629.99 2006.257.13:13:31.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.13:13:31.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.13:13:31.89#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:31.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:13:31.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:13:31.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:13:31.89#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:13:31.89#ibcon#first serial, iclass 21, count 0 2006.257.13:13:31.89#ibcon#enter sib2, iclass 21, count 0 2006.257.13:13:31.89#ibcon#flushed, iclass 21, count 0 2006.257.13:13:31.89#ibcon#about to write, iclass 21, count 0 2006.257.13:13:31.89#ibcon#wrote, iclass 21, count 0 2006.257.13:13:31.89#ibcon#about to read 3, iclass 21, count 0 2006.257.13:13:31.91#ibcon#read 3, iclass 21, count 0 2006.257.13:13:31.91#ibcon#about to read 4, iclass 21, count 0 2006.257.13:13:31.91#ibcon#read 4, iclass 21, count 0 2006.257.13:13:31.91#ibcon#about to read 5, iclass 21, count 0 2006.257.13:13:31.91#ibcon#read 5, iclass 21, count 0 2006.257.13:13:31.91#ibcon#about to read 6, iclass 21, count 0 2006.257.13:13:31.91#ibcon#read 6, iclass 21, count 0 2006.257.13:13:31.91#ibcon#end of sib2, iclass 21, count 0 2006.257.13:13:31.91#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:13:31.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:13:31.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:13:31.91#ibcon#*before write, iclass 21, count 0 2006.257.13:13:31.91#ibcon#enter sib2, iclass 21, count 0 2006.257.13:13:31.91#ibcon#flushed, iclass 21, count 0 2006.257.13:13:31.91#ibcon#about to write, iclass 21, count 0 2006.257.13:13:31.91#ibcon#wrote, iclass 21, count 0 2006.257.13:13:31.91#ibcon#about to read 3, iclass 21, count 0 2006.257.13:13:31.95#ibcon#read 3, iclass 21, count 0 2006.257.13:13:31.95#ibcon#about to read 4, iclass 21, count 0 2006.257.13:13:31.95#ibcon#read 4, iclass 21, count 0 2006.257.13:13:31.95#ibcon#about to read 5, iclass 21, count 0 2006.257.13:13:31.95#ibcon#read 5, iclass 21, count 0 2006.257.13:13:31.95#ibcon#about to read 6, iclass 21, count 0 2006.257.13:13:31.95#ibcon#read 6, iclass 21, count 0 2006.257.13:13:31.95#ibcon#end of sib2, iclass 21, count 0 2006.257.13:13:31.95#ibcon#*after write, iclass 21, count 0 2006.257.13:13:31.95#ibcon#*before return 0, iclass 21, count 0 2006.257.13:13:31.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:13:31.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:13:31.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:13:31.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:13:31.95$vck44/vb=1,4 2006.257.13:13:31.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.13:13:31.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.13:13:31.95#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:31.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:13:31.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:13:31.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:13:31.95#ibcon#enter wrdev, iclass 23, count 2 2006.257.13:13:31.95#ibcon#first serial, iclass 23, count 2 2006.257.13:13:31.95#ibcon#enter sib2, iclass 23, count 2 2006.257.13:13:31.95#ibcon#flushed, iclass 23, count 2 2006.257.13:13:31.95#ibcon#about to write, iclass 23, count 2 2006.257.13:13:31.95#ibcon#wrote, iclass 23, count 2 2006.257.13:13:31.95#ibcon#about to read 3, iclass 23, count 2 2006.257.13:13:31.97#ibcon#read 3, iclass 23, count 2 2006.257.13:13:31.97#ibcon#about to read 4, iclass 23, count 2 2006.257.13:13:31.97#ibcon#read 4, iclass 23, count 2 2006.257.13:13:31.97#ibcon#about to read 5, iclass 23, count 2 2006.257.13:13:31.97#ibcon#read 5, iclass 23, count 2 2006.257.13:13:31.97#ibcon#about to read 6, iclass 23, count 2 2006.257.13:13:31.97#ibcon#read 6, iclass 23, count 2 2006.257.13:13:31.97#ibcon#end of sib2, iclass 23, count 2 2006.257.13:13:31.97#ibcon#*mode == 0, iclass 23, count 2 2006.257.13:13:31.97#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.13:13:31.97#ibcon#[27=AT01-04\r\n] 2006.257.13:13:31.97#ibcon#*before write, iclass 23, count 2 2006.257.13:13:31.97#ibcon#enter sib2, iclass 23, count 2 2006.257.13:13:31.97#ibcon#flushed, iclass 23, count 2 2006.257.13:13:31.97#ibcon#about to write, iclass 23, count 2 2006.257.13:13:31.97#ibcon#wrote, iclass 23, count 2 2006.257.13:13:31.97#ibcon#about to read 3, iclass 23, count 2 2006.257.13:13:32.00#ibcon#read 3, iclass 23, count 2 2006.257.13:13:32.00#ibcon#about to read 4, iclass 23, count 2 2006.257.13:13:32.00#ibcon#read 4, iclass 23, count 2 2006.257.13:13:32.00#ibcon#about to read 5, iclass 23, count 2 2006.257.13:13:32.00#ibcon#read 5, iclass 23, count 2 2006.257.13:13:32.00#ibcon#about to read 6, iclass 23, count 2 2006.257.13:13:32.00#ibcon#read 6, iclass 23, count 2 2006.257.13:13:32.00#ibcon#end of sib2, iclass 23, count 2 2006.257.13:13:32.00#ibcon#*after write, iclass 23, count 2 2006.257.13:13:32.00#ibcon#*before return 0, iclass 23, count 2 2006.257.13:13:32.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:13:32.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:13:32.00#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.13:13:32.00#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:32.00#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:13:32.12#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:13:32.12#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:13:32.12#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:13:32.12#ibcon#first serial, iclass 23, count 0 2006.257.13:13:32.12#ibcon#enter sib2, iclass 23, count 0 2006.257.13:13:32.12#ibcon#flushed, iclass 23, count 0 2006.257.13:13:32.12#ibcon#about to write, iclass 23, count 0 2006.257.13:13:32.12#ibcon#wrote, iclass 23, count 0 2006.257.13:13:32.12#ibcon#about to read 3, iclass 23, count 0 2006.257.13:13:32.14#ibcon#read 3, iclass 23, count 0 2006.257.13:13:32.14#ibcon#about to read 4, iclass 23, count 0 2006.257.13:13:32.14#ibcon#read 4, iclass 23, count 0 2006.257.13:13:32.14#ibcon#about to read 5, iclass 23, count 0 2006.257.13:13:32.14#ibcon#read 5, iclass 23, count 0 2006.257.13:13:32.14#ibcon#about to read 6, iclass 23, count 0 2006.257.13:13:32.14#ibcon#read 6, iclass 23, count 0 2006.257.13:13:32.14#ibcon#end of sib2, iclass 23, count 0 2006.257.13:13:32.14#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:13:32.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:13:32.14#ibcon#[27=USB\r\n] 2006.257.13:13:32.14#ibcon#*before write, iclass 23, count 0 2006.257.13:13:32.14#ibcon#enter sib2, iclass 23, count 0 2006.257.13:13:32.14#ibcon#flushed, iclass 23, count 0 2006.257.13:13:32.14#ibcon#about to write, iclass 23, count 0 2006.257.13:13:32.14#ibcon#wrote, iclass 23, count 0 2006.257.13:13:32.14#ibcon#about to read 3, iclass 23, count 0 2006.257.13:13:32.17#ibcon#read 3, iclass 23, count 0 2006.257.13:13:32.17#ibcon#about to read 4, iclass 23, count 0 2006.257.13:13:32.17#ibcon#read 4, iclass 23, count 0 2006.257.13:13:32.17#ibcon#about to read 5, iclass 23, count 0 2006.257.13:13:32.17#ibcon#read 5, iclass 23, count 0 2006.257.13:13:32.17#ibcon#about to read 6, iclass 23, count 0 2006.257.13:13:32.17#ibcon#read 6, iclass 23, count 0 2006.257.13:13:32.17#ibcon#end of sib2, iclass 23, count 0 2006.257.13:13:32.17#ibcon#*after write, iclass 23, count 0 2006.257.13:13:32.17#ibcon#*before return 0, iclass 23, count 0 2006.257.13:13:32.17#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:13:32.17#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:13:32.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:13:32.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:13:32.17$vck44/vblo=2,634.99 2006.257.13:13:32.17#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.13:13:32.17#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.13:13:32.17#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:32.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:32.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:32.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:32.17#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:13:32.17#ibcon#first serial, iclass 25, count 0 2006.257.13:13:32.17#ibcon#enter sib2, iclass 25, count 0 2006.257.13:13:32.17#ibcon#flushed, iclass 25, count 0 2006.257.13:13:32.17#ibcon#about to write, iclass 25, count 0 2006.257.13:13:32.17#ibcon#wrote, iclass 25, count 0 2006.257.13:13:32.17#ibcon#about to read 3, iclass 25, count 0 2006.257.13:13:32.19#ibcon#read 3, iclass 25, count 0 2006.257.13:13:32.19#ibcon#about to read 4, iclass 25, count 0 2006.257.13:13:32.19#ibcon#read 4, iclass 25, count 0 2006.257.13:13:32.19#ibcon#about to read 5, iclass 25, count 0 2006.257.13:13:32.19#ibcon#read 5, iclass 25, count 0 2006.257.13:13:32.19#ibcon#about to read 6, iclass 25, count 0 2006.257.13:13:32.19#ibcon#read 6, iclass 25, count 0 2006.257.13:13:32.19#ibcon#end of sib2, iclass 25, count 0 2006.257.13:13:32.19#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:13:32.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:13:32.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:13:32.19#ibcon#*before write, iclass 25, count 0 2006.257.13:13:32.19#ibcon#enter sib2, iclass 25, count 0 2006.257.13:13:32.19#ibcon#flushed, iclass 25, count 0 2006.257.13:13:32.19#ibcon#about to write, iclass 25, count 0 2006.257.13:13:32.19#ibcon#wrote, iclass 25, count 0 2006.257.13:13:32.19#ibcon#about to read 3, iclass 25, count 0 2006.257.13:13:32.23#ibcon#read 3, iclass 25, count 0 2006.257.13:13:32.23#ibcon#about to read 4, iclass 25, count 0 2006.257.13:13:32.23#ibcon#read 4, iclass 25, count 0 2006.257.13:13:32.23#ibcon#about to read 5, iclass 25, count 0 2006.257.13:13:32.23#ibcon#read 5, iclass 25, count 0 2006.257.13:13:32.23#ibcon#about to read 6, iclass 25, count 0 2006.257.13:13:32.23#ibcon#read 6, iclass 25, count 0 2006.257.13:13:32.23#ibcon#end of sib2, iclass 25, count 0 2006.257.13:13:32.23#ibcon#*after write, iclass 25, count 0 2006.257.13:13:32.23#ibcon#*before return 0, iclass 25, count 0 2006.257.13:13:32.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:32.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:13:32.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:13:32.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:13:32.23$vck44/vb=2,5 2006.257.13:13:32.23#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.13:13:32.23#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.13:13:32.23#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:32.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:32.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:32.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:32.29#ibcon#enter wrdev, iclass 27, count 2 2006.257.13:13:32.29#ibcon#first serial, iclass 27, count 2 2006.257.13:13:32.29#ibcon#enter sib2, iclass 27, count 2 2006.257.13:13:32.29#ibcon#flushed, iclass 27, count 2 2006.257.13:13:32.29#ibcon#about to write, iclass 27, count 2 2006.257.13:13:32.29#ibcon#wrote, iclass 27, count 2 2006.257.13:13:32.29#ibcon#about to read 3, iclass 27, count 2 2006.257.13:13:32.31#ibcon#read 3, iclass 27, count 2 2006.257.13:13:32.31#ibcon#about to read 4, iclass 27, count 2 2006.257.13:13:32.31#ibcon#read 4, iclass 27, count 2 2006.257.13:13:32.31#ibcon#about to read 5, iclass 27, count 2 2006.257.13:13:32.31#ibcon#read 5, iclass 27, count 2 2006.257.13:13:32.31#ibcon#about to read 6, iclass 27, count 2 2006.257.13:13:32.31#ibcon#read 6, iclass 27, count 2 2006.257.13:13:32.31#ibcon#end of sib2, iclass 27, count 2 2006.257.13:13:32.31#ibcon#*mode == 0, iclass 27, count 2 2006.257.13:13:32.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.13:13:32.31#ibcon#[27=AT02-05\r\n] 2006.257.13:13:32.31#ibcon#*before write, iclass 27, count 2 2006.257.13:13:32.31#ibcon#enter sib2, iclass 27, count 2 2006.257.13:13:32.31#ibcon#flushed, iclass 27, count 2 2006.257.13:13:32.31#ibcon#about to write, iclass 27, count 2 2006.257.13:13:32.31#ibcon#wrote, iclass 27, count 2 2006.257.13:13:32.31#ibcon#about to read 3, iclass 27, count 2 2006.257.13:13:32.34#ibcon#read 3, iclass 27, count 2 2006.257.13:13:32.34#ibcon#about to read 4, iclass 27, count 2 2006.257.13:13:32.34#ibcon#read 4, iclass 27, count 2 2006.257.13:13:32.34#ibcon#about to read 5, iclass 27, count 2 2006.257.13:13:32.34#ibcon#read 5, iclass 27, count 2 2006.257.13:13:32.34#ibcon#about to read 6, iclass 27, count 2 2006.257.13:13:32.34#ibcon#read 6, iclass 27, count 2 2006.257.13:13:32.34#ibcon#end of sib2, iclass 27, count 2 2006.257.13:13:32.34#ibcon#*after write, iclass 27, count 2 2006.257.13:13:32.34#ibcon#*before return 0, iclass 27, count 2 2006.257.13:13:32.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:32.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:13:32.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.13:13:32.34#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:32.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:32.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:32.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:32.46#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:13:32.46#ibcon#first serial, iclass 27, count 0 2006.257.13:13:32.46#ibcon#enter sib2, iclass 27, count 0 2006.257.13:13:32.46#ibcon#flushed, iclass 27, count 0 2006.257.13:13:32.46#ibcon#about to write, iclass 27, count 0 2006.257.13:13:32.46#ibcon#wrote, iclass 27, count 0 2006.257.13:13:32.46#ibcon#about to read 3, iclass 27, count 0 2006.257.13:13:32.48#ibcon#read 3, iclass 27, count 0 2006.257.13:13:32.48#ibcon#about to read 4, iclass 27, count 0 2006.257.13:13:32.48#ibcon#read 4, iclass 27, count 0 2006.257.13:13:32.48#ibcon#about to read 5, iclass 27, count 0 2006.257.13:13:32.48#ibcon#read 5, iclass 27, count 0 2006.257.13:13:32.48#ibcon#about to read 6, iclass 27, count 0 2006.257.13:13:32.48#ibcon#read 6, iclass 27, count 0 2006.257.13:13:32.48#ibcon#end of sib2, iclass 27, count 0 2006.257.13:13:32.48#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:13:32.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:13:32.48#ibcon#[27=USB\r\n] 2006.257.13:13:32.48#ibcon#*before write, iclass 27, count 0 2006.257.13:13:32.48#ibcon#enter sib2, iclass 27, count 0 2006.257.13:13:32.48#ibcon#flushed, iclass 27, count 0 2006.257.13:13:32.48#ibcon#about to write, iclass 27, count 0 2006.257.13:13:32.48#ibcon#wrote, iclass 27, count 0 2006.257.13:13:32.48#ibcon#about to read 3, iclass 27, count 0 2006.257.13:13:32.51#ibcon#read 3, iclass 27, count 0 2006.257.13:13:32.51#ibcon#about to read 4, iclass 27, count 0 2006.257.13:13:32.51#ibcon#read 4, iclass 27, count 0 2006.257.13:13:32.51#ibcon#about to read 5, iclass 27, count 0 2006.257.13:13:32.51#ibcon#read 5, iclass 27, count 0 2006.257.13:13:32.51#ibcon#about to read 6, iclass 27, count 0 2006.257.13:13:32.51#ibcon#read 6, iclass 27, count 0 2006.257.13:13:32.51#ibcon#end of sib2, iclass 27, count 0 2006.257.13:13:32.51#ibcon#*after write, iclass 27, count 0 2006.257.13:13:32.51#ibcon#*before return 0, iclass 27, count 0 2006.257.13:13:32.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:32.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:13:32.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:13:32.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:13:32.51$vck44/vblo=3,649.99 2006.257.13:13:32.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.13:13:32.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.13:13:32.51#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:32.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:32.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:32.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:32.51#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:13:32.51#ibcon#first serial, iclass 29, count 0 2006.257.13:13:32.51#ibcon#enter sib2, iclass 29, count 0 2006.257.13:13:32.51#ibcon#flushed, iclass 29, count 0 2006.257.13:13:32.51#ibcon#about to write, iclass 29, count 0 2006.257.13:13:32.51#ibcon#wrote, iclass 29, count 0 2006.257.13:13:32.51#ibcon#about to read 3, iclass 29, count 0 2006.257.13:13:32.53#ibcon#read 3, iclass 29, count 0 2006.257.13:13:32.53#ibcon#about to read 4, iclass 29, count 0 2006.257.13:13:32.53#ibcon#read 4, iclass 29, count 0 2006.257.13:13:32.53#ibcon#about to read 5, iclass 29, count 0 2006.257.13:13:32.53#ibcon#read 5, iclass 29, count 0 2006.257.13:13:32.53#ibcon#about to read 6, iclass 29, count 0 2006.257.13:13:32.53#ibcon#read 6, iclass 29, count 0 2006.257.13:13:32.53#ibcon#end of sib2, iclass 29, count 0 2006.257.13:13:32.53#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:13:32.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:13:32.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:13:32.53#ibcon#*before write, iclass 29, count 0 2006.257.13:13:32.53#ibcon#enter sib2, iclass 29, count 0 2006.257.13:13:32.53#ibcon#flushed, iclass 29, count 0 2006.257.13:13:32.53#ibcon#about to write, iclass 29, count 0 2006.257.13:13:32.53#ibcon#wrote, iclass 29, count 0 2006.257.13:13:32.53#ibcon#about to read 3, iclass 29, count 0 2006.257.13:13:32.57#ibcon#read 3, iclass 29, count 0 2006.257.13:13:32.57#ibcon#about to read 4, iclass 29, count 0 2006.257.13:13:32.57#ibcon#read 4, iclass 29, count 0 2006.257.13:13:32.57#ibcon#about to read 5, iclass 29, count 0 2006.257.13:13:32.57#ibcon#read 5, iclass 29, count 0 2006.257.13:13:32.57#ibcon#about to read 6, iclass 29, count 0 2006.257.13:13:32.57#ibcon#read 6, iclass 29, count 0 2006.257.13:13:32.57#ibcon#end of sib2, iclass 29, count 0 2006.257.13:13:32.57#ibcon#*after write, iclass 29, count 0 2006.257.13:13:32.57#ibcon#*before return 0, iclass 29, count 0 2006.257.13:13:32.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:32.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:13:32.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:13:32.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:13:32.57$vck44/vb=3,4 2006.257.13:13:32.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.13:13:32.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.13:13:32.57#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:32.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:32.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:32.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:32.63#ibcon#enter wrdev, iclass 31, count 2 2006.257.13:13:32.63#ibcon#first serial, iclass 31, count 2 2006.257.13:13:32.63#ibcon#enter sib2, iclass 31, count 2 2006.257.13:13:32.63#ibcon#flushed, iclass 31, count 2 2006.257.13:13:32.63#ibcon#about to write, iclass 31, count 2 2006.257.13:13:32.63#ibcon#wrote, iclass 31, count 2 2006.257.13:13:32.63#ibcon#about to read 3, iclass 31, count 2 2006.257.13:13:32.65#ibcon#read 3, iclass 31, count 2 2006.257.13:13:32.65#ibcon#about to read 4, iclass 31, count 2 2006.257.13:13:32.65#ibcon#read 4, iclass 31, count 2 2006.257.13:13:32.65#ibcon#about to read 5, iclass 31, count 2 2006.257.13:13:32.65#ibcon#read 5, iclass 31, count 2 2006.257.13:13:32.65#ibcon#about to read 6, iclass 31, count 2 2006.257.13:13:32.65#ibcon#read 6, iclass 31, count 2 2006.257.13:13:32.65#ibcon#end of sib2, iclass 31, count 2 2006.257.13:13:32.65#ibcon#*mode == 0, iclass 31, count 2 2006.257.13:13:32.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.13:13:32.65#ibcon#[27=AT03-04\r\n] 2006.257.13:13:32.65#ibcon#*before write, iclass 31, count 2 2006.257.13:13:32.65#ibcon#enter sib2, iclass 31, count 2 2006.257.13:13:32.65#ibcon#flushed, iclass 31, count 2 2006.257.13:13:32.65#ibcon#about to write, iclass 31, count 2 2006.257.13:13:32.65#ibcon#wrote, iclass 31, count 2 2006.257.13:13:32.65#ibcon#about to read 3, iclass 31, count 2 2006.257.13:13:32.68#ibcon#read 3, iclass 31, count 2 2006.257.13:13:32.68#ibcon#about to read 4, iclass 31, count 2 2006.257.13:13:32.68#ibcon#read 4, iclass 31, count 2 2006.257.13:13:32.68#ibcon#about to read 5, iclass 31, count 2 2006.257.13:13:32.68#ibcon#read 5, iclass 31, count 2 2006.257.13:13:32.68#ibcon#about to read 6, iclass 31, count 2 2006.257.13:13:32.68#ibcon#read 6, iclass 31, count 2 2006.257.13:13:32.68#ibcon#end of sib2, iclass 31, count 2 2006.257.13:13:32.68#ibcon#*after write, iclass 31, count 2 2006.257.13:13:32.68#ibcon#*before return 0, iclass 31, count 2 2006.257.13:13:32.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:32.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:13:32.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.13:13:32.68#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:32.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:32.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:32.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:32.80#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:13:32.80#ibcon#first serial, iclass 31, count 0 2006.257.13:13:32.80#ibcon#enter sib2, iclass 31, count 0 2006.257.13:13:32.80#ibcon#flushed, iclass 31, count 0 2006.257.13:13:32.80#ibcon#about to write, iclass 31, count 0 2006.257.13:13:32.80#ibcon#wrote, iclass 31, count 0 2006.257.13:13:32.80#ibcon#about to read 3, iclass 31, count 0 2006.257.13:13:32.82#ibcon#read 3, iclass 31, count 0 2006.257.13:13:32.82#ibcon#about to read 4, iclass 31, count 0 2006.257.13:13:32.82#ibcon#read 4, iclass 31, count 0 2006.257.13:13:32.82#ibcon#about to read 5, iclass 31, count 0 2006.257.13:13:32.82#ibcon#read 5, iclass 31, count 0 2006.257.13:13:32.82#ibcon#about to read 6, iclass 31, count 0 2006.257.13:13:32.82#ibcon#read 6, iclass 31, count 0 2006.257.13:13:32.82#ibcon#end of sib2, iclass 31, count 0 2006.257.13:13:32.82#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:13:32.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:13:32.82#ibcon#[27=USB\r\n] 2006.257.13:13:32.82#ibcon#*before write, iclass 31, count 0 2006.257.13:13:32.82#ibcon#enter sib2, iclass 31, count 0 2006.257.13:13:32.82#ibcon#flushed, iclass 31, count 0 2006.257.13:13:32.82#ibcon#about to write, iclass 31, count 0 2006.257.13:13:32.82#ibcon#wrote, iclass 31, count 0 2006.257.13:13:32.82#ibcon#about to read 3, iclass 31, count 0 2006.257.13:13:32.85#ibcon#read 3, iclass 31, count 0 2006.257.13:13:32.85#ibcon#about to read 4, iclass 31, count 0 2006.257.13:13:32.85#ibcon#read 4, iclass 31, count 0 2006.257.13:13:32.85#ibcon#about to read 5, iclass 31, count 0 2006.257.13:13:32.85#ibcon#read 5, iclass 31, count 0 2006.257.13:13:32.85#ibcon#about to read 6, iclass 31, count 0 2006.257.13:13:32.85#ibcon#read 6, iclass 31, count 0 2006.257.13:13:32.85#ibcon#end of sib2, iclass 31, count 0 2006.257.13:13:32.85#ibcon#*after write, iclass 31, count 0 2006.257.13:13:32.85#ibcon#*before return 0, iclass 31, count 0 2006.257.13:13:32.85#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:32.85#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:13:32.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:13:32.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:13:32.85$vck44/vblo=4,679.99 2006.257.13:13:32.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.13:13:32.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.13:13:32.85#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:32.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:32.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:32.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:32.85#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:13:32.85#ibcon#first serial, iclass 33, count 0 2006.257.13:13:32.85#ibcon#enter sib2, iclass 33, count 0 2006.257.13:13:32.85#ibcon#flushed, iclass 33, count 0 2006.257.13:13:32.85#ibcon#about to write, iclass 33, count 0 2006.257.13:13:32.85#ibcon#wrote, iclass 33, count 0 2006.257.13:13:32.85#ibcon#about to read 3, iclass 33, count 0 2006.257.13:13:32.87#ibcon#read 3, iclass 33, count 0 2006.257.13:13:32.87#ibcon#about to read 4, iclass 33, count 0 2006.257.13:13:32.87#ibcon#read 4, iclass 33, count 0 2006.257.13:13:32.87#ibcon#about to read 5, iclass 33, count 0 2006.257.13:13:32.87#ibcon#read 5, iclass 33, count 0 2006.257.13:13:32.87#ibcon#about to read 6, iclass 33, count 0 2006.257.13:13:32.87#ibcon#read 6, iclass 33, count 0 2006.257.13:13:32.87#ibcon#end of sib2, iclass 33, count 0 2006.257.13:13:32.87#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:13:32.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:13:32.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:13:32.87#ibcon#*before write, iclass 33, count 0 2006.257.13:13:32.87#ibcon#enter sib2, iclass 33, count 0 2006.257.13:13:32.87#ibcon#flushed, iclass 33, count 0 2006.257.13:13:32.87#ibcon#about to write, iclass 33, count 0 2006.257.13:13:32.87#ibcon#wrote, iclass 33, count 0 2006.257.13:13:32.87#ibcon#about to read 3, iclass 33, count 0 2006.257.13:13:32.91#ibcon#read 3, iclass 33, count 0 2006.257.13:13:32.91#ibcon#about to read 4, iclass 33, count 0 2006.257.13:13:32.91#ibcon#read 4, iclass 33, count 0 2006.257.13:13:32.91#ibcon#about to read 5, iclass 33, count 0 2006.257.13:13:32.91#ibcon#read 5, iclass 33, count 0 2006.257.13:13:32.91#ibcon#about to read 6, iclass 33, count 0 2006.257.13:13:32.91#ibcon#read 6, iclass 33, count 0 2006.257.13:13:32.91#ibcon#end of sib2, iclass 33, count 0 2006.257.13:13:32.91#ibcon#*after write, iclass 33, count 0 2006.257.13:13:32.91#ibcon#*before return 0, iclass 33, count 0 2006.257.13:13:32.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:32.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:13:32.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:13:32.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:13:32.91$vck44/vb=4,5 2006.257.13:13:32.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.13:13:32.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.13:13:32.91#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:32.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:32.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:32.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:32.97#ibcon#enter wrdev, iclass 35, count 2 2006.257.13:13:32.97#ibcon#first serial, iclass 35, count 2 2006.257.13:13:32.97#ibcon#enter sib2, iclass 35, count 2 2006.257.13:13:32.97#ibcon#flushed, iclass 35, count 2 2006.257.13:13:32.97#ibcon#about to write, iclass 35, count 2 2006.257.13:13:32.97#ibcon#wrote, iclass 35, count 2 2006.257.13:13:32.97#ibcon#about to read 3, iclass 35, count 2 2006.257.13:13:32.99#ibcon#read 3, iclass 35, count 2 2006.257.13:13:32.99#ibcon#about to read 4, iclass 35, count 2 2006.257.13:13:32.99#ibcon#read 4, iclass 35, count 2 2006.257.13:13:32.99#ibcon#about to read 5, iclass 35, count 2 2006.257.13:13:32.99#ibcon#read 5, iclass 35, count 2 2006.257.13:13:32.99#ibcon#about to read 6, iclass 35, count 2 2006.257.13:13:32.99#ibcon#read 6, iclass 35, count 2 2006.257.13:13:32.99#ibcon#end of sib2, iclass 35, count 2 2006.257.13:13:32.99#ibcon#*mode == 0, iclass 35, count 2 2006.257.13:13:32.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.13:13:32.99#ibcon#[27=AT04-05\r\n] 2006.257.13:13:32.99#ibcon#*before write, iclass 35, count 2 2006.257.13:13:32.99#ibcon#enter sib2, iclass 35, count 2 2006.257.13:13:32.99#ibcon#flushed, iclass 35, count 2 2006.257.13:13:32.99#ibcon#about to write, iclass 35, count 2 2006.257.13:13:32.99#ibcon#wrote, iclass 35, count 2 2006.257.13:13:32.99#ibcon#about to read 3, iclass 35, count 2 2006.257.13:13:33.02#ibcon#read 3, iclass 35, count 2 2006.257.13:13:33.02#ibcon#about to read 4, iclass 35, count 2 2006.257.13:13:33.02#ibcon#read 4, iclass 35, count 2 2006.257.13:13:33.02#ibcon#about to read 5, iclass 35, count 2 2006.257.13:13:33.02#ibcon#read 5, iclass 35, count 2 2006.257.13:13:33.02#ibcon#about to read 6, iclass 35, count 2 2006.257.13:13:33.02#ibcon#read 6, iclass 35, count 2 2006.257.13:13:33.02#ibcon#end of sib2, iclass 35, count 2 2006.257.13:13:33.02#ibcon#*after write, iclass 35, count 2 2006.257.13:13:33.02#ibcon#*before return 0, iclass 35, count 2 2006.257.13:13:33.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:33.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:13:33.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.13:13:33.02#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:33.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:33.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:33.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:33.14#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:13:33.14#ibcon#first serial, iclass 35, count 0 2006.257.13:13:33.14#ibcon#enter sib2, iclass 35, count 0 2006.257.13:13:33.14#ibcon#flushed, iclass 35, count 0 2006.257.13:13:33.14#ibcon#about to write, iclass 35, count 0 2006.257.13:13:33.14#ibcon#wrote, iclass 35, count 0 2006.257.13:13:33.14#ibcon#about to read 3, iclass 35, count 0 2006.257.13:13:33.16#ibcon#read 3, iclass 35, count 0 2006.257.13:13:33.16#ibcon#about to read 4, iclass 35, count 0 2006.257.13:13:33.16#ibcon#read 4, iclass 35, count 0 2006.257.13:13:33.16#ibcon#about to read 5, iclass 35, count 0 2006.257.13:13:33.16#ibcon#read 5, iclass 35, count 0 2006.257.13:13:33.16#ibcon#about to read 6, iclass 35, count 0 2006.257.13:13:33.16#ibcon#read 6, iclass 35, count 0 2006.257.13:13:33.16#ibcon#end of sib2, iclass 35, count 0 2006.257.13:13:33.16#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:13:33.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:13:33.16#ibcon#[27=USB\r\n] 2006.257.13:13:33.16#ibcon#*before write, iclass 35, count 0 2006.257.13:13:33.16#ibcon#enter sib2, iclass 35, count 0 2006.257.13:13:33.16#ibcon#flushed, iclass 35, count 0 2006.257.13:13:33.16#ibcon#about to write, iclass 35, count 0 2006.257.13:13:33.16#ibcon#wrote, iclass 35, count 0 2006.257.13:13:33.16#ibcon#about to read 3, iclass 35, count 0 2006.257.13:13:33.19#ibcon#read 3, iclass 35, count 0 2006.257.13:13:33.19#ibcon#about to read 4, iclass 35, count 0 2006.257.13:13:33.19#ibcon#read 4, iclass 35, count 0 2006.257.13:13:33.19#ibcon#about to read 5, iclass 35, count 0 2006.257.13:13:33.19#ibcon#read 5, iclass 35, count 0 2006.257.13:13:33.19#ibcon#about to read 6, iclass 35, count 0 2006.257.13:13:33.19#ibcon#read 6, iclass 35, count 0 2006.257.13:13:33.19#ibcon#end of sib2, iclass 35, count 0 2006.257.13:13:33.19#ibcon#*after write, iclass 35, count 0 2006.257.13:13:33.19#ibcon#*before return 0, iclass 35, count 0 2006.257.13:13:33.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:33.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:13:33.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:13:33.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:13:33.19$vck44/vblo=5,709.99 2006.257.13:13:33.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.13:13:33.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.13:13:33.19#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:33.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:33.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:33.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:33.19#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:13:33.19#ibcon#first serial, iclass 37, count 0 2006.257.13:13:33.19#ibcon#enter sib2, iclass 37, count 0 2006.257.13:13:33.19#ibcon#flushed, iclass 37, count 0 2006.257.13:13:33.19#ibcon#about to write, iclass 37, count 0 2006.257.13:13:33.19#ibcon#wrote, iclass 37, count 0 2006.257.13:13:33.19#ibcon#about to read 3, iclass 37, count 0 2006.257.13:13:33.21#ibcon#read 3, iclass 37, count 0 2006.257.13:13:33.21#ibcon#about to read 4, iclass 37, count 0 2006.257.13:13:33.21#ibcon#read 4, iclass 37, count 0 2006.257.13:13:33.21#ibcon#about to read 5, iclass 37, count 0 2006.257.13:13:33.21#ibcon#read 5, iclass 37, count 0 2006.257.13:13:33.21#ibcon#about to read 6, iclass 37, count 0 2006.257.13:13:33.21#ibcon#read 6, iclass 37, count 0 2006.257.13:13:33.21#ibcon#end of sib2, iclass 37, count 0 2006.257.13:13:33.21#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:13:33.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:13:33.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:13:33.21#ibcon#*before write, iclass 37, count 0 2006.257.13:13:33.21#ibcon#enter sib2, iclass 37, count 0 2006.257.13:13:33.21#ibcon#flushed, iclass 37, count 0 2006.257.13:13:33.21#ibcon#about to write, iclass 37, count 0 2006.257.13:13:33.21#ibcon#wrote, iclass 37, count 0 2006.257.13:13:33.21#ibcon#about to read 3, iclass 37, count 0 2006.257.13:13:33.25#ibcon#read 3, iclass 37, count 0 2006.257.13:13:33.25#ibcon#about to read 4, iclass 37, count 0 2006.257.13:13:33.25#ibcon#read 4, iclass 37, count 0 2006.257.13:13:33.25#ibcon#about to read 5, iclass 37, count 0 2006.257.13:13:33.25#ibcon#read 5, iclass 37, count 0 2006.257.13:13:33.25#ibcon#about to read 6, iclass 37, count 0 2006.257.13:13:33.25#ibcon#read 6, iclass 37, count 0 2006.257.13:13:33.25#ibcon#end of sib2, iclass 37, count 0 2006.257.13:13:33.25#ibcon#*after write, iclass 37, count 0 2006.257.13:13:33.25#ibcon#*before return 0, iclass 37, count 0 2006.257.13:13:33.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:33.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:13:33.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:13:33.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:13:33.25$vck44/vb=5,4 2006.257.13:13:33.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.13:13:33.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.13:13:33.25#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:33.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:33.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:33.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:33.31#ibcon#enter wrdev, iclass 39, count 2 2006.257.13:13:33.31#ibcon#first serial, iclass 39, count 2 2006.257.13:13:33.31#ibcon#enter sib2, iclass 39, count 2 2006.257.13:13:33.31#ibcon#flushed, iclass 39, count 2 2006.257.13:13:33.31#ibcon#about to write, iclass 39, count 2 2006.257.13:13:33.31#ibcon#wrote, iclass 39, count 2 2006.257.13:13:33.31#ibcon#about to read 3, iclass 39, count 2 2006.257.13:13:33.33#ibcon#read 3, iclass 39, count 2 2006.257.13:13:33.33#ibcon#about to read 4, iclass 39, count 2 2006.257.13:13:33.33#ibcon#read 4, iclass 39, count 2 2006.257.13:13:33.33#ibcon#about to read 5, iclass 39, count 2 2006.257.13:13:33.33#ibcon#read 5, iclass 39, count 2 2006.257.13:13:33.33#ibcon#about to read 6, iclass 39, count 2 2006.257.13:13:33.33#ibcon#read 6, iclass 39, count 2 2006.257.13:13:33.33#ibcon#end of sib2, iclass 39, count 2 2006.257.13:13:33.33#ibcon#*mode == 0, iclass 39, count 2 2006.257.13:13:33.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.13:13:33.33#ibcon#[27=AT05-04\r\n] 2006.257.13:13:33.33#ibcon#*before write, iclass 39, count 2 2006.257.13:13:33.33#ibcon#enter sib2, iclass 39, count 2 2006.257.13:13:33.33#ibcon#flushed, iclass 39, count 2 2006.257.13:13:33.33#ibcon#about to write, iclass 39, count 2 2006.257.13:13:33.33#ibcon#wrote, iclass 39, count 2 2006.257.13:13:33.33#ibcon#about to read 3, iclass 39, count 2 2006.257.13:13:33.36#ibcon#read 3, iclass 39, count 2 2006.257.13:13:33.36#ibcon#about to read 4, iclass 39, count 2 2006.257.13:13:33.36#ibcon#read 4, iclass 39, count 2 2006.257.13:13:33.36#ibcon#about to read 5, iclass 39, count 2 2006.257.13:13:33.36#ibcon#read 5, iclass 39, count 2 2006.257.13:13:33.36#ibcon#about to read 6, iclass 39, count 2 2006.257.13:13:33.36#ibcon#read 6, iclass 39, count 2 2006.257.13:13:33.36#ibcon#end of sib2, iclass 39, count 2 2006.257.13:13:33.36#ibcon#*after write, iclass 39, count 2 2006.257.13:13:33.36#ibcon#*before return 0, iclass 39, count 2 2006.257.13:13:33.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:33.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:13:33.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.13:13:33.36#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:33.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:33.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:33.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:33.48#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:13:33.48#ibcon#first serial, iclass 39, count 0 2006.257.13:13:33.48#ibcon#enter sib2, iclass 39, count 0 2006.257.13:13:33.48#ibcon#flushed, iclass 39, count 0 2006.257.13:13:33.48#ibcon#about to write, iclass 39, count 0 2006.257.13:13:33.48#ibcon#wrote, iclass 39, count 0 2006.257.13:13:33.48#ibcon#about to read 3, iclass 39, count 0 2006.257.13:13:33.50#ibcon#read 3, iclass 39, count 0 2006.257.13:13:33.50#ibcon#about to read 4, iclass 39, count 0 2006.257.13:13:33.50#ibcon#read 4, iclass 39, count 0 2006.257.13:13:33.50#ibcon#about to read 5, iclass 39, count 0 2006.257.13:13:33.50#ibcon#read 5, iclass 39, count 0 2006.257.13:13:33.50#ibcon#about to read 6, iclass 39, count 0 2006.257.13:13:33.50#ibcon#read 6, iclass 39, count 0 2006.257.13:13:33.50#ibcon#end of sib2, iclass 39, count 0 2006.257.13:13:33.50#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:13:33.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:13:33.50#ibcon#[27=USB\r\n] 2006.257.13:13:33.50#ibcon#*before write, iclass 39, count 0 2006.257.13:13:33.50#ibcon#enter sib2, iclass 39, count 0 2006.257.13:13:33.50#ibcon#flushed, iclass 39, count 0 2006.257.13:13:33.50#ibcon#about to write, iclass 39, count 0 2006.257.13:13:33.50#ibcon#wrote, iclass 39, count 0 2006.257.13:13:33.50#ibcon#about to read 3, iclass 39, count 0 2006.257.13:13:33.53#ibcon#read 3, iclass 39, count 0 2006.257.13:13:33.53#ibcon#about to read 4, iclass 39, count 0 2006.257.13:13:33.53#ibcon#read 4, iclass 39, count 0 2006.257.13:13:33.53#ibcon#about to read 5, iclass 39, count 0 2006.257.13:13:33.53#ibcon#read 5, iclass 39, count 0 2006.257.13:13:33.53#ibcon#about to read 6, iclass 39, count 0 2006.257.13:13:33.53#ibcon#read 6, iclass 39, count 0 2006.257.13:13:33.53#ibcon#end of sib2, iclass 39, count 0 2006.257.13:13:33.53#ibcon#*after write, iclass 39, count 0 2006.257.13:13:33.53#ibcon#*before return 0, iclass 39, count 0 2006.257.13:13:33.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:33.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:13:33.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:13:33.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:13:33.53$vck44/vblo=6,719.99 2006.257.13:13:33.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.13:13:33.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.13:13:33.53#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:33.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:33.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:33.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:33.53#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:13:33.53#ibcon#first serial, iclass 3, count 0 2006.257.13:13:33.53#ibcon#enter sib2, iclass 3, count 0 2006.257.13:13:33.53#ibcon#flushed, iclass 3, count 0 2006.257.13:13:33.53#ibcon#about to write, iclass 3, count 0 2006.257.13:13:33.53#ibcon#wrote, iclass 3, count 0 2006.257.13:13:33.53#ibcon#about to read 3, iclass 3, count 0 2006.257.13:13:33.55#ibcon#read 3, iclass 3, count 0 2006.257.13:13:33.55#ibcon#about to read 4, iclass 3, count 0 2006.257.13:13:33.55#ibcon#read 4, iclass 3, count 0 2006.257.13:13:33.55#ibcon#about to read 5, iclass 3, count 0 2006.257.13:13:33.55#ibcon#read 5, iclass 3, count 0 2006.257.13:13:33.55#ibcon#about to read 6, iclass 3, count 0 2006.257.13:13:33.55#ibcon#read 6, iclass 3, count 0 2006.257.13:13:33.55#ibcon#end of sib2, iclass 3, count 0 2006.257.13:13:33.55#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:13:33.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:13:33.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:13:33.55#ibcon#*before write, iclass 3, count 0 2006.257.13:13:33.55#ibcon#enter sib2, iclass 3, count 0 2006.257.13:13:33.55#ibcon#flushed, iclass 3, count 0 2006.257.13:13:33.55#ibcon#about to write, iclass 3, count 0 2006.257.13:13:33.55#ibcon#wrote, iclass 3, count 0 2006.257.13:13:33.55#ibcon#about to read 3, iclass 3, count 0 2006.257.13:13:33.59#ibcon#read 3, iclass 3, count 0 2006.257.13:13:33.59#ibcon#about to read 4, iclass 3, count 0 2006.257.13:13:33.59#ibcon#read 4, iclass 3, count 0 2006.257.13:13:33.59#ibcon#about to read 5, iclass 3, count 0 2006.257.13:13:33.59#ibcon#read 5, iclass 3, count 0 2006.257.13:13:33.59#ibcon#about to read 6, iclass 3, count 0 2006.257.13:13:33.59#ibcon#read 6, iclass 3, count 0 2006.257.13:13:33.59#ibcon#end of sib2, iclass 3, count 0 2006.257.13:13:33.59#ibcon#*after write, iclass 3, count 0 2006.257.13:13:33.59#ibcon#*before return 0, iclass 3, count 0 2006.257.13:13:33.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:33.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:13:33.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:13:33.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:13:33.59$vck44/vb=6,4 2006.257.13:13:33.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.13:13:33.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.13:13:33.59#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:33.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:33.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:33.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:33.65#ibcon#enter wrdev, iclass 5, count 2 2006.257.13:13:33.65#ibcon#first serial, iclass 5, count 2 2006.257.13:13:33.65#ibcon#enter sib2, iclass 5, count 2 2006.257.13:13:33.65#ibcon#flushed, iclass 5, count 2 2006.257.13:13:33.65#ibcon#about to write, iclass 5, count 2 2006.257.13:13:33.65#ibcon#wrote, iclass 5, count 2 2006.257.13:13:33.65#ibcon#about to read 3, iclass 5, count 2 2006.257.13:13:33.67#ibcon#read 3, iclass 5, count 2 2006.257.13:13:33.67#ibcon#about to read 4, iclass 5, count 2 2006.257.13:13:33.67#ibcon#read 4, iclass 5, count 2 2006.257.13:13:33.67#ibcon#about to read 5, iclass 5, count 2 2006.257.13:13:33.67#ibcon#read 5, iclass 5, count 2 2006.257.13:13:33.67#ibcon#about to read 6, iclass 5, count 2 2006.257.13:13:33.67#ibcon#read 6, iclass 5, count 2 2006.257.13:13:33.67#ibcon#end of sib2, iclass 5, count 2 2006.257.13:13:33.67#ibcon#*mode == 0, iclass 5, count 2 2006.257.13:13:33.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.13:13:33.67#ibcon#[27=AT06-04\r\n] 2006.257.13:13:33.67#ibcon#*before write, iclass 5, count 2 2006.257.13:13:33.67#ibcon#enter sib2, iclass 5, count 2 2006.257.13:13:33.67#ibcon#flushed, iclass 5, count 2 2006.257.13:13:33.67#ibcon#about to write, iclass 5, count 2 2006.257.13:13:33.67#ibcon#wrote, iclass 5, count 2 2006.257.13:13:33.67#ibcon#about to read 3, iclass 5, count 2 2006.257.13:13:33.70#ibcon#read 3, iclass 5, count 2 2006.257.13:13:33.70#ibcon#about to read 4, iclass 5, count 2 2006.257.13:13:33.70#ibcon#read 4, iclass 5, count 2 2006.257.13:13:33.70#ibcon#about to read 5, iclass 5, count 2 2006.257.13:13:33.70#ibcon#read 5, iclass 5, count 2 2006.257.13:13:33.70#ibcon#about to read 6, iclass 5, count 2 2006.257.13:13:33.70#ibcon#read 6, iclass 5, count 2 2006.257.13:13:33.70#ibcon#end of sib2, iclass 5, count 2 2006.257.13:13:33.70#ibcon#*after write, iclass 5, count 2 2006.257.13:13:33.70#ibcon#*before return 0, iclass 5, count 2 2006.257.13:13:33.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:33.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:13:33.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.13:13:33.70#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:33.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:33.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:33.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:33.82#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:13:33.82#ibcon#first serial, iclass 5, count 0 2006.257.13:13:33.82#ibcon#enter sib2, iclass 5, count 0 2006.257.13:13:33.82#ibcon#flushed, iclass 5, count 0 2006.257.13:13:33.82#ibcon#about to write, iclass 5, count 0 2006.257.13:13:33.82#ibcon#wrote, iclass 5, count 0 2006.257.13:13:33.82#ibcon#about to read 3, iclass 5, count 0 2006.257.13:13:33.84#ibcon#read 3, iclass 5, count 0 2006.257.13:13:33.84#ibcon#about to read 4, iclass 5, count 0 2006.257.13:13:33.84#ibcon#read 4, iclass 5, count 0 2006.257.13:13:33.84#ibcon#about to read 5, iclass 5, count 0 2006.257.13:13:33.84#ibcon#read 5, iclass 5, count 0 2006.257.13:13:33.84#ibcon#about to read 6, iclass 5, count 0 2006.257.13:13:33.84#ibcon#read 6, iclass 5, count 0 2006.257.13:13:33.84#ibcon#end of sib2, iclass 5, count 0 2006.257.13:13:33.84#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:13:33.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:13:33.84#ibcon#[27=USB\r\n] 2006.257.13:13:33.84#ibcon#*before write, iclass 5, count 0 2006.257.13:13:33.84#ibcon#enter sib2, iclass 5, count 0 2006.257.13:13:33.84#ibcon#flushed, iclass 5, count 0 2006.257.13:13:33.84#ibcon#about to write, iclass 5, count 0 2006.257.13:13:33.84#ibcon#wrote, iclass 5, count 0 2006.257.13:13:33.84#ibcon#about to read 3, iclass 5, count 0 2006.257.13:13:33.87#ibcon#read 3, iclass 5, count 0 2006.257.13:13:33.87#ibcon#about to read 4, iclass 5, count 0 2006.257.13:13:33.87#ibcon#read 4, iclass 5, count 0 2006.257.13:13:33.87#ibcon#about to read 5, iclass 5, count 0 2006.257.13:13:33.87#ibcon#read 5, iclass 5, count 0 2006.257.13:13:33.87#ibcon#about to read 6, iclass 5, count 0 2006.257.13:13:33.87#ibcon#read 6, iclass 5, count 0 2006.257.13:13:33.87#ibcon#end of sib2, iclass 5, count 0 2006.257.13:13:33.87#ibcon#*after write, iclass 5, count 0 2006.257.13:13:33.87#ibcon#*before return 0, iclass 5, count 0 2006.257.13:13:33.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:33.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:13:33.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:13:33.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:13:33.87$vck44/vblo=7,734.99 2006.257.13:13:33.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.13:13:33.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.13:13:33.87#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:33.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:33.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:33.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:33.87#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:13:33.87#ibcon#first serial, iclass 7, count 0 2006.257.13:13:33.87#ibcon#enter sib2, iclass 7, count 0 2006.257.13:13:33.87#ibcon#flushed, iclass 7, count 0 2006.257.13:13:33.87#ibcon#about to write, iclass 7, count 0 2006.257.13:13:33.87#ibcon#wrote, iclass 7, count 0 2006.257.13:13:33.87#ibcon#about to read 3, iclass 7, count 0 2006.257.13:13:33.89#ibcon#read 3, iclass 7, count 0 2006.257.13:13:33.89#ibcon#about to read 4, iclass 7, count 0 2006.257.13:13:33.89#ibcon#read 4, iclass 7, count 0 2006.257.13:13:33.89#ibcon#about to read 5, iclass 7, count 0 2006.257.13:13:33.89#ibcon#read 5, iclass 7, count 0 2006.257.13:13:33.89#ibcon#about to read 6, iclass 7, count 0 2006.257.13:13:33.89#ibcon#read 6, iclass 7, count 0 2006.257.13:13:33.89#ibcon#end of sib2, iclass 7, count 0 2006.257.13:13:33.89#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:13:33.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:13:33.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:13:33.89#ibcon#*before write, iclass 7, count 0 2006.257.13:13:33.89#ibcon#enter sib2, iclass 7, count 0 2006.257.13:13:33.89#ibcon#flushed, iclass 7, count 0 2006.257.13:13:33.89#ibcon#about to write, iclass 7, count 0 2006.257.13:13:33.89#ibcon#wrote, iclass 7, count 0 2006.257.13:13:33.89#ibcon#about to read 3, iclass 7, count 0 2006.257.13:13:33.93#ibcon#read 3, iclass 7, count 0 2006.257.13:13:33.93#ibcon#about to read 4, iclass 7, count 0 2006.257.13:13:33.93#ibcon#read 4, iclass 7, count 0 2006.257.13:13:33.93#ibcon#about to read 5, iclass 7, count 0 2006.257.13:13:33.93#ibcon#read 5, iclass 7, count 0 2006.257.13:13:33.93#ibcon#about to read 6, iclass 7, count 0 2006.257.13:13:33.93#ibcon#read 6, iclass 7, count 0 2006.257.13:13:33.93#ibcon#end of sib2, iclass 7, count 0 2006.257.13:13:33.93#ibcon#*after write, iclass 7, count 0 2006.257.13:13:33.93#ibcon#*before return 0, iclass 7, count 0 2006.257.13:13:33.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:33.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:13:33.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:13:33.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:13:33.93$vck44/vb=7,4 2006.257.13:13:33.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.13:13:33.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.13:13:33.93#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:33.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:33.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:33.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:33.99#ibcon#enter wrdev, iclass 11, count 2 2006.257.13:13:33.99#ibcon#first serial, iclass 11, count 2 2006.257.13:13:33.99#ibcon#enter sib2, iclass 11, count 2 2006.257.13:13:33.99#ibcon#flushed, iclass 11, count 2 2006.257.13:13:33.99#ibcon#about to write, iclass 11, count 2 2006.257.13:13:33.99#ibcon#wrote, iclass 11, count 2 2006.257.13:13:33.99#ibcon#about to read 3, iclass 11, count 2 2006.257.13:13:34.01#ibcon#read 3, iclass 11, count 2 2006.257.13:13:34.01#ibcon#about to read 4, iclass 11, count 2 2006.257.13:13:34.01#ibcon#read 4, iclass 11, count 2 2006.257.13:13:34.01#ibcon#about to read 5, iclass 11, count 2 2006.257.13:13:34.01#ibcon#read 5, iclass 11, count 2 2006.257.13:13:34.01#ibcon#about to read 6, iclass 11, count 2 2006.257.13:13:34.01#ibcon#read 6, iclass 11, count 2 2006.257.13:13:34.01#ibcon#end of sib2, iclass 11, count 2 2006.257.13:13:34.01#ibcon#*mode == 0, iclass 11, count 2 2006.257.13:13:34.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.13:13:34.01#ibcon#[27=AT07-04\r\n] 2006.257.13:13:34.01#ibcon#*before write, iclass 11, count 2 2006.257.13:13:34.01#ibcon#enter sib2, iclass 11, count 2 2006.257.13:13:34.01#ibcon#flushed, iclass 11, count 2 2006.257.13:13:34.01#ibcon#about to write, iclass 11, count 2 2006.257.13:13:34.01#ibcon#wrote, iclass 11, count 2 2006.257.13:13:34.01#ibcon#about to read 3, iclass 11, count 2 2006.257.13:13:34.04#ibcon#read 3, iclass 11, count 2 2006.257.13:13:34.04#ibcon#about to read 4, iclass 11, count 2 2006.257.13:13:34.04#ibcon#read 4, iclass 11, count 2 2006.257.13:13:34.04#ibcon#about to read 5, iclass 11, count 2 2006.257.13:13:34.04#ibcon#read 5, iclass 11, count 2 2006.257.13:13:34.04#ibcon#about to read 6, iclass 11, count 2 2006.257.13:13:34.04#ibcon#read 6, iclass 11, count 2 2006.257.13:13:34.04#ibcon#end of sib2, iclass 11, count 2 2006.257.13:13:34.04#ibcon#*after write, iclass 11, count 2 2006.257.13:13:34.04#ibcon#*before return 0, iclass 11, count 2 2006.257.13:13:34.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:34.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:13:34.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.13:13:34.04#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:34.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:34.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:34.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:34.16#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:13:34.16#ibcon#first serial, iclass 11, count 0 2006.257.13:13:34.16#ibcon#enter sib2, iclass 11, count 0 2006.257.13:13:34.16#ibcon#flushed, iclass 11, count 0 2006.257.13:13:34.16#ibcon#about to write, iclass 11, count 0 2006.257.13:13:34.16#ibcon#wrote, iclass 11, count 0 2006.257.13:13:34.16#ibcon#about to read 3, iclass 11, count 0 2006.257.13:13:34.18#ibcon#read 3, iclass 11, count 0 2006.257.13:13:34.18#ibcon#about to read 4, iclass 11, count 0 2006.257.13:13:34.18#ibcon#read 4, iclass 11, count 0 2006.257.13:13:34.18#ibcon#about to read 5, iclass 11, count 0 2006.257.13:13:34.18#ibcon#read 5, iclass 11, count 0 2006.257.13:13:34.18#ibcon#about to read 6, iclass 11, count 0 2006.257.13:13:34.18#ibcon#read 6, iclass 11, count 0 2006.257.13:13:34.18#ibcon#end of sib2, iclass 11, count 0 2006.257.13:13:34.18#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:13:34.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:13:34.18#ibcon#[27=USB\r\n] 2006.257.13:13:34.18#ibcon#*before write, iclass 11, count 0 2006.257.13:13:34.18#ibcon#enter sib2, iclass 11, count 0 2006.257.13:13:34.18#ibcon#flushed, iclass 11, count 0 2006.257.13:13:34.18#ibcon#about to write, iclass 11, count 0 2006.257.13:13:34.18#ibcon#wrote, iclass 11, count 0 2006.257.13:13:34.18#ibcon#about to read 3, iclass 11, count 0 2006.257.13:13:34.21#ibcon#read 3, iclass 11, count 0 2006.257.13:13:34.21#ibcon#about to read 4, iclass 11, count 0 2006.257.13:13:34.21#ibcon#read 4, iclass 11, count 0 2006.257.13:13:34.21#ibcon#about to read 5, iclass 11, count 0 2006.257.13:13:34.21#ibcon#read 5, iclass 11, count 0 2006.257.13:13:34.21#ibcon#about to read 6, iclass 11, count 0 2006.257.13:13:34.21#ibcon#read 6, iclass 11, count 0 2006.257.13:13:34.21#ibcon#end of sib2, iclass 11, count 0 2006.257.13:13:34.21#ibcon#*after write, iclass 11, count 0 2006.257.13:13:34.21#ibcon#*before return 0, iclass 11, count 0 2006.257.13:13:34.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:34.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:13:34.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:13:34.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:13:34.21$vck44/vblo=8,744.99 2006.257.13:13:34.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:13:34.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:13:34.21#ibcon#ireg 17 cls_cnt 0 2006.257.13:13:34.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:34.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:34.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:34.21#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:13:34.21#ibcon#first serial, iclass 13, count 0 2006.257.13:13:34.21#ibcon#enter sib2, iclass 13, count 0 2006.257.13:13:34.21#ibcon#flushed, iclass 13, count 0 2006.257.13:13:34.21#ibcon#about to write, iclass 13, count 0 2006.257.13:13:34.21#ibcon#wrote, iclass 13, count 0 2006.257.13:13:34.21#ibcon#about to read 3, iclass 13, count 0 2006.257.13:13:34.23#ibcon#read 3, iclass 13, count 0 2006.257.13:13:34.23#ibcon#about to read 4, iclass 13, count 0 2006.257.13:13:34.23#ibcon#read 4, iclass 13, count 0 2006.257.13:13:34.23#ibcon#about to read 5, iclass 13, count 0 2006.257.13:13:34.23#ibcon#read 5, iclass 13, count 0 2006.257.13:13:34.23#ibcon#about to read 6, iclass 13, count 0 2006.257.13:13:34.23#ibcon#read 6, iclass 13, count 0 2006.257.13:13:34.23#ibcon#end of sib2, iclass 13, count 0 2006.257.13:13:34.23#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:13:34.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:13:34.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:13:34.23#ibcon#*before write, iclass 13, count 0 2006.257.13:13:34.23#ibcon#enter sib2, iclass 13, count 0 2006.257.13:13:34.23#ibcon#flushed, iclass 13, count 0 2006.257.13:13:34.23#ibcon#about to write, iclass 13, count 0 2006.257.13:13:34.23#ibcon#wrote, iclass 13, count 0 2006.257.13:13:34.23#ibcon#about to read 3, iclass 13, count 0 2006.257.13:13:34.27#ibcon#read 3, iclass 13, count 0 2006.257.13:13:34.27#ibcon#about to read 4, iclass 13, count 0 2006.257.13:13:34.27#ibcon#read 4, iclass 13, count 0 2006.257.13:13:34.27#ibcon#about to read 5, iclass 13, count 0 2006.257.13:13:34.27#ibcon#read 5, iclass 13, count 0 2006.257.13:13:34.27#ibcon#about to read 6, iclass 13, count 0 2006.257.13:13:34.27#ibcon#read 6, iclass 13, count 0 2006.257.13:13:34.27#ibcon#end of sib2, iclass 13, count 0 2006.257.13:13:34.27#ibcon#*after write, iclass 13, count 0 2006.257.13:13:34.27#ibcon#*before return 0, iclass 13, count 0 2006.257.13:13:34.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:34.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:13:34.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:13:34.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:13:34.27$vck44/vb=8,4 2006.257.13:13:34.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.13:13:34.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.13:13:34.27#ibcon#ireg 11 cls_cnt 2 2006.257.13:13:34.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:34.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:34.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:34.33#ibcon#enter wrdev, iclass 15, count 2 2006.257.13:13:34.33#ibcon#first serial, iclass 15, count 2 2006.257.13:13:34.33#ibcon#enter sib2, iclass 15, count 2 2006.257.13:13:34.33#ibcon#flushed, iclass 15, count 2 2006.257.13:13:34.33#ibcon#about to write, iclass 15, count 2 2006.257.13:13:34.33#ibcon#wrote, iclass 15, count 2 2006.257.13:13:34.33#ibcon#about to read 3, iclass 15, count 2 2006.257.13:13:34.35#ibcon#read 3, iclass 15, count 2 2006.257.13:13:34.35#ibcon#about to read 4, iclass 15, count 2 2006.257.13:13:34.35#ibcon#read 4, iclass 15, count 2 2006.257.13:13:34.35#ibcon#about to read 5, iclass 15, count 2 2006.257.13:13:34.35#ibcon#read 5, iclass 15, count 2 2006.257.13:13:34.35#ibcon#about to read 6, iclass 15, count 2 2006.257.13:13:34.35#ibcon#read 6, iclass 15, count 2 2006.257.13:13:34.35#ibcon#end of sib2, iclass 15, count 2 2006.257.13:13:34.35#ibcon#*mode == 0, iclass 15, count 2 2006.257.13:13:34.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.13:13:34.35#ibcon#[27=AT08-04\r\n] 2006.257.13:13:34.35#ibcon#*before write, iclass 15, count 2 2006.257.13:13:34.35#ibcon#enter sib2, iclass 15, count 2 2006.257.13:13:34.35#ibcon#flushed, iclass 15, count 2 2006.257.13:13:34.35#ibcon#about to write, iclass 15, count 2 2006.257.13:13:34.35#ibcon#wrote, iclass 15, count 2 2006.257.13:13:34.35#ibcon#about to read 3, iclass 15, count 2 2006.257.13:13:34.38#ibcon#read 3, iclass 15, count 2 2006.257.13:13:34.38#ibcon#about to read 4, iclass 15, count 2 2006.257.13:13:34.38#ibcon#read 4, iclass 15, count 2 2006.257.13:13:34.38#ibcon#about to read 5, iclass 15, count 2 2006.257.13:13:34.38#ibcon#read 5, iclass 15, count 2 2006.257.13:13:34.38#ibcon#about to read 6, iclass 15, count 2 2006.257.13:13:34.38#ibcon#read 6, iclass 15, count 2 2006.257.13:13:34.38#ibcon#end of sib2, iclass 15, count 2 2006.257.13:13:34.38#ibcon#*after write, iclass 15, count 2 2006.257.13:13:34.38#ibcon#*before return 0, iclass 15, count 2 2006.257.13:13:34.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:34.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:13:34.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.13:13:34.38#ibcon#ireg 7 cls_cnt 0 2006.257.13:13:34.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:34.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:34.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:34.50#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:13:34.50#ibcon#first serial, iclass 15, count 0 2006.257.13:13:34.50#ibcon#enter sib2, iclass 15, count 0 2006.257.13:13:34.50#ibcon#flushed, iclass 15, count 0 2006.257.13:13:34.50#ibcon#about to write, iclass 15, count 0 2006.257.13:13:34.50#ibcon#wrote, iclass 15, count 0 2006.257.13:13:34.50#ibcon#about to read 3, iclass 15, count 0 2006.257.13:13:34.52#ibcon#read 3, iclass 15, count 0 2006.257.13:13:34.52#ibcon#about to read 4, iclass 15, count 0 2006.257.13:13:34.52#ibcon#read 4, iclass 15, count 0 2006.257.13:13:34.52#ibcon#about to read 5, iclass 15, count 0 2006.257.13:13:34.52#ibcon#read 5, iclass 15, count 0 2006.257.13:13:34.52#ibcon#about to read 6, iclass 15, count 0 2006.257.13:13:34.52#ibcon#read 6, iclass 15, count 0 2006.257.13:13:34.52#ibcon#end of sib2, iclass 15, count 0 2006.257.13:13:34.52#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:13:34.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:13:34.52#ibcon#[27=USB\r\n] 2006.257.13:13:34.52#ibcon#*before write, iclass 15, count 0 2006.257.13:13:34.52#ibcon#enter sib2, iclass 15, count 0 2006.257.13:13:34.52#ibcon#flushed, iclass 15, count 0 2006.257.13:13:34.52#ibcon#about to write, iclass 15, count 0 2006.257.13:13:34.52#ibcon#wrote, iclass 15, count 0 2006.257.13:13:34.52#ibcon#about to read 3, iclass 15, count 0 2006.257.13:13:34.55#ibcon#read 3, iclass 15, count 0 2006.257.13:13:34.55#ibcon#about to read 4, iclass 15, count 0 2006.257.13:13:34.55#ibcon#read 4, iclass 15, count 0 2006.257.13:13:34.55#ibcon#about to read 5, iclass 15, count 0 2006.257.13:13:34.55#ibcon#read 5, iclass 15, count 0 2006.257.13:13:34.55#ibcon#about to read 6, iclass 15, count 0 2006.257.13:13:34.55#ibcon#read 6, iclass 15, count 0 2006.257.13:13:34.55#ibcon#end of sib2, iclass 15, count 0 2006.257.13:13:34.55#ibcon#*after write, iclass 15, count 0 2006.257.13:13:34.55#ibcon#*before return 0, iclass 15, count 0 2006.257.13:13:34.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:34.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:13:34.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:13:34.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:13:34.55$vck44/vabw=wide 2006.257.13:13:34.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.13:13:34.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.13:13:34.55#ibcon#ireg 8 cls_cnt 0 2006.257.13:13:34.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:34.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:34.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:34.55#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:13:34.55#ibcon#first serial, iclass 17, count 0 2006.257.13:13:34.55#ibcon#enter sib2, iclass 17, count 0 2006.257.13:13:34.55#ibcon#flushed, iclass 17, count 0 2006.257.13:13:34.55#ibcon#about to write, iclass 17, count 0 2006.257.13:13:34.55#ibcon#wrote, iclass 17, count 0 2006.257.13:13:34.55#ibcon#about to read 3, iclass 17, count 0 2006.257.13:13:34.57#ibcon#read 3, iclass 17, count 0 2006.257.13:13:34.57#ibcon#about to read 4, iclass 17, count 0 2006.257.13:13:34.57#ibcon#read 4, iclass 17, count 0 2006.257.13:13:34.57#ibcon#about to read 5, iclass 17, count 0 2006.257.13:13:34.57#ibcon#read 5, iclass 17, count 0 2006.257.13:13:34.57#ibcon#about to read 6, iclass 17, count 0 2006.257.13:13:34.57#ibcon#read 6, iclass 17, count 0 2006.257.13:13:34.57#ibcon#end of sib2, iclass 17, count 0 2006.257.13:13:34.57#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:13:34.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:13:34.57#ibcon#[25=BW32\r\n] 2006.257.13:13:34.57#ibcon#*before write, iclass 17, count 0 2006.257.13:13:34.57#ibcon#enter sib2, iclass 17, count 0 2006.257.13:13:34.57#ibcon#flushed, iclass 17, count 0 2006.257.13:13:34.57#ibcon#about to write, iclass 17, count 0 2006.257.13:13:34.57#ibcon#wrote, iclass 17, count 0 2006.257.13:13:34.57#ibcon#about to read 3, iclass 17, count 0 2006.257.13:13:34.60#ibcon#read 3, iclass 17, count 0 2006.257.13:13:34.60#ibcon#about to read 4, iclass 17, count 0 2006.257.13:13:34.60#ibcon#read 4, iclass 17, count 0 2006.257.13:13:34.60#ibcon#about to read 5, iclass 17, count 0 2006.257.13:13:34.60#ibcon#read 5, iclass 17, count 0 2006.257.13:13:34.60#ibcon#about to read 6, iclass 17, count 0 2006.257.13:13:34.60#ibcon#read 6, iclass 17, count 0 2006.257.13:13:34.60#ibcon#end of sib2, iclass 17, count 0 2006.257.13:13:34.60#ibcon#*after write, iclass 17, count 0 2006.257.13:13:34.60#ibcon#*before return 0, iclass 17, count 0 2006.257.13:13:34.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:34.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:13:34.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:13:34.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:13:34.60$vck44/vbbw=wide 2006.257.13:13:34.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.13:13:34.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.13:13:34.60#ibcon#ireg 8 cls_cnt 0 2006.257.13:13:34.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:13:34.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:13:34.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:13:34.67#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:13:34.67#ibcon#first serial, iclass 19, count 0 2006.257.13:13:34.67#ibcon#enter sib2, iclass 19, count 0 2006.257.13:13:34.67#ibcon#flushed, iclass 19, count 0 2006.257.13:13:34.67#ibcon#about to write, iclass 19, count 0 2006.257.13:13:34.67#ibcon#wrote, iclass 19, count 0 2006.257.13:13:34.67#ibcon#about to read 3, iclass 19, count 0 2006.257.13:13:34.69#ibcon#read 3, iclass 19, count 0 2006.257.13:13:34.69#ibcon#about to read 4, iclass 19, count 0 2006.257.13:13:34.69#ibcon#read 4, iclass 19, count 0 2006.257.13:13:34.69#ibcon#about to read 5, iclass 19, count 0 2006.257.13:13:34.69#ibcon#read 5, iclass 19, count 0 2006.257.13:13:34.69#ibcon#about to read 6, iclass 19, count 0 2006.257.13:13:34.69#ibcon#read 6, iclass 19, count 0 2006.257.13:13:34.69#ibcon#end of sib2, iclass 19, count 0 2006.257.13:13:34.69#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:13:34.69#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:13:34.69#ibcon#[27=BW32\r\n] 2006.257.13:13:34.69#ibcon#*before write, iclass 19, count 0 2006.257.13:13:34.69#ibcon#enter sib2, iclass 19, count 0 2006.257.13:13:34.69#ibcon#flushed, iclass 19, count 0 2006.257.13:13:34.69#ibcon#about to write, iclass 19, count 0 2006.257.13:13:34.69#ibcon#wrote, iclass 19, count 0 2006.257.13:13:34.69#ibcon#about to read 3, iclass 19, count 0 2006.257.13:13:34.72#ibcon#read 3, iclass 19, count 0 2006.257.13:13:34.72#ibcon#about to read 4, iclass 19, count 0 2006.257.13:13:34.72#ibcon#read 4, iclass 19, count 0 2006.257.13:13:34.72#ibcon#about to read 5, iclass 19, count 0 2006.257.13:13:34.72#ibcon#read 5, iclass 19, count 0 2006.257.13:13:34.72#ibcon#about to read 6, iclass 19, count 0 2006.257.13:13:34.72#ibcon#read 6, iclass 19, count 0 2006.257.13:13:34.72#ibcon#end of sib2, iclass 19, count 0 2006.257.13:13:34.72#ibcon#*after write, iclass 19, count 0 2006.257.13:13:34.72#ibcon#*before return 0, iclass 19, count 0 2006.257.13:13:34.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:13:34.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:13:34.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:13:34.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:13:34.72$setupk4/ifdk4 2006.257.13:13:34.72$ifdk4/lo= 2006.257.13:13:34.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:13:34.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:13:34.72$ifdk4/patch= 2006.257.13:13:34.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:13:34.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:13:34.72$setupk4/!*+20s 2006.257.13:13:36.33#abcon#<5=/14 1.5 4.3 17.69 971013.7\r\n> 2006.257.13:13:36.35#abcon#{5=INTERFACE CLEAR} 2006.257.13:13:36.41#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:13:38.13#trakl#Source acquired 2006.257.13:13:39.13#flagr#flagr/antenna,acquired 2006.257.13:13:46.50#abcon#<5=/14 1.5 4.3 17.69 971013.7\r\n> 2006.257.13:13:46.52#abcon#{5=INTERFACE CLEAR} 2006.257.13:13:46.58#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:13:49.22$setupk4/"tpicd 2006.257.13:13:49.22$setupk4/echo=off 2006.257.13:13:49.22$setupk4/xlog=off 2006.257.13:13:49.22:!2006.257.13:14:25 2006.257.13:14:25.02:preob 2006.257.13:14:26.14/onsource/TRACKING 2006.257.13:14:26.14:!2006.257.13:14:35 2006.257.13:14:35.02:"tape 2006.257.13:14:35.02:"st=record 2006.257.13:14:35.02:data_valid=on 2006.257.13:14:35.02:midob 2006.257.13:14:36.14/onsource/TRACKING 2006.257.13:14:36.14/wx/17.68,1013.7,97 2006.257.13:14:36.19/cable/+6.4826E-03 2006.257.13:14:37.28/va/01,08,usb,yes,30,32 2006.257.13:14:37.28/va/02,07,usb,yes,32,33 2006.257.13:14:37.28/va/03,08,usb,yes,29,31 2006.257.13:14:37.28/va/04,07,usb,yes,33,35 2006.257.13:14:37.28/va/05,04,usb,yes,30,30 2006.257.13:14:37.28/va/06,04,usb,yes,33,33 2006.257.13:14:37.28/va/07,04,usb,yes,34,34 2006.257.13:14:37.28/va/08,04,usb,yes,28,35 2006.257.13:14:37.51/valo/01,524.99,yes,locked 2006.257.13:14:37.51/valo/02,534.99,yes,locked 2006.257.13:14:37.51/valo/03,564.99,yes,locked 2006.257.13:14:37.51/valo/04,624.99,yes,locked 2006.257.13:14:37.51/valo/05,734.99,yes,locked 2006.257.13:14:37.51/valo/06,814.99,yes,locked 2006.257.13:14:37.51/valo/07,864.99,yes,locked 2006.257.13:14:37.51/valo/08,884.99,yes,locked 2006.257.13:14:38.60/vb/01,04,usb,yes,30,28 2006.257.13:14:38.60/vb/02,05,usb,yes,28,28 2006.257.13:14:38.60/vb/03,04,usb,yes,29,32 2006.257.13:14:38.60/vb/04,05,usb,yes,29,28 2006.257.13:14:38.60/vb/05,04,usb,yes,26,28 2006.257.13:14:38.60/vb/06,04,usb,yes,30,27 2006.257.13:14:38.60/vb/07,04,usb,yes,30,30 2006.257.13:14:38.60/vb/08,04,usb,yes,28,31 2006.257.13:14:38.83/vblo/01,629.99,yes,locked 2006.257.13:14:38.83/vblo/02,634.99,yes,locked 2006.257.13:14:38.83/vblo/03,649.99,yes,locked 2006.257.13:14:38.83/vblo/04,679.99,yes,locked 2006.257.13:14:38.83/vblo/05,709.99,yes,locked 2006.257.13:14:38.83/vblo/06,719.99,yes,locked 2006.257.13:14:38.83/vblo/07,734.99,yes,locked 2006.257.13:14:38.83/vblo/08,744.99,yes,locked 2006.257.13:14:38.98/vabw/8 2006.257.13:14:39.13/vbbw/8 2006.257.13:14:39.22/xfe/off,on,15.2 2006.257.13:14:39.59/ifatt/23,28,28,28 2006.257.13:14:40.07/fmout-gps/S +4.60E-07 2006.257.13:14:40.12:!2006.257.13:15:45 2006.257.13:15:45.02:data_valid=off 2006.257.13:15:45.02:"et 2006.257.13:15:45.02:!+3s 2006.257.13:15:48.05:"tape 2006.257.13:15:48.06:postob 2006.257.13:15:48.22/cable/+6.4822E-03 2006.257.13:15:48.23/wx/17.68,1013.7,97 2006.257.13:15:48.28/fmout-gps/S +4.61E-07 2006.257.13:15:48.29:scan_name=257-1318,jd0609,120 2006.257.13:15:48.29:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.13:15:49.15#flagr#flagr/antenna,new-source 2006.257.13:15:49.15:checkk5 2006.257.13:15:49.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:15:49.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:15:50.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:15:50.81/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:15:51.19/chk_obsdata//k5ts1/T2571314??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.13:15:51.59/chk_obsdata//k5ts2/T2571314??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.13:15:51.98/chk_obsdata//k5ts3/T2571314??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.13:15:52.38/chk_obsdata//k5ts4/T2571314??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.13:15:53.11/k5log//k5ts1_log_newline 2006.257.13:15:53.83/k5log//k5ts2_log_newline 2006.257.13:15:54.52/k5log//k5ts3_log_newline 2006.257.13:15:55.23/k5log//k5ts4_log_newline 2006.257.13:15:55.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:15:55.25:setupk4=1 2006.257.13:15:55.25$setupk4/echo=on 2006.257.13:15:55.25$setupk4/pcalon 2006.257.13:15:55.25$pcalon/"no phase cal control is implemented here 2006.257.13:15:55.25$setupk4/"tpicd=stop 2006.257.13:15:55.25$setupk4/"rec=synch_on 2006.257.13:15:55.25$setupk4/"rec_mode=128 2006.257.13:15:55.25$setupk4/!* 2006.257.13:15:55.25$setupk4/recpk4 2006.257.13:15:55.25$recpk4/recpatch= 2006.257.13:15:55.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:15:55.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:15:55.25$setupk4/vck44 2006.257.13:15:55.25$vck44/valo=1,524.99 2006.257.13:15:55.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.13:15:55.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.13:15:55.25#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:55.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:55.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:55.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:55.25#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:15:55.25#ibcon#first serial, iclass 6, count 0 2006.257.13:15:55.25#ibcon#enter sib2, iclass 6, count 0 2006.257.13:15:55.25#ibcon#flushed, iclass 6, count 0 2006.257.13:15:55.25#ibcon#about to write, iclass 6, count 0 2006.257.13:15:55.25#ibcon#wrote, iclass 6, count 0 2006.257.13:15:55.25#ibcon#about to read 3, iclass 6, count 0 2006.257.13:15:55.27#ibcon#read 3, iclass 6, count 0 2006.257.13:15:55.27#ibcon#about to read 4, iclass 6, count 0 2006.257.13:15:55.27#ibcon#read 4, iclass 6, count 0 2006.257.13:15:55.27#ibcon#about to read 5, iclass 6, count 0 2006.257.13:15:55.27#ibcon#read 5, iclass 6, count 0 2006.257.13:15:55.27#ibcon#about to read 6, iclass 6, count 0 2006.257.13:15:55.27#ibcon#read 6, iclass 6, count 0 2006.257.13:15:55.27#ibcon#end of sib2, iclass 6, count 0 2006.257.13:15:55.27#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:15:55.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:15:55.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:15:55.27#ibcon#*before write, iclass 6, count 0 2006.257.13:15:55.27#ibcon#enter sib2, iclass 6, count 0 2006.257.13:15:55.27#ibcon#flushed, iclass 6, count 0 2006.257.13:15:55.27#ibcon#about to write, iclass 6, count 0 2006.257.13:15:55.27#ibcon#wrote, iclass 6, count 0 2006.257.13:15:55.27#ibcon#about to read 3, iclass 6, count 0 2006.257.13:15:55.32#ibcon#read 3, iclass 6, count 0 2006.257.13:15:55.32#ibcon#about to read 4, iclass 6, count 0 2006.257.13:15:55.32#ibcon#read 4, iclass 6, count 0 2006.257.13:15:55.32#ibcon#about to read 5, iclass 6, count 0 2006.257.13:15:55.32#ibcon#read 5, iclass 6, count 0 2006.257.13:15:55.32#ibcon#about to read 6, iclass 6, count 0 2006.257.13:15:55.32#ibcon#read 6, iclass 6, count 0 2006.257.13:15:55.32#ibcon#end of sib2, iclass 6, count 0 2006.257.13:15:55.32#ibcon#*after write, iclass 6, count 0 2006.257.13:15:55.32#ibcon#*before return 0, iclass 6, count 0 2006.257.13:15:55.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:55.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:55.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:15:55.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:15:55.33$vck44/va=1,8 2006.257.13:15:55.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.13:15:55.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.13:15:55.33#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:55.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:55.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:55.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:55.33#ibcon#enter wrdev, iclass 10, count 2 2006.257.13:15:55.33#ibcon#first serial, iclass 10, count 2 2006.257.13:15:55.33#ibcon#enter sib2, iclass 10, count 2 2006.257.13:15:55.33#ibcon#flushed, iclass 10, count 2 2006.257.13:15:55.33#ibcon#about to write, iclass 10, count 2 2006.257.13:15:55.33#ibcon#wrote, iclass 10, count 2 2006.257.13:15:55.33#ibcon#about to read 3, iclass 10, count 2 2006.257.13:15:55.34#ibcon#read 3, iclass 10, count 2 2006.257.13:15:55.34#ibcon#about to read 4, iclass 10, count 2 2006.257.13:15:55.34#ibcon#read 4, iclass 10, count 2 2006.257.13:15:55.34#ibcon#about to read 5, iclass 10, count 2 2006.257.13:15:55.34#ibcon#read 5, iclass 10, count 2 2006.257.13:15:55.34#ibcon#about to read 6, iclass 10, count 2 2006.257.13:15:55.34#ibcon#read 6, iclass 10, count 2 2006.257.13:15:55.34#ibcon#end of sib2, iclass 10, count 2 2006.257.13:15:55.34#ibcon#*mode == 0, iclass 10, count 2 2006.257.13:15:55.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.13:15:55.34#ibcon#[25=AT01-08\r\n] 2006.257.13:15:55.34#ibcon#*before write, iclass 10, count 2 2006.257.13:15:55.34#ibcon#enter sib2, iclass 10, count 2 2006.257.13:15:55.34#ibcon#flushed, iclass 10, count 2 2006.257.13:15:55.34#ibcon#about to write, iclass 10, count 2 2006.257.13:15:55.34#ibcon#wrote, iclass 10, count 2 2006.257.13:15:55.34#ibcon#about to read 3, iclass 10, count 2 2006.257.13:15:55.37#ibcon#read 3, iclass 10, count 2 2006.257.13:15:55.37#ibcon#about to read 4, iclass 10, count 2 2006.257.13:15:55.37#ibcon#read 4, iclass 10, count 2 2006.257.13:15:55.37#ibcon#about to read 5, iclass 10, count 2 2006.257.13:15:55.37#ibcon#read 5, iclass 10, count 2 2006.257.13:15:55.37#ibcon#about to read 6, iclass 10, count 2 2006.257.13:15:55.37#ibcon#read 6, iclass 10, count 2 2006.257.13:15:55.37#ibcon#end of sib2, iclass 10, count 2 2006.257.13:15:55.37#ibcon#*after write, iclass 10, count 2 2006.257.13:15:55.37#ibcon#*before return 0, iclass 10, count 2 2006.257.13:15:55.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:55.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:55.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.13:15:55.37#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:55.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:55.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:55.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:55.49#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:15:55.49#ibcon#first serial, iclass 10, count 0 2006.257.13:15:55.49#ibcon#enter sib2, iclass 10, count 0 2006.257.13:15:55.49#ibcon#flushed, iclass 10, count 0 2006.257.13:15:55.49#ibcon#about to write, iclass 10, count 0 2006.257.13:15:55.49#ibcon#wrote, iclass 10, count 0 2006.257.13:15:55.49#ibcon#about to read 3, iclass 10, count 0 2006.257.13:15:55.51#ibcon#read 3, iclass 10, count 0 2006.257.13:15:55.51#ibcon#about to read 4, iclass 10, count 0 2006.257.13:15:55.51#ibcon#read 4, iclass 10, count 0 2006.257.13:15:55.51#ibcon#about to read 5, iclass 10, count 0 2006.257.13:15:55.51#ibcon#read 5, iclass 10, count 0 2006.257.13:15:55.51#ibcon#about to read 6, iclass 10, count 0 2006.257.13:15:55.51#ibcon#read 6, iclass 10, count 0 2006.257.13:15:55.51#ibcon#end of sib2, iclass 10, count 0 2006.257.13:15:55.51#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:15:55.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:15:55.51#ibcon#[25=USB\r\n] 2006.257.13:15:55.51#ibcon#*before write, iclass 10, count 0 2006.257.13:15:55.51#ibcon#enter sib2, iclass 10, count 0 2006.257.13:15:55.51#ibcon#flushed, iclass 10, count 0 2006.257.13:15:55.51#ibcon#about to write, iclass 10, count 0 2006.257.13:15:55.51#ibcon#wrote, iclass 10, count 0 2006.257.13:15:55.52#ibcon#about to read 3, iclass 10, count 0 2006.257.13:15:55.54#ibcon#read 3, iclass 10, count 0 2006.257.13:15:55.54#ibcon#about to read 4, iclass 10, count 0 2006.257.13:15:55.54#ibcon#read 4, iclass 10, count 0 2006.257.13:15:55.54#ibcon#about to read 5, iclass 10, count 0 2006.257.13:15:55.54#ibcon#read 5, iclass 10, count 0 2006.257.13:15:55.54#ibcon#about to read 6, iclass 10, count 0 2006.257.13:15:55.54#ibcon#read 6, iclass 10, count 0 2006.257.13:15:55.54#ibcon#end of sib2, iclass 10, count 0 2006.257.13:15:55.54#ibcon#*after write, iclass 10, count 0 2006.257.13:15:55.54#ibcon#*before return 0, iclass 10, count 0 2006.257.13:15:55.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:55.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:55.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:15:55.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:15:55.55$vck44/valo=2,534.99 2006.257.13:15:55.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.13:15:55.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.13:15:55.55#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:55.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:55.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:55.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:55.55#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:15:55.55#ibcon#first serial, iclass 12, count 0 2006.257.13:15:55.55#ibcon#enter sib2, iclass 12, count 0 2006.257.13:15:55.55#ibcon#flushed, iclass 12, count 0 2006.257.13:15:55.55#ibcon#about to write, iclass 12, count 0 2006.257.13:15:55.55#ibcon#wrote, iclass 12, count 0 2006.257.13:15:55.55#ibcon#about to read 3, iclass 12, count 0 2006.257.13:15:55.56#ibcon#read 3, iclass 12, count 0 2006.257.13:15:55.56#ibcon#about to read 4, iclass 12, count 0 2006.257.13:15:55.56#ibcon#read 4, iclass 12, count 0 2006.257.13:15:55.56#ibcon#about to read 5, iclass 12, count 0 2006.257.13:15:55.56#ibcon#read 5, iclass 12, count 0 2006.257.13:15:55.56#ibcon#about to read 6, iclass 12, count 0 2006.257.13:15:55.56#ibcon#read 6, iclass 12, count 0 2006.257.13:15:55.56#ibcon#end of sib2, iclass 12, count 0 2006.257.13:15:55.56#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:15:55.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:15:55.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:15:55.56#ibcon#*before write, iclass 12, count 0 2006.257.13:15:55.56#ibcon#enter sib2, iclass 12, count 0 2006.257.13:15:55.56#ibcon#flushed, iclass 12, count 0 2006.257.13:15:55.56#ibcon#about to write, iclass 12, count 0 2006.257.13:15:55.56#ibcon#wrote, iclass 12, count 0 2006.257.13:15:55.56#ibcon#about to read 3, iclass 12, count 0 2006.257.13:15:55.60#ibcon#read 3, iclass 12, count 0 2006.257.13:15:55.60#ibcon#about to read 4, iclass 12, count 0 2006.257.13:15:55.60#ibcon#read 4, iclass 12, count 0 2006.257.13:15:55.60#ibcon#about to read 5, iclass 12, count 0 2006.257.13:15:55.60#ibcon#read 5, iclass 12, count 0 2006.257.13:15:55.60#ibcon#about to read 6, iclass 12, count 0 2006.257.13:15:55.60#ibcon#read 6, iclass 12, count 0 2006.257.13:15:55.60#ibcon#end of sib2, iclass 12, count 0 2006.257.13:15:55.60#ibcon#*after write, iclass 12, count 0 2006.257.13:15:55.60#ibcon#*before return 0, iclass 12, count 0 2006.257.13:15:55.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:55.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:55.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:15:55.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:15:55.61$vck44/va=2,7 2006.257.13:15:55.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.13:15:55.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.13:15:55.61#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:55.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:55.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:55.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:55.65#ibcon#enter wrdev, iclass 14, count 2 2006.257.13:15:55.65#ibcon#first serial, iclass 14, count 2 2006.257.13:15:55.65#ibcon#enter sib2, iclass 14, count 2 2006.257.13:15:55.65#ibcon#flushed, iclass 14, count 2 2006.257.13:15:55.65#ibcon#about to write, iclass 14, count 2 2006.257.13:15:55.65#ibcon#wrote, iclass 14, count 2 2006.257.13:15:55.65#ibcon#about to read 3, iclass 14, count 2 2006.257.13:15:55.67#ibcon#read 3, iclass 14, count 2 2006.257.13:15:55.67#ibcon#about to read 4, iclass 14, count 2 2006.257.13:15:55.67#ibcon#read 4, iclass 14, count 2 2006.257.13:15:55.67#ibcon#about to read 5, iclass 14, count 2 2006.257.13:15:55.67#ibcon#read 5, iclass 14, count 2 2006.257.13:15:55.67#ibcon#about to read 6, iclass 14, count 2 2006.257.13:15:55.67#ibcon#read 6, iclass 14, count 2 2006.257.13:15:55.67#ibcon#end of sib2, iclass 14, count 2 2006.257.13:15:55.67#ibcon#*mode == 0, iclass 14, count 2 2006.257.13:15:55.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.13:15:55.67#ibcon#[25=AT02-07\r\n] 2006.257.13:15:55.67#ibcon#*before write, iclass 14, count 2 2006.257.13:15:55.67#ibcon#enter sib2, iclass 14, count 2 2006.257.13:15:55.67#ibcon#flushed, iclass 14, count 2 2006.257.13:15:55.67#ibcon#about to write, iclass 14, count 2 2006.257.13:15:55.67#ibcon#wrote, iclass 14, count 2 2006.257.13:15:55.67#ibcon#about to read 3, iclass 14, count 2 2006.257.13:15:55.70#ibcon#read 3, iclass 14, count 2 2006.257.13:15:55.70#ibcon#about to read 4, iclass 14, count 2 2006.257.13:15:55.70#ibcon#read 4, iclass 14, count 2 2006.257.13:15:55.70#ibcon#about to read 5, iclass 14, count 2 2006.257.13:15:55.70#ibcon#read 5, iclass 14, count 2 2006.257.13:15:55.70#ibcon#about to read 6, iclass 14, count 2 2006.257.13:15:55.70#ibcon#read 6, iclass 14, count 2 2006.257.13:15:55.70#ibcon#end of sib2, iclass 14, count 2 2006.257.13:15:55.70#ibcon#*after write, iclass 14, count 2 2006.257.13:15:55.70#ibcon#*before return 0, iclass 14, count 2 2006.257.13:15:55.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:55.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:55.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.13:15:55.70#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:55.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:55.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:55.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:55.82#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:15:55.82#ibcon#first serial, iclass 14, count 0 2006.257.13:15:55.82#ibcon#enter sib2, iclass 14, count 0 2006.257.13:15:55.82#ibcon#flushed, iclass 14, count 0 2006.257.13:15:55.82#ibcon#about to write, iclass 14, count 0 2006.257.13:15:55.82#ibcon#wrote, iclass 14, count 0 2006.257.13:15:55.82#ibcon#about to read 3, iclass 14, count 0 2006.257.13:15:55.84#ibcon#read 3, iclass 14, count 0 2006.257.13:15:55.84#ibcon#about to read 4, iclass 14, count 0 2006.257.13:15:55.84#ibcon#read 4, iclass 14, count 0 2006.257.13:15:55.84#ibcon#about to read 5, iclass 14, count 0 2006.257.13:15:55.84#ibcon#read 5, iclass 14, count 0 2006.257.13:15:55.84#ibcon#about to read 6, iclass 14, count 0 2006.257.13:15:55.84#ibcon#read 6, iclass 14, count 0 2006.257.13:15:55.84#ibcon#end of sib2, iclass 14, count 0 2006.257.13:15:55.84#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:15:55.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:15:55.84#ibcon#[25=USB\r\n] 2006.257.13:15:55.84#ibcon#*before write, iclass 14, count 0 2006.257.13:15:55.84#ibcon#enter sib2, iclass 14, count 0 2006.257.13:15:55.84#ibcon#flushed, iclass 14, count 0 2006.257.13:15:55.84#ibcon#about to write, iclass 14, count 0 2006.257.13:15:55.84#ibcon#wrote, iclass 14, count 0 2006.257.13:15:55.84#ibcon#about to read 3, iclass 14, count 0 2006.257.13:15:55.87#ibcon#read 3, iclass 14, count 0 2006.257.13:15:55.87#ibcon#about to read 4, iclass 14, count 0 2006.257.13:15:55.87#ibcon#read 4, iclass 14, count 0 2006.257.13:15:55.87#ibcon#about to read 5, iclass 14, count 0 2006.257.13:15:55.87#ibcon#read 5, iclass 14, count 0 2006.257.13:15:55.87#ibcon#about to read 6, iclass 14, count 0 2006.257.13:15:55.87#ibcon#read 6, iclass 14, count 0 2006.257.13:15:55.87#ibcon#end of sib2, iclass 14, count 0 2006.257.13:15:55.87#ibcon#*after write, iclass 14, count 0 2006.257.13:15:55.87#ibcon#*before return 0, iclass 14, count 0 2006.257.13:15:55.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:55.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:55.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:15:55.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:15:55.87$vck44/valo=3,564.99 2006.257.13:15:55.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.13:15:55.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.13:15:55.88#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:55.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:15:55.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:15:55.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:15:55.88#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:15:55.88#ibcon#first serial, iclass 16, count 0 2006.257.13:15:55.88#ibcon#enter sib2, iclass 16, count 0 2006.257.13:15:55.88#ibcon#flushed, iclass 16, count 0 2006.257.13:15:55.88#ibcon#about to write, iclass 16, count 0 2006.257.13:15:55.88#ibcon#wrote, iclass 16, count 0 2006.257.13:15:55.88#ibcon#about to read 3, iclass 16, count 0 2006.257.13:15:55.89#ibcon#read 3, iclass 16, count 0 2006.257.13:15:55.89#ibcon#about to read 4, iclass 16, count 0 2006.257.13:15:55.89#ibcon#read 4, iclass 16, count 0 2006.257.13:15:55.89#ibcon#about to read 5, iclass 16, count 0 2006.257.13:15:55.89#ibcon#read 5, iclass 16, count 0 2006.257.13:15:55.89#ibcon#about to read 6, iclass 16, count 0 2006.257.13:15:55.89#ibcon#read 6, iclass 16, count 0 2006.257.13:15:55.89#ibcon#end of sib2, iclass 16, count 0 2006.257.13:15:55.89#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:15:55.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:15:55.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:15:55.89#ibcon#*before write, iclass 16, count 0 2006.257.13:15:55.89#ibcon#enter sib2, iclass 16, count 0 2006.257.13:15:55.89#ibcon#flushed, iclass 16, count 0 2006.257.13:15:55.89#ibcon#about to write, iclass 16, count 0 2006.257.13:15:55.89#ibcon#wrote, iclass 16, count 0 2006.257.13:15:55.89#ibcon#about to read 3, iclass 16, count 0 2006.257.13:15:55.93#ibcon#read 3, iclass 16, count 0 2006.257.13:15:55.93#ibcon#about to read 4, iclass 16, count 0 2006.257.13:15:55.93#ibcon#read 4, iclass 16, count 0 2006.257.13:15:55.93#ibcon#about to read 5, iclass 16, count 0 2006.257.13:15:55.93#ibcon#read 5, iclass 16, count 0 2006.257.13:15:55.93#ibcon#about to read 6, iclass 16, count 0 2006.257.13:15:55.93#ibcon#read 6, iclass 16, count 0 2006.257.13:15:55.93#ibcon#end of sib2, iclass 16, count 0 2006.257.13:15:55.93#ibcon#*after write, iclass 16, count 0 2006.257.13:15:55.93#ibcon#*before return 0, iclass 16, count 0 2006.257.13:15:55.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:15:55.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:15:55.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:15:55.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:15:55.94$vck44/va=3,8 2006.257.13:15:55.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.13:15:55.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.13:15:55.94#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:55.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:15:55.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:15:55.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:15:55.98#ibcon#enter wrdev, iclass 18, count 2 2006.257.13:15:55.98#ibcon#first serial, iclass 18, count 2 2006.257.13:15:55.98#ibcon#enter sib2, iclass 18, count 2 2006.257.13:15:55.98#ibcon#flushed, iclass 18, count 2 2006.257.13:15:55.98#ibcon#about to write, iclass 18, count 2 2006.257.13:15:55.98#ibcon#wrote, iclass 18, count 2 2006.257.13:15:55.98#ibcon#about to read 3, iclass 18, count 2 2006.257.13:15:56.00#ibcon#read 3, iclass 18, count 2 2006.257.13:15:56.00#ibcon#about to read 4, iclass 18, count 2 2006.257.13:15:56.00#ibcon#read 4, iclass 18, count 2 2006.257.13:15:56.00#ibcon#about to read 5, iclass 18, count 2 2006.257.13:15:56.00#ibcon#read 5, iclass 18, count 2 2006.257.13:15:56.00#ibcon#about to read 6, iclass 18, count 2 2006.257.13:15:56.00#ibcon#read 6, iclass 18, count 2 2006.257.13:15:56.00#ibcon#end of sib2, iclass 18, count 2 2006.257.13:15:56.00#ibcon#*mode == 0, iclass 18, count 2 2006.257.13:15:56.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.13:15:56.00#ibcon#[25=AT03-08\r\n] 2006.257.13:15:56.00#ibcon#*before write, iclass 18, count 2 2006.257.13:15:56.00#ibcon#enter sib2, iclass 18, count 2 2006.257.13:15:56.00#ibcon#flushed, iclass 18, count 2 2006.257.13:15:56.00#ibcon#about to write, iclass 18, count 2 2006.257.13:15:56.00#ibcon#wrote, iclass 18, count 2 2006.257.13:15:56.00#ibcon#about to read 3, iclass 18, count 2 2006.257.13:15:56.03#ibcon#read 3, iclass 18, count 2 2006.257.13:15:56.03#ibcon#about to read 4, iclass 18, count 2 2006.257.13:15:56.03#ibcon#read 4, iclass 18, count 2 2006.257.13:15:56.03#ibcon#about to read 5, iclass 18, count 2 2006.257.13:15:56.03#ibcon#read 5, iclass 18, count 2 2006.257.13:15:56.03#ibcon#about to read 6, iclass 18, count 2 2006.257.13:15:56.03#ibcon#read 6, iclass 18, count 2 2006.257.13:15:56.03#ibcon#end of sib2, iclass 18, count 2 2006.257.13:15:56.03#ibcon#*after write, iclass 18, count 2 2006.257.13:15:56.03#ibcon#*before return 0, iclass 18, count 2 2006.257.13:15:56.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:15:56.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:15:56.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.13:15:56.03#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:56.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:15:56.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:15:56.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:15:56.15#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:15:56.15#ibcon#first serial, iclass 18, count 0 2006.257.13:15:56.15#ibcon#enter sib2, iclass 18, count 0 2006.257.13:15:56.15#ibcon#flushed, iclass 18, count 0 2006.257.13:15:56.15#ibcon#about to write, iclass 18, count 0 2006.257.13:15:56.15#ibcon#wrote, iclass 18, count 0 2006.257.13:15:56.15#ibcon#about to read 3, iclass 18, count 0 2006.257.13:15:56.17#ibcon#read 3, iclass 18, count 0 2006.257.13:15:56.17#ibcon#about to read 4, iclass 18, count 0 2006.257.13:15:56.17#ibcon#read 4, iclass 18, count 0 2006.257.13:15:56.17#ibcon#about to read 5, iclass 18, count 0 2006.257.13:15:56.17#ibcon#read 5, iclass 18, count 0 2006.257.13:15:56.17#ibcon#about to read 6, iclass 18, count 0 2006.257.13:15:56.17#ibcon#read 6, iclass 18, count 0 2006.257.13:15:56.17#ibcon#end of sib2, iclass 18, count 0 2006.257.13:15:56.17#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:15:56.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:15:56.17#ibcon#[25=USB\r\n] 2006.257.13:15:56.17#ibcon#*before write, iclass 18, count 0 2006.257.13:15:56.17#ibcon#enter sib2, iclass 18, count 0 2006.257.13:15:56.17#ibcon#flushed, iclass 18, count 0 2006.257.13:15:56.17#ibcon#about to write, iclass 18, count 0 2006.257.13:15:56.17#ibcon#wrote, iclass 18, count 0 2006.257.13:15:56.17#ibcon#about to read 3, iclass 18, count 0 2006.257.13:15:56.20#ibcon#read 3, iclass 18, count 0 2006.257.13:15:56.20#ibcon#about to read 4, iclass 18, count 0 2006.257.13:15:56.20#ibcon#read 4, iclass 18, count 0 2006.257.13:15:56.20#ibcon#about to read 5, iclass 18, count 0 2006.257.13:15:56.20#ibcon#read 5, iclass 18, count 0 2006.257.13:15:56.20#ibcon#about to read 6, iclass 18, count 0 2006.257.13:15:56.20#ibcon#read 6, iclass 18, count 0 2006.257.13:15:56.20#ibcon#end of sib2, iclass 18, count 0 2006.257.13:15:56.20#ibcon#*after write, iclass 18, count 0 2006.257.13:15:56.20#ibcon#*before return 0, iclass 18, count 0 2006.257.13:15:56.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:15:56.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:15:56.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:15:56.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:15:56.21$vck44/valo=4,624.99 2006.257.13:15:56.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.13:15:56.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.13:15:56.21#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:56.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:56.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:56.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:56.21#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:15:56.21#ibcon#first serial, iclass 20, count 0 2006.257.13:15:56.21#ibcon#enter sib2, iclass 20, count 0 2006.257.13:15:56.21#ibcon#flushed, iclass 20, count 0 2006.257.13:15:56.21#ibcon#about to write, iclass 20, count 0 2006.257.13:15:56.21#ibcon#wrote, iclass 20, count 0 2006.257.13:15:56.21#ibcon#about to read 3, iclass 20, count 0 2006.257.13:15:56.22#ibcon#read 3, iclass 20, count 0 2006.257.13:15:56.22#ibcon#about to read 4, iclass 20, count 0 2006.257.13:15:56.22#ibcon#read 4, iclass 20, count 0 2006.257.13:15:56.22#ibcon#about to read 5, iclass 20, count 0 2006.257.13:15:56.22#ibcon#read 5, iclass 20, count 0 2006.257.13:15:56.22#ibcon#about to read 6, iclass 20, count 0 2006.257.13:15:56.22#ibcon#read 6, iclass 20, count 0 2006.257.13:15:56.22#ibcon#end of sib2, iclass 20, count 0 2006.257.13:15:56.22#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:15:56.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:15:56.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:15:56.22#ibcon#*before write, iclass 20, count 0 2006.257.13:15:56.22#ibcon#enter sib2, iclass 20, count 0 2006.257.13:15:56.22#ibcon#flushed, iclass 20, count 0 2006.257.13:15:56.22#ibcon#about to write, iclass 20, count 0 2006.257.13:15:56.22#ibcon#wrote, iclass 20, count 0 2006.257.13:15:56.22#ibcon#about to read 3, iclass 20, count 0 2006.257.13:15:56.26#ibcon#read 3, iclass 20, count 0 2006.257.13:15:56.26#ibcon#about to read 4, iclass 20, count 0 2006.257.13:15:56.26#ibcon#read 4, iclass 20, count 0 2006.257.13:15:56.26#ibcon#about to read 5, iclass 20, count 0 2006.257.13:15:56.26#ibcon#read 5, iclass 20, count 0 2006.257.13:15:56.26#ibcon#about to read 6, iclass 20, count 0 2006.257.13:15:56.26#ibcon#read 6, iclass 20, count 0 2006.257.13:15:56.26#ibcon#end of sib2, iclass 20, count 0 2006.257.13:15:56.26#ibcon#*after write, iclass 20, count 0 2006.257.13:15:56.26#ibcon#*before return 0, iclass 20, count 0 2006.257.13:15:56.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:56.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:56.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:15:56.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:15:56.27$vck44/va=4,7 2006.257.13:15:56.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.13:15:56.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.13:15:56.27#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:56.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:56.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:56.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:56.31#ibcon#enter wrdev, iclass 22, count 2 2006.257.13:15:56.31#ibcon#first serial, iclass 22, count 2 2006.257.13:15:56.31#ibcon#enter sib2, iclass 22, count 2 2006.257.13:15:56.31#ibcon#flushed, iclass 22, count 2 2006.257.13:15:56.31#ibcon#about to write, iclass 22, count 2 2006.257.13:15:56.31#ibcon#wrote, iclass 22, count 2 2006.257.13:15:56.31#ibcon#about to read 3, iclass 22, count 2 2006.257.13:15:56.33#ibcon#read 3, iclass 22, count 2 2006.257.13:15:56.33#ibcon#about to read 4, iclass 22, count 2 2006.257.13:15:56.33#ibcon#read 4, iclass 22, count 2 2006.257.13:15:56.33#ibcon#about to read 5, iclass 22, count 2 2006.257.13:15:56.33#ibcon#read 5, iclass 22, count 2 2006.257.13:15:56.33#ibcon#about to read 6, iclass 22, count 2 2006.257.13:15:56.33#ibcon#read 6, iclass 22, count 2 2006.257.13:15:56.33#ibcon#end of sib2, iclass 22, count 2 2006.257.13:15:56.33#ibcon#*mode == 0, iclass 22, count 2 2006.257.13:15:56.33#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.13:15:56.33#ibcon#[25=AT04-07\r\n] 2006.257.13:15:56.33#ibcon#*before write, iclass 22, count 2 2006.257.13:15:56.33#ibcon#enter sib2, iclass 22, count 2 2006.257.13:15:56.33#ibcon#flushed, iclass 22, count 2 2006.257.13:15:56.33#ibcon#about to write, iclass 22, count 2 2006.257.13:15:56.33#ibcon#wrote, iclass 22, count 2 2006.257.13:15:56.33#ibcon#about to read 3, iclass 22, count 2 2006.257.13:15:56.36#ibcon#read 3, iclass 22, count 2 2006.257.13:15:56.36#ibcon#about to read 4, iclass 22, count 2 2006.257.13:15:56.36#ibcon#read 4, iclass 22, count 2 2006.257.13:15:56.36#ibcon#about to read 5, iclass 22, count 2 2006.257.13:15:56.36#ibcon#read 5, iclass 22, count 2 2006.257.13:15:56.36#ibcon#about to read 6, iclass 22, count 2 2006.257.13:15:56.36#ibcon#read 6, iclass 22, count 2 2006.257.13:15:56.36#ibcon#end of sib2, iclass 22, count 2 2006.257.13:15:56.36#ibcon#*after write, iclass 22, count 2 2006.257.13:15:56.41#ibcon#*before return 0, iclass 22, count 2 2006.257.13:15:56.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:56.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:56.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.13:15:56.41#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:56.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:56.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:56.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:56.52#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:15:56.52#ibcon#first serial, iclass 22, count 0 2006.257.13:15:56.52#ibcon#enter sib2, iclass 22, count 0 2006.257.13:15:56.52#ibcon#flushed, iclass 22, count 0 2006.257.13:15:56.52#ibcon#about to write, iclass 22, count 0 2006.257.13:15:56.52#ibcon#wrote, iclass 22, count 0 2006.257.13:15:56.52#ibcon#about to read 3, iclass 22, count 0 2006.257.13:15:56.54#ibcon#read 3, iclass 22, count 0 2006.257.13:15:56.54#ibcon#about to read 4, iclass 22, count 0 2006.257.13:15:56.54#ibcon#read 4, iclass 22, count 0 2006.257.13:15:56.54#ibcon#about to read 5, iclass 22, count 0 2006.257.13:15:56.54#ibcon#read 5, iclass 22, count 0 2006.257.13:15:56.54#ibcon#about to read 6, iclass 22, count 0 2006.257.13:15:56.54#ibcon#read 6, iclass 22, count 0 2006.257.13:15:56.54#ibcon#end of sib2, iclass 22, count 0 2006.257.13:15:56.54#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:15:56.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:15:56.54#ibcon#[25=USB\r\n] 2006.257.13:15:56.54#ibcon#*before write, iclass 22, count 0 2006.257.13:15:56.54#ibcon#enter sib2, iclass 22, count 0 2006.257.13:15:56.54#ibcon#flushed, iclass 22, count 0 2006.257.13:15:56.54#ibcon#about to write, iclass 22, count 0 2006.257.13:15:56.54#ibcon#wrote, iclass 22, count 0 2006.257.13:15:56.54#ibcon#about to read 3, iclass 22, count 0 2006.257.13:15:56.57#ibcon#read 3, iclass 22, count 0 2006.257.13:15:56.57#ibcon#about to read 4, iclass 22, count 0 2006.257.13:15:56.57#ibcon#read 4, iclass 22, count 0 2006.257.13:15:56.57#ibcon#about to read 5, iclass 22, count 0 2006.257.13:15:56.57#ibcon#read 5, iclass 22, count 0 2006.257.13:15:56.57#ibcon#about to read 6, iclass 22, count 0 2006.257.13:15:56.57#ibcon#read 6, iclass 22, count 0 2006.257.13:15:56.57#ibcon#end of sib2, iclass 22, count 0 2006.257.13:15:56.57#ibcon#*after write, iclass 22, count 0 2006.257.13:15:56.57#ibcon#*before return 0, iclass 22, count 0 2006.257.13:15:56.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:56.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:56.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:15:56.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:15:56.57$vck44/valo=5,734.99 2006.257.13:15:56.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.13:15:56.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.13:15:56.58#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:56.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:56.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:56.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:56.58#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:15:56.58#ibcon#first serial, iclass 24, count 0 2006.257.13:15:56.58#ibcon#enter sib2, iclass 24, count 0 2006.257.13:15:56.58#ibcon#flushed, iclass 24, count 0 2006.257.13:15:56.58#ibcon#about to write, iclass 24, count 0 2006.257.13:15:56.58#ibcon#wrote, iclass 24, count 0 2006.257.13:15:56.58#ibcon#about to read 3, iclass 24, count 0 2006.257.13:15:56.59#ibcon#read 3, iclass 24, count 0 2006.257.13:15:56.59#ibcon#about to read 4, iclass 24, count 0 2006.257.13:15:56.59#ibcon#read 4, iclass 24, count 0 2006.257.13:15:56.59#ibcon#about to read 5, iclass 24, count 0 2006.257.13:15:56.59#ibcon#read 5, iclass 24, count 0 2006.257.13:15:56.59#ibcon#about to read 6, iclass 24, count 0 2006.257.13:15:56.59#ibcon#read 6, iclass 24, count 0 2006.257.13:15:56.59#ibcon#end of sib2, iclass 24, count 0 2006.257.13:15:56.59#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:15:56.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:15:56.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:15:56.59#ibcon#*before write, iclass 24, count 0 2006.257.13:15:56.59#ibcon#enter sib2, iclass 24, count 0 2006.257.13:15:56.59#ibcon#flushed, iclass 24, count 0 2006.257.13:15:56.59#ibcon#about to write, iclass 24, count 0 2006.257.13:15:56.59#ibcon#wrote, iclass 24, count 0 2006.257.13:15:56.59#ibcon#about to read 3, iclass 24, count 0 2006.257.13:15:56.63#ibcon#read 3, iclass 24, count 0 2006.257.13:15:56.63#ibcon#about to read 4, iclass 24, count 0 2006.257.13:15:56.63#ibcon#read 4, iclass 24, count 0 2006.257.13:15:56.63#ibcon#about to read 5, iclass 24, count 0 2006.257.13:15:56.63#ibcon#read 5, iclass 24, count 0 2006.257.13:15:56.63#ibcon#about to read 6, iclass 24, count 0 2006.257.13:15:56.63#ibcon#read 6, iclass 24, count 0 2006.257.13:15:56.63#ibcon#end of sib2, iclass 24, count 0 2006.257.13:15:56.63#ibcon#*after write, iclass 24, count 0 2006.257.13:15:56.63#ibcon#*before return 0, iclass 24, count 0 2006.257.13:15:56.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:56.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:56.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:15:56.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:15:56.64$vck44/va=5,4 2006.257.13:15:56.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.13:15:56.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.13:15:56.64#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:56.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:56.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:56.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:56.68#ibcon#enter wrdev, iclass 26, count 2 2006.257.13:15:56.68#ibcon#first serial, iclass 26, count 2 2006.257.13:15:56.68#ibcon#enter sib2, iclass 26, count 2 2006.257.13:15:56.68#ibcon#flushed, iclass 26, count 2 2006.257.13:15:56.68#ibcon#about to write, iclass 26, count 2 2006.257.13:15:56.68#ibcon#wrote, iclass 26, count 2 2006.257.13:15:56.68#ibcon#about to read 3, iclass 26, count 2 2006.257.13:15:56.70#ibcon#read 3, iclass 26, count 2 2006.257.13:15:56.70#ibcon#about to read 4, iclass 26, count 2 2006.257.13:15:56.70#ibcon#read 4, iclass 26, count 2 2006.257.13:15:56.70#ibcon#about to read 5, iclass 26, count 2 2006.257.13:15:56.70#ibcon#read 5, iclass 26, count 2 2006.257.13:15:56.70#ibcon#about to read 6, iclass 26, count 2 2006.257.13:15:56.70#ibcon#read 6, iclass 26, count 2 2006.257.13:15:56.70#ibcon#end of sib2, iclass 26, count 2 2006.257.13:15:56.70#ibcon#*mode == 0, iclass 26, count 2 2006.257.13:15:56.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.13:15:56.70#ibcon#[25=AT05-04\r\n] 2006.257.13:15:56.70#ibcon#*before write, iclass 26, count 2 2006.257.13:15:56.70#ibcon#enter sib2, iclass 26, count 2 2006.257.13:15:56.70#ibcon#flushed, iclass 26, count 2 2006.257.13:15:56.70#ibcon#about to write, iclass 26, count 2 2006.257.13:15:56.70#ibcon#wrote, iclass 26, count 2 2006.257.13:15:56.70#ibcon#about to read 3, iclass 26, count 2 2006.257.13:15:56.73#ibcon#read 3, iclass 26, count 2 2006.257.13:15:56.73#ibcon#about to read 4, iclass 26, count 2 2006.257.13:15:56.73#ibcon#read 4, iclass 26, count 2 2006.257.13:15:56.73#ibcon#about to read 5, iclass 26, count 2 2006.257.13:15:56.73#ibcon#read 5, iclass 26, count 2 2006.257.13:15:56.73#ibcon#about to read 6, iclass 26, count 2 2006.257.13:15:56.73#ibcon#read 6, iclass 26, count 2 2006.257.13:15:56.73#ibcon#end of sib2, iclass 26, count 2 2006.257.13:15:56.73#ibcon#*after write, iclass 26, count 2 2006.257.13:15:56.73#ibcon#*before return 0, iclass 26, count 2 2006.257.13:15:56.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:56.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:56.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.13:15:56.73#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:56.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:56.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:56.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:56.85#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:15:56.85#ibcon#first serial, iclass 26, count 0 2006.257.13:15:56.85#ibcon#enter sib2, iclass 26, count 0 2006.257.13:15:56.85#ibcon#flushed, iclass 26, count 0 2006.257.13:15:56.85#ibcon#about to write, iclass 26, count 0 2006.257.13:15:56.85#ibcon#wrote, iclass 26, count 0 2006.257.13:15:56.85#ibcon#about to read 3, iclass 26, count 0 2006.257.13:15:56.87#ibcon#read 3, iclass 26, count 0 2006.257.13:15:56.87#ibcon#about to read 4, iclass 26, count 0 2006.257.13:15:56.87#ibcon#read 4, iclass 26, count 0 2006.257.13:15:56.87#ibcon#about to read 5, iclass 26, count 0 2006.257.13:15:56.87#ibcon#read 5, iclass 26, count 0 2006.257.13:15:56.87#ibcon#about to read 6, iclass 26, count 0 2006.257.13:15:56.87#ibcon#read 6, iclass 26, count 0 2006.257.13:15:56.87#ibcon#end of sib2, iclass 26, count 0 2006.257.13:15:56.87#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:15:56.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:15:56.87#ibcon#[25=USB\r\n] 2006.257.13:15:56.87#ibcon#*before write, iclass 26, count 0 2006.257.13:15:56.87#ibcon#enter sib2, iclass 26, count 0 2006.257.13:15:56.87#ibcon#flushed, iclass 26, count 0 2006.257.13:15:56.87#ibcon#about to write, iclass 26, count 0 2006.257.13:15:56.87#ibcon#wrote, iclass 26, count 0 2006.257.13:15:56.87#ibcon#about to read 3, iclass 26, count 0 2006.257.13:15:56.90#ibcon#read 3, iclass 26, count 0 2006.257.13:15:56.90#ibcon#about to read 4, iclass 26, count 0 2006.257.13:15:56.90#ibcon#read 4, iclass 26, count 0 2006.257.13:15:56.90#ibcon#about to read 5, iclass 26, count 0 2006.257.13:15:56.90#ibcon#read 5, iclass 26, count 0 2006.257.13:15:56.90#ibcon#about to read 6, iclass 26, count 0 2006.257.13:15:56.90#ibcon#read 6, iclass 26, count 0 2006.257.13:15:56.90#ibcon#end of sib2, iclass 26, count 0 2006.257.13:15:56.90#ibcon#*after write, iclass 26, count 0 2006.257.13:15:56.90#ibcon#*before return 0, iclass 26, count 0 2006.257.13:15:56.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:56.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:56.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:15:56.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:15:56.91$vck44/valo=6,814.99 2006.257.13:15:56.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.13:15:56.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.13:15:56.91#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:56.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:56.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:56.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:56.91#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:15:56.91#ibcon#first serial, iclass 28, count 0 2006.257.13:15:56.91#ibcon#enter sib2, iclass 28, count 0 2006.257.13:15:56.91#ibcon#flushed, iclass 28, count 0 2006.257.13:15:56.91#ibcon#about to write, iclass 28, count 0 2006.257.13:15:56.91#ibcon#wrote, iclass 28, count 0 2006.257.13:15:56.91#ibcon#about to read 3, iclass 28, count 0 2006.257.13:15:56.92#ibcon#read 3, iclass 28, count 0 2006.257.13:15:56.92#ibcon#about to read 4, iclass 28, count 0 2006.257.13:15:56.92#ibcon#read 4, iclass 28, count 0 2006.257.13:15:56.92#ibcon#about to read 5, iclass 28, count 0 2006.257.13:15:56.92#ibcon#read 5, iclass 28, count 0 2006.257.13:15:56.92#ibcon#about to read 6, iclass 28, count 0 2006.257.13:15:56.92#ibcon#read 6, iclass 28, count 0 2006.257.13:15:56.92#ibcon#end of sib2, iclass 28, count 0 2006.257.13:15:56.92#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:15:56.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:15:56.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:15:56.92#ibcon#*before write, iclass 28, count 0 2006.257.13:15:56.92#ibcon#enter sib2, iclass 28, count 0 2006.257.13:15:56.92#ibcon#flushed, iclass 28, count 0 2006.257.13:15:56.92#ibcon#about to write, iclass 28, count 0 2006.257.13:15:56.92#ibcon#wrote, iclass 28, count 0 2006.257.13:15:56.92#ibcon#about to read 3, iclass 28, count 0 2006.257.13:15:56.96#ibcon#read 3, iclass 28, count 0 2006.257.13:15:56.96#ibcon#about to read 4, iclass 28, count 0 2006.257.13:15:56.96#ibcon#read 4, iclass 28, count 0 2006.257.13:15:56.96#ibcon#about to read 5, iclass 28, count 0 2006.257.13:15:56.96#ibcon#read 5, iclass 28, count 0 2006.257.13:15:56.96#ibcon#about to read 6, iclass 28, count 0 2006.257.13:15:56.96#ibcon#read 6, iclass 28, count 0 2006.257.13:15:56.96#ibcon#end of sib2, iclass 28, count 0 2006.257.13:15:56.96#ibcon#*after write, iclass 28, count 0 2006.257.13:15:56.96#ibcon#*before return 0, iclass 28, count 0 2006.257.13:15:56.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:56.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:56.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:15:56.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:15:56.97$vck44/va=6,4 2006.257.13:15:56.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.13:15:56.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.13:15:56.97#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:56.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:57.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:57.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:57.02#ibcon#enter wrdev, iclass 30, count 2 2006.257.13:15:57.02#ibcon#first serial, iclass 30, count 2 2006.257.13:15:57.02#ibcon#enter sib2, iclass 30, count 2 2006.257.13:15:57.02#ibcon#flushed, iclass 30, count 2 2006.257.13:15:57.02#ibcon#about to write, iclass 30, count 2 2006.257.13:15:57.02#ibcon#wrote, iclass 30, count 2 2006.257.13:15:57.02#ibcon#about to read 3, iclass 30, count 2 2006.257.13:15:57.03#ibcon#read 3, iclass 30, count 2 2006.257.13:15:57.03#ibcon#about to read 4, iclass 30, count 2 2006.257.13:15:57.03#ibcon#read 4, iclass 30, count 2 2006.257.13:15:57.03#ibcon#about to read 5, iclass 30, count 2 2006.257.13:15:57.03#ibcon#read 5, iclass 30, count 2 2006.257.13:15:57.03#ibcon#about to read 6, iclass 30, count 2 2006.257.13:15:57.03#ibcon#read 6, iclass 30, count 2 2006.257.13:15:57.03#ibcon#end of sib2, iclass 30, count 2 2006.257.13:15:57.03#ibcon#*mode == 0, iclass 30, count 2 2006.257.13:15:57.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.13:15:57.03#ibcon#[25=AT06-04\r\n] 2006.257.13:15:57.03#ibcon#*before write, iclass 30, count 2 2006.257.13:15:57.03#ibcon#enter sib2, iclass 30, count 2 2006.257.13:15:57.03#ibcon#flushed, iclass 30, count 2 2006.257.13:15:57.03#ibcon#about to write, iclass 30, count 2 2006.257.13:15:57.03#ibcon#wrote, iclass 30, count 2 2006.257.13:15:57.03#ibcon#about to read 3, iclass 30, count 2 2006.257.13:15:57.06#ibcon#read 3, iclass 30, count 2 2006.257.13:15:57.06#ibcon#about to read 4, iclass 30, count 2 2006.257.13:15:57.06#ibcon#read 4, iclass 30, count 2 2006.257.13:15:57.06#ibcon#about to read 5, iclass 30, count 2 2006.257.13:15:57.06#ibcon#read 5, iclass 30, count 2 2006.257.13:15:57.06#ibcon#about to read 6, iclass 30, count 2 2006.257.13:15:57.06#ibcon#read 6, iclass 30, count 2 2006.257.13:15:57.06#ibcon#end of sib2, iclass 30, count 2 2006.257.13:15:57.06#ibcon#*after write, iclass 30, count 2 2006.257.13:15:57.06#ibcon#*before return 0, iclass 30, count 2 2006.257.13:15:57.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:57.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:57.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.13:15:57.06#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:57.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:15:57.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:15:57.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:15:57.18#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:15:57.18#ibcon#first serial, iclass 30, count 0 2006.257.13:15:57.18#ibcon#enter sib2, iclass 30, count 0 2006.257.13:15:57.18#ibcon#flushed, iclass 30, count 0 2006.257.13:15:57.18#ibcon#about to write, iclass 30, count 0 2006.257.13:15:57.18#ibcon#wrote, iclass 30, count 0 2006.257.13:15:57.18#ibcon#about to read 3, iclass 30, count 0 2006.257.13:15:57.20#ibcon#read 3, iclass 30, count 0 2006.257.13:15:57.20#ibcon#about to read 4, iclass 30, count 0 2006.257.13:15:57.20#ibcon#read 4, iclass 30, count 0 2006.257.13:15:57.20#ibcon#about to read 5, iclass 30, count 0 2006.257.13:15:57.20#ibcon#read 5, iclass 30, count 0 2006.257.13:15:57.20#ibcon#about to read 6, iclass 30, count 0 2006.257.13:15:57.20#ibcon#read 6, iclass 30, count 0 2006.257.13:15:57.20#ibcon#end of sib2, iclass 30, count 0 2006.257.13:15:57.20#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:15:57.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:15:57.20#ibcon#[25=USB\r\n] 2006.257.13:15:57.20#ibcon#*before write, iclass 30, count 0 2006.257.13:15:57.20#ibcon#enter sib2, iclass 30, count 0 2006.257.13:15:57.20#ibcon#flushed, iclass 30, count 0 2006.257.13:15:57.20#ibcon#about to write, iclass 30, count 0 2006.257.13:15:57.20#ibcon#wrote, iclass 30, count 0 2006.257.13:15:57.20#ibcon#about to read 3, iclass 30, count 0 2006.257.13:15:57.23#ibcon#read 3, iclass 30, count 0 2006.257.13:15:57.23#ibcon#about to read 4, iclass 30, count 0 2006.257.13:15:57.23#ibcon#read 4, iclass 30, count 0 2006.257.13:15:57.23#ibcon#about to read 5, iclass 30, count 0 2006.257.13:15:57.23#ibcon#read 5, iclass 30, count 0 2006.257.13:15:57.23#ibcon#about to read 6, iclass 30, count 0 2006.257.13:15:57.23#ibcon#read 6, iclass 30, count 0 2006.257.13:15:57.23#ibcon#end of sib2, iclass 30, count 0 2006.257.13:15:57.23#ibcon#*after write, iclass 30, count 0 2006.257.13:15:57.23#ibcon#*before return 0, iclass 30, count 0 2006.257.13:15:57.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:15:57.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:15:57.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:15:57.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:15:57.24$vck44/valo=7,864.99 2006.257.13:15:57.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.13:15:57.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.13:15:57.24#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:57.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:15:57.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:15:57.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:15:57.24#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:15:57.24#ibcon#first serial, iclass 32, count 0 2006.257.13:15:57.24#ibcon#enter sib2, iclass 32, count 0 2006.257.13:15:57.24#ibcon#flushed, iclass 32, count 0 2006.257.13:15:57.24#ibcon#about to write, iclass 32, count 0 2006.257.13:15:57.24#ibcon#wrote, iclass 32, count 0 2006.257.13:15:57.24#ibcon#about to read 3, iclass 32, count 0 2006.257.13:15:57.25#ibcon#read 3, iclass 32, count 0 2006.257.13:15:57.25#ibcon#about to read 4, iclass 32, count 0 2006.257.13:15:57.25#ibcon#read 4, iclass 32, count 0 2006.257.13:15:57.25#ibcon#about to read 5, iclass 32, count 0 2006.257.13:15:57.25#ibcon#read 5, iclass 32, count 0 2006.257.13:15:57.25#ibcon#about to read 6, iclass 32, count 0 2006.257.13:15:57.25#ibcon#read 6, iclass 32, count 0 2006.257.13:15:57.25#ibcon#end of sib2, iclass 32, count 0 2006.257.13:15:57.25#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:15:57.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:15:57.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:15:57.25#ibcon#*before write, iclass 32, count 0 2006.257.13:15:57.25#ibcon#enter sib2, iclass 32, count 0 2006.257.13:15:57.25#ibcon#flushed, iclass 32, count 0 2006.257.13:15:57.25#ibcon#about to write, iclass 32, count 0 2006.257.13:15:57.25#ibcon#wrote, iclass 32, count 0 2006.257.13:15:57.25#ibcon#about to read 3, iclass 32, count 0 2006.257.13:15:57.29#ibcon#read 3, iclass 32, count 0 2006.257.13:15:57.29#ibcon#about to read 4, iclass 32, count 0 2006.257.13:15:57.29#ibcon#read 4, iclass 32, count 0 2006.257.13:15:57.29#ibcon#about to read 5, iclass 32, count 0 2006.257.13:15:57.29#ibcon#read 5, iclass 32, count 0 2006.257.13:15:57.29#ibcon#about to read 6, iclass 32, count 0 2006.257.13:15:57.29#ibcon#read 6, iclass 32, count 0 2006.257.13:15:57.29#ibcon#end of sib2, iclass 32, count 0 2006.257.13:15:57.29#ibcon#*after write, iclass 32, count 0 2006.257.13:15:57.29#ibcon#*before return 0, iclass 32, count 0 2006.257.13:15:57.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:15:57.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:15:57.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:15:57.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:15:57.30$vck44/va=7,4 2006.257.13:15:57.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.13:15:57.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.13:15:57.30#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:57.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:15:57.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:15:57.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:15:57.34#ibcon#enter wrdev, iclass 34, count 2 2006.257.13:15:57.34#ibcon#first serial, iclass 34, count 2 2006.257.13:15:57.34#ibcon#enter sib2, iclass 34, count 2 2006.257.13:15:57.34#ibcon#flushed, iclass 34, count 2 2006.257.13:15:57.34#ibcon#about to write, iclass 34, count 2 2006.257.13:15:57.34#ibcon#wrote, iclass 34, count 2 2006.257.13:15:57.34#ibcon#about to read 3, iclass 34, count 2 2006.257.13:15:57.36#ibcon#read 3, iclass 34, count 2 2006.257.13:15:57.36#ibcon#about to read 4, iclass 34, count 2 2006.257.13:15:57.36#ibcon#read 4, iclass 34, count 2 2006.257.13:15:57.36#ibcon#about to read 5, iclass 34, count 2 2006.257.13:15:57.36#ibcon#read 5, iclass 34, count 2 2006.257.13:15:57.36#ibcon#about to read 6, iclass 34, count 2 2006.257.13:15:57.36#ibcon#read 6, iclass 34, count 2 2006.257.13:15:57.36#ibcon#end of sib2, iclass 34, count 2 2006.257.13:15:57.36#ibcon#*mode == 0, iclass 34, count 2 2006.257.13:15:57.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.13:15:57.36#ibcon#[25=AT07-04\r\n] 2006.257.13:15:57.36#ibcon#*before write, iclass 34, count 2 2006.257.13:15:57.36#ibcon#enter sib2, iclass 34, count 2 2006.257.13:15:57.36#ibcon#flushed, iclass 34, count 2 2006.257.13:15:57.36#ibcon#about to write, iclass 34, count 2 2006.257.13:15:57.36#ibcon#wrote, iclass 34, count 2 2006.257.13:15:57.36#ibcon#about to read 3, iclass 34, count 2 2006.257.13:15:57.39#ibcon#read 3, iclass 34, count 2 2006.257.13:15:57.45#ibcon#about to read 4, iclass 34, count 2 2006.257.13:15:57.45#ibcon#read 4, iclass 34, count 2 2006.257.13:15:57.45#ibcon#about to read 5, iclass 34, count 2 2006.257.13:15:57.45#ibcon#read 5, iclass 34, count 2 2006.257.13:15:57.45#ibcon#about to read 6, iclass 34, count 2 2006.257.13:15:57.45#ibcon#read 6, iclass 34, count 2 2006.257.13:15:57.45#ibcon#end of sib2, iclass 34, count 2 2006.257.13:15:57.45#ibcon#*after write, iclass 34, count 2 2006.257.13:15:57.45#ibcon#*before return 0, iclass 34, count 2 2006.257.13:15:57.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:15:57.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:15:57.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.13:15:57.45#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:57.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:15:57.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:15:57.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:15:57.57#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:15:57.57#ibcon#first serial, iclass 34, count 0 2006.257.13:15:57.57#ibcon#enter sib2, iclass 34, count 0 2006.257.13:15:57.57#ibcon#flushed, iclass 34, count 0 2006.257.13:15:57.57#ibcon#about to write, iclass 34, count 0 2006.257.13:15:57.57#ibcon#wrote, iclass 34, count 0 2006.257.13:15:57.57#ibcon#about to read 3, iclass 34, count 0 2006.257.13:15:57.59#ibcon#read 3, iclass 34, count 0 2006.257.13:15:57.59#ibcon#about to read 4, iclass 34, count 0 2006.257.13:15:57.59#ibcon#read 4, iclass 34, count 0 2006.257.13:15:57.59#ibcon#about to read 5, iclass 34, count 0 2006.257.13:15:57.59#ibcon#read 5, iclass 34, count 0 2006.257.13:15:57.59#ibcon#about to read 6, iclass 34, count 0 2006.257.13:15:57.59#ibcon#read 6, iclass 34, count 0 2006.257.13:15:57.59#ibcon#end of sib2, iclass 34, count 0 2006.257.13:15:57.59#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:15:57.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:15:57.59#ibcon#[25=USB\r\n] 2006.257.13:15:57.59#ibcon#*before write, iclass 34, count 0 2006.257.13:15:57.59#ibcon#enter sib2, iclass 34, count 0 2006.257.13:15:57.59#ibcon#flushed, iclass 34, count 0 2006.257.13:15:57.59#ibcon#about to write, iclass 34, count 0 2006.257.13:15:57.59#ibcon#wrote, iclass 34, count 0 2006.257.13:15:57.59#ibcon#about to read 3, iclass 34, count 0 2006.257.13:15:57.62#ibcon#read 3, iclass 34, count 0 2006.257.13:15:57.62#ibcon#about to read 4, iclass 34, count 0 2006.257.13:15:57.62#ibcon#read 4, iclass 34, count 0 2006.257.13:15:57.62#ibcon#about to read 5, iclass 34, count 0 2006.257.13:15:57.62#ibcon#read 5, iclass 34, count 0 2006.257.13:15:57.62#ibcon#about to read 6, iclass 34, count 0 2006.257.13:15:57.62#ibcon#read 6, iclass 34, count 0 2006.257.13:15:57.62#ibcon#end of sib2, iclass 34, count 0 2006.257.13:15:57.62#ibcon#*after write, iclass 34, count 0 2006.257.13:15:57.62#ibcon#*before return 0, iclass 34, count 0 2006.257.13:15:57.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:15:57.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:15:57.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:15:57.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:15:57.63$vck44/valo=8,884.99 2006.257.13:15:57.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.13:15:57.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.13:15:57.63#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:57.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:15:57.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:15:57.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:15:57.63#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:15:57.63#ibcon#first serial, iclass 36, count 0 2006.257.13:15:57.63#ibcon#enter sib2, iclass 36, count 0 2006.257.13:15:57.63#ibcon#flushed, iclass 36, count 0 2006.257.13:15:57.63#ibcon#about to write, iclass 36, count 0 2006.257.13:15:57.63#ibcon#wrote, iclass 36, count 0 2006.257.13:15:57.63#ibcon#about to read 3, iclass 36, count 0 2006.257.13:15:57.64#ibcon#read 3, iclass 36, count 0 2006.257.13:15:57.64#ibcon#about to read 4, iclass 36, count 0 2006.257.13:15:57.64#ibcon#read 4, iclass 36, count 0 2006.257.13:15:57.64#ibcon#about to read 5, iclass 36, count 0 2006.257.13:15:57.64#ibcon#read 5, iclass 36, count 0 2006.257.13:15:57.64#ibcon#about to read 6, iclass 36, count 0 2006.257.13:15:57.64#ibcon#read 6, iclass 36, count 0 2006.257.13:15:57.64#ibcon#end of sib2, iclass 36, count 0 2006.257.13:15:57.64#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:15:57.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:15:57.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:15:57.64#ibcon#*before write, iclass 36, count 0 2006.257.13:15:57.64#ibcon#enter sib2, iclass 36, count 0 2006.257.13:15:57.64#ibcon#flushed, iclass 36, count 0 2006.257.13:15:57.64#ibcon#about to write, iclass 36, count 0 2006.257.13:15:57.64#ibcon#wrote, iclass 36, count 0 2006.257.13:15:57.64#ibcon#about to read 3, iclass 36, count 0 2006.257.13:15:57.68#ibcon#read 3, iclass 36, count 0 2006.257.13:15:57.68#ibcon#about to read 4, iclass 36, count 0 2006.257.13:15:57.68#ibcon#read 4, iclass 36, count 0 2006.257.13:15:57.68#ibcon#about to read 5, iclass 36, count 0 2006.257.13:15:57.68#ibcon#read 5, iclass 36, count 0 2006.257.13:15:57.68#ibcon#about to read 6, iclass 36, count 0 2006.257.13:15:57.68#ibcon#read 6, iclass 36, count 0 2006.257.13:15:57.68#ibcon#end of sib2, iclass 36, count 0 2006.257.13:15:57.68#ibcon#*after write, iclass 36, count 0 2006.257.13:15:57.68#ibcon#*before return 0, iclass 36, count 0 2006.257.13:15:57.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:15:57.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:15:57.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:15:57.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:15:57.69$vck44/va=8,4 2006.257.13:15:57.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.13:15:57.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.13:15:57.69#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:57.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:15:57.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:15:57.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:15:57.73#ibcon#enter wrdev, iclass 38, count 2 2006.257.13:15:57.73#ibcon#first serial, iclass 38, count 2 2006.257.13:15:57.73#ibcon#enter sib2, iclass 38, count 2 2006.257.13:15:57.73#ibcon#flushed, iclass 38, count 2 2006.257.13:15:57.73#ibcon#about to write, iclass 38, count 2 2006.257.13:15:57.73#ibcon#wrote, iclass 38, count 2 2006.257.13:15:57.73#ibcon#about to read 3, iclass 38, count 2 2006.257.13:15:57.75#ibcon#read 3, iclass 38, count 2 2006.257.13:15:57.75#ibcon#about to read 4, iclass 38, count 2 2006.257.13:15:57.75#ibcon#read 4, iclass 38, count 2 2006.257.13:15:57.75#ibcon#about to read 5, iclass 38, count 2 2006.257.13:15:57.75#ibcon#read 5, iclass 38, count 2 2006.257.13:15:57.75#ibcon#about to read 6, iclass 38, count 2 2006.257.13:15:57.75#ibcon#read 6, iclass 38, count 2 2006.257.13:15:57.75#ibcon#end of sib2, iclass 38, count 2 2006.257.13:15:57.75#ibcon#*mode == 0, iclass 38, count 2 2006.257.13:15:57.75#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.13:15:57.75#ibcon#[25=AT08-04\r\n] 2006.257.13:15:57.75#ibcon#*before write, iclass 38, count 2 2006.257.13:15:57.75#ibcon#enter sib2, iclass 38, count 2 2006.257.13:15:57.75#ibcon#flushed, iclass 38, count 2 2006.257.13:15:57.75#ibcon#about to write, iclass 38, count 2 2006.257.13:15:57.75#ibcon#wrote, iclass 38, count 2 2006.257.13:15:57.75#ibcon#about to read 3, iclass 38, count 2 2006.257.13:15:57.78#ibcon#read 3, iclass 38, count 2 2006.257.13:15:57.78#ibcon#about to read 4, iclass 38, count 2 2006.257.13:15:57.78#ibcon#read 4, iclass 38, count 2 2006.257.13:15:57.78#ibcon#about to read 5, iclass 38, count 2 2006.257.13:15:57.78#ibcon#read 5, iclass 38, count 2 2006.257.13:15:57.78#ibcon#about to read 6, iclass 38, count 2 2006.257.13:15:57.78#ibcon#read 6, iclass 38, count 2 2006.257.13:15:57.78#ibcon#end of sib2, iclass 38, count 2 2006.257.13:15:57.78#ibcon#*after write, iclass 38, count 2 2006.257.13:15:57.78#ibcon#*before return 0, iclass 38, count 2 2006.257.13:15:57.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:15:57.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:15:57.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.13:15:57.78#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:57.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:15:57.90#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:15:57.90#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:15:57.90#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:15:57.90#ibcon#first serial, iclass 38, count 0 2006.257.13:15:57.90#ibcon#enter sib2, iclass 38, count 0 2006.257.13:15:57.90#ibcon#flushed, iclass 38, count 0 2006.257.13:15:57.90#ibcon#about to write, iclass 38, count 0 2006.257.13:15:57.90#ibcon#wrote, iclass 38, count 0 2006.257.13:15:57.90#ibcon#about to read 3, iclass 38, count 0 2006.257.13:15:57.92#ibcon#read 3, iclass 38, count 0 2006.257.13:15:57.92#ibcon#about to read 4, iclass 38, count 0 2006.257.13:15:57.92#ibcon#read 4, iclass 38, count 0 2006.257.13:15:57.92#ibcon#about to read 5, iclass 38, count 0 2006.257.13:15:57.92#ibcon#read 5, iclass 38, count 0 2006.257.13:15:57.92#ibcon#about to read 6, iclass 38, count 0 2006.257.13:15:57.92#ibcon#read 6, iclass 38, count 0 2006.257.13:15:57.92#ibcon#end of sib2, iclass 38, count 0 2006.257.13:15:57.92#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:15:57.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:15:57.92#ibcon#[25=USB\r\n] 2006.257.13:15:57.92#ibcon#*before write, iclass 38, count 0 2006.257.13:15:57.92#ibcon#enter sib2, iclass 38, count 0 2006.257.13:15:57.92#ibcon#flushed, iclass 38, count 0 2006.257.13:15:57.92#ibcon#about to write, iclass 38, count 0 2006.257.13:15:57.92#ibcon#wrote, iclass 38, count 0 2006.257.13:15:57.92#ibcon#about to read 3, iclass 38, count 0 2006.257.13:15:57.95#ibcon#read 3, iclass 38, count 0 2006.257.13:15:57.95#ibcon#about to read 4, iclass 38, count 0 2006.257.13:15:57.95#ibcon#read 4, iclass 38, count 0 2006.257.13:15:57.95#ibcon#about to read 5, iclass 38, count 0 2006.257.13:15:57.95#ibcon#read 5, iclass 38, count 0 2006.257.13:15:57.95#ibcon#about to read 6, iclass 38, count 0 2006.257.13:15:57.95#ibcon#read 6, iclass 38, count 0 2006.257.13:15:57.95#ibcon#end of sib2, iclass 38, count 0 2006.257.13:15:57.95#ibcon#*after write, iclass 38, count 0 2006.257.13:15:57.95#ibcon#*before return 0, iclass 38, count 0 2006.257.13:15:57.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:15:57.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:15:57.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:15:57.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:15:57.95$vck44/vblo=1,629.99 2006.257.13:15:57.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.13:15:57.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.13:15:57.96#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:57.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:15:57.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:15:57.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:15:57.96#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:15:57.96#ibcon#first serial, iclass 40, count 0 2006.257.13:15:57.96#ibcon#enter sib2, iclass 40, count 0 2006.257.13:15:57.96#ibcon#flushed, iclass 40, count 0 2006.257.13:15:57.96#ibcon#about to write, iclass 40, count 0 2006.257.13:15:57.96#ibcon#wrote, iclass 40, count 0 2006.257.13:15:57.96#ibcon#about to read 3, iclass 40, count 0 2006.257.13:15:57.97#ibcon#read 3, iclass 40, count 0 2006.257.13:15:57.97#ibcon#about to read 4, iclass 40, count 0 2006.257.13:15:57.97#ibcon#read 4, iclass 40, count 0 2006.257.13:15:57.97#ibcon#about to read 5, iclass 40, count 0 2006.257.13:15:57.97#ibcon#read 5, iclass 40, count 0 2006.257.13:15:57.97#ibcon#about to read 6, iclass 40, count 0 2006.257.13:15:57.97#ibcon#read 6, iclass 40, count 0 2006.257.13:15:57.97#ibcon#end of sib2, iclass 40, count 0 2006.257.13:15:57.97#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:15:57.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:15:57.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:15:57.97#ibcon#*before write, iclass 40, count 0 2006.257.13:15:57.97#ibcon#enter sib2, iclass 40, count 0 2006.257.13:15:57.97#ibcon#flushed, iclass 40, count 0 2006.257.13:15:57.97#ibcon#about to write, iclass 40, count 0 2006.257.13:15:57.97#ibcon#wrote, iclass 40, count 0 2006.257.13:15:57.97#ibcon#about to read 3, iclass 40, count 0 2006.257.13:15:58.01#ibcon#read 3, iclass 40, count 0 2006.257.13:15:58.01#ibcon#about to read 4, iclass 40, count 0 2006.257.13:15:58.01#ibcon#read 4, iclass 40, count 0 2006.257.13:15:58.01#ibcon#about to read 5, iclass 40, count 0 2006.257.13:15:58.01#ibcon#read 5, iclass 40, count 0 2006.257.13:15:58.01#ibcon#about to read 6, iclass 40, count 0 2006.257.13:15:58.01#ibcon#read 6, iclass 40, count 0 2006.257.13:15:58.01#ibcon#end of sib2, iclass 40, count 0 2006.257.13:15:58.01#ibcon#*after write, iclass 40, count 0 2006.257.13:15:58.01#ibcon#*before return 0, iclass 40, count 0 2006.257.13:15:58.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:15:58.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:15:58.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:15:58.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:15:58.02$vck44/vb=1,4 2006.257.13:15:58.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.13:15:58.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.13:15:58.02#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:58.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:15:58.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:15:58.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:15:58.02#ibcon#enter wrdev, iclass 4, count 2 2006.257.13:15:58.02#ibcon#first serial, iclass 4, count 2 2006.257.13:15:58.02#ibcon#enter sib2, iclass 4, count 2 2006.257.13:15:58.02#ibcon#flushed, iclass 4, count 2 2006.257.13:15:58.02#ibcon#about to write, iclass 4, count 2 2006.257.13:15:58.02#ibcon#wrote, iclass 4, count 2 2006.257.13:15:58.02#ibcon#about to read 3, iclass 4, count 2 2006.257.13:15:58.03#ibcon#read 3, iclass 4, count 2 2006.257.13:15:58.03#ibcon#about to read 4, iclass 4, count 2 2006.257.13:15:58.03#ibcon#read 4, iclass 4, count 2 2006.257.13:15:58.03#ibcon#about to read 5, iclass 4, count 2 2006.257.13:15:58.03#ibcon#read 5, iclass 4, count 2 2006.257.13:15:58.03#ibcon#about to read 6, iclass 4, count 2 2006.257.13:15:58.03#ibcon#read 6, iclass 4, count 2 2006.257.13:15:58.03#ibcon#end of sib2, iclass 4, count 2 2006.257.13:15:58.03#ibcon#*mode == 0, iclass 4, count 2 2006.257.13:15:58.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.13:15:58.03#ibcon#[27=AT01-04\r\n] 2006.257.13:15:58.03#ibcon#*before write, iclass 4, count 2 2006.257.13:15:58.03#ibcon#enter sib2, iclass 4, count 2 2006.257.13:15:58.03#ibcon#flushed, iclass 4, count 2 2006.257.13:15:58.03#ibcon#about to write, iclass 4, count 2 2006.257.13:15:58.03#ibcon#wrote, iclass 4, count 2 2006.257.13:15:58.03#ibcon#about to read 3, iclass 4, count 2 2006.257.13:15:58.06#ibcon#read 3, iclass 4, count 2 2006.257.13:15:58.06#ibcon#about to read 4, iclass 4, count 2 2006.257.13:15:58.06#ibcon#read 4, iclass 4, count 2 2006.257.13:15:58.06#ibcon#about to read 5, iclass 4, count 2 2006.257.13:15:58.06#ibcon#read 5, iclass 4, count 2 2006.257.13:15:58.06#ibcon#about to read 6, iclass 4, count 2 2006.257.13:15:58.06#ibcon#read 6, iclass 4, count 2 2006.257.13:15:58.06#ibcon#end of sib2, iclass 4, count 2 2006.257.13:15:58.06#ibcon#*after write, iclass 4, count 2 2006.257.13:15:58.06#ibcon#*before return 0, iclass 4, count 2 2006.257.13:15:58.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:15:58.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:15:58.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.13:15:58.06#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:58.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:15:58.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:15:58.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:15:58.18#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:15:58.18#ibcon#first serial, iclass 4, count 0 2006.257.13:15:58.18#ibcon#enter sib2, iclass 4, count 0 2006.257.13:15:58.18#ibcon#flushed, iclass 4, count 0 2006.257.13:15:58.18#ibcon#about to write, iclass 4, count 0 2006.257.13:15:58.18#ibcon#wrote, iclass 4, count 0 2006.257.13:15:58.18#ibcon#about to read 3, iclass 4, count 0 2006.257.13:15:58.20#ibcon#read 3, iclass 4, count 0 2006.257.13:15:58.20#ibcon#about to read 4, iclass 4, count 0 2006.257.13:15:58.20#ibcon#read 4, iclass 4, count 0 2006.257.13:15:58.20#ibcon#about to read 5, iclass 4, count 0 2006.257.13:15:58.20#ibcon#read 5, iclass 4, count 0 2006.257.13:15:58.20#ibcon#about to read 6, iclass 4, count 0 2006.257.13:15:58.20#ibcon#read 6, iclass 4, count 0 2006.257.13:15:58.20#ibcon#end of sib2, iclass 4, count 0 2006.257.13:15:58.20#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:15:58.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:15:58.20#ibcon#[27=USB\r\n] 2006.257.13:15:58.20#ibcon#*before write, iclass 4, count 0 2006.257.13:15:58.20#ibcon#enter sib2, iclass 4, count 0 2006.257.13:15:58.20#ibcon#flushed, iclass 4, count 0 2006.257.13:15:58.20#ibcon#about to write, iclass 4, count 0 2006.257.13:15:58.20#ibcon#wrote, iclass 4, count 0 2006.257.13:15:58.20#ibcon#about to read 3, iclass 4, count 0 2006.257.13:15:58.23#ibcon#read 3, iclass 4, count 0 2006.257.13:15:58.23#ibcon#about to read 4, iclass 4, count 0 2006.257.13:15:58.23#ibcon#read 4, iclass 4, count 0 2006.257.13:15:58.23#ibcon#about to read 5, iclass 4, count 0 2006.257.13:15:58.23#ibcon#read 5, iclass 4, count 0 2006.257.13:15:58.23#ibcon#about to read 6, iclass 4, count 0 2006.257.13:15:58.23#ibcon#read 6, iclass 4, count 0 2006.257.13:15:58.23#ibcon#end of sib2, iclass 4, count 0 2006.257.13:15:58.23#ibcon#*after write, iclass 4, count 0 2006.257.13:15:58.23#ibcon#*before return 0, iclass 4, count 0 2006.257.13:15:58.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:15:58.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:15:58.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:15:58.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:15:58.24$vck44/vblo=2,634.99 2006.257.13:15:58.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.13:15:58.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.13:15:58.24#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:58.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:58.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:58.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:58.24#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:15:58.24#ibcon#first serial, iclass 6, count 0 2006.257.13:15:58.24#ibcon#enter sib2, iclass 6, count 0 2006.257.13:15:58.24#ibcon#flushed, iclass 6, count 0 2006.257.13:15:58.24#ibcon#about to write, iclass 6, count 0 2006.257.13:15:58.24#ibcon#wrote, iclass 6, count 0 2006.257.13:15:58.24#ibcon#about to read 3, iclass 6, count 0 2006.257.13:15:58.25#ibcon#read 3, iclass 6, count 0 2006.257.13:15:58.25#ibcon#about to read 4, iclass 6, count 0 2006.257.13:15:58.25#ibcon#read 4, iclass 6, count 0 2006.257.13:15:58.25#ibcon#about to read 5, iclass 6, count 0 2006.257.13:15:58.25#ibcon#read 5, iclass 6, count 0 2006.257.13:15:58.25#ibcon#about to read 6, iclass 6, count 0 2006.257.13:15:58.25#ibcon#read 6, iclass 6, count 0 2006.257.13:15:58.25#ibcon#end of sib2, iclass 6, count 0 2006.257.13:15:58.25#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:15:58.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:15:58.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:15:58.25#ibcon#*before write, iclass 6, count 0 2006.257.13:15:58.25#ibcon#enter sib2, iclass 6, count 0 2006.257.13:15:58.25#ibcon#flushed, iclass 6, count 0 2006.257.13:15:58.25#ibcon#about to write, iclass 6, count 0 2006.257.13:15:58.25#ibcon#wrote, iclass 6, count 0 2006.257.13:15:58.25#ibcon#about to read 3, iclass 6, count 0 2006.257.13:15:58.29#ibcon#read 3, iclass 6, count 0 2006.257.13:15:58.29#ibcon#about to read 4, iclass 6, count 0 2006.257.13:15:58.29#ibcon#read 4, iclass 6, count 0 2006.257.13:15:58.29#ibcon#about to read 5, iclass 6, count 0 2006.257.13:15:58.29#ibcon#read 5, iclass 6, count 0 2006.257.13:15:58.29#ibcon#about to read 6, iclass 6, count 0 2006.257.13:15:58.29#ibcon#read 6, iclass 6, count 0 2006.257.13:15:58.29#ibcon#end of sib2, iclass 6, count 0 2006.257.13:15:58.29#ibcon#*after write, iclass 6, count 0 2006.257.13:15:58.29#ibcon#*before return 0, iclass 6, count 0 2006.257.13:15:58.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:58.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:15:58.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:15:58.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:15:58.30$vck44/vb=2,5 2006.257.13:15:58.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.13:15:58.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.13:15:58.30#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:58.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:58.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:58.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:58.34#ibcon#enter wrdev, iclass 10, count 2 2006.257.13:15:58.34#ibcon#first serial, iclass 10, count 2 2006.257.13:15:58.34#ibcon#enter sib2, iclass 10, count 2 2006.257.13:15:58.34#ibcon#flushed, iclass 10, count 2 2006.257.13:15:58.34#ibcon#about to write, iclass 10, count 2 2006.257.13:15:58.34#ibcon#wrote, iclass 10, count 2 2006.257.13:15:58.34#ibcon#about to read 3, iclass 10, count 2 2006.257.13:15:58.36#ibcon#read 3, iclass 10, count 2 2006.257.13:15:58.36#ibcon#about to read 4, iclass 10, count 2 2006.257.13:15:58.36#ibcon#read 4, iclass 10, count 2 2006.257.13:15:58.36#ibcon#about to read 5, iclass 10, count 2 2006.257.13:15:58.36#ibcon#read 5, iclass 10, count 2 2006.257.13:15:58.36#ibcon#about to read 6, iclass 10, count 2 2006.257.13:15:58.36#ibcon#read 6, iclass 10, count 2 2006.257.13:15:58.36#ibcon#end of sib2, iclass 10, count 2 2006.257.13:15:58.36#ibcon#*mode == 0, iclass 10, count 2 2006.257.13:15:58.36#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.13:15:58.36#ibcon#[27=AT02-05\r\n] 2006.257.13:15:58.36#ibcon#*before write, iclass 10, count 2 2006.257.13:15:58.36#ibcon#enter sib2, iclass 10, count 2 2006.257.13:15:58.36#ibcon#flushed, iclass 10, count 2 2006.257.13:15:58.36#ibcon#about to write, iclass 10, count 2 2006.257.13:15:58.36#ibcon#wrote, iclass 10, count 2 2006.257.13:15:58.36#ibcon#about to read 3, iclass 10, count 2 2006.257.13:15:58.39#ibcon#read 3, iclass 10, count 2 2006.257.13:15:58.39#ibcon#about to read 4, iclass 10, count 2 2006.257.13:15:58.49#ibcon#read 4, iclass 10, count 2 2006.257.13:15:58.49#ibcon#about to read 5, iclass 10, count 2 2006.257.13:15:58.49#ibcon#read 5, iclass 10, count 2 2006.257.13:15:58.49#ibcon#about to read 6, iclass 10, count 2 2006.257.13:15:58.49#ibcon#read 6, iclass 10, count 2 2006.257.13:15:58.49#ibcon#end of sib2, iclass 10, count 2 2006.257.13:15:58.49#ibcon#*after write, iclass 10, count 2 2006.257.13:15:58.49#ibcon#*before return 0, iclass 10, count 2 2006.257.13:15:58.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:58.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:15:58.49#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.13:15:58.49#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:58.49#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:58.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:58.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:58.60#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:15:58.60#ibcon#first serial, iclass 10, count 0 2006.257.13:15:58.60#ibcon#enter sib2, iclass 10, count 0 2006.257.13:15:58.60#ibcon#flushed, iclass 10, count 0 2006.257.13:15:58.60#ibcon#about to write, iclass 10, count 0 2006.257.13:15:58.60#ibcon#wrote, iclass 10, count 0 2006.257.13:15:58.60#ibcon#about to read 3, iclass 10, count 0 2006.257.13:15:58.62#ibcon#read 3, iclass 10, count 0 2006.257.13:15:58.62#ibcon#about to read 4, iclass 10, count 0 2006.257.13:15:58.62#ibcon#read 4, iclass 10, count 0 2006.257.13:15:58.62#ibcon#about to read 5, iclass 10, count 0 2006.257.13:15:58.62#ibcon#read 5, iclass 10, count 0 2006.257.13:15:58.62#ibcon#about to read 6, iclass 10, count 0 2006.257.13:15:58.62#ibcon#read 6, iclass 10, count 0 2006.257.13:15:58.62#ibcon#end of sib2, iclass 10, count 0 2006.257.13:15:58.62#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:15:58.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:15:58.62#ibcon#[27=USB\r\n] 2006.257.13:15:58.62#ibcon#*before write, iclass 10, count 0 2006.257.13:15:58.62#ibcon#enter sib2, iclass 10, count 0 2006.257.13:15:58.62#ibcon#flushed, iclass 10, count 0 2006.257.13:15:58.62#ibcon#about to write, iclass 10, count 0 2006.257.13:15:58.62#ibcon#wrote, iclass 10, count 0 2006.257.13:15:58.62#ibcon#about to read 3, iclass 10, count 0 2006.257.13:15:58.65#ibcon#read 3, iclass 10, count 0 2006.257.13:15:58.65#ibcon#about to read 4, iclass 10, count 0 2006.257.13:15:58.65#ibcon#read 4, iclass 10, count 0 2006.257.13:15:58.65#ibcon#about to read 5, iclass 10, count 0 2006.257.13:15:58.65#ibcon#read 5, iclass 10, count 0 2006.257.13:15:58.65#ibcon#about to read 6, iclass 10, count 0 2006.257.13:15:58.65#ibcon#read 6, iclass 10, count 0 2006.257.13:15:58.65#ibcon#end of sib2, iclass 10, count 0 2006.257.13:15:58.65#ibcon#*after write, iclass 10, count 0 2006.257.13:15:58.65#ibcon#*before return 0, iclass 10, count 0 2006.257.13:15:58.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:58.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:15:58.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:15:58.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:15:58.66$vck44/vblo=3,649.99 2006.257.13:15:58.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.13:15:58.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.13:15:58.66#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:58.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:58.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:58.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:58.66#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:15:58.66#ibcon#first serial, iclass 12, count 0 2006.257.13:15:58.66#ibcon#enter sib2, iclass 12, count 0 2006.257.13:15:58.66#ibcon#flushed, iclass 12, count 0 2006.257.13:15:58.66#ibcon#about to write, iclass 12, count 0 2006.257.13:15:58.66#ibcon#wrote, iclass 12, count 0 2006.257.13:15:58.66#ibcon#about to read 3, iclass 12, count 0 2006.257.13:15:58.67#ibcon#read 3, iclass 12, count 0 2006.257.13:15:58.67#ibcon#about to read 4, iclass 12, count 0 2006.257.13:15:58.67#ibcon#read 4, iclass 12, count 0 2006.257.13:15:58.67#ibcon#about to read 5, iclass 12, count 0 2006.257.13:15:58.67#ibcon#read 5, iclass 12, count 0 2006.257.13:15:58.67#ibcon#about to read 6, iclass 12, count 0 2006.257.13:15:58.67#ibcon#read 6, iclass 12, count 0 2006.257.13:15:58.67#ibcon#end of sib2, iclass 12, count 0 2006.257.13:15:58.67#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:15:58.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:15:58.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:15:58.67#ibcon#*before write, iclass 12, count 0 2006.257.13:15:58.67#ibcon#enter sib2, iclass 12, count 0 2006.257.13:15:58.67#ibcon#flushed, iclass 12, count 0 2006.257.13:15:58.67#ibcon#about to write, iclass 12, count 0 2006.257.13:15:58.67#ibcon#wrote, iclass 12, count 0 2006.257.13:15:58.67#ibcon#about to read 3, iclass 12, count 0 2006.257.13:15:58.71#ibcon#read 3, iclass 12, count 0 2006.257.13:15:58.71#ibcon#about to read 4, iclass 12, count 0 2006.257.13:15:58.71#ibcon#read 4, iclass 12, count 0 2006.257.13:15:58.71#ibcon#about to read 5, iclass 12, count 0 2006.257.13:15:58.71#ibcon#read 5, iclass 12, count 0 2006.257.13:15:58.71#ibcon#about to read 6, iclass 12, count 0 2006.257.13:15:58.71#ibcon#read 6, iclass 12, count 0 2006.257.13:15:58.71#ibcon#end of sib2, iclass 12, count 0 2006.257.13:15:58.71#ibcon#*after write, iclass 12, count 0 2006.257.13:15:58.71#ibcon#*before return 0, iclass 12, count 0 2006.257.13:15:58.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:58.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:15:58.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:15:58.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:15:58.72$vck44/vb=3,4 2006.257.13:15:58.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.13:15:58.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.13:15:58.72#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:58.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:58.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:58.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:58.76#ibcon#enter wrdev, iclass 14, count 2 2006.257.13:15:58.76#ibcon#first serial, iclass 14, count 2 2006.257.13:15:58.76#ibcon#enter sib2, iclass 14, count 2 2006.257.13:15:58.76#ibcon#flushed, iclass 14, count 2 2006.257.13:15:58.76#ibcon#about to write, iclass 14, count 2 2006.257.13:15:58.76#ibcon#wrote, iclass 14, count 2 2006.257.13:15:58.76#ibcon#about to read 3, iclass 14, count 2 2006.257.13:15:58.78#ibcon#read 3, iclass 14, count 2 2006.257.13:15:58.78#ibcon#about to read 4, iclass 14, count 2 2006.257.13:15:58.78#ibcon#read 4, iclass 14, count 2 2006.257.13:15:58.78#ibcon#about to read 5, iclass 14, count 2 2006.257.13:15:58.78#ibcon#read 5, iclass 14, count 2 2006.257.13:15:58.78#ibcon#about to read 6, iclass 14, count 2 2006.257.13:15:58.78#ibcon#read 6, iclass 14, count 2 2006.257.13:15:58.78#ibcon#end of sib2, iclass 14, count 2 2006.257.13:15:58.78#ibcon#*mode == 0, iclass 14, count 2 2006.257.13:15:58.78#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.13:15:58.78#ibcon#[27=AT03-04\r\n] 2006.257.13:15:58.78#ibcon#*before write, iclass 14, count 2 2006.257.13:15:58.78#ibcon#enter sib2, iclass 14, count 2 2006.257.13:15:58.78#ibcon#flushed, iclass 14, count 2 2006.257.13:15:58.78#ibcon#about to write, iclass 14, count 2 2006.257.13:15:58.78#ibcon#wrote, iclass 14, count 2 2006.257.13:15:58.78#ibcon#about to read 3, iclass 14, count 2 2006.257.13:15:58.81#ibcon#read 3, iclass 14, count 2 2006.257.13:15:58.81#ibcon#about to read 4, iclass 14, count 2 2006.257.13:15:58.81#ibcon#read 4, iclass 14, count 2 2006.257.13:15:58.81#ibcon#about to read 5, iclass 14, count 2 2006.257.13:15:58.81#ibcon#read 5, iclass 14, count 2 2006.257.13:15:58.81#ibcon#about to read 6, iclass 14, count 2 2006.257.13:15:58.81#ibcon#read 6, iclass 14, count 2 2006.257.13:15:58.81#ibcon#end of sib2, iclass 14, count 2 2006.257.13:15:58.81#ibcon#*after write, iclass 14, count 2 2006.257.13:15:58.81#ibcon#*before return 0, iclass 14, count 2 2006.257.13:15:58.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:58.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:15:58.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.13:15:58.81#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:58.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:58.83#abcon#<5=/14 1.5 4.2 17.68 971013.8\r\n> 2006.257.13:15:58.85#abcon#{5=INTERFACE CLEAR} 2006.257.13:15:58.91#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:15:58.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:58.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:58.93#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:15:58.93#ibcon#first serial, iclass 14, count 0 2006.257.13:15:58.93#ibcon#enter sib2, iclass 14, count 0 2006.257.13:15:58.93#ibcon#flushed, iclass 14, count 0 2006.257.13:15:58.93#ibcon#about to write, iclass 14, count 0 2006.257.13:15:58.93#ibcon#wrote, iclass 14, count 0 2006.257.13:15:58.93#ibcon#about to read 3, iclass 14, count 0 2006.257.13:15:58.95#ibcon#read 3, iclass 14, count 0 2006.257.13:15:58.95#ibcon#about to read 4, iclass 14, count 0 2006.257.13:15:58.95#ibcon#read 4, iclass 14, count 0 2006.257.13:15:58.95#ibcon#about to read 5, iclass 14, count 0 2006.257.13:15:58.95#ibcon#read 5, iclass 14, count 0 2006.257.13:15:58.95#ibcon#about to read 6, iclass 14, count 0 2006.257.13:15:58.95#ibcon#read 6, iclass 14, count 0 2006.257.13:15:58.95#ibcon#end of sib2, iclass 14, count 0 2006.257.13:15:58.95#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:15:58.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:15:58.95#ibcon#[27=USB\r\n] 2006.257.13:15:58.95#ibcon#*before write, iclass 14, count 0 2006.257.13:15:58.95#ibcon#enter sib2, iclass 14, count 0 2006.257.13:15:58.95#ibcon#flushed, iclass 14, count 0 2006.257.13:15:58.95#ibcon#about to write, iclass 14, count 0 2006.257.13:15:58.95#ibcon#wrote, iclass 14, count 0 2006.257.13:15:58.95#ibcon#about to read 3, iclass 14, count 0 2006.257.13:15:58.98#ibcon#read 3, iclass 14, count 0 2006.257.13:15:58.98#ibcon#about to read 4, iclass 14, count 0 2006.257.13:15:58.98#ibcon#read 4, iclass 14, count 0 2006.257.13:15:58.98#ibcon#about to read 5, iclass 14, count 0 2006.257.13:15:58.98#ibcon#read 5, iclass 14, count 0 2006.257.13:15:58.98#ibcon#about to read 6, iclass 14, count 0 2006.257.13:15:58.98#ibcon#read 6, iclass 14, count 0 2006.257.13:15:58.98#ibcon#end of sib2, iclass 14, count 0 2006.257.13:15:58.98#ibcon#*after write, iclass 14, count 0 2006.257.13:15:58.98#ibcon#*before return 0, iclass 14, count 0 2006.257.13:15:58.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:58.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:15:58.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:15:58.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:15:58.98$vck44/vblo=4,679.99 2006.257.13:15:58.99#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.13:15:58.99#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.13:15:58.99#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:58.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:58.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:58.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:58.99#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:15:58.99#ibcon#first serial, iclass 20, count 0 2006.257.13:15:58.99#ibcon#enter sib2, iclass 20, count 0 2006.257.13:15:58.99#ibcon#flushed, iclass 20, count 0 2006.257.13:15:58.99#ibcon#about to write, iclass 20, count 0 2006.257.13:15:58.99#ibcon#wrote, iclass 20, count 0 2006.257.13:15:58.99#ibcon#about to read 3, iclass 20, count 0 2006.257.13:15:59.00#ibcon#read 3, iclass 20, count 0 2006.257.13:15:59.00#ibcon#about to read 4, iclass 20, count 0 2006.257.13:15:59.00#ibcon#read 4, iclass 20, count 0 2006.257.13:15:59.00#ibcon#about to read 5, iclass 20, count 0 2006.257.13:15:59.00#ibcon#read 5, iclass 20, count 0 2006.257.13:15:59.00#ibcon#about to read 6, iclass 20, count 0 2006.257.13:15:59.00#ibcon#read 6, iclass 20, count 0 2006.257.13:15:59.00#ibcon#end of sib2, iclass 20, count 0 2006.257.13:15:59.00#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:15:59.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:15:59.00#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:15:59.00#ibcon#*before write, iclass 20, count 0 2006.257.13:15:59.00#ibcon#enter sib2, iclass 20, count 0 2006.257.13:15:59.00#ibcon#flushed, iclass 20, count 0 2006.257.13:15:59.00#ibcon#about to write, iclass 20, count 0 2006.257.13:15:59.00#ibcon#wrote, iclass 20, count 0 2006.257.13:15:59.00#ibcon#about to read 3, iclass 20, count 0 2006.257.13:15:59.04#ibcon#read 3, iclass 20, count 0 2006.257.13:15:59.04#ibcon#about to read 4, iclass 20, count 0 2006.257.13:15:59.04#ibcon#read 4, iclass 20, count 0 2006.257.13:15:59.04#ibcon#about to read 5, iclass 20, count 0 2006.257.13:15:59.04#ibcon#read 5, iclass 20, count 0 2006.257.13:15:59.04#ibcon#about to read 6, iclass 20, count 0 2006.257.13:15:59.04#ibcon#read 6, iclass 20, count 0 2006.257.13:15:59.04#ibcon#end of sib2, iclass 20, count 0 2006.257.13:15:59.04#ibcon#*after write, iclass 20, count 0 2006.257.13:15:59.04#ibcon#*before return 0, iclass 20, count 0 2006.257.13:15:59.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:59.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:15:59.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:15:59.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:15:59.05$vck44/vb=4,5 2006.257.13:15:59.05#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.13:15:59.05#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.13:15:59.05#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:59.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:59.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:59.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:59.09#ibcon#enter wrdev, iclass 22, count 2 2006.257.13:15:59.09#ibcon#first serial, iclass 22, count 2 2006.257.13:15:59.09#ibcon#enter sib2, iclass 22, count 2 2006.257.13:15:59.09#ibcon#flushed, iclass 22, count 2 2006.257.13:15:59.09#ibcon#about to write, iclass 22, count 2 2006.257.13:15:59.09#ibcon#wrote, iclass 22, count 2 2006.257.13:15:59.09#ibcon#about to read 3, iclass 22, count 2 2006.257.13:15:59.11#ibcon#read 3, iclass 22, count 2 2006.257.13:15:59.11#ibcon#about to read 4, iclass 22, count 2 2006.257.13:15:59.11#ibcon#read 4, iclass 22, count 2 2006.257.13:15:59.11#ibcon#about to read 5, iclass 22, count 2 2006.257.13:15:59.11#ibcon#read 5, iclass 22, count 2 2006.257.13:15:59.11#ibcon#about to read 6, iclass 22, count 2 2006.257.13:15:59.11#ibcon#read 6, iclass 22, count 2 2006.257.13:15:59.11#ibcon#end of sib2, iclass 22, count 2 2006.257.13:15:59.11#ibcon#*mode == 0, iclass 22, count 2 2006.257.13:15:59.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.13:15:59.11#ibcon#[27=AT04-05\r\n] 2006.257.13:15:59.11#ibcon#*before write, iclass 22, count 2 2006.257.13:15:59.11#ibcon#enter sib2, iclass 22, count 2 2006.257.13:15:59.11#ibcon#flushed, iclass 22, count 2 2006.257.13:15:59.11#ibcon#about to write, iclass 22, count 2 2006.257.13:15:59.11#ibcon#wrote, iclass 22, count 2 2006.257.13:15:59.11#ibcon#about to read 3, iclass 22, count 2 2006.257.13:15:59.14#ibcon#read 3, iclass 22, count 2 2006.257.13:15:59.14#ibcon#about to read 4, iclass 22, count 2 2006.257.13:15:59.14#ibcon#read 4, iclass 22, count 2 2006.257.13:15:59.14#ibcon#about to read 5, iclass 22, count 2 2006.257.13:15:59.14#ibcon#read 5, iclass 22, count 2 2006.257.13:15:59.14#ibcon#about to read 6, iclass 22, count 2 2006.257.13:15:59.14#ibcon#read 6, iclass 22, count 2 2006.257.13:15:59.14#ibcon#end of sib2, iclass 22, count 2 2006.257.13:15:59.14#ibcon#*after write, iclass 22, count 2 2006.257.13:15:59.14#ibcon#*before return 0, iclass 22, count 2 2006.257.13:15:59.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:59.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:15:59.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.13:15:59.14#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:59.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:59.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:59.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:59.26#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:15:59.26#ibcon#first serial, iclass 22, count 0 2006.257.13:15:59.26#ibcon#enter sib2, iclass 22, count 0 2006.257.13:15:59.26#ibcon#flushed, iclass 22, count 0 2006.257.13:15:59.26#ibcon#about to write, iclass 22, count 0 2006.257.13:15:59.26#ibcon#wrote, iclass 22, count 0 2006.257.13:15:59.26#ibcon#about to read 3, iclass 22, count 0 2006.257.13:15:59.28#ibcon#read 3, iclass 22, count 0 2006.257.13:15:59.28#ibcon#about to read 4, iclass 22, count 0 2006.257.13:15:59.28#ibcon#read 4, iclass 22, count 0 2006.257.13:15:59.28#ibcon#about to read 5, iclass 22, count 0 2006.257.13:15:59.28#ibcon#read 5, iclass 22, count 0 2006.257.13:15:59.28#ibcon#about to read 6, iclass 22, count 0 2006.257.13:15:59.28#ibcon#read 6, iclass 22, count 0 2006.257.13:15:59.28#ibcon#end of sib2, iclass 22, count 0 2006.257.13:15:59.28#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:15:59.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:15:59.28#ibcon#[27=USB\r\n] 2006.257.13:15:59.28#ibcon#*before write, iclass 22, count 0 2006.257.13:15:59.28#ibcon#enter sib2, iclass 22, count 0 2006.257.13:15:59.28#ibcon#flushed, iclass 22, count 0 2006.257.13:15:59.28#ibcon#about to write, iclass 22, count 0 2006.257.13:15:59.28#ibcon#wrote, iclass 22, count 0 2006.257.13:15:59.28#ibcon#about to read 3, iclass 22, count 0 2006.257.13:15:59.31#ibcon#read 3, iclass 22, count 0 2006.257.13:15:59.31#ibcon#about to read 4, iclass 22, count 0 2006.257.13:15:59.31#ibcon#read 4, iclass 22, count 0 2006.257.13:15:59.31#ibcon#about to read 5, iclass 22, count 0 2006.257.13:15:59.31#ibcon#read 5, iclass 22, count 0 2006.257.13:15:59.31#ibcon#about to read 6, iclass 22, count 0 2006.257.13:15:59.31#ibcon#read 6, iclass 22, count 0 2006.257.13:15:59.31#ibcon#end of sib2, iclass 22, count 0 2006.257.13:15:59.31#ibcon#*after write, iclass 22, count 0 2006.257.13:15:59.31#ibcon#*before return 0, iclass 22, count 0 2006.257.13:15:59.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:59.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:15:59.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:15:59.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:15:59.32$vck44/vblo=5,709.99 2006.257.13:15:59.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.13:15:59.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.13:15:59.32#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:59.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:59.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:59.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:59.32#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:15:59.32#ibcon#first serial, iclass 24, count 0 2006.257.13:15:59.32#ibcon#enter sib2, iclass 24, count 0 2006.257.13:15:59.32#ibcon#flushed, iclass 24, count 0 2006.257.13:15:59.32#ibcon#about to write, iclass 24, count 0 2006.257.13:15:59.32#ibcon#wrote, iclass 24, count 0 2006.257.13:15:59.32#ibcon#about to read 3, iclass 24, count 0 2006.257.13:15:59.33#ibcon#read 3, iclass 24, count 0 2006.257.13:15:59.33#ibcon#about to read 4, iclass 24, count 0 2006.257.13:15:59.33#ibcon#read 4, iclass 24, count 0 2006.257.13:15:59.33#ibcon#about to read 5, iclass 24, count 0 2006.257.13:15:59.33#ibcon#read 5, iclass 24, count 0 2006.257.13:15:59.33#ibcon#about to read 6, iclass 24, count 0 2006.257.13:15:59.33#ibcon#read 6, iclass 24, count 0 2006.257.13:15:59.33#ibcon#end of sib2, iclass 24, count 0 2006.257.13:15:59.33#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:15:59.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:15:59.33#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:15:59.33#ibcon#*before write, iclass 24, count 0 2006.257.13:15:59.33#ibcon#enter sib2, iclass 24, count 0 2006.257.13:15:59.33#ibcon#flushed, iclass 24, count 0 2006.257.13:15:59.33#ibcon#about to write, iclass 24, count 0 2006.257.13:15:59.33#ibcon#wrote, iclass 24, count 0 2006.257.13:15:59.33#ibcon#about to read 3, iclass 24, count 0 2006.257.13:15:59.37#ibcon#read 3, iclass 24, count 0 2006.257.13:15:59.37#ibcon#about to read 4, iclass 24, count 0 2006.257.13:15:59.37#ibcon#read 4, iclass 24, count 0 2006.257.13:15:59.37#ibcon#about to read 5, iclass 24, count 0 2006.257.13:15:59.37#ibcon#read 5, iclass 24, count 0 2006.257.13:15:59.37#ibcon#about to read 6, iclass 24, count 0 2006.257.13:15:59.37#ibcon#read 6, iclass 24, count 0 2006.257.13:15:59.37#ibcon#end of sib2, iclass 24, count 0 2006.257.13:15:59.37#ibcon#*after write, iclass 24, count 0 2006.257.13:15:59.37#ibcon#*before return 0, iclass 24, count 0 2006.257.13:15:59.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:59.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:15:59.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:15:59.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:15:59.38$vck44/vb=5,4 2006.257.13:15:59.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.13:15:59.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.13:15:59.38#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:59.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:59.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:59.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:59.42#ibcon#enter wrdev, iclass 26, count 2 2006.257.13:15:59.42#ibcon#first serial, iclass 26, count 2 2006.257.13:15:59.42#ibcon#enter sib2, iclass 26, count 2 2006.257.13:15:59.42#ibcon#flushed, iclass 26, count 2 2006.257.13:15:59.42#ibcon#about to write, iclass 26, count 2 2006.257.13:15:59.42#ibcon#wrote, iclass 26, count 2 2006.257.13:15:59.42#ibcon#about to read 3, iclass 26, count 2 2006.257.13:15:59.44#ibcon#read 3, iclass 26, count 2 2006.257.13:15:59.44#ibcon#about to read 4, iclass 26, count 2 2006.257.13:15:59.44#ibcon#read 4, iclass 26, count 2 2006.257.13:15:59.44#ibcon#about to read 5, iclass 26, count 2 2006.257.13:15:59.44#ibcon#read 5, iclass 26, count 2 2006.257.13:15:59.44#ibcon#about to read 6, iclass 26, count 2 2006.257.13:15:59.44#ibcon#read 6, iclass 26, count 2 2006.257.13:15:59.44#ibcon#end of sib2, iclass 26, count 2 2006.257.13:15:59.44#ibcon#*mode == 0, iclass 26, count 2 2006.257.13:15:59.44#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.13:15:59.44#ibcon#[27=AT05-04\r\n] 2006.257.13:15:59.44#ibcon#*before write, iclass 26, count 2 2006.257.13:15:59.44#ibcon#enter sib2, iclass 26, count 2 2006.257.13:15:59.44#ibcon#flushed, iclass 26, count 2 2006.257.13:15:59.44#ibcon#about to write, iclass 26, count 2 2006.257.13:15:59.44#ibcon#wrote, iclass 26, count 2 2006.257.13:15:59.44#ibcon#about to read 3, iclass 26, count 2 2006.257.13:15:59.47#ibcon#read 3, iclass 26, count 2 2006.257.13:15:59.47#ibcon#about to read 4, iclass 26, count 2 2006.257.13:15:59.47#ibcon#read 4, iclass 26, count 2 2006.257.13:15:59.47#ibcon#about to read 5, iclass 26, count 2 2006.257.13:15:59.47#ibcon#read 5, iclass 26, count 2 2006.257.13:15:59.47#ibcon#about to read 6, iclass 26, count 2 2006.257.13:15:59.51#ibcon#read 6, iclass 26, count 2 2006.257.13:15:59.51#ibcon#end of sib2, iclass 26, count 2 2006.257.13:15:59.51#ibcon#*after write, iclass 26, count 2 2006.257.13:15:59.51#ibcon#*before return 0, iclass 26, count 2 2006.257.13:15:59.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:59.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:15:59.52#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.13:15:59.52#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:59.52#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:59.63#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:59.63#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:59.63#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:15:59.63#ibcon#first serial, iclass 26, count 0 2006.257.13:15:59.63#ibcon#enter sib2, iclass 26, count 0 2006.257.13:15:59.63#ibcon#flushed, iclass 26, count 0 2006.257.13:15:59.63#ibcon#about to write, iclass 26, count 0 2006.257.13:15:59.63#ibcon#wrote, iclass 26, count 0 2006.257.13:15:59.63#ibcon#about to read 3, iclass 26, count 0 2006.257.13:15:59.65#ibcon#read 3, iclass 26, count 0 2006.257.13:15:59.65#ibcon#about to read 4, iclass 26, count 0 2006.257.13:15:59.65#ibcon#read 4, iclass 26, count 0 2006.257.13:15:59.65#ibcon#about to read 5, iclass 26, count 0 2006.257.13:15:59.65#ibcon#read 5, iclass 26, count 0 2006.257.13:15:59.65#ibcon#about to read 6, iclass 26, count 0 2006.257.13:15:59.65#ibcon#read 6, iclass 26, count 0 2006.257.13:15:59.65#ibcon#end of sib2, iclass 26, count 0 2006.257.13:15:59.65#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:15:59.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:15:59.65#ibcon#[27=USB\r\n] 2006.257.13:15:59.65#ibcon#*before write, iclass 26, count 0 2006.257.13:15:59.65#ibcon#enter sib2, iclass 26, count 0 2006.257.13:15:59.65#ibcon#flushed, iclass 26, count 0 2006.257.13:15:59.65#ibcon#about to write, iclass 26, count 0 2006.257.13:15:59.65#ibcon#wrote, iclass 26, count 0 2006.257.13:15:59.65#ibcon#about to read 3, iclass 26, count 0 2006.257.13:15:59.68#ibcon#read 3, iclass 26, count 0 2006.257.13:15:59.68#ibcon#about to read 4, iclass 26, count 0 2006.257.13:15:59.68#ibcon#read 4, iclass 26, count 0 2006.257.13:15:59.68#ibcon#about to read 5, iclass 26, count 0 2006.257.13:15:59.68#ibcon#read 5, iclass 26, count 0 2006.257.13:15:59.68#ibcon#about to read 6, iclass 26, count 0 2006.257.13:15:59.68#ibcon#read 6, iclass 26, count 0 2006.257.13:15:59.68#ibcon#end of sib2, iclass 26, count 0 2006.257.13:15:59.68#ibcon#*after write, iclass 26, count 0 2006.257.13:15:59.68#ibcon#*before return 0, iclass 26, count 0 2006.257.13:15:59.68#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:59.68#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:15:59.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:15:59.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:15:59.69$vck44/vblo=6,719.99 2006.257.13:15:59.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.13:15:59.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.13:15:59.69#ibcon#ireg 17 cls_cnt 0 2006.257.13:15:59.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:59.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:59.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:59.69#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:15:59.69#ibcon#first serial, iclass 28, count 0 2006.257.13:15:59.69#ibcon#enter sib2, iclass 28, count 0 2006.257.13:15:59.69#ibcon#flushed, iclass 28, count 0 2006.257.13:15:59.69#ibcon#about to write, iclass 28, count 0 2006.257.13:15:59.69#ibcon#wrote, iclass 28, count 0 2006.257.13:15:59.69#ibcon#about to read 3, iclass 28, count 0 2006.257.13:15:59.70#ibcon#read 3, iclass 28, count 0 2006.257.13:15:59.70#ibcon#about to read 4, iclass 28, count 0 2006.257.13:15:59.70#ibcon#read 4, iclass 28, count 0 2006.257.13:15:59.70#ibcon#about to read 5, iclass 28, count 0 2006.257.13:15:59.70#ibcon#read 5, iclass 28, count 0 2006.257.13:15:59.70#ibcon#about to read 6, iclass 28, count 0 2006.257.13:15:59.70#ibcon#read 6, iclass 28, count 0 2006.257.13:15:59.70#ibcon#end of sib2, iclass 28, count 0 2006.257.13:15:59.70#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:15:59.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:15:59.70#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:15:59.70#ibcon#*before write, iclass 28, count 0 2006.257.13:15:59.70#ibcon#enter sib2, iclass 28, count 0 2006.257.13:15:59.70#ibcon#flushed, iclass 28, count 0 2006.257.13:15:59.70#ibcon#about to write, iclass 28, count 0 2006.257.13:15:59.70#ibcon#wrote, iclass 28, count 0 2006.257.13:15:59.70#ibcon#about to read 3, iclass 28, count 0 2006.257.13:15:59.74#ibcon#read 3, iclass 28, count 0 2006.257.13:15:59.74#ibcon#about to read 4, iclass 28, count 0 2006.257.13:15:59.74#ibcon#read 4, iclass 28, count 0 2006.257.13:15:59.74#ibcon#about to read 5, iclass 28, count 0 2006.257.13:15:59.74#ibcon#read 5, iclass 28, count 0 2006.257.13:15:59.74#ibcon#about to read 6, iclass 28, count 0 2006.257.13:15:59.74#ibcon#read 6, iclass 28, count 0 2006.257.13:15:59.74#ibcon#end of sib2, iclass 28, count 0 2006.257.13:15:59.74#ibcon#*after write, iclass 28, count 0 2006.257.13:15:59.74#ibcon#*before return 0, iclass 28, count 0 2006.257.13:15:59.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:59.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:15:59.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:15:59.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:15:59.75$vck44/vb=6,4 2006.257.13:15:59.75#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.13:15:59.75#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.13:15:59.75#ibcon#ireg 11 cls_cnt 2 2006.257.13:15:59.75#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:59.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:59.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:59.79#ibcon#enter wrdev, iclass 30, count 2 2006.257.13:15:59.79#ibcon#first serial, iclass 30, count 2 2006.257.13:15:59.79#ibcon#enter sib2, iclass 30, count 2 2006.257.13:15:59.79#ibcon#flushed, iclass 30, count 2 2006.257.13:15:59.79#ibcon#about to write, iclass 30, count 2 2006.257.13:15:59.79#ibcon#wrote, iclass 30, count 2 2006.257.13:15:59.79#ibcon#about to read 3, iclass 30, count 2 2006.257.13:15:59.81#ibcon#read 3, iclass 30, count 2 2006.257.13:15:59.81#ibcon#about to read 4, iclass 30, count 2 2006.257.13:15:59.81#ibcon#read 4, iclass 30, count 2 2006.257.13:15:59.81#ibcon#about to read 5, iclass 30, count 2 2006.257.13:15:59.81#ibcon#read 5, iclass 30, count 2 2006.257.13:15:59.81#ibcon#about to read 6, iclass 30, count 2 2006.257.13:15:59.81#ibcon#read 6, iclass 30, count 2 2006.257.13:15:59.81#ibcon#end of sib2, iclass 30, count 2 2006.257.13:15:59.81#ibcon#*mode == 0, iclass 30, count 2 2006.257.13:15:59.81#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.13:15:59.81#ibcon#[27=AT06-04\r\n] 2006.257.13:15:59.81#ibcon#*before write, iclass 30, count 2 2006.257.13:15:59.81#ibcon#enter sib2, iclass 30, count 2 2006.257.13:15:59.81#ibcon#flushed, iclass 30, count 2 2006.257.13:15:59.81#ibcon#about to write, iclass 30, count 2 2006.257.13:15:59.81#ibcon#wrote, iclass 30, count 2 2006.257.13:15:59.81#ibcon#about to read 3, iclass 30, count 2 2006.257.13:15:59.84#ibcon#read 3, iclass 30, count 2 2006.257.13:15:59.84#ibcon#about to read 4, iclass 30, count 2 2006.257.13:15:59.84#ibcon#read 4, iclass 30, count 2 2006.257.13:15:59.84#ibcon#about to read 5, iclass 30, count 2 2006.257.13:15:59.84#ibcon#read 5, iclass 30, count 2 2006.257.13:15:59.84#ibcon#about to read 6, iclass 30, count 2 2006.257.13:15:59.84#ibcon#read 6, iclass 30, count 2 2006.257.13:15:59.84#ibcon#end of sib2, iclass 30, count 2 2006.257.13:15:59.84#ibcon#*after write, iclass 30, count 2 2006.257.13:15:59.84#ibcon#*before return 0, iclass 30, count 2 2006.257.13:15:59.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:59.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:15:59.84#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.13:15:59.84#ibcon#ireg 7 cls_cnt 0 2006.257.13:15:59.84#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:15:59.96#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:15:59.96#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:15:59.96#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:15:59.96#ibcon#first serial, iclass 30, count 0 2006.257.13:15:59.96#ibcon#enter sib2, iclass 30, count 0 2006.257.13:15:59.96#ibcon#flushed, iclass 30, count 0 2006.257.13:15:59.96#ibcon#about to write, iclass 30, count 0 2006.257.13:15:59.96#ibcon#wrote, iclass 30, count 0 2006.257.13:15:59.96#ibcon#about to read 3, iclass 30, count 0 2006.257.13:15:59.98#ibcon#read 3, iclass 30, count 0 2006.257.13:15:59.98#ibcon#about to read 4, iclass 30, count 0 2006.257.13:15:59.98#ibcon#read 4, iclass 30, count 0 2006.257.13:15:59.98#ibcon#about to read 5, iclass 30, count 0 2006.257.13:15:59.98#ibcon#read 5, iclass 30, count 0 2006.257.13:15:59.98#ibcon#about to read 6, iclass 30, count 0 2006.257.13:15:59.98#ibcon#read 6, iclass 30, count 0 2006.257.13:15:59.98#ibcon#end of sib2, iclass 30, count 0 2006.257.13:15:59.98#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:15:59.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:15:59.98#ibcon#[27=USB\r\n] 2006.257.13:15:59.98#ibcon#*before write, iclass 30, count 0 2006.257.13:15:59.98#ibcon#enter sib2, iclass 30, count 0 2006.257.13:15:59.98#ibcon#flushed, iclass 30, count 0 2006.257.13:15:59.98#ibcon#about to write, iclass 30, count 0 2006.257.13:15:59.98#ibcon#wrote, iclass 30, count 0 2006.257.13:15:59.98#ibcon#about to read 3, iclass 30, count 0 2006.257.13:16:00.01#ibcon#read 3, iclass 30, count 0 2006.257.13:16:00.01#ibcon#about to read 4, iclass 30, count 0 2006.257.13:16:00.01#ibcon#read 4, iclass 30, count 0 2006.257.13:16:00.01#ibcon#about to read 5, iclass 30, count 0 2006.257.13:16:00.01#ibcon#read 5, iclass 30, count 0 2006.257.13:16:00.01#ibcon#about to read 6, iclass 30, count 0 2006.257.13:16:00.01#ibcon#read 6, iclass 30, count 0 2006.257.13:16:00.01#ibcon#end of sib2, iclass 30, count 0 2006.257.13:16:00.01#ibcon#*after write, iclass 30, count 0 2006.257.13:16:00.01#ibcon#*before return 0, iclass 30, count 0 2006.257.13:16:00.01#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:16:00.01#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:16:00.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:16:00.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:16:00.02$vck44/vblo=7,734.99 2006.257.13:16:00.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.13:16:00.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.13:16:00.02#ibcon#ireg 17 cls_cnt 0 2006.257.13:16:00.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:16:00.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:16:00.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:16:00.02#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:16:00.02#ibcon#first serial, iclass 32, count 0 2006.257.13:16:00.02#ibcon#enter sib2, iclass 32, count 0 2006.257.13:16:00.02#ibcon#flushed, iclass 32, count 0 2006.257.13:16:00.02#ibcon#about to write, iclass 32, count 0 2006.257.13:16:00.02#ibcon#wrote, iclass 32, count 0 2006.257.13:16:00.02#ibcon#about to read 3, iclass 32, count 0 2006.257.13:16:00.03#ibcon#read 3, iclass 32, count 0 2006.257.13:16:00.03#ibcon#about to read 4, iclass 32, count 0 2006.257.13:16:00.03#ibcon#read 4, iclass 32, count 0 2006.257.13:16:00.03#ibcon#about to read 5, iclass 32, count 0 2006.257.13:16:00.03#ibcon#read 5, iclass 32, count 0 2006.257.13:16:00.03#ibcon#about to read 6, iclass 32, count 0 2006.257.13:16:00.03#ibcon#read 6, iclass 32, count 0 2006.257.13:16:00.03#ibcon#end of sib2, iclass 32, count 0 2006.257.13:16:00.03#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:16:00.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:16:00.03#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:16:00.03#ibcon#*before write, iclass 32, count 0 2006.257.13:16:00.03#ibcon#enter sib2, iclass 32, count 0 2006.257.13:16:00.03#ibcon#flushed, iclass 32, count 0 2006.257.13:16:00.03#ibcon#about to write, iclass 32, count 0 2006.257.13:16:00.03#ibcon#wrote, iclass 32, count 0 2006.257.13:16:00.03#ibcon#about to read 3, iclass 32, count 0 2006.257.13:16:00.07#ibcon#read 3, iclass 32, count 0 2006.257.13:16:00.07#ibcon#about to read 4, iclass 32, count 0 2006.257.13:16:00.07#ibcon#read 4, iclass 32, count 0 2006.257.13:16:00.07#ibcon#about to read 5, iclass 32, count 0 2006.257.13:16:00.07#ibcon#read 5, iclass 32, count 0 2006.257.13:16:00.07#ibcon#about to read 6, iclass 32, count 0 2006.257.13:16:00.07#ibcon#read 6, iclass 32, count 0 2006.257.13:16:00.07#ibcon#end of sib2, iclass 32, count 0 2006.257.13:16:00.07#ibcon#*after write, iclass 32, count 0 2006.257.13:16:00.07#ibcon#*before return 0, iclass 32, count 0 2006.257.13:16:00.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:16:00.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:16:00.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:16:00.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:16:00.08$vck44/vb=7,4 2006.257.13:16:00.08#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.13:16:00.08#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.13:16:00.08#ibcon#ireg 11 cls_cnt 2 2006.257.13:16:00.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:16:00.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:16:00.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:16:00.12#ibcon#enter wrdev, iclass 34, count 2 2006.257.13:16:00.12#ibcon#first serial, iclass 34, count 2 2006.257.13:16:00.12#ibcon#enter sib2, iclass 34, count 2 2006.257.13:16:00.12#ibcon#flushed, iclass 34, count 2 2006.257.13:16:00.12#ibcon#about to write, iclass 34, count 2 2006.257.13:16:00.12#ibcon#wrote, iclass 34, count 2 2006.257.13:16:00.12#ibcon#about to read 3, iclass 34, count 2 2006.257.13:16:00.14#ibcon#read 3, iclass 34, count 2 2006.257.13:16:00.14#ibcon#about to read 4, iclass 34, count 2 2006.257.13:16:00.14#ibcon#read 4, iclass 34, count 2 2006.257.13:16:00.14#ibcon#about to read 5, iclass 34, count 2 2006.257.13:16:00.14#ibcon#read 5, iclass 34, count 2 2006.257.13:16:00.14#ibcon#about to read 6, iclass 34, count 2 2006.257.13:16:00.14#ibcon#read 6, iclass 34, count 2 2006.257.13:16:00.14#ibcon#end of sib2, iclass 34, count 2 2006.257.13:16:00.14#ibcon#*mode == 0, iclass 34, count 2 2006.257.13:16:00.14#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.13:16:00.14#ibcon#[27=AT07-04\r\n] 2006.257.13:16:00.14#ibcon#*before write, iclass 34, count 2 2006.257.13:16:00.14#ibcon#enter sib2, iclass 34, count 2 2006.257.13:16:00.14#ibcon#flushed, iclass 34, count 2 2006.257.13:16:00.14#ibcon#about to write, iclass 34, count 2 2006.257.13:16:00.14#ibcon#wrote, iclass 34, count 2 2006.257.13:16:00.14#ibcon#about to read 3, iclass 34, count 2 2006.257.13:16:00.17#ibcon#read 3, iclass 34, count 2 2006.257.13:16:00.17#ibcon#about to read 4, iclass 34, count 2 2006.257.13:16:00.17#ibcon#read 4, iclass 34, count 2 2006.257.13:16:00.17#ibcon#about to read 5, iclass 34, count 2 2006.257.13:16:00.17#ibcon#read 5, iclass 34, count 2 2006.257.13:16:00.17#ibcon#about to read 6, iclass 34, count 2 2006.257.13:16:00.17#ibcon#read 6, iclass 34, count 2 2006.257.13:16:00.17#ibcon#end of sib2, iclass 34, count 2 2006.257.13:16:00.17#ibcon#*after write, iclass 34, count 2 2006.257.13:16:00.17#ibcon#*before return 0, iclass 34, count 2 2006.257.13:16:00.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:16:00.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:16:00.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.13:16:00.17#ibcon#ireg 7 cls_cnt 0 2006.257.13:16:00.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:16:00.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:16:00.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:16:00.29#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:16:00.29#ibcon#first serial, iclass 34, count 0 2006.257.13:16:00.29#ibcon#enter sib2, iclass 34, count 0 2006.257.13:16:00.29#ibcon#flushed, iclass 34, count 0 2006.257.13:16:00.29#ibcon#about to write, iclass 34, count 0 2006.257.13:16:00.29#ibcon#wrote, iclass 34, count 0 2006.257.13:16:00.29#ibcon#about to read 3, iclass 34, count 0 2006.257.13:16:00.31#ibcon#read 3, iclass 34, count 0 2006.257.13:16:00.31#ibcon#about to read 4, iclass 34, count 0 2006.257.13:16:00.31#ibcon#read 4, iclass 34, count 0 2006.257.13:16:00.31#ibcon#about to read 5, iclass 34, count 0 2006.257.13:16:00.31#ibcon#read 5, iclass 34, count 0 2006.257.13:16:00.31#ibcon#about to read 6, iclass 34, count 0 2006.257.13:16:00.31#ibcon#read 6, iclass 34, count 0 2006.257.13:16:00.31#ibcon#end of sib2, iclass 34, count 0 2006.257.13:16:00.31#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:16:00.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:16:00.31#ibcon#[27=USB\r\n] 2006.257.13:16:00.31#ibcon#*before write, iclass 34, count 0 2006.257.13:16:00.31#ibcon#enter sib2, iclass 34, count 0 2006.257.13:16:00.31#ibcon#flushed, iclass 34, count 0 2006.257.13:16:00.31#ibcon#about to write, iclass 34, count 0 2006.257.13:16:00.31#ibcon#wrote, iclass 34, count 0 2006.257.13:16:00.31#ibcon#about to read 3, iclass 34, count 0 2006.257.13:16:00.34#ibcon#read 3, iclass 34, count 0 2006.257.13:16:00.34#ibcon#about to read 4, iclass 34, count 0 2006.257.13:16:00.34#ibcon#read 4, iclass 34, count 0 2006.257.13:16:00.34#ibcon#about to read 5, iclass 34, count 0 2006.257.13:16:00.34#ibcon#read 5, iclass 34, count 0 2006.257.13:16:00.34#ibcon#about to read 6, iclass 34, count 0 2006.257.13:16:00.34#ibcon#read 6, iclass 34, count 0 2006.257.13:16:00.34#ibcon#end of sib2, iclass 34, count 0 2006.257.13:16:00.34#ibcon#*after write, iclass 34, count 0 2006.257.13:16:00.34#ibcon#*before return 0, iclass 34, count 0 2006.257.13:16:00.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:16:00.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:16:00.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:16:00.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:16:00.35$vck44/vblo=8,744.99 2006.257.13:16:00.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.13:16:00.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.13:16:00.35#ibcon#ireg 17 cls_cnt 0 2006.257.13:16:00.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:16:00.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:16:00.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:16:00.35#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:16:00.35#ibcon#first serial, iclass 36, count 0 2006.257.13:16:00.35#ibcon#enter sib2, iclass 36, count 0 2006.257.13:16:00.35#ibcon#flushed, iclass 36, count 0 2006.257.13:16:00.35#ibcon#about to write, iclass 36, count 0 2006.257.13:16:00.35#ibcon#wrote, iclass 36, count 0 2006.257.13:16:00.35#ibcon#about to read 3, iclass 36, count 0 2006.257.13:16:00.36#ibcon#read 3, iclass 36, count 0 2006.257.13:16:00.36#ibcon#about to read 4, iclass 36, count 0 2006.257.13:16:00.36#ibcon#read 4, iclass 36, count 0 2006.257.13:16:00.36#ibcon#about to read 5, iclass 36, count 0 2006.257.13:16:00.36#ibcon#read 5, iclass 36, count 0 2006.257.13:16:00.36#ibcon#about to read 6, iclass 36, count 0 2006.257.13:16:00.36#ibcon#read 6, iclass 36, count 0 2006.257.13:16:00.36#ibcon#end of sib2, iclass 36, count 0 2006.257.13:16:00.36#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:16:00.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:16:00.36#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:16:00.36#ibcon#*before write, iclass 36, count 0 2006.257.13:16:00.36#ibcon#enter sib2, iclass 36, count 0 2006.257.13:16:00.36#ibcon#flushed, iclass 36, count 0 2006.257.13:16:00.36#ibcon#about to write, iclass 36, count 0 2006.257.13:16:00.36#ibcon#wrote, iclass 36, count 0 2006.257.13:16:00.36#ibcon#about to read 3, iclass 36, count 0 2006.257.13:16:00.40#ibcon#read 3, iclass 36, count 0 2006.257.13:16:00.40#ibcon#about to read 4, iclass 36, count 0 2006.257.13:16:00.40#ibcon#read 4, iclass 36, count 0 2006.257.13:16:00.40#ibcon#about to read 5, iclass 36, count 0 2006.257.13:16:00.40#ibcon#read 5, iclass 36, count 0 2006.257.13:16:00.40#ibcon#about to read 6, iclass 36, count 0 2006.257.13:16:00.40#ibcon#read 6, iclass 36, count 0 2006.257.13:16:00.40#ibcon#end of sib2, iclass 36, count 0 2006.257.13:16:00.40#ibcon#*after write, iclass 36, count 0 2006.257.13:16:00.40#ibcon#*before return 0, iclass 36, count 0 2006.257.13:16:00.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:16:00.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:16:00.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:16:00.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:16:00.41$vck44/vb=8,4 2006.257.13:16:00.41#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.13:16:00.41#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.13:16:00.41#ibcon#ireg 11 cls_cnt 2 2006.257.13:16:00.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:16:00.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:16:00.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:16:00.45#ibcon#enter wrdev, iclass 38, count 2 2006.257.13:16:00.45#ibcon#first serial, iclass 38, count 2 2006.257.13:16:00.45#ibcon#enter sib2, iclass 38, count 2 2006.257.13:16:00.45#ibcon#flushed, iclass 38, count 2 2006.257.13:16:00.45#ibcon#about to write, iclass 38, count 2 2006.257.13:16:00.45#ibcon#wrote, iclass 38, count 2 2006.257.13:16:00.45#ibcon#about to read 3, iclass 38, count 2 2006.257.13:16:00.47#ibcon#read 3, iclass 38, count 2 2006.257.13:16:00.47#ibcon#about to read 4, iclass 38, count 2 2006.257.13:16:00.47#ibcon#read 4, iclass 38, count 2 2006.257.13:16:00.47#ibcon#about to read 5, iclass 38, count 2 2006.257.13:16:00.47#ibcon#read 5, iclass 38, count 2 2006.257.13:16:00.47#ibcon#about to read 6, iclass 38, count 2 2006.257.13:16:00.47#ibcon#read 6, iclass 38, count 2 2006.257.13:16:00.47#ibcon#end of sib2, iclass 38, count 2 2006.257.13:16:00.47#ibcon#*mode == 0, iclass 38, count 2 2006.257.13:16:00.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.13:16:00.47#ibcon#[27=AT08-04\r\n] 2006.257.13:16:00.47#ibcon#*before write, iclass 38, count 2 2006.257.13:16:00.47#ibcon#enter sib2, iclass 38, count 2 2006.257.13:16:00.47#ibcon#flushed, iclass 38, count 2 2006.257.13:16:00.47#ibcon#about to write, iclass 38, count 2 2006.257.13:16:00.47#ibcon#wrote, iclass 38, count 2 2006.257.13:16:00.47#ibcon#about to read 3, iclass 38, count 2 2006.257.13:16:00.50#ibcon#read 3, iclass 38, count 2 2006.257.13:16:00.57#ibcon#about to read 4, iclass 38, count 2 2006.257.13:16:00.57#ibcon#read 4, iclass 38, count 2 2006.257.13:16:00.57#ibcon#about to read 5, iclass 38, count 2 2006.257.13:16:00.57#ibcon#read 5, iclass 38, count 2 2006.257.13:16:00.57#ibcon#about to read 6, iclass 38, count 2 2006.257.13:16:00.57#ibcon#read 6, iclass 38, count 2 2006.257.13:16:00.57#ibcon#end of sib2, iclass 38, count 2 2006.257.13:16:00.57#ibcon#*after write, iclass 38, count 2 2006.257.13:16:00.57#ibcon#*before return 0, iclass 38, count 2 2006.257.13:16:00.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:16:00.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:16:00.57#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.13:16:00.57#ibcon#ireg 7 cls_cnt 0 2006.257.13:16:00.57#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:16:00.68#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:16:00.68#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:16:00.68#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:16:00.68#ibcon#first serial, iclass 38, count 0 2006.257.13:16:00.68#ibcon#enter sib2, iclass 38, count 0 2006.257.13:16:00.68#ibcon#flushed, iclass 38, count 0 2006.257.13:16:00.68#ibcon#about to write, iclass 38, count 0 2006.257.13:16:00.68#ibcon#wrote, iclass 38, count 0 2006.257.13:16:00.68#ibcon#about to read 3, iclass 38, count 0 2006.257.13:16:00.70#ibcon#read 3, iclass 38, count 0 2006.257.13:16:00.70#ibcon#about to read 4, iclass 38, count 0 2006.257.13:16:00.70#ibcon#read 4, iclass 38, count 0 2006.257.13:16:00.70#ibcon#about to read 5, iclass 38, count 0 2006.257.13:16:00.70#ibcon#read 5, iclass 38, count 0 2006.257.13:16:00.70#ibcon#about to read 6, iclass 38, count 0 2006.257.13:16:00.70#ibcon#read 6, iclass 38, count 0 2006.257.13:16:00.70#ibcon#end of sib2, iclass 38, count 0 2006.257.13:16:00.70#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:16:00.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:16:00.70#ibcon#[27=USB\r\n] 2006.257.13:16:00.70#ibcon#*before write, iclass 38, count 0 2006.257.13:16:00.70#ibcon#enter sib2, iclass 38, count 0 2006.257.13:16:00.70#ibcon#flushed, iclass 38, count 0 2006.257.13:16:00.70#ibcon#about to write, iclass 38, count 0 2006.257.13:16:00.70#ibcon#wrote, iclass 38, count 0 2006.257.13:16:00.70#ibcon#about to read 3, iclass 38, count 0 2006.257.13:16:00.73#ibcon#read 3, iclass 38, count 0 2006.257.13:16:00.73#ibcon#about to read 4, iclass 38, count 0 2006.257.13:16:00.73#ibcon#read 4, iclass 38, count 0 2006.257.13:16:00.73#ibcon#about to read 5, iclass 38, count 0 2006.257.13:16:00.73#ibcon#read 5, iclass 38, count 0 2006.257.13:16:00.73#ibcon#about to read 6, iclass 38, count 0 2006.257.13:16:00.73#ibcon#read 6, iclass 38, count 0 2006.257.13:16:00.73#ibcon#end of sib2, iclass 38, count 0 2006.257.13:16:00.73#ibcon#*after write, iclass 38, count 0 2006.257.13:16:00.73#ibcon#*before return 0, iclass 38, count 0 2006.257.13:16:00.73#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:16:00.73#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:16:00.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:16:00.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:16:00.74$vck44/vabw=wide 2006.257.13:16:00.74#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.13:16:00.74#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.13:16:00.74#ibcon#ireg 8 cls_cnt 0 2006.257.13:16:00.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:16:00.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:16:00.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:16:00.74#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:16:00.74#ibcon#first serial, iclass 40, count 0 2006.257.13:16:00.74#ibcon#enter sib2, iclass 40, count 0 2006.257.13:16:00.74#ibcon#flushed, iclass 40, count 0 2006.257.13:16:00.74#ibcon#about to write, iclass 40, count 0 2006.257.13:16:00.74#ibcon#wrote, iclass 40, count 0 2006.257.13:16:00.74#ibcon#about to read 3, iclass 40, count 0 2006.257.13:16:00.75#ibcon#read 3, iclass 40, count 0 2006.257.13:16:00.75#ibcon#about to read 4, iclass 40, count 0 2006.257.13:16:00.75#ibcon#read 4, iclass 40, count 0 2006.257.13:16:00.75#ibcon#about to read 5, iclass 40, count 0 2006.257.13:16:00.75#ibcon#read 5, iclass 40, count 0 2006.257.13:16:00.75#ibcon#about to read 6, iclass 40, count 0 2006.257.13:16:00.75#ibcon#read 6, iclass 40, count 0 2006.257.13:16:00.75#ibcon#end of sib2, iclass 40, count 0 2006.257.13:16:00.75#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:16:00.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:16:00.75#ibcon#[25=BW32\r\n] 2006.257.13:16:00.75#ibcon#*before write, iclass 40, count 0 2006.257.13:16:00.75#ibcon#enter sib2, iclass 40, count 0 2006.257.13:16:00.75#ibcon#flushed, iclass 40, count 0 2006.257.13:16:00.75#ibcon#about to write, iclass 40, count 0 2006.257.13:16:00.75#ibcon#wrote, iclass 40, count 0 2006.257.13:16:00.75#ibcon#about to read 3, iclass 40, count 0 2006.257.13:16:00.78#ibcon#read 3, iclass 40, count 0 2006.257.13:16:00.78#ibcon#about to read 4, iclass 40, count 0 2006.257.13:16:00.78#ibcon#read 4, iclass 40, count 0 2006.257.13:16:00.78#ibcon#about to read 5, iclass 40, count 0 2006.257.13:16:00.78#ibcon#read 5, iclass 40, count 0 2006.257.13:16:00.78#ibcon#about to read 6, iclass 40, count 0 2006.257.13:16:00.78#ibcon#read 6, iclass 40, count 0 2006.257.13:16:00.78#ibcon#end of sib2, iclass 40, count 0 2006.257.13:16:00.78#ibcon#*after write, iclass 40, count 0 2006.257.13:16:00.78#ibcon#*before return 0, iclass 40, count 0 2006.257.13:16:00.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:16:00.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:16:00.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:16:00.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:16:00.78$vck44/vbbw=wide 2006.257.13:16:00.79#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.13:16:00.79#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.13:16:00.79#ibcon#ireg 8 cls_cnt 0 2006.257.13:16:00.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:16:00.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:16:00.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:16:00.84#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:16:00.84#ibcon#first serial, iclass 4, count 0 2006.257.13:16:00.84#ibcon#enter sib2, iclass 4, count 0 2006.257.13:16:00.84#ibcon#flushed, iclass 4, count 0 2006.257.13:16:00.84#ibcon#about to write, iclass 4, count 0 2006.257.13:16:00.84#ibcon#wrote, iclass 4, count 0 2006.257.13:16:00.84#ibcon#about to read 3, iclass 4, count 0 2006.257.13:16:00.86#ibcon#read 3, iclass 4, count 0 2006.257.13:16:00.86#ibcon#about to read 4, iclass 4, count 0 2006.257.13:16:00.86#ibcon#read 4, iclass 4, count 0 2006.257.13:16:00.86#ibcon#about to read 5, iclass 4, count 0 2006.257.13:16:00.86#ibcon#read 5, iclass 4, count 0 2006.257.13:16:00.86#ibcon#about to read 6, iclass 4, count 0 2006.257.13:16:00.86#ibcon#read 6, iclass 4, count 0 2006.257.13:16:00.86#ibcon#end of sib2, iclass 4, count 0 2006.257.13:16:00.86#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:16:00.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:16:00.86#ibcon#[27=BW32\r\n] 2006.257.13:16:00.86#ibcon#*before write, iclass 4, count 0 2006.257.13:16:00.86#ibcon#enter sib2, iclass 4, count 0 2006.257.13:16:00.86#ibcon#flushed, iclass 4, count 0 2006.257.13:16:00.86#ibcon#about to write, iclass 4, count 0 2006.257.13:16:00.86#ibcon#wrote, iclass 4, count 0 2006.257.13:16:00.86#ibcon#about to read 3, iclass 4, count 0 2006.257.13:16:00.89#ibcon#read 3, iclass 4, count 0 2006.257.13:16:00.89#ibcon#about to read 4, iclass 4, count 0 2006.257.13:16:00.89#ibcon#read 4, iclass 4, count 0 2006.257.13:16:00.89#ibcon#about to read 5, iclass 4, count 0 2006.257.13:16:00.89#ibcon#read 5, iclass 4, count 0 2006.257.13:16:00.89#ibcon#about to read 6, iclass 4, count 0 2006.257.13:16:00.89#ibcon#read 6, iclass 4, count 0 2006.257.13:16:00.89#ibcon#end of sib2, iclass 4, count 0 2006.257.13:16:00.89#ibcon#*after write, iclass 4, count 0 2006.257.13:16:00.89#ibcon#*before return 0, iclass 4, count 0 2006.257.13:16:00.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:16:00.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:16:00.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:16:00.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:16:00.90$setupk4/ifdk4 2006.257.13:16:00.90$ifdk4/lo= 2006.257.13:16:00.90$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:16:00.90$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:16:00.90$ifdk4/patch= 2006.257.13:16:00.90$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:16:00.90$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:16:00.90$setupk4/!*+20s 2006.257.13:16:09.00#abcon#<5=/14 1.5 4.3 17.68 971013.8\r\n> 2006.257.13:16:09.02#abcon#{5=INTERFACE CLEAR} 2006.257.13:16:09.08#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:16:15.27$setupk4/"tpicd 2006.257.13:16:15.27$setupk4/echo=off 2006.257.13:16:15.27$setupk4/xlog=off 2006.257.13:16:15.27:!2006.257.13:18:34 2006.257.13:16:47.14#trakl#Source acquired 2006.257.13:16:48.14#flagr#flagr/antenna,acquired 2006.257.13:18:34.00:preob 2006.257.13:18:34.14/onsource/TRACKING 2006.257.13:18:34.14:!2006.257.13:18:44 2006.257.13:18:44.00:"tape 2006.257.13:18:44.00:"st=record 2006.257.13:18:44.00:data_valid=on 2006.257.13:18:44.00:midob 2006.257.13:18:45.14/onsource/TRACKING 2006.257.13:18:45.15/wx/17.66,1013.8,97 2006.257.13:18:45.23/cable/+6.4796E-03 2006.257.13:18:46.32/va/01,08,usb,yes,38,41 2006.257.13:18:46.32/va/02,07,usb,yes,41,42 2006.257.13:18:46.32/va/03,08,usb,yes,37,39 2006.257.13:18:46.32/va/04,07,usb,yes,42,44 2006.257.13:18:46.32/va/05,04,usb,yes,38,39 2006.257.13:18:46.32/va/06,04,usb,yes,42,42 2006.257.13:18:46.32/va/07,04,usb,yes,43,44 2006.257.13:18:46.32/va/08,04,usb,yes,36,44 2006.257.13:18:46.55/valo/01,524.99,yes,locked 2006.257.13:18:46.55/valo/02,534.99,yes,locked 2006.257.13:18:46.55/valo/03,564.99,yes,locked 2006.257.13:18:46.55/valo/04,624.99,yes,locked 2006.257.13:18:46.55/valo/05,734.99,yes,locked 2006.257.13:18:46.55/valo/06,814.99,yes,locked 2006.257.13:18:46.55/valo/07,864.99,yes,locked 2006.257.13:18:46.55/valo/08,884.99,yes,locked 2006.257.13:18:47.64/vb/01,04,usb,yes,36,33 2006.257.13:18:47.64/vb/02,05,usb,yes,34,34 2006.257.13:18:47.64/vb/03,04,usb,yes,35,39 2006.257.13:18:47.64/vb/04,05,usb,yes,36,34 2006.257.13:18:47.64/vb/05,04,usb,yes,32,35 2006.257.13:18:47.64/vb/06,04,usb,yes,37,33 2006.257.13:18:47.64/vb/07,04,usb,yes,37,37 2006.257.13:18:47.64/vb/08,04,usb,yes,34,38 2006.257.13:18:47.87/vblo/01,629.99,yes,locked 2006.257.13:18:47.87/vblo/02,634.99,yes,locked 2006.257.13:18:47.87/vblo/03,649.99,yes,locked 2006.257.13:18:47.87/vblo/04,679.99,yes,locked 2006.257.13:18:47.87/vblo/05,709.99,yes,locked 2006.257.13:18:47.87/vblo/06,719.99,yes,locked 2006.257.13:18:47.87/vblo/07,734.99,yes,locked 2006.257.13:18:47.87/vblo/08,744.99,yes,locked 2006.257.13:18:48.02/vabw/8 2006.257.13:18:48.17/vbbw/8 2006.257.13:18:48.26/xfe/off,on,15.5 2006.257.13:18:48.64/ifatt/23,28,28,28 2006.257.13:18:49.07/fmout-gps/S +4.59E-07 2006.257.13:18:49.12:!2006.257.13:20:44 2006.257.13:20:44.01:data_valid=off 2006.257.13:20:44.01:"et 2006.257.13:20:44.01:!+3s 2006.257.13:20:47.02:"tape 2006.257.13:20:47.02:postob 2006.257.13:20:47.16/cable/+6.4783E-03 2006.257.13:20:47.16/wx/17.64,1013.8,97 2006.257.13:20:47.22/fmout-gps/S +4.59E-07 2006.257.13:20:47.22:scan_name=257-1323,jd0609,160 2006.257.13:20:47.22:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.13:20:48.13#flagr#flagr/antenna,new-source 2006.257.13:20:48.13:checkk5 2006.257.13:20:48.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:20:48.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:20:49.33/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:20:49.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:20:50.11/chk_obsdata//k5ts1/T2571318??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.13:20:50.51/chk_obsdata//k5ts2/T2571318??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.13:20:50.91/chk_obsdata//k5ts3/T2571318??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.13:20:51.31/chk_obsdata//k5ts4/T2571318??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.13:20:52.03/k5log//k5ts1_log_newline 2006.257.13:20:52.73/k5log//k5ts2_log_newline 2006.257.13:20:53.44/k5log//k5ts3_log_newline 2006.257.13:20:54.15/k5log//k5ts4_log_newline 2006.257.13:20:54.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:20:54.17:setupk4=1 2006.257.13:20:54.17$setupk4/echo=on 2006.257.13:20:54.17$setupk4/pcalon 2006.257.13:20:54.17$pcalon/"no phase cal control is implemented here 2006.257.13:20:54.17$setupk4/"tpicd=stop 2006.257.13:20:54.17$setupk4/"rec=synch_on 2006.257.13:20:54.17$setupk4/"rec_mode=128 2006.257.13:20:54.17$setupk4/!* 2006.257.13:20:54.17$setupk4/recpk4 2006.257.13:20:54.17$recpk4/recpatch= 2006.257.13:20:54.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:20:54.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:20:54.18$setupk4/vck44 2006.257.13:20:54.18$vck44/valo=1,524.99 2006.257.13:20:54.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.13:20:54.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.13:20:54.18#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:54.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:54.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:54.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:54.18#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:20:54.18#ibcon#first serial, iclass 19, count 0 2006.257.13:20:54.18#ibcon#enter sib2, iclass 19, count 0 2006.257.13:20:54.18#ibcon#flushed, iclass 19, count 0 2006.257.13:20:54.18#ibcon#about to write, iclass 19, count 0 2006.257.13:20:54.18#ibcon#wrote, iclass 19, count 0 2006.257.13:20:54.18#ibcon#about to read 3, iclass 19, count 0 2006.257.13:20:54.20#ibcon#read 3, iclass 19, count 0 2006.257.13:20:54.20#ibcon#about to read 4, iclass 19, count 0 2006.257.13:20:54.20#ibcon#read 4, iclass 19, count 0 2006.257.13:20:54.20#ibcon#about to read 5, iclass 19, count 0 2006.257.13:20:54.20#ibcon#read 5, iclass 19, count 0 2006.257.13:20:54.20#ibcon#about to read 6, iclass 19, count 0 2006.257.13:20:54.20#ibcon#read 6, iclass 19, count 0 2006.257.13:20:54.20#ibcon#end of sib2, iclass 19, count 0 2006.257.13:20:54.20#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:20:54.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:20:54.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:20:54.20#ibcon#*before write, iclass 19, count 0 2006.257.13:20:54.20#ibcon#enter sib2, iclass 19, count 0 2006.257.13:20:54.20#ibcon#flushed, iclass 19, count 0 2006.257.13:20:54.20#ibcon#about to write, iclass 19, count 0 2006.257.13:20:54.20#ibcon#wrote, iclass 19, count 0 2006.257.13:20:54.20#ibcon#about to read 3, iclass 19, count 0 2006.257.13:20:54.25#ibcon#read 3, iclass 19, count 0 2006.257.13:20:54.25#ibcon#about to read 4, iclass 19, count 0 2006.257.13:20:54.25#ibcon#read 4, iclass 19, count 0 2006.257.13:20:54.25#ibcon#about to read 5, iclass 19, count 0 2006.257.13:20:54.25#ibcon#read 5, iclass 19, count 0 2006.257.13:20:54.25#ibcon#about to read 6, iclass 19, count 0 2006.257.13:20:54.25#ibcon#read 6, iclass 19, count 0 2006.257.13:20:54.25#ibcon#end of sib2, iclass 19, count 0 2006.257.13:20:54.25#ibcon#*after write, iclass 19, count 0 2006.257.13:20:54.25#ibcon#*before return 0, iclass 19, count 0 2006.257.13:20:54.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:54.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:54.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:20:54.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:20:54.25$vck44/va=1,8 2006.257.13:20:54.25#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.13:20:54.25#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.13:20:54.25#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:54.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:54.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:54.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:54.25#ibcon#enter wrdev, iclass 21, count 2 2006.257.13:20:54.25#ibcon#first serial, iclass 21, count 2 2006.257.13:20:54.25#ibcon#enter sib2, iclass 21, count 2 2006.257.13:20:54.25#ibcon#flushed, iclass 21, count 2 2006.257.13:20:54.25#ibcon#about to write, iclass 21, count 2 2006.257.13:20:54.25#ibcon#wrote, iclass 21, count 2 2006.257.13:20:54.25#ibcon#about to read 3, iclass 21, count 2 2006.257.13:20:54.27#ibcon#read 3, iclass 21, count 2 2006.257.13:20:54.27#ibcon#about to read 4, iclass 21, count 2 2006.257.13:20:54.27#ibcon#read 4, iclass 21, count 2 2006.257.13:20:54.27#ibcon#about to read 5, iclass 21, count 2 2006.257.13:20:54.27#ibcon#read 5, iclass 21, count 2 2006.257.13:20:54.27#ibcon#about to read 6, iclass 21, count 2 2006.257.13:20:54.27#ibcon#read 6, iclass 21, count 2 2006.257.13:20:54.27#ibcon#end of sib2, iclass 21, count 2 2006.257.13:20:54.27#ibcon#*mode == 0, iclass 21, count 2 2006.257.13:20:54.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.13:20:54.27#ibcon#[25=AT01-08\r\n] 2006.257.13:20:54.27#ibcon#*before write, iclass 21, count 2 2006.257.13:20:54.27#ibcon#enter sib2, iclass 21, count 2 2006.257.13:20:54.27#ibcon#flushed, iclass 21, count 2 2006.257.13:20:54.27#ibcon#about to write, iclass 21, count 2 2006.257.13:20:54.27#ibcon#wrote, iclass 21, count 2 2006.257.13:20:54.27#ibcon#about to read 3, iclass 21, count 2 2006.257.13:20:54.30#ibcon#read 3, iclass 21, count 2 2006.257.13:20:54.30#ibcon#about to read 4, iclass 21, count 2 2006.257.13:20:54.30#ibcon#read 4, iclass 21, count 2 2006.257.13:20:54.30#ibcon#about to read 5, iclass 21, count 2 2006.257.13:20:54.30#ibcon#read 5, iclass 21, count 2 2006.257.13:20:54.30#ibcon#about to read 6, iclass 21, count 2 2006.257.13:20:54.30#ibcon#read 6, iclass 21, count 2 2006.257.13:20:54.30#ibcon#end of sib2, iclass 21, count 2 2006.257.13:20:54.30#ibcon#*after write, iclass 21, count 2 2006.257.13:20:54.30#ibcon#*before return 0, iclass 21, count 2 2006.257.13:20:54.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:54.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:54.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.13:20:54.30#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:54.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:54.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:54.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:54.42#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:20:54.42#ibcon#first serial, iclass 21, count 0 2006.257.13:20:54.42#ibcon#enter sib2, iclass 21, count 0 2006.257.13:20:54.42#ibcon#flushed, iclass 21, count 0 2006.257.13:20:54.42#ibcon#about to write, iclass 21, count 0 2006.257.13:20:54.42#ibcon#wrote, iclass 21, count 0 2006.257.13:20:54.42#ibcon#about to read 3, iclass 21, count 0 2006.257.13:20:54.44#ibcon#read 3, iclass 21, count 0 2006.257.13:20:54.44#ibcon#about to read 4, iclass 21, count 0 2006.257.13:20:54.44#ibcon#read 4, iclass 21, count 0 2006.257.13:20:54.44#ibcon#about to read 5, iclass 21, count 0 2006.257.13:20:54.44#ibcon#read 5, iclass 21, count 0 2006.257.13:20:54.44#ibcon#about to read 6, iclass 21, count 0 2006.257.13:20:54.44#ibcon#read 6, iclass 21, count 0 2006.257.13:20:54.44#ibcon#end of sib2, iclass 21, count 0 2006.257.13:20:54.44#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:20:54.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:20:54.44#ibcon#[25=USB\r\n] 2006.257.13:20:54.44#ibcon#*before write, iclass 21, count 0 2006.257.13:20:54.44#ibcon#enter sib2, iclass 21, count 0 2006.257.13:20:54.44#ibcon#flushed, iclass 21, count 0 2006.257.13:20:54.44#ibcon#about to write, iclass 21, count 0 2006.257.13:20:54.44#ibcon#wrote, iclass 21, count 0 2006.257.13:20:54.44#ibcon#about to read 3, iclass 21, count 0 2006.257.13:20:54.47#ibcon#read 3, iclass 21, count 0 2006.257.13:20:54.47#ibcon#about to read 4, iclass 21, count 0 2006.257.13:20:54.47#ibcon#read 4, iclass 21, count 0 2006.257.13:20:54.47#ibcon#about to read 5, iclass 21, count 0 2006.257.13:20:54.47#ibcon#read 5, iclass 21, count 0 2006.257.13:20:54.47#ibcon#about to read 6, iclass 21, count 0 2006.257.13:20:54.47#ibcon#read 6, iclass 21, count 0 2006.257.13:20:54.47#ibcon#end of sib2, iclass 21, count 0 2006.257.13:20:54.47#ibcon#*after write, iclass 21, count 0 2006.257.13:20:54.47#ibcon#*before return 0, iclass 21, count 0 2006.257.13:20:54.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:54.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:54.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:20:54.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:20:54.47$vck44/valo=2,534.99 2006.257.13:20:54.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.13:20:54.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.13:20:54.47#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:54.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:54.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:54.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:54.47#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:20:54.47#ibcon#first serial, iclass 23, count 0 2006.257.13:20:54.47#ibcon#enter sib2, iclass 23, count 0 2006.257.13:20:54.47#ibcon#flushed, iclass 23, count 0 2006.257.13:20:54.47#ibcon#about to write, iclass 23, count 0 2006.257.13:20:54.47#ibcon#wrote, iclass 23, count 0 2006.257.13:20:54.47#ibcon#about to read 3, iclass 23, count 0 2006.257.13:20:54.49#ibcon#read 3, iclass 23, count 0 2006.257.13:20:54.49#ibcon#about to read 4, iclass 23, count 0 2006.257.13:20:54.49#ibcon#read 4, iclass 23, count 0 2006.257.13:20:54.49#ibcon#about to read 5, iclass 23, count 0 2006.257.13:20:54.49#ibcon#read 5, iclass 23, count 0 2006.257.13:20:54.49#ibcon#about to read 6, iclass 23, count 0 2006.257.13:20:54.49#ibcon#read 6, iclass 23, count 0 2006.257.13:20:54.49#ibcon#end of sib2, iclass 23, count 0 2006.257.13:20:54.49#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:20:54.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:20:54.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:20:54.49#ibcon#*before write, iclass 23, count 0 2006.257.13:20:54.49#ibcon#enter sib2, iclass 23, count 0 2006.257.13:20:54.49#ibcon#flushed, iclass 23, count 0 2006.257.13:20:54.49#ibcon#about to write, iclass 23, count 0 2006.257.13:20:54.49#ibcon#wrote, iclass 23, count 0 2006.257.13:20:54.49#ibcon#about to read 3, iclass 23, count 0 2006.257.13:20:54.53#ibcon#read 3, iclass 23, count 0 2006.257.13:20:54.53#ibcon#about to read 4, iclass 23, count 0 2006.257.13:20:54.53#ibcon#read 4, iclass 23, count 0 2006.257.13:20:54.53#ibcon#about to read 5, iclass 23, count 0 2006.257.13:20:54.53#ibcon#read 5, iclass 23, count 0 2006.257.13:20:54.53#ibcon#about to read 6, iclass 23, count 0 2006.257.13:20:54.53#ibcon#read 6, iclass 23, count 0 2006.257.13:20:54.53#ibcon#end of sib2, iclass 23, count 0 2006.257.13:20:54.53#ibcon#*after write, iclass 23, count 0 2006.257.13:20:54.53#ibcon#*before return 0, iclass 23, count 0 2006.257.13:20:54.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:54.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:54.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:20:54.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:20:54.53$vck44/va=2,7 2006.257.13:20:54.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.13:20:54.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.13:20:54.53#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:54.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:54.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:54.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:54.59#ibcon#enter wrdev, iclass 25, count 2 2006.257.13:20:54.59#ibcon#first serial, iclass 25, count 2 2006.257.13:20:54.59#ibcon#enter sib2, iclass 25, count 2 2006.257.13:20:54.59#ibcon#flushed, iclass 25, count 2 2006.257.13:20:54.59#ibcon#about to write, iclass 25, count 2 2006.257.13:20:54.59#ibcon#wrote, iclass 25, count 2 2006.257.13:20:54.59#ibcon#about to read 3, iclass 25, count 2 2006.257.13:20:54.61#ibcon#read 3, iclass 25, count 2 2006.257.13:20:54.61#ibcon#about to read 4, iclass 25, count 2 2006.257.13:20:54.61#ibcon#read 4, iclass 25, count 2 2006.257.13:20:54.61#ibcon#about to read 5, iclass 25, count 2 2006.257.13:20:54.61#ibcon#read 5, iclass 25, count 2 2006.257.13:20:54.61#ibcon#about to read 6, iclass 25, count 2 2006.257.13:20:54.61#ibcon#read 6, iclass 25, count 2 2006.257.13:20:54.61#ibcon#end of sib2, iclass 25, count 2 2006.257.13:20:54.61#ibcon#*mode == 0, iclass 25, count 2 2006.257.13:20:54.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.13:20:54.61#ibcon#[25=AT02-07\r\n] 2006.257.13:20:54.61#ibcon#*before write, iclass 25, count 2 2006.257.13:20:54.61#ibcon#enter sib2, iclass 25, count 2 2006.257.13:20:54.61#ibcon#flushed, iclass 25, count 2 2006.257.13:20:54.61#ibcon#about to write, iclass 25, count 2 2006.257.13:20:54.61#ibcon#wrote, iclass 25, count 2 2006.257.13:20:54.61#ibcon#about to read 3, iclass 25, count 2 2006.257.13:20:54.64#ibcon#read 3, iclass 25, count 2 2006.257.13:20:54.64#ibcon#about to read 4, iclass 25, count 2 2006.257.13:20:54.64#ibcon#read 4, iclass 25, count 2 2006.257.13:20:54.64#ibcon#about to read 5, iclass 25, count 2 2006.257.13:20:54.64#ibcon#read 5, iclass 25, count 2 2006.257.13:20:54.64#ibcon#about to read 6, iclass 25, count 2 2006.257.13:20:54.64#ibcon#read 6, iclass 25, count 2 2006.257.13:20:54.64#ibcon#end of sib2, iclass 25, count 2 2006.257.13:20:54.64#ibcon#*after write, iclass 25, count 2 2006.257.13:20:54.64#ibcon#*before return 0, iclass 25, count 2 2006.257.13:20:54.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:54.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:54.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.13:20:54.64#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:54.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:54.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:54.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:54.76#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:20:54.76#ibcon#first serial, iclass 25, count 0 2006.257.13:20:54.76#ibcon#enter sib2, iclass 25, count 0 2006.257.13:20:54.76#ibcon#flushed, iclass 25, count 0 2006.257.13:20:54.76#ibcon#about to write, iclass 25, count 0 2006.257.13:20:54.76#ibcon#wrote, iclass 25, count 0 2006.257.13:20:54.76#ibcon#about to read 3, iclass 25, count 0 2006.257.13:20:54.78#ibcon#read 3, iclass 25, count 0 2006.257.13:20:54.78#ibcon#about to read 4, iclass 25, count 0 2006.257.13:20:54.78#ibcon#read 4, iclass 25, count 0 2006.257.13:20:54.78#ibcon#about to read 5, iclass 25, count 0 2006.257.13:20:54.78#ibcon#read 5, iclass 25, count 0 2006.257.13:20:54.78#ibcon#about to read 6, iclass 25, count 0 2006.257.13:20:54.78#ibcon#read 6, iclass 25, count 0 2006.257.13:20:54.78#ibcon#end of sib2, iclass 25, count 0 2006.257.13:20:54.78#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:20:54.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:20:54.78#ibcon#[25=USB\r\n] 2006.257.13:20:54.78#ibcon#*before write, iclass 25, count 0 2006.257.13:20:54.78#ibcon#enter sib2, iclass 25, count 0 2006.257.13:20:54.78#ibcon#flushed, iclass 25, count 0 2006.257.13:20:54.78#ibcon#about to write, iclass 25, count 0 2006.257.13:20:54.78#ibcon#wrote, iclass 25, count 0 2006.257.13:20:54.78#ibcon#about to read 3, iclass 25, count 0 2006.257.13:20:54.81#ibcon#read 3, iclass 25, count 0 2006.257.13:20:54.81#ibcon#about to read 4, iclass 25, count 0 2006.257.13:20:54.81#ibcon#read 4, iclass 25, count 0 2006.257.13:20:54.81#ibcon#about to read 5, iclass 25, count 0 2006.257.13:20:54.81#ibcon#read 5, iclass 25, count 0 2006.257.13:20:54.81#ibcon#about to read 6, iclass 25, count 0 2006.257.13:20:54.81#ibcon#read 6, iclass 25, count 0 2006.257.13:20:54.81#ibcon#end of sib2, iclass 25, count 0 2006.257.13:20:54.81#ibcon#*after write, iclass 25, count 0 2006.257.13:20:54.81#ibcon#*before return 0, iclass 25, count 0 2006.257.13:20:54.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:54.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:54.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:20:54.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:20:54.81$vck44/valo=3,564.99 2006.257.13:20:54.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.13:20:54.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.13:20:54.81#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:54.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:54.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:54.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:54.81#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:20:54.81#ibcon#first serial, iclass 27, count 0 2006.257.13:20:54.81#ibcon#enter sib2, iclass 27, count 0 2006.257.13:20:54.81#ibcon#flushed, iclass 27, count 0 2006.257.13:20:54.81#ibcon#about to write, iclass 27, count 0 2006.257.13:20:54.81#ibcon#wrote, iclass 27, count 0 2006.257.13:20:54.81#ibcon#about to read 3, iclass 27, count 0 2006.257.13:20:54.83#ibcon#read 3, iclass 27, count 0 2006.257.13:20:54.83#ibcon#about to read 4, iclass 27, count 0 2006.257.13:20:54.83#ibcon#read 4, iclass 27, count 0 2006.257.13:20:54.83#ibcon#about to read 5, iclass 27, count 0 2006.257.13:20:54.83#ibcon#read 5, iclass 27, count 0 2006.257.13:20:54.83#ibcon#about to read 6, iclass 27, count 0 2006.257.13:20:54.83#ibcon#read 6, iclass 27, count 0 2006.257.13:20:54.83#ibcon#end of sib2, iclass 27, count 0 2006.257.13:20:54.83#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:20:54.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:20:54.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:20:54.83#ibcon#*before write, iclass 27, count 0 2006.257.13:20:54.83#ibcon#enter sib2, iclass 27, count 0 2006.257.13:20:54.83#ibcon#flushed, iclass 27, count 0 2006.257.13:20:54.83#ibcon#about to write, iclass 27, count 0 2006.257.13:20:54.83#ibcon#wrote, iclass 27, count 0 2006.257.13:20:54.83#ibcon#about to read 3, iclass 27, count 0 2006.257.13:20:54.87#ibcon#read 3, iclass 27, count 0 2006.257.13:20:54.87#ibcon#about to read 4, iclass 27, count 0 2006.257.13:20:54.87#ibcon#read 4, iclass 27, count 0 2006.257.13:20:54.87#ibcon#about to read 5, iclass 27, count 0 2006.257.13:20:54.87#ibcon#read 5, iclass 27, count 0 2006.257.13:20:54.87#ibcon#about to read 6, iclass 27, count 0 2006.257.13:20:54.87#ibcon#read 6, iclass 27, count 0 2006.257.13:20:54.87#ibcon#end of sib2, iclass 27, count 0 2006.257.13:20:54.87#ibcon#*after write, iclass 27, count 0 2006.257.13:20:54.87#ibcon#*before return 0, iclass 27, count 0 2006.257.13:20:54.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:54.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:54.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:20:54.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:20:54.87$vck44/va=3,8 2006.257.13:20:54.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.13:20:54.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.13:20:54.87#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:54.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:54.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:54.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:54.93#ibcon#enter wrdev, iclass 29, count 2 2006.257.13:20:54.93#ibcon#first serial, iclass 29, count 2 2006.257.13:20:54.93#ibcon#enter sib2, iclass 29, count 2 2006.257.13:20:54.93#ibcon#flushed, iclass 29, count 2 2006.257.13:20:54.93#ibcon#about to write, iclass 29, count 2 2006.257.13:20:54.93#ibcon#wrote, iclass 29, count 2 2006.257.13:20:54.93#ibcon#about to read 3, iclass 29, count 2 2006.257.13:20:54.95#ibcon#read 3, iclass 29, count 2 2006.257.13:20:54.95#ibcon#about to read 4, iclass 29, count 2 2006.257.13:20:54.95#ibcon#read 4, iclass 29, count 2 2006.257.13:20:54.95#ibcon#about to read 5, iclass 29, count 2 2006.257.13:20:54.95#ibcon#read 5, iclass 29, count 2 2006.257.13:20:54.95#ibcon#about to read 6, iclass 29, count 2 2006.257.13:20:54.95#ibcon#read 6, iclass 29, count 2 2006.257.13:20:54.95#ibcon#end of sib2, iclass 29, count 2 2006.257.13:20:54.95#ibcon#*mode == 0, iclass 29, count 2 2006.257.13:20:54.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.13:20:54.95#ibcon#[25=AT03-08\r\n] 2006.257.13:20:54.95#ibcon#*before write, iclass 29, count 2 2006.257.13:20:54.95#ibcon#enter sib2, iclass 29, count 2 2006.257.13:20:54.95#ibcon#flushed, iclass 29, count 2 2006.257.13:20:54.95#ibcon#about to write, iclass 29, count 2 2006.257.13:20:54.95#ibcon#wrote, iclass 29, count 2 2006.257.13:20:54.95#ibcon#about to read 3, iclass 29, count 2 2006.257.13:20:54.98#ibcon#read 3, iclass 29, count 2 2006.257.13:20:54.98#ibcon#about to read 4, iclass 29, count 2 2006.257.13:20:54.98#ibcon#read 4, iclass 29, count 2 2006.257.13:20:54.98#ibcon#about to read 5, iclass 29, count 2 2006.257.13:20:54.98#ibcon#read 5, iclass 29, count 2 2006.257.13:20:54.98#ibcon#about to read 6, iclass 29, count 2 2006.257.13:20:54.98#ibcon#read 6, iclass 29, count 2 2006.257.13:20:54.98#ibcon#end of sib2, iclass 29, count 2 2006.257.13:20:54.98#ibcon#*after write, iclass 29, count 2 2006.257.13:20:54.98#ibcon#*before return 0, iclass 29, count 2 2006.257.13:20:54.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:54.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:54.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.13:20:54.98#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:54.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:55.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:55.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:55.10#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:20:55.10#ibcon#first serial, iclass 29, count 0 2006.257.13:20:55.10#ibcon#enter sib2, iclass 29, count 0 2006.257.13:20:55.10#ibcon#flushed, iclass 29, count 0 2006.257.13:20:55.10#ibcon#about to write, iclass 29, count 0 2006.257.13:20:55.10#ibcon#wrote, iclass 29, count 0 2006.257.13:20:55.10#ibcon#about to read 3, iclass 29, count 0 2006.257.13:20:55.12#ibcon#read 3, iclass 29, count 0 2006.257.13:20:55.12#ibcon#about to read 4, iclass 29, count 0 2006.257.13:20:55.12#ibcon#read 4, iclass 29, count 0 2006.257.13:20:55.12#ibcon#about to read 5, iclass 29, count 0 2006.257.13:20:55.12#ibcon#read 5, iclass 29, count 0 2006.257.13:20:55.12#ibcon#about to read 6, iclass 29, count 0 2006.257.13:20:55.12#ibcon#read 6, iclass 29, count 0 2006.257.13:20:55.12#ibcon#end of sib2, iclass 29, count 0 2006.257.13:20:55.12#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:20:55.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:20:55.12#ibcon#[25=USB\r\n] 2006.257.13:20:55.12#ibcon#*before write, iclass 29, count 0 2006.257.13:20:55.12#ibcon#enter sib2, iclass 29, count 0 2006.257.13:20:55.12#ibcon#flushed, iclass 29, count 0 2006.257.13:20:55.12#ibcon#about to write, iclass 29, count 0 2006.257.13:20:55.12#ibcon#wrote, iclass 29, count 0 2006.257.13:20:55.12#ibcon#about to read 3, iclass 29, count 0 2006.257.13:20:55.15#ibcon#read 3, iclass 29, count 0 2006.257.13:20:55.15#ibcon#about to read 4, iclass 29, count 0 2006.257.13:20:55.15#ibcon#read 4, iclass 29, count 0 2006.257.13:20:55.15#ibcon#about to read 5, iclass 29, count 0 2006.257.13:20:55.15#ibcon#read 5, iclass 29, count 0 2006.257.13:20:55.15#ibcon#about to read 6, iclass 29, count 0 2006.257.13:20:55.15#ibcon#read 6, iclass 29, count 0 2006.257.13:20:55.15#ibcon#end of sib2, iclass 29, count 0 2006.257.13:20:55.15#ibcon#*after write, iclass 29, count 0 2006.257.13:20:55.15#ibcon#*before return 0, iclass 29, count 0 2006.257.13:20:55.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:55.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:55.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:20:55.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:20:55.15$vck44/valo=4,624.99 2006.257.13:20:55.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.13:20:55.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.13:20:55.15#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:55.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:55.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:55.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:55.15#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:20:55.15#ibcon#first serial, iclass 31, count 0 2006.257.13:20:55.15#ibcon#enter sib2, iclass 31, count 0 2006.257.13:20:55.15#ibcon#flushed, iclass 31, count 0 2006.257.13:20:55.15#ibcon#about to write, iclass 31, count 0 2006.257.13:20:55.15#ibcon#wrote, iclass 31, count 0 2006.257.13:20:55.15#ibcon#about to read 3, iclass 31, count 0 2006.257.13:20:55.17#ibcon#read 3, iclass 31, count 0 2006.257.13:20:55.17#ibcon#about to read 4, iclass 31, count 0 2006.257.13:20:55.17#ibcon#read 4, iclass 31, count 0 2006.257.13:20:55.17#ibcon#about to read 5, iclass 31, count 0 2006.257.13:20:55.17#ibcon#read 5, iclass 31, count 0 2006.257.13:20:55.17#ibcon#about to read 6, iclass 31, count 0 2006.257.13:20:55.17#ibcon#read 6, iclass 31, count 0 2006.257.13:20:55.17#ibcon#end of sib2, iclass 31, count 0 2006.257.13:20:55.17#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:20:55.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:20:55.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:20:55.17#ibcon#*before write, iclass 31, count 0 2006.257.13:20:55.17#ibcon#enter sib2, iclass 31, count 0 2006.257.13:20:55.17#ibcon#flushed, iclass 31, count 0 2006.257.13:20:55.17#ibcon#about to write, iclass 31, count 0 2006.257.13:20:55.17#ibcon#wrote, iclass 31, count 0 2006.257.13:20:55.17#ibcon#about to read 3, iclass 31, count 0 2006.257.13:20:55.21#ibcon#read 3, iclass 31, count 0 2006.257.13:20:55.21#ibcon#about to read 4, iclass 31, count 0 2006.257.13:20:55.21#ibcon#read 4, iclass 31, count 0 2006.257.13:20:55.21#ibcon#about to read 5, iclass 31, count 0 2006.257.13:20:55.21#ibcon#read 5, iclass 31, count 0 2006.257.13:20:55.21#ibcon#about to read 6, iclass 31, count 0 2006.257.13:20:55.21#ibcon#read 6, iclass 31, count 0 2006.257.13:20:55.21#ibcon#end of sib2, iclass 31, count 0 2006.257.13:20:55.21#ibcon#*after write, iclass 31, count 0 2006.257.13:20:55.21#ibcon#*before return 0, iclass 31, count 0 2006.257.13:20:55.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:55.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:55.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:20:55.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:20:55.21$vck44/va=4,7 2006.257.13:20:55.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.13:20:55.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.13:20:55.21#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:55.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:55.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:55.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:55.27#ibcon#enter wrdev, iclass 33, count 2 2006.257.13:20:55.27#ibcon#first serial, iclass 33, count 2 2006.257.13:20:55.27#ibcon#enter sib2, iclass 33, count 2 2006.257.13:20:55.27#ibcon#flushed, iclass 33, count 2 2006.257.13:20:55.27#ibcon#about to write, iclass 33, count 2 2006.257.13:20:55.27#ibcon#wrote, iclass 33, count 2 2006.257.13:20:55.27#ibcon#about to read 3, iclass 33, count 2 2006.257.13:20:55.29#ibcon#read 3, iclass 33, count 2 2006.257.13:20:55.29#ibcon#about to read 4, iclass 33, count 2 2006.257.13:20:55.29#ibcon#read 4, iclass 33, count 2 2006.257.13:20:55.29#ibcon#about to read 5, iclass 33, count 2 2006.257.13:20:55.29#ibcon#read 5, iclass 33, count 2 2006.257.13:20:55.29#ibcon#about to read 6, iclass 33, count 2 2006.257.13:20:55.29#ibcon#read 6, iclass 33, count 2 2006.257.13:20:55.29#ibcon#end of sib2, iclass 33, count 2 2006.257.13:20:55.29#ibcon#*mode == 0, iclass 33, count 2 2006.257.13:20:55.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.13:20:55.29#ibcon#[25=AT04-07\r\n] 2006.257.13:20:55.29#ibcon#*before write, iclass 33, count 2 2006.257.13:20:55.29#ibcon#enter sib2, iclass 33, count 2 2006.257.13:20:55.29#ibcon#flushed, iclass 33, count 2 2006.257.13:20:55.29#ibcon#about to write, iclass 33, count 2 2006.257.13:20:55.29#ibcon#wrote, iclass 33, count 2 2006.257.13:20:55.29#ibcon#about to read 3, iclass 33, count 2 2006.257.13:20:55.32#ibcon#read 3, iclass 33, count 2 2006.257.13:20:55.32#ibcon#about to read 4, iclass 33, count 2 2006.257.13:20:55.32#ibcon#read 4, iclass 33, count 2 2006.257.13:20:55.32#ibcon#about to read 5, iclass 33, count 2 2006.257.13:20:55.32#ibcon#read 5, iclass 33, count 2 2006.257.13:20:55.32#ibcon#about to read 6, iclass 33, count 2 2006.257.13:20:55.32#ibcon#read 6, iclass 33, count 2 2006.257.13:20:55.32#ibcon#end of sib2, iclass 33, count 2 2006.257.13:20:55.32#ibcon#*after write, iclass 33, count 2 2006.257.13:20:55.32#ibcon#*before return 0, iclass 33, count 2 2006.257.13:20:55.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:55.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:55.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.13:20:55.32#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:55.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:55.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:55.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:55.44#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:20:55.44#ibcon#first serial, iclass 33, count 0 2006.257.13:20:55.44#ibcon#enter sib2, iclass 33, count 0 2006.257.13:20:55.44#ibcon#flushed, iclass 33, count 0 2006.257.13:20:55.44#ibcon#about to write, iclass 33, count 0 2006.257.13:20:55.44#ibcon#wrote, iclass 33, count 0 2006.257.13:20:55.44#ibcon#about to read 3, iclass 33, count 0 2006.257.13:20:55.46#ibcon#read 3, iclass 33, count 0 2006.257.13:20:55.46#ibcon#about to read 4, iclass 33, count 0 2006.257.13:20:55.46#ibcon#read 4, iclass 33, count 0 2006.257.13:20:55.46#ibcon#about to read 5, iclass 33, count 0 2006.257.13:20:55.46#ibcon#read 5, iclass 33, count 0 2006.257.13:20:55.46#ibcon#about to read 6, iclass 33, count 0 2006.257.13:20:55.46#ibcon#read 6, iclass 33, count 0 2006.257.13:20:55.46#ibcon#end of sib2, iclass 33, count 0 2006.257.13:20:55.46#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:20:55.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:20:55.46#ibcon#[25=USB\r\n] 2006.257.13:20:55.46#ibcon#*before write, iclass 33, count 0 2006.257.13:20:55.46#ibcon#enter sib2, iclass 33, count 0 2006.257.13:20:55.46#ibcon#flushed, iclass 33, count 0 2006.257.13:20:55.46#ibcon#about to write, iclass 33, count 0 2006.257.13:20:55.46#ibcon#wrote, iclass 33, count 0 2006.257.13:20:55.46#ibcon#about to read 3, iclass 33, count 0 2006.257.13:20:55.49#ibcon#read 3, iclass 33, count 0 2006.257.13:20:55.49#ibcon#about to read 4, iclass 33, count 0 2006.257.13:20:55.49#ibcon#read 4, iclass 33, count 0 2006.257.13:20:55.49#ibcon#about to read 5, iclass 33, count 0 2006.257.13:20:55.49#ibcon#read 5, iclass 33, count 0 2006.257.13:20:55.49#ibcon#about to read 6, iclass 33, count 0 2006.257.13:20:55.49#ibcon#read 6, iclass 33, count 0 2006.257.13:20:55.49#ibcon#end of sib2, iclass 33, count 0 2006.257.13:20:55.49#ibcon#*after write, iclass 33, count 0 2006.257.13:20:55.49#ibcon#*before return 0, iclass 33, count 0 2006.257.13:20:55.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:55.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:55.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:20:55.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:20:55.49$vck44/valo=5,734.99 2006.257.13:20:55.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.13:20:55.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.13:20:55.49#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:55.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:55.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:55.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:55.49#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:20:55.49#ibcon#first serial, iclass 35, count 0 2006.257.13:20:55.49#ibcon#enter sib2, iclass 35, count 0 2006.257.13:20:55.49#ibcon#flushed, iclass 35, count 0 2006.257.13:20:55.49#ibcon#about to write, iclass 35, count 0 2006.257.13:20:55.49#ibcon#wrote, iclass 35, count 0 2006.257.13:20:55.49#ibcon#about to read 3, iclass 35, count 0 2006.257.13:20:55.51#ibcon#read 3, iclass 35, count 0 2006.257.13:20:55.51#ibcon#about to read 4, iclass 35, count 0 2006.257.13:20:55.51#ibcon#read 4, iclass 35, count 0 2006.257.13:20:55.51#ibcon#about to read 5, iclass 35, count 0 2006.257.13:20:55.51#ibcon#read 5, iclass 35, count 0 2006.257.13:20:55.51#ibcon#about to read 6, iclass 35, count 0 2006.257.13:20:55.51#ibcon#read 6, iclass 35, count 0 2006.257.13:20:55.51#ibcon#end of sib2, iclass 35, count 0 2006.257.13:20:55.51#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:20:55.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:20:55.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:20:55.51#ibcon#*before write, iclass 35, count 0 2006.257.13:20:55.51#ibcon#enter sib2, iclass 35, count 0 2006.257.13:20:55.51#ibcon#flushed, iclass 35, count 0 2006.257.13:20:55.51#ibcon#about to write, iclass 35, count 0 2006.257.13:20:55.51#ibcon#wrote, iclass 35, count 0 2006.257.13:20:55.51#ibcon#about to read 3, iclass 35, count 0 2006.257.13:20:55.55#ibcon#read 3, iclass 35, count 0 2006.257.13:20:55.55#ibcon#about to read 4, iclass 35, count 0 2006.257.13:20:55.55#ibcon#read 4, iclass 35, count 0 2006.257.13:20:55.55#ibcon#about to read 5, iclass 35, count 0 2006.257.13:20:55.55#ibcon#read 5, iclass 35, count 0 2006.257.13:20:55.55#ibcon#about to read 6, iclass 35, count 0 2006.257.13:20:55.55#ibcon#read 6, iclass 35, count 0 2006.257.13:20:55.55#ibcon#end of sib2, iclass 35, count 0 2006.257.13:20:55.55#ibcon#*after write, iclass 35, count 0 2006.257.13:20:55.55#ibcon#*before return 0, iclass 35, count 0 2006.257.13:20:55.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:55.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:55.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:20:55.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:20:55.55$vck44/va=5,4 2006.257.13:20:55.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.13:20:55.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.13:20:55.55#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:55.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:55.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:55.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:55.61#ibcon#enter wrdev, iclass 37, count 2 2006.257.13:20:55.61#ibcon#first serial, iclass 37, count 2 2006.257.13:20:55.61#ibcon#enter sib2, iclass 37, count 2 2006.257.13:20:55.61#ibcon#flushed, iclass 37, count 2 2006.257.13:20:55.61#ibcon#about to write, iclass 37, count 2 2006.257.13:20:55.61#ibcon#wrote, iclass 37, count 2 2006.257.13:20:55.61#ibcon#about to read 3, iclass 37, count 2 2006.257.13:20:55.63#ibcon#read 3, iclass 37, count 2 2006.257.13:20:55.63#ibcon#about to read 4, iclass 37, count 2 2006.257.13:20:55.63#ibcon#read 4, iclass 37, count 2 2006.257.13:20:55.63#ibcon#about to read 5, iclass 37, count 2 2006.257.13:20:55.63#ibcon#read 5, iclass 37, count 2 2006.257.13:20:55.63#ibcon#about to read 6, iclass 37, count 2 2006.257.13:20:55.63#ibcon#read 6, iclass 37, count 2 2006.257.13:20:55.63#ibcon#end of sib2, iclass 37, count 2 2006.257.13:20:55.63#ibcon#*mode == 0, iclass 37, count 2 2006.257.13:20:55.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.13:20:55.63#ibcon#[25=AT05-04\r\n] 2006.257.13:20:55.63#ibcon#*before write, iclass 37, count 2 2006.257.13:20:55.63#ibcon#enter sib2, iclass 37, count 2 2006.257.13:20:55.63#ibcon#flushed, iclass 37, count 2 2006.257.13:20:55.63#ibcon#about to write, iclass 37, count 2 2006.257.13:20:55.63#ibcon#wrote, iclass 37, count 2 2006.257.13:20:55.63#ibcon#about to read 3, iclass 37, count 2 2006.257.13:20:55.66#ibcon#read 3, iclass 37, count 2 2006.257.13:20:55.66#ibcon#about to read 4, iclass 37, count 2 2006.257.13:20:55.66#ibcon#read 4, iclass 37, count 2 2006.257.13:20:55.66#ibcon#about to read 5, iclass 37, count 2 2006.257.13:20:55.66#ibcon#read 5, iclass 37, count 2 2006.257.13:20:55.66#ibcon#about to read 6, iclass 37, count 2 2006.257.13:20:55.66#ibcon#read 6, iclass 37, count 2 2006.257.13:20:55.66#ibcon#end of sib2, iclass 37, count 2 2006.257.13:20:55.66#ibcon#*after write, iclass 37, count 2 2006.257.13:20:55.66#ibcon#*before return 0, iclass 37, count 2 2006.257.13:20:55.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:55.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:55.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.13:20:55.66#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:55.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:55.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:55.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:55.78#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:20:55.78#ibcon#first serial, iclass 37, count 0 2006.257.13:20:55.78#ibcon#enter sib2, iclass 37, count 0 2006.257.13:20:55.78#ibcon#flushed, iclass 37, count 0 2006.257.13:20:55.78#ibcon#about to write, iclass 37, count 0 2006.257.13:20:55.78#ibcon#wrote, iclass 37, count 0 2006.257.13:20:55.78#ibcon#about to read 3, iclass 37, count 0 2006.257.13:20:55.80#ibcon#read 3, iclass 37, count 0 2006.257.13:20:55.80#ibcon#about to read 4, iclass 37, count 0 2006.257.13:20:55.80#ibcon#read 4, iclass 37, count 0 2006.257.13:20:55.80#ibcon#about to read 5, iclass 37, count 0 2006.257.13:20:55.80#ibcon#read 5, iclass 37, count 0 2006.257.13:20:55.80#ibcon#about to read 6, iclass 37, count 0 2006.257.13:20:55.80#ibcon#read 6, iclass 37, count 0 2006.257.13:20:55.80#ibcon#end of sib2, iclass 37, count 0 2006.257.13:20:55.80#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:20:55.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:20:55.80#ibcon#[25=USB\r\n] 2006.257.13:20:55.80#ibcon#*before write, iclass 37, count 0 2006.257.13:20:55.80#ibcon#enter sib2, iclass 37, count 0 2006.257.13:20:55.80#ibcon#flushed, iclass 37, count 0 2006.257.13:20:55.80#ibcon#about to write, iclass 37, count 0 2006.257.13:20:55.80#ibcon#wrote, iclass 37, count 0 2006.257.13:20:55.80#ibcon#about to read 3, iclass 37, count 0 2006.257.13:20:55.83#ibcon#read 3, iclass 37, count 0 2006.257.13:20:55.83#ibcon#about to read 4, iclass 37, count 0 2006.257.13:20:55.83#ibcon#read 4, iclass 37, count 0 2006.257.13:20:55.83#ibcon#about to read 5, iclass 37, count 0 2006.257.13:20:55.83#ibcon#read 5, iclass 37, count 0 2006.257.13:20:55.83#ibcon#about to read 6, iclass 37, count 0 2006.257.13:20:55.83#ibcon#read 6, iclass 37, count 0 2006.257.13:20:55.83#ibcon#end of sib2, iclass 37, count 0 2006.257.13:20:55.83#ibcon#*after write, iclass 37, count 0 2006.257.13:20:55.83#ibcon#*before return 0, iclass 37, count 0 2006.257.13:20:55.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:55.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:55.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:20:55.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:20:55.83$vck44/valo=6,814.99 2006.257.13:20:55.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:20:55.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:20:55.83#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:55.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:55.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:55.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:55.83#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:20:55.83#ibcon#first serial, iclass 39, count 0 2006.257.13:20:55.83#ibcon#enter sib2, iclass 39, count 0 2006.257.13:20:55.83#ibcon#flushed, iclass 39, count 0 2006.257.13:20:55.83#ibcon#about to write, iclass 39, count 0 2006.257.13:20:55.83#ibcon#wrote, iclass 39, count 0 2006.257.13:20:55.83#ibcon#about to read 3, iclass 39, count 0 2006.257.13:20:55.85#ibcon#read 3, iclass 39, count 0 2006.257.13:20:55.85#ibcon#about to read 4, iclass 39, count 0 2006.257.13:20:55.85#ibcon#read 4, iclass 39, count 0 2006.257.13:20:55.85#ibcon#about to read 5, iclass 39, count 0 2006.257.13:20:55.85#ibcon#read 5, iclass 39, count 0 2006.257.13:20:55.85#ibcon#about to read 6, iclass 39, count 0 2006.257.13:20:55.85#ibcon#read 6, iclass 39, count 0 2006.257.13:20:55.85#ibcon#end of sib2, iclass 39, count 0 2006.257.13:20:55.85#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:20:55.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:20:55.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:20:55.85#ibcon#*before write, iclass 39, count 0 2006.257.13:20:55.85#ibcon#enter sib2, iclass 39, count 0 2006.257.13:20:55.85#ibcon#flushed, iclass 39, count 0 2006.257.13:20:55.85#ibcon#about to write, iclass 39, count 0 2006.257.13:20:55.85#ibcon#wrote, iclass 39, count 0 2006.257.13:20:55.85#ibcon#about to read 3, iclass 39, count 0 2006.257.13:20:55.89#ibcon#read 3, iclass 39, count 0 2006.257.13:20:55.89#ibcon#about to read 4, iclass 39, count 0 2006.257.13:20:55.89#ibcon#read 4, iclass 39, count 0 2006.257.13:20:55.89#ibcon#about to read 5, iclass 39, count 0 2006.257.13:20:55.89#ibcon#read 5, iclass 39, count 0 2006.257.13:20:55.89#ibcon#about to read 6, iclass 39, count 0 2006.257.13:20:55.89#ibcon#read 6, iclass 39, count 0 2006.257.13:20:55.89#ibcon#end of sib2, iclass 39, count 0 2006.257.13:20:55.89#ibcon#*after write, iclass 39, count 0 2006.257.13:20:55.89#ibcon#*before return 0, iclass 39, count 0 2006.257.13:20:55.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:55.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:55.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:20:55.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:20:55.89$vck44/va=6,4 2006.257.13:20:55.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.13:20:55.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.13:20:55.89#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:55.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:55.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:55.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:55.95#ibcon#enter wrdev, iclass 3, count 2 2006.257.13:20:55.95#ibcon#first serial, iclass 3, count 2 2006.257.13:20:55.95#ibcon#enter sib2, iclass 3, count 2 2006.257.13:20:55.95#ibcon#flushed, iclass 3, count 2 2006.257.13:20:55.95#ibcon#about to write, iclass 3, count 2 2006.257.13:20:55.95#ibcon#wrote, iclass 3, count 2 2006.257.13:20:55.95#ibcon#about to read 3, iclass 3, count 2 2006.257.13:20:55.97#ibcon#read 3, iclass 3, count 2 2006.257.13:20:55.97#ibcon#about to read 4, iclass 3, count 2 2006.257.13:20:55.97#ibcon#read 4, iclass 3, count 2 2006.257.13:20:55.97#ibcon#about to read 5, iclass 3, count 2 2006.257.13:20:55.97#ibcon#read 5, iclass 3, count 2 2006.257.13:20:55.97#ibcon#about to read 6, iclass 3, count 2 2006.257.13:20:55.97#ibcon#read 6, iclass 3, count 2 2006.257.13:20:55.97#ibcon#end of sib2, iclass 3, count 2 2006.257.13:20:55.97#ibcon#*mode == 0, iclass 3, count 2 2006.257.13:20:55.97#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.13:20:55.97#ibcon#[25=AT06-04\r\n] 2006.257.13:20:55.97#ibcon#*before write, iclass 3, count 2 2006.257.13:20:55.97#ibcon#enter sib2, iclass 3, count 2 2006.257.13:20:55.97#ibcon#flushed, iclass 3, count 2 2006.257.13:20:55.97#ibcon#about to write, iclass 3, count 2 2006.257.13:20:55.97#ibcon#wrote, iclass 3, count 2 2006.257.13:20:55.97#ibcon#about to read 3, iclass 3, count 2 2006.257.13:20:56.00#ibcon#read 3, iclass 3, count 2 2006.257.13:20:56.00#ibcon#about to read 4, iclass 3, count 2 2006.257.13:20:56.00#ibcon#read 4, iclass 3, count 2 2006.257.13:20:56.00#ibcon#about to read 5, iclass 3, count 2 2006.257.13:20:56.00#ibcon#read 5, iclass 3, count 2 2006.257.13:20:56.00#ibcon#about to read 6, iclass 3, count 2 2006.257.13:20:56.00#ibcon#read 6, iclass 3, count 2 2006.257.13:20:56.00#ibcon#end of sib2, iclass 3, count 2 2006.257.13:20:56.00#ibcon#*after write, iclass 3, count 2 2006.257.13:20:56.00#ibcon#*before return 0, iclass 3, count 2 2006.257.13:20:56.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:56.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:56.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.13:20:56.00#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:56.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:56.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:56.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:56.12#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:20:56.12#ibcon#first serial, iclass 3, count 0 2006.257.13:20:56.12#ibcon#enter sib2, iclass 3, count 0 2006.257.13:20:56.12#ibcon#flushed, iclass 3, count 0 2006.257.13:20:56.12#ibcon#about to write, iclass 3, count 0 2006.257.13:20:56.12#ibcon#wrote, iclass 3, count 0 2006.257.13:20:56.12#ibcon#about to read 3, iclass 3, count 0 2006.257.13:20:56.14#ibcon#read 3, iclass 3, count 0 2006.257.13:20:56.14#ibcon#about to read 4, iclass 3, count 0 2006.257.13:20:56.14#ibcon#read 4, iclass 3, count 0 2006.257.13:20:56.14#ibcon#about to read 5, iclass 3, count 0 2006.257.13:20:56.14#ibcon#read 5, iclass 3, count 0 2006.257.13:20:56.14#ibcon#about to read 6, iclass 3, count 0 2006.257.13:20:56.14#ibcon#read 6, iclass 3, count 0 2006.257.13:20:56.14#ibcon#end of sib2, iclass 3, count 0 2006.257.13:20:56.14#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:20:56.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:20:56.14#ibcon#[25=USB\r\n] 2006.257.13:20:56.14#ibcon#*before write, iclass 3, count 0 2006.257.13:20:56.14#ibcon#enter sib2, iclass 3, count 0 2006.257.13:20:56.14#ibcon#flushed, iclass 3, count 0 2006.257.13:20:56.14#ibcon#about to write, iclass 3, count 0 2006.257.13:20:56.14#ibcon#wrote, iclass 3, count 0 2006.257.13:20:56.14#ibcon#about to read 3, iclass 3, count 0 2006.257.13:20:56.17#ibcon#read 3, iclass 3, count 0 2006.257.13:20:56.17#ibcon#about to read 4, iclass 3, count 0 2006.257.13:20:56.17#ibcon#read 4, iclass 3, count 0 2006.257.13:20:56.17#ibcon#about to read 5, iclass 3, count 0 2006.257.13:20:56.17#ibcon#read 5, iclass 3, count 0 2006.257.13:20:56.17#ibcon#about to read 6, iclass 3, count 0 2006.257.13:20:56.17#ibcon#read 6, iclass 3, count 0 2006.257.13:20:56.17#ibcon#end of sib2, iclass 3, count 0 2006.257.13:20:56.17#ibcon#*after write, iclass 3, count 0 2006.257.13:20:56.17#ibcon#*before return 0, iclass 3, count 0 2006.257.13:20:56.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:56.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:56.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:20:56.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:20:56.17$vck44/valo=7,864.99 2006.257.13:20:56.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.13:20:56.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.13:20:56.17#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:56.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:56.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:56.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:56.17#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:20:56.17#ibcon#first serial, iclass 5, count 0 2006.257.13:20:56.17#ibcon#enter sib2, iclass 5, count 0 2006.257.13:20:56.17#ibcon#flushed, iclass 5, count 0 2006.257.13:20:56.17#ibcon#about to write, iclass 5, count 0 2006.257.13:20:56.17#ibcon#wrote, iclass 5, count 0 2006.257.13:20:56.17#ibcon#about to read 3, iclass 5, count 0 2006.257.13:20:56.19#ibcon#read 3, iclass 5, count 0 2006.257.13:20:56.19#ibcon#about to read 4, iclass 5, count 0 2006.257.13:20:56.19#ibcon#read 4, iclass 5, count 0 2006.257.13:20:56.19#ibcon#about to read 5, iclass 5, count 0 2006.257.13:20:56.19#ibcon#read 5, iclass 5, count 0 2006.257.13:20:56.19#ibcon#about to read 6, iclass 5, count 0 2006.257.13:20:56.19#ibcon#read 6, iclass 5, count 0 2006.257.13:20:56.19#ibcon#end of sib2, iclass 5, count 0 2006.257.13:20:56.19#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:20:56.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:20:56.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:20:56.19#ibcon#*before write, iclass 5, count 0 2006.257.13:20:56.19#ibcon#enter sib2, iclass 5, count 0 2006.257.13:20:56.19#ibcon#flushed, iclass 5, count 0 2006.257.13:20:56.19#ibcon#about to write, iclass 5, count 0 2006.257.13:20:56.19#ibcon#wrote, iclass 5, count 0 2006.257.13:20:56.19#ibcon#about to read 3, iclass 5, count 0 2006.257.13:20:56.23#ibcon#read 3, iclass 5, count 0 2006.257.13:20:56.23#ibcon#about to read 4, iclass 5, count 0 2006.257.13:20:56.23#ibcon#read 4, iclass 5, count 0 2006.257.13:20:56.23#ibcon#about to read 5, iclass 5, count 0 2006.257.13:20:56.23#ibcon#read 5, iclass 5, count 0 2006.257.13:20:56.23#ibcon#about to read 6, iclass 5, count 0 2006.257.13:20:56.23#ibcon#read 6, iclass 5, count 0 2006.257.13:20:56.23#ibcon#end of sib2, iclass 5, count 0 2006.257.13:20:56.23#ibcon#*after write, iclass 5, count 0 2006.257.13:20:56.23#ibcon#*before return 0, iclass 5, count 0 2006.257.13:20:56.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:56.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:56.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:20:56.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:20:56.23$vck44/va=7,4 2006.257.13:20:56.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.13:20:56.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.13:20:56.23#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:56.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:56.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:56.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:56.29#ibcon#enter wrdev, iclass 7, count 2 2006.257.13:20:56.29#ibcon#first serial, iclass 7, count 2 2006.257.13:20:56.29#ibcon#enter sib2, iclass 7, count 2 2006.257.13:20:56.29#ibcon#flushed, iclass 7, count 2 2006.257.13:20:56.29#ibcon#about to write, iclass 7, count 2 2006.257.13:20:56.29#ibcon#wrote, iclass 7, count 2 2006.257.13:20:56.29#ibcon#about to read 3, iclass 7, count 2 2006.257.13:20:56.31#ibcon#read 3, iclass 7, count 2 2006.257.13:20:56.31#ibcon#about to read 4, iclass 7, count 2 2006.257.13:20:56.31#ibcon#read 4, iclass 7, count 2 2006.257.13:20:56.31#ibcon#about to read 5, iclass 7, count 2 2006.257.13:20:56.31#ibcon#read 5, iclass 7, count 2 2006.257.13:20:56.31#ibcon#about to read 6, iclass 7, count 2 2006.257.13:20:56.31#ibcon#read 6, iclass 7, count 2 2006.257.13:20:56.31#ibcon#end of sib2, iclass 7, count 2 2006.257.13:20:56.31#ibcon#*mode == 0, iclass 7, count 2 2006.257.13:20:56.31#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.13:20:56.31#ibcon#[25=AT07-04\r\n] 2006.257.13:20:56.31#ibcon#*before write, iclass 7, count 2 2006.257.13:20:56.31#ibcon#enter sib2, iclass 7, count 2 2006.257.13:20:56.31#ibcon#flushed, iclass 7, count 2 2006.257.13:20:56.31#ibcon#about to write, iclass 7, count 2 2006.257.13:20:56.31#ibcon#wrote, iclass 7, count 2 2006.257.13:20:56.31#ibcon#about to read 3, iclass 7, count 2 2006.257.13:20:56.34#ibcon#read 3, iclass 7, count 2 2006.257.13:20:56.34#ibcon#about to read 4, iclass 7, count 2 2006.257.13:20:56.34#ibcon#read 4, iclass 7, count 2 2006.257.13:20:56.34#ibcon#about to read 5, iclass 7, count 2 2006.257.13:20:56.34#ibcon#read 5, iclass 7, count 2 2006.257.13:20:56.34#ibcon#about to read 6, iclass 7, count 2 2006.257.13:20:56.34#ibcon#read 6, iclass 7, count 2 2006.257.13:20:56.34#ibcon#end of sib2, iclass 7, count 2 2006.257.13:20:56.34#ibcon#*after write, iclass 7, count 2 2006.257.13:20:56.34#ibcon#*before return 0, iclass 7, count 2 2006.257.13:20:56.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:56.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:56.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.13:20:56.34#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:56.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:56.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:56.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:56.46#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:20:56.46#ibcon#first serial, iclass 7, count 0 2006.257.13:20:56.46#ibcon#enter sib2, iclass 7, count 0 2006.257.13:20:56.46#ibcon#flushed, iclass 7, count 0 2006.257.13:20:56.46#ibcon#about to write, iclass 7, count 0 2006.257.13:20:56.46#ibcon#wrote, iclass 7, count 0 2006.257.13:20:56.46#ibcon#about to read 3, iclass 7, count 0 2006.257.13:20:56.48#ibcon#read 3, iclass 7, count 0 2006.257.13:20:56.48#ibcon#about to read 4, iclass 7, count 0 2006.257.13:20:56.48#ibcon#read 4, iclass 7, count 0 2006.257.13:20:56.48#ibcon#about to read 5, iclass 7, count 0 2006.257.13:20:56.48#ibcon#read 5, iclass 7, count 0 2006.257.13:20:56.48#ibcon#about to read 6, iclass 7, count 0 2006.257.13:20:56.48#ibcon#read 6, iclass 7, count 0 2006.257.13:20:56.48#ibcon#end of sib2, iclass 7, count 0 2006.257.13:20:56.48#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:20:56.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:20:56.48#ibcon#[25=USB\r\n] 2006.257.13:20:56.48#ibcon#*before write, iclass 7, count 0 2006.257.13:20:56.48#ibcon#enter sib2, iclass 7, count 0 2006.257.13:20:56.48#ibcon#flushed, iclass 7, count 0 2006.257.13:20:56.48#ibcon#about to write, iclass 7, count 0 2006.257.13:20:56.48#ibcon#wrote, iclass 7, count 0 2006.257.13:20:56.48#ibcon#about to read 3, iclass 7, count 0 2006.257.13:20:56.51#ibcon#read 3, iclass 7, count 0 2006.257.13:20:56.51#ibcon#about to read 4, iclass 7, count 0 2006.257.13:20:56.51#ibcon#read 4, iclass 7, count 0 2006.257.13:20:56.51#ibcon#about to read 5, iclass 7, count 0 2006.257.13:20:56.51#ibcon#read 5, iclass 7, count 0 2006.257.13:20:56.51#ibcon#about to read 6, iclass 7, count 0 2006.257.13:20:56.51#ibcon#read 6, iclass 7, count 0 2006.257.13:20:56.51#ibcon#end of sib2, iclass 7, count 0 2006.257.13:20:56.51#ibcon#*after write, iclass 7, count 0 2006.257.13:20:56.51#ibcon#*before return 0, iclass 7, count 0 2006.257.13:20:56.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:56.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:56.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:20:56.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:20:56.51$vck44/valo=8,884.99 2006.257.13:20:56.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.13:20:56.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.13:20:56.51#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:56.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:56.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:56.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:56.51#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:20:56.51#ibcon#first serial, iclass 11, count 0 2006.257.13:20:56.51#ibcon#enter sib2, iclass 11, count 0 2006.257.13:20:56.51#ibcon#flushed, iclass 11, count 0 2006.257.13:20:56.51#ibcon#about to write, iclass 11, count 0 2006.257.13:20:56.51#ibcon#wrote, iclass 11, count 0 2006.257.13:20:56.51#ibcon#about to read 3, iclass 11, count 0 2006.257.13:20:56.53#ibcon#read 3, iclass 11, count 0 2006.257.13:20:56.53#ibcon#about to read 4, iclass 11, count 0 2006.257.13:20:56.53#ibcon#read 4, iclass 11, count 0 2006.257.13:20:56.53#ibcon#about to read 5, iclass 11, count 0 2006.257.13:20:56.53#ibcon#read 5, iclass 11, count 0 2006.257.13:20:56.53#ibcon#about to read 6, iclass 11, count 0 2006.257.13:20:56.53#ibcon#read 6, iclass 11, count 0 2006.257.13:20:56.53#ibcon#end of sib2, iclass 11, count 0 2006.257.13:20:56.53#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:20:56.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:20:56.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:20:56.53#ibcon#*before write, iclass 11, count 0 2006.257.13:20:56.53#ibcon#enter sib2, iclass 11, count 0 2006.257.13:20:56.53#ibcon#flushed, iclass 11, count 0 2006.257.13:20:56.53#ibcon#about to write, iclass 11, count 0 2006.257.13:20:56.53#ibcon#wrote, iclass 11, count 0 2006.257.13:20:56.53#ibcon#about to read 3, iclass 11, count 0 2006.257.13:20:56.57#ibcon#read 3, iclass 11, count 0 2006.257.13:20:56.57#ibcon#about to read 4, iclass 11, count 0 2006.257.13:20:56.57#ibcon#read 4, iclass 11, count 0 2006.257.13:20:56.57#ibcon#about to read 5, iclass 11, count 0 2006.257.13:20:56.57#ibcon#read 5, iclass 11, count 0 2006.257.13:20:56.57#ibcon#about to read 6, iclass 11, count 0 2006.257.13:20:56.57#ibcon#read 6, iclass 11, count 0 2006.257.13:20:56.57#ibcon#end of sib2, iclass 11, count 0 2006.257.13:20:56.57#ibcon#*after write, iclass 11, count 0 2006.257.13:20:56.57#ibcon#*before return 0, iclass 11, count 0 2006.257.13:20:56.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:56.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:56.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:20:56.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:20:56.57$vck44/va=8,4 2006.257.13:20:56.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.13:20:56.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.13:20:56.57#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:56.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:20:56.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:20:56.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:20:56.63#ibcon#enter wrdev, iclass 13, count 2 2006.257.13:20:56.63#ibcon#first serial, iclass 13, count 2 2006.257.13:20:56.63#ibcon#enter sib2, iclass 13, count 2 2006.257.13:20:56.63#ibcon#flushed, iclass 13, count 2 2006.257.13:20:56.63#ibcon#about to write, iclass 13, count 2 2006.257.13:20:56.63#ibcon#wrote, iclass 13, count 2 2006.257.13:20:56.63#ibcon#about to read 3, iclass 13, count 2 2006.257.13:20:56.65#ibcon#read 3, iclass 13, count 2 2006.257.13:20:56.65#ibcon#about to read 4, iclass 13, count 2 2006.257.13:20:56.65#ibcon#read 4, iclass 13, count 2 2006.257.13:20:56.65#ibcon#about to read 5, iclass 13, count 2 2006.257.13:20:56.65#ibcon#read 5, iclass 13, count 2 2006.257.13:20:56.65#ibcon#about to read 6, iclass 13, count 2 2006.257.13:20:56.65#ibcon#read 6, iclass 13, count 2 2006.257.13:20:56.65#ibcon#end of sib2, iclass 13, count 2 2006.257.13:20:56.65#ibcon#*mode == 0, iclass 13, count 2 2006.257.13:20:56.65#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.13:20:56.65#ibcon#[25=AT08-04\r\n] 2006.257.13:20:56.65#ibcon#*before write, iclass 13, count 2 2006.257.13:20:56.65#ibcon#enter sib2, iclass 13, count 2 2006.257.13:20:56.65#ibcon#flushed, iclass 13, count 2 2006.257.13:20:56.65#ibcon#about to write, iclass 13, count 2 2006.257.13:20:56.65#ibcon#wrote, iclass 13, count 2 2006.257.13:20:56.65#ibcon#about to read 3, iclass 13, count 2 2006.257.13:20:56.68#ibcon#read 3, iclass 13, count 2 2006.257.13:20:56.68#ibcon#about to read 4, iclass 13, count 2 2006.257.13:20:56.68#ibcon#read 4, iclass 13, count 2 2006.257.13:20:56.68#ibcon#about to read 5, iclass 13, count 2 2006.257.13:20:56.68#ibcon#read 5, iclass 13, count 2 2006.257.13:20:56.68#ibcon#about to read 6, iclass 13, count 2 2006.257.13:20:56.68#ibcon#read 6, iclass 13, count 2 2006.257.13:20:56.68#ibcon#end of sib2, iclass 13, count 2 2006.257.13:20:56.68#ibcon#*after write, iclass 13, count 2 2006.257.13:20:56.68#ibcon#*before return 0, iclass 13, count 2 2006.257.13:20:56.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:20:56.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:20:56.68#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.13:20:56.68#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:56.68#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:20:56.80#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:20:56.80#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:20:56.80#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:20:56.80#ibcon#first serial, iclass 13, count 0 2006.257.13:20:56.80#ibcon#enter sib2, iclass 13, count 0 2006.257.13:20:56.80#ibcon#flushed, iclass 13, count 0 2006.257.13:20:56.80#ibcon#about to write, iclass 13, count 0 2006.257.13:20:56.80#ibcon#wrote, iclass 13, count 0 2006.257.13:20:56.80#ibcon#about to read 3, iclass 13, count 0 2006.257.13:20:56.82#ibcon#read 3, iclass 13, count 0 2006.257.13:20:56.82#ibcon#about to read 4, iclass 13, count 0 2006.257.13:20:56.82#ibcon#read 4, iclass 13, count 0 2006.257.13:20:56.82#ibcon#about to read 5, iclass 13, count 0 2006.257.13:20:56.82#ibcon#read 5, iclass 13, count 0 2006.257.13:20:56.82#ibcon#about to read 6, iclass 13, count 0 2006.257.13:20:56.82#ibcon#read 6, iclass 13, count 0 2006.257.13:20:56.82#ibcon#end of sib2, iclass 13, count 0 2006.257.13:20:56.82#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:20:56.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:20:56.82#ibcon#[25=USB\r\n] 2006.257.13:20:56.82#ibcon#*before write, iclass 13, count 0 2006.257.13:20:56.82#ibcon#enter sib2, iclass 13, count 0 2006.257.13:20:56.82#ibcon#flushed, iclass 13, count 0 2006.257.13:20:56.82#ibcon#about to write, iclass 13, count 0 2006.257.13:20:56.82#ibcon#wrote, iclass 13, count 0 2006.257.13:20:56.82#ibcon#about to read 3, iclass 13, count 0 2006.257.13:20:56.85#ibcon#read 3, iclass 13, count 0 2006.257.13:20:56.85#ibcon#about to read 4, iclass 13, count 0 2006.257.13:20:56.85#ibcon#read 4, iclass 13, count 0 2006.257.13:20:56.85#ibcon#about to read 5, iclass 13, count 0 2006.257.13:20:56.85#ibcon#read 5, iclass 13, count 0 2006.257.13:20:56.85#ibcon#about to read 6, iclass 13, count 0 2006.257.13:20:56.85#ibcon#read 6, iclass 13, count 0 2006.257.13:20:56.85#ibcon#end of sib2, iclass 13, count 0 2006.257.13:20:56.85#ibcon#*after write, iclass 13, count 0 2006.257.13:20:56.85#ibcon#*before return 0, iclass 13, count 0 2006.257.13:20:56.85#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:20:56.85#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:20:56.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:20:56.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:20:56.85$vck44/vblo=1,629.99 2006.257.13:20:56.85#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.13:20:56.85#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.13:20:56.85#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:56.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:20:56.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:20:56.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:20:56.85#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:20:56.85#ibcon#first serial, iclass 15, count 0 2006.257.13:20:56.85#ibcon#enter sib2, iclass 15, count 0 2006.257.13:20:56.85#ibcon#flushed, iclass 15, count 0 2006.257.13:20:56.85#ibcon#about to write, iclass 15, count 0 2006.257.13:20:56.85#ibcon#wrote, iclass 15, count 0 2006.257.13:20:56.85#ibcon#about to read 3, iclass 15, count 0 2006.257.13:20:56.87#ibcon#read 3, iclass 15, count 0 2006.257.13:20:56.87#ibcon#about to read 4, iclass 15, count 0 2006.257.13:20:56.87#ibcon#read 4, iclass 15, count 0 2006.257.13:20:56.87#ibcon#about to read 5, iclass 15, count 0 2006.257.13:20:56.87#ibcon#read 5, iclass 15, count 0 2006.257.13:20:56.87#ibcon#about to read 6, iclass 15, count 0 2006.257.13:20:56.87#ibcon#read 6, iclass 15, count 0 2006.257.13:20:56.87#ibcon#end of sib2, iclass 15, count 0 2006.257.13:20:56.87#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:20:56.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:20:56.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:20:56.87#ibcon#*before write, iclass 15, count 0 2006.257.13:20:56.87#ibcon#enter sib2, iclass 15, count 0 2006.257.13:20:56.87#ibcon#flushed, iclass 15, count 0 2006.257.13:20:56.87#ibcon#about to write, iclass 15, count 0 2006.257.13:20:56.87#ibcon#wrote, iclass 15, count 0 2006.257.13:20:56.87#ibcon#about to read 3, iclass 15, count 0 2006.257.13:20:56.91#ibcon#read 3, iclass 15, count 0 2006.257.13:20:56.91#ibcon#about to read 4, iclass 15, count 0 2006.257.13:20:56.91#ibcon#read 4, iclass 15, count 0 2006.257.13:20:56.91#ibcon#about to read 5, iclass 15, count 0 2006.257.13:20:56.91#ibcon#read 5, iclass 15, count 0 2006.257.13:20:56.91#ibcon#about to read 6, iclass 15, count 0 2006.257.13:20:56.91#ibcon#read 6, iclass 15, count 0 2006.257.13:20:56.91#ibcon#end of sib2, iclass 15, count 0 2006.257.13:20:56.91#ibcon#*after write, iclass 15, count 0 2006.257.13:20:56.91#ibcon#*before return 0, iclass 15, count 0 2006.257.13:20:56.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:20:56.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:20:56.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:20:56.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:20:56.91$vck44/vb=1,4 2006.257.13:20:56.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.13:20:56.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.13:20:56.91#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:56.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:20:56.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:20:56.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:20:56.91#ibcon#enter wrdev, iclass 17, count 2 2006.257.13:20:56.91#ibcon#first serial, iclass 17, count 2 2006.257.13:20:56.91#ibcon#enter sib2, iclass 17, count 2 2006.257.13:20:56.91#ibcon#flushed, iclass 17, count 2 2006.257.13:20:56.91#ibcon#about to write, iclass 17, count 2 2006.257.13:20:56.91#ibcon#wrote, iclass 17, count 2 2006.257.13:20:56.91#ibcon#about to read 3, iclass 17, count 2 2006.257.13:20:56.93#ibcon#read 3, iclass 17, count 2 2006.257.13:20:56.93#ibcon#about to read 4, iclass 17, count 2 2006.257.13:20:56.93#ibcon#read 4, iclass 17, count 2 2006.257.13:20:56.93#ibcon#about to read 5, iclass 17, count 2 2006.257.13:20:56.93#ibcon#read 5, iclass 17, count 2 2006.257.13:20:56.93#ibcon#about to read 6, iclass 17, count 2 2006.257.13:20:56.93#ibcon#read 6, iclass 17, count 2 2006.257.13:20:56.93#ibcon#end of sib2, iclass 17, count 2 2006.257.13:20:56.93#ibcon#*mode == 0, iclass 17, count 2 2006.257.13:20:56.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.13:20:56.93#ibcon#[27=AT01-04\r\n] 2006.257.13:20:56.93#ibcon#*before write, iclass 17, count 2 2006.257.13:20:56.93#ibcon#enter sib2, iclass 17, count 2 2006.257.13:20:56.93#ibcon#flushed, iclass 17, count 2 2006.257.13:20:56.93#ibcon#about to write, iclass 17, count 2 2006.257.13:20:56.93#ibcon#wrote, iclass 17, count 2 2006.257.13:20:56.93#ibcon#about to read 3, iclass 17, count 2 2006.257.13:20:56.96#ibcon#read 3, iclass 17, count 2 2006.257.13:20:56.96#ibcon#about to read 4, iclass 17, count 2 2006.257.13:20:56.96#ibcon#read 4, iclass 17, count 2 2006.257.13:20:56.96#ibcon#about to read 5, iclass 17, count 2 2006.257.13:20:56.96#ibcon#read 5, iclass 17, count 2 2006.257.13:20:56.96#ibcon#about to read 6, iclass 17, count 2 2006.257.13:20:56.96#ibcon#read 6, iclass 17, count 2 2006.257.13:20:56.96#ibcon#end of sib2, iclass 17, count 2 2006.257.13:20:56.96#ibcon#*after write, iclass 17, count 2 2006.257.13:20:56.96#ibcon#*before return 0, iclass 17, count 2 2006.257.13:20:56.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:20:56.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:20:56.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.13:20:56.96#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:56.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:20:57.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:20:57.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:20:57.08#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:20:57.08#ibcon#first serial, iclass 17, count 0 2006.257.13:20:57.08#ibcon#enter sib2, iclass 17, count 0 2006.257.13:20:57.08#ibcon#flushed, iclass 17, count 0 2006.257.13:20:57.08#ibcon#about to write, iclass 17, count 0 2006.257.13:20:57.08#ibcon#wrote, iclass 17, count 0 2006.257.13:20:57.08#ibcon#about to read 3, iclass 17, count 0 2006.257.13:20:57.10#ibcon#read 3, iclass 17, count 0 2006.257.13:20:57.10#ibcon#about to read 4, iclass 17, count 0 2006.257.13:20:57.10#ibcon#read 4, iclass 17, count 0 2006.257.13:20:57.10#ibcon#about to read 5, iclass 17, count 0 2006.257.13:20:57.10#ibcon#read 5, iclass 17, count 0 2006.257.13:20:57.10#ibcon#about to read 6, iclass 17, count 0 2006.257.13:20:57.10#ibcon#read 6, iclass 17, count 0 2006.257.13:20:57.10#ibcon#end of sib2, iclass 17, count 0 2006.257.13:20:57.10#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:20:57.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:20:57.10#ibcon#[27=USB\r\n] 2006.257.13:20:57.10#ibcon#*before write, iclass 17, count 0 2006.257.13:20:57.10#ibcon#enter sib2, iclass 17, count 0 2006.257.13:20:57.10#ibcon#flushed, iclass 17, count 0 2006.257.13:20:57.10#ibcon#about to write, iclass 17, count 0 2006.257.13:20:57.10#ibcon#wrote, iclass 17, count 0 2006.257.13:20:57.10#ibcon#about to read 3, iclass 17, count 0 2006.257.13:20:57.13#ibcon#read 3, iclass 17, count 0 2006.257.13:20:57.13#ibcon#about to read 4, iclass 17, count 0 2006.257.13:20:57.13#ibcon#read 4, iclass 17, count 0 2006.257.13:20:57.13#ibcon#about to read 5, iclass 17, count 0 2006.257.13:20:57.13#ibcon#read 5, iclass 17, count 0 2006.257.13:20:57.13#ibcon#about to read 6, iclass 17, count 0 2006.257.13:20:57.13#ibcon#read 6, iclass 17, count 0 2006.257.13:20:57.13#ibcon#end of sib2, iclass 17, count 0 2006.257.13:20:57.13#ibcon#*after write, iclass 17, count 0 2006.257.13:20:57.13#ibcon#*before return 0, iclass 17, count 0 2006.257.13:20:57.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:20:57.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:20:57.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:20:57.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:20:57.13$vck44/vblo=2,634.99 2006.257.13:20:57.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.13:20:57.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.13:20:57.13#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:57.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:57.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:57.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:57.13#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:20:57.13#ibcon#first serial, iclass 19, count 0 2006.257.13:20:57.13#ibcon#enter sib2, iclass 19, count 0 2006.257.13:20:57.13#ibcon#flushed, iclass 19, count 0 2006.257.13:20:57.13#ibcon#about to write, iclass 19, count 0 2006.257.13:20:57.13#ibcon#wrote, iclass 19, count 0 2006.257.13:20:57.13#ibcon#about to read 3, iclass 19, count 0 2006.257.13:20:57.15#ibcon#read 3, iclass 19, count 0 2006.257.13:20:57.15#ibcon#about to read 4, iclass 19, count 0 2006.257.13:20:57.15#ibcon#read 4, iclass 19, count 0 2006.257.13:20:57.15#ibcon#about to read 5, iclass 19, count 0 2006.257.13:20:57.15#ibcon#read 5, iclass 19, count 0 2006.257.13:20:57.15#ibcon#about to read 6, iclass 19, count 0 2006.257.13:20:57.15#ibcon#read 6, iclass 19, count 0 2006.257.13:20:57.15#ibcon#end of sib2, iclass 19, count 0 2006.257.13:20:57.15#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:20:57.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:20:57.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:20:57.15#ibcon#*before write, iclass 19, count 0 2006.257.13:20:57.15#ibcon#enter sib2, iclass 19, count 0 2006.257.13:20:57.15#ibcon#flushed, iclass 19, count 0 2006.257.13:20:57.15#ibcon#about to write, iclass 19, count 0 2006.257.13:20:57.15#ibcon#wrote, iclass 19, count 0 2006.257.13:20:57.15#ibcon#about to read 3, iclass 19, count 0 2006.257.13:20:57.19#ibcon#read 3, iclass 19, count 0 2006.257.13:20:57.19#ibcon#about to read 4, iclass 19, count 0 2006.257.13:20:57.19#ibcon#read 4, iclass 19, count 0 2006.257.13:20:57.19#ibcon#about to read 5, iclass 19, count 0 2006.257.13:20:57.19#ibcon#read 5, iclass 19, count 0 2006.257.13:20:57.19#ibcon#about to read 6, iclass 19, count 0 2006.257.13:20:57.19#ibcon#read 6, iclass 19, count 0 2006.257.13:20:57.19#ibcon#end of sib2, iclass 19, count 0 2006.257.13:20:57.19#ibcon#*after write, iclass 19, count 0 2006.257.13:20:57.19#ibcon#*before return 0, iclass 19, count 0 2006.257.13:20:57.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:57.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:20:57.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:20:57.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:20:57.24$vck44/vb=2,5 2006.257.13:20:57.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.13:20:57.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.13:20:57.24#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:57.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:57.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:57.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:57.24#ibcon#enter wrdev, iclass 21, count 2 2006.257.13:20:57.24#ibcon#first serial, iclass 21, count 2 2006.257.13:20:57.24#ibcon#enter sib2, iclass 21, count 2 2006.257.13:20:57.24#ibcon#flushed, iclass 21, count 2 2006.257.13:20:57.24#ibcon#about to write, iclass 21, count 2 2006.257.13:20:57.24#ibcon#wrote, iclass 21, count 2 2006.257.13:20:57.24#ibcon#about to read 3, iclass 21, count 2 2006.257.13:20:57.26#ibcon#read 3, iclass 21, count 2 2006.257.13:20:57.26#ibcon#about to read 4, iclass 21, count 2 2006.257.13:20:57.26#ibcon#read 4, iclass 21, count 2 2006.257.13:20:57.26#ibcon#about to read 5, iclass 21, count 2 2006.257.13:20:57.26#ibcon#read 5, iclass 21, count 2 2006.257.13:20:57.26#ibcon#about to read 6, iclass 21, count 2 2006.257.13:20:57.26#ibcon#read 6, iclass 21, count 2 2006.257.13:20:57.26#ibcon#end of sib2, iclass 21, count 2 2006.257.13:20:57.26#ibcon#*mode == 0, iclass 21, count 2 2006.257.13:20:57.26#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.13:20:57.26#ibcon#[27=AT02-05\r\n] 2006.257.13:20:57.26#ibcon#*before write, iclass 21, count 2 2006.257.13:20:57.26#ibcon#enter sib2, iclass 21, count 2 2006.257.13:20:57.26#ibcon#flushed, iclass 21, count 2 2006.257.13:20:57.26#ibcon#about to write, iclass 21, count 2 2006.257.13:20:57.26#ibcon#wrote, iclass 21, count 2 2006.257.13:20:57.26#ibcon#about to read 3, iclass 21, count 2 2006.257.13:20:57.29#ibcon#read 3, iclass 21, count 2 2006.257.13:20:57.29#ibcon#about to read 4, iclass 21, count 2 2006.257.13:20:57.29#ibcon#read 4, iclass 21, count 2 2006.257.13:20:57.29#ibcon#about to read 5, iclass 21, count 2 2006.257.13:20:57.29#ibcon#read 5, iclass 21, count 2 2006.257.13:20:57.29#ibcon#about to read 6, iclass 21, count 2 2006.257.13:20:57.29#ibcon#read 6, iclass 21, count 2 2006.257.13:20:57.29#ibcon#end of sib2, iclass 21, count 2 2006.257.13:20:57.29#ibcon#*after write, iclass 21, count 2 2006.257.13:20:57.29#ibcon#*before return 0, iclass 21, count 2 2006.257.13:20:57.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:57.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:20:57.29#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.13:20:57.29#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:57.29#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:57.41#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:57.41#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:57.41#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:20:57.41#ibcon#first serial, iclass 21, count 0 2006.257.13:20:57.41#ibcon#enter sib2, iclass 21, count 0 2006.257.13:20:57.41#ibcon#flushed, iclass 21, count 0 2006.257.13:20:57.41#ibcon#about to write, iclass 21, count 0 2006.257.13:20:57.41#ibcon#wrote, iclass 21, count 0 2006.257.13:20:57.41#ibcon#about to read 3, iclass 21, count 0 2006.257.13:20:57.43#ibcon#read 3, iclass 21, count 0 2006.257.13:20:57.43#ibcon#about to read 4, iclass 21, count 0 2006.257.13:20:57.43#ibcon#read 4, iclass 21, count 0 2006.257.13:20:57.43#ibcon#about to read 5, iclass 21, count 0 2006.257.13:20:57.43#ibcon#read 5, iclass 21, count 0 2006.257.13:20:57.43#ibcon#about to read 6, iclass 21, count 0 2006.257.13:20:57.43#ibcon#read 6, iclass 21, count 0 2006.257.13:20:57.43#ibcon#end of sib2, iclass 21, count 0 2006.257.13:20:57.43#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:20:57.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:20:57.43#ibcon#[27=USB\r\n] 2006.257.13:20:57.43#ibcon#*before write, iclass 21, count 0 2006.257.13:20:57.43#ibcon#enter sib2, iclass 21, count 0 2006.257.13:20:57.43#ibcon#flushed, iclass 21, count 0 2006.257.13:20:57.43#ibcon#about to write, iclass 21, count 0 2006.257.13:20:57.43#ibcon#wrote, iclass 21, count 0 2006.257.13:20:57.43#ibcon#about to read 3, iclass 21, count 0 2006.257.13:20:57.46#ibcon#read 3, iclass 21, count 0 2006.257.13:20:57.46#ibcon#about to read 4, iclass 21, count 0 2006.257.13:20:57.46#ibcon#read 4, iclass 21, count 0 2006.257.13:20:57.46#ibcon#about to read 5, iclass 21, count 0 2006.257.13:20:57.46#ibcon#read 5, iclass 21, count 0 2006.257.13:20:57.46#ibcon#about to read 6, iclass 21, count 0 2006.257.13:20:57.46#ibcon#read 6, iclass 21, count 0 2006.257.13:20:57.46#ibcon#end of sib2, iclass 21, count 0 2006.257.13:20:57.46#ibcon#*after write, iclass 21, count 0 2006.257.13:20:57.46#ibcon#*before return 0, iclass 21, count 0 2006.257.13:20:57.46#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:57.46#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:20:57.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:20:57.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:20:57.46$vck44/vblo=3,649.99 2006.257.13:20:57.46#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.13:20:57.46#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.13:20:57.46#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:57.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:57.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:57.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:57.46#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:20:57.46#ibcon#first serial, iclass 23, count 0 2006.257.13:20:57.46#ibcon#enter sib2, iclass 23, count 0 2006.257.13:20:57.46#ibcon#flushed, iclass 23, count 0 2006.257.13:20:57.46#ibcon#about to write, iclass 23, count 0 2006.257.13:20:57.46#ibcon#wrote, iclass 23, count 0 2006.257.13:20:57.46#ibcon#about to read 3, iclass 23, count 0 2006.257.13:20:57.48#ibcon#read 3, iclass 23, count 0 2006.257.13:20:57.48#ibcon#about to read 4, iclass 23, count 0 2006.257.13:20:57.48#ibcon#read 4, iclass 23, count 0 2006.257.13:20:57.48#ibcon#about to read 5, iclass 23, count 0 2006.257.13:20:57.48#ibcon#read 5, iclass 23, count 0 2006.257.13:20:57.48#ibcon#about to read 6, iclass 23, count 0 2006.257.13:20:57.48#ibcon#read 6, iclass 23, count 0 2006.257.13:20:57.48#ibcon#end of sib2, iclass 23, count 0 2006.257.13:20:57.48#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:20:57.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:20:57.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:20:57.48#ibcon#*before write, iclass 23, count 0 2006.257.13:20:57.48#ibcon#enter sib2, iclass 23, count 0 2006.257.13:20:57.48#ibcon#flushed, iclass 23, count 0 2006.257.13:20:57.48#ibcon#about to write, iclass 23, count 0 2006.257.13:20:57.48#ibcon#wrote, iclass 23, count 0 2006.257.13:20:57.48#ibcon#about to read 3, iclass 23, count 0 2006.257.13:20:57.52#ibcon#read 3, iclass 23, count 0 2006.257.13:20:57.52#ibcon#about to read 4, iclass 23, count 0 2006.257.13:20:57.52#ibcon#read 4, iclass 23, count 0 2006.257.13:20:57.52#ibcon#about to read 5, iclass 23, count 0 2006.257.13:20:57.52#ibcon#read 5, iclass 23, count 0 2006.257.13:20:57.52#ibcon#about to read 6, iclass 23, count 0 2006.257.13:20:57.52#ibcon#read 6, iclass 23, count 0 2006.257.13:20:57.52#ibcon#end of sib2, iclass 23, count 0 2006.257.13:20:57.52#ibcon#*after write, iclass 23, count 0 2006.257.13:20:57.52#ibcon#*before return 0, iclass 23, count 0 2006.257.13:20:57.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:57.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:20:57.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:20:57.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:20:57.52$vck44/vb=3,4 2006.257.13:20:57.52#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.13:20:57.52#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.13:20:57.52#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:57.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:57.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:57.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:57.58#ibcon#enter wrdev, iclass 25, count 2 2006.257.13:20:57.58#ibcon#first serial, iclass 25, count 2 2006.257.13:20:57.58#ibcon#enter sib2, iclass 25, count 2 2006.257.13:20:57.58#ibcon#flushed, iclass 25, count 2 2006.257.13:20:57.58#ibcon#about to write, iclass 25, count 2 2006.257.13:20:57.58#ibcon#wrote, iclass 25, count 2 2006.257.13:20:57.58#ibcon#about to read 3, iclass 25, count 2 2006.257.13:20:57.60#ibcon#read 3, iclass 25, count 2 2006.257.13:20:57.60#ibcon#about to read 4, iclass 25, count 2 2006.257.13:20:57.60#ibcon#read 4, iclass 25, count 2 2006.257.13:20:57.60#ibcon#about to read 5, iclass 25, count 2 2006.257.13:20:57.60#ibcon#read 5, iclass 25, count 2 2006.257.13:20:57.60#ibcon#about to read 6, iclass 25, count 2 2006.257.13:20:57.60#ibcon#read 6, iclass 25, count 2 2006.257.13:20:57.60#ibcon#end of sib2, iclass 25, count 2 2006.257.13:20:57.60#ibcon#*mode == 0, iclass 25, count 2 2006.257.13:20:57.60#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.13:20:57.60#ibcon#[27=AT03-04\r\n] 2006.257.13:20:57.60#ibcon#*before write, iclass 25, count 2 2006.257.13:20:57.60#ibcon#enter sib2, iclass 25, count 2 2006.257.13:20:57.60#ibcon#flushed, iclass 25, count 2 2006.257.13:20:57.60#ibcon#about to write, iclass 25, count 2 2006.257.13:20:57.60#ibcon#wrote, iclass 25, count 2 2006.257.13:20:57.60#ibcon#about to read 3, iclass 25, count 2 2006.257.13:20:57.63#ibcon#read 3, iclass 25, count 2 2006.257.13:20:57.63#ibcon#about to read 4, iclass 25, count 2 2006.257.13:20:57.63#ibcon#read 4, iclass 25, count 2 2006.257.13:20:57.63#ibcon#about to read 5, iclass 25, count 2 2006.257.13:20:57.63#ibcon#read 5, iclass 25, count 2 2006.257.13:20:57.63#ibcon#about to read 6, iclass 25, count 2 2006.257.13:20:57.63#ibcon#read 6, iclass 25, count 2 2006.257.13:20:57.63#ibcon#end of sib2, iclass 25, count 2 2006.257.13:20:57.63#ibcon#*after write, iclass 25, count 2 2006.257.13:20:57.63#ibcon#*before return 0, iclass 25, count 2 2006.257.13:20:57.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:57.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:20:57.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.13:20:57.63#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:57.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:57.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:57.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:57.75#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:20:57.75#ibcon#first serial, iclass 25, count 0 2006.257.13:20:57.75#ibcon#enter sib2, iclass 25, count 0 2006.257.13:20:57.75#ibcon#flushed, iclass 25, count 0 2006.257.13:20:57.75#ibcon#about to write, iclass 25, count 0 2006.257.13:20:57.75#ibcon#wrote, iclass 25, count 0 2006.257.13:20:57.75#ibcon#about to read 3, iclass 25, count 0 2006.257.13:20:57.77#ibcon#read 3, iclass 25, count 0 2006.257.13:20:57.77#ibcon#about to read 4, iclass 25, count 0 2006.257.13:20:57.77#ibcon#read 4, iclass 25, count 0 2006.257.13:20:57.77#ibcon#about to read 5, iclass 25, count 0 2006.257.13:20:57.77#ibcon#read 5, iclass 25, count 0 2006.257.13:20:57.77#ibcon#about to read 6, iclass 25, count 0 2006.257.13:20:57.77#ibcon#read 6, iclass 25, count 0 2006.257.13:20:57.77#ibcon#end of sib2, iclass 25, count 0 2006.257.13:20:57.77#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:20:57.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:20:57.77#ibcon#[27=USB\r\n] 2006.257.13:20:57.77#ibcon#*before write, iclass 25, count 0 2006.257.13:20:57.77#ibcon#enter sib2, iclass 25, count 0 2006.257.13:20:57.77#ibcon#flushed, iclass 25, count 0 2006.257.13:20:57.77#ibcon#about to write, iclass 25, count 0 2006.257.13:20:57.77#ibcon#wrote, iclass 25, count 0 2006.257.13:20:57.77#ibcon#about to read 3, iclass 25, count 0 2006.257.13:20:57.80#ibcon#read 3, iclass 25, count 0 2006.257.13:20:57.80#ibcon#about to read 4, iclass 25, count 0 2006.257.13:20:57.80#ibcon#read 4, iclass 25, count 0 2006.257.13:20:57.80#ibcon#about to read 5, iclass 25, count 0 2006.257.13:20:57.80#ibcon#read 5, iclass 25, count 0 2006.257.13:20:57.80#ibcon#about to read 6, iclass 25, count 0 2006.257.13:20:57.80#ibcon#read 6, iclass 25, count 0 2006.257.13:20:57.80#ibcon#end of sib2, iclass 25, count 0 2006.257.13:20:57.80#ibcon#*after write, iclass 25, count 0 2006.257.13:20:57.80#ibcon#*before return 0, iclass 25, count 0 2006.257.13:20:57.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:57.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:20:57.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:20:57.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:20:57.80$vck44/vblo=4,679.99 2006.257.13:20:57.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.13:20:57.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.13:20:57.80#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:57.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:57.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:57.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:57.80#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:20:57.80#ibcon#first serial, iclass 27, count 0 2006.257.13:20:57.80#ibcon#enter sib2, iclass 27, count 0 2006.257.13:20:57.80#ibcon#flushed, iclass 27, count 0 2006.257.13:20:57.80#ibcon#about to write, iclass 27, count 0 2006.257.13:20:57.80#ibcon#wrote, iclass 27, count 0 2006.257.13:20:57.80#ibcon#about to read 3, iclass 27, count 0 2006.257.13:20:57.82#ibcon#read 3, iclass 27, count 0 2006.257.13:20:57.82#ibcon#about to read 4, iclass 27, count 0 2006.257.13:20:57.82#ibcon#read 4, iclass 27, count 0 2006.257.13:20:57.82#ibcon#about to read 5, iclass 27, count 0 2006.257.13:20:57.82#ibcon#read 5, iclass 27, count 0 2006.257.13:20:57.82#ibcon#about to read 6, iclass 27, count 0 2006.257.13:20:57.82#ibcon#read 6, iclass 27, count 0 2006.257.13:20:57.82#ibcon#end of sib2, iclass 27, count 0 2006.257.13:20:57.82#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:20:57.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:20:57.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:20:57.82#ibcon#*before write, iclass 27, count 0 2006.257.13:20:57.82#ibcon#enter sib2, iclass 27, count 0 2006.257.13:20:57.82#ibcon#flushed, iclass 27, count 0 2006.257.13:20:57.82#ibcon#about to write, iclass 27, count 0 2006.257.13:20:57.82#ibcon#wrote, iclass 27, count 0 2006.257.13:20:57.82#ibcon#about to read 3, iclass 27, count 0 2006.257.13:20:57.86#ibcon#read 3, iclass 27, count 0 2006.257.13:20:57.86#ibcon#about to read 4, iclass 27, count 0 2006.257.13:20:57.86#ibcon#read 4, iclass 27, count 0 2006.257.13:20:57.86#ibcon#about to read 5, iclass 27, count 0 2006.257.13:20:57.86#ibcon#read 5, iclass 27, count 0 2006.257.13:20:57.86#ibcon#about to read 6, iclass 27, count 0 2006.257.13:20:57.86#ibcon#read 6, iclass 27, count 0 2006.257.13:20:57.86#ibcon#end of sib2, iclass 27, count 0 2006.257.13:20:57.86#ibcon#*after write, iclass 27, count 0 2006.257.13:20:57.86#ibcon#*before return 0, iclass 27, count 0 2006.257.13:20:57.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:57.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:20:57.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:20:57.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:20:57.86$vck44/vb=4,5 2006.257.13:20:57.86#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.13:20:57.86#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.13:20:57.86#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:57.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:57.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:57.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:57.92#ibcon#enter wrdev, iclass 29, count 2 2006.257.13:20:57.92#ibcon#first serial, iclass 29, count 2 2006.257.13:20:57.92#ibcon#enter sib2, iclass 29, count 2 2006.257.13:20:57.92#ibcon#flushed, iclass 29, count 2 2006.257.13:20:57.92#ibcon#about to write, iclass 29, count 2 2006.257.13:20:57.92#ibcon#wrote, iclass 29, count 2 2006.257.13:20:57.92#ibcon#about to read 3, iclass 29, count 2 2006.257.13:20:57.94#ibcon#read 3, iclass 29, count 2 2006.257.13:20:57.94#ibcon#about to read 4, iclass 29, count 2 2006.257.13:20:57.94#ibcon#read 4, iclass 29, count 2 2006.257.13:20:57.94#ibcon#about to read 5, iclass 29, count 2 2006.257.13:20:57.94#ibcon#read 5, iclass 29, count 2 2006.257.13:20:57.94#ibcon#about to read 6, iclass 29, count 2 2006.257.13:20:57.94#ibcon#read 6, iclass 29, count 2 2006.257.13:20:57.94#ibcon#end of sib2, iclass 29, count 2 2006.257.13:20:57.94#ibcon#*mode == 0, iclass 29, count 2 2006.257.13:20:57.94#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.13:20:57.94#ibcon#[27=AT04-05\r\n] 2006.257.13:20:57.94#ibcon#*before write, iclass 29, count 2 2006.257.13:20:57.94#ibcon#enter sib2, iclass 29, count 2 2006.257.13:20:57.94#ibcon#flushed, iclass 29, count 2 2006.257.13:20:57.94#ibcon#about to write, iclass 29, count 2 2006.257.13:20:57.94#ibcon#wrote, iclass 29, count 2 2006.257.13:20:57.94#ibcon#about to read 3, iclass 29, count 2 2006.257.13:20:57.97#ibcon#read 3, iclass 29, count 2 2006.257.13:20:57.97#ibcon#about to read 4, iclass 29, count 2 2006.257.13:20:57.97#ibcon#read 4, iclass 29, count 2 2006.257.13:20:57.97#ibcon#about to read 5, iclass 29, count 2 2006.257.13:20:57.97#ibcon#read 5, iclass 29, count 2 2006.257.13:20:57.97#ibcon#about to read 6, iclass 29, count 2 2006.257.13:20:57.97#ibcon#read 6, iclass 29, count 2 2006.257.13:20:57.97#ibcon#end of sib2, iclass 29, count 2 2006.257.13:20:57.97#ibcon#*after write, iclass 29, count 2 2006.257.13:20:57.97#ibcon#*before return 0, iclass 29, count 2 2006.257.13:20:57.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:57.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:20:57.97#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.13:20:57.97#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:57.97#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:58.09#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:58.09#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:58.09#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:20:58.09#ibcon#first serial, iclass 29, count 0 2006.257.13:20:58.09#ibcon#enter sib2, iclass 29, count 0 2006.257.13:20:58.09#ibcon#flushed, iclass 29, count 0 2006.257.13:20:58.09#ibcon#about to write, iclass 29, count 0 2006.257.13:20:58.09#ibcon#wrote, iclass 29, count 0 2006.257.13:20:58.09#ibcon#about to read 3, iclass 29, count 0 2006.257.13:20:58.11#ibcon#read 3, iclass 29, count 0 2006.257.13:20:58.11#ibcon#about to read 4, iclass 29, count 0 2006.257.13:20:58.11#ibcon#read 4, iclass 29, count 0 2006.257.13:20:58.11#ibcon#about to read 5, iclass 29, count 0 2006.257.13:20:58.11#ibcon#read 5, iclass 29, count 0 2006.257.13:20:58.11#ibcon#about to read 6, iclass 29, count 0 2006.257.13:20:58.11#ibcon#read 6, iclass 29, count 0 2006.257.13:20:58.11#ibcon#end of sib2, iclass 29, count 0 2006.257.13:20:58.11#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:20:58.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:20:58.11#ibcon#[27=USB\r\n] 2006.257.13:20:58.11#ibcon#*before write, iclass 29, count 0 2006.257.13:20:58.11#ibcon#enter sib2, iclass 29, count 0 2006.257.13:20:58.11#ibcon#flushed, iclass 29, count 0 2006.257.13:20:58.11#ibcon#about to write, iclass 29, count 0 2006.257.13:20:58.11#ibcon#wrote, iclass 29, count 0 2006.257.13:20:58.11#ibcon#about to read 3, iclass 29, count 0 2006.257.13:20:58.14#ibcon#read 3, iclass 29, count 0 2006.257.13:20:58.14#ibcon#about to read 4, iclass 29, count 0 2006.257.13:20:58.14#ibcon#read 4, iclass 29, count 0 2006.257.13:20:58.14#ibcon#about to read 5, iclass 29, count 0 2006.257.13:20:58.14#ibcon#read 5, iclass 29, count 0 2006.257.13:20:58.14#ibcon#about to read 6, iclass 29, count 0 2006.257.13:20:58.14#ibcon#read 6, iclass 29, count 0 2006.257.13:20:58.14#ibcon#end of sib2, iclass 29, count 0 2006.257.13:20:58.14#ibcon#*after write, iclass 29, count 0 2006.257.13:20:58.14#ibcon#*before return 0, iclass 29, count 0 2006.257.13:20:58.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:58.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:20:58.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:20:58.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:20:58.14$vck44/vblo=5,709.99 2006.257.13:20:58.14#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.13:20:58.14#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.13:20:58.14#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:58.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:58.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:58.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:58.14#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:20:58.14#ibcon#first serial, iclass 31, count 0 2006.257.13:20:58.14#ibcon#enter sib2, iclass 31, count 0 2006.257.13:20:58.14#ibcon#flushed, iclass 31, count 0 2006.257.13:20:58.14#ibcon#about to write, iclass 31, count 0 2006.257.13:20:58.14#ibcon#wrote, iclass 31, count 0 2006.257.13:20:58.14#ibcon#about to read 3, iclass 31, count 0 2006.257.13:20:58.16#ibcon#read 3, iclass 31, count 0 2006.257.13:20:58.16#ibcon#about to read 4, iclass 31, count 0 2006.257.13:20:58.16#ibcon#read 4, iclass 31, count 0 2006.257.13:20:58.16#ibcon#about to read 5, iclass 31, count 0 2006.257.13:20:58.16#ibcon#read 5, iclass 31, count 0 2006.257.13:20:58.16#ibcon#about to read 6, iclass 31, count 0 2006.257.13:20:58.16#ibcon#read 6, iclass 31, count 0 2006.257.13:20:58.16#ibcon#end of sib2, iclass 31, count 0 2006.257.13:20:58.16#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:20:58.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:20:58.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:20:58.16#ibcon#*before write, iclass 31, count 0 2006.257.13:20:58.16#ibcon#enter sib2, iclass 31, count 0 2006.257.13:20:58.16#ibcon#flushed, iclass 31, count 0 2006.257.13:20:58.16#ibcon#about to write, iclass 31, count 0 2006.257.13:20:58.16#ibcon#wrote, iclass 31, count 0 2006.257.13:20:58.16#ibcon#about to read 3, iclass 31, count 0 2006.257.13:20:58.20#ibcon#read 3, iclass 31, count 0 2006.257.13:20:58.20#ibcon#about to read 4, iclass 31, count 0 2006.257.13:20:58.20#ibcon#read 4, iclass 31, count 0 2006.257.13:20:58.20#ibcon#about to read 5, iclass 31, count 0 2006.257.13:20:58.20#ibcon#read 5, iclass 31, count 0 2006.257.13:20:58.20#ibcon#about to read 6, iclass 31, count 0 2006.257.13:20:58.20#ibcon#read 6, iclass 31, count 0 2006.257.13:20:58.20#ibcon#end of sib2, iclass 31, count 0 2006.257.13:20:58.20#ibcon#*after write, iclass 31, count 0 2006.257.13:20:58.20#ibcon#*before return 0, iclass 31, count 0 2006.257.13:20:58.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:58.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:20:58.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:20:58.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:20:58.20$vck44/vb=5,4 2006.257.13:20:58.20#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.13:20:58.20#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.13:20:58.20#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:58.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:58.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:58.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:58.26#ibcon#enter wrdev, iclass 33, count 2 2006.257.13:20:58.26#ibcon#first serial, iclass 33, count 2 2006.257.13:20:58.26#ibcon#enter sib2, iclass 33, count 2 2006.257.13:20:58.26#ibcon#flushed, iclass 33, count 2 2006.257.13:20:58.26#ibcon#about to write, iclass 33, count 2 2006.257.13:20:58.26#ibcon#wrote, iclass 33, count 2 2006.257.13:20:58.26#ibcon#about to read 3, iclass 33, count 2 2006.257.13:20:58.28#ibcon#read 3, iclass 33, count 2 2006.257.13:20:58.28#ibcon#about to read 4, iclass 33, count 2 2006.257.13:20:58.28#ibcon#read 4, iclass 33, count 2 2006.257.13:20:58.28#ibcon#about to read 5, iclass 33, count 2 2006.257.13:20:58.28#ibcon#read 5, iclass 33, count 2 2006.257.13:20:58.28#ibcon#about to read 6, iclass 33, count 2 2006.257.13:20:58.28#ibcon#read 6, iclass 33, count 2 2006.257.13:20:58.28#ibcon#end of sib2, iclass 33, count 2 2006.257.13:20:58.28#ibcon#*mode == 0, iclass 33, count 2 2006.257.13:20:58.28#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.13:20:58.28#ibcon#[27=AT05-04\r\n] 2006.257.13:20:58.28#ibcon#*before write, iclass 33, count 2 2006.257.13:20:58.28#ibcon#enter sib2, iclass 33, count 2 2006.257.13:20:58.28#ibcon#flushed, iclass 33, count 2 2006.257.13:20:58.28#ibcon#about to write, iclass 33, count 2 2006.257.13:20:58.28#ibcon#wrote, iclass 33, count 2 2006.257.13:20:58.28#ibcon#about to read 3, iclass 33, count 2 2006.257.13:20:58.31#ibcon#read 3, iclass 33, count 2 2006.257.13:20:58.31#ibcon#about to read 4, iclass 33, count 2 2006.257.13:20:58.31#ibcon#read 4, iclass 33, count 2 2006.257.13:20:58.31#ibcon#about to read 5, iclass 33, count 2 2006.257.13:20:58.31#ibcon#read 5, iclass 33, count 2 2006.257.13:20:58.31#ibcon#about to read 6, iclass 33, count 2 2006.257.13:20:58.31#ibcon#read 6, iclass 33, count 2 2006.257.13:20:58.31#ibcon#end of sib2, iclass 33, count 2 2006.257.13:20:58.31#ibcon#*after write, iclass 33, count 2 2006.257.13:20:58.31#ibcon#*before return 0, iclass 33, count 2 2006.257.13:20:58.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:58.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:20:58.31#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.13:20:58.31#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:58.31#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:58.43#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:58.43#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:58.43#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:20:58.43#ibcon#first serial, iclass 33, count 0 2006.257.13:20:58.43#ibcon#enter sib2, iclass 33, count 0 2006.257.13:20:58.43#ibcon#flushed, iclass 33, count 0 2006.257.13:20:58.43#ibcon#about to write, iclass 33, count 0 2006.257.13:20:58.43#ibcon#wrote, iclass 33, count 0 2006.257.13:20:58.43#ibcon#about to read 3, iclass 33, count 0 2006.257.13:20:58.45#ibcon#read 3, iclass 33, count 0 2006.257.13:20:58.45#ibcon#about to read 4, iclass 33, count 0 2006.257.13:20:58.45#ibcon#read 4, iclass 33, count 0 2006.257.13:20:58.45#ibcon#about to read 5, iclass 33, count 0 2006.257.13:20:58.45#ibcon#read 5, iclass 33, count 0 2006.257.13:20:58.45#ibcon#about to read 6, iclass 33, count 0 2006.257.13:20:58.45#ibcon#read 6, iclass 33, count 0 2006.257.13:20:58.45#ibcon#end of sib2, iclass 33, count 0 2006.257.13:20:58.45#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:20:58.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:20:58.45#ibcon#[27=USB\r\n] 2006.257.13:20:58.45#ibcon#*before write, iclass 33, count 0 2006.257.13:20:58.45#ibcon#enter sib2, iclass 33, count 0 2006.257.13:20:58.45#ibcon#flushed, iclass 33, count 0 2006.257.13:20:58.45#ibcon#about to write, iclass 33, count 0 2006.257.13:20:58.45#ibcon#wrote, iclass 33, count 0 2006.257.13:20:58.45#ibcon#about to read 3, iclass 33, count 0 2006.257.13:20:58.48#ibcon#read 3, iclass 33, count 0 2006.257.13:20:58.48#ibcon#about to read 4, iclass 33, count 0 2006.257.13:20:58.48#ibcon#read 4, iclass 33, count 0 2006.257.13:20:58.48#ibcon#about to read 5, iclass 33, count 0 2006.257.13:20:58.48#ibcon#read 5, iclass 33, count 0 2006.257.13:20:58.48#ibcon#about to read 6, iclass 33, count 0 2006.257.13:20:58.48#ibcon#read 6, iclass 33, count 0 2006.257.13:20:58.48#ibcon#end of sib2, iclass 33, count 0 2006.257.13:20:58.48#ibcon#*after write, iclass 33, count 0 2006.257.13:20:58.48#ibcon#*before return 0, iclass 33, count 0 2006.257.13:20:58.48#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:58.48#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:20:58.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:20:58.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:20:58.48$vck44/vblo=6,719.99 2006.257.13:20:58.48#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.13:20:58.48#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.13:20:58.48#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:58.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:58.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:58.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:58.48#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:20:58.48#ibcon#first serial, iclass 35, count 0 2006.257.13:20:58.48#ibcon#enter sib2, iclass 35, count 0 2006.257.13:20:58.48#ibcon#flushed, iclass 35, count 0 2006.257.13:20:58.48#ibcon#about to write, iclass 35, count 0 2006.257.13:20:58.48#ibcon#wrote, iclass 35, count 0 2006.257.13:20:58.48#ibcon#about to read 3, iclass 35, count 0 2006.257.13:20:58.50#ibcon#read 3, iclass 35, count 0 2006.257.13:20:58.50#ibcon#about to read 4, iclass 35, count 0 2006.257.13:20:58.50#ibcon#read 4, iclass 35, count 0 2006.257.13:20:58.50#ibcon#about to read 5, iclass 35, count 0 2006.257.13:20:58.50#ibcon#read 5, iclass 35, count 0 2006.257.13:20:58.50#ibcon#about to read 6, iclass 35, count 0 2006.257.13:20:58.50#ibcon#read 6, iclass 35, count 0 2006.257.13:20:58.50#ibcon#end of sib2, iclass 35, count 0 2006.257.13:20:58.50#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:20:58.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:20:58.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:20:58.50#ibcon#*before write, iclass 35, count 0 2006.257.13:20:58.50#ibcon#enter sib2, iclass 35, count 0 2006.257.13:20:58.50#ibcon#flushed, iclass 35, count 0 2006.257.13:20:58.50#ibcon#about to write, iclass 35, count 0 2006.257.13:20:58.50#ibcon#wrote, iclass 35, count 0 2006.257.13:20:58.50#ibcon#about to read 3, iclass 35, count 0 2006.257.13:20:58.54#ibcon#read 3, iclass 35, count 0 2006.257.13:20:58.54#ibcon#about to read 4, iclass 35, count 0 2006.257.13:20:58.54#ibcon#read 4, iclass 35, count 0 2006.257.13:20:58.54#ibcon#about to read 5, iclass 35, count 0 2006.257.13:20:58.54#ibcon#read 5, iclass 35, count 0 2006.257.13:20:58.54#ibcon#about to read 6, iclass 35, count 0 2006.257.13:20:58.54#ibcon#read 6, iclass 35, count 0 2006.257.13:20:58.54#ibcon#end of sib2, iclass 35, count 0 2006.257.13:20:58.54#ibcon#*after write, iclass 35, count 0 2006.257.13:20:58.54#ibcon#*before return 0, iclass 35, count 0 2006.257.13:20:58.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:58.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:20:58.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:20:58.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:20:58.54$vck44/vb=6,4 2006.257.13:20:58.54#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.13:20:58.54#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.13:20:58.54#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:58.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:58.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:58.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:58.60#ibcon#enter wrdev, iclass 37, count 2 2006.257.13:20:58.60#ibcon#first serial, iclass 37, count 2 2006.257.13:20:58.60#ibcon#enter sib2, iclass 37, count 2 2006.257.13:20:58.60#ibcon#flushed, iclass 37, count 2 2006.257.13:20:58.60#ibcon#about to write, iclass 37, count 2 2006.257.13:20:58.60#ibcon#wrote, iclass 37, count 2 2006.257.13:20:58.60#ibcon#about to read 3, iclass 37, count 2 2006.257.13:20:58.62#ibcon#read 3, iclass 37, count 2 2006.257.13:20:58.62#ibcon#about to read 4, iclass 37, count 2 2006.257.13:20:58.62#ibcon#read 4, iclass 37, count 2 2006.257.13:20:58.62#ibcon#about to read 5, iclass 37, count 2 2006.257.13:20:58.62#ibcon#read 5, iclass 37, count 2 2006.257.13:20:58.62#ibcon#about to read 6, iclass 37, count 2 2006.257.13:20:58.62#ibcon#read 6, iclass 37, count 2 2006.257.13:20:58.62#ibcon#end of sib2, iclass 37, count 2 2006.257.13:20:58.62#ibcon#*mode == 0, iclass 37, count 2 2006.257.13:20:58.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.13:20:58.62#ibcon#[27=AT06-04\r\n] 2006.257.13:20:58.62#ibcon#*before write, iclass 37, count 2 2006.257.13:20:58.62#ibcon#enter sib2, iclass 37, count 2 2006.257.13:20:58.62#ibcon#flushed, iclass 37, count 2 2006.257.13:20:58.62#ibcon#about to write, iclass 37, count 2 2006.257.13:20:58.62#ibcon#wrote, iclass 37, count 2 2006.257.13:20:58.62#ibcon#about to read 3, iclass 37, count 2 2006.257.13:20:58.65#ibcon#read 3, iclass 37, count 2 2006.257.13:20:58.65#ibcon#about to read 4, iclass 37, count 2 2006.257.13:20:58.65#ibcon#read 4, iclass 37, count 2 2006.257.13:20:58.65#ibcon#about to read 5, iclass 37, count 2 2006.257.13:20:58.65#ibcon#read 5, iclass 37, count 2 2006.257.13:20:58.65#ibcon#about to read 6, iclass 37, count 2 2006.257.13:20:58.65#ibcon#read 6, iclass 37, count 2 2006.257.13:20:58.65#ibcon#end of sib2, iclass 37, count 2 2006.257.13:20:58.65#ibcon#*after write, iclass 37, count 2 2006.257.13:20:58.65#ibcon#*before return 0, iclass 37, count 2 2006.257.13:20:58.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:58.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:20:58.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.13:20:58.65#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:58.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:58.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:58.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:58.77#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:20:58.77#ibcon#first serial, iclass 37, count 0 2006.257.13:20:58.77#ibcon#enter sib2, iclass 37, count 0 2006.257.13:20:58.77#ibcon#flushed, iclass 37, count 0 2006.257.13:20:58.77#ibcon#about to write, iclass 37, count 0 2006.257.13:20:58.77#ibcon#wrote, iclass 37, count 0 2006.257.13:20:58.77#ibcon#about to read 3, iclass 37, count 0 2006.257.13:20:58.79#ibcon#read 3, iclass 37, count 0 2006.257.13:20:58.79#ibcon#about to read 4, iclass 37, count 0 2006.257.13:20:58.79#ibcon#read 4, iclass 37, count 0 2006.257.13:20:58.79#ibcon#about to read 5, iclass 37, count 0 2006.257.13:20:58.79#ibcon#read 5, iclass 37, count 0 2006.257.13:20:58.79#ibcon#about to read 6, iclass 37, count 0 2006.257.13:20:58.79#ibcon#read 6, iclass 37, count 0 2006.257.13:20:58.79#ibcon#end of sib2, iclass 37, count 0 2006.257.13:20:58.79#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:20:58.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:20:58.79#ibcon#[27=USB\r\n] 2006.257.13:20:58.79#ibcon#*before write, iclass 37, count 0 2006.257.13:20:58.79#ibcon#enter sib2, iclass 37, count 0 2006.257.13:20:58.79#ibcon#flushed, iclass 37, count 0 2006.257.13:20:58.79#ibcon#about to write, iclass 37, count 0 2006.257.13:20:58.79#ibcon#wrote, iclass 37, count 0 2006.257.13:20:58.79#ibcon#about to read 3, iclass 37, count 0 2006.257.13:20:58.82#ibcon#read 3, iclass 37, count 0 2006.257.13:20:58.82#ibcon#about to read 4, iclass 37, count 0 2006.257.13:20:58.82#ibcon#read 4, iclass 37, count 0 2006.257.13:20:58.82#ibcon#about to read 5, iclass 37, count 0 2006.257.13:20:58.82#ibcon#read 5, iclass 37, count 0 2006.257.13:20:58.82#ibcon#about to read 6, iclass 37, count 0 2006.257.13:20:58.82#ibcon#read 6, iclass 37, count 0 2006.257.13:20:58.82#ibcon#end of sib2, iclass 37, count 0 2006.257.13:20:58.82#ibcon#*after write, iclass 37, count 0 2006.257.13:20:58.82#ibcon#*before return 0, iclass 37, count 0 2006.257.13:20:58.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:58.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:20:58.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:20:58.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:20:58.82$vck44/vblo=7,734.99 2006.257.13:20:58.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:20:58.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:20:58.82#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:58.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:58.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:58.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:58.82#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:20:58.82#ibcon#first serial, iclass 39, count 0 2006.257.13:20:58.82#ibcon#enter sib2, iclass 39, count 0 2006.257.13:20:58.82#ibcon#flushed, iclass 39, count 0 2006.257.13:20:58.82#ibcon#about to write, iclass 39, count 0 2006.257.13:20:58.82#ibcon#wrote, iclass 39, count 0 2006.257.13:20:58.82#ibcon#about to read 3, iclass 39, count 0 2006.257.13:20:58.84#ibcon#read 3, iclass 39, count 0 2006.257.13:20:58.84#ibcon#about to read 4, iclass 39, count 0 2006.257.13:20:58.84#ibcon#read 4, iclass 39, count 0 2006.257.13:20:58.84#ibcon#about to read 5, iclass 39, count 0 2006.257.13:20:58.84#ibcon#read 5, iclass 39, count 0 2006.257.13:20:58.84#ibcon#about to read 6, iclass 39, count 0 2006.257.13:20:58.84#ibcon#read 6, iclass 39, count 0 2006.257.13:20:58.84#ibcon#end of sib2, iclass 39, count 0 2006.257.13:20:58.84#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:20:58.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:20:58.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:20:58.84#ibcon#*before write, iclass 39, count 0 2006.257.13:20:58.84#ibcon#enter sib2, iclass 39, count 0 2006.257.13:20:58.84#ibcon#flushed, iclass 39, count 0 2006.257.13:20:58.84#ibcon#about to write, iclass 39, count 0 2006.257.13:20:58.84#ibcon#wrote, iclass 39, count 0 2006.257.13:20:58.84#ibcon#about to read 3, iclass 39, count 0 2006.257.13:20:58.88#ibcon#read 3, iclass 39, count 0 2006.257.13:20:58.88#ibcon#about to read 4, iclass 39, count 0 2006.257.13:20:58.88#ibcon#read 4, iclass 39, count 0 2006.257.13:20:58.88#ibcon#about to read 5, iclass 39, count 0 2006.257.13:20:58.88#ibcon#read 5, iclass 39, count 0 2006.257.13:20:58.88#ibcon#about to read 6, iclass 39, count 0 2006.257.13:20:58.88#ibcon#read 6, iclass 39, count 0 2006.257.13:20:58.88#ibcon#end of sib2, iclass 39, count 0 2006.257.13:20:58.88#ibcon#*after write, iclass 39, count 0 2006.257.13:20:58.88#ibcon#*before return 0, iclass 39, count 0 2006.257.13:20:58.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:58.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:20:58.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:20:58.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:20:58.88$vck44/vb=7,4 2006.257.13:20:58.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.13:20:58.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.13:20:58.88#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:58.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:58.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:58.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:58.94#ibcon#enter wrdev, iclass 3, count 2 2006.257.13:20:58.94#ibcon#first serial, iclass 3, count 2 2006.257.13:20:58.94#ibcon#enter sib2, iclass 3, count 2 2006.257.13:20:58.94#ibcon#flushed, iclass 3, count 2 2006.257.13:20:58.94#ibcon#about to write, iclass 3, count 2 2006.257.13:20:58.94#ibcon#wrote, iclass 3, count 2 2006.257.13:20:58.94#ibcon#about to read 3, iclass 3, count 2 2006.257.13:20:58.96#ibcon#read 3, iclass 3, count 2 2006.257.13:20:58.96#ibcon#about to read 4, iclass 3, count 2 2006.257.13:20:58.96#ibcon#read 4, iclass 3, count 2 2006.257.13:20:58.96#ibcon#about to read 5, iclass 3, count 2 2006.257.13:20:58.96#ibcon#read 5, iclass 3, count 2 2006.257.13:20:58.96#ibcon#about to read 6, iclass 3, count 2 2006.257.13:20:58.96#ibcon#read 6, iclass 3, count 2 2006.257.13:20:58.96#ibcon#end of sib2, iclass 3, count 2 2006.257.13:20:58.96#ibcon#*mode == 0, iclass 3, count 2 2006.257.13:20:58.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.13:20:58.96#ibcon#[27=AT07-04\r\n] 2006.257.13:20:58.96#ibcon#*before write, iclass 3, count 2 2006.257.13:20:58.96#ibcon#enter sib2, iclass 3, count 2 2006.257.13:20:58.96#ibcon#flushed, iclass 3, count 2 2006.257.13:20:58.96#ibcon#about to write, iclass 3, count 2 2006.257.13:20:58.96#ibcon#wrote, iclass 3, count 2 2006.257.13:20:58.96#ibcon#about to read 3, iclass 3, count 2 2006.257.13:20:58.99#ibcon#read 3, iclass 3, count 2 2006.257.13:20:58.99#ibcon#about to read 4, iclass 3, count 2 2006.257.13:20:58.99#ibcon#read 4, iclass 3, count 2 2006.257.13:20:58.99#ibcon#about to read 5, iclass 3, count 2 2006.257.13:20:58.99#ibcon#read 5, iclass 3, count 2 2006.257.13:20:58.99#ibcon#about to read 6, iclass 3, count 2 2006.257.13:20:58.99#ibcon#read 6, iclass 3, count 2 2006.257.13:20:58.99#ibcon#end of sib2, iclass 3, count 2 2006.257.13:20:58.99#ibcon#*after write, iclass 3, count 2 2006.257.13:20:58.99#ibcon#*before return 0, iclass 3, count 2 2006.257.13:20:58.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:58.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:20:58.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.13:20:58.99#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:58.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:59.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:59.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:59.11#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:20:59.11#ibcon#first serial, iclass 3, count 0 2006.257.13:20:59.11#ibcon#enter sib2, iclass 3, count 0 2006.257.13:20:59.11#ibcon#flushed, iclass 3, count 0 2006.257.13:20:59.11#ibcon#about to write, iclass 3, count 0 2006.257.13:20:59.11#ibcon#wrote, iclass 3, count 0 2006.257.13:20:59.11#ibcon#about to read 3, iclass 3, count 0 2006.257.13:20:59.13#ibcon#read 3, iclass 3, count 0 2006.257.13:20:59.13#ibcon#about to read 4, iclass 3, count 0 2006.257.13:20:59.13#ibcon#read 4, iclass 3, count 0 2006.257.13:20:59.13#ibcon#about to read 5, iclass 3, count 0 2006.257.13:20:59.13#ibcon#read 5, iclass 3, count 0 2006.257.13:20:59.13#ibcon#about to read 6, iclass 3, count 0 2006.257.13:20:59.13#ibcon#read 6, iclass 3, count 0 2006.257.13:20:59.13#ibcon#end of sib2, iclass 3, count 0 2006.257.13:20:59.13#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:20:59.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:20:59.13#ibcon#[27=USB\r\n] 2006.257.13:20:59.13#ibcon#*before write, iclass 3, count 0 2006.257.13:20:59.13#ibcon#enter sib2, iclass 3, count 0 2006.257.13:20:59.13#ibcon#flushed, iclass 3, count 0 2006.257.13:20:59.13#ibcon#about to write, iclass 3, count 0 2006.257.13:20:59.13#ibcon#wrote, iclass 3, count 0 2006.257.13:20:59.13#ibcon#about to read 3, iclass 3, count 0 2006.257.13:20:59.16#ibcon#read 3, iclass 3, count 0 2006.257.13:20:59.16#ibcon#about to read 4, iclass 3, count 0 2006.257.13:20:59.16#ibcon#read 4, iclass 3, count 0 2006.257.13:20:59.16#ibcon#about to read 5, iclass 3, count 0 2006.257.13:20:59.16#ibcon#read 5, iclass 3, count 0 2006.257.13:20:59.16#ibcon#about to read 6, iclass 3, count 0 2006.257.13:20:59.16#ibcon#read 6, iclass 3, count 0 2006.257.13:20:59.16#ibcon#end of sib2, iclass 3, count 0 2006.257.13:20:59.16#ibcon#*after write, iclass 3, count 0 2006.257.13:20:59.16#ibcon#*before return 0, iclass 3, count 0 2006.257.13:20:59.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:59.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:20:59.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:20:59.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:20:59.16$vck44/vblo=8,744.99 2006.257.13:20:59.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.13:20:59.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.13:20:59.16#ibcon#ireg 17 cls_cnt 0 2006.257.13:20:59.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:59.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:59.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:59.16#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:20:59.16#ibcon#first serial, iclass 5, count 0 2006.257.13:20:59.16#ibcon#enter sib2, iclass 5, count 0 2006.257.13:20:59.16#ibcon#flushed, iclass 5, count 0 2006.257.13:20:59.16#ibcon#about to write, iclass 5, count 0 2006.257.13:20:59.16#ibcon#wrote, iclass 5, count 0 2006.257.13:20:59.16#ibcon#about to read 3, iclass 5, count 0 2006.257.13:20:59.18#ibcon#read 3, iclass 5, count 0 2006.257.13:20:59.18#ibcon#about to read 4, iclass 5, count 0 2006.257.13:20:59.18#ibcon#read 4, iclass 5, count 0 2006.257.13:20:59.18#ibcon#about to read 5, iclass 5, count 0 2006.257.13:20:59.18#ibcon#read 5, iclass 5, count 0 2006.257.13:20:59.18#ibcon#about to read 6, iclass 5, count 0 2006.257.13:20:59.18#ibcon#read 6, iclass 5, count 0 2006.257.13:20:59.18#ibcon#end of sib2, iclass 5, count 0 2006.257.13:20:59.18#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:20:59.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:20:59.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:20:59.18#ibcon#*before write, iclass 5, count 0 2006.257.13:20:59.18#ibcon#enter sib2, iclass 5, count 0 2006.257.13:20:59.18#ibcon#flushed, iclass 5, count 0 2006.257.13:20:59.18#ibcon#about to write, iclass 5, count 0 2006.257.13:20:59.18#ibcon#wrote, iclass 5, count 0 2006.257.13:20:59.18#ibcon#about to read 3, iclass 5, count 0 2006.257.13:20:59.22#ibcon#read 3, iclass 5, count 0 2006.257.13:20:59.22#ibcon#about to read 4, iclass 5, count 0 2006.257.13:20:59.22#ibcon#read 4, iclass 5, count 0 2006.257.13:20:59.22#ibcon#about to read 5, iclass 5, count 0 2006.257.13:20:59.22#ibcon#read 5, iclass 5, count 0 2006.257.13:20:59.22#ibcon#about to read 6, iclass 5, count 0 2006.257.13:20:59.22#ibcon#read 6, iclass 5, count 0 2006.257.13:20:59.22#ibcon#end of sib2, iclass 5, count 0 2006.257.13:20:59.22#ibcon#*after write, iclass 5, count 0 2006.257.13:20:59.22#ibcon#*before return 0, iclass 5, count 0 2006.257.13:20:59.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:59.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:20:59.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:20:59.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:20:59.22$vck44/vb=8,4 2006.257.13:20:59.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.13:20:59.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.13:20:59.22#ibcon#ireg 11 cls_cnt 2 2006.257.13:20:59.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:59.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:59.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:59.28#ibcon#enter wrdev, iclass 7, count 2 2006.257.13:20:59.28#ibcon#first serial, iclass 7, count 2 2006.257.13:20:59.28#ibcon#enter sib2, iclass 7, count 2 2006.257.13:20:59.28#ibcon#flushed, iclass 7, count 2 2006.257.13:20:59.28#ibcon#about to write, iclass 7, count 2 2006.257.13:20:59.28#ibcon#wrote, iclass 7, count 2 2006.257.13:20:59.28#ibcon#about to read 3, iclass 7, count 2 2006.257.13:20:59.30#ibcon#read 3, iclass 7, count 2 2006.257.13:20:59.30#ibcon#about to read 4, iclass 7, count 2 2006.257.13:20:59.30#ibcon#read 4, iclass 7, count 2 2006.257.13:20:59.30#ibcon#about to read 5, iclass 7, count 2 2006.257.13:20:59.30#ibcon#read 5, iclass 7, count 2 2006.257.13:20:59.30#ibcon#about to read 6, iclass 7, count 2 2006.257.13:20:59.30#ibcon#read 6, iclass 7, count 2 2006.257.13:20:59.30#ibcon#end of sib2, iclass 7, count 2 2006.257.13:20:59.30#ibcon#*mode == 0, iclass 7, count 2 2006.257.13:20:59.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.13:20:59.30#ibcon#[27=AT08-04\r\n] 2006.257.13:20:59.30#ibcon#*before write, iclass 7, count 2 2006.257.13:20:59.30#ibcon#enter sib2, iclass 7, count 2 2006.257.13:20:59.30#ibcon#flushed, iclass 7, count 2 2006.257.13:20:59.30#ibcon#about to write, iclass 7, count 2 2006.257.13:20:59.30#ibcon#wrote, iclass 7, count 2 2006.257.13:20:59.30#ibcon#about to read 3, iclass 7, count 2 2006.257.13:20:59.33#ibcon#read 3, iclass 7, count 2 2006.257.13:20:59.33#ibcon#about to read 4, iclass 7, count 2 2006.257.13:20:59.33#ibcon#read 4, iclass 7, count 2 2006.257.13:20:59.33#ibcon#about to read 5, iclass 7, count 2 2006.257.13:20:59.33#ibcon#read 5, iclass 7, count 2 2006.257.13:20:59.33#ibcon#about to read 6, iclass 7, count 2 2006.257.13:20:59.33#ibcon#read 6, iclass 7, count 2 2006.257.13:20:59.33#ibcon#end of sib2, iclass 7, count 2 2006.257.13:20:59.33#ibcon#*after write, iclass 7, count 2 2006.257.13:20:59.33#ibcon#*before return 0, iclass 7, count 2 2006.257.13:20:59.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:59.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:20:59.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.13:20:59.34#ibcon#ireg 7 cls_cnt 0 2006.257.13:20:59.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:59.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:59.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:59.44#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:20:59.44#ibcon#first serial, iclass 7, count 0 2006.257.13:20:59.44#ibcon#enter sib2, iclass 7, count 0 2006.257.13:20:59.44#ibcon#flushed, iclass 7, count 0 2006.257.13:20:59.44#ibcon#about to write, iclass 7, count 0 2006.257.13:20:59.44#ibcon#wrote, iclass 7, count 0 2006.257.13:20:59.44#ibcon#about to read 3, iclass 7, count 0 2006.257.13:20:59.46#ibcon#read 3, iclass 7, count 0 2006.257.13:20:59.46#ibcon#about to read 4, iclass 7, count 0 2006.257.13:20:59.46#ibcon#read 4, iclass 7, count 0 2006.257.13:20:59.46#ibcon#about to read 5, iclass 7, count 0 2006.257.13:20:59.46#ibcon#read 5, iclass 7, count 0 2006.257.13:20:59.46#ibcon#about to read 6, iclass 7, count 0 2006.257.13:20:59.46#ibcon#read 6, iclass 7, count 0 2006.257.13:20:59.46#ibcon#end of sib2, iclass 7, count 0 2006.257.13:20:59.46#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:20:59.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:20:59.46#ibcon#[27=USB\r\n] 2006.257.13:20:59.46#ibcon#*before write, iclass 7, count 0 2006.257.13:20:59.46#ibcon#enter sib2, iclass 7, count 0 2006.257.13:20:59.46#ibcon#flushed, iclass 7, count 0 2006.257.13:20:59.46#ibcon#about to write, iclass 7, count 0 2006.257.13:20:59.46#ibcon#wrote, iclass 7, count 0 2006.257.13:20:59.46#ibcon#about to read 3, iclass 7, count 0 2006.257.13:20:59.49#ibcon#read 3, iclass 7, count 0 2006.257.13:20:59.49#ibcon#about to read 4, iclass 7, count 0 2006.257.13:20:59.49#ibcon#read 4, iclass 7, count 0 2006.257.13:20:59.49#ibcon#about to read 5, iclass 7, count 0 2006.257.13:20:59.49#ibcon#read 5, iclass 7, count 0 2006.257.13:20:59.49#ibcon#about to read 6, iclass 7, count 0 2006.257.13:20:59.49#ibcon#read 6, iclass 7, count 0 2006.257.13:20:59.49#ibcon#end of sib2, iclass 7, count 0 2006.257.13:20:59.49#ibcon#*after write, iclass 7, count 0 2006.257.13:20:59.49#ibcon#*before return 0, iclass 7, count 0 2006.257.13:20:59.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:59.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:20:59.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:20:59.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:20:59.49$vck44/vabw=wide 2006.257.13:20:59.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.13:20:59.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.13:20:59.49#ibcon#ireg 8 cls_cnt 0 2006.257.13:20:59.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:59.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:59.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:59.49#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:20:59.49#ibcon#first serial, iclass 11, count 0 2006.257.13:20:59.49#ibcon#enter sib2, iclass 11, count 0 2006.257.13:20:59.49#ibcon#flushed, iclass 11, count 0 2006.257.13:20:59.49#ibcon#about to write, iclass 11, count 0 2006.257.13:20:59.49#ibcon#wrote, iclass 11, count 0 2006.257.13:20:59.49#ibcon#about to read 3, iclass 11, count 0 2006.257.13:20:59.51#ibcon#read 3, iclass 11, count 0 2006.257.13:20:59.51#ibcon#about to read 4, iclass 11, count 0 2006.257.13:20:59.51#ibcon#read 4, iclass 11, count 0 2006.257.13:20:59.51#ibcon#about to read 5, iclass 11, count 0 2006.257.13:20:59.51#ibcon#read 5, iclass 11, count 0 2006.257.13:20:59.51#ibcon#about to read 6, iclass 11, count 0 2006.257.13:20:59.51#ibcon#read 6, iclass 11, count 0 2006.257.13:20:59.51#ibcon#end of sib2, iclass 11, count 0 2006.257.13:20:59.51#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:20:59.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:20:59.51#ibcon#[25=BW32\r\n] 2006.257.13:20:59.51#ibcon#*before write, iclass 11, count 0 2006.257.13:20:59.51#ibcon#enter sib2, iclass 11, count 0 2006.257.13:20:59.51#ibcon#flushed, iclass 11, count 0 2006.257.13:20:59.51#ibcon#about to write, iclass 11, count 0 2006.257.13:20:59.51#ibcon#wrote, iclass 11, count 0 2006.257.13:20:59.51#ibcon#about to read 3, iclass 11, count 0 2006.257.13:20:59.54#ibcon#read 3, iclass 11, count 0 2006.257.13:20:59.54#ibcon#about to read 4, iclass 11, count 0 2006.257.13:20:59.54#ibcon#read 4, iclass 11, count 0 2006.257.13:20:59.54#ibcon#about to read 5, iclass 11, count 0 2006.257.13:20:59.54#ibcon#read 5, iclass 11, count 0 2006.257.13:20:59.54#ibcon#about to read 6, iclass 11, count 0 2006.257.13:20:59.54#ibcon#read 6, iclass 11, count 0 2006.257.13:20:59.54#ibcon#end of sib2, iclass 11, count 0 2006.257.13:20:59.54#ibcon#*after write, iclass 11, count 0 2006.257.13:20:59.54#ibcon#*before return 0, iclass 11, count 0 2006.257.13:20:59.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:59.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:20:59.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:20:59.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:20:59.54$vck44/vbbw=wide 2006.257.13:20:59.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:20:59.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:20:59.54#ibcon#ireg 8 cls_cnt 0 2006.257.13:20:59.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:20:59.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:20:59.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:20:59.61#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:20:59.61#ibcon#first serial, iclass 13, count 0 2006.257.13:20:59.61#ibcon#enter sib2, iclass 13, count 0 2006.257.13:20:59.61#ibcon#flushed, iclass 13, count 0 2006.257.13:20:59.61#ibcon#about to write, iclass 13, count 0 2006.257.13:20:59.61#ibcon#wrote, iclass 13, count 0 2006.257.13:20:59.61#ibcon#about to read 3, iclass 13, count 0 2006.257.13:20:59.63#ibcon#read 3, iclass 13, count 0 2006.257.13:20:59.63#ibcon#about to read 4, iclass 13, count 0 2006.257.13:20:59.63#ibcon#read 4, iclass 13, count 0 2006.257.13:20:59.63#ibcon#about to read 5, iclass 13, count 0 2006.257.13:20:59.63#ibcon#read 5, iclass 13, count 0 2006.257.13:20:59.63#ibcon#about to read 6, iclass 13, count 0 2006.257.13:20:59.63#ibcon#read 6, iclass 13, count 0 2006.257.13:20:59.63#ibcon#end of sib2, iclass 13, count 0 2006.257.13:20:59.63#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:20:59.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:20:59.63#ibcon#[27=BW32\r\n] 2006.257.13:20:59.63#ibcon#*before write, iclass 13, count 0 2006.257.13:20:59.63#ibcon#enter sib2, iclass 13, count 0 2006.257.13:20:59.63#ibcon#flushed, iclass 13, count 0 2006.257.13:20:59.63#ibcon#about to write, iclass 13, count 0 2006.257.13:20:59.63#ibcon#wrote, iclass 13, count 0 2006.257.13:20:59.63#ibcon#about to read 3, iclass 13, count 0 2006.257.13:20:59.66#ibcon#read 3, iclass 13, count 0 2006.257.13:20:59.66#ibcon#about to read 4, iclass 13, count 0 2006.257.13:20:59.66#ibcon#read 4, iclass 13, count 0 2006.257.13:20:59.66#ibcon#about to read 5, iclass 13, count 0 2006.257.13:20:59.66#ibcon#read 5, iclass 13, count 0 2006.257.13:20:59.66#ibcon#about to read 6, iclass 13, count 0 2006.257.13:20:59.66#ibcon#read 6, iclass 13, count 0 2006.257.13:20:59.66#ibcon#end of sib2, iclass 13, count 0 2006.257.13:20:59.66#ibcon#*after write, iclass 13, count 0 2006.257.13:20:59.66#ibcon#*before return 0, iclass 13, count 0 2006.257.13:20:59.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:20:59.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:20:59.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:20:59.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:20:59.66$setupk4/ifdk4 2006.257.13:20:59.66$ifdk4/lo= 2006.257.13:20:59.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:20:59.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:20:59.66$ifdk4/patch= 2006.257.13:20:59.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:20:59.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:20:59.66$setupk4/!*+20s 2006.257.13:21:03.94#abcon#<5=/14 1.4 4.3 17.63 971013.8\r\n> 2006.257.13:21:03.96#abcon#{5=INTERFACE CLEAR} 2006.257.13:21:04.02#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:21:14.11#abcon#<5=/14 1.3 4.3 17.63 971013.8\r\n> 2006.257.13:21:14.13#abcon#{5=INTERFACE CLEAR} 2006.257.13:21:14.19#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:21:14.19$setupk4/"tpicd 2006.257.13:21:14.19$setupk4/echo=off 2006.257.13:21:14.19$setupk4/xlog=off 2006.257.13:21:14.19:!2006.257.13:23:14 2006.257.13:21:38.13#trakl#Source acquired 2006.257.13:21:38.13#flagr#flagr/antenna,acquired 2006.257.13:23:14.00:preob 2006.257.13:23:15.14/onsource/TRACKING 2006.257.13:23:15.14:!2006.257.13:23:24 2006.257.13:23:24.00:"tape 2006.257.13:23:24.00:"st=record 2006.257.13:23:24.00:data_valid=on 2006.257.13:23:24.00:midob 2006.257.13:23:24.14/onsource/TRACKING 2006.257.13:23:24.14/wx/17.61,1013.8,97 2006.257.13:23:24.26/cable/+6.4808E-03 2006.257.13:23:25.35/va/01,08,usb,yes,31,33 2006.257.13:23:25.35/va/02,07,usb,yes,33,34 2006.257.13:23:25.35/va/03,08,usb,yes,30,32 2006.257.13:23:25.35/va/04,07,usb,yes,34,36 2006.257.13:23:25.35/va/05,04,usb,yes,31,31 2006.257.13:23:25.35/va/06,04,usb,yes,34,34 2006.257.13:23:25.35/va/07,04,usb,yes,35,35 2006.257.13:23:25.35/va/08,04,usb,yes,29,36 2006.257.13:23:25.58/valo/01,524.99,yes,locked 2006.257.13:23:25.58/valo/02,534.99,yes,locked 2006.257.13:23:25.58/valo/03,564.99,yes,locked 2006.257.13:23:25.58/valo/04,624.99,yes,locked 2006.257.13:23:25.58/valo/05,734.99,yes,locked 2006.257.13:23:25.58/valo/06,814.99,yes,locked 2006.257.13:23:25.58/valo/07,864.99,yes,locked 2006.257.13:23:25.58/valo/08,884.99,yes,locked 2006.257.13:23:26.67/vb/01,04,usb,yes,31,28 2006.257.13:23:26.67/vb/02,05,usb,yes,29,29 2006.257.13:23:26.67/vb/03,04,usb,yes,30,33 2006.257.13:23:26.67/vb/04,05,usb,yes,30,29 2006.257.13:23:26.67/vb/05,04,usb,yes,26,29 2006.257.13:23:26.67/vb/06,04,usb,yes,31,27 2006.257.13:23:26.67/vb/07,04,usb,yes,31,31 2006.257.13:23:26.67/vb/08,04,usb,yes,28,32 2006.257.13:23:26.91/vblo/01,629.99,yes,locked 2006.257.13:23:26.91/vblo/02,634.99,yes,locked 2006.257.13:23:26.91/vblo/03,649.99,yes,locked 2006.257.13:23:26.91/vblo/04,679.99,yes,locked 2006.257.13:23:26.91/vblo/05,709.99,yes,locked 2006.257.13:23:26.91/vblo/06,719.99,yes,locked 2006.257.13:23:26.91/vblo/07,734.99,yes,locked 2006.257.13:23:26.91/vblo/08,744.99,yes,locked 2006.257.13:23:27.06/vabw/8 2006.257.13:23:27.21/vbbw/8 2006.257.13:23:27.30/xfe/off,on,16.0 2006.257.13:23:27.68/ifatt/23,28,28,28 2006.257.13:23:28.07/fmout-gps/S +4.59E-07 2006.257.13:23:28.11:!2006.257.13:26:04 2006.257.13:26:04.01:data_valid=off 2006.257.13:26:04.02:"et 2006.257.13:26:04.02:!+3s 2006.257.13:26:07.03:"tape 2006.257.13:26:07.03:postob 2006.257.13:26:07.27/cable/+6.4805E-03 2006.257.13:26:07.27/wx/17.56,1013.9,97 2006.257.13:26:07.33/fmout-gps/S +4.60E-07 2006.257.13:26:07.33:scan_name=257-1328,jd0609,40 2006.257.13:26:07.33:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.257.13:26:09.14#flagr#flagr/antenna,new-source 2006.257.13:26:09.14:checkk5 2006.257.13:26:09.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:26:09.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:26:10.33/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:26:10.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:26:11.11/chk_obsdata//k5ts1/T2571323??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.13:26:11.50/chk_obsdata//k5ts2/T2571323??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.13:26:11.89/chk_obsdata//k5ts3/T2571323??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.13:26:12.29/chk_obsdata//k5ts4/T2571323??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.13:26:13.02/k5log//k5ts1_log_newline 2006.257.13:26:13.73/k5log//k5ts2_log_newline 2006.257.13:26:14.45/k5log//k5ts3_log_newline 2006.257.13:26:15.16/k5log//k5ts4_log_newline 2006.257.13:26:15.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:26:15.18:setupk4=1 2006.257.13:26:15.18$setupk4/echo=on 2006.257.13:26:15.18$setupk4/pcalon 2006.257.13:26:15.18$pcalon/"no phase cal control is implemented here 2006.257.13:26:15.18$setupk4/"tpicd=stop 2006.257.13:26:15.18$setupk4/"rec=synch_on 2006.257.13:26:15.18$setupk4/"rec_mode=128 2006.257.13:26:15.18$setupk4/!* 2006.257.13:26:15.18$setupk4/recpk4 2006.257.13:26:15.18$recpk4/recpatch= 2006.257.13:26:15.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:26:15.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:26:15.19$setupk4/vck44 2006.257.13:26:15.19$vck44/valo=1,524.99 2006.257.13:26:15.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.13:26:15.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.13:26:15.19#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:15.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:15.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:15.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:15.19#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:26:15.19#ibcon#first serial, iclass 34, count 0 2006.257.13:26:15.19#ibcon#enter sib2, iclass 34, count 0 2006.257.13:26:15.19#ibcon#flushed, iclass 34, count 0 2006.257.13:26:15.19#ibcon#about to write, iclass 34, count 0 2006.257.13:26:15.19#ibcon#wrote, iclass 34, count 0 2006.257.13:26:15.19#ibcon#about to read 3, iclass 34, count 0 2006.257.13:26:15.20#ibcon#read 3, iclass 34, count 0 2006.257.13:26:15.20#ibcon#about to read 4, iclass 34, count 0 2006.257.13:26:15.20#ibcon#read 4, iclass 34, count 0 2006.257.13:26:15.20#ibcon#about to read 5, iclass 34, count 0 2006.257.13:26:15.20#ibcon#read 5, iclass 34, count 0 2006.257.13:26:15.20#ibcon#about to read 6, iclass 34, count 0 2006.257.13:26:15.20#ibcon#read 6, iclass 34, count 0 2006.257.13:26:15.20#ibcon#end of sib2, iclass 34, count 0 2006.257.13:26:15.20#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:26:15.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:26:15.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:26:15.20#ibcon#*before write, iclass 34, count 0 2006.257.13:26:15.20#ibcon#enter sib2, iclass 34, count 0 2006.257.13:26:15.20#ibcon#flushed, iclass 34, count 0 2006.257.13:26:15.20#ibcon#about to write, iclass 34, count 0 2006.257.13:26:15.20#ibcon#wrote, iclass 34, count 0 2006.257.13:26:15.20#ibcon#about to read 3, iclass 34, count 0 2006.257.13:26:15.25#ibcon#read 3, iclass 34, count 0 2006.257.13:26:15.25#ibcon#about to read 4, iclass 34, count 0 2006.257.13:26:15.25#ibcon#read 4, iclass 34, count 0 2006.257.13:26:15.25#ibcon#about to read 5, iclass 34, count 0 2006.257.13:26:15.25#ibcon#read 5, iclass 34, count 0 2006.257.13:26:15.25#ibcon#about to read 6, iclass 34, count 0 2006.257.13:26:15.25#ibcon#read 6, iclass 34, count 0 2006.257.13:26:15.25#ibcon#end of sib2, iclass 34, count 0 2006.257.13:26:15.25#ibcon#*after write, iclass 34, count 0 2006.257.13:26:15.25#ibcon#*before return 0, iclass 34, count 0 2006.257.13:26:15.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:15.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:15.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:26:15.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:26:15.25$vck44/va=1,8 2006.257.13:26:15.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.13:26:15.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.13:26:15.25#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:15.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:15.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:15.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:15.25#ibcon#enter wrdev, iclass 36, count 2 2006.257.13:26:15.25#ibcon#first serial, iclass 36, count 2 2006.257.13:26:15.25#ibcon#enter sib2, iclass 36, count 2 2006.257.13:26:15.25#ibcon#flushed, iclass 36, count 2 2006.257.13:26:15.25#ibcon#about to write, iclass 36, count 2 2006.257.13:26:15.25#ibcon#wrote, iclass 36, count 2 2006.257.13:26:15.25#ibcon#about to read 3, iclass 36, count 2 2006.257.13:26:15.27#ibcon#read 3, iclass 36, count 2 2006.257.13:26:15.27#ibcon#about to read 4, iclass 36, count 2 2006.257.13:26:15.27#ibcon#read 4, iclass 36, count 2 2006.257.13:26:15.27#ibcon#about to read 5, iclass 36, count 2 2006.257.13:26:15.27#ibcon#read 5, iclass 36, count 2 2006.257.13:26:15.27#ibcon#about to read 6, iclass 36, count 2 2006.257.13:26:15.27#ibcon#read 6, iclass 36, count 2 2006.257.13:26:15.27#ibcon#end of sib2, iclass 36, count 2 2006.257.13:26:15.27#ibcon#*mode == 0, iclass 36, count 2 2006.257.13:26:15.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.13:26:15.27#ibcon#[25=AT01-08\r\n] 2006.257.13:26:15.27#ibcon#*before write, iclass 36, count 2 2006.257.13:26:15.27#ibcon#enter sib2, iclass 36, count 2 2006.257.13:26:15.27#ibcon#flushed, iclass 36, count 2 2006.257.13:26:15.27#ibcon#about to write, iclass 36, count 2 2006.257.13:26:15.27#ibcon#wrote, iclass 36, count 2 2006.257.13:26:15.27#ibcon#about to read 3, iclass 36, count 2 2006.257.13:26:15.30#ibcon#read 3, iclass 36, count 2 2006.257.13:26:15.30#ibcon#about to read 4, iclass 36, count 2 2006.257.13:26:15.30#ibcon#read 4, iclass 36, count 2 2006.257.13:26:15.30#ibcon#about to read 5, iclass 36, count 2 2006.257.13:26:15.30#ibcon#read 5, iclass 36, count 2 2006.257.13:26:15.30#ibcon#about to read 6, iclass 36, count 2 2006.257.13:26:15.30#ibcon#read 6, iclass 36, count 2 2006.257.13:26:15.30#ibcon#end of sib2, iclass 36, count 2 2006.257.13:26:15.30#ibcon#*after write, iclass 36, count 2 2006.257.13:26:15.30#ibcon#*before return 0, iclass 36, count 2 2006.257.13:26:15.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:15.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:15.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.13:26:15.30#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:15.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:15.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:15.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:15.42#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:26:15.42#ibcon#first serial, iclass 36, count 0 2006.257.13:26:15.42#ibcon#enter sib2, iclass 36, count 0 2006.257.13:26:15.42#ibcon#flushed, iclass 36, count 0 2006.257.13:26:15.42#ibcon#about to write, iclass 36, count 0 2006.257.13:26:15.42#ibcon#wrote, iclass 36, count 0 2006.257.13:26:15.42#ibcon#about to read 3, iclass 36, count 0 2006.257.13:26:15.44#ibcon#read 3, iclass 36, count 0 2006.257.13:26:15.44#ibcon#about to read 4, iclass 36, count 0 2006.257.13:26:15.44#ibcon#read 4, iclass 36, count 0 2006.257.13:26:15.44#ibcon#about to read 5, iclass 36, count 0 2006.257.13:26:15.44#ibcon#read 5, iclass 36, count 0 2006.257.13:26:15.44#ibcon#about to read 6, iclass 36, count 0 2006.257.13:26:15.44#ibcon#read 6, iclass 36, count 0 2006.257.13:26:15.44#ibcon#end of sib2, iclass 36, count 0 2006.257.13:26:15.44#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:26:15.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:26:15.44#ibcon#[25=USB\r\n] 2006.257.13:26:15.44#ibcon#*before write, iclass 36, count 0 2006.257.13:26:15.44#ibcon#enter sib2, iclass 36, count 0 2006.257.13:26:15.44#ibcon#flushed, iclass 36, count 0 2006.257.13:26:15.44#ibcon#about to write, iclass 36, count 0 2006.257.13:26:15.44#ibcon#wrote, iclass 36, count 0 2006.257.13:26:15.44#ibcon#about to read 3, iclass 36, count 0 2006.257.13:26:15.47#ibcon#read 3, iclass 36, count 0 2006.257.13:26:15.47#ibcon#about to read 4, iclass 36, count 0 2006.257.13:26:15.47#ibcon#read 4, iclass 36, count 0 2006.257.13:26:15.47#ibcon#about to read 5, iclass 36, count 0 2006.257.13:26:15.47#ibcon#read 5, iclass 36, count 0 2006.257.13:26:15.47#ibcon#about to read 6, iclass 36, count 0 2006.257.13:26:15.47#ibcon#read 6, iclass 36, count 0 2006.257.13:26:15.47#ibcon#end of sib2, iclass 36, count 0 2006.257.13:26:15.47#ibcon#*after write, iclass 36, count 0 2006.257.13:26:15.47#ibcon#*before return 0, iclass 36, count 0 2006.257.13:26:15.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:15.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:15.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:26:15.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:26:15.47$vck44/valo=2,534.99 2006.257.13:26:15.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.13:26:15.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.13:26:15.47#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:15.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:15.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:15.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:15.47#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:26:15.47#ibcon#first serial, iclass 38, count 0 2006.257.13:26:15.47#ibcon#enter sib2, iclass 38, count 0 2006.257.13:26:15.47#ibcon#flushed, iclass 38, count 0 2006.257.13:26:15.47#ibcon#about to write, iclass 38, count 0 2006.257.13:26:15.47#ibcon#wrote, iclass 38, count 0 2006.257.13:26:15.47#ibcon#about to read 3, iclass 38, count 0 2006.257.13:26:15.49#ibcon#read 3, iclass 38, count 0 2006.257.13:26:15.49#ibcon#about to read 4, iclass 38, count 0 2006.257.13:26:15.49#ibcon#read 4, iclass 38, count 0 2006.257.13:26:15.49#ibcon#about to read 5, iclass 38, count 0 2006.257.13:26:15.49#ibcon#read 5, iclass 38, count 0 2006.257.13:26:15.49#ibcon#about to read 6, iclass 38, count 0 2006.257.13:26:15.49#ibcon#read 6, iclass 38, count 0 2006.257.13:26:15.49#ibcon#end of sib2, iclass 38, count 0 2006.257.13:26:15.49#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:26:15.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:26:15.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:26:15.49#ibcon#*before write, iclass 38, count 0 2006.257.13:26:15.49#ibcon#enter sib2, iclass 38, count 0 2006.257.13:26:15.49#ibcon#flushed, iclass 38, count 0 2006.257.13:26:15.49#ibcon#about to write, iclass 38, count 0 2006.257.13:26:15.49#ibcon#wrote, iclass 38, count 0 2006.257.13:26:15.49#ibcon#about to read 3, iclass 38, count 0 2006.257.13:26:15.53#ibcon#read 3, iclass 38, count 0 2006.257.13:26:15.53#ibcon#about to read 4, iclass 38, count 0 2006.257.13:26:15.53#ibcon#read 4, iclass 38, count 0 2006.257.13:26:15.53#ibcon#about to read 5, iclass 38, count 0 2006.257.13:26:15.53#ibcon#read 5, iclass 38, count 0 2006.257.13:26:15.53#ibcon#about to read 6, iclass 38, count 0 2006.257.13:26:15.53#ibcon#read 6, iclass 38, count 0 2006.257.13:26:15.53#ibcon#end of sib2, iclass 38, count 0 2006.257.13:26:15.53#ibcon#*after write, iclass 38, count 0 2006.257.13:26:15.53#ibcon#*before return 0, iclass 38, count 0 2006.257.13:26:15.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:15.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:15.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:26:15.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:26:15.53$vck44/va=2,7 2006.257.13:26:15.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.13:26:15.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.13:26:15.53#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:15.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:15.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:15.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:15.59#ibcon#enter wrdev, iclass 40, count 2 2006.257.13:26:15.59#ibcon#first serial, iclass 40, count 2 2006.257.13:26:15.59#ibcon#enter sib2, iclass 40, count 2 2006.257.13:26:15.59#ibcon#flushed, iclass 40, count 2 2006.257.13:26:15.59#ibcon#about to write, iclass 40, count 2 2006.257.13:26:15.59#ibcon#wrote, iclass 40, count 2 2006.257.13:26:15.59#ibcon#about to read 3, iclass 40, count 2 2006.257.13:26:15.61#ibcon#read 3, iclass 40, count 2 2006.257.13:26:15.61#ibcon#about to read 4, iclass 40, count 2 2006.257.13:26:15.61#ibcon#read 4, iclass 40, count 2 2006.257.13:26:15.61#ibcon#about to read 5, iclass 40, count 2 2006.257.13:26:15.61#ibcon#read 5, iclass 40, count 2 2006.257.13:26:15.61#ibcon#about to read 6, iclass 40, count 2 2006.257.13:26:15.61#ibcon#read 6, iclass 40, count 2 2006.257.13:26:15.61#ibcon#end of sib2, iclass 40, count 2 2006.257.13:26:15.61#ibcon#*mode == 0, iclass 40, count 2 2006.257.13:26:15.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.13:26:15.61#ibcon#[25=AT02-07\r\n] 2006.257.13:26:15.61#ibcon#*before write, iclass 40, count 2 2006.257.13:26:15.61#ibcon#enter sib2, iclass 40, count 2 2006.257.13:26:15.61#ibcon#flushed, iclass 40, count 2 2006.257.13:26:15.61#ibcon#about to write, iclass 40, count 2 2006.257.13:26:15.61#ibcon#wrote, iclass 40, count 2 2006.257.13:26:15.61#ibcon#about to read 3, iclass 40, count 2 2006.257.13:26:15.64#ibcon#read 3, iclass 40, count 2 2006.257.13:26:15.64#ibcon#about to read 4, iclass 40, count 2 2006.257.13:26:15.64#ibcon#read 4, iclass 40, count 2 2006.257.13:26:15.64#ibcon#about to read 5, iclass 40, count 2 2006.257.13:26:15.64#ibcon#read 5, iclass 40, count 2 2006.257.13:26:15.64#ibcon#about to read 6, iclass 40, count 2 2006.257.13:26:15.64#ibcon#read 6, iclass 40, count 2 2006.257.13:26:15.64#ibcon#end of sib2, iclass 40, count 2 2006.257.13:26:15.64#ibcon#*after write, iclass 40, count 2 2006.257.13:26:15.64#ibcon#*before return 0, iclass 40, count 2 2006.257.13:26:15.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:15.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:15.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.13:26:15.64#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:15.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:15.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:15.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:15.76#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:26:15.76#ibcon#first serial, iclass 40, count 0 2006.257.13:26:15.76#ibcon#enter sib2, iclass 40, count 0 2006.257.13:26:15.76#ibcon#flushed, iclass 40, count 0 2006.257.13:26:15.76#ibcon#about to write, iclass 40, count 0 2006.257.13:26:15.76#ibcon#wrote, iclass 40, count 0 2006.257.13:26:15.76#ibcon#about to read 3, iclass 40, count 0 2006.257.13:26:15.78#ibcon#read 3, iclass 40, count 0 2006.257.13:26:15.78#ibcon#about to read 4, iclass 40, count 0 2006.257.13:26:15.78#ibcon#read 4, iclass 40, count 0 2006.257.13:26:15.78#ibcon#about to read 5, iclass 40, count 0 2006.257.13:26:15.78#ibcon#read 5, iclass 40, count 0 2006.257.13:26:15.78#ibcon#about to read 6, iclass 40, count 0 2006.257.13:26:15.78#ibcon#read 6, iclass 40, count 0 2006.257.13:26:15.78#ibcon#end of sib2, iclass 40, count 0 2006.257.13:26:15.78#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:26:15.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:26:15.78#ibcon#[25=USB\r\n] 2006.257.13:26:15.78#ibcon#*before write, iclass 40, count 0 2006.257.13:26:15.78#ibcon#enter sib2, iclass 40, count 0 2006.257.13:26:15.78#ibcon#flushed, iclass 40, count 0 2006.257.13:26:15.78#ibcon#about to write, iclass 40, count 0 2006.257.13:26:15.78#ibcon#wrote, iclass 40, count 0 2006.257.13:26:15.78#ibcon#about to read 3, iclass 40, count 0 2006.257.13:26:15.81#ibcon#read 3, iclass 40, count 0 2006.257.13:26:15.81#ibcon#about to read 4, iclass 40, count 0 2006.257.13:26:15.81#ibcon#read 4, iclass 40, count 0 2006.257.13:26:15.81#ibcon#about to read 5, iclass 40, count 0 2006.257.13:26:15.81#ibcon#read 5, iclass 40, count 0 2006.257.13:26:15.81#ibcon#about to read 6, iclass 40, count 0 2006.257.13:26:15.81#ibcon#read 6, iclass 40, count 0 2006.257.13:26:15.81#ibcon#end of sib2, iclass 40, count 0 2006.257.13:26:15.81#ibcon#*after write, iclass 40, count 0 2006.257.13:26:15.81#ibcon#*before return 0, iclass 40, count 0 2006.257.13:26:15.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:15.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:15.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:26:15.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:26:15.81$vck44/valo=3,564.99 2006.257.13:26:15.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.13:26:15.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.13:26:15.81#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:15.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:15.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:15.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:15.81#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:26:15.81#ibcon#first serial, iclass 4, count 0 2006.257.13:26:15.81#ibcon#enter sib2, iclass 4, count 0 2006.257.13:26:15.81#ibcon#flushed, iclass 4, count 0 2006.257.13:26:15.81#ibcon#about to write, iclass 4, count 0 2006.257.13:26:15.81#ibcon#wrote, iclass 4, count 0 2006.257.13:26:15.81#ibcon#about to read 3, iclass 4, count 0 2006.257.13:26:15.83#ibcon#read 3, iclass 4, count 0 2006.257.13:26:15.83#ibcon#about to read 4, iclass 4, count 0 2006.257.13:26:15.83#ibcon#read 4, iclass 4, count 0 2006.257.13:26:15.83#ibcon#about to read 5, iclass 4, count 0 2006.257.13:26:15.83#ibcon#read 5, iclass 4, count 0 2006.257.13:26:15.83#ibcon#about to read 6, iclass 4, count 0 2006.257.13:26:15.83#ibcon#read 6, iclass 4, count 0 2006.257.13:26:15.83#ibcon#end of sib2, iclass 4, count 0 2006.257.13:26:15.83#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:26:15.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:26:15.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:26:15.83#ibcon#*before write, iclass 4, count 0 2006.257.13:26:15.83#ibcon#enter sib2, iclass 4, count 0 2006.257.13:26:15.83#ibcon#flushed, iclass 4, count 0 2006.257.13:26:15.83#ibcon#about to write, iclass 4, count 0 2006.257.13:26:15.83#ibcon#wrote, iclass 4, count 0 2006.257.13:26:15.83#ibcon#about to read 3, iclass 4, count 0 2006.257.13:26:15.87#ibcon#read 3, iclass 4, count 0 2006.257.13:26:15.87#ibcon#about to read 4, iclass 4, count 0 2006.257.13:26:15.87#ibcon#read 4, iclass 4, count 0 2006.257.13:26:15.87#ibcon#about to read 5, iclass 4, count 0 2006.257.13:26:15.87#ibcon#read 5, iclass 4, count 0 2006.257.13:26:15.87#ibcon#about to read 6, iclass 4, count 0 2006.257.13:26:15.87#ibcon#read 6, iclass 4, count 0 2006.257.13:26:15.87#ibcon#end of sib2, iclass 4, count 0 2006.257.13:26:15.87#ibcon#*after write, iclass 4, count 0 2006.257.13:26:15.87#ibcon#*before return 0, iclass 4, count 0 2006.257.13:26:15.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:15.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:15.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:26:15.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:26:15.87$vck44/va=3,8 2006.257.13:26:15.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.13:26:15.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.13:26:15.87#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:15.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:15.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:15.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:15.93#ibcon#enter wrdev, iclass 6, count 2 2006.257.13:26:15.93#ibcon#first serial, iclass 6, count 2 2006.257.13:26:15.93#ibcon#enter sib2, iclass 6, count 2 2006.257.13:26:15.93#ibcon#flushed, iclass 6, count 2 2006.257.13:26:15.93#ibcon#about to write, iclass 6, count 2 2006.257.13:26:15.93#ibcon#wrote, iclass 6, count 2 2006.257.13:26:15.93#ibcon#about to read 3, iclass 6, count 2 2006.257.13:26:15.95#ibcon#read 3, iclass 6, count 2 2006.257.13:26:15.95#ibcon#about to read 4, iclass 6, count 2 2006.257.13:26:15.95#ibcon#read 4, iclass 6, count 2 2006.257.13:26:15.95#ibcon#about to read 5, iclass 6, count 2 2006.257.13:26:15.95#ibcon#read 5, iclass 6, count 2 2006.257.13:26:15.95#ibcon#about to read 6, iclass 6, count 2 2006.257.13:26:15.95#ibcon#read 6, iclass 6, count 2 2006.257.13:26:15.95#ibcon#end of sib2, iclass 6, count 2 2006.257.13:26:15.95#ibcon#*mode == 0, iclass 6, count 2 2006.257.13:26:15.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.13:26:15.95#ibcon#[25=AT03-08\r\n] 2006.257.13:26:15.95#ibcon#*before write, iclass 6, count 2 2006.257.13:26:15.95#ibcon#enter sib2, iclass 6, count 2 2006.257.13:26:15.95#ibcon#flushed, iclass 6, count 2 2006.257.13:26:15.95#ibcon#about to write, iclass 6, count 2 2006.257.13:26:15.95#ibcon#wrote, iclass 6, count 2 2006.257.13:26:15.95#ibcon#about to read 3, iclass 6, count 2 2006.257.13:26:15.98#ibcon#read 3, iclass 6, count 2 2006.257.13:26:15.98#ibcon#about to read 4, iclass 6, count 2 2006.257.13:26:15.98#ibcon#read 4, iclass 6, count 2 2006.257.13:26:15.98#ibcon#about to read 5, iclass 6, count 2 2006.257.13:26:15.98#ibcon#read 5, iclass 6, count 2 2006.257.13:26:15.98#ibcon#about to read 6, iclass 6, count 2 2006.257.13:26:15.98#ibcon#read 6, iclass 6, count 2 2006.257.13:26:15.98#ibcon#end of sib2, iclass 6, count 2 2006.257.13:26:15.98#ibcon#*after write, iclass 6, count 2 2006.257.13:26:15.98#ibcon#*before return 0, iclass 6, count 2 2006.257.13:26:15.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:15.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:15.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.13:26:15.98#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:15.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:16.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:16.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:16.10#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:26:16.10#ibcon#first serial, iclass 6, count 0 2006.257.13:26:16.10#ibcon#enter sib2, iclass 6, count 0 2006.257.13:26:16.10#ibcon#flushed, iclass 6, count 0 2006.257.13:26:16.10#ibcon#about to write, iclass 6, count 0 2006.257.13:26:16.10#ibcon#wrote, iclass 6, count 0 2006.257.13:26:16.10#ibcon#about to read 3, iclass 6, count 0 2006.257.13:26:16.12#ibcon#read 3, iclass 6, count 0 2006.257.13:26:16.12#ibcon#about to read 4, iclass 6, count 0 2006.257.13:26:16.12#ibcon#read 4, iclass 6, count 0 2006.257.13:26:16.12#ibcon#about to read 5, iclass 6, count 0 2006.257.13:26:16.12#ibcon#read 5, iclass 6, count 0 2006.257.13:26:16.12#ibcon#about to read 6, iclass 6, count 0 2006.257.13:26:16.12#ibcon#read 6, iclass 6, count 0 2006.257.13:26:16.12#ibcon#end of sib2, iclass 6, count 0 2006.257.13:26:16.12#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:26:16.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:26:16.12#ibcon#[25=USB\r\n] 2006.257.13:26:16.12#ibcon#*before write, iclass 6, count 0 2006.257.13:26:16.12#ibcon#enter sib2, iclass 6, count 0 2006.257.13:26:16.12#ibcon#flushed, iclass 6, count 0 2006.257.13:26:16.12#ibcon#about to write, iclass 6, count 0 2006.257.13:26:16.12#ibcon#wrote, iclass 6, count 0 2006.257.13:26:16.12#ibcon#about to read 3, iclass 6, count 0 2006.257.13:26:16.15#ibcon#read 3, iclass 6, count 0 2006.257.13:26:16.15#ibcon#about to read 4, iclass 6, count 0 2006.257.13:26:16.15#ibcon#read 4, iclass 6, count 0 2006.257.13:26:16.15#ibcon#about to read 5, iclass 6, count 0 2006.257.13:26:16.15#ibcon#read 5, iclass 6, count 0 2006.257.13:26:16.15#ibcon#about to read 6, iclass 6, count 0 2006.257.13:26:16.15#ibcon#read 6, iclass 6, count 0 2006.257.13:26:16.15#ibcon#end of sib2, iclass 6, count 0 2006.257.13:26:16.15#ibcon#*after write, iclass 6, count 0 2006.257.13:26:16.15#ibcon#*before return 0, iclass 6, count 0 2006.257.13:26:16.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:16.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:16.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:26:16.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:26:16.15$vck44/valo=4,624.99 2006.257.13:26:16.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.13:26:16.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.13:26:16.15#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:16.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:16.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:16.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:16.15#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:26:16.15#ibcon#first serial, iclass 10, count 0 2006.257.13:26:16.15#ibcon#enter sib2, iclass 10, count 0 2006.257.13:26:16.15#ibcon#flushed, iclass 10, count 0 2006.257.13:26:16.15#ibcon#about to write, iclass 10, count 0 2006.257.13:26:16.15#ibcon#wrote, iclass 10, count 0 2006.257.13:26:16.15#ibcon#about to read 3, iclass 10, count 0 2006.257.13:26:16.17#ibcon#read 3, iclass 10, count 0 2006.257.13:26:16.17#ibcon#about to read 4, iclass 10, count 0 2006.257.13:26:16.17#ibcon#read 4, iclass 10, count 0 2006.257.13:26:16.17#ibcon#about to read 5, iclass 10, count 0 2006.257.13:26:16.17#ibcon#read 5, iclass 10, count 0 2006.257.13:26:16.17#ibcon#about to read 6, iclass 10, count 0 2006.257.13:26:16.17#ibcon#read 6, iclass 10, count 0 2006.257.13:26:16.17#ibcon#end of sib2, iclass 10, count 0 2006.257.13:26:16.17#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:26:16.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:26:16.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:26:16.17#ibcon#*before write, iclass 10, count 0 2006.257.13:26:16.17#ibcon#enter sib2, iclass 10, count 0 2006.257.13:26:16.17#ibcon#flushed, iclass 10, count 0 2006.257.13:26:16.17#ibcon#about to write, iclass 10, count 0 2006.257.13:26:16.17#ibcon#wrote, iclass 10, count 0 2006.257.13:26:16.17#ibcon#about to read 3, iclass 10, count 0 2006.257.13:26:16.21#ibcon#read 3, iclass 10, count 0 2006.257.13:26:16.21#ibcon#about to read 4, iclass 10, count 0 2006.257.13:26:16.21#ibcon#read 4, iclass 10, count 0 2006.257.13:26:16.21#ibcon#about to read 5, iclass 10, count 0 2006.257.13:26:16.21#ibcon#read 5, iclass 10, count 0 2006.257.13:26:16.21#ibcon#about to read 6, iclass 10, count 0 2006.257.13:26:16.21#ibcon#read 6, iclass 10, count 0 2006.257.13:26:16.21#ibcon#end of sib2, iclass 10, count 0 2006.257.13:26:16.21#ibcon#*after write, iclass 10, count 0 2006.257.13:26:16.21#ibcon#*before return 0, iclass 10, count 0 2006.257.13:26:16.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:16.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:16.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:26:16.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:26:16.21$vck44/va=4,7 2006.257.13:26:16.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.13:26:16.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.13:26:16.21#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:16.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:16.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:16.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:16.27#ibcon#enter wrdev, iclass 12, count 2 2006.257.13:26:16.27#ibcon#first serial, iclass 12, count 2 2006.257.13:26:16.27#ibcon#enter sib2, iclass 12, count 2 2006.257.13:26:16.27#ibcon#flushed, iclass 12, count 2 2006.257.13:26:16.27#ibcon#about to write, iclass 12, count 2 2006.257.13:26:16.27#ibcon#wrote, iclass 12, count 2 2006.257.13:26:16.27#ibcon#about to read 3, iclass 12, count 2 2006.257.13:26:16.29#ibcon#read 3, iclass 12, count 2 2006.257.13:26:16.29#ibcon#about to read 4, iclass 12, count 2 2006.257.13:26:16.29#ibcon#read 4, iclass 12, count 2 2006.257.13:26:16.29#ibcon#about to read 5, iclass 12, count 2 2006.257.13:26:16.29#ibcon#read 5, iclass 12, count 2 2006.257.13:26:16.29#ibcon#about to read 6, iclass 12, count 2 2006.257.13:26:16.29#ibcon#read 6, iclass 12, count 2 2006.257.13:26:16.29#ibcon#end of sib2, iclass 12, count 2 2006.257.13:26:16.29#ibcon#*mode == 0, iclass 12, count 2 2006.257.13:26:16.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.13:26:16.29#ibcon#[25=AT04-07\r\n] 2006.257.13:26:16.29#ibcon#*before write, iclass 12, count 2 2006.257.13:26:16.29#ibcon#enter sib2, iclass 12, count 2 2006.257.13:26:16.29#ibcon#flushed, iclass 12, count 2 2006.257.13:26:16.29#ibcon#about to write, iclass 12, count 2 2006.257.13:26:16.29#ibcon#wrote, iclass 12, count 2 2006.257.13:26:16.29#ibcon#about to read 3, iclass 12, count 2 2006.257.13:26:16.32#ibcon#read 3, iclass 12, count 2 2006.257.13:26:16.32#ibcon#about to read 4, iclass 12, count 2 2006.257.13:26:16.32#ibcon#read 4, iclass 12, count 2 2006.257.13:26:16.32#ibcon#about to read 5, iclass 12, count 2 2006.257.13:26:16.32#ibcon#read 5, iclass 12, count 2 2006.257.13:26:16.32#ibcon#about to read 6, iclass 12, count 2 2006.257.13:26:16.32#ibcon#read 6, iclass 12, count 2 2006.257.13:26:16.32#ibcon#end of sib2, iclass 12, count 2 2006.257.13:26:16.32#ibcon#*after write, iclass 12, count 2 2006.257.13:26:16.32#ibcon#*before return 0, iclass 12, count 2 2006.257.13:26:16.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:16.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:16.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.13:26:16.32#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:16.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:16.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:16.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:16.44#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:26:16.44#ibcon#first serial, iclass 12, count 0 2006.257.13:26:16.44#ibcon#enter sib2, iclass 12, count 0 2006.257.13:26:16.44#ibcon#flushed, iclass 12, count 0 2006.257.13:26:16.44#ibcon#about to write, iclass 12, count 0 2006.257.13:26:16.44#ibcon#wrote, iclass 12, count 0 2006.257.13:26:16.44#ibcon#about to read 3, iclass 12, count 0 2006.257.13:26:16.46#ibcon#read 3, iclass 12, count 0 2006.257.13:26:16.46#ibcon#about to read 4, iclass 12, count 0 2006.257.13:26:16.46#ibcon#read 4, iclass 12, count 0 2006.257.13:26:16.46#ibcon#about to read 5, iclass 12, count 0 2006.257.13:26:16.46#ibcon#read 5, iclass 12, count 0 2006.257.13:26:16.46#ibcon#about to read 6, iclass 12, count 0 2006.257.13:26:16.46#ibcon#read 6, iclass 12, count 0 2006.257.13:26:16.46#ibcon#end of sib2, iclass 12, count 0 2006.257.13:26:16.46#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:26:16.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:26:16.46#ibcon#[25=USB\r\n] 2006.257.13:26:16.46#ibcon#*before write, iclass 12, count 0 2006.257.13:26:16.46#ibcon#enter sib2, iclass 12, count 0 2006.257.13:26:16.46#ibcon#flushed, iclass 12, count 0 2006.257.13:26:16.46#ibcon#about to write, iclass 12, count 0 2006.257.13:26:16.46#ibcon#wrote, iclass 12, count 0 2006.257.13:26:16.46#ibcon#about to read 3, iclass 12, count 0 2006.257.13:26:16.49#ibcon#read 3, iclass 12, count 0 2006.257.13:26:16.49#ibcon#about to read 4, iclass 12, count 0 2006.257.13:26:16.49#ibcon#read 4, iclass 12, count 0 2006.257.13:26:16.49#ibcon#about to read 5, iclass 12, count 0 2006.257.13:26:16.49#ibcon#read 5, iclass 12, count 0 2006.257.13:26:16.49#ibcon#about to read 6, iclass 12, count 0 2006.257.13:26:16.49#ibcon#read 6, iclass 12, count 0 2006.257.13:26:16.49#ibcon#end of sib2, iclass 12, count 0 2006.257.13:26:16.49#ibcon#*after write, iclass 12, count 0 2006.257.13:26:16.49#ibcon#*before return 0, iclass 12, count 0 2006.257.13:26:16.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:16.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:16.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:26:16.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:26:16.49$vck44/valo=5,734.99 2006.257.13:26:16.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.13:26:16.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.13:26:16.49#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:16.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:26:16.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:26:16.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:26:16.49#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:26:16.49#ibcon#first serial, iclass 14, count 0 2006.257.13:26:16.49#ibcon#enter sib2, iclass 14, count 0 2006.257.13:26:16.49#ibcon#flushed, iclass 14, count 0 2006.257.13:26:16.49#ibcon#about to write, iclass 14, count 0 2006.257.13:26:16.49#ibcon#wrote, iclass 14, count 0 2006.257.13:26:16.49#ibcon#about to read 3, iclass 14, count 0 2006.257.13:26:16.51#ibcon#read 3, iclass 14, count 0 2006.257.13:26:16.51#ibcon#about to read 4, iclass 14, count 0 2006.257.13:26:16.51#ibcon#read 4, iclass 14, count 0 2006.257.13:26:16.51#ibcon#about to read 5, iclass 14, count 0 2006.257.13:26:16.51#ibcon#read 5, iclass 14, count 0 2006.257.13:26:16.51#ibcon#about to read 6, iclass 14, count 0 2006.257.13:26:16.51#ibcon#read 6, iclass 14, count 0 2006.257.13:26:16.51#ibcon#end of sib2, iclass 14, count 0 2006.257.13:26:16.51#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:26:16.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:26:16.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:26:16.51#ibcon#*before write, iclass 14, count 0 2006.257.13:26:16.51#ibcon#enter sib2, iclass 14, count 0 2006.257.13:26:16.51#ibcon#flushed, iclass 14, count 0 2006.257.13:26:16.51#ibcon#about to write, iclass 14, count 0 2006.257.13:26:16.51#ibcon#wrote, iclass 14, count 0 2006.257.13:26:16.51#ibcon#about to read 3, iclass 14, count 0 2006.257.13:26:16.55#ibcon#read 3, iclass 14, count 0 2006.257.13:26:16.55#ibcon#about to read 4, iclass 14, count 0 2006.257.13:26:16.55#ibcon#read 4, iclass 14, count 0 2006.257.13:26:16.55#ibcon#about to read 5, iclass 14, count 0 2006.257.13:26:16.55#ibcon#read 5, iclass 14, count 0 2006.257.13:26:16.55#ibcon#about to read 6, iclass 14, count 0 2006.257.13:26:16.55#ibcon#read 6, iclass 14, count 0 2006.257.13:26:16.55#ibcon#end of sib2, iclass 14, count 0 2006.257.13:26:16.55#ibcon#*after write, iclass 14, count 0 2006.257.13:26:16.55#ibcon#*before return 0, iclass 14, count 0 2006.257.13:26:16.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:26:16.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:26:16.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:26:16.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:26:16.55$vck44/va=5,4 2006.257.13:26:16.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.13:26:16.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.13:26:16.55#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:16.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:26:16.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:26:16.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:26:16.61#ibcon#enter wrdev, iclass 16, count 2 2006.257.13:26:16.61#ibcon#first serial, iclass 16, count 2 2006.257.13:26:16.61#ibcon#enter sib2, iclass 16, count 2 2006.257.13:26:16.61#ibcon#flushed, iclass 16, count 2 2006.257.13:26:16.61#ibcon#about to write, iclass 16, count 2 2006.257.13:26:16.61#ibcon#wrote, iclass 16, count 2 2006.257.13:26:16.61#ibcon#about to read 3, iclass 16, count 2 2006.257.13:26:16.63#ibcon#read 3, iclass 16, count 2 2006.257.13:26:16.63#ibcon#about to read 4, iclass 16, count 2 2006.257.13:26:16.63#ibcon#read 4, iclass 16, count 2 2006.257.13:26:16.63#ibcon#about to read 5, iclass 16, count 2 2006.257.13:26:16.63#ibcon#read 5, iclass 16, count 2 2006.257.13:26:16.63#ibcon#about to read 6, iclass 16, count 2 2006.257.13:26:16.63#ibcon#read 6, iclass 16, count 2 2006.257.13:26:16.63#ibcon#end of sib2, iclass 16, count 2 2006.257.13:26:16.63#ibcon#*mode == 0, iclass 16, count 2 2006.257.13:26:16.63#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.13:26:16.63#ibcon#[25=AT05-04\r\n] 2006.257.13:26:16.63#ibcon#*before write, iclass 16, count 2 2006.257.13:26:16.63#ibcon#enter sib2, iclass 16, count 2 2006.257.13:26:16.63#ibcon#flushed, iclass 16, count 2 2006.257.13:26:16.63#ibcon#about to write, iclass 16, count 2 2006.257.13:26:16.63#ibcon#wrote, iclass 16, count 2 2006.257.13:26:16.63#ibcon#about to read 3, iclass 16, count 2 2006.257.13:26:16.66#ibcon#read 3, iclass 16, count 2 2006.257.13:26:16.66#ibcon#about to read 4, iclass 16, count 2 2006.257.13:26:16.66#ibcon#read 4, iclass 16, count 2 2006.257.13:26:16.66#ibcon#about to read 5, iclass 16, count 2 2006.257.13:26:16.66#ibcon#read 5, iclass 16, count 2 2006.257.13:26:16.66#ibcon#about to read 6, iclass 16, count 2 2006.257.13:26:16.66#ibcon#read 6, iclass 16, count 2 2006.257.13:26:16.66#ibcon#end of sib2, iclass 16, count 2 2006.257.13:26:16.66#ibcon#*after write, iclass 16, count 2 2006.257.13:26:16.66#ibcon#*before return 0, iclass 16, count 2 2006.257.13:26:16.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:26:16.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:26:16.66#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.13:26:16.66#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:16.66#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:26:16.78#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:26:16.78#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:26:16.78#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:26:16.78#ibcon#first serial, iclass 16, count 0 2006.257.13:26:16.78#ibcon#enter sib2, iclass 16, count 0 2006.257.13:26:16.78#ibcon#flushed, iclass 16, count 0 2006.257.13:26:16.78#ibcon#about to write, iclass 16, count 0 2006.257.13:26:16.78#ibcon#wrote, iclass 16, count 0 2006.257.13:26:16.78#ibcon#about to read 3, iclass 16, count 0 2006.257.13:26:16.80#ibcon#read 3, iclass 16, count 0 2006.257.13:26:16.80#ibcon#about to read 4, iclass 16, count 0 2006.257.13:26:16.80#ibcon#read 4, iclass 16, count 0 2006.257.13:26:16.80#ibcon#about to read 5, iclass 16, count 0 2006.257.13:26:16.80#ibcon#read 5, iclass 16, count 0 2006.257.13:26:16.80#ibcon#about to read 6, iclass 16, count 0 2006.257.13:26:16.80#ibcon#read 6, iclass 16, count 0 2006.257.13:26:16.80#ibcon#end of sib2, iclass 16, count 0 2006.257.13:26:16.80#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:26:16.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:26:16.80#ibcon#[25=USB\r\n] 2006.257.13:26:16.80#ibcon#*before write, iclass 16, count 0 2006.257.13:26:16.80#ibcon#enter sib2, iclass 16, count 0 2006.257.13:26:16.80#ibcon#flushed, iclass 16, count 0 2006.257.13:26:16.80#ibcon#about to write, iclass 16, count 0 2006.257.13:26:16.80#ibcon#wrote, iclass 16, count 0 2006.257.13:26:16.80#ibcon#about to read 3, iclass 16, count 0 2006.257.13:26:16.83#ibcon#read 3, iclass 16, count 0 2006.257.13:26:16.83#ibcon#about to read 4, iclass 16, count 0 2006.257.13:26:16.83#ibcon#read 4, iclass 16, count 0 2006.257.13:26:16.83#ibcon#about to read 5, iclass 16, count 0 2006.257.13:26:16.83#ibcon#read 5, iclass 16, count 0 2006.257.13:26:16.83#ibcon#about to read 6, iclass 16, count 0 2006.257.13:26:16.83#ibcon#read 6, iclass 16, count 0 2006.257.13:26:16.83#ibcon#end of sib2, iclass 16, count 0 2006.257.13:26:16.83#ibcon#*after write, iclass 16, count 0 2006.257.13:26:16.83#ibcon#*before return 0, iclass 16, count 0 2006.257.13:26:16.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:26:16.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:26:16.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:26:16.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:26:16.83$vck44/valo=6,814.99 2006.257.13:26:16.83#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.13:26:16.83#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.13:26:16.83#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:16.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:16.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:16.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:16.83#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:26:16.83#ibcon#first serial, iclass 18, count 0 2006.257.13:26:16.83#ibcon#enter sib2, iclass 18, count 0 2006.257.13:26:16.83#ibcon#flushed, iclass 18, count 0 2006.257.13:26:16.83#ibcon#about to write, iclass 18, count 0 2006.257.13:26:16.83#ibcon#wrote, iclass 18, count 0 2006.257.13:26:16.83#ibcon#about to read 3, iclass 18, count 0 2006.257.13:26:16.85#ibcon#read 3, iclass 18, count 0 2006.257.13:26:16.85#ibcon#about to read 4, iclass 18, count 0 2006.257.13:26:16.85#ibcon#read 4, iclass 18, count 0 2006.257.13:26:16.85#ibcon#about to read 5, iclass 18, count 0 2006.257.13:26:16.85#ibcon#read 5, iclass 18, count 0 2006.257.13:26:16.85#ibcon#about to read 6, iclass 18, count 0 2006.257.13:26:16.85#ibcon#read 6, iclass 18, count 0 2006.257.13:26:16.85#ibcon#end of sib2, iclass 18, count 0 2006.257.13:26:16.85#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:26:16.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:26:16.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:26:16.85#ibcon#*before write, iclass 18, count 0 2006.257.13:26:16.85#ibcon#enter sib2, iclass 18, count 0 2006.257.13:26:16.85#ibcon#flushed, iclass 18, count 0 2006.257.13:26:16.85#ibcon#about to write, iclass 18, count 0 2006.257.13:26:16.85#ibcon#wrote, iclass 18, count 0 2006.257.13:26:16.85#ibcon#about to read 3, iclass 18, count 0 2006.257.13:26:16.89#ibcon#read 3, iclass 18, count 0 2006.257.13:26:16.89#ibcon#about to read 4, iclass 18, count 0 2006.257.13:26:16.89#ibcon#read 4, iclass 18, count 0 2006.257.13:26:16.89#ibcon#about to read 5, iclass 18, count 0 2006.257.13:26:16.89#ibcon#read 5, iclass 18, count 0 2006.257.13:26:16.89#ibcon#about to read 6, iclass 18, count 0 2006.257.13:26:16.89#ibcon#read 6, iclass 18, count 0 2006.257.13:26:16.89#ibcon#end of sib2, iclass 18, count 0 2006.257.13:26:16.89#ibcon#*after write, iclass 18, count 0 2006.257.13:26:16.89#ibcon#*before return 0, iclass 18, count 0 2006.257.13:26:16.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:16.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:16.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:26:16.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:26:16.89$vck44/va=6,4 2006.257.13:26:16.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.13:26:16.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.13:26:16.89#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:16.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:16.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:16.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:16.95#ibcon#enter wrdev, iclass 20, count 2 2006.257.13:26:16.95#ibcon#first serial, iclass 20, count 2 2006.257.13:26:16.95#ibcon#enter sib2, iclass 20, count 2 2006.257.13:26:16.95#ibcon#flushed, iclass 20, count 2 2006.257.13:26:16.95#ibcon#about to write, iclass 20, count 2 2006.257.13:26:16.95#ibcon#wrote, iclass 20, count 2 2006.257.13:26:16.95#ibcon#about to read 3, iclass 20, count 2 2006.257.13:26:16.97#ibcon#read 3, iclass 20, count 2 2006.257.13:26:16.97#ibcon#about to read 4, iclass 20, count 2 2006.257.13:26:16.97#ibcon#read 4, iclass 20, count 2 2006.257.13:26:16.97#ibcon#about to read 5, iclass 20, count 2 2006.257.13:26:16.97#ibcon#read 5, iclass 20, count 2 2006.257.13:26:16.97#ibcon#about to read 6, iclass 20, count 2 2006.257.13:26:16.97#ibcon#read 6, iclass 20, count 2 2006.257.13:26:16.97#ibcon#end of sib2, iclass 20, count 2 2006.257.13:26:16.97#ibcon#*mode == 0, iclass 20, count 2 2006.257.13:26:16.97#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.13:26:16.97#ibcon#[25=AT06-04\r\n] 2006.257.13:26:16.97#ibcon#*before write, iclass 20, count 2 2006.257.13:26:16.97#ibcon#enter sib2, iclass 20, count 2 2006.257.13:26:16.97#ibcon#flushed, iclass 20, count 2 2006.257.13:26:16.97#ibcon#about to write, iclass 20, count 2 2006.257.13:26:16.97#ibcon#wrote, iclass 20, count 2 2006.257.13:26:16.97#ibcon#about to read 3, iclass 20, count 2 2006.257.13:26:17.00#ibcon#read 3, iclass 20, count 2 2006.257.13:26:17.00#ibcon#about to read 4, iclass 20, count 2 2006.257.13:26:17.00#ibcon#read 4, iclass 20, count 2 2006.257.13:26:17.00#ibcon#about to read 5, iclass 20, count 2 2006.257.13:26:17.00#ibcon#read 5, iclass 20, count 2 2006.257.13:26:17.00#ibcon#about to read 6, iclass 20, count 2 2006.257.13:26:17.00#ibcon#read 6, iclass 20, count 2 2006.257.13:26:17.00#ibcon#end of sib2, iclass 20, count 2 2006.257.13:26:17.00#ibcon#*after write, iclass 20, count 2 2006.257.13:26:17.00#ibcon#*before return 0, iclass 20, count 2 2006.257.13:26:17.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:17.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:17.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.13:26:17.00#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:17.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:17.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:17.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:17.12#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:26:17.12#ibcon#first serial, iclass 20, count 0 2006.257.13:26:17.12#ibcon#enter sib2, iclass 20, count 0 2006.257.13:26:17.12#ibcon#flushed, iclass 20, count 0 2006.257.13:26:17.12#ibcon#about to write, iclass 20, count 0 2006.257.13:26:17.12#ibcon#wrote, iclass 20, count 0 2006.257.13:26:17.12#ibcon#about to read 3, iclass 20, count 0 2006.257.13:26:17.14#ibcon#read 3, iclass 20, count 0 2006.257.13:26:17.14#ibcon#about to read 4, iclass 20, count 0 2006.257.13:26:17.14#ibcon#read 4, iclass 20, count 0 2006.257.13:26:17.14#ibcon#about to read 5, iclass 20, count 0 2006.257.13:26:17.14#ibcon#read 5, iclass 20, count 0 2006.257.13:26:17.14#ibcon#about to read 6, iclass 20, count 0 2006.257.13:26:17.14#ibcon#read 6, iclass 20, count 0 2006.257.13:26:17.14#ibcon#end of sib2, iclass 20, count 0 2006.257.13:26:17.14#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:26:17.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:26:17.14#ibcon#[25=USB\r\n] 2006.257.13:26:17.14#ibcon#*before write, iclass 20, count 0 2006.257.13:26:17.14#ibcon#enter sib2, iclass 20, count 0 2006.257.13:26:17.14#ibcon#flushed, iclass 20, count 0 2006.257.13:26:17.14#ibcon#about to write, iclass 20, count 0 2006.257.13:26:17.14#ibcon#wrote, iclass 20, count 0 2006.257.13:26:17.14#ibcon#about to read 3, iclass 20, count 0 2006.257.13:26:17.17#ibcon#read 3, iclass 20, count 0 2006.257.13:26:17.17#ibcon#about to read 4, iclass 20, count 0 2006.257.13:26:17.17#ibcon#read 4, iclass 20, count 0 2006.257.13:26:17.17#ibcon#about to read 5, iclass 20, count 0 2006.257.13:26:17.17#ibcon#read 5, iclass 20, count 0 2006.257.13:26:17.17#ibcon#about to read 6, iclass 20, count 0 2006.257.13:26:17.17#ibcon#read 6, iclass 20, count 0 2006.257.13:26:17.17#ibcon#end of sib2, iclass 20, count 0 2006.257.13:26:17.17#ibcon#*after write, iclass 20, count 0 2006.257.13:26:17.17#ibcon#*before return 0, iclass 20, count 0 2006.257.13:26:17.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:17.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:17.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:26:17.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:26:17.17$vck44/valo=7,864.99 2006.257.13:26:17.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.13:26:17.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.13:26:17.17#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:17.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:17.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:17.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:17.17#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:26:17.17#ibcon#first serial, iclass 22, count 0 2006.257.13:26:17.17#ibcon#enter sib2, iclass 22, count 0 2006.257.13:26:17.17#ibcon#flushed, iclass 22, count 0 2006.257.13:26:17.17#ibcon#about to write, iclass 22, count 0 2006.257.13:26:17.17#ibcon#wrote, iclass 22, count 0 2006.257.13:26:17.17#ibcon#about to read 3, iclass 22, count 0 2006.257.13:26:17.19#ibcon#read 3, iclass 22, count 0 2006.257.13:26:17.19#ibcon#about to read 4, iclass 22, count 0 2006.257.13:26:17.19#ibcon#read 4, iclass 22, count 0 2006.257.13:26:17.19#ibcon#about to read 5, iclass 22, count 0 2006.257.13:26:17.19#ibcon#read 5, iclass 22, count 0 2006.257.13:26:17.19#ibcon#about to read 6, iclass 22, count 0 2006.257.13:26:17.19#ibcon#read 6, iclass 22, count 0 2006.257.13:26:17.19#ibcon#end of sib2, iclass 22, count 0 2006.257.13:26:17.19#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:26:17.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:26:17.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:26:17.19#ibcon#*before write, iclass 22, count 0 2006.257.13:26:17.19#ibcon#enter sib2, iclass 22, count 0 2006.257.13:26:17.19#ibcon#flushed, iclass 22, count 0 2006.257.13:26:17.19#ibcon#about to write, iclass 22, count 0 2006.257.13:26:17.19#ibcon#wrote, iclass 22, count 0 2006.257.13:26:17.19#ibcon#about to read 3, iclass 22, count 0 2006.257.13:26:17.23#ibcon#read 3, iclass 22, count 0 2006.257.13:26:17.23#ibcon#about to read 4, iclass 22, count 0 2006.257.13:26:17.23#ibcon#read 4, iclass 22, count 0 2006.257.13:26:17.23#ibcon#about to read 5, iclass 22, count 0 2006.257.13:26:17.23#ibcon#read 5, iclass 22, count 0 2006.257.13:26:17.23#ibcon#about to read 6, iclass 22, count 0 2006.257.13:26:17.23#ibcon#read 6, iclass 22, count 0 2006.257.13:26:17.23#ibcon#end of sib2, iclass 22, count 0 2006.257.13:26:17.23#ibcon#*after write, iclass 22, count 0 2006.257.13:26:17.23#ibcon#*before return 0, iclass 22, count 0 2006.257.13:26:17.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:17.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:17.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:26:17.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:26:17.23$vck44/va=7,4 2006.257.13:26:17.23#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.13:26:17.23#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.13:26:17.23#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:17.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:17.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:17.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:17.29#ibcon#enter wrdev, iclass 24, count 2 2006.257.13:26:17.29#ibcon#first serial, iclass 24, count 2 2006.257.13:26:17.29#ibcon#enter sib2, iclass 24, count 2 2006.257.13:26:17.29#ibcon#flushed, iclass 24, count 2 2006.257.13:26:17.29#ibcon#about to write, iclass 24, count 2 2006.257.13:26:17.29#ibcon#wrote, iclass 24, count 2 2006.257.13:26:17.29#ibcon#about to read 3, iclass 24, count 2 2006.257.13:26:17.31#ibcon#read 3, iclass 24, count 2 2006.257.13:26:17.31#ibcon#about to read 4, iclass 24, count 2 2006.257.13:26:17.31#ibcon#read 4, iclass 24, count 2 2006.257.13:26:17.31#ibcon#about to read 5, iclass 24, count 2 2006.257.13:26:17.31#ibcon#read 5, iclass 24, count 2 2006.257.13:26:17.31#ibcon#about to read 6, iclass 24, count 2 2006.257.13:26:17.31#ibcon#read 6, iclass 24, count 2 2006.257.13:26:17.31#ibcon#end of sib2, iclass 24, count 2 2006.257.13:26:17.31#ibcon#*mode == 0, iclass 24, count 2 2006.257.13:26:17.31#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.13:26:17.31#ibcon#[25=AT07-04\r\n] 2006.257.13:26:17.31#ibcon#*before write, iclass 24, count 2 2006.257.13:26:17.31#ibcon#enter sib2, iclass 24, count 2 2006.257.13:26:17.31#ibcon#flushed, iclass 24, count 2 2006.257.13:26:17.31#ibcon#about to write, iclass 24, count 2 2006.257.13:26:17.31#ibcon#wrote, iclass 24, count 2 2006.257.13:26:17.31#ibcon#about to read 3, iclass 24, count 2 2006.257.13:26:17.34#ibcon#read 3, iclass 24, count 2 2006.257.13:26:17.34#ibcon#about to read 4, iclass 24, count 2 2006.257.13:26:17.34#ibcon#read 4, iclass 24, count 2 2006.257.13:26:17.34#ibcon#about to read 5, iclass 24, count 2 2006.257.13:26:17.34#ibcon#read 5, iclass 24, count 2 2006.257.13:26:17.34#ibcon#about to read 6, iclass 24, count 2 2006.257.13:26:17.34#ibcon#read 6, iclass 24, count 2 2006.257.13:26:17.34#ibcon#end of sib2, iclass 24, count 2 2006.257.13:26:17.34#ibcon#*after write, iclass 24, count 2 2006.257.13:26:17.34#ibcon#*before return 0, iclass 24, count 2 2006.257.13:26:17.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:17.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:17.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.13:26:17.34#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:17.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:17.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:17.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:17.46#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:26:17.46#ibcon#first serial, iclass 24, count 0 2006.257.13:26:17.46#ibcon#enter sib2, iclass 24, count 0 2006.257.13:26:17.46#ibcon#flushed, iclass 24, count 0 2006.257.13:26:17.46#ibcon#about to write, iclass 24, count 0 2006.257.13:26:17.46#ibcon#wrote, iclass 24, count 0 2006.257.13:26:17.46#ibcon#about to read 3, iclass 24, count 0 2006.257.13:26:17.48#ibcon#read 3, iclass 24, count 0 2006.257.13:26:17.48#ibcon#about to read 4, iclass 24, count 0 2006.257.13:26:17.48#ibcon#read 4, iclass 24, count 0 2006.257.13:26:17.48#ibcon#about to read 5, iclass 24, count 0 2006.257.13:26:17.48#ibcon#read 5, iclass 24, count 0 2006.257.13:26:17.48#ibcon#about to read 6, iclass 24, count 0 2006.257.13:26:17.48#ibcon#read 6, iclass 24, count 0 2006.257.13:26:17.48#ibcon#end of sib2, iclass 24, count 0 2006.257.13:26:17.48#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:26:17.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:26:17.48#ibcon#[25=USB\r\n] 2006.257.13:26:17.48#ibcon#*before write, iclass 24, count 0 2006.257.13:26:17.48#ibcon#enter sib2, iclass 24, count 0 2006.257.13:26:17.48#ibcon#flushed, iclass 24, count 0 2006.257.13:26:17.48#ibcon#about to write, iclass 24, count 0 2006.257.13:26:17.48#ibcon#wrote, iclass 24, count 0 2006.257.13:26:17.48#ibcon#about to read 3, iclass 24, count 0 2006.257.13:26:17.51#ibcon#read 3, iclass 24, count 0 2006.257.13:26:17.51#ibcon#about to read 4, iclass 24, count 0 2006.257.13:26:17.51#ibcon#read 4, iclass 24, count 0 2006.257.13:26:17.51#ibcon#about to read 5, iclass 24, count 0 2006.257.13:26:17.51#ibcon#read 5, iclass 24, count 0 2006.257.13:26:17.51#ibcon#about to read 6, iclass 24, count 0 2006.257.13:26:17.51#ibcon#read 6, iclass 24, count 0 2006.257.13:26:17.51#ibcon#end of sib2, iclass 24, count 0 2006.257.13:26:17.51#ibcon#*after write, iclass 24, count 0 2006.257.13:26:17.51#ibcon#*before return 0, iclass 24, count 0 2006.257.13:26:17.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:17.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:17.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:26:17.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:26:17.51$vck44/valo=8,884.99 2006.257.13:26:17.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.13:26:17.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.13:26:17.51#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:17.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:17.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:17.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:17.51#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:26:17.51#ibcon#first serial, iclass 26, count 0 2006.257.13:26:17.51#ibcon#enter sib2, iclass 26, count 0 2006.257.13:26:17.51#ibcon#flushed, iclass 26, count 0 2006.257.13:26:17.51#ibcon#about to write, iclass 26, count 0 2006.257.13:26:17.51#ibcon#wrote, iclass 26, count 0 2006.257.13:26:17.51#ibcon#about to read 3, iclass 26, count 0 2006.257.13:26:17.53#ibcon#read 3, iclass 26, count 0 2006.257.13:26:17.53#ibcon#about to read 4, iclass 26, count 0 2006.257.13:26:17.53#ibcon#read 4, iclass 26, count 0 2006.257.13:26:17.53#ibcon#about to read 5, iclass 26, count 0 2006.257.13:26:17.53#ibcon#read 5, iclass 26, count 0 2006.257.13:26:17.53#ibcon#about to read 6, iclass 26, count 0 2006.257.13:26:17.53#ibcon#read 6, iclass 26, count 0 2006.257.13:26:17.53#ibcon#end of sib2, iclass 26, count 0 2006.257.13:26:17.53#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:26:17.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:26:17.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:26:17.53#ibcon#*before write, iclass 26, count 0 2006.257.13:26:17.53#ibcon#enter sib2, iclass 26, count 0 2006.257.13:26:17.53#ibcon#flushed, iclass 26, count 0 2006.257.13:26:17.53#ibcon#about to write, iclass 26, count 0 2006.257.13:26:17.53#ibcon#wrote, iclass 26, count 0 2006.257.13:26:17.53#ibcon#about to read 3, iclass 26, count 0 2006.257.13:26:17.57#ibcon#read 3, iclass 26, count 0 2006.257.13:26:17.57#ibcon#about to read 4, iclass 26, count 0 2006.257.13:26:17.57#ibcon#read 4, iclass 26, count 0 2006.257.13:26:17.57#ibcon#about to read 5, iclass 26, count 0 2006.257.13:26:17.57#ibcon#read 5, iclass 26, count 0 2006.257.13:26:17.57#ibcon#about to read 6, iclass 26, count 0 2006.257.13:26:17.57#ibcon#read 6, iclass 26, count 0 2006.257.13:26:17.57#ibcon#end of sib2, iclass 26, count 0 2006.257.13:26:17.57#ibcon#*after write, iclass 26, count 0 2006.257.13:26:17.57#ibcon#*before return 0, iclass 26, count 0 2006.257.13:26:17.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:17.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:17.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:26:17.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:26:17.57$vck44/va=8,4 2006.257.13:26:17.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.13:26:17.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.13:26:17.57#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:17.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:17.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:17.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:17.63#ibcon#enter wrdev, iclass 28, count 2 2006.257.13:26:17.63#ibcon#first serial, iclass 28, count 2 2006.257.13:26:17.63#ibcon#enter sib2, iclass 28, count 2 2006.257.13:26:17.63#ibcon#flushed, iclass 28, count 2 2006.257.13:26:17.63#ibcon#about to write, iclass 28, count 2 2006.257.13:26:17.63#ibcon#wrote, iclass 28, count 2 2006.257.13:26:17.63#ibcon#about to read 3, iclass 28, count 2 2006.257.13:26:17.65#ibcon#read 3, iclass 28, count 2 2006.257.13:26:17.65#ibcon#about to read 4, iclass 28, count 2 2006.257.13:26:17.65#ibcon#read 4, iclass 28, count 2 2006.257.13:26:17.65#ibcon#about to read 5, iclass 28, count 2 2006.257.13:26:17.65#ibcon#read 5, iclass 28, count 2 2006.257.13:26:17.65#ibcon#about to read 6, iclass 28, count 2 2006.257.13:26:17.65#ibcon#read 6, iclass 28, count 2 2006.257.13:26:17.65#ibcon#end of sib2, iclass 28, count 2 2006.257.13:26:17.65#ibcon#*mode == 0, iclass 28, count 2 2006.257.13:26:17.65#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.13:26:17.65#ibcon#[25=AT08-04\r\n] 2006.257.13:26:17.65#ibcon#*before write, iclass 28, count 2 2006.257.13:26:17.65#ibcon#enter sib2, iclass 28, count 2 2006.257.13:26:17.65#ibcon#flushed, iclass 28, count 2 2006.257.13:26:17.65#ibcon#about to write, iclass 28, count 2 2006.257.13:26:17.65#ibcon#wrote, iclass 28, count 2 2006.257.13:26:17.65#ibcon#about to read 3, iclass 28, count 2 2006.257.13:26:17.68#ibcon#read 3, iclass 28, count 2 2006.257.13:26:17.68#ibcon#about to read 4, iclass 28, count 2 2006.257.13:26:17.68#ibcon#read 4, iclass 28, count 2 2006.257.13:26:17.68#ibcon#about to read 5, iclass 28, count 2 2006.257.13:26:17.68#ibcon#read 5, iclass 28, count 2 2006.257.13:26:17.68#ibcon#about to read 6, iclass 28, count 2 2006.257.13:26:17.68#ibcon#read 6, iclass 28, count 2 2006.257.13:26:17.68#ibcon#end of sib2, iclass 28, count 2 2006.257.13:26:17.68#ibcon#*after write, iclass 28, count 2 2006.257.13:26:17.68#ibcon#*before return 0, iclass 28, count 2 2006.257.13:26:17.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:17.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:17.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.13:26:17.68#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:17.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:17.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:17.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:17.80#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:26:17.80#ibcon#first serial, iclass 28, count 0 2006.257.13:26:17.80#ibcon#enter sib2, iclass 28, count 0 2006.257.13:26:17.80#ibcon#flushed, iclass 28, count 0 2006.257.13:26:17.80#ibcon#about to write, iclass 28, count 0 2006.257.13:26:17.80#ibcon#wrote, iclass 28, count 0 2006.257.13:26:17.80#ibcon#about to read 3, iclass 28, count 0 2006.257.13:26:17.82#ibcon#read 3, iclass 28, count 0 2006.257.13:26:17.82#ibcon#about to read 4, iclass 28, count 0 2006.257.13:26:17.82#ibcon#read 4, iclass 28, count 0 2006.257.13:26:17.82#ibcon#about to read 5, iclass 28, count 0 2006.257.13:26:17.82#ibcon#read 5, iclass 28, count 0 2006.257.13:26:17.82#ibcon#about to read 6, iclass 28, count 0 2006.257.13:26:17.82#ibcon#read 6, iclass 28, count 0 2006.257.13:26:17.82#ibcon#end of sib2, iclass 28, count 0 2006.257.13:26:17.82#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:26:17.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:26:17.82#ibcon#[25=USB\r\n] 2006.257.13:26:17.82#ibcon#*before write, iclass 28, count 0 2006.257.13:26:17.82#ibcon#enter sib2, iclass 28, count 0 2006.257.13:26:17.82#ibcon#flushed, iclass 28, count 0 2006.257.13:26:17.82#ibcon#about to write, iclass 28, count 0 2006.257.13:26:17.82#ibcon#wrote, iclass 28, count 0 2006.257.13:26:17.82#ibcon#about to read 3, iclass 28, count 0 2006.257.13:26:17.85#ibcon#read 3, iclass 28, count 0 2006.257.13:26:17.85#ibcon#about to read 4, iclass 28, count 0 2006.257.13:26:17.85#ibcon#read 4, iclass 28, count 0 2006.257.13:26:17.85#ibcon#about to read 5, iclass 28, count 0 2006.257.13:26:17.85#ibcon#read 5, iclass 28, count 0 2006.257.13:26:17.85#ibcon#about to read 6, iclass 28, count 0 2006.257.13:26:17.85#ibcon#read 6, iclass 28, count 0 2006.257.13:26:17.85#ibcon#end of sib2, iclass 28, count 0 2006.257.13:26:17.85#ibcon#*after write, iclass 28, count 0 2006.257.13:26:17.85#ibcon#*before return 0, iclass 28, count 0 2006.257.13:26:17.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:17.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:17.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:26:17.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:26:17.85$vck44/vblo=1,629.99 2006.257.13:26:17.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.13:26:17.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.13:26:17.85#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:17.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:17.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:17.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:17.85#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:26:17.85#ibcon#first serial, iclass 30, count 0 2006.257.13:26:17.85#ibcon#enter sib2, iclass 30, count 0 2006.257.13:26:17.85#ibcon#flushed, iclass 30, count 0 2006.257.13:26:17.85#ibcon#about to write, iclass 30, count 0 2006.257.13:26:17.85#ibcon#wrote, iclass 30, count 0 2006.257.13:26:17.85#ibcon#about to read 3, iclass 30, count 0 2006.257.13:26:17.87#ibcon#read 3, iclass 30, count 0 2006.257.13:26:17.87#ibcon#about to read 4, iclass 30, count 0 2006.257.13:26:17.87#ibcon#read 4, iclass 30, count 0 2006.257.13:26:17.87#ibcon#about to read 5, iclass 30, count 0 2006.257.13:26:17.87#ibcon#read 5, iclass 30, count 0 2006.257.13:26:17.87#ibcon#about to read 6, iclass 30, count 0 2006.257.13:26:17.87#ibcon#read 6, iclass 30, count 0 2006.257.13:26:17.87#ibcon#end of sib2, iclass 30, count 0 2006.257.13:26:17.87#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:26:17.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:26:17.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:26:17.87#ibcon#*before write, iclass 30, count 0 2006.257.13:26:17.87#ibcon#enter sib2, iclass 30, count 0 2006.257.13:26:17.87#ibcon#flushed, iclass 30, count 0 2006.257.13:26:17.87#ibcon#about to write, iclass 30, count 0 2006.257.13:26:17.87#ibcon#wrote, iclass 30, count 0 2006.257.13:26:17.87#ibcon#about to read 3, iclass 30, count 0 2006.257.13:26:17.91#ibcon#read 3, iclass 30, count 0 2006.257.13:26:17.91#ibcon#about to read 4, iclass 30, count 0 2006.257.13:26:17.91#ibcon#read 4, iclass 30, count 0 2006.257.13:26:17.91#ibcon#about to read 5, iclass 30, count 0 2006.257.13:26:17.91#ibcon#read 5, iclass 30, count 0 2006.257.13:26:17.91#ibcon#about to read 6, iclass 30, count 0 2006.257.13:26:17.91#ibcon#read 6, iclass 30, count 0 2006.257.13:26:17.91#ibcon#end of sib2, iclass 30, count 0 2006.257.13:26:17.91#ibcon#*after write, iclass 30, count 0 2006.257.13:26:17.91#ibcon#*before return 0, iclass 30, count 0 2006.257.13:26:17.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:17.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:17.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:26:17.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:26:17.91$vck44/vb=1,4 2006.257.13:26:17.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.13:26:17.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.13:26:17.91#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:17.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:26:17.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:26:17.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:26:17.91#ibcon#enter wrdev, iclass 32, count 2 2006.257.13:26:17.91#ibcon#first serial, iclass 32, count 2 2006.257.13:26:17.91#ibcon#enter sib2, iclass 32, count 2 2006.257.13:26:17.91#ibcon#flushed, iclass 32, count 2 2006.257.13:26:17.91#ibcon#about to write, iclass 32, count 2 2006.257.13:26:17.91#ibcon#wrote, iclass 32, count 2 2006.257.13:26:17.91#ibcon#about to read 3, iclass 32, count 2 2006.257.13:26:17.93#ibcon#read 3, iclass 32, count 2 2006.257.13:26:17.93#ibcon#about to read 4, iclass 32, count 2 2006.257.13:26:17.93#ibcon#read 4, iclass 32, count 2 2006.257.13:26:17.93#ibcon#about to read 5, iclass 32, count 2 2006.257.13:26:17.93#ibcon#read 5, iclass 32, count 2 2006.257.13:26:17.93#ibcon#about to read 6, iclass 32, count 2 2006.257.13:26:17.93#ibcon#read 6, iclass 32, count 2 2006.257.13:26:17.93#ibcon#end of sib2, iclass 32, count 2 2006.257.13:26:17.93#ibcon#*mode == 0, iclass 32, count 2 2006.257.13:26:17.93#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.13:26:17.93#ibcon#[27=AT01-04\r\n] 2006.257.13:26:17.93#ibcon#*before write, iclass 32, count 2 2006.257.13:26:17.93#ibcon#enter sib2, iclass 32, count 2 2006.257.13:26:17.93#ibcon#flushed, iclass 32, count 2 2006.257.13:26:17.93#ibcon#about to write, iclass 32, count 2 2006.257.13:26:17.93#ibcon#wrote, iclass 32, count 2 2006.257.13:26:17.93#ibcon#about to read 3, iclass 32, count 2 2006.257.13:26:17.96#ibcon#read 3, iclass 32, count 2 2006.257.13:26:17.96#ibcon#about to read 4, iclass 32, count 2 2006.257.13:26:17.96#ibcon#read 4, iclass 32, count 2 2006.257.13:26:17.96#ibcon#about to read 5, iclass 32, count 2 2006.257.13:26:17.96#ibcon#read 5, iclass 32, count 2 2006.257.13:26:17.96#ibcon#about to read 6, iclass 32, count 2 2006.257.13:26:17.96#ibcon#read 6, iclass 32, count 2 2006.257.13:26:17.96#ibcon#end of sib2, iclass 32, count 2 2006.257.13:26:17.96#ibcon#*after write, iclass 32, count 2 2006.257.13:26:17.96#ibcon#*before return 0, iclass 32, count 2 2006.257.13:26:17.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:26:17.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:26:17.96#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.13:26:17.96#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:17.96#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:26:18.08#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:26:18.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:26:18.08#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:26:18.08#ibcon#first serial, iclass 32, count 0 2006.257.13:26:18.08#ibcon#enter sib2, iclass 32, count 0 2006.257.13:26:18.08#ibcon#flushed, iclass 32, count 0 2006.257.13:26:18.08#ibcon#about to write, iclass 32, count 0 2006.257.13:26:18.08#ibcon#wrote, iclass 32, count 0 2006.257.13:26:18.08#ibcon#about to read 3, iclass 32, count 0 2006.257.13:26:18.10#ibcon#read 3, iclass 32, count 0 2006.257.13:26:18.10#ibcon#about to read 4, iclass 32, count 0 2006.257.13:26:18.10#ibcon#read 4, iclass 32, count 0 2006.257.13:26:18.10#ibcon#about to read 5, iclass 32, count 0 2006.257.13:26:18.10#ibcon#read 5, iclass 32, count 0 2006.257.13:26:18.10#ibcon#about to read 6, iclass 32, count 0 2006.257.13:26:18.10#ibcon#read 6, iclass 32, count 0 2006.257.13:26:18.10#ibcon#end of sib2, iclass 32, count 0 2006.257.13:26:18.10#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:26:18.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:26:18.10#ibcon#[27=USB\r\n] 2006.257.13:26:18.10#ibcon#*before write, iclass 32, count 0 2006.257.13:26:18.10#ibcon#enter sib2, iclass 32, count 0 2006.257.13:26:18.10#ibcon#flushed, iclass 32, count 0 2006.257.13:26:18.10#ibcon#about to write, iclass 32, count 0 2006.257.13:26:18.10#ibcon#wrote, iclass 32, count 0 2006.257.13:26:18.10#ibcon#about to read 3, iclass 32, count 0 2006.257.13:26:18.13#ibcon#read 3, iclass 32, count 0 2006.257.13:26:18.13#ibcon#about to read 4, iclass 32, count 0 2006.257.13:26:18.13#ibcon#read 4, iclass 32, count 0 2006.257.13:26:18.13#ibcon#about to read 5, iclass 32, count 0 2006.257.13:26:18.13#ibcon#read 5, iclass 32, count 0 2006.257.13:26:18.13#ibcon#about to read 6, iclass 32, count 0 2006.257.13:26:18.13#ibcon#read 6, iclass 32, count 0 2006.257.13:26:18.13#ibcon#end of sib2, iclass 32, count 0 2006.257.13:26:18.13#ibcon#*after write, iclass 32, count 0 2006.257.13:26:18.13#ibcon#*before return 0, iclass 32, count 0 2006.257.13:26:18.13#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:26:18.13#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:26:18.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:26:18.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:26:18.13$vck44/vblo=2,634.99 2006.257.13:26:18.13#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.13:26:18.13#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.13:26:18.13#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:18.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:18.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:18.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:18.13#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:26:18.13#ibcon#first serial, iclass 34, count 0 2006.257.13:26:18.13#ibcon#enter sib2, iclass 34, count 0 2006.257.13:26:18.13#ibcon#flushed, iclass 34, count 0 2006.257.13:26:18.13#ibcon#about to write, iclass 34, count 0 2006.257.13:26:18.13#ibcon#wrote, iclass 34, count 0 2006.257.13:26:18.13#ibcon#about to read 3, iclass 34, count 0 2006.257.13:26:18.15#ibcon#read 3, iclass 34, count 0 2006.257.13:26:18.15#ibcon#about to read 4, iclass 34, count 0 2006.257.13:26:18.15#ibcon#read 4, iclass 34, count 0 2006.257.13:26:18.15#ibcon#about to read 5, iclass 34, count 0 2006.257.13:26:18.15#ibcon#read 5, iclass 34, count 0 2006.257.13:26:18.15#ibcon#about to read 6, iclass 34, count 0 2006.257.13:26:18.15#ibcon#read 6, iclass 34, count 0 2006.257.13:26:18.15#ibcon#end of sib2, iclass 34, count 0 2006.257.13:26:18.15#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:26:18.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:26:18.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:26:18.15#ibcon#*before write, iclass 34, count 0 2006.257.13:26:18.15#ibcon#enter sib2, iclass 34, count 0 2006.257.13:26:18.15#ibcon#flushed, iclass 34, count 0 2006.257.13:26:18.15#ibcon#about to write, iclass 34, count 0 2006.257.13:26:18.15#ibcon#wrote, iclass 34, count 0 2006.257.13:26:18.15#ibcon#about to read 3, iclass 34, count 0 2006.257.13:26:18.19#ibcon#read 3, iclass 34, count 0 2006.257.13:26:18.19#ibcon#about to read 4, iclass 34, count 0 2006.257.13:26:18.19#ibcon#read 4, iclass 34, count 0 2006.257.13:26:18.19#ibcon#about to read 5, iclass 34, count 0 2006.257.13:26:18.19#ibcon#read 5, iclass 34, count 0 2006.257.13:26:18.19#ibcon#about to read 6, iclass 34, count 0 2006.257.13:26:18.19#ibcon#read 6, iclass 34, count 0 2006.257.13:26:18.19#ibcon#end of sib2, iclass 34, count 0 2006.257.13:26:18.19#ibcon#*after write, iclass 34, count 0 2006.257.13:26:18.19#ibcon#*before return 0, iclass 34, count 0 2006.257.13:26:18.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:18.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:26:18.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:26:18.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:26:18.19$vck44/vb=2,5 2006.257.13:26:18.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.13:26:18.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.13:26:18.19#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:18.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:18.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:18.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:18.25#ibcon#enter wrdev, iclass 36, count 2 2006.257.13:26:18.25#ibcon#first serial, iclass 36, count 2 2006.257.13:26:18.25#ibcon#enter sib2, iclass 36, count 2 2006.257.13:26:18.25#ibcon#flushed, iclass 36, count 2 2006.257.13:26:18.25#ibcon#about to write, iclass 36, count 2 2006.257.13:26:18.25#ibcon#wrote, iclass 36, count 2 2006.257.13:26:18.25#ibcon#about to read 3, iclass 36, count 2 2006.257.13:26:18.27#ibcon#read 3, iclass 36, count 2 2006.257.13:26:18.27#ibcon#about to read 4, iclass 36, count 2 2006.257.13:26:18.27#ibcon#read 4, iclass 36, count 2 2006.257.13:26:18.27#ibcon#about to read 5, iclass 36, count 2 2006.257.13:26:18.27#ibcon#read 5, iclass 36, count 2 2006.257.13:26:18.27#ibcon#about to read 6, iclass 36, count 2 2006.257.13:26:18.27#ibcon#read 6, iclass 36, count 2 2006.257.13:26:18.27#ibcon#end of sib2, iclass 36, count 2 2006.257.13:26:18.27#ibcon#*mode == 0, iclass 36, count 2 2006.257.13:26:18.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.13:26:18.27#ibcon#[27=AT02-05\r\n] 2006.257.13:26:18.27#ibcon#*before write, iclass 36, count 2 2006.257.13:26:18.27#ibcon#enter sib2, iclass 36, count 2 2006.257.13:26:18.27#ibcon#flushed, iclass 36, count 2 2006.257.13:26:18.27#ibcon#about to write, iclass 36, count 2 2006.257.13:26:18.27#ibcon#wrote, iclass 36, count 2 2006.257.13:26:18.27#ibcon#about to read 3, iclass 36, count 2 2006.257.13:26:18.30#ibcon#read 3, iclass 36, count 2 2006.257.13:26:18.33#ibcon#about to read 4, iclass 36, count 2 2006.257.13:26:18.33#ibcon#read 4, iclass 36, count 2 2006.257.13:26:18.33#ibcon#about to read 5, iclass 36, count 2 2006.257.13:26:18.33#ibcon#read 5, iclass 36, count 2 2006.257.13:26:18.33#ibcon#about to read 6, iclass 36, count 2 2006.257.13:26:18.33#ibcon#read 6, iclass 36, count 2 2006.257.13:26:18.33#ibcon#end of sib2, iclass 36, count 2 2006.257.13:26:18.33#ibcon#*after write, iclass 36, count 2 2006.257.13:26:18.33#ibcon#*before return 0, iclass 36, count 2 2006.257.13:26:18.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:18.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:26:18.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.13:26:18.33#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:18.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:18.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:18.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:18.45#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:26:18.45#ibcon#first serial, iclass 36, count 0 2006.257.13:26:18.45#ibcon#enter sib2, iclass 36, count 0 2006.257.13:26:18.45#ibcon#flushed, iclass 36, count 0 2006.257.13:26:18.45#ibcon#about to write, iclass 36, count 0 2006.257.13:26:18.45#ibcon#wrote, iclass 36, count 0 2006.257.13:26:18.45#ibcon#about to read 3, iclass 36, count 0 2006.257.13:26:18.47#ibcon#read 3, iclass 36, count 0 2006.257.13:26:18.47#ibcon#about to read 4, iclass 36, count 0 2006.257.13:26:18.47#ibcon#read 4, iclass 36, count 0 2006.257.13:26:18.47#ibcon#about to read 5, iclass 36, count 0 2006.257.13:26:18.47#ibcon#read 5, iclass 36, count 0 2006.257.13:26:18.47#ibcon#about to read 6, iclass 36, count 0 2006.257.13:26:18.47#ibcon#read 6, iclass 36, count 0 2006.257.13:26:18.47#ibcon#end of sib2, iclass 36, count 0 2006.257.13:26:18.47#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:26:18.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:26:18.47#ibcon#[27=USB\r\n] 2006.257.13:26:18.47#ibcon#*before write, iclass 36, count 0 2006.257.13:26:18.47#ibcon#enter sib2, iclass 36, count 0 2006.257.13:26:18.47#ibcon#flushed, iclass 36, count 0 2006.257.13:26:18.47#ibcon#about to write, iclass 36, count 0 2006.257.13:26:18.47#ibcon#wrote, iclass 36, count 0 2006.257.13:26:18.47#ibcon#about to read 3, iclass 36, count 0 2006.257.13:26:18.50#ibcon#read 3, iclass 36, count 0 2006.257.13:26:18.50#ibcon#about to read 4, iclass 36, count 0 2006.257.13:26:18.50#ibcon#read 4, iclass 36, count 0 2006.257.13:26:18.50#ibcon#about to read 5, iclass 36, count 0 2006.257.13:26:18.50#ibcon#read 5, iclass 36, count 0 2006.257.13:26:18.50#ibcon#about to read 6, iclass 36, count 0 2006.257.13:26:18.50#ibcon#read 6, iclass 36, count 0 2006.257.13:26:18.50#ibcon#end of sib2, iclass 36, count 0 2006.257.13:26:18.50#ibcon#*after write, iclass 36, count 0 2006.257.13:26:18.50#ibcon#*before return 0, iclass 36, count 0 2006.257.13:26:18.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:18.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:26:18.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:26:18.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:26:18.50$vck44/vblo=3,649.99 2006.257.13:26:18.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.13:26:18.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.13:26:18.50#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:18.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:18.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:18.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:18.50#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:26:18.50#ibcon#first serial, iclass 38, count 0 2006.257.13:26:18.50#ibcon#enter sib2, iclass 38, count 0 2006.257.13:26:18.50#ibcon#flushed, iclass 38, count 0 2006.257.13:26:18.50#ibcon#about to write, iclass 38, count 0 2006.257.13:26:18.50#ibcon#wrote, iclass 38, count 0 2006.257.13:26:18.50#ibcon#about to read 3, iclass 38, count 0 2006.257.13:26:18.52#ibcon#read 3, iclass 38, count 0 2006.257.13:26:18.52#ibcon#about to read 4, iclass 38, count 0 2006.257.13:26:18.52#ibcon#read 4, iclass 38, count 0 2006.257.13:26:18.52#ibcon#about to read 5, iclass 38, count 0 2006.257.13:26:18.52#ibcon#read 5, iclass 38, count 0 2006.257.13:26:18.52#ibcon#about to read 6, iclass 38, count 0 2006.257.13:26:18.52#ibcon#read 6, iclass 38, count 0 2006.257.13:26:18.52#ibcon#end of sib2, iclass 38, count 0 2006.257.13:26:18.52#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:26:18.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:26:18.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:26:18.52#ibcon#*before write, iclass 38, count 0 2006.257.13:26:18.52#ibcon#enter sib2, iclass 38, count 0 2006.257.13:26:18.52#ibcon#flushed, iclass 38, count 0 2006.257.13:26:18.52#ibcon#about to write, iclass 38, count 0 2006.257.13:26:18.52#ibcon#wrote, iclass 38, count 0 2006.257.13:26:18.52#ibcon#about to read 3, iclass 38, count 0 2006.257.13:26:18.56#ibcon#read 3, iclass 38, count 0 2006.257.13:26:18.56#ibcon#about to read 4, iclass 38, count 0 2006.257.13:26:18.56#ibcon#read 4, iclass 38, count 0 2006.257.13:26:18.56#ibcon#about to read 5, iclass 38, count 0 2006.257.13:26:18.56#ibcon#read 5, iclass 38, count 0 2006.257.13:26:18.56#ibcon#about to read 6, iclass 38, count 0 2006.257.13:26:18.56#ibcon#read 6, iclass 38, count 0 2006.257.13:26:18.56#ibcon#end of sib2, iclass 38, count 0 2006.257.13:26:18.56#ibcon#*after write, iclass 38, count 0 2006.257.13:26:18.56#ibcon#*before return 0, iclass 38, count 0 2006.257.13:26:18.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:18.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:26:18.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:26:18.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:26:18.56$vck44/vb=3,4 2006.257.13:26:18.56#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.13:26:18.56#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.13:26:18.56#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:18.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:18.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:18.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:18.62#ibcon#enter wrdev, iclass 40, count 2 2006.257.13:26:18.62#ibcon#first serial, iclass 40, count 2 2006.257.13:26:18.62#ibcon#enter sib2, iclass 40, count 2 2006.257.13:26:18.62#ibcon#flushed, iclass 40, count 2 2006.257.13:26:18.62#ibcon#about to write, iclass 40, count 2 2006.257.13:26:18.62#ibcon#wrote, iclass 40, count 2 2006.257.13:26:18.62#ibcon#about to read 3, iclass 40, count 2 2006.257.13:26:18.64#ibcon#read 3, iclass 40, count 2 2006.257.13:26:18.64#ibcon#about to read 4, iclass 40, count 2 2006.257.13:26:18.64#ibcon#read 4, iclass 40, count 2 2006.257.13:26:18.64#ibcon#about to read 5, iclass 40, count 2 2006.257.13:26:18.64#ibcon#read 5, iclass 40, count 2 2006.257.13:26:18.64#ibcon#about to read 6, iclass 40, count 2 2006.257.13:26:18.64#ibcon#read 6, iclass 40, count 2 2006.257.13:26:18.64#ibcon#end of sib2, iclass 40, count 2 2006.257.13:26:18.64#ibcon#*mode == 0, iclass 40, count 2 2006.257.13:26:18.64#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.13:26:18.64#ibcon#[27=AT03-04\r\n] 2006.257.13:26:18.64#ibcon#*before write, iclass 40, count 2 2006.257.13:26:18.64#ibcon#enter sib2, iclass 40, count 2 2006.257.13:26:18.64#ibcon#flushed, iclass 40, count 2 2006.257.13:26:18.64#ibcon#about to write, iclass 40, count 2 2006.257.13:26:18.64#ibcon#wrote, iclass 40, count 2 2006.257.13:26:18.64#ibcon#about to read 3, iclass 40, count 2 2006.257.13:26:18.67#ibcon#read 3, iclass 40, count 2 2006.257.13:26:18.67#ibcon#about to read 4, iclass 40, count 2 2006.257.13:26:18.67#ibcon#read 4, iclass 40, count 2 2006.257.13:26:18.67#ibcon#about to read 5, iclass 40, count 2 2006.257.13:26:18.67#ibcon#read 5, iclass 40, count 2 2006.257.13:26:18.67#ibcon#about to read 6, iclass 40, count 2 2006.257.13:26:18.67#ibcon#read 6, iclass 40, count 2 2006.257.13:26:18.67#ibcon#end of sib2, iclass 40, count 2 2006.257.13:26:18.67#ibcon#*after write, iclass 40, count 2 2006.257.13:26:18.67#ibcon#*before return 0, iclass 40, count 2 2006.257.13:26:18.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:18.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:26:18.67#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.13:26:18.67#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:18.67#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:18.79#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:18.79#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:18.79#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:26:18.79#ibcon#first serial, iclass 40, count 0 2006.257.13:26:18.79#ibcon#enter sib2, iclass 40, count 0 2006.257.13:26:18.79#ibcon#flushed, iclass 40, count 0 2006.257.13:26:18.79#ibcon#about to write, iclass 40, count 0 2006.257.13:26:18.79#ibcon#wrote, iclass 40, count 0 2006.257.13:26:18.79#ibcon#about to read 3, iclass 40, count 0 2006.257.13:26:18.81#ibcon#read 3, iclass 40, count 0 2006.257.13:26:18.81#ibcon#about to read 4, iclass 40, count 0 2006.257.13:26:18.81#ibcon#read 4, iclass 40, count 0 2006.257.13:26:18.81#ibcon#about to read 5, iclass 40, count 0 2006.257.13:26:18.81#ibcon#read 5, iclass 40, count 0 2006.257.13:26:18.81#ibcon#about to read 6, iclass 40, count 0 2006.257.13:26:18.81#ibcon#read 6, iclass 40, count 0 2006.257.13:26:18.81#ibcon#end of sib2, iclass 40, count 0 2006.257.13:26:18.81#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:26:18.81#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:26:18.81#ibcon#[27=USB\r\n] 2006.257.13:26:18.81#ibcon#*before write, iclass 40, count 0 2006.257.13:26:18.81#ibcon#enter sib2, iclass 40, count 0 2006.257.13:26:18.81#ibcon#flushed, iclass 40, count 0 2006.257.13:26:18.81#ibcon#about to write, iclass 40, count 0 2006.257.13:26:18.81#ibcon#wrote, iclass 40, count 0 2006.257.13:26:18.81#ibcon#about to read 3, iclass 40, count 0 2006.257.13:26:18.84#ibcon#read 3, iclass 40, count 0 2006.257.13:26:18.84#ibcon#about to read 4, iclass 40, count 0 2006.257.13:26:18.84#ibcon#read 4, iclass 40, count 0 2006.257.13:26:18.84#ibcon#about to read 5, iclass 40, count 0 2006.257.13:26:18.84#ibcon#read 5, iclass 40, count 0 2006.257.13:26:18.84#ibcon#about to read 6, iclass 40, count 0 2006.257.13:26:18.84#ibcon#read 6, iclass 40, count 0 2006.257.13:26:18.84#ibcon#end of sib2, iclass 40, count 0 2006.257.13:26:18.84#ibcon#*after write, iclass 40, count 0 2006.257.13:26:18.84#ibcon#*before return 0, iclass 40, count 0 2006.257.13:26:18.84#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:18.84#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:26:18.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:26:18.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:26:18.84$vck44/vblo=4,679.99 2006.257.13:26:18.84#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.13:26:18.84#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.13:26:18.84#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:18.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:18.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:18.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:18.84#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:26:18.84#ibcon#first serial, iclass 4, count 0 2006.257.13:26:18.84#ibcon#enter sib2, iclass 4, count 0 2006.257.13:26:18.84#ibcon#flushed, iclass 4, count 0 2006.257.13:26:18.84#ibcon#about to write, iclass 4, count 0 2006.257.13:26:18.84#ibcon#wrote, iclass 4, count 0 2006.257.13:26:18.84#ibcon#about to read 3, iclass 4, count 0 2006.257.13:26:18.86#ibcon#read 3, iclass 4, count 0 2006.257.13:26:18.86#ibcon#about to read 4, iclass 4, count 0 2006.257.13:26:18.86#ibcon#read 4, iclass 4, count 0 2006.257.13:26:18.86#ibcon#about to read 5, iclass 4, count 0 2006.257.13:26:18.86#ibcon#read 5, iclass 4, count 0 2006.257.13:26:18.86#ibcon#about to read 6, iclass 4, count 0 2006.257.13:26:18.86#ibcon#read 6, iclass 4, count 0 2006.257.13:26:18.86#ibcon#end of sib2, iclass 4, count 0 2006.257.13:26:18.86#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:26:18.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:26:18.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:26:18.86#ibcon#*before write, iclass 4, count 0 2006.257.13:26:18.86#ibcon#enter sib2, iclass 4, count 0 2006.257.13:26:18.86#ibcon#flushed, iclass 4, count 0 2006.257.13:26:18.86#ibcon#about to write, iclass 4, count 0 2006.257.13:26:18.86#ibcon#wrote, iclass 4, count 0 2006.257.13:26:18.86#ibcon#about to read 3, iclass 4, count 0 2006.257.13:26:18.90#ibcon#read 3, iclass 4, count 0 2006.257.13:26:18.90#ibcon#about to read 4, iclass 4, count 0 2006.257.13:26:18.90#ibcon#read 4, iclass 4, count 0 2006.257.13:26:18.90#ibcon#about to read 5, iclass 4, count 0 2006.257.13:26:18.90#ibcon#read 5, iclass 4, count 0 2006.257.13:26:18.90#ibcon#about to read 6, iclass 4, count 0 2006.257.13:26:18.90#ibcon#read 6, iclass 4, count 0 2006.257.13:26:18.90#ibcon#end of sib2, iclass 4, count 0 2006.257.13:26:18.90#ibcon#*after write, iclass 4, count 0 2006.257.13:26:18.90#ibcon#*before return 0, iclass 4, count 0 2006.257.13:26:18.90#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:18.90#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:26:18.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:26:18.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:26:18.90$vck44/vb=4,5 2006.257.13:26:18.90#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.13:26:18.90#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.13:26:18.90#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:18.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:18.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:18.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:18.96#ibcon#enter wrdev, iclass 6, count 2 2006.257.13:26:18.96#ibcon#first serial, iclass 6, count 2 2006.257.13:26:18.96#ibcon#enter sib2, iclass 6, count 2 2006.257.13:26:18.96#ibcon#flushed, iclass 6, count 2 2006.257.13:26:18.96#ibcon#about to write, iclass 6, count 2 2006.257.13:26:18.96#ibcon#wrote, iclass 6, count 2 2006.257.13:26:18.96#ibcon#about to read 3, iclass 6, count 2 2006.257.13:26:18.98#ibcon#read 3, iclass 6, count 2 2006.257.13:26:18.98#ibcon#about to read 4, iclass 6, count 2 2006.257.13:26:18.98#ibcon#read 4, iclass 6, count 2 2006.257.13:26:18.98#ibcon#about to read 5, iclass 6, count 2 2006.257.13:26:18.98#ibcon#read 5, iclass 6, count 2 2006.257.13:26:18.98#ibcon#about to read 6, iclass 6, count 2 2006.257.13:26:18.98#ibcon#read 6, iclass 6, count 2 2006.257.13:26:18.98#ibcon#end of sib2, iclass 6, count 2 2006.257.13:26:18.98#ibcon#*mode == 0, iclass 6, count 2 2006.257.13:26:18.98#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.13:26:18.98#ibcon#[27=AT04-05\r\n] 2006.257.13:26:18.98#ibcon#*before write, iclass 6, count 2 2006.257.13:26:18.98#ibcon#enter sib2, iclass 6, count 2 2006.257.13:26:18.98#ibcon#flushed, iclass 6, count 2 2006.257.13:26:18.98#ibcon#about to write, iclass 6, count 2 2006.257.13:26:18.98#ibcon#wrote, iclass 6, count 2 2006.257.13:26:18.98#ibcon#about to read 3, iclass 6, count 2 2006.257.13:26:19.01#ibcon#read 3, iclass 6, count 2 2006.257.13:26:19.01#ibcon#about to read 4, iclass 6, count 2 2006.257.13:26:19.01#ibcon#read 4, iclass 6, count 2 2006.257.13:26:19.01#ibcon#about to read 5, iclass 6, count 2 2006.257.13:26:19.01#ibcon#read 5, iclass 6, count 2 2006.257.13:26:19.01#ibcon#about to read 6, iclass 6, count 2 2006.257.13:26:19.01#ibcon#read 6, iclass 6, count 2 2006.257.13:26:19.01#ibcon#end of sib2, iclass 6, count 2 2006.257.13:26:19.01#ibcon#*after write, iclass 6, count 2 2006.257.13:26:19.01#ibcon#*before return 0, iclass 6, count 2 2006.257.13:26:19.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:19.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:26:19.01#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.13:26:19.01#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:19.01#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:19.13#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:19.13#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:19.13#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:26:19.13#ibcon#first serial, iclass 6, count 0 2006.257.13:26:19.13#ibcon#enter sib2, iclass 6, count 0 2006.257.13:26:19.13#ibcon#flushed, iclass 6, count 0 2006.257.13:26:19.13#ibcon#about to write, iclass 6, count 0 2006.257.13:26:19.13#ibcon#wrote, iclass 6, count 0 2006.257.13:26:19.13#ibcon#about to read 3, iclass 6, count 0 2006.257.13:26:19.15#ibcon#read 3, iclass 6, count 0 2006.257.13:26:19.15#ibcon#about to read 4, iclass 6, count 0 2006.257.13:26:19.15#ibcon#read 4, iclass 6, count 0 2006.257.13:26:19.15#ibcon#about to read 5, iclass 6, count 0 2006.257.13:26:19.15#ibcon#read 5, iclass 6, count 0 2006.257.13:26:19.15#ibcon#about to read 6, iclass 6, count 0 2006.257.13:26:19.15#ibcon#read 6, iclass 6, count 0 2006.257.13:26:19.15#ibcon#end of sib2, iclass 6, count 0 2006.257.13:26:19.15#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:26:19.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:26:19.15#ibcon#[27=USB\r\n] 2006.257.13:26:19.15#ibcon#*before write, iclass 6, count 0 2006.257.13:26:19.15#ibcon#enter sib2, iclass 6, count 0 2006.257.13:26:19.15#ibcon#flushed, iclass 6, count 0 2006.257.13:26:19.15#ibcon#about to write, iclass 6, count 0 2006.257.13:26:19.15#ibcon#wrote, iclass 6, count 0 2006.257.13:26:19.15#ibcon#about to read 3, iclass 6, count 0 2006.257.13:26:19.18#ibcon#read 3, iclass 6, count 0 2006.257.13:26:19.18#ibcon#about to read 4, iclass 6, count 0 2006.257.13:26:19.18#ibcon#read 4, iclass 6, count 0 2006.257.13:26:19.18#ibcon#about to read 5, iclass 6, count 0 2006.257.13:26:19.18#ibcon#read 5, iclass 6, count 0 2006.257.13:26:19.18#ibcon#about to read 6, iclass 6, count 0 2006.257.13:26:19.18#ibcon#read 6, iclass 6, count 0 2006.257.13:26:19.18#ibcon#end of sib2, iclass 6, count 0 2006.257.13:26:19.18#ibcon#*after write, iclass 6, count 0 2006.257.13:26:19.18#ibcon#*before return 0, iclass 6, count 0 2006.257.13:26:19.18#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:19.18#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:26:19.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:26:19.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:26:19.18$vck44/vblo=5,709.99 2006.257.13:26:19.18#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.13:26:19.18#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.13:26:19.18#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:19.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:19.18#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:19.18#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:19.18#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:26:19.18#ibcon#first serial, iclass 10, count 0 2006.257.13:26:19.18#ibcon#enter sib2, iclass 10, count 0 2006.257.13:26:19.18#ibcon#flushed, iclass 10, count 0 2006.257.13:26:19.18#ibcon#about to write, iclass 10, count 0 2006.257.13:26:19.18#ibcon#wrote, iclass 10, count 0 2006.257.13:26:19.18#ibcon#about to read 3, iclass 10, count 0 2006.257.13:26:19.20#ibcon#read 3, iclass 10, count 0 2006.257.13:26:19.20#ibcon#about to read 4, iclass 10, count 0 2006.257.13:26:19.20#ibcon#read 4, iclass 10, count 0 2006.257.13:26:19.20#ibcon#about to read 5, iclass 10, count 0 2006.257.13:26:19.20#ibcon#read 5, iclass 10, count 0 2006.257.13:26:19.20#ibcon#about to read 6, iclass 10, count 0 2006.257.13:26:19.20#ibcon#read 6, iclass 10, count 0 2006.257.13:26:19.20#ibcon#end of sib2, iclass 10, count 0 2006.257.13:26:19.20#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:26:19.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:26:19.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:26:19.20#ibcon#*before write, iclass 10, count 0 2006.257.13:26:19.20#ibcon#enter sib2, iclass 10, count 0 2006.257.13:26:19.20#ibcon#flushed, iclass 10, count 0 2006.257.13:26:19.20#ibcon#about to write, iclass 10, count 0 2006.257.13:26:19.20#ibcon#wrote, iclass 10, count 0 2006.257.13:26:19.20#ibcon#about to read 3, iclass 10, count 0 2006.257.13:26:19.24#ibcon#read 3, iclass 10, count 0 2006.257.13:26:19.24#ibcon#about to read 4, iclass 10, count 0 2006.257.13:26:19.24#ibcon#read 4, iclass 10, count 0 2006.257.13:26:19.24#ibcon#about to read 5, iclass 10, count 0 2006.257.13:26:19.24#ibcon#read 5, iclass 10, count 0 2006.257.13:26:19.24#ibcon#about to read 6, iclass 10, count 0 2006.257.13:26:19.24#ibcon#read 6, iclass 10, count 0 2006.257.13:26:19.24#ibcon#end of sib2, iclass 10, count 0 2006.257.13:26:19.24#ibcon#*after write, iclass 10, count 0 2006.257.13:26:19.24#ibcon#*before return 0, iclass 10, count 0 2006.257.13:26:19.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:19.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:26:19.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:26:19.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:26:19.24$vck44/vb=5,4 2006.257.13:26:19.24#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.13:26:19.24#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.13:26:19.24#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:19.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:19.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:19.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:19.30#ibcon#enter wrdev, iclass 12, count 2 2006.257.13:26:19.30#ibcon#first serial, iclass 12, count 2 2006.257.13:26:19.30#ibcon#enter sib2, iclass 12, count 2 2006.257.13:26:19.30#ibcon#flushed, iclass 12, count 2 2006.257.13:26:19.30#ibcon#about to write, iclass 12, count 2 2006.257.13:26:19.30#ibcon#wrote, iclass 12, count 2 2006.257.13:26:19.30#ibcon#about to read 3, iclass 12, count 2 2006.257.13:26:19.32#ibcon#read 3, iclass 12, count 2 2006.257.13:26:19.32#ibcon#about to read 4, iclass 12, count 2 2006.257.13:26:19.32#ibcon#read 4, iclass 12, count 2 2006.257.13:26:19.32#ibcon#about to read 5, iclass 12, count 2 2006.257.13:26:19.32#ibcon#read 5, iclass 12, count 2 2006.257.13:26:19.32#ibcon#about to read 6, iclass 12, count 2 2006.257.13:26:19.32#ibcon#read 6, iclass 12, count 2 2006.257.13:26:19.32#ibcon#end of sib2, iclass 12, count 2 2006.257.13:26:19.32#ibcon#*mode == 0, iclass 12, count 2 2006.257.13:26:19.32#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.13:26:19.32#ibcon#[27=AT05-04\r\n] 2006.257.13:26:19.32#ibcon#*before write, iclass 12, count 2 2006.257.13:26:19.32#ibcon#enter sib2, iclass 12, count 2 2006.257.13:26:19.32#ibcon#flushed, iclass 12, count 2 2006.257.13:26:19.32#ibcon#about to write, iclass 12, count 2 2006.257.13:26:19.32#ibcon#wrote, iclass 12, count 2 2006.257.13:26:19.32#ibcon#about to read 3, iclass 12, count 2 2006.257.13:26:19.35#ibcon#read 3, iclass 12, count 2 2006.257.13:26:19.35#ibcon#about to read 4, iclass 12, count 2 2006.257.13:26:19.35#ibcon#read 4, iclass 12, count 2 2006.257.13:26:19.35#ibcon#about to read 5, iclass 12, count 2 2006.257.13:26:19.35#ibcon#read 5, iclass 12, count 2 2006.257.13:26:19.35#ibcon#about to read 6, iclass 12, count 2 2006.257.13:26:19.35#ibcon#read 6, iclass 12, count 2 2006.257.13:26:19.35#ibcon#end of sib2, iclass 12, count 2 2006.257.13:26:19.35#ibcon#*after write, iclass 12, count 2 2006.257.13:26:19.35#ibcon#*before return 0, iclass 12, count 2 2006.257.13:26:19.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:19.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:26:19.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.13:26:19.35#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:19.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:19.36#abcon#<5=/14 1.2 2.7 17.56 971013.9\r\n> 2006.257.13:26:19.38#abcon#{5=INTERFACE CLEAR} 2006.257.13:26:19.44#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:26:19.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:19.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:19.47#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:26:19.47#ibcon#first serial, iclass 12, count 0 2006.257.13:26:19.47#ibcon#enter sib2, iclass 12, count 0 2006.257.13:26:19.47#ibcon#flushed, iclass 12, count 0 2006.257.13:26:19.47#ibcon#about to write, iclass 12, count 0 2006.257.13:26:19.47#ibcon#wrote, iclass 12, count 0 2006.257.13:26:19.47#ibcon#about to read 3, iclass 12, count 0 2006.257.13:26:19.49#ibcon#read 3, iclass 12, count 0 2006.257.13:26:19.49#ibcon#about to read 4, iclass 12, count 0 2006.257.13:26:19.49#ibcon#read 4, iclass 12, count 0 2006.257.13:26:19.49#ibcon#about to read 5, iclass 12, count 0 2006.257.13:26:19.49#ibcon#read 5, iclass 12, count 0 2006.257.13:26:19.49#ibcon#about to read 6, iclass 12, count 0 2006.257.13:26:19.49#ibcon#read 6, iclass 12, count 0 2006.257.13:26:19.49#ibcon#end of sib2, iclass 12, count 0 2006.257.13:26:19.49#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:26:19.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:26:19.49#ibcon#[27=USB\r\n] 2006.257.13:26:19.49#ibcon#*before write, iclass 12, count 0 2006.257.13:26:19.49#ibcon#enter sib2, iclass 12, count 0 2006.257.13:26:19.49#ibcon#flushed, iclass 12, count 0 2006.257.13:26:19.49#ibcon#about to write, iclass 12, count 0 2006.257.13:26:19.49#ibcon#wrote, iclass 12, count 0 2006.257.13:26:19.49#ibcon#about to read 3, iclass 12, count 0 2006.257.13:26:19.52#ibcon#read 3, iclass 12, count 0 2006.257.13:26:19.52#ibcon#about to read 4, iclass 12, count 0 2006.257.13:26:19.52#ibcon#read 4, iclass 12, count 0 2006.257.13:26:19.52#ibcon#about to read 5, iclass 12, count 0 2006.257.13:26:19.52#ibcon#read 5, iclass 12, count 0 2006.257.13:26:19.52#ibcon#about to read 6, iclass 12, count 0 2006.257.13:26:19.52#ibcon#read 6, iclass 12, count 0 2006.257.13:26:19.52#ibcon#end of sib2, iclass 12, count 0 2006.257.13:26:19.52#ibcon#*after write, iclass 12, count 0 2006.257.13:26:19.52#ibcon#*before return 0, iclass 12, count 0 2006.257.13:26:19.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:19.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:26:19.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:26:19.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:26:19.52$vck44/vblo=6,719.99 2006.257.13:26:19.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.13:26:19.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.13:26:19.52#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:19.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:19.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:19.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:19.52#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:26:19.52#ibcon#first serial, iclass 18, count 0 2006.257.13:26:19.52#ibcon#enter sib2, iclass 18, count 0 2006.257.13:26:19.52#ibcon#flushed, iclass 18, count 0 2006.257.13:26:19.52#ibcon#about to write, iclass 18, count 0 2006.257.13:26:19.52#ibcon#wrote, iclass 18, count 0 2006.257.13:26:19.52#ibcon#about to read 3, iclass 18, count 0 2006.257.13:26:19.54#ibcon#read 3, iclass 18, count 0 2006.257.13:26:19.54#ibcon#about to read 4, iclass 18, count 0 2006.257.13:26:19.54#ibcon#read 4, iclass 18, count 0 2006.257.13:26:19.54#ibcon#about to read 5, iclass 18, count 0 2006.257.13:26:19.54#ibcon#read 5, iclass 18, count 0 2006.257.13:26:19.54#ibcon#about to read 6, iclass 18, count 0 2006.257.13:26:19.54#ibcon#read 6, iclass 18, count 0 2006.257.13:26:19.54#ibcon#end of sib2, iclass 18, count 0 2006.257.13:26:19.54#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:26:19.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:26:19.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:26:19.54#ibcon#*before write, iclass 18, count 0 2006.257.13:26:19.54#ibcon#enter sib2, iclass 18, count 0 2006.257.13:26:19.54#ibcon#flushed, iclass 18, count 0 2006.257.13:26:19.54#ibcon#about to write, iclass 18, count 0 2006.257.13:26:19.54#ibcon#wrote, iclass 18, count 0 2006.257.13:26:19.54#ibcon#about to read 3, iclass 18, count 0 2006.257.13:26:19.58#ibcon#read 3, iclass 18, count 0 2006.257.13:26:19.58#ibcon#about to read 4, iclass 18, count 0 2006.257.13:26:19.58#ibcon#read 4, iclass 18, count 0 2006.257.13:26:19.58#ibcon#about to read 5, iclass 18, count 0 2006.257.13:26:19.58#ibcon#read 5, iclass 18, count 0 2006.257.13:26:19.58#ibcon#about to read 6, iclass 18, count 0 2006.257.13:26:19.58#ibcon#read 6, iclass 18, count 0 2006.257.13:26:19.58#ibcon#end of sib2, iclass 18, count 0 2006.257.13:26:19.58#ibcon#*after write, iclass 18, count 0 2006.257.13:26:19.58#ibcon#*before return 0, iclass 18, count 0 2006.257.13:26:19.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:19.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:26:19.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:26:19.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:26:19.58$vck44/vb=6,4 2006.257.13:26:19.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.13:26:19.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.13:26:19.58#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:19.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:19.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:19.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:19.64#ibcon#enter wrdev, iclass 20, count 2 2006.257.13:26:19.64#ibcon#first serial, iclass 20, count 2 2006.257.13:26:19.64#ibcon#enter sib2, iclass 20, count 2 2006.257.13:26:19.64#ibcon#flushed, iclass 20, count 2 2006.257.13:26:19.64#ibcon#about to write, iclass 20, count 2 2006.257.13:26:19.64#ibcon#wrote, iclass 20, count 2 2006.257.13:26:19.64#ibcon#about to read 3, iclass 20, count 2 2006.257.13:26:19.66#ibcon#read 3, iclass 20, count 2 2006.257.13:26:19.66#ibcon#about to read 4, iclass 20, count 2 2006.257.13:26:19.66#ibcon#read 4, iclass 20, count 2 2006.257.13:26:19.66#ibcon#about to read 5, iclass 20, count 2 2006.257.13:26:19.66#ibcon#read 5, iclass 20, count 2 2006.257.13:26:19.66#ibcon#about to read 6, iclass 20, count 2 2006.257.13:26:19.66#ibcon#read 6, iclass 20, count 2 2006.257.13:26:19.66#ibcon#end of sib2, iclass 20, count 2 2006.257.13:26:19.66#ibcon#*mode == 0, iclass 20, count 2 2006.257.13:26:19.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.13:26:19.66#ibcon#[27=AT06-04\r\n] 2006.257.13:26:19.66#ibcon#*before write, iclass 20, count 2 2006.257.13:26:19.66#ibcon#enter sib2, iclass 20, count 2 2006.257.13:26:19.66#ibcon#flushed, iclass 20, count 2 2006.257.13:26:19.66#ibcon#about to write, iclass 20, count 2 2006.257.13:26:19.66#ibcon#wrote, iclass 20, count 2 2006.257.13:26:19.66#ibcon#about to read 3, iclass 20, count 2 2006.257.13:26:19.69#ibcon#read 3, iclass 20, count 2 2006.257.13:26:19.69#ibcon#about to read 4, iclass 20, count 2 2006.257.13:26:19.69#ibcon#read 4, iclass 20, count 2 2006.257.13:26:19.69#ibcon#about to read 5, iclass 20, count 2 2006.257.13:26:19.69#ibcon#read 5, iclass 20, count 2 2006.257.13:26:19.69#ibcon#about to read 6, iclass 20, count 2 2006.257.13:26:19.69#ibcon#read 6, iclass 20, count 2 2006.257.13:26:19.69#ibcon#end of sib2, iclass 20, count 2 2006.257.13:26:19.69#ibcon#*after write, iclass 20, count 2 2006.257.13:26:19.69#ibcon#*before return 0, iclass 20, count 2 2006.257.13:26:19.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:19.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:26:19.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.13:26:19.69#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:19.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:19.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:19.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:19.81#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:26:19.81#ibcon#first serial, iclass 20, count 0 2006.257.13:26:19.81#ibcon#enter sib2, iclass 20, count 0 2006.257.13:26:19.81#ibcon#flushed, iclass 20, count 0 2006.257.13:26:19.81#ibcon#about to write, iclass 20, count 0 2006.257.13:26:19.81#ibcon#wrote, iclass 20, count 0 2006.257.13:26:19.81#ibcon#about to read 3, iclass 20, count 0 2006.257.13:26:19.83#ibcon#read 3, iclass 20, count 0 2006.257.13:26:19.83#ibcon#about to read 4, iclass 20, count 0 2006.257.13:26:19.83#ibcon#read 4, iclass 20, count 0 2006.257.13:26:19.83#ibcon#about to read 5, iclass 20, count 0 2006.257.13:26:19.83#ibcon#read 5, iclass 20, count 0 2006.257.13:26:19.83#ibcon#about to read 6, iclass 20, count 0 2006.257.13:26:19.83#ibcon#read 6, iclass 20, count 0 2006.257.13:26:19.83#ibcon#end of sib2, iclass 20, count 0 2006.257.13:26:19.83#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:26:19.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:26:19.83#ibcon#[27=USB\r\n] 2006.257.13:26:19.83#ibcon#*before write, iclass 20, count 0 2006.257.13:26:19.83#ibcon#enter sib2, iclass 20, count 0 2006.257.13:26:19.83#ibcon#flushed, iclass 20, count 0 2006.257.13:26:19.83#ibcon#about to write, iclass 20, count 0 2006.257.13:26:19.83#ibcon#wrote, iclass 20, count 0 2006.257.13:26:19.83#ibcon#about to read 3, iclass 20, count 0 2006.257.13:26:19.86#ibcon#read 3, iclass 20, count 0 2006.257.13:26:19.86#ibcon#about to read 4, iclass 20, count 0 2006.257.13:26:19.86#ibcon#read 4, iclass 20, count 0 2006.257.13:26:19.86#ibcon#about to read 5, iclass 20, count 0 2006.257.13:26:19.86#ibcon#read 5, iclass 20, count 0 2006.257.13:26:19.86#ibcon#about to read 6, iclass 20, count 0 2006.257.13:26:19.86#ibcon#read 6, iclass 20, count 0 2006.257.13:26:19.86#ibcon#end of sib2, iclass 20, count 0 2006.257.13:26:19.86#ibcon#*after write, iclass 20, count 0 2006.257.13:26:19.86#ibcon#*before return 0, iclass 20, count 0 2006.257.13:26:19.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:19.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:26:19.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:26:19.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:26:19.86$vck44/vblo=7,734.99 2006.257.13:26:19.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.13:26:19.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.13:26:19.86#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:19.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:19.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:19.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:19.86#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:26:19.86#ibcon#first serial, iclass 22, count 0 2006.257.13:26:19.86#ibcon#enter sib2, iclass 22, count 0 2006.257.13:26:19.86#ibcon#flushed, iclass 22, count 0 2006.257.13:26:19.86#ibcon#about to write, iclass 22, count 0 2006.257.13:26:19.86#ibcon#wrote, iclass 22, count 0 2006.257.13:26:19.86#ibcon#about to read 3, iclass 22, count 0 2006.257.13:26:19.88#ibcon#read 3, iclass 22, count 0 2006.257.13:26:19.88#ibcon#about to read 4, iclass 22, count 0 2006.257.13:26:19.88#ibcon#read 4, iclass 22, count 0 2006.257.13:26:19.88#ibcon#about to read 5, iclass 22, count 0 2006.257.13:26:19.88#ibcon#read 5, iclass 22, count 0 2006.257.13:26:19.88#ibcon#about to read 6, iclass 22, count 0 2006.257.13:26:19.88#ibcon#read 6, iclass 22, count 0 2006.257.13:26:19.88#ibcon#end of sib2, iclass 22, count 0 2006.257.13:26:19.88#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:26:19.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:26:19.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:26:19.88#ibcon#*before write, iclass 22, count 0 2006.257.13:26:19.88#ibcon#enter sib2, iclass 22, count 0 2006.257.13:26:19.88#ibcon#flushed, iclass 22, count 0 2006.257.13:26:19.88#ibcon#about to write, iclass 22, count 0 2006.257.13:26:19.88#ibcon#wrote, iclass 22, count 0 2006.257.13:26:19.88#ibcon#about to read 3, iclass 22, count 0 2006.257.13:26:19.92#ibcon#read 3, iclass 22, count 0 2006.257.13:26:19.92#ibcon#about to read 4, iclass 22, count 0 2006.257.13:26:19.92#ibcon#read 4, iclass 22, count 0 2006.257.13:26:19.92#ibcon#about to read 5, iclass 22, count 0 2006.257.13:26:19.92#ibcon#read 5, iclass 22, count 0 2006.257.13:26:19.92#ibcon#about to read 6, iclass 22, count 0 2006.257.13:26:19.92#ibcon#read 6, iclass 22, count 0 2006.257.13:26:19.92#ibcon#end of sib2, iclass 22, count 0 2006.257.13:26:19.92#ibcon#*after write, iclass 22, count 0 2006.257.13:26:19.92#ibcon#*before return 0, iclass 22, count 0 2006.257.13:26:19.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:19.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:26:19.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:26:19.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:26:19.92$vck44/vb=7,4 2006.257.13:26:19.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.13:26:19.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.13:26:19.92#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:19.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:19.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:19.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:19.98#ibcon#enter wrdev, iclass 24, count 2 2006.257.13:26:19.98#ibcon#first serial, iclass 24, count 2 2006.257.13:26:19.98#ibcon#enter sib2, iclass 24, count 2 2006.257.13:26:19.98#ibcon#flushed, iclass 24, count 2 2006.257.13:26:19.98#ibcon#about to write, iclass 24, count 2 2006.257.13:26:19.98#ibcon#wrote, iclass 24, count 2 2006.257.13:26:19.98#ibcon#about to read 3, iclass 24, count 2 2006.257.13:26:20.00#ibcon#read 3, iclass 24, count 2 2006.257.13:26:20.00#ibcon#about to read 4, iclass 24, count 2 2006.257.13:26:20.00#ibcon#read 4, iclass 24, count 2 2006.257.13:26:20.00#ibcon#about to read 5, iclass 24, count 2 2006.257.13:26:20.00#ibcon#read 5, iclass 24, count 2 2006.257.13:26:20.00#ibcon#about to read 6, iclass 24, count 2 2006.257.13:26:20.00#ibcon#read 6, iclass 24, count 2 2006.257.13:26:20.00#ibcon#end of sib2, iclass 24, count 2 2006.257.13:26:20.00#ibcon#*mode == 0, iclass 24, count 2 2006.257.13:26:20.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.13:26:20.00#ibcon#[27=AT07-04\r\n] 2006.257.13:26:20.00#ibcon#*before write, iclass 24, count 2 2006.257.13:26:20.00#ibcon#enter sib2, iclass 24, count 2 2006.257.13:26:20.00#ibcon#flushed, iclass 24, count 2 2006.257.13:26:20.00#ibcon#about to write, iclass 24, count 2 2006.257.13:26:20.00#ibcon#wrote, iclass 24, count 2 2006.257.13:26:20.00#ibcon#about to read 3, iclass 24, count 2 2006.257.13:26:20.03#ibcon#read 3, iclass 24, count 2 2006.257.13:26:20.03#ibcon#about to read 4, iclass 24, count 2 2006.257.13:26:20.03#ibcon#read 4, iclass 24, count 2 2006.257.13:26:20.03#ibcon#about to read 5, iclass 24, count 2 2006.257.13:26:20.03#ibcon#read 5, iclass 24, count 2 2006.257.13:26:20.03#ibcon#about to read 6, iclass 24, count 2 2006.257.13:26:20.03#ibcon#read 6, iclass 24, count 2 2006.257.13:26:20.03#ibcon#end of sib2, iclass 24, count 2 2006.257.13:26:20.03#ibcon#*after write, iclass 24, count 2 2006.257.13:26:20.03#ibcon#*before return 0, iclass 24, count 2 2006.257.13:26:20.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:20.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:26:20.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.13:26:20.03#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:20.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:20.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:20.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:20.15#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:26:20.15#ibcon#first serial, iclass 24, count 0 2006.257.13:26:20.15#ibcon#enter sib2, iclass 24, count 0 2006.257.13:26:20.15#ibcon#flushed, iclass 24, count 0 2006.257.13:26:20.15#ibcon#about to write, iclass 24, count 0 2006.257.13:26:20.15#ibcon#wrote, iclass 24, count 0 2006.257.13:26:20.15#ibcon#about to read 3, iclass 24, count 0 2006.257.13:26:20.17#ibcon#read 3, iclass 24, count 0 2006.257.13:26:20.17#ibcon#about to read 4, iclass 24, count 0 2006.257.13:26:20.17#ibcon#read 4, iclass 24, count 0 2006.257.13:26:20.17#ibcon#about to read 5, iclass 24, count 0 2006.257.13:26:20.17#ibcon#read 5, iclass 24, count 0 2006.257.13:26:20.17#ibcon#about to read 6, iclass 24, count 0 2006.257.13:26:20.17#ibcon#read 6, iclass 24, count 0 2006.257.13:26:20.17#ibcon#end of sib2, iclass 24, count 0 2006.257.13:26:20.17#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:26:20.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:26:20.17#ibcon#[27=USB\r\n] 2006.257.13:26:20.17#ibcon#*before write, iclass 24, count 0 2006.257.13:26:20.17#ibcon#enter sib2, iclass 24, count 0 2006.257.13:26:20.17#ibcon#flushed, iclass 24, count 0 2006.257.13:26:20.17#ibcon#about to write, iclass 24, count 0 2006.257.13:26:20.17#ibcon#wrote, iclass 24, count 0 2006.257.13:26:20.17#ibcon#about to read 3, iclass 24, count 0 2006.257.13:26:20.20#ibcon#read 3, iclass 24, count 0 2006.257.13:26:20.20#ibcon#about to read 4, iclass 24, count 0 2006.257.13:26:20.20#ibcon#read 4, iclass 24, count 0 2006.257.13:26:20.20#ibcon#about to read 5, iclass 24, count 0 2006.257.13:26:20.20#ibcon#read 5, iclass 24, count 0 2006.257.13:26:20.20#ibcon#about to read 6, iclass 24, count 0 2006.257.13:26:20.20#ibcon#read 6, iclass 24, count 0 2006.257.13:26:20.20#ibcon#end of sib2, iclass 24, count 0 2006.257.13:26:20.20#ibcon#*after write, iclass 24, count 0 2006.257.13:26:20.20#ibcon#*before return 0, iclass 24, count 0 2006.257.13:26:20.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:20.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:26:20.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:26:20.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:26:20.20$vck44/vblo=8,744.99 2006.257.13:26:20.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.13:26:20.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.13:26:20.20#ibcon#ireg 17 cls_cnt 0 2006.257.13:26:20.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:20.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:20.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:20.20#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:26:20.20#ibcon#first serial, iclass 26, count 0 2006.257.13:26:20.20#ibcon#enter sib2, iclass 26, count 0 2006.257.13:26:20.20#ibcon#flushed, iclass 26, count 0 2006.257.13:26:20.20#ibcon#about to write, iclass 26, count 0 2006.257.13:26:20.20#ibcon#wrote, iclass 26, count 0 2006.257.13:26:20.20#ibcon#about to read 3, iclass 26, count 0 2006.257.13:26:20.22#ibcon#read 3, iclass 26, count 0 2006.257.13:26:20.22#ibcon#about to read 4, iclass 26, count 0 2006.257.13:26:20.22#ibcon#read 4, iclass 26, count 0 2006.257.13:26:20.22#ibcon#about to read 5, iclass 26, count 0 2006.257.13:26:20.22#ibcon#read 5, iclass 26, count 0 2006.257.13:26:20.22#ibcon#about to read 6, iclass 26, count 0 2006.257.13:26:20.22#ibcon#read 6, iclass 26, count 0 2006.257.13:26:20.22#ibcon#end of sib2, iclass 26, count 0 2006.257.13:26:20.22#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:26:20.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:26:20.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:26:20.22#ibcon#*before write, iclass 26, count 0 2006.257.13:26:20.22#ibcon#enter sib2, iclass 26, count 0 2006.257.13:26:20.22#ibcon#flushed, iclass 26, count 0 2006.257.13:26:20.22#ibcon#about to write, iclass 26, count 0 2006.257.13:26:20.22#ibcon#wrote, iclass 26, count 0 2006.257.13:26:20.22#ibcon#about to read 3, iclass 26, count 0 2006.257.13:26:20.26#ibcon#read 3, iclass 26, count 0 2006.257.13:26:20.26#ibcon#about to read 4, iclass 26, count 0 2006.257.13:26:20.26#ibcon#read 4, iclass 26, count 0 2006.257.13:26:20.26#ibcon#about to read 5, iclass 26, count 0 2006.257.13:26:20.26#ibcon#read 5, iclass 26, count 0 2006.257.13:26:20.26#ibcon#about to read 6, iclass 26, count 0 2006.257.13:26:20.26#ibcon#read 6, iclass 26, count 0 2006.257.13:26:20.26#ibcon#end of sib2, iclass 26, count 0 2006.257.13:26:20.26#ibcon#*after write, iclass 26, count 0 2006.257.13:26:20.26#ibcon#*before return 0, iclass 26, count 0 2006.257.13:26:20.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:20.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:26:20.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:26:20.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:26:20.26$vck44/vb=8,4 2006.257.13:26:20.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.13:26:20.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.13:26:20.26#ibcon#ireg 11 cls_cnt 2 2006.257.13:26:20.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:20.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:20.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:20.32#ibcon#enter wrdev, iclass 28, count 2 2006.257.13:26:20.32#ibcon#first serial, iclass 28, count 2 2006.257.13:26:20.32#ibcon#enter sib2, iclass 28, count 2 2006.257.13:26:20.32#ibcon#flushed, iclass 28, count 2 2006.257.13:26:20.32#ibcon#about to write, iclass 28, count 2 2006.257.13:26:20.32#ibcon#wrote, iclass 28, count 2 2006.257.13:26:20.32#ibcon#about to read 3, iclass 28, count 2 2006.257.13:26:20.34#ibcon#read 3, iclass 28, count 2 2006.257.13:26:20.34#ibcon#about to read 4, iclass 28, count 2 2006.257.13:26:20.34#ibcon#read 4, iclass 28, count 2 2006.257.13:26:20.34#ibcon#about to read 5, iclass 28, count 2 2006.257.13:26:20.34#ibcon#read 5, iclass 28, count 2 2006.257.13:26:20.34#ibcon#about to read 6, iclass 28, count 2 2006.257.13:26:20.34#ibcon#read 6, iclass 28, count 2 2006.257.13:26:20.34#ibcon#end of sib2, iclass 28, count 2 2006.257.13:26:20.34#ibcon#*mode == 0, iclass 28, count 2 2006.257.13:26:20.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.13:26:20.34#ibcon#[27=AT08-04\r\n] 2006.257.13:26:20.34#ibcon#*before write, iclass 28, count 2 2006.257.13:26:20.34#ibcon#enter sib2, iclass 28, count 2 2006.257.13:26:20.34#ibcon#flushed, iclass 28, count 2 2006.257.13:26:20.34#ibcon#about to write, iclass 28, count 2 2006.257.13:26:20.34#ibcon#wrote, iclass 28, count 2 2006.257.13:26:20.34#ibcon#about to read 3, iclass 28, count 2 2006.257.13:26:20.38#ibcon#read 3, iclass 28, count 2 2006.257.13:26:20.38#ibcon#about to read 4, iclass 28, count 2 2006.257.13:26:20.38#ibcon#read 4, iclass 28, count 2 2006.257.13:26:20.38#ibcon#about to read 5, iclass 28, count 2 2006.257.13:26:20.38#ibcon#read 5, iclass 28, count 2 2006.257.13:26:20.38#ibcon#about to read 6, iclass 28, count 2 2006.257.13:26:20.38#ibcon#read 6, iclass 28, count 2 2006.257.13:26:20.38#ibcon#end of sib2, iclass 28, count 2 2006.257.13:26:20.38#ibcon#*after write, iclass 28, count 2 2006.257.13:26:20.38#ibcon#*before return 0, iclass 28, count 2 2006.257.13:26:20.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:20.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:26:20.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.13:26:20.38#ibcon#ireg 7 cls_cnt 0 2006.257.13:26:20.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:20.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:20.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:20.49#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:26:20.49#ibcon#first serial, iclass 28, count 0 2006.257.13:26:20.49#ibcon#enter sib2, iclass 28, count 0 2006.257.13:26:20.49#ibcon#flushed, iclass 28, count 0 2006.257.13:26:20.49#ibcon#about to write, iclass 28, count 0 2006.257.13:26:20.49#ibcon#wrote, iclass 28, count 0 2006.257.13:26:20.49#ibcon#about to read 3, iclass 28, count 0 2006.257.13:26:20.51#ibcon#read 3, iclass 28, count 0 2006.257.13:26:20.51#ibcon#about to read 4, iclass 28, count 0 2006.257.13:26:20.51#ibcon#read 4, iclass 28, count 0 2006.257.13:26:20.51#ibcon#about to read 5, iclass 28, count 0 2006.257.13:26:20.51#ibcon#read 5, iclass 28, count 0 2006.257.13:26:20.51#ibcon#about to read 6, iclass 28, count 0 2006.257.13:26:20.51#ibcon#read 6, iclass 28, count 0 2006.257.13:26:20.51#ibcon#end of sib2, iclass 28, count 0 2006.257.13:26:20.51#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:26:20.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:26:20.51#ibcon#[27=USB\r\n] 2006.257.13:26:20.51#ibcon#*before write, iclass 28, count 0 2006.257.13:26:20.51#ibcon#enter sib2, iclass 28, count 0 2006.257.13:26:20.51#ibcon#flushed, iclass 28, count 0 2006.257.13:26:20.51#ibcon#about to write, iclass 28, count 0 2006.257.13:26:20.51#ibcon#wrote, iclass 28, count 0 2006.257.13:26:20.51#ibcon#about to read 3, iclass 28, count 0 2006.257.13:26:20.54#ibcon#read 3, iclass 28, count 0 2006.257.13:26:20.54#ibcon#about to read 4, iclass 28, count 0 2006.257.13:26:20.54#ibcon#read 4, iclass 28, count 0 2006.257.13:26:20.54#ibcon#about to read 5, iclass 28, count 0 2006.257.13:26:20.54#ibcon#read 5, iclass 28, count 0 2006.257.13:26:20.54#ibcon#about to read 6, iclass 28, count 0 2006.257.13:26:20.54#ibcon#read 6, iclass 28, count 0 2006.257.13:26:20.54#ibcon#end of sib2, iclass 28, count 0 2006.257.13:26:20.54#ibcon#*after write, iclass 28, count 0 2006.257.13:26:20.54#ibcon#*before return 0, iclass 28, count 0 2006.257.13:26:20.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:20.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:26:20.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:26:20.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:26:20.54$vck44/vabw=wide 2006.257.13:26:20.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.13:26:20.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.13:26:20.54#ibcon#ireg 8 cls_cnt 0 2006.257.13:26:20.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:20.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:20.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:20.54#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:26:20.54#ibcon#first serial, iclass 30, count 0 2006.257.13:26:20.54#ibcon#enter sib2, iclass 30, count 0 2006.257.13:26:20.54#ibcon#flushed, iclass 30, count 0 2006.257.13:26:20.54#ibcon#about to write, iclass 30, count 0 2006.257.13:26:20.54#ibcon#wrote, iclass 30, count 0 2006.257.13:26:20.54#ibcon#about to read 3, iclass 30, count 0 2006.257.13:26:20.56#ibcon#read 3, iclass 30, count 0 2006.257.13:26:20.56#ibcon#about to read 4, iclass 30, count 0 2006.257.13:26:20.56#ibcon#read 4, iclass 30, count 0 2006.257.13:26:20.56#ibcon#about to read 5, iclass 30, count 0 2006.257.13:26:20.56#ibcon#read 5, iclass 30, count 0 2006.257.13:26:20.56#ibcon#about to read 6, iclass 30, count 0 2006.257.13:26:20.56#ibcon#read 6, iclass 30, count 0 2006.257.13:26:20.56#ibcon#end of sib2, iclass 30, count 0 2006.257.13:26:20.56#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:26:20.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:26:20.56#ibcon#[25=BW32\r\n] 2006.257.13:26:20.56#ibcon#*before write, iclass 30, count 0 2006.257.13:26:20.56#ibcon#enter sib2, iclass 30, count 0 2006.257.13:26:20.56#ibcon#flushed, iclass 30, count 0 2006.257.13:26:20.56#ibcon#about to write, iclass 30, count 0 2006.257.13:26:20.56#ibcon#wrote, iclass 30, count 0 2006.257.13:26:20.56#ibcon#about to read 3, iclass 30, count 0 2006.257.13:26:20.59#ibcon#read 3, iclass 30, count 0 2006.257.13:26:20.59#ibcon#about to read 4, iclass 30, count 0 2006.257.13:26:20.59#ibcon#read 4, iclass 30, count 0 2006.257.13:26:20.59#ibcon#about to read 5, iclass 30, count 0 2006.257.13:26:20.59#ibcon#read 5, iclass 30, count 0 2006.257.13:26:20.59#ibcon#about to read 6, iclass 30, count 0 2006.257.13:26:20.59#ibcon#read 6, iclass 30, count 0 2006.257.13:26:20.59#ibcon#end of sib2, iclass 30, count 0 2006.257.13:26:20.59#ibcon#*after write, iclass 30, count 0 2006.257.13:26:20.59#ibcon#*before return 0, iclass 30, count 0 2006.257.13:26:20.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:20.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:26:20.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:26:20.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:26:20.59$vck44/vbbw=wide 2006.257.13:26:20.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.13:26:20.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.13:26:20.59#ibcon#ireg 8 cls_cnt 0 2006.257.13:26:20.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:26:20.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:26:20.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:26:20.66#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:26:20.66#ibcon#first serial, iclass 32, count 0 2006.257.13:26:20.66#ibcon#enter sib2, iclass 32, count 0 2006.257.13:26:20.66#ibcon#flushed, iclass 32, count 0 2006.257.13:26:20.66#ibcon#about to write, iclass 32, count 0 2006.257.13:26:20.66#ibcon#wrote, iclass 32, count 0 2006.257.13:26:20.66#ibcon#about to read 3, iclass 32, count 0 2006.257.13:26:20.68#ibcon#read 3, iclass 32, count 0 2006.257.13:26:20.68#ibcon#about to read 4, iclass 32, count 0 2006.257.13:26:20.68#ibcon#read 4, iclass 32, count 0 2006.257.13:26:20.68#ibcon#about to read 5, iclass 32, count 0 2006.257.13:26:20.68#ibcon#read 5, iclass 32, count 0 2006.257.13:26:20.68#ibcon#about to read 6, iclass 32, count 0 2006.257.13:26:20.68#ibcon#read 6, iclass 32, count 0 2006.257.13:26:20.68#ibcon#end of sib2, iclass 32, count 0 2006.257.13:26:20.68#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:26:20.68#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:26:20.68#ibcon#[27=BW32\r\n] 2006.257.13:26:20.68#ibcon#*before write, iclass 32, count 0 2006.257.13:26:20.68#ibcon#enter sib2, iclass 32, count 0 2006.257.13:26:20.68#ibcon#flushed, iclass 32, count 0 2006.257.13:26:20.68#ibcon#about to write, iclass 32, count 0 2006.257.13:26:20.68#ibcon#wrote, iclass 32, count 0 2006.257.13:26:20.68#ibcon#about to read 3, iclass 32, count 0 2006.257.13:26:20.71#ibcon#read 3, iclass 32, count 0 2006.257.13:26:20.71#ibcon#about to read 4, iclass 32, count 0 2006.257.13:26:20.71#ibcon#read 4, iclass 32, count 0 2006.257.13:26:20.71#ibcon#about to read 5, iclass 32, count 0 2006.257.13:26:20.71#ibcon#read 5, iclass 32, count 0 2006.257.13:26:20.71#ibcon#about to read 6, iclass 32, count 0 2006.257.13:26:20.71#ibcon#read 6, iclass 32, count 0 2006.257.13:26:20.71#ibcon#end of sib2, iclass 32, count 0 2006.257.13:26:20.71#ibcon#*after write, iclass 32, count 0 2006.257.13:26:20.71#ibcon#*before return 0, iclass 32, count 0 2006.257.13:26:20.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:26:20.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:26:20.71#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:26:20.71#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:26:20.71$setupk4/ifdk4 2006.257.13:26:20.71$ifdk4/lo= 2006.257.13:26:20.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:26:20.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:26:20.71$ifdk4/patch= 2006.257.13:26:20.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:26:20.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:26:20.71$setupk4/!*+20s 2006.257.13:26:29.53#abcon#<5=/14 1.2 2.7 17.55 971013.9\r\n> 2006.257.13:26:29.55#abcon#{5=INTERFACE CLEAR} 2006.257.13:26:29.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:26:35.19$setupk4/"tpicd 2006.257.13:26:35.19$setupk4/echo=off 2006.257.13:26:35.19$setupk4/xlog=off 2006.257.13:26:35.19:!2006.257.13:28:29 2006.257.13:26:42.14#trakl#Source acquired 2006.257.13:26:43.14#flagr#flagr/antenna,acquired 2006.257.13:28:29.00:preob 2006.257.13:28:29.14/onsource/TRACKING 2006.257.13:28:29.14:!2006.257.13:28:39 2006.257.13:28:39.00:"tape 2006.257.13:28:39.00:"st=record 2006.257.13:28:39.00:data_valid=on 2006.257.13:28:39.00:midob 2006.257.13:28:40.14/onsource/TRACKING 2006.257.13:28:40.14/wx/17.52,1013.9,97 2006.257.13:28:40.24/cable/+6.4812E-03 2006.257.13:28:41.33/va/01,08,usb,yes,34,36 2006.257.13:28:41.33/va/02,07,usb,yes,36,37 2006.257.13:28:41.33/va/03,08,usb,yes,33,35 2006.257.13:28:41.33/va/04,07,usb,yes,38,39 2006.257.13:28:41.33/va/05,04,usb,yes,34,34 2006.257.13:28:41.33/va/06,04,usb,yes,37,37 2006.257.13:28:41.33/va/07,04,usb,yes,38,39 2006.257.13:28:41.33/va/08,04,usb,yes,32,39 2006.257.13:28:41.56/valo/01,524.99,yes,locked 2006.257.13:28:41.56/valo/02,534.99,yes,locked 2006.257.13:28:41.56/valo/03,564.99,yes,locked 2006.257.13:28:41.56/valo/04,624.99,yes,locked 2006.257.13:28:41.56/valo/05,734.99,yes,locked 2006.257.13:28:41.56/valo/06,814.99,yes,locked 2006.257.13:28:41.56/valo/07,864.99,yes,locked 2006.257.13:28:41.56/valo/08,884.99,yes,locked 2006.257.13:28:42.65/vb/01,04,usb,yes,32,29 2006.257.13:28:42.65/vb/02,05,usb,yes,30,30 2006.257.13:28:42.65/vb/03,04,usb,yes,31,34 2006.257.13:28:42.65/vb/04,05,usb,yes,31,30 2006.257.13:28:42.65/vb/05,04,usb,yes,28,30 2006.257.13:28:42.65/vb/06,04,usb,yes,32,28 2006.257.13:28:42.65/vb/07,04,usb,yes,32,32 2006.257.13:28:42.65/vb/08,04,usb,yes,29,33 2006.257.13:28:42.89/vblo/01,629.99,yes,locked 2006.257.13:28:42.89/vblo/02,634.99,yes,locked 2006.257.13:28:42.89/vblo/03,649.99,yes,locked 2006.257.13:28:42.89/vblo/04,679.99,yes,locked 2006.257.13:28:42.89/vblo/05,709.99,yes,locked 2006.257.13:28:42.89/vblo/06,719.99,yes,locked 2006.257.13:28:42.89/vblo/07,734.99,yes,locked 2006.257.13:28:42.89/vblo/08,744.99,yes,locked 2006.257.13:28:43.04/vabw/8 2006.257.13:28:43.19/vbbw/8 2006.257.13:28:43.40/xfe/off,on,16.0 2006.257.13:28:43.78/ifatt/23,28,28,28 2006.257.13:28:44.07/fmout-gps/S +4.61E-07 2006.257.13:28:44.11:!2006.257.13:29:19 2006.257.13:29:19.01:data_valid=off 2006.257.13:29:19.02:"et 2006.257.13:29:19.02:!+3s 2006.257.13:29:22.03:"tape 2006.257.13:29:22.03:postob 2006.257.13:29:22.19/cable/+6.4813E-03 2006.257.13:29:22.19/wx/17.51,1013.9,97 2006.257.13:29:22.25/fmout-gps/S +4.60E-07 2006.257.13:29:22.25:scan_name=257-1331,jd0609,70 2006.257.13:29:22.26:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.13:29:24.13#flagr#flagr/antenna,new-source 2006.257.13:29:24.13:checkk5 2006.257.13:29:24.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:29:24.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:29:25.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:29:25.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:29:26.17/chk_obsdata//k5ts1/T2571328??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:29:26.56/chk_obsdata//k5ts2/T2571328??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:29:26.96/chk_obsdata//k5ts3/T2571328??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:29:27.36/chk_obsdata//k5ts4/T2571328??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:29:28.09/k5log//k5ts1_log_newline 2006.257.13:29:28.80/k5log//k5ts2_log_newline 2006.257.13:29:29.51/k5log//k5ts3_log_newline 2006.257.13:29:30.22/k5log//k5ts4_log_newline 2006.257.13:29:30.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:29:30.24:setupk4=1 2006.257.13:29:30.24$setupk4/echo=on 2006.257.13:29:30.24$setupk4/pcalon 2006.257.13:29:30.24$pcalon/"no phase cal control is implemented here 2006.257.13:29:30.24$setupk4/"tpicd=stop 2006.257.13:29:30.24$setupk4/"rec=synch_on 2006.257.13:29:30.24$setupk4/"rec_mode=128 2006.257.13:29:30.25$setupk4/!* 2006.257.13:29:30.25$setupk4/recpk4 2006.257.13:29:30.25$recpk4/recpatch= 2006.257.13:29:30.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:29:30.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:29:30.25$setupk4/vck44 2006.257.13:29:30.25$vck44/valo=1,524.99 2006.257.13:29:30.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.13:29:30.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.13:29:30.25#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:30.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:30.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:30.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:30.25#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:29:30.25#ibcon#first serial, iclass 37, count 0 2006.257.13:29:30.25#ibcon#enter sib2, iclass 37, count 0 2006.257.13:29:30.25#ibcon#flushed, iclass 37, count 0 2006.257.13:29:30.25#ibcon#about to write, iclass 37, count 0 2006.257.13:29:30.25#ibcon#wrote, iclass 37, count 0 2006.257.13:29:30.25#ibcon#about to read 3, iclass 37, count 0 2006.257.13:29:30.26#ibcon#read 3, iclass 37, count 0 2006.257.13:29:30.26#ibcon#about to read 4, iclass 37, count 0 2006.257.13:29:30.26#ibcon#read 4, iclass 37, count 0 2006.257.13:29:30.26#ibcon#about to read 5, iclass 37, count 0 2006.257.13:29:30.26#ibcon#read 5, iclass 37, count 0 2006.257.13:29:30.26#ibcon#about to read 6, iclass 37, count 0 2006.257.13:29:30.26#ibcon#read 6, iclass 37, count 0 2006.257.13:29:30.26#ibcon#end of sib2, iclass 37, count 0 2006.257.13:29:30.26#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:29:30.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:29:30.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:29:30.26#ibcon#*before write, iclass 37, count 0 2006.257.13:29:30.26#ibcon#enter sib2, iclass 37, count 0 2006.257.13:29:30.26#ibcon#flushed, iclass 37, count 0 2006.257.13:29:30.26#ibcon#about to write, iclass 37, count 0 2006.257.13:29:30.26#ibcon#wrote, iclass 37, count 0 2006.257.13:29:30.26#ibcon#about to read 3, iclass 37, count 0 2006.257.13:29:30.31#ibcon#read 3, iclass 37, count 0 2006.257.13:29:30.31#ibcon#about to read 4, iclass 37, count 0 2006.257.13:29:30.31#ibcon#read 4, iclass 37, count 0 2006.257.13:29:30.31#ibcon#about to read 5, iclass 37, count 0 2006.257.13:29:30.31#ibcon#read 5, iclass 37, count 0 2006.257.13:29:30.31#ibcon#about to read 6, iclass 37, count 0 2006.257.13:29:30.31#ibcon#read 6, iclass 37, count 0 2006.257.13:29:30.31#ibcon#end of sib2, iclass 37, count 0 2006.257.13:29:30.31#ibcon#*after write, iclass 37, count 0 2006.257.13:29:30.31#ibcon#*before return 0, iclass 37, count 0 2006.257.13:29:30.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:30.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:30.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:29:30.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:29:30.31$vck44/va=1,8 2006.257.13:29:30.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.13:29:30.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.13:29:30.31#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:30.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:30.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:30.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:30.31#ibcon#enter wrdev, iclass 39, count 2 2006.257.13:29:30.31#ibcon#first serial, iclass 39, count 2 2006.257.13:29:30.31#ibcon#enter sib2, iclass 39, count 2 2006.257.13:29:30.31#ibcon#flushed, iclass 39, count 2 2006.257.13:29:30.31#ibcon#about to write, iclass 39, count 2 2006.257.13:29:30.31#ibcon#wrote, iclass 39, count 2 2006.257.13:29:30.31#ibcon#about to read 3, iclass 39, count 2 2006.257.13:29:30.33#ibcon#read 3, iclass 39, count 2 2006.257.13:29:30.33#ibcon#about to read 4, iclass 39, count 2 2006.257.13:29:30.33#ibcon#read 4, iclass 39, count 2 2006.257.13:29:30.33#ibcon#about to read 5, iclass 39, count 2 2006.257.13:29:30.33#ibcon#read 5, iclass 39, count 2 2006.257.13:29:30.33#ibcon#about to read 6, iclass 39, count 2 2006.257.13:29:30.33#ibcon#read 6, iclass 39, count 2 2006.257.13:29:30.33#ibcon#end of sib2, iclass 39, count 2 2006.257.13:29:30.33#ibcon#*mode == 0, iclass 39, count 2 2006.257.13:29:30.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.13:29:30.33#ibcon#[25=AT01-08\r\n] 2006.257.13:29:30.33#ibcon#*before write, iclass 39, count 2 2006.257.13:29:30.33#ibcon#enter sib2, iclass 39, count 2 2006.257.13:29:30.33#ibcon#flushed, iclass 39, count 2 2006.257.13:29:30.33#ibcon#about to write, iclass 39, count 2 2006.257.13:29:30.33#ibcon#wrote, iclass 39, count 2 2006.257.13:29:30.33#ibcon#about to read 3, iclass 39, count 2 2006.257.13:29:30.36#ibcon#read 3, iclass 39, count 2 2006.257.13:29:30.36#ibcon#about to read 4, iclass 39, count 2 2006.257.13:29:30.36#ibcon#read 4, iclass 39, count 2 2006.257.13:29:30.36#ibcon#about to read 5, iclass 39, count 2 2006.257.13:29:30.36#ibcon#read 5, iclass 39, count 2 2006.257.13:29:30.36#ibcon#about to read 6, iclass 39, count 2 2006.257.13:29:30.36#ibcon#read 6, iclass 39, count 2 2006.257.13:29:30.36#ibcon#end of sib2, iclass 39, count 2 2006.257.13:29:30.36#ibcon#*after write, iclass 39, count 2 2006.257.13:29:30.36#ibcon#*before return 0, iclass 39, count 2 2006.257.13:29:30.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:30.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:30.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.13:29:30.36#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:30.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:30.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:30.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:30.48#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:29:30.48#ibcon#first serial, iclass 39, count 0 2006.257.13:29:30.48#ibcon#enter sib2, iclass 39, count 0 2006.257.13:29:30.48#ibcon#flushed, iclass 39, count 0 2006.257.13:29:30.48#ibcon#about to write, iclass 39, count 0 2006.257.13:29:30.48#ibcon#wrote, iclass 39, count 0 2006.257.13:29:30.48#ibcon#about to read 3, iclass 39, count 0 2006.257.13:29:30.50#ibcon#read 3, iclass 39, count 0 2006.257.13:29:30.50#ibcon#about to read 4, iclass 39, count 0 2006.257.13:29:30.50#ibcon#read 4, iclass 39, count 0 2006.257.13:29:30.50#ibcon#about to read 5, iclass 39, count 0 2006.257.13:29:30.50#ibcon#read 5, iclass 39, count 0 2006.257.13:29:30.50#ibcon#about to read 6, iclass 39, count 0 2006.257.13:29:30.50#ibcon#read 6, iclass 39, count 0 2006.257.13:29:30.50#ibcon#end of sib2, iclass 39, count 0 2006.257.13:29:30.50#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:29:30.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:29:30.50#ibcon#[25=USB\r\n] 2006.257.13:29:30.50#ibcon#*before write, iclass 39, count 0 2006.257.13:29:30.50#ibcon#enter sib2, iclass 39, count 0 2006.257.13:29:30.50#ibcon#flushed, iclass 39, count 0 2006.257.13:29:30.50#ibcon#about to write, iclass 39, count 0 2006.257.13:29:30.50#ibcon#wrote, iclass 39, count 0 2006.257.13:29:30.50#ibcon#about to read 3, iclass 39, count 0 2006.257.13:29:30.53#ibcon#read 3, iclass 39, count 0 2006.257.13:29:30.53#ibcon#about to read 4, iclass 39, count 0 2006.257.13:29:30.53#ibcon#read 4, iclass 39, count 0 2006.257.13:29:30.53#ibcon#about to read 5, iclass 39, count 0 2006.257.13:29:30.53#ibcon#read 5, iclass 39, count 0 2006.257.13:29:30.53#ibcon#about to read 6, iclass 39, count 0 2006.257.13:29:30.53#ibcon#read 6, iclass 39, count 0 2006.257.13:29:30.53#ibcon#end of sib2, iclass 39, count 0 2006.257.13:29:30.53#ibcon#*after write, iclass 39, count 0 2006.257.13:29:30.53#ibcon#*before return 0, iclass 39, count 0 2006.257.13:29:30.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:30.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:30.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:29:30.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:29:30.53$vck44/valo=2,534.99 2006.257.13:29:30.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.13:29:30.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.13:29:30.53#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:30.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:30.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:30.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:30.53#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:29:30.53#ibcon#first serial, iclass 3, count 0 2006.257.13:29:30.53#ibcon#enter sib2, iclass 3, count 0 2006.257.13:29:30.53#ibcon#flushed, iclass 3, count 0 2006.257.13:29:30.53#ibcon#about to write, iclass 3, count 0 2006.257.13:29:30.53#ibcon#wrote, iclass 3, count 0 2006.257.13:29:30.53#ibcon#about to read 3, iclass 3, count 0 2006.257.13:29:30.55#ibcon#read 3, iclass 3, count 0 2006.257.13:29:30.55#ibcon#about to read 4, iclass 3, count 0 2006.257.13:29:30.55#ibcon#read 4, iclass 3, count 0 2006.257.13:29:30.55#ibcon#about to read 5, iclass 3, count 0 2006.257.13:29:30.55#ibcon#read 5, iclass 3, count 0 2006.257.13:29:30.55#ibcon#about to read 6, iclass 3, count 0 2006.257.13:29:30.55#ibcon#read 6, iclass 3, count 0 2006.257.13:29:30.55#ibcon#end of sib2, iclass 3, count 0 2006.257.13:29:30.55#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:29:30.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:29:30.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:29:30.55#ibcon#*before write, iclass 3, count 0 2006.257.13:29:30.55#ibcon#enter sib2, iclass 3, count 0 2006.257.13:29:30.55#ibcon#flushed, iclass 3, count 0 2006.257.13:29:30.55#ibcon#about to write, iclass 3, count 0 2006.257.13:29:30.55#ibcon#wrote, iclass 3, count 0 2006.257.13:29:30.55#ibcon#about to read 3, iclass 3, count 0 2006.257.13:29:30.59#ibcon#read 3, iclass 3, count 0 2006.257.13:29:30.59#ibcon#about to read 4, iclass 3, count 0 2006.257.13:29:30.59#ibcon#read 4, iclass 3, count 0 2006.257.13:29:30.59#ibcon#about to read 5, iclass 3, count 0 2006.257.13:29:30.59#ibcon#read 5, iclass 3, count 0 2006.257.13:29:30.59#ibcon#about to read 6, iclass 3, count 0 2006.257.13:29:30.59#ibcon#read 6, iclass 3, count 0 2006.257.13:29:30.59#ibcon#end of sib2, iclass 3, count 0 2006.257.13:29:30.59#ibcon#*after write, iclass 3, count 0 2006.257.13:29:30.59#ibcon#*before return 0, iclass 3, count 0 2006.257.13:29:30.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:30.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:30.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:29:30.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:29:30.59$vck44/va=2,7 2006.257.13:29:30.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.13:29:30.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.13:29:30.59#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:30.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:30.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:30.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:30.65#ibcon#enter wrdev, iclass 5, count 2 2006.257.13:29:30.65#ibcon#first serial, iclass 5, count 2 2006.257.13:29:30.65#ibcon#enter sib2, iclass 5, count 2 2006.257.13:29:30.65#ibcon#flushed, iclass 5, count 2 2006.257.13:29:30.65#ibcon#about to write, iclass 5, count 2 2006.257.13:29:30.65#ibcon#wrote, iclass 5, count 2 2006.257.13:29:30.65#ibcon#about to read 3, iclass 5, count 2 2006.257.13:29:30.67#ibcon#read 3, iclass 5, count 2 2006.257.13:29:30.67#ibcon#about to read 4, iclass 5, count 2 2006.257.13:29:30.67#ibcon#read 4, iclass 5, count 2 2006.257.13:29:30.67#ibcon#about to read 5, iclass 5, count 2 2006.257.13:29:30.67#ibcon#read 5, iclass 5, count 2 2006.257.13:29:30.67#ibcon#about to read 6, iclass 5, count 2 2006.257.13:29:30.67#ibcon#read 6, iclass 5, count 2 2006.257.13:29:30.67#ibcon#end of sib2, iclass 5, count 2 2006.257.13:29:30.67#ibcon#*mode == 0, iclass 5, count 2 2006.257.13:29:30.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.13:29:30.67#ibcon#[25=AT02-07\r\n] 2006.257.13:29:30.67#ibcon#*before write, iclass 5, count 2 2006.257.13:29:30.67#ibcon#enter sib2, iclass 5, count 2 2006.257.13:29:30.67#ibcon#flushed, iclass 5, count 2 2006.257.13:29:30.67#ibcon#about to write, iclass 5, count 2 2006.257.13:29:30.67#ibcon#wrote, iclass 5, count 2 2006.257.13:29:30.67#ibcon#about to read 3, iclass 5, count 2 2006.257.13:29:30.70#ibcon#read 3, iclass 5, count 2 2006.257.13:29:30.70#ibcon#about to read 4, iclass 5, count 2 2006.257.13:29:30.70#ibcon#read 4, iclass 5, count 2 2006.257.13:29:30.70#ibcon#about to read 5, iclass 5, count 2 2006.257.13:29:30.70#ibcon#read 5, iclass 5, count 2 2006.257.13:29:30.70#ibcon#about to read 6, iclass 5, count 2 2006.257.13:29:30.70#ibcon#read 6, iclass 5, count 2 2006.257.13:29:30.70#ibcon#end of sib2, iclass 5, count 2 2006.257.13:29:30.70#ibcon#*after write, iclass 5, count 2 2006.257.13:29:30.70#ibcon#*before return 0, iclass 5, count 2 2006.257.13:29:30.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:30.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:30.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.13:29:30.70#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:30.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:30.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:30.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:30.82#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:29:30.82#ibcon#first serial, iclass 5, count 0 2006.257.13:29:30.82#ibcon#enter sib2, iclass 5, count 0 2006.257.13:29:30.82#ibcon#flushed, iclass 5, count 0 2006.257.13:29:30.82#ibcon#about to write, iclass 5, count 0 2006.257.13:29:30.82#ibcon#wrote, iclass 5, count 0 2006.257.13:29:30.82#ibcon#about to read 3, iclass 5, count 0 2006.257.13:29:30.84#ibcon#read 3, iclass 5, count 0 2006.257.13:29:30.84#ibcon#about to read 4, iclass 5, count 0 2006.257.13:29:30.84#ibcon#read 4, iclass 5, count 0 2006.257.13:29:30.84#ibcon#about to read 5, iclass 5, count 0 2006.257.13:29:30.84#ibcon#read 5, iclass 5, count 0 2006.257.13:29:30.84#ibcon#about to read 6, iclass 5, count 0 2006.257.13:29:30.84#ibcon#read 6, iclass 5, count 0 2006.257.13:29:30.84#ibcon#end of sib2, iclass 5, count 0 2006.257.13:29:30.84#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:29:30.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:29:30.84#ibcon#[25=USB\r\n] 2006.257.13:29:30.84#ibcon#*before write, iclass 5, count 0 2006.257.13:29:30.84#ibcon#enter sib2, iclass 5, count 0 2006.257.13:29:30.84#ibcon#flushed, iclass 5, count 0 2006.257.13:29:30.84#ibcon#about to write, iclass 5, count 0 2006.257.13:29:30.84#ibcon#wrote, iclass 5, count 0 2006.257.13:29:30.84#ibcon#about to read 3, iclass 5, count 0 2006.257.13:29:30.87#ibcon#read 3, iclass 5, count 0 2006.257.13:29:30.87#ibcon#about to read 4, iclass 5, count 0 2006.257.13:29:30.87#ibcon#read 4, iclass 5, count 0 2006.257.13:29:30.87#ibcon#about to read 5, iclass 5, count 0 2006.257.13:29:30.87#ibcon#read 5, iclass 5, count 0 2006.257.13:29:30.87#ibcon#about to read 6, iclass 5, count 0 2006.257.13:29:30.87#ibcon#read 6, iclass 5, count 0 2006.257.13:29:30.87#ibcon#end of sib2, iclass 5, count 0 2006.257.13:29:30.87#ibcon#*after write, iclass 5, count 0 2006.257.13:29:30.87#ibcon#*before return 0, iclass 5, count 0 2006.257.13:29:30.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:30.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:30.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:29:30.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:29:30.87$vck44/valo=3,564.99 2006.257.13:29:30.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.13:29:30.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.13:29:30.87#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:30.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:30.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:30.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:30.87#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:29:30.87#ibcon#first serial, iclass 7, count 0 2006.257.13:29:30.87#ibcon#enter sib2, iclass 7, count 0 2006.257.13:29:30.87#ibcon#flushed, iclass 7, count 0 2006.257.13:29:30.87#ibcon#about to write, iclass 7, count 0 2006.257.13:29:30.87#ibcon#wrote, iclass 7, count 0 2006.257.13:29:30.87#ibcon#about to read 3, iclass 7, count 0 2006.257.13:29:30.89#ibcon#read 3, iclass 7, count 0 2006.257.13:29:30.89#ibcon#about to read 4, iclass 7, count 0 2006.257.13:29:30.89#ibcon#read 4, iclass 7, count 0 2006.257.13:29:30.89#ibcon#about to read 5, iclass 7, count 0 2006.257.13:29:30.89#ibcon#read 5, iclass 7, count 0 2006.257.13:29:30.89#ibcon#about to read 6, iclass 7, count 0 2006.257.13:29:30.89#ibcon#read 6, iclass 7, count 0 2006.257.13:29:30.89#ibcon#end of sib2, iclass 7, count 0 2006.257.13:29:30.89#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:29:30.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:29:30.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:29:30.89#ibcon#*before write, iclass 7, count 0 2006.257.13:29:30.89#ibcon#enter sib2, iclass 7, count 0 2006.257.13:29:30.89#ibcon#flushed, iclass 7, count 0 2006.257.13:29:30.89#ibcon#about to write, iclass 7, count 0 2006.257.13:29:30.89#ibcon#wrote, iclass 7, count 0 2006.257.13:29:30.89#ibcon#about to read 3, iclass 7, count 0 2006.257.13:29:30.93#ibcon#read 3, iclass 7, count 0 2006.257.13:29:30.93#ibcon#about to read 4, iclass 7, count 0 2006.257.13:29:30.93#ibcon#read 4, iclass 7, count 0 2006.257.13:29:30.93#ibcon#about to read 5, iclass 7, count 0 2006.257.13:29:30.93#ibcon#read 5, iclass 7, count 0 2006.257.13:29:30.93#ibcon#about to read 6, iclass 7, count 0 2006.257.13:29:30.93#ibcon#read 6, iclass 7, count 0 2006.257.13:29:30.93#ibcon#end of sib2, iclass 7, count 0 2006.257.13:29:30.93#ibcon#*after write, iclass 7, count 0 2006.257.13:29:30.93#ibcon#*before return 0, iclass 7, count 0 2006.257.13:29:30.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:30.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:30.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:29:30.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:29:30.93$vck44/va=3,8 2006.257.13:29:30.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.13:29:30.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.13:29:30.93#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:30.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:30.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:30.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:30.99#ibcon#enter wrdev, iclass 11, count 2 2006.257.13:29:30.99#ibcon#first serial, iclass 11, count 2 2006.257.13:29:30.99#ibcon#enter sib2, iclass 11, count 2 2006.257.13:29:30.99#ibcon#flushed, iclass 11, count 2 2006.257.13:29:30.99#ibcon#about to write, iclass 11, count 2 2006.257.13:29:30.99#ibcon#wrote, iclass 11, count 2 2006.257.13:29:30.99#ibcon#about to read 3, iclass 11, count 2 2006.257.13:29:31.01#ibcon#read 3, iclass 11, count 2 2006.257.13:29:31.01#ibcon#about to read 4, iclass 11, count 2 2006.257.13:29:31.01#ibcon#read 4, iclass 11, count 2 2006.257.13:29:31.01#ibcon#about to read 5, iclass 11, count 2 2006.257.13:29:31.01#ibcon#read 5, iclass 11, count 2 2006.257.13:29:31.01#ibcon#about to read 6, iclass 11, count 2 2006.257.13:29:31.01#ibcon#read 6, iclass 11, count 2 2006.257.13:29:31.01#ibcon#end of sib2, iclass 11, count 2 2006.257.13:29:31.01#ibcon#*mode == 0, iclass 11, count 2 2006.257.13:29:31.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.13:29:31.01#ibcon#[25=AT03-08\r\n] 2006.257.13:29:31.01#ibcon#*before write, iclass 11, count 2 2006.257.13:29:31.01#ibcon#enter sib2, iclass 11, count 2 2006.257.13:29:31.01#ibcon#flushed, iclass 11, count 2 2006.257.13:29:31.01#ibcon#about to write, iclass 11, count 2 2006.257.13:29:31.01#ibcon#wrote, iclass 11, count 2 2006.257.13:29:31.01#ibcon#about to read 3, iclass 11, count 2 2006.257.13:29:31.04#ibcon#read 3, iclass 11, count 2 2006.257.13:29:31.04#ibcon#about to read 4, iclass 11, count 2 2006.257.13:29:31.04#ibcon#read 4, iclass 11, count 2 2006.257.13:29:31.04#ibcon#about to read 5, iclass 11, count 2 2006.257.13:29:31.04#ibcon#read 5, iclass 11, count 2 2006.257.13:29:31.04#ibcon#about to read 6, iclass 11, count 2 2006.257.13:29:31.04#ibcon#read 6, iclass 11, count 2 2006.257.13:29:31.04#ibcon#end of sib2, iclass 11, count 2 2006.257.13:29:31.04#ibcon#*after write, iclass 11, count 2 2006.257.13:29:31.04#ibcon#*before return 0, iclass 11, count 2 2006.257.13:29:31.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:31.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:31.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.13:29:31.04#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:31.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:31.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:31.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:31.16#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:29:31.16#ibcon#first serial, iclass 11, count 0 2006.257.13:29:31.16#ibcon#enter sib2, iclass 11, count 0 2006.257.13:29:31.16#ibcon#flushed, iclass 11, count 0 2006.257.13:29:31.16#ibcon#about to write, iclass 11, count 0 2006.257.13:29:31.16#ibcon#wrote, iclass 11, count 0 2006.257.13:29:31.16#ibcon#about to read 3, iclass 11, count 0 2006.257.13:29:31.18#ibcon#read 3, iclass 11, count 0 2006.257.13:29:31.18#ibcon#about to read 4, iclass 11, count 0 2006.257.13:29:31.18#ibcon#read 4, iclass 11, count 0 2006.257.13:29:31.18#ibcon#about to read 5, iclass 11, count 0 2006.257.13:29:31.18#ibcon#read 5, iclass 11, count 0 2006.257.13:29:31.18#ibcon#about to read 6, iclass 11, count 0 2006.257.13:29:31.18#ibcon#read 6, iclass 11, count 0 2006.257.13:29:31.18#ibcon#end of sib2, iclass 11, count 0 2006.257.13:29:31.18#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:29:31.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:29:31.18#ibcon#[25=USB\r\n] 2006.257.13:29:31.18#ibcon#*before write, iclass 11, count 0 2006.257.13:29:31.18#ibcon#enter sib2, iclass 11, count 0 2006.257.13:29:31.18#ibcon#flushed, iclass 11, count 0 2006.257.13:29:31.18#ibcon#about to write, iclass 11, count 0 2006.257.13:29:31.18#ibcon#wrote, iclass 11, count 0 2006.257.13:29:31.18#ibcon#about to read 3, iclass 11, count 0 2006.257.13:29:31.21#ibcon#read 3, iclass 11, count 0 2006.257.13:29:31.21#ibcon#about to read 4, iclass 11, count 0 2006.257.13:29:31.21#ibcon#read 4, iclass 11, count 0 2006.257.13:29:31.21#ibcon#about to read 5, iclass 11, count 0 2006.257.13:29:31.21#ibcon#read 5, iclass 11, count 0 2006.257.13:29:31.21#ibcon#about to read 6, iclass 11, count 0 2006.257.13:29:31.21#ibcon#read 6, iclass 11, count 0 2006.257.13:29:31.21#ibcon#end of sib2, iclass 11, count 0 2006.257.13:29:31.21#ibcon#*after write, iclass 11, count 0 2006.257.13:29:31.21#ibcon#*before return 0, iclass 11, count 0 2006.257.13:29:31.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:31.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:31.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:29:31.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:29:31.21$vck44/valo=4,624.99 2006.257.13:29:31.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:29:31.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:29:31.21#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:31.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:31.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:31.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:31.21#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:29:31.21#ibcon#first serial, iclass 13, count 0 2006.257.13:29:31.21#ibcon#enter sib2, iclass 13, count 0 2006.257.13:29:31.21#ibcon#flushed, iclass 13, count 0 2006.257.13:29:31.21#ibcon#about to write, iclass 13, count 0 2006.257.13:29:31.21#ibcon#wrote, iclass 13, count 0 2006.257.13:29:31.21#ibcon#about to read 3, iclass 13, count 0 2006.257.13:29:31.23#ibcon#read 3, iclass 13, count 0 2006.257.13:29:31.23#ibcon#about to read 4, iclass 13, count 0 2006.257.13:29:31.23#ibcon#read 4, iclass 13, count 0 2006.257.13:29:31.23#ibcon#about to read 5, iclass 13, count 0 2006.257.13:29:31.23#ibcon#read 5, iclass 13, count 0 2006.257.13:29:31.23#ibcon#about to read 6, iclass 13, count 0 2006.257.13:29:31.23#ibcon#read 6, iclass 13, count 0 2006.257.13:29:31.23#ibcon#end of sib2, iclass 13, count 0 2006.257.13:29:31.23#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:29:31.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:29:31.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:29:31.23#ibcon#*before write, iclass 13, count 0 2006.257.13:29:31.23#ibcon#enter sib2, iclass 13, count 0 2006.257.13:29:31.23#ibcon#flushed, iclass 13, count 0 2006.257.13:29:31.23#ibcon#about to write, iclass 13, count 0 2006.257.13:29:31.23#ibcon#wrote, iclass 13, count 0 2006.257.13:29:31.23#ibcon#about to read 3, iclass 13, count 0 2006.257.13:29:31.27#ibcon#read 3, iclass 13, count 0 2006.257.13:29:31.27#ibcon#about to read 4, iclass 13, count 0 2006.257.13:29:31.27#ibcon#read 4, iclass 13, count 0 2006.257.13:29:31.27#ibcon#about to read 5, iclass 13, count 0 2006.257.13:29:31.27#ibcon#read 5, iclass 13, count 0 2006.257.13:29:31.27#ibcon#about to read 6, iclass 13, count 0 2006.257.13:29:31.27#ibcon#read 6, iclass 13, count 0 2006.257.13:29:31.27#ibcon#end of sib2, iclass 13, count 0 2006.257.13:29:31.27#ibcon#*after write, iclass 13, count 0 2006.257.13:29:31.27#ibcon#*before return 0, iclass 13, count 0 2006.257.13:29:31.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:31.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:31.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:29:31.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:29:31.27$vck44/va=4,7 2006.257.13:29:31.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.13:29:31.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.13:29:31.27#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:31.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:31.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:31.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:31.33#ibcon#enter wrdev, iclass 15, count 2 2006.257.13:29:31.33#ibcon#first serial, iclass 15, count 2 2006.257.13:29:31.33#ibcon#enter sib2, iclass 15, count 2 2006.257.13:29:31.33#ibcon#flushed, iclass 15, count 2 2006.257.13:29:31.33#ibcon#about to write, iclass 15, count 2 2006.257.13:29:31.33#ibcon#wrote, iclass 15, count 2 2006.257.13:29:31.33#ibcon#about to read 3, iclass 15, count 2 2006.257.13:29:31.35#ibcon#read 3, iclass 15, count 2 2006.257.13:29:31.35#ibcon#about to read 4, iclass 15, count 2 2006.257.13:29:31.35#ibcon#read 4, iclass 15, count 2 2006.257.13:29:31.35#ibcon#about to read 5, iclass 15, count 2 2006.257.13:29:31.35#ibcon#read 5, iclass 15, count 2 2006.257.13:29:31.35#ibcon#about to read 6, iclass 15, count 2 2006.257.13:29:31.35#ibcon#read 6, iclass 15, count 2 2006.257.13:29:31.35#ibcon#end of sib2, iclass 15, count 2 2006.257.13:29:31.35#ibcon#*mode == 0, iclass 15, count 2 2006.257.13:29:31.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.13:29:31.35#ibcon#[25=AT04-07\r\n] 2006.257.13:29:31.35#ibcon#*before write, iclass 15, count 2 2006.257.13:29:31.35#ibcon#enter sib2, iclass 15, count 2 2006.257.13:29:31.35#ibcon#flushed, iclass 15, count 2 2006.257.13:29:31.35#ibcon#about to write, iclass 15, count 2 2006.257.13:29:31.35#ibcon#wrote, iclass 15, count 2 2006.257.13:29:31.35#ibcon#about to read 3, iclass 15, count 2 2006.257.13:29:31.38#ibcon#read 3, iclass 15, count 2 2006.257.13:29:31.38#ibcon#about to read 4, iclass 15, count 2 2006.257.13:29:31.38#ibcon#read 4, iclass 15, count 2 2006.257.13:29:31.38#ibcon#about to read 5, iclass 15, count 2 2006.257.13:29:31.38#ibcon#read 5, iclass 15, count 2 2006.257.13:29:31.38#ibcon#about to read 6, iclass 15, count 2 2006.257.13:29:31.38#ibcon#read 6, iclass 15, count 2 2006.257.13:29:31.38#ibcon#end of sib2, iclass 15, count 2 2006.257.13:29:31.38#ibcon#*after write, iclass 15, count 2 2006.257.13:29:31.38#ibcon#*before return 0, iclass 15, count 2 2006.257.13:29:31.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:31.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:31.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.13:29:31.38#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:31.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:31.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:31.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:31.50#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:29:31.50#ibcon#first serial, iclass 15, count 0 2006.257.13:29:31.50#ibcon#enter sib2, iclass 15, count 0 2006.257.13:29:31.50#ibcon#flushed, iclass 15, count 0 2006.257.13:29:31.50#ibcon#about to write, iclass 15, count 0 2006.257.13:29:31.50#ibcon#wrote, iclass 15, count 0 2006.257.13:29:31.50#ibcon#about to read 3, iclass 15, count 0 2006.257.13:29:31.52#ibcon#read 3, iclass 15, count 0 2006.257.13:29:31.52#ibcon#about to read 4, iclass 15, count 0 2006.257.13:29:31.52#ibcon#read 4, iclass 15, count 0 2006.257.13:29:31.52#ibcon#about to read 5, iclass 15, count 0 2006.257.13:29:31.52#ibcon#read 5, iclass 15, count 0 2006.257.13:29:31.52#ibcon#about to read 6, iclass 15, count 0 2006.257.13:29:31.52#ibcon#read 6, iclass 15, count 0 2006.257.13:29:31.52#ibcon#end of sib2, iclass 15, count 0 2006.257.13:29:31.52#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:29:31.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:29:31.52#ibcon#[25=USB\r\n] 2006.257.13:29:31.52#ibcon#*before write, iclass 15, count 0 2006.257.13:29:31.52#ibcon#enter sib2, iclass 15, count 0 2006.257.13:29:31.52#ibcon#flushed, iclass 15, count 0 2006.257.13:29:31.52#ibcon#about to write, iclass 15, count 0 2006.257.13:29:31.52#ibcon#wrote, iclass 15, count 0 2006.257.13:29:31.52#ibcon#about to read 3, iclass 15, count 0 2006.257.13:29:31.55#ibcon#read 3, iclass 15, count 0 2006.257.13:29:31.55#ibcon#about to read 4, iclass 15, count 0 2006.257.13:29:31.55#ibcon#read 4, iclass 15, count 0 2006.257.13:29:31.55#ibcon#about to read 5, iclass 15, count 0 2006.257.13:29:31.55#ibcon#read 5, iclass 15, count 0 2006.257.13:29:31.55#ibcon#about to read 6, iclass 15, count 0 2006.257.13:29:31.55#ibcon#read 6, iclass 15, count 0 2006.257.13:29:31.55#ibcon#end of sib2, iclass 15, count 0 2006.257.13:29:31.55#ibcon#*after write, iclass 15, count 0 2006.257.13:29:31.55#ibcon#*before return 0, iclass 15, count 0 2006.257.13:29:31.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:31.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:31.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:29:31.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:29:31.55$vck44/valo=5,734.99 2006.257.13:29:31.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.13:29:31.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.13:29:31.55#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:31.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:31.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:31.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:31.55#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:29:31.55#ibcon#first serial, iclass 17, count 0 2006.257.13:29:31.55#ibcon#enter sib2, iclass 17, count 0 2006.257.13:29:31.55#ibcon#flushed, iclass 17, count 0 2006.257.13:29:31.55#ibcon#about to write, iclass 17, count 0 2006.257.13:29:31.55#ibcon#wrote, iclass 17, count 0 2006.257.13:29:31.55#ibcon#about to read 3, iclass 17, count 0 2006.257.13:29:31.57#ibcon#read 3, iclass 17, count 0 2006.257.13:29:31.57#ibcon#about to read 4, iclass 17, count 0 2006.257.13:29:31.57#ibcon#read 4, iclass 17, count 0 2006.257.13:29:31.57#ibcon#about to read 5, iclass 17, count 0 2006.257.13:29:31.57#ibcon#read 5, iclass 17, count 0 2006.257.13:29:31.57#ibcon#about to read 6, iclass 17, count 0 2006.257.13:29:31.57#ibcon#read 6, iclass 17, count 0 2006.257.13:29:31.57#ibcon#end of sib2, iclass 17, count 0 2006.257.13:29:31.57#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:29:31.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:29:31.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:29:31.57#ibcon#*before write, iclass 17, count 0 2006.257.13:29:31.57#ibcon#enter sib2, iclass 17, count 0 2006.257.13:29:31.57#ibcon#flushed, iclass 17, count 0 2006.257.13:29:31.57#ibcon#about to write, iclass 17, count 0 2006.257.13:29:31.57#ibcon#wrote, iclass 17, count 0 2006.257.13:29:31.57#ibcon#about to read 3, iclass 17, count 0 2006.257.13:29:31.61#ibcon#read 3, iclass 17, count 0 2006.257.13:29:31.61#ibcon#about to read 4, iclass 17, count 0 2006.257.13:29:31.61#ibcon#read 4, iclass 17, count 0 2006.257.13:29:31.61#ibcon#about to read 5, iclass 17, count 0 2006.257.13:29:31.61#ibcon#read 5, iclass 17, count 0 2006.257.13:29:31.61#ibcon#about to read 6, iclass 17, count 0 2006.257.13:29:31.61#ibcon#read 6, iclass 17, count 0 2006.257.13:29:31.61#ibcon#end of sib2, iclass 17, count 0 2006.257.13:29:31.61#ibcon#*after write, iclass 17, count 0 2006.257.13:29:31.61#ibcon#*before return 0, iclass 17, count 0 2006.257.13:29:31.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:31.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:31.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:29:31.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:29:31.61$vck44/va=5,4 2006.257.13:29:31.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.13:29:31.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.13:29:31.61#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:31.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:31.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:31.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:31.67#ibcon#enter wrdev, iclass 19, count 2 2006.257.13:29:31.67#ibcon#first serial, iclass 19, count 2 2006.257.13:29:31.67#ibcon#enter sib2, iclass 19, count 2 2006.257.13:29:31.67#ibcon#flushed, iclass 19, count 2 2006.257.13:29:31.67#ibcon#about to write, iclass 19, count 2 2006.257.13:29:31.67#ibcon#wrote, iclass 19, count 2 2006.257.13:29:31.67#ibcon#about to read 3, iclass 19, count 2 2006.257.13:29:31.69#ibcon#read 3, iclass 19, count 2 2006.257.13:29:31.69#ibcon#about to read 4, iclass 19, count 2 2006.257.13:29:31.69#ibcon#read 4, iclass 19, count 2 2006.257.13:29:31.69#ibcon#about to read 5, iclass 19, count 2 2006.257.13:29:31.69#ibcon#read 5, iclass 19, count 2 2006.257.13:29:31.69#ibcon#about to read 6, iclass 19, count 2 2006.257.13:29:31.69#ibcon#read 6, iclass 19, count 2 2006.257.13:29:31.69#ibcon#end of sib2, iclass 19, count 2 2006.257.13:29:31.69#ibcon#*mode == 0, iclass 19, count 2 2006.257.13:29:31.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.13:29:31.69#ibcon#[25=AT05-04\r\n] 2006.257.13:29:31.69#ibcon#*before write, iclass 19, count 2 2006.257.13:29:31.69#ibcon#enter sib2, iclass 19, count 2 2006.257.13:29:31.69#ibcon#flushed, iclass 19, count 2 2006.257.13:29:31.69#ibcon#about to write, iclass 19, count 2 2006.257.13:29:31.69#ibcon#wrote, iclass 19, count 2 2006.257.13:29:31.69#ibcon#about to read 3, iclass 19, count 2 2006.257.13:29:31.72#ibcon#read 3, iclass 19, count 2 2006.257.13:29:31.72#ibcon#about to read 4, iclass 19, count 2 2006.257.13:29:31.72#ibcon#read 4, iclass 19, count 2 2006.257.13:29:31.72#ibcon#about to read 5, iclass 19, count 2 2006.257.13:29:31.72#ibcon#read 5, iclass 19, count 2 2006.257.13:29:31.72#ibcon#about to read 6, iclass 19, count 2 2006.257.13:29:31.72#ibcon#read 6, iclass 19, count 2 2006.257.13:29:31.72#ibcon#end of sib2, iclass 19, count 2 2006.257.13:29:31.72#ibcon#*after write, iclass 19, count 2 2006.257.13:29:31.72#ibcon#*before return 0, iclass 19, count 2 2006.257.13:29:31.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:31.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:31.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.13:29:31.72#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:31.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:31.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:31.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:31.84#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:29:31.84#ibcon#first serial, iclass 19, count 0 2006.257.13:29:31.84#ibcon#enter sib2, iclass 19, count 0 2006.257.13:29:31.84#ibcon#flushed, iclass 19, count 0 2006.257.13:29:31.84#ibcon#about to write, iclass 19, count 0 2006.257.13:29:31.84#ibcon#wrote, iclass 19, count 0 2006.257.13:29:31.84#ibcon#about to read 3, iclass 19, count 0 2006.257.13:29:31.86#ibcon#read 3, iclass 19, count 0 2006.257.13:29:31.86#ibcon#about to read 4, iclass 19, count 0 2006.257.13:29:31.86#ibcon#read 4, iclass 19, count 0 2006.257.13:29:31.86#ibcon#about to read 5, iclass 19, count 0 2006.257.13:29:31.86#ibcon#read 5, iclass 19, count 0 2006.257.13:29:31.86#ibcon#about to read 6, iclass 19, count 0 2006.257.13:29:31.86#ibcon#read 6, iclass 19, count 0 2006.257.13:29:31.86#ibcon#end of sib2, iclass 19, count 0 2006.257.13:29:31.86#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:29:31.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:29:31.86#ibcon#[25=USB\r\n] 2006.257.13:29:31.86#ibcon#*before write, iclass 19, count 0 2006.257.13:29:31.86#ibcon#enter sib2, iclass 19, count 0 2006.257.13:29:31.86#ibcon#flushed, iclass 19, count 0 2006.257.13:29:31.86#ibcon#about to write, iclass 19, count 0 2006.257.13:29:31.86#ibcon#wrote, iclass 19, count 0 2006.257.13:29:31.86#ibcon#about to read 3, iclass 19, count 0 2006.257.13:29:31.89#ibcon#read 3, iclass 19, count 0 2006.257.13:29:31.89#ibcon#about to read 4, iclass 19, count 0 2006.257.13:29:31.89#ibcon#read 4, iclass 19, count 0 2006.257.13:29:31.89#ibcon#about to read 5, iclass 19, count 0 2006.257.13:29:31.89#ibcon#read 5, iclass 19, count 0 2006.257.13:29:31.89#ibcon#about to read 6, iclass 19, count 0 2006.257.13:29:31.89#ibcon#read 6, iclass 19, count 0 2006.257.13:29:31.89#ibcon#end of sib2, iclass 19, count 0 2006.257.13:29:31.89#ibcon#*after write, iclass 19, count 0 2006.257.13:29:31.89#ibcon#*before return 0, iclass 19, count 0 2006.257.13:29:31.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:31.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:31.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:29:31.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:29:31.89$vck44/valo=6,814.99 2006.257.13:29:31.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.13:29:31.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.13:29:31.89#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:31.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:31.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:31.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:31.89#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:29:31.89#ibcon#first serial, iclass 21, count 0 2006.257.13:29:31.89#ibcon#enter sib2, iclass 21, count 0 2006.257.13:29:31.89#ibcon#flushed, iclass 21, count 0 2006.257.13:29:31.89#ibcon#about to write, iclass 21, count 0 2006.257.13:29:31.89#ibcon#wrote, iclass 21, count 0 2006.257.13:29:31.89#ibcon#about to read 3, iclass 21, count 0 2006.257.13:29:31.91#ibcon#read 3, iclass 21, count 0 2006.257.13:29:31.91#ibcon#about to read 4, iclass 21, count 0 2006.257.13:29:31.91#ibcon#read 4, iclass 21, count 0 2006.257.13:29:31.91#ibcon#about to read 5, iclass 21, count 0 2006.257.13:29:31.91#ibcon#read 5, iclass 21, count 0 2006.257.13:29:31.91#ibcon#about to read 6, iclass 21, count 0 2006.257.13:29:31.91#ibcon#read 6, iclass 21, count 0 2006.257.13:29:31.91#ibcon#end of sib2, iclass 21, count 0 2006.257.13:29:31.91#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:29:31.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:29:31.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:29:31.91#ibcon#*before write, iclass 21, count 0 2006.257.13:29:31.91#ibcon#enter sib2, iclass 21, count 0 2006.257.13:29:31.91#ibcon#flushed, iclass 21, count 0 2006.257.13:29:31.91#ibcon#about to write, iclass 21, count 0 2006.257.13:29:31.91#ibcon#wrote, iclass 21, count 0 2006.257.13:29:31.91#ibcon#about to read 3, iclass 21, count 0 2006.257.13:29:31.95#ibcon#read 3, iclass 21, count 0 2006.257.13:29:31.95#ibcon#about to read 4, iclass 21, count 0 2006.257.13:29:31.95#ibcon#read 4, iclass 21, count 0 2006.257.13:29:31.95#ibcon#about to read 5, iclass 21, count 0 2006.257.13:29:31.95#ibcon#read 5, iclass 21, count 0 2006.257.13:29:31.95#ibcon#about to read 6, iclass 21, count 0 2006.257.13:29:31.95#ibcon#read 6, iclass 21, count 0 2006.257.13:29:31.95#ibcon#end of sib2, iclass 21, count 0 2006.257.13:29:31.95#ibcon#*after write, iclass 21, count 0 2006.257.13:29:31.95#ibcon#*before return 0, iclass 21, count 0 2006.257.13:29:31.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:31.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:31.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:29:31.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:29:31.95$vck44/va=6,4 2006.257.13:29:31.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.13:29:31.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.13:29:31.95#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:31.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:32.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:32.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:32.01#ibcon#enter wrdev, iclass 23, count 2 2006.257.13:29:32.01#ibcon#first serial, iclass 23, count 2 2006.257.13:29:32.01#ibcon#enter sib2, iclass 23, count 2 2006.257.13:29:32.01#ibcon#flushed, iclass 23, count 2 2006.257.13:29:32.01#ibcon#about to write, iclass 23, count 2 2006.257.13:29:32.01#ibcon#wrote, iclass 23, count 2 2006.257.13:29:32.01#ibcon#about to read 3, iclass 23, count 2 2006.257.13:29:32.03#ibcon#read 3, iclass 23, count 2 2006.257.13:29:32.03#ibcon#about to read 4, iclass 23, count 2 2006.257.13:29:32.03#ibcon#read 4, iclass 23, count 2 2006.257.13:29:32.03#ibcon#about to read 5, iclass 23, count 2 2006.257.13:29:32.03#ibcon#read 5, iclass 23, count 2 2006.257.13:29:32.03#ibcon#about to read 6, iclass 23, count 2 2006.257.13:29:32.03#ibcon#read 6, iclass 23, count 2 2006.257.13:29:32.03#ibcon#end of sib2, iclass 23, count 2 2006.257.13:29:32.03#ibcon#*mode == 0, iclass 23, count 2 2006.257.13:29:32.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.13:29:32.03#ibcon#[25=AT06-04\r\n] 2006.257.13:29:32.03#ibcon#*before write, iclass 23, count 2 2006.257.13:29:32.03#ibcon#enter sib2, iclass 23, count 2 2006.257.13:29:32.03#ibcon#flushed, iclass 23, count 2 2006.257.13:29:32.03#ibcon#about to write, iclass 23, count 2 2006.257.13:29:32.03#ibcon#wrote, iclass 23, count 2 2006.257.13:29:32.03#ibcon#about to read 3, iclass 23, count 2 2006.257.13:29:32.06#ibcon#read 3, iclass 23, count 2 2006.257.13:29:32.06#ibcon#about to read 4, iclass 23, count 2 2006.257.13:29:32.06#ibcon#read 4, iclass 23, count 2 2006.257.13:29:32.06#ibcon#about to read 5, iclass 23, count 2 2006.257.13:29:32.06#ibcon#read 5, iclass 23, count 2 2006.257.13:29:32.06#ibcon#about to read 6, iclass 23, count 2 2006.257.13:29:32.06#ibcon#read 6, iclass 23, count 2 2006.257.13:29:32.06#ibcon#end of sib2, iclass 23, count 2 2006.257.13:29:32.06#ibcon#*after write, iclass 23, count 2 2006.257.13:29:32.06#ibcon#*before return 0, iclass 23, count 2 2006.257.13:29:32.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:32.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:32.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.13:29:32.06#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:32.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:32.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:32.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:32.18#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:29:32.18#ibcon#first serial, iclass 23, count 0 2006.257.13:29:32.18#ibcon#enter sib2, iclass 23, count 0 2006.257.13:29:32.18#ibcon#flushed, iclass 23, count 0 2006.257.13:29:32.18#ibcon#about to write, iclass 23, count 0 2006.257.13:29:32.18#ibcon#wrote, iclass 23, count 0 2006.257.13:29:32.18#ibcon#about to read 3, iclass 23, count 0 2006.257.13:29:32.20#ibcon#read 3, iclass 23, count 0 2006.257.13:29:32.20#ibcon#about to read 4, iclass 23, count 0 2006.257.13:29:32.20#ibcon#read 4, iclass 23, count 0 2006.257.13:29:32.20#ibcon#about to read 5, iclass 23, count 0 2006.257.13:29:32.20#ibcon#read 5, iclass 23, count 0 2006.257.13:29:32.20#ibcon#about to read 6, iclass 23, count 0 2006.257.13:29:32.20#ibcon#read 6, iclass 23, count 0 2006.257.13:29:32.20#ibcon#end of sib2, iclass 23, count 0 2006.257.13:29:32.20#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:29:32.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:29:32.20#ibcon#[25=USB\r\n] 2006.257.13:29:32.20#ibcon#*before write, iclass 23, count 0 2006.257.13:29:32.20#ibcon#enter sib2, iclass 23, count 0 2006.257.13:29:32.20#ibcon#flushed, iclass 23, count 0 2006.257.13:29:32.20#ibcon#about to write, iclass 23, count 0 2006.257.13:29:32.20#ibcon#wrote, iclass 23, count 0 2006.257.13:29:32.20#ibcon#about to read 3, iclass 23, count 0 2006.257.13:29:32.23#ibcon#read 3, iclass 23, count 0 2006.257.13:29:32.23#ibcon#about to read 4, iclass 23, count 0 2006.257.13:29:32.23#ibcon#read 4, iclass 23, count 0 2006.257.13:29:32.23#ibcon#about to read 5, iclass 23, count 0 2006.257.13:29:32.23#ibcon#read 5, iclass 23, count 0 2006.257.13:29:32.23#ibcon#about to read 6, iclass 23, count 0 2006.257.13:29:32.23#ibcon#read 6, iclass 23, count 0 2006.257.13:29:32.23#ibcon#end of sib2, iclass 23, count 0 2006.257.13:29:32.23#ibcon#*after write, iclass 23, count 0 2006.257.13:29:32.23#ibcon#*before return 0, iclass 23, count 0 2006.257.13:29:32.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:32.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:32.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:29:32.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:29:32.23$vck44/valo=7,864.99 2006.257.13:29:32.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.13:29:32.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.13:29:32.23#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:32.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:32.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:32.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:32.23#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:29:32.23#ibcon#first serial, iclass 25, count 0 2006.257.13:29:32.23#ibcon#enter sib2, iclass 25, count 0 2006.257.13:29:32.23#ibcon#flushed, iclass 25, count 0 2006.257.13:29:32.23#ibcon#about to write, iclass 25, count 0 2006.257.13:29:32.23#ibcon#wrote, iclass 25, count 0 2006.257.13:29:32.23#ibcon#about to read 3, iclass 25, count 0 2006.257.13:29:32.25#ibcon#read 3, iclass 25, count 0 2006.257.13:29:32.25#ibcon#about to read 4, iclass 25, count 0 2006.257.13:29:32.25#ibcon#read 4, iclass 25, count 0 2006.257.13:29:32.25#ibcon#about to read 5, iclass 25, count 0 2006.257.13:29:32.25#ibcon#read 5, iclass 25, count 0 2006.257.13:29:32.25#ibcon#about to read 6, iclass 25, count 0 2006.257.13:29:32.25#ibcon#read 6, iclass 25, count 0 2006.257.13:29:32.25#ibcon#end of sib2, iclass 25, count 0 2006.257.13:29:32.25#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:29:32.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:29:32.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:29:32.25#ibcon#*before write, iclass 25, count 0 2006.257.13:29:32.25#ibcon#enter sib2, iclass 25, count 0 2006.257.13:29:32.25#ibcon#flushed, iclass 25, count 0 2006.257.13:29:32.25#ibcon#about to write, iclass 25, count 0 2006.257.13:29:32.25#ibcon#wrote, iclass 25, count 0 2006.257.13:29:32.25#ibcon#about to read 3, iclass 25, count 0 2006.257.13:29:32.29#ibcon#read 3, iclass 25, count 0 2006.257.13:29:32.29#ibcon#about to read 4, iclass 25, count 0 2006.257.13:29:32.29#ibcon#read 4, iclass 25, count 0 2006.257.13:29:32.29#ibcon#about to read 5, iclass 25, count 0 2006.257.13:29:32.29#ibcon#read 5, iclass 25, count 0 2006.257.13:29:32.29#ibcon#about to read 6, iclass 25, count 0 2006.257.13:29:32.29#ibcon#read 6, iclass 25, count 0 2006.257.13:29:32.29#ibcon#end of sib2, iclass 25, count 0 2006.257.13:29:32.29#ibcon#*after write, iclass 25, count 0 2006.257.13:29:32.29#ibcon#*before return 0, iclass 25, count 0 2006.257.13:29:32.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:32.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:32.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:29:32.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:29:32.29$vck44/va=7,4 2006.257.13:29:32.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.13:29:32.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.13:29:32.29#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:32.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:32.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:32.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:32.35#ibcon#enter wrdev, iclass 27, count 2 2006.257.13:29:32.35#ibcon#first serial, iclass 27, count 2 2006.257.13:29:32.35#ibcon#enter sib2, iclass 27, count 2 2006.257.13:29:32.35#ibcon#flushed, iclass 27, count 2 2006.257.13:29:32.35#ibcon#about to write, iclass 27, count 2 2006.257.13:29:32.35#ibcon#wrote, iclass 27, count 2 2006.257.13:29:32.35#ibcon#about to read 3, iclass 27, count 2 2006.257.13:29:32.37#ibcon#read 3, iclass 27, count 2 2006.257.13:29:32.37#ibcon#about to read 4, iclass 27, count 2 2006.257.13:29:32.37#ibcon#read 4, iclass 27, count 2 2006.257.13:29:32.37#ibcon#about to read 5, iclass 27, count 2 2006.257.13:29:32.37#ibcon#read 5, iclass 27, count 2 2006.257.13:29:32.37#ibcon#about to read 6, iclass 27, count 2 2006.257.13:29:32.37#ibcon#read 6, iclass 27, count 2 2006.257.13:29:32.37#ibcon#end of sib2, iclass 27, count 2 2006.257.13:29:32.37#ibcon#*mode == 0, iclass 27, count 2 2006.257.13:29:32.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.13:29:32.37#ibcon#[25=AT07-04\r\n] 2006.257.13:29:32.37#ibcon#*before write, iclass 27, count 2 2006.257.13:29:32.37#ibcon#enter sib2, iclass 27, count 2 2006.257.13:29:32.37#ibcon#flushed, iclass 27, count 2 2006.257.13:29:32.37#ibcon#about to write, iclass 27, count 2 2006.257.13:29:32.37#ibcon#wrote, iclass 27, count 2 2006.257.13:29:32.37#ibcon#about to read 3, iclass 27, count 2 2006.257.13:29:32.40#ibcon#read 3, iclass 27, count 2 2006.257.13:29:32.40#ibcon#about to read 4, iclass 27, count 2 2006.257.13:29:32.40#ibcon#read 4, iclass 27, count 2 2006.257.13:29:32.40#ibcon#about to read 5, iclass 27, count 2 2006.257.13:29:32.40#ibcon#read 5, iclass 27, count 2 2006.257.13:29:32.40#ibcon#about to read 6, iclass 27, count 2 2006.257.13:29:32.40#ibcon#read 6, iclass 27, count 2 2006.257.13:29:32.40#ibcon#end of sib2, iclass 27, count 2 2006.257.13:29:32.40#ibcon#*after write, iclass 27, count 2 2006.257.13:29:32.40#ibcon#*before return 0, iclass 27, count 2 2006.257.13:29:32.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:32.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:32.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.13:29:32.40#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:32.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:32.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:32.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:32.52#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:29:32.52#ibcon#first serial, iclass 27, count 0 2006.257.13:29:32.52#ibcon#enter sib2, iclass 27, count 0 2006.257.13:29:32.52#ibcon#flushed, iclass 27, count 0 2006.257.13:29:32.52#ibcon#about to write, iclass 27, count 0 2006.257.13:29:32.52#ibcon#wrote, iclass 27, count 0 2006.257.13:29:32.52#ibcon#about to read 3, iclass 27, count 0 2006.257.13:29:32.54#ibcon#read 3, iclass 27, count 0 2006.257.13:29:32.54#ibcon#about to read 4, iclass 27, count 0 2006.257.13:29:32.54#ibcon#read 4, iclass 27, count 0 2006.257.13:29:32.54#ibcon#about to read 5, iclass 27, count 0 2006.257.13:29:32.54#ibcon#read 5, iclass 27, count 0 2006.257.13:29:32.54#ibcon#about to read 6, iclass 27, count 0 2006.257.13:29:32.54#ibcon#read 6, iclass 27, count 0 2006.257.13:29:32.54#ibcon#end of sib2, iclass 27, count 0 2006.257.13:29:32.54#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:29:32.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:29:32.54#ibcon#[25=USB\r\n] 2006.257.13:29:32.54#ibcon#*before write, iclass 27, count 0 2006.257.13:29:32.54#ibcon#enter sib2, iclass 27, count 0 2006.257.13:29:32.54#ibcon#flushed, iclass 27, count 0 2006.257.13:29:32.54#ibcon#about to write, iclass 27, count 0 2006.257.13:29:32.54#ibcon#wrote, iclass 27, count 0 2006.257.13:29:32.54#ibcon#about to read 3, iclass 27, count 0 2006.257.13:29:32.57#ibcon#read 3, iclass 27, count 0 2006.257.13:29:32.57#ibcon#about to read 4, iclass 27, count 0 2006.257.13:29:32.57#ibcon#read 4, iclass 27, count 0 2006.257.13:29:32.57#ibcon#about to read 5, iclass 27, count 0 2006.257.13:29:32.57#ibcon#read 5, iclass 27, count 0 2006.257.13:29:32.57#ibcon#about to read 6, iclass 27, count 0 2006.257.13:29:32.57#ibcon#read 6, iclass 27, count 0 2006.257.13:29:32.57#ibcon#end of sib2, iclass 27, count 0 2006.257.13:29:32.57#ibcon#*after write, iclass 27, count 0 2006.257.13:29:32.57#ibcon#*before return 0, iclass 27, count 0 2006.257.13:29:32.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:32.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:32.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:29:32.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:29:32.57$vck44/valo=8,884.99 2006.257.13:29:32.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.13:29:32.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.13:29:32.57#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:32.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:29:32.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:29:32.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:29:32.57#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:29:32.57#ibcon#first serial, iclass 30, count 0 2006.257.13:29:32.57#ibcon#enter sib2, iclass 30, count 0 2006.257.13:29:32.57#ibcon#flushed, iclass 30, count 0 2006.257.13:29:32.57#ibcon#about to write, iclass 30, count 0 2006.257.13:29:32.57#ibcon#wrote, iclass 30, count 0 2006.257.13:29:32.57#ibcon#about to read 3, iclass 30, count 0 2006.257.13:29:32.59#ibcon#read 3, iclass 30, count 0 2006.257.13:29:32.59#ibcon#about to read 4, iclass 30, count 0 2006.257.13:29:32.59#ibcon#read 4, iclass 30, count 0 2006.257.13:29:32.59#ibcon#about to read 5, iclass 30, count 0 2006.257.13:29:32.59#ibcon#read 5, iclass 30, count 0 2006.257.13:29:32.59#ibcon#about to read 6, iclass 30, count 0 2006.257.13:29:32.59#ibcon#read 6, iclass 30, count 0 2006.257.13:29:32.59#ibcon#end of sib2, iclass 30, count 0 2006.257.13:29:32.59#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:29:32.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:29:32.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:29:32.59#ibcon#*before write, iclass 30, count 0 2006.257.13:29:32.59#ibcon#enter sib2, iclass 30, count 0 2006.257.13:29:32.59#ibcon#flushed, iclass 30, count 0 2006.257.13:29:32.59#ibcon#about to write, iclass 30, count 0 2006.257.13:29:32.59#ibcon#wrote, iclass 30, count 0 2006.257.13:29:32.59#ibcon#about to read 3, iclass 30, count 0 2006.257.13:29:32.59#abcon#<5=/14 1.1 2.9 17.51 971013.9\r\n> 2006.257.13:29:32.61#abcon#{5=INTERFACE CLEAR} 2006.257.13:29:32.63#ibcon#read 3, iclass 30, count 0 2006.257.13:29:32.63#ibcon#about to read 4, iclass 30, count 0 2006.257.13:29:32.63#ibcon#read 4, iclass 30, count 0 2006.257.13:29:32.63#ibcon#about to read 5, iclass 30, count 0 2006.257.13:29:32.63#ibcon#read 5, iclass 30, count 0 2006.257.13:29:32.63#ibcon#about to read 6, iclass 30, count 0 2006.257.13:29:32.63#ibcon#read 6, iclass 30, count 0 2006.257.13:29:32.63#ibcon#end of sib2, iclass 30, count 0 2006.257.13:29:32.63#ibcon#*after write, iclass 30, count 0 2006.257.13:29:32.63#ibcon#*before return 0, iclass 30, count 0 2006.257.13:29:32.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:29:32.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:29:32.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:29:32.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:29:32.63$vck44/va=8,4 2006.257.13:29:32.63#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.13:29:32.63#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.13:29:32.63#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:32.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:29:32.67#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:29:32.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:29:32.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:29:32.69#ibcon#enter wrdev, iclass 34, count 2 2006.257.13:29:32.69#ibcon#first serial, iclass 34, count 2 2006.257.13:29:32.69#ibcon#enter sib2, iclass 34, count 2 2006.257.13:29:32.69#ibcon#flushed, iclass 34, count 2 2006.257.13:29:32.69#ibcon#about to write, iclass 34, count 2 2006.257.13:29:32.69#ibcon#wrote, iclass 34, count 2 2006.257.13:29:32.69#ibcon#about to read 3, iclass 34, count 2 2006.257.13:29:32.71#ibcon#read 3, iclass 34, count 2 2006.257.13:29:32.71#ibcon#about to read 4, iclass 34, count 2 2006.257.13:29:32.71#ibcon#read 4, iclass 34, count 2 2006.257.13:29:32.71#ibcon#about to read 5, iclass 34, count 2 2006.257.13:29:32.71#ibcon#read 5, iclass 34, count 2 2006.257.13:29:32.71#ibcon#about to read 6, iclass 34, count 2 2006.257.13:29:32.71#ibcon#read 6, iclass 34, count 2 2006.257.13:29:32.71#ibcon#end of sib2, iclass 34, count 2 2006.257.13:29:32.71#ibcon#*mode == 0, iclass 34, count 2 2006.257.13:29:32.71#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.13:29:32.71#ibcon#[25=AT08-04\r\n] 2006.257.13:29:32.71#ibcon#*before write, iclass 34, count 2 2006.257.13:29:32.71#ibcon#enter sib2, iclass 34, count 2 2006.257.13:29:32.71#ibcon#flushed, iclass 34, count 2 2006.257.13:29:32.71#ibcon#about to write, iclass 34, count 2 2006.257.13:29:32.71#ibcon#wrote, iclass 34, count 2 2006.257.13:29:32.71#ibcon#about to read 3, iclass 34, count 2 2006.257.13:29:32.74#ibcon#read 3, iclass 34, count 2 2006.257.13:29:32.74#ibcon#about to read 4, iclass 34, count 2 2006.257.13:29:32.74#ibcon#read 4, iclass 34, count 2 2006.257.13:29:32.74#ibcon#about to read 5, iclass 34, count 2 2006.257.13:29:32.74#ibcon#read 5, iclass 34, count 2 2006.257.13:29:32.74#ibcon#about to read 6, iclass 34, count 2 2006.257.13:29:32.74#ibcon#read 6, iclass 34, count 2 2006.257.13:29:32.74#ibcon#end of sib2, iclass 34, count 2 2006.257.13:29:32.74#ibcon#*after write, iclass 34, count 2 2006.257.13:29:32.74#ibcon#*before return 0, iclass 34, count 2 2006.257.13:29:32.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:29:32.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:29:32.74#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.13:29:32.74#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:32.74#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:29:32.86#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:29:32.86#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:29:32.86#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:29:32.86#ibcon#first serial, iclass 34, count 0 2006.257.13:29:32.86#ibcon#enter sib2, iclass 34, count 0 2006.257.13:29:32.86#ibcon#flushed, iclass 34, count 0 2006.257.13:29:32.86#ibcon#about to write, iclass 34, count 0 2006.257.13:29:32.86#ibcon#wrote, iclass 34, count 0 2006.257.13:29:32.86#ibcon#about to read 3, iclass 34, count 0 2006.257.13:29:32.88#ibcon#read 3, iclass 34, count 0 2006.257.13:29:32.88#ibcon#about to read 4, iclass 34, count 0 2006.257.13:29:32.88#ibcon#read 4, iclass 34, count 0 2006.257.13:29:32.88#ibcon#about to read 5, iclass 34, count 0 2006.257.13:29:32.88#ibcon#read 5, iclass 34, count 0 2006.257.13:29:32.88#ibcon#about to read 6, iclass 34, count 0 2006.257.13:29:32.88#ibcon#read 6, iclass 34, count 0 2006.257.13:29:32.88#ibcon#end of sib2, iclass 34, count 0 2006.257.13:29:32.88#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:29:32.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:29:32.88#ibcon#[25=USB\r\n] 2006.257.13:29:32.88#ibcon#*before write, iclass 34, count 0 2006.257.13:29:32.88#ibcon#enter sib2, iclass 34, count 0 2006.257.13:29:32.88#ibcon#flushed, iclass 34, count 0 2006.257.13:29:32.88#ibcon#about to write, iclass 34, count 0 2006.257.13:29:32.88#ibcon#wrote, iclass 34, count 0 2006.257.13:29:32.88#ibcon#about to read 3, iclass 34, count 0 2006.257.13:29:32.91#ibcon#read 3, iclass 34, count 0 2006.257.13:29:32.91#ibcon#about to read 4, iclass 34, count 0 2006.257.13:29:32.91#ibcon#read 4, iclass 34, count 0 2006.257.13:29:32.91#ibcon#about to read 5, iclass 34, count 0 2006.257.13:29:32.91#ibcon#read 5, iclass 34, count 0 2006.257.13:29:32.91#ibcon#about to read 6, iclass 34, count 0 2006.257.13:29:32.91#ibcon#read 6, iclass 34, count 0 2006.257.13:29:32.91#ibcon#end of sib2, iclass 34, count 0 2006.257.13:29:32.91#ibcon#*after write, iclass 34, count 0 2006.257.13:29:32.91#ibcon#*before return 0, iclass 34, count 0 2006.257.13:29:32.91#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:29:32.91#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:29:32.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:29:32.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:29:32.91$vck44/vblo=1,629.99 2006.257.13:29:32.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.13:29:32.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.13:29:32.91#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:32.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:32.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:32.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:32.91#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:29:32.91#ibcon#first serial, iclass 37, count 0 2006.257.13:29:32.91#ibcon#enter sib2, iclass 37, count 0 2006.257.13:29:32.91#ibcon#flushed, iclass 37, count 0 2006.257.13:29:32.91#ibcon#about to write, iclass 37, count 0 2006.257.13:29:32.91#ibcon#wrote, iclass 37, count 0 2006.257.13:29:32.91#ibcon#about to read 3, iclass 37, count 0 2006.257.13:29:32.93#ibcon#read 3, iclass 37, count 0 2006.257.13:29:32.93#ibcon#about to read 4, iclass 37, count 0 2006.257.13:29:32.93#ibcon#read 4, iclass 37, count 0 2006.257.13:29:32.93#ibcon#about to read 5, iclass 37, count 0 2006.257.13:29:32.93#ibcon#read 5, iclass 37, count 0 2006.257.13:29:32.93#ibcon#about to read 6, iclass 37, count 0 2006.257.13:29:32.93#ibcon#read 6, iclass 37, count 0 2006.257.13:29:32.93#ibcon#end of sib2, iclass 37, count 0 2006.257.13:29:32.93#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:29:32.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:29:32.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:29:32.93#ibcon#*before write, iclass 37, count 0 2006.257.13:29:32.93#ibcon#enter sib2, iclass 37, count 0 2006.257.13:29:32.93#ibcon#flushed, iclass 37, count 0 2006.257.13:29:32.93#ibcon#about to write, iclass 37, count 0 2006.257.13:29:32.93#ibcon#wrote, iclass 37, count 0 2006.257.13:29:32.93#ibcon#about to read 3, iclass 37, count 0 2006.257.13:29:32.97#ibcon#read 3, iclass 37, count 0 2006.257.13:29:32.97#ibcon#about to read 4, iclass 37, count 0 2006.257.13:29:32.97#ibcon#read 4, iclass 37, count 0 2006.257.13:29:32.97#ibcon#about to read 5, iclass 37, count 0 2006.257.13:29:32.97#ibcon#read 5, iclass 37, count 0 2006.257.13:29:32.97#ibcon#about to read 6, iclass 37, count 0 2006.257.13:29:32.97#ibcon#read 6, iclass 37, count 0 2006.257.13:29:32.97#ibcon#end of sib2, iclass 37, count 0 2006.257.13:29:32.97#ibcon#*after write, iclass 37, count 0 2006.257.13:29:32.97#ibcon#*before return 0, iclass 37, count 0 2006.257.13:29:32.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:32.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:29:32.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:29:32.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:29:32.97$vck44/vb=1,4 2006.257.13:29:32.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.13:29:32.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.13:29:32.97#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:32.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:32.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:32.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:32.97#ibcon#enter wrdev, iclass 39, count 2 2006.257.13:29:32.97#ibcon#first serial, iclass 39, count 2 2006.257.13:29:32.97#ibcon#enter sib2, iclass 39, count 2 2006.257.13:29:32.97#ibcon#flushed, iclass 39, count 2 2006.257.13:29:32.97#ibcon#about to write, iclass 39, count 2 2006.257.13:29:32.97#ibcon#wrote, iclass 39, count 2 2006.257.13:29:32.97#ibcon#about to read 3, iclass 39, count 2 2006.257.13:29:32.99#ibcon#read 3, iclass 39, count 2 2006.257.13:29:32.99#ibcon#about to read 4, iclass 39, count 2 2006.257.13:29:32.99#ibcon#read 4, iclass 39, count 2 2006.257.13:29:32.99#ibcon#about to read 5, iclass 39, count 2 2006.257.13:29:32.99#ibcon#read 5, iclass 39, count 2 2006.257.13:29:32.99#ibcon#about to read 6, iclass 39, count 2 2006.257.13:29:32.99#ibcon#read 6, iclass 39, count 2 2006.257.13:29:32.99#ibcon#end of sib2, iclass 39, count 2 2006.257.13:29:32.99#ibcon#*mode == 0, iclass 39, count 2 2006.257.13:29:32.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.13:29:32.99#ibcon#[27=AT01-04\r\n] 2006.257.13:29:32.99#ibcon#*before write, iclass 39, count 2 2006.257.13:29:32.99#ibcon#enter sib2, iclass 39, count 2 2006.257.13:29:32.99#ibcon#flushed, iclass 39, count 2 2006.257.13:29:32.99#ibcon#about to write, iclass 39, count 2 2006.257.13:29:32.99#ibcon#wrote, iclass 39, count 2 2006.257.13:29:32.99#ibcon#about to read 3, iclass 39, count 2 2006.257.13:29:33.02#ibcon#read 3, iclass 39, count 2 2006.257.13:29:33.02#ibcon#about to read 4, iclass 39, count 2 2006.257.13:29:33.02#ibcon#read 4, iclass 39, count 2 2006.257.13:29:33.02#ibcon#about to read 5, iclass 39, count 2 2006.257.13:29:33.02#ibcon#read 5, iclass 39, count 2 2006.257.13:29:33.02#ibcon#about to read 6, iclass 39, count 2 2006.257.13:29:33.02#ibcon#read 6, iclass 39, count 2 2006.257.13:29:33.02#ibcon#end of sib2, iclass 39, count 2 2006.257.13:29:33.02#ibcon#*after write, iclass 39, count 2 2006.257.13:29:33.02#ibcon#*before return 0, iclass 39, count 2 2006.257.13:29:33.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:33.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:29:33.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.13:29:33.02#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:33.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:33.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:33.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:33.14#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:29:33.14#ibcon#first serial, iclass 39, count 0 2006.257.13:29:33.14#ibcon#enter sib2, iclass 39, count 0 2006.257.13:29:33.14#ibcon#flushed, iclass 39, count 0 2006.257.13:29:33.14#ibcon#about to write, iclass 39, count 0 2006.257.13:29:33.14#ibcon#wrote, iclass 39, count 0 2006.257.13:29:33.14#ibcon#about to read 3, iclass 39, count 0 2006.257.13:29:33.16#ibcon#read 3, iclass 39, count 0 2006.257.13:29:33.16#ibcon#about to read 4, iclass 39, count 0 2006.257.13:29:33.16#ibcon#read 4, iclass 39, count 0 2006.257.13:29:33.16#ibcon#about to read 5, iclass 39, count 0 2006.257.13:29:33.16#ibcon#read 5, iclass 39, count 0 2006.257.13:29:33.16#ibcon#about to read 6, iclass 39, count 0 2006.257.13:29:33.16#ibcon#read 6, iclass 39, count 0 2006.257.13:29:33.16#ibcon#end of sib2, iclass 39, count 0 2006.257.13:29:33.16#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:29:33.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:29:33.16#ibcon#[27=USB\r\n] 2006.257.13:29:33.16#ibcon#*before write, iclass 39, count 0 2006.257.13:29:33.16#ibcon#enter sib2, iclass 39, count 0 2006.257.13:29:33.16#ibcon#flushed, iclass 39, count 0 2006.257.13:29:33.16#ibcon#about to write, iclass 39, count 0 2006.257.13:29:33.16#ibcon#wrote, iclass 39, count 0 2006.257.13:29:33.16#ibcon#about to read 3, iclass 39, count 0 2006.257.13:29:33.19#ibcon#read 3, iclass 39, count 0 2006.257.13:29:33.19#ibcon#about to read 4, iclass 39, count 0 2006.257.13:29:33.19#ibcon#read 4, iclass 39, count 0 2006.257.13:29:33.19#ibcon#about to read 5, iclass 39, count 0 2006.257.13:29:33.19#ibcon#read 5, iclass 39, count 0 2006.257.13:29:33.19#ibcon#about to read 6, iclass 39, count 0 2006.257.13:29:33.19#ibcon#read 6, iclass 39, count 0 2006.257.13:29:33.19#ibcon#end of sib2, iclass 39, count 0 2006.257.13:29:33.19#ibcon#*after write, iclass 39, count 0 2006.257.13:29:33.19#ibcon#*before return 0, iclass 39, count 0 2006.257.13:29:33.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:33.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:29:33.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:29:33.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:29:33.19$vck44/vblo=2,634.99 2006.257.13:29:33.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.13:29:33.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.13:29:33.19#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:33.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:33.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:33.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:33.19#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:29:33.19#ibcon#first serial, iclass 3, count 0 2006.257.13:29:33.19#ibcon#enter sib2, iclass 3, count 0 2006.257.13:29:33.19#ibcon#flushed, iclass 3, count 0 2006.257.13:29:33.19#ibcon#about to write, iclass 3, count 0 2006.257.13:29:33.19#ibcon#wrote, iclass 3, count 0 2006.257.13:29:33.19#ibcon#about to read 3, iclass 3, count 0 2006.257.13:29:33.21#ibcon#read 3, iclass 3, count 0 2006.257.13:29:33.21#ibcon#about to read 4, iclass 3, count 0 2006.257.13:29:33.21#ibcon#read 4, iclass 3, count 0 2006.257.13:29:33.21#ibcon#about to read 5, iclass 3, count 0 2006.257.13:29:33.21#ibcon#read 5, iclass 3, count 0 2006.257.13:29:33.21#ibcon#about to read 6, iclass 3, count 0 2006.257.13:29:33.21#ibcon#read 6, iclass 3, count 0 2006.257.13:29:33.21#ibcon#end of sib2, iclass 3, count 0 2006.257.13:29:33.21#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:29:33.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:29:33.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:29:33.21#ibcon#*before write, iclass 3, count 0 2006.257.13:29:33.21#ibcon#enter sib2, iclass 3, count 0 2006.257.13:29:33.21#ibcon#flushed, iclass 3, count 0 2006.257.13:29:33.21#ibcon#about to write, iclass 3, count 0 2006.257.13:29:33.21#ibcon#wrote, iclass 3, count 0 2006.257.13:29:33.21#ibcon#about to read 3, iclass 3, count 0 2006.257.13:29:33.25#ibcon#read 3, iclass 3, count 0 2006.257.13:29:33.25#ibcon#about to read 4, iclass 3, count 0 2006.257.13:29:33.25#ibcon#read 4, iclass 3, count 0 2006.257.13:29:33.25#ibcon#about to read 5, iclass 3, count 0 2006.257.13:29:33.25#ibcon#read 5, iclass 3, count 0 2006.257.13:29:33.25#ibcon#about to read 6, iclass 3, count 0 2006.257.13:29:33.25#ibcon#read 6, iclass 3, count 0 2006.257.13:29:33.25#ibcon#end of sib2, iclass 3, count 0 2006.257.13:29:33.25#ibcon#*after write, iclass 3, count 0 2006.257.13:29:33.25#ibcon#*before return 0, iclass 3, count 0 2006.257.13:29:33.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:33.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:29:33.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:29:33.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:29:33.25$vck44/vb=2,5 2006.257.13:29:33.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.13:29:33.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.13:29:33.25#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:33.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:33.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:33.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:33.31#ibcon#enter wrdev, iclass 5, count 2 2006.257.13:29:33.31#ibcon#first serial, iclass 5, count 2 2006.257.13:29:33.31#ibcon#enter sib2, iclass 5, count 2 2006.257.13:29:33.31#ibcon#flushed, iclass 5, count 2 2006.257.13:29:33.31#ibcon#about to write, iclass 5, count 2 2006.257.13:29:33.31#ibcon#wrote, iclass 5, count 2 2006.257.13:29:33.31#ibcon#about to read 3, iclass 5, count 2 2006.257.13:29:33.33#ibcon#read 3, iclass 5, count 2 2006.257.13:29:33.33#ibcon#about to read 4, iclass 5, count 2 2006.257.13:29:33.33#ibcon#read 4, iclass 5, count 2 2006.257.13:29:33.33#ibcon#about to read 5, iclass 5, count 2 2006.257.13:29:33.33#ibcon#read 5, iclass 5, count 2 2006.257.13:29:33.33#ibcon#about to read 6, iclass 5, count 2 2006.257.13:29:33.33#ibcon#read 6, iclass 5, count 2 2006.257.13:29:33.33#ibcon#end of sib2, iclass 5, count 2 2006.257.13:29:33.33#ibcon#*mode == 0, iclass 5, count 2 2006.257.13:29:33.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.13:29:33.33#ibcon#[27=AT02-05\r\n] 2006.257.13:29:33.33#ibcon#*before write, iclass 5, count 2 2006.257.13:29:33.33#ibcon#enter sib2, iclass 5, count 2 2006.257.13:29:33.33#ibcon#flushed, iclass 5, count 2 2006.257.13:29:33.33#ibcon#about to write, iclass 5, count 2 2006.257.13:29:33.33#ibcon#wrote, iclass 5, count 2 2006.257.13:29:33.33#ibcon#about to read 3, iclass 5, count 2 2006.257.13:29:33.36#ibcon#read 3, iclass 5, count 2 2006.257.13:29:33.36#ibcon#about to read 4, iclass 5, count 2 2006.257.13:29:33.36#ibcon#read 4, iclass 5, count 2 2006.257.13:29:33.36#ibcon#about to read 5, iclass 5, count 2 2006.257.13:29:33.36#ibcon#read 5, iclass 5, count 2 2006.257.13:29:33.36#ibcon#about to read 6, iclass 5, count 2 2006.257.13:29:33.36#ibcon#read 6, iclass 5, count 2 2006.257.13:29:33.36#ibcon#end of sib2, iclass 5, count 2 2006.257.13:29:33.36#ibcon#*after write, iclass 5, count 2 2006.257.13:29:33.36#ibcon#*before return 0, iclass 5, count 2 2006.257.13:29:33.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:33.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:29:33.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.13:29:33.36#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:33.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:33.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:33.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:33.48#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:29:33.48#ibcon#first serial, iclass 5, count 0 2006.257.13:29:33.48#ibcon#enter sib2, iclass 5, count 0 2006.257.13:29:33.48#ibcon#flushed, iclass 5, count 0 2006.257.13:29:33.48#ibcon#about to write, iclass 5, count 0 2006.257.13:29:33.48#ibcon#wrote, iclass 5, count 0 2006.257.13:29:33.48#ibcon#about to read 3, iclass 5, count 0 2006.257.13:29:33.50#ibcon#read 3, iclass 5, count 0 2006.257.13:29:33.50#ibcon#about to read 4, iclass 5, count 0 2006.257.13:29:33.50#ibcon#read 4, iclass 5, count 0 2006.257.13:29:33.50#ibcon#about to read 5, iclass 5, count 0 2006.257.13:29:33.50#ibcon#read 5, iclass 5, count 0 2006.257.13:29:33.50#ibcon#about to read 6, iclass 5, count 0 2006.257.13:29:33.50#ibcon#read 6, iclass 5, count 0 2006.257.13:29:33.50#ibcon#end of sib2, iclass 5, count 0 2006.257.13:29:33.50#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:29:33.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:29:33.50#ibcon#[27=USB\r\n] 2006.257.13:29:33.50#ibcon#*before write, iclass 5, count 0 2006.257.13:29:33.50#ibcon#enter sib2, iclass 5, count 0 2006.257.13:29:33.50#ibcon#flushed, iclass 5, count 0 2006.257.13:29:33.50#ibcon#about to write, iclass 5, count 0 2006.257.13:29:33.50#ibcon#wrote, iclass 5, count 0 2006.257.13:29:33.50#ibcon#about to read 3, iclass 5, count 0 2006.257.13:29:33.53#ibcon#read 3, iclass 5, count 0 2006.257.13:29:33.53#ibcon#about to read 4, iclass 5, count 0 2006.257.13:29:33.53#ibcon#read 4, iclass 5, count 0 2006.257.13:29:33.53#ibcon#about to read 5, iclass 5, count 0 2006.257.13:29:33.53#ibcon#read 5, iclass 5, count 0 2006.257.13:29:33.53#ibcon#about to read 6, iclass 5, count 0 2006.257.13:29:33.53#ibcon#read 6, iclass 5, count 0 2006.257.13:29:33.53#ibcon#end of sib2, iclass 5, count 0 2006.257.13:29:33.53#ibcon#*after write, iclass 5, count 0 2006.257.13:29:33.53#ibcon#*before return 0, iclass 5, count 0 2006.257.13:29:33.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:33.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:29:33.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:29:33.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:29:33.53$vck44/vblo=3,649.99 2006.257.13:29:33.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.13:29:33.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.13:29:33.53#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:33.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:33.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:33.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:33.53#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:29:33.53#ibcon#first serial, iclass 7, count 0 2006.257.13:29:33.53#ibcon#enter sib2, iclass 7, count 0 2006.257.13:29:33.53#ibcon#flushed, iclass 7, count 0 2006.257.13:29:33.53#ibcon#about to write, iclass 7, count 0 2006.257.13:29:33.53#ibcon#wrote, iclass 7, count 0 2006.257.13:29:33.53#ibcon#about to read 3, iclass 7, count 0 2006.257.13:29:33.55#ibcon#read 3, iclass 7, count 0 2006.257.13:29:33.55#ibcon#about to read 4, iclass 7, count 0 2006.257.13:29:33.55#ibcon#read 4, iclass 7, count 0 2006.257.13:29:33.55#ibcon#about to read 5, iclass 7, count 0 2006.257.13:29:33.55#ibcon#read 5, iclass 7, count 0 2006.257.13:29:33.55#ibcon#about to read 6, iclass 7, count 0 2006.257.13:29:33.55#ibcon#read 6, iclass 7, count 0 2006.257.13:29:33.55#ibcon#end of sib2, iclass 7, count 0 2006.257.13:29:33.55#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:29:33.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:29:33.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:29:33.55#ibcon#*before write, iclass 7, count 0 2006.257.13:29:33.55#ibcon#enter sib2, iclass 7, count 0 2006.257.13:29:33.55#ibcon#flushed, iclass 7, count 0 2006.257.13:29:33.55#ibcon#about to write, iclass 7, count 0 2006.257.13:29:33.55#ibcon#wrote, iclass 7, count 0 2006.257.13:29:33.55#ibcon#about to read 3, iclass 7, count 0 2006.257.13:29:33.59#ibcon#read 3, iclass 7, count 0 2006.257.13:29:33.59#ibcon#about to read 4, iclass 7, count 0 2006.257.13:29:33.59#ibcon#read 4, iclass 7, count 0 2006.257.13:29:33.59#ibcon#about to read 5, iclass 7, count 0 2006.257.13:29:33.59#ibcon#read 5, iclass 7, count 0 2006.257.13:29:33.59#ibcon#about to read 6, iclass 7, count 0 2006.257.13:29:33.63#ibcon#read 6, iclass 7, count 0 2006.257.13:29:33.63#ibcon#end of sib2, iclass 7, count 0 2006.257.13:29:33.63#ibcon#*after write, iclass 7, count 0 2006.257.13:29:33.63#ibcon#*before return 0, iclass 7, count 0 2006.257.13:29:33.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:33.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:29:33.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:29:33.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:29:33.63$vck44/vb=3,4 2006.257.13:29:33.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.13:29:33.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.13:29:33.63#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:33.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:33.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:33.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:33.65#ibcon#enter wrdev, iclass 11, count 2 2006.257.13:29:33.65#ibcon#first serial, iclass 11, count 2 2006.257.13:29:33.65#ibcon#enter sib2, iclass 11, count 2 2006.257.13:29:33.65#ibcon#flushed, iclass 11, count 2 2006.257.13:29:33.65#ibcon#about to write, iclass 11, count 2 2006.257.13:29:33.65#ibcon#wrote, iclass 11, count 2 2006.257.13:29:33.65#ibcon#about to read 3, iclass 11, count 2 2006.257.13:29:33.67#ibcon#read 3, iclass 11, count 2 2006.257.13:29:33.67#ibcon#about to read 4, iclass 11, count 2 2006.257.13:29:33.67#ibcon#read 4, iclass 11, count 2 2006.257.13:29:33.67#ibcon#about to read 5, iclass 11, count 2 2006.257.13:29:33.67#ibcon#read 5, iclass 11, count 2 2006.257.13:29:33.67#ibcon#about to read 6, iclass 11, count 2 2006.257.13:29:33.67#ibcon#read 6, iclass 11, count 2 2006.257.13:29:33.67#ibcon#end of sib2, iclass 11, count 2 2006.257.13:29:33.67#ibcon#*mode == 0, iclass 11, count 2 2006.257.13:29:33.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.13:29:33.67#ibcon#[27=AT03-04\r\n] 2006.257.13:29:33.67#ibcon#*before write, iclass 11, count 2 2006.257.13:29:33.67#ibcon#enter sib2, iclass 11, count 2 2006.257.13:29:33.67#ibcon#flushed, iclass 11, count 2 2006.257.13:29:33.67#ibcon#about to write, iclass 11, count 2 2006.257.13:29:33.67#ibcon#wrote, iclass 11, count 2 2006.257.13:29:33.67#ibcon#about to read 3, iclass 11, count 2 2006.257.13:29:33.70#ibcon#read 3, iclass 11, count 2 2006.257.13:29:33.70#ibcon#about to read 4, iclass 11, count 2 2006.257.13:29:33.70#ibcon#read 4, iclass 11, count 2 2006.257.13:29:33.70#ibcon#about to read 5, iclass 11, count 2 2006.257.13:29:33.70#ibcon#read 5, iclass 11, count 2 2006.257.13:29:33.70#ibcon#about to read 6, iclass 11, count 2 2006.257.13:29:33.70#ibcon#read 6, iclass 11, count 2 2006.257.13:29:33.70#ibcon#end of sib2, iclass 11, count 2 2006.257.13:29:33.70#ibcon#*after write, iclass 11, count 2 2006.257.13:29:33.70#ibcon#*before return 0, iclass 11, count 2 2006.257.13:29:33.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:33.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:29:33.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.13:29:33.70#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:33.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:33.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:33.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:33.82#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:29:33.82#ibcon#first serial, iclass 11, count 0 2006.257.13:29:33.82#ibcon#enter sib2, iclass 11, count 0 2006.257.13:29:33.82#ibcon#flushed, iclass 11, count 0 2006.257.13:29:33.82#ibcon#about to write, iclass 11, count 0 2006.257.13:29:33.82#ibcon#wrote, iclass 11, count 0 2006.257.13:29:33.82#ibcon#about to read 3, iclass 11, count 0 2006.257.13:29:33.84#ibcon#read 3, iclass 11, count 0 2006.257.13:29:33.84#ibcon#about to read 4, iclass 11, count 0 2006.257.13:29:33.84#ibcon#read 4, iclass 11, count 0 2006.257.13:29:33.84#ibcon#about to read 5, iclass 11, count 0 2006.257.13:29:33.84#ibcon#read 5, iclass 11, count 0 2006.257.13:29:33.84#ibcon#about to read 6, iclass 11, count 0 2006.257.13:29:33.84#ibcon#read 6, iclass 11, count 0 2006.257.13:29:33.84#ibcon#end of sib2, iclass 11, count 0 2006.257.13:29:33.84#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:29:33.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:29:33.84#ibcon#[27=USB\r\n] 2006.257.13:29:33.84#ibcon#*before write, iclass 11, count 0 2006.257.13:29:33.84#ibcon#enter sib2, iclass 11, count 0 2006.257.13:29:33.84#ibcon#flushed, iclass 11, count 0 2006.257.13:29:33.84#ibcon#about to write, iclass 11, count 0 2006.257.13:29:33.84#ibcon#wrote, iclass 11, count 0 2006.257.13:29:33.84#ibcon#about to read 3, iclass 11, count 0 2006.257.13:29:33.87#ibcon#read 3, iclass 11, count 0 2006.257.13:29:33.87#ibcon#about to read 4, iclass 11, count 0 2006.257.13:29:33.87#ibcon#read 4, iclass 11, count 0 2006.257.13:29:33.87#ibcon#about to read 5, iclass 11, count 0 2006.257.13:29:33.87#ibcon#read 5, iclass 11, count 0 2006.257.13:29:33.87#ibcon#about to read 6, iclass 11, count 0 2006.257.13:29:33.87#ibcon#read 6, iclass 11, count 0 2006.257.13:29:33.87#ibcon#end of sib2, iclass 11, count 0 2006.257.13:29:33.87#ibcon#*after write, iclass 11, count 0 2006.257.13:29:33.87#ibcon#*before return 0, iclass 11, count 0 2006.257.13:29:33.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:33.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:29:33.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:29:33.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:29:33.87$vck44/vblo=4,679.99 2006.257.13:29:33.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:29:33.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:29:33.87#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:33.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:33.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:33.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:33.87#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:29:33.87#ibcon#first serial, iclass 13, count 0 2006.257.13:29:33.87#ibcon#enter sib2, iclass 13, count 0 2006.257.13:29:33.87#ibcon#flushed, iclass 13, count 0 2006.257.13:29:33.87#ibcon#about to write, iclass 13, count 0 2006.257.13:29:33.87#ibcon#wrote, iclass 13, count 0 2006.257.13:29:33.87#ibcon#about to read 3, iclass 13, count 0 2006.257.13:29:33.89#ibcon#read 3, iclass 13, count 0 2006.257.13:29:33.89#ibcon#about to read 4, iclass 13, count 0 2006.257.13:29:33.89#ibcon#read 4, iclass 13, count 0 2006.257.13:29:33.89#ibcon#about to read 5, iclass 13, count 0 2006.257.13:29:33.89#ibcon#read 5, iclass 13, count 0 2006.257.13:29:33.89#ibcon#about to read 6, iclass 13, count 0 2006.257.13:29:33.89#ibcon#read 6, iclass 13, count 0 2006.257.13:29:33.89#ibcon#end of sib2, iclass 13, count 0 2006.257.13:29:33.89#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:29:33.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:29:33.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:29:33.89#ibcon#*before write, iclass 13, count 0 2006.257.13:29:33.89#ibcon#enter sib2, iclass 13, count 0 2006.257.13:29:33.89#ibcon#flushed, iclass 13, count 0 2006.257.13:29:33.89#ibcon#about to write, iclass 13, count 0 2006.257.13:29:33.89#ibcon#wrote, iclass 13, count 0 2006.257.13:29:33.89#ibcon#about to read 3, iclass 13, count 0 2006.257.13:29:33.93#ibcon#read 3, iclass 13, count 0 2006.257.13:29:33.93#ibcon#about to read 4, iclass 13, count 0 2006.257.13:29:33.93#ibcon#read 4, iclass 13, count 0 2006.257.13:29:33.93#ibcon#about to read 5, iclass 13, count 0 2006.257.13:29:33.93#ibcon#read 5, iclass 13, count 0 2006.257.13:29:33.93#ibcon#about to read 6, iclass 13, count 0 2006.257.13:29:33.93#ibcon#read 6, iclass 13, count 0 2006.257.13:29:33.93#ibcon#end of sib2, iclass 13, count 0 2006.257.13:29:33.93#ibcon#*after write, iclass 13, count 0 2006.257.13:29:33.93#ibcon#*before return 0, iclass 13, count 0 2006.257.13:29:33.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:33.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:29:33.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:29:33.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:29:33.93$vck44/vb=4,5 2006.257.13:29:33.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.13:29:33.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.13:29:33.93#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:33.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:33.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:33.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:33.99#ibcon#enter wrdev, iclass 15, count 2 2006.257.13:29:33.99#ibcon#first serial, iclass 15, count 2 2006.257.13:29:33.99#ibcon#enter sib2, iclass 15, count 2 2006.257.13:29:33.99#ibcon#flushed, iclass 15, count 2 2006.257.13:29:33.99#ibcon#about to write, iclass 15, count 2 2006.257.13:29:33.99#ibcon#wrote, iclass 15, count 2 2006.257.13:29:33.99#ibcon#about to read 3, iclass 15, count 2 2006.257.13:29:34.01#ibcon#read 3, iclass 15, count 2 2006.257.13:29:34.01#ibcon#about to read 4, iclass 15, count 2 2006.257.13:29:34.01#ibcon#read 4, iclass 15, count 2 2006.257.13:29:34.01#ibcon#about to read 5, iclass 15, count 2 2006.257.13:29:34.01#ibcon#read 5, iclass 15, count 2 2006.257.13:29:34.01#ibcon#about to read 6, iclass 15, count 2 2006.257.13:29:34.01#ibcon#read 6, iclass 15, count 2 2006.257.13:29:34.01#ibcon#end of sib2, iclass 15, count 2 2006.257.13:29:34.01#ibcon#*mode == 0, iclass 15, count 2 2006.257.13:29:34.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.13:29:34.01#ibcon#[27=AT04-05\r\n] 2006.257.13:29:34.01#ibcon#*before write, iclass 15, count 2 2006.257.13:29:34.01#ibcon#enter sib2, iclass 15, count 2 2006.257.13:29:34.01#ibcon#flushed, iclass 15, count 2 2006.257.13:29:34.01#ibcon#about to write, iclass 15, count 2 2006.257.13:29:34.01#ibcon#wrote, iclass 15, count 2 2006.257.13:29:34.01#ibcon#about to read 3, iclass 15, count 2 2006.257.13:29:34.04#ibcon#read 3, iclass 15, count 2 2006.257.13:29:34.04#ibcon#about to read 4, iclass 15, count 2 2006.257.13:29:34.04#ibcon#read 4, iclass 15, count 2 2006.257.13:29:34.04#ibcon#about to read 5, iclass 15, count 2 2006.257.13:29:34.04#ibcon#read 5, iclass 15, count 2 2006.257.13:29:34.04#ibcon#about to read 6, iclass 15, count 2 2006.257.13:29:34.04#ibcon#read 6, iclass 15, count 2 2006.257.13:29:34.04#ibcon#end of sib2, iclass 15, count 2 2006.257.13:29:34.04#ibcon#*after write, iclass 15, count 2 2006.257.13:29:34.04#ibcon#*before return 0, iclass 15, count 2 2006.257.13:29:34.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:34.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:29:34.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.13:29:34.04#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:34.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:34.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:34.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:34.16#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:29:34.16#ibcon#first serial, iclass 15, count 0 2006.257.13:29:34.16#ibcon#enter sib2, iclass 15, count 0 2006.257.13:29:34.16#ibcon#flushed, iclass 15, count 0 2006.257.13:29:34.16#ibcon#about to write, iclass 15, count 0 2006.257.13:29:34.16#ibcon#wrote, iclass 15, count 0 2006.257.13:29:34.16#ibcon#about to read 3, iclass 15, count 0 2006.257.13:29:34.18#ibcon#read 3, iclass 15, count 0 2006.257.13:29:34.18#ibcon#about to read 4, iclass 15, count 0 2006.257.13:29:34.18#ibcon#read 4, iclass 15, count 0 2006.257.13:29:34.18#ibcon#about to read 5, iclass 15, count 0 2006.257.13:29:34.18#ibcon#read 5, iclass 15, count 0 2006.257.13:29:34.18#ibcon#about to read 6, iclass 15, count 0 2006.257.13:29:34.18#ibcon#read 6, iclass 15, count 0 2006.257.13:29:34.18#ibcon#end of sib2, iclass 15, count 0 2006.257.13:29:34.18#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:29:34.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:29:34.18#ibcon#[27=USB\r\n] 2006.257.13:29:34.18#ibcon#*before write, iclass 15, count 0 2006.257.13:29:34.18#ibcon#enter sib2, iclass 15, count 0 2006.257.13:29:34.18#ibcon#flushed, iclass 15, count 0 2006.257.13:29:34.18#ibcon#about to write, iclass 15, count 0 2006.257.13:29:34.18#ibcon#wrote, iclass 15, count 0 2006.257.13:29:34.18#ibcon#about to read 3, iclass 15, count 0 2006.257.13:29:34.21#ibcon#read 3, iclass 15, count 0 2006.257.13:29:34.21#ibcon#about to read 4, iclass 15, count 0 2006.257.13:29:34.21#ibcon#read 4, iclass 15, count 0 2006.257.13:29:34.21#ibcon#about to read 5, iclass 15, count 0 2006.257.13:29:34.21#ibcon#read 5, iclass 15, count 0 2006.257.13:29:34.21#ibcon#about to read 6, iclass 15, count 0 2006.257.13:29:34.21#ibcon#read 6, iclass 15, count 0 2006.257.13:29:34.21#ibcon#end of sib2, iclass 15, count 0 2006.257.13:29:34.21#ibcon#*after write, iclass 15, count 0 2006.257.13:29:34.21#ibcon#*before return 0, iclass 15, count 0 2006.257.13:29:34.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:34.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:29:34.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:29:34.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:29:34.21$vck44/vblo=5,709.99 2006.257.13:29:34.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.13:29:34.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.13:29:34.21#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:34.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:34.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:34.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:34.21#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:29:34.21#ibcon#first serial, iclass 17, count 0 2006.257.13:29:34.21#ibcon#enter sib2, iclass 17, count 0 2006.257.13:29:34.21#ibcon#flushed, iclass 17, count 0 2006.257.13:29:34.21#ibcon#about to write, iclass 17, count 0 2006.257.13:29:34.21#ibcon#wrote, iclass 17, count 0 2006.257.13:29:34.21#ibcon#about to read 3, iclass 17, count 0 2006.257.13:29:34.23#ibcon#read 3, iclass 17, count 0 2006.257.13:29:34.23#ibcon#about to read 4, iclass 17, count 0 2006.257.13:29:34.23#ibcon#read 4, iclass 17, count 0 2006.257.13:29:34.23#ibcon#about to read 5, iclass 17, count 0 2006.257.13:29:34.23#ibcon#read 5, iclass 17, count 0 2006.257.13:29:34.23#ibcon#about to read 6, iclass 17, count 0 2006.257.13:29:34.23#ibcon#read 6, iclass 17, count 0 2006.257.13:29:34.23#ibcon#end of sib2, iclass 17, count 0 2006.257.13:29:34.23#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:29:34.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:29:34.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:29:34.23#ibcon#*before write, iclass 17, count 0 2006.257.13:29:34.23#ibcon#enter sib2, iclass 17, count 0 2006.257.13:29:34.23#ibcon#flushed, iclass 17, count 0 2006.257.13:29:34.23#ibcon#about to write, iclass 17, count 0 2006.257.13:29:34.23#ibcon#wrote, iclass 17, count 0 2006.257.13:29:34.23#ibcon#about to read 3, iclass 17, count 0 2006.257.13:29:34.27#ibcon#read 3, iclass 17, count 0 2006.257.13:29:34.27#ibcon#about to read 4, iclass 17, count 0 2006.257.13:29:34.27#ibcon#read 4, iclass 17, count 0 2006.257.13:29:34.27#ibcon#about to read 5, iclass 17, count 0 2006.257.13:29:34.27#ibcon#read 5, iclass 17, count 0 2006.257.13:29:34.27#ibcon#about to read 6, iclass 17, count 0 2006.257.13:29:34.27#ibcon#read 6, iclass 17, count 0 2006.257.13:29:34.27#ibcon#end of sib2, iclass 17, count 0 2006.257.13:29:34.27#ibcon#*after write, iclass 17, count 0 2006.257.13:29:34.27#ibcon#*before return 0, iclass 17, count 0 2006.257.13:29:34.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:34.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:29:34.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:29:34.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:29:34.27$vck44/vb=5,4 2006.257.13:29:34.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.13:29:34.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.13:29:34.27#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:34.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:34.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:34.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:34.33#ibcon#enter wrdev, iclass 19, count 2 2006.257.13:29:34.33#ibcon#first serial, iclass 19, count 2 2006.257.13:29:34.33#ibcon#enter sib2, iclass 19, count 2 2006.257.13:29:34.33#ibcon#flushed, iclass 19, count 2 2006.257.13:29:34.33#ibcon#about to write, iclass 19, count 2 2006.257.13:29:34.33#ibcon#wrote, iclass 19, count 2 2006.257.13:29:34.33#ibcon#about to read 3, iclass 19, count 2 2006.257.13:29:34.35#ibcon#read 3, iclass 19, count 2 2006.257.13:29:34.35#ibcon#about to read 4, iclass 19, count 2 2006.257.13:29:34.35#ibcon#read 4, iclass 19, count 2 2006.257.13:29:34.35#ibcon#about to read 5, iclass 19, count 2 2006.257.13:29:34.35#ibcon#read 5, iclass 19, count 2 2006.257.13:29:34.35#ibcon#about to read 6, iclass 19, count 2 2006.257.13:29:34.35#ibcon#read 6, iclass 19, count 2 2006.257.13:29:34.35#ibcon#end of sib2, iclass 19, count 2 2006.257.13:29:34.35#ibcon#*mode == 0, iclass 19, count 2 2006.257.13:29:34.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.13:29:34.35#ibcon#[27=AT05-04\r\n] 2006.257.13:29:34.35#ibcon#*before write, iclass 19, count 2 2006.257.13:29:34.35#ibcon#enter sib2, iclass 19, count 2 2006.257.13:29:34.35#ibcon#flushed, iclass 19, count 2 2006.257.13:29:34.35#ibcon#about to write, iclass 19, count 2 2006.257.13:29:34.35#ibcon#wrote, iclass 19, count 2 2006.257.13:29:34.35#ibcon#about to read 3, iclass 19, count 2 2006.257.13:29:34.38#ibcon#read 3, iclass 19, count 2 2006.257.13:29:34.38#ibcon#about to read 4, iclass 19, count 2 2006.257.13:29:34.38#ibcon#read 4, iclass 19, count 2 2006.257.13:29:34.38#ibcon#about to read 5, iclass 19, count 2 2006.257.13:29:34.38#ibcon#read 5, iclass 19, count 2 2006.257.13:29:34.38#ibcon#about to read 6, iclass 19, count 2 2006.257.13:29:34.38#ibcon#read 6, iclass 19, count 2 2006.257.13:29:34.38#ibcon#end of sib2, iclass 19, count 2 2006.257.13:29:34.38#ibcon#*after write, iclass 19, count 2 2006.257.13:29:34.38#ibcon#*before return 0, iclass 19, count 2 2006.257.13:29:34.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:34.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:29:34.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.13:29:34.38#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:34.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:34.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:34.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:34.50#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:29:34.50#ibcon#first serial, iclass 19, count 0 2006.257.13:29:34.50#ibcon#enter sib2, iclass 19, count 0 2006.257.13:29:34.50#ibcon#flushed, iclass 19, count 0 2006.257.13:29:34.50#ibcon#about to write, iclass 19, count 0 2006.257.13:29:34.50#ibcon#wrote, iclass 19, count 0 2006.257.13:29:34.50#ibcon#about to read 3, iclass 19, count 0 2006.257.13:29:34.52#ibcon#read 3, iclass 19, count 0 2006.257.13:29:34.52#ibcon#about to read 4, iclass 19, count 0 2006.257.13:29:34.52#ibcon#read 4, iclass 19, count 0 2006.257.13:29:34.52#ibcon#about to read 5, iclass 19, count 0 2006.257.13:29:34.52#ibcon#read 5, iclass 19, count 0 2006.257.13:29:34.52#ibcon#about to read 6, iclass 19, count 0 2006.257.13:29:34.52#ibcon#read 6, iclass 19, count 0 2006.257.13:29:34.52#ibcon#end of sib2, iclass 19, count 0 2006.257.13:29:34.52#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:29:34.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:29:34.52#ibcon#[27=USB\r\n] 2006.257.13:29:34.52#ibcon#*before write, iclass 19, count 0 2006.257.13:29:34.52#ibcon#enter sib2, iclass 19, count 0 2006.257.13:29:34.52#ibcon#flushed, iclass 19, count 0 2006.257.13:29:34.52#ibcon#about to write, iclass 19, count 0 2006.257.13:29:34.52#ibcon#wrote, iclass 19, count 0 2006.257.13:29:34.52#ibcon#about to read 3, iclass 19, count 0 2006.257.13:29:34.55#ibcon#read 3, iclass 19, count 0 2006.257.13:29:34.55#ibcon#about to read 4, iclass 19, count 0 2006.257.13:29:34.55#ibcon#read 4, iclass 19, count 0 2006.257.13:29:34.55#ibcon#about to read 5, iclass 19, count 0 2006.257.13:29:34.55#ibcon#read 5, iclass 19, count 0 2006.257.13:29:34.55#ibcon#about to read 6, iclass 19, count 0 2006.257.13:29:34.55#ibcon#read 6, iclass 19, count 0 2006.257.13:29:34.55#ibcon#end of sib2, iclass 19, count 0 2006.257.13:29:34.55#ibcon#*after write, iclass 19, count 0 2006.257.13:29:34.55#ibcon#*before return 0, iclass 19, count 0 2006.257.13:29:34.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:34.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:29:34.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:29:34.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:29:34.55$vck44/vblo=6,719.99 2006.257.13:29:34.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.13:29:34.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.13:29:34.55#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:34.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:34.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:34.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:34.55#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:29:34.55#ibcon#first serial, iclass 21, count 0 2006.257.13:29:34.55#ibcon#enter sib2, iclass 21, count 0 2006.257.13:29:34.55#ibcon#flushed, iclass 21, count 0 2006.257.13:29:34.55#ibcon#about to write, iclass 21, count 0 2006.257.13:29:34.55#ibcon#wrote, iclass 21, count 0 2006.257.13:29:34.55#ibcon#about to read 3, iclass 21, count 0 2006.257.13:29:34.57#ibcon#read 3, iclass 21, count 0 2006.257.13:29:34.57#ibcon#about to read 4, iclass 21, count 0 2006.257.13:29:34.57#ibcon#read 4, iclass 21, count 0 2006.257.13:29:34.57#ibcon#about to read 5, iclass 21, count 0 2006.257.13:29:34.57#ibcon#read 5, iclass 21, count 0 2006.257.13:29:34.57#ibcon#about to read 6, iclass 21, count 0 2006.257.13:29:34.57#ibcon#read 6, iclass 21, count 0 2006.257.13:29:34.57#ibcon#end of sib2, iclass 21, count 0 2006.257.13:29:34.57#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:29:34.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:29:34.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:29:34.57#ibcon#*before write, iclass 21, count 0 2006.257.13:29:34.57#ibcon#enter sib2, iclass 21, count 0 2006.257.13:29:34.57#ibcon#flushed, iclass 21, count 0 2006.257.13:29:34.57#ibcon#about to write, iclass 21, count 0 2006.257.13:29:34.57#ibcon#wrote, iclass 21, count 0 2006.257.13:29:34.57#ibcon#about to read 3, iclass 21, count 0 2006.257.13:29:34.61#ibcon#read 3, iclass 21, count 0 2006.257.13:29:34.61#ibcon#about to read 4, iclass 21, count 0 2006.257.13:29:34.61#ibcon#read 4, iclass 21, count 0 2006.257.13:29:34.61#ibcon#about to read 5, iclass 21, count 0 2006.257.13:29:34.61#ibcon#read 5, iclass 21, count 0 2006.257.13:29:34.61#ibcon#about to read 6, iclass 21, count 0 2006.257.13:29:34.61#ibcon#read 6, iclass 21, count 0 2006.257.13:29:34.61#ibcon#end of sib2, iclass 21, count 0 2006.257.13:29:34.61#ibcon#*after write, iclass 21, count 0 2006.257.13:29:34.61#ibcon#*before return 0, iclass 21, count 0 2006.257.13:29:34.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:34.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:29:34.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:29:34.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:29:34.61$vck44/vb=6,4 2006.257.13:29:34.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.13:29:34.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.13:29:34.61#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:34.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:34.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:34.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:34.67#ibcon#enter wrdev, iclass 23, count 2 2006.257.13:29:34.67#ibcon#first serial, iclass 23, count 2 2006.257.13:29:34.67#ibcon#enter sib2, iclass 23, count 2 2006.257.13:29:34.67#ibcon#flushed, iclass 23, count 2 2006.257.13:29:34.67#ibcon#about to write, iclass 23, count 2 2006.257.13:29:34.67#ibcon#wrote, iclass 23, count 2 2006.257.13:29:34.67#ibcon#about to read 3, iclass 23, count 2 2006.257.13:29:34.69#ibcon#read 3, iclass 23, count 2 2006.257.13:29:34.69#ibcon#about to read 4, iclass 23, count 2 2006.257.13:29:34.69#ibcon#read 4, iclass 23, count 2 2006.257.13:29:34.69#ibcon#about to read 5, iclass 23, count 2 2006.257.13:29:34.69#ibcon#read 5, iclass 23, count 2 2006.257.13:29:34.69#ibcon#about to read 6, iclass 23, count 2 2006.257.13:29:34.69#ibcon#read 6, iclass 23, count 2 2006.257.13:29:34.69#ibcon#end of sib2, iclass 23, count 2 2006.257.13:29:34.69#ibcon#*mode == 0, iclass 23, count 2 2006.257.13:29:34.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.13:29:34.69#ibcon#[27=AT06-04\r\n] 2006.257.13:29:34.69#ibcon#*before write, iclass 23, count 2 2006.257.13:29:34.69#ibcon#enter sib2, iclass 23, count 2 2006.257.13:29:34.69#ibcon#flushed, iclass 23, count 2 2006.257.13:29:34.69#ibcon#about to write, iclass 23, count 2 2006.257.13:29:34.69#ibcon#wrote, iclass 23, count 2 2006.257.13:29:34.69#ibcon#about to read 3, iclass 23, count 2 2006.257.13:29:34.72#ibcon#read 3, iclass 23, count 2 2006.257.13:29:34.72#ibcon#about to read 4, iclass 23, count 2 2006.257.13:29:34.72#ibcon#read 4, iclass 23, count 2 2006.257.13:29:34.72#ibcon#about to read 5, iclass 23, count 2 2006.257.13:29:34.72#ibcon#read 5, iclass 23, count 2 2006.257.13:29:34.72#ibcon#about to read 6, iclass 23, count 2 2006.257.13:29:34.72#ibcon#read 6, iclass 23, count 2 2006.257.13:29:34.72#ibcon#end of sib2, iclass 23, count 2 2006.257.13:29:34.72#ibcon#*after write, iclass 23, count 2 2006.257.13:29:34.72#ibcon#*before return 0, iclass 23, count 2 2006.257.13:29:34.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:34.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:29:34.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.13:29:34.72#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:34.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:34.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:34.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:34.84#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:29:34.84#ibcon#first serial, iclass 23, count 0 2006.257.13:29:34.84#ibcon#enter sib2, iclass 23, count 0 2006.257.13:29:34.84#ibcon#flushed, iclass 23, count 0 2006.257.13:29:34.84#ibcon#about to write, iclass 23, count 0 2006.257.13:29:34.84#ibcon#wrote, iclass 23, count 0 2006.257.13:29:34.84#ibcon#about to read 3, iclass 23, count 0 2006.257.13:29:34.86#ibcon#read 3, iclass 23, count 0 2006.257.13:29:34.86#ibcon#about to read 4, iclass 23, count 0 2006.257.13:29:34.86#ibcon#read 4, iclass 23, count 0 2006.257.13:29:34.86#ibcon#about to read 5, iclass 23, count 0 2006.257.13:29:34.86#ibcon#read 5, iclass 23, count 0 2006.257.13:29:34.86#ibcon#about to read 6, iclass 23, count 0 2006.257.13:29:34.86#ibcon#read 6, iclass 23, count 0 2006.257.13:29:34.86#ibcon#end of sib2, iclass 23, count 0 2006.257.13:29:34.86#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:29:34.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:29:34.86#ibcon#[27=USB\r\n] 2006.257.13:29:34.86#ibcon#*before write, iclass 23, count 0 2006.257.13:29:34.86#ibcon#enter sib2, iclass 23, count 0 2006.257.13:29:34.86#ibcon#flushed, iclass 23, count 0 2006.257.13:29:34.86#ibcon#about to write, iclass 23, count 0 2006.257.13:29:34.86#ibcon#wrote, iclass 23, count 0 2006.257.13:29:34.86#ibcon#about to read 3, iclass 23, count 0 2006.257.13:29:34.89#ibcon#read 3, iclass 23, count 0 2006.257.13:29:34.89#ibcon#about to read 4, iclass 23, count 0 2006.257.13:29:34.89#ibcon#read 4, iclass 23, count 0 2006.257.13:29:34.89#ibcon#about to read 5, iclass 23, count 0 2006.257.13:29:34.89#ibcon#read 5, iclass 23, count 0 2006.257.13:29:34.89#ibcon#about to read 6, iclass 23, count 0 2006.257.13:29:34.89#ibcon#read 6, iclass 23, count 0 2006.257.13:29:34.89#ibcon#end of sib2, iclass 23, count 0 2006.257.13:29:34.89#ibcon#*after write, iclass 23, count 0 2006.257.13:29:34.89#ibcon#*before return 0, iclass 23, count 0 2006.257.13:29:34.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:34.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:29:34.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:29:34.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:29:34.89$vck44/vblo=7,734.99 2006.257.13:29:34.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.13:29:34.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.13:29:34.89#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:34.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:34.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:34.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:34.89#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:29:34.89#ibcon#first serial, iclass 25, count 0 2006.257.13:29:34.89#ibcon#enter sib2, iclass 25, count 0 2006.257.13:29:34.89#ibcon#flushed, iclass 25, count 0 2006.257.13:29:34.89#ibcon#about to write, iclass 25, count 0 2006.257.13:29:34.89#ibcon#wrote, iclass 25, count 0 2006.257.13:29:34.89#ibcon#about to read 3, iclass 25, count 0 2006.257.13:29:34.91#ibcon#read 3, iclass 25, count 0 2006.257.13:29:34.91#ibcon#about to read 4, iclass 25, count 0 2006.257.13:29:34.91#ibcon#read 4, iclass 25, count 0 2006.257.13:29:34.91#ibcon#about to read 5, iclass 25, count 0 2006.257.13:29:34.91#ibcon#read 5, iclass 25, count 0 2006.257.13:29:34.91#ibcon#about to read 6, iclass 25, count 0 2006.257.13:29:34.91#ibcon#read 6, iclass 25, count 0 2006.257.13:29:34.91#ibcon#end of sib2, iclass 25, count 0 2006.257.13:29:34.91#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:29:34.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:29:34.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:29:34.91#ibcon#*before write, iclass 25, count 0 2006.257.13:29:34.91#ibcon#enter sib2, iclass 25, count 0 2006.257.13:29:34.91#ibcon#flushed, iclass 25, count 0 2006.257.13:29:34.91#ibcon#about to write, iclass 25, count 0 2006.257.13:29:34.91#ibcon#wrote, iclass 25, count 0 2006.257.13:29:34.91#ibcon#about to read 3, iclass 25, count 0 2006.257.13:29:34.95#ibcon#read 3, iclass 25, count 0 2006.257.13:29:34.95#ibcon#about to read 4, iclass 25, count 0 2006.257.13:29:34.95#ibcon#read 4, iclass 25, count 0 2006.257.13:29:34.95#ibcon#about to read 5, iclass 25, count 0 2006.257.13:29:34.95#ibcon#read 5, iclass 25, count 0 2006.257.13:29:34.95#ibcon#about to read 6, iclass 25, count 0 2006.257.13:29:34.95#ibcon#read 6, iclass 25, count 0 2006.257.13:29:34.95#ibcon#end of sib2, iclass 25, count 0 2006.257.13:29:34.95#ibcon#*after write, iclass 25, count 0 2006.257.13:29:34.95#ibcon#*before return 0, iclass 25, count 0 2006.257.13:29:34.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:34.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:29:34.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:29:34.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:29:34.95$vck44/vb=7,4 2006.257.13:29:34.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.13:29:34.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.13:29:34.95#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:34.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:35.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:35.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:35.01#ibcon#enter wrdev, iclass 27, count 2 2006.257.13:29:35.01#ibcon#first serial, iclass 27, count 2 2006.257.13:29:35.01#ibcon#enter sib2, iclass 27, count 2 2006.257.13:29:35.01#ibcon#flushed, iclass 27, count 2 2006.257.13:29:35.01#ibcon#about to write, iclass 27, count 2 2006.257.13:29:35.01#ibcon#wrote, iclass 27, count 2 2006.257.13:29:35.01#ibcon#about to read 3, iclass 27, count 2 2006.257.13:29:35.03#ibcon#read 3, iclass 27, count 2 2006.257.13:29:35.03#ibcon#about to read 4, iclass 27, count 2 2006.257.13:29:35.03#ibcon#read 4, iclass 27, count 2 2006.257.13:29:35.03#ibcon#about to read 5, iclass 27, count 2 2006.257.13:29:35.03#ibcon#read 5, iclass 27, count 2 2006.257.13:29:35.03#ibcon#about to read 6, iclass 27, count 2 2006.257.13:29:35.03#ibcon#read 6, iclass 27, count 2 2006.257.13:29:35.03#ibcon#end of sib2, iclass 27, count 2 2006.257.13:29:35.03#ibcon#*mode == 0, iclass 27, count 2 2006.257.13:29:35.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.13:29:35.03#ibcon#[27=AT07-04\r\n] 2006.257.13:29:35.03#ibcon#*before write, iclass 27, count 2 2006.257.13:29:35.03#ibcon#enter sib2, iclass 27, count 2 2006.257.13:29:35.03#ibcon#flushed, iclass 27, count 2 2006.257.13:29:35.03#ibcon#about to write, iclass 27, count 2 2006.257.13:29:35.03#ibcon#wrote, iclass 27, count 2 2006.257.13:29:35.03#ibcon#about to read 3, iclass 27, count 2 2006.257.13:29:35.06#ibcon#read 3, iclass 27, count 2 2006.257.13:29:35.06#ibcon#about to read 4, iclass 27, count 2 2006.257.13:29:35.06#ibcon#read 4, iclass 27, count 2 2006.257.13:29:35.06#ibcon#about to read 5, iclass 27, count 2 2006.257.13:29:35.06#ibcon#read 5, iclass 27, count 2 2006.257.13:29:35.06#ibcon#about to read 6, iclass 27, count 2 2006.257.13:29:35.06#ibcon#read 6, iclass 27, count 2 2006.257.13:29:35.06#ibcon#end of sib2, iclass 27, count 2 2006.257.13:29:35.06#ibcon#*after write, iclass 27, count 2 2006.257.13:29:35.06#ibcon#*before return 0, iclass 27, count 2 2006.257.13:29:35.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:35.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:29:35.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.13:29:35.06#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:35.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:35.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:35.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:35.18#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:29:35.18#ibcon#first serial, iclass 27, count 0 2006.257.13:29:35.18#ibcon#enter sib2, iclass 27, count 0 2006.257.13:29:35.18#ibcon#flushed, iclass 27, count 0 2006.257.13:29:35.18#ibcon#about to write, iclass 27, count 0 2006.257.13:29:35.18#ibcon#wrote, iclass 27, count 0 2006.257.13:29:35.18#ibcon#about to read 3, iclass 27, count 0 2006.257.13:29:35.20#ibcon#read 3, iclass 27, count 0 2006.257.13:29:35.20#ibcon#about to read 4, iclass 27, count 0 2006.257.13:29:35.20#ibcon#read 4, iclass 27, count 0 2006.257.13:29:35.20#ibcon#about to read 5, iclass 27, count 0 2006.257.13:29:35.20#ibcon#read 5, iclass 27, count 0 2006.257.13:29:35.20#ibcon#about to read 6, iclass 27, count 0 2006.257.13:29:35.20#ibcon#read 6, iclass 27, count 0 2006.257.13:29:35.20#ibcon#end of sib2, iclass 27, count 0 2006.257.13:29:35.20#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:29:35.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:29:35.20#ibcon#[27=USB\r\n] 2006.257.13:29:35.20#ibcon#*before write, iclass 27, count 0 2006.257.13:29:35.20#ibcon#enter sib2, iclass 27, count 0 2006.257.13:29:35.20#ibcon#flushed, iclass 27, count 0 2006.257.13:29:35.20#ibcon#about to write, iclass 27, count 0 2006.257.13:29:35.20#ibcon#wrote, iclass 27, count 0 2006.257.13:29:35.20#ibcon#about to read 3, iclass 27, count 0 2006.257.13:29:35.23#ibcon#read 3, iclass 27, count 0 2006.257.13:29:35.23#ibcon#about to read 4, iclass 27, count 0 2006.257.13:29:35.23#ibcon#read 4, iclass 27, count 0 2006.257.13:29:35.23#ibcon#about to read 5, iclass 27, count 0 2006.257.13:29:35.23#ibcon#read 5, iclass 27, count 0 2006.257.13:29:35.23#ibcon#about to read 6, iclass 27, count 0 2006.257.13:29:35.23#ibcon#read 6, iclass 27, count 0 2006.257.13:29:35.23#ibcon#end of sib2, iclass 27, count 0 2006.257.13:29:35.23#ibcon#*after write, iclass 27, count 0 2006.257.13:29:35.23#ibcon#*before return 0, iclass 27, count 0 2006.257.13:29:35.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:35.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:29:35.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:29:35.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:29:35.23$vck44/vblo=8,744.99 2006.257.13:29:35.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.13:29:35.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.13:29:35.23#ibcon#ireg 17 cls_cnt 0 2006.257.13:29:35.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:29:35.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:29:35.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:29:35.23#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:29:35.23#ibcon#first serial, iclass 29, count 0 2006.257.13:29:35.23#ibcon#enter sib2, iclass 29, count 0 2006.257.13:29:35.23#ibcon#flushed, iclass 29, count 0 2006.257.13:29:35.23#ibcon#about to write, iclass 29, count 0 2006.257.13:29:35.23#ibcon#wrote, iclass 29, count 0 2006.257.13:29:35.23#ibcon#about to read 3, iclass 29, count 0 2006.257.13:29:35.25#ibcon#read 3, iclass 29, count 0 2006.257.13:29:35.25#ibcon#about to read 4, iclass 29, count 0 2006.257.13:29:35.25#ibcon#read 4, iclass 29, count 0 2006.257.13:29:35.25#ibcon#about to read 5, iclass 29, count 0 2006.257.13:29:35.25#ibcon#read 5, iclass 29, count 0 2006.257.13:29:35.25#ibcon#about to read 6, iclass 29, count 0 2006.257.13:29:35.25#ibcon#read 6, iclass 29, count 0 2006.257.13:29:35.25#ibcon#end of sib2, iclass 29, count 0 2006.257.13:29:35.25#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:29:35.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:29:35.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:29:35.25#ibcon#*before write, iclass 29, count 0 2006.257.13:29:35.25#ibcon#enter sib2, iclass 29, count 0 2006.257.13:29:35.25#ibcon#flushed, iclass 29, count 0 2006.257.13:29:35.25#ibcon#about to write, iclass 29, count 0 2006.257.13:29:35.25#ibcon#wrote, iclass 29, count 0 2006.257.13:29:35.25#ibcon#about to read 3, iclass 29, count 0 2006.257.13:29:35.29#ibcon#read 3, iclass 29, count 0 2006.257.13:29:35.29#ibcon#about to read 4, iclass 29, count 0 2006.257.13:29:35.29#ibcon#read 4, iclass 29, count 0 2006.257.13:29:35.29#ibcon#about to read 5, iclass 29, count 0 2006.257.13:29:35.29#ibcon#read 5, iclass 29, count 0 2006.257.13:29:35.29#ibcon#about to read 6, iclass 29, count 0 2006.257.13:29:35.29#ibcon#read 6, iclass 29, count 0 2006.257.13:29:35.29#ibcon#end of sib2, iclass 29, count 0 2006.257.13:29:35.29#ibcon#*after write, iclass 29, count 0 2006.257.13:29:35.29#ibcon#*before return 0, iclass 29, count 0 2006.257.13:29:35.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:29:35.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:29:35.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:29:35.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:29:35.29$vck44/vb=8,4 2006.257.13:29:35.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.13:29:35.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.13:29:35.29#ibcon#ireg 11 cls_cnt 2 2006.257.13:29:35.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:29:35.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:29:35.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:29:35.35#ibcon#enter wrdev, iclass 31, count 2 2006.257.13:29:35.35#ibcon#first serial, iclass 31, count 2 2006.257.13:29:35.35#ibcon#enter sib2, iclass 31, count 2 2006.257.13:29:35.35#ibcon#flushed, iclass 31, count 2 2006.257.13:29:35.35#ibcon#about to write, iclass 31, count 2 2006.257.13:29:35.35#ibcon#wrote, iclass 31, count 2 2006.257.13:29:35.35#ibcon#about to read 3, iclass 31, count 2 2006.257.13:29:35.37#ibcon#read 3, iclass 31, count 2 2006.257.13:29:35.37#ibcon#about to read 4, iclass 31, count 2 2006.257.13:29:35.37#ibcon#read 4, iclass 31, count 2 2006.257.13:29:35.37#ibcon#about to read 5, iclass 31, count 2 2006.257.13:29:35.37#ibcon#read 5, iclass 31, count 2 2006.257.13:29:35.37#ibcon#about to read 6, iclass 31, count 2 2006.257.13:29:35.37#ibcon#read 6, iclass 31, count 2 2006.257.13:29:35.37#ibcon#end of sib2, iclass 31, count 2 2006.257.13:29:35.37#ibcon#*mode == 0, iclass 31, count 2 2006.257.13:29:35.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.13:29:35.37#ibcon#[27=AT08-04\r\n] 2006.257.13:29:35.37#ibcon#*before write, iclass 31, count 2 2006.257.13:29:35.37#ibcon#enter sib2, iclass 31, count 2 2006.257.13:29:35.37#ibcon#flushed, iclass 31, count 2 2006.257.13:29:35.37#ibcon#about to write, iclass 31, count 2 2006.257.13:29:35.37#ibcon#wrote, iclass 31, count 2 2006.257.13:29:35.37#ibcon#about to read 3, iclass 31, count 2 2006.257.13:29:35.40#ibcon#read 3, iclass 31, count 2 2006.257.13:29:35.40#ibcon#about to read 4, iclass 31, count 2 2006.257.13:29:35.40#ibcon#read 4, iclass 31, count 2 2006.257.13:29:35.40#ibcon#about to read 5, iclass 31, count 2 2006.257.13:29:35.40#ibcon#read 5, iclass 31, count 2 2006.257.13:29:35.40#ibcon#about to read 6, iclass 31, count 2 2006.257.13:29:35.40#ibcon#read 6, iclass 31, count 2 2006.257.13:29:35.40#ibcon#end of sib2, iclass 31, count 2 2006.257.13:29:35.40#ibcon#*after write, iclass 31, count 2 2006.257.13:29:35.40#ibcon#*before return 0, iclass 31, count 2 2006.257.13:29:35.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:29:35.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:29:35.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.13:29:35.40#ibcon#ireg 7 cls_cnt 0 2006.257.13:29:35.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:29:35.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:29:35.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:29:35.52#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:29:35.52#ibcon#first serial, iclass 31, count 0 2006.257.13:29:35.52#ibcon#enter sib2, iclass 31, count 0 2006.257.13:29:35.52#ibcon#flushed, iclass 31, count 0 2006.257.13:29:35.52#ibcon#about to write, iclass 31, count 0 2006.257.13:29:35.52#ibcon#wrote, iclass 31, count 0 2006.257.13:29:35.52#ibcon#about to read 3, iclass 31, count 0 2006.257.13:29:35.54#ibcon#read 3, iclass 31, count 0 2006.257.13:29:35.54#ibcon#about to read 4, iclass 31, count 0 2006.257.13:29:35.54#ibcon#read 4, iclass 31, count 0 2006.257.13:29:35.54#ibcon#about to read 5, iclass 31, count 0 2006.257.13:29:35.54#ibcon#read 5, iclass 31, count 0 2006.257.13:29:35.54#ibcon#about to read 6, iclass 31, count 0 2006.257.13:29:35.54#ibcon#read 6, iclass 31, count 0 2006.257.13:29:35.54#ibcon#end of sib2, iclass 31, count 0 2006.257.13:29:35.54#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:29:35.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:29:35.54#ibcon#[27=USB\r\n] 2006.257.13:29:35.54#ibcon#*before write, iclass 31, count 0 2006.257.13:29:35.54#ibcon#enter sib2, iclass 31, count 0 2006.257.13:29:35.54#ibcon#flushed, iclass 31, count 0 2006.257.13:29:35.54#ibcon#about to write, iclass 31, count 0 2006.257.13:29:35.54#ibcon#wrote, iclass 31, count 0 2006.257.13:29:35.54#ibcon#about to read 3, iclass 31, count 0 2006.257.13:29:35.57#ibcon#read 3, iclass 31, count 0 2006.257.13:29:35.57#ibcon#about to read 4, iclass 31, count 0 2006.257.13:29:35.57#ibcon#read 4, iclass 31, count 0 2006.257.13:29:35.57#ibcon#about to read 5, iclass 31, count 0 2006.257.13:29:35.57#ibcon#read 5, iclass 31, count 0 2006.257.13:29:35.57#ibcon#about to read 6, iclass 31, count 0 2006.257.13:29:35.57#ibcon#read 6, iclass 31, count 0 2006.257.13:29:35.57#ibcon#end of sib2, iclass 31, count 0 2006.257.13:29:35.57#ibcon#*after write, iclass 31, count 0 2006.257.13:29:35.57#ibcon#*before return 0, iclass 31, count 0 2006.257.13:29:35.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:29:35.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:29:35.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:29:35.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:29:35.57$vck44/vabw=wide 2006.257.13:29:35.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.13:29:35.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.13:29:35.57#ibcon#ireg 8 cls_cnt 0 2006.257.13:29:35.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:29:35.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:29:35.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:29:35.57#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:29:35.57#ibcon#first serial, iclass 33, count 0 2006.257.13:29:35.57#ibcon#enter sib2, iclass 33, count 0 2006.257.13:29:35.57#ibcon#flushed, iclass 33, count 0 2006.257.13:29:35.57#ibcon#about to write, iclass 33, count 0 2006.257.13:29:35.57#ibcon#wrote, iclass 33, count 0 2006.257.13:29:35.57#ibcon#about to read 3, iclass 33, count 0 2006.257.13:29:35.59#ibcon#read 3, iclass 33, count 0 2006.257.13:29:35.59#ibcon#about to read 4, iclass 33, count 0 2006.257.13:29:35.59#ibcon#read 4, iclass 33, count 0 2006.257.13:29:35.59#ibcon#about to read 5, iclass 33, count 0 2006.257.13:29:35.59#ibcon#read 5, iclass 33, count 0 2006.257.13:29:35.59#ibcon#about to read 6, iclass 33, count 0 2006.257.13:29:35.59#ibcon#read 6, iclass 33, count 0 2006.257.13:29:35.59#ibcon#end of sib2, iclass 33, count 0 2006.257.13:29:35.59#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:29:35.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:29:35.59#ibcon#[25=BW32\r\n] 2006.257.13:29:35.59#ibcon#*before write, iclass 33, count 0 2006.257.13:29:35.59#ibcon#enter sib2, iclass 33, count 0 2006.257.13:29:35.59#ibcon#flushed, iclass 33, count 0 2006.257.13:29:35.59#ibcon#about to write, iclass 33, count 0 2006.257.13:29:35.59#ibcon#wrote, iclass 33, count 0 2006.257.13:29:35.59#ibcon#about to read 3, iclass 33, count 0 2006.257.13:29:35.62#ibcon#read 3, iclass 33, count 0 2006.257.13:29:35.62#ibcon#about to read 4, iclass 33, count 0 2006.257.13:29:35.62#ibcon#read 4, iclass 33, count 0 2006.257.13:29:35.62#ibcon#about to read 5, iclass 33, count 0 2006.257.13:29:35.62#ibcon#read 5, iclass 33, count 0 2006.257.13:29:35.62#ibcon#about to read 6, iclass 33, count 0 2006.257.13:29:35.62#ibcon#read 6, iclass 33, count 0 2006.257.13:29:35.62#ibcon#end of sib2, iclass 33, count 0 2006.257.13:29:35.62#ibcon#*after write, iclass 33, count 0 2006.257.13:29:35.62#ibcon#*before return 0, iclass 33, count 0 2006.257.13:29:35.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:29:35.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:29:35.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:29:35.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:29:35.62$vck44/vbbw=wide 2006.257.13:29:35.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.13:29:35.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.13:29:35.62#ibcon#ireg 8 cls_cnt 0 2006.257.13:29:35.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:29:35.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:29:35.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:29:35.69#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:29:35.69#ibcon#first serial, iclass 35, count 0 2006.257.13:29:35.69#ibcon#enter sib2, iclass 35, count 0 2006.257.13:29:35.69#ibcon#flushed, iclass 35, count 0 2006.257.13:29:35.69#ibcon#about to write, iclass 35, count 0 2006.257.13:29:35.69#ibcon#wrote, iclass 35, count 0 2006.257.13:29:35.69#ibcon#about to read 3, iclass 35, count 0 2006.257.13:29:35.71#ibcon#read 3, iclass 35, count 0 2006.257.13:29:35.71#ibcon#about to read 4, iclass 35, count 0 2006.257.13:29:35.71#ibcon#read 4, iclass 35, count 0 2006.257.13:29:35.71#ibcon#about to read 5, iclass 35, count 0 2006.257.13:29:35.71#ibcon#read 5, iclass 35, count 0 2006.257.13:29:35.71#ibcon#about to read 6, iclass 35, count 0 2006.257.13:29:35.71#ibcon#read 6, iclass 35, count 0 2006.257.13:29:35.71#ibcon#end of sib2, iclass 35, count 0 2006.257.13:29:35.71#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:29:35.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:29:35.71#ibcon#[27=BW32\r\n] 2006.257.13:29:35.71#ibcon#*before write, iclass 35, count 0 2006.257.13:29:35.71#ibcon#enter sib2, iclass 35, count 0 2006.257.13:29:35.71#ibcon#flushed, iclass 35, count 0 2006.257.13:29:35.71#ibcon#about to write, iclass 35, count 0 2006.257.13:29:35.71#ibcon#wrote, iclass 35, count 0 2006.257.13:29:35.71#ibcon#about to read 3, iclass 35, count 0 2006.257.13:29:35.74#ibcon#read 3, iclass 35, count 0 2006.257.13:29:35.74#ibcon#about to read 4, iclass 35, count 0 2006.257.13:29:35.74#ibcon#read 4, iclass 35, count 0 2006.257.13:29:35.74#ibcon#about to read 5, iclass 35, count 0 2006.257.13:29:35.74#ibcon#read 5, iclass 35, count 0 2006.257.13:29:35.74#ibcon#about to read 6, iclass 35, count 0 2006.257.13:29:35.74#ibcon#read 6, iclass 35, count 0 2006.257.13:29:35.74#ibcon#end of sib2, iclass 35, count 0 2006.257.13:29:35.74#ibcon#*after write, iclass 35, count 0 2006.257.13:29:35.74#ibcon#*before return 0, iclass 35, count 0 2006.257.13:29:35.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:29:35.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:29:35.74#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:29:35.74#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:29:35.74$setupk4/ifdk4 2006.257.13:29:35.74$ifdk4/lo= 2006.257.13:29:35.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:29:35.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:29:35.74$ifdk4/patch= 2006.257.13:29:35.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:29:35.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:29:35.74$setupk4/!*+20s 2006.257.13:29:42.76#abcon#<5=/14 1.1 2.9 17.51 971013.9\r\n> 2006.257.13:29:42.78#abcon#{5=INTERFACE CLEAR} 2006.257.13:29:42.84#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:29:48.13#trakl#Source acquired 2006.257.13:29:49.13#flagr#flagr/antenna,acquired 2006.257.13:29:50.26$setupk4/"tpicd 2006.257.13:29:50.26$setupk4/echo=off 2006.257.13:29:50.26$setupk4/xlog=off 2006.257.13:29:50.26:!2006.257.13:31:06 2006.257.13:31:06.00:preob 2006.257.13:31:06.13/onsource/TRACKING 2006.257.13:31:06.13:!2006.257.13:31:16 2006.257.13:31:16.00:"tape 2006.257.13:31:16.00:"st=record 2006.257.13:31:16.00:data_valid=on 2006.257.13:31:16.00:midob 2006.257.13:31:16.13/onsource/TRACKING 2006.257.13:31:16.13/wx/17.49,1013.9,98 2006.257.13:31:16.28/cable/+6.4811E-03 2006.257.13:31:17.37/va/01,08,usb,yes,30,33 2006.257.13:31:17.37/va/02,07,usb,yes,33,33 2006.257.13:31:17.37/va/03,08,usb,yes,29,31 2006.257.13:31:17.37/va/04,07,usb,yes,34,35 2006.257.13:31:17.37/va/05,04,usb,yes,30,31 2006.257.13:31:17.37/va/06,04,usb,yes,34,33 2006.257.13:31:17.37/va/07,04,usb,yes,35,35 2006.257.13:31:17.37/va/08,04,usb,yes,29,35 2006.257.13:31:17.60/valo/01,524.99,yes,locked 2006.257.13:31:17.60/valo/02,534.99,yes,locked 2006.257.13:31:17.60/valo/03,564.99,yes,locked 2006.257.13:31:17.60/valo/04,624.99,yes,locked 2006.257.13:31:17.60/valo/05,734.99,yes,locked 2006.257.13:31:17.60/valo/06,814.99,yes,locked 2006.257.13:31:17.60/valo/07,864.99,yes,locked 2006.257.13:31:17.60/valo/08,884.99,yes,locked 2006.257.13:31:18.69/vb/01,04,usb,yes,30,28 2006.257.13:31:18.69/vb/02,05,usb,yes,28,28 2006.257.13:31:18.69/vb/03,04,usb,yes,29,32 2006.257.13:31:18.69/vb/04,05,usb,yes,30,29 2006.257.13:31:18.69/vb/05,04,usb,yes,26,28 2006.257.13:31:18.69/vb/06,04,usb,yes,31,27 2006.257.13:31:18.69/vb/07,04,usb,yes,30,30 2006.257.13:31:18.69/vb/08,04,usb,yes,28,31 2006.257.13:31:18.93/vblo/01,629.99,yes,locked 2006.257.13:31:18.93/vblo/02,634.99,yes,locked 2006.257.13:31:18.93/vblo/03,649.99,yes,locked 2006.257.13:31:18.93/vblo/04,679.99,yes,locked 2006.257.13:31:18.93/vblo/05,709.99,yes,locked 2006.257.13:31:18.93/vblo/06,719.99,yes,locked 2006.257.13:31:18.93/vblo/07,734.99,yes,locked 2006.257.13:31:18.93/vblo/08,744.99,yes,locked 2006.257.13:31:19.08/vabw/8 2006.257.13:31:19.23/vbbw/8 2006.257.13:31:19.33/xfe/off,on,15.5 2006.257.13:31:19.70/ifatt/23,28,28,28 2006.257.13:31:20.07/fmout-gps/S +4.61E-07 2006.257.13:31:20.11:!2006.257.13:32:26 2006.257.13:32:26.01:data_valid=off 2006.257.13:32:26.01:"et 2006.257.13:32:26.01:!+3s 2006.257.13:32:29.02:"tape 2006.257.13:32:29.02:postob 2006.257.13:32:29.23/cable/+6.4808E-03 2006.257.13:32:29.23/wx/17.49,1013.9,98 2006.257.13:32:29.29/fmout-gps/S +4.60E-07 2006.257.13:32:29.29:scan_name=257-1334,jd0609,80 2006.257.13:32:29.29:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.257.13:32:31.14#flagr#flagr/antenna,new-source 2006.257.13:32:31.14:checkk5 2006.257.13:32:31.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:32:31.89/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:32:32.32/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:32:32.72/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:32:33.11/chk_obsdata//k5ts1/T2571331??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.13:32:33.50/chk_obsdata//k5ts2/T2571331??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.13:32:33.90/chk_obsdata//k5ts3/T2571331??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.13:32:34.31/chk_obsdata//k5ts4/T2571331??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.13:32:35.01/k5log//k5ts1_log_newline 2006.257.13:32:35.72/k5log//k5ts2_log_newline 2006.257.13:32:36.43/k5log//k5ts3_log_newline 2006.257.13:32:37.13/k5log//k5ts4_log_newline 2006.257.13:32:37.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:32:37.16:setupk4=1 2006.257.13:32:37.16$setupk4/echo=on 2006.257.13:32:37.16$setupk4/pcalon 2006.257.13:32:37.16$pcalon/"no phase cal control is implemented here 2006.257.13:32:37.16$setupk4/"tpicd=stop 2006.257.13:32:37.16$setupk4/"rec=synch_on 2006.257.13:32:37.16$setupk4/"rec_mode=128 2006.257.13:32:37.16$setupk4/!* 2006.257.13:32:37.16$setupk4/recpk4 2006.257.13:32:37.16$recpk4/recpatch= 2006.257.13:32:37.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:32:37.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:32:37.16$setupk4/vck44 2006.257.13:32:37.16$vck44/valo=1,524.99 2006.257.13:32:37.16#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.13:32:37.16#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.13:32:37.16#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:37.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:37.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:37.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:37.16#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:32:37.16#ibcon#first serial, iclass 40, count 0 2006.257.13:32:37.16#ibcon#enter sib2, iclass 40, count 0 2006.257.13:32:37.16#ibcon#flushed, iclass 40, count 0 2006.257.13:32:37.16#ibcon#about to write, iclass 40, count 0 2006.257.13:32:37.16#ibcon#wrote, iclass 40, count 0 2006.257.13:32:37.16#ibcon#about to read 3, iclass 40, count 0 2006.257.13:32:37.18#ibcon#read 3, iclass 40, count 0 2006.257.13:32:37.18#ibcon#about to read 4, iclass 40, count 0 2006.257.13:32:37.18#ibcon#read 4, iclass 40, count 0 2006.257.13:32:37.18#ibcon#about to read 5, iclass 40, count 0 2006.257.13:32:37.18#ibcon#read 5, iclass 40, count 0 2006.257.13:32:37.18#ibcon#about to read 6, iclass 40, count 0 2006.257.13:32:37.18#ibcon#read 6, iclass 40, count 0 2006.257.13:32:37.18#ibcon#end of sib2, iclass 40, count 0 2006.257.13:32:37.18#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:32:37.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:32:37.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:32:37.18#ibcon#*before write, iclass 40, count 0 2006.257.13:32:37.18#ibcon#enter sib2, iclass 40, count 0 2006.257.13:32:37.18#ibcon#flushed, iclass 40, count 0 2006.257.13:32:37.18#ibcon#about to write, iclass 40, count 0 2006.257.13:32:37.18#ibcon#wrote, iclass 40, count 0 2006.257.13:32:37.18#ibcon#about to read 3, iclass 40, count 0 2006.257.13:32:37.23#ibcon#read 3, iclass 40, count 0 2006.257.13:32:37.23#ibcon#about to read 4, iclass 40, count 0 2006.257.13:32:37.23#ibcon#read 4, iclass 40, count 0 2006.257.13:32:37.23#ibcon#about to read 5, iclass 40, count 0 2006.257.13:32:37.23#ibcon#read 5, iclass 40, count 0 2006.257.13:32:37.23#ibcon#about to read 6, iclass 40, count 0 2006.257.13:32:37.23#ibcon#read 6, iclass 40, count 0 2006.257.13:32:37.23#ibcon#end of sib2, iclass 40, count 0 2006.257.13:32:37.23#ibcon#*after write, iclass 40, count 0 2006.257.13:32:37.23#ibcon#*before return 0, iclass 40, count 0 2006.257.13:32:37.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:37.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:37.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:32:37.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:32:37.23$vck44/va=1,8 2006.257.13:32:37.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.13:32:37.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.13:32:37.23#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:37.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:37.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:37.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:37.23#ibcon#enter wrdev, iclass 4, count 2 2006.257.13:32:37.23#ibcon#first serial, iclass 4, count 2 2006.257.13:32:37.23#ibcon#enter sib2, iclass 4, count 2 2006.257.13:32:37.23#ibcon#flushed, iclass 4, count 2 2006.257.13:32:37.23#ibcon#about to write, iclass 4, count 2 2006.257.13:32:37.23#ibcon#wrote, iclass 4, count 2 2006.257.13:32:37.23#ibcon#about to read 3, iclass 4, count 2 2006.257.13:32:37.25#ibcon#read 3, iclass 4, count 2 2006.257.13:32:37.25#ibcon#about to read 4, iclass 4, count 2 2006.257.13:32:37.25#ibcon#read 4, iclass 4, count 2 2006.257.13:32:37.25#ibcon#about to read 5, iclass 4, count 2 2006.257.13:32:37.25#ibcon#read 5, iclass 4, count 2 2006.257.13:32:37.25#ibcon#about to read 6, iclass 4, count 2 2006.257.13:32:37.25#ibcon#read 6, iclass 4, count 2 2006.257.13:32:37.25#ibcon#end of sib2, iclass 4, count 2 2006.257.13:32:37.25#ibcon#*mode == 0, iclass 4, count 2 2006.257.13:32:37.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.13:32:37.25#ibcon#[25=AT01-08\r\n] 2006.257.13:32:37.25#ibcon#*before write, iclass 4, count 2 2006.257.13:32:37.25#ibcon#enter sib2, iclass 4, count 2 2006.257.13:32:37.25#ibcon#flushed, iclass 4, count 2 2006.257.13:32:37.25#ibcon#about to write, iclass 4, count 2 2006.257.13:32:37.25#ibcon#wrote, iclass 4, count 2 2006.257.13:32:37.25#ibcon#about to read 3, iclass 4, count 2 2006.257.13:32:37.28#ibcon#read 3, iclass 4, count 2 2006.257.13:32:37.28#ibcon#about to read 4, iclass 4, count 2 2006.257.13:32:37.28#ibcon#read 4, iclass 4, count 2 2006.257.13:32:37.28#ibcon#about to read 5, iclass 4, count 2 2006.257.13:32:37.28#ibcon#read 5, iclass 4, count 2 2006.257.13:32:37.28#ibcon#about to read 6, iclass 4, count 2 2006.257.13:32:37.28#ibcon#read 6, iclass 4, count 2 2006.257.13:32:37.28#ibcon#end of sib2, iclass 4, count 2 2006.257.13:32:37.28#ibcon#*after write, iclass 4, count 2 2006.257.13:32:37.28#ibcon#*before return 0, iclass 4, count 2 2006.257.13:32:37.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:37.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:37.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.13:32:37.28#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:37.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:37.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:37.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:37.40#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:32:37.40#ibcon#first serial, iclass 4, count 0 2006.257.13:32:37.40#ibcon#enter sib2, iclass 4, count 0 2006.257.13:32:37.40#ibcon#flushed, iclass 4, count 0 2006.257.13:32:37.40#ibcon#about to write, iclass 4, count 0 2006.257.13:32:37.40#ibcon#wrote, iclass 4, count 0 2006.257.13:32:37.40#ibcon#about to read 3, iclass 4, count 0 2006.257.13:32:37.42#ibcon#read 3, iclass 4, count 0 2006.257.13:32:37.42#ibcon#about to read 4, iclass 4, count 0 2006.257.13:32:37.42#ibcon#read 4, iclass 4, count 0 2006.257.13:32:37.42#ibcon#about to read 5, iclass 4, count 0 2006.257.13:32:37.42#ibcon#read 5, iclass 4, count 0 2006.257.13:32:37.42#ibcon#about to read 6, iclass 4, count 0 2006.257.13:32:37.42#ibcon#read 6, iclass 4, count 0 2006.257.13:32:37.42#ibcon#end of sib2, iclass 4, count 0 2006.257.13:32:37.42#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:32:37.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:32:37.42#ibcon#[25=USB\r\n] 2006.257.13:32:37.42#ibcon#*before write, iclass 4, count 0 2006.257.13:32:37.42#ibcon#enter sib2, iclass 4, count 0 2006.257.13:32:37.42#ibcon#flushed, iclass 4, count 0 2006.257.13:32:37.42#ibcon#about to write, iclass 4, count 0 2006.257.13:32:37.42#ibcon#wrote, iclass 4, count 0 2006.257.13:32:37.42#ibcon#about to read 3, iclass 4, count 0 2006.257.13:32:37.45#ibcon#read 3, iclass 4, count 0 2006.257.13:32:37.45#ibcon#about to read 4, iclass 4, count 0 2006.257.13:32:37.45#ibcon#read 4, iclass 4, count 0 2006.257.13:32:37.45#ibcon#about to read 5, iclass 4, count 0 2006.257.13:32:37.45#ibcon#read 5, iclass 4, count 0 2006.257.13:32:37.45#ibcon#about to read 6, iclass 4, count 0 2006.257.13:32:37.45#ibcon#read 6, iclass 4, count 0 2006.257.13:32:37.45#ibcon#end of sib2, iclass 4, count 0 2006.257.13:32:37.45#ibcon#*after write, iclass 4, count 0 2006.257.13:32:37.45#ibcon#*before return 0, iclass 4, count 0 2006.257.13:32:37.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:37.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:37.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:32:37.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:32:37.45$vck44/valo=2,534.99 2006.257.13:32:37.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.13:32:37.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.13:32:37.45#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:37.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:37.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:37.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:37.45#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:32:37.45#ibcon#first serial, iclass 6, count 0 2006.257.13:32:37.45#ibcon#enter sib2, iclass 6, count 0 2006.257.13:32:37.45#ibcon#flushed, iclass 6, count 0 2006.257.13:32:37.45#ibcon#about to write, iclass 6, count 0 2006.257.13:32:37.45#ibcon#wrote, iclass 6, count 0 2006.257.13:32:37.45#ibcon#about to read 3, iclass 6, count 0 2006.257.13:32:37.47#ibcon#read 3, iclass 6, count 0 2006.257.13:32:37.47#ibcon#about to read 4, iclass 6, count 0 2006.257.13:32:37.47#ibcon#read 4, iclass 6, count 0 2006.257.13:32:37.47#ibcon#about to read 5, iclass 6, count 0 2006.257.13:32:37.47#ibcon#read 5, iclass 6, count 0 2006.257.13:32:37.47#ibcon#about to read 6, iclass 6, count 0 2006.257.13:32:37.47#ibcon#read 6, iclass 6, count 0 2006.257.13:32:37.47#ibcon#end of sib2, iclass 6, count 0 2006.257.13:32:37.47#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:32:37.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:32:37.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:32:37.47#ibcon#*before write, iclass 6, count 0 2006.257.13:32:37.47#ibcon#enter sib2, iclass 6, count 0 2006.257.13:32:37.47#ibcon#flushed, iclass 6, count 0 2006.257.13:32:37.47#ibcon#about to write, iclass 6, count 0 2006.257.13:32:37.47#ibcon#wrote, iclass 6, count 0 2006.257.13:32:37.47#ibcon#about to read 3, iclass 6, count 0 2006.257.13:32:37.51#ibcon#read 3, iclass 6, count 0 2006.257.13:32:37.51#ibcon#about to read 4, iclass 6, count 0 2006.257.13:32:37.51#ibcon#read 4, iclass 6, count 0 2006.257.13:32:37.51#ibcon#about to read 5, iclass 6, count 0 2006.257.13:32:37.51#ibcon#read 5, iclass 6, count 0 2006.257.13:32:37.51#ibcon#about to read 6, iclass 6, count 0 2006.257.13:32:37.51#ibcon#read 6, iclass 6, count 0 2006.257.13:32:37.51#ibcon#end of sib2, iclass 6, count 0 2006.257.13:32:37.51#ibcon#*after write, iclass 6, count 0 2006.257.13:32:37.51#ibcon#*before return 0, iclass 6, count 0 2006.257.13:32:37.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:37.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:37.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:32:37.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:32:37.51$vck44/va=2,7 2006.257.13:32:37.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.13:32:37.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.13:32:37.51#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:37.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:37.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:37.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:37.57#ibcon#enter wrdev, iclass 10, count 2 2006.257.13:32:37.57#ibcon#first serial, iclass 10, count 2 2006.257.13:32:37.57#ibcon#enter sib2, iclass 10, count 2 2006.257.13:32:37.57#ibcon#flushed, iclass 10, count 2 2006.257.13:32:37.57#ibcon#about to write, iclass 10, count 2 2006.257.13:32:37.57#ibcon#wrote, iclass 10, count 2 2006.257.13:32:37.57#ibcon#about to read 3, iclass 10, count 2 2006.257.13:32:37.59#ibcon#read 3, iclass 10, count 2 2006.257.13:32:37.59#ibcon#about to read 4, iclass 10, count 2 2006.257.13:32:37.59#ibcon#read 4, iclass 10, count 2 2006.257.13:32:37.59#ibcon#about to read 5, iclass 10, count 2 2006.257.13:32:37.59#ibcon#read 5, iclass 10, count 2 2006.257.13:32:37.59#ibcon#about to read 6, iclass 10, count 2 2006.257.13:32:37.59#ibcon#read 6, iclass 10, count 2 2006.257.13:32:37.59#ibcon#end of sib2, iclass 10, count 2 2006.257.13:32:37.59#ibcon#*mode == 0, iclass 10, count 2 2006.257.13:32:37.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.13:32:37.59#ibcon#[25=AT02-07\r\n] 2006.257.13:32:37.59#ibcon#*before write, iclass 10, count 2 2006.257.13:32:37.59#ibcon#enter sib2, iclass 10, count 2 2006.257.13:32:37.59#ibcon#flushed, iclass 10, count 2 2006.257.13:32:37.59#ibcon#about to write, iclass 10, count 2 2006.257.13:32:37.59#ibcon#wrote, iclass 10, count 2 2006.257.13:32:37.59#ibcon#about to read 3, iclass 10, count 2 2006.257.13:32:37.62#ibcon#read 3, iclass 10, count 2 2006.257.13:32:37.62#ibcon#about to read 4, iclass 10, count 2 2006.257.13:32:37.62#ibcon#read 4, iclass 10, count 2 2006.257.13:32:37.62#ibcon#about to read 5, iclass 10, count 2 2006.257.13:32:37.62#ibcon#read 5, iclass 10, count 2 2006.257.13:32:37.62#ibcon#about to read 6, iclass 10, count 2 2006.257.13:32:37.62#ibcon#read 6, iclass 10, count 2 2006.257.13:32:37.62#ibcon#end of sib2, iclass 10, count 2 2006.257.13:32:37.62#ibcon#*after write, iclass 10, count 2 2006.257.13:32:37.62#ibcon#*before return 0, iclass 10, count 2 2006.257.13:32:37.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:37.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:37.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.13:32:37.62#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:37.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:37.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:37.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:37.74#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:32:37.74#ibcon#first serial, iclass 10, count 0 2006.257.13:32:37.74#ibcon#enter sib2, iclass 10, count 0 2006.257.13:32:37.74#ibcon#flushed, iclass 10, count 0 2006.257.13:32:37.74#ibcon#about to write, iclass 10, count 0 2006.257.13:32:37.74#ibcon#wrote, iclass 10, count 0 2006.257.13:32:37.74#ibcon#about to read 3, iclass 10, count 0 2006.257.13:32:37.76#ibcon#read 3, iclass 10, count 0 2006.257.13:32:37.76#ibcon#about to read 4, iclass 10, count 0 2006.257.13:32:37.76#ibcon#read 4, iclass 10, count 0 2006.257.13:32:37.76#ibcon#about to read 5, iclass 10, count 0 2006.257.13:32:37.76#ibcon#read 5, iclass 10, count 0 2006.257.13:32:37.76#ibcon#about to read 6, iclass 10, count 0 2006.257.13:32:37.76#ibcon#read 6, iclass 10, count 0 2006.257.13:32:37.76#ibcon#end of sib2, iclass 10, count 0 2006.257.13:32:37.76#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:32:37.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:32:37.76#ibcon#[25=USB\r\n] 2006.257.13:32:37.76#ibcon#*before write, iclass 10, count 0 2006.257.13:32:37.76#ibcon#enter sib2, iclass 10, count 0 2006.257.13:32:37.76#ibcon#flushed, iclass 10, count 0 2006.257.13:32:37.76#ibcon#about to write, iclass 10, count 0 2006.257.13:32:37.76#ibcon#wrote, iclass 10, count 0 2006.257.13:32:37.76#ibcon#about to read 3, iclass 10, count 0 2006.257.13:32:37.79#ibcon#read 3, iclass 10, count 0 2006.257.13:32:37.79#ibcon#about to read 4, iclass 10, count 0 2006.257.13:32:37.79#ibcon#read 4, iclass 10, count 0 2006.257.13:32:37.79#ibcon#about to read 5, iclass 10, count 0 2006.257.13:32:37.79#ibcon#read 5, iclass 10, count 0 2006.257.13:32:37.79#ibcon#about to read 6, iclass 10, count 0 2006.257.13:32:37.79#ibcon#read 6, iclass 10, count 0 2006.257.13:32:37.79#ibcon#end of sib2, iclass 10, count 0 2006.257.13:32:37.79#ibcon#*after write, iclass 10, count 0 2006.257.13:32:37.79#ibcon#*before return 0, iclass 10, count 0 2006.257.13:32:37.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:37.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:37.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:32:37.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:32:37.79$vck44/valo=3,564.99 2006.257.13:32:37.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.13:32:37.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.13:32:37.79#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:37.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:37.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:37.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:37.79#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:32:37.79#ibcon#first serial, iclass 12, count 0 2006.257.13:32:37.79#ibcon#enter sib2, iclass 12, count 0 2006.257.13:32:37.79#ibcon#flushed, iclass 12, count 0 2006.257.13:32:37.79#ibcon#about to write, iclass 12, count 0 2006.257.13:32:37.79#ibcon#wrote, iclass 12, count 0 2006.257.13:32:37.79#ibcon#about to read 3, iclass 12, count 0 2006.257.13:32:37.81#ibcon#read 3, iclass 12, count 0 2006.257.13:32:37.81#ibcon#about to read 4, iclass 12, count 0 2006.257.13:32:37.81#ibcon#read 4, iclass 12, count 0 2006.257.13:32:37.81#ibcon#about to read 5, iclass 12, count 0 2006.257.13:32:37.81#ibcon#read 5, iclass 12, count 0 2006.257.13:32:37.81#ibcon#about to read 6, iclass 12, count 0 2006.257.13:32:37.81#ibcon#read 6, iclass 12, count 0 2006.257.13:32:37.81#ibcon#end of sib2, iclass 12, count 0 2006.257.13:32:37.81#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:32:37.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:32:37.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:32:37.81#ibcon#*before write, iclass 12, count 0 2006.257.13:32:37.81#ibcon#enter sib2, iclass 12, count 0 2006.257.13:32:37.81#ibcon#flushed, iclass 12, count 0 2006.257.13:32:37.81#ibcon#about to write, iclass 12, count 0 2006.257.13:32:37.81#ibcon#wrote, iclass 12, count 0 2006.257.13:32:37.81#ibcon#about to read 3, iclass 12, count 0 2006.257.13:32:37.85#ibcon#read 3, iclass 12, count 0 2006.257.13:32:37.85#ibcon#about to read 4, iclass 12, count 0 2006.257.13:32:37.85#ibcon#read 4, iclass 12, count 0 2006.257.13:32:37.85#ibcon#about to read 5, iclass 12, count 0 2006.257.13:32:37.85#ibcon#read 5, iclass 12, count 0 2006.257.13:32:37.85#ibcon#about to read 6, iclass 12, count 0 2006.257.13:32:37.85#ibcon#read 6, iclass 12, count 0 2006.257.13:32:37.85#ibcon#end of sib2, iclass 12, count 0 2006.257.13:32:37.85#ibcon#*after write, iclass 12, count 0 2006.257.13:32:37.85#ibcon#*before return 0, iclass 12, count 0 2006.257.13:32:37.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:37.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:37.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:32:37.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:32:37.85$vck44/va=3,8 2006.257.13:32:37.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.13:32:37.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.13:32:37.85#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:37.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:37.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:37.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:37.91#ibcon#enter wrdev, iclass 14, count 2 2006.257.13:32:37.91#ibcon#first serial, iclass 14, count 2 2006.257.13:32:37.91#ibcon#enter sib2, iclass 14, count 2 2006.257.13:32:37.91#ibcon#flushed, iclass 14, count 2 2006.257.13:32:37.91#ibcon#about to write, iclass 14, count 2 2006.257.13:32:37.91#ibcon#wrote, iclass 14, count 2 2006.257.13:32:37.91#ibcon#about to read 3, iclass 14, count 2 2006.257.13:32:37.93#ibcon#read 3, iclass 14, count 2 2006.257.13:32:37.93#ibcon#about to read 4, iclass 14, count 2 2006.257.13:32:37.93#ibcon#read 4, iclass 14, count 2 2006.257.13:32:37.93#ibcon#about to read 5, iclass 14, count 2 2006.257.13:32:37.93#ibcon#read 5, iclass 14, count 2 2006.257.13:32:37.93#ibcon#about to read 6, iclass 14, count 2 2006.257.13:32:37.93#ibcon#read 6, iclass 14, count 2 2006.257.13:32:37.93#ibcon#end of sib2, iclass 14, count 2 2006.257.13:32:37.93#ibcon#*mode == 0, iclass 14, count 2 2006.257.13:32:37.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.13:32:37.93#ibcon#[25=AT03-08\r\n] 2006.257.13:32:37.93#ibcon#*before write, iclass 14, count 2 2006.257.13:32:37.93#ibcon#enter sib2, iclass 14, count 2 2006.257.13:32:37.93#ibcon#flushed, iclass 14, count 2 2006.257.13:32:37.93#ibcon#about to write, iclass 14, count 2 2006.257.13:32:37.93#ibcon#wrote, iclass 14, count 2 2006.257.13:32:37.93#ibcon#about to read 3, iclass 14, count 2 2006.257.13:32:37.96#ibcon#read 3, iclass 14, count 2 2006.257.13:32:37.96#ibcon#about to read 4, iclass 14, count 2 2006.257.13:32:37.96#ibcon#read 4, iclass 14, count 2 2006.257.13:32:37.96#ibcon#about to read 5, iclass 14, count 2 2006.257.13:32:37.96#ibcon#read 5, iclass 14, count 2 2006.257.13:32:37.96#ibcon#about to read 6, iclass 14, count 2 2006.257.13:32:37.96#ibcon#read 6, iclass 14, count 2 2006.257.13:32:37.96#ibcon#end of sib2, iclass 14, count 2 2006.257.13:32:37.96#ibcon#*after write, iclass 14, count 2 2006.257.13:32:37.96#ibcon#*before return 0, iclass 14, count 2 2006.257.13:32:37.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:37.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:37.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.13:32:37.96#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:37.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:38.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:38.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:38.08#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:32:38.08#ibcon#first serial, iclass 14, count 0 2006.257.13:32:38.08#ibcon#enter sib2, iclass 14, count 0 2006.257.13:32:38.08#ibcon#flushed, iclass 14, count 0 2006.257.13:32:38.08#ibcon#about to write, iclass 14, count 0 2006.257.13:32:38.08#ibcon#wrote, iclass 14, count 0 2006.257.13:32:38.08#ibcon#about to read 3, iclass 14, count 0 2006.257.13:32:38.10#ibcon#read 3, iclass 14, count 0 2006.257.13:32:38.10#ibcon#about to read 4, iclass 14, count 0 2006.257.13:32:38.10#ibcon#read 4, iclass 14, count 0 2006.257.13:32:38.10#ibcon#about to read 5, iclass 14, count 0 2006.257.13:32:38.10#ibcon#read 5, iclass 14, count 0 2006.257.13:32:38.10#ibcon#about to read 6, iclass 14, count 0 2006.257.13:32:38.10#ibcon#read 6, iclass 14, count 0 2006.257.13:32:38.10#ibcon#end of sib2, iclass 14, count 0 2006.257.13:32:38.10#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:32:38.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:32:38.10#ibcon#[25=USB\r\n] 2006.257.13:32:38.10#ibcon#*before write, iclass 14, count 0 2006.257.13:32:38.10#ibcon#enter sib2, iclass 14, count 0 2006.257.13:32:38.10#ibcon#flushed, iclass 14, count 0 2006.257.13:32:38.10#ibcon#about to write, iclass 14, count 0 2006.257.13:32:38.10#ibcon#wrote, iclass 14, count 0 2006.257.13:32:38.10#ibcon#about to read 3, iclass 14, count 0 2006.257.13:32:38.13#ibcon#read 3, iclass 14, count 0 2006.257.13:32:38.13#ibcon#about to read 4, iclass 14, count 0 2006.257.13:32:38.13#ibcon#read 4, iclass 14, count 0 2006.257.13:32:38.13#ibcon#about to read 5, iclass 14, count 0 2006.257.13:32:38.13#ibcon#read 5, iclass 14, count 0 2006.257.13:32:38.13#ibcon#about to read 6, iclass 14, count 0 2006.257.13:32:38.13#ibcon#read 6, iclass 14, count 0 2006.257.13:32:38.13#ibcon#end of sib2, iclass 14, count 0 2006.257.13:32:38.13#ibcon#*after write, iclass 14, count 0 2006.257.13:32:38.13#ibcon#*before return 0, iclass 14, count 0 2006.257.13:32:38.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:38.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:38.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:32:38.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:32:38.13$vck44/valo=4,624.99 2006.257.13:32:38.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.13:32:38.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.13:32:38.13#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:38.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:38.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:38.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:38.13#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:32:38.13#ibcon#first serial, iclass 16, count 0 2006.257.13:32:38.13#ibcon#enter sib2, iclass 16, count 0 2006.257.13:32:38.13#ibcon#flushed, iclass 16, count 0 2006.257.13:32:38.13#ibcon#about to write, iclass 16, count 0 2006.257.13:32:38.13#ibcon#wrote, iclass 16, count 0 2006.257.13:32:38.13#ibcon#about to read 3, iclass 16, count 0 2006.257.13:32:38.15#ibcon#read 3, iclass 16, count 0 2006.257.13:32:38.15#ibcon#about to read 4, iclass 16, count 0 2006.257.13:32:38.15#ibcon#read 4, iclass 16, count 0 2006.257.13:32:38.15#ibcon#about to read 5, iclass 16, count 0 2006.257.13:32:38.15#ibcon#read 5, iclass 16, count 0 2006.257.13:32:38.15#ibcon#about to read 6, iclass 16, count 0 2006.257.13:32:38.15#ibcon#read 6, iclass 16, count 0 2006.257.13:32:38.15#ibcon#end of sib2, iclass 16, count 0 2006.257.13:32:38.15#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:32:38.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:32:38.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:32:38.15#ibcon#*before write, iclass 16, count 0 2006.257.13:32:38.15#ibcon#enter sib2, iclass 16, count 0 2006.257.13:32:38.15#ibcon#flushed, iclass 16, count 0 2006.257.13:32:38.15#ibcon#about to write, iclass 16, count 0 2006.257.13:32:38.15#ibcon#wrote, iclass 16, count 0 2006.257.13:32:38.15#ibcon#about to read 3, iclass 16, count 0 2006.257.13:32:38.19#ibcon#read 3, iclass 16, count 0 2006.257.13:32:38.19#ibcon#about to read 4, iclass 16, count 0 2006.257.13:32:38.19#ibcon#read 4, iclass 16, count 0 2006.257.13:32:38.19#ibcon#about to read 5, iclass 16, count 0 2006.257.13:32:38.19#ibcon#read 5, iclass 16, count 0 2006.257.13:32:38.19#ibcon#about to read 6, iclass 16, count 0 2006.257.13:32:38.19#ibcon#read 6, iclass 16, count 0 2006.257.13:32:38.19#ibcon#end of sib2, iclass 16, count 0 2006.257.13:32:38.19#ibcon#*after write, iclass 16, count 0 2006.257.13:32:38.19#ibcon#*before return 0, iclass 16, count 0 2006.257.13:32:38.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:38.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:38.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:32:38.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:32:38.19$vck44/va=4,7 2006.257.13:32:38.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.13:32:38.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.13:32:38.19#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:38.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:38.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:38.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:38.25#ibcon#enter wrdev, iclass 18, count 2 2006.257.13:32:38.25#ibcon#first serial, iclass 18, count 2 2006.257.13:32:38.25#ibcon#enter sib2, iclass 18, count 2 2006.257.13:32:38.25#ibcon#flushed, iclass 18, count 2 2006.257.13:32:38.25#ibcon#about to write, iclass 18, count 2 2006.257.13:32:38.25#ibcon#wrote, iclass 18, count 2 2006.257.13:32:38.25#ibcon#about to read 3, iclass 18, count 2 2006.257.13:32:38.27#ibcon#read 3, iclass 18, count 2 2006.257.13:32:38.27#ibcon#about to read 4, iclass 18, count 2 2006.257.13:32:38.27#ibcon#read 4, iclass 18, count 2 2006.257.13:32:38.27#ibcon#about to read 5, iclass 18, count 2 2006.257.13:32:38.27#ibcon#read 5, iclass 18, count 2 2006.257.13:32:38.27#ibcon#about to read 6, iclass 18, count 2 2006.257.13:32:38.27#ibcon#read 6, iclass 18, count 2 2006.257.13:32:38.27#ibcon#end of sib2, iclass 18, count 2 2006.257.13:32:38.27#ibcon#*mode == 0, iclass 18, count 2 2006.257.13:32:38.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.13:32:38.27#ibcon#[25=AT04-07\r\n] 2006.257.13:32:38.27#ibcon#*before write, iclass 18, count 2 2006.257.13:32:38.27#ibcon#enter sib2, iclass 18, count 2 2006.257.13:32:38.27#ibcon#flushed, iclass 18, count 2 2006.257.13:32:38.27#ibcon#about to write, iclass 18, count 2 2006.257.13:32:38.27#ibcon#wrote, iclass 18, count 2 2006.257.13:32:38.27#ibcon#about to read 3, iclass 18, count 2 2006.257.13:32:38.30#ibcon#read 3, iclass 18, count 2 2006.257.13:32:38.30#ibcon#about to read 4, iclass 18, count 2 2006.257.13:32:38.36#ibcon#read 4, iclass 18, count 2 2006.257.13:32:38.36#ibcon#about to read 5, iclass 18, count 2 2006.257.13:32:38.36#ibcon#read 5, iclass 18, count 2 2006.257.13:32:38.36#ibcon#about to read 6, iclass 18, count 2 2006.257.13:32:38.36#ibcon#read 6, iclass 18, count 2 2006.257.13:32:38.36#ibcon#end of sib2, iclass 18, count 2 2006.257.13:32:38.36#ibcon#*after write, iclass 18, count 2 2006.257.13:32:38.36#ibcon#*before return 0, iclass 18, count 2 2006.257.13:32:38.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:38.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:38.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.13:32:38.36#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:38.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:38.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:38.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:38.47#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:32:38.47#ibcon#first serial, iclass 18, count 0 2006.257.13:32:38.47#ibcon#enter sib2, iclass 18, count 0 2006.257.13:32:38.47#ibcon#flushed, iclass 18, count 0 2006.257.13:32:38.47#ibcon#about to write, iclass 18, count 0 2006.257.13:32:38.47#ibcon#wrote, iclass 18, count 0 2006.257.13:32:38.47#ibcon#about to read 3, iclass 18, count 0 2006.257.13:32:38.49#ibcon#read 3, iclass 18, count 0 2006.257.13:32:38.49#ibcon#about to read 4, iclass 18, count 0 2006.257.13:32:38.49#ibcon#read 4, iclass 18, count 0 2006.257.13:32:38.49#ibcon#about to read 5, iclass 18, count 0 2006.257.13:32:38.49#ibcon#read 5, iclass 18, count 0 2006.257.13:32:38.49#ibcon#about to read 6, iclass 18, count 0 2006.257.13:32:38.49#ibcon#read 6, iclass 18, count 0 2006.257.13:32:38.49#ibcon#end of sib2, iclass 18, count 0 2006.257.13:32:38.49#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:32:38.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:32:38.49#ibcon#[25=USB\r\n] 2006.257.13:32:38.49#ibcon#*before write, iclass 18, count 0 2006.257.13:32:38.49#ibcon#enter sib2, iclass 18, count 0 2006.257.13:32:38.49#ibcon#flushed, iclass 18, count 0 2006.257.13:32:38.49#ibcon#about to write, iclass 18, count 0 2006.257.13:32:38.49#ibcon#wrote, iclass 18, count 0 2006.257.13:32:38.49#ibcon#about to read 3, iclass 18, count 0 2006.257.13:32:38.52#ibcon#read 3, iclass 18, count 0 2006.257.13:32:38.52#ibcon#about to read 4, iclass 18, count 0 2006.257.13:32:38.52#ibcon#read 4, iclass 18, count 0 2006.257.13:32:38.52#ibcon#about to read 5, iclass 18, count 0 2006.257.13:32:38.52#ibcon#read 5, iclass 18, count 0 2006.257.13:32:38.52#ibcon#about to read 6, iclass 18, count 0 2006.257.13:32:38.52#ibcon#read 6, iclass 18, count 0 2006.257.13:32:38.52#ibcon#end of sib2, iclass 18, count 0 2006.257.13:32:38.52#ibcon#*after write, iclass 18, count 0 2006.257.13:32:38.52#ibcon#*before return 0, iclass 18, count 0 2006.257.13:32:38.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:38.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:38.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:32:38.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:32:38.52$vck44/valo=5,734.99 2006.257.13:32:38.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.13:32:38.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.13:32:38.52#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:38.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:38.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:38.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:38.52#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:32:38.52#ibcon#first serial, iclass 20, count 0 2006.257.13:32:38.52#ibcon#enter sib2, iclass 20, count 0 2006.257.13:32:38.52#ibcon#flushed, iclass 20, count 0 2006.257.13:32:38.52#ibcon#about to write, iclass 20, count 0 2006.257.13:32:38.52#ibcon#wrote, iclass 20, count 0 2006.257.13:32:38.52#ibcon#about to read 3, iclass 20, count 0 2006.257.13:32:38.54#ibcon#read 3, iclass 20, count 0 2006.257.13:32:38.54#ibcon#about to read 4, iclass 20, count 0 2006.257.13:32:38.54#ibcon#read 4, iclass 20, count 0 2006.257.13:32:38.54#ibcon#about to read 5, iclass 20, count 0 2006.257.13:32:38.54#ibcon#read 5, iclass 20, count 0 2006.257.13:32:38.54#ibcon#about to read 6, iclass 20, count 0 2006.257.13:32:38.54#ibcon#read 6, iclass 20, count 0 2006.257.13:32:38.54#ibcon#end of sib2, iclass 20, count 0 2006.257.13:32:38.54#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:32:38.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:32:38.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:32:38.54#ibcon#*before write, iclass 20, count 0 2006.257.13:32:38.54#ibcon#enter sib2, iclass 20, count 0 2006.257.13:32:38.54#ibcon#flushed, iclass 20, count 0 2006.257.13:32:38.54#ibcon#about to write, iclass 20, count 0 2006.257.13:32:38.54#ibcon#wrote, iclass 20, count 0 2006.257.13:32:38.54#ibcon#about to read 3, iclass 20, count 0 2006.257.13:32:38.58#ibcon#read 3, iclass 20, count 0 2006.257.13:32:38.58#ibcon#about to read 4, iclass 20, count 0 2006.257.13:32:38.58#ibcon#read 4, iclass 20, count 0 2006.257.13:32:38.58#ibcon#about to read 5, iclass 20, count 0 2006.257.13:32:38.58#ibcon#read 5, iclass 20, count 0 2006.257.13:32:38.58#ibcon#about to read 6, iclass 20, count 0 2006.257.13:32:38.58#ibcon#read 6, iclass 20, count 0 2006.257.13:32:38.58#ibcon#end of sib2, iclass 20, count 0 2006.257.13:32:38.58#ibcon#*after write, iclass 20, count 0 2006.257.13:32:38.58#ibcon#*before return 0, iclass 20, count 0 2006.257.13:32:38.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:38.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:38.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:32:38.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:32:38.58$vck44/va=5,4 2006.257.13:32:38.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.13:32:38.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.13:32:38.58#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:38.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:38.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:38.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:38.64#ibcon#enter wrdev, iclass 22, count 2 2006.257.13:32:38.64#ibcon#first serial, iclass 22, count 2 2006.257.13:32:38.64#ibcon#enter sib2, iclass 22, count 2 2006.257.13:32:38.64#ibcon#flushed, iclass 22, count 2 2006.257.13:32:38.64#ibcon#about to write, iclass 22, count 2 2006.257.13:32:38.64#ibcon#wrote, iclass 22, count 2 2006.257.13:32:38.64#ibcon#about to read 3, iclass 22, count 2 2006.257.13:32:38.66#ibcon#read 3, iclass 22, count 2 2006.257.13:32:38.66#ibcon#about to read 4, iclass 22, count 2 2006.257.13:32:38.66#ibcon#read 4, iclass 22, count 2 2006.257.13:32:38.66#ibcon#about to read 5, iclass 22, count 2 2006.257.13:32:38.66#ibcon#read 5, iclass 22, count 2 2006.257.13:32:38.66#ibcon#about to read 6, iclass 22, count 2 2006.257.13:32:38.66#ibcon#read 6, iclass 22, count 2 2006.257.13:32:38.66#ibcon#end of sib2, iclass 22, count 2 2006.257.13:32:38.66#ibcon#*mode == 0, iclass 22, count 2 2006.257.13:32:38.66#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.13:32:38.66#ibcon#[25=AT05-04\r\n] 2006.257.13:32:38.66#ibcon#*before write, iclass 22, count 2 2006.257.13:32:38.66#ibcon#enter sib2, iclass 22, count 2 2006.257.13:32:38.66#ibcon#flushed, iclass 22, count 2 2006.257.13:32:38.66#ibcon#about to write, iclass 22, count 2 2006.257.13:32:38.66#ibcon#wrote, iclass 22, count 2 2006.257.13:32:38.66#ibcon#about to read 3, iclass 22, count 2 2006.257.13:32:38.69#ibcon#read 3, iclass 22, count 2 2006.257.13:32:38.69#ibcon#about to read 4, iclass 22, count 2 2006.257.13:32:38.69#ibcon#read 4, iclass 22, count 2 2006.257.13:32:38.69#ibcon#about to read 5, iclass 22, count 2 2006.257.13:32:38.69#ibcon#read 5, iclass 22, count 2 2006.257.13:32:38.69#ibcon#about to read 6, iclass 22, count 2 2006.257.13:32:38.69#ibcon#read 6, iclass 22, count 2 2006.257.13:32:38.69#ibcon#end of sib2, iclass 22, count 2 2006.257.13:32:38.69#ibcon#*after write, iclass 22, count 2 2006.257.13:32:38.69#ibcon#*before return 0, iclass 22, count 2 2006.257.13:32:38.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:38.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:38.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.13:32:38.69#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:38.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:38.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:38.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:38.81#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:32:38.81#ibcon#first serial, iclass 22, count 0 2006.257.13:32:38.81#ibcon#enter sib2, iclass 22, count 0 2006.257.13:32:38.81#ibcon#flushed, iclass 22, count 0 2006.257.13:32:38.81#ibcon#about to write, iclass 22, count 0 2006.257.13:32:38.81#ibcon#wrote, iclass 22, count 0 2006.257.13:32:38.81#ibcon#about to read 3, iclass 22, count 0 2006.257.13:32:38.83#ibcon#read 3, iclass 22, count 0 2006.257.13:32:38.83#ibcon#about to read 4, iclass 22, count 0 2006.257.13:32:38.83#ibcon#read 4, iclass 22, count 0 2006.257.13:32:38.83#ibcon#about to read 5, iclass 22, count 0 2006.257.13:32:38.83#ibcon#read 5, iclass 22, count 0 2006.257.13:32:38.83#ibcon#about to read 6, iclass 22, count 0 2006.257.13:32:38.83#ibcon#read 6, iclass 22, count 0 2006.257.13:32:38.83#ibcon#end of sib2, iclass 22, count 0 2006.257.13:32:38.83#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:32:38.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:32:38.83#ibcon#[25=USB\r\n] 2006.257.13:32:38.83#ibcon#*before write, iclass 22, count 0 2006.257.13:32:38.83#ibcon#enter sib2, iclass 22, count 0 2006.257.13:32:38.83#ibcon#flushed, iclass 22, count 0 2006.257.13:32:38.83#ibcon#about to write, iclass 22, count 0 2006.257.13:32:38.83#ibcon#wrote, iclass 22, count 0 2006.257.13:32:38.83#ibcon#about to read 3, iclass 22, count 0 2006.257.13:32:38.86#ibcon#read 3, iclass 22, count 0 2006.257.13:32:38.86#ibcon#about to read 4, iclass 22, count 0 2006.257.13:32:38.86#ibcon#read 4, iclass 22, count 0 2006.257.13:32:38.86#ibcon#about to read 5, iclass 22, count 0 2006.257.13:32:38.86#ibcon#read 5, iclass 22, count 0 2006.257.13:32:38.86#ibcon#about to read 6, iclass 22, count 0 2006.257.13:32:38.86#ibcon#read 6, iclass 22, count 0 2006.257.13:32:38.86#ibcon#end of sib2, iclass 22, count 0 2006.257.13:32:38.86#ibcon#*after write, iclass 22, count 0 2006.257.13:32:38.86#ibcon#*before return 0, iclass 22, count 0 2006.257.13:32:38.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:38.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:38.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:32:38.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:32:38.86$vck44/valo=6,814.99 2006.257.13:32:38.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.13:32:38.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.13:32:38.86#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:38.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:38.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:38.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:38.86#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:32:38.86#ibcon#first serial, iclass 24, count 0 2006.257.13:32:38.86#ibcon#enter sib2, iclass 24, count 0 2006.257.13:32:38.86#ibcon#flushed, iclass 24, count 0 2006.257.13:32:38.86#ibcon#about to write, iclass 24, count 0 2006.257.13:32:38.86#ibcon#wrote, iclass 24, count 0 2006.257.13:32:38.86#ibcon#about to read 3, iclass 24, count 0 2006.257.13:32:38.88#ibcon#read 3, iclass 24, count 0 2006.257.13:32:38.88#ibcon#about to read 4, iclass 24, count 0 2006.257.13:32:38.88#ibcon#read 4, iclass 24, count 0 2006.257.13:32:38.88#ibcon#about to read 5, iclass 24, count 0 2006.257.13:32:38.88#ibcon#read 5, iclass 24, count 0 2006.257.13:32:38.88#ibcon#about to read 6, iclass 24, count 0 2006.257.13:32:38.88#ibcon#read 6, iclass 24, count 0 2006.257.13:32:38.88#ibcon#end of sib2, iclass 24, count 0 2006.257.13:32:38.88#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:32:38.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:32:38.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:32:38.88#ibcon#*before write, iclass 24, count 0 2006.257.13:32:38.88#ibcon#enter sib2, iclass 24, count 0 2006.257.13:32:38.88#ibcon#flushed, iclass 24, count 0 2006.257.13:32:38.88#ibcon#about to write, iclass 24, count 0 2006.257.13:32:38.88#ibcon#wrote, iclass 24, count 0 2006.257.13:32:38.88#ibcon#about to read 3, iclass 24, count 0 2006.257.13:32:38.92#ibcon#read 3, iclass 24, count 0 2006.257.13:32:38.92#ibcon#about to read 4, iclass 24, count 0 2006.257.13:32:38.92#ibcon#read 4, iclass 24, count 0 2006.257.13:32:38.92#ibcon#about to read 5, iclass 24, count 0 2006.257.13:32:38.92#ibcon#read 5, iclass 24, count 0 2006.257.13:32:38.92#ibcon#about to read 6, iclass 24, count 0 2006.257.13:32:38.92#ibcon#read 6, iclass 24, count 0 2006.257.13:32:38.92#ibcon#end of sib2, iclass 24, count 0 2006.257.13:32:38.92#ibcon#*after write, iclass 24, count 0 2006.257.13:32:38.92#ibcon#*before return 0, iclass 24, count 0 2006.257.13:32:38.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:38.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:38.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:32:38.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:32:38.92$vck44/va=6,4 2006.257.13:32:38.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.13:32:38.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.13:32:38.92#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:38.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:38.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:38.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:38.98#ibcon#enter wrdev, iclass 26, count 2 2006.257.13:32:38.98#ibcon#first serial, iclass 26, count 2 2006.257.13:32:38.98#ibcon#enter sib2, iclass 26, count 2 2006.257.13:32:38.98#ibcon#flushed, iclass 26, count 2 2006.257.13:32:38.98#ibcon#about to write, iclass 26, count 2 2006.257.13:32:38.98#ibcon#wrote, iclass 26, count 2 2006.257.13:32:38.98#ibcon#about to read 3, iclass 26, count 2 2006.257.13:32:39.00#ibcon#read 3, iclass 26, count 2 2006.257.13:32:39.00#ibcon#about to read 4, iclass 26, count 2 2006.257.13:32:39.00#ibcon#read 4, iclass 26, count 2 2006.257.13:32:39.00#ibcon#about to read 5, iclass 26, count 2 2006.257.13:32:39.00#ibcon#read 5, iclass 26, count 2 2006.257.13:32:39.00#ibcon#about to read 6, iclass 26, count 2 2006.257.13:32:39.00#ibcon#read 6, iclass 26, count 2 2006.257.13:32:39.00#ibcon#end of sib2, iclass 26, count 2 2006.257.13:32:39.00#ibcon#*mode == 0, iclass 26, count 2 2006.257.13:32:39.00#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.13:32:39.00#ibcon#[25=AT06-04\r\n] 2006.257.13:32:39.00#ibcon#*before write, iclass 26, count 2 2006.257.13:32:39.00#ibcon#enter sib2, iclass 26, count 2 2006.257.13:32:39.00#ibcon#flushed, iclass 26, count 2 2006.257.13:32:39.00#ibcon#about to write, iclass 26, count 2 2006.257.13:32:39.00#ibcon#wrote, iclass 26, count 2 2006.257.13:32:39.00#ibcon#about to read 3, iclass 26, count 2 2006.257.13:32:39.03#ibcon#read 3, iclass 26, count 2 2006.257.13:32:39.03#ibcon#about to read 4, iclass 26, count 2 2006.257.13:32:39.03#ibcon#read 4, iclass 26, count 2 2006.257.13:32:39.03#ibcon#about to read 5, iclass 26, count 2 2006.257.13:32:39.03#ibcon#read 5, iclass 26, count 2 2006.257.13:32:39.03#ibcon#about to read 6, iclass 26, count 2 2006.257.13:32:39.03#ibcon#read 6, iclass 26, count 2 2006.257.13:32:39.03#ibcon#end of sib2, iclass 26, count 2 2006.257.13:32:39.03#ibcon#*after write, iclass 26, count 2 2006.257.13:32:39.03#ibcon#*before return 0, iclass 26, count 2 2006.257.13:32:39.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:39.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:39.03#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.13:32:39.03#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:39.03#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:39.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:39.15#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:39.15#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:32:39.15#ibcon#first serial, iclass 26, count 0 2006.257.13:32:39.15#ibcon#enter sib2, iclass 26, count 0 2006.257.13:32:39.15#ibcon#flushed, iclass 26, count 0 2006.257.13:32:39.15#ibcon#about to write, iclass 26, count 0 2006.257.13:32:39.15#ibcon#wrote, iclass 26, count 0 2006.257.13:32:39.15#ibcon#about to read 3, iclass 26, count 0 2006.257.13:32:39.17#ibcon#read 3, iclass 26, count 0 2006.257.13:32:39.17#ibcon#about to read 4, iclass 26, count 0 2006.257.13:32:39.17#ibcon#read 4, iclass 26, count 0 2006.257.13:32:39.17#ibcon#about to read 5, iclass 26, count 0 2006.257.13:32:39.17#ibcon#read 5, iclass 26, count 0 2006.257.13:32:39.17#ibcon#about to read 6, iclass 26, count 0 2006.257.13:32:39.17#ibcon#read 6, iclass 26, count 0 2006.257.13:32:39.17#ibcon#end of sib2, iclass 26, count 0 2006.257.13:32:39.17#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:32:39.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:32:39.17#ibcon#[25=USB\r\n] 2006.257.13:32:39.17#ibcon#*before write, iclass 26, count 0 2006.257.13:32:39.17#ibcon#enter sib2, iclass 26, count 0 2006.257.13:32:39.17#ibcon#flushed, iclass 26, count 0 2006.257.13:32:39.17#ibcon#about to write, iclass 26, count 0 2006.257.13:32:39.17#ibcon#wrote, iclass 26, count 0 2006.257.13:32:39.17#ibcon#about to read 3, iclass 26, count 0 2006.257.13:32:39.20#ibcon#read 3, iclass 26, count 0 2006.257.13:32:39.20#ibcon#about to read 4, iclass 26, count 0 2006.257.13:32:39.20#ibcon#read 4, iclass 26, count 0 2006.257.13:32:39.20#ibcon#about to read 5, iclass 26, count 0 2006.257.13:32:39.20#ibcon#read 5, iclass 26, count 0 2006.257.13:32:39.20#ibcon#about to read 6, iclass 26, count 0 2006.257.13:32:39.20#ibcon#read 6, iclass 26, count 0 2006.257.13:32:39.20#ibcon#end of sib2, iclass 26, count 0 2006.257.13:32:39.20#ibcon#*after write, iclass 26, count 0 2006.257.13:32:39.20#ibcon#*before return 0, iclass 26, count 0 2006.257.13:32:39.20#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:39.20#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:39.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:32:39.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:32:39.20$vck44/valo=7,864.99 2006.257.13:32:39.20#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.13:32:39.20#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.13:32:39.20#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:39.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:39.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:39.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:39.20#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:32:39.20#ibcon#first serial, iclass 28, count 0 2006.257.13:32:39.20#ibcon#enter sib2, iclass 28, count 0 2006.257.13:32:39.20#ibcon#flushed, iclass 28, count 0 2006.257.13:32:39.20#ibcon#about to write, iclass 28, count 0 2006.257.13:32:39.20#ibcon#wrote, iclass 28, count 0 2006.257.13:32:39.20#ibcon#about to read 3, iclass 28, count 0 2006.257.13:32:39.22#ibcon#read 3, iclass 28, count 0 2006.257.13:32:39.22#ibcon#about to read 4, iclass 28, count 0 2006.257.13:32:39.22#ibcon#read 4, iclass 28, count 0 2006.257.13:32:39.22#ibcon#about to read 5, iclass 28, count 0 2006.257.13:32:39.22#ibcon#read 5, iclass 28, count 0 2006.257.13:32:39.22#ibcon#about to read 6, iclass 28, count 0 2006.257.13:32:39.22#ibcon#read 6, iclass 28, count 0 2006.257.13:32:39.22#ibcon#end of sib2, iclass 28, count 0 2006.257.13:32:39.22#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:32:39.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:32:39.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:32:39.22#ibcon#*before write, iclass 28, count 0 2006.257.13:32:39.22#ibcon#enter sib2, iclass 28, count 0 2006.257.13:32:39.22#ibcon#flushed, iclass 28, count 0 2006.257.13:32:39.22#ibcon#about to write, iclass 28, count 0 2006.257.13:32:39.22#ibcon#wrote, iclass 28, count 0 2006.257.13:32:39.22#ibcon#about to read 3, iclass 28, count 0 2006.257.13:32:39.26#ibcon#read 3, iclass 28, count 0 2006.257.13:32:39.26#ibcon#about to read 4, iclass 28, count 0 2006.257.13:32:39.26#ibcon#read 4, iclass 28, count 0 2006.257.13:32:39.26#ibcon#about to read 5, iclass 28, count 0 2006.257.13:32:39.26#ibcon#read 5, iclass 28, count 0 2006.257.13:32:39.26#ibcon#about to read 6, iclass 28, count 0 2006.257.13:32:39.26#ibcon#read 6, iclass 28, count 0 2006.257.13:32:39.26#ibcon#end of sib2, iclass 28, count 0 2006.257.13:32:39.26#ibcon#*after write, iclass 28, count 0 2006.257.13:32:39.26#ibcon#*before return 0, iclass 28, count 0 2006.257.13:32:39.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:39.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:39.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:32:39.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:32:39.26$vck44/va=7,4 2006.257.13:32:39.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.13:32:39.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.13:32:39.26#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:39.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:39.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:39.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:39.32#ibcon#enter wrdev, iclass 30, count 2 2006.257.13:32:39.32#ibcon#first serial, iclass 30, count 2 2006.257.13:32:39.32#ibcon#enter sib2, iclass 30, count 2 2006.257.13:32:39.32#ibcon#flushed, iclass 30, count 2 2006.257.13:32:39.32#ibcon#about to write, iclass 30, count 2 2006.257.13:32:39.32#ibcon#wrote, iclass 30, count 2 2006.257.13:32:39.32#ibcon#about to read 3, iclass 30, count 2 2006.257.13:32:39.34#ibcon#read 3, iclass 30, count 2 2006.257.13:32:39.34#ibcon#about to read 4, iclass 30, count 2 2006.257.13:32:39.34#ibcon#read 4, iclass 30, count 2 2006.257.13:32:39.34#ibcon#about to read 5, iclass 30, count 2 2006.257.13:32:39.34#ibcon#read 5, iclass 30, count 2 2006.257.13:32:39.34#ibcon#about to read 6, iclass 30, count 2 2006.257.13:32:39.34#ibcon#read 6, iclass 30, count 2 2006.257.13:32:39.34#ibcon#end of sib2, iclass 30, count 2 2006.257.13:32:39.34#ibcon#*mode == 0, iclass 30, count 2 2006.257.13:32:39.34#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.13:32:39.34#ibcon#[25=AT07-04\r\n] 2006.257.13:32:39.34#ibcon#*before write, iclass 30, count 2 2006.257.13:32:39.34#ibcon#enter sib2, iclass 30, count 2 2006.257.13:32:39.34#ibcon#flushed, iclass 30, count 2 2006.257.13:32:39.34#ibcon#about to write, iclass 30, count 2 2006.257.13:32:39.34#ibcon#wrote, iclass 30, count 2 2006.257.13:32:39.34#ibcon#about to read 3, iclass 30, count 2 2006.257.13:32:39.37#ibcon#read 3, iclass 30, count 2 2006.257.13:32:39.37#ibcon#about to read 4, iclass 30, count 2 2006.257.13:32:39.37#ibcon#read 4, iclass 30, count 2 2006.257.13:32:39.37#ibcon#about to read 5, iclass 30, count 2 2006.257.13:32:39.37#ibcon#read 5, iclass 30, count 2 2006.257.13:32:39.37#ibcon#about to read 6, iclass 30, count 2 2006.257.13:32:39.37#ibcon#read 6, iclass 30, count 2 2006.257.13:32:39.37#ibcon#end of sib2, iclass 30, count 2 2006.257.13:32:39.37#ibcon#*after write, iclass 30, count 2 2006.257.13:32:39.37#ibcon#*before return 0, iclass 30, count 2 2006.257.13:32:39.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:39.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:39.37#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.13:32:39.37#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:39.37#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:39.49#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:39.49#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:39.49#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:32:39.49#ibcon#first serial, iclass 30, count 0 2006.257.13:32:39.49#ibcon#enter sib2, iclass 30, count 0 2006.257.13:32:39.49#ibcon#flushed, iclass 30, count 0 2006.257.13:32:39.49#ibcon#about to write, iclass 30, count 0 2006.257.13:32:39.49#ibcon#wrote, iclass 30, count 0 2006.257.13:32:39.49#ibcon#about to read 3, iclass 30, count 0 2006.257.13:32:39.51#ibcon#read 3, iclass 30, count 0 2006.257.13:32:39.51#ibcon#about to read 4, iclass 30, count 0 2006.257.13:32:39.51#ibcon#read 4, iclass 30, count 0 2006.257.13:32:39.51#ibcon#about to read 5, iclass 30, count 0 2006.257.13:32:39.51#ibcon#read 5, iclass 30, count 0 2006.257.13:32:39.51#ibcon#about to read 6, iclass 30, count 0 2006.257.13:32:39.51#ibcon#read 6, iclass 30, count 0 2006.257.13:32:39.51#ibcon#end of sib2, iclass 30, count 0 2006.257.13:32:39.51#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:32:39.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:32:39.51#ibcon#[25=USB\r\n] 2006.257.13:32:39.51#ibcon#*before write, iclass 30, count 0 2006.257.13:32:39.51#ibcon#enter sib2, iclass 30, count 0 2006.257.13:32:39.51#ibcon#flushed, iclass 30, count 0 2006.257.13:32:39.51#ibcon#about to write, iclass 30, count 0 2006.257.13:32:39.51#ibcon#wrote, iclass 30, count 0 2006.257.13:32:39.51#ibcon#about to read 3, iclass 30, count 0 2006.257.13:32:39.54#ibcon#read 3, iclass 30, count 0 2006.257.13:32:39.54#ibcon#about to read 4, iclass 30, count 0 2006.257.13:32:39.54#ibcon#read 4, iclass 30, count 0 2006.257.13:32:39.54#ibcon#about to read 5, iclass 30, count 0 2006.257.13:32:39.54#ibcon#read 5, iclass 30, count 0 2006.257.13:32:39.54#ibcon#about to read 6, iclass 30, count 0 2006.257.13:32:39.54#ibcon#read 6, iclass 30, count 0 2006.257.13:32:39.54#ibcon#end of sib2, iclass 30, count 0 2006.257.13:32:39.54#ibcon#*after write, iclass 30, count 0 2006.257.13:32:39.54#ibcon#*before return 0, iclass 30, count 0 2006.257.13:32:39.54#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:39.54#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:39.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:32:39.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:32:39.54$vck44/valo=8,884.99 2006.257.13:32:39.54#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.13:32:39.54#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.13:32:39.54#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:39.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:39.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:39.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:39.54#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:32:39.54#ibcon#first serial, iclass 32, count 0 2006.257.13:32:39.54#ibcon#enter sib2, iclass 32, count 0 2006.257.13:32:39.54#ibcon#flushed, iclass 32, count 0 2006.257.13:32:39.54#ibcon#about to write, iclass 32, count 0 2006.257.13:32:39.54#ibcon#wrote, iclass 32, count 0 2006.257.13:32:39.54#ibcon#about to read 3, iclass 32, count 0 2006.257.13:32:39.56#ibcon#read 3, iclass 32, count 0 2006.257.13:32:39.56#ibcon#about to read 4, iclass 32, count 0 2006.257.13:32:39.56#ibcon#read 4, iclass 32, count 0 2006.257.13:32:39.56#ibcon#about to read 5, iclass 32, count 0 2006.257.13:32:39.56#ibcon#read 5, iclass 32, count 0 2006.257.13:32:39.56#ibcon#about to read 6, iclass 32, count 0 2006.257.13:32:39.56#ibcon#read 6, iclass 32, count 0 2006.257.13:32:39.56#ibcon#end of sib2, iclass 32, count 0 2006.257.13:32:39.56#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:32:39.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:32:39.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:32:39.56#ibcon#*before write, iclass 32, count 0 2006.257.13:32:39.56#ibcon#enter sib2, iclass 32, count 0 2006.257.13:32:39.56#ibcon#flushed, iclass 32, count 0 2006.257.13:32:39.56#ibcon#about to write, iclass 32, count 0 2006.257.13:32:39.56#ibcon#wrote, iclass 32, count 0 2006.257.13:32:39.56#ibcon#about to read 3, iclass 32, count 0 2006.257.13:32:39.60#ibcon#read 3, iclass 32, count 0 2006.257.13:32:39.60#ibcon#about to read 4, iclass 32, count 0 2006.257.13:32:39.60#ibcon#read 4, iclass 32, count 0 2006.257.13:32:39.60#ibcon#about to read 5, iclass 32, count 0 2006.257.13:32:39.60#ibcon#read 5, iclass 32, count 0 2006.257.13:32:39.60#ibcon#about to read 6, iclass 32, count 0 2006.257.13:32:39.60#ibcon#read 6, iclass 32, count 0 2006.257.13:32:39.60#ibcon#end of sib2, iclass 32, count 0 2006.257.13:32:39.60#ibcon#*after write, iclass 32, count 0 2006.257.13:32:39.60#ibcon#*before return 0, iclass 32, count 0 2006.257.13:32:39.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:39.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:39.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:32:39.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:32:39.60$vck44/va=8,4 2006.257.13:32:39.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.13:32:39.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.13:32:39.60#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:39.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:32:39.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:32:39.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:32:39.66#ibcon#enter wrdev, iclass 34, count 2 2006.257.13:32:39.66#ibcon#first serial, iclass 34, count 2 2006.257.13:32:39.66#ibcon#enter sib2, iclass 34, count 2 2006.257.13:32:39.66#ibcon#flushed, iclass 34, count 2 2006.257.13:32:39.66#ibcon#about to write, iclass 34, count 2 2006.257.13:32:39.66#ibcon#wrote, iclass 34, count 2 2006.257.13:32:39.66#ibcon#about to read 3, iclass 34, count 2 2006.257.13:32:39.68#ibcon#read 3, iclass 34, count 2 2006.257.13:32:39.68#ibcon#about to read 4, iclass 34, count 2 2006.257.13:32:39.68#ibcon#read 4, iclass 34, count 2 2006.257.13:32:39.68#ibcon#about to read 5, iclass 34, count 2 2006.257.13:32:39.68#ibcon#read 5, iclass 34, count 2 2006.257.13:32:39.68#ibcon#about to read 6, iclass 34, count 2 2006.257.13:32:39.68#ibcon#read 6, iclass 34, count 2 2006.257.13:32:39.68#ibcon#end of sib2, iclass 34, count 2 2006.257.13:32:39.68#ibcon#*mode == 0, iclass 34, count 2 2006.257.13:32:39.68#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.13:32:39.68#ibcon#[25=AT08-04\r\n] 2006.257.13:32:39.68#ibcon#*before write, iclass 34, count 2 2006.257.13:32:39.68#ibcon#enter sib2, iclass 34, count 2 2006.257.13:32:39.68#ibcon#flushed, iclass 34, count 2 2006.257.13:32:39.68#ibcon#about to write, iclass 34, count 2 2006.257.13:32:39.68#ibcon#wrote, iclass 34, count 2 2006.257.13:32:39.68#ibcon#about to read 3, iclass 34, count 2 2006.257.13:32:39.71#ibcon#read 3, iclass 34, count 2 2006.257.13:32:39.71#ibcon#about to read 4, iclass 34, count 2 2006.257.13:32:39.71#ibcon#read 4, iclass 34, count 2 2006.257.13:32:39.71#ibcon#about to read 5, iclass 34, count 2 2006.257.13:32:39.71#ibcon#read 5, iclass 34, count 2 2006.257.13:32:39.71#ibcon#about to read 6, iclass 34, count 2 2006.257.13:32:39.71#ibcon#read 6, iclass 34, count 2 2006.257.13:32:39.71#ibcon#end of sib2, iclass 34, count 2 2006.257.13:32:39.71#ibcon#*after write, iclass 34, count 2 2006.257.13:32:39.71#ibcon#*before return 0, iclass 34, count 2 2006.257.13:32:39.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:32:39.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:32:39.71#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.13:32:39.71#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:39.71#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:32:39.83#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:32:39.83#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:32:39.83#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:32:39.83#ibcon#first serial, iclass 34, count 0 2006.257.13:32:39.83#ibcon#enter sib2, iclass 34, count 0 2006.257.13:32:39.83#ibcon#flushed, iclass 34, count 0 2006.257.13:32:39.83#ibcon#about to write, iclass 34, count 0 2006.257.13:32:39.83#ibcon#wrote, iclass 34, count 0 2006.257.13:32:39.83#ibcon#about to read 3, iclass 34, count 0 2006.257.13:32:39.85#ibcon#read 3, iclass 34, count 0 2006.257.13:32:39.85#ibcon#about to read 4, iclass 34, count 0 2006.257.13:32:39.85#ibcon#read 4, iclass 34, count 0 2006.257.13:32:39.85#ibcon#about to read 5, iclass 34, count 0 2006.257.13:32:39.85#ibcon#read 5, iclass 34, count 0 2006.257.13:32:39.85#ibcon#about to read 6, iclass 34, count 0 2006.257.13:32:39.85#ibcon#read 6, iclass 34, count 0 2006.257.13:32:39.85#ibcon#end of sib2, iclass 34, count 0 2006.257.13:32:39.85#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:32:39.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:32:39.85#ibcon#[25=USB\r\n] 2006.257.13:32:39.85#ibcon#*before write, iclass 34, count 0 2006.257.13:32:39.85#ibcon#enter sib2, iclass 34, count 0 2006.257.13:32:39.85#ibcon#flushed, iclass 34, count 0 2006.257.13:32:39.85#ibcon#about to write, iclass 34, count 0 2006.257.13:32:39.85#ibcon#wrote, iclass 34, count 0 2006.257.13:32:39.85#ibcon#about to read 3, iclass 34, count 0 2006.257.13:32:39.88#ibcon#read 3, iclass 34, count 0 2006.257.13:32:39.88#ibcon#about to read 4, iclass 34, count 0 2006.257.13:32:39.88#ibcon#read 4, iclass 34, count 0 2006.257.13:32:39.88#ibcon#about to read 5, iclass 34, count 0 2006.257.13:32:39.88#ibcon#read 5, iclass 34, count 0 2006.257.13:32:39.88#ibcon#about to read 6, iclass 34, count 0 2006.257.13:32:39.88#ibcon#read 6, iclass 34, count 0 2006.257.13:32:39.88#ibcon#end of sib2, iclass 34, count 0 2006.257.13:32:39.88#ibcon#*after write, iclass 34, count 0 2006.257.13:32:39.88#ibcon#*before return 0, iclass 34, count 0 2006.257.13:32:39.88#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:32:39.88#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:32:39.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:32:39.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:32:39.88$vck44/vblo=1,629.99 2006.257.13:32:39.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.13:32:39.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.13:32:39.88#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:39.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:32:39.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:32:39.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:32:39.88#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:32:39.88#ibcon#first serial, iclass 36, count 0 2006.257.13:32:39.88#ibcon#enter sib2, iclass 36, count 0 2006.257.13:32:39.88#ibcon#flushed, iclass 36, count 0 2006.257.13:32:39.88#ibcon#about to write, iclass 36, count 0 2006.257.13:32:39.88#ibcon#wrote, iclass 36, count 0 2006.257.13:32:39.88#ibcon#about to read 3, iclass 36, count 0 2006.257.13:32:39.90#ibcon#read 3, iclass 36, count 0 2006.257.13:32:39.90#ibcon#about to read 4, iclass 36, count 0 2006.257.13:32:39.90#ibcon#read 4, iclass 36, count 0 2006.257.13:32:39.90#ibcon#about to read 5, iclass 36, count 0 2006.257.13:32:39.90#ibcon#read 5, iclass 36, count 0 2006.257.13:32:39.90#ibcon#about to read 6, iclass 36, count 0 2006.257.13:32:39.90#ibcon#read 6, iclass 36, count 0 2006.257.13:32:39.90#ibcon#end of sib2, iclass 36, count 0 2006.257.13:32:39.90#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:32:39.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:32:39.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:32:39.90#ibcon#*before write, iclass 36, count 0 2006.257.13:32:39.90#ibcon#enter sib2, iclass 36, count 0 2006.257.13:32:39.90#ibcon#flushed, iclass 36, count 0 2006.257.13:32:39.90#ibcon#about to write, iclass 36, count 0 2006.257.13:32:39.90#ibcon#wrote, iclass 36, count 0 2006.257.13:32:39.90#ibcon#about to read 3, iclass 36, count 0 2006.257.13:32:39.94#ibcon#read 3, iclass 36, count 0 2006.257.13:32:39.94#ibcon#about to read 4, iclass 36, count 0 2006.257.13:32:39.94#ibcon#read 4, iclass 36, count 0 2006.257.13:32:39.94#ibcon#about to read 5, iclass 36, count 0 2006.257.13:32:39.94#ibcon#read 5, iclass 36, count 0 2006.257.13:32:39.94#ibcon#about to read 6, iclass 36, count 0 2006.257.13:32:39.94#ibcon#read 6, iclass 36, count 0 2006.257.13:32:39.94#ibcon#end of sib2, iclass 36, count 0 2006.257.13:32:39.94#ibcon#*after write, iclass 36, count 0 2006.257.13:32:39.94#ibcon#*before return 0, iclass 36, count 0 2006.257.13:32:39.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:32:39.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:32:39.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:32:39.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:32:39.94$vck44/vb=1,4 2006.257.13:32:39.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.13:32:39.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.13:32:39.94#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:39.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:32:39.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:32:39.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:32:39.94#ibcon#enter wrdev, iclass 38, count 2 2006.257.13:32:39.94#ibcon#first serial, iclass 38, count 2 2006.257.13:32:39.94#ibcon#enter sib2, iclass 38, count 2 2006.257.13:32:39.94#ibcon#flushed, iclass 38, count 2 2006.257.13:32:39.94#ibcon#about to write, iclass 38, count 2 2006.257.13:32:39.94#ibcon#wrote, iclass 38, count 2 2006.257.13:32:39.94#ibcon#about to read 3, iclass 38, count 2 2006.257.13:32:39.96#ibcon#read 3, iclass 38, count 2 2006.257.13:32:39.96#ibcon#about to read 4, iclass 38, count 2 2006.257.13:32:39.96#ibcon#read 4, iclass 38, count 2 2006.257.13:32:39.96#ibcon#about to read 5, iclass 38, count 2 2006.257.13:32:39.96#ibcon#read 5, iclass 38, count 2 2006.257.13:32:39.96#ibcon#about to read 6, iclass 38, count 2 2006.257.13:32:39.96#ibcon#read 6, iclass 38, count 2 2006.257.13:32:39.96#ibcon#end of sib2, iclass 38, count 2 2006.257.13:32:39.96#ibcon#*mode == 0, iclass 38, count 2 2006.257.13:32:39.96#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.13:32:39.96#ibcon#[27=AT01-04\r\n] 2006.257.13:32:39.96#ibcon#*before write, iclass 38, count 2 2006.257.13:32:39.96#ibcon#enter sib2, iclass 38, count 2 2006.257.13:32:39.96#ibcon#flushed, iclass 38, count 2 2006.257.13:32:39.96#ibcon#about to write, iclass 38, count 2 2006.257.13:32:39.96#ibcon#wrote, iclass 38, count 2 2006.257.13:32:39.96#ibcon#about to read 3, iclass 38, count 2 2006.257.13:32:39.99#ibcon#read 3, iclass 38, count 2 2006.257.13:32:39.99#ibcon#about to read 4, iclass 38, count 2 2006.257.13:32:39.99#ibcon#read 4, iclass 38, count 2 2006.257.13:32:39.99#ibcon#about to read 5, iclass 38, count 2 2006.257.13:32:39.99#ibcon#read 5, iclass 38, count 2 2006.257.13:32:39.99#ibcon#about to read 6, iclass 38, count 2 2006.257.13:32:39.99#ibcon#read 6, iclass 38, count 2 2006.257.13:32:39.99#ibcon#end of sib2, iclass 38, count 2 2006.257.13:32:39.99#ibcon#*after write, iclass 38, count 2 2006.257.13:32:39.99#ibcon#*before return 0, iclass 38, count 2 2006.257.13:32:39.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:32:39.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:32:39.99#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.13:32:39.99#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:39.99#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:32:40.11#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:32:40.11#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:32:40.11#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:32:40.11#ibcon#first serial, iclass 38, count 0 2006.257.13:32:40.11#ibcon#enter sib2, iclass 38, count 0 2006.257.13:32:40.11#ibcon#flushed, iclass 38, count 0 2006.257.13:32:40.11#ibcon#about to write, iclass 38, count 0 2006.257.13:32:40.11#ibcon#wrote, iclass 38, count 0 2006.257.13:32:40.11#ibcon#about to read 3, iclass 38, count 0 2006.257.13:32:40.13#ibcon#read 3, iclass 38, count 0 2006.257.13:32:40.13#ibcon#about to read 4, iclass 38, count 0 2006.257.13:32:40.13#ibcon#read 4, iclass 38, count 0 2006.257.13:32:40.13#ibcon#about to read 5, iclass 38, count 0 2006.257.13:32:40.13#ibcon#read 5, iclass 38, count 0 2006.257.13:32:40.13#ibcon#about to read 6, iclass 38, count 0 2006.257.13:32:40.13#ibcon#read 6, iclass 38, count 0 2006.257.13:32:40.13#ibcon#end of sib2, iclass 38, count 0 2006.257.13:32:40.13#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:32:40.13#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:32:40.13#ibcon#[27=USB\r\n] 2006.257.13:32:40.13#ibcon#*before write, iclass 38, count 0 2006.257.13:32:40.13#ibcon#enter sib2, iclass 38, count 0 2006.257.13:32:40.13#ibcon#flushed, iclass 38, count 0 2006.257.13:32:40.13#ibcon#about to write, iclass 38, count 0 2006.257.13:32:40.13#ibcon#wrote, iclass 38, count 0 2006.257.13:32:40.13#ibcon#about to read 3, iclass 38, count 0 2006.257.13:32:40.16#ibcon#read 3, iclass 38, count 0 2006.257.13:32:40.16#ibcon#about to read 4, iclass 38, count 0 2006.257.13:32:40.16#ibcon#read 4, iclass 38, count 0 2006.257.13:32:40.16#ibcon#about to read 5, iclass 38, count 0 2006.257.13:32:40.16#ibcon#read 5, iclass 38, count 0 2006.257.13:32:40.16#ibcon#about to read 6, iclass 38, count 0 2006.257.13:32:40.16#ibcon#read 6, iclass 38, count 0 2006.257.13:32:40.16#ibcon#end of sib2, iclass 38, count 0 2006.257.13:32:40.16#ibcon#*after write, iclass 38, count 0 2006.257.13:32:40.16#ibcon#*before return 0, iclass 38, count 0 2006.257.13:32:40.16#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:32:40.16#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:32:40.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:32:40.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:32:40.16$vck44/vblo=2,634.99 2006.257.13:32:40.16#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.13:32:40.16#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.13:32:40.16#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:40.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:40.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:40.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:40.16#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:32:40.16#ibcon#first serial, iclass 40, count 0 2006.257.13:32:40.16#ibcon#enter sib2, iclass 40, count 0 2006.257.13:32:40.16#ibcon#flushed, iclass 40, count 0 2006.257.13:32:40.16#ibcon#about to write, iclass 40, count 0 2006.257.13:32:40.16#ibcon#wrote, iclass 40, count 0 2006.257.13:32:40.16#ibcon#about to read 3, iclass 40, count 0 2006.257.13:32:40.18#ibcon#read 3, iclass 40, count 0 2006.257.13:32:40.18#ibcon#about to read 4, iclass 40, count 0 2006.257.13:32:40.18#ibcon#read 4, iclass 40, count 0 2006.257.13:32:40.18#ibcon#about to read 5, iclass 40, count 0 2006.257.13:32:40.18#ibcon#read 5, iclass 40, count 0 2006.257.13:32:40.18#ibcon#about to read 6, iclass 40, count 0 2006.257.13:32:40.18#ibcon#read 6, iclass 40, count 0 2006.257.13:32:40.18#ibcon#end of sib2, iclass 40, count 0 2006.257.13:32:40.18#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:32:40.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:32:40.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:32:40.18#ibcon#*before write, iclass 40, count 0 2006.257.13:32:40.18#ibcon#enter sib2, iclass 40, count 0 2006.257.13:32:40.18#ibcon#flushed, iclass 40, count 0 2006.257.13:32:40.18#ibcon#about to write, iclass 40, count 0 2006.257.13:32:40.18#ibcon#wrote, iclass 40, count 0 2006.257.13:32:40.18#ibcon#about to read 3, iclass 40, count 0 2006.257.13:32:40.22#ibcon#read 3, iclass 40, count 0 2006.257.13:32:40.22#ibcon#about to read 4, iclass 40, count 0 2006.257.13:32:40.22#ibcon#read 4, iclass 40, count 0 2006.257.13:32:40.22#ibcon#about to read 5, iclass 40, count 0 2006.257.13:32:40.22#ibcon#read 5, iclass 40, count 0 2006.257.13:32:40.22#ibcon#about to read 6, iclass 40, count 0 2006.257.13:32:40.22#ibcon#read 6, iclass 40, count 0 2006.257.13:32:40.22#ibcon#end of sib2, iclass 40, count 0 2006.257.13:32:40.22#ibcon#*after write, iclass 40, count 0 2006.257.13:32:40.22#ibcon#*before return 0, iclass 40, count 0 2006.257.13:32:40.22#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:40.22#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:32:40.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:32:40.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:32:40.22$vck44/vb=2,5 2006.257.13:32:40.22#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.13:32:40.22#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.13:32:40.22#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:40.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:40.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:40.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:40.28#ibcon#enter wrdev, iclass 4, count 2 2006.257.13:32:40.28#ibcon#first serial, iclass 4, count 2 2006.257.13:32:40.28#ibcon#enter sib2, iclass 4, count 2 2006.257.13:32:40.28#ibcon#flushed, iclass 4, count 2 2006.257.13:32:40.28#ibcon#about to write, iclass 4, count 2 2006.257.13:32:40.28#ibcon#wrote, iclass 4, count 2 2006.257.13:32:40.28#ibcon#about to read 3, iclass 4, count 2 2006.257.13:32:40.30#ibcon#read 3, iclass 4, count 2 2006.257.13:32:40.30#ibcon#about to read 4, iclass 4, count 2 2006.257.13:32:40.30#ibcon#read 4, iclass 4, count 2 2006.257.13:32:40.30#ibcon#about to read 5, iclass 4, count 2 2006.257.13:32:40.30#ibcon#read 5, iclass 4, count 2 2006.257.13:32:40.30#ibcon#about to read 6, iclass 4, count 2 2006.257.13:32:40.30#ibcon#read 6, iclass 4, count 2 2006.257.13:32:40.30#ibcon#end of sib2, iclass 4, count 2 2006.257.13:32:40.30#ibcon#*mode == 0, iclass 4, count 2 2006.257.13:32:40.30#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.13:32:40.30#ibcon#[27=AT02-05\r\n] 2006.257.13:32:40.30#ibcon#*before write, iclass 4, count 2 2006.257.13:32:40.30#ibcon#enter sib2, iclass 4, count 2 2006.257.13:32:40.30#ibcon#flushed, iclass 4, count 2 2006.257.13:32:40.30#ibcon#about to write, iclass 4, count 2 2006.257.13:32:40.30#ibcon#wrote, iclass 4, count 2 2006.257.13:32:40.30#ibcon#about to read 3, iclass 4, count 2 2006.257.13:32:40.33#ibcon#read 3, iclass 4, count 2 2006.257.13:32:40.33#ibcon#about to read 4, iclass 4, count 2 2006.257.13:32:40.33#ibcon#read 4, iclass 4, count 2 2006.257.13:32:40.33#ibcon#about to read 5, iclass 4, count 2 2006.257.13:32:40.33#ibcon#read 5, iclass 4, count 2 2006.257.13:32:40.33#ibcon#about to read 6, iclass 4, count 2 2006.257.13:32:40.33#ibcon#read 6, iclass 4, count 2 2006.257.13:32:40.33#ibcon#end of sib2, iclass 4, count 2 2006.257.13:32:40.33#ibcon#*after write, iclass 4, count 2 2006.257.13:32:40.33#ibcon#*before return 0, iclass 4, count 2 2006.257.13:32:40.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:40.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:32:40.33#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.13:32:40.33#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:40.33#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:40.45#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:40.45#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:40.45#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:32:40.45#ibcon#first serial, iclass 4, count 0 2006.257.13:32:40.45#ibcon#enter sib2, iclass 4, count 0 2006.257.13:32:40.45#ibcon#flushed, iclass 4, count 0 2006.257.13:32:40.45#ibcon#about to write, iclass 4, count 0 2006.257.13:32:40.45#ibcon#wrote, iclass 4, count 0 2006.257.13:32:40.45#ibcon#about to read 3, iclass 4, count 0 2006.257.13:32:40.47#ibcon#read 3, iclass 4, count 0 2006.257.13:32:40.47#ibcon#about to read 4, iclass 4, count 0 2006.257.13:32:40.47#ibcon#read 4, iclass 4, count 0 2006.257.13:32:40.47#ibcon#about to read 5, iclass 4, count 0 2006.257.13:32:40.47#ibcon#read 5, iclass 4, count 0 2006.257.13:32:40.47#ibcon#about to read 6, iclass 4, count 0 2006.257.13:32:40.47#ibcon#read 6, iclass 4, count 0 2006.257.13:32:40.47#ibcon#end of sib2, iclass 4, count 0 2006.257.13:32:40.47#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:32:40.47#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:32:40.47#ibcon#[27=USB\r\n] 2006.257.13:32:40.47#ibcon#*before write, iclass 4, count 0 2006.257.13:32:40.47#ibcon#enter sib2, iclass 4, count 0 2006.257.13:32:40.47#ibcon#flushed, iclass 4, count 0 2006.257.13:32:40.47#ibcon#about to write, iclass 4, count 0 2006.257.13:32:40.47#ibcon#wrote, iclass 4, count 0 2006.257.13:32:40.47#ibcon#about to read 3, iclass 4, count 0 2006.257.13:32:40.50#ibcon#read 3, iclass 4, count 0 2006.257.13:32:40.50#ibcon#about to read 4, iclass 4, count 0 2006.257.13:32:40.50#ibcon#read 4, iclass 4, count 0 2006.257.13:32:40.50#ibcon#about to read 5, iclass 4, count 0 2006.257.13:32:40.50#ibcon#read 5, iclass 4, count 0 2006.257.13:32:40.50#ibcon#about to read 6, iclass 4, count 0 2006.257.13:32:40.50#ibcon#read 6, iclass 4, count 0 2006.257.13:32:40.50#ibcon#end of sib2, iclass 4, count 0 2006.257.13:32:40.50#ibcon#*after write, iclass 4, count 0 2006.257.13:32:40.50#ibcon#*before return 0, iclass 4, count 0 2006.257.13:32:40.50#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:40.50#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:32:40.50#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:32:40.50#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:32:40.50$vck44/vblo=3,649.99 2006.257.13:32:40.50#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.13:32:40.50#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.13:32:40.50#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:40.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:40.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:40.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:40.50#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:32:40.50#ibcon#first serial, iclass 6, count 0 2006.257.13:32:40.50#ibcon#enter sib2, iclass 6, count 0 2006.257.13:32:40.50#ibcon#flushed, iclass 6, count 0 2006.257.13:32:40.50#ibcon#about to write, iclass 6, count 0 2006.257.13:32:40.50#ibcon#wrote, iclass 6, count 0 2006.257.13:32:40.50#ibcon#about to read 3, iclass 6, count 0 2006.257.13:32:40.52#ibcon#read 3, iclass 6, count 0 2006.257.13:32:40.52#ibcon#about to read 4, iclass 6, count 0 2006.257.13:32:40.52#ibcon#read 4, iclass 6, count 0 2006.257.13:32:40.52#ibcon#about to read 5, iclass 6, count 0 2006.257.13:32:40.52#ibcon#read 5, iclass 6, count 0 2006.257.13:32:40.52#ibcon#about to read 6, iclass 6, count 0 2006.257.13:32:40.52#ibcon#read 6, iclass 6, count 0 2006.257.13:32:40.52#ibcon#end of sib2, iclass 6, count 0 2006.257.13:32:40.52#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:32:40.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:32:40.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:32:40.52#ibcon#*before write, iclass 6, count 0 2006.257.13:32:40.52#ibcon#enter sib2, iclass 6, count 0 2006.257.13:32:40.52#ibcon#flushed, iclass 6, count 0 2006.257.13:32:40.52#ibcon#about to write, iclass 6, count 0 2006.257.13:32:40.52#ibcon#wrote, iclass 6, count 0 2006.257.13:32:40.52#ibcon#about to read 3, iclass 6, count 0 2006.257.13:32:40.56#ibcon#read 3, iclass 6, count 0 2006.257.13:32:40.56#ibcon#about to read 4, iclass 6, count 0 2006.257.13:32:40.56#ibcon#read 4, iclass 6, count 0 2006.257.13:32:40.56#ibcon#about to read 5, iclass 6, count 0 2006.257.13:32:40.56#ibcon#read 5, iclass 6, count 0 2006.257.13:32:40.56#ibcon#about to read 6, iclass 6, count 0 2006.257.13:32:40.56#ibcon#read 6, iclass 6, count 0 2006.257.13:32:40.56#ibcon#end of sib2, iclass 6, count 0 2006.257.13:32:40.56#ibcon#*after write, iclass 6, count 0 2006.257.13:32:40.56#ibcon#*before return 0, iclass 6, count 0 2006.257.13:32:40.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:40.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:32:40.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:32:40.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:32:40.56$vck44/vb=3,4 2006.257.13:32:40.56#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.13:32:40.56#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.13:32:40.56#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:40.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:40.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:40.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:40.62#ibcon#enter wrdev, iclass 10, count 2 2006.257.13:32:40.62#ibcon#first serial, iclass 10, count 2 2006.257.13:32:40.62#ibcon#enter sib2, iclass 10, count 2 2006.257.13:32:40.62#ibcon#flushed, iclass 10, count 2 2006.257.13:32:40.62#ibcon#about to write, iclass 10, count 2 2006.257.13:32:40.62#ibcon#wrote, iclass 10, count 2 2006.257.13:32:40.62#ibcon#about to read 3, iclass 10, count 2 2006.257.13:32:40.64#ibcon#read 3, iclass 10, count 2 2006.257.13:32:40.64#ibcon#about to read 4, iclass 10, count 2 2006.257.13:32:40.64#ibcon#read 4, iclass 10, count 2 2006.257.13:32:40.64#ibcon#about to read 5, iclass 10, count 2 2006.257.13:32:40.64#ibcon#read 5, iclass 10, count 2 2006.257.13:32:40.64#ibcon#about to read 6, iclass 10, count 2 2006.257.13:32:40.64#ibcon#read 6, iclass 10, count 2 2006.257.13:32:40.64#ibcon#end of sib2, iclass 10, count 2 2006.257.13:32:40.64#ibcon#*mode == 0, iclass 10, count 2 2006.257.13:32:40.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.13:32:40.64#ibcon#[27=AT03-04\r\n] 2006.257.13:32:40.64#ibcon#*before write, iclass 10, count 2 2006.257.13:32:40.64#ibcon#enter sib2, iclass 10, count 2 2006.257.13:32:40.64#ibcon#flushed, iclass 10, count 2 2006.257.13:32:40.64#ibcon#about to write, iclass 10, count 2 2006.257.13:32:40.64#ibcon#wrote, iclass 10, count 2 2006.257.13:32:40.64#ibcon#about to read 3, iclass 10, count 2 2006.257.13:32:40.67#ibcon#read 3, iclass 10, count 2 2006.257.13:32:40.67#ibcon#about to read 4, iclass 10, count 2 2006.257.13:32:40.67#ibcon#read 4, iclass 10, count 2 2006.257.13:32:40.67#ibcon#about to read 5, iclass 10, count 2 2006.257.13:32:40.67#ibcon#read 5, iclass 10, count 2 2006.257.13:32:40.67#ibcon#about to read 6, iclass 10, count 2 2006.257.13:32:40.67#ibcon#read 6, iclass 10, count 2 2006.257.13:32:40.67#ibcon#end of sib2, iclass 10, count 2 2006.257.13:32:40.67#ibcon#*after write, iclass 10, count 2 2006.257.13:32:40.67#ibcon#*before return 0, iclass 10, count 2 2006.257.13:32:40.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:40.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:32:40.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.13:32:40.67#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:40.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:40.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:40.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:40.79#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:32:40.79#ibcon#first serial, iclass 10, count 0 2006.257.13:32:40.79#ibcon#enter sib2, iclass 10, count 0 2006.257.13:32:40.79#ibcon#flushed, iclass 10, count 0 2006.257.13:32:40.79#ibcon#about to write, iclass 10, count 0 2006.257.13:32:40.79#ibcon#wrote, iclass 10, count 0 2006.257.13:32:40.79#ibcon#about to read 3, iclass 10, count 0 2006.257.13:32:40.81#ibcon#read 3, iclass 10, count 0 2006.257.13:32:40.81#ibcon#about to read 4, iclass 10, count 0 2006.257.13:32:40.81#ibcon#read 4, iclass 10, count 0 2006.257.13:32:40.81#ibcon#about to read 5, iclass 10, count 0 2006.257.13:32:40.81#ibcon#read 5, iclass 10, count 0 2006.257.13:32:40.81#ibcon#about to read 6, iclass 10, count 0 2006.257.13:32:40.81#ibcon#read 6, iclass 10, count 0 2006.257.13:32:40.81#ibcon#end of sib2, iclass 10, count 0 2006.257.13:32:40.81#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:32:40.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:32:40.81#ibcon#[27=USB\r\n] 2006.257.13:32:40.81#ibcon#*before write, iclass 10, count 0 2006.257.13:32:40.81#ibcon#enter sib2, iclass 10, count 0 2006.257.13:32:40.81#ibcon#flushed, iclass 10, count 0 2006.257.13:32:40.81#ibcon#about to write, iclass 10, count 0 2006.257.13:32:40.81#ibcon#wrote, iclass 10, count 0 2006.257.13:32:40.81#ibcon#about to read 3, iclass 10, count 0 2006.257.13:32:40.84#ibcon#read 3, iclass 10, count 0 2006.257.13:32:40.84#ibcon#about to read 4, iclass 10, count 0 2006.257.13:32:40.84#ibcon#read 4, iclass 10, count 0 2006.257.13:32:40.84#ibcon#about to read 5, iclass 10, count 0 2006.257.13:32:40.84#ibcon#read 5, iclass 10, count 0 2006.257.13:32:40.84#ibcon#about to read 6, iclass 10, count 0 2006.257.13:32:40.84#ibcon#read 6, iclass 10, count 0 2006.257.13:32:40.84#ibcon#end of sib2, iclass 10, count 0 2006.257.13:32:40.84#ibcon#*after write, iclass 10, count 0 2006.257.13:32:40.84#ibcon#*before return 0, iclass 10, count 0 2006.257.13:32:40.84#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:40.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:32:40.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:32:40.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:32:40.84$vck44/vblo=4,679.99 2006.257.13:32:40.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.13:32:40.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.13:32:40.84#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:40.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:40.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:40.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:40.84#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:32:40.84#ibcon#first serial, iclass 12, count 0 2006.257.13:32:40.84#ibcon#enter sib2, iclass 12, count 0 2006.257.13:32:40.84#ibcon#flushed, iclass 12, count 0 2006.257.13:32:40.84#ibcon#about to write, iclass 12, count 0 2006.257.13:32:40.84#ibcon#wrote, iclass 12, count 0 2006.257.13:32:40.84#ibcon#about to read 3, iclass 12, count 0 2006.257.13:32:40.86#ibcon#read 3, iclass 12, count 0 2006.257.13:32:40.86#ibcon#about to read 4, iclass 12, count 0 2006.257.13:32:40.86#ibcon#read 4, iclass 12, count 0 2006.257.13:32:40.86#ibcon#about to read 5, iclass 12, count 0 2006.257.13:32:40.86#ibcon#read 5, iclass 12, count 0 2006.257.13:32:40.86#ibcon#about to read 6, iclass 12, count 0 2006.257.13:32:40.86#ibcon#read 6, iclass 12, count 0 2006.257.13:32:40.86#ibcon#end of sib2, iclass 12, count 0 2006.257.13:32:40.86#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:32:40.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:32:40.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:32:40.86#ibcon#*before write, iclass 12, count 0 2006.257.13:32:40.86#ibcon#enter sib2, iclass 12, count 0 2006.257.13:32:40.86#ibcon#flushed, iclass 12, count 0 2006.257.13:32:40.86#ibcon#about to write, iclass 12, count 0 2006.257.13:32:40.86#ibcon#wrote, iclass 12, count 0 2006.257.13:32:40.86#ibcon#about to read 3, iclass 12, count 0 2006.257.13:32:40.90#ibcon#read 3, iclass 12, count 0 2006.257.13:32:40.90#ibcon#about to read 4, iclass 12, count 0 2006.257.13:32:40.90#ibcon#read 4, iclass 12, count 0 2006.257.13:32:40.90#ibcon#about to read 5, iclass 12, count 0 2006.257.13:32:40.90#ibcon#read 5, iclass 12, count 0 2006.257.13:32:40.90#ibcon#about to read 6, iclass 12, count 0 2006.257.13:32:40.90#ibcon#read 6, iclass 12, count 0 2006.257.13:32:40.90#ibcon#end of sib2, iclass 12, count 0 2006.257.13:32:40.90#ibcon#*after write, iclass 12, count 0 2006.257.13:32:40.90#ibcon#*before return 0, iclass 12, count 0 2006.257.13:32:40.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:40.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:32:40.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:32:40.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:32:40.90$vck44/vb=4,5 2006.257.13:32:40.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.13:32:40.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.13:32:40.90#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:40.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:40.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:40.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:40.96#ibcon#enter wrdev, iclass 14, count 2 2006.257.13:32:40.96#ibcon#first serial, iclass 14, count 2 2006.257.13:32:40.96#ibcon#enter sib2, iclass 14, count 2 2006.257.13:32:40.96#ibcon#flushed, iclass 14, count 2 2006.257.13:32:40.96#ibcon#about to write, iclass 14, count 2 2006.257.13:32:40.96#ibcon#wrote, iclass 14, count 2 2006.257.13:32:40.96#ibcon#about to read 3, iclass 14, count 2 2006.257.13:32:40.98#ibcon#read 3, iclass 14, count 2 2006.257.13:32:40.98#ibcon#about to read 4, iclass 14, count 2 2006.257.13:32:40.98#ibcon#read 4, iclass 14, count 2 2006.257.13:32:40.98#ibcon#about to read 5, iclass 14, count 2 2006.257.13:32:40.98#ibcon#read 5, iclass 14, count 2 2006.257.13:32:40.98#ibcon#about to read 6, iclass 14, count 2 2006.257.13:32:40.98#ibcon#read 6, iclass 14, count 2 2006.257.13:32:40.98#ibcon#end of sib2, iclass 14, count 2 2006.257.13:32:40.98#ibcon#*mode == 0, iclass 14, count 2 2006.257.13:32:40.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.13:32:40.98#ibcon#[27=AT04-05\r\n] 2006.257.13:32:40.98#ibcon#*before write, iclass 14, count 2 2006.257.13:32:40.98#ibcon#enter sib2, iclass 14, count 2 2006.257.13:32:40.98#ibcon#flushed, iclass 14, count 2 2006.257.13:32:40.98#ibcon#about to write, iclass 14, count 2 2006.257.13:32:40.98#ibcon#wrote, iclass 14, count 2 2006.257.13:32:40.98#ibcon#about to read 3, iclass 14, count 2 2006.257.13:32:41.01#ibcon#read 3, iclass 14, count 2 2006.257.13:32:41.01#ibcon#about to read 4, iclass 14, count 2 2006.257.13:32:41.01#ibcon#read 4, iclass 14, count 2 2006.257.13:32:41.01#ibcon#about to read 5, iclass 14, count 2 2006.257.13:32:41.01#ibcon#read 5, iclass 14, count 2 2006.257.13:32:41.01#ibcon#about to read 6, iclass 14, count 2 2006.257.13:32:41.01#ibcon#read 6, iclass 14, count 2 2006.257.13:32:41.01#ibcon#end of sib2, iclass 14, count 2 2006.257.13:32:41.01#ibcon#*after write, iclass 14, count 2 2006.257.13:32:41.01#ibcon#*before return 0, iclass 14, count 2 2006.257.13:32:41.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:41.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:32:41.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.13:32:41.01#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:41.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:41.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:41.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:41.13#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:32:41.13#ibcon#first serial, iclass 14, count 0 2006.257.13:32:41.13#ibcon#enter sib2, iclass 14, count 0 2006.257.13:32:41.13#ibcon#flushed, iclass 14, count 0 2006.257.13:32:41.13#ibcon#about to write, iclass 14, count 0 2006.257.13:32:41.13#ibcon#wrote, iclass 14, count 0 2006.257.13:32:41.13#ibcon#about to read 3, iclass 14, count 0 2006.257.13:32:41.15#ibcon#read 3, iclass 14, count 0 2006.257.13:32:41.15#ibcon#about to read 4, iclass 14, count 0 2006.257.13:32:41.15#ibcon#read 4, iclass 14, count 0 2006.257.13:32:41.15#ibcon#about to read 5, iclass 14, count 0 2006.257.13:32:41.15#ibcon#read 5, iclass 14, count 0 2006.257.13:32:41.15#ibcon#about to read 6, iclass 14, count 0 2006.257.13:32:41.15#ibcon#read 6, iclass 14, count 0 2006.257.13:32:41.15#ibcon#end of sib2, iclass 14, count 0 2006.257.13:32:41.15#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:32:41.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:32:41.15#ibcon#[27=USB\r\n] 2006.257.13:32:41.15#ibcon#*before write, iclass 14, count 0 2006.257.13:32:41.15#ibcon#enter sib2, iclass 14, count 0 2006.257.13:32:41.15#ibcon#flushed, iclass 14, count 0 2006.257.13:32:41.15#ibcon#about to write, iclass 14, count 0 2006.257.13:32:41.15#ibcon#wrote, iclass 14, count 0 2006.257.13:32:41.15#ibcon#about to read 3, iclass 14, count 0 2006.257.13:32:41.18#ibcon#read 3, iclass 14, count 0 2006.257.13:32:41.18#ibcon#about to read 4, iclass 14, count 0 2006.257.13:32:41.18#ibcon#read 4, iclass 14, count 0 2006.257.13:32:41.18#ibcon#about to read 5, iclass 14, count 0 2006.257.13:32:41.18#ibcon#read 5, iclass 14, count 0 2006.257.13:32:41.18#ibcon#about to read 6, iclass 14, count 0 2006.257.13:32:41.18#ibcon#read 6, iclass 14, count 0 2006.257.13:32:41.18#ibcon#end of sib2, iclass 14, count 0 2006.257.13:32:41.18#ibcon#*after write, iclass 14, count 0 2006.257.13:32:41.18#ibcon#*before return 0, iclass 14, count 0 2006.257.13:32:41.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:41.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:32:41.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:32:41.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:32:41.18$vck44/vblo=5,709.99 2006.257.13:32:41.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.13:32:41.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.13:32:41.18#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:41.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:41.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:41.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:41.18#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:32:41.18#ibcon#first serial, iclass 16, count 0 2006.257.13:32:41.18#ibcon#enter sib2, iclass 16, count 0 2006.257.13:32:41.18#ibcon#flushed, iclass 16, count 0 2006.257.13:32:41.18#ibcon#about to write, iclass 16, count 0 2006.257.13:32:41.18#ibcon#wrote, iclass 16, count 0 2006.257.13:32:41.18#ibcon#about to read 3, iclass 16, count 0 2006.257.13:32:41.20#ibcon#read 3, iclass 16, count 0 2006.257.13:32:41.20#ibcon#about to read 4, iclass 16, count 0 2006.257.13:32:41.20#ibcon#read 4, iclass 16, count 0 2006.257.13:32:41.20#ibcon#about to read 5, iclass 16, count 0 2006.257.13:32:41.20#ibcon#read 5, iclass 16, count 0 2006.257.13:32:41.20#ibcon#about to read 6, iclass 16, count 0 2006.257.13:32:41.20#ibcon#read 6, iclass 16, count 0 2006.257.13:32:41.20#ibcon#end of sib2, iclass 16, count 0 2006.257.13:32:41.20#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:32:41.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:32:41.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:32:41.20#ibcon#*before write, iclass 16, count 0 2006.257.13:32:41.20#ibcon#enter sib2, iclass 16, count 0 2006.257.13:32:41.20#ibcon#flushed, iclass 16, count 0 2006.257.13:32:41.20#ibcon#about to write, iclass 16, count 0 2006.257.13:32:41.20#ibcon#wrote, iclass 16, count 0 2006.257.13:32:41.20#ibcon#about to read 3, iclass 16, count 0 2006.257.13:32:41.24#ibcon#read 3, iclass 16, count 0 2006.257.13:32:41.24#ibcon#about to read 4, iclass 16, count 0 2006.257.13:32:41.24#ibcon#read 4, iclass 16, count 0 2006.257.13:32:41.24#ibcon#about to read 5, iclass 16, count 0 2006.257.13:32:41.24#ibcon#read 5, iclass 16, count 0 2006.257.13:32:41.24#ibcon#about to read 6, iclass 16, count 0 2006.257.13:32:41.24#ibcon#read 6, iclass 16, count 0 2006.257.13:32:41.24#ibcon#end of sib2, iclass 16, count 0 2006.257.13:32:41.24#ibcon#*after write, iclass 16, count 0 2006.257.13:32:41.24#ibcon#*before return 0, iclass 16, count 0 2006.257.13:32:41.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:41.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:32:41.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:32:41.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:32:41.24$vck44/vb=5,4 2006.257.13:32:41.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.13:32:41.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.13:32:41.24#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:41.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:41.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:41.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:41.30#ibcon#enter wrdev, iclass 18, count 2 2006.257.13:32:41.30#ibcon#first serial, iclass 18, count 2 2006.257.13:32:41.30#ibcon#enter sib2, iclass 18, count 2 2006.257.13:32:41.30#ibcon#flushed, iclass 18, count 2 2006.257.13:32:41.30#ibcon#about to write, iclass 18, count 2 2006.257.13:32:41.30#ibcon#wrote, iclass 18, count 2 2006.257.13:32:41.30#ibcon#about to read 3, iclass 18, count 2 2006.257.13:32:41.32#ibcon#read 3, iclass 18, count 2 2006.257.13:32:41.32#ibcon#about to read 4, iclass 18, count 2 2006.257.13:32:41.32#ibcon#read 4, iclass 18, count 2 2006.257.13:32:41.32#ibcon#about to read 5, iclass 18, count 2 2006.257.13:32:41.32#ibcon#read 5, iclass 18, count 2 2006.257.13:32:41.32#ibcon#about to read 6, iclass 18, count 2 2006.257.13:32:41.32#ibcon#read 6, iclass 18, count 2 2006.257.13:32:41.32#ibcon#end of sib2, iclass 18, count 2 2006.257.13:32:41.32#ibcon#*mode == 0, iclass 18, count 2 2006.257.13:32:41.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.13:32:41.32#ibcon#[27=AT05-04\r\n] 2006.257.13:32:41.32#ibcon#*before write, iclass 18, count 2 2006.257.13:32:41.32#ibcon#enter sib2, iclass 18, count 2 2006.257.13:32:41.32#ibcon#flushed, iclass 18, count 2 2006.257.13:32:41.32#ibcon#about to write, iclass 18, count 2 2006.257.13:32:41.32#ibcon#wrote, iclass 18, count 2 2006.257.13:32:41.32#ibcon#about to read 3, iclass 18, count 2 2006.257.13:32:41.35#ibcon#read 3, iclass 18, count 2 2006.257.13:32:41.35#ibcon#about to read 4, iclass 18, count 2 2006.257.13:32:41.35#ibcon#read 4, iclass 18, count 2 2006.257.13:32:41.35#ibcon#about to read 5, iclass 18, count 2 2006.257.13:32:41.35#ibcon#read 5, iclass 18, count 2 2006.257.13:32:41.35#ibcon#about to read 6, iclass 18, count 2 2006.257.13:32:41.35#ibcon#read 6, iclass 18, count 2 2006.257.13:32:41.35#ibcon#end of sib2, iclass 18, count 2 2006.257.13:32:41.35#ibcon#*after write, iclass 18, count 2 2006.257.13:32:41.35#ibcon#*before return 0, iclass 18, count 2 2006.257.13:32:41.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:41.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:32:41.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.13:32:41.35#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:41.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:41.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:41.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:41.47#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:32:41.47#ibcon#first serial, iclass 18, count 0 2006.257.13:32:41.47#ibcon#enter sib2, iclass 18, count 0 2006.257.13:32:41.47#ibcon#flushed, iclass 18, count 0 2006.257.13:32:41.47#ibcon#about to write, iclass 18, count 0 2006.257.13:32:41.47#ibcon#wrote, iclass 18, count 0 2006.257.13:32:41.47#ibcon#about to read 3, iclass 18, count 0 2006.257.13:32:41.49#ibcon#read 3, iclass 18, count 0 2006.257.13:32:41.49#ibcon#about to read 4, iclass 18, count 0 2006.257.13:32:41.49#ibcon#read 4, iclass 18, count 0 2006.257.13:32:41.49#ibcon#about to read 5, iclass 18, count 0 2006.257.13:32:41.49#ibcon#read 5, iclass 18, count 0 2006.257.13:32:41.49#ibcon#about to read 6, iclass 18, count 0 2006.257.13:32:41.49#ibcon#read 6, iclass 18, count 0 2006.257.13:32:41.49#ibcon#end of sib2, iclass 18, count 0 2006.257.13:32:41.49#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:32:41.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:32:41.49#ibcon#[27=USB\r\n] 2006.257.13:32:41.49#ibcon#*before write, iclass 18, count 0 2006.257.13:32:41.49#ibcon#enter sib2, iclass 18, count 0 2006.257.13:32:41.49#ibcon#flushed, iclass 18, count 0 2006.257.13:32:41.49#ibcon#about to write, iclass 18, count 0 2006.257.13:32:41.49#ibcon#wrote, iclass 18, count 0 2006.257.13:32:41.49#ibcon#about to read 3, iclass 18, count 0 2006.257.13:32:41.52#ibcon#read 3, iclass 18, count 0 2006.257.13:32:41.52#ibcon#about to read 4, iclass 18, count 0 2006.257.13:32:41.52#ibcon#read 4, iclass 18, count 0 2006.257.13:32:41.52#ibcon#about to read 5, iclass 18, count 0 2006.257.13:32:41.52#ibcon#read 5, iclass 18, count 0 2006.257.13:32:41.52#ibcon#about to read 6, iclass 18, count 0 2006.257.13:32:41.52#ibcon#read 6, iclass 18, count 0 2006.257.13:32:41.52#ibcon#end of sib2, iclass 18, count 0 2006.257.13:32:41.52#ibcon#*after write, iclass 18, count 0 2006.257.13:32:41.52#ibcon#*before return 0, iclass 18, count 0 2006.257.13:32:41.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:41.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:32:41.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:32:41.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:32:41.52$vck44/vblo=6,719.99 2006.257.13:32:41.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.13:32:41.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.13:32:41.52#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:41.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:41.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:41.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:41.52#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:32:41.52#ibcon#first serial, iclass 20, count 0 2006.257.13:32:41.52#ibcon#enter sib2, iclass 20, count 0 2006.257.13:32:41.52#ibcon#flushed, iclass 20, count 0 2006.257.13:32:41.52#ibcon#about to write, iclass 20, count 0 2006.257.13:32:41.52#ibcon#wrote, iclass 20, count 0 2006.257.13:32:41.52#ibcon#about to read 3, iclass 20, count 0 2006.257.13:32:41.54#ibcon#read 3, iclass 20, count 0 2006.257.13:32:41.54#ibcon#about to read 4, iclass 20, count 0 2006.257.13:32:41.54#ibcon#read 4, iclass 20, count 0 2006.257.13:32:41.54#ibcon#about to read 5, iclass 20, count 0 2006.257.13:32:41.54#ibcon#read 5, iclass 20, count 0 2006.257.13:32:41.54#ibcon#about to read 6, iclass 20, count 0 2006.257.13:32:41.54#ibcon#read 6, iclass 20, count 0 2006.257.13:32:41.54#ibcon#end of sib2, iclass 20, count 0 2006.257.13:32:41.54#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:32:41.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:32:41.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:32:41.54#ibcon#*before write, iclass 20, count 0 2006.257.13:32:41.54#ibcon#enter sib2, iclass 20, count 0 2006.257.13:32:41.54#ibcon#flushed, iclass 20, count 0 2006.257.13:32:41.54#ibcon#about to write, iclass 20, count 0 2006.257.13:32:41.54#ibcon#wrote, iclass 20, count 0 2006.257.13:32:41.54#ibcon#about to read 3, iclass 20, count 0 2006.257.13:32:41.58#ibcon#read 3, iclass 20, count 0 2006.257.13:32:41.58#ibcon#about to read 4, iclass 20, count 0 2006.257.13:32:41.58#ibcon#read 4, iclass 20, count 0 2006.257.13:32:41.58#ibcon#about to read 5, iclass 20, count 0 2006.257.13:32:41.58#ibcon#read 5, iclass 20, count 0 2006.257.13:32:41.58#ibcon#about to read 6, iclass 20, count 0 2006.257.13:32:41.58#ibcon#read 6, iclass 20, count 0 2006.257.13:32:41.58#ibcon#end of sib2, iclass 20, count 0 2006.257.13:32:41.58#ibcon#*after write, iclass 20, count 0 2006.257.13:32:41.58#ibcon#*before return 0, iclass 20, count 0 2006.257.13:32:41.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:41.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:32:41.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:32:41.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:32:41.58$vck44/vb=6,4 2006.257.13:32:41.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.13:32:41.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.13:32:41.58#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:41.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:41.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:41.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:41.64#ibcon#enter wrdev, iclass 22, count 2 2006.257.13:32:41.64#ibcon#first serial, iclass 22, count 2 2006.257.13:32:41.64#ibcon#enter sib2, iclass 22, count 2 2006.257.13:32:41.64#ibcon#flushed, iclass 22, count 2 2006.257.13:32:41.64#ibcon#about to write, iclass 22, count 2 2006.257.13:32:41.64#ibcon#wrote, iclass 22, count 2 2006.257.13:32:41.64#ibcon#about to read 3, iclass 22, count 2 2006.257.13:32:41.66#ibcon#read 3, iclass 22, count 2 2006.257.13:32:41.66#ibcon#about to read 4, iclass 22, count 2 2006.257.13:32:41.66#ibcon#read 4, iclass 22, count 2 2006.257.13:32:41.66#ibcon#about to read 5, iclass 22, count 2 2006.257.13:32:41.66#ibcon#read 5, iclass 22, count 2 2006.257.13:32:41.66#ibcon#about to read 6, iclass 22, count 2 2006.257.13:32:41.66#ibcon#read 6, iclass 22, count 2 2006.257.13:32:41.66#ibcon#end of sib2, iclass 22, count 2 2006.257.13:32:41.66#ibcon#*mode == 0, iclass 22, count 2 2006.257.13:32:41.66#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.13:32:41.66#ibcon#[27=AT06-04\r\n] 2006.257.13:32:41.66#ibcon#*before write, iclass 22, count 2 2006.257.13:32:41.66#ibcon#enter sib2, iclass 22, count 2 2006.257.13:32:41.66#ibcon#flushed, iclass 22, count 2 2006.257.13:32:41.66#ibcon#about to write, iclass 22, count 2 2006.257.13:32:41.66#ibcon#wrote, iclass 22, count 2 2006.257.13:32:41.66#ibcon#about to read 3, iclass 22, count 2 2006.257.13:32:41.69#ibcon#read 3, iclass 22, count 2 2006.257.13:32:41.69#ibcon#about to read 4, iclass 22, count 2 2006.257.13:32:41.69#ibcon#read 4, iclass 22, count 2 2006.257.13:32:41.69#ibcon#about to read 5, iclass 22, count 2 2006.257.13:32:41.69#ibcon#read 5, iclass 22, count 2 2006.257.13:32:41.69#ibcon#about to read 6, iclass 22, count 2 2006.257.13:32:41.69#ibcon#read 6, iclass 22, count 2 2006.257.13:32:41.69#ibcon#end of sib2, iclass 22, count 2 2006.257.13:32:41.69#ibcon#*after write, iclass 22, count 2 2006.257.13:32:41.69#ibcon#*before return 0, iclass 22, count 2 2006.257.13:32:41.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:41.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:32:41.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.13:32:41.69#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:41.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:41.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:41.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:41.81#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:32:41.81#ibcon#first serial, iclass 22, count 0 2006.257.13:32:41.81#ibcon#enter sib2, iclass 22, count 0 2006.257.13:32:41.81#ibcon#flushed, iclass 22, count 0 2006.257.13:32:41.81#ibcon#about to write, iclass 22, count 0 2006.257.13:32:41.81#ibcon#wrote, iclass 22, count 0 2006.257.13:32:41.81#ibcon#about to read 3, iclass 22, count 0 2006.257.13:32:41.83#ibcon#read 3, iclass 22, count 0 2006.257.13:32:41.83#ibcon#about to read 4, iclass 22, count 0 2006.257.13:32:41.83#ibcon#read 4, iclass 22, count 0 2006.257.13:32:41.83#ibcon#about to read 5, iclass 22, count 0 2006.257.13:32:41.83#ibcon#read 5, iclass 22, count 0 2006.257.13:32:41.83#ibcon#about to read 6, iclass 22, count 0 2006.257.13:32:41.83#ibcon#read 6, iclass 22, count 0 2006.257.13:32:41.83#ibcon#end of sib2, iclass 22, count 0 2006.257.13:32:41.83#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:32:41.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:32:41.83#ibcon#[27=USB\r\n] 2006.257.13:32:41.83#ibcon#*before write, iclass 22, count 0 2006.257.13:32:41.83#ibcon#enter sib2, iclass 22, count 0 2006.257.13:32:41.83#ibcon#flushed, iclass 22, count 0 2006.257.13:32:41.83#ibcon#about to write, iclass 22, count 0 2006.257.13:32:41.83#ibcon#wrote, iclass 22, count 0 2006.257.13:32:41.83#ibcon#about to read 3, iclass 22, count 0 2006.257.13:32:41.86#ibcon#read 3, iclass 22, count 0 2006.257.13:32:41.86#ibcon#about to read 4, iclass 22, count 0 2006.257.13:32:41.86#ibcon#read 4, iclass 22, count 0 2006.257.13:32:41.86#ibcon#about to read 5, iclass 22, count 0 2006.257.13:32:41.86#ibcon#read 5, iclass 22, count 0 2006.257.13:32:41.86#ibcon#about to read 6, iclass 22, count 0 2006.257.13:32:41.86#ibcon#read 6, iclass 22, count 0 2006.257.13:32:41.86#ibcon#end of sib2, iclass 22, count 0 2006.257.13:32:41.86#ibcon#*after write, iclass 22, count 0 2006.257.13:32:41.86#ibcon#*before return 0, iclass 22, count 0 2006.257.13:32:41.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:41.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:32:41.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:32:41.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:32:41.86$vck44/vblo=7,734.99 2006.257.13:32:41.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.13:32:41.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.13:32:41.86#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:41.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:41.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:41.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:41.86#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:32:41.86#ibcon#first serial, iclass 24, count 0 2006.257.13:32:41.86#ibcon#enter sib2, iclass 24, count 0 2006.257.13:32:41.86#ibcon#flushed, iclass 24, count 0 2006.257.13:32:41.86#ibcon#about to write, iclass 24, count 0 2006.257.13:32:41.86#ibcon#wrote, iclass 24, count 0 2006.257.13:32:41.86#ibcon#about to read 3, iclass 24, count 0 2006.257.13:32:41.88#ibcon#read 3, iclass 24, count 0 2006.257.13:32:41.88#ibcon#about to read 4, iclass 24, count 0 2006.257.13:32:41.88#ibcon#read 4, iclass 24, count 0 2006.257.13:32:41.88#ibcon#about to read 5, iclass 24, count 0 2006.257.13:32:41.88#ibcon#read 5, iclass 24, count 0 2006.257.13:32:41.88#ibcon#about to read 6, iclass 24, count 0 2006.257.13:32:41.88#ibcon#read 6, iclass 24, count 0 2006.257.13:32:41.88#ibcon#end of sib2, iclass 24, count 0 2006.257.13:32:41.88#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:32:41.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:32:41.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:32:41.88#ibcon#*before write, iclass 24, count 0 2006.257.13:32:41.88#ibcon#enter sib2, iclass 24, count 0 2006.257.13:32:41.88#ibcon#flushed, iclass 24, count 0 2006.257.13:32:41.88#ibcon#about to write, iclass 24, count 0 2006.257.13:32:41.88#ibcon#wrote, iclass 24, count 0 2006.257.13:32:41.88#ibcon#about to read 3, iclass 24, count 0 2006.257.13:32:41.92#ibcon#read 3, iclass 24, count 0 2006.257.13:32:41.92#ibcon#about to read 4, iclass 24, count 0 2006.257.13:32:41.92#ibcon#read 4, iclass 24, count 0 2006.257.13:32:41.92#ibcon#about to read 5, iclass 24, count 0 2006.257.13:32:41.92#ibcon#read 5, iclass 24, count 0 2006.257.13:32:41.92#ibcon#about to read 6, iclass 24, count 0 2006.257.13:32:41.92#ibcon#read 6, iclass 24, count 0 2006.257.13:32:41.92#ibcon#end of sib2, iclass 24, count 0 2006.257.13:32:41.92#ibcon#*after write, iclass 24, count 0 2006.257.13:32:41.92#ibcon#*before return 0, iclass 24, count 0 2006.257.13:32:41.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:41.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:32:41.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:32:41.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:32:41.92$vck44/vb=7,4 2006.257.13:32:41.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.13:32:41.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.13:32:41.92#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:41.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:41.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:41.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:41.98#ibcon#enter wrdev, iclass 26, count 2 2006.257.13:32:41.98#ibcon#first serial, iclass 26, count 2 2006.257.13:32:41.98#ibcon#enter sib2, iclass 26, count 2 2006.257.13:32:41.98#ibcon#flushed, iclass 26, count 2 2006.257.13:32:41.98#ibcon#about to write, iclass 26, count 2 2006.257.13:32:41.98#ibcon#wrote, iclass 26, count 2 2006.257.13:32:41.98#ibcon#about to read 3, iclass 26, count 2 2006.257.13:32:42.00#ibcon#read 3, iclass 26, count 2 2006.257.13:32:42.00#ibcon#about to read 4, iclass 26, count 2 2006.257.13:32:42.00#ibcon#read 4, iclass 26, count 2 2006.257.13:32:42.00#ibcon#about to read 5, iclass 26, count 2 2006.257.13:32:42.00#ibcon#read 5, iclass 26, count 2 2006.257.13:32:42.00#ibcon#about to read 6, iclass 26, count 2 2006.257.13:32:42.00#ibcon#read 6, iclass 26, count 2 2006.257.13:32:42.00#ibcon#end of sib2, iclass 26, count 2 2006.257.13:32:42.00#ibcon#*mode == 0, iclass 26, count 2 2006.257.13:32:42.00#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.13:32:42.00#ibcon#[27=AT07-04\r\n] 2006.257.13:32:42.00#ibcon#*before write, iclass 26, count 2 2006.257.13:32:42.00#ibcon#enter sib2, iclass 26, count 2 2006.257.13:32:42.00#ibcon#flushed, iclass 26, count 2 2006.257.13:32:42.00#ibcon#about to write, iclass 26, count 2 2006.257.13:32:42.00#ibcon#wrote, iclass 26, count 2 2006.257.13:32:42.00#ibcon#about to read 3, iclass 26, count 2 2006.257.13:32:42.03#ibcon#read 3, iclass 26, count 2 2006.257.13:32:42.03#ibcon#about to read 4, iclass 26, count 2 2006.257.13:32:42.03#ibcon#read 4, iclass 26, count 2 2006.257.13:32:42.03#ibcon#about to read 5, iclass 26, count 2 2006.257.13:32:42.03#ibcon#read 5, iclass 26, count 2 2006.257.13:32:42.03#ibcon#about to read 6, iclass 26, count 2 2006.257.13:32:42.03#ibcon#read 6, iclass 26, count 2 2006.257.13:32:42.03#ibcon#end of sib2, iclass 26, count 2 2006.257.13:32:42.03#ibcon#*after write, iclass 26, count 2 2006.257.13:32:42.03#ibcon#*before return 0, iclass 26, count 2 2006.257.13:32:42.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:42.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:32:42.03#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.13:32:42.03#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:42.03#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:42.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:42.15#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:42.15#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:32:42.15#ibcon#first serial, iclass 26, count 0 2006.257.13:32:42.15#ibcon#enter sib2, iclass 26, count 0 2006.257.13:32:42.15#ibcon#flushed, iclass 26, count 0 2006.257.13:32:42.15#ibcon#about to write, iclass 26, count 0 2006.257.13:32:42.15#ibcon#wrote, iclass 26, count 0 2006.257.13:32:42.15#ibcon#about to read 3, iclass 26, count 0 2006.257.13:32:42.17#ibcon#read 3, iclass 26, count 0 2006.257.13:32:42.17#ibcon#about to read 4, iclass 26, count 0 2006.257.13:32:42.17#ibcon#read 4, iclass 26, count 0 2006.257.13:32:42.17#ibcon#about to read 5, iclass 26, count 0 2006.257.13:32:42.17#ibcon#read 5, iclass 26, count 0 2006.257.13:32:42.17#ibcon#about to read 6, iclass 26, count 0 2006.257.13:32:42.17#ibcon#read 6, iclass 26, count 0 2006.257.13:32:42.17#ibcon#end of sib2, iclass 26, count 0 2006.257.13:32:42.17#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:32:42.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:32:42.17#ibcon#[27=USB\r\n] 2006.257.13:32:42.17#ibcon#*before write, iclass 26, count 0 2006.257.13:32:42.17#ibcon#enter sib2, iclass 26, count 0 2006.257.13:32:42.17#ibcon#flushed, iclass 26, count 0 2006.257.13:32:42.17#ibcon#about to write, iclass 26, count 0 2006.257.13:32:42.17#ibcon#wrote, iclass 26, count 0 2006.257.13:32:42.17#ibcon#about to read 3, iclass 26, count 0 2006.257.13:32:42.20#ibcon#read 3, iclass 26, count 0 2006.257.13:32:42.20#ibcon#about to read 4, iclass 26, count 0 2006.257.13:32:42.20#ibcon#read 4, iclass 26, count 0 2006.257.13:32:42.20#ibcon#about to read 5, iclass 26, count 0 2006.257.13:32:42.20#ibcon#read 5, iclass 26, count 0 2006.257.13:32:42.20#ibcon#about to read 6, iclass 26, count 0 2006.257.13:32:42.20#ibcon#read 6, iclass 26, count 0 2006.257.13:32:42.20#ibcon#end of sib2, iclass 26, count 0 2006.257.13:32:42.20#ibcon#*after write, iclass 26, count 0 2006.257.13:32:42.20#ibcon#*before return 0, iclass 26, count 0 2006.257.13:32:42.20#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:42.20#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:32:42.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:32:42.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:32:42.20$vck44/vblo=8,744.99 2006.257.13:32:42.20#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.13:32:42.20#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.13:32:42.20#ibcon#ireg 17 cls_cnt 0 2006.257.13:32:42.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:42.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:42.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:42.20#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:32:42.20#ibcon#first serial, iclass 28, count 0 2006.257.13:32:42.20#ibcon#enter sib2, iclass 28, count 0 2006.257.13:32:42.20#ibcon#flushed, iclass 28, count 0 2006.257.13:32:42.20#ibcon#about to write, iclass 28, count 0 2006.257.13:32:42.20#ibcon#wrote, iclass 28, count 0 2006.257.13:32:42.20#ibcon#about to read 3, iclass 28, count 0 2006.257.13:32:42.22#ibcon#read 3, iclass 28, count 0 2006.257.13:32:42.22#ibcon#about to read 4, iclass 28, count 0 2006.257.13:32:42.22#ibcon#read 4, iclass 28, count 0 2006.257.13:32:42.22#ibcon#about to read 5, iclass 28, count 0 2006.257.13:32:42.22#ibcon#read 5, iclass 28, count 0 2006.257.13:32:42.22#ibcon#about to read 6, iclass 28, count 0 2006.257.13:32:42.22#ibcon#read 6, iclass 28, count 0 2006.257.13:32:42.22#ibcon#end of sib2, iclass 28, count 0 2006.257.13:32:42.22#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:32:42.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:32:42.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:32:42.22#ibcon#*before write, iclass 28, count 0 2006.257.13:32:42.22#ibcon#enter sib2, iclass 28, count 0 2006.257.13:32:42.22#ibcon#flushed, iclass 28, count 0 2006.257.13:32:42.22#ibcon#about to write, iclass 28, count 0 2006.257.13:32:42.22#ibcon#wrote, iclass 28, count 0 2006.257.13:32:42.22#ibcon#about to read 3, iclass 28, count 0 2006.257.13:32:42.26#ibcon#read 3, iclass 28, count 0 2006.257.13:32:42.26#ibcon#about to read 4, iclass 28, count 0 2006.257.13:32:42.26#ibcon#read 4, iclass 28, count 0 2006.257.13:32:42.26#ibcon#about to read 5, iclass 28, count 0 2006.257.13:32:42.26#ibcon#read 5, iclass 28, count 0 2006.257.13:32:42.26#ibcon#about to read 6, iclass 28, count 0 2006.257.13:32:42.26#ibcon#read 6, iclass 28, count 0 2006.257.13:32:42.26#ibcon#end of sib2, iclass 28, count 0 2006.257.13:32:42.26#ibcon#*after write, iclass 28, count 0 2006.257.13:32:42.26#ibcon#*before return 0, iclass 28, count 0 2006.257.13:32:42.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:42.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:32:42.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:32:42.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:32:42.26$vck44/vb=8,4 2006.257.13:32:42.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.13:32:42.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.13:32:42.26#ibcon#ireg 11 cls_cnt 2 2006.257.13:32:42.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:42.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:42.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:42.32#ibcon#enter wrdev, iclass 30, count 2 2006.257.13:32:42.32#ibcon#first serial, iclass 30, count 2 2006.257.13:32:42.32#ibcon#enter sib2, iclass 30, count 2 2006.257.13:32:42.32#ibcon#flushed, iclass 30, count 2 2006.257.13:32:42.32#ibcon#about to write, iclass 30, count 2 2006.257.13:32:42.32#ibcon#wrote, iclass 30, count 2 2006.257.13:32:42.32#ibcon#about to read 3, iclass 30, count 2 2006.257.13:32:42.34#ibcon#read 3, iclass 30, count 2 2006.257.13:32:42.34#ibcon#about to read 4, iclass 30, count 2 2006.257.13:32:42.34#ibcon#read 4, iclass 30, count 2 2006.257.13:32:42.34#ibcon#about to read 5, iclass 30, count 2 2006.257.13:32:42.34#ibcon#read 5, iclass 30, count 2 2006.257.13:32:42.34#ibcon#about to read 6, iclass 30, count 2 2006.257.13:32:42.34#ibcon#read 6, iclass 30, count 2 2006.257.13:32:42.34#ibcon#end of sib2, iclass 30, count 2 2006.257.13:32:42.34#ibcon#*mode == 0, iclass 30, count 2 2006.257.13:32:42.34#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.13:32:42.34#ibcon#[27=AT08-04\r\n] 2006.257.13:32:42.34#ibcon#*before write, iclass 30, count 2 2006.257.13:32:42.34#ibcon#enter sib2, iclass 30, count 2 2006.257.13:32:42.34#ibcon#flushed, iclass 30, count 2 2006.257.13:32:42.34#ibcon#about to write, iclass 30, count 2 2006.257.13:32:42.34#ibcon#wrote, iclass 30, count 2 2006.257.13:32:42.34#ibcon#about to read 3, iclass 30, count 2 2006.257.13:32:42.37#ibcon#read 3, iclass 30, count 2 2006.257.13:32:42.37#ibcon#about to read 4, iclass 30, count 2 2006.257.13:32:42.37#ibcon#read 4, iclass 30, count 2 2006.257.13:32:42.37#ibcon#about to read 5, iclass 30, count 2 2006.257.13:32:42.37#ibcon#read 5, iclass 30, count 2 2006.257.13:32:42.37#ibcon#about to read 6, iclass 30, count 2 2006.257.13:32:42.37#ibcon#read 6, iclass 30, count 2 2006.257.13:32:42.37#ibcon#end of sib2, iclass 30, count 2 2006.257.13:32:42.37#ibcon#*after write, iclass 30, count 2 2006.257.13:32:42.37#ibcon#*before return 0, iclass 30, count 2 2006.257.13:32:42.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:42.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:32:42.37#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.13:32:42.37#ibcon#ireg 7 cls_cnt 0 2006.257.13:32:42.37#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:42.49#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:42.49#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:42.49#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:32:42.49#ibcon#first serial, iclass 30, count 0 2006.257.13:32:42.49#ibcon#enter sib2, iclass 30, count 0 2006.257.13:32:42.49#ibcon#flushed, iclass 30, count 0 2006.257.13:32:42.49#ibcon#about to write, iclass 30, count 0 2006.257.13:32:42.49#ibcon#wrote, iclass 30, count 0 2006.257.13:32:42.49#ibcon#about to read 3, iclass 30, count 0 2006.257.13:32:42.51#ibcon#read 3, iclass 30, count 0 2006.257.13:32:42.51#ibcon#about to read 4, iclass 30, count 0 2006.257.13:32:42.51#ibcon#read 4, iclass 30, count 0 2006.257.13:32:42.51#ibcon#about to read 5, iclass 30, count 0 2006.257.13:32:42.51#ibcon#read 5, iclass 30, count 0 2006.257.13:32:42.51#ibcon#about to read 6, iclass 30, count 0 2006.257.13:32:42.51#ibcon#read 6, iclass 30, count 0 2006.257.13:32:42.51#ibcon#end of sib2, iclass 30, count 0 2006.257.13:32:42.51#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:32:42.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:32:42.51#ibcon#[27=USB\r\n] 2006.257.13:32:42.51#ibcon#*before write, iclass 30, count 0 2006.257.13:32:42.51#ibcon#enter sib2, iclass 30, count 0 2006.257.13:32:42.51#ibcon#flushed, iclass 30, count 0 2006.257.13:32:42.51#ibcon#about to write, iclass 30, count 0 2006.257.13:32:42.51#ibcon#wrote, iclass 30, count 0 2006.257.13:32:42.51#ibcon#about to read 3, iclass 30, count 0 2006.257.13:32:42.54#ibcon#read 3, iclass 30, count 0 2006.257.13:32:42.54#ibcon#about to read 4, iclass 30, count 0 2006.257.13:32:42.54#ibcon#read 4, iclass 30, count 0 2006.257.13:32:42.54#ibcon#about to read 5, iclass 30, count 0 2006.257.13:32:42.54#ibcon#read 5, iclass 30, count 0 2006.257.13:32:42.54#ibcon#about to read 6, iclass 30, count 0 2006.257.13:32:42.54#ibcon#read 6, iclass 30, count 0 2006.257.13:32:42.54#ibcon#end of sib2, iclass 30, count 0 2006.257.13:32:42.54#ibcon#*after write, iclass 30, count 0 2006.257.13:32:42.54#ibcon#*before return 0, iclass 30, count 0 2006.257.13:32:42.54#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:42.54#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:32:42.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:32:42.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:32:42.54$vck44/vabw=wide 2006.257.13:32:42.54#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.13:32:42.54#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.13:32:42.54#ibcon#ireg 8 cls_cnt 0 2006.257.13:32:42.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:42.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:42.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:42.54#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:32:42.54#ibcon#first serial, iclass 32, count 0 2006.257.13:32:42.54#ibcon#enter sib2, iclass 32, count 0 2006.257.13:32:42.54#ibcon#flushed, iclass 32, count 0 2006.257.13:32:42.54#ibcon#about to write, iclass 32, count 0 2006.257.13:32:42.54#ibcon#wrote, iclass 32, count 0 2006.257.13:32:42.54#ibcon#about to read 3, iclass 32, count 0 2006.257.13:32:42.56#ibcon#read 3, iclass 32, count 0 2006.257.13:32:42.56#ibcon#about to read 4, iclass 32, count 0 2006.257.13:32:42.56#ibcon#read 4, iclass 32, count 0 2006.257.13:32:42.56#ibcon#about to read 5, iclass 32, count 0 2006.257.13:32:42.56#ibcon#read 5, iclass 32, count 0 2006.257.13:32:42.56#ibcon#about to read 6, iclass 32, count 0 2006.257.13:32:42.56#ibcon#read 6, iclass 32, count 0 2006.257.13:32:42.56#ibcon#end of sib2, iclass 32, count 0 2006.257.13:32:42.56#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:32:42.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:32:42.56#ibcon#[25=BW32\r\n] 2006.257.13:32:42.56#ibcon#*before write, iclass 32, count 0 2006.257.13:32:42.56#ibcon#enter sib2, iclass 32, count 0 2006.257.13:32:42.56#ibcon#flushed, iclass 32, count 0 2006.257.13:32:42.56#ibcon#about to write, iclass 32, count 0 2006.257.13:32:42.56#ibcon#wrote, iclass 32, count 0 2006.257.13:32:42.56#ibcon#about to read 3, iclass 32, count 0 2006.257.13:32:42.59#ibcon#read 3, iclass 32, count 0 2006.257.13:32:42.59#ibcon#about to read 4, iclass 32, count 0 2006.257.13:32:42.59#ibcon#read 4, iclass 32, count 0 2006.257.13:32:42.59#ibcon#about to read 5, iclass 32, count 0 2006.257.13:32:42.59#ibcon#read 5, iclass 32, count 0 2006.257.13:32:42.59#ibcon#about to read 6, iclass 32, count 0 2006.257.13:32:42.59#ibcon#read 6, iclass 32, count 0 2006.257.13:32:42.59#ibcon#end of sib2, iclass 32, count 0 2006.257.13:32:42.59#ibcon#*after write, iclass 32, count 0 2006.257.13:32:42.59#ibcon#*before return 0, iclass 32, count 0 2006.257.13:32:42.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:42.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:32:42.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:32:42.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:32:42.59$vck44/vbbw=wide 2006.257.13:32:42.59#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.13:32:42.59#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.13:32:42.59#ibcon#ireg 8 cls_cnt 0 2006.257.13:32:42.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:32:42.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:32:42.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:32:42.66#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:32:42.66#ibcon#first serial, iclass 34, count 0 2006.257.13:32:42.66#ibcon#enter sib2, iclass 34, count 0 2006.257.13:32:42.66#ibcon#flushed, iclass 34, count 0 2006.257.13:32:42.66#ibcon#about to write, iclass 34, count 0 2006.257.13:32:42.66#ibcon#wrote, iclass 34, count 0 2006.257.13:32:42.66#ibcon#about to read 3, iclass 34, count 0 2006.257.13:32:42.68#ibcon#read 3, iclass 34, count 0 2006.257.13:32:42.68#ibcon#about to read 4, iclass 34, count 0 2006.257.13:32:42.68#ibcon#read 4, iclass 34, count 0 2006.257.13:32:42.68#ibcon#about to read 5, iclass 34, count 0 2006.257.13:32:42.68#ibcon#read 5, iclass 34, count 0 2006.257.13:32:42.68#ibcon#about to read 6, iclass 34, count 0 2006.257.13:32:42.68#ibcon#read 6, iclass 34, count 0 2006.257.13:32:42.68#ibcon#end of sib2, iclass 34, count 0 2006.257.13:32:42.68#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:32:42.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:32:42.68#ibcon#[27=BW32\r\n] 2006.257.13:32:42.68#ibcon#*before write, iclass 34, count 0 2006.257.13:32:42.68#ibcon#enter sib2, iclass 34, count 0 2006.257.13:32:42.68#ibcon#flushed, iclass 34, count 0 2006.257.13:32:42.68#ibcon#about to write, iclass 34, count 0 2006.257.13:32:42.68#ibcon#wrote, iclass 34, count 0 2006.257.13:32:42.68#ibcon#about to read 3, iclass 34, count 0 2006.257.13:32:42.71#ibcon#read 3, iclass 34, count 0 2006.257.13:32:42.71#ibcon#about to read 4, iclass 34, count 0 2006.257.13:32:42.71#ibcon#read 4, iclass 34, count 0 2006.257.13:32:42.71#ibcon#about to read 5, iclass 34, count 0 2006.257.13:32:42.71#ibcon#read 5, iclass 34, count 0 2006.257.13:32:42.71#ibcon#about to read 6, iclass 34, count 0 2006.257.13:32:42.71#ibcon#read 6, iclass 34, count 0 2006.257.13:32:42.71#ibcon#end of sib2, iclass 34, count 0 2006.257.13:32:42.71#ibcon#*after write, iclass 34, count 0 2006.257.13:32:42.71#ibcon#*before return 0, iclass 34, count 0 2006.257.13:32:42.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:32:42.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:32:42.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:32:42.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:32:42.71$setupk4/ifdk4 2006.257.13:32:42.71$ifdk4/lo= 2006.257.13:32:42.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:32:42.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:32:42.71$ifdk4/patch= 2006.257.13:32:42.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:32:42.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:32:42.71$setupk4/!*+20s 2006.257.13:32:45.83#abcon#<5=/14 1.1 2.9 17.49 981013.9\r\n> 2006.257.13:32:45.85#abcon#{5=INTERFACE CLEAR} 2006.257.13:32:45.91#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:32:56.00#abcon#<5=/14 1.1 2.9 17.49 981013.9\r\n> 2006.257.13:32:56.02#abcon#{5=INTERFACE CLEAR} 2006.257.13:32:56.08#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:32:56.14#trakl#Source acquired 2006.257.13:32:56.14#flagr#flagr/antenna,acquired 2006.257.13:32:57.17$setupk4/"tpicd 2006.257.13:32:57.17$setupk4/echo=off 2006.257.13:32:57.17$setupk4/xlog=off 2006.257.13:32:57.17:!2006.257.13:33:53 2006.257.13:33:53.00:preob 2006.257.13:33:54.14/onsource/TRACKING 2006.257.13:33:54.14:!2006.257.13:34:03 2006.257.13:34:03.00:"tape 2006.257.13:34:03.00:"st=record 2006.257.13:34:03.00:data_valid=on 2006.257.13:34:03.00:midob 2006.257.13:34:03.14/onsource/TRACKING 2006.257.13:34:03.14/wx/17.49,1013.9,98 2006.257.13:34:03.28/cable/+6.4816E-03 2006.257.13:34:04.37/va/01,08,usb,yes,33,35 2006.257.13:34:04.37/va/02,07,usb,yes,35,36 2006.257.13:34:04.37/va/03,08,usb,yes,32,34 2006.257.13:34:04.37/va/04,07,usb,yes,37,38 2006.257.13:34:04.37/va/05,04,usb,yes,33,33 2006.257.13:34:04.37/va/06,04,usb,yes,36,36 2006.257.13:34:04.37/va/07,04,usb,yes,37,38 2006.257.13:34:04.37/va/08,04,usb,yes,31,38 2006.257.13:34:04.60/valo/01,524.99,yes,locked 2006.257.13:34:04.60/valo/02,534.99,yes,locked 2006.257.13:34:04.60/valo/03,564.99,yes,locked 2006.257.13:34:04.60/valo/04,624.99,yes,locked 2006.257.13:34:04.60/valo/05,734.99,yes,locked 2006.257.13:34:04.60/valo/06,814.99,yes,locked 2006.257.13:34:04.60/valo/07,864.99,yes,locked 2006.257.13:34:04.60/valo/08,884.99,yes,locked 2006.257.13:34:05.69/vb/01,04,usb,yes,32,29 2006.257.13:34:05.69/vb/02,05,usb,yes,30,30 2006.257.13:34:05.69/vb/03,04,usb,yes,31,34 2006.257.13:34:05.69/vb/04,05,usb,yes,31,30 2006.257.13:34:05.69/vb/05,04,usb,yes,28,30 2006.257.13:34:05.69/vb/06,04,usb,yes,32,28 2006.257.13:34:05.69/vb/07,04,usb,yes,32,32 2006.257.13:34:05.69/vb/08,04,usb,yes,29,33 2006.257.13:34:05.92/vblo/01,629.99,yes,locked 2006.257.13:34:05.92/vblo/02,634.99,yes,locked 2006.257.13:34:05.92/vblo/03,649.99,yes,locked 2006.257.13:34:05.92/vblo/04,679.99,yes,locked 2006.257.13:34:05.92/vblo/05,709.99,yes,locked 2006.257.13:34:05.92/vblo/06,719.99,yes,locked 2006.257.13:34:05.92/vblo/07,734.99,yes,locked 2006.257.13:34:05.92/vblo/08,744.99,yes,locked 2006.257.13:34:06.07/vabw/8 2006.257.13:34:06.22/vbbw/8 2006.257.13:34:06.31/xfe/off,on,15.5 2006.257.13:34:06.69/ifatt/23,28,28,28 2006.257.13:34:07.08/fmout-gps/S +4.61E-07 2006.257.13:34:07.12:!2006.257.13:35:23 2006.257.13:35:23.01:data_valid=off 2006.257.13:35:23.01:"et 2006.257.13:35:23.02:!+3s 2006.257.13:35:26.03:"tape 2006.257.13:35:26.03:postob 2006.257.13:35:26.20/cable/+6.4817E-03 2006.257.13:35:26.20/wx/17.50,1013.9,97 2006.257.13:35:26.26/fmout-gps/S +4.62E-07 2006.257.13:35:26.26:scan_name=257-1339,jd0609,80 2006.257.13:35:26.27:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.13:35:27.14#flagr#flagr/antenna,new-source 2006.257.13:35:27.14:checkk5 2006.257.13:35:27.57/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:35:27.97/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:35:28.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:35:28.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:35:29.14/chk_obsdata//k5ts1/T2571334??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.13:35:29.55/chk_obsdata//k5ts2/T2571334??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.13:35:29.94/chk_obsdata//k5ts3/T2571334??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.13:35:30.34/chk_obsdata//k5ts4/T2571334??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.257.13:35:31.08/k5log//k5ts1_log_newline 2006.257.13:35:31.80/k5log//k5ts2_log_newline 2006.257.13:35:32.50/k5log//k5ts3_log_newline 2006.257.13:35:33.20/k5log//k5ts4_log_newline 2006.257.13:35:33.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:35:33.22:setupk4=1 2006.257.13:35:33.22$setupk4/echo=on 2006.257.13:35:33.22$setupk4/pcalon 2006.257.13:35:33.22$pcalon/"no phase cal control is implemented here 2006.257.13:35:33.22$setupk4/"tpicd=stop 2006.257.13:35:33.22$setupk4/"rec=synch_on 2006.257.13:35:33.23$setupk4/"rec_mode=128 2006.257.13:35:33.23$setupk4/!* 2006.257.13:35:33.23$setupk4/recpk4 2006.257.13:35:33.23$recpk4/recpatch= 2006.257.13:35:33.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:35:33.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:35:33.23$setupk4/vck44 2006.257.13:35:33.23$vck44/valo=1,524.99 2006.257.13:35:33.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.13:35:33.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.13:35:33.23#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:33.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:33.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:33.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:33.23#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:35:33.23#ibcon#first serial, iclass 35, count 0 2006.257.13:35:33.23#ibcon#enter sib2, iclass 35, count 0 2006.257.13:35:33.23#ibcon#flushed, iclass 35, count 0 2006.257.13:35:33.23#ibcon#about to write, iclass 35, count 0 2006.257.13:35:33.23#ibcon#wrote, iclass 35, count 0 2006.257.13:35:33.23#ibcon#about to read 3, iclass 35, count 0 2006.257.13:35:33.25#ibcon#read 3, iclass 35, count 0 2006.257.13:35:33.25#ibcon#about to read 4, iclass 35, count 0 2006.257.13:35:33.25#ibcon#read 4, iclass 35, count 0 2006.257.13:35:33.25#ibcon#about to read 5, iclass 35, count 0 2006.257.13:35:33.25#ibcon#read 5, iclass 35, count 0 2006.257.13:35:33.25#ibcon#about to read 6, iclass 35, count 0 2006.257.13:35:33.25#ibcon#read 6, iclass 35, count 0 2006.257.13:35:33.25#ibcon#end of sib2, iclass 35, count 0 2006.257.13:35:33.25#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:35:33.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:35:33.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:35:33.25#ibcon#*before write, iclass 35, count 0 2006.257.13:35:33.25#ibcon#enter sib2, iclass 35, count 0 2006.257.13:35:33.25#ibcon#flushed, iclass 35, count 0 2006.257.13:35:33.25#ibcon#about to write, iclass 35, count 0 2006.257.13:35:33.25#ibcon#wrote, iclass 35, count 0 2006.257.13:35:33.25#ibcon#about to read 3, iclass 35, count 0 2006.257.13:35:33.30#ibcon#read 3, iclass 35, count 0 2006.257.13:35:33.30#ibcon#about to read 4, iclass 35, count 0 2006.257.13:35:33.30#ibcon#read 4, iclass 35, count 0 2006.257.13:35:33.30#ibcon#about to read 5, iclass 35, count 0 2006.257.13:35:33.30#ibcon#read 5, iclass 35, count 0 2006.257.13:35:33.30#ibcon#about to read 6, iclass 35, count 0 2006.257.13:35:33.30#ibcon#read 6, iclass 35, count 0 2006.257.13:35:33.30#ibcon#end of sib2, iclass 35, count 0 2006.257.13:35:33.30#ibcon#*after write, iclass 35, count 0 2006.257.13:35:33.30#ibcon#*before return 0, iclass 35, count 0 2006.257.13:35:33.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:33.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:33.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:35:33.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:35:33.30$vck44/va=1,8 2006.257.13:35:33.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.13:35:33.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.13:35:33.30#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:33.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:33.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:33.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:33.30#ibcon#enter wrdev, iclass 37, count 2 2006.257.13:35:33.30#ibcon#first serial, iclass 37, count 2 2006.257.13:35:33.30#ibcon#enter sib2, iclass 37, count 2 2006.257.13:35:33.30#ibcon#flushed, iclass 37, count 2 2006.257.13:35:33.30#ibcon#about to write, iclass 37, count 2 2006.257.13:35:33.30#ibcon#wrote, iclass 37, count 2 2006.257.13:35:33.30#ibcon#about to read 3, iclass 37, count 2 2006.257.13:35:33.32#ibcon#read 3, iclass 37, count 2 2006.257.13:35:33.32#ibcon#about to read 4, iclass 37, count 2 2006.257.13:35:33.32#ibcon#read 4, iclass 37, count 2 2006.257.13:35:33.32#ibcon#about to read 5, iclass 37, count 2 2006.257.13:35:33.32#ibcon#read 5, iclass 37, count 2 2006.257.13:35:33.32#ibcon#about to read 6, iclass 37, count 2 2006.257.13:35:33.32#ibcon#read 6, iclass 37, count 2 2006.257.13:35:33.32#ibcon#end of sib2, iclass 37, count 2 2006.257.13:35:33.32#ibcon#*mode == 0, iclass 37, count 2 2006.257.13:35:33.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.13:35:33.32#ibcon#[25=AT01-08\r\n] 2006.257.13:35:33.32#ibcon#*before write, iclass 37, count 2 2006.257.13:35:33.32#ibcon#enter sib2, iclass 37, count 2 2006.257.13:35:33.32#ibcon#flushed, iclass 37, count 2 2006.257.13:35:33.32#ibcon#about to write, iclass 37, count 2 2006.257.13:35:33.32#ibcon#wrote, iclass 37, count 2 2006.257.13:35:33.32#ibcon#about to read 3, iclass 37, count 2 2006.257.13:35:33.35#ibcon#read 3, iclass 37, count 2 2006.257.13:35:33.35#ibcon#about to read 4, iclass 37, count 2 2006.257.13:35:33.35#ibcon#read 4, iclass 37, count 2 2006.257.13:35:33.35#ibcon#about to read 5, iclass 37, count 2 2006.257.13:35:33.35#ibcon#read 5, iclass 37, count 2 2006.257.13:35:33.35#ibcon#about to read 6, iclass 37, count 2 2006.257.13:35:33.35#ibcon#read 6, iclass 37, count 2 2006.257.13:35:33.35#ibcon#end of sib2, iclass 37, count 2 2006.257.13:35:33.35#ibcon#*after write, iclass 37, count 2 2006.257.13:35:33.35#ibcon#*before return 0, iclass 37, count 2 2006.257.13:35:33.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:33.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:33.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.13:35:33.35#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:33.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:33.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:33.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:33.47#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:35:33.47#ibcon#first serial, iclass 37, count 0 2006.257.13:35:33.47#ibcon#enter sib2, iclass 37, count 0 2006.257.13:35:33.47#ibcon#flushed, iclass 37, count 0 2006.257.13:35:33.47#ibcon#about to write, iclass 37, count 0 2006.257.13:35:33.47#ibcon#wrote, iclass 37, count 0 2006.257.13:35:33.47#ibcon#about to read 3, iclass 37, count 0 2006.257.13:35:33.49#ibcon#read 3, iclass 37, count 0 2006.257.13:35:33.49#ibcon#about to read 4, iclass 37, count 0 2006.257.13:35:33.49#ibcon#read 4, iclass 37, count 0 2006.257.13:35:33.49#ibcon#about to read 5, iclass 37, count 0 2006.257.13:35:33.49#ibcon#read 5, iclass 37, count 0 2006.257.13:35:33.49#ibcon#about to read 6, iclass 37, count 0 2006.257.13:35:33.49#ibcon#read 6, iclass 37, count 0 2006.257.13:35:33.49#ibcon#end of sib2, iclass 37, count 0 2006.257.13:35:33.49#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:35:33.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:35:33.49#ibcon#[25=USB\r\n] 2006.257.13:35:33.49#ibcon#*before write, iclass 37, count 0 2006.257.13:35:33.49#ibcon#enter sib2, iclass 37, count 0 2006.257.13:35:33.49#ibcon#flushed, iclass 37, count 0 2006.257.13:35:33.49#ibcon#about to write, iclass 37, count 0 2006.257.13:35:33.49#ibcon#wrote, iclass 37, count 0 2006.257.13:35:33.49#ibcon#about to read 3, iclass 37, count 0 2006.257.13:35:33.52#ibcon#read 3, iclass 37, count 0 2006.257.13:35:33.52#ibcon#about to read 4, iclass 37, count 0 2006.257.13:35:33.52#ibcon#read 4, iclass 37, count 0 2006.257.13:35:33.52#ibcon#about to read 5, iclass 37, count 0 2006.257.13:35:33.52#ibcon#read 5, iclass 37, count 0 2006.257.13:35:33.52#ibcon#about to read 6, iclass 37, count 0 2006.257.13:35:33.52#ibcon#read 6, iclass 37, count 0 2006.257.13:35:33.52#ibcon#end of sib2, iclass 37, count 0 2006.257.13:35:33.52#ibcon#*after write, iclass 37, count 0 2006.257.13:35:33.52#ibcon#*before return 0, iclass 37, count 0 2006.257.13:35:33.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:33.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:33.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:35:33.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:35:33.52$vck44/valo=2,534.99 2006.257.13:35:33.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:35:33.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:35:33.52#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:33.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:33.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:33.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:33.52#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:35:33.52#ibcon#first serial, iclass 39, count 0 2006.257.13:35:33.52#ibcon#enter sib2, iclass 39, count 0 2006.257.13:35:33.52#ibcon#flushed, iclass 39, count 0 2006.257.13:35:33.52#ibcon#about to write, iclass 39, count 0 2006.257.13:35:33.52#ibcon#wrote, iclass 39, count 0 2006.257.13:35:33.52#ibcon#about to read 3, iclass 39, count 0 2006.257.13:35:33.54#ibcon#read 3, iclass 39, count 0 2006.257.13:35:33.54#ibcon#about to read 4, iclass 39, count 0 2006.257.13:35:33.54#ibcon#read 4, iclass 39, count 0 2006.257.13:35:33.54#ibcon#about to read 5, iclass 39, count 0 2006.257.13:35:33.54#ibcon#read 5, iclass 39, count 0 2006.257.13:35:33.54#ibcon#about to read 6, iclass 39, count 0 2006.257.13:35:33.54#ibcon#read 6, iclass 39, count 0 2006.257.13:35:33.54#ibcon#end of sib2, iclass 39, count 0 2006.257.13:35:33.54#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:35:33.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:35:33.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:35:33.54#ibcon#*before write, iclass 39, count 0 2006.257.13:35:33.54#ibcon#enter sib2, iclass 39, count 0 2006.257.13:35:33.54#ibcon#flushed, iclass 39, count 0 2006.257.13:35:33.54#ibcon#about to write, iclass 39, count 0 2006.257.13:35:33.54#ibcon#wrote, iclass 39, count 0 2006.257.13:35:33.54#ibcon#about to read 3, iclass 39, count 0 2006.257.13:35:33.58#ibcon#read 3, iclass 39, count 0 2006.257.13:35:33.58#ibcon#about to read 4, iclass 39, count 0 2006.257.13:35:33.58#ibcon#read 4, iclass 39, count 0 2006.257.13:35:33.58#ibcon#about to read 5, iclass 39, count 0 2006.257.13:35:33.58#ibcon#read 5, iclass 39, count 0 2006.257.13:35:33.58#ibcon#about to read 6, iclass 39, count 0 2006.257.13:35:33.58#ibcon#read 6, iclass 39, count 0 2006.257.13:35:33.58#ibcon#end of sib2, iclass 39, count 0 2006.257.13:35:33.58#ibcon#*after write, iclass 39, count 0 2006.257.13:35:33.58#ibcon#*before return 0, iclass 39, count 0 2006.257.13:35:33.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:33.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:33.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:35:33.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:35:33.58$vck44/va=2,7 2006.257.13:35:33.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.13:35:33.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.13:35:33.58#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:33.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:33.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:33.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:33.64#ibcon#enter wrdev, iclass 3, count 2 2006.257.13:35:33.64#ibcon#first serial, iclass 3, count 2 2006.257.13:35:33.64#ibcon#enter sib2, iclass 3, count 2 2006.257.13:35:33.64#ibcon#flushed, iclass 3, count 2 2006.257.13:35:33.64#ibcon#about to write, iclass 3, count 2 2006.257.13:35:33.64#ibcon#wrote, iclass 3, count 2 2006.257.13:35:33.64#ibcon#about to read 3, iclass 3, count 2 2006.257.13:35:33.66#ibcon#read 3, iclass 3, count 2 2006.257.13:35:33.66#ibcon#about to read 4, iclass 3, count 2 2006.257.13:35:33.66#ibcon#read 4, iclass 3, count 2 2006.257.13:35:33.66#ibcon#about to read 5, iclass 3, count 2 2006.257.13:35:33.66#ibcon#read 5, iclass 3, count 2 2006.257.13:35:33.66#ibcon#about to read 6, iclass 3, count 2 2006.257.13:35:33.66#ibcon#read 6, iclass 3, count 2 2006.257.13:35:33.66#ibcon#end of sib2, iclass 3, count 2 2006.257.13:35:33.66#ibcon#*mode == 0, iclass 3, count 2 2006.257.13:35:33.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.13:35:33.66#ibcon#[25=AT02-07\r\n] 2006.257.13:35:33.66#ibcon#*before write, iclass 3, count 2 2006.257.13:35:33.66#ibcon#enter sib2, iclass 3, count 2 2006.257.13:35:33.66#ibcon#flushed, iclass 3, count 2 2006.257.13:35:33.66#ibcon#about to write, iclass 3, count 2 2006.257.13:35:33.66#ibcon#wrote, iclass 3, count 2 2006.257.13:35:33.66#ibcon#about to read 3, iclass 3, count 2 2006.257.13:35:33.69#ibcon#read 3, iclass 3, count 2 2006.257.13:35:33.69#ibcon#about to read 4, iclass 3, count 2 2006.257.13:35:33.69#ibcon#read 4, iclass 3, count 2 2006.257.13:35:33.69#ibcon#about to read 5, iclass 3, count 2 2006.257.13:35:33.69#ibcon#read 5, iclass 3, count 2 2006.257.13:35:33.69#ibcon#about to read 6, iclass 3, count 2 2006.257.13:35:33.69#ibcon#read 6, iclass 3, count 2 2006.257.13:35:33.69#ibcon#end of sib2, iclass 3, count 2 2006.257.13:35:33.69#ibcon#*after write, iclass 3, count 2 2006.257.13:35:33.69#ibcon#*before return 0, iclass 3, count 2 2006.257.13:35:33.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:33.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:33.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.13:35:33.69#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:33.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:33.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:33.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:33.81#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:35:33.81#ibcon#first serial, iclass 3, count 0 2006.257.13:35:33.81#ibcon#enter sib2, iclass 3, count 0 2006.257.13:35:33.81#ibcon#flushed, iclass 3, count 0 2006.257.13:35:33.81#ibcon#about to write, iclass 3, count 0 2006.257.13:35:33.81#ibcon#wrote, iclass 3, count 0 2006.257.13:35:33.81#ibcon#about to read 3, iclass 3, count 0 2006.257.13:35:33.83#ibcon#read 3, iclass 3, count 0 2006.257.13:35:33.83#ibcon#about to read 4, iclass 3, count 0 2006.257.13:35:33.83#ibcon#read 4, iclass 3, count 0 2006.257.13:35:33.83#ibcon#about to read 5, iclass 3, count 0 2006.257.13:35:33.83#ibcon#read 5, iclass 3, count 0 2006.257.13:35:33.83#ibcon#about to read 6, iclass 3, count 0 2006.257.13:35:33.83#ibcon#read 6, iclass 3, count 0 2006.257.13:35:33.83#ibcon#end of sib2, iclass 3, count 0 2006.257.13:35:33.83#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:35:33.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:35:33.83#ibcon#[25=USB\r\n] 2006.257.13:35:33.83#ibcon#*before write, iclass 3, count 0 2006.257.13:35:33.83#ibcon#enter sib2, iclass 3, count 0 2006.257.13:35:33.83#ibcon#flushed, iclass 3, count 0 2006.257.13:35:33.83#ibcon#about to write, iclass 3, count 0 2006.257.13:35:33.83#ibcon#wrote, iclass 3, count 0 2006.257.13:35:33.83#ibcon#about to read 3, iclass 3, count 0 2006.257.13:35:33.86#ibcon#read 3, iclass 3, count 0 2006.257.13:35:33.86#ibcon#about to read 4, iclass 3, count 0 2006.257.13:35:33.86#ibcon#read 4, iclass 3, count 0 2006.257.13:35:33.86#ibcon#about to read 5, iclass 3, count 0 2006.257.13:35:33.86#ibcon#read 5, iclass 3, count 0 2006.257.13:35:33.86#ibcon#about to read 6, iclass 3, count 0 2006.257.13:35:33.86#ibcon#read 6, iclass 3, count 0 2006.257.13:35:33.86#ibcon#end of sib2, iclass 3, count 0 2006.257.13:35:33.86#ibcon#*after write, iclass 3, count 0 2006.257.13:35:33.86#ibcon#*before return 0, iclass 3, count 0 2006.257.13:35:33.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:33.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:33.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:35:33.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:35:33.86$vck44/valo=3,564.99 2006.257.13:35:33.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.13:35:33.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.13:35:33.86#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:33.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:33.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:33.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:33.86#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:35:33.86#ibcon#first serial, iclass 5, count 0 2006.257.13:35:33.86#ibcon#enter sib2, iclass 5, count 0 2006.257.13:35:33.86#ibcon#flushed, iclass 5, count 0 2006.257.13:35:33.86#ibcon#about to write, iclass 5, count 0 2006.257.13:35:33.86#ibcon#wrote, iclass 5, count 0 2006.257.13:35:33.86#ibcon#about to read 3, iclass 5, count 0 2006.257.13:35:33.88#ibcon#read 3, iclass 5, count 0 2006.257.13:35:33.88#ibcon#about to read 4, iclass 5, count 0 2006.257.13:35:33.88#ibcon#read 4, iclass 5, count 0 2006.257.13:35:33.88#ibcon#about to read 5, iclass 5, count 0 2006.257.13:35:33.88#ibcon#read 5, iclass 5, count 0 2006.257.13:35:33.88#ibcon#about to read 6, iclass 5, count 0 2006.257.13:35:33.88#ibcon#read 6, iclass 5, count 0 2006.257.13:35:33.88#ibcon#end of sib2, iclass 5, count 0 2006.257.13:35:33.88#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:35:33.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:35:33.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:35:33.88#ibcon#*before write, iclass 5, count 0 2006.257.13:35:33.88#ibcon#enter sib2, iclass 5, count 0 2006.257.13:35:33.88#ibcon#flushed, iclass 5, count 0 2006.257.13:35:33.88#ibcon#about to write, iclass 5, count 0 2006.257.13:35:33.88#ibcon#wrote, iclass 5, count 0 2006.257.13:35:33.88#ibcon#about to read 3, iclass 5, count 0 2006.257.13:35:33.92#ibcon#read 3, iclass 5, count 0 2006.257.13:35:33.92#ibcon#about to read 4, iclass 5, count 0 2006.257.13:35:33.92#ibcon#read 4, iclass 5, count 0 2006.257.13:35:33.92#ibcon#about to read 5, iclass 5, count 0 2006.257.13:35:33.92#ibcon#read 5, iclass 5, count 0 2006.257.13:35:33.92#ibcon#about to read 6, iclass 5, count 0 2006.257.13:35:33.92#ibcon#read 6, iclass 5, count 0 2006.257.13:35:33.92#ibcon#end of sib2, iclass 5, count 0 2006.257.13:35:33.92#ibcon#*after write, iclass 5, count 0 2006.257.13:35:33.92#ibcon#*before return 0, iclass 5, count 0 2006.257.13:35:33.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:33.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:33.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:35:33.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:35:33.92$vck44/va=3,8 2006.257.13:35:33.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.13:35:33.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.13:35:33.92#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:33.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:33.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:33.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:33.98#ibcon#enter wrdev, iclass 7, count 2 2006.257.13:35:33.98#ibcon#first serial, iclass 7, count 2 2006.257.13:35:33.98#ibcon#enter sib2, iclass 7, count 2 2006.257.13:35:33.98#ibcon#flushed, iclass 7, count 2 2006.257.13:35:33.98#ibcon#about to write, iclass 7, count 2 2006.257.13:35:33.98#ibcon#wrote, iclass 7, count 2 2006.257.13:35:33.98#ibcon#about to read 3, iclass 7, count 2 2006.257.13:35:34.00#ibcon#read 3, iclass 7, count 2 2006.257.13:35:34.00#ibcon#about to read 4, iclass 7, count 2 2006.257.13:35:34.00#ibcon#read 4, iclass 7, count 2 2006.257.13:35:34.00#ibcon#about to read 5, iclass 7, count 2 2006.257.13:35:34.00#ibcon#read 5, iclass 7, count 2 2006.257.13:35:34.00#ibcon#about to read 6, iclass 7, count 2 2006.257.13:35:34.00#ibcon#read 6, iclass 7, count 2 2006.257.13:35:34.00#ibcon#end of sib2, iclass 7, count 2 2006.257.13:35:34.00#ibcon#*mode == 0, iclass 7, count 2 2006.257.13:35:34.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.13:35:34.00#ibcon#[25=AT03-08\r\n] 2006.257.13:35:34.00#ibcon#*before write, iclass 7, count 2 2006.257.13:35:34.00#ibcon#enter sib2, iclass 7, count 2 2006.257.13:35:34.00#ibcon#flushed, iclass 7, count 2 2006.257.13:35:34.00#ibcon#about to write, iclass 7, count 2 2006.257.13:35:34.00#ibcon#wrote, iclass 7, count 2 2006.257.13:35:34.00#ibcon#about to read 3, iclass 7, count 2 2006.257.13:35:34.03#ibcon#read 3, iclass 7, count 2 2006.257.13:35:34.03#ibcon#about to read 4, iclass 7, count 2 2006.257.13:35:34.03#ibcon#read 4, iclass 7, count 2 2006.257.13:35:34.03#ibcon#about to read 5, iclass 7, count 2 2006.257.13:35:34.03#ibcon#read 5, iclass 7, count 2 2006.257.13:35:34.03#ibcon#about to read 6, iclass 7, count 2 2006.257.13:35:34.03#ibcon#read 6, iclass 7, count 2 2006.257.13:35:34.03#ibcon#end of sib2, iclass 7, count 2 2006.257.13:35:34.03#ibcon#*after write, iclass 7, count 2 2006.257.13:35:34.03#ibcon#*before return 0, iclass 7, count 2 2006.257.13:35:34.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:34.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:34.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.13:35:34.03#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:34.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:34.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:34.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:34.15#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:35:34.15#ibcon#first serial, iclass 7, count 0 2006.257.13:35:34.15#ibcon#enter sib2, iclass 7, count 0 2006.257.13:35:34.15#ibcon#flushed, iclass 7, count 0 2006.257.13:35:34.15#ibcon#about to write, iclass 7, count 0 2006.257.13:35:34.15#ibcon#wrote, iclass 7, count 0 2006.257.13:35:34.15#ibcon#about to read 3, iclass 7, count 0 2006.257.13:35:34.17#ibcon#read 3, iclass 7, count 0 2006.257.13:35:34.17#ibcon#about to read 4, iclass 7, count 0 2006.257.13:35:34.17#ibcon#read 4, iclass 7, count 0 2006.257.13:35:34.17#ibcon#about to read 5, iclass 7, count 0 2006.257.13:35:34.17#ibcon#read 5, iclass 7, count 0 2006.257.13:35:34.17#ibcon#about to read 6, iclass 7, count 0 2006.257.13:35:34.17#ibcon#read 6, iclass 7, count 0 2006.257.13:35:34.17#ibcon#end of sib2, iclass 7, count 0 2006.257.13:35:34.17#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:35:34.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:35:34.17#ibcon#[25=USB\r\n] 2006.257.13:35:34.17#ibcon#*before write, iclass 7, count 0 2006.257.13:35:34.17#ibcon#enter sib2, iclass 7, count 0 2006.257.13:35:34.17#ibcon#flushed, iclass 7, count 0 2006.257.13:35:34.17#ibcon#about to write, iclass 7, count 0 2006.257.13:35:34.17#ibcon#wrote, iclass 7, count 0 2006.257.13:35:34.17#ibcon#about to read 3, iclass 7, count 0 2006.257.13:35:34.20#ibcon#read 3, iclass 7, count 0 2006.257.13:35:34.20#ibcon#about to read 4, iclass 7, count 0 2006.257.13:35:34.20#ibcon#read 4, iclass 7, count 0 2006.257.13:35:34.20#ibcon#about to read 5, iclass 7, count 0 2006.257.13:35:34.20#ibcon#read 5, iclass 7, count 0 2006.257.13:35:34.20#ibcon#about to read 6, iclass 7, count 0 2006.257.13:35:34.20#ibcon#read 6, iclass 7, count 0 2006.257.13:35:34.20#ibcon#end of sib2, iclass 7, count 0 2006.257.13:35:34.20#ibcon#*after write, iclass 7, count 0 2006.257.13:35:34.20#ibcon#*before return 0, iclass 7, count 0 2006.257.13:35:34.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:34.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:34.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:35:34.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:35:34.20$vck44/valo=4,624.99 2006.257.13:35:34.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.13:35:34.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.13:35:34.20#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:34.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:34.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:34.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:34.20#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:35:34.20#ibcon#first serial, iclass 11, count 0 2006.257.13:35:34.20#ibcon#enter sib2, iclass 11, count 0 2006.257.13:35:34.20#ibcon#flushed, iclass 11, count 0 2006.257.13:35:34.20#ibcon#about to write, iclass 11, count 0 2006.257.13:35:34.20#ibcon#wrote, iclass 11, count 0 2006.257.13:35:34.20#ibcon#about to read 3, iclass 11, count 0 2006.257.13:35:34.22#ibcon#read 3, iclass 11, count 0 2006.257.13:35:34.22#ibcon#about to read 4, iclass 11, count 0 2006.257.13:35:34.22#ibcon#read 4, iclass 11, count 0 2006.257.13:35:34.22#ibcon#about to read 5, iclass 11, count 0 2006.257.13:35:34.22#ibcon#read 5, iclass 11, count 0 2006.257.13:35:34.22#ibcon#about to read 6, iclass 11, count 0 2006.257.13:35:34.22#ibcon#read 6, iclass 11, count 0 2006.257.13:35:34.22#ibcon#end of sib2, iclass 11, count 0 2006.257.13:35:34.22#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:35:34.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:35:34.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:35:34.22#ibcon#*before write, iclass 11, count 0 2006.257.13:35:34.22#ibcon#enter sib2, iclass 11, count 0 2006.257.13:35:34.22#ibcon#flushed, iclass 11, count 0 2006.257.13:35:34.22#ibcon#about to write, iclass 11, count 0 2006.257.13:35:34.22#ibcon#wrote, iclass 11, count 0 2006.257.13:35:34.22#ibcon#about to read 3, iclass 11, count 0 2006.257.13:35:34.26#ibcon#read 3, iclass 11, count 0 2006.257.13:35:34.26#ibcon#about to read 4, iclass 11, count 0 2006.257.13:35:34.26#ibcon#read 4, iclass 11, count 0 2006.257.13:35:34.26#ibcon#about to read 5, iclass 11, count 0 2006.257.13:35:34.26#ibcon#read 5, iclass 11, count 0 2006.257.13:35:34.26#ibcon#about to read 6, iclass 11, count 0 2006.257.13:35:34.26#ibcon#read 6, iclass 11, count 0 2006.257.13:35:34.26#ibcon#end of sib2, iclass 11, count 0 2006.257.13:35:34.26#ibcon#*after write, iclass 11, count 0 2006.257.13:35:34.26#ibcon#*before return 0, iclass 11, count 0 2006.257.13:35:34.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:34.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:34.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:35:34.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:35:34.26$vck44/va=4,7 2006.257.13:35:34.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.13:35:34.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.13:35:34.26#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:34.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:34.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:34.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:34.32#ibcon#enter wrdev, iclass 13, count 2 2006.257.13:35:34.32#ibcon#first serial, iclass 13, count 2 2006.257.13:35:34.32#ibcon#enter sib2, iclass 13, count 2 2006.257.13:35:34.32#ibcon#flushed, iclass 13, count 2 2006.257.13:35:34.32#ibcon#about to write, iclass 13, count 2 2006.257.13:35:34.32#ibcon#wrote, iclass 13, count 2 2006.257.13:35:34.32#ibcon#about to read 3, iclass 13, count 2 2006.257.13:35:34.34#ibcon#read 3, iclass 13, count 2 2006.257.13:35:34.34#ibcon#about to read 4, iclass 13, count 2 2006.257.13:35:34.34#ibcon#read 4, iclass 13, count 2 2006.257.13:35:34.34#ibcon#about to read 5, iclass 13, count 2 2006.257.13:35:34.34#ibcon#read 5, iclass 13, count 2 2006.257.13:35:34.34#ibcon#about to read 6, iclass 13, count 2 2006.257.13:35:34.34#ibcon#read 6, iclass 13, count 2 2006.257.13:35:34.34#ibcon#end of sib2, iclass 13, count 2 2006.257.13:35:34.34#ibcon#*mode == 0, iclass 13, count 2 2006.257.13:35:34.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.13:35:34.34#ibcon#[25=AT04-07\r\n] 2006.257.13:35:34.34#ibcon#*before write, iclass 13, count 2 2006.257.13:35:34.34#ibcon#enter sib2, iclass 13, count 2 2006.257.13:35:34.34#ibcon#flushed, iclass 13, count 2 2006.257.13:35:34.34#ibcon#about to write, iclass 13, count 2 2006.257.13:35:34.34#ibcon#wrote, iclass 13, count 2 2006.257.13:35:34.34#ibcon#about to read 3, iclass 13, count 2 2006.257.13:35:34.37#ibcon#read 3, iclass 13, count 2 2006.257.13:35:34.37#ibcon#about to read 4, iclass 13, count 2 2006.257.13:35:34.37#ibcon#read 4, iclass 13, count 2 2006.257.13:35:34.37#ibcon#about to read 5, iclass 13, count 2 2006.257.13:35:34.37#ibcon#read 5, iclass 13, count 2 2006.257.13:35:34.37#ibcon#about to read 6, iclass 13, count 2 2006.257.13:35:34.37#ibcon#read 6, iclass 13, count 2 2006.257.13:35:34.37#ibcon#end of sib2, iclass 13, count 2 2006.257.13:35:34.37#ibcon#*after write, iclass 13, count 2 2006.257.13:35:34.37#ibcon#*before return 0, iclass 13, count 2 2006.257.13:35:34.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:34.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:34.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.13:35:34.37#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:34.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:34.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:34.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:34.49#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:35:34.49#ibcon#first serial, iclass 13, count 0 2006.257.13:35:34.49#ibcon#enter sib2, iclass 13, count 0 2006.257.13:35:34.49#ibcon#flushed, iclass 13, count 0 2006.257.13:35:34.49#ibcon#about to write, iclass 13, count 0 2006.257.13:35:34.49#ibcon#wrote, iclass 13, count 0 2006.257.13:35:34.49#ibcon#about to read 3, iclass 13, count 0 2006.257.13:35:34.51#ibcon#read 3, iclass 13, count 0 2006.257.13:35:34.51#ibcon#about to read 4, iclass 13, count 0 2006.257.13:35:34.51#ibcon#read 4, iclass 13, count 0 2006.257.13:35:34.51#ibcon#about to read 5, iclass 13, count 0 2006.257.13:35:34.51#ibcon#read 5, iclass 13, count 0 2006.257.13:35:34.51#ibcon#about to read 6, iclass 13, count 0 2006.257.13:35:34.51#ibcon#read 6, iclass 13, count 0 2006.257.13:35:34.51#ibcon#end of sib2, iclass 13, count 0 2006.257.13:35:34.51#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:35:34.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:35:34.51#ibcon#[25=USB\r\n] 2006.257.13:35:34.51#ibcon#*before write, iclass 13, count 0 2006.257.13:35:34.51#ibcon#enter sib2, iclass 13, count 0 2006.257.13:35:34.51#ibcon#flushed, iclass 13, count 0 2006.257.13:35:34.51#ibcon#about to write, iclass 13, count 0 2006.257.13:35:34.51#ibcon#wrote, iclass 13, count 0 2006.257.13:35:34.51#ibcon#about to read 3, iclass 13, count 0 2006.257.13:35:34.54#ibcon#read 3, iclass 13, count 0 2006.257.13:35:34.54#ibcon#about to read 4, iclass 13, count 0 2006.257.13:35:34.54#ibcon#read 4, iclass 13, count 0 2006.257.13:35:34.54#ibcon#about to read 5, iclass 13, count 0 2006.257.13:35:34.54#ibcon#read 5, iclass 13, count 0 2006.257.13:35:34.54#ibcon#about to read 6, iclass 13, count 0 2006.257.13:35:34.54#ibcon#read 6, iclass 13, count 0 2006.257.13:35:34.54#ibcon#end of sib2, iclass 13, count 0 2006.257.13:35:34.54#ibcon#*after write, iclass 13, count 0 2006.257.13:35:34.54#ibcon#*before return 0, iclass 13, count 0 2006.257.13:35:34.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:34.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:34.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:35:34.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:35:34.54$vck44/valo=5,734.99 2006.257.13:35:34.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.13:35:34.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.13:35:34.54#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:34.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:34.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:34.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:34.54#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:35:34.54#ibcon#first serial, iclass 15, count 0 2006.257.13:35:34.54#ibcon#enter sib2, iclass 15, count 0 2006.257.13:35:34.54#ibcon#flushed, iclass 15, count 0 2006.257.13:35:34.54#ibcon#about to write, iclass 15, count 0 2006.257.13:35:34.54#ibcon#wrote, iclass 15, count 0 2006.257.13:35:34.54#ibcon#about to read 3, iclass 15, count 0 2006.257.13:35:34.56#ibcon#read 3, iclass 15, count 0 2006.257.13:35:34.56#ibcon#about to read 4, iclass 15, count 0 2006.257.13:35:34.56#ibcon#read 4, iclass 15, count 0 2006.257.13:35:34.56#ibcon#about to read 5, iclass 15, count 0 2006.257.13:35:34.56#ibcon#read 5, iclass 15, count 0 2006.257.13:35:34.56#ibcon#about to read 6, iclass 15, count 0 2006.257.13:35:34.56#ibcon#read 6, iclass 15, count 0 2006.257.13:35:34.56#ibcon#end of sib2, iclass 15, count 0 2006.257.13:35:34.56#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:35:34.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:35:34.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:35:34.56#ibcon#*before write, iclass 15, count 0 2006.257.13:35:34.56#ibcon#enter sib2, iclass 15, count 0 2006.257.13:35:34.56#ibcon#flushed, iclass 15, count 0 2006.257.13:35:34.56#ibcon#about to write, iclass 15, count 0 2006.257.13:35:34.56#ibcon#wrote, iclass 15, count 0 2006.257.13:35:34.56#ibcon#about to read 3, iclass 15, count 0 2006.257.13:35:34.60#ibcon#read 3, iclass 15, count 0 2006.257.13:35:34.60#ibcon#about to read 4, iclass 15, count 0 2006.257.13:35:34.60#ibcon#read 4, iclass 15, count 0 2006.257.13:35:34.60#ibcon#about to read 5, iclass 15, count 0 2006.257.13:35:34.60#ibcon#read 5, iclass 15, count 0 2006.257.13:35:34.60#ibcon#about to read 6, iclass 15, count 0 2006.257.13:35:34.60#ibcon#read 6, iclass 15, count 0 2006.257.13:35:34.60#ibcon#end of sib2, iclass 15, count 0 2006.257.13:35:34.60#ibcon#*after write, iclass 15, count 0 2006.257.13:35:34.60#ibcon#*before return 0, iclass 15, count 0 2006.257.13:35:34.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:34.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:34.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:35:34.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:35:34.60$vck44/va=5,4 2006.257.13:35:34.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.13:35:34.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.13:35:34.60#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:34.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:34.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:34.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:34.66#ibcon#enter wrdev, iclass 17, count 2 2006.257.13:35:34.66#ibcon#first serial, iclass 17, count 2 2006.257.13:35:34.66#ibcon#enter sib2, iclass 17, count 2 2006.257.13:35:34.66#ibcon#flushed, iclass 17, count 2 2006.257.13:35:34.66#ibcon#about to write, iclass 17, count 2 2006.257.13:35:34.66#ibcon#wrote, iclass 17, count 2 2006.257.13:35:34.66#ibcon#about to read 3, iclass 17, count 2 2006.257.13:35:34.68#ibcon#read 3, iclass 17, count 2 2006.257.13:35:34.68#ibcon#about to read 4, iclass 17, count 2 2006.257.13:35:34.68#ibcon#read 4, iclass 17, count 2 2006.257.13:35:34.68#ibcon#about to read 5, iclass 17, count 2 2006.257.13:35:34.68#ibcon#read 5, iclass 17, count 2 2006.257.13:35:34.68#ibcon#about to read 6, iclass 17, count 2 2006.257.13:35:34.68#ibcon#read 6, iclass 17, count 2 2006.257.13:35:34.68#ibcon#end of sib2, iclass 17, count 2 2006.257.13:35:34.68#ibcon#*mode == 0, iclass 17, count 2 2006.257.13:35:34.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.13:35:34.68#ibcon#[25=AT05-04\r\n] 2006.257.13:35:34.68#ibcon#*before write, iclass 17, count 2 2006.257.13:35:34.68#ibcon#enter sib2, iclass 17, count 2 2006.257.13:35:34.68#ibcon#flushed, iclass 17, count 2 2006.257.13:35:34.68#ibcon#about to write, iclass 17, count 2 2006.257.13:35:34.68#ibcon#wrote, iclass 17, count 2 2006.257.13:35:34.68#ibcon#about to read 3, iclass 17, count 2 2006.257.13:35:34.71#ibcon#read 3, iclass 17, count 2 2006.257.13:35:34.71#ibcon#about to read 4, iclass 17, count 2 2006.257.13:35:34.71#ibcon#read 4, iclass 17, count 2 2006.257.13:35:34.71#ibcon#about to read 5, iclass 17, count 2 2006.257.13:35:34.71#ibcon#read 5, iclass 17, count 2 2006.257.13:35:34.71#ibcon#about to read 6, iclass 17, count 2 2006.257.13:35:34.71#ibcon#read 6, iclass 17, count 2 2006.257.13:35:34.71#ibcon#end of sib2, iclass 17, count 2 2006.257.13:35:34.71#ibcon#*after write, iclass 17, count 2 2006.257.13:35:34.71#ibcon#*before return 0, iclass 17, count 2 2006.257.13:35:34.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:34.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:34.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.13:35:34.71#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:34.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:34.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:34.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:34.83#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:35:34.83#ibcon#first serial, iclass 17, count 0 2006.257.13:35:34.83#ibcon#enter sib2, iclass 17, count 0 2006.257.13:35:34.83#ibcon#flushed, iclass 17, count 0 2006.257.13:35:34.83#ibcon#about to write, iclass 17, count 0 2006.257.13:35:34.83#ibcon#wrote, iclass 17, count 0 2006.257.13:35:34.83#ibcon#about to read 3, iclass 17, count 0 2006.257.13:35:34.85#ibcon#read 3, iclass 17, count 0 2006.257.13:35:34.85#ibcon#about to read 4, iclass 17, count 0 2006.257.13:35:34.85#ibcon#read 4, iclass 17, count 0 2006.257.13:35:34.85#ibcon#about to read 5, iclass 17, count 0 2006.257.13:35:34.85#ibcon#read 5, iclass 17, count 0 2006.257.13:35:34.85#ibcon#about to read 6, iclass 17, count 0 2006.257.13:35:34.85#ibcon#read 6, iclass 17, count 0 2006.257.13:35:34.85#ibcon#end of sib2, iclass 17, count 0 2006.257.13:35:34.85#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:35:34.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:35:34.85#ibcon#[25=USB\r\n] 2006.257.13:35:34.85#ibcon#*before write, iclass 17, count 0 2006.257.13:35:34.85#ibcon#enter sib2, iclass 17, count 0 2006.257.13:35:34.85#ibcon#flushed, iclass 17, count 0 2006.257.13:35:34.85#ibcon#about to write, iclass 17, count 0 2006.257.13:35:34.85#ibcon#wrote, iclass 17, count 0 2006.257.13:35:34.85#ibcon#about to read 3, iclass 17, count 0 2006.257.13:35:34.88#ibcon#read 3, iclass 17, count 0 2006.257.13:35:34.88#ibcon#about to read 4, iclass 17, count 0 2006.257.13:35:34.88#ibcon#read 4, iclass 17, count 0 2006.257.13:35:34.88#ibcon#about to read 5, iclass 17, count 0 2006.257.13:35:34.88#ibcon#read 5, iclass 17, count 0 2006.257.13:35:34.88#ibcon#about to read 6, iclass 17, count 0 2006.257.13:35:34.88#ibcon#read 6, iclass 17, count 0 2006.257.13:35:34.88#ibcon#end of sib2, iclass 17, count 0 2006.257.13:35:34.88#ibcon#*after write, iclass 17, count 0 2006.257.13:35:34.88#ibcon#*before return 0, iclass 17, count 0 2006.257.13:35:34.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:34.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:34.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:35:34.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:35:34.88$vck44/valo=6,814.99 2006.257.13:35:34.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.13:35:34.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.13:35:34.88#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:34.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:34.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:34.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:34.88#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:35:34.88#ibcon#first serial, iclass 19, count 0 2006.257.13:35:34.88#ibcon#enter sib2, iclass 19, count 0 2006.257.13:35:34.88#ibcon#flushed, iclass 19, count 0 2006.257.13:35:34.88#ibcon#about to write, iclass 19, count 0 2006.257.13:35:34.88#ibcon#wrote, iclass 19, count 0 2006.257.13:35:34.88#ibcon#about to read 3, iclass 19, count 0 2006.257.13:35:34.90#ibcon#read 3, iclass 19, count 0 2006.257.13:35:34.90#ibcon#about to read 4, iclass 19, count 0 2006.257.13:35:34.90#ibcon#read 4, iclass 19, count 0 2006.257.13:35:34.90#ibcon#about to read 5, iclass 19, count 0 2006.257.13:35:34.90#ibcon#read 5, iclass 19, count 0 2006.257.13:35:34.90#ibcon#about to read 6, iclass 19, count 0 2006.257.13:35:34.90#ibcon#read 6, iclass 19, count 0 2006.257.13:35:34.90#ibcon#end of sib2, iclass 19, count 0 2006.257.13:35:34.90#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:35:34.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:35:34.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:35:34.90#ibcon#*before write, iclass 19, count 0 2006.257.13:35:34.90#ibcon#enter sib2, iclass 19, count 0 2006.257.13:35:34.90#ibcon#flushed, iclass 19, count 0 2006.257.13:35:34.90#ibcon#about to write, iclass 19, count 0 2006.257.13:35:34.90#ibcon#wrote, iclass 19, count 0 2006.257.13:35:34.90#ibcon#about to read 3, iclass 19, count 0 2006.257.13:35:34.94#ibcon#read 3, iclass 19, count 0 2006.257.13:35:34.94#ibcon#about to read 4, iclass 19, count 0 2006.257.13:35:34.94#ibcon#read 4, iclass 19, count 0 2006.257.13:35:34.94#ibcon#about to read 5, iclass 19, count 0 2006.257.13:35:34.94#ibcon#read 5, iclass 19, count 0 2006.257.13:35:34.94#ibcon#about to read 6, iclass 19, count 0 2006.257.13:35:34.94#ibcon#read 6, iclass 19, count 0 2006.257.13:35:34.94#ibcon#end of sib2, iclass 19, count 0 2006.257.13:35:34.94#ibcon#*after write, iclass 19, count 0 2006.257.13:35:34.94#ibcon#*before return 0, iclass 19, count 0 2006.257.13:35:34.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:34.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:34.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:35:34.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:35:34.94$vck44/va=6,4 2006.257.13:35:34.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.13:35:34.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.13:35:34.94#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:34.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:35.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:35.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:35.00#ibcon#enter wrdev, iclass 21, count 2 2006.257.13:35:35.00#ibcon#first serial, iclass 21, count 2 2006.257.13:35:35.00#ibcon#enter sib2, iclass 21, count 2 2006.257.13:35:35.00#ibcon#flushed, iclass 21, count 2 2006.257.13:35:35.00#ibcon#about to write, iclass 21, count 2 2006.257.13:35:35.00#ibcon#wrote, iclass 21, count 2 2006.257.13:35:35.00#ibcon#about to read 3, iclass 21, count 2 2006.257.13:35:35.02#ibcon#read 3, iclass 21, count 2 2006.257.13:35:35.02#ibcon#about to read 4, iclass 21, count 2 2006.257.13:35:35.02#ibcon#read 4, iclass 21, count 2 2006.257.13:35:35.02#ibcon#about to read 5, iclass 21, count 2 2006.257.13:35:35.02#ibcon#read 5, iclass 21, count 2 2006.257.13:35:35.02#ibcon#about to read 6, iclass 21, count 2 2006.257.13:35:35.02#ibcon#read 6, iclass 21, count 2 2006.257.13:35:35.02#ibcon#end of sib2, iclass 21, count 2 2006.257.13:35:35.02#ibcon#*mode == 0, iclass 21, count 2 2006.257.13:35:35.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.13:35:35.02#ibcon#[25=AT06-04\r\n] 2006.257.13:35:35.02#ibcon#*before write, iclass 21, count 2 2006.257.13:35:35.02#ibcon#enter sib2, iclass 21, count 2 2006.257.13:35:35.02#ibcon#flushed, iclass 21, count 2 2006.257.13:35:35.02#ibcon#about to write, iclass 21, count 2 2006.257.13:35:35.02#ibcon#wrote, iclass 21, count 2 2006.257.13:35:35.02#ibcon#about to read 3, iclass 21, count 2 2006.257.13:35:35.05#ibcon#read 3, iclass 21, count 2 2006.257.13:35:35.05#ibcon#about to read 4, iclass 21, count 2 2006.257.13:35:35.05#ibcon#read 4, iclass 21, count 2 2006.257.13:35:35.05#ibcon#about to read 5, iclass 21, count 2 2006.257.13:35:35.05#ibcon#read 5, iclass 21, count 2 2006.257.13:35:35.05#ibcon#about to read 6, iclass 21, count 2 2006.257.13:35:35.05#ibcon#read 6, iclass 21, count 2 2006.257.13:35:35.05#ibcon#end of sib2, iclass 21, count 2 2006.257.13:35:35.05#ibcon#*after write, iclass 21, count 2 2006.257.13:35:35.05#ibcon#*before return 0, iclass 21, count 2 2006.257.13:35:35.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:35.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:35.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.13:35:35.05#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:35.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:35.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:35.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:35.17#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:35:35.17#ibcon#first serial, iclass 21, count 0 2006.257.13:35:35.17#ibcon#enter sib2, iclass 21, count 0 2006.257.13:35:35.17#ibcon#flushed, iclass 21, count 0 2006.257.13:35:35.17#ibcon#about to write, iclass 21, count 0 2006.257.13:35:35.17#ibcon#wrote, iclass 21, count 0 2006.257.13:35:35.17#ibcon#about to read 3, iclass 21, count 0 2006.257.13:35:35.19#ibcon#read 3, iclass 21, count 0 2006.257.13:35:35.19#ibcon#about to read 4, iclass 21, count 0 2006.257.13:35:35.19#ibcon#read 4, iclass 21, count 0 2006.257.13:35:35.19#ibcon#about to read 5, iclass 21, count 0 2006.257.13:35:35.19#ibcon#read 5, iclass 21, count 0 2006.257.13:35:35.19#ibcon#about to read 6, iclass 21, count 0 2006.257.13:35:35.19#ibcon#read 6, iclass 21, count 0 2006.257.13:35:35.19#ibcon#end of sib2, iclass 21, count 0 2006.257.13:35:35.19#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:35:35.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:35:35.19#ibcon#[25=USB\r\n] 2006.257.13:35:35.19#ibcon#*before write, iclass 21, count 0 2006.257.13:35:35.19#ibcon#enter sib2, iclass 21, count 0 2006.257.13:35:35.19#ibcon#flushed, iclass 21, count 0 2006.257.13:35:35.19#ibcon#about to write, iclass 21, count 0 2006.257.13:35:35.19#ibcon#wrote, iclass 21, count 0 2006.257.13:35:35.19#ibcon#about to read 3, iclass 21, count 0 2006.257.13:35:35.22#ibcon#read 3, iclass 21, count 0 2006.257.13:35:35.22#ibcon#about to read 4, iclass 21, count 0 2006.257.13:35:35.22#ibcon#read 4, iclass 21, count 0 2006.257.13:35:35.22#ibcon#about to read 5, iclass 21, count 0 2006.257.13:35:35.22#ibcon#read 5, iclass 21, count 0 2006.257.13:35:35.22#ibcon#about to read 6, iclass 21, count 0 2006.257.13:35:35.22#ibcon#read 6, iclass 21, count 0 2006.257.13:35:35.22#ibcon#end of sib2, iclass 21, count 0 2006.257.13:35:35.22#ibcon#*after write, iclass 21, count 0 2006.257.13:35:35.22#ibcon#*before return 0, iclass 21, count 0 2006.257.13:35:35.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:35.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:35.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:35:35.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:35:35.22$vck44/valo=7,864.99 2006.257.13:35:35.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.13:35:35.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.13:35:35.22#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:35.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:35.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:35.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:35.22#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:35:35.22#ibcon#first serial, iclass 23, count 0 2006.257.13:35:35.22#ibcon#enter sib2, iclass 23, count 0 2006.257.13:35:35.22#ibcon#flushed, iclass 23, count 0 2006.257.13:35:35.22#ibcon#about to write, iclass 23, count 0 2006.257.13:35:35.22#ibcon#wrote, iclass 23, count 0 2006.257.13:35:35.22#ibcon#about to read 3, iclass 23, count 0 2006.257.13:35:35.24#ibcon#read 3, iclass 23, count 0 2006.257.13:35:35.24#ibcon#about to read 4, iclass 23, count 0 2006.257.13:35:35.24#ibcon#read 4, iclass 23, count 0 2006.257.13:35:35.24#ibcon#about to read 5, iclass 23, count 0 2006.257.13:35:35.24#ibcon#read 5, iclass 23, count 0 2006.257.13:35:35.24#ibcon#about to read 6, iclass 23, count 0 2006.257.13:35:35.24#ibcon#read 6, iclass 23, count 0 2006.257.13:35:35.24#ibcon#end of sib2, iclass 23, count 0 2006.257.13:35:35.24#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:35:35.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:35:35.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:35:35.24#ibcon#*before write, iclass 23, count 0 2006.257.13:35:35.24#ibcon#enter sib2, iclass 23, count 0 2006.257.13:35:35.24#ibcon#flushed, iclass 23, count 0 2006.257.13:35:35.24#ibcon#about to write, iclass 23, count 0 2006.257.13:35:35.24#ibcon#wrote, iclass 23, count 0 2006.257.13:35:35.24#ibcon#about to read 3, iclass 23, count 0 2006.257.13:35:35.28#ibcon#read 3, iclass 23, count 0 2006.257.13:35:35.28#ibcon#about to read 4, iclass 23, count 0 2006.257.13:35:35.28#ibcon#read 4, iclass 23, count 0 2006.257.13:35:35.28#ibcon#about to read 5, iclass 23, count 0 2006.257.13:35:35.28#ibcon#read 5, iclass 23, count 0 2006.257.13:35:35.28#ibcon#about to read 6, iclass 23, count 0 2006.257.13:35:35.28#ibcon#read 6, iclass 23, count 0 2006.257.13:35:35.28#ibcon#end of sib2, iclass 23, count 0 2006.257.13:35:35.28#ibcon#*after write, iclass 23, count 0 2006.257.13:35:35.28#ibcon#*before return 0, iclass 23, count 0 2006.257.13:35:35.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:35.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:35.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:35:35.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:35:35.28$vck44/va=7,4 2006.257.13:35:35.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.13:35:35.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.13:35:35.28#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:35.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:35.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:35.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:35.34#ibcon#enter wrdev, iclass 25, count 2 2006.257.13:35:35.34#ibcon#first serial, iclass 25, count 2 2006.257.13:35:35.34#ibcon#enter sib2, iclass 25, count 2 2006.257.13:35:35.34#ibcon#flushed, iclass 25, count 2 2006.257.13:35:35.34#ibcon#about to write, iclass 25, count 2 2006.257.13:35:35.34#ibcon#wrote, iclass 25, count 2 2006.257.13:35:35.34#ibcon#about to read 3, iclass 25, count 2 2006.257.13:35:35.36#ibcon#read 3, iclass 25, count 2 2006.257.13:35:35.36#ibcon#about to read 4, iclass 25, count 2 2006.257.13:35:35.36#ibcon#read 4, iclass 25, count 2 2006.257.13:35:35.36#ibcon#about to read 5, iclass 25, count 2 2006.257.13:35:35.36#ibcon#read 5, iclass 25, count 2 2006.257.13:35:35.36#ibcon#about to read 6, iclass 25, count 2 2006.257.13:35:35.36#ibcon#read 6, iclass 25, count 2 2006.257.13:35:35.36#ibcon#end of sib2, iclass 25, count 2 2006.257.13:35:35.36#ibcon#*mode == 0, iclass 25, count 2 2006.257.13:35:35.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.13:35:35.36#ibcon#[25=AT07-04\r\n] 2006.257.13:35:35.36#ibcon#*before write, iclass 25, count 2 2006.257.13:35:35.36#ibcon#enter sib2, iclass 25, count 2 2006.257.13:35:35.36#ibcon#flushed, iclass 25, count 2 2006.257.13:35:35.36#ibcon#about to write, iclass 25, count 2 2006.257.13:35:35.36#ibcon#wrote, iclass 25, count 2 2006.257.13:35:35.36#ibcon#about to read 3, iclass 25, count 2 2006.257.13:35:35.39#ibcon#read 3, iclass 25, count 2 2006.257.13:35:35.39#ibcon#about to read 4, iclass 25, count 2 2006.257.13:35:35.39#ibcon#read 4, iclass 25, count 2 2006.257.13:35:35.39#ibcon#about to read 5, iclass 25, count 2 2006.257.13:35:35.39#ibcon#read 5, iclass 25, count 2 2006.257.13:35:35.39#ibcon#about to read 6, iclass 25, count 2 2006.257.13:35:35.39#ibcon#read 6, iclass 25, count 2 2006.257.13:35:35.39#ibcon#end of sib2, iclass 25, count 2 2006.257.13:35:35.39#ibcon#*after write, iclass 25, count 2 2006.257.13:35:35.39#ibcon#*before return 0, iclass 25, count 2 2006.257.13:35:35.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:35.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:35.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.13:35:35.39#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:35.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:35.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:35.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:35.51#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:35:35.51#ibcon#first serial, iclass 25, count 0 2006.257.13:35:35.51#ibcon#enter sib2, iclass 25, count 0 2006.257.13:35:35.51#ibcon#flushed, iclass 25, count 0 2006.257.13:35:35.51#ibcon#about to write, iclass 25, count 0 2006.257.13:35:35.51#ibcon#wrote, iclass 25, count 0 2006.257.13:35:35.51#ibcon#about to read 3, iclass 25, count 0 2006.257.13:35:35.53#ibcon#read 3, iclass 25, count 0 2006.257.13:35:35.53#ibcon#about to read 4, iclass 25, count 0 2006.257.13:35:35.53#ibcon#read 4, iclass 25, count 0 2006.257.13:35:35.53#ibcon#about to read 5, iclass 25, count 0 2006.257.13:35:35.53#ibcon#read 5, iclass 25, count 0 2006.257.13:35:35.53#ibcon#about to read 6, iclass 25, count 0 2006.257.13:35:35.53#ibcon#read 6, iclass 25, count 0 2006.257.13:35:35.53#ibcon#end of sib2, iclass 25, count 0 2006.257.13:35:35.53#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:35:35.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:35:35.53#ibcon#[25=USB\r\n] 2006.257.13:35:35.53#ibcon#*before write, iclass 25, count 0 2006.257.13:35:35.53#ibcon#enter sib2, iclass 25, count 0 2006.257.13:35:35.53#ibcon#flushed, iclass 25, count 0 2006.257.13:35:35.53#ibcon#about to write, iclass 25, count 0 2006.257.13:35:35.53#ibcon#wrote, iclass 25, count 0 2006.257.13:35:35.53#ibcon#about to read 3, iclass 25, count 0 2006.257.13:35:35.56#ibcon#read 3, iclass 25, count 0 2006.257.13:35:35.56#ibcon#about to read 4, iclass 25, count 0 2006.257.13:35:35.56#ibcon#read 4, iclass 25, count 0 2006.257.13:35:35.56#ibcon#about to read 5, iclass 25, count 0 2006.257.13:35:35.56#ibcon#read 5, iclass 25, count 0 2006.257.13:35:35.56#ibcon#about to read 6, iclass 25, count 0 2006.257.13:35:35.56#ibcon#read 6, iclass 25, count 0 2006.257.13:35:35.56#ibcon#end of sib2, iclass 25, count 0 2006.257.13:35:35.56#ibcon#*after write, iclass 25, count 0 2006.257.13:35:35.56#ibcon#*before return 0, iclass 25, count 0 2006.257.13:35:35.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:35.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:35.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:35:35.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:35:35.56$vck44/valo=8,884.99 2006.257.13:35:35.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.13:35:35.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.13:35:35.56#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:35.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:35.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:35.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:35.56#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:35:35.56#ibcon#first serial, iclass 27, count 0 2006.257.13:35:35.56#ibcon#enter sib2, iclass 27, count 0 2006.257.13:35:35.56#ibcon#flushed, iclass 27, count 0 2006.257.13:35:35.56#ibcon#about to write, iclass 27, count 0 2006.257.13:35:35.56#ibcon#wrote, iclass 27, count 0 2006.257.13:35:35.56#ibcon#about to read 3, iclass 27, count 0 2006.257.13:35:35.58#ibcon#read 3, iclass 27, count 0 2006.257.13:35:35.58#ibcon#about to read 4, iclass 27, count 0 2006.257.13:35:35.58#ibcon#read 4, iclass 27, count 0 2006.257.13:35:35.58#ibcon#about to read 5, iclass 27, count 0 2006.257.13:35:35.58#ibcon#read 5, iclass 27, count 0 2006.257.13:35:35.58#ibcon#about to read 6, iclass 27, count 0 2006.257.13:35:35.58#ibcon#read 6, iclass 27, count 0 2006.257.13:35:35.58#ibcon#end of sib2, iclass 27, count 0 2006.257.13:35:35.58#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:35:35.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:35:35.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:35:35.58#ibcon#*before write, iclass 27, count 0 2006.257.13:35:35.58#ibcon#enter sib2, iclass 27, count 0 2006.257.13:35:35.58#ibcon#flushed, iclass 27, count 0 2006.257.13:35:35.58#ibcon#about to write, iclass 27, count 0 2006.257.13:35:35.58#ibcon#wrote, iclass 27, count 0 2006.257.13:35:35.58#ibcon#about to read 3, iclass 27, count 0 2006.257.13:35:35.62#ibcon#read 3, iclass 27, count 0 2006.257.13:35:35.62#ibcon#about to read 4, iclass 27, count 0 2006.257.13:35:35.62#ibcon#read 4, iclass 27, count 0 2006.257.13:35:35.62#ibcon#about to read 5, iclass 27, count 0 2006.257.13:35:35.62#ibcon#read 5, iclass 27, count 0 2006.257.13:35:35.62#ibcon#about to read 6, iclass 27, count 0 2006.257.13:35:35.62#ibcon#read 6, iclass 27, count 0 2006.257.13:35:35.62#ibcon#end of sib2, iclass 27, count 0 2006.257.13:35:35.62#ibcon#*after write, iclass 27, count 0 2006.257.13:35:35.62#ibcon#*before return 0, iclass 27, count 0 2006.257.13:35:35.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:35.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:35.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:35:35.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:35:35.62$vck44/va=8,4 2006.257.13:35:35.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.13:35:35.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.13:35:35.62#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:35.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:35:35.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:35:35.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:35:35.68#ibcon#enter wrdev, iclass 29, count 2 2006.257.13:35:35.68#ibcon#first serial, iclass 29, count 2 2006.257.13:35:35.68#ibcon#enter sib2, iclass 29, count 2 2006.257.13:35:35.68#ibcon#flushed, iclass 29, count 2 2006.257.13:35:35.68#ibcon#about to write, iclass 29, count 2 2006.257.13:35:35.68#ibcon#wrote, iclass 29, count 2 2006.257.13:35:35.68#ibcon#about to read 3, iclass 29, count 2 2006.257.13:35:35.70#ibcon#read 3, iclass 29, count 2 2006.257.13:35:35.70#ibcon#about to read 4, iclass 29, count 2 2006.257.13:35:35.70#ibcon#read 4, iclass 29, count 2 2006.257.13:35:35.70#ibcon#about to read 5, iclass 29, count 2 2006.257.13:35:35.70#ibcon#read 5, iclass 29, count 2 2006.257.13:35:35.70#ibcon#about to read 6, iclass 29, count 2 2006.257.13:35:35.70#ibcon#read 6, iclass 29, count 2 2006.257.13:35:35.70#ibcon#end of sib2, iclass 29, count 2 2006.257.13:35:35.70#ibcon#*mode == 0, iclass 29, count 2 2006.257.13:35:35.70#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.13:35:35.70#ibcon#[25=AT08-04\r\n] 2006.257.13:35:35.70#ibcon#*before write, iclass 29, count 2 2006.257.13:35:35.70#ibcon#enter sib2, iclass 29, count 2 2006.257.13:35:35.70#ibcon#flushed, iclass 29, count 2 2006.257.13:35:35.70#ibcon#about to write, iclass 29, count 2 2006.257.13:35:35.70#ibcon#wrote, iclass 29, count 2 2006.257.13:35:35.70#ibcon#about to read 3, iclass 29, count 2 2006.257.13:35:35.73#ibcon#read 3, iclass 29, count 2 2006.257.13:35:35.73#ibcon#about to read 4, iclass 29, count 2 2006.257.13:35:35.73#ibcon#read 4, iclass 29, count 2 2006.257.13:35:35.73#ibcon#about to read 5, iclass 29, count 2 2006.257.13:35:35.73#ibcon#read 5, iclass 29, count 2 2006.257.13:35:35.73#ibcon#about to read 6, iclass 29, count 2 2006.257.13:35:35.73#ibcon#read 6, iclass 29, count 2 2006.257.13:35:35.73#ibcon#end of sib2, iclass 29, count 2 2006.257.13:35:35.73#ibcon#*after write, iclass 29, count 2 2006.257.13:35:35.73#ibcon#*before return 0, iclass 29, count 2 2006.257.13:35:35.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:35:35.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:35:35.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.13:35:35.73#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:35.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:35:35.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:35:35.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:35:35.85#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:35:35.85#ibcon#first serial, iclass 29, count 0 2006.257.13:35:35.85#ibcon#enter sib2, iclass 29, count 0 2006.257.13:35:35.85#ibcon#flushed, iclass 29, count 0 2006.257.13:35:35.85#ibcon#about to write, iclass 29, count 0 2006.257.13:35:35.85#ibcon#wrote, iclass 29, count 0 2006.257.13:35:35.85#ibcon#about to read 3, iclass 29, count 0 2006.257.13:35:35.87#ibcon#read 3, iclass 29, count 0 2006.257.13:35:35.87#ibcon#about to read 4, iclass 29, count 0 2006.257.13:35:35.87#ibcon#read 4, iclass 29, count 0 2006.257.13:35:35.87#ibcon#about to read 5, iclass 29, count 0 2006.257.13:35:35.87#ibcon#read 5, iclass 29, count 0 2006.257.13:35:35.87#ibcon#about to read 6, iclass 29, count 0 2006.257.13:35:35.87#ibcon#read 6, iclass 29, count 0 2006.257.13:35:35.87#ibcon#end of sib2, iclass 29, count 0 2006.257.13:35:35.87#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:35:35.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:35:35.87#ibcon#[25=USB\r\n] 2006.257.13:35:35.87#ibcon#*before write, iclass 29, count 0 2006.257.13:35:35.87#ibcon#enter sib2, iclass 29, count 0 2006.257.13:35:35.87#ibcon#flushed, iclass 29, count 0 2006.257.13:35:35.87#ibcon#about to write, iclass 29, count 0 2006.257.13:35:35.87#ibcon#wrote, iclass 29, count 0 2006.257.13:35:35.87#ibcon#about to read 3, iclass 29, count 0 2006.257.13:35:35.90#ibcon#read 3, iclass 29, count 0 2006.257.13:35:35.90#ibcon#about to read 4, iclass 29, count 0 2006.257.13:35:35.90#ibcon#read 4, iclass 29, count 0 2006.257.13:35:35.90#ibcon#about to read 5, iclass 29, count 0 2006.257.13:35:35.90#ibcon#read 5, iclass 29, count 0 2006.257.13:35:35.90#ibcon#about to read 6, iclass 29, count 0 2006.257.13:35:35.90#ibcon#read 6, iclass 29, count 0 2006.257.13:35:35.90#ibcon#end of sib2, iclass 29, count 0 2006.257.13:35:35.90#ibcon#*after write, iclass 29, count 0 2006.257.13:35:35.90#ibcon#*before return 0, iclass 29, count 0 2006.257.13:35:35.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:35:35.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:35:35.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:35:35.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:35:35.90$vck44/vblo=1,629.99 2006.257.13:35:35.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.13:35:35.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.13:35:35.90#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:35.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:35:35.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:35:35.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:35:35.90#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:35:35.90#ibcon#first serial, iclass 31, count 0 2006.257.13:35:35.90#ibcon#enter sib2, iclass 31, count 0 2006.257.13:35:35.90#ibcon#flushed, iclass 31, count 0 2006.257.13:35:35.90#ibcon#about to write, iclass 31, count 0 2006.257.13:35:35.90#ibcon#wrote, iclass 31, count 0 2006.257.13:35:35.90#ibcon#about to read 3, iclass 31, count 0 2006.257.13:35:35.92#ibcon#read 3, iclass 31, count 0 2006.257.13:35:35.92#ibcon#about to read 4, iclass 31, count 0 2006.257.13:35:35.92#ibcon#read 4, iclass 31, count 0 2006.257.13:35:35.92#ibcon#about to read 5, iclass 31, count 0 2006.257.13:35:35.92#ibcon#read 5, iclass 31, count 0 2006.257.13:35:35.92#ibcon#about to read 6, iclass 31, count 0 2006.257.13:35:35.92#ibcon#read 6, iclass 31, count 0 2006.257.13:35:35.92#ibcon#end of sib2, iclass 31, count 0 2006.257.13:35:35.92#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:35:35.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:35:35.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:35:35.92#ibcon#*before write, iclass 31, count 0 2006.257.13:35:35.92#ibcon#enter sib2, iclass 31, count 0 2006.257.13:35:35.92#ibcon#flushed, iclass 31, count 0 2006.257.13:35:35.92#ibcon#about to write, iclass 31, count 0 2006.257.13:35:35.92#ibcon#wrote, iclass 31, count 0 2006.257.13:35:35.92#ibcon#about to read 3, iclass 31, count 0 2006.257.13:35:35.96#ibcon#read 3, iclass 31, count 0 2006.257.13:35:35.96#ibcon#about to read 4, iclass 31, count 0 2006.257.13:35:35.96#ibcon#read 4, iclass 31, count 0 2006.257.13:35:35.96#ibcon#about to read 5, iclass 31, count 0 2006.257.13:35:35.96#ibcon#read 5, iclass 31, count 0 2006.257.13:35:35.96#ibcon#about to read 6, iclass 31, count 0 2006.257.13:35:35.96#ibcon#read 6, iclass 31, count 0 2006.257.13:35:35.96#ibcon#end of sib2, iclass 31, count 0 2006.257.13:35:35.96#ibcon#*after write, iclass 31, count 0 2006.257.13:35:35.96#ibcon#*before return 0, iclass 31, count 0 2006.257.13:35:35.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:35:35.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:35:35.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:35:35.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:35:35.96$vck44/vb=1,4 2006.257.13:35:35.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.13:35:35.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.13:35:35.96#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:35.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:35:35.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:35:35.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:35:35.96#ibcon#enter wrdev, iclass 33, count 2 2006.257.13:35:35.96#ibcon#first serial, iclass 33, count 2 2006.257.13:35:35.96#ibcon#enter sib2, iclass 33, count 2 2006.257.13:35:35.96#ibcon#flushed, iclass 33, count 2 2006.257.13:35:35.96#ibcon#about to write, iclass 33, count 2 2006.257.13:35:35.96#ibcon#wrote, iclass 33, count 2 2006.257.13:35:35.96#ibcon#about to read 3, iclass 33, count 2 2006.257.13:35:35.98#ibcon#read 3, iclass 33, count 2 2006.257.13:35:35.98#ibcon#about to read 4, iclass 33, count 2 2006.257.13:35:35.98#ibcon#read 4, iclass 33, count 2 2006.257.13:35:35.98#ibcon#about to read 5, iclass 33, count 2 2006.257.13:35:35.98#ibcon#read 5, iclass 33, count 2 2006.257.13:35:35.98#ibcon#about to read 6, iclass 33, count 2 2006.257.13:35:35.98#ibcon#read 6, iclass 33, count 2 2006.257.13:35:35.98#ibcon#end of sib2, iclass 33, count 2 2006.257.13:35:35.98#ibcon#*mode == 0, iclass 33, count 2 2006.257.13:35:35.98#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.13:35:35.98#ibcon#[27=AT01-04\r\n] 2006.257.13:35:35.98#ibcon#*before write, iclass 33, count 2 2006.257.13:35:35.98#ibcon#enter sib2, iclass 33, count 2 2006.257.13:35:35.98#ibcon#flushed, iclass 33, count 2 2006.257.13:35:35.98#ibcon#about to write, iclass 33, count 2 2006.257.13:35:35.98#ibcon#wrote, iclass 33, count 2 2006.257.13:35:35.98#ibcon#about to read 3, iclass 33, count 2 2006.257.13:35:36.01#ibcon#read 3, iclass 33, count 2 2006.257.13:35:36.01#ibcon#about to read 4, iclass 33, count 2 2006.257.13:35:36.01#ibcon#read 4, iclass 33, count 2 2006.257.13:35:36.01#ibcon#about to read 5, iclass 33, count 2 2006.257.13:35:36.01#ibcon#read 5, iclass 33, count 2 2006.257.13:35:36.01#ibcon#about to read 6, iclass 33, count 2 2006.257.13:35:36.01#ibcon#read 6, iclass 33, count 2 2006.257.13:35:36.01#ibcon#end of sib2, iclass 33, count 2 2006.257.13:35:36.01#ibcon#*after write, iclass 33, count 2 2006.257.13:35:36.01#ibcon#*before return 0, iclass 33, count 2 2006.257.13:35:36.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:35:36.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:35:36.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.13:35:36.01#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:36.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:35:36.13#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:35:36.13#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:35:36.13#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:35:36.13#ibcon#first serial, iclass 33, count 0 2006.257.13:35:36.13#ibcon#enter sib2, iclass 33, count 0 2006.257.13:35:36.13#ibcon#flushed, iclass 33, count 0 2006.257.13:35:36.13#ibcon#about to write, iclass 33, count 0 2006.257.13:35:36.13#ibcon#wrote, iclass 33, count 0 2006.257.13:35:36.13#ibcon#about to read 3, iclass 33, count 0 2006.257.13:35:36.15#ibcon#read 3, iclass 33, count 0 2006.257.13:35:36.15#ibcon#about to read 4, iclass 33, count 0 2006.257.13:35:36.15#ibcon#read 4, iclass 33, count 0 2006.257.13:35:36.15#ibcon#about to read 5, iclass 33, count 0 2006.257.13:35:36.15#ibcon#read 5, iclass 33, count 0 2006.257.13:35:36.15#ibcon#about to read 6, iclass 33, count 0 2006.257.13:35:36.15#ibcon#read 6, iclass 33, count 0 2006.257.13:35:36.15#ibcon#end of sib2, iclass 33, count 0 2006.257.13:35:36.15#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:35:36.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:35:36.15#ibcon#[27=USB\r\n] 2006.257.13:35:36.15#ibcon#*before write, iclass 33, count 0 2006.257.13:35:36.15#ibcon#enter sib2, iclass 33, count 0 2006.257.13:35:36.15#ibcon#flushed, iclass 33, count 0 2006.257.13:35:36.15#ibcon#about to write, iclass 33, count 0 2006.257.13:35:36.15#ibcon#wrote, iclass 33, count 0 2006.257.13:35:36.15#ibcon#about to read 3, iclass 33, count 0 2006.257.13:35:36.18#ibcon#read 3, iclass 33, count 0 2006.257.13:35:36.18#ibcon#about to read 4, iclass 33, count 0 2006.257.13:35:36.18#ibcon#read 4, iclass 33, count 0 2006.257.13:35:36.18#ibcon#about to read 5, iclass 33, count 0 2006.257.13:35:36.18#ibcon#read 5, iclass 33, count 0 2006.257.13:35:36.18#ibcon#about to read 6, iclass 33, count 0 2006.257.13:35:36.18#ibcon#read 6, iclass 33, count 0 2006.257.13:35:36.18#ibcon#end of sib2, iclass 33, count 0 2006.257.13:35:36.18#ibcon#*after write, iclass 33, count 0 2006.257.13:35:36.18#ibcon#*before return 0, iclass 33, count 0 2006.257.13:35:36.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:35:36.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:35:36.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:35:36.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:35:36.18$vck44/vblo=2,634.99 2006.257.13:35:36.18#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.13:35:36.18#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.13:35:36.18#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:36.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:36.18#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:36.18#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:36.18#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:35:36.18#ibcon#first serial, iclass 35, count 0 2006.257.13:35:36.18#ibcon#enter sib2, iclass 35, count 0 2006.257.13:35:36.18#ibcon#flushed, iclass 35, count 0 2006.257.13:35:36.18#ibcon#about to write, iclass 35, count 0 2006.257.13:35:36.18#ibcon#wrote, iclass 35, count 0 2006.257.13:35:36.18#ibcon#about to read 3, iclass 35, count 0 2006.257.13:35:36.20#ibcon#read 3, iclass 35, count 0 2006.257.13:35:36.20#ibcon#about to read 4, iclass 35, count 0 2006.257.13:35:36.20#ibcon#read 4, iclass 35, count 0 2006.257.13:35:36.20#ibcon#about to read 5, iclass 35, count 0 2006.257.13:35:36.20#ibcon#read 5, iclass 35, count 0 2006.257.13:35:36.20#ibcon#about to read 6, iclass 35, count 0 2006.257.13:35:36.20#ibcon#read 6, iclass 35, count 0 2006.257.13:35:36.20#ibcon#end of sib2, iclass 35, count 0 2006.257.13:35:36.20#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:35:36.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:35:36.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:35:36.20#ibcon#*before write, iclass 35, count 0 2006.257.13:35:36.20#ibcon#enter sib2, iclass 35, count 0 2006.257.13:35:36.20#ibcon#flushed, iclass 35, count 0 2006.257.13:35:36.20#ibcon#about to write, iclass 35, count 0 2006.257.13:35:36.20#ibcon#wrote, iclass 35, count 0 2006.257.13:35:36.20#ibcon#about to read 3, iclass 35, count 0 2006.257.13:35:36.24#ibcon#read 3, iclass 35, count 0 2006.257.13:35:36.24#ibcon#about to read 4, iclass 35, count 0 2006.257.13:35:36.24#ibcon#read 4, iclass 35, count 0 2006.257.13:35:36.24#ibcon#about to read 5, iclass 35, count 0 2006.257.13:35:36.24#ibcon#read 5, iclass 35, count 0 2006.257.13:35:36.24#ibcon#about to read 6, iclass 35, count 0 2006.257.13:35:36.24#ibcon#read 6, iclass 35, count 0 2006.257.13:35:36.24#ibcon#end of sib2, iclass 35, count 0 2006.257.13:35:36.24#ibcon#*after write, iclass 35, count 0 2006.257.13:35:36.24#ibcon#*before return 0, iclass 35, count 0 2006.257.13:35:36.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:36.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:35:36.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:35:36.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:35:36.24$vck44/vb=2,5 2006.257.13:35:36.24#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.13:35:36.24#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.13:35:36.24#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:36.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:36.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:36.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:36.30#ibcon#enter wrdev, iclass 37, count 2 2006.257.13:35:36.30#ibcon#first serial, iclass 37, count 2 2006.257.13:35:36.30#ibcon#enter sib2, iclass 37, count 2 2006.257.13:35:36.30#ibcon#flushed, iclass 37, count 2 2006.257.13:35:36.30#ibcon#about to write, iclass 37, count 2 2006.257.13:35:36.30#ibcon#wrote, iclass 37, count 2 2006.257.13:35:36.30#ibcon#about to read 3, iclass 37, count 2 2006.257.13:35:36.32#ibcon#read 3, iclass 37, count 2 2006.257.13:35:36.32#ibcon#about to read 4, iclass 37, count 2 2006.257.13:35:36.32#ibcon#read 4, iclass 37, count 2 2006.257.13:35:36.32#ibcon#about to read 5, iclass 37, count 2 2006.257.13:35:36.32#ibcon#read 5, iclass 37, count 2 2006.257.13:35:36.32#ibcon#about to read 6, iclass 37, count 2 2006.257.13:35:36.32#ibcon#read 6, iclass 37, count 2 2006.257.13:35:36.32#ibcon#end of sib2, iclass 37, count 2 2006.257.13:35:36.32#ibcon#*mode == 0, iclass 37, count 2 2006.257.13:35:36.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.13:35:36.32#ibcon#[27=AT02-05\r\n] 2006.257.13:35:36.32#ibcon#*before write, iclass 37, count 2 2006.257.13:35:36.32#ibcon#enter sib2, iclass 37, count 2 2006.257.13:35:36.32#ibcon#flushed, iclass 37, count 2 2006.257.13:35:36.32#ibcon#about to write, iclass 37, count 2 2006.257.13:35:36.32#ibcon#wrote, iclass 37, count 2 2006.257.13:35:36.32#ibcon#about to read 3, iclass 37, count 2 2006.257.13:35:36.35#ibcon#read 3, iclass 37, count 2 2006.257.13:35:36.35#ibcon#about to read 4, iclass 37, count 2 2006.257.13:35:36.35#ibcon#read 4, iclass 37, count 2 2006.257.13:35:36.35#ibcon#about to read 5, iclass 37, count 2 2006.257.13:35:36.35#ibcon#read 5, iclass 37, count 2 2006.257.13:35:36.35#ibcon#about to read 6, iclass 37, count 2 2006.257.13:35:36.35#ibcon#read 6, iclass 37, count 2 2006.257.13:35:36.35#ibcon#end of sib2, iclass 37, count 2 2006.257.13:35:36.35#ibcon#*after write, iclass 37, count 2 2006.257.13:35:36.35#ibcon#*before return 0, iclass 37, count 2 2006.257.13:35:36.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:36.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:35:36.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.13:35:36.35#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:36.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:36.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:36.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:36.47#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:35:36.47#ibcon#first serial, iclass 37, count 0 2006.257.13:35:36.47#ibcon#enter sib2, iclass 37, count 0 2006.257.13:35:36.47#ibcon#flushed, iclass 37, count 0 2006.257.13:35:36.47#ibcon#about to write, iclass 37, count 0 2006.257.13:35:36.47#ibcon#wrote, iclass 37, count 0 2006.257.13:35:36.47#ibcon#about to read 3, iclass 37, count 0 2006.257.13:35:36.49#ibcon#read 3, iclass 37, count 0 2006.257.13:35:36.49#ibcon#about to read 4, iclass 37, count 0 2006.257.13:35:36.49#ibcon#read 4, iclass 37, count 0 2006.257.13:35:36.49#ibcon#about to read 5, iclass 37, count 0 2006.257.13:35:36.49#ibcon#read 5, iclass 37, count 0 2006.257.13:35:36.49#ibcon#about to read 6, iclass 37, count 0 2006.257.13:35:36.49#ibcon#read 6, iclass 37, count 0 2006.257.13:35:36.49#ibcon#end of sib2, iclass 37, count 0 2006.257.13:35:36.49#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:35:36.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:35:36.49#ibcon#[27=USB\r\n] 2006.257.13:35:36.49#ibcon#*before write, iclass 37, count 0 2006.257.13:35:36.49#ibcon#enter sib2, iclass 37, count 0 2006.257.13:35:36.49#ibcon#flushed, iclass 37, count 0 2006.257.13:35:36.49#ibcon#about to write, iclass 37, count 0 2006.257.13:35:36.49#ibcon#wrote, iclass 37, count 0 2006.257.13:35:36.49#ibcon#about to read 3, iclass 37, count 0 2006.257.13:35:36.52#ibcon#read 3, iclass 37, count 0 2006.257.13:35:36.52#ibcon#about to read 4, iclass 37, count 0 2006.257.13:35:36.52#ibcon#read 4, iclass 37, count 0 2006.257.13:35:36.52#ibcon#about to read 5, iclass 37, count 0 2006.257.13:35:36.52#ibcon#read 5, iclass 37, count 0 2006.257.13:35:36.52#ibcon#about to read 6, iclass 37, count 0 2006.257.13:35:36.52#ibcon#read 6, iclass 37, count 0 2006.257.13:35:36.52#ibcon#end of sib2, iclass 37, count 0 2006.257.13:35:36.52#ibcon#*after write, iclass 37, count 0 2006.257.13:35:36.52#ibcon#*before return 0, iclass 37, count 0 2006.257.13:35:36.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:36.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:35:36.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:35:36.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:35:36.52$vck44/vblo=3,649.99 2006.257.13:35:36.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:35:36.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:35:36.52#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:36.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:36.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:36.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:36.52#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:35:36.52#ibcon#first serial, iclass 39, count 0 2006.257.13:35:36.52#ibcon#enter sib2, iclass 39, count 0 2006.257.13:35:36.52#ibcon#flushed, iclass 39, count 0 2006.257.13:35:36.52#ibcon#about to write, iclass 39, count 0 2006.257.13:35:36.52#ibcon#wrote, iclass 39, count 0 2006.257.13:35:36.52#ibcon#about to read 3, iclass 39, count 0 2006.257.13:35:36.54#ibcon#read 3, iclass 39, count 0 2006.257.13:35:36.54#ibcon#about to read 4, iclass 39, count 0 2006.257.13:35:36.54#ibcon#read 4, iclass 39, count 0 2006.257.13:35:36.54#ibcon#about to read 5, iclass 39, count 0 2006.257.13:35:36.54#ibcon#read 5, iclass 39, count 0 2006.257.13:35:36.54#ibcon#about to read 6, iclass 39, count 0 2006.257.13:35:36.54#ibcon#read 6, iclass 39, count 0 2006.257.13:35:36.54#ibcon#end of sib2, iclass 39, count 0 2006.257.13:35:36.54#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:35:36.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:35:36.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:35:36.54#ibcon#*before write, iclass 39, count 0 2006.257.13:35:36.54#ibcon#enter sib2, iclass 39, count 0 2006.257.13:35:36.54#ibcon#flushed, iclass 39, count 0 2006.257.13:35:36.54#ibcon#about to write, iclass 39, count 0 2006.257.13:35:36.54#ibcon#wrote, iclass 39, count 0 2006.257.13:35:36.54#ibcon#about to read 3, iclass 39, count 0 2006.257.13:35:36.59#ibcon#read 3, iclass 39, count 0 2006.257.13:35:36.59#ibcon#about to read 4, iclass 39, count 0 2006.257.13:35:36.59#ibcon#read 4, iclass 39, count 0 2006.257.13:35:36.59#ibcon#about to read 5, iclass 39, count 0 2006.257.13:35:36.59#ibcon#read 5, iclass 39, count 0 2006.257.13:35:36.59#ibcon#about to read 6, iclass 39, count 0 2006.257.13:35:36.59#ibcon#read 6, iclass 39, count 0 2006.257.13:35:36.59#ibcon#end of sib2, iclass 39, count 0 2006.257.13:35:36.59#ibcon#*after write, iclass 39, count 0 2006.257.13:35:36.59#ibcon#*before return 0, iclass 39, count 0 2006.257.13:35:36.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:36.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:35:36.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:35:36.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:35:36.59$vck44/vb=3,4 2006.257.13:35:36.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.13:35:36.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.13:35:36.59#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:36.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:36.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:36.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:36.64#ibcon#enter wrdev, iclass 3, count 2 2006.257.13:35:36.64#ibcon#first serial, iclass 3, count 2 2006.257.13:35:36.64#ibcon#enter sib2, iclass 3, count 2 2006.257.13:35:36.64#ibcon#flushed, iclass 3, count 2 2006.257.13:35:36.64#ibcon#about to write, iclass 3, count 2 2006.257.13:35:36.64#ibcon#wrote, iclass 3, count 2 2006.257.13:35:36.64#ibcon#about to read 3, iclass 3, count 2 2006.257.13:35:36.66#ibcon#read 3, iclass 3, count 2 2006.257.13:35:36.66#ibcon#about to read 4, iclass 3, count 2 2006.257.13:35:36.66#ibcon#read 4, iclass 3, count 2 2006.257.13:35:36.66#ibcon#about to read 5, iclass 3, count 2 2006.257.13:35:36.66#ibcon#read 5, iclass 3, count 2 2006.257.13:35:36.66#ibcon#about to read 6, iclass 3, count 2 2006.257.13:35:36.66#ibcon#read 6, iclass 3, count 2 2006.257.13:35:36.66#ibcon#end of sib2, iclass 3, count 2 2006.257.13:35:36.66#ibcon#*mode == 0, iclass 3, count 2 2006.257.13:35:36.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.13:35:36.66#ibcon#[27=AT03-04\r\n] 2006.257.13:35:36.66#ibcon#*before write, iclass 3, count 2 2006.257.13:35:36.66#ibcon#enter sib2, iclass 3, count 2 2006.257.13:35:36.66#ibcon#flushed, iclass 3, count 2 2006.257.13:35:36.66#ibcon#about to write, iclass 3, count 2 2006.257.13:35:36.66#ibcon#wrote, iclass 3, count 2 2006.257.13:35:36.66#ibcon#about to read 3, iclass 3, count 2 2006.257.13:35:36.69#ibcon#read 3, iclass 3, count 2 2006.257.13:35:36.69#ibcon#about to read 4, iclass 3, count 2 2006.257.13:35:36.69#ibcon#read 4, iclass 3, count 2 2006.257.13:35:36.69#ibcon#about to read 5, iclass 3, count 2 2006.257.13:35:36.69#ibcon#read 5, iclass 3, count 2 2006.257.13:35:36.69#ibcon#about to read 6, iclass 3, count 2 2006.257.13:35:36.69#ibcon#read 6, iclass 3, count 2 2006.257.13:35:36.69#ibcon#end of sib2, iclass 3, count 2 2006.257.13:35:36.69#ibcon#*after write, iclass 3, count 2 2006.257.13:35:36.69#ibcon#*before return 0, iclass 3, count 2 2006.257.13:35:36.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:36.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:35:36.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.13:35:36.69#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:36.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:36.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:36.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:36.81#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:35:36.81#ibcon#first serial, iclass 3, count 0 2006.257.13:35:36.81#ibcon#enter sib2, iclass 3, count 0 2006.257.13:35:36.81#ibcon#flushed, iclass 3, count 0 2006.257.13:35:36.81#ibcon#about to write, iclass 3, count 0 2006.257.13:35:36.81#ibcon#wrote, iclass 3, count 0 2006.257.13:35:36.81#ibcon#about to read 3, iclass 3, count 0 2006.257.13:35:36.83#ibcon#read 3, iclass 3, count 0 2006.257.13:35:36.83#ibcon#about to read 4, iclass 3, count 0 2006.257.13:35:36.83#ibcon#read 4, iclass 3, count 0 2006.257.13:35:36.83#ibcon#about to read 5, iclass 3, count 0 2006.257.13:35:36.83#ibcon#read 5, iclass 3, count 0 2006.257.13:35:36.83#ibcon#about to read 6, iclass 3, count 0 2006.257.13:35:36.83#ibcon#read 6, iclass 3, count 0 2006.257.13:35:36.83#ibcon#end of sib2, iclass 3, count 0 2006.257.13:35:36.83#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:35:36.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:35:36.83#ibcon#[27=USB\r\n] 2006.257.13:35:36.83#ibcon#*before write, iclass 3, count 0 2006.257.13:35:36.83#ibcon#enter sib2, iclass 3, count 0 2006.257.13:35:36.83#ibcon#flushed, iclass 3, count 0 2006.257.13:35:36.83#ibcon#about to write, iclass 3, count 0 2006.257.13:35:36.83#ibcon#wrote, iclass 3, count 0 2006.257.13:35:36.83#ibcon#about to read 3, iclass 3, count 0 2006.257.13:35:36.86#ibcon#read 3, iclass 3, count 0 2006.257.13:35:36.86#ibcon#about to read 4, iclass 3, count 0 2006.257.13:35:36.86#ibcon#read 4, iclass 3, count 0 2006.257.13:35:36.86#ibcon#about to read 5, iclass 3, count 0 2006.257.13:35:36.86#ibcon#read 5, iclass 3, count 0 2006.257.13:35:36.86#ibcon#about to read 6, iclass 3, count 0 2006.257.13:35:36.86#ibcon#read 6, iclass 3, count 0 2006.257.13:35:36.86#ibcon#end of sib2, iclass 3, count 0 2006.257.13:35:36.86#ibcon#*after write, iclass 3, count 0 2006.257.13:35:36.86#ibcon#*before return 0, iclass 3, count 0 2006.257.13:35:36.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:36.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:35:36.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:35:36.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:35:36.86$vck44/vblo=4,679.99 2006.257.13:35:36.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.13:35:36.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.13:35:36.86#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:36.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:36.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:36.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:36.86#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:35:36.86#ibcon#first serial, iclass 5, count 0 2006.257.13:35:36.86#ibcon#enter sib2, iclass 5, count 0 2006.257.13:35:36.86#ibcon#flushed, iclass 5, count 0 2006.257.13:35:36.86#ibcon#about to write, iclass 5, count 0 2006.257.13:35:36.86#ibcon#wrote, iclass 5, count 0 2006.257.13:35:36.86#ibcon#about to read 3, iclass 5, count 0 2006.257.13:35:36.88#ibcon#read 3, iclass 5, count 0 2006.257.13:35:36.88#ibcon#about to read 4, iclass 5, count 0 2006.257.13:35:36.88#ibcon#read 4, iclass 5, count 0 2006.257.13:35:36.88#ibcon#about to read 5, iclass 5, count 0 2006.257.13:35:36.88#ibcon#read 5, iclass 5, count 0 2006.257.13:35:36.88#ibcon#about to read 6, iclass 5, count 0 2006.257.13:35:36.88#ibcon#read 6, iclass 5, count 0 2006.257.13:35:36.88#ibcon#end of sib2, iclass 5, count 0 2006.257.13:35:36.88#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:35:36.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:35:36.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:35:36.88#ibcon#*before write, iclass 5, count 0 2006.257.13:35:36.88#ibcon#enter sib2, iclass 5, count 0 2006.257.13:35:36.88#ibcon#flushed, iclass 5, count 0 2006.257.13:35:36.88#ibcon#about to write, iclass 5, count 0 2006.257.13:35:36.88#ibcon#wrote, iclass 5, count 0 2006.257.13:35:36.88#ibcon#about to read 3, iclass 5, count 0 2006.257.13:35:36.92#ibcon#read 3, iclass 5, count 0 2006.257.13:35:36.92#ibcon#about to read 4, iclass 5, count 0 2006.257.13:35:36.92#ibcon#read 4, iclass 5, count 0 2006.257.13:35:36.92#ibcon#about to read 5, iclass 5, count 0 2006.257.13:35:36.92#ibcon#read 5, iclass 5, count 0 2006.257.13:35:36.92#ibcon#about to read 6, iclass 5, count 0 2006.257.13:35:36.92#ibcon#read 6, iclass 5, count 0 2006.257.13:35:36.92#ibcon#end of sib2, iclass 5, count 0 2006.257.13:35:36.92#ibcon#*after write, iclass 5, count 0 2006.257.13:35:36.92#ibcon#*before return 0, iclass 5, count 0 2006.257.13:35:36.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:36.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:35:36.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:35:36.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:35:36.92$vck44/vb=4,5 2006.257.13:35:36.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.13:35:36.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.13:35:36.92#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:36.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:36.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:36.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:36.98#ibcon#enter wrdev, iclass 7, count 2 2006.257.13:35:36.98#ibcon#first serial, iclass 7, count 2 2006.257.13:35:36.98#ibcon#enter sib2, iclass 7, count 2 2006.257.13:35:36.98#ibcon#flushed, iclass 7, count 2 2006.257.13:35:36.98#ibcon#about to write, iclass 7, count 2 2006.257.13:35:36.98#ibcon#wrote, iclass 7, count 2 2006.257.13:35:36.98#ibcon#about to read 3, iclass 7, count 2 2006.257.13:35:37.00#ibcon#read 3, iclass 7, count 2 2006.257.13:35:37.00#ibcon#about to read 4, iclass 7, count 2 2006.257.13:35:37.00#ibcon#read 4, iclass 7, count 2 2006.257.13:35:37.00#ibcon#about to read 5, iclass 7, count 2 2006.257.13:35:37.00#ibcon#read 5, iclass 7, count 2 2006.257.13:35:37.00#ibcon#about to read 6, iclass 7, count 2 2006.257.13:35:37.00#ibcon#read 6, iclass 7, count 2 2006.257.13:35:37.00#ibcon#end of sib2, iclass 7, count 2 2006.257.13:35:37.00#ibcon#*mode == 0, iclass 7, count 2 2006.257.13:35:37.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.13:35:37.00#ibcon#[27=AT04-05\r\n] 2006.257.13:35:37.00#ibcon#*before write, iclass 7, count 2 2006.257.13:35:37.00#ibcon#enter sib2, iclass 7, count 2 2006.257.13:35:37.00#ibcon#flushed, iclass 7, count 2 2006.257.13:35:37.00#ibcon#about to write, iclass 7, count 2 2006.257.13:35:37.00#ibcon#wrote, iclass 7, count 2 2006.257.13:35:37.00#ibcon#about to read 3, iclass 7, count 2 2006.257.13:35:37.03#ibcon#read 3, iclass 7, count 2 2006.257.13:35:37.03#ibcon#about to read 4, iclass 7, count 2 2006.257.13:35:37.03#ibcon#read 4, iclass 7, count 2 2006.257.13:35:37.03#ibcon#about to read 5, iclass 7, count 2 2006.257.13:35:37.03#ibcon#read 5, iclass 7, count 2 2006.257.13:35:37.03#ibcon#about to read 6, iclass 7, count 2 2006.257.13:35:37.03#ibcon#read 6, iclass 7, count 2 2006.257.13:35:37.03#ibcon#end of sib2, iclass 7, count 2 2006.257.13:35:37.03#ibcon#*after write, iclass 7, count 2 2006.257.13:35:37.03#ibcon#*before return 0, iclass 7, count 2 2006.257.13:35:37.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:37.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:35:37.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.13:35:37.03#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:37.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:37.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:37.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:37.15#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:35:37.15#ibcon#first serial, iclass 7, count 0 2006.257.13:35:37.15#ibcon#enter sib2, iclass 7, count 0 2006.257.13:35:37.15#ibcon#flushed, iclass 7, count 0 2006.257.13:35:37.15#ibcon#about to write, iclass 7, count 0 2006.257.13:35:37.15#ibcon#wrote, iclass 7, count 0 2006.257.13:35:37.15#ibcon#about to read 3, iclass 7, count 0 2006.257.13:35:37.17#ibcon#read 3, iclass 7, count 0 2006.257.13:35:37.17#ibcon#about to read 4, iclass 7, count 0 2006.257.13:35:37.17#ibcon#read 4, iclass 7, count 0 2006.257.13:35:37.17#ibcon#about to read 5, iclass 7, count 0 2006.257.13:35:37.17#ibcon#read 5, iclass 7, count 0 2006.257.13:35:37.17#ibcon#about to read 6, iclass 7, count 0 2006.257.13:35:37.17#ibcon#read 6, iclass 7, count 0 2006.257.13:35:37.17#ibcon#end of sib2, iclass 7, count 0 2006.257.13:35:37.17#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:35:37.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:35:37.17#ibcon#[27=USB\r\n] 2006.257.13:35:37.17#ibcon#*before write, iclass 7, count 0 2006.257.13:35:37.17#ibcon#enter sib2, iclass 7, count 0 2006.257.13:35:37.17#ibcon#flushed, iclass 7, count 0 2006.257.13:35:37.17#ibcon#about to write, iclass 7, count 0 2006.257.13:35:37.17#ibcon#wrote, iclass 7, count 0 2006.257.13:35:37.17#ibcon#about to read 3, iclass 7, count 0 2006.257.13:35:37.20#ibcon#read 3, iclass 7, count 0 2006.257.13:35:37.20#ibcon#about to read 4, iclass 7, count 0 2006.257.13:35:37.20#ibcon#read 4, iclass 7, count 0 2006.257.13:35:37.20#ibcon#about to read 5, iclass 7, count 0 2006.257.13:35:37.20#ibcon#read 5, iclass 7, count 0 2006.257.13:35:37.20#ibcon#about to read 6, iclass 7, count 0 2006.257.13:35:37.20#ibcon#read 6, iclass 7, count 0 2006.257.13:35:37.20#ibcon#end of sib2, iclass 7, count 0 2006.257.13:35:37.20#ibcon#*after write, iclass 7, count 0 2006.257.13:35:37.20#ibcon#*before return 0, iclass 7, count 0 2006.257.13:35:37.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:37.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:35:37.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:35:37.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:35:37.20$vck44/vblo=5,709.99 2006.257.13:35:37.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.13:35:37.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.13:35:37.20#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:37.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:37.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:37.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:37.20#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:35:37.20#ibcon#first serial, iclass 11, count 0 2006.257.13:35:37.20#ibcon#enter sib2, iclass 11, count 0 2006.257.13:35:37.20#ibcon#flushed, iclass 11, count 0 2006.257.13:35:37.20#ibcon#about to write, iclass 11, count 0 2006.257.13:35:37.20#ibcon#wrote, iclass 11, count 0 2006.257.13:35:37.20#ibcon#about to read 3, iclass 11, count 0 2006.257.13:35:37.22#ibcon#read 3, iclass 11, count 0 2006.257.13:35:37.22#ibcon#about to read 4, iclass 11, count 0 2006.257.13:35:37.22#ibcon#read 4, iclass 11, count 0 2006.257.13:35:37.22#ibcon#about to read 5, iclass 11, count 0 2006.257.13:35:37.22#ibcon#read 5, iclass 11, count 0 2006.257.13:35:37.22#ibcon#about to read 6, iclass 11, count 0 2006.257.13:35:37.22#ibcon#read 6, iclass 11, count 0 2006.257.13:35:37.22#ibcon#end of sib2, iclass 11, count 0 2006.257.13:35:37.22#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:35:37.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:35:37.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:35:37.22#ibcon#*before write, iclass 11, count 0 2006.257.13:35:37.22#ibcon#enter sib2, iclass 11, count 0 2006.257.13:35:37.22#ibcon#flushed, iclass 11, count 0 2006.257.13:35:37.22#ibcon#about to write, iclass 11, count 0 2006.257.13:35:37.22#ibcon#wrote, iclass 11, count 0 2006.257.13:35:37.22#ibcon#about to read 3, iclass 11, count 0 2006.257.13:35:37.26#ibcon#read 3, iclass 11, count 0 2006.257.13:35:37.26#ibcon#about to read 4, iclass 11, count 0 2006.257.13:35:37.26#ibcon#read 4, iclass 11, count 0 2006.257.13:35:37.26#ibcon#about to read 5, iclass 11, count 0 2006.257.13:35:37.26#ibcon#read 5, iclass 11, count 0 2006.257.13:35:37.26#ibcon#about to read 6, iclass 11, count 0 2006.257.13:35:37.26#ibcon#read 6, iclass 11, count 0 2006.257.13:35:37.26#ibcon#end of sib2, iclass 11, count 0 2006.257.13:35:37.26#ibcon#*after write, iclass 11, count 0 2006.257.13:35:37.26#ibcon#*before return 0, iclass 11, count 0 2006.257.13:35:37.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:37.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:35:37.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:35:37.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:35:37.26$vck44/vb=5,4 2006.257.13:35:37.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.13:35:37.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.13:35:37.26#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:37.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:37.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:37.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:37.32#ibcon#enter wrdev, iclass 13, count 2 2006.257.13:35:37.32#ibcon#first serial, iclass 13, count 2 2006.257.13:35:37.32#ibcon#enter sib2, iclass 13, count 2 2006.257.13:35:37.32#ibcon#flushed, iclass 13, count 2 2006.257.13:35:37.32#ibcon#about to write, iclass 13, count 2 2006.257.13:35:37.32#ibcon#wrote, iclass 13, count 2 2006.257.13:35:37.32#ibcon#about to read 3, iclass 13, count 2 2006.257.13:35:37.34#ibcon#read 3, iclass 13, count 2 2006.257.13:35:37.34#ibcon#about to read 4, iclass 13, count 2 2006.257.13:35:37.34#ibcon#read 4, iclass 13, count 2 2006.257.13:35:37.34#ibcon#about to read 5, iclass 13, count 2 2006.257.13:35:37.34#ibcon#read 5, iclass 13, count 2 2006.257.13:35:37.34#ibcon#about to read 6, iclass 13, count 2 2006.257.13:35:37.34#ibcon#read 6, iclass 13, count 2 2006.257.13:35:37.34#ibcon#end of sib2, iclass 13, count 2 2006.257.13:35:37.34#ibcon#*mode == 0, iclass 13, count 2 2006.257.13:35:37.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.13:35:37.34#ibcon#[27=AT05-04\r\n] 2006.257.13:35:37.34#ibcon#*before write, iclass 13, count 2 2006.257.13:35:37.34#ibcon#enter sib2, iclass 13, count 2 2006.257.13:35:37.34#ibcon#flushed, iclass 13, count 2 2006.257.13:35:37.34#ibcon#about to write, iclass 13, count 2 2006.257.13:35:37.34#ibcon#wrote, iclass 13, count 2 2006.257.13:35:37.34#ibcon#about to read 3, iclass 13, count 2 2006.257.13:35:37.37#ibcon#read 3, iclass 13, count 2 2006.257.13:35:37.37#ibcon#about to read 4, iclass 13, count 2 2006.257.13:35:37.37#ibcon#read 4, iclass 13, count 2 2006.257.13:35:37.37#ibcon#about to read 5, iclass 13, count 2 2006.257.13:35:37.37#ibcon#read 5, iclass 13, count 2 2006.257.13:35:37.37#ibcon#about to read 6, iclass 13, count 2 2006.257.13:35:37.37#ibcon#read 6, iclass 13, count 2 2006.257.13:35:37.37#ibcon#end of sib2, iclass 13, count 2 2006.257.13:35:37.37#ibcon#*after write, iclass 13, count 2 2006.257.13:35:37.37#ibcon#*before return 0, iclass 13, count 2 2006.257.13:35:37.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:37.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:35:37.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.13:35:37.37#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:37.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:37.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:37.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:37.49#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:35:37.49#ibcon#first serial, iclass 13, count 0 2006.257.13:35:37.49#ibcon#enter sib2, iclass 13, count 0 2006.257.13:35:37.49#ibcon#flushed, iclass 13, count 0 2006.257.13:35:37.49#ibcon#about to write, iclass 13, count 0 2006.257.13:35:37.49#ibcon#wrote, iclass 13, count 0 2006.257.13:35:37.49#ibcon#about to read 3, iclass 13, count 0 2006.257.13:35:37.51#ibcon#read 3, iclass 13, count 0 2006.257.13:35:37.51#ibcon#about to read 4, iclass 13, count 0 2006.257.13:35:37.51#ibcon#read 4, iclass 13, count 0 2006.257.13:35:37.51#ibcon#about to read 5, iclass 13, count 0 2006.257.13:35:37.51#ibcon#read 5, iclass 13, count 0 2006.257.13:35:37.51#ibcon#about to read 6, iclass 13, count 0 2006.257.13:35:37.51#ibcon#read 6, iclass 13, count 0 2006.257.13:35:37.51#ibcon#end of sib2, iclass 13, count 0 2006.257.13:35:37.51#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:35:37.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:35:37.51#ibcon#[27=USB\r\n] 2006.257.13:35:37.51#ibcon#*before write, iclass 13, count 0 2006.257.13:35:37.51#ibcon#enter sib2, iclass 13, count 0 2006.257.13:35:37.51#ibcon#flushed, iclass 13, count 0 2006.257.13:35:37.51#ibcon#about to write, iclass 13, count 0 2006.257.13:35:37.51#ibcon#wrote, iclass 13, count 0 2006.257.13:35:37.51#ibcon#about to read 3, iclass 13, count 0 2006.257.13:35:37.54#ibcon#read 3, iclass 13, count 0 2006.257.13:35:37.54#ibcon#about to read 4, iclass 13, count 0 2006.257.13:35:37.54#ibcon#read 4, iclass 13, count 0 2006.257.13:35:37.54#ibcon#about to read 5, iclass 13, count 0 2006.257.13:35:37.54#ibcon#read 5, iclass 13, count 0 2006.257.13:35:37.54#ibcon#about to read 6, iclass 13, count 0 2006.257.13:35:37.54#ibcon#read 6, iclass 13, count 0 2006.257.13:35:37.54#ibcon#end of sib2, iclass 13, count 0 2006.257.13:35:37.54#ibcon#*after write, iclass 13, count 0 2006.257.13:35:37.54#ibcon#*before return 0, iclass 13, count 0 2006.257.13:35:37.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:37.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:35:37.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:35:37.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:35:37.54$vck44/vblo=6,719.99 2006.257.13:35:37.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.13:35:37.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.13:35:37.54#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:37.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:37.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:37.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:37.54#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:35:37.54#ibcon#first serial, iclass 15, count 0 2006.257.13:35:37.54#ibcon#enter sib2, iclass 15, count 0 2006.257.13:35:37.54#ibcon#flushed, iclass 15, count 0 2006.257.13:35:37.54#ibcon#about to write, iclass 15, count 0 2006.257.13:35:37.54#ibcon#wrote, iclass 15, count 0 2006.257.13:35:37.54#ibcon#about to read 3, iclass 15, count 0 2006.257.13:35:37.56#ibcon#read 3, iclass 15, count 0 2006.257.13:35:37.56#ibcon#about to read 4, iclass 15, count 0 2006.257.13:35:37.56#ibcon#read 4, iclass 15, count 0 2006.257.13:35:37.56#ibcon#about to read 5, iclass 15, count 0 2006.257.13:35:37.56#ibcon#read 5, iclass 15, count 0 2006.257.13:35:37.56#ibcon#about to read 6, iclass 15, count 0 2006.257.13:35:37.56#ibcon#read 6, iclass 15, count 0 2006.257.13:35:37.56#ibcon#end of sib2, iclass 15, count 0 2006.257.13:35:37.56#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:35:37.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:35:37.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:35:37.56#ibcon#*before write, iclass 15, count 0 2006.257.13:35:37.56#ibcon#enter sib2, iclass 15, count 0 2006.257.13:35:37.56#ibcon#flushed, iclass 15, count 0 2006.257.13:35:37.56#ibcon#about to write, iclass 15, count 0 2006.257.13:35:37.56#ibcon#wrote, iclass 15, count 0 2006.257.13:35:37.56#ibcon#about to read 3, iclass 15, count 0 2006.257.13:35:37.60#ibcon#read 3, iclass 15, count 0 2006.257.13:35:37.60#ibcon#about to read 4, iclass 15, count 0 2006.257.13:35:37.60#ibcon#read 4, iclass 15, count 0 2006.257.13:35:37.60#ibcon#about to read 5, iclass 15, count 0 2006.257.13:35:37.60#ibcon#read 5, iclass 15, count 0 2006.257.13:35:37.60#ibcon#about to read 6, iclass 15, count 0 2006.257.13:35:37.60#ibcon#read 6, iclass 15, count 0 2006.257.13:35:37.60#ibcon#end of sib2, iclass 15, count 0 2006.257.13:35:37.60#ibcon#*after write, iclass 15, count 0 2006.257.13:35:37.60#ibcon#*before return 0, iclass 15, count 0 2006.257.13:35:37.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:37.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:35:37.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:35:37.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:35:37.60$vck44/vb=6,4 2006.257.13:35:37.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.13:35:37.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.13:35:37.60#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:37.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:37.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:37.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:37.66#ibcon#enter wrdev, iclass 17, count 2 2006.257.13:35:37.66#ibcon#first serial, iclass 17, count 2 2006.257.13:35:37.66#ibcon#enter sib2, iclass 17, count 2 2006.257.13:35:37.66#ibcon#flushed, iclass 17, count 2 2006.257.13:35:37.66#ibcon#about to write, iclass 17, count 2 2006.257.13:35:37.66#ibcon#wrote, iclass 17, count 2 2006.257.13:35:37.66#ibcon#about to read 3, iclass 17, count 2 2006.257.13:35:37.68#ibcon#read 3, iclass 17, count 2 2006.257.13:35:37.68#ibcon#about to read 4, iclass 17, count 2 2006.257.13:35:37.68#ibcon#read 4, iclass 17, count 2 2006.257.13:35:37.68#ibcon#about to read 5, iclass 17, count 2 2006.257.13:35:37.68#ibcon#read 5, iclass 17, count 2 2006.257.13:35:37.68#ibcon#about to read 6, iclass 17, count 2 2006.257.13:35:37.68#ibcon#read 6, iclass 17, count 2 2006.257.13:35:37.68#ibcon#end of sib2, iclass 17, count 2 2006.257.13:35:37.68#ibcon#*mode == 0, iclass 17, count 2 2006.257.13:35:37.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.13:35:37.68#ibcon#[27=AT06-04\r\n] 2006.257.13:35:37.68#ibcon#*before write, iclass 17, count 2 2006.257.13:35:37.68#ibcon#enter sib2, iclass 17, count 2 2006.257.13:35:37.68#ibcon#flushed, iclass 17, count 2 2006.257.13:35:37.68#ibcon#about to write, iclass 17, count 2 2006.257.13:35:37.68#ibcon#wrote, iclass 17, count 2 2006.257.13:35:37.68#ibcon#about to read 3, iclass 17, count 2 2006.257.13:35:37.71#ibcon#read 3, iclass 17, count 2 2006.257.13:35:37.71#ibcon#about to read 4, iclass 17, count 2 2006.257.13:35:37.71#ibcon#read 4, iclass 17, count 2 2006.257.13:35:37.71#ibcon#about to read 5, iclass 17, count 2 2006.257.13:35:37.71#ibcon#read 5, iclass 17, count 2 2006.257.13:35:37.71#ibcon#about to read 6, iclass 17, count 2 2006.257.13:35:37.71#ibcon#read 6, iclass 17, count 2 2006.257.13:35:37.71#ibcon#end of sib2, iclass 17, count 2 2006.257.13:35:37.71#ibcon#*after write, iclass 17, count 2 2006.257.13:35:37.71#ibcon#*before return 0, iclass 17, count 2 2006.257.13:35:37.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:37.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:35:37.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.13:35:37.71#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:37.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:37.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:37.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:37.83#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:35:37.83#ibcon#first serial, iclass 17, count 0 2006.257.13:35:37.83#ibcon#enter sib2, iclass 17, count 0 2006.257.13:35:37.83#ibcon#flushed, iclass 17, count 0 2006.257.13:35:37.83#ibcon#about to write, iclass 17, count 0 2006.257.13:35:37.83#ibcon#wrote, iclass 17, count 0 2006.257.13:35:37.83#ibcon#about to read 3, iclass 17, count 0 2006.257.13:35:37.85#ibcon#read 3, iclass 17, count 0 2006.257.13:35:37.85#ibcon#about to read 4, iclass 17, count 0 2006.257.13:35:37.85#ibcon#read 4, iclass 17, count 0 2006.257.13:35:37.85#ibcon#about to read 5, iclass 17, count 0 2006.257.13:35:37.85#ibcon#read 5, iclass 17, count 0 2006.257.13:35:37.85#ibcon#about to read 6, iclass 17, count 0 2006.257.13:35:37.85#ibcon#read 6, iclass 17, count 0 2006.257.13:35:37.85#ibcon#end of sib2, iclass 17, count 0 2006.257.13:35:37.85#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:35:37.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:35:37.85#ibcon#[27=USB\r\n] 2006.257.13:35:37.85#ibcon#*before write, iclass 17, count 0 2006.257.13:35:37.85#ibcon#enter sib2, iclass 17, count 0 2006.257.13:35:37.85#ibcon#flushed, iclass 17, count 0 2006.257.13:35:37.85#ibcon#about to write, iclass 17, count 0 2006.257.13:35:37.85#ibcon#wrote, iclass 17, count 0 2006.257.13:35:37.85#ibcon#about to read 3, iclass 17, count 0 2006.257.13:35:37.88#ibcon#read 3, iclass 17, count 0 2006.257.13:35:37.88#ibcon#about to read 4, iclass 17, count 0 2006.257.13:35:37.88#ibcon#read 4, iclass 17, count 0 2006.257.13:35:37.88#ibcon#about to read 5, iclass 17, count 0 2006.257.13:35:37.88#ibcon#read 5, iclass 17, count 0 2006.257.13:35:37.88#ibcon#about to read 6, iclass 17, count 0 2006.257.13:35:37.88#ibcon#read 6, iclass 17, count 0 2006.257.13:35:37.88#ibcon#end of sib2, iclass 17, count 0 2006.257.13:35:37.88#ibcon#*after write, iclass 17, count 0 2006.257.13:35:37.88#ibcon#*before return 0, iclass 17, count 0 2006.257.13:35:37.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:37.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:35:37.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:35:37.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:35:37.88$vck44/vblo=7,734.99 2006.257.13:35:37.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.13:35:37.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.13:35:37.88#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:37.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:37.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:37.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:37.88#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:35:37.88#ibcon#first serial, iclass 19, count 0 2006.257.13:35:37.88#ibcon#enter sib2, iclass 19, count 0 2006.257.13:35:37.88#ibcon#flushed, iclass 19, count 0 2006.257.13:35:37.88#ibcon#about to write, iclass 19, count 0 2006.257.13:35:37.88#ibcon#wrote, iclass 19, count 0 2006.257.13:35:37.88#ibcon#about to read 3, iclass 19, count 0 2006.257.13:35:37.90#ibcon#read 3, iclass 19, count 0 2006.257.13:35:37.90#ibcon#about to read 4, iclass 19, count 0 2006.257.13:35:37.90#ibcon#read 4, iclass 19, count 0 2006.257.13:35:37.90#ibcon#about to read 5, iclass 19, count 0 2006.257.13:35:37.90#ibcon#read 5, iclass 19, count 0 2006.257.13:35:37.90#ibcon#about to read 6, iclass 19, count 0 2006.257.13:35:37.90#ibcon#read 6, iclass 19, count 0 2006.257.13:35:37.90#ibcon#end of sib2, iclass 19, count 0 2006.257.13:35:37.90#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:35:37.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:35:37.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:35:37.90#ibcon#*before write, iclass 19, count 0 2006.257.13:35:37.90#ibcon#enter sib2, iclass 19, count 0 2006.257.13:35:37.90#ibcon#flushed, iclass 19, count 0 2006.257.13:35:37.90#ibcon#about to write, iclass 19, count 0 2006.257.13:35:37.90#ibcon#wrote, iclass 19, count 0 2006.257.13:35:37.90#ibcon#about to read 3, iclass 19, count 0 2006.257.13:35:37.94#ibcon#read 3, iclass 19, count 0 2006.257.13:35:37.94#ibcon#about to read 4, iclass 19, count 0 2006.257.13:35:37.94#ibcon#read 4, iclass 19, count 0 2006.257.13:35:37.94#ibcon#about to read 5, iclass 19, count 0 2006.257.13:35:37.94#ibcon#read 5, iclass 19, count 0 2006.257.13:35:37.94#ibcon#about to read 6, iclass 19, count 0 2006.257.13:35:37.94#ibcon#read 6, iclass 19, count 0 2006.257.13:35:37.94#ibcon#end of sib2, iclass 19, count 0 2006.257.13:35:37.94#ibcon#*after write, iclass 19, count 0 2006.257.13:35:37.94#ibcon#*before return 0, iclass 19, count 0 2006.257.13:35:37.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:37.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:35:37.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:35:37.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:35:37.94$vck44/vb=7,4 2006.257.13:35:37.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.13:35:37.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.13:35:37.94#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:37.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:38.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:38.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:38.00#ibcon#enter wrdev, iclass 21, count 2 2006.257.13:35:38.00#ibcon#first serial, iclass 21, count 2 2006.257.13:35:38.00#ibcon#enter sib2, iclass 21, count 2 2006.257.13:35:38.00#ibcon#flushed, iclass 21, count 2 2006.257.13:35:38.00#ibcon#about to write, iclass 21, count 2 2006.257.13:35:38.00#ibcon#wrote, iclass 21, count 2 2006.257.13:35:38.00#ibcon#about to read 3, iclass 21, count 2 2006.257.13:35:38.02#ibcon#read 3, iclass 21, count 2 2006.257.13:35:38.02#ibcon#about to read 4, iclass 21, count 2 2006.257.13:35:38.02#ibcon#read 4, iclass 21, count 2 2006.257.13:35:38.02#ibcon#about to read 5, iclass 21, count 2 2006.257.13:35:38.02#ibcon#read 5, iclass 21, count 2 2006.257.13:35:38.02#ibcon#about to read 6, iclass 21, count 2 2006.257.13:35:38.02#ibcon#read 6, iclass 21, count 2 2006.257.13:35:38.02#ibcon#end of sib2, iclass 21, count 2 2006.257.13:35:38.02#ibcon#*mode == 0, iclass 21, count 2 2006.257.13:35:38.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.13:35:38.02#ibcon#[27=AT07-04\r\n] 2006.257.13:35:38.02#ibcon#*before write, iclass 21, count 2 2006.257.13:35:38.02#ibcon#enter sib2, iclass 21, count 2 2006.257.13:35:38.02#ibcon#flushed, iclass 21, count 2 2006.257.13:35:38.02#ibcon#about to write, iclass 21, count 2 2006.257.13:35:38.02#ibcon#wrote, iclass 21, count 2 2006.257.13:35:38.02#ibcon#about to read 3, iclass 21, count 2 2006.257.13:35:38.05#ibcon#read 3, iclass 21, count 2 2006.257.13:35:38.05#ibcon#about to read 4, iclass 21, count 2 2006.257.13:35:38.05#ibcon#read 4, iclass 21, count 2 2006.257.13:35:38.05#ibcon#about to read 5, iclass 21, count 2 2006.257.13:35:38.05#ibcon#read 5, iclass 21, count 2 2006.257.13:35:38.05#ibcon#about to read 6, iclass 21, count 2 2006.257.13:35:38.05#ibcon#read 6, iclass 21, count 2 2006.257.13:35:38.05#ibcon#end of sib2, iclass 21, count 2 2006.257.13:35:38.05#ibcon#*after write, iclass 21, count 2 2006.257.13:35:38.05#ibcon#*before return 0, iclass 21, count 2 2006.257.13:35:38.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:38.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:35:38.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.13:35:38.05#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:38.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:38.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:38.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:38.17#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:35:38.17#ibcon#first serial, iclass 21, count 0 2006.257.13:35:38.17#ibcon#enter sib2, iclass 21, count 0 2006.257.13:35:38.17#ibcon#flushed, iclass 21, count 0 2006.257.13:35:38.17#ibcon#about to write, iclass 21, count 0 2006.257.13:35:38.17#ibcon#wrote, iclass 21, count 0 2006.257.13:35:38.17#ibcon#about to read 3, iclass 21, count 0 2006.257.13:35:38.19#ibcon#read 3, iclass 21, count 0 2006.257.13:35:38.19#ibcon#about to read 4, iclass 21, count 0 2006.257.13:35:38.19#ibcon#read 4, iclass 21, count 0 2006.257.13:35:38.19#ibcon#about to read 5, iclass 21, count 0 2006.257.13:35:38.19#ibcon#read 5, iclass 21, count 0 2006.257.13:35:38.19#ibcon#about to read 6, iclass 21, count 0 2006.257.13:35:38.19#ibcon#read 6, iclass 21, count 0 2006.257.13:35:38.19#ibcon#end of sib2, iclass 21, count 0 2006.257.13:35:38.19#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:35:38.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:35:38.19#ibcon#[27=USB\r\n] 2006.257.13:35:38.19#ibcon#*before write, iclass 21, count 0 2006.257.13:35:38.19#ibcon#enter sib2, iclass 21, count 0 2006.257.13:35:38.19#ibcon#flushed, iclass 21, count 0 2006.257.13:35:38.19#ibcon#about to write, iclass 21, count 0 2006.257.13:35:38.19#ibcon#wrote, iclass 21, count 0 2006.257.13:35:38.19#ibcon#about to read 3, iclass 21, count 0 2006.257.13:35:38.22#ibcon#read 3, iclass 21, count 0 2006.257.13:35:38.22#ibcon#about to read 4, iclass 21, count 0 2006.257.13:35:38.22#ibcon#read 4, iclass 21, count 0 2006.257.13:35:38.22#ibcon#about to read 5, iclass 21, count 0 2006.257.13:35:38.22#ibcon#read 5, iclass 21, count 0 2006.257.13:35:38.22#ibcon#about to read 6, iclass 21, count 0 2006.257.13:35:38.22#ibcon#read 6, iclass 21, count 0 2006.257.13:35:38.22#ibcon#end of sib2, iclass 21, count 0 2006.257.13:35:38.22#ibcon#*after write, iclass 21, count 0 2006.257.13:35:38.22#ibcon#*before return 0, iclass 21, count 0 2006.257.13:35:38.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:38.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:35:38.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:35:38.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:35:38.22$vck44/vblo=8,744.99 2006.257.13:35:38.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.13:35:38.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.13:35:38.22#ibcon#ireg 17 cls_cnt 0 2006.257.13:35:38.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:38.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:38.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:38.22#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:35:38.22#ibcon#first serial, iclass 23, count 0 2006.257.13:35:38.22#ibcon#enter sib2, iclass 23, count 0 2006.257.13:35:38.22#ibcon#flushed, iclass 23, count 0 2006.257.13:35:38.22#ibcon#about to write, iclass 23, count 0 2006.257.13:35:38.22#ibcon#wrote, iclass 23, count 0 2006.257.13:35:38.22#ibcon#about to read 3, iclass 23, count 0 2006.257.13:35:38.24#ibcon#read 3, iclass 23, count 0 2006.257.13:35:38.24#ibcon#about to read 4, iclass 23, count 0 2006.257.13:35:38.24#ibcon#read 4, iclass 23, count 0 2006.257.13:35:38.24#ibcon#about to read 5, iclass 23, count 0 2006.257.13:35:38.24#ibcon#read 5, iclass 23, count 0 2006.257.13:35:38.24#ibcon#about to read 6, iclass 23, count 0 2006.257.13:35:38.24#ibcon#read 6, iclass 23, count 0 2006.257.13:35:38.24#ibcon#end of sib2, iclass 23, count 0 2006.257.13:35:38.24#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:35:38.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:35:38.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:35:38.24#ibcon#*before write, iclass 23, count 0 2006.257.13:35:38.24#ibcon#enter sib2, iclass 23, count 0 2006.257.13:35:38.24#ibcon#flushed, iclass 23, count 0 2006.257.13:35:38.24#ibcon#about to write, iclass 23, count 0 2006.257.13:35:38.24#ibcon#wrote, iclass 23, count 0 2006.257.13:35:38.24#ibcon#about to read 3, iclass 23, count 0 2006.257.13:35:38.28#ibcon#read 3, iclass 23, count 0 2006.257.13:35:38.28#ibcon#about to read 4, iclass 23, count 0 2006.257.13:35:38.28#ibcon#read 4, iclass 23, count 0 2006.257.13:35:38.28#ibcon#about to read 5, iclass 23, count 0 2006.257.13:35:38.28#ibcon#read 5, iclass 23, count 0 2006.257.13:35:38.28#ibcon#about to read 6, iclass 23, count 0 2006.257.13:35:38.28#ibcon#read 6, iclass 23, count 0 2006.257.13:35:38.28#ibcon#end of sib2, iclass 23, count 0 2006.257.13:35:38.28#ibcon#*after write, iclass 23, count 0 2006.257.13:35:38.28#ibcon#*before return 0, iclass 23, count 0 2006.257.13:35:38.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:38.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:35:38.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:35:38.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:35:38.28$vck44/vb=8,4 2006.257.13:35:38.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.13:35:38.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.13:35:38.28#ibcon#ireg 11 cls_cnt 2 2006.257.13:35:38.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:38.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:38.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:38.34#ibcon#enter wrdev, iclass 25, count 2 2006.257.13:35:38.34#ibcon#first serial, iclass 25, count 2 2006.257.13:35:38.34#ibcon#enter sib2, iclass 25, count 2 2006.257.13:35:38.34#ibcon#flushed, iclass 25, count 2 2006.257.13:35:38.34#ibcon#about to write, iclass 25, count 2 2006.257.13:35:38.34#ibcon#wrote, iclass 25, count 2 2006.257.13:35:38.34#ibcon#about to read 3, iclass 25, count 2 2006.257.13:35:38.36#ibcon#read 3, iclass 25, count 2 2006.257.13:35:38.36#ibcon#about to read 4, iclass 25, count 2 2006.257.13:35:38.36#ibcon#read 4, iclass 25, count 2 2006.257.13:35:38.36#ibcon#about to read 5, iclass 25, count 2 2006.257.13:35:38.36#ibcon#read 5, iclass 25, count 2 2006.257.13:35:38.36#ibcon#about to read 6, iclass 25, count 2 2006.257.13:35:38.36#ibcon#read 6, iclass 25, count 2 2006.257.13:35:38.36#ibcon#end of sib2, iclass 25, count 2 2006.257.13:35:38.36#ibcon#*mode == 0, iclass 25, count 2 2006.257.13:35:38.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.13:35:38.36#ibcon#[27=AT08-04\r\n] 2006.257.13:35:38.36#ibcon#*before write, iclass 25, count 2 2006.257.13:35:38.36#ibcon#enter sib2, iclass 25, count 2 2006.257.13:35:38.36#ibcon#flushed, iclass 25, count 2 2006.257.13:35:38.36#ibcon#about to write, iclass 25, count 2 2006.257.13:35:38.36#ibcon#wrote, iclass 25, count 2 2006.257.13:35:38.36#ibcon#about to read 3, iclass 25, count 2 2006.257.13:35:38.39#ibcon#read 3, iclass 25, count 2 2006.257.13:35:38.39#ibcon#about to read 4, iclass 25, count 2 2006.257.13:35:38.39#ibcon#read 4, iclass 25, count 2 2006.257.13:35:38.39#ibcon#about to read 5, iclass 25, count 2 2006.257.13:35:38.39#ibcon#read 5, iclass 25, count 2 2006.257.13:35:38.39#ibcon#about to read 6, iclass 25, count 2 2006.257.13:35:38.39#ibcon#read 6, iclass 25, count 2 2006.257.13:35:38.39#ibcon#end of sib2, iclass 25, count 2 2006.257.13:35:38.39#ibcon#*after write, iclass 25, count 2 2006.257.13:35:38.39#ibcon#*before return 0, iclass 25, count 2 2006.257.13:35:38.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:38.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:35:38.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.13:35:38.39#ibcon#ireg 7 cls_cnt 0 2006.257.13:35:38.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:38.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:38.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:38.51#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:35:38.51#ibcon#first serial, iclass 25, count 0 2006.257.13:35:38.51#ibcon#enter sib2, iclass 25, count 0 2006.257.13:35:38.51#ibcon#flushed, iclass 25, count 0 2006.257.13:35:38.51#ibcon#about to write, iclass 25, count 0 2006.257.13:35:38.51#ibcon#wrote, iclass 25, count 0 2006.257.13:35:38.51#ibcon#about to read 3, iclass 25, count 0 2006.257.13:35:38.53#ibcon#read 3, iclass 25, count 0 2006.257.13:35:38.53#ibcon#about to read 4, iclass 25, count 0 2006.257.13:35:38.53#ibcon#read 4, iclass 25, count 0 2006.257.13:35:38.53#ibcon#about to read 5, iclass 25, count 0 2006.257.13:35:38.53#ibcon#read 5, iclass 25, count 0 2006.257.13:35:38.53#ibcon#about to read 6, iclass 25, count 0 2006.257.13:35:38.53#ibcon#read 6, iclass 25, count 0 2006.257.13:35:38.53#ibcon#end of sib2, iclass 25, count 0 2006.257.13:35:38.53#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:35:38.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:35:38.53#ibcon#[27=USB\r\n] 2006.257.13:35:38.53#ibcon#*before write, iclass 25, count 0 2006.257.13:35:38.53#ibcon#enter sib2, iclass 25, count 0 2006.257.13:35:38.53#ibcon#flushed, iclass 25, count 0 2006.257.13:35:38.53#ibcon#about to write, iclass 25, count 0 2006.257.13:35:38.53#ibcon#wrote, iclass 25, count 0 2006.257.13:35:38.53#ibcon#about to read 3, iclass 25, count 0 2006.257.13:35:38.56#ibcon#read 3, iclass 25, count 0 2006.257.13:35:38.56#ibcon#about to read 4, iclass 25, count 0 2006.257.13:35:38.56#ibcon#read 4, iclass 25, count 0 2006.257.13:35:38.56#ibcon#about to read 5, iclass 25, count 0 2006.257.13:35:38.56#ibcon#read 5, iclass 25, count 0 2006.257.13:35:38.56#ibcon#about to read 6, iclass 25, count 0 2006.257.13:35:38.56#ibcon#read 6, iclass 25, count 0 2006.257.13:35:38.56#ibcon#end of sib2, iclass 25, count 0 2006.257.13:35:38.56#ibcon#*after write, iclass 25, count 0 2006.257.13:35:38.56#ibcon#*before return 0, iclass 25, count 0 2006.257.13:35:38.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:38.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:35:38.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:35:38.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:35:38.56$vck44/vabw=wide 2006.257.13:35:38.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.13:35:38.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.13:35:38.56#ibcon#ireg 8 cls_cnt 0 2006.257.13:35:38.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:38.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:38.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:38.56#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:35:38.56#ibcon#first serial, iclass 27, count 0 2006.257.13:35:38.56#ibcon#enter sib2, iclass 27, count 0 2006.257.13:35:38.56#ibcon#flushed, iclass 27, count 0 2006.257.13:35:38.56#ibcon#about to write, iclass 27, count 0 2006.257.13:35:38.56#ibcon#wrote, iclass 27, count 0 2006.257.13:35:38.56#ibcon#about to read 3, iclass 27, count 0 2006.257.13:35:38.58#ibcon#read 3, iclass 27, count 0 2006.257.13:35:38.58#ibcon#about to read 4, iclass 27, count 0 2006.257.13:35:38.58#ibcon#read 4, iclass 27, count 0 2006.257.13:35:38.58#ibcon#about to read 5, iclass 27, count 0 2006.257.13:35:38.58#ibcon#read 5, iclass 27, count 0 2006.257.13:35:38.58#ibcon#about to read 6, iclass 27, count 0 2006.257.13:35:38.58#ibcon#read 6, iclass 27, count 0 2006.257.13:35:38.58#ibcon#end of sib2, iclass 27, count 0 2006.257.13:35:38.58#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:35:38.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:35:38.58#ibcon#[25=BW32\r\n] 2006.257.13:35:38.58#ibcon#*before write, iclass 27, count 0 2006.257.13:35:38.58#ibcon#enter sib2, iclass 27, count 0 2006.257.13:35:38.58#ibcon#flushed, iclass 27, count 0 2006.257.13:35:38.58#ibcon#about to write, iclass 27, count 0 2006.257.13:35:38.58#ibcon#wrote, iclass 27, count 0 2006.257.13:35:38.58#ibcon#about to read 3, iclass 27, count 0 2006.257.13:35:38.61#ibcon#read 3, iclass 27, count 0 2006.257.13:35:38.61#ibcon#about to read 4, iclass 27, count 0 2006.257.13:35:38.61#ibcon#read 4, iclass 27, count 0 2006.257.13:35:38.61#ibcon#about to read 5, iclass 27, count 0 2006.257.13:35:38.61#ibcon#read 5, iclass 27, count 0 2006.257.13:35:38.61#ibcon#about to read 6, iclass 27, count 0 2006.257.13:35:38.61#ibcon#read 6, iclass 27, count 0 2006.257.13:35:38.61#ibcon#end of sib2, iclass 27, count 0 2006.257.13:35:38.61#ibcon#*after write, iclass 27, count 0 2006.257.13:35:38.61#ibcon#*before return 0, iclass 27, count 0 2006.257.13:35:38.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:38.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:35:38.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:35:38.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:35:38.61$vck44/vbbw=wide 2006.257.13:35:38.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.13:35:38.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.13:35:38.61#ibcon#ireg 8 cls_cnt 0 2006.257.13:35:38.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:35:38.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:35:38.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:35:38.68#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:35:38.68#ibcon#first serial, iclass 29, count 0 2006.257.13:35:38.68#ibcon#enter sib2, iclass 29, count 0 2006.257.13:35:38.68#ibcon#flushed, iclass 29, count 0 2006.257.13:35:38.68#ibcon#about to write, iclass 29, count 0 2006.257.13:35:38.68#ibcon#wrote, iclass 29, count 0 2006.257.13:35:38.68#ibcon#about to read 3, iclass 29, count 0 2006.257.13:35:38.70#ibcon#read 3, iclass 29, count 0 2006.257.13:35:38.70#ibcon#about to read 4, iclass 29, count 0 2006.257.13:35:38.70#ibcon#read 4, iclass 29, count 0 2006.257.13:35:38.70#ibcon#about to read 5, iclass 29, count 0 2006.257.13:35:38.70#ibcon#read 5, iclass 29, count 0 2006.257.13:35:38.70#ibcon#about to read 6, iclass 29, count 0 2006.257.13:35:38.70#ibcon#read 6, iclass 29, count 0 2006.257.13:35:38.70#ibcon#end of sib2, iclass 29, count 0 2006.257.13:35:38.70#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:35:38.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:35:38.70#ibcon#[27=BW32\r\n] 2006.257.13:35:38.70#ibcon#*before write, iclass 29, count 0 2006.257.13:35:38.70#ibcon#enter sib2, iclass 29, count 0 2006.257.13:35:38.70#ibcon#flushed, iclass 29, count 0 2006.257.13:35:38.70#ibcon#about to write, iclass 29, count 0 2006.257.13:35:38.70#ibcon#wrote, iclass 29, count 0 2006.257.13:35:38.70#ibcon#about to read 3, iclass 29, count 0 2006.257.13:35:38.73#ibcon#read 3, iclass 29, count 0 2006.257.13:35:38.73#ibcon#about to read 4, iclass 29, count 0 2006.257.13:35:38.73#ibcon#read 4, iclass 29, count 0 2006.257.13:35:38.73#ibcon#about to read 5, iclass 29, count 0 2006.257.13:35:38.73#ibcon#read 5, iclass 29, count 0 2006.257.13:35:38.73#ibcon#about to read 6, iclass 29, count 0 2006.257.13:35:38.73#ibcon#read 6, iclass 29, count 0 2006.257.13:35:38.73#ibcon#end of sib2, iclass 29, count 0 2006.257.13:35:38.73#ibcon#*after write, iclass 29, count 0 2006.257.13:35:38.73#ibcon#*before return 0, iclass 29, count 0 2006.257.13:35:38.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:35:38.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:35:38.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:35:38.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:35:38.73$setupk4/ifdk4 2006.257.13:35:38.73$ifdk4/lo= 2006.257.13:35:38.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:35:38.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:35:38.73$ifdk4/patch= 2006.257.13:35:38.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:35:38.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:35:38.73$setupk4/!*+20s 2006.257.13:35:38.85#abcon#<5=/14 1.1 2.9 17.50 981013.9\r\n> 2006.257.13:35:38.87#abcon#{5=INTERFACE CLEAR} 2006.257.13:35:38.93#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:35:49.02#abcon#<5=/14 1.2 2.9 17.50 981014.0\r\n> 2006.257.13:35:49.04#abcon#{5=INTERFACE CLEAR} 2006.257.13:35:49.10#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:35:53.24$setupk4/"tpicd 2006.257.13:35:53.24$setupk4/echo=off 2006.257.13:35:53.24$setupk4/xlog=off 2006.257.13:35:53.24:!2006.257.13:38:55 2006.257.13:35:59.14#trakl#Source acquired 2006.257.13:36:01.14#flagr#flagr/antenna,acquired 2006.257.13:38:55.00:preob 2006.257.13:38:56.13/onsource/TRACKING 2006.257.13:38:56.13:!2006.257.13:39:05 2006.257.13:39:05.00:"tape 2006.257.13:39:05.00:"st=record 2006.257.13:39:05.00:data_valid=on 2006.257.13:39:05.00:midob 2006.257.13:39:05.13/onsource/TRACKING 2006.257.13:39:05.13/wx/17.51,1013.9,97 2006.257.13:39:05.24/cable/+6.4822E-03 2006.257.13:39:06.33/va/01,08,usb,yes,33,35 2006.257.13:39:06.33/va/02,07,usb,yes,36,36 2006.257.13:39:06.33/va/03,08,usb,yes,32,34 2006.257.13:39:06.33/va/04,07,usb,yes,37,39 2006.257.13:39:06.33/va/05,04,usb,yes,33,34 2006.257.13:39:06.33/va/06,04,usb,yes,37,36 2006.257.13:39:06.33/va/07,04,usb,yes,38,38 2006.257.13:39:06.33/va/08,04,usb,yes,32,38 2006.257.13:39:06.56/valo/01,524.99,yes,locked 2006.257.13:39:06.56/valo/02,534.99,yes,locked 2006.257.13:39:06.56/valo/03,564.99,yes,locked 2006.257.13:39:06.56/valo/04,624.99,yes,locked 2006.257.13:39:06.56/valo/05,734.99,yes,locked 2006.257.13:39:06.56/valo/06,814.99,yes,locked 2006.257.13:39:06.56/valo/07,864.99,yes,locked 2006.257.13:39:06.56/valo/08,884.99,yes,locked 2006.257.13:39:07.65/vb/01,04,usb,yes,32,30 2006.257.13:39:07.65/vb/02,05,usb,yes,30,30 2006.257.13:39:07.65/vb/03,04,usb,yes,31,35 2006.257.13:39:07.65/vb/04,05,usb,yes,32,31 2006.257.13:39:07.65/vb/05,04,usb,yes,28,31 2006.257.13:39:07.65/vb/06,04,usb,yes,33,29 2006.257.13:39:07.65/vb/07,04,usb,yes,33,32 2006.257.13:39:07.65/vb/08,04,usb,yes,30,33 2006.257.13:39:07.88/vblo/01,629.99,yes,locked 2006.257.13:39:07.88/vblo/02,634.99,yes,locked 2006.257.13:39:07.88/vblo/03,649.99,yes,locked 2006.257.13:39:07.88/vblo/04,679.99,yes,locked 2006.257.13:39:07.88/vblo/05,709.99,yes,locked 2006.257.13:39:07.88/vblo/06,719.99,yes,locked 2006.257.13:39:07.88/vblo/07,734.99,yes,locked 2006.257.13:39:07.88/vblo/08,744.99,yes,locked 2006.257.13:39:08.03/vabw/8 2006.257.13:39:08.18/vbbw/8 2006.257.13:39:08.27/xfe/off,on,15.5 2006.257.13:39:08.65/ifatt/23,28,28,28 2006.257.13:39:09.07/fmout-gps/S +4.63E-07 2006.257.13:39:09.11:!2006.257.13:40:25 2006.257.13:40:25.00:data_valid=off 2006.257.13:40:25.00:"et 2006.257.13:40:25.00:!+3s 2006.257.13:40:28.01:"tape 2006.257.13:40:28.01:postob 2006.257.13:40:28.07/cable/+6.4814E-03 2006.257.13:40:28.07/wx/17.52,1013.9,97 2006.257.13:40:29.07/fmout-gps/S +4.63E-07 2006.257.13:40:29.07:scan_name=257-1345,jd0609,160 2006.257.13:40:29.07:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.257.13:40:30.14#flagr#flagr/antenna,new-source 2006.257.13:40:30.14:checkk5 2006.257.13:40:30.46/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:40:30.85/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:40:31.26/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:40:31.64/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:40:32.05/chk_obsdata//k5ts1/T2571339??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.13:40:32.46/chk_obsdata//k5ts2/T2571339??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.13:40:32.84/chk_obsdata//k5ts3/T2571339??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.13:40:33.24/chk_obsdata//k5ts4/T2571339??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.13:40:33.96/k5log//k5ts1_log_newline 2006.257.13:40:34.67/k5log//k5ts2_log_newline 2006.257.13:40:35.38/k5log//k5ts3_log_newline 2006.257.13:40:36.08/k5log//k5ts4_log_newline 2006.257.13:40:36.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:40:36.10:setupk4=1 2006.257.13:40:36.10$setupk4/echo=on 2006.257.13:40:36.10$setupk4/pcalon 2006.257.13:40:36.10$pcalon/"no phase cal control is implemented here 2006.257.13:40:36.11$setupk4/"tpicd=stop 2006.257.13:40:36.11$setupk4/"rec=synch_on 2006.257.13:40:36.11$setupk4/"rec_mode=128 2006.257.13:40:36.11$setupk4/!* 2006.257.13:40:36.11$setupk4/recpk4 2006.257.13:40:36.11$recpk4/recpatch= 2006.257.13:40:36.11$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:40:36.11$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:40:36.11$setupk4/vck44 2006.257.13:40:36.11$vck44/valo=1,524.99 2006.257.13:40:36.11#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.13:40:36.11#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.13:40:36.11#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:36.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:36.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:36.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:36.11#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:40:36.11#ibcon#first serial, iclass 10, count 0 2006.257.13:40:36.11#ibcon#enter sib2, iclass 10, count 0 2006.257.13:40:36.11#ibcon#flushed, iclass 10, count 0 2006.257.13:40:36.11#ibcon#about to write, iclass 10, count 0 2006.257.13:40:36.11#ibcon#wrote, iclass 10, count 0 2006.257.13:40:36.11#ibcon#about to read 3, iclass 10, count 0 2006.257.13:40:36.13#ibcon#read 3, iclass 10, count 0 2006.257.13:40:36.13#ibcon#about to read 4, iclass 10, count 0 2006.257.13:40:36.13#ibcon#read 4, iclass 10, count 0 2006.257.13:40:36.13#ibcon#about to read 5, iclass 10, count 0 2006.257.13:40:36.13#ibcon#read 5, iclass 10, count 0 2006.257.13:40:36.13#ibcon#about to read 6, iclass 10, count 0 2006.257.13:40:36.13#ibcon#read 6, iclass 10, count 0 2006.257.13:40:36.13#ibcon#end of sib2, iclass 10, count 0 2006.257.13:40:36.13#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:40:36.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:40:36.13#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:40:36.13#ibcon#*before write, iclass 10, count 0 2006.257.13:40:36.13#ibcon#enter sib2, iclass 10, count 0 2006.257.13:40:36.13#ibcon#flushed, iclass 10, count 0 2006.257.13:40:36.13#ibcon#about to write, iclass 10, count 0 2006.257.13:40:36.13#ibcon#wrote, iclass 10, count 0 2006.257.13:40:36.13#ibcon#about to read 3, iclass 10, count 0 2006.257.13:40:36.18#ibcon#read 3, iclass 10, count 0 2006.257.13:40:36.18#ibcon#about to read 4, iclass 10, count 0 2006.257.13:40:36.18#ibcon#read 4, iclass 10, count 0 2006.257.13:40:36.18#ibcon#about to read 5, iclass 10, count 0 2006.257.13:40:36.18#ibcon#read 5, iclass 10, count 0 2006.257.13:40:36.18#ibcon#about to read 6, iclass 10, count 0 2006.257.13:40:36.18#ibcon#read 6, iclass 10, count 0 2006.257.13:40:36.18#ibcon#end of sib2, iclass 10, count 0 2006.257.13:40:36.18#ibcon#*after write, iclass 10, count 0 2006.257.13:40:36.18#ibcon#*before return 0, iclass 10, count 0 2006.257.13:40:36.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:36.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:36.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:40:36.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:40:36.18$vck44/va=1,8 2006.257.13:40:36.18#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.13:40:36.18#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.13:40:36.18#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:36.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:36.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:36.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:36.18#ibcon#enter wrdev, iclass 12, count 2 2006.257.13:40:36.18#ibcon#first serial, iclass 12, count 2 2006.257.13:40:36.18#ibcon#enter sib2, iclass 12, count 2 2006.257.13:40:36.18#ibcon#flushed, iclass 12, count 2 2006.257.13:40:36.18#ibcon#about to write, iclass 12, count 2 2006.257.13:40:36.18#ibcon#wrote, iclass 12, count 2 2006.257.13:40:36.18#ibcon#about to read 3, iclass 12, count 2 2006.257.13:40:36.20#ibcon#read 3, iclass 12, count 2 2006.257.13:40:36.20#ibcon#about to read 4, iclass 12, count 2 2006.257.13:40:36.20#ibcon#read 4, iclass 12, count 2 2006.257.13:40:36.20#ibcon#about to read 5, iclass 12, count 2 2006.257.13:40:36.20#ibcon#read 5, iclass 12, count 2 2006.257.13:40:36.20#ibcon#about to read 6, iclass 12, count 2 2006.257.13:40:36.20#ibcon#read 6, iclass 12, count 2 2006.257.13:40:36.20#ibcon#end of sib2, iclass 12, count 2 2006.257.13:40:36.20#ibcon#*mode == 0, iclass 12, count 2 2006.257.13:40:36.20#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.13:40:36.20#ibcon#[25=AT01-08\r\n] 2006.257.13:40:36.20#ibcon#*before write, iclass 12, count 2 2006.257.13:40:36.20#ibcon#enter sib2, iclass 12, count 2 2006.257.13:40:36.20#ibcon#flushed, iclass 12, count 2 2006.257.13:40:36.20#ibcon#about to write, iclass 12, count 2 2006.257.13:40:36.20#ibcon#wrote, iclass 12, count 2 2006.257.13:40:36.20#ibcon#about to read 3, iclass 12, count 2 2006.257.13:40:36.23#ibcon#read 3, iclass 12, count 2 2006.257.13:40:36.23#ibcon#about to read 4, iclass 12, count 2 2006.257.13:40:36.23#ibcon#read 4, iclass 12, count 2 2006.257.13:40:36.23#ibcon#about to read 5, iclass 12, count 2 2006.257.13:40:36.23#ibcon#read 5, iclass 12, count 2 2006.257.13:40:36.23#ibcon#about to read 6, iclass 12, count 2 2006.257.13:40:36.23#ibcon#read 6, iclass 12, count 2 2006.257.13:40:36.23#ibcon#end of sib2, iclass 12, count 2 2006.257.13:40:36.23#ibcon#*after write, iclass 12, count 2 2006.257.13:40:36.23#ibcon#*before return 0, iclass 12, count 2 2006.257.13:40:36.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:36.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:36.23#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.13:40:36.23#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:36.23#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:36.35#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:36.35#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:36.35#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:40:36.35#ibcon#first serial, iclass 12, count 0 2006.257.13:40:36.35#ibcon#enter sib2, iclass 12, count 0 2006.257.13:40:36.35#ibcon#flushed, iclass 12, count 0 2006.257.13:40:36.35#ibcon#about to write, iclass 12, count 0 2006.257.13:40:36.35#ibcon#wrote, iclass 12, count 0 2006.257.13:40:36.35#ibcon#about to read 3, iclass 12, count 0 2006.257.13:40:36.37#ibcon#read 3, iclass 12, count 0 2006.257.13:40:36.37#ibcon#about to read 4, iclass 12, count 0 2006.257.13:40:36.37#ibcon#read 4, iclass 12, count 0 2006.257.13:40:36.37#ibcon#about to read 5, iclass 12, count 0 2006.257.13:40:36.37#ibcon#read 5, iclass 12, count 0 2006.257.13:40:36.37#ibcon#about to read 6, iclass 12, count 0 2006.257.13:40:36.37#ibcon#read 6, iclass 12, count 0 2006.257.13:40:36.37#ibcon#end of sib2, iclass 12, count 0 2006.257.13:40:36.37#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:40:36.37#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:40:36.37#ibcon#[25=USB\r\n] 2006.257.13:40:36.37#ibcon#*before write, iclass 12, count 0 2006.257.13:40:36.37#ibcon#enter sib2, iclass 12, count 0 2006.257.13:40:36.37#ibcon#flushed, iclass 12, count 0 2006.257.13:40:36.37#ibcon#about to write, iclass 12, count 0 2006.257.13:40:36.37#ibcon#wrote, iclass 12, count 0 2006.257.13:40:36.37#ibcon#about to read 3, iclass 12, count 0 2006.257.13:40:36.40#ibcon#read 3, iclass 12, count 0 2006.257.13:40:36.40#ibcon#about to read 4, iclass 12, count 0 2006.257.13:40:36.40#ibcon#read 4, iclass 12, count 0 2006.257.13:40:36.40#ibcon#about to read 5, iclass 12, count 0 2006.257.13:40:36.40#ibcon#read 5, iclass 12, count 0 2006.257.13:40:36.40#ibcon#about to read 6, iclass 12, count 0 2006.257.13:40:36.40#ibcon#read 6, iclass 12, count 0 2006.257.13:40:36.40#ibcon#end of sib2, iclass 12, count 0 2006.257.13:40:36.40#ibcon#*after write, iclass 12, count 0 2006.257.13:40:36.40#ibcon#*before return 0, iclass 12, count 0 2006.257.13:40:36.40#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:36.40#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:36.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:40:36.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:40:36.40$vck44/valo=2,534.99 2006.257.13:40:36.40#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.13:40:36.40#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.13:40:36.40#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:36.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:36.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:36.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:36.40#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:40:36.40#ibcon#first serial, iclass 14, count 0 2006.257.13:40:36.40#ibcon#enter sib2, iclass 14, count 0 2006.257.13:40:36.40#ibcon#flushed, iclass 14, count 0 2006.257.13:40:36.40#ibcon#about to write, iclass 14, count 0 2006.257.13:40:36.40#ibcon#wrote, iclass 14, count 0 2006.257.13:40:36.40#ibcon#about to read 3, iclass 14, count 0 2006.257.13:40:36.42#ibcon#read 3, iclass 14, count 0 2006.257.13:40:36.42#ibcon#about to read 4, iclass 14, count 0 2006.257.13:40:36.42#ibcon#read 4, iclass 14, count 0 2006.257.13:40:36.42#ibcon#about to read 5, iclass 14, count 0 2006.257.13:40:36.42#ibcon#read 5, iclass 14, count 0 2006.257.13:40:36.42#ibcon#about to read 6, iclass 14, count 0 2006.257.13:40:36.42#ibcon#read 6, iclass 14, count 0 2006.257.13:40:36.42#ibcon#end of sib2, iclass 14, count 0 2006.257.13:40:36.42#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:40:36.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:40:36.42#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:40:36.42#ibcon#*before write, iclass 14, count 0 2006.257.13:40:36.42#ibcon#enter sib2, iclass 14, count 0 2006.257.13:40:36.42#ibcon#flushed, iclass 14, count 0 2006.257.13:40:36.42#ibcon#about to write, iclass 14, count 0 2006.257.13:40:36.42#ibcon#wrote, iclass 14, count 0 2006.257.13:40:36.42#ibcon#about to read 3, iclass 14, count 0 2006.257.13:40:36.46#ibcon#read 3, iclass 14, count 0 2006.257.13:40:36.46#ibcon#about to read 4, iclass 14, count 0 2006.257.13:40:36.46#ibcon#read 4, iclass 14, count 0 2006.257.13:40:36.46#ibcon#about to read 5, iclass 14, count 0 2006.257.13:40:36.46#ibcon#read 5, iclass 14, count 0 2006.257.13:40:36.46#ibcon#about to read 6, iclass 14, count 0 2006.257.13:40:36.46#ibcon#read 6, iclass 14, count 0 2006.257.13:40:36.46#ibcon#end of sib2, iclass 14, count 0 2006.257.13:40:36.46#ibcon#*after write, iclass 14, count 0 2006.257.13:40:36.46#ibcon#*before return 0, iclass 14, count 0 2006.257.13:40:36.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:36.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:36.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:40:36.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:40:36.46$vck44/va=2,7 2006.257.13:40:36.46#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.13:40:36.46#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.13:40:36.46#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:36.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:36.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:36.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:36.52#ibcon#enter wrdev, iclass 16, count 2 2006.257.13:40:36.52#ibcon#first serial, iclass 16, count 2 2006.257.13:40:36.52#ibcon#enter sib2, iclass 16, count 2 2006.257.13:40:36.52#ibcon#flushed, iclass 16, count 2 2006.257.13:40:36.52#ibcon#about to write, iclass 16, count 2 2006.257.13:40:36.52#ibcon#wrote, iclass 16, count 2 2006.257.13:40:36.52#ibcon#about to read 3, iclass 16, count 2 2006.257.13:40:36.54#ibcon#read 3, iclass 16, count 2 2006.257.13:40:36.54#ibcon#about to read 4, iclass 16, count 2 2006.257.13:40:36.54#ibcon#read 4, iclass 16, count 2 2006.257.13:40:36.54#ibcon#about to read 5, iclass 16, count 2 2006.257.13:40:36.54#ibcon#read 5, iclass 16, count 2 2006.257.13:40:36.54#ibcon#about to read 6, iclass 16, count 2 2006.257.13:40:36.54#ibcon#read 6, iclass 16, count 2 2006.257.13:40:36.54#ibcon#end of sib2, iclass 16, count 2 2006.257.13:40:36.54#ibcon#*mode == 0, iclass 16, count 2 2006.257.13:40:36.54#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.13:40:36.54#ibcon#[25=AT02-07\r\n] 2006.257.13:40:36.54#ibcon#*before write, iclass 16, count 2 2006.257.13:40:36.54#ibcon#enter sib2, iclass 16, count 2 2006.257.13:40:36.54#ibcon#flushed, iclass 16, count 2 2006.257.13:40:36.54#ibcon#about to write, iclass 16, count 2 2006.257.13:40:36.54#ibcon#wrote, iclass 16, count 2 2006.257.13:40:36.54#ibcon#about to read 3, iclass 16, count 2 2006.257.13:40:36.57#ibcon#read 3, iclass 16, count 2 2006.257.13:40:36.57#ibcon#about to read 4, iclass 16, count 2 2006.257.13:40:36.57#ibcon#read 4, iclass 16, count 2 2006.257.13:40:36.57#ibcon#about to read 5, iclass 16, count 2 2006.257.13:40:36.57#ibcon#read 5, iclass 16, count 2 2006.257.13:40:36.57#ibcon#about to read 6, iclass 16, count 2 2006.257.13:40:36.57#ibcon#read 6, iclass 16, count 2 2006.257.13:40:36.57#ibcon#end of sib2, iclass 16, count 2 2006.257.13:40:36.57#ibcon#*after write, iclass 16, count 2 2006.257.13:40:36.57#ibcon#*before return 0, iclass 16, count 2 2006.257.13:40:36.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:36.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:36.57#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.13:40:36.57#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:36.57#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:36.69#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:36.69#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:36.69#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:40:36.69#ibcon#first serial, iclass 16, count 0 2006.257.13:40:36.69#ibcon#enter sib2, iclass 16, count 0 2006.257.13:40:36.69#ibcon#flushed, iclass 16, count 0 2006.257.13:40:36.69#ibcon#about to write, iclass 16, count 0 2006.257.13:40:36.69#ibcon#wrote, iclass 16, count 0 2006.257.13:40:36.69#ibcon#about to read 3, iclass 16, count 0 2006.257.13:40:36.71#ibcon#read 3, iclass 16, count 0 2006.257.13:40:36.71#ibcon#about to read 4, iclass 16, count 0 2006.257.13:40:36.71#ibcon#read 4, iclass 16, count 0 2006.257.13:40:36.71#ibcon#about to read 5, iclass 16, count 0 2006.257.13:40:36.71#ibcon#read 5, iclass 16, count 0 2006.257.13:40:36.71#ibcon#about to read 6, iclass 16, count 0 2006.257.13:40:36.71#ibcon#read 6, iclass 16, count 0 2006.257.13:40:36.71#ibcon#end of sib2, iclass 16, count 0 2006.257.13:40:36.71#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:40:36.71#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:40:36.71#ibcon#[25=USB\r\n] 2006.257.13:40:36.71#ibcon#*before write, iclass 16, count 0 2006.257.13:40:36.71#ibcon#enter sib2, iclass 16, count 0 2006.257.13:40:36.71#ibcon#flushed, iclass 16, count 0 2006.257.13:40:36.71#ibcon#about to write, iclass 16, count 0 2006.257.13:40:36.71#ibcon#wrote, iclass 16, count 0 2006.257.13:40:36.71#ibcon#about to read 3, iclass 16, count 0 2006.257.13:40:36.74#ibcon#read 3, iclass 16, count 0 2006.257.13:40:36.74#ibcon#about to read 4, iclass 16, count 0 2006.257.13:40:36.74#ibcon#read 4, iclass 16, count 0 2006.257.13:40:36.74#ibcon#about to read 5, iclass 16, count 0 2006.257.13:40:36.74#ibcon#read 5, iclass 16, count 0 2006.257.13:40:36.74#ibcon#about to read 6, iclass 16, count 0 2006.257.13:40:36.74#ibcon#read 6, iclass 16, count 0 2006.257.13:40:36.74#ibcon#end of sib2, iclass 16, count 0 2006.257.13:40:36.74#ibcon#*after write, iclass 16, count 0 2006.257.13:40:36.74#ibcon#*before return 0, iclass 16, count 0 2006.257.13:40:36.74#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:36.74#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:36.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:40:36.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:40:36.74$vck44/valo=3,564.99 2006.257.13:40:36.74#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.13:40:36.74#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.13:40:36.74#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:36.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:36.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:36.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:36.74#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:40:36.74#ibcon#first serial, iclass 18, count 0 2006.257.13:40:36.74#ibcon#enter sib2, iclass 18, count 0 2006.257.13:40:36.74#ibcon#flushed, iclass 18, count 0 2006.257.13:40:36.74#ibcon#about to write, iclass 18, count 0 2006.257.13:40:36.74#ibcon#wrote, iclass 18, count 0 2006.257.13:40:36.74#ibcon#about to read 3, iclass 18, count 0 2006.257.13:40:36.76#ibcon#read 3, iclass 18, count 0 2006.257.13:40:36.76#ibcon#about to read 4, iclass 18, count 0 2006.257.13:40:36.76#ibcon#read 4, iclass 18, count 0 2006.257.13:40:36.76#ibcon#about to read 5, iclass 18, count 0 2006.257.13:40:36.76#ibcon#read 5, iclass 18, count 0 2006.257.13:40:36.76#ibcon#about to read 6, iclass 18, count 0 2006.257.13:40:36.76#ibcon#read 6, iclass 18, count 0 2006.257.13:40:36.76#ibcon#end of sib2, iclass 18, count 0 2006.257.13:40:36.76#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:40:36.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:40:36.76#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:40:36.76#ibcon#*before write, iclass 18, count 0 2006.257.13:40:36.76#ibcon#enter sib2, iclass 18, count 0 2006.257.13:40:36.76#ibcon#flushed, iclass 18, count 0 2006.257.13:40:36.76#ibcon#about to write, iclass 18, count 0 2006.257.13:40:36.76#ibcon#wrote, iclass 18, count 0 2006.257.13:40:36.76#ibcon#about to read 3, iclass 18, count 0 2006.257.13:40:36.80#ibcon#read 3, iclass 18, count 0 2006.257.13:40:36.80#ibcon#about to read 4, iclass 18, count 0 2006.257.13:40:36.80#ibcon#read 4, iclass 18, count 0 2006.257.13:40:36.80#ibcon#about to read 5, iclass 18, count 0 2006.257.13:40:36.80#ibcon#read 5, iclass 18, count 0 2006.257.13:40:36.80#ibcon#about to read 6, iclass 18, count 0 2006.257.13:40:36.80#ibcon#read 6, iclass 18, count 0 2006.257.13:40:36.80#ibcon#end of sib2, iclass 18, count 0 2006.257.13:40:36.80#ibcon#*after write, iclass 18, count 0 2006.257.13:40:36.80#ibcon#*before return 0, iclass 18, count 0 2006.257.13:40:36.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:36.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:36.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:40:36.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:40:36.80$vck44/va=3,8 2006.257.13:40:36.80#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.13:40:36.80#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.13:40:36.80#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:36.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:36.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:36.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:36.86#ibcon#enter wrdev, iclass 20, count 2 2006.257.13:40:36.86#ibcon#first serial, iclass 20, count 2 2006.257.13:40:36.86#ibcon#enter sib2, iclass 20, count 2 2006.257.13:40:36.86#ibcon#flushed, iclass 20, count 2 2006.257.13:40:36.86#ibcon#about to write, iclass 20, count 2 2006.257.13:40:36.86#ibcon#wrote, iclass 20, count 2 2006.257.13:40:36.86#ibcon#about to read 3, iclass 20, count 2 2006.257.13:40:36.88#ibcon#read 3, iclass 20, count 2 2006.257.13:40:36.88#ibcon#about to read 4, iclass 20, count 2 2006.257.13:40:36.88#ibcon#read 4, iclass 20, count 2 2006.257.13:40:36.88#ibcon#about to read 5, iclass 20, count 2 2006.257.13:40:36.88#ibcon#read 5, iclass 20, count 2 2006.257.13:40:36.88#ibcon#about to read 6, iclass 20, count 2 2006.257.13:40:36.88#ibcon#read 6, iclass 20, count 2 2006.257.13:40:36.88#ibcon#end of sib2, iclass 20, count 2 2006.257.13:40:36.88#ibcon#*mode == 0, iclass 20, count 2 2006.257.13:40:36.88#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.13:40:36.88#ibcon#[25=AT03-08\r\n] 2006.257.13:40:36.88#ibcon#*before write, iclass 20, count 2 2006.257.13:40:36.88#ibcon#enter sib2, iclass 20, count 2 2006.257.13:40:36.88#ibcon#flushed, iclass 20, count 2 2006.257.13:40:36.88#ibcon#about to write, iclass 20, count 2 2006.257.13:40:36.88#ibcon#wrote, iclass 20, count 2 2006.257.13:40:36.88#ibcon#about to read 3, iclass 20, count 2 2006.257.13:40:36.91#ibcon#read 3, iclass 20, count 2 2006.257.13:40:36.91#ibcon#about to read 4, iclass 20, count 2 2006.257.13:40:36.91#ibcon#read 4, iclass 20, count 2 2006.257.13:40:36.91#ibcon#about to read 5, iclass 20, count 2 2006.257.13:40:36.91#ibcon#read 5, iclass 20, count 2 2006.257.13:40:36.91#ibcon#about to read 6, iclass 20, count 2 2006.257.13:40:36.91#ibcon#read 6, iclass 20, count 2 2006.257.13:40:36.91#ibcon#end of sib2, iclass 20, count 2 2006.257.13:40:36.91#ibcon#*after write, iclass 20, count 2 2006.257.13:40:36.91#ibcon#*before return 0, iclass 20, count 2 2006.257.13:40:36.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:36.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:36.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.13:40:36.91#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:36.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:37.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:37.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:37.03#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:40:37.03#ibcon#first serial, iclass 20, count 0 2006.257.13:40:37.03#ibcon#enter sib2, iclass 20, count 0 2006.257.13:40:37.03#ibcon#flushed, iclass 20, count 0 2006.257.13:40:37.03#ibcon#about to write, iclass 20, count 0 2006.257.13:40:37.03#ibcon#wrote, iclass 20, count 0 2006.257.13:40:37.03#ibcon#about to read 3, iclass 20, count 0 2006.257.13:40:37.05#ibcon#read 3, iclass 20, count 0 2006.257.13:40:37.05#ibcon#about to read 4, iclass 20, count 0 2006.257.13:40:37.05#ibcon#read 4, iclass 20, count 0 2006.257.13:40:37.05#ibcon#about to read 5, iclass 20, count 0 2006.257.13:40:37.05#ibcon#read 5, iclass 20, count 0 2006.257.13:40:37.05#ibcon#about to read 6, iclass 20, count 0 2006.257.13:40:37.05#ibcon#read 6, iclass 20, count 0 2006.257.13:40:37.05#ibcon#end of sib2, iclass 20, count 0 2006.257.13:40:37.05#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:40:37.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:40:37.05#ibcon#[25=USB\r\n] 2006.257.13:40:37.05#ibcon#*before write, iclass 20, count 0 2006.257.13:40:37.05#ibcon#enter sib2, iclass 20, count 0 2006.257.13:40:37.05#ibcon#flushed, iclass 20, count 0 2006.257.13:40:37.05#ibcon#about to write, iclass 20, count 0 2006.257.13:40:37.05#ibcon#wrote, iclass 20, count 0 2006.257.13:40:37.05#ibcon#about to read 3, iclass 20, count 0 2006.257.13:40:37.08#ibcon#read 3, iclass 20, count 0 2006.257.13:40:37.08#ibcon#about to read 4, iclass 20, count 0 2006.257.13:40:37.08#ibcon#read 4, iclass 20, count 0 2006.257.13:40:37.08#ibcon#about to read 5, iclass 20, count 0 2006.257.13:40:37.08#ibcon#read 5, iclass 20, count 0 2006.257.13:40:37.08#ibcon#about to read 6, iclass 20, count 0 2006.257.13:40:37.08#ibcon#read 6, iclass 20, count 0 2006.257.13:40:37.08#ibcon#end of sib2, iclass 20, count 0 2006.257.13:40:37.08#ibcon#*after write, iclass 20, count 0 2006.257.13:40:37.08#ibcon#*before return 0, iclass 20, count 0 2006.257.13:40:37.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:37.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:37.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:40:37.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:40:37.08$vck44/valo=4,624.99 2006.257.13:40:37.08#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.13:40:37.08#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.13:40:37.08#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:37.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:37.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:37.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:37.08#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:40:37.08#ibcon#first serial, iclass 22, count 0 2006.257.13:40:37.08#ibcon#enter sib2, iclass 22, count 0 2006.257.13:40:37.08#ibcon#flushed, iclass 22, count 0 2006.257.13:40:37.08#ibcon#about to write, iclass 22, count 0 2006.257.13:40:37.08#ibcon#wrote, iclass 22, count 0 2006.257.13:40:37.08#ibcon#about to read 3, iclass 22, count 0 2006.257.13:40:37.10#ibcon#read 3, iclass 22, count 0 2006.257.13:40:37.10#ibcon#about to read 4, iclass 22, count 0 2006.257.13:40:37.10#ibcon#read 4, iclass 22, count 0 2006.257.13:40:37.10#ibcon#about to read 5, iclass 22, count 0 2006.257.13:40:37.10#ibcon#read 5, iclass 22, count 0 2006.257.13:40:37.10#ibcon#about to read 6, iclass 22, count 0 2006.257.13:40:37.10#ibcon#read 6, iclass 22, count 0 2006.257.13:40:37.10#ibcon#end of sib2, iclass 22, count 0 2006.257.13:40:37.10#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:40:37.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:40:37.10#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:40:37.10#ibcon#*before write, iclass 22, count 0 2006.257.13:40:37.10#ibcon#enter sib2, iclass 22, count 0 2006.257.13:40:37.10#ibcon#flushed, iclass 22, count 0 2006.257.13:40:37.10#ibcon#about to write, iclass 22, count 0 2006.257.13:40:37.10#ibcon#wrote, iclass 22, count 0 2006.257.13:40:37.10#ibcon#about to read 3, iclass 22, count 0 2006.257.13:40:37.14#ibcon#read 3, iclass 22, count 0 2006.257.13:40:37.14#ibcon#about to read 4, iclass 22, count 0 2006.257.13:40:37.14#ibcon#read 4, iclass 22, count 0 2006.257.13:40:37.14#ibcon#about to read 5, iclass 22, count 0 2006.257.13:40:37.14#ibcon#read 5, iclass 22, count 0 2006.257.13:40:37.14#ibcon#about to read 6, iclass 22, count 0 2006.257.13:40:37.14#ibcon#read 6, iclass 22, count 0 2006.257.13:40:37.14#ibcon#end of sib2, iclass 22, count 0 2006.257.13:40:37.14#ibcon#*after write, iclass 22, count 0 2006.257.13:40:37.14#ibcon#*before return 0, iclass 22, count 0 2006.257.13:40:37.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:37.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:37.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:40:37.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:40:37.14$vck44/va=4,7 2006.257.13:40:37.14#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.13:40:37.14#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.13:40:37.14#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:37.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:37.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:37.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:37.20#ibcon#enter wrdev, iclass 24, count 2 2006.257.13:40:37.20#ibcon#first serial, iclass 24, count 2 2006.257.13:40:37.20#ibcon#enter sib2, iclass 24, count 2 2006.257.13:40:37.20#ibcon#flushed, iclass 24, count 2 2006.257.13:40:37.20#ibcon#about to write, iclass 24, count 2 2006.257.13:40:37.20#ibcon#wrote, iclass 24, count 2 2006.257.13:40:37.20#ibcon#about to read 3, iclass 24, count 2 2006.257.13:40:37.22#ibcon#read 3, iclass 24, count 2 2006.257.13:40:37.22#ibcon#about to read 4, iclass 24, count 2 2006.257.13:40:37.22#ibcon#read 4, iclass 24, count 2 2006.257.13:40:37.22#ibcon#about to read 5, iclass 24, count 2 2006.257.13:40:37.22#ibcon#read 5, iclass 24, count 2 2006.257.13:40:37.22#ibcon#about to read 6, iclass 24, count 2 2006.257.13:40:37.22#ibcon#read 6, iclass 24, count 2 2006.257.13:40:37.22#ibcon#end of sib2, iclass 24, count 2 2006.257.13:40:37.22#ibcon#*mode == 0, iclass 24, count 2 2006.257.13:40:37.22#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.13:40:37.22#ibcon#[25=AT04-07\r\n] 2006.257.13:40:37.22#ibcon#*before write, iclass 24, count 2 2006.257.13:40:37.22#ibcon#enter sib2, iclass 24, count 2 2006.257.13:40:37.22#ibcon#flushed, iclass 24, count 2 2006.257.13:40:37.22#ibcon#about to write, iclass 24, count 2 2006.257.13:40:37.22#ibcon#wrote, iclass 24, count 2 2006.257.13:40:37.22#ibcon#about to read 3, iclass 24, count 2 2006.257.13:40:37.25#ibcon#read 3, iclass 24, count 2 2006.257.13:40:37.27#ibcon#about to read 4, iclass 24, count 2 2006.257.13:40:37.27#ibcon#read 4, iclass 24, count 2 2006.257.13:40:37.27#ibcon#about to read 5, iclass 24, count 2 2006.257.13:40:37.27#ibcon#read 5, iclass 24, count 2 2006.257.13:40:37.28#ibcon#about to read 6, iclass 24, count 2 2006.257.13:40:37.28#ibcon#read 6, iclass 24, count 2 2006.257.13:40:37.28#ibcon#end of sib2, iclass 24, count 2 2006.257.13:40:37.28#ibcon#*after write, iclass 24, count 2 2006.257.13:40:37.28#ibcon#*before return 0, iclass 24, count 2 2006.257.13:40:37.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:37.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:37.28#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.13:40:37.28#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:37.28#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:37.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:37.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:37.39#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:40:37.39#ibcon#first serial, iclass 24, count 0 2006.257.13:40:37.39#ibcon#enter sib2, iclass 24, count 0 2006.257.13:40:37.39#ibcon#flushed, iclass 24, count 0 2006.257.13:40:37.39#ibcon#about to write, iclass 24, count 0 2006.257.13:40:37.39#ibcon#wrote, iclass 24, count 0 2006.257.13:40:37.39#ibcon#about to read 3, iclass 24, count 0 2006.257.13:40:37.41#ibcon#read 3, iclass 24, count 0 2006.257.13:40:37.41#ibcon#about to read 4, iclass 24, count 0 2006.257.13:40:37.41#ibcon#read 4, iclass 24, count 0 2006.257.13:40:37.41#ibcon#about to read 5, iclass 24, count 0 2006.257.13:40:37.41#ibcon#read 5, iclass 24, count 0 2006.257.13:40:37.41#ibcon#about to read 6, iclass 24, count 0 2006.257.13:40:37.41#ibcon#read 6, iclass 24, count 0 2006.257.13:40:37.41#ibcon#end of sib2, iclass 24, count 0 2006.257.13:40:37.41#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:40:37.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:40:37.41#ibcon#[25=USB\r\n] 2006.257.13:40:37.41#ibcon#*before write, iclass 24, count 0 2006.257.13:40:37.41#ibcon#enter sib2, iclass 24, count 0 2006.257.13:40:37.41#ibcon#flushed, iclass 24, count 0 2006.257.13:40:37.41#ibcon#about to write, iclass 24, count 0 2006.257.13:40:37.41#ibcon#wrote, iclass 24, count 0 2006.257.13:40:37.41#ibcon#about to read 3, iclass 24, count 0 2006.257.13:40:37.44#ibcon#read 3, iclass 24, count 0 2006.257.13:40:37.44#ibcon#about to read 4, iclass 24, count 0 2006.257.13:40:37.44#ibcon#read 4, iclass 24, count 0 2006.257.13:40:37.44#ibcon#about to read 5, iclass 24, count 0 2006.257.13:40:37.44#ibcon#read 5, iclass 24, count 0 2006.257.13:40:37.44#ibcon#about to read 6, iclass 24, count 0 2006.257.13:40:37.44#ibcon#read 6, iclass 24, count 0 2006.257.13:40:37.44#ibcon#end of sib2, iclass 24, count 0 2006.257.13:40:37.44#ibcon#*after write, iclass 24, count 0 2006.257.13:40:37.44#ibcon#*before return 0, iclass 24, count 0 2006.257.13:40:37.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:37.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:37.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:40:37.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:40:37.44$vck44/valo=5,734.99 2006.257.13:40:37.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.13:40:37.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.13:40:37.44#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:37.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:37.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:37.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:37.44#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:40:37.44#ibcon#first serial, iclass 26, count 0 2006.257.13:40:37.44#ibcon#enter sib2, iclass 26, count 0 2006.257.13:40:37.44#ibcon#flushed, iclass 26, count 0 2006.257.13:40:37.44#ibcon#about to write, iclass 26, count 0 2006.257.13:40:37.44#ibcon#wrote, iclass 26, count 0 2006.257.13:40:37.44#ibcon#about to read 3, iclass 26, count 0 2006.257.13:40:37.46#ibcon#read 3, iclass 26, count 0 2006.257.13:40:37.46#ibcon#about to read 4, iclass 26, count 0 2006.257.13:40:37.46#ibcon#read 4, iclass 26, count 0 2006.257.13:40:37.46#ibcon#about to read 5, iclass 26, count 0 2006.257.13:40:37.46#ibcon#read 5, iclass 26, count 0 2006.257.13:40:37.46#ibcon#about to read 6, iclass 26, count 0 2006.257.13:40:37.46#ibcon#read 6, iclass 26, count 0 2006.257.13:40:37.46#ibcon#end of sib2, iclass 26, count 0 2006.257.13:40:37.46#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:40:37.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:40:37.46#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:40:37.46#ibcon#*before write, iclass 26, count 0 2006.257.13:40:37.46#ibcon#enter sib2, iclass 26, count 0 2006.257.13:40:37.46#ibcon#flushed, iclass 26, count 0 2006.257.13:40:37.46#ibcon#about to write, iclass 26, count 0 2006.257.13:40:37.46#ibcon#wrote, iclass 26, count 0 2006.257.13:40:37.46#ibcon#about to read 3, iclass 26, count 0 2006.257.13:40:37.50#ibcon#read 3, iclass 26, count 0 2006.257.13:40:37.50#ibcon#about to read 4, iclass 26, count 0 2006.257.13:40:37.50#ibcon#read 4, iclass 26, count 0 2006.257.13:40:37.50#ibcon#about to read 5, iclass 26, count 0 2006.257.13:40:37.50#ibcon#read 5, iclass 26, count 0 2006.257.13:40:37.50#ibcon#about to read 6, iclass 26, count 0 2006.257.13:40:37.50#ibcon#read 6, iclass 26, count 0 2006.257.13:40:37.50#ibcon#end of sib2, iclass 26, count 0 2006.257.13:40:37.50#ibcon#*after write, iclass 26, count 0 2006.257.13:40:37.50#ibcon#*before return 0, iclass 26, count 0 2006.257.13:40:37.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:37.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:37.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:40:37.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:40:37.50$vck44/va=5,4 2006.257.13:40:37.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.13:40:37.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.13:40:37.50#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:37.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:37.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:37.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:37.56#ibcon#enter wrdev, iclass 28, count 2 2006.257.13:40:37.56#ibcon#first serial, iclass 28, count 2 2006.257.13:40:37.56#ibcon#enter sib2, iclass 28, count 2 2006.257.13:40:37.56#ibcon#flushed, iclass 28, count 2 2006.257.13:40:37.56#ibcon#about to write, iclass 28, count 2 2006.257.13:40:37.56#ibcon#wrote, iclass 28, count 2 2006.257.13:40:37.56#ibcon#about to read 3, iclass 28, count 2 2006.257.13:40:37.58#ibcon#read 3, iclass 28, count 2 2006.257.13:40:37.58#ibcon#about to read 4, iclass 28, count 2 2006.257.13:40:37.58#ibcon#read 4, iclass 28, count 2 2006.257.13:40:37.58#ibcon#about to read 5, iclass 28, count 2 2006.257.13:40:37.58#ibcon#read 5, iclass 28, count 2 2006.257.13:40:37.58#ibcon#about to read 6, iclass 28, count 2 2006.257.13:40:37.58#ibcon#read 6, iclass 28, count 2 2006.257.13:40:37.58#ibcon#end of sib2, iclass 28, count 2 2006.257.13:40:37.58#ibcon#*mode == 0, iclass 28, count 2 2006.257.13:40:37.58#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.13:40:37.58#ibcon#[25=AT05-04\r\n] 2006.257.13:40:37.58#ibcon#*before write, iclass 28, count 2 2006.257.13:40:37.58#ibcon#enter sib2, iclass 28, count 2 2006.257.13:40:37.58#ibcon#flushed, iclass 28, count 2 2006.257.13:40:37.58#ibcon#about to write, iclass 28, count 2 2006.257.13:40:37.58#ibcon#wrote, iclass 28, count 2 2006.257.13:40:37.58#ibcon#about to read 3, iclass 28, count 2 2006.257.13:40:37.61#ibcon#read 3, iclass 28, count 2 2006.257.13:40:37.61#ibcon#about to read 4, iclass 28, count 2 2006.257.13:40:37.61#ibcon#read 4, iclass 28, count 2 2006.257.13:40:37.61#ibcon#about to read 5, iclass 28, count 2 2006.257.13:40:37.61#ibcon#read 5, iclass 28, count 2 2006.257.13:40:37.61#ibcon#about to read 6, iclass 28, count 2 2006.257.13:40:37.61#ibcon#read 6, iclass 28, count 2 2006.257.13:40:37.61#ibcon#end of sib2, iclass 28, count 2 2006.257.13:40:37.61#ibcon#*after write, iclass 28, count 2 2006.257.13:40:37.61#ibcon#*before return 0, iclass 28, count 2 2006.257.13:40:37.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:37.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:37.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.13:40:37.61#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:37.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:37.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:37.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:37.73#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:40:37.73#ibcon#first serial, iclass 28, count 0 2006.257.13:40:37.73#ibcon#enter sib2, iclass 28, count 0 2006.257.13:40:37.73#ibcon#flushed, iclass 28, count 0 2006.257.13:40:37.73#ibcon#about to write, iclass 28, count 0 2006.257.13:40:37.73#ibcon#wrote, iclass 28, count 0 2006.257.13:40:37.73#ibcon#about to read 3, iclass 28, count 0 2006.257.13:40:37.75#ibcon#read 3, iclass 28, count 0 2006.257.13:40:37.75#ibcon#about to read 4, iclass 28, count 0 2006.257.13:40:37.75#ibcon#read 4, iclass 28, count 0 2006.257.13:40:37.75#ibcon#about to read 5, iclass 28, count 0 2006.257.13:40:37.75#ibcon#read 5, iclass 28, count 0 2006.257.13:40:37.75#ibcon#about to read 6, iclass 28, count 0 2006.257.13:40:37.75#ibcon#read 6, iclass 28, count 0 2006.257.13:40:37.75#ibcon#end of sib2, iclass 28, count 0 2006.257.13:40:37.75#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:40:37.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:40:37.75#ibcon#[25=USB\r\n] 2006.257.13:40:37.75#ibcon#*before write, iclass 28, count 0 2006.257.13:40:37.75#ibcon#enter sib2, iclass 28, count 0 2006.257.13:40:37.75#ibcon#flushed, iclass 28, count 0 2006.257.13:40:37.75#ibcon#about to write, iclass 28, count 0 2006.257.13:40:37.75#ibcon#wrote, iclass 28, count 0 2006.257.13:40:37.75#ibcon#about to read 3, iclass 28, count 0 2006.257.13:40:37.78#ibcon#read 3, iclass 28, count 0 2006.257.13:40:37.78#ibcon#about to read 4, iclass 28, count 0 2006.257.13:40:37.78#ibcon#read 4, iclass 28, count 0 2006.257.13:40:37.78#ibcon#about to read 5, iclass 28, count 0 2006.257.13:40:37.78#ibcon#read 5, iclass 28, count 0 2006.257.13:40:37.78#ibcon#about to read 6, iclass 28, count 0 2006.257.13:40:37.78#ibcon#read 6, iclass 28, count 0 2006.257.13:40:37.78#ibcon#end of sib2, iclass 28, count 0 2006.257.13:40:37.78#ibcon#*after write, iclass 28, count 0 2006.257.13:40:37.78#ibcon#*before return 0, iclass 28, count 0 2006.257.13:40:37.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:37.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:37.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:40:37.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:40:37.78$vck44/valo=6,814.99 2006.257.13:40:37.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.13:40:37.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.13:40:37.78#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:37.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:37.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:37.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:37.78#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:40:37.78#ibcon#first serial, iclass 30, count 0 2006.257.13:40:37.78#ibcon#enter sib2, iclass 30, count 0 2006.257.13:40:37.78#ibcon#flushed, iclass 30, count 0 2006.257.13:40:37.78#ibcon#about to write, iclass 30, count 0 2006.257.13:40:37.78#ibcon#wrote, iclass 30, count 0 2006.257.13:40:37.78#ibcon#about to read 3, iclass 30, count 0 2006.257.13:40:37.80#ibcon#read 3, iclass 30, count 0 2006.257.13:40:37.80#ibcon#about to read 4, iclass 30, count 0 2006.257.13:40:37.80#ibcon#read 4, iclass 30, count 0 2006.257.13:40:37.80#ibcon#about to read 5, iclass 30, count 0 2006.257.13:40:37.80#ibcon#read 5, iclass 30, count 0 2006.257.13:40:37.80#ibcon#about to read 6, iclass 30, count 0 2006.257.13:40:37.80#ibcon#read 6, iclass 30, count 0 2006.257.13:40:37.80#ibcon#end of sib2, iclass 30, count 0 2006.257.13:40:37.80#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:40:37.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:40:37.80#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:40:37.80#ibcon#*before write, iclass 30, count 0 2006.257.13:40:37.80#ibcon#enter sib2, iclass 30, count 0 2006.257.13:40:37.80#ibcon#flushed, iclass 30, count 0 2006.257.13:40:37.80#ibcon#about to write, iclass 30, count 0 2006.257.13:40:37.80#ibcon#wrote, iclass 30, count 0 2006.257.13:40:37.80#ibcon#about to read 3, iclass 30, count 0 2006.257.13:40:37.84#ibcon#read 3, iclass 30, count 0 2006.257.13:40:37.84#ibcon#about to read 4, iclass 30, count 0 2006.257.13:40:37.84#ibcon#read 4, iclass 30, count 0 2006.257.13:40:37.84#ibcon#about to read 5, iclass 30, count 0 2006.257.13:40:37.84#ibcon#read 5, iclass 30, count 0 2006.257.13:40:37.84#ibcon#about to read 6, iclass 30, count 0 2006.257.13:40:37.84#ibcon#read 6, iclass 30, count 0 2006.257.13:40:37.84#ibcon#end of sib2, iclass 30, count 0 2006.257.13:40:37.84#ibcon#*after write, iclass 30, count 0 2006.257.13:40:37.84#ibcon#*before return 0, iclass 30, count 0 2006.257.13:40:37.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:37.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:37.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:40:37.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:40:37.84$vck44/va=6,4 2006.257.13:40:37.84#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.13:40:37.84#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.13:40:37.84#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:37.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:37.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:37.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:37.90#ibcon#enter wrdev, iclass 32, count 2 2006.257.13:40:37.90#ibcon#first serial, iclass 32, count 2 2006.257.13:40:37.90#ibcon#enter sib2, iclass 32, count 2 2006.257.13:40:37.90#ibcon#flushed, iclass 32, count 2 2006.257.13:40:37.90#ibcon#about to write, iclass 32, count 2 2006.257.13:40:37.90#ibcon#wrote, iclass 32, count 2 2006.257.13:40:37.90#ibcon#about to read 3, iclass 32, count 2 2006.257.13:40:37.92#ibcon#read 3, iclass 32, count 2 2006.257.13:40:37.92#ibcon#about to read 4, iclass 32, count 2 2006.257.13:40:37.92#ibcon#read 4, iclass 32, count 2 2006.257.13:40:37.92#ibcon#about to read 5, iclass 32, count 2 2006.257.13:40:37.92#ibcon#read 5, iclass 32, count 2 2006.257.13:40:37.92#ibcon#about to read 6, iclass 32, count 2 2006.257.13:40:37.92#ibcon#read 6, iclass 32, count 2 2006.257.13:40:37.92#ibcon#end of sib2, iclass 32, count 2 2006.257.13:40:37.92#ibcon#*mode == 0, iclass 32, count 2 2006.257.13:40:37.92#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.13:40:37.92#ibcon#[25=AT06-04\r\n] 2006.257.13:40:37.92#ibcon#*before write, iclass 32, count 2 2006.257.13:40:37.92#ibcon#enter sib2, iclass 32, count 2 2006.257.13:40:37.92#ibcon#flushed, iclass 32, count 2 2006.257.13:40:37.92#ibcon#about to write, iclass 32, count 2 2006.257.13:40:37.92#ibcon#wrote, iclass 32, count 2 2006.257.13:40:37.92#ibcon#about to read 3, iclass 32, count 2 2006.257.13:40:37.95#ibcon#read 3, iclass 32, count 2 2006.257.13:40:37.95#ibcon#about to read 4, iclass 32, count 2 2006.257.13:40:37.95#ibcon#read 4, iclass 32, count 2 2006.257.13:40:37.95#ibcon#about to read 5, iclass 32, count 2 2006.257.13:40:37.95#ibcon#read 5, iclass 32, count 2 2006.257.13:40:37.95#ibcon#about to read 6, iclass 32, count 2 2006.257.13:40:37.95#ibcon#read 6, iclass 32, count 2 2006.257.13:40:37.95#ibcon#end of sib2, iclass 32, count 2 2006.257.13:40:37.95#ibcon#*after write, iclass 32, count 2 2006.257.13:40:37.95#ibcon#*before return 0, iclass 32, count 2 2006.257.13:40:37.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:37.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:37.95#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.13:40:37.95#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:37.95#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:38.07#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:38.07#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:38.07#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:40:38.07#ibcon#first serial, iclass 32, count 0 2006.257.13:40:38.07#ibcon#enter sib2, iclass 32, count 0 2006.257.13:40:38.07#ibcon#flushed, iclass 32, count 0 2006.257.13:40:38.07#ibcon#about to write, iclass 32, count 0 2006.257.13:40:38.07#ibcon#wrote, iclass 32, count 0 2006.257.13:40:38.07#ibcon#about to read 3, iclass 32, count 0 2006.257.13:40:38.09#ibcon#read 3, iclass 32, count 0 2006.257.13:40:38.09#ibcon#about to read 4, iclass 32, count 0 2006.257.13:40:38.09#ibcon#read 4, iclass 32, count 0 2006.257.13:40:38.09#ibcon#about to read 5, iclass 32, count 0 2006.257.13:40:38.09#ibcon#read 5, iclass 32, count 0 2006.257.13:40:38.09#ibcon#about to read 6, iclass 32, count 0 2006.257.13:40:38.09#ibcon#read 6, iclass 32, count 0 2006.257.13:40:38.09#ibcon#end of sib2, iclass 32, count 0 2006.257.13:40:38.09#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:40:38.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:40:38.09#ibcon#[25=USB\r\n] 2006.257.13:40:38.09#ibcon#*before write, iclass 32, count 0 2006.257.13:40:38.09#ibcon#enter sib2, iclass 32, count 0 2006.257.13:40:38.09#ibcon#flushed, iclass 32, count 0 2006.257.13:40:38.09#ibcon#about to write, iclass 32, count 0 2006.257.13:40:38.09#ibcon#wrote, iclass 32, count 0 2006.257.13:40:38.09#ibcon#about to read 3, iclass 32, count 0 2006.257.13:40:38.12#ibcon#read 3, iclass 32, count 0 2006.257.13:40:38.12#ibcon#about to read 4, iclass 32, count 0 2006.257.13:40:38.12#ibcon#read 4, iclass 32, count 0 2006.257.13:40:38.12#ibcon#about to read 5, iclass 32, count 0 2006.257.13:40:38.12#ibcon#read 5, iclass 32, count 0 2006.257.13:40:38.12#ibcon#about to read 6, iclass 32, count 0 2006.257.13:40:38.12#ibcon#read 6, iclass 32, count 0 2006.257.13:40:38.12#ibcon#end of sib2, iclass 32, count 0 2006.257.13:40:38.12#ibcon#*after write, iclass 32, count 0 2006.257.13:40:38.12#ibcon#*before return 0, iclass 32, count 0 2006.257.13:40:38.12#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:38.12#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:38.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:40:38.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:40:38.12$vck44/valo=7,864.99 2006.257.13:40:38.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.13:40:38.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.13:40:38.12#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:38.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:38.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:38.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:38.12#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:40:38.12#ibcon#first serial, iclass 34, count 0 2006.257.13:40:38.12#ibcon#enter sib2, iclass 34, count 0 2006.257.13:40:38.12#ibcon#flushed, iclass 34, count 0 2006.257.13:40:38.12#ibcon#about to write, iclass 34, count 0 2006.257.13:40:38.12#ibcon#wrote, iclass 34, count 0 2006.257.13:40:38.12#ibcon#about to read 3, iclass 34, count 0 2006.257.13:40:38.14#ibcon#read 3, iclass 34, count 0 2006.257.13:40:38.14#ibcon#about to read 4, iclass 34, count 0 2006.257.13:40:38.14#ibcon#read 4, iclass 34, count 0 2006.257.13:40:38.14#ibcon#about to read 5, iclass 34, count 0 2006.257.13:40:38.14#ibcon#read 5, iclass 34, count 0 2006.257.13:40:38.14#ibcon#about to read 6, iclass 34, count 0 2006.257.13:40:38.14#ibcon#read 6, iclass 34, count 0 2006.257.13:40:38.14#ibcon#end of sib2, iclass 34, count 0 2006.257.13:40:38.14#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:40:38.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:40:38.14#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:40:38.14#ibcon#*before write, iclass 34, count 0 2006.257.13:40:38.14#ibcon#enter sib2, iclass 34, count 0 2006.257.13:40:38.14#ibcon#flushed, iclass 34, count 0 2006.257.13:40:38.14#ibcon#about to write, iclass 34, count 0 2006.257.13:40:38.14#ibcon#wrote, iclass 34, count 0 2006.257.13:40:38.14#ibcon#about to read 3, iclass 34, count 0 2006.257.13:40:38.18#ibcon#read 3, iclass 34, count 0 2006.257.13:40:38.18#ibcon#about to read 4, iclass 34, count 0 2006.257.13:40:38.18#ibcon#read 4, iclass 34, count 0 2006.257.13:40:38.18#ibcon#about to read 5, iclass 34, count 0 2006.257.13:40:38.18#ibcon#read 5, iclass 34, count 0 2006.257.13:40:38.18#ibcon#about to read 6, iclass 34, count 0 2006.257.13:40:38.18#ibcon#read 6, iclass 34, count 0 2006.257.13:40:38.18#ibcon#end of sib2, iclass 34, count 0 2006.257.13:40:38.18#ibcon#*after write, iclass 34, count 0 2006.257.13:40:38.18#ibcon#*before return 0, iclass 34, count 0 2006.257.13:40:38.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:38.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:38.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:40:38.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:40:38.18$vck44/va=7,4 2006.257.13:40:38.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.13:40:38.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.13:40:38.18#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:38.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:38.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:38.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:38.24#ibcon#enter wrdev, iclass 36, count 2 2006.257.13:40:38.24#ibcon#first serial, iclass 36, count 2 2006.257.13:40:38.24#ibcon#enter sib2, iclass 36, count 2 2006.257.13:40:38.24#ibcon#flushed, iclass 36, count 2 2006.257.13:40:38.24#ibcon#about to write, iclass 36, count 2 2006.257.13:40:38.24#ibcon#wrote, iclass 36, count 2 2006.257.13:40:38.24#ibcon#about to read 3, iclass 36, count 2 2006.257.13:40:38.26#ibcon#read 3, iclass 36, count 2 2006.257.13:40:38.26#ibcon#about to read 4, iclass 36, count 2 2006.257.13:40:38.26#ibcon#read 4, iclass 36, count 2 2006.257.13:40:38.26#ibcon#about to read 5, iclass 36, count 2 2006.257.13:40:38.26#ibcon#read 5, iclass 36, count 2 2006.257.13:40:38.26#ibcon#about to read 6, iclass 36, count 2 2006.257.13:40:38.26#ibcon#read 6, iclass 36, count 2 2006.257.13:40:38.26#ibcon#end of sib2, iclass 36, count 2 2006.257.13:40:38.26#ibcon#*mode == 0, iclass 36, count 2 2006.257.13:40:38.26#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.13:40:38.26#ibcon#[25=AT07-04\r\n] 2006.257.13:40:38.26#ibcon#*before write, iclass 36, count 2 2006.257.13:40:38.26#ibcon#enter sib2, iclass 36, count 2 2006.257.13:40:38.26#ibcon#flushed, iclass 36, count 2 2006.257.13:40:38.26#ibcon#about to write, iclass 36, count 2 2006.257.13:40:38.26#ibcon#wrote, iclass 36, count 2 2006.257.13:40:38.26#ibcon#about to read 3, iclass 36, count 2 2006.257.13:40:38.29#ibcon#read 3, iclass 36, count 2 2006.257.13:40:38.29#ibcon#about to read 4, iclass 36, count 2 2006.257.13:40:38.29#ibcon#read 4, iclass 36, count 2 2006.257.13:40:38.29#ibcon#about to read 5, iclass 36, count 2 2006.257.13:40:38.29#ibcon#read 5, iclass 36, count 2 2006.257.13:40:38.29#ibcon#about to read 6, iclass 36, count 2 2006.257.13:40:38.29#ibcon#read 6, iclass 36, count 2 2006.257.13:40:38.29#ibcon#end of sib2, iclass 36, count 2 2006.257.13:40:38.29#ibcon#*after write, iclass 36, count 2 2006.257.13:40:38.29#ibcon#*before return 0, iclass 36, count 2 2006.257.13:40:38.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:38.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:38.29#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.13:40:38.29#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:38.29#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:38.41#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:38.41#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:38.41#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:40:38.41#ibcon#first serial, iclass 36, count 0 2006.257.13:40:38.41#ibcon#enter sib2, iclass 36, count 0 2006.257.13:40:38.41#ibcon#flushed, iclass 36, count 0 2006.257.13:40:38.41#ibcon#about to write, iclass 36, count 0 2006.257.13:40:38.41#ibcon#wrote, iclass 36, count 0 2006.257.13:40:38.41#ibcon#about to read 3, iclass 36, count 0 2006.257.13:40:38.43#ibcon#read 3, iclass 36, count 0 2006.257.13:40:38.43#ibcon#about to read 4, iclass 36, count 0 2006.257.13:40:38.43#ibcon#read 4, iclass 36, count 0 2006.257.13:40:38.43#ibcon#about to read 5, iclass 36, count 0 2006.257.13:40:38.43#ibcon#read 5, iclass 36, count 0 2006.257.13:40:38.43#ibcon#about to read 6, iclass 36, count 0 2006.257.13:40:38.43#ibcon#read 6, iclass 36, count 0 2006.257.13:40:38.43#ibcon#end of sib2, iclass 36, count 0 2006.257.13:40:38.43#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:40:38.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:40:38.43#ibcon#[25=USB\r\n] 2006.257.13:40:38.43#ibcon#*before write, iclass 36, count 0 2006.257.13:40:38.43#ibcon#enter sib2, iclass 36, count 0 2006.257.13:40:38.43#ibcon#flushed, iclass 36, count 0 2006.257.13:40:38.43#ibcon#about to write, iclass 36, count 0 2006.257.13:40:38.43#ibcon#wrote, iclass 36, count 0 2006.257.13:40:38.43#ibcon#about to read 3, iclass 36, count 0 2006.257.13:40:38.46#ibcon#read 3, iclass 36, count 0 2006.257.13:40:38.46#ibcon#about to read 4, iclass 36, count 0 2006.257.13:40:38.46#ibcon#read 4, iclass 36, count 0 2006.257.13:40:38.46#ibcon#about to read 5, iclass 36, count 0 2006.257.13:40:38.46#ibcon#read 5, iclass 36, count 0 2006.257.13:40:38.46#ibcon#about to read 6, iclass 36, count 0 2006.257.13:40:38.46#ibcon#read 6, iclass 36, count 0 2006.257.13:40:38.46#ibcon#end of sib2, iclass 36, count 0 2006.257.13:40:38.46#ibcon#*after write, iclass 36, count 0 2006.257.13:40:38.46#ibcon#*before return 0, iclass 36, count 0 2006.257.13:40:38.46#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:38.46#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:38.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:40:38.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:40:38.46$vck44/valo=8,884.99 2006.257.13:40:38.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.13:40:38.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.13:40:38.46#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:38.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:38.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:38.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:38.46#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:40:38.46#ibcon#first serial, iclass 38, count 0 2006.257.13:40:38.46#ibcon#enter sib2, iclass 38, count 0 2006.257.13:40:38.46#ibcon#flushed, iclass 38, count 0 2006.257.13:40:38.46#ibcon#about to write, iclass 38, count 0 2006.257.13:40:38.46#ibcon#wrote, iclass 38, count 0 2006.257.13:40:38.46#ibcon#about to read 3, iclass 38, count 0 2006.257.13:40:38.48#ibcon#read 3, iclass 38, count 0 2006.257.13:40:38.48#ibcon#about to read 4, iclass 38, count 0 2006.257.13:40:38.48#ibcon#read 4, iclass 38, count 0 2006.257.13:40:38.48#ibcon#about to read 5, iclass 38, count 0 2006.257.13:40:38.48#ibcon#read 5, iclass 38, count 0 2006.257.13:40:38.48#ibcon#about to read 6, iclass 38, count 0 2006.257.13:40:38.48#ibcon#read 6, iclass 38, count 0 2006.257.13:40:38.48#ibcon#end of sib2, iclass 38, count 0 2006.257.13:40:38.48#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:40:38.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:40:38.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:40:38.48#ibcon#*before write, iclass 38, count 0 2006.257.13:40:38.48#ibcon#enter sib2, iclass 38, count 0 2006.257.13:40:38.48#ibcon#flushed, iclass 38, count 0 2006.257.13:40:38.48#ibcon#about to write, iclass 38, count 0 2006.257.13:40:38.48#ibcon#wrote, iclass 38, count 0 2006.257.13:40:38.48#ibcon#about to read 3, iclass 38, count 0 2006.257.13:40:38.52#ibcon#read 3, iclass 38, count 0 2006.257.13:40:38.52#ibcon#about to read 4, iclass 38, count 0 2006.257.13:40:38.52#ibcon#read 4, iclass 38, count 0 2006.257.13:40:38.52#ibcon#about to read 5, iclass 38, count 0 2006.257.13:40:38.52#ibcon#read 5, iclass 38, count 0 2006.257.13:40:38.52#ibcon#about to read 6, iclass 38, count 0 2006.257.13:40:38.52#ibcon#read 6, iclass 38, count 0 2006.257.13:40:38.52#ibcon#end of sib2, iclass 38, count 0 2006.257.13:40:38.52#ibcon#*after write, iclass 38, count 0 2006.257.13:40:38.52#ibcon#*before return 0, iclass 38, count 0 2006.257.13:40:38.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:38.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:38.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:40:38.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:40:38.52$vck44/va=8,4 2006.257.13:40:38.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.13:40:38.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.13:40:38.52#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:38.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:40:38.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:40:38.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:40:38.58#ibcon#enter wrdev, iclass 40, count 2 2006.257.13:40:38.58#ibcon#first serial, iclass 40, count 2 2006.257.13:40:38.58#ibcon#enter sib2, iclass 40, count 2 2006.257.13:40:38.58#ibcon#flushed, iclass 40, count 2 2006.257.13:40:38.58#ibcon#about to write, iclass 40, count 2 2006.257.13:40:38.58#ibcon#wrote, iclass 40, count 2 2006.257.13:40:38.58#ibcon#about to read 3, iclass 40, count 2 2006.257.13:40:38.60#ibcon#read 3, iclass 40, count 2 2006.257.13:40:38.60#ibcon#about to read 4, iclass 40, count 2 2006.257.13:40:38.60#ibcon#read 4, iclass 40, count 2 2006.257.13:40:38.60#ibcon#about to read 5, iclass 40, count 2 2006.257.13:40:38.60#ibcon#read 5, iclass 40, count 2 2006.257.13:40:38.60#ibcon#about to read 6, iclass 40, count 2 2006.257.13:40:38.60#ibcon#read 6, iclass 40, count 2 2006.257.13:40:38.60#ibcon#end of sib2, iclass 40, count 2 2006.257.13:40:38.60#ibcon#*mode == 0, iclass 40, count 2 2006.257.13:40:38.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.13:40:38.60#ibcon#[25=AT08-04\r\n] 2006.257.13:40:38.60#ibcon#*before write, iclass 40, count 2 2006.257.13:40:38.60#ibcon#enter sib2, iclass 40, count 2 2006.257.13:40:38.60#ibcon#flushed, iclass 40, count 2 2006.257.13:40:38.60#ibcon#about to write, iclass 40, count 2 2006.257.13:40:38.60#ibcon#wrote, iclass 40, count 2 2006.257.13:40:38.60#ibcon#about to read 3, iclass 40, count 2 2006.257.13:40:38.63#ibcon#read 3, iclass 40, count 2 2006.257.13:40:38.63#ibcon#about to read 4, iclass 40, count 2 2006.257.13:40:38.63#ibcon#read 4, iclass 40, count 2 2006.257.13:40:38.63#ibcon#about to read 5, iclass 40, count 2 2006.257.13:40:38.63#ibcon#read 5, iclass 40, count 2 2006.257.13:40:38.63#ibcon#about to read 6, iclass 40, count 2 2006.257.13:40:38.63#ibcon#read 6, iclass 40, count 2 2006.257.13:40:38.63#ibcon#end of sib2, iclass 40, count 2 2006.257.13:40:38.63#ibcon#*after write, iclass 40, count 2 2006.257.13:40:38.63#ibcon#*before return 0, iclass 40, count 2 2006.257.13:40:38.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:40:38.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.13:40:38.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.13:40:38.63#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:38.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:40:38.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:40:38.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:40:38.75#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:40:38.75#ibcon#first serial, iclass 40, count 0 2006.257.13:40:38.75#ibcon#enter sib2, iclass 40, count 0 2006.257.13:40:38.75#ibcon#flushed, iclass 40, count 0 2006.257.13:40:38.75#ibcon#about to write, iclass 40, count 0 2006.257.13:40:38.75#ibcon#wrote, iclass 40, count 0 2006.257.13:40:38.75#ibcon#about to read 3, iclass 40, count 0 2006.257.13:40:38.77#ibcon#read 3, iclass 40, count 0 2006.257.13:40:38.77#ibcon#about to read 4, iclass 40, count 0 2006.257.13:40:38.77#ibcon#read 4, iclass 40, count 0 2006.257.13:40:38.77#ibcon#about to read 5, iclass 40, count 0 2006.257.13:40:38.77#ibcon#read 5, iclass 40, count 0 2006.257.13:40:38.77#ibcon#about to read 6, iclass 40, count 0 2006.257.13:40:38.77#ibcon#read 6, iclass 40, count 0 2006.257.13:40:38.77#ibcon#end of sib2, iclass 40, count 0 2006.257.13:40:38.77#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:40:38.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:40:38.77#ibcon#[25=USB\r\n] 2006.257.13:40:38.77#ibcon#*before write, iclass 40, count 0 2006.257.13:40:38.77#ibcon#enter sib2, iclass 40, count 0 2006.257.13:40:38.77#ibcon#flushed, iclass 40, count 0 2006.257.13:40:38.77#ibcon#about to write, iclass 40, count 0 2006.257.13:40:38.77#ibcon#wrote, iclass 40, count 0 2006.257.13:40:38.77#ibcon#about to read 3, iclass 40, count 0 2006.257.13:40:38.80#ibcon#read 3, iclass 40, count 0 2006.257.13:40:38.80#ibcon#about to read 4, iclass 40, count 0 2006.257.13:40:38.80#ibcon#read 4, iclass 40, count 0 2006.257.13:40:38.80#ibcon#about to read 5, iclass 40, count 0 2006.257.13:40:38.80#ibcon#read 5, iclass 40, count 0 2006.257.13:40:38.80#ibcon#about to read 6, iclass 40, count 0 2006.257.13:40:38.80#ibcon#read 6, iclass 40, count 0 2006.257.13:40:38.80#ibcon#end of sib2, iclass 40, count 0 2006.257.13:40:38.80#ibcon#*after write, iclass 40, count 0 2006.257.13:40:38.80#ibcon#*before return 0, iclass 40, count 0 2006.257.13:40:38.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:40:38.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.13:40:38.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:40:38.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:40:38.80$vck44/vblo=1,629.99 2006.257.13:40:38.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.13:40:38.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.13:40:38.80#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:38.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:40:38.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:40:38.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:40:38.80#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:40:38.80#ibcon#first serial, iclass 4, count 0 2006.257.13:40:38.80#ibcon#enter sib2, iclass 4, count 0 2006.257.13:40:38.80#ibcon#flushed, iclass 4, count 0 2006.257.13:40:38.80#ibcon#about to write, iclass 4, count 0 2006.257.13:40:38.80#ibcon#wrote, iclass 4, count 0 2006.257.13:40:38.80#ibcon#about to read 3, iclass 4, count 0 2006.257.13:40:38.82#ibcon#read 3, iclass 4, count 0 2006.257.13:40:38.82#ibcon#about to read 4, iclass 4, count 0 2006.257.13:40:38.82#ibcon#read 4, iclass 4, count 0 2006.257.13:40:38.82#ibcon#about to read 5, iclass 4, count 0 2006.257.13:40:38.82#ibcon#read 5, iclass 4, count 0 2006.257.13:40:38.82#ibcon#about to read 6, iclass 4, count 0 2006.257.13:40:38.82#ibcon#read 6, iclass 4, count 0 2006.257.13:40:38.82#ibcon#end of sib2, iclass 4, count 0 2006.257.13:40:38.82#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:40:38.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:40:38.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:40:38.82#ibcon#*before write, iclass 4, count 0 2006.257.13:40:38.82#ibcon#enter sib2, iclass 4, count 0 2006.257.13:40:38.82#ibcon#flushed, iclass 4, count 0 2006.257.13:40:38.82#ibcon#about to write, iclass 4, count 0 2006.257.13:40:38.82#ibcon#wrote, iclass 4, count 0 2006.257.13:40:38.82#ibcon#about to read 3, iclass 4, count 0 2006.257.13:40:38.86#ibcon#read 3, iclass 4, count 0 2006.257.13:40:38.86#ibcon#about to read 4, iclass 4, count 0 2006.257.13:40:38.86#ibcon#read 4, iclass 4, count 0 2006.257.13:40:38.86#ibcon#about to read 5, iclass 4, count 0 2006.257.13:40:38.86#ibcon#read 5, iclass 4, count 0 2006.257.13:40:38.86#ibcon#about to read 6, iclass 4, count 0 2006.257.13:40:38.86#ibcon#read 6, iclass 4, count 0 2006.257.13:40:38.86#ibcon#end of sib2, iclass 4, count 0 2006.257.13:40:38.86#ibcon#*after write, iclass 4, count 0 2006.257.13:40:38.86#ibcon#*before return 0, iclass 4, count 0 2006.257.13:40:38.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:40:38.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:40:38.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:40:38.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:40:38.86$vck44/vb=1,4 2006.257.13:40:38.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.13:40:38.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.13:40:38.86#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:38.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:40:38.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:40:38.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:40:38.86#ibcon#enter wrdev, iclass 6, count 2 2006.257.13:40:38.86#ibcon#first serial, iclass 6, count 2 2006.257.13:40:38.86#ibcon#enter sib2, iclass 6, count 2 2006.257.13:40:38.86#ibcon#flushed, iclass 6, count 2 2006.257.13:40:38.86#ibcon#about to write, iclass 6, count 2 2006.257.13:40:38.86#ibcon#wrote, iclass 6, count 2 2006.257.13:40:38.86#ibcon#about to read 3, iclass 6, count 2 2006.257.13:40:38.88#ibcon#read 3, iclass 6, count 2 2006.257.13:40:38.88#ibcon#about to read 4, iclass 6, count 2 2006.257.13:40:38.88#ibcon#read 4, iclass 6, count 2 2006.257.13:40:38.88#ibcon#about to read 5, iclass 6, count 2 2006.257.13:40:38.88#ibcon#read 5, iclass 6, count 2 2006.257.13:40:38.88#ibcon#about to read 6, iclass 6, count 2 2006.257.13:40:38.88#ibcon#read 6, iclass 6, count 2 2006.257.13:40:38.88#ibcon#end of sib2, iclass 6, count 2 2006.257.13:40:38.88#ibcon#*mode == 0, iclass 6, count 2 2006.257.13:40:38.88#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.13:40:38.88#ibcon#[27=AT01-04\r\n] 2006.257.13:40:38.88#ibcon#*before write, iclass 6, count 2 2006.257.13:40:38.88#ibcon#enter sib2, iclass 6, count 2 2006.257.13:40:38.88#ibcon#flushed, iclass 6, count 2 2006.257.13:40:38.88#ibcon#about to write, iclass 6, count 2 2006.257.13:40:38.88#ibcon#wrote, iclass 6, count 2 2006.257.13:40:38.88#ibcon#about to read 3, iclass 6, count 2 2006.257.13:40:38.91#ibcon#read 3, iclass 6, count 2 2006.257.13:40:38.91#ibcon#about to read 4, iclass 6, count 2 2006.257.13:40:38.91#ibcon#read 4, iclass 6, count 2 2006.257.13:40:38.91#ibcon#about to read 5, iclass 6, count 2 2006.257.13:40:38.91#ibcon#read 5, iclass 6, count 2 2006.257.13:40:38.91#ibcon#about to read 6, iclass 6, count 2 2006.257.13:40:38.91#ibcon#read 6, iclass 6, count 2 2006.257.13:40:38.91#ibcon#end of sib2, iclass 6, count 2 2006.257.13:40:38.91#ibcon#*after write, iclass 6, count 2 2006.257.13:40:38.91#ibcon#*before return 0, iclass 6, count 2 2006.257.13:40:38.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:40:38.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.13:40:38.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.13:40:38.91#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:38.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:40:39.03#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:40:39.03#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:40:39.03#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:40:39.03#ibcon#first serial, iclass 6, count 0 2006.257.13:40:39.03#ibcon#enter sib2, iclass 6, count 0 2006.257.13:40:39.03#ibcon#flushed, iclass 6, count 0 2006.257.13:40:39.03#ibcon#about to write, iclass 6, count 0 2006.257.13:40:39.03#ibcon#wrote, iclass 6, count 0 2006.257.13:40:39.03#ibcon#about to read 3, iclass 6, count 0 2006.257.13:40:39.05#ibcon#read 3, iclass 6, count 0 2006.257.13:40:39.05#ibcon#about to read 4, iclass 6, count 0 2006.257.13:40:39.05#ibcon#read 4, iclass 6, count 0 2006.257.13:40:39.05#ibcon#about to read 5, iclass 6, count 0 2006.257.13:40:39.05#ibcon#read 5, iclass 6, count 0 2006.257.13:40:39.05#ibcon#about to read 6, iclass 6, count 0 2006.257.13:40:39.05#ibcon#read 6, iclass 6, count 0 2006.257.13:40:39.05#ibcon#end of sib2, iclass 6, count 0 2006.257.13:40:39.05#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:40:39.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:40:39.05#ibcon#[27=USB\r\n] 2006.257.13:40:39.05#ibcon#*before write, iclass 6, count 0 2006.257.13:40:39.05#ibcon#enter sib2, iclass 6, count 0 2006.257.13:40:39.05#ibcon#flushed, iclass 6, count 0 2006.257.13:40:39.05#ibcon#about to write, iclass 6, count 0 2006.257.13:40:39.05#ibcon#wrote, iclass 6, count 0 2006.257.13:40:39.05#ibcon#about to read 3, iclass 6, count 0 2006.257.13:40:39.08#ibcon#read 3, iclass 6, count 0 2006.257.13:40:39.08#ibcon#about to read 4, iclass 6, count 0 2006.257.13:40:39.08#ibcon#read 4, iclass 6, count 0 2006.257.13:40:39.08#ibcon#about to read 5, iclass 6, count 0 2006.257.13:40:39.08#ibcon#read 5, iclass 6, count 0 2006.257.13:40:39.08#ibcon#about to read 6, iclass 6, count 0 2006.257.13:40:39.08#ibcon#read 6, iclass 6, count 0 2006.257.13:40:39.08#ibcon#end of sib2, iclass 6, count 0 2006.257.13:40:39.08#ibcon#*after write, iclass 6, count 0 2006.257.13:40:39.08#ibcon#*before return 0, iclass 6, count 0 2006.257.13:40:39.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:40:39.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.13:40:39.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:40:39.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:40:39.08$vck44/vblo=2,634.99 2006.257.13:40:39.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.13:40:39.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.13:40:39.08#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:39.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:39.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:39.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:39.08#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:40:39.08#ibcon#first serial, iclass 10, count 0 2006.257.13:40:39.08#ibcon#enter sib2, iclass 10, count 0 2006.257.13:40:39.08#ibcon#flushed, iclass 10, count 0 2006.257.13:40:39.08#ibcon#about to write, iclass 10, count 0 2006.257.13:40:39.08#ibcon#wrote, iclass 10, count 0 2006.257.13:40:39.08#ibcon#about to read 3, iclass 10, count 0 2006.257.13:40:39.10#ibcon#read 3, iclass 10, count 0 2006.257.13:40:39.10#ibcon#about to read 4, iclass 10, count 0 2006.257.13:40:39.10#ibcon#read 4, iclass 10, count 0 2006.257.13:40:39.10#ibcon#about to read 5, iclass 10, count 0 2006.257.13:40:39.10#ibcon#read 5, iclass 10, count 0 2006.257.13:40:39.10#ibcon#about to read 6, iclass 10, count 0 2006.257.13:40:39.10#ibcon#read 6, iclass 10, count 0 2006.257.13:40:39.10#ibcon#end of sib2, iclass 10, count 0 2006.257.13:40:39.10#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:40:39.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:40:39.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:40:39.10#ibcon#*before write, iclass 10, count 0 2006.257.13:40:39.10#ibcon#enter sib2, iclass 10, count 0 2006.257.13:40:39.10#ibcon#flushed, iclass 10, count 0 2006.257.13:40:39.10#ibcon#about to write, iclass 10, count 0 2006.257.13:40:39.10#ibcon#wrote, iclass 10, count 0 2006.257.13:40:39.10#ibcon#about to read 3, iclass 10, count 0 2006.257.13:40:39.14#ibcon#read 3, iclass 10, count 0 2006.257.13:40:39.14#ibcon#about to read 4, iclass 10, count 0 2006.257.13:40:39.14#ibcon#read 4, iclass 10, count 0 2006.257.13:40:39.14#ibcon#about to read 5, iclass 10, count 0 2006.257.13:40:39.14#ibcon#read 5, iclass 10, count 0 2006.257.13:40:39.14#ibcon#about to read 6, iclass 10, count 0 2006.257.13:40:39.14#ibcon#read 6, iclass 10, count 0 2006.257.13:40:39.14#ibcon#end of sib2, iclass 10, count 0 2006.257.13:40:39.14#ibcon#*after write, iclass 10, count 0 2006.257.13:40:39.14#ibcon#*before return 0, iclass 10, count 0 2006.257.13:40:39.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:39.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.13:40:39.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:40:39.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:40:39.14$vck44/vb=2,5 2006.257.13:40:39.14#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.13:40:39.14#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.13:40:39.14#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:39.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:39.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:39.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:39.20#ibcon#enter wrdev, iclass 12, count 2 2006.257.13:40:39.20#ibcon#first serial, iclass 12, count 2 2006.257.13:40:39.20#ibcon#enter sib2, iclass 12, count 2 2006.257.13:40:39.20#ibcon#flushed, iclass 12, count 2 2006.257.13:40:39.20#ibcon#about to write, iclass 12, count 2 2006.257.13:40:39.20#ibcon#wrote, iclass 12, count 2 2006.257.13:40:39.20#ibcon#about to read 3, iclass 12, count 2 2006.257.13:40:39.22#ibcon#read 3, iclass 12, count 2 2006.257.13:40:39.22#ibcon#about to read 4, iclass 12, count 2 2006.257.13:40:39.22#ibcon#read 4, iclass 12, count 2 2006.257.13:40:39.22#ibcon#about to read 5, iclass 12, count 2 2006.257.13:40:39.22#ibcon#read 5, iclass 12, count 2 2006.257.13:40:39.22#ibcon#about to read 6, iclass 12, count 2 2006.257.13:40:39.22#ibcon#read 6, iclass 12, count 2 2006.257.13:40:39.22#ibcon#end of sib2, iclass 12, count 2 2006.257.13:40:39.22#ibcon#*mode == 0, iclass 12, count 2 2006.257.13:40:39.22#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.13:40:39.22#ibcon#[27=AT02-05\r\n] 2006.257.13:40:39.22#ibcon#*before write, iclass 12, count 2 2006.257.13:40:39.22#ibcon#enter sib2, iclass 12, count 2 2006.257.13:40:39.22#ibcon#flushed, iclass 12, count 2 2006.257.13:40:39.22#ibcon#about to write, iclass 12, count 2 2006.257.13:40:39.22#ibcon#wrote, iclass 12, count 2 2006.257.13:40:39.22#ibcon#about to read 3, iclass 12, count 2 2006.257.13:40:39.25#ibcon#read 3, iclass 12, count 2 2006.257.13:40:39.25#ibcon#about to read 4, iclass 12, count 2 2006.257.13:40:39.35#ibcon#read 4, iclass 12, count 2 2006.257.13:40:39.35#ibcon#about to read 5, iclass 12, count 2 2006.257.13:40:39.35#ibcon#read 5, iclass 12, count 2 2006.257.13:40:39.35#ibcon#about to read 6, iclass 12, count 2 2006.257.13:40:39.35#ibcon#read 6, iclass 12, count 2 2006.257.13:40:39.35#ibcon#end of sib2, iclass 12, count 2 2006.257.13:40:39.35#ibcon#*after write, iclass 12, count 2 2006.257.13:40:39.35#ibcon#*before return 0, iclass 12, count 2 2006.257.13:40:39.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:39.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.13:40:39.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.13:40:39.35#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:39.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:39.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:39.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:39.47#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:40:39.47#ibcon#first serial, iclass 12, count 0 2006.257.13:40:39.47#ibcon#enter sib2, iclass 12, count 0 2006.257.13:40:39.47#ibcon#flushed, iclass 12, count 0 2006.257.13:40:39.47#ibcon#about to write, iclass 12, count 0 2006.257.13:40:39.47#ibcon#wrote, iclass 12, count 0 2006.257.13:40:39.47#ibcon#about to read 3, iclass 12, count 0 2006.257.13:40:39.49#ibcon#read 3, iclass 12, count 0 2006.257.13:40:39.49#ibcon#about to read 4, iclass 12, count 0 2006.257.13:40:39.49#ibcon#read 4, iclass 12, count 0 2006.257.13:40:39.49#ibcon#about to read 5, iclass 12, count 0 2006.257.13:40:39.49#ibcon#read 5, iclass 12, count 0 2006.257.13:40:39.49#ibcon#about to read 6, iclass 12, count 0 2006.257.13:40:39.49#ibcon#read 6, iclass 12, count 0 2006.257.13:40:39.49#ibcon#end of sib2, iclass 12, count 0 2006.257.13:40:39.49#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:40:39.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:40:39.49#ibcon#[27=USB\r\n] 2006.257.13:40:39.49#ibcon#*before write, iclass 12, count 0 2006.257.13:40:39.49#ibcon#enter sib2, iclass 12, count 0 2006.257.13:40:39.49#ibcon#flushed, iclass 12, count 0 2006.257.13:40:39.49#ibcon#about to write, iclass 12, count 0 2006.257.13:40:39.49#ibcon#wrote, iclass 12, count 0 2006.257.13:40:39.49#ibcon#about to read 3, iclass 12, count 0 2006.257.13:40:39.52#ibcon#read 3, iclass 12, count 0 2006.257.13:40:39.52#ibcon#about to read 4, iclass 12, count 0 2006.257.13:40:39.52#ibcon#read 4, iclass 12, count 0 2006.257.13:40:39.52#ibcon#about to read 5, iclass 12, count 0 2006.257.13:40:39.52#ibcon#read 5, iclass 12, count 0 2006.257.13:40:39.52#ibcon#about to read 6, iclass 12, count 0 2006.257.13:40:39.52#ibcon#read 6, iclass 12, count 0 2006.257.13:40:39.52#ibcon#end of sib2, iclass 12, count 0 2006.257.13:40:39.52#ibcon#*after write, iclass 12, count 0 2006.257.13:40:39.52#ibcon#*before return 0, iclass 12, count 0 2006.257.13:40:39.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:39.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.13:40:39.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:40:39.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:40:39.52$vck44/vblo=3,649.99 2006.257.13:40:39.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.13:40:39.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.13:40:39.52#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:39.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:39.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:39.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:39.52#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:40:39.52#ibcon#first serial, iclass 14, count 0 2006.257.13:40:39.52#ibcon#enter sib2, iclass 14, count 0 2006.257.13:40:39.52#ibcon#flushed, iclass 14, count 0 2006.257.13:40:39.52#ibcon#about to write, iclass 14, count 0 2006.257.13:40:39.52#ibcon#wrote, iclass 14, count 0 2006.257.13:40:39.52#ibcon#about to read 3, iclass 14, count 0 2006.257.13:40:39.54#ibcon#read 3, iclass 14, count 0 2006.257.13:40:39.54#ibcon#about to read 4, iclass 14, count 0 2006.257.13:40:39.54#ibcon#read 4, iclass 14, count 0 2006.257.13:40:39.54#ibcon#about to read 5, iclass 14, count 0 2006.257.13:40:39.54#ibcon#read 5, iclass 14, count 0 2006.257.13:40:39.54#ibcon#about to read 6, iclass 14, count 0 2006.257.13:40:39.54#ibcon#read 6, iclass 14, count 0 2006.257.13:40:39.54#ibcon#end of sib2, iclass 14, count 0 2006.257.13:40:39.54#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:40:39.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:40:39.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:40:39.54#ibcon#*before write, iclass 14, count 0 2006.257.13:40:39.54#ibcon#enter sib2, iclass 14, count 0 2006.257.13:40:39.54#ibcon#flushed, iclass 14, count 0 2006.257.13:40:39.54#ibcon#about to write, iclass 14, count 0 2006.257.13:40:39.54#ibcon#wrote, iclass 14, count 0 2006.257.13:40:39.54#ibcon#about to read 3, iclass 14, count 0 2006.257.13:40:39.58#ibcon#read 3, iclass 14, count 0 2006.257.13:40:39.58#ibcon#about to read 4, iclass 14, count 0 2006.257.13:40:39.58#ibcon#read 4, iclass 14, count 0 2006.257.13:40:39.58#ibcon#about to read 5, iclass 14, count 0 2006.257.13:40:39.58#ibcon#read 5, iclass 14, count 0 2006.257.13:40:39.58#ibcon#about to read 6, iclass 14, count 0 2006.257.13:40:39.58#ibcon#read 6, iclass 14, count 0 2006.257.13:40:39.58#ibcon#end of sib2, iclass 14, count 0 2006.257.13:40:39.58#ibcon#*after write, iclass 14, count 0 2006.257.13:40:39.58#ibcon#*before return 0, iclass 14, count 0 2006.257.13:40:39.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:39.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.13:40:39.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:40:39.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:40:39.58$vck44/vb=3,4 2006.257.13:40:39.58#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.13:40:39.58#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.13:40:39.58#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:39.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:39.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:39.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:39.64#ibcon#enter wrdev, iclass 16, count 2 2006.257.13:40:39.64#ibcon#first serial, iclass 16, count 2 2006.257.13:40:39.64#ibcon#enter sib2, iclass 16, count 2 2006.257.13:40:39.64#ibcon#flushed, iclass 16, count 2 2006.257.13:40:39.64#ibcon#about to write, iclass 16, count 2 2006.257.13:40:39.64#ibcon#wrote, iclass 16, count 2 2006.257.13:40:39.64#ibcon#about to read 3, iclass 16, count 2 2006.257.13:40:39.66#ibcon#read 3, iclass 16, count 2 2006.257.13:40:39.66#ibcon#about to read 4, iclass 16, count 2 2006.257.13:40:39.66#ibcon#read 4, iclass 16, count 2 2006.257.13:40:39.66#ibcon#about to read 5, iclass 16, count 2 2006.257.13:40:39.66#ibcon#read 5, iclass 16, count 2 2006.257.13:40:39.66#ibcon#about to read 6, iclass 16, count 2 2006.257.13:40:39.66#ibcon#read 6, iclass 16, count 2 2006.257.13:40:39.66#ibcon#end of sib2, iclass 16, count 2 2006.257.13:40:39.66#ibcon#*mode == 0, iclass 16, count 2 2006.257.13:40:39.66#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.13:40:39.66#ibcon#[27=AT03-04\r\n] 2006.257.13:40:39.66#ibcon#*before write, iclass 16, count 2 2006.257.13:40:39.66#ibcon#enter sib2, iclass 16, count 2 2006.257.13:40:39.66#ibcon#flushed, iclass 16, count 2 2006.257.13:40:39.66#ibcon#about to write, iclass 16, count 2 2006.257.13:40:39.66#ibcon#wrote, iclass 16, count 2 2006.257.13:40:39.66#ibcon#about to read 3, iclass 16, count 2 2006.257.13:40:39.69#ibcon#read 3, iclass 16, count 2 2006.257.13:40:39.69#ibcon#about to read 4, iclass 16, count 2 2006.257.13:40:39.69#ibcon#read 4, iclass 16, count 2 2006.257.13:40:39.69#ibcon#about to read 5, iclass 16, count 2 2006.257.13:40:39.69#ibcon#read 5, iclass 16, count 2 2006.257.13:40:39.69#ibcon#about to read 6, iclass 16, count 2 2006.257.13:40:39.69#ibcon#read 6, iclass 16, count 2 2006.257.13:40:39.69#ibcon#end of sib2, iclass 16, count 2 2006.257.13:40:39.69#ibcon#*after write, iclass 16, count 2 2006.257.13:40:39.69#ibcon#*before return 0, iclass 16, count 2 2006.257.13:40:39.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:39.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.13:40:39.69#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.13:40:39.69#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:39.69#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:39.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:39.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:39.81#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:40:39.81#ibcon#first serial, iclass 16, count 0 2006.257.13:40:39.81#ibcon#enter sib2, iclass 16, count 0 2006.257.13:40:39.81#ibcon#flushed, iclass 16, count 0 2006.257.13:40:39.81#ibcon#about to write, iclass 16, count 0 2006.257.13:40:39.81#ibcon#wrote, iclass 16, count 0 2006.257.13:40:39.81#ibcon#about to read 3, iclass 16, count 0 2006.257.13:40:39.83#ibcon#read 3, iclass 16, count 0 2006.257.13:40:39.83#ibcon#about to read 4, iclass 16, count 0 2006.257.13:40:39.83#ibcon#read 4, iclass 16, count 0 2006.257.13:40:39.83#ibcon#about to read 5, iclass 16, count 0 2006.257.13:40:39.83#ibcon#read 5, iclass 16, count 0 2006.257.13:40:39.83#ibcon#about to read 6, iclass 16, count 0 2006.257.13:40:39.83#ibcon#read 6, iclass 16, count 0 2006.257.13:40:39.83#ibcon#end of sib2, iclass 16, count 0 2006.257.13:40:39.83#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:40:39.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:40:39.83#ibcon#[27=USB\r\n] 2006.257.13:40:39.83#ibcon#*before write, iclass 16, count 0 2006.257.13:40:39.83#ibcon#enter sib2, iclass 16, count 0 2006.257.13:40:39.83#ibcon#flushed, iclass 16, count 0 2006.257.13:40:39.83#ibcon#about to write, iclass 16, count 0 2006.257.13:40:39.83#ibcon#wrote, iclass 16, count 0 2006.257.13:40:39.83#ibcon#about to read 3, iclass 16, count 0 2006.257.13:40:39.86#ibcon#read 3, iclass 16, count 0 2006.257.13:40:39.86#ibcon#about to read 4, iclass 16, count 0 2006.257.13:40:39.86#ibcon#read 4, iclass 16, count 0 2006.257.13:40:39.86#ibcon#about to read 5, iclass 16, count 0 2006.257.13:40:39.86#ibcon#read 5, iclass 16, count 0 2006.257.13:40:39.86#ibcon#about to read 6, iclass 16, count 0 2006.257.13:40:39.86#ibcon#read 6, iclass 16, count 0 2006.257.13:40:39.86#ibcon#end of sib2, iclass 16, count 0 2006.257.13:40:39.86#ibcon#*after write, iclass 16, count 0 2006.257.13:40:39.86#ibcon#*before return 0, iclass 16, count 0 2006.257.13:40:39.86#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:39.86#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.13:40:39.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:40:39.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:40:39.86$vck44/vblo=4,679.99 2006.257.13:40:39.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.13:40:39.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.13:40:39.86#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:39.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:39.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:39.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:39.86#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:40:39.86#ibcon#first serial, iclass 18, count 0 2006.257.13:40:39.86#ibcon#enter sib2, iclass 18, count 0 2006.257.13:40:39.86#ibcon#flushed, iclass 18, count 0 2006.257.13:40:39.86#ibcon#about to write, iclass 18, count 0 2006.257.13:40:39.86#ibcon#wrote, iclass 18, count 0 2006.257.13:40:39.86#ibcon#about to read 3, iclass 18, count 0 2006.257.13:40:39.88#ibcon#read 3, iclass 18, count 0 2006.257.13:40:39.88#ibcon#about to read 4, iclass 18, count 0 2006.257.13:40:39.88#ibcon#read 4, iclass 18, count 0 2006.257.13:40:39.88#ibcon#about to read 5, iclass 18, count 0 2006.257.13:40:39.88#ibcon#read 5, iclass 18, count 0 2006.257.13:40:39.88#ibcon#about to read 6, iclass 18, count 0 2006.257.13:40:39.88#ibcon#read 6, iclass 18, count 0 2006.257.13:40:39.88#ibcon#end of sib2, iclass 18, count 0 2006.257.13:40:39.88#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:40:39.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:40:39.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:40:39.88#ibcon#*before write, iclass 18, count 0 2006.257.13:40:39.88#ibcon#enter sib2, iclass 18, count 0 2006.257.13:40:39.88#ibcon#flushed, iclass 18, count 0 2006.257.13:40:39.88#ibcon#about to write, iclass 18, count 0 2006.257.13:40:39.88#ibcon#wrote, iclass 18, count 0 2006.257.13:40:39.88#ibcon#about to read 3, iclass 18, count 0 2006.257.13:40:39.92#ibcon#read 3, iclass 18, count 0 2006.257.13:40:39.92#ibcon#about to read 4, iclass 18, count 0 2006.257.13:40:39.92#ibcon#read 4, iclass 18, count 0 2006.257.13:40:39.92#ibcon#about to read 5, iclass 18, count 0 2006.257.13:40:39.92#ibcon#read 5, iclass 18, count 0 2006.257.13:40:39.92#ibcon#about to read 6, iclass 18, count 0 2006.257.13:40:39.92#ibcon#read 6, iclass 18, count 0 2006.257.13:40:39.92#ibcon#end of sib2, iclass 18, count 0 2006.257.13:40:39.92#ibcon#*after write, iclass 18, count 0 2006.257.13:40:39.92#ibcon#*before return 0, iclass 18, count 0 2006.257.13:40:39.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:39.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.13:40:39.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:40:39.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:40:39.92$vck44/vb=4,5 2006.257.13:40:39.92#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.13:40:39.92#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.13:40:39.92#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:39.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:39.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:39.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:39.98#ibcon#enter wrdev, iclass 20, count 2 2006.257.13:40:39.98#ibcon#first serial, iclass 20, count 2 2006.257.13:40:39.98#ibcon#enter sib2, iclass 20, count 2 2006.257.13:40:39.98#ibcon#flushed, iclass 20, count 2 2006.257.13:40:39.98#ibcon#about to write, iclass 20, count 2 2006.257.13:40:39.98#ibcon#wrote, iclass 20, count 2 2006.257.13:40:39.98#ibcon#about to read 3, iclass 20, count 2 2006.257.13:40:40.00#ibcon#read 3, iclass 20, count 2 2006.257.13:40:40.00#ibcon#about to read 4, iclass 20, count 2 2006.257.13:40:40.00#ibcon#read 4, iclass 20, count 2 2006.257.13:40:40.00#ibcon#about to read 5, iclass 20, count 2 2006.257.13:40:40.00#ibcon#read 5, iclass 20, count 2 2006.257.13:40:40.00#ibcon#about to read 6, iclass 20, count 2 2006.257.13:40:40.00#ibcon#read 6, iclass 20, count 2 2006.257.13:40:40.00#ibcon#end of sib2, iclass 20, count 2 2006.257.13:40:40.00#ibcon#*mode == 0, iclass 20, count 2 2006.257.13:40:40.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.13:40:40.00#ibcon#[27=AT04-05\r\n] 2006.257.13:40:40.00#ibcon#*before write, iclass 20, count 2 2006.257.13:40:40.00#ibcon#enter sib2, iclass 20, count 2 2006.257.13:40:40.00#ibcon#flushed, iclass 20, count 2 2006.257.13:40:40.00#ibcon#about to write, iclass 20, count 2 2006.257.13:40:40.00#ibcon#wrote, iclass 20, count 2 2006.257.13:40:40.00#ibcon#about to read 3, iclass 20, count 2 2006.257.13:40:40.03#ibcon#read 3, iclass 20, count 2 2006.257.13:40:40.03#ibcon#about to read 4, iclass 20, count 2 2006.257.13:40:40.03#ibcon#read 4, iclass 20, count 2 2006.257.13:40:40.03#ibcon#about to read 5, iclass 20, count 2 2006.257.13:40:40.03#ibcon#read 5, iclass 20, count 2 2006.257.13:40:40.03#ibcon#about to read 6, iclass 20, count 2 2006.257.13:40:40.03#ibcon#read 6, iclass 20, count 2 2006.257.13:40:40.03#ibcon#end of sib2, iclass 20, count 2 2006.257.13:40:40.03#ibcon#*after write, iclass 20, count 2 2006.257.13:40:40.03#ibcon#*before return 0, iclass 20, count 2 2006.257.13:40:40.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:40.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.13:40:40.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.13:40:40.03#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:40.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:40.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:40.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:40.15#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:40:40.15#ibcon#first serial, iclass 20, count 0 2006.257.13:40:40.15#ibcon#enter sib2, iclass 20, count 0 2006.257.13:40:40.15#ibcon#flushed, iclass 20, count 0 2006.257.13:40:40.15#ibcon#about to write, iclass 20, count 0 2006.257.13:40:40.15#ibcon#wrote, iclass 20, count 0 2006.257.13:40:40.15#ibcon#about to read 3, iclass 20, count 0 2006.257.13:40:40.17#ibcon#read 3, iclass 20, count 0 2006.257.13:40:40.17#ibcon#about to read 4, iclass 20, count 0 2006.257.13:40:40.17#ibcon#read 4, iclass 20, count 0 2006.257.13:40:40.17#ibcon#about to read 5, iclass 20, count 0 2006.257.13:40:40.17#ibcon#read 5, iclass 20, count 0 2006.257.13:40:40.17#ibcon#about to read 6, iclass 20, count 0 2006.257.13:40:40.17#ibcon#read 6, iclass 20, count 0 2006.257.13:40:40.17#ibcon#end of sib2, iclass 20, count 0 2006.257.13:40:40.17#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:40:40.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:40:40.17#ibcon#[27=USB\r\n] 2006.257.13:40:40.17#ibcon#*before write, iclass 20, count 0 2006.257.13:40:40.17#ibcon#enter sib2, iclass 20, count 0 2006.257.13:40:40.17#ibcon#flushed, iclass 20, count 0 2006.257.13:40:40.17#ibcon#about to write, iclass 20, count 0 2006.257.13:40:40.17#ibcon#wrote, iclass 20, count 0 2006.257.13:40:40.17#ibcon#about to read 3, iclass 20, count 0 2006.257.13:40:40.20#ibcon#read 3, iclass 20, count 0 2006.257.13:40:40.20#ibcon#about to read 4, iclass 20, count 0 2006.257.13:40:40.20#ibcon#read 4, iclass 20, count 0 2006.257.13:40:40.20#ibcon#about to read 5, iclass 20, count 0 2006.257.13:40:40.20#ibcon#read 5, iclass 20, count 0 2006.257.13:40:40.20#ibcon#about to read 6, iclass 20, count 0 2006.257.13:40:40.20#ibcon#read 6, iclass 20, count 0 2006.257.13:40:40.20#ibcon#end of sib2, iclass 20, count 0 2006.257.13:40:40.20#ibcon#*after write, iclass 20, count 0 2006.257.13:40:40.20#ibcon#*before return 0, iclass 20, count 0 2006.257.13:40:40.20#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:40.20#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.13:40:40.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:40:40.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:40:40.20$vck44/vblo=5,709.99 2006.257.13:40:40.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.13:40:40.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.13:40:40.20#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:40.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:40.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:40.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:40.20#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:40:40.20#ibcon#first serial, iclass 22, count 0 2006.257.13:40:40.20#ibcon#enter sib2, iclass 22, count 0 2006.257.13:40:40.20#ibcon#flushed, iclass 22, count 0 2006.257.13:40:40.20#ibcon#about to write, iclass 22, count 0 2006.257.13:40:40.20#ibcon#wrote, iclass 22, count 0 2006.257.13:40:40.20#ibcon#about to read 3, iclass 22, count 0 2006.257.13:40:40.22#ibcon#read 3, iclass 22, count 0 2006.257.13:40:40.22#ibcon#about to read 4, iclass 22, count 0 2006.257.13:40:40.22#ibcon#read 4, iclass 22, count 0 2006.257.13:40:40.22#ibcon#about to read 5, iclass 22, count 0 2006.257.13:40:40.22#ibcon#read 5, iclass 22, count 0 2006.257.13:40:40.22#ibcon#about to read 6, iclass 22, count 0 2006.257.13:40:40.22#ibcon#read 6, iclass 22, count 0 2006.257.13:40:40.22#ibcon#end of sib2, iclass 22, count 0 2006.257.13:40:40.22#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:40:40.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:40:40.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:40:40.22#ibcon#*before write, iclass 22, count 0 2006.257.13:40:40.22#ibcon#enter sib2, iclass 22, count 0 2006.257.13:40:40.22#ibcon#flushed, iclass 22, count 0 2006.257.13:40:40.22#ibcon#about to write, iclass 22, count 0 2006.257.13:40:40.22#ibcon#wrote, iclass 22, count 0 2006.257.13:40:40.22#ibcon#about to read 3, iclass 22, count 0 2006.257.13:40:40.26#ibcon#read 3, iclass 22, count 0 2006.257.13:40:40.26#ibcon#about to read 4, iclass 22, count 0 2006.257.13:40:40.26#ibcon#read 4, iclass 22, count 0 2006.257.13:40:40.26#ibcon#about to read 5, iclass 22, count 0 2006.257.13:40:40.26#ibcon#read 5, iclass 22, count 0 2006.257.13:40:40.26#ibcon#about to read 6, iclass 22, count 0 2006.257.13:40:40.26#ibcon#read 6, iclass 22, count 0 2006.257.13:40:40.26#ibcon#end of sib2, iclass 22, count 0 2006.257.13:40:40.26#ibcon#*after write, iclass 22, count 0 2006.257.13:40:40.26#ibcon#*before return 0, iclass 22, count 0 2006.257.13:40:40.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:40.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.13:40:40.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:40:40.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:40:40.26$vck44/vb=5,4 2006.257.13:40:40.26#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.13:40:40.26#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.13:40:40.26#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:40.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:40.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:40.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:40.32#ibcon#enter wrdev, iclass 24, count 2 2006.257.13:40:40.32#ibcon#first serial, iclass 24, count 2 2006.257.13:40:40.32#ibcon#enter sib2, iclass 24, count 2 2006.257.13:40:40.32#ibcon#flushed, iclass 24, count 2 2006.257.13:40:40.32#ibcon#about to write, iclass 24, count 2 2006.257.13:40:40.32#ibcon#wrote, iclass 24, count 2 2006.257.13:40:40.32#ibcon#about to read 3, iclass 24, count 2 2006.257.13:40:40.34#ibcon#read 3, iclass 24, count 2 2006.257.13:40:40.34#ibcon#about to read 4, iclass 24, count 2 2006.257.13:40:40.34#ibcon#read 4, iclass 24, count 2 2006.257.13:40:40.34#ibcon#about to read 5, iclass 24, count 2 2006.257.13:40:40.34#ibcon#read 5, iclass 24, count 2 2006.257.13:40:40.34#ibcon#about to read 6, iclass 24, count 2 2006.257.13:40:40.34#ibcon#read 6, iclass 24, count 2 2006.257.13:40:40.34#ibcon#end of sib2, iclass 24, count 2 2006.257.13:40:40.34#ibcon#*mode == 0, iclass 24, count 2 2006.257.13:40:40.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.13:40:40.34#ibcon#[27=AT05-04\r\n] 2006.257.13:40:40.34#ibcon#*before write, iclass 24, count 2 2006.257.13:40:40.34#ibcon#enter sib2, iclass 24, count 2 2006.257.13:40:40.34#ibcon#flushed, iclass 24, count 2 2006.257.13:40:40.34#ibcon#about to write, iclass 24, count 2 2006.257.13:40:40.34#ibcon#wrote, iclass 24, count 2 2006.257.13:40:40.34#ibcon#about to read 3, iclass 24, count 2 2006.257.13:40:40.37#ibcon#read 3, iclass 24, count 2 2006.257.13:40:40.37#ibcon#about to read 4, iclass 24, count 2 2006.257.13:40:40.37#ibcon#read 4, iclass 24, count 2 2006.257.13:40:40.37#ibcon#about to read 5, iclass 24, count 2 2006.257.13:40:40.37#ibcon#read 5, iclass 24, count 2 2006.257.13:40:40.37#ibcon#about to read 6, iclass 24, count 2 2006.257.13:40:40.37#ibcon#read 6, iclass 24, count 2 2006.257.13:40:40.37#ibcon#end of sib2, iclass 24, count 2 2006.257.13:40:40.37#ibcon#*after write, iclass 24, count 2 2006.257.13:40:40.43#ibcon#*before return 0, iclass 24, count 2 2006.257.13:40:40.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:40.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.13:40:40.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.13:40:40.43#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:40.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:40.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:40.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:40.55#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:40:40.55#ibcon#first serial, iclass 24, count 0 2006.257.13:40:40.55#ibcon#enter sib2, iclass 24, count 0 2006.257.13:40:40.55#ibcon#flushed, iclass 24, count 0 2006.257.13:40:40.55#ibcon#about to write, iclass 24, count 0 2006.257.13:40:40.55#ibcon#wrote, iclass 24, count 0 2006.257.13:40:40.55#ibcon#about to read 3, iclass 24, count 0 2006.257.13:40:40.57#ibcon#read 3, iclass 24, count 0 2006.257.13:40:40.57#ibcon#about to read 4, iclass 24, count 0 2006.257.13:40:40.57#ibcon#read 4, iclass 24, count 0 2006.257.13:40:40.57#ibcon#about to read 5, iclass 24, count 0 2006.257.13:40:40.57#ibcon#read 5, iclass 24, count 0 2006.257.13:40:40.57#ibcon#about to read 6, iclass 24, count 0 2006.257.13:40:40.57#ibcon#read 6, iclass 24, count 0 2006.257.13:40:40.57#ibcon#end of sib2, iclass 24, count 0 2006.257.13:40:40.57#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:40:40.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:40:40.57#ibcon#[27=USB\r\n] 2006.257.13:40:40.57#ibcon#*before write, iclass 24, count 0 2006.257.13:40:40.57#ibcon#enter sib2, iclass 24, count 0 2006.257.13:40:40.57#ibcon#flushed, iclass 24, count 0 2006.257.13:40:40.57#ibcon#about to write, iclass 24, count 0 2006.257.13:40:40.57#ibcon#wrote, iclass 24, count 0 2006.257.13:40:40.57#ibcon#about to read 3, iclass 24, count 0 2006.257.13:40:40.60#ibcon#read 3, iclass 24, count 0 2006.257.13:40:40.60#ibcon#about to read 4, iclass 24, count 0 2006.257.13:40:40.60#ibcon#read 4, iclass 24, count 0 2006.257.13:40:40.60#ibcon#about to read 5, iclass 24, count 0 2006.257.13:40:40.60#ibcon#read 5, iclass 24, count 0 2006.257.13:40:40.60#ibcon#about to read 6, iclass 24, count 0 2006.257.13:40:40.60#ibcon#read 6, iclass 24, count 0 2006.257.13:40:40.60#ibcon#end of sib2, iclass 24, count 0 2006.257.13:40:40.60#ibcon#*after write, iclass 24, count 0 2006.257.13:40:40.60#ibcon#*before return 0, iclass 24, count 0 2006.257.13:40:40.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:40.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.13:40:40.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:40:40.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:40:40.60$vck44/vblo=6,719.99 2006.257.13:40:40.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.13:40:40.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.13:40:40.60#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:40.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:40.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:40.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:40.60#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:40:40.60#ibcon#first serial, iclass 26, count 0 2006.257.13:40:40.60#ibcon#enter sib2, iclass 26, count 0 2006.257.13:40:40.60#ibcon#flushed, iclass 26, count 0 2006.257.13:40:40.60#ibcon#about to write, iclass 26, count 0 2006.257.13:40:40.60#ibcon#wrote, iclass 26, count 0 2006.257.13:40:40.60#ibcon#about to read 3, iclass 26, count 0 2006.257.13:40:40.62#ibcon#read 3, iclass 26, count 0 2006.257.13:40:40.62#ibcon#about to read 4, iclass 26, count 0 2006.257.13:40:40.62#ibcon#read 4, iclass 26, count 0 2006.257.13:40:40.62#ibcon#about to read 5, iclass 26, count 0 2006.257.13:40:40.62#ibcon#read 5, iclass 26, count 0 2006.257.13:40:40.62#ibcon#about to read 6, iclass 26, count 0 2006.257.13:40:40.62#ibcon#read 6, iclass 26, count 0 2006.257.13:40:40.62#ibcon#end of sib2, iclass 26, count 0 2006.257.13:40:40.62#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:40:40.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:40:40.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:40:40.62#ibcon#*before write, iclass 26, count 0 2006.257.13:40:40.62#ibcon#enter sib2, iclass 26, count 0 2006.257.13:40:40.62#ibcon#flushed, iclass 26, count 0 2006.257.13:40:40.62#ibcon#about to write, iclass 26, count 0 2006.257.13:40:40.62#ibcon#wrote, iclass 26, count 0 2006.257.13:40:40.62#ibcon#about to read 3, iclass 26, count 0 2006.257.13:40:40.66#ibcon#read 3, iclass 26, count 0 2006.257.13:40:40.66#ibcon#about to read 4, iclass 26, count 0 2006.257.13:40:40.66#ibcon#read 4, iclass 26, count 0 2006.257.13:40:40.66#ibcon#about to read 5, iclass 26, count 0 2006.257.13:40:40.66#ibcon#read 5, iclass 26, count 0 2006.257.13:40:40.66#ibcon#about to read 6, iclass 26, count 0 2006.257.13:40:40.66#ibcon#read 6, iclass 26, count 0 2006.257.13:40:40.66#ibcon#end of sib2, iclass 26, count 0 2006.257.13:40:40.66#ibcon#*after write, iclass 26, count 0 2006.257.13:40:40.66#ibcon#*before return 0, iclass 26, count 0 2006.257.13:40:40.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:40.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:40:40.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:40:40.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:40:40.66$vck44/vb=6,4 2006.257.13:40:40.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.13:40:40.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.13:40:40.66#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:40.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:40.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:40.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:40.72#ibcon#enter wrdev, iclass 28, count 2 2006.257.13:40:40.72#ibcon#first serial, iclass 28, count 2 2006.257.13:40:40.72#ibcon#enter sib2, iclass 28, count 2 2006.257.13:40:40.72#ibcon#flushed, iclass 28, count 2 2006.257.13:40:40.72#ibcon#about to write, iclass 28, count 2 2006.257.13:40:40.72#ibcon#wrote, iclass 28, count 2 2006.257.13:40:40.72#ibcon#about to read 3, iclass 28, count 2 2006.257.13:40:40.74#ibcon#read 3, iclass 28, count 2 2006.257.13:40:40.74#ibcon#about to read 4, iclass 28, count 2 2006.257.13:40:40.74#ibcon#read 4, iclass 28, count 2 2006.257.13:40:40.74#ibcon#about to read 5, iclass 28, count 2 2006.257.13:40:40.74#ibcon#read 5, iclass 28, count 2 2006.257.13:40:40.74#ibcon#about to read 6, iclass 28, count 2 2006.257.13:40:40.74#ibcon#read 6, iclass 28, count 2 2006.257.13:40:40.74#ibcon#end of sib2, iclass 28, count 2 2006.257.13:40:40.74#ibcon#*mode == 0, iclass 28, count 2 2006.257.13:40:40.74#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.13:40:40.74#ibcon#[27=AT06-04\r\n] 2006.257.13:40:40.74#ibcon#*before write, iclass 28, count 2 2006.257.13:40:40.74#ibcon#enter sib2, iclass 28, count 2 2006.257.13:40:40.74#ibcon#flushed, iclass 28, count 2 2006.257.13:40:40.74#ibcon#about to write, iclass 28, count 2 2006.257.13:40:40.74#ibcon#wrote, iclass 28, count 2 2006.257.13:40:40.74#ibcon#about to read 3, iclass 28, count 2 2006.257.13:40:40.77#ibcon#read 3, iclass 28, count 2 2006.257.13:40:40.77#ibcon#about to read 4, iclass 28, count 2 2006.257.13:40:40.77#ibcon#read 4, iclass 28, count 2 2006.257.13:40:40.77#ibcon#about to read 5, iclass 28, count 2 2006.257.13:40:40.77#ibcon#read 5, iclass 28, count 2 2006.257.13:40:40.77#ibcon#about to read 6, iclass 28, count 2 2006.257.13:40:40.77#ibcon#read 6, iclass 28, count 2 2006.257.13:40:40.77#ibcon#end of sib2, iclass 28, count 2 2006.257.13:40:40.77#ibcon#*after write, iclass 28, count 2 2006.257.13:40:40.77#ibcon#*before return 0, iclass 28, count 2 2006.257.13:40:40.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:40.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:40:40.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.13:40:40.77#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:40.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:40.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:40.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:40.89#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:40:40.89#ibcon#first serial, iclass 28, count 0 2006.257.13:40:40.89#ibcon#enter sib2, iclass 28, count 0 2006.257.13:40:40.89#ibcon#flushed, iclass 28, count 0 2006.257.13:40:40.89#ibcon#about to write, iclass 28, count 0 2006.257.13:40:40.89#ibcon#wrote, iclass 28, count 0 2006.257.13:40:40.89#ibcon#about to read 3, iclass 28, count 0 2006.257.13:40:40.91#ibcon#read 3, iclass 28, count 0 2006.257.13:40:40.91#ibcon#about to read 4, iclass 28, count 0 2006.257.13:40:40.91#ibcon#read 4, iclass 28, count 0 2006.257.13:40:40.91#ibcon#about to read 5, iclass 28, count 0 2006.257.13:40:40.91#ibcon#read 5, iclass 28, count 0 2006.257.13:40:40.91#ibcon#about to read 6, iclass 28, count 0 2006.257.13:40:40.91#ibcon#read 6, iclass 28, count 0 2006.257.13:40:40.91#ibcon#end of sib2, iclass 28, count 0 2006.257.13:40:40.91#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:40:40.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:40:40.91#ibcon#[27=USB\r\n] 2006.257.13:40:40.91#ibcon#*before write, iclass 28, count 0 2006.257.13:40:40.91#ibcon#enter sib2, iclass 28, count 0 2006.257.13:40:40.91#ibcon#flushed, iclass 28, count 0 2006.257.13:40:40.91#ibcon#about to write, iclass 28, count 0 2006.257.13:40:40.91#ibcon#wrote, iclass 28, count 0 2006.257.13:40:40.91#ibcon#about to read 3, iclass 28, count 0 2006.257.13:40:40.94#ibcon#read 3, iclass 28, count 0 2006.257.13:40:40.94#ibcon#about to read 4, iclass 28, count 0 2006.257.13:40:40.94#ibcon#read 4, iclass 28, count 0 2006.257.13:40:40.94#ibcon#about to read 5, iclass 28, count 0 2006.257.13:40:40.94#ibcon#read 5, iclass 28, count 0 2006.257.13:40:40.94#ibcon#about to read 6, iclass 28, count 0 2006.257.13:40:40.94#ibcon#read 6, iclass 28, count 0 2006.257.13:40:40.94#ibcon#end of sib2, iclass 28, count 0 2006.257.13:40:40.94#ibcon#*after write, iclass 28, count 0 2006.257.13:40:40.94#ibcon#*before return 0, iclass 28, count 0 2006.257.13:40:40.94#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:40.94#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:40:40.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:40:40.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:40:40.94$vck44/vblo=7,734.99 2006.257.13:40:40.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.13:40:40.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.13:40:40.94#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:40.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:40.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:40.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:40.94#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:40:40.94#ibcon#first serial, iclass 30, count 0 2006.257.13:40:40.94#ibcon#enter sib2, iclass 30, count 0 2006.257.13:40:40.94#ibcon#flushed, iclass 30, count 0 2006.257.13:40:40.94#ibcon#about to write, iclass 30, count 0 2006.257.13:40:40.94#ibcon#wrote, iclass 30, count 0 2006.257.13:40:40.94#ibcon#about to read 3, iclass 30, count 0 2006.257.13:40:40.96#ibcon#read 3, iclass 30, count 0 2006.257.13:40:40.96#ibcon#about to read 4, iclass 30, count 0 2006.257.13:40:40.96#ibcon#read 4, iclass 30, count 0 2006.257.13:40:40.96#ibcon#about to read 5, iclass 30, count 0 2006.257.13:40:40.96#ibcon#read 5, iclass 30, count 0 2006.257.13:40:40.96#ibcon#about to read 6, iclass 30, count 0 2006.257.13:40:40.96#ibcon#read 6, iclass 30, count 0 2006.257.13:40:40.96#ibcon#end of sib2, iclass 30, count 0 2006.257.13:40:40.96#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:40:40.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:40:40.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:40:40.96#ibcon#*before write, iclass 30, count 0 2006.257.13:40:40.96#ibcon#enter sib2, iclass 30, count 0 2006.257.13:40:40.96#ibcon#flushed, iclass 30, count 0 2006.257.13:40:40.96#ibcon#about to write, iclass 30, count 0 2006.257.13:40:40.96#ibcon#wrote, iclass 30, count 0 2006.257.13:40:40.96#ibcon#about to read 3, iclass 30, count 0 2006.257.13:40:41.00#ibcon#read 3, iclass 30, count 0 2006.257.13:40:41.00#ibcon#about to read 4, iclass 30, count 0 2006.257.13:40:41.00#ibcon#read 4, iclass 30, count 0 2006.257.13:40:41.00#ibcon#about to read 5, iclass 30, count 0 2006.257.13:40:41.00#ibcon#read 5, iclass 30, count 0 2006.257.13:40:41.00#ibcon#about to read 6, iclass 30, count 0 2006.257.13:40:41.00#ibcon#read 6, iclass 30, count 0 2006.257.13:40:41.00#ibcon#end of sib2, iclass 30, count 0 2006.257.13:40:41.00#ibcon#*after write, iclass 30, count 0 2006.257.13:40:41.00#ibcon#*before return 0, iclass 30, count 0 2006.257.13:40:41.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:41.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.13:40:41.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:40:41.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:40:41.00$vck44/vb=7,4 2006.257.13:40:41.00#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.13:40:41.00#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.13:40:41.00#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:41.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:41.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:41.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:41.06#ibcon#enter wrdev, iclass 32, count 2 2006.257.13:40:41.06#ibcon#first serial, iclass 32, count 2 2006.257.13:40:41.06#ibcon#enter sib2, iclass 32, count 2 2006.257.13:40:41.06#ibcon#flushed, iclass 32, count 2 2006.257.13:40:41.06#ibcon#about to write, iclass 32, count 2 2006.257.13:40:41.06#ibcon#wrote, iclass 32, count 2 2006.257.13:40:41.06#ibcon#about to read 3, iclass 32, count 2 2006.257.13:40:41.08#ibcon#read 3, iclass 32, count 2 2006.257.13:40:41.08#ibcon#about to read 4, iclass 32, count 2 2006.257.13:40:41.08#ibcon#read 4, iclass 32, count 2 2006.257.13:40:41.08#ibcon#about to read 5, iclass 32, count 2 2006.257.13:40:41.08#ibcon#read 5, iclass 32, count 2 2006.257.13:40:41.08#ibcon#about to read 6, iclass 32, count 2 2006.257.13:40:41.08#ibcon#read 6, iclass 32, count 2 2006.257.13:40:41.08#ibcon#end of sib2, iclass 32, count 2 2006.257.13:40:41.08#ibcon#*mode == 0, iclass 32, count 2 2006.257.13:40:41.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.13:40:41.08#ibcon#[27=AT07-04\r\n] 2006.257.13:40:41.08#ibcon#*before write, iclass 32, count 2 2006.257.13:40:41.08#ibcon#enter sib2, iclass 32, count 2 2006.257.13:40:41.08#ibcon#flushed, iclass 32, count 2 2006.257.13:40:41.08#ibcon#about to write, iclass 32, count 2 2006.257.13:40:41.08#ibcon#wrote, iclass 32, count 2 2006.257.13:40:41.08#ibcon#about to read 3, iclass 32, count 2 2006.257.13:40:41.11#ibcon#read 3, iclass 32, count 2 2006.257.13:40:41.11#ibcon#about to read 4, iclass 32, count 2 2006.257.13:40:41.11#ibcon#read 4, iclass 32, count 2 2006.257.13:40:41.11#ibcon#about to read 5, iclass 32, count 2 2006.257.13:40:41.11#ibcon#read 5, iclass 32, count 2 2006.257.13:40:41.11#ibcon#about to read 6, iclass 32, count 2 2006.257.13:40:41.11#ibcon#read 6, iclass 32, count 2 2006.257.13:40:41.11#ibcon#end of sib2, iclass 32, count 2 2006.257.13:40:41.11#ibcon#*after write, iclass 32, count 2 2006.257.13:40:41.11#ibcon#*before return 0, iclass 32, count 2 2006.257.13:40:41.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:41.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.13:40:41.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.13:40:41.11#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:41.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:41.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:41.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:41.23#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:40:41.23#ibcon#first serial, iclass 32, count 0 2006.257.13:40:41.23#ibcon#enter sib2, iclass 32, count 0 2006.257.13:40:41.23#ibcon#flushed, iclass 32, count 0 2006.257.13:40:41.23#ibcon#about to write, iclass 32, count 0 2006.257.13:40:41.23#ibcon#wrote, iclass 32, count 0 2006.257.13:40:41.23#ibcon#about to read 3, iclass 32, count 0 2006.257.13:40:41.25#ibcon#read 3, iclass 32, count 0 2006.257.13:40:41.25#ibcon#about to read 4, iclass 32, count 0 2006.257.13:40:41.25#ibcon#read 4, iclass 32, count 0 2006.257.13:40:41.25#ibcon#about to read 5, iclass 32, count 0 2006.257.13:40:41.25#ibcon#read 5, iclass 32, count 0 2006.257.13:40:41.25#ibcon#about to read 6, iclass 32, count 0 2006.257.13:40:41.25#ibcon#read 6, iclass 32, count 0 2006.257.13:40:41.25#ibcon#end of sib2, iclass 32, count 0 2006.257.13:40:41.25#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:40:41.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:40:41.25#ibcon#[27=USB\r\n] 2006.257.13:40:41.25#ibcon#*before write, iclass 32, count 0 2006.257.13:40:41.25#ibcon#enter sib2, iclass 32, count 0 2006.257.13:40:41.25#ibcon#flushed, iclass 32, count 0 2006.257.13:40:41.25#ibcon#about to write, iclass 32, count 0 2006.257.13:40:41.25#ibcon#wrote, iclass 32, count 0 2006.257.13:40:41.25#ibcon#about to read 3, iclass 32, count 0 2006.257.13:40:41.28#ibcon#read 3, iclass 32, count 0 2006.257.13:40:41.28#ibcon#about to read 4, iclass 32, count 0 2006.257.13:40:41.28#ibcon#read 4, iclass 32, count 0 2006.257.13:40:41.28#ibcon#about to read 5, iclass 32, count 0 2006.257.13:40:41.28#ibcon#read 5, iclass 32, count 0 2006.257.13:40:41.28#ibcon#about to read 6, iclass 32, count 0 2006.257.13:40:41.28#ibcon#read 6, iclass 32, count 0 2006.257.13:40:41.28#ibcon#end of sib2, iclass 32, count 0 2006.257.13:40:41.28#ibcon#*after write, iclass 32, count 0 2006.257.13:40:41.28#ibcon#*before return 0, iclass 32, count 0 2006.257.13:40:41.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:41.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.13:40:41.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:40:41.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:40:41.28$vck44/vblo=8,744.99 2006.257.13:40:41.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.13:40:41.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.13:40:41.28#ibcon#ireg 17 cls_cnt 0 2006.257.13:40:41.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:41.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:41.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:41.28#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:40:41.28#ibcon#first serial, iclass 34, count 0 2006.257.13:40:41.28#ibcon#enter sib2, iclass 34, count 0 2006.257.13:40:41.28#ibcon#flushed, iclass 34, count 0 2006.257.13:40:41.28#ibcon#about to write, iclass 34, count 0 2006.257.13:40:41.28#ibcon#wrote, iclass 34, count 0 2006.257.13:40:41.28#ibcon#about to read 3, iclass 34, count 0 2006.257.13:40:41.30#ibcon#read 3, iclass 34, count 0 2006.257.13:40:41.30#ibcon#about to read 4, iclass 34, count 0 2006.257.13:40:41.30#ibcon#read 4, iclass 34, count 0 2006.257.13:40:41.30#ibcon#about to read 5, iclass 34, count 0 2006.257.13:40:41.30#ibcon#read 5, iclass 34, count 0 2006.257.13:40:41.30#ibcon#about to read 6, iclass 34, count 0 2006.257.13:40:41.30#ibcon#read 6, iclass 34, count 0 2006.257.13:40:41.30#ibcon#end of sib2, iclass 34, count 0 2006.257.13:40:41.30#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:40:41.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:40:41.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:40:41.30#ibcon#*before write, iclass 34, count 0 2006.257.13:40:41.30#ibcon#enter sib2, iclass 34, count 0 2006.257.13:40:41.30#ibcon#flushed, iclass 34, count 0 2006.257.13:40:41.30#ibcon#about to write, iclass 34, count 0 2006.257.13:40:41.30#ibcon#wrote, iclass 34, count 0 2006.257.13:40:41.30#ibcon#about to read 3, iclass 34, count 0 2006.257.13:40:41.34#ibcon#read 3, iclass 34, count 0 2006.257.13:40:41.34#ibcon#about to read 4, iclass 34, count 0 2006.257.13:40:41.34#ibcon#read 4, iclass 34, count 0 2006.257.13:40:41.34#ibcon#about to read 5, iclass 34, count 0 2006.257.13:40:41.34#ibcon#read 5, iclass 34, count 0 2006.257.13:40:41.34#ibcon#about to read 6, iclass 34, count 0 2006.257.13:40:41.34#ibcon#read 6, iclass 34, count 0 2006.257.13:40:41.34#ibcon#end of sib2, iclass 34, count 0 2006.257.13:40:41.34#ibcon#*after write, iclass 34, count 0 2006.257.13:40:41.34#ibcon#*before return 0, iclass 34, count 0 2006.257.13:40:41.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:41.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.13:40:41.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:40:41.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:40:41.34$vck44/vb=8,4 2006.257.13:40:41.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.13:40:41.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.13:40:41.34#ibcon#ireg 11 cls_cnt 2 2006.257.13:40:41.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:41.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:41.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:41.40#ibcon#enter wrdev, iclass 36, count 2 2006.257.13:40:41.40#ibcon#first serial, iclass 36, count 2 2006.257.13:40:41.40#ibcon#enter sib2, iclass 36, count 2 2006.257.13:40:41.40#ibcon#flushed, iclass 36, count 2 2006.257.13:40:41.40#ibcon#about to write, iclass 36, count 2 2006.257.13:40:41.40#ibcon#wrote, iclass 36, count 2 2006.257.13:40:41.40#ibcon#about to read 3, iclass 36, count 2 2006.257.13:40:41.42#ibcon#read 3, iclass 36, count 2 2006.257.13:40:41.42#ibcon#about to read 4, iclass 36, count 2 2006.257.13:40:41.42#ibcon#read 4, iclass 36, count 2 2006.257.13:40:41.42#ibcon#about to read 5, iclass 36, count 2 2006.257.13:40:41.42#ibcon#read 5, iclass 36, count 2 2006.257.13:40:41.42#ibcon#about to read 6, iclass 36, count 2 2006.257.13:40:41.42#ibcon#read 6, iclass 36, count 2 2006.257.13:40:41.42#ibcon#end of sib2, iclass 36, count 2 2006.257.13:40:41.42#ibcon#*mode == 0, iclass 36, count 2 2006.257.13:40:41.42#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.13:40:41.42#ibcon#[27=AT08-04\r\n] 2006.257.13:40:41.42#ibcon#*before write, iclass 36, count 2 2006.257.13:40:41.42#ibcon#enter sib2, iclass 36, count 2 2006.257.13:40:41.42#ibcon#flushed, iclass 36, count 2 2006.257.13:40:41.42#ibcon#about to write, iclass 36, count 2 2006.257.13:40:41.42#ibcon#wrote, iclass 36, count 2 2006.257.13:40:41.42#ibcon#about to read 3, iclass 36, count 2 2006.257.13:40:41.45#ibcon#read 3, iclass 36, count 2 2006.257.13:40:41.47#ibcon#about to read 4, iclass 36, count 2 2006.257.13:40:41.47#ibcon#read 4, iclass 36, count 2 2006.257.13:40:41.47#ibcon#about to read 5, iclass 36, count 2 2006.257.13:40:41.47#ibcon#read 5, iclass 36, count 2 2006.257.13:40:41.47#ibcon#about to read 6, iclass 36, count 2 2006.257.13:40:41.47#ibcon#read 6, iclass 36, count 2 2006.257.13:40:41.47#ibcon#end of sib2, iclass 36, count 2 2006.257.13:40:41.47#ibcon#*after write, iclass 36, count 2 2006.257.13:40:41.47#ibcon#*before return 0, iclass 36, count 2 2006.257.13:40:41.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:41.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.13:40:41.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.13:40:41.47#ibcon#ireg 7 cls_cnt 0 2006.257.13:40:41.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:41.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:41.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:41.59#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:40:41.59#ibcon#first serial, iclass 36, count 0 2006.257.13:40:41.59#ibcon#enter sib2, iclass 36, count 0 2006.257.13:40:41.59#ibcon#flushed, iclass 36, count 0 2006.257.13:40:41.59#ibcon#about to write, iclass 36, count 0 2006.257.13:40:41.59#ibcon#wrote, iclass 36, count 0 2006.257.13:40:41.59#ibcon#about to read 3, iclass 36, count 0 2006.257.13:40:41.61#ibcon#read 3, iclass 36, count 0 2006.257.13:40:41.61#ibcon#about to read 4, iclass 36, count 0 2006.257.13:40:41.61#ibcon#read 4, iclass 36, count 0 2006.257.13:40:41.61#ibcon#about to read 5, iclass 36, count 0 2006.257.13:40:41.61#ibcon#read 5, iclass 36, count 0 2006.257.13:40:41.61#ibcon#about to read 6, iclass 36, count 0 2006.257.13:40:41.61#ibcon#read 6, iclass 36, count 0 2006.257.13:40:41.61#ibcon#end of sib2, iclass 36, count 0 2006.257.13:40:41.61#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:40:41.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:40:41.61#ibcon#[27=USB\r\n] 2006.257.13:40:41.61#ibcon#*before write, iclass 36, count 0 2006.257.13:40:41.61#ibcon#enter sib2, iclass 36, count 0 2006.257.13:40:41.61#ibcon#flushed, iclass 36, count 0 2006.257.13:40:41.61#ibcon#about to write, iclass 36, count 0 2006.257.13:40:41.61#ibcon#wrote, iclass 36, count 0 2006.257.13:40:41.61#ibcon#about to read 3, iclass 36, count 0 2006.257.13:40:41.64#ibcon#read 3, iclass 36, count 0 2006.257.13:40:41.64#ibcon#about to read 4, iclass 36, count 0 2006.257.13:40:41.64#ibcon#read 4, iclass 36, count 0 2006.257.13:40:41.64#ibcon#about to read 5, iclass 36, count 0 2006.257.13:40:41.64#ibcon#read 5, iclass 36, count 0 2006.257.13:40:41.64#ibcon#about to read 6, iclass 36, count 0 2006.257.13:40:41.64#ibcon#read 6, iclass 36, count 0 2006.257.13:40:41.64#ibcon#end of sib2, iclass 36, count 0 2006.257.13:40:41.64#ibcon#*after write, iclass 36, count 0 2006.257.13:40:41.64#ibcon#*before return 0, iclass 36, count 0 2006.257.13:40:41.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:41.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.13:40:41.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:40:41.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:40:41.64$vck44/vabw=wide 2006.257.13:40:41.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.13:40:41.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.13:40:41.64#ibcon#ireg 8 cls_cnt 0 2006.257.13:40:41.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:41.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:41.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:41.64#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:40:41.64#ibcon#first serial, iclass 38, count 0 2006.257.13:40:41.64#ibcon#enter sib2, iclass 38, count 0 2006.257.13:40:41.64#ibcon#flushed, iclass 38, count 0 2006.257.13:40:41.64#ibcon#about to write, iclass 38, count 0 2006.257.13:40:41.64#ibcon#wrote, iclass 38, count 0 2006.257.13:40:41.64#ibcon#about to read 3, iclass 38, count 0 2006.257.13:40:41.66#ibcon#read 3, iclass 38, count 0 2006.257.13:40:41.66#ibcon#about to read 4, iclass 38, count 0 2006.257.13:40:41.66#ibcon#read 4, iclass 38, count 0 2006.257.13:40:41.66#ibcon#about to read 5, iclass 38, count 0 2006.257.13:40:41.66#ibcon#read 5, iclass 38, count 0 2006.257.13:40:41.66#ibcon#about to read 6, iclass 38, count 0 2006.257.13:40:41.66#ibcon#read 6, iclass 38, count 0 2006.257.13:40:41.66#ibcon#end of sib2, iclass 38, count 0 2006.257.13:40:41.66#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:40:41.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:40:41.66#ibcon#[25=BW32\r\n] 2006.257.13:40:41.66#ibcon#*before write, iclass 38, count 0 2006.257.13:40:41.66#ibcon#enter sib2, iclass 38, count 0 2006.257.13:40:41.66#ibcon#flushed, iclass 38, count 0 2006.257.13:40:41.66#ibcon#about to write, iclass 38, count 0 2006.257.13:40:41.66#ibcon#wrote, iclass 38, count 0 2006.257.13:40:41.66#ibcon#about to read 3, iclass 38, count 0 2006.257.13:40:41.69#ibcon#read 3, iclass 38, count 0 2006.257.13:40:41.69#ibcon#about to read 4, iclass 38, count 0 2006.257.13:40:41.69#ibcon#read 4, iclass 38, count 0 2006.257.13:40:41.69#ibcon#about to read 5, iclass 38, count 0 2006.257.13:40:41.69#ibcon#read 5, iclass 38, count 0 2006.257.13:40:41.69#ibcon#about to read 6, iclass 38, count 0 2006.257.13:40:41.69#ibcon#read 6, iclass 38, count 0 2006.257.13:40:41.69#ibcon#end of sib2, iclass 38, count 0 2006.257.13:40:41.69#ibcon#*after write, iclass 38, count 0 2006.257.13:40:41.69#ibcon#*before return 0, iclass 38, count 0 2006.257.13:40:41.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:41.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.13:40:41.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:40:41.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:40:41.69$vck44/vbbw=wide 2006.257.13:40:41.69#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.13:40:41.69#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.13:40:41.69#ibcon#ireg 8 cls_cnt 0 2006.257.13:40:41.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:40:41.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:40:41.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:40:41.76#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:40:41.76#ibcon#first serial, iclass 40, count 0 2006.257.13:40:41.76#ibcon#enter sib2, iclass 40, count 0 2006.257.13:40:41.76#ibcon#flushed, iclass 40, count 0 2006.257.13:40:41.76#ibcon#about to write, iclass 40, count 0 2006.257.13:40:41.76#ibcon#wrote, iclass 40, count 0 2006.257.13:40:41.76#ibcon#about to read 3, iclass 40, count 0 2006.257.13:40:41.78#ibcon#read 3, iclass 40, count 0 2006.257.13:40:41.78#ibcon#about to read 4, iclass 40, count 0 2006.257.13:40:41.78#ibcon#read 4, iclass 40, count 0 2006.257.13:40:41.78#ibcon#about to read 5, iclass 40, count 0 2006.257.13:40:41.78#ibcon#read 5, iclass 40, count 0 2006.257.13:40:41.78#ibcon#about to read 6, iclass 40, count 0 2006.257.13:40:41.78#ibcon#read 6, iclass 40, count 0 2006.257.13:40:41.78#ibcon#end of sib2, iclass 40, count 0 2006.257.13:40:41.78#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:40:41.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:40:41.78#ibcon#[27=BW32\r\n] 2006.257.13:40:41.78#ibcon#*before write, iclass 40, count 0 2006.257.13:40:41.78#ibcon#enter sib2, iclass 40, count 0 2006.257.13:40:41.78#ibcon#flushed, iclass 40, count 0 2006.257.13:40:41.78#ibcon#about to write, iclass 40, count 0 2006.257.13:40:41.78#ibcon#wrote, iclass 40, count 0 2006.257.13:40:41.78#ibcon#about to read 3, iclass 40, count 0 2006.257.13:40:41.81#ibcon#read 3, iclass 40, count 0 2006.257.13:40:41.81#ibcon#about to read 4, iclass 40, count 0 2006.257.13:40:41.81#ibcon#read 4, iclass 40, count 0 2006.257.13:40:41.81#ibcon#about to read 5, iclass 40, count 0 2006.257.13:40:41.81#ibcon#read 5, iclass 40, count 0 2006.257.13:40:41.81#ibcon#about to read 6, iclass 40, count 0 2006.257.13:40:41.81#ibcon#read 6, iclass 40, count 0 2006.257.13:40:41.81#ibcon#end of sib2, iclass 40, count 0 2006.257.13:40:41.81#ibcon#*after write, iclass 40, count 0 2006.257.13:40:41.81#ibcon#*before return 0, iclass 40, count 0 2006.257.13:40:41.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:40:41.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:40:41.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:40:41.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:40:41.81$setupk4/ifdk4 2006.257.13:40:41.81$ifdk4/lo= 2006.257.13:40:41.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:40:41.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:40:41.81$ifdk4/patch= 2006.257.13:40:41.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:40:41.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:40:41.81$setupk4/!*+20s 2006.257.13:40:44.04#abcon#<5=/14 1.3 4.1 17.52 971013.9\r\n> 2006.257.13:40:44.06#abcon#{5=INTERFACE CLEAR} 2006.257.13:40:44.12#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:40:54.21#abcon#<5=/14 1.3 4.1 17.52 971013.9\r\n> 2006.257.13:40:54.23#abcon#{5=INTERFACE CLEAR} 2006.257.13:40:54.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:40:56.12$setupk4/"tpicd 2006.257.13:40:56.12$setupk4/echo=off 2006.257.13:40:56.12$setupk4/xlog=off 2006.257.13:40:56.12:!2006.257.13:45:05 2006.257.13:41:03.14#trakl#Source acquired 2006.257.13:41:05.14#flagr#flagr/antenna,acquired 2006.257.13:45:05.00:preob 2006.257.13:45:06.14/onsource/TRACKING 2006.257.13:45:06.14:!2006.257.13:45:15 2006.257.13:45:15.00:"tape 2006.257.13:45:15.00:"st=record 2006.257.13:45:15.00:data_valid=on 2006.257.13:45:15.00:midob 2006.257.13:45:15.14/onsource/TRACKING 2006.257.13:45:15.14/wx/17.54,1013.9,97 2006.257.13:45:15.28/cable/+6.4817E-03 2006.257.13:45:16.37/va/01,08,usb,yes,30,33 2006.257.13:45:16.37/va/02,07,usb,yes,33,33 2006.257.13:45:16.37/va/03,08,usb,yes,29,31 2006.257.13:45:16.37/va/04,07,usb,yes,34,35 2006.257.13:45:16.37/va/05,04,usb,yes,30,31 2006.257.13:45:16.37/va/06,04,usb,yes,34,33 2006.257.13:45:16.37/va/07,04,usb,yes,35,35 2006.257.13:45:16.37/va/08,04,usb,yes,29,35 2006.257.13:45:16.60/valo/01,524.99,yes,locked 2006.257.13:45:16.60/valo/02,534.99,yes,locked 2006.257.13:45:16.60/valo/03,564.99,yes,locked 2006.257.13:45:16.60/valo/04,624.99,yes,locked 2006.257.13:45:16.60/valo/05,734.99,yes,locked 2006.257.13:45:16.60/valo/06,814.99,yes,locked 2006.257.13:45:16.60/valo/07,864.99,yes,locked 2006.257.13:45:16.60/valo/08,884.99,yes,locked 2006.257.13:45:17.69/vb/01,04,usb,yes,30,28 2006.257.13:45:17.69/vb/02,05,usb,yes,28,28 2006.257.13:45:17.69/vb/03,04,usb,yes,29,32 2006.257.13:45:17.69/vb/04,05,usb,yes,29,28 2006.257.13:45:17.69/vb/05,04,usb,yes,26,28 2006.257.13:45:17.69/vb/06,04,usb,yes,30,27 2006.257.13:45:17.69/vb/07,04,usb,yes,30,30 2006.257.13:45:17.69/vb/08,04,usb,yes,28,31 2006.257.13:45:17.93/vblo/01,629.99,yes,locked 2006.257.13:45:17.93/vblo/02,634.99,yes,locked 2006.257.13:45:17.93/vblo/03,649.99,yes,locked 2006.257.13:45:17.93/vblo/04,679.99,yes,locked 2006.257.13:45:17.93/vblo/05,709.99,yes,locked 2006.257.13:45:17.93/vblo/06,719.99,yes,locked 2006.257.13:45:17.93/vblo/07,734.99,yes,locked 2006.257.13:45:17.93/vblo/08,744.99,yes,locked 2006.257.13:45:18.08/vabw/8 2006.257.13:45:18.23/vbbw/8 2006.257.13:45:18.32/xfe/off,on,15.5 2006.257.13:45:18.69/ifatt/23,28,28,28 2006.257.13:45:19.08/fmout-gps/S +4.64E-07 2006.257.13:45:19.12:!2006.257.13:47:55 2006.257.13:47:55.00:data_valid=off 2006.257.13:47:55.00:"et 2006.257.13:47:55.00:!+3s 2006.257.13:47:58.01:"tape 2006.257.13:47:58.01:postob 2006.257.13:47:58.20/cable/+6.4806E-03 2006.257.13:47:58.20/wx/17.55,1014.0,97 2006.257.13:47:59.07/fmout-gps/S +4.62E-07 2006.257.13:47:59.07:scan_name=257-1348,jd0609,40 2006.257.13:47:59.07:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.257.13:48:00.13#flagr#flagr/antenna,new-source 2006.257.13:48:00.13:checkk5 2006.257.13:48:00.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:48:00.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:48:01.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:48:01.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:48:02.15/chk_obsdata//k5ts1/T2571345??a.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.13:48:02.58/chk_obsdata//k5ts2/T2571345??b.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.13:48:02.99/chk_obsdata//k5ts3/T2571345??c.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.13:48:03.38/chk_obsdata//k5ts4/T2571345??d.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.13:48:04.10/k5log//k5ts1_log_newline 2006.257.13:48:04.83/k5log//k5ts2_log_newline 2006.257.13:48:05.55/k5log//k5ts3_log_newline 2006.257.13:48:06.27/k5log//k5ts4_log_newline 2006.257.13:48:06.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:48:06.29:setupk4=1 2006.257.13:48:06.30$setupk4/echo=on 2006.257.13:48:06.30$setupk4/pcalon 2006.257.13:48:06.30$pcalon/"no phase cal control is implemented here 2006.257.13:48:06.30$setupk4/"tpicd=stop 2006.257.13:48:06.30$setupk4/"rec=synch_on 2006.257.13:48:06.30$setupk4/"rec_mode=128 2006.257.13:48:06.30$setupk4/!* 2006.257.13:48:06.30$setupk4/recpk4 2006.257.13:48:06.30$recpk4/recpatch= 2006.257.13:48:06.30$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:48:06.30$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:48:06.30$setupk4/vck44 2006.257.13:48:06.30$vck44/valo=1,524.99 2006.257.13:48:06.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.13:48:06.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.13:48:06.30#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:06.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:06.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:06.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:06.30#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:48:06.30#ibcon#first serial, iclass 3, count 0 2006.257.13:48:06.30#ibcon#enter sib2, iclass 3, count 0 2006.257.13:48:06.30#ibcon#flushed, iclass 3, count 0 2006.257.13:48:06.30#ibcon#about to write, iclass 3, count 0 2006.257.13:48:06.30#ibcon#wrote, iclass 3, count 0 2006.257.13:48:06.30#ibcon#about to read 3, iclass 3, count 0 2006.257.13:48:06.32#ibcon#read 3, iclass 3, count 0 2006.257.13:48:06.32#ibcon#about to read 4, iclass 3, count 0 2006.257.13:48:06.32#ibcon#read 4, iclass 3, count 0 2006.257.13:48:06.32#ibcon#about to read 5, iclass 3, count 0 2006.257.13:48:06.32#ibcon#read 5, iclass 3, count 0 2006.257.13:48:06.32#ibcon#about to read 6, iclass 3, count 0 2006.257.13:48:06.32#ibcon#read 6, iclass 3, count 0 2006.257.13:48:06.32#ibcon#end of sib2, iclass 3, count 0 2006.257.13:48:06.32#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:48:06.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:48:06.32#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:48:06.32#ibcon#*before write, iclass 3, count 0 2006.257.13:48:06.32#ibcon#enter sib2, iclass 3, count 0 2006.257.13:48:06.32#ibcon#flushed, iclass 3, count 0 2006.257.13:48:06.32#ibcon#about to write, iclass 3, count 0 2006.257.13:48:06.32#ibcon#wrote, iclass 3, count 0 2006.257.13:48:06.32#ibcon#about to read 3, iclass 3, count 0 2006.257.13:48:06.37#ibcon#read 3, iclass 3, count 0 2006.257.13:48:06.37#ibcon#about to read 4, iclass 3, count 0 2006.257.13:48:06.37#ibcon#read 4, iclass 3, count 0 2006.257.13:48:06.37#ibcon#about to read 5, iclass 3, count 0 2006.257.13:48:06.37#ibcon#read 5, iclass 3, count 0 2006.257.13:48:06.37#ibcon#about to read 6, iclass 3, count 0 2006.257.13:48:06.37#ibcon#read 6, iclass 3, count 0 2006.257.13:48:06.37#ibcon#end of sib2, iclass 3, count 0 2006.257.13:48:06.37#ibcon#*after write, iclass 3, count 0 2006.257.13:48:06.37#ibcon#*before return 0, iclass 3, count 0 2006.257.13:48:06.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:06.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:06.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:48:06.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:48:06.37$vck44/va=1,8 2006.257.13:48:06.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.13:48:06.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.13:48:06.37#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:06.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:06.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:06.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:06.37#ibcon#enter wrdev, iclass 5, count 2 2006.257.13:48:06.37#ibcon#first serial, iclass 5, count 2 2006.257.13:48:06.37#ibcon#enter sib2, iclass 5, count 2 2006.257.13:48:06.37#ibcon#flushed, iclass 5, count 2 2006.257.13:48:06.37#ibcon#about to write, iclass 5, count 2 2006.257.13:48:06.37#ibcon#wrote, iclass 5, count 2 2006.257.13:48:06.37#ibcon#about to read 3, iclass 5, count 2 2006.257.13:48:06.39#ibcon#read 3, iclass 5, count 2 2006.257.13:48:06.39#ibcon#about to read 4, iclass 5, count 2 2006.257.13:48:06.39#ibcon#read 4, iclass 5, count 2 2006.257.13:48:06.39#ibcon#about to read 5, iclass 5, count 2 2006.257.13:48:06.39#ibcon#read 5, iclass 5, count 2 2006.257.13:48:06.39#ibcon#about to read 6, iclass 5, count 2 2006.257.13:48:06.39#ibcon#read 6, iclass 5, count 2 2006.257.13:48:06.39#ibcon#end of sib2, iclass 5, count 2 2006.257.13:48:06.39#ibcon#*mode == 0, iclass 5, count 2 2006.257.13:48:06.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.13:48:06.39#ibcon#[25=AT01-08\r\n] 2006.257.13:48:06.39#ibcon#*before write, iclass 5, count 2 2006.257.13:48:06.39#ibcon#enter sib2, iclass 5, count 2 2006.257.13:48:06.39#ibcon#flushed, iclass 5, count 2 2006.257.13:48:06.39#ibcon#about to write, iclass 5, count 2 2006.257.13:48:06.39#ibcon#wrote, iclass 5, count 2 2006.257.13:48:06.39#ibcon#about to read 3, iclass 5, count 2 2006.257.13:48:06.42#ibcon#read 3, iclass 5, count 2 2006.257.13:48:06.42#ibcon#about to read 4, iclass 5, count 2 2006.257.13:48:06.42#ibcon#read 4, iclass 5, count 2 2006.257.13:48:06.42#ibcon#about to read 5, iclass 5, count 2 2006.257.13:48:06.42#ibcon#read 5, iclass 5, count 2 2006.257.13:48:06.42#ibcon#about to read 6, iclass 5, count 2 2006.257.13:48:06.42#ibcon#read 6, iclass 5, count 2 2006.257.13:48:06.42#ibcon#end of sib2, iclass 5, count 2 2006.257.13:48:06.42#ibcon#*after write, iclass 5, count 2 2006.257.13:48:06.42#ibcon#*before return 0, iclass 5, count 2 2006.257.13:48:06.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:06.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:06.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.13:48:06.42#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:06.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:06.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:06.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:06.54#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:48:06.54#ibcon#first serial, iclass 5, count 0 2006.257.13:48:06.54#ibcon#enter sib2, iclass 5, count 0 2006.257.13:48:06.54#ibcon#flushed, iclass 5, count 0 2006.257.13:48:06.54#ibcon#about to write, iclass 5, count 0 2006.257.13:48:06.54#ibcon#wrote, iclass 5, count 0 2006.257.13:48:06.54#ibcon#about to read 3, iclass 5, count 0 2006.257.13:48:06.56#ibcon#read 3, iclass 5, count 0 2006.257.13:48:06.56#ibcon#about to read 4, iclass 5, count 0 2006.257.13:48:06.56#ibcon#read 4, iclass 5, count 0 2006.257.13:48:06.56#ibcon#about to read 5, iclass 5, count 0 2006.257.13:48:06.56#ibcon#read 5, iclass 5, count 0 2006.257.13:48:06.56#ibcon#about to read 6, iclass 5, count 0 2006.257.13:48:06.56#ibcon#read 6, iclass 5, count 0 2006.257.13:48:06.56#ibcon#end of sib2, iclass 5, count 0 2006.257.13:48:06.56#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:48:06.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:48:06.56#ibcon#[25=USB\r\n] 2006.257.13:48:06.56#ibcon#*before write, iclass 5, count 0 2006.257.13:48:06.56#ibcon#enter sib2, iclass 5, count 0 2006.257.13:48:06.56#ibcon#flushed, iclass 5, count 0 2006.257.13:48:06.56#ibcon#about to write, iclass 5, count 0 2006.257.13:48:06.56#ibcon#wrote, iclass 5, count 0 2006.257.13:48:06.56#ibcon#about to read 3, iclass 5, count 0 2006.257.13:48:06.59#ibcon#read 3, iclass 5, count 0 2006.257.13:48:06.59#ibcon#about to read 4, iclass 5, count 0 2006.257.13:48:06.59#ibcon#read 4, iclass 5, count 0 2006.257.13:48:06.59#ibcon#about to read 5, iclass 5, count 0 2006.257.13:48:06.59#ibcon#read 5, iclass 5, count 0 2006.257.13:48:06.59#ibcon#about to read 6, iclass 5, count 0 2006.257.13:48:06.59#ibcon#read 6, iclass 5, count 0 2006.257.13:48:06.59#ibcon#end of sib2, iclass 5, count 0 2006.257.13:48:06.59#ibcon#*after write, iclass 5, count 0 2006.257.13:48:06.59#ibcon#*before return 0, iclass 5, count 0 2006.257.13:48:06.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:06.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:06.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:48:06.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:48:06.59$vck44/valo=2,534.99 2006.257.13:48:06.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.13:48:06.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.13:48:06.59#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:06.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:06.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:06.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:06.59#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:48:06.59#ibcon#first serial, iclass 7, count 0 2006.257.13:48:06.59#ibcon#enter sib2, iclass 7, count 0 2006.257.13:48:06.59#ibcon#flushed, iclass 7, count 0 2006.257.13:48:06.59#ibcon#about to write, iclass 7, count 0 2006.257.13:48:06.59#ibcon#wrote, iclass 7, count 0 2006.257.13:48:06.59#ibcon#about to read 3, iclass 7, count 0 2006.257.13:48:06.61#ibcon#read 3, iclass 7, count 0 2006.257.13:48:06.61#ibcon#about to read 4, iclass 7, count 0 2006.257.13:48:06.61#ibcon#read 4, iclass 7, count 0 2006.257.13:48:06.61#ibcon#about to read 5, iclass 7, count 0 2006.257.13:48:06.61#ibcon#read 5, iclass 7, count 0 2006.257.13:48:06.61#ibcon#about to read 6, iclass 7, count 0 2006.257.13:48:06.61#ibcon#read 6, iclass 7, count 0 2006.257.13:48:06.61#ibcon#end of sib2, iclass 7, count 0 2006.257.13:48:06.61#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:48:06.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:48:06.61#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:48:06.61#ibcon#*before write, iclass 7, count 0 2006.257.13:48:06.61#ibcon#enter sib2, iclass 7, count 0 2006.257.13:48:06.61#ibcon#flushed, iclass 7, count 0 2006.257.13:48:06.61#ibcon#about to write, iclass 7, count 0 2006.257.13:48:06.61#ibcon#wrote, iclass 7, count 0 2006.257.13:48:06.61#ibcon#about to read 3, iclass 7, count 0 2006.257.13:48:06.65#ibcon#read 3, iclass 7, count 0 2006.257.13:48:06.65#ibcon#about to read 4, iclass 7, count 0 2006.257.13:48:06.65#ibcon#read 4, iclass 7, count 0 2006.257.13:48:06.65#ibcon#about to read 5, iclass 7, count 0 2006.257.13:48:06.65#ibcon#read 5, iclass 7, count 0 2006.257.13:48:06.65#ibcon#about to read 6, iclass 7, count 0 2006.257.13:48:06.65#ibcon#read 6, iclass 7, count 0 2006.257.13:48:06.65#ibcon#end of sib2, iclass 7, count 0 2006.257.13:48:06.65#ibcon#*after write, iclass 7, count 0 2006.257.13:48:06.65#ibcon#*before return 0, iclass 7, count 0 2006.257.13:48:06.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:06.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:06.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:48:06.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:48:06.65$vck44/va=2,7 2006.257.13:48:06.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.13:48:06.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.13:48:06.65#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:06.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:06.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:06.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:06.71#ibcon#enter wrdev, iclass 11, count 2 2006.257.13:48:06.71#ibcon#first serial, iclass 11, count 2 2006.257.13:48:06.71#ibcon#enter sib2, iclass 11, count 2 2006.257.13:48:06.71#ibcon#flushed, iclass 11, count 2 2006.257.13:48:06.71#ibcon#about to write, iclass 11, count 2 2006.257.13:48:06.71#ibcon#wrote, iclass 11, count 2 2006.257.13:48:06.71#ibcon#about to read 3, iclass 11, count 2 2006.257.13:48:06.73#ibcon#read 3, iclass 11, count 2 2006.257.13:48:06.73#ibcon#about to read 4, iclass 11, count 2 2006.257.13:48:06.73#ibcon#read 4, iclass 11, count 2 2006.257.13:48:06.73#ibcon#about to read 5, iclass 11, count 2 2006.257.13:48:06.73#ibcon#read 5, iclass 11, count 2 2006.257.13:48:06.73#ibcon#about to read 6, iclass 11, count 2 2006.257.13:48:06.73#ibcon#read 6, iclass 11, count 2 2006.257.13:48:06.73#ibcon#end of sib2, iclass 11, count 2 2006.257.13:48:06.73#ibcon#*mode == 0, iclass 11, count 2 2006.257.13:48:06.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.13:48:06.73#ibcon#[25=AT02-07\r\n] 2006.257.13:48:06.73#ibcon#*before write, iclass 11, count 2 2006.257.13:48:06.73#ibcon#enter sib2, iclass 11, count 2 2006.257.13:48:06.73#ibcon#flushed, iclass 11, count 2 2006.257.13:48:06.73#ibcon#about to write, iclass 11, count 2 2006.257.13:48:06.73#ibcon#wrote, iclass 11, count 2 2006.257.13:48:06.73#ibcon#about to read 3, iclass 11, count 2 2006.257.13:48:06.76#ibcon#read 3, iclass 11, count 2 2006.257.13:48:06.76#ibcon#about to read 4, iclass 11, count 2 2006.257.13:48:06.76#ibcon#read 4, iclass 11, count 2 2006.257.13:48:06.76#ibcon#about to read 5, iclass 11, count 2 2006.257.13:48:06.76#ibcon#read 5, iclass 11, count 2 2006.257.13:48:06.76#ibcon#about to read 6, iclass 11, count 2 2006.257.13:48:06.76#ibcon#read 6, iclass 11, count 2 2006.257.13:48:06.76#ibcon#end of sib2, iclass 11, count 2 2006.257.13:48:06.76#ibcon#*after write, iclass 11, count 2 2006.257.13:48:06.76#ibcon#*before return 0, iclass 11, count 2 2006.257.13:48:06.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:06.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:06.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.13:48:06.76#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:06.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:06.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:06.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:06.88#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:48:06.88#ibcon#first serial, iclass 11, count 0 2006.257.13:48:06.88#ibcon#enter sib2, iclass 11, count 0 2006.257.13:48:06.88#ibcon#flushed, iclass 11, count 0 2006.257.13:48:06.88#ibcon#about to write, iclass 11, count 0 2006.257.13:48:06.88#ibcon#wrote, iclass 11, count 0 2006.257.13:48:06.88#ibcon#about to read 3, iclass 11, count 0 2006.257.13:48:06.90#ibcon#read 3, iclass 11, count 0 2006.257.13:48:06.90#ibcon#about to read 4, iclass 11, count 0 2006.257.13:48:06.90#ibcon#read 4, iclass 11, count 0 2006.257.13:48:06.90#ibcon#about to read 5, iclass 11, count 0 2006.257.13:48:06.90#ibcon#read 5, iclass 11, count 0 2006.257.13:48:06.90#ibcon#about to read 6, iclass 11, count 0 2006.257.13:48:06.90#ibcon#read 6, iclass 11, count 0 2006.257.13:48:06.90#ibcon#end of sib2, iclass 11, count 0 2006.257.13:48:06.90#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:48:06.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:48:06.90#ibcon#[25=USB\r\n] 2006.257.13:48:06.90#ibcon#*before write, iclass 11, count 0 2006.257.13:48:06.90#ibcon#enter sib2, iclass 11, count 0 2006.257.13:48:06.90#ibcon#flushed, iclass 11, count 0 2006.257.13:48:06.90#ibcon#about to write, iclass 11, count 0 2006.257.13:48:06.90#ibcon#wrote, iclass 11, count 0 2006.257.13:48:06.90#ibcon#about to read 3, iclass 11, count 0 2006.257.13:48:06.93#ibcon#read 3, iclass 11, count 0 2006.257.13:48:06.93#ibcon#about to read 4, iclass 11, count 0 2006.257.13:48:06.93#ibcon#read 4, iclass 11, count 0 2006.257.13:48:06.93#ibcon#about to read 5, iclass 11, count 0 2006.257.13:48:06.93#ibcon#read 5, iclass 11, count 0 2006.257.13:48:06.93#ibcon#about to read 6, iclass 11, count 0 2006.257.13:48:06.93#ibcon#read 6, iclass 11, count 0 2006.257.13:48:06.93#ibcon#end of sib2, iclass 11, count 0 2006.257.13:48:06.93#ibcon#*after write, iclass 11, count 0 2006.257.13:48:06.93#ibcon#*before return 0, iclass 11, count 0 2006.257.13:48:06.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:06.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:06.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:48:06.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:48:06.93$vck44/valo=3,564.99 2006.257.13:48:06.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:48:06.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:48:06.93#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:06.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:06.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:06.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:06.93#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:48:06.93#ibcon#first serial, iclass 13, count 0 2006.257.13:48:06.93#ibcon#enter sib2, iclass 13, count 0 2006.257.13:48:06.93#ibcon#flushed, iclass 13, count 0 2006.257.13:48:06.93#ibcon#about to write, iclass 13, count 0 2006.257.13:48:06.93#ibcon#wrote, iclass 13, count 0 2006.257.13:48:06.93#ibcon#about to read 3, iclass 13, count 0 2006.257.13:48:06.95#ibcon#read 3, iclass 13, count 0 2006.257.13:48:06.95#ibcon#about to read 4, iclass 13, count 0 2006.257.13:48:06.95#ibcon#read 4, iclass 13, count 0 2006.257.13:48:06.95#ibcon#about to read 5, iclass 13, count 0 2006.257.13:48:06.95#ibcon#read 5, iclass 13, count 0 2006.257.13:48:06.95#ibcon#about to read 6, iclass 13, count 0 2006.257.13:48:06.95#ibcon#read 6, iclass 13, count 0 2006.257.13:48:06.95#ibcon#end of sib2, iclass 13, count 0 2006.257.13:48:06.95#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:48:06.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:48:06.95#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:48:06.95#ibcon#*before write, iclass 13, count 0 2006.257.13:48:06.95#ibcon#enter sib2, iclass 13, count 0 2006.257.13:48:06.95#ibcon#flushed, iclass 13, count 0 2006.257.13:48:06.95#ibcon#about to write, iclass 13, count 0 2006.257.13:48:06.95#ibcon#wrote, iclass 13, count 0 2006.257.13:48:06.95#ibcon#about to read 3, iclass 13, count 0 2006.257.13:48:06.99#ibcon#read 3, iclass 13, count 0 2006.257.13:48:06.99#ibcon#about to read 4, iclass 13, count 0 2006.257.13:48:06.99#ibcon#read 4, iclass 13, count 0 2006.257.13:48:06.99#ibcon#about to read 5, iclass 13, count 0 2006.257.13:48:06.99#ibcon#read 5, iclass 13, count 0 2006.257.13:48:06.99#ibcon#about to read 6, iclass 13, count 0 2006.257.13:48:06.99#ibcon#read 6, iclass 13, count 0 2006.257.13:48:06.99#ibcon#end of sib2, iclass 13, count 0 2006.257.13:48:06.99#ibcon#*after write, iclass 13, count 0 2006.257.13:48:06.99#ibcon#*before return 0, iclass 13, count 0 2006.257.13:48:06.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:06.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:06.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:48:06.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:48:06.99$vck44/va=3,8 2006.257.13:48:06.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.13:48:06.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.13:48:06.99#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:06.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:07.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:07.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:07.05#ibcon#enter wrdev, iclass 15, count 2 2006.257.13:48:07.05#ibcon#first serial, iclass 15, count 2 2006.257.13:48:07.05#ibcon#enter sib2, iclass 15, count 2 2006.257.13:48:07.05#ibcon#flushed, iclass 15, count 2 2006.257.13:48:07.05#ibcon#about to write, iclass 15, count 2 2006.257.13:48:07.05#ibcon#wrote, iclass 15, count 2 2006.257.13:48:07.05#ibcon#about to read 3, iclass 15, count 2 2006.257.13:48:07.07#ibcon#read 3, iclass 15, count 2 2006.257.13:48:07.07#ibcon#about to read 4, iclass 15, count 2 2006.257.13:48:07.07#ibcon#read 4, iclass 15, count 2 2006.257.13:48:07.07#ibcon#about to read 5, iclass 15, count 2 2006.257.13:48:07.07#ibcon#read 5, iclass 15, count 2 2006.257.13:48:07.07#ibcon#about to read 6, iclass 15, count 2 2006.257.13:48:07.07#ibcon#read 6, iclass 15, count 2 2006.257.13:48:07.07#ibcon#end of sib2, iclass 15, count 2 2006.257.13:48:07.07#ibcon#*mode == 0, iclass 15, count 2 2006.257.13:48:07.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.13:48:07.07#ibcon#[25=AT03-08\r\n] 2006.257.13:48:07.07#ibcon#*before write, iclass 15, count 2 2006.257.13:48:07.07#ibcon#enter sib2, iclass 15, count 2 2006.257.13:48:07.07#ibcon#flushed, iclass 15, count 2 2006.257.13:48:07.07#ibcon#about to write, iclass 15, count 2 2006.257.13:48:07.07#ibcon#wrote, iclass 15, count 2 2006.257.13:48:07.07#ibcon#about to read 3, iclass 15, count 2 2006.257.13:48:07.10#ibcon#read 3, iclass 15, count 2 2006.257.13:48:07.10#ibcon#about to read 4, iclass 15, count 2 2006.257.13:48:07.10#ibcon#read 4, iclass 15, count 2 2006.257.13:48:07.10#ibcon#about to read 5, iclass 15, count 2 2006.257.13:48:07.10#ibcon#read 5, iclass 15, count 2 2006.257.13:48:07.10#ibcon#about to read 6, iclass 15, count 2 2006.257.13:48:07.10#ibcon#read 6, iclass 15, count 2 2006.257.13:48:07.10#ibcon#end of sib2, iclass 15, count 2 2006.257.13:48:07.10#ibcon#*after write, iclass 15, count 2 2006.257.13:48:07.10#ibcon#*before return 0, iclass 15, count 2 2006.257.13:48:07.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:07.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:07.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.13:48:07.10#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:07.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:07.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:07.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:07.22#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:48:07.22#ibcon#first serial, iclass 15, count 0 2006.257.13:48:07.22#ibcon#enter sib2, iclass 15, count 0 2006.257.13:48:07.22#ibcon#flushed, iclass 15, count 0 2006.257.13:48:07.22#ibcon#about to write, iclass 15, count 0 2006.257.13:48:07.22#ibcon#wrote, iclass 15, count 0 2006.257.13:48:07.22#ibcon#about to read 3, iclass 15, count 0 2006.257.13:48:07.24#ibcon#read 3, iclass 15, count 0 2006.257.13:48:07.24#ibcon#about to read 4, iclass 15, count 0 2006.257.13:48:07.24#ibcon#read 4, iclass 15, count 0 2006.257.13:48:07.24#ibcon#about to read 5, iclass 15, count 0 2006.257.13:48:07.24#ibcon#read 5, iclass 15, count 0 2006.257.13:48:07.24#ibcon#about to read 6, iclass 15, count 0 2006.257.13:48:07.24#ibcon#read 6, iclass 15, count 0 2006.257.13:48:07.24#ibcon#end of sib2, iclass 15, count 0 2006.257.13:48:07.24#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:48:07.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:48:07.24#ibcon#[25=USB\r\n] 2006.257.13:48:07.24#ibcon#*before write, iclass 15, count 0 2006.257.13:48:07.24#ibcon#enter sib2, iclass 15, count 0 2006.257.13:48:07.24#ibcon#flushed, iclass 15, count 0 2006.257.13:48:07.24#ibcon#about to write, iclass 15, count 0 2006.257.13:48:07.24#ibcon#wrote, iclass 15, count 0 2006.257.13:48:07.24#ibcon#about to read 3, iclass 15, count 0 2006.257.13:48:07.27#ibcon#read 3, iclass 15, count 0 2006.257.13:48:07.27#ibcon#about to read 4, iclass 15, count 0 2006.257.13:48:07.27#ibcon#read 4, iclass 15, count 0 2006.257.13:48:07.27#ibcon#about to read 5, iclass 15, count 0 2006.257.13:48:07.27#ibcon#read 5, iclass 15, count 0 2006.257.13:48:07.27#ibcon#about to read 6, iclass 15, count 0 2006.257.13:48:07.27#ibcon#read 6, iclass 15, count 0 2006.257.13:48:07.27#ibcon#end of sib2, iclass 15, count 0 2006.257.13:48:07.27#ibcon#*after write, iclass 15, count 0 2006.257.13:48:07.27#ibcon#*before return 0, iclass 15, count 0 2006.257.13:48:07.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:07.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:07.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:48:07.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:48:07.27$vck44/valo=4,624.99 2006.257.13:48:07.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.13:48:07.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.13:48:07.27#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:07.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:07.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:07.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:07.27#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:48:07.27#ibcon#first serial, iclass 17, count 0 2006.257.13:48:07.27#ibcon#enter sib2, iclass 17, count 0 2006.257.13:48:07.27#ibcon#flushed, iclass 17, count 0 2006.257.13:48:07.27#ibcon#about to write, iclass 17, count 0 2006.257.13:48:07.27#ibcon#wrote, iclass 17, count 0 2006.257.13:48:07.27#ibcon#about to read 3, iclass 17, count 0 2006.257.13:48:07.29#ibcon#read 3, iclass 17, count 0 2006.257.13:48:07.29#ibcon#about to read 4, iclass 17, count 0 2006.257.13:48:07.29#ibcon#read 4, iclass 17, count 0 2006.257.13:48:07.29#ibcon#about to read 5, iclass 17, count 0 2006.257.13:48:07.29#ibcon#read 5, iclass 17, count 0 2006.257.13:48:07.29#ibcon#about to read 6, iclass 17, count 0 2006.257.13:48:07.29#ibcon#read 6, iclass 17, count 0 2006.257.13:48:07.29#ibcon#end of sib2, iclass 17, count 0 2006.257.13:48:07.29#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:48:07.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:48:07.29#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:48:07.29#ibcon#*before write, iclass 17, count 0 2006.257.13:48:07.29#ibcon#enter sib2, iclass 17, count 0 2006.257.13:48:07.29#ibcon#flushed, iclass 17, count 0 2006.257.13:48:07.29#ibcon#about to write, iclass 17, count 0 2006.257.13:48:07.29#ibcon#wrote, iclass 17, count 0 2006.257.13:48:07.29#ibcon#about to read 3, iclass 17, count 0 2006.257.13:48:07.33#ibcon#read 3, iclass 17, count 0 2006.257.13:48:07.33#ibcon#about to read 4, iclass 17, count 0 2006.257.13:48:07.33#ibcon#read 4, iclass 17, count 0 2006.257.13:48:07.33#ibcon#about to read 5, iclass 17, count 0 2006.257.13:48:07.33#ibcon#read 5, iclass 17, count 0 2006.257.13:48:07.33#ibcon#about to read 6, iclass 17, count 0 2006.257.13:48:07.33#ibcon#read 6, iclass 17, count 0 2006.257.13:48:07.33#ibcon#end of sib2, iclass 17, count 0 2006.257.13:48:07.33#ibcon#*after write, iclass 17, count 0 2006.257.13:48:07.33#ibcon#*before return 0, iclass 17, count 0 2006.257.13:48:07.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:07.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:07.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:48:07.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:48:07.33$vck44/va=4,7 2006.257.13:48:07.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.13:48:07.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.13:48:07.33#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:07.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:07.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:07.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:07.39#ibcon#enter wrdev, iclass 19, count 2 2006.257.13:48:07.39#ibcon#first serial, iclass 19, count 2 2006.257.13:48:07.39#ibcon#enter sib2, iclass 19, count 2 2006.257.13:48:07.39#ibcon#flushed, iclass 19, count 2 2006.257.13:48:07.39#ibcon#about to write, iclass 19, count 2 2006.257.13:48:07.39#ibcon#wrote, iclass 19, count 2 2006.257.13:48:07.39#ibcon#about to read 3, iclass 19, count 2 2006.257.13:48:07.41#ibcon#read 3, iclass 19, count 2 2006.257.13:48:07.41#ibcon#about to read 4, iclass 19, count 2 2006.257.13:48:07.41#ibcon#read 4, iclass 19, count 2 2006.257.13:48:07.41#ibcon#about to read 5, iclass 19, count 2 2006.257.13:48:07.41#ibcon#read 5, iclass 19, count 2 2006.257.13:48:07.41#ibcon#about to read 6, iclass 19, count 2 2006.257.13:48:07.41#ibcon#read 6, iclass 19, count 2 2006.257.13:48:07.41#ibcon#end of sib2, iclass 19, count 2 2006.257.13:48:07.41#ibcon#*mode == 0, iclass 19, count 2 2006.257.13:48:07.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.13:48:07.41#ibcon#[25=AT04-07\r\n] 2006.257.13:48:07.41#ibcon#*before write, iclass 19, count 2 2006.257.13:48:07.41#ibcon#enter sib2, iclass 19, count 2 2006.257.13:48:07.41#ibcon#flushed, iclass 19, count 2 2006.257.13:48:07.41#ibcon#about to write, iclass 19, count 2 2006.257.13:48:07.41#ibcon#wrote, iclass 19, count 2 2006.257.13:48:07.41#ibcon#about to read 3, iclass 19, count 2 2006.257.13:48:07.44#ibcon#read 3, iclass 19, count 2 2006.257.13:48:07.44#ibcon#about to read 4, iclass 19, count 2 2006.257.13:48:07.44#ibcon#read 4, iclass 19, count 2 2006.257.13:48:07.44#ibcon#about to read 5, iclass 19, count 2 2006.257.13:48:07.44#ibcon#read 5, iclass 19, count 2 2006.257.13:48:07.44#ibcon#about to read 6, iclass 19, count 2 2006.257.13:48:07.44#ibcon#read 6, iclass 19, count 2 2006.257.13:48:07.44#ibcon#end of sib2, iclass 19, count 2 2006.257.13:48:07.44#ibcon#*after write, iclass 19, count 2 2006.257.13:48:07.44#ibcon#*before return 0, iclass 19, count 2 2006.257.13:48:07.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:07.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:07.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.13:48:07.44#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:07.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:07.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:07.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:07.56#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:48:07.56#ibcon#first serial, iclass 19, count 0 2006.257.13:48:07.56#ibcon#enter sib2, iclass 19, count 0 2006.257.13:48:07.56#ibcon#flushed, iclass 19, count 0 2006.257.13:48:07.56#ibcon#about to write, iclass 19, count 0 2006.257.13:48:07.56#ibcon#wrote, iclass 19, count 0 2006.257.13:48:07.56#ibcon#about to read 3, iclass 19, count 0 2006.257.13:48:07.58#ibcon#read 3, iclass 19, count 0 2006.257.13:48:07.58#ibcon#about to read 4, iclass 19, count 0 2006.257.13:48:07.58#ibcon#read 4, iclass 19, count 0 2006.257.13:48:07.58#ibcon#about to read 5, iclass 19, count 0 2006.257.13:48:07.58#ibcon#read 5, iclass 19, count 0 2006.257.13:48:07.58#ibcon#about to read 6, iclass 19, count 0 2006.257.13:48:07.58#ibcon#read 6, iclass 19, count 0 2006.257.13:48:07.58#ibcon#end of sib2, iclass 19, count 0 2006.257.13:48:07.58#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:48:07.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:48:07.58#ibcon#[25=USB\r\n] 2006.257.13:48:07.58#ibcon#*before write, iclass 19, count 0 2006.257.13:48:07.58#ibcon#enter sib2, iclass 19, count 0 2006.257.13:48:07.58#ibcon#flushed, iclass 19, count 0 2006.257.13:48:07.58#ibcon#about to write, iclass 19, count 0 2006.257.13:48:07.58#ibcon#wrote, iclass 19, count 0 2006.257.13:48:07.58#ibcon#about to read 3, iclass 19, count 0 2006.257.13:48:07.61#ibcon#read 3, iclass 19, count 0 2006.257.13:48:07.61#ibcon#about to read 4, iclass 19, count 0 2006.257.13:48:07.61#ibcon#read 4, iclass 19, count 0 2006.257.13:48:07.61#ibcon#about to read 5, iclass 19, count 0 2006.257.13:48:07.61#ibcon#read 5, iclass 19, count 0 2006.257.13:48:07.61#ibcon#about to read 6, iclass 19, count 0 2006.257.13:48:07.61#ibcon#read 6, iclass 19, count 0 2006.257.13:48:07.61#ibcon#end of sib2, iclass 19, count 0 2006.257.13:48:07.61#ibcon#*after write, iclass 19, count 0 2006.257.13:48:07.61#ibcon#*before return 0, iclass 19, count 0 2006.257.13:48:07.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:07.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:07.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:48:07.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:48:07.61$vck44/valo=5,734.99 2006.257.13:48:07.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.13:48:07.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.13:48:07.61#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:07.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:07.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:07.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:07.61#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:48:07.61#ibcon#first serial, iclass 21, count 0 2006.257.13:48:07.61#ibcon#enter sib2, iclass 21, count 0 2006.257.13:48:07.61#ibcon#flushed, iclass 21, count 0 2006.257.13:48:07.61#ibcon#about to write, iclass 21, count 0 2006.257.13:48:07.61#ibcon#wrote, iclass 21, count 0 2006.257.13:48:07.61#ibcon#about to read 3, iclass 21, count 0 2006.257.13:48:07.63#ibcon#read 3, iclass 21, count 0 2006.257.13:48:07.63#ibcon#about to read 4, iclass 21, count 0 2006.257.13:48:07.63#ibcon#read 4, iclass 21, count 0 2006.257.13:48:07.63#ibcon#about to read 5, iclass 21, count 0 2006.257.13:48:07.63#ibcon#read 5, iclass 21, count 0 2006.257.13:48:07.63#ibcon#about to read 6, iclass 21, count 0 2006.257.13:48:07.63#ibcon#read 6, iclass 21, count 0 2006.257.13:48:07.63#ibcon#end of sib2, iclass 21, count 0 2006.257.13:48:07.63#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:48:07.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:48:07.63#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:48:07.63#ibcon#*before write, iclass 21, count 0 2006.257.13:48:07.63#ibcon#enter sib2, iclass 21, count 0 2006.257.13:48:07.63#ibcon#flushed, iclass 21, count 0 2006.257.13:48:07.63#ibcon#about to write, iclass 21, count 0 2006.257.13:48:07.63#ibcon#wrote, iclass 21, count 0 2006.257.13:48:07.63#ibcon#about to read 3, iclass 21, count 0 2006.257.13:48:07.67#ibcon#read 3, iclass 21, count 0 2006.257.13:48:07.67#ibcon#about to read 4, iclass 21, count 0 2006.257.13:48:07.67#ibcon#read 4, iclass 21, count 0 2006.257.13:48:07.67#ibcon#about to read 5, iclass 21, count 0 2006.257.13:48:07.67#ibcon#read 5, iclass 21, count 0 2006.257.13:48:07.67#ibcon#about to read 6, iclass 21, count 0 2006.257.13:48:07.67#ibcon#read 6, iclass 21, count 0 2006.257.13:48:07.67#ibcon#end of sib2, iclass 21, count 0 2006.257.13:48:07.67#ibcon#*after write, iclass 21, count 0 2006.257.13:48:07.67#ibcon#*before return 0, iclass 21, count 0 2006.257.13:48:07.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:07.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:07.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:48:07.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:48:07.67$vck44/va=5,4 2006.257.13:48:07.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.13:48:07.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.13:48:07.67#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:07.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:07.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:07.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:07.73#ibcon#enter wrdev, iclass 23, count 2 2006.257.13:48:07.73#ibcon#first serial, iclass 23, count 2 2006.257.13:48:07.73#ibcon#enter sib2, iclass 23, count 2 2006.257.13:48:07.73#ibcon#flushed, iclass 23, count 2 2006.257.13:48:07.73#ibcon#about to write, iclass 23, count 2 2006.257.13:48:07.73#ibcon#wrote, iclass 23, count 2 2006.257.13:48:07.73#ibcon#about to read 3, iclass 23, count 2 2006.257.13:48:07.75#ibcon#read 3, iclass 23, count 2 2006.257.13:48:07.75#ibcon#about to read 4, iclass 23, count 2 2006.257.13:48:07.75#ibcon#read 4, iclass 23, count 2 2006.257.13:48:07.75#ibcon#about to read 5, iclass 23, count 2 2006.257.13:48:07.75#ibcon#read 5, iclass 23, count 2 2006.257.13:48:07.75#ibcon#about to read 6, iclass 23, count 2 2006.257.13:48:07.75#ibcon#read 6, iclass 23, count 2 2006.257.13:48:07.75#ibcon#end of sib2, iclass 23, count 2 2006.257.13:48:07.75#ibcon#*mode == 0, iclass 23, count 2 2006.257.13:48:07.75#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.13:48:07.75#ibcon#[25=AT05-04\r\n] 2006.257.13:48:07.75#ibcon#*before write, iclass 23, count 2 2006.257.13:48:07.75#ibcon#enter sib2, iclass 23, count 2 2006.257.13:48:07.75#ibcon#flushed, iclass 23, count 2 2006.257.13:48:07.75#ibcon#about to write, iclass 23, count 2 2006.257.13:48:07.75#ibcon#wrote, iclass 23, count 2 2006.257.13:48:07.75#ibcon#about to read 3, iclass 23, count 2 2006.257.13:48:07.78#ibcon#read 3, iclass 23, count 2 2006.257.13:48:07.78#ibcon#about to read 4, iclass 23, count 2 2006.257.13:48:07.78#ibcon#read 4, iclass 23, count 2 2006.257.13:48:07.78#ibcon#about to read 5, iclass 23, count 2 2006.257.13:48:07.78#ibcon#read 5, iclass 23, count 2 2006.257.13:48:07.78#ibcon#about to read 6, iclass 23, count 2 2006.257.13:48:07.78#ibcon#read 6, iclass 23, count 2 2006.257.13:48:07.78#ibcon#end of sib2, iclass 23, count 2 2006.257.13:48:07.78#ibcon#*after write, iclass 23, count 2 2006.257.13:48:07.78#ibcon#*before return 0, iclass 23, count 2 2006.257.13:48:07.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:07.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:07.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.13:48:07.78#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:07.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:07.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:07.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:07.90#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:48:07.90#ibcon#first serial, iclass 23, count 0 2006.257.13:48:07.90#ibcon#enter sib2, iclass 23, count 0 2006.257.13:48:07.90#ibcon#flushed, iclass 23, count 0 2006.257.13:48:07.90#ibcon#about to write, iclass 23, count 0 2006.257.13:48:07.90#ibcon#wrote, iclass 23, count 0 2006.257.13:48:07.90#ibcon#about to read 3, iclass 23, count 0 2006.257.13:48:07.92#ibcon#read 3, iclass 23, count 0 2006.257.13:48:07.92#ibcon#about to read 4, iclass 23, count 0 2006.257.13:48:07.92#ibcon#read 4, iclass 23, count 0 2006.257.13:48:07.92#ibcon#about to read 5, iclass 23, count 0 2006.257.13:48:07.92#ibcon#read 5, iclass 23, count 0 2006.257.13:48:07.92#ibcon#about to read 6, iclass 23, count 0 2006.257.13:48:07.92#ibcon#read 6, iclass 23, count 0 2006.257.13:48:07.92#ibcon#end of sib2, iclass 23, count 0 2006.257.13:48:07.92#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:48:07.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:48:07.92#ibcon#[25=USB\r\n] 2006.257.13:48:07.92#ibcon#*before write, iclass 23, count 0 2006.257.13:48:07.92#ibcon#enter sib2, iclass 23, count 0 2006.257.13:48:07.92#ibcon#flushed, iclass 23, count 0 2006.257.13:48:07.92#ibcon#about to write, iclass 23, count 0 2006.257.13:48:07.92#ibcon#wrote, iclass 23, count 0 2006.257.13:48:07.92#ibcon#about to read 3, iclass 23, count 0 2006.257.13:48:07.95#ibcon#read 3, iclass 23, count 0 2006.257.13:48:07.95#ibcon#about to read 4, iclass 23, count 0 2006.257.13:48:07.95#ibcon#read 4, iclass 23, count 0 2006.257.13:48:07.95#ibcon#about to read 5, iclass 23, count 0 2006.257.13:48:07.95#ibcon#read 5, iclass 23, count 0 2006.257.13:48:07.95#ibcon#about to read 6, iclass 23, count 0 2006.257.13:48:07.95#ibcon#read 6, iclass 23, count 0 2006.257.13:48:07.95#ibcon#end of sib2, iclass 23, count 0 2006.257.13:48:07.95#ibcon#*after write, iclass 23, count 0 2006.257.13:48:07.95#ibcon#*before return 0, iclass 23, count 0 2006.257.13:48:07.95#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:07.95#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:07.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:48:07.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:48:07.95$vck44/valo=6,814.99 2006.257.13:48:07.95#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.13:48:07.95#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.13:48:07.95#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:07.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:07.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:07.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:07.95#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:48:07.95#ibcon#first serial, iclass 25, count 0 2006.257.13:48:07.95#ibcon#enter sib2, iclass 25, count 0 2006.257.13:48:07.95#ibcon#flushed, iclass 25, count 0 2006.257.13:48:07.95#ibcon#about to write, iclass 25, count 0 2006.257.13:48:07.95#ibcon#wrote, iclass 25, count 0 2006.257.13:48:07.95#ibcon#about to read 3, iclass 25, count 0 2006.257.13:48:07.97#ibcon#read 3, iclass 25, count 0 2006.257.13:48:07.97#ibcon#about to read 4, iclass 25, count 0 2006.257.13:48:07.97#ibcon#read 4, iclass 25, count 0 2006.257.13:48:07.97#ibcon#about to read 5, iclass 25, count 0 2006.257.13:48:07.97#ibcon#read 5, iclass 25, count 0 2006.257.13:48:07.97#ibcon#about to read 6, iclass 25, count 0 2006.257.13:48:07.97#ibcon#read 6, iclass 25, count 0 2006.257.13:48:07.97#ibcon#end of sib2, iclass 25, count 0 2006.257.13:48:07.97#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:48:07.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:48:07.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:48:07.97#ibcon#*before write, iclass 25, count 0 2006.257.13:48:07.97#ibcon#enter sib2, iclass 25, count 0 2006.257.13:48:07.97#ibcon#flushed, iclass 25, count 0 2006.257.13:48:07.97#ibcon#about to write, iclass 25, count 0 2006.257.13:48:07.97#ibcon#wrote, iclass 25, count 0 2006.257.13:48:07.97#ibcon#about to read 3, iclass 25, count 0 2006.257.13:48:08.01#ibcon#read 3, iclass 25, count 0 2006.257.13:48:08.01#ibcon#about to read 4, iclass 25, count 0 2006.257.13:48:08.01#ibcon#read 4, iclass 25, count 0 2006.257.13:48:08.01#ibcon#about to read 5, iclass 25, count 0 2006.257.13:48:08.01#ibcon#read 5, iclass 25, count 0 2006.257.13:48:08.01#ibcon#about to read 6, iclass 25, count 0 2006.257.13:48:08.01#ibcon#read 6, iclass 25, count 0 2006.257.13:48:08.01#ibcon#end of sib2, iclass 25, count 0 2006.257.13:48:08.01#ibcon#*after write, iclass 25, count 0 2006.257.13:48:08.01#ibcon#*before return 0, iclass 25, count 0 2006.257.13:48:08.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:08.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:08.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:48:08.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:48:08.01$vck44/va=6,4 2006.257.13:48:08.01#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.13:48:08.01#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.13:48:08.01#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:08.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:08.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:08.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:08.07#ibcon#enter wrdev, iclass 27, count 2 2006.257.13:48:08.07#ibcon#first serial, iclass 27, count 2 2006.257.13:48:08.07#ibcon#enter sib2, iclass 27, count 2 2006.257.13:48:08.07#ibcon#flushed, iclass 27, count 2 2006.257.13:48:08.07#ibcon#about to write, iclass 27, count 2 2006.257.13:48:08.07#ibcon#wrote, iclass 27, count 2 2006.257.13:48:08.07#ibcon#about to read 3, iclass 27, count 2 2006.257.13:48:08.09#ibcon#read 3, iclass 27, count 2 2006.257.13:48:08.09#ibcon#about to read 4, iclass 27, count 2 2006.257.13:48:08.09#ibcon#read 4, iclass 27, count 2 2006.257.13:48:08.09#ibcon#about to read 5, iclass 27, count 2 2006.257.13:48:08.09#ibcon#read 5, iclass 27, count 2 2006.257.13:48:08.09#ibcon#about to read 6, iclass 27, count 2 2006.257.13:48:08.09#ibcon#read 6, iclass 27, count 2 2006.257.13:48:08.09#ibcon#end of sib2, iclass 27, count 2 2006.257.13:48:08.09#ibcon#*mode == 0, iclass 27, count 2 2006.257.13:48:08.09#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.13:48:08.09#ibcon#[25=AT06-04\r\n] 2006.257.13:48:08.09#ibcon#*before write, iclass 27, count 2 2006.257.13:48:08.09#ibcon#enter sib2, iclass 27, count 2 2006.257.13:48:08.09#ibcon#flushed, iclass 27, count 2 2006.257.13:48:08.09#ibcon#about to write, iclass 27, count 2 2006.257.13:48:08.09#ibcon#wrote, iclass 27, count 2 2006.257.13:48:08.09#ibcon#about to read 3, iclass 27, count 2 2006.257.13:48:08.12#ibcon#read 3, iclass 27, count 2 2006.257.13:48:08.12#ibcon#about to read 4, iclass 27, count 2 2006.257.13:48:08.12#ibcon#read 4, iclass 27, count 2 2006.257.13:48:08.12#ibcon#about to read 5, iclass 27, count 2 2006.257.13:48:08.12#ibcon#read 5, iclass 27, count 2 2006.257.13:48:08.12#ibcon#about to read 6, iclass 27, count 2 2006.257.13:48:08.12#ibcon#read 6, iclass 27, count 2 2006.257.13:48:08.12#ibcon#end of sib2, iclass 27, count 2 2006.257.13:48:08.12#ibcon#*after write, iclass 27, count 2 2006.257.13:48:08.12#ibcon#*before return 0, iclass 27, count 2 2006.257.13:48:08.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:08.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:08.12#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.13:48:08.12#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:08.12#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:08.24#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:08.24#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:08.24#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:48:08.24#ibcon#first serial, iclass 27, count 0 2006.257.13:48:08.24#ibcon#enter sib2, iclass 27, count 0 2006.257.13:48:08.24#ibcon#flushed, iclass 27, count 0 2006.257.13:48:08.24#ibcon#about to write, iclass 27, count 0 2006.257.13:48:08.24#ibcon#wrote, iclass 27, count 0 2006.257.13:48:08.24#ibcon#about to read 3, iclass 27, count 0 2006.257.13:48:08.26#ibcon#read 3, iclass 27, count 0 2006.257.13:48:08.26#ibcon#about to read 4, iclass 27, count 0 2006.257.13:48:08.26#ibcon#read 4, iclass 27, count 0 2006.257.13:48:08.26#ibcon#about to read 5, iclass 27, count 0 2006.257.13:48:08.26#ibcon#read 5, iclass 27, count 0 2006.257.13:48:08.26#ibcon#about to read 6, iclass 27, count 0 2006.257.13:48:08.26#ibcon#read 6, iclass 27, count 0 2006.257.13:48:08.26#ibcon#end of sib2, iclass 27, count 0 2006.257.13:48:08.26#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:48:08.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:48:08.26#ibcon#[25=USB\r\n] 2006.257.13:48:08.26#ibcon#*before write, iclass 27, count 0 2006.257.13:48:08.26#ibcon#enter sib2, iclass 27, count 0 2006.257.13:48:08.26#ibcon#flushed, iclass 27, count 0 2006.257.13:48:08.26#ibcon#about to write, iclass 27, count 0 2006.257.13:48:08.26#ibcon#wrote, iclass 27, count 0 2006.257.13:48:08.26#ibcon#about to read 3, iclass 27, count 0 2006.257.13:48:08.29#ibcon#read 3, iclass 27, count 0 2006.257.13:48:08.29#ibcon#about to read 4, iclass 27, count 0 2006.257.13:48:08.29#ibcon#read 4, iclass 27, count 0 2006.257.13:48:08.29#ibcon#about to read 5, iclass 27, count 0 2006.257.13:48:08.29#ibcon#read 5, iclass 27, count 0 2006.257.13:48:08.29#ibcon#about to read 6, iclass 27, count 0 2006.257.13:48:08.29#ibcon#read 6, iclass 27, count 0 2006.257.13:48:08.29#ibcon#end of sib2, iclass 27, count 0 2006.257.13:48:08.29#ibcon#*after write, iclass 27, count 0 2006.257.13:48:08.29#ibcon#*before return 0, iclass 27, count 0 2006.257.13:48:08.29#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:08.29#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:08.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:48:08.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:48:08.29$vck44/valo=7,864.99 2006.257.13:48:08.29#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.13:48:08.29#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.13:48:08.29#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:08.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:08.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:08.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:08.29#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:48:08.29#ibcon#first serial, iclass 29, count 0 2006.257.13:48:08.29#ibcon#enter sib2, iclass 29, count 0 2006.257.13:48:08.29#ibcon#flushed, iclass 29, count 0 2006.257.13:48:08.29#ibcon#about to write, iclass 29, count 0 2006.257.13:48:08.29#ibcon#wrote, iclass 29, count 0 2006.257.13:48:08.29#ibcon#about to read 3, iclass 29, count 0 2006.257.13:48:08.31#ibcon#read 3, iclass 29, count 0 2006.257.13:48:08.31#ibcon#about to read 4, iclass 29, count 0 2006.257.13:48:08.31#ibcon#read 4, iclass 29, count 0 2006.257.13:48:08.31#ibcon#about to read 5, iclass 29, count 0 2006.257.13:48:08.31#ibcon#read 5, iclass 29, count 0 2006.257.13:48:08.31#ibcon#about to read 6, iclass 29, count 0 2006.257.13:48:08.31#ibcon#read 6, iclass 29, count 0 2006.257.13:48:08.31#ibcon#end of sib2, iclass 29, count 0 2006.257.13:48:08.31#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:48:08.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:48:08.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:48:08.31#ibcon#*before write, iclass 29, count 0 2006.257.13:48:08.31#ibcon#enter sib2, iclass 29, count 0 2006.257.13:48:08.31#ibcon#flushed, iclass 29, count 0 2006.257.13:48:08.31#ibcon#about to write, iclass 29, count 0 2006.257.13:48:08.31#ibcon#wrote, iclass 29, count 0 2006.257.13:48:08.31#ibcon#about to read 3, iclass 29, count 0 2006.257.13:48:08.35#ibcon#read 3, iclass 29, count 0 2006.257.13:48:08.35#ibcon#about to read 4, iclass 29, count 0 2006.257.13:48:08.35#ibcon#read 4, iclass 29, count 0 2006.257.13:48:08.35#ibcon#about to read 5, iclass 29, count 0 2006.257.13:48:08.35#ibcon#read 5, iclass 29, count 0 2006.257.13:48:08.35#ibcon#about to read 6, iclass 29, count 0 2006.257.13:48:08.35#ibcon#read 6, iclass 29, count 0 2006.257.13:48:08.35#ibcon#end of sib2, iclass 29, count 0 2006.257.13:48:08.35#ibcon#*after write, iclass 29, count 0 2006.257.13:48:08.35#ibcon#*before return 0, iclass 29, count 0 2006.257.13:48:08.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:08.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:08.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:48:08.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:48:08.35$vck44/va=7,4 2006.257.13:48:08.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.13:48:08.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.13:48:08.35#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:08.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:08.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:08.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:08.41#ibcon#enter wrdev, iclass 31, count 2 2006.257.13:48:08.41#ibcon#first serial, iclass 31, count 2 2006.257.13:48:08.41#ibcon#enter sib2, iclass 31, count 2 2006.257.13:48:08.41#ibcon#flushed, iclass 31, count 2 2006.257.13:48:08.41#ibcon#about to write, iclass 31, count 2 2006.257.13:48:08.41#ibcon#wrote, iclass 31, count 2 2006.257.13:48:08.41#ibcon#about to read 3, iclass 31, count 2 2006.257.13:48:08.43#ibcon#read 3, iclass 31, count 2 2006.257.13:48:08.43#ibcon#about to read 4, iclass 31, count 2 2006.257.13:48:08.43#ibcon#read 4, iclass 31, count 2 2006.257.13:48:08.43#ibcon#about to read 5, iclass 31, count 2 2006.257.13:48:08.43#ibcon#read 5, iclass 31, count 2 2006.257.13:48:08.43#ibcon#about to read 6, iclass 31, count 2 2006.257.13:48:08.43#ibcon#read 6, iclass 31, count 2 2006.257.13:48:08.43#ibcon#end of sib2, iclass 31, count 2 2006.257.13:48:08.43#ibcon#*mode == 0, iclass 31, count 2 2006.257.13:48:08.43#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.13:48:08.43#ibcon#[25=AT07-04\r\n] 2006.257.13:48:08.43#ibcon#*before write, iclass 31, count 2 2006.257.13:48:08.43#ibcon#enter sib2, iclass 31, count 2 2006.257.13:48:08.43#ibcon#flushed, iclass 31, count 2 2006.257.13:48:08.43#ibcon#about to write, iclass 31, count 2 2006.257.13:48:08.43#ibcon#wrote, iclass 31, count 2 2006.257.13:48:08.43#ibcon#about to read 3, iclass 31, count 2 2006.257.13:48:08.46#ibcon#read 3, iclass 31, count 2 2006.257.13:48:08.46#ibcon#about to read 4, iclass 31, count 2 2006.257.13:48:08.46#ibcon#read 4, iclass 31, count 2 2006.257.13:48:08.46#ibcon#about to read 5, iclass 31, count 2 2006.257.13:48:08.46#ibcon#read 5, iclass 31, count 2 2006.257.13:48:08.46#ibcon#about to read 6, iclass 31, count 2 2006.257.13:48:08.46#ibcon#read 6, iclass 31, count 2 2006.257.13:48:08.46#ibcon#end of sib2, iclass 31, count 2 2006.257.13:48:08.46#ibcon#*after write, iclass 31, count 2 2006.257.13:48:08.46#ibcon#*before return 0, iclass 31, count 2 2006.257.13:48:08.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:08.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:08.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.13:48:08.52#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:08.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:08.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:08.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:08.64#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:48:08.64#ibcon#first serial, iclass 31, count 0 2006.257.13:48:08.64#ibcon#enter sib2, iclass 31, count 0 2006.257.13:48:08.64#ibcon#flushed, iclass 31, count 0 2006.257.13:48:08.64#ibcon#about to write, iclass 31, count 0 2006.257.13:48:08.64#ibcon#wrote, iclass 31, count 0 2006.257.13:48:08.64#ibcon#about to read 3, iclass 31, count 0 2006.257.13:48:08.66#ibcon#read 3, iclass 31, count 0 2006.257.13:48:08.66#ibcon#about to read 4, iclass 31, count 0 2006.257.13:48:08.66#ibcon#read 4, iclass 31, count 0 2006.257.13:48:08.66#ibcon#about to read 5, iclass 31, count 0 2006.257.13:48:08.66#ibcon#read 5, iclass 31, count 0 2006.257.13:48:08.66#ibcon#about to read 6, iclass 31, count 0 2006.257.13:48:08.66#ibcon#read 6, iclass 31, count 0 2006.257.13:48:08.66#ibcon#end of sib2, iclass 31, count 0 2006.257.13:48:08.66#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:48:08.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:48:08.66#ibcon#[25=USB\r\n] 2006.257.13:48:08.66#ibcon#*before write, iclass 31, count 0 2006.257.13:48:08.66#ibcon#enter sib2, iclass 31, count 0 2006.257.13:48:08.66#ibcon#flushed, iclass 31, count 0 2006.257.13:48:08.66#ibcon#about to write, iclass 31, count 0 2006.257.13:48:08.66#ibcon#wrote, iclass 31, count 0 2006.257.13:48:08.66#ibcon#about to read 3, iclass 31, count 0 2006.257.13:48:08.69#ibcon#read 3, iclass 31, count 0 2006.257.13:48:08.69#ibcon#about to read 4, iclass 31, count 0 2006.257.13:48:08.69#ibcon#read 4, iclass 31, count 0 2006.257.13:48:08.69#ibcon#about to read 5, iclass 31, count 0 2006.257.13:48:08.69#ibcon#read 5, iclass 31, count 0 2006.257.13:48:08.69#ibcon#about to read 6, iclass 31, count 0 2006.257.13:48:08.69#ibcon#read 6, iclass 31, count 0 2006.257.13:48:08.69#ibcon#end of sib2, iclass 31, count 0 2006.257.13:48:08.69#ibcon#*after write, iclass 31, count 0 2006.257.13:48:08.69#ibcon#*before return 0, iclass 31, count 0 2006.257.13:48:08.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:08.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:08.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:48:08.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:48:08.69$vck44/valo=8,884.99 2006.257.13:48:08.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.13:48:08.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.13:48:08.69#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:08.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:48:08.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:48:08.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:48:08.69#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:48:08.69#ibcon#first serial, iclass 33, count 0 2006.257.13:48:08.69#ibcon#enter sib2, iclass 33, count 0 2006.257.13:48:08.69#ibcon#flushed, iclass 33, count 0 2006.257.13:48:08.69#ibcon#about to write, iclass 33, count 0 2006.257.13:48:08.69#ibcon#wrote, iclass 33, count 0 2006.257.13:48:08.69#ibcon#about to read 3, iclass 33, count 0 2006.257.13:48:08.71#ibcon#read 3, iclass 33, count 0 2006.257.13:48:08.71#ibcon#about to read 4, iclass 33, count 0 2006.257.13:48:08.71#ibcon#read 4, iclass 33, count 0 2006.257.13:48:08.71#ibcon#about to read 5, iclass 33, count 0 2006.257.13:48:08.71#ibcon#read 5, iclass 33, count 0 2006.257.13:48:08.71#ibcon#about to read 6, iclass 33, count 0 2006.257.13:48:08.71#ibcon#read 6, iclass 33, count 0 2006.257.13:48:08.71#ibcon#end of sib2, iclass 33, count 0 2006.257.13:48:08.71#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:48:08.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:48:08.71#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:48:08.71#ibcon#*before write, iclass 33, count 0 2006.257.13:48:08.71#ibcon#enter sib2, iclass 33, count 0 2006.257.13:48:08.71#ibcon#flushed, iclass 33, count 0 2006.257.13:48:08.71#ibcon#about to write, iclass 33, count 0 2006.257.13:48:08.71#ibcon#wrote, iclass 33, count 0 2006.257.13:48:08.71#ibcon#about to read 3, iclass 33, count 0 2006.257.13:48:08.75#ibcon#read 3, iclass 33, count 0 2006.257.13:48:08.75#ibcon#about to read 4, iclass 33, count 0 2006.257.13:48:08.75#ibcon#read 4, iclass 33, count 0 2006.257.13:48:08.75#ibcon#about to read 5, iclass 33, count 0 2006.257.13:48:08.75#ibcon#read 5, iclass 33, count 0 2006.257.13:48:08.75#ibcon#about to read 6, iclass 33, count 0 2006.257.13:48:08.75#ibcon#read 6, iclass 33, count 0 2006.257.13:48:08.75#ibcon#end of sib2, iclass 33, count 0 2006.257.13:48:08.75#ibcon#*after write, iclass 33, count 0 2006.257.13:48:08.75#ibcon#*before return 0, iclass 33, count 0 2006.257.13:48:08.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:48:08.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:48:08.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:48:08.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:48:08.75$vck44/va=8,4 2006.257.13:48:08.75#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.13:48:08.75#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.13:48:08.75#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:08.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:48:08.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:48:08.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:48:08.81#ibcon#enter wrdev, iclass 35, count 2 2006.257.13:48:08.81#ibcon#first serial, iclass 35, count 2 2006.257.13:48:08.81#ibcon#enter sib2, iclass 35, count 2 2006.257.13:48:08.81#ibcon#flushed, iclass 35, count 2 2006.257.13:48:08.81#ibcon#about to write, iclass 35, count 2 2006.257.13:48:08.81#ibcon#wrote, iclass 35, count 2 2006.257.13:48:08.81#ibcon#about to read 3, iclass 35, count 2 2006.257.13:48:08.83#ibcon#read 3, iclass 35, count 2 2006.257.13:48:08.83#ibcon#about to read 4, iclass 35, count 2 2006.257.13:48:08.83#ibcon#read 4, iclass 35, count 2 2006.257.13:48:08.83#ibcon#about to read 5, iclass 35, count 2 2006.257.13:48:08.83#ibcon#read 5, iclass 35, count 2 2006.257.13:48:08.83#ibcon#about to read 6, iclass 35, count 2 2006.257.13:48:08.83#ibcon#read 6, iclass 35, count 2 2006.257.13:48:08.83#ibcon#end of sib2, iclass 35, count 2 2006.257.13:48:08.83#ibcon#*mode == 0, iclass 35, count 2 2006.257.13:48:08.83#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.13:48:08.83#ibcon#[25=AT08-04\r\n] 2006.257.13:48:08.83#ibcon#*before write, iclass 35, count 2 2006.257.13:48:08.83#ibcon#enter sib2, iclass 35, count 2 2006.257.13:48:08.83#ibcon#flushed, iclass 35, count 2 2006.257.13:48:08.83#ibcon#about to write, iclass 35, count 2 2006.257.13:48:08.83#ibcon#wrote, iclass 35, count 2 2006.257.13:48:08.83#ibcon#about to read 3, iclass 35, count 2 2006.257.13:48:08.86#ibcon#read 3, iclass 35, count 2 2006.257.13:48:08.86#ibcon#about to read 4, iclass 35, count 2 2006.257.13:48:08.86#ibcon#read 4, iclass 35, count 2 2006.257.13:48:08.86#ibcon#about to read 5, iclass 35, count 2 2006.257.13:48:08.86#ibcon#read 5, iclass 35, count 2 2006.257.13:48:08.86#ibcon#about to read 6, iclass 35, count 2 2006.257.13:48:08.86#ibcon#read 6, iclass 35, count 2 2006.257.13:48:08.86#ibcon#end of sib2, iclass 35, count 2 2006.257.13:48:08.86#ibcon#*after write, iclass 35, count 2 2006.257.13:48:08.86#ibcon#*before return 0, iclass 35, count 2 2006.257.13:48:08.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:48:08.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:48:08.86#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.13:48:08.86#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:08.86#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:48:08.98#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:48:08.98#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:48:08.98#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:48:08.98#ibcon#first serial, iclass 35, count 0 2006.257.13:48:08.98#ibcon#enter sib2, iclass 35, count 0 2006.257.13:48:08.98#ibcon#flushed, iclass 35, count 0 2006.257.13:48:08.98#ibcon#about to write, iclass 35, count 0 2006.257.13:48:08.98#ibcon#wrote, iclass 35, count 0 2006.257.13:48:08.98#ibcon#about to read 3, iclass 35, count 0 2006.257.13:48:09.00#ibcon#read 3, iclass 35, count 0 2006.257.13:48:09.00#ibcon#about to read 4, iclass 35, count 0 2006.257.13:48:09.00#ibcon#read 4, iclass 35, count 0 2006.257.13:48:09.00#ibcon#about to read 5, iclass 35, count 0 2006.257.13:48:09.00#ibcon#read 5, iclass 35, count 0 2006.257.13:48:09.00#ibcon#about to read 6, iclass 35, count 0 2006.257.13:48:09.00#ibcon#read 6, iclass 35, count 0 2006.257.13:48:09.00#ibcon#end of sib2, iclass 35, count 0 2006.257.13:48:09.00#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:48:09.00#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:48:09.00#ibcon#[25=USB\r\n] 2006.257.13:48:09.00#ibcon#*before write, iclass 35, count 0 2006.257.13:48:09.00#ibcon#enter sib2, iclass 35, count 0 2006.257.13:48:09.00#ibcon#flushed, iclass 35, count 0 2006.257.13:48:09.00#ibcon#about to write, iclass 35, count 0 2006.257.13:48:09.00#ibcon#wrote, iclass 35, count 0 2006.257.13:48:09.00#ibcon#about to read 3, iclass 35, count 0 2006.257.13:48:09.03#ibcon#read 3, iclass 35, count 0 2006.257.13:48:09.03#ibcon#about to read 4, iclass 35, count 0 2006.257.13:48:09.03#ibcon#read 4, iclass 35, count 0 2006.257.13:48:09.03#ibcon#about to read 5, iclass 35, count 0 2006.257.13:48:09.03#ibcon#read 5, iclass 35, count 0 2006.257.13:48:09.03#ibcon#about to read 6, iclass 35, count 0 2006.257.13:48:09.03#ibcon#read 6, iclass 35, count 0 2006.257.13:48:09.03#ibcon#end of sib2, iclass 35, count 0 2006.257.13:48:09.03#ibcon#*after write, iclass 35, count 0 2006.257.13:48:09.03#ibcon#*before return 0, iclass 35, count 0 2006.257.13:48:09.03#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:48:09.03#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:48:09.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:48:09.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:48:09.03$vck44/vblo=1,629.99 2006.257.13:48:09.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.13:48:09.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.13:48:09.03#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:09.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:48:09.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:48:09.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:48:09.03#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:48:09.03#ibcon#first serial, iclass 37, count 0 2006.257.13:48:09.03#ibcon#enter sib2, iclass 37, count 0 2006.257.13:48:09.03#ibcon#flushed, iclass 37, count 0 2006.257.13:48:09.03#ibcon#about to write, iclass 37, count 0 2006.257.13:48:09.03#ibcon#wrote, iclass 37, count 0 2006.257.13:48:09.03#ibcon#about to read 3, iclass 37, count 0 2006.257.13:48:09.05#ibcon#read 3, iclass 37, count 0 2006.257.13:48:09.05#ibcon#about to read 4, iclass 37, count 0 2006.257.13:48:09.05#ibcon#read 4, iclass 37, count 0 2006.257.13:48:09.05#ibcon#about to read 5, iclass 37, count 0 2006.257.13:48:09.05#ibcon#read 5, iclass 37, count 0 2006.257.13:48:09.05#ibcon#about to read 6, iclass 37, count 0 2006.257.13:48:09.05#ibcon#read 6, iclass 37, count 0 2006.257.13:48:09.05#ibcon#end of sib2, iclass 37, count 0 2006.257.13:48:09.05#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:48:09.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:48:09.05#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:48:09.05#ibcon#*before write, iclass 37, count 0 2006.257.13:48:09.05#ibcon#enter sib2, iclass 37, count 0 2006.257.13:48:09.05#ibcon#flushed, iclass 37, count 0 2006.257.13:48:09.05#ibcon#about to write, iclass 37, count 0 2006.257.13:48:09.05#ibcon#wrote, iclass 37, count 0 2006.257.13:48:09.05#ibcon#about to read 3, iclass 37, count 0 2006.257.13:48:09.09#ibcon#read 3, iclass 37, count 0 2006.257.13:48:09.09#ibcon#about to read 4, iclass 37, count 0 2006.257.13:48:09.09#ibcon#read 4, iclass 37, count 0 2006.257.13:48:09.09#ibcon#about to read 5, iclass 37, count 0 2006.257.13:48:09.09#ibcon#read 5, iclass 37, count 0 2006.257.13:48:09.09#ibcon#about to read 6, iclass 37, count 0 2006.257.13:48:09.09#ibcon#read 6, iclass 37, count 0 2006.257.13:48:09.09#ibcon#end of sib2, iclass 37, count 0 2006.257.13:48:09.09#ibcon#*after write, iclass 37, count 0 2006.257.13:48:09.09#ibcon#*before return 0, iclass 37, count 0 2006.257.13:48:09.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:48:09.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:48:09.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:48:09.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:48:09.09$vck44/vb=1,4 2006.257.13:48:09.09#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.13:48:09.09#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.13:48:09.09#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:09.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:48:09.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:48:09.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:48:09.09#ibcon#enter wrdev, iclass 39, count 2 2006.257.13:48:09.09#ibcon#first serial, iclass 39, count 2 2006.257.13:48:09.09#ibcon#enter sib2, iclass 39, count 2 2006.257.13:48:09.09#ibcon#flushed, iclass 39, count 2 2006.257.13:48:09.09#ibcon#about to write, iclass 39, count 2 2006.257.13:48:09.09#ibcon#wrote, iclass 39, count 2 2006.257.13:48:09.09#ibcon#about to read 3, iclass 39, count 2 2006.257.13:48:09.11#ibcon#read 3, iclass 39, count 2 2006.257.13:48:09.11#ibcon#about to read 4, iclass 39, count 2 2006.257.13:48:09.11#ibcon#read 4, iclass 39, count 2 2006.257.13:48:09.11#ibcon#about to read 5, iclass 39, count 2 2006.257.13:48:09.11#ibcon#read 5, iclass 39, count 2 2006.257.13:48:09.11#ibcon#about to read 6, iclass 39, count 2 2006.257.13:48:09.11#ibcon#read 6, iclass 39, count 2 2006.257.13:48:09.11#ibcon#end of sib2, iclass 39, count 2 2006.257.13:48:09.11#ibcon#*mode == 0, iclass 39, count 2 2006.257.13:48:09.11#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.13:48:09.11#ibcon#[27=AT01-04\r\n] 2006.257.13:48:09.11#ibcon#*before write, iclass 39, count 2 2006.257.13:48:09.11#ibcon#enter sib2, iclass 39, count 2 2006.257.13:48:09.11#ibcon#flushed, iclass 39, count 2 2006.257.13:48:09.11#ibcon#about to write, iclass 39, count 2 2006.257.13:48:09.11#ibcon#wrote, iclass 39, count 2 2006.257.13:48:09.11#ibcon#about to read 3, iclass 39, count 2 2006.257.13:48:09.14#ibcon#read 3, iclass 39, count 2 2006.257.13:48:09.14#ibcon#about to read 4, iclass 39, count 2 2006.257.13:48:09.14#ibcon#read 4, iclass 39, count 2 2006.257.13:48:09.14#ibcon#about to read 5, iclass 39, count 2 2006.257.13:48:09.14#ibcon#read 5, iclass 39, count 2 2006.257.13:48:09.14#ibcon#about to read 6, iclass 39, count 2 2006.257.13:48:09.14#ibcon#read 6, iclass 39, count 2 2006.257.13:48:09.14#ibcon#end of sib2, iclass 39, count 2 2006.257.13:48:09.14#ibcon#*after write, iclass 39, count 2 2006.257.13:48:09.14#ibcon#*before return 0, iclass 39, count 2 2006.257.13:48:09.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:48:09.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:48:09.14#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.13:48:09.14#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:09.14#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:48:09.26#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:48:09.26#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:48:09.26#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:48:09.26#ibcon#first serial, iclass 39, count 0 2006.257.13:48:09.26#ibcon#enter sib2, iclass 39, count 0 2006.257.13:48:09.26#ibcon#flushed, iclass 39, count 0 2006.257.13:48:09.26#ibcon#about to write, iclass 39, count 0 2006.257.13:48:09.26#ibcon#wrote, iclass 39, count 0 2006.257.13:48:09.26#ibcon#about to read 3, iclass 39, count 0 2006.257.13:48:09.28#ibcon#read 3, iclass 39, count 0 2006.257.13:48:09.28#ibcon#about to read 4, iclass 39, count 0 2006.257.13:48:09.28#ibcon#read 4, iclass 39, count 0 2006.257.13:48:09.28#ibcon#about to read 5, iclass 39, count 0 2006.257.13:48:09.28#ibcon#read 5, iclass 39, count 0 2006.257.13:48:09.28#ibcon#about to read 6, iclass 39, count 0 2006.257.13:48:09.28#ibcon#read 6, iclass 39, count 0 2006.257.13:48:09.28#ibcon#end of sib2, iclass 39, count 0 2006.257.13:48:09.28#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:48:09.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:48:09.28#ibcon#[27=USB\r\n] 2006.257.13:48:09.28#ibcon#*before write, iclass 39, count 0 2006.257.13:48:09.28#ibcon#enter sib2, iclass 39, count 0 2006.257.13:48:09.28#ibcon#flushed, iclass 39, count 0 2006.257.13:48:09.28#ibcon#about to write, iclass 39, count 0 2006.257.13:48:09.28#ibcon#wrote, iclass 39, count 0 2006.257.13:48:09.28#ibcon#about to read 3, iclass 39, count 0 2006.257.13:48:09.31#ibcon#read 3, iclass 39, count 0 2006.257.13:48:09.31#ibcon#about to read 4, iclass 39, count 0 2006.257.13:48:09.31#ibcon#read 4, iclass 39, count 0 2006.257.13:48:09.31#ibcon#about to read 5, iclass 39, count 0 2006.257.13:48:09.31#ibcon#read 5, iclass 39, count 0 2006.257.13:48:09.31#ibcon#about to read 6, iclass 39, count 0 2006.257.13:48:09.31#ibcon#read 6, iclass 39, count 0 2006.257.13:48:09.31#ibcon#end of sib2, iclass 39, count 0 2006.257.13:48:09.31#ibcon#*after write, iclass 39, count 0 2006.257.13:48:09.31#ibcon#*before return 0, iclass 39, count 0 2006.257.13:48:09.31#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:48:09.31#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:48:09.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:48:09.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:48:09.31$vck44/vblo=2,634.99 2006.257.13:48:09.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.13:48:09.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.13:48:09.31#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:09.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:09.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:09.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:09.31#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:48:09.31#ibcon#first serial, iclass 3, count 0 2006.257.13:48:09.31#ibcon#enter sib2, iclass 3, count 0 2006.257.13:48:09.31#ibcon#flushed, iclass 3, count 0 2006.257.13:48:09.31#ibcon#about to write, iclass 3, count 0 2006.257.13:48:09.31#ibcon#wrote, iclass 3, count 0 2006.257.13:48:09.31#ibcon#about to read 3, iclass 3, count 0 2006.257.13:48:09.33#ibcon#read 3, iclass 3, count 0 2006.257.13:48:09.33#ibcon#about to read 4, iclass 3, count 0 2006.257.13:48:09.33#ibcon#read 4, iclass 3, count 0 2006.257.13:48:09.33#ibcon#about to read 5, iclass 3, count 0 2006.257.13:48:09.33#ibcon#read 5, iclass 3, count 0 2006.257.13:48:09.33#ibcon#about to read 6, iclass 3, count 0 2006.257.13:48:09.33#ibcon#read 6, iclass 3, count 0 2006.257.13:48:09.33#ibcon#end of sib2, iclass 3, count 0 2006.257.13:48:09.33#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:48:09.33#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:48:09.33#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:48:09.33#ibcon#*before write, iclass 3, count 0 2006.257.13:48:09.33#ibcon#enter sib2, iclass 3, count 0 2006.257.13:48:09.33#ibcon#flushed, iclass 3, count 0 2006.257.13:48:09.33#ibcon#about to write, iclass 3, count 0 2006.257.13:48:09.33#ibcon#wrote, iclass 3, count 0 2006.257.13:48:09.33#ibcon#about to read 3, iclass 3, count 0 2006.257.13:48:09.37#ibcon#read 3, iclass 3, count 0 2006.257.13:48:09.37#ibcon#about to read 4, iclass 3, count 0 2006.257.13:48:09.37#ibcon#read 4, iclass 3, count 0 2006.257.13:48:09.37#ibcon#about to read 5, iclass 3, count 0 2006.257.13:48:09.37#ibcon#read 5, iclass 3, count 0 2006.257.13:48:09.37#ibcon#about to read 6, iclass 3, count 0 2006.257.13:48:09.37#ibcon#read 6, iclass 3, count 0 2006.257.13:48:09.37#ibcon#end of sib2, iclass 3, count 0 2006.257.13:48:09.37#ibcon#*after write, iclass 3, count 0 2006.257.13:48:09.37#ibcon#*before return 0, iclass 3, count 0 2006.257.13:48:09.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:09.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:48:09.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:48:09.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:48:09.37$vck44/vb=2,5 2006.257.13:48:09.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.13:48:09.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.13:48:09.37#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:09.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:09.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:09.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:09.43#ibcon#enter wrdev, iclass 5, count 2 2006.257.13:48:09.43#ibcon#first serial, iclass 5, count 2 2006.257.13:48:09.43#ibcon#enter sib2, iclass 5, count 2 2006.257.13:48:09.43#ibcon#flushed, iclass 5, count 2 2006.257.13:48:09.43#ibcon#about to write, iclass 5, count 2 2006.257.13:48:09.43#ibcon#wrote, iclass 5, count 2 2006.257.13:48:09.43#ibcon#about to read 3, iclass 5, count 2 2006.257.13:48:09.45#ibcon#read 3, iclass 5, count 2 2006.257.13:48:09.45#ibcon#about to read 4, iclass 5, count 2 2006.257.13:48:09.45#ibcon#read 4, iclass 5, count 2 2006.257.13:48:09.45#ibcon#about to read 5, iclass 5, count 2 2006.257.13:48:09.45#ibcon#read 5, iclass 5, count 2 2006.257.13:48:09.45#ibcon#about to read 6, iclass 5, count 2 2006.257.13:48:09.45#ibcon#read 6, iclass 5, count 2 2006.257.13:48:09.45#ibcon#end of sib2, iclass 5, count 2 2006.257.13:48:09.45#ibcon#*mode == 0, iclass 5, count 2 2006.257.13:48:09.45#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.13:48:09.45#ibcon#[27=AT02-05\r\n] 2006.257.13:48:09.45#ibcon#*before write, iclass 5, count 2 2006.257.13:48:09.45#ibcon#enter sib2, iclass 5, count 2 2006.257.13:48:09.45#ibcon#flushed, iclass 5, count 2 2006.257.13:48:09.45#ibcon#about to write, iclass 5, count 2 2006.257.13:48:09.45#ibcon#wrote, iclass 5, count 2 2006.257.13:48:09.45#ibcon#about to read 3, iclass 5, count 2 2006.257.13:48:09.48#ibcon#read 3, iclass 5, count 2 2006.257.13:48:09.48#ibcon#about to read 4, iclass 5, count 2 2006.257.13:48:09.48#ibcon#read 4, iclass 5, count 2 2006.257.13:48:09.48#ibcon#about to read 5, iclass 5, count 2 2006.257.13:48:09.48#ibcon#read 5, iclass 5, count 2 2006.257.13:48:09.48#ibcon#about to read 6, iclass 5, count 2 2006.257.13:48:09.48#ibcon#read 6, iclass 5, count 2 2006.257.13:48:09.48#ibcon#end of sib2, iclass 5, count 2 2006.257.13:48:09.48#ibcon#*after write, iclass 5, count 2 2006.257.13:48:09.48#ibcon#*before return 0, iclass 5, count 2 2006.257.13:48:09.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:09.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:48:09.54#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.13:48:09.54#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:09.54#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:09.66#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:09.66#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:09.66#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:48:09.66#ibcon#first serial, iclass 5, count 0 2006.257.13:48:09.66#ibcon#enter sib2, iclass 5, count 0 2006.257.13:48:09.66#ibcon#flushed, iclass 5, count 0 2006.257.13:48:09.66#ibcon#about to write, iclass 5, count 0 2006.257.13:48:09.66#ibcon#wrote, iclass 5, count 0 2006.257.13:48:09.66#ibcon#about to read 3, iclass 5, count 0 2006.257.13:48:09.68#ibcon#read 3, iclass 5, count 0 2006.257.13:48:09.68#ibcon#about to read 4, iclass 5, count 0 2006.257.13:48:09.68#ibcon#read 4, iclass 5, count 0 2006.257.13:48:09.68#ibcon#about to read 5, iclass 5, count 0 2006.257.13:48:09.68#ibcon#read 5, iclass 5, count 0 2006.257.13:48:09.68#ibcon#about to read 6, iclass 5, count 0 2006.257.13:48:09.68#ibcon#read 6, iclass 5, count 0 2006.257.13:48:09.68#ibcon#end of sib2, iclass 5, count 0 2006.257.13:48:09.68#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:48:09.68#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:48:09.68#ibcon#[27=USB\r\n] 2006.257.13:48:09.68#ibcon#*before write, iclass 5, count 0 2006.257.13:48:09.68#ibcon#enter sib2, iclass 5, count 0 2006.257.13:48:09.68#ibcon#flushed, iclass 5, count 0 2006.257.13:48:09.68#ibcon#about to write, iclass 5, count 0 2006.257.13:48:09.68#ibcon#wrote, iclass 5, count 0 2006.257.13:48:09.68#ibcon#about to read 3, iclass 5, count 0 2006.257.13:48:09.71#ibcon#read 3, iclass 5, count 0 2006.257.13:48:09.71#ibcon#about to read 4, iclass 5, count 0 2006.257.13:48:09.71#ibcon#read 4, iclass 5, count 0 2006.257.13:48:09.71#ibcon#about to read 5, iclass 5, count 0 2006.257.13:48:09.71#ibcon#read 5, iclass 5, count 0 2006.257.13:48:09.71#ibcon#about to read 6, iclass 5, count 0 2006.257.13:48:09.71#ibcon#read 6, iclass 5, count 0 2006.257.13:48:09.71#ibcon#end of sib2, iclass 5, count 0 2006.257.13:48:09.71#ibcon#*after write, iclass 5, count 0 2006.257.13:48:09.71#ibcon#*before return 0, iclass 5, count 0 2006.257.13:48:09.71#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:09.71#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:48:09.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:48:09.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:48:09.71$vck44/vblo=3,649.99 2006.257.13:48:09.71#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.13:48:09.71#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.13:48:09.71#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:09.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:09.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:09.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:09.71#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:48:09.71#ibcon#first serial, iclass 7, count 0 2006.257.13:48:09.71#ibcon#enter sib2, iclass 7, count 0 2006.257.13:48:09.71#ibcon#flushed, iclass 7, count 0 2006.257.13:48:09.71#ibcon#about to write, iclass 7, count 0 2006.257.13:48:09.71#ibcon#wrote, iclass 7, count 0 2006.257.13:48:09.71#ibcon#about to read 3, iclass 7, count 0 2006.257.13:48:09.73#ibcon#read 3, iclass 7, count 0 2006.257.13:48:09.73#ibcon#about to read 4, iclass 7, count 0 2006.257.13:48:09.73#ibcon#read 4, iclass 7, count 0 2006.257.13:48:09.73#ibcon#about to read 5, iclass 7, count 0 2006.257.13:48:09.73#ibcon#read 5, iclass 7, count 0 2006.257.13:48:09.73#ibcon#about to read 6, iclass 7, count 0 2006.257.13:48:09.73#ibcon#read 6, iclass 7, count 0 2006.257.13:48:09.73#ibcon#end of sib2, iclass 7, count 0 2006.257.13:48:09.73#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:48:09.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:48:09.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:48:09.73#ibcon#*before write, iclass 7, count 0 2006.257.13:48:09.73#ibcon#enter sib2, iclass 7, count 0 2006.257.13:48:09.73#ibcon#flushed, iclass 7, count 0 2006.257.13:48:09.73#ibcon#about to write, iclass 7, count 0 2006.257.13:48:09.73#ibcon#wrote, iclass 7, count 0 2006.257.13:48:09.73#ibcon#about to read 3, iclass 7, count 0 2006.257.13:48:09.77#ibcon#read 3, iclass 7, count 0 2006.257.13:48:09.77#ibcon#about to read 4, iclass 7, count 0 2006.257.13:48:09.77#ibcon#read 4, iclass 7, count 0 2006.257.13:48:09.77#ibcon#about to read 5, iclass 7, count 0 2006.257.13:48:09.77#ibcon#read 5, iclass 7, count 0 2006.257.13:48:09.77#ibcon#about to read 6, iclass 7, count 0 2006.257.13:48:09.77#ibcon#read 6, iclass 7, count 0 2006.257.13:48:09.77#ibcon#end of sib2, iclass 7, count 0 2006.257.13:48:09.77#ibcon#*after write, iclass 7, count 0 2006.257.13:48:09.77#ibcon#*before return 0, iclass 7, count 0 2006.257.13:48:09.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:09.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:48:09.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:48:09.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:48:09.77$vck44/vb=3,4 2006.257.13:48:09.77#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.13:48:09.77#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.13:48:09.77#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:09.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:09.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:09.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:09.83#ibcon#enter wrdev, iclass 11, count 2 2006.257.13:48:09.83#ibcon#first serial, iclass 11, count 2 2006.257.13:48:09.83#ibcon#enter sib2, iclass 11, count 2 2006.257.13:48:09.83#ibcon#flushed, iclass 11, count 2 2006.257.13:48:09.83#ibcon#about to write, iclass 11, count 2 2006.257.13:48:09.83#ibcon#wrote, iclass 11, count 2 2006.257.13:48:09.83#ibcon#about to read 3, iclass 11, count 2 2006.257.13:48:09.85#ibcon#read 3, iclass 11, count 2 2006.257.13:48:09.85#ibcon#about to read 4, iclass 11, count 2 2006.257.13:48:09.85#ibcon#read 4, iclass 11, count 2 2006.257.13:48:09.85#ibcon#about to read 5, iclass 11, count 2 2006.257.13:48:09.85#ibcon#read 5, iclass 11, count 2 2006.257.13:48:09.85#ibcon#about to read 6, iclass 11, count 2 2006.257.13:48:09.85#ibcon#read 6, iclass 11, count 2 2006.257.13:48:09.85#ibcon#end of sib2, iclass 11, count 2 2006.257.13:48:09.85#ibcon#*mode == 0, iclass 11, count 2 2006.257.13:48:09.85#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.13:48:09.85#ibcon#[27=AT03-04\r\n] 2006.257.13:48:09.85#ibcon#*before write, iclass 11, count 2 2006.257.13:48:09.85#ibcon#enter sib2, iclass 11, count 2 2006.257.13:48:09.85#ibcon#flushed, iclass 11, count 2 2006.257.13:48:09.85#ibcon#about to write, iclass 11, count 2 2006.257.13:48:09.85#ibcon#wrote, iclass 11, count 2 2006.257.13:48:09.85#ibcon#about to read 3, iclass 11, count 2 2006.257.13:48:09.88#ibcon#read 3, iclass 11, count 2 2006.257.13:48:09.88#ibcon#about to read 4, iclass 11, count 2 2006.257.13:48:09.88#ibcon#read 4, iclass 11, count 2 2006.257.13:48:09.88#ibcon#about to read 5, iclass 11, count 2 2006.257.13:48:09.88#ibcon#read 5, iclass 11, count 2 2006.257.13:48:09.88#ibcon#about to read 6, iclass 11, count 2 2006.257.13:48:09.88#ibcon#read 6, iclass 11, count 2 2006.257.13:48:09.88#ibcon#end of sib2, iclass 11, count 2 2006.257.13:48:09.88#ibcon#*after write, iclass 11, count 2 2006.257.13:48:09.88#ibcon#*before return 0, iclass 11, count 2 2006.257.13:48:09.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:09.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:48:09.88#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.13:48:09.88#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:09.88#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:10.00#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:10.00#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:10.00#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:48:10.00#ibcon#first serial, iclass 11, count 0 2006.257.13:48:10.00#ibcon#enter sib2, iclass 11, count 0 2006.257.13:48:10.00#ibcon#flushed, iclass 11, count 0 2006.257.13:48:10.00#ibcon#about to write, iclass 11, count 0 2006.257.13:48:10.00#ibcon#wrote, iclass 11, count 0 2006.257.13:48:10.00#ibcon#about to read 3, iclass 11, count 0 2006.257.13:48:10.02#ibcon#read 3, iclass 11, count 0 2006.257.13:48:10.02#ibcon#about to read 4, iclass 11, count 0 2006.257.13:48:10.02#ibcon#read 4, iclass 11, count 0 2006.257.13:48:10.02#ibcon#about to read 5, iclass 11, count 0 2006.257.13:48:10.02#ibcon#read 5, iclass 11, count 0 2006.257.13:48:10.02#ibcon#about to read 6, iclass 11, count 0 2006.257.13:48:10.02#ibcon#read 6, iclass 11, count 0 2006.257.13:48:10.02#ibcon#end of sib2, iclass 11, count 0 2006.257.13:48:10.02#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:48:10.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:48:10.02#ibcon#[27=USB\r\n] 2006.257.13:48:10.02#ibcon#*before write, iclass 11, count 0 2006.257.13:48:10.02#ibcon#enter sib2, iclass 11, count 0 2006.257.13:48:10.02#ibcon#flushed, iclass 11, count 0 2006.257.13:48:10.02#ibcon#about to write, iclass 11, count 0 2006.257.13:48:10.02#ibcon#wrote, iclass 11, count 0 2006.257.13:48:10.02#ibcon#about to read 3, iclass 11, count 0 2006.257.13:48:10.05#ibcon#read 3, iclass 11, count 0 2006.257.13:48:10.05#ibcon#about to read 4, iclass 11, count 0 2006.257.13:48:10.05#ibcon#read 4, iclass 11, count 0 2006.257.13:48:10.05#ibcon#about to read 5, iclass 11, count 0 2006.257.13:48:10.05#ibcon#read 5, iclass 11, count 0 2006.257.13:48:10.05#ibcon#about to read 6, iclass 11, count 0 2006.257.13:48:10.05#ibcon#read 6, iclass 11, count 0 2006.257.13:48:10.05#ibcon#end of sib2, iclass 11, count 0 2006.257.13:48:10.05#ibcon#*after write, iclass 11, count 0 2006.257.13:48:10.05#ibcon#*before return 0, iclass 11, count 0 2006.257.13:48:10.05#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:10.05#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:48:10.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:48:10.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:48:10.05$vck44/vblo=4,679.99 2006.257.13:48:10.05#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:48:10.05#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:48:10.05#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:10.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:10.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:10.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:10.05#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:48:10.05#ibcon#first serial, iclass 13, count 0 2006.257.13:48:10.05#ibcon#enter sib2, iclass 13, count 0 2006.257.13:48:10.05#ibcon#flushed, iclass 13, count 0 2006.257.13:48:10.05#ibcon#about to write, iclass 13, count 0 2006.257.13:48:10.05#ibcon#wrote, iclass 13, count 0 2006.257.13:48:10.05#ibcon#about to read 3, iclass 13, count 0 2006.257.13:48:10.07#ibcon#read 3, iclass 13, count 0 2006.257.13:48:10.07#ibcon#about to read 4, iclass 13, count 0 2006.257.13:48:10.07#ibcon#read 4, iclass 13, count 0 2006.257.13:48:10.07#ibcon#about to read 5, iclass 13, count 0 2006.257.13:48:10.07#ibcon#read 5, iclass 13, count 0 2006.257.13:48:10.07#ibcon#about to read 6, iclass 13, count 0 2006.257.13:48:10.07#ibcon#read 6, iclass 13, count 0 2006.257.13:48:10.07#ibcon#end of sib2, iclass 13, count 0 2006.257.13:48:10.07#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:48:10.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:48:10.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:48:10.07#ibcon#*before write, iclass 13, count 0 2006.257.13:48:10.07#ibcon#enter sib2, iclass 13, count 0 2006.257.13:48:10.07#ibcon#flushed, iclass 13, count 0 2006.257.13:48:10.07#ibcon#about to write, iclass 13, count 0 2006.257.13:48:10.07#ibcon#wrote, iclass 13, count 0 2006.257.13:48:10.07#ibcon#about to read 3, iclass 13, count 0 2006.257.13:48:10.11#ibcon#read 3, iclass 13, count 0 2006.257.13:48:10.11#ibcon#about to read 4, iclass 13, count 0 2006.257.13:48:10.11#ibcon#read 4, iclass 13, count 0 2006.257.13:48:10.11#ibcon#about to read 5, iclass 13, count 0 2006.257.13:48:10.11#ibcon#read 5, iclass 13, count 0 2006.257.13:48:10.11#ibcon#about to read 6, iclass 13, count 0 2006.257.13:48:10.11#ibcon#read 6, iclass 13, count 0 2006.257.13:48:10.11#ibcon#end of sib2, iclass 13, count 0 2006.257.13:48:10.11#ibcon#*after write, iclass 13, count 0 2006.257.13:48:10.11#ibcon#*before return 0, iclass 13, count 0 2006.257.13:48:10.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:10.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:48:10.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:48:10.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:48:10.11$vck44/vb=4,5 2006.257.13:48:10.11#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.13:48:10.11#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.13:48:10.11#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:10.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:10.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:10.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:10.17#ibcon#enter wrdev, iclass 15, count 2 2006.257.13:48:10.17#ibcon#first serial, iclass 15, count 2 2006.257.13:48:10.17#ibcon#enter sib2, iclass 15, count 2 2006.257.13:48:10.17#ibcon#flushed, iclass 15, count 2 2006.257.13:48:10.17#ibcon#about to write, iclass 15, count 2 2006.257.13:48:10.17#ibcon#wrote, iclass 15, count 2 2006.257.13:48:10.17#ibcon#about to read 3, iclass 15, count 2 2006.257.13:48:10.19#ibcon#read 3, iclass 15, count 2 2006.257.13:48:10.19#ibcon#about to read 4, iclass 15, count 2 2006.257.13:48:10.19#ibcon#read 4, iclass 15, count 2 2006.257.13:48:10.19#ibcon#about to read 5, iclass 15, count 2 2006.257.13:48:10.19#ibcon#read 5, iclass 15, count 2 2006.257.13:48:10.19#ibcon#about to read 6, iclass 15, count 2 2006.257.13:48:10.19#ibcon#read 6, iclass 15, count 2 2006.257.13:48:10.19#ibcon#end of sib2, iclass 15, count 2 2006.257.13:48:10.19#ibcon#*mode == 0, iclass 15, count 2 2006.257.13:48:10.19#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.13:48:10.19#ibcon#[27=AT04-05\r\n] 2006.257.13:48:10.19#ibcon#*before write, iclass 15, count 2 2006.257.13:48:10.19#ibcon#enter sib2, iclass 15, count 2 2006.257.13:48:10.19#ibcon#flushed, iclass 15, count 2 2006.257.13:48:10.19#ibcon#about to write, iclass 15, count 2 2006.257.13:48:10.19#ibcon#wrote, iclass 15, count 2 2006.257.13:48:10.19#ibcon#about to read 3, iclass 15, count 2 2006.257.13:48:10.22#ibcon#read 3, iclass 15, count 2 2006.257.13:48:10.22#ibcon#about to read 4, iclass 15, count 2 2006.257.13:48:10.22#ibcon#read 4, iclass 15, count 2 2006.257.13:48:10.22#ibcon#about to read 5, iclass 15, count 2 2006.257.13:48:10.22#ibcon#read 5, iclass 15, count 2 2006.257.13:48:10.22#ibcon#about to read 6, iclass 15, count 2 2006.257.13:48:10.22#ibcon#read 6, iclass 15, count 2 2006.257.13:48:10.22#ibcon#end of sib2, iclass 15, count 2 2006.257.13:48:10.22#ibcon#*after write, iclass 15, count 2 2006.257.13:48:10.22#ibcon#*before return 0, iclass 15, count 2 2006.257.13:48:10.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:10.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:48:10.22#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.13:48:10.22#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:10.22#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:10.34#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:10.34#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:10.34#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:48:10.34#ibcon#first serial, iclass 15, count 0 2006.257.13:48:10.34#ibcon#enter sib2, iclass 15, count 0 2006.257.13:48:10.34#ibcon#flushed, iclass 15, count 0 2006.257.13:48:10.34#ibcon#about to write, iclass 15, count 0 2006.257.13:48:10.34#ibcon#wrote, iclass 15, count 0 2006.257.13:48:10.34#ibcon#about to read 3, iclass 15, count 0 2006.257.13:48:10.36#ibcon#read 3, iclass 15, count 0 2006.257.13:48:10.36#ibcon#about to read 4, iclass 15, count 0 2006.257.13:48:10.36#ibcon#read 4, iclass 15, count 0 2006.257.13:48:10.36#ibcon#about to read 5, iclass 15, count 0 2006.257.13:48:10.36#ibcon#read 5, iclass 15, count 0 2006.257.13:48:10.36#ibcon#about to read 6, iclass 15, count 0 2006.257.13:48:10.36#ibcon#read 6, iclass 15, count 0 2006.257.13:48:10.36#ibcon#end of sib2, iclass 15, count 0 2006.257.13:48:10.36#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:48:10.36#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:48:10.36#ibcon#[27=USB\r\n] 2006.257.13:48:10.36#ibcon#*before write, iclass 15, count 0 2006.257.13:48:10.36#ibcon#enter sib2, iclass 15, count 0 2006.257.13:48:10.36#ibcon#flushed, iclass 15, count 0 2006.257.13:48:10.36#ibcon#about to write, iclass 15, count 0 2006.257.13:48:10.36#ibcon#wrote, iclass 15, count 0 2006.257.13:48:10.36#ibcon#about to read 3, iclass 15, count 0 2006.257.13:48:10.39#ibcon#read 3, iclass 15, count 0 2006.257.13:48:10.39#ibcon#about to read 4, iclass 15, count 0 2006.257.13:48:10.39#ibcon#read 4, iclass 15, count 0 2006.257.13:48:10.39#ibcon#about to read 5, iclass 15, count 0 2006.257.13:48:10.39#ibcon#read 5, iclass 15, count 0 2006.257.13:48:10.39#ibcon#about to read 6, iclass 15, count 0 2006.257.13:48:10.39#ibcon#read 6, iclass 15, count 0 2006.257.13:48:10.39#ibcon#end of sib2, iclass 15, count 0 2006.257.13:48:10.39#ibcon#*after write, iclass 15, count 0 2006.257.13:48:10.39#ibcon#*before return 0, iclass 15, count 0 2006.257.13:48:10.39#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:10.39#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:48:10.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:48:10.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:48:10.39$vck44/vblo=5,709.99 2006.257.13:48:10.39#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.13:48:10.39#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.13:48:10.39#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:10.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:10.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:10.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:10.39#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:48:10.39#ibcon#first serial, iclass 17, count 0 2006.257.13:48:10.39#ibcon#enter sib2, iclass 17, count 0 2006.257.13:48:10.39#ibcon#flushed, iclass 17, count 0 2006.257.13:48:10.39#ibcon#about to write, iclass 17, count 0 2006.257.13:48:10.39#ibcon#wrote, iclass 17, count 0 2006.257.13:48:10.39#ibcon#about to read 3, iclass 17, count 0 2006.257.13:48:10.41#ibcon#read 3, iclass 17, count 0 2006.257.13:48:10.41#ibcon#about to read 4, iclass 17, count 0 2006.257.13:48:10.41#ibcon#read 4, iclass 17, count 0 2006.257.13:48:10.41#ibcon#about to read 5, iclass 17, count 0 2006.257.13:48:10.41#ibcon#read 5, iclass 17, count 0 2006.257.13:48:10.41#ibcon#about to read 6, iclass 17, count 0 2006.257.13:48:10.41#ibcon#read 6, iclass 17, count 0 2006.257.13:48:10.41#ibcon#end of sib2, iclass 17, count 0 2006.257.13:48:10.41#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:48:10.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:48:10.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:48:10.41#ibcon#*before write, iclass 17, count 0 2006.257.13:48:10.41#ibcon#enter sib2, iclass 17, count 0 2006.257.13:48:10.41#ibcon#flushed, iclass 17, count 0 2006.257.13:48:10.41#ibcon#about to write, iclass 17, count 0 2006.257.13:48:10.41#ibcon#wrote, iclass 17, count 0 2006.257.13:48:10.41#ibcon#about to read 3, iclass 17, count 0 2006.257.13:48:10.45#ibcon#read 3, iclass 17, count 0 2006.257.13:48:10.45#ibcon#about to read 4, iclass 17, count 0 2006.257.13:48:10.45#ibcon#read 4, iclass 17, count 0 2006.257.13:48:10.45#ibcon#about to read 5, iclass 17, count 0 2006.257.13:48:10.45#ibcon#read 5, iclass 17, count 0 2006.257.13:48:10.45#ibcon#about to read 6, iclass 17, count 0 2006.257.13:48:10.45#ibcon#read 6, iclass 17, count 0 2006.257.13:48:10.45#ibcon#end of sib2, iclass 17, count 0 2006.257.13:48:10.45#ibcon#*after write, iclass 17, count 0 2006.257.13:48:10.45#ibcon#*before return 0, iclass 17, count 0 2006.257.13:48:10.45#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:10.45#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:48:10.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:48:10.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:48:10.45$vck44/vb=5,4 2006.257.13:48:10.45#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.13:48:10.45#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.13:48:10.45#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:10.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:10.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:10.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:10.51#ibcon#enter wrdev, iclass 19, count 2 2006.257.13:48:10.51#ibcon#first serial, iclass 19, count 2 2006.257.13:48:10.51#ibcon#enter sib2, iclass 19, count 2 2006.257.13:48:10.51#ibcon#flushed, iclass 19, count 2 2006.257.13:48:10.51#ibcon#about to write, iclass 19, count 2 2006.257.13:48:10.51#ibcon#wrote, iclass 19, count 2 2006.257.13:48:10.51#ibcon#about to read 3, iclass 19, count 2 2006.257.13:48:10.53#ibcon#read 3, iclass 19, count 2 2006.257.13:48:10.53#ibcon#about to read 4, iclass 19, count 2 2006.257.13:48:10.53#ibcon#read 4, iclass 19, count 2 2006.257.13:48:10.53#ibcon#about to read 5, iclass 19, count 2 2006.257.13:48:10.53#ibcon#read 5, iclass 19, count 2 2006.257.13:48:10.53#ibcon#about to read 6, iclass 19, count 2 2006.257.13:48:10.53#ibcon#read 6, iclass 19, count 2 2006.257.13:48:10.53#ibcon#end of sib2, iclass 19, count 2 2006.257.13:48:10.53#ibcon#*mode == 0, iclass 19, count 2 2006.257.13:48:10.53#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.13:48:10.53#ibcon#[27=AT05-04\r\n] 2006.257.13:48:10.53#ibcon#*before write, iclass 19, count 2 2006.257.13:48:10.53#ibcon#enter sib2, iclass 19, count 2 2006.257.13:48:10.53#ibcon#flushed, iclass 19, count 2 2006.257.13:48:10.53#ibcon#about to write, iclass 19, count 2 2006.257.13:48:10.53#ibcon#wrote, iclass 19, count 2 2006.257.13:48:10.53#ibcon#about to read 3, iclass 19, count 2 2006.257.13:48:10.56#ibcon#read 3, iclass 19, count 2 2006.257.13:48:10.56#ibcon#about to read 4, iclass 19, count 2 2006.257.13:48:10.59#ibcon#read 4, iclass 19, count 2 2006.257.13:48:10.59#ibcon#about to read 5, iclass 19, count 2 2006.257.13:48:10.59#ibcon#read 5, iclass 19, count 2 2006.257.13:48:10.59#ibcon#about to read 6, iclass 19, count 2 2006.257.13:48:10.59#ibcon#read 6, iclass 19, count 2 2006.257.13:48:10.59#ibcon#end of sib2, iclass 19, count 2 2006.257.13:48:10.59#ibcon#*after write, iclass 19, count 2 2006.257.13:48:10.59#ibcon#*before return 0, iclass 19, count 2 2006.257.13:48:10.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:10.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:48:10.59#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.13:48:10.59#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:10.59#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:10.71#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:10.71#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:10.71#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:48:10.71#ibcon#first serial, iclass 19, count 0 2006.257.13:48:10.71#ibcon#enter sib2, iclass 19, count 0 2006.257.13:48:10.71#ibcon#flushed, iclass 19, count 0 2006.257.13:48:10.71#ibcon#about to write, iclass 19, count 0 2006.257.13:48:10.71#ibcon#wrote, iclass 19, count 0 2006.257.13:48:10.71#ibcon#about to read 3, iclass 19, count 0 2006.257.13:48:10.73#ibcon#read 3, iclass 19, count 0 2006.257.13:48:10.73#ibcon#about to read 4, iclass 19, count 0 2006.257.13:48:10.73#ibcon#read 4, iclass 19, count 0 2006.257.13:48:10.73#ibcon#about to read 5, iclass 19, count 0 2006.257.13:48:10.73#ibcon#read 5, iclass 19, count 0 2006.257.13:48:10.73#ibcon#about to read 6, iclass 19, count 0 2006.257.13:48:10.73#ibcon#read 6, iclass 19, count 0 2006.257.13:48:10.73#ibcon#end of sib2, iclass 19, count 0 2006.257.13:48:10.73#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:48:10.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:48:10.73#ibcon#[27=USB\r\n] 2006.257.13:48:10.73#ibcon#*before write, iclass 19, count 0 2006.257.13:48:10.73#ibcon#enter sib2, iclass 19, count 0 2006.257.13:48:10.73#ibcon#flushed, iclass 19, count 0 2006.257.13:48:10.73#ibcon#about to write, iclass 19, count 0 2006.257.13:48:10.73#ibcon#wrote, iclass 19, count 0 2006.257.13:48:10.73#ibcon#about to read 3, iclass 19, count 0 2006.257.13:48:10.76#ibcon#read 3, iclass 19, count 0 2006.257.13:48:10.76#ibcon#about to read 4, iclass 19, count 0 2006.257.13:48:10.76#ibcon#read 4, iclass 19, count 0 2006.257.13:48:10.76#ibcon#about to read 5, iclass 19, count 0 2006.257.13:48:10.76#ibcon#read 5, iclass 19, count 0 2006.257.13:48:10.76#ibcon#about to read 6, iclass 19, count 0 2006.257.13:48:10.76#ibcon#read 6, iclass 19, count 0 2006.257.13:48:10.76#ibcon#end of sib2, iclass 19, count 0 2006.257.13:48:10.76#ibcon#*after write, iclass 19, count 0 2006.257.13:48:10.76#ibcon#*before return 0, iclass 19, count 0 2006.257.13:48:10.76#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:10.76#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:48:10.76#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:48:10.76#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:48:10.76$vck44/vblo=6,719.99 2006.257.13:48:10.76#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.13:48:10.76#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.13:48:10.76#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:10.76#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:10.76#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:10.76#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:10.76#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:48:10.76#ibcon#first serial, iclass 21, count 0 2006.257.13:48:10.76#ibcon#enter sib2, iclass 21, count 0 2006.257.13:48:10.76#ibcon#flushed, iclass 21, count 0 2006.257.13:48:10.76#ibcon#about to write, iclass 21, count 0 2006.257.13:48:10.76#ibcon#wrote, iclass 21, count 0 2006.257.13:48:10.76#ibcon#about to read 3, iclass 21, count 0 2006.257.13:48:10.78#ibcon#read 3, iclass 21, count 0 2006.257.13:48:10.78#ibcon#about to read 4, iclass 21, count 0 2006.257.13:48:10.78#ibcon#read 4, iclass 21, count 0 2006.257.13:48:10.78#ibcon#about to read 5, iclass 21, count 0 2006.257.13:48:10.78#ibcon#read 5, iclass 21, count 0 2006.257.13:48:10.78#ibcon#about to read 6, iclass 21, count 0 2006.257.13:48:10.78#ibcon#read 6, iclass 21, count 0 2006.257.13:48:10.78#ibcon#end of sib2, iclass 21, count 0 2006.257.13:48:10.78#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:48:10.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:48:10.78#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:48:10.78#ibcon#*before write, iclass 21, count 0 2006.257.13:48:10.78#ibcon#enter sib2, iclass 21, count 0 2006.257.13:48:10.78#ibcon#flushed, iclass 21, count 0 2006.257.13:48:10.78#ibcon#about to write, iclass 21, count 0 2006.257.13:48:10.78#ibcon#wrote, iclass 21, count 0 2006.257.13:48:10.78#ibcon#about to read 3, iclass 21, count 0 2006.257.13:48:10.82#ibcon#read 3, iclass 21, count 0 2006.257.13:48:10.82#ibcon#about to read 4, iclass 21, count 0 2006.257.13:48:10.82#ibcon#read 4, iclass 21, count 0 2006.257.13:48:10.82#ibcon#about to read 5, iclass 21, count 0 2006.257.13:48:10.82#ibcon#read 5, iclass 21, count 0 2006.257.13:48:10.82#ibcon#about to read 6, iclass 21, count 0 2006.257.13:48:10.82#ibcon#read 6, iclass 21, count 0 2006.257.13:48:10.82#ibcon#end of sib2, iclass 21, count 0 2006.257.13:48:10.82#ibcon#*after write, iclass 21, count 0 2006.257.13:48:10.82#ibcon#*before return 0, iclass 21, count 0 2006.257.13:48:10.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:10.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:48:10.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:48:10.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:48:10.82$vck44/vb=6,4 2006.257.13:48:10.82#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.13:48:10.82#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.13:48:10.82#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:10.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:10.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:10.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:10.88#ibcon#enter wrdev, iclass 23, count 2 2006.257.13:48:10.88#ibcon#first serial, iclass 23, count 2 2006.257.13:48:10.88#ibcon#enter sib2, iclass 23, count 2 2006.257.13:48:10.88#ibcon#flushed, iclass 23, count 2 2006.257.13:48:10.88#ibcon#about to write, iclass 23, count 2 2006.257.13:48:10.88#ibcon#wrote, iclass 23, count 2 2006.257.13:48:10.88#ibcon#about to read 3, iclass 23, count 2 2006.257.13:48:10.90#ibcon#read 3, iclass 23, count 2 2006.257.13:48:10.90#ibcon#about to read 4, iclass 23, count 2 2006.257.13:48:10.90#ibcon#read 4, iclass 23, count 2 2006.257.13:48:10.90#ibcon#about to read 5, iclass 23, count 2 2006.257.13:48:10.90#ibcon#read 5, iclass 23, count 2 2006.257.13:48:10.90#ibcon#about to read 6, iclass 23, count 2 2006.257.13:48:10.90#ibcon#read 6, iclass 23, count 2 2006.257.13:48:10.90#ibcon#end of sib2, iclass 23, count 2 2006.257.13:48:10.90#ibcon#*mode == 0, iclass 23, count 2 2006.257.13:48:10.90#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.13:48:10.90#ibcon#[27=AT06-04\r\n] 2006.257.13:48:10.90#ibcon#*before write, iclass 23, count 2 2006.257.13:48:10.90#ibcon#enter sib2, iclass 23, count 2 2006.257.13:48:10.90#ibcon#flushed, iclass 23, count 2 2006.257.13:48:10.90#ibcon#about to write, iclass 23, count 2 2006.257.13:48:10.90#ibcon#wrote, iclass 23, count 2 2006.257.13:48:10.90#ibcon#about to read 3, iclass 23, count 2 2006.257.13:48:10.93#ibcon#read 3, iclass 23, count 2 2006.257.13:48:10.93#ibcon#about to read 4, iclass 23, count 2 2006.257.13:48:10.93#ibcon#read 4, iclass 23, count 2 2006.257.13:48:10.93#ibcon#about to read 5, iclass 23, count 2 2006.257.13:48:10.93#ibcon#read 5, iclass 23, count 2 2006.257.13:48:10.93#ibcon#about to read 6, iclass 23, count 2 2006.257.13:48:10.93#ibcon#read 6, iclass 23, count 2 2006.257.13:48:10.93#ibcon#end of sib2, iclass 23, count 2 2006.257.13:48:10.93#ibcon#*after write, iclass 23, count 2 2006.257.13:48:10.93#ibcon#*before return 0, iclass 23, count 2 2006.257.13:48:10.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:10.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:48:10.93#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.13:48:10.93#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:10.93#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:11.05#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:11.05#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:11.05#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:48:11.05#ibcon#first serial, iclass 23, count 0 2006.257.13:48:11.05#ibcon#enter sib2, iclass 23, count 0 2006.257.13:48:11.05#ibcon#flushed, iclass 23, count 0 2006.257.13:48:11.05#ibcon#about to write, iclass 23, count 0 2006.257.13:48:11.05#ibcon#wrote, iclass 23, count 0 2006.257.13:48:11.05#ibcon#about to read 3, iclass 23, count 0 2006.257.13:48:11.07#ibcon#read 3, iclass 23, count 0 2006.257.13:48:11.07#ibcon#about to read 4, iclass 23, count 0 2006.257.13:48:11.07#ibcon#read 4, iclass 23, count 0 2006.257.13:48:11.07#ibcon#about to read 5, iclass 23, count 0 2006.257.13:48:11.07#ibcon#read 5, iclass 23, count 0 2006.257.13:48:11.07#ibcon#about to read 6, iclass 23, count 0 2006.257.13:48:11.07#ibcon#read 6, iclass 23, count 0 2006.257.13:48:11.07#ibcon#end of sib2, iclass 23, count 0 2006.257.13:48:11.07#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:48:11.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:48:11.07#ibcon#[27=USB\r\n] 2006.257.13:48:11.07#ibcon#*before write, iclass 23, count 0 2006.257.13:48:11.07#ibcon#enter sib2, iclass 23, count 0 2006.257.13:48:11.07#ibcon#flushed, iclass 23, count 0 2006.257.13:48:11.07#ibcon#about to write, iclass 23, count 0 2006.257.13:48:11.07#ibcon#wrote, iclass 23, count 0 2006.257.13:48:11.07#ibcon#about to read 3, iclass 23, count 0 2006.257.13:48:11.10#ibcon#read 3, iclass 23, count 0 2006.257.13:48:11.10#ibcon#about to read 4, iclass 23, count 0 2006.257.13:48:11.10#ibcon#read 4, iclass 23, count 0 2006.257.13:48:11.10#ibcon#about to read 5, iclass 23, count 0 2006.257.13:48:11.10#ibcon#read 5, iclass 23, count 0 2006.257.13:48:11.10#ibcon#about to read 6, iclass 23, count 0 2006.257.13:48:11.10#ibcon#read 6, iclass 23, count 0 2006.257.13:48:11.10#ibcon#end of sib2, iclass 23, count 0 2006.257.13:48:11.10#ibcon#*after write, iclass 23, count 0 2006.257.13:48:11.10#ibcon#*before return 0, iclass 23, count 0 2006.257.13:48:11.10#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:11.10#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:48:11.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:48:11.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:48:11.10$vck44/vblo=7,734.99 2006.257.13:48:11.10#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.13:48:11.10#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.13:48:11.10#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:11.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:11.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:11.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:11.10#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:48:11.10#ibcon#first serial, iclass 25, count 0 2006.257.13:48:11.10#ibcon#enter sib2, iclass 25, count 0 2006.257.13:48:11.10#ibcon#flushed, iclass 25, count 0 2006.257.13:48:11.10#ibcon#about to write, iclass 25, count 0 2006.257.13:48:11.10#ibcon#wrote, iclass 25, count 0 2006.257.13:48:11.10#ibcon#about to read 3, iclass 25, count 0 2006.257.13:48:11.12#ibcon#read 3, iclass 25, count 0 2006.257.13:48:11.12#ibcon#about to read 4, iclass 25, count 0 2006.257.13:48:11.12#ibcon#read 4, iclass 25, count 0 2006.257.13:48:11.12#ibcon#about to read 5, iclass 25, count 0 2006.257.13:48:11.12#ibcon#read 5, iclass 25, count 0 2006.257.13:48:11.12#ibcon#about to read 6, iclass 25, count 0 2006.257.13:48:11.12#ibcon#read 6, iclass 25, count 0 2006.257.13:48:11.12#ibcon#end of sib2, iclass 25, count 0 2006.257.13:48:11.12#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:48:11.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:48:11.12#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:48:11.12#ibcon#*before write, iclass 25, count 0 2006.257.13:48:11.12#ibcon#enter sib2, iclass 25, count 0 2006.257.13:48:11.12#ibcon#flushed, iclass 25, count 0 2006.257.13:48:11.12#ibcon#about to write, iclass 25, count 0 2006.257.13:48:11.12#ibcon#wrote, iclass 25, count 0 2006.257.13:48:11.12#ibcon#about to read 3, iclass 25, count 0 2006.257.13:48:11.16#ibcon#read 3, iclass 25, count 0 2006.257.13:48:11.16#ibcon#about to read 4, iclass 25, count 0 2006.257.13:48:11.16#ibcon#read 4, iclass 25, count 0 2006.257.13:48:11.16#ibcon#about to read 5, iclass 25, count 0 2006.257.13:48:11.16#ibcon#read 5, iclass 25, count 0 2006.257.13:48:11.16#ibcon#about to read 6, iclass 25, count 0 2006.257.13:48:11.16#ibcon#read 6, iclass 25, count 0 2006.257.13:48:11.16#ibcon#end of sib2, iclass 25, count 0 2006.257.13:48:11.16#ibcon#*after write, iclass 25, count 0 2006.257.13:48:11.16#ibcon#*before return 0, iclass 25, count 0 2006.257.13:48:11.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:11.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:48:11.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:48:11.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:48:11.16$vck44/vb=7,4 2006.257.13:48:11.16#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.13:48:11.16#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.13:48:11.16#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:11.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:11.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:11.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:11.22#ibcon#enter wrdev, iclass 27, count 2 2006.257.13:48:11.22#ibcon#first serial, iclass 27, count 2 2006.257.13:48:11.22#ibcon#enter sib2, iclass 27, count 2 2006.257.13:48:11.22#ibcon#flushed, iclass 27, count 2 2006.257.13:48:11.22#ibcon#about to write, iclass 27, count 2 2006.257.13:48:11.22#ibcon#wrote, iclass 27, count 2 2006.257.13:48:11.22#ibcon#about to read 3, iclass 27, count 2 2006.257.13:48:11.24#ibcon#read 3, iclass 27, count 2 2006.257.13:48:11.24#ibcon#about to read 4, iclass 27, count 2 2006.257.13:48:11.24#ibcon#read 4, iclass 27, count 2 2006.257.13:48:11.24#ibcon#about to read 5, iclass 27, count 2 2006.257.13:48:11.24#ibcon#read 5, iclass 27, count 2 2006.257.13:48:11.24#ibcon#about to read 6, iclass 27, count 2 2006.257.13:48:11.24#ibcon#read 6, iclass 27, count 2 2006.257.13:48:11.24#ibcon#end of sib2, iclass 27, count 2 2006.257.13:48:11.24#ibcon#*mode == 0, iclass 27, count 2 2006.257.13:48:11.24#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.13:48:11.24#ibcon#[27=AT07-04\r\n] 2006.257.13:48:11.24#ibcon#*before write, iclass 27, count 2 2006.257.13:48:11.24#ibcon#enter sib2, iclass 27, count 2 2006.257.13:48:11.24#ibcon#flushed, iclass 27, count 2 2006.257.13:48:11.24#ibcon#about to write, iclass 27, count 2 2006.257.13:48:11.24#ibcon#wrote, iclass 27, count 2 2006.257.13:48:11.24#ibcon#about to read 3, iclass 27, count 2 2006.257.13:48:11.27#ibcon#read 3, iclass 27, count 2 2006.257.13:48:11.27#ibcon#about to read 4, iclass 27, count 2 2006.257.13:48:11.27#ibcon#read 4, iclass 27, count 2 2006.257.13:48:11.27#ibcon#about to read 5, iclass 27, count 2 2006.257.13:48:11.27#ibcon#read 5, iclass 27, count 2 2006.257.13:48:11.27#ibcon#about to read 6, iclass 27, count 2 2006.257.13:48:11.27#ibcon#read 6, iclass 27, count 2 2006.257.13:48:11.27#ibcon#end of sib2, iclass 27, count 2 2006.257.13:48:11.27#ibcon#*after write, iclass 27, count 2 2006.257.13:48:11.27#ibcon#*before return 0, iclass 27, count 2 2006.257.13:48:11.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:11.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:48:11.27#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.13:48:11.27#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:11.27#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:11.39#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:11.39#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:11.39#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:48:11.39#ibcon#first serial, iclass 27, count 0 2006.257.13:48:11.39#ibcon#enter sib2, iclass 27, count 0 2006.257.13:48:11.39#ibcon#flushed, iclass 27, count 0 2006.257.13:48:11.39#ibcon#about to write, iclass 27, count 0 2006.257.13:48:11.39#ibcon#wrote, iclass 27, count 0 2006.257.13:48:11.39#ibcon#about to read 3, iclass 27, count 0 2006.257.13:48:11.41#ibcon#read 3, iclass 27, count 0 2006.257.13:48:11.41#ibcon#about to read 4, iclass 27, count 0 2006.257.13:48:11.41#ibcon#read 4, iclass 27, count 0 2006.257.13:48:11.41#ibcon#about to read 5, iclass 27, count 0 2006.257.13:48:11.41#ibcon#read 5, iclass 27, count 0 2006.257.13:48:11.41#ibcon#about to read 6, iclass 27, count 0 2006.257.13:48:11.41#ibcon#read 6, iclass 27, count 0 2006.257.13:48:11.41#ibcon#end of sib2, iclass 27, count 0 2006.257.13:48:11.41#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:48:11.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:48:11.41#ibcon#[27=USB\r\n] 2006.257.13:48:11.41#ibcon#*before write, iclass 27, count 0 2006.257.13:48:11.41#ibcon#enter sib2, iclass 27, count 0 2006.257.13:48:11.41#ibcon#flushed, iclass 27, count 0 2006.257.13:48:11.41#ibcon#about to write, iclass 27, count 0 2006.257.13:48:11.41#ibcon#wrote, iclass 27, count 0 2006.257.13:48:11.41#ibcon#about to read 3, iclass 27, count 0 2006.257.13:48:11.44#ibcon#read 3, iclass 27, count 0 2006.257.13:48:11.44#ibcon#about to read 4, iclass 27, count 0 2006.257.13:48:11.44#ibcon#read 4, iclass 27, count 0 2006.257.13:48:11.44#ibcon#about to read 5, iclass 27, count 0 2006.257.13:48:11.44#ibcon#read 5, iclass 27, count 0 2006.257.13:48:11.44#ibcon#about to read 6, iclass 27, count 0 2006.257.13:48:11.44#ibcon#read 6, iclass 27, count 0 2006.257.13:48:11.44#ibcon#end of sib2, iclass 27, count 0 2006.257.13:48:11.44#ibcon#*after write, iclass 27, count 0 2006.257.13:48:11.44#ibcon#*before return 0, iclass 27, count 0 2006.257.13:48:11.44#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:11.44#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:48:11.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:48:11.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:48:11.44$vck44/vblo=8,744.99 2006.257.13:48:11.44#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.13:48:11.44#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.13:48:11.44#ibcon#ireg 17 cls_cnt 0 2006.257.13:48:11.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:11.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:11.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:11.44#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:48:11.44#ibcon#first serial, iclass 29, count 0 2006.257.13:48:11.44#ibcon#enter sib2, iclass 29, count 0 2006.257.13:48:11.44#ibcon#flushed, iclass 29, count 0 2006.257.13:48:11.44#ibcon#about to write, iclass 29, count 0 2006.257.13:48:11.44#ibcon#wrote, iclass 29, count 0 2006.257.13:48:11.44#ibcon#about to read 3, iclass 29, count 0 2006.257.13:48:11.46#ibcon#read 3, iclass 29, count 0 2006.257.13:48:11.46#ibcon#about to read 4, iclass 29, count 0 2006.257.13:48:11.46#ibcon#read 4, iclass 29, count 0 2006.257.13:48:11.46#ibcon#about to read 5, iclass 29, count 0 2006.257.13:48:11.46#ibcon#read 5, iclass 29, count 0 2006.257.13:48:11.46#ibcon#about to read 6, iclass 29, count 0 2006.257.13:48:11.46#ibcon#read 6, iclass 29, count 0 2006.257.13:48:11.46#ibcon#end of sib2, iclass 29, count 0 2006.257.13:48:11.46#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:48:11.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:48:11.46#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:48:11.46#ibcon#*before write, iclass 29, count 0 2006.257.13:48:11.46#ibcon#enter sib2, iclass 29, count 0 2006.257.13:48:11.46#ibcon#flushed, iclass 29, count 0 2006.257.13:48:11.46#ibcon#about to write, iclass 29, count 0 2006.257.13:48:11.46#ibcon#wrote, iclass 29, count 0 2006.257.13:48:11.46#ibcon#about to read 3, iclass 29, count 0 2006.257.13:48:11.50#ibcon#read 3, iclass 29, count 0 2006.257.13:48:11.50#ibcon#about to read 4, iclass 29, count 0 2006.257.13:48:11.50#ibcon#read 4, iclass 29, count 0 2006.257.13:48:11.50#ibcon#about to read 5, iclass 29, count 0 2006.257.13:48:11.50#ibcon#read 5, iclass 29, count 0 2006.257.13:48:11.50#ibcon#about to read 6, iclass 29, count 0 2006.257.13:48:11.50#ibcon#read 6, iclass 29, count 0 2006.257.13:48:11.50#ibcon#end of sib2, iclass 29, count 0 2006.257.13:48:11.50#ibcon#*after write, iclass 29, count 0 2006.257.13:48:11.50#ibcon#*before return 0, iclass 29, count 0 2006.257.13:48:11.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:11.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:48:11.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:48:11.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:48:11.50$vck44/vb=8,4 2006.257.13:48:11.50#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.13:48:11.50#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.13:48:11.50#ibcon#ireg 11 cls_cnt 2 2006.257.13:48:11.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:11.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:11.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:11.56#ibcon#enter wrdev, iclass 31, count 2 2006.257.13:48:11.56#ibcon#first serial, iclass 31, count 2 2006.257.13:48:11.56#ibcon#enter sib2, iclass 31, count 2 2006.257.13:48:11.56#ibcon#flushed, iclass 31, count 2 2006.257.13:48:11.56#ibcon#about to write, iclass 31, count 2 2006.257.13:48:11.56#ibcon#wrote, iclass 31, count 2 2006.257.13:48:11.56#ibcon#about to read 3, iclass 31, count 2 2006.257.13:48:11.58#ibcon#read 3, iclass 31, count 2 2006.257.13:48:11.58#ibcon#about to read 4, iclass 31, count 2 2006.257.13:48:11.58#ibcon#read 4, iclass 31, count 2 2006.257.13:48:11.58#ibcon#about to read 5, iclass 31, count 2 2006.257.13:48:11.58#ibcon#read 5, iclass 31, count 2 2006.257.13:48:11.58#ibcon#about to read 6, iclass 31, count 2 2006.257.13:48:11.58#ibcon#read 6, iclass 31, count 2 2006.257.13:48:11.58#ibcon#end of sib2, iclass 31, count 2 2006.257.13:48:11.58#ibcon#*mode == 0, iclass 31, count 2 2006.257.13:48:11.58#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.13:48:11.58#ibcon#[27=AT08-04\r\n] 2006.257.13:48:11.58#ibcon#*before write, iclass 31, count 2 2006.257.13:48:11.58#ibcon#enter sib2, iclass 31, count 2 2006.257.13:48:11.58#ibcon#flushed, iclass 31, count 2 2006.257.13:48:11.58#ibcon#about to write, iclass 31, count 2 2006.257.13:48:11.58#ibcon#wrote, iclass 31, count 2 2006.257.13:48:11.58#ibcon#about to read 3, iclass 31, count 2 2006.257.13:48:11.61#ibcon#read 3, iclass 31, count 2 2006.257.13:48:11.61#ibcon#about to read 4, iclass 31, count 2 2006.257.13:48:11.61#ibcon#read 4, iclass 31, count 2 2006.257.13:48:11.61#ibcon#about to read 5, iclass 31, count 2 2006.257.13:48:11.61#ibcon#read 5, iclass 31, count 2 2006.257.13:48:11.61#ibcon#about to read 6, iclass 31, count 2 2006.257.13:48:11.61#ibcon#read 6, iclass 31, count 2 2006.257.13:48:11.61#ibcon#end of sib2, iclass 31, count 2 2006.257.13:48:11.61#ibcon#*after write, iclass 31, count 2 2006.257.13:48:11.62#ibcon#*before return 0, iclass 31, count 2 2006.257.13:48:11.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:11.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:48:11.62#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.13:48:11.62#ibcon#ireg 7 cls_cnt 0 2006.257.13:48:11.62#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:11.73#abcon#<5=/14 1.6 4.1 17.55 971014.0\r\n> 2006.257.13:48:11.74#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:11.74#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:11.74#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:48:11.74#ibcon#first serial, iclass 31, count 0 2006.257.13:48:11.74#ibcon#enter sib2, iclass 31, count 0 2006.257.13:48:11.74#ibcon#flushed, iclass 31, count 0 2006.257.13:48:11.74#ibcon#about to write, iclass 31, count 0 2006.257.13:48:11.74#ibcon#wrote, iclass 31, count 0 2006.257.13:48:11.74#ibcon#about to read 3, iclass 31, count 0 2006.257.13:48:11.75#abcon#{5=INTERFACE CLEAR} 2006.257.13:48:11.76#ibcon#read 3, iclass 31, count 0 2006.257.13:48:11.76#ibcon#about to read 4, iclass 31, count 0 2006.257.13:48:11.76#ibcon#read 4, iclass 31, count 0 2006.257.13:48:11.76#ibcon#about to read 5, iclass 31, count 0 2006.257.13:48:11.76#ibcon#read 5, iclass 31, count 0 2006.257.13:48:11.76#ibcon#about to read 6, iclass 31, count 0 2006.257.13:48:11.76#ibcon#read 6, iclass 31, count 0 2006.257.13:48:11.76#ibcon#end of sib2, iclass 31, count 0 2006.257.13:48:11.76#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:48:11.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:48:11.76#ibcon#[27=USB\r\n] 2006.257.13:48:11.76#ibcon#*before write, iclass 31, count 0 2006.257.13:48:11.76#ibcon#enter sib2, iclass 31, count 0 2006.257.13:48:11.76#ibcon#flushed, iclass 31, count 0 2006.257.13:48:11.76#ibcon#about to write, iclass 31, count 0 2006.257.13:48:11.76#ibcon#wrote, iclass 31, count 0 2006.257.13:48:11.76#ibcon#about to read 3, iclass 31, count 0 2006.257.13:48:11.79#ibcon#read 3, iclass 31, count 0 2006.257.13:48:11.79#ibcon#about to read 4, iclass 31, count 0 2006.257.13:48:11.79#ibcon#read 4, iclass 31, count 0 2006.257.13:48:11.79#ibcon#about to read 5, iclass 31, count 0 2006.257.13:48:11.79#ibcon#read 5, iclass 31, count 0 2006.257.13:48:11.79#ibcon#about to read 6, iclass 31, count 0 2006.257.13:48:11.79#ibcon#read 6, iclass 31, count 0 2006.257.13:48:11.79#ibcon#end of sib2, iclass 31, count 0 2006.257.13:48:11.79#ibcon#*after write, iclass 31, count 0 2006.257.13:48:11.79#ibcon#*before return 0, iclass 31, count 0 2006.257.13:48:11.79#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:11.79#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:48:11.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:48:11.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:48:11.79$vck44/vabw=wide 2006.257.13:48:11.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.13:48:11.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.13:48:11.79#ibcon#ireg 8 cls_cnt 0 2006.257.13:48:11.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:48:11.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:48:11.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:48:11.79#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:48:11.79#ibcon#first serial, iclass 36, count 0 2006.257.13:48:11.79#ibcon#enter sib2, iclass 36, count 0 2006.257.13:48:11.79#ibcon#flushed, iclass 36, count 0 2006.257.13:48:11.79#ibcon#about to write, iclass 36, count 0 2006.257.13:48:11.79#ibcon#wrote, iclass 36, count 0 2006.257.13:48:11.79#ibcon#about to read 3, iclass 36, count 0 2006.257.13:48:11.81#ibcon#read 3, iclass 36, count 0 2006.257.13:48:11.81#ibcon#about to read 4, iclass 36, count 0 2006.257.13:48:11.81#ibcon#read 4, iclass 36, count 0 2006.257.13:48:11.81#ibcon#about to read 5, iclass 36, count 0 2006.257.13:48:11.81#ibcon#read 5, iclass 36, count 0 2006.257.13:48:11.81#ibcon#about to read 6, iclass 36, count 0 2006.257.13:48:11.81#ibcon#read 6, iclass 36, count 0 2006.257.13:48:11.81#ibcon#end of sib2, iclass 36, count 0 2006.257.13:48:11.81#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:48:11.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:48:11.81#ibcon#[25=BW32\r\n] 2006.257.13:48:11.81#ibcon#*before write, iclass 36, count 0 2006.257.13:48:11.81#ibcon#enter sib2, iclass 36, count 0 2006.257.13:48:11.81#ibcon#flushed, iclass 36, count 0 2006.257.13:48:11.81#ibcon#about to write, iclass 36, count 0 2006.257.13:48:11.81#ibcon#wrote, iclass 36, count 0 2006.257.13:48:11.81#ibcon#about to read 3, iclass 36, count 0 2006.257.13:48:11.81#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:48:11.84#ibcon#read 3, iclass 36, count 0 2006.257.13:48:11.84#ibcon#about to read 4, iclass 36, count 0 2006.257.13:48:11.84#ibcon#read 4, iclass 36, count 0 2006.257.13:48:11.84#ibcon#about to read 5, iclass 36, count 0 2006.257.13:48:11.84#ibcon#read 5, iclass 36, count 0 2006.257.13:48:11.84#ibcon#about to read 6, iclass 36, count 0 2006.257.13:48:11.84#ibcon#read 6, iclass 36, count 0 2006.257.13:48:11.84#ibcon#end of sib2, iclass 36, count 0 2006.257.13:48:11.84#ibcon#*after write, iclass 36, count 0 2006.257.13:48:11.84#ibcon#*before return 0, iclass 36, count 0 2006.257.13:48:11.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:48:11.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:48:11.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:48:11.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:48:11.84$vck44/vbbw=wide 2006.257.13:48:11.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:48:11.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:48:11.84#ibcon#ireg 8 cls_cnt 0 2006.257.13:48:11.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:48:11.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:48:11.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:48:11.91#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:48:11.91#ibcon#first serial, iclass 39, count 0 2006.257.13:48:11.91#ibcon#enter sib2, iclass 39, count 0 2006.257.13:48:11.91#ibcon#flushed, iclass 39, count 0 2006.257.13:48:11.91#ibcon#about to write, iclass 39, count 0 2006.257.13:48:11.91#ibcon#wrote, iclass 39, count 0 2006.257.13:48:11.91#ibcon#about to read 3, iclass 39, count 0 2006.257.13:48:11.93#ibcon#read 3, iclass 39, count 0 2006.257.13:48:11.93#ibcon#about to read 4, iclass 39, count 0 2006.257.13:48:11.93#ibcon#read 4, iclass 39, count 0 2006.257.13:48:11.93#ibcon#about to read 5, iclass 39, count 0 2006.257.13:48:11.93#ibcon#read 5, iclass 39, count 0 2006.257.13:48:11.93#ibcon#about to read 6, iclass 39, count 0 2006.257.13:48:11.93#ibcon#read 6, iclass 39, count 0 2006.257.13:48:11.93#ibcon#end of sib2, iclass 39, count 0 2006.257.13:48:11.93#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:48:11.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:48:11.93#ibcon#[27=BW32\r\n] 2006.257.13:48:11.93#ibcon#*before write, iclass 39, count 0 2006.257.13:48:11.93#ibcon#enter sib2, iclass 39, count 0 2006.257.13:48:11.93#ibcon#flushed, iclass 39, count 0 2006.257.13:48:11.93#ibcon#about to write, iclass 39, count 0 2006.257.13:48:11.93#ibcon#wrote, iclass 39, count 0 2006.257.13:48:11.93#ibcon#about to read 3, iclass 39, count 0 2006.257.13:48:11.96#ibcon#read 3, iclass 39, count 0 2006.257.13:48:11.96#ibcon#about to read 4, iclass 39, count 0 2006.257.13:48:11.96#ibcon#read 4, iclass 39, count 0 2006.257.13:48:11.96#ibcon#about to read 5, iclass 39, count 0 2006.257.13:48:11.96#ibcon#read 5, iclass 39, count 0 2006.257.13:48:11.96#ibcon#about to read 6, iclass 39, count 0 2006.257.13:48:11.96#ibcon#read 6, iclass 39, count 0 2006.257.13:48:11.96#ibcon#end of sib2, iclass 39, count 0 2006.257.13:48:11.96#ibcon#*after write, iclass 39, count 0 2006.257.13:48:11.96#ibcon#*before return 0, iclass 39, count 0 2006.257.13:48:11.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:48:11.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:48:11.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:48:11.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:48:11.96$setupk4/ifdk4 2006.257.13:48:11.96$ifdk4/lo= 2006.257.13:48:11.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:48:11.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:48:11.96$ifdk4/patch= 2006.257.13:48:11.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:48:11.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:48:11.96$setupk4/!*+20s 2006.257.13:48:21.90#abcon#<5=/14 1.6 4.1 17.55 971014.0\r\n> 2006.257.13:48:21.92#abcon#{5=INTERFACE CLEAR} 2006.257.13:48:21.98#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:48:26.31$setupk4/"tpicd 2006.257.13:48:26.31$setupk4/echo=off 2006.257.13:48:26.31$setupk4/xlog=off 2006.257.13:48:26.31:!2006.257.13:48:49 2006.257.13:48:35.13#trakl#Source acquired 2006.257.13:48:37.13#flagr#flagr/antenna,acquired 2006.257.13:48:49.00:preob 2006.257.13:48:50.14/onsource/TRACKING 2006.257.13:48:50.14:!2006.257.13:48:59 2006.257.13:48:59.00:"tape 2006.257.13:48:59.00:"st=record 2006.257.13:48:59.00:data_valid=on 2006.257.13:48:59.00:midob 2006.257.13:48:59.13/onsource/TRACKING 2006.257.13:48:59.13/wx/17.56,1014.0,97 2006.257.13:48:59.20/cable/+6.4827E-03 2006.257.13:49:00.29/va/01,08,usb,yes,36,38 2006.257.13:49:00.29/va/02,07,usb,yes,39,39 2006.257.13:49:00.29/va/03,08,usb,yes,35,37 2006.257.13:49:00.29/va/04,07,usb,yes,40,42 2006.257.13:49:00.29/va/05,04,usb,yes,36,36 2006.257.13:49:00.29/va/06,04,usb,yes,40,39 2006.257.13:49:00.29/va/07,04,usb,yes,41,41 2006.257.13:49:00.29/va/08,04,usb,yes,34,42 2006.257.13:49:00.52/valo/01,524.99,yes,locked 2006.257.13:49:00.52/valo/02,534.99,yes,locked 2006.257.13:49:00.52/valo/03,564.99,yes,locked 2006.257.13:49:00.52/valo/04,624.99,yes,locked 2006.257.13:49:00.52/valo/05,734.99,yes,locked 2006.257.13:49:00.52/valo/06,814.99,yes,locked 2006.257.13:49:00.52/valo/07,864.99,yes,locked 2006.257.13:49:00.52/valo/08,884.99,yes,locked 2006.257.13:49:01.61/vb/01,04,usb,yes,34,31 2006.257.13:49:01.61/vb/02,05,usb,yes,32,32 2006.257.13:49:01.61/vb/03,04,usb,yes,33,36 2006.257.13:49:01.61/vb/04,05,usb,yes,33,32 2006.257.13:49:01.61/vb/05,04,usb,yes,30,32 2006.257.13:49:01.61/vb/06,04,usb,yes,35,31 2006.257.13:49:01.61/vb/07,04,usb,yes,35,34 2006.257.13:49:01.61/vb/08,04,usb,yes,32,35 2006.257.13:49:01.84/vblo/01,629.99,yes,locked 2006.257.13:49:01.84/vblo/02,634.99,yes,locked 2006.257.13:49:01.84/vblo/03,649.99,yes,locked 2006.257.13:49:01.84/vblo/04,679.99,yes,locked 2006.257.13:49:01.84/vblo/05,709.99,yes,locked 2006.257.13:49:01.84/vblo/06,719.99,yes,locked 2006.257.13:49:01.84/vblo/07,734.99,yes,locked 2006.257.13:49:01.84/vblo/08,744.99,yes,locked 2006.257.13:49:01.99/vabw/8 2006.257.13:49:02.14/vbbw/8 2006.257.13:49:02.23/xfe/off,on,15.5 2006.257.13:49:02.60/ifatt/23,28,28,28 2006.257.13:49:03.08/fmout-gps/S +4.62E-07 2006.257.13:49:03.12:!2006.257.13:49:39 2006.257.13:49:39.00:data_valid=off 2006.257.13:49:39.00:"et 2006.257.13:49:39.00:!+3s 2006.257.13:49:42.02:"tape 2006.257.13:49:42.02:postob 2006.257.13:49:42.12/cable/+6.4819E-03 2006.257.13:49:42.12/wx/17.56,1014.0,97 2006.257.13:49:43.08/fmout-gps/S +4.63E-07 2006.257.13:49:43.08:scan_name=257-1351,jd0609,70 2006.257.13:49:43.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.13:49:44.14#flagr#flagr/antenna,new-source 2006.257.13:49:44.14:checkk5 2006.257.13:49:44.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:49:44.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:49:45.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:49:45.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:49:46.12/chk_obsdata//k5ts1/T2571348??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:49:46.53/chk_obsdata//k5ts2/T2571348??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:49:46.93/chk_obsdata//k5ts3/T2571348??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:49:47.33/chk_obsdata//k5ts4/T2571348??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.13:49:48.07/k5log//k5ts1_log_newline 2006.257.13:49:48.77/k5log//k5ts2_log_newline 2006.257.13:49:49.49/k5log//k5ts3_log_newline 2006.257.13:49:50.21/k5log//k5ts4_log_newline 2006.257.13:49:50.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:49:50.23:setupk4=1 2006.257.13:49:50.24$setupk4/echo=on 2006.257.13:49:50.24$setupk4/pcalon 2006.257.13:49:50.24$pcalon/"no phase cal control is implemented here 2006.257.13:49:50.24$setupk4/"tpicd=stop 2006.257.13:49:50.24$setupk4/"rec=synch_on 2006.257.13:49:50.24$setupk4/"rec_mode=128 2006.257.13:49:50.24$setupk4/!* 2006.257.13:49:50.24$setupk4/recpk4 2006.257.13:49:50.24$recpk4/recpatch= 2006.257.13:49:50.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:49:50.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:49:50.24$setupk4/vck44 2006.257.13:49:50.24$vck44/valo=1,524.99 2006.257.13:49:50.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.13:49:50.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.13:49:50.24#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:50.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:50.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:50.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:50.24#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:49:50.24#ibcon#first serial, iclass 6, count 0 2006.257.13:49:50.24#ibcon#enter sib2, iclass 6, count 0 2006.257.13:49:50.24#ibcon#flushed, iclass 6, count 0 2006.257.13:49:50.24#ibcon#about to write, iclass 6, count 0 2006.257.13:49:50.24#ibcon#wrote, iclass 6, count 0 2006.257.13:49:50.24#ibcon#about to read 3, iclass 6, count 0 2006.257.13:49:50.26#ibcon#read 3, iclass 6, count 0 2006.257.13:49:50.26#ibcon#about to read 4, iclass 6, count 0 2006.257.13:49:50.26#ibcon#read 4, iclass 6, count 0 2006.257.13:49:50.26#ibcon#about to read 5, iclass 6, count 0 2006.257.13:49:50.26#ibcon#read 5, iclass 6, count 0 2006.257.13:49:50.26#ibcon#about to read 6, iclass 6, count 0 2006.257.13:49:50.26#ibcon#read 6, iclass 6, count 0 2006.257.13:49:50.26#ibcon#end of sib2, iclass 6, count 0 2006.257.13:49:50.26#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:49:50.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:49:50.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:49:50.26#ibcon#*before write, iclass 6, count 0 2006.257.13:49:50.26#ibcon#enter sib2, iclass 6, count 0 2006.257.13:49:50.26#ibcon#flushed, iclass 6, count 0 2006.257.13:49:50.26#ibcon#about to write, iclass 6, count 0 2006.257.13:49:50.26#ibcon#wrote, iclass 6, count 0 2006.257.13:49:50.26#ibcon#about to read 3, iclass 6, count 0 2006.257.13:49:50.31#ibcon#read 3, iclass 6, count 0 2006.257.13:49:50.31#ibcon#about to read 4, iclass 6, count 0 2006.257.13:49:50.31#ibcon#read 4, iclass 6, count 0 2006.257.13:49:50.31#ibcon#about to read 5, iclass 6, count 0 2006.257.13:49:50.31#ibcon#read 5, iclass 6, count 0 2006.257.13:49:50.31#ibcon#about to read 6, iclass 6, count 0 2006.257.13:49:50.31#ibcon#read 6, iclass 6, count 0 2006.257.13:49:50.31#ibcon#end of sib2, iclass 6, count 0 2006.257.13:49:50.31#ibcon#*after write, iclass 6, count 0 2006.257.13:49:50.31#ibcon#*before return 0, iclass 6, count 0 2006.257.13:49:50.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:50.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:50.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:49:50.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:49:50.31$vck44/va=1,8 2006.257.13:49:50.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.13:49:50.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.13:49:50.31#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:50.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:50.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:50.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:50.31#ibcon#enter wrdev, iclass 10, count 2 2006.257.13:49:50.31#ibcon#first serial, iclass 10, count 2 2006.257.13:49:50.31#ibcon#enter sib2, iclass 10, count 2 2006.257.13:49:50.31#ibcon#flushed, iclass 10, count 2 2006.257.13:49:50.31#ibcon#about to write, iclass 10, count 2 2006.257.13:49:50.31#ibcon#wrote, iclass 10, count 2 2006.257.13:49:50.31#ibcon#about to read 3, iclass 10, count 2 2006.257.13:49:50.33#ibcon#read 3, iclass 10, count 2 2006.257.13:49:50.33#ibcon#about to read 4, iclass 10, count 2 2006.257.13:49:50.33#ibcon#read 4, iclass 10, count 2 2006.257.13:49:50.33#ibcon#about to read 5, iclass 10, count 2 2006.257.13:49:50.33#ibcon#read 5, iclass 10, count 2 2006.257.13:49:50.33#ibcon#about to read 6, iclass 10, count 2 2006.257.13:49:50.33#ibcon#read 6, iclass 10, count 2 2006.257.13:49:50.33#ibcon#end of sib2, iclass 10, count 2 2006.257.13:49:50.33#ibcon#*mode == 0, iclass 10, count 2 2006.257.13:49:50.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.13:49:50.33#ibcon#[25=AT01-08\r\n] 2006.257.13:49:50.33#ibcon#*before write, iclass 10, count 2 2006.257.13:49:50.33#ibcon#enter sib2, iclass 10, count 2 2006.257.13:49:50.33#ibcon#flushed, iclass 10, count 2 2006.257.13:49:50.33#ibcon#about to write, iclass 10, count 2 2006.257.13:49:50.33#ibcon#wrote, iclass 10, count 2 2006.257.13:49:50.33#ibcon#about to read 3, iclass 10, count 2 2006.257.13:49:50.36#ibcon#read 3, iclass 10, count 2 2006.257.13:49:50.36#ibcon#about to read 4, iclass 10, count 2 2006.257.13:49:50.36#ibcon#read 4, iclass 10, count 2 2006.257.13:49:50.36#ibcon#about to read 5, iclass 10, count 2 2006.257.13:49:50.36#ibcon#read 5, iclass 10, count 2 2006.257.13:49:50.36#ibcon#about to read 6, iclass 10, count 2 2006.257.13:49:50.36#ibcon#read 6, iclass 10, count 2 2006.257.13:49:50.36#ibcon#end of sib2, iclass 10, count 2 2006.257.13:49:50.36#ibcon#*after write, iclass 10, count 2 2006.257.13:49:50.36#ibcon#*before return 0, iclass 10, count 2 2006.257.13:49:50.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:50.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:50.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.13:49:50.36#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:50.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:50.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:50.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:50.48#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:49:50.48#ibcon#first serial, iclass 10, count 0 2006.257.13:49:50.48#ibcon#enter sib2, iclass 10, count 0 2006.257.13:49:50.48#ibcon#flushed, iclass 10, count 0 2006.257.13:49:50.48#ibcon#about to write, iclass 10, count 0 2006.257.13:49:50.48#ibcon#wrote, iclass 10, count 0 2006.257.13:49:50.48#ibcon#about to read 3, iclass 10, count 0 2006.257.13:49:50.50#ibcon#read 3, iclass 10, count 0 2006.257.13:49:50.50#ibcon#about to read 4, iclass 10, count 0 2006.257.13:49:50.50#ibcon#read 4, iclass 10, count 0 2006.257.13:49:50.50#ibcon#about to read 5, iclass 10, count 0 2006.257.13:49:50.50#ibcon#read 5, iclass 10, count 0 2006.257.13:49:50.50#ibcon#about to read 6, iclass 10, count 0 2006.257.13:49:50.50#ibcon#read 6, iclass 10, count 0 2006.257.13:49:50.50#ibcon#end of sib2, iclass 10, count 0 2006.257.13:49:50.50#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:49:50.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:49:50.50#ibcon#[25=USB\r\n] 2006.257.13:49:50.50#ibcon#*before write, iclass 10, count 0 2006.257.13:49:50.50#ibcon#enter sib2, iclass 10, count 0 2006.257.13:49:50.50#ibcon#flushed, iclass 10, count 0 2006.257.13:49:50.50#ibcon#about to write, iclass 10, count 0 2006.257.13:49:50.50#ibcon#wrote, iclass 10, count 0 2006.257.13:49:50.50#ibcon#about to read 3, iclass 10, count 0 2006.257.13:49:50.53#ibcon#read 3, iclass 10, count 0 2006.257.13:49:50.53#ibcon#about to read 4, iclass 10, count 0 2006.257.13:49:50.53#ibcon#read 4, iclass 10, count 0 2006.257.13:49:50.53#ibcon#about to read 5, iclass 10, count 0 2006.257.13:49:50.53#ibcon#read 5, iclass 10, count 0 2006.257.13:49:50.53#ibcon#about to read 6, iclass 10, count 0 2006.257.13:49:50.53#ibcon#read 6, iclass 10, count 0 2006.257.13:49:50.53#ibcon#end of sib2, iclass 10, count 0 2006.257.13:49:50.53#ibcon#*after write, iclass 10, count 0 2006.257.13:49:50.53#ibcon#*before return 0, iclass 10, count 0 2006.257.13:49:50.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:50.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:50.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:49:50.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:49:50.53$vck44/valo=2,534.99 2006.257.13:49:50.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.13:49:50.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.13:49:50.53#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:50.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:49:50.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:49:50.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:49:50.53#ibcon#enter wrdev, iclass 12, count 0 2006.257.13:49:50.53#ibcon#first serial, iclass 12, count 0 2006.257.13:49:50.53#ibcon#enter sib2, iclass 12, count 0 2006.257.13:49:50.53#ibcon#flushed, iclass 12, count 0 2006.257.13:49:50.53#ibcon#about to write, iclass 12, count 0 2006.257.13:49:50.53#ibcon#wrote, iclass 12, count 0 2006.257.13:49:50.53#ibcon#about to read 3, iclass 12, count 0 2006.257.13:49:50.55#ibcon#read 3, iclass 12, count 0 2006.257.13:49:50.55#ibcon#about to read 4, iclass 12, count 0 2006.257.13:49:50.55#ibcon#read 4, iclass 12, count 0 2006.257.13:49:50.55#ibcon#about to read 5, iclass 12, count 0 2006.257.13:49:50.55#ibcon#read 5, iclass 12, count 0 2006.257.13:49:50.55#ibcon#about to read 6, iclass 12, count 0 2006.257.13:49:50.55#ibcon#read 6, iclass 12, count 0 2006.257.13:49:50.55#ibcon#end of sib2, iclass 12, count 0 2006.257.13:49:50.55#ibcon#*mode == 0, iclass 12, count 0 2006.257.13:49:50.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.13:49:50.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:49:50.55#ibcon#*before write, iclass 12, count 0 2006.257.13:49:50.55#ibcon#enter sib2, iclass 12, count 0 2006.257.13:49:50.55#ibcon#flushed, iclass 12, count 0 2006.257.13:49:50.55#ibcon#about to write, iclass 12, count 0 2006.257.13:49:50.55#ibcon#wrote, iclass 12, count 0 2006.257.13:49:50.55#ibcon#about to read 3, iclass 12, count 0 2006.257.13:49:50.59#ibcon#read 3, iclass 12, count 0 2006.257.13:49:50.59#ibcon#about to read 4, iclass 12, count 0 2006.257.13:49:50.59#ibcon#read 4, iclass 12, count 0 2006.257.13:49:50.59#ibcon#about to read 5, iclass 12, count 0 2006.257.13:49:50.59#ibcon#read 5, iclass 12, count 0 2006.257.13:49:50.59#ibcon#about to read 6, iclass 12, count 0 2006.257.13:49:50.59#ibcon#read 6, iclass 12, count 0 2006.257.13:49:50.59#ibcon#end of sib2, iclass 12, count 0 2006.257.13:49:50.59#ibcon#*after write, iclass 12, count 0 2006.257.13:49:50.59#ibcon#*before return 0, iclass 12, count 0 2006.257.13:49:50.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:49:50.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.13:49:50.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.13:49:50.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.13:49:50.59$vck44/va=2,7 2006.257.13:49:50.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.13:49:50.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.13:49:50.59#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:50.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:49:50.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:49:50.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:49:50.65#ibcon#enter wrdev, iclass 14, count 2 2006.257.13:49:50.65#ibcon#first serial, iclass 14, count 2 2006.257.13:49:50.65#ibcon#enter sib2, iclass 14, count 2 2006.257.13:49:50.65#ibcon#flushed, iclass 14, count 2 2006.257.13:49:50.65#ibcon#about to write, iclass 14, count 2 2006.257.13:49:50.65#ibcon#wrote, iclass 14, count 2 2006.257.13:49:50.65#ibcon#about to read 3, iclass 14, count 2 2006.257.13:49:50.67#ibcon#read 3, iclass 14, count 2 2006.257.13:49:50.67#ibcon#about to read 4, iclass 14, count 2 2006.257.13:49:50.67#ibcon#read 4, iclass 14, count 2 2006.257.13:49:50.67#ibcon#about to read 5, iclass 14, count 2 2006.257.13:49:50.67#ibcon#read 5, iclass 14, count 2 2006.257.13:49:50.67#ibcon#about to read 6, iclass 14, count 2 2006.257.13:49:50.67#ibcon#read 6, iclass 14, count 2 2006.257.13:49:50.67#ibcon#end of sib2, iclass 14, count 2 2006.257.13:49:50.67#ibcon#*mode == 0, iclass 14, count 2 2006.257.13:49:50.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.13:49:50.67#ibcon#[25=AT02-07\r\n] 2006.257.13:49:50.67#ibcon#*before write, iclass 14, count 2 2006.257.13:49:50.67#ibcon#enter sib2, iclass 14, count 2 2006.257.13:49:50.67#ibcon#flushed, iclass 14, count 2 2006.257.13:49:50.67#ibcon#about to write, iclass 14, count 2 2006.257.13:49:50.67#ibcon#wrote, iclass 14, count 2 2006.257.13:49:50.67#ibcon#about to read 3, iclass 14, count 2 2006.257.13:49:50.70#ibcon#read 3, iclass 14, count 2 2006.257.13:49:50.70#ibcon#about to read 4, iclass 14, count 2 2006.257.13:49:50.70#ibcon#read 4, iclass 14, count 2 2006.257.13:49:50.70#ibcon#about to read 5, iclass 14, count 2 2006.257.13:49:50.70#ibcon#read 5, iclass 14, count 2 2006.257.13:49:50.70#ibcon#about to read 6, iclass 14, count 2 2006.257.13:49:50.70#ibcon#read 6, iclass 14, count 2 2006.257.13:49:50.70#ibcon#end of sib2, iclass 14, count 2 2006.257.13:49:50.70#ibcon#*after write, iclass 14, count 2 2006.257.13:49:50.70#ibcon#*before return 0, iclass 14, count 2 2006.257.13:49:50.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:49:50.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.13:49:50.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.13:49:50.70#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:50.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:49:50.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:49:50.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:49:50.82#ibcon#enter wrdev, iclass 14, count 0 2006.257.13:49:50.82#ibcon#first serial, iclass 14, count 0 2006.257.13:49:50.82#ibcon#enter sib2, iclass 14, count 0 2006.257.13:49:50.82#ibcon#flushed, iclass 14, count 0 2006.257.13:49:50.82#ibcon#about to write, iclass 14, count 0 2006.257.13:49:50.82#ibcon#wrote, iclass 14, count 0 2006.257.13:49:50.82#ibcon#about to read 3, iclass 14, count 0 2006.257.13:49:50.84#ibcon#read 3, iclass 14, count 0 2006.257.13:49:50.84#ibcon#about to read 4, iclass 14, count 0 2006.257.13:49:50.84#ibcon#read 4, iclass 14, count 0 2006.257.13:49:50.84#ibcon#about to read 5, iclass 14, count 0 2006.257.13:49:50.84#ibcon#read 5, iclass 14, count 0 2006.257.13:49:50.84#ibcon#about to read 6, iclass 14, count 0 2006.257.13:49:50.84#ibcon#read 6, iclass 14, count 0 2006.257.13:49:50.84#ibcon#end of sib2, iclass 14, count 0 2006.257.13:49:50.84#ibcon#*mode == 0, iclass 14, count 0 2006.257.13:49:50.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.13:49:50.84#ibcon#[25=USB\r\n] 2006.257.13:49:50.84#ibcon#*before write, iclass 14, count 0 2006.257.13:49:50.84#ibcon#enter sib2, iclass 14, count 0 2006.257.13:49:50.84#ibcon#flushed, iclass 14, count 0 2006.257.13:49:50.84#ibcon#about to write, iclass 14, count 0 2006.257.13:49:50.84#ibcon#wrote, iclass 14, count 0 2006.257.13:49:50.84#ibcon#about to read 3, iclass 14, count 0 2006.257.13:49:50.87#ibcon#read 3, iclass 14, count 0 2006.257.13:49:50.87#ibcon#about to read 4, iclass 14, count 0 2006.257.13:49:50.87#ibcon#read 4, iclass 14, count 0 2006.257.13:49:50.87#ibcon#about to read 5, iclass 14, count 0 2006.257.13:49:50.87#ibcon#read 5, iclass 14, count 0 2006.257.13:49:50.87#ibcon#about to read 6, iclass 14, count 0 2006.257.13:49:50.87#ibcon#read 6, iclass 14, count 0 2006.257.13:49:50.87#ibcon#end of sib2, iclass 14, count 0 2006.257.13:49:50.87#ibcon#*after write, iclass 14, count 0 2006.257.13:49:50.87#ibcon#*before return 0, iclass 14, count 0 2006.257.13:49:50.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:49:50.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.13:49:50.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.13:49:50.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.13:49:50.87$vck44/valo=3,564.99 2006.257.13:49:50.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.13:49:50.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.13:49:50.87#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:50.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:50.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:50.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:50.87#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:49:50.87#ibcon#first serial, iclass 16, count 0 2006.257.13:49:50.87#ibcon#enter sib2, iclass 16, count 0 2006.257.13:49:50.87#ibcon#flushed, iclass 16, count 0 2006.257.13:49:50.87#ibcon#about to write, iclass 16, count 0 2006.257.13:49:50.87#ibcon#wrote, iclass 16, count 0 2006.257.13:49:50.87#ibcon#about to read 3, iclass 16, count 0 2006.257.13:49:50.89#ibcon#read 3, iclass 16, count 0 2006.257.13:49:50.89#ibcon#about to read 4, iclass 16, count 0 2006.257.13:49:50.89#ibcon#read 4, iclass 16, count 0 2006.257.13:49:50.89#ibcon#about to read 5, iclass 16, count 0 2006.257.13:49:50.89#ibcon#read 5, iclass 16, count 0 2006.257.13:49:50.89#ibcon#about to read 6, iclass 16, count 0 2006.257.13:49:50.89#ibcon#read 6, iclass 16, count 0 2006.257.13:49:50.89#ibcon#end of sib2, iclass 16, count 0 2006.257.13:49:50.89#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:49:50.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:49:50.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:49:50.89#ibcon#*before write, iclass 16, count 0 2006.257.13:49:50.89#ibcon#enter sib2, iclass 16, count 0 2006.257.13:49:50.89#ibcon#flushed, iclass 16, count 0 2006.257.13:49:50.89#ibcon#about to write, iclass 16, count 0 2006.257.13:49:50.89#ibcon#wrote, iclass 16, count 0 2006.257.13:49:50.89#ibcon#about to read 3, iclass 16, count 0 2006.257.13:49:50.93#ibcon#read 3, iclass 16, count 0 2006.257.13:49:50.93#ibcon#about to read 4, iclass 16, count 0 2006.257.13:49:50.93#ibcon#read 4, iclass 16, count 0 2006.257.13:49:50.93#ibcon#about to read 5, iclass 16, count 0 2006.257.13:49:50.93#ibcon#read 5, iclass 16, count 0 2006.257.13:49:50.93#ibcon#about to read 6, iclass 16, count 0 2006.257.13:49:50.93#ibcon#read 6, iclass 16, count 0 2006.257.13:49:50.93#ibcon#end of sib2, iclass 16, count 0 2006.257.13:49:50.93#ibcon#*after write, iclass 16, count 0 2006.257.13:49:50.93#ibcon#*before return 0, iclass 16, count 0 2006.257.13:49:50.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:50.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:50.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:49:50.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:49:50.93$vck44/va=3,8 2006.257.13:49:50.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.13:49:50.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.13:49:50.93#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:50.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:50.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:50.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:50.99#ibcon#enter wrdev, iclass 18, count 2 2006.257.13:49:50.99#ibcon#first serial, iclass 18, count 2 2006.257.13:49:50.99#ibcon#enter sib2, iclass 18, count 2 2006.257.13:49:50.99#ibcon#flushed, iclass 18, count 2 2006.257.13:49:50.99#ibcon#about to write, iclass 18, count 2 2006.257.13:49:50.99#ibcon#wrote, iclass 18, count 2 2006.257.13:49:50.99#ibcon#about to read 3, iclass 18, count 2 2006.257.13:49:51.01#ibcon#read 3, iclass 18, count 2 2006.257.13:49:51.01#ibcon#about to read 4, iclass 18, count 2 2006.257.13:49:51.01#ibcon#read 4, iclass 18, count 2 2006.257.13:49:51.01#ibcon#about to read 5, iclass 18, count 2 2006.257.13:49:51.01#ibcon#read 5, iclass 18, count 2 2006.257.13:49:51.01#ibcon#about to read 6, iclass 18, count 2 2006.257.13:49:51.01#ibcon#read 6, iclass 18, count 2 2006.257.13:49:51.01#ibcon#end of sib2, iclass 18, count 2 2006.257.13:49:51.01#ibcon#*mode == 0, iclass 18, count 2 2006.257.13:49:51.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.13:49:51.01#ibcon#[25=AT03-08\r\n] 2006.257.13:49:51.01#ibcon#*before write, iclass 18, count 2 2006.257.13:49:51.01#ibcon#enter sib2, iclass 18, count 2 2006.257.13:49:51.01#ibcon#flushed, iclass 18, count 2 2006.257.13:49:51.01#ibcon#about to write, iclass 18, count 2 2006.257.13:49:51.01#ibcon#wrote, iclass 18, count 2 2006.257.13:49:51.01#ibcon#about to read 3, iclass 18, count 2 2006.257.13:49:51.04#ibcon#read 3, iclass 18, count 2 2006.257.13:49:51.04#ibcon#about to read 4, iclass 18, count 2 2006.257.13:49:51.04#ibcon#read 4, iclass 18, count 2 2006.257.13:49:51.04#ibcon#about to read 5, iclass 18, count 2 2006.257.13:49:51.04#ibcon#read 5, iclass 18, count 2 2006.257.13:49:51.04#ibcon#about to read 6, iclass 18, count 2 2006.257.13:49:51.04#ibcon#read 6, iclass 18, count 2 2006.257.13:49:51.04#ibcon#end of sib2, iclass 18, count 2 2006.257.13:49:51.04#ibcon#*after write, iclass 18, count 2 2006.257.13:49:51.04#ibcon#*before return 0, iclass 18, count 2 2006.257.13:49:51.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:51.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:51.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.13:49:51.04#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:51.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:51.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:51.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:51.16#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:49:51.16#ibcon#first serial, iclass 18, count 0 2006.257.13:49:51.16#ibcon#enter sib2, iclass 18, count 0 2006.257.13:49:51.16#ibcon#flushed, iclass 18, count 0 2006.257.13:49:51.16#ibcon#about to write, iclass 18, count 0 2006.257.13:49:51.16#ibcon#wrote, iclass 18, count 0 2006.257.13:49:51.16#ibcon#about to read 3, iclass 18, count 0 2006.257.13:49:51.18#ibcon#read 3, iclass 18, count 0 2006.257.13:49:51.18#ibcon#about to read 4, iclass 18, count 0 2006.257.13:49:51.18#ibcon#read 4, iclass 18, count 0 2006.257.13:49:51.18#ibcon#about to read 5, iclass 18, count 0 2006.257.13:49:51.18#ibcon#read 5, iclass 18, count 0 2006.257.13:49:51.18#ibcon#about to read 6, iclass 18, count 0 2006.257.13:49:51.18#ibcon#read 6, iclass 18, count 0 2006.257.13:49:51.18#ibcon#end of sib2, iclass 18, count 0 2006.257.13:49:51.18#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:49:51.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:49:51.18#ibcon#[25=USB\r\n] 2006.257.13:49:51.18#ibcon#*before write, iclass 18, count 0 2006.257.13:49:51.18#ibcon#enter sib2, iclass 18, count 0 2006.257.13:49:51.18#ibcon#flushed, iclass 18, count 0 2006.257.13:49:51.18#ibcon#about to write, iclass 18, count 0 2006.257.13:49:51.18#ibcon#wrote, iclass 18, count 0 2006.257.13:49:51.18#ibcon#about to read 3, iclass 18, count 0 2006.257.13:49:51.21#ibcon#read 3, iclass 18, count 0 2006.257.13:49:51.21#ibcon#about to read 4, iclass 18, count 0 2006.257.13:49:51.21#ibcon#read 4, iclass 18, count 0 2006.257.13:49:51.21#ibcon#about to read 5, iclass 18, count 0 2006.257.13:49:51.21#ibcon#read 5, iclass 18, count 0 2006.257.13:49:51.21#ibcon#about to read 6, iclass 18, count 0 2006.257.13:49:51.21#ibcon#read 6, iclass 18, count 0 2006.257.13:49:51.21#ibcon#end of sib2, iclass 18, count 0 2006.257.13:49:51.21#ibcon#*after write, iclass 18, count 0 2006.257.13:49:51.21#ibcon#*before return 0, iclass 18, count 0 2006.257.13:49:51.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:51.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:51.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:49:51.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:49:51.21$vck44/valo=4,624.99 2006.257.13:49:51.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.13:49:51.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.13:49:51.21#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:51.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:51.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:51.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:51.21#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:49:51.21#ibcon#first serial, iclass 20, count 0 2006.257.13:49:51.21#ibcon#enter sib2, iclass 20, count 0 2006.257.13:49:51.21#ibcon#flushed, iclass 20, count 0 2006.257.13:49:51.21#ibcon#about to write, iclass 20, count 0 2006.257.13:49:51.21#ibcon#wrote, iclass 20, count 0 2006.257.13:49:51.21#ibcon#about to read 3, iclass 20, count 0 2006.257.13:49:51.23#ibcon#read 3, iclass 20, count 0 2006.257.13:49:51.23#ibcon#about to read 4, iclass 20, count 0 2006.257.13:49:51.23#ibcon#read 4, iclass 20, count 0 2006.257.13:49:51.23#ibcon#about to read 5, iclass 20, count 0 2006.257.13:49:51.23#ibcon#read 5, iclass 20, count 0 2006.257.13:49:51.23#ibcon#about to read 6, iclass 20, count 0 2006.257.13:49:51.23#ibcon#read 6, iclass 20, count 0 2006.257.13:49:51.23#ibcon#end of sib2, iclass 20, count 0 2006.257.13:49:51.23#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:49:51.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:49:51.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:49:51.23#ibcon#*before write, iclass 20, count 0 2006.257.13:49:51.23#ibcon#enter sib2, iclass 20, count 0 2006.257.13:49:51.23#ibcon#flushed, iclass 20, count 0 2006.257.13:49:51.23#ibcon#about to write, iclass 20, count 0 2006.257.13:49:51.23#ibcon#wrote, iclass 20, count 0 2006.257.13:49:51.23#ibcon#about to read 3, iclass 20, count 0 2006.257.13:49:51.27#ibcon#read 3, iclass 20, count 0 2006.257.13:49:51.27#ibcon#about to read 4, iclass 20, count 0 2006.257.13:49:51.27#ibcon#read 4, iclass 20, count 0 2006.257.13:49:51.27#ibcon#about to read 5, iclass 20, count 0 2006.257.13:49:51.27#ibcon#read 5, iclass 20, count 0 2006.257.13:49:51.27#ibcon#about to read 6, iclass 20, count 0 2006.257.13:49:51.27#ibcon#read 6, iclass 20, count 0 2006.257.13:49:51.27#ibcon#end of sib2, iclass 20, count 0 2006.257.13:49:51.27#ibcon#*after write, iclass 20, count 0 2006.257.13:49:51.27#ibcon#*before return 0, iclass 20, count 0 2006.257.13:49:51.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:51.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:51.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:49:51.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:49:51.27$vck44/va=4,7 2006.257.13:49:51.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.13:49:51.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.13:49:51.27#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:51.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:51.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:51.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:51.33#ibcon#enter wrdev, iclass 22, count 2 2006.257.13:49:51.33#ibcon#first serial, iclass 22, count 2 2006.257.13:49:51.33#ibcon#enter sib2, iclass 22, count 2 2006.257.13:49:51.33#ibcon#flushed, iclass 22, count 2 2006.257.13:49:51.33#ibcon#about to write, iclass 22, count 2 2006.257.13:49:51.33#ibcon#wrote, iclass 22, count 2 2006.257.13:49:51.33#ibcon#about to read 3, iclass 22, count 2 2006.257.13:49:51.35#ibcon#read 3, iclass 22, count 2 2006.257.13:49:51.35#ibcon#about to read 4, iclass 22, count 2 2006.257.13:49:51.35#ibcon#read 4, iclass 22, count 2 2006.257.13:49:51.35#ibcon#about to read 5, iclass 22, count 2 2006.257.13:49:51.35#ibcon#read 5, iclass 22, count 2 2006.257.13:49:51.35#ibcon#about to read 6, iclass 22, count 2 2006.257.13:49:51.35#ibcon#read 6, iclass 22, count 2 2006.257.13:49:51.35#ibcon#end of sib2, iclass 22, count 2 2006.257.13:49:51.35#ibcon#*mode == 0, iclass 22, count 2 2006.257.13:49:51.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.13:49:51.35#ibcon#[25=AT04-07\r\n] 2006.257.13:49:51.35#ibcon#*before write, iclass 22, count 2 2006.257.13:49:51.35#ibcon#enter sib2, iclass 22, count 2 2006.257.13:49:51.35#ibcon#flushed, iclass 22, count 2 2006.257.13:49:51.35#ibcon#about to write, iclass 22, count 2 2006.257.13:49:51.35#ibcon#wrote, iclass 22, count 2 2006.257.13:49:51.35#ibcon#about to read 3, iclass 22, count 2 2006.257.13:49:51.38#ibcon#read 3, iclass 22, count 2 2006.257.13:49:51.38#ibcon#about to read 4, iclass 22, count 2 2006.257.13:49:51.38#ibcon#read 4, iclass 22, count 2 2006.257.13:49:51.38#ibcon#about to read 5, iclass 22, count 2 2006.257.13:49:51.38#ibcon#read 5, iclass 22, count 2 2006.257.13:49:51.38#ibcon#about to read 6, iclass 22, count 2 2006.257.13:49:51.38#ibcon#read 6, iclass 22, count 2 2006.257.13:49:51.38#ibcon#end of sib2, iclass 22, count 2 2006.257.13:49:51.38#ibcon#*after write, iclass 22, count 2 2006.257.13:49:51.38#ibcon#*before return 0, iclass 22, count 2 2006.257.13:49:51.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:51.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:51.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.13:49:51.38#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:51.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:51.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:51.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:51.50#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:49:51.50#ibcon#first serial, iclass 22, count 0 2006.257.13:49:51.50#ibcon#enter sib2, iclass 22, count 0 2006.257.13:49:51.50#ibcon#flushed, iclass 22, count 0 2006.257.13:49:51.50#ibcon#about to write, iclass 22, count 0 2006.257.13:49:51.50#ibcon#wrote, iclass 22, count 0 2006.257.13:49:51.50#ibcon#about to read 3, iclass 22, count 0 2006.257.13:49:51.52#ibcon#read 3, iclass 22, count 0 2006.257.13:49:51.52#ibcon#about to read 4, iclass 22, count 0 2006.257.13:49:51.52#ibcon#read 4, iclass 22, count 0 2006.257.13:49:51.52#ibcon#about to read 5, iclass 22, count 0 2006.257.13:49:51.52#ibcon#read 5, iclass 22, count 0 2006.257.13:49:51.52#ibcon#about to read 6, iclass 22, count 0 2006.257.13:49:51.52#ibcon#read 6, iclass 22, count 0 2006.257.13:49:51.52#ibcon#end of sib2, iclass 22, count 0 2006.257.13:49:51.52#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:49:51.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:49:51.52#ibcon#[25=USB\r\n] 2006.257.13:49:51.52#ibcon#*before write, iclass 22, count 0 2006.257.13:49:51.52#ibcon#enter sib2, iclass 22, count 0 2006.257.13:49:51.52#ibcon#flushed, iclass 22, count 0 2006.257.13:49:51.52#ibcon#about to write, iclass 22, count 0 2006.257.13:49:51.52#ibcon#wrote, iclass 22, count 0 2006.257.13:49:51.52#ibcon#about to read 3, iclass 22, count 0 2006.257.13:49:51.55#ibcon#read 3, iclass 22, count 0 2006.257.13:49:51.55#ibcon#about to read 4, iclass 22, count 0 2006.257.13:49:51.55#ibcon#read 4, iclass 22, count 0 2006.257.13:49:51.55#ibcon#about to read 5, iclass 22, count 0 2006.257.13:49:51.55#ibcon#read 5, iclass 22, count 0 2006.257.13:49:51.55#ibcon#about to read 6, iclass 22, count 0 2006.257.13:49:51.55#ibcon#read 6, iclass 22, count 0 2006.257.13:49:51.55#ibcon#end of sib2, iclass 22, count 0 2006.257.13:49:51.55#ibcon#*after write, iclass 22, count 0 2006.257.13:49:51.55#ibcon#*before return 0, iclass 22, count 0 2006.257.13:49:51.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:51.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:51.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:49:51.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:49:51.55$vck44/valo=5,734.99 2006.257.13:49:51.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.13:49:51.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.13:49:51.55#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:51.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:51.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:51.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:51.55#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:49:51.55#ibcon#first serial, iclass 24, count 0 2006.257.13:49:51.55#ibcon#enter sib2, iclass 24, count 0 2006.257.13:49:51.55#ibcon#flushed, iclass 24, count 0 2006.257.13:49:51.55#ibcon#about to write, iclass 24, count 0 2006.257.13:49:51.55#ibcon#wrote, iclass 24, count 0 2006.257.13:49:51.55#ibcon#about to read 3, iclass 24, count 0 2006.257.13:49:51.57#ibcon#read 3, iclass 24, count 0 2006.257.13:49:51.57#ibcon#about to read 4, iclass 24, count 0 2006.257.13:49:51.57#ibcon#read 4, iclass 24, count 0 2006.257.13:49:51.57#ibcon#about to read 5, iclass 24, count 0 2006.257.13:49:51.57#ibcon#read 5, iclass 24, count 0 2006.257.13:49:51.57#ibcon#about to read 6, iclass 24, count 0 2006.257.13:49:51.57#ibcon#read 6, iclass 24, count 0 2006.257.13:49:51.57#ibcon#end of sib2, iclass 24, count 0 2006.257.13:49:51.57#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:49:51.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:49:51.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:49:51.57#ibcon#*before write, iclass 24, count 0 2006.257.13:49:51.57#ibcon#enter sib2, iclass 24, count 0 2006.257.13:49:51.57#ibcon#flushed, iclass 24, count 0 2006.257.13:49:51.57#ibcon#about to write, iclass 24, count 0 2006.257.13:49:51.57#ibcon#wrote, iclass 24, count 0 2006.257.13:49:51.57#ibcon#about to read 3, iclass 24, count 0 2006.257.13:49:51.61#ibcon#read 3, iclass 24, count 0 2006.257.13:49:51.61#ibcon#about to read 4, iclass 24, count 0 2006.257.13:49:51.61#ibcon#read 4, iclass 24, count 0 2006.257.13:49:51.61#ibcon#about to read 5, iclass 24, count 0 2006.257.13:49:51.61#ibcon#read 5, iclass 24, count 0 2006.257.13:49:51.61#ibcon#about to read 6, iclass 24, count 0 2006.257.13:49:51.61#ibcon#read 6, iclass 24, count 0 2006.257.13:49:51.61#ibcon#end of sib2, iclass 24, count 0 2006.257.13:49:51.61#ibcon#*after write, iclass 24, count 0 2006.257.13:49:51.61#ibcon#*before return 0, iclass 24, count 0 2006.257.13:49:51.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:51.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:51.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:49:51.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:49:51.61$vck44/va=5,4 2006.257.13:49:51.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.13:49:51.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.13:49:51.61#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:51.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:51.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:51.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:51.67#ibcon#enter wrdev, iclass 26, count 2 2006.257.13:49:51.67#ibcon#first serial, iclass 26, count 2 2006.257.13:49:51.67#ibcon#enter sib2, iclass 26, count 2 2006.257.13:49:51.67#ibcon#flushed, iclass 26, count 2 2006.257.13:49:51.67#ibcon#about to write, iclass 26, count 2 2006.257.13:49:51.67#ibcon#wrote, iclass 26, count 2 2006.257.13:49:51.67#ibcon#about to read 3, iclass 26, count 2 2006.257.13:49:51.69#ibcon#read 3, iclass 26, count 2 2006.257.13:49:51.69#ibcon#about to read 4, iclass 26, count 2 2006.257.13:49:51.69#ibcon#read 4, iclass 26, count 2 2006.257.13:49:51.69#ibcon#about to read 5, iclass 26, count 2 2006.257.13:49:51.69#ibcon#read 5, iclass 26, count 2 2006.257.13:49:51.69#ibcon#about to read 6, iclass 26, count 2 2006.257.13:49:51.69#ibcon#read 6, iclass 26, count 2 2006.257.13:49:51.69#ibcon#end of sib2, iclass 26, count 2 2006.257.13:49:51.69#ibcon#*mode == 0, iclass 26, count 2 2006.257.13:49:51.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.13:49:51.69#ibcon#[25=AT05-04\r\n] 2006.257.13:49:51.69#ibcon#*before write, iclass 26, count 2 2006.257.13:49:51.69#ibcon#enter sib2, iclass 26, count 2 2006.257.13:49:51.69#ibcon#flushed, iclass 26, count 2 2006.257.13:49:51.69#ibcon#about to write, iclass 26, count 2 2006.257.13:49:51.69#ibcon#wrote, iclass 26, count 2 2006.257.13:49:51.69#ibcon#about to read 3, iclass 26, count 2 2006.257.13:49:51.72#ibcon#read 3, iclass 26, count 2 2006.257.13:49:51.72#ibcon#about to read 4, iclass 26, count 2 2006.257.13:49:51.72#ibcon#read 4, iclass 26, count 2 2006.257.13:49:51.72#ibcon#about to read 5, iclass 26, count 2 2006.257.13:49:51.72#ibcon#read 5, iclass 26, count 2 2006.257.13:49:51.72#ibcon#about to read 6, iclass 26, count 2 2006.257.13:49:51.72#ibcon#read 6, iclass 26, count 2 2006.257.13:49:51.72#ibcon#end of sib2, iclass 26, count 2 2006.257.13:49:51.72#ibcon#*after write, iclass 26, count 2 2006.257.13:49:51.72#ibcon#*before return 0, iclass 26, count 2 2006.257.13:49:51.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:51.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:51.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.13:49:51.72#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:51.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:51.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:51.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:51.84#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:49:51.84#ibcon#first serial, iclass 26, count 0 2006.257.13:49:51.84#ibcon#enter sib2, iclass 26, count 0 2006.257.13:49:51.84#ibcon#flushed, iclass 26, count 0 2006.257.13:49:51.84#ibcon#about to write, iclass 26, count 0 2006.257.13:49:51.84#ibcon#wrote, iclass 26, count 0 2006.257.13:49:51.84#ibcon#about to read 3, iclass 26, count 0 2006.257.13:49:51.86#ibcon#read 3, iclass 26, count 0 2006.257.13:49:51.86#ibcon#about to read 4, iclass 26, count 0 2006.257.13:49:51.86#ibcon#read 4, iclass 26, count 0 2006.257.13:49:51.86#ibcon#about to read 5, iclass 26, count 0 2006.257.13:49:51.86#ibcon#read 5, iclass 26, count 0 2006.257.13:49:51.86#ibcon#about to read 6, iclass 26, count 0 2006.257.13:49:51.86#ibcon#read 6, iclass 26, count 0 2006.257.13:49:51.86#ibcon#end of sib2, iclass 26, count 0 2006.257.13:49:51.86#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:49:51.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:49:51.86#ibcon#[25=USB\r\n] 2006.257.13:49:51.86#ibcon#*before write, iclass 26, count 0 2006.257.13:49:51.86#ibcon#enter sib2, iclass 26, count 0 2006.257.13:49:51.86#ibcon#flushed, iclass 26, count 0 2006.257.13:49:51.86#ibcon#about to write, iclass 26, count 0 2006.257.13:49:51.86#ibcon#wrote, iclass 26, count 0 2006.257.13:49:51.86#ibcon#about to read 3, iclass 26, count 0 2006.257.13:49:51.89#ibcon#read 3, iclass 26, count 0 2006.257.13:49:51.89#ibcon#about to read 4, iclass 26, count 0 2006.257.13:49:51.89#ibcon#read 4, iclass 26, count 0 2006.257.13:49:51.89#ibcon#about to read 5, iclass 26, count 0 2006.257.13:49:51.89#ibcon#read 5, iclass 26, count 0 2006.257.13:49:51.89#ibcon#about to read 6, iclass 26, count 0 2006.257.13:49:51.89#ibcon#read 6, iclass 26, count 0 2006.257.13:49:51.89#ibcon#end of sib2, iclass 26, count 0 2006.257.13:49:51.89#ibcon#*after write, iclass 26, count 0 2006.257.13:49:51.89#ibcon#*before return 0, iclass 26, count 0 2006.257.13:49:51.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:51.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:51.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:49:51.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:49:51.89$vck44/valo=6,814.99 2006.257.13:49:51.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.13:49:51.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.13:49:51.89#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:51.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:51.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:51.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:51.89#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:49:51.89#ibcon#first serial, iclass 28, count 0 2006.257.13:49:51.89#ibcon#enter sib2, iclass 28, count 0 2006.257.13:49:51.89#ibcon#flushed, iclass 28, count 0 2006.257.13:49:51.89#ibcon#about to write, iclass 28, count 0 2006.257.13:49:51.89#ibcon#wrote, iclass 28, count 0 2006.257.13:49:51.89#ibcon#about to read 3, iclass 28, count 0 2006.257.13:49:51.91#ibcon#read 3, iclass 28, count 0 2006.257.13:49:51.91#ibcon#about to read 4, iclass 28, count 0 2006.257.13:49:51.91#ibcon#read 4, iclass 28, count 0 2006.257.13:49:51.91#ibcon#about to read 5, iclass 28, count 0 2006.257.13:49:51.91#ibcon#read 5, iclass 28, count 0 2006.257.13:49:51.91#ibcon#about to read 6, iclass 28, count 0 2006.257.13:49:51.91#ibcon#read 6, iclass 28, count 0 2006.257.13:49:51.91#ibcon#end of sib2, iclass 28, count 0 2006.257.13:49:51.91#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:49:51.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:49:51.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:49:51.91#ibcon#*before write, iclass 28, count 0 2006.257.13:49:51.91#ibcon#enter sib2, iclass 28, count 0 2006.257.13:49:51.91#ibcon#flushed, iclass 28, count 0 2006.257.13:49:51.91#ibcon#about to write, iclass 28, count 0 2006.257.13:49:51.91#ibcon#wrote, iclass 28, count 0 2006.257.13:49:51.91#ibcon#about to read 3, iclass 28, count 0 2006.257.13:49:51.95#ibcon#read 3, iclass 28, count 0 2006.257.13:49:51.95#ibcon#about to read 4, iclass 28, count 0 2006.257.13:49:51.95#ibcon#read 4, iclass 28, count 0 2006.257.13:49:51.95#ibcon#about to read 5, iclass 28, count 0 2006.257.13:49:51.95#ibcon#read 5, iclass 28, count 0 2006.257.13:49:51.95#ibcon#about to read 6, iclass 28, count 0 2006.257.13:49:51.95#ibcon#read 6, iclass 28, count 0 2006.257.13:49:51.95#ibcon#end of sib2, iclass 28, count 0 2006.257.13:49:51.95#ibcon#*after write, iclass 28, count 0 2006.257.13:49:51.95#ibcon#*before return 0, iclass 28, count 0 2006.257.13:49:51.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:51.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:51.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:49:51.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:49:51.95$vck44/va=6,4 2006.257.13:49:51.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.13:49:51.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.13:49:51.95#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:51.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:52.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:52.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:52.01#ibcon#enter wrdev, iclass 30, count 2 2006.257.13:49:52.01#ibcon#first serial, iclass 30, count 2 2006.257.13:49:52.01#ibcon#enter sib2, iclass 30, count 2 2006.257.13:49:52.01#ibcon#flushed, iclass 30, count 2 2006.257.13:49:52.01#ibcon#about to write, iclass 30, count 2 2006.257.13:49:52.01#ibcon#wrote, iclass 30, count 2 2006.257.13:49:52.01#ibcon#about to read 3, iclass 30, count 2 2006.257.13:49:52.03#ibcon#read 3, iclass 30, count 2 2006.257.13:49:52.03#ibcon#about to read 4, iclass 30, count 2 2006.257.13:49:52.03#ibcon#read 4, iclass 30, count 2 2006.257.13:49:52.03#ibcon#about to read 5, iclass 30, count 2 2006.257.13:49:52.03#ibcon#read 5, iclass 30, count 2 2006.257.13:49:52.03#ibcon#about to read 6, iclass 30, count 2 2006.257.13:49:52.03#ibcon#read 6, iclass 30, count 2 2006.257.13:49:52.03#ibcon#end of sib2, iclass 30, count 2 2006.257.13:49:52.03#ibcon#*mode == 0, iclass 30, count 2 2006.257.13:49:52.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.13:49:52.03#ibcon#[25=AT06-04\r\n] 2006.257.13:49:52.03#ibcon#*before write, iclass 30, count 2 2006.257.13:49:52.03#ibcon#enter sib2, iclass 30, count 2 2006.257.13:49:52.03#ibcon#flushed, iclass 30, count 2 2006.257.13:49:52.03#ibcon#about to write, iclass 30, count 2 2006.257.13:49:52.03#ibcon#wrote, iclass 30, count 2 2006.257.13:49:52.03#ibcon#about to read 3, iclass 30, count 2 2006.257.13:49:52.06#ibcon#read 3, iclass 30, count 2 2006.257.13:49:52.06#ibcon#about to read 4, iclass 30, count 2 2006.257.13:49:52.06#ibcon#read 4, iclass 30, count 2 2006.257.13:49:52.06#ibcon#about to read 5, iclass 30, count 2 2006.257.13:49:52.06#ibcon#read 5, iclass 30, count 2 2006.257.13:49:52.06#ibcon#about to read 6, iclass 30, count 2 2006.257.13:49:52.06#ibcon#read 6, iclass 30, count 2 2006.257.13:49:52.06#ibcon#end of sib2, iclass 30, count 2 2006.257.13:49:52.06#ibcon#*after write, iclass 30, count 2 2006.257.13:49:52.06#ibcon#*before return 0, iclass 30, count 2 2006.257.13:49:52.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:52.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:52.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.13:49:52.06#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:52.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:52.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:52.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:52.18#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:49:52.18#ibcon#first serial, iclass 30, count 0 2006.257.13:49:52.18#ibcon#enter sib2, iclass 30, count 0 2006.257.13:49:52.18#ibcon#flushed, iclass 30, count 0 2006.257.13:49:52.18#ibcon#about to write, iclass 30, count 0 2006.257.13:49:52.18#ibcon#wrote, iclass 30, count 0 2006.257.13:49:52.18#ibcon#about to read 3, iclass 30, count 0 2006.257.13:49:52.20#ibcon#read 3, iclass 30, count 0 2006.257.13:49:52.20#ibcon#about to read 4, iclass 30, count 0 2006.257.13:49:52.20#ibcon#read 4, iclass 30, count 0 2006.257.13:49:52.20#ibcon#about to read 5, iclass 30, count 0 2006.257.13:49:52.20#ibcon#read 5, iclass 30, count 0 2006.257.13:49:52.20#ibcon#about to read 6, iclass 30, count 0 2006.257.13:49:52.20#ibcon#read 6, iclass 30, count 0 2006.257.13:49:52.20#ibcon#end of sib2, iclass 30, count 0 2006.257.13:49:52.20#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:49:52.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:49:52.20#ibcon#[25=USB\r\n] 2006.257.13:49:52.20#ibcon#*before write, iclass 30, count 0 2006.257.13:49:52.20#ibcon#enter sib2, iclass 30, count 0 2006.257.13:49:52.20#ibcon#flushed, iclass 30, count 0 2006.257.13:49:52.20#ibcon#about to write, iclass 30, count 0 2006.257.13:49:52.20#ibcon#wrote, iclass 30, count 0 2006.257.13:49:52.20#ibcon#about to read 3, iclass 30, count 0 2006.257.13:49:52.23#ibcon#read 3, iclass 30, count 0 2006.257.13:49:52.23#ibcon#about to read 4, iclass 30, count 0 2006.257.13:49:52.23#ibcon#read 4, iclass 30, count 0 2006.257.13:49:52.23#ibcon#about to read 5, iclass 30, count 0 2006.257.13:49:52.23#ibcon#read 5, iclass 30, count 0 2006.257.13:49:52.23#ibcon#about to read 6, iclass 30, count 0 2006.257.13:49:52.23#ibcon#read 6, iclass 30, count 0 2006.257.13:49:52.23#ibcon#end of sib2, iclass 30, count 0 2006.257.13:49:52.23#ibcon#*after write, iclass 30, count 0 2006.257.13:49:52.23#ibcon#*before return 0, iclass 30, count 0 2006.257.13:49:52.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:52.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:52.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:49:52.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:49:52.23$vck44/valo=7,864.99 2006.257.13:49:52.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.13:49:52.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.13:49:52.23#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:52.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:52.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:52.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:52.23#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:49:52.23#ibcon#first serial, iclass 32, count 0 2006.257.13:49:52.23#ibcon#enter sib2, iclass 32, count 0 2006.257.13:49:52.23#ibcon#flushed, iclass 32, count 0 2006.257.13:49:52.23#ibcon#about to write, iclass 32, count 0 2006.257.13:49:52.23#ibcon#wrote, iclass 32, count 0 2006.257.13:49:52.23#ibcon#about to read 3, iclass 32, count 0 2006.257.13:49:52.25#ibcon#read 3, iclass 32, count 0 2006.257.13:49:52.25#ibcon#about to read 4, iclass 32, count 0 2006.257.13:49:52.25#ibcon#read 4, iclass 32, count 0 2006.257.13:49:52.25#ibcon#about to read 5, iclass 32, count 0 2006.257.13:49:52.25#ibcon#read 5, iclass 32, count 0 2006.257.13:49:52.25#ibcon#about to read 6, iclass 32, count 0 2006.257.13:49:52.25#ibcon#read 6, iclass 32, count 0 2006.257.13:49:52.25#ibcon#end of sib2, iclass 32, count 0 2006.257.13:49:52.25#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:49:52.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:49:52.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:49:52.25#ibcon#*before write, iclass 32, count 0 2006.257.13:49:52.25#ibcon#enter sib2, iclass 32, count 0 2006.257.13:49:52.25#ibcon#flushed, iclass 32, count 0 2006.257.13:49:52.25#ibcon#about to write, iclass 32, count 0 2006.257.13:49:52.25#ibcon#wrote, iclass 32, count 0 2006.257.13:49:52.25#ibcon#about to read 3, iclass 32, count 0 2006.257.13:49:52.29#ibcon#read 3, iclass 32, count 0 2006.257.13:49:52.29#ibcon#about to read 4, iclass 32, count 0 2006.257.13:49:52.29#ibcon#read 4, iclass 32, count 0 2006.257.13:49:52.29#ibcon#about to read 5, iclass 32, count 0 2006.257.13:49:52.29#ibcon#read 5, iclass 32, count 0 2006.257.13:49:52.29#ibcon#about to read 6, iclass 32, count 0 2006.257.13:49:52.29#ibcon#read 6, iclass 32, count 0 2006.257.13:49:52.29#ibcon#end of sib2, iclass 32, count 0 2006.257.13:49:52.29#ibcon#*after write, iclass 32, count 0 2006.257.13:49:52.29#ibcon#*before return 0, iclass 32, count 0 2006.257.13:49:52.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:52.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:52.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:49:52.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:49:52.29$vck44/va=7,4 2006.257.13:49:52.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.13:49:52.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.13:49:52.29#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:52.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:52.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:52.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:52.35#ibcon#enter wrdev, iclass 34, count 2 2006.257.13:49:52.35#ibcon#first serial, iclass 34, count 2 2006.257.13:49:52.35#ibcon#enter sib2, iclass 34, count 2 2006.257.13:49:52.35#ibcon#flushed, iclass 34, count 2 2006.257.13:49:52.35#ibcon#about to write, iclass 34, count 2 2006.257.13:49:52.35#ibcon#wrote, iclass 34, count 2 2006.257.13:49:52.35#ibcon#about to read 3, iclass 34, count 2 2006.257.13:49:52.37#ibcon#read 3, iclass 34, count 2 2006.257.13:49:52.37#ibcon#about to read 4, iclass 34, count 2 2006.257.13:49:52.37#ibcon#read 4, iclass 34, count 2 2006.257.13:49:52.37#ibcon#about to read 5, iclass 34, count 2 2006.257.13:49:52.37#ibcon#read 5, iclass 34, count 2 2006.257.13:49:52.37#ibcon#about to read 6, iclass 34, count 2 2006.257.13:49:52.37#ibcon#read 6, iclass 34, count 2 2006.257.13:49:52.37#ibcon#end of sib2, iclass 34, count 2 2006.257.13:49:52.37#ibcon#*mode == 0, iclass 34, count 2 2006.257.13:49:52.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.13:49:52.37#ibcon#[25=AT07-04\r\n] 2006.257.13:49:52.37#ibcon#*before write, iclass 34, count 2 2006.257.13:49:52.37#ibcon#enter sib2, iclass 34, count 2 2006.257.13:49:52.37#ibcon#flushed, iclass 34, count 2 2006.257.13:49:52.37#ibcon#about to write, iclass 34, count 2 2006.257.13:49:52.37#ibcon#wrote, iclass 34, count 2 2006.257.13:49:52.37#ibcon#about to read 3, iclass 34, count 2 2006.257.13:49:52.40#ibcon#read 3, iclass 34, count 2 2006.257.13:49:52.40#ibcon#about to read 4, iclass 34, count 2 2006.257.13:49:52.40#ibcon#read 4, iclass 34, count 2 2006.257.13:49:52.40#ibcon#about to read 5, iclass 34, count 2 2006.257.13:49:52.40#ibcon#read 5, iclass 34, count 2 2006.257.13:49:52.40#ibcon#about to read 6, iclass 34, count 2 2006.257.13:49:52.40#ibcon#read 6, iclass 34, count 2 2006.257.13:49:52.40#ibcon#end of sib2, iclass 34, count 2 2006.257.13:49:52.40#ibcon#*after write, iclass 34, count 2 2006.257.13:49:52.43#ibcon#*before return 0, iclass 34, count 2 2006.257.13:49:52.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:52.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:52.43#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.13:49:52.43#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:52.43#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:52.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:52.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:52.55#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:49:52.55#ibcon#first serial, iclass 34, count 0 2006.257.13:49:52.55#ibcon#enter sib2, iclass 34, count 0 2006.257.13:49:52.55#ibcon#flushed, iclass 34, count 0 2006.257.13:49:52.55#ibcon#about to write, iclass 34, count 0 2006.257.13:49:52.55#ibcon#wrote, iclass 34, count 0 2006.257.13:49:52.55#ibcon#about to read 3, iclass 34, count 0 2006.257.13:49:52.57#ibcon#read 3, iclass 34, count 0 2006.257.13:49:52.57#ibcon#about to read 4, iclass 34, count 0 2006.257.13:49:52.57#ibcon#read 4, iclass 34, count 0 2006.257.13:49:52.57#ibcon#about to read 5, iclass 34, count 0 2006.257.13:49:52.57#ibcon#read 5, iclass 34, count 0 2006.257.13:49:52.57#ibcon#about to read 6, iclass 34, count 0 2006.257.13:49:52.57#ibcon#read 6, iclass 34, count 0 2006.257.13:49:52.57#ibcon#end of sib2, iclass 34, count 0 2006.257.13:49:52.57#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:49:52.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:49:52.57#ibcon#[25=USB\r\n] 2006.257.13:49:52.57#ibcon#*before write, iclass 34, count 0 2006.257.13:49:52.57#ibcon#enter sib2, iclass 34, count 0 2006.257.13:49:52.57#ibcon#flushed, iclass 34, count 0 2006.257.13:49:52.57#ibcon#about to write, iclass 34, count 0 2006.257.13:49:52.57#ibcon#wrote, iclass 34, count 0 2006.257.13:49:52.57#ibcon#about to read 3, iclass 34, count 0 2006.257.13:49:52.60#ibcon#read 3, iclass 34, count 0 2006.257.13:49:52.60#ibcon#about to read 4, iclass 34, count 0 2006.257.13:49:52.60#ibcon#read 4, iclass 34, count 0 2006.257.13:49:52.60#ibcon#about to read 5, iclass 34, count 0 2006.257.13:49:52.60#ibcon#read 5, iclass 34, count 0 2006.257.13:49:52.60#ibcon#about to read 6, iclass 34, count 0 2006.257.13:49:52.60#ibcon#read 6, iclass 34, count 0 2006.257.13:49:52.60#ibcon#end of sib2, iclass 34, count 0 2006.257.13:49:52.60#ibcon#*after write, iclass 34, count 0 2006.257.13:49:52.60#ibcon#*before return 0, iclass 34, count 0 2006.257.13:49:52.60#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:52.60#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:52.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:49:52.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:49:52.60$vck44/valo=8,884.99 2006.257.13:49:52.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.13:49:52.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.13:49:52.60#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:52.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:52.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:52.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:52.60#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:49:52.60#ibcon#first serial, iclass 36, count 0 2006.257.13:49:52.60#ibcon#enter sib2, iclass 36, count 0 2006.257.13:49:52.60#ibcon#flushed, iclass 36, count 0 2006.257.13:49:52.60#ibcon#about to write, iclass 36, count 0 2006.257.13:49:52.60#ibcon#wrote, iclass 36, count 0 2006.257.13:49:52.60#ibcon#about to read 3, iclass 36, count 0 2006.257.13:49:52.62#ibcon#read 3, iclass 36, count 0 2006.257.13:49:52.62#ibcon#about to read 4, iclass 36, count 0 2006.257.13:49:52.62#ibcon#read 4, iclass 36, count 0 2006.257.13:49:52.62#ibcon#about to read 5, iclass 36, count 0 2006.257.13:49:52.62#ibcon#read 5, iclass 36, count 0 2006.257.13:49:52.62#ibcon#about to read 6, iclass 36, count 0 2006.257.13:49:52.62#ibcon#read 6, iclass 36, count 0 2006.257.13:49:52.62#ibcon#end of sib2, iclass 36, count 0 2006.257.13:49:52.62#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:49:52.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:49:52.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:49:52.62#ibcon#*before write, iclass 36, count 0 2006.257.13:49:52.62#ibcon#enter sib2, iclass 36, count 0 2006.257.13:49:52.62#ibcon#flushed, iclass 36, count 0 2006.257.13:49:52.62#ibcon#about to write, iclass 36, count 0 2006.257.13:49:52.62#ibcon#wrote, iclass 36, count 0 2006.257.13:49:52.62#ibcon#about to read 3, iclass 36, count 0 2006.257.13:49:52.66#ibcon#read 3, iclass 36, count 0 2006.257.13:49:52.66#ibcon#about to read 4, iclass 36, count 0 2006.257.13:49:52.66#ibcon#read 4, iclass 36, count 0 2006.257.13:49:52.66#ibcon#about to read 5, iclass 36, count 0 2006.257.13:49:52.66#ibcon#read 5, iclass 36, count 0 2006.257.13:49:52.66#ibcon#about to read 6, iclass 36, count 0 2006.257.13:49:52.66#ibcon#read 6, iclass 36, count 0 2006.257.13:49:52.66#ibcon#end of sib2, iclass 36, count 0 2006.257.13:49:52.66#ibcon#*after write, iclass 36, count 0 2006.257.13:49:52.66#ibcon#*before return 0, iclass 36, count 0 2006.257.13:49:52.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:52.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:52.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:49:52.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:49:52.66$vck44/va=8,4 2006.257.13:49:52.66#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.13:49:52.66#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.13:49:52.66#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:52.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:52.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:52.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:52.72#ibcon#enter wrdev, iclass 38, count 2 2006.257.13:49:52.72#ibcon#first serial, iclass 38, count 2 2006.257.13:49:52.72#ibcon#enter sib2, iclass 38, count 2 2006.257.13:49:52.72#ibcon#flushed, iclass 38, count 2 2006.257.13:49:52.72#ibcon#about to write, iclass 38, count 2 2006.257.13:49:52.72#ibcon#wrote, iclass 38, count 2 2006.257.13:49:52.72#ibcon#about to read 3, iclass 38, count 2 2006.257.13:49:52.74#ibcon#read 3, iclass 38, count 2 2006.257.13:49:52.74#ibcon#about to read 4, iclass 38, count 2 2006.257.13:49:52.74#ibcon#read 4, iclass 38, count 2 2006.257.13:49:52.74#ibcon#about to read 5, iclass 38, count 2 2006.257.13:49:52.74#ibcon#read 5, iclass 38, count 2 2006.257.13:49:52.74#ibcon#about to read 6, iclass 38, count 2 2006.257.13:49:52.74#ibcon#read 6, iclass 38, count 2 2006.257.13:49:52.74#ibcon#end of sib2, iclass 38, count 2 2006.257.13:49:52.74#ibcon#*mode == 0, iclass 38, count 2 2006.257.13:49:52.74#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.13:49:52.74#ibcon#[25=AT08-04\r\n] 2006.257.13:49:52.74#ibcon#*before write, iclass 38, count 2 2006.257.13:49:52.74#ibcon#enter sib2, iclass 38, count 2 2006.257.13:49:52.74#ibcon#flushed, iclass 38, count 2 2006.257.13:49:52.74#ibcon#about to write, iclass 38, count 2 2006.257.13:49:52.74#ibcon#wrote, iclass 38, count 2 2006.257.13:49:52.74#ibcon#about to read 3, iclass 38, count 2 2006.257.13:49:52.77#ibcon#read 3, iclass 38, count 2 2006.257.13:49:52.77#ibcon#about to read 4, iclass 38, count 2 2006.257.13:49:52.77#ibcon#read 4, iclass 38, count 2 2006.257.13:49:52.77#ibcon#about to read 5, iclass 38, count 2 2006.257.13:49:52.77#ibcon#read 5, iclass 38, count 2 2006.257.13:49:52.77#ibcon#about to read 6, iclass 38, count 2 2006.257.13:49:52.77#ibcon#read 6, iclass 38, count 2 2006.257.13:49:52.77#ibcon#end of sib2, iclass 38, count 2 2006.257.13:49:52.77#ibcon#*after write, iclass 38, count 2 2006.257.13:49:52.77#ibcon#*before return 0, iclass 38, count 2 2006.257.13:49:52.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:52.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:52.77#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.13:49:52.77#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:52.77#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:52.89#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:52.89#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:52.89#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:49:52.89#ibcon#first serial, iclass 38, count 0 2006.257.13:49:52.89#ibcon#enter sib2, iclass 38, count 0 2006.257.13:49:52.89#ibcon#flushed, iclass 38, count 0 2006.257.13:49:52.89#ibcon#about to write, iclass 38, count 0 2006.257.13:49:52.89#ibcon#wrote, iclass 38, count 0 2006.257.13:49:52.89#ibcon#about to read 3, iclass 38, count 0 2006.257.13:49:52.91#ibcon#read 3, iclass 38, count 0 2006.257.13:49:52.91#ibcon#about to read 4, iclass 38, count 0 2006.257.13:49:52.91#ibcon#read 4, iclass 38, count 0 2006.257.13:49:52.91#ibcon#about to read 5, iclass 38, count 0 2006.257.13:49:52.91#ibcon#read 5, iclass 38, count 0 2006.257.13:49:52.91#ibcon#about to read 6, iclass 38, count 0 2006.257.13:49:52.91#ibcon#read 6, iclass 38, count 0 2006.257.13:49:52.91#ibcon#end of sib2, iclass 38, count 0 2006.257.13:49:52.91#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:49:52.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:49:52.91#ibcon#[25=USB\r\n] 2006.257.13:49:52.91#ibcon#*before write, iclass 38, count 0 2006.257.13:49:52.91#ibcon#enter sib2, iclass 38, count 0 2006.257.13:49:52.91#ibcon#flushed, iclass 38, count 0 2006.257.13:49:52.91#ibcon#about to write, iclass 38, count 0 2006.257.13:49:52.91#ibcon#wrote, iclass 38, count 0 2006.257.13:49:52.91#ibcon#about to read 3, iclass 38, count 0 2006.257.13:49:52.94#ibcon#read 3, iclass 38, count 0 2006.257.13:49:52.94#ibcon#about to read 4, iclass 38, count 0 2006.257.13:49:52.94#ibcon#read 4, iclass 38, count 0 2006.257.13:49:52.94#ibcon#about to read 5, iclass 38, count 0 2006.257.13:49:52.94#ibcon#read 5, iclass 38, count 0 2006.257.13:49:52.94#ibcon#about to read 6, iclass 38, count 0 2006.257.13:49:52.94#ibcon#read 6, iclass 38, count 0 2006.257.13:49:52.94#ibcon#end of sib2, iclass 38, count 0 2006.257.13:49:52.94#ibcon#*after write, iclass 38, count 0 2006.257.13:49:52.94#ibcon#*before return 0, iclass 38, count 0 2006.257.13:49:52.94#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:52.94#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:52.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:49:52.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:49:52.94$vck44/vblo=1,629.99 2006.257.13:49:52.94#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.13:49:52.94#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.13:49:52.94#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:52.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:52.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:52.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:52.94#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:49:52.94#ibcon#first serial, iclass 40, count 0 2006.257.13:49:52.94#ibcon#enter sib2, iclass 40, count 0 2006.257.13:49:52.94#ibcon#flushed, iclass 40, count 0 2006.257.13:49:52.94#ibcon#about to write, iclass 40, count 0 2006.257.13:49:52.94#ibcon#wrote, iclass 40, count 0 2006.257.13:49:52.94#ibcon#about to read 3, iclass 40, count 0 2006.257.13:49:52.96#ibcon#read 3, iclass 40, count 0 2006.257.13:49:52.96#ibcon#about to read 4, iclass 40, count 0 2006.257.13:49:52.96#ibcon#read 4, iclass 40, count 0 2006.257.13:49:52.96#ibcon#about to read 5, iclass 40, count 0 2006.257.13:49:52.96#ibcon#read 5, iclass 40, count 0 2006.257.13:49:52.96#ibcon#about to read 6, iclass 40, count 0 2006.257.13:49:52.96#ibcon#read 6, iclass 40, count 0 2006.257.13:49:52.96#ibcon#end of sib2, iclass 40, count 0 2006.257.13:49:52.96#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:49:52.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:49:52.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:49:52.96#ibcon#*before write, iclass 40, count 0 2006.257.13:49:52.96#ibcon#enter sib2, iclass 40, count 0 2006.257.13:49:52.96#ibcon#flushed, iclass 40, count 0 2006.257.13:49:52.96#ibcon#about to write, iclass 40, count 0 2006.257.13:49:52.96#ibcon#wrote, iclass 40, count 0 2006.257.13:49:52.96#ibcon#about to read 3, iclass 40, count 0 2006.257.13:49:53.00#ibcon#read 3, iclass 40, count 0 2006.257.13:49:53.00#ibcon#about to read 4, iclass 40, count 0 2006.257.13:49:53.00#ibcon#read 4, iclass 40, count 0 2006.257.13:49:53.00#ibcon#about to read 5, iclass 40, count 0 2006.257.13:49:53.00#ibcon#read 5, iclass 40, count 0 2006.257.13:49:53.00#ibcon#about to read 6, iclass 40, count 0 2006.257.13:49:53.00#ibcon#read 6, iclass 40, count 0 2006.257.13:49:53.00#ibcon#end of sib2, iclass 40, count 0 2006.257.13:49:53.00#ibcon#*after write, iclass 40, count 0 2006.257.13:49:53.00#ibcon#*before return 0, iclass 40, count 0 2006.257.13:49:53.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:53.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:53.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:49:53.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:49:53.00$vck44/vb=1,4 2006.257.13:49:53.00#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.13:49:53.00#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.13:49:53.00#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:53.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:49:53.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:49:53.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:49:53.00#ibcon#enter wrdev, iclass 4, count 2 2006.257.13:49:53.00#ibcon#first serial, iclass 4, count 2 2006.257.13:49:53.00#ibcon#enter sib2, iclass 4, count 2 2006.257.13:49:53.00#ibcon#flushed, iclass 4, count 2 2006.257.13:49:53.00#ibcon#about to write, iclass 4, count 2 2006.257.13:49:53.00#ibcon#wrote, iclass 4, count 2 2006.257.13:49:53.00#ibcon#about to read 3, iclass 4, count 2 2006.257.13:49:53.02#ibcon#read 3, iclass 4, count 2 2006.257.13:49:53.02#ibcon#about to read 4, iclass 4, count 2 2006.257.13:49:53.02#ibcon#read 4, iclass 4, count 2 2006.257.13:49:53.02#ibcon#about to read 5, iclass 4, count 2 2006.257.13:49:53.02#ibcon#read 5, iclass 4, count 2 2006.257.13:49:53.02#ibcon#about to read 6, iclass 4, count 2 2006.257.13:49:53.02#ibcon#read 6, iclass 4, count 2 2006.257.13:49:53.02#ibcon#end of sib2, iclass 4, count 2 2006.257.13:49:53.02#ibcon#*mode == 0, iclass 4, count 2 2006.257.13:49:53.02#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.13:49:53.02#ibcon#[27=AT01-04\r\n] 2006.257.13:49:53.02#ibcon#*before write, iclass 4, count 2 2006.257.13:49:53.02#ibcon#enter sib2, iclass 4, count 2 2006.257.13:49:53.02#ibcon#flushed, iclass 4, count 2 2006.257.13:49:53.02#ibcon#about to write, iclass 4, count 2 2006.257.13:49:53.02#ibcon#wrote, iclass 4, count 2 2006.257.13:49:53.02#ibcon#about to read 3, iclass 4, count 2 2006.257.13:49:53.05#ibcon#read 3, iclass 4, count 2 2006.257.13:49:53.05#ibcon#about to read 4, iclass 4, count 2 2006.257.13:49:53.05#ibcon#read 4, iclass 4, count 2 2006.257.13:49:53.05#ibcon#about to read 5, iclass 4, count 2 2006.257.13:49:53.05#ibcon#read 5, iclass 4, count 2 2006.257.13:49:53.05#ibcon#about to read 6, iclass 4, count 2 2006.257.13:49:53.05#ibcon#read 6, iclass 4, count 2 2006.257.13:49:53.05#ibcon#end of sib2, iclass 4, count 2 2006.257.13:49:53.05#ibcon#*after write, iclass 4, count 2 2006.257.13:49:53.05#ibcon#*before return 0, iclass 4, count 2 2006.257.13:49:53.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:49:53.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.13:49:53.05#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.13:49:53.05#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:53.05#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:49:53.17#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:49:53.17#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:49:53.17#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:49:53.17#ibcon#first serial, iclass 4, count 0 2006.257.13:49:53.17#ibcon#enter sib2, iclass 4, count 0 2006.257.13:49:53.17#ibcon#flushed, iclass 4, count 0 2006.257.13:49:53.17#ibcon#about to write, iclass 4, count 0 2006.257.13:49:53.17#ibcon#wrote, iclass 4, count 0 2006.257.13:49:53.17#ibcon#about to read 3, iclass 4, count 0 2006.257.13:49:53.19#ibcon#read 3, iclass 4, count 0 2006.257.13:49:53.19#ibcon#about to read 4, iclass 4, count 0 2006.257.13:49:53.19#ibcon#read 4, iclass 4, count 0 2006.257.13:49:53.19#ibcon#about to read 5, iclass 4, count 0 2006.257.13:49:53.19#ibcon#read 5, iclass 4, count 0 2006.257.13:49:53.19#ibcon#about to read 6, iclass 4, count 0 2006.257.13:49:53.19#ibcon#read 6, iclass 4, count 0 2006.257.13:49:53.19#ibcon#end of sib2, iclass 4, count 0 2006.257.13:49:53.19#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:49:53.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:49:53.19#ibcon#[27=USB\r\n] 2006.257.13:49:53.19#ibcon#*before write, iclass 4, count 0 2006.257.13:49:53.19#ibcon#enter sib2, iclass 4, count 0 2006.257.13:49:53.19#ibcon#flushed, iclass 4, count 0 2006.257.13:49:53.19#ibcon#about to write, iclass 4, count 0 2006.257.13:49:53.19#ibcon#wrote, iclass 4, count 0 2006.257.13:49:53.19#ibcon#about to read 3, iclass 4, count 0 2006.257.13:49:53.22#ibcon#read 3, iclass 4, count 0 2006.257.13:49:53.22#ibcon#about to read 4, iclass 4, count 0 2006.257.13:49:53.22#ibcon#read 4, iclass 4, count 0 2006.257.13:49:53.22#ibcon#about to read 5, iclass 4, count 0 2006.257.13:49:53.22#ibcon#read 5, iclass 4, count 0 2006.257.13:49:53.22#ibcon#about to read 6, iclass 4, count 0 2006.257.13:49:53.22#ibcon#read 6, iclass 4, count 0 2006.257.13:49:53.22#ibcon#end of sib2, iclass 4, count 0 2006.257.13:49:53.22#ibcon#*after write, iclass 4, count 0 2006.257.13:49:53.22#ibcon#*before return 0, iclass 4, count 0 2006.257.13:49:53.22#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:49:53.22#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.13:49:53.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:49:53.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:49:53.22$vck44/vblo=2,634.99 2006.257.13:49:53.22#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.13:49:53.22#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.13:49:53.22#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:53.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:53.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:53.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:53.22#ibcon#enter wrdev, iclass 6, count 0 2006.257.13:49:53.22#ibcon#first serial, iclass 6, count 0 2006.257.13:49:53.22#ibcon#enter sib2, iclass 6, count 0 2006.257.13:49:53.22#ibcon#flushed, iclass 6, count 0 2006.257.13:49:53.22#ibcon#about to write, iclass 6, count 0 2006.257.13:49:53.22#ibcon#wrote, iclass 6, count 0 2006.257.13:49:53.22#ibcon#about to read 3, iclass 6, count 0 2006.257.13:49:53.24#ibcon#read 3, iclass 6, count 0 2006.257.13:49:53.24#ibcon#about to read 4, iclass 6, count 0 2006.257.13:49:53.24#ibcon#read 4, iclass 6, count 0 2006.257.13:49:53.24#ibcon#about to read 5, iclass 6, count 0 2006.257.13:49:53.24#ibcon#read 5, iclass 6, count 0 2006.257.13:49:53.24#ibcon#about to read 6, iclass 6, count 0 2006.257.13:49:53.24#ibcon#read 6, iclass 6, count 0 2006.257.13:49:53.24#ibcon#end of sib2, iclass 6, count 0 2006.257.13:49:53.24#ibcon#*mode == 0, iclass 6, count 0 2006.257.13:49:53.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.13:49:53.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:49:53.24#ibcon#*before write, iclass 6, count 0 2006.257.13:49:53.24#ibcon#enter sib2, iclass 6, count 0 2006.257.13:49:53.24#ibcon#flushed, iclass 6, count 0 2006.257.13:49:53.24#ibcon#about to write, iclass 6, count 0 2006.257.13:49:53.24#ibcon#wrote, iclass 6, count 0 2006.257.13:49:53.24#ibcon#about to read 3, iclass 6, count 0 2006.257.13:49:53.28#ibcon#read 3, iclass 6, count 0 2006.257.13:49:53.28#ibcon#about to read 4, iclass 6, count 0 2006.257.13:49:53.28#ibcon#read 4, iclass 6, count 0 2006.257.13:49:53.28#ibcon#about to read 5, iclass 6, count 0 2006.257.13:49:53.28#ibcon#read 5, iclass 6, count 0 2006.257.13:49:53.28#ibcon#about to read 6, iclass 6, count 0 2006.257.13:49:53.28#ibcon#read 6, iclass 6, count 0 2006.257.13:49:53.28#ibcon#end of sib2, iclass 6, count 0 2006.257.13:49:53.28#ibcon#*after write, iclass 6, count 0 2006.257.13:49:53.28#ibcon#*before return 0, iclass 6, count 0 2006.257.13:49:53.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:53.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.13:49:53.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.13:49:53.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.13:49:53.28$vck44/vb=2,5 2006.257.13:49:53.28#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.13:49:53.28#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.13:49:53.28#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:53.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:53.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:53.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:53.34#ibcon#enter wrdev, iclass 10, count 2 2006.257.13:49:53.34#ibcon#first serial, iclass 10, count 2 2006.257.13:49:53.34#ibcon#enter sib2, iclass 10, count 2 2006.257.13:49:53.34#ibcon#flushed, iclass 10, count 2 2006.257.13:49:53.34#ibcon#about to write, iclass 10, count 2 2006.257.13:49:53.34#ibcon#wrote, iclass 10, count 2 2006.257.13:49:53.34#ibcon#about to read 3, iclass 10, count 2 2006.257.13:49:53.36#ibcon#read 3, iclass 10, count 2 2006.257.13:49:53.36#ibcon#about to read 4, iclass 10, count 2 2006.257.13:49:53.36#ibcon#read 4, iclass 10, count 2 2006.257.13:49:53.36#ibcon#about to read 5, iclass 10, count 2 2006.257.13:49:53.36#ibcon#read 5, iclass 10, count 2 2006.257.13:49:53.36#ibcon#about to read 6, iclass 10, count 2 2006.257.13:49:53.36#ibcon#read 6, iclass 10, count 2 2006.257.13:49:53.36#ibcon#end of sib2, iclass 10, count 2 2006.257.13:49:53.36#ibcon#*mode == 0, iclass 10, count 2 2006.257.13:49:53.36#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.13:49:53.36#ibcon#[27=AT02-05\r\n] 2006.257.13:49:53.36#ibcon#*before write, iclass 10, count 2 2006.257.13:49:53.36#ibcon#enter sib2, iclass 10, count 2 2006.257.13:49:53.36#ibcon#flushed, iclass 10, count 2 2006.257.13:49:53.36#ibcon#about to write, iclass 10, count 2 2006.257.13:49:53.36#ibcon#wrote, iclass 10, count 2 2006.257.13:49:53.36#ibcon#about to read 3, iclass 10, count 2 2006.257.13:49:53.39#ibcon#read 3, iclass 10, count 2 2006.257.13:49:53.39#ibcon#about to read 4, iclass 10, count 2 2006.257.13:49:53.44#ibcon#read 4, iclass 10, count 2 2006.257.13:49:53.44#ibcon#about to read 5, iclass 10, count 2 2006.257.13:49:53.44#ibcon#read 5, iclass 10, count 2 2006.257.13:49:53.44#ibcon#about to read 6, iclass 10, count 2 2006.257.13:49:53.44#ibcon#read 6, iclass 10, count 2 2006.257.13:49:53.44#ibcon#end of sib2, iclass 10, count 2 2006.257.13:49:53.44#ibcon#*after write, iclass 10, count 2 2006.257.13:49:53.44#ibcon#*before return 0, iclass 10, count 2 2006.257.13:49:53.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:53.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.13:49:53.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.13:49:53.44#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:53.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:53.50#abcon#<5=/14 1.6 4.1 17.56 971014.0\r\n> 2006.257.13:49:53.52#abcon#{5=INTERFACE CLEAR} 2006.257.13:49:53.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:53.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:53.56#ibcon#enter wrdev, iclass 10, count 0 2006.257.13:49:53.56#ibcon#first serial, iclass 10, count 0 2006.257.13:49:53.56#ibcon#enter sib2, iclass 10, count 0 2006.257.13:49:53.56#ibcon#flushed, iclass 10, count 0 2006.257.13:49:53.56#ibcon#about to write, iclass 10, count 0 2006.257.13:49:53.56#ibcon#wrote, iclass 10, count 0 2006.257.13:49:53.56#ibcon#about to read 3, iclass 10, count 0 2006.257.13:49:53.58#ibcon#read 3, iclass 10, count 0 2006.257.13:49:53.58#ibcon#about to read 4, iclass 10, count 0 2006.257.13:49:53.58#ibcon#read 4, iclass 10, count 0 2006.257.13:49:53.58#ibcon#about to read 5, iclass 10, count 0 2006.257.13:49:53.58#ibcon#read 5, iclass 10, count 0 2006.257.13:49:53.58#ibcon#about to read 6, iclass 10, count 0 2006.257.13:49:53.58#ibcon#read 6, iclass 10, count 0 2006.257.13:49:53.58#ibcon#end of sib2, iclass 10, count 0 2006.257.13:49:53.58#ibcon#*mode == 0, iclass 10, count 0 2006.257.13:49:53.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.13:49:53.58#ibcon#[27=USB\r\n] 2006.257.13:49:53.58#ibcon#*before write, iclass 10, count 0 2006.257.13:49:53.58#ibcon#enter sib2, iclass 10, count 0 2006.257.13:49:53.58#ibcon#flushed, iclass 10, count 0 2006.257.13:49:53.58#ibcon#about to write, iclass 10, count 0 2006.257.13:49:53.58#ibcon#wrote, iclass 10, count 0 2006.257.13:49:53.58#ibcon#about to read 3, iclass 10, count 0 2006.257.13:49:53.58#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:49:53.61#ibcon#read 3, iclass 10, count 0 2006.257.13:49:53.61#ibcon#about to read 4, iclass 10, count 0 2006.257.13:49:53.61#ibcon#read 4, iclass 10, count 0 2006.257.13:49:53.61#ibcon#about to read 5, iclass 10, count 0 2006.257.13:49:53.61#ibcon#read 5, iclass 10, count 0 2006.257.13:49:53.61#ibcon#about to read 6, iclass 10, count 0 2006.257.13:49:53.61#ibcon#read 6, iclass 10, count 0 2006.257.13:49:53.61#ibcon#end of sib2, iclass 10, count 0 2006.257.13:49:53.61#ibcon#*after write, iclass 10, count 0 2006.257.13:49:53.61#ibcon#*before return 0, iclass 10, count 0 2006.257.13:49:53.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:53.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.13:49:53.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.13:49:53.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.13:49:53.61$vck44/vblo=3,649.99 2006.257.13:49:53.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.13:49:53.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.13:49:53.61#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:53.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:53.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:53.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:53.61#ibcon#enter wrdev, iclass 16, count 0 2006.257.13:49:53.61#ibcon#first serial, iclass 16, count 0 2006.257.13:49:53.61#ibcon#enter sib2, iclass 16, count 0 2006.257.13:49:53.61#ibcon#flushed, iclass 16, count 0 2006.257.13:49:53.61#ibcon#about to write, iclass 16, count 0 2006.257.13:49:53.61#ibcon#wrote, iclass 16, count 0 2006.257.13:49:53.61#ibcon#about to read 3, iclass 16, count 0 2006.257.13:49:53.63#ibcon#read 3, iclass 16, count 0 2006.257.13:49:53.63#ibcon#about to read 4, iclass 16, count 0 2006.257.13:49:53.63#ibcon#read 4, iclass 16, count 0 2006.257.13:49:53.63#ibcon#about to read 5, iclass 16, count 0 2006.257.13:49:53.63#ibcon#read 5, iclass 16, count 0 2006.257.13:49:53.63#ibcon#about to read 6, iclass 16, count 0 2006.257.13:49:53.63#ibcon#read 6, iclass 16, count 0 2006.257.13:49:53.63#ibcon#end of sib2, iclass 16, count 0 2006.257.13:49:53.63#ibcon#*mode == 0, iclass 16, count 0 2006.257.13:49:53.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.13:49:53.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:49:53.63#ibcon#*before write, iclass 16, count 0 2006.257.13:49:53.63#ibcon#enter sib2, iclass 16, count 0 2006.257.13:49:53.63#ibcon#flushed, iclass 16, count 0 2006.257.13:49:53.63#ibcon#about to write, iclass 16, count 0 2006.257.13:49:53.63#ibcon#wrote, iclass 16, count 0 2006.257.13:49:53.63#ibcon#about to read 3, iclass 16, count 0 2006.257.13:49:53.67#ibcon#read 3, iclass 16, count 0 2006.257.13:49:53.67#ibcon#about to read 4, iclass 16, count 0 2006.257.13:49:53.67#ibcon#read 4, iclass 16, count 0 2006.257.13:49:53.67#ibcon#about to read 5, iclass 16, count 0 2006.257.13:49:53.67#ibcon#read 5, iclass 16, count 0 2006.257.13:49:53.67#ibcon#about to read 6, iclass 16, count 0 2006.257.13:49:53.67#ibcon#read 6, iclass 16, count 0 2006.257.13:49:53.67#ibcon#end of sib2, iclass 16, count 0 2006.257.13:49:53.67#ibcon#*after write, iclass 16, count 0 2006.257.13:49:53.67#ibcon#*before return 0, iclass 16, count 0 2006.257.13:49:53.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:53.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.13:49:53.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.13:49:53.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.13:49:53.67$vck44/vb=3,4 2006.257.13:49:53.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.13:49:53.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.13:49:53.67#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:53.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:53.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:53.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:53.73#ibcon#enter wrdev, iclass 18, count 2 2006.257.13:49:53.73#ibcon#first serial, iclass 18, count 2 2006.257.13:49:53.73#ibcon#enter sib2, iclass 18, count 2 2006.257.13:49:53.73#ibcon#flushed, iclass 18, count 2 2006.257.13:49:53.73#ibcon#about to write, iclass 18, count 2 2006.257.13:49:53.73#ibcon#wrote, iclass 18, count 2 2006.257.13:49:53.73#ibcon#about to read 3, iclass 18, count 2 2006.257.13:49:53.75#ibcon#read 3, iclass 18, count 2 2006.257.13:49:53.75#ibcon#about to read 4, iclass 18, count 2 2006.257.13:49:53.75#ibcon#read 4, iclass 18, count 2 2006.257.13:49:53.75#ibcon#about to read 5, iclass 18, count 2 2006.257.13:49:53.75#ibcon#read 5, iclass 18, count 2 2006.257.13:49:53.75#ibcon#about to read 6, iclass 18, count 2 2006.257.13:49:53.75#ibcon#read 6, iclass 18, count 2 2006.257.13:49:53.75#ibcon#end of sib2, iclass 18, count 2 2006.257.13:49:53.75#ibcon#*mode == 0, iclass 18, count 2 2006.257.13:49:53.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.13:49:53.75#ibcon#[27=AT03-04\r\n] 2006.257.13:49:53.75#ibcon#*before write, iclass 18, count 2 2006.257.13:49:53.75#ibcon#enter sib2, iclass 18, count 2 2006.257.13:49:53.75#ibcon#flushed, iclass 18, count 2 2006.257.13:49:53.75#ibcon#about to write, iclass 18, count 2 2006.257.13:49:53.75#ibcon#wrote, iclass 18, count 2 2006.257.13:49:53.75#ibcon#about to read 3, iclass 18, count 2 2006.257.13:49:53.78#ibcon#read 3, iclass 18, count 2 2006.257.13:49:53.78#ibcon#about to read 4, iclass 18, count 2 2006.257.13:49:53.78#ibcon#read 4, iclass 18, count 2 2006.257.13:49:53.78#ibcon#about to read 5, iclass 18, count 2 2006.257.13:49:53.78#ibcon#read 5, iclass 18, count 2 2006.257.13:49:53.78#ibcon#about to read 6, iclass 18, count 2 2006.257.13:49:53.78#ibcon#read 6, iclass 18, count 2 2006.257.13:49:53.78#ibcon#end of sib2, iclass 18, count 2 2006.257.13:49:53.78#ibcon#*after write, iclass 18, count 2 2006.257.13:49:53.78#ibcon#*before return 0, iclass 18, count 2 2006.257.13:49:53.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:53.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.13:49:53.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.13:49:53.78#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:53.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:53.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:53.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:53.90#ibcon#enter wrdev, iclass 18, count 0 2006.257.13:49:53.90#ibcon#first serial, iclass 18, count 0 2006.257.13:49:53.90#ibcon#enter sib2, iclass 18, count 0 2006.257.13:49:53.90#ibcon#flushed, iclass 18, count 0 2006.257.13:49:53.90#ibcon#about to write, iclass 18, count 0 2006.257.13:49:53.90#ibcon#wrote, iclass 18, count 0 2006.257.13:49:53.90#ibcon#about to read 3, iclass 18, count 0 2006.257.13:49:53.92#ibcon#read 3, iclass 18, count 0 2006.257.13:49:53.92#ibcon#about to read 4, iclass 18, count 0 2006.257.13:49:53.92#ibcon#read 4, iclass 18, count 0 2006.257.13:49:53.92#ibcon#about to read 5, iclass 18, count 0 2006.257.13:49:53.92#ibcon#read 5, iclass 18, count 0 2006.257.13:49:53.92#ibcon#about to read 6, iclass 18, count 0 2006.257.13:49:53.92#ibcon#read 6, iclass 18, count 0 2006.257.13:49:53.92#ibcon#end of sib2, iclass 18, count 0 2006.257.13:49:53.92#ibcon#*mode == 0, iclass 18, count 0 2006.257.13:49:53.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.13:49:53.92#ibcon#[27=USB\r\n] 2006.257.13:49:53.92#ibcon#*before write, iclass 18, count 0 2006.257.13:49:53.92#ibcon#enter sib2, iclass 18, count 0 2006.257.13:49:53.92#ibcon#flushed, iclass 18, count 0 2006.257.13:49:53.92#ibcon#about to write, iclass 18, count 0 2006.257.13:49:53.92#ibcon#wrote, iclass 18, count 0 2006.257.13:49:53.92#ibcon#about to read 3, iclass 18, count 0 2006.257.13:49:53.95#ibcon#read 3, iclass 18, count 0 2006.257.13:49:53.95#ibcon#about to read 4, iclass 18, count 0 2006.257.13:49:53.95#ibcon#read 4, iclass 18, count 0 2006.257.13:49:53.95#ibcon#about to read 5, iclass 18, count 0 2006.257.13:49:53.95#ibcon#read 5, iclass 18, count 0 2006.257.13:49:53.95#ibcon#about to read 6, iclass 18, count 0 2006.257.13:49:53.95#ibcon#read 6, iclass 18, count 0 2006.257.13:49:53.95#ibcon#end of sib2, iclass 18, count 0 2006.257.13:49:53.95#ibcon#*after write, iclass 18, count 0 2006.257.13:49:53.95#ibcon#*before return 0, iclass 18, count 0 2006.257.13:49:53.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:53.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.13:49:53.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.13:49:53.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.13:49:53.95$vck44/vblo=4,679.99 2006.257.13:49:53.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.13:49:53.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.13:49:53.95#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:53.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:53.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:53.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:53.95#ibcon#enter wrdev, iclass 20, count 0 2006.257.13:49:53.95#ibcon#first serial, iclass 20, count 0 2006.257.13:49:53.95#ibcon#enter sib2, iclass 20, count 0 2006.257.13:49:53.95#ibcon#flushed, iclass 20, count 0 2006.257.13:49:53.95#ibcon#about to write, iclass 20, count 0 2006.257.13:49:53.95#ibcon#wrote, iclass 20, count 0 2006.257.13:49:53.95#ibcon#about to read 3, iclass 20, count 0 2006.257.13:49:53.97#ibcon#read 3, iclass 20, count 0 2006.257.13:49:53.97#ibcon#about to read 4, iclass 20, count 0 2006.257.13:49:53.97#ibcon#read 4, iclass 20, count 0 2006.257.13:49:53.97#ibcon#about to read 5, iclass 20, count 0 2006.257.13:49:53.97#ibcon#read 5, iclass 20, count 0 2006.257.13:49:53.97#ibcon#about to read 6, iclass 20, count 0 2006.257.13:49:53.97#ibcon#read 6, iclass 20, count 0 2006.257.13:49:53.97#ibcon#end of sib2, iclass 20, count 0 2006.257.13:49:53.97#ibcon#*mode == 0, iclass 20, count 0 2006.257.13:49:53.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.13:49:53.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:49:53.97#ibcon#*before write, iclass 20, count 0 2006.257.13:49:53.97#ibcon#enter sib2, iclass 20, count 0 2006.257.13:49:53.97#ibcon#flushed, iclass 20, count 0 2006.257.13:49:53.97#ibcon#about to write, iclass 20, count 0 2006.257.13:49:53.97#ibcon#wrote, iclass 20, count 0 2006.257.13:49:53.97#ibcon#about to read 3, iclass 20, count 0 2006.257.13:49:54.01#ibcon#read 3, iclass 20, count 0 2006.257.13:49:54.01#ibcon#about to read 4, iclass 20, count 0 2006.257.13:49:54.01#ibcon#read 4, iclass 20, count 0 2006.257.13:49:54.01#ibcon#about to read 5, iclass 20, count 0 2006.257.13:49:54.01#ibcon#read 5, iclass 20, count 0 2006.257.13:49:54.01#ibcon#about to read 6, iclass 20, count 0 2006.257.13:49:54.01#ibcon#read 6, iclass 20, count 0 2006.257.13:49:54.01#ibcon#end of sib2, iclass 20, count 0 2006.257.13:49:54.01#ibcon#*after write, iclass 20, count 0 2006.257.13:49:54.01#ibcon#*before return 0, iclass 20, count 0 2006.257.13:49:54.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:54.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.13:49:54.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.13:49:54.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.13:49:54.01$vck44/vb=4,5 2006.257.13:49:54.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.13:49:54.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.13:49:54.01#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:54.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:54.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:54.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:54.07#ibcon#enter wrdev, iclass 22, count 2 2006.257.13:49:54.07#ibcon#first serial, iclass 22, count 2 2006.257.13:49:54.07#ibcon#enter sib2, iclass 22, count 2 2006.257.13:49:54.07#ibcon#flushed, iclass 22, count 2 2006.257.13:49:54.07#ibcon#about to write, iclass 22, count 2 2006.257.13:49:54.07#ibcon#wrote, iclass 22, count 2 2006.257.13:49:54.07#ibcon#about to read 3, iclass 22, count 2 2006.257.13:49:54.09#ibcon#read 3, iclass 22, count 2 2006.257.13:49:54.09#ibcon#about to read 4, iclass 22, count 2 2006.257.13:49:54.09#ibcon#read 4, iclass 22, count 2 2006.257.13:49:54.09#ibcon#about to read 5, iclass 22, count 2 2006.257.13:49:54.09#ibcon#read 5, iclass 22, count 2 2006.257.13:49:54.09#ibcon#about to read 6, iclass 22, count 2 2006.257.13:49:54.09#ibcon#read 6, iclass 22, count 2 2006.257.13:49:54.09#ibcon#end of sib2, iclass 22, count 2 2006.257.13:49:54.09#ibcon#*mode == 0, iclass 22, count 2 2006.257.13:49:54.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.13:49:54.09#ibcon#[27=AT04-05\r\n] 2006.257.13:49:54.09#ibcon#*before write, iclass 22, count 2 2006.257.13:49:54.09#ibcon#enter sib2, iclass 22, count 2 2006.257.13:49:54.09#ibcon#flushed, iclass 22, count 2 2006.257.13:49:54.09#ibcon#about to write, iclass 22, count 2 2006.257.13:49:54.09#ibcon#wrote, iclass 22, count 2 2006.257.13:49:54.09#ibcon#about to read 3, iclass 22, count 2 2006.257.13:49:54.12#ibcon#read 3, iclass 22, count 2 2006.257.13:49:54.12#ibcon#about to read 4, iclass 22, count 2 2006.257.13:49:54.12#ibcon#read 4, iclass 22, count 2 2006.257.13:49:54.12#ibcon#about to read 5, iclass 22, count 2 2006.257.13:49:54.12#ibcon#read 5, iclass 22, count 2 2006.257.13:49:54.12#ibcon#about to read 6, iclass 22, count 2 2006.257.13:49:54.12#ibcon#read 6, iclass 22, count 2 2006.257.13:49:54.12#ibcon#end of sib2, iclass 22, count 2 2006.257.13:49:54.12#ibcon#*after write, iclass 22, count 2 2006.257.13:49:54.12#ibcon#*before return 0, iclass 22, count 2 2006.257.13:49:54.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:54.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.13:49:54.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.13:49:54.12#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:54.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:54.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:54.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:54.24#ibcon#enter wrdev, iclass 22, count 0 2006.257.13:49:54.24#ibcon#first serial, iclass 22, count 0 2006.257.13:49:54.24#ibcon#enter sib2, iclass 22, count 0 2006.257.13:49:54.24#ibcon#flushed, iclass 22, count 0 2006.257.13:49:54.24#ibcon#about to write, iclass 22, count 0 2006.257.13:49:54.24#ibcon#wrote, iclass 22, count 0 2006.257.13:49:54.24#ibcon#about to read 3, iclass 22, count 0 2006.257.13:49:54.26#ibcon#read 3, iclass 22, count 0 2006.257.13:49:54.26#ibcon#about to read 4, iclass 22, count 0 2006.257.13:49:54.26#ibcon#read 4, iclass 22, count 0 2006.257.13:49:54.26#ibcon#about to read 5, iclass 22, count 0 2006.257.13:49:54.26#ibcon#read 5, iclass 22, count 0 2006.257.13:49:54.26#ibcon#about to read 6, iclass 22, count 0 2006.257.13:49:54.26#ibcon#read 6, iclass 22, count 0 2006.257.13:49:54.26#ibcon#end of sib2, iclass 22, count 0 2006.257.13:49:54.26#ibcon#*mode == 0, iclass 22, count 0 2006.257.13:49:54.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.13:49:54.26#ibcon#[27=USB\r\n] 2006.257.13:49:54.26#ibcon#*before write, iclass 22, count 0 2006.257.13:49:54.26#ibcon#enter sib2, iclass 22, count 0 2006.257.13:49:54.26#ibcon#flushed, iclass 22, count 0 2006.257.13:49:54.26#ibcon#about to write, iclass 22, count 0 2006.257.13:49:54.26#ibcon#wrote, iclass 22, count 0 2006.257.13:49:54.26#ibcon#about to read 3, iclass 22, count 0 2006.257.13:49:54.29#ibcon#read 3, iclass 22, count 0 2006.257.13:49:54.29#ibcon#about to read 4, iclass 22, count 0 2006.257.13:49:54.29#ibcon#read 4, iclass 22, count 0 2006.257.13:49:54.29#ibcon#about to read 5, iclass 22, count 0 2006.257.13:49:54.29#ibcon#read 5, iclass 22, count 0 2006.257.13:49:54.29#ibcon#about to read 6, iclass 22, count 0 2006.257.13:49:54.29#ibcon#read 6, iclass 22, count 0 2006.257.13:49:54.29#ibcon#end of sib2, iclass 22, count 0 2006.257.13:49:54.29#ibcon#*after write, iclass 22, count 0 2006.257.13:49:54.29#ibcon#*before return 0, iclass 22, count 0 2006.257.13:49:54.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:54.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.13:49:54.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.13:49:54.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.13:49:54.29$vck44/vblo=5,709.99 2006.257.13:49:54.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.13:49:54.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.13:49:54.29#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:54.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:54.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:54.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:54.29#ibcon#enter wrdev, iclass 24, count 0 2006.257.13:49:54.29#ibcon#first serial, iclass 24, count 0 2006.257.13:49:54.29#ibcon#enter sib2, iclass 24, count 0 2006.257.13:49:54.29#ibcon#flushed, iclass 24, count 0 2006.257.13:49:54.29#ibcon#about to write, iclass 24, count 0 2006.257.13:49:54.29#ibcon#wrote, iclass 24, count 0 2006.257.13:49:54.29#ibcon#about to read 3, iclass 24, count 0 2006.257.13:49:54.31#ibcon#read 3, iclass 24, count 0 2006.257.13:49:54.31#ibcon#about to read 4, iclass 24, count 0 2006.257.13:49:54.31#ibcon#read 4, iclass 24, count 0 2006.257.13:49:54.31#ibcon#about to read 5, iclass 24, count 0 2006.257.13:49:54.31#ibcon#read 5, iclass 24, count 0 2006.257.13:49:54.31#ibcon#about to read 6, iclass 24, count 0 2006.257.13:49:54.31#ibcon#read 6, iclass 24, count 0 2006.257.13:49:54.31#ibcon#end of sib2, iclass 24, count 0 2006.257.13:49:54.31#ibcon#*mode == 0, iclass 24, count 0 2006.257.13:49:54.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.13:49:54.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:49:54.31#ibcon#*before write, iclass 24, count 0 2006.257.13:49:54.31#ibcon#enter sib2, iclass 24, count 0 2006.257.13:49:54.31#ibcon#flushed, iclass 24, count 0 2006.257.13:49:54.31#ibcon#about to write, iclass 24, count 0 2006.257.13:49:54.31#ibcon#wrote, iclass 24, count 0 2006.257.13:49:54.31#ibcon#about to read 3, iclass 24, count 0 2006.257.13:49:54.35#ibcon#read 3, iclass 24, count 0 2006.257.13:49:54.35#ibcon#about to read 4, iclass 24, count 0 2006.257.13:49:54.35#ibcon#read 4, iclass 24, count 0 2006.257.13:49:54.35#ibcon#about to read 5, iclass 24, count 0 2006.257.13:49:54.35#ibcon#read 5, iclass 24, count 0 2006.257.13:49:54.35#ibcon#about to read 6, iclass 24, count 0 2006.257.13:49:54.35#ibcon#read 6, iclass 24, count 0 2006.257.13:49:54.35#ibcon#end of sib2, iclass 24, count 0 2006.257.13:49:54.35#ibcon#*after write, iclass 24, count 0 2006.257.13:49:54.35#ibcon#*before return 0, iclass 24, count 0 2006.257.13:49:54.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:54.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.13:49:54.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.13:49:54.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.13:49:54.35$vck44/vb=5,4 2006.257.13:49:54.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.13:49:54.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.13:49:54.35#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:54.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:54.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:54.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:54.41#ibcon#enter wrdev, iclass 26, count 2 2006.257.13:49:54.41#ibcon#first serial, iclass 26, count 2 2006.257.13:49:54.41#ibcon#enter sib2, iclass 26, count 2 2006.257.13:49:54.41#ibcon#flushed, iclass 26, count 2 2006.257.13:49:54.41#ibcon#about to write, iclass 26, count 2 2006.257.13:49:54.41#ibcon#wrote, iclass 26, count 2 2006.257.13:49:54.41#ibcon#about to read 3, iclass 26, count 2 2006.257.13:49:54.43#ibcon#read 3, iclass 26, count 2 2006.257.13:49:54.43#ibcon#about to read 4, iclass 26, count 2 2006.257.13:49:54.43#ibcon#read 4, iclass 26, count 2 2006.257.13:49:54.43#ibcon#about to read 5, iclass 26, count 2 2006.257.13:49:54.43#ibcon#read 5, iclass 26, count 2 2006.257.13:49:54.43#ibcon#about to read 6, iclass 26, count 2 2006.257.13:49:54.43#ibcon#read 6, iclass 26, count 2 2006.257.13:49:54.43#ibcon#end of sib2, iclass 26, count 2 2006.257.13:49:54.43#ibcon#*mode == 0, iclass 26, count 2 2006.257.13:49:54.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.13:49:54.43#ibcon#[27=AT05-04\r\n] 2006.257.13:49:54.43#ibcon#*before write, iclass 26, count 2 2006.257.13:49:54.43#ibcon#enter sib2, iclass 26, count 2 2006.257.13:49:54.43#ibcon#flushed, iclass 26, count 2 2006.257.13:49:54.43#ibcon#about to write, iclass 26, count 2 2006.257.13:49:54.43#ibcon#wrote, iclass 26, count 2 2006.257.13:49:54.43#ibcon#about to read 3, iclass 26, count 2 2006.257.13:49:54.46#ibcon#read 3, iclass 26, count 2 2006.257.13:49:54.46#ibcon#about to read 4, iclass 26, count 2 2006.257.13:49:54.46#ibcon#read 4, iclass 26, count 2 2006.257.13:49:54.46#ibcon#about to read 5, iclass 26, count 2 2006.257.13:49:54.46#ibcon#read 5, iclass 26, count 2 2006.257.13:49:54.46#ibcon#about to read 6, iclass 26, count 2 2006.257.13:49:54.46#ibcon#read 6, iclass 26, count 2 2006.257.13:49:54.52#ibcon#end of sib2, iclass 26, count 2 2006.257.13:49:54.52#ibcon#*after write, iclass 26, count 2 2006.257.13:49:54.52#ibcon#*before return 0, iclass 26, count 2 2006.257.13:49:54.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:54.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.13:49:54.52#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.13:49:54.52#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:54.52#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:54.64#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:54.64#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:54.64#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:49:54.64#ibcon#first serial, iclass 26, count 0 2006.257.13:49:54.64#ibcon#enter sib2, iclass 26, count 0 2006.257.13:49:54.64#ibcon#flushed, iclass 26, count 0 2006.257.13:49:54.64#ibcon#about to write, iclass 26, count 0 2006.257.13:49:54.64#ibcon#wrote, iclass 26, count 0 2006.257.13:49:54.64#ibcon#about to read 3, iclass 26, count 0 2006.257.13:49:54.66#ibcon#read 3, iclass 26, count 0 2006.257.13:49:54.66#ibcon#about to read 4, iclass 26, count 0 2006.257.13:49:54.66#ibcon#read 4, iclass 26, count 0 2006.257.13:49:54.66#ibcon#about to read 5, iclass 26, count 0 2006.257.13:49:54.66#ibcon#read 5, iclass 26, count 0 2006.257.13:49:54.66#ibcon#about to read 6, iclass 26, count 0 2006.257.13:49:54.66#ibcon#read 6, iclass 26, count 0 2006.257.13:49:54.66#ibcon#end of sib2, iclass 26, count 0 2006.257.13:49:54.66#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:49:54.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:49:54.66#ibcon#[27=USB\r\n] 2006.257.13:49:54.66#ibcon#*before write, iclass 26, count 0 2006.257.13:49:54.66#ibcon#enter sib2, iclass 26, count 0 2006.257.13:49:54.66#ibcon#flushed, iclass 26, count 0 2006.257.13:49:54.66#ibcon#about to write, iclass 26, count 0 2006.257.13:49:54.66#ibcon#wrote, iclass 26, count 0 2006.257.13:49:54.66#ibcon#about to read 3, iclass 26, count 0 2006.257.13:49:54.69#ibcon#read 3, iclass 26, count 0 2006.257.13:49:54.69#ibcon#about to read 4, iclass 26, count 0 2006.257.13:49:54.69#ibcon#read 4, iclass 26, count 0 2006.257.13:49:54.69#ibcon#about to read 5, iclass 26, count 0 2006.257.13:49:54.69#ibcon#read 5, iclass 26, count 0 2006.257.13:49:54.69#ibcon#about to read 6, iclass 26, count 0 2006.257.13:49:54.69#ibcon#read 6, iclass 26, count 0 2006.257.13:49:54.69#ibcon#end of sib2, iclass 26, count 0 2006.257.13:49:54.69#ibcon#*after write, iclass 26, count 0 2006.257.13:49:54.69#ibcon#*before return 0, iclass 26, count 0 2006.257.13:49:54.69#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:54.69#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.13:49:54.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:49:54.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:49:54.69$vck44/vblo=6,719.99 2006.257.13:49:54.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.13:49:54.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.13:49:54.69#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:54.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:54.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:54.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:54.69#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:49:54.69#ibcon#first serial, iclass 28, count 0 2006.257.13:49:54.69#ibcon#enter sib2, iclass 28, count 0 2006.257.13:49:54.69#ibcon#flushed, iclass 28, count 0 2006.257.13:49:54.69#ibcon#about to write, iclass 28, count 0 2006.257.13:49:54.69#ibcon#wrote, iclass 28, count 0 2006.257.13:49:54.69#ibcon#about to read 3, iclass 28, count 0 2006.257.13:49:54.71#ibcon#read 3, iclass 28, count 0 2006.257.13:49:54.71#ibcon#about to read 4, iclass 28, count 0 2006.257.13:49:54.71#ibcon#read 4, iclass 28, count 0 2006.257.13:49:54.71#ibcon#about to read 5, iclass 28, count 0 2006.257.13:49:54.71#ibcon#read 5, iclass 28, count 0 2006.257.13:49:54.71#ibcon#about to read 6, iclass 28, count 0 2006.257.13:49:54.71#ibcon#read 6, iclass 28, count 0 2006.257.13:49:54.71#ibcon#end of sib2, iclass 28, count 0 2006.257.13:49:54.71#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:49:54.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:49:54.71#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:49:54.71#ibcon#*before write, iclass 28, count 0 2006.257.13:49:54.71#ibcon#enter sib2, iclass 28, count 0 2006.257.13:49:54.71#ibcon#flushed, iclass 28, count 0 2006.257.13:49:54.71#ibcon#about to write, iclass 28, count 0 2006.257.13:49:54.71#ibcon#wrote, iclass 28, count 0 2006.257.13:49:54.71#ibcon#about to read 3, iclass 28, count 0 2006.257.13:49:54.75#ibcon#read 3, iclass 28, count 0 2006.257.13:49:54.75#ibcon#about to read 4, iclass 28, count 0 2006.257.13:49:54.75#ibcon#read 4, iclass 28, count 0 2006.257.13:49:54.75#ibcon#about to read 5, iclass 28, count 0 2006.257.13:49:54.75#ibcon#read 5, iclass 28, count 0 2006.257.13:49:54.75#ibcon#about to read 6, iclass 28, count 0 2006.257.13:49:54.75#ibcon#read 6, iclass 28, count 0 2006.257.13:49:54.75#ibcon#end of sib2, iclass 28, count 0 2006.257.13:49:54.75#ibcon#*after write, iclass 28, count 0 2006.257.13:49:54.75#ibcon#*before return 0, iclass 28, count 0 2006.257.13:49:54.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:54.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.13:49:54.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:49:54.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:49:54.75$vck44/vb=6,4 2006.257.13:49:54.75#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.13:49:54.75#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.13:49:54.75#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:54.75#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:54.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:54.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:54.81#ibcon#enter wrdev, iclass 30, count 2 2006.257.13:49:54.81#ibcon#first serial, iclass 30, count 2 2006.257.13:49:54.81#ibcon#enter sib2, iclass 30, count 2 2006.257.13:49:54.81#ibcon#flushed, iclass 30, count 2 2006.257.13:49:54.81#ibcon#about to write, iclass 30, count 2 2006.257.13:49:54.81#ibcon#wrote, iclass 30, count 2 2006.257.13:49:54.81#ibcon#about to read 3, iclass 30, count 2 2006.257.13:49:54.83#ibcon#read 3, iclass 30, count 2 2006.257.13:49:54.83#ibcon#about to read 4, iclass 30, count 2 2006.257.13:49:54.83#ibcon#read 4, iclass 30, count 2 2006.257.13:49:54.83#ibcon#about to read 5, iclass 30, count 2 2006.257.13:49:54.83#ibcon#read 5, iclass 30, count 2 2006.257.13:49:54.83#ibcon#about to read 6, iclass 30, count 2 2006.257.13:49:54.83#ibcon#read 6, iclass 30, count 2 2006.257.13:49:54.83#ibcon#end of sib2, iclass 30, count 2 2006.257.13:49:54.83#ibcon#*mode == 0, iclass 30, count 2 2006.257.13:49:54.83#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.13:49:54.83#ibcon#[27=AT06-04\r\n] 2006.257.13:49:54.83#ibcon#*before write, iclass 30, count 2 2006.257.13:49:54.83#ibcon#enter sib2, iclass 30, count 2 2006.257.13:49:54.83#ibcon#flushed, iclass 30, count 2 2006.257.13:49:54.83#ibcon#about to write, iclass 30, count 2 2006.257.13:49:54.83#ibcon#wrote, iclass 30, count 2 2006.257.13:49:54.83#ibcon#about to read 3, iclass 30, count 2 2006.257.13:49:54.86#ibcon#read 3, iclass 30, count 2 2006.257.13:49:54.86#ibcon#about to read 4, iclass 30, count 2 2006.257.13:49:54.86#ibcon#read 4, iclass 30, count 2 2006.257.13:49:54.86#ibcon#about to read 5, iclass 30, count 2 2006.257.13:49:54.86#ibcon#read 5, iclass 30, count 2 2006.257.13:49:54.86#ibcon#about to read 6, iclass 30, count 2 2006.257.13:49:54.86#ibcon#read 6, iclass 30, count 2 2006.257.13:49:54.86#ibcon#end of sib2, iclass 30, count 2 2006.257.13:49:54.86#ibcon#*after write, iclass 30, count 2 2006.257.13:49:54.86#ibcon#*before return 0, iclass 30, count 2 2006.257.13:49:54.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:54.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:49:54.86#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.13:49:54.86#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:54.86#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:54.98#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:54.98#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:54.98#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:49:54.98#ibcon#first serial, iclass 30, count 0 2006.257.13:49:54.98#ibcon#enter sib2, iclass 30, count 0 2006.257.13:49:54.98#ibcon#flushed, iclass 30, count 0 2006.257.13:49:54.98#ibcon#about to write, iclass 30, count 0 2006.257.13:49:54.98#ibcon#wrote, iclass 30, count 0 2006.257.13:49:54.98#ibcon#about to read 3, iclass 30, count 0 2006.257.13:49:55.00#ibcon#read 3, iclass 30, count 0 2006.257.13:49:55.00#ibcon#about to read 4, iclass 30, count 0 2006.257.13:49:55.00#ibcon#read 4, iclass 30, count 0 2006.257.13:49:55.00#ibcon#about to read 5, iclass 30, count 0 2006.257.13:49:55.00#ibcon#read 5, iclass 30, count 0 2006.257.13:49:55.00#ibcon#about to read 6, iclass 30, count 0 2006.257.13:49:55.00#ibcon#read 6, iclass 30, count 0 2006.257.13:49:55.00#ibcon#end of sib2, iclass 30, count 0 2006.257.13:49:55.00#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:49:55.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:49:55.00#ibcon#[27=USB\r\n] 2006.257.13:49:55.00#ibcon#*before write, iclass 30, count 0 2006.257.13:49:55.00#ibcon#enter sib2, iclass 30, count 0 2006.257.13:49:55.00#ibcon#flushed, iclass 30, count 0 2006.257.13:49:55.00#ibcon#about to write, iclass 30, count 0 2006.257.13:49:55.00#ibcon#wrote, iclass 30, count 0 2006.257.13:49:55.00#ibcon#about to read 3, iclass 30, count 0 2006.257.13:49:55.03#ibcon#read 3, iclass 30, count 0 2006.257.13:49:55.03#ibcon#about to read 4, iclass 30, count 0 2006.257.13:49:55.03#ibcon#read 4, iclass 30, count 0 2006.257.13:49:55.03#ibcon#about to read 5, iclass 30, count 0 2006.257.13:49:55.03#ibcon#read 5, iclass 30, count 0 2006.257.13:49:55.03#ibcon#about to read 6, iclass 30, count 0 2006.257.13:49:55.03#ibcon#read 6, iclass 30, count 0 2006.257.13:49:55.03#ibcon#end of sib2, iclass 30, count 0 2006.257.13:49:55.03#ibcon#*after write, iclass 30, count 0 2006.257.13:49:55.03#ibcon#*before return 0, iclass 30, count 0 2006.257.13:49:55.03#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:55.03#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:49:55.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:49:55.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:49:55.03$vck44/vblo=7,734.99 2006.257.13:49:55.03#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.13:49:55.03#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.13:49:55.03#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:55.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:55.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:55.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:55.03#ibcon#enter wrdev, iclass 32, count 0 2006.257.13:49:55.03#ibcon#first serial, iclass 32, count 0 2006.257.13:49:55.03#ibcon#enter sib2, iclass 32, count 0 2006.257.13:49:55.03#ibcon#flushed, iclass 32, count 0 2006.257.13:49:55.03#ibcon#about to write, iclass 32, count 0 2006.257.13:49:55.03#ibcon#wrote, iclass 32, count 0 2006.257.13:49:55.03#ibcon#about to read 3, iclass 32, count 0 2006.257.13:49:55.05#ibcon#read 3, iclass 32, count 0 2006.257.13:49:55.05#ibcon#about to read 4, iclass 32, count 0 2006.257.13:49:55.05#ibcon#read 4, iclass 32, count 0 2006.257.13:49:55.05#ibcon#about to read 5, iclass 32, count 0 2006.257.13:49:55.05#ibcon#read 5, iclass 32, count 0 2006.257.13:49:55.05#ibcon#about to read 6, iclass 32, count 0 2006.257.13:49:55.05#ibcon#read 6, iclass 32, count 0 2006.257.13:49:55.05#ibcon#end of sib2, iclass 32, count 0 2006.257.13:49:55.05#ibcon#*mode == 0, iclass 32, count 0 2006.257.13:49:55.05#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.13:49:55.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:49:55.05#ibcon#*before write, iclass 32, count 0 2006.257.13:49:55.05#ibcon#enter sib2, iclass 32, count 0 2006.257.13:49:55.05#ibcon#flushed, iclass 32, count 0 2006.257.13:49:55.05#ibcon#about to write, iclass 32, count 0 2006.257.13:49:55.05#ibcon#wrote, iclass 32, count 0 2006.257.13:49:55.05#ibcon#about to read 3, iclass 32, count 0 2006.257.13:49:55.09#ibcon#read 3, iclass 32, count 0 2006.257.13:49:55.09#ibcon#about to read 4, iclass 32, count 0 2006.257.13:49:55.09#ibcon#read 4, iclass 32, count 0 2006.257.13:49:55.09#ibcon#about to read 5, iclass 32, count 0 2006.257.13:49:55.09#ibcon#read 5, iclass 32, count 0 2006.257.13:49:55.09#ibcon#about to read 6, iclass 32, count 0 2006.257.13:49:55.09#ibcon#read 6, iclass 32, count 0 2006.257.13:49:55.09#ibcon#end of sib2, iclass 32, count 0 2006.257.13:49:55.09#ibcon#*after write, iclass 32, count 0 2006.257.13:49:55.09#ibcon#*before return 0, iclass 32, count 0 2006.257.13:49:55.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:55.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.13:49:55.09#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.13:49:55.09#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.13:49:55.09$vck44/vb=7,4 2006.257.13:49:55.09#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.13:49:55.09#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.13:49:55.09#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:55.09#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:55.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:55.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:55.15#ibcon#enter wrdev, iclass 34, count 2 2006.257.13:49:55.15#ibcon#first serial, iclass 34, count 2 2006.257.13:49:55.15#ibcon#enter sib2, iclass 34, count 2 2006.257.13:49:55.15#ibcon#flushed, iclass 34, count 2 2006.257.13:49:55.15#ibcon#about to write, iclass 34, count 2 2006.257.13:49:55.15#ibcon#wrote, iclass 34, count 2 2006.257.13:49:55.15#ibcon#about to read 3, iclass 34, count 2 2006.257.13:49:55.17#ibcon#read 3, iclass 34, count 2 2006.257.13:49:55.17#ibcon#about to read 4, iclass 34, count 2 2006.257.13:49:55.17#ibcon#read 4, iclass 34, count 2 2006.257.13:49:55.17#ibcon#about to read 5, iclass 34, count 2 2006.257.13:49:55.17#ibcon#read 5, iclass 34, count 2 2006.257.13:49:55.17#ibcon#about to read 6, iclass 34, count 2 2006.257.13:49:55.17#ibcon#read 6, iclass 34, count 2 2006.257.13:49:55.17#ibcon#end of sib2, iclass 34, count 2 2006.257.13:49:55.17#ibcon#*mode == 0, iclass 34, count 2 2006.257.13:49:55.17#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.13:49:55.17#ibcon#[27=AT07-04\r\n] 2006.257.13:49:55.17#ibcon#*before write, iclass 34, count 2 2006.257.13:49:55.17#ibcon#enter sib2, iclass 34, count 2 2006.257.13:49:55.17#ibcon#flushed, iclass 34, count 2 2006.257.13:49:55.17#ibcon#about to write, iclass 34, count 2 2006.257.13:49:55.17#ibcon#wrote, iclass 34, count 2 2006.257.13:49:55.17#ibcon#about to read 3, iclass 34, count 2 2006.257.13:49:55.20#ibcon#read 3, iclass 34, count 2 2006.257.13:49:55.20#ibcon#about to read 4, iclass 34, count 2 2006.257.13:49:55.20#ibcon#read 4, iclass 34, count 2 2006.257.13:49:55.20#ibcon#about to read 5, iclass 34, count 2 2006.257.13:49:55.20#ibcon#read 5, iclass 34, count 2 2006.257.13:49:55.20#ibcon#about to read 6, iclass 34, count 2 2006.257.13:49:55.20#ibcon#read 6, iclass 34, count 2 2006.257.13:49:55.20#ibcon#end of sib2, iclass 34, count 2 2006.257.13:49:55.20#ibcon#*after write, iclass 34, count 2 2006.257.13:49:55.20#ibcon#*before return 0, iclass 34, count 2 2006.257.13:49:55.20#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:55.20#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.13:49:55.20#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.13:49:55.20#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:55.20#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:55.32#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:55.32#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:55.32#ibcon#enter wrdev, iclass 34, count 0 2006.257.13:49:55.32#ibcon#first serial, iclass 34, count 0 2006.257.13:49:55.32#ibcon#enter sib2, iclass 34, count 0 2006.257.13:49:55.32#ibcon#flushed, iclass 34, count 0 2006.257.13:49:55.32#ibcon#about to write, iclass 34, count 0 2006.257.13:49:55.32#ibcon#wrote, iclass 34, count 0 2006.257.13:49:55.32#ibcon#about to read 3, iclass 34, count 0 2006.257.13:49:55.34#ibcon#read 3, iclass 34, count 0 2006.257.13:49:55.34#ibcon#about to read 4, iclass 34, count 0 2006.257.13:49:55.34#ibcon#read 4, iclass 34, count 0 2006.257.13:49:55.34#ibcon#about to read 5, iclass 34, count 0 2006.257.13:49:55.34#ibcon#read 5, iclass 34, count 0 2006.257.13:49:55.34#ibcon#about to read 6, iclass 34, count 0 2006.257.13:49:55.34#ibcon#read 6, iclass 34, count 0 2006.257.13:49:55.34#ibcon#end of sib2, iclass 34, count 0 2006.257.13:49:55.34#ibcon#*mode == 0, iclass 34, count 0 2006.257.13:49:55.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.13:49:55.34#ibcon#[27=USB\r\n] 2006.257.13:49:55.34#ibcon#*before write, iclass 34, count 0 2006.257.13:49:55.34#ibcon#enter sib2, iclass 34, count 0 2006.257.13:49:55.34#ibcon#flushed, iclass 34, count 0 2006.257.13:49:55.34#ibcon#about to write, iclass 34, count 0 2006.257.13:49:55.34#ibcon#wrote, iclass 34, count 0 2006.257.13:49:55.34#ibcon#about to read 3, iclass 34, count 0 2006.257.13:49:55.37#ibcon#read 3, iclass 34, count 0 2006.257.13:49:55.37#ibcon#about to read 4, iclass 34, count 0 2006.257.13:49:55.37#ibcon#read 4, iclass 34, count 0 2006.257.13:49:55.37#ibcon#about to read 5, iclass 34, count 0 2006.257.13:49:55.37#ibcon#read 5, iclass 34, count 0 2006.257.13:49:55.37#ibcon#about to read 6, iclass 34, count 0 2006.257.13:49:55.37#ibcon#read 6, iclass 34, count 0 2006.257.13:49:55.37#ibcon#end of sib2, iclass 34, count 0 2006.257.13:49:55.37#ibcon#*after write, iclass 34, count 0 2006.257.13:49:55.37#ibcon#*before return 0, iclass 34, count 0 2006.257.13:49:55.37#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:55.37#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.13:49:55.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.13:49:55.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.13:49:55.37$vck44/vblo=8,744.99 2006.257.13:49:55.37#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.13:49:55.37#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.13:49:55.37#ibcon#ireg 17 cls_cnt 0 2006.257.13:49:55.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:55.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:55.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:55.37#ibcon#enter wrdev, iclass 36, count 0 2006.257.13:49:55.37#ibcon#first serial, iclass 36, count 0 2006.257.13:49:55.37#ibcon#enter sib2, iclass 36, count 0 2006.257.13:49:55.37#ibcon#flushed, iclass 36, count 0 2006.257.13:49:55.37#ibcon#about to write, iclass 36, count 0 2006.257.13:49:55.37#ibcon#wrote, iclass 36, count 0 2006.257.13:49:55.37#ibcon#about to read 3, iclass 36, count 0 2006.257.13:49:55.39#ibcon#read 3, iclass 36, count 0 2006.257.13:49:55.39#ibcon#about to read 4, iclass 36, count 0 2006.257.13:49:55.39#ibcon#read 4, iclass 36, count 0 2006.257.13:49:55.39#ibcon#about to read 5, iclass 36, count 0 2006.257.13:49:55.39#ibcon#read 5, iclass 36, count 0 2006.257.13:49:55.39#ibcon#about to read 6, iclass 36, count 0 2006.257.13:49:55.39#ibcon#read 6, iclass 36, count 0 2006.257.13:49:55.39#ibcon#end of sib2, iclass 36, count 0 2006.257.13:49:55.39#ibcon#*mode == 0, iclass 36, count 0 2006.257.13:49:55.39#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.13:49:55.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:49:55.39#ibcon#*before write, iclass 36, count 0 2006.257.13:49:55.39#ibcon#enter sib2, iclass 36, count 0 2006.257.13:49:55.39#ibcon#flushed, iclass 36, count 0 2006.257.13:49:55.39#ibcon#about to write, iclass 36, count 0 2006.257.13:49:55.39#ibcon#wrote, iclass 36, count 0 2006.257.13:49:55.39#ibcon#about to read 3, iclass 36, count 0 2006.257.13:49:55.43#ibcon#read 3, iclass 36, count 0 2006.257.13:49:55.43#ibcon#about to read 4, iclass 36, count 0 2006.257.13:49:55.43#ibcon#read 4, iclass 36, count 0 2006.257.13:49:55.43#ibcon#about to read 5, iclass 36, count 0 2006.257.13:49:55.43#ibcon#read 5, iclass 36, count 0 2006.257.13:49:55.43#ibcon#about to read 6, iclass 36, count 0 2006.257.13:49:55.43#ibcon#read 6, iclass 36, count 0 2006.257.13:49:55.43#ibcon#end of sib2, iclass 36, count 0 2006.257.13:49:55.43#ibcon#*after write, iclass 36, count 0 2006.257.13:49:55.43#ibcon#*before return 0, iclass 36, count 0 2006.257.13:49:55.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:55.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.13:49:55.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.13:49:55.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.13:49:55.43$vck44/vb=8,4 2006.257.13:49:55.43#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.13:49:55.43#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.13:49:55.43#ibcon#ireg 11 cls_cnt 2 2006.257.13:49:55.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:55.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:55.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:55.49#ibcon#enter wrdev, iclass 38, count 2 2006.257.13:49:55.49#ibcon#first serial, iclass 38, count 2 2006.257.13:49:55.49#ibcon#enter sib2, iclass 38, count 2 2006.257.13:49:55.49#ibcon#flushed, iclass 38, count 2 2006.257.13:49:55.49#ibcon#about to write, iclass 38, count 2 2006.257.13:49:55.49#ibcon#wrote, iclass 38, count 2 2006.257.13:49:55.49#ibcon#about to read 3, iclass 38, count 2 2006.257.13:49:55.51#ibcon#read 3, iclass 38, count 2 2006.257.13:49:55.51#ibcon#about to read 4, iclass 38, count 2 2006.257.13:49:55.51#ibcon#read 4, iclass 38, count 2 2006.257.13:49:55.51#ibcon#about to read 5, iclass 38, count 2 2006.257.13:49:55.51#ibcon#read 5, iclass 38, count 2 2006.257.13:49:55.51#ibcon#about to read 6, iclass 38, count 2 2006.257.13:49:55.51#ibcon#read 6, iclass 38, count 2 2006.257.13:49:55.51#ibcon#end of sib2, iclass 38, count 2 2006.257.13:49:55.51#ibcon#*mode == 0, iclass 38, count 2 2006.257.13:49:55.51#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.13:49:55.51#ibcon#[27=AT08-04\r\n] 2006.257.13:49:55.51#ibcon#*before write, iclass 38, count 2 2006.257.13:49:55.51#ibcon#enter sib2, iclass 38, count 2 2006.257.13:49:55.51#ibcon#flushed, iclass 38, count 2 2006.257.13:49:55.51#ibcon#about to write, iclass 38, count 2 2006.257.13:49:55.51#ibcon#wrote, iclass 38, count 2 2006.257.13:49:55.51#ibcon#about to read 3, iclass 38, count 2 2006.257.13:49:55.54#ibcon#read 3, iclass 38, count 2 2006.257.13:49:55.54#ibcon#about to read 4, iclass 38, count 2 2006.257.13:49:55.55#ibcon#read 4, iclass 38, count 2 2006.257.13:49:55.55#ibcon#about to read 5, iclass 38, count 2 2006.257.13:49:55.55#ibcon#read 5, iclass 38, count 2 2006.257.13:49:55.55#ibcon#about to read 6, iclass 38, count 2 2006.257.13:49:55.55#ibcon#read 6, iclass 38, count 2 2006.257.13:49:55.55#ibcon#end of sib2, iclass 38, count 2 2006.257.13:49:55.55#ibcon#*after write, iclass 38, count 2 2006.257.13:49:55.55#ibcon#*before return 0, iclass 38, count 2 2006.257.13:49:55.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:55.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.13:49:55.55#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.13:49:55.55#ibcon#ireg 7 cls_cnt 0 2006.257.13:49:55.55#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:55.67#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:55.67#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:55.67#ibcon#enter wrdev, iclass 38, count 0 2006.257.13:49:55.67#ibcon#first serial, iclass 38, count 0 2006.257.13:49:55.67#ibcon#enter sib2, iclass 38, count 0 2006.257.13:49:55.67#ibcon#flushed, iclass 38, count 0 2006.257.13:49:55.67#ibcon#about to write, iclass 38, count 0 2006.257.13:49:55.67#ibcon#wrote, iclass 38, count 0 2006.257.13:49:55.67#ibcon#about to read 3, iclass 38, count 0 2006.257.13:49:55.69#ibcon#read 3, iclass 38, count 0 2006.257.13:49:55.69#ibcon#about to read 4, iclass 38, count 0 2006.257.13:49:55.69#ibcon#read 4, iclass 38, count 0 2006.257.13:49:55.69#ibcon#about to read 5, iclass 38, count 0 2006.257.13:49:55.69#ibcon#read 5, iclass 38, count 0 2006.257.13:49:55.69#ibcon#about to read 6, iclass 38, count 0 2006.257.13:49:55.69#ibcon#read 6, iclass 38, count 0 2006.257.13:49:55.69#ibcon#end of sib2, iclass 38, count 0 2006.257.13:49:55.69#ibcon#*mode == 0, iclass 38, count 0 2006.257.13:49:55.69#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.13:49:55.69#ibcon#[27=USB\r\n] 2006.257.13:49:55.69#ibcon#*before write, iclass 38, count 0 2006.257.13:49:55.69#ibcon#enter sib2, iclass 38, count 0 2006.257.13:49:55.69#ibcon#flushed, iclass 38, count 0 2006.257.13:49:55.69#ibcon#about to write, iclass 38, count 0 2006.257.13:49:55.69#ibcon#wrote, iclass 38, count 0 2006.257.13:49:55.69#ibcon#about to read 3, iclass 38, count 0 2006.257.13:49:55.72#ibcon#read 3, iclass 38, count 0 2006.257.13:49:55.72#ibcon#about to read 4, iclass 38, count 0 2006.257.13:49:55.72#ibcon#read 4, iclass 38, count 0 2006.257.13:49:55.72#ibcon#about to read 5, iclass 38, count 0 2006.257.13:49:55.72#ibcon#read 5, iclass 38, count 0 2006.257.13:49:55.72#ibcon#about to read 6, iclass 38, count 0 2006.257.13:49:55.72#ibcon#read 6, iclass 38, count 0 2006.257.13:49:55.72#ibcon#end of sib2, iclass 38, count 0 2006.257.13:49:55.72#ibcon#*after write, iclass 38, count 0 2006.257.13:49:55.72#ibcon#*before return 0, iclass 38, count 0 2006.257.13:49:55.72#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:55.72#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.13:49:55.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.13:49:55.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.13:49:55.72$vck44/vabw=wide 2006.257.13:49:55.72#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.13:49:55.72#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.13:49:55.72#ibcon#ireg 8 cls_cnt 0 2006.257.13:49:55.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:55.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:55.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:55.72#ibcon#enter wrdev, iclass 40, count 0 2006.257.13:49:55.72#ibcon#first serial, iclass 40, count 0 2006.257.13:49:55.72#ibcon#enter sib2, iclass 40, count 0 2006.257.13:49:55.72#ibcon#flushed, iclass 40, count 0 2006.257.13:49:55.72#ibcon#about to write, iclass 40, count 0 2006.257.13:49:55.72#ibcon#wrote, iclass 40, count 0 2006.257.13:49:55.72#ibcon#about to read 3, iclass 40, count 0 2006.257.13:49:55.74#ibcon#read 3, iclass 40, count 0 2006.257.13:49:55.74#ibcon#about to read 4, iclass 40, count 0 2006.257.13:49:55.74#ibcon#read 4, iclass 40, count 0 2006.257.13:49:55.74#ibcon#about to read 5, iclass 40, count 0 2006.257.13:49:55.74#ibcon#read 5, iclass 40, count 0 2006.257.13:49:55.74#ibcon#about to read 6, iclass 40, count 0 2006.257.13:49:55.74#ibcon#read 6, iclass 40, count 0 2006.257.13:49:55.74#ibcon#end of sib2, iclass 40, count 0 2006.257.13:49:55.74#ibcon#*mode == 0, iclass 40, count 0 2006.257.13:49:55.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.13:49:55.74#ibcon#[25=BW32\r\n] 2006.257.13:49:55.74#ibcon#*before write, iclass 40, count 0 2006.257.13:49:55.74#ibcon#enter sib2, iclass 40, count 0 2006.257.13:49:55.74#ibcon#flushed, iclass 40, count 0 2006.257.13:49:55.74#ibcon#about to write, iclass 40, count 0 2006.257.13:49:55.74#ibcon#wrote, iclass 40, count 0 2006.257.13:49:55.74#ibcon#about to read 3, iclass 40, count 0 2006.257.13:49:55.77#ibcon#read 3, iclass 40, count 0 2006.257.13:49:55.77#ibcon#about to read 4, iclass 40, count 0 2006.257.13:49:55.77#ibcon#read 4, iclass 40, count 0 2006.257.13:49:55.77#ibcon#about to read 5, iclass 40, count 0 2006.257.13:49:55.77#ibcon#read 5, iclass 40, count 0 2006.257.13:49:55.77#ibcon#about to read 6, iclass 40, count 0 2006.257.13:49:55.77#ibcon#read 6, iclass 40, count 0 2006.257.13:49:55.77#ibcon#end of sib2, iclass 40, count 0 2006.257.13:49:55.77#ibcon#*after write, iclass 40, count 0 2006.257.13:49:55.77#ibcon#*before return 0, iclass 40, count 0 2006.257.13:49:55.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:55.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.13:49:55.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.13:49:55.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.13:49:55.77$vck44/vbbw=wide 2006.257.13:49:55.77#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.13:49:55.77#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.13:49:55.77#ibcon#ireg 8 cls_cnt 0 2006.257.13:49:55.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:49:55.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:49:55.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:49:55.84#ibcon#enter wrdev, iclass 4, count 0 2006.257.13:49:55.84#ibcon#first serial, iclass 4, count 0 2006.257.13:49:55.84#ibcon#enter sib2, iclass 4, count 0 2006.257.13:49:55.84#ibcon#flushed, iclass 4, count 0 2006.257.13:49:55.84#ibcon#about to write, iclass 4, count 0 2006.257.13:49:55.84#ibcon#wrote, iclass 4, count 0 2006.257.13:49:55.84#ibcon#about to read 3, iclass 4, count 0 2006.257.13:49:55.86#ibcon#read 3, iclass 4, count 0 2006.257.13:49:55.86#ibcon#about to read 4, iclass 4, count 0 2006.257.13:49:55.86#ibcon#read 4, iclass 4, count 0 2006.257.13:49:55.86#ibcon#about to read 5, iclass 4, count 0 2006.257.13:49:55.86#ibcon#read 5, iclass 4, count 0 2006.257.13:49:55.86#ibcon#about to read 6, iclass 4, count 0 2006.257.13:49:55.86#ibcon#read 6, iclass 4, count 0 2006.257.13:49:55.86#ibcon#end of sib2, iclass 4, count 0 2006.257.13:49:55.86#ibcon#*mode == 0, iclass 4, count 0 2006.257.13:49:55.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.13:49:55.86#ibcon#[27=BW32\r\n] 2006.257.13:49:55.86#ibcon#*before write, iclass 4, count 0 2006.257.13:49:55.86#ibcon#enter sib2, iclass 4, count 0 2006.257.13:49:55.86#ibcon#flushed, iclass 4, count 0 2006.257.13:49:55.86#ibcon#about to write, iclass 4, count 0 2006.257.13:49:55.86#ibcon#wrote, iclass 4, count 0 2006.257.13:49:55.86#ibcon#about to read 3, iclass 4, count 0 2006.257.13:49:55.89#ibcon#read 3, iclass 4, count 0 2006.257.13:49:55.89#ibcon#about to read 4, iclass 4, count 0 2006.257.13:49:55.89#ibcon#read 4, iclass 4, count 0 2006.257.13:49:55.89#ibcon#about to read 5, iclass 4, count 0 2006.257.13:49:55.89#ibcon#read 5, iclass 4, count 0 2006.257.13:49:55.89#ibcon#about to read 6, iclass 4, count 0 2006.257.13:49:55.89#ibcon#read 6, iclass 4, count 0 2006.257.13:49:55.89#ibcon#end of sib2, iclass 4, count 0 2006.257.13:49:55.89#ibcon#*after write, iclass 4, count 0 2006.257.13:49:55.89#ibcon#*before return 0, iclass 4, count 0 2006.257.13:49:55.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:49:55.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.13:49:55.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.13:49:55.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.13:49:55.89$setupk4/ifdk4 2006.257.13:49:55.89$ifdk4/lo= 2006.257.13:49:55.89$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:49:55.89$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:49:55.89$ifdk4/patch= 2006.257.13:49:55.89$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:49:55.89$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:49:55.89$setupk4/!*+20s 2006.257.13:50:03.66#abcon#<5=/14 1.5 4.1 17.56 971014.0\r\n> 2006.257.13:50:03.69#abcon#{5=INTERFACE CLEAR} 2006.257.13:50:03.75#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:50:10.25$setupk4/"tpicd 2006.257.13:50:10.25$setupk4/echo=off 2006.257.13:50:10.25$setupk4/xlog=off 2006.257.13:50:10.25:!2006.257.13:51:46 2006.257.13:50:12.14#trakl#Source acquired 2006.257.13:50:12.14#flagr#flagr/antenna,acquired 2006.257.13:51:46.02:preob 2006.257.13:51:47.15/onsource/TRACKING 2006.257.13:51:47.15:!2006.257.13:51:56 2006.257.13:51:56.02:"tape 2006.257.13:51:56.02:"st=record 2006.257.13:51:56.02:data_valid=on 2006.257.13:51:56.02:midob 2006.257.13:51:57.15/onsource/TRACKING 2006.257.13:51:57.15/wx/17.57,1014.1,97 2006.257.13:51:57.23/cable/+6.4817E-03 2006.257.13:51:58.32/va/01,08,usb,yes,30,33 2006.257.13:51:58.32/va/02,07,usb,yes,33,33 2006.257.13:51:58.32/va/03,08,usb,yes,29,31 2006.257.13:51:58.32/va/04,07,usb,yes,34,35 2006.257.13:51:58.32/va/05,04,usb,yes,30,31 2006.257.13:51:58.32/va/06,04,usb,yes,34,33 2006.257.13:51:58.32/va/07,04,usb,yes,35,35 2006.257.13:51:58.32/va/08,04,usb,yes,29,35 2006.257.13:51:58.55/valo/01,524.99,yes,locked 2006.257.13:51:58.55/valo/02,534.99,yes,locked 2006.257.13:51:58.55/valo/03,564.99,yes,locked 2006.257.13:51:58.55/valo/04,624.99,yes,locked 2006.257.13:51:58.55/valo/05,734.99,yes,locked 2006.257.13:51:58.55/valo/06,814.99,yes,locked 2006.257.13:51:58.55/valo/07,864.99,yes,locked 2006.257.13:51:58.55/valo/08,884.99,yes,locked 2006.257.13:51:59.64/vb/01,04,usb,yes,30,28 2006.257.13:51:59.64/vb/02,05,usb,yes,28,28 2006.257.13:51:59.64/vb/03,04,usb,yes,29,32 2006.257.13:51:59.64/vb/04,05,usb,yes,30,28 2006.257.13:51:59.64/vb/05,04,usb,yes,26,31 2006.257.13:51:59.64/vb/06,04,usb,yes,31,29 2006.257.13:51:59.64/vb/07,04,usb,yes,30,30 2006.257.13:51:59.64/vb/08,04,usb,yes,28,31 2006.257.13:51:59.88/vblo/01,629.99,yes,locked 2006.257.13:51:59.88/vblo/02,634.99,yes,locked 2006.257.13:51:59.88/vblo/03,649.99,yes,locked 2006.257.13:51:59.88/vblo/04,679.99,yes,locked 2006.257.13:51:59.88/vblo/05,709.99,yes,locked 2006.257.13:51:59.88/vblo/06,719.99,yes,locked 2006.257.13:51:59.88/vblo/07,734.99,yes,locked 2006.257.13:51:59.88/vblo/08,744.99,yes,locked 2006.257.13:52:00.03/vabw/8 2006.257.13:52:00.18/vbbw/8 2006.257.13:52:00.27/xfe/off,on,16.0 2006.257.13:52:00.64/ifatt/23,28,28,28 2006.257.13:52:01.07/fmout-gps/S +4.58E-07 2006.257.13:52:01.12:!2006.257.13:53:06 2006.257.13:53:06.02:data_valid=off 2006.257.13:53:06.02:"et 2006.257.13:53:06.02:!+3s 2006.257.13:53:09.03:"tape 2006.257.13:53:09.04:postob 2006.257.13:53:09.19/cable/+6.4827E-03 2006.257.13:53:09.20/wx/17.57,1014.1,97 2006.257.13:53:09.25/fmout-gps/S +4.58E-07 2006.257.13:53:09.26:scan_name=257-1357,jd0609,100 2006.257.13:53:09.26:source=2128-123,213135.26,-120704.8,2000.0,ccw 2006.257.13:53:10.15#flagr#flagr/antenna,new-source 2006.257.13:53:10.15:checkk5 2006.257.13:53:10.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:53:10.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:53:11.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:53:11.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:53:12.16/chk_obsdata//k5ts1/T2571351??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.13:53:12.55/chk_obsdata//k5ts2/T2571351??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.13:53:12.95/chk_obsdata//k5ts3/T2571351??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.13:53:13.35/chk_obsdata//k5ts4/T2571351??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.13:53:14.07/k5log//k5ts1_log_newline 2006.257.13:53:14.79/k5log//k5ts2_log_newline 2006.257.13:53:15.52/k5log//k5ts3_log_newline 2006.257.13:53:16.24/k5log//k5ts4_log_newline 2006.257.13:53:16.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:53:16.27:setupk4=1 2006.257.13:53:16.27$setupk4/echo=on 2006.257.13:53:16.27$setupk4/pcalon 2006.257.13:53:16.27$pcalon/"no phase cal control is implemented here 2006.257.13:53:16.27$setupk4/"tpicd=stop 2006.257.13:53:16.27$setupk4/"rec=synch_on 2006.257.13:53:16.27$setupk4/"rec_mode=128 2006.257.13:53:16.27$setupk4/!* 2006.257.13:53:16.27$setupk4/recpk4 2006.257.13:53:16.27$recpk4/recpatch= 2006.257.13:53:16.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:53:16.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:53:16.27$setupk4/vck44 2006.257.13:53:16.27$vck44/valo=1,524.99 2006.257.13:53:16.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.13:53:16.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.13:53:16.27#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:16.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:16.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:16.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:16.27#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:53:16.27#ibcon#first serial, iclass 15, count 0 2006.257.13:53:16.27#ibcon#enter sib2, iclass 15, count 0 2006.257.13:53:16.27#ibcon#flushed, iclass 15, count 0 2006.257.13:53:16.27#ibcon#about to write, iclass 15, count 0 2006.257.13:53:16.27#ibcon#wrote, iclass 15, count 0 2006.257.13:53:16.27#ibcon#about to read 3, iclass 15, count 0 2006.257.13:53:16.28#ibcon#read 3, iclass 15, count 0 2006.257.13:53:16.28#ibcon#about to read 4, iclass 15, count 0 2006.257.13:53:16.28#ibcon#read 4, iclass 15, count 0 2006.257.13:53:16.28#ibcon#about to read 5, iclass 15, count 0 2006.257.13:53:16.28#ibcon#read 5, iclass 15, count 0 2006.257.13:53:16.28#ibcon#about to read 6, iclass 15, count 0 2006.257.13:53:16.28#ibcon#read 6, iclass 15, count 0 2006.257.13:53:16.28#ibcon#end of sib2, iclass 15, count 0 2006.257.13:53:16.28#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:53:16.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:53:16.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:53:16.28#ibcon#*before write, iclass 15, count 0 2006.257.13:53:16.28#ibcon#enter sib2, iclass 15, count 0 2006.257.13:53:16.28#ibcon#flushed, iclass 15, count 0 2006.257.13:53:16.28#ibcon#about to write, iclass 15, count 0 2006.257.13:53:16.28#ibcon#wrote, iclass 15, count 0 2006.257.13:53:16.28#ibcon#about to read 3, iclass 15, count 0 2006.257.13:53:16.33#ibcon#read 3, iclass 15, count 0 2006.257.13:53:16.33#ibcon#about to read 4, iclass 15, count 0 2006.257.13:53:16.33#ibcon#read 4, iclass 15, count 0 2006.257.13:53:16.33#ibcon#about to read 5, iclass 15, count 0 2006.257.13:53:16.33#ibcon#read 5, iclass 15, count 0 2006.257.13:53:16.33#ibcon#about to read 6, iclass 15, count 0 2006.257.13:53:16.33#ibcon#read 6, iclass 15, count 0 2006.257.13:53:16.33#ibcon#end of sib2, iclass 15, count 0 2006.257.13:53:16.33#ibcon#*after write, iclass 15, count 0 2006.257.13:53:16.33#ibcon#*before return 0, iclass 15, count 0 2006.257.13:53:16.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:16.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:16.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:53:16.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:53:16.33$vck44/va=1,8 2006.257.13:53:16.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.13:53:16.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.13:53:16.33#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:16.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:16.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:16.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:16.33#ibcon#enter wrdev, iclass 17, count 2 2006.257.13:53:16.33#ibcon#first serial, iclass 17, count 2 2006.257.13:53:16.33#ibcon#enter sib2, iclass 17, count 2 2006.257.13:53:16.33#ibcon#flushed, iclass 17, count 2 2006.257.13:53:16.33#ibcon#about to write, iclass 17, count 2 2006.257.13:53:16.34#ibcon#wrote, iclass 17, count 2 2006.257.13:53:16.34#ibcon#about to read 3, iclass 17, count 2 2006.257.13:53:16.35#ibcon#read 3, iclass 17, count 2 2006.257.13:53:16.35#ibcon#about to read 4, iclass 17, count 2 2006.257.13:53:16.35#ibcon#read 4, iclass 17, count 2 2006.257.13:53:16.35#ibcon#about to read 5, iclass 17, count 2 2006.257.13:53:16.35#ibcon#read 5, iclass 17, count 2 2006.257.13:53:16.35#ibcon#about to read 6, iclass 17, count 2 2006.257.13:53:16.35#ibcon#read 6, iclass 17, count 2 2006.257.13:53:16.35#ibcon#end of sib2, iclass 17, count 2 2006.257.13:53:16.35#ibcon#*mode == 0, iclass 17, count 2 2006.257.13:53:16.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.13:53:16.35#ibcon#[25=AT01-08\r\n] 2006.257.13:53:16.35#ibcon#*before write, iclass 17, count 2 2006.257.13:53:16.35#ibcon#enter sib2, iclass 17, count 2 2006.257.13:53:16.35#ibcon#flushed, iclass 17, count 2 2006.257.13:53:16.35#ibcon#about to write, iclass 17, count 2 2006.257.13:53:16.35#ibcon#wrote, iclass 17, count 2 2006.257.13:53:16.35#ibcon#about to read 3, iclass 17, count 2 2006.257.13:53:16.38#ibcon#read 3, iclass 17, count 2 2006.257.13:53:16.38#ibcon#about to read 4, iclass 17, count 2 2006.257.13:53:16.38#ibcon#read 4, iclass 17, count 2 2006.257.13:53:16.38#ibcon#about to read 5, iclass 17, count 2 2006.257.13:53:16.38#ibcon#read 5, iclass 17, count 2 2006.257.13:53:16.38#ibcon#about to read 6, iclass 17, count 2 2006.257.13:53:16.38#ibcon#read 6, iclass 17, count 2 2006.257.13:53:16.38#ibcon#end of sib2, iclass 17, count 2 2006.257.13:53:16.38#ibcon#*after write, iclass 17, count 2 2006.257.13:53:16.38#ibcon#*before return 0, iclass 17, count 2 2006.257.13:53:16.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:16.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:16.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.13:53:16.38#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:16.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:16.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:16.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:16.50#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:53:16.50#ibcon#first serial, iclass 17, count 0 2006.257.13:53:16.50#ibcon#enter sib2, iclass 17, count 0 2006.257.13:53:16.50#ibcon#flushed, iclass 17, count 0 2006.257.13:53:16.50#ibcon#about to write, iclass 17, count 0 2006.257.13:53:16.50#ibcon#wrote, iclass 17, count 0 2006.257.13:53:16.50#ibcon#about to read 3, iclass 17, count 0 2006.257.13:53:16.52#ibcon#read 3, iclass 17, count 0 2006.257.13:53:16.52#ibcon#about to read 4, iclass 17, count 0 2006.257.13:53:16.52#ibcon#read 4, iclass 17, count 0 2006.257.13:53:16.52#ibcon#about to read 5, iclass 17, count 0 2006.257.13:53:16.52#ibcon#read 5, iclass 17, count 0 2006.257.13:53:16.52#ibcon#about to read 6, iclass 17, count 0 2006.257.13:53:16.52#ibcon#read 6, iclass 17, count 0 2006.257.13:53:16.52#ibcon#end of sib2, iclass 17, count 0 2006.257.13:53:16.52#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:53:16.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:53:16.52#ibcon#[25=USB\r\n] 2006.257.13:53:16.52#ibcon#*before write, iclass 17, count 0 2006.257.13:53:16.52#ibcon#enter sib2, iclass 17, count 0 2006.257.13:53:16.52#ibcon#flushed, iclass 17, count 0 2006.257.13:53:16.52#ibcon#about to write, iclass 17, count 0 2006.257.13:53:16.52#ibcon#wrote, iclass 17, count 0 2006.257.13:53:16.52#ibcon#about to read 3, iclass 17, count 0 2006.257.13:53:16.55#ibcon#read 3, iclass 17, count 0 2006.257.13:53:16.55#ibcon#about to read 4, iclass 17, count 0 2006.257.13:53:16.55#ibcon#read 4, iclass 17, count 0 2006.257.13:53:16.55#ibcon#about to read 5, iclass 17, count 0 2006.257.13:53:16.55#ibcon#read 5, iclass 17, count 0 2006.257.13:53:16.55#ibcon#about to read 6, iclass 17, count 0 2006.257.13:53:16.55#ibcon#read 6, iclass 17, count 0 2006.257.13:53:16.55#ibcon#end of sib2, iclass 17, count 0 2006.257.13:53:16.55#ibcon#*after write, iclass 17, count 0 2006.257.13:53:16.55#ibcon#*before return 0, iclass 17, count 0 2006.257.13:53:16.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:16.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:16.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:53:16.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:53:16.55$vck44/valo=2,534.99 2006.257.13:53:16.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.13:53:16.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.13:53:16.55#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:16.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:16.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:16.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:16.55#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:53:16.55#ibcon#first serial, iclass 19, count 0 2006.257.13:53:16.55#ibcon#enter sib2, iclass 19, count 0 2006.257.13:53:16.55#ibcon#flushed, iclass 19, count 0 2006.257.13:53:16.55#ibcon#about to write, iclass 19, count 0 2006.257.13:53:16.55#ibcon#wrote, iclass 19, count 0 2006.257.13:53:16.56#ibcon#about to read 3, iclass 19, count 0 2006.257.13:53:16.57#ibcon#read 3, iclass 19, count 0 2006.257.13:53:16.57#ibcon#about to read 4, iclass 19, count 0 2006.257.13:53:16.57#ibcon#read 4, iclass 19, count 0 2006.257.13:53:16.57#ibcon#about to read 5, iclass 19, count 0 2006.257.13:53:16.57#ibcon#read 5, iclass 19, count 0 2006.257.13:53:16.57#ibcon#about to read 6, iclass 19, count 0 2006.257.13:53:16.57#ibcon#read 6, iclass 19, count 0 2006.257.13:53:16.57#ibcon#end of sib2, iclass 19, count 0 2006.257.13:53:16.57#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:53:16.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:53:16.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:53:16.57#ibcon#*before write, iclass 19, count 0 2006.257.13:53:16.57#ibcon#enter sib2, iclass 19, count 0 2006.257.13:53:16.57#ibcon#flushed, iclass 19, count 0 2006.257.13:53:16.57#ibcon#about to write, iclass 19, count 0 2006.257.13:53:16.57#ibcon#wrote, iclass 19, count 0 2006.257.13:53:16.57#ibcon#about to read 3, iclass 19, count 0 2006.257.13:53:16.61#ibcon#read 3, iclass 19, count 0 2006.257.13:53:16.61#ibcon#about to read 4, iclass 19, count 0 2006.257.13:53:16.61#ibcon#read 4, iclass 19, count 0 2006.257.13:53:16.61#ibcon#about to read 5, iclass 19, count 0 2006.257.13:53:16.61#ibcon#read 5, iclass 19, count 0 2006.257.13:53:16.61#ibcon#about to read 6, iclass 19, count 0 2006.257.13:53:16.61#ibcon#read 6, iclass 19, count 0 2006.257.13:53:16.61#ibcon#end of sib2, iclass 19, count 0 2006.257.13:53:16.61#ibcon#*after write, iclass 19, count 0 2006.257.13:53:16.61#ibcon#*before return 0, iclass 19, count 0 2006.257.13:53:16.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:16.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:16.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:53:16.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:53:16.61$vck44/va=2,7 2006.257.13:53:16.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.13:53:16.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.13:53:16.61#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:16.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:16.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:16.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:16.67#ibcon#enter wrdev, iclass 21, count 2 2006.257.13:53:16.67#ibcon#first serial, iclass 21, count 2 2006.257.13:53:16.67#ibcon#enter sib2, iclass 21, count 2 2006.257.13:53:16.67#ibcon#flushed, iclass 21, count 2 2006.257.13:53:16.67#ibcon#about to write, iclass 21, count 2 2006.257.13:53:16.67#ibcon#wrote, iclass 21, count 2 2006.257.13:53:16.67#ibcon#about to read 3, iclass 21, count 2 2006.257.13:53:16.69#ibcon#read 3, iclass 21, count 2 2006.257.13:53:16.69#ibcon#about to read 4, iclass 21, count 2 2006.257.13:53:16.69#ibcon#read 4, iclass 21, count 2 2006.257.13:53:16.69#ibcon#about to read 5, iclass 21, count 2 2006.257.13:53:16.69#ibcon#read 5, iclass 21, count 2 2006.257.13:53:16.69#ibcon#about to read 6, iclass 21, count 2 2006.257.13:53:16.69#ibcon#read 6, iclass 21, count 2 2006.257.13:53:16.69#ibcon#end of sib2, iclass 21, count 2 2006.257.13:53:16.69#ibcon#*mode == 0, iclass 21, count 2 2006.257.13:53:16.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.13:53:16.69#ibcon#[25=AT02-07\r\n] 2006.257.13:53:16.69#ibcon#*before write, iclass 21, count 2 2006.257.13:53:16.69#ibcon#enter sib2, iclass 21, count 2 2006.257.13:53:16.69#ibcon#flushed, iclass 21, count 2 2006.257.13:53:16.69#ibcon#about to write, iclass 21, count 2 2006.257.13:53:16.69#ibcon#wrote, iclass 21, count 2 2006.257.13:53:16.69#ibcon#about to read 3, iclass 21, count 2 2006.257.13:53:16.72#ibcon#read 3, iclass 21, count 2 2006.257.13:53:16.72#ibcon#about to read 4, iclass 21, count 2 2006.257.13:53:16.72#ibcon#read 4, iclass 21, count 2 2006.257.13:53:16.72#ibcon#about to read 5, iclass 21, count 2 2006.257.13:53:16.72#ibcon#read 5, iclass 21, count 2 2006.257.13:53:16.72#ibcon#about to read 6, iclass 21, count 2 2006.257.13:53:16.72#ibcon#read 6, iclass 21, count 2 2006.257.13:53:16.72#ibcon#end of sib2, iclass 21, count 2 2006.257.13:53:16.72#ibcon#*after write, iclass 21, count 2 2006.257.13:53:16.72#ibcon#*before return 0, iclass 21, count 2 2006.257.13:53:16.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:16.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:16.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.13:53:16.72#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:16.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:16.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:16.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:16.84#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:53:16.84#ibcon#first serial, iclass 21, count 0 2006.257.13:53:16.84#ibcon#enter sib2, iclass 21, count 0 2006.257.13:53:16.84#ibcon#flushed, iclass 21, count 0 2006.257.13:53:16.84#ibcon#about to write, iclass 21, count 0 2006.257.13:53:16.84#ibcon#wrote, iclass 21, count 0 2006.257.13:53:16.84#ibcon#about to read 3, iclass 21, count 0 2006.257.13:53:16.86#ibcon#read 3, iclass 21, count 0 2006.257.13:53:16.86#ibcon#about to read 4, iclass 21, count 0 2006.257.13:53:16.86#ibcon#read 4, iclass 21, count 0 2006.257.13:53:16.86#ibcon#about to read 5, iclass 21, count 0 2006.257.13:53:16.86#ibcon#read 5, iclass 21, count 0 2006.257.13:53:16.86#ibcon#about to read 6, iclass 21, count 0 2006.257.13:53:16.86#ibcon#read 6, iclass 21, count 0 2006.257.13:53:16.86#ibcon#end of sib2, iclass 21, count 0 2006.257.13:53:16.86#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:53:16.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:53:16.86#ibcon#[25=USB\r\n] 2006.257.13:53:16.86#ibcon#*before write, iclass 21, count 0 2006.257.13:53:16.86#ibcon#enter sib2, iclass 21, count 0 2006.257.13:53:16.86#ibcon#flushed, iclass 21, count 0 2006.257.13:53:16.86#ibcon#about to write, iclass 21, count 0 2006.257.13:53:16.86#ibcon#wrote, iclass 21, count 0 2006.257.13:53:16.86#ibcon#about to read 3, iclass 21, count 0 2006.257.13:53:16.89#abcon#<5=/14 1.6 4.1 17.58 971014.1\r\n> 2006.257.13:53:16.89#ibcon#read 3, iclass 21, count 0 2006.257.13:53:16.89#ibcon#about to read 4, iclass 21, count 0 2006.257.13:53:16.89#ibcon#read 4, iclass 21, count 0 2006.257.13:53:16.89#ibcon#about to read 5, iclass 21, count 0 2006.257.13:53:16.89#ibcon#read 5, iclass 21, count 0 2006.257.13:53:16.89#ibcon#about to read 6, iclass 21, count 0 2006.257.13:53:16.89#ibcon#read 6, iclass 21, count 0 2006.257.13:53:16.89#ibcon#end of sib2, iclass 21, count 0 2006.257.13:53:16.89#ibcon#*after write, iclass 21, count 0 2006.257.13:53:16.89#ibcon#*before return 0, iclass 21, count 0 2006.257.13:53:16.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:16.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:16.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:53:16.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:53:16.89$vck44/valo=3,564.99 2006.257.13:53:16.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.13:53:16.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.13:53:16.90#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:16.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:53:16.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:53:16.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:53:16.90#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:53:16.90#ibcon#first serial, iclass 26, count 0 2006.257.13:53:16.90#ibcon#enter sib2, iclass 26, count 0 2006.257.13:53:16.90#ibcon#flushed, iclass 26, count 0 2006.257.13:53:16.90#ibcon#about to write, iclass 26, count 0 2006.257.13:53:16.90#ibcon#wrote, iclass 26, count 0 2006.257.13:53:16.90#ibcon#about to read 3, iclass 26, count 0 2006.257.13:53:16.91#abcon#{5=INTERFACE CLEAR} 2006.257.13:53:16.91#ibcon#read 3, iclass 26, count 0 2006.257.13:53:16.91#ibcon#about to read 4, iclass 26, count 0 2006.257.13:53:16.91#ibcon#read 4, iclass 26, count 0 2006.257.13:53:16.91#ibcon#about to read 5, iclass 26, count 0 2006.257.13:53:16.91#ibcon#read 5, iclass 26, count 0 2006.257.13:53:16.91#ibcon#about to read 6, iclass 26, count 0 2006.257.13:53:16.91#ibcon#read 6, iclass 26, count 0 2006.257.13:53:16.91#ibcon#end of sib2, iclass 26, count 0 2006.257.13:53:16.91#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:53:16.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:53:16.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:53:16.91#ibcon#*before write, iclass 26, count 0 2006.257.13:53:16.91#ibcon#enter sib2, iclass 26, count 0 2006.257.13:53:16.91#ibcon#flushed, iclass 26, count 0 2006.257.13:53:16.91#ibcon#about to write, iclass 26, count 0 2006.257.13:53:16.91#ibcon#wrote, iclass 26, count 0 2006.257.13:53:16.91#ibcon#about to read 3, iclass 26, count 0 2006.257.13:53:16.95#ibcon#read 3, iclass 26, count 0 2006.257.13:53:16.95#ibcon#about to read 4, iclass 26, count 0 2006.257.13:53:16.95#ibcon#read 4, iclass 26, count 0 2006.257.13:53:16.95#ibcon#about to read 5, iclass 26, count 0 2006.257.13:53:16.95#ibcon#read 5, iclass 26, count 0 2006.257.13:53:16.95#ibcon#about to read 6, iclass 26, count 0 2006.257.13:53:16.95#ibcon#read 6, iclass 26, count 0 2006.257.13:53:16.95#ibcon#end of sib2, iclass 26, count 0 2006.257.13:53:16.95#ibcon#*after write, iclass 26, count 0 2006.257.13:53:16.95#ibcon#*before return 0, iclass 26, count 0 2006.257.13:53:16.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:53:16.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:53:16.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:53:16.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:53:16.95$vck44/va=3,8 2006.257.13:53:16.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.13:53:16.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.13:53:16.95#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:16.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:53:16.97#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:53:17.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:53:17.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:53:17.01#ibcon#enter wrdev, iclass 28, count 2 2006.257.13:53:17.01#ibcon#first serial, iclass 28, count 2 2006.257.13:53:17.01#ibcon#enter sib2, iclass 28, count 2 2006.257.13:53:17.01#ibcon#flushed, iclass 28, count 2 2006.257.13:53:17.01#ibcon#about to write, iclass 28, count 2 2006.257.13:53:17.01#ibcon#wrote, iclass 28, count 2 2006.257.13:53:17.01#ibcon#about to read 3, iclass 28, count 2 2006.257.13:53:17.03#ibcon#read 3, iclass 28, count 2 2006.257.13:53:17.03#ibcon#about to read 4, iclass 28, count 2 2006.257.13:53:17.03#ibcon#read 4, iclass 28, count 2 2006.257.13:53:17.03#ibcon#about to read 5, iclass 28, count 2 2006.257.13:53:17.03#ibcon#read 5, iclass 28, count 2 2006.257.13:53:17.03#ibcon#about to read 6, iclass 28, count 2 2006.257.13:53:17.03#ibcon#read 6, iclass 28, count 2 2006.257.13:53:17.03#ibcon#end of sib2, iclass 28, count 2 2006.257.13:53:17.03#ibcon#*mode == 0, iclass 28, count 2 2006.257.13:53:17.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.13:53:17.03#ibcon#[25=AT03-08\r\n] 2006.257.13:53:17.03#ibcon#*before write, iclass 28, count 2 2006.257.13:53:17.03#ibcon#enter sib2, iclass 28, count 2 2006.257.13:53:17.03#ibcon#flushed, iclass 28, count 2 2006.257.13:53:17.03#ibcon#about to write, iclass 28, count 2 2006.257.13:53:17.03#ibcon#wrote, iclass 28, count 2 2006.257.13:53:17.03#ibcon#about to read 3, iclass 28, count 2 2006.257.13:53:17.06#ibcon#read 3, iclass 28, count 2 2006.257.13:53:17.06#ibcon#about to read 4, iclass 28, count 2 2006.257.13:53:17.06#ibcon#read 4, iclass 28, count 2 2006.257.13:53:17.06#ibcon#about to read 5, iclass 28, count 2 2006.257.13:53:17.06#ibcon#read 5, iclass 28, count 2 2006.257.13:53:17.06#ibcon#about to read 6, iclass 28, count 2 2006.257.13:53:17.06#ibcon#read 6, iclass 28, count 2 2006.257.13:53:17.06#ibcon#end of sib2, iclass 28, count 2 2006.257.13:53:17.06#ibcon#*after write, iclass 28, count 2 2006.257.13:53:17.06#ibcon#*before return 0, iclass 28, count 2 2006.257.13:53:17.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:53:17.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.13:53:17.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.13:53:17.06#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:17.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:53:17.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:53:17.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:53:17.18#ibcon#enter wrdev, iclass 28, count 0 2006.257.13:53:17.18#ibcon#first serial, iclass 28, count 0 2006.257.13:53:17.18#ibcon#enter sib2, iclass 28, count 0 2006.257.13:53:17.18#ibcon#flushed, iclass 28, count 0 2006.257.13:53:17.18#ibcon#about to write, iclass 28, count 0 2006.257.13:53:17.18#ibcon#wrote, iclass 28, count 0 2006.257.13:53:17.18#ibcon#about to read 3, iclass 28, count 0 2006.257.13:53:17.20#ibcon#read 3, iclass 28, count 0 2006.257.13:53:17.20#ibcon#about to read 4, iclass 28, count 0 2006.257.13:53:17.20#ibcon#read 4, iclass 28, count 0 2006.257.13:53:17.20#ibcon#about to read 5, iclass 28, count 0 2006.257.13:53:17.20#ibcon#read 5, iclass 28, count 0 2006.257.13:53:17.20#ibcon#about to read 6, iclass 28, count 0 2006.257.13:53:17.20#ibcon#read 6, iclass 28, count 0 2006.257.13:53:17.20#ibcon#end of sib2, iclass 28, count 0 2006.257.13:53:17.20#ibcon#*mode == 0, iclass 28, count 0 2006.257.13:53:17.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.13:53:17.20#ibcon#[25=USB\r\n] 2006.257.13:53:17.20#ibcon#*before write, iclass 28, count 0 2006.257.13:53:17.20#ibcon#enter sib2, iclass 28, count 0 2006.257.13:53:17.20#ibcon#flushed, iclass 28, count 0 2006.257.13:53:17.20#ibcon#about to write, iclass 28, count 0 2006.257.13:53:17.20#ibcon#wrote, iclass 28, count 0 2006.257.13:53:17.20#ibcon#about to read 3, iclass 28, count 0 2006.257.13:53:17.23#ibcon#read 3, iclass 28, count 0 2006.257.13:53:17.23#ibcon#about to read 4, iclass 28, count 0 2006.257.13:53:17.23#ibcon#read 4, iclass 28, count 0 2006.257.13:53:17.23#ibcon#about to read 5, iclass 28, count 0 2006.257.13:53:17.23#ibcon#read 5, iclass 28, count 0 2006.257.13:53:17.23#ibcon#about to read 6, iclass 28, count 0 2006.257.13:53:17.23#ibcon#read 6, iclass 28, count 0 2006.257.13:53:17.23#ibcon#end of sib2, iclass 28, count 0 2006.257.13:53:17.23#ibcon#*after write, iclass 28, count 0 2006.257.13:53:17.23#ibcon#*before return 0, iclass 28, count 0 2006.257.13:53:17.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:53:17.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.13:53:17.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.13:53:17.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.13:53:17.23$vck44/valo=4,624.99 2006.257.13:53:17.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.13:53:17.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.13:53:17.23#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:17.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:17.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:17.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:17.23#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:53:17.23#ibcon#first serial, iclass 31, count 0 2006.257.13:53:17.23#ibcon#enter sib2, iclass 31, count 0 2006.257.13:53:17.23#ibcon#flushed, iclass 31, count 0 2006.257.13:53:17.23#ibcon#about to write, iclass 31, count 0 2006.257.13:53:17.24#ibcon#wrote, iclass 31, count 0 2006.257.13:53:17.24#ibcon#about to read 3, iclass 31, count 0 2006.257.13:53:17.25#ibcon#read 3, iclass 31, count 0 2006.257.13:53:17.25#ibcon#about to read 4, iclass 31, count 0 2006.257.13:53:17.25#ibcon#read 4, iclass 31, count 0 2006.257.13:53:17.25#ibcon#about to read 5, iclass 31, count 0 2006.257.13:53:17.25#ibcon#read 5, iclass 31, count 0 2006.257.13:53:17.25#ibcon#about to read 6, iclass 31, count 0 2006.257.13:53:17.25#ibcon#read 6, iclass 31, count 0 2006.257.13:53:17.25#ibcon#end of sib2, iclass 31, count 0 2006.257.13:53:17.25#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:53:17.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:53:17.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:53:17.25#ibcon#*before write, iclass 31, count 0 2006.257.13:53:17.25#ibcon#enter sib2, iclass 31, count 0 2006.257.13:53:17.25#ibcon#flushed, iclass 31, count 0 2006.257.13:53:17.25#ibcon#about to write, iclass 31, count 0 2006.257.13:53:17.25#ibcon#wrote, iclass 31, count 0 2006.257.13:53:17.25#ibcon#about to read 3, iclass 31, count 0 2006.257.13:53:17.29#ibcon#read 3, iclass 31, count 0 2006.257.13:53:17.29#ibcon#about to read 4, iclass 31, count 0 2006.257.13:53:17.29#ibcon#read 4, iclass 31, count 0 2006.257.13:53:17.29#ibcon#about to read 5, iclass 31, count 0 2006.257.13:53:17.29#ibcon#read 5, iclass 31, count 0 2006.257.13:53:17.29#ibcon#about to read 6, iclass 31, count 0 2006.257.13:53:17.29#ibcon#read 6, iclass 31, count 0 2006.257.13:53:17.29#ibcon#end of sib2, iclass 31, count 0 2006.257.13:53:17.29#ibcon#*after write, iclass 31, count 0 2006.257.13:53:17.29#ibcon#*before return 0, iclass 31, count 0 2006.257.13:53:17.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:17.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:17.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:53:17.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:53:17.29$vck44/va=4,7 2006.257.13:53:17.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.13:53:17.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.13:53:17.29#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:17.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:17.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:17.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:17.35#ibcon#enter wrdev, iclass 33, count 2 2006.257.13:53:17.35#ibcon#first serial, iclass 33, count 2 2006.257.13:53:17.35#ibcon#enter sib2, iclass 33, count 2 2006.257.13:53:17.35#ibcon#flushed, iclass 33, count 2 2006.257.13:53:17.35#ibcon#about to write, iclass 33, count 2 2006.257.13:53:17.35#ibcon#wrote, iclass 33, count 2 2006.257.13:53:17.35#ibcon#about to read 3, iclass 33, count 2 2006.257.13:53:17.37#ibcon#read 3, iclass 33, count 2 2006.257.13:53:17.37#ibcon#about to read 4, iclass 33, count 2 2006.257.13:53:17.37#ibcon#read 4, iclass 33, count 2 2006.257.13:53:17.37#ibcon#about to read 5, iclass 33, count 2 2006.257.13:53:17.37#ibcon#read 5, iclass 33, count 2 2006.257.13:53:17.37#ibcon#about to read 6, iclass 33, count 2 2006.257.13:53:17.37#ibcon#read 6, iclass 33, count 2 2006.257.13:53:17.37#ibcon#end of sib2, iclass 33, count 2 2006.257.13:53:17.37#ibcon#*mode == 0, iclass 33, count 2 2006.257.13:53:17.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.13:53:17.37#ibcon#[25=AT04-07\r\n] 2006.257.13:53:17.37#ibcon#*before write, iclass 33, count 2 2006.257.13:53:17.37#ibcon#enter sib2, iclass 33, count 2 2006.257.13:53:17.37#ibcon#flushed, iclass 33, count 2 2006.257.13:53:17.37#ibcon#about to write, iclass 33, count 2 2006.257.13:53:17.37#ibcon#wrote, iclass 33, count 2 2006.257.13:53:17.37#ibcon#about to read 3, iclass 33, count 2 2006.257.13:53:17.40#ibcon#read 3, iclass 33, count 2 2006.257.13:53:17.40#ibcon#about to read 4, iclass 33, count 2 2006.257.13:53:17.40#ibcon#read 4, iclass 33, count 2 2006.257.13:53:17.40#ibcon#about to read 5, iclass 33, count 2 2006.257.13:53:17.40#ibcon#read 5, iclass 33, count 2 2006.257.13:53:17.40#ibcon#about to read 6, iclass 33, count 2 2006.257.13:53:17.40#ibcon#read 6, iclass 33, count 2 2006.257.13:53:17.40#ibcon#end of sib2, iclass 33, count 2 2006.257.13:53:17.42#ibcon#*after write, iclass 33, count 2 2006.257.13:53:17.42#ibcon#*before return 0, iclass 33, count 2 2006.257.13:53:17.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:17.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:17.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.13:53:17.43#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:17.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:17.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:17.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:17.54#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:53:17.54#ibcon#first serial, iclass 33, count 0 2006.257.13:53:17.54#ibcon#enter sib2, iclass 33, count 0 2006.257.13:53:17.54#ibcon#flushed, iclass 33, count 0 2006.257.13:53:17.54#ibcon#about to write, iclass 33, count 0 2006.257.13:53:17.54#ibcon#wrote, iclass 33, count 0 2006.257.13:53:17.54#ibcon#about to read 3, iclass 33, count 0 2006.257.13:53:17.56#ibcon#read 3, iclass 33, count 0 2006.257.13:53:17.56#ibcon#about to read 4, iclass 33, count 0 2006.257.13:53:17.56#ibcon#read 4, iclass 33, count 0 2006.257.13:53:17.56#ibcon#about to read 5, iclass 33, count 0 2006.257.13:53:17.56#ibcon#read 5, iclass 33, count 0 2006.257.13:53:17.56#ibcon#about to read 6, iclass 33, count 0 2006.257.13:53:17.56#ibcon#read 6, iclass 33, count 0 2006.257.13:53:17.56#ibcon#end of sib2, iclass 33, count 0 2006.257.13:53:17.56#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:53:17.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:53:17.56#ibcon#[25=USB\r\n] 2006.257.13:53:17.56#ibcon#*before write, iclass 33, count 0 2006.257.13:53:17.56#ibcon#enter sib2, iclass 33, count 0 2006.257.13:53:17.56#ibcon#flushed, iclass 33, count 0 2006.257.13:53:17.56#ibcon#about to write, iclass 33, count 0 2006.257.13:53:17.56#ibcon#wrote, iclass 33, count 0 2006.257.13:53:17.56#ibcon#about to read 3, iclass 33, count 0 2006.257.13:53:17.59#ibcon#read 3, iclass 33, count 0 2006.257.13:53:17.59#ibcon#about to read 4, iclass 33, count 0 2006.257.13:53:17.59#ibcon#read 4, iclass 33, count 0 2006.257.13:53:17.59#ibcon#about to read 5, iclass 33, count 0 2006.257.13:53:17.59#ibcon#read 5, iclass 33, count 0 2006.257.13:53:17.59#ibcon#about to read 6, iclass 33, count 0 2006.257.13:53:17.59#ibcon#read 6, iclass 33, count 0 2006.257.13:53:17.59#ibcon#end of sib2, iclass 33, count 0 2006.257.13:53:17.59#ibcon#*after write, iclass 33, count 0 2006.257.13:53:17.59#ibcon#*before return 0, iclass 33, count 0 2006.257.13:53:17.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:17.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:17.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:53:17.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:53:17.59$vck44/valo=5,734.99 2006.257.13:53:17.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.13:53:17.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.13:53:17.59#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:17.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:17.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:17.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:17.59#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:53:17.59#ibcon#first serial, iclass 35, count 0 2006.257.13:53:17.59#ibcon#enter sib2, iclass 35, count 0 2006.257.13:53:17.59#ibcon#flushed, iclass 35, count 0 2006.257.13:53:17.59#ibcon#about to write, iclass 35, count 0 2006.257.13:53:17.60#ibcon#wrote, iclass 35, count 0 2006.257.13:53:17.60#ibcon#about to read 3, iclass 35, count 0 2006.257.13:53:17.61#ibcon#read 3, iclass 35, count 0 2006.257.13:53:17.61#ibcon#about to read 4, iclass 35, count 0 2006.257.13:53:17.61#ibcon#read 4, iclass 35, count 0 2006.257.13:53:17.61#ibcon#about to read 5, iclass 35, count 0 2006.257.13:53:17.61#ibcon#read 5, iclass 35, count 0 2006.257.13:53:17.61#ibcon#about to read 6, iclass 35, count 0 2006.257.13:53:17.61#ibcon#read 6, iclass 35, count 0 2006.257.13:53:17.61#ibcon#end of sib2, iclass 35, count 0 2006.257.13:53:17.61#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:53:17.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:53:17.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:53:17.61#ibcon#*before write, iclass 35, count 0 2006.257.13:53:17.61#ibcon#enter sib2, iclass 35, count 0 2006.257.13:53:17.61#ibcon#flushed, iclass 35, count 0 2006.257.13:53:17.61#ibcon#about to write, iclass 35, count 0 2006.257.13:53:17.61#ibcon#wrote, iclass 35, count 0 2006.257.13:53:17.61#ibcon#about to read 3, iclass 35, count 0 2006.257.13:53:17.65#ibcon#read 3, iclass 35, count 0 2006.257.13:53:17.65#ibcon#about to read 4, iclass 35, count 0 2006.257.13:53:17.65#ibcon#read 4, iclass 35, count 0 2006.257.13:53:17.65#ibcon#about to read 5, iclass 35, count 0 2006.257.13:53:17.65#ibcon#read 5, iclass 35, count 0 2006.257.13:53:17.65#ibcon#about to read 6, iclass 35, count 0 2006.257.13:53:17.65#ibcon#read 6, iclass 35, count 0 2006.257.13:53:17.65#ibcon#end of sib2, iclass 35, count 0 2006.257.13:53:17.65#ibcon#*after write, iclass 35, count 0 2006.257.13:53:17.65#ibcon#*before return 0, iclass 35, count 0 2006.257.13:53:17.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:17.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:17.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:53:17.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:53:17.65$vck44/va=5,4 2006.257.13:53:17.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.13:53:17.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.13:53:17.65#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:17.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:17.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:17.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:17.71#ibcon#enter wrdev, iclass 37, count 2 2006.257.13:53:17.71#ibcon#first serial, iclass 37, count 2 2006.257.13:53:17.71#ibcon#enter sib2, iclass 37, count 2 2006.257.13:53:17.71#ibcon#flushed, iclass 37, count 2 2006.257.13:53:17.71#ibcon#about to write, iclass 37, count 2 2006.257.13:53:17.71#ibcon#wrote, iclass 37, count 2 2006.257.13:53:17.71#ibcon#about to read 3, iclass 37, count 2 2006.257.13:53:17.73#ibcon#read 3, iclass 37, count 2 2006.257.13:53:17.73#ibcon#about to read 4, iclass 37, count 2 2006.257.13:53:17.73#ibcon#read 4, iclass 37, count 2 2006.257.13:53:17.73#ibcon#about to read 5, iclass 37, count 2 2006.257.13:53:17.73#ibcon#read 5, iclass 37, count 2 2006.257.13:53:17.73#ibcon#about to read 6, iclass 37, count 2 2006.257.13:53:17.73#ibcon#read 6, iclass 37, count 2 2006.257.13:53:17.73#ibcon#end of sib2, iclass 37, count 2 2006.257.13:53:17.73#ibcon#*mode == 0, iclass 37, count 2 2006.257.13:53:17.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.13:53:17.73#ibcon#[25=AT05-04\r\n] 2006.257.13:53:17.73#ibcon#*before write, iclass 37, count 2 2006.257.13:53:17.73#ibcon#enter sib2, iclass 37, count 2 2006.257.13:53:17.73#ibcon#flushed, iclass 37, count 2 2006.257.13:53:17.73#ibcon#about to write, iclass 37, count 2 2006.257.13:53:17.73#ibcon#wrote, iclass 37, count 2 2006.257.13:53:17.73#ibcon#about to read 3, iclass 37, count 2 2006.257.13:53:17.76#ibcon#read 3, iclass 37, count 2 2006.257.13:53:17.76#ibcon#about to read 4, iclass 37, count 2 2006.257.13:53:17.76#ibcon#read 4, iclass 37, count 2 2006.257.13:53:17.76#ibcon#about to read 5, iclass 37, count 2 2006.257.13:53:17.76#ibcon#read 5, iclass 37, count 2 2006.257.13:53:17.76#ibcon#about to read 6, iclass 37, count 2 2006.257.13:53:17.76#ibcon#read 6, iclass 37, count 2 2006.257.13:53:17.76#ibcon#end of sib2, iclass 37, count 2 2006.257.13:53:17.76#ibcon#*after write, iclass 37, count 2 2006.257.13:53:17.76#ibcon#*before return 0, iclass 37, count 2 2006.257.13:53:17.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:17.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:17.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.13:53:17.76#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:17.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:17.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:17.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:17.88#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:53:17.88#ibcon#first serial, iclass 37, count 0 2006.257.13:53:17.88#ibcon#enter sib2, iclass 37, count 0 2006.257.13:53:17.88#ibcon#flushed, iclass 37, count 0 2006.257.13:53:17.88#ibcon#about to write, iclass 37, count 0 2006.257.13:53:17.88#ibcon#wrote, iclass 37, count 0 2006.257.13:53:17.88#ibcon#about to read 3, iclass 37, count 0 2006.257.13:53:17.90#ibcon#read 3, iclass 37, count 0 2006.257.13:53:17.90#ibcon#about to read 4, iclass 37, count 0 2006.257.13:53:17.90#ibcon#read 4, iclass 37, count 0 2006.257.13:53:17.90#ibcon#about to read 5, iclass 37, count 0 2006.257.13:53:17.90#ibcon#read 5, iclass 37, count 0 2006.257.13:53:17.90#ibcon#about to read 6, iclass 37, count 0 2006.257.13:53:17.90#ibcon#read 6, iclass 37, count 0 2006.257.13:53:17.90#ibcon#end of sib2, iclass 37, count 0 2006.257.13:53:17.90#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:53:17.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:53:17.90#ibcon#[25=USB\r\n] 2006.257.13:53:17.90#ibcon#*before write, iclass 37, count 0 2006.257.13:53:17.90#ibcon#enter sib2, iclass 37, count 0 2006.257.13:53:17.90#ibcon#flushed, iclass 37, count 0 2006.257.13:53:17.90#ibcon#about to write, iclass 37, count 0 2006.257.13:53:17.90#ibcon#wrote, iclass 37, count 0 2006.257.13:53:17.90#ibcon#about to read 3, iclass 37, count 0 2006.257.13:53:17.93#ibcon#read 3, iclass 37, count 0 2006.257.13:53:17.93#ibcon#about to read 4, iclass 37, count 0 2006.257.13:53:17.93#ibcon#read 4, iclass 37, count 0 2006.257.13:53:17.93#ibcon#about to read 5, iclass 37, count 0 2006.257.13:53:17.93#ibcon#read 5, iclass 37, count 0 2006.257.13:53:17.93#ibcon#about to read 6, iclass 37, count 0 2006.257.13:53:17.93#ibcon#read 6, iclass 37, count 0 2006.257.13:53:17.93#ibcon#end of sib2, iclass 37, count 0 2006.257.13:53:17.93#ibcon#*after write, iclass 37, count 0 2006.257.13:53:17.93#ibcon#*before return 0, iclass 37, count 0 2006.257.13:53:17.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:17.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:17.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:53:17.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:53:17.93$vck44/valo=6,814.99 2006.257.13:53:17.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:53:17.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:53:17.93#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:17.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:17.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:17.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:17.93#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:53:17.93#ibcon#first serial, iclass 39, count 0 2006.257.13:53:17.93#ibcon#enter sib2, iclass 39, count 0 2006.257.13:53:17.93#ibcon#flushed, iclass 39, count 0 2006.257.13:53:17.93#ibcon#about to write, iclass 39, count 0 2006.257.13:53:17.93#ibcon#wrote, iclass 39, count 0 2006.257.13:53:17.93#ibcon#about to read 3, iclass 39, count 0 2006.257.13:53:17.95#ibcon#read 3, iclass 39, count 0 2006.257.13:53:17.95#ibcon#about to read 4, iclass 39, count 0 2006.257.13:53:17.95#ibcon#read 4, iclass 39, count 0 2006.257.13:53:17.95#ibcon#about to read 5, iclass 39, count 0 2006.257.13:53:17.95#ibcon#read 5, iclass 39, count 0 2006.257.13:53:17.95#ibcon#about to read 6, iclass 39, count 0 2006.257.13:53:17.95#ibcon#read 6, iclass 39, count 0 2006.257.13:53:17.95#ibcon#end of sib2, iclass 39, count 0 2006.257.13:53:17.95#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:53:17.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:53:17.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:53:17.95#ibcon#*before write, iclass 39, count 0 2006.257.13:53:17.95#ibcon#enter sib2, iclass 39, count 0 2006.257.13:53:17.95#ibcon#flushed, iclass 39, count 0 2006.257.13:53:17.95#ibcon#about to write, iclass 39, count 0 2006.257.13:53:17.95#ibcon#wrote, iclass 39, count 0 2006.257.13:53:17.95#ibcon#about to read 3, iclass 39, count 0 2006.257.13:53:17.99#ibcon#read 3, iclass 39, count 0 2006.257.13:53:17.99#ibcon#about to read 4, iclass 39, count 0 2006.257.13:53:17.99#ibcon#read 4, iclass 39, count 0 2006.257.13:53:17.99#ibcon#about to read 5, iclass 39, count 0 2006.257.13:53:17.99#ibcon#read 5, iclass 39, count 0 2006.257.13:53:17.99#ibcon#about to read 6, iclass 39, count 0 2006.257.13:53:17.99#ibcon#read 6, iclass 39, count 0 2006.257.13:53:17.99#ibcon#end of sib2, iclass 39, count 0 2006.257.13:53:17.99#ibcon#*after write, iclass 39, count 0 2006.257.13:53:17.99#ibcon#*before return 0, iclass 39, count 0 2006.257.13:53:17.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:17.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:17.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:53:17.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:53:17.99$vck44/va=6,4 2006.257.13:53:17.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.13:53:17.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.13:53:17.99#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:17.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:18.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:18.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:18.05#ibcon#enter wrdev, iclass 3, count 2 2006.257.13:53:18.05#ibcon#first serial, iclass 3, count 2 2006.257.13:53:18.05#ibcon#enter sib2, iclass 3, count 2 2006.257.13:53:18.05#ibcon#flushed, iclass 3, count 2 2006.257.13:53:18.05#ibcon#about to write, iclass 3, count 2 2006.257.13:53:18.05#ibcon#wrote, iclass 3, count 2 2006.257.13:53:18.05#ibcon#about to read 3, iclass 3, count 2 2006.257.13:53:18.07#ibcon#read 3, iclass 3, count 2 2006.257.13:53:18.07#ibcon#about to read 4, iclass 3, count 2 2006.257.13:53:18.07#ibcon#read 4, iclass 3, count 2 2006.257.13:53:18.07#ibcon#about to read 5, iclass 3, count 2 2006.257.13:53:18.07#ibcon#read 5, iclass 3, count 2 2006.257.13:53:18.07#ibcon#about to read 6, iclass 3, count 2 2006.257.13:53:18.07#ibcon#read 6, iclass 3, count 2 2006.257.13:53:18.07#ibcon#end of sib2, iclass 3, count 2 2006.257.13:53:18.07#ibcon#*mode == 0, iclass 3, count 2 2006.257.13:53:18.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.13:53:18.07#ibcon#[25=AT06-04\r\n] 2006.257.13:53:18.07#ibcon#*before write, iclass 3, count 2 2006.257.13:53:18.07#ibcon#enter sib2, iclass 3, count 2 2006.257.13:53:18.07#ibcon#flushed, iclass 3, count 2 2006.257.13:53:18.07#ibcon#about to write, iclass 3, count 2 2006.257.13:53:18.07#ibcon#wrote, iclass 3, count 2 2006.257.13:53:18.07#ibcon#about to read 3, iclass 3, count 2 2006.257.13:53:18.10#ibcon#read 3, iclass 3, count 2 2006.257.13:53:18.10#ibcon#about to read 4, iclass 3, count 2 2006.257.13:53:18.10#ibcon#read 4, iclass 3, count 2 2006.257.13:53:18.10#ibcon#about to read 5, iclass 3, count 2 2006.257.13:53:18.10#ibcon#read 5, iclass 3, count 2 2006.257.13:53:18.10#ibcon#about to read 6, iclass 3, count 2 2006.257.13:53:18.10#ibcon#read 6, iclass 3, count 2 2006.257.13:53:18.10#ibcon#end of sib2, iclass 3, count 2 2006.257.13:53:18.10#ibcon#*after write, iclass 3, count 2 2006.257.13:53:18.10#ibcon#*before return 0, iclass 3, count 2 2006.257.13:53:18.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:18.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:18.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.13:53:18.10#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:18.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:18.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:18.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:18.22#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:53:18.22#ibcon#first serial, iclass 3, count 0 2006.257.13:53:18.22#ibcon#enter sib2, iclass 3, count 0 2006.257.13:53:18.22#ibcon#flushed, iclass 3, count 0 2006.257.13:53:18.22#ibcon#about to write, iclass 3, count 0 2006.257.13:53:18.22#ibcon#wrote, iclass 3, count 0 2006.257.13:53:18.22#ibcon#about to read 3, iclass 3, count 0 2006.257.13:53:18.24#ibcon#read 3, iclass 3, count 0 2006.257.13:53:18.24#ibcon#about to read 4, iclass 3, count 0 2006.257.13:53:18.24#ibcon#read 4, iclass 3, count 0 2006.257.13:53:18.24#ibcon#about to read 5, iclass 3, count 0 2006.257.13:53:18.24#ibcon#read 5, iclass 3, count 0 2006.257.13:53:18.24#ibcon#about to read 6, iclass 3, count 0 2006.257.13:53:18.24#ibcon#read 6, iclass 3, count 0 2006.257.13:53:18.24#ibcon#end of sib2, iclass 3, count 0 2006.257.13:53:18.24#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:53:18.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:53:18.24#ibcon#[25=USB\r\n] 2006.257.13:53:18.24#ibcon#*before write, iclass 3, count 0 2006.257.13:53:18.24#ibcon#enter sib2, iclass 3, count 0 2006.257.13:53:18.24#ibcon#flushed, iclass 3, count 0 2006.257.13:53:18.24#ibcon#about to write, iclass 3, count 0 2006.257.13:53:18.24#ibcon#wrote, iclass 3, count 0 2006.257.13:53:18.24#ibcon#about to read 3, iclass 3, count 0 2006.257.13:53:18.27#ibcon#read 3, iclass 3, count 0 2006.257.13:53:18.27#ibcon#about to read 4, iclass 3, count 0 2006.257.13:53:18.27#ibcon#read 4, iclass 3, count 0 2006.257.13:53:18.27#ibcon#about to read 5, iclass 3, count 0 2006.257.13:53:18.27#ibcon#read 5, iclass 3, count 0 2006.257.13:53:18.27#ibcon#about to read 6, iclass 3, count 0 2006.257.13:53:18.27#ibcon#read 6, iclass 3, count 0 2006.257.13:53:18.27#ibcon#end of sib2, iclass 3, count 0 2006.257.13:53:18.27#ibcon#*after write, iclass 3, count 0 2006.257.13:53:18.27#ibcon#*before return 0, iclass 3, count 0 2006.257.13:53:18.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:18.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:18.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:53:18.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:53:18.27$vck44/valo=7,864.99 2006.257.13:53:18.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.13:53:18.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.13:53:18.27#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:18.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:18.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:18.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:18.27#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:53:18.27#ibcon#first serial, iclass 5, count 0 2006.257.13:53:18.27#ibcon#enter sib2, iclass 5, count 0 2006.257.13:53:18.27#ibcon#flushed, iclass 5, count 0 2006.257.13:53:18.27#ibcon#about to write, iclass 5, count 0 2006.257.13:53:18.28#ibcon#wrote, iclass 5, count 0 2006.257.13:53:18.28#ibcon#about to read 3, iclass 5, count 0 2006.257.13:53:18.29#ibcon#read 3, iclass 5, count 0 2006.257.13:53:18.29#ibcon#about to read 4, iclass 5, count 0 2006.257.13:53:18.29#ibcon#read 4, iclass 5, count 0 2006.257.13:53:18.29#ibcon#about to read 5, iclass 5, count 0 2006.257.13:53:18.29#ibcon#read 5, iclass 5, count 0 2006.257.13:53:18.29#ibcon#about to read 6, iclass 5, count 0 2006.257.13:53:18.29#ibcon#read 6, iclass 5, count 0 2006.257.13:53:18.29#ibcon#end of sib2, iclass 5, count 0 2006.257.13:53:18.29#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:53:18.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:53:18.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:53:18.29#ibcon#*before write, iclass 5, count 0 2006.257.13:53:18.29#ibcon#enter sib2, iclass 5, count 0 2006.257.13:53:18.29#ibcon#flushed, iclass 5, count 0 2006.257.13:53:18.29#ibcon#about to write, iclass 5, count 0 2006.257.13:53:18.29#ibcon#wrote, iclass 5, count 0 2006.257.13:53:18.29#ibcon#about to read 3, iclass 5, count 0 2006.257.13:53:18.33#ibcon#read 3, iclass 5, count 0 2006.257.13:53:18.33#ibcon#about to read 4, iclass 5, count 0 2006.257.13:53:18.33#ibcon#read 4, iclass 5, count 0 2006.257.13:53:18.33#ibcon#about to read 5, iclass 5, count 0 2006.257.13:53:18.33#ibcon#read 5, iclass 5, count 0 2006.257.13:53:18.33#ibcon#about to read 6, iclass 5, count 0 2006.257.13:53:18.33#ibcon#read 6, iclass 5, count 0 2006.257.13:53:18.33#ibcon#end of sib2, iclass 5, count 0 2006.257.13:53:18.33#ibcon#*after write, iclass 5, count 0 2006.257.13:53:18.33#ibcon#*before return 0, iclass 5, count 0 2006.257.13:53:18.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:18.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:18.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:53:18.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:53:18.33$vck44/va=7,4 2006.257.13:53:18.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.13:53:18.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.13:53:18.33#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:18.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:18.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:18.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:18.39#ibcon#enter wrdev, iclass 7, count 2 2006.257.13:53:18.39#ibcon#first serial, iclass 7, count 2 2006.257.13:53:18.39#ibcon#enter sib2, iclass 7, count 2 2006.257.13:53:18.39#ibcon#flushed, iclass 7, count 2 2006.257.13:53:18.39#ibcon#about to write, iclass 7, count 2 2006.257.13:53:18.39#ibcon#wrote, iclass 7, count 2 2006.257.13:53:18.39#ibcon#about to read 3, iclass 7, count 2 2006.257.13:53:18.41#ibcon#read 3, iclass 7, count 2 2006.257.13:53:18.41#ibcon#about to read 4, iclass 7, count 2 2006.257.13:53:18.41#ibcon#read 4, iclass 7, count 2 2006.257.13:53:18.41#ibcon#about to read 5, iclass 7, count 2 2006.257.13:53:18.41#ibcon#read 5, iclass 7, count 2 2006.257.13:53:18.41#ibcon#about to read 6, iclass 7, count 2 2006.257.13:53:18.41#ibcon#read 6, iclass 7, count 2 2006.257.13:53:18.41#ibcon#end of sib2, iclass 7, count 2 2006.257.13:53:18.41#ibcon#*mode == 0, iclass 7, count 2 2006.257.13:53:18.41#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.13:53:18.41#ibcon#[25=AT07-04\r\n] 2006.257.13:53:18.41#ibcon#*before write, iclass 7, count 2 2006.257.13:53:18.41#ibcon#enter sib2, iclass 7, count 2 2006.257.13:53:18.41#ibcon#flushed, iclass 7, count 2 2006.257.13:53:18.41#ibcon#about to write, iclass 7, count 2 2006.257.13:53:18.41#ibcon#wrote, iclass 7, count 2 2006.257.13:53:18.41#ibcon#about to read 3, iclass 7, count 2 2006.257.13:53:18.44#ibcon#read 3, iclass 7, count 2 2006.257.13:53:18.44#ibcon#about to read 4, iclass 7, count 2 2006.257.13:53:18.44#ibcon#read 4, iclass 7, count 2 2006.257.13:53:18.44#ibcon#about to read 5, iclass 7, count 2 2006.257.13:53:18.44#ibcon#read 5, iclass 7, count 2 2006.257.13:53:18.44#ibcon#about to read 6, iclass 7, count 2 2006.257.13:53:18.44#ibcon#read 6, iclass 7, count 2 2006.257.13:53:18.44#ibcon#end of sib2, iclass 7, count 2 2006.257.13:53:18.44#ibcon#*after write, iclass 7, count 2 2006.257.13:53:18.44#ibcon#*before return 0, iclass 7, count 2 2006.257.13:53:18.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:18.48#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:18.48#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.13:53:18.48#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:18.48#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:18.59#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:18.59#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:18.59#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:53:18.59#ibcon#first serial, iclass 7, count 0 2006.257.13:53:18.59#ibcon#enter sib2, iclass 7, count 0 2006.257.13:53:18.59#ibcon#flushed, iclass 7, count 0 2006.257.13:53:18.59#ibcon#about to write, iclass 7, count 0 2006.257.13:53:18.59#ibcon#wrote, iclass 7, count 0 2006.257.13:53:18.59#ibcon#about to read 3, iclass 7, count 0 2006.257.13:53:18.61#ibcon#read 3, iclass 7, count 0 2006.257.13:53:18.61#ibcon#about to read 4, iclass 7, count 0 2006.257.13:53:18.61#ibcon#read 4, iclass 7, count 0 2006.257.13:53:18.61#ibcon#about to read 5, iclass 7, count 0 2006.257.13:53:18.61#ibcon#read 5, iclass 7, count 0 2006.257.13:53:18.61#ibcon#about to read 6, iclass 7, count 0 2006.257.13:53:18.61#ibcon#read 6, iclass 7, count 0 2006.257.13:53:18.61#ibcon#end of sib2, iclass 7, count 0 2006.257.13:53:18.61#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:53:18.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:53:18.61#ibcon#[25=USB\r\n] 2006.257.13:53:18.61#ibcon#*before write, iclass 7, count 0 2006.257.13:53:18.61#ibcon#enter sib2, iclass 7, count 0 2006.257.13:53:18.61#ibcon#flushed, iclass 7, count 0 2006.257.13:53:18.61#ibcon#about to write, iclass 7, count 0 2006.257.13:53:18.61#ibcon#wrote, iclass 7, count 0 2006.257.13:53:18.61#ibcon#about to read 3, iclass 7, count 0 2006.257.13:53:18.64#ibcon#read 3, iclass 7, count 0 2006.257.13:53:18.64#ibcon#about to read 4, iclass 7, count 0 2006.257.13:53:18.64#ibcon#read 4, iclass 7, count 0 2006.257.13:53:18.64#ibcon#about to read 5, iclass 7, count 0 2006.257.13:53:18.64#ibcon#read 5, iclass 7, count 0 2006.257.13:53:18.64#ibcon#about to read 6, iclass 7, count 0 2006.257.13:53:18.64#ibcon#read 6, iclass 7, count 0 2006.257.13:53:18.64#ibcon#end of sib2, iclass 7, count 0 2006.257.13:53:18.64#ibcon#*after write, iclass 7, count 0 2006.257.13:53:18.64#ibcon#*before return 0, iclass 7, count 0 2006.257.13:53:18.64#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:18.64#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:18.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:53:18.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:53:18.64$vck44/valo=8,884.99 2006.257.13:53:18.64#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.13:53:18.64#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.13:53:18.64#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:18.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:18.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:18.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:18.64#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:53:18.64#ibcon#first serial, iclass 11, count 0 2006.257.13:53:18.64#ibcon#enter sib2, iclass 11, count 0 2006.257.13:53:18.64#ibcon#flushed, iclass 11, count 0 2006.257.13:53:18.64#ibcon#about to write, iclass 11, count 0 2006.257.13:53:18.65#ibcon#wrote, iclass 11, count 0 2006.257.13:53:18.65#ibcon#about to read 3, iclass 11, count 0 2006.257.13:53:18.66#ibcon#read 3, iclass 11, count 0 2006.257.13:53:18.66#ibcon#about to read 4, iclass 11, count 0 2006.257.13:53:18.66#ibcon#read 4, iclass 11, count 0 2006.257.13:53:18.66#ibcon#about to read 5, iclass 11, count 0 2006.257.13:53:18.66#ibcon#read 5, iclass 11, count 0 2006.257.13:53:18.66#ibcon#about to read 6, iclass 11, count 0 2006.257.13:53:18.66#ibcon#read 6, iclass 11, count 0 2006.257.13:53:18.66#ibcon#end of sib2, iclass 11, count 0 2006.257.13:53:18.66#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:53:18.66#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:53:18.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:53:18.66#ibcon#*before write, iclass 11, count 0 2006.257.13:53:18.66#ibcon#enter sib2, iclass 11, count 0 2006.257.13:53:18.66#ibcon#flushed, iclass 11, count 0 2006.257.13:53:18.66#ibcon#about to write, iclass 11, count 0 2006.257.13:53:18.66#ibcon#wrote, iclass 11, count 0 2006.257.13:53:18.66#ibcon#about to read 3, iclass 11, count 0 2006.257.13:53:18.70#ibcon#read 3, iclass 11, count 0 2006.257.13:53:18.70#ibcon#about to read 4, iclass 11, count 0 2006.257.13:53:18.70#ibcon#read 4, iclass 11, count 0 2006.257.13:53:18.70#ibcon#about to read 5, iclass 11, count 0 2006.257.13:53:18.70#ibcon#read 5, iclass 11, count 0 2006.257.13:53:18.70#ibcon#about to read 6, iclass 11, count 0 2006.257.13:53:18.70#ibcon#read 6, iclass 11, count 0 2006.257.13:53:18.70#ibcon#end of sib2, iclass 11, count 0 2006.257.13:53:18.70#ibcon#*after write, iclass 11, count 0 2006.257.13:53:18.70#ibcon#*before return 0, iclass 11, count 0 2006.257.13:53:18.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:18.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:18.70#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:53:18.70#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:53:18.70$vck44/va=8,4 2006.257.13:53:18.70#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.13:53:18.70#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.13:53:18.70#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:18.70#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:53:18.76#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:53:18.76#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:53:18.76#ibcon#enter wrdev, iclass 13, count 2 2006.257.13:53:18.76#ibcon#first serial, iclass 13, count 2 2006.257.13:53:18.76#ibcon#enter sib2, iclass 13, count 2 2006.257.13:53:18.76#ibcon#flushed, iclass 13, count 2 2006.257.13:53:18.76#ibcon#about to write, iclass 13, count 2 2006.257.13:53:18.76#ibcon#wrote, iclass 13, count 2 2006.257.13:53:18.76#ibcon#about to read 3, iclass 13, count 2 2006.257.13:53:18.78#ibcon#read 3, iclass 13, count 2 2006.257.13:53:18.78#ibcon#about to read 4, iclass 13, count 2 2006.257.13:53:18.78#ibcon#read 4, iclass 13, count 2 2006.257.13:53:18.78#ibcon#about to read 5, iclass 13, count 2 2006.257.13:53:18.78#ibcon#read 5, iclass 13, count 2 2006.257.13:53:18.78#ibcon#about to read 6, iclass 13, count 2 2006.257.13:53:18.78#ibcon#read 6, iclass 13, count 2 2006.257.13:53:18.78#ibcon#end of sib2, iclass 13, count 2 2006.257.13:53:18.78#ibcon#*mode == 0, iclass 13, count 2 2006.257.13:53:18.78#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.13:53:18.78#ibcon#[25=AT08-04\r\n] 2006.257.13:53:18.78#ibcon#*before write, iclass 13, count 2 2006.257.13:53:18.78#ibcon#enter sib2, iclass 13, count 2 2006.257.13:53:18.78#ibcon#flushed, iclass 13, count 2 2006.257.13:53:18.78#ibcon#about to write, iclass 13, count 2 2006.257.13:53:18.78#ibcon#wrote, iclass 13, count 2 2006.257.13:53:18.78#ibcon#about to read 3, iclass 13, count 2 2006.257.13:53:18.81#ibcon#read 3, iclass 13, count 2 2006.257.13:53:18.81#ibcon#about to read 4, iclass 13, count 2 2006.257.13:53:18.81#ibcon#read 4, iclass 13, count 2 2006.257.13:53:18.81#ibcon#about to read 5, iclass 13, count 2 2006.257.13:53:18.81#ibcon#read 5, iclass 13, count 2 2006.257.13:53:18.81#ibcon#about to read 6, iclass 13, count 2 2006.257.13:53:18.81#ibcon#read 6, iclass 13, count 2 2006.257.13:53:18.81#ibcon#end of sib2, iclass 13, count 2 2006.257.13:53:18.81#ibcon#*after write, iclass 13, count 2 2006.257.13:53:18.81#ibcon#*before return 0, iclass 13, count 2 2006.257.13:53:18.81#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:53:18.81#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.13:53:18.81#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.13:53:18.81#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:18.81#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:53:18.93#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:53:18.93#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:53:18.93#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:53:18.93#ibcon#first serial, iclass 13, count 0 2006.257.13:53:18.93#ibcon#enter sib2, iclass 13, count 0 2006.257.13:53:18.93#ibcon#flushed, iclass 13, count 0 2006.257.13:53:18.93#ibcon#about to write, iclass 13, count 0 2006.257.13:53:18.93#ibcon#wrote, iclass 13, count 0 2006.257.13:53:18.93#ibcon#about to read 3, iclass 13, count 0 2006.257.13:53:18.95#ibcon#read 3, iclass 13, count 0 2006.257.13:53:18.95#ibcon#about to read 4, iclass 13, count 0 2006.257.13:53:18.95#ibcon#read 4, iclass 13, count 0 2006.257.13:53:18.95#ibcon#about to read 5, iclass 13, count 0 2006.257.13:53:18.95#ibcon#read 5, iclass 13, count 0 2006.257.13:53:18.95#ibcon#about to read 6, iclass 13, count 0 2006.257.13:53:18.95#ibcon#read 6, iclass 13, count 0 2006.257.13:53:18.95#ibcon#end of sib2, iclass 13, count 0 2006.257.13:53:18.95#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:53:18.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:53:18.95#ibcon#[25=USB\r\n] 2006.257.13:53:18.95#ibcon#*before write, iclass 13, count 0 2006.257.13:53:18.95#ibcon#enter sib2, iclass 13, count 0 2006.257.13:53:18.95#ibcon#flushed, iclass 13, count 0 2006.257.13:53:18.95#ibcon#about to write, iclass 13, count 0 2006.257.13:53:18.95#ibcon#wrote, iclass 13, count 0 2006.257.13:53:18.95#ibcon#about to read 3, iclass 13, count 0 2006.257.13:53:18.98#ibcon#read 3, iclass 13, count 0 2006.257.13:53:18.98#ibcon#about to read 4, iclass 13, count 0 2006.257.13:53:18.98#ibcon#read 4, iclass 13, count 0 2006.257.13:53:18.98#ibcon#about to read 5, iclass 13, count 0 2006.257.13:53:18.98#ibcon#read 5, iclass 13, count 0 2006.257.13:53:18.98#ibcon#about to read 6, iclass 13, count 0 2006.257.13:53:18.98#ibcon#read 6, iclass 13, count 0 2006.257.13:53:18.98#ibcon#end of sib2, iclass 13, count 0 2006.257.13:53:18.98#ibcon#*after write, iclass 13, count 0 2006.257.13:53:18.98#ibcon#*before return 0, iclass 13, count 0 2006.257.13:53:18.98#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:53:18.98#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.13:53:18.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:53:18.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:53:18.98$vck44/vblo=1,629.99 2006.257.13:53:18.98#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.13:53:18.98#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.13:53:18.98#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:18.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:18.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:18.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:18.98#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:53:18.98#ibcon#first serial, iclass 15, count 0 2006.257.13:53:18.98#ibcon#enter sib2, iclass 15, count 0 2006.257.13:53:18.98#ibcon#flushed, iclass 15, count 0 2006.257.13:53:18.98#ibcon#about to write, iclass 15, count 0 2006.257.13:53:18.98#ibcon#wrote, iclass 15, count 0 2006.257.13:53:18.98#ibcon#about to read 3, iclass 15, count 0 2006.257.13:53:19.00#ibcon#read 3, iclass 15, count 0 2006.257.13:53:19.00#ibcon#about to read 4, iclass 15, count 0 2006.257.13:53:19.00#ibcon#read 4, iclass 15, count 0 2006.257.13:53:19.00#ibcon#about to read 5, iclass 15, count 0 2006.257.13:53:19.00#ibcon#read 5, iclass 15, count 0 2006.257.13:53:19.00#ibcon#about to read 6, iclass 15, count 0 2006.257.13:53:19.00#ibcon#read 6, iclass 15, count 0 2006.257.13:53:19.00#ibcon#end of sib2, iclass 15, count 0 2006.257.13:53:19.00#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:53:19.00#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:53:19.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:53:19.00#ibcon#*before write, iclass 15, count 0 2006.257.13:53:19.00#ibcon#enter sib2, iclass 15, count 0 2006.257.13:53:19.00#ibcon#flushed, iclass 15, count 0 2006.257.13:53:19.00#ibcon#about to write, iclass 15, count 0 2006.257.13:53:19.00#ibcon#wrote, iclass 15, count 0 2006.257.13:53:19.00#ibcon#about to read 3, iclass 15, count 0 2006.257.13:53:19.04#ibcon#read 3, iclass 15, count 0 2006.257.13:53:19.04#ibcon#about to read 4, iclass 15, count 0 2006.257.13:53:19.04#ibcon#read 4, iclass 15, count 0 2006.257.13:53:19.04#ibcon#about to read 5, iclass 15, count 0 2006.257.13:53:19.04#ibcon#read 5, iclass 15, count 0 2006.257.13:53:19.04#ibcon#about to read 6, iclass 15, count 0 2006.257.13:53:19.04#ibcon#read 6, iclass 15, count 0 2006.257.13:53:19.04#ibcon#end of sib2, iclass 15, count 0 2006.257.13:53:19.04#ibcon#*after write, iclass 15, count 0 2006.257.13:53:19.04#ibcon#*before return 0, iclass 15, count 0 2006.257.13:53:19.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:19.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.13:53:19.04#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:53:19.04#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:53:19.04$vck44/vb=1,4 2006.257.13:53:19.04#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.13:53:19.04#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.13:53:19.04#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:19.04#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:19.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:19.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:19.04#ibcon#enter wrdev, iclass 17, count 2 2006.257.13:53:19.04#ibcon#first serial, iclass 17, count 2 2006.257.13:53:19.04#ibcon#enter sib2, iclass 17, count 2 2006.257.13:53:19.04#ibcon#flushed, iclass 17, count 2 2006.257.13:53:19.04#ibcon#about to write, iclass 17, count 2 2006.257.13:53:19.04#ibcon#wrote, iclass 17, count 2 2006.257.13:53:19.04#ibcon#about to read 3, iclass 17, count 2 2006.257.13:53:19.06#ibcon#read 3, iclass 17, count 2 2006.257.13:53:19.06#ibcon#about to read 4, iclass 17, count 2 2006.257.13:53:19.06#ibcon#read 4, iclass 17, count 2 2006.257.13:53:19.06#ibcon#about to read 5, iclass 17, count 2 2006.257.13:53:19.06#ibcon#read 5, iclass 17, count 2 2006.257.13:53:19.06#ibcon#about to read 6, iclass 17, count 2 2006.257.13:53:19.06#ibcon#read 6, iclass 17, count 2 2006.257.13:53:19.06#ibcon#end of sib2, iclass 17, count 2 2006.257.13:53:19.06#ibcon#*mode == 0, iclass 17, count 2 2006.257.13:53:19.06#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.13:53:19.06#ibcon#[27=AT01-04\r\n] 2006.257.13:53:19.06#ibcon#*before write, iclass 17, count 2 2006.257.13:53:19.06#ibcon#enter sib2, iclass 17, count 2 2006.257.13:53:19.06#ibcon#flushed, iclass 17, count 2 2006.257.13:53:19.06#ibcon#about to write, iclass 17, count 2 2006.257.13:53:19.06#ibcon#wrote, iclass 17, count 2 2006.257.13:53:19.06#ibcon#about to read 3, iclass 17, count 2 2006.257.13:53:19.09#ibcon#read 3, iclass 17, count 2 2006.257.13:53:19.09#ibcon#about to read 4, iclass 17, count 2 2006.257.13:53:19.09#ibcon#read 4, iclass 17, count 2 2006.257.13:53:19.09#ibcon#about to read 5, iclass 17, count 2 2006.257.13:53:19.09#ibcon#read 5, iclass 17, count 2 2006.257.13:53:19.09#ibcon#about to read 6, iclass 17, count 2 2006.257.13:53:19.09#ibcon#read 6, iclass 17, count 2 2006.257.13:53:19.09#ibcon#end of sib2, iclass 17, count 2 2006.257.13:53:19.09#ibcon#*after write, iclass 17, count 2 2006.257.13:53:19.09#ibcon#*before return 0, iclass 17, count 2 2006.257.13:53:19.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:19.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.13:53:19.09#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.13:53:19.09#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:19.09#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:19.21#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:19.21#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:19.21#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:53:19.21#ibcon#first serial, iclass 17, count 0 2006.257.13:53:19.21#ibcon#enter sib2, iclass 17, count 0 2006.257.13:53:19.21#ibcon#flushed, iclass 17, count 0 2006.257.13:53:19.21#ibcon#about to write, iclass 17, count 0 2006.257.13:53:19.21#ibcon#wrote, iclass 17, count 0 2006.257.13:53:19.21#ibcon#about to read 3, iclass 17, count 0 2006.257.13:53:19.23#ibcon#read 3, iclass 17, count 0 2006.257.13:53:19.23#ibcon#about to read 4, iclass 17, count 0 2006.257.13:53:19.23#ibcon#read 4, iclass 17, count 0 2006.257.13:53:19.23#ibcon#about to read 5, iclass 17, count 0 2006.257.13:53:19.23#ibcon#read 5, iclass 17, count 0 2006.257.13:53:19.23#ibcon#about to read 6, iclass 17, count 0 2006.257.13:53:19.23#ibcon#read 6, iclass 17, count 0 2006.257.13:53:19.23#ibcon#end of sib2, iclass 17, count 0 2006.257.13:53:19.23#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:53:19.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:53:19.23#ibcon#[27=USB\r\n] 2006.257.13:53:19.23#ibcon#*before write, iclass 17, count 0 2006.257.13:53:19.23#ibcon#enter sib2, iclass 17, count 0 2006.257.13:53:19.23#ibcon#flushed, iclass 17, count 0 2006.257.13:53:19.23#ibcon#about to write, iclass 17, count 0 2006.257.13:53:19.23#ibcon#wrote, iclass 17, count 0 2006.257.13:53:19.23#ibcon#about to read 3, iclass 17, count 0 2006.257.13:53:19.26#ibcon#read 3, iclass 17, count 0 2006.257.13:53:19.26#ibcon#about to read 4, iclass 17, count 0 2006.257.13:53:19.26#ibcon#read 4, iclass 17, count 0 2006.257.13:53:19.26#ibcon#about to read 5, iclass 17, count 0 2006.257.13:53:19.26#ibcon#read 5, iclass 17, count 0 2006.257.13:53:19.26#ibcon#about to read 6, iclass 17, count 0 2006.257.13:53:19.26#ibcon#read 6, iclass 17, count 0 2006.257.13:53:19.26#ibcon#end of sib2, iclass 17, count 0 2006.257.13:53:19.26#ibcon#*after write, iclass 17, count 0 2006.257.13:53:19.26#ibcon#*before return 0, iclass 17, count 0 2006.257.13:53:19.26#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:19.26#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.13:53:19.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:53:19.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:53:19.26$vck44/vblo=2,634.99 2006.257.13:53:19.26#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.13:53:19.26#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.13:53:19.26#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:19.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:19.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:19.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:19.26#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:53:19.26#ibcon#first serial, iclass 19, count 0 2006.257.13:53:19.26#ibcon#enter sib2, iclass 19, count 0 2006.257.13:53:19.26#ibcon#flushed, iclass 19, count 0 2006.257.13:53:19.26#ibcon#about to write, iclass 19, count 0 2006.257.13:53:19.26#ibcon#wrote, iclass 19, count 0 2006.257.13:53:19.27#ibcon#about to read 3, iclass 19, count 0 2006.257.13:53:19.28#ibcon#read 3, iclass 19, count 0 2006.257.13:53:19.28#ibcon#about to read 4, iclass 19, count 0 2006.257.13:53:19.28#ibcon#read 4, iclass 19, count 0 2006.257.13:53:19.28#ibcon#about to read 5, iclass 19, count 0 2006.257.13:53:19.28#ibcon#read 5, iclass 19, count 0 2006.257.13:53:19.28#ibcon#about to read 6, iclass 19, count 0 2006.257.13:53:19.28#ibcon#read 6, iclass 19, count 0 2006.257.13:53:19.28#ibcon#end of sib2, iclass 19, count 0 2006.257.13:53:19.28#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:53:19.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:53:19.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:53:19.28#ibcon#*before write, iclass 19, count 0 2006.257.13:53:19.28#ibcon#enter sib2, iclass 19, count 0 2006.257.13:53:19.28#ibcon#flushed, iclass 19, count 0 2006.257.13:53:19.28#ibcon#about to write, iclass 19, count 0 2006.257.13:53:19.28#ibcon#wrote, iclass 19, count 0 2006.257.13:53:19.28#ibcon#about to read 3, iclass 19, count 0 2006.257.13:53:19.32#ibcon#read 3, iclass 19, count 0 2006.257.13:53:19.32#ibcon#about to read 4, iclass 19, count 0 2006.257.13:53:19.32#ibcon#read 4, iclass 19, count 0 2006.257.13:53:19.32#ibcon#about to read 5, iclass 19, count 0 2006.257.13:53:19.32#ibcon#read 5, iclass 19, count 0 2006.257.13:53:19.32#ibcon#about to read 6, iclass 19, count 0 2006.257.13:53:19.32#ibcon#read 6, iclass 19, count 0 2006.257.13:53:19.32#ibcon#end of sib2, iclass 19, count 0 2006.257.13:53:19.32#ibcon#*after write, iclass 19, count 0 2006.257.13:53:19.32#ibcon#*before return 0, iclass 19, count 0 2006.257.13:53:19.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:19.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.13:53:19.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:53:19.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:53:19.32$vck44/vb=2,5 2006.257.13:53:19.32#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.13:53:19.32#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.13:53:19.32#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:19.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:19.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:19.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:19.38#ibcon#enter wrdev, iclass 21, count 2 2006.257.13:53:19.38#ibcon#first serial, iclass 21, count 2 2006.257.13:53:19.38#ibcon#enter sib2, iclass 21, count 2 2006.257.13:53:19.38#ibcon#flushed, iclass 21, count 2 2006.257.13:53:19.38#ibcon#about to write, iclass 21, count 2 2006.257.13:53:19.38#ibcon#wrote, iclass 21, count 2 2006.257.13:53:19.38#ibcon#about to read 3, iclass 21, count 2 2006.257.13:53:19.40#ibcon#read 3, iclass 21, count 2 2006.257.13:53:19.40#ibcon#about to read 4, iclass 21, count 2 2006.257.13:53:19.40#ibcon#read 4, iclass 21, count 2 2006.257.13:53:19.40#ibcon#about to read 5, iclass 21, count 2 2006.257.13:53:19.40#ibcon#read 5, iclass 21, count 2 2006.257.13:53:19.40#ibcon#about to read 6, iclass 21, count 2 2006.257.13:53:19.40#ibcon#read 6, iclass 21, count 2 2006.257.13:53:19.40#ibcon#end of sib2, iclass 21, count 2 2006.257.13:53:19.40#ibcon#*mode == 0, iclass 21, count 2 2006.257.13:53:19.40#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.13:53:19.40#ibcon#[27=AT02-05\r\n] 2006.257.13:53:19.40#ibcon#*before write, iclass 21, count 2 2006.257.13:53:19.40#ibcon#enter sib2, iclass 21, count 2 2006.257.13:53:19.40#ibcon#flushed, iclass 21, count 2 2006.257.13:53:19.40#ibcon#about to write, iclass 21, count 2 2006.257.13:53:19.40#ibcon#wrote, iclass 21, count 2 2006.257.13:53:19.40#ibcon#about to read 3, iclass 21, count 2 2006.257.13:53:19.43#ibcon#read 3, iclass 21, count 2 2006.257.13:53:19.43#ibcon#about to read 4, iclass 21, count 2 2006.257.13:53:19.57#ibcon#read 4, iclass 21, count 2 2006.257.13:53:19.57#ibcon#about to read 5, iclass 21, count 2 2006.257.13:53:19.57#ibcon#read 5, iclass 21, count 2 2006.257.13:53:19.57#ibcon#about to read 6, iclass 21, count 2 2006.257.13:53:19.57#ibcon#read 6, iclass 21, count 2 2006.257.13:53:19.57#ibcon#end of sib2, iclass 21, count 2 2006.257.13:53:19.57#ibcon#*after write, iclass 21, count 2 2006.257.13:53:19.57#ibcon#*before return 0, iclass 21, count 2 2006.257.13:53:19.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:19.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.13:53:19.57#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.13:53:19.57#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:19.57#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:19.68#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:19.68#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:19.68#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:53:19.68#ibcon#first serial, iclass 21, count 0 2006.257.13:53:19.68#ibcon#enter sib2, iclass 21, count 0 2006.257.13:53:19.68#ibcon#flushed, iclass 21, count 0 2006.257.13:53:19.68#ibcon#about to write, iclass 21, count 0 2006.257.13:53:19.68#ibcon#wrote, iclass 21, count 0 2006.257.13:53:19.68#ibcon#about to read 3, iclass 21, count 0 2006.257.13:53:19.70#ibcon#read 3, iclass 21, count 0 2006.257.13:53:19.70#ibcon#about to read 4, iclass 21, count 0 2006.257.13:53:19.70#ibcon#read 4, iclass 21, count 0 2006.257.13:53:19.70#ibcon#about to read 5, iclass 21, count 0 2006.257.13:53:19.70#ibcon#read 5, iclass 21, count 0 2006.257.13:53:19.70#ibcon#about to read 6, iclass 21, count 0 2006.257.13:53:19.70#ibcon#read 6, iclass 21, count 0 2006.257.13:53:19.70#ibcon#end of sib2, iclass 21, count 0 2006.257.13:53:19.70#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:53:19.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:53:19.70#ibcon#[27=USB\r\n] 2006.257.13:53:19.70#ibcon#*before write, iclass 21, count 0 2006.257.13:53:19.70#ibcon#enter sib2, iclass 21, count 0 2006.257.13:53:19.70#ibcon#flushed, iclass 21, count 0 2006.257.13:53:19.70#ibcon#about to write, iclass 21, count 0 2006.257.13:53:19.70#ibcon#wrote, iclass 21, count 0 2006.257.13:53:19.70#ibcon#about to read 3, iclass 21, count 0 2006.257.13:53:19.73#ibcon#read 3, iclass 21, count 0 2006.257.13:53:19.73#ibcon#about to read 4, iclass 21, count 0 2006.257.13:53:19.73#ibcon#read 4, iclass 21, count 0 2006.257.13:53:19.73#ibcon#about to read 5, iclass 21, count 0 2006.257.13:53:19.73#ibcon#read 5, iclass 21, count 0 2006.257.13:53:19.73#ibcon#about to read 6, iclass 21, count 0 2006.257.13:53:19.73#ibcon#read 6, iclass 21, count 0 2006.257.13:53:19.73#ibcon#end of sib2, iclass 21, count 0 2006.257.13:53:19.73#ibcon#*after write, iclass 21, count 0 2006.257.13:53:19.73#ibcon#*before return 0, iclass 21, count 0 2006.257.13:53:19.73#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:19.73#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.13:53:19.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:53:19.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:53:19.73$vck44/vblo=3,649.99 2006.257.13:53:19.73#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.13:53:19.73#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.13:53:19.73#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:19.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:53:19.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:53:19.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:53:19.73#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:53:19.73#ibcon#first serial, iclass 23, count 0 2006.257.13:53:19.73#ibcon#enter sib2, iclass 23, count 0 2006.257.13:53:19.73#ibcon#flushed, iclass 23, count 0 2006.257.13:53:19.73#ibcon#about to write, iclass 23, count 0 2006.257.13:53:19.73#ibcon#wrote, iclass 23, count 0 2006.257.13:53:19.73#ibcon#about to read 3, iclass 23, count 0 2006.257.13:53:19.75#ibcon#read 3, iclass 23, count 0 2006.257.13:53:19.75#ibcon#about to read 4, iclass 23, count 0 2006.257.13:53:19.75#ibcon#read 4, iclass 23, count 0 2006.257.13:53:19.75#ibcon#about to read 5, iclass 23, count 0 2006.257.13:53:19.75#ibcon#read 5, iclass 23, count 0 2006.257.13:53:19.75#ibcon#about to read 6, iclass 23, count 0 2006.257.13:53:19.75#ibcon#read 6, iclass 23, count 0 2006.257.13:53:19.75#ibcon#end of sib2, iclass 23, count 0 2006.257.13:53:19.75#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:53:19.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:53:19.75#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:53:19.75#ibcon#*before write, iclass 23, count 0 2006.257.13:53:19.75#ibcon#enter sib2, iclass 23, count 0 2006.257.13:53:19.75#ibcon#flushed, iclass 23, count 0 2006.257.13:53:19.75#ibcon#about to write, iclass 23, count 0 2006.257.13:53:19.75#ibcon#wrote, iclass 23, count 0 2006.257.13:53:19.75#ibcon#about to read 3, iclass 23, count 0 2006.257.13:53:19.79#ibcon#read 3, iclass 23, count 0 2006.257.13:53:19.79#ibcon#about to read 4, iclass 23, count 0 2006.257.13:53:19.79#ibcon#read 4, iclass 23, count 0 2006.257.13:53:19.79#ibcon#about to read 5, iclass 23, count 0 2006.257.13:53:19.79#ibcon#read 5, iclass 23, count 0 2006.257.13:53:19.79#ibcon#about to read 6, iclass 23, count 0 2006.257.13:53:19.79#ibcon#read 6, iclass 23, count 0 2006.257.13:53:19.79#ibcon#end of sib2, iclass 23, count 0 2006.257.13:53:19.79#ibcon#*after write, iclass 23, count 0 2006.257.13:53:19.79#ibcon#*before return 0, iclass 23, count 0 2006.257.13:53:19.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:53:19.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.13:53:19.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:53:19.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:53:19.79$vck44/vb=3,4 2006.257.13:53:19.79#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.13:53:19.79#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.13:53:19.79#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:19.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:53:19.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:53:19.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:53:19.85#ibcon#enter wrdev, iclass 25, count 2 2006.257.13:53:19.85#ibcon#first serial, iclass 25, count 2 2006.257.13:53:19.85#ibcon#enter sib2, iclass 25, count 2 2006.257.13:53:19.85#ibcon#flushed, iclass 25, count 2 2006.257.13:53:19.85#ibcon#about to write, iclass 25, count 2 2006.257.13:53:19.85#ibcon#wrote, iclass 25, count 2 2006.257.13:53:19.85#ibcon#about to read 3, iclass 25, count 2 2006.257.13:53:19.87#ibcon#read 3, iclass 25, count 2 2006.257.13:53:19.87#ibcon#about to read 4, iclass 25, count 2 2006.257.13:53:19.87#ibcon#read 4, iclass 25, count 2 2006.257.13:53:19.87#ibcon#about to read 5, iclass 25, count 2 2006.257.13:53:19.87#ibcon#read 5, iclass 25, count 2 2006.257.13:53:19.87#ibcon#about to read 6, iclass 25, count 2 2006.257.13:53:19.87#ibcon#read 6, iclass 25, count 2 2006.257.13:53:19.87#ibcon#end of sib2, iclass 25, count 2 2006.257.13:53:19.87#ibcon#*mode == 0, iclass 25, count 2 2006.257.13:53:19.87#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.13:53:19.87#ibcon#[27=AT03-04\r\n] 2006.257.13:53:19.87#ibcon#*before write, iclass 25, count 2 2006.257.13:53:19.87#ibcon#enter sib2, iclass 25, count 2 2006.257.13:53:19.87#ibcon#flushed, iclass 25, count 2 2006.257.13:53:19.87#ibcon#about to write, iclass 25, count 2 2006.257.13:53:19.87#ibcon#wrote, iclass 25, count 2 2006.257.13:53:19.87#ibcon#about to read 3, iclass 25, count 2 2006.257.13:53:19.90#ibcon#read 3, iclass 25, count 2 2006.257.13:53:19.90#ibcon#about to read 4, iclass 25, count 2 2006.257.13:53:19.90#ibcon#read 4, iclass 25, count 2 2006.257.13:53:19.90#ibcon#about to read 5, iclass 25, count 2 2006.257.13:53:19.90#ibcon#read 5, iclass 25, count 2 2006.257.13:53:19.90#ibcon#about to read 6, iclass 25, count 2 2006.257.13:53:19.90#ibcon#read 6, iclass 25, count 2 2006.257.13:53:19.90#ibcon#end of sib2, iclass 25, count 2 2006.257.13:53:19.90#ibcon#*after write, iclass 25, count 2 2006.257.13:53:19.90#ibcon#*before return 0, iclass 25, count 2 2006.257.13:53:19.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:53:19.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.13:53:19.90#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.13:53:19.90#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:19.90#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:53:20.02#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:53:20.02#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:53:20.02#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:53:20.02#ibcon#first serial, iclass 25, count 0 2006.257.13:53:20.02#ibcon#enter sib2, iclass 25, count 0 2006.257.13:53:20.02#ibcon#flushed, iclass 25, count 0 2006.257.13:53:20.02#ibcon#about to write, iclass 25, count 0 2006.257.13:53:20.02#ibcon#wrote, iclass 25, count 0 2006.257.13:53:20.02#ibcon#about to read 3, iclass 25, count 0 2006.257.13:53:20.04#ibcon#read 3, iclass 25, count 0 2006.257.13:53:20.04#ibcon#about to read 4, iclass 25, count 0 2006.257.13:53:20.04#ibcon#read 4, iclass 25, count 0 2006.257.13:53:20.04#ibcon#about to read 5, iclass 25, count 0 2006.257.13:53:20.04#ibcon#read 5, iclass 25, count 0 2006.257.13:53:20.04#ibcon#about to read 6, iclass 25, count 0 2006.257.13:53:20.04#ibcon#read 6, iclass 25, count 0 2006.257.13:53:20.04#ibcon#end of sib2, iclass 25, count 0 2006.257.13:53:20.04#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:53:20.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:53:20.04#ibcon#[27=USB\r\n] 2006.257.13:53:20.04#ibcon#*before write, iclass 25, count 0 2006.257.13:53:20.04#ibcon#enter sib2, iclass 25, count 0 2006.257.13:53:20.04#ibcon#flushed, iclass 25, count 0 2006.257.13:53:20.04#ibcon#about to write, iclass 25, count 0 2006.257.13:53:20.04#ibcon#wrote, iclass 25, count 0 2006.257.13:53:20.04#ibcon#about to read 3, iclass 25, count 0 2006.257.13:53:20.07#ibcon#read 3, iclass 25, count 0 2006.257.13:53:20.07#ibcon#about to read 4, iclass 25, count 0 2006.257.13:53:20.07#ibcon#read 4, iclass 25, count 0 2006.257.13:53:20.07#ibcon#about to read 5, iclass 25, count 0 2006.257.13:53:20.07#ibcon#read 5, iclass 25, count 0 2006.257.13:53:20.07#ibcon#about to read 6, iclass 25, count 0 2006.257.13:53:20.07#ibcon#read 6, iclass 25, count 0 2006.257.13:53:20.07#ibcon#end of sib2, iclass 25, count 0 2006.257.13:53:20.07#ibcon#*after write, iclass 25, count 0 2006.257.13:53:20.07#ibcon#*before return 0, iclass 25, count 0 2006.257.13:53:20.07#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:53:20.07#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.13:53:20.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:53:20.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:53:20.07$vck44/vblo=4,679.99 2006.257.13:53:20.07#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.13:53:20.07#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.13:53:20.07#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:20.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:53:20.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:53:20.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:53:20.07#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:53:20.07#ibcon#first serial, iclass 27, count 0 2006.257.13:53:20.07#ibcon#enter sib2, iclass 27, count 0 2006.257.13:53:20.07#ibcon#flushed, iclass 27, count 0 2006.257.13:53:20.07#ibcon#about to write, iclass 27, count 0 2006.257.13:53:20.07#ibcon#wrote, iclass 27, count 0 2006.257.13:53:20.07#ibcon#about to read 3, iclass 27, count 0 2006.257.13:53:20.09#ibcon#read 3, iclass 27, count 0 2006.257.13:53:20.09#ibcon#about to read 4, iclass 27, count 0 2006.257.13:53:20.09#ibcon#read 4, iclass 27, count 0 2006.257.13:53:20.09#ibcon#about to read 5, iclass 27, count 0 2006.257.13:53:20.09#ibcon#read 5, iclass 27, count 0 2006.257.13:53:20.09#ibcon#about to read 6, iclass 27, count 0 2006.257.13:53:20.09#ibcon#read 6, iclass 27, count 0 2006.257.13:53:20.09#ibcon#end of sib2, iclass 27, count 0 2006.257.13:53:20.09#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:53:20.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:53:20.09#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:53:20.09#ibcon#*before write, iclass 27, count 0 2006.257.13:53:20.09#ibcon#enter sib2, iclass 27, count 0 2006.257.13:53:20.09#ibcon#flushed, iclass 27, count 0 2006.257.13:53:20.09#ibcon#about to write, iclass 27, count 0 2006.257.13:53:20.09#ibcon#wrote, iclass 27, count 0 2006.257.13:53:20.09#ibcon#about to read 3, iclass 27, count 0 2006.257.13:53:20.13#ibcon#read 3, iclass 27, count 0 2006.257.13:53:20.13#ibcon#about to read 4, iclass 27, count 0 2006.257.13:53:20.13#ibcon#read 4, iclass 27, count 0 2006.257.13:53:20.13#ibcon#about to read 5, iclass 27, count 0 2006.257.13:53:20.13#ibcon#read 5, iclass 27, count 0 2006.257.13:53:20.13#ibcon#about to read 6, iclass 27, count 0 2006.257.13:53:20.13#ibcon#read 6, iclass 27, count 0 2006.257.13:53:20.13#ibcon#end of sib2, iclass 27, count 0 2006.257.13:53:20.13#ibcon#*after write, iclass 27, count 0 2006.257.13:53:20.13#ibcon#*before return 0, iclass 27, count 0 2006.257.13:53:20.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:53:20.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.13:53:20.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:53:20.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:53:20.13$vck44/vb=4,5 2006.257.13:53:20.13#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.13:53:20.13#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.13:53:20.13#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:20.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:53:20.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:53:20.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:53:20.19#ibcon#enter wrdev, iclass 29, count 2 2006.257.13:53:20.19#ibcon#first serial, iclass 29, count 2 2006.257.13:53:20.19#ibcon#enter sib2, iclass 29, count 2 2006.257.13:53:20.19#ibcon#flushed, iclass 29, count 2 2006.257.13:53:20.19#ibcon#about to write, iclass 29, count 2 2006.257.13:53:20.19#ibcon#wrote, iclass 29, count 2 2006.257.13:53:20.19#ibcon#about to read 3, iclass 29, count 2 2006.257.13:53:20.21#ibcon#read 3, iclass 29, count 2 2006.257.13:53:20.21#ibcon#about to read 4, iclass 29, count 2 2006.257.13:53:20.21#ibcon#read 4, iclass 29, count 2 2006.257.13:53:20.21#ibcon#about to read 5, iclass 29, count 2 2006.257.13:53:20.21#ibcon#read 5, iclass 29, count 2 2006.257.13:53:20.21#ibcon#about to read 6, iclass 29, count 2 2006.257.13:53:20.21#ibcon#read 6, iclass 29, count 2 2006.257.13:53:20.21#ibcon#end of sib2, iclass 29, count 2 2006.257.13:53:20.21#ibcon#*mode == 0, iclass 29, count 2 2006.257.13:53:20.21#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.13:53:20.21#ibcon#[27=AT04-05\r\n] 2006.257.13:53:20.21#ibcon#*before write, iclass 29, count 2 2006.257.13:53:20.21#ibcon#enter sib2, iclass 29, count 2 2006.257.13:53:20.21#ibcon#flushed, iclass 29, count 2 2006.257.13:53:20.21#ibcon#about to write, iclass 29, count 2 2006.257.13:53:20.21#ibcon#wrote, iclass 29, count 2 2006.257.13:53:20.21#ibcon#about to read 3, iclass 29, count 2 2006.257.13:53:20.24#ibcon#read 3, iclass 29, count 2 2006.257.13:53:20.24#ibcon#about to read 4, iclass 29, count 2 2006.257.13:53:20.24#ibcon#read 4, iclass 29, count 2 2006.257.13:53:20.24#ibcon#about to read 5, iclass 29, count 2 2006.257.13:53:20.24#ibcon#read 5, iclass 29, count 2 2006.257.13:53:20.24#ibcon#about to read 6, iclass 29, count 2 2006.257.13:53:20.24#ibcon#read 6, iclass 29, count 2 2006.257.13:53:20.24#ibcon#end of sib2, iclass 29, count 2 2006.257.13:53:20.24#ibcon#*after write, iclass 29, count 2 2006.257.13:53:20.24#ibcon#*before return 0, iclass 29, count 2 2006.257.13:53:20.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:53:20.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.13:53:20.24#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.13:53:20.24#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:20.24#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:53:20.36#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:53:20.36#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:53:20.36#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:53:20.36#ibcon#first serial, iclass 29, count 0 2006.257.13:53:20.36#ibcon#enter sib2, iclass 29, count 0 2006.257.13:53:20.36#ibcon#flushed, iclass 29, count 0 2006.257.13:53:20.36#ibcon#about to write, iclass 29, count 0 2006.257.13:53:20.36#ibcon#wrote, iclass 29, count 0 2006.257.13:53:20.36#ibcon#about to read 3, iclass 29, count 0 2006.257.13:53:20.38#ibcon#read 3, iclass 29, count 0 2006.257.13:53:20.38#ibcon#about to read 4, iclass 29, count 0 2006.257.13:53:20.38#ibcon#read 4, iclass 29, count 0 2006.257.13:53:20.38#ibcon#about to read 5, iclass 29, count 0 2006.257.13:53:20.38#ibcon#read 5, iclass 29, count 0 2006.257.13:53:20.38#ibcon#about to read 6, iclass 29, count 0 2006.257.13:53:20.38#ibcon#read 6, iclass 29, count 0 2006.257.13:53:20.38#ibcon#end of sib2, iclass 29, count 0 2006.257.13:53:20.38#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:53:20.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:53:20.38#ibcon#[27=USB\r\n] 2006.257.13:53:20.38#ibcon#*before write, iclass 29, count 0 2006.257.13:53:20.38#ibcon#enter sib2, iclass 29, count 0 2006.257.13:53:20.38#ibcon#flushed, iclass 29, count 0 2006.257.13:53:20.38#ibcon#about to write, iclass 29, count 0 2006.257.13:53:20.38#ibcon#wrote, iclass 29, count 0 2006.257.13:53:20.38#ibcon#about to read 3, iclass 29, count 0 2006.257.13:53:20.41#ibcon#read 3, iclass 29, count 0 2006.257.13:53:20.41#ibcon#about to read 4, iclass 29, count 0 2006.257.13:53:20.41#ibcon#read 4, iclass 29, count 0 2006.257.13:53:20.41#ibcon#about to read 5, iclass 29, count 0 2006.257.13:53:20.41#ibcon#read 5, iclass 29, count 0 2006.257.13:53:20.41#ibcon#about to read 6, iclass 29, count 0 2006.257.13:53:20.41#ibcon#read 6, iclass 29, count 0 2006.257.13:53:20.41#ibcon#end of sib2, iclass 29, count 0 2006.257.13:53:20.41#ibcon#*after write, iclass 29, count 0 2006.257.13:53:20.41#ibcon#*before return 0, iclass 29, count 0 2006.257.13:53:20.41#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:53:20.41#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.13:53:20.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:53:20.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:53:20.41$vck44/vblo=5,709.99 2006.257.13:53:20.41#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.13:53:20.41#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.13:53:20.41#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:20.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:20.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:20.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:20.41#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:53:20.41#ibcon#first serial, iclass 31, count 0 2006.257.13:53:20.41#ibcon#enter sib2, iclass 31, count 0 2006.257.13:53:20.41#ibcon#flushed, iclass 31, count 0 2006.257.13:53:20.42#ibcon#about to write, iclass 31, count 0 2006.257.13:53:20.42#ibcon#wrote, iclass 31, count 0 2006.257.13:53:20.42#ibcon#about to read 3, iclass 31, count 0 2006.257.13:53:20.43#ibcon#read 3, iclass 31, count 0 2006.257.13:53:20.43#ibcon#about to read 4, iclass 31, count 0 2006.257.13:53:20.43#ibcon#read 4, iclass 31, count 0 2006.257.13:53:20.43#ibcon#about to read 5, iclass 31, count 0 2006.257.13:53:20.43#ibcon#read 5, iclass 31, count 0 2006.257.13:53:20.43#ibcon#about to read 6, iclass 31, count 0 2006.257.13:53:20.43#ibcon#read 6, iclass 31, count 0 2006.257.13:53:20.43#ibcon#end of sib2, iclass 31, count 0 2006.257.13:53:20.43#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:53:20.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:53:20.43#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:53:20.43#ibcon#*before write, iclass 31, count 0 2006.257.13:53:20.43#ibcon#enter sib2, iclass 31, count 0 2006.257.13:53:20.43#ibcon#flushed, iclass 31, count 0 2006.257.13:53:20.43#ibcon#about to write, iclass 31, count 0 2006.257.13:53:20.43#ibcon#wrote, iclass 31, count 0 2006.257.13:53:20.43#ibcon#about to read 3, iclass 31, count 0 2006.257.13:53:20.47#ibcon#read 3, iclass 31, count 0 2006.257.13:53:20.47#ibcon#about to read 4, iclass 31, count 0 2006.257.13:53:20.47#ibcon#read 4, iclass 31, count 0 2006.257.13:53:20.47#ibcon#about to read 5, iclass 31, count 0 2006.257.13:53:20.47#ibcon#read 5, iclass 31, count 0 2006.257.13:53:20.47#ibcon#about to read 6, iclass 31, count 0 2006.257.13:53:20.47#ibcon#read 6, iclass 31, count 0 2006.257.13:53:20.47#ibcon#end of sib2, iclass 31, count 0 2006.257.13:53:20.47#ibcon#*after write, iclass 31, count 0 2006.257.13:53:20.47#ibcon#*before return 0, iclass 31, count 0 2006.257.13:53:20.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:20.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.13:53:20.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:53:20.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:53:20.47$vck44/vb=5,4 2006.257.13:53:20.47#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.13:53:20.47#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.13:53:20.47#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:20.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:20.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:20.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:20.53#ibcon#enter wrdev, iclass 33, count 2 2006.257.13:53:20.53#ibcon#first serial, iclass 33, count 2 2006.257.13:53:20.53#ibcon#enter sib2, iclass 33, count 2 2006.257.13:53:20.53#ibcon#flushed, iclass 33, count 2 2006.257.13:53:20.53#ibcon#about to write, iclass 33, count 2 2006.257.13:53:20.53#ibcon#wrote, iclass 33, count 2 2006.257.13:53:20.53#ibcon#about to read 3, iclass 33, count 2 2006.257.13:53:20.55#ibcon#read 3, iclass 33, count 2 2006.257.13:53:20.55#ibcon#about to read 4, iclass 33, count 2 2006.257.13:53:20.55#ibcon#read 4, iclass 33, count 2 2006.257.13:53:20.55#ibcon#about to read 5, iclass 33, count 2 2006.257.13:53:20.55#ibcon#read 5, iclass 33, count 2 2006.257.13:53:20.55#ibcon#about to read 6, iclass 33, count 2 2006.257.13:53:20.55#ibcon#read 6, iclass 33, count 2 2006.257.13:53:20.55#ibcon#end of sib2, iclass 33, count 2 2006.257.13:53:20.55#ibcon#*mode == 0, iclass 33, count 2 2006.257.13:53:20.55#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.13:53:20.55#ibcon#[27=AT05-04\r\n] 2006.257.13:53:20.55#ibcon#*before write, iclass 33, count 2 2006.257.13:53:20.55#ibcon#enter sib2, iclass 33, count 2 2006.257.13:53:20.55#ibcon#flushed, iclass 33, count 2 2006.257.13:53:20.55#ibcon#about to write, iclass 33, count 2 2006.257.13:53:20.55#ibcon#wrote, iclass 33, count 2 2006.257.13:53:20.55#ibcon#about to read 3, iclass 33, count 2 2006.257.13:53:20.58#ibcon#read 3, iclass 33, count 2 2006.257.13:53:20.58#ibcon#about to read 4, iclass 33, count 2 2006.257.13:53:20.58#ibcon#read 4, iclass 33, count 2 2006.257.13:53:20.58#ibcon#about to read 5, iclass 33, count 2 2006.257.13:53:20.58#ibcon#read 5, iclass 33, count 2 2006.257.13:53:20.58#ibcon#about to read 6, iclass 33, count 2 2006.257.13:53:20.58#ibcon#read 6, iclass 33, count 2 2006.257.13:53:20.58#ibcon#end of sib2, iclass 33, count 2 2006.257.13:53:20.58#ibcon#*after write, iclass 33, count 2 2006.257.13:53:20.58#ibcon#*before return 0, iclass 33, count 2 2006.257.13:53:20.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:20.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.13:53:20.59#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.13:53:20.59#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:20.59#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:20.70#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:20.70#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:20.70#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:53:20.70#ibcon#first serial, iclass 33, count 0 2006.257.13:53:20.70#ibcon#enter sib2, iclass 33, count 0 2006.257.13:53:20.70#ibcon#flushed, iclass 33, count 0 2006.257.13:53:20.70#ibcon#about to write, iclass 33, count 0 2006.257.13:53:20.70#ibcon#wrote, iclass 33, count 0 2006.257.13:53:20.70#ibcon#about to read 3, iclass 33, count 0 2006.257.13:53:20.72#ibcon#read 3, iclass 33, count 0 2006.257.13:53:20.72#ibcon#about to read 4, iclass 33, count 0 2006.257.13:53:20.72#ibcon#read 4, iclass 33, count 0 2006.257.13:53:20.72#ibcon#about to read 5, iclass 33, count 0 2006.257.13:53:20.72#ibcon#read 5, iclass 33, count 0 2006.257.13:53:20.72#ibcon#about to read 6, iclass 33, count 0 2006.257.13:53:20.72#ibcon#read 6, iclass 33, count 0 2006.257.13:53:20.72#ibcon#end of sib2, iclass 33, count 0 2006.257.13:53:20.72#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:53:20.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:53:20.72#ibcon#[27=USB\r\n] 2006.257.13:53:20.72#ibcon#*before write, iclass 33, count 0 2006.257.13:53:20.72#ibcon#enter sib2, iclass 33, count 0 2006.257.13:53:20.72#ibcon#flushed, iclass 33, count 0 2006.257.13:53:20.72#ibcon#about to write, iclass 33, count 0 2006.257.13:53:20.72#ibcon#wrote, iclass 33, count 0 2006.257.13:53:20.72#ibcon#about to read 3, iclass 33, count 0 2006.257.13:53:20.75#ibcon#read 3, iclass 33, count 0 2006.257.13:53:20.75#ibcon#about to read 4, iclass 33, count 0 2006.257.13:53:20.75#ibcon#read 4, iclass 33, count 0 2006.257.13:53:20.75#ibcon#about to read 5, iclass 33, count 0 2006.257.13:53:20.75#ibcon#read 5, iclass 33, count 0 2006.257.13:53:20.75#ibcon#about to read 6, iclass 33, count 0 2006.257.13:53:20.75#ibcon#read 6, iclass 33, count 0 2006.257.13:53:20.75#ibcon#end of sib2, iclass 33, count 0 2006.257.13:53:20.75#ibcon#*after write, iclass 33, count 0 2006.257.13:53:20.75#ibcon#*before return 0, iclass 33, count 0 2006.257.13:53:20.75#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:20.75#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.13:53:20.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:53:20.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:53:20.75$vck44/vblo=6,719.99 2006.257.13:53:20.75#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.13:53:20.75#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.13:53:20.75#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:20.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:20.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:20.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:20.75#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:53:20.75#ibcon#first serial, iclass 35, count 0 2006.257.13:53:20.75#ibcon#enter sib2, iclass 35, count 0 2006.257.13:53:20.75#ibcon#flushed, iclass 35, count 0 2006.257.13:53:20.75#ibcon#about to write, iclass 35, count 0 2006.257.13:53:20.76#ibcon#wrote, iclass 35, count 0 2006.257.13:53:20.76#ibcon#about to read 3, iclass 35, count 0 2006.257.13:53:20.77#ibcon#read 3, iclass 35, count 0 2006.257.13:53:20.77#ibcon#about to read 4, iclass 35, count 0 2006.257.13:53:20.77#ibcon#read 4, iclass 35, count 0 2006.257.13:53:20.77#ibcon#about to read 5, iclass 35, count 0 2006.257.13:53:20.77#ibcon#read 5, iclass 35, count 0 2006.257.13:53:20.77#ibcon#about to read 6, iclass 35, count 0 2006.257.13:53:20.77#ibcon#read 6, iclass 35, count 0 2006.257.13:53:20.77#ibcon#end of sib2, iclass 35, count 0 2006.257.13:53:20.77#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:53:20.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:53:20.77#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:53:20.77#ibcon#*before write, iclass 35, count 0 2006.257.13:53:20.77#ibcon#enter sib2, iclass 35, count 0 2006.257.13:53:20.77#ibcon#flushed, iclass 35, count 0 2006.257.13:53:20.77#ibcon#about to write, iclass 35, count 0 2006.257.13:53:20.77#ibcon#wrote, iclass 35, count 0 2006.257.13:53:20.77#ibcon#about to read 3, iclass 35, count 0 2006.257.13:53:20.81#ibcon#read 3, iclass 35, count 0 2006.257.13:53:20.81#ibcon#about to read 4, iclass 35, count 0 2006.257.13:53:20.81#ibcon#read 4, iclass 35, count 0 2006.257.13:53:20.81#ibcon#about to read 5, iclass 35, count 0 2006.257.13:53:20.81#ibcon#read 5, iclass 35, count 0 2006.257.13:53:20.81#ibcon#about to read 6, iclass 35, count 0 2006.257.13:53:20.81#ibcon#read 6, iclass 35, count 0 2006.257.13:53:20.81#ibcon#end of sib2, iclass 35, count 0 2006.257.13:53:20.81#ibcon#*after write, iclass 35, count 0 2006.257.13:53:20.81#ibcon#*before return 0, iclass 35, count 0 2006.257.13:53:20.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:20.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.13:53:20.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:53:20.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:53:20.81$vck44/vb=6,4 2006.257.13:53:20.81#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.13:53:20.81#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.13:53:20.81#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:20.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:20.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:20.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:20.87#ibcon#enter wrdev, iclass 37, count 2 2006.257.13:53:20.87#ibcon#first serial, iclass 37, count 2 2006.257.13:53:20.87#ibcon#enter sib2, iclass 37, count 2 2006.257.13:53:20.87#ibcon#flushed, iclass 37, count 2 2006.257.13:53:20.87#ibcon#about to write, iclass 37, count 2 2006.257.13:53:20.87#ibcon#wrote, iclass 37, count 2 2006.257.13:53:20.87#ibcon#about to read 3, iclass 37, count 2 2006.257.13:53:20.89#ibcon#read 3, iclass 37, count 2 2006.257.13:53:20.89#ibcon#about to read 4, iclass 37, count 2 2006.257.13:53:20.89#ibcon#read 4, iclass 37, count 2 2006.257.13:53:20.89#ibcon#about to read 5, iclass 37, count 2 2006.257.13:53:20.89#ibcon#read 5, iclass 37, count 2 2006.257.13:53:20.89#ibcon#about to read 6, iclass 37, count 2 2006.257.13:53:20.89#ibcon#read 6, iclass 37, count 2 2006.257.13:53:20.89#ibcon#end of sib2, iclass 37, count 2 2006.257.13:53:20.89#ibcon#*mode == 0, iclass 37, count 2 2006.257.13:53:20.89#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.13:53:20.89#ibcon#[27=AT06-04\r\n] 2006.257.13:53:20.89#ibcon#*before write, iclass 37, count 2 2006.257.13:53:20.89#ibcon#enter sib2, iclass 37, count 2 2006.257.13:53:20.89#ibcon#flushed, iclass 37, count 2 2006.257.13:53:20.89#ibcon#about to write, iclass 37, count 2 2006.257.13:53:20.89#ibcon#wrote, iclass 37, count 2 2006.257.13:53:20.89#ibcon#about to read 3, iclass 37, count 2 2006.257.13:53:20.92#ibcon#read 3, iclass 37, count 2 2006.257.13:53:20.92#ibcon#about to read 4, iclass 37, count 2 2006.257.13:53:20.92#ibcon#read 4, iclass 37, count 2 2006.257.13:53:20.92#ibcon#about to read 5, iclass 37, count 2 2006.257.13:53:20.92#ibcon#read 5, iclass 37, count 2 2006.257.13:53:20.92#ibcon#about to read 6, iclass 37, count 2 2006.257.13:53:20.92#ibcon#read 6, iclass 37, count 2 2006.257.13:53:20.92#ibcon#end of sib2, iclass 37, count 2 2006.257.13:53:20.92#ibcon#*after write, iclass 37, count 2 2006.257.13:53:20.92#ibcon#*before return 0, iclass 37, count 2 2006.257.13:53:20.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:20.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.13:53:20.92#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.13:53:20.92#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:20.92#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:21.04#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:21.04#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:21.04#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:53:21.04#ibcon#first serial, iclass 37, count 0 2006.257.13:53:21.04#ibcon#enter sib2, iclass 37, count 0 2006.257.13:53:21.04#ibcon#flushed, iclass 37, count 0 2006.257.13:53:21.04#ibcon#about to write, iclass 37, count 0 2006.257.13:53:21.04#ibcon#wrote, iclass 37, count 0 2006.257.13:53:21.04#ibcon#about to read 3, iclass 37, count 0 2006.257.13:53:21.06#ibcon#read 3, iclass 37, count 0 2006.257.13:53:21.06#ibcon#about to read 4, iclass 37, count 0 2006.257.13:53:21.06#ibcon#read 4, iclass 37, count 0 2006.257.13:53:21.06#ibcon#about to read 5, iclass 37, count 0 2006.257.13:53:21.06#ibcon#read 5, iclass 37, count 0 2006.257.13:53:21.06#ibcon#about to read 6, iclass 37, count 0 2006.257.13:53:21.06#ibcon#read 6, iclass 37, count 0 2006.257.13:53:21.06#ibcon#end of sib2, iclass 37, count 0 2006.257.13:53:21.06#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:53:21.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:53:21.06#ibcon#[27=USB\r\n] 2006.257.13:53:21.06#ibcon#*before write, iclass 37, count 0 2006.257.13:53:21.06#ibcon#enter sib2, iclass 37, count 0 2006.257.13:53:21.06#ibcon#flushed, iclass 37, count 0 2006.257.13:53:21.06#ibcon#about to write, iclass 37, count 0 2006.257.13:53:21.06#ibcon#wrote, iclass 37, count 0 2006.257.13:53:21.06#ibcon#about to read 3, iclass 37, count 0 2006.257.13:53:21.09#ibcon#read 3, iclass 37, count 0 2006.257.13:53:21.09#ibcon#about to read 4, iclass 37, count 0 2006.257.13:53:21.09#ibcon#read 4, iclass 37, count 0 2006.257.13:53:21.09#ibcon#about to read 5, iclass 37, count 0 2006.257.13:53:21.09#ibcon#read 5, iclass 37, count 0 2006.257.13:53:21.09#ibcon#about to read 6, iclass 37, count 0 2006.257.13:53:21.09#ibcon#read 6, iclass 37, count 0 2006.257.13:53:21.09#ibcon#end of sib2, iclass 37, count 0 2006.257.13:53:21.09#ibcon#*after write, iclass 37, count 0 2006.257.13:53:21.09#ibcon#*before return 0, iclass 37, count 0 2006.257.13:53:21.09#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:21.09#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.13:53:21.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:53:21.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:53:21.09$vck44/vblo=7,734.99 2006.257.13:53:21.09#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:53:21.09#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:53:21.09#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:21.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:21.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:21.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:21.09#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:53:21.09#ibcon#first serial, iclass 39, count 0 2006.257.13:53:21.09#ibcon#enter sib2, iclass 39, count 0 2006.257.13:53:21.09#ibcon#flushed, iclass 39, count 0 2006.257.13:53:21.09#ibcon#about to write, iclass 39, count 0 2006.257.13:53:21.09#ibcon#wrote, iclass 39, count 0 2006.257.13:53:21.09#ibcon#about to read 3, iclass 39, count 0 2006.257.13:53:21.11#ibcon#read 3, iclass 39, count 0 2006.257.13:53:21.11#ibcon#about to read 4, iclass 39, count 0 2006.257.13:53:21.11#ibcon#read 4, iclass 39, count 0 2006.257.13:53:21.11#ibcon#about to read 5, iclass 39, count 0 2006.257.13:53:21.11#ibcon#read 5, iclass 39, count 0 2006.257.13:53:21.11#ibcon#about to read 6, iclass 39, count 0 2006.257.13:53:21.11#ibcon#read 6, iclass 39, count 0 2006.257.13:53:21.11#ibcon#end of sib2, iclass 39, count 0 2006.257.13:53:21.11#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:53:21.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:53:21.11#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:53:21.11#ibcon#*before write, iclass 39, count 0 2006.257.13:53:21.11#ibcon#enter sib2, iclass 39, count 0 2006.257.13:53:21.11#ibcon#flushed, iclass 39, count 0 2006.257.13:53:21.11#ibcon#about to write, iclass 39, count 0 2006.257.13:53:21.11#ibcon#wrote, iclass 39, count 0 2006.257.13:53:21.11#ibcon#about to read 3, iclass 39, count 0 2006.257.13:53:21.15#ibcon#read 3, iclass 39, count 0 2006.257.13:53:21.15#ibcon#about to read 4, iclass 39, count 0 2006.257.13:53:21.15#ibcon#read 4, iclass 39, count 0 2006.257.13:53:21.15#ibcon#about to read 5, iclass 39, count 0 2006.257.13:53:21.15#ibcon#read 5, iclass 39, count 0 2006.257.13:53:21.15#ibcon#about to read 6, iclass 39, count 0 2006.257.13:53:21.15#ibcon#read 6, iclass 39, count 0 2006.257.13:53:21.15#ibcon#end of sib2, iclass 39, count 0 2006.257.13:53:21.15#ibcon#*after write, iclass 39, count 0 2006.257.13:53:21.15#ibcon#*before return 0, iclass 39, count 0 2006.257.13:53:21.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:21.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:53:21.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:53:21.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:53:21.15$vck44/vb=7,4 2006.257.13:53:21.15#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.13:53:21.15#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.13:53:21.15#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:21.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:21.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:21.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:21.21#ibcon#enter wrdev, iclass 3, count 2 2006.257.13:53:21.21#ibcon#first serial, iclass 3, count 2 2006.257.13:53:21.21#ibcon#enter sib2, iclass 3, count 2 2006.257.13:53:21.21#ibcon#flushed, iclass 3, count 2 2006.257.13:53:21.21#ibcon#about to write, iclass 3, count 2 2006.257.13:53:21.21#ibcon#wrote, iclass 3, count 2 2006.257.13:53:21.21#ibcon#about to read 3, iclass 3, count 2 2006.257.13:53:21.23#ibcon#read 3, iclass 3, count 2 2006.257.13:53:21.23#ibcon#about to read 4, iclass 3, count 2 2006.257.13:53:21.23#ibcon#read 4, iclass 3, count 2 2006.257.13:53:21.23#ibcon#about to read 5, iclass 3, count 2 2006.257.13:53:21.23#ibcon#read 5, iclass 3, count 2 2006.257.13:53:21.23#ibcon#about to read 6, iclass 3, count 2 2006.257.13:53:21.23#ibcon#read 6, iclass 3, count 2 2006.257.13:53:21.23#ibcon#end of sib2, iclass 3, count 2 2006.257.13:53:21.23#ibcon#*mode == 0, iclass 3, count 2 2006.257.13:53:21.23#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.13:53:21.23#ibcon#[27=AT07-04\r\n] 2006.257.13:53:21.23#ibcon#*before write, iclass 3, count 2 2006.257.13:53:21.23#ibcon#enter sib2, iclass 3, count 2 2006.257.13:53:21.23#ibcon#flushed, iclass 3, count 2 2006.257.13:53:21.23#ibcon#about to write, iclass 3, count 2 2006.257.13:53:21.23#ibcon#wrote, iclass 3, count 2 2006.257.13:53:21.23#ibcon#about to read 3, iclass 3, count 2 2006.257.13:53:21.26#ibcon#read 3, iclass 3, count 2 2006.257.13:53:21.26#ibcon#about to read 4, iclass 3, count 2 2006.257.13:53:21.26#ibcon#read 4, iclass 3, count 2 2006.257.13:53:21.26#ibcon#about to read 5, iclass 3, count 2 2006.257.13:53:21.26#ibcon#read 5, iclass 3, count 2 2006.257.13:53:21.26#ibcon#about to read 6, iclass 3, count 2 2006.257.13:53:21.26#ibcon#read 6, iclass 3, count 2 2006.257.13:53:21.26#ibcon#end of sib2, iclass 3, count 2 2006.257.13:53:21.26#ibcon#*after write, iclass 3, count 2 2006.257.13:53:21.26#ibcon#*before return 0, iclass 3, count 2 2006.257.13:53:21.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:21.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.13:53:21.26#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.13:53:21.26#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:21.26#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:21.38#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:21.38#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:21.38#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:53:21.38#ibcon#first serial, iclass 3, count 0 2006.257.13:53:21.38#ibcon#enter sib2, iclass 3, count 0 2006.257.13:53:21.38#ibcon#flushed, iclass 3, count 0 2006.257.13:53:21.38#ibcon#about to write, iclass 3, count 0 2006.257.13:53:21.38#ibcon#wrote, iclass 3, count 0 2006.257.13:53:21.38#ibcon#about to read 3, iclass 3, count 0 2006.257.13:53:21.40#ibcon#read 3, iclass 3, count 0 2006.257.13:53:21.40#ibcon#about to read 4, iclass 3, count 0 2006.257.13:53:21.40#ibcon#read 4, iclass 3, count 0 2006.257.13:53:21.40#ibcon#about to read 5, iclass 3, count 0 2006.257.13:53:21.40#ibcon#read 5, iclass 3, count 0 2006.257.13:53:21.40#ibcon#about to read 6, iclass 3, count 0 2006.257.13:53:21.40#ibcon#read 6, iclass 3, count 0 2006.257.13:53:21.40#ibcon#end of sib2, iclass 3, count 0 2006.257.13:53:21.40#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:53:21.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:53:21.40#ibcon#[27=USB\r\n] 2006.257.13:53:21.40#ibcon#*before write, iclass 3, count 0 2006.257.13:53:21.40#ibcon#enter sib2, iclass 3, count 0 2006.257.13:53:21.40#ibcon#flushed, iclass 3, count 0 2006.257.13:53:21.40#ibcon#about to write, iclass 3, count 0 2006.257.13:53:21.40#ibcon#wrote, iclass 3, count 0 2006.257.13:53:21.40#ibcon#about to read 3, iclass 3, count 0 2006.257.13:53:21.43#ibcon#read 3, iclass 3, count 0 2006.257.13:53:21.43#ibcon#about to read 4, iclass 3, count 0 2006.257.13:53:21.43#ibcon#read 4, iclass 3, count 0 2006.257.13:53:21.43#ibcon#about to read 5, iclass 3, count 0 2006.257.13:53:21.43#ibcon#read 5, iclass 3, count 0 2006.257.13:53:21.43#ibcon#about to read 6, iclass 3, count 0 2006.257.13:53:21.43#ibcon#read 6, iclass 3, count 0 2006.257.13:53:21.43#ibcon#end of sib2, iclass 3, count 0 2006.257.13:53:21.43#ibcon#*after write, iclass 3, count 0 2006.257.13:53:21.43#ibcon#*before return 0, iclass 3, count 0 2006.257.13:53:21.43#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:21.43#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.13:53:21.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:53:21.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:53:21.43$vck44/vblo=8,744.99 2006.257.13:53:21.43#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.13:53:21.43#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.13:53:21.43#ibcon#ireg 17 cls_cnt 0 2006.257.13:53:21.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:21.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:21.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:21.43#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:53:21.43#ibcon#first serial, iclass 5, count 0 2006.257.13:53:21.43#ibcon#enter sib2, iclass 5, count 0 2006.257.13:53:21.43#ibcon#flushed, iclass 5, count 0 2006.257.13:53:21.43#ibcon#about to write, iclass 5, count 0 2006.257.13:53:21.43#ibcon#wrote, iclass 5, count 0 2006.257.13:53:21.43#ibcon#about to read 3, iclass 5, count 0 2006.257.13:53:21.45#ibcon#read 3, iclass 5, count 0 2006.257.13:53:21.45#ibcon#about to read 4, iclass 5, count 0 2006.257.13:53:21.45#ibcon#read 4, iclass 5, count 0 2006.257.13:53:21.45#ibcon#about to read 5, iclass 5, count 0 2006.257.13:53:21.45#ibcon#read 5, iclass 5, count 0 2006.257.13:53:21.45#ibcon#about to read 6, iclass 5, count 0 2006.257.13:53:21.45#ibcon#read 6, iclass 5, count 0 2006.257.13:53:21.45#ibcon#end of sib2, iclass 5, count 0 2006.257.13:53:21.45#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:53:21.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:53:21.45#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:53:21.45#ibcon#*before write, iclass 5, count 0 2006.257.13:53:21.45#ibcon#enter sib2, iclass 5, count 0 2006.257.13:53:21.45#ibcon#flushed, iclass 5, count 0 2006.257.13:53:21.45#ibcon#about to write, iclass 5, count 0 2006.257.13:53:21.45#ibcon#wrote, iclass 5, count 0 2006.257.13:53:21.45#ibcon#about to read 3, iclass 5, count 0 2006.257.13:53:21.49#ibcon#read 3, iclass 5, count 0 2006.257.13:53:21.49#ibcon#about to read 4, iclass 5, count 0 2006.257.13:53:21.49#ibcon#read 4, iclass 5, count 0 2006.257.13:53:21.49#ibcon#about to read 5, iclass 5, count 0 2006.257.13:53:21.49#ibcon#read 5, iclass 5, count 0 2006.257.13:53:21.49#ibcon#about to read 6, iclass 5, count 0 2006.257.13:53:21.49#ibcon#read 6, iclass 5, count 0 2006.257.13:53:21.49#ibcon#end of sib2, iclass 5, count 0 2006.257.13:53:21.49#ibcon#*after write, iclass 5, count 0 2006.257.13:53:21.49#ibcon#*before return 0, iclass 5, count 0 2006.257.13:53:21.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:21.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.13:53:21.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:53:21.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:53:21.49$vck44/vb=8,4 2006.257.13:53:21.49#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.13:53:21.49#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.13:53:21.49#ibcon#ireg 11 cls_cnt 2 2006.257.13:53:21.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:21.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:21.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:21.55#ibcon#enter wrdev, iclass 7, count 2 2006.257.13:53:21.55#ibcon#first serial, iclass 7, count 2 2006.257.13:53:21.55#ibcon#enter sib2, iclass 7, count 2 2006.257.13:53:21.55#ibcon#flushed, iclass 7, count 2 2006.257.13:53:21.55#ibcon#about to write, iclass 7, count 2 2006.257.13:53:21.55#ibcon#wrote, iclass 7, count 2 2006.257.13:53:21.55#ibcon#about to read 3, iclass 7, count 2 2006.257.13:53:21.57#ibcon#read 3, iclass 7, count 2 2006.257.13:53:21.57#ibcon#about to read 4, iclass 7, count 2 2006.257.13:53:21.57#ibcon#read 4, iclass 7, count 2 2006.257.13:53:21.57#ibcon#about to read 5, iclass 7, count 2 2006.257.13:53:21.57#ibcon#read 5, iclass 7, count 2 2006.257.13:53:21.57#ibcon#about to read 6, iclass 7, count 2 2006.257.13:53:21.57#ibcon#read 6, iclass 7, count 2 2006.257.13:53:21.57#ibcon#end of sib2, iclass 7, count 2 2006.257.13:53:21.57#ibcon#*mode == 0, iclass 7, count 2 2006.257.13:53:21.57#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.13:53:21.57#ibcon#[27=AT08-04\r\n] 2006.257.13:53:21.57#ibcon#*before write, iclass 7, count 2 2006.257.13:53:21.57#ibcon#enter sib2, iclass 7, count 2 2006.257.13:53:21.57#ibcon#flushed, iclass 7, count 2 2006.257.13:53:21.57#ibcon#about to write, iclass 7, count 2 2006.257.13:53:21.57#ibcon#wrote, iclass 7, count 2 2006.257.13:53:21.57#ibcon#about to read 3, iclass 7, count 2 2006.257.13:53:21.60#ibcon#read 3, iclass 7, count 2 2006.257.13:53:21.60#ibcon#about to read 4, iclass 7, count 2 2006.257.13:53:21.60#ibcon#read 4, iclass 7, count 2 2006.257.13:53:21.61#ibcon#about to read 5, iclass 7, count 2 2006.257.13:53:21.61#ibcon#read 5, iclass 7, count 2 2006.257.13:53:21.61#ibcon#about to read 6, iclass 7, count 2 2006.257.13:53:21.61#ibcon#read 6, iclass 7, count 2 2006.257.13:53:21.61#ibcon#end of sib2, iclass 7, count 2 2006.257.13:53:21.61#ibcon#*after write, iclass 7, count 2 2006.257.13:53:21.61#ibcon#*before return 0, iclass 7, count 2 2006.257.13:53:21.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:21.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.13:53:21.61#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.13:53:21.61#ibcon#ireg 7 cls_cnt 0 2006.257.13:53:21.61#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:21.73#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:21.73#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:21.73#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:53:21.73#ibcon#first serial, iclass 7, count 0 2006.257.13:53:21.73#ibcon#enter sib2, iclass 7, count 0 2006.257.13:53:21.73#ibcon#flushed, iclass 7, count 0 2006.257.13:53:21.73#ibcon#about to write, iclass 7, count 0 2006.257.13:53:21.73#ibcon#wrote, iclass 7, count 0 2006.257.13:53:21.73#ibcon#about to read 3, iclass 7, count 0 2006.257.13:53:21.75#ibcon#read 3, iclass 7, count 0 2006.257.13:53:21.75#ibcon#about to read 4, iclass 7, count 0 2006.257.13:53:21.75#ibcon#read 4, iclass 7, count 0 2006.257.13:53:21.75#ibcon#about to read 5, iclass 7, count 0 2006.257.13:53:21.75#ibcon#read 5, iclass 7, count 0 2006.257.13:53:21.75#ibcon#about to read 6, iclass 7, count 0 2006.257.13:53:21.75#ibcon#read 6, iclass 7, count 0 2006.257.13:53:21.75#ibcon#end of sib2, iclass 7, count 0 2006.257.13:53:21.75#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:53:21.75#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:53:21.75#ibcon#[27=USB\r\n] 2006.257.13:53:21.75#ibcon#*before write, iclass 7, count 0 2006.257.13:53:21.75#ibcon#enter sib2, iclass 7, count 0 2006.257.13:53:21.75#ibcon#flushed, iclass 7, count 0 2006.257.13:53:21.75#ibcon#about to write, iclass 7, count 0 2006.257.13:53:21.75#ibcon#wrote, iclass 7, count 0 2006.257.13:53:21.75#ibcon#about to read 3, iclass 7, count 0 2006.257.13:53:21.78#ibcon#read 3, iclass 7, count 0 2006.257.13:53:21.78#ibcon#about to read 4, iclass 7, count 0 2006.257.13:53:21.78#ibcon#read 4, iclass 7, count 0 2006.257.13:53:21.78#ibcon#about to read 5, iclass 7, count 0 2006.257.13:53:21.78#ibcon#read 5, iclass 7, count 0 2006.257.13:53:21.78#ibcon#about to read 6, iclass 7, count 0 2006.257.13:53:21.78#ibcon#read 6, iclass 7, count 0 2006.257.13:53:21.78#ibcon#end of sib2, iclass 7, count 0 2006.257.13:53:21.78#ibcon#*after write, iclass 7, count 0 2006.257.13:53:21.78#ibcon#*before return 0, iclass 7, count 0 2006.257.13:53:21.78#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:21.78#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.13:53:21.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:53:21.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:53:21.78$vck44/vabw=wide 2006.257.13:53:21.78#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.13:53:21.78#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.13:53:21.78#ibcon#ireg 8 cls_cnt 0 2006.257.13:53:21.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:21.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:21.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:21.78#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:53:21.78#ibcon#first serial, iclass 11, count 0 2006.257.13:53:21.78#ibcon#enter sib2, iclass 11, count 0 2006.257.13:53:21.78#ibcon#flushed, iclass 11, count 0 2006.257.13:53:21.78#ibcon#about to write, iclass 11, count 0 2006.257.13:53:21.78#ibcon#wrote, iclass 11, count 0 2006.257.13:53:21.78#ibcon#about to read 3, iclass 11, count 0 2006.257.13:53:21.80#ibcon#read 3, iclass 11, count 0 2006.257.13:53:21.80#ibcon#about to read 4, iclass 11, count 0 2006.257.13:53:21.80#ibcon#read 4, iclass 11, count 0 2006.257.13:53:21.80#ibcon#about to read 5, iclass 11, count 0 2006.257.13:53:21.80#ibcon#read 5, iclass 11, count 0 2006.257.13:53:21.80#ibcon#about to read 6, iclass 11, count 0 2006.257.13:53:21.80#ibcon#read 6, iclass 11, count 0 2006.257.13:53:21.80#ibcon#end of sib2, iclass 11, count 0 2006.257.13:53:21.80#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:53:21.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:53:21.80#ibcon#[25=BW32\r\n] 2006.257.13:53:21.80#ibcon#*before write, iclass 11, count 0 2006.257.13:53:21.80#ibcon#enter sib2, iclass 11, count 0 2006.257.13:53:21.80#ibcon#flushed, iclass 11, count 0 2006.257.13:53:21.80#ibcon#about to write, iclass 11, count 0 2006.257.13:53:21.80#ibcon#wrote, iclass 11, count 0 2006.257.13:53:21.80#ibcon#about to read 3, iclass 11, count 0 2006.257.13:53:21.83#ibcon#read 3, iclass 11, count 0 2006.257.13:53:21.83#ibcon#about to read 4, iclass 11, count 0 2006.257.13:53:21.83#ibcon#read 4, iclass 11, count 0 2006.257.13:53:21.83#ibcon#about to read 5, iclass 11, count 0 2006.257.13:53:21.83#ibcon#read 5, iclass 11, count 0 2006.257.13:53:21.83#ibcon#about to read 6, iclass 11, count 0 2006.257.13:53:21.83#ibcon#read 6, iclass 11, count 0 2006.257.13:53:21.83#ibcon#end of sib2, iclass 11, count 0 2006.257.13:53:21.83#ibcon#*after write, iclass 11, count 0 2006.257.13:53:21.83#ibcon#*before return 0, iclass 11, count 0 2006.257.13:53:21.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:21.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.13:53:21.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:53:21.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:53:21.83$vck44/vbbw=wide 2006.257.13:53:21.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:53:21.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:53:21.83#ibcon#ireg 8 cls_cnt 0 2006.257.13:53:21.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:53:21.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:53:21.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:53:21.90#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:53:21.90#ibcon#first serial, iclass 13, count 0 2006.257.13:53:21.90#ibcon#enter sib2, iclass 13, count 0 2006.257.13:53:21.90#ibcon#flushed, iclass 13, count 0 2006.257.13:53:21.90#ibcon#about to write, iclass 13, count 0 2006.257.13:53:21.90#ibcon#wrote, iclass 13, count 0 2006.257.13:53:21.90#ibcon#about to read 3, iclass 13, count 0 2006.257.13:53:21.92#ibcon#read 3, iclass 13, count 0 2006.257.13:53:21.92#ibcon#about to read 4, iclass 13, count 0 2006.257.13:53:21.92#ibcon#read 4, iclass 13, count 0 2006.257.13:53:21.92#ibcon#about to read 5, iclass 13, count 0 2006.257.13:53:21.92#ibcon#read 5, iclass 13, count 0 2006.257.13:53:21.92#ibcon#about to read 6, iclass 13, count 0 2006.257.13:53:21.92#ibcon#read 6, iclass 13, count 0 2006.257.13:53:21.92#ibcon#end of sib2, iclass 13, count 0 2006.257.13:53:21.92#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:53:21.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:53:21.92#ibcon#[27=BW32\r\n] 2006.257.13:53:21.92#ibcon#*before write, iclass 13, count 0 2006.257.13:53:21.92#ibcon#enter sib2, iclass 13, count 0 2006.257.13:53:21.92#ibcon#flushed, iclass 13, count 0 2006.257.13:53:21.92#ibcon#about to write, iclass 13, count 0 2006.257.13:53:21.92#ibcon#wrote, iclass 13, count 0 2006.257.13:53:21.92#ibcon#about to read 3, iclass 13, count 0 2006.257.13:53:21.95#ibcon#read 3, iclass 13, count 0 2006.257.13:53:21.95#ibcon#about to read 4, iclass 13, count 0 2006.257.13:53:21.95#ibcon#read 4, iclass 13, count 0 2006.257.13:53:21.95#ibcon#about to read 5, iclass 13, count 0 2006.257.13:53:21.95#ibcon#read 5, iclass 13, count 0 2006.257.13:53:21.95#ibcon#about to read 6, iclass 13, count 0 2006.257.13:53:21.95#ibcon#read 6, iclass 13, count 0 2006.257.13:53:21.95#ibcon#end of sib2, iclass 13, count 0 2006.257.13:53:21.95#ibcon#*after write, iclass 13, count 0 2006.257.13:53:21.95#ibcon#*before return 0, iclass 13, count 0 2006.257.13:53:21.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:53:21.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:53:21.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:53:21.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:53:21.95$setupk4/ifdk4 2006.257.13:53:21.95$ifdk4/lo= 2006.257.13:53:21.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:53:21.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:53:21.96$ifdk4/patch= 2006.257.13:53:21.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:53:21.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:53:21.96$setupk4/!*+20s 2006.257.13:53:27.06#abcon#<5=/14 1.6 4.1 17.58 971014.1\r\n> 2006.257.13:53:27.08#abcon#{5=INTERFACE CLEAR} 2006.257.13:53:27.14#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:53:30.14#trakl#Source acquired 2006.257.13:53:30.14#flagr#flagr/antenna,acquired 2006.257.13:53:36.29$setupk4/"tpicd 2006.257.13:53:36.29$setupk4/echo=off 2006.257.13:53:36.29$setupk4/xlog=off 2006.257.13:53:36.29:!2006.257.13:57:13 2006.257.13:57:13.00:preob 2006.257.13:57:13.14/onsource/TRACKING 2006.257.13:57:13.14:!2006.257.13:57:23 2006.257.13:57:23.00:"tape 2006.257.13:57:23.00:"st=record 2006.257.13:57:23.00:data_valid=on 2006.257.13:57:23.00:midob 2006.257.13:57:24.14/onsource/TRACKING 2006.257.13:57:24.14/wx/17.58,1014.0,97 2006.257.13:57:24.35/cable/+6.4827E-03 2006.257.13:57:25.44/va/01,08,usb,yes,31,33 2006.257.13:57:25.44/va/02,07,usb,yes,33,34 2006.257.13:57:25.44/va/03,08,usb,yes,30,32 2006.257.13:57:25.44/va/04,07,usb,yes,35,36 2006.257.13:57:25.44/va/05,04,usb,yes,31,31 2006.257.13:57:25.44/va/06,04,usb,yes,34,34 2006.257.13:57:25.44/va/07,04,usb,yes,35,36 2006.257.13:57:25.44/va/08,04,usb,yes,29,36 2006.257.13:57:25.67/valo/01,524.99,yes,locked 2006.257.13:57:25.67/valo/02,534.99,yes,locked 2006.257.13:57:25.67/valo/03,564.99,yes,locked 2006.257.13:57:25.67/valo/04,624.99,yes,locked 2006.257.13:57:25.67/valo/05,734.99,yes,locked 2006.257.13:57:25.67/valo/06,814.99,yes,locked 2006.257.13:57:25.67/valo/07,864.99,yes,locked 2006.257.13:57:25.67/valo/08,884.99,yes,locked 2006.257.13:57:26.76/vb/01,04,usb,yes,30,28 2006.257.13:57:26.76/vb/02,05,usb,yes,29,29 2006.257.13:57:26.76/vb/03,04,usb,yes,30,33 2006.257.13:57:26.76/vb/04,05,usb,yes,30,29 2006.257.13:57:26.76/vb/05,04,usb,yes,26,29 2006.257.13:57:26.76/vb/06,04,usb,yes,31,27 2006.257.13:57:26.76/vb/07,04,usb,yes,31,31 2006.257.13:57:26.76/vb/08,04,usb,yes,28,32 2006.257.13:57:27.00/vblo/01,629.99,yes,locked 2006.257.13:57:27.00/vblo/02,634.99,yes,locked 2006.257.13:57:27.00/vblo/03,649.99,yes,locked 2006.257.13:57:27.00/vblo/04,679.99,yes,locked 2006.257.13:57:27.00/vblo/05,709.99,yes,locked 2006.257.13:57:27.00/vblo/06,719.99,yes,locked 2006.257.13:57:27.00/vblo/07,734.99,yes,locked 2006.257.13:57:27.00/vblo/08,744.99,yes,locked 2006.257.13:57:27.15/vabw/8 2006.257.13:57:27.30/vbbw/8 2006.257.13:57:27.39/xfe/off,on,16.0 2006.257.13:57:27.77/ifatt/23,28,28,28 2006.257.13:57:28.07/fmout-gps/S +4.56E-07 2006.257.13:57:28.12:!2006.257.13:59:03 2006.257.13:59:03.01:data_valid=off 2006.257.13:59:03.02:"et 2006.257.13:59:03.02:!+3s 2006.257.13:59:06.03:"tape 2006.257.13:59:06.04:postob 2006.257.13:59:06.11/cable/+6.4817E-03 2006.257.13:59:06.12/wx/17.58,1014.0,97 2006.257.13:59:06.17/fmout-gps/S +4.53E-07 2006.257.13:59:06.18:scan_name=257-1402,jd0609,80 2006.257.13:59:06.18:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.13:59:08.14#flagr#flagr/antenna,new-source 2006.257.13:59:08.15:checkk5 2006.257.13:59:08.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.13:59:08.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.13:59:09.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.13:59:09.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.13:59:10.10/chk_obsdata//k5ts1/T2571357??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.13:59:10.50/chk_obsdata//k5ts2/T2571357??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.13:59:10.91/chk_obsdata//k5ts3/T2571357??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.13:59:11.32/chk_obsdata//k5ts4/T2571357??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.13:59:12.04/k5log//k5ts1_log_newline 2006.257.13:59:12.76/k5log//k5ts2_log_newline 2006.257.13:59:13.46/k5log//k5ts3_log_newline 2006.257.13:59:14.16/k5log//k5ts4_log_newline 2006.257.13:59:14.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.13:59:14.18:setupk4=1 2006.257.13:59:14.18$setupk4/echo=on 2006.257.13:59:14.18$setupk4/pcalon 2006.257.13:59:14.18$pcalon/"no phase cal control is implemented here 2006.257.13:59:14.18$setupk4/"tpicd=stop 2006.257.13:59:14.18$setupk4/"rec=synch_on 2006.257.13:59:14.18$setupk4/"rec_mode=128 2006.257.13:59:14.18$setupk4/!* 2006.257.13:59:14.18$setupk4/recpk4 2006.257.13:59:14.18$recpk4/recpatch= 2006.257.13:59:14.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.13:59:14.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.13:59:14.19$setupk4/vck44 2006.257.13:59:14.19$vck44/valo=1,524.99 2006.257.13:59:14.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.13:59:14.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.13:59:14.19#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:14.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:14.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:14.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:14.19#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:59:14.19#ibcon#first serial, iclass 3, count 0 2006.257.13:59:14.19#ibcon#enter sib2, iclass 3, count 0 2006.257.13:59:14.19#ibcon#flushed, iclass 3, count 0 2006.257.13:59:14.19#ibcon#about to write, iclass 3, count 0 2006.257.13:59:14.19#ibcon#wrote, iclass 3, count 0 2006.257.13:59:14.19#ibcon#about to read 3, iclass 3, count 0 2006.257.13:59:14.20#ibcon#read 3, iclass 3, count 0 2006.257.13:59:14.20#ibcon#about to read 4, iclass 3, count 0 2006.257.13:59:14.20#ibcon#read 4, iclass 3, count 0 2006.257.13:59:14.20#ibcon#about to read 5, iclass 3, count 0 2006.257.13:59:14.20#ibcon#read 5, iclass 3, count 0 2006.257.13:59:14.20#ibcon#about to read 6, iclass 3, count 0 2006.257.13:59:14.20#ibcon#read 6, iclass 3, count 0 2006.257.13:59:14.20#ibcon#end of sib2, iclass 3, count 0 2006.257.13:59:14.20#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:59:14.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:59:14.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.13:59:14.20#ibcon#*before write, iclass 3, count 0 2006.257.13:59:14.20#ibcon#enter sib2, iclass 3, count 0 2006.257.13:59:14.20#ibcon#flushed, iclass 3, count 0 2006.257.13:59:14.20#ibcon#about to write, iclass 3, count 0 2006.257.13:59:14.20#ibcon#wrote, iclass 3, count 0 2006.257.13:59:14.20#ibcon#about to read 3, iclass 3, count 0 2006.257.13:59:14.25#ibcon#read 3, iclass 3, count 0 2006.257.13:59:14.25#ibcon#about to read 4, iclass 3, count 0 2006.257.13:59:14.25#ibcon#read 4, iclass 3, count 0 2006.257.13:59:14.25#ibcon#about to read 5, iclass 3, count 0 2006.257.13:59:14.25#ibcon#read 5, iclass 3, count 0 2006.257.13:59:14.25#ibcon#about to read 6, iclass 3, count 0 2006.257.13:59:14.25#ibcon#read 6, iclass 3, count 0 2006.257.13:59:14.25#ibcon#end of sib2, iclass 3, count 0 2006.257.13:59:14.25#ibcon#*after write, iclass 3, count 0 2006.257.13:59:14.25#ibcon#*before return 0, iclass 3, count 0 2006.257.13:59:14.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:14.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:14.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:59:14.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:59:14.25$vck44/va=1,8 2006.257.13:59:14.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.13:59:14.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.13:59:14.25#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:14.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:14.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:14.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:14.25#ibcon#enter wrdev, iclass 5, count 2 2006.257.13:59:14.25#ibcon#first serial, iclass 5, count 2 2006.257.13:59:14.25#ibcon#enter sib2, iclass 5, count 2 2006.257.13:59:14.25#ibcon#flushed, iclass 5, count 2 2006.257.13:59:14.25#ibcon#about to write, iclass 5, count 2 2006.257.13:59:14.25#ibcon#wrote, iclass 5, count 2 2006.257.13:59:14.25#ibcon#about to read 3, iclass 5, count 2 2006.257.13:59:14.27#ibcon#read 3, iclass 5, count 2 2006.257.13:59:14.27#ibcon#about to read 4, iclass 5, count 2 2006.257.13:59:14.27#ibcon#read 4, iclass 5, count 2 2006.257.13:59:14.27#ibcon#about to read 5, iclass 5, count 2 2006.257.13:59:14.27#ibcon#read 5, iclass 5, count 2 2006.257.13:59:14.27#ibcon#about to read 6, iclass 5, count 2 2006.257.13:59:14.27#ibcon#read 6, iclass 5, count 2 2006.257.13:59:14.27#ibcon#end of sib2, iclass 5, count 2 2006.257.13:59:14.27#ibcon#*mode == 0, iclass 5, count 2 2006.257.13:59:14.27#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.13:59:14.27#ibcon#[25=AT01-08\r\n] 2006.257.13:59:14.27#ibcon#*before write, iclass 5, count 2 2006.257.13:59:14.27#ibcon#enter sib2, iclass 5, count 2 2006.257.13:59:14.27#ibcon#flushed, iclass 5, count 2 2006.257.13:59:14.27#ibcon#about to write, iclass 5, count 2 2006.257.13:59:14.27#ibcon#wrote, iclass 5, count 2 2006.257.13:59:14.27#ibcon#about to read 3, iclass 5, count 2 2006.257.13:59:14.30#ibcon#read 3, iclass 5, count 2 2006.257.13:59:14.30#ibcon#about to read 4, iclass 5, count 2 2006.257.13:59:14.30#ibcon#read 4, iclass 5, count 2 2006.257.13:59:14.30#ibcon#about to read 5, iclass 5, count 2 2006.257.13:59:14.30#ibcon#read 5, iclass 5, count 2 2006.257.13:59:14.30#ibcon#about to read 6, iclass 5, count 2 2006.257.13:59:14.30#ibcon#read 6, iclass 5, count 2 2006.257.13:59:14.30#ibcon#end of sib2, iclass 5, count 2 2006.257.13:59:14.30#ibcon#*after write, iclass 5, count 2 2006.257.13:59:14.30#ibcon#*before return 0, iclass 5, count 2 2006.257.13:59:14.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:14.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:14.30#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.13:59:14.30#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:14.30#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:14.42#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:14.42#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:14.42#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:59:14.42#ibcon#first serial, iclass 5, count 0 2006.257.13:59:14.42#ibcon#enter sib2, iclass 5, count 0 2006.257.13:59:14.42#ibcon#flushed, iclass 5, count 0 2006.257.13:59:14.42#ibcon#about to write, iclass 5, count 0 2006.257.13:59:14.42#ibcon#wrote, iclass 5, count 0 2006.257.13:59:14.42#ibcon#about to read 3, iclass 5, count 0 2006.257.13:59:14.44#ibcon#read 3, iclass 5, count 0 2006.257.13:59:14.44#ibcon#about to read 4, iclass 5, count 0 2006.257.13:59:14.44#ibcon#read 4, iclass 5, count 0 2006.257.13:59:14.44#ibcon#about to read 5, iclass 5, count 0 2006.257.13:59:14.44#ibcon#read 5, iclass 5, count 0 2006.257.13:59:14.44#ibcon#about to read 6, iclass 5, count 0 2006.257.13:59:14.44#ibcon#read 6, iclass 5, count 0 2006.257.13:59:14.44#ibcon#end of sib2, iclass 5, count 0 2006.257.13:59:14.44#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:59:14.44#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:59:14.44#ibcon#[25=USB\r\n] 2006.257.13:59:14.44#ibcon#*before write, iclass 5, count 0 2006.257.13:59:14.44#ibcon#enter sib2, iclass 5, count 0 2006.257.13:59:14.44#ibcon#flushed, iclass 5, count 0 2006.257.13:59:14.44#ibcon#about to write, iclass 5, count 0 2006.257.13:59:14.44#ibcon#wrote, iclass 5, count 0 2006.257.13:59:14.44#ibcon#about to read 3, iclass 5, count 0 2006.257.13:59:14.47#ibcon#read 3, iclass 5, count 0 2006.257.13:59:14.47#ibcon#about to read 4, iclass 5, count 0 2006.257.13:59:14.47#ibcon#read 4, iclass 5, count 0 2006.257.13:59:14.47#ibcon#about to read 5, iclass 5, count 0 2006.257.13:59:14.47#ibcon#read 5, iclass 5, count 0 2006.257.13:59:14.47#ibcon#about to read 6, iclass 5, count 0 2006.257.13:59:14.47#ibcon#read 6, iclass 5, count 0 2006.257.13:59:14.47#ibcon#end of sib2, iclass 5, count 0 2006.257.13:59:14.47#ibcon#*after write, iclass 5, count 0 2006.257.13:59:14.47#ibcon#*before return 0, iclass 5, count 0 2006.257.13:59:14.47#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:14.47#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:14.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:59:14.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:59:14.47$vck44/valo=2,534.99 2006.257.13:59:14.47#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.13:59:14.47#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.13:59:14.47#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:14.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:14.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:14.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:14.47#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:59:14.47#ibcon#first serial, iclass 7, count 0 2006.257.13:59:14.47#ibcon#enter sib2, iclass 7, count 0 2006.257.13:59:14.47#ibcon#flushed, iclass 7, count 0 2006.257.13:59:14.47#ibcon#about to write, iclass 7, count 0 2006.257.13:59:14.47#ibcon#wrote, iclass 7, count 0 2006.257.13:59:14.47#ibcon#about to read 3, iclass 7, count 0 2006.257.13:59:14.49#ibcon#read 3, iclass 7, count 0 2006.257.13:59:14.49#ibcon#about to read 4, iclass 7, count 0 2006.257.13:59:14.49#ibcon#read 4, iclass 7, count 0 2006.257.13:59:14.49#ibcon#about to read 5, iclass 7, count 0 2006.257.13:59:14.49#ibcon#read 5, iclass 7, count 0 2006.257.13:59:14.49#ibcon#about to read 6, iclass 7, count 0 2006.257.13:59:14.49#ibcon#read 6, iclass 7, count 0 2006.257.13:59:14.49#ibcon#end of sib2, iclass 7, count 0 2006.257.13:59:14.49#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:59:14.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:59:14.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.13:59:14.49#ibcon#*before write, iclass 7, count 0 2006.257.13:59:14.49#ibcon#enter sib2, iclass 7, count 0 2006.257.13:59:14.49#ibcon#flushed, iclass 7, count 0 2006.257.13:59:14.49#ibcon#about to write, iclass 7, count 0 2006.257.13:59:14.49#ibcon#wrote, iclass 7, count 0 2006.257.13:59:14.49#ibcon#about to read 3, iclass 7, count 0 2006.257.13:59:14.53#ibcon#read 3, iclass 7, count 0 2006.257.13:59:14.53#ibcon#about to read 4, iclass 7, count 0 2006.257.13:59:14.53#ibcon#read 4, iclass 7, count 0 2006.257.13:59:14.53#ibcon#about to read 5, iclass 7, count 0 2006.257.13:59:14.53#ibcon#read 5, iclass 7, count 0 2006.257.13:59:14.53#ibcon#about to read 6, iclass 7, count 0 2006.257.13:59:14.53#ibcon#read 6, iclass 7, count 0 2006.257.13:59:14.53#ibcon#end of sib2, iclass 7, count 0 2006.257.13:59:14.53#ibcon#*after write, iclass 7, count 0 2006.257.13:59:14.53#ibcon#*before return 0, iclass 7, count 0 2006.257.13:59:14.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:14.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:14.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:59:14.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:59:14.53$vck44/va=2,7 2006.257.13:59:14.53#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.13:59:14.53#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.13:59:14.53#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:14.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:14.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:14.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:14.59#ibcon#enter wrdev, iclass 11, count 2 2006.257.13:59:14.59#ibcon#first serial, iclass 11, count 2 2006.257.13:59:14.59#ibcon#enter sib2, iclass 11, count 2 2006.257.13:59:14.59#ibcon#flushed, iclass 11, count 2 2006.257.13:59:14.59#ibcon#about to write, iclass 11, count 2 2006.257.13:59:14.59#ibcon#wrote, iclass 11, count 2 2006.257.13:59:14.59#ibcon#about to read 3, iclass 11, count 2 2006.257.13:59:14.61#ibcon#read 3, iclass 11, count 2 2006.257.13:59:14.61#ibcon#about to read 4, iclass 11, count 2 2006.257.13:59:14.61#ibcon#read 4, iclass 11, count 2 2006.257.13:59:14.61#ibcon#about to read 5, iclass 11, count 2 2006.257.13:59:14.61#ibcon#read 5, iclass 11, count 2 2006.257.13:59:14.61#ibcon#about to read 6, iclass 11, count 2 2006.257.13:59:14.61#ibcon#read 6, iclass 11, count 2 2006.257.13:59:14.61#ibcon#end of sib2, iclass 11, count 2 2006.257.13:59:14.61#ibcon#*mode == 0, iclass 11, count 2 2006.257.13:59:14.61#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.13:59:14.61#ibcon#[25=AT02-07\r\n] 2006.257.13:59:14.61#ibcon#*before write, iclass 11, count 2 2006.257.13:59:14.61#ibcon#enter sib2, iclass 11, count 2 2006.257.13:59:14.61#ibcon#flushed, iclass 11, count 2 2006.257.13:59:14.61#ibcon#about to write, iclass 11, count 2 2006.257.13:59:14.61#ibcon#wrote, iclass 11, count 2 2006.257.13:59:14.61#ibcon#about to read 3, iclass 11, count 2 2006.257.13:59:14.64#ibcon#read 3, iclass 11, count 2 2006.257.13:59:14.64#ibcon#about to read 4, iclass 11, count 2 2006.257.13:59:14.64#ibcon#read 4, iclass 11, count 2 2006.257.13:59:14.64#ibcon#about to read 5, iclass 11, count 2 2006.257.13:59:14.64#ibcon#read 5, iclass 11, count 2 2006.257.13:59:14.64#ibcon#about to read 6, iclass 11, count 2 2006.257.13:59:14.64#ibcon#read 6, iclass 11, count 2 2006.257.13:59:14.64#ibcon#end of sib2, iclass 11, count 2 2006.257.13:59:14.64#ibcon#*after write, iclass 11, count 2 2006.257.13:59:14.64#ibcon#*before return 0, iclass 11, count 2 2006.257.13:59:14.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:14.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:14.64#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.13:59:14.64#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:14.64#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:14.76#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:14.76#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:14.76#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:59:14.76#ibcon#first serial, iclass 11, count 0 2006.257.13:59:14.76#ibcon#enter sib2, iclass 11, count 0 2006.257.13:59:14.76#ibcon#flushed, iclass 11, count 0 2006.257.13:59:14.76#ibcon#about to write, iclass 11, count 0 2006.257.13:59:14.76#ibcon#wrote, iclass 11, count 0 2006.257.13:59:14.76#ibcon#about to read 3, iclass 11, count 0 2006.257.13:59:14.78#ibcon#read 3, iclass 11, count 0 2006.257.13:59:14.78#ibcon#about to read 4, iclass 11, count 0 2006.257.13:59:14.78#ibcon#read 4, iclass 11, count 0 2006.257.13:59:14.78#ibcon#about to read 5, iclass 11, count 0 2006.257.13:59:14.78#ibcon#read 5, iclass 11, count 0 2006.257.13:59:14.78#ibcon#about to read 6, iclass 11, count 0 2006.257.13:59:14.78#ibcon#read 6, iclass 11, count 0 2006.257.13:59:14.78#ibcon#end of sib2, iclass 11, count 0 2006.257.13:59:14.78#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:59:14.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:59:14.78#ibcon#[25=USB\r\n] 2006.257.13:59:14.78#ibcon#*before write, iclass 11, count 0 2006.257.13:59:14.78#ibcon#enter sib2, iclass 11, count 0 2006.257.13:59:14.78#ibcon#flushed, iclass 11, count 0 2006.257.13:59:14.78#ibcon#about to write, iclass 11, count 0 2006.257.13:59:14.78#ibcon#wrote, iclass 11, count 0 2006.257.13:59:14.78#ibcon#about to read 3, iclass 11, count 0 2006.257.13:59:14.81#ibcon#read 3, iclass 11, count 0 2006.257.13:59:14.81#ibcon#about to read 4, iclass 11, count 0 2006.257.13:59:14.81#ibcon#read 4, iclass 11, count 0 2006.257.13:59:14.81#ibcon#about to read 5, iclass 11, count 0 2006.257.13:59:14.81#ibcon#read 5, iclass 11, count 0 2006.257.13:59:14.81#ibcon#about to read 6, iclass 11, count 0 2006.257.13:59:14.81#ibcon#read 6, iclass 11, count 0 2006.257.13:59:14.81#ibcon#end of sib2, iclass 11, count 0 2006.257.13:59:14.81#ibcon#*after write, iclass 11, count 0 2006.257.13:59:14.81#ibcon#*before return 0, iclass 11, count 0 2006.257.13:59:14.81#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:14.81#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:14.81#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:59:14.81#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:59:14.81$vck44/valo=3,564.99 2006.257.13:59:14.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:59:14.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:59:14.81#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:14.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:14.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:14.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:14.81#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:59:14.81#ibcon#first serial, iclass 13, count 0 2006.257.13:59:14.81#ibcon#enter sib2, iclass 13, count 0 2006.257.13:59:14.81#ibcon#flushed, iclass 13, count 0 2006.257.13:59:14.81#ibcon#about to write, iclass 13, count 0 2006.257.13:59:14.81#ibcon#wrote, iclass 13, count 0 2006.257.13:59:14.81#ibcon#about to read 3, iclass 13, count 0 2006.257.13:59:14.83#ibcon#read 3, iclass 13, count 0 2006.257.13:59:14.83#ibcon#about to read 4, iclass 13, count 0 2006.257.13:59:14.83#ibcon#read 4, iclass 13, count 0 2006.257.13:59:14.83#ibcon#about to read 5, iclass 13, count 0 2006.257.13:59:14.83#ibcon#read 5, iclass 13, count 0 2006.257.13:59:14.83#ibcon#about to read 6, iclass 13, count 0 2006.257.13:59:14.83#ibcon#read 6, iclass 13, count 0 2006.257.13:59:14.83#ibcon#end of sib2, iclass 13, count 0 2006.257.13:59:14.83#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:59:14.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:59:14.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.13:59:14.83#ibcon#*before write, iclass 13, count 0 2006.257.13:59:14.83#ibcon#enter sib2, iclass 13, count 0 2006.257.13:59:14.83#ibcon#flushed, iclass 13, count 0 2006.257.13:59:14.83#ibcon#about to write, iclass 13, count 0 2006.257.13:59:14.83#ibcon#wrote, iclass 13, count 0 2006.257.13:59:14.83#ibcon#about to read 3, iclass 13, count 0 2006.257.13:59:14.87#ibcon#read 3, iclass 13, count 0 2006.257.13:59:14.87#ibcon#about to read 4, iclass 13, count 0 2006.257.13:59:14.87#ibcon#read 4, iclass 13, count 0 2006.257.13:59:14.87#ibcon#about to read 5, iclass 13, count 0 2006.257.13:59:14.87#ibcon#read 5, iclass 13, count 0 2006.257.13:59:14.87#ibcon#about to read 6, iclass 13, count 0 2006.257.13:59:14.87#ibcon#read 6, iclass 13, count 0 2006.257.13:59:14.87#ibcon#end of sib2, iclass 13, count 0 2006.257.13:59:14.87#ibcon#*after write, iclass 13, count 0 2006.257.13:59:14.87#ibcon#*before return 0, iclass 13, count 0 2006.257.13:59:14.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:14.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:14.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:59:14.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:59:14.87$vck44/va=3,8 2006.257.13:59:14.87#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.13:59:14.87#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.13:59:14.87#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:14.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:14.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:14.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:14.93#ibcon#enter wrdev, iclass 15, count 2 2006.257.13:59:14.93#ibcon#first serial, iclass 15, count 2 2006.257.13:59:14.93#ibcon#enter sib2, iclass 15, count 2 2006.257.13:59:14.93#ibcon#flushed, iclass 15, count 2 2006.257.13:59:14.93#ibcon#about to write, iclass 15, count 2 2006.257.13:59:14.93#ibcon#wrote, iclass 15, count 2 2006.257.13:59:14.93#ibcon#about to read 3, iclass 15, count 2 2006.257.13:59:14.95#ibcon#read 3, iclass 15, count 2 2006.257.13:59:14.95#ibcon#about to read 4, iclass 15, count 2 2006.257.13:59:14.95#ibcon#read 4, iclass 15, count 2 2006.257.13:59:14.95#ibcon#about to read 5, iclass 15, count 2 2006.257.13:59:14.95#ibcon#read 5, iclass 15, count 2 2006.257.13:59:14.95#ibcon#about to read 6, iclass 15, count 2 2006.257.13:59:14.95#ibcon#read 6, iclass 15, count 2 2006.257.13:59:14.95#ibcon#end of sib2, iclass 15, count 2 2006.257.13:59:14.95#ibcon#*mode == 0, iclass 15, count 2 2006.257.13:59:14.95#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.13:59:14.95#ibcon#[25=AT03-08\r\n] 2006.257.13:59:14.95#ibcon#*before write, iclass 15, count 2 2006.257.13:59:14.95#ibcon#enter sib2, iclass 15, count 2 2006.257.13:59:14.95#ibcon#flushed, iclass 15, count 2 2006.257.13:59:14.95#ibcon#about to write, iclass 15, count 2 2006.257.13:59:14.95#ibcon#wrote, iclass 15, count 2 2006.257.13:59:14.95#ibcon#about to read 3, iclass 15, count 2 2006.257.13:59:14.98#ibcon#read 3, iclass 15, count 2 2006.257.13:59:14.98#ibcon#about to read 4, iclass 15, count 2 2006.257.13:59:14.98#ibcon#read 4, iclass 15, count 2 2006.257.13:59:14.98#ibcon#about to read 5, iclass 15, count 2 2006.257.13:59:14.98#ibcon#read 5, iclass 15, count 2 2006.257.13:59:14.98#ibcon#about to read 6, iclass 15, count 2 2006.257.13:59:14.98#ibcon#read 6, iclass 15, count 2 2006.257.13:59:14.98#ibcon#end of sib2, iclass 15, count 2 2006.257.13:59:14.98#ibcon#*after write, iclass 15, count 2 2006.257.13:59:14.98#ibcon#*before return 0, iclass 15, count 2 2006.257.13:59:14.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:14.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:14.98#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.13:59:14.98#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:14.98#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:15.10#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:15.10#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:15.10#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:59:15.10#ibcon#first serial, iclass 15, count 0 2006.257.13:59:15.10#ibcon#enter sib2, iclass 15, count 0 2006.257.13:59:15.10#ibcon#flushed, iclass 15, count 0 2006.257.13:59:15.10#ibcon#about to write, iclass 15, count 0 2006.257.13:59:15.10#ibcon#wrote, iclass 15, count 0 2006.257.13:59:15.10#ibcon#about to read 3, iclass 15, count 0 2006.257.13:59:15.12#ibcon#read 3, iclass 15, count 0 2006.257.13:59:15.12#ibcon#about to read 4, iclass 15, count 0 2006.257.13:59:15.12#ibcon#read 4, iclass 15, count 0 2006.257.13:59:15.12#ibcon#about to read 5, iclass 15, count 0 2006.257.13:59:15.12#ibcon#read 5, iclass 15, count 0 2006.257.13:59:15.12#ibcon#about to read 6, iclass 15, count 0 2006.257.13:59:15.12#ibcon#read 6, iclass 15, count 0 2006.257.13:59:15.12#ibcon#end of sib2, iclass 15, count 0 2006.257.13:59:15.12#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:59:15.12#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:59:15.12#ibcon#[25=USB\r\n] 2006.257.13:59:15.12#ibcon#*before write, iclass 15, count 0 2006.257.13:59:15.12#ibcon#enter sib2, iclass 15, count 0 2006.257.13:59:15.12#ibcon#flushed, iclass 15, count 0 2006.257.13:59:15.12#ibcon#about to write, iclass 15, count 0 2006.257.13:59:15.12#ibcon#wrote, iclass 15, count 0 2006.257.13:59:15.12#ibcon#about to read 3, iclass 15, count 0 2006.257.13:59:15.15#ibcon#read 3, iclass 15, count 0 2006.257.13:59:15.15#ibcon#about to read 4, iclass 15, count 0 2006.257.13:59:15.15#ibcon#read 4, iclass 15, count 0 2006.257.13:59:15.15#ibcon#about to read 5, iclass 15, count 0 2006.257.13:59:15.15#ibcon#read 5, iclass 15, count 0 2006.257.13:59:15.15#ibcon#about to read 6, iclass 15, count 0 2006.257.13:59:15.15#ibcon#read 6, iclass 15, count 0 2006.257.13:59:15.15#ibcon#end of sib2, iclass 15, count 0 2006.257.13:59:15.15#ibcon#*after write, iclass 15, count 0 2006.257.13:59:15.15#ibcon#*before return 0, iclass 15, count 0 2006.257.13:59:15.15#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:15.15#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:15.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:59:15.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:59:15.15$vck44/valo=4,624.99 2006.257.13:59:15.15#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.13:59:15.15#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.13:59:15.15#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:15.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:15.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:15.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:15.15#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:59:15.15#ibcon#first serial, iclass 17, count 0 2006.257.13:59:15.15#ibcon#enter sib2, iclass 17, count 0 2006.257.13:59:15.15#ibcon#flushed, iclass 17, count 0 2006.257.13:59:15.15#ibcon#about to write, iclass 17, count 0 2006.257.13:59:15.15#ibcon#wrote, iclass 17, count 0 2006.257.13:59:15.15#ibcon#about to read 3, iclass 17, count 0 2006.257.13:59:15.17#ibcon#read 3, iclass 17, count 0 2006.257.13:59:15.17#ibcon#about to read 4, iclass 17, count 0 2006.257.13:59:15.17#ibcon#read 4, iclass 17, count 0 2006.257.13:59:15.17#ibcon#about to read 5, iclass 17, count 0 2006.257.13:59:15.17#ibcon#read 5, iclass 17, count 0 2006.257.13:59:15.17#ibcon#about to read 6, iclass 17, count 0 2006.257.13:59:15.17#ibcon#read 6, iclass 17, count 0 2006.257.13:59:15.17#ibcon#end of sib2, iclass 17, count 0 2006.257.13:59:15.17#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:59:15.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:59:15.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.13:59:15.17#ibcon#*before write, iclass 17, count 0 2006.257.13:59:15.17#ibcon#enter sib2, iclass 17, count 0 2006.257.13:59:15.17#ibcon#flushed, iclass 17, count 0 2006.257.13:59:15.17#ibcon#about to write, iclass 17, count 0 2006.257.13:59:15.17#ibcon#wrote, iclass 17, count 0 2006.257.13:59:15.17#ibcon#about to read 3, iclass 17, count 0 2006.257.13:59:15.21#ibcon#read 3, iclass 17, count 0 2006.257.13:59:15.21#ibcon#about to read 4, iclass 17, count 0 2006.257.13:59:15.21#ibcon#read 4, iclass 17, count 0 2006.257.13:59:15.21#ibcon#about to read 5, iclass 17, count 0 2006.257.13:59:15.21#ibcon#read 5, iclass 17, count 0 2006.257.13:59:15.21#ibcon#about to read 6, iclass 17, count 0 2006.257.13:59:15.21#ibcon#read 6, iclass 17, count 0 2006.257.13:59:15.21#ibcon#end of sib2, iclass 17, count 0 2006.257.13:59:15.21#ibcon#*after write, iclass 17, count 0 2006.257.13:59:15.21#ibcon#*before return 0, iclass 17, count 0 2006.257.13:59:15.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:15.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:15.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:59:15.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:59:15.21$vck44/va=4,7 2006.257.13:59:15.21#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.13:59:15.21#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.13:59:15.21#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:15.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:15.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:15.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:15.27#ibcon#enter wrdev, iclass 19, count 2 2006.257.13:59:15.27#ibcon#first serial, iclass 19, count 2 2006.257.13:59:15.27#ibcon#enter sib2, iclass 19, count 2 2006.257.13:59:15.27#ibcon#flushed, iclass 19, count 2 2006.257.13:59:15.27#ibcon#about to write, iclass 19, count 2 2006.257.13:59:15.27#ibcon#wrote, iclass 19, count 2 2006.257.13:59:15.27#ibcon#about to read 3, iclass 19, count 2 2006.257.13:59:15.29#ibcon#read 3, iclass 19, count 2 2006.257.13:59:15.29#ibcon#about to read 4, iclass 19, count 2 2006.257.13:59:15.29#ibcon#read 4, iclass 19, count 2 2006.257.13:59:15.29#ibcon#about to read 5, iclass 19, count 2 2006.257.13:59:15.29#ibcon#read 5, iclass 19, count 2 2006.257.13:59:15.29#ibcon#about to read 6, iclass 19, count 2 2006.257.13:59:15.29#ibcon#read 6, iclass 19, count 2 2006.257.13:59:15.29#ibcon#end of sib2, iclass 19, count 2 2006.257.13:59:15.29#ibcon#*mode == 0, iclass 19, count 2 2006.257.13:59:15.29#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.13:59:15.29#ibcon#[25=AT04-07\r\n] 2006.257.13:59:15.29#ibcon#*before write, iclass 19, count 2 2006.257.13:59:15.29#ibcon#enter sib2, iclass 19, count 2 2006.257.13:59:15.29#ibcon#flushed, iclass 19, count 2 2006.257.13:59:15.29#ibcon#about to write, iclass 19, count 2 2006.257.13:59:15.29#ibcon#wrote, iclass 19, count 2 2006.257.13:59:15.29#ibcon#about to read 3, iclass 19, count 2 2006.257.13:59:15.32#ibcon#read 3, iclass 19, count 2 2006.257.13:59:15.32#ibcon#about to read 4, iclass 19, count 2 2006.257.13:59:15.32#ibcon#read 4, iclass 19, count 2 2006.257.13:59:15.32#ibcon#about to read 5, iclass 19, count 2 2006.257.13:59:15.32#ibcon#read 5, iclass 19, count 2 2006.257.13:59:15.32#ibcon#about to read 6, iclass 19, count 2 2006.257.13:59:15.32#ibcon#read 6, iclass 19, count 2 2006.257.13:59:15.32#ibcon#end of sib2, iclass 19, count 2 2006.257.13:59:15.32#ibcon#*after write, iclass 19, count 2 2006.257.13:59:15.32#ibcon#*before return 0, iclass 19, count 2 2006.257.13:59:15.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:15.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:15.32#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.13:59:15.32#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:15.32#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:15.44#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:15.44#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:15.44#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:59:15.44#ibcon#first serial, iclass 19, count 0 2006.257.13:59:15.44#ibcon#enter sib2, iclass 19, count 0 2006.257.13:59:15.44#ibcon#flushed, iclass 19, count 0 2006.257.13:59:15.44#ibcon#about to write, iclass 19, count 0 2006.257.13:59:15.44#ibcon#wrote, iclass 19, count 0 2006.257.13:59:15.44#ibcon#about to read 3, iclass 19, count 0 2006.257.13:59:15.46#ibcon#read 3, iclass 19, count 0 2006.257.13:59:15.46#ibcon#about to read 4, iclass 19, count 0 2006.257.13:59:15.46#ibcon#read 4, iclass 19, count 0 2006.257.13:59:15.46#ibcon#about to read 5, iclass 19, count 0 2006.257.13:59:15.46#ibcon#read 5, iclass 19, count 0 2006.257.13:59:15.46#ibcon#about to read 6, iclass 19, count 0 2006.257.13:59:15.46#ibcon#read 6, iclass 19, count 0 2006.257.13:59:15.46#ibcon#end of sib2, iclass 19, count 0 2006.257.13:59:15.46#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:59:15.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:59:15.46#ibcon#[25=USB\r\n] 2006.257.13:59:15.46#ibcon#*before write, iclass 19, count 0 2006.257.13:59:15.46#ibcon#enter sib2, iclass 19, count 0 2006.257.13:59:15.46#ibcon#flushed, iclass 19, count 0 2006.257.13:59:15.46#ibcon#about to write, iclass 19, count 0 2006.257.13:59:15.46#ibcon#wrote, iclass 19, count 0 2006.257.13:59:15.46#ibcon#about to read 3, iclass 19, count 0 2006.257.13:59:15.49#ibcon#read 3, iclass 19, count 0 2006.257.13:59:15.49#ibcon#about to read 4, iclass 19, count 0 2006.257.13:59:15.49#ibcon#read 4, iclass 19, count 0 2006.257.13:59:15.49#ibcon#about to read 5, iclass 19, count 0 2006.257.13:59:15.49#ibcon#read 5, iclass 19, count 0 2006.257.13:59:15.49#ibcon#about to read 6, iclass 19, count 0 2006.257.13:59:15.49#ibcon#read 6, iclass 19, count 0 2006.257.13:59:15.49#ibcon#end of sib2, iclass 19, count 0 2006.257.13:59:15.49#ibcon#*after write, iclass 19, count 0 2006.257.13:59:15.49#ibcon#*before return 0, iclass 19, count 0 2006.257.13:59:15.49#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:15.49#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:15.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:59:15.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:59:15.49$vck44/valo=5,734.99 2006.257.13:59:15.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.13:59:15.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.13:59:15.49#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:15.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:15.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:15.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:15.49#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:59:15.49#ibcon#first serial, iclass 21, count 0 2006.257.13:59:15.49#ibcon#enter sib2, iclass 21, count 0 2006.257.13:59:15.49#ibcon#flushed, iclass 21, count 0 2006.257.13:59:15.49#ibcon#about to write, iclass 21, count 0 2006.257.13:59:15.49#ibcon#wrote, iclass 21, count 0 2006.257.13:59:15.49#ibcon#about to read 3, iclass 21, count 0 2006.257.13:59:15.51#ibcon#read 3, iclass 21, count 0 2006.257.13:59:15.51#ibcon#about to read 4, iclass 21, count 0 2006.257.13:59:15.51#ibcon#read 4, iclass 21, count 0 2006.257.13:59:15.51#ibcon#about to read 5, iclass 21, count 0 2006.257.13:59:15.51#ibcon#read 5, iclass 21, count 0 2006.257.13:59:15.51#ibcon#about to read 6, iclass 21, count 0 2006.257.13:59:15.51#ibcon#read 6, iclass 21, count 0 2006.257.13:59:15.51#ibcon#end of sib2, iclass 21, count 0 2006.257.13:59:15.51#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:59:15.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:59:15.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.13:59:15.51#ibcon#*before write, iclass 21, count 0 2006.257.13:59:15.51#ibcon#enter sib2, iclass 21, count 0 2006.257.13:59:15.51#ibcon#flushed, iclass 21, count 0 2006.257.13:59:15.51#ibcon#about to write, iclass 21, count 0 2006.257.13:59:15.51#ibcon#wrote, iclass 21, count 0 2006.257.13:59:15.51#ibcon#about to read 3, iclass 21, count 0 2006.257.13:59:15.55#ibcon#read 3, iclass 21, count 0 2006.257.13:59:15.55#ibcon#about to read 4, iclass 21, count 0 2006.257.13:59:15.55#ibcon#read 4, iclass 21, count 0 2006.257.13:59:15.55#ibcon#about to read 5, iclass 21, count 0 2006.257.13:59:15.55#ibcon#read 5, iclass 21, count 0 2006.257.13:59:15.55#ibcon#about to read 6, iclass 21, count 0 2006.257.13:59:15.55#ibcon#read 6, iclass 21, count 0 2006.257.13:59:15.55#ibcon#end of sib2, iclass 21, count 0 2006.257.13:59:15.55#ibcon#*after write, iclass 21, count 0 2006.257.13:59:15.55#ibcon#*before return 0, iclass 21, count 0 2006.257.13:59:15.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:15.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:15.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:59:15.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:59:15.55$vck44/va=5,4 2006.257.13:59:15.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.13:59:15.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.13:59:15.55#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:15.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:15.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:15.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:15.61#ibcon#enter wrdev, iclass 23, count 2 2006.257.13:59:15.61#ibcon#first serial, iclass 23, count 2 2006.257.13:59:15.61#ibcon#enter sib2, iclass 23, count 2 2006.257.13:59:15.61#ibcon#flushed, iclass 23, count 2 2006.257.13:59:15.61#ibcon#about to write, iclass 23, count 2 2006.257.13:59:15.61#ibcon#wrote, iclass 23, count 2 2006.257.13:59:15.61#ibcon#about to read 3, iclass 23, count 2 2006.257.13:59:15.63#ibcon#read 3, iclass 23, count 2 2006.257.13:59:15.63#ibcon#about to read 4, iclass 23, count 2 2006.257.13:59:15.63#ibcon#read 4, iclass 23, count 2 2006.257.13:59:15.63#ibcon#about to read 5, iclass 23, count 2 2006.257.13:59:15.63#ibcon#read 5, iclass 23, count 2 2006.257.13:59:15.63#ibcon#about to read 6, iclass 23, count 2 2006.257.13:59:15.63#ibcon#read 6, iclass 23, count 2 2006.257.13:59:15.63#ibcon#end of sib2, iclass 23, count 2 2006.257.13:59:15.63#ibcon#*mode == 0, iclass 23, count 2 2006.257.13:59:15.63#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.13:59:15.63#ibcon#[25=AT05-04\r\n] 2006.257.13:59:15.63#ibcon#*before write, iclass 23, count 2 2006.257.13:59:15.63#ibcon#enter sib2, iclass 23, count 2 2006.257.13:59:15.63#ibcon#flushed, iclass 23, count 2 2006.257.13:59:15.63#ibcon#about to write, iclass 23, count 2 2006.257.13:59:15.63#ibcon#wrote, iclass 23, count 2 2006.257.13:59:15.63#ibcon#about to read 3, iclass 23, count 2 2006.257.13:59:15.66#ibcon#read 3, iclass 23, count 2 2006.257.13:59:15.66#ibcon#about to read 4, iclass 23, count 2 2006.257.13:59:15.66#ibcon#read 4, iclass 23, count 2 2006.257.13:59:15.66#ibcon#about to read 5, iclass 23, count 2 2006.257.13:59:15.66#ibcon#read 5, iclass 23, count 2 2006.257.13:59:15.66#ibcon#about to read 6, iclass 23, count 2 2006.257.13:59:15.66#ibcon#read 6, iclass 23, count 2 2006.257.13:59:15.66#ibcon#end of sib2, iclass 23, count 2 2006.257.13:59:15.66#ibcon#*after write, iclass 23, count 2 2006.257.13:59:15.66#ibcon#*before return 0, iclass 23, count 2 2006.257.13:59:15.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:15.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:15.66#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.13:59:15.66#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:15.66#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:15.78#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:15.78#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:15.78#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:59:15.78#ibcon#first serial, iclass 23, count 0 2006.257.13:59:15.78#ibcon#enter sib2, iclass 23, count 0 2006.257.13:59:15.78#ibcon#flushed, iclass 23, count 0 2006.257.13:59:15.78#ibcon#about to write, iclass 23, count 0 2006.257.13:59:15.78#ibcon#wrote, iclass 23, count 0 2006.257.13:59:15.78#ibcon#about to read 3, iclass 23, count 0 2006.257.13:59:15.80#ibcon#read 3, iclass 23, count 0 2006.257.13:59:15.80#ibcon#about to read 4, iclass 23, count 0 2006.257.13:59:15.80#ibcon#read 4, iclass 23, count 0 2006.257.13:59:15.80#ibcon#about to read 5, iclass 23, count 0 2006.257.13:59:15.80#ibcon#read 5, iclass 23, count 0 2006.257.13:59:15.80#ibcon#about to read 6, iclass 23, count 0 2006.257.13:59:15.80#ibcon#read 6, iclass 23, count 0 2006.257.13:59:15.80#ibcon#end of sib2, iclass 23, count 0 2006.257.13:59:15.80#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:59:15.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:59:15.80#ibcon#[25=USB\r\n] 2006.257.13:59:15.80#ibcon#*before write, iclass 23, count 0 2006.257.13:59:15.80#ibcon#enter sib2, iclass 23, count 0 2006.257.13:59:15.80#ibcon#flushed, iclass 23, count 0 2006.257.13:59:15.80#ibcon#about to write, iclass 23, count 0 2006.257.13:59:15.80#ibcon#wrote, iclass 23, count 0 2006.257.13:59:15.80#ibcon#about to read 3, iclass 23, count 0 2006.257.13:59:15.83#ibcon#read 3, iclass 23, count 0 2006.257.13:59:15.83#ibcon#about to read 4, iclass 23, count 0 2006.257.13:59:15.83#ibcon#read 4, iclass 23, count 0 2006.257.13:59:15.83#ibcon#about to read 5, iclass 23, count 0 2006.257.13:59:15.83#ibcon#read 5, iclass 23, count 0 2006.257.13:59:15.83#ibcon#about to read 6, iclass 23, count 0 2006.257.13:59:15.83#ibcon#read 6, iclass 23, count 0 2006.257.13:59:15.83#ibcon#end of sib2, iclass 23, count 0 2006.257.13:59:15.83#ibcon#*after write, iclass 23, count 0 2006.257.13:59:15.83#ibcon#*before return 0, iclass 23, count 0 2006.257.13:59:15.83#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:15.83#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:15.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:59:15.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:59:15.83$vck44/valo=6,814.99 2006.257.13:59:15.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.13:59:15.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.13:59:15.83#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:15.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:59:15.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:59:15.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:59:15.83#ibcon#enter wrdev, iclass 26, count 0 2006.257.13:59:15.83#ibcon#first serial, iclass 26, count 0 2006.257.13:59:15.83#ibcon#enter sib2, iclass 26, count 0 2006.257.13:59:15.83#ibcon#flushed, iclass 26, count 0 2006.257.13:59:15.83#ibcon#about to write, iclass 26, count 0 2006.257.13:59:15.83#ibcon#wrote, iclass 26, count 0 2006.257.13:59:15.83#ibcon#about to read 3, iclass 26, count 0 2006.257.13:59:15.85#ibcon#read 3, iclass 26, count 0 2006.257.13:59:15.85#ibcon#about to read 4, iclass 26, count 0 2006.257.13:59:15.85#ibcon#read 4, iclass 26, count 0 2006.257.13:59:15.85#ibcon#about to read 5, iclass 26, count 0 2006.257.13:59:15.85#ibcon#read 5, iclass 26, count 0 2006.257.13:59:15.85#ibcon#about to read 6, iclass 26, count 0 2006.257.13:59:15.85#ibcon#read 6, iclass 26, count 0 2006.257.13:59:15.85#ibcon#end of sib2, iclass 26, count 0 2006.257.13:59:15.85#ibcon#*mode == 0, iclass 26, count 0 2006.257.13:59:15.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.13:59:15.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.13:59:15.85#ibcon#*before write, iclass 26, count 0 2006.257.13:59:15.85#ibcon#enter sib2, iclass 26, count 0 2006.257.13:59:15.85#ibcon#flushed, iclass 26, count 0 2006.257.13:59:15.85#ibcon#about to write, iclass 26, count 0 2006.257.13:59:15.85#ibcon#wrote, iclass 26, count 0 2006.257.13:59:15.85#ibcon#about to read 3, iclass 26, count 0 2006.257.13:59:15.85#abcon#<5=/14 1.4 4.3 17.58 971013.9\r\n> 2006.257.13:59:15.87#abcon#{5=INTERFACE CLEAR} 2006.257.13:59:15.89#ibcon#read 3, iclass 26, count 0 2006.257.13:59:15.89#ibcon#about to read 4, iclass 26, count 0 2006.257.13:59:15.89#ibcon#read 4, iclass 26, count 0 2006.257.13:59:15.89#ibcon#about to read 5, iclass 26, count 0 2006.257.13:59:15.89#ibcon#read 5, iclass 26, count 0 2006.257.13:59:15.89#ibcon#about to read 6, iclass 26, count 0 2006.257.13:59:15.89#ibcon#read 6, iclass 26, count 0 2006.257.13:59:15.89#ibcon#end of sib2, iclass 26, count 0 2006.257.13:59:15.89#ibcon#*after write, iclass 26, count 0 2006.257.13:59:15.89#ibcon#*before return 0, iclass 26, count 0 2006.257.13:59:15.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:59:15.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.13:59:15.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.13:59:15.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.13:59:15.89$vck44/va=6,4 2006.257.13:59:15.89#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.13:59:15.89#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.13:59:15.89#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:15.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:59:15.93#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:59:15.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:59:15.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:59:15.95#ibcon#enter wrdev, iclass 30, count 2 2006.257.13:59:15.95#ibcon#first serial, iclass 30, count 2 2006.257.13:59:15.95#ibcon#enter sib2, iclass 30, count 2 2006.257.13:59:15.95#ibcon#flushed, iclass 30, count 2 2006.257.13:59:15.95#ibcon#about to write, iclass 30, count 2 2006.257.13:59:15.95#ibcon#wrote, iclass 30, count 2 2006.257.13:59:15.95#ibcon#about to read 3, iclass 30, count 2 2006.257.13:59:15.97#ibcon#read 3, iclass 30, count 2 2006.257.13:59:15.97#ibcon#about to read 4, iclass 30, count 2 2006.257.13:59:15.97#ibcon#read 4, iclass 30, count 2 2006.257.13:59:15.97#ibcon#about to read 5, iclass 30, count 2 2006.257.13:59:15.97#ibcon#read 5, iclass 30, count 2 2006.257.13:59:15.97#ibcon#about to read 6, iclass 30, count 2 2006.257.13:59:15.97#ibcon#read 6, iclass 30, count 2 2006.257.13:59:15.97#ibcon#end of sib2, iclass 30, count 2 2006.257.13:59:15.97#ibcon#*mode == 0, iclass 30, count 2 2006.257.13:59:15.97#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.13:59:15.97#ibcon#[25=AT06-04\r\n] 2006.257.13:59:15.97#ibcon#*before write, iclass 30, count 2 2006.257.13:59:15.97#ibcon#enter sib2, iclass 30, count 2 2006.257.13:59:15.97#ibcon#flushed, iclass 30, count 2 2006.257.13:59:15.97#ibcon#about to write, iclass 30, count 2 2006.257.13:59:15.97#ibcon#wrote, iclass 30, count 2 2006.257.13:59:15.97#ibcon#about to read 3, iclass 30, count 2 2006.257.13:59:16.00#ibcon#read 3, iclass 30, count 2 2006.257.13:59:16.00#ibcon#about to read 4, iclass 30, count 2 2006.257.13:59:16.00#ibcon#read 4, iclass 30, count 2 2006.257.13:59:16.00#ibcon#about to read 5, iclass 30, count 2 2006.257.13:59:16.00#ibcon#read 5, iclass 30, count 2 2006.257.13:59:16.00#ibcon#about to read 6, iclass 30, count 2 2006.257.13:59:16.00#ibcon#read 6, iclass 30, count 2 2006.257.13:59:16.00#ibcon#end of sib2, iclass 30, count 2 2006.257.13:59:16.00#ibcon#*after write, iclass 30, count 2 2006.257.13:59:16.00#ibcon#*before return 0, iclass 30, count 2 2006.257.13:59:16.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:59:16.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.13:59:16.00#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.13:59:16.00#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:16.00#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:59:16.12#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:59:16.12#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:59:16.12#ibcon#enter wrdev, iclass 30, count 0 2006.257.13:59:16.12#ibcon#first serial, iclass 30, count 0 2006.257.13:59:16.12#ibcon#enter sib2, iclass 30, count 0 2006.257.13:59:16.12#ibcon#flushed, iclass 30, count 0 2006.257.13:59:16.12#ibcon#about to write, iclass 30, count 0 2006.257.13:59:16.12#ibcon#wrote, iclass 30, count 0 2006.257.13:59:16.12#ibcon#about to read 3, iclass 30, count 0 2006.257.13:59:16.14#ibcon#read 3, iclass 30, count 0 2006.257.13:59:16.14#ibcon#about to read 4, iclass 30, count 0 2006.257.13:59:16.14#ibcon#read 4, iclass 30, count 0 2006.257.13:59:16.14#ibcon#about to read 5, iclass 30, count 0 2006.257.13:59:16.14#ibcon#read 5, iclass 30, count 0 2006.257.13:59:16.14#ibcon#about to read 6, iclass 30, count 0 2006.257.13:59:16.14#ibcon#read 6, iclass 30, count 0 2006.257.13:59:16.14#ibcon#end of sib2, iclass 30, count 0 2006.257.13:59:16.14#ibcon#*mode == 0, iclass 30, count 0 2006.257.13:59:16.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.13:59:16.14#ibcon#[25=USB\r\n] 2006.257.13:59:16.14#ibcon#*before write, iclass 30, count 0 2006.257.13:59:16.14#ibcon#enter sib2, iclass 30, count 0 2006.257.13:59:16.14#ibcon#flushed, iclass 30, count 0 2006.257.13:59:16.14#ibcon#about to write, iclass 30, count 0 2006.257.13:59:16.14#ibcon#wrote, iclass 30, count 0 2006.257.13:59:16.14#ibcon#about to read 3, iclass 30, count 0 2006.257.13:59:16.17#ibcon#read 3, iclass 30, count 0 2006.257.13:59:16.17#ibcon#about to read 4, iclass 30, count 0 2006.257.13:59:16.17#ibcon#read 4, iclass 30, count 0 2006.257.13:59:16.17#ibcon#about to read 5, iclass 30, count 0 2006.257.13:59:16.17#ibcon#read 5, iclass 30, count 0 2006.257.13:59:16.17#ibcon#about to read 6, iclass 30, count 0 2006.257.13:59:16.17#ibcon#read 6, iclass 30, count 0 2006.257.13:59:16.17#ibcon#end of sib2, iclass 30, count 0 2006.257.13:59:16.17#ibcon#*after write, iclass 30, count 0 2006.257.13:59:16.17#ibcon#*before return 0, iclass 30, count 0 2006.257.13:59:16.17#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:59:16.17#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.13:59:16.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.13:59:16.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.13:59:16.17$vck44/valo=7,864.99 2006.257.13:59:16.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.13:59:16.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.13:59:16.17#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:16.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:16.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:16.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:16.17#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:59:16.17#ibcon#first serial, iclass 33, count 0 2006.257.13:59:16.17#ibcon#enter sib2, iclass 33, count 0 2006.257.13:59:16.17#ibcon#flushed, iclass 33, count 0 2006.257.13:59:16.17#ibcon#about to write, iclass 33, count 0 2006.257.13:59:16.17#ibcon#wrote, iclass 33, count 0 2006.257.13:59:16.17#ibcon#about to read 3, iclass 33, count 0 2006.257.13:59:16.19#ibcon#read 3, iclass 33, count 0 2006.257.13:59:16.19#ibcon#about to read 4, iclass 33, count 0 2006.257.13:59:16.19#ibcon#read 4, iclass 33, count 0 2006.257.13:59:16.19#ibcon#about to read 5, iclass 33, count 0 2006.257.13:59:16.19#ibcon#read 5, iclass 33, count 0 2006.257.13:59:16.19#ibcon#about to read 6, iclass 33, count 0 2006.257.13:59:16.19#ibcon#read 6, iclass 33, count 0 2006.257.13:59:16.19#ibcon#end of sib2, iclass 33, count 0 2006.257.13:59:16.19#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:59:16.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:59:16.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.13:59:16.19#ibcon#*before write, iclass 33, count 0 2006.257.13:59:16.19#ibcon#enter sib2, iclass 33, count 0 2006.257.13:59:16.19#ibcon#flushed, iclass 33, count 0 2006.257.13:59:16.19#ibcon#about to write, iclass 33, count 0 2006.257.13:59:16.19#ibcon#wrote, iclass 33, count 0 2006.257.13:59:16.19#ibcon#about to read 3, iclass 33, count 0 2006.257.13:59:16.23#ibcon#read 3, iclass 33, count 0 2006.257.13:59:16.23#ibcon#about to read 4, iclass 33, count 0 2006.257.13:59:16.23#ibcon#read 4, iclass 33, count 0 2006.257.13:59:16.23#ibcon#about to read 5, iclass 33, count 0 2006.257.13:59:16.23#ibcon#read 5, iclass 33, count 0 2006.257.13:59:16.23#ibcon#about to read 6, iclass 33, count 0 2006.257.13:59:16.23#ibcon#read 6, iclass 33, count 0 2006.257.13:59:16.23#ibcon#end of sib2, iclass 33, count 0 2006.257.13:59:16.23#ibcon#*after write, iclass 33, count 0 2006.257.13:59:16.23#ibcon#*before return 0, iclass 33, count 0 2006.257.13:59:16.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:16.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:16.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:59:16.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:59:16.23$vck44/va=7,4 2006.257.13:59:16.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.13:59:16.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.13:59:16.23#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:16.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:16.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:16.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:16.29#ibcon#enter wrdev, iclass 35, count 2 2006.257.13:59:16.29#ibcon#first serial, iclass 35, count 2 2006.257.13:59:16.29#ibcon#enter sib2, iclass 35, count 2 2006.257.13:59:16.29#ibcon#flushed, iclass 35, count 2 2006.257.13:59:16.29#ibcon#about to write, iclass 35, count 2 2006.257.13:59:16.29#ibcon#wrote, iclass 35, count 2 2006.257.13:59:16.29#ibcon#about to read 3, iclass 35, count 2 2006.257.13:59:16.31#ibcon#read 3, iclass 35, count 2 2006.257.13:59:16.31#ibcon#about to read 4, iclass 35, count 2 2006.257.13:59:16.31#ibcon#read 4, iclass 35, count 2 2006.257.13:59:16.31#ibcon#about to read 5, iclass 35, count 2 2006.257.13:59:16.31#ibcon#read 5, iclass 35, count 2 2006.257.13:59:16.31#ibcon#about to read 6, iclass 35, count 2 2006.257.13:59:16.31#ibcon#read 6, iclass 35, count 2 2006.257.13:59:16.31#ibcon#end of sib2, iclass 35, count 2 2006.257.13:59:16.31#ibcon#*mode == 0, iclass 35, count 2 2006.257.13:59:16.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.13:59:16.31#ibcon#[25=AT07-04\r\n] 2006.257.13:59:16.31#ibcon#*before write, iclass 35, count 2 2006.257.13:59:16.31#ibcon#enter sib2, iclass 35, count 2 2006.257.13:59:16.31#ibcon#flushed, iclass 35, count 2 2006.257.13:59:16.31#ibcon#about to write, iclass 35, count 2 2006.257.13:59:16.31#ibcon#wrote, iclass 35, count 2 2006.257.13:59:16.31#ibcon#about to read 3, iclass 35, count 2 2006.257.13:59:16.34#ibcon#read 3, iclass 35, count 2 2006.257.13:59:16.34#ibcon#about to read 4, iclass 35, count 2 2006.257.13:59:16.34#ibcon#read 4, iclass 35, count 2 2006.257.13:59:16.34#ibcon#about to read 5, iclass 35, count 2 2006.257.13:59:16.34#ibcon#read 5, iclass 35, count 2 2006.257.13:59:16.34#ibcon#about to read 6, iclass 35, count 2 2006.257.13:59:16.34#ibcon#read 6, iclass 35, count 2 2006.257.13:59:16.34#ibcon#end of sib2, iclass 35, count 2 2006.257.13:59:16.34#ibcon#*after write, iclass 35, count 2 2006.257.13:59:16.34#ibcon#*before return 0, iclass 35, count 2 2006.257.13:59:16.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:16.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:16.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.13:59:16.34#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:16.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:16.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:16.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:16.46#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:59:16.46#ibcon#first serial, iclass 35, count 0 2006.257.13:59:16.46#ibcon#enter sib2, iclass 35, count 0 2006.257.13:59:16.46#ibcon#flushed, iclass 35, count 0 2006.257.13:59:16.46#ibcon#about to write, iclass 35, count 0 2006.257.13:59:16.46#ibcon#wrote, iclass 35, count 0 2006.257.13:59:16.46#ibcon#about to read 3, iclass 35, count 0 2006.257.13:59:16.48#ibcon#read 3, iclass 35, count 0 2006.257.13:59:16.48#ibcon#about to read 4, iclass 35, count 0 2006.257.13:59:16.48#ibcon#read 4, iclass 35, count 0 2006.257.13:59:16.48#ibcon#about to read 5, iclass 35, count 0 2006.257.13:59:16.48#ibcon#read 5, iclass 35, count 0 2006.257.13:59:16.48#ibcon#about to read 6, iclass 35, count 0 2006.257.13:59:16.48#ibcon#read 6, iclass 35, count 0 2006.257.13:59:16.48#ibcon#end of sib2, iclass 35, count 0 2006.257.13:59:16.48#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:59:16.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:59:16.48#ibcon#[25=USB\r\n] 2006.257.13:59:16.48#ibcon#*before write, iclass 35, count 0 2006.257.13:59:16.48#ibcon#enter sib2, iclass 35, count 0 2006.257.13:59:16.48#ibcon#flushed, iclass 35, count 0 2006.257.13:59:16.48#ibcon#about to write, iclass 35, count 0 2006.257.13:59:16.48#ibcon#wrote, iclass 35, count 0 2006.257.13:59:16.48#ibcon#about to read 3, iclass 35, count 0 2006.257.13:59:16.51#ibcon#read 3, iclass 35, count 0 2006.257.13:59:16.51#ibcon#about to read 4, iclass 35, count 0 2006.257.13:59:16.51#ibcon#read 4, iclass 35, count 0 2006.257.13:59:16.51#ibcon#about to read 5, iclass 35, count 0 2006.257.13:59:16.51#ibcon#read 5, iclass 35, count 0 2006.257.13:59:16.51#ibcon#about to read 6, iclass 35, count 0 2006.257.13:59:16.51#ibcon#read 6, iclass 35, count 0 2006.257.13:59:16.51#ibcon#end of sib2, iclass 35, count 0 2006.257.13:59:16.51#ibcon#*after write, iclass 35, count 0 2006.257.13:59:16.51#ibcon#*before return 0, iclass 35, count 0 2006.257.13:59:16.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:16.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:16.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:59:16.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:59:16.51$vck44/valo=8,884.99 2006.257.13:59:16.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.13:59:16.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.13:59:16.51#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:16.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:16.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:16.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:16.51#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:59:16.51#ibcon#first serial, iclass 37, count 0 2006.257.13:59:16.51#ibcon#enter sib2, iclass 37, count 0 2006.257.13:59:16.51#ibcon#flushed, iclass 37, count 0 2006.257.13:59:16.51#ibcon#about to write, iclass 37, count 0 2006.257.13:59:16.51#ibcon#wrote, iclass 37, count 0 2006.257.13:59:16.51#ibcon#about to read 3, iclass 37, count 0 2006.257.13:59:16.53#ibcon#read 3, iclass 37, count 0 2006.257.13:59:16.53#ibcon#about to read 4, iclass 37, count 0 2006.257.13:59:16.53#ibcon#read 4, iclass 37, count 0 2006.257.13:59:16.53#ibcon#about to read 5, iclass 37, count 0 2006.257.13:59:16.53#ibcon#read 5, iclass 37, count 0 2006.257.13:59:16.53#ibcon#about to read 6, iclass 37, count 0 2006.257.13:59:16.53#ibcon#read 6, iclass 37, count 0 2006.257.13:59:16.53#ibcon#end of sib2, iclass 37, count 0 2006.257.13:59:16.53#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:59:16.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:59:16.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.13:59:16.53#ibcon#*before write, iclass 37, count 0 2006.257.13:59:16.53#ibcon#enter sib2, iclass 37, count 0 2006.257.13:59:16.53#ibcon#flushed, iclass 37, count 0 2006.257.13:59:16.53#ibcon#about to write, iclass 37, count 0 2006.257.13:59:16.53#ibcon#wrote, iclass 37, count 0 2006.257.13:59:16.53#ibcon#about to read 3, iclass 37, count 0 2006.257.13:59:16.57#ibcon#read 3, iclass 37, count 0 2006.257.13:59:16.57#ibcon#about to read 4, iclass 37, count 0 2006.257.13:59:16.57#ibcon#read 4, iclass 37, count 0 2006.257.13:59:16.57#ibcon#about to read 5, iclass 37, count 0 2006.257.13:59:16.57#ibcon#read 5, iclass 37, count 0 2006.257.13:59:16.57#ibcon#about to read 6, iclass 37, count 0 2006.257.13:59:16.57#ibcon#read 6, iclass 37, count 0 2006.257.13:59:16.57#ibcon#end of sib2, iclass 37, count 0 2006.257.13:59:16.57#ibcon#*after write, iclass 37, count 0 2006.257.13:59:16.57#ibcon#*before return 0, iclass 37, count 0 2006.257.13:59:16.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:16.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:16.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:59:16.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:59:16.57$vck44/va=8,4 2006.257.13:59:16.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.13:59:16.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.13:59:16.57#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:16.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:59:16.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:59:16.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:59:16.63#ibcon#enter wrdev, iclass 39, count 2 2006.257.13:59:16.63#ibcon#first serial, iclass 39, count 2 2006.257.13:59:16.63#ibcon#enter sib2, iclass 39, count 2 2006.257.13:59:16.63#ibcon#flushed, iclass 39, count 2 2006.257.13:59:16.63#ibcon#about to write, iclass 39, count 2 2006.257.13:59:16.63#ibcon#wrote, iclass 39, count 2 2006.257.13:59:16.63#ibcon#about to read 3, iclass 39, count 2 2006.257.13:59:16.65#ibcon#read 3, iclass 39, count 2 2006.257.13:59:16.65#ibcon#about to read 4, iclass 39, count 2 2006.257.13:59:16.65#ibcon#read 4, iclass 39, count 2 2006.257.13:59:16.65#ibcon#about to read 5, iclass 39, count 2 2006.257.13:59:16.65#ibcon#read 5, iclass 39, count 2 2006.257.13:59:16.65#ibcon#about to read 6, iclass 39, count 2 2006.257.13:59:16.65#ibcon#read 6, iclass 39, count 2 2006.257.13:59:16.65#ibcon#end of sib2, iclass 39, count 2 2006.257.13:59:16.65#ibcon#*mode == 0, iclass 39, count 2 2006.257.13:59:16.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.13:59:16.65#ibcon#[25=AT08-04\r\n] 2006.257.13:59:16.65#ibcon#*before write, iclass 39, count 2 2006.257.13:59:16.65#ibcon#enter sib2, iclass 39, count 2 2006.257.13:59:16.65#ibcon#flushed, iclass 39, count 2 2006.257.13:59:16.65#ibcon#about to write, iclass 39, count 2 2006.257.13:59:16.65#ibcon#wrote, iclass 39, count 2 2006.257.13:59:16.65#ibcon#about to read 3, iclass 39, count 2 2006.257.13:59:16.68#ibcon#read 3, iclass 39, count 2 2006.257.13:59:16.68#ibcon#about to read 4, iclass 39, count 2 2006.257.13:59:16.68#ibcon#read 4, iclass 39, count 2 2006.257.13:59:16.68#ibcon#about to read 5, iclass 39, count 2 2006.257.13:59:16.68#ibcon#read 5, iclass 39, count 2 2006.257.13:59:16.68#ibcon#about to read 6, iclass 39, count 2 2006.257.13:59:16.68#ibcon#read 6, iclass 39, count 2 2006.257.13:59:16.68#ibcon#end of sib2, iclass 39, count 2 2006.257.13:59:16.68#ibcon#*after write, iclass 39, count 2 2006.257.13:59:16.68#ibcon#*before return 0, iclass 39, count 2 2006.257.13:59:16.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:59:16.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.13:59:16.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.13:59:16.68#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:16.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:59:16.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:59:16.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:59:16.80#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:59:16.80#ibcon#first serial, iclass 39, count 0 2006.257.13:59:16.80#ibcon#enter sib2, iclass 39, count 0 2006.257.13:59:16.80#ibcon#flushed, iclass 39, count 0 2006.257.13:59:16.80#ibcon#about to write, iclass 39, count 0 2006.257.13:59:16.80#ibcon#wrote, iclass 39, count 0 2006.257.13:59:16.80#ibcon#about to read 3, iclass 39, count 0 2006.257.13:59:16.82#ibcon#read 3, iclass 39, count 0 2006.257.13:59:16.82#ibcon#about to read 4, iclass 39, count 0 2006.257.13:59:16.82#ibcon#read 4, iclass 39, count 0 2006.257.13:59:16.82#ibcon#about to read 5, iclass 39, count 0 2006.257.13:59:16.82#ibcon#read 5, iclass 39, count 0 2006.257.13:59:16.82#ibcon#about to read 6, iclass 39, count 0 2006.257.13:59:16.82#ibcon#read 6, iclass 39, count 0 2006.257.13:59:16.82#ibcon#end of sib2, iclass 39, count 0 2006.257.13:59:16.82#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:59:16.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:59:16.82#ibcon#[25=USB\r\n] 2006.257.13:59:16.82#ibcon#*before write, iclass 39, count 0 2006.257.13:59:16.82#ibcon#enter sib2, iclass 39, count 0 2006.257.13:59:16.82#ibcon#flushed, iclass 39, count 0 2006.257.13:59:16.82#ibcon#about to write, iclass 39, count 0 2006.257.13:59:16.82#ibcon#wrote, iclass 39, count 0 2006.257.13:59:16.82#ibcon#about to read 3, iclass 39, count 0 2006.257.13:59:16.85#ibcon#read 3, iclass 39, count 0 2006.257.13:59:16.85#ibcon#about to read 4, iclass 39, count 0 2006.257.13:59:16.85#ibcon#read 4, iclass 39, count 0 2006.257.13:59:16.85#ibcon#about to read 5, iclass 39, count 0 2006.257.13:59:16.85#ibcon#read 5, iclass 39, count 0 2006.257.13:59:16.85#ibcon#about to read 6, iclass 39, count 0 2006.257.13:59:16.85#ibcon#read 6, iclass 39, count 0 2006.257.13:59:16.85#ibcon#end of sib2, iclass 39, count 0 2006.257.13:59:16.85#ibcon#*after write, iclass 39, count 0 2006.257.13:59:16.85#ibcon#*before return 0, iclass 39, count 0 2006.257.13:59:16.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:59:16.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.13:59:16.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:59:16.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:59:16.85$vck44/vblo=1,629.99 2006.257.13:59:16.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.13:59:16.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.13:59:16.85#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:16.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:16.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:16.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:16.85#ibcon#enter wrdev, iclass 3, count 0 2006.257.13:59:16.85#ibcon#first serial, iclass 3, count 0 2006.257.13:59:16.85#ibcon#enter sib2, iclass 3, count 0 2006.257.13:59:16.85#ibcon#flushed, iclass 3, count 0 2006.257.13:59:16.85#ibcon#about to write, iclass 3, count 0 2006.257.13:59:16.85#ibcon#wrote, iclass 3, count 0 2006.257.13:59:16.85#ibcon#about to read 3, iclass 3, count 0 2006.257.13:59:16.87#ibcon#read 3, iclass 3, count 0 2006.257.13:59:16.87#ibcon#about to read 4, iclass 3, count 0 2006.257.13:59:16.87#ibcon#read 4, iclass 3, count 0 2006.257.13:59:16.87#ibcon#about to read 5, iclass 3, count 0 2006.257.13:59:16.87#ibcon#read 5, iclass 3, count 0 2006.257.13:59:16.87#ibcon#about to read 6, iclass 3, count 0 2006.257.13:59:16.87#ibcon#read 6, iclass 3, count 0 2006.257.13:59:16.87#ibcon#end of sib2, iclass 3, count 0 2006.257.13:59:16.87#ibcon#*mode == 0, iclass 3, count 0 2006.257.13:59:16.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.13:59:16.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.13:59:16.87#ibcon#*before write, iclass 3, count 0 2006.257.13:59:16.87#ibcon#enter sib2, iclass 3, count 0 2006.257.13:59:16.87#ibcon#flushed, iclass 3, count 0 2006.257.13:59:16.87#ibcon#about to write, iclass 3, count 0 2006.257.13:59:16.87#ibcon#wrote, iclass 3, count 0 2006.257.13:59:16.87#ibcon#about to read 3, iclass 3, count 0 2006.257.13:59:16.91#ibcon#read 3, iclass 3, count 0 2006.257.13:59:16.91#ibcon#about to read 4, iclass 3, count 0 2006.257.13:59:16.91#ibcon#read 4, iclass 3, count 0 2006.257.13:59:16.91#ibcon#about to read 5, iclass 3, count 0 2006.257.13:59:16.91#ibcon#read 5, iclass 3, count 0 2006.257.13:59:16.91#ibcon#about to read 6, iclass 3, count 0 2006.257.13:59:16.91#ibcon#read 6, iclass 3, count 0 2006.257.13:59:16.91#ibcon#end of sib2, iclass 3, count 0 2006.257.13:59:16.91#ibcon#*after write, iclass 3, count 0 2006.257.13:59:16.91#ibcon#*before return 0, iclass 3, count 0 2006.257.13:59:16.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:16.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.13:59:16.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.13:59:16.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.13:59:16.91$vck44/vb=1,4 2006.257.13:59:16.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.13:59:16.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.13:59:16.91#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:16.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:16.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:16.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:16.91#ibcon#enter wrdev, iclass 5, count 2 2006.257.13:59:16.91#ibcon#first serial, iclass 5, count 2 2006.257.13:59:16.91#ibcon#enter sib2, iclass 5, count 2 2006.257.13:59:16.91#ibcon#flushed, iclass 5, count 2 2006.257.13:59:16.91#ibcon#about to write, iclass 5, count 2 2006.257.13:59:16.91#ibcon#wrote, iclass 5, count 2 2006.257.13:59:16.91#ibcon#about to read 3, iclass 5, count 2 2006.257.13:59:16.93#ibcon#read 3, iclass 5, count 2 2006.257.13:59:16.93#ibcon#about to read 4, iclass 5, count 2 2006.257.13:59:16.93#ibcon#read 4, iclass 5, count 2 2006.257.13:59:16.93#ibcon#about to read 5, iclass 5, count 2 2006.257.13:59:16.93#ibcon#read 5, iclass 5, count 2 2006.257.13:59:16.93#ibcon#about to read 6, iclass 5, count 2 2006.257.13:59:16.93#ibcon#read 6, iclass 5, count 2 2006.257.13:59:16.93#ibcon#end of sib2, iclass 5, count 2 2006.257.13:59:16.93#ibcon#*mode == 0, iclass 5, count 2 2006.257.13:59:16.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.13:59:16.93#ibcon#[27=AT01-04\r\n] 2006.257.13:59:16.93#ibcon#*before write, iclass 5, count 2 2006.257.13:59:16.93#ibcon#enter sib2, iclass 5, count 2 2006.257.13:59:16.93#ibcon#flushed, iclass 5, count 2 2006.257.13:59:16.93#ibcon#about to write, iclass 5, count 2 2006.257.13:59:16.93#ibcon#wrote, iclass 5, count 2 2006.257.13:59:16.93#ibcon#about to read 3, iclass 5, count 2 2006.257.13:59:16.96#ibcon#read 3, iclass 5, count 2 2006.257.13:59:16.96#ibcon#about to read 4, iclass 5, count 2 2006.257.13:59:16.96#ibcon#read 4, iclass 5, count 2 2006.257.13:59:16.96#ibcon#about to read 5, iclass 5, count 2 2006.257.13:59:16.96#ibcon#read 5, iclass 5, count 2 2006.257.13:59:16.96#ibcon#about to read 6, iclass 5, count 2 2006.257.13:59:16.96#ibcon#read 6, iclass 5, count 2 2006.257.13:59:16.96#ibcon#end of sib2, iclass 5, count 2 2006.257.13:59:16.96#ibcon#*after write, iclass 5, count 2 2006.257.13:59:16.96#ibcon#*before return 0, iclass 5, count 2 2006.257.13:59:16.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:16.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.13:59:16.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.13:59:16.96#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:16.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:17.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:17.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:17.08#ibcon#enter wrdev, iclass 5, count 0 2006.257.13:59:17.08#ibcon#first serial, iclass 5, count 0 2006.257.13:59:17.08#ibcon#enter sib2, iclass 5, count 0 2006.257.13:59:17.08#ibcon#flushed, iclass 5, count 0 2006.257.13:59:17.08#ibcon#about to write, iclass 5, count 0 2006.257.13:59:17.08#ibcon#wrote, iclass 5, count 0 2006.257.13:59:17.08#ibcon#about to read 3, iclass 5, count 0 2006.257.13:59:17.10#ibcon#read 3, iclass 5, count 0 2006.257.13:59:17.10#ibcon#about to read 4, iclass 5, count 0 2006.257.13:59:17.10#ibcon#read 4, iclass 5, count 0 2006.257.13:59:17.10#ibcon#about to read 5, iclass 5, count 0 2006.257.13:59:17.10#ibcon#read 5, iclass 5, count 0 2006.257.13:59:17.10#ibcon#about to read 6, iclass 5, count 0 2006.257.13:59:17.10#ibcon#read 6, iclass 5, count 0 2006.257.13:59:17.10#ibcon#end of sib2, iclass 5, count 0 2006.257.13:59:17.10#ibcon#*mode == 0, iclass 5, count 0 2006.257.13:59:17.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.13:59:17.10#ibcon#[27=USB\r\n] 2006.257.13:59:17.10#ibcon#*before write, iclass 5, count 0 2006.257.13:59:17.10#ibcon#enter sib2, iclass 5, count 0 2006.257.13:59:17.10#ibcon#flushed, iclass 5, count 0 2006.257.13:59:17.10#ibcon#about to write, iclass 5, count 0 2006.257.13:59:17.10#ibcon#wrote, iclass 5, count 0 2006.257.13:59:17.10#ibcon#about to read 3, iclass 5, count 0 2006.257.13:59:17.13#ibcon#read 3, iclass 5, count 0 2006.257.13:59:17.13#ibcon#about to read 4, iclass 5, count 0 2006.257.13:59:17.13#ibcon#read 4, iclass 5, count 0 2006.257.13:59:17.13#ibcon#about to read 5, iclass 5, count 0 2006.257.13:59:17.13#ibcon#read 5, iclass 5, count 0 2006.257.13:59:17.13#ibcon#about to read 6, iclass 5, count 0 2006.257.13:59:17.13#ibcon#read 6, iclass 5, count 0 2006.257.13:59:17.13#ibcon#end of sib2, iclass 5, count 0 2006.257.13:59:17.13#ibcon#*after write, iclass 5, count 0 2006.257.13:59:17.13#ibcon#*before return 0, iclass 5, count 0 2006.257.13:59:17.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:17.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.13:59:17.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.13:59:17.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.13:59:17.13$vck44/vblo=2,634.99 2006.257.13:59:17.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.13:59:17.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.13:59:17.13#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:17.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:17.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:17.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:17.13#ibcon#enter wrdev, iclass 7, count 0 2006.257.13:59:17.13#ibcon#first serial, iclass 7, count 0 2006.257.13:59:17.13#ibcon#enter sib2, iclass 7, count 0 2006.257.13:59:17.13#ibcon#flushed, iclass 7, count 0 2006.257.13:59:17.13#ibcon#about to write, iclass 7, count 0 2006.257.13:59:17.13#ibcon#wrote, iclass 7, count 0 2006.257.13:59:17.13#ibcon#about to read 3, iclass 7, count 0 2006.257.13:59:17.15#ibcon#read 3, iclass 7, count 0 2006.257.13:59:17.15#ibcon#about to read 4, iclass 7, count 0 2006.257.13:59:17.15#ibcon#read 4, iclass 7, count 0 2006.257.13:59:17.15#ibcon#about to read 5, iclass 7, count 0 2006.257.13:59:17.15#ibcon#read 5, iclass 7, count 0 2006.257.13:59:17.15#ibcon#about to read 6, iclass 7, count 0 2006.257.13:59:17.15#ibcon#read 6, iclass 7, count 0 2006.257.13:59:17.15#ibcon#end of sib2, iclass 7, count 0 2006.257.13:59:17.15#ibcon#*mode == 0, iclass 7, count 0 2006.257.13:59:17.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.13:59:17.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.13:59:17.15#ibcon#*before write, iclass 7, count 0 2006.257.13:59:17.15#ibcon#enter sib2, iclass 7, count 0 2006.257.13:59:17.15#ibcon#flushed, iclass 7, count 0 2006.257.13:59:17.15#ibcon#about to write, iclass 7, count 0 2006.257.13:59:17.15#ibcon#wrote, iclass 7, count 0 2006.257.13:59:17.15#ibcon#about to read 3, iclass 7, count 0 2006.257.13:59:17.19#ibcon#read 3, iclass 7, count 0 2006.257.13:59:17.19#ibcon#about to read 4, iclass 7, count 0 2006.257.13:59:17.19#ibcon#read 4, iclass 7, count 0 2006.257.13:59:17.19#ibcon#about to read 5, iclass 7, count 0 2006.257.13:59:17.19#ibcon#read 5, iclass 7, count 0 2006.257.13:59:17.19#ibcon#about to read 6, iclass 7, count 0 2006.257.13:59:17.19#ibcon#read 6, iclass 7, count 0 2006.257.13:59:17.19#ibcon#end of sib2, iclass 7, count 0 2006.257.13:59:17.19#ibcon#*after write, iclass 7, count 0 2006.257.13:59:17.19#ibcon#*before return 0, iclass 7, count 0 2006.257.13:59:17.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:17.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.13:59:17.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.13:59:17.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.13:59:17.19$vck44/vb=2,5 2006.257.13:59:17.19#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.13:59:17.19#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.13:59:17.19#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:17.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:17.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:17.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:17.25#ibcon#enter wrdev, iclass 11, count 2 2006.257.13:59:17.25#ibcon#first serial, iclass 11, count 2 2006.257.13:59:17.25#ibcon#enter sib2, iclass 11, count 2 2006.257.13:59:17.25#ibcon#flushed, iclass 11, count 2 2006.257.13:59:17.25#ibcon#about to write, iclass 11, count 2 2006.257.13:59:17.25#ibcon#wrote, iclass 11, count 2 2006.257.13:59:17.25#ibcon#about to read 3, iclass 11, count 2 2006.257.13:59:17.27#ibcon#read 3, iclass 11, count 2 2006.257.13:59:17.27#ibcon#about to read 4, iclass 11, count 2 2006.257.13:59:17.27#ibcon#read 4, iclass 11, count 2 2006.257.13:59:17.27#ibcon#about to read 5, iclass 11, count 2 2006.257.13:59:17.27#ibcon#read 5, iclass 11, count 2 2006.257.13:59:17.27#ibcon#about to read 6, iclass 11, count 2 2006.257.13:59:17.27#ibcon#read 6, iclass 11, count 2 2006.257.13:59:17.27#ibcon#end of sib2, iclass 11, count 2 2006.257.13:59:17.27#ibcon#*mode == 0, iclass 11, count 2 2006.257.13:59:17.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.13:59:17.27#ibcon#[27=AT02-05\r\n] 2006.257.13:59:17.27#ibcon#*before write, iclass 11, count 2 2006.257.13:59:17.27#ibcon#enter sib2, iclass 11, count 2 2006.257.13:59:17.27#ibcon#flushed, iclass 11, count 2 2006.257.13:59:17.27#ibcon#about to write, iclass 11, count 2 2006.257.13:59:17.27#ibcon#wrote, iclass 11, count 2 2006.257.13:59:17.27#ibcon#about to read 3, iclass 11, count 2 2006.257.13:59:17.30#ibcon#read 3, iclass 11, count 2 2006.257.13:59:17.30#ibcon#about to read 4, iclass 11, count 2 2006.257.13:59:17.30#ibcon#read 4, iclass 11, count 2 2006.257.13:59:17.30#ibcon#about to read 5, iclass 11, count 2 2006.257.13:59:17.30#ibcon#read 5, iclass 11, count 2 2006.257.13:59:17.30#ibcon#about to read 6, iclass 11, count 2 2006.257.13:59:17.30#ibcon#read 6, iclass 11, count 2 2006.257.13:59:17.30#ibcon#end of sib2, iclass 11, count 2 2006.257.13:59:17.30#ibcon#*after write, iclass 11, count 2 2006.257.13:59:17.30#ibcon#*before return 0, iclass 11, count 2 2006.257.13:59:17.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:17.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.13:59:17.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.13:59:17.30#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:17.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:17.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:17.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:17.42#ibcon#enter wrdev, iclass 11, count 0 2006.257.13:59:17.42#ibcon#first serial, iclass 11, count 0 2006.257.13:59:17.42#ibcon#enter sib2, iclass 11, count 0 2006.257.13:59:17.42#ibcon#flushed, iclass 11, count 0 2006.257.13:59:17.42#ibcon#about to write, iclass 11, count 0 2006.257.13:59:17.42#ibcon#wrote, iclass 11, count 0 2006.257.13:59:17.42#ibcon#about to read 3, iclass 11, count 0 2006.257.13:59:17.44#ibcon#read 3, iclass 11, count 0 2006.257.13:59:17.44#ibcon#about to read 4, iclass 11, count 0 2006.257.13:59:17.44#ibcon#read 4, iclass 11, count 0 2006.257.13:59:17.44#ibcon#about to read 5, iclass 11, count 0 2006.257.13:59:17.44#ibcon#read 5, iclass 11, count 0 2006.257.13:59:17.44#ibcon#about to read 6, iclass 11, count 0 2006.257.13:59:17.44#ibcon#read 6, iclass 11, count 0 2006.257.13:59:17.44#ibcon#end of sib2, iclass 11, count 0 2006.257.13:59:17.44#ibcon#*mode == 0, iclass 11, count 0 2006.257.13:59:17.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.13:59:17.44#ibcon#[27=USB\r\n] 2006.257.13:59:17.44#ibcon#*before write, iclass 11, count 0 2006.257.13:59:17.44#ibcon#enter sib2, iclass 11, count 0 2006.257.13:59:17.44#ibcon#flushed, iclass 11, count 0 2006.257.13:59:17.44#ibcon#about to write, iclass 11, count 0 2006.257.13:59:17.44#ibcon#wrote, iclass 11, count 0 2006.257.13:59:17.44#ibcon#about to read 3, iclass 11, count 0 2006.257.13:59:17.47#ibcon#read 3, iclass 11, count 0 2006.257.13:59:17.47#ibcon#about to read 4, iclass 11, count 0 2006.257.13:59:17.47#ibcon#read 4, iclass 11, count 0 2006.257.13:59:17.47#ibcon#about to read 5, iclass 11, count 0 2006.257.13:59:17.47#ibcon#read 5, iclass 11, count 0 2006.257.13:59:17.47#ibcon#about to read 6, iclass 11, count 0 2006.257.13:59:17.47#ibcon#read 6, iclass 11, count 0 2006.257.13:59:17.47#ibcon#end of sib2, iclass 11, count 0 2006.257.13:59:17.47#ibcon#*after write, iclass 11, count 0 2006.257.13:59:17.47#ibcon#*before return 0, iclass 11, count 0 2006.257.13:59:17.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:17.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.13:59:17.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.13:59:17.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.13:59:17.47$vck44/vblo=3,649.99 2006.257.13:59:17.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.13:59:17.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.13:59:17.47#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:17.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:17.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:17.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:17.47#ibcon#enter wrdev, iclass 13, count 0 2006.257.13:59:17.47#ibcon#first serial, iclass 13, count 0 2006.257.13:59:17.47#ibcon#enter sib2, iclass 13, count 0 2006.257.13:59:17.47#ibcon#flushed, iclass 13, count 0 2006.257.13:59:17.47#ibcon#about to write, iclass 13, count 0 2006.257.13:59:17.47#ibcon#wrote, iclass 13, count 0 2006.257.13:59:17.47#ibcon#about to read 3, iclass 13, count 0 2006.257.13:59:17.49#ibcon#read 3, iclass 13, count 0 2006.257.13:59:17.49#ibcon#about to read 4, iclass 13, count 0 2006.257.13:59:17.49#ibcon#read 4, iclass 13, count 0 2006.257.13:59:17.49#ibcon#about to read 5, iclass 13, count 0 2006.257.13:59:17.49#ibcon#read 5, iclass 13, count 0 2006.257.13:59:17.49#ibcon#about to read 6, iclass 13, count 0 2006.257.13:59:17.49#ibcon#read 6, iclass 13, count 0 2006.257.13:59:17.49#ibcon#end of sib2, iclass 13, count 0 2006.257.13:59:17.49#ibcon#*mode == 0, iclass 13, count 0 2006.257.13:59:17.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.13:59:17.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.13:59:17.49#ibcon#*before write, iclass 13, count 0 2006.257.13:59:17.49#ibcon#enter sib2, iclass 13, count 0 2006.257.13:59:17.49#ibcon#flushed, iclass 13, count 0 2006.257.13:59:17.49#ibcon#about to write, iclass 13, count 0 2006.257.13:59:17.49#ibcon#wrote, iclass 13, count 0 2006.257.13:59:17.49#ibcon#about to read 3, iclass 13, count 0 2006.257.13:59:17.53#ibcon#read 3, iclass 13, count 0 2006.257.13:59:17.53#ibcon#about to read 4, iclass 13, count 0 2006.257.13:59:17.53#ibcon#read 4, iclass 13, count 0 2006.257.13:59:17.53#ibcon#about to read 5, iclass 13, count 0 2006.257.13:59:17.53#ibcon#read 5, iclass 13, count 0 2006.257.13:59:17.53#ibcon#about to read 6, iclass 13, count 0 2006.257.13:59:17.53#ibcon#read 6, iclass 13, count 0 2006.257.13:59:17.53#ibcon#end of sib2, iclass 13, count 0 2006.257.13:59:17.53#ibcon#*after write, iclass 13, count 0 2006.257.13:59:17.53#ibcon#*before return 0, iclass 13, count 0 2006.257.13:59:17.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:17.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.13:59:17.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.13:59:17.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.13:59:17.53$vck44/vb=3,4 2006.257.13:59:17.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.13:59:17.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.13:59:17.53#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:17.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:17.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:17.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:17.59#ibcon#enter wrdev, iclass 15, count 2 2006.257.13:59:17.59#ibcon#first serial, iclass 15, count 2 2006.257.13:59:17.59#ibcon#enter sib2, iclass 15, count 2 2006.257.13:59:17.59#ibcon#flushed, iclass 15, count 2 2006.257.13:59:17.59#ibcon#about to write, iclass 15, count 2 2006.257.13:59:17.59#ibcon#wrote, iclass 15, count 2 2006.257.13:59:17.59#ibcon#about to read 3, iclass 15, count 2 2006.257.13:59:17.61#ibcon#read 3, iclass 15, count 2 2006.257.13:59:17.61#ibcon#about to read 4, iclass 15, count 2 2006.257.13:59:17.61#ibcon#read 4, iclass 15, count 2 2006.257.13:59:17.61#ibcon#about to read 5, iclass 15, count 2 2006.257.13:59:17.61#ibcon#read 5, iclass 15, count 2 2006.257.13:59:17.61#ibcon#about to read 6, iclass 15, count 2 2006.257.13:59:17.61#ibcon#read 6, iclass 15, count 2 2006.257.13:59:17.61#ibcon#end of sib2, iclass 15, count 2 2006.257.13:59:17.61#ibcon#*mode == 0, iclass 15, count 2 2006.257.13:59:17.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.13:59:17.61#ibcon#[27=AT03-04\r\n] 2006.257.13:59:17.61#ibcon#*before write, iclass 15, count 2 2006.257.13:59:17.61#ibcon#enter sib2, iclass 15, count 2 2006.257.13:59:17.61#ibcon#flushed, iclass 15, count 2 2006.257.13:59:17.61#ibcon#about to write, iclass 15, count 2 2006.257.13:59:17.61#ibcon#wrote, iclass 15, count 2 2006.257.13:59:17.61#ibcon#about to read 3, iclass 15, count 2 2006.257.13:59:17.64#ibcon#read 3, iclass 15, count 2 2006.257.13:59:17.64#ibcon#about to read 4, iclass 15, count 2 2006.257.13:59:17.64#ibcon#read 4, iclass 15, count 2 2006.257.13:59:17.64#ibcon#about to read 5, iclass 15, count 2 2006.257.13:59:17.64#ibcon#read 5, iclass 15, count 2 2006.257.13:59:17.64#ibcon#about to read 6, iclass 15, count 2 2006.257.13:59:17.64#ibcon#read 6, iclass 15, count 2 2006.257.13:59:17.64#ibcon#end of sib2, iclass 15, count 2 2006.257.13:59:17.64#ibcon#*after write, iclass 15, count 2 2006.257.13:59:17.64#ibcon#*before return 0, iclass 15, count 2 2006.257.13:59:17.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:17.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.13:59:17.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.13:59:17.64#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:17.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:17.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:17.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:17.76#ibcon#enter wrdev, iclass 15, count 0 2006.257.13:59:17.76#ibcon#first serial, iclass 15, count 0 2006.257.13:59:17.76#ibcon#enter sib2, iclass 15, count 0 2006.257.13:59:17.76#ibcon#flushed, iclass 15, count 0 2006.257.13:59:17.76#ibcon#about to write, iclass 15, count 0 2006.257.13:59:17.76#ibcon#wrote, iclass 15, count 0 2006.257.13:59:17.76#ibcon#about to read 3, iclass 15, count 0 2006.257.13:59:17.78#ibcon#read 3, iclass 15, count 0 2006.257.13:59:17.78#ibcon#about to read 4, iclass 15, count 0 2006.257.13:59:17.78#ibcon#read 4, iclass 15, count 0 2006.257.13:59:17.78#ibcon#about to read 5, iclass 15, count 0 2006.257.13:59:17.78#ibcon#read 5, iclass 15, count 0 2006.257.13:59:17.78#ibcon#about to read 6, iclass 15, count 0 2006.257.13:59:17.78#ibcon#read 6, iclass 15, count 0 2006.257.13:59:17.78#ibcon#end of sib2, iclass 15, count 0 2006.257.13:59:17.78#ibcon#*mode == 0, iclass 15, count 0 2006.257.13:59:17.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.13:59:17.78#ibcon#[27=USB\r\n] 2006.257.13:59:17.78#ibcon#*before write, iclass 15, count 0 2006.257.13:59:17.78#ibcon#enter sib2, iclass 15, count 0 2006.257.13:59:17.78#ibcon#flushed, iclass 15, count 0 2006.257.13:59:17.78#ibcon#about to write, iclass 15, count 0 2006.257.13:59:17.78#ibcon#wrote, iclass 15, count 0 2006.257.13:59:17.78#ibcon#about to read 3, iclass 15, count 0 2006.257.13:59:17.81#ibcon#read 3, iclass 15, count 0 2006.257.13:59:17.81#ibcon#about to read 4, iclass 15, count 0 2006.257.13:59:17.81#ibcon#read 4, iclass 15, count 0 2006.257.13:59:17.81#ibcon#about to read 5, iclass 15, count 0 2006.257.13:59:17.81#ibcon#read 5, iclass 15, count 0 2006.257.13:59:17.81#ibcon#about to read 6, iclass 15, count 0 2006.257.13:59:17.81#ibcon#read 6, iclass 15, count 0 2006.257.13:59:17.81#ibcon#end of sib2, iclass 15, count 0 2006.257.13:59:17.81#ibcon#*after write, iclass 15, count 0 2006.257.13:59:17.81#ibcon#*before return 0, iclass 15, count 0 2006.257.13:59:17.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:17.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.13:59:17.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.13:59:17.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.13:59:17.81$vck44/vblo=4,679.99 2006.257.13:59:17.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.13:59:17.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.13:59:17.81#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:17.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:17.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:17.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:17.81#ibcon#enter wrdev, iclass 17, count 0 2006.257.13:59:17.81#ibcon#first serial, iclass 17, count 0 2006.257.13:59:17.81#ibcon#enter sib2, iclass 17, count 0 2006.257.13:59:17.81#ibcon#flushed, iclass 17, count 0 2006.257.13:59:17.81#ibcon#about to write, iclass 17, count 0 2006.257.13:59:17.81#ibcon#wrote, iclass 17, count 0 2006.257.13:59:17.81#ibcon#about to read 3, iclass 17, count 0 2006.257.13:59:17.83#ibcon#read 3, iclass 17, count 0 2006.257.13:59:17.83#ibcon#about to read 4, iclass 17, count 0 2006.257.13:59:17.83#ibcon#read 4, iclass 17, count 0 2006.257.13:59:17.83#ibcon#about to read 5, iclass 17, count 0 2006.257.13:59:17.83#ibcon#read 5, iclass 17, count 0 2006.257.13:59:17.83#ibcon#about to read 6, iclass 17, count 0 2006.257.13:59:17.83#ibcon#read 6, iclass 17, count 0 2006.257.13:59:17.83#ibcon#end of sib2, iclass 17, count 0 2006.257.13:59:17.83#ibcon#*mode == 0, iclass 17, count 0 2006.257.13:59:17.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.13:59:17.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.13:59:17.83#ibcon#*before write, iclass 17, count 0 2006.257.13:59:17.83#ibcon#enter sib2, iclass 17, count 0 2006.257.13:59:17.83#ibcon#flushed, iclass 17, count 0 2006.257.13:59:17.83#ibcon#about to write, iclass 17, count 0 2006.257.13:59:17.83#ibcon#wrote, iclass 17, count 0 2006.257.13:59:17.83#ibcon#about to read 3, iclass 17, count 0 2006.257.13:59:17.87#ibcon#read 3, iclass 17, count 0 2006.257.13:59:17.87#ibcon#about to read 4, iclass 17, count 0 2006.257.13:59:17.87#ibcon#read 4, iclass 17, count 0 2006.257.13:59:17.87#ibcon#about to read 5, iclass 17, count 0 2006.257.13:59:17.87#ibcon#read 5, iclass 17, count 0 2006.257.13:59:17.87#ibcon#about to read 6, iclass 17, count 0 2006.257.13:59:17.87#ibcon#read 6, iclass 17, count 0 2006.257.13:59:17.87#ibcon#end of sib2, iclass 17, count 0 2006.257.13:59:17.87#ibcon#*after write, iclass 17, count 0 2006.257.13:59:17.87#ibcon#*before return 0, iclass 17, count 0 2006.257.13:59:17.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:17.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.13:59:17.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.13:59:17.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.13:59:17.87$vck44/vb=4,5 2006.257.13:59:17.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.13:59:17.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.13:59:17.87#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:17.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:17.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:17.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:17.93#ibcon#enter wrdev, iclass 19, count 2 2006.257.13:59:17.93#ibcon#first serial, iclass 19, count 2 2006.257.13:59:17.93#ibcon#enter sib2, iclass 19, count 2 2006.257.13:59:17.93#ibcon#flushed, iclass 19, count 2 2006.257.13:59:17.93#ibcon#about to write, iclass 19, count 2 2006.257.13:59:17.93#ibcon#wrote, iclass 19, count 2 2006.257.13:59:17.93#ibcon#about to read 3, iclass 19, count 2 2006.257.13:59:17.95#ibcon#read 3, iclass 19, count 2 2006.257.13:59:17.95#ibcon#about to read 4, iclass 19, count 2 2006.257.13:59:17.95#ibcon#read 4, iclass 19, count 2 2006.257.13:59:17.95#ibcon#about to read 5, iclass 19, count 2 2006.257.13:59:17.95#ibcon#read 5, iclass 19, count 2 2006.257.13:59:17.95#ibcon#about to read 6, iclass 19, count 2 2006.257.13:59:17.95#ibcon#read 6, iclass 19, count 2 2006.257.13:59:17.95#ibcon#end of sib2, iclass 19, count 2 2006.257.13:59:17.95#ibcon#*mode == 0, iclass 19, count 2 2006.257.13:59:17.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.13:59:17.95#ibcon#[27=AT04-05\r\n] 2006.257.13:59:17.95#ibcon#*before write, iclass 19, count 2 2006.257.13:59:17.95#ibcon#enter sib2, iclass 19, count 2 2006.257.13:59:17.95#ibcon#flushed, iclass 19, count 2 2006.257.13:59:17.95#ibcon#about to write, iclass 19, count 2 2006.257.13:59:17.95#ibcon#wrote, iclass 19, count 2 2006.257.13:59:17.95#ibcon#about to read 3, iclass 19, count 2 2006.257.13:59:17.98#ibcon#read 3, iclass 19, count 2 2006.257.13:59:17.98#ibcon#about to read 4, iclass 19, count 2 2006.257.13:59:17.98#ibcon#read 4, iclass 19, count 2 2006.257.13:59:17.98#ibcon#about to read 5, iclass 19, count 2 2006.257.13:59:17.98#ibcon#read 5, iclass 19, count 2 2006.257.13:59:17.98#ibcon#about to read 6, iclass 19, count 2 2006.257.13:59:17.98#ibcon#read 6, iclass 19, count 2 2006.257.13:59:17.98#ibcon#end of sib2, iclass 19, count 2 2006.257.13:59:17.98#ibcon#*after write, iclass 19, count 2 2006.257.13:59:17.98#ibcon#*before return 0, iclass 19, count 2 2006.257.13:59:17.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:17.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.13:59:17.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.13:59:17.98#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:17.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:18.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:18.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:18.10#ibcon#enter wrdev, iclass 19, count 0 2006.257.13:59:18.10#ibcon#first serial, iclass 19, count 0 2006.257.13:59:18.10#ibcon#enter sib2, iclass 19, count 0 2006.257.13:59:18.10#ibcon#flushed, iclass 19, count 0 2006.257.13:59:18.10#ibcon#about to write, iclass 19, count 0 2006.257.13:59:18.10#ibcon#wrote, iclass 19, count 0 2006.257.13:59:18.10#ibcon#about to read 3, iclass 19, count 0 2006.257.13:59:18.12#ibcon#read 3, iclass 19, count 0 2006.257.13:59:18.12#ibcon#about to read 4, iclass 19, count 0 2006.257.13:59:18.12#ibcon#read 4, iclass 19, count 0 2006.257.13:59:18.12#ibcon#about to read 5, iclass 19, count 0 2006.257.13:59:18.12#ibcon#read 5, iclass 19, count 0 2006.257.13:59:18.12#ibcon#about to read 6, iclass 19, count 0 2006.257.13:59:18.12#ibcon#read 6, iclass 19, count 0 2006.257.13:59:18.12#ibcon#end of sib2, iclass 19, count 0 2006.257.13:59:18.12#ibcon#*mode == 0, iclass 19, count 0 2006.257.13:59:18.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.13:59:18.12#ibcon#[27=USB\r\n] 2006.257.13:59:18.12#ibcon#*before write, iclass 19, count 0 2006.257.13:59:18.12#ibcon#enter sib2, iclass 19, count 0 2006.257.13:59:18.12#ibcon#flushed, iclass 19, count 0 2006.257.13:59:18.12#ibcon#about to write, iclass 19, count 0 2006.257.13:59:18.12#ibcon#wrote, iclass 19, count 0 2006.257.13:59:18.12#ibcon#about to read 3, iclass 19, count 0 2006.257.13:59:18.15#ibcon#read 3, iclass 19, count 0 2006.257.13:59:18.15#ibcon#about to read 4, iclass 19, count 0 2006.257.13:59:18.15#ibcon#read 4, iclass 19, count 0 2006.257.13:59:18.15#ibcon#about to read 5, iclass 19, count 0 2006.257.13:59:18.15#ibcon#read 5, iclass 19, count 0 2006.257.13:59:18.15#ibcon#about to read 6, iclass 19, count 0 2006.257.13:59:18.15#ibcon#read 6, iclass 19, count 0 2006.257.13:59:18.15#ibcon#end of sib2, iclass 19, count 0 2006.257.13:59:18.15#ibcon#*after write, iclass 19, count 0 2006.257.13:59:18.15#ibcon#*before return 0, iclass 19, count 0 2006.257.13:59:18.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:18.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.13:59:18.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.13:59:18.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.13:59:18.15$vck44/vblo=5,709.99 2006.257.13:59:18.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.13:59:18.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.13:59:18.15#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:18.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:18.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:18.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:18.15#ibcon#enter wrdev, iclass 21, count 0 2006.257.13:59:18.15#ibcon#first serial, iclass 21, count 0 2006.257.13:59:18.15#ibcon#enter sib2, iclass 21, count 0 2006.257.13:59:18.15#ibcon#flushed, iclass 21, count 0 2006.257.13:59:18.15#ibcon#about to write, iclass 21, count 0 2006.257.13:59:18.15#ibcon#wrote, iclass 21, count 0 2006.257.13:59:18.15#ibcon#about to read 3, iclass 21, count 0 2006.257.13:59:18.17#ibcon#read 3, iclass 21, count 0 2006.257.13:59:18.17#ibcon#about to read 4, iclass 21, count 0 2006.257.13:59:18.17#ibcon#read 4, iclass 21, count 0 2006.257.13:59:18.17#ibcon#about to read 5, iclass 21, count 0 2006.257.13:59:18.17#ibcon#read 5, iclass 21, count 0 2006.257.13:59:18.17#ibcon#about to read 6, iclass 21, count 0 2006.257.13:59:18.17#ibcon#read 6, iclass 21, count 0 2006.257.13:59:18.17#ibcon#end of sib2, iclass 21, count 0 2006.257.13:59:18.17#ibcon#*mode == 0, iclass 21, count 0 2006.257.13:59:18.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.13:59:18.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.13:59:18.17#ibcon#*before write, iclass 21, count 0 2006.257.13:59:18.17#ibcon#enter sib2, iclass 21, count 0 2006.257.13:59:18.17#ibcon#flushed, iclass 21, count 0 2006.257.13:59:18.17#ibcon#about to write, iclass 21, count 0 2006.257.13:59:18.17#ibcon#wrote, iclass 21, count 0 2006.257.13:59:18.17#ibcon#about to read 3, iclass 21, count 0 2006.257.13:59:18.21#ibcon#read 3, iclass 21, count 0 2006.257.13:59:18.21#ibcon#about to read 4, iclass 21, count 0 2006.257.13:59:18.21#ibcon#read 4, iclass 21, count 0 2006.257.13:59:18.21#ibcon#about to read 5, iclass 21, count 0 2006.257.13:59:18.21#ibcon#read 5, iclass 21, count 0 2006.257.13:59:18.21#ibcon#about to read 6, iclass 21, count 0 2006.257.13:59:18.21#ibcon#read 6, iclass 21, count 0 2006.257.13:59:18.21#ibcon#end of sib2, iclass 21, count 0 2006.257.13:59:18.21#ibcon#*after write, iclass 21, count 0 2006.257.13:59:18.21#ibcon#*before return 0, iclass 21, count 0 2006.257.13:59:18.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:18.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.13:59:18.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.13:59:18.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.13:59:18.21$vck44/vb=5,4 2006.257.13:59:18.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.13:59:18.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.13:59:18.21#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:18.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:18.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:18.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:18.27#ibcon#enter wrdev, iclass 23, count 2 2006.257.13:59:18.27#ibcon#first serial, iclass 23, count 2 2006.257.13:59:18.27#ibcon#enter sib2, iclass 23, count 2 2006.257.13:59:18.27#ibcon#flushed, iclass 23, count 2 2006.257.13:59:18.27#ibcon#about to write, iclass 23, count 2 2006.257.13:59:18.27#ibcon#wrote, iclass 23, count 2 2006.257.13:59:18.27#ibcon#about to read 3, iclass 23, count 2 2006.257.13:59:18.29#ibcon#read 3, iclass 23, count 2 2006.257.13:59:18.29#ibcon#about to read 4, iclass 23, count 2 2006.257.13:59:18.29#ibcon#read 4, iclass 23, count 2 2006.257.13:59:18.29#ibcon#about to read 5, iclass 23, count 2 2006.257.13:59:18.29#ibcon#read 5, iclass 23, count 2 2006.257.13:59:18.29#ibcon#about to read 6, iclass 23, count 2 2006.257.13:59:18.29#ibcon#read 6, iclass 23, count 2 2006.257.13:59:18.29#ibcon#end of sib2, iclass 23, count 2 2006.257.13:59:18.29#ibcon#*mode == 0, iclass 23, count 2 2006.257.13:59:18.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.13:59:18.29#ibcon#[27=AT05-04\r\n] 2006.257.13:59:18.29#ibcon#*before write, iclass 23, count 2 2006.257.13:59:18.29#ibcon#enter sib2, iclass 23, count 2 2006.257.13:59:18.29#ibcon#flushed, iclass 23, count 2 2006.257.13:59:18.29#ibcon#about to write, iclass 23, count 2 2006.257.13:59:18.29#ibcon#wrote, iclass 23, count 2 2006.257.13:59:18.29#ibcon#about to read 3, iclass 23, count 2 2006.257.13:59:18.32#ibcon#read 3, iclass 23, count 2 2006.257.13:59:18.33#ibcon#about to read 4, iclass 23, count 2 2006.257.13:59:18.33#ibcon#read 4, iclass 23, count 2 2006.257.13:59:18.33#ibcon#about to read 5, iclass 23, count 2 2006.257.13:59:18.33#ibcon#read 5, iclass 23, count 2 2006.257.13:59:18.33#ibcon#about to read 6, iclass 23, count 2 2006.257.13:59:18.33#ibcon#read 6, iclass 23, count 2 2006.257.13:59:18.33#ibcon#end of sib2, iclass 23, count 2 2006.257.13:59:18.33#ibcon#*after write, iclass 23, count 2 2006.257.13:59:18.33#ibcon#*before return 0, iclass 23, count 2 2006.257.13:59:18.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:18.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.13:59:18.33#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.13:59:18.33#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:18.33#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:18.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:18.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:18.44#ibcon#enter wrdev, iclass 23, count 0 2006.257.13:59:18.44#ibcon#first serial, iclass 23, count 0 2006.257.13:59:18.44#ibcon#enter sib2, iclass 23, count 0 2006.257.13:59:18.44#ibcon#flushed, iclass 23, count 0 2006.257.13:59:18.44#ibcon#about to write, iclass 23, count 0 2006.257.13:59:18.44#ibcon#wrote, iclass 23, count 0 2006.257.13:59:18.44#ibcon#about to read 3, iclass 23, count 0 2006.257.13:59:18.46#ibcon#read 3, iclass 23, count 0 2006.257.13:59:18.46#ibcon#about to read 4, iclass 23, count 0 2006.257.13:59:18.46#ibcon#read 4, iclass 23, count 0 2006.257.13:59:18.46#ibcon#about to read 5, iclass 23, count 0 2006.257.13:59:18.46#ibcon#read 5, iclass 23, count 0 2006.257.13:59:18.46#ibcon#about to read 6, iclass 23, count 0 2006.257.13:59:18.46#ibcon#read 6, iclass 23, count 0 2006.257.13:59:18.46#ibcon#end of sib2, iclass 23, count 0 2006.257.13:59:18.46#ibcon#*mode == 0, iclass 23, count 0 2006.257.13:59:18.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.13:59:18.46#ibcon#[27=USB\r\n] 2006.257.13:59:18.46#ibcon#*before write, iclass 23, count 0 2006.257.13:59:18.46#ibcon#enter sib2, iclass 23, count 0 2006.257.13:59:18.46#ibcon#flushed, iclass 23, count 0 2006.257.13:59:18.46#ibcon#about to write, iclass 23, count 0 2006.257.13:59:18.46#ibcon#wrote, iclass 23, count 0 2006.257.13:59:18.46#ibcon#about to read 3, iclass 23, count 0 2006.257.13:59:18.49#ibcon#read 3, iclass 23, count 0 2006.257.13:59:18.49#ibcon#about to read 4, iclass 23, count 0 2006.257.13:59:18.49#ibcon#read 4, iclass 23, count 0 2006.257.13:59:18.49#ibcon#about to read 5, iclass 23, count 0 2006.257.13:59:18.49#ibcon#read 5, iclass 23, count 0 2006.257.13:59:18.49#ibcon#about to read 6, iclass 23, count 0 2006.257.13:59:18.49#ibcon#read 6, iclass 23, count 0 2006.257.13:59:18.49#ibcon#end of sib2, iclass 23, count 0 2006.257.13:59:18.49#ibcon#*after write, iclass 23, count 0 2006.257.13:59:18.49#ibcon#*before return 0, iclass 23, count 0 2006.257.13:59:18.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:18.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.13:59:18.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.13:59:18.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.13:59:18.49$vck44/vblo=6,719.99 2006.257.13:59:18.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.13:59:18.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.13:59:18.49#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:18.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:59:18.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:59:18.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:59:18.49#ibcon#enter wrdev, iclass 25, count 0 2006.257.13:59:18.49#ibcon#first serial, iclass 25, count 0 2006.257.13:59:18.49#ibcon#enter sib2, iclass 25, count 0 2006.257.13:59:18.49#ibcon#flushed, iclass 25, count 0 2006.257.13:59:18.49#ibcon#about to write, iclass 25, count 0 2006.257.13:59:18.49#ibcon#wrote, iclass 25, count 0 2006.257.13:59:18.49#ibcon#about to read 3, iclass 25, count 0 2006.257.13:59:18.51#ibcon#read 3, iclass 25, count 0 2006.257.13:59:18.51#ibcon#about to read 4, iclass 25, count 0 2006.257.13:59:18.51#ibcon#read 4, iclass 25, count 0 2006.257.13:59:18.51#ibcon#about to read 5, iclass 25, count 0 2006.257.13:59:18.51#ibcon#read 5, iclass 25, count 0 2006.257.13:59:18.51#ibcon#about to read 6, iclass 25, count 0 2006.257.13:59:18.51#ibcon#read 6, iclass 25, count 0 2006.257.13:59:18.51#ibcon#end of sib2, iclass 25, count 0 2006.257.13:59:18.51#ibcon#*mode == 0, iclass 25, count 0 2006.257.13:59:18.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.13:59:18.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.13:59:18.51#ibcon#*before write, iclass 25, count 0 2006.257.13:59:18.51#ibcon#enter sib2, iclass 25, count 0 2006.257.13:59:18.51#ibcon#flushed, iclass 25, count 0 2006.257.13:59:18.51#ibcon#about to write, iclass 25, count 0 2006.257.13:59:18.51#ibcon#wrote, iclass 25, count 0 2006.257.13:59:18.51#ibcon#about to read 3, iclass 25, count 0 2006.257.13:59:18.55#ibcon#read 3, iclass 25, count 0 2006.257.13:59:18.55#ibcon#about to read 4, iclass 25, count 0 2006.257.13:59:18.55#ibcon#read 4, iclass 25, count 0 2006.257.13:59:18.55#ibcon#about to read 5, iclass 25, count 0 2006.257.13:59:18.55#ibcon#read 5, iclass 25, count 0 2006.257.13:59:18.55#ibcon#about to read 6, iclass 25, count 0 2006.257.13:59:18.55#ibcon#read 6, iclass 25, count 0 2006.257.13:59:18.55#ibcon#end of sib2, iclass 25, count 0 2006.257.13:59:18.55#ibcon#*after write, iclass 25, count 0 2006.257.13:59:18.55#ibcon#*before return 0, iclass 25, count 0 2006.257.13:59:18.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:59:18.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.13:59:18.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.13:59:18.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.13:59:18.55$vck44/vb=6,4 2006.257.13:59:18.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.13:59:18.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.13:59:18.55#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:18.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:59:18.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:59:18.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:59:18.61#ibcon#enter wrdev, iclass 27, count 2 2006.257.13:59:18.61#ibcon#first serial, iclass 27, count 2 2006.257.13:59:18.61#ibcon#enter sib2, iclass 27, count 2 2006.257.13:59:18.61#ibcon#flushed, iclass 27, count 2 2006.257.13:59:18.61#ibcon#about to write, iclass 27, count 2 2006.257.13:59:18.61#ibcon#wrote, iclass 27, count 2 2006.257.13:59:18.61#ibcon#about to read 3, iclass 27, count 2 2006.257.13:59:18.63#ibcon#read 3, iclass 27, count 2 2006.257.13:59:18.63#ibcon#about to read 4, iclass 27, count 2 2006.257.13:59:18.63#ibcon#read 4, iclass 27, count 2 2006.257.13:59:18.63#ibcon#about to read 5, iclass 27, count 2 2006.257.13:59:18.63#ibcon#read 5, iclass 27, count 2 2006.257.13:59:18.63#ibcon#about to read 6, iclass 27, count 2 2006.257.13:59:18.63#ibcon#read 6, iclass 27, count 2 2006.257.13:59:18.63#ibcon#end of sib2, iclass 27, count 2 2006.257.13:59:18.63#ibcon#*mode == 0, iclass 27, count 2 2006.257.13:59:18.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.13:59:18.63#ibcon#[27=AT06-04\r\n] 2006.257.13:59:18.63#ibcon#*before write, iclass 27, count 2 2006.257.13:59:18.63#ibcon#enter sib2, iclass 27, count 2 2006.257.13:59:18.63#ibcon#flushed, iclass 27, count 2 2006.257.13:59:18.63#ibcon#about to write, iclass 27, count 2 2006.257.13:59:18.63#ibcon#wrote, iclass 27, count 2 2006.257.13:59:18.63#ibcon#about to read 3, iclass 27, count 2 2006.257.13:59:18.66#ibcon#read 3, iclass 27, count 2 2006.257.13:59:18.66#ibcon#about to read 4, iclass 27, count 2 2006.257.13:59:18.66#ibcon#read 4, iclass 27, count 2 2006.257.13:59:18.66#ibcon#about to read 5, iclass 27, count 2 2006.257.13:59:18.66#ibcon#read 5, iclass 27, count 2 2006.257.13:59:18.66#ibcon#about to read 6, iclass 27, count 2 2006.257.13:59:18.66#ibcon#read 6, iclass 27, count 2 2006.257.13:59:18.66#ibcon#end of sib2, iclass 27, count 2 2006.257.13:59:18.66#ibcon#*after write, iclass 27, count 2 2006.257.13:59:18.66#ibcon#*before return 0, iclass 27, count 2 2006.257.13:59:18.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:59:18.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.13:59:18.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.13:59:18.66#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:18.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:59:18.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:59:18.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:59:18.78#ibcon#enter wrdev, iclass 27, count 0 2006.257.13:59:18.78#ibcon#first serial, iclass 27, count 0 2006.257.13:59:18.78#ibcon#enter sib2, iclass 27, count 0 2006.257.13:59:18.78#ibcon#flushed, iclass 27, count 0 2006.257.13:59:18.78#ibcon#about to write, iclass 27, count 0 2006.257.13:59:18.78#ibcon#wrote, iclass 27, count 0 2006.257.13:59:18.78#ibcon#about to read 3, iclass 27, count 0 2006.257.13:59:18.80#ibcon#read 3, iclass 27, count 0 2006.257.13:59:18.80#ibcon#about to read 4, iclass 27, count 0 2006.257.13:59:18.80#ibcon#read 4, iclass 27, count 0 2006.257.13:59:18.80#ibcon#about to read 5, iclass 27, count 0 2006.257.13:59:18.80#ibcon#read 5, iclass 27, count 0 2006.257.13:59:18.80#ibcon#about to read 6, iclass 27, count 0 2006.257.13:59:18.80#ibcon#read 6, iclass 27, count 0 2006.257.13:59:18.80#ibcon#end of sib2, iclass 27, count 0 2006.257.13:59:18.80#ibcon#*mode == 0, iclass 27, count 0 2006.257.13:59:18.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.13:59:18.80#ibcon#[27=USB\r\n] 2006.257.13:59:18.80#ibcon#*before write, iclass 27, count 0 2006.257.13:59:18.80#ibcon#enter sib2, iclass 27, count 0 2006.257.13:59:18.80#ibcon#flushed, iclass 27, count 0 2006.257.13:59:18.80#ibcon#about to write, iclass 27, count 0 2006.257.13:59:18.80#ibcon#wrote, iclass 27, count 0 2006.257.13:59:18.80#ibcon#about to read 3, iclass 27, count 0 2006.257.13:59:18.83#ibcon#read 3, iclass 27, count 0 2006.257.13:59:18.83#ibcon#about to read 4, iclass 27, count 0 2006.257.13:59:18.83#ibcon#read 4, iclass 27, count 0 2006.257.13:59:18.83#ibcon#about to read 5, iclass 27, count 0 2006.257.13:59:18.83#ibcon#read 5, iclass 27, count 0 2006.257.13:59:18.83#ibcon#about to read 6, iclass 27, count 0 2006.257.13:59:18.83#ibcon#read 6, iclass 27, count 0 2006.257.13:59:18.83#ibcon#end of sib2, iclass 27, count 0 2006.257.13:59:18.83#ibcon#*after write, iclass 27, count 0 2006.257.13:59:18.83#ibcon#*before return 0, iclass 27, count 0 2006.257.13:59:18.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:59:18.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.13:59:18.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.13:59:18.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.13:59:18.83$vck44/vblo=7,734.99 2006.257.13:59:18.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.13:59:18.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.13:59:18.83#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:18.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:59:18.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:59:18.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:59:18.83#ibcon#enter wrdev, iclass 29, count 0 2006.257.13:59:18.83#ibcon#first serial, iclass 29, count 0 2006.257.13:59:18.83#ibcon#enter sib2, iclass 29, count 0 2006.257.13:59:18.83#ibcon#flushed, iclass 29, count 0 2006.257.13:59:18.83#ibcon#about to write, iclass 29, count 0 2006.257.13:59:18.83#ibcon#wrote, iclass 29, count 0 2006.257.13:59:18.83#ibcon#about to read 3, iclass 29, count 0 2006.257.13:59:18.85#ibcon#read 3, iclass 29, count 0 2006.257.13:59:18.85#ibcon#about to read 4, iclass 29, count 0 2006.257.13:59:18.85#ibcon#read 4, iclass 29, count 0 2006.257.13:59:18.85#ibcon#about to read 5, iclass 29, count 0 2006.257.13:59:18.85#ibcon#read 5, iclass 29, count 0 2006.257.13:59:18.85#ibcon#about to read 6, iclass 29, count 0 2006.257.13:59:18.85#ibcon#read 6, iclass 29, count 0 2006.257.13:59:18.85#ibcon#end of sib2, iclass 29, count 0 2006.257.13:59:18.85#ibcon#*mode == 0, iclass 29, count 0 2006.257.13:59:18.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.13:59:18.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.13:59:18.85#ibcon#*before write, iclass 29, count 0 2006.257.13:59:18.85#ibcon#enter sib2, iclass 29, count 0 2006.257.13:59:18.85#ibcon#flushed, iclass 29, count 0 2006.257.13:59:18.85#ibcon#about to write, iclass 29, count 0 2006.257.13:59:18.85#ibcon#wrote, iclass 29, count 0 2006.257.13:59:18.85#ibcon#about to read 3, iclass 29, count 0 2006.257.13:59:18.89#ibcon#read 3, iclass 29, count 0 2006.257.13:59:18.89#ibcon#about to read 4, iclass 29, count 0 2006.257.13:59:18.89#ibcon#read 4, iclass 29, count 0 2006.257.13:59:18.89#ibcon#about to read 5, iclass 29, count 0 2006.257.13:59:18.89#ibcon#read 5, iclass 29, count 0 2006.257.13:59:18.89#ibcon#about to read 6, iclass 29, count 0 2006.257.13:59:18.89#ibcon#read 6, iclass 29, count 0 2006.257.13:59:18.89#ibcon#end of sib2, iclass 29, count 0 2006.257.13:59:18.89#ibcon#*after write, iclass 29, count 0 2006.257.13:59:18.89#ibcon#*before return 0, iclass 29, count 0 2006.257.13:59:18.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:59:18.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.13:59:18.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.13:59:18.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.13:59:18.89$vck44/vb=7,4 2006.257.13:59:18.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.13:59:18.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.13:59:18.89#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:18.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:59:18.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:59:18.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:59:18.95#ibcon#enter wrdev, iclass 31, count 2 2006.257.13:59:18.95#ibcon#first serial, iclass 31, count 2 2006.257.13:59:18.95#ibcon#enter sib2, iclass 31, count 2 2006.257.13:59:18.95#ibcon#flushed, iclass 31, count 2 2006.257.13:59:18.95#ibcon#about to write, iclass 31, count 2 2006.257.13:59:18.95#ibcon#wrote, iclass 31, count 2 2006.257.13:59:18.95#ibcon#about to read 3, iclass 31, count 2 2006.257.13:59:18.97#ibcon#read 3, iclass 31, count 2 2006.257.13:59:18.97#ibcon#about to read 4, iclass 31, count 2 2006.257.13:59:18.97#ibcon#read 4, iclass 31, count 2 2006.257.13:59:18.97#ibcon#about to read 5, iclass 31, count 2 2006.257.13:59:18.97#ibcon#read 5, iclass 31, count 2 2006.257.13:59:18.97#ibcon#about to read 6, iclass 31, count 2 2006.257.13:59:18.97#ibcon#read 6, iclass 31, count 2 2006.257.13:59:18.97#ibcon#end of sib2, iclass 31, count 2 2006.257.13:59:18.97#ibcon#*mode == 0, iclass 31, count 2 2006.257.13:59:18.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.13:59:18.97#ibcon#[27=AT07-04\r\n] 2006.257.13:59:18.97#ibcon#*before write, iclass 31, count 2 2006.257.13:59:18.97#ibcon#enter sib2, iclass 31, count 2 2006.257.13:59:18.97#ibcon#flushed, iclass 31, count 2 2006.257.13:59:18.97#ibcon#about to write, iclass 31, count 2 2006.257.13:59:18.97#ibcon#wrote, iclass 31, count 2 2006.257.13:59:18.97#ibcon#about to read 3, iclass 31, count 2 2006.257.13:59:19.00#ibcon#read 3, iclass 31, count 2 2006.257.13:59:19.00#ibcon#about to read 4, iclass 31, count 2 2006.257.13:59:19.00#ibcon#read 4, iclass 31, count 2 2006.257.13:59:19.00#ibcon#about to read 5, iclass 31, count 2 2006.257.13:59:19.00#ibcon#read 5, iclass 31, count 2 2006.257.13:59:19.00#ibcon#about to read 6, iclass 31, count 2 2006.257.13:59:19.00#ibcon#read 6, iclass 31, count 2 2006.257.13:59:19.00#ibcon#end of sib2, iclass 31, count 2 2006.257.13:59:19.00#ibcon#*after write, iclass 31, count 2 2006.257.13:59:19.00#ibcon#*before return 0, iclass 31, count 2 2006.257.13:59:19.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:59:19.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.13:59:19.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.13:59:19.00#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:19.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:59:19.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:59:19.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:59:19.12#ibcon#enter wrdev, iclass 31, count 0 2006.257.13:59:19.12#ibcon#first serial, iclass 31, count 0 2006.257.13:59:19.12#ibcon#enter sib2, iclass 31, count 0 2006.257.13:59:19.12#ibcon#flushed, iclass 31, count 0 2006.257.13:59:19.12#ibcon#about to write, iclass 31, count 0 2006.257.13:59:19.12#ibcon#wrote, iclass 31, count 0 2006.257.13:59:19.12#ibcon#about to read 3, iclass 31, count 0 2006.257.13:59:19.14#ibcon#read 3, iclass 31, count 0 2006.257.13:59:19.14#ibcon#about to read 4, iclass 31, count 0 2006.257.13:59:19.14#ibcon#read 4, iclass 31, count 0 2006.257.13:59:19.14#ibcon#about to read 5, iclass 31, count 0 2006.257.13:59:19.14#ibcon#read 5, iclass 31, count 0 2006.257.13:59:19.14#ibcon#about to read 6, iclass 31, count 0 2006.257.13:59:19.14#ibcon#read 6, iclass 31, count 0 2006.257.13:59:19.14#ibcon#end of sib2, iclass 31, count 0 2006.257.13:59:19.14#ibcon#*mode == 0, iclass 31, count 0 2006.257.13:59:19.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.13:59:19.14#ibcon#[27=USB\r\n] 2006.257.13:59:19.14#ibcon#*before write, iclass 31, count 0 2006.257.13:59:19.14#ibcon#enter sib2, iclass 31, count 0 2006.257.13:59:19.14#ibcon#flushed, iclass 31, count 0 2006.257.13:59:19.14#ibcon#about to write, iclass 31, count 0 2006.257.13:59:19.14#ibcon#wrote, iclass 31, count 0 2006.257.13:59:19.14#ibcon#about to read 3, iclass 31, count 0 2006.257.13:59:19.17#ibcon#read 3, iclass 31, count 0 2006.257.13:59:19.17#ibcon#about to read 4, iclass 31, count 0 2006.257.13:59:19.17#ibcon#read 4, iclass 31, count 0 2006.257.13:59:19.17#ibcon#about to read 5, iclass 31, count 0 2006.257.13:59:19.17#ibcon#read 5, iclass 31, count 0 2006.257.13:59:19.17#ibcon#about to read 6, iclass 31, count 0 2006.257.13:59:19.17#ibcon#read 6, iclass 31, count 0 2006.257.13:59:19.17#ibcon#end of sib2, iclass 31, count 0 2006.257.13:59:19.17#ibcon#*after write, iclass 31, count 0 2006.257.13:59:19.17#ibcon#*before return 0, iclass 31, count 0 2006.257.13:59:19.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:59:19.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.13:59:19.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.13:59:19.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.13:59:19.17$vck44/vblo=8,744.99 2006.257.13:59:19.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.13:59:19.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.13:59:19.17#ibcon#ireg 17 cls_cnt 0 2006.257.13:59:19.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:19.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:19.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:19.17#ibcon#enter wrdev, iclass 33, count 0 2006.257.13:59:19.17#ibcon#first serial, iclass 33, count 0 2006.257.13:59:19.17#ibcon#enter sib2, iclass 33, count 0 2006.257.13:59:19.17#ibcon#flushed, iclass 33, count 0 2006.257.13:59:19.17#ibcon#about to write, iclass 33, count 0 2006.257.13:59:19.17#ibcon#wrote, iclass 33, count 0 2006.257.13:59:19.17#ibcon#about to read 3, iclass 33, count 0 2006.257.13:59:19.19#ibcon#read 3, iclass 33, count 0 2006.257.13:59:19.19#ibcon#about to read 4, iclass 33, count 0 2006.257.13:59:19.19#ibcon#read 4, iclass 33, count 0 2006.257.13:59:19.19#ibcon#about to read 5, iclass 33, count 0 2006.257.13:59:19.19#ibcon#read 5, iclass 33, count 0 2006.257.13:59:19.19#ibcon#about to read 6, iclass 33, count 0 2006.257.13:59:19.19#ibcon#read 6, iclass 33, count 0 2006.257.13:59:19.19#ibcon#end of sib2, iclass 33, count 0 2006.257.13:59:19.19#ibcon#*mode == 0, iclass 33, count 0 2006.257.13:59:19.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.13:59:19.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.13:59:19.19#ibcon#*before write, iclass 33, count 0 2006.257.13:59:19.19#ibcon#enter sib2, iclass 33, count 0 2006.257.13:59:19.19#ibcon#flushed, iclass 33, count 0 2006.257.13:59:19.19#ibcon#about to write, iclass 33, count 0 2006.257.13:59:19.19#ibcon#wrote, iclass 33, count 0 2006.257.13:59:19.19#ibcon#about to read 3, iclass 33, count 0 2006.257.13:59:19.23#ibcon#read 3, iclass 33, count 0 2006.257.13:59:19.23#ibcon#about to read 4, iclass 33, count 0 2006.257.13:59:19.23#ibcon#read 4, iclass 33, count 0 2006.257.13:59:19.23#ibcon#about to read 5, iclass 33, count 0 2006.257.13:59:19.23#ibcon#read 5, iclass 33, count 0 2006.257.13:59:19.23#ibcon#about to read 6, iclass 33, count 0 2006.257.13:59:19.23#ibcon#read 6, iclass 33, count 0 2006.257.13:59:19.23#ibcon#end of sib2, iclass 33, count 0 2006.257.13:59:19.23#ibcon#*after write, iclass 33, count 0 2006.257.13:59:19.23#ibcon#*before return 0, iclass 33, count 0 2006.257.13:59:19.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:19.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.13:59:19.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.13:59:19.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.13:59:19.23$vck44/vb=8,4 2006.257.13:59:19.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.13:59:19.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.13:59:19.23#ibcon#ireg 11 cls_cnt 2 2006.257.13:59:19.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:19.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:19.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:19.29#ibcon#enter wrdev, iclass 35, count 2 2006.257.13:59:19.29#ibcon#first serial, iclass 35, count 2 2006.257.13:59:19.29#ibcon#enter sib2, iclass 35, count 2 2006.257.13:59:19.29#ibcon#flushed, iclass 35, count 2 2006.257.13:59:19.29#ibcon#about to write, iclass 35, count 2 2006.257.13:59:19.29#ibcon#wrote, iclass 35, count 2 2006.257.13:59:19.29#ibcon#about to read 3, iclass 35, count 2 2006.257.13:59:19.31#ibcon#read 3, iclass 35, count 2 2006.257.13:59:19.31#ibcon#about to read 4, iclass 35, count 2 2006.257.13:59:19.31#ibcon#read 4, iclass 35, count 2 2006.257.13:59:19.31#ibcon#about to read 5, iclass 35, count 2 2006.257.13:59:19.31#ibcon#read 5, iclass 35, count 2 2006.257.13:59:19.31#ibcon#about to read 6, iclass 35, count 2 2006.257.13:59:19.31#ibcon#read 6, iclass 35, count 2 2006.257.13:59:19.31#ibcon#end of sib2, iclass 35, count 2 2006.257.13:59:19.31#ibcon#*mode == 0, iclass 35, count 2 2006.257.13:59:19.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.13:59:19.31#ibcon#[27=AT08-04\r\n] 2006.257.13:59:19.31#ibcon#*before write, iclass 35, count 2 2006.257.13:59:19.31#ibcon#enter sib2, iclass 35, count 2 2006.257.13:59:19.31#ibcon#flushed, iclass 35, count 2 2006.257.13:59:19.31#ibcon#about to write, iclass 35, count 2 2006.257.13:59:19.31#ibcon#wrote, iclass 35, count 2 2006.257.13:59:19.31#ibcon#about to read 3, iclass 35, count 2 2006.257.13:59:19.34#ibcon#read 3, iclass 35, count 2 2006.257.13:59:19.34#ibcon#about to read 4, iclass 35, count 2 2006.257.13:59:19.34#ibcon#read 4, iclass 35, count 2 2006.257.13:59:19.34#ibcon#about to read 5, iclass 35, count 2 2006.257.13:59:19.34#ibcon#read 5, iclass 35, count 2 2006.257.13:59:19.34#ibcon#about to read 6, iclass 35, count 2 2006.257.13:59:19.34#ibcon#read 6, iclass 35, count 2 2006.257.13:59:19.34#ibcon#end of sib2, iclass 35, count 2 2006.257.13:59:19.34#ibcon#*after write, iclass 35, count 2 2006.257.13:59:19.39#ibcon#*before return 0, iclass 35, count 2 2006.257.13:59:19.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:19.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.13:59:19.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.13:59:19.39#ibcon#ireg 7 cls_cnt 0 2006.257.13:59:19.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:19.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:19.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:19.50#ibcon#enter wrdev, iclass 35, count 0 2006.257.13:59:19.50#ibcon#first serial, iclass 35, count 0 2006.257.13:59:19.50#ibcon#enter sib2, iclass 35, count 0 2006.257.13:59:19.50#ibcon#flushed, iclass 35, count 0 2006.257.13:59:19.50#ibcon#about to write, iclass 35, count 0 2006.257.13:59:19.50#ibcon#wrote, iclass 35, count 0 2006.257.13:59:19.50#ibcon#about to read 3, iclass 35, count 0 2006.257.13:59:19.52#ibcon#read 3, iclass 35, count 0 2006.257.13:59:19.52#ibcon#about to read 4, iclass 35, count 0 2006.257.13:59:19.52#ibcon#read 4, iclass 35, count 0 2006.257.13:59:19.52#ibcon#about to read 5, iclass 35, count 0 2006.257.13:59:19.52#ibcon#read 5, iclass 35, count 0 2006.257.13:59:19.52#ibcon#about to read 6, iclass 35, count 0 2006.257.13:59:19.52#ibcon#read 6, iclass 35, count 0 2006.257.13:59:19.52#ibcon#end of sib2, iclass 35, count 0 2006.257.13:59:19.52#ibcon#*mode == 0, iclass 35, count 0 2006.257.13:59:19.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.13:59:19.52#ibcon#[27=USB\r\n] 2006.257.13:59:19.52#ibcon#*before write, iclass 35, count 0 2006.257.13:59:19.52#ibcon#enter sib2, iclass 35, count 0 2006.257.13:59:19.52#ibcon#flushed, iclass 35, count 0 2006.257.13:59:19.52#ibcon#about to write, iclass 35, count 0 2006.257.13:59:19.52#ibcon#wrote, iclass 35, count 0 2006.257.13:59:19.52#ibcon#about to read 3, iclass 35, count 0 2006.257.13:59:19.55#ibcon#read 3, iclass 35, count 0 2006.257.13:59:19.55#ibcon#about to read 4, iclass 35, count 0 2006.257.13:59:19.55#ibcon#read 4, iclass 35, count 0 2006.257.13:59:19.55#ibcon#about to read 5, iclass 35, count 0 2006.257.13:59:19.55#ibcon#read 5, iclass 35, count 0 2006.257.13:59:19.55#ibcon#about to read 6, iclass 35, count 0 2006.257.13:59:19.55#ibcon#read 6, iclass 35, count 0 2006.257.13:59:19.55#ibcon#end of sib2, iclass 35, count 0 2006.257.13:59:19.55#ibcon#*after write, iclass 35, count 0 2006.257.13:59:19.55#ibcon#*before return 0, iclass 35, count 0 2006.257.13:59:19.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:19.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.13:59:19.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.13:59:19.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.13:59:19.55$vck44/vabw=wide 2006.257.13:59:19.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.13:59:19.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.13:59:19.55#ibcon#ireg 8 cls_cnt 0 2006.257.13:59:19.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:19.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:19.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:19.55#ibcon#enter wrdev, iclass 37, count 0 2006.257.13:59:19.55#ibcon#first serial, iclass 37, count 0 2006.257.13:59:19.55#ibcon#enter sib2, iclass 37, count 0 2006.257.13:59:19.55#ibcon#flushed, iclass 37, count 0 2006.257.13:59:19.55#ibcon#about to write, iclass 37, count 0 2006.257.13:59:19.55#ibcon#wrote, iclass 37, count 0 2006.257.13:59:19.55#ibcon#about to read 3, iclass 37, count 0 2006.257.13:59:19.57#ibcon#read 3, iclass 37, count 0 2006.257.13:59:19.57#ibcon#about to read 4, iclass 37, count 0 2006.257.13:59:19.57#ibcon#read 4, iclass 37, count 0 2006.257.13:59:19.57#ibcon#about to read 5, iclass 37, count 0 2006.257.13:59:19.57#ibcon#read 5, iclass 37, count 0 2006.257.13:59:19.57#ibcon#about to read 6, iclass 37, count 0 2006.257.13:59:19.57#ibcon#read 6, iclass 37, count 0 2006.257.13:59:19.57#ibcon#end of sib2, iclass 37, count 0 2006.257.13:59:19.57#ibcon#*mode == 0, iclass 37, count 0 2006.257.13:59:19.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.13:59:19.57#ibcon#[25=BW32\r\n] 2006.257.13:59:19.57#ibcon#*before write, iclass 37, count 0 2006.257.13:59:19.57#ibcon#enter sib2, iclass 37, count 0 2006.257.13:59:19.57#ibcon#flushed, iclass 37, count 0 2006.257.13:59:19.57#ibcon#about to write, iclass 37, count 0 2006.257.13:59:19.57#ibcon#wrote, iclass 37, count 0 2006.257.13:59:19.57#ibcon#about to read 3, iclass 37, count 0 2006.257.13:59:19.60#ibcon#read 3, iclass 37, count 0 2006.257.13:59:19.60#ibcon#about to read 4, iclass 37, count 0 2006.257.13:59:19.60#ibcon#read 4, iclass 37, count 0 2006.257.13:59:19.60#ibcon#about to read 5, iclass 37, count 0 2006.257.13:59:19.60#ibcon#read 5, iclass 37, count 0 2006.257.13:59:19.60#ibcon#about to read 6, iclass 37, count 0 2006.257.13:59:19.60#ibcon#read 6, iclass 37, count 0 2006.257.13:59:19.60#ibcon#end of sib2, iclass 37, count 0 2006.257.13:59:19.60#ibcon#*after write, iclass 37, count 0 2006.257.13:59:19.60#ibcon#*before return 0, iclass 37, count 0 2006.257.13:59:19.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:19.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.13:59:19.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.13:59:19.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.13:59:19.60$vck44/vbbw=wide 2006.257.13:59:19.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.13:59:19.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.13:59:19.60#ibcon#ireg 8 cls_cnt 0 2006.257.13:59:19.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:59:19.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:59:19.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:59:19.67#ibcon#enter wrdev, iclass 39, count 0 2006.257.13:59:19.67#ibcon#first serial, iclass 39, count 0 2006.257.13:59:19.67#ibcon#enter sib2, iclass 39, count 0 2006.257.13:59:19.67#ibcon#flushed, iclass 39, count 0 2006.257.13:59:19.67#ibcon#about to write, iclass 39, count 0 2006.257.13:59:19.67#ibcon#wrote, iclass 39, count 0 2006.257.13:59:19.67#ibcon#about to read 3, iclass 39, count 0 2006.257.13:59:19.69#ibcon#read 3, iclass 39, count 0 2006.257.13:59:19.69#ibcon#about to read 4, iclass 39, count 0 2006.257.13:59:19.69#ibcon#read 4, iclass 39, count 0 2006.257.13:59:19.69#ibcon#about to read 5, iclass 39, count 0 2006.257.13:59:19.69#ibcon#read 5, iclass 39, count 0 2006.257.13:59:19.69#ibcon#about to read 6, iclass 39, count 0 2006.257.13:59:19.69#ibcon#read 6, iclass 39, count 0 2006.257.13:59:19.69#ibcon#end of sib2, iclass 39, count 0 2006.257.13:59:19.69#ibcon#*mode == 0, iclass 39, count 0 2006.257.13:59:19.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.13:59:19.69#ibcon#[27=BW32\r\n] 2006.257.13:59:19.69#ibcon#*before write, iclass 39, count 0 2006.257.13:59:19.69#ibcon#enter sib2, iclass 39, count 0 2006.257.13:59:19.69#ibcon#flushed, iclass 39, count 0 2006.257.13:59:19.69#ibcon#about to write, iclass 39, count 0 2006.257.13:59:19.69#ibcon#wrote, iclass 39, count 0 2006.257.13:59:19.69#ibcon#about to read 3, iclass 39, count 0 2006.257.13:59:19.72#ibcon#read 3, iclass 39, count 0 2006.257.13:59:19.72#ibcon#about to read 4, iclass 39, count 0 2006.257.13:59:19.72#ibcon#read 4, iclass 39, count 0 2006.257.13:59:19.72#ibcon#about to read 5, iclass 39, count 0 2006.257.13:59:19.72#ibcon#read 5, iclass 39, count 0 2006.257.13:59:19.72#ibcon#about to read 6, iclass 39, count 0 2006.257.13:59:19.72#ibcon#read 6, iclass 39, count 0 2006.257.13:59:19.72#ibcon#end of sib2, iclass 39, count 0 2006.257.13:59:19.72#ibcon#*after write, iclass 39, count 0 2006.257.13:59:19.72#ibcon#*before return 0, iclass 39, count 0 2006.257.13:59:19.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:59:19.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.13:59:19.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.13:59:19.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.13:59:19.72$setupk4/ifdk4 2006.257.13:59:19.72$ifdk4/lo= 2006.257.13:59:19.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.13:59:19.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.13:59:19.72$ifdk4/patch= 2006.257.13:59:19.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.13:59:19.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.13:59:19.72$setupk4/!*+20s 2006.257.13:59:26.02#abcon#<5=/14 1.4 4.2 17.58 971014.0\r\n> 2006.257.13:59:26.04#abcon#{5=INTERFACE CLEAR} 2006.257.13:59:26.10#abcon#[5=S1D000X0/0*\r\n] 2006.257.13:59:34.19$setupk4/"tpicd 2006.257.13:59:34.19$setupk4/echo=off 2006.257.13:59:34.19$setupk4/xlog=off 2006.257.13:59:34.19:!2006.257.14:01:53 2006.257.14:00:06.14#trakl#Source acquired 2006.257.14:00:06.14#flagr#flagr/antenna,acquired 2006.257.14:01:53.00:preob 2006.257.14:01:53.14/onsource/TRACKING 2006.257.14:01:53.14:!2006.257.14:02:03 2006.257.14:02:03.00:"tape 2006.257.14:02:03.00:"st=record 2006.257.14:02:03.00:data_valid=on 2006.257.14:02:03.00:midob 2006.257.14:02:03.14/onsource/TRACKING 2006.257.14:02:03.14/wx/17.57,1013.9,97 2006.257.14:02:03.32/cable/+6.4814E-03 2006.257.14:02:04.41/va/01,08,usb,yes,34,37 2006.257.14:02:04.41/va/02,07,usb,yes,37,37 2006.257.14:02:04.41/va/03,08,usb,yes,33,35 2006.257.14:02:04.41/va/04,07,usb,yes,38,40 2006.257.14:02:04.41/va/05,04,usb,yes,34,34 2006.257.14:02:04.41/va/06,04,usb,yes,38,37 2006.257.14:02:04.41/va/07,04,usb,yes,39,39 2006.257.14:02:04.41/va/08,04,usb,yes,32,40 2006.257.14:02:04.64/valo/01,524.99,yes,locked 2006.257.14:02:04.64/valo/02,534.99,yes,locked 2006.257.14:02:04.64/valo/03,564.99,yes,locked 2006.257.14:02:04.64/valo/04,624.99,yes,locked 2006.257.14:02:04.64/valo/05,734.99,yes,locked 2006.257.14:02:04.64/valo/06,814.99,yes,locked 2006.257.14:02:04.64/valo/07,864.99,yes,locked 2006.257.14:02:04.64/valo/08,884.99,yes,locked 2006.257.14:02:05.73/vb/01,04,usb,yes,33,30 2006.257.14:02:05.73/vb/02,05,usb,yes,31,31 2006.257.14:02:05.73/vb/03,04,usb,yes,32,35 2006.257.14:02:05.73/vb/04,05,usb,yes,32,31 2006.257.14:02:05.73/vb/05,04,usb,yes,29,31 2006.257.14:02:05.73/vb/06,04,usb,yes,34,30 2006.257.14:02:05.73/vb/07,04,usb,yes,33,33 2006.257.14:02:05.73/vb/08,04,usb,yes,31,34 2006.257.14:02:05.96/vblo/01,629.99,yes,locked 2006.257.14:02:05.96/vblo/02,634.99,yes,locked 2006.257.14:02:05.96/vblo/03,649.99,yes,locked 2006.257.14:02:05.96/vblo/04,679.99,yes,locked 2006.257.14:02:05.96/vblo/05,709.99,yes,locked 2006.257.14:02:05.96/vblo/06,719.99,yes,locked 2006.257.14:02:05.96/vblo/07,734.99,yes,locked 2006.257.14:02:05.96/vblo/08,744.99,yes,locked 2006.257.14:02:06.11/vabw/8 2006.257.14:02:06.26/vbbw/8 2006.257.14:02:06.46/xfe/off,on,15.2 2006.257.14:02:06.83/ifatt/23,28,28,28 2006.257.14:02:07.07/fmout-gps/S +4.51E-07 2006.257.14:02:07.12:!2006.257.14:03:23 2006.257.14:03:23.01:data_valid=off 2006.257.14:03:23.01:"et 2006.257.14:03:23.01:!+3s 2006.257.14:03:26.02:"tape 2006.257.14:03:26.02:postob 2006.257.14:03:26.08/cable/+6.4805E-03 2006.257.14:03:26.08/wx/17.56,1014.0,97 2006.257.14:03:26.14/fmout-gps/S +4.52E-07 2006.257.14:03:26.14:scan_name=257-1404,jd0609,110 2006.257.14:03:26.14:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.257.14:03:27.13#flagr#flagr/antenna,new-source 2006.257.14:03:27.13:checkk5 2006.257.14:03:27.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:03:27.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:03:28.31/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:03:28.70/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:03:29.09/chk_obsdata//k5ts1/T2571402??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:03:29.49/chk_obsdata//k5ts2/T2571402??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:03:29.88/chk_obsdata//k5ts3/T2571402??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:03:30.28/chk_obsdata//k5ts4/T2571402??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:03:30.99/k5log//k5ts1_log_newline 2006.257.14:03:31.69/k5log//k5ts2_log_newline 2006.257.14:03:32.40/k5log//k5ts3_log_newline 2006.257.14:03:33.13/k5log//k5ts4_log_newline 2006.257.14:03:33.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:03:33.15:setupk4=1 2006.257.14:03:33.15$setupk4/echo=on 2006.257.14:03:33.15$setupk4/pcalon 2006.257.14:03:33.15$pcalon/"no phase cal control is implemented here 2006.257.14:03:33.15$setupk4/"tpicd=stop 2006.257.14:03:33.15$setupk4/"rec=synch_on 2006.257.14:03:33.15$setupk4/"rec_mode=128 2006.257.14:03:33.15$setupk4/!* 2006.257.14:03:33.15$setupk4/recpk4 2006.257.14:03:33.15$recpk4/recpatch= 2006.257.14:03:33.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:03:33.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:03:33.16$setupk4/vck44 2006.257.14:03:33.16$vck44/valo=1,524.99 2006.257.14:03:33.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.14:03:33.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.14:03:33.16#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:33.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:33.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:33.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:33.16#ibcon#enter wrdev, iclass 31, count 0 2006.257.14:03:33.16#ibcon#first serial, iclass 31, count 0 2006.257.14:03:33.16#ibcon#enter sib2, iclass 31, count 0 2006.257.14:03:33.16#ibcon#flushed, iclass 31, count 0 2006.257.14:03:33.16#ibcon#about to write, iclass 31, count 0 2006.257.14:03:33.16#ibcon#wrote, iclass 31, count 0 2006.257.14:03:33.16#ibcon#about to read 3, iclass 31, count 0 2006.257.14:03:33.17#ibcon#read 3, iclass 31, count 0 2006.257.14:03:33.17#ibcon#about to read 4, iclass 31, count 0 2006.257.14:03:33.17#ibcon#read 4, iclass 31, count 0 2006.257.14:03:33.17#ibcon#about to read 5, iclass 31, count 0 2006.257.14:03:33.17#ibcon#read 5, iclass 31, count 0 2006.257.14:03:33.17#ibcon#about to read 6, iclass 31, count 0 2006.257.14:03:33.17#ibcon#read 6, iclass 31, count 0 2006.257.14:03:33.17#ibcon#end of sib2, iclass 31, count 0 2006.257.14:03:33.17#ibcon#*mode == 0, iclass 31, count 0 2006.257.14:03:33.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.14:03:33.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:03:33.17#ibcon#*before write, iclass 31, count 0 2006.257.14:03:33.17#ibcon#enter sib2, iclass 31, count 0 2006.257.14:03:33.17#ibcon#flushed, iclass 31, count 0 2006.257.14:03:33.17#ibcon#about to write, iclass 31, count 0 2006.257.14:03:33.17#ibcon#wrote, iclass 31, count 0 2006.257.14:03:33.17#ibcon#about to read 3, iclass 31, count 0 2006.257.14:03:33.22#ibcon#read 3, iclass 31, count 0 2006.257.14:03:33.22#ibcon#about to read 4, iclass 31, count 0 2006.257.14:03:33.22#ibcon#read 4, iclass 31, count 0 2006.257.14:03:33.22#ibcon#about to read 5, iclass 31, count 0 2006.257.14:03:33.22#ibcon#read 5, iclass 31, count 0 2006.257.14:03:33.22#ibcon#about to read 6, iclass 31, count 0 2006.257.14:03:33.22#ibcon#read 6, iclass 31, count 0 2006.257.14:03:33.22#ibcon#end of sib2, iclass 31, count 0 2006.257.14:03:33.22#ibcon#*after write, iclass 31, count 0 2006.257.14:03:33.22#ibcon#*before return 0, iclass 31, count 0 2006.257.14:03:33.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:33.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:33.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.14:03:33.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.14:03:33.22$vck44/va=1,8 2006.257.14:03:33.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.14:03:33.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.14:03:33.22#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:33.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:33.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:33.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:33.22#ibcon#enter wrdev, iclass 33, count 2 2006.257.14:03:33.22#ibcon#first serial, iclass 33, count 2 2006.257.14:03:33.22#ibcon#enter sib2, iclass 33, count 2 2006.257.14:03:33.22#ibcon#flushed, iclass 33, count 2 2006.257.14:03:33.22#ibcon#about to write, iclass 33, count 2 2006.257.14:03:33.22#ibcon#wrote, iclass 33, count 2 2006.257.14:03:33.22#ibcon#about to read 3, iclass 33, count 2 2006.257.14:03:33.24#ibcon#read 3, iclass 33, count 2 2006.257.14:03:33.24#ibcon#about to read 4, iclass 33, count 2 2006.257.14:03:33.24#ibcon#read 4, iclass 33, count 2 2006.257.14:03:33.24#ibcon#about to read 5, iclass 33, count 2 2006.257.14:03:33.24#ibcon#read 5, iclass 33, count 2 2006.257.14:03:33.24#ibcon#about to read 6, iclass 33, count 2 2006.257.14:03:33.24#ibcon#read 6, iclass 33, count 2 2006.257.14:03:33.24#ibcon#end of sib2, iclass 33, count 2 2006.257.14:03:33.24#ibcon#*mode == 0, iclass 33, count 2 2006.257.14:03:33.24#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.14:03:33.24#ibcon#[25=AT01-08\r\n] 2006.257.14:03:33.24#ibcon#*before write, iclass 33, count 2 2006.257.14:03:33.24#ibcon#enter sib2, iclass 33, count 2 2006.257.14:03:33.24#ibcon#flushed, iclass 33, count 2 2006.257.14:03:33.24#ibcon#about to write, iclass 33, count 2 2006.257.14:03:33.24#ibcon#wrote, iclass 33, count 2 2006.257.14:03:33.24#ibcon#about to read 3, iclass 33, count 2 2006.257.14:03:33.27#ibcon#read 3, iclass 33, count 2 2006.257.14:03:33.27#ibcon#about to read 4, iclass 33, count 2 2006.257.14:03:33.27#ibcon#read 4, iclass 33, count 2 2006.257.14:03:33.27#ibcon#about to read 5, iclass 33, count 2 2006.257.14:03:33.27#ibcon#read 5, iclass 33, count 2 2006.257.14:03:33.27#ibcon#about to read 6, iclass 33, count 2 2006.257.14:03:33.27#ibcon#read 6, iclass 33, count 2 2006.257.14:03:33.27#ibcon#end of sib2, iclass 33, count 2 2006.257.14:03:33.27#ibcon#*after write, iclass 33, count 2 2006.257.14:03:33.27#ibcon#*before return 0, iclass 33, count 2 2006.257.14:03:33.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:33.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:33.27#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.14:03:33.27#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:33.27#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:33.39#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:33.39#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:33.39#ibcon#enter wrdev, iclass 33, count 0 2006.257.14:03:33.39#ibcon#first serial, iclass 33, count 0 2006.257.14:03:33.39#ibcon#enter sib2, iclass 33, count 0 2006.257.14:03:33.39#ibcon#flushed, iclass 33, count 0 2006.257.14:03:33.39#ibcon#about to write, iclass 33, count 0 2006.257.14:03:33.39#ibcon#wrote, iclass 33, count 0 2006.257.14:03:33.39#ibcon#about to read 3, iclass 33, count 0 2006.257.14:03:33.41#ibcon#read 3, iclass 33, count 0 2006.257.14:03:33.41#ibcon#about to read 4, iclass 33, count 0 2006.257.14:03:33.41#ibcon#read 4, iclass 33, count 0 2006.257.14:03:33.41#ibcon#about to read 5, iclass 33, count 0 2006.257.14:03:33.41#ibcon#read 5, iclass 33, count 0 2006.257.14:03:33.41#ibcon#about to read 6, iclass 33, count 0 2006.257.14:03:33.41#ibcon#read 6, iclass 33, count 0 2006.257.14:03:33.41#ibcon#end of sib2, iclass 33, count 0 2006.257.14:03:33.41#ibcon#*mode == 0, iclass 33, count 0 2006.257.14:03:33.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.14:03:33.41#ibcon#[25=USB\r\n] 2006.257.14:03:33.41#ibcon#*before write, iclass 33, count 0 2006.257.14:03:33.41#ibcon#enter sib2, iclass 33, count 0 2006.257.14:03:33.41#ibcon#flushed, iclass 33, count 0 2006.257.14:03:33.41#ibcon#about to write, iclass 33, count 0 2006.257.14:03:33.41#ibcon#wrote, iclass 33, count 0 2006.257.14:03:33.41#ibcon#about to read 3, iclass 33, count 0 2006.257.14:03:33.44#ibcon#read 3, iclass 33, count 0 2006.257.14:03:33.44#ibcon#about to read 4, iclass 33, count 0 2006.257.14:03:33.44#ibcon#read 4, iclass 33, count 0 2006.257.14:03:33.44#ibcon#about to read 5, iclass 33, count 0 2006.257.14:03:33.44#ibcon#read 5, iclass 33, count 0 2006.257.14:03:33.44#ibcon#about to read 6, iclass 33, count 0 2006.257.14:03:33.44#ibcon#read 6, iclass 33, count 0 2006.257.14:03:33.44#ibcon#end of sib2, iclass 33, count 0 2006.257.14:03:33.44#ibcon#*after write, iclass 33, count 0 2006.257.14:03:33.44#ibcon#*before return 0, iclass 33, count 0 2006.257.14:03:33.44#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:33.44#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:33.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.14:03:33.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.14:03:33.44$vck44/valo=2,534.99 2006.257.14:03:33.44#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.14:03:33.44#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.14:03:33.44#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:33.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:33.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:33.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:33.44#ibcon#enter wrdev, iclass 35, count 0 2006.257.14:03:33.44#ibcon#first serial, iclass 35, count 0 2006.257.14:03:33.44#ibcon#enter sib2, iclass 35, count 0 2006.257.14:03:33.44#ibcon#flushed, iclass 35, count 0 2006.257.14:03:33.44#ibcon#about to write, iclass 35, count 0 2006.257.14:03:33.44#ibcon#wrote, iclass 35, count 0 2006.257.14:03:33.44#ibcon#about to read 3, iclass 35, count 0 2006.257.14:03:33.46#ibcon#read 3, iclass 35, count 0 2006.257.14:03:33.46#ibcon#about to read 4, iclass 35, count 0 2006.257.14:03:33.46#ibcon#read 4, iclass 35, count 0 2006.257.14:03:33.46#ibcon#about to read 5, iclass 35, count 0 2006.257.14:03:33.46#ibcon#read 5, iclass 35, count 0 2006.257.14:03:33.46#ibcon#about to read 6, iclass 35, count 0 2006.257.14:03:33.46#ibcon#read 6, iclass 35, count 0 2006.257.14:03:33.46#ibcon#end of sib2, iclass 35, count 0 2006.257.14:03:33.46#ibcon#*mode == 0, iclass 35, count 0 2006.257.14:03:33.46#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.14:03:33.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:03:33.46#ibcon#*before write, iclass 35, count 0 2006.257.14:03:33.46#ibcon#enter sib2, iclass 35, count 0 2006.257.14:03:33.46#ibcon#flushed, iclass 35, count 0 2006.257.14:03:33.46#ibcon#about to write, iclass 35, count 0 2006.257.14:03:33.46#ibcon#wrote, iclass 35, count 0 2006.257.14:03:33.46#ibcon#about to read 3, iclass 35, count 0 2006.257.14:03:33.50#ibcon#read 3, iclass 35, count 0 2006.257.14:03:33.50#ibcon#about to read 4, iclass 35, count 0 2006.257.14:03:33.50#ibcon#read 4, iclass 35, count 0 2006.257.14:03:33.50#ibcon#about to read 5, iclass 35, count 0 2006.257.14:03:33.50#ibcon#read 5, iclass 35, count 0 2006.257.14:03:33.50#ibcon#about to read 6, iclass 35, count 0 2006.257.14:03:33.50#ibcon#read 6, iclass 35, count 0 2006.257.14:03:33.50#ibcon#end of sib2, iclass 35, count 0 2006.257.14:03:33.50#ibcon#*after write, iclass 35, count 0 2006.257.14:03:33.50#ibcon#*before return 0, iclass 35, count 0 2006.257.14:03:33.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:33.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:33.50#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.14:03:33.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.14:03:33.50$vck44/va=2,7 2006.257.14:03:33.50#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.14:03:33.50#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.14:03:33.50#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:33.50#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:33.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:33.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:33.56#ibcon#enter wrdev, iclass 37, count 2 2006.257.14:03:33.56#ibcon#first serial, iclass 37, count 2 2006.257.14:03:33.56#ibcon#enter sib2, iclass 37, count 2 2006.257.14:03:33.56#ibcon#flushed, iclass 37, count 2 2006.257.14:03:33.56#ibcon#about to write, iclass 37, count 2 2006.257.14:03:33.56#ibcon#wrote, iclass 37, count 2 2006.257.14:03:33.56#ibcon#about to read 3, iclass 37, count 2 2006.257.14:03:33.58#ibcon#read 3, iclass 37, count 2 2006.257.14:03:33.58#ibcon#about to read 4, iclass 37, count 2 2006.257.14:03:33.58#ibcon#read 4, iclass 37, count 2 2006.257.14:03:33.58#ibcon#about to read 5, iclass 37, count 2 2006.257.14:03:33.58#ibcon#read 5, iclass 37, count 2 2006.257.14:03:33.58#ibcon#about to read 6, iclass 37, count 2 2006.257.14:03:33.58#ibcon#read 6, iclass 37, count 2 2006.257.14:03:33.58#ibcon#end of sib2, iclass 37, count 2 2006.257.14:03:33.58#ibcon#*mode == 0, iclass 37, count 2 2006.257.14:03:33.58#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.14:03:33.58#ibcon#[25=AT02-07\r\n] 2006.257.14:03:33.58#ibcon#*before write, iclass 37, count 2 2006.257.14:03:33.58#ibcon#enter sib2, iclass 37, count 2 2006.257.14:03:33.58#ibcon#flushed, iclass 37, count 2 2006.257.14:03:33.58#ibcon#about to write, iclass 37, count 2 2006.257.14:03:33.58#ibcon#wrote, iclass 37, count 2 2006.257.14:03:33.58#ibcon#about to read 3, iclass 37, count 2 2006.257.14:03:33.61#ibcon#read 3, iclass 37, count 2 2006.257.14:03:33.61#ibcon#about to read 4, iclass 37, count 2 2006.257.14:03:33.61#ibcon#read 4, iclass 37, count 2 2006.257.14:03:33.61#ibcon#about to read 5, iclass 37, count 2 2006.257.14:03:33.61#ibcon#read 5, iclass 37, count 2 2006.257.14:03:33.61#ibcon#about to read 6, iclass 37, count 2 2006.257.14:03:33.61#ibcon#read 6, iclass 37, count 2 2006.257.14:03:33.61#ibcon#end of sib2, iclass 37, count 2 2006.257.14:03:33.61#ibcon#*after write, iclass 37, count 2 2006.257.14:03:33.61#ibcon#*before return 0, iclass 37, count 2 2006.257.14:03:33.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:33.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:33.61#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.14:03:33.61#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:33.61#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:33.73#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:33.73#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:33.73#ibcon#enter wrdev, iclass 37, count 0 2006.257.14:03:33.73#ibcon#first serial, iclass 37, count 0 2006.257.14:03:33.73#ibcon#enter sib2, iclass 37, count 0 2006.257.14:03:33.73#ibcon#flushed, iclass 37, count 0 2006.257.14:03:33.73#ibcon#about to write, iclass 37, count 0 2006.257.14:03:33.73#ibcon#wrote, iclass 37, count 0 2006.257.14:03:33.73#ibcon#about to read 3, iclass 37, count 0 2006.257.14:03:33.75#ibcon#read 3, iclass 37, count 0 2006.257.14:03:33.75#ibcon#about to read 4, iclass 37, count 0 2006.257.14:03:33.75#ibcon#read 4, iclass 37, count 0 2006.257.14:03:33.75#ibcon#about to read 5, iclass 37, count 0 2006.257.14:03:33.75#ibcon#read 5, iclass 37, count 0 2006.257.14:03:33.75#ibcon#about to read 6, iclass 37, count 0 2006.257.14:03:33.75#ibcon#read 6, iclass 37, count 0 2006.257.14:03:33.75#ibcon#end of sib2, iclass 37, count 0 2006.257.14:03:33.75#ibcon#*mode == 0, iclass 37, count 0 2006.257.14:03:33.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.14:03:33.75#ibcon#[25=USB\r\n] 2006.257.14:03:33.75#ibcon#*before write, iclass 37, count 0 2006.257.14:03:33.75#ibcon#enter sib2, iclass 37, count 0 2006.257.14:03:33.75#ibcon#flushed, iclass 37, count 0 2006.257.14:03:33.75#ibcon#about to write, iclass 37, count 0 2006.257.14:03:33.75#ibcon#wrote, iclass 37, count 0 2006.257.14:03:33.75#ibcon#about to read 3, iclass 37, count 0 2006.257.14:03:33.78#ibcon#read 3, iclass 37, count 0 2006.257.14:03:33.78#ibcon#about to read 4, iclass 37, count 0 2006.257.14:03:33.78#ibcon#read 4, iclass 37, count 0 2006.257.14:03:33.78#ibcon#about to read 5, iclass 37, count 0 2006.257.14:03:33.78#ibcon#read 5, iclass 37, count 0 2006.257.14:03:33.78#ibcon#about to read 6, iclass 37, count 0 2006.257.14:03:33.78#ibcon#read 6, iclass 37, count 0 2006.257.14:03:33.78#ibcon#end of sib2, iclass 37, count 0 2006.257.14:03:33.78#ibcon#*after write, iclass 37, count 0 2006.257.14:03:33.78#ibcon#*before return 0, iclass 37, count 0 2006.257.14:03:33.78#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:33.78#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:33.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.14:03:33.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.14:03:33.78$vck44/valo=3,564.99 2006.257.14:03:33.78#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.14:03:33.78#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.14:03:33.78#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:33.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:33.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:33.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:33.78#ibcon#enter wrdev, iclass 39, count 0 2006.257.14:03:33.78#ibcon#first serial, iclass 39, count 0 2006.257.14:03:33.78#ibcon#enter sib2, iclass 39, count 0 2006.257.14:03:33.78#ibcon#flushed, iclass 39, count 0 2006.257.14:03:33.78#ibcon#about to write, iclass 39, count 0 2006.257.14:03:33.78#ibcon#wrote, iclass 39, count 0 2006.257.14:03:33.78#ibcon#about to read 3, iclass 39, count 0 2006.257.14:03:33.80#ibcon#read 3, iclass 39, count 0 2006.257.14:03:33.80#ibcon#about to read 4, iclass 39, count 0 2006.257.14:03:33.80#ibcon#read 4, iclass 39, count 0 2006.257.14:03:33.80#ibcon#about to read 5, iclass 39, count 0 2006.257.14:03:33.80#ibcon#read 5, iclass 39, count 0 2006.257.14:03:33.80#ibcon#about to read 6, iclass 39, count 0 2006.257.14:03:33.80#ibcon#read 6, iclass 39, count 0 2006.257.14:03:33.80#ibcon#end of sib2, iclass 39, count 0 2006.257.14:03:33.80#ibcon#*mode == 0, iclass 39, count 0 2006.257.14:03:33.80#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.14:03:33.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:03:33.80#ibcon#*before write, iclass 39, count 0 2006.257.14:03:33.80#ibcon#enter sib2, iclass 39, count 0 2006.257.14:03:33.80#ibcon#flushed, iclass 39, count 0 2006.257.14:03:33.80#ibcon#about to write, iclass 39, count 0 2006.257.14:03:33.80#ibcon#wrote, iclass 39, count 0 2006.257.14:03:33.80#ibcon#about to read 3, iclass 39, count 0 2006.257.14:03:33.84#ibcon#read 3, iclass 39, count 0 2006.257.14:03:33.84#ibcon#about to read 4, iclass 39, count 0 2006.257.14:03:33.84#ibcon#read 4, iclass 39, count 0 2006.257.14:03:33.84#ibcon#about to read 5, iclass 39, count 0 2006.257.14:03:33.84#ibcon#read 5, iclass 39, count 0 2006.257.14:03:33.84#ibcon#about to read 6, iclass 39, count 0 2006.257.14:03:33.84#ibcon#read 6, iclass 39, count 0 2006.257.14:03:33.84#ibcon#end of sib2, iclass 39, count 0 2006.257.14:03:33.84#ibcon#*after write, iclass 39, count 0 2006.257.14:03:33.84#ibcon#*before return 0, iclass 39, count 0 2006.257.14:03:33.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:33.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:33.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.14:03:33.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.14:03:33.84$vck44/va=3,8 2006.257.14:03:33.84#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.14:03:33.84#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.14:03:33.84#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:33.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:33.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:33.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:33.90#ibcon#enter wrdev, iclass 3, count 2 2006.257.14:03:33.90#ibcon#first serial, iclass 3, count 2 2006.257.14:03:33.90#ibcon#enter sib2, iclass 3, count 2 2006.257.14:03:33.90#ibcon#flushed, iclass 3, count 2 2006.257.14:03:33.90#ibcon#about to write, iclass 3, count 2 2006.257.14:03:33.90#ibcon#wrote, iclass 3, count 2 2006.257.14:03:33.90#ibcon#about to read 3, iclass 3, count 2 2006.257.14:03:33.92#ibcon#read 3, iclass 3, count 2 2006.257.14:03:33.92#ibcon#about to read 4, iclass 3, count 2 2006.257.14:03:33.92#ibcon#read 4, iclass 3, count 2 2006.257.14:03:33.92#ibcon#about to read 5, iclass 3, count 2 2006.257.14:03:33.92#ibcon#read 5, iclass 3, count 2 2006.257.14:03:33.92#ibcon#about to read 6, iclass 3, count 2 2006.257.14:03:33.92#ibcon#read 6, iclass 3, count 2 2006.257.14:03:33.92#ibcon#end of sib2, iclass 3, count 2 2006.257.14:03:33.92#ibcon#*mode == 0, iclass 3, count 2 2006.257.14:03:33.92#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.14:03:33.92#ibcon#[25=AT03-08\r\n] 2006.257.14:03:33.92#ibcon#*before write, iclass 3, count 2 2006.257.14:03:33.92#ibcon#enter sib2, iclass 3, count 2 2006.257.14:03:33.92#ibcon#flushed, iclass 3, count 2 2006.257.14:03:33.92#ibcon#about to write, iclass 3, count 2 2006.257.14:03:33.92#ibcon#wrote, iclass 3, count 2 2006.257.14:03:33.92#ibcon#about to read 3, iclass 3, count 2 2006.257.14:03:33.95#ibcon#read 3, iclass 3, count 2 2006.257.14:03:33.95#ibcon#about to read 4, iclass 3, count 2 2006.257.14:03:33.95#ibcon#read 4, iclass 3, count 2 2006.257.14:03:33.95#ibcon#about to read 5, iclass 3, count 2 2006.257.14:03:33.95#ibcon#read 5, iclass 3, count 2 2006.257.14:03:33.95#ibcon#about to read 6, iclass 3, count 2 2006.257.14:03:33.95#ibcon#read 6, iclass 3, count 2 2006.257.14:03:33.95#ibcon#end of sib2, iclass 3, count 2 2006.257.14:03:33.95#ibcon#*after write, iclass 3, count 2 2006.257.14:03:33.95#ibcon#*before return 0, iclass 3, count 2 2006.257.14:03:33.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:33.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:33.95#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.14:03:33.95#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:33.95#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:34.07#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:34.07#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:34.07#ibcon#enter wrdev, iclass 3, count 0 2006.257.14:03:34.07#ibcon#first serial, iclass 3, count 0 2006.257.14:03:34.07#ibcon#enter sib2, iclass 3, count 0 2006.257.14:03:34.07#ibcon#flushed, iclass 3, count 0 2006.257.14:03:34.07#ibcon#about to write, iclass 3, count 0 2006.257.14:03:34.07#ibcon#wrote, iclass 3, count 0 2006.257.14:03:34.07#ibcon#about to read 3, iclass 3, count 0 2006.257.14:03:34.09#ibcon#read 3, iclass 3, count 0 2006.257.14:03:34.09#ibcon#about to read 4, iclass 3, count 0 2006.257.14:03:34.09#ibcon#read 4, iclass 3, count 0 2006.257.14:03:34.09#ibcon#about to read 5, iclass 3, count 0 2006.257.14:03:34.09#ibcon#read 5, iclass 3, count 0 2006.257.14:03:34.09#ibcon#about to read 6, iclass 3, count 0 2006.257.14:03:34.09#ibcon#read 6, iclass 3, count 0 2006.257.14:03:34.09#ibcon#end of sib2, iclass 3, count 0 2006.257.14:03:34.09#ibcon#*mode == 0, iclass 3, count 0 2006.257.14:03:34.09#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.14:03:34.09#ibcon#[25=USB\r\n] 2006.257.14:03:34.09#ibcon#*before write, iclass 3, count 0 2006.257.14:03:34.09#ibcon#enter sib2, iclass 3, count 0 2006.257.14:03:34.09#ibcon#flushed, iclass 3, count 0 2006.257.14:03:34.09#ibcon#about to write, iclass 3, count 0 2006.257.14:03:34.09#ibcon#wrote, iclass 3, count 0 2006.257.14:03:34.09#ibcon#about to read 3, iclass 3, count 0 2006.257.14:03:34.12#ibcon#read 3, iclass 3, count 0 2006.257.14:03:34.12#ibcon#about to read 4, iclass 3, count 0 2006.257.14:03:34.12#ibcon#read 4, iclass 3, count 0 2006.257.14:03:34.12#ibcon#about to read 5, iclass 3, count 0 2006.257.14:03:34.12#ibcon#read 5, iclass 3, count 0 2006.257.14:03:34.12#ibcon#about to read 6, iclass 3, count 0 2006.257.14:03:34.12#ibcon#read 6, iclass 3, count 0 2006.257.14:03:34.12#ibcon#end of sib2, iclass 3, count 0 2006.257.14:03:34.12#ibcon#*after write, iclass 3, count 0 2006.257.14:03:34.12#ibcon#*before return 0, iclass 3, count 0 2006.257.14:03:34.12#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:34.12#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:34.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.14:03:34.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.14:03:34.12$vck44/valo=4,624.99 2006.257.14:03:34.12#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.14:03:34.12#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.14:03:34.12#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:34.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:34.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:34.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:34.12#ibcon#enter wrdev, iclass 5, count 0 2006.257.14:03:34.12#ibcon#first serial, iclass 5, count 0 2006.257.14:03:34.12#ibcon#enter sib2, iclass 5, count 0 2006.257.14:03:34.12#ibcon#flushed, iclass 5, count 0 2006.257.14:03:34.12#ibcon#about to write, iclass 5, count 0 2006.257.14:03:34.12#ibcon#wrote, iclass 5, count 0 2006.257.14:03:34.12#ibcon#about to read 3, iclass 5, count 0 2006.257.14:03:34.14#ibcon#read 3, iclass 5, count 0 2006.257.14:03:34.14#ibcon#about to read 4, iclass 5, count 0 2006.257.14:03:34.14#ibcon#read 4, iclass 5, count 0 2006.257.14:03:34.14#ibcon#about to read 5, iclass 5, count 0 2006.257.14:03:34.14#ibcon#read 5, iclass 5, count 0 2006.257.14:03:34.14#ibcon#about to read 6, iclass 5, count 0 2006.257.14:03:34.14#ibcon#read 6, iclass 5, count 0 2006.257.14:03:34.14#ibcon#end of sib2, iclass 5, count 0 2006.257.14:03:34.14#ibcon#*mode == 0, iclass 5, count 0 2006.257.14:03:34.14#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.14:03:34.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:03:34.14#ibcon#*before write, iclass 5, count 0 2006.257.14:03:34.14#ibcon#enter sib2, iclass 5, count 0 2006.257.14:03:34.14#ibcon#flushed, iclass 5, count 0 2006.257.14:03:34.14#ibcon#about to write, iclass 5, count 0 2006.257.14:03:34.14#ibcon#wrote, iclass 5, count 0 2006.257.14:03:34.14#ibcon#about to read 3, iclass 5, count 0 2006.257.14:03:34.18#ibcon#read 3, iclass 5, count 0 2006.257.14:03:34.18#ibcon#about to read 4, iclass 5, count 0 2006.257.14:03:34.18#ibcon#read 4, iclass 5, count 0 2006.257.14:03:34.18#ibcon#about to read 5, iclass 5, count 0 2006.257.14:03:34.18#ibcon#read 5, iclass 5, count 0 2006.257.14:03:34.18#ibcon#about to read 6, iclass 5, count 0 2006.257.14:03:34.18#ibcon#read 6, iclass 5, count 0 2006.257.14:03:34.18#ibcon#end of sib2, iclass 5, count 0 2006.257.14:03:34.18#ibcon#*after write, iclass 5, count 0 2006.257.14:03:34.18#ibcon#*before return 0, iclass 5, count 0 2006.257.14:03:34.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:34.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:34.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.14:03:34.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.14:03:34.18$vck44/va=4,7 2006.257.14:03:34.18#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.14:03:34.18#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.14:03:34.18#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:34.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:34.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:34.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:34.24#ibcon#enter wrdev, iclass 7, count 2 2006.257.14:03:34.24#ibcon#first serial, iclass 7, count 2 2006.257.14:03:34.24#ibcon#enter sib2, iclass 7, count 2 2006.257.14:03:34.24#ibcon#flushed, iclass 7, count 2 2006.257.14:03:34.24#ibcon#about to write, iclass 7, count 2 2006.257.14:03:34.24#ibcon#wrote, iclass 7, count 2 2006.257.14:03:34.24#ibcon#about to read 3, iclass 7, count 2 2006.257.14:03:34.26#ibcon#read 3, iclass 7, count 2 2006.257.14:03:34.26#ibcon#about to read 4, iclass 7, count 2 2006.257.14:03:34.26#ibcon#read 4, iclass 7, count 2 2006.257.14:03:34.26#ibcon#about to read 5, iclass 7, count 2 2006.257.14:03:34.26#ibcon#read 5, iclass 7, count 2 2006.257.14:03:34.26#ibcon#about to read 6, iclass 7, count 2 2006.257.14:03:34.26#ibcon#read 6, iclass 7, count 2 2006.257.14:03:34.26#ibcon#end of sib2, iclass 7, count 2 2006.257.14:03:34.26#ibcon#*mode == 0, iclass 7, count 2 2006.257.14:03:34.26#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.14:03:34.26#ibcon#[25=AT04-07\r\n] 2006.257.14:03:34.26#ibcon#*before write, iclass 7, count 2 2006.257.14:03:34.26#ibcon#enter sib2, iclass 7, count 2 2006.257.14:03:34.26#ibcon#flushed, iclass 7, count 2 2006.257.14:03:34.26#ibcon#about to write, iclass 7, count 2 2006.257.14:03:34.26#ibcon#wrote, iclass 7, count 2 2006.257.14:03:34.26#ibcon#about to read 3, iclass 7, count 2 2006.257.14:03:34.29#ibcon#read 3, iclass 7, count 2 2006.257.14:03:34.29#ibcon#about to read 4, iclass 7, count 2 2006.257.14:03:34.29#ibcon#read 4, iclass 7, count 2 2006.257.14:03:34.29#ibcon#about to read 5, iclass 7, count 2 2006.257.14:03:34.29#ibcon#read 5, iclass 7, count 2 2006.257.14:03:34.29#ibcon#about to read 6, iclass 7, count 2 2006.257.14:03:34.29#ibcon#read 6, iclass 7, count 2 2006.257.14:03:34.29#ibcon#end of sib2, iclass 7, count 2 2006.257.14:03:34.29#ibcon#*after write, iclass 7, count 2 2006.257.14:03:34.29#ibcon#*before return 0, iclass 7, count 2 2006.257.14:03:34.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:34.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:34.29#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.14:03:34.29#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:34.29#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:34.41#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:34.41#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:34.41#ibcon#enter wrdev, iclass 7, count 0 2006.257.14:03:34.41#ibcon#first serial, iclass 7, count 0 2006.257.14:03:34.41#ibcon#enter sib2, iclass 7, count 0 2006.257.14:03:34.41#ibcon#flushed, iclass 7, count 0 2006.257.14:03:34.41#ibcon#about to write, iclass 7, count 0 2006.257.14:03:34.41#ibcon#wrote, iclass 7, count 0 2006.257.14:03:34.41#ibcon#about to read 3, iclass 7, count 0 2006.257.14:03:34.43#ibcon#read 3, iclass 7, count 0 2006.257.14:03:34.43#ibcon#about to read 4, iclass 7, count 0 2006.257.14:03:34.43#ibcon#read 4, iclass 7, count 0 2006.257.14:03:34.43#ibcon#about to read 5, iclass 7, count 0 2006.257.14:03:34.43#ibcon#read 5, iclass 7, count 0 2006.257.14:03:34.43#ibcon#about to read 6, iclass 7, count 0 2006.257.14:03:34.43#ibcon#read 6, iclass 7, count 0 2006.257.14:03:34.43#ibcon#end of sib2, iclass 7, count 0 2006.257.14:03:34.43#ibcon#*mode == 0, iclass 7, count 0 2006.257.14:03:34.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.14:03:34.43#ibcon#[25=USB\r\n] 2006.257.14:03:34.43#ibcon#*before write, iclass 7, count 0 2006.257.14:03:34.43#ibcon#enter sib2, iclass 7, count 0 2006.257.14:03:34.43#ibcon#flushed, iclass 7, count 0 2006.257.14:03:34.43#ibcon#about to write, iclass 7, count 0 2006.257.14:03:34.43#ibcon#wrote, iclass 7, count 0 2006.257.14:03:34.43#ibcon#about to read 3, iclass 7, count 0 2006.257.14:03:34.46#ibcon#read 3, iclass 7, count 0 2006.257.14:03:34.46#ibcon#about to read 4, iclass 7, count 0 2006.257.14:03:34.46#ibcon#read 4, iclass 7, count 0 2006.257.14:03:34.46#ibcon#about to read 5, iclass 7, count 0 2006.257.14:03:34.46#ibcon#read 5, iclass 7, count 0 2006.257.14:03:34.46#ibcon#about to read 6, iclass 7, count 0 2006.257.14:03:34.46#ibcon#read 6, iclass 7, count 0 2006.257.14:03:34.46#ibcon#end of sib2, iclass 7, count 0 2006.257.14:03:34.46#ibcon#*after write, iclass 7, count 0 2006.257.14:03:34.46#ibcon#*before return 0, iclass 7, count 0 2006.257.14:03:34.46#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:34.46#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:34.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.14:03:34.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.14:03:34.46$vck44/valo=5,734.99 2006.257.14:03:34.46#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.14:03:34.46#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.14:03:34.46#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:34.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:34.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:34.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:34.46#ibcon#enter wrdev, iclass 11, count 0 2006.257.14:03:34.46#ibcon#first serial, iclass 11, count 0 2006.257.14:03:34.46#ibcon#enter sib2, iclass 11, count 0 2006.257.14:03:34.46#ibcon#flushed, iclass 11, count 0 2006.257.14:03:34.46#ibcon#about to write, iclass 11, count 0 2006.257.14:03:34.46#ibcon#wrote, iclass 11, count 0 2006.257.14:03:34.46#ibcon#about to read 3, iclass 11, count 0 2006.257.14:03:34.48#ibcon#read 3, iclass 11, count 0 2006.257.14:03:34.48#ibcon#about to read 4, iclass 11, count 0 2006.257.14:03:34.48#ibcon#read 4, iclass 11, count 0 2006.257.14:03:34.48#ibcon#about to read 5, iclass 11, count 0 2006.257.14:03:34.48#ibcon#read 5, iclass 11, count 0 2006.257.14:03:34.48#ibcon#about to read 6, iclass 11, count 0 2006.257.14:03:34.48#ibcon#read 6, iclass 11, count 0 2006.257.14:03:34.48#ibcon#end of sib2, iclass 11, count 0 2006.257.14:03:34.48#ibcon#*mode == 0, iclass 11, count 0 2006.257.14:03:34.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.14:03:34.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:03:34.48#ibcon#*before write, iclass 11, count 0 2006.257.14:03:34.48#ibcon#enter sib2, iclass 11, count 0 2006.257.14:03:34.48#ibcon#flushed, iclass 11, count 0 2006.257.14:03:34.48#ibcon#about to write, iclass 11, count 0 2006.257.14:03:34.48#ibcon#wrote, iclass 11, count 0 2006.257.14:03:34.48#ibcon#about to read 3, iclass 11, count 0 2006.257.14:03:34.52#ibcon#read 3, iclass 11, count 0 2006.257.14:03:34.52#ibcon#about to read 4, iclass 11, count 0 2006.257.14:03:34.52#ibcon#read 4, iclass 11, count 0 2006.257.14:03:34.52#ibcon#about to read 5, iclass 11, count 0 2006.257.14:03:34.52#ibcon#read 5, iclass 11, count 0 2006.257.14:03:34.52#ibcon#about to read 6, iclass 11, count 0 2006.257.14:03:34.52#ibcon#read 6, iclass 11, count 0 2006.257.14:03:35.31#ibcon#end of sib2, iclass 11, count 0 2006.257.14:03:35.31#ibcon#*after write, iclass 11, count 0 2006.257.14:03:35.31#ibcon#*before return 0, iclass 11, count 0 2006.257.14:03:35.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:35.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:35.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.14:03:35.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.14:03:35.31$vck44/va=5,4 2006.257.14:03:35.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.14:03:35.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.14:03:35.32#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:35.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:35.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:35.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:35.32#ibcon#enter wrdev, iclass 13, count 2 2006.257.14:03:35.32#ibcon#first serial, iclass 13, count 2 2006.257.14:03:35.32#ibcon#enter sib2, iclass 13, count 2 2006.257.14:03:35.32#ibcon#flushed, iclass 13, count 2 2006.257.14:03:35.32#ibcon#about to write, iclass 13, count 2 2006.257.14:03:35.32#ibcon#wrote, iclass 13, count 2 2006.257.14:03:35.32#ibcon#about to read 3, iclass 13, count 2 2006.257.14:03:35.33#ibcon#read 3, iclass 13, count 2 2006.257.14:03:35.33#ibcon#about to read 4, iclass 13, count 2 2006.257.14:03:35.33#ibcon#read 4, iclass 13, count 2 2006.257.14:03:35.33#ibcon#about to read 5, iclass 13, count 2 2006.257.14:03:35.33#ibcon#read 5, iclass 13, count 2 2006.257.14:03:35.33#ibcon#about to read 6, iclass 13, count 2 2006.257.14:03:35.33#ibcon#read 6, iclass 13, count 2 2006.257.14:03:35.33#ibcon#end of sib2, iclass 13, count 2 2006.257.14:03:35.33#ibcon#*mode == 0, iclass 13, count 2 2006.257.14:03:35.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.14:03:35.33#ibcon#[25=AT05-04\r\n] 2006.257.14:03:35.33#ibcon#*before write, iclass 13, count 2 2006.257.14:03:35.33#ibcon#enter sib2, iclass 13, count 2 2006.257.14:03:35.33#ibcon#flushed, iclass 13, count 2 2006.257.14:03:35.33#ibcon#about to write, iclass 13, count 2 2006.257.14:03:35.33#ibcon#wrote, iclass 13, count 2 2006.257.14:03:35.33#ibcon#about to read 3, iclass 13, count 2 2006.257.14:03:35.36#ibcon#read 3, iclass 13, count 2 2006.257.14:03:35.36#ibcon#about to read 4, iclass 13, count 2 2006.257.14:03:35.36#ibcon#read 4, iclass 13, count 2 2006.257.14:03:35.36#ibcon#about to read 5, iclass 13, count 2 2006.257.14:03:35.36#ibcon#read 5, iclass 13, count 2 2006.257.14:03:35.36#ibcon#about to read 6, iclass 13, count 2 2006.257.14:03:35.36#ibcon#read 6, iclass 13, count 2 2006.257.14:03:35.36#ibcon#end of sib2, iclass 13, count 2 2006.257.14:03:35.36#ibcon#*after write, iclass 13, count 2 2006.257.14:03:35.36#ibcon#*before return 0, iclass 13, count 2 2006.257.14:03:35.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:35.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:35.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.14:03:35.36#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:35.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:35.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:35.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:35.48#ibcon#enter wrdev, iclass 13, count 0 2006.257.14:03:35.48#ibcon#first serial, iclass 13, count 0 2006.257.14:03:35.48#ibcon#enter sib2, iclass 13, count 0 2006.257.14:03:35.48#ibcon#flushed, iclass 13, count 0 2006.257.14:03:35.48#ibcon#about to write, iclass 13, count 0 2006.257.14:03:35.48#ibcon#wrote, iclass 13, count 0 2006.257.14:03:35.48#ibcon#about to read 3, iclass 13, count 0 2006.257.14:03:35.50#ibcon#read 3, iclass 13, count 0 2006.257.14:03:35.50#ibcon#about to read 4, iclass 13, count 0 2006.257.14:03:35.50#ibcon#read 4, iclass 13, count 0 2006.257.14:03:35.50#ibcon#about to read 5, iclass 13, count 0 2006.257.14:03:35.50#ibcon#read 5, iclass 13, count 0 2006.257.14:03:35.50#ibcon#about to read 6, iclass 13, count 0 2006.257.14:03:35.50#ibcon#read 6, iclass 13, count 0 2006.257.14:03:35.50#ibcon#end of sib2, iclass 13, count 0 2006.257.14:03:35.50#ibcon#*mode == 0, iclass 13, count 0 2006.257.14:03:35.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.14:03:35.50#ibcon#[25=USB\r\n] 2006.257.14:03:35.50#ibcon#*before write, iclass 13, count 0 2006.257.14:03:35.50#ibcon#enter sib2, iclass 13, count 0 2006.257.14:03:35.50#ibcon#flushed, iclass 13, count 0 2006.257.14:03:35.50#ibcon#about to write, iclass 13, count 0 2006.257.14:03:35.50#ibcon#wrote, iclass 13, count 0 2006.257.14:03:35.50#ibcon#about to read 3, iclass 13, count 0 2006.257.14:03:35.53#ibcon#read 3, iclass 13, count 0 2006.257.14:03:35.53#ibcon#about to read 4, iclass 13, count 0 2006.257.14:03:35.53#ibcon#read 4, iclass 13, count 0 2006.257.14:03:35.53#ibcon#about to read 5, iclass 13, count 0 2006.257.14:03:35.53#ibcon#read 5, iclass 13, count 0 2006.257.14:03:35.53#ibcon#about to read 6, iclass 13, count 0 2006.257.14:03:35.53#ibcon#read 6, iclass 13, count 0 2006.257.14:03:35.53#ibcon#end of sib2, iclass 13, count 0 2006.257.14:03:35.53#ibcon#*after write, iclass 13, count 0 2006.257.14:03:35.53#ibcon#*before return 0, iclass 13, count 0 2006.257.14:03:35.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:35.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:35.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.14:03:35.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.14:03:35.53$vck44/valo=6,814.99 2006.257.14:03:35.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.14:03:35.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.14:03:35.53#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:35.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:35.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:35.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:35.53#ibcon#enter wrdev, iclass 15, count 0 2006.257.14:03:35.53#ibcon#first serial, iclass 15, count 0 2006.257.14:03:35.53#ibcon#enter sib2, iclass 15, count 0 2006.257.14:03:35.53#ibcon#flushed, iclass 15, count 0 2006.257.14:03:35.53#ibcon#about to write, iclass 15, count 0 2006.257.14:03:35.53#ibcon#wrote, iclass 15, count 0 2006.257.14:03:35.53#ibcon#about to read 3, iclass 15, count 0 2006.257.14:03:35.55#ibcon#read 3, iclass 15, count 0 2006.257.14:03:35.55#ibcon#about to read 4, iclass 15, count 0 2006.257.14:03:35.55#ibcon#read 4, iclass 15, count 0 2006.257.14:03:35.55#ibcon#about to read 5, iclass 15, count 0 2006.257.14:03:35.55#ibcon#read 5, iclass 15, count 0 2006.257.14:03:35.55#ibcon#about to read 6, iclass 15, count 0 2006.257.14:03:35.55#ibcon#read 6, iclass 15, count 0 2006.257.14:03:35.55#ibcon#end of sib2, iclass 15, count 0 2006.257.14:03:35.55#ibcon#*mode == 0, iclass 15, count 0 2006.257.14:03:35.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.14:03:35.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:03:35.55#ibcon#*before write, iclass 15, count 0 2006.257.14:03:35.55#ibcon#enter sib2, iclass 15, count 0 2006.257.14:03:35.55#ibcon#flushed, iclass 15, count 0 2006.257.14:03:35.55#ibcon#about to write, iclass 15, count 0 2006.257.14:03:35.55#ibcon#wrote, iclass 15, count 0 2006.257.14:03:35.55#ibcon#about to read 3, iclass 15, count 0 2006.257.14:03:35.59#ibcon#read 3, iclass 15, count 0 2006.257.14:03:35.59#ibcon#about to read 4, iclass 15, count 0 2006.257.14:03:35.59#ibcon#read 4, iclass 15, count 0 2006.257.14:03:35.59#ibcon#about to read 5, iclass 15, count 0 2006.257.14:03:35.59#ibcon#read 5, iclass 15, count 0 2006.257.14:03:35.59#ibcon#about to read 6, iclass 15, count 0 2006.257.14:03:35.59#ibcon#read 6, iclass 15, count 0 2006.257.14:03:35.59#ibcon#end of sib2, iclass 15, count 0 2006.257.14:03:35.59#ibcon#*after write, iclass 15, count 0 2006.257.14:03:35.59#ibcon#*before return 0, iclass 15, count 0 2006.257.14:03:35.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:35.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:35.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.14:03:35.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.14:03:35.59$vck44/va=6,4 2006.257.14:03:35.59#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.14:03:35.59#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.14:03:35.59#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:35.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:35.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:35.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:35.65#ibcon#enter wrdev, iclass 17, count 2 2006.257.14:03:35.65#ibcon#first serial, iclass 17, count 2 2006.257.14:03:35.65#ibcon#enter sib2, iclass 17, count 2 2006.257.14:03:35.65#ibcon#flushed, iclass 17, count 2 2006.257.14:03:35.65#ibcon#about to write, iclass 17, count 2 2006.257.14:03:35.65#ibcon#wrote, iclass 17, count 2 2006.257.14:03:35.65#ibcon#about to read 3, iclass 17, count 2 2006.257.14:03:35.67#ibcon#read 3, iclass 17, count 2 2006.257.14:03:35.67#ibcon#about to read 4, iclass 17, count 2 2006.257.14:03:35.67#ibcon#read 4, iclass 17, count 2 2006.257.14:03:35.67#ibcon#about to read 5, iclass 17, count 2 2006.257.14:03:35.67#ibcon#read 5, iclass 17, count 2 2006.257.14:03:35.67#ibcon#about to read 6, iclass 17, count 2 2006.257.14:03:35.67#ibcon#read 6, iclass 17, count 2 2006.257.14:03:35.67#ibcon#end of sib2, iclass 17, count 2 2006.257.14:03:35.67#ibcon#*mode == 0, iclass 17, count 2 2006.257.14:03:35.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.14:03:35.67#ibcon#[25=AT06-04\r\n] 2006.257.14:03:35.67#ibcon#*before write, iclass 17, count 2 2006.257.14:03:35.67#ibcon#enter sib2, iclass 17, count 2 2006.257.14:03:35.67#ibcon#flushed, iclass 17, count 2 2006.257.14:03:35.67#ibcon#about to write, iclass 17, count 2 2006.257.14:03:35.67#ibcon#wrote, iclass 17, count 2 2006.257.14:03:35.67#ibcon#about to read 3, iclass 17, count 2 2006.257.14:03:35.70#ibcon#read 3, iclass 17, count 2 2006.257.14:03:35.70#ibcon#about to read 4, iclass 17, count 2 2006.257.14:03:35.70#ibcon#read 4, iclass 17, count 2 2006.257.14:03:35.70#ibcon#about to read 5, iclass 17, count 2 2006.257.14:03:35.70#ibcon#read 5, iclass 17, count 2 2006.257.14:03:35.70#ibcon#about to read 6, iclass 17, count 2 2006.257.14:03:35.70#ibcon#read 6, iclass 17, count 2 2006.257.14:03:35.70#ibcon#end of sib2, iclass 17, count 2 2006.257.14:03:35.70#ibcon#*after write, iclass 17, count 2 2006.257.14:03:35.70#ibcon#*before return 0, iclass 17, count 2 2006.257.14:03:35.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:35.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:35.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.14:03:35.70#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:35.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:35.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:35.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:35.82#ibcon#enter wrdev, iclass 17, count 0 2006.257.14:03:35.82#ibcon#first serial, iclass 17, count 0 2006.257.14:03:35.82#ibcon#enter sib2, iclass 17, count 0 2006.257.14:03:35.82#ibcon#flushed, iclass 17, count 0 2006.257.14:03:35.82#ibcon#about to write, iclass 17, count 0 2006.257.14:03:35.82#ibcon#wrote, iclass 17, count 0 2006.257.14:03:35.82#ibcon#about to read 3, iclass 17, count 0 2006.257.14:03:35.84#ibcon#read 3, iclass 17, count 0 2006.257.14:03:35.84#ibcon#about to read 4, iclass 17, count 0 2006.257.14:03:35.84#ibcon#read 4, iclass 17, count 0 2006.257.14:03:35.84#ibcon#about to read 5, iclass 17, count 0 2006.257.14:03:35.84#ibcon#read 5, iclass 17, count 0 2006.257.14:03:35.84#ibcon#about to read 6, iclass 17, count 0 2006.257.14:03:35.84#ibcon#read 6, iclass 17, count 0 2006.257.14:03:35.84#ibcon#end of sib2, iclass 17, count 0 2006.257.14:03:35.84#ibcon#*mode == 0, iclass 17, count 0 2006.257.14:03:35.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.14:03:35.84#ibcon#[25=USB\r\n] 2006.257.14:03:35.84#ibcon#*before write, iclass 17, count 0 2006.257.14:03:35.84#ibcon#enter sib2, iclass 17, count 0 2006.257.14:03:35.84#ibcon#flushed, iclass 17, count 0 2006.257.14:03:35.84#ibcon#about to write, iclass 17, count 0 2006.257.14:03:35.84#ibcon#wrote, iclass 17, count 0 2006.257.14:03:35.84#ibcon#about to read 3, iclass 17, count 0 2006.257.14:03:35.87#ibcon#read 3, iclass 17, count 0 2006.257.14:03:35.87#ibcon#about to read 4, iclass 17, count 0 2006.257.14:03:35.87#ibcon#read 4, iclass 17, count 0 2006.257.14:03:35.87#ibcon#about to read 5, iclass 17, count 0 2006.257.14:03:35.87#ibcon#read 5, iclass 17, count 0 2006.257.14:03:35.87#ibcon#about to read 6, iclass 17, count 0 2006.257.14:03:35.87#ibcon#read 6, iclass 17, count 0 2006.257.14:03:35.87#ibcon#end of sib2, iclass 17, count 0 2006.257.14:03:35.87#ibcon#*after write, iclass 17, count 0 2006.257.14:03:35.87#ibcon#*before return 0, iclass 17, count 0 2006.257.14:03:35.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:35.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:35.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.14:03:35.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.14:03:35.87$vck44/valo=7,864.99 2006.257.14:03:35.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.14:03:35.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.14:03:35.87#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:35.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:35.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:35.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:35.87#ibcon#enter wrdev, iclass 19, count 0 2006.257.14:03:35.87#ibcon#first serial, iclass 19, count 0 2006.257.14:03:35.87#ibcon#enter sib2, iclass 19, count 0 2006.257.14:03:35.87#ibcon#flushed, iclass 19, count 0 2006.257.14:03:35.87#ibcon#about to write, iclass 19, count 0 2006.257.14:03:35.87#ibcon#wrote, iclass 19, count 0 2006.257.14:03:35.87#ibcon#about to read 3, iclass 19, count 0 2006.257.14:03:35.89#ibcon#read 3, iclass 19, count 0 2006.257.14:03:35.89#ibcon#about to read 4, iclass 19, count 0 2006.257.14:03:35.89#ibcon#read 4, iclass 19, count 0 2006.257.14:03:35.89#ibcon#about to read 5, iclass 19, count 0 2006.257.14:03:35.89#ibcon#read 5, iclass 19, count 0 2006.257.14:03:35.89#ibcon#about to read 6, iclass 19, count 0 2006.257.14:03:35.89#ibcon#read 6, iclass 19, count 0 2006.257.14:03:35.89#ibcon#end of sib2, iclass 19, count 0 2006.257.14:03:35.89#ibcon#*mode == 0, iclass 19, count 0 2006.257.14:03:35.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.14:03:35.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:03:35.89#ibcon#*before write, iclass 19, count 0 2006.257.14:03:35.89#ibcon#enter sib2, iclass 19, count 0 2006.257.14:03:35.89#ibcon#flushed, iclass 19, count 0 2006.257.14:03:35.89#ibcon#about to write, iclass 19, count 0 2006.257.14:03:35.89#ibcon#wrote, iclass 19, count 0 2006.257.14:03:35.89#ibcon#about to read 3, iclass 19, count 0 2006.257.14:03:35.93#ibcon#read 3, iclass 19, count 0 2006.257.14:03:35.93#ibcon#about to read 4, iclass 19, count 0 2006.257.14:03:35.93#ibcon#read 4, iclass 19, count 0 2006.257.14:03:35.93#ibcon#about to read 5, iclass 19, count 0 2006.257.14:03:35.93#ibcon#read 5, iclass 19, count 0 2006.257.14:03:35.93#ibcon#about to read 6, iclass 19, count 0 2006.257.14:03:35.93#ibcon#read 6, iclass 19, count 0 2006.257.14:03:35.93#ibcon#end of sib2, iclass 19, count 0 2006.257.14:03:35.93#ibcon#*after write, iclass 19, count 0 2006.257.14:03:35.93#ibcon#*before return 0, iclass 19, count 0 2006.257.14:03:35.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:35.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:35.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.14:03:35.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.14:03:35.93$vck44/va=7,4 2006.257.14:03:35.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.14:03:35.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.14:03:35.93#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:35.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:35.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:35.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:35.99#ibcon#enter wrdev, iclass 21, count 2 2006.257.14:03:35.99#ibcon#first serial, iclass 21, count 2 2006.257.14:03:35.99#ibcon#enter sib2, iclass 21, count 2 2006.257.14:03:35.99#ibcon#flushed, iclass 21, count 2 2006.257.14:03:35.99#ibcon#about to write, iclass 21, count 2 2006.257.14:03:35.99#ibcon#wrote, iclass 21, count 2 2006.257.14:03:35.99#ibcon#about to read 3, iclass 21, count 2 2006.257.14:03:36.01#ibcon#read 3, iclass 21, count 2 2006.257.14:03:36.01#ibcon#about to read 4, iclass 21, count 2 2006.257.14:03:36.01#ibcon#read 4, iclass 21, count 2 2006.257.14:03:36.01#ibcon#about to read 5, iclass 21, count 2 2006.257.14:03:36.01#ibcon#read 5, iclass 21, count 2 2006.257.14:03:36.01#ibcon#about to read 6, iclass 21, count 2 2006.257.14:03:36.01#ibcon#read 6, iclass 21, count 2 2006.257.14:03:36.01#ibcon#end of sib2, iclass 21, count 2 2006.257.14:03:36.01#ibcon#*mode == 0, iclass 21, count 2 2006.257.14:03:36.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.14:03:36.01#ibcon#[25=AT07-04\r\n] 2006.257.14:03:36.01#ibcon#*before write, iclass 21, count 2 2006.257.14:03:36.01#ibcon#enter sib2, iclass 21, count 2 2006.257.14:03:36.01#ibcon#flushed, iclass 21, count 2 2006.257.14:03:36.01#ibcon#about to write, iclass 21, count 2 2006.257.14:03:36.01#ibcon#wrote, iclass 21, count 2 2006.257.14:03:36.01#ibcon#about to read 3, iclass 21, count 2 2006.257.14:03:36.04#ibcon#read 3, iclass 21, count 2 2006.257.14:03:36.04#ibcon#about to read 4, iclass 21, count 2 2006.257.14:03:36.04#ibcon#read 4, iclass 21, count 2 2006.257.14:03:36.04#ibcon#about to read 5, iclass 21, count 2 2006.257.14:03:36.04#ibcon#read 5, iclass 21, count 2 2006.257.14:03:36.04#ibcon#about to read 6, iclass 21, count 2 2006.257.14:03:36.04#ibcon#read 6, iclass 21, count 2 2006.257.14:03:36.04#ibcon#end of sib2, iclass 21, count 2 2006.257.14:03:36.04#ibcon#*after write, iclass 21, count 2 2006.257.14:03:36.04#ibcon#*before return 0, iclass 21, count 2 2006.257.14:03:36.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:36.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:36.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.14:03:36.04#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:36.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:36.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:36.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:36.16#ibcon#enter wrdev, iclass 21, count 0 2006.257.14:03:36.16#ibcon#first serial, iclass 21, count 0 2006.257.14:03:36.16#ibcon#enter sib2, iclass 21, count 0 2006.257.14:03:36.16#ibcon#flushed, iclass 21, count 0 2006.257.14:03:36.16#ibcon#about to write, iclass 21, count 0 2006.257.14:03:36.16#ibcon#wrote, iclass 21, count 0 2006.257.14:03:36.16#ibcon#about to read 3, iclass 21, count 0 2006.257.14:03:36.18#ibcon#read 3, iclass 21, count 0 2006.257.14:03:36.18#ibcon#about to read 4, iclass 21, count 0 2006.257.14:03:36.18#ibcon#read 4, iclass 21, count 0 2006.257.14:03:36.18#ibcon#about to read 5, iclass 21, count 0 2006.257.14:03:36.18#ibcon#read 5, iclass 21, count 0 2006.257.14:03:36.18#ibcon#about to read 6, iclass 21, count 0 2006.257.14:03:36.18#ibcon#read 6, iclass 21, count 0 2006.257.14:03:36.18#ibcon#end of sib2, iclass 21, count 0 2006.257.14:03:36.18#ibcon#*mode == 0, iclass 21, count 0 2006.257.14:03:36.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.14:03:36.18#ibcon#[25=USB\r\n] 2006.257.14:03:36.18#ibcon#*before write, iclass 21, count 0 2006.257.14:03:36.18#ibcon#enter sib2, iclass 21, count 0 2006.257.14:03:36.18#ibcon#flushed, iclass 21, count 0 2006.257.14:03:36.18#ibcon#about to write, iclass 21, count 0 2006.257.14:03:36.18#ibcon#wrote, iclass 21, count 0 2006.257.14:03:36.18#ibcon#about to read 3, iclass 21, count 0 2006.257.14:03:36.21#ibcon#read 3, iclass 21, count 0 2006.257.14:03:36.21#ibcon#about to read 4, iclass 21, count 0 2006.257.14:03:36.21#ibcon#read 4, iclass 21, count 0 2006.257.14:03:36.21#ibcon#about to read 5, iclass 21, count 0 2006.257.14:03:36.21#ibcon#read 5, iclass 21, count 0 2006.257.14:03:36.21#ibcon#about to read 6, iclass 21, count 0 2006.257.14:03:36.21#ibcon#read 6, iclass 21, count 0 2006.257.14:03:36.21#ibcon#end of sib2, iclass 21, count 0 2006.257.14:03:36.21#ibcon#*after write, iclass 21, count 0 2006.257.14:03:36.21#ibcon#*before return 0, iclass 21, count 0 2006.257.14:03:36.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:36.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:36.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.14:03:36.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.14:03:36.21$vck44/valo=8,884.99 2006.257.14:03:36.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.14:03:36.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.14:03:36.21#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:36.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:36.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:36.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:36.21#ibcon#enter wrdev, iclass 23, count 0 2006.257.14:03:36.21#ibcon#first serial, iclass 23, count 0 2006.257.14:03:36.21#ibcon#enter sib2, iclass 23, count 0 2006.257.14:03:36.21#ibcon#flushed, iclass 23, count 0 2006.257.14:03:36.21#ibcon#about to write, iclass 23, count 0 2006.257.14:03:36.21#ibcon#wrote, iclass 23, count 0 2006.257.14:03:36.21#ibcon#about to read 3, iclass 23, count 0 2006.257.14:03:36.23#ibcon#read 3, iclass 23, count 0 2006.257.14:03:36.23#ibcon#about to read 4, iclass 23, count 0 2006.257.14:03:36.23#ibcon#read 4, iclass 23, count 0 2006.257.14:03:36.23#ibcon#about to read 5, iclass 23, count 0 2006.257.14:03:36.23#ibcon#read 5, iclass 23, count 0 2006.257.14:03:36.23#ibcon#about to read 6, iclass 23, count 0 2006.257.14:03:36.23#ibcon#read 6, iclass 23, count 0 2006.257.14:03:36.23#ibcon#end of sib2, iclass 23, count 0 2006.257.14:03:36.23#ibcon#*mode == 0, iclass 23, count 0 2006.257.14:03:36.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.14:03:36.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:03:36.23#ibcon#*before write, iclass 23, count 0 2006.257.14:03:36.23#ibcon#enter sib2, iclass 23, count 0 2006.257.14:03:36.23#ibcon#flushed, iclass 23, count 0 2006.257.14:03:36.23#ibcon#about to write, iclass 23, count 0 2006.257.14:03:36.23#ibcon#wrote, iclass 23, count 0 2006.257.14:03:36.23#ibcon#about to read 3, iclass 23, count 0 2006.257.14:03:36.27#ibcon#read 3, iclass 23, count 0 2006.257.14:03:36.27#ibcon#about to read 4, iclass 23, count 0 2006.257.14:03:36.27#ibcon#read 4, iclass 23, count 0 2006.257.14:03:36.27#ibcon#about to read 5, iclass 23, count 0 2006.257.14:03:36.27#ibcon#read 5, iclass 23, count 0 2006.257.14:03:36.27#ibcon#about to read 6, iclass 23, count 0 2006.257.14:03:36.27#ibcon#read 6, iclass 23, count 0 2006.257.14:03:36.27#ibcon#end of sib2, iclass 23, count 0 2006.257.14:03:36.27#ibcon#*after write, iclass 23, count 0 2006.257.14:03:36.27#ibcon#*before return 0, iclass 23, count 0 2006.257.14:03:36.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:36.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:36.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.14:03:36.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.14:03:36.27$vck44/va=8,4 2006.257.14:03:36.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.14:03:36.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.14:03:36.27#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:36.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:03:36.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:03:36.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:03:36.33#ibcon#enter wrdev, iclass 25, count 2 2006.257.14:03:36.33#ibcon#first serial, iclass 25, count 2 2006.257.14:03:36.33#ibcon#enter sib2, iclass 25, count 2 2006.257.14:03:36.33#ibcon#flushed, iclass 25, count 2 2006.257.14:03:36.33#ibcon#about to write, iclass 25, count 2 2006.257.14:03:36.33#ibcon#wrote, iclass 25, count 2 2006.257.14:03:36.33#ibcon#about to read 3, iclass 25, count 2 2006.257.14:03:36.35#ibcon#read 3, iclass 25, count 2 2006.257.14:03:36.35#ibcon#about to read 4, iclass 25, count 2 2006.257.14:03:36.35#ibcon#read 4, iclass 25, count 2 2006.257.14:03:36.35#ibcon#about to read 5, iclass 25, count 2 2006.257.14:03:36.35#ibcon#read 5, iclass 25, count 2 2006.257.14:03:36.35#ibcon#about to read 6, iclass 25, count 2 2006.257.14:03:36.35#ibcon#read 6, iclass 25, count 2 2006.257.14:03:36.35#ibcon#end of sib2, iclass 25, count 2 2006.257.14:03:36.35#ibcon#*mode == 0, iclass 25, count 2 2006.257.14:03:36.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.14:03:36.35#ibcon#[25=AT08-04\r\n] 2006.257.14:03:36.35#ibcon#*before write, iclass 25, count 2 2006.257.14:03:36.35#ibcon#enter sib2, iclass 25, count 2 2006.257.14:03:36.35#ibcon#flushed, iclass 25, count 2 2006.257.14:03:36.35#ibcon#about to write, iclass 25, count 2 2006.257.14:03:36.35#ibcon#wrote, iclass 25, count 2 2006.257.14:03:36.35#ibcon#about to read 3, iclass 25, count 2 2006.257.14:03:36.38#ibcon#read 3, iclass 25, count 2 2006.257.14:03:37.17#ibcon#about to read 4, iclass 25, count 2 2006.257.14:03:37.17#ibcon#read 4, iclass 25, count 2 2006.257.14:03:37.17#ibcon#about to read 5, iclass 25, count 2 2006.257.14:03:37.17#ibcon#read 5, iclass 25, count 2 2006.257.14:03:37.17#ibcon#about to read 6, iclass 25, count 2 2006.257.14:03:37.17#ibcon#read 6, iclass 25, count 2 2006.257.14:03:37.17#ibcon#end of sib2, iclass 25, count 2 2006.257.14:03:37.17#ibcon#*after write, iclass 25, count 2 2006.257.14:03:37.17#ibcon#*before return 0, iclass 25, count 2 2006.257.14:03:37.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:03:37.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:03:37.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.14:03:37.18#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:37.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:03:37.28#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:03:37.28#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:03:37.28#ibcon#enter wrdev, iclass 25, count 0 2006.257.14:03:37.28#ibcon#first serial, iclass 25, count 0 2006.257.14:03:37.28#ibcon#enter sib2, iclass 25, count 0 2006.257.14:03:37.28#ibcon#flushed, iclass 25, count 0 2006.257.14:03:37.28#ibcon#about to write, iclass 25, count 0 2006.257.14:03:37.28#ibcon#wrote, iclass 25, count 0 2006.257.14:03:37.28#ibcon#about to read 3, iclass 25, count 0 2006.257.14:03:37.30#ibcon#read 3, iclass 25, count 0 2006.257.14:03:37.30#ibcon#about to read 4, iclass 25, count 0 2006.257.14:03:37.30#ibcon#read 4, iclass 25, count 0 2006.257.14:03:37.30#ibcon#about to read 5, iclass 25, count 0 2006.257.14:03:37.30#ibcon#read 5, iclass 25, count 0 2006.257.14:03:37.30#ibcon#about to read 6, iclass 25, count 0 2006.257.14:03:37.30#ibcon#read 6, iclass 25, count 0 2006.257.14:03:37.30#ibcon#end of sib2, iclass 25, count 0 2006.257.14:03:37.30#ibcon#*mode == 0, iclass 25, count 0 2006.257.14:03:37.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.14:03:37.30#ibcon#[25=USB\r\n] 2006.257.14:03:37.30#ibcon#*before write, iclass 25, count 0 2006.257.14:03:37.30#ibcon#enter sib2, iclass 25, count 0 2006.257.14:03:37.30#ibcon#flushed, iclass 25, count 0 2006.257.14:03:37.30#ibcon#about to write, iclass 25, count 0 2006.257.14:03:37.30#ibcon#wrote, iclass 25, count 0 2006.257.14:03:37.30#ibcon#about to read 3, iclass 25, count 0 2006.257.14:03:37.33#ibcon#read 3, iclass 25, count 0 2006.257.14:03:37.33#ibcon#about to read 4, iclass 25, count 0 2006.257.14:03:37.33#ibcon#read 4, iclass 25, count 0 2006.257.14:03:37.33#ibcon#about to read 5, iclass 25, count 0 2006.257.14:03:37.33#ibcon#read 5, iclass 25, count 0 2006.257.14:03:37.33#ibcon#about to read 6, iclass 25, count 0 2006.257.14:03:37.33#ibcon#read 6, iclass 25, count 0 2006.257.14:03:37.33#ibcon#end of sib2, iclass 25, count 0 2006.257.14:03:37.33#ibcon#*after write, iclass 25, count 0 2006.257.14:03:37.33#ibcon#*before return 0, iclass 25, count 0 2006.257.14:03:37.33#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:03:37.33#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:03:37.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.14:03:37.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.14:03:37.33$vck44/vblo=1,629.99 2006.257.14:03:37.33#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.14:03:37.33#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.14:03:37.33#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:37.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:03:37.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:03:37.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:03:37.33#ibcon#enter wrdev, iclass 27, count 0 2006.257.14:03:37.33#ibcon#first serial, iclass 27, count 0 2006.257.14:03:37.33#ibcon#enter sib2, iclass 27, count 0 2006.257.14:03:37.33#ibcon#flushed, iclass 27, count 0 2006.257.14:03:37.33#ibcon#about to write, iclass 27, count 0 2006.257.14:03:37.33#ibcon#wrote, iclass 27, count 0 2006.257.14:03:37.33#ibcon#about to read 3, iclass 27, count 0 2006.257.14:03:37.35#ibcon#read 3, iclass 27, count 0 2006.257.14:03:37.35#ibcon#about to read 4, iclass 27, count 0 2006.257.14:03:37.35#ibcon#read 4, iclass 27, count 0 2006.257.14:03:37.35#ibcon#about to read 5, iclass 27, count 0 2006.257.14:03:37.35#ibcon#read 5, iclass 27, count 0 2006.257.14:03:37.35#ibcon#about to read 6, iclass 27, count 0 2006.257.14:03:37.35#ibcon#read 6, iclass 27, count 0 2006.257.14:03:37.35#ibcon#end of sib2, iclass 27, count 0 2006.257.14:03:37.35#ibcon#*mode == 0, iclass 27, count 0 2006.257.14:03:37.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.14:03:37.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:03:37.35#ibcon#*before write, iclass 27, count 0 2006.257.14:03:37.35#ibcon#enter sib2, iclass 27, count 0 2006.257.14:03:37.35#ibcon#flushed, iclass 27, count 0 2006.257.14:03:37.35#ibcon#about to write, iclass 27, count 0 2006.257.14:03:37.35#ibcon#wrote, iclass 27, count 0 2006.257.14:03:37.35#ibcon#about to read 3, iclass 27, count 0 2006.257.14:03:37.39#ibcon#read 3, iclass 27, count 0 2006.257.14:03:37.39#ibcon#about to read 4, iclass 27, count 0 2006.257.14:03:37.39#ibcon#read 4, iclass 27, count 0 2006.257.14:03:37.39#ibcon#about to read 5, iclass 27, count 0 2006.257.14:03:37.39#ibcon#read 5, iclass 27, count 0 2006.257.14:03:37.39#ibcon#about to read 6, iclass 27, count 0 2006.257.14:03:37.39#ibcon#read 6, iclass 27, count 0 2006.257.14:03:37.39#ibcon#end of sib2, iclass 27, count 0 2006.257.14:03:37.39#ibcon#*after write, iclass 27, count 0 2006.257.14:03:37.39#ibcon#*before return 0, iclass 27, count 0 2006.257.14:03:37.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:03:37.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:03:37.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.14:03:37.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.14:03:37.39$vck44/vb=1,4 2006.257.14:03:37.39#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.14:03:37.39#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.14:03:37.39#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:37.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:03:37.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:03:37.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:03:37.39#ibcon#enter wrdev, iclass 29, count 2 2006.257.14:03:37.39#ibcon#first serial, iclass 29, count 2 2006.257.14:03:37.39#ibcon#enter sib2, iclass 29, count 2 2006.257.14:03:37.39#ibcon#flushed, iclass 29, count 2 2006.257.14:03:37.39#ibcon#about to write, iclass 29, count 2 2006.257.14:03:37.39#ibcon#wrote, iclass 29, count 2 2006.257.14:03:37.39#ibcon#about to read 3, iclass 29, count 2 2006.257.14:03:37.41#ibcon#read 3, iclass 29, count 2 2006.257.14:03:37.41#ibcon#about to read 4, iclass 29, count 2 2006.257.14:03:37.41#ibcon#read 4, iclass 29, count 2 2006.257.14:03:37.41#ibcon#about to read 5, iclass 29, count 2 2006.257.14:03:37.41#ibcon#read 5, iclass 29, count 2 2006.257.14:03:37.41#ibcon#about to read 6, iclass 29, count 2 2006.257.14:03:37.41#ibcon#read 6, iclass 29, count 2 2006.257.14:03:37.41#ibcon#end of sib2, iclass 29, count 2 2006.257.14:03:37.41#ibcon#*mode == 0, iclass 29, count 2 2006.257.14:03:37.41#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.14:03:37.41#ibcon#[27=AT01-04\r\n] 2006.257.14:03:37.41#ibcon#*before write, iclass 29, count 2 2006.257.14:03:37.41#ibcon#enter sib2, iclass 29, count 2 2006.257.14:03:37.41#ibcon#flushed, iclass 29, count 2 2006.257.14:03:37.41#ibcon#about to write, iclass 29, count 2 2006.257.14:03:37.41#ibcon#wrote, iclass 29, count 2 2006.257.14:03:37.41#ibcon#about to read 3, iclass 29, count 2 2006.257.14:03:37.44#ibcon#read 3, iclass 29, count 2 2006.257.14:03:37.44#ibcon#about to read 4, iclass 29, count 2 2006.257.14:03:37.44#ibcon#read 4, iclass 29, count 2 2006.257.14:03:37.44#ibcon#about to read 5, iclass 29, count 2 2006.257.14:03:37.44#ibcon#read 5, iclass 29, count 2 2006.257.14:03:37.44#ibcon#about to read 6, iclass 29, count 2 2006.257.14:03:37.44#ibcon#read 6, iclass 29, count 2 2006.257.14:03:37.44#ibcon#end of sib2, iclass 29, count 2 2006.257.14:03:37.44#ibcon#*after write, iclass 29, count 2 2006.257.14:03:37.44#ibcon#*before return 0, iclass 29, count 2 2006.257.14:03:37.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:03:37.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:03:37.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.14:03:37.44#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:37.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:03:37.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:03:37.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:03:37.56#ibcon#enter wrdev, iclass 29, count 0 2006.257.14:03:37.56#ibcon#first serial, iclass 29, count 0 2006.257.14:03:37.56#ibcon#enter sib2, iclass 29, count 0 2006.257.14:03:37.56#ibcon#flushed, iclass 29, count 0 2006.257.14:03:37.56#ibcon#about to write, iclass 29, count 0 2006.257.14:03:37.56#ibcon#wrote, iclass 29, count 0 2006.257.14:03:37.56#ibcon#about to read 3, iclass 29, count 0 2006.257.14:03:37.58#ibcon#read 3, iclass 29, count 0 2006.257.14:03:37.58#ibcon#about to read 4, iclass 29, count 0 2006.257.14:03:37.58#ibcon#read 4, iclass 29, count 0 2006.257.14:03:37.58#ibcon#about to read 5, iclass 29, count 0 2006.257.14:03:37.58#ibcon#read 5, iclass 29, count 0 2006.257.14:03:37.58#ibcon#about to read 6, iclass 29, count 0 2006.257.14:03:37.58#ibcon#read 6, iclass 29, count 0 2006.257.14:03:37.58#ibcon#end of sib2, iclass 29, count 0 2006.257.14:03:37.58#ibcon#*mode == 0, iclass 29, count 0 2006.257.14:03:37.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.14:03:37.58#ibcon#[27=USB\r\n] 2006.257.14:03:37.58#ibcon#*before write, iclass 29, count 0 2006.257.14:03:37.58#ibcon#enter sib2, iclass 29, count 0 2006.257.14:03:37.58#ibcon#flushed, iclass 29, count 0 2006.257.14:03:37.58#ibcon#about to write, iclass 29, count 0 2006.257.14:03:37.58#ibcon#wrote, iclass 29, count 0 2006.257.14:03:37.58#ibcon#about to read 3, iclass 29, count 0 2006.257.14:03:37.61#ibcon#read 3, iclass 29, count 0 2006.257.14:03:37.61#ibcon#about to read 4, iclass 29, count 0 2006.257.14:03:37.61#ibcon#read 4, iclass 29, count 0 2006.257.14:03:37.61#ibcon#about to read 5, iclass 29, count 0 2006.257.14:03:37.61#ibcon#read 5, iclass 29, count 0 2006.257.14:03:37.61#ibcon#about to read 6, iclass 29, count 0 2006.257.14:03:37.61#ibcon#read 6, iclass 29, count 0 2006.257.14:03:37.61#ibcon#end of sib2, iclass 29, count 0 2006.257.14:03:37.61#ibcon#*after write, iclass 29, count 0 2006.257.14:03:37.61#ibcon#*before return 0, iclass 29, count 0 2006.257.14:03:37.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:03:37.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:03:37.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.14:03:37.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.14:03:37.61$vck44/vblo=2,634.99 2006.257.14:03:37.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.14:03:37.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.14:03:37.61#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:37.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:37.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:37.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:37.61#ibcon#enter wrdev, iclass 31, count 0 2006.257.14:03:37.61#ibcon#first serial, iclass 31, count 0 2006.257.14:03:37.61#ibcon#enter sib2, iclass 31, count 0 2006.257.14:03:37.61#ibcon#flushed, iclass 31, count 0 2006.257.14:03:37.61#ibcon#about to write, iclass 31, count 0 2006.257.14:03:37.61#ibcon#wrote, iclass 31, count 0 2006.257.14:03:37.61#ibcon#about to read 3, iclass 31, count 0 2006.257.14:03:37.63#ibcon#read 3, iclass 31, count 0 2006.257.14:03:37.63#ibcon#about to read 4, iclass 31, count 0 2006.257.14:03:37.63#ibcon#read 4, iclass 31, count 0 2006.257.14:03:37.63#ibcon#about to read 5, iclass 31, count 0 2006.257.14:03:37.63#ibcon#read 5, iclass 31, count 0 2006.257.14:03:37.63#ibcon#about to read 6, iclass 31, count 0 2006.257.14:03:37.63#ibcon#read 6, iclass 31, count 0 2006.257.14:03:37.63#ibcon#end of sib2, iclass 31, count 0 2006.257.14:03:37.63#ibcon#*mode == 0, iclass 31, count 0 2006.257.14:03:37.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.14:03:37.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:03:37.63#ibcon#*before write, iclass 31, count 0 2006.257.14:03:37.63#ibcon#enter sib2, iclass 31, count 0 2006.257.14:03:37.63#ibcon#flushed, iclass 31, count 0 2006.257.14:03:37.63#ibcon#about to write, iclass 31, count 0 2006.257.14:03:37.63#ibcon#wrote, iclass 31, count 0 2006.257.14:03:37.63#ibcon#about to read 3, iclass 31, count 0 2006.257.14:03:37.67#ibcon#read 3, iclass 31, count 0 2006.257.14:03:37.67#ibcon#about to read 4, iclass 31, count 0 2006.257.14:03:37.67#ibcon#read 4, iclass 31, count 0 2006.257.14:03:37.67#ibcon#about to read 5, iclass 31, count 0 2006.257.14:03:37.67#ibcon#read 5, iclass 31, count 0 2006.257.14:03:37.67#ibcon#about to read 6, iclass 31, count 0 2006.257.14:03:37.67#ibcon#read 6, iclass 31, count 0 2006.257.14:03:37.67#ibcon#end of sib2, iclass 31, count 0 2006.257.14:03:37.67#ibcon#*after write, iclass 31, count 0 2006.257.14:03:37.67#ibcon#*before return 0, iclass 31, count 0 2006.257.14:03:37.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:37.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:03:37.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.14:03:37.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.14:03:37.67$vck44/vb=2,5 2006.257.14:03:37.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.14:03:37.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.14:03:37.67#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:37.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:37.73#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:37.73#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:37.73#ibcon#enter wrdev, iclass 33, count 2 2006.257.14:03:37.73#ibcon#first serial, iclass 33, count 2 2006.257.14:03:37.73#ibcon#enter sib2, iclass 33, count 2 2006.257.14:03:37.73#ibcon#flushed, iclass 33, count 2 2006.257.14:03:37.73#ibcon#about to write, iclass 33, count 2 2006.257.14:03:37.73#ibcon#wrote, iclass 33, count 2 2006.257.14:03:37.73#ibcon#about to read 3, iclass 33, count 2 2006.257.14:03:37.75#ibcon#read 3, iclass 33, count 2 2006.257.14:03:37.75#ibcon#about to read 4, iclass 33, count 2 2006.257.14:03:37.75#ibcon#read 4, iclass 33, count 2 2006.257.14:03:37.75#ibcon#about to read 5, iclass 33, count 2 2006.257.14:03:37.75#ibcon#read 5, iclass 33, count 2 2006.257.14:03:37.75#ibcon#about to read 6, iclass 33, count 2 2006.257.14:03:37.75#ibcon#read 6, iclass 33, count 2 2006.257.14:03:37.75#ibcon#end of sib2, iclass 33, count 2 2006.257.14:03:37.75#ibcon#*mode == 0, iclass 33, count 2 2006.257.14:03:37.75#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.14:03:37.75#ibcon#[27=AT02-05\r\n] 2006.257.14:03:37.75#ibcon#*before write, iclass 33, count 2 2006.257.14:03:37.75#ibcon#enter sib2, iclass 33, count 2 2006.257.14:03:37.75#ibcon#flushed, iclass 33, count 2 2006.257.14:03:37.75#ibcon#about to write, iclass 33, count 2 2006.257.14:03:37.75#ibcon#wrote, iclass 33, count 2 2006.257.14:03:37.75#ibcon#about to read 3, iclass 33, count 2 2006.257.14:03:37.78#ibcon#read 3, iclass 33, count 2 2006.257.14:03:37.78#ibcon#about to read 4, iclass 33, count 2 2006.257.14:03:37.78#ibcon#read 4, iclass 33, count 2 2006.257.14:03:37.78#ibcon#about to read 5, iclass 33, count 2 2006.257.14:03:37.78#ibcon#read 5, iclass 33, count 2 2006.257.14:03:37.78#ibcon#about to read 6, iclass 33, count 2 2006.257.14:03:37.78#ibcon#read 6, iclass 33, count 2 2006.257.14:03:37.78#ibcon#end of sib2, iclass 33, count 2 2006.257.14:03:37.78#ibcon#*after write, iclass 33, count 2 2006.257.14:03:37.78#ibcon#*before return 0, iclass 33, count 2 2006.257.14:03:37.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:37.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:03:37.78#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.14:03:37.78#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:37.78#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:37.90#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:37.90#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:37.90#ibcon#enter wrdev, iclass 33, count 0 2006.257.14:03:37.90#ibcon#first serial, iclass 33, count 0 2006.257.14:03:37.90#ibcon#enter sib2, iclass 33, count 0 2006.257.14:03:37.90#ibcon#flushed, iclass 33, count 0 2006.257.14:03:37.90#ibcon#about to write, iclass 33, count 0 2006.257.14:03:37.90#ibcon#wrote, iclass 33, count 0 2006.257.14:03:37.90#ibcon#about to read 3, iclass 33, count 0 2006.257.14:03:37.92#ibcon#read 3, iclass 33, count 0 2006.257.14:03:37.92#ibcon#about to read 4, iclass 33, count 0 2006.257.14:03:37.92#ibcon#read 4, iclass 33, count 0 2006.257.14:03:37.92#ibcon#about to read 5, iclass 33, count 0 2006.257.14:03:37.92#ibcon#read 5, iclass 33, count 0 2006.257.14:03:37.92#ibcon#about to read 6, iclass 33, count 0 2006.257.14:03:37.92#ibcon#read 6, iclass 33, count 0 2006.257.14:03:37.92#ibcon#end of sib2, iclass 33, count 0 2006.257.14:03:37.92#ibcon#*mode == 0, iclass 33, count 0 2006.257.14:03:37.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.14:03:37.92#ibcon#[27=USB\r\n] 2006.257.14:03:37.92#ibcon#*before write, iclass 33, count 0 2006.257.14:03:37.92#ibcon#enter sib2, iclass 33, count 0 2006.257.14:03:37.92#ibcon#flushed, iclass 33, count 0 2006.257.14:03:37.92#ibcon#about to write, iclass 33, count 0 2006.257.14:03:37.92#ibcon#wrote, iclass 33, count 0 2006.257.14:03:37.92#ibcon#about to read 3, iclass 33, count 0 2006.257.14:03:37.95#ibcon#read 3, iclass 33, count 0 2006.257.14:03:37.95#ibcon#about to read 4, iclass 33, count 0 2006.257.14:03:37.95#ibcon#read 4, iclass 33, count 0 2006.257.14:03:37.95#ibcon#about to read 5, iclass 33, count 0 2006.257.14:03:37.95#ibcon#read 5, iclass 33, count 0 2006.257.14:03:37.95#ibcon#about to read 6, iclass 33, count 0 2006.257.14:03:37.95#ibcon#read 6, iclass 33, count 0 2006.257.14:03:37.95#ibcon#end of sib2, iclass 33, count 0 2006.257.14:03:37.95#ibcon#*after write, iclass 33, count 0 2006.257.14:03:37.95#ibcon#*before return 0, iclass 33, count 0 2006.257.14:03:37.95#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:37.95#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:03:37.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.14:03:37.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.14:03:37.95$vck44/vblo=3,649.99 2006.257.14:03:37.95#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.14:03:37.95#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.14:03:37.95#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:37.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:37.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:37.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:37.95#ibcon#enter wrdev, iclass 35, count 0 2006.257.14:03:37.95#ibcon#first serial, iclass 35, count 0 2006.257.14:03:37.95#ibcon#enter sib2, iclass 35, count 0 2006.257.14:03:37.95#ibcon#flushed, iclass 35, count 0 2006.257.14:03:37.95#ibcon#about to write, iclass 35, count 0 2006.257.14:03:37.95#ibcon#wrote, iclass 35, count 0 2006.257.14:03:37.95#ibcon#about to read 3, iclass 35, count 0 2006.257.14:03:37.97#ibcon#read 3, iclass 35, count 0 2006.257.14:03:37.97#ibcon#about to read 4, iclass 35, count 0 2006.257.14:03:37.97#ibcon#read 4, iclass 35, count 0 2006.257.14:03:37.97#ibcon#about to read 5, iclass 35, count 0 2006.257.14:03:37.97#ibcon#read 5, iclass 35, count 0 2006.257.14:03:37.97#ibcon#about to read 6, iclass 35, count 0 2006.257.14:03:37.97#ibcon#read 6, iclass 35, count 0 2006.257.14:03:37.97#ibcon#end of sib2, iclass 35, count 0 2006.257.14:03:37.97#ibcon#*mode == 0, iclass 35, count 0 2006.257.14:03:37.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.14:03:37.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:03:37.97#ibcon#*before write, iclass 35, count 0 2006.257.14:03:37.97#ibcon#enter sib2, iclass 35, count 0 2006.257.14:03:37.97#ibcon#flushed, iclass 35, count 0 2006.257.14:03:37.97#ibcon#about to write, iclass 35, count 0 2006.257.14:03:37.97#ibcon#wrote, iclass 35, count 0 2006.257.14:03:37.97#ibcon#about to read 3, iclass 35, count 0 2006.257.14:03:38.01#ibcon#read 3, iclass 35, count 0 2006.257.14:03:38.01#ibcon#about to read 4, iclass 35, count 0 2006.257.14:03:38.01#ibcon#read 4, iclass 35, count 0 2006.257.14:03:38.01#ibcon#about to read 5, iclass 35, count 0 2006.257.14:03:38.01#ibcon#read 5, iclass 35, count 0 2006.257.14:03:38.01#ibcon#about to read 6, iclass 35, count 0 2006.257.14:03:38.01#ibcon#read 6, iclass 35, count 0 2006.257.14:03:38.01#ibcon#end of sib2, iclass 35, count 0 2006.257.14:03:38.01#ibcon#*after write, iclass 35, count 0 2006.257.14:03:38.01#ibcon#*before return 0, iclass 35, count 0 2006.257.14:03:38.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:38.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:03:38.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.14:03:38.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.14:03:38.01$vck44/vb=3,4 2006.257.14:03:38.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.14:03:38.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.14:03:38.01#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:38.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:38.07#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:38.07#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:38.07#ibcon#enter wrdev, iclass 37, count 2 2006.257.14:03:38.07#ibcon#first serial, iclass 37, count 2 2006.257.14:03:38.07#ibcon#enter sib2, iclass 37, count 2 2006.257.14:03:38.07#ibcon#flushed, iclass 37, count 2 2006.257.14:03:38.07#ibcon#about to write, iclass 37, count 2 2006.257.14:03:38.07#ibcon#wrote, iclass 37, count 2 2006.257.14:03:38.07#ibcon#about to read 3, iclass 37, count 2 2006.257.14:03:38.09#ibcon#read 3, iclass 37, count 2 2006.257.14:03:38.09#ibcon#about to read 4, iclass 37, count 2 2006.257.14:03:38.09#ibcon#read 4, iclass 37, count 2 2006.257.14:03:38.09#ibcon#about to read 5, iclass 37, count 2 2006.257.14:03:38.09#ibcon#read 5, iclass 37, count 2 2006.257.14:03:38.09#ibcon#about to read 6, iclass 37, count 2 2006.257.14:03:38.09#ibcon#read 6, iclass 37, count 2 2006.257.14:03:38.09#ibcon#end of sib2, iclass 37, count 2 2006.257.14:03:38.09#ibcon#*mode == 0, iclass 37, count 2 2006.257.14:03:38.09#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.14:03:38.09#ibcon#[27=AT03-04\r\n] 2006.257.14:03:38.09#ibcon#*before write, iclass 37, count 2 2006.257.14:03:38.09#ibcon#enter sib2, iclass 37, count 2 2006.257.14:03:38.09#ibcon#flushed, iclass 37, count 2 2006.257.14:03:38.09#ibcon#about to write, iclass 37, count 2 2006.257.14:03:38.09#ibcon#wrote, iclass 37, count 2 2006.257.14:03:38.09#ibcon#about to read 3, iclass 37, count 2 2006.257.14:03:38.12#ibcon#read 3, iclass 37, count 2 2006.257.14:03:38.12#ibcon#about to read 4, iclass 37, count 2 2006.257.14:03:38.12#ibcon#read 4, iclass 37, count 2 2006.257.14:03:38.12#ibcon#about to read 5, iclass 37, count 2 2006.257.14:03:38.12#ibcon#read 5, iclass 37, count 2 2006.257.14:03:38.12#ibcon#about to read 6, iclass 37, count 2 2006.257.14:03:38.12#ibcon#read 6, iclass 37, count 2 2006.257.14:03:38.12#ibcon#end of sib2, iclass 37, count 2 2006.257.14:03:38.12#ibcon#*after write, iclass 37, count 2 2006.257.14:03:38.12#ibcon#*before return 0, iclass 37, count 2 2006.257.14:03:38.12#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:38.12#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:03:38.12#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.14:03:38.12#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:38.12#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:38.24#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:38.24#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:38.24#ibcon#enter wrdev, iclass 37, count 0 2006.257.14:03:38.24#ibcon#first serial, iclass 37, count 0 2006.257.14:03:38.24#ibcon#enter sib2, iclass 37, count 0 2006.257.14:03:38.24#ibcon#flushed, iclass 37, count 0 2006.257.14:03:38.24#ibcon#about to write, iclass 37, count 0 2006.257.14:03:38.24#ibcon#wrote, iclass 37, count 0 2006.257.14:03:38.24#ibcon#about to read 3, iclass 37, count 0 2006.257.14:03:38.26#ibcon#read 3, iclass 37, count 0 2006.257.14:03:38.26#ibcon#about to read 4, iclass 37, count 0 2006.257.14:03:38.26#ibcon#read 4, iclass 37, count 0 2006.257.14:03:38.26#ibcon#about to read 5, iclass 37, count 0 2006.257.14:03:38.26#ibcon#read 5, iclass 37, count 0 2006.257.14:03:38.26#ibcon#about to read 6, iclass 37, count 0 2006.257.14:03:38.26#ibcon#read 6, iclass 37, count 0 2006.257.14:03:38.26#ibcon#end of sib2, iclass 37, count 0 2006.257.14:03:38.26#ibcon#*mode == 0, iclass 37, count 0 2006.257.14:03:38.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.14:03:38.26#ibcon#[27=USB\r\n] 2006.257.14:03:38.26#ibcon#*before write, iclass 37, count 0 2006.257.14:03:38.26#ibcon#enter sib2, iclass 37, count 0 2006.257.14:03:38.26#ibcon#flushed, iclass 37, count 0 2006.257.14:03:38.26#ibcon#about to write, iclass 37, count 0 2006.257.14:03:38.26#ibcon#wrote, iclass 37, count 0 2006.257.14:03:38.26#ibcon#about to read 3, iclass 37, count 0 2006.257.14:03:38.29#ibcon#read 3, iclass 37, count 0 2006.257.14:03:38.29#ibcon#about to read 4, iclass 37, count 0 2006.257.14:03:38.29#ibcon#read 4, iclass 37, count 0 2006.257.14:03:38.29#ibcon#about to read 5, iclass 37, count 0 2006.257.14:03:38.29#ibcon#read 5, iclass 37, count 0 2006.257.14:03:38.29#ibcon#about to read 6, iclass 37, count 0 2006.257.14:03:38.29#ibcon#read 6, iclass 37, count 0 2006.257.14:03:38.29#ibcon#end of sib2, iclass 37, count 0 2006.257.14:03:38.29#ibcon#*after write, iclass 37, count 0 2006.257.14:03:38.29#ibcon#*before return 0, iclass 37, count 0 2006.257.14:03:38.29#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:38.29#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:03:38.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.14:03:38.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.14:03:38.29$vck44/vblo=4,679.99 2006.257.14:03:38.29#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.14:03:38.29#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.14:03:38.29#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:38.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:38.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:38.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:38.29#ibcon#enter wrdev, iclass 39, count 0 2006.257.14:03:38.29#ibcon#first serial, iclass 39, count 0 2006.257.14:03:38.29#ibcon#enter sib2, iclass 39, count 0 2006.257.14:03:38.29#ibcon#flushed, iclass 39, count 0 2006.257.14:03:38.29#ibcon#about to write, iclass 39, count 0 2006.257.14:03:38.29#ibcon#wrote, iclass 39, count 0 2006.257.14:03:38.29#ibcon#about to read 3, iclass 39, count 0 2006.257.14:03:39.14#ibcon#read 3, iclass 39, count 0 2006.257.14:03:39.14#ibcon#about to read 4, iclass 39, count 0 2006.257.14:03:39.14#ibcon#read 4, iclass 39, count 0 2006.257.14:03:39.14#ibcon#about to read 5, iclass 39, count 0 2006.257.14:03:39.14#ibcon#read 5, iclass 39, count 0 2006.257.14:03:39.14#ibcon#about to read 6, iclass 39, count 0 2006.257.14:03:39.14#ibcon#read 6, iclass 39, count 0 2006.257.14:03:39.14#ibcon#end of sib2, iclass 39, count 0 2006.257.14:03:39.14#ibcon#*mode == 0, iclass 39, count 0 2006.257.14:03:39.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.14:03:39.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:03:39.14#ibcon#*before write, iclass 39, count 0 2006.257.14:03:39.14#ibcon#enter sib2, iclass 39, count 0 2006.257.14:03:39.14#ibcon#flushed, iclass 39, count 0 2006.257.14:03:39.14#ibcon#about to write, iclass 39, count 0 2006.257.14:03:39.14#ibcon#wrote, iclass 39, count 0 2006.257.14:03:39.14#ibcon#about to read 3, iclass 39, count 0 2006.257.14:03:39.18#ibcon#read 3, iclass 39, count 0 2006.257.14:03:39.18#ibcon#about to read 4, iclass 39, count 0 2006.257.14:03:39.18#ibcon#read 4, iclass 39, count 0 2006.257.14:03:39.18#ibcon#about to read 5, iclass 39, count 0 2006.257.14:03:39.18#ibcon#read 5, iclass 39, count 0 2006.257.14:03:39.18#ibcon#about to read 6, iclass 39, count 0 2006.257.14:03:39.18#ibcon#read 6, iclass 39, count 0 2006.257.14:03:39.18#ibcon#end of sib2, iclass 39, count 0 2006.257.14:03:39.18#ibcon#*after write, iclass 39, count 0 2006.257.14:03:39.18#ibcon#*before return 0, iclass 39, count 0 2006.257.14:03:39.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:39.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:03:39.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.14:03:39.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.14:03:39.18$vck44/vb=4,5 2006.257.14:03:39.18#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.14:03:39.18#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.14:03:39.18#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:39.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:39.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:39.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:39.18#ibcon#enter wrdev, iclass 3, count 2 2006.257.14:03:39.18#ibcon#first serial, iclass 3, count 2 2006.257.14:03:39.18#ibcon#enter sib2, iclass 3, count 2 2006.257.14:03:39.18#ibcon#flushed, iclass 3, count 2 2006.257.14:03:39.18#ibcon#about to write, iclass 3, count 2 2006.257.14:03:39.18#ibcon#wrote, iclass 3, count 2 2006.257.14:03:39.18#ibcon#about to read 3, iclass 3, count 2 2006.257.14:03:39.20#ibcon#read 3, iclass 3, count 2 2006.257.14:03:39.20#ibcon#about to read 4, iclass 3, count 2 2006.257.14:03:39.20#ibcon#read 4, iclass 3, count 2 2006.257.14:03:39.20#ibcon#about to read 5, iclass 3, count 2 2006.257.14:03:39.20#ibcon#read 5, iclass 3, count 2 2006.257.14:03:39.20#ibcon#about to read 6, iclass 3, count 2 2006.257.14:03:39.20#ibcon#read 6, iclass 3, count 2 2006.257.14:03:39.20#ibcon#end of sib2, iclass 3, count 2 2006.257.14:03:39.20#ibcon#*mode == 0, iclass 3, count 2 2006.257.14:03:39.20#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.14:03:39.20#ibcon#[27=AT04-05\r\n] 2006.257.14:03:39.20#ibcon#*before write, iclass 3, count 2 2006.257.14:03:39.20#ibcon#enter sib2, iclass 3, count 2 2006.257.14:03:39.20#ibcon#flushed, iclass 3, count 2 2006.257.14:03:39.20#ibcon#about to write, iclass 3, count 2 2006.257.14:03:39.20#ibcon#wrote, iclass 3, count 2 2006.257.14:03:39.20#ibcon#about to read 3, iclass 3, count 2 2006.257.14:03:39.23#ibcon#read 3, iclass 3, count 2 2006.257.14:03:39.23#ibcon#about to read 4, iclass 3, count 2 2006.257.14:03:39.23#ibcon#read 4, iclass 3, count 2 2006.257.14:03:39.23#ibcon#about to read 5, iclass 3, count 2 2006.257.14:03:39.23#ibcon#read 5, iclass 3, count 2 2006.257.14:03:39.23#ibcon#about to read 6, iclass 3, count 2 2006.257.14:03:39.23#ibcon#read 6, iclass 3, count 2 2006.257.14:03:39.23#ibcon#end of sib2, iclass 3, count 2 2006.257.14:03:39.23#ibcon#*after write, iclass 3, count 2 2006.257.14:03:39.23#ibcon#*before return 0, iclass 3, count 2 2006.257.14:03:39.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:39.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:03:39.23#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.14:03:39.23#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:39.23#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:39.35#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:39.35#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:39.35#ibcon#enter wrdev, iclass 3, count 0 2006.257.14:03:39.35#ibcon#first serial, iclass 3, count 0 2006.257.14:03:39.35#ibcon#enter sib2, iclass 3, count 0 2006.257.14:03:39.35#ibcon#flushed, iclass 3, count 0 2006.257.14:03:39.35#ibcon#about to write, iclass 3, count 0 2006.257.14:03:39.35#ibcon#wrote, iclass 3, count 0 2006.257.14:03:39.35#ibcon#about to read 3, iclass 3, count 0 2006.257.14:03:39.37#ibcon#read 3, iclass 3, count 0 2006.257.14:03:39.37#ibcon#about to read 4, iclass 3, count 0 2006.257.14:03:39.37#ibcon#read 4, iclass 3, count 0 2006.257.14:03:39.37#ibcon#about to read 5, iclass 3, count 0 2006.257.14:03:39.37#ibcon#read 5, iclass 3, count 0 2006.257.14:03:39.37#ibcon#about to read 6, iclass 3, count 0 2006.257.14:03:39.37#ibcon#read 6, iclass 3, count 0 2006.257.14:03:39.37#ibcon#end of sib2, iclass 3, count 0 2006.257.14:03:39.37#ibcon#*mode == 0, iclass 3, count 0 2006.257.14:03:39.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.14:03:39.37#ibcon#[27=USB\r\n] 2006.257.14:03:39.37#ibcon#*before write, iclass 3, count 0 2006.257.14:03:39.37#ibcon#enter sib2, iclass 3, count 0 2006.257.14:03:39.37#ibcon#flushed, iclass 3, count 0 2006.257.14:03:39.37#ibcon#about to write, iclass 3, count 0 2006.257.14:03:39.37#ibcon#wrote, iclass 3, count 0 2006.257.14:03:39.37#ibcon#about to read 3, iclass 3, count 0 2006.257.14:03:39.40#ibcon#read 3, iclass 3, count 0 2006.257.14:03:39.40#ibcon#about to read 4, iclass 3, count 0 2006.257.14:03:39.40#ibcon#read 4, iclass 3, count 0 2006.257.14:03:39.40#ibcon#about to read 5, iclass 3, count 0 2006.257.14:03:39.40#ibcon#read 5, iclass 3, count 0 2006.257.14:03:39.40#ibcon#about to read 6, iclass 3, count 0 2006.257.14:03:39.40#ibcon#read 6, iclass 3, count 0 2006.257.14:03:39.40#ibcon#end of sib2, iclass 3, count 0 2006.257.14:03:39.40#ibcon#*after write, iclass 3, count 0 2006.257.14:03:39.40#ibcon#*before return 0, iclass 3, count 0 2006.257.14:03:39.40#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:39.40#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:03:39.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.14:03:39.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.14:03:39.40$vck44/vblo=5,709.99 2006.257.14:03:39.40#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.14:03:39.40#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.14:03:39.40#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:39.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:39.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:39.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:39.40#ibcon#enter wrdev, iclass 5, count 0 2006.257.14:03:39.40#ibcon#first serial, iclass 5, count 0 2006.257.14:03:39.40#ibcon#enter sib2, iclass 5, count 0 2006.257.14:03:39.40#ibcon#flushed, iclass 5, count 0 2006.257.14:03:39.40#ibcon#about to write, iclass 5, count 0 2006.257.14:03:39.40#ibcon#wrote, iclass 5, count 0 2006.257.14:03:39.40#ibcon#about to read 3, iclass 5, count 0 2006.257.14:03:39.42#ibcon#read 3, iclass 5, count 0 2006.257.14:03:39.42#ibcon#about to read 4, iclass 5, count 0 2006.257.14:03:39.42#ibcon#read 4, iclass 5, count 0 2006.257.14:03:39.42#ibcon#about to read 5, iclass 5, count 0 2006.257.14:03:39.42#ibcon#read 5, iclass 5, count 0 2006.257.14:03:39.42#ibcon#about to read 6, iclass 5, count 0 2006.257.14:03:39.42#ibcon#read 6, iclass 5, count 0 2006.257.14:03:39.42#ibcon#end of sib2, iclass 5, count 0 2006.257.14:03:39.42#ibcon#*mode == 0, iclass 5, count 0 2006.257.14:03:39.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.14:03:39.42#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:03:39.42#ibcon#*before write, iclass 5, count 0 2006.257.14:03:39.42#ibcon#enter sib2, iclass 5, count 0 2006.257.14:03:39.42#ibcon#flushed, iclass 5, count 0 2006.257.14:03:39.42#ibcon#about to write, iclass 5, count 0 2006.257.14:03:39.42#ibcon#wrote, iclass 5, count 0 2006.257.14:03:39.42#ibcon#about to read 3, iclass 5, count 0 2006.257.14:03:39.46#ibcon#read 3, iclass 5, count 0 2006.257.14:03:39.46#ibcon#about to read 4, iclass 5, count 0 2006.257.14:03:39.46#ibcon#read 4, iclass 5, count 0 2006.257.14:03:39.46#ibcon#about to read 5, iclass 5, count 0 2006.257.14:03:39.46#ibcon#read 5, iclass 5, count 0 2006.257.14:03:39.46#ibcon#about to read 6, iclass 5, count 0 2006.257.14:03:39.46#ibcon#read 6, iclass 5, count 0 2006.257.14:03:39.46#ibcon#end of sib2, iclass 5, count 0 2006.257.14:03:39.46#ibcon#*after write, iclass 5, count 0 2006.257.14:03:39.46#ibcon#*before return 0, iclass 5, count 0 2006.257.14:03:39.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:39.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:03:39.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.14:03:39.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.14:03:39.46$vck44/vb=5,4 2006.257.14:03:39.46#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.14:03:39.46#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.14:03:39.46#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:39.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:39.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:39.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:39.52#ibcon#enter wrdev, iclass 7, count 2 2006.257.14:03:39.52#ibcon#first serial, iclass 7, count 2 2006.257.14:03:39.52#ibcon#enter sib2, iclass 7, count 2 2006.257.14:03:39.52#ibcon#flushed, iclass 7, count 2 2006.257.14:03:39.52#ibcon#about to write, iclass 7, count 2 2006.257.14:03:39.52#ibcon#wrote, iclass 7, count 2 2006.257.14:03:39.52#ibcon#about to read 3, iclass 7, count 2 2006.257.14:03:39.54#ibcon#read 3, iclass 7, count 2 2006.257.14:03:39.54#ibcon#about to read 4, iclass 7, count 2 2006.257.14:03:39.54#ibcon#read 4, iclass 7, count 2 2006.257.14:03:39.54#ibcon#about to read 5, iclass 7, count 2 2006.257.14:03:39.54#ibcon#read 5, iclass 7, count 2 2006.257.14:03:39.54#ibcon#about to read 6, iclass 7, count 2 2006.257.14:03:39.54#ibcon#read 6, iclass 7, count 2 2006.257.14:03:39.54#ibcon#end of sib2, iclass 7, count 2 2006.257.14:03:39.54#ibcon#*mode == 0, iclass 7, count 2 2006.257.14:03:39.54#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.14:03:39.54#ibcon#[27=AT05-04\r\n] 2006.257.14:03:39.54#ibcon#*before write, iclass 7, count 2 2006.257.14:03:39.54#ibcon#enter sib2, iclass 7, count 2 2006.257.14:03:39.54#ibcon#flushed, iclass 7, count 2 2006.257.14:03:39.54#ibcon#about to write, iclass 7, count 2 2006.257.14:03:39.54#ibcon#wrote, iclass 7, count 2 2006.257.14:03:39.54#ibcon#about to read 3, iclass 7, count 2 2006.257.14:03:39.57#ibcon#read 3, iclass 7, count 2 2006.257.14:03:39.57#ibcon#about to read 4, iclass 7, count 2 2006.257.14:03:39.57#ibcon#read 4, iclass 7, count 2 2006.257.14:03:39.57#ibcon#about to read 5, iclass 7, count 2 2006.257.14:03:39.57#ibcon#read 5, iclass 7, count 2 2006.257.14:03:39.57#ibcon#about to read 6, iclass 7, count 2 2006.257.14:03:39.57#ibcon#read 6, iclass 7, count 2 2006.257.14:03:39.57#ibcon#end of sib2, iclass 7, count 2 2006.257.14:03:39.57#ibcon#*after write, iclass 7, count 2 2006.257.14:03:39.57#ibcon#*before return 0, iclass 7, count 2 2006.257.14:03:39.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:39.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:03:39.57#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.14:03:39.57#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:39.57#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:39.69#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:39.69#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:39.69#ibcon#enter wrdev, iclass 7, count 0 2006.257.14:03:39.69#ibcon#first serial, iclass 7, count 0 2006.257.14:03:39.69#ibcon#enter sib2, iclass 7, count 0 2006.257.14:03:39.69#ibcon#flushed, iclass 7, count 0 2006.257.14:03:39.69#ibcon#about to write, iclass 7, count 0 2006.257.14:03:39.69#ibcon#wrote, iclass 7, count 0 2006.257.14:03:39.69#ibcon#about to read 3, iclass 7, count 0 2006.257.14:03:39.71#ibcon#read 3, iclass 7, count 0 2006.257.14:03:39.71#ibcon#about to read 4, iclass 7, count 0 2006.257.14:03:39.71#ibcon#read 4, iclass 7, count 0 2006.257.14:03:39.71#ibcon#about to read 5, iclass 7, count 0 2006.257.14:03:39.71#ibcon#read 5, iclass 7, count 0 2006.257.14:03:39.71#ibcon#about to read 6, iclass 7, count 0 2006.257.14:03:39.71#ibcon#read 6, iclass 7, count 0 2006.257.14:03:39.71#ibcon#end of sib2, iclass 7, count 0 2006.257.14:03:39.71#ibcon#*mode == 0, iclass 7, count 0 2006.257.14:03:39.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.14:03:39.71#ibcon#[27=USB\r\n] 2006.257.14:03:39.71#ibcon#*before write, iclass 7, count 0 2006.257.14:03:39.71#ibcon#enter sib2, iclass 7, count 0 2006.257.14:03:39.71#ibcon#flushed, iclass 7, count 0 2006.257.14:03:39.71#ibcon#about to write, iclass 7, count 0 2006.257.14:03:39.71#ibcon#wrote, iclass 7, count 0 2006.257.14:03:39.71#ibcon#about to read 3, iclass 7, count 0 2006.257.14:03:39.74#ibcon#read 3, iclass 7, count 0 2006.257.14:03:39.74#ibcon#about to read 4, iclass 7, count 0 2006.257.14:03:39.74#ibcon#read 4, iclass 7, count 0 2006.257.14:03:39.74#ibcon#about to read 5, iclass 7, count 0 2006.257.14:03:39.74#ibcon#read 5, iclass 7, count 0 2006.257.14:03:39.74#ibcon#about to read 6, iclass 7, count 0 2006.257.14:03:39.74#ibcon#read 6, iclass 7, count 0 2006.257.14:03:39.74#ibcon#end of sib2, iclass 7, count 0 2006.257.14:03:39.74#ibcon#*after write, iclass 7, count 0 2006.257.14:03:39.74#ibcon#*before return 0, iclass 7, count 0 2006.257.14:03:39.74#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:39.74#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:03:39.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.14:03:39.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.14:03:39.74$vck44/vblo=6,719.99 2006.257.14:03:39.74#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.14:03:39.74#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.14:03:39.74#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:39.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:39.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:39.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:39.74#ibcon#enter wrdev, iclass 11, count 0 2006.257.14:03:39.74#ibcon#first serial, iclass 11, count 0 2006.257.14:03:39.74#ibcon#enter sib2, iclass 11, count 0 2006.257.14:03:39.74#ibcon#flushed, iclass 11, count 0 2006.257.14:03:39.74#ibcon#about to write, iclass 11, count 0 2006.257.14:03:39.74#ibcon#wrote, iclass 11, count 0 2006.257.14:03:39.74#ibcon#about to read 3, iclass 11, count 0 2006.257.14:03:39.76#ibcon#read 3, iclass 11, count 0 2006.257.14:03:39.76#ibcon#about to read 4, iclass 11, count 0 2006.257.14:03:39.76#ibcon#read 4, iclass 11, count 0 2006.257.14:03:39.76#ibcon#about to read 5, iclass 11, count 0 2006.257.14:03:39.76#ibcon#read 5, iclass 11, count 0 2006.257.14:03:39.76#ibcon#about to read 6, iclass 11, count 0 2006.257.14:03:39.76#ibcon#read 6, iclass 11, count 0 2006.257.14:03:39.76#ibcon#end of sib2, iclass 11, count 0 2006.257.14:03:39.76#ibcon#*mode == 0, iclass 11, count 0 2006.257.14:03:39.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.14:03:39.76#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:03:39.76#ibcon#*before write, iclass 11, count 0 2006.257.14:03:39.76#ibcon#enter sib2, iclass 11, count 0 2006.257.14:03:39.76#ibcon#flushed, iclass 11, count 0 2006.257.14:03:39.76#ibcon#about to write, iclass 11, count 0 2006.257.14:03:39.76#ibcon#wrote, iclass 11, count 0 2006.257.14:03:39.76#ibcon#about to read 3, iclass 11, count 0 2006.257.14:03:39.80#ibcon#read 3, iclass 11, count 0 2006.257.14:03:39.80#ibcon#about to read 4, iclass 11, count 0 2006.257.14:03:39.80#ibcon#read 4, iclass 11, count 0 2006.257.14:03:39.80#ibcon#about to read 5, iclass 11, count 0 2006.257.14:03:39.80#ibcon#read 5, iclass 11, count 0 2006.257.14:03:39.80#ibcon#about to read 6, iclass 11, count 0 2006.257.14:03:39.80#ibcon#read 6, iclass 11, count 0 2006.257.14:03:39.80#ibcon#end of sib2, iclass 11, count 0 2006.257.14:03:39.80#ibcon#*after write, iclass 11, count 0 2006.257.14:03:39.80#ibcon#*before return 0, iclass 11, count 0 2006.257.14:03:39.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:39.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:03:39.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.14:03:39.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.14:03:39.80$vck44/vb=6,4 2006.257.14:03:39.80#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.14:03:39.80#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.14:03:39.80#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:39.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:39.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:39.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:39.86#ibcon#enter wrdev, iclass 13, count 2 2006.257.14:03:39.86#ibcon#first serial, iclass 13, count 2 2006.257.14:03:39.86#ibcon#enter sib2, iclass 13, count 2 2006.257.14:03:39.86#ibcon#flushed, iclass 13, count 2 2006.257.14:03:39.86#ibcon#about to write, iclass 13, count 2 2006.257.14:03:39.86#ibcon#wrote, iclass 13, count 2 2006.257.14:03:39.86#ibcon#about to read 3, iclass 13, count 2 2006.257.14:03:39.88#ibcon#read 3, iclass 13, count 2 2006.257.14:03:39.88#ibcon#about to read 4, iclass 13, count 2 2006.257.14:03:39.88#ibcon#read 4, iclass 13, count 2 2006.257.14:03:39.88#ibcon#about to read 5, iclass 13, count 2 2006.257.14:03:39.88#ibcon#read 5, iclass 13, count 2 2006.257.14:03:39.88#ibcon#about to read 6, iclass 13, count 2 2006.257.14:03:39.88#ibcon#read 6, iclass 13, count 2 2006.257.14:03:39.88#ibcon#end of sib2, iclass 13, count 2 2006.257.14:03:39.88#ibcon#*mode == 0, iclass 13, count 2 2006.257.14:03:39.88#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.14:03:39.88#ibcon#[27=AT06-04\r\n] 2006.257.14:03:39.88#ibcon#*before write, iclass 13, count 2 2006.257.14:03:39.88#ibcon#enter sib2, iclass 13, count 2 2006.257.14:03:39.88#ibcon#flushed, iclass 13, count 2 2006.257.14:03:39.88#ibcon#about to write, iclass 13, count 2 2006.257.14:03:39.88#ibcon#wrote, iclass 13, count 2 2006.257.14:03:39.88#ibcon#about to read 3, iclass 13, count 2 2006.257.14:03:39.91#ibcon#read 3, iclass 13, count 2 2006.257.14:03:39.91#ibcon#about to read 4, iclass 13, count 2 2006.257.14:03:39.91#ibcon#read 4, iclass 13, count 2 2006.257.14:03:39.91#ibcon#about to read 5, iclass 13, count 2 2006.257.14:03:39.91#ibcon#read 5, iclass 13, count 2 2006.257.14:03:39.91#ibcon#about to read 6, iclass 13, count 2 2006.257.14:03:39.91#ibcon#read 6, iclass 13, count 2 2006.257.14:03:39.91#ibcon#end of sib2, iclass 13, count 2 2006.257.14:03:39.91#ibcon#*after write, iclass 13, count 2 2006.257.14:03:39.91#ibcon#*before return 0, iclass 13, count 2 2006.257.14:03:39.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:39.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:03:39.91#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.14:03:39.91#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:39.91#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:40.03#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:40.03#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:40.03#ibcon#enter wrdev, iclass 13, count 0 2006.257.14:03:40.03#ibcon#first serial, iclass 13, count 0 2006.257.14:03:40.03#ibcon#enter sib2, iclass 13, count 0 2006.257.14:03:40.03#ibcon#flushed, iclass 13, count 0 2006.257.14:03:40.03#ibcon#about to write, iclass 13, count 0 2006.257.14:03:40.03#ibcon#wrote, iclass 13, count 0 2006.257.14:03:40.03#ibcon#about to read 3, iclass 13, count 0 2006.257.14:03:40.05#ibcon#read 3, iclass 13, count 0 2006.257.14:03:40.05#ibcon#about to read 4, iclass 13, count 0 2006.257.14:03:40.05#ibcon#read 4, iclass 13, count 0 2006.257.14:03:40.05#ibcon#about to read 5, iclass 13, count 0 2006.257.14:03:40.05#ibcon#read 5, iclass 13, count 0 2006.257.14:03:40.05#ibcon#about to read 6, iclass 13, count 0 2006.257.14:03:40.05#ibcon#read 6, iclass 13, count 0 2006.257.14:03:40.05#ibcon#end of sib2, iclass 13, count 0 2006.257.14:03:40.05#ibcon#*mode == 0, iclass 13, count 0 2006.257.14:03:40.05#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.14:03:40.05#ibcon#[27=USB\r\n] 2006.257.14:03:40.05#ibcon#*before write, iclass 13, count 0 2006.257.14:03:40.05#ibcon#enter sib2, iclass 13, count 0 2006.257.14:03:40.05#ibcon#flushed, iclass 13, count 0 2006.257.14:03:40.05#ibcon#about to write, iclass 13, count 0 2006.257.14:03:40.05#ibcon#wrote, iclass 13, count 0 2006.257.14:03:40.05#ibcon#about to read 3, iclass 13, count 0 2006.257.14:03:40.08#ibcon#read 3, iclass 13, count 0 2006.257.14:03:40.08#ibcon#about to read 4, iclass 13, count 0 2006.257.14:03:40.08#ibcon#read 4, iclass 13, count 0 2006.257.14:03:40.08#ibcon#about to read 5, iclass 13, count 0 2006.257.14:03:40.08#ibcon#read 5, iclass 13, count 0 2006.257.14:03:40.08#ibcon#about to read 6, iclass 13, count 0 2006.257.14:03:40.08#ibcon#read 6, iclass 13, count 0 2006.257.14:03:40.08#ibcon#end of sib2, iclass 13, count 0 2006.257.14:03:40.08#ibcon#*after write, iclass 13, count 0 2006.257.14:03:40.08#ibcon#*before return 0, iclass 13, count 0 2006.257.14:03:40.08#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:40.08#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:03:40.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.14:03:40.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.14:03:40.08$vck44/vblo=7,734.99 2006.257.14:03:40.08#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.14:03:40.08#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.14:03:40.08#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:40.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:40.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:40.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:40.08#ibcon#enter wrdev, iclass 15, count 0 2006.257.14:03:40.08#ibcon#first serial, iclass 15, count 0 2006.257.14:03:40.08#ibcon#enter sib2, iclass 15, count 0 2006.257.14:03:40.08#ibcon#flushed, iclass 15, count 0 2006.257.14:03:40.08#ibcon#about to write, iclass 15, count 0 2006.257.14:03:40.08#ibcon#wrote, iclass 15, count 0 2006.257.14:03:40.08#ibcon#about to read 3, iclass 15, count 0 2006.257.14:03:40.10#ibcon#read 3, iclass 15, count 0 2006.257.14:03:40.10#ibcon#about to read 4, iclass 15, count 0 2006.257.14:03:40.10#ibcon#read 4, iclass 15, count 0 2006.257.14:03:40.10#ibcon#about to read 5, iclass 15, count 0 2006.257.14:03:40.10#ibcon#read 5, iclass 15, count 0 2006.257.14:03:40.10#ibcon#about to read 6, iclass 15, count 0 2006.257.14:03:40.10#ibcon#read 6, iclass 15, count 0 2006.257.14:03:40.10#ibcon#end of sib2, iclass 15, count 0 2006.257.14:03:40.10#ibcon#*mode == 0, iclass 15, count 0 2006.257.14:03:40.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.14:03:40.10#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:03:40.10#ibcon#*before write, iclass 15, count 0 2006.257.14:03:40.10#ibcon#enter sib2, iclass 15, count 0 2006.257.14:03:40.10#ibcon#flushed, iclass 15, count 0 2006.257.14:03:40.10#ibcon#about to write, iclass 15, count 0 2006.257.14:03:40.10#ibcon#wrote, iclass 15, count 0 2006.257.14:03:40.10#ibcon#about to read 3, iclass 15, count 0 2006.257.14:03:40.14#ibcon#read 3, iclass 15, count 0 2006.257.14:03:40.14#ibcon#about to read 4, iclass 15, count 0 2006.257.14:03:40.14#ibcon#read 4, iclass 15, count 0 2006.257.14:03:40.14#ibcon#about to read 5, iclass 15, count 0 2006.257.14:03:40.14#ibcon#read 5, iclass 15, count 0 2006.257.14:03:40.14#ibcon#about to read 6, iclass 15, count 0 2006.257.14:03:40.14#ibcon#read 6, iclass 15, count 0 2006.257.14:03:40.14#ibcon#end of sib2, iclass 15, count 0 2006.257.14:03:40.14#ibcon#*after write, iclass 15, count 0 2006.257.14:03:40.14#ibcon#*before return 0, iclass 15, count 0 2006.257.14:03:40.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:40.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:03:40.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.14:03:40.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.14:03:40.14$vck44/vb=7,4 2006.257.14:03:40.14#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.14:03:40.14#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.14:03:40.14#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:40.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:40.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:40.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:40.20#ibcon#enter wrdev, iclass 17, count 2 2006.257.14:03:40.20#ibcon#first serial, iclass 17, count 2 2006.257.14:03:40.20#ibcon#enter sib2, iclass 17, count 2 2006.257.14:03:40.20#ibcon#flushed, iclass 17, count 2 2006.257.14:03:40.20#ibcon#about to write, iclass 17, count 2 2006.257.14:03:40.20#ibcon#wrote, iclass 17, count 2 2006.257.14:03:40.20#ibcon#about to read 3, iclass 17, count 2 2006.257.14:03:40.22#ibcon#read 3, iclass 17, count 2 2006.257.14:03:40.22#ibcon#about to read 4, iclass 17, count 2 2006.257.14:03:40.22#ibcon#read 4, iclass 17, count 2 2006.257.14:03:40.22#ibcon#about to read 5, iclass 17, count 2 2006.257.14:03:40.22#ibcon#read 5, iclass 17, count 2 2006.257.14:03:40.22#ibcon#about to read 6, iclass 17, count 2 2006.257.14:03:40.22#ibcon#read 6, iclass 17, count 2 2006.257.14:03:40.22#ibcon#end of sib2, iclass 17, count 2 2006.257.14:03:40.22#ibcon#*mode == 0, iclass 17, count 2 2006.257.14:03:40.22#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.14:03:40.22#ibcon#[27=AT07-04\r\n] 2006.257.14:03:40.22#ibcon#*before write, iclass 17, count 2 2006.257.14:03:40.22#ibcon#enter sib2, iclass 17, count 2 2006.257.14:03:40.22#ibcon#flushed, iclass 17, count 2 2006.257.14:03:40.22#ibcon#about to write, iclass 17, count 2 2006.257.14:03:40.22#ibcon#wrote, iclass 17, count 2 2006.257.14:03:40.22#ibcon#about to read 3, iclass 17, count 2 2006.257.14:03:40.25#ibcon#read 3, iclass 17, count 2 2006.257.14:03:40.25#ibcon#about to read 4, iclass 17, count 2 2006.257.14:03:40.25#ibcon#read 4, iclass 17, count 2 2006.257.14:03:41.09#ibcon#about to read 5, iclass 17, count 2 2006.257.14:03:41.09#ibcon#read 5, iclass 17, count 2 2006.257.14:03:41.09#ibcon#about to read 6, iclass 17, count 2 2006.257.14:03:41.09#ibcon#read 6, iclass 17, count 2 2006.257.14:03:41.09#ibcon#end of sib2, iclass 17, count 2 2006.257.14:03:41.09#ibcon#*after write, iclass 17, count 2 2006.257.14:03:41.09#ibcon#*before return 0, iclass 17, count 2 2006.257.14:03:41.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:41.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:03:41.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.14:03:41.10#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:41.10#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:41.21#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:41.21#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:41.21#ibcon#enter wrdev, iclass 17, count 0 2006.257.14:03:41.21#ibcon#first serial, iclass 17, count 0 2006.257.14:03:41.21#ibcon#enter sib2, iclass 17, count 0 2006.257.14:03:41.21#ibcon#flushed, iclass 17, count 0 2006.257.14:03:41.21#ibcon#about to write, iclass 17, count 0 2006.257.14:03:41.21#ibcon#wrote, iclass 17, count 0 2006.257.14:03:41.21#ibcon#about to read 3, iclass 17, count 0 2006.257.14:03:41.23#ibcon#read 3, iclass 17, count 0 2006.257.14:03:41.23#ibcon#about to read 4, iclass 17, count 0 2006.257.14:03:41.23#ibcon#read 4, iclass 17, count 0 2006.257.14:03:41.23#ibcon#about to read 5, iclass 17, count 0 2006.257.14:03:41.23#ibcon#read 5, iclass 17, count 0 2006.257.14:03:41.23#ibcon#about to read 6, iclass 17, count 0 2006.257.14:03:41.23#ibcon#read 6, iclass 17, count 0 2006.257.14:03:41.23#ibcon#end of sib2, iclass 17, count 0 2006.257.14:03:41.23#ibcon#*mode == 0, iclass 17, count 0 2006.257.14:03:41.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.14:03:41.23#ibcon#[27=USB\r\n] 2006.257.14:03:41.23#ibcon#*before write, iclass 17, count 0 2006.257.14:03:41.23#ibcon#enter sib2, iclass 17, count 0 2006.257.14:03:41.23#ibcon#flushed, iclass 17, count 0 2006.257.14:03:41.23#ibcon#about to write, iclass 17, count 0 2006.257.14:03:41.23#ibcon#wrote, iclass 17, count 0 2006.257.14:03:41.23#ibcon#about to read 3, iclass 17, count 0 2006.257.14:03:41.26#ibcon#read 3, iclass 17, count 0 2006.257.14:03:41.26#ibcon#about to read 4, iclass 17, count 0 2006.257.14:03:41.26#ibcon#read 4, iclass 17, count 0 2006.257.14:03:41.26#ibcon#about to read 5, iclass 17, count 0 2006.257.14:03:41.26#ibcon#read 5, iclass 17, count 0 2006.257.14:03:41.26#ibcon#about to read 6, iclass 17, count 0 2006.257.14:03:41.26#ibcon#read 6, iclass 17, count 0 2006.257.14:03:41.26#ibcon#end of sib2, iclass 17, count 0 2006.257.14:03:41.26#ibcon#*after write, iclass 17, count 0 2006.257.14:03:41.26#ibcon#*before return 0, iclass 17, count 0 2006.257.14:03:41.26#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:41.26#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:03:41.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.14:03:41.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.14:03:41.26$vck44/vblo=8,744.99 2006.257.14:03:41.26#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.14:03:41.26#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.14:03:41.26#ibcon#ireg 17 cls_cnt 0 2006.257.14:03:41.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:41.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:41.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:41.26#ibcon#enter wrdev, iclass 19, count 0 2006.257.14:03:41.26#ibcon#first serial, iclass 19, count 0 2006.257.14:03:41.26#ibcon#enter sib2, iclass 19, count 0 2006.257.14:03:41.26#ibcon#flushed, iclass 19, count 0 2006.257.14:03:41.26#ibcon#about to write, iclass 19, count 0 2006.257.14:03:41.26#ibcon#wrote, iclass 19, count 0 2006.257.14:03:41.26#ibcon#about to read 3, iclass 19, count 0 2006.257.14:03:41.28#ibcon#read 3, iclass 19, count 0 2006.257.14:03:41.28#ibcon#about to read 4, iclass 19, count 0 2006.257.14:03:41.28#ibcon#read 4, iclass 19, count 0 2006.257.14:03:41.28#ibcon#about to read 5, iclass 19, count 0 2006.257.14:03:41.28#ibcon#read 5, iclass 19, count 0 2006.257.14:03:41.28#ibcon#about to read 6, iclass 19, count 0 2006.257.14:03:41.28#ibcon#read 6, iclass 19, count 0 2006.257.14:03:41.28#ibcon#end of sib2, iclass 19, count 0 2006.257.14:03:41.28#ibcon#*mode == 0, iclass 19, count 0 2006.257.14:03:41.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.14:03:41.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:03:41.28#ibcon#*before write, iclass 19, count 0 2006.257.14:03:41.28#ibcon#enter sib2, iclass 19, count 0 2006.257.14:03:41.28#ibcon#flushed, iclass 19, count 0 2006.257.14:03:41.28#ibcon#about to write, iclass 19, count 0 2006.257.14:03:41.28#ibcon#wrote, iclass 19, count 0 2006.257.14:03:41.28#ibcon#about to read 3, iclass 19, count 0 2006.257.14:03:41.32#ibcon#read 3, iclass 19, count 0 2006.257.14:03:41.32#ibcon#about to read 4, iclass 19, count 0 2006.257.14:03:41.32#ibcon#read 4, iclass 19, count 0 2006.257.14:03:41.32#ibcon#about to read 5, iclass 19, count 0 2006.257.14:03:41.32#ibcon#read 5, iclass 19, count 0 2006.257.14:03:41.32#ibcon#about to read 6, iclass 19, count 0 2006.257.14:03:41.32#ibcon#read 6, iclass 19, count 0 2006.257.14:03:41.32#ibcon#end of sib2, iclass 19, count 0 2006.257.14:03:41.32#ibcon#*after write, iclass 19, count 0 2006.257.14:03:41.32#ibcon#*before return 0, iclass 19, count 0 2006.257.14:03:41.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:41.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:03:41.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.14:03:41.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.14:03:41.32$vck44/vb=8,4 2006.257.14:03:41.32#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.14:03:41.32#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.14:03:41.32#ibcon#ireg 11 cls_cnt 2 2006.257.14:03:41.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:41.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:41.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:41.38#ibcon#enter wrdev, iclass 21, count 2 2006.257.14:03:41.38#ibcon#first serial, iclass 21, count 2 2006.257.14:03:41.38#ibcon#enter sib2, iclass 21, count 2 2006.257.14:03:41.38#ibcon#flushed, iclass 21, count 2 2006.257.14:03:41.38#ibcon#about to write, iclass 21, count 2 2006.257.14:03:41.38#ibcon#wrote, iclass 21, count 2 2006.257.14:03:41.38#ibcon#about to read 3, iclass 21, count 2 2006.257.14:03:41.40#ibcon#read 3, iclass 21, count 2 2006.257.14:03:41.40#ibcon#about to read 4, iclass 21, count 2 2006.257.14:03:41.40#ibcon#read 4, iclass 21, count 2 2006.257.14:03:41.40#ibcon#about to read 5, iclass 21, count 2 2006.257.14:03:41.40#ibcon#read 5, iclass 21, count 2 2006.257.14:03:41.40#ibcon#about to read 6, iclass 21, count 2 2006.257.14:03:41.40#ibcon#read 6, iclass 21, count 2 2006.257.14:03:41.40#ibcon#end of sib2, iclass 21, count 2 2006.257.14:03:41.40#ibcon#*mode == 0, iclass 21, count 2 2006.257.14:03:41.40#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.14:03:41.40#ibcon#[27=AT08-04\r\n] 2006.257.14:03:41.40#ibcon#*before write, iclass 21, count 2 2006.257.14:03:41.40#ibcon#enter sib2, iclass 21, count 2 2006.257.14:03:41.40#ibcon#flushed, iclass 21, count 2 2006.257.14:03:41.40#ibcon#about to write, iclass 21, count 2 2006.257.14:03:41.40#ibcon#wrote, iclass 21, count 2 2006.257.14:03:41.40#ibcon#about to read 3, iclass 21, count 2 2006.257.14:03:41.43#ibcon#read 3, iclass 21, count 2 2006.257.14:03:41.43#ibcon#about to read 4, iclass 21, count 2 2006.257.14:03:41.43#ibcon#read 4, iclass 21, count 2 2006.257.14:03:41.43#ibcon#about to read 5, iclass 21, count 2 2006.257.14:03:41.43#ibcon#read 5, iclass 21, count 2 2006.257.14:03:41.43#ibcon#about to read 6, iclass 21, count 2 2006.257.14:03:41.43#ibcon#read 6, iclass 21, count 2 2006.257.14:03:41.43#ibcon#end of sib2, iclass 21, count 2 2006.257.14:03:41.43#ibcon#*after write, iclass 21, count 2 2006.257.14:03:41.43#ibcon#*before return 0, iclass 21, count 2 2006.257.14:03:41.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:41.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:03:41.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.14:03:41.43#ibcon#ireg 7 cls_cnt 0 2006.257.14:03:41.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:41.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:41.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:41.55#ibcon#enter wrdev, iclass 21, count 0 2006.257.14:03:41.55#ibcon#first serial, iclass 21, count 0 2006.257.14:03:41.55#ibcon#enter sib2, iclass 21, count 0 2006.257.14:03:41.55#ibcon#flushed, iclass 21, count 0 2006.257.14:03:41.55#ibcon#about to write, iclass 21, count 0 2006.257.14:03:41.55#ibcon#wrote, iclass 21, count 0 2006.257.14:03:41.55#ibcon#about to read 3, iclass 21, count 0 2006.257.14:03:41.57#ibcon#read 3, iclass 21, count 0 2006.257.14:03:41.57#ibcon#about to read 4, iclass 21, count 0 2006.257.14:03:41.57#ibcon#read 4, iclass 21, count 0 2006.257.14:03:41.57#ibcon#about to read 5, iclass 21, count 0 2006.257.14:03:41.57#ibcon#read 5, iclass 21, count 0 2006.257.14:03:41.57#ibcon#about to read 6, iclass 21, count 0 2006.257.14:03:41.57#ibcon#read 6, iclass 21, count 0 2006.257.14:03:41.57#ibcon#end of sib2, iclass 21, count 0 2006.257.14:03:41.57#ibcon#*mode == 0, iclass 21, count 0 2006.257.14:03:41.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.14:03:41.57#ibcon#[27=USB\r\n] 2006.257.14:03:41.57#ibcon#*before write, iclass 21, count 0 2006.257.14:03:41.57#ibcon#enter sib2, iclass 21, count 0 2006.257.14:03:41.57#ibcon#flushed, iclass 21, count 0 2006.257.14:03:41.57#ibcon#about to write, iclass 21, count 0 2006.257.14:03:41.57#ibcon#wrote, iclass 21, count 0 2006.257.14:03:41.57#ibcon#about to read 3, iclass 21, count 0 2006.257.14:03:41.60#ibcon#read 3, iclass 21, count 0 2006.257.14:03:41.60#ibcon#about to read 4, iclass 21, count 0 2006.257.14:03:41.60#ibcon#read 4, iclass 21, count 0 2006.257.14:03:41.60#ibcon#about to read 5, iclass 21, count 0 2006.257.14:03:41.60#ibcon#read 5, iclass 21, count 0 2006.257.14:03:41.60#ibcon#about to read 6, iclass 21, count 0 2006.257.14:03:41.60#ibcon#read 6, iclass 21, count 0 2006.257.14:03:41.60#ibcon#end of sib2, iclass 21, count 0 2006.257.14:03:41.60#ibcon#*after write, iclass 21, count 0 2006.257.14:03:41.60#ibcon#*before return 0, iclass 21, count 0 2006.257.14:03:41.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:41.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:03:41.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.14:03:41.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.14:03:41.60$vck44/vabw=wide 2006.257.14:03:41.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.14:03:41.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.14:03:41.60#ibcon#ireg 8 cls_cnt 0 2006.257.14:03:41.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:41.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:41.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:41.60#ibcon#enter wrdev, iclass 23, count 0 2006.257.14:03:41.60#ibcon#first serial, iclass 23, count 0 2006.257.14:03:41.60#ibcon#enter sib2, iclass 23, count 0 2006.257.14:03:41.60#ibcon#flushed, iclass 23, count 0 2006.257.14:03:41.60#ibcon#about to write, iclass 23, count 0 2006.257.14:03:41.60#ibcon#wrote, iclass 23, count 0 2006.257.14:03:41.60#ibcon#about to read 3, iclass 23, count 0 2006.257.14:03:41.62#ibcon#read 3, iclass 23, count 0 2006.257.14:03:41.62#ibcon#about to read 4, iclass 23, count 0 2006.257.14:03:41.62#ibcon#read 4, iclass 23, count 0 2006.257.14:03:41.62#ibcon#about to read 5, iclass 23, count 0 2006.257.14:03:41.62#ibcon#read 5, iclass 23, count 0 2006.257.14:03:41.62#ibcon#about to read 6, iclass 23, count 0 2006.257.14:03:41.62#ibcon#read 6, iclass 23, count 0 2006.257.14:03:41.62#ibcon#end of sib2, iclass 23, count 0 2006.257.14:03:41.62#ibcon#*mode == 0, iclass 23, count 0 2006.257.14:03:41.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.14:03:41.62#ibcon#[25=BW32\r\n] 2006.257.14:03:41.62#ibcon#*before write, iclass 23, count 0 2006.257.14:03:41.62#ibcon#enter sib2, iclass 23, count 0 2006.257.14:03:41.62#ibcon#flushed, iclass 23, count 0 2006.257.14:03:41.62#ibcon#about to write, iclass 23, count 0 2006.257.14:03:41.62#ibcon#wrote, iclass 23, count 0 2006.257.14:03:41.62#ibcon#about to read 3, iclass 23, count 0 2006.257.14:03:41.65#ibcon#read 3, iclass 23, count 0 2006.257.14:03:41.65#ibcon#about to read 4, iclass 23, count 0 2006.257.14:03:41.65#ibcon#read 4, iclass 23, count 0 2006.257.14:03:41.65#ibcon#about to read 5, iclass 23, count 0 2006.257.14:03:41.65#ibcon#read 5, iclass 23, count 0 2006.257.14:03:41.65#ibcon#about to read 6, iclass 23, count 0 2006.257.14:03:41.65#ibcon#read 6, iclass 23, count 0 2006.257.14:03:41.65#ibcon#end of sib2, iclass 23, count 0 2006.257.14:03:41.65#ibcon#*after write, iclass 23, count 0 2006.257.14:03:41.65#ibcon#*before return 0, iclass 23, count 0 2006.257.14:03:41.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:41.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:03:41.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.14:03:41.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.14:03:41.65$vck44/vbbw=wide 2006.257.14:03:41.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.14:03:41.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.14:03:41.65#ibcon#ireg 8 cls_cnt 0 2006.257.14:03:41.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:03:41.72#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:03:41.72#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:03:41.72#ibcon#enter wrdev, iclass 25, count 0 2006.257.14:03:41.72#ibcon#first serial, iclass 25, count 0 2006.257.14:03:41.72#ibcon#enter sib2, iclass 25, count 0 2006.257.14:03:41.72#ibcon#flushed, iclass 25, count 0 2006.257.14:03:41.72#ibcon#about to write, iclass 25, count 0 2006.257.14:03:41.72#ibcon#wrote, iclass 25, count 0 2006.257.14:03:41.72#ibcon#about to read 3, iclass 25, count 0 2006.257.14:03:41.74#ibcon#read 3, iclass 25, count 0 2006.257.14:03:41.74#ibcon#about to read 4, iclass 25, count 0 2006.257.14:03:41.74#ibcon#read 4, iclass 25, count 0 2006.257.14:03:41.74#ibcon#about to read 5, iclass 25, count 0 2006.257.14:03:41.74#ibcon#read 5, iclass 25, count 0 2006.257.14:03:41.74#ibcon#about to read 6, iclass 25, count 0 2006.257.14:03:41.74#ibcon#read 6, iclass 25, count 0 2006.257.14:03:41.74#ibcon#end of sib2, iclass 25, count 0 2006.257.14:03:41.74#ibcon#*mode == 0, iclass 25, count 0 2006.257.14:03:41.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.14:03:41.74#ibcon#[27=BW32\r\n] 2006.257.14:03:41.74#ibcon#*before write, iclass 25, count 0 2006.257.14:03:41.74#ibcon#enter sib2, iclass 25, count 0 2006.257.14:03:41.74#ibcon#flushed, iclass 25, count 0 2006.257.14:03:41.74#ibcon#about to write, iclass 25, count 0 2006.257.14:03:41.74#ibcon#wrote, iclass 25, count 0 2006.257.14:03:41.74#ibcon#about to read 3, iclass 25, count 0 2006.257.14:03:41.77#ibcon#read 3, iclass 25, count 0 2006.257.14:03:41.77#ibcon#about to read 4, iclass 25, count 0 2006.257.14:03:41.77#ibcon#read 4, iclass 25, count 0 2006.257.14:03:41.77#ibcon#about to read 5, iclass 25, count 0 2006.257.14:03:41.77#ibcon#read 5, iclass 25, count 0 2006.257.14:03:41.77#ibcon#about to read 6, iclass 25, count 0 2006.257.14:03:41.77#ibcon#read 6, iclass 25, count 0 2006.257.14:03:41.77#ibcon#end of sib2, iclass 25, count 0 2006.257.14:03:41.77#ibcon#*after write, iclass 25, count 0 2006.257.14:03:41.77#ibcon#*before return 0, iclass 25, count 0 2006.257.14:03:41.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:03:41.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:03:41.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.14:03:41.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.14:03:41.77$setupk4/ifdk4 2006.257.14:03:41.77$ifdk4/lo= 2006.257.14:03:41.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:03:41.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:03:41.77$ifdk4/patch= 2006.257.14:03:41.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:03:41.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:03:41.77$setupk4/!*+20s 2006.257.14:03:43.10#abcon#<5=/14 1.5 4.2 17.56 971014.0\r\n> 2006.257.14:03:43.12#abcon#{5=INTERFACE CLEAR} 2006.257.14:03:43.18#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:03:52.13#trakl#Source acquired 2006.257.14:03:52.13#flagr#flagr/antenna,acquired 2006.257.14:03:53.16$setupk4/"tpicd 2006.257.14:03:53.16$setupk4/echo=off 2006.257.14:03:53.16$setupk4/xlog=off 2006.257.14:03:53.16:!2006.257.14:04:28 2006.257.14:04:28.00:preob 2006.257.14:04:29.13/onsource/TRACKING 2006.257.14:04:29.13:!2006.257.14:04:38 2006.257.14:04:38.00:"tape 2006.257.14:04:38.00:"st=record 2006.257.14:04:38.00:data_valid=on 2006.257.14:04:38.00:midob 2006.257.14:04:38.13/onsource/TRACKING 2006.257.14:04:38.13/wx/17.55,1014.0,97 2006.257.14:04:38.20/cable/+6.4807E-03 2006.257.14:04:39.29/va/01,08,usb,yes,30,33 2006.257.14:04:39.29/va/02,07,usb,yes,33,33 2006.257.14:04:39.29/va/03,08,usb,yes,29,31 2006.257.14:04:39.29/va/04,07,usb,yes,34,35 2006.257.14:04:39.29/va/05,04,usb,yes,30,31 2006.257.14:04:39.29/va/06,04,usb,yes,34,33 2006.257.14:04:39.29/va/07,04,usb,yes,35,35 2006.257.14:04:39.29/va/08,04,usb,yes,29,35 2006.257.14:04:39.52/valo/01,524.99,yes,locked 2006.257.14:04:39.52/valo/02,534.99,yes,locked 2006.257.14:04:39.52/valo/03,564.99,yes,locked 2006.257.14:04:39.52/valo/04,624.99,yes,locked 2006.257.14:04:39.52/valo/05,734.99,yes,locked 2006.257.14:04:39.52/valo/06,814.99,yes,locked 2006.257.14:04:39.52/valo/07,864.99,yes,locked 2006.257.14:04:39.52/valo/08,884.99,yes,locked 2006.257.14:04:40.61/vb/01,04,usb,yes,30,28 2006.257.14:04:40.61/vb/02,05,usb,yes,28,28 2006.257.14:04:40.61/vb/03,04,usb,yes,29,32 2006.257.14:04:40.61/vb/04,05,usb,yes,29,28 2006.257.14:04:40.61/vb/05,04,usb,yes,26,28 2006.257.14:04:40.61/vb/06,04,usb,yes,30,27 2006.257.14:04:40.61/vb/07,04,usb,yes,30,30 2006.257.14:04:40.61/vb/08,04,usb,yes,27,31 2006.257.14:04:40.84/vblo/01,629.99,yes,locked 2006.257.14:04:40.84/vblo/02,634.99,yes,locked 2006.257.14:04:40.84/vblo/03,649.99,yes,locked 2006.257.14:04:40.84/vblo/04,679.99,yes,locked 2006.257.14:04:40.84/vblo/05,709.99,yes,locked 2006.257.14:04:40.84/vblo/06,719.99,yes,locked 2006.257.14:04:40.84/vblo/07,734.99,yes,locked 2006.257.14:04:40.84/vblo/08,744.99,yes,locked 2006.257.14:04:40.99/vabw/8 2006.257.14:04:41.14/vbbw/8 2006.257.14:04:41.23/xfe/off,on,15.2 2006.257.14:04:41.60/ifatt/23,28,28,28 2006.257.14:04:42.07/fmout-gps/S +4.53E-07 2006.257.14:04:42.11:!2006.257.14:06:28 2006.257.14:06:28.00:data_valid=off 2006.257.14:06:28.00:"et 2006.257.14:06:28.00:!+3s 2006.257.14:06:31.01:"tape 2006.257.14:06:31.01:postob 2006.257.14:06:31.15/cable/+6.4802E-03 2006.257.14:06:31.15/wx/17.53,1014.0,97 2006.257.14:06:32.07/fmout-gps/S +4.52E-07 2006.257.14:06:32.07:scan_name=257-1409,jd0609,80 2006.257.14:06:32.07:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.14:06:33.14#flagr#flagr/antenna,new-source 2006.257.14:06:33.14:checkk5 2006.257.14:06:33.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:06:33.89/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:06:34.28/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:06:34.65/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:06:35.03/chk_obsdata//k5ts1/T2571404??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.14:06:35.42/chk_obsdata//k5ts2/T2571404??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.14:06:35.81/chk_obsdata//k5ts3/T2571404??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.14:06:36.22/chk_obsdata//k5ts4/T2571404??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.14:06:36.91/k5log//k5ts1_log_newline 2006.257.14:06:37.61/k5log//k5ts2_log_newline 2006.257.14:06:38.32/k5log//k5ts3_log_newline 2006.257.14:06:39.01/k5log//k5ts4_log_newline 2006.257.14:06:39.04/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:06:39.04:setupk4=1 2006.257.14:06:39.04$setupk4/echo=on 2006.257.14:06:39.04$setupk4/pcalon 2006.257.14:06:39.04$pcalon/"no phase cal control is implemented here 2006.257.14:06:39.04$setupk4/"tpicd=stop 2006.257.14:06:39.04$setupk4/"rec=synch_on 2006.257.14:06:39.04$setupk4/"rec_mode=128 2006.257.14:06:39.04$setupk4/!* 2006.257.14:06:39.04$setupk4/recpk4 2006.257.14:06:39.04$recpk4/recpatch= 2006.257.14:06:39.04$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:06:39.04$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:06:39.04$setupk4/vck44 2006.257.14:06:39.04$vck44/valo=1,524.99 2006.257.14:06:39.04#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.14:06:39.04#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.14:06:39.04#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:39.04#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:39.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:39.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:39.04#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:06:39.04#ibcon#first serial, iclass 30, count 0 2006.257.14:06:39.04#ibcon#enter sib2, iclass 30, count 0 2006.257.14:06:39.04#ibcon#flushed, iclass 30, count 0 2006.257.14:06:39.04#ibcon#about to write, iclass 30, count 0 2006.257.14:06:39.04#ibcon#wrote, iclass 30, count 0 2006.257.14:06:39.04#ibcon#about to read 3, iclass 30, count 0 2006.257.14:06:39.06#ibcon#read 3, iclass 30, count 0 2006.257.14:06:39.06#ibcon#about to read 4, iclass 30, count 0 2006.257.14:06:39.06#ibcon#read 4, iclass 30, count 0 2006.257.14:06:39.06#ibcon#about to read 5, iclass 30, count 0 2006.257.14:06:39.06#ibcon#read 5, iclass 30, count 0 2006.257.14:06:39.06#ibcon#about to read 6, iclass 30, count 0 2006.257.14:06:39.06#ibcon#read 6, iclass 30, count 0 2006.257.14:06:39.06#ibcon#end of sib2, iclass 30, count 0 2006.257.14:06:39.06#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:06:39.06#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:06:39.06#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:06:39.06#ibcon#*before write, iclass 30, count 0 2006.257.14:06:39.06#ibcon#enter sib2, iclass 30, count 0 2006.257.14:06:39.06#ibcon#flushed, iclass 30, count 0 2006.257.14:06:39.06#ibcon#about to write, iclass 30, count 0 2006.257.14:06:39.06#ibcon#wrote, iclass 30, count 0 2006.257.14:06:39.06#ibcon#about to read 3, iclass 30, count 0 2006.257.14:06:39.11#ibcon#read 3, iclass 30, count 0 2006.257.14:06:39.11#ibcon#about to read 4, iclass 30, count 0 2006.257.14:06:39.11#ibcon#read 4, iclass 30, count 0 2006.257.14:06:39.11#ibcon#about to read 5, iclass 30, count 0 2006.257.14:06:39.11#ibcon#read 5, iclass 30, count 0 2006.257.14:06:39.11#ibcon#about to read 6, iclass 30, count 0 2006.257.14:06:39.11#ibcon#read 6, iclass 30, count 0 2006.257.14:06:39.11#ibcon#end of sib2, iclass 30, count 0 2006.257.14:06:39.11#ibcon#*after write, iclass 30, count 0 2006.257.14:06:39.11#ibcon#*before return 0, iclass 30, count 0 2006.257.14:06:39.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:39.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:39.11#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:06:39.11#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:06:39.11$vck44/va=1,8 2006.257.14:06:39.11#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.14:06:39.11#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.14:06:39.11#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:39.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:39.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:39.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:39.11#ibcon#enter wrdev, iclass 32, count 2 2006.257.14:06:39.11#ibcon#first serial, iclass 32, count 2 2006.257.14:06:39.11#ibcon#enter sib2, iclass 32, count 2 2006.257.14:06:39.11#ibcon#flushed, iclass 32, count 2 2006.257.14:06:39.11#ibcon#about to write, iclass 32, count 2 2006.257.14:06:39.11#ibcon#wrote, iclass 32, count 2 2006.257.14:06:39.11#ibcon#about to read 3, iclass 32, count 2 2006.257.14:06:39.13#ibcon#read 3, iclass 32, count 2 2006.257.14:06:39.13#ibcon#about to read 4, iclass 32, count 2 2006.257.14:06:39.13#ibcon#read 4, iclass 32, count 2 2006.257.14:06:39.13#ibcon#about to read 5, iclass 32, count 2 2006.257.14:06:39.13#ibcon#read 5, iclass 32, count 2 2006.257.14:06:39.13#ibcon#about to read 6, iclass 32, count 2 2006.257.14:06:39.13#ibcon#read 6, iclass 32, count 2 2006.257.14:06:39.13#ibcon#end of sib2, iclass 32, count 2 2006.257.14:06:39.13#ibcon#*mode == 0, iclass 32, count 2 2006.257.14:06:39.13#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.14:06:39.13#ibcon#[25=AT01-08\r\n] 2006.257.14:06:39.13#ibcon#*before write, iclass 32, count 2 2006.257.14:06:39.13#ibcon#enter sib2, iclass 32, count 2 2006.257.14:06:39.13#ibcon#flushed, iclass 32, count 2 2006.257.14:06:39.13#ibcon#about to write, iclass 32, count 2 2006.257.14:06:39.13#ibcon#wrote, iclass 32, count 2 2006.257.14:06:39.13#ibcon#about to read 3, iclass 32, count 2 2006.257.14:06:39.16#ibcon#read 3, iclass 32, count 2 2006.257.14:06:39.16#ibcon#about to read 4, iclass 32, count 2 2006.257.14:06:39.16#ibcon#read 4, iclass 32, count 2 2006.257.14:06:39.16#ibcon#about to read 5, iclass 32, count 2 2006.257.14:06:39.16#ibcon#read 5, iclass 32, count 2 2006.257.14:06:39.16#ibcon#about to read 6, iclass 32, count 2 2006.257.14:06:39.16#ibcon#read 6, iclass 32, count 2 2006.257.14:06:39.16#ibcon#end of sib2, iclass 32, count 2 2006.257.14:06:39.16#ibcon#*after write, iclass 32, count 2 2006.257.14:06:39.16#ibcon#*before return 0, iclass 32, count 2 2006.257.14:06:39.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:39.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:39.16#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.14:06:39.16#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:39.16#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:39.28#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:39.28#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:39.28#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:06:39.28#ibcon#first serial, iclass 32, count 0 2006.257.14:06:39.28#ibcon#enter sib2, iclass 32, count 0 2006.257.14:06:39.28#ibcon#flushed, iclass 32, count 0 2006.257.14:06:39.28#ibcon#about to write, iclass 32, count 0 2006.257.14:06:39.28#ibcon#wrote, iclass 32, count 0 2006.257.14:06:39.28#ibcon#about to read 3, iclass 32, count 0 2006.257.14:06:39.30#ibcon#read 3, iclass 32, count 0 2006.257.14:06:39.30#ibcon#about to read 4, iclass 32, count 0 2006.257.14:06:39.30#ibcon#read 4, iclass 32, count 0 2006.257.14:06:39.30#ibcon#about to read 5, iclass 32, count 0 2006.257.14:06:39.30#ibcon#read 5, iclass 32, count 0 2006.257.14:06:39.30#ibcon#about to read 6, iclass 32, count 0 2006.257.14:06:39.30#ibcon#read 6, iclass 32, count 0 2006.257.14:06:39.30#ibcon#end of sib2, iclass 32, count 0 2006.257.14:06:39.30#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:06:39.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:06:39.30#ibcon#[25=USB\r\n] 2006.257.14:06:39.30#ibcon#*before write, iclass 32, count 0 2006.257.14:06:39.30#ibcon#enter sib2, iclass 32, count 0 2006.257.14:06:39.30#ibcon#flushed, iclass 32, count 0 2006.257.14:06:39.30#ibcon#about to write, iclass 32, count 0 2006.257.14:06:39.30#ibcon#wrote, iclass 32, count 0 2006.257.14:06:39.30#ibcon#about to read 3, iclass 32, count 0 2006.257.14:06:39.33#ibcon#read 3, iclass 32, count 0 2006.257.14:06:39.33#ibcon#about to read 4, iclass 32, count 0 2006.257.14:06:39.33#ibcon#read 4, iclass 32, count 0 2006.257.14:06:39.33#ibcon#about to read 5, iclass 32, count 0 2006.257.14:06:39.33#ibcon#read 5, iclass 32, count 0 2006.257.14:06:39.33#ibcon#about to read 6, iclass 32, count 0 2006.257.14:06:39.33#ibcon#read 6, iclass 32, count 0 2006.257.14:06:39.33#ibcon#end of sib2, iclass 32, count 0 2006.257.14:06:39.33#ibcon#*after write, iclass 32, count 0 2006.257.14:06:39.33#ibcon#*before return 0, iclass 32, count 0 2006.257.14:06:39.33#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:39.33#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:39.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:06:39.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:06:39.33$vck44/valo=2,534.99 2006.257.14:06:39.33#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.14:06:39.33#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.14:06:39.33#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:39.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:39.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:39.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:39.33#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:06:39.33#ibcon#first serial, iclass 34, count 0 2006.257.14:06:39.33#ibcon#enter sib2, iclass 34, count 0 2006.257.14:06:39.33#ibcon#flushed, iclass 34, count 0 2006.257.14:06:39.33#ibcon#about to write, iclass 34, count 0 2006.257.14:06:39.33#ibcon#wrote, iclass 34, count 0 2006.257.14:06:39.33#ibcon#about to read 3, iclass 34, count 0 2006.257.14:06:39.35#ibcon#read 3, iclass 34, count 0 2006.257.14:06:39.35#ibcon#about to read 4, iclass 34, count 0 2006.257.14:06:39.35#ibcon#read 4, iclass 34, count 0 2006.257.14:06:39.35#ibcon#about to read 5, iclass 34, count 0 2006.257.14:06:39.35#ibcon#read 5, iclass 34, count 0 2006.257.14:06:39.35#ibcon#about to read 6, iclass 34, count 0 2006.257.14:06:39.35#ibcon#read 6, iclass 34, count 0 2006.257.14:06:39.35#ibcon#end of sib2, iclass 34, count 0 2006.257.14:06:39.35#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:06:39.35#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:06:39.35#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:06:39.35#ibcon#*before write, iclass 34, count 0 2006.257.14:06:39.35#ibcon#enter sib2, iclass 34, count 0 2006.257.14:06:39.35#ibcon#flushed, iclass 34, count 0 2006.257.14:06:39.35#ibcon#about to write, iclass 34, count 0 2006.257.14:06:39.35#ibcon#wrote, iclass 34, count 0 2006.257.14:06:39.35#ibcon#about to read 3, iclass 34, count 0 2006.257.14:06:39.39#ibcon#read 3, iclass 34, count 0 2006.257.14:06:39.39#ibcon#about to read 4, iclass 34, count 0 2006.257.14:06:39.39#ibcon#read 4, iclass 34, count 0 2006.257.14:06:39.39#ibcon#about to read 5, iclass 34, count 0 2006.257.14:06:39.39#ibcon#read 5, iclass 34, count 0 2006.257.14:06:39.39#ibcon#about to read 6, iclass 34, count 0 2006.257.14:06:39.39#ibcon#read 6, iclass 34, count 0 2006.257.14:06:39.39#ibcon#end of sib2, iclass 34, count 0 2006.257.14:06:39.39#ibcon#*after write, iclass 34, count 0 2006.257.14:06:39.39#ibcon#*before return 0, iclass 34, count 0 2006.257.14:06:39.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:39.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:39.39#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:06:39.39#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:06:39.39$vck44/va=2,7 2006.257.14:06:39.39#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.14:06:39.39#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.14:06:39.39#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:39.39#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:39.45#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:39.45#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:39.45#ibcon#enter wrdev, iclass 36, count 2 2006.257.14:06:39.45#ibcon#first serial, iclass 36, count 2 2006.257.14:06:39.45#ibcon#enter sib2, iclass 36, count 2 2006.257.14:06:39.45#ibcon#flushed, iclass 36, count 2 2006.257.14:06:39.45#ibcon#about to write, iclass 36, count 2 2006.257.14:06:39.45#ibcon#wrote, iclass 36, count 2 2006.257.14:06:39.45#ibcon#about to read 3, iclass 36, count 2 2006.257.14:06:39.47#ibcon#read 3, iclass 36, count 2 2006.257.14:06:39.47#ibcon#about to read 4, iclass 36, count 2 2006.257.14:06:39.47#ibcon#read 4, iclass 36, count 2 2006.257.14:06:39.47#ibcon#about to read 5, iclass 36, count 2 2006.257.14:06:39.47#ibcon#read 5, iclass 36, count 2 2006.257.14:06:39.47#ibcon#about to read 6, iclass 36, count 2 2006.257.14:06:39.47#ibcon#read 6, iclass 36, count 2 2006.257.14:06:39.47#ibcon#end of sib2, iclass 36, count 2 2006.257.14:06:39.47#ibcon#*mode == 0, iclass 36, count 2 2006.257.14:06:39.47#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.14:06:39.47#ibcon#[25=AT02-07\r\n] 2006.257.14:06:39.47#ibcon#*before write, iclass 36, count 2 2006.257.14:06:39.47#ibcon#enter sib2, iclass 36, count 2 2006.257.14:06:39.47#ibcon#flushed, iclass 36, count 2 2006.257.14:06:39.47#ibcon#about to write, iclass 36, count 2 2006.257.14:06:39.47#ibcon#wrote, iclass 36, count 2 2006.257.14:06:39.47#ibcon#about to read 3, iclass 36, count 2 2006.257.14:06:39.50#ibcon#read 3, iclass 36, count 2 2006.257.14:06:39.50#ibcon#about to read 4, iclass 36, count 2 2006.257.14:06:39.50#ibcon#read 4, iclass 36, count 2 2006.257.14:06:39.50#ibcon#about to read 5, iclass 36, count 2 2006.257.14:06:39.50#ibcon#read 5, iclass 36, count 2 2006.257.14:06:39.50#ibcon#about to read 6, iclass 36, count 2 2006.257.14:06:39.50#ibcon#read 6, iclass 36, count 2 2006.257.14:06:39.50#ibcon#end of sib2, iclass 36, count 2 2006.257.14:06:39.50#ibcon#*after write, iclass 36, count 2 2006.257.14:06:39.50#ibcon#*before return 0, iclass 36, count 2 2006.257.14:06:39.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:39.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:39.50#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.14:06:39.50#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:39.50#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:39.62#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:39.62#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:39.62#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:06:39.62#ibcon#first serial, iclass 36, count 0 2006.257.14:06:39.62#ibcon#enter sib2, iclass 36, count 0 2006.257.14:06:39.62#ibcon#flushed, iclass 36, count 0 2006.257.14:06:39.62#ibcon#about to write, iclass 36, count 0 2006.257.14:06:39.62#ibcon#wrote, iclass 36, count 0 2006.257.14:06:39.62#ibcon#about to read 3, iclass 36, count 0 2006.257.14:06:39.64#ibcon#read 3, iclass 36, count 0 2006.257.14:06:39.64#ibcon#about to read 4, iclass 36, count 0 2006.257.14:06:39.64#ibcon#read 4, iclass 36, count 0 2006.257.14:06:39.64#ibcon#about to read 5, iclass 36, count 0 2006.257.14:06:39.64#ibcon#read 5, iclass 36, count 0 2006.257.14:06:39.64#ibcon#about to read 6, iclass 36, count 0 2006.257.14:06:39.64#ibcon#read 6, iclass 36, count 0 2006.257.14:06:39.64#ibcon#end of sib2, iclass 36, count 0 2006.257.14:06:39.64#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:06:39.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:06:39.64#ibcon#[25=USB\r\n] 2006.257.14:06:39.64#ibcon#*before write, iclass 36, count 0 2006.257.14:06:39.64#ibcon#enter sib2, iclass 36, count 0 2006.257.14:06:39.64#ibcon#flushed, iclass 36, count 0 2006.257.14:06:39.64#ibcon#about to write, iclass 36, count 0 2006.257.14:06:39.64#ibcon#wrote, iclass 36, count 0 2006.257.14:06:39.64#ibcon#about to read 3, iclass 36, count 0 2006.257.14:06:39.67#ibcon#read 3, iclass 36, count 0 2006.257.14:06:39.67#ibcon#about to read 4, iclass 36, count 0 2006.257.14:06:39.67#ibcon#read 4, iclass 36, count 0 2006.257.14:06:39.67#ibcon#about to read 5, iclass 36, count 0 2006.257.14:06:39.67#ibcon#read 5, iclass 36, count 0 2006.257.14:06:39.67#ibcon#about to read 6, iclass 36, count 0 2006.257.14:06:39.67#ibcon#read 6, iclass 36, count 0 2006.257.14:06:39.67#ibcon#end of sib2, iclass 36, count 0 2006.257.14:06:39.67#ibcon#*after write, iclass 36, count 0 2006.257.14:06:39.67#ibcon#*before return 0, iclass 36, count 0 2006.257.14:06:39.67#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:39.67#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:39.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:06:39.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:06:39.67$vck44/valo=3,564.99 2006.257.14:06:39.67#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.14:06:39.67#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.14:06:39.67#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:39.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:39.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:39.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:39.67#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:06:39.67#ibcon#first serial, iclass 38, count 0 2006.257.14:06:39.67#ibcon#enter sib2, iclass 38, count 0 2006.257.14:06:39.67#ibcon#flushed, iclass 38, count 0 2006.257.14:06:39.67#ibcon#about to write, iclass 38, count 0 2006.257.14:06:39.67#ibcon#wrote, iclass 38, count 0 2006.257.14:06:39.67#ibcon#about to read 3, iclass 38, count 0 2006.257.14:06:39.69#ibcon#read 3, iclass 38, count 0 2006.257.14:06:39.69#ibcon#about to read 4, iclass 38, count 0 2006.257.14:06:39.69#ibcon#read 4, iclass 38, count 0 2006.257.14:06:39.69#ibcon#about to read 5, iclass 38, count 0 2006.257.14:06:39.69#ibcon#read 5, iclass 38, count 0 2006.257.14:06:39.69#ibcon#about to read 6, iclass 38, count 0 2006.257.14:06:39.69#ibcon#read 6, iclass 38, count 0 2006.257.14:06:39.69#ibcon#end of sib2, iclass 38, count 0 2006.257.14:06:39.69#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:06:39.69#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:06:39.69#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:06:39.69#ibcon#*before write, iclass 38, count 0 2006.257.14:06:39.69#ibcon#enter sib2, iclass 38, count 0 2006.257.14:06:39.69#ibcon#flushed, iclass 38, count 0 2006.257.14:06:39.69#ibcon#about to write, iclass 38, count 0 2006.257.14:06:39.69#ibcon#wrote, iclass 38, count 0 2006.257.14:06:39.69#ibcon#about to read 3, iclass 38, count 0 2006.257.14:06:39.73#ibcon#read 3, iclass 38, count 0 2006.257.14:06:39.73#ibcon#about to read 4, iclass 38, count 0 2006.257.14:06:39.73#ibcon#read 4, iclass 38, count 0 2006.257.14:06:39.73#ibcon#about to read 5, iclass 38, count 0 2006.257.14:06:39.73#ibcon#read 5, iclass 38, count 0 2006.257.14:06:39.73#ibcon#about to read 6, iclass 38, count 0 2006.257.14:06:39.73#ibcon#read 6, iclass 38, count 0 2006.257.14:06:39.73#ibcon#end of sib2, iclass 38, count 0 2006.257.14:06:39.73#ibcon#*after write, iclass 38, count 0 2006.257.14:06:39.73#ibcon#*before return 0, iclass 38, count 0 2006.257.14:06:39.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:39.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:39.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:06:39.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:06:39.73$vck44/va=3,8 2006.257.14:06:39.73#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.14:06:39.73#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.14:06:39.73#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:39.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:39.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:39.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:39.79#ibcon#enter wrdev, iclass 40, count 2 2006.257.14:06:39.79#ibcon#first serial, iclass 40, count 2 2006.257.14:06:39.79#ibcon#enter sib2, iclass 40, count 2 2006.257.14:06:39.79#ibcon#flushed, iclass 40, count 2 2006.257.14:06:39.79#ibcon#about to write, iclass 40, count 2 2006.257.14:06:39.79#ibcon#wrote, iclass 40, count 2 2006.257.14:06:39.79#ibcon#about to read 3, iclass 40, count 2 2006.257.14:06:39.81#ibcon#read 3, iclass 40, count 2 2006.257.14:06:39.81#ibcon#about to read 4, iclass 40, count 2 2006.257.14:06:39.81#ibcon#read 4, iclass 40, count 2 2006.257.14:06:39.81#ibcon#about to read 5, iclass 40, count 2 2006.257.14:06:39.81#ibcon#read 5, iclass 40, count 2 2006.257.14:06:39.81#ibcon#about to read 6, iclass 40, count 2 2006.257.14:06:39.81#ibcon#read 6, iclass 40, count 2 2006.257.14:06:39.81#ibcon#end of sib2, iclass 40, count 2 2006.257.14:06:39.81#ibcon#*mode == 0, iclass 40, count 2 2006.257.14:06:39.81#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.14:06:39.81#ibcon#[25=AT03-08\r\n] 2006.257.14:06:39.81#ibcon#*before write, iclass 40, count 2 2006.257.14:06:39.81#ibcon#enter sib2, iclass 40, count 2 2006.257.14:06:39.81#ibcon#flushed, iclass 40, count 2 2006.257.14:06:39.81#ibcon#about to write, iclass 40, count 2 2006.257.14:06:39.81#ibcon#wrote, iclass 40, count 2 2006.257.14:06:39.81#ibcon#about to read 3, iclass 40, count 2 2006.257.14:06:39.84#ibcon#read 3, iclass 40, count 2 2006.257.14:06:39.84#ibcon#about to read 4, iclass 40, count 2 2006.257.14:06:39.84#ibcon#read 4, iclass 40, count 2 2006.257.14:06:39.84#ibcon#about to read 5, iclass 40, count 2 2006.257.14:06:39.84#ibcon#read 5, iclass 40, count 2 2006.257.14:06:39.84#ibcon#about to read 6, iclass 40, count 2 2006.257.14:06:39.84#ibcon#read 6, iclass 40, count 2 2006.257.14:06:39.84#ibcon#end of sib2, iclass 40, count 2 2006.257.14:06:39.84#ibcon#*after write, iclass 40, count 2 2006.257.14:06:39.84#ibcon#*before return 0, iclass 40, count 2 2006.257.14:06:39.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:39.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:39.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.14:06:39.84#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:39.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:39.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:39.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:39.96#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:06:39.96#ibcon#first serial, iclass 40, count 0 2006.257.14:06:39.96#ibcon#enter sib2, iclass 40, count 0 2006.257.14:06:39.96#ibcon#flushed, iclass 40, count 0 2006.257.14:06:39.96#ibcon#about to write, iclass 40, count 0 2006.257.14:06:39.96#ibcon#wrote, iclass 40, count 0 2006.257.14:06:39.96#ibcon#about to read 3, iclass 40, count 0 2006.257.14:06:39.98#ibcon#read 3, iclass 40, count 0 2006.257.14:06:39.98#ibcon#about to read 4, iclass 40, count 0 2006.257.14:06:39.98#ibcon#read 4, iclass 40, count 0 2006.257.14:06:39.98#ibcon#about to read 5, iclass 40, count 0 2006.257.14:06:39.98#ibcon#read 5, iclass 40, count 0 2006.257.14:06:39.98#ibcon#about to read 6, iclass 40, count 0 2006.257.14:06:39.98#ibcon#read 6, iclass 40, count 0 2006.257.14:06:39.98#ibcon#end of sib2, iclass 40, count 0 2006.257.14:06:39.98#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:06:39.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:06:39.98#ibcon#[25=USB\r\n] 2006.257.14:06:39.98#ibcon#*before write, iclass 40, count 0 2006.257.14:06:39.98#ibcon#enter sib2, iclass 40, count 0 2006.257.14:06:39.98#ibcon#flushed, iclass 40, count 0 2006.257.14:06:39.98#ibcon#about to write, iclass 40, count 0 2006.257.14:06:39.98#ibcon#wrote, iclass 40, count 0 2006.257.14:06:39.98#ibcon#about to read 3, iclass 40, count 0 2006.257.14:06:40.01#ibcon#read 3, iclass 40, count 0 2006.257.14:06:40.01#ibcon#about to read 4, iclass 40, count 0 2006.257.14:06:40.01#ibcon#read 4, iclass 40, count 0 2006.257.14:06:40.01#ibcon#about to read 5, iclass 40, count 0 2006.257.14:06:40.01#ibcon#read 5, iclass 40, count 0 2006.257.14:06:40.01#ibcon#about to read 6, iclass 40, count 0 2006.257.14:06:40.01#ibcon#read 6, iclass 40, count 0 2006.257.14:06:40.01#ibcon#end of sib2, iclass 40, count 0 2006.257.14:06:40.01#ibcon#*after write, iclass 40, count 0 2006.257.14:06:40.01#ibcon#*before return 0, iclass 40, count 0 2006.257.14:06:40.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:40.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:40.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:06:40.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:06:40.01$vck44/valo=4,624.99 2006.257.14:06:40.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.14:06:40.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.14:06:40.01#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:40.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:40.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:40.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:40.01#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:06:40.01#ibcon#first serial, iclass 4, count 0 2006.257.14:06:40.01#ibcon#enter sib2, iclass 4, count 0 2006.257.14:06:40.01#ibcon#flushed, iclass 4, count 0 2006.257.14:06:40.01#ibcon#about to write, iclass 4, count 0 2006.257.14:06:40.01#ibcon#wrote, iclass 4, count 0 2006.257.14:06:40.01#ibcon#about to read 3, iclass 4, count 0 2006.257.14:06:40.03#ibcon#read 3, iclass 4, count 0 2006.257.14:06:40.03#ibcon#about to read 4, iclass 4, count 0 2006.257.14:06:40.03#ibcon#read 4, iclass 4, count 0 2006.257.14:06:40.03#ibcon#about to read 5, iclass 4, count 0 2006.257.14:06:40.03#ibcon#read 5, iclass 4, count 0 2006.257.14:06:40.03#ibcon#about to read 6, iclass 4, count 0 2006.257.14:06:40.03#ibcon#read 6, iclass 4, count 0 2006.257.14:06:40.03#ibcon#end of sib2, iclass 4, count 0 2006.257.14:06:40.03#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:06:40.03#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:06:40.03#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:06:40.03#ibcon#*before write, iclass 4, count 0 2006.257.14:06:40.03#ibcon#enter sib2, iclass 4, count 0 2006.257.14:06:40.03#ibcon#flushed, iclass 4, count 0 2006.257.14:06:40.03#ibcon#about to write, iclass 4, count 0 2006.257.14:06:40.03#ibcon#wrote, iclass 4, count 0 2006.257.14:06:40.03#ibcon#about to read 3, iclass 4, count 0 2006.257.14:06:40.07#ibcon#read 3, iclass 4, count 0 2006.257.14:06:40.07#ibcon#about to read 4, iclass 4, count 0 2006.257.14:06:40.07#ibcon#read 4, iclass 4, count 0 2006.257.14:06:40.07#ibcon#about to read 5, iclass 4, count 0 2006.257.14:06:40.07#ibcon#read 5, iclass 4, count 0 2006.257.14:06:40.07#ibcon#about to read 6, iclass 4, count 0 2006.257.14:06:40.07#ibcon#read 6, iclass 4, count 0 2006.257.14:06:40.07#ibcon#end of sib2, iclass 4, count 0 2006.257.14:06:40.07#ibcon#*after write, iclass 4, count 0 2006.257.14:06:40.07#ibcon#*before return 0, iclass 4, count 0 2006.257.14:06:40.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:40.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:40.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:06:40.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:06:40.07$vck44/va=4,7 2006.257.14:06:40.07#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.14:06:40.07#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.14:06:40.07#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:40.07#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:40.13#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:40.13#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:40.13#ibcon#enter wrdev, iclass 6, count 2 2006.257.14:06:40.13#ibcon#first serial, iclass 6, count 2 2006.257.14:06:40.13#ibcon#enter sib2, iclass 6, count 2 2006.257.14:06:40.13#ibcon#flushed, iclass 6, count 2 2006.257.14:06:40.13#ibcon#about to write, iclass 6, count 2 2006.257.14:06:40.13#ibcon#wrote, iclass 6, count 2 2006.257.14:06:40.13#ibcon#about to read 3, iclass 6, count 2 2006.257.14:06:40.15#ibcon#read 3, iclass 6, count 2 2006.257.14:06:40.15#ibcon#about to read 4, iclass 6, count 2 2006.257.14:06:40.15#ibcon#read 4, iclass 6, count 2 2006.257.14:06:40.15#ibcon#about to read 5, iclass 6, count 2 2006.257.14:06:40.15#ibcon#read 5, iclass 6, count 2 2006.257.14:06:40.15#ibcon#about to read 6, iclass 6, count 2 2006.257.14:06:40.15#ibcon#read 6, iclass 6, count 2 2006.257.14:06:40.15#ibcon#end of sib2, iclass 6, count 2 2006.257.14:06:40.15#ibcon#*mode == 0, iclass 6, count 2 2006.257.14:06:40.15#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.14:06:40.15#ibcon#[25=AT04-07\r\n] 2006.257.14:06:40.15#ibcon#*before write, iclass 6, count 2 2006.257.14:06:40.15#ibcon#enter sib2, iclass 6, count 2 2006.257.14:06:40.15#ibcon#flushed, iclass 6, count 2 2006.257.14:06:40.15#ibcon#about to write, iclass 6, count 2 2006.257.14:06:40.15#ibcon#wrote, iclass 6, count 2 2006.257.14:06:40.15#ibcon#about to read 3, iclass 6, count 2 2006.257.14:06:40.18#ibcon#read 3, iclass 6, count 2 2006.257.14:06:40.18#ibcon#about to read 4, iclass 6, count 2 2006.257.14:06:40.18#ibcon#read 4, iclass 6, count 2 2006.257.14:06:40.18#ibcon#about to read 5, iclass 6, count 2 2006.257.14:06:40.18#ibcon#read 5, iclass 6, count 2 2006.257.14:06:40.18#ibcon#about to read 6, iclass 6, count 2 2006.257.14:06:40.18#ibcon#read 6, iclass 6, count 2 2006.257.14:06:40.18#ibcon#end of sib2, iclass 6, count 2 2006.257.14:06:40.18#ibcon#*after write, iclass 6, count 2 2006.257.14:06:40.18#ibcon#*before return 0, iclass 6, count 2 2006.257.14:06:40.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:40.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:40.18#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.14:06:40.18#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:40.18#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:40.30#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:40.30#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:40.30#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:06:40.30#ibcon#first serial, iclass 6, count 0 2006.257.14:06:40.30#ibcon#enter sib2, iclass 6, count 0 2006.257.14:06:40.30#ibcon#flushed, iclass 6, count 0 2006.257.14:06:40.30#ibcon#about to write, iclass 6, count 0 2006.257.14:06:40.30#ibcon#wrote, iclass 6, count 0 2006.257.14:06:40.30#ibcon#about to read 3, iclass 6, count 0 2006.257.14:06:40.32#ibcon#read 3, iclass 6, count 0 2006.257.14:06:40.32#ibcon#about to read 4, iclass 6, count 0 2006.257.14:06:40.32#ibcon#read 4, iclass 6, count 0 2006.257.14:06:40.32#ibcon#about to read 5, iclass 6, count 0 2006.257.14:06:40.32#ibcon#read 5, iclass 6, count 0 2006.257.14:06:40.32#ibcon#about to read 6, iclass 6, count 0 2006.257.14:06:40.32#ibcon#read 6, iclass 6, count 0 2006.257.14:06:40.32#ibcon#end of sib2, iclass 6, count 0 2006.257.14:06:40.32#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:06:40.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:06:40.32#ibcon#[25=USB\r\n] 2006.257.14:06:40.32#ibcon#*before write, iclass 6, count 0 2006.257.14:06:40.32#ibcon#enter sib2, iclass 6, count 0 2006.257.14:06:40.32#ibcon#flushed, iclass 6, count 0 2006.257.14:06:40.32#ibcon#about to write, iclass 6, count 0 2006.257.14:06:40.32#ibcon#wrote, iclass 6, count 0 2006.257.14:06:40.32#ibcon#about to read 3, iclass 6, count 0 2006.257.14:06:40.35#ibcon#read 3, iclass 6, count 0 2006.257.14:06:40.35#ibcon#about to read 4, iclass 6, count 0 2006.257.14:06:40.35#ibcon#read 4, iclass 6, count 0 2006.257.14:06:40.35#ibcon#about to read 5, iclass 6, count 0 2006.257.14:06:40.35#ibcon#read 5, iclass 6, count 0 2006.257.14:06:40.35#ibcon#about to read 6, iclass 6, count 0 2006.257.14:06:40.35#ibcon#read 6, iclass 6, count 0 2006.257.14:06:40.35#ibcon#end of sib2, iclass 6, count 0 2006.257.14:06:40.35#ibcon#*after write, iclass 6, count 0 2006.257.14:06:40.35#ibcon#*before return 0, iclass 6, count 0 2006.257.14:06:40.35#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:40.35#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:40.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:06:40.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:06:40.35$vck44/valo=5,734.99 2006.257.14:06:40.35#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.14:06:40.35#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.14:06:40.35#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:40.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:40.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:40.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:40.35#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:06:40.35#ibcon#first serial, iclass 10, count 0 2006.257.14:06:40.35#ibcon#enter sib2, iclass 10, count 0 2006.257.14:06:40.35#ibcon#flushed, iclass 10, count 0 2006.257.14:06:40.35#ibcon#about to write, iclass 10, count 0 2006.257.14:06:40.35#ibcon#wrote, iclass 10, count 0 2006.257.14:06:40.35#ibcon#about to read 3, iclass 10, count 0 2006.257.14:06:40.37#ibcon#read 3, iclass 10, count 0 2006.257.14:06:41.04#ibcon#about to read 4, iclass 10, count 0 2006.257.14:06:41.04#ibcon#read 4, iclass 10, count 0 2006.257.14:06:41.04#ibcon#about to read 5, iclass 10, count 0 2006.257.14:06:41.04#ibcon#read 5, iclass 10, count 0 2006.257.14:06:41.04#ibcon#about to read 6, iclass 10, count 0 2006.257.14:06:41.04#ibcon#read 6, iclass 10, count 0 2006.257.14:06:41.04#ibcon#end of sib2, iclass 10, count 0 2006.257.14:06:41.04#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:06:41.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:06:41.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:06:41.04#ibcon#*before write, iclass 10, count 0 2006.257.14:06:41.04#ibcon#enter sib2, iclass 10, count 0 2006.257.14:06:41.04#ibcon#flushed, iclass 10, count 0 2006.257.14:06:41.04#ibcon#about to write, iclass 10, count 0 2006.257.14:06:41.04#ibcon#wrote, iclass 10, count 0 2006.257.14:06:41.04#ibcon#about to read 3, iclass 10, count 0 2006.257.14:06:41.08#ibcon#read 3, iclass 10, count 0 2006.257.14:06:41.08#ibcon#about to read 4, iclass 10, count 0 2006.257.14:06:41.08#ibcon#read 4, iclass 10, count 0 2006.257.14:06:41.08#ibcon#about to read 5, iclass 10, count 0 2006.257.14:06:41.08#ibcon#read 5, iclass 10, count 0 2006.257.14:06:41.08#ibcon#about to read 6, iclass 10, count 0 2006.257.14:06:41.08#ibcon#read 6, iclass 10, count 0 2006.257.14:06:41.08#ibcon#end of sib2, iclass 10, count 0 2006.257.14:06:41.08#ibcon#*after write, iclass 10, count 0 2006.257.14:06:41.08#ibcon#*before return 0, iclass 10, count 0 2006.257.14:06:41.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:41.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:41.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:06:41.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:06:41.08$vck44/va=5,4 2006.257.14:06:41.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.14:06:41.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.14:06:41.08#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:41.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:41.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:41.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:41.08#ibcon#enter wrdev, iclass 12, count 2 2006.257.14:06:41.08#ibcon#first serial, iclass 12, count 2 2006.257.14:06:41.08#ibcon#enter sib2, iclass 12, count 2 2006.257.14:06:41.08#ibcon#flushed, iclass 12, count 2 2006.257.14:06:41.08#ibcon#about to write, iclass 12, count 2 2006.257.14:06:41.08#ibcon#wrote, iclass 12, count 2 2006.257.14:06:41.08#ibcon#about to read 3, iclass 12, count 2 2006.257.14:06:41.10#ibcon#read 3, iclass 12, count 2 2006.257.14:06:41.10#ibcon#about to read 4, iclass 12, count 2 2006.257.14:06:41.10#ibcon#read 4, iclass 12, count 2 2006.257.14:06:41.10#ibcon#about to read 5, iclass 12, count 2 2006.257.14:06:41.10#ibcon#read 5, iclass 12, count 2 2006.257.14:06:41.10#ibcon#about to read 6, iclass 12, count 2 2006.257.14:06:41.10#ibcon#read 6, iclass 12, count 2 2006.257.14:06:41.10#ibcon#end of sib2, iclass 12, count 2 2006.257.14:06:41.10#ibcon#*mode == 0, iclass 12, count 2 2006.257.14:06:41.10#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.14:06:41.10#ibcon#[25=AT05-04\r\n] 2006.257.14:06:41.10#ibcon#*before write, iclass 12, count 2 2006.257.14:06:41.10#ibcon#enter sib2, iclass 12, count 2 2006.257.14:06:41.10#ibcon#flushed, iclass 12, count 2 2006.257.14:06:41.10#ibcon#about to write, iclass 12, count 2 2006.257.14:06:41.10#ibcon#wrote, iclass 12, count 2 2006.257.14:06:41.10#ibcon#about to read 3, iclass 12, count 2 2006.257.14:06:41.13#ibcon#read 3, iclass 12, count 2 2006.257.14:06:41.13#ibcon#about to read 4, iclass 12, count 2 2006.257.14:06:41.13#ibcon#read 4, iclass 12, count 2 2006.257.14:06:41.13#ibcon#about to read 5, iclass 12, count 2 2006.257.14:06:41.13#ibcon#read 5, iclass 12, count 2 2006.257.14:06:41.13#ibcon#about to read 6, iclass 12, count 2 2006.257.14:06:41.13#ibcon#read 6, iclass 12, count 2 2006.257.14:06:41.13#ibcon#end of sib2, iclass 12, count 2 2006.257.14:06:41.13#ibcon#*after write, iclass 12, count 2 2006.257.14:06:41.13#ibcon#*before return 0, iclass 12, count 2 2006.257.14:06:41.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:41.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:41.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.14:06:41.13#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:41.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:41.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:41.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:41.25#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:06:41.25#ibcon#first serial, iclass 12, count 0 2006.257.14:06:41.25#ibcon#enter sib2, iclass 12, count 0 2006.257.14:06:41.25#ibcon#flushed, iclass 12, count 0 2006.257.14:06:41.25#ibcon#about to write, iclass 12, count 0 2006.257.14:06:41.25#ibcon#wrote, iclass 12, count 0 2006.257.14:06:41.25#ibcon#about to read 3, iclass 12, count 0 2006.257.14:06:41.27#ibcon#read 3, iclass 12, count 0 2006.257.14:06:41.27#ibcon#about to read 4, iclass 12, count 0 2006.257.14:06:41.27#ibcon#read 4, iclass 12, count 0 2006.257.14:06:41.27#ibcon#about to read 5, iclass 12, count 0 2006.257.14:06:41.27#ibcon#read 5, iclass 12, count 0 2006.257.14:06:41.27#ibcon#about to read 6, iclass 12, count 0 2006.257.14:06:41.27#ibcon#read 6, iclass 12, count 0 2006.257.14:06:41.27#ibcon#end of sib2, iclass 12, count 0 2006.257.14:06:41.27#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:06:41.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:06:41.27#ibcon#[25=USB\r\n] 2006.257.14:06:41.27#ibcon#*before write, iclass 12, count 0 2006.257.14:06:41.27#ibcon#enter sib2, iclass 12, count 0 2006.257.14:06:41.27#ibcon#flushed, iclass 12, count 0 2006.257.14:06:41.27#ibcon#about to write, iclass 12, count 0 2006.257.14:06:41.27#ibcon#wrote, iclass 12, count 0 2006.257.14:06:41.27#ibcon#about to read 3, iclass 12, count 0 2006.257.14:06:41.30#ibcon#read 3, iclass 12, count 0 2006.257.14:06:41.30#ibcon#about to read 4, iclass 12, count 0 2006.257.14:06:41.30#ibcon#read 4, iclass 12, count 0 2006.257.14:06:41.30#ibcon#about to read 5, iclass 12, count 0 2006.257.14:06:41.30#ibcon#read 5, iclass 12, count 0 2006.257.14:06:41.30#ibcon#about to read 6, iclass 12, count 0 2006.257.14:06:41.30#ibcon#read 6, iclass 12, count 0 2006.257.14:06:41.30#ibcon#end of sib2, iclass 12, count 0 2006.257.14:06:41.30#ibcon#*after write, iclass 12, count 0 2006.257.14:06:41.30#ibcon#*before return 0, iclass 12, count 0 2006.257.14:06:41.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:41.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:41.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:06:41.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:06:41.30$vck44/valo=6,814.99 2006.257.14:06:41.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.14:06:41.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.14:06:41.30#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:41.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:41.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:41.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:41.30#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:06:41.30#ibcon#first serial, iclass 14, count 0 2006.257.14:06:41.30#ibcon#enter sib2, iclass 14, count 0 2006.257.14:06:41.30#ibcon#flushed, iclass 14, count 0 2006.257.14:06:41.30#ibcon#about to write, iclass 14, count 0 2006.257.14:06:41.30#ibcon#wrote, iclass 14, count 0 2006.257.14:06:41.30#ibcon#about to read 3, iclass 14, count 0 2006.257.14:06:41.32#ibcon#read 3, iclass 14, count 0 2006.257.14:06:41.32#ibcon#about to read 4, iclass 14, count 0 2006.257.14:06:41.32#ibcon#read 4, iclass 14, count 0 2006.257.14:06:41.32#ibcon#about to read 5, iclass 14, count 0 2006.257.14:06:41.32#ibcon#read 5, iclass 14, count 0 2006.257.14:06:41.32#ibcon#about to read 6, iclass 14, count 0 2006.257.14:06:41.32#ibcon#read 6, iclass 14, count 0 2006.257.14:06:41.32#ibcon#end of sib2, iclass 14, count 0 2006.257.14:06:41.32#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:06:41.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:06:41.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:06:41.32#ibcon#*before write, iclass 14, count 0 2006.257.14:06:41.32#ibcon#enter sib2, iclass 14, count 0 2006.257.14:06:41.32#ibcon#flushed, iclass 14, count 0 2006.257.14:06:41.32#ibcon#about to write, iclass 14, count 0 2006.257.14:06:41.32#ibcon#wrote, iclass 14, count 0 2006.257.14:06:41.32#ibcon#about to read 3, iclass 14, count 0 2006.257.14:06:41.36#ibcon#read 3, iclass 14, count 0 2006.257.14:06:41.36#ibcon#about to read 4, iclass 14, count 0 2006.257.14:06:41.36#ibcon#read 4, iclass 14, count 0 2006.257.14:06:41.36#ibcon#about to read 5, iclass 14, count 0 2006.257.14:06:41.36#ibcon#read 5, iclass 14, count 0 2006.257.14:06:41.36#ibcon#about to read 6, iclass 14, count 0 2006.257.14:06:41.36#ibcon#read 6, iclass 14, count 0 2006.257.14:06:41.36#ibcon#end of sib2, iclass 14, count 0 2006.257.14:06:41.36#ibcon#*after write, iclass 14, count 0 2006.257.14:06:41.36#ibcon#*before return 0, iclass 14, count 0 2006.257.14:06:41.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:41.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:41.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:06:41.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:06:41.36$vck44/va=6,4 2006.257.14:06:41.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.14:06:41.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.14:06:41.36#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:41.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:41.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:41.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:41.42#ibcon#enter wrdev, iclass 16, count 2 2006.257.14:06:41.42#ibcon#first serial, iclass 16, count 2 2006.257.14:06:41.42#ibcon#enter sib2, iclass 16, count 2 2006.257.14:06:41.42#ibcon#flushed, iclass 16, count 2 2006.257.14:06:41.42#ibcon#about to write, iclass 16, count 2 2006.257.14:06:41.42#ibcon#wrote, iclass 16, count 2 2006.257.14:06:41.42#ibcon#about to read 3, iclass 16, count 2 2006.257.14:06:41.44#ibcon#read 3, iclass 16, count 2 2006.257.14:06:41.44#ibcon#about to read 4, iclass 16, count 2 2006.257.14:06:41.44#ibcon#read 4, iclass 16, count 2 2006.257.14:06:41.44#ibcon#about to read 5, iclass 16, count 2 2006.257.14:06:41.44#ibcon#read 5, iclass 16, count 2 2006.257.14:06:41.44#ibcon#about to read 6, iclass 16, count 2 2006.257.14:06:41.44#ibcon#read 6, iclass 16, count 2 2006.257.14:06:41.44#ibcon#end of sib2, iclass 16, count 2 2006.257.14:06:41.44#ibcon#*mode == 0, iclass 16, count 2 2006.257.14:06:41.44#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.14:06:41.44#ibcon#[25=AT06-04\r\n] 2006.257.14:06:41.44#ibcon#*before write, iclass 16, count 2 2006.257.14:06:41.44#ibcon#enter sib2, iclass 16, count 2 2006.257.14:06:41.44#ibcon#flushed, iclass 16, count 2 2006.257.14:06:41.44#ibcon#about to write, iclass 16, count 2 2006.257.14:06:41.44#ibcon#wrote, iclass 16, count 2 2006.257.14:06:41.44#ibcon#about to read 3, iclass 16, count 2 2006.257.14:06:41.47#ibcon#read 3, iclass 16, count 2 2006.257.14:06:41.47#ibcon#about to read 4, iclass 16, count 2 2006.257.14:06:41.47#ibcon#read 4, iclass 16, count 2 2006.257.14:06:41.47#ibcon#about to read 5, iclass 16, count 2 2006.257.14:06:41.47#ibcon#read 5, iclass 16, count 2 2006.257.14:06:41.47#ibcon#about to read 6, iclass 16, count 2 2006.257.14:06:41.47#ibcon#read 6, iclass 16, count 2 2006.257.14:06:41.47#ibcon#end of sib2, iclass 16, count 2 2006.257.14:06:41.47#ibcon#*after write, iclass 16, count 2 2006.257.14:06:41.47#ibcon#*before return 0, iclass 16, count 2 2006.257.14:06:41.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:41.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:41.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.14:06:41.47#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:41.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:41.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:41.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:41.59#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:06:41.59#ibcon#first serial, iclass 16, count 0 2006.257.14:06:41.59#ibcon#enter sib2, iclass 16, count 0 2006.257.14:06:41.59#ibcon#flushed, iclass 16, count 0 2006.257.14:06:41.59#ibcon#about to write, iclass 16, count 0 2006.257.14:06:41.59#ibcon#wrote, iclass 16, count 0 2006.257.14:06:41.59#ibcon#about to read 3, iclass 16, count 0 2006.257.14:06:41.61#ibcon#read 3, iclass 16, count 0 2006.257.14:06:41.61#ibcon#about to read 4, iclass 16, count 0 2006.257.14:06:41.61#ibcon#read 4, iclass 16, count 0 2006.257.14:06:41.61#ibcon#about to read 5, iclass 16, count 0 2006.257.14:06:41.61#ibcon#read 5, iclass 16, count 0 2006.257.14:06:41.61#ibcon#about to read 6, iclass 16, count 0 2006.257.14:06:41.61#ibcon#read 6, iclass 16, count 0 2006.257.14:06:41.61#ibcon#end of sib2, iclass 16, count 0 2006.257.14:06:41.61#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:06:41.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:06:41.61#ibcon#[25=USB\r\n] 2006.257.14:06:41.61#ibcon#*before write, iclass 16, count 0 2006.257.14:06:41.61#ibcon#enter sib2, iclass 16, count 0 2006.257.14:06:41.61#ibcon#flushed, iclass 16, count 0 2006.257.14:06:41.61#ibcon#about to write, iclass 16, count 0 2006.257.14:06:41.61#ibcon#wrote, iclass 16, count 0 2006.257.14:06:41.61#ibcon#about to read 3, iclass 16, count 0 2006.257.14:06:41.64#ibcon#read 3, iclass 16, count 0 2006.257.14:06:41.64#ibcon#about to read 4, iclass 16, count 0 2006.257.14:06:41.64#ibcon#read 4, iclass 16, count 0 2006.257.14:06:41.64#ibcon#about to read 5, iclass 16, count 0 2006.257.14:06:41.64#ibcon#read 5, iclass 16, count 0 2006.257.14:06:41.64#ibcon#about to read 6, iclass 16, count 0 2006.257.14:06:41.64#ibcon#read 6, iclass 16, count 0 2006.257.14:06:41.64#ibcon#end of sib2, iclass 16, count 0 2006.257.14:06:41.64#ibcon#*after write, iclass 16, count 0 2006.257.14:06:41.64#ibcon#*before return 0, iclass 16, count 0 2006.257.14:06:41.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:41.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:41.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:06:41.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:06:41.64$vck44/valo=7,864.99 2006.257.14:06:41.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.14:06:41.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.14:06:41.64#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:41.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:06:41.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:06:41.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:06:41.64#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:06:41.64#ibcon#first serial, iclass 18, count 0 2006.257.14:06:41.64#ibcon#enter sib2, iclass 18, count 0 2006.257.14:06:41.64#ibcon#flushed, iclass 18, count 0 2006.257.14:06:41.64#ibcon#about to write, iclass 18, count 0 2006.257.14:06:41.64#ibcon#wrote, iclass 18, count 0 2006.257.14:06:41.64#ibcon#about to read 3, iclass 18, count 0 2006.257.14:06:41.66#ibcon#read 3, iclass 18, count 0 2006.257.14:06:41.66#ibcon#about to read 4, iclass 18, count 0 2006.257.14:06:41.66#ibcon#read 4, iclass 18, count 0 2006.257.14:06:41.66#ibcon#about to read 5, iclass 18, count 0 2006.257.14:06:41.66#ibcon#read 5, iclass 18, count 0 2006.257.14:06:41.66#ibcon#about to read 6, iclass 18, count 0 2006.257.14:06:41.66#ibcon#read 6, iclass 18, count 0 2006.257.14:06:41.66#ibcon#end of sib2, iclass 18, count 0 2006.257.14:06:41.66#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:06:41.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:06:41.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:06:41.66#ibcon#*before write, iclass 18, count 0 2006.257.14:06:41.66#ibcon#enter sib2, iclass 18, count 0 2006.257.14:06:41.66#ibcon#flushed, iclass 18, count 0 2006.257.14:06:41.66#ibcon#about to write, iclass 18, count 0 2006.257.14:06:41.66#ibcon#wrote, iclass 18, count 0 2006.257.14:06:41.66#ibcon#about to read 3, iclass 18, count 0 2006.257.14:06:41.70#ibcon#read 3, iclass 18, count 0 2006.257.14:06:41.70#ibcon#about to read 4, iclass 18, count 0 2006.257.14:06:41.70#ibcon#read 4, iclass 18, count 0 2006.257.14:06:41.70#ibcon#about to read 5, iclass 18, count 0 2006.257.14:06:41.70#ibcon#read 5, iclass 18, count 0 2006.257.14:06:41.70#ibcon#about to read 6, iclass 18, count 0 2006.257.14:06:41.70#ibcon#read 6, iclass 18, count 0 2006.257.14:06:41.70#ibcon#end of sib2, iclass 18, count 0 2006.257.14:06:41.70#ibcon#*after write, iclass 18, count 0 2006.257.14:06:41.70#ibcon#*before return 0, iclass 18, count 0 2006.257.14:06:41.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:06:41.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:06:41.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:06:41.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:06:41.70$vck44/va=7,4 2006.257.14:06:41.70#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.14:06:41.70#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.14:06:41.70#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:41.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:06:41.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:06:41.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:06:41.76#ibcon#enter wrdev, iclass 20, count 2 2006.257.14:06:41.76#ibcon#first serial, iclass 20, count 2 2006.257.14:06:41.76#ibcon#enter sib2, iclass 20, count 2 2006.257.14:06:41.76#ibcon#flushed, iclass 20, count 2 2006.257.14:06:41.76#ibcon#about to write, iclass 20, count 2 2006.257.14:06:41.76#ibcon#wrote, iclass 20, count 2 2006.257.14:06:41.76#ibcon#about to read 3, iclass 20, count 2 2006.257.14:06:41.78#ibcon#read 3, iclass 20, count 2 2006.257.14:06:41.78#ibcon#about to read 4, iclass 20, count 2 2006.257.14:06:41.78#ibcon#read 4, iclass 20, count 2 2006.257.14:06:41.78#ibcon#about to read 5, iclass 20, count 2 2006.257.14:06:41.78#ibcon#read 5, iclass 20, count 2 2006.257.14:06:41.78#ibcon#about to read 6, iclass 20, count 2 2006.257.14:06:41.78#ibcon#read 6, iclass 20, count 2 2006.257.14:06:41.78#ibcon#end of sib2, iclass 20, count 2 2006.257.14:06:41.78#ibcon#*mode == 0, iclass 20, count 2 2006.257.14:06:41.78#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.14:06:41.78#ibcon#[25=AT07-04\r\n] 2006.257.14:06:41.78#ibcon#*before write, iclass 20, count 2 2006.257.14:06:41.78#ibcon#enter sib2, iclass 20, count 2 2006.257.14:06:41.78#ibcon#flushed, iclass 20, count 2 2006.257.14:06:41.78#ibcon#about to write, iclass 20, count 2 2006.257.14:06:41.78#ibcon#wrote, iclass 20, count 2 2006.257.14:06:41.78#ibcon#about to read 3, iclass 20, count 2 2006.257.14:06:41.81#ibcon#read 3, iclass 20, count 2 2006.257.14:06:41.81#ibcon#about to read 4, iclass 20, count 2 2006.257.14:06:41.81#ibcon#read 4, iclass 20, count 2 2006.257.14:06:41.81#ibcon#about to read 5, iclass 20, count 2 2006.257.14:06:41.81#ibcon#read 5, iclass 20, count 2 2006.257.14:06:41.81#ibcon#about to read 6, iclass 20, count 2 2006.257.14:06:41.81#ibcon#read 6, iclass 20, count 2 2006.257.14:06:41.81#ibcon#end of sib2, iclass 20, count 2 2006.257.14:06:41.81#ibcon#*after write, iclass 20, count 2 2006.257.14:06:41.81#ibcon#*before return 0, iclass 20, count 2 2006.257.14:06:41.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:06:41.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:06:41.81#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.14:06:41.81#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:41.81#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:06:41.93#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:06:41.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:06:41.93#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:06:41.93#ibcon#first serial, iclass 20, count 0 2006.257.14:06:41.93#ibcon#enter sib2, iclass 20, count 0 2006.257.14:06:41.93#ibcon#flushed, iclass 20, count 0 2006.257.14:06:41.93#ibcon#about to write, iclass 20, count 0 2006.257.14:06:41.93#ibcon#wrote, iclass 20, count 0 2006.257.14:06:41.93#ibcon#about to read 3, iclass 20, count 0 2006.257.14:06:41.95#ibcon#read 3, iclass 20, count 0 2006.257.14:06:41.95#ibcon#about to read 4, iclass 20, count 0 2006.257.14:06:41.95#ibcon#read 4, iclass 20, count 0 2006.257.14:06:41.95#ibcon#about to read 5, iclass 20, count 0 2006.257.14:06:41.95#ibcon#read 5, iclass 20, count 0 2006.257.14:06:41.95#ibcon#about to read 6, iclass 20, count 0 2006.257.14:06:41.95#ibcon#read 6, iclass 20, count 0 2006.257.14:06:41.95#ibcon#end of sib2, iclass 20, count 0 2006.257.14:06:41.95#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:06:41.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:06:41.95#ibcon#[25=USB\r\n] 2006.257.14:06:41.95#ibcon#*before write, iclass 20, count 0 2006.257.14:06:41.95#ibcon#enter sib2, iclass 20, count 0 2006.257.14:06:41.95#ibcon#flushed, iclass 20, count 0 2006.257.14:06:41.95#ibcon#about to write, iclass 20, count 0 2006.257.14:06:41.95#ibcon#wrote, iclass 20, count 0 2006.257.14:06:41.95#ibcon#about to read 3, iclass 20, count 0 2006.257.14:06:41.98#ibcon#read 3, iclass 20, count 0 2006.257.14:06:41.98#ibcon#about to read 4, iclass 20, count 0 2006.257.14:06:41.98#ibcon#read 4, iclass 20, count 0 2006.257.14:06:41.98#ibcon#about to read 5, iclass 20, count 0 2006.257.14:06:41.98#ibcon#read 5, iclass 20, count 0 2006.257.14:06:41.98#ibcon#about to read 6, iclass 20, count 0 2006.257.14:06:41.98#ibcon#read 6, iclass 20, count 0 2006.257.14:06:41.98#ibcon#end of sib2, iclass 20, count 0 2006.257.14:06:41.98#ibcon#*after write, iclass 20, count 0 2006.257.14:06:41.98#ibcon#*before return 0, iclass 20, count 0 2006.257.14:06:41.98#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:06:41.98#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:06:41.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:06:41.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:06:41.98$vck44/valo=8,884.99 2006.257.14:06:41.98#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.14:06:41.98#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.14:06:41.98#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:41.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:41.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:41.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:41.98#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:06:41.98#ibcon#first serial, iclass 22, count 0 2006.257.14:06:41.98#ibcon#enter sib2, iclass 22, count 0 2006.257.14:06:41.98#ibcon#flushed, iclass 22, count 0 2006.257.14:06:41.98#ibcon#about to write, iclass 22, count 0 2006.257.14:06:41.98#ibcon#wrote, iclass 22, count 0 2006.257.14:06:41.98#ibcon#about to read 3, iclass 22, count 0 2006.257.14:06:42.00#ibcon#read 3, iclass 22, count 0 2006.257.14:06:42.00#ibcon#about to read 4, iclass 22, count 0 2006.257.14:06:42.00#ibcon#read 4, iclass 22, count 0 2006.257.14:06:42.00#ibcon#about to read 5, iclass 22, count 0 2006.257.14:06:42.00#ibcon#read 5, iclass 22, count 0 2006.257.14:06:42.00#ibcon#about to read 6, iclass 22, count 0 2006.257.14:06:42.00#ibcon#read 6, iclass 22, count 0 2006.257.14:06:42.00#ibcon#end of sib2, iclass 22, count 0 2006.257.14:06:42.00#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:06:42.00#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:06:42.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:06:42.00#ibcon#*before write, iclass 22, count 0 2006.257.14:06:42.00#ibcon#enter sib2, iclass 22, count 0 2006.257.14:06:42.00#ibcon#flushed, iclass 22, count 0 2006.257.14:06:42.00#ibcon#about to write, iclass 22, count 0 2006.257.14:06:42.00#ibcon#wrote, iclass 22, count 0 2006.257.14:06:42.00#ibcon#about to read 3, iclass 22, count 0 2006.257.14:06:42.04#ibcon#read 3, iclass 22, count 0 2006.257.14:06:42.04#ibcon#about to read 4, iclass 22, count 0 2006.257.14:06:42.04#ibcon#read 4, iclass 22, count 0 2006.257.14:06:42.04#ibcon#about to read 5, iclass 22, count 0 2006.257.14:06:42.04#ibcon#read 5, iclass 22, count 0 2006.257.14:06:42.04#ibcon#about to read 6, iclass 22, count 0 2006.257.14:06:42.04#ibcon#read 6, iclass 22, count 0 2006.257.14:06:42.04#ibcon#end of sib2, iclass 22, count 0 2006.257.14:06:42.04#ibcon#*after write, iclass 22, count 0 2006.257.14:06:42.04#ibcon#*before return 0, iclass 22, count 0 2006.257.14:06:42.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:42.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:42.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:06:42.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:06:42.04$vck44/va=8,4 2006.257.14:06:42.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.14:06:42.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.14:06:42.04#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:42.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:42.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:42.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:42.10#ibcon#enter wrdev, iclass 24, count 2 2006.257.14:06:42.10#ibcon#first serial, iclass 24, count 2 2006.257.14:06:42.10#ibcon#enter sib2, iclass 24, count 2 2006.257.14:06:42.10#ibcon#flushed, iclass 24, count 2 2006.257.14:06:42.10#ibcon#about to write, iclass 24, count 2 2006.257.14:06:42.10#ibcon#wrote, iclass 24, count 2 2006.257.14:06:42.10#ibcon#about to read 3, iclass 24, count 2 2006.257.14:06:42.12#ibcon#read 3, iclass 24, count 2 2006.257.14:06:42.12#ibcon#about to read 4, iclass 24, count 2 2006.257.14:06:42.12#ibcon#read 4, iclass 24, count 2 2006.257.14:06:42.12#ibcon#about to read 5, iclass 24, count 2 2006.257.14:06:42.12#ibcon#read 5, iclass 24, count 2 2006.257.14:06:42.12#ibcon#about to read 6, iclass 24, count 2 2006.257.14:06:42.12#ibcon#read 6, iclass 24, count 2 2006.257.14:06:42.12#ibcon#end of sib2, iclass 24, count 2 2006.257.14:06:42.12#ibcon#*mode == 0, iclass 24, count 2 2006.257.14:06:42.12#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.14:06:42.12#ibcon#[25=AT08-04\r\n] 2006.257.14:06:42.12#ibcon#*before write, iclass 24, count 2 2006.257.14:06:42.12#ibcon#enter sib2, iclass 24, count 2 2006.257.14:06:42.12#ibcon#flushed, iclass 24, count 2 2006.257.14:06:42.12#ibcon#about to write, iclass 24, count 2 2006.257.14:06:42.12#ibcon#wrote, iclass 24, count 2 2006.257.14:06:42.12#ibcon#about to read 3, iclass 24, count 2 2006.257.14:06:42.15#ibcon#read 3, iclass 24, count 2 2006.257.14:06:42.98#ibcon#about to read 4, iclass 24, count 2 2006.257.14:06:42.98#ibcon#read 4, iclass 24, count 2 2006.257.14:06:42.98#ibcon#about to read 5, iclass 24, count 2 2006.257.14:06:42.98#ibcon#read 5, iclass 24, count 2 2006.257.14:06:42.98#ibcon#about to read 6, iclass 24, count 2 2006.257.14:06:42.98#ibcon#read 6, iclass 24, count 2 2006.257.14:06:42.98#ibcon#end of sib2, iclass 24, count 2 2006.257.14:06:42.98#ibcon#*after write, iclass 24, count 2 2006.257.14:06:42.98#ibcon#*before return 0, iclass 24, count 2 2006.257.14:06:42.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:42.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:42.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.14:06:42.98#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:42.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:43.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:43.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:43.10#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:06:43.10#ibcon#first serial, iclass 24, count 0 2006.257.14:06:43.10#ibcon#enter sib2, iclass 24, count 0 2006.257.14:06:43.10#ibcon#flushed, iclass 24, count 0 2006.257.14:06:43.10#ibcon#about to write, iclass 24, count 0 2006.257.14:06:43.10#ibcon#wrote, iclass 24, count 0 2006.257.14:06:43.10#ibcon#about to read 3, iclass 24, count 0 2006.257.14:06:43.12#ibcon#read 3, iclass 24, count 0 2006.257.14:06:43.12#ibcon#about to read 4, iclass 24, count 0 2006.257.14:06:43.12#ibcon#read 4, iclass 24, count 0 2006.257.14:06:43.12#ibcon#about to read 5, iclass 24, count 0 2006.257.14:06:43.12#ibcon#read 5, iclass 24, count 0 2006.257.14:06:43.12#ibcon#about to read 6, iclass 24, count 0 2006.257.14:06:43.12#ibcon#read 6, iclass 24, count 0 2006.257.14:06:43.12#ibcon#end of sib2, iclass 24, count 0 2006.257.14:06:43.12#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:06:43.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:06:43.12#ibcon#[25=USB\r\n] 2006.257.14:06:43.12#ibcon#*before write, iclass 24, count 0 2006.257.14:06:43.12#ibcon#enter sib2, iclass 24, count 0 2006.257.14:06:43.12#ibcon#flushed, iclass 24, count 0 2006.257.14:06:43.12#ibcon#about to write, iclass 24, count 0 2006.257.14:06:43.12#ibcon#wrote, iclass 24, count 0 2006.257.14:06:43.12#ibcon#about to read 3, iclass 24, count 0 2006.257.14:06:43.15#ibcon#read 3, iclass 24, count 0 2006.257.14:06:43.15#ibcon#about to read 4, iclass 24, count 0 2006.257.14:06:43.15#ibcon#read 4, iclass 24, count 0 2006.257.14:06:43.15#ibcon#about to read 5, iclass 24, count 0 2006.257.14:06:43.15#ibcon#read 5, iclass 24, count 0 2006.257.14:06:43.15#ibcon#about to read 6, iclass 24, count 0 2006.257.14:06:43.15#ibcon#read 6, iclass 24, count 0 2006.257.14:06:43.15#ibcon#end of sib2, iclass 24, count 0 2006.257.14:06:43.15#ibcon#*after write, iclass 24, count 0 2006.257.14:06:43.15#ibcon#*before return 0, iclass 24, count 0 2006.257.14:06:43.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:43.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:43.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:06:43.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:06:43.15$vck44/vblo=1,629.99 2006.257.14:06:43.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.14:06:43.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.14:06:43.15#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:43.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:43.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:43.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:43.15#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:06:43.15#ibcon#first serial, iclass 26, count 0 2006.257.14:06:43.15#ibcon#enter sib2, iclass 26, count 0 2006.257.14:06:43.15#ibcon#flushed, iclass 26, count 0 2006.257.14:06:43.15#ibcon#about to write, iclass 26, count 0 2006.257.14:06:43.15#ibcon#wrote, iclass 26, count 0 2006.257.14:06:43.15#ibcon#about to read 3, iclass 26, count 0 2006.257.14:06:43.17#ibcon#read 3, iclass 26, count 0 2006.257.14:06:43.17#ibcon#about to read 4, iclass 26, count 0 2006.257.14:06:43.17#ibcon#read 4, iclass 26, count 0 2006.257.14:06:43.17#ibcon#about to read 5, iclass 26, count 0 2006.257.14:06:43.17#ibcon#read 5, iclass 26, count 0 2006.257.14:06:43.17#ibcon#about to read 6, iclass 26, count 0 2006.257.14:06:43.17#ibcon#read 6, iclass 26, count 0 2006.257.14:06:43.17#ibcon#end of sib2, iclass 26, count 0 2006.257.14:06:43.17#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:06:43.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:06:43.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:06:43.17#ibcon#*before write, iclass 26, count 0 2006.257.14:06:43.17#ibcon#enter sib2, iclass 26, count 0 2006.257.14:06:43.17#ibcon#flushed, iclass 26, count 0 2006.257.14:06:43.17#ibcon#about to write, iclass 26, count 0 2006.257.14:06:43.17#ibcon#wrote, iclass 26, count 0 2006.257.14:06:43.17#ibcon#about to read 3, iclass 26, count 0 2006.257.14:06:43.21#ibcon#read 3, iclass 26, count 0 2006.257.14:06:43.21#ibcon#about to read 4, iclass 26, count 0 2006.257.14:06:43.21#ibcon#read 4, iclass 26, count 0 2006.257.14:06:43.21#ibcon#about to read 5, iclass 26, count 0 2006.257.14:06:43.21#ibcon#read 5, iclass 26, count 0 2006.257.14:06:43.21#ibcon#about to read 6, iclass 26, count 0 2006.257.14:06:43.21#ibcon#read 6, iclass 26, count 0 2006.257.14:06:43.21#ibcon#end of sib2, iclass 26, count 0 2006.257.14:06:43.21#ibcon#*after write, iclass 26, count 0 2006.257.14:06:43.21#ibcon#*before return 0, iclass 26, count 0 2006.257.14:06:43.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:43.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:43.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:06:43.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:06:43.21$vck44/vb=1,4 2006.257.14:06:43.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.14:06:43.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.14:06:43.21#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:43.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:06:43.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:06:43.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:06:43.21#ibcon#enter wrdev, iclass 28, count 2 2006.257.14:06:43.21#ibcon#first serial, iclass 28, count 2 2006.257.14:06:43.21#ibcon#enter sib2, iclass 28, count 2 2006.257.14:06:43.21#ibcon#flushed, iclass 28, count 2 2006.257.14:06:43.21#ibcon#about to write, iclass 28, count 2 2006.257.14:06:43.21#ibcon#wrote, iclass 28, count 2 2006.257.14:06:43.21#ibcon#about to read 3, iclass 28, count 2 2006.257.14:06:43.23#ibcon#read 3, iclass 28, count 2 2006.257.14:06:43.23#ibcon#about to read 4, iclass 28, count 2 2006.257.14:06:43.23#ibcon#read 4, iclass 28, count 2 2006.257.14:06:43.23#ibcon#about to read 5, iclass 28, count 2 2006.257.14:06:43.23#ibcon#read 5, iclass 28, count 2 2006.257.14:06:43.23#ibcon#about to read 6, iclass 28, count 2 2006.257.14:06:43.23#ibcon#read 6, iclass 28, count 2 2006.257.14:06:43.23#ibcon#end of sib2, iclass 28, count 2 2006.257.14:06:43.23#ibcon#*mode == 0, iclass 28, count 2 2006.257.14:06:43.23#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.14:06:43.23#ibcon#[27=AT01-04\r\n] 2006.257.14:06:43.23#ibcon#*before write, iclass 28, count 2 2006.257.14:06:43.23#ibcon#enter sib2, iclass 28, count 2 2006.257.14:06:43.23#ibcon#flushed, iclass 28, count 2 2006.257.14:06:43.23#ibcon#about to write, iclass 28, count 2 2006.257.14:06:43.23#ibcon#wrote, iclass 28, count 2 2006.257.14:06:43.23#ibcon#about to read 3, iclass 28, count 2 2006.257.14:06:43.26#ibcon#read 3, iclass 28, count 2 2006.257.14:06:43.26#ibcon#about to read 4, iclass 28, count 2 2006.257.14:06:43.26#ibcon#read 4, iclass 28, count 2 2006.257.14:06:43.26#ibcon#about to read 5, iclass 28, count 2 2006.257.14:06:43.26#ibcon#read 5, iclass 28, count 2 2006.257.14:06:43.26#ibcon#about to read 6, iclass 28, count 2 2006.257.14:06:43.26#ibcon#read 6, iclass 28, count 2 2006.257.14:06:43.26#ibcon#end of sib2, iclass 28, count 2 2006.257.14:06:43.26#ibcon#*after write, iclass 28, count 2 2006.257.14:06:43.26#ibcon#*before return 0, iclass 28, count 2 2006.257.14:06:43.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:06:43.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:06:43.26#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.14:06:43.26#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:43.26#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:06:43.38#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:06:43.38#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:06:43.38#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:06:43.38#ibcon#first serial, iclass 28, count 0 2006.257.14:06:43.38#ibcon#enter sib2, iclass 28, count 0 2006.257.14:06:43.38#ibcon#flushed, iclass 28, count 0 2006.257.14:06:43.38#ibcon#about to write, iclass 28, count 0 2006.257.14:06:43.38#ibcon#wrote, iclass 28, count 0 2006.257.14:06:43.38#ibcon#about to read 3, iclass 28, count 0 2006.257.14:06:43.40#ibcon#read 3, iclass 28, count 0 2006.257.14:06:43.40#ibcon#about to read 4, iclass 28, count 0 2006.257.14:06:43.40#ibcon#read 4, iclass 28, count 0 2006.257.14:06:43.40#ibcon#about to read 5, iclass 28, count 0 2006.257.14:06:43.40#ibcon#read 5, iclass 28, count 0 2006.257.14:06:43.40#ibcon#about to read 6, iclass 28, count 0 2006.257.14:06:43.40#ibcon#read 6, iclass 28, count 0 2006.257.14:06:43.40#ibcon#end of sib2, iclass 28, count 0 2006.257.14:06:43.40#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:06:43.40#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:06:43.40#ibcon#[27=USB\r\n] 2006.257.14:06:43.40#ibcon#*before write, iclass 28, count 0 2006.257.14:06:43.40#ibcon#enter sib2, iclass 28, count 0 2006.257.14:06:43.40#ibcon#flushed, iclass 28, count 0 2006.257.14:06:43.40#ibcon#about to write, iclass 28, count 0 2006.257.14:06:43.40#ibcon#wrote, iclass 28, count 0 2006.257.14:06:43.40#ibcon#about to read 3, iclass 28, count 0 2006.257.14:06:43.43#ibcon#read 3, iclass 28, count 0 2006.257.14:06:43.43#ibcon#about to read 4, iclass 28, count 0 2006.257.14:06:43.43#ibcon#read 4, iclass 28, count 0 2006.257.14:06:43.43#ibcon#about to read 5, iclass 28, count 0 2006.257.14:06:43.43#ibcon#read 5, iclass 28, count 0 2006.257.14:06:43.43#ibcon#about to read 6, iclass 28, count 0 2006.257.14:06:43.43#ibcon#read 6, iclass 28, count 0 2006.257.14:06:43.43#ibcon#end of sib2, iclass 28, count 0 2006.257.14:06:43.43#ibcon#*after write, iclass 28, count 0 2006.257.14:06:43.43#ibcon#*before return 0, iclass 28, count 0 2006.257.14:06:43.43#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:06:43.43#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:06:43.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:06:43.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:06:43.43$vck44/vblo=2,634.99 2006.257.14:06:43.43#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.14:06:43.43#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.14:06:43.43#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:43.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:43.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:43.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:43.43#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:06:43.43#ibcon#first serial, iclass 30, count 0 2006.257.14:06:43.43#ibcon#enter sib2, iclass 30, count 0 2006.257.14:06:43.43#ibcon#flushed, iclass 30, count 0 2006.257.14:06:43.43#ibcon#about to write, iclass 30, count 0 2006.257.14:06:43.43#ibcon#wrote, iclass 30, count 0 2006.257.14:06:43.43#ibcon#about to read 3, iclass 30, count 0 2006.257.14:06:43.45#ibcon#read 3, iclass 30, count 0 2006.257.14:06:43.45#ibcon#about to read 4, iclass 30, count 0 2006.257.14:06:43.45#ibcon#read 4, iclass 30, count 0 2006.257.14:06:43.45#ibcon#about to read 5, iclass 30, count 0 2006.257.14:06:43.45#ibcon#read 5, iclass 30, count 0 2006.257.14:06:43.45#ibcon#about to read 6, iclass 30, count 0 2006.257.14:06:43.45#ibcon#read 6, iclass 30, count 0 2006.257.14:06:43.45#ibcon#end of sib2, iclass 30, count 0 2006.257.14:06:43.45#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:06:43.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:06:43.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:06:43.45#ibcon#*before write, iclass 30, count 0 2006.257.14:06:43.45#ibcon#enter sib2, iclass 30, count 0 2006.257.14:06:43.45#ibcon#flushed, iclass 30, count 0 2006.257.14:06:43.45#ibcon#about to write, iclass 30, count 0 2006.257.14:06:43.45#ibcon#wrote, iclass 30, count 0 2006.257.14:06:43.45#ibcon#about to read 3, iclass 30, count 0 2006.257.14:06:43.49#ibcon#read 3, iclass 30, count 0 2006.257.14:06:43.49#ibcon#about to read 4, iclass 30, count 0 2006.257.14:06:43.49#ibcon#read 4, iclass 30, count 0 2006.257.14:06:43.49#ibcon#about to read 5, iclass 30, count 0 2006.257.14:06:43.49#ibcon#read 5, iclass 30, count 0 2006.257.14:06:43.49#ibcon#about to read 6, iclass 30, count 0 2006.257.14:06:43.49#ibcon#read 6, iclass 30, count 0 2006.257.14:06:43.49#ibcon#end of sib2, iclass 30, count 0 2006.257.14:06:43.49#ibcon#*after write, iclass 30, count 0 2006.257.14:06:43.49#ibcon#*before return 0, iclass 30, count 0 2006.257.14:06:43.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:43.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:06:43.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:06:43.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:06:43.49$vck44/vb=2,5 2006.257.14:06:43.49#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.14:06:43.49#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.14:06:43.49#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:43.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:43.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:43.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:43.55#ibcon#enter wrdev, iclass 32, count 2 2006.257.14:06:43.55#ibcon#first serial, iclass 32, count 2 2006.257.14:06:43.55#ibcon#enter sib2, iclass 32, count 2 2006.257.14:06:43.55#ibcon#flushed, iclass 32, count 2 2006.257.14:06:43.55#ibcon#about to write, iclass 32, count 2 2006.257.14:06:43.55#ibcon#wrote, iclass 32, count 2 2006.257.14:06:43.55#ibcon#about to read 3, iclass 32, count 2 2006.257.14:06:43.57#ibcon#read 3, iclass 32, count 2 2006.257.14:06:43.57#ibcon#about to read 4, iclass 32, count 2 2006.257.14:06:43.57#ibcon#read 4, iclass 32, count 2 2006.257.14:06:43.57#ibcon#about to read 5, iclass 32, count 2 2006.257.14:06:43.57#ibcon#read 5, iclass 32, count 2 2006.257.14:06:43.57#ibcon#about to read 6, iclass 32, count 2 2006.257.14:06:43.57#ibcon#read 6, iclass 32, count 2 2006.257.14:06:43.57#ibcon#end of sib2, iclass 32, count 2 2006.257.14:06:43.57#ibcon#*mode == 0, iclass 32, count 2 2006.257.14:06:43.57#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.14:06:43.57#ibcon#[27=AT02-05\r\n] 2006.257.14:06:43.57#ibcon#*before write, iclass 32, count 2 2006.257.14:06:43.57#ibcon#enter sib2, iclass 32, count 2 2006.257.14:06:43.57#ibcon#flushed, iclass 32, count 2 2006.257.14:06:43.57#ibcon#about to write, iclass 32, count 2 2006.257.14:06:43.57#ibcon#wrote, iclass 32, count 2 2006.257.14:06:43.57#ibcon#about to read 3, iclass 32, count 2 2006.257.14:06:43.60#ibcon#read 3, iclass 32, count 2 2006.257.14:06:43.60#ibcon#about to read 4, iclass 32, count 2 2006.257.14:06:43.60#ibcon#read 4, iclass 32, count 2 2006.257.14:06:43.60#ibcon#about to read 5, iclass 32, count 2 2006.257.14:06:43.60#ibcon#read 5, iclass 32, count 2 2006.257.14:06:43.60#ibcon#about to read 6, iclass 32, count 2 2006.257.14:06:43.60#ibcon#read 6, iclass 32, count 2 2006.257.14:06:43.60#ibcon#end of sib2, iclass 32, count 2 2006.257.14:06:43.60#ibcon#*after write, iclass 32, count 2 2006.257.14:06:43.60#ibcon#*before return 0, iclass 32, count 2 2006.257.14:06:43.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:43.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:06:43.60#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.14:06:43.60#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:43.60#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:43.72#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:43.72#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:43.72#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:06:43.72#ibcon#first serial, iclass 32, count 0 2006.257.14:06:43.72#ibcon#enter sib2, iclass 32, count 0 2006.257.14:06:43.72#ibcon#flushed, iclass 32, count 0 2006.257.14:06:43.72#ibcon#about to write, iclass 32, count 0 2006.257.14:06:43.72#ibcon#wrote, iclass 32, count 0 2006.257.14:06:43.72#ibcon#about to read 3, iclass 32, count 0 2006.257.14:06:43.74#ibcon#read 3, iclass 32, count 0 2006.257.14:06:43.74#ibcon#about to read 4, iclass 32, count 0 2006.257.14:06:43.74#ibcon#read 4, iclass 32, count 0 2006.257.14:06:43.74#ibcon#about to read 5, iclass 32, count 0 2006.257.14:06:43.74#ibcon#read 5, iclass 32, count 0 2006.257.14:06:43.74#ibcon#about to read 6, iclass 32, count 0 2006.257.14:06:43.74#ibcon#read 6, iclass 32, count 0 2006.257.14:06:43.74#ibcon#end of sib2, iclass 32, count 0 2006.257.14:06:43.74#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:06:43.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:06:43.74#ibcon#[27=USB\r\n] 2006.257.14:06:43.74#ibcon#*before write, iclass 32, count 0 2006.257.14:06:43.74#ibcon#enter sib2, iclass 32, count 0 2006.257.14:06:43.74#ibcon#flushed, iclass 32, count 0 2006.257.14:06:43.74#ibcon#about to write, iclass 32, count 0 2006.257.14:06:43.74#ibcon#wrote, iclass 32, count 0 2006.257.14:06:43.74#ibcon#about to read 3, iclass 32, count 0 2006.257.14:06:43.77#ibcon#read 3, iclass 32, count 0 2006.257.14:06:43.77#ibcon#about to read 4, iclass 32, count 0 2006.257.14:06:43.77#ibcon#read 4, iclass 32, count 0 2006.257.14:06:43.77#ibcon#about to read 5, iclass 32, count 0 2006.257.14:06:43.77#ibcon#read 5, iclass 32, count 0 2006.257.14:06:43.77#ibcon#about to read 6, iclass 32, count 0 2006.257.14:06:43.77#ibcon#read 6, iclass 32, count 0 2006.257.14:06:43.77#ibcon#end of sib2, iclass 32, count 0 2006.257.14:06:43.77#ibcon#*after write, iclass 32, count 0 2006.257.14:06:43.77#ibcon#*before return 0, iclass 32, count 0 2006.257.14:06:43.77#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:43.77#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:06:43.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:06:43.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:06:43.77$vck44/vblo=3,649.99 2006.257.14:06:43.77#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.14:06:43.77#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.14:06:43.77#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:43.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:43.77#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:43.77#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:43.77#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:06:43.77#ibcon#first serial, iclass 34, count 0 2006.257.14:06:43.77#ibcon#enter sib2, iclass 34, count 0 2006.257.14:06:43.77#ibcon#flushed, iclass 34, count 0 2006.257.14:06:43.77#ibcon#about to write, iclass 34, count 0 2006.257.14:06:43.77#ibcon#wrote, iclass 34, count 0 2006.257.14:06:43.77#ibcon#about to read 3, iclass 34, count 0 2006.257.14:06:43.79#ibcon#read 3, iclass 34, count 0 2006.257.14:06:43.79#ibcon#about to read 4, iclass 34, count 0 2006.257.14:06:43.79#ibcon#read 4, iclass 34, count 0 2006.257.14:06:43.79#ibcon#about to read 5, iclass 34, count 0 2006.257.14:06:43.79#ibcon#read 5, iclass 34, count 0 2006.257.14:06:43.79#ibcon#about to read 6, iclass 34, count 0 2006.257.14:06:43.79#ibcon#read 6, iclass 34, count 0 2006.257.14:06:43.79#ibcon#end of sib2, iclass 34, count 0 2006.257.14:06:43.79#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:06:43.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:06:43.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:06:43.79#ibcon#*before write, iclass 34, count 0 2006.257.14:06:43.79#ibcon#enter sib2, iclass 34, count 0 2006.257.14:06:43.79#ibcon#flushed, iclass 34, count 0 2006.257.14:06:43.79#ibcon#about to write, iclass 34, count 0 2006.257.14:06:43.79#ibcon#wrote, iclass 34, count 0 2006.257.14:06:43.79#ibcon#about to read 3, iclass 34, count 0 2006.257.14:06:43.83#ibcon#read 3, iclass 34, count 0 2006.257.14:06:43.83#ibcon#about to read 4, iclass 34, count 0 2006.257.14:06:43.83#ibcon#read 4, iclass 34, count 0 2006.257.14:06:43.83#ibcon#about to read 5, iclass 34, count 0 2006.257.14:06:43.83#ibcon#read 5, iclass 34, count 0 2006.257.14:06:43.83#ibcon#about to read 6, iclass 34, count 0 2006.257.14:06:43.83#ibcon#read 6, iclass 34, count 0 2006.257.14:06:43.83#ibcon#end of sib2, iclass 34, count 0 2006.257.14:06:43.83#ibcon#*after write, iclass 34, count 0 2006.257.14:06:43.83#ibcon#*before return 0, iclass 34, count 0 2006.257.14:06:43.83#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:43.83#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:06:43.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:06:43.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:06:43.83$vck44/vb=3,4 2006.257.14:06:43.83#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.14:06:43.83#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.14:06:43.83#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:43.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:43.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:43.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:43.89#ibcon#enter wrdev, iclass 36, count 2 2006.257.14:06:43.89#ibcon#first serial, iclass 36, count 2 2006.257.14:06:43.89#ibcon#enter sib2, iclass 36, count 2 2006.257.14:06:43.89#ibcon#flushed, iclass 36, count 2 2006.257.14:06:43.89#ibcon#about to write, iclass 36, count 2 2006.257.14:06:43.89#ibcon#wrote, iclass 36, count 2 2006.257.14:06:43.89#ibcon#about to read 3, iclass 36, count 2 2006.257.14:06:43.91#ibcon#read 3, iclass 36, count 2 2006.257.14:06:43.91#ibcon#about to read 4, iclass 36, count 2 2006.257.14:06:43.91#ibcon#read 4, iclass 36, count 2 2006.257.14:06:43.91#ibcon#about to read 5, iclass 36, count 2 2006.257.14:06:43.91#ibcon#read 5, iclass 36, count 2 2006.257.14:06:43.91#ibcon#about to read 6, iclass 36, count 2 2006.257.14:06:43.91#ibcon#read 6, iclass 36, count 2 2006.257.14:06:43.91#ibcon#end of sib2, iclass 36, count 2 2006.257.14:06:43.91#ibcon#*mode == 0, iclass 36, count 2 2006.257.14:06:43.91#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.14:06:43.91#ibcon#[27=AT03-04\r\n] 2006.257.14:06:43.91#ibcon#*before write, iclass 36, count 2 2006.257.14:06:43.91#ibcon#enter sib2, iclass 36, count 2 2006.257.14:06:43.91#ibcon#flushed, iclass 36, count 2 2006.257.14:06:43.91#ibcon#about to write, iclass 36, count 2 2006.257.14:06:43.91#ibcon#wrote, iclass 36, count 2 2006.257.14:06:43.91#ibcon#about to read 3, iclass 36, count 2 2006.257.14:06:43.94#ibcon#read 3, iclass 36, count 2 2006.257.14:06:43.94#ibcon#about to read 4, iclass 36, count 2 2006.257.14:06:43.94#ibcon#read 4, iclass 36, count 2 2006.257.14:06:43.94#ibcon#about to read 5, iclass 36, count 2 2006.257.14:06:43.94#ibcon#read 5, iclass 36, count 2 2006.257.14:06:43.94#ibcon#about to read 6, iclass 36, count 2 2006.257.14:06:43.94#ibcon#read 6, iclass 36, count 2 2006.257.14:06:43.94#ibcon#end of sib2, iclass 36, count 2 2006.257.14:06:43.94#ibcon#*after write, iclass 36, count 2 2006.257.14:06:43.94#ibcon#*before return 0, iclass 36, count 2 2006.257.14:06:43.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:43.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:06:43.94#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.14:06:43.94#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:43.94#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:44.06#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:44.06#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:44.06#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:06:44.06#ibcon#first serial, iclass 36, count 0 2006.257.14:06:44.06#ibcon#enter sib2, iclass 36, count 0 2006.257.14:06:44.06#ibcon#flushed, iclass 36, count 0 2006.257.14:06:44.06#ibcon#about to write, iclass 36, count 0 2006.257.14:06:44.06#ibcon#wrote, iclass 36, count 0 2006.257.14:06:44.06#ibcon#about to read 3, iclass 36, count 0 2006.257.14:06:44.08#ibcon#read 3, iclass 36, count 0 2006.257.14:06:44.08#ibcon#about to read 4, iclass 36, count 0 2006.257.14:06:44.08#ibcon#read 4, iclass 36, count 0 2006.257.14:06:44.08#ibcon#about to read 5, iclass 36, count 0 2006.257.14:06:44.08#ibcon#read 5, iclass 36, count 0 2006.257.14:06:44.08#ibcon#about to read 6, iclass 36, count 0 2006.257.14:06:44.08#ibcon#read 6, iclass 36, count 0 2006.257.14:06:44.08#ibcon#end of sib2, iclass 36, count 0 2006.257.14:06:44.08#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:06:44.08#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:06:44.08#ibcon#[27=USB\r\n] 2006.257.14:06:44.08#ibcon#*before write, iclass 36, count 0 2006.257.14:06:44.08#ibcon#enter sib2, iclass 36, count 0 2006.257.14:06:44.08#ibcon#flushed, iclass 36, count 0 2006.257.14:06:44.08#ibcon#about to write, iclass 36, count 0 2006.257.14:06:44.08#ibcon#wrote, iclass 36, count 0 2006.257.14:06:44.08#ibcon#about to read 3, iclass 36, count 0 2006.257.14:06:44.11#ibcon#read 3, iclass 36, count 0 2006.257.14:06:44.11#ibcon#about to read 4, iclass 36, count 0 2006.257.14:06:44.11#ibcon#read 4, iclass 36, count 0 2006.257.14:06:44.11#ibcon#about to read 5, iclass 36, count 0 2006.257.14:06:44.80#ibcon#read 5, iclass 36, count 0 2006.257.14:06:44.80#ibcon#about to read 6, iclass 36, count 0 2006.257.14:06:44.80#ibcon#read 6, iclass 36, count 0 2006.257.14:06:44.80#ibcon#end of sib2, iclass 36, count 0 2006.257.14:06:44.80#ibcon#*after write, iclass 36, count 0 2006.257.14:06:44.80#ibcon#*before return 0, iclass 36, count 0 2006.257.14:06:44.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:44.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:06:44.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:06:44.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:06:44.80$vck44/vblo=4,679.99 2006.257.14:06:44.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.14:06:44.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.14:06:44.81#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:44.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:44.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:44.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:44.81#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:06:44.81#ibcon#first serial, iclass 38, count 0 2006.257.14:06:44.81#ibcon#enter sib2, iclass 38, count 0 2006.257.14:06:44.81#ibcon#flushed, iclass 38, count 0 2006.257.14:06:44.81#ibcon#about to write, iclass 38, count 0 2006.257.14:06:44.81#ibcon#wrote, iclass 38, count 0 2006.257.14:06:44.81#ibcon#about to read 3, iclass 38, count 0 2006.257.14:06:44.82#ibcon#read 3, iclass 38, count 0 2006.257.14:06:44.82#ibcon#about to read 4, iclass 38, count 0 2006.257.14:06:44.82#ibcon#read 4, iclass 38, count 0 2006.257.14:06:44.82#ibcon#about to read 5, iclass 38, count 0 2006.257.14:06:44.82#ibcon#read 5, iclass 38, count 0 2006.257.14:06:44.82#ibcon#about to read 6, iclass 38, count 0 2006.257.14:06:44.82#ibcon#read 6, iclass 38, count 0 2006.257.14:06:44.82#ibcon#end of sib2, iclass 38, count 0 2006.257.14:06:44.82#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:06:44.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:06:44.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:06:44.82#ibcon#*before write, iclass 38, count 0 2006.257.14:06:44.82#ibcon#enter sib2, iclass 38, count 0 2006.257.14:06:44.82#ibcon#flushed, iclass 38, count 0 2006.257.14:06:44.82#ibcon#about to write, iclass 38, count 0 2006.257.14:06:44.82#ibcon#wrote, iclass 38, count 0 2006.257.14:06:44.82#ibcon#about to read 3, iclass 38, count 0 2006.257.14:06:44.86#ibcon#read 3, iclass 38, count 0 2006.257.14:06:44.86#ibcon#about to read 4, iclass 38, count 0 2006.257.14:06:44.86#ibcon#read 4, iclass 38, count 0 2006.257.14:06:44.86#ibcon#about to read 5, iclass 38, count 0 2006.257.14:06:44.86#ibcon#read 5, iclass 38, count 0 2006.257.14:06:44.86#ibcon#about to read 6, iclass 38, count 0 2006.257.14:06:44.86#ibcon#read 6, iclass 38, count 0 2006.257.14:06:44.86#ibcon#end of sib2, iclass 38, count 0 2006.257.14:06:44.86#ibcon#*after write, iclass 38, count 0 2006.257.14:06:44.86#ibcon#*before return 0, iclass 38, count 0 2006.257.14:06:44.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:44.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:06:44.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:06:44.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:06:44.86$vck44/vb=4,5 2006.257.14:06:44.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.14:06:44.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.14:06:44.86#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:44.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:44.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:44.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:44.92#ibcon#enter wrdev, iclass 40, count 2 2006.257.14:06:44.92#ibcon#first serial, iclass 40, count 2 2006.257.14:06:44.92#ibcon#enter sib2, iclass 40, count 2 2006.257.14:06:44.92#ibcon#flushed, iclass 40, count 2 2006.257.14:06:44.92#ibcon#about to write, iclass 40, count 2 2006.257.14:06:44.92#ibcon#wrote, iclass 40, count 2 2006.257.14:06:44.92#ibcon#about to read 3, iclass 40, count 2 2006.257.14:06:44.94#ibcon#read 3, iclass 40, count 2 2006.257.14:06:44.94#ibcon#about to read 4, iclass 40, count 2 2006.257.14:06:44.94#ibcon#read 4, iclass 40, count 2 2006.257.14:06:44.94#ibcon#about to read 5, iclass 40, count 2 2006.257.14:06:44.94#ibcon#read 5, iclass 40, count 2 2006.257.14:06:44.94#ibcon#about to read 6, iclass 40, count 2 2006.257.14:06:44.94#ibcon#read 6, iclass 40, count 2 2006.257.14:06:44.94#ibcon#end of sib2, iclass 40, count 2 2006.257.14:06:44.94#ibcon#*mode == 0, iclass 40, count 2 2006.257.14:06:44.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.14:06:44.94#ibcon#[27=AT04-05\r\n] 2006.257.14:06:44.94#ibcon#*before write, iclass 40, count 2 2006.257.14:06:44.94#ibcon#enter sib2, iclass 40, count 2 2006.257.14:06:44.94#ibcon#flushed, iclass 40, count 2 2006.257.14:06:44.94#ibcon#about to write, iclass 40, count 2 2006.257.14:06:44.94#ibcon#wrote, iclass 40, count 2 2006.257.14:06:44.94#ibcon#about to read 3, iclass 40, count 2 2006.257.14:06:44.97#ibcon#read 3, iclass 40, count 2 2006.257.14:06:44.97#ibcon#about to read 4, iclass 40, count 2 2006.257.14:06:44.97#ibcon#read 4, iclass 40, count 2 2006.257.14:06:44.97#ibcon#about to read 5, iclass 40, count 2 2006.257.14:06:44.97#ibcon#read 5, iclass 40, count 2 2006.257.14:06:44.97#ibcon#about to read 6, iclass 40, count 2 2006.257.14:06:44.97#ibcon#read 6, iclass 40, count 2 2006.257.14:06:44.97#ibcon#end of sib2, iclass 40, count 2 2006.257.14:06:44.97#ibcon#*after write, iclass 40, count 2 2006.257.14:06:44.97#ibcon#*before return 0, iclass 40, count 2 2006.257.14:06:44.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:44.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:06:44.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.14:06:44.97#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:44.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:45.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:45.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:45.09#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:06:45.09#ibcon#first serial, iclass 40, count 0 2006.257.14:06:45.09#ibcon#enter sib2, iclass 40, count 0 2006.257.14:06:45.09#ibcon#flushed, iclass 40, count 0 2006.257.14:06:45.09#ibcon#about to write, iclass 40, count 0 2006.257.14:06:45.09#ibcon#wrote, iclass 40, count 0 2006.257.14:06:45.09#ibcon#about to read 3, iclass 40, count 0 2006.257.14:06:45.11#ibcon#read 3, iclass 40, count 0 2006.257.14:06:45.11#ibcon#about to read 4, iclass 40, count 0 2006.257.14:06:45.11#ibcon#read 4, iclass 40, count 0 2006.257.14:06:45.11#ibcon#about to read 5, iclass 40, count 0 2006.257.14:06:45.11#ibcon#read 5, iclass 40, count 0 2006.257.14:06:45.11#ibcon#about to read 6, iclass 40, count 0 2006.257.14:06:45.11#ibcon#read 6, iclass 40, count 0 2006.257.14:06:45.11#ibcon#end of sib2, iclass 40, count 0 2006.257.14:06:45.11#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:06:45.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:06:45.11#ibcon#[27=USB\r\n] 2006.257.14:06:45.11#ibcon#*before write, iclass 40, count 0 2006.257.14:06:45.11#ibcon#enter sib2, iclass 40, count 0 2006.257.14:06:45.11#ibcon#flushed, iclass 40, count 0 2006.257.14:06:45.11#ibcon#about to write, iclass 40, count 0 2006.257.14:06:45.11#ibcon#wrote, iclass 40, count 0 2006.257.14:06:45.11#ibcon#about to read 3, iclass 40, count 0 2006.257.14:06:45.14#ibcon#read 3, iclass 40, count 0 2006.257.14:06:45.14#ibcon#about to read 4, iclass 40, count 0 2006.257.14:06:45.14#ibcon#read 4, iclass 40, count 0 2006.257.14:06:45.14#ibcon#about to read 5, iclass 40, count 0 2006.257.14:06:45.14#ibcon#read 5, iclass 40, count 0 2006.257.14:06:45.14#ibcon#about to read 6, iclass 40, count 0 2006.257.14:06:45.14#ibcon#read 6, iclass 40, count 0 2006.257.14:06:45.14#ibcon#end of sib2, iclass 40, count 0 2006.257.14:06:45.14#ibcon#*after write, iclass 40, count 0 2006.257.14:06:45.14#ibcon#*before return 0, iclass 40, count 0 2006.257.14:06:45.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:45.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:06:45.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:06:45.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:06:45.14$vck44/vblo=5,709.99 2006.257.14:06:45.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.14:06:45.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.14:06:45.14#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:45.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:45.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:45.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:45.14#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:06:45.14#ibcon#first serial, iclass 4, count 0 2006.257.14:06:45.14#ibcon#enter sib2, iclass 4, count 0 2006.257.14:06:45.14#ibcon#flushed, iclass 4, count 0 2006.257.14:06:45.14#ibcon#about to write, iclass 4, count 0 2006.257.14:06:45.14#ibcon#wrote, iclass 4, count 0 2006.257.14:06:45.14#ibcon#about to read 3, iclass 4, count 0 2006.257.14:06:45.16#ibcon#read 3, iclass 4, count 0 2006.257.14:06:45.16#ibcon#about to read 4, iclass 4, count 0 2006.257.14:06:45.16#ibcon#read 4, iclass 4, count 0 2006.257.14:06:45.16#ibcon#about to read 5, iclass 4, count 0 2006.257.14:06:45.16#ibcon#read 5, iclass 4, count 0 2006.257.14:06:45.16#ibcon#about to read 6, iclass 4, count 0 2006.257.14:06:45.16#ibcon#read 6, iclass 4, count 0 2006.257.14:06:45.16#ibcon#end of sib2, iclass 4, count 0 2006.257.14:06:45.16#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:06:45.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:06:45.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:06:45.16#ibcon#*before write, iclass 4, count 0 2006.257.14:06:45.16#ibcon#enter sib2, iclass 4, count 0 2006.257.14:06:45.16#ibcon#flushed, iclass 4, count 0 2006.257.14:06:45.16#ibcon#about to write, iclass 4, count 0 2006.257.14:06:45.16#ibcon#wrote, iclass 4, count 0 2006.257.14:06:45.16#ibcon#about to read 3, iclass 4, count 0 2006.257.14:06:45.20#ibcon#read 3, iclass 4, count 0 2006.257.14:06:45.20#ibcon#about to read 4, iclass 4, count 0 2006.257.14:06:45.20#ibcon#read 4, iclass 4, count 0 2006.257.14:06:45.20#ibcon#about to read 5, iclass 4, count 0 2006.257.14:06:45.20#ibcon#read 5, iclass 4, count 0 2006.257.14:06:45.20#ibcon#about to read 6, iclass 4, count 0 2006.257.14:06:45.20#ibcon#read 6, iclass 4, count 0 2006.257.14:06:45.20#ibcon#end of sib2, iclass 4, count 0 2006.257.14:06:45.20#ibcon#*after write, iclass 4, count 0 2006.257.14:06:45.20#ibcon#*before return 0, iclass 4, count 0 2006.257.14:06:45.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:45.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:06:45.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:06:45.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:06:45.20$vck44/vb=5,4 2006.257.14:06:45.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.14:06:45.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.14:06:45.20#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:45.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:45.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:45.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:45.26#ibcon#enter wrdev, iclass 6, count 2 2006.257.14:06:45.26#ibcon#first serial, iclass 6, count 2 2006.257.14:06:45.26#ibcon#enter sib2, iclass 6, count 2 2006.257.14:06:45.26#ibcon#flushed, iclass 6, count 2 2006.257.14:06:45.26#ibcon#about to write, iclass 6, count 2 2006.257.14:06:45.26#ibcon#wrote, iclass 6, count 2 2006.257.14:06:45.26#ibcon#about to read 3, iclass 6, count 2 2006.257.14:06:45.28#ibcon#read 3, iclass 6, count 2 2006.257.14:06:45.28#ibcon#about to read 4, iclass 6, count 2 2006.257.14:06:45.28#ibcon#read 4, iclass 6, count 2 2006.257.14:06:45.28#ibcon#about to read 5, iclass 6, count 2 2006.257.14:06:45.28#ibcon#read 5, iclass 6, count 2 2006.257.14:06:45.28#ibcon#about to read 6, iclass 6, count 2 2006.257.14:06:45.28#ibcon#read 6, iclass 6, count 2 2006.257.14:06:45.28#ibcon#end of sib2, iclass 6, count 2 2006.257.14:06:45.28#ibcon#*mode == 0, iclass 6, count 2 2006.257.14:06:45.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.14:06:45.28#ibcon#[27=AT05-04\r\n] 2006.257.14:06:45.28#ibcon#*before write, iclass 6, count 2 2006.257.14:06:45.28#ibcon#enter sib2, iclass 6, count 2 2006.257.14:06:45.28#ibcon#flushed, iclass 6, count 2 2006.257.14:06:45.28#ibcon#about to write, iclass 6, count 2 2006.257.14:06:45.28#ibcon#wrote, iclass 6, count 2 2006.257.14:06:45.28#ibcon#about to read 3, iclass 6, count 2 2006.257.14:06:45.31#ibcon#read 3, iclass 6, count 2 2006.257.14:06:45.31#ibcon#about to read 4, iclass 6, count 2 2006.257.14:06:45.31#ibcon#read 4, iclass 6, count 2 2006.257.14:06:45.31#ibcon#about to read 5, iclass 6, count 2 2006.257.14:06:45.31#ibcon#read 5, iclass 6, count 2 2006.257.14:06:45.31#ibcon#about to read 6, iclass 6, count 2 2006.257.14:06:45.31#ibcon#read 6, iclass 6, count 2 2006.257.14:06:45.31#ibcon#end of sib2, iclass 6, count 2 2006.257.14:06:45.31#ibcon#*after write, iclass 6, count 2 2006.257.14:06:45.31#ibcon#*before return 0, iclass 6, count 2 2006.257.14:06:45.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:45.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:06:45.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.14:06:45.31#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:45.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:45.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:45.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:45.43#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:06:45.43#ibcon#first serial, iclass 6, count 0 2006.257.14:06:45.43#ibcon#enter sib2, iclass 6, count 0 2006.257.14:06:45.43#ibcon#flushed, iclass 6, count 0 2006.257.14:06:45.43#ibcon#about to write, iclass 6, count 0 2006.257.14:06:45.43#ibcon#wrote, iclass 6, count 0 2006.257.14:06:45.43#ibcon#about to read 3, iclass 6, count 0 2006.257.14:06:45.45#ibcon#read 3, iclass 6, count 0 2006.257.14:06:45.45#ibcon#about to read 4, iclass 6, count 0 2006.257.14:06:45.45#ibcon#read 4, iclass 6, count 0 2006.257.14:06:45.45#ibcon#about to read 5, iclass 6, count 0 2006.257.14:06:45.45#ibcon#read 5, iclass 6, count 0 2006.257.14:06:45.45#ibcon#about to read 6, iclass 6, count 0 2006.257.14:06:45.45#ibcon#read 6, iclass 6, count 0 2006.257.14:06:45.45#ibcon#end of sib2, iclass 6, count 0 2006.257.14:06:45.45#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:06:45.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:06:45.45#ibcon#[27=USB\r\n] 2006.257.14:06:45.45#ibcon#*before write, iclass 6, count 0 2006.257.14:06:45.45#ibcon#enter sib2, iclass 6, count 0 2006.257.14:06:45.45#ibcon#flushed, iclass 6, count 0 2006.257.14:06:45.45#ibcon#about to write, iclass 6, count 0 2006.257.14:06:45.45#ibcon#wrote, iclass 6, count 0 2006.257.14:06:45.45#ibcon#about to read 3, iclass 6, count 0 2006.257.14:06:45.48#ibcon#read 3, iclass 6, count 0 2006.257.14:06:45.48#ibcon#about to read 4, iclass 6, count 0 2006.257.14:06:45.48#ibcon#read 4, iclass 6, count 0 2006.257.14:06:45.48#ibcon#about to read 5, iclass 6, count 0 2006.257.14:06:45.48#ibcon#read 5, iclass 6, count 0 2006.257.14:06:45.48#ibcon#about to read 6, iclass 6, count 0 2006.257.14:06:45.48#ibcon#read 6, iclass 6, count 0 2006.257.14:06:45.48#ibcon#end of sib2, iclass 6, count 0 2006.257.14:06:45.48#ibcon#*after write, iclass 6, count 0 2006.257.14:06:45.48#ibcon#*before return 0, iclass 6, count 0 2006.257.14:06:45.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:45.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:06:45.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:06:45.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:06:45.48$vck44/vblo=6,719.99 2006.257.14:06:45.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.14:06:45.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.14:06:45.48#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:45.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:45.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:45.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:45.48#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:06:45.48#ibcon#first serial, iclass 10, count 0 2006.257.14:06:45.48#ibcon#enter sib2, iclass 10, count 0 2006.257.14:06:45.48#ibcon#flushed, iclass 10, count 0 2006.257.14:06:45.48#ibcon#about to write, iclass 10, count 0 2006.257.14:06:45.48#ibcon#wrote, iclass 10, count 0 2006.257.14:06:45.48#ibcon#about to read 3, iclass 10, count 0 2006.257.14:06:45.50#ibcon#read 3, iclass 10, count 0 2006.257.14:06:45.50#ibcon#about to read 4, iclass 10, count 0 2006.257.14:06:45.50#ibcon#read 4, iclass 10, count 0 2006.257.14:06:45.50#ibcon#about to read 5, iclass 10, count 0 2006.257.14:06:45.50#ibcon#read 5, iclass 10, count 0 2006.257.14:06:45.50#ibcon#about to read 6, iclass 10, count 0 2006.257.14:06:45.50#ibcon#read 6, iclass 10, count 0 2006.257.14:06:45.50#ibcon#end of sib2, iclass 10, count 0 2006.257.14:06:45.50#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:06:45.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:06:45.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:06:45.50#ibcon#*before write, iclass 10, count 0 2006.257.14:06:45.50#ibcon#enter sib2, iclass 10, count 0 2006.257.14:06:45.50#ibcon#flushed, iclass 10, count 0 2006.257.14:06:45.50#ibcon#about to write, iclass 10, count 0 2006.257.14:06:45.50#ibcon#wrote, iclass 10, count 0 2006.257.14:06:45.50#ibcon#about to read 3, iclass 10, count 0 2006.257.14:06:45.54#ibcon#read 3, iclass 10, count 0 2006.257.14:06:45.54#ibcon#about to read 4, iclass 10, count 0 2006.257.14:06:45.54#ibcon#read 4, iclass 10, count 0 2006.257.14:06:45.54#ibcon#about to read 5, iclass 10, count 0 2006.257.14:06:45.54#ibcon#read 5, iclass 10, count 0 2006.257.14:06:45.54#ibcon#about to read 6, iclass 10, count 0 2006.257.14:06:45.54#ibcon#read 6, iclass 10, count 0 2006.257.14:06:45.54#ibcon#end of sib2, iclass 10, count 0 2006.257.14:06:45.54#ibcon#*after write, iclass 10, count 0 2006.257.14:06:45.54#ibcon#*before return 0, iclass 10, count 0 2006.257.14:06:45.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:45.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:06:45.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:06:45.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:06:45.54$vck44/vb=6,4 2006.257.14:06:45.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.14:06:45.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.14:06:45.54#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:45.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:45.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:45.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:45.60#ibcon#enter wrdev, iclass 12, count 2 2006.257.14:06:45.60#ibcon#first serial, iclass 12, count 2 2006.257.14:06:45.60#ibcon#enter sib2, iclass 12, count 2 2006.257.14:06:45.60#ibcon#flushed, iclass 12, count 2 2006.257.14:06:45.60#ibcon#about to write, iclass 12, count 2 2006.257.14:06:45.60#ibcon#wrote, iclass 12, count 2 2006.257.14:06:45.60#ibcon#about to read 3, iclass 12, count 2 2006.257.14:06:45.62#ibcon#read 3, iclass 12, count 2 2006.257.14:06:45.62#ibcon#about to read 4, iclass 12, count 2 2006.257.14:06:45.62#ibcon#read 4, iclass 12, count 2 2006.257.14:06:45.62#ibcon#about to read 5, iclass 12, count 2 2006.257.14:06:45.62#ibcon#read 5, iclass 12, count 2 2006.257.14:06:45.62#ibcon#about to read 6, iclass 12, count 2 2006.257.14:06:45.62#ibcon#read 6, iclass 12, count 2 2006.257.14:06:45.62#ibcon#end of sib2, iclass 12, count 2 2006.257.14:06:45.62#ibcon#*mode == 0, iclass 12, count 2 2006.257.14:06:45.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.14:06:45.62#ibcon#[27=AT06-04\r\n] 2006.257.14:06:45.62#ibcon#*before write, iclass 12, count 2 2006.257.14:06:45.62#ibcon#enter sib2, iclass 12, count 2 2006.257.14:06:45.62#ibcon#flushed, iclass 12, count 2 2006.257.14:06:45.62#ibcon#about to write, iclass 12, count 2 2006.257.14:06:45.62#ibcon#wrote, iclass 12, count 2 2006.257.14:06:45.62#ibcon#about to read 3, iclass 12, count 2 2006.257.14:06:45.65#ibcon#read 3, iclass 12, count 2 2006.257.14:06:45.65#ibcon#about to read 4, iclass 12, count 2 2006.257.14:06:45.65#ibcon#read 4, iclass 12, count 2 2006.257.14:06:45.65#ibcon#about to read 5, iclass 12, count 2 2006.257.14:06:45.65#ibcon#read 5, iclass 12, count 2 2006.257.14:06:45.65#ibcon#about to read 6, iclass 12, count 2 2006.257.14:06:45.65#ibcon#read 6, iclass 12, count 2 2006.257.14:06:45.65#ibcon#end of sib2, iclass 12, count 2 2006.257.14:06:45.65#ibcon#*after write, iclass 12, count 2 2006.257.14:06:45.65#ibcon#*before return 0, iclass 12, count 2 2006.257.14:06:45.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:45.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:06:45.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.14:06:45.65#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:45.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:45.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:45.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:45.77#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:06:45.77#ibcon#first serial, iclass 12, count 0 2006.257.14:06:45.77#ibcon#enter sib2, iclass 12, count 0 2006.257.14:06:45.77#ibcon#flushed, iclass 12, count 0 2006.257.14:06:45.77#ibcon#about to write, iclass 12, count 0 2006.257.14:06:45.77#ibcon#wrote, iclass 12, count 0 2006.257.14:06:45.77#ibcon#about to read 3, iclass 12, count 0 2006.257.14:06:45.79#ibcon#read 3, iclass 12, count 0 2006.257.14:06:45.79#ibcon#about to read 4, iclass 12, count 0 2006.257.14:06:45.79#ibcon#read 4, iclass 12, count 0 2006.257.14:06:45.79#ibcon#about to read 5, iclass 12, count 0 2006.257.14:06:45.79#ibcon#read 5, iclass 12, count 0 2006.257.14:06:45.79#ibcon#about to read 6, iclass 12, count 0 2006.257.14:06:45.79#ibcon#read 6, iclass 12, count 0 2006.257.14:06:45.79#ibcon#end of sib2, iclass 12, count 0 2006.257.14:06:45.79#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:06:45.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:06:45.79#ibcon#[27=USB\r\n] 2006.257.14:06:45.79#ibcon#*before write, iclass 12, count 0 2006.257.14:06:45.79#ibcon#enter sib2, iclass 12, count 0 2006.257.14:06:45.79#ibcon#flushed, iclass 12, count 0 2006.257.14:06:45.79#ibcon#about to write, iclass 12, count 0 2006.257.14:06:45.79#ibcon#wrote, iclass 12, count 0 2006.257.14:06:45.79#ibcon#about to read 3, iclass 12, count 0 2006.257.14:06:45.82#ibcon#read 3, iclass 12, count 0 2006.257.14:06:45.82#ibcon#about to read 4, iclass 12, count 0 2006.257.14:06:45.82#ibcon#read 4, iclass 12, count 0 2006.257.14:06:45.82#ibcon#about to read 5, iclass 12, count 0 2006.257.14:06:45.82#ibcon#read 5, iclass 12, count 0 2006.257.14:06:45.82#ibcon#about to read 6, iclass 12, count 0 2006.257.14:06:45.82#ibcon#read 6, iclass 12, count 0 2006.257.14:06:45.82#ibcon#end of sib2, iclass 12, count 0 2006.257.14:06:45.82#ibcon#*after write, iclass 12, count 0 2006.257.14:06:45.82#ibcon#*before return 0, iclass 12, count 0 2006.257.14:06:45.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:45.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:06:45.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:06:45.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:06:45.82$vck44/vblo=7,734.99 2006.257.14:06:45.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.14:06:45.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.14:06:45.82#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:45.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:45.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:45.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:45.82#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:06:45.82#ibcon#first serial, iclass 14, count 0 2006.257.14:06:45.82#ibcon#enter sib2, iclass 14, count 0 2006.257.14:06:45.82#ibcon#flushed, iclass 14, count 0 2006.257.14:06:45.82#ibcon#about to write, iclass 14, count 0 2006.257.14:06:45.82#ibcon#wrote, iclass 14, count 0 2006.257.14:06:45.82#ibcon#about to read 3, iclass 14, count 0 2006.257.14:06:45.84#ibcon#read 3, iclass 14, count 0 2006.257.14:06:45.84#ibcon#about to read 4, iclass 14, count 0 2006.257.14:06:45.84#ibcon#read 4, iclass 14, count 0 2006.257.14:06:45.84#ibcon#about to read 5, iclass 14, count 0 2006.257.14:06:45.84#ibcon#read 5, iclass 14, count 0 2006.257.14:06:45.84#ibcon#about to read 6, iclass 14, count 0 2006.257.14:06:45.84#ibcon#read 6, iclass 14, count 0 2006.257.14:06:45.84#ibcon#end of sib2, iclass 14, count 0 2006.257.14:06:45.84#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:06:45.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:06:45.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:06:45.84#ibcon#*before write, iclass 14, count 0 2006.257.14:06:45.84#ibcon#enter sib2, iclass 14, count 0 2006.257.14:06:45.84#ibcon#flushed, iclass 14, count 0 2006.257.14:06:45.84#ibcon#about to write, iclass 14, count 0 2006.257.14:06:45.84#ibcon#wrote, iclass 14, count 0 2006.257.14:06:45.84#ibcon#about to read 3, iclass 14, count 0 2006.257.14:06:45.88#ibcon#read 3, iclass 14, count 0 2006.257.14:06:45.88#ibcon#about to read 4, iclass 14, count 0 2006.257.14:06:45.88#ibcon#read 4, iclass 14, count 0 2006.257.14:06:45.88#ibcon#about to read 5, iclass 14, count 0 2006.257.14:06:45.88#ibcon#read 5, iclass 14, count 0 2006.257.14:06:45.88#ibcon#about to read 6, iclass 14, count 0 2006.257.14:06:45.88#ibcon#read 6, iclass 14, count 0 2006.257.14:06:45.88#ibcon#end of sib2, iclass 14, count 0 2006.257.14:06:45.88#ibcon#*after write, iclass 14, count 0 2006.257.14:06:45.88#ibcon#*before return 0, iclass 14, count 0 2006.257.14:06:45.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:45.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:06:45.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:06:45.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:06:45.88$vck44/vb=7,4 2006.257.14:06:45.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.14:06:45.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.14:06:45.88#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:45.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:45.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:45.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:45.94#ibcon#enter wrdev, iclass 16, count 2 2006.257.14:06:45.94#ibcon#first serial, iclass 16, count 2 2006.257.14:06:45.94#ibcon#enter sib2, iclass 16, count 2 2006.257.14:06:45.94#ibcon#flushed, iclass 16, count 2 2006.257.14:06:45.94#ibcon#about to write, iclass 16, count 2 2006.257.14:06:45.94#ibcon#wrote, iclass 16, count 2 2006.257.14:06:45.94#ibcon#about to read 3, iclass 16, count 2 2006.257.14:06:45.96#ibcon#read 3, iclass 16, count 2 2006.257.14:06:45.96#ibcon#about to read 4, iclass 16, count 2 2006.257.14:06:45.96#ibcon#read 4, iclass 16, count 2 2006.257.14:06:45.96#ibcon#about to read 5, iclass 16, count 2 2006.257.14:06:45.96#ibcon#read 5, iclass 16, count 2 2006.257.14:06:45.96#ibcon#about to read 6, iclass 16, count 2 2006.257.14:06:45.96#ibcon#read 6, iclass 16, count 2 2006.257.14:06:45.96#ibcon#end of sib2, iclass 16, count 2 2006.257.14:06:45.96#ibcon#*mode == 0, iclass 16, count 2 2006.257.14:06:45.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.14:06:45.96#ibcon#[27=AT07-04\r\n] 2006.257.14:06:45.96#ibcon#*before write, iclass 16, count 2 2006.257.14:06:45.96#ibcon#enter sib2, iclass 16, count 2 2006.257.14:06:45.96#ibcon#flushed, iclass 16, count 2 2006.257.14:06:45.96#ibcon#about to write, iclass 16, count 2 2006.257.14:06:45.96#ibcon#wrote, iclass 16, count 2 2006.257.14:06:45.96#ibcon#about to read 3, iclass 16, count 2 2006.257.14:06:45.99#ibcon#read 3, iclass 16, count 2 2006.257.14:06:45.99#ibcon#about to read 4, iclass 16, count 2 2006.257.14:06:45.99#ibcon#read 4, iclass 16, count 2 2006.257.14:06:46.74#ibcon#about to read 5, iclass 16, count 2 2006.257.14:06:46.74#ibcon#read 5, iclass 16, count 2 2006.257.14:06:46.74#ibcon#about to read 6, iclass 16, count 2 2006.257.14:06:46.74#ibcon#read 6, iclass 16, count 2 2006.257.14:06:46.74#ibcon#end of sib2, iclass 16, count 2 2006.257.14:06:46.74#ibcon#*after write, iclass 16, count 2 2006.257.14:06:46.74#ibcon#*before return 0, iclass 16, count 2 2006.257.14:06:46.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:46.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:06:46.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.14:06:46.74#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:46.16#abcon#<5=/14 1.5 3.3 17.53 971014.0\r\n> 2006.257.14:06:46.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:46.76#abcon#{5=INTERFACE CLEAR} 2006.257.14:06:46.82#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:06:46.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:46.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:46.86#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:06:46.86#ibcon#first serial, iclass 16, count 0 2006.257.14:06:46.86#ibcon#enter sib2, iclass 16, count 0 2006.257.14:06:46.86#ibcon#flushed, iclass 16, count 0 2006.257.14:06:46.86#ibcon#about to write, iclass 16, count 0 2006.257.14:06:46.86#ibcon#wrote, iclass 16, count 0 2006.257.14:06:46.86#ibcon#about to read 3, iclass 16, count 0 2006.257.14:06:46.88#ibcon#read 3, iclass 16, count 0 2006.257.14:06:46.88#ibcon#about to read 4, iclass 16, count 0 2006.257.14:06:46.88#ibcon#read 4, iclass 16, count 0 2006.257.14:06:46.88#ibcon#about to read 5, iclass 16, count 0 2006.257.14:06:46.88#ibcon#read 5, iclass 16, count 0 2006.257.14:06:46.88#ibcon#about to read 6, iclass 16, count 0 2006.257.14:06:46.88#ibcon#read 6, iclass 16, count 0 2006.257.14:06:46.88#ibcon#end of sib2, iclass 16, count 0 2006.257.14:06:46.88#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:06:46.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:06:46.88#ibcon#[27=USB\r\n] 2006.257.14:06:46.88#ibcon#*before write, iclass 16, count 0 2006.257.14:06:46.88#ibcon#enter sib2, iclass 16, count 0 2006.257.14:06:46.88#ibcon#flushed, iclass 16, count 0 2006.257.14:06:46.88#ibcon#about to write, iclass 16, count 0 2006.257.14:06:46.88#ibcon#wrote, iclass 16, count 0 2006.257.14:06:46.88#ibcon#about to read 3, iclass 16, count 0 2006.257.14:06:46.91#ibcon#read 3, iclass 16, count 0 2006.257.14:06:46.91#ibcon#about to read 4, iclass 16, count 0 2006.257.14:06:46.91#ibcon#read 4, iclass 16, count 0 2006.257.14:06:46.91#ibcon#about to read 5, iclass 16, count 0 2006.257.14:06:46.91#ibcon#read 5, iclass 16, count 0 2006.257.14:06:46.91#ibcon#about to read 6, iclass 16, count 0 2006.257.14:06:46.91#ibcon#read 6, iclass 16, count 0 2006.257.14:06:46.91#ibcon#end of sib2, iclass 16, count 0 2006.257.14:06:46.91#ibcon#*after write, iclass 16, count 0 2006.257.14:06:46.91#ibcon#*before return 0, iclass 16, count 0 2006.257.14:06:46.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:46.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:06:46.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:06:46.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:06:46.91$vck44/vblo=8,744.99 2006.257.14:06:46.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.14:06:46.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.14:06:46.91#ibcon#ireg 17 cls_cnt 0 2006.257.14:06:46.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:46.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:46.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:46.91#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:06:46.91#ibcon#first serial, iclass 22, count 0 2006.257.14:06:46.91#ibcon#enter sib2, iclass 22, count 0 2006.257.14:06:46.91#ibcon#flushed, iclass 22, count 0 2006.257.14:06:46.91#ibcon#about to write, iclass 22, count 0 2006.257.14:06:46.91#ibcon#wrote, iclass 22, count 0 2006.257.14:06:46.91#ibcon#about to read 3, iclass 22, count 0 2006.257.14:06:46.93#ibcon#read 3, iclass 22, count 0 2006.257.14:06:46.93#ibcon#about to read 4, iclass 22, count 0 2006.257.14:06:46.93#ibcon#read 4, iclass 22, count 0 2006.257.14:06:46.93#ibcon#about to read 5, iclass 22, count 0 2006.257.14:06:46.93#ibcon#read 5, iclass 22, count 0 2006.257.14:06:46.93#ibcon#about to read 6, iclass 22, count 0 2006.257.14:06:46.93#ibcon#read 6, iclass 22, count 0 2006.257.14:06:46.93#ibcon#end of sib2, iclass 22, count 0 2006.257.14:06:46.93#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:06:46.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:06:46.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:06:46.93#ibcon#*before write, iclass 22, count 0 2006.257.14:06:46.93#ibcon#enter sib2, iclass 22, count 0 2006.257.14:06:46.93#ibcon#flushed, iclass 22, count 0 2006.257.14:06:46.93#ibcon#about to write, iclass 22, count 0 2006.257.14:06:46.93#ibcon#wrote, iclass 22, count 0 2006.257.14:06:46.93#ibcon#about to read 3, iclass 22, count 0 2006.257.14:06:46.97#ibcon#read 3, iclass 22, count 0 2006.257.14:06:46.97#ibcon#about to read 4, iclass 22, count 0 2006.257.14:06:46.97#ibcon#read 4, iclass 22, count 0 2006.257.14:06:46.97#ibcon#about to read 5, iclass 22, count 0 2006.257.14:06:46.97#ibcon#read 5, iclass 22, count 0 2006.257.14:06:46.97#ibcon#about to read 6, iclass 22, count 0 2006.257.14:06:46.97#ibcon#read 6, iclass 22, count 0 2006.257.14:06:46.97#ibcon#end of sib2, iclass 22, count 0 2006.257.14:06:46.97#ibcon#*after write, iclass 22, count 0 2006.257.14:06:46.97#ibcon#*before return 0, iclass 22, count 0 2006.257.14:06:46.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:46.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:06:46.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:06:46.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:06:46.97$vck44/vb=8,4 2006.257.14:06:46.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.14:06:46.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.14:06:46.97#ibcon#ireg 11 cls_cnt 2 2006.257.14:06:46.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:47.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:47.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:47.03#ibcon#enter wrdev, iclass 24, count 2 2006.257.14:06:47.03#ibcon#first serial, iclass 24, count 2 2006.257.14:06:47.03#ibcon#enter sib2, iclass 24, count 2 2006.257.14:06:47.03#ibcon#flushed, iclass 24, count 2 2006.257.14:06:47.03#ibcon#about to write, iclass 24, count 2 2006.257.14:06:47.03#ibcon#wrote, iclass 24, count 2 2006.257.14:06:47.03#ibcon#about to read 3, iclass 24, count 2 2006.257.14:06:47.05#ibcon#read 3, iclass 24, count 2 2006.257.14:06:47.05#ibcon#about to read 4, iclass 24, count 2 2006.257.14:06:47.05#ibcon#read 4, iclass 24, count 2 2006.257.14:06:47.05#ibcon#about to read 5, iclass 24, count 2 2006.257.14:06:47.05#ibcon#read 5, iclass 24, count 2 2006.257.14:06:47.05#ibcon#about to read 6, iclass 24, count 2 2006.257.14:06:47.05#ibcon#read 6, iclass 24, count 2 2006.257.14:06:47.05#ibcon#end of sib2, iclass 24, count 2 2006.257.14:06:47.05#ibcon#*mode == 0, iclass 24, count 2 2006.257.14:06:47.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.14:06:47.05#ibcon#[27=AT08-04\r\n] 2006.257.14:06:47.05#ibcon#*before write, iclass 24, count 2 2006.257.14:06:47.05#ibcon#enter sib2, iclass 24, count 2 2006.257.14:06:47.05#ibcon#flushed, iclass 24, count 2 2006.257.14:06:47.05#ibcon#about to write, iclass 24, count 2 2006.257.14:06:47.05#ibcon#wrote, iclass 24, count 2 2006.257.14:06:47.05#ibcon#about to read 3, iclass 24, count 2 2006.257.14:06:47.08#ibcon#read 3, iclass 24, count 2 2006.257.14:06:47.08#ibcon#about to read 4, iclass 24, count 2 2006.257.14:06:47.08#ibcon#read 4, iclass 24, count 2 2006.257.14:06:47.08#ibcon#about to read 5, iclass 24, count 2 2006.257.14:06:47.08#ibcon#read 5, iclass 24, count 2 2006.257.14:06:47.08#ibcon#about to read 6, iclass 24, count 2 2006.257.14:06:47.08#ibcon#read 6, iclass 24, count 2 2006.257.14:06:47.08#ibcon#end of sib2, iclass 24, count 2 2006.257.14:06:47.08#ibcon#*after write, iclass 24, count 2 2006.257.14:06:47.08#ibcon#*before return 0, iclass 24, count 2 2006.257.14:06:47.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:47.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:06:47.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.14:06:47.08#ibcon#ireg 7 cls_cnt 0 2006.257.14:06:47.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:47.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:47.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:47.20#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:06:47.20#ibcon#first serial, iclass 24, count 0 2006.257.14:06:47.20#ibcon#enter sib2, iclass 24, count 0 2006.257.14:06:47.20#ibcon#flushed, iclass 24, count 0 2006.257.14:06:47.20#ibcon#about to write, iclass 24, count 0 2006.257.14:06:47.20#ibcon#wrote, iclass 24, count 0 2006.257.14:06:47.20#ibcon#about to read 3, iclass 24, count 0 2006.257.14:06:47.22#ibcon#read 3, iclass 24, count 0 2006.257.14:06:47.22#ibcon#about to read 4, iclass 24, count 0 2006.257.14:06:47.22#ibcon#read 4, iclass 24, count 0 2006.257.14:06:47.22#ibcon#about to read 5, iclass 24, count 0 2006.257.14:06:47.22#ibcon#read 5, iclass 24, count 0 2006.257.14:06:47.22#ibcon#about to read 6, iclass 24, count 0 2006.257.14:06:47.22#ibcon#read 6, iclass 24, count 0 2006.257.14:06:47.22#ibcon#end of sib2, iclass 24, count 0 2006.257.14:06:47.22#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:06:47.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:06:47.22#ibcon#[27=USB\r\n] 2006.257.14:06:47.22#ibcon#*before write, iclass 24, count 0 2006.257.14:06:47.22#ibcon#enter sib2, iclass 24, count 0 2006.257.14:06:47.22#ibcon#flushed, iclass 24, count 0 2006.257.14:06:47.22#ibcon#about to write, iclass 24, count 0 2006.257.14:06:47.22#ibcon#wrote, iclass 24, count 0 2006.257.14:06:47.22#ibcon#about to read 3, iclass 24, count 0 2006.257.14:06:47.25#ibcon#read 3, iclass 24, count 0 2006.257.14:06:47.25#ibcon#about to read 4, iclass 24, count 0 2006.257.14:06:47.25#ibcon#read 4, iclass 24, count 0 2006.257.14:06:47.25#ibcon#about to read 5, iclass 24, count 0 2006.257.14:06:47.25#ibcon#read 5, iclass 24, count 0 2006.257.14:06:47.25#ibcon#about to read 6, iclass 24, count 0 2006.257.14:06:47.25#ibcon#read 6, iclass 24, count 0 2006.257.14:06:47.25#ibcon#end of sib2, iclass 24, count 0 2006.257.14:06:47.25#ibcon#*after write, iclass 24, count 0 2006.257.14:06:47.25#ibcon#*before return 0, iclass 24, count 0 2006.257.14:06:47.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:47.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:06:47.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:06:47.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:06:47.25$vck44/vabw=wide 2006.257.14:06:47.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.14:06:47.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.14:06:47.25#ibcon#ireg 8 cls_cnt 0 2006.257.14:06:47.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:47.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:47.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:47.25#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:06:47.25#ibcon#first serial, iclass 26, count 0 2006.257.14:06:47.25#ibcon#enter sib2, iclass 26, count 0 2006.257.14:06:47.25#ibcon#flushed, iclass 26, count 0 2006.257.14:06:47.25#ibcon#about to write, iclass 26, count 0 2006.257.14:06:47.25#ibcon#wrote, iclass 26, count 0 2006.257.14:06:47.25#ibcon#about to read 3, iclass 26, count 0 2006.257.14:06:47.27#ibcon#read 3, iclass 26, count 0 2006.257.14:06:47.27#ibcon#about to read 4, iclass 26, count 0 2006.257.14:06:47.27#ibcon#read 4, iclass 26, count 0 2006.257.14:06:47.27#ibcon#about to read 5, iclass 26, count 0 2006.257.14:06:47.27#ibcon#read 5, iclass 26, count 0 2006.257.14:06:47.27#ibcon#about to read 6, iclass 26, count 0 2006.257.14:06:47.27#ibcon#read 6, iclass 26, count 0 2006.257.14:06:47.27#ibcon#end of sib2, iclass 26, count 0 2006.257.14:06:47.27#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:06:47.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:06:47.27#ibcon#[25=BW32\r\n] 2006.257.14:06:47.27#ibcon#*before write, iclass 26, count 0 2006.257.14:06:47.27#ibcon#enter sib2, iclass 26, count 0 2006.257.14:06:47.27#ibcon#flushed, iclass 26, count 0 2006.257.14:06:47.27#ibcon#about to write, iclass 26, count 0 2006.257.14:06:47.27#ibcon#wrote, iclass 26, count 0 2006.257.14:06:47.27#ibcon#about to read 3, iclass 26, count 0 2006.257.14:06:47.30#ibcon#read 3, iclass 26, count 0 2006.257.14:06:47.30#ibcon#about to read 4, iclass 26, count 0 2006.257.14:06:47.30#ibcon#read 4, iclass 26, count 0 2006.257.14:06:47.30#ibcon#about to read 5, iclass 26, count 0 2006.257.14:06:47.30#ibcon#read 5, iclass 26, count 0 2006.257.14:06:47.30#ibcon#about to read 6, iclass 26, count 0 2006.257.14:06:47.30#ibcon#read 6, iclass 26, count 0 2006.257.14:06:47.30#ibcon#end of sib2, iclass 26, count 0 2006.257.14:06:47.30#ibcon#*after write, iclass 26, count 0 2006.257.14:06:47.30#ibcon#*before return 0, iclass 26, count 0 2006.257.14:06:47.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:47.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:06:47.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:06:47.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:06:47.30$vck44/vbbw=wide 2006.257.14:06:47.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.14:06:47.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.14:06:47.30#ibcon#ireg 8 cls_cnt 0 2006.257.14:06:47.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:06:47.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:06:47.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:06:47.37#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:06:47.37#ibcon#first serial, iclass 28, count 0 2006.257.14:06:47.37#ibcon#enter sib2, iclass 28, count 0 2006.257.14:06:47.37#ibcon#flushed, iclass 28, count 0 2006.257.14:06:47.37#ibcon#about to write, iclass 28, count 0 2006.257.14:06:47.37#ibcon#wrote, iclass 28, count 0 2006.257.14:06:47.37#ibcon#about to read 3, iclass 28, count 0 2006.257.14:06:47.39#ibcon#read 3, iclass 28, count 0 2006.257.14:06:47.39#ibcon#about to read 4, iclass 28, count 0 2006.257.14:06:47.39#ibcon#read 4, iclass 28, count 0 2006.257.14:06:47.39#ibcon#about to read 5, iclass 28, count 0 2006.257.14:06:47.39#ibcon#read 5, iclass 28, count 0 2006.257.14:06:47.39#ibcon#about to read 6, iclass 28, count 0 2006.257.14:06:47.39#ibcon#read 6, iclass 28, count 0 2006.257.14:06:47.39#ibcon#end of sib2, iclass 28, count 0 2006.257.14:06:47.39#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:06:47.39#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:06:47.39#ibcon#[27=BW32\r\n] 2006.257.14:06:47.39#ibcon#*before write, iclass 28, count 0 2006.257.14:06:47.39#ibcon#enter sib2, iclass 28, count 0 2006.257.14:06:47.39#ibcon#flushed, iclass 28, count 0 2006.257.14:06:47.39#ibcon#about to write, iclass 28, count 0 2006.257.14:06:47.39#ibcon#wrote, iclass 28, count 0 2006.257.14:06:47.39#ibcon#about to read 3, iclass 28, count 0 2006.257.14:06:47.42#ibcon#read 3, iclass 28, count 0 2006.257.14:06:47.42#ibcon#about to read 4, iclass 28, count 0 2006.257.14:06:47.42#ibcon#read 4, iclass 28, count 0 2006.257.14:06:47.42#ibcon#about to read 5, iclass 28, count 0 2006.257.14:06:47.42#ibcon#read 5, iclass 28, count 0 2006.257.14:06:47.42#ibcon#about to read 6, iclass 28, count 0 2006.257.14:06:47.42#ibcon#read 6, iclass 28, count 0 2006.257.14:06:47.42#ibcon#end of sib2, iclass 28, count 0 2006.257.14:06:47.42#ibcon#*after write, iclass 28, count 0 2006.257.14:06:47.42#ibcon#*before return 0, iclass 28, count 0 2006.257.14:06:47.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:06:47.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:06:47.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:06:47.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:06:47.42$setupk4/ifdk4 2006.257.14:06:47.42$ifdk4/lo= 2006.257.14:06:47.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:06:47.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:06:47.42$ifdk4/patch= 2006.257.14:06:47.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:06:47.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:06:47.42$setupk4/!*+20s 2006.257.14:06:56.91#abcon#<5=/14 1.6 3.3 17.53 971014.0\r\n> 2006.257.14:06:56.93#abcon#{5=INTERFACE CLEAR} 2006.257.14:06:56.99#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:06:59.05$setupk4/"tpicd 2006.257.14:06:59.05$setupk4/echo=off 2006.257.14:06:59.05$setupk4/xlog=off 2006.257.14:06:59.05:!2006.257.14:09:44 2006.257.14:07:41.14#trakl#Source acquired 2006.257.14:07:41.14#flagr#flagr/antenna,acquired 2006.257.14:09:44.00:preob 2006.257.14:09:45.14/onsource/TRACKING 2006.257.14:09:45.14:!2006.257.14:09:54 2006.257.14:09:54.00:"tape 2006.257.14:09:54.00:"st=record 2006.257.14:09:54.00:data_valid=on 2006.257.14:09:54.00:midob 2006.257.14:09:54.14/onsource/TRACKING 2006.257.14:09:54.14/wx/17.50,1014.0,97 2006.257.14:09:54.31/cable/+6.4818E-03 2006.257.14:09:55.40/va/01,08,usb,yes,30,33 2006.257.14:09:55.40/va/02,07,usb,yes,33,33 2006.257.14:09:55.40/va/03,08,usb,yes,29,31 2006.257.14:09:55.40/va/04,07,usb,yes,34,35 2006.257.14:09:55.40/va/05,04,usb,yes,30,31 2006.257.14:09:55.40/va/06,04,usb,yes,34,34 2006.257.14:09:55.40/va/07,04,usb,yes,35,35 2006.257.14:09:55.40/va/08,04,usb,yes,29,35 2006.257.14:09:55.63/valo/01,524.99,yes,locked 2006.257.14:09:55.63/valo/02,534.99,yes,locked 2006.257.14:09:55.63/valo/03,564.99,yes,locked 2006.257.14:09:55.63/valo/04,624.99,yes,locked 2006.257.14:09:55.63/valo/05,734.99,yes,locked 2006.257.14:09:55.63/valo/06,814.99,yes,locked 2006.257.14:09:55.63/valo/07,864.99,yes,locked 2006.257.14:09:55.63/valo/08,884.99,yes,locked 2006.257.14:09:56.72/vb/01,04,usb,yes,30,28 2006.257.14:09:56.72/vb/02,05,usb,yes,28,28 2006.257.14:09:56.72/vb/03,04,usb,yes,29,32 2006.257.14:09:56.72/vb/04,05,usb,yes,30,29 2006.257.14:09:56.72/vb/05,04,usb,yes,26,29 2006.257.14:09:56.72/vb/06,04,usb,yes,31,27 2006.257.14:09:56.72/vb/07,04,usb,yes,30,30 2006.257.14:09:56.72/vb/08,04,usb,yes,28,31 2006.257.14:09:56.96/vblo/01,629.99,yes,locked 2006.257.14:09:56.96/vblo/02,634.99,yes,locked 2006.257.14:09:56.96/vblo/03,649.99,yes,locked 2006.257.14:09:56.96/vblo/04,679.99,yes,locked 2006.257.14:09:56.96/vblo/05,709.99,yes,locked 2006.257.14:09:56.96/vblo/06,719.99,yes,locked 2006.257.14:09:56.96/vblo/07,734.99,yes,locked 2006.257.14:09:56.96/vblo/08,744.99,yes,locked 2006.257.14:09:57.11/vabw/8 2006.257.14:09:57.26/vbbw/8 2006.257.14:09:57.35/xfe/off,on,15.5 2006.257.14:09:57.72/ifatt/23,28,28,28 2006.257.14:09:58.07/fmout-gps/S +4.53E-07 2006.257.14:09:58.11:!2006.257.14:11:14 2006.257.14:11:14.01:data_valid=off 2006.257.14:11:14.01:"et 2006.257.14:11:14.02:!+3s 2006.257.14:11:17.03:"tape 2006.257.14:11:17.03:postob 2006.257.14:11:17.16/cable/+6.4818E-03 2006.257.14:11:17.16/wx/17.49,1013.9,97 2006.257.14:11:17.22/fmout-gps/S +4.53E-07 2006.257.14:11:17.22:scan_name=257-1412,jd0609,40 2006.257.14:11:17.23:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.257.14:11:18.14#flagr#flagr/antenna,new-source 2006.257.14:11:18.14:checkk5 2006.257.14:11:18.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:11:18.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:11:19.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:11:19.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:11:20.13/chk_obsdata//k5ts1/T2571409??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:11:20.51/chk_obsdata//k5ts2/T2571409??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:11:20.89/chk_obsdata//k5ts3/T2571409??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:11:21.29/chk_obsdata//k5ts4/T2571409??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:11:22.00/k5log//k5ts1_log_newline 2006.257.14:11:22.70/k5log//k5ts2_log_newline 2006.257.14:11:23.41/k5log//k5ts3_log_newline 2006.257.14:11:24.10/k5log//k5ts4_log_newline 2006.257.14:11:24.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:11:24.12:setupk4=1 2006.257.14:11:24.12$setupk4/echo=on 2006.257.14:11:24.12$setupk4/pcalon 2006.257.14:11:24.12$pcalon/"no phase cal control is implemented here 2006.257.14:11:24.12$setupk4/"tpicd=stop 2006.257.14:11:24.12$setupk4/"rec=synch_on 2006.257.14:11:24.12$setupk4/"rec_mode=128 2006.257.14:11:24.12$setupk4/!* 2006.257.14:11:24.12$setupk4/recpk4 2006.257.14:11:24.12$recpk4/recpatch= 2006.257.14:11:24.13$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:11:24.13$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:11:24.13$setupk4/vck44 2006.257.14:11:24.13$vck44/valo=1,524.99 2006.257.14:11:24.13#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.14:11:24.13#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.14:11:24.13#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:24.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:24.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:24.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:24.13#ibcon#enter wrdev, iclass 33, count 0 2006.257.14:11:24.13#ibcon#first serial, iclass 33, count 0 2006.257.14:11:24.13#ibcon#enter sib2, iclass 33, count 0 2006.257.14:11:24.13#ibcon#flushed, iclass 33, count 0 2006.257.14:11:24.13#ibcon#about to write, iclass 33, count 0 2006.257.14:11:24.13#ibcon#wrote, iclass 33, count 0 2006.257.14:11:24.13#ibcon#about to read 3, iclass 33, count 0 2006.257.14:11:24.14#ibcon#read 3, iclass 33, count 0 2006.257.14:11:24.14#ibcon#about to read 4, iclass 33, count 0 2006.257.14:11:24.14#ibcon#read 4, iclass 33, count 0 2006.257.14:11:24.14#ibcon#about to read 5, iclass 33, count 0 2006.257.14:11:24.14#ibcon#read 5, iclass 33, count 0 2006.257.14:11:24.14#ibcon#about to read 6, iclass 33, count 0 2006.257.14:11:24.14#ibcon#read 6, iclass 33, count 0 2006.257.14:11:24.14#ibcon#end of sib2, iclass 33, count 0 2006.257.14:11:24.14#ibcon#*mode == 0, iclass 33, count 0 2006.257.14:11:24.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.14:11:24.14#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:11:24.14#ibcon#*before write, iclass 33, count 0 2006.257.14:11:24.14#ibcon#enter sib2, iclass 33, count 0 2006.257.14:11:24.14#ibcon#flushed, iclass 33, count 0 2006.257.14:11:24.14#ibcon#about to write, iclass 33, count 0 2006.257.14:11:24.14#ibcon#wrote, iclass 33, count 0 2006.257.14:11:24.14#ibcon#about to read 3, iclass 33, count 0 2006.257.14:11:24.19#ibcon#read 3, iclass 33, count 0 2006.257.14:11:24.19#ibcon#about to read 4, iclass 33, count 0 2006.257.14:11:24.19#ibcon#read 4, iclass 33, count 0 2006.257.14:11:24.19#ibcon#about to read 5, iclass 33, count 0 2006.257.14:11:24.19#ibcon#read 5, iclass 33, count 0 2006.257.14:11:24.19#ibcon#about to read 6, iclass 33, count 0 2006.257.14:11:24.19#ibcon#read 6, iclass 33, count 0 2006.257.14:11:24.19#ibcon#end of sib2, iclass 33, count 0 2006.257.14:11:24.19#ibcon#*after write, iclass 33, count 0 2006.257.14:11:24.19#ibcon#*before return 0, iclass 33, count 0 2006.257.14:11:24.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:24.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:24.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.14:11:24.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.14:11:24.19$vck44/va=1,8 2006.257.14:11:24.19#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.14:11:24.19#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.14:11:24.19#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:24.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:24.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:24.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:24.19#ibcon#enter wrdev, iclass 35, count 2 2006.257.14:11:24.19#ibcon#first serial, iclass 35, count 2 2006.257.14:11:24.19#ibcon#enter sib2, iclass 35, count 2 2006.257.14:11:24.19#ibcon#flushed, iclass 35, count 2 2006.257.14:11:24.19#ibcon#about to write, iclass 35, count 2 2006.257.14:11:24.19#ibcon#wrote, iclass 35, count 2 2006.257.14:11:24.19#ibcon#about to read 3, iclass 35, count 2 2006.257.14:11:24.21#ibcon#read 3, iclass 35, count 2 2006.257.14:11:24.21#ibcon#about to read 4, iclass 35, count 2 2006.257.14:11:24.21#ibcon#read 4, iclass 35, count 2 2006.257.14:11:24.21#ibcon#about to read 5, iclass 35, count 2 2006.257.14:11:24.21#ibcon#read 5, iclass 35, count 2 2006.257.14:11:24.21#ibcon#about to read 6, iclass 35, count 2 2006.257.14:11:24.21#ibcon#read 6, iclass 35, count 2 2006.257.14:11:24.21#ibcon#end of sib2, iclass 35, count 2 2006.257.14:11:24.21#ibcon#*mode == 0, iclass 35, count 2 2006.257.14:11:24.21#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.14:11:24.21#ibcon#[25=AT01-08\r\n] 2006.257.14:11:24.21#ibcon#*before write, iclass 35, count 2 2006.257.14:11:24.21#ibcon#enter sib2, iclass 35, count 2 2006.257.14:11:24.21#ibcon#flushed, iclass 35, count 2 2006.257.14:11:24.21#ibcon#about to write, iclass 35, count 2 2006.257.14:11:24.21#ibcon#wrote, iclass 35, count 2 2006.257.14:11:24.21#ibcon#about to read 3, iclass 35, count 2 2006.257.14:11:24.24#ibcon#read 3, iclass 35, count 2 2006.257.14:11:24.24#ibcon#about to read 4, iclass 35, count 2 2006.257.14:11:24.24#ibcon#read 4, iclass 35, count 2 2006.257.14:11:24.24#ibcon#about to read 5, iclass 35, count 2 2006.257.14:11:24.24#ibcon#read 5, iclass 35, count 2 2006.257.14:11:24.24#ibcon#about to read 6, iclass 35, count 2 2006.257.14:11:24.24#ibcon#read 6, iclass 35, count 2 2006.257.14:11:24.24#ibcon#end of sib2, iclass 35, count 2 2006.257.14:11:24.24#ibcon#*after write, iclass 35, count 2 2006.257.14:11:24.24#ibcon#*before return 0, iclass 35, count 2 2006.257.14:11:24.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:24.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:24.24#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.14:11:24.24#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:24.24#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:24.36#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:24.36#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:24.36#ibcon#enter wrdev, iclass 35, count 0 2006.257.14:11:24.36#ibcon#first serial, iclass 35, count 0 2006.257.14:11:24.36#ibcon#enter sib2, iclass 35, count 0 2006.257.14:11:24.36#ibcon#flushed, iclass 35, count 0 2006.257.14:11:24.36#ibcon#about to write, iclass 35, count 0 2006.257.14:11:24.36#ibcon#wrote, iclass 35, count 0 2006.257.14:11:24.36#ibcon#about to read 3, iclass 35, count 0 2006.257.14:11:24.38#ibcon#read 3, iclass 35, count 0 2006.257.14:11:24.38#ibcon#about to read 4, iclass 35, count 0 2006.257.14:11:24.38#ibcon#read 4, iclass 35, count 0 2006.257.14:11:24.38#ibcon#about to read 5, iclass 35, count 0 2006.257.14:11:24.38#ibcon#read 5, iclass 35, count 0 2006.257.14:11:24.38#ibcon#about to read 6, iclass 35, count 0 2006.257.14:11:24.38#ibcon#read 6, iclass 35, count 0 2006.257.14:11:24.38#ibcon#end of sib2, iclass 35, count 0 2006.257.14:11:24.38#ibcon#*mode == 0, iclass 35, count 0 2006.257.14:11:24.38#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.14:11:24.38#ibcon#[25=USB\r\n] 2006.257.14:11:24.38#ibcon#*before write, iclass 35, count 0 2006.257.14:11:24.38#ibcon#enter sib2, iclass 35, count 0 2006.257.14:11:24.38#ibcon#flushed, iclass 35, count 0 2006.257.14:11:24.38#ibcon#about to write, iclass 35, count 0 2006.257.14:11:24.38#ibcon#wrote, iclass 35, count 0 2006.257.14:11:24.38#ibcon#about to read 3, iclass 35, count 0 2006.257.14:11:24.41#ibcon#read 3, iclass 35, count 0 2006.257.14:11:24.41#ibcon#about to read 4, iclass 35, count 0 2006.257.14:11:24.41#ibcon#read 4, iclass 35, count 0 2006.257.14:11:24.41#ibcon#about to read 5, iclass 35, count 0 2006.257.14:11:24.41#ibcon#read 5, iclass 35, count 0 2006.257.14:11:24.41#ibcon#about to read 6, iclass 35, count 0 2006.257.14:11:24.41#ibcon#read 6, iclass 35, count 0 2006.257.14:11:24.41#ibcon#end of sib2, iclass 35, count 0 2006.257.14:11:24.41#ibcon#*after write, iclass 35, count 0 2006.257.14:11:24.41#ibcon#*before return 0, iclass 35, count 0 2006.257.14:11:24.41#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:24.41#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:24.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.14:11:24.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.14:11:24.41$vck44/valo=2,534.99 2006.257.14:11:24.41#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.14:11:24.41#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.14:11:24.41#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:24.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:24.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:24.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:24.41#ibcon#enter wrdev, iclass 37, count 0 2006.257.14:11:24.41#ibcon#first serial, iclass 37, count 0 2006.257.14:11:24.41#ibcon#enter sib2, iclass 37, count 0 2006.257.14:11:24.41#ibcon#flushed, iclass 37, count 0 2006.257.14:11:24.41#ibcon#about to write, iclass 37, count 0 2006.257.14:11:24.41#ibcon#wrote, iclass 37, count 0 2006.257.14:11:24.41#ibcon#about to read 3, iclass 37, count 0 2006.257.14:11:24.43#ibcon#read 3, iclass 37, count 0 2006.257.14:11:24.43#ibcon#about to read 4, iclass 37, count 0 2006.257.14:11:24.43#ibcon#read 4, iclass 37, count 0 2006.257.14:11:24.43#ibcon#about to read 5, iclass 37, count 0 2006.257.14:11:24.43#ibcon#read 5, iclass 37, count 0 2006.257.14:11:24.43#ibcon#about to read 6, iclass 37, count 0 2006.257.14:11:24.43#ibcon#read 6, iclass 37, count 0 2006.257.14:11:24.43#ibcon#end of sib2, iclass 37, count 0 2006.257.14:11:24.43#ibcon#*mode == 0, iclass 37, count 0 2006.257.14:11:24.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.14:11:24.43#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:11:24.43#ibcon#*before write, iclass 37, count 0 2006.257.14:11:24.43#ibcon#enter sib2, iclass 37, count 0 2006.257.14:11:24.43#ibcon#flushed, iclass 37, count 0 2006.257.14:11:24.43#ibcon#about to write, iclass 37, count 0 2006.257.14:11:24.43#ibcon#wrote, iclass 37, count 0 2006.257.14:11:24.43#ibcon#about to read 3, iclass 37, count 0 2006.257.14:11:24.47#ibcon#read 3, iclass 37, count 0 2006.257.14:11:24.47#ibcon#about to read 4, iclass 37, count 0 2006.257.14:11:24.47#ibcon#read 4, iclass 37, count 0 2006.257.14:11:24.47#ibcon#about to read 5, iclass 37, count 0 2006.257.14:11:24.47#ibcon#read 5, iclass 37, count 0 2006.257.14:11:24.47#ibcon#about to read 6, iclass 37, count 0 2006.257.14:11:24.47#ibcon#read 6, iclass 37, count 0 2006.257.14:11:24.47#ibcon#end of sib2, iclass 37, count 0 2006.257.14:11:24.47#ibcon#*after write, iclass 37, count 0 2006.257.14:11:24.47#ibcon#*before return 0, iclass 37, count 0 2006.257.14:11:24.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:24.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:24.47#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.14:11:24.47#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.14:11:24.47$vck44/va=2,7 2006.257.14:11:24.47#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.14:11:24.47#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.14:11:24.47#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:24.47#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:24.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:24.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:24.53#ibcon#enter wrdev, iclass 39, count 2 2006.257.14:11:24.53#ibcon#first serial, iclass 39, count 2 2006.257.14:11:24.53#ibcon#enter sib2, iclass 39, count 2 2006.257.14:11:24.53#ibcon#flushed, iclass 39, count 2 2006.257.14:11:24.53#ibcon#about to write, iclass 39, count 2 2006.257.14:11:24.53#ibcon#wrote, iclass 39, count 2 2006.257.14:11:24.53#ibcon#about to read 3, iclass 39, count 2 2006.257.14:11:24.55#ibcon#read 3, iclass 39, count 2 2006.257.14:11:24.55#ibcon#about to read 4, iclass 39, count 2 2006.257.14:11:24.55#ibcon#read 4, iclass 39, count 2 2006.257.14:11:24.55#ibcon#about to read 5, iclass 39, count 2 2006.257.14:11:24.55#ibcon#read 5, iclass 39, count 2 2006.257.14:11:24.55#ibcon#about to read 6, iclass 39, count 2 2006.257.14:11:24.55#ibcon#read 6, iclass 39, count 2 2006.257.14:11:24.55#ibcon#end of sib2, iclass 39, count 2 2006.257.14:11:24.55#ibcon#*mode == 0, iclass 39, count 2 2006.257.14:11:24.55#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.14:11:24.55#ibcon#[25=AT02-07\r\n] 2006.257.14:11:24.55#ibcon#*before write, iclass 39, count 2 2006.257.14:11:24.55#ibcon#enter sib2, iclass 39, count 2 2006.257.14:11:24.55#ibcon#flushed, iclass 39, count 2 2006.257.14:11:24.55#ibcon#about to write, iclass 39, count 2 2006.257.14:11:24.55#ibcon#wrote, iclass 39, count 2 2006.257.14:11:24.55#ibcon#about to read 3, iclass 39, count 2 2006.257.14:11:24.58#ibcon#read 3, iclass 39, count 2 2006.257.14:11:24.58#ibcon#about to read 4, iclass 39, count 2 2006.257.14:11:24.58#ibcon#read 4, iclass 39, count 2 2006.257.14:11:24.58#ibcon#about to read 5, iclass 39, count 2 2006.257.14:11:24.58#ibcon#read 5, iclass 39, count 2 2006.257.14:11:24.58#ibcon#about to read 6, iclass 39, count 2 2006.257.14:11:24.58#ibcon#read 6, iclass 39, count 2 2006.257.14:11:24.58#ibcon#end of sib2, iclass 39, count 2 2006.257.14:11:24.58#ibcon#*after write, iclass 39, count 2 2006.257.14:11:24.58#ibcon#*before return 0, iclass 39, count 2 2006.257.14:11:24.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:24.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:24.58#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.14:11:24.58#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:24.58#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:24.70#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:24.70#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:24.70#ibcon#enter wrdev, iclass 39, count 0 2006.257.14:11:24.70#ibcon#first serial, iclass 39, count 0 2006.257.14:11:24.70#ibcon#enter sib2, iclass 39, count 0 2006.257.14:11:24.70#ibcon#flushed, iclass 39, count 0 2006.257.14:11:24.70#ibcon#about to write, iclass 39, count 0 2006.257.14:11:24.70#ibcon#wrote, iclass 39, count 0 2006.257.14:11:24.70#ibcon#about to read 3, iclass 39, count 0 2006.257.14:11:24.72#ibcon#read 3, iclass 39, count 0 2006.257.14:11:24.72#ibcon#about to read 4, iclass 39, count 0 2006.257.14:11:24.72#ibcon#read 4, iclass 39, count 0 2006.257.14:11:24.72#ibcon#about to read 5, iclass 39, count 0 2006.257.14:11:24.72#ibcon#read 5, iclass 39, count 0 2006.257.14:11:24.72#ibcon#about to read 6, iclass 39, count 0 2006.257.14:11:24.72#ibcon#read 6, iclass 39, count 0 2006.257.14:11:24.72#ibcon#end of sib2, iclass 39, count 0 2006.257.14:11:24.72#ibcon#*mode == 0, iclass 39, count 0 2006.257.14:11:24.72#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.14:11:24.72#ibcon#[25=USB\r\n] 2006.257.14:11:24.72#ibcon#*before write, iclass 39, count 0 2006.257.14:11:24.72#ibcon#enter sib2, iclass 39, count 0 2006.257.14:11:24.72#ibcon#flushed, iclass 39, count 0 2006.257.14:11:24.72#ibcon#about to write, iclass 39, count 0 2006.257.14:11:24.72#ibcon#wrote, iclass 39, count 0 2006.257.14:11:24.72#ibcon#about to read 3, iclass 39, count 0 2006.257.14:11:24.75#ibcon#read 3, iclass 39, count 0 2006.257.14:11:24.75#ibcon#about to read 4, iclass 39, count 0 2006.257.14:11:24.75#ibcon#read 4, iclass 39, count 0 2006.257.14:11:24.75#ibcon#about to read 5, iclass 39, count 0 2006.257.14:11:24.75#ibcon#read 5, iclass 39, count 0 2006.257.14:11:24.75#ibcon#about to read 6, iclass 39, count 0 2006.257.14:11:24.75#ibcon#read 6, iclass 39, count 0 2006.257.14:11:24.75#ibcon#end of sib2, iclass 39, count 0 2006.257.14:11:24.75#ibcon#*after write, iclass 39, count 0 2006.257.14:11:24.75#ibcon#*before return 0, iclass 39, count 0 2006.257.14:11:24.75#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:24.75#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:24.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.14:11:24.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.14:11:24.75$vck44/valo=3,564.99 2006.257.14:11:24.75#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.14:11:24.75#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.14:11:24.75#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:24.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:11:24.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:11:24.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:11:24.75#ibcon#enter wrdev, iclass 3, count 0 2006.257.14:11:24.75#ibcon#first serial, iclass 3, count 0 2006.257.14:11:24.75#ibcon#enter sib2, iclass 3, count 0 2006.257.14:11:24.75#ibcon#flushed, iclass 3, count 0 2006.257.14:11:24.75#ibcon#about to write, iclass 3, count 0 2006.257.14:11:24.75#ibcon#wrote, iclass 3, count 0 2006.257.14:11:24.75#ibcon#about to read 3, iclass 3, count 0 2006.257.14:11:24.77#ibcon#read 3, iclass 3, count 0 2006.257.14:11:24.77#ibcon#about to read 4, iclass 3, count 0 2006.257.14:11:24.77#ibcon#read 4, iclass 3, count 0 2006.257.14:11:24.77#ibcon#about to read 5, iclass 3, count 0 2006.257.14:11:24.77#ibcon#read 5, iclass 3, count 0 2006.257.14:11:24.77#ibcon#about to read 6, iclass 3, count 0 2006.257.14:11:24.77#ibcon#read 6, iclass 3, count 0 2006.257.14:11:24.77#ibcon#end of sib2, iclass 3, count 0 2006.257.14:11:24.77#ibcon#*mode == 0, iclass 3, count 0 2006.257.14:11:24.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.14:11:24.77#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:11:24.77#ibcon#*before write, iclass 3, count 0 2006.257.14:11:24.77#ibcon#enter sib2, iclass 3, count 0 2006.257.14:11:24.77#ibcon#flushed, iclass 3, count 0 2006.257.14:11:24.77#ibcon#about to write, iclass 3, count 0 2006.257.14:11:24.77#ibcon#wrote, iclass 3, count 0 2006.257.14:11:24.77#ibcon#about to read 3, iclass 3, count 0 2006.257.14:11:24.81#ibcon#read 3, iclass 3, count 0 2006.257.14:11:24.81#ibcon#about to read 4, iclass 3, count 0 2006.257.14:11:24.81#ibcon#read 4, iclass 3, count 0 2006.257.14:11:24.81#ibcon#about to read 5, iclass 3, count 0 2006.257.14:11:24.81#ibcon#read 5, iclass 3, count 0 2006.257.14:11:24.81#ibcon#about to read 6, iclass 3, count 0 2006.257.14:11:24.81#ibcon#read 6, iclass 3, count 0 2006.257.14:11:24.81#ibcon#end of sib2, iclass 3, count 0 2006.257.14:11:24.81#ibcon#*after write, iclass 3, count 0 2006.257.14:11:24.81#ibcon#*before return 0, iclass 3, count 0 2006.257.14:11:24.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:11:24.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:11:24.81#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.14:11:24.81#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.14:11:24.81$vck44/va=3,8 2006.257.14:11:24.81#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.14:11:24.81#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.14:11:24.81#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:24.81#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:11:24.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:11:24.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:11:24.87#ibcon#enter wrdev, iclass 5, count 2 2006.257.14:11:24.87#ibcon#first serial, iclass 5, count 2 2006.257.14:11:24.87#ibcon#enter sib2, iclass 5, count 2 2006.257.14:11:24.87#ibcon#flushed, iclass 5, count 2 2006.257.14:11:24.87#ibcon#about to write, iclass 5, count 2 2006.257.14:11:24.87#ibcon#wrote, iclass 5, count 2 2006.257.14:11:24.87#ibcon#about to read 3, iclass 5, count 2 2006.257.14:11:24.89#ibcon#read 3, iclass 5, count 2 2006.257.14:11:24.89#ibcon#about to read 4, iclass 5, count 2 2006.257.14:11:24.89#ibcon#read 4, iclass 5, count 2 2006.257.14:11:24.89#ibcon#about to read 5, iclass 5, count 2 2006.257.14:11:24.89#ibcon#read 5, iclass 5, count 2 2006.257.14:11:24.89#ibcon#about to read 6, iclass 5, count 2 2006.257.14:11:24.89#ibcon#read 6, iclass 5, count 2 2006.257.14:11:24.89#ibcon#end of sib2, iclass 5, count 2 2006.257.14:11:24.89#ibcon#*mode == 0, iclass 5, count 2 2006.257.14:11:24.89#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.14:11:24.89#ibcon#[25=AT03-08\r\n] 2006.257.14:11:24.89#ibcon#*before write, iclass 5, count 2 2006.257.14:11:24.89#ibcon#enter sib2, iclass 5, count 2 2006.257.14:11:24.89#ibcon#flushed, iclass 5, count 2 2006.257.14:11:24.89#ibcon#about to write, iclass 5, count 2 2006.257.14:11:24.89#ibcon#wrote, iclass 5, count 2 2006.257.14:11:24.89#ibcon#about to read 3, iclass 5, count 2 2006.257.14:11:24.92#ibcon#read 3, iclass 5, count 2 2006.257.14:11:24.92#ibcon#about to read 4, iclass 5, count 2 2006.257.14:11:24.92#ibcon#read 4, iclass 5, count 2 2006.257.14:11:24.92#ibcon#about to read 5, iclass 5, count 2 2006.257.14:11:24.92#ibcon#read 5, iclass 5, count 2 2006.257.14:11:24.92#ibcon#about to read 6, iclass 5, count 2 2006.257.14:11:24.92#ibcon#read 6, iclass 5, count 2 2006.257.14:11:24.92#ibcon#end of sib2, iclass 5, count 2 2006.257.14:11:24.92#ibcon#*after write, iclass 5, count 2 2006.257.14:11:24.92#ibcon#*before return 0, iclass 5, count 2 2006.257.14:11:24.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:11:24.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:11:24.92#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.14:11:24.92#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:24.92#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:11:25.04#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:11:25.04#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:11:25.04#ibcon#enter wrdev, iclass 5, count 0 2006.257.14:11:25.04#ibcon#first serial, iclass 5, count 0 2006.257.14:11:25.04#ibcon#enter sib2, iclass 5, count 0 2006.257.14:11:25.04#ibcon#flushed, iclass 5, count 0 2006.257.14:11:25.04#ibcon#about to write, iclass 5, count 0 2006.257.14:11:25.04#ibcon#wrote, iclass 5, count 0 2006.257.14:11:25.04#ibcon#about to read 3, iclass 5, count 0 2006.257.14:11:25.06#ibcon#read 3, iclass 5, count 0 2006.257.14:11:25.06#ibcon#about to read 4, iclass 5, count 0 2006.257.14:11:25.06#ibcon#read 4, iclass 5, count 0 2006.257.14:11:25.06#ibcon#about to read 5, iclass 5, count 0 2006.257.14:11:25.06#ibcon#read 5, iclass 5, count 0 2006.257.14:11:25.06#ibcon#about to read 6, iclass 5, count 0 2006.257.14:11:25.06#ibcon#read 6, iclass 5, count 0 2006.257.14:11:25.06#ibcon#end of sib2, iclass 5, count 0 2006.257.14:11:25.06#ibcon#*mode == 0, iclass 5, count 0 2006.257.14:11:25.06#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.14:11:25.06#ibcon#[25=USB\r\n] 2006.257.14:11:25.06#ibcon#*before write, iclass 5, count 0 2006.257.14:11:25.06#ibcon#enter sib2, iclass 5, count 0 2006.257.14:11:25.06#ibcon#flushed, iclass 5, count 0 2006.257.14:11:25.06#ibcon#about to write, iclass 5, count 0 2006.257.14:11:25.06#ibcon#wrote, iclass 5, count 0 2006.257.14:11:25.06#ibcon#about to read 3, iclass 5, count 0 2006.257.14:11:25.09#ibcon#read 3, iclass 5, count 0 2006.257.14:11:25.09#ibcon#about to read 4, iclass 5, count 0 2006.257.14:11:25.09#ibcon#read 4, iclass 5, count 0 2006.257.14:11:25.09#ibcon#about to read 5, iclass 5, count 0 2006.257.14:11:25.09#ibcon#read 5, iclass 5, count 0 2006.257.14:11:25.09#ibcon#about to read 6, iclass 5, count 0 2006.257.14:11:25.09#ibcon#read 6, iclass 5, count 0 2006.257.14:11:25.09#ibcon#end of sib2, iclass 5, count 0 2006.257.14:11:25.09#ibcon#*after write, iclass 5, count 0 2006.257.14:11:25.09#ibcon#*before return 0, iclass 5, count 0 2006.257.14:11:25.09#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:11:25.09#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:11:25.09#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.14:11:25.09#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.14:11:25.09$vck44/valo=4,624.99 2006.257.14:11:25.09#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.14:11:25.09#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.14:11:25.09#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:25.09#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:25.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:25.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:25.09#ibcon#enter wrdev, iclass 7, count 0 2006.257.14:11:25.09#ibcon#first serial, iclass 7, count 0 2006.257.14:11:25.09#ibcon#enter sib2, iclass 7, count 0 2006.257.14:11:25.09#ibcon#flushed, iclass 7, count 0 2006.257.14:11:25.09#ibcon#about to write, iclass 7, count 0 2006.257.14:11:25.09#ibcon#wrote, iclass 7, count 0 2006.257.14:11:25.09#ibcon#about to read 3, iclass 7, count 0 2006.257.14:11:25.11#ibcon#read 3, iclass 7, count 0 2006.257.14:11:25.11#ibcon#about to read 4, iclass 7, count 0 2006.257.14:11:25.11#ibcon#read 4, iclass 7, count 0 2006.257.14:11:25.11#ibcon#about to read 5, iclass 7, count 0 2006.257.14:11:25.11#ibcon#read 5, iclass 7, count 0 2006.257.14:11:25.11#ibcon#about to read 6, iclass 7, count 0 2006.257.14:11:25.11#ibcon#read 6, iclass 7, count 0 2006.257.14:11:25.11#ibcon#end of sib2, iclass 7, count 0 2006.257.14:11:25.11#ibcon#*mode == 0, iclass 7, count 0 2006.257.14:11:25.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.14:11:25.11#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:11:25.11#ibcon#*before write, iclass 7, count 0 2006.257.14:11:25.11#ibcon#enter sib2, iclass 7, count 0 2006.257.14:11:25.11#ibcon#flushed, iclass 7, count 0 2006.257.14:11:25.11#ibcon#about to write, iclass 7, count 0 2006.257.14:11:25.11#ibcon#wrote, iclass 7, count 0 2006.257.14:11:25.11#ibcon#about to read 3, iclass 7, count 0 2006.257.14:11:25.15#ibcon#read 3, iclass 7, count 0 2006.257.14:11:25.15#ibcon#about to read 4, iclass 7, count 0 2006.257.14:11:25.15#ibcon#read 4, iclass 7, count 0 2006.257.14:11:25.15#ibcon#about to read 5, iclass 7, count 0 2006.257.14:11:25.15#ibcon#read 5, iclass 7, count 0 2006.257.14:11:25.15#ibcon#about to read 6, iclass 7, count 0 2006.257.14:11:25.15#ibcon#read 6, iclass 7, count 0 2006.257.14:11:25.15#ibcon#end of sib2, iclass 7, count 0 2006.257.14:11:25.15#ibcon#*after write, iclass 7, count 0 2006.257.14:11:25.15#ibcon#*before return 0, iclass 7, count 0 2006.257.14:11:25.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:25.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:25.15#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.14:11:25.15#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.14:11:25.15$vck44/va=4,7 2006.257.14:11:25.15#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.14:11:25.15#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.14:11:25.15#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:25.15#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:25.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:25.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:25.21#ibcon#enter wrdev, iclass 11, count 2 2006.257.14:11:25.21#ibcon#first serial, iclass 11, count 2 2006.257.14:11:25.21#ibcon#enter sib2, iclass 11, count 2 2006.257.14:11:25.21#ibcon#flushed, iclass 11, count 2 2006.257.14:11:25.21#ibcon#about to write, iclass 11, count 2 2006.257.14:11:25.21#ibcon#wrote, iclass 11, count 2 2006.257.14:11:25.21#ibcon#about to read 3, iclass 11, count 2 2006.257.14:11:25.23#ibcon#read 3, iclass 11, count 2 2006.257.14:11:25.23#ibcon#about to read 4, iclass 11, count 2 2006.257.14:11:25.23#ibcon#read 4, iclass 11, count 2 2006.257.14:11:25.23#ibcon#about to read 5, iclass 11, count 2 2006.257.14:11:25.23#ibcon#read 5, iclass 11, count 2 2006.257.14:11:25.23#ibcon#about to read 6, iclass 11, count 2 2006.257.14:11:25.23#ibcon#read 6, iclass 11, count 2 2006.257.14:11:25.23#ibcon#end of sib2, iclass 11, count 2 2006.257.14:11:25.23#ibcon#*mode == 0, iclass 11, count 2 2006.257.14:11:25.23#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.14:11:25.23#ibcon#[25=AT04-07\r\n] 2006.257.14:11:25.23#ibcon#*before write, iclass 11, count 2 2006.257.14:11:25.23#ibcon#enter sib2, iclass 11, count 2 2006.257.14:11:25.23#ibcon#flushed, iclass 11, count 2 2006.257.14:11:25.23#ibcon#about to write, iclass 11, count 2 2006.257.14:11:25.23#ibcon#wrote, iclass 11, count 2 2006.257.14:11:25.23#ibcon#about to read 3, iclass 11, count 2 2006.257.14:11:25.26#ibcon#read 3, iclass 11, count 2 2006.257.14:11:25.26#ibcon#about to read 4, iclass 11, count 2 2006.257.14:11:25.26#ibcon#read 4, iclass 11, count 2 2006.257.14:11:25.26#ibcon#about to read 5, iclass 11, count 2 2006.257.14:11:25.26#ibcon#read 5, iclass 11, count 2 2006.257.14:11:25.26#ibcon#about to read 6, iclass 11, count 2 2006.257.14:11:25.26#ibcon#read 6, iclass 11, count 2 2006.257.14:11:25.26#ibcon#end of sib2, iclass 11, count 2 2006.257.14:11:25.26#ibcon#*after write, iclass 11, count 2 2006.257.14:11:25.26#ibcon#*before return 0, iclass 11, count 2 2006.257.14:11:25.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:25.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:25.26#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.14:11:25.26#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:25.26#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:25.38#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:25.38#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:25.38#ibcon#enter wrdev, iclass 11, count 0 2006.257.14:11:25.38#ibcon#first serial, iclass 11, count 0 2006.257.14:11:25.38#ibcon#enter sib2, iclass 11, count 0 2006.257.14:11:25.38#ibcon#flushed, iclass 11, count 0 2006.257.14:11:25.38#ibcon#about to write, iclass 11, count 0 2006.257.14:11:25.38#ibcon#wrote, iclass 11, count 0 2006.257.14:11:25.38#ibcon#about to read 3, iclass 11, count 0 2006.257.14:11:25.40#ibcon#read 3, iclass 11, count 0 2006.257.14:11:25.40#ibcon#about to read 4, iclass 11, count 0 2006.257.14:11:25.40#ibcon#read 4, iclass 11, count 0 2006.257.14:11:25.40#ibcon#about to read 5, iclass 11, count 0 2006.257.14:11:25.40#ibcon#read 5, iclass 11, count 0 2006.257.14:11:25.40#ibcon#about to read 6, iclass 11, count 0 2006.257.14:11:25.40#ibcon#read 6, iclass 11, count 0 2006.257.14:11:25.40#ibcon#end of sib2, iclass 11, count 0 2006.257.14:11:25.40#ibcon#*mode == 0, iclass 11, count 0 2006.257.14:11:25.40#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.14:11:25.40#ibcon#[25=USB\r\n] 2006.257.14:11:25.40#ibcon#*before write, iclass 11, count 0 2006.257.14:11:25.40#ibcon#enter sib2, iclass 11, count 0 2006.257.14:11:25.40#ibcon#flushed, iclass 11, count 0 2006.257.14:11:25.40#ibcon#about to write, iclass 11, count 0 2006.257.14:11:25.40#ibcon#wrote, iclass 11, count 0 2006.257.14:11:25.40#ibcon#about to read 3, iclass 11, count 0 2006.257.14:11:25.43#ibcon#read 3, iclass 11, count 0 2006.257.14:11:25.43#ibcon#about to read 4, iclass 11, count 0 2006.257.14:11:25.43#ibcon#read 4, iclass 11, count 0 2006.257.14:11:25.43#ibcon#about to read 5, iclass 11, count 0 2006.257.14:11:25.43#ibcon#read 5, iclass 11, count 0 2006.257.14:11:25.43#ibcon#about to read 6, iclass 11, count 0 2006.257.14:11:25.43#ibcon#read 6, iclass 11, count 0 2006.257.14:11:25.43#ibcon#end of sib2, iclass 11, count 0 2006.257.14:11:25.43#ibcon#*after write, iclass 11, count 0 2006.257.14:11:25.43#ibcon#*before return 0, iclass 11, count 0 2006.257.14:11:25.43#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:25.43#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:25.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.14:11:25.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.14:11:25.43$vck44/valo=5,734.99 2006.257.14:11:25.43#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.14:11:25.43#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.14:11:25.43#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:25.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:25.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:25.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:25.43#ibcon#enter wrdev, iclass 13, count 0 2006.257.14:11:25.43#ibcon#first serial, iclass 13, count 0 2006.257.14:11:25.43#ibcon#enter sib2, iclass 13, count 0 2006.257.14:11:25.43#ibcon#flushed, iclass 13, count 0 2006.257.14:11:25.43#ibcon#about to write, iclass 13, count 0 2006.257.14:11:25.43#ibcon#wrote, iclass 13, count 0 2006.257.14:11:25.43#ibcon#about to read 3, iclass 13, count 0 2006.257.14:11:25.45#ibcon#read 3, iclass 13, count 0 2006.257.14:11:25.45#ibcon#about to read 4, iclass 13, count 0 2006.257.14:11:25.45#ibcon#read 4, iclass 13, count 0 2006.257.14:11:25.45#ibcon#about to read 5, iclass 13, count 0 2006.257.14:11:25.45#ibcon#read 5, iclass 13, count 0 2006.257.14:11:25.45#ibcon#about to read 6, iclass 13, count 0 2006.257.14:11:25.45#ibcon#read 6, iclass 13, count 0 2006.257.14:11:25.45#ibcon#end of sib2, iclass 13, count 0 2006.257.14:11:25.45#ibcon#*mode == 0, iclass 13, count 0 2006.257.14:11:25.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.14:11:25.45#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:11:25.45#ibcon#*before write, iclass 13, count 0 2006.257.14:11:25.45#ibcon#enter sib2, iclass 13, count 0 2006.257.14:11:25.45#ibcon#flushed, iclass 13, count 0 2006.257.14:11:25.45#ibcon#about to write, iclass 13, count 0 2006.257.14:11:25.45#ibcon#wrote, iclass 13, count 0 2006.257.14:11:25.45#ibcon#about to read 3, iclass 13, count 0 2006.257.14:11:25.49#ibcon#read 3, iclass 13, count 0 2006.257.14:11:25.49#ibcon#about to read 4, iclass 13, count 0 2006.257.14:11:25.49#ibcon#read 4, iclass 13, count 0 2006.257.14:11:25.49#ibcon#about to read 5, iclass 13, count 0 2006.257.14:11:25.49#ibcon#read 5, iclass 13, count 0 2006.257.14:11:25.49#ibcon#about to read 6, iclass 13, count 0 2006.257.14:11:25.49#ibcon#read 6, iclass 13, count 0 2006.257.14:11:25.49#ibcon#end of sib2, iclass 13, count 0 2006.257.14:11:25.49#ibcon#*after write, iclass 13, count 0 2006.257.14:11:25.49#ibcon#*before return 0, iclass 13, count 0 2006.257.14:11:25.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:25.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:25.49#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.14:11:26.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.14:11:26.20$vck44/va=5,4 2006.257.14:11:26.20#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.14:11:26.20#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.14:11:26.20#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:26.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:26.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:26.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:26.21#ibcon#enter wrdev, iclass 15, count 2 2006.257.14:11:26.21#ibcon#first serial, iclass 15, count 2 2006.257.14:11:26.21#ibcon#enter sib2, iclass 15, count 2 2006.257.14:11:26.21#ibcon#flushed, iclass 15, count 2 2006.257.14:11:26.21#ibcon#about to write, iclass 15, count 2 2006.257.14:11:26.21#ibcon#wrote, iclass 15, count 2 2006.257.14:11:26.21#ibcon#about to read 3, iclass 15, count 2 2006.257.14:11:26.22#ibcon#read 3, iclass 15, count 2 2006.257.14:11:26.22#ibcon#about to read 4, iclass 15, count 2 2006.257.14:11:26.22#ibcon#read 4, iclass 15, count 2 2006.257.14:11:26.22#ibcon#about to read 5, iclass 15, count 2 2006.257.14:11:26.22#ibcon#read 5, iclass 15, count 2 2006.257.14:11:26.22#ibcon#about to read 6, iclass 15, count 2 2006.257.14:11:26.22#ibcon#read 6, iclass 15, count 2 2006.257.14:11:26.22#ibcon#end of sib2, iclass 15, count 2 2006.257.14:11:26.22#ibcon#*mode == 0, iclass 15, count 2 2006.257.14:11:26.22#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.14:11:26.22#ibcon#[25=AT05-04\r\n] 2006.257.14:11:26.22#ibcon#*before write, iclass 15, count 2 2006.257.14:11:26.22#ibcon#enter sib2, iclass 15, count 2 2006.257.14:11:26.22#ibcon#flushed, iclass 15, count 2 2006.257.14:11:26.22#ibcon#about to write, iclass 15, count 2 2006.257.14:11:26.22#ibcon#wrote, iclass 15, count 2 2006.257.14:11:26.22#ibcon#about to read 3, iclass 15, count 2 2006.257.14:11:26.25#ibcon#read 3, iclass 15, count 2 2006.257.14:11:26.25#ibcon#about to read 4, iclass 15, count 2 2006.257.14:11:26.25#ibcon#read 4, iclass 15, count 2 2006.257.14:11:26.25#ibcon#about to read 5, iclass 15, count 2 2006.257.14:11:26.25#ibcon#read 5, iclass 15, count 2 2006.257.14:11:26.25#ibcon#about to read 6, iclass 15, count 2 2006.257.14:11:26.25#ibcon#read 6, iclass 15, count 2 2006.257.14:11:26.25#ibcon#end of sib2, iclass 15, count 2 2006.257.14:11:26.25#ibcon#*after write, iclass 15, count 2 2006.257.14:11:26.25#ibcon#*before return 0, iclass 15, count 2 2006.257.14:11:26.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:26.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:26.25#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.14:11:26.25#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:26.25#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:26.37#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:26.37#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:26.37#ibcon#enter wrdev, iclass 15, count 0 2006.257.14:11:26.37#ibcon#first serial, iclass 15, count 0 2006.257.14:11:26.37#ibcon#enter sib2, iclass 15, count 0 2006.257.14:11:26.37#ibcon#flushed, iclass 15, count 0 2006.257.14:11:26.37#ibcon#about to write, iclass 15, count 0 2006.257.14:11:26.37#ibcon#wrote, iclass 15, count 0 2006.257.14:11:26.37#ibcon#about to read 3, iclass 15, count 0 2006.257.14:11:26.39#ibcon#read 3, iclass 15, count 0 2006.257.14:11:26.39#ibcon#about to read 4, iclass 15, count 0 2006.257.14:11:26.39#ibcon#read 4, iclass 15, count 0 2006.257.14:11:26.39#ibcon#about to read 5, iclass 15, count 0 2006.257.14:11:26.39#ibcon#read 5, iclass 15, count 0 2006.257.14:11:26.39#ibcon#about to read 6, iclass 15, count 0 2006.257.14:11:26.39#ibcon#read 6, iclass 15, count 0 2006.257.14:11:26.39#ibcon#end of sib2, iclass 15, count 0 2006.257.14:11:26.39#ibcon#*mode == 0, iclass 15, count 0 2006.257.14:11:26.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.14:11:26.39#ibcon#[25=USB\r\n] 2006.257.14:11:26.39#ibcon#*before write, iclass 15, count 0 2006.257.14:11:26.39#ibcon#enter sib2, iclass 15, count 0 2006.257.14:11:26.39#ibcon#flushed, iclass 15, count 0 2006.257.14:11:26.39#ibcon#about to write, iclass 15, count 0 2006.257.14:11:26.39#ibcon#wrote, iclass 15, count 0 2006.257.14:11:26.39#ibcon#about to read 3, iclass 15, count 0 2006.257.14:11:26.42#ibcon#read 3, iclass 15, count 0 2006.257.14:11:26.42#ibcon#about to read 4, iclass 15, count 0 2006.257.14:11:26.42#ibcon#read 4, iclass 15, count 0 2006.257.14:11:26.42#ibcon#about to read 5, iclass 15, count 0 2006.257.14:11:26.42#ibcon#read 5, iclass 15, count 0 2006.257.14:11:26.42#ibcon#about to read 6, iclass 15, count 0 2006.257.14:11:26.42#ibcon#read 6, iclass 15, count 0 2006.257.14:11:26.42#ibcon#end of sib2, iclass 15, count 0 2006.257.14:11:26.42#ibcon#*after write, iclass 15, count 0 2006.257.14:11:26.42#ibcon#*before return 0, iclass 15, count 0 2006.257.14:11:26.42#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:26.42#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:26.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.14:11:26.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.14:11:26.42$vck44/valo=6,814.99 2006.257.14:11:26.42#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.14:11:26.42#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.14:11:26.42#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:26.42#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:26.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:26.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:26.42#ibcon#enter wrdev, iclass 17, count 0 2006.257.14:11:26.42#ibcon#first serial, iclass 17, count 0 2006.257.14:11:26.42#ibcon#enter sib2, iclass 17, count 0 2006.257.14:11:26.42#ibcon#flushed, iclass 17, count 0 2006.257.14:11:26.42#ibcon#about to write, iclass 17, count 0 2006.257.14:11:26.42#ibcon#wrote, iclass 17, count 0 2006.257.14:11:26.42#ibcon#about to read 3, iclass 17, count 0 2006.257.14:11:26.44#ibcon#read 3, iclass 17, count 0 2006.257.14:11:26.44#ibcon#about to read 4, iclass 17, count 0 2006.257.14:11:26.44#ibcon#read 4, iclass 17, count 0 2006.257.14:11:26.44#ibcon#about to read 5, iclass 17, count 0 2006.257.14:11:26.44#ibcon#read 5, iclass 17, count 0 2006.257.14:11:26.44#ibcon#about to read 6, iclass 17, count 0 2006.257.14:11:26.44#ibcon#read 6, iclass 17, count 0 2006.257.14:11:26.44#ibcon#end of sib2, iclass 17, count 0 2006.257.14:11:26.44#ibcon#*mode == 0, iclass 17, count 0 2006.257.14:11:26.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.14:11:26.44#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:11:26.44#ibcon#*before write, iclass 17, count 0 2006.257.14:11:26.44#ibcon#enter sib2, iclass 17, count 0 2006.257.14:11:26.44#ibcon#flushed, iclass 17, count 0 2006.257.14:11:26.44#ibcon#about to write, iclass 17, count 0 2006.257.14:11:26.44#ibcon#wrote, iclass 17, count 0 2006.257.14:11:26.44#ibcon#about to read 3, iclass 17, count 0 2006.257.14:11:26.48#ibcon#read 3, iclass 17, count 0 2006.257.14:11:26.48#ibcon#about to read 4, iclass 17, count 0 2006.257.14:11:26.48#ibcon#read 4, iclass 17, count 0 2006.257.14:11:26.48#ibcon#about to read 5, iclass 17, count 0 2006.257.14:11:26.48#ibcon#read 5, iclass 17, count 0 2006.257.14:11:26.48#ibcon#about to read 6, iclass 17, count 0 2006.257.14:11:26.48#ibcon#read 6, iclass 17, count 0 2006.257.14:11:26.48#ibcon#end of sib2, iclass 17, count 0 2006.257.14:11:26.48#ibcon#*after write, iclass 17, count 0 2006.257.14:11:26.48#ibcon#*before return 0, iclass 17, count 0 2006.257.14:11:26.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:26.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:26.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.14:11:26.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.14:11:26.48$vck44/va=6,4 2006.257.14:11:26.48#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.14:11:26.48#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.14:11:26.48#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:26.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:26.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:26.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:26.54#ibcon#enter wrdev, iclass 19, count 2 2006.257.14:11:26.54#ibcon#first serial, iclass 19, count 2 2006.257.14:11:26.54#ibcon#enter sib2, iclass 19, count 2 2006.257.14:11:26.54#ibcon#flushed, iclass 19, count 2 2006.257.14:11:26.54#ibcon#about to write, iclass 19, count 2 2006.257.14:11:26.54#ibcon#wrote, iclass 19, count 2 2006.257.14:11:26.54#ibcon#about to read 3, iclass 19, count 2 2006.257.14:11:26.56#ibcon#read 3, iclass 19, count 2 2006.257.14:11:26.56#ibcon#about to read 4, iclass 19, count 2 2006.257.14:11:26.56#ibcon#read 4, iclass 19, count 2 2006.257.14:11:26.56#ibcon#about to read 5, iclass 19, count 2 2006.257.14:11:26.56#ibcon#read 5, iclass 19, count 2 2006.257.14:11:26.56#ibcon#about to read 6, iclass 19, count 2 2006.257.14:11:26.56#ibcon#read 6, iclass 19, count 2 2006.257.14:11:26.56#ibcon#end of sib2, iclass 19, count 2 2006.257.14:11:26.56#ibcon#*mode == 0, iclass 19, count 2 2006.257.14:11:26.56#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.14:11:26.56#ibcon#[25=AT06-04\r\n] 2006.257.14:11:26.56#ibcon#*before write, iclass 19, count 2 2006.257.14:11:26.56#ibcon#enter sib2, iclass 19, count 2 2006.257.14:11:26.56#ibcon#flushed, iclass 19, count 2 2006.257.14:11:26.56#ibcon#about to write, iclass 19, count 2 2006.257.14:11:26.56#ibcon#wrote, iclass 19, count 2 2006.257.14:11:26.56#ibcon#about to read 3, iclass 19, count 2 2006.257.14:11:26.59#ibcon#read 3, iclass 19, count 2 2006.257.14:11:26.59#ibcon#about to read 4, iclass 19, count 2 2006.257.14:11:26.59#ibcon#read 4, iclass 19, count 2 2006.257.14:11:26.59#ibcon#about to read 5, iclass 19, count 2 2006.257.14:11:26.59#ibcon#read 5, iclass 19, count 2 2006.257.14:11:26.59#ibcon#about to read 6, iclass 19, count 2 2006.257.14:11:26.59#ibcon#read 6, iclass 19, count 2 2006.257.14:11:26.59#ibcon#end of sib2, iclass 19, count 2 2006.257.14:11:26.59#ibcon#*after write, iclass 19, count 2 2006.257.14:11:26.59#ibcon#*before return 0, iclass 19, count 2 2006.257.14:11:26.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:26.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:26.59#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.14:11:26.59#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:26.59#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:26.71#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:26.71#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:26.71#ibcon#enter wrdev, iclass 19, count 0 2006.257.14:11:26.71#ibcon#first serial, iclass 19, count 0 2006.257.14:11:26.71#ibcon#enter sib2, iclass 19, count 0 2006.257.14:11:26.71#ibcon#flushed, iclass 19, count 0 2006.257.14:11:26.71#ibcon#about to write, iclass 19, count 0 2006.257.14:11:26.71#ibcon#wrote, iclass 19, count 0 2006.257.14:11:26.71#ibcon#about to read 3, iclass 19, count 0 2006.257.14:11:26.73#ibcon#read 3, iclass 19, count 0 2006.257.14:11:26.73#ibcon#about to read 4, iclass 19, count 0 2006.257.14:11:26.73#ibcon#read 4, iclass 19, count 0 2006.257.14:11:26.73#ibcon#about to read 5, iclass 19, count 0 2006.257.14:11:26.73#ibcon#read 5, iclass 19, count 0 2006.257.14:11:26.73#ibcon#about to read 6, iclass 19, count 0 2006.257.14:11:26.73#ibcon#read 6, iclass 19, count 0 2006.257.14:11:26.73#ibcon#end of sib2, iclass 19, count 0 2006.257.14:11:26.73#ibcon#*mode == 0, iclass 19, count 0 2006.257.14:11:26.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.14:11:26.73#ibcon#[25=USB\r\n] 2006.257.14:11:26.73#ibcon#*before write, iclass 19, count 0 2006.257.14:11:26.73#ibcon#enter sib2, iclass 19, count 0 2006.257.14:11:26.73#ibcon#flushed, iclass 19, count 0 2006.257.14:11:26.73#ibcon#about to write, iclass 19, count 0 2006.257.14:11:26.73#ibcon#wrote, iclass 19, count 0 2006.257.14:11:26.73#ibcon#about to read 3, iclass 19, count 0 2006.257.14:11:26.76#ibcon#read 3, iclass 19, count 0 2006.257.14:11:26.76#ibcon#about to read 4, iclass 19, count 0 2006.257.14:11:26.76#ibcon#read 4, iclass 19, count 0 2006.257.14:11:26.76#ibcon#about to read 5, iclass 19, count 0 2006.257.14:11:26.76#ibcon#read 5, iclass 19, count 0 2006.257.14:11:26.76#ibcon#about to read 6, iclass 19, count 0 2006.257.14:11:26.76#ibcon#read 6, iclass 19, count 0 2006.257.14:11:26.76#ibcon#end of sib2, iclass 19, count 0 2006.257.14:11:26.76#ibcon#*after write, iclass 19, count 0 2006.257.14:11:26.76#ibcon#*before return 0, iclass 19, count 0 2006.257.14:11:26.76#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:26.76#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:26.76#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.14:11:26.76#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.14:11:26.76$vck44/valo=7,864.99 2006.257.14:11:26.76#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.14:11:26.76#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.14:11:26.76#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:26.76#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:26.76#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:26.76#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:26.76#ibcon#enter wrdev, iclass 21, count 0 2006.257.14:11:26.76#ibcon#first serial, iclass 21, count 0 2006.257.14:11:26.76#ibcon#enter sib2, iclass 21, count 0 2006.257.14:11:26.76#ibcon#flushed, iclass 21, count 0 2006.257.14:11:26.76#ibcon#about to write, iclass 21, count 0 2006.257.14:11:26.76#ibcon#wrote, iclass 21, count 0 2006.257.14:11:26.76#ibcon#about to read 3, iclass 21, count 0 2006.257.14:11:26.78#ibcon#read 3, iclass 21, count 0 2006.257.14:11:26.78#ibcon#about to read 4, iclass 21, count 0 2006.257.14:11:26.78#ibcon#read 4, iclass 21, count 0 2006.257.14:11:26.78#ibcon#about to read 5, iclass 21, count 0 2006.257.14:11:26.78#ibcon#read 5, iclass 21, count 0 2006.257.14:11:26.78#ibcon#about to read 6, iclass 21, count 0 2006.257.14:11:26.78#ibcon#read 6, iclass 21, count 0 2006.257.14:11:26.78#ibcon#end of sib2, iclass 21, count 0 2006.257.14:11:26.78#ibcon#*mode == 0, iclass 21, count 0 2006.257.14:11:26.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.14:11:26.78#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:11:26.78#ibcon#*before write, iclass 21, count 0 2006.257.14:11:26.78#ibcon#enter sib2, iclass 21, count 0 2006.257.14:11:26.78#ibcon#flushed, iclass 21, count 0 2006.257.14:11:26.78#ibcon#about to write, iclass 21, count 0 2006.257.14:11:26.78#ibcon#wrote, iclass 21, count 0 2006.257.14:11:26.78#ibcon#about to read 3, iclass 21, count 0 2006.257.14:11:26.82#ibcon#read 3, iclass 21, count 0 2006.257.14:11:26.82#ibcon#about to read 4, iclass 21, count 0 2006.257.14:11:26.82#ibcon#read 4, iclass 21, count 0 2006.257.14:11:26.82#ibcon#about to read 5, iclass 21, count 0 2006.257.14:11:26.82#ibcon#read 5, iclass 21, count 0 2006.257.14:11:26.82#ibcon#about to read 6, iclass 21, count 0 2006.257.14:11:26.82#ibcon#read 6, iclass 21, count 0 2006.257.14:11:26.82#ibcon#end of sib2, iclass 21, count 0 2006.257.14:11:26.82#ibcon#*after write, iclass 21, count 0 2006.257.14:11:26.82#ibcon#*before return 0, iclass 21, count 0 2006.257.14:11:26.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:26.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:26.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.14:11:26.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.14:11:26.82$vck44/va=7,4 2006.257.14:11:26.82#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.14:11:26.82#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.14:11:26.82#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:26.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:26.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:26.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:26.88#ibcon#enter wrdev, iclass 23, count 2 2006.257.14:11:26.88#ibcon#first serial, iclass 23, count 2 2006.257.14:11:26.88#ibcon#enter sib2, iclass 23, count 2 2006.257.14:11:26.88#ibcon#flushed, iclass 23, count 2 2006.257.14:11:26.88#ibcon#about to write, iclass 23, count 2 2006.257.14:11:26.88#ibcon#wrote, iclass 23, count 2 2006.257.14:11:26.88#ibcon#about to read 3, iclass 23, count 2 2006.257.14:11:26.90#ibcon#read 3, iclass 23, count 2 2006.257.14:11:26.90#ibcon#about to read 4, iclass 23, count 2 2006.257.14:11:26.90#ibcon#read 4, iclass 23, count 2 2006.257.14:11:26.90#ibcon#about to read 5, iclass 23, count 2 2006.257.14:11:26.90#ibcon#read 5, iclass 23, count 2 2006.257.14:11:26.90#ibcon#about to read 6, iclass 23, count 2 2006.257.14:11:26.90#ibcon#read 6, iclass 23, count 2 2006.257.14:11:26.90#ibcon#end of sib2, iclass 23, count 2 2006.257.14:11:26.90#ibcon#*mode == 0, iclass 23, count 2 2006.257.14:11:26.90#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.14:11:26.90#ibcon#[25=AT07-04\r\n] 2006.257.14:11:26.90#ibcon#*before write, iclass 23, count 2 2006.257.14:11:26.90#ibcon#enter sib2, iclass 23, count 2 2006.257.14:11:26.90#ibcon#flushed, iclass 23, count 2 2006.257.14:11:26.90#ibcon#about to write, iclass 23, count 2 2006.257.14:11:26.90#ibcon#wrote, iclass 23, count 2 2006.257.14:11:26.90#ibcon#about to read 3, iclass 23, count 2 2006.257.14:11:26.93#ibcon#read 3, iclass 23, count 2 2006.257.14:11:26.93#ibcon#about to read 4, iclass 23, count 2 2006.257.14:11:26.93#ibcon#read 4, iclass 23, count 2 2006.257.14:11:26.93#ibcon#about to read 5, iclass 23, count 2 2006.257.14:11:26.93#ibcon#read 5, iclass 23, count 2 2006.257.14:11:26.93#ibcon#about to read 6, iclass 23, count 2 2006.257.14:11:26.93#ibcon#read 6, iclass 23, count 2 2006.257.14:11:26.93#ibcon#end of sib2, iclass 23, count 2 2006.257.14:11:26.93#ibcon#*after write, iclass 23, count 2 2006.257.14:11:26.93#ibcon#*before return 0, iclass 23, count 2 2006.257.14:11:26.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:26.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:26.93#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.14:11:26.93#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:26.93#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:27.05#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:27.05#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:27.05#ibcon#enter wrdev, iclass 23, count 0 2006.257.14:11:27.05#ibcon#first serial, iclass 23, count 0 2006.257.14:11:27.05#ibcon#enter sib2, iclass 23, count 0 2006.257.14:11:27.05#ibcon#flushed, iclass 23, count 0 2006.257.14:11:27.05#ibcon#about to write, iclass 23, count 0 2006.257.14:11:27.05#ibcon#wrote, iclass 23, count 0 2006.257.14:11:27.05#ibcon#about to read 3, iclass 23, count 0 2006.257.14:11:27.07#ibcon#read 3, iclass 23, count 0 2006.257.14:11:27.07#ibcon#about to read 4, iclass 23, count 0 2006.257.14:11:27.07#ibcon#read 4, iclass 23, count 0 2006.257.14:11:27.07#ibcon#about to read 5, iclass 23, count 0 2006.257.14:11:27.07#ibcon#read 5, iclass 23, count 0 2006.257.14:11:27.07#ibcon#about to read 6, iclass 23, count 0 2006.257.14:11:27.07#ibcon#read 6, iclass 23, count 0 2006.257.14:11:27.07#ibcon#end of sib2, iclass 23, count 0 2006.257.14:11:27.07#ibcon#*mode == 0, iclass 23, count 0 2006.257.14:11:27.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.14:11:27.07#ibcon#[25=USB\r\n] 2006.257.14:11:27.07#ibcon#*before write, iclass 23, count 0 2006.257.14:11:27.07#ibcon#enter sib2, iclass 23, count 0 2006.257.14:11:27.07#ibcon#flushed, iclass 23, count 0 2006.257.14:11:27.07#ibcon#about to write, iclass 23, count 0 2006.257.14:11:27.07#ibcon#wrote, iclass 23, count 0 2006.257.14:11:27.07#ibcon#about to read 3, iclass 23, count 0 2006.257.14:11:27.10#ibcon#read 3, iclass 23, count 0 2006.257.14:11:27.10#ibcon#about to read 4, iclass 23, count 0 2006.257.14:11:27.10#ibcon#read 4, iclass 23, count 0 2006.257.14:11:27.10#ibcon#about to read 5, iclass 23, count 0 2006.257.14:11:27.10#ibcon#read 5, iclass 23, count 0 2006.257.14:11:27.10#ibcon#about to read 6, iclass 23, count 0 2006.257.14:11:27.10#ibcon#read 6, iclass 23, count 0 2006.257.14:11:27.10#ibcon#end of sib2, iclass 23, count 0 2006.257.14:11:27.10#ibcon#*after write, iclass 23, count 0 2006.257.14:11:27.10#ibcon#*before return 0, iclass 23, count 0 2006.257.14:11:27.10#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:27.10#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:27.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.14:11:27.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.14:11:27.10$vck44/valo=8,884.99 2006.257.14:11:27.10#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.14:11:27.10#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.14:11:27.10#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:27.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:27.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:27.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:27.10#ibcon#enter wrdev, iclass 25, count 0 2006.257.14:11:27.10#ibcon#first serial, iclass 25, count 0 2006.257.14:11:27.10#ibcon#enter sib2, iclass 25, count 0 2006.257.14:11:27.10#ibcon#flushed, iclass 25, count 0 2006.257.14:11:27.10#ibcon#about to write, iclass 25, count 0 2006.257.14:11:27.10#ibcon#wrote, iclass 25, count 0 2006.257.14:11:27.10#ibcon#about to read 3, iclass 25, count 0 2006.257.14:11:27.12#ibcon#read 3, iclass 25, count 0 2006.257.14:11:27.12#ibcon#about to read 4, iclass 25, count 0 2006.257.14:11:27.12#ibcon#read 4, iclass 25, count 0 2006.257.14:11:27.12#ibcon#about to read 5, iclass 25, count 0 2006.257.14:11:27.12#ibcon#read 5, iclass 25, count 0 2006.257.14:11:27.12#ibcon#about to read 6, iclass 25, count 0 2006.257.14:11:27.12#ibcon#read 6, iclass 25, count 0 2006.257.14:11:27.12#ibcon#end of sib2, iclass 25, count 0 2006.257.14:11:27.12#ibcon#*mode == 0, iclass 25, count 0 2006.257.14:11:27.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.14:11:27.12#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:11:27.12#ibcon#*before write, iclass 25, count 0 2006.257.14:11:27.12#ibcon#enter sib2, iclass 25, count 0 2006.257.14:11:27.12#ibcon#flushed, iclass 25, count 0 2006.257.14:11:27.12#ibcon#about to write, iclass 25, count 0 2006.257.14:11:27.12#ibcon#wrote, iclass 25, count 0 2006.257.14:11:27.12#ibcon#about to read 3, iclass 25, count 0 2006.257.14:11:27.16#ibcon#read 3, iclass 25, count 0 2006.257.14:11:27.16#ibcon#about to read 4, iclass 25, count 0 2006.257.14:11:27.16#ibcon#read 4, iclass 25, count 0 2006.257.14:11:27.16#ibcon#about to read 5, iclass 25, count 0 2006.257.14:11:27.16#ibcon#read 5, iclass 25, count 0 2006.257.14:11:27.16#ibcon#about to read 6, iclass 25, count 0 2006.257.14:11:27.16#ibcon#read 6, iclass 25, count 0 2006.257.14:11:27.16#ibcon#end of sib2, iclass 25, count 0 2006.257.14:11:27.16#ibcon#*after write, iclass 25, count 0 2006.257.14:11:27.16#ibcon#*before return 0, iclass 25, count 0 2006.257.14:11:27.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:27.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:27.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.14:11:27.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.14:11:27.16$vck44/va=8,4 2006.257.14:11:27.16#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.14:11:27.16#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.14:11:27.16#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:27.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:27.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:27.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:27.22#ibcon#enter wrdev, iclass 27, count 2 2006.257.14:11:27.22#ibcon#first serial, iclass 27, count 2 2006.257.14:11:27.22#ibcon#enter sib2, iclass 27, count 2 2006.257.14:11:27.22#ibcon#flushed, iclass 27, count 2 2006.257.14:11:27.22#ibcon#about to write, iclass 27, count 2 2006.257.14:11:27.22#ibcon#wrote, iclass 27, count 2 2006.257.14:11:27.22#ibcon#about to read 3, iclass 27, count 2 2006.257.14:11:27.24#ibcon#read 3, iclass 27, count 2 2006.257.14:11:27.24#ibcon#about to read 4, iclass 27, count 2 2006.257.14:11:27.24#ibcon#read 4, iclass 27, count 2 2006.257.14:11:27.24#ibcon#about to read 5, iclass 27, count 2 2006.257.14:11:27.24#ibcon#read 5, iclass 27, count 2 2006.257.14:11:27.24#ibcon#about to read 6, iclass 27, count 2 2006.257.14:11:27.24#ibcon#read 6, iclass 27, count 2 2006.257.14:11:27.24#ibcon#end of sib2, iclass 27, count 2 2006.257.14:11:27.24#ibcon#*mode == 0, iclass 27, count 2 2006.257.14:11:27.24#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.14:11:27.24#ibcon#[25=AT08-04\r\n] 2006.257.14:11:27.24#ibcon#*before write, iclass 27, count 2 2006.257.14:11:27.24#ibcon#enter sib2, iclass 27, count 2 2006.257.14:11:27.24#ibcon#flushed, iclass 27, count 2 2006.257.14:11:27.24#ibcon#about to write, iclass 27, count 2 2006.257.14:11:27.24#ibcon#wrote, iclass 27, count 2 2006.257.14:11:27.24#ibcon#about to read 3, iclass 27, count 2 2006.257.14:11:27.27#ibcon#read 3, iclass 27, count 2 2006.257.14:11:27.27#ibcon#about to read 4, iclass 27, count 2 2006.257.14:11:27.27#ibcon#read 4, iclass 27, count 2 2006.257.14:11:27.27#ibcon#about to read 5, iclass 27, count 2 2006.257.14:11:27.27#ibcon#read 5, iclass 27, count 2 2006.257.14:11:27.27#ibcon#about to read 6, iclass 27, count 2 2006.257.14:11:27.27#ibcon#read 6, iclass 27, count 2 2006.257.14:11:27.27#ibcon#end of sib2, iclass 27, count 2 2006.257.14:11:27.27#ibcon#*after write, iclass 27, count 2 2006.257.14:11:28.27#ibcon#*before return 0, iclass 27, count 2 2006.257.14:11:28.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:28.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:28.27#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.14:11:28.27#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:28.27#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:28.39#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:28.39#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:28.39#ibcon#enter wrdev, iclass 27, count 0 2006.257.14:11:28.39#ibcon#first serial, iclass 27, count 0 2006.257.14:11:28.39#ibcon#enter sib2, iclass 27, count 0 2006.257.14:11:28.39#ibcon#flushed, iclass 27, count 0 2006.257.14:11:28.39#ibcon#about to write, iclass 27, count 0 2006.257.14:11:28.39#ibcon#wrote, iclass 27, count 0 2006.257.14:11:28.39#ibcon#about to read 3, iclass 27, count 0 2006.257.14:11:28.41#ibcon#read 3, iclass 27, count 0 2006.257.14:11:28.41#ibcon#about to read 4, iclass 27, count 0 2006.257.14:11:28.41#ibcon#read 4, iclass 27, count 0 2006.257.14:11:28.41#ibcon#about to read 5, iclass 27, count 0 2006.257.14:11:28.41#ibcon#read 5, iclass 27, count 0 2006.257.14:11:28.41#ibcon#about to read 6, iclass 27, count 0 2006.257.14:11:28.41#ibcon#read 6, iclass 27, count 0 2006.257.14:11:28.41#ibcon#end of sib2, iclass 27, count 0 2006.257.14:11:28.41#ibcon#*mode == 0, iclass 27, count 0 2006.257.14:11:28.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.14:11:28.41#ibcon#[25=USB\r\n] 2006.257.14:11:28.41#ibcon#*before write, iclass 27, count 0 2006.257.14:11:28.41#ibcon#enter sib2, iclass 27, count 0 2006.257.14:11:28.41#ibcon#flushed, iclass 27, count 0 2006.257.14:11:28.41#ibcon#about to write, iclass 27, count 0 2006.257.14:11:28.41#ibcon#wrote, iclass 27, count 0 2006.257.14:11:28.41#ibcon#about to read 3, iclass 27, count 0 2006.257.14:11:28.44#ibcon#read 3, iclass 27, count 0 2006.257.14:11:28.44#ibcon#about to read 4, iclass 27, count 0 2006.257.14:11:28.44#ibcon#read 4, iclass 27, count 0 2006.257.14:11:28.44#ibcon#about to read 5, iclass 27, count 0 2006.257.14:11:28.44#ibcon#read 5, iclass 27, count 0 2006.257.14:11:28.44#ibcon#about to read 6, iclass 27, count 0 2006.257.14:11:28.44#ibcon#read 6, iclass 27, count 0 2006.257.14:11:28.44#ibcon#end of sib2, iclass 27, count 0 2006.257.14:11:28.44#ibcon#*after write, iclass 27, count 0 2006.257.14:11:28.44#ibcon#*before return 0, iclass 27, count 0 2006.257.14:11:28.44#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:28.44#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:28.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.14:11:28.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.14:11:28.44$vck44/vblo=1,629.99 2006.257.14:11:28.44#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.14:11:28.44#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.14:11:28.44#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:28.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:28.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:28.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:28.44#ibcon#enter wrdev, iclass 29, count 0 2006.257.14:11:28.44#ibcon#first serial, iclass 29, count 0 2006.257.14:11:28.44#ibcon#enter sib2, iclass 29, count 0 2006.257.14:11:28.44#ibcon#flushed, iclass 29, count 0 2006.257.14:11:28.44#ibcon#about to write, iclass 29, count 0 2006.257.14:11:28.44#ibcon#wrote, iclass 29, count 0 2006.257.14:11:28.44#ibcon#about to read 3, iclass 29, count 0 2006.257.14:11:28.46#ibcon#read 3, iclass 29, count 0 2006.257.14:11:28.46#ibcon#about to read 4, iclass 29, count 0 2006.257.14:11:28.46#ibcon#read 4, iclass 29, count 0 2006.257.14:11:28.46#ibcon#about to read 5, iclass 29, count 0 2006.257.14:11:28.46#ibcon#read 5, iclass 29, count 0 2006.257.14:11:28.46#ibcon#about to read 6, iclass 29, count 0 2006.257.14:11:28.46#ibcon#read 6, iclass 29, count 0 2006.257.14:11:28.46#ibcon#end of sib2, iclass 29, count 0 2006.257.14:11:28.46#ibcon#*mode == 0, iclass 29, count 0 2006.257.14:11:28.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.14:11:28.46#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:11:28.46#ibcon#*before write, iclass 29, count 0 2006.257.14:11:28.46#ibcon#enter sib2, iclass 29, count 0 2006.257.14:11:28.46#ibcon#flushed, iclass 29, count 0 2006.257.14:11:28.46#ibcon#about to write, iclass 29, count 0 2006.257.14:11:28.46#ibcon#wrote, iclass 29, count 0 2006.257.14:11:28.46#ibcon#about to read 3, iclass 29, count 0 2006.257.14:11:28.50#ibcon#read 3, iclass 29, count 0 2006.257.14:11:28.50#ibcon#about to read 4, iclass 29, count 0 2006.257.14:11:28.50#ibcon#read 4, iclass 29, count 0 2006.257.14:11:28.50#ibcon#about to read 5, iclass 29, count 0 2006.257.14:11:28.50#ibcon#read 5, iclass 29, count 0 2006.257.14:11:28.50#ibcon#about to read 6, iclass 29, count 0 2006.257.14:11:28.50#ibcon#read 6, iclass 29, count 0 2006.257.14:11:28.50#ibcon#end of sib2, iclass 29, count 0 2006.257.14:11:28.50#ibcon#*after write, iclass 29, count 0 2006.257.14:11:28.50#ibcon#*before return 0, iclass 29, count 0 2006.257.14:11:28.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:28.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:28.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.14:11:28.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.14:11:28.50$vck44/vb=1,4 2006.257.14:11:28.50#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.14:11:28.50#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.14:11:28.50#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:28.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:11:28.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:11:28.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:11:28.50#ibcon#enter wrdev, iclass 31, count 2 2006.257.14:11:28.50#ibcon#first serial, iclass 31, count 2 2006.257.14:11:28.50#ibcon#enter sib2, iclass 31, count 2 2006.257.14:11:28.50#ibcon#flushed, iclass 31, count 2 2006.257.14:11:28.50#ibcon#about to write, iclass 31, count 2 2006.257.14:11:28.50#ibcon#wrote, iclass 31, count 2 2006.257.14:11:28.50#ibcon#about to read 3, iclass 31, count 2 2006.257.14:11:28.52#ibcon#read 3, iclass 31, count 2 2006.257.14:11:28.52#ibcon#about to read 4, iclass 31, count 2 2006.257.14:11:28.52#ibcon#read 4, iclass 31, count 2 2006.257.14:11:28.52#ibcon#about to read 5, iclass 31, count 2 2006.257.14:11:28.52#ibcon#read 5, iclass 31, count 2 2006.257.14:11:28.52#ibcon#about to read 6, iclass 31, count 2 2006.257.14:11:28.52#ibcon#read 6, iclass 31, count 2 2006.257.14:11:28.52#ibcon#end of sib2, iclass 31, count 2 2006.257.14:11:28.52#ibcon#*mode == 0, iclass 31, count 2 2006.257.14:11:28.52#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.14:11:28.52#ibcon#[27=AT01-04\r\n] 2006.257.14:11:28.52#ibcon#*before write, iclass 31, count 2 2006.257.14:11:28.52#ibcon#enter sib2, iclass 31, count 2 2006.257.14:11:28.52#ibcon#flushed, iclass 31, count 2 2006.257.14:11:28.52#ibcon#about to write, iclass 31, count 2 2006.257.14:11:28.52#ibcon#wrote, iclass 31, count 2 2006.257.14:11:28.52#ibcon#about to read 3, iclass 31, count 2 2006.257.14:11:28.55#ibcon#read 3, iclass 31, count 2 2006.257.14:11:28.55#ibcon#about to read 4, iclass 31, count 2 2006.257.14:11:28.55#ibcon#read 4, iclass 31, count 2 2006.257.14:11:28.55#ibcon#about to read 5, iclass 31, count 2 2006.257.14:11:28.55#ibcon#read 5, iclass 31, count 2 2006.257.14:11:28.55#ibcon#about to read 6, iclass 31, count 2 2006.257.14:11:28.55#ibcon#read 6, iclass 31, count 2 2006.257.14:11:28.55#ibcon#end of sib2, iclass 31, count 2 2006.257.14:11:28.55#ibcon#*after write, iclass 31, count 2 2006.257.14:11:28.55#ibcon#*before return 0, iclass 31, count 2 2006.257.14:11:28.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:11:28.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:11:28.55#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.14:11:28.55#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:28.55#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:11:28.67#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:11:28.67#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:11:28.67#ibcon#enter wrdev, iclass 31, count 0 2006.257.14:11:28.67#ibcon#first serial, iclass 31, count 0 2006.257.14:11:28.67#ibcon#enter sib2, iclass 31, count 0 2006.257.14:11:28.67#ibcon#flushed, iclass 31, count 0 2006.257.14:11:28.67#ibcon#about to write, iclass 31, count 0 2006.257.14:11:28.67#ibcon#wrote, iclass 31, count 0 2006.257.14:11:28.67#ibcon#about to read 3, iclass 31, count 0 2006.257.14:11:28.69#ibcon#read 3, iclass 31, count 0 2006.257.14:11:28.69#ibcon#about to read 4, iclass 31, count 0 2006.257.14:11:28.69#ibcon#read 4, iclass 31, count 0 2006.257.14:11:28.69#ibcon#about to read 5, iclass 31, count 0 2006.257.14:11:28.69#ibcon#read 5, iclass 31, count 0 2006.257.14:11:28.69#ibcon#about to read 6, iclass 31, count 0 2006.257.14:11:28.69#ibcon#read 6, iclass 31, count 0 2006.257.14:11:28.69#ibcon#end of sib2, iclass 31, count 0 2006.257.14:11:28.69#ibcon#*mode == 0, iclass 31, count 0 2006.257.14:11:28.69#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.14:11:28.69#ibcon#[27=USB\r\n] 2006.257.14:11:28.69#ibcon#*before write, iclass 31, count 0 2006.257.14:11:28.69#ibcon#enter sib2, iclass 31, count 0 2006.257.14:11:28.69#ibcon#flushed, iclass 31, count 0 2006.257.14:11:28.69#ibcon#about to write, iclass 31, count 0 2006.257.14:11:28.69#ibcon#wrote, iclass 31, count 0 2006.257.14:11:28.69#ibcon#about to read 3, iclass 31, count 0 2006.257.14:11:28.72#ibcon#read 3, iclass 31, count 0 2006.257.14:11:28.72#ibcon#about to read 4, iclass 31, count 0 2006.257.14:11:28.72#ibcon#read 4, iclass 31, count 0 2006.257.14:11:28.72#ibcon#about to read 5, iclass 31, count 0 2006.257.14:11:28.72#ibcon#read 5, iclass 31, count 0 2006.257.14:11:28.72#ibcon#about to read 6, iclass 31, count 0 2006.257.14:11:28.72#ibcon#read 6, iclass 31, count 0 2006.257.14:11:28.72#ibcon#end of sib2, iclass 31, count 0 2006.257.14:11:28.72#ibcon#*after write, iclass 31, count 0 2006.257.14:11:28.72#ibcon#*before return 0, iclass 31, count 0 2006.257.14:11:28.72#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:11:28.72#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:11:28.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.14:11:28.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.14:11:28.72$vck44/vblo=2,634.99 2006.257.14:11:28.72#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.14:11:28.72#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.14:11:28.72#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:28.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:28.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:28.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:28.72#ibcon#enter wrdev, iclass 33, count 0 2006.257.14:11:28.72#ibcon#first serial, iclass 33, count 0 2006.257.14:11:28.72#ibcon#enter sib2, iclass 33, count 0 2006.257.14:11:28.72#ibcon#flushed, iclass 33, count 0 2006.257.14:11:28.72#ibcon#about to write, iclass 33, count 0 2006.257.14:11:28.72#ibcon#wrote, iclass 33, count 0 2006.257.14:11:28.72#ibcon#about to read 3, iclass 33, count 0 2006.257.14:11:28.74#ibcon#read 3, iclass 33, count 0 2006.257.14:11:28.74#ibcon#about to read 4, iclass 33, count 0 2006.257.14:11:28.74#ibcon#read 4, iclass 33, count 0 2006.257.14:11:28.74#ibcon#about to read 5, iclass 33, count 0 2006.257.14:11:28.74#ibcon#read 5, iclass 33, count 0 2006.257.14:11:28.74#ibcon#about to read 6, iclass 33, count 0 2006.257.14:11:28.74#ibcon#read 6, iclass 33, count 0 2006.257.14:11:28.74#ibcon#end of sib2, iclass 33, count 0 2006.257.14:11:28.74#ibcon#*mode == 0, iclass 33, count 0 2006.257.14:11:28.74#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.14:11:28.74#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:11:28.74#ibcon#*before write, iclass 33, count 0 2006.257.14:11:28.74#ibcon#enter sib2, iclass 33, count 0 2006.257.14:11:28.74#ibcon#flushed, iclass 33, count 0 2006.257.14:11:28.74#ibcon#about to write, iclass 33, count 0 2006.257.14:11:28.74#ibcon#wrote, iclass 33, count 0 2006.257.14:11:28.74#ibcon#about to read 3, iclass 33, count 0 2006.257.14:11:28.78#ibcon#read 3, iclass 33, count 0 2006.257.14:11:28.78#ibcon#about to read 4, iclass 33, count 0 2006.257.14:11:28.78#ibcon#read 4, iclass 33, count 0 2006.257.14:11:28.78#ibcon#about to read 5, iclass 33, count 0 2006.257.14:11:28.78#ibcon#read 5, iclass 33, count 0 2006.257.14:11:28.78#ibcon#about to read 6, iclass 33, count 0 2006.257.14:11:28.78#ibcon#read 6, iclass 33, count 0 2006.257.14:11:28.78#ibcon#end of sib2, iclass 33, count 0 2006.257.14:11:28.78#ibcon#*after write, iclass 33, count 0 2006.257.14:11:28.78#ibcon#*before return 0, iclass 33, count 0 2006.257.14:11:28.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:28.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:11:28.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.14:11:28.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.14:11:28.78$vck44/vb=2,5 2006.257.14:11:28.78#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.14:11:28.78#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.14:11:28.78#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:28.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:28.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:28.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:28.84#ibcon#enter wrdev, iclass 35, count 2 2006.257.14:11:28.84#ibcon#first serial, iclass 35, count 2 2006.257.14:11:28.84#ibcon#enter sib2, iclass 35, count 2 2006.257.14:11:28.84#ibcon#flushed, iclass 35, count 2 2006.257.14:11:28.84#ibcon#about to write, iclass 35, count 2 2006.257.14:11:28.84#ibcon#wrote, iclass 35, count 2 2006.257.14:11:28.84#ibcon#about to read 3, iclass 35, count 2 2006.257.14:11:28.86#ibcon#read 3, iclass 35, count 2 2006.257.14:11:28.86#ibcon#about to read 4, iclass 35, count 2 2006.257.14:11:28.86#ibcon#read 4, iclass 35, count 2 2006.257.14:11:28.86#ibcon#about to read 5, iclass 35, count 2 2006.257.14:11:28.86#ibcon#read 5, iclass 35, count 2 2006.257.14:11:28.86#ibcon#about to read 6, iclass 35, count 2 2006.257.14:11:28.86#ibcon#read 6, iclass 35, count 2 2006.257.14:11:28.86#ibcon#end of sib2, iclass 35, count 2 2006.257.14:11:28.86#ibcon#*mode == 0, iclass 35, count 2 2006.257.14:11:28.86#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.14:11:28.86#ibcon#[27=AT02-05\r\n] 2006.257.14:11:28.86#ibcon#*before write, iclass 35, count 2 2006.257.14:11:28.86#ibcon#enter sib2, iclass 35, count 2 2006.257.14:11:28.86#ibcon#flushed, iclass 35, count 2 2006.257.14:11:28.86#ibcon#about to write, iclass 35, count 2 2006.257.14:11:28.86#ibcon#wrote, iclass 35, count 2 2006.257.14:11:28.86#ibcon#about to read 3, iclass 35, count 2 2006.257.14:11:28.89#ibcon#read 3, iclass 35, count 2 2006.257.14:11:28.89#ibcon#about to read 4, iclass 35, count 2 2006.257.14:11:28.89#ibcon#read 4, iclass 35, count 2 2006.257.14:11:28.89#ibcon#about to read 5, iclass 35, count 2 2006.257.14:11:28.89#ibcon#read 5, iclass 35, count 2 2006.257.14:11:28.89#ibcon#about to read 6, iclass 35, count 2 2006.257.14:11:28.89#ibcon#read 6, iclass 35, count 2 2006.257.14:11:28.89#ibcon#end of sib2, iclass 35, count 2 2006.257.14:11:28.89#ibcon#*after write, iclass 35, count 2 2006.257.14:11:28.89#ibcon#*before return 0, iclass 35, count 2 2006.257.14:11:28.89#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:28.89#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:11:28.89#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.14:11:28.89#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:28.89#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:29.01#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:29.01#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:29.01#ibcon#enter wrdev, iclass 35, count 0 2006.257.14:11:29.01#ibcon#first serial, iclass 35, count 0 2006.257.14:11:29.01#ibcon#enter sib2, iclass 35, count 0 2006.257.14:11:29.01#ibcon#flushed, iclass 35, count 0 2006.257.14:11:29.01#ibcon#about to write, iclass 35, count 0 2006.257.14:11:29.01#ibcon#wrote, iclass 35, count 0 2006.257.14:11:29.01#ibcon#about to read 3, iclass 35, count 0 2006.257.14:11:29.03#ibcon#read 3, iclass 35, count 0 2006.257.14:11:29.03#ibcon#about to read 4, iclass 35, count 0 2006.257.14:11:29.03#ibcon#read 4, iclass 35, count 0 2006.257.14:11:29.03#ibcon#about to read 5, iclass 35, count 0 2006.257.14:11:29.03#ibcon#read 5, iclass 35, count 0 2006.257.14:11:29.03#ibcon#about to read 6, iclass 35, count 0 2006.257.14:11:29.03#ibcon#read 6, iclass 35, count 0 2006.257.14:11:29.03#ibcon#end of sib2, iclass 35, count 0 2006.257.14:11:29.03#ibcon#*mode == 0, iclass 35, count 0 2006.257.14:11:29.03#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.14:11:29.03#ibcon#[27=USB\r\n] 2006.257.14:11:29.03#ibcon#*before write, iclass 35, count 0 2006.257.14:11:29.03#ibcon#enter sib2, iclass 35, count 0 2006.257.14:11:29.03#ibcon#flushed, iclass 35, count 0 2006.257.14:11:29.03#ibcon#about to write, iclass 35, count 0 2006.257.14:11:29.03#ibcon#wrote, iclass 35, count 0 2006.257.14:11:29.03#ibcon#about to read 3, iclass 35, count 0 2006.257.14:11:29.06#ibcon#read 3, iclass 35, count 0 2006.257.14:11:29.06#ibcon#about to read 4, iclass 35, count 0 2006.257.14:11:29.06#ibcon#read 4, iclass 35, count 0 2006.257.14:11:29.06#ibcon#about to read 5, iclass 35, count 0 2006.257.14:11:29.06#ibcon#read 5, iclass 35, count 0 2006.257.14:11:29.06#ibcon#about to read 6, iclass 35, count 0 2006.257.14:11:29.06#ibcon#read 6, iclass 35, count 0 2006.257.14:11:29.06#ibcon#end of sib2, iclass 35, count 0 2006.257.14:11:29.06#ibcon#*after write, iclass 35, count 0 2006.257.14:11:29.06#ibcon#*before return 0, iclass 35, count 0 2006.257.14:11:29.06#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:29.06#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:11:29.06#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.14:11:29.06#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.14:11:29.06$vck44/vblo=3,649.99 2006.257.14:11:29.06#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.14:11:29.06#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.14:11:29.06#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:29.06#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:29.06#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:29.06#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:29.06#ibcon#enter wrdev, iclass 37, count 0 2006.257.14:11:29.06#ibcon#first serial, iclass 37, count 0 2006.257.14:11:29.06#ibcon#enter sib2, iclass 37, count 0 2006.257.14:11:29.06#ibcon#flushed, iclass 37, count 0 2006.257.14:11:29.06#ibcon#about to write, iclass 37, count 0 2006.257.14:11:29.06#ibcon#wrote, iclass 37, count 0 2006.257.14:11:29.06#ibcon#about to read 3, iclass 37, count 0 2006.257.14:11:29.08#ibcon#read 3, iclass 37, count 0 2006.257.14:11:29.08#ibcon#about to read 4, iclass 37, count 0 2006.257.14:11:29.08#ibcon#read 4, iclass 37, count 0 2006.257.14:11:29.08#ibcon#about to read 5, iclass 37, count 0 2006.257.14:11:29.08#ibcon#read 5, iclass 37, count 0 2006.257.14:11:29.08#ibcon#about to read 6, iclass 37, count 0 2006.257.14:11:29.08#ibcon#read 6, iclass 37, count 0 2006.257.14:11:29.08#ibcon#end of sib2, iclass 37, count 0 2006.257.14:11:29.08#ibcon#*mode == 0, iclass 37, count 0 2006.257.14:11:29.08#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.14:11:29.08#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:11:29.08#ibcon#*before write, iclass 37, count 0 2006.257.14:11:29.08#ibcon#enter sib2, iclass 37, count 0 2006.257.14:11:29.08#ibcon#flushed, iclass 37, count 0 2006.257.14:11:29.08#ibcon#about to write, iclass 37, count 0 2006.257.14:11:29.08#ibcon#wrote, iclass 37, count 0 2006.257.14:11:29.08#ibcon#about to read 3, iclass 37, count 0 2006.257.14:11:29.12#ibcon#read 3, iclass 37, count 0 2006.257.14:11:29.12#ibcon#about to read 4, iclass 37, count 0 2006.257.14:11:29.12#ibcon#read 4, iclass 37, count 0 2006.257.14:11:29.12#ibcon#about to read 5, iclass 37, count 0 2006.257.14:11:29.12#ibcon#read 5, iclass 37, count 0 2006.257.14:11:29.12#ibcon#about to read 6, iclass 37, count 0 2006.257.14:11:29.12#ibcon#read 6, iclass 37, count 0 2006.257.14:11:29.12#ibcon#end of sib2, iclass 37, count 0 2006.257.14:11:29.12#ibcon#*after write, iclass 37, count 0 2006.257.14:11:29.12#ibcon#*before return 0, iclass 37, count 0 2006.257.14:11:29.12#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:29.12#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:11:29.12#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.14:11:29.12#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.14:11:29.12$vck44/vb=3,4 2006.257.14:11:29.12#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.14:11:29.12#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.14:11:29.12#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:29.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:29.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:29.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:29.18#ibcon#enter wrdev, iclass 39, count 2 2006.257.14:11:29.18#ibcon#first serial, iclass 39, count 2 2006.257.14:11:29.18#ibcon#enter sib2, iclass 39, count 2 2006.257.14:11:29.18#ibcon#flushed, iclass 39, count 2 2006.257.14:11:29.18#ibcon#about to write, iclass 39, count 2 2006.257.14:11:29.18#ibcon#wrote, iclass 39, count 2 2006.257.14:11:29.18#ibcon#about to read 3, iclass 39, count 2 2006.257.14:11:29.20#ibcon#read 3, iclass 39, count 2 2006.257.14:11:29.20#ibcon#about to read 4, iclass 39, count 2 2006.257.14:11:29.20#ibcon#read 4, iclass 39, count 2 2006.257.14:11:29.20#ibcon#about to read 5, iclass 39, count 2 2006.257.14:11:29.20#ibcon#read 5, iclass 39, count 2 2006.257.14:11:29.20#ibcon#about to read 6, iclass 39, count 2 2006.257.14:11:29.20#ibcon#read 6, iclass 39, count 2 2006.257.14:11:29.20#ibcon#end of sib2, iclass 39, count 2 2006.257.14:11:29.20#ibcon#*mode == 0, iclass 39, count 2 2006.257.14:11:29.20#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.14:11:29.20#ibcon#[27=AT03-04\r\n] 2006.257.14:11:29.20#ibcon#*before write, iclass 39, count 2 2006.257.14:11:29.20#ibcon#enter sib2, iclass 39, count 2 2006.257.14:11:29.20#ibcon#flushed, iclass 39, count 2 2006.257.14:11:29.20#ibcon#about to write, iclass 39, count 2 2006.257.14:11:29.20#ibcon#wrote, iclass 39, count 2 2006.257.14:11:29.20#ibcon#about to read 3, iclass 39, count 2 2006.257.14:11:29.23#ibcon#read 3, iclass 39, count 2 2006.257.14:11:31.59#abcon#<5=/14 1.7 3.3 17.48 971014.0\r\n> 2006.257.14:11:32.15#ibcon#about to read 4, iclass 39, count 2 2006.257.14:11:32.15#ibcon#read 4, iclass 39, count 2 2006.257.14:11:32.16#ibcon#about to read 5, iclass 39, count 2 2006.257.14:11:32.16#ibcon#read 5, iclass 39, count 2 2006.257.14:11:32.16#ibcon#about to read 6, iclass 39, count 2 2006.257.14:11:32.16#ibcon#read 6, iclass 39, count 2 2006.257.14:11:32.16#ibcon#end of sib2, iclass 39, count 2 2006.257.14:11:32.16#ibcon#*after write, iclass 39, count 2 2006.257.14:11:32.16#ibcon#*before return 0, iclass 39, count 2 2006.257.14:11:32.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:32.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:11:32.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.14:11:32.16#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:32.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:32.17#abcon#{5=INTERFACE CLEAR} 2006.257.14:11:32.23#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:11:32.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:32.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:32.27#ibcon#enter wrdev, iclass 39, count 0 2006.257.14:11:32.27#ibcon#first serial, iclass 39, count 0 2006.257.14:11:32.27#ibcon#enter sib2, iclass 39, count 0 2006.257.14:11:32.27#ibcon#flushed, iclass 39, count 0 2006.257.14:11:32.27#ibcon#about to write, iclass 39, count 0 2006.257.14:11:32.27#ibcon#wrote, iclass 39, count 0 2006.257.14:11:32.27#ibcon#about to read 3, iclass 39, count 0 2006.257.14:11:32.29#ibcon#read 3, iclass 39, count 0 2006.257.14:11:32.29#ibcon#about to read 4, iclass 39, count 0 2006.257.14:11:32.29#ibcon#read 4, iclass 39, count 0 2006.257.14:11:32.29#ibcon#about to read 5, iclass 39, count 0 2006.257.14:11:32.29#ibcon#read 5, iclass 39, count 0 2006.257.14:11:32.29#ibcon#about to read 6, iclass 39, count 0 2006.257.14:11:32.29#ibcon#read 6, iclass 39, count 0 2006.257.14:11:32.29#ibcon#end of sib2, iclass 39, count 0 2006.257.14:11:32.29#ibcon#*mode == 0, iclass 39, count 0 2006.257.14:11:32.29#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.14:11:32.29#ibcon#[27=USB\r\n] 2006.257.14:11:32.29#ibcon#*before write, iclass 39, count 0 2006.257.14:11:32.29#ibcon#enter sib2, iclass 39, count 0 2006.257.14:11:32.29#ibcon#flushed, iclass 39, count 0 2006.257.14:11:32.29#ibcon#about to write, iclass 39, count 0 2006.257.14:11:32.29#ibcon#wrote, iclass 39, count 0 2006.257.14:11:32.29#ibcon#about to read 3, iclass 39, count 0 2006.257.14:11:32.32#ibcon#read 3, iclass 39, count 0 2006.257.14:11:32.32#ibcon#about to read 4, iclass 39, count 0 2006.257.14:11:32.32#ibcon#read 4, iclass 39, count 0 2006.257.14:11:32.32#ibcon#about to read 5, iclass 39, count 0 2006.257.14:11:32.32#ibcon#read 5, iclass 39, count 0 2006.257.14:11:32.32#ibcon#about to read 6, iclass 39, count 0 2006.257.14:11:32.32#ibcon#read 6, iclass 39, count 0 2006.257.14:11:32.32#ibcon#end of sib2, iclass 39, count 0 2006.257.14:11:32.32#ibcon#*after write, iclass 39, count 0 2006.257.14:11:32.32#ibcon#*before return 0, iclass 39, count 0 2006.257.14:11:32.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:32.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:11:32.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.14:11:32.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.14:11:32.32$vck44/vblo=4,679.99 2006.257.14:11:32.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.14:11:32.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.14:11:32.32#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:32.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:32.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:32.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:32.32#ibcon#enter wrdev, iclass 7, count 0 2006.257.14:11:32.32#ibcon#first serial, iclass 7, count 0 2006.257.14:11:32.32#ibcon#enter sib2, iclass 7, count 0 2006.257.14:11:32.32#ibcon#flushed, iclass 7, count 0 2006.257.14:11:32.32#ibcon#about to write, iclass 7, count 0 2006.257.14:11:32.32#ibcon#wrote, iclass 7, count 0 2006.257.14:11:32.32#ibcon#about to read 3, iclass 7, count 0 2006.257.14:11:32.34#ibcon#read 3, iclass 7, count 0 2006.257.14:11:32.34#ibcon#about to read 4, iclass 7, count 0 2006.257.14:11:32.34#ibcon#read 4, iclass 7, count 0 2006.257.14:11:32.34#ibcon#about to read 5, iclass 7, count 0 2006.257.14:11:32.34#ibcon#read 5, iclass 7, count 0 2006.257.14:11:32.34#ibcon#about to read 6, iclass 7, count 0 2006.257.14:11:32.34#ibcon#read 6, iclass 7, count 0 2006.257.14:11:32.34#ibcon#end of sib2, iclass 7, count 0 2006.257.14:11:32.34#ibcon#*mode == 0, iclass 7, count 0 2006.257.14:11:32.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.14:11:32.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:11:32.34#ibcon#*before write, iclass 7, count 0 2006.257.14:11:32.34#ibcon#enter sib2, iclass 7, count 0 2006.257.14:11:32.34#ibcon#flushed, iclass 7, count 0 2006.257.14:11:32.34#ibcon#about to write, iclass 7, count 0 2006.257.14:11:32.34#ibcon#wrote, iclass 7, count 0 2006.257.14:11:32.34#ibcon#about to read 3, iclass 7, count 0 2006.257.14:11:32.38#ibcon#read 3, iclass 7, count 0 2006.257.14:11:32.38#ibcon#about to read 4, iclass 7, count 0 2006.257.14:11:32.38#ibcon#read 4, iclass 7, count 0 2006.257.14:11:32.38#ibcon#about to read 5, iclass 7, count 0 2006.257.14:11:32.38#ibcon#read 5, iclass 7, count 0 2006.257.14:11:32.38#ibcon#about to read 6, iclass 7, count 0 2006.257.14:11:32.38#ibcon#read 6, iclass 7, count 0 2006.257.14:11:32.38#ibcon#end of sib2, iclass 7, count 0 2006.257.14:11:32.38#ibcon#*after write, iclass 7, count 0 2006.257.14:11:32.38#ibcon#*before return 0, iclass 7, count 0 2006.257.14:11:32.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:32.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:11:32.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.14:11:32.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.14:11:32.38$vck44/vb=4,5 2006.257.14:11:32.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.14:11:32.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.14:11:32.38#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:32.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:32.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:32.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:32.44#ibcon#enter wrdev, iclass 11, count 2 2006.257.14:11:32.44#ibcon#first serial, iclass 11, count 2 2006.257.14:11:32.44#ibcon#enter sib2, iclass 11, count 2 2006.257.14:11:32.44#ibcon#flushed, iclass 11, count 2 2006.257.14:11:32.44#ibcon#about to write, iclass 11, count 2 2006.257.14:11:32.44#ibcon#wrote, iclass 11, count 2 2006.257.14:11:32.44#ibcon#about to read 3, iclass 11, count 2 2006.257.14:11:32.46#ibcon#read 3, iclass 11, count 2 2006.257.14:11:32.46#ibcon#about to read 4, iclass 11, count 2 2006.257.14:11:32.46#ibcon#read 4, iclass 11, count 2 2006.257.14:11:32.46#ibcon#about to read 5, iclass 11, count 2 2006.257.14:11:32.46#ibcon#read 5, iclass 11, count 2 2006.257.14:11:32.46#ibcon#about to read 6, iclass 11, count 2 2006.257.14:11:32.46#ibcon#read 6, iclass 11, count 2 2006.257.14:11:32.46#ibcon#end of sib2, iclass 11, count 2 2006.257.14:11:32.46#ibcon#*mode == 0, iclass 11, count 2 2006.257.14:11:32.46#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.14:11:32.46#ibcon#[27=AT04-05\r\n] 2006.257.14:11:32.46#ibcon#*before write, iclass 11, count 2 2006.257.14:11:32.46#ibcon#enter sib2, iclass 11, count 2 2006.257.14:11:32.46#ibcon#flushed, iclass 11, count 2 2006.257.14:11:32.46#ibcon#about to write, iclass 11, count 2 2006.257.14:11:32.46#ibcon#wrote, iclass 11, count 2 2006.257.14:11:32.46#ibcon#about to read 3, iclass 11, count 2 2006.257.14:11:32.49#ibcon#read 3, iclass 11, count 2 2006.257.14:11:32.49#ibcon#about to read 4, iclass 11, count 2 2006.257.14:11:32.49#ibcon#read 4, iclass 11, count 2 2006.257.14:11:32.49#ibcon#about to read 5, iclass 11, count 2 2006.257.14:11:32.49#ibcon#read 5, iclass 11, count 2 2006.257.14:11:32.49#ibcon#about to read 6, iclass 11, count 2 2006.257.14:11:32.49#ibcon#read 6, iclass 11, count 2 2006.257.14:11:32.49#ibcon#end of sib2, iclass 11, count 2 2006.257.14:11:32.49#ibcon#*after write, iclass 11, count 2 2006.257.14:11:32.49#ibcon#*before return 0, iclass 11, count 2 2006.257.14:11:32.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:32.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:11:32.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.14:11:32.49#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:32.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:32.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:32.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:32.61#ibcon#enter wrdev, iclass 11, count 0 2006.257.14:11:32.61#ibcon#first serial, iclass 11, count 0 2006.257.14:11:32.61#ibcon#enter sib2, iclass 11, count 0 2006.257.14:11:32.61#ibcon#flushed, iclass 11, count 0 2006.257.14:11:32.61#ibcon#about to write, iclass 11, count 0 2006.257.14:11:32.61#ibcon#wrote, iclass 11, count 0 2006.257.14:11:32.61#ibcon#about to read 3, iclass 11, count 0 2006.257.14:11:32.63#ibcon#read 3, iclass 11, count 0 2006.257.14:11:32.63#ibcon#about to read 4, iclass 11, count 0 2006.257.14:11:32.63#ibcon#read 4, iclass 11, count 0 2006.257.14:11:32.63#ibcon#about to read 5, iclass 11, count 0 2006.257.14:11:32.63#ibcon#read 5, iclass 11, count 0 2006.257.14:11:32.63#ibcon#about to read 6, iclass 11, count 0 2006.257.14:11:32.63#ibcon#read 6, iclass 11, count 0 2006.257.14:11:32.63#ibcon#end of sib2, iclass 11, count 0 2006.257.14:11:32.63#ibcon#*mode == 0, iclass 11, count 0 2006.257.14:11:32.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.14:11:32.63#ibcon#[27=USB\r\n] 2006.257.14:11:32.63#ibcon#*before write, iclass 11, count 0 2006.257.14:11:32.63#ibcon#enter sib2, iclass 11, count 0 2006.257.14:11:32.63#ibcon#flushed, iclass 11, count 0 2006.257.14:11:32.63#ibcon#about to write, iclass 11, count 0 2006.257.14:11:32.63#ibcon#wrote, iclass 11, count 0 2006.257.14:11:32.63#ibcon#about to read 3, iclass 11, count 0 2006.257.14:11:32.66#ibcon#read 3, iclass 11, count 0 2006.257.14:11:32.66#ibcon#about to read 4, iclass 11, count 0 2006.257.14:11:32.66#ibcon#read 4, iclass 11, count 0 2006.257.14:11:32.66#ibcon#about to read 5, iclass 11, count 0 2006.257.14:11:32.66#ibcon#read 5, iclass 11, count 0 2006.257.14:11:32.66#ibcon#about to read 6, iclass 11, count 0 2006.257.14:11:32.66#ibcon#read 6, iclass 11, count 0 2006.257.14:11:32.66#ibcon#end of sib2, iclass 11, count 0 2006.257.14:11:32.66#ibcon#*after write, iclass 11, count 0 2006.257.14:11:32.66#ibcon#*before return 0, iclass 11, count 0 2006.257.14:11:32.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:32.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:11:32.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.14:11:32.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.14:11:32.66$vck44/vblo=5,709.99 2006.257.14:11:32.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.14:11:32.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.14:11:32.66#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:32.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:32.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:32.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:32.66#ibcon#enter wrdev, iclass 13, count 0 2006.257.14:11:32.66#ibcon#first serial, iclass 13, count 0 2006.257.14:11:32.66#ibcon#enter sib2, iclass 13, count 0 2006.257.14:11:32.66#ibcon#flushed, iclass 13, count 0 2006.257.14:11:32.66#ibcon#about to write, iclass 13, count 0 2006.257.14:11:32.66#ibcon#wrote, iclass 13, count 0 2006.257.14:11:32.66#ibcon#about to read 3, iclass 13, count 0 2006.257.14:11:32.68#ibcon#read 3, iclass 13, count 0 2006.257.14:11:32.68#ibcon#about to read 4, iclass 13, count 0 2006.257.14:11:32.68#ibcon#read 4, iclass 13, count 0 2006.257.14:11:32.68#ibcon#about to read 5, iclass 13, count 0 2006.257.14:11:32.68#ibcon#read 5, iclass 13, count 0 2006.257.14:11:32.68#ibcon#about to read 6, iclass 13, count 0 2006.257.14:11:32.68#ibcon#read 6, iclass 13, count 0 2006.257.14:11:32.68#ibcon#end of sib2, iclass 13, count 0 2006.257.14:11:32.68#ibcon#*mode == 0, iclass 13, count 0 2006.257.14:11:32.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.14:11:32.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:11:32.68#ibcon#*before write, iclass 13, count 0 2006.257.14:11:32.68#ibcon#enter sib2, iclass 13, count 0 2006.257.14:11:32.68#ibcon#flushed, iclass 13, count 0 2006.257.14:11:32.68#ibcon#about to write, iclass 13, count 0 2006.257.14:11:32.68#ibcon#wrote, iclass 13, count 0 2006.257.14:11:32.68#ibcon#about to read 3, iclass 13, count 0 2006.257.14:11:32.72#ibcon#read 3, iclass 13, count 0 2006.257.14:11:32.72#ibcon#about to read 4, iclass 13, count 0 2006.257.14:11:32.72#ibcon#read 4, iclass 13, count 0 2006.257.14:11:32.72#ibcon#about to read 5, iclass 13, count 0 2006.257.14:11:32.72#ibcon#read 5, iclass 13, count 0 2006.257.14:11:32.72#ibcon#about to read 6, iclass 13, count 0 2006.257.14:11:32.72#ibcon#read 6, iclass 13, count 0 2006.257.14:11:32.72#ibcon#end of sib2, iclass 13, count 0 2006.257.14:11:32.72#ibcon#*after write, iclass 13, count 0 2006.257.14:11:32.72#ibcon#*before return 0, iclass 13, count 0 2006.257.14:11:32.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:32.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:11:32.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.14:11:32.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.14:11:32.72$vck44/vb=5,4 2006.257.14:11:32.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.14:11:32.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.14:11:32.72#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:32.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:32.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:32.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:32.78#ibcon#enter wrdev, iclass 15, count 2 2006.257.14:11:32.78#ibcon#first serial, iclass 15, count 2 2006.257.14:11:32.78#ibcon#enter sib2, iclass 15, count 2 2006.257.14:11:32.78#ibcon#flushed, iclass 15, count 2 2006.257.14:11:32.78#ibcon#about to write, iclass 15, count 2 2006.257.14:11:32.78#ibcon#wrote, iclass 15, count 2 2006.257.14:11:32.78#ibcon#about to read 3, iclass 15, count 2 2006.257.14:11:32.80#ibcon#read 3, iclass 15, count 2 2006.257.14:11:32.80#ibcon#about to read 4, iclass 15, count 2 2006.257.14:11:32.80#ibcon#read 4, iclass 15, count 2 2006.257.14:11:32.80#ibcon#about to read 5, iclass 15, count 2 2006.257.14:11:32.80#ibcon#read 5, iclass 15, count 2 2006.257.14:11:32.80#ibcon#about to read 6, iclass 15, count 2 2006.257.14:11:32.80#ibcon#read 6, iclass 15, count 2 2006.257.14:11:32.80#ibcon#end of sib2, iclass 15, count 2 2006.257.14:11:32.80#ibcon#*mode == 0, iclass 15, count 2 2006.257.14:11:32.80#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.14:11:32.80#ibcon#[27=AT05-04\r\n] 2006.257.14:11:32.80#ibcon#*before write, iclass 15, count 2 2006.257.14:11:32.80#ibcon#enter sib2, iclass 15, count 2 2006.257.14:11:32.80#ibcon#flushed, iclass 15, count 2 2006.257.14:11:32.80#ibcon#about to write, iclass 15, count 2 2006.257.14:11:32.80#ibcon#wrote, iclass 15, count 2 2006.257.14:11:32.80#ibcon#about to read 3, iclass 15, count 2 2006.257.14:11:32.83#ibcon#read 3, iclass 15, count 2 2006.257.14:11:32.83#ibcon#about to read 4, iclass 15, count 2 2006.257.14:11:32.83#ibcon#read 4, iclass 15, count 2 2006.257.14:11:32.83#ibcon#about to read 5, iclass 15, count 2 2006.257.14:11:32.83#ibcon#read 5, iclass 15, count 2 2006.257.14:11:32.83#ibcon#about to read 6, iclass 15, count 2 2006.257.14:11:32.83#ibcon#read 6, iclass 15, count 2 2006.257.14:11:32.83#ibcon#end of sib2, iclass 15, count 2 2006.257.14:11:32.83#ibcon#*after write, iclass 15, count 2 2006.257.14:11:32.83#ibcon#*before return 0, iclass 15, count 2 2006.257.14:11:32.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:32.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:11:32.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.14:11:32.83#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:32.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:32.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:32.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:32.95#ibcon#enter wrdev, iclass 15, count 0 2006.257.14:11:32.95#ibcon#first serial, iclass 15, count 0 2006.257.14:11:32.95#ibcon#enter sib2, iclass 15, count 0 2006.257.14:11:32.95#ibcon#flushed, iclass 15, count 0 2006.257.14:11:32.95#ibcon#about to write, iclass 15, count 0 2006.257.14:11:32.95#ibcon#wrote, iclass 15, count 0 2006.257.14:11:32.95#ibcon#about to read 3, iclass 15, count 0 2006.257.14:11:32.97#ibcon#read 3, iclass 15, count 0 2006.257.14:11:32.97#ibcon#about to read 4, iclass 15, count 0 2006.257.14:11:32.97#ibcon#read 4, iclass 15, count 0 2006.257.14:11:32.97#ibcon#about to read 5, iclass 15, count 0 2006.257.14:11:32.97#ibcon#read 5, iclass 15, count 0 2006.257.14:11:32.97#ibcon#about to read 6, iclass 15, count 0 2006.257.14:11:32.97#ibcon#read 6, iclass 15, count 0 2006.257.14:11:32.97#ibcon#end of sib2, iclass 15, count 0 2006.257.14:11:32.97#ibcon#*mode == 0, iclass 15, count 0 2006.257.14:11:32.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.14:11:32.97#ibcon#[27=USB\r\n] 2006.257.14:11:32.97#ibcon#*before write, iclass 15, count 0 2006.257.14:11:32.97#ibcon#enter sib2, iclass 15, count 0 2006.257.14:11:32.97#ibcon#flushed, iclass 15, count 0 2006.257.14:11:32.97#ibcon#about to write, iclass 15, count 0 2006.257.14:11:32.97#ibcon#wrote, iclass 15, count 0 2006.257.14:11:32.97#ibcon#about to read 3, iclass 15, count 0 2006.257.14:11:33.00#ibcon#read 3, iclass 15, count 0 2006.257.14:11:33.00#ibcon#about to read 4, iclass 15, count 0 2006.257.14:11:33.00#ibcon#read 4, iclass 15, count 0 2006.257.14:11:33.00#ibcon#about to read 5, iclass 15, count 0 2006.257.14:11:33.00#ibcon#read 5, iclass 15, count 0 2006.257.14:11:33.00#ibcon#about to read 6, iclass 15, count 0 2006.257.14:11:33.00#ibcon#read 6, iclass 15, count 0 2006.257.14:11:33.00#ibcon#end of sib2, iclass 15, count 0 2006.257.14:11:33.00#ibcon#*after write, iclass 15, count 0 2006.257.14:11:33.00#ibcon#*before return 0, iclass 15, count 0 2006.257.14:11:33.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:33.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:11:33.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.14:11:33.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.14:11:33.00$vck44/vblo=6,719.99 2006.257.14:11:33.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.14:11:33.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.14:11:33.00#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:33.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:33.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:33.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:33.00#ibcon#enter wrdev, iclass 17, count 0 2006.257.14:11:33.00#ibcon#first serial, iclass 17, count 0 2006.257.14:11:33.00#ibcon#enter sib2, iclass 17, count 0 2006.257.14:11:33.00#ibcon#flushed, iclass 17, count 0 2006.257.14:11:33.00#ibcon#about to write, iclass 17, count 0 2006.257.14:11:33.00#ibcon#wrote, iclass 17, count 0 2006.257.14:11:33.00#ibcon#about to read 3, iclass 17, count 0 2006.257.14:11:33.02#ibcon#read 3, iclass 17, count 0 2006.257.14:11:33.02#ibcon#about to read 4, iclass 17, count 0 2006.257.14:11:33.02#ibcon#read 4, iclass 17, count 0 2006.257.14:11:33.02#ibcon#about to read 5, iclass 17, count 0 2006.257.14:11:33.02#ibcon#read 5, iclass 17, count 0 2006.257.14:11:33.02#ibcon#about to read 6, iclass 17, count 0 2006.257.14:11:33.02#ibcon#read 6, iclass 17, count 0 2006.257.14:11:33.02#ibcon#end of sib2, iclass 17, count 0 2006.257.14:11:33.02#ibcon#*mode == 0, iclass 17, count 0 2006.257.14:11:33.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.14:11:33.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:11:33.02#ibcon#*before write, iclass 17, count 0 2006.257.14:11:33.02#ibcon#enter sib2, iclass 17, count 0 2006.257.14:11:33.02#ibcon#flushed, iclass 17, count 0 2006.257.14:11:33.02#ibcon#about to write, iclass 17, count 0 2006.257.14:11:33.02#ibcon#wrote, iclass 17, count 0 2006.257.14:11:33.02#ibcon#about to read 3, iclass 17, count 0 2006.257.14:11:33.06#ibcon#read 3, iclass 17, count 0 2006.257.14:11:33.06#ibcon#about to read 4, iclass 17, count 0 2006.257.14:11:33.06#ibcon#read 4, iclass 17, count 0 2006.257.14:11:33.06#ibcon#about to read 5, iclass 17, count 0 2006.257.14:11:33.06#ibcon#read 5, iclass 17, count 0 2006.257.14:11:33.06#ibcon#about to read 6, iclass 17, count 0 2006.257.14:11:33.06#ibcon#read 6, iclass 17, count 0 2006.257.14:11:33.06#ibcon#end of sib2, iclass 17, count 0 2006.257.14:11:33.06#ibcon#*after write, iclass 17, count 0 2006.257.14:11:33.06#ibcon#*before return 0, iclass 17, count 0 2006.257.14:11:33.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:33.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:11:33.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.14:11:33.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.14:11:33.06$vck44/vb=6,4 2006.257.14:11:33.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.14:11:33.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.14:11:33.06#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:33.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:33.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:33.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:33.12#ibcon#enter wrdev, iclass 19, count 2 2006.257.14:11:33.12#ibcon#first serial, iclass 19, count 2 2006.257.14:11:33.12#ibcon#enter sib2, iclass 19, count 2 2006.257.14:11:33.12#ibcon#flushed, iclass 19, count 2 2006.257.14:11:33.12#ibcon#about to write, iclass 19, count 2 2006.257.14:11:33.12#ibcon#wrote, iclass 19, count 2 2006.257.14:11:33.12#ibcon#about to read 3, iclass 19, count 2 2006.257.14:11:33.14#ibcon#read 3, iclass 19, count 2 2006.257.14:11:33.14#ibcon#about to read 4, iclass 19, count 2 2006.257.14:11:33.14#ibcon#read 4, iclass 19, count 2 2006.257.14:11:33.14#ibcon#about to read 5, iclass 19, count 2 2006.257.14:11:33.14#ibcon#read 5, iclass 19, count 2 2006.257.14:11:33.14#ibcon#about to read 6, iclass 19, count 2 2006.257.14:11:33.14#ibcon#read 6, iclass 19, count 2 2006.257.14:11:33.14#ibcon#end of sib2, iclass 19, count 2 2006.257.14:11:33.14#ibcon#*mode == 0, iclass 19, count 2 2006.257.14:11:33.14#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.14:11:33.14#ibcon#[27=AT06-04\r\n] 2006.257.14:11:33.14#ibcon#*before write, iclass 19, count 2 2006.257.14:11:33.14#ibcon#enter sib2, iclass 19, count 2 2006.257.14:11:33.14#ibcon#flushed, iclass 19, count 2 2006.257.14:11:33.14#ibcon#about to write, iclass 19, count 2 2006.257.14:11:33.14#ibcon#wrote, iclass 19, count 2 2006.257.14:11:33.14#ibcon#about to read 3, iclass 19, count 2 2006.257.14:11:33.17#ibcon#read 3, iclass 19, count 2 2006.257.14:11:33.17#ibcon#about to read 4, iclass 19, count 2 2006.257.14:11:33.17#ibcon#read 4, iclass 19, count 2 2006.257.14:11:33.17#ibcon#about to read 5, iclass 19, count 2 2006.257.14:11:33.17#ibcon#read 5, iclass 19, count 2 2006.257.14:11:33.17#ibcon#about to read 6, iclass 19, count 2 2006.257.14:11:33.17#ibcon#read 6, iclass 19, count 2 2006.257.14:11:33.17#ibcon#end of sib2, iclass 19, count 2 2006.257.14:11:33.17#ibcon#*after write, iclass 19, count 2 2006.257.14:11:33.17#ibcon#*before return 0, iclass 19, count 2 2006.257.14:11:33.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:33.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:11:33.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.14:11:33.17#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:33.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:33.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:33.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:33.29#ibcon#enter wrdev, iclass 19, count 0 2006.257.14:11:33.29#ibcon#first serial, iclass 19, count 0 2006.257.14:11:33.29#ibcon#enter sib2, iclass 19, count 0 2006.257.14:11:33.29#ibcon#flushed, iclass 19, count 0 2006.257.14:11:33.29#ibcon#about to write, iclass 19, count 0 2006.257.14:11:33.29#ibcon#wrote, iclass 19, count 0 2006.257.14:11:33.29#ibcon#about to read 3, iclass 19, count 0 2006.257.14:11:33.31#ibcon#read 3, iclass 19, count 0 2006.257.14:11:33.31#ibcon#about to read 4, iclass 19, count 0 2006.257.14:11:33.31#ibcon#read 4, iclass 19, count 0 2006.257.14:11:33.31#ibcon#about to read 5, iclass 19, count 0 2006.257.14:11:33.31#ibcon#read 5, iclass 19, count 0 2006.257.14:11:33.31#ibcon#about to read 6, iclass 19, count 0 2006.257.14:11:33.31#ibcon#read 6, iclass 19, count 0 2006.257.14:11:33.31#ibcon#end of sib2, iclass 19, count 0 2006.257.14:11:33.31#ibcon#*mode == 0, iclass 19, count 0 2006.257.14:11:33.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.14:11:33.31#ibcon#[27=USB\r\n] 2006.257.14:11:33.31#ibcon#*before write, iclass 19, count 0 2006.257.14:11:33.31#ibcon#enter sib2, iclass 19, count 0 2006.257.14:11:33.31#ibcon#flushed, iclass 19, count 0 2006.257.14:11:33.31#ibcon#about to write, iclass 19, count 0 2006.257.14:11:33.31#ibcon#wrote, iclass 19, count 0 2006.257.14:11:33.31#ibcon#about to read 3, iclass 19, count 0 2006.257.14:11:33.34#ibcon#read 3, iclass 19, count 0 2006.257.14:11:33.34#ibcon#about to read 4, iclass 19, count 0 2006.257.14:11:33.34#ibcon#read 4, iclass 19, count 0 2006.257.14:11:33.34#ibcon#about to read 5, iclass 19, count 0 2006.257.14:11:33.34#ibcon#read 5, iclass 19, count 0 2006.257.14:11:33.34#ibcon#about to read 6, iclass 19, count 0 2006.257.14:11:33.34#ibcon#read 6, iclass 19, count 0 2006.257.14:11:33.34#ibcon#end of sib2, iclass 19, count 0 2006.257.14:11:33.34#ibcon#*after write, iclass 19, count 0 2006.257.14:11:33.34#ibcon#*before return 0, iclass 19, count 0 2006.257.14:11:33.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:33.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:11:33.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.14:11:33.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.14:11:33.34$vck44/vblo=7,734.99 2006.257.14:11:33.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.14:11:33.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.14:11:33.34#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:33.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:33.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:33.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:33.34#ibcon#enter wrdev, iclass 21, count 0 2006.257.14:11:33.34#ibcon#first serial, iclass 21, count 0 2006.257.14:11:33.34#ibcon#enter sib2, iclass 21, count 0 2006.257.14:11:34.12#ibcon#flushed, iclass 21, count 0 2006.257.14:11:34.12#ibcon#about to write, iclass 21, count 0 2006.257.14:11:34.12#ibcon#wrote, iclass 21, count 0 2006.257.14:11:34.12#ibcon#about to read 3, iclass 21, count 0 2006.257.14:11:34.13#ibcon#read 3, iclass 21, count 0 2006.257.14:11:34.13#ibcon#about to read 4, iclass 21, count 0 2006.257.14:11:34.13#ibcon#read 4, iclass 21, count 0 2006.257.14:11:34.13#ibcon#about to read 5, iclass 21, count 0 2006.257.14:11:34.13#ibcon#read 5, iclass 21, count 0 2006.257.14:11:34.13#ibcon#about to read 6, iclass 21, count 0 2006.257.14:11:34.13#ibcon#read 6, iclass 21, count 0 2006.257.14:11:34.13#ibcon#end of sib2, iclass 21, count 0 2006.257.14:11:34.13#ibcon#*mode == 0, iclass 21, count 0 2006.257.14:11:34.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.14:11:34.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:11:34.13#ibcon#*before write, iclass 21, count 0 2006.257.14:11:34.13#ibcon#enter sib2, iclass 21, count 0 2006.257.14:11:34.13#ibcon#flushed, iclass 21, count 0 2006.257.14:11:34.13#ibcon#about to write, iclass 21, count 0 2006.257.14:11:34.13#ibcon#wrote, iclass 21, count 0 2006.257.14:11:34.13#ibcon#about to read 3, iclass 21, count 0 2006.257.14:11:34.17#ibcon#read 3, iclass 21, count 0 2006.257.14:11:34.17#ibcon#about to read 4, iclass 21, count 0 2006.257.14:11:34.17#ibcon#read 4, iclass 21, count 0 2006.257.14:11:34.17#ibcon#about to read 5, iclass 21, count 0 2006.257.14:11:34.17#ibcon#read 5, iclass 21, count 0 2006.257.14:11:34.17#ibcon#about to read 6, iclass 21, count 0 2006.257.14:11:34.17#ibcon#read 6, iclass 21, count 0 2006.257.14:11:34.17#ibcon#end of sib2, iclass 21, count 0 2006.257.14:11:34.17#ibcon#*after write, iclass 21, count 0 2006.257.14:11:34.17#ibcon#*before return 0, iclass 21, count 0 2006.257.14:11:34.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:34.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:11:34.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.14:11:34.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.14:11:34.17$vck44/vb=7,4 2006.257.14:11:34.17#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.14:11:34.17#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.14:11:34.17#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:34.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:34.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:34.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:34.17#ibcon#enter wrdev, iclass 23, count 2 2006.257.14:11:34.17#ibcon#first serial, iclass 23, count 2 2006.257.14:11:34.17#ibcon#enter sib2, iclass 23, count 2 2006.257.14:11:34.17#ibcon#flushed, iclass 23, count 2 2006.257.14:11:34.17#ibcon#about to write, iclass 23, count 2 2006.257.14:11:34.17#ibcon#wrote, iclass 23, count 2 2006.257.14:11:34.17#ibcon#about to read 3, iclass 23, count 2 2006.257.14:11:34.19#ibcon#read 3, iclass 23, count 2 2006.257.14:11:34.19#ibcon#about to read 4, iclass 23, count 2 2006.257.14:11:34.19#ibcon#read 4, iclass 23, count 2 2006.257.14:11:34.19#ibcon#about to read 5, iclass 23, count 2 2006.257.14:11:34.19#ibcon#read 5, iclass 23, count 2 2006.257.14:11:34.19#ibcon#about to read 6, iclass 23, count 2 2006.257.14:11:34.19#ibcon#read 6, iclass 23, count 2 2006.257.14:11:34.19#ibcon#end of sib2, iclass 23, count 2 2006.257.14:11:34.19#ibcon#*mode == 0, iclass 23, count 2 2006.257.14:11:34.19#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.14:11:34.19#ibcon#[27=AT07-04\r\n] 2006.257.14:11:34.19#ibcon#*before write, iclass 23, count 2 2006.257.14:11:34.19#ibcon#enter sib2, iclass 23, count 2 2006.257.14:11:34.19#ibcon#flushed, iclass 23, count 2 2006.257.14:11:34.19#ibcon#about to write, iclass 23, count 2 2006.257.14:11:34.19#ibcon#wrote, iclass 23, count 2 2006.257.14:11:34.19#ibcon#about to read 3, iclass 23, count 2 2006.257.14:11:34.22#ibcon#read 3, iclass 23, count 2 2006.257.14:11:34.22#ibcon#about to read 4, iclass 23, count 2 2006.257.14:11:34.22#ibcon#read 4, iclass 23, count 2 2006.257.14:11:34.22#ibcon#about to read 5, iclass 23, count 2 2006.257.14:11:34.22#ibcon#read 5, iclass 23, count 2 2006.257.14:11:34.22#ibcon#about to read 6, iclass 23, count 2 2006.257.14:11:34.22#ibcon#read 6, iclass 23, count 2 2006.257.14:11:34.22#ibcon#end of sib2, iclass 23, count 2 2006.257.14:11:34.22#ibcon#*after write, iclass 23, count 2 2006.257.14:11:34.22#ibcon#*before return 0, iclass 23, count 2 2006.257.14:11:34.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:34.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:11:34.22#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.14:11:34.22#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:34.22#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:34.34#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:34.34#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:34.34#ibcon#enter wrdev, iclass 23, count 0 2006.257.14:11:34.34#ibcon#first serial, iclass 23, count 0 2006.257.14:11:34.34#ibcon#enter sib2, iclass 23, count 0 2006.257.14:11:34.34#ibcon#flushed, iclass 23, count 0 2006.257.14:11:34.34#ibcon#about to write, iclass 23, count 0 2006.257.14:11:34.34#ibcon#wrote, iclass 23, count 0 2006.257.14:11:34.34#ibcon#about to read 3, iclass 23, count 0 2006.257.14:11:34.36#ibcon#read 3, iclass 23, count 0 2006.257.14:11:34.36#ibcon#about to read 4, iclass 23, count 0 2006.257.14:11:34.36#ibcon#read 4, iclass 23, count 0 2006.257.14:11:34.36#ibcon#about to read 5, iclass 23, count 0 2006.257.14:11:34.36#ibcon#read 5, iclass 23, count 0 2006.257.14:11:34.36#ibcon#about to read 6, iclass 23, count 0 2006.257.14:11:34.36#ibcon#read 6, iclass 23, count 0 2006.257.14:11:34.36#ibcon#end of sib2, iclass 23, count 0 2006.257.14:11:34.36#ibcon#*mode == 0, iclass 23, count 0 2006.257.14:11:34.36#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.14:11:34.36#ibcon#[27=USB\r\n] 2006.257.14:11:34.36#ibcon#*before write, iclass 23, count 0 2006.257.14:11:34.36#ibcon#enter sib2, iclass 23, count 0 2006.257.14:11:34.36#ibcon#flushed, iclass 23, count 0 2006.257.14:11:34.36#ibcon#about to write, iclass 23, count 0 2006.257.14:11:34.36#ibcon#wrote, iclass 23, count 0 2006.257.14:11:34.36#ibcon#about to read 3, iclass 23, count 0 2006.257.14:11:34.39#ibcon#read 3, iclass 23, count 0 2006.257.14:11:34.39#ibcon#about to read 4, iclass 23, count 0 2006.257.14:11:34.39#ibcon#read 4, iclass 23, count 0 2006.257.14:11:34.39#ibcon#about to read 5, iclass 23, count 0 2006.257.14:11:34.39#ibcon#read 5, iclass 23, count 0 2006.257.14:11:34.39#ibcon#about to read 6, iclass 23, count 0 2006.257.14:11:34.39#ibcon#read 6, iclass 23, count 0 2006.257.14:11:34.39#ibcon#end of sib2, iclass 23, count 0 2006.257.14:11:34.39#ibcon#*after write, iclass 23, count 0 2006.257.14:11:34.39#ibcon#*before return 0, iclass 23, count 0 2006.257.14:11:34.39#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:34.39#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:11:34.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.14:11:34.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.14:11:34.39$vck44/vblo=8,744.99 2006.257.14:11:34.39#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.14:11:34.39#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.14:11:34.39#ibcon#ireg 17 cls_cnt 0 2006.257.14:11:34.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:34.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:34.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:34.39#ibcon#enter wrdev, iclass 25, count 0 2006.257.14:11:34.39#ibcon#first serial, iclass 25, count 0 2006.257.14:11:34.39#ibcon#enter sib2, iclass 25, count 0 2006.257.14:11:34.39#ibcon#flushed, iclass 25, count 0 2006.257.14:11:34.39#ibcon#about to write, iclass 25, count 0 2006.257.14:11:34.39#ibcon#wrote, iclass 25, count 0 2006.257.14:11:34.39#ibcon#about to read 3, iclass 25, count 0 2006.257.14:11:34.41#ibcon#read 3, iclass 25, count 0 2006.257.14:11:34.41#ibcon#about to read 4, iclass 25, count 0 2006.257.14:11:34.41#ibcon#read 4, iclass 25, count 0 2006.257.14:11:34.41#ibcon#about to read 5, iclass 25, count 0 2006.257.14:11:34.41#ibcon#read 5, iclass 25, count 0 2006.257.14:11:34.41#ibcon#about to read 6, iclass 25, count 0 2006.257.14:11:34.41#ibcon#read 6, iclass 25, count 0 2006.257.14:11:34.41#ibcon#end of sib2, iclass 25, count 0 2006.257.14:11:34.41#ibcon#*mode == 0, iclass 25, count 0 2006.257.14:11:34.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.14:11:34.41#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:11:34.41#ibcon#*before write, iclass 25, count 0 2006.257.14:11:34.41#ibcon#enter sib2, iclass 25, count 0 2006.257.14:11:34.41#ibcon#flushed, iclass 25, count 0 2006.257.14:11:34.41#ibcon#about to write, iclass 25, count 0 2006.257.14:11:34.41#ibcon#wrote, iclass 25, count 0 2006.257.14:11:34.41#ibcon#about to read 3, iclass 25, count 0 2006.257.14:11:34.45#ibcon#read 3, iclass 25, count 0 2006.257.14:11:34.45#ibcon#about to read 4, iclass 25, count 0 2006.257.14:11:34.45#ibcon#read 4, iclass 25, count 0 2006.257.14:11:34.45#ibcon#about to read 5, iclass 25, count 0 2006.257.14:11:34.45#ibcon#read 5, iclass 25, count 0 2006.257.14:11:34.45#ibcon#about to read 6, iclass 25, count 0 2006.257.14:11:34.45#ibcon#read 6, iclass 25, count 0 2006.257.14:11:34.45#ibcon#end of sib2, iclass 25, count 0 2006.257.14:11:34.45#ibcon#*after write, iclass 25, count 0 2006.257.14:11:34.45#ibcon#*before return 0, iclass 25, count 0 2006.257.14:11:34.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:34.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:11:34.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.14:11:34.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.14:11:34.45$vck44/vb=8,4 2006.257.14:11:34.45#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.14:11:34.45#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.14:11:34.45#ibcon#ireg 11 cls_cnt 2 2006.257.14:11:34.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:34.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:34.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:34.51#ibcon#enter wrdev, iclass 27, count 2 2006.257.14:11:34.51#ibcon#first serial, iclass 27, count 2 2006.257.14:11:34.51#ibcon#enter sib2, iclass 27, count 2 2006.257.14:11:34.51#ibcon#flushed, iclass 27, count 2 2006.257.14:11:34.51#ibcon#about to write, iclass 27, count 2 2006.257.14:11:34.51#ibcon#wrote, iclass 27, count 2 2006.257.14:11:34.51#ibcon#about to read 3, iclass 27, count 2 2006.257.14:11:34.53#ibcon#read 3, iclass 27, count 2 2006.257.14:11:34.53#ibcon#about to read 4, iclass 27, count 2 2006.257.14:11:34.53#ibcon#read 4, iclass 27, count 2 2006.257.14:11:34.53#ibcon#about to read 5, iclass 27, count 2 2006.257.14:11:34.53#ibcon#read 5, iclass 27, count 2 2006.257.14:11:34.53#ibcon#about to read 6, iclass 27, count 2 2006.257.14:11:34.53#ibcon#read 6, iclass 27, count 2 2006.257.14:11:34.53#ibcon#end of sib2, iclass 27, count 2 2006.257.14:11:34.53#ibcon#*mode == 0, iclass 27, count 2 2006.257.14:11:34.53#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.14:11:34.53#ibcon#[27=AT08-04\r\n] 2006.257.14:11:34.53#ibcon#*before write, iclass 27, count 2 2006.257.14:11:34.53#ibcon#enter sib2, iclass 27, count 2 2006.257.14:11:34.53#ibcon#flushed, iclass 27, count 2 2006.257.14:11:34.53#ibcon#about to write, iclass 27, count 2 2006.257.14:11:34.53#ibcon#wrote, iclass 27, count 2 2006.257.14:11:34.53#ibcon#about to read 3, iclass 27, count 2 2006.257.14:11:34.56#ibcon#read 3, iclass 27, count 2 2006.257.14:11:34.56#ibcon#about to read 4, iclass 27, count 2 2006.257.14:11:34.56#ibcon#read 4, iclass 27, count 2 2006.257.14:11:34.56#ibcon#about to read 5, iclass 27, count 2 2006.257.14:11:34.56#ibcon#read 5, iclass 27, count 2 2006.257.14:11:34.56#ibcon#about to read 6, iclass 27, count 2 2006.257.14:11:34.56#ibcon#read 6, iclass 27, count 2 2006.257.14:11:34.56#ibcon#end of sib2, iclass 27, count 2 2006.257.14:11:34.56#ibcon#*after write, iclass 27, count 2 2006.257.14:11:34.56#ibcon#*before return 0, iclass 27, count 2 2006.257.14:11:34.56#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:34.56#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:11:34.56#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.14:11:34.56#ibcon#ireg 7 cls_cnt 0 2006.257.14:11:34.56#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:34.68#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:34.68#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:34.68#ibcon#enter wrdev, iclass 27, count 0 2006.257.14:11:34.68#ibcon#first serial, iclass 27, count 0 2006.257.14:11:34.68#ibcon#enter sib2, iclass 27, count 0 2006.257.14:11:34.68#ibcon#flushed, iclass 27, count 0 2006.257.14:11:34.68#ibcon#about to write, iclass 27, count 0 2006.257.14:11:34.68#ibcon#wrote, iclass 27, count 0 2006.257.14:11:34.68#ibcon#about to read 3, iclass 27, count 0 2006.257.14:11:34.70#ibcon#read 3, iclass 27, count 0 2006.257.14:11:34.70#ibcon#about to read 4, iclass 27, count 0 2006.257.14:11:34.70#ibcon#read 4, iclass 27, count 0 2006.257.14:11:34.70#ibcon#about to read 5, iclass 27, count 0 2006.257.14:11:34.70#ibcon#read 5, iclass 27, count 0 2006.257.14:11:34.70#ibcon#about to read 6, iclass 27, count 0 2006.257.14:11:34.70#ibcon#read 6, iclass 27, count 0 2006.257.14:11:34.70#ibcon#end of sib2, iclass 27, count 0 2006.257.14:11:34.70#ibcon#*mode == 0, iclass 27, count 0 2006.257.14:11:34.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.14:11:34.70#ibcon#[27=USB\r\n] 2006.257.14:11:34.70#ibcon#*before write, iclass 27, count 0 2006.257.14:11:34.70#ibcon#enter sib2, iclass 27, count 0 2006.257.14:11:34.70#ibcon#flushed, iclass 27, count 0 2006.257.14:11:34.70#ibcon#about to write, iclass 27, count 0 2006.257.14:11:34.70#ibcon#wrote, iclass 27, count 0 2006.257.14:11:34.70#ibcon#about to read 3, iclass 27, count 0 2006.257.14:11:34.73#ibcon#read 3, iclass 27, count 0 2006.257.14:11:34.73#ibcon#about to read 4, iclass 27, count 0 2006.257.14:11:34.73#ibcon#read 4, iclass 27, count 0 2006.257.14:11:34.73#ibcon#about to read 5, iclass 27, count 0 2006.257.14:11:34.73#ibcon#read 5, iclass 27, count 0 2006.257.14:11:34.73#ibcon#about to read 6, iclass 27, count 0 2006.257.14:11:34.73#ibcon#read 6, iclass 27, count 0 2006.257.14:11:34.73#ibcon#end of sib2, iclass 27, count 0 2006.257.14:11:34.73#ibcon#*after write, iclass 27, count 0 2006.257.14:11:34.73#ibcon#*before return 0, iclass 27, count 0 2006.257.14:11:34.73#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:34.73#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:11:34.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.14:11:34.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.14:11:34.73$vck44/vabw=wide 2006.257.14:11:34.73#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.14:11:34.73#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.14:11:34.73#ibcon#ireg 8 cls_cnt 0 2006.257.14:11:34.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:34.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:34.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:34.73#ibcon#enter wrdev, iclass 29, count 0 2006.257.14:11:34.73#ibcon#first serial, iclass 29, count 0 2006.257.14:11:34.73#ibcon#enter sib2, iclass 29, count 0 2006.257.14:11:34.73#ibcon#flushed, iclass 29, count 0 2006.257.14:11:34.73#ibcon#about to write, iclass 29, count 0 2006.257.14:11:34.73#ibcon#wrote, iclass 29, count 0 2006.257.14:11:34.73#ibcon#about to read 3, iclass 29, count 0 2006.257.14:11:34.75#ibcon#read 3, iclass 29, count 0 2006.257.14:11:34.75#ibcon#about to read 4, iclass 29, count 0 2006.257.14:11:34.75#ibcon#read 4, iclass 29, count 0 2006.257.14:11:34.75#ibcon#about to read 5, iclass 29, count 0 2006.257.14:11:34.75#ibcon#read 5, iclass 29, count 0 2006.257.14:11:34.75#ibcon#about to read 6, iclass 29, count 0 2006.257.14:11:34.75#ibcon#read 6, iclass 29, count 0 2006.257.14:11:34.75#ibcon#end of sib2, iclass 29, count 0 2006.257.14:11:34.75#ibcon#*mode == 0, iclass 29, count 0 2006.257.14:11:34.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.14:11:34.75#ibcon#[25=BW32\r\n] 2006.257.14:11:34.75#ibcon#*before write, iclass 29, count 0 2006.257.14:11:34.75#ibcon#enter sib2, iclass 29, count 0 2006.257.14:11:34.75#ibcon#flushed, iclass 29, count 0 2006.257.14:11:34.75#ibcon#about to write, iclass 29, count 0 2006.257.14:11:34.75#ibcon#wrote, iclass 29, count 0 2006.257.14:11:34.75#ibcon#about to read 3, iclass 29, count 0 2006.257.14:11:34.78#ibcon#read 3, iclass 29, count 0 2006.257.14:11:34.78#ibcon#about to read 4, iclass 29, count 0 2006.257.14:11:34.78#ibcon#read 4, iclass 29, count 0 2006.257.14:11:34.78#ibcon#about to read 5, iclass 29, count 0 2006.257.14:11:34.78#ibcon#read 5, iclass 29, count 0 2006.257.14:11:34.78#ibcon#about to read 6, iclass 29, count 0 2006.257.14:11:34.78#ibcon#read 6, iclass 29, count 0 2006.257.14:11:34.78#ibcon#end of sib2, iclass 29, count 0 2006.257.14:11:34.78#ibcon#*after write, iclass 29, count 0 2006.257.14:11:34.78#ibcon#*before return 0, iclass 29, count 0 2006.257.14:11:34.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:34.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:11:34.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.14:11:34.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.14:11:34.78$vck44/vbbw=wide 2006.257.14:11:34.78#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.14:11:34.78#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.14:11:34.78#ibcon#ireg 8 cls_cnt 0 2006.257.14:11:34.78#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:11:34.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:11:34.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:11:34.85#ibcon#enter wrdev, iclass 31, count 0 2006.257.14:11:34.85#ibcon#first serial, iclass 31, count 0 2006.257.14:11:34.85#ibcon#enter sib2, iclass 31, count 0 2006.257.14:11:34.85#ibcon#flushed, iclass 31, count 0 2006.257.14:11:34.85#ibcon#about to write, iclass 31, count 0 2006.257.14:11:34.85#ibcon#wrote, iclass 31, count 0 2006.257.14:11:34.85#ibcon#about to read 3, iclass 31, count 0 2006.257.14:11:34.87#ibcon#read 3, iclass 31, count 0 2006.257.14:11:34.87#ibcon#about to read 4, iclass 31, count 0 2006.257.14:11:34.87#ibcon#read 4, iclass 31, count 0 2006.257.14:11:34.87#ibcon#about to read 5, iclass 31, count 0 2006.257.14:11:34.87#ibcon#read 5, iclass 31, count 0 2006.257.14:11:34.87#ibcon#about to read 6, iclass 31, count 0 2006.257.14:11:34.87#ibcon#read 6, iclass 31, count 0 2006.257.14:11:34.87#ibcon#end of sib2, iclass 31, count 0 2006.257.14:11:34.87#ibcon#*mode == 0, iclass 31, count 0 2006.257.14:11:34.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.14:11:34.87#ibcon#[27=BW32\r\n] 2006.257.14:11:34.87#ibcon#*before write, iclass 31, count 0 2006.257.14:11:34.87#ibcon#enter sib2, iclass 31, count 0 2006.257.14:11:34.87#ibcon#flushed, iclass 31, count 0 2006.257.14:11:34.87#ibcon#about to write, iclass 31, count 0 2006.257.14:11:34.87#ibcon#wrote, iclass 31, count 0 2006.257.14:11:34.87#ibcon#about to read 3, iclass 31, count 0 2006.257.14:11:34.90#ibcon#read 3, iclass 31, count 0 2006.257.14:11:34.90#ibcon#about to read 4, iclass 31, count 0 2006.257.14:11:34.90#ibcon#read 4, iclass 31, count 0 2006.257.14:11:34.90#ibcon#about to read 5, iclass 31, count 0 2006.257.14:11:34.90#ibcon#read 5, iclass 31, count 0 2006.257.14:11:34.90#ibcon#about to read 6, iclass 31, count 0 2006.257.14:11:34.90#ibcon#read 6, iclass 31, count 0 2006.257.14:11:34.90#ibcon#end of sib2, iclass 31, count 0 2006.257.14:11:34.90#ibcon#*after write, iclass 31, count 0 2006.257.14:11:34.90#ibcon#*before return 0, iclass 31, count 0 2006.257.14:11:34.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:11:34.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:11:34.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.14:11:34.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.14:11:34.90$setupk4/ifdk4 2006.257.14:11:34.90$ifdk4/lo= 2006.257.14:11:34.90$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:11:34.90$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:11:34.90$ifdk4/patch= 2006.257.14:11:34.90$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:11:34.90$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:11:34.90$setupk4/!*+20s 2006.257.14:11:42.32#abcon#<5=/14 1.7 3.3 17.48 971014.0\r\n> 2006.257.14:11:42.34#abcon#{5=INTERFACE CLEAR} 2006.257.14:11:42.40#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:11:43.13#trakl#Source acquired 2006.257.14:11:43.13#flagr#flagr/antenna,acquired 2006.257.14:11:44.13$setupk4/"tpicd 2006.257.14:11:44.13$setupk4/echo=off 2006.257.14:11:44.13$setupk4/xlog=off 2006.257.14:11:44.13:!2006.257.14:12:41 2006.257.14:12:41.00:preob 2006.257.14:12:41.13/onsource/TRACKING 2006.257.14:12:41.13:!2006.257.14:12:51 2006.257.14:12:51.00:"tape 2006.257.14:12:51.00:"st=record 2006.257.14:12:51.00:data_valid=on 2006.257.14:12:51.00:midob 2006.257.14:12:52.13/onsource/TRACKING 2006.257.14:12:52.13/wx/17.48,1014.0,97 2006.257.14:12:52.23/cable/+6.4838E-03 2006.257.14:12:53.32/va/01,08,usb,yes,35,38 2006.257.14:12:53.32/va/02,07,usb,yes,38,38 2006.257.14:12:53.32/va/03,08,usb,yes,34,36 2006.257.14:12:53.32/va/04,07,usb,yes,39,41 2006.257.14:12:53.32/va/05,04,usb,yes,35,36 2006.257.14:12:53.32/va/06,04,usb,yes,39,39 2006.257.14:12:53.32/va/07,04,usb,yes,40,40 2006.257.14:12:53.32/va/08,04,usb,yes,34,41 2006.257.14:12:53.55/valo/01,524.99,yes,locked 2006.257.14:12:53.55/valo/02,534.99,yes,locked 2006.257.14:12:53.55/valo/03,564.99,yes,locked 2006.257.14:12:53.55/valo/04,624.99,yes,locked 2006.257.14:12:53.55/valo/05,734.99,yes,locked 2006.257.14:12:53.55/valo/06,814.99,yes,locked 2006.257.14:12:53.55/valo/07,864.99,yes,locked 2006.257.14:12:53.55/valo/08,884.99,yes,locked 2006.257.14:12:54.64/vb/01,04,usb,yes,33,31 2006.257.14:12:54.64/vb/02,05,usb,yes,32,31 2006.257.14:12:54.64/vb/03,04,usb,yes,33,36 2006.257.14:12:54.64/vb/04,05,usb,yes,33,32 2006.257.14:12:54.64/vb/05,04,usb,yes,29,32 2006.257.14:12:54.64/vb/06,04,usb,yes,34,30 2006.257.14:12:54.64/vb/07,04,usb,yes,34,34 2006.257.14:12:54.64/vb/08,04,usb,yes,31,35 2006.257.14:12:54.88/vblo/01,629.99,yes,locked 2006.257.14:12:54.88/vblo/02,634.99,yes,locked 2006.257.14:12:54.88/vblo/03,649.99,yes,locked 2006.257.14:12:54.88/vblo/04,679.99,yes,locked 2006.257.14:12:54.88/vblo/05,709.99,yes,locked 2006.257.14:12:54.88/vblo/06,719.99,yes,locked 2006.257.14:12:54.88/vblo/07,734.99,yes,locked 2006.257.14:12:54.88/vblo/08,744.99,yes,locked 2006.257.14:12:55.03/vabw/8 2006.257.14:12:55.18/vbbw/8 2006.257.14:12:55.27/xfe/off,on,16.2 2006.257.14:12:55.64/ifatt/23,28,28,28 2006.257.14:12:56.07/fmout-gps/S +4.54E-07 2006.257.14:12:56.11:!2006.257.14:13:31 2006.257.14:13:31.00:data_valid=off 2006.257.14:13:31.00:"et 2006.257.14:13:31.00:!+3s 2006.257.14:13:34.01:"tape 2006.257.14:13:34.01:postob 2006.257.14:13:34.19/cable/+6.4842E-03 2006.257.14:13:34.19/wx/17.47,1014.0,97 2006.257.14:13:35.08/fmout-gps/S +4.55E-07 2006.257.14:13:35.08:scan_name=257-1418,jd0609,100 2006.257.14:13:35.08:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.257.14:13:36.13#flagr#flagr/antenna,new-source 2006.257.14:13:36.13:checkk5 2006.257.14:13:36.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:13:36.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:13:37.30/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:13:37.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:13:38.13/chk_obsdata//k5ts1/T2571412??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.14:13:38.53/chk_obsdata//k5ts2/T2571412??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.14:13:38.91/chk_obsdata//k5ts3/T2571412??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.14:13:39.32/chk_obsdata//k5ts4/T2571412??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.14:13:40.04/k5log//k5ts1_log_newline 2006.257.14:13:40.74/k5log//k5ts2_log_newline 2006.257.14:13:41.45/k5log//k5ts3_log_newline 2006.257.14:13:42.14/k5log//k5ts4_log_newline 2006.257.14:13:42.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:13:42.16:setupk4=1 2006.257.14:13:42.16$setupk4/echo=on 2006.257.14:13:42.16$setupk4/pcalon 2006.257.14:13:42.16$pcalon/"no phase cal control is implemented here 2006.257.14:13:42.16$setupk4/"tpicd=stop 2006.257.14:13:42.16$setupk4/"rec=synch_on 2006.257.14:13:42.16$setupk4/"rec_mode=128 2006.257.14:13:42.16$setupk4/!* 2006.257.14:13:42.16$setupk4/recpk4 2006.257.14:13:42.16$recpk4/recpatch= 2006.257.14:13:42.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:13:42.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:13:42.16$setupk4/vck44 2006.257.14:13:42.16$vck44/valo=1,524.99 2006.257.14:13:42.16#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.14:13:42.16#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.14:13:42.16#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:42.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:42.16#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:42.16#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:42.16#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:13:42.16#ibcon#first serial, iclass 12, count 0 2006.257.14:13:42.16#ibcon#enter sib2, iclass 12, count 0 2006.257.14:13:42.16#ibcon#flushed, iclass 12, count 0 2006.257.14:13:42.16#ibcon#about to write, iclass 12, count 0 2006.257.14:13:42.16#ibcon#wrote, iclass 12, count 0 2006.257.14:13:42.16#ibcon#about to read 3, iclass 12, count 0 2006.257.14:13:42.18#ibcon#read 3, iclass 12, count 0 2006.257.14:13:42.18#ibcon#about to read 4, iclass 12, count 0 2006.257.14:13:42.18#ibcon#read 4, iclass 12, count 0 2006.257.14:13:42.18#ibcon#about to read 5, iclass 12, count 0 2006.257.14:13:42.18#ibcon#read 5, iclass 12, count 0 2006.257.14:13:42.18#ibcon#about to read 6, iclass 12, count 0 2006.257.14:13:42.18#ibcon#read 6, iclass 12, count 0 2006.257.14:13:42.18#ibcon#end of sib2, iclass 12, count 0 2006.257.14:13:42.18#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:13:42.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:13:42.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:13:42.18#ibcon#*before write, iclass 12, count 0 2006.257.14:13:42.18#ibcon#enter sib2, iclass 12, count 0 2006.257.14:13:42.18#ibcon#flushed, iclass 12, count 0 2006.257.14:13:42.18#ibcon#about to write, iclass 12, count 0 2006.257.14:13:42.18#ibcon#wrote, iclass 12, count 0 2006.257.14:13:42.18#ibcon#about to read 3, iclass 12, count 0 2006.257.14:13:42.23#ibcon#read 3, iclass 12, count 0 2006.257.14:13:42.23#ibcon#about to read 4, iclass 12, count 0 2006.257.14:13:42.23#ibcon#read 4, iclass 12, count 0 2006.257.14:13:42.23#ibcon#about to read 5, iclass 12, count 0 2006.257.14:13:42.23#ibcon#read 5, iclass 12, count 0 2006.257.14:13:42.23#ibcon#about to read 6, iclass 12, count 0 2006.257.14:13:42.23#ibcon#read 6, iclass 12, count 0 2006.257.14:13:42.23#ibcon#end of sib2, iclass 12, count 0 2006.257.14:13:42.23#ibcon#*after write, iclass 12, count 0 2006.257.14:13:42.23#ibcon#*before return 0, iclass 12, count 0 2006.257.14:13:42.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:42.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:42.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:13:42.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:13:42.23$vck44/va=1,8 2006.257.14:13:42.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.14:13:42.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.14:13:42.23#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:42.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:42.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:42.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:42.23#ibcon#enter wrdev, iclass 14, count 2 2006.257.14:13:42.23#ibcon#first serial, iclass 14, count 2 2006.257.14:13:42.23#ibcon#enter sib2, iclass 14, count 2 2006.257.14:13:42.23#ibcon#flushed, iclass 14, count 2 2006.257.14:13:42.23#ibcon#about to write, iclass 14, count 2 2006.257.14:13:42.23#ibcon#wrote, iclass 14, count 2 2006.257.14:13:42.23#ibcon#about to read 3, iclass 14, count 2 2006.257.14:13:42.25#ibcon#read 3, iclass 14, count 2 2006.257.14:13:42.25#ibcon#about to read 4, iclass 14, count 2 2006.257.14:13:42.25#ibcon#read 4, iclass 14, count 2 2006.257.14:13:42.25#ibcon#about to read 5, iclass 14, count 2 2006.257.14:13:42.25#ibcon#read 5, iclass 14, count 2 2006.257.14:13:42.25#ibcon#about to read 6, iclass 14, count 2 2006.257.14:13:42.25#ibcon#read 6, iclass 14, count 2 2006.257.14:13:42.25#ibcon#end of sib2, iclass 14, count 2 2006.257.14:13:42.25#ibcon#*mode == 0, iclass 14, count 2 2006.257.14:13:42.25#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.14:13:42.25#ibcon#[25=AT01-08\r\n] 2006.257.14:13:42.25#ibcon#*before write, iclass 14, count 2 2006.257.14:13:42.25#ibcon#enter sib2, iclass 14, count 2 2006.257.14:13:42.25#ibcon#flushed, iclass 14, count 2 2006.257.14:13:42.25#ibcon#about to write, iclass 14, count 2 2006.257.14:13:42.25#ibcon#wrote, iclass 14, count 2 2006.257.14:13:42.25#ibcon#about to read 3, iclass 14, count 2 2006.257.14:13:42.28#ibcon#read 3, iclass 14, count 2 2006.257.14:13:42.28#ibcon#about to read 4, iclass 14, count 2 2006.257.14:13:42.28#ibcon#read 4, iclass 14, count 2 2006.257.14:13:42.28#ibcon#about to read 5, iclass 14, count 2 2006.257.14:13:42.28#ibcon#read 5, iclass 14, count 2 2006.257.14:13:42.28#ibcon#about to read 6, iclass 14, count 2 2006.257.14:13:42.28#ibcon#read 6, iclass 14, count 2 2006.257.14:13:42.28#ibcon#end of sib2, iclass 14, count 2 2006.257.14:13:42.28#ibcon#*after write, iclass 14, count 2 2006.257.14:13:42.28#ibcon#*before return 0, iclass 14, count 2 2006.257.14:13:42.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:42.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:42.28#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.14:13:42.28#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:42.28#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:42.40#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:42.40#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:42.40#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:13:42.40#ibcon#first serial, iclass 14, count 0 2006.257.14:13:42.40#ibcon#enter sib2, iclass 14, count 0 2006.257.14:13:42.40#ibcon#flushed, iclass 14, count 0 2006.257.14:13:42.40#ibcon#about to write, iclass 14, count 0 2006.257.14:13:42.40#ibcon#wrote, iclass 14, count 0 2006.257.14:13:42.40#ibcon#about to read 3, iclass 14, count 0 2006.257.14:13:42.42#ibcon#read 3, iclass 14, count 0 2006.257.14:13:42.42#ibcon#about to read 4, iclass 14, count 0 2006.257.14:13:42.42#ibcon#read 4, iclass 14, count 0 2006.257.14:13:42.42#ibcon#about to read 5, iclass 14, count 0 2006.257.14:13:42.42#ibcon#read 5, iclass 14, count 0 2006.257.14:13:42.42#ibcon#about to read 6, iclass 14, count 0 2006.257.14:13:42.42#ibcon#read 6, iclass 14, count 0 2006.257.14:13:42.42#ibcon#end of sib2, iclass 14, count 0 2006.257.14:13:42.42#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:13:42.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:13:42.42#ibcon#[25=USB\r\n] 2006.257.14:13:42.42#ibcon#*before write, iclass 14, count 0 2006.257.14:13:42.42#ibcon#enter sib2, iclass 14, count 0 2006.257.14:13:42.42#ibcon#flushed, iclass 14, count 0 2006.257.14:13:42.42#ibcon#about to write, iclass 14, count 0 2006.257.14:13:42.42#ibcon#wrote, iclass 14, count 0 2006.257.14:13:42.42#ibcon#about to read 3, iclass 14, count 0 2006.257.14:13:42.45#ibcon#read 3, iclass 14, count 0 2006.257.14:13:42.45#ibcon#about to read 4, iclass 14, count 0 2006.257.14:13:42.45#ibcon#read 4, iclass 14, count 0 2006.257.14:13:42.45#ibcon#about to read 5, iclass 14, count 0 2006.257.14:13:42.45#ibcon#read 5, iclass 14, count 0 2006.257.14:13:42.45#ibcon#about to read 6, iclass 14, count 0 2006.257.14:13:42.45#ibcon#read 6, iclass 14, count 0 2006.257.14:13:42.45#ibcon#end of sib2, iclass 14, count 0 2006.257.14:13:42.45#ibcon#*after write, iclass 14, count 0 2006.257.14:13:42.45#ibcon#*before return 0, iclass 14, count 0 2006.257.14:13:42.45#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:42.45#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:42.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:13:42.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:13:42.45$vck44/valo=2,534.99 2006.257.14:13:42.45#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.14:13:42.45#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.14:13:42.45#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:42.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:42.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:42.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:42.45#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:13:42.45#ibcon#first serial, iclass 16, count 0 2006.257.14:13:42.45#ibcon#enter sib2, iclass 16, count 0 2006.257.14:13:42.45#ibcon#flushed, iclass 16, count 0 2006.257.14:13:42.45#ibcon#about to write, iclass 16, count 0 2006.257.14:13:42.45#ibcon#wrote, iclass 16, count 0 2006.257.14:13:42.45#ibcon#about to read 3, iclass 16, count 0 2006.257.14:13:42.47#ibcon#read 3, iclass 16, count 0 2006.257.14:13:42.47#ibcon#about to read 4, iclass 16, count 0 2006.257.14:13:42.47#ibcon#read 4, iclass 16, count 0 2006.257.14:13:42.47#ibcon#about to read 5, iclass 16, count 0 2006.257.14:13:42.47#ibcon#read 5, iclass 16, count 0 2006.257.14:13:42.47#ibcon#about to read 6, iclass 16, count 0 2006.257.14:13:42.47#ibcon#read 6, iclass 16, count 0 2006.257.14:13:42.47#ibcon#end of sib2, iclass 16, count 0 2006.257.14:13:42.47#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:13:42.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:13:42.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:13:42.47#ibcon#*before write, iclass 16, count 0 2006.257.14:13:42.47#ibcon#enter sib2, iclass 16, count 0 2006.257.14:13:42.47#ibcon#flushed, iclass 16, count 0 2006.257.14:13:42.47#ibcon#about to write, iclass 16, count 0 2006.257.14:13:42.47#ibcon#wrote, iclass 16, count 0 2006.257.14:13:42.47#ibcon#about to read 3, iclass 16, count 0 2006.257.14:13:42.51#ibcon#read 3, iclass 16, count 0 2006.257.14:13:42.51#ibcon#about to read 4, iclass 16, count 0 2006.257.14:13:42.51#ibcon#read 4, iclass 16, count 0 2006.257.14:13:42.51#ibcon#about to read 5, iclass 16, count 0 2006.257.14:13:42.51#ibcon#read 5, iclass 16, count 0 2006.257.14:13:42.51#ibcon#about to read 6, iclass 16, count 0 2006.257.14:13:42.51#ibcon#read 6, iclass 16, count 0 2006.257.14:13:42.51#ibcon#end of sib2, iclass 16, count 0 2006.257.14:13:42.51#ibcon#*after write, iclass 16, count 0 2006.257.14:13:42.51#ibcon#*before return 0, iclass 16, count 0 2006.257.14:13:42.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:42.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:42.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:13:42.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:13:42.51$vck44/va=2,7 2006.257.14:13:42.51#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.14:13:42.51#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.14:13:42.51#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:42.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:42.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:42.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:42.57#ibcon#enter wrdev, iclass 18, count 2 2006.257.14:13:42.57#ibcon#first serial, iclass 18, count 2 2006.257.14:13:42.57#ibcon#enter sib2, iclass 18, count 2 2006.257.14:13:42.57#ibcon#flushed, iclass 18, count 2 2006.257.14:13:42.57#ibcon#about to write, iclass 18, count 2 2006.257.14:13:42.57#ibcon#wrote, iclass 18, count 2 2006.257.14:13:42.57#ibcon#about to read 3, iclass 18, count 2 2006.257.14:13:42.59#ibcon#read 3, iclass 18, count 2 2006.257.14:13:42.59#ibcon#about to read 4, iclass 18, count 2 2006.257.14:13:42.59#ibcon#read 4, iclass 18, count 2 2006.257.14:13:42.59#ibcon#about to read 5, iclass 18, count 2 2006.257.14:13:42.59#ibcon#read 5, iclass 18, count 2 2006.257.14:13:42.59#ibcon#about to read 6, iclass 18, count 2 2006.257.14:13:42.59#ibcon#read 6, iclass 18, count 2 2006.257.14:13:42.59#ibcon#end of sib2, iclass 18, count 2 2006.257.14:13:42.59#ibcon#*mode == 0, iclass 18, count 2 2006.257.14:13:42.59#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.14:13:42.59#ibcon#[25=AT02-07\r\n] 2006.257.14:13:42.59#ibcon#*before write, iclass 18, count 2 2006.257.14:13:42.59#ibcon#enter sib2, iclass 18, count 2 2006.257.14:13:42.59#ibcon#flushed, iclass 18, count 2 2006.257.14:13:42.59#ibcon#about to write, iclass 18, count 2 2006.257.14:13:42.59#ibcon#wrote, iclass 18, count 2 2006.257.14:13:42.59#ibcon#about to read 3, iclass 18, count 2 2006.257.14:13:42.62#ibcon#read 3, iclass 18, count 2 2006.257.14:13:42.62#ibcon#about to read 4, iclass 18, count 2 2006.257.14:13:42.62#ibcon#read 4, iclass 18, count 2 2006.257.14:13:42.62#ibcon#about to read 5, iclass 18, count 2 2006.257.14:13:42.62#ibcon#read 5, iclass 18, count 2 2006.257.14:13:42.62#ibcon#about to read 6, iclass 18, count 2 2006.257.14:13:42.62#ibcon#read 6, iclass 18, count 2 2006.257.14:13:42.62#ibcon#end of sib2, iclass 18, count 2 2006.257.14:13:42.62#ibcon#*after write, iclass 18, count 2 2006.257.14:13:42.62#ibcon#*before return 0, iclass 18, count 2 2006.257.14:13:42.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:42.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:42.62#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.14:13:42.62#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:42.62#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:42.74#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:42.74#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:42.74#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:13:42.74#ibcon#first serial, iclass 18, count 0 2006.257.14:13:42.74#ibcon#enter sib2, iclass 18, count 0 2006.257.14:13:42.74#ibcon#flushed, iclass 18, count 0 2006.257.14:13:42.74#ibcon#about to write, iclass 18, count 0 2006.257.14:13:42.74#ibcon#wrote, iclass 18, count 0 2006.257.14:13:42.74#ibcon#about to read 3, iclass 18, count 0 2006.257.14:13:42.76#ibcon#read 3, iclass 18, count 0 2006.257.14:13:42.76#ibcon#about to read 4, iclass 18, count 0 2006.257.14:13:42.76#ibcon#read 4, iclass 18, count 0 2006.257.14:13:42.76#ibcon#about to read 5, iclass 18, count 0 2006.257.14:13:42.76#ibcon#read 5, iclass 18, count 0 2006.257.14:13:42.76#ibcon#about to read 6, iclass 18, count 0 2006.257.14:13:42.76#ibcon#read 6, iclass 18, count 0 2006.257.14:13:42.76#ibcon#end of sib2, iclass 18, count 0 2006.257.14:13:42.76#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:13:42.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:13:42.76#ibcon#[25=USB\r\n] 2006.257.14:13:42.76#ibcon#*before write, iclass 18, count 0 2006.257.14:13:42.76#ibcon#enter sib2, iclass 18, count 0 2006.257.14:13:42.76#ibcon#flushed, iclass 18, count 0 2006.257.14:13:42.76#ibcon#about to write, iclass 18, count 0 2006.257.14:13:42.76#ibcon#wrote, iclass 18, count 0 2006.257.14:13:42.76#ibcon#about to read 3, iclass 18, count 0 2006.257.14:13:42.79#ibcon#read 3, iclass 18, count 0 2006.257.14:13:42.79#ibcon#about to read 4, iclass 18, count 0 2006.257.14:13:42.79#ibcon#read 4, iclass 18, count 0 2006.257.14:13:42.79#ibcon#about to read 5, iclass 18, count 0 2006.257.14:13:42.79#ibcon#read 5, iclass 18, count 0 2006.257.14:13:42.79#ibcon#about to read 6, iclass 18, count 0 2006.257.14:13:42.79#ibcon#read 6, iclass 18, count 0 2006.257.14:13:42.79#ibcon#end of sib2, iclass 18, count 0 2006.257.14:13:42.79#ibcon#*after write, iclass 18, count 0 2006.257.14:13:42.79#ibcon#*before return 0, iclass 18, count 0 2006.257.14:13:42.79#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:42.79#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:42.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:13:42.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:13:42.79$vck44/valo=3,564.99 2006.257.14:13:42.79#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.14:13:42.79#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.14:13:42.79#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:42.79#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:42.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:42.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:42.79#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:13:42.79#ibcon#first serial, iclass 20, count 0 2006.257.14:13:42.79#ibcon#enter sib2, iclass 20, count 0 2006.257.14:13:42.79#ibcon#flushed, iclass 20, count 0 2006.257.14:13:42.79#ibcon#about to write, iclass 20, count 0 2006.257.14:13:42.79#ibcon#wrote, iclass 20, count 0 2006.257.14:13:42.79#ibcon#about to read 3, iclass 20, count 0 2006.257.14:13:42.81#ibcon#read 3, iclass 20, count 0 2006.257.14:13:42.81#ibcon#about to read 4, iclass 20, count 0 2006.257.14:13:42.81#ibcon#read 4, iclass 20, count 0 2006.257.14:13:42.81#ibcon#about to read 5, iclass 20, count 0 2006.257.14:13:42.81#ibcon#read 5, iclass 20, count 0 2006.257.14:13:42.81#ibcon#about to read 6, iclass 20, count 0 2006.257.14:13:42.81#ibcon#read 6, iclass 20, count 0 2006.257.14:13:42.81#ibcon#end of sib2, iclass 20, count 0 2006.257.14:13:42.81#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:13:42.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:13:42.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:13:42.81#ibcon#*before write, iclass 20, count 0 2006.257.14:13:42.81#ibcon#enter sib2, iclass 20, count 0 2006.257.14:13:42.81#ibcon#flushed, iclass 20, count 0 2006.257.14:13:42.81#ibcon#about to write, iclass 20, count 0 2006.257.14:13:42.81#ibcon#wrote, iclass 20, count 0 2006.257.14:13:42.81#ibcon#about to read 3, iclass 20, count 0 2006.257.14:13:42.85#ibcon#read 3, iclass 20, count 0 2006.257.14:13:42.85#ibcon#about to read 4, iclass 20, count 0 2006.257.14:13:42.85#ibcon#read 4, iclass 20, count 0 2006.257.14:13:42.85#ibcon#about to read 5, iclass 20, count 0 2006.257.14:13:42.85#ibcon#read 5, iclass 20, count 0 2006.257.14:13:42.85#ibcon#about to read 6, iclass 20, count 0 2006.257.14:13:42.85#ibcon#read 6, iclass 20, count 0 2006.257.14:13:42.85#ibcon#end of sib2, iclass 20, count 0 2006.257.14:13:42.85#ibcon#*after write, iclass 20, count 0 2006.257.14:13:42.85#ibcon#*before return 0, iclass 20, count 0 2006.257.14:13:42.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:42.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:42.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:13:42.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:13:42.85$vck44/va=3,8 2006.257.14:13:42.85#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.14:13:42.85#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.14:13:42.85#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:42.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:42.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:42.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:42.91#ibcon#enter wrdev, iclass 22, count 2 2006.257.14:13:42.91#ibcon#first serial, iclass 22, count 2 2006.257.14:13:42.91#ibcon#enter sib2, iclass 22, count 2 2006.257.14:13:42.91#ibcon#flushed, iclass 22, count 2 2006.257.14:13:42.91#ibcon#about to write, iclass 22, count 2 2006.257.14:13:42.91#ibcon#wrote, iclass 22, count 2 2006.257.14:13:42.91#ibcon#about to read 3, iclass 22, count 2 2006.257.14:13:42.93#ibcon#read 3, iclass 22, count 2 2006.257.14:13:42.93#ibcon#about to read 4, iclass 22, count 2 2006.257.14:13:42.93#ibcon#read 4, iclass 22, count 2 2006.257.14:13:42.93#ibcon#about to read 5, iclass 22, count 2 2006.257.14:13:42.93#ibcon#read 5, iclass 22, count 2 2006.257.14:13:42.93#ibcon#about to read 6, iclass 22, count 2 2006.257.14:13:42.93#ibcon#read 6, iclass 22, count 2 2006.257.14:13:42.93#ibcon#end of sib2, iclass 22, count 2 2006.257.14:13:42.93#ibcon#*mode == 0, iclass 22, count 2 2006.257.14:13:42.93#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.14:13:42.93#ibcon#[25=AT03-08\r\n] 2006.257.14:13:42.93#ibcon#*before write, iclass 22, count 2 2006.257.14:13:42.93#ibcon#enter sib2, iclass 22, count 2 2006.257.14:13:42.93#ibcon#flushed, iclass 22, count 2 2006.257.14:13:42.93#ibcon#about to write, iclass 22, count 2 2006.257.14:13:42.93#ibcon#wrote, iclass 22, count 2 2006.257.14:13:42.93#ibcon#about to read 3, iclass 22, count 2 2006.257.14:13:42.96#ibcon#read 3, iclass 22, count 2 2006.257.14:13:42.96#ibcon#about to read 4, iclass 22, count 2 2006.257.14:13:42.96#ibcon#read 4, iclass 22, count 2 2006.257.14:13:42.96#ibcon#about to read 5, iclass 22, count 2 2006.257.14:13:42.96#ibcon#read 5, iclass 22, count 2 2006.257.14:13:42.96#ibcon#about to read 6, iclass 22, count 2 2006.257.14:13:42.96#ibcon#read 6, iclass 22, count 2 2006.257.14:13:42.96#ibcon#end of sib2, iclass 22, count 2 2006.257.14:13:42.96#ibcon#*after write, iclass 22, count 2 2006.257.14:13:42.96#ibcon#*before return 0, iclass 22, count 2 2006.257.14:13:42.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:42.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:42.96#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.14:13:42.96#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:42.96#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:43.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:43.08#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:43.08#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:13:43.08#ibcon#first serial, iclass 22, count 0 2006.257.14:13:43.08#ibcon#enter sib2, iclass 22, count 0 2006.257.14:13:43.08#ibcon#flushed, iclass 22, count 0 2006.257.14:13:43.08#ibcon#about to write, iclass 22, count 0 2006.257.14:13:43.08#ibcon#wrote, iclass 22, count 0 2006.257.14:13:43.08#ibcon#about to read 3, iclass 22, count 0 2006.257.14:13:43.10#ibcon#read 3, iclass 22, count 0 2006.257.14:13:43.10#ibcon#about to read 4, iclass 22, count 0 2006.257.14:13:43.10#ibcon#read 4, iclass 22, count 0 2006.257.14:13:43.10#ibcon#about to read 5, iclass 22, count 0 2006.257.14:13:43.10#ibcon#read 5, iclass 22, count 0 2006.257.14:13:43.10#ibcon#about to read 6, iclass 22, count 0 2006.257.14:13:43.10#ibcon#read 6, iclass 22, count 0 2006.257.14:13:43.10#ibcon#end of sib2, iclass 22, count 0 2006.257.14:13:43.10#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:13:43.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:13:43.10#ibcon#[25=USB\r\n] 2006.257.14:13:43.10#ibcon#*before write, iclass 22, count 0 2006.257.14:13:43.10#ibcon#enter sib2, iclass 22, count 0 2006.257.14:13:43.10#ibcon#flushed, iclass 22, count 0 2006.257.14:13:43.10#ibcon#about to write, iclass 22, count 0 2006.257.14:13:43.10#ibcon#wrote, iclass 22, count 0 2006.257.14:13:43.10#ibcon#about to read 3, iclass 22, count 0 2006.257.14:13:43.13#ibcon#read 3, iclass 22, count 0 2006.257.14:13:43.13#ibcon#about to read 4, iclass 22, count 0 2006.257.14:13:43.13#ibcon#read 4, iclass 22, count 0 2006.257.14:13:43.13#ibcon#about to read 5, iclass 22, count 0 2006.257.14:13:43.13#ibcon#read 5, iclass 22, count 0 2006.257.14:13:43.13#ibcon#about to read 6, iclass 22, count 0 2006.257.14:13:43.13#ibcon#read 6, iclass 22, count 0 2006.257.14:13:43.13#ibcon#end of sib2, iclass 22, count 0 2006.257.14:13:43.13#ibcon#*after write, iclass 22, count 0 2006.257.14:13:43.13#ibcon#*before return 0, iclass 22, count 0 2006.257.14:13:43.13#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:43.13#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:43.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:13:43.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:13:43.13$vck44/valo=4,624.99 2006.257.14:13:43.13#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.14:13:43.13#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.14:13:43.13#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:43.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:43.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:43.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:43.13#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:13:43.13#ibcon#first serial, iclass 24, count 0 2006.257.14:13:43.13#ibcon#enter sib2, iclass 24, count 0 2006.257.14:13:43.13#ibcon#flushed, iclass 24, count 0 2006.257.14:13:43.13#ibcon#about to write, iclass 24, count 0 2006.257.14:13:43.13#ibcon#wrote, iclass 24, count 0 2006.257.14:13:43.13#ibcon#about to read 3, iclass 24, count 0 2006.257.14:13:43.15#ibcon#read 3, iclass 24, count 0 2006.257.14:13:43.15#ibcon#about to read 4, iclass 24, count 0 2006.257.14:13:43.15#ibcon#read 4, iclass 24, count 0 2006.257.14:13:43.15#ibcon#about to read 5, iclass 24, count 0 2006.257.14:13:43.15#ibcon#read 5, iclass 24, count 0 2006.257.14:13:43.15#ibcon#about to read 6, iclass 24, count 0 2006.257.14:13:43.15#ibcon#read 6, iclass 24, count 0 2006.257.14:13:43.15#ibcon#end of sib2, iclass 24, count 0 2006.257.14:13:43.15#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:13:43.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:13:43.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:13:43.15#ibcon#*before write, iclass 24, count 0 2006.257.14:13:43.15#ibcon#enter sib2, iclass 24, count 0 2006.257.14:13:43.15#ibcon#flushed, iclass 24, count 0 2006.257.14:13:43.15#ibcon#about to write, iclass 24, count 0 2006.257.14:13:43.15#ibcon#wrote, iclass 24, count 0 2006.257.14:13:43.15#ibcon#about to read 3, iclass 24, count 0 2006.257.14:13:43.19#ibcon#read 3, iclass 24, count 0 2006.257.14:13:43.19#ibcon#about to read 4, iclass 24, count 0 2006.257.14:13:43.19#ibcon#read 4, iclass 24, count 0 2006.257.14:13:43.19#ibcon#about to read 5, iclass 24, count 0 2006.257.14:13:43.19#ibcon#read 5, iclass 24, count 0 2006.257.14:13:43.19#ibcon#about to read 6, iclass 24, count 0 2006.257.14:13:43.19#ibcon#read 6, iclass 24, count 0 2006.257.14:13:43.19#ibcon#end of sib2, iclass 24, count 0 2006.257.14:13:43.19#ibcon#*after write, iclass 24, count 0 2006.257.14:13:43.19#ibcon#*before return 0, iclass 24, count 0 2006.257.14:13:43.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:43.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:43.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:13:43.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:13:43.19$vck44/va=4,7 2006.257.14:13:43.19#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.14:13:43.19#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.14:13:43.19#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:43.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:43.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:43.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:43.25#ibcon#enter wrdev, iclass 26, count 2 2006.257.14:13:43.25#ibcon#first serial, iclass 26, count 2 2006.257.14:13:43.25#ibcon#enter sib2, iclass 26, count 2 2006.257.14:13:43.25#ibcon#flushed, iclass 26, count 2 2006.257.14:13:43.25#ibcon#about to write, iclass 26, count 2 2006.257.14:13:43.25#ibcon#wrote, iclass 26, count 2 2006.257.14:13:43.25#ibcon#about to read 3, iclass 26, count 2 2006.257.14:13:43.27#ibcon#read 3, iclass 26, count 2 2006.257.14:13:43.27#ibcon#about to read 4, iclass 26, count 2 2006.257.14:13:43.27#ibcon#read 4, iclass 26, count 2 2006.257.14:13:43.27#ibcon#about to read 5, iclass 26, count 2 2006.257.14:13:43.27#ibcon#read 5, iclass 26, count 2 2006.257.14:13:43.27#ibcon#about to read 6, iclass 26, count 2 2006.257.14:13:43.27#ibcon#read 6, iclass 26, count 2 2006.257.14:13:43.27#ibcon#end of sib2, iclass 26, count 2 2006.257.14:13:43.27#ibcon#*mode == 0, iclass 26, count 2 2006.257.14:13:43.27#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.14:13:43.27#ibcon#[25=AT04-07\r\n] 2006.257.14:13:43.27#ibcon#*before write, iclass 26, count 2 2006.257.14:13:43.27#ibcon#enter sib2, iclass 26, count 2 2006.257.14:13:43.27#ibcon#flushed, iclass 26, count 2 2006.257.14:13:43.27#ibcon#about to write, iclass 26, count 2 2006.257.14:13:43.27#ibcon#wrote, iclass 26, count 2 2006.257.14:13:43.27#ibcon#about to read 3, iclass 26, count 2 2006.257.14:13:43.30#ibcon#read 3, iclass 26, count 2 2006.257.14:13:43.30#ibcon#about to read 4, iclass 26, count 2 2006.257.14:13:43.30#ibcon#read 4, iclass 26, count 2 2006.257.14:13:43.30#ibcon#about to read 5, iclass 26, count 2 2006.257.14:13:43.30#ibcon#read 5, iclass 26, count 2 2006.257.14:13:43.30#ibcon#about to read 6, iclass 26, count 2 2006.257.14:13:43.30#ibcon#read 6, iclass 26, count 2 2006.257.14:13:43.30#ibcon#end of sib2, iclass 26, count 2 2006.257.14:13:43.30#ibcon#*after write, iclass 26, count 2 2006.257.14:13:43.30#ibcon#*before return 0, iclass 26, count 2 2006.257.14:13:43.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:43.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:43.30#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.14:13:43.30#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:43.30#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:43.42#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:43.42#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:43.42#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:13:43.42#ibcon#first serial, iclass 26, count 0 2006.257.14:13:43.42#ibcon#enter sib2, iclass 26, count 0 2006.257.14:13:43.42#ibcon#flushed, iclass 26, count 0 2006.257.14:13:43.42#ibcon#about to write, iclass 26, count 0 2006.257.14:13:43.42#ibcon#wrote, iclass 26, count 0 2006.257.14:13:43.42#ibcon#about to read 3, iclass 26, count 0 2006.257.14:13:43.44#ibcon#read 3, iclass 26, count 0 2006.257.14:13:43.44#ibcon#about to read 4, iclass 26, count 0 2006.257.14:13:43.44#ibcon#read 4, iclass 26, count 0 2006.257.14:13:43.44#ibcon#about to read 5, iclass 26, count 0 2006.257.14:13:43.44#ibcon#read 5, iclass 26, count 0 2006.257.14:13:43.44#ibcon#about to read 6, iclass 26, count 0 2006.257.14:13:43.44#ibcon#read 6, iclass 26, count 0 2006.257.14:13:43.44#ibcon#end of sib2, iclass 26, count 0 2006.257.14:13:43.44#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:13:43.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:13:43.44#ibcon#[25=USB\r\n] 2006.257.14:13:43.44#ibcon#*before write, iclass 26, count 0 2006.257.14:13:43.44#ibcon#enter sib2, iclass 26, count 0 2006.257.14:13:43.44#ibcon#flushed, iclass 26, count 0 2006.257.14:13:43.44#ibcon#about to write, iclass 26, count 0 2006.257.14:13:43.44#ibcon#wrote, iclass 26, count 0 2006.257.14:13:43.44#ibcon#about to read 3, iclass 26, count 0 2006.257.14:13:43.47#ibcon#read 3, iclass 26, count 0 2006.257.14:13:43.47#ibcon#about to read 4, iclass 26, count 0 2006.257.14:13:43.47#ibcon#read 4, iclass 26, count 0 2006.257.14:13:43.47#ibcon#about to read 5, iclass 26, count 0 2006.257.14:13:43.47#ibcon#read 5, iclass 26, count 0 2006.257.14:13:43.47#ibcon#about to read 6, iclass 26, count 0 2006.257.14:13:43.47#ibcon#read 6, iclass 26, count 0 2006.257.14:13:43.47#ibcon#end of sib2, iclass 26, count 0 2006.257.14:13:43.47#ibcon#*after write, iclass 26, count 0 2006.257.14:13:43.47#ibcon#*before return 0, iclass 26, count 0 2006.257.14:13:43.47#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:43.47#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:43.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:13:43.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:13:43.47$vck44/valo=5,734.99 2006.257.14:13:43.47#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.14:13:43.47#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.14:13:43.47#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:43.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:43.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:43.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:43.47#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:13:43.47#ibcon#first serial, iclass 28, count 0 2006.257.14:13:43.47#ibcon#enter sib2, iclass 28, count 0 2006.257.14:13:43.47#ibcon#flushed, iclass 28, count 0 2006.257.14:13:43.47#ibcon#about to write, iclass 28, count 0 2006.257.14:13:43.47#ibcon#wrote, iclass 28, count 0 2006.257.14:13:43.47#ibcon#about to read 3, iclass 28, count 0 2006.257.14:13:43.49#ibcon#read 3, iclass 28, count 0 2006.257.14:13:43.49#ibcon#about to read 4, iclass 28, count 0 2006.257.14:13:43.49#ibcon#read 4, iclass 28, count 0 2006.257.14:13:43.49#ibcon#about to read 5, iclass 28, count 0 2006.257.14:13:43.49#ibcon#read 5, iclass 28, count 0 2006.257.14:13:43.49#ibcon#about to read 6, iclass 28, count 0 2006.257.14:13:43.49#ibcon#read 6, iclass 28, count 0 2006.257.14:13:43.49#ibcon#end of sib2, iclass 28, count 0 2006.257.14:13:43.49#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:13:43.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:13:43.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:13:43.49#ibcon#*before write, iclass 28, count 0 2006.257.14:13:43.49#ibcon#enter sib2, iclass 28, count 0 2006.257.14:13:43.49#ibcon#flushed, iclass 28, count 0 2006.257.14:13:43.49#ibcon#about to write, iclass 28, count 0 2006.257.14:13:43.49#ibcon#wrote, iclass 28, count 0 2006.257.14:13:43.49#ibcon#about to read 3, iclass 28, count 0 2006.257.14:13:43.53#ibcon#read 3, iclass 28, count 0 2006.257.14:13:43.53#ibcon#about to read 4, iclass 28, count 0 2006.257.14:13:43.53#ibcon#read 4, iclass 28, count 0 2006.257.14:13:43.53#ibcon#about to read 5, iclass 28, count 0 2006.257.14:13:43.53#ibcon#read 5, iclass 28, count 0 2006.257.14:13:44.19#ibcon#about to read 6, iclass 28, count 0 2006.257.14:13:44.19#ibcon#read 6, iclass 28, count 0 2006.257.14:13:44.19#ibcon#end of sib2, iclass 28, count 0 2006.257.14:13:44.19#ibcon#*after write, iclass 28, count 0 2006.257.14:13:44.19#ibcon#*before return 0, iclass 28, count 0 2006.257.14:13:44.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:44.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:44.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:13:44.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:13:44.19$vck44/va=5,4 2006.257.14:13:44.19#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.14:13:44.19#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.14:13:44.19#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:44.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:44.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:44.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:44.19#ibcon#enter wrdev, iclass 30, count 2 2006.257.14:13:44.19#ibcon#first serial, iclass 30, count 2 2006.257.14:13:44.19#ibcon#enter sib2, iclass 30, count 2 2006.257.14:13:44.19#ibcon#flushed, iclass 30, count 2 2006.257.14:13:44.19#ibcon#about to write, iclass 30, count 2 2006.257.14:13:44.19#ibcon#wrote, iclass 30, count 2 2006.257.14:13:44.19#ibcon#about to read 3, iclass 30, count 2 2006.257.14:13:44.21#ibcon#read 3, iclass 30, count 2 2006.257.14:13:44.21#ibcon#about to read 4, iclass 30, count 2 2006.257.14:13:44.21#ibcon#read 4, iclass 30, count 2 2006.257.14:13:44.21#ibcon#about to read 5, iclass 30, count 2 2006.257.14:13:44.21#ibcon#read 5, iclass 30, count 2 2006.257.14:13:44.21#ibcon#about to read 6, iclass 30, count 2 2006.257.14:13:44.21#ibcon#read 6, iclass 30, count 2 2006.257.14:13:44.21#ibcon#end of sib2, iclass 30, count 2 2006.257.14:13:44.21#ibcon#*mode == 0, iclass 30, count 2 2006.257.14:13:44.21#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.14:13:44.21#ibcon#[25=AT05-04\r\n] 2006.257.14:13:44.21#ibcon#*before write, iclass 30, count 2 2006.257.14:13:44.21#ibcon#enter sib2, iclass 30, count 2 2006.257.14:13:44.21#ibcon#flushed, iclass 30, count 2 2006.257.14:13:44.21#ibcon#about to write, iclass 30, count 2 2006.257.14:13:44.21#ibcon#wrote, iclass 30, count 2 2006.257.14:13:44.21#ibcon#about to read 3, iclass 30, count 2 2006.257.14:13:44.24#ibcon#read 3, iclass 30, count 2 2006.257.14:13:44.24#ibcon#about to read 4, iclass 30, count 2 2006.257.14:13:44.24#ibcon#read 4, iclass 30, count 2 2006.257.14:13:44.24#ibcon#about to read 5, iclass 30, count 2 2006.257.14:13:44.24#ibcon#read 5, iclass 30, count 2 2006.257.14:13:44.24#ibcon#about to read 6, iclass 30, count 2 2006.257.14:13:44.24#ibcon#read 6, iclass 30, count 2 2006.257.14:13:44.24#ibcon#end of sib2, iclass 30, count 2 2006.257.14:13:44.24#ibcon#*after write, iclass 30, count 2 2006.257.14:13:44.24#ibcon#*before return 0, iclass 30, count 2 2006.257.14:13:44.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:44.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:44.24#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.14:13:44.24#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:44.24#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:44.36#abcon#<5=/14 1.8 4.7 17.47 971014.0\r\n> 2006.257.14:13:44.36#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:44.36#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:44.36#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:13:44.36#ibcon#first serial, iclass 30, count 0 2006.257.14:13:44.36#ibcon#enter sib2, iclass 30, count 0 2006.257.14:13:44.36#ibcon#flushed, iclass 30, count 0 2006.257.14:13:44.36#ibcon#about to write, iclass 30, count 0 2006.257.14:13:44.36#ibcon#wrote, iclass 30, count 0 2006.257.14:13:44.36#ibcon#about to read 3, iclass 30, count 0 2006.257.14:13:44.38#abcon#{5=INTERFACE CLEAR} 2006.257.14:13:44.38#ibcon#read 3, iclass 30, count 0 2006.257.14:13:44.38#ibcon#about to read 4, iclass 30, count 0 2006.257.14:13:44.38#ibcon#read 4, iclass 30, count 0 2006.257.14:13:44.38#ibcon#about to read 5, iclass 30, count 0 2006.257.14:13:44.38#ibcon#read 5, iclass 30, count 0 2006.257.14:13:44.38#ibcon#about to read 6, iclass 30, count 0 2006.257.14:13:44.38#ibcon#read 6, iclass 30, count 0 2006.257.14:13:44.38#ibcon#end of sib2, iclass 30, count 0 2006.257.14:13:44.38#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:13:44.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:13:44.38#ibcon#[25=USB\r\n] 2006.257.14:13:44.38#ibcon#*before write, iclass 30, count 0 2006.257.14:13:44.38#ibcon#enter sib2, iclass 30, count 0 2006.257.14:13:44.38#ibcon#flushed, iclass 30, count 0 2006.257.14:13:44.38#ibcon#about to write, iclass 30, count 0 2006.257.14:13:44.38#ibcon#wrote, iclass 30, count 0 2006.257.14:13:44.38#ibcon#about to read 3, iclass 30, count 0 2006.257.14:13:44.41#ibcon#read 3, iclass 30, count 0 2006.257.14:13:44.41#ibcon#about to read 4, iclass 30, count 0 2006.257.14:13:44.41#ibcon#read 4, iclass 30, count 0 2006.257.14:13:44.41#ibcon#about to read 5, iclass 30, count 0 2006.257.14:13:44.41#ibcon#read 5, iclass 30, count 0 2006.257.14:13:44.41#ibcon#about to read 6, iclass 30, count 0 2006.257.14:13:44.41#ibcon#read 6, iclass 30, count 0 2006.257.14:13:44.41#ibcon#end of sib2, iclass 30, count 0 2006.257.14:13:44.41#ibcon#*after write, iclass 30, count 0 2006.257.14:13:44.41#ibcon#*before return 0, iclass 30, count 0 2006.257.14:13:44.41#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:44.41#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:44.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:13:44.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:13:44.41$vck44/valo=6,814.99 2006.257.14:13:44.41#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.14:13:44.41#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.14:13:44.41#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:44.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:13:44.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:13:44.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:13:44.41#ibcon#enter wrdev, iclass 35, count 0 2006.257.14:13:44.41#ibcon#first serial, iclass 35, count 0 2006.257.14:13:44.41#ibcon#enter sib2, iclass 35, count 0 2006.257.14:13:44.41#ibcon#flushed, iclass 35, count 0 2006.257.14:13:44.41#ibcon#about to write, iclass 35, count 0 2006.257.14:13:44.41#ibcon#wrote, iclass 35, count 0 2006.257.14:13:44.41#ibcon#about to read 3, iclass 35, count 0 2006.257.14:13:44.43#ibcon#read 3, iclass 35, count 0 2006.257.14:13:44.43#ibcon#about to read 4, iclass 35, count 0 2006.257.14:13:44.43#ibcon#read 4, iclass 35, count 0 2006.257.14:13:44.43#ibcon#about to read 5, iclass 35, count 0 2006.257.14:13:44.43#ibcon#read 5, iclass 35, count 0 2006.257.14:13:44.43#ibcon#about to read 6, iclass 35, count 0 2006.257.14:13:44.43#ibcon#read 6, iclass 35, count 0 2006.257.14:13:44.43#ibcon#end of sib2, iclass 35, count 0 2006.257.14:13:44.43#ibcon#*mode == 0, iclass 35, count 0 2006.257.14:13:44.43#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.14:13:44.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:13:44.43#ibcon#*before write, iclass 35, count 0 2006.257.14:13:44.43#ibcon#enter sib2, iclass 35, count 0 2006.257.14:13:44.43#ibcon#flushed, iclass 35, count 0 2006.257.14:13:44.43#ibcon#about to write, iclass 35, count 0 2006.257.14:13:44.43#ibcon#wrote, iclass 35, count 0 2006.257.14:13:44.43#ibcon#about to read 3, iclass 35, count 0 2006.257.14:13:44.44#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:13:44.47#ibcon#read 3, iclass 35, count 0 2006.257.14:13:44.47#ibcon#about to read 4, iclass 35, count 0 2006.257.14:13:44.47#ibcon#read 4, iclass 35, count 0 2006.257.14:13:44.47#ibcon#about to read 5, iclass 35, count 0 2006.257.14:13:44.47#ibcon#read 5, iclass 35, count 0 2006.257.14:13:44.47#ibcon#about to read 6, iclass 35, count 0 2006.257.14:13:44.47#ibcon#read 6, iclass 35, count 0 2006.257.14:13:44.47#ibcon#end of sib2, iclass 35, count 0 2006.257.14:13:44.47#ibcon#*after write, iclass 35, count 0 2006.257.14:13:44.47#ibcon#*before return 0, iclass 35, count 0 2006.257.14:13:44.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:13:44.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:13:44.47#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.14:13:44.47#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.14:13:44.47$vck44/va=6,4 2006.257.14:13:44.47#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.14:13:44.47#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.14:13:44.47#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:44.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:44.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:44.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:44.53#ibcon#enter wrdev, iclass 38, count 2 2006.257.14:13:44.53#ibcon#first serial, iclass 38, count 2 2006.257.14:13:44.53#ibcon#enter sib2, iclass 38, count 2 2006.257.14:13:44.53#ibcon#flushed, iclass 38, count 2 2006.257.14:13:44.53#ibcon#about to write, iclass 38, count 2 2006.257.14:13:44.53#ibcon#wrote, iclass 38, count 2 2006.257.14:13:44.53#ibcon#about to read 3, iclass 38, count 2 2006.257.14:13:44.55#ibcon#read 3, iclass 38, count 2 2006.257.14:13:44.55#ibcon#about to read 4, iclass 38, count 2 2006.257.14:13:44.55#ibcon#read 4, iclass 38, count 2 2006.257.14:13:44.55#ibcon#about to read 5, iclass 38, count 2 2006.257.14:13:44.55#ibcon#read 5, iclass 38, count 2 2006.257.14:13:44.55#ibcon#about to read 6, iclass 38, count 2 2006.257.14:13:44.55#ibcon#read 6, iclass 38, count 2 2006.257.14:13:44.55#ibcon#end of sib2, iclass 38, count 2 2006.257.14:13:44.55#ibcon#*mode == 0, iclass 38, count 2 2006.257.14:13:44.55#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.14:13:44.55#ibcon#[25=AT06-04\r\n] 2006.257.14:13:44.55#ibcon#*before write, iclass 38, count 2 2006.257.14:13:44.55#ibcon#enter sib2, iclass 38, count 2 2006.257.14:13:44.55#ibcon#flushed, iclass 38, count 2 2006.257.14:13:44.55#ibcon#about to write, iclass 38, count 2 2006.257.14:13:44.55#ibcon#wrote, iclass 38, count 2 2006.257.14:13:44.55#ibcon#about to read 3, iclass 38, count 2 2006.257.14:13:44.58#ibcon#read 3, iclass 38, count 2 2006.257.14:13:44.58#ibcon#about to read 4, iclass 38, count 2 2006.257.14:13:44.58#ibcon#read 4, iclass 38, count 2 2006.257.14:13:44.58#ibcon#about to read 5, iclass 38, count 2 2006.257.14:13:44.58#ibcon#read 5, iclass 38, count 2 2006.257.14:13:44.58#ibcon#about to read 6, iclass 38, count 2 2006.257.14:13:44.58#ibcon#read 6, iclass 38, count 2 2006.257.14:13:44.58#ibcon#end of sib2, iclass 38, count 2 2006.257.14:13:44.58#ibcon#*after write, iclass 38, count 2 2006.257.14:13:44.58#ibcon#*before return 0, iclass 38, count 2 2006.257.14:13:44.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:44.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:44.58#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.14:13:44.58#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:44.58#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:44.70#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:44.70#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:44.70#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:13:44.70#ibcon#first serial, iclass 38, count 0 2006.257.14:13:44.70#ibcon#enter sib2, iclass 38, count 0 2006.257.14:13:44.70#ibcon#flushed, iclass 38, count 0 2006.257.14:13:44.70#ibcon#about to write, iclass 38, count 0 2006.257.14:13:44.70#ibcon#wrote, iclass 38, count 0 2006.257.14:13:44.70#ibcon#about to read 3, iclass 38, count 0 2006.257.14:13:44.72#ibcon#read 3, iclass 38, count 0 2006.257.14:13:44.72#ibcon#about to read 4, iclass 38, count 0 2006.257.14:13:44.72#ibcon#read 4, iclass 38, count 0 2006.257.14:13:44.72#ibcon#about to read 5, iclass 38, count 0 2006.257.14:13:44.72#ibcon#read 5, iclass 38, count 0 2006.257.14:13:44.72#ibcon#about to read 6, iclass 38, count 0 2006.257.14:13:44.72#ibcon#read 6, iclass 38, count 0 2006.257.14:13:44.72#ibcon#end of sib2, iclass 38, count 0 2006.257.14:13:44.72#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:13:44.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:13:44.72#ibcon#[25=USB\r\n] 2006.257.14:13:44.72#ibcon#*before write, iclass 38, count 0 2006.257.14:13:44.72#ibcon#enter sib2, iclass 38, count 0 2006.257.14:13:44.72#ibcon#flushed, iclass 38, count 0 2006.257.14:13:44.72#ibcon#about to write, iclass 38, count 0 2006.257.14:13:44.72#ibcon#wrote, iclass 38, count 0 2006.257.14:13:44.72#ibcon#about to read 3, iclass 38, count 0 2006.257.14:13:44.75#ibcon#read 3, iclass 38, count 0 2006.257.14:13:44.75#ibcon#about to read 4, iclass 38, count 0 2006.257.14:13:44.75#ibcon#read 4, iclass 38, count 0 2006.257.14:13:44.75#ibcon#about to read 5, iclass 38, count 0 2006.257.14:13:44.75#ibcon#read 5, iclass 38, count 0 2006.257.14:13:44.75#ibcon#about to read 6, iclass 38, count 0 2006.257.14:13:44.75#ibcon#read 6, iclass 38, count 0 2006.257.14:13:44.75#ibcon#end of sib2, iclass 38, count 0 2006.257.14:13:44.75#ibcon#*after write, iclass 38, count 0 2006.257.14:13:44.75#ibcon#*before return 0, iclass 38, count 0 2006.257.14:13:44.75#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:44.75#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:44.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:13:44.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:13:44.75$vck44/valo=7,864.99 2006.257.14:13:44.75#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.14:13:44.75#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.14:13:44.75#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:44.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:44.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:44.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:44.75#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:13:44.75#ibcon#first serial, iclass 40, count 0 2006.257.14:13:44.75#ibcon#enter sib2, iclass 40, count 0 2006.257.14:13:44.75#ibcon#flushed, iclass 40, count 0 2006.257.14:13:44.75#ibcon#about to write, iclass 40, count 0 2006.257.14:13:44.75#ibcon#wrote, iclass 40, count 0 2006.257.14:13:44.75#ibcon#about to read 3, iclass 40, count 0 2006.257.14:13:44.77#ibcon#read 3, iclass 40, count 0 2006.257.14:13:44.77#ibcon#about to read 4, iclass 40, count 0 2006.257.14:13:44.77#ibcon#read 4, iclass 40, count 0 2006.257.14:13:44.77#ibcon#about to read 5, iclass 40, count 0 2006.257.14:13:44.77#ibcon#read 5, iclass 40, count 0 2006.257.14:13:44.77#ibcon#about to read 6, iclass 40, count 0 2006.257.14:13:44.77#ibcon#read 6, iclass 40, count 0 2006.257.14:13:44.77#ibcon#end of sib2, iclass 40, count 0 2006.257.14:13:44.77#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:13:44.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:13:44.77#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:13:44.77#ibcon#*before write, iclass 40, count 0 2006.257.14:13:44.77#ibcon#enter sib2, iclass 40, count 0 2006.257.14:13:44.77#ibcon#flushed, iclass 40, count 0 2006.257.14:13:44.77#ibcon#about to write, iclass 40, count 0 2006.257.14:13:44.77#ibcon#wrote, iclass 40, count 0 2006.257.14:13:44.77#ibcon#about to read 3, iclass 40, count 0 2006.257.14:13:44.81#ibcon#read 3, iclass 40, count 0 2006.257.14:13:44.81#ibcon#about to read 4, iclass 40, count 0 2006.257.14:13:44.81#ibcon#read 4, iclass 40, count 0 2006.257.14:13:44.81#ibcon#about to read 5, iclass 40, count 0 2006.257.14:13:44.81#ibcon#read 5, iclass 40, count 0 2006.257.14:13:44.81#ibcon#about to read 6, iclass 40, count 0 2006.257.14:13:44.81#ibcon#read 6, iclass 40, count 0 2006.257.14:13:44.81#ibcon#end of sib2, iclass 40, count 0 2006.257.14:13:44.81#ibcon#*after write, iclass 40, count 0 2006.257.14:13:44.81#ibcon#*before return 0, iclass 40, count 0 2006.257.14:13:44.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:44.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:44.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:13:44.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:13:44.81$vck44/va=7,4 2006.257.14:13:44.81#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.14:13:44.81#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.14:13:44.81#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:44.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:44.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:44.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:44.87#ibcon#enter wrdev, iclass 4, count 2 2006.257.14:13:44.87#ibcon#first serial, iclass 4, count 2 2006.257.14:13:44.87#ibcon#enter sib2, iclass 4, count 2 2006.257.14:13:44.87#ibcon#flushed, iclass 4, count 2 2006.257.14:13:44.87#ibcon#about to write, iclass 4, count 2 2006.257.14:13:44.87#ibcon#wrote, iclass 4, count 2 2006.257.14:13:44.87#ibcon#about to read 3, iclass 4, count 2 2006.257.14:13:44.89#ibcon#read 3, iclass 4, count 2 2006.257.14:13:44.89#ibcon#about to read 4, iclass 4, count 2 2006.257.14:13:44.89#ibcon#read 4, iclass 4, count 2 2006.257.14:13:44.89#ibcon#about to read 5, iclass 4, count 2 2006.257.14:13:44.89#ibcon#read 5, iclass 4, count 2 2006.257.14:13:44.89#ibcon#about to read 6, iclass 4, count 2 2006.257.14:13:44.89#ibcon#read 6, iclass 4, count 2 2006.257.14:13:44.89#ibcon#end of sib2, iclass 4, count 2 2006.257.14:13:44.89#ibcon#*mode == 0, iclass 4, count 2 2006.257.14:13:44.89#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.14:13:44.89#ibcon#[25=AT07-04\r\n] 2006.257.14:13:44.89#ibcon#*before write, iclass 4, count 2 2006.257.14:13:44.89#ibcon#enter sib2, iclass 4, count 2 2006.257.14:13:44.89#ibcon#flushed, iclass 4, count 2 2006.257.14:13:44.89#ibcon#about to write, iclass 4, count 2 2006.257.14:13:44.89#ibcon#wrote, iclass 4, count 2 2006.257.14:13:44.89#ibcon#about to read 3, iclass 4, count 2 2006.257.14:13:44.92#ibcon#read 3, iclass 4, count 2 2006.257.14:13:44.92#ibcon#about to read 4, iclass 4, count 2 2006.257.14:13:44.92#ibcon#read 4, iclass 4, count 2 2006.257.14:13:44.92#ibcon#about to read 5, iclass 4, count 2 2006.257.14:13:44.92#ibcon#read 5, iclass 4, count 2 2006.257.14:13:44.92#ibcon#about to read 6, iclass 4, count 2 2006.257.14:13:44.92#ibcon#read 6, iclass 4, count 2 2006.257.14:13:44.92#ibcon#end of sib2, iclass 4, count 2 2006.257.14:13:44.92#ibcon#*after write, iclass 4, count 2 2006.257.14:13:44.92#ibcon#*before return 0, iclass 4, count 2 2006.257.14:13:44.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:44.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:44.92#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.14:13:44.92#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:44.92#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:45.04#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:45.04#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:45.04#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:13:45.04#ibcon#first serial, iclass 4, count 0 2006.257.14:13:45.04#ibcon#enter sib2, iclass 4, count 0 2006.257.14:13:45.04#ibcon#flushed, iclass 4, count 0 2006.257.14:13:45.04#ibcon#about to write, iclass 4, count 0 2006.257.14:13:45.04#ibcon#wrote, iclass 4, count 0 2006.257.14:13:45.04#ibcon#about to read 3, iclass 4, count 0 2006.257.14:13:45.06#ibcon#read 3, iclass 4, count 0 2006.257.14:13:45.06#ibcon#about to read 4, iclass 4, count 0 2006.257.14:13:45.06#ibcon#read 4, iclass 4, count 0 2006.257.14:13:45.06#ibcon#about to read 5, iclass 4, count 0 2006.257.14:13:45.06#ibcon#read 5, iclass 4, count 0 2006.257.14:13:45.06#ibcon#about to read 6, iclass 4, count 0 2006.257.14:13:45.06#ibcon#read 6, iclass 4, count 0 2006.257.14:13:45.06#ibcon#end of sib2, iclass 4, count 0 2006.257.14:13:45.06#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:13:45.06#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:13:45.06#ibcon#[25=USB\r\n] 2006.257.14:13:45.06#ibcon#*before write, iclass 4, count 0 2006.257.14:13:45.06#ibcon#enter sib2, iclass 4, count 0 2006.257.14:13:45.06#ibcon#flushed, iclass 4, count 0 2006.257.14:13:45.06#ibcon#about to write, iclass 4, count 0 2006.257.14:13:45.06#ibcon#wrote, iclass 4, count 0 2006.257.14:13:45.06#ibcon#about to read 3, iclass 4, count 0 2006.257.14:13:45.09#ibcon#read 3, iclass 4, count 0 2006.257.14:13:45.09#ibcon#about to read 4, iclass 4, count 0 2006.257.14:13:45.09#ibcon#read 4, iclass 4, count 0 2006.257.14:13:45.09#ibcon#about to read 5, iclass 4, count 0 2006.257.14:13:45.09#ibcon#read 5, iclass 4, count 0 2006.257.14:13:45.09#ibcon#about to read 6, iclass 4, count 0 2006.257.14:13:45.09#ibcon#read 6, iclass 4, count 0 2006.257.14:13:45.09#ibcon#end of sib2, iclass 4, count 0 2006.257.14:13:45.09#ibcon#*after write, iclass 4, count 0 2006.257.14:13:45.09#ibcon#*before return 0, iclass 4, count 0 2006.257.14:13:45.09#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:45.09#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:45.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:13:45.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:13:45.09$vck44/valo=8,884.99 2006.257.14:13:45.09#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.14:13:45.09#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.14:13:45.09#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:45.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:45.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:45.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:45.09#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:13:45.09#ibcon#first serial, iclass 6, count 0 2006.257.14:13:45.09#ibcon#enter sib2, iclass 6, count 0 2006.257.14:13:45.09#ibcon#flushed, iclass 6, count 0 2006.257.14:13:45.09#ibcon#about to write, iclass 6, count 0 2006.257.14:13:45.09#ibcon#wrote, iclass 6, count 0 2006.257.14:13:45.09#ibcon#about to read 3, iclass 6, count 0 2006.257.14:13:45.11#ibcon#read 3, iclass 6, count 0 2006.257.14:13:45.11#ibcon#about to read 4, iclass 6, count 0 2006.257.14:13:45.11#ibcon#read 4, iclass 6, count 0 2006.257.14:13:45.11#ibcon#about to read 5, iclass 6, count 0 2006.257.14:13:45.11#ibcon#read 5, iclass 6, count 0 2006.257.14:13:45.11#ibcon#about to read 6, iclass 6, count 0 2006.257.14:13:45.11#ibcon#read 6, iclass 6, count 0 2006.257.14:13:45.11#ibcon#end of sib2, iclass 6, count 0 2006.257.14:13:45.11#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:13:45.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:13:45.11#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:13:45.11#ibcon#*before write, iclass 6, count 0 2006.257.14:13:45.11#ibcon#enter sib2, iclass 6, count 0 2006.257.14:13:45.11#ibcon#flushed, iclass 6, count 0 2006.257.14:13:45.11#ibcon#about to write, iclass 6, count 0 2006.257.14:13:45.11#ibcon#wrote, iclass 6, count 0 2006.257.14:13:45.11#ibcon#about to read 3, iclass 6, count 0 2006.257.14:13:45.15#ibcon#read 3, iclass 6, count 0 2006.257.14:13:45.15#ibcon#about to read 4, iclass 6, count 0 2006.257.14:13:45.15#ibcon#read 4, iclass 6, count 0 2006.257.14:13:45.15#ibcon#about to read 5, iclass 6, count 0 2006.257.14:13:45.15#ibcon#read 5, iclass 6, count 0 2006.257.14:13:45.15#ibcon#about to read 6, iclass 6, count 0 2006.257.14:13:45.15#ibcon#read 6, iclass 6, count 0 2006.257.14:13:45.15#ibcon#end of sib2, iclass 6, count 0 2006.257.14:13:45.15#ibcon#*after write, iclass 6, count 0 2006.257.14:13:45.15#ibcon#*before return 0, iclass 6, count 0 2006.257.14:13:45.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:45.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:45.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:13:45.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:13:45.15$vck44/va=8,4 2006.257.14:13:45.15#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.14:13:45.15#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.14:13:45.15#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:45.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:13:45.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:13:45.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:13:45.21#ibcon#enter wrdev, iclass 10, count 2 2006.257.14:13:45.21#ibcon#first serial, iclass 10, count 2 2006.257.14:13:45.21#ibcon#enter sib2, iclass 10, count 2 2006.257.14:13:45.21#ibcon#flushed, iclass 10, count 2 2006.257.14:13:45.21#ibcon#about to write, iclass 10, count 2 2006.257.14:13:45.21#ibcon#wrote, iclass 10, count 2 2006.257.14:13:45.21#ibcon#about to read 3, iclass 10, count 2 2006.257.14:13:45.23#ibcon#read 3, iclass 10, count 2 2006.257.14:13:45.23#ibcon#about to read 4, iclass 10, count 2 2006.257.14:13:45.23#ibcon#read 4, iclass 10, count 2 2006.257.14:13:45.23#ibcon#about to read 5, iclass 10, count 2 2006.257.14:13:45.23#ibcon#read 5, iclass 10, count 2 2006.257.14:13:45.23#ibcon#about to read 6, iclass 10, count 2 2006.257.14:13:45.23#ibcon#read 6, iclass 10, count 2 2006.257.14:13:45.23#ibcon#end of sib2, iclass 10, count 2 2006.257.14:13:45.23#ibcon#*mode == 0, iclass 10, count 2 2006.257.14:13:45.23#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.14:13:45.23#ibcon#[25=AT08-04\r\n] 2006.257.14:13:45.23#ibcon#*before write, iclass 10, count 2 2006.257.14:13:45.23#ibcon#enter sib2, iclass 10, count 2 2006.257.14:13:45.23#ibcon#flushed, iclass 10, count 2 2006.257.14:13:45.23#ibcon#about to write, iclass 10, count 2 2006.257.14:13:45.23#ibcon#wrote, iclass 10, count 2 2006.257.14:13:45.23#ibcon#about to read 3, iclass 10, count 2 2006.257.14:13:45.26#ibcon#read 3, iclass 10, count 2 2006.257.14:13:45.26#ibcon#about to read 4, iclass 10, count 2 2006.257.14:13:45.26#ibcon#read 4, iclass 10, count 2 2006.257.14:13:45.26#ibcon#about to read 5, iclass 10, count 2 2006.257.14:13:45.26#ibcon#read 5, iclass 10, count 2 2006.257.14:13:45.26#ibcon#about to read 6, iclass 10, count 2 2006.257.14:13:45.26#ibcon#read 6, iclass 10, count 2 2006.257.14:13:45.26#ibcon#end of sib2, iclass 10, count 2 2006.257.14:13:45.26#ibcon#*after write, iclass 10, count 2 2006.257.14:13:46.05#ibcon#*before return 0, iclass 10, count 2 2006.257.14:13:46.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:13:46.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:13:46.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.14:13:46.05#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:46.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:13:46.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:13:46.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:13:46.16#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:13:46.16#ibcon#first serial, iclass 10, count 0 2006.257.14:13:46.16#ibcon#enter sib2, iclass 10, count 0 2006.257.14:13:46.16#ibcon#flushed, iclass 10, count 0 2006.257.14:13:46.16#ibcon#about to write, iclass 10, count 0 2006.257.14:13:46.16#ibcon#wrote, iclass 10, count 0 2006.257.14:13:46.16#ibcon#about to read 3, iclass 10, count 0 2006.257.14:13:46.18#ibcon#read 3, iclass 10, count 0 2006.257.14:13:46.18#ibcon#about to read 4, iclass 10, count 0 2006.257.14:13:46.18#ibcon#read 4, iclass 10, count 0 2006.257.14:13:46.18#ibcon#about to read 5, iclass 10, count 0 2006.257.14:13:46.18#ibcon#read 5, iclass 10, count 0 2006.257.14:13:46.18#ibcon#about to read 6, iclass 10, count 0 2006.257.14:13:46.18#ibcon#read 6, iclass 10, count 0 2006.257.14:13:46.18#ibcon#end of sib2, iclass 10, count 0 2006.257.14:13:46.18#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:13:46.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:13:46.18#ibcon#[25=USB\r\n] 2006.257.14:13:46.18#ibcon#*before write, iclass 10, count 0 2006.257.14:13:46.18#ibcon#enter sib2, iclass 10, count 0 2006.257.14:13:46.18#ibcon#flushed, iclass 10, count 0 2006.257.14:13:46.18#ibcon#about to write, iclass 10, count 0 2006.257.14:13:46.18#ibcon#wrote, iclass 10, count 0 2006.257.14:13:46.18#ibcon#about to read 3, iclass 10, count 0 2006.257.14:13:46.21#ibcon#read 3, iclass 10, count 0 2006.257.14:13:46.21#ibcon#about to read 4, iclass 10, count 0 2006.257.14:13:46.21#ibcon#read 4, iclass 10, count 0 2006.257.14:13:46.21#ibcon#about to read 5, iclass 10, count 0 2006.257.14:13:46.21#ibcon#read 5, iclass 10, count 0 2006.257.14:13:46.21#ibcon#about to read 6, iclass 10, count 0 2006.257.14:13:46.21#ibcon#read 6, iclass 10, count 0 2006.257.14:13:46.21#ibcon#end of sib2, iclass 10, count 0 2006.257.14:13:46.21#ibcon#*after write, iclass 10, count 0 2006.257.14:13:46.21#ibcon#*before return 0, iclass 10, count 0 2006.257.14:13:46.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:13:46.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:13:46.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:13:46.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:13:46.21$vck44/vblo=1,629.99 2006.257.14:13:46.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.14:13:46.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.14:13:46.21#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:46.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:46.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:46.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:46.21#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:13:46.21#ibcon#first serial, iclass 12, count 0 2006.257.14:13:46.21#ibcon#enter sib2, iclass 12, count 0 2006.257.14:13:46.21#ibcon#flushed, iclass 12, count 0 2006.257.14:13:46.21#ibcon#about to write, iclass 12, count 0 2006.257.14:13:46.21#ibcon#wrote, iclass 12, count 0 2006.257.14:13:46.21#ibcon#about to read 3, iclass 12, count 0 2006.257.14:13:46.23#ibcon#read 3, iclass 12, count 0 2006.257.14:13:46.23#ibcon#about to read 4, iclass 12, count 0 2006.257.14:13:46.23#ibcon#read 4, iclass 12, count 0 2006.257.14:13:46.23#ibcon#about to read 5, iclass 12, count 0 2006.257.14:13:46.23#ibcon#read 5, iclass 12, count 0 2006.257.14:13:46.23#ibcon#about to read 6, iclass 12, count 0 2006.257.14:13:46.23#ibcon#read 6, iclass 12, count 0 2006.257.14:13:46.23#ibcon#end of sib2, iclass 12, count 0 2006.257.14:13:46.23#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:13:46.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:13:46.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:13:46.23#ibcon#*before write, iclass 12, count 0 2006.257.14:13:46.23#ibcon#enter sib2, iclass 12, count 0 2006.257.14:13:46.23#ibcon#flushed, iclass 12, count 0 2006.257.14:13:46.23#ibcon#about to write, iclass 12, count 0 2006.257.14:13:46.23#ibcon#wrote, iclass 12, count 0 2006.257.14:13:46.23#ibcon#about to read 3, iclass 12, count 0 2006.257.14:13:46.27#ibcon#read 3, iclass 12, count 0 2006.257.14:13:46.27#ibcon#about to read 4, iclass 12, count 0 2006.257.14:13:46.27#ibcon#read 4, iclass 12, count 0 2006.257.14:13:46.27#ibcon#about to read 5, iclass 12, count 0 2006.257.14:13:46.27#ibcon#read 5, iclass 12, count 0 2006.257.14:13:46.27#ibcon#about to read 6, iclass 12, count 0 2006.257.14:13:46.27#ibcon#read 6, iclass 12, count 0 2006.257.14:13:46.27#ibcon#end of sib2, iclass 12, count 0 2006.257.14:13:46.27#ibcon#*after write, iclass 12, count 0 2006.257.14:13:46.27#ibcon#*before return 0, iclass 12, count 0 2006.257.14:13:46.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:46.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:13:46.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:13:46.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:13:46.27$vck44/vb=1,4 2006.257.14:13:46.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.14:13:46.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.14:13:46.27#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:46.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:46.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:46.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:46.27#ibcon#enter wrdev, iclass 14, count 2 2006.257.14:13:46.27#ibcon#first serial, iclass 14, count 2 2006.257.14:13:46.27#ibcon#enter sib2, iclass 14, count 2 2006.257.14:13:46.27#ibcon#flushed, iclass 14, count 2 2006.257.14:13:46.27#ibcon#about to write, iclass 14, count 2 2006.257.14:13:46.27#ibcon#wrote, iclass 14, count 2 2006.257.14:13:46.27#ibcon#about to read 3, iclass 14, count 2 2006.257.14:13:46.29#ibcon#read 3, iclass 14, count 2 2006.257.14:13:46.29#ibcon#about to read 4, iclass 14, count 2 2006.257.14:13:46.29#ibcon#read 4, iclass 14, count 2 2006.257.14:13:46.29#ibcon#about to read 5, iclass 14, count 2 2006.257.14:13:46.29#ibcon#read 5, iclass 14, count 2 2006.257.14:13:46.29#ibcon#about to read 6, iclass 14, count 2 2006.257.14:13:46.29#ibcon#read 6, iclass 14, count 2 2006.257.14:13:46.29#ibcon#end of sib2, iclass 14, count 2 2006.257.14:13:46.29#ibcon#*mode == 0, iclass 14, count 2 2006.257.14:13:46.29#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.14:13:46.29#ibcon#[27=AT01-04\r\n] 2006.257.14:13:46.29#ibcon#*before write, iclass 14, count 2 2006.257.14:13:46.29#ibcon#enter sib2, iclass 14, count 2 2006.257.14:13:46.29#ibcon#flushed, iclass 14, count 2 2006.257.14:13:46.29#ibcon#about to write, iclass 14, count 2 2006.257.14:13:46.29#ibcon#wrote, iclass 14, count 2 2006.257.14:13:46.29#ibcon#about to read 3, iclass 14, count 2 2006.257.14:13:46.32#ibcon#read 3, iclass 14, count 2 2006.257.14:13:46.32#ibcon#about to read 4, iclass 14, count 2 2006.257.14:13:46.32#ibcon#read 4, iclass 14, count 2 2006.257.14:13:46.32#ibcon#about to read 5, iclass 14, count 2 2006.257.14:13:46.32#ibcon#read 5, iclass 14, count 2 2006.257.14:13:46.32#ibcon#about to read 6, iclass 14, count 2 2006.257.14:13:46.32#ibcon#read 6, iclass 14, count 2 2006.257.14:13:46.32#ibcon#end of sib2, iclass 14, count 2 2006.257.14:13:46.32#ibcon#*after write, iclass 14, count 2 2006.257.14:13:46.32#ibcon#*before return 0, iclass 14, count 2 2006.257.14:13:46.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:46.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:13:46.32#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.14:13:46.32#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:46.32#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:46.44#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:46.44#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:46.44#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:13:46.44#ibcon#first serial, iclass 14, count 0 2006.257.14:13:46.44#ibcon#enter sib2, iclass 14, count 0 2006.257.14:13:46.44#ibcon#flushed, iclass 14, count 0 2006.257.14:13:46.44#ibcon#about to write, iclass 14, count 0 2006.257.14:13:46.44#ibcon#wrote, iclass 14, count 0 2006.257.14:13:46.44#ibcon#about to read 3, iclass 14, count 0 2006.257.14:13:46.46#ibcon#read 3, iclass 14, count 0 2006.257.14:13:46.46#ibcon#about to read 4, iclass 14, count 0 2006.257.14:13:46.46#ibcon#read 4, iclass 14, count 0 2006.257.14:13:46.46#ibcon#about to read 5, iclass 14, count 0 2006.257.14:13:46.46#ibcon#read 5, iclass 14, count 0 2006.257.14:13:46.46#ibcon#about to read 6, iclass 14, count 0 2006.257.14:13:46.46#ibcon#read 6, iclass 14, count 0 2006.257.14:13:46.46#ibcon#end of sib2, iclass 14, count 0 2006.257.14:13:46.46#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:13:46.46#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:13:46.46#ibcon#[27=USB\r\n] 2006.257.14:13:46.46#ibcon#*before write, iclass 14, count 0 2006.257.14:13:46.46#ibcon#enter sib2, iclass 14, count 0 2006.257.14:13:46.46#ibcon#flushed, iclass 14, count 0 2006.257.14:13:46.46#ibcon#about to write, iclass 14, count 0 2006.257.14:13:46.46#ibcon#wrote, iclass 14, count 0 2006.257.14:13:46.46#ibcon#about to read 3, iclass 14, count 0 2006.257.14:13:46.49#ibcon#read 3, iclass 14, count 0 2006.257.14:13:46.49#ibcon#about to read 4, iclass 14, count 0 2006.257.14:13:46.49#ibcon#read 4, iclass 14, count 0 2006.257.14:13:46.49#ibcon#about to read 5, iclass 14, count 0 2006.257.14:13:46.49#ibcon#read 5, iclass 14, count 0 2006.257.14:13:46.49#ibcon#about to read 6, iclass 14, count 0 2006.257.14:13:46.49#ibcon#read 6, iclass 14, count 0 2006.257.14:13:46.49#ibcon#end of sib2, iclass 14, count 0 2006.257.14:13:46.49#ibcon#*after write, iclass 14, count 0 2006.257.14:13:46.49#ibcon#*before return 0, iclass 14, count 0 2006.257.14:13:46.49#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:46.49#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:13:46.49#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:13:46.49#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:13:46.49$vck44/vblo=2,634.99 2006.257.14:13:46.49#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.14:13:46.49#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.14:13:46.49#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:46.49#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:46.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:46.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:46.49#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:13:46.49#ibcon#first serial, iclass 16, count 0 2006.257.14:13:46.49#ibcon#enter sib2, iclass 16, count 0 2006.257.14:13:46.49#ibcon#flushed, iclass 16, count 0 2006.257.14:13:46.49#ibcon#about to write, iclass 16, count 0 2006.257.14:13:46.49#ibcon#wrote, iclass 16, count 0 2006.257.14:13:46.49#ibcon#about to read 3, iclass 16, count 0 2006.257.14:13:46.51#ibcon#read 3, iclass 16, count 0 2006.257.14:13:46.51#ibcon#about to read 4, iclass 16, count 0 2006.257.14:13:46.51#ibcon#read 4, iclass 16, count 0 2006.257.14:13:46.51#ibcon#about to read 5, iclass 16, count 0 2006.257.14:13:46.51#ibcon#read 5, iclass 16, count 0 2006.257.14:13:46.51#ibcon#about to read 6, iclass 16, count 0 2006.257.14:13:46.51#ibcon#read 6, iclass 16, count 0 2006.257.14:13:46.51#ibcon#end of sib2, iclass 16, count 0 2006.257.14:13:46.51#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:13:46.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:13:46.51#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:13:46.51#ibcon#*before write, iclass 16, count 0 2006.257.14:13:46.51#ibcon#enter sib2, iclass 16, count 0 2006.257.14:13:46.51#ibcon#flushed, iclass 16, count 0 2006.257.14:13:46.51#ibcon#about to write, iclass 16, count 0 2006.257.14:13:46.51#ibcon#wrote, iclass 16, count 0 2006.257.14:13:46.51#ibcon#about to read 3, iclass 16, count 0 2006.257.14:13:46.55#ibcon#read 3, iclass 16, count 0 2006.257.14:13:46.55#ibcon#about to read 4, iclass 16, count 0 2006.257.14:13:46.55#ibcon#read 4, iclass 16, count 0 2006.257.14:13:46.55#ibcon#about to read 5, iclass 16, count 0 2006.257.14:13:46.55#ibcon#read 5, iclass 16, count 0 2006.257.14:13:46.55#ibcon#about to read 6, iclass 16, count 0 2006.257.14:13:46.55#ibcon#read 6, iclass 16, count 0 2006.257.14:13:46.55#ibcon#end of sib2, iclass 16, count 0 2006.257.14:13:46.55#ibcon#*after write, iclass 16, count 0 2006.257.14:13:46.55#ibcon#*before return 0, iclass 16, count 0 2006.257.14:13:46.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:46.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:13:46.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:13:46.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:13:46.55$vck44/vb=2,5 2006.257.14:13:46.55#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.14:13:46.55#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.14:13:46.55#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:46.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:46.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:46.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:46.61#ibcon#enter wrdev, iclass 18, count 2 2006.257.14:13:46.61#ibcon#first serial, iclass 18, count 2 2006.257.14:13:46.61#ibcon#enter sib2, iclass 18, count 2 2006.257.14:13:46.61#ibcon#flushed, iclass 18, count 2 2006.257.14:13:46.61#ibcon#about to write, iclass 18, count 2 2006.257.14:13:46.61#ibcon#wrote, iclass 18, count 2 2006.257.14:13:46.61#ibcon#about to read 3, iclass 18, count 2 2006.257.14:13:46.63#ibcon#read 3, iclass 18, count 2 2006.257.14:13:46.63#ibcon#about to read 4, iclass 18, count 2 2006.257.14:13:46.63#ibcon#read 4, iclass 18, count 2 2006.257.14:13:46.63#ibcon#about to read 5, iclass 18, count 2 2006.257.14:13:46.63#ibcon#read 5, iclass 18, count 2 2006.257.14:13:46.63#ibcon#about to read 6, iclass 18, count 2 2006.257.14:13:46.63#ibcon#read 6, iclass 18, count 2 2006.257.14:13:46.63#ibcon#end of sib2, iclass 18, count 2 2006.257.14:13:46.63#ibcon#*mode == 0, iclass 18, count 2 2006.257.14:13:46.63#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.14:13:46.63#ibcon#[27=AT02-05\r\n] 2006.257.14:13:46.63#ibcon#*before write, iclass 18, count 2 2006.257.14:13:46.63#ibcon#enter sib2, iclass 18, count 2 2006.257.14:13:46.63#ibcon#flushed, iclass 18, count 2 2006.257.14:13:46.63#ibcon#about to write, iclass 18, count 2 2006.257.14:13:46.63#ibcon#wrote, iclass 18, count 2 2006.257.14:13:46.63#ibcon#about to read 3, iclass 18, count 2 2006.257.14:13:46.66#ibcon#read 3, iclass 18, count 2 2006.257.14:13:46.66#ibcon#about to read 4, iclass 18, count 2 2006.257.14:13:46.66#ibcon#read 4, iclass 18, count 2 2006.257.14:13:46.66#ibcon#about to read 5, iclass 18, count 2 2006.257.14:13:46.66#ibcon#read 5, iclass 18, count 2 2006.257.14:13:46.66#ibcon#about to read 6, iclass 18, count 2 2006.257.14:13:46.66#ibcon#read 6, iclass 18, count 2 2006.257.14:13:46.66#ibcon#end of sib2, iclass 18, count 2 2006.257.14:13:46.66#ibcon#*after write, iclass 18, count 2 2006.257.14:13:46.66#ibcon#*before return 0, iclass 18, count 2 2006.257.14:13:46.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:46.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:13:46.66#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.14:13:46.66#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:46.66#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:46.78#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:46.78#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:46.78#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:13:46.78#ibcon#first serial, iclass 18, count 0 2006.257.14:13:46.78#ibcon#enter sib2, iclass 18, count 0 2006.257.14:13:46.78#ibcon#flushed, iclass 18, count 0 2006.257.14:13:46.78#ibcon#about to write, iclass 18, count 0 2006.257.14:13:46.78#ibcon#wrote, iclass 18, count 0 2006.257.14:13:46.78#ibcon#about to read 3, iclass 18, count 0 2006.257.14:13:46.80#ibcon#read 3, iclass 18, count 0 2006.257.14:13:46.80#ibcon#about to read 4, iclass 18, count 0 2006.257.14:13:46.80#ibcon#read 4, iclass 18, count 0 2006.257.14:13:46.80#ibcon#about to read 5, iclass 18, count 0 2006.257.14:13:46.80#ibcon#read 5, iclass 18, count 0 2006.257.14:13:46.80#ibcon#about to read 6, iclass 18, count 0 2006.257.14:13:46.80#ibcon#read 6, iclass 18, count 0 2006.257.14:13:46.80#ibcon#end of sib2, iclass 18, count 0 2006.257.14:13:46.80#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:13:46.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:13:46.80#ibcon#[27=USB\r\n] 2006.257.14:13:46.80#ibcon#*before write, iclass 18, count 0 2006.257.14:13:46.80#ibcon#enter sib2, iclass 18, count 0 2006.257.14:13:46.80#ibcon#flushed, iclass 18, count 0 2006.257.14:13:46.80#ibcon#about to write, iclass 18, count 0 2006.257.14:13:46.80#ibcon#wrote, iclass 18, count 0 2006.257.14:13:46.80#ibcon#about to read 3, iclass 18, count 0 2006.257.14:13:46.83#ibcon#read 3, iclass 18, count 0 2006.257.14:13:46.83#ibcon#about to read 4, iclass 18, count 0 2006.257.14:13:46.83#ibcon#read 4, iclass 18, count 0 2006.257.14:13:46.83#ibcon#about to read 5, iclass 18, count 0 2006.257.14:13:46.83#ibcon#read 5, iclass 18, count 0 2006.257.14:13:46.83#ibcon#about to read 6, iclass 18, count 0 2006.257.14:13:46.83#ibcon#read 6, iclass 18, count 0 2006.257.14:13:46.83#ibcon#end of sib2, iclass 18, count 0 2006.257.14:13:46.83#ibcon#*after write, iclass 18, count 0 2006.257.14:13:46.83#ibcon#*before return 0, iclass 18, count 0 2006.257.14:13:46.83#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:46.83#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:13:46.83#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:13:46.83#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:13:46.83$vck44/vblo=3,649.99 2006.257.14:13:46.83#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.14:13:46.83#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.14:13:46.83#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:46.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:46.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:46.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:46.83#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:13:46.83#ibcon#first serial, iclass 20, count 0 2006.257.14:13:46.83#ibcon#enter sib2, iclass 20, count 0 2006.257.14:13:46.83#ibcon#flushed, iclass 20, count 0 2006.257.14:13:46.83#ibcon#about to write, iclass 20, count 0 2006.257.14:13:46.83#ibcon#wrote, iclass 20, count 0 2006.257.14:13:46.83#ibcon#about to read 3, iclass 20, count 0 2006.257.14:13:46.85#ibcon#read 3, iclass 20, count 0 2006.257.14:13:46.85#ibcon#about to read 4, iclass 20, count 0 2006.257.14:13:46.85#ibcon#read 4, iclass 20, count 0 2006.257.14:13:46.85#ibcon#about to read 5, iclass 20, count 0 2006.257.14:13:46.85#ibcon#read 5, iclass 20, count 0 2006.257.14:13:46.85#ibcon#about to read 6, iclass 20, count 0 2006.257.14:13:46.85#ibcon#read 6, iclass 20, count 0 2006.257.14:13:46.85#ibcon#end of sib2, iclass 20, count 0 2006.257.14:13:46.85#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:13:46.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:13:46.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:13:46.85#ibcon#*before write, iclass 20, count 0 2006.257.14:13:46.85#ibcon#enter sib2, iclass 20, count 0 2006.257.14:13:46.85#ibcon#flushed, iclass 20, count 0 2006.257.14:13:46.85#ibcon#about to write, iclass 20, count 0 2006.257.14:13:46.85#ibcon#wrote, iclass 20, count 0 2006.257.14:13:46.85#ibcon#about to read 3, iclass 20, count 0 2006.257.14:13:46.89#ibcon#read 3, iclass 20, count 0 2006.257.14:13:46.89#ibcon#about to read 4, iclass 20, count 0 2006.257.14:13:46.89#ibcon#read 4, iclass 20, count 0 2006.257.14:13:46.89#ibcon#about to read 5, iclass 20, count 0 2006.257.14:13:46.89#ibcon#read 5, iclass 20, count 0 2006.257.14:13:46.89#ibcon#about to read 6, iclass 20, count 0 2006.257.14:13:46.89#ibcon#read 6, iclass 20, count 0 2006.257.14:13:46.89#ibcon#end of sib2, iclass 20, count 0 2006.257.14:13:46.89#ibcon#*after write, iclass 20, count 0 2006.257.14:13:46.89#ibcon#*before return 0, iclass 20, count 0 2006.257.14:13:46.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:46.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:13:46.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:13:46.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:13:46.89$vck44/vb=3,4 2006.257.14:13:46.89#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.14:13:46.89#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.14:13:46.89#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:46.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:46.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:46.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:46.95#ibcon#enter wrdev, iclass 22, count 2 2006.257.14:13:46.95#ibcon#first serial, iclass 22, count 2 2006.257.14:13:46.95#ibcon#enter sib2, iclass 22, count 2 2006.257.14:13:46.95#ibcon#flushed, iclass 22, count 2 2006.257.14:13:46.95#ibcon#about to write, iclass 22, count 2 2006.257.14:13:46.95#ibcon#wrote, iclass 22, count 2 2006.257.14:13:46.95#ibcon#about to read 3, iclass 22, count 2 2006.257.14:13:46.97#ibcon#read 3, iclass 22, count 2 2006.257.14:13:46.97#ibcon#about to read 4, iclass 22, count 2 2006.257.14:13:46.97#ibcon#read 4, iclass 22, count 2 2006.257.14:13:46.97#ibcon#about to read 5, iclass 22, count 2 2006.257.14:13:46.97#ibcon#read 5, iclass 22, count 2 2006.257.14:13:46.97#ibcon#about to read 6, iclass 22, count 2 2006.257.14:13:46.97#ibcon#read 6, iclass 22, count 2 2006.257.14:13:46.97#ibcon#end of sib2, iclass 22, count 2 2006.257.14:13:46.97#ibcon#*mode == 0, iclass 22, count 2 2006.257.14:13:46.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.14:13:46.97#ibcon#[27=AT03-04\r\n] 2006.257.14:13:46.97#ibcon#*before write, iclass 22, count 2 2006.257.14:13:46.97#ibcon#enter sib2, iclass 22, count 2 2006.257.14:13:46.97#ibcon#flushed, iclass 22, count 2 2006.257.14:13:46.97#ibcon#about to write, iclass 22, count 2 2006.257.14:13:46.97#ibcon#wrote, iclass 22, count 2 2006.257.14:13:46.97#ibcon#about to read 3, iclass 22, count 2 2006.257.14:13:47.00#ibcon#read 3, iclass 22, count 2 2006.257.14:13:47.00#ibcon#about to read 4, iclass 22, count 2 2006.257.14:13:47.00#ibcon#read 4, iclass 22, count 2 2006.257.14:13:47.00#ibcon#about to read 5, iclass 22, count 2 2006.257.14:13:47.00#ibcon#read 5, iclass 22, count 2 2006.257.14:13:47.00#ibcon#about to read 6, iclass 22, count 2 2006.257.14:13:47.00#ibcon#read 6, iclass 22, count 2 2006.257.14:13:47.00#ibcon#end of sib2, iclass 22, count 2 2006.257.14:13:47.00#ibcon#*after write, iclass 22, count 2 2006.257.14:13:47.00#ibcon#*before return 0, iclass 22, count 2 2006.257.14:13:47.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:47.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:13:47.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.14:13:47.00#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:47.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:47.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:47.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:47.12#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:13:47.12#ibcon#first serial, iclass 22, count 0 2006.257.14:13:47.12#ibcon#enter sib2, iclass 22, count 0 2006.257.14:13:47.12#ibcon#flushed, iclass 22, count 0 2006.257.14:13:47.12#ibcon#about to write, iclass 22, count 0 2006.257.14:13:47.12#ibcon#wrote, iclass 22, count 0 2006.257.14:13:47.12#ibcon#about to read 3, iclass 22, count 0 2006.257.14:13:47.14#ibcon#read 3, iclass 22, count 0 2006.257.14:13:47.14#ibcon#about to read 4, iclass 22, count 0 2006.257.14:13:47.14#ibcon#read 4, iclass 22, count 0 2006.257.14:13:47.14#ibcon#about to read 5, iclass 22, count 0 2006.257.14:13:47.14#ibcon#read 5, iclass 22, count 0 2006.257.14:13:47.14#ibcon#about to read 6, iclass 22, count 0 2006.257.14:13:47.14#ibcon#read 6, iclass 22, count 0 2006.257.14:13:47.14#ibcon#end of sib2, iclass 22, count 0 2006.257.14:13:47.14#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:13:47.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:13:47.14#ibcon#[27=USB\r\n] 2006.257.14:13:47.14#ibcon#*before write, iclass 22, count 0 2006.257.14:13:47.14#ibcon#enter sib2, iclass 22, count 0 2006.257.14:13:47.14#ibcon#flushed, iclass 22, count 0 2006.257.14:13:47.14#ibcon#about to write, iclass 22, count 0 2006.257.14:13:47.14#ibcon#wrote, iclass 22, count 0 2006.257.14:13:47.14#ibcon#about to read 3, iclass 22, count 0 2006.257.14:13:47.17#ibcon#read 3, iclass 22, count 0 2006.257.14:13:47.17#ibcon#about to read 4, iclass 22, count 0 2006.257.14:13:47.17#ibcon#read 4, iclass 22, count 0 2006.257.14:13:47.17#ibcon#about to read 5, iclass 22, count 0 2006.257.14:13:47.17#ibcon#read 5, iclass 22, count 0 2006.257.14:13:47.17#ibcon#about to read 6, iclass 22, count 0 2006.257.14:13:47.17#ibcon#read 6, iclass 22, count 0 2006.257.14:13:47.17#ibcon#end of sib2, iclass 22, count 0 2006.257.14:13:47.17#ibcon#*after write, iclass 22, count 0 2006.257.14:13:47.17#ibcon#*before return 0, iclass 22, count 0 2006.257.14:13:47.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:47.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:13:47.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:13:47.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:13:47.17$vck44/vblo=4,679.99 2006.257.14:13:47.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.14:13:47.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.14:13:47.17#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:47.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:47.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:47.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:47.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:13:47.17#ibcon#first serial, iclass 24, count 0 2006.257.14:13:47.17#ibcon#enter sib2, iclass 24, count 0 2006.257.14:13:47.17#ibcon#flushed, iclass 24, count 0 2006.257.14:13:47.17#ibcon#about to write, iclass 24, count 0 2006.257.14:13:47.17#ibcon#wrote, iclass 24, count 0 2006.257.14:13:47.17#ibcon#about to read 3, iclass 24, count 0 2006.257.14:13:47.19#ibcon#read 3, iclass 24, count 0 2006.257.14:13:47.19#ibcon#about to read 4, iclass 24, count 0 2006.257.14:13:47.19#ibcon#read 4, iclass 24, count 0 2006.257.14:13:47.19#ibcon#about to read 5, iclass 24, count 0 2006.257.14:13:47.19#ibcon#read 5, iclass 24, count 0 2006.257.14:13:47.19#ibcon#about to read 6, iclass 24, count 0 2006.257.14:13:47.19#ibcon#read 6, iclass 24, count 0 2006.257.14:13:47.19#ibcon#end of sib2, iclass 24, count 0 2006.257.14:13:47.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:13:47.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:13:47.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:13:47.19#ibcon#*before write, iclass 24, count 0 2006.257.14:13:47.19#ibcon#enter sib2, iclass 24, count 0 2006.257.14:13:47.19#ibcon#flushed, iclass 24, count 0 2006.257.14:13:47.19#ibcon#about to write, iclass 24, count 0 2006.257.14:13:47.19#ibcon#wrote, iclass 24, count 0 2006.257.14:13:47.19#ibcon#about to read 3, iclass 24, count 0 2006.257.14:13:47.23#ibcon#read 3, iclass 24, count 0 2006.257.14:13:47.23#ibcon#about to read 4, iclass 24, count 0 2006.257.14:13:47.23#ibcon#read 4, iclass 24, count 0 2006.257.14:13:47.23#ibcon#about to read 5, iclass 24, count 0 2006.257.14:13:48.02#ibcon#read 5, iclass 24, count 0 2006.257.14:13:48.02#ibcon#about to read 6, iclass 24, count 0 2006.257.14:13:48.02#ibcon#read 6, iclass 24, count 0 2006.257.14:13:48.02#ibcon#end of sib2, iclass 24, count 0 2006.257.14:13:48.02#ibcon#*after write, iclass 24, count 0 2006.257.14:13:48.03#ibcon#*before return 0, iclass 24, count 0 2006.257.14:13:48.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:48.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:13:48.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:13:48.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:13:48.03$vck44/vb=4,5 2006.257.14:13:48.03#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.14:13:48.03#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.14:13:48.03#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:48.03#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:48.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:48.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:48.03#ibcon#enter wrdev, iclass 26, count 2 2006.257.14:13:48.03#ibcon#first serial, iclass 26, count 2 2006.257.14:13:48.03#ibcon#enter sib2, iclass 26, count 2 2006.257.14:13:48.03#ibcon#flushed, iclass 26, count 2 2006.257.14:13:48.03#ibcon#about to write, iclass 26, count 2 2006.257.14:13:48.03#ibcon#wrote, iclass 26, count 2 2006.257.14:13:48.03#ibcon#about to read 3, iclass 26, count 2 2006.257.14:13:48.05#ibcon#read 3, iclass 26, count 2 2006.257.14:13:48.05#ibcon#about to read 4, iclass 26, count 2 2006.257.14:13:48.05#ibcon#read 4, iclass 26, count 2 2006.257.14:13:48.05#ibcon#about to read 5, iclass 26, count 2 2006.257.14:13:48.05#ibcon#read 5, iclass 26, count 2 2006.257.14:13:48.05#ibcon#about to read 6, iclass 26, count 2 2006.257.14:13:48.05#ibcon#read 6, iclass 26, count 2 2006.257.14:13:48.05#ibcon#end of sib2, iclass 26, count 2 2006.257.14:13:48.05#ibcon#*mode == 0, iclass 26, count 2 2006.257.14:13:48.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.14:13:48.05#ibcon#[27=AT04-05\r\n] 2006.257.14:13:48.05#ibcon#*before write, iclass 26, count 2 2006.257.14:13:48.05#ibcon#enter sib2, iclass 26, count 2 2006.257.14:13:48.05#ibcon#flushed, iclass 26, count 2 2006.257.14:13:48.05#ibcon#about to write, iclass 26, count 2 2006.257.14:13:48.05#ibcon#wrote, iclass 26, count 2 2006.257.14:13:48.05#ibcon#about to read 3, iclass 26, count 2 2006.257.14:13:48.08#ibcon#read 3, iclass 26, count 2 2006.257.14:13:48.08#ibcon#about to read 4, iclass 26, count 2 2006.257.14:13:48.08#ibcon#read 4, iclass 26, count 2 2006.257.14:13:48.08#ibcon#about to read 5, iclass 26, count 2 2006.257.14:13:48.08#ibcon#read 5, iclass 26, count 2 2006.257.14:13:48.08#ibcon#about to read 6, iclass 26, count 2 2006.257.14:13:48.08#ibcon#read 6, iclass 26, count 2 2006.257.14:13:48.08#ibcon#end of sib2, iclass 26, count 2 2006.257.14:13:48.08#ibcon#*after write, iclass 26, count 2 2006.257.14:13:48.08#ibcon#*before return 0, iclass 26, count 2 2006.257.14:13:48.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:48.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:13:48.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.14:13:48.08#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:48.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:48.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:48.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:48.20#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:13:48.20#ibcon#first serial, iclass 26, count 0 2006.257.14:13:48.20#ibcon#enter sib2, iclass 26, count 0 2006.257.14:13:48.20#ibcon#flushed, iclass 26, count 0 2006.257.14:13:48.20#ibcon#about to write, iclass 26, count 0 2006.257.14:13:48.20#ibcon#wrote, iclass 26, count 0 2006.257.14:13:48.20#ibcon#about to read 3, iclass 26, count 0 2006.257.14:13:48.22#ibcon#read 3, iclass 26, count 0 2006.257.14:13:48.22#ibcon#about to read 4, iclass 26, count 0 2006.257.14:13:48.22#ibcon#read 4, iclass 26, count 0 2006.257.14:13:48.22#ibcon#about to read 5, iclass 26, count 0 2006.257.14:13:48.22#ibcon#read 5, iclass 26, count 0 2006.257.14:13:48.22#ibcon#about to read 6, iclass 26, count 0 2006.257.14:13:48.22#ibcon#read 6, iclass 26, count 0 2006.257.14:13:48.22#ibcon#end of sib2, iclass 26, count 0 2006.257.14:13:48.22#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:13:48.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:13:48.22#ibcon#[27=USB\r\n] 2006.257.14:13:48.22#ibcon#*before write, iclass 26, count 0 2006.257.14:13:48.22#ibcon#enter sib2, iclass 26, count 0 2006.257.14:13:48.22#ibcon#flushed, iclass 26, count 0 2006.257.14:13:48.22#ibcon#about to write, iclass 26, count 0 2006.257.14:13:48.22#ibcon#wrote, iclass 26, count 0 2006.257.14:13:48.22#ibcon#about to read 3, iclass 26, count 0 2006.257.14:13:48.25#ibcon#read 3, iclass 26, count 0 2006.257.14:13:48.25#ibcon#about to read 4, iclass 26, count 0 2006.257.14:13:48.25#ibcon#read 4, iclass 26, count 0 2006.257.14:13:48.25#ibcon#about to read 5, iclass 26, count 0 2006.257.14:13:48.25#ibcon#read 5, iclass 26, count 0 2006.257.14:13:48.25#ibcon#about to read 6, iclass 26, count 0 2006.257.14:13:48.25#ibcon#read 6, iclass 26, count 0 2006.257.14:13:48.25#ibcon#end of sib2, iclass 26, count 0 2006.257.14:13:48.25#ibcon#*after write, iclass 26, count 0 2006.257.14:13:48.25#ibcon#*before return 0, iclass 26, count 0 2006.257.14:13:48.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:48.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:13:48.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:13:48.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:13:48.25$vck44/vblo=5,709.99 2006.257.14:13:48.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.14:13:48.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.14:13:48.25#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:48.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:48.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:48.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:48.25#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:13:48.25#ibcon#first serial, iclass 28, count 0 2006.257.14:13:48.25#ibcon#enter sib2, iclass 28, count 0 2006.257.14:13:48.25#ibcon#flushed, iclass 28, count 0 2006.257.14:13:48.25#ibcon#about to write, iclass 28, count 0 2006.257.14:13:48.25#ibcon#wrote, iclass 28, count 0 2006.257.14:13:48.25#ibcon#about to read 3, iclass 28, count 0 2006.257.14:13:48.27#ibcon#read 3, iclass 28, count 0 2006.257.14:13:48.27#ibcon#about to read 4, iclass 28, count 0 2006.257.14:13:48.27#ibcon#read 4, iclass 28, count 0 2006.257.14:13:48.27#ibcon#about to read 5, iclass 28, count 0 2006.257.14:13:48.27#ibcon#read 5, iclass 28, count 0 2006.257.14:13:48.27#ibcon#about to read 6, iclass 28, count 0 2006.257.14:13:48.27#ibcon#read 6, iclass 28, count 0 2006.257.14:13:48.27#ibcon#end of sib2, iclass 28, count 0 2006.257.14:13:48.27#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:13:48.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:13:48.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:13:48.27#ibcon#*before write, iclass 28, count 0 2006.257.14:13:48.27#ibcon#enter sib2, iclass 28, count 0 2006.257.14:13:48.27#ibcon#flushed, iclass 28, count 0 2006.257.14:13:48.27#ibcon#about to write, iclass 28, count 0 2006.257.14:13:48.27#ibcon#wrote, iclass 28, count 0 2006.257.14:13:48.27#ibcon#about to read 3, iclass 28, count 0 2006.257.14:13:48.31#ibcon#read 3, iclass 28, count 0 2006.257.14:13:48.31#ibcon#about to read 4, iclass 28, count 0 2006.257.14:13:48.31#ibcon#read 4, iclass 28, count 0 2006.257.14:13:48.31#ibcon#about to read 5, iclass 28, count 0 2006.257.14:13:48.31#ibcon#read 5, iclass 28, count 0 2006.257.14:13:48.31#ibcon#about to read 6, iclass 28, count 0 2006.257.14:13:48.31#ibcon#read 6, iclass 28, count 0 2006.257.14:13:48.31#ibcon#end of sib2, iclass 28, count 0 2006.257.14:13:48.31#ibcon#*after write, iclass 28, count 0 2006.257.14:13:48.31#ibcon#*before return 0, iclass 28, count 0 2006.257.14:13:48.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:48.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:13:48.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:13:48.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:13:48.31$vck44/vb=5,4 2006.257.14:13:48.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.14:13:48.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.14:13:48.31#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:48.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:48.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:48.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:48.37#ibcon#enter wrdev, iclass 30, count 2 2006.257.14:13:48.37#ibcon#first serial, iclass 30, count 2 2006.257.14:13:48.37#ibcon#enter sib2, iclass 30, count 2 2006.257.14:13:48.37#ibcon#flushed, iclass 30, count 2 2006.257.14:13:48.37#ibcon#about to write, iclass 30, count 2 2006.257.14:13:48.37#ibcon#wrote, iclass 30, count 2 2006.257.14:13:48.37#ibcon#about to read 3, iclass 30, count 2 2006.257.14:13:48.39#ibcon#read 3, iclass 30, count 2 2006.257.14:13:48.39#ibcon#about to read 4, iclass 30, count 2 2006.257.14:13:48.39#ibcon#read 4, iclass 30, count 2 2006.257.14:13:48.39#ibcon#about to read 5, iclass 30, count 2 2006.257.14:13:48.39#ibcon#read 5, iclass 30, count 2 2006.257.14:13:48.39#ibcon#about to read 6, iclass 30, count 2 2006.257.14:13:48.39#ibcon#read 6, iclass 30, count 2 2006.257.14:13:48.39#ibcon#end of sib2, iclass 30, count 2 2006.257.14:13:48.39#ibcon#*mode == 0, iclass 30, count 2 2006.257.14:13:48.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.14:13:48.39#ibcon#[27=AT05-04\r\n] 2006.257.14:13:48.39#ibcon#*before write, iclass 30, count 2 2006.257.14:13:48.39#ibcon#enter sib2, iclass 30, count 2 2006.257.14:13:48.39#ibcon#flushed, iclass 30, count 2 2006.257.14:13:48.39#ibcon#about to write, iclass 30, count 2 2006.257.14:13:48.39#ibcon#wrote, iclass 30, count 2 2006.257.14:13:48.39#ibcon#about to read 3, iclass 30, count 2 2006.257.14:13:48.42#ibcon#read 3, iclass 30, count 2 2006.257.14:13:48.42#ibcon#about to read 4, iclass 30, count 2 2006.257.14:13:48.42#ibcon#read 4, iclass 30, count 2 2006.257.14:13:48.42#ibcon#about to read 5, iclass 30, count 2 2006.257.14:13:48.42#ibcon#read 5, iclass 30, count 2 2006.257.14:13:48.42#ibcon#about to read 6, iclass 30, count 2 2006.257.14:13:48.42#ibcon#read 6, iclass 30, count 2 2006.257.14:13:48.42#ibcon#end of sib2, iclass 30, count 2 2006.257.14:13:48.42#ibcon#*after write, iclass 30, count 2 2006.257.14:13:48.42#ibcon#*before return 0, iclass 30, count 2 2006.257.14:13:48.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:48.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:13:48.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.14:13:48.42#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:48.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:48.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:48.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:48.54#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:13:48.54#ibcon#first serial, iclass 30, count 0 2006.257.14:13:48.54#ibcon#enter sib2, iclass 30, count 0 2006.257.14:13:48.54#ibcon#flushed, iclass 30, count 0 2006.257.14:13:48.54#ibcon#about to write, iclass 30, count 0 2006.257.14:13:48.54#ibcon#wrote, iclass 30, count 0 2006.257.14:13:48.54#ibcon#about to read 3, iclass 30, count 0 2006.257.14:13:48.56#ibcon#read 3, iclass 30, count 0 2006.257.14:13:48.56#ibcon#about to read 4, iclass 30, count 0 2006.257.14:13:48.56#ibcon#read 4, iclass 30, count 0 2006.257.14:13:48.56#ibcon#about to read 5, iclass 30, count 0 2006.257.14:13:48.56#ibcon#read 5, iclass 30, count 0 2006.257.14:13:48.56#ibcon#about to read 6, iclass 30, count 0 2006.257.14:13:48.56#ibcon#read 6, iclass 30, count 0 2006.257.14:13:48.56#ibcon#end of sib2, iclass 30, count 0 2006.257.14:13:48.56#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:13:48.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:13:48.56#ibcon#[27=USB\r\n] 2006.257.14:13:48.56#ibcon#*before write, iclass 30, count 0 2006.257.14:13:48.56#ibcon#enter sib2, iclass 30, count 0 2006.257.14:13:48.56#ibcon#flushed, iclass 30, count 0 2006.257.14:13:48.56#ibcon#about to write, iclass 30, count 0 2006.257.14:13:48.56#ibcon#wrote, iclass 30, count 0 2006.257.14:13:48.56#ibcon#about to read 3, iclass 30, count 0 2006.257.14:13:48.59#ibcon#read 3, iclass 30, count 0 2006.257.14:13:48.59#ibcon#about to read 4, iclass 30, count 0 2006.257.14:13:48.59#ibcon#read 4, iclass 30, count 0 2006.257.14:13:48.59#ibcon#about to read 5, iclass 30, count 0 2006.257.14:13:48.59#ibcon#read 5, iclass 30, count 0 2006.257.14:13:48.59#ibcon#about to read 6, iclass 30, count 0 2006.257.14:13:48.59#ibcon#read 6, iclass 30, count 0 2006.257.14:13:48.59#ibcon#end of sib2, iclass 30, count 0 2006.257.14:13:48.59#ibcon#*after write, iclass 30, count 0 2006.257.14:13:48.59#ibcon#*before return 0, iclass 30, count 0 2006.257.14:13:48.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:48.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:13:48.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:13:48.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:13:48.59$vck44/vblo=6,719.99 2006.257.14:13:48.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.14:13:48.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.14:13:48.59#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:48.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:13:48.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:13:48.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:13:48.59#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:13:48.59#ibcon#first serial, iclass 32, count 0 2006.257.14:13:48.59#ibcon#enter sib2, iclass 32, count 0 2006.257.14:13:48.59#ibcon#flushed, iclass 32, count 0 2006.257.14:13:48.59#ibcon#about to write, iclass 32, count 0 2006.257.14:13:48.59#ibcon#wrote, iclass 32, count 0 2006.257.14:13:48.59#ibcon#about to read 3, iclass 32, count 0 2006.257.14:13:48.61#ibcon#read 3, iclass 32, count 0 2006.257.14:13:48.61#ibcon#about to read 4, iclass 32, count 0 2006.257.14:13:48.61#ibcon#read 4, iclass 32, count 0 2006.257.14:13:48.61#ibcon#about to read 5, iclass 32, count 0 2006.257.14:13:48.61#ibcon#read 5, iclass 32, count 0 2006.257.14:13:48.61#ibcon#about to read 6, iclass 32, count 0 2006.257.14:13:48.61#ibcon#read 6, iclass 32, count 0 2006.257.14:13:48.61#ibcon#end of sib2, iclass 32, count 0 2006.257.14:13:48.61#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:13:48.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:13:48.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:13:48.61#ibcon#*before write, iclass 32, count 0 2006.257.14:13:48.61#ibcon#enter sib2, iclass 32, count 0 2006.257.14:13:48.61#ibcon#flushed, iclass 32, count 0 2006.257.14:13:48.61#ibcon#about to write, iclass 32, count 0 2006.257.14:13:48.61#ibcon#wrote, iclass 32, count 0 2006.257.14:13:48.61#ibcon#about to read 3, iclass 32, count 0 2006.257.14:13:48.65#ibcon#read 3, iclass 32, count 0 2006.257.14:13:48.65#ibcon#about to read 4, iclass 32, count 0 2006.257.14:13:48.65#ibcon#read 4, iclass 32, count 0 2006.257.14:13:48.65#ibcon#about to read 5, iclass 32, count 0 2006.257.14:13:48.65#ibcon#read 5, iclass 32, count 0 2006.257.14:13:48.65#ibcon#about to read 6, iclass 32, count 0 2006.257.14:13:48.65#ibcon#read 6, iclass 32, count 0 2006.257.14:13:48.65#ibcon#end of sib2, iclass 32, count 0 2006.257.14:13:48.65#ibcon#*after write, iclass 32, count 0 2006.257.14:13:48.65#ibcon#*before return 0, iclass 32, count 0 2006.257.14:13:48.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:13:48.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:13:48.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:13:48.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:13:48.65$vck44/vb=6,4 2006.257.14:13:48.65#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.14:13:48.65#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.14:13:48.65#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:48.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:13:48.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:13:48.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:13:48.71#ibcon#enter wrdev, iclass 34, count 2 2006.257.14:13:48.71#ibcon#first serial, iclass 34, count 2 2006.257.14:13:48.71#ibcon#enter sib2, iclass 34, count 2 2006.257.14:13:48.71#ibcon#flushed, iclass 34, count 2 2006.257.14:13:48.71#ibcon#about to write, iclass 34, count 2 2006.257.14:13:48.71#ibcon#wrote, iclass 34, count 2 2006.257.14:13:48.71#ibcon#about to read 3, iclass 34, count 2 2006.257.14:13:48.73#ibcon#read 3, iclass 34, count 2 2006.257.14:13:48.73#ibcon#about to read 4, iclass 34, count 2 2006.257.14:13:48.73#ibcon#read 4, iclass 34, count 2 2006.257.14:13:48.73#ibcon#about to read 5, iclass 34, count 2 2006.257.14:13:48.73#ibcon#read 5, iclass 34, count 2 2006.257.14:13:48.73#ibcon#about to read 6, iclass 34, count 2 2006.257.14:13:48.73#ibcon#read 6, iclass 34, count 2 2006.257.14:13:48.73#ibcon#end of sib2, iclass 34, count 2 2006.257.14:13:48.73#ibcon#*mode == 0, iclass 34, count 2 2006.257.14:13:48.73#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.14:13:48.73#ibcon#[27=AT06-04\r\n] 2006.257.14:13:48.73#ibcon#*before write, iclass 34, count 2 2006.257.14:13:48.73#ibcon#enter sib2, iclass 34, count 2 2006.257.14:13:48.73#ibcon#flushed, iclass 34, count 2 2006.257.14:13:48.73#ibcon#about to write, iclass 34, count 2 2006.257.14:13:48.73#ibcon#wrote, iclass 34, count 2 2006.257.14:13:48.73#ibcon#about to read 3, iclass 34, count 2 2006.257.14:13:48.76#ibcon#read 3, iclass 34, count 2 2006.257.14:13:48.76#ibcon#about to read 4, iclass 34, count 2 2006.257.14:13:48.76#ibcon#read 4, iclass 34, count 2 2006.257.14:13:48.76#ibcon#about to read 5, iclass 34, count 2 2006.257.14:13:48.76#ibcon#read 5, iclass 34, count 2 2006.257.14:13:48.76#ibcon#about to read 6, iclass 34, count 2 2006.257.14:13:48.76#ibcon#read 6, iclass 34, count 2 2006.257.14:13:48.76#ibcon#end of sib2, iclass 34, count 2 2006.257.14:13:48.76#ibcon#*after write, iclass 34, count 2 2006.257.14:13:48.76#ibcon#*before return 0, iclass 34, count 2 2006.257.14:13:48.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:13:48.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:13:48.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.14:13:48.76#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:48.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:13:48.88#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:13:48.88#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:13:48.88#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:13:48.88#ibcon#first serial, iclass 34, count 0 2006.257.14:13:48.88#ibcon#enter sib2, iclass 34, count 0 2006.257.14:13:48.88#ibcon#flushed, iclass 34, count 0 2006.257.14:13:48.88#ibcon#about to write, iclass 34, count 0 2006.257.14:13:48.88#ibcon#wrote, iclass 34, count 0 2006.257.14:13:48.88#ibcon#about to read 3, iclass 34, count 0 2006.257.14:13:48.90#ibcon#read 3, iclass 34, count 0 2006.257.14:13:48.90#ibcon#about to read 4, iclass 34, count 0 2006.257.14:13:48.90#ibcon#read 4, iclass 34, count 0 2006.257.14:13:48.90#ibcon#about to read 5, iclass 34, count 0 2006.257.14:13:48.90#ibcon#read 5, iclass 34, count 0 2006.257.14:13:48.90#ibcon#about to read 6, iclass 34, count 0 2006.257.14:13:48.90#ibcon#read 6, iclass 34, count 0 2006.257.14:13:48.90#ibcon#end of sib2, iclass 34, count 0 2006.257.14:13:48.90#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:13:48.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:13:48.90#ibcon#[27=USB\r\n] 2006.257.14:13:48.90#ibcon#*before write, iclass 34, count 0 2006.257.14:13:48.90#ibcon#enter sib2, iclass 34, count 0 2006.257.14:13:48.90#ibcon#flushed, iclass 34, count 0 2006.257.14:13:48.90#ibcon#about to write, iclass 34, count 0 2006.257.14:13:48.90#ibcon#wrote, iclass 34, count 0 2006.257.14:13:48.90#ibcon#about to read 3, iclass 34, count 0 2006.257.14:13:48.93#ibcon#read 3, iclass 34, count 0 2006.257.14:13:48.93#ibcon#about to read 4, iclass 34, count 0 2006.257.14:13:48.93#ibcon#read 4, iclass 34, count 0 2006.257.14:13:48.93#ibcon#about to read 5, iclass 34, count 0 2006.257.14:13:48.93#ibcon#read 5, iclass 34, count 0 2006.257.14:13:48.93#ibcon#about to read 6, iclass 34, count 0 2006.257.14:13:48.93#ibcon#read 6, iclass 34, count 0 2006.257.14:13:48.93#ibcon#end of sib2, iclass 34, count 0 2006.257.14:13:48.93#ibcon#*after write, iclass 34, count 0 2006.257.14:13:48.93#ibcon#*before return 0, iclass 34, count 0 2006.257.14:13:48.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:13:48.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:13:48.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:13:48.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:13:48.93$vck44/vblo=7,734.99 2006.257.14:13:48.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.14:13:48.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.14:13:48.93#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:48.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:13:48.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:13:48.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:13:48.93#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:13:48.93#ibcon#first serial, iclass 36, count 0 2006.257.14:13:48.93#ibcon#enter sib2, iclass 36, count 0 2006.257.14:13:48.93#ibcon#flushed, iclass 36, count 0 2006.257.14:13:48.93#ibcon#about to write, iclass 36, count 0 2006.257.14:13:48.93#ibcon#wrote, iclass 36, count 0 2006.257.14:13:48.93#ibcon#about to read 3, iclass 36, count 0 2006.257.14:13:48.95#ibcon#read 3, iclass 36, count 0 2006.257.14:13:48.95#ibcon#about to read 4, iclass 36, count 0 2006.257.14:13:48.95#ibcon#read 4, iclass 36, count 0 2006.257.14:13:48.95#ibcon#about to read 5, iclass 36, count 0 2006.257.14:13:48.95#ibcon#read 5, iclass 36, count 0 2006.257.14:13:48.95#ibcon#about to read 6, iclass 36, count 0 2006.257.14:13:48.95#ibcon#read 6, iclass 36, count 0 2006.257.14:13:48.95#ibcon#end of sib2, iclass 36, count 0 2006.257.14:13:48.95#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:13:48.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:13:48.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:13:48.95#ibcon#*before write, iclass 36, count 0 2006.257.14:13:48.95#ibcon#enter sib2, iclass 36, count 0 2006.257.14:13:48.95#ibcon#flushed, iclass 36, count 0 2006.257.14:13:48.95#ibcon#about to write, iclass 36, count 0 2006.257.14:13:48.95#ibcon#wrote, iclass 36, count 0 2006.257.14:13:48.95#ibcon#about to read 3, iclass 36, count 0 2006.257.14:13:48.99#ibcon#read 3, iclass 36, count 0 2006.257.14:13:48.99#ibcon#about to read 4, iclass 36, count 0 2006.257.14:13:48.99#ibcon#read 4, iclass 36, count 0 2006.257.14:13:48.99#ibcon#about to read 5, iclass 36, count 0 2006.257.14:13:48.99#ibcon#read 5, iclass 36, count 0 2006.257.14:13:48.99#ibcon#about to read 6, iclass 36, count 0 2006.257.14:13:48.99#ibcon#read 6, iclass 36, count 0 2006.257.14:13:48.99#ibcon#end of sib2, iclass 36, count 0 2006.257.14:13:48.99#ibcon#*after write, iclass 36, count 0 2006.257.14:13:48.99#ibcon#*before return 0, iclass 36, count 0 2006.257.14:13:48.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:13:48.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:13:48.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:13:48.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:13:48.99$vck44/vb=7,4 2006.257.14:13:48.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.14:13:48.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.14:13:48.99#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:48.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:49.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:49.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:49.05#ibcon#enter wrdev, iclass 38, count 2 2006.257.14:13:49.05#ibcon#first serial, iclass 38, count 2 2006.257.14:13:49.05#ibcon#enter sib2, iclass 38, count 2 2006.257.14:13:49.05#ibcon#flushed, iclass 38, count 2 2006.257.14:13:49.05#ibcon#about to write, iclass 38, count 2 2006.257.14:13:49.05#ibcon#wrote, iclass 38, count 2 2006.257.14:13:49.05#ibcon#about to read 3, iclass 38, count 2 2006.257.14:13:49.07#ibcon#read 3, iclass 38, count 2 2006.257.14:13:49.07#ibcon#about to read 4, iclass 38, count 2 2006.257.14:13:49.07#ibcon#read 4, iclass 38, count 2 2006.257.14:13:49.07#ibcon#about to read 5, iclass 38, count 2 2006.257.14:13:49.07#ibcon#read 5, iclass 38, count 2 2006.257.14:13:49.07#ibcon#about to read 6, iclass 38, count 2 2006.257.14:13:49.07#ibcon#read 6, iclass 38, count 2 2006.257.14:13:49.07#ibcon#end of sib2, iclass 38, count 2 2006.257.14:13:49.07#ibcon#*mode == 0, iclass 38, count 2 2006.257.14:13:49.07#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.14:13:49.07#ibcon#[27=AT07-04\r\n] 2006.257.14:13:49.07#ibcon#*before write, iclass 38, count 2 2006.257.14:13:49.07#ibcon#enter sib2, iclass 38, count 2 2006.257.14:13:49.07#ibcon#flushed, iclass 38, count 2 2006.257.14:13:49.07#ibcon#about to write, iclass 38, count 2 2006.257.14:13:49.07#ibcon#wrote, iclass 38, count 2 2006.257.14:13:49.07#ibcon#about to read 3, iclass 38, count 2 2006.257.14:13:49.10#ibcon#read 3, iclass 38, count 2 2006.257.14:13:49.89#ibcon#about to read 4, iclass 38, count 2 2006.257.14:13:49.89#ibcon#read 4, iclass 38, count 2 2006.257.14:13:49.89#ibcon#about to read 5, iclass 38, count 2 2006.257.14:13:49.89#ibcon#read 5, iclass 38, count 2 2006.257.14:13:49.89#ibcon#about to read 6, iclass 38, count 2 2006.257.14:13:49.89#ibcon#read 6, iclass 38, count 2 2006.257.14:13:49.89#ibcon#end of sib2, iclass 38, count 2 2006.257.14:13:49.89#ibcon#*after write, iclass 38, count 2 2006.257.14:13:49.89#ibcon#*before return 0, iclass 38, count 2 2006.257.14:13:49.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:49.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:13:49.89#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.14:13:49.89#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:49.89#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:50.01#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:50.01#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:50.01#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:13:50.01#ibcon#first serial, iclass 38, count 0 2006.257.14:13:50.01#ibcon#enter sib2, iclass 38, count 0 2006.257.14:13:50.01#ibcon#flushed, iclass 38, count 0 2006.257.14:13:50.01#ibcon#about to write, iclass 38, count 0 2006.257.14:13:50.01#ibcon#wrote, iclass 38, count 0 2006.257.14:13:50.01#ibcon#about to read 3, iclass 38, count 0 2006.257.14:13:50.03#ibcon#read 3, iclass 38, count 0 2006.257.14:13:50.03#ibcon#about to read 4, iclass 38, count 0 2006.257.14:13:50.03#ibcon#read 4, iclass 38, count 0 2006.257.14:13:50.03#ibcon#about to read 5, iclass 38, count 0 2006.257.14:13:50.03#ibcon#read 5, iclass 38, count 0 2006.257.14:13:50.03#ibcon#about to read 6, iclass 38, count 0 2006.257.14:13:50.03#ibcon#read 6, iclass 38, count 0 2006.257.14:13:50.03#ibcon#end of sib2, iclass 38, count 0 2006.257.14:13:50.03#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:13:50.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:13:50.03#ibcon#[27=USB\r\n] 2006.257.14:13:50.03#ibcon#*before write, iclass 38, count 0 2006.257.14:13:50.03#ibcon#enter sib2, iclass 38, count 0 2006.257.14:13:50.03#ibcon#flushed, iclass 38, count 0 2006.257.14:13:50.03#ibcon#about to write, iclass 38, count 0 2006.257.14:13:50.03#ibcon#wrote, iclass 38, count 0 2006.257.14:13:50.03#ibcon#about to read 3, iclass 38, count 0 2006.257.14:13:50.06#ibcon#read 3, iclass 38, count 0 2006.257.14:13:50.06#ibcon#about to read 4, iclass 38, count 0 2006.257.14:13:50.06#ibcon#read 4, iclass 38, count 0 2006.257.14:13:50.06#ibcon#about to read 5, iclass 38, count 0 2006.257.14:13:50.06#ibcon#read 5, iclass 38, count 0 2006.257.14:13:50.06#ibcon#about to read 6, iclass 38, count 0 2006.257.14:13:50.06#ibcon#read 6, iclass 38, count 0 2006.257.14:13:50.06#ibcon#end of sib2, iclass 38, count 0 2006.257.14:13:50.06#ibcon#*after write, iclass 38, count 0 2006.257.14:13:50.06#ibcon#*before return 0, iclass 38, count 0 2006.257.14:13:50.06#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:50.06#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:13:50.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:13:50.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:13:50.06$vck44/vblo=8,744.99 2006.257.14:13:50.06#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.14:13:50.06#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.14:13:50.06#ibcon#ireg 17 cls_cnt 0 2006.257.14:13:50.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:50.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:50.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:50.06#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:13:50.06#ibcon#first serial, iclass 40, count 0 2006.257.14:13:50.06#ibcon#enter sib2, iclass 40, count 0 2006.257.14:13:50.06#ibcon#flushed, iclass 40, count 0 2006.257.14:13:50.06#ibcon#about to write, iclass 40, count 0 2006.257.14:13:50.06#ibcon#wrote, iclass 40, count 0 2006.257.14:13:50.06#ibcon#about to read 3, iclass 40, count 0 2006.257.14:13:50.08#ibcon#read 3, iclass 40, count 0 2006.257.14:13:50.08#ibcon#about to read 4, iclass 40, count 0 2006.257.14:13:50.08#ibcon#read 4, iclass 40, count 0 2006.257.14:13:50.08#ibcon#about to read 5, iclass 40, count 0 2006.257.14:13:50.08#ibcon#read 5, iclass 40, count 0 2006.257.14:13:50.08#ibcon#about to read 6, iclass 40, count 0 2006.257.14:13:50.08#ibcon#read 6, iclass 40, count 0 2006.257.14:13:50.08#ibcon#end of sib2, iclass 40, count 0 2006.257.14:13:50.08#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:13:50.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:13:50.08#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:13:50.08#ibcon#*before write, iclass 40, count 0 2006.257.14:13:50.08#ibcon#enter sib2, iclass 40, count 0 2006.257.14:13:50.08#ibcon#flushed, iclass 40, count 0 2006.257.14:13:50.08#ibcon#about to write, iclass 40, count 0 2006.257.14:13:50.08#ibcon#wrote, iclass 40, count 0 2006.257.14:13:50.08#ibcon#about to read 3, iclass 40, count 0 2006.257.14:13:50.12#ibcon#read 3, iclass 40, count 0 2006.257.14:13:50.12#ibcon#about to read 4, iclass 40, count 0 2006.257.14:13:50.12#ibcon#read 4, iclass 40, count 0 2006.257.14:13:50.12#ibcon#about to read 5, iclass 40, count 0 2006.257.14:13:50.12#ibcon#read 5, iclass 40, count 0 2006.257.14:13:50.12#ibcon#about to read 6, iclass 40, count 0 2006.257.14:13:50.12#ibcon#read 6, iclass 40, count 0 2006.257.14:13:50.12#ibcon#end of sib2, iclass 40, count 0 2006.257.14:13:50.12#ibcon#*after write, iclass 40, count 0 2006.257.14:13:50.12#ibcon#*before return 0, iclass 40, count 0 2006.257.14:13:50.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:50.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:13:50.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:13:50.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:13:50.12$vck44/vb=8,4 2006.257.14:13:50.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.14:13:50.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.14:13:50.12#ibcon#ireg 11 cls_cnt 2 2006.257.14:13:50.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:50.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:50.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:50.18#ibcon#enter wrdev, iclass 4, count 2 2006.257.14:13:50.18#ibcon#first serial, iclass 4, count 2 2006.257.14:13:50.18#ibcon#enter sib2, iclass 4, count 2 2006.257.14:13:50.18#ibcon#flushed, iclass 4, count 2 2006.257.14:13:50.18#ibcon#about to write, iclass 4, count 2 2006.257.14:13:50.18#ibcon#wrote, iclass 4, count 2 2006.257.14:13:50.18#ibcon#about to read 3, iclass 4, count 2 2006.257.14:13:50.20#ibcon#read 3, iclass 4, count 2 2006.257.14:13:50.20#ibcon#about to read 4, iclass 4, count 2 2006.257.14:13:50.20#ibcon#read 4, iclass 4, count 2 2006.257.14:13:50.20#ibcon#about to read 5, iclass 4, count 2 2006.257.14:13:50.20#ibcon#read 5, iclass 4, count 2 2006.257.14:13:50.20#ibcon#about to read 6, iclass 4, count 2 2006.257.14:13:50.20#ibcon#read 6, iclass 4, count 2 2006.257.14:13:50.20#ibcon#end of sib2, iclass 4, count 2 2006.257.14:13:50.20#ibcon#*mode == 0, iclass 4, count 2 2006.257.14:13:50.20#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.14:13:50.20#ibcon#[27=AT08-04\r\n] 2006.257.14:13:50.20#ibcon#*before write, iclass 4, count 2 2006.257.14:13:50.20#ibcon#enter sib2, iclass 4, count 2 2006.257.14:13:50.20#ibcon#flushed, iclass 4, count 2 2006.257.14:13:50.20#ibcon#about to write, iclass 4, count 2 2006.257.14:13:50.20#ibcon#wrote, iclass 4, count 2 2006.257.14:13:50.20#ibcon#about to read 3, iclass 4, count 2 2006.257.14:13:50.23#ibcon#read 3, iclass 4, count 2 2006.257.14:13:50.23#ibcon#about to read 4, iclass 4, count 2 2006.257.14:13:50.23#ibcon#read 4, iclass 4, count 2 2006.257.14:13:50.23#ibcon#about to read 5, iclass 4, count 2 2006.257.14:13:50.23#ibcon#read 5, iclass 4, count 2 2006.257.14:13:50.23#ibcon#about to read 6, iclass 4, count 2 2006.257.14:13:50.23#ibcon#read 6, iclass 4, count 2 2006.257.14:13:50.23#ibcon#end of sib2, iclass 4, count 2 2006.257.14:13:50.23#ibcon#*after write, iclass 4, count 2 2006.257.14:13:50.23#ibcon#*before return 0, iclass 4, count 2 2006.257.14:13:50.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:50.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:13:50.23#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.14:13:50.23#ibcon#ireg 7 cls_cnt 0 2006.257.14:13:50.23#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:50.35#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:50.35#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:50.35#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:13:50.35#ibcon#first serial, iclass 4, count 0 2006.257.14:13:50.35#ibcon#enter sib2, iclass 4, count 0 2006.257.14:13:50.35#ibcon#flushed, iclass 4, count 0 2006.257.14:13:50.35#ibcon#about to write, iclass 4, count 0 2006.257.14:13:50.35#ibcon#wrote, iclass 4, count 0 2006.257.14:13:50.35#ibcon#about to read 3, iclass 4, count 0 2006.257.14:13:50.37#ibcon#read 3, iclass 4, count 0 2006.257.14:13:50.37#ibcon#about to read 4, iclass 4, count 0 2006.257.14:13:50.37#ibcon#read 4, iclass 4, count 0 2006.257.14:13:50.37#ibcon#about to read 5, iclass 4, count 0 2006.257.14:13:50.37#ibcon#read 5, iclass 4, count 0 2006.257.14:13:50.37#ibcon#about to read 6, iclass 4, count 0 2006.257.14:13:50.37#ibcon#read 6, iclass 4, count 0 2006.257.14:13:50.37#ibcon#end of sib2, iclass 4, count 0 2006.257.14:13:50.37#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:13:50.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:13:50.37#ibcon#[27=USB\r\n] 2006.257.14:13:50.37#ibcon#*before write, iclass 4, count 0 2006.257.14:13:50.37#ibcon#enter sib2, iclass 4, count 0 2006.257.14:13:50.37#ibcon#flushed, iclass 4, count 0 2006.257.14:13:50.37#ibcon#about to write, iclass 4, count 0 2006.257.14:13:50.37#ibcon#wrote, iclass 4, count 0 2006.257.14:13:50.37#ibcon#about to read 3, iclass 4, count 0 2006.257.14:13:50.40#ibcon#read 3, iclass 4, count 0 2006.257.14:13:50.40#ibcon#about to read 4, iclass 4, count 0 2006.257.14:13:50.40#ibcon#read 4, iclass 4, count 0 2006.257.14:13:50.40#ibcon#about to read 5, iclass 4, count 0 2006.257.14:13:50.40#ibcon#read 5, iclass 4, count 0 2006.257.14:13:50.40#ibcon#about to read 6, iclass 4, count 0 2006.257.14:13:50.40#ibcon#read 6, iclass 4, count 0 2006.257.14:13:50.40#ibcon#end of sib2, iclass 4, count 0 2006.257.14:13:50.40#ibcon#*after write, iclass 4, count 0 2006.257.14:13:50.40#ibcon#*before return 0, iclass 4, count 0 2006.257.14:13:50.40#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:50.40#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:13:50.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:13:50.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:13:50.40$vck44/vabw=wide 2006.257.14:13:50.40#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.14:13:50.40#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.14:13:50.40#ibcon#ireg 8 cls_cnt 0 2006.257.14:13:50.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:50.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:50.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:50.40#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:13:50.40#ibcon#first serial, iclass 6, count 0 2006.257.14:13:50.40#ibcon#enter sib2, iclass 6, count 0 2006.257.14:13:50.40#ibcon#flushed, iclass 6, count 0 2006.257.14:13:50.40#ibcon#about to write, iclass 6, count 0 2006.257.14:13:50.40#ibcon#wrote, iclass 6, count 0 2006.257.14:13:50.40#ibcon#about to read 3, iclass 6, count 0 2006.257.14:13:50.42#ibcon#read 3, iclass 6, count 0 2006.257.14:13:50.42#ibcon#about to read 4, iclass 6, count 0 2006.257.14:13:50.42#ibcon#read 4, iclass 6, count 0 2006.257.14:13:50.42#ibcon#about to read 5, iclass 6, count 0 2006.257.14:13:50.42#ibcon#read 5, iclass 6, count 0 2006.257.14:13:50.42#ibcon#about to read 6, iclass 6, count 0 2006.257.14:13:50.42#ibcon#read 6, iclass 6, count 0 2006.257.14:13:50.42#ibcon#end of sib2, iclass 6, count 0 2006.257.14:13:50.42#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:13:50.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:13:50.42#ibcon#[25=BW32\r\n] 2006.257.14:13:50.42#ibcon#*before write, iclass 6, count 0 2006.257.14:13:50.42#ibcon#enter sib2, iclass 6, count 0 2006.257.14:13:50.42#ibcon#flushed, iclass 6, count 0 2006.257.14:13:50.42#ibcon#about to write, iclass 6, count 0 2006.257.14:13:50.42#ibcon#wrote, iclass 6, count 0 2006.257.14:13:50.42#ibcon#about to read 3, iclass 6, count 0 2006.257.14:13:50.45#ibcon#read 3, iclass 6, count 0 2006.257.14:13:50.45#ibcon#about to read 4, iclass 6, count 0 2006.257.14:13:50.45#ibcon#read 4, iclass 6, count 0 2006.257.14:13:50.45#ibcon#about to read 5, iclass 6, count 0 2006.257.14:13:50.45#ibcon#read 5, iclass 6, count 0 2006.257.14:13:50.45#ibcon#about to read 6, iclass 6, count 0 2006.257.14:13:50.45#ibcon#read 6, iclass 6, count 0 2006.257.14:13:50.45#ibcon#end of sib2, iclass 6, count 0 2006.257.14:13:50.45#ibcon#*after write, iclass 6, count 0 2006.257.14:13:50.45#ibcon#*before return 0, iclass 6, count 0 2006.257.14:13:50.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:50.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:13:50.45#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:13:50.45#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:13:50.45$vck44/vbbw=wide 2006.257.14:13:50.45#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.14:13:50.45#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.14:13:50.45#ibcon#ireg 8 cls_cnt 0 2006.257.14:13:50.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:13:50.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:13:50.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:13:50.52#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:13:50.52#ibcon#first serial, iclass 10, count 0 2006.257.14:13:50.52#ibcon#enter sib2, iclass 10, count 0 2006.257.14:13:50.52#ibcon#flushed, iclass 10, count 0 2006.257.14:13:50.52#ibcon#about to write, iclass 10, count 0 2006.257.14:13:50.52#ibcon#wrote, iclass 10, count 0 2006.257.14:13:50.52#ibcon#about to read 3, iclass 10, count 0 2006.257.14:13:50.54#ibcon#read 3, iclass 10, count 0 2006.257.14:13:50.54#ibcon#about to read 4, iclass 10, count 0 2006.257.14:13:50.54#ibcon#read 4, iclass 10, count 0 2006.257.14:13:50.54#ibcon#about to read 5, iclass 10, count 0 2006.257.14:13:50.54#ibcon#read 5, iclass 10, count 0 2006.257.14:13:50.54#ibcon#about to read 6, iclass 10, count 0 2006.257.14:13:50.54#ibcon#read 6, iclass 10, count 0 2006.257.14:13:50.54#ibcon#end of sib2, iclass 10, count 0 2006.257.14:13:50.54#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:13:50.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:13:50.54#ibcon#[27=BW32\r\n] 2006.257.14:13:50.54#ibcon#*before write, iclass 10, count 0 2006.257.14:13:50.54#ibcon#enter sib2, iclass 10, count 0 2006.257.14:13:50.54#ibcon#flushed, iclass 10, count 0 2006.257.14:13:50.54#ibcon#about to write, iclass 10, count 0 2006.257.14:13:50.54#ibcon#wrote, iclass 10, count 0 2006.257.14:13:50.54#ibcon#about to read 3, iclass 10, count 0 2006.257.14:13:50.57#ibcon#read 3, iclass 10, count 0 2006.257.14:13:50.57#ibcon#about to read 4, iclass 10, count 0 2006.257.14:13:50.57#ibcon#read 4, iclass 10, count 0 2006.257.14:13:50.57#ibcon#about to read 5, iclass 10, count 0 2006.257.14:13:50.57#ibcon#read 5, iclass 10, count 0 2006.257.14:13:50.57#ibcon#about to read 6, iclass 10, count 0 2006.257.14:13:50.57#ibcon#read 6, iclass 10, count 0 2006.257.14:13:50.57#ibcon#end of sib2, iclass 10, count 0 2006.257.14:13:50.57#ibcon#*after write, iclass 10, count 0 2006.257.14:13:50.57#ibcon#*before return 0, iclass 10, count 0 2006.257.14:13:50.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:13:50.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:13:50.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:13:50.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:13:50.57$setupk4/ifdk4 2006.257.14:13:50.57$ifdk4/lo= 2006.257.14:13:50.57$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:13:50.57$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:13:50.57$ifdk4/patch= 2006.257.14:13:50.57$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:13:50.57$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:13:50.57$setupk4/!*+20s 2006.257.14:13:54.53#abcon#<5=/14 1.8 4.8 17.47 971014.0\r\n> 2006.257.14:13:54.55#abcon#{5=INTERFACE CLEAR} 2006.257.14:13:54.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:14:02.17$setupk4/"tpicd 2006.257.14:14:02.17$setupk4/echo=off 2006.257.14:14:02.17$setupk4/xlog=off 2006.257.14:14:02.17:!2006.257.14:18:31 2006.257.14:14:07.14#trakl#Source acquired 2006.257.14:14:07.14#flagr#flagr/antenna,acquired 2006.257.14:18:31.00:preob 2006.257.14:18:32.14/onsource/TRACKING 2006.257.14:18:32.14:!2006.257.14:18:41 2006.257.14:18:41.00:"tape 2006.257.14:18:41.00:"st=record 2006.257.14:18:41.00:data_valid=on 2006.257.14:18:41.00:midob 2006.257.14:18:41.14/onsource/TRACKING 2006.257.14:18:41.14/wx/17.45,1014.0,97 2006.257.14:18:41.28/cable/+6.4841E-03 2006.257.14:18:42.37/va/01,08,usb,yes,44,47 2006.257.14:18:42.37/va/02,07,usb,yes,48,48 2006.257.14:18:42.37/va/03,08,usb,yes,43,46 2006.257.14:18:42.37/va/04,07,usb,yes,50,52 2006.257.14:18:42.37/va/05,04,usb,yes,45,45 2006.257.14:18:42.37/va/06,04,usb,yes,49,49 2006.257.14:18:42.37/va/07,04,usb,yes,50,51 2006.257.14:18:42.37/va/08,04,usb,yes,43,51 2006.257.14:18:42.60/valo/01,524.99,yes,locked 2006.257.14:18:42.60/valo/02,534.99,yes,locked 2006.257.14:18:42.60/valo/03,564.99,yes,locked 2006.257.14:18:42.60/valo/04,624.99,yes,locked 2006.257.14:18:42.60/valo/05,734.99,yes,locked 2006.257.14:18:42.60/valo/06,814.99,yes,locked 2006.257.14:18:42.60/valo/07,864.99,yes,locked 2006.257.14:18:42.60/valo/08,884.99,yes,locked 2006.257.14:18:43.69/vb/01,04,usb,yes,41,38 2006.257.14:18:43.69/vb/02,05,usb,yes,39,38 2006.257.14:18:43.69/vb/03,04,usb,yes,40,44 2006.257.14:18:43.69/vb/04,05,usb,yes,40,39 2006.257.14:18:43.69/vb/05,04,usb,yes,36,39 2006.257.14:18:43.69/vb/06,04,usb,yes,42,37 2006.257.14:18:43.69/vb/07,04,usb,yes,42,42 2006.257.14:18:43.69/vb/08,04,usb,yes,38,43 2006.257.14:18:43.92/vblo/01,629.99,yes,locked 2006.257.14:18:43.92/vblo/02,634.99,yes,locked 2006.257.14:18:43.92/vblo/03,649.99,yes,locked 2006.257.14:18:43.92/vblo/04,679.99,yes,locked 2006.257.14:18:43.92/vblo/05,709.99,yes,locked 2006.257.14:18:43.92/vblo/06,719.99,yes,locked 2006.257.14:18:43.92/vblo/07,734.99,yes,locked 2006.257.14:18:43.92/vblo/08,744.99,yes,locked 2006.257.14:18:44.07/vabw/8 2006.257.14:18:44.22/vbbw/8 2006.257.14:18:44.31/xfe/off,on,16.2 2006.257.14:18:44.70/ifatt/23,28,28,28 2006.257.14:18:45.07/fmout-gps/S +4.57E-07 2006.257.14:18:45.11:!2006.257.14:20:21 2006.257.14:20:21.00:data_valid=off 2006.257.14:20:21.00:"et 2006.257.14:20:21.00:!+3s 2006.257.14:20:24.01:"tape 2006.257.14:20:24.01:postob 2006.257.14:20:24.09/cable/+6.4823E-03 2006.257.14:20:24.09/wx/17.45,1014.0,97 2006.257.14:20:25.08/fmout-gps/S +4.56E-07 2006.257.14:20:25.08:scan_name=257-1429,jd0609,160 2006.257.14:20:25.08:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.14:20:26.13#flagr#flagr/antenna,new-source 2006.257.14:20:26.13:checkk5 2006.257.14:20:26.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:20:26.88/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:20:27.27/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:20:27.67/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:20:28.07/chk_obsdata//k5ts1/T2571418??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.14:20:28.46/chk_obsdata//k5ts2/T2571418??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.14:20:28.84/chk_obsdata//k5ts3/T2571418??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.14:20:29.26/chk_obsdata//k5ts4/T2571418??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.14:20:29.95/k5log//k5ts1_log_newline 2006.257.14:20:30.65/k5log//k5ts2_log_newline 2006.257.14:20:31.35/k5log//k5ts3_log_newline 2006.257.14:20:32.04/k5log//k5ts4_log_newline 2006.257.14:20:32.06/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:20:32.06:setupk4=1 2006.257.14:20:32.06$setupk4/echo=on 2006.257.14:20:32.06$setupk4/pcalon 2006.257.14:20:32.06$pcalon/"no phase cal control is implemented here 2006.257.14:20:32.06$setupk4/"tpicd=stop 2006.257.14:20:32.06$setupk4/"rec=synch_on 2006.257.14:20:32.06$setupk4/"rec_mode=128 2006.257.14:20:32.06$setupk4/!* 2006.257.14:20:32.06$setupk4/recpk4 2006.257.14:20:32.06$recpk4/recpatch= 2006.257.14:20:32.06$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:20:32.06$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:20:32.06$setupk4/vck44 2006.257.14:20:32.07$vck44/valo=1,524.99 2006.257.14:20:32.07#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.14:20:32.07#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.14:20:32.07#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:32.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:32.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:32.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:32.07#ibcon#enter wrdev, iclass 31, count 0 2006.257.14:20:32.07#ibcon#first serial, iclass 31, count 0 2006.257.14:20:32.07#ibcon#enter sib2, iclass 31, count 0 2006.257.14:20:32.07#ibcon#flushed, iclass 31, count 0 2006.257.14:20:32.07#ibcon#about to write, iclass 31, count 0 2006.257.14:20:32.07#ibcon#wrote, iclass 31, count 0 2006.257.14:20:32.07#ibcon#about to read 3, iclass 31, count 0 2006.257.14:20:32.08#ibcon#read 3, iclass 31, count 0 2006.257.14:20:32.08#ibcon#about to read 4, iclass 31, count 0 2006.257.14:20:32.08#ibcon#read 4, iclass 31, count 0 2006.257.14:20:32.08#ibcon#about to read 5, iclass 31, count 0 2006.257.14:20:32.08#ibcon#read 5, iclass 31, count 0 2006.257.14:20:32.08#ibcon#about to read 6, iclass 31, count 0 2006.257.14:20:32.08#ibcon#read 6, iclass 31, count 0 2006.257.14:20:32.08#ibcon#end of sib2, iclass 31, count 0 2006.257.14:20:32.08#ibcon#*mode == 0, iclass 31, count 0 2006.257.14:20:32.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.14:20:32.08#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:20:32.08#ibcon#*before write, iclass 31, count 0 2006.257.14:20:32.08#ibcon#enter sib2, iclass 31, count 0 2006.257.14:20:32.08#ibcon#flushed, iclass 31, count 0 2006.257.14:20:32.08#ibcon#about to write, iclass 31, count 0 2006.257.14:20:32.08#ibcon#wrote, iclass 31, count 0 2006.257.14:20:32.08#ibcon#about to read 3, iclass 31, count 0 2006.257.14:20:32.13#ibcon#read 3, iclass 31, count 0 2006.257.14:20:32.13#ibcon#about to read 4, iclass 31, count 0 2006.257.14:20:32.13#ibcon#read 4, iclass 31, count 0 2006.257.14:20:32.13#ibcon#about to read 5, iclass 31, count 0 2006.257.14:20:32.13#ibcon#read 5, iclass 31, count 0 2006.257.14:20:32.13#ibcon#about to read 6, iclass 31, count 0 2006.257.14:20:32.13#ibcon#read 6, iclass 31, count 0 2006.257.14:20:32.13#ibcon#end of sib2, iclass 31, count 0 2006.257.14:20:32.13#ibcon#*after write, iclass 31, count 0 2006.257.14:20:32.13#ibcon#*before return 0, iclass 31, count 0 2006.257.14:20:32.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:32.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:32.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.14:20:32.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.14:20:32.13$vck44/va=1,8 2006.257.14:20:32.13#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.14:20:32.13#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.14:20:32.13#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:32.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:32.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:32.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:32.13#ibcon#enter wrdev, iclass 33, count 2 2006.257.14:20:32.13#ibcon#first serial, iclass 33, count 2 2006.257.14:20:32.13#ibcon#enter sib2, iclass 33, count 2 2006.257.14:20:32.13#ibcon#flushed, iclass 33, count 2 2006.257.14:20:32.13#ibcon#about to write, iclass 33, count 2 2006.257.14:20:32.13#ibcon#wrote, iclass 33, count 2 2006.257.14:20:32.13#ibcon#about to read 3, iclass 33, count 2 2006.257.14:20:32.15#ibcon#read 3, iclass 33, count 2 2006.257.14:20:32.15#ibcon#about to read 4, iclass 33, count 2 2006.257.14:20:32.15#ibcon#read 4, iclass 33, count 2 2006.257.14:20:32.15#ibcon#about to read 5, iclass 33, count 2 2006.257.14:20:32.15#ibcon#read 5, iclass 33, count 2 2006.257.14:20:32.15#ibcon#about to read 6, iclass 33, count 2 2006.257.14:20:32.15#ibcon#read 6, iclass 33, count 2 2006.257.14:20:32.15#ibcon#end of sib2, iclass 33, count 2 2006.257.14:20:32.15#ibcon#*mode == 0, iclass 33, count 2 2006.257.14:20:32.15#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.14:20:32.15#ibcon#[25=AT01-08\r\n] 2006.257.14:20:32.15#ibcon#*before write, iclass 33, count 2 2006.257.14:20:32.15#ibcon#enter sib2, iclass 33, count 2 2006.257.14:20:32.15#ibcon#flushed, iclass 33, count 2 2006.257.14:20:32.15#ibcon#about to write, iclass 33, count 2 2006.257.14:20:32.15#ibcon#wrote, iclass 33, count 2 2006.257.14:20:32.15#ibcon#about to read 3, iclass 33, count 2 2006.257.14:20:32.18#ibcon#read 3, iclass 33, count 2 2006.257.14:20:32.18#ibcon#about to read 4, iclass 33, count 2 2006.257.14:20:32.18#ibcon#read 4, iclass 33, count 2 2006.257.14:20:32.18#ibcon#about to read 5, iclass 33, count 2 2006.257.14:20:32.18#ibcon#read 5, iclass 33, count 2 2006.257.14:20:32.18#ibcon#about to read 6, iclass 33, count 2 2006.257.14:20:32.18#ibcon#read 6, iclass 33, count 2 2006.257.14:20:32.18#ibcon#end of sib2, iclass 33, count 2 2006.257.14:20:32.18#ibcon#*after write, iclass 33, count 2 2006.257.14:20:32.18#ibcon#*before return 0, iclass 33, count 2 2006.257.14:20:32.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:32.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:32.18#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.14:20:32.18#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:32.18#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:32.30#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:32.30#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:32.30#ibcon#enter wrdev, iclass 33, count 0 2006.257.14:20:32.30#ibcon#first serial, iclass 33, count 0 2006.257.14:20:32.30#ibcon#enter sib2, iclass 33, count 0 2006.257.14:20:32.30#ibcon#flushed, iclass 33, count 0 2006.257.14:20:32.30#ibcon#about to write, iclass 33, count 0 2006.257.14:20:32.30#ibcon#wrote, iclass 33, count 0 2006.257.14:20:32.30#ibcon#about to read 3, iclass 33, count 0 2006.257.14:20:32.32#ibcon#read 3, iclass 33, count 0 2006.257.14:20:32.32#ibcon#about to read 4, iclass 33, count 0 2006.257.14:20:32.32#ibcon#read 4, iclass 33, count 0 2006.257.14:20:32.32#ibcon#about to read 5, iclass 33, count 0 2006.257.14:20:32.32#ibcon#read 5, iclass 33, count 0 2006.257.14:20:32.32#ibcon#about to read 6, iclass 33, count 0 2006.257.14:20:32.32#ibcon#read 6, iclass 33, count 0 2006.257.14:20:32.32#ibcon#end of sib2, iclass 33, count 0 2006.257.14:20:32.32#ibcon#*mode == 0, iclass 33, count 0 2006.257.14:20:32.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.14:20:32.32#ibcon#[25=USB\r\n] 2006.257.14:20:32.32#ibcon#*before write, iclass 33, count 0 2006.257.14:20:32.32#ibcon#enter sib2, iclass 33, count 0 2006.257.14:20:32.32#ibcon#flushed, iclass 33, count 0 2006.257.14:20:32.32#ibcon#about to write, iclass 33, count 0 2006.257.14:20:32.32#ibcon#wrote, iclass 33, count 0 2006.257.14:20:32.32#ibcon#about to read 3, iclass 33, count 0 2006.257.14:20:32.35#ibcon#read 3, iclass 33, count 0 2006.257.14:20:32.35#ibcon#about to read 4, iclass 33, count 0 2006.257.14:20:32.35#ibcon#read 4, iclass 33, count 0 2006.257.14:20:32.35#ibcon#about to read 5, iclass 33, count 0 2006.257.14:20:32.35#ibcon#read 5, iclass 33, count 0 2006.257.14:20:32.35#ibcon#about to read 6, iclass 33, count 0 2006.257.14:20:32.35#ibcon#read 6, iclass 33, count 0 2006.257.14:20:32.35#ibcon#end of sib2, iclass 33, count 0 2006.257.14:20:32.35#ibcon#*after write, iclass 33, count 0 2006.257.14:20:32.35#ibcon#*before return 0, iclass 33, count 0 2006.257.14:20:32.35#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:32.35#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:32.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.14:20:32.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.14:20:32.35$vck44/valo=2,534.99 2006.257.14:20:32.35#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.14:20:32.35#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.14:20:32.35#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:32.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:32.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:32.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:32.35#ibcon#enter wrdev, iclass 35, count 0 2006.257.14:20:32.35#ibcon#first serial, iclass 35, count 0 2006.257.14:20:32.35#ibcon#enter sib2, iclass 35, count 0 2006.257.14:20:32.35#ibcon#flushed, iclass 35, count 0 2006.257.14:20:32.35#ibcon#about to write, iclass 35, count 0 2006.257.14:20:32.35#ibcon#wrote, iclass 35, count 0 2006.257.14:20:32.35#ibcon#about to read 3, iclass 35, count 0 2006.257.14:20:32.37#ibcon#read 3, iclass 35, count 0 2006.257.14:20:32.37#ibcon#about to read 4, iclass 35, count 0 2006.257.14:20:32.37#ibcon#read 4, iclass 35, count 0 2006.257.14:20:32.37#ibcon#about to read 5, iclass 35, count 0 2006.257.14:20:32.37#ibcon#read 5, iclass 35, count 0 2006.257.14:20:32.37#ibcon#about to read 6, iclass 35, count 0 2006.257.14:20:32.37#ibcon#read 6, iclass 35, count 0 2006.257.14:20:32.37#ibcon#end of sib2, iclass 35, count 0 2006.257.14:20:32.37#ibcon#*mode == 0, iclass 35, count 0 2006.257.14:20:32.37#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.14:20:32.37#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:20:32.37#ibcon#*before write, iclass 35, count 0 2006.257.14:20:32.37#ibcon#enter sib2, iclass 35, count 0 2006.257.14:20:32.37#ibcon#flushed, iclass 35, count 0 2006.257.14:20:32.37#ibcon#about to write, iclass 35, count 0 2006.257.14:20:32.37#ibcon#wrote, iclass 35, count 0 2006.257.14:20:32.37#ibcon#about to read 3, iclass 35, count 0 2006.257.14:20:32.41#ibcon#read 3, iclass 35, count 0 2006.257.14:20:32.41#ibcon#about to read 4, iclass 35, count 0 2006.257.14:20:32.41#ibcon#read 4, iclass 35, count 0 2006.257.14:20:32.41#ibcon#about to read 5, iclass 35, count 0 2006.257.14:20:32.41#ibcon#read 5, iclass 35, count 0 2006.257.14:20:32.41#ibcon#about to read 6, iclass 35, count 0 2006.257.14:20:32.41#ibcon#read 6, iclass 35, count 0 2006.257.14:20:32.41#ibcon#end of sib2, iclass 35, count 0 2006.257.14:20:32.41#ibcon#*after write, iclass 35, count 0 2006.257.14:20:32.41#ibcon#*before return 0, iclass 35, count 0 2006.257.14:20:32.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:32.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:32.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.14:20:32.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.14:20:32.41$vck44/va=2,7 2006.257.14:20:32.41#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.14:20:32.41#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.14:20:32.41#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:32.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:32.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:32.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:32.47#ibcon#enter wrdev, iclass 37, count 2 2006.257.14:20:32.47#ibcon#first serial, iclass 37, count 2 2006.257.14:20:32.47#ibcon#enter sib2, iclass 37, count 2 2006.257.14:20:32.47#ibcon#flushed, iclass 37, count 2 2006.257.14:20:32.47#ibcon#about to write, iclass 37, count 2 2006.257.14:20:32.47#ibcon#wrote, iclass 37, count 2 2006.257.14:20:32.47#ibcon#about to read 3, iclass 37, count 2 2006.257.14:20:32.49#ibcon#read 3, iclass 37, count 2 2006.257.14:20:32.49#ibcon#about to read 4, iclass 37, count 2 2006.257.14:20:32.49#ibcon#read 4, iclass 37, count 2 2006.257.14:20:32.49#ibcon#about to read 5, iclass 37, count 2 2006.257.14:20:32.49#ibcon#read 5, iclass 37, count 2 2006.257.14:20:32.49#ibcon#about to read 6, iclass 37, count 2 2006.257.14:20:32.49#ibcon#read 6, iclass 37, count 2 2006.257.14:20:32.49#ibcon#end of sib2, iclass 37, count 2 2006.257.14:20:32.49#ibcon#*mode == 0, iclass 37, count 2 2006.257.14:20:32.49#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.14:20:32.49#ibcon#[25=AT02-07\r\n] 2006.257.14:20:32.49#ibcon#*before write, iclass 37, count 2 2006.257.14:20:32.49#ibcon#enter sib2, iclass 37, count 2 2006.257.14:20:32.49#ibcon#flushed, iclass 37, count 2 2006.257.14:20:32.49#ibcon#about to write, iclass 37, count 2 2006.257.14:20:32.49#ibcon#wrote, iclass 37, count 2 2006.257.14:20:32.49#ibcon#about to read 3, iclass 37, count 2 2006.257.14:20:32.52#ibcon#read 3, iclass 37, count 2 2006.257.14:20:32.52#ibcon#about to read 4, iclass 37, count 2 2006.257.14:20:32.52#ibcon#read 4, iclass 37, count 2 2006.257.14:20:32.52#ibcon#about to read 5, iclass 37, count 2 2006.257.14:20:32.52#ibcon#read 5, iclass 37, count 2 2006.257.14:20:32.52#ibcon#about to read 6, iclass 37, count 2 2006.257.14:20:32.52#ibcon#read 6, iclass 37, count 2 2006.257.14:20:32.52#ibcon#end of sib2, iclass 37, count 2 2006.257.14:20:32.52#ibcon#*after write, iclass 37, count 2 2006.257.14:20:32.52#ibcon#*before return 0, iclass 37, count 2 2006.257.14:20:32.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:32.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:32.52#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.14:20:32.52#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:32.52#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:32.64#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:32.64#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:32.64#ibcon#enter wrdev, iclass 37, count 0 2006.257.14:20:32.64#ibcon#first serial, iclass 37, count 0 2006.257.14:20:32.64#ibcon#enter sib2, iclass 37, count 0 2006.257.14:20:32.64#ibcon#flushed, iclass 37, count 0 2006.257.14:20:32.64#ibcon#about to write, iclass 37, count 0 2006.257.14:20:32.64#ibcon#wrote, iclass 37, count 0 2006.257.14:20:32.64#ibcon#about to read 3, iclass 37, count 0 2006.257.14:20:32.66#ibcon#read 3, iclass 37, count 0 2006.257.14:20:32.66#ibcon#about to read 4, iclass 37, count 0 2006.257.14:20:32.66#ibcon#read 4, iclass 37, count 0 2006.257.14:20:32.66#ibcon#about to read 5, iclass 37, count 0 2006.257.14:20:32.66#ibcon#read 5, iclass 37, count 0 2006.257.14:20:32.66#ibcon#about to read 6, iclass 37, count 0 2006.257.14:20:32.66#ibcon#read 6, iclass 37, count 0 2006.257.14:20:32.66#ibcon#end of sib2, iclass 37, count 0 2006.257.14:20:32.66#ibcon#*mode == 0, iclass 37, count 0 2006.257.14:20:32.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.14:20:32.66#ibcon#[25=USB\r\n] 2006.257.14:20:32.66#ibcon#*before write, iclass 37, count 0 2006.257.14:20:32.66#ibcon#enter sib2, iclass 37, count 0 2006.257.14:20:32.66#ibcon#flushed, iclass 37, count 0 2006.257.14:20:32.66#ibcon#about to write, iclass 37, count 0 2006.257.14:20:32.66#ibcon#wrote, iclass 37, count 0 2006.257.14:20:32.66#ibcon#about to read 3, iclass 37, count 0 2006.257.14:20:32.69#ibcon#read 3, iclass 37, count 0 2006.257.14:20:32.69#ibcon#about to read 4, iclass 37, count 0 2006.257.14:20:32.69#ibcon#read 4, iclass 37, count 0 2006.257.14:20:32.69#ibcon#about to read 5, iclass 37, count 0 2006.257.14:20:32.69#ibcon#read 5, iclass 37, count 0 2006.257.14:20:32.69#ibcon#about to read 6, iclass 37, count 0 2006.257.14:20:32.69#ibcon#read 6, iclass 37, count 0 2006.257.14:20:32.69#ibcon#end of sib2, iclass 37, count 0 2006.257.14:20:32.69#ibcon#*after write, iclass 37, count 0 2006.257.14:20:32.69#ibcon#*before return 0, iclass 37, count 0 2006.257.14:20:32.69#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:32.69#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:32.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.14:20:32.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.14:20:32.69$vck44/valo=3,564.99 2006.257.14:20:32.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.14:20:32.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.14:20:32.69#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:32.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:32.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:32.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:32.69#ibcon#enter wrdev, iclass 39, count 0 2006.257.14:20:32.69#ibcon#first serial, iclass 39, count 0 2006.257.14:20:32.69#ibcon#enter sib2, iclass 39, count 0 2006.257.14:20:32.69#ibcon#flushed, iclass 39, count 0 2006.257.14:20:32.69#ibcon#about to write, iclass 39, count 0 2006.257.14:20:32.69#ibcon#wrote, iclass 39, count 0 2006.257.14:20:32.69#ibcon#about to read 3, iclass 39, count 0 2006.257.14:20:32.71#ibcon#read 3, iclass 39, count 0 2006.257.14:20:32.71#ibcon#about to read 4, iclass 39, count 0 2006.257.14:20:32.71#ibcon#read 4, iclass 39, count 0 2006.257.14:20:32.71#ibcon#about to read 5, iclass 39, count 0 2006.257.14:20:32.71#ibcon#read 5, iclass 39, count 0 2006.257.14:20:32.71#ibcon#about to read 6, iclass 39, count 0 2006.257.14:20:32.71#ibcon#read 6, iclass 39, count 0 2006.257.14:20:32.71#ibcon#end of sib2, iclass 39, count 0 2006.257.14:20:32.71#ibcon#*mode == 0, iclass 39, count 0 2006.257.14:20:32.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.14:20:32.71#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:20:32.71#ibcon#*before write, iclass 39, count 0 2006.257.14:20:32.71#ibcon#enter sib2, iclass 39, count 0 2006.257.14:20:32.71#ibcon#flushed, iclass 39, count 0 2006.257.14:20:32.71#ibcon#about to write, iclass 39, count 0 2006.257.14:20:32.71#ibcon#wrote, iclass 39, count 0 2006.257.14:20:32.71#ibcon#about to read 3, iclass 39, count 0 2006.257.14:20:32.75#ibcon#read 3, iclass 39, count 0 2006.257.14:20:32.75#ibcon#about to read 4, iclass 39, count 0 2006.257.14:20:32.75#ibcon#read 4, iclass 39, count 0 2006.257.14:20:32.75#ibcon#about to read 5, iclass 39, count 0 2006.257.14:20:32.75#ibcon#read 5, iclass 39, count 0 2006.257.14:20:32.75#ibcon#about to read 6, iclass 39, count 0 2006.257.14:20:32.75#ibcon#read 6, iclass 39, count 0 2006.257.14:20:32.75#ibcon#end of sib2, iclass 39, count 0 2006.257.14:20:32.75#ibcon#*after write, iclass 39, count 0 2006.257.14:20:32.75#ibcon#*before return 0, iclass 39, count 0 2006.257.14:20:32.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:32.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:32.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.14:20:32.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.14:20:32.75$vck44/va=3,8 2006.257.14:20:32.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.14:20:32.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.14:20:32.75#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:32.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:32.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:32.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:32.81#ibcon#enter wrdev, iclass 3, count 2 2006.257.14:20:32.81#ibcon#first serial, iclass 3, count 2 2006.257.14:20:32.81#ibcon#enter sib2, iclass 3, count 2 2006.257.14:20:32.81#ibcon#flushed, iclass 3, count 2 2006.257.14:20:32.81#ibcon#about to write, iclass 3, count 2 2006.257.14:20:32.81#ibcon#wrote, iclass 3, count 2 2006.257.14:20:32.81#ibcon#about to read 3, iclass 3, count 2 2006.257.14:20:32.83#ibcon#read 3, iclass 3, count 2 2006.257.14:20:32.83#ibcon#about to read 4, iclass 3, count 2 2006.257.14:20:32.83#ibcon#read 4, iclass 3, count 2 2006.257.14:20:32.83#ibcon#about to read 5, iclass 3, count 2 2006.257.14:20:32.83#ibcon#read 5, iclass 3, count 2 2006.257.14:20:32.83#ibcon#about to read 6, iclass 3, count 2 2006.257.14:20:32.83#ibcon#read 6, iclass 3, count 2 2006.257.14:20:32.83#ibcon#end of sib2, iclass 3, count 2 2006.257.14:20:32.83#ibcon#*mode == 0, iclass 3, count 2 2006.257.14:20:32.83#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.14:20:32.83#ibcon#[25=AT03-08\r\n] 2006.257.14:20:32.83#ibcon#*before write, iclass 3, count 2 2006.257.14:20:32.83#ibcon#enter sib2, iclass 3, count 2 2006.257.14:20:32.83#ibcon#flushed, iclass 3, count 2 2006.257.14:20:32.83#ibcon#about to write, iclass 3, count 2 2006.257.14:20:32.83#ibcon#wrote, iclass 3, count 2 2006.257.14:20:32.83#ibcon#about to read 3, iclass 3, count 2 2006.257.14:20:32.86#ibcon#read 3, iclass 3, count 2 2006.257.14:20:32.86#ibcon#about to read 4, iclass 3, count 2 2006.257.14:20:32.86#ibcon#read 4, iclass 3, count 2 2006.257.14:20:32.86#ibcon#about to read 5, iclass 3, count 2 2006.257.14:20:32.86#ibcon#read 5, iclass 3, count 2 2006.257.14:20:32.86#ibcon#about to read 6, iclass 3, count 2 2006.257.14:20:32.86#ibcon#read 6, iclass 3, count 2 2006.257.14:20:32.86#ibcon#end of sib2, iclass 3, count 2 2006.257.14:20:32.86#ibcon#*after write, iclass 3, count 2 2006.257.14:20:32.86#ibcon#*before return 0, iclass 3, count 2 2006.257.14:20:32.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:32.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:32.86#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.14:20:32.86#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:32.86#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:32.98#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:32.98#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:32.98#ibcon#enter wrdev, iclass 3, count 0 2006.257.14:20:32.98#ibcon#first serial, iclass 3, count 0 2006.257.14:20:32.98#ibcon#enter sib2, iclass 3, count 0 2006.257.14:20:32.98#ibcon#flushed, iclass 3, count 0 2006.257.14:20:32.98#ibcon#about to write, iclass 3, count 0 2006.257.14:20:32.98#ibcon#wrote, iclass 3, count 0 2006.257.14:20:32.98#ibcon#about to read 3, iclass 3, count 0 2006.257.14:20:33.00#ibcon#read 3, iclass 3, count 0 2006.257.14:20:33.00#ibcon#about to read 4, iclass 3, count 0 2006.257.14:20:33.00#ibcon#read 4, iclass 3, count 0 2006.257.14:20:33.00#ibcon#about to read 5, iclass 3, count 0 2006.257.14:20:33.00#ibcon#read 5, iclass 3, count 0 2006.257.14:20:33.00#ibcon#about to read 6, iclass 3, count 0 2006.257.14:20:33.00#ibcon#read 6, iclass 3, count 0 2006.257.14:20:33.00#ibcon#end of sib2, iclass 3, count 0 2006.257.14:20:33.00#ibcon#*mode == 0, iclass 3, count 0 2006.257.14:20:33.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.14:20:33.00#ibcon#[25=USB\r\n] 2006.257.14:20:33.00#ibcon#*before write, iclass 3, count 0 2006.257.14:20:33.00#ibcon#enter sib2, iclass 3, count 0 2006.257.14:20:33.00#ibcon#flushed, iclass 3, count 0 2006.257.14:20:33.00#ibcon#about to write, iclass 3, count 0 2006.257.14:20:33.00#ibcon#wrote, iclass 3, count 0 2006.257.14:20:33.00#ibcon#about to read 3, iclass 3, count 0 2006.257.14:20:33.03#ibcon#read 3, iclass 3, count 0 2006.257.14:20:33.03#ibcon#about to read 4, iclass 3, count 0 2006.257.14:20:33.03#ibcon#read 4, iclass 3, count 0 2006.257.14:20:33.03#ibcon#about to read 5, iclass 3, count 0 2006.257.14:20:33.03#ibcon#read 5, iclass 3, count 0 2006.257.14:20:33.03#ibcon#about to read 6, iclass 3, count 0 2006.257.14:20:33.03#ibcon#read 6, iclass 3, count 0 2006.257.14:20:33.03#ibcon#end of sib2, iclass 3, count 0 2006.257.14:20:33.03#ibcon#*after write, iclass 3, count 0 2006.257.14:20:33.03#ibcon#*before return 0, iclass 3, count 0 2006.257.14:20:33.03#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:33.03#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:33.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.14:20:33.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.14:20:33.03$vck44/valo=4,624.99 2006.257.14:20:33.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.14:20:33.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.14:20:33.03#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:33.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:33.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:33.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:33.03#ibcon#enter wrdev, iclass 5, count 0 2006.257.14:20:33.03#ibcon#first serial, iclass 5, count 0 2006.257.14:20:33.03#ibcon#enter sib2, iclass 5, count 0 2006.257.14:20:33.03#ibcon#flushed, iclass 5, count 0 2006.257.14:20:33.03#ibcon#about to write, iclass 5, count 0 2006.257.14:20:33.03#ibcon#wrote, iclass 5, count 0 2006.257.14:20:33.03#ibcon#about to read 3, iclass 5, count 0 2006.257.14:20:33.05#ibcon#read 3, iclass 5, count 0 2006.257.14:20:33.05#ibcon#about to read 4, iclass 5, count 0 2006.257.14:20:33.72#ibcon#read 4, iclass 5, count 0 2006.257.14:20:33.72#ibcon#about to read 5, iclass 5, count 0 2006.257.14:20:33.72#ibcon#read 5, iclass 5, count 0 2006.257.14:20:33.72#ibcon#about to read 6, iclass 5, count 0 2006.257.14:20:33.72#ibcon#read 6, iclass 5, count 0 2006.257.14:20:33.72#ibcon#end of sib2, iclass 5, count 0 2006.257.14:20:33.73#ibcon#*mode == 0, iclass 5, count 0 2006.257.14:20:33.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.14:20:33.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:20:33.73#ibcon#*before write, iclass 5, count 0 2006.257.14:20:33.73#ibcon#enter sib2, iclass 5, count 0 2006.257.14:20:33.73#ibcon#flushed, iclass 5, count 0 2006.257.14:20:33.73#ibcon#about to write, iclass 5, count 0 2006.257.14:20:33.73#ibcon#wrote, iclass 5, count 0 2006.257.14:20:33.73#ibcon#about to read 3, iclass 5, count 0 2006.257.14:20:33.77#ibcon#read 3, iclass 5, count 0 2006.257.14:20:33.77#ibcon#about to read 4, iclass 5, count 0 2006.257.14:20:33.77#ibcon#read 4, iclass 5, count 0 2006.257.14:20:33.77#ibcon#about to read 5, iclass 5, count 0 2006.257.14:20:33.77#ibcon#read 5, iclass 5, count 0 2006.257.14:20:33.77#ibcon#about to read 6, iclass 5, count 0 2006.257.14:20:33.77#ibcon#read 6, iclass 5, count 0 2006.257.14:20:33.77#ibcon#end of sib2, iclass 5, count 0 2006.257.14:20:33.77#ibcon#*after write, iclass 5, count 0 2006.257.14:20:33.77#ibcon#*before return 0, iclass 5, count 0 2006.257.14:20:33.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:33.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:33.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.14:20:33.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.14:20:33.77$vck44/va=4,7 2006.257.14:20:33.77#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.14:20:33.77#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.14:20:33.77#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:33.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:33.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:33.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:33.77#ibcon#enter wrdev, iclass 7, count 2 2006.257.14:20:33.77#ibcon#first serial, iclass 7, count 2 2006.257.14:20:33.77#ibcon#enter sib2, iclass 7, count 2 2006.257.14:20:33.77#ibcon#flushed, iclass 7, count 2 2006.257.14:20:33.77#ibcon#about to write, iclass 7, count 2 2006.257.14:20:33.77#ibcon#wrote, iclass 7, count 2 2006.257.14:20:33.77#ibcon#about to read 3, iclass 7, count 2 2006.257.14:20:33.79#ibcon#read 3, iclass 7, count 2 2006.257.14:20:33.79#ibcon#about to read 4, iclass 7, count 2 2006.257.14:20:33.79#ibcon#read 4, iclass 7, count 2 2006.257.14:20:33.79#ibcon#about to read 5, iclass 7, count 2 2006.257.14:20:33.79#ibcon#read 5, iclass 7, count 2 2006.257.14:20:33.79#ibcon#about to read 6, iclass 7, count 2 2006.257.14:20:33.79#ibcon#read 6, iclass 7, count 2 2006.257.14:20:33.79#ibcon#end of sib2, iclass 7, count 2 2006.257.14:20:33.79#ibcon#*mode == 0, iclass 7, count 2 2006.257.14:20:33.79#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.14:20:33.79#ibcon#[25=AT04-07\r\n] 2006.257.14:20:33.79#ibcon#*before write, iclass 7, count 2 2006.257.14:20:33.79#ibcon#enter sib2, iclass 7, count 2 2006.257.14:20:33.79#ibcon#flushed, iclass 7, count 2 2006.257.14:20:33.79#ibcon#about to write, iclass 7, count 2 2006.257.14:20:33.79#ibcon#wrote, iclass 7, count 2 2006.257.14:20:33.79#ibcon#about to read 3, iclass 7, count 2 2006.257.14:20:33.82#ibcon#read 3, iclass 7, count 2 2006.257.14:20:33.82#ibcon#about to read 4, iclass 7, count 2 2006.257.14:20:33.82#ibcon#read 4, iclass 7, count 2 2006.257.14:20:33.82#ibcon#about to read 5, iclass 7, count 2 2006.257.14:20:33.82#ibcon#read 5, iclass 7, count 2 2006.257.14:20:33.82#ibcon#about to read 6, iclass 7, count 2 2006.257.14:20:33.82#ibcon#read 6, iclass 7, count 2 2006.257.14:20:33.82#ibcon#end of sib2, iclass 7, count 2 2006.257.14:20:33.82#ibcon#*after write, iclass 7, count 2 2006.257.14:20:33.82#ibcon#*before return 0, iclass 7, count 2 2006.257.14:20:33.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:33.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:33.82#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.14:20:33.82#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:33.82#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:33.94#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:33.94#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:33.94#ibcon#enter wrdev, iclass 7, count 0 2006.257.14:20:33.94#ibcon#first serial, iclass 7, count 0 2006.257.14:20:33.94#ibcon#enter sib2, iclass 7, count 0 2006.257.14:20:33.94#ibcon#flushed, iclass 7, count 0 2006.257.14:20:33.94#ibcon#about to write, iclass 7, count 0 2006.257.14:20:33.94#ibcon#wrote, iclass 7, count 0 2006.257.14:20:33.94#ibcon#about to read 3, iclass 7, count 0 2006.257.14:20:33.96#ibcon#read 3, iclass 7, count 0 2006.257.14:20:33.96#ibcon#about to read 4, iclass 7, count 0 2006.257.14:20:33.96#ibcon#read 4, iclass 7, count 0 2006.257.14:20:33.96#ibcon#about to read 5, iclass 7, count 0 2006.257.14:20:33.96#ibcon#read 5, iclass 7, count 0 2006.257.14:20:33.96#ibcon#about to read 6, iclass 7, count 0 2006.257.14:20:33.96#ibcon#read 6, iclass 7, count 0 2006.257.14:20:33.96#ibcon#end of sib2, iclass 7, count 0 2006.257.14:20:33.96#ibcon#*mode == 0, iclass 7, count 0 2006.257.14:20:33.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.14:20:33.96#ibcon#[25=USB\r\n] 2006.257.14:20:33.96#ibcon#*before write, iclass 7, count 0 2006.257.14:20:33.96#ibcon#enter sib2, iclass 7, count 0 2006.257.14:20:33.96#ibcon#flushed, iclass 7, count 0 2006.257.14:20:33.96#ibcon#about to write, iclass 7, count 0 2006.257.14:20:33.96#ibcon#wrote, iclass 7, count 0 2006.257.14:20:33.96#ibcon#about to read 3, iclass 7, count 0 2006.257.14:20:33.99#ibcon#read 3, iclass 7, count 0 2006.257.14:20:33.99#ibcon#about to read 4, iclass 7, count 0 2006.257.14:20:33.99#ibcon#read 4, iclass 7, count 0 2006.257.14:20:33.99#ibcon#about to read 5, iclass 7, count 0 2006.257.14:20:33.99#ibcon#read 5, iclass 7, count 0 2006.257.14:20:33.99#ibcon#about to read 6, iclass 7, count 0 2006.257.14:20:33.99#ibcon#read 6, iclass 7, count 0 2006.257.14:20:33.99#ibcon#end of sib2, iclass 7, count 0 2006.257.14:20:33.99#ibcon#*after write, iclass 7, count 0 2006.257.14:20:33.99#ibcon#*before return 0, iclass 7, count 0 2006.257.14:20:33.99#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:33.99#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:33.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.14:20:33.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.14:20:33.99$vck44/valo=5,734.99 2006.257.14:20:33.99#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.14:20:33.99#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.14:20:33.99#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:33.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:33.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:33.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:33.99#ibcon#enter wrdev, iclass 11, count 0 2006.257.14:20:33.99#ibcon#first serial, iclass 11, count 0 2006.257.14:20:33.99#ibcon#enter sib2, iclass 11, count 0 2006.257.14:20:33.99#ibcon#flushed, iclass 11, count 0 2006.257.14:20:33.99#ibcon#about to write, iclass 11, count 0 2006.257.14:20:33.99#ibcon#wrote, iclass 11, count 0 2006.257.14:20:33.99#ibcon#about to read 3, iclass 11, count 0 2006.257.14:20:34.01#ibcon#read 3, iclass 11, count 0 2006.257.14:20:34.01#ibcon#about to read 4, iclass 11, count 0 2006.257.14:20:34.01#ibcon#read 4, iclass 11, count 0 2006.257.14:20:34.01#ibcon#about to read 5, iclass 11, count 0 2006.257.14:20:34.01#ibcon#read 5, iclass 11, count 0 2006.257.14:20:34.01#ibcon#about to read 6, iclass 11, count 0 2006.257.14:20:34.01#ibcon#read 6, iclass 11, count 0 2006.257.14:20:34.01#ibcon#end of sib2, iclass 11, count 0 2006.257.14:20:34.01#ibcon#*mode == 0, iclass 11, count 0 2006.257.14:20:34.01#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.14:20:34.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:20:34.01#ibcon#*before write, iclass 11, count 0 2006.257.14:20:34.01#ibcon#enter sib2, iclass 11, count 0 2006.257.14:20:34.01#ibcon#flushed, iclass 11, count 0 2006.257.14:20:34.01#ibcon#about to write, iclass 11, count 0 2006.257.14:20:34.01#ibcon#wrote, iclass 11, count 0 2006.257.14:20:34.01#ibcon#about to read 3, iclass 11, count 0 2006.257.14:20:34.05#ibcon#read 3, iclass 11, count 0 2006.257.14:20:34.05#ibcon#about to read 4, iclass 11, count 0 2006.257.14:20:34.05#ibcon#read 4, iclass 11, count 0 2006.257.14:20:34.05#ibcon#about to read 5, iclass 11, count 0 2006.257.14:20:34.05#ibcon#read 5, iclass 11, count 0 2006.257.14:20:34.05#ibcon#about to read 6, iclass 11, count 0 2006.257.14:20:34.05#ibcon#read 6, iclass 11, count 0 2006.257.14:20:34.05#ibcon#end of sib2, iclass 11, count 0 2006.257.14:20:34.05#ibcon#*after write, iclass 11, count 0 2006.257.14:20:34.05#ibcon#*before return 0, iclass 11, count 0 2006.257.14:20:34.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:34.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:34.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.14:20:34.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.14:20:34.05$vck44/va=5,4 2006.257.14:20:34.05#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.14:20:34.05#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.14:20:34.05#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:34.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:34.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:34.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:34.11#ibcon#enter wrdev, iclass 13, count 2 2006.257.14:20:34.11#ibcon#first serial, iclass 13, count 2 2006.257.14:20:34.11#ibcon#enter sib2, iclass 13, count 2 2006.257.14:20:34.11#ibcon#flushed, iclass 13, count 2 2006.257.14:20:34.11#ibcon#about to write, iclass 13, count 2 2006.257.14:20:34.11#ibcon#wrote, iclass 13, count 2 2006.257.14:20:34.11#ibcon#about to read 3, iclass 13, count 2 2006.257.14:20:34.13#ibcon#read 3, iclass 13, count 2 2006.257.14:20:34.13#ibcon#about to read 4, iclass 13, count 2 2006.257.14:20:34.13#ibcon#read 4, iclass 13, count 2 2006.257.14:20:34.13#ibcon#about to read 5, iclass 13, count 2 2006.257.14:20:34.13#ibcon#read 5, iclass 13, count 2 2006.257.14:20:34.13#ibcon#about to read 6, iclass 13, count 2 2006.257.14:20:34.13#ibcon#read 6, iclass 13, count 2 2006.257.14:20:34.13#ibcon#end of sib2, iclass 13, count 2 2006.257.14:20:34.13#ibcon#*mode == 0, iclass 13, count 2 2006.257.14:20:34.13#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.14:20:34.13#ibcon#[25=AT05-04\r\n] 2006.257.14:20:34.13#ibcon#*before write, iclass 13, count 2 2006.257.14:20:34.13#ibcon#enter sib2, iclass 13, count 2 2006.257.14:20:34.13#ibcon#flushed, iclass 13, count 2 2006.257.14:20:34.13#ibcon#about to write, iclass 13, count 2 2006.257.14:20:34.13#ibcon#wrote, iclass 13, count 2 2006.257.14:20:34.13#ibcon#about to read 3, iclass 13, count 2 2006.257.14:20:34.16#ibcon#read 3, iclass 13, count 2 2006.257.14:20:34.16#ibcon#about to read 4, iclass 13, count 2 2006.257.14:20:34.16#ibcon#read 4, iclass 13, count 2 2006.257.14:20:34.16#ibcon#about to read 5, iclass 13, count 2 2006.257.14:20:34.16#ibcon#read 5, iclass 13, count 2 2006.257.14:20:34.16#ibcon#about to read 6, iclass 13, count 2 2006.257.14:20:34.16#ibcon#read 6, iclass 13, count 2 2006.257.14:20:34.16#ibcon#end of sib2, iclass 13, count 2 2006.257.14:20:34.16#ibcon#*after write, iclass 13, count 2 2006.257.14:20:34.16#ibcon#*before return 0, iclass 13, count 2 2006.257.14:20:34.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:34.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:34.16#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.14:20:34.16#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:34.16#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:34.28#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:34.28#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:34.28#ibcon#enter wrdev, iclass 13, count 0 2006.257.14:20:34.28#ibcon#first serial, iclass 13, count 0 2006.257.14:20:34.28#ibcon#enter sib2, iclass 13, count 0 2006.257.14:20:34.28#ibcon#flushed, iclass 13, count 0 2006.257.14:20:34.28#ibcon#about to write, iclass 13, count 0 2006.257.14:20:34.28#ibcon#wrote, iclass 13, count 0 2006.257.14:20:34.28#ibcon#about to read 3, iclass 13, count 0 2006.257.14:20:34.30#ibcon#read 3, iclass 13, count 0 2006.257.14:20:34.30#ibcon#about to read 4, iclass 13, count 0 2006.257.14:20:34.30#ibcon#read 4, iclass 13, count 0 2006.257.14:20:34.30#ibcon#about to read 5, iclass 13, count 0 2006.257.14:20:34.30#ibcon#read 5, iclass 13, count 0 2006.257.14:20:34.30#ibcon#about to read 6, iclass 13, count 0 2006.257.14:20:34.30#ibcon#read 6, iclass 13, count 0 2006.257.14:20:34.30#ibcon#end of sib2, iclass 13, count 0 2006.257.14:20:34.30#ibcon#*mode == 0, iclass 13, count 0 2006.257.14:20:34.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.14:20:34.30#ibcon#[25=USB\r\n] 2006.257.14:20:34.30#ibcon#*before write, iclass 13, count 0 2006.257.14:20:34.30#ibcon#enter sib2, iclass 13, count 0 2006.257.14:20:34.30#ibcon#flushed, iclass 13, count 0 2006.257.14:20:34.30#ibcon#about to write, iclass 13, count 0 2006.257.14:20:34.30#ibcon#wrote, iclass 13, count 0 2006.257.14:20:34.30#ibcon#about to read 3, iclass 13, count 0 2006.257.14:20:34.33#ibcon#read 3, iclass 13, count 0 2006.257.14:20:34.33#ibcon#about to read 4, iclass 13, count 0 2006.257.14:20:34.33#ibcon#read 4, iclass 13, count 0 2006.257.14:20:34.33#ibcon#about to read 5, iclass 13, count 0 2006.257.14:20:34.33#ibcon#read 5, iclass 13, count 0 2006.257.14:20:34.33#ibcon#about to read 6, iclass 13, count 0 2006.257.14:20:34.33#ibcon#read 6, iclass 13, count 0 2006.257.14:20:34.33#ibcon#end of sib2, iclass 13, count 0 2006.257.14:20:34.33#ibcon#*after write, iclass 13, count 0 2006.257.14:20:34.33#ibcon#*before return 0, iclass 13, count 0 2006.257.14:20:34.33#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:34.33#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:34.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.14:20:34.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.14:20:34.33$vck44/valo=6,814.99 2006.257.14:20:34.33#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.14:20:34.33#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.14:20:34.33#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:34.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:34.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:34.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:34.33#ibcon#enter wrdev, iclass 15, count 0 2006.257.14:20:34.33#ibcon#first serial, iclass 15, count 0 2006.257.14:20:34.33#ibcon#enter sib2, iclass 15, count 0 2006.257.14:20:34.33#ibcon#flushed, iclass 15, count 0 2006.257.14:20:34.33#ibcon#about to write, iclass 15, count 0 2006.257.14:20:34.33#ibcon#wrote, iclass 15, count 0 2006.257.14:20:34.33#ibcon#about to read 3, iclass 15, count 0 2006.257.14:20:34.35#ibcon#read 3, iclass 15, count 0 2006.257.14:20:34.35#ibcon#about to read 4, iclass 15, count 0 2006.257.14:20:34.35#ibcon#read 4, iclass 15, count 0 2006.257.14:20:34.35#ibcon#about to read 5, iclass 15, count 0 2006.257.14:20:34.35#ibcon#read 5, iclass 15, count 0 2006.257.14:20:34.35#ibcon#about to read 6, iclass 15, count 0 2006.257.14:20:34.35#ibcon#read 6, iclass 15, count 0 2006.257.14:20:34.35#ibcon#end of sib2, iclass 15, count 0 2006.257.14:20:34.35#ibcon#*mode == 0, iclass 15, count 0 2006.257.14:20:34.35#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.14:20:34.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:20:34.35#ibcon#*before write, iclass 15, count 0 2006.257.14:20:34.35#ibcon#enter sib2, iclass 15, count 0 2006.257.14:20:34.35#ibcon#flushed, iclass 15, count 0 2006.257.14:20:34.35#ibcon#about to write, iclass 15, count 0 2006.257.14:20:34.35#ibcon#wrote, iclass 15, count 0 2006.257.14:20:34.35#ibcon#about to read 3, iclass 15, count 0 2006.257.14:20:34.39#ibcon#read 3, iclass 15, count 0 2006.257.14:20:34.39#ibcon#about to read 4, iclass 15, count 0 2006.257.14:20:34.39#ibcon#read 4, iclass 15, count 0 2006.257.14:20:34.39#ibcon#about to read 5, iclass 15, count 0 2006.257.14:20:34.39#ibcon#read 5, iclass 15, count 0 2006.257.14:20:34.39#ibcon#about to read 6, iclass 15, count 0 2006.257.14:20:34.39#ibcon#read 6, iclass 15, count 0 2006.257.14:20:34.39#ibcon#end of sib2, iclass 15, count 0 2006.257.14:20:34.39#ibcon#*after write, iclass 15, count 0 2006.257.14:20:34.39#ibcon#*before return 0, iclass 15, count 0 2006.257.14:20:34.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:34.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:34.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.14:20:34.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.14:20:34.39$vck44/va=6,4 2006.257.14:20:34.39#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.14:20:34.39#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.14:20:34.39#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:34.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:34.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:34.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:34.45#ibcon#enter wrdev, iclass 17, count 2 2006.257.14:20:34.45#ibcon#first serial, iclass 17, count 2 2006.257.14:20:34.45#ibcon#enter sib2, iclass 17, count 2 2006.257.14:20:34.45#ibcon#flushed, iclass 17, count 2 2006.257.14:20:34.45#ibcon#about to write, iclass 17, count 2 2006.257.14:20:34.45#ibcon#wrote, iclass 17, count 2 2006.257.14:20:34.45#ibcon#about to read 3, iclass 17, count 2 2006.257.14:20:34.47#ibcon#read 3, iclass 17, count 2 2006.257.14:20:34.47#ibcon#about to read 4, iclass 17, count 2 2006.257.14:20:34.47#ibcon#read 4, iclass 17, count 2 2006.257.14:20:34.47#ibcon#about to read 5, iclass 17, count 2 2006.257.14:20:34.47#ibcon#read 5, iclass 17, count 2 2006.257.14:20:34.47#ibcon#about to read 6, iclass 17, count 2 2006.257.14:20:34.47#ibcon#read 6, iclass 17, count 2 2006.257.14:20:34.47#ibcon#end of sib2, iclass 17, count 2 2006.257.14:20:34.47#ibcon#*mode == 0, iclass 17, count 2 2006.257.14:20:34.47#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.14:20:34.47#ibcon#[25=AT06-04\r\n] 2006.257.14:20:34.47#ibcon#*before write, iclass 17, count 2 2006.257.14:20:34.47#ibcon#enter sib2, iclass 17, count 2 2006.257.14:20:34.47#ibcon#flushed, iclass 17, count 2 2006.257.14:20:34.47#ibcon#about to write, iclass 17, count 2 2006.257.14:20:34.47#ibcon#wrote, iclass 17, count 2 2006.257.14:20:34.47#ibcon#about to read 3, iclass 17, count 2 2006.257.14:20:34.50#ibcon#read 3, iclass 17, count 2 2006.257.14:20:34.50#ibcon#about to read 4, iclass 17, count 2 2006.257.14:20:34.50#ibcon#read 4, iclass 17, count 2 2006.257.14:20:34.50#ibcon#about to read 5, iclass 17, count 2 2006.257.14:20:34.50#ibcon#read 5, iclass 17, count 2 2006.257.14:20:34.50#ibcon#about to read 6, iclass 17, count 2 2006.257.14:20:34.50#ibcon#read 6, iclass 17, count 2 2006.257.14:20:34.50#ibcon#end of sib2, iclass 17, count 2 2006.257.14:20:34.50#ibcon#*after write, iclass 17, count 2 2006.257.14:20:34.50#ibcon#*before return 0, iclass 17, count 2 2006.257.14:20:34.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:34.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:34.50#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.14:20:34.50#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:34.50#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:34.62#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:34.62#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:34.62#ibcon#enter wrdev, iclass 17, count 0 2006.257.14:20:34.62#ibcon#first serial, iclass 17, count 0 2006.257.14:20:34.62#ibcon#enter sib2, iclass 17, count 0 2006.257.14:20:34.62#ibcon#flushed, iclass 17, count 0 2006.257.14:20:34.62#ibcon#about to write, iclass 17, count 0 2006.257.14:20:34.62#ibcon#wrote, iclass 17, count 0 2006.257.14:20:34.62#ibcon#about to read 3, iclass 17, count 0 2006.257.14:20:34.64#ibcon#read 3, iclass 17, count 0 2006.257.14:20:34.64#ibcon#about to read 4, iclass 17, count 0 2006.257.14:20:34.64#ibcon#read 4, iclass 17, count 0 2006.257.14:20:34.64#ibcon#about to read 5, iclass 17, count 0 2006.257.14:20:34.64#ibcon#read 5, iclass 17, count 0 2006.257.14:20:34.64#ibcon#about to read 6, iclass 17, count 0 2006.257.14:20:34.64#ibcon#read 6, iclass 17, count 0 2006.257.14:20:34.64#ibcon#end of sib2, iclass 17, count 0 2006.257.14:20:34.64#ibcon#*mode == 0, iclass 17, count 0 2006.257.14:20:34.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.14:20:34.64#ibcon#[25=USB\r\n] 2006.257.14:20:34.64#ibcon#*before write, iclass 17, count 0 2006.257.14:20:34.64#ibcon#enter sib2, iclass 17, count 0 2006.257.14:20:34.64#ibcon#flushed, iclass 17, count 0 2006.257.14:20:34.64#ibcon#about to write, iclass 17, count 0 2006.257.14:20:34.64#ibcon#wrote, iclass 17, count 0 2006.257.14:20:34.64#ibcon#about to read 3, iclass 17, count 0 2006.257.14:20:34.67#ibcon#read 3, iclass 17, count 0 2006.257.14:20:34.67#ibcon#about to read 4, iclass 17, count 0 2006.257.14:20:34.67#ibcon#read 4, iclass 17, count 0 2006.257.14:20:34.67#ibcon#about to read 5, iclass 17, count 0 2006.257.14:20:34.67#ibcon#read 5, iclass 17, count 0 2006.257.14:20:34.67#ibcon#about to read 6, iclass 17, count 0 2006.257.14:20:34.67#ibcon#read 6, iclass 17, count 0 2006.257.14:20:34.67#ibcon#end of sib2, iclass 17, count 0 2006.257.14:20:34.67#ibcon#*after write, iclass 17, count 0 2006.257.14:20:34.67#ibcon#*before return 0, iclass 17, count 0 2006.257.14:20:34.67#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:34.67#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:34.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.14:20:34.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.14:20:34.67$vck44/valo=7,864.99 2006.257.14:20:34.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.14:20:34.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.14:20:34.67#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:34.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:34.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:34.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:34.67#ibcon#enter wrdev, iclass 19, count 0 2006.257.14:20:34.67#ibcon#first serial, iclass 19, count 0 2006.257.14:20:34.67#ibcon#enter sib2, iclass 19, count 0 2006.257.14:20:34.67#ibcon#flushed, iclass 19, count 0 2006.257.14:20:34.67#ibcon#about to write, iclass 19, count 0 2006.257.14:20:34.67#ibcon#wrote, iclass 19, count 0 2006.257.14:20:34.67#ibcon#about to read 3, iclass 19, count 0 2006.257.14:20:34.69#ibcon#read 3, iclass 19, count 0 2006.257.14:20:34.69#ibcon#about to read 4, iclass 19, count 0 2006.257.14:20:34.69#ibcon#read 4, iclass 19, count 0 2006.257.14:20:34.69#ibcon#about to read 5, iclass 19, count 0 2006.257.14:20:34.69#ibcon#read 5, iclass 19, count 0 2006.257.14:20:34.69#ibcon#about to read 6, iclass 19, count 0 2006.257.14:20:34.69#ibcon#read 6, iclass 19, count 0 2006.257.14:20:34.69#ibcon#end of sib2, iclass 19, count 0 2006.257.14:20:34.69#ibcon#*mode == 0, iclass 19, count 0 2006.257.14:20:34.69#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.14:20:34.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:20:34.69#ibcon#*before write, iclass 19, count 0 2006.257.14:20:34.69#ibcon#enter sib2, iclass 19, count 0 2006.257.14:20:34.69#ibcon#flushed, iclass 19, count 0 2006.257.14:20:34.69#ibcon#about to write, iclass 19, count 0 2006.257.14:20:34.69#ibcon#wrote, iclass 19, count 0 2006.257.14:20:34.69#ibcon#about to read 3, iclass 19, count 0 2006.257.14:20:34.73#ibcon#read 3, iclass 19, count 0 2006.257.14:20:34.73#ibcon#about to read 4, iclass 19, count 0 2006.257.14:20:34.73#ibcon#read 4, iclass 19, count 0 2006.257.14:20:34.73#ibcon#about to read 5, iclass 19, count 0 2006.257.14:20:34.73#ibcon#read 5, iclass 19, count 0 2006.257.14:20:34.73#ibcon#about to read 6, iclass 19, count 0 2006.257.14:20:34.73#ibcon#read 6, iclass 19, count 0 2006.257.14:20:34.73#ibcon#end of sib2, iclass 19, count 0 2006.257.14:20:34.73#ibcon#*after write, iclass 19, count 0 2006.257.14:20:34.73#ibcon#*before return 0, iclass 19, count 0 2006.257.14:20:34.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:34.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:34.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.14:20:34.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.14:20:34.73$vck44/va=7,4 2006.257.14:20:34.73#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.14:20:34.73#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.14:20:34.73#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:34.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:34.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:34.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:34.79#ibcon#enter wrdev, iclass 21, count 2 2006.257.14:20:34.79#ibcon#first serial, iclass 21, count 2 2006.257.14:20:34.79#ibcon#enter sib2, iclass 21, count 2 2006.257.14:20:34.79#ibcon#flushed, iclass 21, count 2 2006.257.14:20:34.79#ibcon#about to write, iclass 21, count 2 2006.257.14:20:34.79#ibcon#wrote, iclass 21, count 2 2006.257.14:20:34.79#ibcon#about to read 3, iclass 21, count 2 2006.257.14:20:34.81#ibcon#read 3, iclass 21, count 2 2006.257.14:20:34.81#ibcon#about to read 4, iclass 21, count 2 2006.257.14:20:34.81#ibcon#read 4, iclass 21, count 2 2006.257.14:20:34.81#ibcon#about to read 5, iclass 21, count 2 2006.257.14:20:34.81#ibcon#read 5, iclass 21, count 2 2006.257.14:20:34.81#ibcon#about to read 6, iclass 21, count 2 2006.257.14:20:34.81#ibcon#read 6, iclass 21, count 2 2006.257.14:20:34.81#ibcon#end of sib2, iclass 21, count 2 2006.257.14:20:34.81#ibcon#*mode == 0, iclass 21, count 2 2006.257.14:20:34.81#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.14:20:34.81#ibcon#[25=AT07-04\r\n] 2006.257.14:20:34.81#ibcon#*before write, iclass 21, count 2 2006.257.14:20:34.81#ibcon#enter sib2, iclass 21, count 2 2006.257.14:20:34.81#ibcon#flushed, iclass 21, count 2 2006.257.14:20:34.81#ibcon#about to write, iclass 21, count 2 2006.257.14:20:34.81#ibcon#wrote, iclass 21, count 2 2006.257.14:20:34.81#ibcon#about to read 3, iclass 21, count 2 2006.257.14:20:34.84#ibcon#read 3, iclass 21, count 2 2006.257.14:20:34.84#ibcon#about to read 4, iclass 21, count 2 2006.257.14:20:35.70#ibcon#read 4, iclass 21, count 2 2006.257.14:20:35.70#ibcon#about to read 5, iclass 21, count 2 2006.257.14:20:35.70#ibcon#read 5, iclass 21, count 2 2006.257.14:20:35.70#ibcon#about to read 6, iclass 21, count 2 2006.257.14:20:35.70#ibcon#read 6, iclass 21, count 2 2006.257.14:20:35.70#ibcon#end of sib2, iclass 21, count 2 2006.257.14:20:35.70#ibcon#*after write, iclass 21, count 2 2006.257.14:20:35.70#ibcon#*before return 0, iclass 21, count 2 2006.257.14:20:35.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:35.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:35.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.14:20:35.70#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:35.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:35.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:35.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:35.82#ibcon#enter wrdev, iclass 21, count 0 2006.257.14:20:35.82#ibcon#first serial, iclass 21, count 0 2006.257.14:20:35.82#ibcon#enter sib2, iclass 21, count 0 2006.257.14:20:35.82#ibcon#flushed, iclass 21, count 0 2006.257.14:20:35.82#ibcon#about to write, iclass 21, count 0 2006.257.14:20:35.82#ibcon#wrote, iclass 21, count 0 2006.257.14:20:35.82#ibcon#about to read 3, iclass 21, count 0 2006.257.14:20:35.84#ibcon#read 3, iclass 21, count 0 2006.257.14:20:35.84#ibcon#about to read 4, iclass 21, count 0 2006.257.14:20:35.84#ibcon#read 4, iclass 21, count 0 2006.257.14:20:35.84#ibcon#about to read 5, iclass 21, count 0 2006.257.14:20:35.84#ibcon#read 5, iclass 21, count 0 2006.257.14:20:35.84#ibcon#about to read 6, iclass 21, count 0 2006.257.14:20:35.84#ibcon#read 6, iclass 21, count 0 2006.257.14:20:35.84#ibcon#end of sib2, iclass 21, count 0 2006.257.14:20:35.84#ibcon#*mode == 0, iclass 21, count 0 2006.257.14:20:35.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.14:20:35.84#ibcon#[25=USB\r\n] 2006.257.14:20:35.84#ibcon#*before write, iclass 21, count 0 2006.257.14:20:35.84#ibcon#enter sib2, iclass 21, count 0 2006.257.14:20:35.84#ibcon#flushed, iclass 21, count 0 2006.257.14:20:35.84#ibcon#about to write, iclass 21, count 0 2006.257.14:20:35.84#ibcon#wrote, iclass 21, count 0 2006.257.14:20:35.84#ibcon#about to read 3, iclass 21, count 0 2006.257.14:20:35.87#ibcon#read 3, iclass 21, count 0 2006.257.14:20:35.87#ibcon#about to read 4, iclass 21, count 0 2006.257.14:20:35.87#ibcon#read 4, iclass 21, count 0 2006.257.14:20:35.87#ibcon#about to read 5, iclass 21, count 0 2006.257.14:20:35.87#ibcon#read 5, iclass 21, count 0 2006.257.14:20:35.87#ibcon#about to read 6, iclass 21, count 0 2006.257.14:20:35.87#ibcon#read 6, iclass 21, count 0 2006.257.14:20:35.87#ibcon#end of sib2, iclass 21, count 0 2006.257.14:20:35.87#ibcon#*after write, iclass 21, count 0 2006.257.14:20:35.87#ibcon#*before return 0, iclass 21, count 0 2006.257.14:20:35.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:35.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:35.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.14:20:35.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.14:20:35.87$vck44/valo=8,884.99 2006.257.14:20:35.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.14:20:35.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.14:20:35.87#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:35.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:35.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:35.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:35.87#ibcon#enter wrdev, iclass 23, count 0 2006.257.14:20:35.87#ibcon#first serial, iclass 23, count 0 2006.257.14:20:35.87#ibcon#enter sib2, iclass 23, count 0 2006.257.14:20:35.87#ibcon#flushed, iclass 23, count 0 2006.257.14:20:35.87#ibcon#about to write, iclass 23, count 0 2006.257.14:20:35.87#ibcon#wrote, iclass 23, count 0 2006.257.14:20:35.87#ibcon#about to read 3, iclass 23, count 0 2006.257.14:20:35.89#ibcon#read 3, iclass 23, count 0 2006.257.14:20:35.89#ibcon#about to read 4, iclass 23, count 0 2006.257.14:20:35.89#ibcon#read 4, iclass 23, count 0 2006.257.14:20:35.89#ibcon#about to read 5, iclass 23, count 0 2006.257.14:20:35.89#ibcon#read 5, iclass 23, count 0 2006.257.14:20:35.89#ibcon#about to read 6, iclass 23, count 0 2006.257.14:20:35.89#ibcon#read 6, iclass 23, count 0 2006.257.14:20:35.89#ibcon#end of sib2, iclass 23, count 0 2006.257.14:20:35.89#ibcon#*mode == 0, iclass 23, count 0 2006.257.14:20:35.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.14:20:35.89#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:20:35.89#ibcon#*before write, iclass 23, count 0 2006.257.14:20:35.89#ibcon#enter sib2, iclass 23, count 0 2006.257.14:20:35.89#ibcon#flushed, iclass 23, count 0 2006.257.14:20:35.89#ibcon#about to write, iclass 23, count 0 2006.257.14:20:35.89#ibcon#wrote, iclass 23, count 0 2006.257.14:20:35.89#ibcon#about to read 3, iclass 23, count 0 2006.257.14:20:35.93#ibcon#read 3, iclass 23, count 0 2006.257.14:20:35.93#ibcon#about to read 4, iclass 23, count 0 2006.257.14:20:35.93#ibcon#read 4, iclass 23, count 0 2006.257.14:20:35.93#ibcon#about to read 5, iclass 23, count 0 2006.257.14:20:35.93#ibcon#read 5, iclass 23, count 0 2006.257.14:20:35.93#ibcon#about to read 6, iclass 23, count 0 2006.257.14:20:35.93#ibcon#read 6, iclass 23, count 0 2006.257.14:20:35.93#ibcon#end of sib2, iclass 23, count 0 2006.257.14:20:35.93#ibcon#*after write, iclass 23, count 0 2006.257.14:20:35.93#ibcon#*before return 0, iclass 23, count 0 2006.257.14:20:35.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:35.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:35.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.14:20:35.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.14:20:35.93$vck44/va=8,4 2006.257.14:20:35.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.14:20:35.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.14:20:35.93#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:35.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:20:35.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:20:35.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:20:35.99#ibcon#enter wrdev, iclass 25, count 2 2006.257.14:20:35.99#ibcon#first serial, iclass 25, count 2 2006.257.14:20:35.99#ibcon#enter sib2, iclass 25, count 2 2006.257.14:20:35.99#ibcon#flushed, iclass 25, count 2 2006.257.14:20:35.99#ibcon#about to write, iclass 25, count 2 2006.257.14:20:35.99#ibcon#wrote, iclass 25, count 2 2006.257.14:20:35.99#ibcon#about to read 3, iclass 25, count 2 2006.257.14:20:36.01#ibcon#read 3, iclass 25, count 2 2006.257.14:20:36.01#ibcon#about to read 4, iclass 25, count 2 2006.257.14:20:36.01#ibcon#read 4, iclass 25, count 2 2006.257.14:20:36.01#ibcon#about to read 5, iclass 25, count 2 2006.257.14:20:36.01#ibcon#read 5, iclass 25, count 2 2006.257.14:20:36.01#ibcon#about to read 6, iclass 25, count 2 2006.257.14:20:36.01#ibcon#read 6, iclass 25, count 2 2006.257.14:20:36.01#ibcon#end of sib2, iclass 25, count 2 2006.257.14:20:36.01#ibcon#*mode == 0, iclass 25, count 2 2006.257.14:20:36.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.14:20:36.01#ibcon#[25=AT08-04\r\n] 2006.257.14:20:36.01#ibcon#*before write, iclass 25, count 2 2006.257.14:20:36.01#ibcon#enter sib2, iclass 25, count 2 2006.257.14:20:36.01#ibcon#flushed, iclass 25, count 2 2006.257.14:20:36.01#ibcon#about to write, iclass 25, count 2 2006.257.14:20:36.01#ibcon#wrote, iclass 25, count 2 2006.257.14:20:36.01#ibcon#about to read 3, iclass 25, count 2 2006.257.14:20:36.04#ibcon#read 3, iclass 25, count 2 2006.257.14:20:36.04#ibcon#about to read 4, iclass 25, count 2 2006.257.14:20:36.04#ibcon#read 4, iclass 25, count 2 2006.257.14:20:36.04#ibcon#about to read 5, iclass 25, count 2 2006.257.14:20:36.04#ibcon#read 5, iclass 25, count 2 2006.257.14:20:36.04#ibcon#about to read 6, iclass 25, count 2 2006.257.14:20:36.04#ibcon#read 6, iclass 25, count 2 2006.257.14:20:36.04#ibcon#end of sib2, iclass 25, count 2 2006.257.14:20:36.04#ibcon#*after write, iclass 25, count 2 2006.257.14:20:36.04#ibcon#*before return 0, iclass 25, count 2 2006.257.14:20:36.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:20:36.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.14:20:36.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.14:20:36.04#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:36.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:20:36.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:20:36.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:20:36.16#ibcon#enter wrdev, iclass 25, count 0 2006.257.14:20:36.16#ibcon#first serial, iclass 25, count 0 2006.257.14:20:36.16#ibcon#enter sib2, iclass 25, count 0 2006.257.14:20:36.16#ibcon#flushed, iclass 25, count 0 2006.257.14:20:36.16#ibcon#about to write, iclass 25, count 0 2006.257.14:20:36.16#ibcon#wrote, iclass 25, count 0 2006.257.14:20:36.16#ibcon#about to read 3, iclass 25, count 0 2006.257.14:20:36.18#ibcon#read 3, iclass 25, count 0 2006.257.14:20:36.18#ibcon#about to read 4, iclass 25, count 0 2006.257.14:20:36.18#ibcon#read 4, iclass 25, count 0 2006.257.14:20:36.18#ibcon#about to read 5, iclass 25, count 0 2006.257.14:20:36.18#ibcon#read 5, iclass 25, count 0 2006.257.14:20:36.18#ibcon#about to read 6, iclass 25, count 0 2006.257.14:20:36.18#ibcon#read 6, iclass 25, count 0 2006.257.14:20:36.18#ibcon#end of sib2, iclass 25, count 0 2006.257.14:20:36.18#ibcon#*mode == 0, iclass 25, count 0 2006.257.14:20:36.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.14:20:36.18#ibcon#[25=USB\r\n] 2006.257.14:20:36.18#ibcon#*before write, iclass 25, count 0 2006.257.14:20:36.18#ibcon#enter sib2, iclass 25, count 0 2006.257.14:20:36.18#ibcon#flushed, iclass 25, count 0 2006.257.14:20:36.18#ibcon#about to write, iclass 25, count 0 2006.257.14:20:36.18#ibcon#wrote, iclass 25, count 0 2006.257.14:20:36.18#ibcon#about to read 3, iclass 25, count 0 2006.257.14:20:36.21#ibcon#read 3, iclass 25, count 0 2006.257.14:20:36.21#ibcon#about to read 4, iclass 25, count 0 2006.257.14:20:36.21#ibcon#read 4, iclass 25, count 0 2006.257.14:20:36.21#ibcon#about to read 5, iclass 25, count 0 2006.257.14:20:36.21#ibcon#read 5, iclass 25, count 0 2006.257.14:20:36.21#ibcon#about to read 6, iclass 25, count 0 2006.257.14:20:36.21#ibcon#read 6, iclass 25, count 0 2006.257.14:20:36.21#ibcon#end of sib2, iclass 25, count 0 2006.257.14:20:36.21#ibcon#*after write, iclass 25, count 0 2006.257.14:20:36.21#ibcon#*before return 0, iclass 25, count 0 2006.257.14:20:36.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:20:36.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.14:20:36.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.14:20:36.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.14:20:36.21$vck44/vblo=1,629.99 2006.257.14:20:36.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.14:20:36.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.14:20:36.21#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:36.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:20:36.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:20:36.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:20:36.21#ibcon#enter wrdev, iclass 27, count 0 2006.257.14:20:36.21#ibcon#first serial, iclass 27, count 0 2006.257.14:20:36.21#ibcon#enter sib2, iclass 27, count 0 2006.257.14:20:36.21#ibcon#flushed, iclass 27, count 0 2006.257.14:20:36.21#ibcon#about to write, iclass 27, count 0 2006.257.14:20:36.21#ibcon#wrote, iclass 27, count 0 2006.257.14:20:36.21#ibcon#about to read 3, iclass 27, count 0 2006.257.14:20:36.23#ibcon#read 3, iclass 27, count 0 2006.257.14:20:36.23#ibcon#about to read 4, iclass 27, count 0 2006.257.14:20:36.23#ibcon#read 4, iclass 27, count 0 2006.257.14:20:36.23#ibcon#about to read 5, iclass 27, count 0 2006.257.14:20:36.23#ibcon#read 5, iclass 27, count 0 2006.257.14:20:36.23#ibcon#about to read 6, iclass 27, count 0 2006.257.14:20:36.23#ibcon#read 6, iclass 27, count 0 2006.257.14:20:36.23#ibcon#end of sib2, iclass 27, count 0 2006.257.14:20:36.23#ibcon#*mode == 0, iclass 27, count 0 2006.257.14:20:36.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.14:20:36.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:20:36.23#ibcon#*before write, iclass 27, count 0 2006.257.14:20:36.23#ibcon#enter sib2, iclass 27, count 0 2006.257.14:20:36.23#ibcon#flushed, iclass 27, count 0 2006.257.14:20:36.23#ibcon#about to write, iclass 27, count 0 2006.257.14:20:36.23#ibcon#wrote, iclass 27, count 0 2006.257.14:20:36.23#ibcon#about to read 3, iclass 27, count 0 2006.257.14:20:36.27#ibcon#read 3, iclass 27, count 0 2006.257.14:20:36.27#ibcon#about to read 4, iclass 27, count 0 2006.257.14:20:36.27#ibcon#read 4, iclass 27, count 0 2006.257.14:20:36.27#ibcon#about to read 5, iclass 27, count 0 2006.257.14:20:36.27#ibcon#read 5, iclass 27, count 0 2006.257.14:20:36.27#ibcon#about to read 6, iclass 27, count 0 2006.257.14:20:36.27#ibcon#read 6, iclass 27, count 0 2006.257.14:20:36.27#ibcon#end of sib2, iclass 27, count 0 2006.257.14:20:36.27#ibcon#*after write, iclass 27, count 0 2006.257.14:20:36.27#ibcon#*before return 0, iclass 27, count 0 2006.257.14:20:36.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:20:36.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:20:36.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.14:20:36.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.14:20:36.27$vck44/vb=1,4 2006.257.14:20:36.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.14:20:36.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.14:20:36.27#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:36.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:20:36.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:20:36.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:20:36.27#ibcon#enter wrdev, iclass 29, count 2 2006.257.14:20:36.27#ibcon#first serial, iclass 29, count 2 2006.257.14:20:36.27#ibcon#enter sib2, iclass 29, count 2 2006.257.14:20:36.27#ibcon#flushed, iclass 29, count 2 2006.257.14:20:36.27#ibcon#about to write, iclass 29, count 2 2006.257.14:20:36.27#ibcon#wrote, iclass 29, count 2 2006.257.14:20:36.27#ibcon#about to read 3, iclass 29, count 2 2006.257.14:20:36.29#ibcon#read 3, iclass 29, count 2 2006.257.14:20:36.29#ibcon#about to read 4, iclass 29, count 2 2006.257.14:20:36.29#ibcon#read 4, iclass 29, count 2 2006.257.14:20:36.29#ibcon#about to read 5, iclass 29, count 2 2006.257.14:20:36.29#ibcon#read 5, iclass 29, count 2 2006.257.14:20:36.29#ibcon#about to read 6, iclass 29, count 2 2006.257.14:20:36.29#ibcon#read 6, iclass 29, count 2 2006.257.14:20:36.29#ibcon#end of sib2, iclass 29, count 2 2006.257.14:20:36.29#ibcon#*mode == 0, iclass 29, count 2 2006.257.14:20:36.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.14:20:36.29#ibcon#[27=AT01-04\r\n] 2006.257.14:20:36.29#ibcon#*before write, iclass 29, count 2 2006.257.14:20:36.29#ibcon#enter sib2, iclass 29, count 2 2006.257.14:20:36.29#ibcon#flushed, iclass 29, count 2 2006.257.14:20:36.29#ibcon#about to write, iclass 29, count 2 2006.257.14:20:36.29#ibcon#wrote, iclass 29, count 2 2006.257.14:20:36.29#ibcon#about to read 3, iclass 29, count 2 2006.257.14:20:36.32#ibcon#read 3, iclass 29, count 2 2006.257.14:20:36.32#ibcon#about to read 4, iclass 29, count 2 2006.257.14:20:36.32#ibcon#read 4, iclass 29, count 2 2006.257.14:20:36.32#ibcon#about to read 5, iclass 29, count 2 2006.257.14:20:36.32#ibcon#read 5, iclass 29, count 2 2006.257.14:20:36.32#ibcon#about to read 6, iclass 29, count 2 2006.257.14:20:36.32#ibcon#read 6, iclass 29, count 2 2006.257.14:20:36.32#ibcon#end of sib2, iclass 29, count 2 2006.257.14:20:36.32#ibcon#*after write, iclass 29, count 2 2006.257.14:20:36.32#ibcon#*before return 0, iclass 29, count 2 2006.257.14:20:36.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:20:36.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.14:20:36.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.14:20:36.32#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:36.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:20:36.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:20:36.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:20:36.44#ibcon#enter wrdev, iclass 29, count 0 2006.257.14:20:36.44#ibcon#first serial, iclass 29, count 0 2006.257.14:20:36.44#ibcon#enter sib2, iclass 29, count 0 2006.257.14:20:36.44#ibcon#flushed, iclass 29, count 0 2006.257.14:20:36.44#ibcon#about to write, iclass 29, count 0 2006.257.14:20:36.44#ibcon#wrote, iclass 29, count 0 2006.257.14:20:36.44#ibcon#about to read 3, iclass 29, count 0 2006.257.14:20:36.46#ibcon#read 3, iclass 29, count 0 2006.257.14:20:36.46#ibcon#about to read 4, iclass 29, count 0 2006.257.14:20:36.46#ibcon#read 4, iclass 29, count 0 2006.257.14:20:36.46#ibcon#about to read 5, iclass 29, count 0 2006.257.14:20:36.46#ibcon#read 5, iclass 29, count 0 2006.257.14:20:36.46#ibcon#about to read 6, iclass 29, count 0 2006.257.14:20:36.46#ibcon#read 6, iclass 29, count 0 2006.257.14:20:36.46#ibcon#end of sib2, iclass 29, count 0 2006.257.14:20:36.46#ibcon#*mode == 0, iclass 29, count 0 2006.257.14:20:36.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.14:20:36.46#ibcon#[27=USB\r\n] 2006.257.14:20:36.46#ibcon#*before write, iclass 29, count 0 2006.257.14:20:36.46#ibcon#enter sib2, iclass 29, count 0 2006.257.14:20:36.46#ibcon#flushed, iclass 29, count 0 2006.257.14:20:36.46#ibcon#about to write, iclass 29, count 0 2006.257.14:20:36.46#ibcon#wrote, iclass 29, count 0 2006.257.14:20:36.46#ibcon#about to read 3, iclass 29, count 0 2006.257.14:20:36.49#ibcon#read 3, iclass 29, count 0 2006.257.14:20:36.49#ibcon#about to read 4, iclass 29, count 0 2006.257.14:20:36.49#ibcon#read 4, iclass 29, count 0 2006.257.14:20:36.49#ibcon#about to read 5, iclass 29, count 0 2006.257.14:20:36.49#ibcon#read 5, iclass 29, count 0 2006.257.14:20:36.49#ibcon#about to read 6, iclass 29, count 0 2006.257.14:20:36.49#ibcon#read 6, iclass 29, count 0 2006.257.14:20:36.49#ibcon#end of sib2, iclass 29, count 0 2006.257.14:20:36.49#ibcon#*after write, iclass 29, count 0 2006.257.14:20:36.49#ibcon#*before return 0, iclass 29, count 0 2006.257.14:20:36.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:20:36.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.14:20:36.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.14:20:36.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.14:20:36.49$vck44/vblo=2,634.99 2006.257.14:20:36.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.14:20:36.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.14:20:36.49#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:36.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:36.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:36.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:36.49#ibcon#enter wrdev, iclass 31, count 0 2006.257.14:20:36.49#ibcon#first serial, iclass 31, count 0 2006.257.14:20:36.49#ibcon#enter sib2, iclass 31, count 0 2006.257.14:20:36.49#ibcon#flushed, iclass 31, count 0 2006.257.14:20:36.49#ibcon#about to write, iclass 31, count 0 2006.257.14:20:36.49#ibcon#wrote, iclass 31, count 0 2006.257.14:20:36.49#ibcon#about to read 3, iclass 31, count 0 2006.257.14:20:36.51#ibcon#read 3, iclass 31, count 0 2006.257.14:20:36.51#ibcon#about to read 4, iclass 31, count 0 2006.257.14:20:36.51#ibcon#read 4, iclass 31, count 0 2006.257.14:20:36.51#ibcon#about to read 5, iclass 31, count 0 2006.257.14:20:36.51#ibcon#read 5, iclass 31, count 0 2006.257.14:20:36.51#ibcon#about to read 6, iclass 31, count 0 2006.257.14:20:36.51#ibcon#read 6, iclass 31, count 0 2006.257.14:20:36.51#ibcon#end of sib2, iclass 31, count 0 2006.257.14:20:36.51#ibcon#*mode == 0, iclass 31, count 0 2006.257.14:20:36.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.14:20:36.51#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:20:36.51#ibcon#*before write, iclass 31, count 0 2006.257.14:20:36.51#ibcon#enter sib2, iclass 31, count 0 2006.257.14:20:36.51#ibcon#flushed, iclass 31, count 0 2006.257.14:20:36.51#ibcon#about to write, iclass 31, count 0 2006.257.14:20:36.51#ibcon#wrote, iclass 31, count 0 2006.257.14:20:36.51#ibcon#about to read 3, iclass 31, count 0 2006.257.14:20:36.55#ibcon#read 3, iclass 31, count 0 2006.257.14:20:36.55#ibcon#about to read 4, iclass 31, count 0 2006.257.14:20:36.55#ibcon#read 4, iclass 31, count 0 2006.257.14:20:36.55#ibcon#about to read 5, iclass 31, count 0 2006.257.14:20:36.55#ibcon#read 5, iclass 31, count 0 2006.257.14:20:36.55#ibcon#about to read 6, iclass 31, count 0 2006.257.14:20:36.55#ibcon#read 6, iclass 31, count 0 2006.257.14:20:36.55#ibcon#end of sib2, iclass 31, count 0 2006.257.14:20:36.55#ibcon#*after write, iclass 31, count 0 2006.257.14:20:36.55#ibcon#*before return 0, iclass 31, count 0 2006.257.14:20:36.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:36.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.14:20:36.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.14:20:36.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.14:20:36.55$vck44/vb=2,5 2006.257.14:20:36.55#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.14:20:36.55#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.14:20:36.55#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:36.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:36.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:36.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:36.61#ibcon#enter wrdev, iclass 33, count 2 2006.257.14:20:36.61#ibcon#first serial, iclass 33, count 2 2006.257.14:20:36.61#ibcon#enter sib2, iclass 33, count 2 2006.257.14:20:36.61#ibcon#flushed, iclass 33, count 2 2006.257.14:20:36.61#ibcon#about to write, iclass 33, count 2 2006.257.14:20:36.61#ibcon#wrote, iclass 33, count 2 2006.257.14:20:36.61#ibcon#about to read 3, iclass 33, count 2 2006.257.14:20:36.63#ibcon#read 3, iclass 33, count 2 2006.257.14:20:36.63#ibcon#about to read 4, iclass 33, count 2 2006.257.14:20:36.63#ibcon#read 4, iclass 33, count 2 2006.257.14:20:36.63#ibcon#about to read 5, iclass 33, count 2 2006.257.14:20:36.63#ibcon#read 5, iclass 33, count 2 2006.257.14:20:36.63#ibcon#about to read 6, iclass 33, count 2 2006.257.14:20:36.63#ibcon#read 6, iclass 33, count 2 2006.257.14:20:36.63#ibcon#end of sib2, iclass 33, count 2 2006.257.14:20:36.63#ibcon#*mode == 0, iclass 33, count 2 2006.257.14:20:36.63#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.14:20:36.63#ibcon#[27=AT02-05\r\n] 2006.257.14:20:36.63#ibcon#*before write, iclass 33, count 2 2006.257.14:20:36.63#ibcon#enter sib2, iclass 33, count 2 2006.257.14:20:36.63#ibcon#flushed, iclass 33, count 2 2006.257.14:20:36.63#ibcon#about to write, iclass 33, count 2 2006.257.14:20:36.63#ibcon#wrote, iclass 33, count 2 2006.257.14:20:36.63#ibcon#about to read 3, iclass 33, count 2 2006.257.14:20:36.66#ibcon#read 3, iclass 33, count 2 2006.257.14:20:36.66#ibcon#about to read 4, iclass 33, count 2 2006.257.14:20:36.66#ibcon#read 4, iclass 33, count 2 2006.257.14:20:36.66#ibcon#about to read 5, iclass 33, count 2 2006.257.14:20:36.66#ibcon#read 5, iclass 33, count 2 2006.257.14:20:36.66#ibcon#about to read 6, iclass 33, count 2 2006.257.14:20:36.66#ibcon#read 6, iclass 33, count 2 2006.257.14:20:36.66#ibcon#end of sib2, iclass 33, count 2 2006.257.14:20:36.66#ibcon#*after write, iclass 33, count 2 2006.257.14:20:36.66#ibcon#*before return 0, iclass 33, count 2 2006.257.14:20:36.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:36.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.14:20:36.66#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.14:20:36.66#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:36.66#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:36.78#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:36.78#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:36.78#ibcon#enter wrdev, iclass 33, count 0 2006.257.14:20:36.78#ibcon#first serial, iclass 33, count 0 2006.257.14:20:36.78#ibcon#enter sib2, iclass 33, count 0 2006.257.14:20:36.78#ibcon#flushed, iclass 33, count 0 2006.257.14:20:36.78#ibcon#about to write, iclass 33, count 0 2006.257.14:20:36.78#ibcon#wrote, iclass 33, count 0 2006.257.14:20:36.78#ibcon#about to read 3, iclass 33, count 0 2006.257.14:20:36.80#ibcon#read 3, iclass 33, count 0 2006.257.14:20:36.80#ibcon#about to read 4, iclass 33, count 0 2006.257.14:20:36.80#ibcon#read 4, iclass 33, count 0 2006.257.14:20:36.80#ibcon#about to read 5, iclass 33, count 0 2006.257.14:20:36.80#ibcon#read 5, iclass 33, count 0 2006.257.14:20:36.80#ibcon#about to read 6, iclass 33, count 0 2006.257.14:20:36.80#ibcon#read 6, iclass 33, count 0 2006.257.14:20:36.80#ibcon#end of sib2, iclass 33, count 0 2006.257.14:20:36.80#ibcon#*mode == 0, iclass 33, count 0 2006.257.14:20:36.80#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.14:20:36.80#ibcon#[27=USB\r\n] 2006.257.14:20:36.80#ibcon#*before write, iclass 33, count 0 2006.257.14:20:36.80#ibcon#enter sib2, iclass 33, count 0 2006.257.14:20:36.80#ibcon#flushed, iclass 33, count 0 2006.257.14:20:36.80#ibcon#about to write, iclass 33, count 0 2006.257.14:20:36.80#ibcon#wrote, iclass 33, count 0 2006.257.14:20:36.80#ibcon#about to read 3, iclass 33, count 0 2006.257.14:20:36.83#ibcon#read 3, iclass 33, count 0 2006.257.14:20:36.83#ibcon#about to read 4, iclass 33, count 0 2006.257.14:20:36.83#ibcon#read 4, iclass 33, count 0 2006.257.14:20:36.83#ibcon#about to read 5, iclass 33, count 0 2006.257.14:20:36.83#ibcon#read 5, iclass 33, count 0 2006.257.14:20:36.83#ibcon#about to read 6, iclass 33, count 0 2006.257.14:20:36.83#ibcon#read 6, iclass 33, count 0 2006.257.14:20:36.83#ibcon#end of sib2, iclass 33, count 0 2006.257.14:20:36.83#ibcon#*after write, iclass 33, count 0 2006.257.14:20:36.83#ibcon#*before return 0, iclass 33, count 0 2006.257.14:20:36.83#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:36.83#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.14:20:36.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.14:20:36.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.14:20:36.83$vck44/vblo=3,649.99 2006.257.14:20:36.83#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.14:20:36.83#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.14:20:36.83#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:36.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:36.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:36.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:36.83#ibcon#enter wrdev, iclass 35, count 0 2006.257.14:20:36.83#ibcon#first serial, iclass 35, count 0 2006.257.14:20:36.83#ibcon#enter sib2, iclass 35, count 0 2006.257.14:20:36.83#ibcon#flushed, iclass 35, count 0 2006.257.14:20:36.83#ibcon#about to write, iclass 35, count 0 2006.257.14:20:36.83#ibcon#wrote, iclass 35, count 0 2006.257.14:20:36.83#ibcon#about to read 3, iclass 35, count 0 2006.257.14:20:37.63#ibcon#read 3, iclass 35, count 0 2006.257.14:20:37.63#ibcon#about to read 4, iclass 35, count 0 2006.257.14:20:37.63#ibcon#read 4, iclass 35, count 0 2006.257.14:20:37.63#ibcon#about to read 5, iclass 35, count 0 2006.257.14:20:37.63#ibcon#read 5, iclass 35, count 0 2006.257.14:20:37.63#ibcon#about to read 6, iclass 35, count 0 2006.257.14:20:37.63#ibcon#read 6, iclass 35, count 0 2006.257.14:20:37.63#ibcon#end of sib2, iclass 35, count 0 2006.257.14:20:37.63#ibcon#*mode == 0, iclass 35, count 0 2006.257.14:20:37.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.14:20:37.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:20:37.63#ibcon#*before write, iclass 35, count 0 2006.257.14:20:37.63#ibcon#enter sib2, iclass 35, count 0 2006.257.14:20:37.63#ibcon#flushed, iclass 35, count 0 2006.257.14:20:37.63#ibcon#about to write, iclass 35, count 0 2006.257.14:20:37.63#ibcon#wrote, iclass 35, count 0 2006.257.14:20:37.63#ibcon#about to read 3, iclass 35, count 0 2006.257.14:20:37.67#ibcon#read 3, iclass 35, count 0 2006.257.14:20:37.67#ibcon#about to read 4, iclass 35, count 0 2006.257.14:20:37.67#ibcon#read 4, iclass 35, count 0 2006.257.14:20:37.67#ibcon#about to read 5, iclass 35, count 0 2006.257.14:20:37.67#ibcon#read 5, iclass 35, count 0 2006.257.14:20:37.67#ibcon#about to read 6, iclass 35, count 0 2006.257.14:20:37.67#ibcon#read 6, iclass 35, count 0 2006.257.14:20:37.67#ibcon#end of sib2, iclass 35, count 0 2006.257.14:20:37.67#ibcon#*after write, iclass 35, count 0 2006.257.14:20:37.67#ibcon#*before return 0, iclass 35, count 0 2006.257.14:20:37.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:37.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.14:20:37.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.14:20:37.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.14:20:37.67$vck44/vb=3,4 2006.257.14:20:37.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.14:20:37.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.14:20:37.67#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:37.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:37.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:37.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:37.67#ibcon#enter wrdev, iclass 37, count 2 2006.257.14:20:37.67#ibcon#first serial, iclass 37, count 2 2006.257.14:20:37.67#ibcon#enter sib2, iclass 37, count 2 2006.257.14:20:37.67#ibcon#flushed, iclass 37, count 2 2006.257.14:20:37.67#ibcon#about to write, iclass 37, count 2 2006.257.14:20:37.67#ibcon#wrote, iclass 37, count 2 2006.257.14:20:37.67#ibcon#about to read 3, iclass 37, count 2 2006.257.14:20:37.69#ibcon#read 3, iclass 37, count 2 2006.257.14:20:37.69#ibcon#about to read 4, iclass 37, count 2 2006.257.14:20:37.69#ibcon#read 4, iclass 37, count 2 2006.257.14:20:37.69#ibcon#about to read 5, iclass 37, count 2 2006.257.14:20:37.69#ibcon#read 5, iclass 37, count 2 2006.257.14:20:37.69#ibcon#about to read 6, iclass 37, count 2 2006.257.14:20:37.69#ibcon#read 6, iclass 37, count 2 2006.257.14:20:37.69#ibcon#end of sib2, iclass 37, count 2 2006.257.14:20:37.69#ibcon#*mode == 0, iclass 37, count 2 2006.257.14:20:37.69#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.14:20:37.69#ibcon#[27=AT03-04\r\n] 2006.257.14:20:37.69#ibcon#*before write, iclass 37, count 2 2006.257.14:20:37.69#ibcon#enter sib2, iclass 37, count 2 2006.257.14:20:37.69#ibcon#flushed, iclass 37, count 2 2006.257.14:20:37.69#ibcon#about to write, iclass 37, count 2 2006.257.14:20:37.69#ibcon#wrote, iclass 37, count 2 2006.257.14:20:37.69#ibcon#about to read 3, iclass 37, count 2 2006.257.14:20:37.72#ibcon#read 3, iclass 37, count 2 2006.257.14:20:37.72#ibcon#about to read 4, iclass 37, count 2 2006.257.14:20:37.72#ibcon#read 4, iclass 37, count 2 2006.257.14:20:37.72#ibcon#about to read 5, iclass 37, count 2 2006.257.14:20:37.72#ibcon#read 5, iclass 37, count 2 2006.257.14:20:37.72#ibcon#about to read 6, iclass 37, count 2 2006.257.14:20:37.72#ibcon#read 6, iclass 37, count 2 2006.257.14:20:37.72#ibcon#end of sib2, iclass 37, count 2 2006.257.14:20:37.72#ibcon#*after write, iclass 37, count 2 2006.257.14:20:37.72#ibcon#*before return 0, iclass 37, count 2 2006.257.14:20:37.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:37.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.14:20:37.72#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.14:20:37.72#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:37.72#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:37.84#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:37.84#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:37.84#ibcon#enter wrdev, iclass 37, count 0 2006.257.14:20:37.84#ibcon#first serial, iclass 37, count 0 2006.257.14:20:37.84#ibcon#enter sib2, iclass 37, count 0 2006.257.14:20:37.84#ibcon#flushed, iclass 37, count 0 2006.257.14:20:37.84#ibcon#about to write, iclass 37, count 0 2006.257.14:20:37.84#ibcon#wrote, iclass 37, count 0 2006.257.14:20:37.84#ibcon#about to read 3, iclass 37, count 0 2006.257.14:20:37.86#ibcon#read 3, iclass 37, count 0 2006.257.14:20:37.86#ibcon#about to read 4, iclass 37, count 0 2006.257.14:20:37.86#ibcon#read 4, iclass 37, count 0 2006.257.14:20:37.86#ibcon#about to read 5, iclass 37, count 0 2006.257.14:20:37.86#ibcon#read 5, iclass 37, count 0 2006.257.14:20:37.86#ibcon#about to read 6, iclass 37, count 0 2006.257.14:20:37.86#ibcon#read 6, iclass 37, count 0 2006.257.14:20:37.86#ibcon#end of sib2, iclass 37, count 0 2006.257.14:20:37.86#ibcon#*mode == 0, iclass 37, count 0 2006.257.14:20:37.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.14:20:37.86#ibcon#[27=USB\r\n] 2006.257.14:20:37.86#ibcon#*before write, iclass 37, count 0 2006.257.14:20:37.86#ibcon#enter sib2, iclass 37, count 0 2006.257.14:20:37.86#ibcon#flushed, iclass 37, count 0 2006.257.14:20:37.86#ibcon#about to write, iclass 37, count 0 2006.257.14:20:37.86#ibcon#wrote, iclass 37, count 0 2006.257.14:20:37.86#ibcon#about to read 3, iclass 37, count 0 2006.257.14:20:37.89#ibcon#read 3, iclass 37, count 0 2006.257.14:20:37.89#ibcon#about to read 4, iclass 37, count 0 2006.257.14:20:37.89#ibcon#read 4, iclass 37, count 0 2006.257.14:20:37.89#ibcon#about to read 5, iclass 37, count 0 2006.257.14:20:37.89#ibcon#read 5, iclass 37, count 0 2006.257.14:20:37.89#ibcon#about to read 6, iclass 37, count 0 2006.257.14:20:37.89#ibcon#read 6, iclass 37, count 0 2006.257.14:20:37.89#ibcon#end of sib2, iclass 37, count 0 2006.257.14:20:37.89#ibcon#*after write, iclass 37, count 0 2006.257.14:20:37.89#ibcon#*before return 0, iclass 37, count 0 2006.257.14:20:37.89#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:37.89#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.14:20:37.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.14:20:37.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.14:20:37.89$vck44/vblo=4,679.99 2006.257.14:20:37.89#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.14:20:37.89#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.14:20:37.89#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:37.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:37.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:37.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:37.89#ibcon#enter wrdev, iclass 39, count 0 2006.257.14:20:37.89#ibcon#first serial, iclass 39, count 0 2006.257.14:20:37.89#ibcon#enter sib2, iclass 39, count 0 2006.257.14:20:37.89#ibcon#flushed, iclass 39, count 0 2006.257.14:20:37.89#ibcon#about to write, iclass 39, count 0 2006.257.14:20:37.89#ibcon#wrote, iclass 39, count 0 2006.257.14:20:37.89#ibcon#about to read 3, iclass 39, count 0 2006.257.14:20:37.91#ibcon#read 3, iclass 39, count 0 2006.257.14:20:37.91#ibcon#about to read 4, iclass 39, count 0 2006.257.14:20:37.91#ibcon#read 4, iclass 39, count 0 2006.257.14:20:37.91#ibcon#about to read 5, iclass 39, count 0 2006.257.14:20:37.91#ibcon#read 5, iclass 39, count 0 2006.257.14:20:37.91#ibcon#about to read 6, iclass 39, count 0 2006.257.14:20:37.91#ibcon#read 6, iclass 39, count 0 2006.257.14:20:37.91#ibcon#end of sib2, iclass 39, count 0 2006.257.14:20:37.91#ibcon#*mode == 0, iclass 39, count 0 2006.257.14:20:37.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.14:20:37.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:20:37.91#ibcon#*before write, iclass 39, count 0 2006.257.14:20:37.91#ibcon#enter sib2, iclass 39, count 0 2006.257.14:20:37.91#ibcon#flushed, iclass 39, count 0 2006.257.14:20:37.91#ibcon#about to write, iclass 39, count 0 2006.257.14:20:37.91#ibcon#wrote, iclass 39, count 0 2006.257.14:20:37.91#ibcon#about to read 3, iclass 39, count 0 2006.257.14:20:37.95#ibcon#read 3, iclass 39, count 0 2006.257.14:20:37.95#ibcon#about to read 4, iclass 39, count 0 2006.257.14:20:37.95#ibcon#read 4, iclass 39, count 0 2006.257.14:20:37.95#ibcon#about to read 5, iclass 39, count 0 2006.257.14:20:37.95#ibcon#read 5, iclass 39, count 0 2006.257.14:20:37.95#ibcon#about to read 6, iclass 39, count 0 2006.257.14:20:37.95#ibcon#read 6, iclass 39, count 0 2006.257.14:20:37.95#ibcon#end of sib2, iclass 39, count 0 2006.257.14:20:37.95#ibcon#*after write, iclass 39, count 0 2006.257.14:20:37.95#ibcon#*before return 0, iclass 39, count 0 2006.257.14:20:37.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:37.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.14:20:37.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.14:20:37.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.14:20:37.95$vck44/vb=4,5 2006.257.14:20:37.95#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.14:20:37.95#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.14:20:37.95#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:37.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:38.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:38.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:38.01#ibcon#enter wrdev, iclass 3, count 2 2006.257.14:20:38.01#ibcon#first serial, iclass 3, count 2 2006.257.14:20:38.01#ibcon#enter sib2, iclass 3, count 2 2006.257.14:20:38.01#ibcon#flushed, iclass 3, count 2 2006.257.14:20:38.01#ibcon#about to write, iclass 3, count 2 2006.257.14:20:38.01#ibcon#wrote, iclass 3, count 2 2006.257.14:20:38.01#ibcon#about to read 3, iclass 3, count 2 2006.257.14:20:38.03#ibcon#read 3, iclass 3, count 2 2006.257.14:20:38.03#ibcon#about to read 4, iclass 3, count 2 2006.257.14:20:38.03#ibcon#read 4, iclass 3, count 2 2006.257.14:20:38.03#ibcon#about to read 5, iclass 3, count 2 2006.257.14:20:38.03#ibcon#read 5, iclass 3, count 2 2006.257.14:20:38.03#ibcon#about to read 6, iclass 3, count 2 2006.257.14:20:38.03#ibcon#read 6, iclass 3, count 2 2006.257.14:20:38.03#ibcon#end of sib2, iclass 3, count 2 2006.257.14:20:38.03#ibcon#*mode == 0, iclass 3, count 2 2006.257.14:20:38.03#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.14:20:38.03#ibcon#[27=AT04-05\r\n] 2006.257.14:20:38.03#ibcon#*before write, iclass 3, count 2 2006.257.14:20:38.03#ibcon#enter sib2, iclass 3, count 2 2006.257.14:20:38.03#ibcon#flushed, iclass 3, count 2 2006.257.14:20:38.03#ibcon#about to write, iclass 3, count 2 2006.257.14:20:38.03#ibcon#wrote, iclass 3, count 2 2006.257.14:20:38.03#ibcon#about to read 3, iclass 3, count 2 2006.257.14:20:38.06#ibcon#read 3, iclass 3, count 2 2006.257.14:20:38.06#ibcon#about to read 4, iclass 3, count 2 2006.257.14:20:38.06#ibcon#read 4, iclass 3, count 2 2006.257.14:20:38.06#ibcon#about to read 5, iclass 3, count 2 2006.257.14:20:38.06#ibcon#read 5, iclass 3, count 2 2006.257.14:20:38.06#ibcon#about to read 6, iclass 3, count 2 2006.257.14:20:38.06#ibcon#read 6, iclass 3, count 2 2006.257.14:20:38.06#ibcon#end of sib2, iclass 3, count 2 2006.257.14:20:38.06#ibcon#*after write, iclass 3, count 2 2006.257.14:20:38.06#ibcon#*before return 0, iclass 3, count 2 2006.257.14:20:38.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:38.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.14:20:38.06#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.14:20:38.06#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:38.06#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:38.18#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:38.18#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:38.18#ibcon#enter wrdev, iclass 3, count 0 2006.257.14:20:38.18#ibcon#first serial, iclass 3, count 0 2006.257.14:20:38.18#ibcon#enter sib2, iclass 3, count 0 2006.257.14:20:38.18#ibcon#flushed, iclass 3, count 0 2006.257.14:20:38.18#ibcon#about to write, iclass 3, count 0 2006.257.14:20:38.18#ibcon#wrote, iclass 3, count 0 2006.257.14:20:38.18#ibcon#about to read 3, iclass 3, count 0 2006.257.14:20:38.20#ibcon#read 3, iclass 3, count 0 2006.257.14:20:38.20#ibcon#about to read 4, iclass 3, count 0 2006.257.14:20:38.20#ibcon#read 4, iclass 3, count 0 2006.257.14:20:38.20#ibcon#about to read 5, iclass 3, count 0 2006.257.14:20:38.20#ibcon#read 5, iclass 3, count 0 2006.257.14:20:38.20#ibcon#about to read 6, iclass 3, count 0 2006.257.14:20:38.20#ibcon#read 6, iclass 3, count 0 2006.257.14:20:38.20#ibcon#end of sib2, iclass 3, count 0 2006.257.14:20:38.20#ibcon#*mode == 0, iclass 3, count 0 2006.257.14:20:38.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.14:20:38.20#ibcon#[27=USB\r\n] 2006.257.14:20:38.20#ibcon#*before write, iclass 3, count 0 2006.257.14:20:38.20#ibcon#enter sib2, iclass 3, count 0 2006.257.14:20:38.20#ibcon#flushed, iclass 3, count 0 2006.257.14:20:38.20#ibcon#about to write, iclass 3, count 0 2006.257.14:20:38.20#ibcon#wrote, iclass 3, count 0 2006.257.14:20:38.20#ibcon#about to read 3, iclass 3, count 0 2006.257.14:20:38.23#ibcon#read 3, iclass 3, count 0 2006.257.14:20:38.23#ibcon#about to read 4, iclass 3, count 0 2006.257.14:20:38.23#ibcon#read 4, iclass 3, count 0 2006.257.14:20:38.23#ibcon#about to read 5, iclass 3, count 0 2006.257.14:20:38.23#ibcon#read 5, iclass 3, count 0 2006.257.14:20:38.23#ibcon#about to read 6, iclass 3, count 0 2006.257.14:20:38.23#ibcon#read 6, iclass 3, count 0 2006.257.14:20:38.23#ibcon#end of sib2, iclass 3, count 0 2006.257.14:20:38.23#ibcon#*after write, iclass 3, count 0 2006.257.14:20:38.23#ibcon#*before return 0, iclass 3, count 0 2006.257.14:20:38.23#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:38.23#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.14:20:38.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.14:20:38.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.14:20:38.23$vck44/vblo=5,709.99 2006.257.14:20:38.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.14:20:38.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.14:20:38.23#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:38.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:38.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:38.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:38.23#ibcon#enter wrdev, iclass 5, count 0 2006.257.14:20:38.23#ibcon#first serial, iclass 5, count 0 2006.257.14:20:38.23#ibcon#enter sib2, iclass 5, count 0 2006.257.14:20:38.23#ibcon#flushed, iclass 5, count 0 2006.257.14:20:38.23#ibcon#about to write, iclass 5, count 0 2006.257.14:20:38.23#ibcon#wrote, iclass 5, count 0 2006.257.14:20:38.23#ibcon#about to read 3, iclass 5, count 0 2006.257.14:20:38.25#ibcon#read 3, iclass 5, count 0 2006.257.14:20:38.25#ibcon#about to read 4, iclass 5, count 0 2006.257.14:20:38.25#ibcon#read 4, iclass 5, count 0 2006.257.14:20:38.25#ibcon#about to read 5, iclass 5, count 0 2006.257.14:20:38.25#ibcon#read 5, iclass 5, count 0 2006.257.14:20:38.25#ibcon#about to read 6, iclass 5, count 0 2006.257.14:20:38.25#ibcon#read 6, iclass 5, count 0 2006.257.14:20:38.25#ibcon#end of sib2, iclass 5, count 0 2006.257.14:20:38.25#ibcon#*mode == 0, iclass 5, count 0 2006.257.14:20:38.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.14:20:38.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:20:38.25#ibcon#*before write, iclass 5, count 0 2006.257.14:20:38.25#ibcon#enter sib2, iclass 5, count 0 2006.257.14:20:38.25#ibcon#flushed, iclass 5, count 0 2006.257.14:20:38.25#ibcon#about to write, iclass 5, count 0 2006.257.14:20:38.25#ibcon#wrote, iclass 5, count 0 2006.257.14:20:38.25#ibcon#about to read 3, iclass 5, count 0 2006.257.14:20:38.29#ibcon#read 3, iclass 5, count 0 2006.257.14:20:38.29#ibcon#about to read 4, iclass 5, count 0 2006.257.14:20:38.29#ibcon#read 4, iclass 5, count 0 2006.257.14:20:38.29#ibcon#about to read 5, iclass 5, count 0 2006.257.14:20:38.29#ibcon#read 5, iclass 5, count 0 2006.257.14:20:38.29#ibcon#about to read 6, iclass 5, count 0 2006.257.14:20:38.29#ibcon#read 6, iclass 5, count 0 2006.257.14:20:38.29#ibcon#end of sib2, iclass 5, count 0 2006.257.14:20:38.29#ibcon#*after write, iclass 5, count 0 2006.257.14:20:38.29#ibcon#*before return 0, iclass 5, count 0 2006.257.14:20:38.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:38.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.14:20:38.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.14:20:38.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.14:20:38.29$vck44/vb=5,4 2006.257.14:20:38.29#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.14:20:38.29#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.14:20:38.29#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:38.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:38.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:38.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:38.35#ibcon#enter wrdev, iclass 7, count 2 2006.257.14:20:38.35#ibcon#first serial, iclass 7, count 2 2006.257.14:20:38.35#ibcon#enter sib2, iclass 7, count 2 2006.257.14:20:38.35#ibcon#flushed, iclass 7, count 2 2006.257.14:20:38.35#ibcon#about to write, iclass 7, count 2 2006.257.14:20:38.35#ibcon#wrote, iclass 7, count 2 2006.257.14:20:38.35#ibcon#about to read 3, iclass 7, count 2 2006.257.14:20:38.37#ibcon#read 3, iclass 7, count 2 2006.257.14:20:38.37#ibcon#about to read 4, iclass 7, count 2 2006.257.14:20:38.37#ibcon#read 4, iclass 7, count 2 2006.257.14:20:38.37#ibcon#about to read 5, iclass 7, count 2 2006.257.14:20:38.37#ibcon#read 5, iclass 7, count 2 2006.257.14:20:38.37#ibcon#about to read 6, iclass 7, count 2 2006.257.14:20:38.37#ibcon#read 6, iclass 7, count 2 2006.257.14:20:38.37#ibcon#end of sib2, iclass 7, count 2 2006.257.14:20:38.37#ibcon#*mode == 0, iclass 7, count 2 2006.257.14:20:38.37#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.14:20:38.37#ibcon#[27=AT05-04\r\n] 2006.257.14:20:38.37#ibcon#*before write, iclass 7, count 2 2006.257.14:20:38.37#ibcon#enter sib2, iclass 7, count 2 2006.257.14:20:38.37#ibcon#flushed, iclass 7, count 2 2006.257.14:20:38.37#ibcon#about to write, iclass 7, count 2 2006.257.14:20:38.37#ibcon#wrote, iclass 7, count 2 2006.257.14:20:38.37#ibcon#about to read 3, iclass 7, count 2 2006.257.14:20:38.40#ibcon#read 3, iclass 7, count 2 2006.257.14:20:38.40#ibcon#about to read 4, iclass 7, count 2 2006.257.14:20:38.40#ibcon#read 4, iclass 7, count 2 2006.257.14:20:38.40#ibcon#about to read 5, iclass 7, count 2 2006.257.14:20:38.40#ibcon#read 5, iclass 7, count 2 2006.257.14:20:38.40#ibcon#about to read 6, iclass 7, count 2 2006.257.14:20:38.40#ibcon#read 6, iclass 7, count 2 2006.257.14:20:38.40#ibcon#end of sib2, iclass 7, count 2 2006.257.14:20:38.40#ibcon#*after write, iclass 7, count 2 2006.257.14:20:38.40#ibcon#*before return 0, iclass 7, count 2 2006.257.14:20:38.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:38.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.14:20:38.40#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.14:20:38.40#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:38.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:38.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:38.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:38.52#ibcon#enter wrdev, iclass 7, count 0 2006.257.14:20:38.52#ibcon#first serial, iclass 7, count 0 2006.257.14:20:38.52#ibcon#enter sib2, iclass 7, count 0 2006.257.14:20:38.52#ibcon#flushed, iclass 7, count 0 2006.257.14:20:38.52#ibcon#about to write, iclass 7, count 0 2006.257.14:20:38.52#ibcon#wrote, iclass 7, count 0 2006.257.14:20:38.52#ibcon#about to read 3, iclass 7, count 0 2006.257.14:20:38.54#ibcon#read 3, iclass 7, count 0 2006.257.14:20:38.54#ibcon#about to read 4, iclass 7, count 0 2006.257.14:20:38.54#ibcon#read 4, iclass 7, count 0 2006.257.14:20:38.54#ibcon#about to read 5, iclass 7, count 0 2006.257.14:20:38.54#ibcon#read 5, iclass 7, count 0 2006.257.14:20:38.54#ibcon#about to read 6, iclass 7, count 0 2006.257.14:20:38.54#ibcon#read 6, iclass 7, count 0 2006.257.14:20:38.54#ibcon#end of sib2, iclass 7, count 0 2006.257.14:20:38.54#ibcon#*mode == 0, iclass 7, count 0 2006.257.14:20:38.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.14:20:38.54#ibcon#[27=USB\r\n] 2006.257.14:20:38.54#ibcon#*before write, iclass 7, count 0 2006.257.14:20:38.54#ibcon#enter sib2, iclass 7, count 0 2006.257.14:20:38.54#ibcon#flushed, iclass 7, count 0 2006.257.14:20:38.54#ibcon#about to write, iclass 7, count 0 2006.257.14:20:38.54#ibcon#wrote, iclass 7, count 0 2006.257.14:20:38.54#ibcon#about to read 3, iclass 7, count 0 2006.257.14:20:38.57#ibcon#read 3, iclass 7, count 0 2006.257.14:20:38.57#ibcon#about to read 4, iclass 7, count 0 2006.257.14:20:38.57#ibcon#read 4, iclass 7, count 0 2006.257.14:20:38.57#ibcon#about to read 5, iclass 7, count 0 2006.257.14:20:38.57#ibcon#read 5, iclass 7, count 0 2006.257.14:20:38.57#ibcon#about to read 6, iclass 7, count 0 2006.257.14:20:38.57#ibcon#read 6, iclass 7, count 0 2006.257.14:20:38.57#ibcon#end of sib2, iclass 7, count 0 2006.257.14:20:38.57#ibcon#*after write, iclass 7, count 0 2006.257.14:20:38.57#ibcon#*before return 0, iclass 7, count 0 2006.257.14:20:38.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:38.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.14:20:38.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.14:20:38.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.14:20:38.57$vck44/vblo=6,719.99 2006.257.14:20:38.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.14:20:38.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.14:20:38.57#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:38.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:38.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:38.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:38.57#ibcon#enter wrdev, iclass 11, count 0 2006.257.14:20:38.57#ibcon#first serial, iclass 11, count 0 2006.257.14:20:38.57#ibcon#enter sib2, iclass 11, count 0 2006.257.14:20:38.57#ibcon#flushed, iclass 11, count 0 2006.257.14:20:38.57#ibcon#about to write, iclass 11, count 0 2006.257.14:20:38.57#ibcon#wrote, iclass 11, count 0 2006.257.14:20:38.57#ibcon#about to read 3, iclass 11, count 0 2006.257.14:20:38.59#ibcon#read 3, iclass 11, count 0 2006.257.14:20:38.59#ibcon#about to read 4, iclass 11, count 0 2006.257.14:20:38.59#ibcon#read 4, iclass 11, count 0 2006.257.14:20:38.59#ibcon#about to read 5, iclass 11, count 0 2006.257.14:20:38.59#ibcon#read 5, iclass 11, count 0 2006.257.14:20:38.59#ibcon#about to read 6, iclass 11, count 0 2006.257.14:20:38.59#ibcon#read 6, iclass 11, count 0 2006.257.14:20:38.59#ibcon#end of sib2, iclass 11, count 0 2006.257.14:20:38.59#ibcon#*mode == 0, iclass 11, count 0 2006.257.14:20:38.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.14:20:38.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:20:38.59#ibcon#*before write, iclass 11, count 0 2006.257.14:20:38.59#ibcon#enter sib2, iclass 11, count 0 2006.257.14:20:38.59#ibcon#flushed, iclass 11, count 0 2006.257.14:20:38.59#ibcon#about to write, iclass 11, count 0 2006.257.14:20:38.59#ibcon#wrote, iclass 11, count 0 2006.257.14:20:38.59#ibcon#about to read 3, iclass 11, count 0 2006.257.14:20:38.63#ibcon#read 3, iclass 11, count 0 2006.257.14:20:38.63#ibcon#about to read 4, iclass 11, count 0 2006.257.14:20:38.63#ibcon#read 4, iclass 11, count 0 2006.257.14:20:38.63#ibcon#about to read 5, iclass 11, count 0 2006.257.14:20:38.63#ibcon#read 5, iclass 11, count 0 2006.257.14:20:38.63#ibcon#about to read 6, iclass 11, count 0 2006.257.14:20:38.63#ibcon#read 6, iclass 11, count 0 2006.257.14:20:38.63#ibcon#end of sib2, iclass 11, count 0 2006.257.14:20:38.63#ibcon#*after write, iclass 11, count 0 2006.257.14:20:38.63#ibcon#*before return 0, iclass 11, count 0 2006.257.14:20:38.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:38.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.14:20:38.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.14:20:38.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.14:20:38.63$vck44/vb=6,4 2006.257.14:20:38.63#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.14:20:38.63#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.14:20:38.63#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:38.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:38.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:38.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:38.69#ibcon#enter wrdev, iclass 13, count 2 2006.257.14:20:38.69#ibcon#first serial, iclass 13, count 2 2006.257.14:20:38.69#ibcon#enter sib2, iclass 13, count 2 2006.257.14:20:38.69#ibcon#flushed, iclass 13, count 2 2006.257.14:20:38.69#ibcon#about to write, iclass 13, count 2 2006.257.14:20:38.69#ibcon#wrote, iclass 13, count 2 2006.257.14:20:38.69#ibcon#about to read 3, iclass 13, count 2 2006.257.14:20:38.71#ibcon#read 3, iclass 13, count 2 2006.257.14:20:38.71#ibcon#about to read 4, iclass 13, count 2 2006.257.14:20:38.71#ibcon#read 4, iclass 13, count 2 2006.257.14:20:38.71#ibcon#about to read 5, iclass 13, count 2 2006.257.14:20:38.71#ibcon#read 5, iclass 13, count 2 2006.257.14:20:38.71#ibcon#about to read 6, iclass 13, count 2 2006.257.14:20:38.71#ibcon#read 6, iclass 13, count 2 2006.257.14:20:38.71#ibcon#end of sib2, iclass 13, count 2 2006.257.14:20:38.71#ibcon#*mode == 0, iclass 13, count 2 2006.257.14:20:38.71#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.14:20:38.71#ibcon#[27=AT06-04\r\n] 2006.257.14:20:38.71#ibcon#*before write, iclass 13, count 2 2006.257.14:20:38.71#ibcon#enter sib2, iclass 13, count 2 2006.257.14:20:38.71#ibcon#flushed, iclass 13, count 2 2006.257.14:20:38.71#ibcon#about to write, iclass 13, count 2 2006.257.14:20:38.71#ibcon#wrote, iclass 13, count 2 2006.257.14:20:38.71#ibcon#about to read 3, iclass 13, count 2 2006.257.14:20:38.74#ibcon#read 3, iclass 13, count 2 2006.257.14:20:38.74#ibcon#about to read 4, iclass 13, count 2 2006.257.14:20:38.74#ibcon#read 4, iclass 13, count 2 2006.257.14:20:38.74#ibcon#about to read 5, iclass 13, count 2 2006.257.14:20:38.74#ibcon#read 5, iclass 13, count 2 2006.257.14:20:38.74#ibcon#about to read 6, iclass 13, count 2 2006.257.14:20:38.74#ibcon#read 6, iclass 13, count 2 2006.257.14:20:38.74#ibcon#end of sib2, iclass 13, count 2 2006.257.14:20:38.74#ibcon#*after write, iclass 13, count 2 2006.257.14:20:38.74#ibcon#*before return 0, iclass 13, count 2 2006.257.14:20:38.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:39.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.14:20:39.61#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.14:20:39.61#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:39.61#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:39.73#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:39.73#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:39.73#ibcon#enter wrdev, iclass 13, count 0 2006.257.14:20:39.73#ibcon#first serial, iclass 13, count 0 2006.257.14:20:39.73#ibcon#enter sib2, iclass 13, count 0 2006.257.14:20:39.73#ibcon#flushed, iclass 13, count 0 2006.257.14:20:39.73#ibcon#about to write, iclass 13, count 0 2006.257.14:20:39.73#ibcon#wrote, iclass 13, count 0 2006.257.14:20:39.73#ibcon#about to read 3, iclass 13, count 0 2006.257.14:20:39.75#ibcon#read 3, iclass 13, count 0 2006.257.14:20:39.75#ibcon#about to read 4, iclass 13, count 0 2006.257.14:20:39.75#ibcon#read 4, iclass 13, count 0 2006.257.14:20:39.75#ibcon#about to read 5, iclass 13, count 0 2006.257.14:20:39.75#ibcon#read 5, iclass 13, count 0 2006.257.14:20:39.75#ibcon#about to read 6, iclass 13, count 0 2006.257.14:20:39.75#ibcon#read 6, iclass 13, count 0 2006.257.14:20:39.75#ibcon#end of sib2, iclass 13, count 0 2006.257.14:20:39.75#ibcon#*mode == 0, iclass 13, count 0 2006.257.14:20:39.75#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.14:20:39.75#ibcon#[27=USB\r\n] 2006.257.14:20:39.75#ibcon#*before write, iclass 13, count 0 2006.257.14:20:39.75#ibcon#enter sib2, iclass 13, count 0 2006.257.14:20:39.75#ibcon#flushed, iclass 13, count 0 2006.257.14:20:39.75#ibcon#about to write, iclass 13, count 0 2006.257.14:20:39.75#ibcon#wrote, iclass 13, count 0 2006.257.14:20:39.75#ibcon#about to read 3, iclass 13, count 0 2006.257.14:20:39.78#ibcon#read 3, iclass 13, count 0 2006.257.14:20:39.78#ibcon#about to read 4, iclass 13, count 0 2006.257.14:20:39.78#ibcon#read 4, iclass 13, count 0 2006.257.14:20:39.78#ibcon#about to read 5, iclass 13, count 0 2006.257.14:20:39.78#ibcon#read 5, iclass 13, count 0 2006.257.14:20:39.78#ibcon#about to read 6, iclass 13, count 0 2006.257.14:20:39.78#ibcon#read 6, iclass 13, count 0 2006.257.14:20:39.78#ibcon#end of sib2, iclass 13, count 0 2006.257.14:20:39.78#ibcon#*after write, iclass 13, count 0 2006.257.14:20:39.78#ibcon#*before return 0, iclass 13, count 0 2006.257.14:20:39.78#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:39.78#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.14:20:39.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.14:20:39.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.14:20:39.78$vck44/vblo=7,734.99 2006.257.14:20:39.78#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.14:20:39.78#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.14:20:39.78#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:39.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:39.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:39.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:39.78#ibcon#enter wrdev, iclass 15, count 0 2006.257.14:20:39.78#ibcon#first serial, iclass 15, count 0 2006.257.14:20:39.78#ibcon#enter sib2, iclass 15, count 0 2006.257.14:20:39.78#ibcon#flushed, iclass 15, count 0 2006.257.14:20:39.78#ibcon#about to write, iclass 15, count 0 2006.257.14:20:39.78#ibcon#wrote, iclass 15, count 0 2006.257.14:20:39.78#ibcon#about to read 3, iclass 15, count 0 2006.257.14:20:39.80#ibcon#read 3, iclass 15, count 0 2006.257.14:20:39.80#ibcon#about to read 4, iclass 15, count 0 2006.257.14:20:39.80#ibcon#read 4, iclass 15, count 0 2006.257.14:20:39.80#ibcon#about to read 5, iclass 15, count 0 2006.257.14:20:39.80#ibcon#read 5, iclass 15, count 0 2006.257.14:20:39.80#ibcon#about to read 6, iclass 15, count 0 2006.257.14:20:39.80#ibcon#read 6, iclass 15, count 0 2006.257.14:20:39.80#ibcon#end of sib2, iclass 15, count 0 2006.257.14:20:39.80#ibcon#*mode == 0, iclass 15, count 0 2006.257.14:20:39.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.14:20:39.80#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:20:39.80#ibcon#*before write, iclass 15, count 0 2006.257.14:20:39.80#ibcon#enter sib2, iclass 15, count 0 2006.257.14:20:39.80#ibcon#flushed, iclass 15, count 0 2006.257.14:20:39.80#ibcon#about to write, iclass 15, count 0 2006.257.14:20:39.80#ibcon#wrote, iclass 15, count 0 2006.257.14:20:39.80#ibcon#about to read 3, iclass 15, count 0 2006.257.14:20:39.84#ibcon#read 3, iclass 15, count 0 2006.257.14:20:39.84#ibcon#about to read 4, iclass 15, count 0 2006.257.14:20:39.84#ibcon#read 4, iclass 15, count 0 2006.257.14:20:39.84#ibcon#about to read 5, iclass 15, count 0 2006.257.14:20:39.84#ibcon#read 5, iclass 15, count 0 2006.257.14:20:39.84#ibcon#about to read 6, iclass 15, count 0 2006.257.14:20:39.84#ibcon#read 6, iclass 15, count 0 2006.257.14:20:39.84#ibcon#end of sib2, iclass 15, count 0 2006.257.14:20:39.84#ibcon#*after write, iclass 15, count 0 2006.257.14:20:39.84#ibcon#*before return 0, iclass 15, count 0 2006.257.14:20:39.84#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:39.84#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.14:20:39.84#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.14:20:39.84#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.14:20:39.84$vck44/vb=7,4 2006.257.14:20:39.84#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.14:20:39.84#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.14:20:39.84#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:39.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:39.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:39.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:39.90#ibcon#enter wrdev, iclass 17, count 2 2006.257.14:20:39.90#ibcon#first serial, iclass 17, count 2 2006.257.14:20:39.90#ibcon#enter sib2, iclass 17, count 2 2006.257.14:20:39.90#ibcon#flushed, iclass 17, count 2 2006.257.14:20:39.90#ibcon#about to write, iclass 17, count 2 2006.257.14:20:39.90#ibcon#wrote, iclass 17, count 2 2006.257.14:20:39.90#ibcon#about to read 3, iclass 17, count 2 2006.257.14:20:39.92#ibcon#read 3, iclass 17, count 2 2006.257.14:20:39.92#ibcon#about to read 4, iclass 17, count 2 2006.257.14:20:39.92#ibcon#read 4, iclass 17, count 2 2006.257.14:20:39.92#ibcon#about to read 5, iclass 17, count 2 2006.257.14:20:39.92#ibcon#read 5, iclass 17, count 2 2006.257.14:20:39.92#ibcon#about to read 6, iclass 17, count 2 2006.257.14:20:39.92#ibcon#read 6, iclass 17, count 2 2006.257.14:20:39.92#ibcon#end of sib2, iclass 17, count 2 2006.257.14:20:39.92#ibcon#*mode == 0, iclass 17, count 2 2006.257.14:20:39.92#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.14:20:39.92#ibcon#[27=AT07-04\r\n] 2006.257.14:20:39.92#ibcon#*before write, iclass 17, count 2 2006.257.14:20:39.92#ibcon#enter sib2, iclass 17, count 2 2006.257.14:20:39.92#ibcon#flushed, iclass 17, count 2 2006.257.14:20:39.92#ibcon#about to write, iclass 17, count 2 2006.257.14:20:39.92#ibcon#wrote, iclass 17, count 2 2006.257.14:20:39.92#ibcon#about to read 3, iclass 17, count 2 2006.257.14:20:39.95#ibcon#read 3, iclass 17, count 2 2006.257.14:20:39.95#ibcon#about to read 4, iclass 17, count 2 2006.257.14:20:39.95#ibcon#read 4, iclass 17, count 2 2006.257.14:20:39.95#ibcon#about to read 5, iclass 17, count 2 2006.257.14:20:39.95#ibcon#read 5, iclass 17, count 2 2006.257.14:20:39.95#ibcon#about to read 6, iclass 17, count 2 2006.257.14:20:39.95#ibcon#read 6, iclass 17, count 2 2006.257.14:20:39.95#ibcon#end of sib2, iclass 17, count 2 2006.257.14:20:39.95#ibcon#*after write, iclass 17, count 2 2006.257.14:20:39.95#ibcon#*before return 0, iclass 17, count 2 2006.257.14:20:39.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:39.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.14:20:39.95#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.14:20:39.95#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:39.95#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:40.07#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:40.07#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:40.07#ibcon#enter wrdev, iclass 17, count 0 2006.257.14:20:40.07#ibcon#first serial, iclass 17, count 0 2006.257.14:20:40.07#ibcon#enter sib2, iclass 17, count 0 2006.257.14:20:40.07#ibcon#flushed, iclass 17, count 0 2006.257.14:20:40.07#ibcon#about to write, iclass 17, count 0 2006.257.14:20:40.07#ibcon#wrote, iclass 17, count 0 2006.257.14:20:40.07#ibcon#about to read 3, iclass 17, count 0 2006.257.14:20:40.09#ibcon#read 3, iclass 17, count 0 2006.257.14:20:40.09#ibcon#about to read 4, iclass 17, count 0 2006.257.14:20:40.09#ibcon#read 4, iclass 17, count 0 2006.257.14:20:40.09#ibcon#about to read 5, iclass 17, count 0 2006.257.14:20:40.09#ibcon#read 5, iclass 17, count 0 2006.257.14:20:40.09#ibcon#about to read 6, iclass 17, count 0 2006.257.14:20:40.09#ibcon#read 6, iclass 17, count 0 2006.257.14:20:40.09#ibcon#end of sib2, iclass 17, count 0 2006.257.14:20:40.09#ibcon#*mode == 0, iclass 17, count 0 2006.257.14:20:40.09#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.14:20:40.09#ibcon#[27=USB\r\n] 2006.257.14:20:40.09#ibcon#*before write, iclass 17, count 0 2006.257.14:20:40.09#ibcon#enter sib2, iclass 17, count 0 2006.257.14:20:40.09#ibcon#flushed, iclass 17, count 0 2006.257.14:20:40.09#ibcon#about to write, iclass 17, count 0 2006.257.14:20:40.09#ibcon#wrote, iclass 17, count 0 2006.257.14:20:40.09#ibcon#about to read 3, iclass 17, count 0 2006.257.14:20:40.12#ibcon#read 3, iclass 17, count 0 2006.257.14:20:40.12#ibcon#about to read 4, iclass 17, count 0 2006.257.14:20:40.12#ibcon#read 4, iclass 17, count 0 2006.257.14:20:40.12#ibcon#about to read 5, iclass 17, count 0 2006.257.14:20:40.12#ibcon#read 5, iclass 17, count 0 2006.257.14:20:40.12#ibcon#about to read 6, iclass 17, count 0 2006.257.14:20:40.12#ibcon#read 6, iclass 17, count 0 2006.257.14:20:40.12#ibcon#end of sib2, iclass 17, count 0 2006.257.14:20:40.12#ibcon#*after write, iclass 17, count 0 2006.257.14:20:40.12#ibcon#*before return 0, iclass 17, count 0 2006.257.14:20:40.12#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:40.12#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.14:20:40.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.14:20:40.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.14:20:40.12$vck44/vblo=8,744.99 2006.257.14:20:40.12#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.14:20:40.12#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.14:20:40.12#ibcon#ireg 17 cls_cnt 0 2006.257.14:20:40.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:40.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:40.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:40.12#ibcon#enter wrdev, iclass 19, count 0 2006.257.14:20:40.12#ibcon#first serial, iclass 19, count 0 2006.257.14:20:40.12#ibcon#enter sib2, iclass 19, count 0 2006.257.14:20:40.12#ibcon#flushed, iclass 19, count 0 2006.257.14:20:40.12#ibcon#about to write, iclass 19, count 0 2006.257.14:20:40.12#ibcon#wrote, iclass 19, count 0 2006.257.14:20:40.12#ibcon#about to read 3, iclass 19, count 0 2006.257.14:20:40.14#ibcon#read 3, iclass 19, count 0 2006.257.14:20:40.14#ibcon#about to read 4, iclass 19, count 0 2006.257.14:20:40.14#ibcon#read 4, iclass 19, count 0 2006.257.14:20:40.14#ibcon#about to read 5, iclass 19, count 0 2006.257.14:20:40.14#ibcon#read 5, iclass 19, count 0 2006.257.14:20:40.14#ibcon#about to read 6, iclass 19, count 0 2006.257.14:20:40.14#ibcon#read 6, iclass 19, count 0 2006.257.14:20:40.14#ibcon#end of sib2, iclass 19, count 0 2006.257.14:20:40.14#ibcon#*mode == 0, iclass 19, count 0 2006.257.14:20:40.14#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.14:20:40.14#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:20:40.14#ibcon#*before write, iclass 19, count 0 2006.257.14:20:40.14#ibcon#enter sib2, iclass 19, count 0 2006.257.14:20:40.14#ibcon#flushed, iclass 19, count 0 2006.257.14:20:40.14#ibcon#about to write, iclass 19, count 0 2006.257.14:20:40.14#ibcon#wrote, iclass 19, count 0 2006.257.14:20:40.14#ibcon#about to read 3, iclass 19, count 0 2006.257.14:20:40.18#ibcon#read 3, iclass 19, count 0 2006.257.14:20:40.18#ibcon#about to read 4, iclass 19, count 0 2006.257.14:20:40.18#ibcon#read 4, iclass 19, count 0 2006.257.14:20:40.18#ibcon#about to read 5, iclass 19, count 0 2006.257.14:20:40.18#ibcon#read 5, iclass 19, count 0 2006.257.14:20:40.18#ibcon#about to read 6, iclass 19, count 0 2006.257.14:20:40.18#ibcon#read 6, iclass 19, count 0 2006.257.14:20:40.18#ibcon#end of sib2, iclass 19, count 0 2006.257.14:20:40.18#ibcon#*after write, iclass 19, count 0 2006.257.14:20:40.18#ibcon#*before return 0, iclass 19, count 0 2006.257.14:20:40.18#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:40.18#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.14:20:40.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.14:20:40.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.14:20:40.18$vck44/vb=8,4 2006.257.14:20:40.18#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.14:20:40.18#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.14:20:40.18#ibcon#ireg 11 cls_cnt 2 2006.257.14:20:40.18#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:40.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:40.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:40.24#ibcon#enter wrdev, iclass 21, count 2 2006.257.14:20:40.24#ibcon#first serial, iclass 21, count 2 2006.257.14:20:40.24#ibcon#enter sib2, iclass 21, count 2 2006.257.14:20:40.24#ibcon#flushed, iclass 21, count 2 2006.257.14:20:40.24#ibcon#about to write, iclass 21, count 2 2006.257.14:20:40.24#ibcon#wrote, iclass 21, count 2 2006.257.14:20:40.24#ibcon#about to read 3, iclass 21, count 2 2006.257.14:20:40.26#ibcon#read 3, iclass 21, count 2 2006.257.14:20:40.26#ibcon#about to read 4, iclass 21, count 2 2006.257.14:20:40.26#ibcon#read 4, iclass 21, count 2 2006.257.14:20:40.26#ibcon#about to read 5, iclass 21, count 2 2006.257.14:20:40.26#ibcon#read 5, iclass 21, count 2 2006.257.14:20:40.26#ibcon#about to read 6, iclass 21, count 2 2006.257.14:20:40.26#ibcon#read 6, iclass 21, count 2 2006.257.14:20:40.26#ibcon#end of sib2, iclass 21, count 2 2006.257.14:20:40.26#ibcon#*mode == 0, iclass 21, count 2 2006.257.14:20:40.26#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.14:20:40.26#ibcon#[27=AT08-04\r\n] 2006.257.14:20:40.26#ibcon#*before write, iclass 21, count 2 2006.257.14:20:40.26#ibcon#enter sib2, iclass 21, count 2 2006.257.14:20:40.26#ibcon#flushed, iclass 21, count 2 2006.257.14:20:40.26#ibcon#about to write, iclass 21, count 2 2006.257.14:20:40.26#ibcon#wrote, iclass 21, count 2 2006.257.14:20:40.26#ibcon#about to read 3, iclass 21, count 2 2006.257.14:20:40.29#ibcon#read 3, iclass 21, count 2 2006.257.14:20:40.29#ibcon#about to read 4, iclass 21, count 2 2006.257.14:20:40.29#ibcon#read 4, iclass 21, count 2 2006.257.14:20:40.29#ibcon#about to read 5, iclass 21, count 2 2006.257.14:20:40.29#ibcon#read 5, iclass 21, count 2 2006.257.14:20:40.29#ibcon#about to read 6, iclass 21, count 2 2006.257.14:20:40.29#ibcon#read 6, iclass 21, count 2 2006.257.14:20:40.29#ibcon#end of sib2, iclass 21, count 2 2006.257.14:20:40.29#ibcon#*after write, iclass 21, count 2 2006.257.14:20:40.29#ibcon#*before return 0, iclass 21, count 2 2006.257.14:20:40.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:40.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:20:40.29#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.14:20:40.29#ibcon#ireg 7 cls_cnt 0 2006.257.14:20:40.29#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:40.41#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:40.41#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:40.41#ibcon#enter wrdev, iclass 21, count 0 2006.257.14:20:40.41#ibcon#first serial, iclass 21, count 0 2006.257.14:20:40.41#ibcon#enter sib2, iclass 21, count 0 2006.257.14:20:40.41#ibcon#flushed, iclass 21, count 0 2006.257.14:20:40.41#ibcon#about to write, iclass 21, count 0 2006.257.14:20:40.41#ibcon#wrote, iclass 21, count 0 2006.257.14:20:40.41#ibcon#about to read 3, iclass 21, count 0 2006.257.14:20:40.43#ibcon#read 3, iclass 21, count 0 2006.257.14:20:40.43#ibcon#about to read 4, iclass 21, count 0 2006.257.14:20:40.43#ibcon#read 4, iclass 21, count 0 2006.257.14:20:40.43#ibcon#about to read 5, iclass 21, count 0 2006.257.14:20:40.43#ibcon#read 5, iclass 21, count 0 2006.257.14:20:40.43#ibcon#about to read 6, iclass 21, count 0 2006.257.14:20:40.43#ibcon#read 6, iclass 21, count 0 2006.257.14:20:40.43#ibcon#end of sib2, iclass 21, count 0 2006.257.14:20:40.43#ibcon#*mode == 0, iclass 21, count 0 2006.257.14:20:40.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.14:20:40.43#ibcon#[27=USB\r\n] 2006.257.14:20:40.43#ibcon#*before write, iclass 21, count 0 2006.257.14:20:40.43#ibcon#enter sib2, iclass 21, count 0 2006.257.14:20:40.43#ibcon#flushed, iclass 21, count 0 2006.257.14:20:40.43#ibcon#about to write, iclass 21, count 0 2006.257.14:20:40.43#ibcon#wrote, iclass 21, count 0 2006.257.14:20:40.43#ibcon#about to read 3, iclass 21, count 0 2006.257.14:20:40.46#ibcon#read 3, iclass 21, count 0 2006.257.14:20:40.46#ibcon#about to read 4, iclass 21, count 0 2006.257.14:20:40.46#ibcon#read 4, iclass 21, count 0 2006.257.14:20:40.46#ibcon#about to read 5, iclass 21, count 0 2006.257.14:20:40.46#ibcon#read 5, iclass 21, count 0 2006.257.14:20:40.46#ibcon#about to read 6, iclass 21, count 0 2006.257.14:20:40.46#ibcon#read 6, iclass 21, count 0 2006.257.14:20:40.46#ibcon#end of sib2, iclass 21, count 0 2006.257.14:20:40.46#ibcon#*after write, iclass 21, count 0 2006.257.14:20:40.46#ibcon#*before return 0, iclass 21, count 0 2006.257.14:20:40.46#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:40.46#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:20:40.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.14:20:40.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.14:20:40.46$vck44/vabw=wide 2006.257.14:20:40.46#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.14:20:40.46#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.14:20:40.46#ibcon#ireg 8 cls_cnt 0 2006.257.14:20:40.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:40.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:40.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:40.46#ibcon#enter wrdev, iclass 23, count 0 2006.257.14:20:40.46#ibcon#first serial, iclass 23, count 0 2006.257.14:20:40.46#ibcon#enter sib2, iclass 23, count 0 2006.257.14:20:40.46#ibcon#flushed, iclass 23, count 0 2006.257.14:20:40.46#ibcon#about to write, iclass 23, count 0 2006.257.14:20:40.46#ibcon#wrote, iclass 23, count 0 2006.257.14:20:40.46#ibcon#about to read 3, iclass 23, count 0 2006.257.14:20:40.48#ibcon#read 3, iclass 23, count 0 2006.257.14:20:40.48#ibcon#about to read 4, iclass 23, count 0 2006.257.14:20:40.48#ibcon#read 4, iclass 23, count 0 2006.257.14:20:40.48#ibcon#about to read 5, iclass 23, count 0 2006.257.14:20:40.48#ibcon#read 5, iclass 23, count 0 2006.257.14:20:40.48#ibcon#about to read 6, iclass 23, count 0 2006.257.14:20:40.48#ibcon#read 6, iclass 23, count 0 2006.257.14:20:40.48#ibcon#end of sib2, iclass 23, count 0 2006.257.14:20:40.48#ibcon#*mode == 0, iclass 23, count 0 2006.257.14:20:40.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.14:20:40.48#ibcon#[25=BW32\r\n] 2006.257.14:20:40.48#ibcon#*before write, iclass 23, count 0 2006.257.14:20:40.48#ibcon#enter sib2, iclass 23, count 0 2006.257.14:20:40.48#ibcon#flushed, iclass 23, count 0 2006.257.14:20:40.48#ibcon#about to write, iclass 23, count 0 2006.257.14:20:40.48#ibcon#wrote, iclass 23, count 0 2006.257.14:20:40.48#ibcon#about to read 3, iclass 23, count 0 2006.257.14:20:40.51#ibcon#read 3, iclass 23, count 0 2006.257.14:20:40.51#ibcon#about to read 4, iclass 23, count 0 2006.257.14:20:40.51#ibcon#read 4, iclass 23, count 0 2006.257.14:20:40.51#ibcon#about to read 5, iclass 23, count 0 2006.257.14:20:40.51#ibcon#read 5, iclass 23, count 0 2006.257.14:20:40.51#ibcon#about to read 6, iclass 23, count 0 2006.257.14:20:40.51#ibcon#read 6, iclass 23, count 0 2006.257.14:20:40.51#ibcon#end of sib2, iclass 23, count 0 2006.257.14:20:40.51#ibcon#*after write, iclass 23, count 0 2006.257.14:20:40.51#ibcon#*before return 0, iclass 23, count 0 2006.257.14:20:40.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:40.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.14:20:40.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.14:20:40.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.14:20:40.51$vck44/vbbw=wide 2006.257.14:20:40.51#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.14:20:40.51#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.14:20:40.51#ibcon#ireg 8 cls_cnt 0 2006.257.14:20:40.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:20:40.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:20:40.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:20:40.58#ibcon#enter wrdev, iclass 25, count 0 2006.257.14:20:40.58#ibcon#first serial, iclass 25, count 0 2006.257.14:20:40.58#ibcon#enter sib2, iclass 25, count 0 2006.257.14:20:40.58#ibcon#flushed, iclass 25, count 0 2006.257.14:20:40.58#ibcon#about to write, iclass 25, count 0 2006.257.14:20:40.58#ibcon#wrote, iclass 25, count 0 2006.257.14:20:40.58#ibcon#about to read 3, iclass 25, count 0 2006.257.14:20:40.60#ibcon#read 3, iclass 25, count 0 2006.257.14:20:40.60#ibcon#about to read 4, iclass 25, count 0 2006.257.14:20:40.60#ibcon#read 4, iclass 25, count 0 2006.257.14:20:40.60#ibcon#about to read 5, iclass 25, count 0 2006.257.14:20:40.60#ibcon#read 5, iclass 25, count 0 2006.257.14:20:40.60#ibcon#about to read 6, iclass 25, count 0 2006.257.14:20:40.60#ibcon#read 6, iclass 25, count 0 2006.257.14:20:40.60#ibcon#end of sib2, iclass 25, count 0 2006.257.14:20:40.60#ibcon#*mode == 0, iclass 25, count 0 2006.257.14:20:40.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.14:20:40.60#ibcon#[27=BW32\r\n] 2006.257.14:20:40.60#ibcon#*before write, iclass 25, count 0 2006.257.14:20:40.60#ibcon#enter sib2, iclass 25, count 0 2006.257.14:20:40.60#ibcon#flushed, iclass 25, count 0 2006.257.14:20:40.60#ibcon#about to write, iclass 25, count 0 2006.257.14:20:40.60#ibcon#wrote, iclass 25, count 0 2006.257.14:20:40.60#ibcon#about to read 3, iclass 25, count 0 2006.257.14:20:40.63#ibcon#read 3, iclass 25, count 0 2006.257.14:20:41.59#ibcon#about to read 4, iclass 25, count 0 2006.257.14:20:41.59#ibcon#read 4, iclass 25, count 0 2006.257.14:20:41.59#ibcon#about to read 5, iclass 25, count 0 2006.257.14:20:41.59#ibcon#read 5, iclass 25, count 0 2006.257.14:20:41.59#ibcon#about to read 6, iclass 25, count 0 2006.257.14:20:41.59#ibcon#read 6, iclass 25, count 0 2006.257.14:20:41.59#ibcon#end of sib2, iclass 25, count 0 2006.257.14:20:41.59#ibcon#*after write, iclass 25, count 0 2006.257.14:20:41.59#ibcon#*before return 0, iclass 25, count 0 2006.257.14:20:41.39#abcon#<5=/14 1.6 4.8 17.45 971014.0\r\n> 2006.257.14:20:41.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:20:41.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:20:41.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.14:20:41.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.14:20:41.59$setupk4/ifdk4 2006.257.14:20:41.59$ifdk4/lo= 2006.257.14:20:41.59$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:20:41.59$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:20:41.59$ifdk4/patch= 2006.257.14:20:41.59$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:20:41.59$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:20:41.59$setupk4/!*+20s 2006.257.14:20:41.61#abcon#{5=INTERFACE CLEAR} 2006.257.14:20:41.67#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:20:51.76#abcon#<5=/14 1.7 4.7 17.45 971014.0\r\n> 2006.257.14:20:51.78#abcon#{5=INTERFACE CLEAR} 2006.257.14:20:51.84#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:20:52.07$setupk4/"tpicd 2006.257.14:20:52.07$setupk4/echo=off 2006.257.14:20:52.07$setupk4/xlog=off 2006.257.14:20:52.07:!2006.257.14:29:05 2006.257.14:21:09.13#trakl#Source acquired 2006.257.14:21:09.13#flagr#flagr/antenna,acquired 2006.257.14:29:05.01:preob 2006.257.14:29:06.13/onsource/TRACKING 2006.257.14:29:06.14:!2006.257.14:29:15 2006.257.14:29:15.01:"tape 2006.257.14:29:15.01:"st=record 2006.257.14:29:15.02:data_valid=on 2006.257.14:29:15.02:midob 2006.257.14:29:16.13/onsource/TRACKING 2006.257.14:29:16.14/wx/17.45,1014.1,97 2006.257.14:29:16.35/cable/+6.4818E-03 2006.257.14:29:17.44/va/01,08,usb,yes,31,33 2006.257.14:29:17.44/va/02,07,usb,yes,33,34 2006.257.14:29:17.44/va/03,08,usb,yes,30,32 2006.257.14:29:17.44/va/04,07,usb,yes,34,36 2006.257.14:29:17.44/va/05,04,usb,yes,31,31 2006.257.14:29:17.44/va/06,04,usb,yes,34,34 2006.257.14:29:17.44/va/07,04,usb,yes,35,35 2006.257.14:29:17.44/va/08,04,usb,yes,29,36 2006.257.14:29:17.67/valo/01,524.99,yes,locked 2006.257.14:29:17.67/valo/02,534.99,yes,locked 2006.257.14:29:17.67/valo/03,564.99,yes,locked 2006.257.14:29:17.67/valo/04,624.99,yes,locked 2006.257.14:29:17.67/valo/05,734.99,yes,locked 2006.257.14:29:17.67/valo/06,814.99,yes,locked 2006.257.14:29:17.67/valo/07,864.99,yes,locked 2006.257.14:29:17.67/valo/08,884.99,yes,locked 2006.257.14:29:18.76/vb/01,04,usb,yes,30,28 2006.257.14:29:18.76/vb/02,05,usb,yes,29,29 2006.257.14:29:18.76/vb/03,04,usb,yes,30,33 2006.257.14:29:18.76/vb/04,05,usb,yes,30,29 2006.257.14:29:18.76/vb/05,04,usb,yes,26,29 2006.257.14:29:18.76/vb/06,04,usb,yes,31,27 2006.257.14:29:18.76/vb/07,04,usb,yes,31,31 2006.257.14:29:18.76/vb/08,04,usb,yes,28,32 2006.257.14:29:19.00/vblo/01,629.99,yes,locked 2006.257.14:29:19.00/vblo/02,634.99,yes,locked 2006.257.14:29:19.00/vblo/03,649.99,yes,locked 2006.257.14:29:19.00/vblo/04,679.99,yes,locked 2006.257.14:29:19.00/vblo/05,709.99,yes,locked 2006.257.14:29:19.00/vblo/06,719.99,yes,locked 2006.257.14:29:19.00/vblo/07,734.99,yes,locked 2006.257.14:29:19.00/vblo/08,744.99,yes,locked 2006.257.14:29:19.15/vabw/8 2006.257.14:29:19.30/vbbw/8 2006.257.14:29:19.39/xfe/off,on,16.5 2006.257.14:29:19.76/ifatt/23,28,28,28 2006.257.14:29:20.07/fmout-gps/S +4.59E-07 2006.257.14:29:20.12:!2006.257.14:31:55 2006.257.14:31:55.01:data_valid=off 2006.257.14:31:55.02:"et 2006.257.14:31:55.02:!+3s 2006.257.14:31:58.03:"tape 2006.257.14:31:58.04:postob 2006.257.14:31:58.16/cable/+6.4827E-03 2006.257.14:31:58.17/wx/17.45,1014.1,97 2006.257.14:31:58.22/fmout-gps/S +4.59E-07 2006.257.14:31:58.23:scan_name=257-1434,jd0609,70 2006.257.14:31:58.23:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.14:31:59.14#flagr#flagr/antenna,new-source 2006.257.14:31:59.15:checkk5 2006.257.14:31:59.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:31:59.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:32:00.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:32:00.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:32:01.16/chk_obsdata//k5ts1/T2571429??a.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.14:32:01.57/chk_obsdata//k5ts2/T2571429??b.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.14:32:01.97/chk_obsdata//k5ts3/T2571429??c.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.14:32:02.37/chk_obsdata//k5ts4/T2571429??d.dat file size is correct (nominal:640MB, actual:636MB). 2006.257.14:32:03.08/k5log//k5ts1_log_newline 2006.257.14:32:03.79/k5log//k5ts2_log_newline 2006.257.14:32:04.51/k5log//k5ts3_log_newline 2006.257.14:32:05.23/k5log//k5ts4_log_newline 2006.257.14:32:05.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:32:05.25:setupk4=1 2006.257.14:32:05.25$setupk4/echo=on 2006.257.14:32:05.25$setupk4/pcalon 2006.257.14:32:05.25$pcalon/"no phase cal control is implemented here 2006.257.14:32:05.25$setupk4/"tpicd=stop 2006.257.14:32:05.25$setupk4/"rec=synch_on 2006.257.14:32:05.25$setupk4/"rec_mode=128 2006.257.14:32:05.25$setupk4/!* 2006.257.14:32:05.25$setupk4/recpk4 2006.257.14:32:05.25$recpk4/recpatch= 2006.257.14:32:05.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:32:05.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:32:05.26$setupk4/vck44 2006.257.14:32:05.26$vck44/valo=1,524.99 2006.257.14:32:05.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.14:32:05.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.14:32:05.26#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:05.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:05.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:05.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:05.26#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:32:05.26#ibcon#first serial, iclass 14, count 0 2006.257.14:32:05.26#ibcon#enter sib2, iclass 14, count 0 2006.257.14:32:05.26#ibcon#flushed, iclass 14, count 0 2006.257.14:32:05.26#ibcon#about to write, iclass 14, count 0 2006.257.14:32:05.26#ibcon#wrote, iclass 14, count 0 2006.257.14:32:05.26#ibcon#about to read 3, iclass 14, count 0 2006.257.14:32:05.27#ibcon#read 3, iclass 14, count 0 2006.257.14:32:05.27#ibcon#about to read 4, iclass 14, count 0 2006.257.14:32:05.27#ibcon#read 4, iclass 14, count 0 2006.257.14:32:05.27#ibcon#about to read 5, iclass 14, count 0 2006.257.14:32:05.27#ibcon#read 5, iclass 14, count 0 2006.257.14:32:05.27#ibcon#about to read 6, iclass 14, count 0 2006.257.14:32:05.27#ibcon#read 6, iclass 14, count 0 2006.257.14:32:05.27#ibcon#end of sib2, iclass 14, count 0 2006.257.14:32:05.27#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:32:05.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:32:05.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:32:05.27#ibcon#*before write, iclass 14, count 0 2006.257.14:32:05.27#ibcon#enter sib2, iclass 14, count 0 2006.257.14:32:05.27#ibcon#flushed, iclass 14, count 0 2006.257.14:32:05.27#ibcon#about to write, iclass 14, count 0 2006.257.14:32:05.27#ibcon#wrote, iclass 14, count 0 2006.257.14:32:05.27#ibcon#about to read 3, iclass 14, count 0 2006.257.14:32:05.32#ibcon#read 3, iclass 14, count 0 2006.257.14:32:05.32#ibcon#about to read 4, iclass 14, count 0 2006.257.14:32:05.32#ibcon#read 4, iclass 14, count 0 2006.257.14:32:05.32#ibcon#about to read 5, iclass 14, count 0 2006.257.14:32:05.32#ibcon#read 5, iclass 14, count 0 2006.257.14:32:05.32#ibcon#about to read 6, iclass 14, count 0 2006.257.14:32:05.32#ibcon#read 6, iclass 14, count 0 2006.257.14:32:05.32#ibcon#end of sib2, iclass 14, count 0 2006.257.14:32:05.32#ibcon#*after write, iclass 14, count 0 2006.257.14:32:05.32#ibcon#*before return 0, iclass 14, count 0 2006.257.14:32:05.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:05.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:05.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:32:05.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:32:05.32$vck44/va=1,8 2006.257.14:32:05.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.14:32:05.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.14:32:05.32#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:05.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:05.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:05.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:05.32#ibcon#enter wrdev, iclass 16, count 2 2006.257.14:32:05.32#ibcon#first serial, iclass 16, count 2 2006.257.14:32:05.32#ibcon#enter sib2, iclass 16, count 2 2006.257.14:32:05.32#ibcon#flushed, iclass 16, count 2 2006.257.14:32:05.32#ibcon#about to write, iclass 16, count 2 2006.257.14:32:05.32#ibcon#wrote, iclass 16, count 2 2006.257.14:32:05.32#ibcon#about to read 3, iclass 16, count 2 2006.257.14:32:05.34#ibcon#read 3, iclass 16, count 2 2006.257.14:32:05.34#ibcon#about to read 4, iclass 16, count 2 2006.257.14:32:05.34#ibcon#read 4, iclass 16, count 2 2006.257.14:32:05.34#ibcon#about to read 5, iclass 16, count 2 2006.257.14:32:05.34#ibcon#read 5, iclass 16, count 2 2006.257.14:32:05.34#ibcon#about to read 6, iclass 16, count 2 2006.257.14:32:05.34#ibcon#read 6, iclass 16, count 2 2006.257.14:32:05.34#ibcon#end of sib2, iclass 16, count 2 2006.257.14:32:05.34#ibcon#*mode == 0, iclass 16, count 2 2006.257.14:32:05.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.14:32:05.34#ibcon#[25=AT01-08\r\n] 2006.257.14:32:05.34#ibcon#*before write, iclass 16, count 2 2006.257.14:32:05.34#ibcon#enter sib2, iclass 16, count 2 2006.257.14:32:05.34#ibcon#flushed, iclass 16, count 2 2006.257.14:32:05.34#ibcon#about to write, iclass 16, count 2 2006.257.14:32:05.34#ibcon#wrote, iclass 16, count 2 2006.257.14:32:05.34#ibcon#about to read 3, iclass 16, count 2 2006.257.14:32:05.37#ibcon#read 3, iclass 16, count 2 2006.257.14:32:05.37#ibcon#about to read 4, iclass 16, count 2 2006.257.14:32:05.37#ibcon#read 4, iclass 16, count 2 2006.257.14:32:05.37#ibcon#about to read 5, iclass 16, count 2 2006.257.14:32:05.37#ibcon#read 5, iclass 16, count 2 2006.257.14:32:05.37#ibcon#about to read 6, iclass 16, count 2 2006.257.14:32:05.37#ibcon#read 6, iclass 16, count 2 2006.257.14:32:05.37#ibcon#end of sib2, iclass 16, count 2 2006.257.14:32:05.37#ibcon#*after write, iclass 16, count 2 2006.257.14:32:05.37#ibcon#*before return 0, iclass 16, count 2 2006.257.14:32:05.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:05.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:05.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.14:32:05.37#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:05.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:05.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:05.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:05.49#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:32:05.49#ibcon#first serial, iclass 16, count 0 2006.257.14:32:05.49#ibcon#enter sib2, iclass 16, count 0 2006.257.14:32:05.49#ibcon#flushed, iclass 16, count 0 2006.257.14:32:05.49#ibcon#about to write, iclass 16, count 0 2006.257.14:32:05.49#ibcon#wrote, iclass 16, count 0 2006.257.14:32:05.49#ibcon#about to read 3, iclass 16, count 0 2006.257.14:32:05.51#ibcon#read 3, iclass 16, count 0 2006.257.14:32:05.51#ibcon#about to read 4, iclass 16, count 0 2006.257.14:32:05.51#ibcon#read 4, iclass 16, count 0 2006.257.14:32:05.51#ibcon#about to read 5, iclass 16, count 0 2006.257.14:32:05.51#ibcon#read 5, iclass 16, count 0 2006.257.14:32:05.51#ibcon#about to read 6, iclass 16, count 0 2006.257.14:32:05.51#ibcon#read 6, iclass 16, count 0 2006.257.14:32:05.51#ibcon#end of sib2, iclass 16, count 0 2006.257.14:32:05.51#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:32:05.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:32:05.51#ibcon#[25=USB\r\n] 2006.257.14:32:05.51#ibcon#*before write, iclass 16, count 0 2006.257.14:32:05.51#ibcon#enter sib2, iclass 16, count 0 2006.257.14:32:05.51#ibcon#flushed, iclass 16, count 0 2006.257.14:32:05.51#ibcon#about to write, iclass 16, count 0 2006.257.14:32:05.51#ibcon#wrote, iclass 16, count 0 2006.257.14:32:05.51#ibcon#about to read 3, iclass 16, count 0 2006.257.14:32:05.54#ibcon#read 3, iclass 16, count 0 2006.257.14:32:05.54#ibcon#about to read 4, iclass 16, count 0 2006.257.14:32:05.54#ibcon#read 4, iclass 16, count 0 2006.257.14:32:05.54#ibcon#about to read 5, iclass 16, count 0 2006.257.14:32:05.54#ibcon#read 5, iclass 16, count 0 2006.257.14:32:05.54#ibcon#about to read 6, iclass 16, count 0 2006.257.14:32:05.54#ibcon#read 6, iclass 16, count 0 2006.257.14:32:05.54#ibcon#end of sib2, iclass 16, count 0 2006.257.14:32:05.54#ibcon#*after write, iclass 16, count 0 2006.257.14:32:05.54#ibcon#*before return 0, iclass 16, count 0 2006.257.14:32:05.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:05.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:05.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:32:05.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:32:05.54$vck44/valo=2,534.99 2006.257.14:32:05.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.14:32:05.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.14:32:05.54#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:05.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:05.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:05.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:05.54#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:32:05.54#ibcon#first serial, iclass 18, count 0 2006.257.14:32:05.54#ibcon#enter sib2, iclass 18, count 0 2006.257.14:32:05.54#ibcon#flushed, iclass 18, count 0 2006.257.14:32:05.54#ibcon#about to write, iclass 18, count 0 2006.257.14:32:05.54#ibcon#wrote, iclass 18, count 0 2006.257.14:32:05.54#ibcon#about to read 3, iclass 18, count 0 2006.257.14:32:05.56#ibcon#read 3, iclass 18, count 0 2006.257.14:32:05.56#ibcon#about to read 4, iclass 18, count 0 2006.257.14:32:05.56#ibcon#read 4, iclass 18, count 0 2006.257.14:32:05.56#ibcon#about to read 5, iclass 18, count 0 2006.257.14:32:05.56#ibcon#read 5, iclass 18, count 0 2006.257.14:32:05.56#ibcon#about to read 6, iclass 18, count 0 2006.257.14:32:05.56#ibcon#read 6, iclass 18, count 0 2006.257.14:32:05.56#ibcon#end of sib2, iclass 18, count 0 2006.257.14:32:05.56#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:32:05.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:32:05.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:32:05.56#ibcon#*before write, iclass 18, count 0 2006.257.14:32:05.56#ibcon#enter sib2, iclass 18, count 0 2006.257.14:32:05.56#ibcon#flushed, iclass 18, count 0 2006.257.14:32:05.56#ibcon#about to write, iclass 18, count 0 2006.257.14:32:05.56#ibcon#wrote, iclass 18, count 0 2006.257.14:32:05.56#ibcon#about to read 3, iclass 18, count 0 2006.257.14:32:05.60#ibcon#read 3, iclass 18, count 0 2006.257.14:32:05.60#ibcon#about to read 4, iclass 18, count 0 2006.257.14:32:05.60#ibcon#read 4, iclass 18, count 0 2006.257.14:32:05.60#ibcon#about to read 5, iclass 18, count 0 2006.257.14:32:05.60#ibcon#read 5, iclass 18, count 0 2006.257.14:32:05.60#ibcon#about to read 6, iclass 18, count 0 2006.257.14:32:05.60#ibcon#read 6, iclass 18, count 0 2006.257.14:32:05.60#ibcon#end of sib2, iclass 18, count 0 2006.257.14:32:05.60#ibcon#*after write, iclass 18, count 0 2006.257.14:32:05.60#ibcon#*before return 0, iclass 18, count 0 2006.257.14:32:05.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:05.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:05.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:32:05.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:32:05.60$vck44/va=2,7 2006.257.14:32:05.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.14:32:05.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.14:32:05.60#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:05.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:05.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:05.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:05.66#ibcon#enter wrdev, iclass 20, count 2 2006.257.14:32:05.66#ibcon#first serial, iclass 20, count 2 2006.257.14:32:05.66#ibcon#enter sib2, iclass 20, count 2 2006.257.14:32:05.66#ibcon#flushed, iclass 20, count 2 2006.257.14:32:05.66#ibcon#about to write, iclass 20, count 2 2006.257.14:32:05.66#ibcon#wrote, iclass 20, count 2 2006.257.14:32:05.66#ibcon#about to read 3, iclass 20, count 2 2006.257.14:32:05.68#ibcon#read 3, iclass 20, count 2 2006.257.14:32:05.68#ibcon#about to read 4, iclass 20, count 2 2006.257.14:32:05.68#ibcon#read 4, iclass 20, count 2 2006.257.14:32:05.68#ibcon#about to read 5, iclass 20, count 2 2006.257.14:32:05.68#ibcon#read 5, iclass 20, count 2 2006.257.14:32:05.68#ibcon#about to read 6, iclass 20, count 2 2006.257.14:32:05.68#ibcon#read 6, iclass 20, count 2 2006.257.14:32:05.68#ibcon#end of sib2, iclass 20, count 2 2006.257.14:32:05.68#ibcon#*mode == 0, iclass 20, count 2 2006.257.14:32:05.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.14:32:05.68#ibcon#[25=AT02-07\r\n] 2006.257.14:32:05.68#ibcon#*before write, iclass 20, count 2 2006.257.14:32:05.68#ibcon#enter sib2, iclass 20, count 2 2006.257.14:32:05.68#ibcon#flushed, iclass 20, count 2 2006.257.14:32:05.68#ibcon#about to write, iclass 20, count 2 2006.257.14:32:05.68#ibcon#wrote, iclass 20, count 2 2006.257.14:32:05.68#ibcon#about to read 3, iclass 20, count 2 2006.257.14:32:05.71#ibcon#read 3, iclass 20, count 2 2006.257.14:32:05.71#ibcon#about to read 4, iclass 20, count 2 2006.257.14:32:05.71#ibcon#read 4, iclass 20, count 2 2006.257.14:32:05.71#ibcon#about to read 5, iclass 20, count 2 2006.257.14:32:05.71#ibcon#read 5, iclass 20, count 2 2006.257.14:32:05.71#ibcon#about to read 6, iclass 20, count 2 2006.257.14:32:05.71#ibcon#read 6, iclass 20, count 2 2006.257.14:32:05.71#ibcon#end of sib2, iclass 20, count 2 2006.257.14:32:05.71#ibcon#*after write, iclass 20, count 2 2006.257.14:32:05.71#ibcon#*before return 0, iclass 20, count 2 2006.257.14:32:05.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:05.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:05.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.14:32:05.71#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:05.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:05.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:05.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:05.83#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:32:05.83#ibcon#first serial, iclass 20, count 0 2006.257.14:32:05.83#ibcon#enter sib2, iclass 20, count 0 2006.257.14:32:05.83#ibcon#flushed, iclass 20, count 0 2006.257.14:32:05.83#ibcon#about to write, iclass 20, count 0 2006.257.14:32:05.83#ibcon#wrote, iclass 20, count 0 2006.257.14:32:05.83#ibcon#about to read 3, iclass 20, count 0 2006.257.14:32:05.85#ibcon#read 3, iclass 20, count 0 2006.257.14:32:05.85#ibcon#about to read 4, iclass 20, count 0 2006.257.14:32:05.85#ibcon#read 4, iclass 20, count 0 2006.257.14:32:05.85#ibcon#about to read 5, iclass 20, count 0 2006.257.14:32:05.85#ibcon#read 5, iclass 20, count 0 2006.257.14:32:05.85#ibcon#about to read 6, iclass 20, count 0 2006.257.14:32:05.85#ibcon#read 6, iclass 20, count 0 2006.257.14:32:05.85#ibcon#end of sib2, iclass 20, count 0 2006.257.14:32:05.85#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:32:05.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:32:05.85#ibcon#[25=USB\r\n] 2006.257.14:32:05.85#ibcon#*before write, iclass 20, count 0 2006.257.14:32:05.85#ibcon#enter sib2, iclass 20, count 0 2006.257.14:32:05.85#ibcon#flushed, iclass 20, count 0 2006.257.14:32:05.85#ibcon#about to write, iclass 20, count 0 2006.257.14:32:05.85#ibcon#wrote, iclass 20, count 0 2006.257.14:32:05.85#ibcon#about to read 3, iclass 20, count 0 2006.257.14:32:05.88#ibcon#read 3, iclass 20, count 0 2006.257.14:32:05.88#ibcon#about to read 4, iclass 20, count 0 2006.257.14:32:05.88#ibcon#read 4, iclass 20, count 0 2006.257.14:32:05.88#ibcon#about to read 5, iclass 20, count 0 2006.257.14:32:05.88#ibcon#read 5, iclass 20, count 0 2006.257.14:32:05.88#ibcon#about to read 6, iclass 20, count 0 2006.257.14:32:05.88#ibcon#read 6, iclass 20, count 0 2006.257.14:32:05.88#ibcon#end of sib2, iclass 20, count 0 2006.257.14:32:05.88#ibcon#*after write, iclass 20, count 0 2006.257.14:32:05.88#ibcon#*before return 0, iclass 20, count 0 2006.257.14:32:05.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:05.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:05.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:32:05.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:32:05.88$vck44/valo=3,564.99 2006.257.14:32:05.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.14:32:05.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.14:32:05.88#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:05.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:05.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:05.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:05.88#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:32:05.88#ibcon#first serial, iclass 22, count 0 2006.257.14:32:05.88#ibcon#enter sib2, iclass 22, count 0 2006.257.14:32:05.88#ibcon#flushed, iclass 22, count 0 2006.257.14:32:05.88#ibcon#about to write, iclass 22, count 0 2006.257.14:32:05.88#ibcon#wrote, iclass 22, count 0 2006.257.14:32:05.88#ibcon#about to read 3, iclass 22, count 0 2006.257.14:32:05.90#ibcon#read 3, iclass 22, count 0 2006.257.14:32:05.90#ibcon#about to read 4, iclass 22, count 0 2006.257.14:32:05.90#ibcon#read 4, iclass 22, count 0 2006.257.14:32:05.90#ibcon#about to read 5, iclass 22, count 0 2006.257.14:32:05.90#ibcon#read 5, iclass 22, count 0 2006.257.14:32:05.90#ibcon#about to read 6, iclass 22, count 0 2006.257.14:32:05.90#ibcon#read 6, iclass 22, count 0 2006.257.14:32:05.90#ibcon#end of sib2, iclass 22, count 0 2006.257.14:32:05.90#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:32:05.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:32:05.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:32:05.90#ibcon#*before write, iclass 22, count 0 2006.257.14:32:05.90#ibcon#enter sib2, iclass 22, count 0 2006.257.14:32:05.90#ibcon#flushed, iclass 22, count 0 2006.257.14:32:05.90#ibcon#about to write, iclass 22, count 0 2006.257.14:32:05.90#ibcon#wrote, iclass 22, count 0 2006.257.14:32:05.90#ibcon#about to read 3, iclass 22, count 0 2006.257.14:32:05.94#ibcon#read 3, iclass 22, count 0 2006.257.14:32:05.94#ibcon#about to read 4, iclass 22, count 0 2006.257.14:32:05.94#ibcon#read 4, iclass 22, count 0 2006.257.14:32:05.94#ibcon#about to read 5, iclass 22, count 0 2006.257.14:32:05.94#ibcon#read 5, iclass 22, count 0 2006.257.14:32:05.94#ibcon#about to read 6, iclass 22, count 0 2006.257.14:32:05.94#ibcon#read 6, iclass 22, count 0 2006.257.14:32:05.94#ibcon#end of sib2, iclass 22, count 0 2006.257.14:32:05.94#ibcon#*after write, iclass 22, count 0 2006.257.14:32:05.94#ibcon#*before return 0, iclass 22, count 0 2006.257.14:32:05.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:05.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:05.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:32:05.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:32:05.94$vck44/va=3,8 2006.257.14:32:05.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.14:32:05.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.14:32:05.94#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:05.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:06.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:06.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:06.00#ibcon#enter wrdev, iclass 24, count 2 2006.257.14:32:06.00#ibcon#first serial, iclass 24, count 2 2006.257.14:32:06.00#ibcon#enter sib2, iclass 24, count 2 2006.257.14:32:06.00#ibcon#flushed, iclass 24, count 2 2006.257.14:32:06.00#ibcon#about to write, iclass 24, count 2 2006.257.14:32:06.00#ibcon#wrote, iclass 24, count 2 2006.257.14:32:06.00#ibcon#about to read 3, iclass 24, count 2 2006.257.14:32:06.02#ibcon#read 3, iclass 24, count 2 2006.257.14:32:06.02#ibcon#about to read 4, iclass 24, count 2 2006.257.14:32:06.02#ibcon#read 4, iclass 24, count 2 2006.257.14:32:06.02#ibcon#about to read 5, iclass 24, count 2 2006.257.14:32:06.02#ibcon#read 5, iclass 24, count 2 2006.257.14:32:06.02#ibcon#about to read 6, iclass 24, count 2 2006.257.14:32:06.02#ibcon#read 6, iclass 24, count 2 2006.257.14:32:06.02#ibcon#end of sib2, iclass 24, count 2 2006.257.14:32:06.02#ibcon#*mode == 0, iclass 24, count 2 2006.257.14:32:06.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.14:32:06.02#ibcon#[25=AT03-08\r\n] 2006.257.14:32:06.02#ibcon#*before write, iclass 24, count 2 2006.257.14:32:06.02#ibcon#enter sib2, iclass 24, count 2 2006.257.14:32:06.02#ibcon#flushed, iclass 24, count 2 2006.257.14:32:06.02#ibcon#about to write, iclass 24, count 2 2006.257.14:32:06.02#ibcon#wrote, iclass 24, count 2 2006.257.14:32:06.02#ibcon#about to read 3, iclass 24, count 2 2006.257.14:32:06.05#ibcon#read 3, iclass 24, count 2 2006.257.14:32:06.05#ibcon#about to read 4, iclass 24, count 2 2006.257.14:32:06.05#ibcon#read 4, iclass 24, count 2 2006.257.14:32:06.05#ibcon#about to read 5, iclass 24, count 2 2006.257.14:32:06.05#ibcon#read 5, iclass 24, count 2 2006.257.14:32:06.05#ibcon#about to read 6, iclass 24, count 2 2006.257.14:32:06.05#ibcon#read 6, iclass 24, count 2 2006.257.14:32:06.05#ibcon#end of sib2, iclass 24, count 2 2006.257.14:32:06.05#ibcon#*after write, iclass 24, count 2 2006.257.14:32:06.05#ibcon#*before return 0, iclass 24, count 2 2006.257.14:32:06.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:06.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:06.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.14:32:06.05#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:06.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:06.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:06.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:06.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:32:06.17#ibcon#first serial, iclass 24, count 0 2006.257.14:32:06.17#ibcon#enter sib2, iclass 24, count 0 2006.257.14:32:06.17#ibcon#flushed, iclass 24, count 0 2006.257.14:32:06.17#ibcon#about to write, iclass 24, count 0 2006.257.14:32:06.17#ibcon#wrote, iclass 24, count 0 2006.257.14:32:06.17#ibcon#about to read 3, iclass 24, count 0 2006.257.14:32:06.19#ibcon#read 3, iclass 24, count 0 2006.257.14:32:06.19#ibcon#about to read 4, iclass 24, count 0 2006.257.14:32:06.19#ibcon#read 4, iclass 24, count 0 2006.257.14:32:06.19#ibcon#about to read 5, iclass 24, count 0 2006.257.14:32:06.19#ibcon#read 5, iclass 24, count 0 2006.257.14:32:06.19#ibcon#about to read 6, iclass 24, count 0 2006.257.14:32:06.19#ibcon#read 6, iclass 24, count 0 2006.257.14:32:06.19#ibcon#end of sib2, iclass 24, count 0 2006.257.14:32:06.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:32:06.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:32:06.19#ibcon#[25=USB\r\n] 2006.257.14:32:06.19#ibcon#*before write, iclass 24, count 0 2006.257.14:32:06.19#ibcon#enter sib2, iclass 24, count 0 2006.257.14:32:06.19#ibcon#flushed, iclass 24, count 0 2006.257.14:32:06.19#ibcon#about to write, iclass 24, count 0 2006.257.14:32:06.19#ibcon#wrote, iclass 24, count 0 2006.257.14:32:06.19#ibcon#about to read 3, iclass 24, count 0 2006.257.14:32:06.22#ibcon#read 3, iclass 24, count 0 2006.257.14:32:06.22#ibcon#about to read 4, iclass 24, count 0 2006.257.14:32:06.22#ibcon#read 4, iclass 24, count 0 2006.257.14:32:06.22#ibcon#about to read 5, iclass 24, count 0 2006.257.14:32:06.22#ibcon#read 5, iclass 24, count 0 2006.257.14:32:06.22#ibcon#about to read 6, iclass 24, count 0 2006.257.14:32:06.22#ibcon#read 6, iclass 24, count 0 2006.257.14:32:06.22#ibcon#end of sib2, iclass 24, count 0 2006.257.14:32:06.22#ibcon#*after write, iclass 24, count 0 2006.257.14:32:06.22#ibcon#*before return 0, iclass 24, count 0 2006.257.14:32:06.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:06.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:06.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:32:06.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:32:06.22$vck44/valo=4,624.99 2006.257.14:32:06.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.14:32:06.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.14:32:06.22#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:06.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:06.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:06.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:06.22#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:32:06.22#ibcon#first serial, iclass 26, count 0 2006.257.14:32:06.22#ibcon#enter sib2, iclass 26, count 0 2006.257.14:32:06.22#ibcon#flushed, iclass 26, count 0 2006.257.14:32:06.22#ibcon#about to write, iclass 26, count 0 2006.257.14:32:06.22#ibcon#wrote, iclass 26, count 0 2006.257.14:32:06.22#ibcon#about to read 3, iclass 26, count 0 2006.257.14:32:06.24#ibcon#read 3, iclass 26, count 0 2006.257.14:32:06.24#ibcon#about to read 4, iclass 26, count 0 2006.257.14:32:06.24#ibcon#read 4, iclass 26, count 0 2006.257.14:32:06.24#ibcon#about to read 5, iclass 26, count 0 2006.257.14:32:06.24#ibcon#read 5, iclass 26, count 0 2006.257.14:32:06.24#ibcon#about to read 6, iclass 26, count 0 2006.257.14:32:06.24#ibcon#read 6, iclass 26, count 0 2006.257.14:32:06.24#ibcon#end of sib2, iclass 26, count 0 2006.257.14:32:06.24#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:32:06.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:32:06.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:32:06.24#ibcon#*before write, iclass 26, count 0 2006.257.14:32:06.24#ibcon#enter sib2, iclass 26, count 0 2006.257.14:32:06.24#ibcon#flushed, iclass 26, count 0 2006.257.14:32:06.24#ibcon#about to write, iclass 26, count 0 2006.257.14:32:06.24#ibcon#wrote, iclass 26, count 0 2006.257.14:32:06.24#ibcon#about to read 3, iclass 26, count 0 2006.257.14:32:06.28#ibcon#read 3, iclass 26, count 0 2006.257.14:32:06.28#ibcon#about to read 4, iclass 26, count 0 2006.257.14:32:06.28#ibcon#read 4, iclass 26, count 0 2006.257.14:32:06.28#ibcon#about to read 5, iclass 26, count 0 2006.257.14:32:06.28#ibcon#read 5, iclass 26, count 0 2006.257.14:32:06.28#ibcon#about to read 6, iclass 26, count 0 2006.257.14:32:06.28#ibcon#read 6, iclass 26, count 0 2006.257.14:32:06.28#ibcon#end of sib2, iclass 26, count 0 2006.257.14:32:06.28#ibcon#*after write, iclass 26, count 0 2006.257.14:32:06.28#ibcon#*before return 0, iclass 26, count 0 2006.257.14:32:06.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:06.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:06.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:32:06.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:32:06.28$vck44/va=4,7 2006.257.14:32:06.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.14:32:06.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.14:32:06.28#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:06.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:06.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:06.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:06.34#ibcon#enter wrdev, iclass 28, count 2 2006.257.14:32:06.34#ibcon#first serial, iclass 28, count 2 2006.257.14:32:06.34#ibcon#enter sib2, iclass 28, count 2 2006.257.14:32:06.34#ibcon#flushed, iclass 28, count 2 2006.257.14:32:06.34#ibcon#about to write, iclass 28, count 2 2006.257.14:32:06.34#ibcon#wrote, iclass 28, count 2 2006.257.14:32:06.34#ibcon#about to read 3, iclass 28, count 2 2006.257.14:32:06.36#ibcon#read 3, iclass 28, count 2 2006.257.14:32:06.36#ibcon#about to read 4, iclass 28, count 2 2006.257.14:32:06.36#ibcon#read 4, iclass 28, count 2 2006.257.14:32:06.36#ibcon#about to read 5, iclass 28, count 2 2006.257.14:32:06.36#ibcon#read 5, iclass 28, count 2 2006.257.14:32:06.36#ibcon#about to read 6, iclass 28, count 2 2006.257.14:32:06.36#ibcon#read 6, iclass 28, count 2 2006.257.14:32:06.36#ibcon#end of sib2, iclass 28, count 2 2006.257.14:32:06.36#ibcon#*mode == 0, iclass 28, count 2 2006.257.14:32:06.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.14:32:06.36#ibcon#[25=AT04-07\r\n] 2006.257.14:32:06.36#ibcon#*before write, iclass 28, count 2 2006.257.14:32:06.36#ibcon#enter sib2, iclass 28, count 2 2006.257.14:32:06.36#ibcon#flushed, iclass 28, count 2 2006.257.14:32:06.36#ibcon#about to write, iclass 28, count 2 2006.257.14:32:06.36#ibcon#wrote, iclass 28, count 2 2006.257.14:32:06.36#ibcon#about to read 3, iclass 28, count 2 2006.257.14:32:06.39#ibcon#read 3, iclass 28, count 2 2006.257.14:32:06.39#ibcon#about to read 4, iclass 28, count 2 2006.257.14:32:06.39#ibcon#read 4, iclass 28, count 2 2006.257.14:32:06.39#ibcon#about to read 5, iclass 28, count 2 2006.257.14:32:06.39#ibcon#read 5, iclass 28, count 2 2006.257.14:32:06.39#ibcon#about to read 6, iclass 28, count 2 2006.257.14:32:06.39#ibcon#read 6, iclass 28, count 2 2006.257.14:32:06.39#ibcon#end of sib2, iclass 28, count 2 2006.257.14:32:06.39#ibcon#*after write, iclass 28, count 2 2006.257.14:32:06.39#ibcon#*before return 0, iclass 28, count 2 2006.257.14:32:06.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:06.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:06.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.14:32:06.39#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:06.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:06.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:06.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:06.51#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:32:06.51#ibcon#first serial, iclass 28, count 0 2006.257.14:32:06.51#ibcon#enter sib2, iclass 28, count 0 2006.257.14:32:06.51#ibcon#flushed, iclass 28, count 0 2006.257.14:32:06.51#ibcon#about to write, iclass 28, count 0 2006.257.14:32:06.51#ibcon#wrote, iclass 28, count 0 2006.257.14:32:06.51#ibcon#about to read 3, iclass 28, count 0 2006.257.14:32:06.53#ibcon#read 3, iclass 28, count 0 2006.257.14:32:06.53#ibcon#about to read 4, iclass 28, count 0 2006.257.14:32:06.53#ibcon#read 4, iclass 28, count 0 2006.257.14:32:06.53#ibcon#about to read 5, iclass 28, count 0 2006.257.14:32:06.53#ibcon#read 5, iclass 28, count 0 2006.257.14:32:06.53#ibcon#about to read 6, iclass 28, count 0 2006.257.14:32:06.53#ibcon#read 6, iclass 28, count 0 2006.257.14:32:06.53#ibcon#end of sib2, iclass 28, count 0 2006.257.14:32:06.53#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:32:06.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:32:06.53#ibcon#[25=USB\r\n] 2006.257.14:32:06.53#ibcon#*before write, iclass 28, count 0 2006.257.14:32:06.53#ibcon#enter sib2, iclass 28, count 0 2006.257.14:32:06.53#ibcon#flushed, iclass 28, count 0 2006.257.14:32:06.53#ibcon#about to write, iclass 28, count 0 2006.257.14:32:06.53#ibcon#wrote, iclass 28, count 0 2006.257.14:32:06.53#ibcon#about to read 3, iclass 28, count 0 2006.257.14:32:06.56#ibcon#read 3, iclass 28, count 0 2006.257.14:32:06.56#ibcon#about to read 4, iclass 28, count 0 2006.257.14:32:06.56#ibcon#read 4, iclass 28, count 0 2006.257.14:32:06.56#ibcon#about to read 5, iclass 28, count 0 2006.257.14:32:06.56#ibcon#read 5, iclass 28, count 0 2006.257.14:32:06.56#ibcon#about to read 6, iclass 28, count 0 2006.257.14:32:06.56#ibcon#read 6, iclass 28, count 0 2006.257.14:32:06.56#ibcon#end of sib2, iclass 28, count 0 2006.257.14:32:06.56#ibcon#*after write, iclass 28, count 0 2006.257.14:32:06.56#ibcon#*before return 0, iclass 28, count 0 2006.257.14:32:06.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:06.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:06.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:32:06.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:32:06.56$vck44/valo=5,734.99 2006.257.14:32:06.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.14:32:06.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.14:32:06.56#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:06.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:06.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:06.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:06.56#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:32:06.56#ibcon#first serial, iclass 30, count 0 2006.257.14:32:06.56#ibcon#enter sib2, iclass 30, count 0 2006.257.14:32:06.56#ibcon#flushed, iclass 30, count 0 2006.257.14:32:06.56#ibcon#about to write, iclass 30, count 0 2006.257.14:32:06.56#ibcon#wrote, iclass 30, count 0 2006.257.14:32:06.56#ibcon#about to read 3, iclass 30, count 0 2006.257.14:32:06.58#ibcon#read 3, iclass 30, count 0 2006.257.14:32:06.58#ibcon#about to read 4, iclass 30, count 0 2006.257.14:32:06.58#ibcon#read 4, iclass 30, count 0 2006.257.14:32:06.58#ibcon#about to read 5, iclass 30, count 0 2006.257.14:32:06.58#ibcon#read 5, iclass 30, count 0 2006.257.14:32:06.58#ibcon#about to read 6, iclass 30, count 0 2006.257.14:32:06.58#ibcon#read 6, iclass 30, count 0 2006.257.14:32:06.58#ibcon#end of sib2, iclass 30, count 0 2006.257.14:32:06.58#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:32:06.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:32:06.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:32:06.58#ibcon#*before write, iclass 30, count 0 2006.257.14:32:06.58#ibcon#enter sib2, iclass 30, count 0 2006.257.14:32:06.58#ibcon#flushed, iclass 30, count 0 2006.257.14:32:06.58#ibcon#about to write, iclass 30, count 0 2006.257.14:32:06.58#ibcon#wrote, iclass 30, count 0 2006.257.14:32:06.58#ibcon#about to read 3, iclass 30, count 0 2006.257.14:32:06.62#ibcon#read 3, iclass 30, count 0 2006.257.14:32:06.62#ibcon#about to read 4, iclass 30, count 0 2006.257.14:32:06.62#ibcon#read 4, iclass 30, count 0 2006.257.14:32:06.62#ibcon#about to read 5, iclass 30, count 0 2006.257.14:32:06.62#ibcon#read 5, iclass 30, count 0 2006.257.14:32:06.62#ibcon#about to read 6, iclass 30, count 0 2006.257.14:32:06.62#ibcon#read 6, iclass 30, count 0 2006.257.14:32:06.62#ibcon#end of sib2, iclass 30, count 0 2006.257.14:32:06.62#ibcon#*after write, iclass 30, count 0 2006.257.14:32:06.62#ibcon#*before return 0, iclass 30, count 0 2006.257.14:32:06.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:06.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:06.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:32:06.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:32:06.62$vck44/va=5,4 2006.257.14:32:06.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.14:32:06.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.14:32:06.62#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:06.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:06.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:06.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:06.68#ibcon#enter wrdev, iclass 32, count 2 2006.257.14:32:06.68#ibcon#first serial, iclass 32, count 2 2006.257.14:32:06.68#ibcon#enter sib2, iclass 32, count 2 2006.257.14:32:06.68#ibcon#flushed, iclass 32, count 2 2006.257.14:32:06.68#ibcon#about to write, iclass 32, count 2 2006.257.14:32:06.68#ibcon#wrote, iclass 32, count 2 2006.257.14:32:06.68#ibcon#about to read 3, iclass 32, count 2 2006.257.14:32:06.70#ibcon#read 3, iclass 32, count 2 2006.257.14:32:06.70#ibcon#about to read 4, iclass 32, count 2 2006.257.14:32:06.70#ibcon#read 4, iclass 32, count 2 2006.257.14:32:06.70#ibcon#about to read 5, iclass 32, count 2 2006.257.14:32:06.70#ibcon#read 5, iclass 32, count 2 2006.257.14:32:06.70#ibcon#about to read 6, iclass 32, count 2 2006.257.14:32:06.70#ibcon#read 6, iclass 32, count 2 2006.257.14:32:06.70#ibcon#end of sib2, iclass 32, count 2 2006.257.14:32:06.70#ibcon#*mode == 0, iclass 32, count 2 2006.257.14:32:06.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.14:32:06.70#ibcon#[25=AT05-04\r\n] 2006.257.14:32:06.70#ibcon#*before write, iclass 32, count 2 2006.257.14:32:06.70#ibcon#enter sib2, iclass 32, count 2 2006.257.14:32:06.70#ibcon#flushed, iclass 32, count 2 2006.257.14:32:06.70#ibcon#about to write, iclass 32, count 2 2006.257.14:32:06.70#ibcon#wrote, iclass 32, count 2 2006.257.14:32:06.70#ibcon#about to read 3, iclass 32, count 2 2006.257.14:32:06.73#ibcon#read 3, iclass 32, count 2 2006.257.14:32:06.73#ibcon#about to read 4, iclass 32, count 2 2006.257.14:32:06.73#ibcon#read 4, iclass 32, count 2 2006.257.14:32:06.73#ibcon#about to read 5, iclass 32, count 2 2006.257.14:32:06.73#ibcon#read 5, iclass 32, count 2 2006.257.14:32:06.73#ibcon#about to read 6, iclass 32, count 2 2006.257.14:32:06.73#ibcon#read 6, iclass 32, count 2 2006.257.14:32:06.73#ibcon#end of sib2, iclass 32, count 2 2006.257.14:32:06.73#ibcon#*after write, iclass 32, count 2 2006.257.14:32:06.73#ibcon#*before return 0, iclass 32, count 2 2006.257.14:32:06.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:06.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:06.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.14:32:06.73#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:06.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:06.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:06.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:06.85#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:32:06.85#ibcon#first serial, iclass 32, count 0 2006.257.14:32:06.85#ibcon#enter sib2, iclass 32, count 0 2006.257.14:32:06.85#ibcon#flushed, iclass 32, count 0 2006.257.14:32:06.85#ibcon#about to write, iclass 32, count 0 2006.257.14:32:06.85#ibcon#wrote, iclass 32, count 0 2006.257.14:32:06.85#ibcon#about to read 3, iclass 32, count 0 2006.257.14:32:06.87#ibcon#read 3, iclass 32, count 0 2006.257.14:32:06.87#ibcon#about to read 4, iclass 32, count 0 2006.257.14:32:06.87#ibcon#read 4, iclass 32, count 0 2006.257.14:32:06.87#ibcon#about to read 5, iclass 32, count 0 2006.257.14:32:06.87#ibcon#read 5, iclass 32, count 0 2006.257.14:32:06.87#ibcon#about to read 6, iclass 32, count 0 2006.257.14:32:06.87#ibcon#read 6, iclass 32, count 0 2006.257.14:32:06.87#ibcon#end of sib2, iclass 32, count 0 2006.257.14:32:06.87#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:32:06.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:32:06.87#ibcon#[25=USB\r\n] 2006.257.14:32:06.87#ibcon#*before write, iclass 32, count 0 2006.257.14:32:06.87#ibcon#enter sib2, iclass 32, count 0 2006.257.14:32:06.87#ibcon#flushed, iclass 32, count 0 2006.257.14:32:06.87#ibcon#about to write, iclass 32, count 0 2006.257.14:32:06.87#ibcon#wrote, iclass 32, count 0 2006.257.14:32:06.87#ibcon#about to read 3, iclass 32, count 0 2006.257.14:32:06.90#ibcon#read 3, iclass 32, count 0 2006.257.14:32:06.90#ibcon#about to read 4, iclass 32, count 0 2006.257.14:32:06.90#ibcon#read 4, iclass 32, count 0 2006.257.14:32:06.90#ibcon#about to read 5, iclass 32, count 0 2006.257.14:32:06.90#ibcon#read 5, iclass 32, count 0 2006.257.14:32:06.90#ibcon#about to read 6, iclass 32, count 0 2006.257.14:32:06.90#ibcon#read 6, iclass 32, count 0 2006.257.14:32:06.90#ibcon#end of sib2, iclass 32, count 0 2006.257.14:32:06.90#ibcon#*after write, iclass 32, count 0 2006.257.14:32:06.90#ibcon#*before return 0, iclass 32, count 0 2006.257.14:32:06.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:06.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:06.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:32:06.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:32:06.90$vck44/valo=6,814.99 2006.257.14:32:06.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.14:32:06.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.14:32:06.90#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:06.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:06.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:06.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:06.90#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:32:06.90#ibcon#first serial, iclass 34, count 0 2006.257.14:32:06.90#ibcon#enter sib2, iclass 34, count 0 2006.257.14:32:06.90#ibcon#flushed, iclass 34, count 0 2006.257.14:32:06.90#ibcon#about to write, iclass 34, count 0 2006.257.14:32:06.90#ibcon#wrote, iclass 34, count 0 2006.257.14:32:06.90#ibcon#about to read 3, iclass 34, count 0 2006.257.14:32:06.92#ibcon#read 3, iclass 34, count 0 2006.257.14:32:06.92#ibcon#about to read 4, iclass 34, count 0 2006.257.14:32:06.92#ibcon#read 4, iclass 34, count 0 2006.257.14:32:06.92#ibcon#about to read 5, iclass 34, count 0 2006.257.14:32:06.92#ibcon#read 5, iclass 34, count 0 2006.257.14:32:06.92#ibcon#about to read 6, iclass 34, count 0 2006.257.14:32:06.92#ibcon#read 6, iclass 34, count 0 2006.257.14:32:06.92#ibcon#end of sib2, iclass 34, count 0 2006.257.14:32:06.92#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:32:06.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:32:06.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:32:06.92#ibcon#*before write, iclass 34, count 0 2006.257.14:32:06.92#ibcon#enter sib2, iclass 34, count 0 2006.257.14:32:06.92#ibcon#flushed, iclass 34, count 0 2006.257.14:32:06.92#ibcon#about to write, iclass 34, count 0 2006.257.14:32:06.92#ibcon#wrote, iclass 34, count 0 2006.257.14:32:06.92#ibcon#about to read 3, iclass 34, count 0 2006.257.14:32:06.96#ibcon#read 3, iclass 34, count 0 2006.257.14:32:06.96#ibcon#about to read 4, iclass 34, count 0 2006.257.14:32:06.96#ibcon#read 4, iclass 34, count 0 2006.257.14:32:06.96#ibcon#about to read 5, iclass 34, count 0 2006.257.14:32:06.96#ibcon#read 5, iclass 34, count 0 2006.257.14:32:06.96#ibcon#about to read 6, iclass 34, count 0 2006.257.14:32:06.96#ibcon#read 6, iclass 34, count 0 2006.257.14:32:06.96#ibcon#end of sib2, iclass 34, count 0 2006.257.14:32:06.96#ibcon#*after write, iclass 34, count 0 2006.257.14:32:06.96#ibcon#*before return 0, iclass 34, count 0 2006.257.14:32:06.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:06.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:06.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:32:06.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:32:06.96$vck44/va=6,4 2006.257.14:32:06.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.14:32:06.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.14:32:06.96#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:06.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:07.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:07.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:07.02#ibcon#enter wrdev, iclass 36, count 2 2006.257.14:32:07.02#ibcon#first serial, iclass 36, count 2 2006.257.14:32:07.02#ibcon#enter sib2, iclass 36, count 2 2006.257.14:32:07.02#ibcon#flushed, iclass 36, count 2 2006.257.14:32:07.02#ibcon#about to write, iclass 36, count 2 2006.257.14:32:07.02#ibcon#wrote, iclass 36, count 2 2006.257.14:32:07.02#ibcon#about to read 3, iclass 36, count 2 2006.257.14:32:07.04#ibcon#read 3, iclass 36, count 2 2006.257.14:32:07.04#ibcon#about to read 4, iclass 36, count 2 2006.257.14:32:07.04#ibcon#read 4, iclass 36, count 2 2006.257.14:32:07.04#ibcon#about to read 5, iclass 36, count 2 2006.257.14:32:07.04#ibcon#read 5, iclass 36, count 2 2006.257.14:32:07.04#ibcon#about to read 6, iclass 36, count 2 2006.257.14:32:07.04#ibcon#read 6, iclass 36, count 2 2006.257.14:32:07.04#ibcon#end of sib2, iclass 36, count 2 2006.257.14:32:07.04#ibcon#*mode == 0, iclass 36, count 2 2006.257.14:32:07.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.14:32:07.04#ibcon#[25=AT06-04\r\n] 2006.257.14:32:07.04#ibcon#*before write, iclass 36, count 2 2006.257.14:32:07.04#ibcon#enter sib2, iclass 36, count 2 2006.257.14:32:07.04#ibcon#flushed, iclass 36, count 2 2006.257.14:32:07.04#ibcon#about to write, iclass 36, count 2 2006.257.14:32:07.04#ibcon#wrote, iclass 36, count 2 2006.257.14:32:07.04#ibcon#about to read 3, iclass 36, count 2 2006.257.14:32:07.07#ibcon#read 3, iclass 36, count 2 2006.257.14:32:07.07#ibcon#about to read 4, iclass 36, count 2 2006.257.14:32:07.07#ibcon#read 4, iclass 36, count 2 2006.257.14:32:07.07#ibcon#about to read 5, iclass 36, count 2 2006.257.14:32:07.07#ibcon#read 5, iclass 36, count 2 2006.257.14:32:07.07#ibcon#about to read 6, iclass 36, count 2 2006.257.14:32:07.07#ibcon#read 6, iclass 36, count 2 2006.257.14:32:07.07#ibcon#end of sib2, iclass 36, count 2 2006.257.14:32:07.07#ibcon#*after write, iclass 36, count 2 2006.257.14:32:07.07#ibcon#*before return 0, iclass 36, count 2 2006.257.14:32:07.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:07.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:07.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.14:32:07.07#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:07.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:07.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:07.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:07.19#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:32:07.19#ibcon#first serial, iclass 36, count 0 2006.257.14:32:07.19#ibcon#enter sib2, iclass 36, count 0 2006.257.14:32:07.19#ibcon#flushed, iclass 36, count 0 2006.257.14:32:07.19#ibcon#about to write, iclass 36, count 0 2006.257.14:32:07.19#ibcon#wrote, iclass 36, count 0 2006.257.14:32:07.19#ibcon#about to read 3, iclass 36, count 0 2006.257.14:32:07.21#ibcon#read 3, iclass 36, count 0 2006.257.14:32:07.21#ibcon#about to read 4, iclass 36, count 0 2006.257.14:32:07.21#ibcon#read 4, iclass 36, count 0 2006.257.14:32:07.21#ibcon#about to read 5, iclass 36, count 0 2006.257.14:32:07.21#ibcon#read 5, iclass 36, count 0 2006.257.14:32:07.21#ibcon#about to read 6, iclass 36, count 0 2006.257.14:32:07.21#ibcon#read 6, iclass 36, count 0 2006.257.14:32:07.21#ibcon#end of sib2, iclass 36, count 0 2006.257.14:32:07.21#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:32:07.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:32:07.21#ibcon#[25=USB\r\n] 2006.257.14:32:07.21#ibcon#*before write, iclass 36, count 0 2006.257.14:32:07.21#ibcon#enter sib2, iclass 36, count 0 2006.257.14:32:07.21#ibcon#flushed, iclass 36, count 0 2006.257.14:32:07.21#ibcon#about to write, iclass 36, count 0 2006.257.14:32:07.21#ibcon#wrote, iclass 36, count 0 2006.257.14:32:07.21#ibcon#about to read 3, iclass 36, count 0 2006.257.14:32:07.24#ibcon#read 3, iclass 36, count 0 2006.257.14:32:07.24#ibcon#about to read 4, iclass 36, count 0 2006.257.14:32:07.24#ibcon#read 4, iclass 36, count 0 2006.257.14:32:07.24#ibcon#about to read 5, iclass 36, count 0 2006.257.14:32:07.24#ibcon#read 5, iclass 36, count 0 2006.257.14:32:07.24#ibcon#about to read 6, iclass 36, count 0 2006.257.14:32:07.24#ibcon#read 6, iclass 36, count 0 2006.257.14:32:07.24#ibcon#end of sib2, iclass 36, count 0 2006.257.14:32:07.24#ibcon#*after write, iclass 36, count 0 2006.257.14:32:07.24#ibcon#*before return 0, iclass 36, count 0 2006.257.14:32:07.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:07.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:07.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:32:07.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:32:07.24$vck44/valo=7,864.99 2006.257.14:32:07.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.14:32:07.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.14:32:07.24#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:07.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:07.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:07.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:07.24#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:32:07.24#ibcon#first serial, iclass 38, count 0 2006.257.14:32:07.24#ibcon#enter sib2, iclass 38, count 0 2006.257.14:32:07.24#ibcon#flushed, iclass 38, count 0 2006.257.14:32:07.24#ibcon#about to write, iclass 38, count 0 2006.257.14:32:07.24#ibcon#wrote, iclass 38, count 0 2006.257.14:32:07.24#ibcon#about to read 3, iclass 38, count 0 2006.257.14:32:07.26#ibcon#read 3, iclass 38, count 0 2006.257.14:32:07.26#ibcon#about to read 4, iclass 38, count 0 2006.257.14:32:07.26#ibcon#read 4, iclass 38, count 0 2006.257.14:32:07.26#ibcon#about to read 5, iclass 38, count 0 2006.257.14:32:07.26#ibcon#read 5, iclass 38, count 0 2006.257.14:32:07.26#ibcon#about to read 6, iclass 38, count 0 2006.257.14:32:07.26#ibcon#read 6, iclass 38, count 0 2006.257.14:32:07.26#ibcon#end of sib2, iclass 38, count 0 2006.257.14:32:07.26#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:32:07.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:32:07.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:32:07.26#ibcon#*before write, iclass 38, count 0 2006.257.14:32:07.26#ibcon#enter sib2, iclass 38, count 0 2006.257.14:32:07.26#ibcon#flushed, iclass 38, count 0 2006.257.14:32:07.26#ibcon#about to write, iclass 38, count 0 2006.257.14:32:07.26#ibcon#wrote, iclass 38, count 0 2006.257.14:32:07.26#ibcon#about to read 3, iclass 38, count 0 2006.257.14:32:07.30#ibcon#read 3, iclass 38, count 0 2006.257.14:32:07.30#ibcon#about to read 4, iclass 38, count 0 2006.257.14:32:07.30#ibcon#read 4, iclass 38, count 0 2006.257.14:32:07.30#ibcon#about to read 5, iclass 38, count 0 2006.257.14:32:07.30#ibcon#read 5, iclass 38, count 0 2006.257.14:32:07.30#ibcon#about to read 6, iclass 38, count 0 2006.257.14:32:07.30#ibcon#read 6, iclass 38, count 0 2006.257.14:32:07.30#ibcon#end of sib2, iclass 38, count 0 2006.257.14:32:07.30#ibcon#*after write, iclass 38, count 0 2006.257.14:32:07.30#ibcon#*before return 0, iclass 38, count 0 2006.257.14:32:07.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:07.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:07.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:32:07.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:32:07.30$vck44/va=7,4 2006.257.14:32:07.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.14:32:07.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.14:32:07.30#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:07.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:07.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:07.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:07.36#ibcon#enter wrdev, iclass 40, count 2 2006.257.14:32:07.36#ibcon#first serial, iclass 40, count 2 2006.257.14:32:07.36#ibcon#enter sib2, iclass 40, count 2 2006.257.14:32:07.36#ibcon#flushed, iclass 40, count 2 2006.257.14:32:07.36#ibcon#about to write, iclass 40, count 2 2006.257.14:32:07.36#ibcon#wrote, iclass 40, count 2 2006.257.14:32:07.36#ibcon#about to read 3, iclass 40, count 2 2006.257.14:32:07.38#ibcon#read 3, iclass 40, count 2 2006.257.14:32:07.38#ibcon#about to read 4, iclass 40, count 2 2006.257.14:32:07.38#ibcon#read 4, iclass 40, count 2 2006.257.14:32:07.38#ibcon#about to read 5, iclass 40, count 2 2006.257.14:32:07.38#ibcon#read 5, iclass 40, count 2 2006.257.14:32:07.38#ibcon#about to read 6, iclass 40, count 2 2006.257.14:32:07.38#ibcon#read 6, iclass 40, count 2 2006.257.14:32:07.38#ibcon#end of sib2, iclass 40, count 2 2006.257.14:32:07.38#ibcon#*mode == 0, iclass 40, count 2 2006.257.14:32:07.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.14:32:07.38#ibcon#[25=AT07-04\r\n] 2006.257.14:32:07.38#ibcon#*before write, iclass 40, count 2 2006.257.14:32:07.38#ibcon#enter sib2, iclass 40, count 2 2006.257.14:32:07.38#ibcon#flushed, iclass 40, count 2 2006.257.14:32:07.38#ibcon#about to write, iclass 40, count 2 2006.257.14:32:07.38#ibcon#wrote, iclass 40, count 2 2006.257.14:32:07.38#ibcon#about to read 3, iclass 40, count 2 2006.257.14:32:07.41#ibcon#read 3, iclass 40, count 2 2006.257.14:32:07.41#ibcon#about to read 4, iclass 40, count 2 2006.257.14:32:07.41#ibcon#read 4, iclass 40, count 2 2006.257.14:32:07.41#ibcon#about to read 5, iclass 40, count 2 2006.257.14:32:07.41#ibcon#read 5, iclass 40, count 2 2006.257.14:32:07.41#ibcon#about to read 6, iclass 40, count 2 2006.257.14:32:07.41#ibcon#read 6, iclass 40, count 2 2006.257.14:32:07.41#ibcon#end of sib2, iclass 40, count 2 2006.257.14:32:07.41#ibcon#*after write, iclass 40, count 2 2006.257.14:32:07.45#ibcon#*before return 0, iclass 40, count 2 2006.257.14:32:07.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:07.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:07.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.14:32:07.45#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:07.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:07.57#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:07.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:07.57#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:32:07.57#ibcon#first serial, iclass 40, count 0 2006.257.14:32:07.57#ibcon#enter sib2, iclass 40, count 0 2006.257.14:32:07.57#ibcon#flushed, iclass 40, count 0 2006.257.14:32:07.57#ibcon#about to write, iclass 40, count 0 2006.257.14:32:07.57#ibcon#wrote, iclass 40, count 0 2006.257.14:32:07.57#ibcon#about to read 3, iclass 40, count 0 2006.257.14:32:07.59#ibcon#read 3, iclass 40, count 0 2006.257.14:32:07.59#ibcon#about to read 4, iclass 40, count 0 2006.257.14:32:07.59#ibcon#read 4, iclass 40, count 0 2006.257.14:32:07.59#ibcon#about to read 5, iclass 40, count 0 2006.257.14:32:07.59#ibcon#read 5, iclass 40, count 0 2006.257.14:32:07.59#ibcon#about to read 6, iclass 40, count 0 2006.257.14:32:07.59#ibcon#read 6, iclass 40, count 0 2006.257.14:32:07.59#ibcon#end of sib2, iclass 40, count 0 2006.257.14:32:07.59#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:32:07.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:32:07.59#ibcon#[25=USB\r\n] 2006.257.14:32:07.59#ibcon#*before write, iclass 40, count 0 2006.257.14:32:07.59#ibcon#enter sib2, iclass 40, count 0 2006.257.14:32:07.59#ibcon#flushed, iclass 40, count 0 2006.257.14:32:07.59#ibcon#about to write, iclass 40, count 0 2006.257.14:32:07.59#ibcon#wrote, iclass 40, count 0 2006.257.14:32:07.59#ibcon#about to read 3, iclass 40, count 0 2006.257.14:32:07.62#ibcon#read 3, iclass 40, count 0 2006.257.14:32:07.62#ibcon#about to read 4, iclass 40, count 0 2006.257.14:32:07.62#ibcon#read 4, iclass 40, count 0 2006.257.14:32:07.62#ibcon#about to read 5, iclass 40, count 0 2006.257.14:32:07.62#ibcon#read 5, iclass 40, count 0 2006.257.14:32:07.62#ibcon#about to read 6, iclass 40, count 0 2006.257.14:32:07.62#ibcon#read 6, iclass 40, count 0 2006.257.14:32:07.62#ibcon#end of sib2, iclass 40, count 0 2006.257.14:32:07.62#ibcon#*after write, iclass 40, count 0 2006.257.14:32:07.62#ibcon#*before return 0, iclass 40, count 0 2006.257.14:32:07.62#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:07.62#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:07.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:32:07.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:32:07.62$vck44/valo=8,884.99 2006.257.14:32:07.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.14:32:07.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.14:32:07.62#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:07.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:07.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:07.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:07.62#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:32:07.62#ibcon#first serial, iclass 4, count 0 2006.257.14:32:07.62#ibcon#enter sib2, iclass 4, count 0 2006.257.14:32:07.62#ibcon#flushed, iclass 4, count 0 2006.257.14:32:07.62#ibcon#about to write, iclass 4, count 0 2006.257.14:32:07.62#ibcon#wrote, iclass 4, count 0 2006.257.14:32:07.62#ibcon#about to read 3, iclass 4, count 0 2006.257.14:32:07.64#ibcon#read 3, iclass 4, count 0 2006.257.14:32:07.64#ibcon#about to read 4, iclass 4, count 0 2006.257.14:32:07.64#ibcon#read 4, iclass 4, count 0 2006.257.14:32:07.64#ibcon#about to read 5, iclass 4, count 0 2006.257.14:32:07.64#ibcon#read 5, iclass 4, count 0 2006.257.14:32:07.64#ibcon#about to read 6, iclass 4, count 0 2006.257.14:32:07.64#ibcon#read 6, iclass 4, count 0 2006.257.14:32:07.64#ibcon#end of sib2, iclass 4, count 0 2006.257.14:32:07.64#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:32:07.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:32:07.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:32:07.64#ibcon#*before write, iclass 4, count 0 2006.257.14:32:07.64#ibcon#enter sib2, iclass 4, count 0 2006.257.14:32:07.64#ibcon#flushed, iclass 4, count 0 2006.257.14:32:07.64#ibcon#about to write, iclass 4, count 0 2006.257.14:32:07.64#ibcon#wrote, iclass 4, count 0 2006.257.14:32:07.64#ibcon#about to read 3, iclass 4, count 0 2006.257.14:32:07.68#ibcon#read 3, iclass 4, count 0 2006.257.14:32:07.68#ibcon#about to read 4, iclass 4, count 0 2006.257.14:32:07.68#ibcon#read 4, iclass 4, count 0 2006.257.14:32:07.68#ibcon#about to read 5, iclass 4, count 0 2006.257.14:32:07.68#ibcon#read 5, iclass 4, count 0 2006.257.14:32:07.68#ibcon#about to read 6, iclass 4, count 0 2006.257.14:32:07.68#ibcon#read 6, iclass 4, count 0 2006.257.14:32:07.68#ibcon#end of sib2, iclass 4, count 0 2006.257.14:32:07.68#ibcon#*after write, iclass 4, count 0 2006.257.14:32:07.68#ibcon#*before return 0, iclass 4, count 0 2006.257.14:32:07.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:07.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:07.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:32:07.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:32:07.68$vck44/va=8,4 2006.257.14:32:07.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.14:32:07.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.14:32:07.68#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:07.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:32:07.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:32:07.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:32:07.74#ibcon#enter wrdev, iclass 6, count 2 2006.257.14:32:07.74#ibcon#first serial, iclass 6, count 2 2006.257.14:32:07.74#ibcon#enter sib2, iclass 6, count 2 2006.257.14:32:07.74#ibcon#flushed, iclass 6, count 2 2006.257.14:32:07.74#ibcon#about to write, iclass 6, count 2 2006.257.14:32:07.74#ibcon#wrote, iclass 6, count 2 2006.257.14:32:07.74#ibcon#about to read 3, iclass 6, count 2 2006.257.14:32:07.76#ibcon#read 3, iclass 6, count 2 2006.257.14:32:07.76#ibcon#about to read 4, iclass 6, count 2 2006.257.14:32:07.76#ibcon#read 4, iclass 6, count 2 2006.257.14:32:07.76#ibcon#about to read 5, iclass 6, count 2 2006.257.14:32:07.76#ibcon#read 5, iclass 6, count 2 2006.257.14:32:07.76#ibcon#about to read 6, iclass 6, count 2 2006.257.14:32:07.76#ibcon#read 6, iclass 6, count 2 2006.257.14:32:07.76#ibcon#end of sib2, iclass 6, count 2 2006.257.14:32:07.76#ibcon#*mode == 0, iclass 6, count 2 2006.257.14:32:07.76#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.14:32:07.76#ibcon#[25=AT08-04\r\n] 2006.257.14:32:07.76#ibcon#*before write, iclass 6, count 2 2006.257.14:32:07.76#ibcon#enter sib2, iclass 6, count 2 2006.257.14:32:07.76#ibcon#flushed, iclass 6, count 2 2006.257.14:32:07.76#ibcon#about to write, iclass 6, count 2 2006.257.14:32:07.76#ibcon#wrote, iclass 6, count 2 2006.257.14:32:07.76#ibcon#about to read 3, iclass 6, count 2 2006.257.14:32:07.79#ibcon#read 3, iclass 6, count 2 2006.257.14:32:07.79#ibcon#about to read 4, iclass 6, count 2 2006.257.14:32:07.79#ibcon#read 4, iclass 6, count 2 2006.257.14:32:07.79#ibcon#about to read 5, iclass 6, count 2 2006.257.14:32:07.79#ibcon#read 5, iclass 6, count 2 2006.257.14:32:07.79#ibcon#about to read 6, iclass 6, count 2 2006.257.14:32:07.79#ibcon#read 6, iclass 6, count 2 2006.257.14:32:07.79#ibcon#end of sib2, iclass 6, count 2 2006.257.14:32:07.79#ibcon#*after write, iclass 6, count 2 2006.257.14:32:07.79#ibcon#*before return 0, iclass 6, count 2 2006.257.14:32:07.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:32:07.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:32:07.79#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.14:32:07.79#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:07.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:32:07.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:32:07.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:32:07.91#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:32:07.91#ibcon#first serial, iclass 6, count 0 2006.257.14:32:07.91#ibcon#enter sib2, iclass 6, count 0 2006.257.14:32:07.91#ibcon#flushed, iclass 6, count 0 2006.257.14:32:07.91#ibcon#about to write, iclass 6, count 0 2006.257.14:32:07.91#ibcon#wrote, iclass 6, count 0 2006.257.14:32:07.91#ibcon#about to read 3, iclass 6, count 0 2006.257.14:32:07.93#ibcon#read 3, iclass 6, count 0 2006.257.14:32:07.93#ibcon#about to read 4, iclass 6, count 0 2006.257.14:32:07.93#ibcon#read 4, iclass 6, count 0 2006.257.14:32:07.93#ibcon#about to read 5, iclass 6, count 0 2006.257.14:32:07.93#ibcon#read 5, iclass 6, count 0 2006.257.14:32:07.93#ibcon#about to read 6, iclass 6, count 0 2006.257.14:32:07.93#ibcon#read 6, iclass 6, count 0 2006.257.14:32:07.93#ibcon#end of sib2, iclass 6, count 0 2006.257.14:32:07.93#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:32:07.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:32:07.93#ibcon#[25=USB\r\n] 2006.257.14:32:07.93#ibcon#*before write, iclass 6, count 0 2006.257.14:32:07.93#ibcon#enter sib2, iclass 6, count 0 2006.257.14:32:07.93#ibcon#flushed, iclass 6, count 0 2006.257.14:32:07.93#ibcon#about to write, iclass 6, count 0 2006.257.14:32:07.93#ibcon#wrote, iclass 6, count 0 2006.257.14:32:07.93#ibcon#about to read 3, iclass 6, count 0 2006.257.14:32:07.96#ibcon#read 3, iclass 6, count 0 2006.257.14:32:07.96#ibcon#about to read 4, iclass 6, count 0 2006.257.14:32:07.96#ibcon#read 4, iclass 6, count 0 2006.257.14:32:07.96#ibcon#about to read 5, iclass 6, count 0 2006.257.14:32:07.96#ibcon#read 5, iclass 6, count 0 2006.257.14:32:07.96#ibcon#about to read 6, iclass 6, count 0 2006.257.14:32:07.96#ibcon#read 6, iclass 6, count 0 2006.257.14:32:07.96#ibcon#end of sib2, iclass 6, count 0 2006.257.14:32:07.96#ibcon#*after write, iclass 6, count 0 2006.257.14:32:07.96#ibcon#*before return 0, iclass 6, count 0 2006.257.14:32:07.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:32:07.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:32:07.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:32:07.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:32:07.96$vck44/vblo=1,629.99 2006.257.14:32:07.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.14:32:07.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.14:32:07.96#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:07.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:32:07.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:32:07.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:32:07.96#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:32:07.96#ibcon#first serial, iclass 10, count 0 2006.257.14:32:07.96#ibcon#enter sib2, iclass 10, count 0 2006.257.14:32:07.96#ibcon#flushed, iclass 10, count 0 2006.257.14:32:07.96#ibcon#about to write, iclass 10, count 0 2006.257.14:32:07.96#ibcon#wrote, iclass 10, count 0 2006.257.14:32:07.96#ibcon#about to read 3, iclass 10, count 0 2006.257.14:32:07.98#ibcon#read 3, iclass 10, count 0 2006.257.14:32:07.98#ibcon#about to read 4, iclass 10, count 0 2006.257.14:32:07.98#ibcon#read 4, iclass 10, count 0 2006.257.14:32:07.98#ibcon#about to read 5, iclass 10, count 0 2006.257.14:32:07.98#ibcon#read 5, iclass 10, count 0 2006.257.14:32:07.98#ibcon#about to read 6, iclass 10, count 0 2006.257.14:32:07.98#ibcon#read 6, iclass 10, count 0 2006.257.14:32:07.98#ibcon#end of sib2, iclass 10, count 0 2006.257.14:32:07.98#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:32:07.98#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:32:07.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:32:07.98#ibcon#*before write, iclass 10, count 0 2006.257.14:32:07.98#ibcon#enter sib2, iclass 10, count 0 2006.257.14:32:07.98#ibcon#flushed, iclass 10, count 0 2006.257.14:32:07.98#ibcon#about to write, iclass 10, count 0 2006.257.14:32:07.98#ibcon#wrote, iclass 10, count 0 2006.257.14:32:07.98#ibcon#about to read 3, iclass 10, count 0 2006.257.14:32:08.02#ibcon#read 3, iclass 10, count 0 2006.257.14:32:08.02#ibcon#about to read 4, iclass 10, count 0 2006.257.14:32:08.02#ibcon#read 4, iclass 10, count 0 2006.257.14:32:08.02#ibcon#about to read 5, iclass 10, count 0 2006.257.14:32:08.02#ibcon#read 5, iclass 10, count 0 2006.257.14:32:08.02#ibcon#about to read 6, iclass 10, count 0 2006.257.14:32:08.02#ibcon#read 6, iclass 10, count 0 2006.257.14:32:08.02#ibcon#end of sib2, iclass 10, count 0 2006.257.14:32:08.02#ibcon#*after write, iclass 10, count 0 2006.257.14:32:08.02#ibcon#*before return 0, iclass 10, count 0 2006.257.14:32:08.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:32:08.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:32:08.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:32:08.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:32:08.02$vck44/vb=1,4 2006.257.14:32:08.02#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.14:32:08.02#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.14:32:08.02#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:08.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:32:08.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:32:08.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:32:08.02#ibcon#enter wrdev, iclass 12, count 2 2006.257.14:32:08.02#ibcon#first serial, iclass 12, count 2 2006.257.14:32:08.02#ibcon#enter sib2, iclass 12, count 2 2006.257.14:32:08.02#ibcon#flushed, iclass 12, count 2 2006.257.14:32:08.02#ibcon#about to write, iclass 12, count 2 2006.257.14:32:08.02#ibcon#wrote, iclass 12, count 2 2006.257.14:32:08.02#ibcon#about to read 3, iclass 12, count 2 2006.257.14:32:08.04#ibcon#read 3, iclass 12, count 2 2006.257.14:32:08.04#ibcon#about to read 4, iclass 12, count 2 2006.257.14:32:08.04#ibcon#read 4, iclass 12, count 2 2006.257.14:32:08.04#ibcon#about to read 5, iclass 12, count 2 2006.257.14:32:08.04#ibcon#read 5, iclass 12, count 2 2006.257.14:32:08.04#ibcon#about to read 6, iclass 12, count 2 2006.257.14:32:08.04#ibcon#read 6, iclass 12, count 2 2006.257.14:32:08.04#ibcon#end of sib2, iclass 12, count 2 2006.257.14:32:08.04#ibcon#*mode == 0, iclass 12, count 2 2006.257.14:32:08.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.14:32:08.04#ibcon#[27=AT01-04\r\n] 2006.257.14:32:08.04#ibcon#*before write, iclass 12, count 2 2006.257.14:32:08.04#ibcon#enter sib2, iclass 12, count 2 2006.257.14:32:08.04#ibcon#flushed, iclass 12, count 2 2006.257.14:32:08.04#ibcon#about to write, iclass 12, count 2 2006.257.14:32:08.04#ibcon#wrote, iclass 12, count 2 2006.257.14:32:08.04#ibcon#about to read 3, iclass 12, count 2 2006.257.14:32:08.07#ibcon#read 3, iclass 12, count 2 2006.257.14:32:08.07#ibcon#about to read 4, iclass 12, count 2 2006.257.14:32:08.07#ibcon#read 4, iclass 12, count 2 2006.257.14:32:08.07#ibcon#about to read 5, iclass 12, count 2 2006.257.14:32:08.07#ibcon#read 5, iclass 12, count 2 2006.257.14:32:08.07#ibcon#about to read 6, iclass 12, count 2 2006.257.14:32:08.07#ibcon#read 6, iclass 12, count 2 2006.257.14:32:08.07#ibcon#end of sib2, iclass 12, count 2 2006.257.14:32:08.07#ibcon#*after write, iclass 12, count 2 2006.257.14:32:08.07#ibcon#*before return 0, iclass 12, count 2 2006.257.14:32:08.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:32:08.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:32:08.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.14:32:08.07#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:08.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:32:08.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:32:08.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:32:08.19#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:32:08.19#ibcon#first serial, iclass 12, count 0 2006.257.14:32:08.19#ibcon#enter sib2, iclass 12, count 0 2006.257.14:32:08.19#ibcon#flushed, iclass 12, count 0 2006.257.14:32:08.19#ibcon#about to write, iclass 12, count 0 2006.257.14:32:08.19#ibcon#wrote, iclass 12, count 0 2006.257.14:32:08.19#ibcon#about to read 3, iclass 12, count 0 2006.257.14:32:08.21#ibcon#read 3, iclass 12, count 0 2006.257.14:32:08.21#ibcon#about to read 4, iclass 12, count 0 2006.257.14:32:08.21#ibcon#read 4, iclass 12, count 0 2006.257.14:32:08.21#ibcon#about to read 5, iclass 12, count 0 2006.257.14:32:08.21#ibcon#read 5, iclass 12, count 0 2006.257.14:32:08.21#ibcon#about to read 6, iclass 12, count 0 2006.257.14:32:08.21#ibcon#read 6, iclass 12, count 0 2006.257.14:32:08.21#ibcon#end of sib2, iclass 12, count 0 2006.257.14:32:08.21#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:32:08.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:32:08.21#ibcon#[27=USB\r\n] 2006.257.14:32:08.21#ibcon#*before write, iclass 12, count 0 2006.257.14:32:08.21#ibcon#enter sib2, iclass 12, count 0 2006.257.14:32:08.21#ibcon#flushed, iclass 12, count 0 2006.257.14:32:08.21#ibcon#about to write, iclass 12, count 0 2006.257.14:32:08.21#ibcon#wrote, iclass 12, count 0 2006.257.14:32:08.21#ibcon#about to read 3, iclass 12, count 0 2006.257.14:32:08.24#ibcon#read 3, iclass 12, count 0 2006.257.14:32:08.24#ibcon#about to read 4, iclass 12, count 0 2006.257.14:32:08.24#ibcon#read 4, iclass 12, count 0 2006.257.14:32:08.24#ibcon#about to read 5, iclass 12, count 0 2006.257.14:32:08.24#ibcon#read 5, iclass 12, count 0 2006.257.14:32:08.24#ibcon#about to read 6, iclass 12, count 0 2006.257.14:32:08.24#ibcon#read 6, iclass 12, count 0 2006.257.14:32:08.24#ibcon#end of sib2, iclass 12, count 0 2006.257.14:32:08.24#ibcon#*after write, iclass 12, count 0 2006.257.14:32:08.24#ibcon#*before return 0, iclass 12, count 0 2006.257.14:32:08.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:32:08.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:32:08.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:32:08.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:32:08.24$vck44/vblo=2,634.99 2006.257.14:32:08.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.14:32:08.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.14:32:08.24#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:08.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:08.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:08.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:08.24#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:32:08.24#ibcon#first serial, iclass 14, count 0 2006.257.14:32:08.24#ibcon#enter sib2, iclass 14, count 0 2006.257.14:32:08.24#ibcon#flushed, iclass 14, count 0 2006.257.14:32:08.24#ibcon#about to write, iclass 14, count 0 2006.257.14:32:08.24#ibcon#wrote, iclass 14, count 0 2006.257.14:32:08.24#ibcon#about to read 3, iclass 14, count 0 2006.257.14:32:08.26#ibcon#read 3, iclass 14, count 0 2006.257.14:32:08.26#ibcon#about to read 4, iclass 14, count 0 2006.257.14:32:08.26#ibcon#read 4, iclass 14, count 0 2006.257.14:32:08.26#ibcon#about to read 5, iclass 14, count 0 2006.257.14:32:08.26#ibcon#read 5, iclass 14, count 0 2006.257.14:32:08.26#ibcon#about to read 6, iclass 14, count 0 2006.257.14:32:08.26#ibcon#read 6, iclass 14, count 0 2006.257.14:32:08.26#ibcon#end of sib2, iclass 14, count 0 2006.257.14:32:08.26#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:32:08.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:32:08.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:32:08.26#ibcon#*before write, iclass 14, count 0 2006.257.14:32:08.26#ibcon#enter sib2, iclass 14, count 0 2006.257.14:32:08.26#ibcon#flushed, iclass 14, count 0 2006.257.14:32:08.26#ibcon#about to write, iclass 14, count 0 2006.257.14:32:08.26#ibcon#wrote, iclass 14, count 0 2006.257.14:32:08.26#ibcon#about to read 3, iclass 14, count 0 2006.257.14:32:08.30#ibcon#read 3, iclass 14, count 0 2006.257.14:32:08.30#ibcon#about to read 4, iclass 14, count 0 2006.257.14:32:08.30#ibcon#read 4, iclass 14, count 0 2006.257.14:32:08.30#ibcon#about to read 5, iclass 14, count 0 2006.257.14:32:08.30#ibcon#read 5, iclass 14, count 0 2006.257.14:32:08.30#ibcon#about to read 6, iclass 14, count 0 2006.257.14:32:08.30#ibcon#read 6, iclass 14, count 0 2006.257.14:32:08.30#ibcon#end of sib2, iclass 14, count 0 2006.257.14:32:08.30#ibcon#*after write, iclass 14, count 0 2006.257.14:32:08.30#ibcon#*before return 0, iclass 14, count 0 2006.257.14:32:08.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:08.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:32:08.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:32:08.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:32:08.30$vck44/vb=2,5 2006.257.14:32:08.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.14:32:08.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.14:32:08.30#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:08.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:08.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:08.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:08.36#ibcon#enter wrdev, iclass 16, count 2 2006.257.14:32:08.36#ibcon#first serial, iclass 16, count 2 2006.257.14:32:08.36#ibcon#enter sib2, iclass 16, count 2 2006.257.14:32:08.36#ibcon#flushed, iclass 16, count 2 2006.257.14:32:08.36#ibcon#about to write, iclass 16, count 2 2006.257.14:32:08.36#ibcon#wrote, iclass 16, count 2 2006.257.14:32:08.36#ibcon#about to read 3, iclass 16, count 2 2006.257.14:32:08.38#ibcon#read 3, iclass 16, count 2 2006.257.14:32:08.38#ibcon#about to read 4, iclass 16, count 2 2006.257.14:32:08.38#ibcon#read 4, iclass 16, count 2 2006.257.14:32:08.38#ibcon#about to read 5, iclass 16, count 2 2006.257.14:32:08.38#ibcon#read 5, iclass 16, count 2 2006.257.14:32:08.38#ibcon#about to read 6, iclass 16, count 2 2006.257.14:32:08.38#ibcon#read 6, iclass 16, count 2 2006.257.14:32:08.38#ibcon#end of sib2, iclass 16, count 2 2006.257.14:32:08.38#ibcon#*mode == 0, iclass 16, count 2 2006.257.14:32:08.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.14:32:08.38#ibcon#[27=AT02-05\r\n] 2006.257.14:32:08.38#ibcon#*before write, iclass 16, count 2 2006.257.14:32:08.38#ibcon#enter sib2, iclass 16, count 2 2006.257.14:32:08.38#ibcon#flushed, iclass 16, count 2 2006.257.14:32:08.38#ibcon#about to write, iclass 16, count 2 2006.257.14:32:08.38#ibcon#wrote, iclass 16, count 2 2006.257.14:32:08.38#ibcon#about to read 3, iclass 16, count 2 2006.257.14:32:08.41#ibcon#read 3, iclass 16, count 2 2006.257.14:32:08.41#ibcon#about to read 4, iclass 16, count 2 2006.257.14:32:08.41#ibcon#read 4, iclass 16, count 2 2006.257.14:32:08.41#ibcon#about to read 5, iclass 16, count 2 2006.257.14:32:08.41#ibcon#read 5, iclass 16, count 2 2006.257.14:32:08.41#ibcon#about to read 6, iclass 16, count 2 2006.257.14:32:08.41#ibcon#read 6, iclass 16, count 2 2006.257.14:32:08.41#ibcon#end of sib2, iclass 16, count 2 2006.257.14:32:08.41#ibcon#*after write, iclass 16, count 2 2006.257.14:32:08.41#ibcon#*before return 0, iclass 16, count 2 2006.257.14:32:08.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:08.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:32:08.55#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.14:32:08.55#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:08.55#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:08.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:08.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:08.66#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:32:08.66#ibcon#first serial, iclass 16, count 0 2006.257.14:32:08.66#ibcon#enter sib2, iclass 16, count 0 2006.257.14:32:08.66#ibcon#flushed, iclass 16, count 0 2006.257.14:32:08.66#ibcon#about to write, iclass 16, count 0 2006.257.14:32:08.66#ibcon#wrote, iclass 16, count 0 2006.257.14:32:08.66#ibcon#about to read 3, iclass 16, count 0 2006.257.14:32:08.68#ibcon#read 3, iclass 16, count 0 2006.257.14:32:08.68#ibcon#about to read 4, iclass 16, count 0 2006.257.14:32:08.68#ibcon#read 4, iclass 16, count 0 2006.257.14:32:08.68#ibcon#about to read 5, iclass 16, count 0 2006.257.14:32:08.68#ibcon#read 5, iclass 16, count 0 2006.257.14:32:08.68#ibcon#about to read 6, iclass 16, count 0 2006.257.14:32:08.68#ibcon#read 6, iclass 16, count 0 2006.257.14:32:08.68#ibcon#end of sib2, iclass 16, count 0 2006.257.14:32:08.68#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:32:08.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:32:08.68#ibcon#[27=USB\r\n] 2006.257.14:32:08.68#ibcon#*before write, iclass 16, count 0 2006.257.14:32:08.68#ibcon#enter sib2, iclass 16, count 0 2006.257.14:32:08.68#ibcon#flushed, iclass 16, count 0 2006.257.14:32:08.68#ibcon#about to write, iclass 16, count 0 2006.257.14:32:08.68#ibcon#wrote, iclass 16, count 0 2006.257.14:32:08.68#ibcon#about to read 3, iclass 16, count 0 2006.257.14:32:08.71#ibcon#read 3, iclass 16, count 0 2006.257.14:32:08.71#ibcon#about to read 4, iclass 16, count 0 2006.257.14:32:08.71#ibcon#read 4, iclass 16, count 0 2006.257.14:32:08.71#ibcon#about to read 5, iclass 16, count 0 2006.257.14:32:08.71#ibcon#read 5, iclass 16, count 0 2006.257.14:32:08.71#ibcon#about to read 6, iclass 16, count 0 2006.257.14:32:08.71#ibcon#read 6, iclass 16, count 0 2006.257.14:32:08.71#ibcon#end of sib2, iclass 16, count 0 2006.257.14:32:08.71#ibcon#*after write, iclass 16, count 0 2006.257.14:32:08.71#ibcon#*before return 0, iclass 16, count 0 2006.257.14:32:08.71#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:08.71#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:32:08.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:32:08.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:32:08.71$vck44/vblo=3,649.99 2006.257.14:32:08.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.14:32:08.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.14:32:08.71#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:08.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:08.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:08.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:08.71#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:32:08.71#ibcon#first serial, iclass 18, count 0 2006.257.14:32:08.71#ibcon#enter sib2, iclass 18, count 0 2006.257.14:32:08.71#ibcon#flushed, iclass 18, count 0 2006.257.14:32:08.71#ibcon#about to write, iclass 18, count 0 2006.257.14:32:08.71#ibcon#wrote, iclass 18, count 0 2006.257.14:32:08.71#ibcon#about to read 3, iclass 18, count 0 2006.257.14:32:08.73#ibcon#read 3, iclass 18, count 0 2006.257.14:32:08.73#ibcon#about to read 4, iclass 18, count 0 2006.257.14:32:08.73#ibcon#read 4, iclass 18, count 0 2006.257.14:32:08.73#ibcon#about to read 5, iclass 18, count 0 2006.257.14:32:08.73#ibcon#read 5, iclass 18, count 0 2006.257.14:32:08.73#ibcon#about to read 6, iclass 18, count 0 2006.257.14:32:08.73#ibcon#read 6, iclass 18, count 0 2006.257.14:32:08.73#ibcon#end of sib2, iclass 18, count 0 2006.257.14:32:08.73#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:32:08.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:32:08.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:32:08.73#ibcon#*before write, iclass 18, count 0 2006.257.14:32:08.73#ibcon#enter sib2, iclass 18, count 0 2006.257.14:32:08.73#ibcon#flushed, iclass 18, count 0 2006.257.14:32:08.73#ibcon#about to write, iclass 18, count 0 2006.257.14:32:08.73#ibcon#wrote, iclass 18, count 0 2006.257.14:32:08.73#ibcon#about to read 3, iclass 18, count 0 2006.257.14:32:08.77#ibcon#read 3, iclass 18, count 0 2006.257.14:32:08.77#ibcon#about to read 4, iclass 18, count 0 2006.257.14:32:08.77#ibcon#read 4, iclass 18, count 0 2006.257.14:32:08.77#ibcon#about to read 5, iclass 18, count 0 2006.257.14:32:08.77#ibcon#read 5, iclass 18, count 0 2006.257.14:32:08.77#ibcon#about to read 6, iclass 18, count 0 2006.257.14:32:08.77#ibcon#read 6, iclass 18, count 0 2006.257.14:32:08.77#ibcon#end of sib2, iclass 18, count 0 2006.257.14:32:08.77#ibcon#*after write, iclass 18, count 0 2006.257.14:32:08.77#ibcon#*before return 0, iclass 18, count 0 2006.257.14:32:08.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:08.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:32:08.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:32:08.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:32:08.77$vck44/vb=3,4 2006.257.14:32:08.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.14:32:08.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.14:32:08.77#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:08.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:08.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:08.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:08.83#ibcon#enter wrdev, iclass 20, count 2 2006.257.14:32:08.83#ibcon#first serial, iclass 20, count 2 2006.257.14:32:08.83#ibcon#enter sib2, iclass 20, count 2 2006.257.14:32:08.83#ibcon#flushed, iclass 20, count 2 2006.257.14:32:08.83#ibcon#about to write, iclass 20, count 2 2006.257.14:32:08.83#ibcon#wrote, iclass 20, count 2 2006.257.14:32:08.83#ibcon#about to read 3, iclass 20, count 2 2006.257.14:32:08.85#ibcon#read 3, iclass 20, count 2 2006.257.14:32:08.85#ibcon#about to read 4, iclass 20, count 2 2006.257.14:32:08.85#ibcon#read 4, iclass 20, count 2 2006.257.14:32:08.85#ibcon#about to read 5, iclass 20, count 2 2006.257.14:32:08.85#ibcon#read 5, iclass 20, count 2 2006.257.14:32:08.85#ibcon#about to read 6, iclass 20, count 2 2006.257.14:32:08.85#ibcon#read 6, iclass 20, count 2 2006.257.14:32:08.85#ibcon#end of sib2, iclass 20, count 2 2006.257.14:32:08.85#ibcon#*mode == 0, iclass 20, count 2 2006.257.14:32:08.85#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.14:32:08.85#ibcon#[27=AT03-04\r\n] 2006.257.14:32:08.85#ibcon#*before write, iclass 20, count 2 2006.257.14:32:08.85#ibcon#enter sib2, iclass 20, count 2 2006.257.14:32:08.85#ibcon#flushed, iclass 20, count 2 2006.257.14:32:08.85#ibcon#about to write, iclass 20, count 2 2006.257.14:32:08.85#ibcon#wrote, iclass 20, count 2 2006.257.14:32:08.85#ibcon#about to read 3, iclass 20, count 2 2006.257.14:32:08.88#ibcon#read 3, iclass 20, count 2 2006.257.14:32:08.88#ibcon#about to read 4, iclass 20, count 2 2006.257.14:32:08.88#ibcon#read 4, iclass 20, count 2 2006.257.14:32:08.88#ibcon#about to read 5, iclass 20, count 2 2006.257.14:32:08.88#ibcon#read 5, iclass 20, count 2 2006.257.14:32:08.88#ibcon#about to read 6, iclass 20, count 2 2006.257.14:32:08.88#ibcon#read 6, iclass 20, count 2 2006.257.14:32:08.88#ibcon#end of sib2, iclass 20, count 2 2006.257.14:32:08.88#ibcon#*after write, iclass 20, count 2 2006.257.14:32:08.88#ibcon#*before return 0, iclass 20, count 2 2006.257.14:32:08.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:08.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:32:08.88#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.14:32:08.88#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:08.88#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:09.00#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:09.00#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:09.00#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:32:09.00#ibcon#first serial, iclass 20, count 0 2006.257.14:32:09.00#ibcon#enter sib2, iclass 20, count 0 2006.257.14:32:09.00#ibcon#flushed, iclass 20, count 0 2006.257.14:32:09.00#ibcon#about to write, iclass 20, count 0 2006.257.14:32:09.00#ibcon#wrote, iclass 20, count 0 2006.257.14:32:09.00#ibcon#about to read 3, iclass 20, count 0 2006.257.14:32:09.02#ibcon#read 3, iclass 20, count 0 2006.257.14:32:09.02#ibcon#about to read 4, iclass 20, count 0 2006.257.14:32:09.02#ibcon#read 4, iclass 20, count 0 2006.257.14:32:09.02#ibcon#about to read 5, iclass 20, count 0 2006.257.14:32:09.02#ibcon#read 5, iclass 20, count 0 2006.257.14:32:09.02#ibcon#about to read 6, iclass 20, count 0 2006.257.14:32:09.02#ibcon#read 6, iclass 20, count 0 2006.257.14:32:09.02#ibcon#end of sib2, iclass 20, count 0 2006.257.14:32:09.02#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:32:09.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:32:09.02#ibcon#[27=USB\r\n] 2006.257.14:32:09.02#ibcon#*before write, iclass 20, count 0 2006.257.14:32:09.02#ibcon#enter sib2, iclass 20, count 0 2006.257.14:32:09.02#ibcon#flushed, iclass 20, count 0 2006.257.14:32:09.02#ibcon#about to write, iclass 20, count 0 2006.257.14:32:09.02#ibcon#wrote, iclass 20, count 0 2006.257.14:32:09.02#ibcon#about to read 3, iclass 20, count 0 2006.257.14:32:09.05#ibcon#read 3, iclass 20, count 0 2006.257.14:32:09.05#ibcon#about to read 4, iclass 20, count 0 2006.257.14:32:09.05#ibcon#read 4, iclass 20, count 0 2006.257.14:32:09.05#ibcon#about to read 5, iclass 20, count 0 2006.257.14:32:09.05#ibcon#read 5, iclass 20, count 0 2006.257.14:32:09.05#ibcon#about to read 6, iclass 20, count 0 2006.257.14:32:09.05#ibcon#read 6, iclass 20, count 0 2006.257.14:32:09.05#ibcon#end of sib2, iclass 20, count 0 2006.257.14:32:09.05#ibcon#*after write, iclass 20, count 0 2006.257.14:32:09.05#ibcon#*before return 0, iclass 20, count 0 2006.257.14:32:09.05#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:09.05#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:32:09.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:32:09.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:32:09.05$vck44/vblo=4,679.99 2006.257.14:32:09.05#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.14:32:09.05#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.14:32:09.05#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:09.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:09.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:09.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:09.05#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:32:09.05#ibcon#first serial, iclass 22, count 0 2006.257.14:32:09.05#ibcon#enter sib2, iclass 22, count 0 2006.257.14:32:09.05#ibcon#flushed, iclass 22, count 0 2006.257.14:32:09.05#ibcon#about to write, iclass 22, count 0 2006.257.14:32:09.05#ibcon#wrote, iclass 22, count 0 2006.257.14:32:09.05#ibcon#about to read 3, iclass 22, count 0 2006.257.14:32:09.07#ibcon#read 3, iclass 22, count 0 2006.257.14:32:09.07#ibcon#about to read 4, iclass 22, count 0 2006.257.14:32:09.07#ibcon#read 4, iclass 22, count 0 2006.257.14:32:09.07#ibcon#about to read 5, iclass 22, count 0 2006.257.14:32:09.07#ibcon#read 5, iclass 22, count 0 2006.257.14:32:09.07#ibcon#about to read 6, iclass 22, count 0 2006.257.14:32:09.07#ibcon#read 6, iclass 22, count 0 2006.257.14:32:09.07#ibcon#end of sib2, iclass 22, count 0 2006.257.14:32:09.07#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:32:09.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:32:09.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:32:09.07#ibcon#*before write, iclass 22, count 0 2006.257.14:32:09.07#ibcon#enter sib2, iclass 22, count 0 2006.257.14:32:09.07#ibcon#flushed, iclass 22, count 0 2006.257.14:32:09.07#ibcon#about to write, iclass 22, count 0 2006.257.14:32:09.07#ibcon#wrote, iclass 22, count 0 2006.257.14:32:09.07#ibcon#about to read 3, iclass 22, count 0 2006.257.14:32:09.11#ibcon#read 3, iclass 22, count 0 2006.257.14:32:09.11#ibcon#about to read 4, iclass 22, count 0 2006.257.14:32:09.11#ibcon#read 4, iclass 22, count 0 2006.257.14:32:09.11#ibcon#about to read 5, iclass 22, count 0 2006.257.14:32:09.11#ibcon#read 5, iclass 22, count 0 2006.257.14:32:09.11#ibcon#about to read 6, iclass 22, count 0 2006.257.14:32:09.11#ibcon#read 6, iclass 22, count 0 2006.257.14:32:09.11#ibcon#end of sib2, iclass 22, count 0 2006.257.14:32:09.11#ibcon#*after write, iclass 22, count 0 2006.257.14:32:09.11#ibcon#*before return 0, iclass 22, count 0 2006.257.14:32:09.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:09.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:32:09.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:32:09.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:32:09.11$vck44/vb=4,5 2006.257.14:32:09.11#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.14:32:09.11#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.14:32:09.11#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:09.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:09.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:09.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:09.17#ibcon#enter wrdev, iclass 24, count 2 2006.257.14:32:09.17#ibcon#first serial, iclass 24, count 2 2006.257.14:32:09.17#ibcon#enter sib2, iclass 24, count 2 2006.257.14:32:09.17#ibcon#flushed, iclass 24, count 2 2006.257.14:32:09.17#ibcon#about to write, iclass 24, count 2 2006.257.14:32:09.17#ibcon#wrote, iclass 24, count 2 2006.257.14:32:09.17#ibcon#about to read 3, iclass 24, count 2 2006.257.14:32:09.19#ibcon#read 3, iclass 24, count 2 2006.257.14:32:09.19#ibcon#about to read 4, iclass 24, count 2 2006.257.14:32:09.19#ibcon#read 4, iclass 24, count 2 2006.257.14:32:09.19#ibcon#about to read 5, iclass 24, count 2 2006.257.14:32:09.19#ibcon#read 5, iclass 24, count 2 2006.257.14:32:09.19#ibcon#about to read 6, iclass 24, count 2 2006.257.14:32:09.19#ibcon#read 6, iclass 24, count 2 2006.257.14:32:09.19#ibcon#end of sib2, iclass 24, count 2 2006.257.14:32:09.19#ibcon#*mode == 0, iclass 24, count 2 2006.257.14:32:09.19#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.14:32:09.19#ibcon#[27=AT04-05\r\n] 2006.257.14:32:09.19#ibcon#*before write, iclass 24, count 2 2006.257.14:32:09.19#ibcon#enter sib2, iclass 24, count 2 2006.257.14:32:09.19#ibcon#flushed, iclass 24, count 2 2006.257.14:32:09.19#ibcon#about to write, iclass 24, count 2 2006.257.14:32:09.19#ibcon#wrote, iclass 24, count 2 2006.257.14:32:09.19#ibcon#about to read 3, iclass 24, count 2 2006.257.14:32:09.22#ibcon#read 3, iclass 24, count 2 2006.257.14:32:09.22#ibcon#about to read 4, iclass 24, count 2 2006.257.14:32:09.22#ibcon#read 4, iclass 24, count 2 2006.257.14:32:09.22#ibcon#about to read 5, iclass 24, count 2 2006.257.14:32:09.22#ibcon#read 5, iclass 24, count 2 2006.257.14:32:09.22#ibcon#about to read 6, iclass 24, count 2 2006.257.14:32:09.22#ibcon#read 6, iclass 24, count 2 2006.257.14:32:09.22#ibcon#end of sib2, iclass 24, count 2 2006.257.14:32:09.22#ibcon#*after write, iclass 24, count 2 2006.257.14:32:09.22#ibcon#*before return 0, iclass 24, count 2 2006.257.14:32:09.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:09.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:32:09.22#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.14:32:09.22#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:09.22#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:09.34#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:09.34#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:09.34#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:32:09.34#ibcon#first serial, iclass 24, count 0 2006.257.14:32:09.34#ibcon#enter sib2, iclass 24, count 0 2006.257.14:32:09.34#ibcon#flushed, iclass 24, count 0 2006.257.14:32:09.34#ibcon#about to write, iclass 24, count 0 2006.257.14:32:09.34#ibcon#wrote, iclass 24, count 0 2006.257.14:32:09.34#ibcon#about to read 3, iclass 24, count 0 2006.257.14:32:09.36#ibcon#read 3, iclass 24, count 0 2006.257.14:32:09.36#ibcon#about to read 4, iclass 24, count 0 2006.257.14:32:09.36#ibcon#read 4, iclass 24, count 0 2006.257.14:32:09.36#ibcon#about to read 5, iclass 24, count 0 2006.257.14:32:09.36#ibcon#read 5, iclass 24, count 0 2006.257.14:32:09.36#ibcon#about to read 6, iclass 24, count 0 2006.257.14:32:09.36#ibcon#read 6, iclass 24, count 0 2006.257.14:32:09.36#ibcon#end of sib2, iclass 24, count 0 2006.257.14:32:09.36#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:32:09.36#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:32:09.36#ibcon#[27=USB\r\n] 2006.257.14:32:09.36#ibcon#*before write, iclass 24, count 0 2006.257.14:32:09.36#ibcon#enter sib2, iclass 24, count 0 2006.257.14:32:09.36#ibcon#flushed, iclass 24, count 0 2006.257.14:32:09.36#ibcon#about to write, iclass 24, count 0 2006.257.14:32:09.36#ibcon#wrote, iclass 24, count 0 2006.257.14:32:09.36#ibcon#about to read 3, iclass 24, count 0 2006.257.14:32:09.39#ibcon#read 3, iclass 24, count 0 2006.257.14:32:09.39#ibcon#about to read 4, iclass 24, count 0 2006.257.14:32:09.39#ibcon#read 4, iclass 24, count 0 2006.257.14:32:09.39#ibcon#about to read 5, iclass 24, count 0 2006.257.14:32:09.39#ibcon#read 5, iclass 24, count 0 2006.257.14:32:09.39#ibcon#about to read 6, iclass 24, count 0 2006.257.14:32:09.39#ibcon#read 6, iclass 24, count 0 2006.257.14:32:09.39#ibcon#end of sib2, iclass 24, count 0 2006.257.14:32:09.39#ibcon#*after write, iclass 24, count 0 2006.257.14:32:09.39#ibcon#*before return 0, iclass 24, count 0 2006.257.14:32:09.39#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:09.39#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:32:09.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:32:09.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:32:09.39$vck44/vblo=5,709.99 2006.257.14:32:09.39#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.14:32:09.39#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.14:32:09.39#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:09.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:09.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:09.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:09.39#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:32:09.39#ibcon#first serial, iclass 26, count 0 2006.257.14:32:09.39#ibcon#enter sib2, iclass 26, count 0 2006.257.14:32:09.39#ibcon#flushed, iclass 26, count 0 2006.257.14:32:09.39#ibcon#about to write, iclass 26, count 0 2006.257.14:32:09.39#ibcon#wrote, iclass 26, count 0 2006.257.14:32:09.39#ibcon#about to read 3, iclass 26, count 0 2006.257.14:32:09.41#ibcon#read 3, iclass 26, count 0 2006.257.14:32:09.41#ibcon#about to read 4, iclass 26, count 0 2006.257.14:32:09.41#ibcon#read 4, iclass 26, count 0 2006.257.14:32:09.41#ibcon#about to read 5, iclass 26, count 0 2006.257.14:32:09.41#ibcon#read 5, iclass 26, count 0 2006.257.14:32:09.41#ibcon#about to read 6, iclass 26, count 0 2006.257.14:32:09.41#ibcon#read 6, iclass 26, count 0 2006.257.14:32:09.41#ibcon#end of sib2, iclass 26, count 0 2006.257.14:32:09.41#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:32:09.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:32:09.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:32:09.41#ibcon#*before write, iclass 26, count 0 2006.257.14:32:09.41#ibcon#enter sib2, iclass 26, count 0 2006.257.14:32:09.41#ibcon#flushed, iclass 26, count 0 2006.257.14:32:09.41#ibcon#about to write, iclass 26, count 0 2006.257.14:32:09.41#ibcon#wrote, iclass 26, count 0 2006.257.14:32:09.41#ibcon#about to read 3, iclass 26, count 0 2006.257.14:32:09.45#ibcon#read 3, iclass 26, count 0 2006.257.14:32:09.45#ibcon#about to read 4, iclass 26, count 0 2006.257.14:32:09.45#ibcon#read 4, iclass 26, count 0 2006.257.14:32:09.45#ibcon#about to read 5, iclass 26, count 0 2006.257.14:32:09.45#ibcon#read 5, iclass 26, count 0 2006.257.14:32:09.45#ibcon#about to read 6, iclass 26, count 0 2006.257.14:32:09.45#ibcon#read 6, iclass 26, count 0 2006.257.14:32:09.45#ibcon#end of sib2, iclass 26, count 0 2006.257.14:32:09.45#ibcon#*after write, iclass 26, count 0 2006.257.14:32:09.45#ibcon#*before return 0, iclass 26, count 0 2006.257.14:32:09.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:09.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:32:09.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:32:09.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:32:09.45$vck44/vb=5,4 2006.257.14:32:09.45#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.14:32:09.45#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.14:32:09.45#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:09.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:09.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:09.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:09.51#ibcon#enter wrdev, iclass 28, count 2 2006.257.14:32:09.51#ibcon#first serial, iclass 28, count 2 2006.257.14:32:09.51#ibcon#enter sib2, iclass 28, count 2 2006.257.14:32:09.51#ibcon#flushed, iclass 28, count 2 2006.257.14:32:09.51#ibcon#about to write, iclass 28, count 2 2006.257.14:32:09.51#ibcon#wrote, iclass 28, count 2 2006.257.14:32:09.51#ibcon#about to read 3, iclass 28, count 2 2006.257.14:32:09.53#ibcon#read 3, iclass 28, count 2 2006.257.14:32:09.53#ibcon#about to read 4, iclass 28, count 2 2006.257.14:32:09.53#ibcon#read 4, iclass 28, count 2 2006.257.14:32:09.53#ibcon#about to read 5, iclass 28, count 2 2006.257.14:32:09.53#ibcon#read 5, iclass 28, count 2 2006.257.14:32:09.53#ibcon#about to read 6, iclass 28, count 2 2006.257.14:32:09.53#ibcon#read 6, iclass 28, count 2 2006.257.14:32:09.53#ibcon#end of sib2, iclass 28, count 2 2006.257.14:32:09.53#ibcon#*mode == 0, iclass 28, count 2 2006.257.14:32:09.53#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.14:32:09.53#ibcon#[27=AT05-04\r\n] 2006.257.14:32:09.53#ibcon#*before write, iclass 28, count 2 2006.257.14:32:09.53#ibcon#enter sib2, iclass 28, count 2 2006.257.14:32:09.53#ibcon#flushed, iclass 28, count 2 2006.257.14:32:09.53#ibcon#about to write, iclass 28, count 2 2006.257.14:32:09.53#ibcon#wrote, iclass 28, count 2 2006.257.14:32:09.53#ibcon#about to read 3, iclass 28, count 2 2006.257.14:32:09.56#ibcon#read 3, iclass 28, count 2 2006.257.14:32:09.59#ibcon#about to read 4, iclass 28, count 2 2006.257.14:32:09.59#ibcon#read 4, iclass 28, count 2 2006.257.14:32:09.59#ibcon#about to read 5, iclass 28, count 2 2006.257.14:32:09.59#ibcon#read 5, iclass 28, count 2 2006.257.14:32:09.59#ibcon#about to read 6, iclass 28, count 2 2006.257.14:32:09.59#ibcon#read 6, iclass 28, count 2 2006.257.14:32:09.59#ibcon#end of sib2, iclass 28, count 2 2006.257.14:32:09.59#ibcon#*after write, iclass 28, count 2 2006.257.14:32:09.59#ibcon#*before return 0, iclass 28, count 2 2006.257.14:32:09.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:09.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:32:09.59#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.14:32:09.59#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:09.59#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:09.70#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:09.70#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:09.70#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:32:09.70#ibcon#first serial, iclass 28, count 0 2006.257.14:32:09.70#ibcon#enter sib2, iclass 28, count 0 2006.257.14:32:09.70#ibcon#flushed, iclass 28, count 0 2006.257.14:32:09.70#ibcon#about to write, iclass 28, count 0 2006.257.14:32:09.70#ibcon#wrote, iclass 28, count 0 2006.257.14:32:09.70#ibcon#about to read 3, iclass 28, count 0 2006.257.14:32:09.72#ibcon#read 3, iclass 28, count 0 2006.257.14:32:09.72#ibcon#about to read 4, iclass 28, count 0 2006.257.14:32:09.72#ibcon#read 4, iclass 28, count 0 2006.257.14:32:09.72#ibcon#about to read 5, iclass 28, count 0 2006.257.14:32:09.72#ibcon#read 5, iclass 28, count 0 2006.257.14:32:09.72#ibcon#about to read 6, iclass 28, count 0 2006.257.14:32:09.72#ibcon#read 6, iclass 28, count 0 2006.257.14:32:09.72#ibcon#end of sib2, iclass 28, count 0 2006.257.14:32:09.72#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:32:09.72#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:32:09.72#ibcon#[27=USB\r\n] 2006.257.14:32:09.72#ibcon#*before write, iclass 28, count 0 2006.257.14:32:09.72#ibcon#enter sib2, iclass 28, count 0 2006.257.14:32:09.72#ibcon#flushed, iclass 28, count 0 2006.257.14:32:09.72#ibcon#about to write, iclass 28, count 0 2006.257.14:32:09.72#ibcon#wrote, iclass 28, count 0 2006.257.14:32:09.72#ibcon#about to read 3, iclass 28, count 0 2006.257.14:32:09.75#ibcon#read 3, iclass 28, count 0 2006.257.14:32:09.75#ibcon#about to read 4, iclass 28, count 0 2006.257.14:32:09.75#ibcon#read 4, iclass 28, count 0 2006.257.14:32:09.75#ibcon#about to read 5, iclass 28, count 0 2006.257.14:32:09.75#ibcon#read 5, iclass 28, count 0 2006.257.14:32:09.75#ibcon#about to read 6, iclass 28, count 0 2006.257.14:32:09.75#ibcon#read 6, iclass 28, count 0 2006.257.14:32:09.75#ibcon#end of sib2, iclass 28, count 0 2006.257.14:32:09.75#ibcon#*after write, iclass 28, count 0 2006.257.14:32:09.75#ibcon#*before return 0, iclass 28, count 0 2006.257.14:32:09.75#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:09.75#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:32:09.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:32:09.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:32:09.75$vck44/vblo=6,719.99 2006.257.14:32:09.75#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.14:32:09.75#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.14:32:09.75#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:09.75#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:09.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:09.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:09.75#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:32:09.75#ibcon#first serial, iclass 30, count 0 2006.257.14:32:09.75#ibcon#enter sib2, iclass 30, count 0 2006.257.14:32:09.75#ibcon#flushed, iclass 30, count 0 2006.257.14:32:09.75#ibcon#about to write, iclass 30, count 0 2006.257.14:32:09.75#ibcon#wrote, iclass 30, count 0 2006.257.14:32:09.75#ibcon#about to read 3, iclass 30, count 0 2006.257.14:32:09.77#ibcon#read 3, iclass 30, count 0 2006.257.14:32:09.77#ibcon#about to read 4, iclass 30, count 0 2006.257.14:32:09.77#ibcon#read 4, iclass 30, count 0 2006.257.14:32:09.77#ibcon#about to read 5, iclass 30, count 0 2006.257.14:32:09.77#ibcon#read 5, iclass 30, count 0 2006.257.14:32:09.77#ibcon#about to read 6, iclass 30, count 0 2006.257.14:32:09.77#ibcon#read 6, iclass 30, count 0 2006.257.14:32:09.77#ibcon#end of sib2, iclass 30, count 0 2006.257.14:32:09.77#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:32:09.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:32:09.77#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:32:09.77#ibcon#*before write, iclass 30, count 0 2006.257.14:32:09.77#ibcon#enter sib2, iclass 30, count 0 2006.257.14:32:09.77#ibcon#flushed, iclass 30, count 0 2006.257.14:32:09.77#ibcon#about to write, iclass 30, count 0 2006.257.14:32:09.77#ibcon#wrote, iclass 30, count 0 2006.257.14:32:09.77#ibcon#about to read 3, iclass 30, count 0 2006.257.14:32:09.81#ibcon#read 3, iclass 30, count 0 2006.257.14:32:09.81#ibcon#about to read 4, iclass 30, count 0 2006.257.14:32:09.81#ibcon#read 4, iclass 30, count 0 2006.257.14:32:09.81#ibcon#about to read 5, iclass 30, count 0 2006.257.14:32:09.81#ibcon#read 5, iclass 30, count 0 2006.257.14:32:09.81#ibcon#about to read 6, iclass 30, count 0 2006.257.14:32:09.81#ibcon#read 6, iclass 30, count 0 2006.257.14:32:09.81#ibcon#end of sib2, iclass 30, count 0 2006.257.14:32:09.81#ibcon#*after write, iclass 30, count 0 2006.257.14:32:09.81#ibcon#*before return 0, iclass 30, count 0 2006.257.14:32:09.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:09.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:32:09.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:32:09.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:32:09.81$vck44/vb=6,4 2006.257.14:32:09.81#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.14:32:09.81#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.14:32:09.81#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:09.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:09.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:09.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:09.87#ibcon#enter wrdev, iclass 32, count 2 2006.257.14:32:09.87#ibcon#first serial, iclass 32, count 2 2006.257.14:32:09.87#ibcon#enter sib2, iclass 32, count 2 2006.257.14:32:09.87#ibcon#flushed, iclass 32, count 2 2006.257.14:32:09.87#ibcon#about to write, iclass 32, count 2 2006.257.14:32:09.87#ibcon#wrote, iclass 32, count 2 2006.257.14:32:09.87#ibcon#about to read 3, iclass 32, count 2 2006.257.14:32:09.89#ibcon#read 3, iclass 32, count 2 2006.257.14:32:09.89#ibcon#about to read 4, iclass 32, count 2 2006.257.14:32:09.89#ibcon#read 4, iclass 32, count 2 2006.257.14:32:09.89#ibcon#about to read 5, iclass 32, count 2 2006.257.14:32:09.89#ibcon#read 5, iclass 32, count 2 2006.257.14:32:09.89#ibcon#about to read 6, iclass 32, count 2 2006.257.14:32:09.89#ibcon#read 6, iclass 32, count 2 2006.257.14:32:09.89#ibcon#end of sib2, iclass 32, count 2 2006.257.14:32:09.89#ibcon#*mode == 0, iclass 32, count 2 2006.257.14:32:09.89#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.14:32:09.89#ibcon#[27=AT06-04\r\n] 2006.257.14:32:09.89#ibcon#*before write, iclass 32, count 2 2006.257.14:32:09.89#ibcon#enter sib2, iclass 32, count 2 2006.257.14:32:09.89#ibcon#flushed, iclass 32, count 2 2006.257.14:32:09.89#ibcon#about to write, iclass 32, count 2 2006.257.14:32:09.89#ibcon#wrote, iclass 32, count 2 2006.257.14:32:09.89#ibcon#about to read 3, iclass 32, count 2 2006.257.14:32:09.92#ibcon#read 3, iclass 32, count 2 2006.257.14:32:09.92#ibcon#about to read 4, iclass 32, count 2 2006.257.14:32:09.92#ibcon#read 4, iclass 32, count 2 2006.257.14:32:09.92#ibcon#about to read 5, iclass 32, count 2 2006.257.14:32:09.92#ibcon#read 5, iclass 32, count 2 2006.257.14:32:09.92#ibcon#about to read 6, iclass 32, count 2 2006.257.14:32:09.92#ibcon#read 6, iclass 32, count 2 2006.257.14:32:09.92#ibcon#end of sib2, iclass 32, count 2 2006.257.14:32:09.92#ibcon#*after write, iclass 32, count 2 2006.257.14:32:09.92#ibcon#*before return 0, iclass 32, count 2 2006.257.14:32:09.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:09.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:32:09.92#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.14:32:09.92#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:09.92#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:10.04#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:10.04#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:10.04#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:32:10.04#ibcon#first serial, iclass 32, count 0 2006.257.14:32:10.04#ibcon#enter sib2, iclass 32, count 0 2006.257.14:32:10.04#ibcon#flushed, iclass 32, count 0 2006.257.14:32:10.04#ibcon#about to write, iclass 32, count 0 2006.257.14:32:10.04#ibcon#wrote, iclass 32, count 0 2006.257.14:32:10.04#ibcon#about to read 3, iclass 32, count 0 2006.257.14:32:10.06#ibcon#read 3, iclass 32, count 0 2006.257.14:32:10.06#ibcon#about to read 4, iclass 32, count 0 2006.257.14:32:10.06#ibcon#read 4, iclass 32, count 0 2006.257.14:32:10.06#ibcon#about to read 5, iclass 32, count 0 2006.257.14:32:10.06#ibcon#read 5, iclass 32, count 0 2006.257.14:32:10.06#ibcon#about to read 6, iclass 32, count 0 2006.257.14:32:10.06#ibcon#read 6, iclass 32, count 0 2006.257.14:32:10.06#ibcon#end of sib2, iclass 32, count 0 2006.257.14:32:10.06#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:32:10.06#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:32:10.06#ibcon#[27=USB\r\n] 2006.257.14:32:10.06#ibcon#*before write, iclass 32, count 0 2006.257.14:32:10.06#ibcon#enter sib2, iclass 32, count 0 2006.257.14:32:10.06#ibcon#flushed, iclass 32, count 0 2006.257.14:32:10.06#ibcon#about to write, iclass 32, count 0 2006.257.14:32:10.06#ibcon#wrote, iclass 32, count 0 2006.257.14:32:10.06#ibcon#about to read 3, iclass 32, count 0 2006.257.14:32:10.09#ibcon#read 3, iclass 32, count 0 2006.257.14:32:10.09#ibcon#about to read 4, iclass 32, count 0 2006.257.14:32:10.09#ibcon#read 4, iclass 32, count 0 2006.257.14:32:10.09#ibcon#about to read 5, iclass 32, count 0 2006.257.14:32:10.09#ibcon#read 5, iclass 32, count 0 2006.257.14:32:10.09#ibcon#about to read 6, iclass 32, count 0 2006.257.14:32:10.09#ibcon#read 6, iclass 32, count 0 2006.257.14:32:10.09#ibcon#end of sib2, iclass 32, count 0 2006.257.14:32:10.09#ibcon#*after write, iclass 32, count 0 2006.257.14:32:10.09#ibcon#*before return 0, iclass 32, count 0 2006.257.14:32:10.09#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:10.09#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:32:10.09#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:32:10.09#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:32:10.09$vck44/vblo=7,734.99 2006.257.14:32:10.09#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.14:32:10.09#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.14:32:10.09#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:10.09#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:10.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:10.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:10.09#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:32:10.09#ibcon#first serial, iclass 34, count 0 2006.257.14:32:10.09#ibcon#enter sib2, iclass 34, count 0 2006.257.14:32:10.09#ibcon#flushed, iclass 34, count 0 2006.257.14:32:10.09#ibcon#about to write, iclass 34, count 0 2006.257.14:32:10.09#ibcon#wrote, iclass 34, count 0 2006.257.14:32:10.09#ibcon#about to read 3, iclass 34, count 0 2006.257.14:32:10.11#ibcon#read 3, iclass 34, count 0 2006.257.14:32:10.11#ibcon#about to read 4, iclass 34, count 0 2006.257.14:32:10.11#ibcon#read 4, iclass 34, count 0 2006.257.14:32:10.11#ibcon#about to read 5, iclass 34, count 0 2006.257.14:32:10.11#ibcon#read 5, iclass 34, count 0 2006.257.14:32:10.11#ibcon#about to read 6, iclass 34, count 0 2006.257.14:32:10.11#ibcon#read 6, iclass 34, count 0 2006.257.14:32:10.11#ibcon#end of sib2, iclass 34, count 0 2006.257.14:32:10.11#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:32:10.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:32:10.11#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:32:10.11#ibcon#*before write, iclass 34, count 0 2006.257.14:32:10.11#ibcon#enter sib2, iclass 34, count 0 2006.257.14:32:10.11#ibcon#flushed, iclass 34, count 0 2006.257.14:32:10.11#ibcon#about to write, iclass 34, count 0 2006.257.14:32:10.11#ibcon#wrote, iclass 34, count 0 2006.257.14:32:10.11#ibcon#about to read 3, iclass 34, count 0 2006.257.14:32:10.15#ibcon#read 3, iclass 34, count 0 2006.257.14:32:10.15#ibcon#about to read 4, iclass 34, count 0 2006.257.14:32:10.15#ibcon#read 4, iclass 34, count 0 2006.257.14:32:10.15#ibcon#about to read 5, iclass 34, count 0 2006.257.14:32:10.15#ibcon#read 5, iclass 34, count 0 2006.257.14:32:10.15#ibcon#about to read 6, iclass 34, count 0 2006.257.14:32:10.15#ibcon#read 6, iclass 34, count 0 2006.257.14:32:10.15#ibcon#end of sib2, iclass 34, count 0 2006.257.14:32:10.15#ibcon#*after write, iclass 34, count 0 2006.257.14:32:10.15#ibcon#*before return 0, iclass 34, count 0 2006.257.14:32:10.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:10.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:32:10.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:32:10.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:32:10.15$vck44/vb=7,4 2006.257.14:32:10.15#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.14:32:10.15#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.14:32:10.15#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:10.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:10.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:10.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:10.21#ibcon#enter wrdev, iclass 36, count 2 2006.257.14:32:10.21#ibcon#first serial, iclass 36, count 2 2006.257.14:32:10.21#ibcon#enter sib2, iclass 36, count 2 2006.257.14:32:10.21#ibcon#flushed, iclass 36, count 2 2006.257.14:32:10.21#ibcon#about to write, iclass 36, count 2 2006.257.14:32:10.21#ibcon#wrote, iclass 36, count 2 2006.257.14:32:10.21#ibcon#about to read 3, iclass 36, count 2 2006.257.14:32:10.23#ibcon#read 3, iclass 36, count 2 2006.257.14:32:10.23#ibcon#about to read 4, iclass 36, count 2 2006.257.14:32:10.23#ibcon#read 4, iclass 36, count 2 2006.257.14:32:10.23#ibcon#about to read 5, iclass 36, count 2 2006.257.14:32:10.23#ibcon#read 5, iclass 36, count 2 2006.257.14:32:10.23#ibcon#about to read 6, iclass 36, count 2 2006.257.14:32:10.23#ibcon#read 6, iclass 36, count 2 2006.257.14:32:10.23#ibcon#end of sib2, iclass 36, count 2 2006.257.14:32:10.23#ibcon#*mode == 0, iclass 36, count 2 2006.257.14:32:10.23#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.14:32:10.23#ibcon#[27=AT07-04\r\n] 2006.257.14:32:10.23#ibcon#*before write, iclass 36, count 2 2006.257.14:32:10.23#ibcon#enter sib2, iclass 36, count 2 2006.257.14:32:10.23#ibcon#flushed, iclass 36, count 2 2006.257.14:32:10.23#ibcon#about to write, iclass 36, count 2 2006.257.14:32:10.23#ibcon#wrote, iclass 36, count 2 2006.257.14:32:10.23#ibcon#about to read 3, iclass 36, count 2 2006.257.14:32:10.26#ibcon#read 3, iclass 36, count 2 2006.257.14:32:10.26#ibcon#about to read 4, iclass 36, count 2 2006.257.14:32:10.26#ibcon#read 4, iclass 36, count 2 2006.257.14:32:10.26#ibcon#about to read 5, iclass 36, count 2 2006.257.14:32:10.26#ibcon#read 5, iclass 36, count 2 2006.257.14:32:10.26#ibcon#about to read 6, iclass 36, count 2 2006.257.14:32:10.26#ibcon#read 6, iclass 36, count 2 2006.257.14:32:10.26#ibcon#end of sib2, iclass 36, count 2 2006.257.14:32:10.26#ibcon#*after write, iclass 36, count 2 2006.257.14:32:10.26#ibcon#*before return 0, iclass 36, count 2 2006.257.14:32:10.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:10.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:32:10.26#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.14:32:10.26#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:10.26#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:10.38#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:10.38#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:10.38#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:32:10.38#ibcon#first serial, iclass 36, count 0 2006.257.14:32:10.38#ibcon#enter sib2, iclass 36, count 0 2006.257.14:32:10.38#ibcon#flushed, iclass 36, count 0 2006.257.14:32:10.38#ibcon#about to write, iclass 36, count 0 2006.257.14:32:10.38#ibcon#wrote, iclass 36, count 0 2006.257.14:32:10.38#ibcon#about to read 3, iclass 36, count 0 2006.257.14:32:10.40#ibcon#read 3, iclass 36, count 0 2006.257.14:32:10.40#ibcon#about to read 4, iclass 36, count 0 2006.257.14:32:10.40#ibcon#read 4, iclass 36, count 0 2006.257.14:32:10.40#ibcon#about to read 5, iclass 36, count 0 2006.257.14:32:10.40#ibcon#read 5, iclass 36, count 0 2006.257.14:32:10.40#ibcon#about to read 6, iclass 36, count 0 2006.257.14:32:10.40#ibcon#read 6, iclass 36, count 0 2006.257.14:32:10.40#ibcon#end of sib2, iclass 36, count 0 2006.257.14:32:10.40#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:32:10.40#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:32:10.40#ibcon#[27=USB\r\n] 2006.257.14:32:10.40#ibcon#*before write, iclass 36, count 0 2006.257.14:32:10.40#ibcon#enter sib2, iclass 36, count 0 2006.257.14:32:10.40#ibcon#flushed, iclass 36, count 0 2006.257.14:32:10.40#ibcon#about to write, iclass 36, count 0 2006.257.14:32:10.40#ibcon#wrote, iclass 36, count 0 2006.257.14:32:10.40#ibcon#about to read 3, iclass 36, count 0 2006.257.14:32:10.43#ibcon#read 3, iclass 36, count 0 2006.257.14:32:10.43#ibcon#about to read 4, iclass 36, count 0 2006.257.14:32:10.43#ibcon#read 4, iclass 36, count 0 2006.257.14:32:10.43#ibcon#about to read 5, iclass 36, count 0 2006.257.14:32:10.43#ibcon#read 5, iclass 36, count 0 2006.257.14:32:10.43#ibcon#about to read 6, iclass 36, count 0 2006.257.14:32:10.43#ibcon#read 6, iclass 36, count 0 2006.257.14:32:10.43#ibcon#end of sib2, iclass 36, count 0 2006.257.14:32:10.43#ibcon#*after write, iclass 36, count 0 2006.257.14:32:10.43#ibcon#*before return 0, iclass 36, count 0 2006.257.14:32:10.43#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:10.43#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:32:10.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:32:10.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:32:10.43$vck44/vblo=8,744.99 2006.257.14:32:10.43#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.14:32:10.43#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.14:32:10.43#ibcon#ireg 17 cls_cnt 0 2006.257.14:32:10.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:10.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:10.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:10.43#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:32:10.43#ibcon#first serial, iclass 38, count 0 2006.257.14:32:10.43#ibcon#enter sib2, iclass 38, count 0 2006.257.14:32:10.43#ibcon#flushed, iclass 38, count 0 2006.257.14:32:10.43#ibcon#about to write, iclass 38, count 0 2006.257.14:32:10.43#ibcon#wrote, iclass 38, count 0 2006.257.14:32:10.43#ibcon#about to read 3, iclass 38, count 0 2006.257.14:32:10.45#ibcon#read 3, iclass 38, count 0 2006.257.14:32:10.45#ibcon#about to read 4, iclass 38, count 0 2006.257.14:32:10.45#ibcon#read 4, iclass 38, count 0 2006.257.14:32:10.45#ibcon#about to read 5, iclass 38, count 0 2006.257.14:32:10.45#ibcon#read 5, iclass 38, count 0 2006.257.14:32:10.45#ibcon#about to read 6, iclass 38, count 0 2006.257.14:32:10.45#ibcon#read 6, iclass 38, count 0 2006.257.14:32:10.45#ibcon#end of sib2, iclass 38, count 0 2006.257.14:32:10.45#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:32:10.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:32:10.45#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:32:10.45#ibcon#*before write, iclass 38, count 0 2006.257.14:32:10.45#ibcon#enter sib2, iclass 38, count 0 2006.257.14:32:10.45#ibcon#flushed, iclass 38, count 0 2006.257.14:32:10.45#ibcon#about to write, iclass 38, count 0 2006.257.14:32:10.45#ibcon#wrote, iclass 38, count 0 2006.257.14:32:10.45#ibcon#about to read 3, iclass 38, count 0 2006.257.14:32:10.49#ibcon#read 3, iclass 38, count 0 2006.257.14:32:10.49#ibcon#about to read 4, iclass 38, count 0 2006.257.14:32:10.49#ibcon#read 4, iclass 38, count 0 2006.257.14:32:10.49#ibcon#about to read 5, iclass 38, count 0 2006.257.14:32:10.49#ibcon#read 5, iclass 38, count 0 2006.257.14:32:10.49#ibcon#about to read 6, iclass 38, count 0 2006.257.14:32:10.49#ibcon#read 6, iclass 38, count 0 2006.257.14:32:10.49#ibcon#end of sib2, iclass 38, count 0 2006.257.14:32:10.49#ibcon#*after write, iclass 38, count 0 2006.257.14:32:10.49#ibcon#*before return 0, iclass 38, count 0 2006.257.14:32:10.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:10.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:32:10.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:32:10.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:32:10.49$vck44/vb=8,4 2006.257.14:32:10.49#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.14:32:10.49#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.14:32:10.49#ibcon#ireg 11 cls_cnt 2 2006.257.14:32:10.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:10.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:10.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:10.55#ibcon#enter wrdev, iclass 40, count 2 2006.257.14:32:10.55#ibcon#first serial, iclass 40, count 2 2006.257.14:32:10.55#ibcon#enter sib2, iclass 40, count 2 2006.257.14:32:10.55#ibcon#flushed, iclass 40, count 2 2006.257.14:32:10.55#ibcon#about to write, iclass 40, count 2 2006.257.14:32:10.55#ibcon#wrote, iclass 40, count 2 2006.257.14:32:10.55#ibcon#about to read 3, iclass 40, count 2 2006.257.14:32:10.57#ibcon#read 3, iclass 40, count 2 2006.257.14:32:10.57#ibcon#about to read 4, iclass 40, count 2 2006.257.14:32:10.57#ibcon#read 4, iclass 40, count 2 2006.257.14:32:10.57#ibcon#about to read 5, iclass 40, count 2 2006.257.14:32:10.57#ibcon#read 5, iclass 40, count 2 2006.257.14:32:10.57#ibcon#about to read 6, iclass 40, count 2 2006.257.14:32:10.57#ibcon#read 6, iclass 40, count 2 2006.257.14:32:10.57#ibcon#end of sib2, iclass 40, count 2 2006.257.14:32:10.57#ibcon#*mode == 0, iclass 40, count 2 2006.257.14:32:10.57#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.14:32:10.57#ibcon#[27=AT08-04\r\n] 2006.257.14:32:10.57#ibcon#*before write, iclass 40, count 2 2006.257.14:32:10.57#ibcon#enter sib2, iclass 40, count 2 2006.257.14:32:10.57#ibcon#flushed, iclass 40, count 2 2006.257.14:32:10.57#ibcon#about to write, iclass 40, count 2 2006.257.14:32:10.57#ibcon#wrote, iclass 40, count 2 2006.257.14:32:10.57#ibcon#about to read 3, iclass 40, count 2 2006.257.14:32:10.60#ibcon#read 3, iclass 40, count 2 2006.257.14:32:10.64#ibcon#about to read 4, iclass 40, count 2 2006.257.14:32:10.64#ibcon#read 4, iclass 40, count 2 2006.257.14:32:10.64#ibcon#about to read 5, iclass 40, count 2 2006.257.14:32:10.64#ibcon#read 5, iclass 40, count 2 2006.257.14:32:10.64#ibcon#about to read 6, iclass 40, count 2 2006.257.14:32:10.64#ibcon#read 6, iclass 40, count 2 2006.257.14:32:10.64#ibcon#end of sib2, iclass 40, count 2 2006.257.14:32:10.64#ibcon#*after write, iclass 40, count 2 2006.257.14:32:10.64#ibcon#*before return 0, iclass 40, count 2 2006.257.14:32:10.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:10.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:32:10.65#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.14:32:10.65#ibcon#ireg 7 cls_cnt 0 2006.257.14:32:10.65#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:10.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:10.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:10.76#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:32:10.76#ibcon#first serial, iclass 40, count 0 2006.257.14:32:10.76#ibcon#enter sib2, iclass 40, count 0 2006.257.14:32:10.76#ibcon#flushed, iclass 40, count 0 2006.257.14:32:10.76#ibcon#about to write, iclass 40, count 0 2006.257.14:32:10.76#ibcon#wrote, iclass 40, count 0 2006.257.14:32:10.76#ibcon#about to read 3, iclass 40, count 0 2006.257.14:32:10.78#ibcon#read 3, iclass 40, count 0 2006.257.14:32:10.78#ibcon#about to read 4, iclass 40, count 0 2006.257.14:32:10.78#ibcon#read 4, iclass 40, count 0 2006.257.14:32:10.78#ibcon#about to read 5, iclass 40, count 0 2006.257.14:32:10.78#ibcon#read 5, iclass 40, count 0 2006.257.14:32:10.78#ibcon#about to read 6, iclass 40, count 0 2006.257.14:32:10.78#ibcon#read 6, iclass 40, count 0 2006.257.14:32:10.78#ibcon#end of sib2, iclass 40, count 0 2006.257.14:32:10.78#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:32:10.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:32:10.78#ibcon#[27=USB\r\n] 2006.257.14:32:10.78#ibcon#*before write, iclass 40, count 0 2006.257.14:32:10.78#ibcon#enter sib2, iclass 40, count 0 2006.257.14:32:10.78#ibcon#flushed, iclass 40, count 0 2006.257.14:32:10.78#ibcon#about to write, iclass 40, count 0 2006.257.14:32:10.78#ibcon#wrote, iclass 40, count 0 2006.257.14:32:10.78#ibcon#about to read 3, iclass 40, count 0 2006.257.14:32:10.81#ibcon#read 3, iclass 40, count 0 2006.257.14:32:10.81#ibcon#about to read 4, iclass 40, count 0 2006.257.14:32:10.81#ibcon#read 4, iclass 40, count 0 2006.257.14:32:10.81#ibcon#about to read 5, iclass 40, count 0 2006.257.14:32:10.81#ibcon#read 5, iclass 40, count 0 2006.257.14:32:10.81#ibcon#about to read 6, iclass 40, count 0 2006.257.14:32:10.81#ibcon#read 6, iclass 40, count 0 2006.257.14:32:10.81#ibcon#end of sib2, iclass 40, count 0 2006.257.14:32:10.81#ibcon#*after write, iclass 40, count 0 2006.257.14:32:10.81#ibcon#*before return 0, iclass 40, count 0 2006.257.14:32:10.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:10.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:32:10.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:32:10.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:32:10.81$vck44/vabw=wide 2006.257.14:32:10.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.14:32:10.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.14:32:10.81#ibcon#ireg 8 cls_cnt 0 2006.257.14:32:10.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:10.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:10.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:10.81#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:32:10.81#ibcon#first serial, iclass 4, count 0 2006.257.14:32:10.81#ibcon#enter sib2, iclass 4, count 0 2006.257.14:32:10.81#ibcon#flushed, iclass 4, count 0 2006.257.14:32:10.81#ibcon#about to write, iclass 4, count 0 2006.257.14:32:10.81#ibcon#wrote, iclass 4, count 0 2006.257.14:32:10.81#ibcon#about to read 3, iclass 4, count 0 2006.257.14:32:10.83#ibcon#read 3, iclass 4, count 0 2006.257.14:32:10.83#ibcon#about to read 4, iclass 4, count 0 2006.257.14:32:10.83#ibcon#read 4, iclass 4, count 0 2006.257.14:32:10.83#ibcon#about to read 5, iclass 4, count 0 2006.257.14:32:10.83#ibcon#read 5, iclass 4, count 0 2006.257.14:32:10.83#ibcon#about to read 6, iclass 4, count 0 2006.257.14:32:10.83#ibcon#read 6, iclass 4, count 0 2006.257.14:32:10.83#ibcon#end of sib2, iclass 4, count 0 2006.257.14:32:10.83#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:32:10.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:32:10.83#ibcon#[25=BW32\r\n] 2006.257.14:32:10.83#ibcon#*before write, iclass 4, count 0 2006.257.14:32:10.83#ibcon#enter sib2, iclass 4, count 0 2006.257.14:32:10.83#ibcon#flushed, iclass 4, count 0 2006.257.14:32:10.83#ibcon#about to write, iclass 4, count 0 2006.257.14:32:10.83#ibcon#wrote, iclass 4, count 0 2006.257.14:32:10.83#ibcon#about to read 3, iclass 4, count 0 2006.257.14:32:10.86#ibcon#read 3, iclass 4, count 0 2006.257.14:32:10.86#ibcon#about to read 4, iclass 4, count 0 2006.257.14:32:10.86#ibcon#read 4, iclass 4, count 0 2006.257.14:32:10.86#ibcon#about to read 5, iclass 4, count 0 2006.257.14:32:10.86#ibcon#read 5, iclass 4, count 0 2006.257.14:32:10.86#ibcon#about to read 6, iclass 4, count 0 2006.257.14:32:10.86#ibcon#read 6, iclass 4, count 0 2006.257.14:32:10.86#ibcon#end of sib2, iclass 4, count 0 2006.257.14:32:10.86#ibcon#*after write, iclass 4, count 0 2006.257.14:32:10.86#ibcon#*before return 0, iclass 4, count 0 2006.257.14:32:10.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:10.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:32:10.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:32:10.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:32:10.86$vck44/vbbw=wide 2006.257.14:32:10.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.14:32:10.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.14:32:10.86#ibcon#ireg 8 cls_cnt 0 2006.257.14:32:10.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:32:10.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:32:10.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:32:10.93#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:32:10.93#ibcon#first serial, iclass 6, count 0 2006.257.14:32:10.93#ibcon#enter sib2, iclass 6, count 0 2006.257.14:32:10.93#ibcon#flushed, iclass 6, count 0 2006.257.14:32:10.93#ibcon#about to write, iclass 6, count 0 2006.257.14:32:10.93#ibcon#wrote, iclass 6, count 0 2006.257.14:32:10.93#ibcon#about to read 3, iclass 6, count 0 2006.257.14:32:10.95#ibcon#read 3, iclass 6, count 0 2006.257.14:32:10.95#ibcon#about to read 4, iclass 6, count 0 2006.257.14:32:10.95#ibcon#read 4, iclass 6, count 0 2006.257.14:32:10.95#ibcon#about to read 5, iclass 6, count 0 2006.257.14:32:10.95#ibcon#read 5, iclass 6, count 0 2006.257.14:32:10.95#ibcon#about to read 6, iclass 6, count 0 2006.257.14:32:10.95#ibcon#read 6, iclass 6, count 0 2006.257.14:32:10.95#ibcon#end of sib2, iclass 6, count 0 2006.257.14:32:10.95#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:32:10.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:32:10.95#ibcon#[27=BW32\r\n] 2006.257.14:32:10.95#ibcon#*before write, iclass 6, count 0 2006.257.14:32:10.95#ibcon#enter sib2, iclass 6, count 0 2006.257.14:32:10.95#ibcon#flushed, iclass 6, count 0 2006.257.14:32:10.95#ibcon#about to write, iclass 6, count 0 2006.257.14:32:10.95#ibcon#wrote, iclass 6, count 0 2006.257.14:32:10.95#ibcon#about to read 3, iclass 6, count 0 2006.257.14:32:10.98#ibcon#read 3, iclass 6, count 0 2006.257.14:32:10.98#ibcon#about to read 4, iclass 6, count 0 2006.257.14:32:10.98#ibcon#read 4, iclass 6, count 0 2006.257.14:32:10.98#ibcon#about to read 5, iclass 6, count 0 2006.257.14:32:10.98#ibcon#read 5, iclass 6, count 0 2006.257.14:32:10.98#ibcon#about to read 6, iclass 6, count 0 2006.257.14:32:10.98#ibcon#read 6, iclass 6, count 0 2006.257.14:32:10.98#ibcon#end of sib2, iclass 6, count 0 2006.257.14:32:10.98#ibcon#*after write, iclass 6, count 0 2006.257.14:32:10.98#ibcon#*before return 0, iclass 6, count 0 2006.257.14:32:10.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:32:10.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:32:10.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:32:10.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:32:10.98$setupk4/ifdk4 2006.257.14:32:10.98$ifdk4/lo= 2006.257.14:32:10.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:32:10.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:32:10.98$ifdk4/patch= 2006.257.14:32:10.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:32:10.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:32:10.99$setupk4/!*+20s 2006.257.14:32:13.34#abcon#<5=/14 1.4 3.6 17.45 971014.1\r\n> 2006.257.14:32:13.36#abcon#{5=INTERFACE CLEAR} 2006.257.14:32:13.42#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:32:19.14#trakl#Source acquired 2006.257.14:32:19.14#flagr#flagr/antenna,acquired 2006.257.14:32:23.51#abcon#<5=/14 1.4 3.6 17.46 971014.1\r\n> 2006.257.14:32:23.53#abcon#{5=INTERFACE CLEAR} 2006.257.14:32:23.59#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:32:25.27$setupk4/"tpicd 2006.257.14:32:25.27$setupk4/echo=off 2006.257.14:32:25.27$setupk4/xlog=off 2006.257.14:32:25.27:!2006.257.14:34:22 2006.257.14:34:22.00:preob 2006.257.14:34:23.14/onsource/TRACKING 2006.257.14:34:23.14:!2006.257.14:34:32 2006.257.14:34:32.00:"tape 2006.257.14:34:32.00:"st=record 2006.257.14:34:32.00:data_valid=on 2006.257.14:34:32.00:midob 2006.257.14:34:32.14/onsource/TRACKING 2006.257.14:34:32.14/wx/17.46,1014.1,97 2006.257.14:34:32.20/cable/+6.4825E-03 2006.257.14:34:33.29/va/01,08,usb,yes,30,33 2006.257.14:34:33.29/va/02,07,usb,yes,33,33 2006.257.14:34:33.29/va/03,08,usb,yes,29,31 2006.257.14:34:33.29/va/04,07,usb,yes,34,35 2006.257.14:34:33.29/va/05,04,usb,yes,30,31 2006.257.14:34:33.29/va/06,04,usb,yes,34,33 2006.257.14:34:33.29/va/07,04,usb,yes,35,35 2006.257.14:34:33.29/va/08,04,usb,yes,29,35 2006.257.14:34:33.52/valo/01,524.99,yes,locked 2006.257.14:34:33.52/valo/02,534.99,yes,locked 2006.257.14:34:33.52/valo/03,564.99,yes,locked 2006.257.14:34:33.52/valo/04,624.99,yes,locked 2006.257.14:34:33.52/valo/05,734.99,yes,locked 2006.257.14:34:33.52/valo/06,814.99,yes,locked 2006.257.14:34:33.52/valo/07,864.99,yes,locked 2006.257.14:34:33.52/valo/08,884.99,yes,locked 2006.257.14:34:34.61/vb/01,04,usb,yes,30,28 2006.257.14:34:34.61/vb/02,05,usb,yes,28,28 2006.257.14:34:34.61/vb/03,04,usb,yes,29,32 2006.257.14:34:34.61/vb/04,05,usb,yes,29,28 2006.257.14:34:34.61/vb/05,04,usb,yes,26,28 2006.257.14:34:34.61/vb/06,04,usb,yes,30,27 2006.257.14:34:34.61/vb/07,04,usb,yes,30,30 2006.257.14:34:34.61/vb/08,04,usb,yes,28,31 2006.257.14:34:34.85/vblo/01,629.99,yes,locked 2006.257.14:34:34.85/vblo/02,634.99,yes,locked 2006.257.14:34:34.85/vblo/03,649.99,yes,locked 2006.257.14:34:34.85/vblo/04,679.99,yes,locked 2006.257.14:34:34.85/vblo/05,709.99,yes,locked 2006.257.14:34:34.85/vblo/06,719.99,yes,locked 2006.257.14:34:34.85/vblo/07,734.99,yes,locked 2006.257.14:34:34.85/vblo/08,744.99,yes,locked 2006.257.14:34:35.00/vabw/8 2006.257.14:34:35.15/vbbw/8 2006.257.14:34:35.26/xfe/off,on,15.2 2006.257.14:34:35.63/ifatt/23,28,28,28 2006.257.14:34:36.07/fmout-gps/S +4.57E-07 2006.257.14:34:36.11:!2006.257.14:35:42 2006.257.14:35:42.00:data_valid=off 2006.257.14:35:42.00:"et 2006.257.14:35:42.00:!+3s 2006.257.14:35:45.01:"tape 2006.257.14:35:45.01:postob 2006.257.14:35:45.08/cable/+6.4824E-03 2006.257.14:35:45.08/wx/17.47,1014.1,97 2006.257.14:35:46.07/fmout-gps/S +4.57E-07 2006.257.14:35:46.07:scan_name=257-1439,jd0609,160 2006.257.14:35:46.07:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.257.14:35:47.14#flagr#flagr/antenna,new-source 2006.257.14:35:47.14:checkk5 2006.257.14:35:47.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:35:47.90/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:35:48.32/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:35:48.70/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:35:49.09/chk_obsdata//k5ts1/T2571434??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.14:35:49.49/chk_obsdata//k5ts2/T2571434??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.14:35:49.88/chk_obsdata//k5ts3/T2571434??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.14:35:50.29/chk_obsdata//k5ts4/T2571434??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.257.14:35:51.01/k5log//k5ts1_log_newline 2006.257.14:35:51.71/k5log//k5ts2_log_newline 2006.257.14:35:52.41/k5log//k5ts3_log_newline 2006.257.14:35:53.11/k5log//k5ts4_log_newline 2006.257.14:35:53.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:35:53.13:setupk4=1 2006.257.14:35:53.13$setupk4/echo=on 2006.257.14:35:53.13$setupk4/pcalon 2006.257.14:35:53.13$pcalon/"no phase cal control is implemented here 2006.257.14:35:53.13$setupk4/"tpicd=stop 2006.257.14:35:53.13$setupk4/"rec=synch_on 2006.257.14:35:53.13$setupk4/"rec_mode=128 2006.257.14:35:53.13$setupk4/!* 2006.257.14:35:53.13$setupk4/recpk4 2006.257.14:35:53.14$recpk4/recpatch= 2006.257.14:35:53.14$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:35:53.14$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:35:53.14$setupk4/vck44 2006.257.14:35:53.14$vck44/valo=1,524.99 2006.257.14:35:53.14#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.14:35:53.14#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.14:35:53.14#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:53.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:53.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:53.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:53.14#ibcon#enter wrdev, iclass 29, count 0 2006.257.14:35:53.14#ibcon#first serial, iclass 29, count 0 2006.257.14:35:53.14#ibcon#enter sib2, iclass 29, count 0 2006.257.14:35:53.14#ibcon#flushed, iclass 29, count 0 2006.257.14:35:53.14#ibcon#about to write, iclass 29, count 0 2006.257.14:35:53.14#ibcon#wrote, iclass 29, count 0 2006.257.14:35:53.14#ibcon#about to read 3, iclass 29, count 0 2006.257.14:35:53.15#ibcon#read 3, iclass 29, count 0 2006.257.14:35:53.15#ibcon#about to read 4, iclass 29, count 0 2006.257.14:35:53.15#ibcon#read 4, iclass 29, count 0 2006.257.14:35:53.15#ibcon#about to read 5, iclass 29, count 0 2006.257.14:35:53.15#ibcon#read 5, iclass 29, count 0 2006.257.14:35:53.15#ibcon#about to read 6, iclass 29, count 0 2006.257.14:35:53.15#ibcon#read 6, iclass 29, count 0 2006.257.14:35:53.15#ibcon#end of sib2, iclass 29, count 0 2006.257.14:35:53.15#ibcon#*mode == 0, iclass 29, count 0 2006.257.14:35:53.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.14:35:53.15#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:35:53.15#ibcon#*before write, iclass 29, count 0 2006.257.14:35:53.15#ibcon#enter sib2, iclass 29, count 0 2006.257.14:35:53.15#ibcon#flushed, iclass 29, count 0 2006.257.14:35:53.15#ibcon#about to write, iclass 29, count 0 2006.257.14:35:53.15#ibcon#wrote, iclass 29, count 0 2006.257.14:35:53.15#ibcon#about to read 3, iclass 29, count 0 2006.257.14:35:53.20#ibcon#read 3, iclass 29, count 0 2006.257.14:35:53.20#ibcon#about to read 4, iclass 29, count 0 2006.257.14:35:53.20#ibcon#read 4, iclass 29, count 0 2006.257.14:35:53.20#ibcon#about to read 5, iclass 29, count 0 2006.257.14:35:53.20#ibcon#read 5, iclass 29, count 0 2006.257.14:35:53.20#ibcon#about to read 6, iclass 29, count 0 2006.257.14:35:53.20#ibcon#read 6, iclass 29, count 0 2006.257.14:35:53.20#ibcon#end of sib2, iclass 29, count 0 2006.257.14:35:53.20#ibcon#*after write, iclass 29, count 0 2006.257.14:35:53.20#ibcon#*before return 0, iclass 29, count 0 2006.257.14:35:53.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:53.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:53.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.14:35:53.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.14:35:53.20$vck44/va=1,8 2006.257.14:35:53.20#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.14:35:53.20#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.14:35:53.20#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:53.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:53.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:53.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:53.20#ibcon#enter wrdev, iclass 31, count 2 2006.257.14:35:53.20#ibcon#first serial, iclass 31, count 2 2006.257.14:35:53.20#ibcon#enter sib2, iclass 31, count 2 2006.257.14:35:53.20#ibcon#flushed, iclass 31, count 2 2006.257.14:35:53.20#ibcon#about to write, iclass 31, count 2 2006.257.14:35:53.20#ibcon#wrote, iclass 31, count 2 2006.257.14:35:53.20#ibcon#about to read 3, iclass 31, count 2 2006.257.14:35:53.22#ibcon#read 3, iclass 31, count 2 2006.257.14:35:53.22#ibcon#about to read 4, iclass 31, count 2 2006.257.14:35:53.22#ibcon#read 4, iclass 31, count 2 2006.257.14:35:53.22#ibcon#about to read 5, iclass 31, count 2 2006.257.14:35:53.22#ibcon#read 5, iclass 31, count 2 2006.257.14:35:53.22#ibcon#about to read 6, iclass 31, count 2 2006.257.14:35:53.22#ibcon#read 6, iclass 31, count 2 2006.257.14:35:53.22#ibcon#end of sib2, iclass 31, count 2 2006.257.14:35:53.22#ibcon#*mode == 0, iclass 31, count 2 2006.257.14:35:53.22#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.14:35:53.22#ibcon#[25=AT01-08\r\n] 2006.257.14:35:53.22#ibcon#*before write, iclass 31, count 2 2006.257.14:35:53.22#ibcon#enter sib2, iclass 31, count 2 2006.257.14:35:53.22#ibcon#flushed, iclass 31, count 2 2006.257.14:35:53.22#ibcon#about to write, iclass 31, count 2 2006.257.14:35:53.22#ibcon#wrote, iclass 31, count 2 2006.257.14:35:53.22#ibcon#about to read 3, iclass 31, count 2 2006.257.14:35:53.25#ibcon#read 3, iclass 31, count 2 2006.257.14:35:53.25#ibcon#about to read 4, iclass 31, count 2 2006.257.14:35:53.25#ibcon#read 4, iclass 31, count 2 2006.257.14:35:53.25#ibcon#about to read 5, iclass 31, count 2 2006.257.14:35:53.25#ibcon#read 5, iclass 31, count 2 2006.257.14:35:53.25#ibcon#about to read 6, iclass 31, count 2 2006.257.14:35:53.25#ibcon#read 6, iclass 31, count 2 2006.257.14:35:53.25#ibcon#end of sib2, iclass 31, count 2 2006.257.14:35:53.25#ibcon#*after write, iclass 31, count 2 2006.257.14:35:53.25#ibcon#*before return 0, iclass 31, count 2 2006.257.14:35:53.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:53.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:53.25#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.14:35:53.25#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:53.25#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:53.37#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:53.37#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:53.37#ibcon#enter wrdev, iclass 31, count 0 2006.257.14:35:53.37#ibcon#first serial, iclass 31, count 0 2006.257.14:35:53.37#ibcon#enter sib2, iclass 31, count 0 2006.257.14:35:53.37#ibcon#flushed, iclass 31, count 0 2006.257.14:35:53.37#ibcon#about to write, iclass 31, count 0 2006.257.14:35:53.37#ibcon#wrote, iclass 31, count 0 2006.257.14:35:53.37#ibcon#about to read 3, iclass 31, count 0 2006.257.14:35:53.39#ibcon#read 3, iclass 31, count 0 2006.257.14:35:53.39#ibcon#about to read 4, iclass 31, count 0 2006.257.14:35:53.39#ibcon#read 4, iclass 31, count 0 2006.257.14:35:53.39#ibcon#about to read 5, iclass 31, count 0 2006.257.14:35:53.39#ibcon#read 5, iclass 31, count 0 2006.257.14:35:53.39#ibcon#about to read 6, iclass 31, count 0 2006.257.14:35:53.39#ibcon#read 6, iclass 31, count 0 2006.257.14:35:53.39#ibcon#end of sib2, iclass 31, count 0 2006.257.14:35:53.39#ibcon#*mode == 0, iclass 31, count 0 2006.257.14:35:53.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.14:35:53.39#ibcon#[25=USB\r\n] 2006.257.14:35:53.39#ibcon#*before write, iclass 31, count 0 2006.257.14:35:53.39#ibcon#enter sib2, iclass 31, count 0 2006.257.14:35:53.39#ibcon#flushed, iclass 31, count 0 2006.257.14:35:53.39#ibcon#about to write, iclass 31, count 0 2006.257.14:35:53.39#ibcon#wrote, iclass 31, count 0 2006.257.14:35:53.39#ibcon#about to read 3, iclass 31, count 0 2006.257.14:35:53.42#ibcon#read 3, iclass 31, count 0 2006.257.14:35:53.42#ibcon#about to read 4, iclass 31, count 0 2006.257.14:35:53.42#ibcon#read 4, iclass 31, count 0 2006.257.14:35:53.42#ibcon#about to read 5, iclass 31, count 0 2006.257.14:35:53.42#ibcon#read 5, iclass 31, count 0 2006.257.14:35:53.42#ibcon#about to read 6, iclass 31, count 0 2006.257.14:35:53.42#ibcon#read 6, iclass 31, count 0 2006.257.14:35:53.42#ibcon#end of sib2, iclass 31, count 0 2006.257.14:35:53.42#ibcon#*after write, iclass 31, count 0 2006.257.14:35:53.42#ibcon#*before return 0, iclass 31, count 0 2006.257.14:35:53.42#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:53.42#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:53.42#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.14:35:53.42#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.14:35:53.42$vck44/valo=2,534.99 2006.257.14:35:53.42#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.14:35:53.42#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.14:35:53.42#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:53.42#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:53.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:53.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:53.42#ibcon#enter wrdev, iclass 33, count 0 2006.257.14:35:53.42#ibcon#first serial, iclass 33, count 0 2006.257.14:35:53.42#ibcon#enter sib2, iclass 33, count 0 2006.257.14:35:53.42#ibcon#flushed, iclass 33, count 0 2006.257.14:35:53.42#ibcon#about to write, iclass 33, count 0 2006.257.14:35:53.42#ibcon#wrote, iclass 33, count 0 2006.257.14:35:53.42#ibcon#about to read 3, iclass 33, count 0 2006.257.14:35:53.44#ibcon#read 3, iclass 33, count 0 2006.257.14:35:53.44#ibcon#about to read 4, iclass 33, count 0 2006.257.14:35:53.44#ibcon#read 4, iclass 33, count 0 2006.257.14:35:53.44#ibcon#about to read 5, iclass 33, count 0 2006.257.14:35:53.44#ibcon#read 5, iclass 33, count 0 2006.257.14:35:53.44#ibcon#about to read 6, iclass 33, count 0 2006.257.14:35:53.44#ibcon#read 6, iclass 33, count 0 2006.257.14:35:53.44#ibcon#end of sib2, iclass 33, count 0 2006.257.14:35:53.44#ibcon#*mode == 0, iclass 33, count 0 2006.257.14:35:53.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.14:35:53.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:35:53.44#ibcon#*before write, iclass 33, count 0 2006.257.14:35:53.44#ibcon#enter sib2, iclass 33, count 0 2006.257.14:35:53.44#ibcon#flushed, iclass 33, count 0 2006.257.14:35:53.44#ibcon#about to write, iclass 33, count 0 2006.257.14:35:53.44#ibcon#wrote, iclass 33, count 0 2006.257.14:35:53.44#ibcon#about to read 3, iclass 33, count 0 2006.257.14:35:53.48#ibcon#read 3, iclass 33, count 0 2006.257.14:35:53.48#ibcon#about to read 4, iclass 33, count 0 2006.257.14:35:53.48#ibcon#read 4, iclass 33, count 0 2006.257.14:35:53.48#ibcon#about to read 5, iclass 33, count 0 2006.257.14:35:53.48#ibcon#read 5, iclass 33, count 0 2006.257.14:35:53.48#ibcon#about to read 6, iclass 33, count 0 2006.257.14:35:53.48#ibcon#read 6, iclass 33, count 0 2006.257.14:35:53.48#ibcon#end of sib2, iclass 33, count 0 2006.257.14:35:53.48#ibcon#*after write, iclass 33, count 0 2006.257.14:35:53.48#ibcon#*before return 0, iclass 33, count 0 2006.257.14:35:53.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:53.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:53.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.14:35:53.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.14:35:53.48$vck44/va=2,7 2006.257.14:35:53.48#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.14:35:53.48#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.14:35:53.48#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:53.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:53.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:53.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:53.54#ibcon#enter wrdev, iclass 35, count 2 2006.257.14:35:53.54#ibcon#first serial, iclass 35, count 2 2006.257.14:35:53.54#ibcon#enter sib2, iclass 35, count 2 2006.257.14:35:53.54#ibcon#flushed, iclass 35, count 2 2006.257.14:35:53.54#ibcon#about to write, iclass 35, count 2 2006.257.14:35:53.54#ibcon#wrote, iclass 35, count 2 2006.257.14:35:53.54#ibcon#about to read 3, iclass 35, count 2 2006.257.14:35:53.56#ibcon#read 3, iclass 35, count 2 2006.257.14:35:53.56#ibcon#about to read 4, iclass 35, count 2 2006.257.14:35:53.56#ibcon#read 4, iclass 35, count 2 2006.257.14:35:53.56#ibcon#about to read 5, iclass 35, count 2 2006.257.14:35:53.56#ibcon#read 5, iclass 35, count 2 2006.257.14:35:53.56#ibcon#about to read 6, iclass 35, count 2 2006.257.14:35:53.56#ibcon#read 6, iclass 35, count 2 2006.257.14:35:53.56#ibcon#end of sib2, iclass 35, count 2 2006.257.14:35:53.56#ibcon#*mode == 0, iclass 35, count 2 2006.257.14:35:53.56#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.14:35:53.56#ibcon#[25=AT02-07\r\n] 2006.257.14:35:53.56#ibcon#*before write, iclass 35, count 2 2006.257.14:35:53.56#ibcon#enter sib2, iclass 35, count 2 2006.257.14:35:53.56#ibcon#flushed, iclass 35, count 2 2006.257.14:35:53.56#ibcon#about to write, iclass 35, count 2 2006.257.14:35:53.56#ibcon#wrote, iclass 35, count 2 2006.257.14:35:53.56#ibcon#about to read 3, iclass 35, count 2 2006.257.14:35:53.59#ibcon#read 3, iclass 35, count 2 2006.257.14:35:53.59#ibcon#about to read 4, iclass 35, count 2 2006.257.14:35:53.59#ibcon#read 4, iclass 35, count 2 2006.257.14:35:53.59#ibcon#about to read 5, iclass 35, count 2 2006.257.14:35:53.59#ibcon#read 5, iclass 35, count 2 2006.257.14:35:53.59#ibcon#about to read 6, iclass 35, count 2 2006.257.14:35:53.59#ibcon#read 6, iclass 35, count 2 2006.257.14:35:53.59#ibcon#end of sib2, iclass 35, count 2 2006.257.14:35:53.59#ibcon#*after write, iclass 35, count 2 2006.257.14:35:53.59#ibcon#*before return 0, iclass 35, count 2 2006.257.14:35:53.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:53.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:53.59#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.14:35:53.59#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:53.59#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:53.71#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:53.71#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:53.71#ibcon#enter wrdev, iclass 35, count 0 2006.257.14:35:53.71#ibcon#first serial, iclass 35, count 0 2006.257.14:35:53.71#ibcon#enter sib2, iclass 35, count 0 2006.257.14:35:53.71#ibcon#flushed, iclass 35, count 0 2006.257.14:35:53.71#ibcon#about to write, iclass 35, count 0 2006.257.14:35:53.71#ibcon#wrote, iclass 35, count 0 2006.257.14:35:53.71#ibcon#about to read 3, iclass 35, count 0 2006.257.14:35:53.73#ibcon#read 3, iclass 35, count 0 2006.257.14:35:53.73#ibcon#about to read 4, iclass 35, count 0 2006.257.14:35:53.73#ibcon#read 4, iclass 35, count 0 2006.257.14:35:53.73#ibcon#about to read 5, iclass 35, count 0 2006.257.14:35:53.73#ibcon#read 5, iclass 35, count 0 2006.257.14:35:53.73#ibcon#about to read 6, iclass 35, count 0 2006.257.14:35:53.73#ibcon#read 6, iclass 35, count 0 2006.257.14:35:53.73#ibcon#end of sib2, iclass 35, count 0 2006.257.14:35:53.73#ibcon#*mode == 0, iclass 35, count 0 2006.257.14:35:53.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.14:35:53.73#ibcon#[25=USB\r\n] 2006.257.14:35:53.73#ibcon#*before write, iclass 35, count 0 2006.257.14:35:53.73#ibcon#enter sib2, iclass 35, count 0 2006.257.14:35:53.73#ibcon#flushed, iclass 35, count 0 2006.257.14:35:53.73#ibcon#about to write, iclass 35, count 0 2006.257.14:35:53.73#ibcon#wrote, iclass 35, count 0 2006.257.14:35:53.73#ibcon#about to read 3, iclass 35, count 0 2006.257.14:35:53.76#ibcon#read 3, iclass 35, count 0 2006.257.14:35:53.76#ibcon#about to read 4, iclass 35, count 0 2006.257.14:35:53.76#ibcon#read 4, iclass 35, count 0 2006.257.14:35:53.76#ibcon#about to read 5, iclass 35, count 0 2006.257.14:35:53.76#ibcon#read 5, iclass 35, count 0 2006.257.14:35:53.76#ibcon#about to read 6, iclass 35, count 0 2006.257.14:35:53.76#ibcon#read 6, iclass 35, count 0 2006.257.14:35:53.76#ibcon#end of sib2, iclass 35, count 0 2006.257.14:35:53.76#ibcon#*after write, iclass 35, count 0 2006.257.14:35:53.76#ibcon#*before return 0, iclass 35, count 0 2006.257.14:35:53.76#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:53.76#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:53.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.14:35:53.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.14:35:53.76$vck44/valo=3,564.99 2006.257.14:35:53.76#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.14:35:53.76#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.14:35:53.76#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:53.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:53.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:53.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:53.76#ibcon#enter wrdev, iclass 37, count 0 2006.257.14:35:53.76#ibcon#first serial, iclass 37, count 0 2006.257.14:35:53.76#ibcon#enter sib2, iclass 37, count 0 2006.257.14:35:53.76#ibcon#flushed, iclass 37, count 0 2006.257.14:35:53.76#ibcon#about to write, iclass 37, count 0 2006.257.14:35:53.76#ibcon#wrote, iclass 37, count 0 2006.257.14:35:53.76#ibcon#about to read 3, iclass 37, count 0 2006.257.14:35:53.78#ibcon#read 3, iclass 37, count 0 2006.257.14:35:53.78#ibcon#about to read 4, iclass 37, count 0 2006.257.14:35:53.78#ibcon#read 4, iclass 37, count 0 2006.257.14:35:53.78#ibcon#about to read 5, iclass 37, count 0 2006.257.14:35:53.78#ibcon#read 5, iclass 37, count 0 2006.257.14:35:53.78#ibcon#about to read 6, iclass 37, count 0 2006.257.14:35:53.78#ibcon#read 6, iclass 37, count 0 2006.257.14:35:53.78#ibcon#end of sib2, iclass 37, count 0 2006.257.14:35:53.78#ibcon#*mode == 0, iclass 37, count 0 2006.257.14:35:53.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.14:35:53.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:35:53.78#ibcon#*before write, iclass 37, count 0 2006.257.14:35:53.78#ibcon#enter sib2, iclass 37, count 0 2006.257.14:35:53.78#ibcon#flushed, iclass 37, count 0 2006.257.14:35:53.78#ibcon#about to write, iclass 37, count 0 2006.257.14:35:53.78#ibcon#wrote, iclass 37, count 0 2006.257.14:35:53.78#ibcon#about to read 3, iclass 37, count 0 2006.257.14:35:53.82#ibcon#read 3, iclass 37, count 0 2006.257.14:35:53.82#ibcon#about to read 4, iclass 37, count 0 2006.257.14:35:53.82#ibcon#read 4, iclass 37, count 0 2006.257.14:35:53.82#ibcon#about to read 5, iclass 37, count 0 2006.257.14:35:53.82#ibcon#read 5, iclass 37, count 0 2006.257.14:35:53.82#ibcon#about to read 6, iclass 37, count 0 2006.257.14:35:53.82#ibcon#read 6, iclass 37, count 0 2006.257.14:35:53.82#ibcon#end of sib2, iclass 37, count 0 2006.257.14:35:53.82#ibcon#*after write, iclass 37, count 0 2006.257.14:35:53.82#ibcon#*before return 0, iclass 37, count 0 2006.257.14:35:53.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:53.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:53.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.14:35:53.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.14:35:53.82$vck44/va=3,8 2006.257.14:35:53.82#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.14:35:53.82#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.14:35:53.82#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:53.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:53.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:53.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:53.88#ibcon#enter wrdev, iclass 39, count 2 2006.257.14:35:53.88#ibcon#first serial, iclass 39, count 2 2006.257.14:35:53.88#ibcon#enter sib2, iclass 39, count 2 2006.257.14:35:53.88#ibcon#flushed, iclass 39, count 2 2006.257.14:35:53.88#ibcon#about to write, iclass 39, count 2 2006.257.14:35:53.88#ibcon#wrote, iclass 39, count 2 2006.257.14:35:53.88#ibcon#about to read 3, iclass 39, count 2 2006.257.14:35:53.90#ibcon#read 3, iclass 39, count 2 2006.257.14:35:53.90#ibcon#about to read 4, iclass 39, count 2 2006.257.14:35:53.90#ibcon#read 4, iclass 39, count 2 2006.257.14:35:53.90#ibcon#about to read 5, iclass 39, count 2 2006.257.14:35:53.90#ibcon#read 5, iclass 39, count 2 2006.257.14:35:53.90#ibcon#about to read 6, iclass 39, count 2 2006.257.14:35:53.90#ibcon#read 6, iclass 39, count 2 2006.257.14:35:53.90#ibcon#end of sib2, iclass 39, count 2 2006.257.14:35:53.90#ibcon#*mode == 0, iclass 39, count 2 2006.257.14:35:53.90#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.14:35:53.90#ibcon#[25=AT03-08\r\n] 2006.257.14:35:53.90#ibcon#*before write, iclass 39, count 2 2006.257.14:35:53.90#ibcon#enter sib2, iclass 39, count 2 2006.257.14:35:53.90#ibcon#flushed, iclass 39, count 2 2006.257.14:35:53.90#ibcon#about to write, iclass 39, count 2 2006.257.14:35:53.90#ibcon#wrote, iclass 39, count 2 2006.257.14:35:53.90#ibcon#about to read 3, iclass 39, count 2 2006.257.14:35:53.93#ibcon#read 3, iclass 39, count 2 2006.257.14:35:53.93#ibcon#about to read 4, iclass 39, count 2 2006.257.14:35:53.93#ibcon#read 4, iclass 39, count 2 2006.257.14:35:53.93#ibcon#about to read 5, iclass 39, count 2 2006.257.14:35:53.93#ibcon#read 5, iclass 39, count 2 2006.257.14:35:53.93#ibcon#about to read 6, iclass 39, count 2 2006.257.14:35:53.93#ibcon#read 6, iclass 39, count 2 2006.257.14:35:53.93#ibcon#end of sib2, iclass 39, count 2 2006.257.14:35:53.93#ibcon#*after write, iclass 39, count 2 2006.257.14:35:53.93#ibcon#*before return 0, iclass 39, count 2 2006.257.14:35:53.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:53.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:53.93#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.14:35:53.93#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:53.93#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:54.05#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:54.05#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:54.05#ibcon#enter wrdev, iclass 39, count 0 2006.257.14:35:54.05#ibcon#first serial, iclass 39, count 0 2006.257.14:35:54.05#ibcon#enter sib2, iclass 39, count 0 2006.257.14:35:54.05#ibcon#flushed, iclass 39, count 0 2006.257.14:35:54.05#ibcon#about to write, iclass 39, count 0 2006.257.14:35:54.05#ibcon#wrote, iclass 39, count 0 2006.257.14:35:54.05#ibcon#about to read 3, iclass 39, count 0 2006.257.14:35:54.07#ibcon#read 3, iclass 39, count 0 2006.257.14:35:54.07#ibcon#about to read 4, iclass 39, count 0 2006.257.14:35:54.07#ibcon#read 4, iclass 39, count 0 2006.257.14:35:54.07#ibcon#about to read 5, iclass 39, count 0 2006.257.14:35:54.07#ibcon#read 5, iclass 39, count 0 2006.257.14:35:54.07#ibcon#about to read 6, iclass 39, count 0 2006.257.14:35:54.07#ibcon#read 6, iclass 39, count 0 2006.257.14:35:54.07#ibcon#end of sib2, iclass 39, count 0 2006.257.14:35:54.07#ibcon#*mode == 0, iclass 39, count 0 2006.257.14:35:54.07#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.14:35:54.07#ibcon#[25=USB\r\n] 2006.257.14:35:54.07#ibcon#*before write, iclass 39, count 0 2006.257.14:35:54.07#ibcon#enter sib2, iclass 39, count 0 2006.257.14:35:54.07#ibcon#flushed, iclass 39, count 0 2006.257.14:35:54.07#ibcon#about to write, iclass 39, count 0 2006.257.14:35:54.07#ibcon#wrote, iclass 39, count 0 2006.257.14:35:54.07#ibcon#about to read 3, iclass 39, count 0 2006.257.14:35:54.10#ibcon#read 3, iclass 39, count 0 2006.257.14:35:54.10#ibcon#about to read 4, iclass 39, count 0 2006.257.14:35:54.10#ibcon#read 4, iclass 39, count 0 2006.257.14:35:54.10#ibcon#about to read 5, iclass 39, count 0 2006.257.14:35:54.10#ibcon#read 5, iclass 39, count 0 2006.257.14:35:54.10#ibcon#about to read 6, iclass 39, count 0 2006.257.14:35:54.10#ibcon#read 6, iclass 39, count 0 2006.257.14:35:54.10#ibcon#end of sib2, iclass 39, count 0 2006.257.14:35:54.10#ibcon#*after write, iclass 39, count 0 2006.257.14:35:54.10#ibcon#*before return 0, iclass 39, count 0 2006.257.14:35:54.10#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:54.10#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:54.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.14:35:54.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.14:35:54.10$vck44/valo=4,624.99 2006.257.14:35:54.10#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.14:35:54.10#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.14:35:54.10#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:54.10#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:35:54.10#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:35:54.10#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:35:54.10#ibcon#enter wrdev, iclass 3, count 0 2006.257.14:35:54.10#ibcon#first serial, iclass 3, count 0 2006.257.14:35:54.10#ibcon#enter sib2, iclass 3, count 0 2006.257.14:35:54.10#ibcon#flushed, iclass 3, count 0 2006.257.14:35:54.10#ibcon#about to write, iclass 3, count 0 2006.257.14:35:54.10#ibcon#wrote, iclass 3, count 0 2006.257.14:35:54.10#ibcon#about to read 3, iclass 3, count 0 2006.257.14:35:54.12#ibcon#read 3, iclass 3, count 0 2006.257.14:35:54.12#ibcon#about to read 4, iclass 3, count 0 2006.257.14:35:54.12#ibcon#read 4, iclass 3, count 0 2006.257.14:35:54.12#ibcon#about to read 5, iclass 3, count 0 2006.257.14:35:54.12#ibcon#read 5, iclass 3, count 0 2006.257.14:35:54.12#ibcon#about to read 6, iclass 3, count 0 2006.257.14:35:54.12#ibcon#read 6, iclass 3, count 0 2006.257.14:35:54.12#ibcon#end of sib2, iclass 3, count 0 2006.257.14:35:54.12#ibcon#*mode == 0, iclass 3, count 0 2006.257.14:35:54.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.14:35:54.12#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:35:54.12#ibcon#*before write, iclass 3, count 0 2006.257.14:35:54.12#ibcon#enter sib2, iclass 3, count 0 2006.257.14:35:54.12#ibcon#flushed, iclass 3, count 0 2006.257.14:35:54.12#ibcon#about to write, iclass 3, count 0 2006.257.14:35:54.12#ibcon#wrote, iclass 3, count 0 2006.257.14:35:54.12#ibcon#about to read 3, iclass 3, count 0 2006.257.14:35:54.16#ibcon#read 3, iclass 3, count 0 2006.257.14:35:54.16#ibcon#about to read 4, iclass 3, count 0 2006.257.14:35:54.16#ibcon#read 4, iclass 3, count 0 2006.257.14:35:54.16#ibcon#about to read 5, iclass 3, count 0 2006.257.14:35:54.16#ibcon#read 5, iclass 3, count 0 2006.257.14:35:54.16#ibcon#about to read 6, iclass 3, count 0 2006.257.14:35:54.16#ibcon#read 6, iclass 3, count 0 2006.257.14:35:54.16#ibcon#end of sib2, iclass 3, count 0 2006.257.14:35:54.16#ibcon#*after write, iclass 3, count 0 2006.257.14:35:54.16#ibcon#*before return 0, iclass 3, count 0 2006.257.14:35:54.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:35:54.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.14:35:54.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.14:35:54.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.14:35:54.16$vck44/va=4,7 2006.257.14:35:54.16#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.14:35:54.16#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.14:35:54.16#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:54.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:35:54.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:35:54.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:35:54.22#ibcon#enter wrdev, iclass 5, count 2 2006.257.14:35:54.22#ibcon#first serial, iclass 5, count 2 2006.257.14:35:54.22#ibcon#enter sib2, iclass 5, count 2 2006.257.14:35:54.22#ibcon#flushed, iclass 5, count 2 2006.257.14:35:54.22#ibcon#about to write, iclass 5, count 2 2006.257.14:35:54.22#ibcon#wrote, iclass 5, count 2 2006.257.14:35:54.22#ibcon#about to read 3, iclass 5, count 2 2006.257.14:35:54.24#ibcon#read 3, iclass 5, count 2 2006.257.14:35:54.24#ibcon#about to read 4, iclass 5, count 2 2006.257.14:35:54.24#ibcon#read 4, iclass 5, count 2 2006.257.14:35:54.24#ibcon#about to read 5, iclass 5, count 2 2006.257.14:35:54.24#ibcon#read 5, iclass 5, count 2 2006.257.14:35:54.24#ibcon#about to read 6, iclass 5, count 2 2006.257.14:35:54.24#ibcon#read 6, iclass 5, count 2 2006.257.14:35:54.24#ibcon#end of sib2, iclass 5, count 2 2006.257.14:35:54.24#ibcon#*mode == 0, iclass 5, count 2 2006.257.14:35:54.24#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.14:35:54.24#ibcon#[25=AT04-07\r\n] 2006.257.14:35:54.24#ibcon#*before write, iclass 5, count 2 2006.257.14:35:54.24#ibcon#enter sib2, iclass 5, count 2 2006.257.14:35:54.24#ibcon#flushed, iclass 5, count 2 2006.257.14:35:54.24#ibcon#about to write, iclass 5, count 2 2006.257.14:35:54.24#ibcon#wrote, iclass 5, count 2 2006.257.14:35:54.24#ibcon#about to read 3, iclass 5, count 2 2006.257.14:35:54.27#ibcon#read 3, iclass 5, count 2 2006.257.14:35:54.27#ibcon#about to read 4, iclass 5, count 2 2006.257.14:35:54.27#ibcon#read 4, iclass 5, count 2 2006.257.14:35:54.27#ibcon#about to read 5, iclass 5, count 2 2006.257.14:35:54.27#ibcon#read 5, iclass 5, count 2 2006.257.14:35:54.27#ibcon#about to read 6, iclass 5, count 2 2006.257.14:35:54.27#ibcon#read 6, iclass 5, count 2 2006.257.14:35:54.27#ibcon#end of sib2, iclass 5, count 2 2006.257.14:35:54.27#ibcon#*after write, iclass 5, count 2 2006.257.14:35:54.27#ibcon#*before return 0, iclass 5, count 2 2006.257.14:35:54.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:35:54.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.14:35:54.27#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.14:35:54.27#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:54.27#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:35:54.39#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:35:54.39#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:35:54.39#ibcon#enter wrdev, iclass 5, count 0 2006.257.14:35:54.39#ibcon#first serial, iclass 5, count 0 2006.257.14:35:54.39#ibcon#enter sib2, iclass 5, count 0 2006.257.14:35:54.39#ibcon#flushed, iclass 5, count 0 2006.257.14:35:54.39#ibcon#about to write, iclass 5, count 0 2006.257.14:35:54.39#ibcon#wrote, iclass 5, count 0 2006.257.14:35:54.39#ibcon#about to read 3, iclass 5, count 0 2006.257.14:35:54.41#ibcon#read 3, iclass 5, count 0 2006.257.14:35:54.41#ibcon#about to read 4, iclass 5, count 0 2006.257.14:35:54.41#ibcon#read 4, iclass 5, count 0 2006.257.14:35:54.41#ibcon#about to read 5, iclass 5, count 0 2006.257.14:35:54.41#ibcon#read 5, iclass 5, count 0 2006.257.14:35:54.41#ibcon#about to read 6, iclass 5, count 0 2006.257.14:35:54.41#ibcon#read 6, iclass 5, count 0 2006.257.14:35:54.41#ibcon#end of sib2, iclass 5, count 0 2006.257.14:35:54.41#ibcon#*mode == 0, iclass 5, count 0 2006.257.14:35:54.41#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.14:35:54.41#ibcon#[25=USB\r\n] 2006.257.14:35:54.41#ibcon#*before write, iclass 5, count 0 2006.257.14:35:54.41#ibcon#enter sib2, iclass 5, count 0 2006.257.14:35:54.41#ibcon#flushed, iclass 5, count 0 2006.257.14:35:54.41#ibcon#about to write, iclass 5, count 0 2006.257.14:35:54.41#ibcon#wrote, iclass 5, count 0 2006.257.14:35:54.41#ibcon#about to read 3, iclass 5, count 0 2006.257.14:35:54.44#ibcon#read 3, iclass 5, count 0 2006.257.14:35:54.44#ibcon#about to read 4, iclass 5, count 0 2006.257.14:35:54.44#ibcon#read 4, iclass 5, count 0 2006.257.14:35:54.44#ibcon#about to read 5, iclass 5, count 0 2006.257.14:35:54.44#ibcon#read 5, iclass 5, count 0 2006.257.14:35:54.44#ibcon#about to read 6, iclass 5, count 0 2006.257.14:35:54.44#ibcon#read 6, iclass 5, count 0 2006.257.14:35:54.44#ibcon#end of sib2, iclass 5, count 0 2006.257.14:35:54.44#ibcon#*after write, iclass 5, count 0 2006.257.14:35:54.44#ibcon#*before return 0, iclass 5, count 0 2006.257.14:35:54.44#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:35:54.44#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.14:35:54.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.14:35:54.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.14:35:54.44$vck44/valo=5,734.99 2006.257.14:35:54.44#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.14:35:54.44#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.14:35:54.44#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:54.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:35:54.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:35:54.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:35:54.44#ibcon#enter wrdev, iclass 7, count 0 2006.257.14:35:54.44#ibcon#first serial, iclass 7, count 0 2006.257.14:35:54.44#ibcon#enter sib2, iclass 7, count 0 2006.257.14:35:54.44#ibcon#flushed, iclass 7, count 0 2006.257.14:35:54.44#ibcon#about to write, iclass 7, count 0 2006.257.14:35:54.44#ibcon#wrote, iclass 7, count 0 2006.257.14:35:54.44#ibcon#about to read 3, iclass 7, count 0 2006.257.14:35:54.46#ibcon#read 3, iclass 7, count 0 2006.257.14:35:54.46#ibcon#about to read 4, iclass 7, count 0 2006.257.14:35:54.46#ibcon#read 4, iclass 7, count 0 2006.257.14:35:54.46#ibcon#about to read 5, iclass 7, count 0 2006.257.14:35:54.46#ibcon#read 5, iclass 7, count 0 2006.257.14:35:54.46#ibcon#about to read 6, iclass 7, count 0 2006.257.14:35:54.46#ibcon#read 6, iclass 7, count 0 2006.257.14:35:54.46#ibcon#end of sib2, iclass 7, count 0 2006.257.14:35:54.46#ibcon#*mode == 0, iclass 7, count 0 2006.257.14:35:54.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.14:35:54.46#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:35:54.46#ibcon#*before write, iclass 7, count 0 2006.257.14:35:54.46#ibcon#enter sib2, iclass 7, count 0 2006.257.14:35:54.46#ibcon#flushed, iclass 7, count 0 2006.257.14:35:54.46#ibcon#about to write, iclass 7, count 0 2006.257.14:35:54.46#ibcon#wrote, iclass 7, count 0 2006.257.14:35:54.46#ibcon#about to read 3, iclass 7, count 0 2006.257.14:35:54.50#ibcon#read 3, iclass 7, count 0 2006.257.14:35:54.50#ibcon#about to read 4, iclass 7, count 0 2006.257.14:35:54.50#ibcon#read 4, iclass 7, count 0 2006.257.14:35:54.50#ibcon#about to read 5, iclass 7, count 0 2006.257.14:35:54.50#ibcon#read 5, iclass 7, count 0 2006.257.14:35:54.50#ibcon#about to read 6, iclass 7, count 0 2006.257.14:35:54.50#ibcon#read 6, iclass 7, count 0 2006.257.14:35:54.50#ibcon#end of sib2, iclass 7, count 0 2006.257.14:35:54.50#ibcon#*after write, iclass 7, count 0 2006.257.14:35:54.50#ibcon#*before return 0, iclass 7, count 0 2006.257.14:35:54.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:35:54.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.14:35:54.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.14:35:54.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.14:35:54.50$vck44/va=5,4 2006.257.14:35:54.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.14:35:54.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.14:35:54.50#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:54.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:54.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:54.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:54.56#ibcon#enter wrdev, iclass 11, count 2 2006.257.14:35:54.56#ibcon#first serial, iclass 11, count 2 2006.257.14:35:54.56#ibcon#enter sib2, iclass 11, count 2 2006.257.14:35:54.56#ibcon#flushed, iclass 11, count 2 2006.257.14:35:54.56#ibcon#about to write, iclass 11, count 2 2006.257.14:35:54.56#ibcon#wrote, iclass 11, count 2 2006.257.14:35:54.56#ibcon#about to read 3, iclass 11, count 2 2006.257.14:35:54.58#ibcon#read 3, iclass 11, count 2 2006.257.14:35:54.58#ibcon#about to read 4, iclass 11, count 2 2006.257.14:35:54.58#ibcon#read 4, iclass 11, count 2 2006.257.14:35:54.58#ibcon#about to read 5, iclass 11, count 2 2006.257.14:35:54.58#ibcon#read 5, iclass 11, count 2 2006.257.14:35:54.58#ibcon#about to read 6, iclass 11, count 2 2006.257.14:35:54.58#ibcon#read 6, iclass 11, count 2 2006.257.14:35:54.58#ibcon#end of sib2, iclass 11, count 2 2006.257.14:35:54.58#ibcon#*mode == 0, iclass 11, count 2 2006.257.14:35:54.58#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.14:35:54.58#ibcon#[25=AT05-04\r\n] 2006.257.14:35:54.58#ibcon#*before write, iclass 11, count 2 2006.257.14:35:54.58#ibcon#enter sib2, iclass 11, count 2 2006.257.14:35:54.58#ibcon#flushed, iclass 11, count 2 2006.257.14:35:54.58#ibcon#about to write, iclass 11, count 2 2006.257.14:35:54.58#ibcon#wrote, iclass 11, count 2 2006.257.14:35:54.58#ibcon#about to read 3, iclass 11, count 2 2006.257.14:35:54.61#ibcon#read 3, iclass 11, count 2 2006.257.14:35:54.61#ibcon#about to read 4, iclass 11, count 2 2006.257.14:35:54.61#ibcon#read 4, iclass 11, count 2 2006.257.14:35:54.61#ibcon#about to read 5, iclass 11, count 2 2006.257.14:35:54.61#ibcon#read 5, iclass 11, count 2 2006.257.14:35:54.61#ibcon#about to read 6, iclass 11, count 2 2006.257.14:35:54.61#ibcon#read 6, iclass 11, count 2 2006.257.14:35:54.61#ibcon#end of sib2, iclass 11, count 2 2006.257.14:35:54.61#ibcon#*after write, iclass 11, count 2 2006.257.14:35:54.61#ibcon#*before return 0, iclass 11, count 2 2006.257.14:35:54.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:54.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:54.61#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.14:35:54.61#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:54.61#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:54.73#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:54.73#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:54.73#ibcon#enter wrdev, iclass 11, count 0 2006.257.14:35:54.73#ibcon#first serial, iclass 11, count 0 2006.257.14:35:54.73#ibcon#enter sib2, iclass 11, count 0 2006.257.14:35:54.73#ibcon#flushed, iclass 11, count 0 2006.257.14:35:54.73#ibcon#about to write, iclass 11, count 0 2006.257.14:35:54.73#ibcon#wrote, iclass 11, count 0 2006.257.14:35:54.73#ibcon#about to read 3, iclass 11, count 0 2006.257.14:35:54.75#ibcon#read 3, iclass 11, count 0 2006.257.14:35:54.75#ibcon#about to read 4, iclass 11, count 0 2006.257.14:35:54.75#ibcon#read 4, iclass 11, count 0 2006.257.14:35:54.75#ibcon#about to read 5, iclass 11, count 0 2006.257.14:35:54.75#ibcon#read 5, iclass 11, count 0 2006.257.14:35:54.75#ibcon#about to read 6, iclass 11, count 0 2006.257.14:35:54.75#ibcon#read 6, iclass 11, count 0 2006.257.14:35:54.75#ibcon#end of sib2, iclass 11, count 0 2006.257.14:35:54.75#ibcon#*mode == 0, iclass 11, count 0 2006.257.14:35:54.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.14:35:54.75#ibcon#[25=USB\r\n] 2006.257.14:35:54.75#ibcon#*before write, iclass 11, count 0 2006.257.14:35:54.75#ibcon#enter sib2, iclass 11, count 0 2006.257.14:35:54.75#ibcon#flushed, iclass 11, count 0 2006.257.14:35:54.75#ibcon#about to write, iclass 11, count 0 2006.257.14:35:54.75#ibcon#wrote, iclass 11, count 0 2006.257.14:35:54.75#ibcon#about to read 3, iclass 11, count 0 2006.257.14:35:54.78#ibcon#read 3, iclass 11, count 0 2006.257.14:35:54.78#ibcon#about to read 4, iclass 11, count 0 2006.257.14:35:54.78#ibcon#read 4, iclass 11, count 0 2006.257.14:35:54.78#ibcon#about to read 5, iclass 11, count 0 2006.257.14:35:54.78#ibcon#read 5, iclass 11, count 0 2006.257.14:35:54.78#ibcon#about to read 6, iclass 11, count 0 2006.257.14:35:54.78#ibcon#read 6, iclass 11, count 0 2006.257.14:35:54.78#ibcon#end of sib2, iclass 11, count 0 2006.257.14:35:54.78#ibcon#*after write, iclass 11, count 0 2006.257.14:35:54.78#ibcon#*before return 0, iclass 11, count 0 2006.257.14:35:54.78#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:54.78#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:54.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.14:35:54.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.14:35:54.78$vck44/valo=6,814.99 2006.257.14:35:54.78#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.14:35:54.78#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.14:35:54.78#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:54.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:54.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:54.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:54.78#ibcon#enter wrdev, iclass 13, count 0 2006.257.14:35:54.78#ibcon#first serial, iclass 13, count 0 2006.257.14:35:54.78#ibcon#enter sib2, iclass 13, count 0 2006.257.14:35:54.78#ibcon#flushed, iclass 13, count 0 2006.257.14:35:54.78#ibcon#about to write, iclass 13, count 0 2006.257.14:35:54.78#ibcon#wrote, iclass 13, count 0 2006.257.14:35:54.78#ibcon#about to read 3, iclass 13, count 0 2006.257.14:35:54.80#ibcon#read 3, iclass 13, count 0 2006.257.14:35:54.80#ibcon#about to read 4, iclass 13, count 0 2006.257.14:35:54.80#ibcon#read 4, iclass 13, count 0 2006.257.14:35:54.80#ibcon#about to read 5, iclass 13, count 0 2006.257.14:35:54.80#ibcon#read 5, iclass 13, count 0 2006.257.14:35:54.80#ibcon#about to read 6, iclass 13, count 0 2006.257.14:35:54.80#ibcon#read 6, iclass 13, count 0 2006.257.14:35:54.80#ibcon#end of sib2, iclass 13, count 0 2006.257.14:35:54.80#ibcon#*mode == 0, iclass 13, count 0 2006.257.14:35:54.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.14:35:54.80#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:35:54.80#ibcon#*before write, iclass 13, count 0 2006.257.14:35:54.80#ibcon#enter sib2, iclass 13, count 0 2006.257.14:35:54.80#ibcon#flushed, iclass 13, count 0 2006.257.14:35:54.80#ibcon#about to write, iclass 13, count 0 2006.257.14:35:54.80#ibcon#wrote, iclass 13, count 0 2006.257.14:35:54.80#ibcon#about to read 3, iclass 13, count 0 2006.257.14:35:54.84#ibcon#read 3, iclass 13, count 0 2006.257.14:35:54.84#ibcon#about to read 4, iclass 13, count 0 2006.257.14:35:54.84#ibcon#read 4, iclass 13, count 0 2006.257.14:35:54.84#ibcon#about to read 5, iclass 13, count 0 2006.257.14:35:54.84#ibcon#read 5, iclass 13, count 0 2006.257.14:35:54.84#ibcon#about to read 6, iclass 13, count 0 2006.257.14:35:54.84#ibcon#read 6, iclass 13, count 0 2006.257.14:35:54.84#ibcon#end of sib2, iclass 13, count 0 2006.257.14:35:54.84#ibcon#*after write, iclass 13, count 0 2006.257.14:35:54.84#ibcon#*before return 0, iclass 13, count 0 2006.257.14:35:54.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:54.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:54.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.14:35:54.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.14:35:54.84$vck44/va=6,4 2006.257.14:35:54.84#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.14:35:54.84#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.14:35:54.84#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:54.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:54.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:54.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:54.90#ibcon#enter wrdev, iclass 15, count 2 2006.257.14:35:54.90#ibcon#first serial, iclass 15, count 2 2006.257.14:35:54.90#ibcon#enter sib2, iclass 15, count 2 2006.257.14:35:54.90#ibcon#flushed, iclass 15, count 2 2006.257.14:35:54.90#ibcon#about to write, iclass 15, count 2 2006.257.14:35:54.90#ibcon#wrote, iclass 15, count 2 2006.257.14:35:54.90#ibcon#about to read 3, iclass 15, count 2 2006.257.14:35:54.92#ibcon#read 3, iclass 15, count 2 2006.257.14:35:54.92#ibcon#about to read 4, iclass 15, count 2 2006.257.14:35:54.92#ibcon#read 4, iclass 15, count 2 2006.257.14:35:54.92#ibcon#about to read 5, iclass 15, count 2 2006.257.14:35:54.92#ibcon#read 5, iclass 15, count 2 2006.257.14:35:54.92#ibcon#about to read 6, iclass 15, count 2 2006.257.14:35:54.92#ibcon#read 6, iclass 15, count 2 2006.257.14:35:54.92#ibcon#end of sib2, iclass 15, count 2 2006.257.14:35:54.92#ibcon#*mode == 0, iclass 15, count 2 2006.257.14:35:54.92#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.14:35:54.92#ibcon#[25=AT06-04\r\n] 2006.257.14:35:54.92#ibcon#*before write, iclass 15, count 2 2006.257.14:35:54.92#ibcon#enter sib2, iclass 15, count 2 2006.257.14:35:54.92#ibcon#flushed, iclass 15, count 2 2006.257.14:35:54.92#ibcon#about to write, iclass 15, count 2 2006.257.14:35:54.92#ibcon#wrote, iclass 15, count 2 2006.257.14:35:54.92#ibcon#about to read 3, iclass 15, count 2 2006.257.14:35:54.95#ibcon#read 3, iclass 15, count 2 2006.257.14:35:54.95#ibcon#about to read 4, iclass 15, count 2 2006.257.14:35:54.95#ibcon#read 4, iclass 15, count 2 2006.257.14:35:54.95#ibcon#about to read 5, iclass 15, count 2 2006.257.14:35:54.95#ibcon#read 5, iclass 15, count 2 2006.257.14:35:54.95#ibcon#about to read 6, iclass 15, count 2 2006.257.14:35:54.95#ibcon#read 6, iclass 15, count 2 2006.257.14:35:54.95#ibcon#end of sib2, iclass 15, count 2 2006.257.14:35:54.95#ibcon#*after write, iclass 15, count 2 2006.257.14:35:54.95#ibcon#*before return 0, iclass 15, count 2 2006.257.14:35:54.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:54.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:54.95#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.14:35:54.95#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:54.95#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:55.07#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:55.07#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:55.07#ibcon#enter wrdev, iclass 15, count 0 2006.257.14:35:55.07#ibcon#first serial, iclass 15, count 0 2006.257.14:35:55.07#ibcon#enter sib2, iclass 15, count 0 2006.257.14:35:55.07#ibcon#flushed, iclass 15, count 0 2006.257.14:35:55.07#ibcon#about to write, iclass 15, count 0 2006.257.14:35:55.07#ibcon#wrote, iclass 15, count 0 2006.257.14:35:55.07#ibcon#about to read 3, iclass 15, count 0 2006.257.14:35:55.09#ibcon#read 3, iclass 15, count 0 2006.257.14:35:55.09#ibcon#about to read 4, iclass 15, count 0 2006.257.14:35:55.09#ibcon#read 4, iclass 15, count 0 2006.257.14:35:55.09#ibcon#about to read 5, iclass 15, count 0 2006.257.14:35:55.09#ibcon#read 5, iclass 15, count 0 2006.257.14:35:55.09#ibcon#about to read 6, iclass 15, count 0 2006.257.14:35:55.09#ibcon#read 6, iclass 15, count 0 2006.257.14:35:55.09#ibcon#end of sib2, iclass 15, count 0 2006.257.14:35:55.09#ibcon#*mode == 0, iclass 15, count 0 2006.257.14:35:55.09#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.14:35:55.09#ibcon#[25=USB\r\n] 2006.257.14:35:55.09#ibcon#*before write, iclass 15, count 0 2006.257.14:35:55.09#ibcon#enter sib2, iclass 15, count 0 2006.257.14:35:55.09#ibcon#flushed, iclass 15, count 0 2006.257.14:35:55.09#ibcon#about to write, iclass 15, count 0 2006.257.14:35:55.09#ibcon#wrote, iclass 15, count 0 2006.257.14:35:55.09#ibcon#about to read 3, iclass 15, count 0 2006.257.14:35:55.12#ibcon#read 3, iclass 15, count 0 2006.257.14:35:55.12#ibcon#about to read 4, iclass 15, count 0 2006.257.14:35:55.12#ibcon#read 4, iclass 15, count 0 2006.257.14:35:55.12#ibcon#about to read 5, iclass 15, count 0 2006.257.14:35:55.12#ibcon#read 5, iclass 15, count 0 2006.257.14:35:55.12#ibcon#about to read 6, iclass 15, count 0 2006.257.14:35:55.12#ibcon#read 6, iclass 15, count 0 2006.257.14:35:55.12#ibcon#end of sib2, iclass 15, count 0 2006.257.14:35:55.12#ibcon#*after write, iclass 15, count 0 2006.257.14:35:55.12#ibcon#*before return 0, iclass 15, count 0 2006.257.14:35:55.12#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:55.12#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:55.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.14:35:55.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.14:35:55.12$vck44/valo=7,864.99 2006.257.14:35:55.12#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.14:35:55.12#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.14:35:55.12#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:55.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:55.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:55.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:55.12#ibcon#enter wrdev, iclass 17, count 0 2006.257.14:35:55.12#ibcon#first serial, iclass 17, count 0 2006.257.14:35:55.12#ibcon#enter sib2, iclass 17, count 0 2006.257.14:35:55.12#ibcon#flushed, iclass 17, count 0 2006.257.14:35:55.12#ibcon#about to write, iclass 17, count 0 2006.257.14:35:55.12#ibcon#wrote, iclass 17, count 0 2006.257.14:35:55.12#ibcon#about to read 3, iclass 17, count 0 2006.257.14:35:55.14#ibcon#read 3, iclass 17, count 0 2006.257.14:35:55.14#ibcon#about to read 4, iclass 17, count 0 2006.257.14:35:55.14#ibcon#read 4, iclass 17, count 0 2006.257.14:35:55.14#ibcon#about to read 5, iclass 17, count 0 2006.257.14:35:55.14#ibcon#read 5, iclass 17, count 0 2006.257.14:35:55.14#ibcon#about to read 6, iclass 17, count 0 2006.257.14:35:55.14#ibcon#read 6, iclass 17, count 0 2006.257.14:35:55.14#ibcon#end of sib2, iclass 17, count 0 2006.257.14:35:55.14#ibcon#*mode == 0, iclass 17, count 0 2006.257.14:35:55.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.14:35:55.14#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:35:55.14#ibcon#*before write, iclass 17, count 0 2006.257.14:35:55.14#ibcon#enter sib2, iclass 17, count 0 2006.257.14:35:55.14#ibcon#flushed, iclass 17, count 0 2006.257.14:35:55.14#ibcon#about to write, iclass 17, count 0 2006.257.14:35:55.14#ibcon#wrote, iclass 17, count 0 2006.257.14:35:55.14#ibcon#about to read 3, iclass 17, count 0 2006.257.14:35:55.18#ibcon#read 3, iclass 17, count 0 2006.257.14:35:55.18#ibcon#about to read 4, iclass 17, count 0 2006.257.14:35:55.18#ibcon#read 4, iclass 17, count 0 2006.257.14:35:55.18#ibcon#about to read 5, iclass 17, count 0 2006.257.14:35:55.18#ibcon#read 5, iclass 17, count 0 2006.257.14:35:55.18#ibcon#about to read 6, iclass 17, count 0 2006.257.14:35:55.18#ibcon#read 6, iclass 17, count 0 2006.257.14:35:55.18#ibcon#end of sib2, iclass 17, count 0 2006.257.14:35:55.18#ibcon#*after write, iclass 17, count 0 2006.257.14:35:55.18#ibcon#*before return 0, iclass 17, count 0 2006.257.14:35:55.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:55.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:55.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.14:35:55.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.14:35:55.18$vck44/va=7,4 2006.257.14:35:55.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.14:35:55.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.14:35:55.18#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:55.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:55.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:55.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:55.24#ibcon#enter wrdev, iclass 19, count 2 2006.257.14:35:55.24#ibcon#first serial, iclass 19, count 2 2006.257.14:35:55.24#ibcon#enter sib2, iclass 19, count 2 2006.257.14:35:55.24#ibcon#flushed, iclass 19, count 2 2006.257.14:35:55.24#ibcon#about to write, iclass 19, count 2 2006.257.14:35:55.24#ibcon#wrote, iclass 19, count 2 2006.257.14:35:55.24#ibcon#about to read 3, iclass 19, count 2 2006.257.14:35:55.26#ibcon#read 3, iclass 19, count 2 2006.257.14:35:55.26#ibcon#about to read 4, iclass 19, count 2 2006.257.14:35:55.26#ibcon#read 4, iclass 19, count 2 2006.257.14:35:55.26#ibcon#about to read 5, iclass 19, count 2 2006.257.14:35:55.26#ibcon#read 5, iclass 19, count 2 2006.257.14:35:55.26#ibcon#about to read 6, iclass 19, count 2 2006.257.14:35:55.26#ibcon#read 6, iclass 19, count 2 2006.257.14:35:55.26#ibcon#end of sib2, iclass 19, count 2 2006.257.14:35:55.26#ibcon#*mode == 0, iclass 19, count 2 2006.257.14:35:55.26#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.14:35:55.26#ibcon#[25=AT07-04\r\n] 2006.257.14:35:55.26#ibcon#*before write, iclass 19, count 2 2006.257.14:35:55.26#ibcon#enter sib2, iclass 19, count 2 2006.257.14:35:55.26#ibcon#flushed, iclass 19, count 2 2006.257.14:35:55.26#ibcon#about to write, iclass 19, count 2 2006.257.14:35:55.26#ibcon#wrote, iclass 19, count 2 2006.257.14:35:55.26#ibcon#about to read 3, iclass 19, count 2 2006.257.14:35:55.29#ibcon#read 3, iclass 19, count 2 2006.257.14:35:55.29#ibcon#about to read 4, iclass 19, count 2 2006.257.14:35:55.29#ibcon#read 4, iclass 19, count 2 2006.257.14:35:55.29#ibcon#about to read 5, iclass 19, count 2 2006.257.14:35:55.29#ibcon#read 5, iclass 19, count 2 2006.257.14:35:55.29#ibcon#about to read 6, iclass 19, count 2 2006.257.14:35:55.29#ibcon#read 6, iclass 19, count 2 2006.257.14:35:55.29#ibcon#end of sib2, iclass 19, count 2 2006.257.14:35:55.29#ibcon#*after write, iclass 19, count 2 2006.257.14:35:55.29#ibcon#*before return 0, iclass 19, count 2 2006.257.14:35:55.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:55.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:55.29#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.14:35:55.29#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:55.29#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:55.41#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:55.41#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:55.41#ibcon#enter wrdev, iclass 19, count 0 2006.257.14:35:55.41#ibcon#first serial, iclass 19, count 0 2006.257.14:35:55.41#ibcon#enter sib2, iclass 19, count 0 2006.257.14:35:55.41#ibcon#flushed, iclass 19, count 0 2006.257.14:35:55.41#ibcon#about to write, iclass 19, count 0 2006.257.14:35:55.41#ibcon#wrote, iclass 19, count 0 2006.257.14:35:55.41#ibcon#about to read 3, iclass 19, count 0 2006.257.14:35:55.43#ibcon#read 3, iclass 19, count 0 2006.257.14:35:55.43#ibcon#about to read 4, iclass 19, count 0 2006.257.14:35:55.43#ibcon#read 4, iclass 19, count 0 2006.257.14:35:55.43#ibcon#about to read 5, iclass 19, count 0 2006.257.14:35:55.43#ibcon#read 5, iclass 19, count 0 2006.257.14:35:55.43#ibcon#about to read 6, iclass 19, count 0 2006.257.14:35:55.43#ibcon#read 6, iclass 19, count 0 2006.257.14:35:55.43#ibcon#end of sib2, iclass 19, count 0 2006.257.14:35:55.43#ibcon#*mode == 0, iclass 19, count 0 2006.257.14:35:55.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.14:35:55.43#ibcon#[25=USB\r\n] 2006.257.14:35:55.43#ibcon#*before write, iclass 19, count 0 2006.257.14:35:55.43#ibcon#enter sib2, iclass 19, count 0 2006.257.14:35:55.43#ibcon#flushed, iclass 19, count 0 2006.257.14:35:55.43#ibcon#about to write, iclass 19, count 0 2006.257.14:35:55.43#ibcon#wrote, iclass 19, count 0 2006.257.14:35:55.43#ibcon#about to read 3, iclass 19, count 0 2006.257.14:35:55.46#ibcon#read 3, iclass 19, count 0 2006.257.14:35:55.46#ibcon#about to read 4, iclass 19, count 0 2006.257.14:35:55.46#ibcon#read 4, iclass 19, count 0 2006.257.14:35:55.46#ibcon#about to read 5, iclass 19, count 0 2006.257.14:35:55.46#ibcon#read 5, iclass 19, count 0 2006.257.14:35:55.46#ibcon#about to read 6, iclass 19, count 0 2006.257.14:35:55.46#ibcon#read 6, iclass 19, count 0 2006.257.14:35:55.46#ibcon#end of sib2, iclass 19, count 0 2006.257.14:35:55.46#ibcon#*after write, iclass 19, count 0 2006.257.14:35:55.46#ibcon#*before return 0, iclass 19, count 0 2006.257.14:35:55.46#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:55.46#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:55.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.14:35:55.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.14:35:55.46$vck44/valo=8,884.99 2006.257.14:35:55.46#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.14:35:55.46#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.14:35:55.46#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:55.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:55.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:55.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:55.46#ibcon#enter wrdev, iclass 21, count 0 2006.257.14:35:55.46#ibcon#first serial, iclass 21, count 0 2006.257.14:35:55.46#ibcon#enter sib2, iclass 21, count 0 2006.257.14:35:55.46#ibcon#flushed, iclass 21, count 0 2006.257.14:35:55.46#ibcon#about to write, iclass 21, count 0 2006.257.14:35:55.46#ibcon#wrote, iclass 21, count 0 2006.257.14:35:55.46#ibcon#about to read 3, iclass 21, count 0 2006.257.14:35:55.48#ibcon#read 3, iclass 21, count 0 2006.257.14:35:55.48#ibcon#about to read 4, iclass 21, count 0 2006.257.14:35:55.48#ibcon#read 4, iclass 21, count 0 2006.257.14:35:55.48#ibcon#about to read 5, iclass 21, count 0 2006.257.14:35:55.48#ibcon#read 5, iclass 21, count 0 2006.257.14:35:55.48#ibcon#about to read 6, iclass 21, count 0 2006.257.14:35:55.48#ibcon#read 6, iclass 21, count 0 2006.257.14:35:55.48#ibcon#end of sib2, iclass 21, count 0 2006.257.14:35:55.48#ibcon#*mode == 0, iclass 21, count 0 2006.257.14:35:55.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.14:35:55.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:35:55.48#ibcon#*before write, iclass 21, count 0 2006.257.14:35:55.48#ibcon#enter sib2, iclass 21, count 0 2006.257.14:35:55.48#ibcon#flushed, iclass 21, count 0 2006.257.14:35:55.48#ibcon#about to write, iclass 21, count 0 2006.257.14:35:55.48#ibcon#wrote, iclass 21, count 0 2006.257.14:35:55.48#ibcon#about to read 3, iclass 21, count 0 2006.257.14:35:55.52#ibcon#read 3, iclass 21, count 0 2006.257.14:35:55.52#ibcon#about to read 4, iclass 21, count 0 2006.257.14:35:55.52#ibcon#read 4, iclass 21, count 0 2006.257.14:35:55.52#ibcon#about to read 5, iclass 21, count 0 2006.257.14:35:55.52#ibcon#read 5, iclass 21, count 0 2006.257.14:35:55.52#ibcon#about to read 6, iclass 21, count 0 2006.257.14:35:55.52#ibcon#read 6, iclass 21, count 0 2006.257.14:35:55.52#ibcon#end of sib2, iclass 21, count 0 2006.257.14:35:55.52#ibcon#*after write, iclass 21, count 0 2006.257.14:35:55.52#ibcon#*before return 0, iclass 21, count 0 2006.257.14:35:55.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:55.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:55.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.14:35:55.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.14:35:55.52$vck44/va=8,4 2006.257.14:35:55.52#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.14:35:55.52#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.14:35:55.52#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:55.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:55.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:55.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:55.58#ibcon#enter wrdev, iclass 23, count 2 2006.257.14:35:55.58#ibcon#first serial, iclass 23, count 2 2006.257.14:35:55.58#ibcon#enter sib2, iclass 23, count 2 2006.257.14:35:55.58#ibcon#flushed, iclass 23, count 2 2006.257.14:35:55.58#ibcon#about to write, iclass 23, count 2 2006.257.14:35:55.58#ibcon#wrote, iclass 23, count 2 2006.257.14:35:55.58#ibcon#about to read 3, iclass 23, count 2 2006.257.14:35:55.60#ibcon#read 3, iclass 23, count 2 2006.257.14:35:55.60#ibcon#about to read 4, iclass 23, count 2 2006.257.14:35:55.60#ibcon#read 4, iclass 23, count 2 2006.257.14:35:55.60#ibcon#about to read 5, iclass 23, count 2 2006.257.14:35:55.60#ibcon#read 5, iclass 23, count 2 2006.257.14:35:55.60#ibcon#about to read 6, iclass 23, count 2 2006.257.14:35:55.60#ibcon#read 6, iclass 23, count 2 2006.257.14:35:55.60#ibcon#end of sib2, iclass 23, count 2 2006.257.14:35:55.60#ibcon#*mode == 0, iclass 23, count 2 2006.257.14:35:55.60#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.14:35:55.60#ibcon#[25=AT08-04\r\n] 2006.257.14:35:55.60#ibcon#*before write, iclass 23, count 2 2006.257.14:35:55.60#ibcon#enter sib2, iclass 23, count 2 2006.257.14:35:55.60#ibcon#flushed, iclass 23, count 2 2006.257.14:35:55.60#ibcon#about to write, iclass 23, count 2 2006.257.14:35:55.60#ibcon#wrote, iclass 23, count 2 2006.257.14:35:55.60#ibcon#about to read 3, iclass 23, count 2 2006.257.14:35:55.63#ibcon#read 3, iclass 23, count 2 2006.257.14:35:55.63#ibcon#about to read 4, iclass 23, count 2 2006.257.14:35:55.63#ibcon#read 4, iclass 23, count 2 2006.257.14:35:55.63#ibcon#about to read 5, iclass 23, count 2 2006.257.14:35:55.63#ibcon#read 5, iclass 23, count 2 2006.257.14:35:55.63#ibcon#about to read 6, iclass 23, count 2 2006.257.14:35:55.63#ibcon#read 6, iclass 23, count 2 2006.257.14:35:55.63#ibcon#end of sib2, iclass 23, count 2 2006.257.14:35:55.63#ibcon#*after write, iclass 23, count 2 2006.257.14:35:55.63#ibcon#*before return 0, iclass 23, count 2 2006.257.14:35:55.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:55.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:55.63#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.14:35:55.63#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:55.63#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:55.75#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:55.75#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:55.75#ibcon#enter wrdev, iclass 23, count 0 2006.257.14:35:55.75#ibcon#first serial, iclass 23, count 0 2006.257.14:35:55.75#ibcon#enter sib2, iclass 23, count 0 2006.257.14:35:55.75#ibcon#flushed, iclass 23, count 0 2006.257.14:35:55.75#ibcon#about to write, iclass 23, count 0 2006.257.14:35:55.75#ibcon#wrote, iclass 23, count 0 2006.257.14:35:55.75#ibcon#about to read 3, iclass 23, count 0 2006.257.14:35:55.77#ibcon#read 3, iclass 23, count 0 2006.257.14:35:55.77#ibcon#about to read 4, iclass 23, count 0 2006.257.14:35:55.77#ibcon#read 4, iclass 23, count 0 2006.257.14:35:55.77#ibcon#about to read 5, iclass 23, count 0 2006.257.14:35:55.77#ibcon#read 5, iclass 23, count 0 2006.257.14:35:55.77#ibcon#about to read 6, iclass 23, count 0 2006.257.14:35:55.77#ibcon#read 6, iclass 23, count 0 2006.257.14:35:55.77#ibcon#end of sib2, iclass 23, count 0 2006.257.14:35:55.77#ibcon#*mode == 0, iclass 23, count 0 2006.257.14:35:55.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.14:35:55.77#ibcon#[25=USB\r\n] 2006.257.14:35:55.77#ibcon#*before write, iclass 23, count 0 2006.257.14:35:55.77#ibcon#enter sib2, iclass 23, count 0 2006.257.14:35:55.77#ibcon#flushed, iclass 23, count 0 2006.257.14:35:55.77#ibcon#about to write, iclass 23, count 0 2006.257.14:35:55.77#ibcon#wrote, iclass 23, count 0 2006.257.14:35:55.77#ibcon#about to read 3, iclass 23, count 0 2006.257.14:35:55.80#ibcon#read 3, iclass 23, count 0 2006.257.14:35:55.80#ibcon#about to read 4, iclass 23, count 0 2006.257.14:35:55.80#ibcon#read 4, iclass 23, count 0 2006.257.14:35:55.80#ibcon#about to read 5, iclass 23, count 0 2006.257.14:35:55.80#ibcon#read 5, iclass 23, count 0 2006.257.14:35:55.80#ibcon#about to read 6, iclass 23, count 0 2006.257.14:35:55.80#ibcon#read 6, iclass 23, count 0 2006.257.14:35:55.80#ibcon#end of sib2, iclass 23, count 0 2006.257.14:35:55.80#ibcon#*after write, iclass 23, count 0 2006.257.14:35:55.80#ibcon#*before return 0, iclass 23, count 0 2006.257.14:35:55.80#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:55.80#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:55.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.14:35:55.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.14:35:55.80$vck44/vblo=1,629.99 2006.257.14:35:55.80#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.14:35:55.80#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.14:35:55.80#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:55.80#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:55.80#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:55.80#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:55.80#ibcon#enter wrdev, iclass 25, count 0 2006.257.14:35:55.80#ibcon#first serial, iclass 25, count 0 2006.257.14:35:55.80#ibcon#enter sib2, iclass 25, count 0 2006.257.14:35:55.80#ibcon#flushed, iclass 25, count 0 2006.257.14:35:55.80#ibcon#about to write, iclass 25, count 0 2006.257.14:35:55.80#ibcon#wrote, iclass 25, count 0 2006.257.14:35:55.80#ibcon#about to read 3, iclass 25, count 0 2006.257.14:35:55.82#ibcon#read 3, iclass 25, count 0 2006.257.14:35:55.82#ibcon#about to read 4, iclass 25, count 0 2006.257.14:35:55.82#ibcon#read 4, iclass 25, count 0 2006.257.14:35:55.82#ibcon#about to read 5, iclass 25, count 0 2006.257.14:35:55.82#ibcon#read 5, iclass 25, count 0 2006.257.14:35:55.82#ibcon#about to read 6, iclass 25, count 0 2006.257.14:35:55.82#ibcon#read 6, iclass 25, count 0 2006.257.14:35:55.82#ibcon#end of sib2, iclass 25, count 0 2006.257.14:35:55.82#ibcon#*mode == 0, iclass 25, count 0 2006.257.14:35:55.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.14:35:55.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:35:55.82#ibcon#*before write, iclass 25, count 0 2006.257.14:35:55.82#ibcon#enter sib2, iclass 25, count 0 2006.257.14:35:55.82#ibcon#flushed, iclass 25, count 0 2006.257.14:35:55.82#ibcon#about to write, iclass 25, count 0 2006.257.14:35:55.82#ibcon#wrote, iclass 25, count 0 2006.257.14:35:55.82#ibcon#about to read 3, iclass 25, count 0 2006.257.14:35:55.86#ibcon#read 3, iclass 25, count 0 2006.257.14:35:55.86#ibcon#about to read 4, iclass 25, count 0 2006.257.14:35:55.86#ibcon#read 4, iclass 25, count 0 2006.257.14:35:55.86#ibcon#about to read 5, iclass 25, count 0 2006.257.14:35:55.86#ibcon#read 5, iclass 25, count 0 2006.257.14:35:55.86#ibcon#about to read 6, iclass 25, count 0 2006.257.14:35:55.86#ibcon#read 6, iclass 25, count 0 2006.257.14:35:55.86#ibcon#end of sib2, iclass 25, count 0 2006.257.14:35:55.86#ibcon#*after write, iclass 25, count 0 2006.257.14:35:55.86#ibcon#*before return 0, iclass 25, count 0 2006.257.14:35:55.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:55.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:55.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.14:35:55.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.14:35:55.86$vck44/vb=1,4 2006.257.14:35:55.86#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.14:35:55.86#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.14:35:55.86#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:55.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:35:55.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:35:55.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:35:55.86#ibcon#enter wrdev, iclass 27, count 2 2006.257.14:35:55.86#ibcon#first serial, iclass 27, count 2 2006.257.14:35:55.86#ibcon#enter sib2, iclass 27, count 2 2006.257.14:35:55.86#ibcon#flushed, iclass 27, count 2 2006.257.14:35:55.86#ibcon#about to write, iclass 27, count 2 2006.257.14:35:55.86#ibcon#wrote, iclass 27, count 2 2006.257.14:35:55.86#ibcon#about to read 3, iclass 27, count 2 2006.257.14:35:55.88#ibcon#read 3, iclass 27, count 2 2006.257.14:35:55.88#ibcon#about to read 4, iclass 27, count 2 2006.257.14:35:55.88#ibcon#read 4, iclass 27, count 2 2006.257.14:35:55.88#ibcon#about to read 5, iclass 27, count 2 2006.257.14:35:55.88#ibcon#read 5, iclass 27, count 2 2006.257.14:35:55.88#ibcon#about to read 6, iclass 27, count 2 2006.257.14:35:55.88#ibcon#read 6, iclass 27, count 2 2006.257.14:35:55.88#ibcon#end of sib2, iclass 27, count 2 2006.257.14:35:55.88#ibcon#*mode == 0, iclass 27, count 2 2006.257.14:35:55.88#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.14:35:55.88#ibcon#[27=AT01-04\r\n] 2006.257.14:35:55.88#ibcon#*before write, iclass 27, count 2 2006.257.14:35:55.88#ibcon#enter sib2, iclass 27, count 2 2006.257.14:35:55.88#ibcon#flushed, iclass 27, count 2 2006.257.14:35:55.88#ibcon#about to write, iclass 27, count 2 2006.257.14:35:55.88#ibcon#wrote, iclass 27, count 2 2006.257.14:35:55.88#ibcon#about to read 3, iclass 27, count 2 2006.257.14:35:55.91#ibcon#read 3, iclass 27, count 2 2006.257.14:35:55.91#ibcon#about to read 4, iclass 27, count 2 2006.257.14:35:55.91#ibcon#read 4, iclass 27, count 2 2006.257.14:35:55.91#ibcon#about to read 5, iclass 27, count 2 2006.257.14:35:55.91#ibcon#read 5, iclass 27, count 2 2006.257.14:35:55.91#ibcon#about to read 6, iclass 27, count 2 2006.257.14:35:55.91#ibcon#read 6, iclass 27, count 2 2006.257.14:35:55.91#ibcon#end of sib2, iclass 27, count 2 2006.257.14:35:55.91#ibcon#*after write, iclass 27, count 2 2006.257.14:35:55.91#ibcon#*before return 0, iclass 27, count 2 2006.257.14:35:55.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:35:55.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.14:35:55.91#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.14:35:55.91#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:55.91#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:35:56.03#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:35:56.03#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:35:56.03#ibcon#enter wrdev, iclass 27, count 0 2006.257.14:35:56.03#ibcon#first serial, iclass 27, count 0 2006.257.14:35:56.03#ibcon#enter sib2, iclass 27, count 0 2006.257.14:35:56.03#ibcon#flushed, iclass 27, count 0 2006.257.14:35:56.03#ibcon#about to write, iclass 27, count 0 2006.257.14:35:56.03#ibcon#wrote, iclass 27, count 0 2006.257.14:35:56.03#ibcon#about to read 3, iclass 27, count 0 2006.257.14:35:56.05#ibcon#read 3, iclass 27, count 0 2006.257.14:35:56.05#ibcon#about to read 4, iclass 27, count 0 2006.257.14:35:56.05#ibcon#read 4, iclass 27, count 0 2006.257.14:35:56.05#ibcon#about to read 5, iclass 27, count 0 2006.257.14:35:56.05#ibcon#read 5, iclass 27, count 0 2006.257.14:35:56.05#ibcon#about to read 6, iclass 27, count 0 2006.257.14:35:56.05#ibcon#read 6, iclass 27, count 0 2006.257.14:35:56.05#ibcon#end of sib2, iclass 27, count 0 2006.257.14:35:56.05#ibcon#*mode == 0, iclass 27, count 0 2006.257.14:35:56.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.14:35:56.05#ibcon#[27=USB\r\n] 2006.257.14:35:56.05#ibcon#*before write, iclass 27, count 0 2006.257.14:35:56.05#ibcon#enter sib2, iclass 27, count 0 2006.257.14:35:56.05#ibcon#flushed, iclass 27, count 0 2006.257.14:35:56.05#ibcon#about to write, iclass 27, count 0 2006.257.14:35:56.05#ibcon#wrote, iclass 27, count 0 2006.257.14:35:56.05#ibcon#about to read 3, iclass 27, count 0 2006.257.14:35:56.08#ibcon#read 3, iclass 27, count 0 2006.257.14:35:56.08#ibcon#about to read 4, iclass 27, count 0 2006.257.14:35:56.08#ibcon#read 4, iclass 27, count 0 2006.257.14:35:56.08#ibcon#about to read 5, iclass 27, count 0 2006.257.14:35:56.08#ibcon#read 5, iclass 27, count 0 2006.257.14:35:56.08#ibcon#about to read 6, iclass 27, count 0 2006.257.14:35:56.08#ibcon#read 6, iclass 27, count 0 2006.257.14:35:56.08#ibcon#end of sib2, iclass 27, count 0 2006.257.14:35:56.08#ibcon#*after write, iclass 27, count 0 2006.257.14:35:56.08#ibcon#*before return 0, iclass 27, count 0 2006.257.14:35:56.08#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:35:56.08#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.14:35:56.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.14:35:56.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.14:35:56.08$vck44/vblo=2,634.99 2006.257.14:35:56.08#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.14:35:56.08#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.14:35:56.08#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:56.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:56.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:56.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:56.08#ibcon#enter wrdev, iclass 29, count 0 2006.257.14:35:56.08#ibcon#first serial, iclass 29, count 0 2006.257.14:35:56.08#ibcon#enter sib2, iclass 29, count 0 2006.257.14:35:56.08#ibcon#flushed, iclass 29, count 0 2006.257.14:35:56.08#ibcon#about to write, iclass 29, count 0 2006.257.14:35:56.08#ibcon#wrote, iclass 29, count 0 2006.257.14:35:56.08#ibcon#about to read 3, iclass 29, count 0 2006.257.14:35:56.10#ibcon#read 3, iclass 29, count 0 2006.257.14:35:56.10#ibcon#about to read 4, iclass 29, count 0 2006.257.14:35:56.10#ibcon#read 4, iclass 29, count 0 2006.257.14:35:56.10#ibcon#about to read 5, iclass 29, count 0 2006.257.14:35:56.10#ibcon#read 5, iclass 29, count 0 2006.257.14:35:56.10#ibcon#about to read 6, iclass 29, count 0 2006.257.14:35:56.10#ibcon#read 6, iclass 29, count 0 2006.257.14:35:56.10#ibcon#end of sib2, iclass 29, count 0 2006.257.14:35:56.10#ibcon#*mode == 0, iclass 29, count 0 2006.257.14:35:56.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.14:35:56.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:35:56.10#ibcon#*before write, iclass 29, count 0 2006.257.14:35:56.10#ibcon#enter sib2, iclass 29, count 0 2006.257.14:35:56.10#ibcon#flushed, iclass 29, count 0 2006.257.14:35:56.10#ibcon#about to write, iclass 29, count 0 2006.257.14:35:56.10#ibcon#wrote, iclass 29, count 0 2006.257.14:35:56.10#ibcon#about to read 3, iclass 29, count 0 2006.257.14:35:56.14#ibcon#read 3, iclass 29, count 0 2006.257.14:35:56.14#ibcon#about to read 4, iclass 29, count 0 2006.257.14:35:56.14#ibcon#read 4, iclass 29, count 0 2006.257.14:35:56.14#ibcon#about to read 5, iclass 29, count 0 2006.257.14:35:56.14#ibcon#read 5, iclass 29, count 0 2006.257.14:35:56.14#ibcon#about to read 6, iclass 29, count 0 2006.257.14:35:56.14#ibcon#read 6, iclass 29, count 0 2006.257.14:35:56.14#ibcon#end of sib2, iclass 29, count 0 2006.257.14:35:56.14#ibcon#*after write, iclass 29, count 0 2006.257.14:35:56.14#ibcon#*before return 0, iclass 29, count 0 2006.257.14:35:56.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:56.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.14:35:56.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.14:35:56.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.14:35:56.14$vck44/vb=2,5 2006.257.14:35:56.14#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.14:35:56.14#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.14:35:56.14#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:56.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:56.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:56.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:56.20#ibcon#enter wrdev, iclass 31, count 2 2006.257.14:35:56.20#ibcon#first serial, iclass 31, count 2 2006.257.14:35:56.20#ibcon#enter sib2, iclass 31, count 2 2006.257.14:35:56.20#ibcon#flushed, iclass 31, count 2 2006.257.14:35:56.20#ibcon#about to write, iclass 31, count 2 2006.257.14:35:56.20#ibcon#wrote, iclass 31, count 2 2006.257.14:35:56.20#ibcon#about to read 3, iclass 31, count 2 2006.257.14:35:56.22#ibcon#read 3, iclass 31, count 2 2006.257.14:35:56.22#ibcon#about to read 4, iclass 31, count 2 2006.257.14:35:56.22#ibcon#read 4, iclass 31, count 2 2006.257.14:35:56.22#ibcon#about to read 5, iclass 31, count 2 2006.257.14:35:56.22#ibcon#read 5, iclass 31, count 2 2006.257.14:35:56.22#ibcon#about to read 6, iclass 31, count 2 2006.257.14:35:56.22#ibcon#read 6, iclass 31, count 2 2006.257.14:35:56.22#ibcon#end of sib2, iclass 31, count 2 2006.257.14:35:56.22#ibcon#*mode == 0, iclass 31, count 2 2006.257.14:35:56.22#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.14:35:56.22#ibcon#[27=AT02-05\r\n] 2006.257.14:35:56.22#ibcon#*before write, iclass 31, count 2 2006.257.14:35:56.22#ibcon#enter sib2, iclass 31, count 2 2006.257.14:35:56.22#ibcon#flushed, iclass 31, count 2 2006.257.14:35:56.22#ibcon#about to write, iclass 31, count 2 2006.257.14:35:56.22#ibcon#wrote, iclass 31, count 2 2006.257.14:35:56.22#ibcon#about to read 3, iclass 31, count 2 2006.257.14:35:56.25#ibcon#read 3, iclass 31, count 2 2006.257.14:35:56.25#ibcon#about to read 4, iclass 31, count 2 2006.257.14:35:56.25#ibcon#read 4, iclass 31, count 2 2006.257.14:35:56.25#ibcon#about to read 5, iclass 31, count 2 2006.257.14:35:56.25#ibcon#read 5, iclass 31, count 2 2006.257.14:35:56.25#ibcon#about to read 6, iclass 31, count 2 2006.257.14:35:56.25#ibcon#read 6, iclass 31, count 2 2006.257.14:35:56.25#ibcon#end of sib2, iclass 31, count 2 2006.257.14:35:56.25#ibcon#*after write, iclass 31, count 2 2006.257.14:35:56.25#ibcon#*before return 0, iclass 31, count 2 2006.257.14:35:56.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:56.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.14:35:56.25#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.14:35:56.25#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:56.25#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:56.37#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:56.37#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:56.37#ibcon#enter wrdev, iclass 31, count 0 2006.257.14:35:56.37#ibcon#first serial, iclass 31, count 0 2006.257.14:35:56.37#ibcon#enter sib2, iclass 31, count 0 2006.257.14:35:56.37#ibcon#flushed, iclass 31, count 0 2006.257.14:35:56.37#ibcon#about to write, iclass 31, count 0 2006.257.14:35:56.37#ibcon#wrote, iclass 31, count 0 2006.257.14:35:56.37#ibcon#about to read 3, iclass 31, count 0 2006.257.14:35:56.39#ibcon#read 3, iclass 31, count 0 2006.257.14:35:56.39#ibcon#about to read 4, iclass 31, count 0 2006.257.14:35:56.39#ibcon#read 4, iclass 31, count 0 2006.257.14:35:56.39#ibcon#about to read 5, iclass 31, count 0 2006.257.14:35:56.39#ibcon#read 5, iclass 31, count 0 2006.257.14:35:56.39#ibcon#about to read 6, iclass 31, count 0 2006.257.14:35:56.39#ibcon#read 6, iclass 31, count 0 2006.257.14:35:56.39#ibcon#end of sib2, iclass 31, count 0 2006.257.14:35:56.39#ibcon#*mode == 0, iclass 31, count 0 2006.257.14:35:56.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.14:35:56.39#ibcon#[27=USB\r\n] 2006.257.14:35:56.39#ibcon#*before write, iclass 31, count 0 2006.257.14:35:56.39#ibcon#enter sib2, iclass 31, count 0 2006.257.14:35:56.39#ibcon#flushed, iclass 31, count 0 2006.257.14:35:56.39#ibcon#about to write, iclass 31, count 0 2006.257.14:35:56.39#ibcon#wrote, iclass 31, count 0 2006.257.14:35:56.39#ibcon#about to read 3, iclass 31, count 0 2006.257.14:35:56.42#ibcon#read 3, iclass 31, count 0 2006.257.14:35:56.42#ibcon#about to read 4, iclass 31, count 0 2006.257.14:35:56.42#ibcon#read 4, iclass 31, count 0 2006.257.14:35:56.42#ibcon#about to read 5, iclass 31, count 0 2006.257.14:35:56.42#ibcon#read 5, iclass 31, count 0 2006.257.14:35:56.42#ibcon#about to read 6, iclass 31, count 0 2006.257.14:35:56.42#ibcon#read 6, iclass 31, count 0 2006.257.14:35:56.42#ibcon#end of sib2, iclass 31, count 0 2006.257.14:35:56.42#ibcon#*after write, iclass 31, count 0 2006.257.14:35:56.42#ibcon#*before return 0, iclass 31, count 0 2006.257.14:35:56.42#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:56.42#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.14:35:56.42#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.14:35:56.42#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.14:35:56.42$vck44/vblo=3,649.99 2006.257.14:35:56.42#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.14:35:56.42#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.14:35:56.42#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:56.42#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:56.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:56.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:56.42#ibcon#enter wrdev, iclass 33, count 0 2006.257.14:35:56.42#ibcon#first serial, iclass 33, count 0 2006.257.14:35:56.42#ibcon#enter sib2, iclass 33, count 0 2006.257.14:35:56.42#ibcon#flushed, iclass 33, count 0 2006.257.14:35:56.44#ibcon#about to write, iclass 33, count 0 2006.257.14:35:56.44#ibcon#wrote, iclass 33, count 0 2006.257.14:35:56.44#ibcon#about to read 3, iclass 33, count 0 2006.257.14:35:56.46#ibcon#read 3, iclass 33, count 0 2006.257.14:35:56.46#ibcon#about to read 4, iclass 33, count 0 2006.257.14:35:56.46#ibcon#read 4, iclass 33, count 0 2006.257.14:35:56.46#ibcon#about to read 5, iclass 33, count 0 2006.257.14:35:56.46#ibcon#read 5, iclass 33, count 0 2006.257.14:35:56.46#ibcon#about to read 6, iclass 33, count 0 2006.257.14:35:56.46#ibcon#read 6, iclass 33, count 0 2006.257.14:35:56.46#ibcon#end of sib2, iclass 33, count 0 2006.257.14:35:56.46#ibcon#*mode == 0, iclass 33, count 0 2006.257.14:35:56.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.14:35:56.46#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:35:56.46#ibcon#*before write, iclass 33, count 0 2006.257.14:35:56.46#ibcon#enter sib2, iclass 33, count 0 2006.257.14:35:56.46#ibcon#flushed, iclass 33, count 0 2006.257.14:35:56.46#ibcon#about to write, iclass 33, count 0 2006.257.14:35:56.46#ibcon#wrote, iclass 33, count 0 2006.257.14:35:56.46#ibcon#about to read 3, iclass 33, count 0 2006.257.14:35:56.50#ibcon#read 3, iclass 33, count 0 2006.257.14:35:56.50#ibcon#about to read 4, iclass 33, count 0 2006.257.14:35:56.50#ibcon#read 4, iclass 33, count 0 2006.257.14:35:56.50#ibcon#about to read 5, iclass 33, count 0 2006.257.14:35:56.50#ibcon#read 5, iclass 33, count 0 2006.257.14:35:56.50#ibcon#about to read 6, iclass 33, count 0 2006.257.14:35:56.50#ibcon#read 6, iclass 33, count 0 2006.257.14:35:56.50#ibcon#end of sib2, iclass 33, count 0 2006.257.14:35:56.50#ibcon#*after write, iclass 33, count 0 2006.257.14:35:56.50#ibcon#*before return 0, iclass 33, count 0 2006.257.14:35:56.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:56.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.14:35:56.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.14:35:56.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.14:35:56.50$vck44/vb=3,4 2006.257.14:35:56.50#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.14:35:56.50#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.14:35:56.50#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:56.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:56.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:56.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:56.54#ibcon#enter wrdev, iclass 35, count 2 2006.257.14:35:56.54#ibcon#first serial, iclass 35, count 2 2006.257.14:35:56.54#ibcon#enter sib2, iclass 35, count 2 2006.257.14:35:56.54#ibcon#flushed, iclass 35, count 2 2006.257.14:35:56.54#ibcon#about to write, iclass 35, count 2 2006.257.14:35:56.54#ibcon#wrote, iclass 35, count 2 2006.257.14:35:56.54#ibcon#about to read 3, iclass 35, count 2 2006.257.14:35:56.56#ibcon#read 3, iclass 35, count 2 2006.257.14:35:56.56#ibcon#about to read 4, iclass 35, count 2 2006.257.14:35:56.56#ibcon#read 4, iclass 35, count 2 2006.257.14:35:56.56#ibcon#about to read 5, iclass 35, count 2 2006.257.14:35:56.56#ibcon#read 5, iclass 35, count 2 2006.257.14:35:56.56#ibcon#about to read 6, iclass 35, count 2 2006.257.14:35:56.56#ibcon#read 6, iclass 35, count 2 2006.257.14:35:56.56#ibcon#end of sib2, iclass 35, count 2 2006.257.14:35:56.56#ibcon#*mode == 0, iclass 35, count 2 2006.257.14:35:56.56#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.14:35:56.56#ibcon#[27=AT03-04\r\n] 2006.257.14:35:56.56#ibcon#*before write, iclass 35, count 2 2006.257.14:35:56.56#ibcon#enter sib2, iclass 35, count 2 2006.257.14:35:56.56#ibcon#flushed, iclass 35, count 2 2006.257.14:35:56.56#ibcon#about to write, iclass 35, count 2 2006.257.14:35:56.56#ibcon#wrote, iclass 35, count 2 2006.257.14:35:56.56#ibcon#about to read 3, iclass 35, count 2 2006.257.14:35:56.59#ibcon#read 3, iclass 35, count 2 2006.257.14:35:56.59#ibcon#about to read 4, iclass 35, count 2 2006.257.14:35:56.59#ibcon#read 4, iclass 35, count 2 2006.257.14:35:56.59#ibcon#about to read 5, iclass 35, count 2 2006.257.14:35:56.59#ibcon#read 5, iclass 35, count 2 2006.257.14:35:56.59#ibcon#about to read 6, iclass 35, count 2 2006.257.14:35:56.59#ibcon#read 6, iclass 35, count 2 2006.257.14:35:56.59#ibcon#end of sib2, iclass 35, count 2 2006.257.14:35:56.59#ibcon#*after write, iclass 35, count 2 2006.257.14:35:56.59#ibcon#*before return 0, iclass 35, count 2 2006.257.14:35:56.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:56.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.14:35:56.59#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.14:35:56.59#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:56.59#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:56.71#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:56.71#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:56.71#ibcon#enter wrdev, iclass 35, count 0 2006.257.14:35:56.71#ibcon#first serial, iclass 35, count 0 2006.257.14:35:56.71#ibcon#enter sib2, iclass 35, count 0 2006.257.14:35:56.71#ibcon#flushed, iclass 35, count 0 2006.257.14:35:56.71#ibcon#about to write, iclass 35, count 0 2006.257.14:35:56.71#ibcon#wrote, iclass 35, count 0 2006.257.14:35:56.71#ibcon#about to read 3, iclass 35, count 0 2006.257.14:35:56.73#ibcon#read 3, iclass 35, count 0 2006.257.14:35:56.73#ibcon#about to read 4, iclass 35, count 0 2006.257.14:35:56.73#ibcon#read 4, iclass 35, count 0 2006.257.14:35:56.73#ibcon#about to read 5, iclass 35, count 0 2006.257.14:35:56.73#ibcon#read 5, iclass 35, count 0 2006.257.14:35:56.73#ibcon#about to read 6, iclass 35, count 0 2006.257.14:35:56.73#ibcon#read 6, iclass 35, count 0 2006.257.14:35:56.73#ibcon#end of sib2, iclass 35, count 0 2006.257.14:35:56.73#ibcon#*mode == 0, iclass 35, count 0 2006.257.14:35:56.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.14:35:56.73#ibcon#[27=USB\r\n] 2006.257.14:35:56.73#ibcon#*before write, iclass 35, count 0 2006.257.14:35:56.73#ibcon#enter sib2, iclass 35, count 0 2006.257.14:35:56.73#ibcon#flushed, iclass 35, count 0 2006.257.14:35:56.73#ibcon#about to write, iclass 35, count 0 2006.257.14:35:56.73#ibcon#wrote, iclass 35, count 0 2006.257.14:35:56.73#ibcon#about to read 3, iclass 35, count 0 2006.257.14:35:56.76#ibcon#read 3, iclass 35, count 0 2006.257.14:35:56.76#ibcon#about to read 4, iclass 35, count 0 2006.257.14:35:56.76#ibcon#read 4, iclass 35, count 0 2006.257.14:35:56.76#ibcon#about to read 5, iclass 35, count 0 2006.257.14:35:56.76#ibcon#read 5, iclass 35, count 0 2006.257.14:35:56.76#ibcon#about to read 6, iclass 35, count 0 2006.257.14:35:56.76#ibcon#read 6, iclass 35, count 0 2006.257.14:35:56.76#ibcon#end of sib2, iclass 35, count 0 2006.257.14:35:56.76#ibcon#*after write, iclass 35, count 0 2006.257.14:35:56.76#ibcon#*before return 0, iclass 35, count 0 2006.257.14:35:56.76#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:56.76#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.14:35:56.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.14:35:56.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.14:35:56.76$vck44/vblo=4,679.99 2006.257.14:35:56.76#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.14:35:56.76#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.14:35:56.76#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:56.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:56.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:56.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:56.76#ibcon#enter wrdev, iclass 37, count 0 2006.257.14:35:56.76#ibcon#first serial, iclass 37, count 0 2006.257.14:35:56.76#ibcon#enter sib2, iclass 37, count 0 2006.257.14:35:56.76#ibcon#flushed, iclass 37, count 0 2006.257.14:35:56.76#ibcon#about to write, iclass 37, count 0 2006.257.14:35:56.76#ibcon#wrote, iclass 37, count 0 2006.257.14:35:56.76#ibcon#about to read 3, iclass 37, count 0 2006.257.14:35:56.78#ibcon#read 3, iclass 37, count 0 2006.257.14:35:56.78#ibcon#about to read 4, iclass 37, count 0 2006.257.14:35:56.78#ibcon#read 4, iclass 37, count 0 2006.257.14:35:56.78#ibcon#about to read 5, iclass 37, count 0 2006.257.14:35:56.78#ibcon#read 5, iclass 37, count 0 2006.257.14:35:56.78#ibcon#about to read 6, iclass 37, count 0 2006.257.14:35:56.78#ibcon#read 6, iclass 37, count 0 2006.257.14:35:56.78#ibcon#end of sib2, iclass 37, count 0 2006.257.14:35:56.78#ibcon#*mode == 0, iclass 37, count 0 2006.257.14:35:56.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.14:35:56.78#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:35:56.78#ibcon#*before write, iclass 37, count 0 2006.257.14:35:56.78#ibcon#enter sib2, iclass 37, count 0 2006.257.14:35:56.78#ibcon#flushed, iclass 37, count 0 2006.257.14:35:56.78#ibcon#about to write, iclass 37, count 0 2006.257.14:35:56.78#ibcon#wrote, iclass 37, count 0 2006.257.14:35:56.78#ibcon#about to read 3, iclass 37, count 0 2006.257.14:35:56.82#ibcon#read 3, iclass 37, count 0 2006.257.14:35:56.82#ibcon#about to read 4, iclass 37, count 0 2006.257.14:35:56.82#ibcon#read 4, iclass 37, count 0 2006.257.14:35:56.82#ibcon#about to read 5, iclass 37, count 0 2006.257.14:35:56.82#ibcon#read 5, iclass 37, count 0 2006.257.14:35:56.82#ibcon#about to read 6, iclass 37, count 0 2006.257.14:35:56.82#ibcon#read 6, iclass 37, count 0 2006.257.14:35:56.82#ibcon#end of sib2, iclass 37, count 0 2006.257.14:35:56.82#ibcon#*after write, iclass 37, count 0 2006.257.14:35:56.82#ibcon#*before return 0, iclass 37, count 0 2006.257.14:35:56.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:56.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.14:35:56.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.14:35:56.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.14:35:56.82$vck44/vb=4,5 2006.257.14:35:56.82#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.14:35:56.82#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.14:35:56.82#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:56.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:56.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:56.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:56.88#ibcon#enter wrdev, iclass 39, count 2 2006.257.14:35:56.88#ibcon#first serial, iclass 39, count 2 2006.257.14:35:56.88#ibcon#enter sib2, iclass 39, count 2 2006.257.14:35:56.88#ibcon#flushed, iclass 39, count 2 2006.257.14:35:56.88#ibcon#about to write, iclass 39, count 2 2006.257.14:35:56.88#ibcon#wrote, iclass 39, count 2 2006.257.14:35:56.88#ibcon#about to read 3, iclass 39, count 2 2006.257.14:35:56.90#ibcon#read 3, iclass 39, count 2 2006.257.14:35:56.90#ibcon#about to read 4, iclass 39, count 2 2006.257.14:35:56.90#ibcon#read 4, iclass 39, count 2 2006.257.14:35:56.90#ibcon#about to read 5, iclass 39, count 2 2006.257.14:35:56.90#ibcon#read 5, iclass 39, count 2 2006.257.14:35:56.90#ibcon#about to read 6, iclass 39, count 2 2006.257.14:35:56.90#ibcon#read 6, iclass 39, count 2 2006.257.14:35:56.90#ibcon#end of sib2, iclass 39, count 2 2006.257.14:35:56.90#ibcon#*mode == 0, iclass 39, count 2 2006.257.14:35:56.90#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.14:35:56.90#ibcon#[27=AT04-05\r\n] 2006.257.14:35:56.90#ibcon#*before write, iclass 39, count 2 2006.257.14:35:56.90#ibcon#enter sib2, iclass 39, count 2 2006.257.14:35:56.90#ibcon#flushed, iclass 39, count 2 2006.257.14:35:56.90#ibcon#about to write, iclass 39, count 2 2006.257.14:35:56.90#ibcon#wrote, iclass 39, count 2 2006.257.14:35:56.90#ibcon#about to read 3, iclass 39, count 2 2006.257.14:35:56.93#ibcon#read 3, iclass 39, count 2 2006.257.14:35:56.93#ibcon#about to read 4, iclass 39, count 2 2006.257.14:35:56.93#ibcon#read 4, iclass 39, count 2 2006.257.14:35:56.93#ibcon#about to read 5, iclass 39, count 2 2006.257.14:35:56.93#ibcon#read 5, iclass 39, count 2 2006.257.14:35:56.93#ibcon#about to read 6, iclass 39, count 2 2006.257.14:35:56.93#ibcon#read 6, iclass 39, count 2 2006.257.14:35:56.93#ibcon#end of sib2, iclass 39, count 2 2006.257.14:35:56.93#ibcon#*after write, iclass 39, count 2 2006.257.14:35:56.93#ibcon#*before return 0, iclass 39, count 2 2006.257.14:35:56.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:56.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.14:35:56.93#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.14:35:56.93#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:56.93#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:57.05#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:57.05#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:57.05#ibcon#enter wrdev, iclass 39, count 0 2006.257.14:35:57.05#ibcon#first serial, iclass 39, count 0 2006.257.14:35:57.05#ibcon#enter sib2, iclass 39, count 0 2006.257.14:35:57.05#ibcon#flushed, iclass 39, count 0 2006.257.14:35:57.05#ibcon#about to write, iclass 39, count 0 2006.257.14:35:57.05#ibcon#wrote, iclass 39, count 0 2006.257.14:35:57.05#ibcon#about to read 3, iclass 39, count 0 2006.257.14:35:57.07#ibcon#read 3, iclass 39, count 0 2006.257.14:35:57.07#ibcon#about to read 4, iclass 39, count 0 2006.257.14:35:57.07#ibcon#read 4, iclass 39, count 0 2006.257.14:35:57.07#ibcon#about to read 5, iclass 39, count 0 2006.257.14:35:57.07#ibcon#read 5, iclass 39, count 0 2006.257.14:35:57.07#ibcon#about to read 6, iclass 39, count 0 2006.257.14:35:57.07#ibcon#read 6, iclass 39, count 0 2006.257.14:35:57.07#ibcon#end of sib2, iclass 39, count 0 2006.257.14:35:57.07#ibcon#*mode == 0, iclass 39, count 0 2006.257.14:35:57.07#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.14:35:57.07#ibcon#[27=USB\r\n] 2006.257.14:35:57.07#ibcon#*before write, iclass 39, count 0 2006.257.14:35:57.07#ibcon#enter sib2, iclass 39, count 0 2006.257.14:35:57.07#ibcon#flushed, iclass 39, count 0 2006.257.14:35:57.07#ibcon#about to write, iclass 39, count 0 2006.257.14:35:57.07#ibcon#wrote, iclass 39, count 0 2006.257.14:35:57.07#ibcon#about to read 3, iclass 39, count 0 2006.257.14:35:57.08#abcon#<5=/14 1.3 3.6 17.47 971014.1\r\n> 2006.257.14:35:57.10#abcon#{5=INTERFACE CLEAR} 2006.257.14:35:57.10#ibcon#read 3, iclass 39, count 0 2006.257.14:35:57.10#ibcon#about to read 4, iclass 39, count 0 2006.257.14:35:57.10#ibcon#read 4, iclass 39, count 0 2006.257.14:35:57.10#ibcon#about to read 5, iclass 39, count 0 2006.257.14:35:57.10#ibcon#read 5, iclass 39, count 0 2006.257.14:35:57.10#ibcon#about to read 6, iclass 39, count 0 2006.257.14:35:57.10#ibcon#read 6, iclass 39, count 0 2006.257.14:35:57.10#ibcon#end of sib2, iclass 39, count 0 2006.257.14:35:57.10#ibcon#*after write, iclass 39, count 0 2006.257.14:35:57.10#ibcon#*before return 0, iclass 39, count 0 2006.257.14:35:57.10#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:57.10#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.14:35:57.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.14:35:57.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.14:35:57.10$vck44/vblo=5,709.99 2006.257.14:35:57.10#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.14:35:57.10#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.14:35:57.10#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:57.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:35:57.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:35:57.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:35:57.10#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:35:57.10#ibcon#first serial, iclass 6, count 0 2006.257.14:35:57.10#ibcon#enter sib2, iclass 6, count 0 2006.257.14:35:57.10#ibcon#flushed, iclass 6, count 0 2006.257.14:35:57.10#ibcon#about to write, iclass 6, count 0 2006.257.14:35:57.10#ibcon#wrote, iclass 6, count 0 2006.257.14:35:57.10#ibcon#about to read 3, iclass 6, count 0 2006.257.14:35:57.12#ibcon#read 3, iclass 6, count 0 2006.257.14:35:57.12#ibcon#about to read 4, iclass 6, count 0 2006.257.14:35:57.12#ibcon#read 4, iclass 6, count 0 2006.257.14:35:57.12#ibcon#about to read 5, iclass 6, count 0 2006.257.14:35:57.12#ibcon#read 5, iclass 6, count 0 2006.257.14:35:57.12#ibcon#about to read 6, iclass 6, count 0 2006.257.14:35:57.12#ibcon#read 6, iclass 6, count 0 2006.257.14:35:57.12#ibcon#end of sib2, iclass 6, count 0 2006.257.14:35:57.12#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:35:57.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:35:57.12#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:35:57.12#ibcon#*before write, iclass 6, count 0 2006.257.14:35:57.12#ibcon#enter sib2, iclass 6, count 0 2006.257.14:35:57.12#ibcon#flushed, iclass 6, count 0 2006.257.14:35:57.12#ibcon#about to write, iclass 6, count 0 2006.257.14:35:57.12#ibcon#wrote, iclass 6, count 0 2006.257.14:35:57.12#ibcon#about to read 3, iclass 6, count 0 2006.257.14:35:57.16#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:35:57.16#ibcon#read 3, iclass 6, count 0 2006.257.14:35:57.16#ibcon#about to read 4, iclass 6, count 0 2006.257.14:35:57.16#ibcon#read 4, iclass 6, count 0 2006.257.14:35:57.16#ibcon#about to read 5, iclass 6, count 0 2006.257.14:35:57.16#ibcon#read 5, iclass 6, count 0 2006.257.14:35:57.16#ibcon#about to read 6, iclass 6, count 0 2006.257.14:35:57.16#ibcon#read 6, iclass 6, count 0 2006.257.14:35:57.16#ibcon#end of sib2, iclass 6, count 0 2006.257.14:35:57.16#ibcon#*after write, iclass 6, count 0 2006.257.14:35:57.16#ibcon#*before return 0, iclass 6, count 0 2006.257.14:35:57.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:35:57.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:35:57.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:35:57.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:35:57.16$vck44/vb=5,4 2006.257.14:35:57.16#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.14:35:57.16#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.14:35:57.16#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:57.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:57.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:57.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:57.22#ibcon#enter wrdev, iclass 11, count 2 2006.257.14:35:57.22#ibcon#first serial, iclass 11, count 2 2006.257.14:35:57.22#ibcon#enter sib2, iclass 11, count 2 2006.257.14:35:57.22#ibcon#flushed, iclass 11, count 2 2006.257.14:35:57.22#ibcon#about to write, iclass 11, count 2 2006.257.14:35:57.22#ibcon#wrote, iclass 11, count 2 2006.257.14:35:57.22#ibcon#about to read 3, iclass 11, count 2 2006.257.14:35:57.24#ibcon#read 3, iclass 11, count 2 2006.257.14:35:57.24#ibcon#about to read 4, iclass 11, count 2 2006.257.14:35:57.24#ibcon#read 4, iclass 11, count 2 2006.257.14:35:57.24#ibcon#about to read 5, iclass 11, count 2 2006.257.14:35:57.24#ibcon#read 5, iclass 11, count 2 2006.257.14:35:57.24#ibcon#about to read 6, iclass 11, count 2 2006.257.14:35:57.24#ibcon#read 6, iclass 11, count 2 2006.257.14:35:57.24#ibcon#end of sib2, iclass 11, count 2 2006.257.14:35:57.24#ibcon#*mode == 0, iclass 11, count 2 2006.257.14:35:57.24#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.14:35:57.24#ibcon#[27=AT05-04\r\n] 2006.257.14:35:57.24#ibcon#*before write, iclass 11, count 2 2006.257.14:35:57.24#ibcon#enter sib2, iclass 11, count 2 2006.257.14:35:57.24#ibcon#flushed, iclass 11, count 2 2006.257.14:35:57.24#ibcon#about to write, iclass 11, count 2 2006.257.14:35:57.24#ibcon#wrote, iclass 11, count 2 2006.257.14:35:57.24#ibcon#about to read 3, iclass 11, count 2 2006.257.14:35:57.27#ibcon#read 3, iclass 11, count 2 2006.257.14:35:57.27#ibcon#about to read 4, iclass 11, count 2 2006.257.14:35:57.27#ibcon#read 4, iclass 11, count 2 2006.257.14:35:57.27#ibcon#about to read 5, iclass 11, count 2 2006.257.14:35:57.27#ibcon#read 5, iclass 11, count 2 2006.257.14:35:57.27#ibcon#about to read 6, iclass 11, count 2 2006.257.14:35:57.27#ibcon#read 6, iclass 11, count 2 2006.257.14:35:57.27#ibcon#end of sib2, iclass 11, count 2 2006.257.14:35:57.27#ibcon#*after write, iclass 11, count 2 2006.257.14:35:57.27#ibcon#*before return 0, iclass 11, count 2 2006.257.14:35:57.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:57.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.14:35:57.27#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.14:35:57.27#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:57.27#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:57.39#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:57.39#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:57.39#ibcon#enter wrdev, iclass 11, count 0 2006.257.14:35:57.39#ibcon#first serial, iclass 11, count 0 2006.257.14:35:57.39#ibcon#enter sib2, iclass 11, count 0 2006.257.14:35:57.39#ibcon#flushed, iclass 11, count 0 2006.257.14:35:57.39#ibcon#about to write, iclass 11, count 0 2006.257.14:35:57.39#ibcon#wrote, iclass 11, count 0 2006.257.14:35:57.39#ibcon#about to read 3, iclass 11, count 0 2006.257.14:35:57.41#ibcon#read 3, iclass 11, count 0 2006.257.14:35:57.41#ibcon#about to read 4, iclass 11, count 0 2006.257.14:35:57.41#ibcon#read 4, iclass 11, count 0 2006.257.14:35:57.41#ibcon#about to read 5, iclass 11, count 0 2006.257.14:35:57.41#ibcon#read 5, iclass 11, count 0 2006.257.14:35:57.41#ibcon#about to read 6, iclass 11, count 0 2006.257.14:35:57.41#ibcon#read 6, iclass 11, count 0 2006.257.14:35:57.41#ibcon#end of sib2, iclass 11, count 0 2006.257.14:35:57.41#ibcon#*mode == 0, iclass 11, count 0 2006.257.14:35:57.41#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.14:35:57.41#ibcon#[27=USB\r\n] 2006.257.14:35:57.41#ibcon#*before write, iclass 11, count 0 2006.257.14:35:57.41#ibcon#enter sib2, iclass 11, count 0 2006.257.14:35:57.41#ibcon#flushed, iclass 11, count 0 2006.257.14:35:57.41#ibcon#about to write, iclass 11, count 0 2006.257.14:35:57.41#ibcon#wrote, iclass 11, count 0 2006.257.14:35:57.41#ibcon#about to read 3, iclass 11, count 0 2006.257.14:35:57.44#ibcon#read 3, iclass 11, count 0 2006.257.14:35:57.44#ibcon#about to read 4, iclass 11, count 0 2006.257.14:35:57.44#ibcon#read 4, iclass 11, count 0 2006.257.14:35:57.44#ibcon#about to read 5, iclass 11, count 0 2006.257.14:35:57.44#ibcon#read 5, iclass 11, count 0 2006.257.14:35:57.44#ibcon#about to read 6, iclass 11, count 0 2006.257.14:35:57.44#ibcon#read 6, iclass 11, count 0 2006.257.14:35:57.44#ibcon#end of sib2, iclass 11, count 0 2006.257.14:35:57.44#ibcon#*after write, iclass 11, count 0 2006.257.14:35:57.44#ibcon#*before return 0, iclass 11, count 0 2006.257.14:35:57.44#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:57.44#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.14:35:57.44#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.14:35:57.44#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.14:35:57.44$vck44/vblo=6,719.99 2006.257.14:35:57.44#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.14:35:57.44#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.14:35:57.44#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:57.44#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:57.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:57.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:57.44#ibcon#enter wrdev, iclass 13, count 0 2006.257.14:35:57.44#ibcon#first serial, iclass 13, count 0 2006.257.14:35:57.44#ibcon#enter sib2, iclass 13, count 0 2006.257.14:35:57.44#ibcon#flushed, iclass 13, count 0 2006.257.14:35:57.44#ibcon#about to write, iclass 13, count 0 2006.257.14:35:57.44#ibcon#wrote, iclass 13, count 0 2006.257.14:35:57.44#ibcon#about to read 3, iclass 13, count 0 2006.257.14:35:57.46#ibcon#read 3, iclass 13, count 0 2006.257.14:35:57.46#ibcon#about to read 4, iclass 13, count 0 2006.257.14:35:57.46#ibcon#read 4, iclass 13, count 0 2006.257.14:35:57.46#ibcon#about to read 5, iclass 13, count 0 2006.257.14:35:57.46#ibcon#read 5, iclass 13, count 0 2006.257.14:35:57.46#ibcon#about to read 6, iclass 13, count 0 2006.257.14:35:57.46#ibcon#read 6, iclass 13, count 0 2006.257.14:35:57.46#ibcon#end of sib2, iclass 13, count 0 2006.257.14:35:57.46#ibcon#*mode == 0, iclass 13, count 0 2006.257.14:35:57.46#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.14:35:57.46#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:35:57.46#ibcon#*before write, iclass 13, count 0 2006.257.14:35:57.46#ibcon#enter sib2, iclass 13, count 0 2006.257.14:35:57.46#ibcon#flushed, iclass 13, count 0 2006.257.14:35:57.46#ibcon#about to write, iclass 13, count 0 2006.257.14:35:57.46#ibcon#wrote, iclass 13, count 0 2006.257.14:35:57.46#ibcon#about to read 3, iclass 13, count 0 2006.257.14:35:57.50#ibcon#read 3, iclass 13, count 0 2006.257.14:35:57.50#ibcon#about to read 4, iclass 13, count 0 2006.257.14:35:57.50#ibcon#read 4, iclass 13, count 0 2006.257.14:35:57.50#ibcon#about to read 5, iclass 13, count 0 2006.257.14:35:57.50#ibcon#read 5, iclass 13, count 0 2006.257.14:35:57.50#ibcon#about to read 6, iclass 13, count 0 2006.257.14:35:57.50#ibcon#read 6, iclass 13, count 0 2006.257.14:35:57.50#ibcon#end of sib2, iclass 13, count 0 2006.257.14:35:57.50#ibcon#*after write, iclass 13, count 0 2006.257.14:35:57.50#ibcon#*before return 0, iclass 13, count 0 2006.257.14:35:57.50#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:57.50#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.14:35:57.50#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.14:35:57.50#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.14:35:57.50$vck44/vb=6,4 2006.257.14:35:57.50#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.14:35:57.50#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.14:35:57.50#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:57.50#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:57.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:57.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:57.56#ibcon#enter wrdev, iclass 15, count 2 2006.257.14:35:57.56#ibcon#first serial, iclass 15, count 2 2006.257.14:35:57.56#ibcon#enter sib2, iclass 15, count 2 2006.257.14:35:57.56#ibcon#flushed, iclass 15, count 2 2006.257.14:35:57.56#ibcon#about to write, iclass 15, count 2 2006.257.14:35:57.56#ibcon#wrote, iclass 15, count 2 2006.257.14:35:57.56#ibcon#about to read 3, iclass 15, count 2 2006.257.14:35:57.58#ibcon#read 3, iclass 15, count 2 2006.257.14:35:57.58#ibcon#about to read 4, iclass 15, count 2 2006.257.14:35:57.58#ibcon#read 4, iclass 15, count 2 2006.257.14:35:57.58#ibcon#about to read 5, iclass 15, count 2 2006.257.14:35:57.58#ibcon#read 5, iclass 15, count 2 2006.257.14:35:57.58#ibcon#about to read 6, iclass 15, count 2 2006.257.14:35:57.58#ibcon#read 6, iclass 15, count 2 2006.257.14:35:57.58#ibcon#end of sib2, iclass 15, count 2 2006.257.14:35:57.58#ibcon#*mode == 0, iclass 15, count 2 2006.257.14:35:57.58#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.14:35:57.58#ibcon#[27=AT06-04\r\n] 2006.257.14:35:57.58#ibcon#*before write, iclass 15, count 2 2006.257.14:35:57.58#ibcon#enter sib2, iclass 15, count 2 2006.257.14:35:57.58#ibcon#flushed, iclass 15, count 2 2006.257.14:35:57.58#ibcon#about to write, iclass 15, count 2 2006.257.14:35:57.58#ibcon#wrote, iclass 15, count 2 2006.257.14:35:57.58#ibcon#about to read 3, iclass 15, count 2 2006.257.14:35:57.61#ibcon#read 3, iclass 15, count 2 2006.257.14:35:57.61#ibcon#about to read 4, iclass 15, count 2 2006.257.14:35:57.61#ibcon#read 4, iclass 15, count 2 2006.257.14:35:57.61#ibcon#about to read 5, iclass 15, count 2 2006.257.14:35:57.61#ibcon#read 5, iclass 15, count 2 2006.257.14:35:57.61#ibcon#about to read 6, iclass 15, count 2 2006.257.14:35:57.61#ibcon#read 6, iclass 15, count 2 2006.257.14:35:57.61#ibcon#end of sib2, iclass 15, count 2 2006.257.14:35:57.61#ibcon#*after write, iclass 15, count 2 2006.257.14:35:57.61#ibcon#*before return 0, iclass 15, count 2 2006.257.14:35:57.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:57.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.14:35:57.61#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.14:35:57.61#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:57.61#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:57.73#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:57.73#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:57.73#ibcon#enter wrdev, iclass 15, count 0 2006.257.14:35:57.73#ibcon#first serial, iclass 15, count 0 2006.257.14:35:57.73#ibcon#enter sib2, iclass 15, count 0 2006.257.14:35:57.73#ibcon#flushed, iclass 15, count 0 2006.257.14:35:57.73#ibcon#about to write, iclass 15, count 0 2006.257.14:35:57.73#ibcon#wrote, iclass 15, count 0 2006.257.14:35:57.73#ibcon#about to read 3, iclass 15, count 0 2006.257.14:35:57.75#ibcon#read 3, iclass 15, count 0 2006.257.14:35:57.75#ibcon#about to read 4, iclass 15, count 0 2006.257.14:35:57.75#ibcon#read 4, iclass 15, count 0 2006.257.14:35:57.75#ibcon#about to read 5, iclass 15, count 0 2006.257.14:35:57.75#ibcon#read 5, iclass 15, count 0 2006.257.14:35:57.75#ibcon#about to read 6, iclass 15, count 0 2006.257.14:35:57.75#ibcon#read 6, iclass 15, count 0 2006.257.14:35:57.75#ibcon#end of sib2, iclass 15, count 0 2006.257.14:35:57.75#ibcon#*mode == 0, iclass 15, count 0 2006.257.14:35:57.75#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.14:35:57.75#ibcon#[27=USB\r\n] 2006.257.14:35:57.75#ibcon#*before write, iclass 15, count 0 2006.257.14:35:57.75#ibcon#enter sib2, iclass 15, count 0 2006.257.14:35:57.75#ibcon#flushed, iclass 15, count 0 2006.257.14:35:57.75#ibcon#about to write, iclass 15, count 0 2006.257.14:35:57.75#ibcon#wrote, iclass 15, count 0 2006.257.14:35:57.75#ibcon#about to read 3, iclass 15, count 0 2006.257.14:35:57.78#ibcon#read 3, iclass 15, count 0 2006.257.14:35:57.78#ibcon#about to read 4, iclass 15, count 0 2006.257.14:35:57.78#ibcon#read 4, iclass 15, count 0 2006.257.14:35:57.78#ibcon#about to read 5, iclass 15, count 0 2006.257.14:35:57.78#ibcon#read 5, iclass 15, count 0 2006.257.14:35:57.78#ibcon#about to read 6, iclass 15, count 0 2006.257.14:35:57.78#ibcon#read 6, iclass 15, count 0 2006.257.14:35:57.78#ibcon#end of sib2, iclass 15, count 0 2006.257.14:35:57.78#ibcon#*after write, iclass 15, count 0 2006.257.14:35:57.78#ibcon#*before return 0, iclass 15, count 0 2006.257.14:35:57.78#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:57.78#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.14:35:57.78#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.14:35:57.78#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.14:35:57.78$vck44/vblo=7,734.99 2006.257.14:35:57.78#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.14:35:57.78#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.14:35:57.78#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:57.78#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:57.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:57.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:57.78#ibcon#enter wrdev, iclass 17, count 0 2006.257.14:35:57.78#ibcon#first serial, iclass 17, count 0 2006.257.14:35:57.78#ibcon#enter sib2, iclass 17, count 0 2006.257.14:35:57.78#ibcon#flushed, iclass 17, count 0 2006.257.14:35:57.78#ibcon#about to write, iclass 17, count 0 2006.257.14:35:57.78#ibcon#wrote, iclass 17, count 0 2006.257.14:35:57.78#ibcon#about to read 3, iclass 17, count 0 2006.257.14:35:57.80#ibcon#read 3, iclass 17, count 0 2006.257.14:35:57.80#ibcon#about to read 4, iclass 17, count 0 2006.257.14:35:57.80#ibcon#read 4, iclass 17, count 0 2006.257.14:35:57.80#ibcon#about to read 5, iclass 17, count 0 2006.257.14:35:57.80#ibcon#read 5, iclass 17, count 0 2006.257.14:35:57.80#ibcon#about to read 6, iclass 17, count 0 2006.257.14:35:57.80#ibcon#read 6, iclass 17, count 0 2006.257.14:35:57.80#ibcon#end of sib2, iclass 17, count 0 2006.257.14:35:57.80#ibcon#*mode == 0, iclass 17, count 0 2006.257.14:35:57.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.14:35:57.80#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:35:57.80#ibcon#*before write, iclass 17, count 0 2006.257.14:35:57.80#ibcon#enter sib2, iclass 17, count 0 2006.257.14:35:57.80#ibcon#flushed, iclass 17, count 0 2006.257.14:35:57.80#ibcon#about to write, iclass 17, count 0 2006.257.14:35:57.80#ibcon#wrote, iclass 17, count 0 2006.257.14:35:57.80#ibcon#about to read 3, iclass 17, count 0 2006.257.14:35:57.84#ibcon#read 3, iclass 17, count 0 2006.257.14:35:57.84#ibcon#about to read 4, iclass 17, count 0 2006.257.14:35:57.84#ibcon#read 4, iclass 17, count 0 2006.257.14:35:57.84#ibcon#about to read 5, iclass 17, count 0 2006.257.14:35:57.84#ibcon#read 5, iclass 17, count 0 2006.257.14:35:57.84#ibcon#about to read 6, iclass 17, count 0 2006.257.14:35:57.84#ibcon#read 6, iclass 17, count 0 2006.257.14:35:57.84#ibcon#end of sib2, iclass 17, count 0 2006.257.14:35:57.84#ibcon#*after write, iclass 17, count 0 2006.257.14:35:57.84#ibcon#*before return 0, iclass 17, count 0 2006.257.14:35:57.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:57.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.14:35:57.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.14:35:57.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.14:35:57.84$vck44/vb=7,4 2006.257.14:35:57.84#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.14:35:57.84#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.14:35:57.84#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:57.84#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:57.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:57.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:57.90#ibcon#enter wrdev, iclass 19, count 2 2006.257.14:35:57.90#ibcon#first serial, iclass 19, count 2 2006.257.14:35:57.90#ibcon#enter sib2, iclass 19, count 2 2006.257.14:35:57.90#ibcon#flushed, iclass 19, count 2 2006.257.14:35:57.90#ibcon#about to write, iclass 19, count 2 2006.257.14:35:57.90#ibcon#wrote, iclass 19, count 2 2006.257.14:35:57.90#ibcon#about to read 3, iclass 19, count 2 2006.257.14:35:57.92#ibcon#read 3, iclass 19, count 2 2006.257.14:35:57.92#ibcon#about to read 4, iclass 19, count 2 2006.257.14:35:57.92#ibcon#read 4, iclass 19, count 2 2006.257.14:35:57.92#ibcon#about to read 5, iclass 19, count 2 2006.257.14:35:57.92#ibcon#read 5, iclass 19, count 2 2006.257.14:35:57.92#ibcon#about to read 6, iclass 19, count 2 2006.257.14:35:57.92#ibcon#read 6, iclass 19, count 2 2006.257.14:35:57.92#ibcon#end of sib2, iclass 19, count 2 2006.257.14:35:57.92#ibcon#*mode == 0, iclass 19, count 2 2006.257.14:35:57.92#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.14:35:57.92#ibcon#[27=AT07-04\r\n] 2006.257.14:35:57.92#ibcon#*before write, iclass 19, count 2 2006.257.14:35:57.92#ibcon#enter sib2, iclass 19, count 2 2006.257.14:35:57.92#ibcon#flushed, iclass 19, count 2 2006.257.14:35:57.92#ibcon#about to write, iclass 19, count 2 2006.257.14:35:57.92#ibcon#wrote, iclass 19, count 2 2006.257.14:35:57.92#ibcon#about to read 3, iclass 19, count 2 2006.257.14:35:57.95#ibcon#read 3, iclass 19, count 2 2006.257.14:35:57.95#ibcon#about to read 4, iclass 19, count 2 2006.257.14:35:57.95#ibcon#read 4, iclass 19, count 2 2006.257.14:35:57.95#ibcon#about to read 5, iclass 19, count 2 2006.257.14:35:57.95#ibcon#read 5, iclass 19, count 2 2006.257.14:35:57.95#ibcon#about to read 6, iclass 19, count 2 2006.257.14:35:57.95#ibcon#read 6, iclass 19, count 2 2006.257.14:35:57.95#ibcon#end of sib2, iclass 19, count 2 2006.257.14:35:57.95#ibcon#*after write, iclass 19, count 2 2006.257.14:35:57.95#ibcon#*before return 0, iclass 19, count 2 2006.257.14:35:57.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:57.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.14:35:57.95#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.14:35:57.95#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:57.95#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:58.07#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:58.07#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:58.07#ibcon#enter wrdev, iclass 19, count 0 2006.257.14:35:58.07#ibcon#first serial, iclass 19, count 0 2006.257.14:35:58.07#ibcon#enter sib2, iclass 19, count 0 2006.257.14:35:58.07#ibcon#flushed, iclass 19, count 0 2006.257.14:35:58.07#ibcon#about to write, iclass 19, count 0 2006.257.14:35:58.07#ibcon#wrote, iclass 19, count 0 2006.257.14:35:58.07#ibcon#about to read 3, iclass 19, count 0 2006.257.14:35:58.09#ibcon#read 3, iclass 19, count 0 2006.257.14:35:58.09#ibcon#about to read 4, iclass 19, count 0 2006.257.14:35:58.09#ibcon#read 4, iclass 19, count 0 2006.257.14:35:58.09#ibcon#about to read 5, iclass 19, count 0 2006.257.14:35:58.09#ibcon#read 5, iclass 19, count 0 2006.257.14:35:58.09#ibcon#about to read 6, iclass 19, count 0 2006.257.14:35:58.09#ibcon#read 6, iclass 19, count 0 2006.257.14:35:58.09#ibcon#end of sib2, iclass 19, count 0 2006.257.14:35:58.09#ibcon#*mode == 0, iclass 19, count 0 2006.257.14:35:58.09#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.14:35:58.09#ibcon#[27=USB\r\n] 2006.257.14:35:58.09#ibcon#*before write, iclass 19, count 0 2006.257.14:35:58.09#ibcon#enter sib2, iclass 19, count 0 2006.257.14:35:58.09#ibcon#flushed, iclass 19, count 0 2006.257.14:35:58.09#ibcon#about to write, iclass 19, count 0 2006.257.14:35:58.09#ibcon#wrote, iclass 19, count 0 2006.257.14:35:58.09#ibcon#about to read 3, iclass 19, count 0 2006.257.14:35:58.12#ibcon#read 3, iclass 19, count 0 2006.257.14:35:58.12#ibcon#about to read 4, iclass 19, count 0 2006.257.14:35:58.12#ibcon#read 4, iclass 19, count 0 2006.257.14:35:58.12#ibcon#about to read 5, iclass 19, count 0 2006.257.14:35:58.12#ibcon#read 5, iclass 19, count 0 2006.257.14:35:58.12#ibcon#about to read 6, iclass 19, count 0 2006.257.14:35:58.12#ibcon#read 6, iclass 19, count 0 2006.257.14:35:58.12#ibcon#end of sib2, iclass 19, count 0 2006.257.14:35:58.12#ibcon#*after write, iclass 19, count 0 2006.257.14:35:58.12#ibcon#*before return 0, iclass 19, count 0 2006.257.14:35:58.12#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:58.12#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.14:35:58.12#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.14:35:58.12#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.14:35:58.12$vck44/vblo=8,744.99 2006.257.14:35:58.12#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.14:35:58.12#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.14:35:58.12#ibcon#ireg 17 cls_cnt 0 2006.257.14:35:58.12#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:58.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:58.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:58.12#ibcon#enter wrdev, iclass 21, count 0 2006.257.14:35:58.12#ibcon#first serial, iclass 21, count 0 2006.257.14:35:58.12#ibcon#enter sib2, iclass 21, count 0 2006.257.14:35:58.12#ibcon#flushed, iclass 21, count 0 2006.257.14:35:58.12#ibcon#about to write, iclass 21, count 0 2006.257.14:35:58.12#ibcon#wrote, iclass 21, count 0 2006.257.14:35:58.12#ibcon#about to read 3, iclass 21, count 0 2006.257.14:35:58.14#ibcon#read 3, iclass 21, count 0 2006.257.14:35:58.14#ibcon#about to read 4, iclass 21, count 0 2006.257.14:35:58.14#ibcon#read 4, iclass 21, count 0 2006.257.14:35:58.14#ibcon#about to read 5, iclass 21, count 0 2006.257.14:35:58.14#ibcon#read 5, iclass 21, count 0 2006.257.14:35:58.14#ibcon#about to read 6, iclass 21, count 0 2006.257.14:35:58.14#ibcon#read 6, iclass 21, count 0 2006.257.14:35:58.14#ibcon#end of sib2, iclass 21, count 0 2006.257.14:35:58.14#ibcon#*mode == 0, iclass 21, count 0 2006.257.14:35:58.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.14:35:58.14#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:35:58.14#ibcon#*before write, iclass 21, count 0 2006.257.14:35:58.14#ibcon#enter sib2, iclass 21, count 0 2006.257.14:35:58.14#ibcon#flushed, iclass 21, count 0 2006.257.14:35:58.14#ibcon#about to write, iclass 21, count 0 2006.257.14:35:58.14#ibcon#wrote, iclass 21, count 0 2006.257.14:35:58.14#ibcon#about to read 3, iclass 21, count 0 2006.257.14:35:58.18#ibcon#read 3, iclass 21, count 0 2006.257.14:35:58.18#ibcon#about to read 4, iclass 21, count 0 2006.257.14:35:58.18#ibcon#read 4, iclass 21, count 0 2006.257.14:35:58.18#ibcon#about to read 5, iclass 21, count 0 2006.257.14:35:58.18#ibcon#read 5, iclass 21, count 0 2006.257.14:35:58.18#ibcon#about to read 6, iclass 21, count 0 2006.257.14:35:58.18#ibcon#read 6, iclass 21, count 0 2006.257.14:35:58.18#ibcon#end of sib2, iclass 21, count 0 2006.257.14:35:58.18#ibcon#*after write, iclass 21, count 0 2006.257.14:35:58.18#ibcon#*before return 0, iclass 21, count 0 2006.257.14:35:58.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:58.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.14:35:58.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.14:35:58.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.14:35:58.18$vck44/vb=8,4 2006.257.14:35:58.18#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.14:35:58.18#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.14:35:58.18#ibcon#ireg 11 cls_cnt 2 2006.257.14:35:58.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:58.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:58.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:58.24#ibcon#enter wrdev, iclass 23, count 2 2006.257.14:35:58.24#ibcon#first serial, iclass 23, count 2 2006.257.14:35:58.24#ibcon#enter sib2, iclass 23, count 2 2006.257.14:35:58.24#ibcon#flushed, iclass 23, count 2 2006.257.14:35:58.24#ibcon#about to write, iclass 23, count 2 2006.257.14:35:58.24#ibcon#wrote, iclass 23, count 2 2006.257.14:35:58.24#ibcon#about to read 3, iclass 23, count 2 2006.257.14:35:58.26#ibcon#read 3, iclass 23, count 2 2006.257.14:35:58.26#ibcon#about to read 4, iclass 23, count 2 2006.257.14:35:58.26#ibcon#read 4, iclass 23, count 2 2006.257.14:35:58.26#ibcon#about to read 5, iclass 23, count 2 2006.257.14:35:58.26#ibcon#read 5, iclass 23, count 2 2006.257.14:35:58.26#ibcon#about to read 6, iclass 23, count 2 2006.257.14:35:58.26#ibcon#read 6, iclass 23, count 2 2006.257.14:35:58.26#ibcon#end of sib2, iclass 23, count 2 2006.257.14:35:58.26#ibcon#*mode == 0, iclass 23, count 2 2006.257.14:35:58.26#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.14:35:58.26#ibcon#[27=AT08-04\r\n] 2006.257.14:35:58.26#ibcon#*before write, iclass 23, count 2 2006.257.14:35:58.26#ibcon#enter sib2, iclass 23, count 2 2006.257.14:35:58.26#ibcon#flushed, iclass 23, count 2 2006.257.14:35:58.26#ibcon#about to write, iclass 23, count 2 2006.257.14:35:58.26#ibcon#wrote, iclass 23, count 2 2006.257.14:35:58.26#ibcon#about to read 3, iclass 23, count 2 2006.257.14:35:58.29#ibcon#read 3, iclass 23, count 2 2006.257.14:35:58.29#ibcon#about to read 4, iclass 23, count 2 2006.257.14:35:58.29#ibcon#read 4, iclass 23, count 2 2006.257.14:35:58.29#ibcon#about to read 5, iclass 23, count 2 2006.257.14:35:58.29#ibcon#read 5, iclass 23, count 2 2006.257.14:35:58.29#ibcon#about to read 6, iclass 23, count 2 2006.257.14:35:58.29#ibcon#read 6, iclass 23, count 2 2006.257.14:35:58.29#ibcon#end of sib2, iclass 23, count 2 2006.257.14:35:58.29#ibcon#*after write, iclass 23, count 2 2006.257.14:35:58.29#ibcon#*before return 0, iclass 23, count 2 2006.257.14:35:58.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:58.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:35:58.29#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.14:35:58.29#ibcon#ireg 7 cls_cnt 0 2006.257.14:35:58.29#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:58.41#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:58.41#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:58.41#ibcon#enter wrdev, iclass 23, count 0 2006.257.14:35:58.41#ibcon#first serial, iclass 23, count 0 2006.257.14:35:58.41#ibcon#enter sib2, iclass 23, count 0 2006.257.14:35:58.41#ibcon#flushed, iclass 23, count 0 2006.257.14:35:58.41#ibcon#about to write, iclass 23, count 0 2006.257.14:35:58.41#ibcon#wrote, iclass 23, count 0 2006.257.14:35:58.41#ibcon#about to read 3, iclass 23, count 0 2006.257.14:35:58.43#ibcon#read 3, iclass 23, count 0 2006.257.14:35:58.43#ibcon#about to read 4, iclass 23, count 0 2006.257.14:35:58.43#ibcon#read 4, iclass 23, count 0 2006.257.14:35:58.43#ibcon#about to read 5, iclass 23, count 0 2006.257.14:35:58.43#ibcon#read 5, iclass 23, count 0 2006.257.14:35:58.43#ibcon#about to read 6, iclass 23, count 0 2006.257.14:35:58.43#ibcon#read 6, iclass 23, count 0 2006.257.14:35:58.43#ibcon#end of sib2, iclass 23, count 0 2006.257.14:35:58.43#ibcon#*mode == 0, iclass 23, count 0 2006.257.14:35:58.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.14:35:58.43#ibcon#[27=USB\r\n] 2006.257.14:35:58.43#ibcon#*before write, iclass 23, count 0 2006.257.14:35:58.43#ibcon#enter sib2, iclass 23, count 0 2006.257.14:35:58.43#ibcon#flushed, iclass 23, count 0 2006.257.14:35:58.43#ibcon#about to write, iclass 23, count 0 2006.257.14:35:58.43#ibcon#wrote, iclass 23, count 0 2006.257.14:35:58.43#ibcon#about to read 3, iclass 23, count 0 2006.257.14:35:58.46#ibcon#read 3, iclass 23, count 0 2006.257.14:35:58.46#ibcon#about to read 4, iclass 23, count 0 2006.257.14:35:58.46#ibcon#read 4, iclass 23, count 0 2006.257.14:35:58.46#ibcon#about to read 5, iclass 23, count 0 2006.257.14:35:58.46#ibcon#read 5, iclass 23, count 0 2006.257.14:35:58.46#ibcon#about to read 6, iclass 23, count 0 2006.257.14:35:58.46#ibcon#read 6, iclass 23, count 0 2006.257.14:35:58.46#ibcon#end of sib2, iclass 23, count 0 2006.257.14:35:58.46#ibcon#*after write, iclass 23, count 0 2006.257.14:35:58.46#ibcon#*before return 0, iclass 23, count 0 2006.257.14:35:58.46#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:58.46#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:35:58.46#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.14:35:58.46#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.14:35:58.46$vck44/vabw=wide 2006.257.14:35:58.46#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.14:35:58.46#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.14:35:58.46#ibcon#ireg 8 cls_cnt 0 2006.257.14:35:58.46#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:58.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:58.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:58.46#ibcon#enter wrdev, iclass 25, count 0 2006.257.14:35:58.46#ibcon#first serial, iclass 25, count 0 2006.257.14:35:58.46#ibcon#enter sib2, iclass 25, count 0 2006.257.14:35:58.46#ibcon#flushed, iclass 25, count 0 2006.257.14:35:58.46#ibcon#about to write, iclass 25, count 0 2006.257.14:35:58.46#ibcon#wrote, iclass 25, count 0 2006.257.14:35:58.46#ibcon#about to read 3, iclass 25, count 0 2006.257.14:35:58.48#ibcon#read 3, iclass 25, count 0 2006.257.14:35:58.48#ibcon#about to read 4, iclass 25, count 0 2006.257.14:35:58.48#ibcon#read 4, iclass 25, count 0 2006.257.14:35:58.48#ibcon#about to read 5, iclass 25, count 0 2006.257.14:35:58.48#ibcon#read 5, iclass 25, count 0 2006.257.14:35:58.48#ibcon#about to read 6, iclass 25, count 0 2006.257.14:35:58.48#ibcon#read 6, iclass 25, count 0 2006.257.14:35:58.48#ibcon#end of sib2, iclass 25, count 0 2006.257.14:35:58.48#ibcon#*mode == 0, iclass 25, count 0 2006.257.14:35:58.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.14:35:58.48#ibcon#[25=BW32\r\n] 2006.257.14:35:58.48#ibcon#*before write, iclass 25, count 0 2006.257.14:35:58.48#ibcon#enter sib2, iclass 25, count 0 2006.257.14:35:58.48#ibcon#flushed, iclass 25, count 0 2006.257.14:35:58.48#ibcon#about to write, iclass 25, count 0 2006.257.14:35:58.48#ibcon#wrote, iclass 25, count 0 2006.257.14:35:58.48#ibcon#about to read 3, iclass 25, count 0 2006.257.14:35:58.51#ibcon#read 3, iclass 25, count 0 2006.257.14:35:58.51#ibcon#about to read 4, iclass 25, count 0 2006.257.14:35:58.51#ibcon#read 4, iclass 25, count 0 2006.257.14:35:58.51#ibcon#about to read 5, iclass 25, count 0 2006.257.14:35:58.51#ibcon#read 5, iclass 25, count 0 2006.257.14:35:58.51#ibcon#about to read 6, iclass 25, count 0 2006.257.14:35:58.51#ibcon#read 6, iclass 25, count 0 2006.257.14:35:58.51#ibcon#end of sib2, iclass 25, count 0 2006.257.14:35:58.51#ibcon#*after write, iclass 25, count 0 2006.257.14:35:58.51#ibcon#*before return 0, iclass 25, count 0 2006.257.14:35:58.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:58.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.14:35:58.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.14:35:58.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.14:35:58.51$vck44/vbbw=wide 2006.257.14:35:58.51#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.14:35:58.51#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.14:35:58.51#ibcon#ireg 8 cls_cnt 0 2006.257.14:35:58.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:35:58.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:35:58.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:35:58.58#ibcon#enter wrdev, iclass 27, count 0 2006.257.14:35:58.58#ibcon#first serial, iclass 27, count 0 2006.257.14:35:58.58#ibcon#enter sib2, iclass 27, count 0 2006.257.14:35:58.58#ibcon#flushed, iclass 27, count 0 2006.257.14:35:58.58#ibcon#about to write, iclass 27, count 0 2006.257.14:35:58.58#ibcon#wrote, iclass 27, count 0 2006.257.14:35:58.58#ibcon#about to read 3, iclass 27, count 0 2006.257.14:35:58.60#ibcon#read 3, iclass 27, count 0 2006.257.14:35:58.60#ibcon#about to read 4, iclass 27, count 0 2006.257.14:35:58.60#ibcon#read 4, iclass 27, count 0 2006.257.14:35:58.60#ibcon#about to read 5, iclass 27, count 0 2006.257.14:35:58.60#ibcon#read 5, iclass 27, count 0 2006.257.14:35:58.60#ibcon#about to read 6, iclass 27, count 0 2006.257.14:35:58.60#ibcon#read 6, iclass 27, count 0 2006.257.14:35:58.60#ibcon#end of sib2, iclass 27, count 0 2006.257.14:35:58.60#ibcon#*mode == 0, iclass 27, count 0 2006.257.14:35:58.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.14:35:58.60#ibcon#[27=BW32\r\n] 2006.257.14:35:58.60#ibcon#*before write, iclass 27, count 0 2006.257.14:35:58.60#ibcon#enter sib2, iclass 27, count 0 2006.257.14:35:58.60#ibcon#flushed, iclass 27, count 0 2006.257.14:35:58.60#ibcon#about to write, iclass 27, count 0 2006.257.14:35:58.60#ibcon#wrote, iclass 27, count 0 2006.257.14:35:58.60#ibcon#about to read 3, iclass 27, count 0 2006.257.14:35:58.63#ibcon#read 3, iclass 27, count 0 2006.257.14:35:58.63#ibcon#about to read 4, iclass 27, count 0 2006.257.14:35:58.63#ibcon#read 4, iclass 27, count 0 2006.257.14:35:58.63#ibcon#about to read 5, iclass 27, count 0 2006.257.14:35:58.63#ibcon#read 5, iclass 27, count 0 2006.257.14:35:58.63#ibcon#about to read 6, iclass 27, count 0 2006.257.14:35:58.63#ibcon#read 6, iclass 27, count 0 2006.257.14:35:58.63#ibcon#end of sib2, iclass 27, count 0 2006.257.14:35:58.63#ibcon#*after write, iclass 27, count 0 2006.257.14:35:58.63#ibcon#*before return 0, iclass 27, count 0 2006.257.14:35:58.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:35:58.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.14:35:58.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.14:35:58.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.14:35:58.63$setupk4/ifdk4 2006.257.14:35:58.63$ifdk4/lo= 2006.257.14:35:58.63$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:35:58.63$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:35:58.63$ifdk4/patch= 2006.257.14:35:58.63$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:35:58.63$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:35:58.63$setupk4/!*+20s 2006.257.14:36:05.14#trakl#Source acquired 2006.257.14:36:06.14#flagr#flagr/antenna,acquired 2006.257.14:36:07.25#abcon#<5=/14 1.3 3.6 17.47 971014.1\r\n> 2006.257.14:36:07.27#abcon#{5=INTERFACE CLEAR} 2006.257.14:36:07.33#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:36:13.14$setupk4/"tpicd 2006.257.14:36:13.14$setupk4/echo=off 2006.257.14:36:13.14$setupk4/xlog=off 2006.257.14:36:13.14:!2006.257.14:39:49 2006.257.14:39:49.00:preob 2006.257.14:39:49.14/onsource/TRACKING 2006.257.14:39:49.14:!2006.257.14:39:59 2006.257.14:39:59.00:"tape 2006.257.14:39:59.00:"st=record 2006.257.14:39:59.00:data_valid=on 2006.257.14:39:59.00:midob 2006.257.14:40:00.14/onsource/TRACKING 2006.257.14:40:00.14/wx/17.49,1014.1,97 2006.257.14:40:00.32/cable/+6.4815E-03 2006.257.14:40:01.41/va/01,08,usb,yes,30,32 2006.257.14:40:01.41/va/02,07,usb,yes,33,33 2006.257.14:40:01.41/va/03,08,usb,yes,29,31 2006.257.14:40:01.41/va/04,07,usb,yes,34,35 2006.257.14:40:01.41/va/05,04,usb,yes,30,30 2006.257.14:40:01.41/va/06,04,usb,yes,34,33 2006.257.14:40:01.41/va/07,04,usb,yes,34,35 2006.257.14:40:01.41/va/08,04,usb,yes,29,35 2006.257.14:40:01.64/valo/01,524.99,yes,locked 2006.257.14:40:01.64/valo/02,534.99,yes,locked 2006.257.14:40:01.64/valo/03,564.99,yes,locked 2006.257.14:40:01.64/valo/04,624.99,yes,locked 2006.257.14:40:01.64/valo/05,734.99,yes,locked 2006.257.14:40:01.64/valo/06,814.99,yes,locked 2006.257.14:40:01.64/valo/07,864.99,yes,locked 2006.257.14:40:01.64/valo/08,884.99,yes,locked 2006.257.14:40:02.73/vb/01,04,usb,yes,30,28 2006.257.14:40:02.73/vb/02,05,usb,yes,28,28 2006.257.14:40:02.73/vb/03,04,usb,yes,29,32 2006.257.14:40:02.73/vb/04,05,usb,yes,30,29 2006.257.14:40:02.73/vb/05,04,usb,yes,26,28 2006.257.14:40:02.73/vb/06,04,usb,yes,30,27 2006.257.14:40:02.73/vb/07,04,usb,yes,30,30 2006.257.14:40:02.73/vb/08,04,usb,yes,28,31 2006.257.14:40:02.97/vblo/01,629.99,yes,locked 2006.257.14:40:02.97/vblo/02,634.99,yes,locked 2006.257.14:40:02.97/vblo/03,649.99,yes,locked 2006.257.14:40:02.97/vblo/04,679.99,yes,locked 2006.257.14:40:02.97/vblo/05,709.99,yes,locked 2006.257.14:40:02.97/vblo/06,719.99,yes,locked 2006.257.14:40:02.97/vblo/07,734.99,yes,locked 2006.257.14:40:02.97/vblo/08,744.99,yes,locked 2006.257.14:40:03.12/vabw/8 2006.257.14:40:03.27/vbbw/8 2006.257.14:40:03.36/xfe/off,on,14.5 2006.257.14:40:03.75/ifatt/23,28,28,28 2006.257.14:40:04.07/fmout-gps/S +4.57E-07 2006.257.14:40:04.11:!2006.257.14:42:39 2006.257.14:42:39.01:data_valid=off 2006.257.14:42:39.01:"et 2006.257.14:42:39.02:!+3s 2006.257.14:42:42.03:"tape 2006.257.14:42:42.03:postob 2006.257.14:42:42.11/cable/+6.4832E-03 2006.257.14:42:42.11/wx/17.48,1014.1,97 2006.257.14:42:42.17/fmout-gps/S +4.57E-07 2006.257.14:42:42.17:scan_name=257-1448,jd0609,60 2006.257.14:42:42.18:source=0552+398,055530.81,394849.2,2000.0,cw 2006.257.14:42:44.14#flagr#flagr/antenna,new-source 2006.257.14:42:44.14:checkk5 2006.257.14:42:44.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:42:44.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:42:45.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:42:45.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:42:46.16/chk_obsdata//k5ts1/T2571439??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.14:42:46.56/chk_obsdata//k5ts2/T2571439??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.14:42:46.97/chk_obsdata//k5ts3/T2571439??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.14:42:47.38/chk_obsdata//k5ts4/T2571439??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.14:42:48.12/k5log//k5ts1_log_newline 2006.257.14:42:48.83/k5log//k5ts2_log_newline 2006.257.14:42:49.54/k5log//k5ts3_log_newline 2006.257.14:42:50.25/k5log//k5ts4_log_newline 2006.257.14:42:50.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:42:50.28:setupk4=1 2006.257.14:42:50.28$setupk4/echo=on 2006.257.14:42:50.28$setupk4/pcalon 2006.257.14:42:50.28$pcalon/"no phase cal control is implemented here 2006.257.14:42:50.28$setupk4/"tpicd=stop 2006.257.14:42:50.28$setupk4/"rec=synch_on 2006.257.14:42:50.28$setupk4/"rec_mode=128 2006.257.14:42:50.28$setupk4/!* 2006.257.14:42:50.28$setupk4/recpk4 2006.257.14:42:50.28$recpk4/recpatch= 2006.257.14:42:50.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:42:50.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:42:50.28$setupk4/vck44 2006.257.14:42:50.28$vck44/valo=1,524.99 2006.257.14:42:50.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.14:42:50.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.14:42:50.28#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:50.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:50.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:50.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:50.28#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:42:50.28#ibcon#first serial, iclass 12, count 0 2006.257.14:42:50.28#ibcon#enter sib2, iclass 12, count 0 2006.257.14:42:50.28#ibcon#flushed, iclass 12, count 0 2006.257.14:42:50.28#ibcon#about to write, iclass 12, count 0 2006.257.14:42:50.28#ibcon#wrote, iclass 12, count 0 2006.257.14:42:50.28#ibcon#about to read 3, iclass 12, count 0 2006.257.14:42:50.30#ibcon#read 3, iclass 12, count 0 2006.257.14:42:50.30#ibcon#about to read 4, iclass 12, count 0 2006.257.14:42:50.30#ibcon#read 4, iclass 12, count 0 2006.257.14:42:50.30#ibcon#about to read 5, iclass 12, count 0 2006.257.14:42:50.30#ibcon#read 5, iclass 12, count 0 2006.257.14:42:50.30#ibcon#about to read 6, iclass 12, count 0 2006.257.14:42:50.30#ibcon#read 6, iclass 12, count 0 2006.257.14:42:50.30#ibcon#end of sib2, iclass 12, count 0 2006.257.14:42:50.30#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:42:50.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:42:50.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:42:50.30#ibcon#*before write, iclass 12, count 0 2006.257.14:42:50.30#ibcon#enter sib2, iclass 12, count 0 2006.257.14:42:50.30#ibcon#flushed, iclass 12, count 0 2006.257.14:42:50.30#ibcon#about to write, iclass 12, count 0 2006.257.14:42:50.30#ibcon#wrote, iclass 12, count 0 2006.257.14:42:50.30#ibcon#about to read 3, iclass 12, count 0 2006.257.14:42:50.35#ibcon#read 3, iclass 12, count 0 2006.257.14:42:50.35#ibcon#about to read 4, iclass 12, count 0 2006.257.14:42:50.35#ibcon#read 4, iclass 12, count 0 2006.257.14:42:50.35#ibcon#about to read 5, iclass 12, count 0 2006.257.14:42:50.35#ibcon#read 5, iclass 12, count 0 2006.257.14:42:50.35#ibcon#about to read 6, iclass 12, count 0 2006.257.14:42:50.35#ibcon#read 6, iclass 12, count 0 2006.257.14:42:50.35#ibcon#end of sib2, iclass 12, count 0 2006.257.14:42:50.35#ibcon#*after write, iclass 12, count 0 2006.257.14:42:50.35#ibcon#*before return 0, iclass 12, count 0 2006.257.14:42:50.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:50.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:50.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:42:50.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:42:50.35$vck44/va=1,8 2006.257.14:42:50.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.14:42:50.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.14:42:50.35#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:50.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:50.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:50.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:50.35#ibcon#enter wrdev, iclass 14, count 2 2006.257.14:42:50.35#ibcon#first serial, iclass 14, count 2 2006.257.14:42:50.35#ibcon#enter sib2, iclass 14, count 2 2006.257.14:42:50.35#ibcon#flushed, iclass 14, count 2 2006.257.14:42:50.35#ibcon#about to write, iclass 14, count 2 2006.257.14:42:50.35#ibcon#wrote, iclass 14, count 2 2006.257.14:42:50.35#ibcon#about to read 3, iclass 14, count 2 2006.257.14:42:50.37#ibcon#read 3, iclass 14, count 2 2006.257.14:42:50.37#ibcon#about to read 4, iclass 14, count 2 2006.257.14:42:50.37#ibcon#read 4, iclass 14, count 2 2006.257.14:42:50.37#ibcon#about to read 5, iclass 14, count 2 2006.257.14:42:50.37#ibcon#read 5, iclass 14, count 2 2006.257.14:42:50.37#ibcon#about to read 6, iclass 14, count 2 2006.257.14:42:50.37#ibcon#read 6, iclass 14, count 2 2006.257.14:42:50.37#ibcon#end of sib2, iclass 14, count 2 2006.257.14:42:50.37#ibcon#*mode == 0, iclass 14, count 2 2006.257.14:42:50.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.14:42:50.37#ibcon#[25=AT01-08\r\n] 2006.257.14:42:50.37#ibcon#*before write, iclass 14, count 2 2006.257.14:42:50.37#ibcon#enter sib2, iclass 14, count 2 2006.257.14:42:50.37#ibcon#flushed, iclass 14, count 2 2006.257.14:42:50.37#ibcon#about to write, iclass 14, count 2 2006.257.14:42:50.37#ibcon#wrote, iclass 14, count 2 2006.257.14:42:50.37#ibcon#about to read 3, iclass 14, count 2 2006.257.14:42:50.40#ibcon#read 3, iclass 14, count 2 2006.257.14:42:50.40#ibcon#about to read 4, iclass 14, count 2 2006.257.14:42:50.40#ibcon#read 4, iclass 14, count 2 2006.257.14:42:50.40#ibcon#about to read 5, iclass 14, count 2 2006.257.14:42:50.40#ibcon#read 5, iclass 14, count 2 2006.257.14:42:50.40#ibcon#about to read 6, iclass 14, count 2 2006.257.14:42:50.40#ibcon#read 6, iclass 14, count 2 2006.257.14:42:50.40#ibcon#end of sib2, iclass 14, count 2 2006.257.14:42:50.40#ibcon#*after write, iclass 14, count 2 2006.257.14:42:50.40#ibcon#*before return 0, iclass 14, count 2 2006.257.14:42:50.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:50.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:50.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.14:42:50.40#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:50.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:50.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:50.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:50.52#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:42:50.52#ibcon#first serial, iclass 14, count 0 2006.257.14:42:50.52#ibcon#enter sib2, iclass 14, count 0 2006.257.14:42:50.52#ibcon#flushed, iclass 14, count 0 2006.257.14:42:50.52#ibcon#about to write, iclass 14, count 0 2006.257.14:42:50.52#ibcon#wrote, iclass 14, count 0 2006.257.14:42:50.52#ibcon#about to read 3, iclass 14, count 0 2006.257.14:42:50.54#ibcon#read 3, iclass 14, count 0 2006.257.14:42:50.54#ibcon#about to read 4, iclass 14, count 0 2006.257.14:42:50.54#ibcon#read 4, iclass 14, count 0 2006.257.14:42:50.54#ibcon#about to read 5, iclass 14, count 0 2006.257.14:42:50.54#ibcon#read 5, iclass 14, count 0 2006.257.14:42:50.54#ibcon#about to read 6, iclass 14, count 0 2006.257.14:42:50.54#ibcon#read 6, iclass 14, count 0 2006.257.14:42:50.54#ibcon#end of sib2, iclass 14, count 0 2006.257.14:42:50.54#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:42:50.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:42:50.54#ibcon#[25=USB\r\n] 2006.257.14:42:50.54#ibcon#*before write, iclass 14, count 0 2006.257.14:42:50.54#ibcon#enter sib2, iclass 14, count 0 2006.257.14:42:50.54#ibcon#flushed, iclass 14, count 0 2006.257.14:42:50.54#ibcon#about to write, iclass 14, count 0 2006.257.14:42:50.54#ibcon#wrote, iclass 14, count 0 2006.257.14:42:50.54#ibcon#about to read 3, iclass 14, count 0 2006.257.14:42:50.57#ibcon#read 3, iclass 14, count 0 2006.257.14:42:50.57#ibcon#about to read 4, iclass 14, count 0 2006.257.14:42:50.57#ibcon#read 4, iclass 14, count 0 2006.257.14:42:50.57#ibcon#about to read 5, iclass 14, count 0 2006.257.14:42:50.57#ibcon#read 5, iclass 14, count 0 2006.257.14:42:50.57#ibcon#about to read 6, iclass 14, count 0 2006.257.14:42:50.57#ibcon#read 6, iclass 14, count 0 2006.257.14:42:50.57#ibcon#end of sib2, iclass 14, count 0 2006.257.14:42:50.57#ibcon#*after write, iclass 14, count 0 2006.257.14:42:50.57#ibcon#*before return 0, iclass 14, count 0 2006.257.14:42:50.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:50.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:50.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:42:50.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:42:50.57$vck44/valo=2,534.99 2006.257.14:42:50.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.14:42:50.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.14:42:50.57#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:50.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:50.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:50.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:50.57#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:42:50.57#ibcon#first serial, iclass 16, count 0 2006.257.14:42:50.57#ibcon#enter sib2, iclass 16, count 0 2006.257.14:42:50.57#ibcon#flushed, iclass 16, count 0 2006.257.14:42:50.57#ibcon#about to write, iclass 16, count 0 2006.257.14:42:50.57#ibcon#wrote, iclass 16, count 0 2006.257.14:42:50.57#ibcon#about to read 3, iclass 16, count 0 2006.257.14:42:50.59#ibcon#read 3, iclass 16, count 0 2006.257.14:42:50.59#ibcon#about to read 4, iclass 16, count 0 2006.257.14:42:50.59#ibcon#read 4, iclass 16, count 0 2006.257.14:42:50.59#ibcon#about to read 5, iclass 16, count 0 2006.257.14:42:50.59#ibcon#read 5, iclass 16, count 0 2006.257.14:42:50.59#ibcon#about to read 6, iclass 16, count 0 2006.257.14:42:50.59#ibcon#read 6, iclass 16, count 0 2006.257.14:42:50.59#ibcon#end of sib2, iclass 16, count 0 2006.257.14:42:50.59#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:42:50.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:42:50.59#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:42:50.59#ibcon#*before write, iclass 16, count 0 2006.257.14:42:50.59#ibcon#enter sib2, iclass 16, count 0 2006.257.14:42:50.59#ibcon#flushed, iclass 16, count 0 2006.257.14:42:50.59#ibcon#about to write, iclass 16, count 0 2006.257.14:42:50.59#ibcon#wrote, iclass 16, count 0 2006.257.14:42:50.59#ibcon#about to read 3, iclass 16, count 0 2006.257.14:42:50.63#ibcon#read 3, iclass 16, count 0 2006.257.14:42:50.63#ibcon#about to read 4, iclass 16, count 0 2006.257.14:42:50.63#ibcon#read 4, iclass 16, count 0 2006.257.14:42:50.63#ibcon#about to read 5, iclass 16, count 0 2006.257.14:42:50.63#ibcon#read 5, iclass 16, count 0 2006.257.14:42:50.63#ibcon#about to read 6, iclass 16, count 0 2006.257.14:42:50.63#ibcon#read 6, iclass 16, count 0 2006.257.14:42:50.63#ibcon#end of sib2, iclass 16, count 0 2006.257.14:42:50.63#ibcon#*after write, iclass 16, count 0 2006.257.14:42:50.63#ibcon#*before return 0, iclass 16, count 0 2006.257.14:42:50.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:50.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:50.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:42:50.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:42:50.63$vck44/va=2,7 2006.257.14:42:50.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.14:42:50.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.14:42:50.63#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:50.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:50.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:50.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:50.69#ibcon#enter wrdev, iclass 18, count 2 2006.257.14:42:50.69#ibcon#first serial, iclass 18, count 2 2006.257.14:42:50.69#ibcon#enter sib2, iclass 18, count 2 2006.257.14:42:50.69#ibcon#flushed, iclass 18, count 2 2006.257.14:42:50.69#ibcon#about to write, iclass 18, count 2 2006.257.14:42:50.69#ibcon#wrote, iclass 18, count 2 2006.257.14:42:50.69#ibcon#about to read 3, iclass 18, count 2 2006.257.14:42:50.71#ibcon#read 3, iclass 18, count 2 2006.257.14:42:50.71#ibcon#about to read 4, iclass 18, count 2 2006.257.14:42:50.71#ibcon#read 4, iclass 18, count 2 2006.257.14:42:50.71#ibcon#about to read 5, iclass 18, count 2 2006.257.14:42:50.71#ibcon#read 5, iclass 18, count 2 2006.257.14:42:50.71#ibcon#about to read 6, iclass 18, count 2 2006.257.14:42:50.71#ibcon#read 6, iclass 18, count 2 2006.257.14:42:50.71#ibcon#end of sib2, iclass 18, count 2 2006.257.14:42:50.71#ibcon#*mode == 0, iclass 18, count 2 2006.257.14:42:50.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.14:42:50.71#ibcon#[25=AT02-07\r\n] 2006.257.14:42:50.71#ibcon#*before write, iclass 18, count 2 2006.257.14:42:50.71#ibcon#enter sib2, iclass 18, count 2 2006.257.14:42:50.71#ibcon#flushed, iclass 18, count 2 2006.257.14:42:50.71#ibcon#about to write, iclass 18, count 2 2006.257.14:42:50.71#ibcon#wrote, iclass 18, count 2 2006.257.14:42:50.71#ibcon#about to read 3, iclass 18, count 2 2006.257.14:42:50.74#ibcon#read 3, iclass 18, count 2 2006.257.14:42:50.74#ibcon#about to read 4, iclass 18, count 2 2006.257.14:42:50.74#ibcon#read 4, iclass 18, count 2 2006.257.14:42:50.74#ibcon#about to read 5, iclass 18, count 2 2006.257.14:42:50.74#ibcon#read 5, iclass 18, count 2 2006.257.14:42:50.74#ibcon#about to read 6, iclass 18, count 2 2006.257.14:42:50.74#ibcon#read 6, iclass 18, count 2 2006.257.14:42:50.74#ibcon#end of sib2, iclass 18, count 2 2006.257.14:42:50.74#ibcon#*after write, iclass 18, count 2 2006.257.14:42:50.74#ibcon#*before return 0, iclass 18, count 2 2006.257.14:42:50.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:50.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:50.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.14:42:50.74#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:50.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:50.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:50.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:50.86#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:42:50.86#ibcon#first serial, iclass 18, count 0 2006.257.14:42:50.86#ibcon#enter sib2, iclass 18, count 0 2006.257.14:42:50.86#ibcon#flushed, iclass 18, count 0 2006.257.14:42:50.86#ibcon#about to write, iclass 18, count 0 2006.257.14:42:50.86#ibcon#wrote, iclass 18, count 0 2006.257.14:42:50.86#ibcon#about to read 3, iclass 18, count 0 2006.257.14:42:50.88#ibcon#read 3, iclass 18, count 0 2006.257.14:42:50.88#ibcon#about to read 4, iclass 18, count 0 2006.257.14:42:50.88#ibcon#read 4, iclass 18, count 0 2006.257.14:42:50.88#ibcon#about to read 5, iclass 18, count 0 2006.257.14:42:50.88#ibcon#read 5, iclass 18, count 0 2006.257.14:42:50.88#ibcon#about to read 6, iclass 18, count 0 2006.257.14:42:50.88#ibcon#read 6, iclass 18, count 0 2006.257.14:42:50.88#ibcon#end of sib2, iclass 18, count 0 2006.257.14:42:50.88#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:42:50.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:42:50.88#ibcon#[25=USB\r\n] 2006.257.14:42:50.88#ibcon#*before write, iclass 18, count 0 2006.257.14:42:50.88#ibcon#enter sib2, iclass 18, count 0 2006.257.14:42:50.88#ibcon#flushed, iclass 18, count 0 2006.257.14:42:50.88#ibcon#about to write, iclass 18, count 0 2006.257.14:42:50.88#ibcon#wrote, iclass 18, count 0 2006.257.14:42:50.88#ibcon#about to read 3, iclass 18, count 0 2006.257.14:42:50.91#ibcon#read 3, iclass 18, count 0 2006.257.14:42:50.91#ibcon#about to read 4, iclass 18, count 0 2006.257.14:42:50.91#ibcon#read 4, iclass 18, count 0 2006.257.14:42:50.91#ibcon#about to read 5, iclass 18, count 0 2006.257.14:42:50.91#ibcon#read 5, iclass 18, count 0 2006.257.14:42:50.91#ibcon#about to read 6, iclass 18, count 0 2006.257.14:42:50.91#ibcon#read 6, iclass 18, count 0 2006.257.14:42:50.91#ibcon#end of sib2, iclass 18, count 0 2006.257.14:42:50.91#ibcon#*after write, iclass 18, count 0 2006.257.14:42:50.91#ibcon#*before return 0, iclass 18, count 0 2006.257.14:42:50.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:50.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:50.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:42:50.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:42:50.91$vck44/valo=3,564.99 2006.257.14:42:50.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.14:42:50.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.14:42:50.91#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:50.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:50.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:50.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:50.91#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:42:50.91#ibcon#first serial, iclass 20, count 0 2006.257.14:42:50.91#ibcon#enter sib2, iclass 20, count 0 2006.257.14:42:50.91#ibcon#flushed, iclass 20, count 0 2006.257.14:42:50.91#ibcon#about to write, iclass 20, count 0 2006.257.14:42:50.91#ibcon#wrote, iclass 20, count 0 2006.257.14:42:50.91#ibcon#about to read 3, iclass 20, count 0 2006.257.14:42:50.93#ibcon#read 3, iclass 20, count 0 2006.257.14:42:50.93#ibcon#about to read 4, iclass 20, count 0 2006.257.14:42:50.93#ibcon#read 4, iclass 20, count 0 2006.257.14:42:50.93#ibcon#about to read 5, iclass 20, count 0 2006.257.14:42:50.93#ibcon#read 5, iclass 20, count 0 2006.257.14:42:50.93#ibcon#about to read 6, iclass 20, count 0 2006.257.14:42:50.93#ibcon#read 6, iclass 20, count 0 2006.257.14:42:50.93#ibcon#end of sib2, iclass 20, count 0 2006.257.14:42:50.93#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:42:50.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:42:50.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:42:50.93#ibcon#*before write, iclass 20, count 0 2006.257.14:42:50.93#ibcon#enter sib2, iclass 20, count 0 2006.257.14:42:50.93#ibcon#flushed, iclass 20, count 0 2006.257.14:42:50.93#ibcon#about to write, iclass 20, count 0 2006.257.14:42:50.93#ibcon#wrote, iclass 20, count 0 2006.257.14:42:50.93#ibcon#about to read 3, iclass 20, count 0 2006.257.14:42:50.97#ibcon#read 3, iclass 20, count 0 2006.257.14:42:50.97#ibcon#about to read 4, iclass 20, count 0 2006.257.14:42:50.97#ibcon#read 4, iclass 20, count 0 2006.257.14:42:50.97#ibcon#about to read 5, iclass 20, count 0 2006.257.14:42:50.97#ibcon#read 5, iclass 20, count 0 2006.257.14:42:50.97#ibcon#about to read 6, iclass 20, count 0 2006.257.14:42:50.97#ibcon#read 6, iclass 20, count 0 2006.257.14:42:50.97#ibcon#end of sib2, iclass 20, count 0 2006.257.14:42:50.97#ibcon#*after write, iclass 20, count 0 2006.257.14:42:50.97#ibcon#*before return 0, iclass 20, count 0 2006.257.14:42:50.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:50.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:50.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:42:50.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:42:50.97$vck44/va=3,8 2006.257.14:42:50.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.14:42:50.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.14:42:50.97#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:50.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:42:51.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:42:51.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:42:51.03#ibcon#enter wrdev, iclass 22, count 2 2006.257.14:42:51.03#ibcon#first serial, iclass 22, count 2 2006.257.14:42:51.03#ibcon#enter sib2, iclass 22, count 2 2006.257.14:42:51.03#ibcon#flushed, iclass 22, count 2 2006.257.14:42:51.03#ibcon#about to write, iclass 22, count 2 2006.257.14:42:51.03#ibcon#wrote, iclass 22, count 2 2006.257.14:42:51.03#ibcon#about to read 3, iclass 22, count 2 2006.257.14:42:51.05#ibcon#read 3, iclass 22, count 2 2006.257.14:42:51.05#ibcon#about to read 4, iclass 22, count 2 2006.257.14:42:51.05#ibcon#read 4, iclass 22, count 2 2006.257.14:42:51.05#ibcon#about to read 5, iclass 22, count 2 2006.257.14:42:51.05#ibcon#read 5, iclass 22, count 2 2006.257.14:42:51.05#ibcon#about to read 6, iclass 22, count 2 2006.257.14:42:51.05#ibcon#read 6, iclass 22, count 2 2006.257.14:42:51.05#ibcon#end of sib2, iclass 22, count 2 2006.257.14:42:51.05#ibcon#*mode == 0, iclass 22, count 2 2006.257.14:42:51.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.14:42:51.05#ibcon#[25=AT03-08\r\n] 2006.257.14:42:51.05#ibcon#*before write, iclass 22, count 2 2006.257.14:42:51.05#ibcon#enter sib2, iclass 22, count 2 2006.257.14:42:51.05#ibcon#flushed, iclass 22, count 2 2006.257.14:42:51.05#ibcon#about to write, iclass 22, count 2 2006.257.14:42:51.05#ibcon#wrote, iclass 22, count 2 2006.257.14:42:51.05#ibcon#about to read 3, iclass 22, count 2 2006.257.14:42:51.08#ibcon#read 3, iclass 22, count 2 2006.257.14:42:51.08#ibcon#about to read 4, iclass 22, count 2 2006.257.14:42:51.08#ibcon#read 4, iclass 22, count 2 2006.257.14:42:51.08#ibcon#about to read 5, iclass 22, count 2 2006.257.14:42:51.08#ibcon#read 5, iclass 22, count 2 2006.257.14:42:51.08#ibcon#about to read 6, iclass 22, count 2 2006.257.14:42:51.08#ibcon#read 6, iclass 22, count 2 2006.257.14:42:51.08#ibcon#end of sib2, iclass 22, count 2 2006.257.14:42:51.08#ibcon#*after write, iclass 22, count 2 2006.257.14:42:51.08#ibcon#*before return 0, iclass 22, count 2 2006.257.14:42:51.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:42:51.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:42:51.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.14:42:51.08#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:51.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:42:51.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:42:51.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:42:51.20#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:42:51.20#ibcon#first serial, iclass 22, count 0 2006.257.14:42:51.20#ibcon#enter sib2, iclass 22, count 0 2006.257.14:42:51.20#ibcon#flushed, iclass 22, count 0 2006.257.14:42:51.20#ibcon#about to write, iclass 22, count 0 2006.257.14:42:51.20#ibcon#wrote, iclass 22, count 0 2006.257.14:42:51.20#ibcon#about to read 3, iclass 22, count 0 2006.257.14:42:51.22#ibcon#read 3, iclass 22, count 0 2006.257.14:42:51.22#ibcon#about to read 4, iclass 22, count 0 2006.257.14:42:51.22#ibcon#read 4, iclass 22, count 0 2006.257.14:42:51.22#ibcon#about to read 5, iclass 22, count 0 2006.257.14:42:51.22#ibcon#read 5, iclass 22, count 0 2006.257.14:42:51.22#ibcon#about to read 6, iclass 22, count 0 2006.257.14:42:51.22#ibcon#read 6, iclass 22, count 0 2006.257.14:42:51.22#ibcon#end of sib2, iclass 22, count 0 2006.257.14:42:51.22#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:42:51.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:42:51.22#ibcon#[25=USB\r\n] 2006.257.14:42:51.22#ibcon#*before write, iclass 22, count 0 2006.257.14:42:51.22#ibcon#enter sib2, iclass 22, count 0 2006.257.14:42:51.22#ibcon#flushed, iclass 22, count 0 2006.257.14:42:51.22#ibcon#about to write, iclass 22, count 0 2006.257.14:42:51.22#ibcon#wrote, iclass 22, count 0 2006.257.14:42:51.22#ibcon#about to read 3, iclass 22, count 0 2006.257.14:42:51.25#ibcon#read 3, iclass 22, count 0 2006.257.14:42:51.25#ibcon#about to read 4, iclass 22, count 0 2006.257.14:42:51.25#ibcon#read 4, iclass 22, count 0 2006.257.14:42:51.25#ibcon#about to read 5, iclass 22, count 0 2006.257.14:42:51.25#ibcon#read 5, iclass 22, count 0 2006.257.14:42:51.25#ibcon#about to read 6, iclass 22, count 0 2006.257.14:42:51.25#ibcon#read 6, iclass 22, count 0 2006.257.14:42:51.25#ibcon#end of sib2, iclass 22, count 0 2006.257.14:42:51.25#ibcon#*after write, iclass 22, count 0 2006.257.14:42:51.25#ibcon#*before return 0, iclass 22, count 0 2006.257.14:42:51.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:42:51.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:42:51.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:42:51.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:42:51.25$vck44/valo=4,624.99 2006.257.14:42:51.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.14:42:51.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.14:42:51.25#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:51.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:42:51.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:42:51.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:42:51.25#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:42:51.25#ibcon#first serial, iclass 24, count 0 2006.257.14:42:51.25#ibcon#enter sib2, iclass 24, count 0 2006.257.14:42:51.25#ibcon#flushed, iclass 24, count 0 2006.257.14:42:51.25#ibcon#about to write, iclass 24, count 0 2006.257.14:42:51.25#ibcon#wrote, iclass 24, count 0 2006.257.14:42:51.25#ibcon#about to read 3, iclass 24, count 0 2006.257.14:42:51.27#ibcon#read 3, iclass 24, count 0 2006.257.14:42:51.27#ibcon#about to read 4, iclass 24, count 0 2006.257.14:42:51.27#ibcon#read 4, iclass 24, count 0 2006.257.14:42:51.27#ibcon#about to read 5, iclass 24, count 0 2006.257.14:42:51.27#ibcon#read 5, iclass 24, count 0 2006.257.14:42:51.27#ibcon#about to read 6, iclass 24, count 0 2006.257.14:42:51.27#ibcon#read 6, iclass 24, count 0 2006.257.14:42:51.27#ibcon#end of sib2, iclass 24, count 0 2006.257.14:42:51.27#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:42:51.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:42:51.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:42:51.27#ibcon#*before write, iclass 24, count 0 2006.257.14:42:51.27#ibcon#enter sib2, iclass 24, count 0 2006.257.14:42:51.27#ibcon#flushed, iclass 24, count 0 2006.257.14:42:51.27#ibcon#about to write, iclass 24, count 0 2006.257.14:42:51.27#ibcon#wrote, iclass 24, count 0 2006.257.14:42:51.27#ibcon#about to read 3, iclass 24, count 0 2006.257.14:42:51.31#ibcon#read 3, iclass 24, count 0 2006.257.14:42:51.31#ibcon#about to read 4, iclass 24, count 0 2006.257.14:42:51.31#ibcon#read 4, iclass 24, count 0 2006.257.14:42:51.31#ibcon#about to read 5, iclass 24, count 0 2006.257.14:42:51.31#ibcon#read 5, iclass 24, count 0 2006.257.14:42:51.31#ibcon#about to read 6, iclass 24, count 0 2006.257.14:42:51.31#ibcon#read 6, iclass 24, count 0 2006.257.14:42:51.31#ibcon#end of sib2, iclass 24, count 0 2006.257.14:42:51.31#ibcon#*after write, iclass 24, count 0 2006.257.14:42:51.31#ibcon#*before return 0, iclass 24, count 0 2006.257.14:42:51.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:42:51.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:42:51.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:42:51.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:42:51.31$vck44/va=4,7 2006.257.14:42:51.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.14:42:51.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.14:42:51.31#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:51.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:42:51.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:42:51.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:42:51.37#ibcon#enter wrdev, iclass 26, count 2 2006.257.14:42:51.37#ibcon#first serial, iclass 26, count 2 2006.257.14:42:51.37#ibcon#enter sib2, iclass 26, count 2 2006.257.14:42:51.37#ibcon#flushed, iclass 26, count 2 2006.257.14:42:51.37#ibcon#about to write, iclass 26, count 2 2006.257.14:42:51.37#ibcon#wrote, iclass 26, count 2 2006.257.14:42:51.37#ibcon#about to read 3, iclass 26, count 2 2006.257.14:42:51.39#ibcon#read 3, iclass 26, count 2 2006.257.14:42:51.39#ibcon#about to read 4, iclass 26, count 2 2006.257.14:42:51.39#ibcon#read 4, iclass 26, count 2 2006.257.14:42:51.39#ibcon#about to read 5, iclass 26, count 2 2006.257.14:42:51.39#ibcon#read 5, iclass 26, count 2 2006.257.14:42:51.39#ibcon#about to read 6, iclass 26, count 2 2006.257.14:42:51.39#ibcon#read 6, iclass 26, count 2 2006.257.14:42:51.39#ibcon#end of sib2, iclass 26, count 2 2006.257.14:42:51.39#ibcon#*mode == 0, iclass 26, count 2 2006.257.14:42:51.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.14:42:51.39#ibcon#[25=AT04-07\r\n] 2006.257.14:42:51.39#ibcon#*before write, iclass 26, count 2 2006.257.14:42:51.39#ibcon#enter sib2, iclass 26, count 2 2006.257.14:42:51.39#ibcon#flushed, iclass 26, count 2 2006.257.14:42:51.39#ibcon#about to write, iclass 26, count 2 2006.257.14:42:51.39#ibcon#wrote, iclass 26, count 2 2006.257.14:42:51.39#ibcon#about to read 3, iclass 26, count 2 2006.257.14:42:51.42#ibcon#read 3, iclass 26, count 2 2006.257.14:42:51.42#ibcon#about to read 4, iclass 26, count 2 2006.257.14:42:51.42#ibcon#read 4, iclass 26, count 2 2006.257.14:42:51.42#ibcon#about to read 5, iclass 26, count 2 2006.257.14:42:51.42#ibcon#read 5, iclass 26, count 2 2006.257.14:42:51.42#ibcon#about to read 6, iclass 26, count 2 2006.257.14:42:51.42#ibcon#read 6, iclass 26, count 2 2006.257.14:42:51.42#ibcon#end of sib2, iclass 26, count 2 2006.257.14:42:51.42#ibcon#*after write, iclass 26, count 2 2006.257.14:42:51.42#ibcon#*before return 0, iclass 26, count 2 2006.257.14:42:51.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:42:51.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:42:51.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.14:42:51.42#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:51.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:42:51.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:42:51.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:42:51.54#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:42:51.54#ibcon#first serial, iclass 26, count 0 2006.257.14:42:51.54#ibcon#enter sib2, iclass 26, count 0 2006.257.14:42:51.54#ibcon#flushed, iclass 26, count 0 2006.257.14:42:51.54#ibcon#about to write, iclass 26, count 0 2006.257.14:42:51.54#ibcon#wrote, iclass 26, count 0 2006.257.14:42:51.54#ibcon#about to read 3, iclass 26, count 0 2006.257.14:42:51.56#ibcon#read 3, iclass 26, count 0 2006.257.14:42:51.56#ibcon#about to read 4, iclass 26, count 0 2006.257.14:42:51.56#ibcon#read 4, iclass 26, count 0 2006.257.14:42:51.56#ibcon#about to read 5, iclass 26, count 0 2006.257.14:42:51.56#ibcon#read 5, iclass 26, count 0 2006.257.14:42:51.56#ibcon#about to read 6, iclass 26, count 0 2006.257.14:42:51.56#ibcon#read 6, iclass 26, count 0 2006.257.14:42:51.56#ibcon#end of sib2, iclass 26, count 0 2006.257.14:42:51.56#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:42:51.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:42:51.56#ibcon#[25=USB\r\n] 2006.257.14:42:51.56#ibcon#*before write, iclass 26, count 0 2006.257.14:42:51.56#ibcon#enter sib2, iclass 26, count 0 2006.257.14:42:51.56#ibcon#flushed, iclass 26, count 0 2006.257.14:42:51.56#ibcon#about to write, iclass 26, count 0 2006.257.14:42:51.56#ibcon#wrote, iclass 26, count 0 2006.257.14:42:51.56#ibcon#about to read 3, iclass 26, count 0 2006.257.14:42:51.59#ibcon#read 3, iclass 26, count 0 2006.257.14:42:51.59#ibcon#about to read 4, iclass 26, count 0 2006.257.14:42:51.59#ibcon#read 4, iclass 26, count 0 2006.257.14:42:51.59#ibcon#about to read 5, iclass 26, count 0 2006.257.14:42:51.59#ibcon#read 5, iclass 26, count 0 2006.257.14:42:51.59#ibcon#about to read 6, iclass 26, count 0 2006.257.14:42:51.59#ibcon#read 6, iclass 26, count 0 2006.257.14:42:51.59#ibcon#end of sib2, iclass 26, count 0 2006.257.14:42:51.59#ibcon#*after write, iclass 26, count 0 2006.257.14:42:51.59#ibcon#*before return 0, iclass 26, count 0 2006.257.14:42:51.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:42:51.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:42:51.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:42:51.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:42:51.59$vck44/valo=5,734.99 2006.257.14:42:51.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.14:42:51.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.14:42:51.59#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:51.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:51.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:51.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:51.59#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:42:51.59#ibcon#first serial, iclass 28, count 0 2006.257.14:42:51.59#ibcon#enter sib2, iclass 28, count 0 2006.257.14:42:51.59#ibcon#flushed, iclass 28, count 0 2006.257.14:42:51.59#ibcon#about to write, iclass 28, count 0 2006.257.14:42:51.59#ibcon#wrote, iclass 28, count 0 2006.257.14:42:51.59#ibcon#about to read 3, iclass 28, count 0 2006.257.14:42:51.61#ibcon#read 3, iclass 28, count 0 2006.257.14:42:51.61#ibcon#about to read 4, iclass 28, count 0 2006.257.14:42:51.61#ibcon#read 4, iclass 28, count 0 2006.257.14:42:51.61#ibcon#about to read 5, iclass 28, count 0 2006.257.14:42:51.61#ibcon#read 5, iclass 28, count 0 2006.257.14:42:51.61#ibcon#about to read 6, iclass 28, count 0 2006.257.14:42:51.61#ibcon#read 6, iclass 28, count 0 2006.257.14:42:51.61#ibcon#end of sib2, iclass 28, count 0 2006.257.14:42:51.61#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:42:51.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:42:51.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:42:51.61#ibcon#*before write, iclass 28, count 0 2006.257.14:42:51.61#ibcon#enter sib2, iclass 28, count 0 2006.257.14:42:51.61#ibcon#flushed, iclass 28, count 0 2006.257.14:42:51.61#ibcon#about to write, iclass 28, count 0 2006.257.14:42:51.61#ibcon#wrote, iclass 28, count 0 2006.257.14:42:51.61#ibcon#about to read 3, iclass 28, count 0 2006.257.14:42:51.65#ibcon#read 3, iclass 28, count 0 2006.257.14:42:51.65#ibcon#about to read 4, iclass 28, count 0 2006.257.14:42:51.65#ibcon#read 4, iclass 28, count 0 2006.257.14:42:51.65#ibcon#about to read 5, iclass 28, count 0 2006.257.14:42:51.65#ibcon#read 5, iclass 28, count 0 2006.257.14:42:51.65#ibcon#about to read 6, iclass 28, count 0 2006.257.14:42:51.65#ibcon#read 6, iclass 28, count 0 2006.257.14:42:51.65#ibcon#end of sib2, iclass 28, count 0 2006.257.14:42:51.65#ibcon#*after write, iclass 28, count 0 2006.257.14:42:51.65#ibcon#*before return 0, iclass 28, count 0 2006.257.14:42:51.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:51.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:51.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:42:51.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:42:51.65$vck44/va=5,4 2006.257.14:42:51.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.14:42:51.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.14:42:51.65#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:51.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:51.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:51.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:51.71#ibcon#enter wrdev, iclass 30, count 2 2006.257.14:42:51.71#ibcon#first serial, iclass 30, count 2 2006.257.14:42:51.71#ibcon#enter sib2, iclass 30, count 2 2006.257.14:42:51.71#ibcon#flushed, iclass 30, count 2 2006.257.14:42:51.71#ibcon#about to write, iclass 30, count 2 2006.257.14:42:51.71#ibcon#wrote, iclass 30, count 2 2006.257.14:42:51.71#ibcon#about to read 3, iclass 30, count 2 2006.257.14:42:51.73#ibcon#read 3, iclass 30, count 2 2006.257.14:42:51.73#ibcon#about to read 4, iclass 30, count 2 2006.257.14:42:51.73#ibcon#read 4, iclass 30, count 2 2006.257.14:42:51.73#ibcon#about to read 5, iclass 30, count 2 2006.257.14:42:51.73#ibcon#read 5, iclass 30, count 2 2006.257.14:42:51.73#ibcon#about to read 6, iclass 30, count 2 2006.257.14:42:51.73#ibcon#read 6, iclass 30, count 2 2006.257.14:42:51.73#ibcon#end of sib2, iclass 30, count 2 2006.257.14:42:51.73#ibcon#*mode == 0, iclass 30, count 2 2006.257.14:42:51.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.14:42:51.73#ibcon#[25=AT05-04\r\n] 2006.257.14:42:51.73#ibcon#*before write, iclass 30, count 2 2006.257.14:42:51.73#ibcon#enter sib2, iclass 30, count 2 2006.257.14:42:51.73#ibcon#flushed, iclass 30, count 2 2006.257.14:42:51.73#ibcon#about to write, iclass 30, count 2 2006.257.14:42:51.73#ibcon#wrote, iclass 30, count 2 2006.257.14:42:51.73#ibcon#about to read 3, iclass 30, count 2 2006.257.14:42:51.76#ibcon#read 3, iclass 30, count 2 2006.257.14:42:51.76#ibcon#about to read 4, iclass 30, count 2 2006.257.14:42:51.76#ibcon#read 4, iclass 30, count 2 2006.257.14:42:51.76#ibcon#about to read 5, iclass 30, count 2 2006.257.14:42:51.76#ibcon#read 5, iclass 30, count 2 2006.257.14:42:51.76#ibcon#about to read 6, iclass 30, count 2 2006.257.14:42:51.76#ibcon#read 6, iclass 30, count 2 2006.257.14:42:51.76#ibcon#end of sib2, iclass 30, count 2 2006.257.14:42:51.76#ibcon#*after write, iclass 30, count 2 2006.257.14:42:51.76#ibcon#*before return 0, iclass 30, count 2 2006.257.14:42:51.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:51.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:51.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.14:42:51.76#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:51.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:51.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:51.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:51.88#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:42:51.88#ibcon#first serial, iclass 30, count 0 2006.257.14:42:51.88#ibcon#enter sib2, iclass 30, count 0 2006.257.14:42:51.88#ibcon#flushed, iclass 30, count 0 2006.257.14:42:51.88#ibcon#about to write, iclass 30, count 0 2006.257.14:42:51.88#ibcon#wrote, iclass 30, count 0 2006.257.14:42:51.88#ibcon#about to read 3, iclass 30, count 0 2006.257.14:42:51.90#ibcon#read 3, iclass 30, count 0 2006.257.14:42:51.90#ibcon#about to read 4, iclass 30, count 0 2006.257.14:42:51.90#ibcon#read 4, iclass 30, count 0 2006.257.14:42:51.90#ibcon#about to read 5, iclass 30, count 0 2006.257.14:42:51.90#ibcon#read 5, iclass 30, count 0 2006.257.14:42:51.90#ibcon#about to read 6, iclass 30, count 0 2006.257.14:42:51.90#ibcon#read 6, iclass 30, count 0 2006.257.14:42:51.90#ibcon#end of sib2, iclass 30, count 0 2006.257.14:42:51.90#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:42:51.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:42:51.90#ibcon#[25=USB\r\n] 2006.257.14:42:51.90#ibcon#*before write, iclass 30, count 0 2006.257.14:42:51.90#ibcon#enter sib2, iclass 30, count 0 2006.257.14:42:51.90#ibcon#flushed, iclass 30, count 0 2006.257.14:42:51.90#ibcon#about to write, iclass 30, count 0 2006.257.14:42:51.90#ibcon#wrote, iclass 30, count 0 2006.257.14:42:51.90#ibcon#about to read 3, iclass 30, count 0 2006.257.14:42:51.93#ibcon#read 3, iclass 30, count 0 2006.257.14:42:51.93#ibcon#about to read 4, iclass 30, count 0 2006.257.14:42:51.93#ibcon#read 4, iclass 30, count 0 2006.257.14:42:51.93#ibcon#about to read 5, iclass 30, count 0 2006.257.14:42:51.93#ibcon#read 5, iclass 30, count 0 2006.257.14:42:51.93#ibcon#about to read 6, iclass 30, count 0 2006.257.14:42:51.93#ibcon#read 6, iclass 30, count 0 2006.257.14:42:51.93#ibcon#end of sib2, iclass 30, count 0 2006.257.14:42:51.93#ibcon#*after write, iclass 30, count 0 2006.257.14:42:51.93#ibcon#*before return 0, iclass 30, count 0 2006.257.14:42:51.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:51.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:51.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:42:51.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:42:51.93$vck44/valo=6,814.99 2006.257.14:42:51.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.14:42:51.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.14:42:51.93#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:51.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:51.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:51.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:51.93#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:42:51.93#ibcon#first serial, iclass 32, count 0 2006.257.14:42:51.93#ibcon#enter sib2, iclass 32, count 0 2006.257.14:42:51.93#ibcon#flushed, iclass 32, count 0 2006.257.14:42:51.93#ibcon#about to write, iclass 32, count 0 2006.257.14:42:51.93#ibcon#wrote, iclass 32, count 0 2006.257.14:42:51.93#ibcon#about to read 3, iclass 32, count 0 2006.257.14:42:51.95#ibcon#read 3, iclass 32, count 0 2006.257.14:42:51.95#ibcon#about to read 4, iclass 32, count 0 2006.257.14:42:51.95#ibcon#read 4, iclass 32, count 0 2006.257.14:42:51.95#ibcon#about to read 5, iclass 32, count 0 2006.257.14:42:51.95#ibcon#read 5, iclass 32, count 0 2006.257.14:42:51.95#ibcon#about to read 6, iclass 32, count 0 2006.257.14:42:51.95#ibcon#read 6, iclass 32, count 0 2006.257.14:42:51.95#ibcon#end of sib2, iclass 32, count 0 2006.257.14:42:51.95#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:42:51.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:42:51.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:42:51.95#ibcon#*before write, iclass 32, count 0 2006.257.14:42:51.95#ibcon#enter sib2, iclass 32, count 0 2006.257.14:42:51.95#ibcon#flushed, iclass 32, count 0 2006.257.14:42:51.95#ibcon#about to write, iclass 32, count 0 2006.257.14:42:51.95#ibcon#wrote, iclass 32, count 0 2006.257.14:42:51.95#ibcon#about to read 3, iclass 32, count 0 2006.257.14:42:51.99#ibcon#read 3, iclass 32, count 0 2006.257.14:42:51.99#ibcon#about to read 4, iclass 32, count 0 2006.257.14:42:51.99#ibcon#read 4, iclass 32, count 0 2006.257.14:42:51.99#ibcon#about to read 5, iclass 32, count 0 2006.257.14:42:51.99#ibcon#read 5, iclass 32, count 0 2006.257.14:42:51.99#ibcon#about to read 6, iclass 32, count 0 2006.257.14:42:51.99#ibcon#read 6, iclass 32, count 0 2006.257.14:42:51.99#ibcon#end of sib2, iclass 32, count 0 2006.257.14:42:51.99#ibcon#*after write, iclass 32, count 0 2006.257.14:42:51.99#ibcon#*before return 0, iclass 32, count 0 2006.257.14:42:51.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:51.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:51.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:42:51.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:42:51.99$vck44/va=6,4 2006.257.14:42:51.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.14:42:51.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.14:42:51.99#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:51.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:52.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:52.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:52.05#ibcon#enter wrdev, iclass 34, count 2 2006.257.14:42:52.05#ibcon#first serial, iclass 34, count 2 2006.257.14:42:52.05#ibcon#enter sib2, iclass 34, count 2 2006.257.14:42:52.05#ibcon#flushed, iclass 34, count 2 2006.257.14:42:52.05#ibcon#about to write, iclass 34, count 2 2006.257.14:42:52.05#ibcon#wrote, iclass 34, count 2 2006.257.14:42:52.05#ibcon#about to read 3, iclass 34, count 2 2006.257.14:42:52.07#ibcon#read 3, iclass 34, count 2 2006.257.14:42:52.07#ibcon#about to read 4, iclass 34, count 2 2006.257.14:42:52.07#ibcon#read 4, iclass 34, count 2 2006.257.14:42:52.07#ibcon#about to read 5, iclass 34, count 2 2006.257.14:42:52.07#ibcon#read 5, iclass 34, count 2 2006.257.14:42:52.07#ibcon#about to read 6, iclass 34, count 2 2006.257.14:42:52.07#ibcon#read 6, iclass 34, count 2 2006.257.14:42:52.07#ibcon#end of sib2, iclass 34, count 2 2006.257.14:42:52.07#ibcon#*mode == 0, iclass 34, count 2 2006.257.14:42:52.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.14:42:52.07#ibcon#[25=AT06-04\r\n] 2006.257.14:42:52.07#ibcon#*before write, iclass 34, count 2 2006.257.14:42:52.07#ibcon#enter sib2, iclass 34, count 2 2006.257.14:42:52.07#ibcon#flushed, iclass 34, count 2 2006.257.14:42:52.07#ibcon#about to write, iclass 34, count 2 2006.257.14:42:52.07#ibcon#wrote, iclass 34, count 2 2006.257.14:42:52.07#ibcon#about to read 3, iclass 34, count 2 2006.257.14:42:52.10#ibcon#read 3, iclass 34, count 2 2006.257.14:42:52.10#ibcon#about to read 4, iclass 34, count 2 2006.257.14:42:52.10#ibcon#read 4, iclass 34, count 2 2006.257.14:42:52.10#ibcon#about to read 5, iclass 34, count 2 2006.257.14:42:52.10#ibcon#read 5, iclass 34, count 2 2006.257.14:42:52.10#ibcon#about to read 6, iclass 34, count 2 2006.257.14:42:52.10#ibcon#read 6, iclass 34, count 2 2006.257.14:42:52.10#ibcon#end of sib2, iclass 34, count 2 2006.257.14:42:52.10#ibcon#*after write, iclass 34, count 2 2006.257.14:42:52.10#ibcon#*before return 0, iclass 34, count 2 2006.257.14:42:52.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:52.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:52.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.14:42:52.10#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:52.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:52.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:52.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:52.22#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:42:52.22#ibcon#first serial, iclass 34, count 0 2006.257.14:42:52.22#ibcon#enter sib2, iclass 34, count 0 2006.257.14:42:52.22#ibcon#flushed, iclass 34, count 0 2006.257.14:42:52.22#ibcon#about to write, iclass 34, count 0 2006.257.14:42:52.22#ibcon#wrote, iclass 34, count 0 2006.257.14:42:52.22#ibcon#about to read 3, iclass 34, count 0 2006.257.14:42:52.24#ibcon#read 3, iclass 34, count 0 2006.257.14:42:52.24#ibcon#about to read 4, iclass 34, count 0 2006.257.14:42:52.24#ibcon#read 4, iclass 34, count 0 2006.257.14:42:52.24#ibcon#about to read 5, iclass 34, count 0 2006.257.14:42:52.24#ibcon#read 5, iclass 34, count 0 2006.257.14:42:52.24#ibcon#about to read 6, iclass 34, count 0 2006.257.14:42:52.24#ibcon#read 6, iclass 34, count 0 2006.257.14:42:52.24#ibcon#end of sib2, iclass 34, count 0 2006.257.14:42:52.24#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:42:52.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:42:52.24#ibcon#[25=USB\r\n] 2006.257.14:42:52.24#ibcon#*before write, iclass 34, count 0 2006.257.14:42:52.24#ibcon#enter sib2, iclass 34, count 0 2006.257.14:42:52.24#ibcon#flushed, iclass 34, count 0 2006.257.14:42:52.24#ibcon#about to write, iclass 34, count 0 2006.257.14:42:52.24#ibcon#wrote, iclass 34, count 0 2006.257.14:42:52.24#ibcon#about to read 3, iclass 34, count 0 2006.257.14:42:52.27#ibcon#read 3, iclass 34, count 0 2006.257.14:42:52.27#ibcon#about to read 4, iclass 34, count 0 2006.257.14:42:52.27#ibcon#read 4, iclass 34, count 0 2006.257.14:42:52.27#ibcon#about to read 5, iclass 34, count 0 2006.257.14:42:52.27#ibcon#read 5, iclass 34, count 0 2006.257.14:42:52.27#ibcon#about to read 6, iclass 34, count 0 2006.257.14:42:52.27#ibcon#read 6, iclass 34, count 0 2006.257.14:42:52.27#ibcon#end of sib2, iclass 34, count 0 2006.257.14:42:52.27#ibcon#*after write, iclass 34, count 0 2006.257.14:42:52.27#ibcon#*before return 0, iclass 34, count 0 2006.257.14:42:52.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:52.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:52.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:42:52.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:42:52.27$vck44/valo=7,864.99 2006.257.14:42:52.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.14:42:52.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.14:42:52.27#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:52.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:52.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:52.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:52.27#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:42:52.27#ibcon#first serial, iclass 36, count 0 2006.257.14:42:52.27#ibcon#enter sib2, iclass 36, count 0 2006.257.14:42:52.27#ibcon#flushed, iclass 36, count 0 2006.257.14:42:52.27#ibcon#about to write, iclass 36, count 0 2006.257.14:42:52.27#ibcon#wrote, iclass 36, count 0 2006.257.14:42:52.27#ibcon#about to read 3, iclass 36, count 0 2006.257.14:42:52.29#ibcon#read 3, iclass 36, count 0 2006.257.14:42:52.29#ibcon#about to read 4, iclass 36, count 0 2006.257.14:42:52.29#ibcon#read 4, iclass 36, count 0 2006.257.14:42:52.29#ibcon#about to read 5, iclass 36, count 0 2006.257.14:42:52.29#ibcon#read 5, iclass 36, count 0 2006.257.14:42:52.29#ibcon#about to read 6, iclass 36, count 0 2006.257.14:42:52.29#ibcon#read 6, iclass 36, count 0 2006.257.14:42:52.29#ibcon#end of sib2, iclass 36, count 0 2006.257.14:42:52.29#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:42:52.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:42:52.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:42:52.29#ibcon#*before write, iclass 36, count 0 2006.257.14:42:52.29#ibcon#enter sib2, iclass 36, count 0 2006.257.14:42:52.29#ibcon#flushed, iclass 36, count 0 2006.257.14:42:52.29#ibcon#about to write, iclass 36, count 0 2006.257.14:42:52.29#ibcon#wrote, iclass 36, count 0 2006.257.14:42:52.29#ibcon#about to read 3, iclass 36, count 0 2006.257.14:42:52.33#ibcon#read 3, iclass 36, count 0 2006.257.14:42:52.33#ibcon#about to read 4, iclass 36, count 0 2006.257.14:42:52.33#ibcon#read 4, iclass 36, count 0 2006.257.14:42:52.33#ibcon#about to read 5, iclass 36, count 0 2006.257.14:42:52.33#ibcon#read 5, iclass 36, count 0 2006.257.14:42:52.33#ibcon#about to read 6, iclass 36, count 0 2006.257.14:42:52.33#ibcon#read 6, iclass 36, count 0 2006.257.14:42:52.33#ibcon#end of sib2, iclass 36, count 0 2006.257.14:42:52.33#ibcon#*after write, iclass 36, count 0 2006.257.14:42:52.33#ibcon#*before return 0, iclass 36, count 0 2006.257.14:42:52.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:52.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:52.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:42:52.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:42:52.33$vck44/va=7,4 2006.257.14:42:52.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.14:42:52.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.14:42:52.33#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:52.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:52.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:52.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:52.39#ibcon#enter wrdev, iclass 38, count 2 2006.257.14:42:52.39#ibcon#first serial, iclass 38, count 2 2006.257.14:42:52.39#ibcon#enter sib2, iclass 38, count 2 2006.257.14:42:52.39#ibcon#flushed, iclass 38, count 2 2006.257.14:42:52.39#ibcon#about to write, iclass 38, count 2 2006.257.14:42:52.39#ibcon#wrote, iclass 38, count 2 2006.257.14:42:52.39#ibcon#about to read 3, iclass 38, count 2 2006.257.14:42:52.41#ibcon#read 3, iclass 38, count 2 2006.257.14:42:52.41#ibcon#about to read 4, iclass 38, count 2 2006.257.14:42:52.41#ibcon#read 4, iclass 38, count 2 2006.257.14:42:52.41#ibcon#about to read 5, iclass 38, count 2 2006.257.14:42:52.41#ibcon#read 5, iclass 38, count 2 2006.257.14:42:52.41#ibcon#about to read 6, iclass 38, count 2 2006.257.14:42:52.41#ibcon#read 6, iclass 38, count 2 2006.257.14:42:52.41#ibcon#end of sib2, iclass 38, count 2 2006.257.14:42:52.41#ibcon#*mode == 0, iclass 38, count 2 2006.257.14:42:52.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.14:42:52.41#ibcon#[25=AT07-04\r\n] 2006.257.14:42:52.41#ibcon#*before write, iclass 38, count 2 2006.257.14:42:52.41#ibcon#enter sib2, iclass 38, count 2 2006.257.14:42:52.41#ibcon#flushed, iclass 38, count 2 2006.257.14:42:52.41#ibcon#about to write, iclass 38, count 2 2006.257.14:42:52.41#ibcon#wrote, iclass 38, count 2 2006.257.14:42:52.41#ibcon#about to read 3, iclass 38, count 2 2006.257.14:42:52.44#ibcon#read 3, iclass 38, count 2 2006.257.14:42:52.45#ibcon#about to read 4, iclass 38, count 2 2006.257.14:42:52.45#ibcon#read 4, iclass 38, count 2 2006.257.14:42:52.45#ibcon#about to read 5, iclass 38, count 2 2006.257.14:42:52.45#ibcon#read 5, iclass 38, count 2 2006.257.14:42:52.45#ibcon#about to read 6, iclass 38, count 2 2006.257.14:42:52.45#ibcon#read 6, iclass 38, count 2 2006.257.14:42:52.45#ibcon#end of sib2, iclass 38, count 2 2006.257.14:42:52.45#ibcon#*after write, iclass 38, count 2 2006.257.14:42:52.45#ibcon#*before return 0, iclass 38, count 2 2006.257.14:42:52.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:52.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:52.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.14:42:52.45#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:52.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:52.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:52.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:52.57#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:42:52.57#ibcon#first serial, iclass 38, count 0 2006.257.14:42:52.57#ibcon#enter sib2, iclass 38, count 0 2006.257.14:42:52.57#ibcon#flushed, iclass 38, count 0 2006.257.14:42:52.57#ibcon#about to write, iclass 38, count 0 2006.257.14:42:52.57#ibcon#wrote, iclass 38, count 0 2006.257.14:42:52.57#ibcon#about to read 3, iclass 38, count 0 2006.257.14:42:52.59#ibcon#read 3, iclass 38, count 0 2006.257.14:42:52.59#ibcon#about to read 4, iclass 38, count 0 2006.257.14:42:52.59#ibcon#read 4, iclass 38, count 0 2006.257.14:42:52.59#ibcon#about to read 5, iclass 38, count 0 2006.257.14:42:52.59#ibcon#read 5, iclass 38, count 0 2006.257.14:42:52.59#ibcon#about to read 6, iclass 38, count 0 2006.257.14:42:52.59#ibcon#read 6, iclass 38, count 0 2006.257.14:42:52.59#ibcon#end of sib2, iclass 38, count 0 2006.257.14:42:52.59#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:42:52.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:42:52.59#ibcon#[25=USB\r\n] 2006.257.14:42:52.59#ibcon#*before write, iclass 38, count 0 2006.257.14:42:52.59#ibcon#enter sib2, iclass 38, count 0 2006.257.14:42:52.59#ibcon#flushed, iclass 38, count 0 2006.257.14:42:52.59#ibcon#about to write, iclass 38, count 0 2006.257.14:42:52.59#ibcon#wrote, iclass 38, count 0 2006.257.14:42:52.59#ibcon#about to read 3, iclass 38, count 0 2006.257.14:42:52.62#ibcon#read 3, iclass 38, count 0 2006.257.14:42:52.62#ibcon#about to read 4, iclass 38, count 0 2006.257.14:42:52.62#ibcon#read 4, iclass 38, count 0 2006.257.14:42:52.62#ibcon#about to read 5, iclass 38, count 0 2006.257.14:42:52.62#ibcon#read 5, iclass 38, count 0 2006.257.14:42:52.62#ibcon#about to read 6, iclass 38, count 0 2006.257.14:42:52.62#ibcon#read 6, iclass 38, count 0 2006.257.14:42:52.62#ibcon#end of sib2, iclass 38, count 0 2006.257.14:42:52.62#ibcon#*after write, iclass 38, count 0 2006.257.14:42:52.62#ibcon#*before return 0, iclass 38, count 0 2006.257.14:42:52.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:52.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:52.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:42:52.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:42:52.62$vck44/valo=8,884.99 2006.257.14:42:52.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.14:42:52.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.14:42:52.62#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:52.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:52.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:52.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:52.62#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:42:52.62#ibcon#first serial, iclass 40, count 0 2006.257.14:42:52.62#ibcon#enter sib2, iclass 40, count 0 2006.257.14:42:52.62#ibcon#flushed, iclass 40, count 0 2006.257.14:42:52.62#ibcon#about to write, iclass 40, count 0 2006.257.14:42:52.62#ibcon#wrote, iclass 40, count 0 2006.257.14:42:52.62#ibcon#about to read 3, iclass 40, count 0 2006.257.14:42:52.64#ibcon#read 3, iclass 40, count 0 2006.257.14:42:52.64#ibcon#about to read 4, iclass 40, count 0 2006.257.14:42:52.64#ibcon#read 4, iclass 40, count 0 2006.257.14:42:52.64#ibcon#about to read 5, iclass 40, count 0 2006.257.14:42:52.64#ibcon#read 5, iclass 40, count 0 2006.257.14:42:52.64#ibcon#about to read 6, iclass 40, count 0 2006.257.14:42:52.64#ibcon#read 6, iclass 40, count 0 2006.257.14:42:52.64#ibcon#end of sib2, iclass 40, count 0 2006.257.14:42:52.64#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:42:52.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:42:52.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:42:52.64#ibcon#*before write, iclass 40, count 0 2006.257.14:42:52.64#ibcon#enter sib2, iclass 40, count 0 2006.257.14:42:52.64#ibcon#flushed, iclass 40, count 0 2006.257.14:42:52.64#ibcon#about to write, iclass 40, count 0 2006.257.14:42:52.64#ibcon#wrote, iclass 40, count 0 2006.257.14:42:52.64#ibcon#about to read 3, iclass 40, count 0 2006.257.14:42:52.68#ibcon#read 3, iclass 40, count 0 2006.257.14:42:52.68#ibcon#about to read 4, iclass 40, count 0 2006.257.14:42:52.68#ibcon#read 4, iclass 40, count 0 2006.257.14:42:52.68#ibcon#about to read 5, iclass 40, count 0 2006.257.14:42:52.68#ibcon#read 5, iclass 40, count 0 2006.257.14:42:52.68#ibcon#about to read 6, iclass 40, count 0 2006.257.14:42:52.68#ibcon#read 6, iclass 40, count 0 2006.257.14:42:52.68#ibcon#end of sib2, iclass 40, count 0 2006.257.14:42:52.68#ibcon#*after write, iclass 40, count 0 2006.257.14:42:52.68#ibcon#*before return 0, iclass 40, count 0 2006.257.14:42:52.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:52.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:52.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:42:52.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:42:52.68$vck44/va=8,4 2006.257.14:42:52.68#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.14:42:52.68#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.14:42:52.68#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:52.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:52.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:52.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:52.74#ibcon#enter wrdev, iclass 4, count 2 2006.257.14:42:52.74#ibcon#first serial, iclass 4, count 2 2006.257.14:42:52.74#ibcon#enter sib2, iclass 4, count 2 2006.257.14:42:52.74#ibcon#flushed, iclass 4, count 2 2006.257.14:42:52.74#ibcon#about to write, iclass 4, count 2 2006.257.14:42:52.74#ibcon#wrote, iclass 4, count 2 2006.257.14:42:52.74#ibcon#about to read 3, iclass 4, count 2 2006.257.14:42:52.76#ibcon#read 3, iclass 4, count 2 2006.257.14:42:52.76#ibcon#about to read 4, iclass 4, count 2 2006.257.14:42:52.76#ibcon#read 4, iclass 4, count 2 2006.257.14:42:52.76#ibcon#about to read 5, iclass 4, count 2 2006.257.14:42:52.76#ibcon#read 5, iclass 4, count 2 2006.257.14:42:52.76#ibcon#about to read 6, iclass 4, count 2 2006.257.14:42:52.76#ibcon#read 6, iclass 4, count 2 2006.257.14:42:52.76#ibcon#end of sib2, iclass 4, count 2 2006.257.14:42:52.76#ibcon#*mode == 0, iclass 4, count 2 2006.257.14:42:52.76#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.14:42:52.76#ibcon#[25=AT08-04\r\n] 2006.257.14:42:52.76#ibcon#*before write, iclass 4, count 2 2006.257.14:42:52.76#ibcon#enter sib2, iclass 4, count 2 2006.257.14:42:52.76#ibcon#flushed, iclass 4, count 2 2006.257.14:42:52.76#ibcon#about to write, iclass 4, count 2 2006.257.14:42:52.76#ibcon#wrote, iclass 4, count 2 2006.257.14:42:52.76#ibcon#about to read 3, iclass 4, count 2 2006.257.14:42:52.79#ibcon#read 3, iclass 4, count 2 2006.257.14:42:52.79#ibcon#about to read 4, iclass 4, count 2 2006.257.14:42:52.79#ibcon#read 4, iclass 4, count 2 2006.257.14:42:52.79#ibcon#about to read 5, iclass 4, count 2 2006.257.14:42:52.79#ibcon#read 5, iclass 4, count 2 2006.257.14:42:52.79#ibcon#about to read 6, iclass 4, count 2 2006.257.14:42:52.79#ibcon#read 6, iclass 4, count 2 2006.257.14:42:52.79#ibcon#end of sib2, iclass 4, count 2 2006.257.14:42:52.79#ibcon#*after write, iclass 4, count 2 2006.257.14:42:52.79#ibcon#*before return 0, iclass 4, count 2 2006.257.14:42:52.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:52.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:52.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.14:42:52.79#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:52.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:52.91#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:52.91#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:52.91#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:42:52.91#ibcon#first serial, iclass 4, count 0 2006.257.14:42:52.91#ibcon#enter sib2, iclass 4, count 0 2006.257.14:42:52.91#ibcon#flushed, iclass 4, count 0 2006.257.14:42:52.91#ibcon#about to write, iclass 4, count 0 2006.257.14:42:52.91#ibcon#wrote, iclass 4, count 0 2006.257.14:42:52.91#ibcon#about to read 3, iclass 4, count 0 2006.257.14:42:52.93#ibcon#read 3, iclass 4, count 0 2006.257.14:42:52.93#ibcon#about to read 4, iclass 4, count 0 2006.257.14:42:52.93#ibcon#read 4, iclass 4, count 0 2006.257.14:42:52.93#ibcon#about to read 5, iclass 4, count 0 2006.257.14:42:52.93#ibcon#read 5, iclass 4, count 0 2006.257.14:42:52.93#ibcon#about to read 6, iclass 4, count 0 2006.257.14:42:52.93#ibcon#read 6, iclass 4, count 0 2006.257.14:42:52.93#ibcon#end of sib2, iclass 4, count 0 2006.257.14:42:52.93#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:42:52.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:42:52.93#ibcon#[25=USB\r\n] 2006.257.14:42:52.93#ibcon#*before write, iclass 4, count 0 2006.257.14:42:52.93#ibcon#enter sib2, iclass 4, count 0 2006.257.14:42:52.93#ibcon#flushed, iclass 4, count 0 2006.257.14:42:52.93#ibcon#about to write, iclass 4, count 0 2006.257.14:42:52.93#ibcon#wrote, iclass 4, count 0 2006.257.14:42:52.93#ibcon#about to read 3, iclass 4, count 0 2006.257.14:42:52.96#ibcon#read 3, iclass 4, count 0 2006.257.14:42:52.96#ibcon#about to read 4, iclass 4, count 0 2006.257.14:42:52.96#ibcon#read 4, iclass 4, count 0 2006.257.14:42:52.96#ibcon#about to read 5, iclass 4, count 0 2006.257.14:42:52.96#ibcon#read 5, iclass 4, count 0 2006.257.14:42:52.96#ibcon#about to read 6, iclass 4, count 0 2006.257.14:42:52.96#ibcon#read 6, iclass 4, count 0 2006.257.14:42:52.96#ibcon#end of sib2, iclass 4, count 0 2006.257.14:42:52.96#ibcon#*after write, iclass 4, count 0 2006.257.14:42:52.96#ibcon#*before return 0, iclass 4, count 0 2006.257.14:42:52.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:52.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:52.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:42:52.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:42:52.96$vck44/vblo=1,629.99 2006.257.14:42:52.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.14:42:52.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.14:42:52.96#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:52.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:52.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:52.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:52.96#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:42:52.96#ibcon#first serial, iclass 6, count 0 2006.257.14:42:52.96#ibcon#enter sib2, iclass 6, count 0 2006.257.14:42:52.96#ibcon#flushed, iclass 6, count 0 2006.257.14:42:52.96#ibcon#about to write, iclass 6, count 0 2006.257.14:42:52.96#ibcon#wrote, iclass 6, count 0 2006.257.14:42:52.96#ibcon#about to read 3, iclass 6, count 0 2006.257.14:42:52.98#ibcon#read 3, iclass 6, count 0 2006.257.14:42:52.98#ibcon#about to read 4, iclass 6, count 0 2006.257.14:42:52.98#ibcon#read 4, iclass 6, count 0 2006.257.14:42:52.98#ibcon#about to read 5, iclass 6, count 0 2006.257.14:42:52.98#ibcon#read 5, iclass 6, count 0 2006.257.14:42:52.98#ibcon#about to read 6, iclass 6, count 0 2006.257.14:42:52.98#ibcon#read 6, iclass 6, count 0 2006.257.14:42:52.98#ibcon#end of sib2, iclass 6, count 0 2006.257.14:42:52.98#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:42:52.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:42:52.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:42:52.98#ibcon#*before write, iclass 6, count 0 2006.257.14:42:52.98#ibcon#enter sib2, iclass 6, count 0 2006.257.14:42:52.98#ibcon#flushed, iclass 6, count 0 2006.257.14:42:52.98#ibcon#about to write, iclass 6, count 0 2006.257.14:42:52.98#ibcon#wrote, iclass 6, count 0 2006.257.14:42:52.98#ibcon#about to read 3, iclass 6, count 0 2006.257.14:42:53.02#ibcon#read 3, iclass 6, count 0 2006.257.14:42:53.02#ibcon#about to read 4, iclass 6, count 0 2006.257.14:42:53.02#ibcon#read 4, iclass 6, count 0 2006.257.14:42:53.02#ibcon#about to read 5, iclass 6, count 0 2006.257.14:42:53.02#ibcon#read 5, iclass 6, count 0 2006.257.14:42:53.02#ibcon#about to read 6, iclass 6, count 0 2006.257.14:42:53.02#ibcon#read 6, iclass 6, count 0 2006.257.14:42:53.02#ibcon#end of sib2, iclass 6, count 0 2006.257.14:42:53.02#ibcon#*after write, iclass 6, count 0 2006.257.14:42:53.02#ibcon#*before return 0, iclass 6, count 0 2006.257.14:42:53.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:53.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:53.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:42:53.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:42:53.02$vck44/vb=1,4 2006.257.14:42:53.02#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.14:42:53.02#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.14:42:53.02#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:53.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:42:53.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:42:53.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:42:53.02#ibcon#enter wrdev, iclass 10, count 2 2006.257.14:42:53.02#ibcon#first serial, iclass 10, count 2 2006.257.14:42:53.02#ibcon#enter sib2, iclass 10, count 2 2006.257.14:42:53.02#ibcon#flushed, iclass 10, count 2 2006.257.14:42:53.02#ibcon#about to write, iclass 10, count 2 2006.257.14:42:53.02#ibcon#wrote, iclass 10, count 2 2006.257.14:42:53.02#ibcon#about to read 3, iclass 10, count 2 2006.257.14:42:53.04#ibcon#read 3, iclass 10, count 2 2006.257.14:42:53.04#ibcon#about to read 4, iclass 10, count 2 2006.257.14:42:53.04#ibcon#read 4, iclass 10, count 2 2006.257.14:42:53.04#ibcon#about to read 5, iclass 10, count 2 2006.257.14:42:53.04#ibcon#read 5, iclass 10, count 2 2006.257.14:42:53.04#ibcon#about to read 6, iclass 10, count 2 2006.257.14:42:53.04#ibcon#read 6, iclass 10, count 2 2006.257.14:42:53.04#ibcon#end of sib2, iclass 10, count 2 2006.257.14:42:53.04#ibcon#*mode == 0, iclass 10, count 2 2006.257.14:42:53.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.14:42:53.04#ibcon#[27=AT01-04\r\n] 2006.257.14:42:53.04#ibcon#*before write, iclass 10, count 2 2006.257.14:42:53.04#ibcon#enter sib2, iclass 10, count 2 2006.257.14:42:53.04#ibcon#flushed, iclass 10, count 2 2006.257.14:42:53.04#ibcon#about to write, iclass 10, count 2 2006.257.14:42:53.04#ibcon#wrote, iclass 10, count 2 2006.257.14:42:53.04#ibcon#about to read 3, iclass 10, count 2 2006.257.14:42:53.07#ibcon#read 3, iclass 10, count 2 2006.257.14:42:53.07#ibcon#about to read 4, iclass 10, count 2 2006.257.14:42:53.07#ibcon#read 4, iclass 10, count 2 2006.257.14:42:53.07#ibcon#about to read 5, iclass 10, count 2 2006.257.14:42:53.07#ibcon#read 5, iclass 10, count 2 2006.257.14:42:53.07#ibcon#about to read 6, iclass 10, count 2 2006.257.14:42:53.07#ibcon#read 6, iclass 10, count 2 2006.257.14:42:53.07#ibcon#end of sib2, iclass 10, count 2 2006.257.14:42:53.07#ibcon#*after write, iclass 10, count 2 2006.257.14:42:53.07#ibcon#*before return 0, iclass 10, count 2 2006.257.14:42:53.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:42:53.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:42:53.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.14:42:53.07#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:53.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:42:53.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:42:53.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:42:53.19#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:42:53.19#ibcon#first serial, iclass 10, count 0 2006.257.14:42:53.19#ibcon#enter sib2, iclass 10, count 0 2006.257.14:42:53.19#ibcon#flushed, iclass 10, count 0 2006.257.14:42:53.19#ibcon#about to write, iclass 10, count 0 2006.257.14:42:53.19#ibcon#wrote, iclass 10, count 0 2006.257.14:42:53.19#ibcon#about to read 3, iclass 10, count 0 2006.257.14:42:53.21#ibcon#read 3, iclass 10, count 0 2006.257.14:42:53.21#ibcon#about to read 4, iclass 10, count 0 2006.257.14:42:53.21#ibcon#read 4, iclass 10, count 0 2006.257.14:42:53.21#ibcon#about to read 5, iclass 10, count 0 2006.257.14:42:53.21#ibcon#read 5, iclass 10, count 0 2006.257.14:42:53.21#ibcon#about to read 6, iclass 10, count 0 2006.257.14:42:53.21#ibcon#read 6, iclass 10, count 0 2006.257.14:42:53.21#ibcon#end of sib2, iclass 10, count 0 2006.257.14:42:53.21#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:42:53.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:42:53.21#ibcon#[27=USB\r\n] 2006.257.14:42:53.21#ibcon#*before write, iclass 10, count 0 2006.257.14:42:53.21#ibcon#enter sib2, iclass 10, count 0 2006.257.14:42:53.21#ibcon#flushed, iclass 10, count 0 2006.257.14:42:53.21#ibcon#about to write, iclass 10, count 0 2006.257.14:42:53.21#ibcon#wrote, iclass 10, count 0 2006.257.14:42:53.21#ibcon#about to read 3, iclass 10, count 0 2006.257.14:42:53.24#ibcon#read 3, iclass 10, count 0 2006.257.14:42:53.24#ibcon#about to read 4, iclass 10, count 0 2006.257.14:42:53.24#ibcon#read 4, iclass 10, count 0 2006.257.14:42:53.24#ibcon#about to read 5, iclass 10, count 0 2006.257.14:42:53.24#ibcon#read 5, iclass 10, count 0 2006.257.14:42:53.24#ibcon#about to read 6, iclass 10, count 0 2006.257.14:42:53.24#ibcon#read 6, iclass 10, count 0 2006.257.14:42:53.24#ibcon#end of sib2, iclass 10, count 0 2006.257.14:42:53.24#ibcon#*after write, iclass 10, count 0 2006.257.14:42:53.24#ibcon#*before return 0, iclass 10, count 0 2006.257.14:42:53.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:42:53.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:42:53.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:42:53.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:42:53.24$vck44/vblo=2,634.99 2006.257.14:42:53.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.14:42:53.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.14:42:53.24#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:53.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:53.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:53.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:53.24#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:42:53.24#ibcon#first serial, iclass 12, count 0 2006.257.14:42:53.24#ibcon#enter sib2, iclass 12, count 0 2006.257.14:42:53.24#ibcon#flushed, iclass 12, count 0 2006.257.14:42:53.24#ibcon#about to write, iclass 12, count 0 2006.257.14:42:53.24#ibcon#wrote, iclass 12, count 0 2006.257.14:42:53.24#ibcon#about to read 3, iclass 12, count 0 2006.257.14:42:53.26#ibcon#read 3, iclass 12, count 0 2006.257.14:42:53.26#ibcon#about to read 4, iclass 12, count 0 2006.257.14:42:53.26#ibcon#read 4, iclass 12, count 0 2006.257.14:42:53.26#ibcon#about to read 5, iclass 12, count 0 2006.257.14:42:53.26#ibcon#read 5, iclass 12, count 0 2006.257.14:42:53.26#ibcon#about to read 6, iclass 12, count 0 2006.257.14:42:53.26#ibcon#read 6, iclass 12, count 0 2006.257.14:42:53.26#ibcon#end of sib2, iclass 12, count 0 2006.257.14:42:53.26#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:42:53.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:42:53.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:42:53.26#ibcon#*before write, iclass 12, count 0 2006.257.14:42:53.26#ibcon#enter sib2, iclass 12, count 0 2006.257.14:42:53.26#ibcon#flushed, iclass 12, count 0 2006.257.14:42:53.26#ibcon#about to write, iclass 12, count 0 2006.257.14:42:53.26#ibcon#wrote, iclass 12, count 0 2006.257.14:42:53.26#ibcon#about to read 3, iclass 12, count 0 2006.257.14:42:53.30#ibcon#read 3, iclass 12, count 0 2006.257.14:42:53.30#ibcon#about to read 4, iclass 12, count 0 2006.257.14:42:53.30#ibcon#read 4, iclass 12, count 0 2006.257.14:42:53.30#ibcon#about to read 5, iclass 12, count 0 2006.257.14:42:53.30#ibcon#read 5, iclass 12, count 0 2006.257.14:42:53.30#ibcon#about to read 6, iclass 12, count 0 2006.257.14:42:53.30#ibcon#read 6, iclass 12, count 0 2006.257.14:42:53.30#ibcon#end of sib2, iclass 12, count 0 2006.257.14:42:53.30#ibcon#*after write, iclass 12, count 0 2006.257.14:42:53.30#ibcon#*before return 0, iclass 12, count 0 2006.257.14:42:53.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:53.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:42:53.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:42:53.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:42:53.30$vck44/vb=2,5 2006.257.14:42:53.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.14:42:53.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.14:42:53.30#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:53.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:53.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:53.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:53.36#ibcon#enter wrdev, iclass 14, count 2 2006.257.14:42:53.36#ibcon#first serial, iclass 14, count 2 2006.257.14:42:53.36#ibcon#enter sib2, iclass 14, count 2 2006.257.14:42:53.36#ibcon#flushed, iclass 14, count 2 2006.257.14:42:53.36#ibcon#about to write, iclass 14, count 2 2006.257.14:42:53.36#ibcon#wrote, iclass 14, count 2 2006.257.14:42:53.36#ibcon#about to read 3, iclass 14, count 2 2006.257.14:42:53.38#ibcon#read 3, iclass 14, count 2 2006.257.14:42:53.38#ibcon#about to read 4, iclass 14, count 2 2006.257.14:42:53.38#ibcon#read 4, iclass 14, count 2 2006.257.14:42:53.38#ibcon#about to read 5, iclass 14, count 2 2006.257.14:42:53.38#ibcon#read 5, iclass 14, count 2 2006.257.14:42:53.38#ibcon#about to read 6, iclass 14, count 2 2006.257.14:42:53.38#ibcon#read 6, iclass 14, count 2 2006.257.14:42:53.38#ibcon#end of sib2, iclass 14, count 2 2006.257.14:42:53.38#ibcon#*mode == 0, iclass 14, count 2 2006.257.14:42:53.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.14:42:53.38#ibcon#[27=AT02-05\r\n] 2006.257.14:42:53.38#ibcon#*before write, iclass 14, count 2 2006.257.14:42:53.38#ibcon#enter sib2, iclass 14, count 2 2006.257.14:42:53.38#ibcon#flushed, iclass 14, count 2 2006.257.14:42:53.38#ibcon#about to write, iclass 14, count 2 2006.257.14:42:53.38#ibcon#wrote, iclass 14, count 2 2006.257.14:42:53.38#ibcon#about to read 3, iclass 14, count 2 2006.257.14:42:53.41#ibcon#read 3, iclass 14, count 2 2006.257.14:42:53.41#ibcon#about to read 4, iclass 14, count 2 2006.257.14:42:53.41#ibcon#read 4, iclass 14, count 2 2006.257.14:42:53.41#ibcon#about to read 5, iclass 14, count 2 2006.257.14:42:53.41#ibcon#read 5, iclass 14, count 2 2006.257.14:42:53.41#ibcon#about to read 6, iclass 14, count 2 2006.257.14:42:53.41#ibcon#read 6, iclass 14, count 2 2006.257.14:42:53.41#ibcon#end of sib2, iclass 14, count 2 2006.257.14:42:53.41#ibcon#*after write, iclass 14, count 2 2006.257.14:42:53.41#ibcon#*before return 0, iclass 14, count 2 2006.257.14:42:53.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:53.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:42:53.49#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.14:42:53.49#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:53.49#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:53.61#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:53.61#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:53.61#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:42:53.61#ibcon#first serial, iclass 14, count 0 2006.257.14:42:53.61#ibcon#enter sib2, iclass 14, count 0 2006.257.14:42:53.61#ibcon#flushed, iclass 14, count 0 2006.257.14:42:53.61#ibcon#about to write, iclass 14, count 0 2006.257.14:42:53.61#ibcon#wrote, iclass 14, count 0 2006.257.14:42:53.61#ibcon#about to read 3, iclass 14, count 0 2006.257.14:42:53.63#ibcon#read 3, iclass 14, count 0 2006.257.14:42:53.63#ibcon#about to read 4, iclass 14, count 0 2006.257.14:42:53.63#ibcon#read 4, iclass 14, count 0 2006.257.14:42:53.63#ibcon#about to read 5, iclass 14, count 0 2006.257.14:42:53.63#ibcon#read 5, iclass 14, count 0 2006.257.14:42:53.63#ibcon#about to read 6, iclass 14, count 0 2006.257.14:42:53.63#ibcon#read 6, iclass 14, count 0 2006.257.14:42:53.63#ibcon#end of sib2, iclass 14, count 0 2006.257.14:42:53.63#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:42:53.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:42:53.63#ibcon#[27=USB\r\n] 2006.257.14:42:53.63#ibcon#*before write, iclass 14, count 0 2006.257.14:42:53.63#ibcon#enter sib2, iclass 14, count 0 2006.257.14:42:53.63#ibcon#flushed, iclass 14, count 0 2006.257.14:42:53.63#ibcon#about to write, iclass 14, count 0 2006.257.14:42:53.63#ibcon#wrote, iclass 14, count 0 2006.257.14:42:53.63#ibcon#about to read 3, iclass 14, count 0 2006.257.14:42:53.66#ibcon#read 3, iclass 14, count 0 2006.257.14:42:53.66#ibcon#about to read 4, iclass 14, count 0 2006.257.14:42:53.66#ibcon#read 4, iclass 14, count 0 2006.257.14:42:53.66#ibcon#about to read 5, iclass 14, count 0 2006.257.14:42:53.66#ibcon#read 5, iclass 14, count 0 2006.257.14:42:53.66#ibcon#about to read 6, iclass 14, count 0 2006.257.14:42:53.66#ibcon#read 6, iclass 14, count 0 2006.257.14:42:53.66#ibcon#end of sib2, iclass 14, count 0 2006.257.14:42:53.66#ibcon#*after write, iclass 14, count 0 2006.257.14:42:53.66#ibcon#*before return 0, iclass 14, count 0 2006.257.14:42:53.66#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:53.66#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:42:53.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:42:53.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:42:53.66$vck44/vblo=3,649.99 2006.257.14:42:53.66#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.14:42:53.66#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.14:42:53.66#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:53.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:53.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:53.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:53.66#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:42:53.66#ibcon#first serial, iclass 16, count 0 2006.257.14:42:53.66#ibcon#enter sib2, iclass 16, count 0 2006.257.14:42:53.66#ibcon#flushed, iclass 16, count 0 2006.257.14:42:53.66#ibcon#about to write, iclass 16, count 0 2006.257.14:42:53.66#ibcon#wrote, iclass 16, count 0 2006.257.14:42:53.66#ibcon#about to read 3, iclass 16, count 0 2006.257.14:42:53.68#ibcon#read 3, iclass 16, count 0 2006.257.14:42:53.68#ibcon#about to read 4, iclass 16, count 0 2006.257.14:42:53.68#ibcon#read 4, iclass 16, count 0 2006.257.14:42:53.68#ibcon#about to read 5, iclass 16, count 0 2006.257.14:42:53.68#ibcon#read 5, iclass 16, count 0 2006.257.14:42:53.68#ibcon#about to read 6, iclass 16, count 0 2006.257.14:42:53.68#ibcon#read 6, iclass 16, count 0 2006.257.14:42:53.68#ibcon#end of sib2, iclass 16, count 0 2006.257.14:42:53.68#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:42:53.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:42:53.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:42:53.68#ibcon#*before write, iclass 16, count 0 2006.257.14:42:53.68#ibcon#enter sib2, iclass 16, count 0 2006.257.14:42:53.68#ibcon#flushed, iclass 16, count 0 2006.257.14:42:53.68#ibcon#about to write, iclass 16, count 0 2006.257.14:42:53.68#ibcon#wrote, iclass 16, count 0 2006.257.14:42:53.68#ibcon#about to read 3, iclass 16, count 0 2006.257.14:42:53.72#ibcon#read 3, iclass 16, count 0 2006.257.14:42:53.72#ibcon#about to read 4, iclass 16, count 0 2006.257.14:42:53.72#ibcon#read 4, iclass 16, count 0 2006.257.14:42:53.72#ibcon#about to read 5, iclass 16, count 0 2006.257.14:42:53.72#ibcon#read 5, iclass 16, count 0 2006.257.14:42:53.72#ibcon#about to read 6, iclass 16, count 0 2006.257.14:42:53.72#ibcon#read 6, iclass 16, count 0 2006.257.14:42:53.72#ibcon#end of sib2, iclass 16, count 0 2006.257.14:42:53.72#ibcon#*after write, iclass 16, count 0 2006.257.14:42:53.72#ibcon#*before return 0, iclass 16, count 0 2006.257.14:42:53.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:53.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:42:53.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:42:53.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:42:53.72$vck44/vb=3,4 2006.257.14:42:53.72#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.14:42:53.72#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.14:42:53.72#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:53.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:53.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:53.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:53.78#ibcon#enter wrdev, iclass 18, count 2 2006.257.14:42:53.78#ibcon#first serial, iclass 18, count 2 2006.257.14:42:53.78#ibcon#enter sib2, iclass 18, count 2 2006.257.14:42:53.78#ibcon#flushed, iclass 18, count 2 2006.257.14:42:53.78#ibcon#about to write, iclass 18, count 2 2006.257.14:42:53.78#ibcon#wrote, iclass 18, count 2 2006.257.14:42:53.78#ibcon#about to read 3, iclass 18, count 2 2006.257.14:42:53.80#ibcon#read 3, iclass 18, count 2 2006.257.14:42:53.80#ibcon#about to read 4, iclass 18, count 2 2006.257.14:42:53.80#ibcon#read 4, iclass 18, count 2 2006.257.14:42:53.80#ibcon#about to read 5, iclass 18, count 2 2006.257.14:42:53.80#ibcon#read 5, iclass 18, count 2 2006.257.14:42:53.80#ibcon#about to read 6, iclass 18, count 2 2006.257.14:42:53.80#ibcon#read 6, iclass 18, count 2 2006.257.14:42:53.80#ibcon#end of sib2, iclass 18, count 2 2006.257.14:42:53.80#ibcon#*mode == 0, iclass 18, count 2 2006.257.14:42:53.80#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.14:42:53.80#ibcon#[27=AT03-04\r\n] 2006.257.14:42:53.80#ibcon#*before write, iclass 18, count 2 2006.257.14:42:53.80#ibcon#enter sib2, iclass 18, count 2 2006.257.14:42:53.80#ibcon#flushed, iclass 18, count 2 2006.257.14:42:53.80#ibcon#about to write, iclass 18, count 2 2006.257.14:42:53.80#ibcon#wrote, iclass 18, count 2 2006.257.14:42:53.80#ibcon#about to read 3, iclass 18, count 2 2006.257.14:42:53.83#ibcon#read 3, iclass 18, count 2 2006.257.14:42:53.83#ibcon#about to read 4, iclass 18, count 2 2006.257.14:42:53.83#ibcon#read 4, iclass 18, count 2 2006.257.14:42:53.83#ibcon#about to read 5, iclass 18, count 2 2006.257.14:42:53.83#ibcon#read 5, iclass 18, count 2 2006.257.14:42:53.83#ibcon#about to read 6, iclass 18, count 2 2006.257.14:42:53.83#ibcon#read 6, iclass 18, count 2 2006.257.14:42:53.83#ibcon#end of sib2, iclass 18, count 2 2006.257.14:42:53.83#ibcon#*after write, iclass 18, count 2 2006.257.14:42:53.83#ibcon#*before return 0, iclass 18, count 2 2006.257.14:42:53.83#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:53.83#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:42:53.83#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.14:42:53.83#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:53.83#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:53.95#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:53.95#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:53.95#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:42:53.95#ibcon#first serial, iclass 18, count 0 2006.257.14:42:53.95#ibcon#enter sib2, iclass 18, count 0 2006.257.14:42:53.95#ibcon#flushed, iclass 18, count 0 2006.257.14:42:53.95#ibcon#about to write, iclass 18, count 0 2006.257.14:42:53.95#ibcon#wrote, iclass 18, count 0 2006.257.14:42:53.95#ibcon#about to read 3, iclass 18, count 0 2006.257.14:42:53.97#ibcon#read 3, iclass 18, count 0 2006.257.14:42:53.97#ibcon#about to read 4, iclass 18, count 0 2006.257.14:42:53.97#ibcon#read 4, iclass 18, count 0 2006.257.14:42:53.97#ibcon#about to read 5, iclass 18, count 0 2006.257.14:42:53.97#ibcon#read 5, iclass 18, count 0 2006.257.14:42:53.97#ibcon#about to read 6, iclass 18, count 0 2006.257.14:42:53.97#ibcon#read 6, iclass 18, count 0 2006.257.14:42:53.97#ibcon#end of sib2, iclass 18, count 0 2006.257.14:42:53.97#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:42:53.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:42:53.97#ibcon#[27=USB\r\n] 2006.257.14:42:53.97#ibcon#*before write, iclass 18, count 0 2006.257.14:42:53.97#ibcon#enter sib2, iclass 18, count 0 2006.257.14:42:53.97#ibcon#flushed, iclass 18, count 0 2006.257.14:42:53.97#ibcon#about to write, iclass 18, count 0 2006.257.14:42:53.97#ibcon#wrote, iclass 18, count 0 2006.257.14:42:53.97#ibcon#about to read 3, iclass 18, count 0 2006.257.14:42:54.00#ibcon#read 3, iclass 18, count 0 2006.257.14:42:54.00#ibcon#about to read 4, iclass 18, count 0 2006.257.14:42:54.00#ibcon#read 4, iclass 18, count 0 2006.257.14:42:54.00#ibcon#about to read 5, iclass 18, count 0 2006.257.14:42:54.00#ibcon#read 5, iclass 18, count 0 2006.257.14:42:54.00#ibcon#about to read 6, iclass 18, count 0 2006.257.14:42:54.00#ibcon#read 6, iclass 18, count 0 2006.257.14:42:54.00#ibcon#end of sib2, iclass 18, count 0 2006.257.14:42:54.00#ibcon#*after write, iclass 18, count 0 2006.257.14:42:54.00#ibcon#*before return 0, iclass 18, count 0 2006.257.14:42:54.00#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:54.00#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:42:54.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:42:54.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:42:54.00$vck44/vblo=4,679.99 2006.257.14:42:54.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.14:42:54.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.14:42:54.00#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:54.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:54.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:54.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:54.00#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:42:54.00#ibcon#first serial, iclass 20, count 0 2006.257.14:42:54.00#ibcon#enter sib2, iclass 20, count 0 2006.257.14:42:54.00#ibcon#flushed, iclass 20, count 0 2006.257.14:42:54.00#ibcon#about to write, iclass 20, count 0 2006.257.14:42:54.00#ibcon#wrote, iclass 20, count 0 2006.257.14:42:54.00#ibcon#about to read 3, iclass 20, count 0 2006.257.14:42:54.02#ibcon#read 3, iclass 20, count 0 2006.257.14:42:54.02#ibcon#about to read 4, iclass 20, count 0 2006.257.14:42:54.02#ibcon#read 4, iclass 20, count 0 2006.257.14:42:54.02#ibcon#about to read 5, iclass 20, count 0 2006.257.14:42:54.02#ibcon#read 5, iclass 20, count 0 2006.257.14:42:54.02#ibcon#about to read 6, iclass 20, count 0 2006.257.14:42:54.02#ibcon#read 6, iclass 20, count 0 2006.257.14:42:54.02#ibcon#end of sib2, iclass 20, count 0 2006.257.14:42:54.02#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:42:54.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:42:54.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:42:54.02#ibcon#*before write, iclass 20, count 0 2006.257.14:42:54.02#ibcon#enter sib2, iclass 20, count 0 2006.257.14:42:54.02#ibcon#flushed, iclass 20, count 0 2006.257.14:42:54.02#ibcon#about to write, iclass 20, count 0 2006.257.14:42:54.02#ibcon#wrote, iclass 20, count 0 2006.257.14:42:54.02#ibcon#about to read 3, iclass 20, count 0 2006.257.14:42:54.06#ibcon#read 3, iclass 20, count 0 2006.257.14:42:54.06#ibcon#about to read 4, iclass 20, count 0 2006.257.14:42:54.06#ibcon#read 4, iclass 20, count 0 2006.257.14:42:54.06#ibcon#about to read 5, iclass 20, count 0 2006.257.14:42:54.06#ibcon#read 5, iclass 20, count 0 2006.257.14:42:54.06#ibcon#about to read 6, iclass 20, count 0 2006.257.14:42:54.06#ibcon#read 6, iclass 20, count 0 2006.257.14:42:54.06#ibcon#end of sib2, iclass 20, count 0 2006.257.14:42:54.06#ibcon#*after write, iclass 20, count 0 2006.257.14:42:54.06#ibcon#*before return 0, iclass 20, count 0 2006.257.14:42:54.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:54.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:42:54.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:42:54.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:42:54.06$vck44/vb=4,5 2006.257.14:42:54.06#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.14:42:54.06#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.14:42:54.06#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:54.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:42:54.10#abcon#<5=/14 1.3 3.3 17.48 971014.1\r\n> 2006.257.14:42:54.12#abcon#{5=INTERFACE CLEAR} 2006.257.14:42:54.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:42:54.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:42:54.12#ibcon#enter wrdev, iclass 23, count 2 2006.257.14:42:54.12#ibcon#first serial, iclass 23, count 2 2006.257.14:42:54.12#ibcon#enter sib2, iclass 23, count 2 2006.257.14:42:54.12#ibcon#flushed, iclass 23, count 2 2006.257.14:42:54.12#ibcon#about to write, iclass 23, count 2 2006.257.14:42:54.12#ibcon#wrote, iclass 23, count 2 2006.257.14:42:54.12#ibcon#about to read 3, iclass 23, count 2 2006.257.14:42:54.14#ibcon#read 3, iclass 23, count 2 2006.257.14:42:54.14#ibcon#about to read 4, iclass 23, count 2 2006.257.14:42:54.14#ibcon#read 4, iclass 23, count 2 2006.257.14:42:54.14#ibcon#about to read 5, iclass 23, count 2 2006.257.14:42:54.14#ibcon#read 5, iclass 23, count 2 2006.257.14:42:54.14#ibcon#about to read 6, iclass 23, count 2 2006.257.14:42:54.14#ibcon#read 6, iclass 23, count 2 2006.257.14:42:54.14#ibcon#end of sib2, iclass 23, count 2 2006.257.14:42:54.14#ibcon#*mode == 0, iclass 23, count 2 2006.257.14:42:54.14#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.14:42:54.14#ibcon#[27=AT04-05\r\n] 2006.257.14:42:54.14#ibcon#*before write, iclass 23, count 2 2006.257.14:42:54.14#ibcon#enter sib2, iclass 23, count 2 2006.257.14:42:54.14#ibcon#flushed, iclass 23, count 2 2006.257.14:42:54.14#ibcon#about to write, iclass 23, count 2 2006.257.14:42:54.14#ibcon#wrote, iclass 23, count 2 2006.257.14:42:54.14#ibcon#about to read 3, iclass 23, count 2 2006.257.14:42:54.17#ibcon#read 3, iclass 23, count 2 2006.257.14:42:54.17#ibcon#about to read 4, iclass 23, count 2 2006.257.14:42:54.17#ibcon#read 4, iclass 23, count 2 2006.257.14:42:54.17#ibcon#about to read 5, iclass 23, count 2 2006.257.14:42:54.17#ibcon#read 5, iclass 23, count 2 2006.257.14:42:54.17#ibcon#about to read 6, iclass 23, count 2 2006.257.14:42:54.17#ibcon#read 6, iclass 23, count 2 2006.257.14:42:54.17#ibcon#end of sib2, iclass 23, count 2 2006.257.14:42:54.17#ibcon#*after write, iclass 23, count 2 2006.257.14:42:54.17#ibcon#*before return 0, iclass 23, count 2 2006.257.14:42:54.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:42:54.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.14:42:54.17#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.14:42:54.17#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:54.17#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:42:54.18#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:42:54.29#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:42:54.29#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:42:54.29#ibcon#enter wrdev, iclass 23, count 0 2006.257.14:42:54.29#ibcon#first serial, iclass 23, count 0 2006.257.14:42:54.29#ibcon#enter sib2, iclass 23, count 0 2006.257.14:42:54.29#ibcon#flushed, iclass 23, count 0 2006.257.14:42:54.29#ibcon#about to write, iclass 23, count 0 2006.257.14:42:54.29#ibcon#wrote, iclass 23, count 0 2006.257.14:42:54.29#ibcon#about to read 3, iclass 23, count 0 2006.257.14:42:54.31#ibcon#read 3, iclass 23, count 0 2006.257.14:42:54.31#ibcon#about to read 4, iclass 23, count 0 2006.257.14:42:54.31#ibcon#read 4, iclass 23, count 0 2006.257.14:42:54.31#ibcon#about to read 5, iclass 23, count 0 2006.257.14:42:54.31#ibcon#read 5, iclass 23, count 0 2006.257.14:42:54.31#ibcon#about to read 6, iclass 23, count 0 2006.257.14:42:54.31#ibcon#read 6, iclass 23, count 0 2006.257.14:42:54.31#ibcon#end of sib2, iclass 23, count 0 2006.257.14:42:54.31#ibcon#*mode == 0, iclass 23, count 0 2006.257.14:42:54.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.14:42:54.31#ibcon#[27=USB\r\n] 2006.257.14:42:54.31#ibcon#*before write, iclass 23, count 0 2006.257.14:42:54.31#ibcon#enter sib2, iclass 23, count 0 2006.257.14:42:54.31#ibcon#flushed, iclass 23, count 0 2006.257.14:42:54.31#ibcon#about to write, iclass 23, count 0 2006.257.14:42:54.31#ibcon#wrote, iclass 23, count 0 2006.257.14:42:54.31#ibcon#about to read 3, iclass 23, count 0 2006.257.14:42:54.34#ibcon#read 3, iclass 23, count 0 2006.257.14:42:54.34#ibcon#about to read 4, iclass 23, count 0 2006.257.14:42:54.34#ibcon#read 4, iclass 23, count 0 2006.257.14:42:54.34#ibcon#about to read 5, iclass 23, count 0 2006.257.14:42:54.34#ibcon#read 5, iclass 23, count 0 2006.257.14:42:54.34#ibcon#about to read 6, iclass 23, count 0 2006.257.14:42:54.34#ibcon#read 6, iclass 23, count 0 2006.257.14:42:54.34#ibcon#end of sib2, iclass 23, count 0 2006.257.14:42:54.34#ibcon#*after write, iclass 23, count 0 2006.257.14:42:54.34#ibcon#*before return 0, iclass 23, count 0 2006.257.14:42:54.34#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:42:54.34#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.14:42:54.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.14:42:54.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.14:42:54.34$vck44/vblo=5,709.99 2006.257.14:42:54.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.14:42:54.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.14:42:54.34#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:54.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:54.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:54.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:54.34#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:42:54.34#ibcon#first serial, iclass 28, count 0 2006.257.14:42:54.34#ibcon#enter sib2, iclass 28, count 0 2006.257.14:42:54.34#ibcon#flushed, iclass 28, count 0 2006.257.14:42:54.34#ibcon#about to write, iclass 28, count 0 2006.257.14:42:54.34#ibcon#wrote, iclass 28, count 0 2006.257.14:42:54.34#ibcon#about to read 3, iclass 28, count 0 2006.257.14:42:54.36#ibcon#read 3, iclass 28, count 0 2006.257.14:42:54.36#ibcon#about to read 4, iclass 28, count 0 2006.257.14:42:54.36#ibcon#read 4, iclass 28, count 0 2006.257.14:42:54.36#ibcon#about to read 5, iclass 28, count 0 2006.257.14:42:54.36#ibcon#read 5, iclass 28, count 0 2006.257.14:42:54.36#ibcon#about to read 6, iclass 28, count 0 2006.257.14:42:54.36#ibcon#read 6, iclass 28, count 0 2006.257.14:42:54.36#ibcon#end of sib2, iclass 28, count 0 2006.257.14:42:54.36#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:42:54.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:42:54.36#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:42:54.36#ibcon#*before write, iclass 28, count 0 2006.257.14:42:54.36#ibcon#enter sib2, iclass 28, count 0 2006.257.14:42:54.36#ibcon#flushed, iclass 28, count 0 2006.257.14:42:54.36#ibcon#about to write, iclass 28, count 0 2006.257.14:42:54.36#ibcon#wrote, iclass 28, count 0 2006.257.14:42:54.36#ibcon#about to read 3, iclass 28, count 0 2006.257.14:42:54.40#ibcon#read 3, iclass 28, count 0 2006.257.14:42:54.40#ibcon#about to read 4, iclass 28, count 0 2006.257.14:42:54.40#ibcon#read 4, iclass 28, count 0 2006.257.14:42:54.40#ibcon#about to read 5, iclass 28, count 0 2006.257.14:42:54.40#ibcon#read 5, iclass 28, count 0 2006.257.14:42:54.40#ibcon#about to read 6, iclass 28, count 0 2006.257.14:42:54.40#ibcon#read 6, iclass 28, count 0 2006.257.14:42:54.40#ibcon#end of sib2, iclass 28, count 0 2006.257.14:42:54.40#ibcon#*after write, iclass 28, count 0 2006.257.14:42:54.40#ibcon#*before return 0, iclass 28, count 0 2006.257.14:42:54.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:54.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:42:54.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:42:54.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:42:54.40$vck44/vb=5,4 2006.257.14:42:54.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.14:42:54.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.14:42:54.40#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:54.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:54.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:54.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:54.46#ibcon#enter wrdev, iclass 30, count 2 2006.257.14:42:54.46#ibcon#first serial, iclass 30, count 2 2006.257.14:42:54.46#ibcon#enter sib2, iclass 30, count 2 2006.257.14:42:54.46#ibcon#flushed, iclass 30, count 2 2006.257.14:42:54.46#ibcon#about to write, iclass 30, count 2 2006.257.14:42:54.46#ibcon#wrote, iclass 30, count 2 2006.257.14:42:54.46#ibcon#about to read 3, iclass 30, count 2 2006.257.14:42:54.48#ibcon#read 3, iclass 30, count 2 2006.257.14:42:54.48#ibcon#about to read 4, iclass 30, count 2 2006.257.14:42:54.48#ibcon#read 4, iclass 30, count 2 2006.257.14:42:54.48#ibcon#about to read 5, iclass 30, count 2 2006.257.14:42:54.48#ibcon#read 5, iclass 30, count 2 2006.257.14:42:54.48#ibcon#about to read 6, iclass 30, count 2 2006.257.14:42:54.48#ibcon#read 6, iclass 30, count 2 2006.257.14:42:54.48#ibcon#end of sib2, iclass 30, count 2 2006.257.14:42:54.48#ibcon#*mode == 0, iclass 30, count 2 2006.257.14:42:54.48#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.14:42:54.48#ibcon#[27=AT05-04\r\n] 2006.257.14:42:54.48#ibcon#*before write, iclass 30, count 2 2006.257.14:42:54.48#ibcon#enter sib2, iclass 30, count 2 2006.257.14:42:54.48#ibcon#flushed, iclass 30, count 2 2006.257.14:42:54.48#ibcon#about to write, iclass 30, count 2 2006.257.14:42:54.48#ibcon#wrote, iclass 30, count 2 2006.257.14:42:54.48#ibcon#about to read 3, iclass 30, count 2 2006.257.14:42:54.51#ibcon#read 3, iclass 30, count 2 2006.257.14:42:54.51#ibcon#about to read 4, iclass 30, count 2 2006.257.14:42:54.51#ibcon#read 4, iclass 30, count 2 2006.257.14:42:54.51#ibcon#about to read 5, iclass 30, count 2 2006.257.14:42:54.51#ibcon#read 5, iclass 30, count 2 2006.257.14:42:54.51#ibcon#about to read 6, iclass 30, count 2 2006.257.14:42:54.51#ibcon#read 6, iclass 30, count 2 2006.257.14:42:54.51#ibcon#end of sib2, iclass 30, count 2 2006.257.14:42:54.51#ibcon#*after write, iclass 30, count 2 2006.257.14:42:54.51#ibcon#*before return 0, iclass 30, count 2 2006.257.14:42:54.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:54.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:42:54.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.14:42:54.51#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:54.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:54.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:54.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:54.63#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:42:54.63#ibcon#first serial, iclass 30, count 0 2006.257.14:42:54.63#ibcon#enter sib2, iclass 30, count 0 2006.257.14:42:54.63#ibcon#flushed, iclass 30, count 0 2006.257.14:42:54.63#ibcon#about to write, iclass 30, count 0 2006.257.14:42:54.63#ibcon#wrote, iclass 30, count 0 2006.257.14:42:54.63#ibcon#about to read 3, iclass 30, count 0 2006.257.14:42:54.65#ibcon#read 3, iclass 30, count 0 2006.257.14:42:54.65#ibcon#about to read 4, iclass 30, count 0 2006.257.14:42:54.65#ibcon#read 4, iclass 30, count 0 2006.257.14:42:54.65#ibcon#about to read 5, iclass 30, count 0 2006.257.14:42:54.65#ibcon#read 5, iclass 30, count 0 2006.257.14:42:54.65#ibcon#about to read 6, iclass 30, count 0 2006.257.14:42:54.65#ibcon#read 6, iclass 30, count 0 2006.257.14:42:54.65#ibcon#end of sib2, iclass 30, count 0 2006.257.14:42:54.65#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:42:54.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:42:54.65#ibcon#[27=USB\r\n] 2006.257.14:42:54.65#ibcon#*before write, iclass 30, count 0 2006.257.14:42:54.65#ibcon#enter sib2, iclass 30, count 0 2006.257.14:42:54.65#ibcon#flushed, iclass 30, count 0 2006.257.14:42:54.65#ibcon#about to write, iclass 30, count 0 2006.257.14:42:54.65#ibcon#wrote, iclass 30, count 0 2006.257.14:42:54.65#ibcon#about to read 3, iclass 30, count 0 2006.257.14:42:54.68#ibcon#read 3, iclass 30, count 0 2006.257.14:42:54.68#ibcon#about to read 4, iclass 30, count 0 2006.257.14:42:54.68#ibcon#read 4, iclass 30, count 0 2006.257.14:42:54.68#ibcon#about to read 5, iclass 30, count 0 2006.257.14:42:54.68#ibcon#read 5, iclass 30, count 0 2006.257.14:42:54.68#ibcon#about to read 6, iclass 30, count 0 2006.257.14:42:54.68#ibcon#read 6, iclass 30, count 0 2006.257.14:42:54.68#ibcon#end of sib2, iclass 30, count 0 2006.257.14:42:54.68#ibcon#*after write, iclass 30, count 0 2006.257.14:42:54.68#ibcon#*before return 0, iclass 30, count 0 2006.257.14:42:54.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:54.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:42:54.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:42:54.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:42:54.68$vck44/vblo=6,719.99 2006.257.14:42:54.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.14:42:54.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.14:42:54.68#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:54.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:54.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:54.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:54.68#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:42:54.68#ibcon#first serial, iclass 32, count 0 2006.257.14:42:54.68#ibcon#enter sib2, iclass 32, count 0 2006.257.14:42:54.68#ibcon#flushed, iclass 32, count 0 2006.257.14:42:54.68#ibcon#about to write, iclass 32, count 0 2006.257.14:42:54.68#ibcon#wrote, iclass 32, count 0 2006.257.14:42:54.68#ibcon#about to read 3, iclass 32, count 0 2006.257.14:42:54.70#ibcon#read 3, iclass 32, count 0 2006.257.14:42:54.70#ibcon#about to read 4, iclass 32, count 0 2006.257.14:42:54.70#ibcon#read 4, iclass 32, count 0 2006.257.14:42:54.70#ibcon#about to read 5, iclass 32, count 0 2006.257.14:42:54.70#ibcon#read 5, iclass 32, count 0 2006.257.14:42:54.70#ibcon#about to read 6, iclass 32, count 0 2006.257.14:42:54.70#ibcon#read 6, iclass 32, count 0 2006.257.14:42:54.70#ibcon#end of sib2, iclass 32, count 0 2006.257.14:42:54.70#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:42:54.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:42:54.70#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:42:54.70#ibcon#*before write, iclass 32, count 0 2006.257.14:42:54.70#ibcon#enter sib2, iclass 32, count 0 2006.257.14:42:54.70#ibcon#flushed, iclass 32, count 0 2006.257.14:42:54.70#ibcon#about to write, iclass 32, count 0 2006.257.14:42:54.70#ibcon#wrote, iclass 32, count 0 2006.257.14:42:54.70#ibcon#about to read 3, iclass 32, count 0 2006.257.14:42:54.74#ibcon#read 3, iclass 32, count 0 2006.257.14:42:54.74#ibcon#about to read 4, iclass 32, count 0 2006.257.14:42:54.74#ibcon#read 4, iclass 32, count 0 2006.257.14:42:54.74#ibcon#about to read 5, iclass 32, count 0 2006.257.14:42:54.74#ibcon#read 5, iclass 32, count 0 2006.257.14:42:54.74#ibcon#about to read 6, iclass 32, count 0 2006.257.14:42:54.74#ibcon#read 6, iclass 32, count 0 2006.257.14:42:54.74#ibcon#end of sib2, iclass 32, count 0 2006.257.14:42:54.74#ibcon#*after write, iclass 32, count 0 2006.257.14:42:54.74#ibcon#*before return 0, iclass 32, count 0 2006.257.14:42:54.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:54.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:42:54.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:42:54.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:42:54.74$vck44/vb=6,4 2006.257.14:42:54.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.14:42:54.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.14:42:54.74#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:54.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:54.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:54.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:54.80#ibcon#enter wrdev, iclass 34, count 2 2006.257.14:42:54.80#ibcon#first serial, iclass 34, count 2 2006.257.14:42:54.80#ibcon#enter sib2, iclass 34, count 2 2006.257.14:42:54.80#ibcon#flushed, iclass 34, count 2 2006.257.14:42:54.80#ibcon#about to write, iclass 34, count 2 2006.257.14:42:54.80#ibcon#wrote, iclass 34, count 2 2006.257.14:42:54.80#ibcon#about to read 3, iclass 34, count 2 2006.257.14:42:54.82#ibcon#read 3, iclass 34, count 2 2006.257.14:42:54.82#ibcon#about to read 4, iclass 34, count 2 2006.257.14:42:54.82#ibcon#read 4, iclass 34, count 2 2006.257.14:42:54.82#ibcon#about to read 5, iclass 34, count 2 2006.257.14:42:54.82#ibcon#read 5, iclass 34, count 2 2006.257.14:42:54.82#ibcon#about to read 6, iclass 34, count 2 2006.257.14:42:54.82#ibcon#read 6, iclass 34, count 2 2006.257.14:42:54.82#ibcon#end of sib2, iclass 34, count 2 2006.257.14:42:54.82#ibcon#*mode == 0, iclass 34, count 2 2006.257.14:42:54.82#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.14:42:54.82#ibcon#[27=AT06-04\r\n] 2006.257.14:42:54.82#ibcon#*before write, iclass 34, count 2 2006.257.14:42:54.82#ibcon#enter sib2, iclass 34, count 2 2006.257.14:42:54.82#ibcon#flushed, iclass 34, count 2 2006.257.14:42:54.82#ibcon#about to write, iclass 34, count 2 2006.257.14:42:54.82#ibcon#wrote, iclass 34, count 2 2006.257.14:42:54.82#ibcon#about to read 3, iclass 34, count 2 2006.257.14:42:54.85#ibcon#read 3, iclass 34, count 2 2006.257.14:42:54.85#ibcon#about to read 4, iclass 34, count 2 2006.257.14:42:54.85#ibcon#read 4, iclass 34, count 2 2006.257.14:42:54.85#ibcon#about to read 5, iclass 34, count 2 2006.257.14:42:54.85#ibcon#read 5, iclass 34, count 2 2006.257.14:42:54.85#ibcon#about to read 6, iclass 34, count 2 2006.257.14:42:54.85#ibcon#read 6, iclass 34, count 2 2006.257.14:42:54.85#ibcon#end of sib2, iclass 34, count 2 2006.257.14:42:54.85#ibcon#*after write, iclass 34, count 2 2006.257.14:42:54.85#ibcon#*before return 0, iclass 34, count 2 2006.257.14:42:54.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:54.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:42:54.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.14:42:54.85#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:54.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:54.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:54.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:54.97#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:42:54.97#ibcon#first serial, iclass 34, count 0 2006.257.14:42:54.97#ibcon#enter sib2, iclass 34, count 0 2006.257.14:42:54.97#ibcon#flushed, iclass 34, count 0 2006.257.14:42:54.97#ibcon#about to write, iclass 34, count 0 2006.257.14:42:54.97#ibcon#wrote, iclass 34, count 0 2006.257.14:42:54.97#ibcon#about to read 3, iclass 34, count 0 2006.257.14:42:54.99#ibcon#read 3, iclass 34, count 0 2006.257.14:42:54.99#ibcon#about to read 4, iclass 34, count 0 2006.257.14:42:54.99#ibcon#read 4, iclass 34, count 0 2006.257.14:42:54.99#ibcon#about to read 5, iclass 34, count 0 2006.257.14:42:54.99#ibcon#read 5, iclass 34, count 0 2006.257.14:42:54.99#ibcon#about to read 6, iclass 34, count 0 2006.257.14:42:54.99#ibcon#read 6, iclass 34, count 0 2006.257.14:42:54.99#ibcon#end of sib2, iclass 34, count 0 2006.257.14:42:54.99#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:42:54.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:42:54.99#ibcon#[27=USB\r\n] 2006.257.14:42:54.99#ibcon#*before write, iclass 34, count 0 2006.257.14:42:54.99#ibcon#enter sib2, iclass 34, count 0 2006.257.14:42:54.99#ibcon#flushed, iclass 34, count 0 2006.257.14:42:54.99#ibcon#about to write, iclass 34, count 0 2006.257.14:42:54.99#ibcon#wrote, iclass 34, count 0 2006.257.14:42:54.99#ibcon#about to read 3, iclass 34, count 0 2006.257.14:42:55.02#ibcon#read 3, iclass 34, count 0 2006.257.14:42:55.02#ibcon#about to read 4, iclass 34, count 0 2006.257.14:42:55.02#ibcon#read 4, iclass 34, count 0 2006.257.14:42:55.02#ibcon#about to read 5, iclass 34, count 0 2006.257.14:42:55.02#ibcon#read 5, iclass 34, count 0 2006.257.14:42:55.02#ibcon#about to read 6, iclass 34, count 0 2006.257.14:42:55.02#ibcon#read 6, iclass 34, count 0 2006.257.14:42:55.02#ibcon#end of sib2, iclass 34, count 0 2006.257.14:42:55.02#ibcon#*after write, iclass 34, count 0 2006.257.14:42:55.02#ibcon#*before return 0, iclass 34, count 0 2006.257.14:42:55.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:55.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:42:55.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:42:55.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:42:55.02$vck44/vblo=7,734.99 2006.257.14:42:55.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.14:42:55.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.14:42:55.02#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:55.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:55.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:55.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:55.02#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:42:55.02#ibcon#first serial, iclass 36, count 0 2006.257.14:42:55.02#ibcon#enter sib2, iclass 36, count 0 2006.257.14:42:55.02#ibcon#flushed, iclass 36, count 0 2006.257.14:42:55.02#ibcon#about to write, iclass 36, count 0 2006.257.14:42:55.02#ibcon#wrote, iclass 36, count 0 2006.257.14:42:55.02#ibcon#about to read 3, iclass 36, count 0 2006.257.14:42:55.04#ibcon#read 3, iclass 36, count 0 2006.257.14:42:55.04#ibcon#about to read 4, iclass 36, count 0 2006.257.14:42:55.04#ibcon#read 4, iclass 36, count 0 2006.257.14:42:55.04#ibcon#about to read 5, iclass 36, count 0 2006.257.14:42:55.04#ibcon#read 5, iclass 36, count 0 2006.257.14:42:55.04#ibcon#about to read 6, iclass 36, count 0 2006.257.14:42:55.04#ibcon#read 6, iclass 36, count 0 2006.257.14:42:55.04#ibcon#end of sib2, iclass 36, count 0 2006.257.14:42:55.04#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:42:55.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:42:55.04#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:42:55.04#ibcon#*before write, iclass 36, count 0 2006.257.14:42:55.04#ibcon#enter sib2, iclass 36, count 0 2006.257.14:42:55.04#ibcon#flushed, iclass 36, count 0 2006.257.14:42:55.04#ibcon#about to write, iclass 36, count 0 2006.257.14:42:55.04#ibcon#wrote, iclass 36, count 0 2006.257.14:42:55.04#ibcon#about to read 3, iclass 36, count 0 2006.257.14:42:55.08#ibcon#read 3, iclass 36, count 0 2006.257.14:42:55.08#ibcon#about to read 4, iclass 36, count 0 2006.257.14:42:55.08#ibcon#read 4, iclass 36, count 0 2006.257.14:42:55.08#ibcon#about to read 5, iclass 36, count 0 2006.257.14:42:55.08#ibcon#read 5, iclass 36, count 0 2006.257.14:42:55.08#ibcon#about to read 6, iclass 36, count 0 2006.257.14:42:55.08#ibcon#read 6, iclass 36, count 0 2006.257.14:42:55.08#ibcon#end of sib2, iclass 36, count 0 2006.257.14:42:55.08#ibcon#*after write, iclass 36, count 0 2006.257.14:42:55.08#ibcon#*before return 0, iclass 36, count 0 2006.257.14:42:55.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:55.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:42:55.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:42:55.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:42:55.08$vck44/vb=7,4 2006.257.14:42:55.08#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.14:42:55.08#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.14:42:55.08#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:55.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:55.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:55.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:55.14#ibcon#enter wrdev, iclass 38, count 2 2006.257.14:42:55.14#ibcon#first serial, iclass 38, count 2 2006.257.14:42:55.14#ibcon#enter sib2, iclass 38, count 2 2006.257.14:42:55.14#ibcon#flushed, iclass 38, count 2 2006.257.14:42:55.14#ibcon#about to write, iclass 38, count 2 2006.257.14:42:55.14#ibcon#wrote, iclass 38, count 2 2006.257.14:42:55.14#ibcon#about to read 3, iclass 38, count 2 2006.257.14:42:55.16#ibcon#read 3, iclass 38, count 2 2006.257.14:42:55.16#ibcon#about to read 4, iclass 38, count 2 2006.257.14:42:55.16#ibcon#read 4, iclass 38, count 2 2006.257.14:42:55.16#ibcon#about to read 5, iclass 38, count 2 2006.257.14:42:55.16#ibcon#read 5, iclass 38, count 2 2006.257.14:42:55.16#ibcon#about to read 6, iclass 38, count 2 2006.257.14:42:55.16#ibcon#read 6, iclass 38, count 2 2006.257.14:42:55.16#ibcon#end of sib2, iclass 38, count 2 2006.257.14:42:55.16#ibcon#*mode == 0, iclass 38, count 2 2006.257.14:42:55.16#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.14:42:55.16#ibcon#[27=AT07-04\r\n] 2006.257.14:42:55.16#ibcon#*before write, iclass 38, count 2 2006.257.14:42:55.16#ibcon#enter sib2, iclass 38, count 2 2006.257.14:42:55.16#ibcon#flushed, iclass 38, count 2 2006.257.14:42:55.16#ibcon#about to write, iclass 38, count 2 2006.257.14:42:55.16#ibcon#wrote, iclass 38, count 2 2006.257.14:42:55.16#ibcon#about to read 3, iclass 38, count 2 2006.257.14:42:55.19#ibcon#read 3, iclass 38, count 2 2006.257.14:42:55.19#ibcon#about to read 4, iclass 38, count 2 2006.257.14:42:55.19#ibcon#read 4, iclass 38, count 2 2006.257.14:42:55.19#ibcon#about to read 5, iclass 38, count 2 2006.257.14:42:55.19#ibcon#read 5, iclass 38, count 2 2006.257.14:42:55.19#ibcon#about to read 6, iclass 38, count 2 2006.257.14:42:55.19#ibcon#read 6, iclass 38, count 2 2006.257.14:42:55.19#ibcon#end of sib2, iclass 38, count 2 2006.257.14:42:55.19#ibcon#*after write, iclass 38, count 2 2006.257.14:42:55.19#ibcon#*before return 0, iclass 38, count 2 2006.257.14:42:55.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:55.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:42:55.19#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.14:42:55.19#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:55.19#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:55.31#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:55.31#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:55.31#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:42:55.31#ibcon#first serial, iclass 38, count 0 2006.257.14:42:55.31#ibcon#enter sib2, iclass 38, count 0 2006.257.14:42:55.31#ibcon#flushed, iclass 38, count 0 2006.257.14:42:55.31#ibcon#about to write, iclass 38, count 0 2006.257.14:42:55.31#ibcon#wrote, iclass 38, count 0 2006.257.14:42:55.31#ibcon#about to read 3, iclass 38, count 0 2006.257.14:42:55.33#ibcon#read 3, iclass 38, count 0 2006.257.14:42:55.33#ibcon#about to read 4, iclass 38, count 0 2006.257.14:42:55.33#ibcon#read 4, iclass 38, count 0 2006.257.14:42:55.33#ibcon#about to read 5, iclass 38, count 0 2006.257.14:42:55.33#ibcon#read 5, iclass 38, count 0 2006.257.14:42:55.33#ibcon#about to read 6, iclass 38, count 0 2006.257.14:42:55.33#ibcon#read 6, iclass 38, count 0 2006.257.14:42:55.33#ibcon#end of sib2, iclass 38, count 0 2006.257.14:42:55.33#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:42:55.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:42:55.33#ibcon#[27=USB\r\n] 2006.257.14:42:55.33#ibcon#*before write, iclass 38, count 0 2006.257.14:42:55.33#ibcon#enter sib2, iclass 38, count 0 2006.257.14:42:55.33#ibcon#flushed, iclass 38, count 0 2006.257.14:42:55.33#ibcon#about to write, iclass 38, count 0 2006.257.14:42:55.33#ibcon#wrote, iclass 38, count 0 2006.257.14:42:55.33#ibcon#about to read 3, iclass 38, count 0 2006.257.14:42:55.36#ibcon#read 3, iclass 38, count 0 2006.257.14:42:55.36#ibcon#about to read 4, iclass 38, count 0 2006.257.14:42:55.36#ibcon#read 4, iclass 38, count 0 2006.257.14:42:55.36#ibcon#about to read 5, iclass 38, count 0 2006.257.14:42:55.36#ibcon#read 5, iclass 38, count 0 2006.257.14:42:55.36#ibcon#about to read 6, iclass 38, count 0 2006.257.14:42:55.36#ibcon#read 6, iclass 38, count 0 2006.257.14:42:55.36#ibcon#end of sib2, iclass 38, count 0 2006.257.14:42:55.36#ibcon#*after write, iclass 38, count 0 2006.257.14:42:55.36#ibcon#*before return 0, iclass 38, count 0 2006.257.14:42:55.36#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:55.36#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:42:55.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:42:55.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:42:55.36$vck44/vblo=8,744.99 2006.257.14:42:55.36#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.14:42:55.36#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.14:42:55.36#ibcon#ireg 17 cls_cnt 0 2006.257.14:42:55.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:55.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:55.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:55.36#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:42:55.36#ibcon#first serial, iclass 40, count 0 2006.257.14:42:55.36#ibcon#enter sib2, iclass 40, count 0 2006.257.14:42:55.36#ibcon#flushed, iclass 40, count 0 2006.257.14:42:55.36#ibcon#about to write, iclass 40, count 0 2006.257.14:42:55.36#ibcon#wrote, iclass 40, count 0 2006.257.14:42:55.36#ibcon#about to read 3, iclass 40, count 0 2006.257.14:42:55.38#ibcon#read 3, iclass 40, count 0 2006.257.14:42:55.38#ibcon#about to read 4, iclass 40, count 0 2006.257.14:42:55.38#ibcon#read 4, iclass 40, count 0 2006.257.14:42:55.38#ibcon#about to read 5, iclass 40, count 0 2006.257.14:42:55.38#ibcon#read 5, iclass 40, count 0 2006.257.14:42:55.38#ibcon#about to read 6, iclass 40, count 0 2006.257.14:42:55.38#ibcon#read 6, iclass 40, count 0 2006.257.14:42:55.38#ibcon#end of sib2, iclass 40, count 0 2006.257.14:42:55.38#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:42:55.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:42:55.38#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:42:55.38#ibcon#*before write, iclass 40, count 0 2006.257.14:42:55.38#ibcon#enter sib2, iclass 40, count 0 2006.257.14:42:55.38#ibcon#flushed, iclass 40, count 0 2006.257.14:42:55.38#ibcon#about to write, iclass 40, count 0 2006.257.14:42:55.38#ibcon#wrote, iclass 40, count 0 2006.257.14:42:55.38#ibcon#about to read 3, iclass 40, count 0 2006.257.14:42:55.42#ibcon#read 3, iclass 40, count 0 2006.257.14:42:55.42#ibcon#about to read 4, iclass 40, count 0 2006.257.14:42:55.42#ibcon#read 4, iclass 40, count 0 2006.257.14:42:55.42#ibcon#about to read 5, iclass 40, count 0 2006.257.14:42:55.42#ibcon#read 5, iclass 40, count 0 2006.257.14:42:55.42#ibcon#about to read 6, iclass 40, count 0 2006.257.14:42:55.42#ibcon#read 6, iclass 40, count 0 2006.257.14:42:55.42#ibcon#end of sib2, iclass 40, count 0 2006.257.14:42:55.42#ibcon#*after write, iclass 40, count 0 2006.257.14:42:55.42#ibcon#*before return 0, iclass 40, count 0 2006.257.14:42:55.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:55.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:42:55.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:42:55.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:42:55.42$vck44/vb=8,4 2006.257.14:42:55.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.14:42:55.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.14:42:55.42#ibcon#ireg 11 cls_cnt 2 2006.257.14:42:55.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:55.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:55.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:55.48#ibcon#enter wrdev, iclass 4, count 2 2006.257.14:42:55.48#ibcon#first serial, iclass 4, count 2 2006.257.14:42:55.48#ibcon#enter sib2, iclass 4, count 2 2006.257.14:42:55.48#ibcon#flushed, iclass 4, count 2 2006.257.14:42:55.48#ibcon#about to write, iclass 4, count 2 2006.257.14:42:55.48#ibcon#wrote, iclass 4, count 2 2006.257.14:42:55.48#ibcon#about to read 3, iclass 4, count 2 2006.257.14:42:55.50#ibcon#read 3, iclass 4, count 2 2006.257.14:42:55.50#ibcon#about to read 4, iclass 4, count 2 2006.257.14:42:55.50#ibcon#read 4, iclass 4, count 2 2006.257.14:42:55.50#ibcon#about to read 5, iclass 4, count 2 2006.257.14:42:55.50#ibcon#read 5, iclass 4, count 2 2006.257.14:42:55.50#ibcon#about to read 6, iclass 4, count 2 2006.257.14:42:55.50#ibcon#read 6, iclass 4, count 2 2006.257.14:42:55.50#ibcon#end of sib2, iclass 4, count 2 2006.257.14:42:55.50#ibcon#*mode == 0, iclass 4, count 2 2006.257.14:42:55.50#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.14:42:55.50#ibcon#[27=AT08-04\r\n] 2006.257.14:42:55.50#ibcon#*before write, iclass 4, count 2 2006.257.14:42:55.50#ibcon#enter sib2, iclass 4, count 2 2006.257.14:42:55.50#ibcon#flushed, iclass 4, count 2 2006.257.14:42:55.50#ibcon#about to write, iclass 4, count 2 2006.257.14:42:55.50#ibcon#wrote, iclass 4, count 2 2006.257.14:42:55.50#ibcon#about to read 3, iclass 4, count 2 2006.257.14:42:55.53#ibcon#read 3, iclass 4, count 2 2006.257.14:42:55.54#ibcon#about to read 4, iclass 4, count 2 2006.257.14:42:55.54#ibcon#read 4, iclass 4, count 2 2006.257.14:42:55.54#ibcon#about to read 5, iclass 4, count 2 2006.257.14:42:55.54#ibcon#read 5, iclass 4, count 2 2006.257.14:42:55.54#ibcon#about to read 6, iclass 4, count 2 2006.257.14:42:55.54#ibcon#read 6, iclass 4, count 2 2006.257.14:42:55.54#ibcon#end of sib2, iclass 4, count 2 2006.257.14:42:55.54#ibcon#*after write, iclass 4, count 2 2006.257.14:42:55.54#ibcon#*before return 0, iclass 4, count 2 2006.257.14:42:55.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:55.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:42:55.54#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.14:42:55.54#ibcon#ireg 7 cls_cnt 0 2006.257.14:42:55.54#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:55.66#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:55.66#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:55.66#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:42:55.66#ibcon#first serial, iclass 4, count 0 2006.257.14:42:55.66#ibcon#enter sib2, iclass 4, count 0 2006.257.14:42:55.66#ibcon#flushed, iclass 4, count 0 2006.257.14:42:55.66#ibcon#about to write, iclass 4, count 0 2006.257.14:42:55.66#ibcon#wrote, iclass 4, count 0 2006.257.14:42:55.66#ibcon#about to read 3, iclass 4, count 0 2006.257.14:42:55.68#ibcon#read 3, iclass 4, count 0 2006.257.14:42:55.68#ibcon#about to read 4, iclass 4, count 0 2006.257.14:42:55.68#ibcon#read 4, iclass 4, count 0 2006.257.14:42:55.68#ibcon#about to read 5, iclass 4, count 0 2006.257.14:42:55.68#ibcon#read 5, iclass 4, count 0 2006.257.14:42:55.68#ibcon#about to read 6, iclass 4, count 0 2006.257.14:42:55.68#ibcon#read 6, iclass 4, count 0 2006.257.14:42:55.68#ibcon#end of sib2, iclass 4, count 0 2006.257.14:42:55.68#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:42:55.68#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:42:55.68#ibcon#[27=USB\r\n] 2006.257.14:42:55.68#ibcon#*before write, iclass 4, count 0 2006.257.14:42:55.68#ibcon#enter sib2, iclass 4, count 0 2006.257.14:42:55.68#ibcon#flushed, iclass 4, count 0 2006.257.14:42:55.68#ibcon#about to write, iclass 4, count 0 2006.257.14:42:55.68#ibcon#wrote, iclass 4, count 0 2006.257.14:42:55.68#ibcon#about to read 3, iclass 4, count 0 2006.257.14:42:55.71#ibcon#read 3, iclass 4, count 0 2006.257.14:42:55.71#ibcon#about to read 4, iclass 4, count 0 2006.257.14:42:55.71#ibcon#read 4, iclass 4, count 0 2006.257.14:42:55.71#ibcon#about to read 5, iclass 4, count 0 2006.257.14:42:55.71#ibcon#read 5, iclass 4, count 0 2006.257.14:42:55.71#ibcon#about to read 6, iclass 4, count 0 2006.257.14:42:55.71#ibcon#read 6, iclass 4, count 0 2006.257.14:42:55.71#ibcon#end of sib2, iclass 4, count 0 2006.257.14:42:55.71#ibcon#*after write, iclass 4, count 0 2006.257.14:42:55.71#ibcon#*before return 0, iclass 4, count 0 2006.257.14:42:55.71#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:55.71#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:42:55.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:42:55.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:42:55.71$vck44/vabw=wide 2006.257.14:42:55.71#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.14:42:55.71#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.14:42:55.71#ibcon#ireg 8 cls_cnt 0 2006.257.14:42:55.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:55.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:55.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:55.71#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:42:55.71#ibcon#first serial, iclass 6, count 0 2006.257.14:42:55.71#ibcon#enter sib2, iclass 6, count 0 2006.257.14:42:55.71#ibcon#flushed, iclass 6, count 0 2006.257.14:42:55.71#ibcon#about to write, iclass 6, count 0 2006.257.14:42:55.71#ibcon#wrote, iclass 6, count 0 2006.257.14:42:55.71#ibcon#about to read 3, iclass 6, count 0 2006.257.14:42:55.73#ibcon#read 3, iclass 6, count 0 2006.257.14:42:55.73#ibcon#about to read 4, iclass 6, count 0 2006.257.14:42:55.73#ibcon#read 4, iclass 6, count 0 2006.257.14:42:55.73#ibcon#about to read 5, iclass 6, count 0 2006.257.14:42:55.73#ibcon#read 5, iclass 6, count 0 2006.257.14:42:55.73#ibcon#about to read 6, iclass 6, count 0 2006.257.14:42:55.73#ibcon#read 6, iclass 6, count 0 2006.257.14:42:55.73#ibcon#end of sib2, iclass 6, count 0 2006.257.14:42:55.73#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:42:55.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:42:55.73#ibcon#[25=BW32\r\n] 2006.257.14:42:55.73#ibcon#*before write, iclass 6, count 0 2006.257.14:42:55.73#ibcon#enter sib2, iclass 6, count 0 2006.257.14:42:55.73#ibcon#flushed, iclass 6, count 0 2006.257.14:42:55.73#ibcon#about to write, iclass 6, count 0 2006.257.14:42:55.73#ibcon#wrote, iclass 6, count 0 2006.257.14:42:55.73#ibcon#about to read 3, iclass 6, count 0 2006.257.14:42:55.76#ibcon#read 3, iclass 6, count 0 2006.257.14:42:55.76#ibcon#about to read 4, iclass 6, count 0 2006.257.14:42:55.76#ibcon#read 4, iclass 6, count 0 2006.257.14:42:55.76#ibcon#about to read 5, iclass 6, count 0 2006.257.14:42:55.76#ibcon#read 5, iclass 6, count 0 2006.257.14:42:55.76#ibcon#about to read 6, iclass 6, count 0 2006.257.14:42:55.76#ibcon#read 6, iclass 6, count 0 2006.257.14:42:55.76#ibcon#end of sib2, iclass 6, count 0 2006.257.14:42:55.76#ibcon#*after write, iclass 6, count 0 2006.257.14:42:55.76#ibcon#*before return 0, iclass 6, count 0 2006.257.14:42:55.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:55.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:42:55.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:42:55.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:42:55.76$vck44/vbbw=wide 2006.257.14:42:55.76#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.14:42:55.76#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.14:42:55.76#ibcon#ireg 8 cls_cnt 0 2006.257.14:42:55.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:42:55.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:42:55.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:42:55.83#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:42:55.83#ibcon#first serial, iclass 10, count 0 2006.257.14:42:55.83#ibcon#enter sib2, iclass 10, count 0 2006.257.14:42:55.83#ibcon#flushed, iclass 10, count 0 2006.257.14:42:55.83#ibcon#about to write, iclass 10, count 0 2006.257.14:42:55.83#ibcon#wrote, iclass 10, count 0 2006.257.14:42:55.83#ibcon#about to read 3, iclass 10, count 0 2006.257.14:42:55.85#ibcon#read 3, iclass 10, count 0 2006.257.14:42:55.85#ibcon#about to read 4, iclass 10, count 0 2006.257.14:42:55.85#ibcon#read 4, iclass 10, count 0 2006.257.14:42:55.85#ibcon#about to read 5, iclass 10, count 0 2006.257.14:42:55.85#ibcon#read 5, iclass 10, count 0 2006.257.14:42:55.85#ibcon#about to read 6, iclass 10, count 0 2006.257.14:42:55.85#ibcon#read 6, iclass 10, count 0 2006.257.14:42:55.85#ibcon#end of sib2, iclass 10, count 0 2006.257.14:42:55.85#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:42:55.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:42:55.85#ibcon#[27=BW32\r\n] 2006.257.14:42:55.85#ibcon#*before write, iclass 10, count 0 2006.257.14:42:55.85#ibcon#enter sib2, iclass 10, count 0 2006.257.14:42:55.85#ibcon#flushed, iclass 10, count 0 2006.257.14:42:55.85#ibcon#about to write, iclass 10, count 0 2006.257.14:42:55.85#ibcon#wrote, iclass 10, count 0 2006.257.14:42:55.85#ibcon#about to read 3, iclass 10, count 0 2006.257.14:42:55.88#ibcon#read 3, iclass 10, count 0 2006.257.14:42:55.88#ibcon#about to read 4, iclass 10, count 0 2006.257.14:42:55.88#ibcon#read 4, iclass 10, count 0 2006.257.14:42:55.88#ibcon#about to read 5, iclass 10, count 0 2006.257.14:42:55.88#ibcon#read 5, iclass 10, count 0 2006.257.14:42:55.88#ibcon#about to read 6, iclass 10, count 0 2006.257.14:42:55.88#ibcon#read 6, iclass 10, count 0 2006.257.14:42:55.88#ibcon#end of sib2, iclass 10, count 0 2006.257.14:42:55.88#ibcon#*after write, iclass 10, count 0 2006.257.14:42:55.88#ibcon#*before return 0, iclass 10, count 0 2006.257.14:42:55.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:42:55.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:42:55.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:42:55.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:42:55.88$setupk4/ifdk4 2006.257.14:42:55.88$ifdk4/lo= 2006.257.14:42:55.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:42:55.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:42:55.88$ifdk4/patch= 2006.257.14:42:55.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:42:55.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:42:55.88$setupk4/!*+20s 2006.257.14:43:04.27#abcon#<5=/14 1.3 3.3 17.48 971014.1\r\n> 2006.257.14:43:04.29#abcon#{5=INTERFACE CLEAR} 2006.257.14:43:04.35#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:43:10.29$setupk4/"tpicd 2006.257.14:43:10.29$setupk4/echo=off 2006.257.14:43:10.29$setupk4/xlog=off 2006.257.14:43:10.29:!2006.257.14:48:11 2006.257.14:43:40.14#trakl#Source acquired 2006.257.14:43:42.14#flagr#flagr/antenna,acquired 2006.257.14:48:11.00:preob 2006.257.14:48:11.14/onsource/TRACKING 2006.257.14:48:11.14:!2006.257.14:48:21 2006.257.14:48:21.00:"tape 2006.257.14:48:21.00:"st=record 2006.257.14:48:21.00:data_valid=on 2006.257.14:48:21.00:midob 2006.257.14:48:21.14/onsource/TRACKING 2006.257.14:48:21.14/wx/17.47,1014.1,97 2006.257.14:48:21.32/cable/+6.4822E-03 2006.257.14:48:22.41/va/01,08,usb,yes,32,34 2006.257.14:48:22.41/va/02,07,usb,yes,35,35 2006.257.14:48:22.41/va/03,08,usb,yes,31,33 2006.257.14:48:22.41/va/04,07,usb,yes,36,38 2006.257.14:48:22.41/va/05,04,usb,yes,32,33 2006.257.14:48:22.41/va/06,04,usb,yes,36,35 2006.257.14:48:22.41/va/07,04,usb,yes,37,37 2006.257.14:48:22.41/va/08,04,usb,yes,31,37 2006.257.14:48:22.64/valo/01,524.99,yes,locked 2006.257.14:48:22.64/valo/02,534.99,yes,locked 2006.257.14:48:22.64/valo/03,564.99,yes,locked 2006.257.14:48:22.64/valo/04,624.99,yes,locked 2006.257.14:48:22.64/valo/05,734.99,yes,locked 2006.257.14:48:22.64/valo/06,814.99,yes,locked 2006.257.14:48:22.64/valo/07,864.99,yes,locked 2006.257.14:48:22.64/valo/08,884.99,yes,locked 2006.257.14:48:23.73/vb/01,04,usb,yes,32,29 2006.257.14:48:23.73/vb/02,05,usb,yes,30,30 2006.257.14:48:23.73/vb/03,04,usb,yes,31,34 2006.257.14:48:23.73/vb/04,05,usb,yes,31,30 2006.257.14:48:23.73/vb/05,04,usb,yes,28,30 2006.257.14:48:23.73/vb/06,04,usb,yes,32,28 2006.257.14:48:23.73/vb/07,04,usb,yes,32,32 2006.257.14:48:23.73/vb/08,04,usb,yes,30,33 2006.257.14:48:23.96/vblo/01,629.99,yes,locked 2006.257.14:48:23.96/vblo/02,634.99,yes,locked 2006.257.14:48:23.96/vblo/03,649.99,yes,locked 2006.257.14:48:23.96/vblo/04,679.99,yes,locked 2006.257.14:48:23.96/vblo/05,709.99,yes,locked 2006.257.14:48:23.96/vblo/06,719.99,yes,locked 2006.257.14:48:23.96/vblo/07,734.99,yes,locked 2006.257.14:48:23.96/vblo/08,744.99,yes,locked 2006.257.14:48:24.11/vabw/8 2006.257.14:48:24.26/vbbw/8 2006.257.14:48:24.41/xfe/off,on,15.2 2006.257.14:48:24.78/ifatt/23,28,28,28 2006.257.14:48:25.07/fmout-gps/S +4.59E-07 2006.257.14:48:25.11:!2006.257.14:49:21 2006.257.14:49:21.00:data_valid=off 2006.257.14:49:21.00:"et 2006.257.14:49:21.00:!+3s 2006.257.14:49:24.01:"tape 2006.257.14:49:24.01:postob 2006.257.14:49:24.12/cable/+6.4808E-03 2006.257.14:49:24.12/wx/17.47,1014.1,97 2006.257.14:49:25.07/fmout-gps/S +4.60E-07 2006.257.14:49:25.07:scan_name=257-1454,jd0609,80 2006.257.14:49:25.07:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.14:49:25.14#flagr#flagr/antenna,new-source 2006.257.14:49:26.14:checkk5 2006.257.14:49:26.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:49:26.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:49:27.35/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:49:27.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:49:28.13/chk_obsdata//k5ts1/T2571448??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.14:49:28.53/chk_obsdata//k5ts2/T2571448??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.14:49:28.93/chk_obsdata//k5ts3/T2571448??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.14:49:29.33/chk_obsdata//k5ts4/T2571448??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.14:49:30.04/k5log//k5ts1_log_newline 2006.257.14:49:30.75/k5log//k5ts2_log_newline 2006.257.14:49:31.46/k5log//k5ts3_log_newline 2006.257.14:49:32.15/k5log//k5ts4_log_newline 2006.257.14:49:32.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:49:32.18:setupk4=1 2006.257.14:49:32.18$setupk4/echo=on 2006.257.14:49:32.18$setupk4/pcalon 2006.257.14:49:32.18$pcalon/"no phase cal control is implemented here 2006.257.14:49:32.18$setupk4/"tpicd=stop 2006.257.14:49:32.18$setupk4/"rec=synch_on 2006.257.14:49:32.18$setupk4/"rec_mode=128 2006.257.14:49:32.18$setupk4/!* 2006.257.14:49:32.18$setupk4/recpk4 2006.257.14:49:32.18$recpk4/recpatch= 2006.257.14:49:32.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:49:32.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:49:32.18$setupk4/vck44 2006.257.14:49:32.18$vck44/valo=1,524.99 2006.257.14:49:32.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.14:49:32.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.14:49:32.18#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:32.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:32.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:32.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:32.18#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:49:32.18#ibcon#first serial, iclass 18, count 0 2006.257.14:49:32.18#ibcon#enter sib2, iclass 18, count 0 2006.257.14:49:32.18#ibcon#flushed, iclass 18, count 0 2006.257.14:49:32.18#ibcon#about to write, iclass 18, count 0 2006.257.14:49:32.18#ibcon#wrote, iclass 18, count 0 2006.257.14:49:32.18#ibcon#about to read 3, iclass 18, count 0 2006.257.14:49:32.20#ibcon#read 3, iclass 18, count 0 2006.257.14:49:32.20#ibcon#about to read 4, iclass 18, count 0 2006.257.14:49:32.20#ibcon#read 4, iclass 18, count 0 2006.257.14:49:32.20#ibcon#about to read 5, iclass 18, count 0 2006.257.14:49:32.20#ibcon#read 5, iclass 18, count 0 2006.257.14:49:32.20#ibcon#about to read 6, iclass 18, count 0 2006.257.14:49:32.20#ibcon#read 6, iclass 18, count 0 2006.257.14:49:32.20#ibcon#end of sib2, iclass 18, count 0 2006.257.14:49:32.20#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:49:32.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:49:32.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:49:32.20#ibcon#*before write, iclass 18, count 0 2006.257.14:49:32.20#ibcon#enter sib2, iclass 18, count 0 2006.257.14:49:32.20#ibcon#flushed, iclass 18, count 0 2006.257.14:49:32.20#ibcon#about to write, iclass 18, count 0 2006.257.14:49:32.20#ibcon#wrote, iclass 18, count 0 2006.257.14:49:32.20#ibcon#about to read 3, iclass 18, count 0 2006.257.14:49:32.25#ibcon#read 3, iclass 18, count 0 2006.257.14:49:32.25#ibcon#about to read 4, iclass 18, count 0 2006.257.14:49:32.25#ibcon#read 4, iclass 18, count 0 2006.257.14:49:32.25#ibcon#about to read 5, iclass 18, count 0 2006.257.14:49:32.25#ibcon#read 5, iclass 18, count 0 2006.257.14:49:32.25#ibcon#about to read 6, iclass 18, count 0 2006.257.14:49:32.25#ibcon#read 6, iclass 18, count 0 2006.257.14:49:32.25#ibcon#end of sib2, iclass 18, count 0 2006.257.14:49:32.25#ibcon#*after write, iclass 18, count 0 2006.257.14:49:32.25#ibcon#*before return 0, iclass 18, count 0 2006.257.14:49:32.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:32.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:32.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:49:32.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:49:32.25$vck44/va=1,8 2006.257.14:49:32.25#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.14:49:32.25#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.14:49:32.25#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:32.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:32.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:32.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:32.25#ibcon#enter wrdev, iclass 20, count 2 2006.257.14:49:32.25#ibcon#first serial, iclass 20, count 2 2006.257.14:49:32.25#ibcon#enter sib2, iclass 20, count 2 2006.257.14:49:32.25#ibcon#flushed, iclass 20, count 2 2006.257.14:49:32.25#ibcon#about to write, iclass 20, count 2 2006.257.14:49:32.25#ibcon#wrote, iclass 20, count 2 2006.257.14:49:32.25#ibcon#about to read 3, iclass 20, count 2 2006.257.14:49:32.27#ibcon#read 3, iclass 20, count 2 2006.257.14:49:32.27#ibcon#about to read 4, iclass 20, count 2 2006.257.14:49:32.27#ibcon#read 4, iclass 20, count 2 2006.257.14:49:32.27#ibcon#about to read 5, iclass 20, count 2 2006.257.14:49:32.27#ibcon#read 5, iclass 20, count 2 2006.257.14:49:32.27#ibcon#about to read 6, iclass 20, count 2 2006.257.14:49:32.27#ibcon#read 6, iclass 20, count 2 2006.257.14:49:32.27#ibcon#end of sib2, iclass 20, count 2 2006.257.14:49:32.27#ibcon#*mode == 0, iclass 20, count 2 2006.257.14:49:32.27#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.14:49:32.27#ibcon#[25=AT01-08\r\n] 2006.257.14:49:32.27#ibcon#*before write, iclass 20, count 2 2006.257.14:49:32.27#ibcon#enter sib2, iclass 20, count 2 2006.257.14:49:32.27#ibcon#flushed, iclass 20, count 2 2006.257.14:49:32.27#ibcon#about to write, iclass 20, count 2 2006.257.14:49:32.27#ibcon#wrote, iclass 20, count 2 2006.257.14:49:32.27#ibcon#about to read 3, iclass 20, count 2 2006.257.14:49:32.30#ibcon#read 3, iclass 20, count 2 2006.257.14:49:32.30#ibcon#about to read 4, iclass 20, count 2 2006.257.14:49:32.30#ibcon#read 4, iclass 20, count 2 2006.257.14:49:32.30#ibcon#about to read 5, iclass 20, count 2 2006.257.14:49:32.30#ibcon#read 5, iclass 20, count 2 2006.257.14:49:32.30#ibcon#about to read 6, iclass 20, count 2 2006.257.14:49:32.30#ibcon#read 6, iclass 20, count 2 2006.257.14:49:32.30#ibcon#end of sib2, iclass 20, count 2 2006.257.14:49:32.30#ibcon#*after write, iclass 20, count 2 2006.257.14:49:32.30#ibcon#*before return 0, iclass 20, count 2 2006.257.14:49:32.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:32.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:32.30#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.14:49:32.30#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:32.30#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:32.42#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:32.42#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:32.42#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:49:32.42#ibcon#first serial, iclass 20, count 0 2006.257.14:49:32.42#ibcon#enter sib2, iclass 20, count 0 2006.257.14:49:32.42#ibcon#flushed, iclass 20, count 0 2006.257.14:49:32.42#ibcon#about to write, iclass 20, count 0 2006.257.14:49:32.42#ibcon#wrote, iclass 20, count 0 2006.257.14:49:32.42#ibcon#about to read 3, iclass 20, count 0 2006.257.14:49:32.44#ibcon#read 3, iclass 20, count 0 2006.257.14:49:32.44#ibcon#about to read 4, iclass 20, count 0 2006.257.14:49:32.44#ibcon#read 4, iclass 20, count 0 2006.257.14:49:32.44#ibcon#about to read 5, iclass 20, count 0 2006.257.14:49:32.44#ibcon#read 5, iclass 20, count 0 2006.257.14:49:32.44#ibcon#about to read 6, iclass 20, count 0 2006.257.14:49:32.44#ibcon#read 6, iclass 20, count 0 2006.257.14:49:32.44#ibcon#end of sib2, iclass 20, count 0 2006.257.14:49:32.44#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:49:32.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:49:32.44#ibcon#[25=USB\r\n] 2006.257.14:49:32.44#ibcon#*before write, iclass 20, count 0 2006.257.14:49:32.44#ibcon#enter sib2, iclass 20, count 0 2006.257.14:49:32.44#ibcon#flushed, iclass 20, count 0 2006.257.14:49:32.44#ibcon#about to write, iclass 20, count 0 2006.257.14:49:32.44#ibcon#wrote, iclass 20, count 0 2006.257.14:49:32.44#ibcon#about to read 3, iclass 20, count 0 2006.257.14:49:32.47#ibcon#read 3, iclass 20, count 0 2006.257.14:49:32.47#ibcon#about to read 4, iclass 20, count 0 2006.257.14:49:32.47#ibcon#read 4, iclass 20, count 0 2006.257.14:49:32.47#ibcon#about to read 5, iclass 20, count 0 2006.257.14:49:32.47#ibcon#read 5, iclass 20, count 0 2006.257.14:49:32.47#ibcon#about to read 6, iclass 20, count 0 2006.257.14:49:32.47#ibcon#read 6, iclass 20, count 0 2006.257.14:49:32.47#ibcon#end of sib2, iclass 20, count 0 2006.257.14:49:32.47#ibcon#*after write, iclass 20, count 0 2006.257.14:49:32.47#ibcon#*before return 0, iclass 20, count 0 2006.257.14:49:32.47#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:32.47#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:32.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:49:32.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:49:32.47$vck44/valo=2,534.99 2006.257.14:49:32.47#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.14:49:32.47#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.14:49:32.47#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:32.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:32.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:32.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:32.47#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:49:32.47#ibcon#first serial, iclass 22, count 0 2006.257.14:49:32.47#ibcon#enter sib2, iclass 22, count 0 2006.257.14:49:32.47#ibcon#flushed, iclass 22, count 0 2006.257.14:49:32.47#ibcon#about to write, iclass 22, count 0 2006.257.14:49:32.47#ibcon#wrote, iclass 22, count 0 2006.257.14:49:32.47#ibcon#about to read 3, iclass 22, count 0 2006.257.14:49:32.49#ibcon#read 3, iclass 22, count 0 2006.257.14:49:32.49#ibcon#about to read 4, iclass 22, count 0 2006.257.14:49:32.49#ibcon#read 4, iclass 22, count 0 2006.257.14:49:32.49#ibcon#about to read 5, iclass 22, count 0 2006.257.14:49:32.49#ibcon#read 5, iclass 22, count 0 2006.257.14:49:32.49#ibcon#about to read 6, iclass 22, count 0 2006.257.14:49:32.49#ibcon#read 6, iclass 22, count 0 2006.257.14:49:32.49#ibcon#end of sib2, iclass 22, count 0 2006.257.14:49:32.49#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:49:32.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:49:32.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:49:32.49#ibcon#*before write, iclass 22, count 0 2006.257.14:49:32.49#ibcon#enter sib2, iclass 22, count 0 2006.257.14:49:32.49#ibcon#flushed, iclass 22, count 0 2006.257.14:49:32.49#ibcon#about to write, iclass 22, count 0 2006.257.14:49:32.49#ibcon#wrote, iclass 22, count 0 2006.257.14:49:32.49#ibcon#about to read 3, iclass 22, count 0 2006.257.14:49:32.53#ibcon#read 3, iclass 22, count 0 2006.257.14:49:32.53#ibcon#about to read 4, iclass 22, count 0 2006.257.14:49:32.53#ibcon#read 4, iclass 22, count 0 2006.257.14:49:32.53#ibcon#about to read 5, iclass 22, count 0 2006.257.14:49:32.53#ibcon#read 5, iclass 22, count 0 2006.257.14:49:32.53#ibcon#about to read 6, iclass 22, count 0 2006.257.14:49:32.53#ibcon#read 6, iclass 22, count 0 2006.257.14:49:32.53#ibcon#end of sib2, iclass 22, count 0 2006.257.14:49:32.53#ibcon#*after write, iclass 22, count 0 2006.257.14:49:32.53#ibcon#*before return 0, iclass 22, count 0 2006.257.14:49:32.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:32.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:32.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:49:32.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:49:32.53$vck44/va=2,7 2006.257.14:49:32.53#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.14:49:32.53#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.14:49:32.53#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:32.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:32.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:32.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:32.59#ibcon#enter wrdev, iclass 24, count 2 2006.257.14:49:32.59#ibcon#first serial, iclass 24, count 2 2006.257.14:49:32.59#ibcon#enter sib2, iclass 24, count 2 2006.257.14:49:32.59#ibcon#flushed, iclass 24, count 2 2006.257.14:49:32.59#ibcon#about to write, iclass 24, count 2 2006.257.14:49:32.59#ibcon#wrote, iclass 24, count 2 2006.257.14:49:32.59#ibcon#about to read 3, iclass 24, count 2 2006.257.14:49:32.61#ibcon#read 3, iclass 24, count 2 2006.257.14:49:32.61#ibcon#about to read 4, iclass 24, count 2 2006.257.14:49:32.61#ibcon#read 4, iclass 24, count 2 2006.257.14:49:32.61#ibcon#about to read 5, iclass 24, count 2 2006.257.14:49:32.61#ibcon#read 5, iclass 24, count 2 2006.257.14:49:32.61#ibcon#about to read 6, iclass 24, count 2 2006.257.14:49:32.61#ibcon#read 6, iclass 24, count 2 2006.257.14:49:32.61#ibcon#end of sib2, iclass 24, count 2 2006.257.14:49:32.61#ibcon#*mode == 0, iclass 24, count 2 2006.257.14:49:32.61#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.14:49:32.61#ibcon#[25=AT02-07\r\n] 2006.257.14:49:32.61#ibcon#*before write, iclass 24, count 2 2006.257.14:49:32.61#ibcon#enter sib2, iclass 24, count 2 2006.257.14:49:32.61#ibcon#flushed, iclass 24, count 2 2006.257.14:49:32.61#ibcon#about to write, iclass 24, count 2 2006.257.14:49:32.61#ibcon#wrote, iclass 24, count 2 2006.257.14:49:32.61#ibcon#about to read 3, iclass 24, count 2 2006.257.14:49:32.64#ibcon#read 3, iclass 24, count 2 2006.257.14:49:32.64#ibcon#about to read 4, iclass 24, count 2 2006.257.14:49:32.64#ibcon#read 4, iclass 24, count 2 2006.257.14:49:32.64#ibcon#about to read 5, iclass 24, count 2 2006.257.14:49:32.64#ibcon#read 5, iclass 24, count 2 2006.257.14:49:32.64#ibcon#about to read 6, iclass 24, count 2 2006.257.14:49:32.64#ibcon#read 6, iclass 24, count 2 2006.257.14:49:32.64#ibcon#end of sib2, iclass 24, count 2 2006.257.14:49:32.64#ibcon#*after write, iclass 24, count 2 2006.257.14:49:32.64#ibcon#*before return 0, iclass 24, count 2 2006.257.14:49:32.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:32.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:32.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.14:49:32.64#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:32.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:32.76#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:32.76#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:32.76#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:49:32.76#ibcon#first serial, iclass 24, count 0 2006.257.14:49:32.76#ibcon#enter sib2, iclass 24, count 0 2006.257.14:49:32.76#ibcon#flushed, iclass 24, count 0 2006.257.14:49:32.76#ibcon#about to write, iclass 24, count 0 2006.257.14:49:32.76#ibcon#wrote, iclass 24, count 0 2006.257.14:49:32.76#ibcon#about to read 3, iclass 24, count 0 2006.257.14:49:32.78#ibcon#read 3, iclass 24, count 0 2006.257.14:49:32.78#ibcon#about to read 4, iclass 24, count 0 2006.257.14:49:32.78#ibcon#read 4, iclass 24, count 0 2006.257.14:49:32.78#ibcon#about to read 5, iclass 24, count 0 2006.257.14:49:32.78#ibcon#read 5, iclass 24, count 0 2006.257.14:49:32.78#ibcon#about to read 6, iclass 24, count 0 2006.257.14:49:32.78#ibcon#read 6, iclass 24, count 0 2006.257.14:49:32.78#ibcon#end of sib2, iclass 24, count 0 2006.257.14:49:32.78#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:49:32.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:49:32.78#ibcon#[25=USB\r\n] 2006.257.14:49:32.78#ibcon#*before write, iclass 24, count 0 2006.257.14:49:32.78#ibcon#enter sib2, iclass 24, count 0 2006.257.14:49:32.78#ibcon#flushed, iclass 24, count 0 2006.257.14:49:32.78#ibcon#about to write, iclass 24, count 0 2006.257.14:49:32.78#ibcon#wrote, iclass 24, count 0 2006.257.14:49:32.78#ibcon#about to read 3, iclass 24, count 0 2006.257.14:49:32.81#ibcon#read 3, iclass 24, count 0 2006.257.14:49:32.81#ibcon#about to read 4, iclass 24, count 0 2006.257.14:49:32.81#ibcon#read 4, iclass 24, count 0 2006.257.14:49:32.81#ibcon#about to read 5, iclass 24, count 0 2006.257.14:49:32.81#ibcon#read 5, iclass 24, count 0 2006.257.14:49:32.81#ibcon#about to read 6, iclass 24, count 0 2006.257.14:49:32.81#ibcon#read 6, iclass 24, count 0 2006.257.14:49:32.81#ibcon#end of sib2, iclass 24, count 0 2006.257.14:49:32.81#ibcon#*after write, iclass 24, count 0 2006.257.14:49:32.81#ibcon#*before return 0, iclass 24, count 0 2006.257.14:49:32.81#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:32.81#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:32.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:49:32.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:49:32.81$vck44/valo=3,564.99 2006.257.14:49:32.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.14:49:32.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.14:49:32.81#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:32.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:32.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:32.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:32.81#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:49:32.81#ibcon#first serial, iclass 26, count 0 2006.257.14:49:32.81#ibcon#enter sib2, iclass 26, count 0 2006.257.14:49:32.81#ibcon#flushed, iclass 26, count 0 2006.257.14:49:32.81#ibcon#about to write, iclass 26, count 0 2006.257.14:49:32.81#ibcon#wrote, iclass 26, count 0 2006.257.14:49:32.81#ibcon#about to read 3, iclass 26, count 0 2006.257.14:49:32.83#ibcon#read 3, iclass 26, count 0 2006.257.14:49:32.83#ibcon#about to read 4, iclass 26, count 0 2006.257.14:49:32.83#ibcon#read 4, iclass 26, count 0 2006.257.14:49:32.83#ibcon#about to read 5, iclass 26, count 0 2006.257.14:49:32.83#ibcon#read 5, iclass 26, count 0 2006.257.14:49:32.83#ibcon#about to read 6, iclass 26, count 0 2006.257.14:49:32.83#ibcon#read 6, iclass 26, count 0 2006.257.14:49:32.83#ibcon#end of sib2, iclass 26, count 0 2006.257.14:49:32.83#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:49:32.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:49:32.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:49:32.83#ibcon#*before write, iclass 26, count 0 2006.257.14:49:32.83#ibcon#enter sib2, iclass 26, count 0 2006.257.14:49:32.83#ibcon#flushed, iclass 26, count 0 2006.257.14:49:32.83#ibcon#about to write, iclass 26, count 0 2006.257.14:49:32.83#ibcon#wrote, iclass 26, count 0 2006.257.14:49:32.83#ibcon#about to read 3, iclass 26, count 0 2006.257.14:49:32.87#ibcon#read 3, iclass 26, count 0 2006.257.14:49:32.87#ibcon#about to read 4, iclass 26, count 0 2006.257.14:49:32.87#ibcon#read 4, iclass 26, count 0 2006.257.14:49:32.87#ibcon#about to read 5, iclass 26, count 0 2006.257.14:49:32.87#ibcon#read 5, iclass 26, count 0 2006.257.14:49:32.87#ibcon#about to read 6, iclass 26, count 0 2006.257.14:49:32.87#ibcon#read 6, iclass 26, count 0 2006.257.14:49:32.87#ibcon#end of sib2, iclass 26, count 0 2006.257.14:49:32.87#ibcon#*after write, iclass 26, count 0 2006.257.14:49:32.87#ibcon#*before return 0, iclass 26, count 0 2006.257.14:49:32.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:32.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:32.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:49:32.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:49:32.87$vck44/va=3,8 2006.257.14:49:32.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.14:49:32.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.14:49:32.87#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:32.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:32.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:32.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:32.93#ibcon#enter wrdev, iclass 28, count 2 2006.257.14:49:32.93#ibcon#first serial, iclass 28, count 2 2006.257.14:49:32.93#ibcon#enter sib2, iclass 28, count 2 2006.257.14:49:32.93#ibcon#flushed, iclass 28, count 2 2006.257.14:49:32.93#ibcon#about to write, iclass 28, count 2 2006.257.14:49:32.93#ibcon#wrote, iclass 28, count 2 2006.257.14:49:32.93#ibcon#about to read 3, iclass 28, count 2 2006.257.14:49:32.95#ibcon#read 3, iclass 28, count 2 2006.257.14:49:32.95#ibcon#about to read 4, iclass 28, count 2 2006.257.14:49:32.95#ibcon#read 4, iclass 28, count 2 2006.257.14:49:32.95#ibcon#about to read 5, iclass 28, count 2 2006.257.14:49:32.95#ibcon#read 5, iclass 28, count 2 2006.257.14:49:32.95#ibcon#about to read 6, iclass 28, count 2 2006.257.14:49:32.95#ibcon#read 6, iclass 28, count 2 2006.257.14:49:32.95#ibcon#end of sib2, iclass 28, count 2 2006.257.14:49:32.95#ibcon#*mode == 0, iclass 28, count 2 2006.257.14:49:32.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.14:49:32.95#ibcon#[25=AT03-08\r\n] 2006.257.14:49:32.95#ibcon#*before write, iclass 28, count 2 2006.257.14:49:32.95#ibcon#enter sib2, iclass 28, count 2 2006.257.14:49:32.95#ibcon#flushed, iclass 28, count 2 2006.257.14:49:32.95#ibcon#about to write, iclass 28, count 2 2006.257.14:49:32.95#ibcon#wrote, iclass 28, count 2 2006.257.14:49:32.95#ibcon#about to read 3, iclass 28, count 2 2006.257.14:49:32.98#ibcon#read 3, iclass 28, count 2 2006.257.14:49:32.98#ibcon#about to read 4, iclass 28, count 2 2006.257.14:49:32.98#ibcon#read 4, iclass 28, count 2 2006.257.14:49:32.98#ibcon#about to read 5, iclass 28, count 2 2006.257.14:49:32.98#ibcon#read 5, iclass 28, count 2 2006.257.14:49:32.98#ibcon#about to read 6, iclass 28, count 2 2006.257.14:49:32.98#ibcon#read 6, iclass 28, count 2 2006.257.14:49:32.98#ibcon#end of sib2, iclass 28, count 2 2006.257.14:49:32.98#ibcon#*after write, iclass 28, count 2 2006.257.14:49:32.98#ibcon#*before return 0, iclass 28, count 2 2006.257.14:49:32.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:32.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:32.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.14:49:32.98#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:32.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:33.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:33.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:33.10#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:49:33.10#ibcon#first serial, iclass 28, count 0 2006.257.14:49:33.10#ibcon#enter sib2, iclass 28, count 0 2006.257.14:49:33.10#ibcon#flushed, iclass 28, count 0 2006.257.14:49:33.10#ibcon#about to write, iclass 28, count 0 2006.257.14:49:33.10#ibcon#wrote, iclass 28, count 0 2006.257.14:49:33.10#ibcon#about to read 3, iclass 28, count 0 2006.257.14:49:33.12#ibcon#read 3, iclass 28, count 0 2006.257.14:49:33.12#ibcon#about to read 4, iclass 28, count 0 2006.257.14:49:33.12#ibcon#read 4, iclass 28, count 0 2006.257.14:49:33.12#ibcon#about to read 5, iclass 28, count 0 2006.257.14:49:33.12#ibcon#read 5, iclass 28, count 0 2006.257.14:49:33.12#ibcon#about to read 6, iclass 28, count 0 2006.257.14:49:33.12#ibcon#read 6, iclass 28, count 0 2006.257.14:49:33.12#ibcon#end of sib2, iclass 28, count 0 2006.257.14:49:33.12#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:49:33.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:49:33.12#ibcon#[25=USB\r\n] 2006.257.14:49:33.12#ibcon#*before write, iclass 28, count 0 2006.257.14:49:33.12#ibcon#enter sib2, iclass 28, count 0 2006.257.14:49:33.12#ibcon#flushed, iclass 28, count 0 2006.257.14:49:33.12#ibcon#about to write, iclass 28, count 0 2006.257.14:49:33.12#ibcon#wrote, iclass 28, count 0 2006.257.14:49:33.12#ibcon#about to read 3, iclass 28, count 0 2006.257.14:49:33.15#ibcon#read 3, iclass 28, count 0 2006.257.14:49:33.15#ibcon#about to read 4, iclass 28, count 0 2006.257.14:49:33.15#ibcon#read 4, iclass 28, count 0 2006.257.14:49:33.15#ibcon#about to read 5, iclass 28, count 0 2006.257.14:49:33.15#ibcon#read 5, iclass 28, count 0 2006.257.14:49:33.15#ibcon#about to read 6, iclass 28, count 0 2006.257.14:49:33.15#ibcon#read 6, iclass 28, count 0 2006.257.14:49:33.15#ibcon#end of sib2, iclass 28, count 0 2006.257.14:49:33.15#ibcon#*after write, iclass 28, count 0 2006.257.14:49:33.15#ibcon#*before return 0, iclass 28, count 0 2006.257.14:49:33.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:33.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:33.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:49:33.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:49:33.15$vck44/valo=4,624.99 2006.257.14:49:33.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.14:49:33.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.14:49:33.15#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:33.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:33.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:33.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:33.15#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:49:33.15#ibcon#first serial, iclass 30, count 0 2006.257.14:49:33.15#ibcon#enter sib2, iclass 30, count 0 2006.257.14:49:33.15#ibcon#flushed, iclass 30, count 0 2006.257.14:49:33.15#ibcon#about to write, iclass 30, count 0 2006.257.14:49:33.15#ibcon#wrote, iclass 30, count 0 2006.257.14:49:33.15#ibcon#about to read 3, iclass 30, count 0 2006.257.14:49:33.17#ibcon#read 3, iclass 30, count 0 2006.257.14:49:33.17#ibcon#about to read 4, iclass 30, count 0 2006.257.14:49:33.17#ibcon#read 4, iclass 30, count 0 2006.257.14:49:33.17#ibcon#about to read 5, iclass 30, count 0 2006.257.14:49:33.17#ibcon#read 5, iclass 30, count 0 2006.257.14:49:33.17#ibcon#about to read 6, iclass 30, count 0 2006.257.14:49:33.17#ibcon#read 6, iclass 30, count 0 2006.257.14:49:33.17#ibcon#end of sib2, iclass 30, count 0 2006.257.14:49:33.17#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:49:33.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:49:33.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:49:33.17#ibcon#*before write, iclass 30, count 0 2006.257.14:49:33.17#ibcon#enter sib2, iclass 30, count 0 2006.257.14:49:33.17#ibcon#flushed, iclass 30, count 0 2006.257.14:49:33.17#ibcon#about to write, iclass 30, count 0 2006.257.14:49:33.17#ibcon#wrote, iclass 30, count 0 2006.257.14:49:33.17#ibcon#about to read 3, iclass 30, count 0 2006.257.14:49:33.21#ibcon#read 3, iclass 30, count 0 2006.257.14:49:33.21#ibcon#about to read 4, iclass 30, count 0 2006.257.14:49:33.21#ibcon#read 4, iclass 30, count 0 2006.257.14:49:33.21#ibcon#about to read 5, iclass 30, count 0 2006.257.14:49:33.21#ibcon#read 5, iclass 30, count 0 2006.257.14:49:33.21#ibcon#about to read 6, iclass 30, count 0 2006.257.14:49:33.21#ibcon#read 6, iclass 30, count 0 2006.257.14:49:33.21#ibcon#end of sib2, iclass 30, count 0 2006.257.14:49:33.21#ibcon#*after write, iclass 30, count 0 2006.257.14:49:33.21#ibcon#*before return 0, iclass 30, count 0 2006.257.14:49:33.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:33.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:33.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:49:33.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:49:33.21$vck44/va=4,7 2006.257.14:49:33.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.14:49:33.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.14:49:33.21#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:33.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:33.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:33.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:33.27#ibcon#enter wrdev, iclass 32, count 2 2006.257.14:49:33.27#ibcon#first serial, iclass 32, count 2 2006.257.14:49:33.27#ibcon#enter sib2, iclass 32, count 2 2006.257.14:49:33.27#ibcon#flushed, iclass 32, count 2 2006.257.14:49:33.27#ibcon#about to write, iclass 32, count 2 2006.257.14:49:33.27#ibcon#wrote, iclass 32, count 2 2006.257.14:49:33.27#ibcon#about to read 3, iclass 32, count 2 2006.257.14:49:33.29#ibcon#read 3, iclass 32, count 2 2006.257.14:49:33.29#ibcon#about to read 4, iclass 32, count 2 2006.257.14:49:33.29#ibcon#read 4, iclass 32, count 2 2006.257.14:49:33.29#ibcon#about to read 5, iclass 32, count 2 2006.257.14:49:33.29#ibcon#read 5, iclass 32, count 2 2006.257.14:49:33.29#ibcon#about to read 6, iclass 32, count 2 2006.257.14:49:33.29#ibcon#read 6, iclass 32, count 2 2006.257.14:49:33.29#ibcon#end of sib2, iclass 32, count 2 2006.257.14:49:33.29#ibcon#*mode == 0, iclass 32, count 2 2006.257.14:49:33.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.14:49:33.29#ibcon#[25=AT04-07\r\n] 2006.257.14:49:33.29#ibcon#*before write, iclass 32, count 2 2006.257.14:49:33.29#ibcon#enter sib2, iclass 32, count 2 2006.257.14:49:33.29#ibcon#flushed, iclass 32, count 2 2006.257.14:49:33.29#ibcon#about to write, iclass 32, count 2 2006.257.14:49:33.29#ibcon#wrote, iclass 32, count 2 2006.257.14:49:33.29#ibcon#about to read 3, iclass 32, count 2 2006.257.14:49:33.32#ibcon#read 3, iclass 32, count 2 2006.257.14:49:33.32#ibcon#about to read 4, iclass 32, count 2 2006.257.14:49:33.32#ibcon#read 4, iclass 32, count 2 2006.257.14:49:33.32#ibcon#about to read 5, iclass 32, count 2 2006.257.14:49:33.32#ibcon#read 5, iclass 32, count 2 2006.257.14:49:33.32#ibcon#about to read 6, iclass 32, count 2 2006.257.14:49:33.32#ibcon#read 6, iclass 32, count 2 2006.257.14:49:33.32#ibcon#end of sib2, iclass 32, count 2 2006.257.14:49:33.32#ibcon#*after write, iclass 32, count 2 2006.257.14:49:33.32#ibcon#*before return 0, iclass 32, count 2 2006.257.14:49:33.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:33.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:33.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.14:49:33.32#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:33.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:33.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:33.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:33.44#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:49:33.44#ibcon#first serial, iclass 32, count 0 2006.257.14:49:33.44#ibcon#enter sib2, iclass 32, count 0 2006.257.14:49:33.44#ibcon#flushed, iclass 32, count 0 2006.257.14:49:33.44#ibcon#about to write, iclass 32, count 0 2006.257.14:49:33.44#ibcon#wrote, iclass 32, count 0 2006.257.14:49:33.44#ibcon#about to read 3, iclass 32, count 0 2006.257.14:49:33.46#ibcon#read 3, iclass 32, count 0 2006.257.14:49:33.46#ibcon#about to read 4, iclass 32, count 0 2006.257.14:49:33.46#ibcon#read 4, iclass 32, count 0 2006.257.14:49:33.46#ibcon#about to read 5, iclass 32, count 0 2006.257.14:49:33.46#ibcon#read 5, iclass 32, count 0 2006.257.14:49:33.46#ibcon#about to read 6, iclass 32, count 0 2006.257.14:49:33.46#ibcon#read 6, iclass 32, count 0 2006.257.14:49:33.46#ibcon#end of sib2, iclass 32, count 0 2006.257.14:49:33.46#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:49:33.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:49:33.46#ibcon#[25=USB\r\n] 2006.257.14:49:33.46#ibcon#*before write, iclass 32, count 0 2006.257.14:49:33.46#ibcon#enter sib2, iclass 32, count 0 2006.257.14:49:33.46#ibcon#flushed, iclass 32, count 0 2006.257.14:49:33.46#ibcon#about to write, iclass 32, count 0 2006.257.14:49:33.46#ibcon#wrote, iclass 32, count 0 2006.257.14:49:33.46#ibcon#about to read 3, iclass 32, count 0 2006.257.14:49:33.49#ibcon#read 3, iclass 32, count 0 2006.257.14:49:33.49#ibcon#about to read 4, iclass 32, count 0 2006.257.14:49:33.49#ibcon#read 4, iclass 32, count 0 2006.257.14:49:33.49#ibcon#about to read 5, iclass 32, count 0 2006.257.14:49:33.49#ibcon#read 5, iclass 32, count 0 2006.257.14:49:33.49#ibcon#about to read 6, iclass 32, count 0 2006.257.14:49:33.49#ibcon#read 6, iclass 32, count 0 2006.257.14:49:33.49#ibcon#end of sib2, iclass 32, count 0 2006.257.14:49:33.49#ibcon#*after write, iclass 32, count 0 2006.257.14:49:33.49#ibcon#*before return 0, iclass 32, count 0 2006.257.14:49:33.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:33.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:33.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:49:33.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:49:33.49$vck44/valo=5,734.99 2006.257.14:49:33.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.14:49:33.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.14:49:33.49#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:33.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:33.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:33.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:33.49#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:49:33.49#ibcon#first serial, iclass 34, count 0 2006.257.14:49:33.49#ibcon#enter sib2, iclass 34, count 0 2006.257.14:49:33.49#ibcon#flushed, iclass 34, count 0 2006.257.14:49:33.49#ibcon#about to write, iclass 34, count 0 2006.257.14:49:33.49#ibcon#wrote, iclass 34, count 0 2006.257.14:49:33.49#ibcon#about to read 3, iclass 34, count 0 2006.257.14:49:33.51#ibcon#read 3, iclass 34, count 0 2006.257.14:49:33.51#ibcon#about to read 4, iclass 34, count 0 2006.257.14:49:33.51#ibcon#read 4, iclass 34, count 0 2006.257.14:49:33.51#ibcon#about to read 5, iclass 34, count 0 2006.257.14:49:33.51#ibcon#read 5, iclass 34, count 0 2006.257.14:49:33.51#ibcon#about to read 6, iclass 34, count 0 2006.257.14:49:33.51#ibcon#read 6, iclass 34, count 0 2006.257.14:49:33.51#ibcon#end of sib2, iclass 34, count 0 2006.257.14:49:33.51#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:49:33.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:49:33.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:49:33.51#ibcon#*before write, iclass 34, count 0 2006.257.14:49:33.51#ibcon#enter sib2, iclass 34, count 0 2006.257.14:49:33.51#ibcon#flushed, iclass 34, count 0 2006.257.14:49:33.51#ibcon#about to write, iclass 34, count 0 2006.257.14:49:33.51#ibcon#wrote, iclass 34, count 0 2006.257.14:49:33.51#ibcon#about to read 3, iclass 34, count 0 2006.257.14:49:33.55#ibcon#read 3, iclass 34, count 0 2006.257.14:49:33.55#ibcon#about to read 4, iclass 34, count 0 2006.257.14:49:33.55#ibcon#read 4, iclass 34, count 0 2006.257.14:49:33.55#ibcon#about to read 5, iclass 34, count 0 2006.257.14:49:33.55#ibcon#read 5, iclass 34, count 0 2006.257.14:49:33.55#ibcon#about to read 6, iclass 34, count 0 2006.257.14:49:33.55#ibcon#read 6, iclass 34, count 0 2006.257.14:49:33.55#ibcon#end of sib2, iclass 34, count 0 2006.257.14:49:33.55#ibcon#*after write, iclass 34, count 0 2006.257.14:49:33.55#ibcon#*before return 0, iclass 34, count 0 2006.257.14:49:33.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:33.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:33.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:49:33.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:49:33.55$vck44/va=5,4 2006.257.14:49:33.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.14:49:33.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.14:49:33.55#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:33.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:33.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:33.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:33.61#ibcon#enter wrdev, iclass 36, count 2 2006.257.14:49:33.61#ibcon#first serial, iclass 36, count 2 2006.257.14:49:33.61#ibcon#enter sib2, iclass 36, count 2 2006.257.14:49:33.61#ibcon#flushed, iclass 36, count 2 2006.257.14:49:33.61#ibcon#about to write, iclass 36, count 2 2006.257.14:49:33.61#ibcon#wrote, iclass 36, count 2 2006.257.14:49:33.61#ibcon#about to read 3, iclass 36, count 2 2006.257.14:49:33.63#ibcon#read 3, iclass 36, count 2 2006.257.14:49:33.63#ibcon#about to read 4, iclass 36, count 2 2006.257.14:49:33.63#ibcon#read 4, iclass 36, count 2 2006.257.14:49:33.63#ibcon#about to read 5, iclass 36, count 2 2006.257.14:49:33.63#ibcon#read 5, iclass 36, count 2 2006.257.14:49:33.63#ibcon#about to read 6, iclass 36, count 2 2006.257.14:49:33.63#ibcon#read 6, iclass 36, count 2 2006.257.14:49:33.63#ibcon#end of sib2, iclass 36, count 2 2006.257.14:49:33.63#ibcon#*mode == 0, iclass 36, count 2 2006.257.14:49:33.63#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.14:49:33.63#ibcon#[25=AT05-04\r\n] 2006.257.14:49:33.63#ibcon#*before write, iclass 36, count 2 2006.257.14:49:33.63#ibcon#enter sib2, iclass 36, count 2 2006.257.14:49:33.63#ibcon#flushed, iclass 36, count 2 2006.257.14:49:33.63#ibcon#about to write, iclass 36, count 2 2006.257.14:49:33.63#ibcon#wrote, iclass 36, count 2 2006.257.14:49:33.63#ibcon#about to read 3, iclass 36, count 2 2006.257.14:49:33.65#abcon#<5=/14 1.2 3.3 17.47 971014.2\r\n> 2006.257.14:49:33.66#ibcon#read 3, iclass 36, count 2 2006.257.14:49:33.66#ibcon#about to read 4, iclass 36, count 2 2006.257.14:49:33.66#ibcon#read 4, iclass 36, count 2 2006.257.14:49:33.66#ibcon#about to read 5, iclass 36, count 2 2006.257.14:49:33.66#ibcon#read 5, iclass 36, count 2 2006.257.14:49:33.66#ibcon#about to read 6, iclass 36, count 2 2006.257.14:49:33.66#ibcon#read 6, iclass 36, count 2 2006.257.14:49:33.66#ibcon#end of sib2, iclass 36, count 2 2006.257.14:49:33.66#ibcon#*after write, iclass 36, count 2 2006.257.14:49:33.66#ibcon#*before return 0, iclass 36, count 2 2006.257.14:49:33.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:33.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:33.66#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.14:49:33.66#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:33.66#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:33.67#abcon#{5=INTERFACE CLEAR} 2006.257.14:49:33.73#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:49:33.78#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:33.78#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:33.78#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:49:33.78#ibcon#first serial, iclass 36, count 0 2006.257.14:49:33.78#ibcon#enter sib2, iclass 36, count 0 2006.257.14:49:33.78#ibcon#flushed, iclass 36, count 0 2006.257.14:49:33.78#ibcon#about to write, iclass 36, count 0 2006.257.14:49:33.78#ibcon#wrote, iclass 36, count 0 2006.257.14:49:33.78#ibcon#about to read 3, iclass 36, count 0 2006.257.14:49:33.80#ibcon#read 3, iclass 36, count 0 2006.257.14:49:33.80#ibcon#about to read 4, iclass 36, count 0 2006.257.14:49:33.80#ibcon#read 4, iclass 36, count 0 2006.257.14:49:33.80#ibcon#about to read 5, iclass 36, count 0 2006.257.14:49:33.80#ibcon#read 5, iclass 36, count 0 2006.257.14:49:33.80#ibcon#about to read 6, iclass 36, count 0 2006.257.14:49:33.80#ibcon#read 6, iclass 36, count 0 2006.257.14:49:33.80#ibcon#end of sib2, iclass 36, count 0 2006.257.14:49:33.80#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:49:33.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:49:33.80#ibcon#[25=USB\r\n] 2006.257.14:49:33.80#ibcon#*before write, iclass 36, count 0 2006.257.14:49:33.80#ibcon#enter sib2, iclass 36, count 0 2006.257.14:49:33.80#ibcon#flushed, iclass 36, count 0 2006.257.14:49:33.80#ibcon#about to write, iclass 36, count 0 2006.257.14:49:33.80#ibcon#wrote, iclass 36, count 0 2006.257.14:49:33.80#ibcon#about to read 3, iclass 36, count 0 2006.257.14:49:33.83#ibcon#read 3, iclass 36, count 0 2006.257.14:49:33.83#ibcon#about to read 4, iclass 36, count 0 2006.257.14:49:33.83#ibcon#read 4, iclass 36, count 0 2006.257.14:49:33.83#ibcon#about to read 5, iclass 36, count 0 2006.257.14:49:33.83#ibcon#read 5, iclass 36, count 0 2006.257.14:49:33.83#ibcon#about to read 6, iclass 36, count 0 2006.257.14:49:33.83#ibcon#read 6, iclass 36, count 0 2006.257.14:49:33.83#ibcon#end of sib2, iclass 36, count 0 2006.257.14:49:33.83#ibcon#*after write, iclass 36, count 0 2006.257.14:49:33.83#ibcon#*before return 0, iclass 36, count 0 2006.257.14:49:33.83#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:33.83#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:33.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:49:33.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:49:33.83$vck44/valo=6,814.99 2006.257.14:49:33.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.14:49:33.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.14:49:33.83#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:33.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:33.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:33.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:33.83#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:49:33.83#ibcon#first serial, iclass 4, count 0 2006.257.14:49:33.83#ibcon#enter sib2, iclass 4, count 0 2006.257.14:49:33.83#ibcon#flushed, iclass 4, count 0 2006.257.14:49:33.83#ibcon#about to write, iclass 4, count 0 2006.257.14:49:33.83#ibcon#wrote, iclass 4, count 0 2006.257.14:49:33.83#ibcon#about to read 3, iclass 4, count 0 2006.257.14:49:33.85#ibcon#read 3, iclass 4, count 0 2006.257.14:49:33.85#ibcon#about to read 4, iclass 4, count 0 2006.257.14:49:33.85#ibcon#read 4, iclass 4, count 0 2006.257.14:49:33.85#ibcon#about to read 5, iclass 4, count 0 2006.257.14:49:33.85#ibcon#read 5, iclass 4, count 0 2006.257.14:49:33.85#ibcon#about to read 6, iclass 4, count 0 2006.257.14:49:33.85#ibcon#read 6, iclass 4, count 0 2006.257.14:49:33.85#ibcon#end of sib2, iclass 4, count 0 2006.257.14:49:33.85#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:49:33.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:49:33.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:49:33.85#ibcon#*before write, iclass 4, count 0 2006.257.14:49:33.85#ibcon#enter sib2, iclass 4, count 0 2006.257.14:49:33.85#ibcon#flushed, iclass 4, count 0 2006.257.14:49:33.85#ibcon#about to write, iclass 4, count 0 2006.257.14:49:33.85#ibcon#wrote, iclass 4, count 0 2006.257.14:49:33.85#ibcon#about to read 3, iclass 4, count 0 2006.257.14:49:33.89#ibcon#read 3, iclass 4, count 0 2006.257.14:49:33.89#ibcon#about to read 4, iclass 4, count 0 2006.257.14:49:33.89#ibcon#read 4, iclass 4, count 0 2006.257.14:49:33.89#ibcon#about to read 5, iclass 4, count 0 2006.257.14:49:33.89#ibcon#read 5, iclass 4, count 0 2006.257.14:49:33.89#ibcon#about to read 6, iclass 4, count 0 2006.257.14:49:33.89#ibcon#read 6, iclass 4, count 0 2006.257.14:49:33.89#ibcon#end of sib2, iclass 4, count 0 2006.257.14:49:33.89#ibcon#*after write, iclass 4, count 0 2006.257.14:49:33.89#ibcon#*before return 0, iclass 4, count 0 2006.257.14:49:33.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:33.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:33.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:49:33.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:49:33.89$vck44/va=6,4 2006.257.14:49:33.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.14:49:33.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.14:49:33.89#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:33.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:33.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:33.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:33.95#ibcon#enter wrdev, iclass 6, count 2 2006.257.14:49:33.95#ibcon#first serial, iclass 6, count 2 2006.257.14:49:33.95#ibcon#enter sib2, iclass 6, count 2 2006.257.14:49:33.95#ibcon#flushed, iclass 6, count 2 2006.257.14:49:33.95#ibcon#about to write, iclass 6, count 2 2006.257.14:49:33.95#ibcon#wrote, iclass 6, count 2 2006.257.14:49:33.95#ibcon#about to read 3, iclass 6, count 2 2006.257.14:49:33.97#ibcon#read 3, iclass 6, count 2 2006.257.14:49:33.97#ibcon#about to read 4, iclass 6, count 2 2006.257.14:49:33.97#ibcon#read 4, iclass 6, count 2 2006.257.14:49:33.97#ibcon#about to read 5, iclass 6, count 2 2006.257.14:49:33.97#ibcon#read 5, iclass 6, count 2 2006.257.14:49:33.97#ibcon#about to read 6, iclass 6, count 2 2006.257.14:49:33.97#ibcon#read 6, iclass 6, count 2 2006.257.14:49:33.97#ibcon#end of sib2, iclass 6, count 2 2006.257.14:49:33.97#ibcon#*mode == 0, iclass 6, count 2 2006.257.14:49:33.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.14:49:33.97#ibcon#[25=AT06-04\r\n] 2006.257.14:49:33.97#ibcon#*before write, iclass 6, count 2 2006.257.14:49:33.97#ibcon#enter sib2, iclass 6, count 2 2006.257.14:49:33.97#ibcon#flushed, iclass 6, count 2 2006.257.14:49:33.97#ibcon#about to write, iclass 6, count 2 2006.257.14:49:33.97#ibcon#wrote, iclass 6, count 2 2006.257.14:49:33.97#ibcon#about to read 3, iclass 6, count 2 2006.257.14:49:34.00#ibcon#read 3, iclass 6, count 2 2006.257.14:49:34.00#ibcon#about to read 4, iclass 6, count 2 2006.257.14:49:34.00#ibcon#read 4, iclass 6, count 2 2006.257.14:49:34.00#ibcon#about to read 5, iclass 6, count 2 2006.257.14:49:34.00#ibcon#read 5, iclass 6, count 2 2006.257.14:49:34.00#ibcon#about to read 6, iclass 6, count 2 2006.257.14:49:34.00#ibcon#read 6, iclass 6, count 2 2006.257.14:49:34.00#ibcon#end of sib2, iclass 6, count 2 2006.257.14:49:34.00#ibcon#*after write, iclass 6, count 2 2006.257.14:49:34.00#ibcon#*before return 0, iclass 6, count 2 2006.257.14:49:34.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:34.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:34.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.14:49:34.00#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:34.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:34.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:34.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:34.12#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:49:34.12#ibcon#first serial, iclass 6, count 0 2006.257.14:49:34.12#ibcon#enter sib2, iclass 6, count 0 2006.257.14:49:34.12#ibcon#flushed, iclass 6, count 0 2006.257.14:49:34.12#ibcon#about to write, iclass 6, count 0 2006.257.14:49:34.12#ibcon#wrote, iclass 6, count 0 2006.257.14:49:34.12#ibcon#about to read 3, iclass 6, count 0 2006.257.14:49:34.14#ibcon#read 3, iclass 6, count 0 2006.257.14:49:34.14#ibcon#about to read 4, iclass 6, count 0 2006.257.14:49:34.14#ibcon#read 4, iclass 6, count 0 2006.257.14:49:34.14#ibcon#about to read 5, iclass 6, count 0 2006.257.14:49:34.14#ibcon#read 5, iclass 6, count 0 2006.257.14:49:34.14#ibcon#about to read 6, iclass 6, count 0 2006.257.14:49:34.14#ibcon#read 6, iclass 6, count 0 2006.257.14:49:34.14#ibcon#end of sib2, iclass 6, count 0 2006.257.14:49:34.14#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:49:34.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:49:34.14#ibcon#[25=USB\r\n] 2006.257.14:49:34.14#ibcon#*before write, iclass 6, count 0 2006.257.14:49:34.14#ibcon#enter sib2, iclass 6, count 0 2006.257.14:49:34.14#ibcon#flushed, iclass 6, count 0 2006.257.14:49:34.14#ibcon#about to write, iclass 6, count 0 2006.257.14:49:34.14#ibcon#wrote, iclass 6, count 0 2006.257.14:49:34.14#ibcon#about to read 3, iclass 6, count 0 2006.257.14:49:34.17#ibcon#read 3, iclass 6, count 0 2006.257.14:49:34.17#ibcon#about to read 4, iclass 6, count 0 2006.257.14:49:34.17#ibcon#read 4, iclass 6, count 0 2006.257.14:49:34.17#ibcon#about to read 5, iclass 6, count 0 2006.257.14:49:34.17#ibcon#read 5, iclass 6, count 0 2006.257.14:49:34.17#ibcon#about to read 6, iclass 6, count 0 2006.257.14:49:34.17#ibcon#read 6, iclass 6, count 0 2006.257.14:49:34.17#ibcon#end of sib2, iclass 6, count 0 2006.257.14:49:34.17#ibcon#*after write, iclass 6, count 0 2006.257.14:49:34.17#ibcon#*before return 0, iclass 6, count 0 2006.257.14:49:34.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:34.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:34.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:49:34.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:49:34.17$vck44/valo=7,864.99 2006.257.14:49:34.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.14:49:34.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.14:49:34.17#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:34.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:34.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:34.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:34.17#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:49:34.17#ibcon#first serial, iclass 10, count 0 2006.257.14:49:34.17#ibcon#enter sib2, iclass 10, count 0 2006.257.14:49:34.17#ibcon#flushed, iclass 10, count 0 2006.257.14:49:34.17#ibcon#about to write, iclass 10, count 0 2006.257.14:49:34.17#ibcon#wrote, iclass 10, count 0 2006.257.14:49:34.17#ibcon#about to read 3, iclass 10, count 0 2006.257.14:49:34.19#ibcon#read 3, iclass 10, count 0 2006.257.14:49:34.19#ibcon#about to read 4, iclass 10, count 0 2006.257.14:49:34.19#ibcon#read 4, iclass 10, count 0 2006.257.14:49:34.19#ibcon#about to read 5, iclass 10, count 0 2006.257.14:49:34.19#ibcon#read 5, iclass 10, count 0 2006.257.14:49:34.19#ibcon#about to read 6, iclass 10, count 0 2006.257.14:49:34.19#ibcon#read 6, iclass 10, count 0 2006.257.14:49:34.19#ibcon#end of sib2, iclass 10, count 0 2006.257.14:49:34.19#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:49:34.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:49:34.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:49:34.19#ibcon#*before write, iclass 10, count 0 2006.257.14:49:34.19#ibcon#enter sib2, iclass 10, count 0 2006.257.14:49:34.19#ibcon#flushed, iclass 10, count 0 2006.257.14:49:34.19#ibcon#about to write, iclass 10, count 0 2006.257.14:49:34.19#ibcon#wrote, iclass 10, count 0 2006.257.14:49:34.19#ibcon#about to read 3, iclass 10, count 0 2006.257.14:49:34.23#ibcon#read 3, iclass 10, count 0 2006.257.14:49:34.23#ibcon#about to read 4, iclass 10, count 0 2006.257.14:49:34.23#ibcon#read 4, iclass 10, count 0 2006.257.14:49:34.23#ibcon#about to read 5, iclass 10, count 0 2006.257.14:49:34.23#ibcon#read 5, iclass 10, count 0 2006.257.14:49:34.23#ibcon#about to read 6, iclass 10, count 0 2006.257.14:49:34.23#ibcon#read 6, iclass 10, count 0 2006.257.14:49:34.23#ibcon#end of sib2, iclass 10, count 0 2006.257.14:49:34.23#ibcon#*after write, iclass 10, count 0 2006.257.14:49:34.23#ibcon#*before return 0, iclass 10, count 0 2006.257.14:49:34.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:34.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:34.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:49:34.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:49:34.23$vck44/va=7,4 2006.257.14:49:34.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.14:49:34.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.14:49:34.23#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:34.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:34.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:34.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:34.29#ibcon#enter wrdev, iclass 12, count 2 2006.257.14:49:34.29#ibcon#first serial, iclass 12, count 2 2006.257.14:49:34.29#ibcon#enter sib2, iclass 12, count 2 2006.257.14:49:34.29#ibcon#flushed, iclass 12, count 2 2006.257.14:49:34.29#ibcon#about to write, iclass 12, count 2 2006.257.14:49:34.29#ibcon#wrote, iclass 12, count 2 2006.257.14:49:34.29#ibcon#about to read 3, iclass 12, count 2 2006.257.14:49:34.31#ibcon#read 3, iclass 12, count 2 2006.257.14:49:34.31#ibcon#about to read 4, iclass 12, count 2 2006.257.14:49:34.31#ibcon#read 4, iclass 12, count 2 2006.257.14:49:34.31#ibcon#about to read 5, iclass 12, count 2 2006.257.14:49:34.31#ibcon#read 5, iclass 12, count 2 2006.257.14:49:34.31#ibcon#about to read 6, iclass 12, count 2 2006.257.14:49:34.31#ibcon#read 6, iclass 12, count 2 2006.257.14:49:34.31#ibcon#end of sib2, iclass 12, count 2 2006.257.14:49:34.31#ibcon#*mode == 0, iclass 12, count 2 2006.257.14:49:34.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.14:49:34.31#ibcon#[25=AT07-04\r\n] 2006.257.14:49:34.31#ibcon#*before write, iclass 12, count 2 2006.257.14:49:34.31#ibcon#enter sib2, iclass 12, count 2 2006.257.14:49:34.31#ibcon#flushed, iclass 12, count 2 2006.257.14:49:34.31#ibcon#about to write, iclass 12, count 2 2006.257.14:49:34.31#ibcon#wrote, iclass 12, count 2 2006.257.14:49:34.31#ibcon#about to read 3, iclass 12, count 2 2006.257.14:49:34.34#ibcon#read 3, iclass 12, count 2 2006.257.14:49:34.34#ibcon#about to read 4, iclass 12, count 2 2006.257.14:49:34.34#ibcon#read 4, iclass 12, count 2 2006.257.14:49:34.34#ibcon#about to read 5, iclass 12, count 2 2006.257.14:49:34.34#ibcon#read 5, iclass 12, count 2 2006.257.14:49:34.34#ibcon#about to read 6, iclass 12, count 2 2006.257.14:49:34.34#ibcon#read 6, iclass 12, count 2 2006.257.14:49:34.34#ibcon#end of sib2, iclass 12, count 2 2006.257.14:49:34.34#ibcon#*after write, iclass 12, count 2 2006.257.14:49:34.34#ibcon#*before return 0, iclass 12, count 2 2006.257.14:49:34.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:34.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:34.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.14:49:34.34#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:34.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:34.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:34.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:34.46#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:49:34.46#ibcon#first serial, iclass 12, count 0 2006.257.14:49:34.46#ibcon#enter sib2, iclass 12, count 0 2006.257.14:49:34.46#ibcon#flushed, iclass 12, count 0 2006.257.14:49:34.46#ibcon#about to write, iclass 12, count 0 2006.257.14:49:34.46#ibcon#wrote, iclass 12, count 0 2006.257.14:49:34.46#ibcon#about to read 3, iclass 12, count 0 2006.257.14:49:34.48#ibcon#read 3, iclass 12, count 0 2006.257.14:49:34.48#ibcon#about to read 4, iclass 12, count 0 2006.257.14:49:34.48#ibcon#read 4, iclass 12, count 0 2006.257.14:49:34.48#ibcon#about to read 5, iclass 12, count 0 2006.257.14:49:34.48#ibcon#read 5, iclass 12, count 0 2006.257.14:49:34.48#ibcon#about to read 6, iclass 12, count 0 2006.257.14:49:34.48#ibcon#read 6, iclass 12, count 0 2006.257.14:49:34.48#ibcon#end of sib2, iclass 12, count 0 2006.257.14:49:34.48#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:49:34.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:49:34.48#ibcon#[25=USB\r\n] 2006.257.14:49:34.48#ibcon#*before write, iclass 12, count 0 2006.257.14:49:34.48#ibcon#enter sib2, iclass 12, count 0 2006.257.14:49:34.48#ibcon#flushed, iclass 12, count 0 2006.257.14:49:34.48#ibcon#about to write, iclass 12, count 0 2006.257.14:49:34.48#ibcon#wrote, iclass 12, count 0 2006.257.14:49:34.48#ibcon#about to read 3, iclass 12, count 0 2006.257.14:49:34.51#ibcon#read 3, iclass 12, count 0 2006.257.14:49:34.51#ibcon#about to read 4, iclass 12, count 0 2006.257.14:49:34.51#ibcon#read 4, iclass 12, count 0 2006.257.14:49:34.51#ibcon#about to read 5, iclass 12, count 0 2006.257.14:49:34.51#ibcon#read 5, iclass 12, count 0 2006.257.14:49:34.51#ibcon#about to read 6, iclass 12, count 0 2006.257.14:49:34.51#ibcon#read 6, iclass 12, count 0 2006.257.14:49:34.51#ibcon#end of sib2, iclass 12, count 0 2006.257.14:49:34.51#ibcon#*after write, iclass 12, count 0 2006.257.14:49:34.51#ibcon#*before return 0, iclass 12, count 0 2006.257.14:49:34.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:34.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:34.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:49:34.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:49:34.51$vck44/valo=8,884.99 2006.257.14:49:34.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.14:49:34.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.14:49:34.51#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:34.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:34.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:34.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:34.51#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:49:34.51#ibcon#first serial, iclass 14, count 0 2006.257.14:49:34.51#ibcon#enter sib2, iclass 14, count 0 2006.257.14:49:34.51#ibcon#flushed, iclass 14, count 0 2006.257.14:49:34.51#ibcon#about to write, iclass 14, count 0 2006.257.14:49:34.51#ibcon#wrote, iclass 14, count 0 2006.257.14:49:34.51#ibcon#about to read 3, iclass 14, count 0 2006.257.14:49:34.53#ibcon#read 3, iclass 14, count 0 2006.257.14:49:34.53#ibcon#about to read 4, iclass 14, count 0 2006.257.14:49:34.53#ibcon#read 4, iclass 14, count 0 2006.257.14:49:34.53#ibcon#about to read 5, iclass 14, count 0 2006.257.14:49:34.53#ibcon#read 5, iclass 14, count 0 2006.257.14:49:34.53#ibcon#about to read 6, iclass 14, count 0 2006.257.14:49:34.53#ibcon#read 6, iclass 14, count 0 2006.257.14:49:34.53#ibcon#end of sib2, iclass 14, count 0 2006.257.14:49:34.53#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:49:34.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:49:34.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:49:34.53#ibcon#*before write, iclass 14, count 0 2006.257.14:49:34.53#ibcon#enter sib2, iclass 14, count 0 2006.257.14:49:34.53#ibcon#flushed, iclass 14, count 0 2006.257.14:49:34.53#ibcon#about to write, iclass 14, count 0 2006.257.14:49:34.53#ibcon#wrote, iclass 14, count 0 2006.257.14:49:34.53#ibcon#about to read 3, iclass 14, count 0 2006.257.14:49:34.57#ibcon#read 3, iclass 14, count 0 2006.257.14:49:34.57#ibcon#about to read 4, iclass 14, count 0 2006.257.14:49:34.57#ibcon#read 4, iclass 14, count 0 2006.257.14:49:34.57#ibcon#about to read 5, iclass 14, count 0 2006.257.14:49:34.57#ibcon#read 5, iclass 14, count 0 2006.257.14:49:34.57#ibcon#about to read 6, iclass 14, count 0 2006.257.14:49:34.57#ibcon#read 6, iclass 14, count 0 2006.257.14:49:34.57#ibcon#end of sib2, iclass 14, count 0 2006.257.14:49:34.57#ibcon#*after write, iclass 14, count 0 2006.257.14:49:34.57#ibcon#*before return 0, iclass 14, count 0 2006.257.14:49:34.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:34.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:34.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:49:34.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:49:34.57$vck44/va=8,4 2006.257.14:49:34.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.14:49:34.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.14:49:34.57#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:34.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:49:34.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:49:34.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:49:34.63#ibcon#enter wrdev, iclass 16, count 2 2006.257.14:49:34.63#ibcon#first serial, iclass 16, count 2 2006.257.14:49:34.63#ibcon#enter sib2, iclass 16, count 2 2006.257.14:49:34.63#ibcon#flushed, iclass 16, count 2 2006.257.14:49:34.63#ibcon#about to write, iclass 16, count 2 2006.257.14:49:34.63#ibcon#wrote, iclass 16, count 2 2006.257.14:49:34.63#ibcon#about to read 3, iclass 16, count 2 2006.257.14:49:34.65#ibcon#read 3, iclass 16, count 2 2006.257.14:49:34.65#ibcon#about to read 4, iclass 16, count 2 2006.257.14:49:34.65#ibcon#read 4, iclass 16, count 2 2006.257.14:49:34.65#ibcon#about to read 5, iclass 16, count 2 2006.257.14:49:34.65#ibcon#read 5, iclass 16, count 2 2006.257.14:49:34.65#ibcon#about to read 6, iclass 16, count 2 2006.257.14:49:34.65#ibcon#read 6, iclass 16, count 2 2006.257.14:49:34.65#ibcon#end of sib2, iclass 16, count 2 2006.257.14:49:34.65#ibcon#*mode == 0, iclass 16, count 2 2006.257.14:49:34.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.14:49:34.65#ibcon#[25=AT08-04\r\n] 2006.257.14:49:34.65#ibcon#*before write, iclass 16, count 2 2006.257.14:49:34.65#ibcon#enter sib2, iclass 16, count 2 2006.257.14:49:34.65#ibcon#flushed, iclass 16, count 2 2006.257.14:49:34.65#ibcon#about to write, iclass 16, count 2 2006.257.14:49:34.65#ibcon#wrote, iclass 16, count 2 2006.257.14:49:34.65#ibcon#about to read 3, iclass 16, count 2 2006.257.14:49:34.68#ibcon#read 3, iclass 16, count 2 2006.257.14:49:34.68#ibcon#about to read 4, iclass 16, count 2 2006.257.14:49:34.68#ibcon#read 4, iclass 16, count 2 2006.257.14:49:34.68#ibcon#about to read 5, iclass 16, count 2 2006.257.14:49:34.68#ibcon#read 5, iclass 16, count 2 2006.257.14:49:34.68#ibcon#about to read 6, iclass 16, count 2 2006.257.14:49:34.68#ibcon#read 6, iclass 16, count 2 2006.257.14:49:34.68#ibcon#end of sib2, iclass 16, count 2 2006.257.14:49:34.68#ibcon#*after write, iclass 16, count 2 2006.257.14:49:34.68#ibcon#*before return 0, iclass 16, count 2 2006.257.14:49:34.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:49:34.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.14:49:34.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.14:49:34.68#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:34.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:49:34.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:49:34.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:49:34.80#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:49:34.80#ibcon#first serial, iclass 16, count 0 2006.257.14:49:34.80#ibcon#enter sib2, iclass 16, count 0 2006.257.14:49:34.80#ibcon#flushed, iclass 16, count 0 2006.257.14:49:34.80#ibcon#about to write, iclass 16, count 0 2006.257.14:49:34.80#ibcon#wrote, iclass 16, count 0 2006.257.14:49:34.80#ibcon#about to read 3, iclass 16, count 0 2006.257.14:49:34.82#ibcon#read 3, iclass 16, count 0 2006.257.14:49:34.82#ibcon#about to read 4, iclass 16, count 0 2006.257.14:49:34.82#ibcon#read 4, iclass 16, count 0 2006.257.14:49:34.82#ibcon#about to read 5, iclass 16, count 0 2006.257.14:49:34.82#ibcon#read 5, iclass 16, count 0 2006.257.14:49:34.82#ibcon#about to read 6, iclass 16, count 0 2006.257.14:49:34.82#ibcon#read 6, iclass 16, count 0 2006.257.14:49:34.82#ibcon#end of sib2, iclass 16, count 0 2006.257.14:49:34.82#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:49:34.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:49:34.82#ibcon#[25=USB\r\n] 2006.257.14:49:34.82#ibcon#*before write, iclass 16, count 0 2006.257.14:49:34.82#ibcon#enter sib2, iclass 16, count 0 2006.257.14:49:34.82#ibcon#flushed, iclass 16, count 0 2006.257.14:49:34.82#ibcon#about to write, iclass 16, count 0 2006.257.14:49:34.82#ibcon#wrote, iclass 16, count 0 2006.257.14:49:34.82#ibcon#about to read 3, iclass 16, count 0 2006.257.14:49:34.85#ibcon#read 3, iclass 16, count 0 2006.257.14:49:34.85#ibcon#about to read 4, iclass 16, count 0 2006.257.14:49:34.85#ibcon#read 4, iclass 16, count 0 2006.257.14:49:34.85#ibcon#about to read 5, iclass 16, count 0 2006.257.14:49:34.85#ibcon#read 5, iclass 16, count 0 2006.257.14:49:34.85#ibcon#about to read 6, iclass 16, count 0 2006.257.14:49:34.85#ibcon#read 6, iclass 16, count 0 2006.257.14:49:34.85#ibcon#end of sib2, iclass 16, count 0 2006.257.14:49:34.85#ibcon#*after write, iclass 16, count 0 2006.257.14:49:34.85#ibcon#*before return 0, iclass 16, count 0 2006.257.14:49:34.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:49:34.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.14:49:34.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:49:34.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:49:34.85$vck44/vblo=1,629.99 2006.257.14:49:34.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.14:49:34.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.14:49:34.85#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:34.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:34.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:34.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:34.85#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:49:34.85#ibcon#first serial, iclass 18, count 0 2006.257.14:49:34.85#ibcon#enter sib2, iclass 18, count 0 2006.257.14:49:34.85#ibcon#flushed, iclass 18, count 0 2006.257.14:49:34.85#ibcon#about to write, iclass 18, count 0 2006.257.14:49:34.85#ibcon#wrote, iclass 18, count 0 2006.257.14:49:34.85#ibcon#about to read 3, iclass 18, count 0 2006.257.14:49:34.87#ibcon#read 3, iclass 18, count 0 2006.257.14:49:34.87#ibcon#about to read 4, iclass 18, count 0 2006.257.14:49:34.87#ibcon#read 4, iclass 18, count 0 2006.257.14:49:34.87#ibcon#about to read 5, iclass 18, count 0 2006.257.14:49:34.87#ibcon#read 5, iclass 18, count 0 2006.257.14:49:34.87#ibcon#about to read 6, iclass 18, count 0 2006.257.14:49:34.87#ibcon#read 6, iclass 18, count 0 2006.257.14:49:34.87#ibcon#end of sib2, iclass 18, count 0 2006.257.14:49:34.87#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:49:34.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:49:34.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:49:34.87#ibcon#*before write, iclass 18, count 0 2006.257.14:49:34.87#ibcon#enter sib2, iclass 18, count 0 2006.257.14:49:34.87#ibcon#flushed, iclass 18, count 0 2006.257.14:49:34.87#ibcon#about to write, iclass 18, count 0 2006.257.14:49:34.87#ibcon#wrote, iclass 18, count 0 2006.257.14:49:34.87#ibcon#about to read 3, iclass 18, count 0 2006.257.14:49:34.91#ibcon#read 3, iclass 18, count 0 2006.257.14:49:34.91#ibcon#about to read 4, iclass 18, count 0 2006.257.14:49:34.91#ibcon#read 4, iclass 18, count 0 2006.257.14:49:34.91#ibcon#about to read 5, iclass 18, count 0 2006.257.14:49:34.91#ibcon#read 5, iclass 18, count 0 2006.257.14:49:34.91#ibcon#about to read 6, iclass 18, count 0 2006.257.14:49:34.91#ibcon#read 6, iclass 18, count 0 2006.257.14:49:34.91#ibcon#end of sib2, iclass 18, count 0 2006.257.14:49:34.91#ibcon#*after write, iclass 18, count 0 2006.257.14:49:34.91#ibcon#*before return 0, iclass 18, count 0 2006.257.14:49:34.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:34.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.14:49:34.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:49:34.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:49:34.91$vck44/vb=1,4 2006.257.14:49:34.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.14:49:34.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.14:49:34.91#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:34.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:34.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:34.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:34.91#ibcon#enter wrdev, iclass 20, count 2 2006.257.14:49:34.91#ibcon#first serial, iclass 20, count 2 2006.257.14:49:34.91#ibcon#enter sib2, iclass 20, count 2 2006.257.14:49:34.91#ibcon#flushed, iclass 20, count 2 2006.257.14:49:34.91#ibcon#about to write, iclass 20, count 2 2006.257.14:49:34.91#ibcon#wrote, iclass 20, count 2 2006.257.14:49:34.91#ibcon#about to read 3, iclass 20, count 2 2006.257.14:49:34.93#ibcon#read 3, iclass 20, count 2 2006.257.14:49:34.93#ibcon#about to read 4, iclass 20, count 2 2006.257.14:49:34.93#ibcon#read 4, iclass 20, count 2 2006.257.14:49:34.93#ibcon#about to read 5, iclass 20, count 2 2006.257.14:49:34.93#ibcon#read 5, iclass 20, count 2 2006.257.14:49:34.93#ibcon#about to read 6, iclass 20, count 2 2006.257.14:49:34.93#ibcon#read 6, iclass 20, count 2 2006.257.14:49:34.93#ibcon#end of sib2, iclass 20, count 2 2006.257.14:49:34.93#ibcon#*mode == 0, iclass 20, count 2 2006.257.14:49:34.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.14:49:34.93#ibcon#[27=AT01-04\r\n] 2006.257.14:49:34.93#ibcon#*before write, iclass 20, count 2 2006.257.14:49:34.93#ibcon#enter sib2, iclass 20, count 2 2006.257.14:49:34.93#ibcon#flushed, iclass 20, count 2 2006.257.14:49:34.93#ibcon#about to write, iclass 20, count 2 2006.257.14:49:34.93#ibcon#wrote, iclass 20, count 2 2006.257.14:49:34.93#ibcon#about to read 3, iclass 20, count 2 2006.257.14:49:34.96#ibcon#read 3, iclass 20, count 2 2006.257.14:49:34.96#ibcon#about to read 4, iclass 20, count 2 2006.257.14:49:34.96#ibcon#read 4, iclass 20, count 2 2006.257.14:49:34.96#ibcon#about to read 5, iclass 20, count 2 2006.257.14:49:34.96#ibcon#read 5, iclass 20, count 2 2006.257.14:49:34.96#ibcon#about to read 6, iclass 20, count 2 2006.257.14:49:34.96#ibcon#read 6, iclass 20, count 2 2006.257.14:49:34.96#ibcon#end of sib2, iclass 20, count 2 2006.257.14:49:34.96#ibcon#*after write, iclass 20, count 2 2006.257.14:49:34.96#ibcon#*before return 0, iclass 20, count 2 2006.257.14:49:34.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:34.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.14:49:34.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.14:49:34.96#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:34.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:35.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:35.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:35.08#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:49:35.08#ibcon#first serial, iclass 20, count 0 2006.257.14:49:35.08#ibcon#enter sib2, iclass 20, count 0 2006.257.14:49:35.08#ibcon#flushed, iclass 20, count 0 2006.257.14:49:35.08#ibcon#about to write, iclass 20, count 0 2006.257.14:49:35.08#ibcon#wrote, iclass 20, count 0 2006.257.14:49:35.08#ibcon#about to read 3, iclass 20, count 0 2006.257.14:49:35.10#ibcon#read 3, iclass 20, count 0 2006.257.14:49:35.10#ibcon#about to read 4, iclass 20, count 0 2006.257.14:49:35.10#ibcon#read 4, iclass 20, count 0 2006.257.14:49:35.10#ibcon#about to read 5, iclass 20, count 0 2006.257.14:49:35.10#ibcon#read 5, iclass 20, count 0 2006.257.14:49:35.10#ibcon#about to read 6, iclass 20, count 0 2006.257.14:49:35.10#ibcon#read 6, iclass 20, count 0 2006.257.14:49:35.10#ibcon#end of sib2, iclass 20, count 0 2006.257.14:49:35.10#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:49:35.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:49:35.10#ibcon#[27=USB\r\n] 2006.257.14:49:35.10#ibcon#*before write, iclass 20, count 0 2006.257.14:49:35.10#ibcon#enter sib2, iclass 20, count 0 2006.257.14:49:35.10#ibcon#flushed, iclass 20, count 0 2006.257.14:49:35.10#ibcon#about to write, iclass 20, count 0 2006.257.14:49:35.10#ibcon#wrote, iclass 20, count 0 2006.257.14:49:35.10#ibcon#about to read 3, iclass 20, count 0 2006.257.14:49:35.13#ibcon#read 3, iclass 20, count 0 2006.257.14:49:35.13#ibcon#about to read 4, iclass 20, count 0 2006.257.14:49:35.13#ibcon#read 4, iclass 20, count 0 2006.257.14:49:35.13#ibcon#about to read 5, iclass 20, count 0 2006.257.14:49:35.13#ibcon#read 5, iclass 20, count 0 2006.257.14:49:35.13#ibcon#about to read 6, iclass 20, count 0 2006.257.14:49:35.13#ibcon#read 6, iclass 20, count 0 2006.257.14:49:35.13#ibcon#end of sib2, iclass 20, count 0 2006.257.14:49:35.13#ibcon#*after write, iclass 20, count 0 2006.257.14:49:35.13#ibcon#*before return 0, iclass 20, count 0 2006.257.14:49:35.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:35.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.14:49:35.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:49:35.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:49:35.13$vck44/vblo=2,634.99 2006.257.14:49:35.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.14:49:35.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.14:49:35.13#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:35.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:35.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:35.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:35.13#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:49:35.13#ibcon#first serial, iclass 22, count 0 2006.257.14:49:35.13#ibcon#enter sib2, iclass 22, count 0 2006.257.14:49:35.13#ibcon#flushed, iclass 22, count 0 2006.257.14:49:35.13#ibcon#about to write, iclass 22, count 0 2006.257.14:49:35.13#ibcon#wrote, iclass 22, count 0 2006.257.14:49:35.13#ibcon#about to read 3, iclass 22, count 0 2006.257.14:49:35.15#ibcon#read 3, iclass 22, count 0 2006.257.14:49:35.15#ibcon#about to read 4, iclass 22, count 0 2006.257.14:49:35.15#ibcon#read 4, iclass 22, count 0 2006.257.14:49:35.15#ibcon#about to read 5, iclass 22, count 0 2006.257.14:49:35.15#ibcon#read 5, iclass 22, count 0 2006.257.14:49:35.15#ibcon#about to read 6, iclass 22, count 0 2006.257.14:49:35.15#ibcon#read 6, iclass 22, count 0 2006.257.14:49:35.15#ibcon#end of sib2, iclass 22, count 0 2006.257.14:49:35.15#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:49:35.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:49:35.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:49:35.15#ibcon#*before write, iclass 22, count 0 2006.257.14:49:35.15#ibcon#enter sib2, iclass 22, count 0 2006.257.14:49:35.15#ibcon#flushed, iclass 22, count 0 2006.257.14:49:35.15#ibcon#about to write, iclass 22, count 0 2006.257.14:49:35.15#ibcon#wrote, iclass 22, count 0 2006.257.14:49:35.15#ibcon#about to read 3, iclass 22, count 0 2006.257.14:49:35.19#ibcon#read 3, iclass 22, count 0 2006.257.14:49:35.19#ibcon#about to read 4, iclass 22, count 0 2006.257.14:49:35.19#ibcon#read 4, iclass 22, count 0 2006.257.14:49:35.19#ibcon#about to read 5, iclass 22, count 0 2006.257.14:49:35.19#ibcon#read 5, iclass 22, count 0 2006.257.14:49:35.19#ibcon#about to read 6, iclass 22, count 0 2006.257.14:49:35.19#ibcon#read 6, iclass 22, count 0 2006.257.14:49:35.19#ibcon#end of sib2, iclass 22, count 0 2006.257.14:49:35.19#ibcon#*after write, iclass 22, count 0 2006.257.14:49:35.19#ibcon#*before return 0, iclass 22, count 0 2006.257.14:49:35.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:35.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.14:49:35.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:49:35.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:49:35.19$vck44/vb=2,5 2006.257.14:49:35.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.14:49:35.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.14:49:35.19#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:35.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:35.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:35.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:35.25#ibcon#enter wrdev, iclass 24, count 2 2006.257.14:49:35.25#ibcon#first serial, iclass 24, count 2 2006.257.14:49:35.25#ibcon#enter sib2, iclass 24, count 2 2006.257.14:49:35.25#ibcon#flushed, iclass 24, count 2 2006.257.14:49:35.25#ibcon#about to write, iclass 24, count 2 2006.257.14:49:35.25#ibcon#wrote, iclass 24, count 2 2006.257.14:49:35.25#ibcon#about to read 3, iclass 24, count 2 2006.257.14:49:35.27#ibcon#read 3, iclass 24, count 2 2006.257.14:49:35.27#ibcon#about to read 4, iclass 24, count 2 2006.257.14:49:35.27#ibcon#read 4, iclass 24, count 2 2006.257.14:49:35.27#ibcon#about to read 5, iclass 24, count 2 2006.257.14:49:35.27#ibcon#read 5, iclass 24, count 2 2006.257.14:49:35.27#ibcon#about to read 6, iclass 24, count 2 2006.257.14:49:35.27#ibcon#read 6, iclass 24, count 2 2006.257.14:49:35.27#ibcon#end of sib2, iclass 24, count 2 2006.257.14:49:35.27#ibcon#*mode == 0, iclass 24, count 2 2006.257.14:49:35.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.14:49:35.27#ibcon#[27=AT02-05\r\n] 2006.257.14:49:35.27#ibcon#*before write, iclass 24, count 2 2006.257.14:49:35.27#ibcon#enter sib2, iclass 24, count 2 2006.257.14:49:35.27#ibcon#flushed, iclass 24, count 2 2006.257.14:49:35.27#ibcon#about to write, iclass 24, count 2 2006.257.14:49:35.27#ibcon#wrote, iclass 24, count 2 2006.257.14:49:35.27#ibcon#about to read 3, iclass 24, count 2 2006.257.14:49:35.30#ibcon#read 3, iclass 24, count 2 2006.257.14:49:35.34#ibcon#about to read 4, iclass 24, count 2 2006.257.14:49:35.34#ibcon#read 4, iclass 24, count 2 2006.257.14:49:35.34#ibcon#about to read 5, iclass 24, count 2 2006.257.14:49:35.34#ibcon#read 5, iclass 24, count 2 2006.257.14:49:35.34#ibcon#about to read 6, iclass 24, count 2 2006.257.14:49:35.34#ibcon#read 6, iclass 24, count 2 2006.257.14:49:35.34#ibcon#end of sib2, iclass 24, count 2 2006.257.14:49:35.34#ibcon#*after write, iclass 24, count 2 2006.257.14:49:35.34#ibcon#*before return 0, iclass 24, count 2 2006.257.14:49:35.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:35.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.14:49:35.35#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.14:49:35.35#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:35.35#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:35.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:35.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:35.46#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:49:35.46#ibcon#first serial, iclass 24, count 0 2006.257.14:49:35.46#ibcon#enter sib2, iclass 24, count 0 2006.257.14:49:35.46#ibcon#flushed, iclass 24, count 0 2006.257.14:49:35.46#ibcon#about to write, iclass 24, count 0 2006.257.14:49:35.46#ibcon#wrote, iclass 24, count 0 2006.257.14:49:35.46#ibcon#about to read 3, iclass 24, count 0 2006.257.14:49:35.48#ibcon#read 3, iclass 24, count 0 2006.257.14:49:35.48#ibcon#about to read 4, iclass 24, count 0 2006.257.14:49:35.48#ibcon#read 4, iclass 24, count 0 2006.257.14:49:35.48#ibcon#about to read 5, iclass 24, count 0 2006.257.14:49:35.48#ibcon#read 5, iclass 24, count 0 2006.257.14:49:35.48#ibcon#about to read 6, iclass 24, count 0 2006.257.14:49:35.48#ibcon#read 6, iclass 24, count 0 2006.257.14:49:35.48#ibcon#end of sib2, iclass 24, count 0 2006.257.14:49:35.48#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:49:35.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:49:35.48#ibcon#[27=USB\r\n] 2006.257.14:49:35.48#ibcon#*before write, iclass 24, count 0 2006.257.14:49:35.48#ibcon#enter sib2, iclass 24, count 0 2006.257.14:49:35.48#ibcon#flushed, iclass 24, count 0 2006.257.14:49:35.48#ibcon#about to write, iclass 24, count 0 2006.257.14:49:35.48#ibcon#wrote, iclass 24, count 0 2006.257.14:49:35.48#ibcon#about to read 3, iclass 24, count 0 2006.257.14:49:35.51#ibcon#read 3, iclass 24, count 0 2006.257.14:49:35.51#ibcon#about to read 4, iclass 24, count 0 2006.257.14:49:35.51#ibcon#read 4, iclass 24, count 0 2006.257.14:49:35.51#ibcon#about to read 5, iclass 24, count 0 2006.257.14:49:35.51#ibcon#read 5, iclass 24, count 0 2006.257.14:49:35.51#ibcon#about to read 6, iclass 24, count 0 2006.257.14:49:35.51#ibcon#read 6, iclass 24, count 0 2006.257.14:49:35.51#ibcon#end of sib2, iclass 24, count 0 2006.257.14:49:35.51#ibcon#*after write, iclass 24, count 0 2006.257.14:49:35.51#ibcon#*before return 0, iclass 24, count 0 2006.257.14:49:35.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:35.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.14:49:35.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:49:35.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:49:35.51$vck44/vblo=3,649.99 2006.257.14:49:35.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.14:49:35.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.14:49:35.51#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:35.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:35.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:35.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:35.51#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:49:35.51#ibcon#first serial, iclass 26, count 0 2006.257.14:49:35.51#ibcon#enter sib2, iclass 26, count 0 2006.257.14:49:35.51#ibcon#flushed, iclass 26, count 0 2006.257.14:49:35.51#ibcon#about to write, iclass 26, count 0 2006.257.14:49:35.51#ibcon#wrote, iclass 26, count 0 2006.257.14:49:35.51#ibcon#about to read 3, iclass 26, count 0 2006.257.14:49:35.53#ibcon#read 3, iclass 26, count 0 2006.257.14:49:35.53#ibcon#about to read 4, iclass 26, count 0 2006.257.14:49:35.53#ibcon#read 4, iclass 26, count 0 2006.257.14:49:35.53#ibcon#about to read 5, iclass 26, count 0 2006.257.14:49:35.53#ibcon#read 5, iclass 26, count 0 2006.257.14:49:35.53#ibcon#about to read 6, iclass 26, count 0 2006.257.14:49:35.53#ibcon#read 6, iclass 26, count 0 2006.257.14:49:35.53#ibcon#end of sib2, iclass 26, count 0 2006.257.14:49:35.53#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:49:35.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:49:35.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:49:35.53#ibcon#*before write, iclass 26, count 0 2006.257.14:49:35.53#ibcon#enter sib2, iclass 26, count 0 2006.257.14:49:35.53#ibcon#flushed, iclass 26, count 0 2006.257.14:49:35.53#ibcon#about to write, iclass 26, count 0 2006.257.14:49:35.53#ibcon#wrote, iclass 26, count 0 2006.257.14:49:35.53#ibcon#about to read 3, iclass 26, count 0 2006.257.14:49:35.57#ibcon#read 3, iclass 26, count 0 2006.257.14:49:35.57#ibcon#about to read 4, iclass 26, count 0 2006.257.14:49:35.57#ibcon#read 4, iclass 26, count 0 2006.257.14:49:35.57#ibcon#about to read 5, iclass 26, count 0 2006.257.14:49:35.57#ibcon#read 5, iclass 26, count 0 2006.257.14:49:35.57#ibcon#about to read 6, iclass 26, count 0 2006.257.14:49:35.57#ibcon#read 6, iclass 26, count 0 2006.257.14:49:35.57#ibcon#end of sib2, iclass 26, count 0 2006.257.14:49:35.57#ibcon#*after write, iclass 26, count 0 2006.257.14:49:35.57#ibcon#*before return 0, iclass 26, count 0 2006.257.14:49:35.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:35.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:49:35.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:49:35.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:49:35.57$vck44/vb=3,4 2006.257.14:49:35.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.14:49:35.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.14:49:35.57#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:35.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:35.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:35.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:35.63#ibcon#enter wrdev, iclass 28, count 2 2006.257.14:49:35.63#ibcon#first serial, iclass 28, count 2 2006.257.14:49:35.63#ibcon#enter sib2, iclass 28, count 2 2006.257.14:49:35.63#ibcon#flushed, iclass 28, count 2 2006.257.14:49:35.63#ibcon#about to write, iclass 28, count 2 2006.257.14:49:35.63#ibcon#wrote, iclass 28, count 2 2006.257.14:49:35.63#ibcon#about to read 3, iclass 28, count 2 2006.257.14:49:35.65#ibcon#read 3, iclass 28, count 2 2006.257.14:49:35.65#ibcon#about to read 4, iclass 28, count 2 2006.257.14:49:35.65#ibcon#read 4, iclass 28, count 2 2006.257.14:49:35.65#ibcon#about to read 5, iclass 28, count 2 2006.257.14:49:35.65#ibcon#read 5, iclass 28, count 2 2006.257.14:49:35.65#ibcon#about to read 6, iclass 28, count 2 2006.257.14:49:35.65#ibcon#read 6, iclass 28, count 2 2006.257.14:49:35.65#ibcon#end of sib2, iclass 28, count 2 2006.257.14:49:35.65#ibcon#*mode == 0, iclass 28, count 2 2006.257.14:49:35.65#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.14:49:35.65#ibcon#[27=AT03-04\r\n] 2006.257.14:49:35.65#ibcon#*before write, iclass 28, count 2 2006.257.14:49:35.65#ibcon#enter sib2, iclass 28, count 2 2006.257.14:49:35.65#ibcon#flushed, iclass 28, count 2 2006.257.14:49:35.65#ibcon#about to write, iclass 28, count 2 2006.257.14:49:35.65#ibcon#wrote, iclass 28, count 2 2006.257.14:49:35.65#ibcon#about to read 3, iclass 28, count 2 2006.257.14:49:35.68#ibcon#read 3, iclass 28, count 2 2006.257.14:49:35.68#ibcon#about to read 4, iclass 28, count 2 2006.257.14:49:35.68#ibcon#read 4, iclass 28, count 2 2006.257.14:49:35.68#ibcon#about to read 5, iclass 28, count 2 2006.257.14:49:35.68#ibcon#read 5, iclass 28, count 2 2006.257.14:49:35.68#ibcon#about to read 6, iclass 28, count 2 2006.257.14:49:35.68#ibcon#read 6, iclass 28, count 2 2006.257.14:49:35.68#ibcon#end of sib2, iclass 28, count 2 2006.257.14:49:35.68#ibcon#*after write, iclass 28, count 2 2006.257.14:49:35.68#ibcon#*before return 0, iclass 28, count 2 2006.257.14:49:35.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:35.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.14:49:35.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.14:49:35.68#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:35.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:35.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:35.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:35.80#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:49:35.80#ibcon#first serial, iclass 28, count 0 2006.257.14:49:35.80#ibcon#enter sib2, iclass 28, count 0 2006.257.14:49:35.80#ibcon#flushed, iclass 28, count 0 2006.257.14:49:35.80#ibcon#about to write, iclass 28, count 0 2006.257.14:49:35.80#ibcon#wrote, iclass 28, count 0 2006.257.14:49:35.80#ibcon#about to read 3, iclass 28, count 0 2006.257.14:49:35.82#ibcon#read 3, iclass 28, count 0 2006.257.14:49:35.82#ibcon#about to read 4, iclass 28, count 0 2006.257.14:49:35.82#ibcon#read 4, iclass 28, count 0 2006.257.14:49:35.82#ibcon#about to read 5, iclass 28, count 0 2006.257.14:49:35.82#ibcon#read 5, iclass 28, count 0 2006.257.14:49:35.82#ibcon#about to read 6, iclass 28, count 0 2006.257.14:49:35.82#ibcon#read 6, iclass 28, count 0 2006.257.14:49:35.82#ibcon#end of sib2, iclass 28, count 0 2006.257.14:49:35.82#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:49:35.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:49:35.82#ibcon#[27=USB\r\n] 2006.257.14:49:35.82#ibcon#*before write, iclass 28, count 0 2006.257.14:49:35.82#ibcon#enter sib2, iclass 28, count 0 2006.257.14:49:35.82#ibcon#flushed, iclass 28, count 0 2006.257.14:49:35.82#ibcon#about to write, iclass 28, count 0 2006.257.14:49:35.82#ibcon#wrote, iclass 28, count 0 2006.257.14:49:35.82#ibcon#about to read 3, iclass 28, count 0 2006.257.14:49:35.85#ibcon#read 3, iclass 28, count 0 2006.257.14:49:35.85#ibcon#about to read 4, iclass 28, count 0 2006.257.14:49:35.85#ibcon#read 4, iclass 28, count 0 2006.257.14:49:35.85#ibcon#about to read 5, iclass 28, count 0 2006.257.14:49:35.85#ibcon#read 5, iclass 28, count 0 2006.257.14:49:35.85#ibcon#about to read 6, iclass 28, count 0 2006.257.14:49:35.85#ibcon#read 6, iclass 28, count 0 2006.257.14:49:35.85#ibcon#end of sib2, iclass 28, count 0 2006.257.14:49:35.85#ibcon#*after write, iclass 28, count 0 2006.257.14:49:35.85#ibcon#*before return 0, iclass 28, count 0 2006.257.14:49:35.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:35.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.14:49:35.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:49:35.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:49:35.85$vck44/vblo=4,679.99 2006.257.14:49:35.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.14:49:35.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.14:49:35.85#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:35.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:35.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:35.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:35.85#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:49:35.85#ibcon#first serial, iclass 30, count 0 2006.257.14:49:35.85#ibcon#enter sib2, iclass 30, count 0 2006.257.14:49:35.85#ibcon#flushed, iclass 30, count 0 2006.257.14:49:35.85#ibcon#about to write, iclass 30, count 0 2006.257.14:49:35.85#ibcon#wrote, iclass 30, count 0 2006.257.14:49:35.85#ibcon#about to read 3, iclass 30, count 0 2006.257.14:49:35.87#ibcon#read 3, iclass 30, count 0 2006.257.14:49:35.87#ibcon#about to read 4, iclass 30, count 0 2006.257.14:49:35.87#ibcon#read 4, iclass 30, count 0 2006.257.14:49:35.87#ibcon#about to read 5, iclass 30, count 0 2006.257.14:49:35.87#ibcon#read 5, iclass 30, count 0 2006.257.14:49:35.87#ibcon#about to read 6, iclass 30, count 0 2006.257.14:49:35.87#ibcon#read 6, iclass 30, count 0 2006.257.14:49:35.87#ibcon#end of sib2, iclass 30, count 0 2006.257.14:49:35.87#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:49:35.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:49:35.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:49:35.87#ibcon#*before write, iclass 30, count 0 2006.257.14:49:35.87#ibcon#enter sib2, iclass 30, count 0 2006.257.14:49:35.87#ibcon#flushed, iclass 30, count 0 2006.257.14:49:35.87#ibcon#about to write, iclass 30, count 0 2006.257.14:49:35.87#ibcon#wrote, iclass 30, count 0 2006.257.14:49:35.87#ibcon#about to read 3, iclass 30, count 0 2006.257.14:49:35.91#ibcon#read 3, iclass 30, count 0 2006.257.14:49:35.91#ibcon#about to read 4, iclass 30, count 0 2006.257.14:49:35.91#ibcon#read 4, iclass 30, count 0 2006.257.14:49:35.91#ibcon#about to read 5, iclass 30, count 0 2006.257.14:49:35.91#ibcon#read 5, iclass 30, count 0 2006.257.14:49:35.91#ibcon#about to read 6, iclass 30, count 0 2006.257.14:49:35.91#ibcon#read 6, iclass 30, count 0 2006.257.14:49:35.91#ibcon#end of sib2, iclass 30, count 0 2006.257.14:49:35.91#ibcon#*after write, iclass 30, count 0 2006.257.14:49:35.91#ibcon#*before return 0, iclass 30, count 0 2006.257.14:49:35.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:35.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.14:49:35.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:49:35.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:49:35.91$vck44/vb=4,5 2006.257.14:49:35.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.14:49:35.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.14:49:35.91#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:35.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:35.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:35.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:35.97#ibcon#enter wrdev, iclass 32, count 2 2006.257.14:49:35.97#ibcon#first serial, iclass 32, count 2 2006.257.14:49:35.97#ibcon#enter sib2, iclass 32, count 2 2006.257.14:49:35.97#ibcon#flushed, iclass 32, count 2 2006.257.14:49:35.97#ibcon#about to write, iclass 32, count 2 2006.257.14:49:35.97#ibcon#wrote, iclass 32, count 2 2006.257.14:49:35.97#ibcon#about to read 3, iclass 32, count 2 2006.257.14:49:35.99#ibcon#read 3, iclass 32, count 2 2006.257.14:49:35.99#ibcon#about to read 4, iclass 32, count 2 2006.257.14:49:35.99#ibcon#read 4, iclass 32, count 2 2006.257.14:49:35.99#ibcon#about to read 5, iclass 32, count 2 2006.257.14:49:35.99#ibcon#read 5, iclass 32, count 2 2006.257.14:49:35.99#ibcon#about to read 6, iclass 32, count 2 2006.257.14:49:35.99#ibcon#read 6, iclass 32, count 2 2006.257.14:49:35.99#ibcon#end of sib2, iclass 32, count 2 2006.257.14:49:35.99#ibcon#*mode == 0, iclass 32, count 2 2006.257.14:49:35.99#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.14:49:35.99#ibcon#[27=AT04-05\r\n] 2006.257.14:49:35.99#ibcon#*before write, iclass 32, count 2 2006.257.14:49:35.99#ibcon#enter sib2, iclass 32, count 2 2006.257.14:49:35.99#ibcon#flushed, iclass 32, count 2 2006.257.14:49:35.99#ibcon#about to write, iclass 32, count 2 2006.257.14:49:35.99#ibcon#wrote, iclass 32, count 2 2006.257.14:49:35.99#ibcon#about to read 3, iclass 32, count 2 2006.257.14:49:36.02#ibcon#read 3, iclass 32, count 2 2006.257.14:49:36.02#ibcon#about to read 4, iclass 32, count 2 2006.257.14:49:36.02#ibcon#read 4, iclass 32, count 2 2006.257.14:49:36.02#ibcon#about to read 5, iclass 32, count 2 2006.257.14:49:36.02#ibcon#read 5, iclass 32, count 2 2006.257.14:49:36.02#ibcon#about to read 6, iclass 32, count 2 2006.257.14:49:36.02#ibcon#read 6, iclass 32, count 2 2006.257.14:49:36.02#ibcon#end of sib2, iclass 32, count 2 2006.257.14:49:36.02#ibcon#*after write, iclass 32, count 2 2006.257.14:49:36.02#ibcon#*before return 0, iclass 32, count 2 2006.257.14:49:36.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:36.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.14:49:36.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.14:49:36.02#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:36.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:36.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:36.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:36.14#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:49:36.14#ibcon#first serial, iclass 32, count 0 2006.257.14:49:36.14#ibcon#enter sib2, iclass 32, count 0 2006.257.14:49:36.14#ibcon#flushed, iclass 32, count 0 2006.257.14:49:36.14#ibcon#about to write, iclass 32, count 0 2006.257.14:49:36.14#ibcon#wrote, iclass 32, count 0 2006.257.14:49:36.14#ibcon#about to read 3, iclass 32, count 0 2006.257.14:49:36.16#ibcon#read 3, iclass 32, count 0 2006.257.14:49:36.16#ibcon#about to read 4, iclass 32, count 0 2006.257.14:49:36.16#ibcon#read 4, iclass 32, count 0 2006.257.14:49:36.16#ibcon#about to read 5, iclass 32, count 0 2006.257.14:49:36.16#ibcon#read 5, iclass 32, count 0 2006.257.14:49:36.16#ibcon#about to read 6, iclass 32, count 0 2006.257.14:49:36.16#ibcon#read 6, iclass 32, count 0 2006.257.14:49:36.16#ibcon#end of sib2, iclass 32, count 0 2006.257.14:49:36.16#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:49:36.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:49:36.16#ibcon#[27=USB\r\n] 2006.257.14:49:36.16#ibcon#*before write, iclass 32, count 0 2006.257.14:49:36.16#ibcon#enter sib2, iclass 32, count 0 2006.257.14:49:36.16#ibcon#flushed, iclass 32, count 0 2006.257.14:49:36.16#ibcon#about to write, iclass 32, count 0 2006.257.14:49:36.16#ibcon#wrote, iclass 32, count 0 2006.257.14:49:36.16#ibcon#about to read 3, iclass 32, count 0 2006.257.14:49:36.19#ibcon#read 3, iclass 32, count 0 2006.257.14:49:36.19#ibcon#about to read 4, iclass 32, count 0 2006.257.14:49:36.19#ibcon#read 4, iclass 32, count 0 2006.257.14:49:36.19#ibcon#about to read 5, iclass 32, count 0 2006.257.14:49:36.19#ibcon#read 5, iclass 32, count 0 2006.257.14:49:36.19#ibcon#about to read 6, iclass 32, count 0 2006.257.14:49:36.19#ibcon#read 6, iclass 32, count 0 2006.257.14:49:36.19#ibcon#end of sib2, iclass 32, count 0 2006.257.14:49:36.19#ibcon#*after write, iclass 32, count 0 2006.257.14:49:36.19#ibcon#*before return 0, iclass 32, count 0 2006.257.14:49:36.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:36.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.14:49:36.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:49:36.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:49:36.19$vck44/vblo=5,709.99 2006.257.14:49:36.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.14:49:36.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.14:49:36.19#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:36.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:36.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:36.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:36.19#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:49:36.19#ibcon#first serial, iclass 34, count 0 2006.257.14:49:36.19#ibcon#enter sib2, iclass 34, count 0 2006.257.14:49:36.19#ibcon#flushed, iclass 34, count 0 2006.257.14:49:36.19#ibcon#about to write, iclass 34, count 0 2006.257.14:49:36.19#ibcon#wrote, iclass 34, count 0 2006.257.14:49:36.19#ibcon#about to read 3, iclass 34, count 0 2006.257.14:49:36.21#ibcon#read 3, iclass 34, count 0 2006.257.14:49:36.21#ibcon#about to read 4, iclass 34, count 0 2006.257.14:49:36.21#ibcon#read 4, iclass 34, count 0 2006.257.14:49:36.21#ibcon#about to read 5, iclass 34, count 0 2006.257.14:49:36.21#ibcon#read 5, iclass 34, count 0 2006.257.14:49:36.21#ibcon#about to read 6, iclass 34, count 0 2006.257.14:49:36.21#ibcon#read 6, iclass 34, count 0 2006.257.14:49:36.21#ibcon#end of sib2, iclass 34, count 0 2006.257.14:49:36.21#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:49:36.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:49:36.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:49:36.21#ibcon#*before write, iclass 34, count 0 2006.257.14:49:36.21#ibcon#enter sib2, iclass 34, count 0 2006.257.14:49:36.21#ibcon#flushed, iclass 34, count 0 2006.257.14:49:36.21#ibcon#about to write, iclass 34, count 0 2006.257.14:49:36.21#ibcon#wrote, iclass 34, count 0 2006.257.14:49:36.21#ibcon#about to read 3, iclass 34, count 0 2006.257.14:49:36.25#ibcon#read 3, iclass 34, count 0 2006.257.14:49:36.25#ibcon#about to read 4, iclass 34, count 0 2006.257.14:49:36.25#ibcon#read 4, iclass 34, count 0 2006.257.14:49:36.25#ibcon#about to read 5, iclass 34, count 0 2006.257.14:49:36.25#ibcon#read 5, iclass 34, count 0 2006.257.14:49:36.25#ibcon#about to read 6, iclass 34, count 0 2006.257.14:49:36.25#ibcon#read 6, iclass 34, count 0 2006.257.14:49:36.25#ibcon#end of sib2, iclass 34, count 0 2006.257.14:49:36.25#ibcon#*after write, iclass 34, count 0 2006.257.14:49:36.25#ibcon#*before return 0, iclass 34, count 0 2006.257.14:49:36.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:36.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.14:49:36.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:49:36.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:49:36.25$vck44/vb=5,4 2006.257.14:49:36.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.14:49:36.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.14:49:36.25#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:36.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:36.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:36.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:36.31#ibcon#enter wrdev, iclass 36, count 2 2006.257.14:49:36.31#ibcon#first serial, iclass 36, count 2 2006.257.14:49:36.31#ibcon#enter sib2, iclass 36, count 2 2006.257.14:49:36.31#ibcon#flushed, iclass 36, count 2 2006.257.14:49:36.31#ibcon#about to write, iclass 36, count 2 2006.257.14:49:36.31#ibcon#wrote, iclass 36, count 2 2006.257.14:49:36.31#ibcon#about to read 3, iclass 36, count 2 2006.257.14:49:36.33#ibcon#read 3, iclass 36, count 2 2006.257.14:49:36.33#ibcon#about to read 4, iclass 36, count 2 2006.257.14:49:36.33#ibcon#read 4, iclass 36, count 2 2006.257.14:49:36.33#ibcon#about to read 5, iclass 36, count 2 2006.257.14:49:36.33#ibcon#read 5, iclass 36, count 2 2006.257.14:49:36.33#ibcon#about to read 6, iclass 36, count 2 2006.257.14:49:36.33#ibcon#read 6, iclass 36, count 2 2006.257.14:49:36.33#ibcon#end of sib2, iclass 36, count 2 2006.257.14:49:36.33#ibcon#*mode == 0, iclass 36, count 2 2006.257.14:49:36.33#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.14:49:36.33#ibcon#[27=AT05-04\r\n] 2006.257.14:49:36.33#ibcon#*before write, iclass 36, count 2 2006.257.14:49:36.33#ibcon#enter sib2, iclass 36, count 2 2006.257.14:49:36.33#ibcon#flushed, iclass 36, count 2 2006.257.14:49:36.33#ibcon#about to write, iclass 36, count 2 2006.257.14:49:36.33#ibcon#wrote, iclass 36, count 2 2006.257.14:49:36.33#ibcon#about to read 3, iclass 36, count 2 2006.257.14:49:36.36#ibcon#read 3, iclass 36, count 2 2006.257.14:49:36.36#ibcon#about to read 4, iclass 36, count 2 2006.257.14:49:36.36#ibcon#read 4, iclass 36, count 2 2006.257.14:49:36.36#ibcon#about to read 5, iclass 36, count 2 2006.257.14:49:36.36#ibcon#read 5, iclass 36, count 2 2006.257.14:49:36.36#ibcon#about to read 6, iclass 36, count 2 2006.257.14:49:36.36#ibcon#read 6, iclass 36, count 2 2006.257.14:49:36.36#ibcon#end of sib2, iclass 36, count 2 2006.257.14:49:36.36#ibcon#*after write, iclass 36, count 2 2006.257.14:49:36.41#ibcon#*before return 0, iclass 36, count 2 2006.257.14:49:36.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:36.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.14:49:36.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.14:49:36.41#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:36.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:36.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:36.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:36.53#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:49:36.53#ibcon#first serial, iclass 36, count 0 2006.257.14:49:36.53#ibcon#enter sib2, iclass 36, count 0 2006.257.14:49:36.53#ibcon#flushed, iclass 36, count 0 2006.257.14:49:36.53#ibcon#about to write, iclass 36, count 0 2006.257.14:49:36.53#ibcon#wrote, iclass 36, count 0 2006.257.14:49:36.53#ibcon#about to read 3, iclass 36, count 0 2006.257.14:49:36.55#ibcon#read 3, iclass 36, count 0 2006.257.14:49:36.55#ibcon#about to read 4, iclass 36, count 0 2006.257.14:49:36.55#ibcon#read 4, iclass 36, count 0 2006.257.14:49:36.55#ibcon#about to read 5, iclass 36, count 0 2006.257.14:49:36.55#ibcon#read 5, iclass 36, count 0 2006.257.14:49:36.55#ibcon#about to read 6, iclass 36, count 0 2006.257.14:49:36.55#ibcon#read 6, iclass 36, count 0 2006.257.14:49:36.55#ibcon#end of sib2, iclass 36, count 0 2006.257.14:49:36.55#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:49:36.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:49:36.55#ibcon#[27=USB\r\n] 2006.257.14:49:36.55#ibcon#*before write, iclass 36, count 0 2006.257.14:49:36.55#ibcon#enter sib2, iclass 36, count 0 2006.257.14:49:36.55#ibcon#flushed, iclass 36, count 0 2006.257.14:49:36.55#ibcon#about to write, iclass 36, count 0 2006.257.14:49:36.55#ibcon#wrote, iclass 36, count 0 2006.257.14:49:36.55#ibcon#about to read 3, iclass 36, count 0 2006.257.14:49:36.58#ibcon#read 3, iclass 36, count 0 2006.257.14:49:36.58#ibcon#about to read 4, iclass 36, count 0 2006.257.14:49:36.58#ibcon#read 4, iclass 36, count 0 2006.257.14:49:36.58#ibcon#about to read 5, iclass 36, count 0 2006.257.14:49:36.58#ibcon#read 5, iclass 36, count 0 2006.257.14:49:36.58#ibcon#about to read 6, iclass 36, count 0 2006.257.14:49:36.58#ibcon#read 6, iclass 36, count 0 2006.257.14:49:36.58#ibcon#end of sib2, iclass 36, count 0 2006.257.14:49:36.58#ibcon#*after write, iclass 36, count 0 2006.257.14:49:36.58#ibcon#*before return 0, iclass 36, count 0 2006.257.14:49:36.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:36.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.14:49:36.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:49:36.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:49:36.58$vck44/vblo=6,719.99 2006.257.14:49:36.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.14:49:36.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.14:49:36.58#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:36.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:49:36.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:49:36.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:49:36.58#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:49:36.58#ibcon#first serial, iclass 38, count 0 2006.257.14:49:36.58#ibcon#enter sib2, iclass 38, count 0 2006.257.14:49:36.58#ibcon#flushed, iclass 38, count 0 2006.257.14:49:36.58#ibcon#about to write, iclass 38, count 0 2006.257.14:49:36.58#ibcon#wrote, iclass 38, count 0 2006.257.14:49:36.58#ibcon#about to read 3, iclass 38, count 0 2006.257.14:49:36.60#ibcon#read 3, iclass 38, count 0 2006.257.14:49:36.60#ibcon#about to read 4, iclass 38, count 0 2006.257.14:49:36.60#ibcon#read 4, iclass 38, count 0 2006.257.14:49:36.60#ibcon#about to read 5, iclass 38, count 0 2006.257.14:49:36.60#ibcon#read 5, iclass 38, count 0 2006.257.14:49:36.60#ibcon#about to read 6, iclass 38, count 0 2006.257.14:49:36.60#ibcon#read 6, iclass 38, count 0 2006.257.14:49:36.60#ibcon#end of sib2, iclass 38, count 0 2006.257.14:49:36.60#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:49:36.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:49:36.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:49:36.60#ibcon#*before write, iclass 38, count 0 2006.257.14:49:36.60#ibcon#enter sib2, iclass 38, count 0 2006.257.14:49:36.60#ibcon#flushed, iclass 38, count 0 2006.257.14:49:36.60#ibcon#about to write, iclass 38, count 0 2006.257.14:49:36.60#ibcon#wrote, iclass 38, count 0 2006.257.14:49:36.60#ibcon#about to read 3, iclass 38, count 0 2006.257.14:49:36.64#ibcon#read 3, iclass 38, count 0 2006.257.14:49:36.64#ibcon#about to read 4, iclass 38, count 0 2006.257.14:49:36.64#ibcon#read 4, iclass 38, count 0 2006.257.14:49:36.64#ibcon#about to read 5, iclass 38, count 0 2006.257.14:49:36.64#ibcon#read 5, iclass 38, count 0 2006.257.14:49:36.64#ibcon#about to read 6, iclass 38, count 0 2006.257.14:49:36.64#ibcon#read 6, iclass 38, count 0 2006.257.14:49:36.64#ibcon#end of sib2, iclass 38, count 0 2006.257.14:49:36.64#ibcon#*after write, iclass 38, count 0 2006.257.14:49:36.64#ibcon#*before return 0, iclass 38, count 0 2006.257.14:49:36.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:49:36.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.14:49:36.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:49:36.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:49:36.64$vck44/vb=6,4 2006.257.14:49:36.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.14:49:36.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.14:49:36.64#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:36.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:49:36.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:49:36.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:49:36.70#ibcon#enter wrdev, iclass 40, count 2 2006.257.14:49:36.70#ibcon#first serial, iclass 40, count 2 2006.257.14:49:36.70#ibcon#enter sib2, iclass 40, count 2 2006.257.14:49:36.70#ibcon#flushed, iclass 40, count 2 2006.257.14:49:36.70#ibcon#about to write, iclass 40, count 2 2006.257.14:49:36.70#ibcon#wrote, iclass 40, count 2 2006.257.14:49:36.70#ibcon#about to read 3, iclass 40, count 2 2006.257.14:49:36.72#ibcon#read 3, iclass 40, count 2 2006.257.14:49:36.72#ibcon#about to read 4, iclass 40, count 2 2006.257.14:49:36.72#ibcon#read 4, iclass 40, count 2 2006.257.14:49:36.72#ibcon#about to read 5, iclass 40, count 2 2006.257.14:49:36.72#ibcon#read 5, iclass 40, count 2 2006.257.14:49:36.72#ibcon#about to read 6, iclass 40, count 2 2006.257.14:49:36.72#ibcon#read 6, iclass 40, count 2 2006.257.14:49:36.72#ibcon#end of sib2, iclass 40, count 2 2006.257.14:49:36.72#ibcon#*mode == 0, iclass 40, count 2 2006.257.14:49:36.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.14:49:36.72#ibcon#[27=AT06-04\r\n] 2006.257.14:49:36.72#ibcon#*before write, iclass 40, count 2 2006.257.14:49:36.72#ibcon#enter sib2, iclass 40, count 2 2006.257.14:49:36.72#ibcon#flushed, iclass 40, count 2 2006.257.14:49:36.72#ibcon#about to write, iclass 40, count 2 2006.257.14:49:36.72#ibcon#wrote, iclass 40, count 2 2006.257.14:49:36.72#ibcon#about to read 3, iclass 40, count 2 2006.257.14:49:36.75#ibcon#read 3, iclass 40, count 2 2006.257.14:49:36.75#ibcon#about to read 4, iclass 40, count 2 2006.257.14:49:36.75#ibcon#read 4, iclass 40, count 2 2006.257.14:49:36.75#ibcon#about to read 5, iclass 40, count 2 2006.257.14:49:36.75#ibcon#read 5, iclass 40, count 2 2006.257.14:49:36.75#ibcon#about to read 6, iclass 40, count 2 2006.257.14:49:36.75#ibcon#read 6, iclass 40, count 2 2006.257.14:49:36.75#ibcon#end of sib2, iclass 40, count 2 2006.257.14:49:36.75#ibcon#*after write, iclass 40, count 2 2006.257.14:49:36.75#ibcon#*before return 0, iclass 40, count 2 2006.257.14:49:36.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:49:36.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.14:49:36.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.14:49:36.75#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:36.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:49:36.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:49:36.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:49:36.87#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:49:36.87#ibcon#first serial, iclass 40, count 0 2006.257.14:49:36.87#ibcon#enter sib2, iclass 40, count 0 2006.257.14:49:36.87#ibcon#flushed, iclass 40, count 0 2006.257.14:49:36.87#ibcon#about to write, iclass 40, count 0 2006.257.14:49:36.87#ibcon#wrote, iclass 40, count 0 2006.257.14:49:36.87#ibcon#about to read 3, iclass 40, count 0 2006.257.14:49:36.89#ibcon#read 3, iclass 40, count 0 2006.257.14:49:36.89#ibcon#about to read 4, iclass 40, count 0 2006.257.14:49:36.89#ibcon#read 4, iclass 40, count 0 2006.257.14:49:36.89#ibcon#about to read 5, iclass 40, count 0 2006.257.14:49:36.89#ibcon#read 5, iclass 40, count 0 2006.257.14:49:36.89#ibcon#about to read 6, iclass 40, count 0 2006.257.14:49:36.89#ibcon#read 6, iclass 40, count 0 2006.257.14:49:36.89#ibcon#end of sib2, iclass 40, count 0 2006.257.14:49:36.89#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:49:36.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:49:36.89#ibcon#[27=USB\r\n] 2006.257.14:49:36.89#ibcon#*before write, iclass 40, count 0 2006.257.14:49:36.89#ibcon#enter sib2, iclass 40, count 0 2006.257.14:49:36.89#ibcon#flushed, iclass 40, count 0 2006.257.14:49:36.89#ibcon#about to write, iclass 40, count 0 2006.257.14:49:36.89#ibcon#wrote, iclass 40, count 0 2006.257.14:49:36.89#ibcon#about to read 3, iclass 40, count 0 2006.257.14:49:36.92#ibcon#read 3, iclass 40, count 0 2006.257.14:49:36.92#ibcon#about to read 4, iclass 40, count 0 2006.257.14:49:36.92#ibcon#read 4, iclass 40, count 0 2006.257.14:49:36.92#ibcon#about to read 5, iclass 40, count 0 2006.257.14:49:36.92#ibcon#read 5, iclass 40, count 0 2006.257.14:49:36.92#ibcon#about to read 6, iclass 40, count 0 2006.257.14:49:36.92#ibcon#read 6, iclass 40, count 0 2006.257.14:49:36.92#ibcon#end of sib2, iclass 40, count 0 2006.257.14:49:36.92#ibcon#*after write, iclass 40, count 0 2006.257.14:49:36.92#ibcon#*before return 0, iclass 40, count 0 2006.257.14:49:36.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:49:36.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.14:49:36.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:49:36.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:49:36.92$vck44/vblo=7,734.99 2006.257.14:49:36.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.14:49:36.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.14:49:36.92#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:36.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:36.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:36.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:36.92#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:49:36.92#ibcon#first serial, iclass 4, count 0 2006.257.14:49:36.92#ibcon#enter sib2, iclass 4, count 0 2006.257.14:49:36.92#ibcon#flushed, iclass 4, count 0 2006.257.14:49:36.92#ibcon#about to write, iclass 4, count 0 2006.257.14:49:36.92#ibcon#wrote, iclass 4, count 0 2006.257.14:49:36.92#ibcon#about to read 3, iclass 4, count 0 2006.257.14:49:36.94#ibcon#read 3, iclass 4, count 0 2006.257.14:49:36.94#ibcon#about to read 4, iclass 4, count 0 2006.257.14:49:36.94#ibcon#read 4, iclass 4, count 0 2006.257.14:49:36.94#ibcon#about to read 5, iclass 4, count 0 2006.257.14:49:36.94#ibcon#read 5, iclass 4, count 0 2006.257.14:49:36.94#ibcon#about to read 6, iclass 4, count 0 2006.257.14:49:36.94#ibcon#read 6, iclass 4, count 0 2006.257.14:49:36.94#ibcon#end of sib2, iclass 4, count 0 2006.257.14:49:36.94#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:49:36.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:49:36.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:49:36.94#ibcon#*before write, iclass 4, count 0 2006.257.14:49:36.94#ibcon#enter sib2, iclass 4, count 0 2006.257.14:49:36.94#ibcon#flushed, iclass 4, count 0 2006.257.14:49:36.94#ibcon#about to write, iclass 4, count 0 2006.257.14:49:36.94#ibcon#wrote, iclass 4, count 0 2006.257.14:49:36.94#ibcon#about to read 3, iclass 4, count 0 2006.257.14:49:36.98#ibcon#read 3, iclass 4, count 0 2006.257.14:49:36.98#ibcon#about to read 4, iclass 4, count 0 2006.257.14:49:36.98#ibcon#read 4, iclass 4, count 0 2006.257.14:49:36.98#ibcon#about to read 5, iclass 4, count 0 2006.257.14:49:36.98#ibcon#read 5, iclass 4, count 0 2006.257.14:49:36.98#ibcon#about to read 6, iclass 4, count 0 2006.257.14:49:36.98#ibcon#read 6, iclass 4, count 0 2006.257.14:49:36.98#ibcon#end of sib2, iclass 4, count 0 2006.257.14:49:36.98#ibcon#*after write, iclass 4, count 0 2006.257.14:49:36.98#ibcon#*before return 0, iclass 4, count 0 2006.257.14:49:36.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:36.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.14:49:36.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:49:36.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:49:36.98$vck44/vb=7,4 2006.257.14:49:36.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.14:49:36.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.14:49:36.98#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:36.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:37.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:37.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:37.04#ibcon#enter wrdev, iclass 6, count 2 2006.257.14:49:37.04#ibcon#first serial, iclass 6, count 2 2006.257.14:49:37.04#ibcon#enter sib2, iclass 6, count 2 2006.257.14:49:37.04#ibcon#flushed, iclass 6, count 2 2006.257.14:49:37.04#ibcon#about to write, iclass 6, count 2 2006.257.14:49:37.04#ibcon#wrote, iclass 6, count 2 2006.257.14:49:37.04#ibcon#about to read 3, iclass 6, count 2 2006.257.14:49:37.06#ibcon#read 3, iclass 6, count 2 2006.257.14:49:37.06#ibcon#about to read 4, iclass 6, count 2 2006.257.14:49:37.06#ibcon#read 4, iclass 6, count 2 2006.257.14:49:37.06#ibcon#about to read 5, iclass 6, count 2 2006.257.14:49:37.06#ibcon#read 5, iclass 6, count 2 2006.257.14:49:37.06#ibcon#about to read 6, iclass 6, count 2 2006.257.14:49:37.06#ibcon#read 6, iclass 6, count 2 2006.257.14:49:37.06#ibcon#end of sib2, iclass 6, count 2 2006.257.14:49:37.06#ibcon#*mode == 0, iclass 6, count 2 2006.257.14:49:37.06#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.14:49:37.06#ibcon#[27=AT07-04\r\n] 2006.257.14:49:37.06#ibcon#*before write, iclass 6, count 2 2006.257.14:49:37.06#ibcon#enter sib2, iclass 6, count 2 2006.257.14:49:37.06#ibcon#flushed, iclass 6, count 2 2006.257.14:49:37.06#ibcon#about to write, iclass 6, count 2 2006.257.14:49:37.06#ibcon#wrote, iclass 6, count 2 2006.257.14:49:37.06#ibcon#about to read 3, iclass 6, count 2 2006.257.14:49:37.09#ibcon#read 3, iclass 6, count 2 2006.257.14:49:37.09#ibcon#about to read 4, iclass 6, count 2 2006.257.14:49:37.09#ibcon#read 4, iclass 6, count 2 2006.257.14:49:37.09#ibcon#about to read 5, iclass 6, count 2 2006.257.14:49:37.09#ibcon#read 5, iclass 6, count 2 2006.257.14:49:37.09#ibcon#about to read 6, iclass 6, count 2 2006.257.14:49:37.09#ibcon#read 6, iclass 6, count 2 2006.257.14:49:37.09#ibcon#end of sib2, iclass 6, count 2 2006.257.14:49:37.09#ibcon#*after write, iclass 6, count 2 2006.257.14:49:37.09#ibcon#*before return 0, iclass 6, count 2 2006.257.14:49:37.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:37.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.14:49:37.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.14:49:37.09#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:37.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:37.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:37.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:37.21#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:49:37.21#ibcon#first serial, iclass 6, count 0 2006.257.14:49:37.21#ibcon#enter sib2, iclass 6, count 0 2006.257.14:49:37.21#ibcon#flushed, iclass 6, count 0 2006.257.14:49:37.21#ibcon#about to write, iclass 6, count 0 2006.257.14:49:37.21#ibcon#wrote, iclass 6, count 0 2006.257.14:49:37.21#ibcon#about to read 3, iclass 6, count 0 2006.257.14:49:37.23#ibcon#read 3, iclass 6, count 0 2006.257.14:49:37.23#ibcon#about to read 4, iclass 6, count 0 2006.257.14:49:37.23#ibcon#read 4, iclass 6, count 0 2006.257.14:49:37.23#ibcon#about to read 5, iclass 6, count 0 2006.257.14:49:37.23#ibcon#read 5, iclass 6, count 0 2006.257.14:49:37.23#ibcon#about to read 6, iclass 6, count 0 2006.257.14:49:37.23#ibcon#read 6, iclass 6, count 0 2006.257.14:49:37.23#ibcon#end of sib2, iclass 6, count 0 2006.257.14:49:37.23#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:49:37.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:49:37.23#ibcon#[27=USB\r\n] 2006.257.14:49:37.23#ibcon#*before write, iclass 6, count 0 2006.257.14:49:37.23#ibcon#enter sib2, iclass 6, count 0 2006.257.14:49:37.23#ibcon#flushed, iclass 6, count 0 2006.257.14:49:37.23#ibcon#about to write, iclass 6, count 0 2006.257.14:49:37.23#ibcon#wrote, iclass 6, count 0 2006.257.14:49:37.23#ibcon#about to read 3, iclass 6, count 0 2006.257.14:49:37.26#ibcon#read 3, iclass 6, count 0 2006.257.14:49:37.26#ibcon#about to read 4, iclass 6, count 0 2006.257.14:49:37.26#ibcon#read 4, iclass 6, count 0 2006.257.14:49:37.26#ibcon#about to read 5, iclass 6, count 0 2006.257.14:49:37.26#ibcon#read 5, iclass 6, count 0 2006.257.14:49:37.26#ibcon#about to read 6, iclass 6, count 0 2006.257.14:49:37.26#ibcon#read 6, iclass 6, count 0 2006.257.14:49:37.26#ibcon#end of sib2, iclass 6, count 0 2006.257.14:49:37.26#ibcon#*after write, iclass 6, count 0 2006.257.14:49:37.26#ibcon#*before return 0, iclass 6, count 0 2006.257.14:49:37.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:37.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.14:49:37.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:49:37.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:49:37.26$vck44/vblo=8,744.99 2006.257.14:49:37.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.14:49:37.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.14:49:37.26#ibcon#ireg 17 cls_cnt 0 2006.257.14:49:37.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:37.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:37.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:37.26#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:49:37.26#ibcon#first serial, iclass 10, count 0 2006.257.14:49:37.26#ibcon#enter sib2, iclass 10, count 0 2006.257.14:49:37.26#ibcon#flushed, iclass 10, count 0 2006.257.14:49:37.26#ibcon#about to write, iclass 10, count 0 2006.257.14:49:37.26#ibcon#wrote, iclass 10, count 0 2006.257.14:49:37.26#ibcon#about to read 3, iclass 10, count 0 2006.257.14:49:37.28#ibcon#read 3, iclass 10, count 0 2006.257.14:49:37.28#ibcon#about to read 4, iclass 10, count 0 2006.257.14:49:37.28#ibcon#read 4, iclass 10, count 0 2006.257.14:49:37.28#ibcon#about to read 5, iclass 10, count 0 2006.257.14:49:37.28#ibcon#read 5, iclass 10, count 0 2006.257.14:49:37.28#ibcon#about to read 6, iclass 10, count 0 2006.257.14:49:37.28#ibcon#read 6, iclass 10, count 0 2006.257.14:49:37.28#ibcon#end of sib2, iclass 10, count 0 2006.257.14:49:37.28#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:49:37.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:49:37.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:49:37.28#ibcon#*before write, iclass 10, count 0 2006.257.14:49:37.28#ibcon#enter sib2, iclass 10, count 0 2006.257.14:49:37.28#ibcon#flushed, iclass 10, count 0 2006.257.14:49:37.28#ibcon#about to write, iclass 10, count 0 2006.257.14:49:37.28#ibcon#wrote, iclass 10, count 0 2006.257.14:49:37.28#ibcon#about to read 3, iclass 10, count 0 2006.257.14:49:37.32#ibcon#read 3, iclass 10, count 0 2006.257.14:49:37.32#ibcon#about to read 4, iclass 10, count 0 2006.257.14:49:37.32#ibcon#read 4, iclass 10, count 0 2006.257.14:49:37.32#ibcon#about to read 5, iclass 10, count 0 2006.257.14:49:37.32#ibcon#read 5, iclass 10, count 0 2006.257.14:49:37.32#ibcon#about to read 6, iclass 10, count 0 2006.257.14:49:37.32#ibcon#read 6, iclass 10, count 0 2006.257.14:49:37.32#ibcon#end of sib2, iclass 10, count 0 2006.257.14:49:37.32#ibcon#*after write, iclass 10, count 0 2006.257.14:49:37.32#ibcon#*before return 0, iclass 10, count 0 2006.257.14:49:37.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:37.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.14:49:37.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:49:37.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:49:37.32$vck44/vb=8,4 2006.257.14:49:37.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.14:49:37.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.14:49:37.32#ibcon#ireg 11 cls_cnt 2 2006.257.14:49:37.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:37.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:37.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:37.38#ibcon#enter wrdev, iclass 12, count 2 2006.257.14:49:37.38#ibcon#first serial, iclass 12, count 2 2006.257.14:49:37.38#ibcon#enter sib2, iclass 12, count 2 2006.257.14:49:37.38#ibcon#flushed, iclass 12, count 2 2006.257.14:49:37.38#ibcon#about to write, iclass 12, count 2 2006.257.14:49:37.38#ibcon#wrote, iclass 12, count 2 2006.257.14:49:37.38#ibcon#about to read 3, iclass 12, count 2 2006.257.14:49:37.40#ibcon#read 3, iclass 12, count 2 2006.257.14:49:37.40#ibcon#about to read 4, iclass 12, count 2 2006.257.14:49:37.40#ibcon#read 4, iclass 12, count 2 2006.257.14:49:37.40#ibcon#about to read 5, iclass 12, count 2 2006.257.14:49:37.40#ibcon#read 5, iclass 12, count 2 2006.257.14:49:37.40#ibcon#about to read 6, iclass 12, count 2 2006.257.14:49:37.40#ibcon#read 6, iclass 12, count 2 2006.257.14:49:37.40#ibcon#end of sib2, iclass 12, count 2 2006.257.14:49:37.40#ibcon#*mode == 0, iclass 12, count 2 2006.257.14:49:37.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.14:49:37.40#ibcon#[27=AT08-04\r\n] 2006.257.14:49:37.40#ibcon#*before write, iclass 12, count 2 2006.257.14:49:37.40#ibcon#enter sib2, iclass 12, count 2 2006.257.14:49:37.40#ibcon#flushed, iclass 12, count 2 2006.257.14:49:37.40#ibcon#about to write, iclass 12, count 2 2006.257.14:49:37.40#ibcon#wrote, iclass 12, count 2 2006.257.14:49:37.40#ibcon#about to read 3, iclass 12, count 2 2006.257.14:49:37.43#ibcon#read 3, iclass 12, count 2 2006.257.14:49:37.43#ibcon#about to read 4, iclass 12, count 2 2006.257.14:49:37.50#ibcon#read 4, iclass 12, count 2 2006.257.14:49:37.50#ibcon#about to read 5, iclass 12, count 2 2006.257.14:49:37.50#ibcon#read 5, iclass 12, count 2 2006.257.14:49:37.50#ibcon#about to read 6, iclass 12, count 2 2006.257.14:49:37.50#ibcon#read 6, iclass 12, count 2 2006.257.14:49:37.50#ibcon#end of sib2, iclass 12, count 2 2006.257.14:49:37.50#ibcon#*after write, iclass 12, count 2 2006.257.14:49:37.50#ibcon#*before return 0, iclass 12, count 2 2006.257.14:49:37.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:37.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.14:49:37.50#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.14:49:37.50#ibcon#ireg 7 cls_cnt 0 2006.257.14:49:37.50#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:37.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:37.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:37.61#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:49:37.61#ibcon#first serial, iclass 12, count 0 2006.257.14:49:37.61#ibcon#enter sib2, iclass 12, count 0 2006.257.14:49:37.61#ibcon#flushed, iclass 12, count 0 2006.257.14:49:37.61#ibcon#about to write, iclass 12, count 0 2006.257.14:49:37.61#ibcon#wrote, iclass 12, count 0 2006.257.14:49:37.61#ibcon#about to read 3, iclass 12, count 0 2006.257.14:49:37.63#ibcon#read 3, iclass 12, count 0 2006.257.14:49:37.63#ibcon#about to read 4, iclass 12, count 0 2006.257.14:49:37.63#ibcon#read 4, iclass 12, count 0 2006.257.14:49:37.63#ibcon#about to read 5, iclass 12, count 0 2006.257.14:49:37.63#ibcon#read 5, iclass 12, count 0 2006.257.14:49:37.63#ibcon#about to read 6, iclass 12, count 0 2006.257.14:49:37.63#ibcon#read 6, iclass 12, count 0 2006.257.14:49:37.63#ibcon#end of sib2, iclass 12, count 0 2006.257.14:49:37.63#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:49:37.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:49:37.63#ibcon#[27=USB\r\n] 2006.257.14:49:37.63#ibcon#*before write, iclass 12, count 0 2006.257.14:49:37.63#ibcon#enter sib2, iclass 12, count 0 2006.257.14:49:37.63#ibcon#flushed, iclass 12, count 0 2006.257.14:49:37.63#ibcon#about to write, iclass 12, count 0 2006.257.14:49:37.63#ibcon#wrote, iclass 12, count 0 2006.257.14:49:37.63#ibcon#about to read 3, iclass 12, count 0 2006.257.14:49:37.66#ibcon#read 3, iclass 12, count 0 2006.257.14:49:37.66#ibcon#about to read 4, iclass 12, count 0 2006.257.14:49:37.66#ibcon#read 4, iclass 12, count 0 2006.257.14:49:37.66#ibcon#about to read 5, iclass 12, count 0 2006.257.14:49:37.66#ibcon#read 5, iclass 12, count 0 2006.257.14:49:37.66#ibcon#about to read 6, iclass 12, count 0 2006.257.14:49:37.66#ibcon#read 6, iclass 12, count 0 2006.257.14:49:37.66#ibcon#end of sib2, iclass 12, count 0 2006.257.14:49:37.66#ibcon#*after write, iclass 12, count 0 2006.257.14:49:37.66#ibcon#*before return 0, iclass 12, count 0 2006.257.14:49:37.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:37.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.14:49:37.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:49:37.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:49:37.66$vck44/vabw=wide 2006.257.14:49:37.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.14:49:37.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.14:49:37.66#ibcon#ireg 8 cls_cnt 0 2006.257.14:49:37.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:37.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:37.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:37.66#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:49:37.66#ibcon#first serial, iclass 14, count 0 2006.257.14:49:37.66#ibcon#enter sib2, iclass 14, count 0 2006.257.14:49:37.66#ibcon#flushed, iclass 14, count 0 2006.257.14:49:37.66#ibcon#about to write, iclass 14, count 0 2006.257.14:49:37.66#ibcon#wrote, iclass 14, count 0 2006.257.14:49:37.66#ibcon#about to read 3, iclass 14, count 0 2006.257.14:49:37.68#ibcon#read 3, iclass 14, count 0 2006.257.14:49:37.68#ibcon#about to read 4, iclass 14, count 0 2006.257.14:49:37.68#ibcon#read 4, iclass 14, count 0 2006.257.14:49:37.68#ibcon#about to read 5, iclass 14, count 0 2006.257.14:49:37.68#ibcon#read 5, iclass 14, count 0 2006.257.14:49:37.68#ibcon#about to read 6, iclass 14, count 0 2006.257.14:49:37.68#ibcon#read 6, iclass 14, count 0 2006.257.14:49:37.68#ibcon#end of sib2, iclass 14, count 0 2006.257.14:49:37.68#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:49:37.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:49:37.68#ibcon#[25=BW32\r\n] 2006.257.14:49:37.68#ibcon#*before write, iclass 14, count 0 2006.257.14:49:37.68#ibcon#enter sib2, iclass 14, count 0 2006.257.14:49:37.68#ibcon#flushed, iclass 14, count 0 2006.257.14:49:37.68#ibcon#about to write, iclass 14, count 0 2006.257.14:49:37.68#ibcon#wrote, iclass 14, count 0 2006.257.14:49:37.68#ibcon#about to read 3, iclass 14, count 0 2006.257.14:49:37.71#ibcon#read 3, iclass 14, count 0 2006.257.14:49:37.71#ibcon#about to read 4, iclass 14, count 0 2006.257.14:49:37.71#ibcon#read 4, iclass 14, count 0 2006.257.14:49:37.71#ibcon#about to read 5, iclass 14, count 0 2006.257.14:49:37.71#ibcon#read 5, iclass 14, count 0 2006.257.14:49:37.71#ibcon#about to read 6, iclass 14, count 0 2006.257.14:49:37.71#ibcon#read 6, iclass 14, count 0 2006.257.14:49:37.71#ibcon#end of sib2, iclass 14, count 0 2006.257.14:49:37.71#ibcon#*after write, iclass 14, count 0 2006.257.14:49:37.71#ibcon#*before return 0, iclass 14, count 0 2006.257.14:49:37.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:37.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.14:49:37.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:49:37.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:49:37.71$vck44/vbbw=wide 2006.257.14:49:37.71#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.14:49:37.71#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.14:49:37.71#ibcon#ireg 8 cls_cnt 0 2006.257.14:49:37.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:49:37.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:49:37.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:49:37.78#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:49:37.78#ibcon#first serial, iclass 16, count 0 2006.257.14:49:37.78#ibcon#enter sib2, iclass 16, count 0 2006.257.14:49:37.78#ibcon#flushed, iclass 16, count 0 2006.257.14:49:37.78#ibcon#about to write, iclass 16, count 0 2006.257.14:49:37.78#ibcon#wrote, iclass 16, count 0 2006.257.14:49:37.78#ibcon#about to read 3, iclass 16, count 0 2006.257.14:49:37.80#ibcon#read 3, iclass 16, count 0 2006.257.14:49:37.80#ibcon#about to read 4, iclass 16, count 0 2006.257.14:49:37.80#ibcon#read 4, iclass 16, count 0 2006.257.14:49:37.80#ibcon#about to read 5, iclass 16, count 0 2006.257.14:49:37.80#ibcon#read 5, iclass 16, count 0 2006.257.14:49:37.80#ibcon#about to read 6, iclass 16, count 0 2006.257.14:49:37.80#ibcon#read 6, iclass 16, count 0 2006.257.14:49:37.80#ibcon#end of sib2, iclass 16, count 0 2006.257.14:49:37.80#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:49:37.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:49:37.80#ibcon#[27=BW32\r\n] 2006.257.14:49:37.80#ibcon#*before write, iclass 16, count 0 2006.257.14:49:37.80#ibcon#enter sib2, iclass 16, count 0 2006.257.14:49:37.80#ibcon#flushed, iclass 16, count 0 2006.257.14:49:37.80#ibcon#about to write, iclass 16, count 0 2006.257.14:49:37.80#ibcon#wrote, iclass 16, count 0 2006.257.14:49:37.80#ibcon#about to read 3, iclass 16, count 0 2006.257.14:49:37.83#ibcon#read 3, iclass 16, count 0 2006.257.14:49:37.83#ibcon#about to read 4, iclass 16, count 0 2006.257.14:49:37.83#ibcon#read 4, iclass 16, count 0 2006.257.14:49:37.83#ibcon#about to read 5, iclass 16, count 0 2006.257.14:49:37.83#ibcon#read 5, iclass 16, count 0 2006.257.14:49:37.83#ibcon#about to read 6, iclass 16, count 0 2006.257.14:49:37.83#ibcon#read 6, iclass 16, count 0 2006.257.14:49:37.83#ibcon#end of sib2, iclass 16, count 0 2006.257.14:49:37.83#ibcon#*after write, iclass 16, count 0 2006.257.14:49:37.83#ibcon#*before return 0, iclass 16, count 0 2006.257.14:49:37.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:49:37.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:49:37.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:49:37.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:49:37.83$setupk4/ifdk4 2006.257.14:49:37.83$ifdk4/lo= 2006.257.14:49:37.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:49:37.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:49:37.83$ifdk4/patch= 2006.257.14:49:37.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:49:37.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:49:37.83$setupk4/!*+20s 2006.257.14:49:43.82#abcon#<5=/14 1.2 3.3 17.47 971014.2\r\n> 2006.257.14:49:43.84#abcon#{5=INTERFACE CLEAR} 2006.257.14:49:43.90#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:49:52.19$setupk4/"tpicd 2006.257.14:49:52.19$setupk4/echo=off 2006.257.14:49:52.19$setupk4/xlog=off 2006.257.14:49:52.19:!2006.257.14:54:37 2006.257.14:50:31.14#trakl#Source acquired 2006.257.14:50:31.14#flagr#flagr/antenna,acquired 2006.257.14:54:37.00:preob 2006.257.14:54:38.13/onsource/TRACKING 2006.257.14:54:38.13:!2006.257.14:54:47 2006.257.14:54:47.00:"tape 2006.257.14:54:47.00:"st=record 2006.257.14:54:47.00:data_valid=on 2006.257.14:54:47.00:midob 2006.257.14:54:47.13/onsource/TRACKING 2006.257.14:54:47.13/wx/17.47,1014.2,97 2006.257.14:54:47.19/cable/+6.4840E-03 2006.257.14:54:48.28/va/01,08,usb,yes,30,33 2006.257.14:54:48.28/va/02,07,usb,yes,33,33 2006.257.14:54:48.28/va/03,08,usb,yes,30,31 2006.257.14:54:48.28/va/04,07,usb,yes,34,36 2006.257.14:54:48.28/va/05,04,usb,yes,31,31 2006.257.14:54:48.28/va/06,04,usb,yes,34,34 2006.257.14:54:48.28/va/07,04,usb,yes,35,35 2006.257.14:54:48.28/va/08,04,usb,yes,29,36 2006.257.14:54:48.51/valo/01,524.99,yes,locked 2006.257.14:54:48.51/valo/02,534.99,yes,locked 2006.257.14:54:48.51/valo/03,564.99,yes,locked 2006.257.14:54:48.51/valo/04,624.99,yes,locked 2006.257.14:54:48.51/valo/05,734.99,yes,locked 2006.257.14:54:48.51/valo/06,814.99,yes,locked 2006.257.14:54:48.51/valo/07,864.99,yes,locked 2006.257.14:54:48.51/valo/08,884.99,yes,locked 2006.257.14:54:49.60/vb/01,04,usb,yes,30,28 2006.257.14:54:49.60/vb/02,05,usb,yes,29,29 2006.257.14:54:49.60/vb/03,04,usb,yes,29,32 2006.257.14:54:49.60/vb/04,05,usb,yes,30,29 2006.257.14:54:49.60/vb/05,04,usb,yes,26,29 2006.257.14:54:49.60/vb/06,04,usb,yes,31,27 2006.257.14:54:49.60/vb/07,04,usb,yes,30,30 2006.257.14:54:49.60/vb/08,04,usb,yes,28,31 2006.257.14:54:49.83/vblo/01,629.99,yes,locked 2006.257.14:54:49.83/vblo/02,634.99,yes,locked 2006.257.14:54:49.83/vblo/03,649.99,yes,locked 2006.257.14:54:49.83/vblo/04,679.99,yes,locked 2006.257.14:54:49.83/vblo/05,709.99,yes,locked 2006.257.14:54:49.83/vblo/06,719.99,yes,locked 2006.257.14:54:49.83/vblo/07,734.99,yes,locked 2006.257.14:54:49.83/vblo/08,744.99,yes,locked 2006.257.14:54:49.98/vabw/8 2006.257.14:54:50.13/vbbw/8 2006.257.14:54:50.22/xfe/off,on,15.2 2006.257.14:54:50.60/ifatt/23,28,28,28 2006.257.14:54:51.08/fmout-gps/S +4.61E-07 2006.257.14:54:51.12:!2006.257.14:56:07 2006.257.14:56:07.00:data_valid=off 2006.257.14:56:07.00:"et 2006.257.14:56:07.00:!+3s 2006.257.14:56:10.02:"tape 2006.257.14:56:10.02:postob 2006.257.14:56:10.08/cable/+6.4841E-03 2006.257.14:56:10.08/wx/17.46,1014.2,97 2006.257.14:56:11.08/fmout-gps/S +4.62E-07 2006.257.14:56:11.08:scan_name=257-1459,jd0609,140 2006.257.14:56:11.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.257.14:56:12.13#flagr#flagr/antenna,new-source 2006.257.14:56:12.14:checkk5 2006.257.14:56:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.257.14:56:12.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.14:56:13.33/chk_autoobs//k5ts3/ autoobs is running! 2006.257.14:56:13.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.14:56:14.11/chk_obsdata//k5ts1/T2571454??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:56:14.52/chk_obsdata//k5ts2/T2571454??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:56:14.91/chk_obsdata//k5ts3/T2571454??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:56:15.31/chk_obsdata//k5ts4/T2571454??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.14:56:16.04/k5log//k5ts1_log_newline 2006.257.14:56:16.75/k5log//k5ts2_log_newline 2006.257.14:56:17.45/k5log//k5ts3_log_newline 2006.257.14:56:18.15/k5log//k5ts4_log_newline 2006.257.14:56:18.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.14:56:18.18:setupk4=1 2006.257.14:56:18.18$setupk4/echo=on 2006.257.14:56:18.18$setupk4/pcalon 2006.257.14:56:18.18$pcalon/"no phase cal control is implemented here 2006.257.14:56:18.18$setupk4/"tpicd=stop 2006.257.14:56:18.18$setupk4/"rec=synch_on 2006.257.14:56:18.18$setupk4/"rec_mode=128 2006.257.14:56:18.18$setupk4/!* 2006.257.14:56:18.18$setupk4/recpk4 2006.257.14:56:18.18$recpk4/recpatch= 2006.257.14:56:18.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.14:56:18.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.14:56:18.18$setupk4/vck44 2006.257.14:56:18.18$vck44/valo=1,524.99 2006.257.14:56:18.18#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.14:56:18.18#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.14:56:18.18#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:18.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:18.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:18.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:18.18#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:56:18.18#ibcon#first serial, iclass 28, count 0 2006.257.14:56:18.18#ibcon#enter sib2, iclass 28, count 0 2006.257.14:56:18.18#ibcon#flushed, iclass 28, count 0 2006.257.14:56:18.18#ibcon#about to write, iclass 28, count 0 2006.257.14:56:18.18#ibcon#wrote, iclass 28, count 0 2006.257.14:56:18.18#ibcon#about to read 3, iclass 28, count 0 2006.257.14:56:18.20#ibcon#read 3, iclass 28, count 0 2006.257.14:56:18.20#ibcon#about to read 4, iclass 28, count 0 2006.257.14:56:18.20#ibcon#read 4, iclass 28, count 0 2006.257.14:56:18.20#ibcon#about to read 5, iclass 28, count 0 2006.257.14:56:18.20#ibcon#read 5, iclass 28, count 0 2006.257.14:56:18.20#ibcon#about to read 6, iclass 28, count 0 2006.257.14:56:18.20#ibcon#read 6, iclass 28, count 0 2006.257.14:56:18.20#ibcon#end of sib2, iclass 28, count 0 2006.257.14:56:18.20#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:56:18.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:56:18.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.14:56:18.20#ibcon#*before write, iclass 28, count 0 2006.257.14:56:18.20#ibcon#enter sib2, iclass 28, count 0 2006.257.14:56:18.20#ibcon#flushed, iclass 28, count 0 2006.257.14:56:18.20#ibcon#about to write, iclass 28, count 0 2006.257.14:56:18.20#ibcon#wrote, iclass 28, count 0 2006.257.14:56:18.20#ibcon#about to read 3, iclass 28, count 0 2006.257.14:56:18.25#ibcon#read 3, iclass 28, count 0 2006.257.14:56:18.25#ibcon#about to read 4, iclass 28, count 0 2006.257.14:56:18.25#ibcon#read 4, iclass 28, count 0 2006.257.14:56:18.25#ibcon#about to read 5, iclass 28, count 0 2006.257.14:56:18.25#ibcon#read 5, iclass 28, count 0 2006.257.14:56:18.25#ibcon#about to read 6, iclass 28, count 0 2006.257.14:56:18.25#ibcon#read 6, iclass 28, count 0 2006.257.14:56:18.25#ibcon#end of sib2, iclass 28, count 0 2006.257.14:56:18.25#ibcon#*after write, iclass 28, count 0 2006.257.14:56:18.25#ibcon#*before return 0, iclass 28, count 0 2006.257.14:56:18.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:18.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:18.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:56:18.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:56:18.25$vck44/va=1,8 2006.257.14:56:18.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.14:56:18.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.14:56:18.25#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:18.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:18.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:18.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:18.25#ibcon#enter wrdev, iclass 30, count 2 2006.257.14:56:18.25#ibcon#first serial, iclass 30, count 2 2006.257.14:56:18.25#ibcon#enter sib2, iclass 30, count 2 2006.257.14:56:18.25#ibcon#flushed, iclass 30, count 2 2006.257.14:56:18.25#ibcon#about to write, iclass 30, count 2 2006.257.14:56:18.25#ibcon#wrote, iclass 30, count 2 2006.257.14:56:18.25#ibcon#about to read 3, iclass 30, count 2 2006.257.14:56:18.27#ibcon#read 3, iclass 30, count 2 2006.257.14:56:18.27#ibcon#about to read 4, iclass 30, count 2 2006.257.14:56:18.27#ibcon#read 4, iclass 30, count 2 2006.257.14:56:18.27#ibcon#about to read 5, iclass 30, count 2 2006.257.14:56:18.27#ibcon#read 5, iclass 30, count 2 2006.257.14:56:18.27#ibcon#about to read 6, iclass 30, count 2 2006.257.14:56:18.27#ibcon#read 6, iclass 30, count 2 2006.257.14:56:18.27#ibcon#end of sib2, iclass 30, count 2 2006.257.14:56:18.27#ibcon#*mode == 0, iclass 30, count 2 2006.257.14:56:18.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.14:56:18.27#ibcon#[25=AT01-08\r\n] 2006.257.14:56:18.27#ibcon#*before write, iclass 30, count 2 2006.257.14:56:18.27#ibcon#enter sib2, iclass 30, count 2 2006.257.14:56:18.27#ibcon#flushed, iclass 30, count 2 2006.257.14:56:18.27#ibcon#about to write, iclass 30, count 2 2006.257.14:56:18.27#ibcon#wrote, iclass 30, count 2 2006.257.14:56:18.27#ibcon#about to read 3, iclass 30, count 2 2006.257.14:56:18.30#ibcon#read 3, iclass 30, count 2 2006.257.14:56:18.30#ibcon#about to read 4, iclass 30, count 2 2006.257.14:56:18.30#ibcon#read 4, iclass 30, count 2 2006.257.14:56:18.30#ibcon#about to read 5, iclass 30, count 2 2006.257.14:56:18.30#ibcon#read 5, iclass 30, count 2 2006.257.14:56:18.30#ibcon#about to read 6, iclass 30, count 2 2006.257.14:56:18.30#ibcon#read 6, iclass 30, count 2 2006.257.14:56:18.30#ibcon#end of sib2, iclass 30, count 2 2006.257.14:56:18.30#ibcon#*after write, iclass 30, count 2 2006.257.14:56:18.30#ibcon#*before return 0, iclass 30, count 2 2006.257.14:56:18.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:18.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:18.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.14:56:18.30#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:18.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:18.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:18.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:18.42#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:56:18.42#ibcon#first serial, iclass 30, count 0 2006.257.14:56:18.42#ibcon#enter sib2, iclass 30, count 0 2006.257.14:56:18.42#ibcon#flushed, iclass 30, count 0 2006.257.14:56:18.42#ibcon#about to write, iclass 30, count 0 2006.257.14:56:18.42#ibcon#wrote, iclass 30, count 0 2006.257.14:56:18.42#ibcon#about to read 3, iclass 30, count 0 2006.257.14:56:18.44#ibcon#read 3, iclass 30, count 0 2006.257.14:56:18.44#ibcon#about to read 4, iclass 30, count 0 2006.257.14:56:18.44#ibcon#read 4, iclass 30, count 0 2006.257.14:56:18.44#ibcon#about to read 5, iclass 30, count 0 2006.257.14:56:18.44#ibcon#read 5, iclass 30, count 0 2006.257.14:56:18.44#ibcon#about to read 6, iclass 30, count 0 2006.257.14:56:18.44#ibcon#read 6, iclass 30, count 0 2006.257.14:56:18.44#ibcon#end of sib2, iclass 30, count 0 2006.257.14:56:18.44#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:56:18.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:56:18.44#ibcon#[25=USB\r\n] 2006.257.14:56:18.44#ibcon#*before write, iclass 30, count 0 2006.257.14:56:18.44#ibcon#enter sib2, iclass 30, count 0 2006.257.14:56:18.44#ibcon#flushed, iclass 30, count 0 2006.257.14:56:18.44#ibcon#about to write, iclass 30, count 0 2006.257.14:56:18.44#ibcon#wrote, iclass 30, count 0 2006.257.14:56:18.44#ibcon#about to read 3, iclass 30, count 0 2006.257.14:56:18.47#ibcon#read 3, iclass 30, count 0 2006.257.14:56:18.47#ibcon#about to read 4, iclass 30, count 0 2006.257.14:56:18.47#ibcon#read 4, iclass 30, count 0 2006.257.14:56:18.47#ibcon#about to read 5, iclass 30, count 0 2006.257.14:56:18.47#ibcon#read 5, iclass 30, count 0 2006.257.14:56:18.47#ibcon#about to read 6, iclass 30, count 0 2006.257.14:56:18.47#ibcon#read 6, iclass 30, count 0 2006.257.14:56:18.47#ibcon#end of sib2, iclass 30, count 0 2006.257.14:56:18.47#ibcon#*after write, iclass 30, count 0 2006.257.14:56:18.47#ibcon#*before return 0, iclass 30, count 0 2006.257.14:56:18.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:18.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:18.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:56:18.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:56:18.47$vck44/valo=2,534.99 2006.257.14:56:18.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.14:56:18.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.14:56:18.47#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:18.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:18.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:18.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:18.47#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:56:18.47#ibcon#first serial, iclass 32, count 0 2006.257.14:56:18.47#ibcon#enter sib2, iclass 32, count 0 2006.257.14:56:18.47#ibcon#flushed, iclass 32, count 0 2006.257.14:56:18.47#ibcon#about to write, iclass 32, count 0 2006.257.14:56:18.47#ibcon#wrote, iclass 32, count 0 2006.257.14:56:18.47#ibcon#about to read 3, iclass 32, count 0 2006.257.14:56:18.49#ibcon#read 3, iclass 32, count 0 2006.257.14:56:18.49#ibcon#about to read 4, iclass 32, count 0 2006.257.14:56:18.49#ibcon#read 4, iclass 32, count 0 2006.257.14:56:18.49#ibcon#about to read 5, iclass 32, count 0 2006.257.14:56:18.49#ibcon#read 5, iclass 32, count 0 2006.257.14:56:18.49#ibcon#about to read 6, iclass 32, count 0 2006.257.14:56:18.49#ibcon#read 6, iclass 32, count 0 2006.257.14:56:18.49#ibcon#end of sib2, iclass 32, count 0 2006.257.14:56:18.49#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:56:18.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:56:18.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.14:56:18.49#ibcon#*before write, iclass 32, count 0 2006.257.14:56:18.49#ibcon#enter sib2, iclass 32, count 0 2006.257.14:56:18.49#ibcon#flushed, iclass 32, count 0 2006.257.14:56:18.49#ibcon#about to write, iclass 32, count 0 2006.257.14:56:18.49#ibcon#wrote, iclass 32, count 0 2006.257.14:56:18.49#ibcon#about to read 3, iclass 32, count 0 2006.257.14:56:18.53#ibcon#read 3, iclass 32, count 0 2006.257.14:56:18.53#ibcon#about to read 4, iclass 32, count 0 2006.257.14:56:18.53#ibcon#read 4, iclass 32, count 0 2006.257.14:56:18.53#ibcon#about to read 5, iclass 32, count 0 2006.257.14:56:18.53#ibcon#read 5, iclass 32, count 0 2006.257.14:56:18.53#ibcon#about to read 6, iclass 32, count 0 2006.257.14:56:18.53#ibcon#read 6, iclass 32, count 0 2006.257.14:56:18.53#ibcon#end of sib2, iclass 32, count 0 2006.257.14:56:18.53#ibcon#*after write, iclass 32, count 0 2006.257.14:56:18.53#ibcon#*before return 0, iclass 32, count 0 2006.257.14:56:18.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:18.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:18.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:56:18.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:56:18.53$vck44/va=2,7 2006.257.14:56:18.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.14:56:18.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.14:56:18.53#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:18.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:18.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:18.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:18.59#ibcon#enter wrdev, iclass 34, count 2 2006.257.14:56:18.59#ibcon#first serial, iclass 34, count 2 2006.257.14:56:18.59#ibcon#enter sib2, iclass 34, count 2 2006.257.14:56:18.59#ibcon#flushed, iclass 34, count 2 2006.257.14:56:18.59#ibcon#about to write, iclass 34, count 2 2006.257.14:56:18.59#ibcon#wrote, iclass 34, count 2 2006.257.14:56:18.59#ibcon#about to read 3, iclass 34, count 2 2006.257.14:56:18.61#ibcon#read 3, iclass 34, count 2 2006.257.14:56:18.61#ibcon#about to read 4, iclass 34, count 2 2006.257.14:56:18.61#ibcon#read 4, iclass 34, count 2 2006.257.14:56:18.61#ibcon#about to read 5, iclass 34, count 2 2006.257.14:56:18.61#ibcon#read 5, iclass 34, count 2 2006.257.14:56:18.61#ibcon#about to read 6, iclass 34, count 2 2006.257.14:56:18.61#ibcon#read 6, iclass 34, count 2 2006.257.14:56:18.61#ibcon#end of sib2, iclass 34, count 2 2006.257.14:56:18.61#ibcon#*mode == 0, iclass 34, count 2 2006.257.14:56:18.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.14:56:18.61#ibcon#[25=AT02-07\r\n] 2006.257.14:56:18.61#ibcon#*before write, iclass 34, count 2 2006.257.14:56:18.61#ibcon#enter sib2, iclass 34, count 2 2006.257.14:56:18.61#ibcon#flushed, iclass 34, count 2 2006.257.14:56:18.61#ibcon#about to write, iclass 34, count 2 2006.257.14:56:18.61#ibcon#wrote, iclass 34, count 2 2006.257.14:56:18.61#ibcon#about to read 3, iclass 34, count 2 2006.257.14:56:18.64#ibcon#read 3, iclass 34, count 2 2006.257.14:56:18.64#ibcon#about to read 4, iclass 34, count 2 2006.257.14:56:18.64#ibcon#read 4, iclass 34, count 2 2006.257.14:56:18.64#ibcon#about to read 5, iclass 34, count 2 2006.257.14:56:18.64#ibcon#read 5, iclass 34, count 2 2006.257.14:56:18.64#ibcon#about to read 6, iclass 34, count 2 2006.257.14:56:18.64#ibcon#read 6, iclass 34, count 2 2006.257.14:56:18.64#ibcon#end of sib2, iclass 34, count 2 2006.257.14:56:18.64#ibcon#*after write, iclass 34, count 2 2006.257.14:56:18.64#ibcon#*before return 0, iclass 34, count 2 2006.257.14:56:18.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:18.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:18.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.14:56:18.64#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:18.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:18.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:18.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:18.76#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:56:18.76#ibcon#first serial, iclass 34, count 0 2006.257.14:56:18.76#ibcon#enter sib2, iclass 34, count 0 2006.257.14:56:18.76#ibcon#flushed, iclass 34, count 0 2006.257.14:56:18.76#ibcon#about to write, iclass 34, count 0 2006.257.14:56:18.76#ibcon#wrote, iclass 34, count 0 2006.257.14:56:18.76#ibcon#about to read 3, iclass 34, count 0 2006.257.14:56:18.78#ibcon#read 3, iclass 34, count 0 2006.257.14:56:18.78#ibcon#about to read 4, iclass 34, count 0 2006.257.14:56:18.78#ibcon#read 4, iclass 34, count 0 2006.257.14:56:18.78#ibcon#about to read 5, iclass 34, count 0 2006.257.14:56:18.78#ibcon#read 5, iclass 34, count 0 2006.257.14:56:18.78#ibcon#about to read 6, iclass 34, count 0 2006.257.14:56:18.78#ibcon#read 6, iclass 34, count 0 2006.257.14:56:18.78#ibcon#end of sib2, iclass 34, count 0 2006.257.14:56:18.78#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:56:18.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:56:18.78#ibcon#[25=USB\r\n] 2006.257.14:56:18.78#ibcon#*before write, iclass 34, count 0 2006.257.14:56:18.78#ibcon#enter sib2, iclass 34, count 0 2006.257.14:56:18.78#ibcon#flushed, iclass 34, count 0 2006.257.14:56:18.78#ibcon#about to write, iclass 34, count 0 2006.257.14:56:18.78#ibcon#wrote, iclass 34, count 0 2006.257.14:56:18.78#ibcon#about to read 3, iclass 34, count 0 2006.257.14:56:18.81#ibcon#read 3, iclass 34, count 0 2006.257.14:56:18.81#ibcon#about to read 4, iclass 34, count 0 2006.257.14:56:18.81#ibcon#read 4, iclass 34, count 0 2006.257.14:56:18.81#ibcon#about to read 5, iclass 34, count 0 2006.257.14:56:18.81#ibcon#read 5, iclass 34, count 0 2006.257.14:56:18.81#ibcon#about to read 6, iclass 34, count 0 2006.257.14:56:18.81#ibcon#read 6, iclass 34, count 0 2006.257.14:56:18.81#ibcon#end of sib2, iclass 34, count 0 2006.257.14:56:18.81#ibcon#*after write, iclass 34, count 0 2006.257.14:56:18.81#ibcon#*before return 0, iclass 34, count 0 2006.257.14:56:18.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:18.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:18.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:56:18.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:56:18.81$vck44/valo=3,564.99 2006.257.14:56:18.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.14:56:18.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.14:56:18.81#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:18.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:18.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:18.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:18.81#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:56:18.81#ibcon#first serial, iclass 36, count 0 2006.257.14:56:18.81#ibcon#enter sib2, iclass 36, count 0 2006.257.14:56:18.81#ibcon#flushed, iclass 36, count 0 2006.257.14:56:18.81#ibcon#about to write, iclass 36, count 0 2006.257.14:56:18.81#ibcon#wrote, iclass 36, count 0 2006.257.14:56:18.81#ibcon#about to read 3, iclass 36, count 0 2006.257.14:56:18.83#ibcon#read 3, iclass 36, count 0 2006.257.14:56:18.83#ibcon#about to read 4, iclass 36, count 0 2006.257.14:56:18.83#ibcon#read 4, iclass 36, count 0 2006.257.14:56:18.83#ibcon#about to read 5, iclass 36, count 0 2006.257.14:56:18.83#ibcon#read 5, iclass 36, count 0 2006.257.14:56:18.83#ibcon#about to read 6, iclass 36, count 0 2006.257.14:56:18.83#ibcon#read 6, iclass 36, count 0 2006.257.14:56:18.83#ibcon#end of sib2, iclass 36, count 0 2006.257.14:56:18.83#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:56:18.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:56:18.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.14:56:18.83#ibcon#*before write, iclass 36, count 0 2006.257.14:56:18.83#ibcon#enter sib2, iclass 36, count 0 2006.257.14:56:18.83#ibcon#flushed, iclass 36, count 0 2006.257.14:56:18.83#ibcon#about to write, iclass 36, count 0 2006.257.14:56:18.83#ibcon#wrote, iclass 36, count 0 2006.257.14:56:18.83#ibcon#about to read 3, iclass 36, count 0 2006.257.14:56:18.87#ibcon#read 3, iclass 36, count 0 2006.257.14:56:18.87#ibcon#about to read 4, iclass 36, count 0 2006.257.14:56:18.87#ibcon#read 4, iclass 36, count 0 2006.257.14:56:18.87#ibcon#about to read 5, iclass 36, count 0 2006.257.14:56:18.87#ibcon#read 5, iclass 36, count 0 2006.257.14:56:18.87#ibcon#about to read 6, iclass 36, count 0 2006.257.14:56:18.87#ibcon#read 6, iclass 36, count 0 2006.257.14:56:18.87#ibcon#end of sib2, iclass 36, count 0 2006.257.14:56:18.87#ibcon#*after write, iclass 36, count 0 2006.257.14:56:18.87#ibcon#*before return 0, iclass 36, count 0 2006.257.14:56:18.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:18.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:18.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:56:18.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:56:18.87$vck44/va=3,8 2006.257.14:56:18.87#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.14:56:18.87#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.14:56:18.87#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:18.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:18.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:18.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:18.93#ibcon#enter wrdev, iclass 38, count 2 2006.257.14:56:18.93#ibcon#first serial, iclass 38, count 2 2006.257.14:56:18.93#ibcon#enter sib2, iclass 38, count 2 2006.257.14:56:18.93#ibcon#flushed, iclass 38, count 2 2006.257.14:56:18.93#ibcon#about to write, iclass 38, count 2 2006.257.14:56:18.93#ibcon#wrote, iclass 38, count 2 2006.257.14:56:18.93#ibcon#about to read 3, iclass 38, count 2 2006.257.14:56:18.95#ibcon#read 3, iclass 38, count 2 2006.257.14:56:18.95#ibcon#about to read 4, iclass 38, count 2 2006.257.14:56:18.95#ibcon#read 4, iclass 38, count 2 2006.257.14:56:18.95#ibcon#about to read 5, iclass 38, count 2 2006.257.14:56:18.95#ibcon#read 5, iclass 38, count 2 2006.257.14:56:18.95#ibcon#about to read 6, iclass 38, count 2 2006.257.14:56:18.95#ibcon#read 6, iclass 38, count 2 2006.257.14:56:18.95#ibcon#end of sib2, iclass 38, count 2 2006.257.14:56:18.95#ibcon#*mode == 0, iclass 38, count 2 2006.257.14:56:18.95#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.14:56:18.95#ibcon#[25=AT03-08\r\n] 2006.257.14:56:18.95#ibcon#*before write, iclass 38, count 2 2006.257.14:56:18.95#ibcon#enter sib2, iclass 38, count 2 2006.257.14:56:18.95#ibcon#flushed, iclass 38, count 2 2006.257.14:56:18.95#ibcon#about to write, iclass 38, count 2 2006.257.14:56:18.95#ibcon#wrote, iclass 38, count 2 2006.257.14:56:18.95#ibcon#about to read 3, iclass 38, count 2 2006.257.14:56:18.98#ibcon#read 3, iclass 38, count 2 2006.257.14:56:18.98#ibcon#about to read 4, iclass 38, count 2 2006.257.14:56:18.98#ibcon#read 4, iclass 38, count 2 2006.257.14:56:18.98#ibcon#about to read 5, iclass 38, count 2 2006.257.14:56:18.98#ibcon#read 5, iclass 38, count 2 2006.257.14:56:18.98#ibcon#about to read 6, iclass 38, count 2 2006.257.14:56:18.98#ibcon#read 6, iclass 38, count 2 2006.257.14:56:18.98#ibcon#end of sib2, iclass 38, count 2 2006.257.14:56:18.98#ibcon#*after write, iclass 38, count 2 2006.257.14:56:18.98#ibcon#*before return 0, iclass 38, count 2 2006.257.14:56:18.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:18.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:18.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.14:56:18.98#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:18.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:19.10#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:19.10#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:19.10#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:56:19.10#ibcon#first serial, iclass 38, count 0 2006.257.14:56:19.10#ibcon#enter sib2, iclass 38, count 0 2006.257.14:56:19.10#ibcon#flushed, iclass 38, count 0 2006.257.14:56:19.10#ibcon#about to write, iclass 38, count 0 2006.257.14:56:19.10#ibcon#wrote, iclass 38, count 0 2006.257.14:56:19.10#ibcon#about to read 3, iclass 38, count 0 2006.257.14:56:19.12#ibcon#read 3, iclass 38, count 0 2006.257.14:56:19.12#ibcon#about to read 4, iclass 38, count 0 2006.257.14:56:19.12#ibcon#read 4, iclass 38, count 0 2006.257.14:56:19.12#ibcon#about to read 5, iclass 38, count 0 2006.257.14:56:19.12#ibcon#read 5, iclass 38, count 0 2006.257.14:56:19.12#ibcon#about to read 6, iclass 38, count 0 2006.257.14:56:19.12#ibcon#read 6, iclass 38, count 0 2006.257.14:56:19.12#ibcon#end of sib2, iclass 38, count 0 2006.257.14:56:19.12#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:56:19.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:56:19.12#ibcon#[25=USB\r\n] 2006.257.14:56:19.12#ibcon#*before write, iclass 38, count 0 2006.257.14:56:19.12#ibcon#enter sib2, iclass 38, count 0 2006.257.14:56:19.12#ibcon#flushed, iclass 38, count 0 2006.257.14:56:19.12#ibcon#about to write, iclass 38, count 0 2006.257.14:56:19.12#ibcon#wrote, iclass 38, count 0 2006.257.14:56:19.12#ibcon#about to read 3, iclass 38, count 0 2006.257.14:56:19.15#ibcon#read 3, iclass 38, count 0 2006.257.14:56:19.15#ibcon#about to read 4, iclass 38, count 0 2006.257.14:56:19.15#ibcon#read 4, iclass 38, count 0 2006.257.14:56:19.15#ibcon#about to read 5, iclass 38, count 0 2006.257.14:56:19.15#ibcon#read 5, iclass 38, count 0 2006.257.14:56:19.15#ibcon#about to read 6, iclass 38, count 0 2006.257.14:56:19.15#ibcon#read 6, iclass 38, count 0 2006.257.14:56:19.15#ibcon#end of sib2, iclass 38, count 0 2006.257.14:56:19.15#ibcon#*after write, iclass 38, count 0 2006.257.14:56:19.15#ibcon#*before return 0, iclass 38, count 0 2006.257.14:56:19.15#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:19.15#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:19.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:56:19.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:56:19.15$vck44/valo=4,624.99 2006.257.14:56:19.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.14:56:19.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.14:56:19.15#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:19.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:19.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:19.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:19.15#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:56:19.15#ibcon#first serial, iclass 40, count 0 2006.257.14:56:19.15#ibcon#enter sib2, iclass 40, count 0 2006.257.14:56:19.15#ibcon#flushed, iclass 40, count 0 2006.257.14:56:19.15#ibcon#about to write, iclass 40, count 0 2006.257.14:56:19.15#ibcon#wrote, iclass 40, count 0 2006.257.14:56:19.15#ibcon#about to read 3, iclass 40, count 0 2006.257.14:56:19.17#ibcon#read 3, iclass 40, count 0 2006.257.14:56:19.17#ibcon#about to read 4, iclass 40, count 0 2006.257.14:56:19.17#ibcon#read 4, iclass 40, count 0 2006.257.14:56:19.17#ibcon#about to read 5, iclass 40, count 0 2006.257.14:56:19.17#ibcon#read 5, iclass 40, count 0 2006.257.14:56:19.17#ibcon#about to read 6, iclass 40, count 0 2006.257.14:56:19.17#ibcon#read 6, iclass 40, count 0 2006.257.14:56:19.17#ibcon#end of sib2, iclass 40, count 0 2006.257.14:56:19.17#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:56:19.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:56:19.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.14:56:19.17#ibcon#*before write, iclass 40, count 0 2006.257.14:56:19.17#ibcon#enter sib2, iclass 40, count 0 2006.257.14:56:19.17#ibcon#flushed, iclass 40, count 0 2006.257.14:56:19.17#ibcon#about to write, iclass 40, count 0 2006.257.14:56:19.17#ibcon#wrote, iclass 40, count 0 2006.257.14:56:19.17#ibcon#about to read 3, iclass 40, count 0 2006.257.14:56:19.21#ibcon#read 3, iclass 40, count 0 2006.257.14:56:19.21#ibcon#about to read 4, iclass 40, count 0 2006.257.14:56:19.21#ibcon#read 4, iclass 40, count 0 2006.257.14:56:19.21#ibcon#about to read 5, iclass 40, count 0 2006.257.14:56:19.21#ibcon#read 5, iclass 40, count 0 2006.257.14:56:19.21#ibcon#about to read 6, iclass 40, count 0 2006.257.14:56:19.21#ibcon#read 6, iclass 40, count 0 2006.257.14:56:19.21#ibcon#end of sib2, iclass 40, count 0 2006.257.14:56:19.21#ibcon#*after write, iclass 40, count 0 2006.257.14:56:19.21#ibcon#*before return 0, iclass 40, count 0 2006.257.14:56:19.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:19.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:19.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:56:19.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:56:19.21$vck44/va=4,7 2006.257.14:56:19.21#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.14:56:19.21#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.14:56:19.21#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:19.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:19.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:19.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:19.27#ibcon#enter wrdev, iclass 4, count 2 2006.257.14:56:19.27#ibcon#first serial, iclass 4, count 2 2006.257.14:56:19.27#ibcon#enter sib2, iclass 4, count 2 2006.257.14:56:19.27#ibcon#flushed, iclass 4, count 2 2006.257.14:56:19.27#ibcon#about to write, iclass 4, count 2 2006.257.14:56:19.27#ibcon#wrote, iclass 4, count 2 2006.257.14:56:19.27#ibcon#about to read 3, iclass 4, count 2 2006.257.14:56:19.29#ibcon#read 3, iclass 4, count 2 2006.257.14:56:19.29#ibcon#about to read 4, iclass 4, count 2 2006.257.14:56:19.29#ibcon#read 4, iclass 4, count 2 2006.257.14:56:19.29#ibcon#about to read 5, iclass 4, count 2 2006.257.14:56:19.29#ibcon#read 5, iclass 4, count 2 2006.257.14:56:19.29#ibcon#about to read 6, iclass 4, count 2 2006.257.14:56:19.29#ibcon#read 6, iclass 4, count 2 2006.257.14:56:19.29#ibcon#end of sib2, iclass 4, count 2 2006.257.14:56:19.29#ibcon#*mode == 0, iclass 4, count 2 2006.257.14:56:19.29#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.14:56:19.29#ibcon#[25=AT04-07\r\n] 2006.257.14:56:19.29#ibcon#*before write, iclass 4, count 2 2006.257.14:56:19.29#ibcon#enter sib2, iclass 4, count 2 2006.257.14:56:19.29#ibcon#flushed, iclass 4, count 2 2006.257.14:56:19.29#ibcon#about to write, iclass 4, count 2 2006.257.14:56:19.29#ibcon#wrote, iclass 4, count 2 2006.257.14:56:19.29#ibcon#about to read 3, iclass 4, count 2 2006.257.14:56:19.32#ibcon#read 3, iclass 4, count 2 2006.257.14:56:19.32#ibcon#about to read 4, iclass 4, count 2 2006.257.14:56:19.32#ibcon#read 4, iclass 4, count 2 2006.257.14:56:19.32#ibcon#about to read 5, iclass 4, count 2 2006.257.14:56:19.32#ibcon#read 5, iclass 4, count 2 2006.257.14:56:19.32#ibcon#about to read 6, iclass 4, count 2 2006.257.14:56:19.32#ibcon#read 6, iclass 4, count 2 2006.257.14:56:19.32#ibcon#end of sib2, iclass 4, count 2 2006.257.14:56:19.32#ibcon#*after write, iclass 4, count 2 2006.257.14:56:19.32#ibcon#*before return 0, iclass 4, count 2 2006.257.14:56:19.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:19.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:19.32#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.14:56:19.32#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:19.32#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:19.44#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:19.44#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:19.44#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:56:19.44#ibcon#first serial, iclass 4, count 0 2006.257.14:56:19.44#ibcon#enter sib2, iclass 4, count 0 2006.257.14:56:19.44#ibcon#flushed, iclass 4, count 0 2006.257.14:56:19.44#ibcon#about to write, iclass 4, count 0 2006.257.14:56:19.44#ibcon#wrote, iclass 4, count 0 2006.257.14:56:19.44#ibcon#about to read 3, iclass 4, count 0 2006.257.14:56:19.46#ibcon#read 3, iclass 4, count 0 2006.257.14:56:19.46#ibcon#about to read 4, iclass 4, count 0 2006.257.14:56:19.46#ibcon#read 4, iclass 4, count 0 2006.257.14:56:19.46#ibcon#about to read 5, iclass 4, count 0 2006.257.14:56:19.46#ibcon#read 5, iclass 4, count 0 2006.257.14:56:19.46#ibcon#about to read 6, iclass 4, count 0 2006.257.14:56:19.46#ibcon#read 6, iclass 4, count 0 2006.257.14:56:19.46#ibcon#end of sib2, iclass 4, count 0 2006.257.14:56:19.46#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:56:19.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:56:19.46#ibcon#[25=USB\r\n] 2006.257.14:56:19.46#ibcon#*before write, iclass 4, count 0 2006.257.14:56:19.46#ibcon#enter sib2, iclass 4, count 0 2006.257.14:56:19.46#ibcon#flushed, iclass 4, count 0 2006.257.14:56:19.46#ibcon#about to write, iclass 4, count 0 2006.257.14:56:19.46#ibcon#wrote, iclass 4, count 0 2006.257.14:56:19.46#ibcon#about to read 3, iclass 4, count 0 2006.257.14:56:19.49#ibcon#read 3, iclass 4, count 0 2006.257.14:56:19.49#ibcon#about to read 4, iclass 4, count 0 2006.257.14:56:19.49#ibcon#read 4, iclass 4, count 0 2006.257.14:56:19.49#ibcon#about to read 5, iclass 4, count 0 2006.257.14:56:19.49#ibcon#read 5, iclass 4, count 0 2006.257.14:56:19.49#ibcon#about to read 6, iclass 4, count 0 2006.257.14:56:19.49#ibcon#read 6, iclass 4, count 0 2006.257.14:56:19.49#ibcon#end of sib2, iclass 4, count 0 2006.257.14:56:19.49#ibcon#*after write, iclass 4, count 0 2006.257.14:56:19.49#ibcon#*before return 0, iclass 4, count 0 2006.257.14:56:19.49#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:19.49#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:19.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:56:19.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:56:19.49$vck44/valo=5,734.99 2006.257.14:56:19.49#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.14:56:19.49#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.14:56:19.49#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:19.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:19.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:19.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:19.49#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:56:19.49#ibcon#first serial, iclass 6, count 0 2006.257.14:56:19.49#ibcon#enter sib2, iclass 6, count 0 2006.257.14:56:19.49#ibcon#flushed, iclass 6, count 0 2006.257.14:56:19.49#ibcon#about to write, iclass 6, count 0 2006.257.14:56:19.49#ibcon#wrote, iclass 6, count 0 2006.257.14:56:19.49#ibcon#about to read 3, iclass 6, count 0 2006.257.14:56:19.51#ibcon#read 3, iclass 6, count 0 2006.257.14:56:19.51#ibcon#about to read 4, iclass 6, count 0 2006.257.14:56:19.51#ibcon#read 4, iclass 6, count 0 2006.257.14:56:19.51#ibcon#about to read 5, iclass 6, count 0 2006.257.14:56:19.51#ibcon#read 5, iclass 6, count 0 2006.257.14:56:19.51#ibcon#about to read 6, iclass 6, count 0 2006.257.14:56:19.51#ibcon#read 6, iclass 6, count 0 2006.257.14:56:19.51#ibcon#end of sib2, iclass 6, count 0 2006.257.14:56:19.51#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:56:19.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:56:19.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.14:56:19.51#ibcon#*before write, iclass 6, count 0 2006.257.14:56:19.51#ibcon#enter sib2, iclass 6, count 0 2006.257.14:56:19.51#ibcon#flushed, iclass 6, count 0 2006.257.14:56:19.51#ibcon#about to write, iclass 6, count 0 2006.257.14:56:19.51#ibcon#wrote, iclass 6, count 0 2006.257.14:56:19.51#ibcon#about to read 3, iclass 6, count 0 2006.257.14:56:19.55#ibcon#read 3, iclass 6, count 0 2006.257.14:56:19.55#ibcon#about to read 4, iclass 6, count 0 2006.257.14:56:19.55#ibcon#read 4, iclass 6, count 0 2006.257.14:56:19.55#ibcon#about to read 5, iclass 6, count 0 2006.257.14:56:19.55#ibcon#read 5, iclass 6, count 0 2006.257.14:56:19.55#ibcon#about to read 6, iclass 6, count 0 2006.257.14:56:19.55#ibcon#read 6, iclass 6, count 0 2006.257.14:56:19.55#ibcon#end of sib2, iclass 6, count 0 2006.257.14:56:19.55#ibcon#*after write, iclass 6, count 0 2006.257.14:56:19.55#ibcon#*before return 0, iclass 6, count 0 2006.257.14:56:19.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:19.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:19.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:56:19.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:56:19.55$vck44/va=5,4 2006.257.14:56:19.55#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.14:56:19.55#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.14:56:19.55#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:19.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:19.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:19.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:19.61#ibcon#enter wrdev, iclass 10, count 2 2006.257.14:56:19.61#ibcon#first serial, iclass 10, count 2 2006.257.14:56:19.61#ibcon#enter sib2, iclass 10, count 2 2006.257.14:56:19.61#ibcon#flushed, iclass 10, count 2 2006.257.14:56:19.61#ibcon#about to write, iclass 10, count 2 2006.257.14:56:19.61#ibcon#wrote, iclass 10, count 2 2006.257.14:56:19.61#ibcon#about to read 3, iclass 10, count 2 2006.257.14:56:19.63#ibcon#read 3, iclass 10, count 2 2006.257.14:56:19.63#ibcon#about to read 4, iclass 10, count 2 2006.257.14:56:19.63#ibcon#read 4, iclass 10, count 2 2006.257.14:56:19.63#ibcon#about to read 5, iclass 10, count 2 2006.257.14:56:19.63#ibcon#read 5, iclass 10, count 2 2006.257.14:56:19.63#ibcon#about to read 6, iclass 10, count 2 2006.257.14:56:19.63#ibcon#read 6, iclass 10, count 2 2006.257.14:56:19.63#ibcon#end of sib2, iclass 10, count 2 2006.257.14:56:19.63#ibcon#*mode == 0, iclass 10, count 2 2006.257.14:56:19.63#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.14:56:19.63#ibcon#[25=AT05-04\r\n] 2006.257.14:56:19.63#ibcon#*before write, iclass 10, count 2 2006.257.14:56:19.63#ibcon#enter sib2, iclass 10, count 2 2006.257.14:56:19.63#ibcon#flushed, iclass 10, count 2 2006.257.14:56:19.63#ibcon#about to write, iclass 10, count 2 2006.257.14:56:19.63#ibcon#wrote, iclass 10, count 2 2006.257.14:56:19.63#ibcon#about to read 3, iclass 10, count 2 2006.257.14:56:19.66#ibcon#read 3, iclass 10, count 2 2006.257.14:56:19.66#ibcon#about to read 4, iclass 10, count 2 2006.257.14:56:19.66#ibcon#read 4, iclass 10, count 2 2006.257.14:56:19.66#ibcon#about to read 5, iclass 10, count 2 2006.257.14:56:19.66#ibcon#read 5, iclass 10, count 2 2006.257.14:56:19.66#ibcon#about to read 6, iclass 10, count 2 2006.257.14:56:19.66#ibcon#read 6, iclass 10, count 2 2006.257.14:56:19.66#ibcon#end of sib2, iclass 10, count 2 2006.257.14:56:19.66#ibcon#*after write, iclass 10, count 2 2006.257.14:56:19.66#ibcon#*before return 0, iclass 10, count 2 2006.257.14:56:19.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:19.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:19.66#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.14:56:19.66#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:19.66#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:19.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:19.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:19.78#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:56:19.78#ibcon#first serial, iclass 10, count 0 2006.257.14:56:19.78#ibcon#enter sib2, iclass 10, count 0 2006.257.14:56:19.78#ibcon#flushed, iclass 10, count 0 2006.257.14:56:19.78#ibcon#about to write, iclass 10, count 0 2006.257.14:56:19.78#ibcon#wrote, iclass 10, count 0 2006.257.14:56:19.78#ibcon#about to read 3, iclass 10, count 0 2006.257.14:56:19.80#ibcon#read 3, iclass 10, count 0 2006.257.14:56:19.80#ibcon#about to read 4, iclass 10, count 0 2006.257.14:56:19.80#ibcon#read 4, iclass 10, count 0 2006.257.14:56:19.80#ibcon#about to read 5, iclass 10, count 0 2006.257.14:56:19.80#ibcon#read 5, iclass 10, count 0 2006.257.14:56:19.80#ibcon#about to read 6, iclass 10, count 0 2006.257.14:56:19.80#ibcon#read 6, iclass 10, count 0 2006.257.14:56:19.80#ibcon#end of sib2, iclass 10, count 0 2006.257.14:56:19.80#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:56:19.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:56:19.80#ibcon#[25=USB\r\n] 2006.257.14:56:19.80#ibcon#*before write, iclass 10, count 0 2006.257.14:56:19.80#ibcon#enter sib2, iclass 10, count 0 2006.257.14:56:19.80#ibcon#flushed, iclass 10, count 0 2006.257.14:56:19.80#ibcon#about to write, iclass 10, count 0 2006.257.14:56:19.80#ibcon#wrote, iclass 10, count 0 2006.257.14:56:19.80#ibcon#about to read 3, iclass 10, count 0 2006.257.14:56:19.83#ibcon#read 3, iclass 10, count 0 2006.257.14:56:19.83#ibcon#about to read 4, iclass 10, count 0 2006.257.14:56:19.83#ibcon#read 4, iclass 10, count 0 2006.257.14:56:19.83#ibcon#about to read 5, iclass 10, count 0 2006.257.14:56:19.83#ibcon#read 5, iclass 10, count 0 2006.257.14:56:19.83#ibcon#about to read 6, iclass 10, count 0 2006.257.14:56:19.83#ibcon#read 6, iclass 10, count 0 2006.257.14:56:19.83#ibcon#end of sib2, iclass 10, count 0 2006.257.14:56:19.83#ibcon#*after write, iclass 10, count 0 2006.257.14:56:19.83#ibcon#*before return 0, iclass 10, count 0 2006.257.14:56:19.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:19.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:19.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:56:19.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:56:19.83$vck44/valo=6,814.99 2006.257.14:56:19.83#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.14:56:19.83#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.14:56:19.83#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:19.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:19.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:19.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:19.83#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:56:19.83#ibcon#first serial, iclass 12, count 0 2006.257.14:56:19.83#ibcon#enter sib2, iclass 12, count 0 2006.257.14:56:19.83#ibcon#flushed, iclass 12, count 0 2006.257.14:56:19.83#ibcon#about to write, iclass 12, count 0 2006.257.14:56:19.83#ibcon#wrote, iclass 12, count 0 2006.257.14:56:19.83#ibcon#about to read 3, iclass 12, count 0 2006.257.14:56:19.85#ibcon#read 3, iclass 12, count 0 2006.257.14:56:19.85#ibcon#about to read 4, iclass 12, count 0 2006.257.14:56:19.85#ibcon#read 4, iclass 12, count 0 2006.257.14:56:19.85#ibcon#about to read 5, iclass 12, count 0 2006.257.14:56:19.85#ibcon#read 5, iclass 12, count 0 2006.257.14:56:19.85#ibcon#about to read 6, iclass 12, count 0 2006.257.14:56:19.85#ibcon#read 6, iclass 12, count 0 2006.257.14:56:19.85#ibcon#end of sib2, iclass 12, count 0 2006.257.14:56:19.85#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:56:19.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:56:19.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.14:56:19.85#ibcon#*before write, iclass 12, count 0 2006.257.14:56:19.85#ibcon#enter sib2, iclass 12, count 0 2006.257.14:56:19.85#ibcon#flushed, iclass 12, count 0 2006.257.14:56:19.85#ibcon#about to write, iclass 12, count 0 2006.257.14:56:19.85#ibcon#wrote, iclass 12, count 0 2006.257.14:56:19.85#ibcon#about to read 3, iclass 12, count 0 2006.257.14:56:19.89#ibcon#read 3, iclass 12, count 0 2006.257.14:56:19.89#ibcon#about to read 4, iclass 12, count 0 2006.257.14:56:19.89#ibcon#read 4, iclass 12, count 0 2006.257.14:56:19.89#ibcon#about to read 5, iclass 12, count 0 2006.257.14:56:19.89#ibcon#read 5, iclass 12, count 0 2006.257.14:56:19.89#ibcon#about to read 6, iclass 12, count 0 2006.257.14:56:19.89#ibcon#read 6, iclass 12, count 0 2006.257.14:56:19.89#ibcon#end of sib2, iclass 12, count 0 2006.257.14:56:19.89#ibcon#*after write, iclass 12, count 0 2006.257.14:56:19.89#ibcon#*before return 0, iclass 12, count 0 2006.257.14:56:19.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:19.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:19.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:56:19.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:56:19.89$vck44/va=6,4 2006.257.14:56:19.89#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.14:56:19.89#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.14:56:19.89#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:19.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:19.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:19.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:19.95#ibcon#enter wrdev, iclass 14, count 2 2006.257.14:56:19.95#ibcon#first serial, iclass 14, count 2 2006.257.14:56:19.95#ibcon#enter sib2, iclass 14, count 2 2006.257.14:56:19.95#ibcon#flushed, iclass 14, count 2 2006.257.14:56:19.95#ibcon#about to write, iclass 14, count 2 2006.257.14:56:19.95#ibcon#wrote, iclass 14, count 2 2006.257.14:56:19.95#ibcon#about to read 3, iclass 14, count 2 2006.257.14:56:19.97#ibcon#read 3, iclass 14, count 2 2006.257.14:56:19.97#ibcon#about to read 4, iclass 14, count 2 2006.257.14:56:19.97#ibcon#read 4, iclass 14, count 2 2006.257.14:56:19.97#ibcon#about to read 5, iclass 14, count 2 2006.257.14:56:19.97#ibcon#read 5, iclass 14, count 2 2006.257.14:56:19.97#ibcon#about to read 6, iclass 14, count 2 2006.257.14:56:19.97#ibcon#read 6, iclass 14, count 2 2006.257.14:56:19.97#ibcon#end of sib2, iclass 14, count 2 2006.257.14:56:19.97#ibcon#*mode == 0, iclass 14, count 2 2006.257.14:56:19.97#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.14:56:19.97#ibcon#[25=AT06-04\r\n] 2006.257.14:56:19.97#ibcon#*before write, iclass 14, count 2 2006.257.14:56:19.97#ibcon#enter sib2, iclass 14, count 2 2006.257.14:56:19.97#ibcon#flushed, iclass 14, count 2 2006.257.14:56:19.97#ibcon#about to write, iclass 14, count 2 2006.257.14:56:19.97#ibcon#wrote, iclass 14, count 2 2006.257.14:56:19.97#ibcon#about to read 3, iclass 14, count 2 2006.257.14:56:20.00#ibcon#read 3, iclass 14, count 2 2006.257.14:56:20.00#ibcon#about to read 4, iclass 14, count 2 2006.257.14:56:20.00#ibcon#read 4, iclass 14, count 2 2006.257.14:56:20.00#ibcon#about to read 5, iclass 14, count 2 2006.257.14:56:20.00#ibcon#read 5, iclass 14, count 2 2006.257.14:56:20.00#ibcon#about to read 6, iclass 14, count 2 2006.257.14:56:20.00#ibcon#read 6, iclass 14, count 2 2006.257.14:56:20.00#ibcon#end of sib2, iclass 14, count 2 2006.257.14:56:20.00#ibcon#*after write, iclass 14, count 2 2006.257.14:56:20.00#ibcon#*before return 0, iclass 14, count 2 2006.257.14:56:20.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:20.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:20.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.14:56:20.00#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:20.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:20.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:20.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:20.12#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:56:20.12#ibcon#first serial, iclass 14, count 0 2006.257.14:56:20.12#ibcon#enter sib2, iclass 14, count 0 2006.257.14:56:20.12#ibcon#flushed, iclass 14, count 0 2006.257.14:56:20.12#ibcon#about to write, iclass 14, count 0 2006.257.14:56:20.12#ibcon#wrote, iclass 14, count 0 2006.257.14:56:20.12#ibcon#about to read 3, iclass 14, count 0 2006.257.14:56:20.14#ibcon#read 3, iclass 14, count 0 2006.257.14:56:20.14#ibcon#about to read 4, iclass 14, count 0 2006.257.14:56:20.14#ibcon#read 4, iclass 14, count 0 2006.257.14:56:20.14#ibcon#about to read 5, iclass 14, count 0 2006.257.14:56:20.14#ibcon#read 5, iclass 14, count 0 2006.257.14:56:20.14#ibcon#about to read 6, iclass 14, count 0 2006.257.14:56:20.14#ibcon#read 6, iclass 14, count 0 2006.257.14:56:20.14#ibcon#end of sib2, iclass 14, count 0 2006.257.14:56:20.14#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:56:20.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:56:20.14#ibcon#[25=USB\r\n] 2006.257.14:56:20.14#ibcon#*before write, iclass 14, count 0 2006.257.14:56:20.14#ibcon#enter sib2, iclass 14, count 0 2006.257.14:56:20.14#ibcon#flushed, iclass 14, count 0 2006.257.14:56:20.14#ibcon#about to write, iclass 14, count 0 2006.257.14:56:20.14#ibcon#wrote, iclass 14, count 0 2006.257.14:56:20.14#ibcon#about to read 3, iclass 14, count 0 2006.257.14:56:20.17#ibcon#read 3, iclass 14, count 0 2006.257.14:56:20.17#ibcon#about to read 4, iclass 14, count 0 2006.257.14:56:20.17#ibcon#read 4, iclass 14, count 0 2006.257.14:56:20.17#ibcon#about to read 5, iclass 14, count 0 2006.257.14:56:20.17#ibcon#read 5, iclass 14, count 0 2006.257.14:56:20.17#ibcon#about to read 6, iclass 14, count 0 2006.257.14:56:20.17#ibcon#read 6, iclass 14, count 0 2006.257.14:56:20.17#ibcon#end of sib2, iclass 14, count 0 2006.257.14:56:20.17#ibcon#*after write, iclass 14, count 0 2006.257.14:56:20.17#ibcon#*before return 0, iclass 14, count 0 2006.257.14:56:20.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:20.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:20.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:56:20.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:56:20.17$vck44/valo=7,864.99 2006.257.14:56:20.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.14:56:20.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.14:56:20.17#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:20.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:20.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:20.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:20.17#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:56:20.17#ibcon#first serial, iclass 16, count 0 2006.257.14:56:20.17#ibcon#enter sib2, iclass 16, count 0 2006.257.14:56:20.17#ibcon#flushed, iclass 16, count 0 2006.257.14:56:20.17#ibcon#about to write, iclass 16, count 0 2006.257.14:56:20.17#ibcon#wrote, iclass 16, count 0 2006.257.14:56:20.17#ibcon#about to read 3, iclass 16, count 0 2006.257.14:56:20.19#ibcon#read 3, iclass 16, count 0 2006.257.14:56:20.19#ibcon#about to read 4, iclass 16, count 0 2006.257.14:56:20.19#ibcon#read 4, iclass 16, count 0 2006.257.14:56:20.19#ibcon#about to read 5, iclass 16, count 0 2006.257.14:56:20.19#ibcon#read 5, iclass 16, count 0 2006.257.14:56:20.19#ibcon#about to read 6, iclass 16, count 0 2006.257.14:56:20.19#ibcon#read 6, iclass 16, count 0 2006.257.14:56:20.19#ibcon#end of sib2, iclass 16, count 0 2006.257.14:56:20.19#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:56:20.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:56:20.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.14:56:20.19#ibcon#*before write, iclass 16, count 0 2006.257.14:56:20.19#ibcon#enter sib2, iclass 16, count 0 2006.257.14:56:20.19#ibcon#flushed, iclass 16, count 0 2006.257.14:56:20.19#ibcon#about to write, iclass 16, count 0 2006.257.14:56:20.19#ibcon#wrote, iclass 16, count 0 2006.257.14:56:20.19#ibcon#about to read 3, iclass 16, count 0 2006.257.14:56:20.23#ibcon#read 3, iclass 16, count 0 2006.257.14:56:20.23#ibcon#about to read 4, iclass 16, count 0 2006.257.14:56:20.23#ibcon#read 4, iclass 16, count 0 2006.257.14:56:20.23#ibcon#about to read 5, iclass 16, count 0 2006.257.14:56:20.23#ibcon#read 5, iclass 16, count 0 2006.257.14:56:20.23#ibcon#about to read 6, iclass 16, count 0 2006.257.14:56:20.23#ibcon#read 6, iclass 16, count 0 2006.257.14:56:20.23#ibcon#end of sib2, iclass 16, count 0 2006.257.14:56:20.23#ibcon#*after write, iclass 16, count 0 2006.257.14:56:20.23#ibcon#*before return 0, iclass 16, count 0 2006.257.14:56:20.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:20.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:20.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:56:20.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:56:20.23$vck44/va=7,4 2006.257.14:56:20.23#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.14:56:20.23#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.14:56:20.23#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:20.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:56:20.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:56:20.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:56:20.29#ibcon#enter wrdev, iclass 18, count 2 2006.257.14:56:20.29#ibcon#first serial, iclass 18, count 2 2006.257.14:56:20.29#ibcon#enter sib2, iclass 18, count 2 2006.257.14:56:20.29#ibcon#flushed, iclass 18, count 2 2006.257.14:56:20.29#ibcon#about to write, iclass 18, count 2 2006.257.14:56:20.29#ibcon#wrote, iclass 18, count 2 2006.257.14:56:20.29#ibcon#about to read 3, iclass 18, count 2 2006.257.14:56:20.31#ibcon#read 3, iclass 18, count 2 2006.257.14:56:20.31#ibcon#about to read 4, iclass 18, count 2 2006.257.14:56:20.31#ibcon#read 4, iclass 18, count 2 2006.257.14:56:20.31#ibcon#about to read 5, iclass 18, count 2 2006.257.14:56:20.31#ibcon#read 5, iclass 18, count 2 2006.257.14:56:20.31#ibcon#about to read 6, iclass 18, count 2 2006.257.14:56:20.31#ibcon#read 6, iclass 18, count 2 2006.257.14:56:20.31#ibcon#end of sib2, iclass 18, count 2 2006.257.14:56:20.31#ibcon#*mode == 0, iclass 18, count 2 2006.257.14:56:20.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.14:56:20.31#ibcon#[25=AT07-04\r\n] 2006.257.14:56:20.31#ibcon#*before write, iclass 18, count 2 2006.257.14:56:20.31#ibcon#enter sib2, iclass 18, count 2 2006.257.14:56:20.31#ibcon#flushed, iclass 18, count 2 2006.257.14:56:20.31#ibcon#about to write, iclass 18, count 2 2006.257.14:56:20.31#ibcon#wrote, iclass 18, count 2 2006.257.14:56:20.31#ibcon#about to read 3, iclass 18, count 2 2006.257.14:56:20.34#ibcon#read 3, iclass 18, count 2 2006.257.14:56:20.34#ibcon#about to read 4, iclass 18, count 2 2006.257.14:56:20.34#ibcon#read 4, iclass 18, count 2 2006.257.14:56:20.34#ibcon#about to read 5, iclass 18, count 2 2006.257.14:56:20.34#ibcon#read 5, iclass 18, count 2 2006.257.14:56:20.34#ibcon#about to read 6, iclass 18, count 2 2006.257.14:56:20.34#ibcon#read 6, iclass 18, count 2 2006.257.14:56:20.34#ibcon#end of sib2, iclass 18, count 2 2006.257.14:56:20.34#ibcon#*after write, iclass 18, count 2 2006.257.14:56:20.34#ibcon#*before return 0, iclass 18, count 2 2006.257.14:56:20.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:56:20.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.14:56:20.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.14:56:20.34#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:20.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:56:20.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:56:20.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:56:20.46#ibcon#enter wrdev, iclass 18, count 0 2006.257.14:56:20.46#ibcon#first serial, iclass 18, count 0 2006.257.14:56:20.46#ibcon#enter sib2, iclass 18, count 0 2006.257.14:56:20.46#ibcon#flushed, iclass 18, count 0 2006.257.14:56:20.46#ibcon#about to write, iclass 18, count 0 2006.257.14:56:20.46#ibcon#wrote, iclass 18, count 0 2006.257.14:56:20.46#ibcon#about to read 3, iclass 18, count 0 2006.257.14:56:20.48#ibcon#read 3, iclass 18, count 0 2006.257.14:56:20.48#ibcon#about to read 4, iclass 18, count 0 2006.257.14:56:20.48#ibcon#read 4, iclass 18, count 0 2006.257.14:56:20.48#ibcon#about to read 5, iclass 18, count 0 2006.257.14:56:20.48#ibcon#read 5, iclass 18, count 0 2006.257.14:56:20.48#ibcon#about to read 6, iclass 18, count 0 2006.257.14:56:20.48#ibcon#read 6, iclass 18, count 0 2006.257.14:56:20.48#ibcon#end of sib2, iclass 18, count 0 2006.257.14:56:20.48#ibcon#*mode == 0, iclass 18, count 0 2006.257.14:56:20.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.14:56:20.48#ibcon#[25=USB\r\n] 2006.257.14:56:20.48#ibcon#*before write, iclass 18, count 0 2006.257.14:56:20.48#ibcon#enter sib2, iclass 18, count 0 2006.257.14:56:20.48#ibcon#flushed, iclass 18, count 0 2006.257.14:56:20.48#ibcon#about to write, iclass 18, count 0 2006.257.14:56:20.48#ibcon#wrote, iclass 18, count 0 2006.257.14:56:20.48#ibcon#about to read 3, iclass 18, count 0 2006.257.14:56:20.51#ibcon#read 3, iclass 18, count 0 2006.257.14:56:20.51#ibcon#about to read 4, iclass 18, count 0 2006.257.14:56:20.51#ibcon#read 4, iclass 18, count 0 2006.257.14:56:20.51#ibcon#about to read 5, iclass 18, count 0 2006.257.14:56:20.51#ibcon#read 5, iclass 18, count 0 2006.257.14:56:20.51#ibcon#about to read 6, iclass 18, count 0 2006.257.14:56:20.51#ibcon#read 6, iclass 18, count 0 2006.257.14:56:20.51#ibcon#end of sib2, iclass 18, count 0 2006.257.14:56:20.51#ibcon#*after write, iclass 18, count 0 2006.257.14:56:20.51#ibcon#*before return 0, iclass 18, count 0 2006.257.14:56:20.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:56:20.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.14:56:20.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.14:56:20.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.14:56:20.51$vck44/valo=8,884.99 2006.257.14:56:20.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.14:56:20.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.14:56:20.51#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:20.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:56:20.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:56:20.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:56:20.51#ibcon#enter wrdev, iclass 20, count 0 2006.257.14:56:20.51#ibcon#first serial, iclass 20, count 0 2006.257.14:56:20.51#ibcon#enter sib2, iclass 20, count 0 2006.257.14:56:20.51#ibcon#flushed, iclass 20, count 0 2006.257.14:56:20.51#ibcon#about to write, iclass 20, count 0 2006.257.14:56:20.51#ibcon#wrote, iclass 20, count 0 2006.257.14:56:20.51#ibcon#about to read 3, iclass 20, count 0 2006.257.14:56:20.53#ibcon#read 3, iclass 20, count 0 2006.257.14:56:20.53#ibcon#about to read 4, iclass 20, count 0 2006.257.14:56:20.53#ibcon#read 4, iclass 20, count 0 2006.257.14:56:20.53#ibcon#about to read 5, iclass 20, count 0 2006.257.14:56:20.53#ibcon#read 5, iclass 20, count 0 2006.257.14:56:20.53#ibcon#about to read 6, iclass 20, count 0 2006.257.14:56:20.53#ibcon#read 6, iclass 20, count 0 2006.257.14:56:20.53#ibcon#end of sib2, iclass 20, count 0 2006.257.14:56:20.53#ibcon#*mode == 0, iclass 20, count 0 2006.257.14:56:20.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.14:56:20.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.14:56:20.53#ibcon#*before write, iclass 20, count 0 2006.257.14:56:20.53#ibcon#enter sib2, iclass 20, count 0 2006.257.14:56:20.53#ibcon#flushed, iclass 20, count 0 2006.257.14:56:20.53#ibcon#about to write, iclass 20, count 0 2006.257.14:56:20.53#ibcon#wrote, iclass 20, count 0 2006.257.14:56:20.53#ibcon#about to read 3, iclass 20, count 0 2006.257.14:56:20.57#ibcon#read 3, iclass 20, count 0 2006.257.14:56:20.57#ibcon#about to read 4, iclass 20, count 0 2006.257.14:56:20.57#ibcon#read 4, iclass 20, count 0 2006.257.14:56:20.57#ibcon#about to read 5, iclass 20, count 0 2006.257.14:56:20.57#ibcon#read 5, iclass 20, count 0 2006.257.14:56:20.57#ibcon#about to read 6, iclass 20, count 0 2006.257.14:56:20.57#ibcon#read 6, iclass 20, count 0 2006.257.14:56:20.57#ibcon#end of sib2, iclass 20, count 0 2006.257.14:56:20.57#ibcon#*after write, iclass 20, count 0 2006.257.14:56:20.57#ibcon#*before return 0, iclass 20, count 0 2006.257.14:56:20.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:56:20.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.14:56:20.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.14:56:20.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.14:56:20.57$vck44/va=8,4 2006.257.14:56:20.57#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.14:56:20.57#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.14:56:20.57#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:20.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:56:20.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:56:20.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:56:20.63#ibcon#enter wrdev, iclass 22, count 2 2006.257.14:56:20.63#ibcon#first serial, iclass 22, count 2 2006.257.14:56:20.63#ibcon#enter sib2, iclass 22, count 2 2006.257.14:56:20.63#ibcon#flushed, iclass 22, count 2 2006.257.14:56:20.63#ibcon#about to write, iclass 22, count 2 2006.257.14:56:20.63#ibcon#wrote, iclass 22, count 2 2006.257.14:56:20.63#ibcon#about to read 3, iclass 22, count 2 2006.257.14:56:20.65#ibcon#read 3, iclass 22, count 2 2006.257.14:56:20.65#ibcon#about to read 4, iclass 22, count 2 2006.257.14:56:20.65#ibcon#read 4, iclass 22, count 2 2006.257.14:56:20.65#ibcon#about to read 5, iclass 22, count 2 2006.257.14:56:20.65#ibcon#read 5, iclass 22, count 2 2006.257.14:56:20.65#ibcon#about to read 6, iclass 22, count 2 2006.257.14:56:20.65#ibcon#read 6, iclass 22, count 2 2006.257.14:56:20.65#ibcon#end of sib2, iclass 22, count 2 2006.257.14:56:20.65#ibcon#*mode == 0, iclass 22, count 2 2006.257.14:56:20.65#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.14:56:20.65#ibcon#[25=AT08-04\r\n] 2006.257.14:56:20.65#ibcon#*before write, iclass 22, count 2 2006.257.14:56:20.65#ibcon#enter sib2, iclass 22, count 2 2006.257.14:56:20.65#ibcon#flushed, iclass 22, count 2 2006.257.14:56:20.65#ibcon#about to write, iclass 22, count 2 2006.257.14:56:20.65#ibcon#wrote, iclass 22, count 2 2006.257.14:56:20.65#ibcon#about to read 3, iclass 22, count 2 2006.257.14:56:20.68#ibcon#read 3, iclass 22, count 2 2006.257.14:56:20.68#ibcon#about to read 4, iclass 22, count 2 2006.257.14:56:20.68#ibcon#read 4, iclass 22, count 2 2006.257.14:56:20.68#ibcon#about to read 5, iclass 22, count 2 2006.257.14:56:20.68#ibcon#read 5, iclass 22, count 2 2006.257.14:56:20.68#ibcon#about to read 6, iclass 22, count 2 2006.257.14:56:20.68#ibcon#read 6, iclass 22, count 2 2006.257.14:56:20.68#ibcon#end of sib2, iclass 22, count 2 2006.257.14:56:20.68#ibcon#*after write, iclass 22, count 2 2006.257.14:56:20.68#ibcon#*before return 0, iclass 22, count 2 2006.257.14:56:20.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:56:20.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.14:56:20.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.14:56:20.68#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:20.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:56:20.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:56:20.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:56:20.80#ibcon#enter wrdev, iclass 22, count 0 2006.257.14:56:20.80#ibcon#first serial, iclass 22, count 0 2006.257.14:56:20.80#ibcon#enter sib2, iclass 22, count 0 2006.257.14:56:20.80#ibcon#flushed, iclass 22, count 0 2006.257.14:56:20.80#ibcon#about to write, iclass 22, count 0 2006.257.14:56:20.80#ibcon#wrote, iclass 22, count 0 2006.257.14:56:20.80#ibcon#about to read 3, iclass 22, count 0 2006.257.14:56:20.82#ibcon#read 3, iclass 22, count 0 2006.257.14:56:20.82#ibcon#about to read 4, iclass 22, count 0 2006.257.14:56:20.82#ibcon#read 4, iclass 22, count 0 2006.257.14:56:20.82#ibcon#about to read 5, iclass 22, count 0 2006.257.14:56:20.82#ibcon#read 5, iclass 22, count 0 2006.257.14:56:20.82#ibcon#about to read 6, iclass 22, count 0 2006.257.14:56:20.82#ibcon#read 6, iclass 22, count 0 2006.257.14:56:20.82#ibcon#end of sib2, iclass 22, count 0 2006.257.14:56:20.82#ibcon#*mode == 0, iclass 22, count 0 2006.257.14:56:20.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.14:56:20.82#ibcon#[25=USB\r\n] 2006.257.14:56:20.82#ibcon#*before write, iclass 22, count 0 2006.257.14:56:20.82#ibcon#enter sib2, iclass 22, count 0 2006.257.14:56:20.82#ibcon#flushed, iclass 22, count 0 2006.257.14:56:20.82#ibcon#about to write, iclass 22, count 0 2006.257.14:56:20.82#ibcon#wrote, iclass 22, count 0 2006.257.14:56:20.82#ibcon#about to read 3, iclass 22, count 0 2006.257.14:56:20.85#ibcon#read 3, iclass 22, count 0 2006.257.14:56:20.85#ibcon#about to read 4, iclass 22, count 0 2006.257.14:56:20.85#ibcon#read 4, iclass 22, count 0 2006.257.14:56:20.85#ibcon#about to read 5, iclass 22, count 0 2006.257.14:56:20.85#ibcon#read 5, iclass 22, count 0 2006.257.14:56:20.85#ibcon#about to read 6, iclass 22, count 0 2006.257.14:56:20.85#ibcon#read 6, iclass 22, count 0 2006.257.14:56:20.85#ibcon#end of sib2, iclass 22, count 0 2006.257.14:56:20.85#ibcon#*after write, iclass 22, count 0 2006.257.14:56:20.85#ibcon#*before return 0, iclass 22, count 0 2006.257.14:56:20.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:56:20.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.14:56:20.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.14:56:20.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.14:56:20.85$vck44/vblo=1,629.99 2006.257.14:56:20.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.14:56:20.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.14:56:20.85#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:20.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:20.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:20.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:20.85#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:56:20.85#ibcon#first serial, iclass 24, count 0 2006.257.14:56:20.85#ibcon#enter sib2, iclass 24, count 0 2006.257.14:56:20.85#ibcon#flushed, iclass 24, count 0 2006.257.14:56:20.85#ibcon#about to write, iclass 24, count 0 2006.257.14:56:20.85#ibcon#wrote, iclass 24, count 0 2006.257.14:56:20.85#ibcon#about to read 3, iclass 24, count 0 2006.257.14:56:20.87#ibcon#read 3, iclass 24, count 0 2006.257.14:56:20.87#ibcon#about to read 4, iclass 24, count 0 2006.257.14:56:20.87#ibcon#read 4, iclass 24, count 0 2006.257.14:56:20.87#ibcon#about to read 5, iclass 24, count 0 2006.257.14:56:20.87#ibcon#read 5, iclass 24, count 0 2006.257.14:56:20.87#ibcon#about to read 6, iclass 24, count 0 2006.257.14:56:20.87#ibcon#read 6, iclass 24, count 0 2006.257.14:56:20.87#ibcon#end of sib2, iclass 24, count 0 2006.257.14:56:20.87#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:56:20.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:56:20.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.14:56:20.87#ibcon#*before write, iclass 24, count 0 2006.257.14:56:20.87#ibcon#enter sib2, iclass 24, count 0 2006.257.14:56:20.87#ibcon#flushed, iclass 24, count 0 2006.257.14:56:20.87#ibcon#about to write, iclass 24, count 0 2006.257.14:56:20.87#ibcon#wrote, iclass 24, count 0 2006.257.14:56:20.87#ibcon#about to read 3, iclass 24, count 0 2006.257.14:56:20.91#ibcon#read 3, iclass 24, count 0 2006.257.14:56:20.91#ibcon#about to read 4, iclass 24, count 0 2006.257.14:56:20.91#ibcon#read 4, iclass 24, count 0 2006.257.14:56:20.91#ibcon#about to read 5, iclass 24, count 0 2006.257.14:56:20.91#ibcon#read 5, iclass 24, count 0 2006.257.14:56:20.91#ibcon#about to read 6, iclass 24, count 0 2006.257.14:56:20.91#ibcon#read 6, iclass 24, count 0 2006.257.14:56:20.91#ibcon#end of sib2, iclass 24, count 0 2006.257.14:56:20.91#ibcon#*after write, iclass 24, count 0 2006.257.14:56:20.91#ibcon#*before return 0, iclass 24, count 0 2006.257.14:56:20.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:20.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:20.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:56:20.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:56:20.91$vck44/vb=1,4 2006.257.14:56:20.91#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.14:56:20.91#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.14:56:20.91#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:20.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:56:20.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:56:20.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:56:20.91#ibcon#enter wrdev, iclass 26, count 2 2006.257.14:56:20.91#ibcon#first serial, iclass 26, count 2 2006.257.14:56:20.91#ibcon#enter sib2, iclass 26, count 2 2006.257.14:56:20.91#ibcon#flushed, iclass 26, count 2 2006.257.14:56:20.91#ibcon#about to write, iclass 26, count 2 2006.257.14:56:20.91#ibcon#wrote, iclass 26, count 2 2006.257.14:56:20.91#ibcon#about to read 3, iclass 26, count 2 2006.257.14:56:20.93#ibcon#read 3, iclass 26, count 2 2006.257.14:56:20.93#ibcon#about to read 4, iclass 26, count 2 2006.257.14:56:20.93#ibcon#read 4, iclass 26, count 2 2006.257.14:56:20.93#ibcon#about to read 5, iclass 26, count 2 2006.257.14:56:20.93#ibcon#read 5, iclass 26, count 2 2006.257.14:56:20.93#ibcon#about to read 6, iclass 26, count 2 2006.257.14:56:20.93#ibcon#read 6, iclass 26, count 2 2006.257.14:56:20.93#ibcon#end of sib2, iclass 26, count 2 2006.257.14:56:20.93#ibcon#*mode == 0, iclass 26, count 2 2006.257.14:56:20.93#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.14:56:20.93#ibcon#[27=AT01-04\r\n] 2006.257.14:56:20.93#ibcon#*before write, iclass 26, count 2 2006.257.14:56:20.93#ibcon#enter sib2, iclass 26, count 2 2006.257.14:56:20.93#ibcon#flushed, iclass 26, count 2 2006.257.14:56:20.93#ibcon#about to write, iclass 26, count 2 2006.257.14:56:20.93#ibcon#wrote, iclass 26, count 2 2006.257.14:56:20.93#ibcon#about to read 3, iclass 26, count 2 2006.257.14:56:20.96#ibcon#read 3, iclass 26, count 2 2006.257.14:56:20.96#ibcon#about to read 4, iclass 26, count 2 2006.257.14:56:20.96#ibcon#read 4, iclass 26, count 2 2006.257.14:56:20.96#ibcon#about to read 5, iclass 26, count 2 2006.257.14:56:20.96#ibcon#read 5, iclass 26, count 2 2006.257.14:56:20.96#ibcon#about to read 6, iclass 26, count 2 2006.257.14:56:20.96#ibcon#read 6, iclass 26, count 2 2006.257.14:56:20.96#ibcon#end of sib2, iclass 26, count 2 2006.257.14:56:20.96#ibcon#*after write, iclass 26, count 2 2006.257.14:56:20.96#ibcon#*before return 0, iclass 26, count 2 2006.257.14:56:20.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:56:20.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.14:56:20.96#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.14:56:20.96#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:20.96#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:56:21.08#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:56:21.08#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:56:21.08#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:56:21.08#ibcon#first serial, iclass 26, count 0 2006.257.14:56:21.08#ibcon#enter sib2, iclass 26, count 0 2006.257.14:56:21.08#ibcon#flushed, iclass 26, count 0 2006.257.14:56:21.08#ibcon#about to write, iclass 26, count 0 2006.257.14:56:21.08#ibcon#wrote, iclass 26, count 0 2006.257.14:56:21.08#ibcon#about to read 3, iclass 26, count 0 2006.257.14:56:21.10#ibcon#read 3, iclass 26, count 0 2006.257.14:56:21.10#ibcon#about to read 4, iclass 26, count 0 2006.257.14:56:21.10#ibcon#read 4, iclass 26, count 0 2006.257.14:56:21.10#ibcon#about to read 5, iclass 26, count 0 2006.257.14:56:21.10#ibcon#read 5, iclass 26, count 0 2006.257.14:56:21.10#ibcon#about to read 6, iclass 26, count 0 2006.257.14:56:21.10#ibcon#read 6, iclass 26, count 0 2006.257.14:56:21.10#ibcon#end of sib2, iclass 26, count 0 2006.257.14:56:21.10#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:56:21.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:56:21.10#ibcon#[27=USB\r\n] 2006.257.14:56:21.10#ibcon#*before write, iclass 26, count 0 2006.257.14:56:21.10#ibcon#enter sib2, iclass 26, count 0 2006.257.14:56:21.10#ibcon#flushed, iclass 26, count 0 2006.257.14:56:21.10#ibcon#about to write, iclass 26, count 0 2006.257.14:56:21.10#ibcon#wrote, iclass 26, count 0 2006.257.14:56:21.10#ibcon#about to read 3, iclass 26, count 0 2006.257.14:56:21.13#ibcon#read 3, iclass 26, count 0 2006.257.14:56:21.13#ibcon#about to read 4, iclass 26, count 0 2006.257.14:56:21.13#ibcon#read 4, iclass 26, count 0 2006.257.14:56:21.13#ibcon#about to read 5, iclass 26, count 0 2006.257.14:56:21.13#ibcon#read 5, iclass 26, count 0 2006.257.14:56:21.13#ibcon#about to read 6, iclass 26, count 0 2006.257.14:56:21.13#ibcon#read 6, iclass 26, count 0 2006.257.14:56:21.13#ibcon#end of sib2, iclass 26, count 0 2006.257.14:56:21.13#ibcon#*after write, iclass 26, count 0 2006.257.14:56:21.13#ibcon#*before return 0, iclass 26, count 0 2006.257.14:56:21.13#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:56:21.13#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.14:56:21.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:56:21.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:56:21.13$vck44/vblo=2,634.99 2006.257.14:56:21.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.14:56:21.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.14:56:21.13#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:21.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:21.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:21.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:21.13#ibcon#enter wrdev, iclass 28, count 0 2006.257.14:56:21.13#ibcon#first serial, iclass 28, count 0 2006.257.14:56:21.13#ibcon#enter sib2, iclass 28, count 0 2006.257.14:56:21.13#ibcon#flushed, iclass 28, count 0 2006.257.14:56:21.13#ibcon#about to write, iclass 28, count 0 2006.257.14:56:21.13#ibcon#wrote, iclass 28, count 0 2006.257.14:56:21.13#ibcon#about to read 3, iclass 28, count 0 2006.257.14:56:21.15#ibcon#read 3, iclass 28, count 0 2006.257.14:56:21.15#ibcon#about to read 4, iclass 28, count 0 2006.257.14:56:21.15#ibcon#read 4, iclass 28, count 0 2006.257.14:56:21.15#ibcon#about to read 5, iclass 28, count 0 2006.257.14:56:21.15#ibcon#read 5, iclass 28, count 0 2006.257.14:56:21.15#ibcon#about to read 6, iclass 28, count 0 2006.257.14:56:21.15#ibcon#read 6, iclass 28, count 0 2006.257.14:56:21.15#ibcon#end of sib2, iclass 28, count 0 2006.257.14:56:21.15#ibcon#*mode == 0, iclass 28, count 0 2006.257.14:56:21.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.14:56:21.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.14:56:21.15#ibcon#*before write, iclass 28, count 0 2006.257.14:56:21.15#ibcon#enter sib2, iclass 28, count 0 2006.257.14:56:21.15#ibcon#flushed, iclass 28, count 0 2006.257.14:56:21.15#ibcon#about to write, iclass 28, count 0 2006.257.14:56:21.15#ibcon#wrote, iclass 28, count 0 2006.257.14:56:21.15#ibcon#about to read 3, iclass 28, count 0 2006.257.14:56:21.19#ibcon#read 3, iclass 28, count 0 2006.257.14:56:21.19#ibcon#about to read 4, iclass 28, count 0 2006.257.14:56:21.19#ibcon#read 4, iclass 28, count 0 2006.257.14:56:21.19#ibcon#about to read 5, iclass 28, count 0 2006.257.14:56:21.19#ibcon#read 5, iclass 28, count 0 2006.257.14:56:21.19#ibcon#about to read 6, iclass 28, count 0 2006.257.14:56:21.19#ibcon#read 6, iclass 28, count 0 2006.257.14:56:21.19#ibcon#end of sib2, iclass 28, count 0 2006.257.14:56:21.19#ibcon#*after write, iclass 28, count 0 2006.257.14:56:21.19#ibcon#*before return 0, iclass 28, count 0 2006.257.14:56:21.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:21.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.14:56:21.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.14:56:21.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.14:56:21.19$vck44/vb=2,5 2006.257.14:56:21.19#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.14:56:21.19#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.14:56:21.19#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:21.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:21.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:21.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:21.25#ibcon#enter wrdev, iclass 30, count 2 2006.257.14:56:21.25#ibcon#first serial, iclass 30, count 2 2006.257.14:56:21.25#ibcon#enter sib2, iclass 30, count 2 2006.257.14:56:21.25#ibcon#flushed, iclass 30, count 2 2006.257.14:56:21.25#ibcon#about to write, iclass 30, count 2 2006.257.14:56:21.25#ibcon#wrote, iclass 30, count 2 2006.257.14:56:21.25#ibcon#about to read 3, iclass 30, count 2 2006.257.14:56:21.27#ibcon#read 3, iclass 30, count 2 2006.257.14:56:21.27#ibcon#about to read 4, iclass 30, count 2 2006.257.14:56:21.27#ibcon#read 4, iclass 30, count 2 2006.257.14:56:21.27#ibcon#about to read 5, iclass 30, count 2 2006.257.14:56:21.27#ibcon#read 5, iclass 30, count 2 2006.257.14:56:21.27#ibcon#about to read 6, iclass 30, count 2 2006.257.14:56:21.27#ibcon#read 6, iclass 30, count 2 2006.257.14:56:21.27#ibcon#end of sib2, iclass 30, count 2 2006.257.14:56:21.27#ibcon#*mode == 0, iclass 30, count 2 2006.257.14:56:21.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.14:56:21.27#ibcon#[27=AT02-05\r\n] 2006.257.14:56:21.27#ibcon#*before write, iclass 30, count 2 2006.257.14:56:21.27#ibcon#enter sib2, iclass 30, count 2 2006.257.14:56:21.27#ibcon#flushed, iclass 30, count 2 2006.257.14:56:21.27#ibcon#about to write, iclass 30, count 2 2006.257.14:56:21.27#ibcon#wrote, iclass 30, count 2 2006.257.14:56:21.27#ibcon#about to read 3, iclass 30, count 2 2006.257.14:56:21.30#ibcon#read 3, iclass 30, count 2 2006.257.14:56:21.31#ibcon#about to read 4, iclass 30, count 2 2006.257.14:56:21.32#ibcon#read 4, iclass 30, count 2 2006.257.14:56:21.32#ibcon#about to read 5, iclass 30, count 2 2006.257.14:56:21.32#ibcon#read 5, iclass 30, count 2 2006.257.14:56:21.32#ibcon#about to read 6, iclass 30, count 2 2006.257.14:56:21.32#ibcon#read 6, iclass 30, count 2 2006.257.14:56:21.32#ibcon#end of sib2, iclass 30, count 2 2006.257.14:56:21.32#ibcon#*after write, iclass 30, count 2 2006.257.14:56:21.32#ibcon#*before return 0, iclass 30, count 2 2006.257.14:56:21.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:21.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.14:56:21.32#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.14:56:21.32#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:21.32#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:21.44#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:21.44#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:21.44#ibcon#enter wrdev, iclass 30, count 0 2006.257.14:56:21.44#ibcon#first serial, iclass 30, count 0 2006.257.14:56:21.44#ibcon#enter sib2, iclass 30, count 0 2006.257.14:56:21.44#ibcon#flushed, iclass 30, count 0 2006.257.14:56:21.44#ibcon#about to write, iclass 30, count 0 2006.257.14:56:21.44#ibcon#wrote, iclass 30, count 0 2006.257.14:56:21.44#ibcon#about to read 3, iclass 30, count 0 2006.257.14:56:21.46#ibcon#read 3, iclass 30, count 0 2006.257.14:56:21.46#ibcon#about to read 4, iclass 30, count 0 2006.257.14:56:21.46#ibcon#read 4, iclass 30, count 0 2006.257.14:56:21.46#ibcon#about to read 5, iclass 30, count 0 2006.257.14:56:21.46#ibcon#read 5, iclass 30, count 0 2006.257.14:56:21.46#ibcon#about to read 6, iclass 30, count 0 2006.257.14:56:21.46#ibcon#read 6, iclass 30, count 0 2006.257.14:56:21.46#ibcon#end of sib2, iclass 30, count 0 2006.257.14:56:21.46#ibcon#*mode == 0, iclass 30, count 0 2006.257.14:56:21.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.14:56:21.46#ibcon#[27=USB\r\n] 2006.257.14:56:21.46#ibcon#*before write, iclass 30, count 0 2006.257.14:56:21.46#ibcon#enter sib2, iclass 30, count 0 2006.257.14:56:21.46#ibcon#flushed, iclass 30, count 0 2006.257.14:56:21.46#ibcon#about to write, iclass 30, count 0 2006.257.14:56:21.46#ibcon#wrote, iclass 30, count 0 2006.257.14:56:21.46#ibcon#about to read 3, iclass 30, count 0 2006.257.14:56:21.49#ibcon#read 3, iclass 30, count 0 2006.257.14:56:21.49#ibcon#about to read 4, iclass 30, count 0 2006.257.14:56:21.49#ibcon#read 4, iclass 30, count 0 2006.257.14:56:21.49#ibcon#about to read 5, iclass 30, count 0 2006.257.14:56:21.49#ibcon#read 5, iclass 30, count 0 2006.257.14:56:21.49#ibcon#about to read 6, iclass 30, count 0 2006.257.14:56:21.49#ibcon#read 6, iclass 30, count 0 2006.257.14:56:21.49#ibcon#end of sib2, iclass 30, count 0 2006.257.14:56:21.49#ibcon#*after write, iclass 30, count 0 2006.257.14:56:21.49#ibcon#*before return 0, iclass 30, count 0 2006.257.14:56:21.49#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:21.49#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.14:56:21.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.14:56:21.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.14:56:21.49$vck44/vblo=3,649.99 2006.257.14:56:21.49#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.14:56:21.49#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.14:56:21.49#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:21.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:21.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:21.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:21.49#ibcon#enter wrdev, iclass 32, count 0 2006.257.14:56:21.49#ibcon#first serial, iclass 32, count 0 2006.257.14:56:21.49#ibcon#enter sib2, iclass 32, count 0 2006.257.14:56:21.49#ibcon#flushed, iclass 32, count 0 2006.257.14:56:21.49#ibcon#about to write, iclass 32, count 0 2006.257.14:56:21.49#ibcon#wrote, iclass 32, count 0 2006.257.14:56:21.49#ibcon#about to read 3, iclass 32, count 0 2006.257.14:56:21.51#ibcon#read 3, iclass 32, count 0 2006.257.14:56:21.51#ibcon#about to read 4, iclass 32, count 0 2006.257.14:56:21.51#ibcon#read 4, iclass 32, count 0 2006.257.14:56:21.51#ibcon#about to read 5, iclass 32, count 0 2006.257.14:56:21.51#ibcon#read 5, iclass 32, count 0 2006.257.14:56:21.51#ibcon#about to read 6, iclass 32, count 0 2006.257.14:56:21.51#ibcon#read 6, iclass 32, count 0 2006.257.14:56:21.51#ibcon#end of sib2, iclass 32, count 0 2006.257.14:56:21.51#ibcon#*mode == 0, iclass 32, count 0 2006.257.14:56:21.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.14:56:21.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.14:56:21.51#ibcon#*before write, iclass 32, count 0 2006.257.14:56:21.51#ibcon#enter sib2, iclass 32, count 0 2006.257.14:56:21.51#ibcon#flushed, iclass 32, count 0 2006.257.14:56:21.51#ibcon#about to write, iclass 32, count 0 2006.257.14:56:21.51#ibcon#wrote, iclass 32, count 0 2006.257.14:56:21.51#ibcon#about to read 3, iclass 32, count 0 2006.257.14:56:21.55#ibcon#read 3, iclass 32, count 0 2006.257.14:56:21.55#ibcon#about to read 4, iclass 32, count 0 2006.257.14:56:21.55#ibcon#read 4, iclass 32, count 0 2006.257.14:56:21.55#ibcon#about to read 5, iclass 32, count 0 2006.257.14:56:21.55#ibcon#read 5, iclass 32, count 0 2006.257.14:56:21.55#ibcon#about to read 6, iclass 32, count 0 2006.257.14:56:21.55#ibcon#read 6, iclass 32, count 0 2006.257.14:56:21.55#ibcon#end of sib2, iclass 32, count 0 2006.257.14:56:21.55#ibcon#*after write, iclass 32, count 0 2006.257.14:56:21.55#ibcon#*before return 0, iclass 32, count 0 2006.257.14:56:21.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:21.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.14:56:21.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.14:56:21.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.14:56:21.55$vck44/vb=3,4 2006.257.14:56:21.55#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.14:56:21.55#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.14:56:21.55#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:21.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:21.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:21.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:21.61#ibcon#enter wrdev, iclass 34, count 2 2006.257.14:56:21.61#ibcon#first serial, iclass 34, count 2 2006.257.14:56:21.61#ibcon#enter sib2, iclass 34, count 2 2006.257.14:56:21.61#ibcon#flushed, iclass 34, count 2 2006.257.14:56:21.61#ibcon#about to write, iclass 34, count 2 2006.257.14:56:21.61#ibcon#wrote, iclass 34, count 2 2006.257.14:56:21.61#ibcon#about to read 3, iclass 34, count 2 2006.257.14:56:21.63#ibcon#read 3, iclass 34, count 2 2006.257.14:56:21.63#ibcon#about to read 4, iclass 34, count 2 2006.257.14:56:21.63#ibcon#read 4, iclass 34, count 2 2006.257.14:56:21.63#ibcon#about to read 5, iclass 34, count 2 2006.257.14:56:21.63#ibcon#read 5, iclass 34, count 2 2006.257.14:56:21.63#ibcon#about to read 6, iclass 34, count 2 2006.257.14:56:21.63#ibcon#read 6, iclass 34, count 2 2006.257.14:56:21.63#ibcon#end of sib2, iclass 34, count 2 2006.257.14:56:21.63#ibcon#*mode == 0, iclass 34, count 2 2006.257.14:56:21.63#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.14:56:21.63#ibcon#[27=AT03-04\r\n] 2006.257.14:56:21.63#ibcon#*before write, iclass 34, count 2 2006.257.14:56:21.63#ibcon#enter sib2, iclass 34, count 2 2006.257.14:56:21.63#ibcon#flushed, iclass 34, count 2 2006.257.14:56:21.63#ibcon#about to write, iclass 34, count 2 2006.257.14:56:21.63#ibcon#wrote, iclass 34, count 2 2006.257.14:56:21.63#ibcon#about to read 3, iclass 34, count 2 2006.257.14:56:21.66#ibcon#read 3, iclass 34, count 2 2006.257.14:56:21.66#ibcon#about to read 4, iclass 34, count 2 2006.257.14:56:21.66#ibcon#read 4, iclass 34, count 2 2006.257.14:56:21.66#ibcon#about to read 5, iclass 34, count 2 2006.257.14:56:21.66#ibcon#read 5, iclass 34, count 2 2006.257.14:56:21.66#ibcon#about to read 6, iclass 34, count 2 2006.257.14:56:21.66#ibcon#read 6, iclass 34, count 2 2006.257.14:56:21.66#ibcon#end of sib2, iclass 34, count 2 2006.257.14:56:21.66#ibcon#*after write, iclass 34, count 2 2006.257.14:56:21.66#ibcon#*before return 0, iclass 34, count 2 2006.257.14:56:21.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:21.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.14:56:21.66#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.14:56:21.66#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:21.66#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:21.78#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:21.78#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:21.78#ibcon#enter wrdev, iclass 34, count 0 2006.257.14:56:21.78#ibcon#first serial, iclass 34, count 0 2006.257.14:56:21.78#ibcon#enter sib2, iclass 34, count 0 2006.257.14:56:21.78#ibcon#flushed, iclass 34, count 0 2006.257.14:56:21.78#ibcon#about to write, iclass 34, count 0 2006.257.14:56:21.78#ibcon#wrote, iclass 34, count 0 2006.257.14:56:21.78#ibcon#about to read 3, iclass 34, count 0 2006.257.14:56:21.80#ibcon#read 3, iclass 34, count 0 2006.257.14:56:21.80#ibcon#about to read 4, iclass 34, count 0 2006.257.14:56:21.80#ibcon#read 4, iclass 34, count 0 2006.257.14:56:21.80#ibcon#about to read 5, iclass 34, count 0 2006.257.14:56:21.80#ibcon#read 5, iclass 34, count 0 2006.257.14:56:21.80#ibcon#about to read 6, iclass 34, count 0 2006.257.14:56:21.80#ibcon#read 6, iclass 34, count 0 2006.257.14:56:21.80#ibcon#end of sib2, iclass 34, count 0 2006.257.14:56:21.80#ibcon#*mode == 0, iclass 34, count 0 2006.257.14:56:21.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.14:56:21.80#ibcon#[27=USB\r\n] 2006.257.14:56:21.80#ibcon#*before write, iclass 34, count 0 2006.257.14:56:21.80#ibcon#enter sib2, iclass 34, count 0 2006.257.14:56:21.80#ibcon#flushed, iclass 34, count 0 2006.257.14:56:21.80#ibcon#about to write, iclass 34, count 0 2006.257.14:56:21.80#ibcon#wrote, iclass 34, count 0 2006.257.14:56:21.80#ibcon#about to read 3, iclass 34, count 0 2006.257.14:56:21.83#ibcon#read 3, iclass 34, count 0 2006.257.14:56:21.83#ibcon#about to read 4, iclass 34, count 0 2006.257.14:56:21.83#ibcon#read 4, iclass 34, count 0 2006.257.14:56:21.83#ibcon#about to read 5, iclass 34, count 0 2006.257.14:56:21.83#ibcon#read 5, iclass 34, count 0 2006.257.14:56:21.83#ibcon#about to read 6, iclass 34, count 0 2006.257.14:56:21.83#ibcon#read 6, iclass 34, count 0 2006.257.14:56:21.83#ibcon#end of sib2, iclass 34, count 0 2006.257.14:56:21.83#ibcon#*after write, iclass 34, count 0 2006.257.14:56:21.83#ibcon#*before return 0, iclass 34, count 0 2006.257.14:56:21.83#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:21.83#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.14:56:21.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.14:56:21.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.14:56:21.83$vck44/vblo=4,679.99 2006.257.14:56:21.83#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.14:56:21.83#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.14:56:21.83#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:21.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:21.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:21.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:21.83#ibcon#enter wrdev, iclass 36, count 0 2006.257.14:56:21.83#ibcon#first serial, iclass 36, count 0 2006.257.14:56:21.83#ibcon#enter sib2, iclass 36, count 0 2006.257.14:56:21.83#ibcon#flushed, iclass 36, count 0 2006.257.14:56:21.83#ibcon#about to write, iclass 36, count 0 2006.257.14:56:21.83#ibcon#wrote, iclass 36, count 0 2006.257.14:56:21.83#ibcon#about to read 3, iclass 36, count 0 2006.257.14:56:21.85#ibcon#read 3, iclass 36, count 0 2006.257.14:56:21.85#ibcon#about to read 4, iclass 36, count 0 2006.257.14:56:21.85#ibcon#read 4, iclass 36, count 0 2006.257.14:56:21.85#ibcon#about to read 5, iclass 36, count 0 2006.257.14:56:21.85#ibcon#read 5, iclass 36, count 0 2006.257.14:56:21.85#ibcon#about to read 6, iclass 36, count 0 2006.257.14:56:21.85#ibcon#read 6, iclass 36, count 0 2006.257.14:56:21.85#ibcon#end of sib2, iclass 36, count 0 2006.257.14:56:21.85#ibcon#*mode == 0, iclass 36, count 0 2006.257.14:56:21.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.14:56:21.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.14:56:21.85#ibcon#*before write, iclass 36, count 0 2006.257.14:56:21.85#ibcon#enter sib2, iclass 36, count 0 2006.257.14:56:21.85#ibcon#flushed, iclass 36, count 0 2006.257.14:56:21.85#ibcon#about to write, iclass 36, count 0 2006.257.14:56:21.85#ibcon#wrote, iclass 36, count 0 2006.257.14:56:21.85#ibcon#about to read 3, iclass 36, count 0 2006.257.14:56:21.89#ibcon#read 3, iclass 36, count 0 2006.257.14:56:21.89#ibcon#about to read 4, iclass 36, count 0 2006.257.14:56:21.89#ibcon#read 4, iclass 36, count 0 2006.257.14:56:21.89#ibcon#about to read 5, iclass 36, count 0 2006.257.14:56:21.89#ibcon#read 5, iclass 36, count 0 2006.257.14:56:21.89#ibcon#about to read 6, iclass 36, count 0 2006.257.14:56:21.89#ibcon#read 6, iclass 36, count 0 2006.257.14:56:21.89#ibcon#end of sib2, iclass 36, count 0 2006.257.14:56:21.89#ibcon#*after write, iclass 36, count 0 2006.257.14:56:21.89#ibcon#*before return 0, iclass 36, count 0 2006.257.14:56:21.89#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:21.89#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.14:56:21.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.14:56:21.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.14:56:21.89$vck44/vb=4,5 2006.257.14:56:21.89#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.14:56:21.89#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.14:56:21.89#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:21.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:21.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:21.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:21.95#ibcon#enter wrdev, iclass 38, count 2 2006.257.14:56:21.95#ibcon#first serial, iclass 38, count 2 2006.257.14:56:21.95#ibcon#enter sib2, iclass 38, count 2 2006.257.14:56:21.95#ibcon#flushed, iclass 38, count 2 2006.257.14:56:21.95#ibcon#about to write, iclass 38, count 2 2006.257.14:56:21.95#ibcon#wrote, iclass 38, count 2 2006.257.14:56:21.95#ibcon#about to read 3, iclass 38, count 2 2006.257.14:56:21.97#ibcon#read 3, iclass 38, count 2 2006.257.14:56:21.97#ibcon#about to read 4, iclass 38, count 2 2006.257.14:56:21.97#ibcon#read 4, iclass 38, count 2 2006.257.14:56:21.97#ibcon#about to read 5, iclass 38, count 2 2006.257.14:56:21.97#ibcon#read 5, iclass 38, count 2 2006.257.14:56:21.97#ibcon#about to read 6, iclass 38, count 2 2006.257.14:56:21.97#ibcon#read 6, iclass 38, count 2 2006.257.14:56:21.97#ibcon#end of sib2, iclass 38, count 2 2006.257.14:56:21.97#ibcon#*mode == 0, iclass 38, count 2 2006.257.14:56:21.97#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.14:56:21.97#ibcon#[27=AT04-05\r\n] 2006.257.14:56:21.97#ibcon#*before write, iclass 38, count 2 2006.257.14:56:21.97#ibcon#enter sib2, iclass 38, count 2 2006.257.14:56:21.97#ibcon#flushed, iclass 38, count 2 2006.257.14:56:21.97#ibcon#about to write, iclass 38, count 2 2006.257.14:56:21.97#ibcon#wrote, iclass 38, count 2 2006.257.14:56:21.97#ibcon#about to read 3, iclass 38, count 2 2006.257.14:56:22.00#ibcon#read 3, iclass 38, count 2 2006.257.14:56:22.00#ibcon#about to read 4, iclass 38, count 2 2006.257.14:56:22.00#ibcon#read 4, iclass 38, count 2 2006.257.14:56:22.00#ibcon#about to read 5, iclass 38, count 2 2006.257.14:56:22.00#ibcon#read 5, iclass 38, count 2 2006.257.14:56:22.00#ibcon#about to read 6, iclass 38, count 2 2006.257.14:56:22.00#ibcon#read 6, iclass 38, count 2 2006.257.14:56:22.00#ibcon#end of sib2, iclass 38, count 2 2006.257.14:56:22.00#ibcon#*after write, iclass 38, count 2 2006.257.14:56:22.00#ibcon#*before return 0, iclass 38, count 2 2006.257.14:56:22.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:22.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.14:56:22.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.14:56:22.00#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:22.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:22.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:22.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:22.12#ibcon#enter wrdev, iclass 38, count 0 2006.257.14:56:22.12#ibcon#first serial, iclass 38, count 0 2006.257.14:56:22.12#ibcon#enter sib2, iclass 38, count 0 2006.257.14:56:22.12#ibcon#flushed, iclass 38, count 0 2006.257.14:56:22.12#ibcon#about to write, iclass 38, count 0 2006.257.14:56:22.12#ibcon#wrote, iclass 38, count 0 2006.257.14:56:22.12#ibcon#about to read 3, iclass 38, count 0 2006.257.14:56:22.14#ibcon#read 3, iclass 38, count 0 2006.257.14:56:22.14#ibcon#about to read 4, iclass 38, count 0 2006.257.14:56:22.14#ibcon#read 4, iclass 38, count 0 2006.257.14:56:22.14#ibcon#about to read 5, iclass 38, count 0 2006.257.14:56:22.14#ibcon#read 5, iclass 38, count 0 2006.257.14:56:22.14#ibcon#about to read 6, iclass 38, count 0 2006.257.14:56:22.14#ibcon#read 6, iclass 38, count 0 2006.257.14:56:22.14#ibcon#end of sib2, iclass 38, count 0 2006.257.14:56:22.14#ibcon#*mode == 0, iclass 38, count 0 2006.257.14:56:22.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.14:56:22.14#ibcon#[27=USB\r\n] 2006.257.14:56:22.14#ibcon#*before write, iclass 38, count 0 2006.257.14:56:22.14#ibcon#enter sib2, iclass 38, count 0 2006.257.14:56:22.14#ibcon#flushed, iclass 38, count 0 2006.257.14:56:22.14#ibcon#about to write, iclass 38, count 0 2006.257.14:56:22.14#ibcon#wrote, iclass 38, count 0 2006.257.14:56:22.14#ibcon#about to read 3, iclass 38, count 0 2006.257.14:56:22.17#ibcon#read 3, iclass 38, count 0 2006.257.14:56:22.17#ibcon#about to read 4, iclass 38, count 0 2006.257.14:56:22.17#ibcon#read 4, iclass 38, count 0 2006.257.14:56:22.17#ibcon#about to read 5, iclass 38, count 0 2006.257.14:56:22.17#ibcon#read 5, iclass 38, count 0 2006.257.14:56:22.17#ibcon#about to read 6, iclass 38, count 0 2006.257.14:56:22.17#ibcon#read 6, iclass 38, count 0 2006.257.14:56:22.17#ibcon#end of sib2, iclass 38, count 0 2006.257.14:56:22.17#ibcon#*after write, iclass 38, count 0 2006.257.14:56:22.17#ibcon#*before return 0, iclass 38, count 0 2006.257.14:56:22.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:22.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.14:56:22.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.14:56:22.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.14:56:22.17$vck44/vblo=5,709.99 2006.257.14:56:22.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.14:56:22.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.14:56:22.17#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:22.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:22.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:22.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:22.17#ibcon#enter wrdev, iclass 40, count 0 2006.257.14:56:22.17#ibcon#first serial, iclass 40, count 0 2006.257.14:56:22.17#ibcon#enter sib2, iclass 40, count 0 2006.257.14:56:22.17#ibcon#flushed, iclass 40, count 0 2006.257.14:56:22.17#ibcon#about to write, iclass 40, count 0 2006.257.14:56:22.17#ibcon#wrote, iclass 40, count 0 2006.257.14:56:22.17#ibcon#about to read 3, iclass 40, count 0 2006.257.14:56:22.19#ibcon#read 3, iclass 40, count 0 2006.257.14:56:22.19#ibcon#about to read 4, iclass 40, count 0 2006.257.14:56:22.19#ibcon#read 4, iclass 40, count 0 2006.257.14:56:22.19#ibcon#about to read 5, iclass 40, count 0 2006.257.14:56:22.19#ibcon#read 5, iclass 40, count 0 2006.257.14:56:22.19#ibcon#about to read 6, iclass 40, count 0 2006.257.14:56:22.19#ibcon#read 6, iclass 40, count 0 2006.257.14:56:22.19#ibcon#end of sib2, iclass 40, count 0 2006.257.14:56:22.19#ibcon#*mode == 0, iclass 40, count 0 2006.257.14:56:22.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.14:56:22.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.14:56:22.19#ibcon#*before write, iclass 40, count 0 2006.257.14:56:22.19#ibcon#enter sib2, iclass 40, count 0 2006.257.14:56:22.19#ibcon#flushed, iclass 40, count 0 2006.257.14:56:22.19#ibcon#about to write, iclass 40, count 0 2006.257.14:56:22.19#ibcon#wrote, iclass 40, count 0 2006.257.14:56:22.19#ibcon#about to read 3, iclass 40, count 0 2006.257.14:56:22.23#ibcon#read 3, iclass 40, count 0 2006.257.14:56:22.23#ibcon#about to read 4, iclass 40, count 0 2006.257.14:56:22.23#ibcon#read 4, iclass 40, count 0 2006.257.14:56:22.23#ibcon#about to read 5, iclass 40, count 0 2006.257.14:56:22.23#ibcon#read 5, iclass 40, count 0 2006.257.14:56:22.23#ibcon#about to read 6, iclass 40, count 0 2006.257.14:56:22.23#ibcon#read 6, iclass 40, count 0 2006.257.14:56:22.23#ibcon#end of sib2, iclass 40, count 0 2006.257.14:56:22.23#ibcon#*after write, iclass 40, count 0 2006.257.14:56:22.23#ibcon#*before return 0, iclass 40, count 0 2006.257.14:56:22.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:22.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.14:56:22.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.14:56:22.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.14:56:22.23$vck44/vb=5,4 2006.257.14:56:22.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.14:56:22.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.14:56:22.23#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:22.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:22.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:22.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:22.29#ibcon#enter wrdev, iclass 4, count 2 2006.257.14:56:22.29#ibcon#first serial, iclass 4, count 2 2006.257.14:56:22.29#ibcon#enter sib2, iclass 4, count 2 2006.257.14:56:22.29#ibcon#flushed, iclass 4, count 2 2006.257.14:56:22.29#ibcon#about to write, iclass 4, count 2 2006.257.14:56:22.29#ibcon#wrote, iclass 4, count 2 2006.257.14:56:22.29#ibcon#about to read 3, iclass 4, count 2 2006.257.14:56:22.31#ibcon#read 3, iclass 4, count 2 2006.257.14:56:22.31#ibcon#about to read 4, iclass 4, count 2 2006.257.14:56:22.31#ibcon#read 4, iclass 4, count 2 2006.257.14:56:22.31#ibcon#about to read 5, iclass 4, count 2 2006.257.14:56:22.31#ibcon#read 5, iclass 4, count 2 2006.257.14:56:22.31#ibcon#about to read 6, iclass 4, count 2 2006.257.14:56:22.31#ibcon#read 6, iclass 4, count 2 2006.257.14:56:22.31#ibcon#end of sib2, iclass 4, count 2 2006.257.14:56:22.31#ibcon#*mode == 0, iclass 4, count 2 2006.257.14:56:22.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.14:56:22.31#ibcon#[27=AT05-04\r\n] 2006.257.14:56:22.31#ibcon#*before write, iclass 4, count 2 2006.257.14:56:22.31#ibcon#enter sib2, iclass 4, count 2 2006.257.14:56:22.31#ibcon#flushed, iclass 4, count 2 2006.257.14:56:22.31#ibcon#about to write, iclass 4, count 2 2006.257.14:56:22.31#ibcon#wrote, iclass 4, count 2 2006.257.14:56:22.31#ibcon#about to read 3, iclass 4, count 2 2006.257.14:56:22.34#ibcon#read 3, iclass 4, count 2 2006.257.14:56:22.34#ibcon#about to read 4, iclass 4, count 2 2006.257.14:56:22.34#ibcon#read 4, iclass 4, count 2 2006.257.14:56:22.34#ibcon#about to read 5, iclass 4, count 2 2006.257.14:56:22.34#ibcon#read 5, iclass 4, count 2 2006.257.14:56:22.34#ibcon#about to read 6, iclass 4, count 2 2006.257.14:56:22.34#ibcon#read 6, iclass 4, count 2 2006.257.14:56:22.34#ibcon#end of sib2, iclass 4, count 2 2006.257.14:56:22.34#ibcon#*after write, iclass 4, count 2 2006.257.14:56:22.38#ibcon#*before return 0, iclass 4, count 2 2006.257.14:56:22.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:22.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.14:56:22.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.14:56:22.39#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:22.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:22.49#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:22.49#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:22.49#ibcon#enter wrdev, iclass 4, count 0 2006.257.14:56:22.49#ibcon#first serial, iclass 4, count 0 2006.257.14:56:22.49#ibcon#enter sib2, iclass 4, count 0 2006.257.14:56:22.49#ibcon#flushed, iclass 4, count 0 2006.257.14:56:22.49#ibcon#about to write, iclass 4, count 0 2006.257.14:56:22.49#ibcon#wrote, iclass 4, count 0 2006.257.14:56:22.49#ibcon#about to read 3, iclass 4, count 0 2006.257.14:56:22.51#ibcon#read 3, iclass 4, count 0 2006.257.14:56:22.51#ibcon#about to read 4, iclass 4, count 0 2006.257.14:56:22.51#ibcon#read 4, iclass 4, count 0 2006.257.14:56:22.51#ibcon#about to read 5, iclass 4, count 0 2006.257.14:56:22.51#ibcon#read 5, iclass 4, count 0 2006.257.14:56:22.51#ibcon#about to read 6, iclass 4, count 0 2006.257.14:56:22.51#ibcon#read 6, iclass 4, count 0 2006.257.14:56:22.51#ibcon#end of sib2, iclass 4, count 0 2006.257.14:56:22.51#ibcon#*mode == 0, iclass 4, count 0 2006.257.14:56:22.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.14:56:22.51#ibcon#[27=USB\r\n] 2006.257.14:56:22.51#ibcon#*before write, iclass 4, count 0 2006.257.14:56:22.51#ibcon#enter sib2, iclass 4, count 0 2006.257.14:56:22.51#ibcon#flushed, iclass 4, count 0 2006.257.14:56:22.51#ibcon#about to write, iclass 4, count 0 2006.257.14:56:22.51#ibcon#wrote, iclass 4, count 0 2006.257.14:56:22.51#ibcon#about to read 3, iclass 4, count 0 2006.257.14:56:22.54#ibcon#read 3, iclass 4, count 0 2006.257.14:56:22.54#ibcon#about to read 4, iclass 4, count 0 2006.257.14:56:22.54#ibcon#read 4, iclass 4, count 0 2006.257.14:56:22.54#ibcon#about to read 5, iclass 4, count 0 2006.257.14:56:22.54#ibcon#read 5, iclass 4, count 0 2006.257.14:56:22.54#ibcon#about to read 6, iclass 4, count 0 2006.257.14:56:22.54#ibcon#read 6, iclass 4, count 0 2006.257.14:56:22.54#ibcon#end of sib2, iclass 4, count 0 2006.257.14:56:22.54#ibcon#*after write, iclass 4, count 0 2006.257.14:56:22.54#ibcon#*before return 0, iclass 4, count 0 2006.257.14:56:22.54#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:22.54#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.14:56:22.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.14:56:22.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.14:56:22.54$vck44/vblo=6,719.99 2006.257.14:56:22.54#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.14:56:22.54#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.14:56:22.54#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:22.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:22.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:22.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:22.54#ibcon#enter wrdev, iclass 6, count 0 2006.257.14:56:22.54#ibcon#first serial, iclass 6, count 0 2006.257.14:56:22.54#ibcon#enter sib2, iclass 6, count 0 2006.257.14:56:22.54#ibcon#flushed, iclass 6, count 0 2006.257.14:56:22.54#ibcon#about to write, iclass 6, count 0 2006.257.14:56:22.54#ibcon#wrote, iclass 6, count 0 2006.257.14:56:22.54#ibcon#about to read 3, iclass 6, count 0 2006.257.14:56:22.56#ibcon#read 3, iclass 6, count 0 2006.257.14:56:22.56#ibcon#about to read 4, iclass 6, count 0 2006.257.14:56:22.56#ibcon#read 4, iclass 6, count 0 2006.257.14:56:22.56#ibcon#about to read 5, iclass 6, count 0 2006.257.14:56:22.56#ibcon#read 5, iclass 6, count 0 2006.257.14:56:22.56#ibcon#about to read 6, iclass 6, count 0 2006.257.14:56:22.56#ibcon#read 6, iclass 6, count 0 2006.257.14:56:22.56#ibcon#end of sib2, iclass 6, count 0 2006.257.14:56:22.56#ibcon#*mode == 0, iclass 6, count 0 2006.257.14:56:22.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.14:56:22.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.14:56:22.56#ibcon#*before write, iclass 6, count 0 2006.257.14:56:22.56#ibcon#enter sib2, iclass 6, count 0 2006.257.14:56:22.56#ibcon#flushed, iclass 6, count 0 2006.257.14:56:22.56#ibcon#about to write, iclass 6, count 0 2006.257.14:56:22.56#ibcon#wrote, iclass 6, count 0 2006.257.14:56:22.56#ibcon#about to read 3, iclass 6, count 0 2006.257.14:56:22.60#ibcon#read 3, iclass 6, count 0 2006.257.14:56:22.60#ibcon#about to read 4, iclass 6, count 0 2006.257.14:56:22.60#ibcon#read 4, iclass 6, count 0 2006.257.14:56:22.60#ibcon#about to read 5, iclass 6, count 0 2006.257.14:56:22.60#ibcon#read 5, iclass 6, count 0 2006.257.14:56:22.60#ibcon#about to read 6, iclass 6, count 0 2006.257.14:56:22.60#ibcon#read 6, iclass 6, count 0 2006.257.14:56:22.60#ibcon#end of sib2, iclass 6, count 0 2006.257.14:56:22.60#ibcon#*after write, iclass 6, count 0 2006.257.14:56:22.60#ibcon#*before return 0, iclass 6, count 0 2006.257.14:56:22.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:22.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.14:56:22.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.14:56:22.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.14:56:22.60$vck44/vb=6,4 2006.257.14:56:22.60#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.14:56:22.60#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.14:56:22.60#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:22.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:22.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:22.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:22.66#ibcon#enter wrdev, iclass 10, count 2 2006.257.14:56:22.66#ibcon#first serial, iclass 10, count 2 2006.257.14:56:22.66#ibcon#enter sib2, iclass 10, count 2 2006.257.14:56:22.66#ibcon#flushed, iclass 10, count 2 2006.257.14:56:22.66#ibcon#about to write, iclass 10, count 2 2006.257.14:56:22.66#ibcon#wrote, iclass 10, count 2 2006.257.14:56:22.66#ibcon#about to read 3, iclass 10, count 2 2006.257.14:56:22.68#ibcon#read 3, iclass 10, count 2 2006.257.14:56:22.68#ibcon#about to read 4, iclass 10, count 2 2006.257.14:56:22.68#ibcon#read 4, iclass 10, count 2 2006.257.14:56:22.68#ibcon#about to read 5, iclass 10, count 2 2006.257.14:56:22.68#ibcon#read 5, iclass 10, count 2 2006.257.14:56:22.68#ibcon#about to read 6, iclass 10, count 2 2006.257.14:56:22.68#ibcon#read 6, iclass 10, count 2 2006.257.14:56:22.68#ibcon#end of sib2, iclass 10, count 2 2006.257.14:56:22.68#ibcon#*mode == 0, iclass 10, count 2 2006.257.14:56:22.68#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.14:56:22.68#ibcon#[27=AT06-04\r\n] 2006.257.14:56:22.68#ibcon#*before write, iclass 10, count 2 2006.257.14:56:22.68#ibcon#enter sib2, iclass 10, count 2 2006.257.14:56:22.68#ibcon#flushed, iclass 10, count 2 2006.257.14:56:22.68#ibcon#about to write, iclass 10, count 2 2006.257.14:56:22.68#ibcon#wrote, iclass 10, count 2 2006.257.14:56:22.68#ibcon#about to read 3, iclass 10, count 2 2006.257.14:56:22.71#ibcon#read 3, iclass 10, count 2 2006.257.14:56:22.71#ibcon#about to read 4, iclass 10, count 2 2006.257.14:56:22.71#ibcon#read 4, iclass 10, count 2 2006.257.14:56:22.71#ibcon#about to read 5, iclass 10, count 2 2006.257.14:56:22.71#ibcon#read 5, iclass 10, count 2 2006.257.14:56:22.71#ibcon#about to read 6, iclass 10, count 2 2006.257.14:56:22.71#ibcon#read 6, iclass 10, count 2 2006.257.14:56:22.71#ibcon#end of sib2, iclass 10, count 2 2006.257.14:56:22.71#ibcon#*after write, iclass 10, count 2 2006.257.14:56:22.71#ibcon#*before return 0, iclass 10, count 2 2006.257.14:56:22.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:22.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.14:56:22.71#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.14:56:22.71#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:22.71#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:22.83#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:22.83#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:22.83#ibcon#enter wrdev, iclass 10, count 0 2006.257.14:56:22.83#ibcon#first serial, iclass 10, count 0 2006.257.14:56:22.83#ibcon#enter sib2, iclass 10, count 0 2006.257.14:56:22.83#ibcon#flushed, iclass 10, count 0 2006.257.14:56:22.83#ibcon#about to write, iclass 10, count 0 2006.257.14:56:22.83#ibcon#wrote, iclass 10, count 0 2006.257.14:56:22.83#ibcon#about to read 3, iclass 10, count 0 2006.257.14:56:22.85#ibcon#read 3, iclass 10, count 0 2006.257.14:56:22.85#ibcon#about to read 4, iclass 10, count 0 2006.257.14:56:22.85#ibcon#read 4, iclass 10, count 0 2006.257.14:56:22.85#ibcon#about to read 5, iclass 10, count 0 2006.257.14:56:22.85#ibcon#read 5, iclass 10, count 0 2006.257.14:56:22.85#ibcon#about to read 6, iclass 10, count 0 2006.257.14:56:22.85#ibcon#read 6, iclass 10, count 0 2006.257.14:56:22.85#ibcon#end of sib2, iclass 10, count 0 2006.257.14:56:22.85#ibcon#*mode == 0, iclass 10, count 0 2006.257.14:56:22.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.14:56:22.85#ibcon#[27=USB\r\n] 2006.257.14:56:22.85#ibcon#*before write, iclass 10, count 0 2006.257.14:56:22.85#ibcon#enter sib2, iclass 10, count 0 2006.257.14:56:22.85#ibcon#flushed, iclass 10, count 0 2006.257.14:56:22.85#ibcon#about to write, iclass 10, count 0 2006.257.14:56:22.85#ibcon#wrote, iclass 10, count 0 2006.257.14:56:22.85#ibcon#about to read 3, iclass 10, count 0 2006.257.14:56:22.88#ibcon#read 3, iclass 10, count 0 2006.257.14:56:22.88#ibcon#about to read 4, iclass 10, count 0 2006.257.14:56:22.88#ibcon#read 4, iclass 10, count 0 2006.257.14:56:22.88#ibcon#about to read 5, iclass 10, count 0 2006.257.14:56:22.88#ibcon#read 5, iclass 10, count 0 2006.257.14:56:22.88#ibcon#about to read 6, iclass 10, count 0 2006.257.14:56:22.88#ibcon#read 6, iclass 10, count 0 2006.257.14:56:22.88#ibcon#end of sib2, iclass 10, count 0 2006.257.14:56:22.88#ibcon#*after write, iclass 10, count 0 2006.257.14:56:22.88#ibcon#*before return 0, iclass 10, count 0 2006.257.14:56:22.88#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:22.88#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.14:56:22.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.14:56:22.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.14:56:22.88$vck44/vblo=7,734.99 2006.257.14:56:22.88#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.14:56:22.88#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.14:56:22.88#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:22.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:22.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:22.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:22.88#ibcon#enter wrdev, iclass 12, count 0 2006.257.14:56:22.88#ibcon#first serial, iclass 12, count 0 2006.257.14:56:22.88#ibcon#enter sib2, iclass 12, count 0 2006.257.14:56:22.88#ibcon#flushed, iclass 12, count 0 2006.257.14:56:22.88#ibcon#about to write, iclass 12, count 0 2006.257.14:56:22.88#ibcon#wrote, iclass 12, count 0 2006.257.14:56:22.88#ibcon#about to read 3, iclass 12, count 0 2006.257.14:56:22.90#ibcon#read 3, iclass 12, count 0 2006.257.14:56:22.90#ibcon#about to read 4, iclass 12, count 0 2006.257.14:56:22.90#ibcon#read 4, iclass 12, count 0 2006.257.14:56:22.90#ibcon#about to read 5, iclass 12, count 0 2006.257.14:56:22.90#ibcon#read 5, iclass 12, count 0 2006.257.14:56:22.90#ibcon#about to read 6, iclass 12, count 0 2006.257.14:56:22.90#ibcon#read 6, iclass 12, count 0 2006.257.14:56:22.90#ibcon#end of sib2, iclass 12, count 0 2006.257.14:56:22.90#ibcon#*mode == 0, iclass 12, count 0 2006.257.14:56:22.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.14:56:22.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.14:56:22.90#ibcon#*before write, iclass 12, count 0 2006.257.14:56:22.90#ibcon#enter sib2, iclass 12, count 0 2006.257.14:56:22.90#ibcon#flushed, iclass 12, count 0 2006.257.14:56:22.90#ibcon#about to write, iclass 12, count 0 2006.257.14:56:22.90#ibcon#wrote, iclass 12, count 0 2006.257.14:56:22.90#ibcon#about to read 3, iclass 12, count 0 2006.257.14:56:22.94#ibcon#read 3, iclass 12, count 0 2006.257.14:56:22.94#ibcon#about to read 4, iclass 12, count 0 2006.257.14:56:22.94#ibcon#read 4, iclass 12, count 0 2006.257.14:56:22.94#ibcon#about to read 5, iclass 12, count 0 2006.257.14:56:22.94#ibcon#read 5, iclass 12, count 0 2006.257.14:56:22.94#ibcon#about to read 6, iclass 12, count 0 2006.257.14:56:22.94#ibcon#read 6, iclass 12, count 0 2006.257.14:56:22.94#ibcon#end of sib2, iclass 12, count 0 2006.257.14:56:22.94#ibcon#*after write, iclass 12, count 0 2006.257.14:56:22.94#ibcon#*before return 0, iclass 12, count 0 2006.257.14:56:22.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:22.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.14:56:22.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.14:56:22.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.14:56:22.94$vck44/vb=7,4 2006.257.14:56:22.94#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.14:56:22.94#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.14:56:22.94#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:22.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:23.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:23.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:23.00#ibcon#enter wrdev, iclass 14, count 2 2006.257.14:56:23.00#ibcon#first serial, iclass 14, count 2 2006.257.14:56:23.00#ibcon#enter sib2, iclass 14, count 2 2006.257.14:56:23.00#ibcon#flushed, iclass 14, count 2 2006.257.14:56:23.00#ibcon#about to write, iclass 14, count 2 2006.257.14:56:23.00#ibcon#wrote, iclass 14, count 2 2006.257.14:56:23.00#ibcon#about to read 3, iclass 14, count 2 2006.257.14:56:23.02#ibcon#read 3, iclass 14, count 2 2006.257.14:56:23.02#ibcon#about to read 4, iclass 14, count 2 2006.257.14:56:23.02#ibcon#read 4, iclass 14, count 2 2006.257.14:56:23.02#ibcon#about to read 5, iclass 14, count 2 2006.257.14:56:23.02#ibcon#read 5, iclass 14, count 2 2006.257.14:56:23.02#ibcon#about to read 6, iclass 14, count 2 2006.257.14:56:23.02#ibcon#read 6, iclass 14, count 2 2006.257.14:56:23.02#ibcon#end of sib2, iclass 14, count 2 2006.257.14:56:23.02#ibcon#*mode == 0, iclass 14, count 2 2006.257.14:56:23.02#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.14:56:23.02#ibcon#[27=AT07-04\r\n] 2006.257.14:56:23.02#ibcon#*before write, iclass 14, count 2 2006.257.14:56:23.02#ibcon#enter sib2, iclass 14, count 2 2006.257.14:56:23.02#ibcon#flushed, iclass 14, count 2 2006.257.14:56:23.02#ibcon#about to write, iclass 14, count 2 2006.257.14:56:23.02#ibcon#wrote, iclass 14, count 2 2006.257.14:56:23.02#ibcon#about to read 3, iclass 14, count 2 2006.257.14:56:23.05#ibcon#read 3, iclass 14, count 2 2006.257.14:56:23.05#ibcon#about to read 4, iclass 14, count 2 2006.257.14:56:23.05#ibcon#read 4, iclass 14, count 2 2006.257.14:56:23.05#ibcon#about to read 5, iclass 14, count 2 2006.257.14:56:23.05#ibcon#read 5, iclass 14, count 2 2006.257.14:56:23.05#ibcon#about to read 6, iclass 14, count 2 2006.257.14:56:23.05#ibcon#read 6, iclass 14, count 2 2006.257.14:56:23.05#ibcon#end of sib2, iclass 14, count 2 2006.257.14:56:23.05#ibcon#*after write, iclass 14, count 2 2006.257.14:56:23.05#ibcon#*before return 0, iclass 14, count 2 2006.257.14:56:23.05#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:23.05#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.14:56:23.05#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.14:56:23.05#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:23.05#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:23.17#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:23.17#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:23.17#ibcon#enter wrdev, iclass 14, count 0 2006.257.14:56:23.17#ibcon#first serial, iclass 14, count 0 2006.257.14:56:23.17#ibcon#enter sib2, iclass 14, count 0 2006.257.14:56:23.17#ibcon#flushed, iclass 14, count 0 2006.257.14:56:23.17#ibcon#about to write, iclass 14, count 0 2006.257.14:56:23.17#ibcon#wrote, iclass 14, count 0 2006.257.14:56:23.17#ibcon#about to read 3, iclass 14, count 0 2006.257.14:56:23.19#ibcon#read 3, iclass 14, count 0 2006.257.14:56:23.19#ibcon#about to read 4, iclass 14, count 0 2006.257.14:56:23.19#ibcon#read 4, iclass 14, count 0 2006.257.14:56:23.19#ibcon#about to read 5, iclass 14, count 0 2006.257.14:56:23.19#ibcon#read 5, iclass 14, count 0 2006.257.14:56:23.19#ibcon#about to read 6, iclass 14, count 0 2006.257.14:56:23.19#ibcon#read 6, iclass 14, count 0 2006.257.14:56:23.19#ibcon#end of sib2, iclass 14, count 0 2006.257.14:56:23.19#ibcon#*mode == 0, iclass 14, count 0 2006.257.14:56:23.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.14:56:23.19#ibcon#[27=USB\r\n] 2006.257.14:56:23.19#ibcon#*before write, iclass 14, count 0 2006.257.14:56:23.19#ibcon#enter sib2, iclass 14, count 0 2006.257.14:56:23.19#ibcon#flushed, iclass 14, count 0 2006.257.14:56:23.19#ibcon#about to write, iclass 14, count 0 2006.257.14:56:23.19#ibcon#wrote, iclass 14, count 0 2006.257.14:56:23.19#ibcon#about to read 3, iclass 14, count 0 2006.257.14:56:23.22#ibcon#read 3, iclass 14, count 0 2006.257.14:56:23.22#ibcon#about to read 4, iclass 14, count 0 2006.257.14:56:23.22#ibcon#read 4, iclass 14, count 0 2006.257.14:56:23.22#ibcon#about to read 5, iclass 14, count 0 2006.257.14:56:23.22#ibcon#read 5, iclass 14, count 0 2006.257.14:56:23.22#ibcon#about to read 6, iclass 14, count 0 2006.257.14:56:23.22#ibcon#read 6, iclass 14, count 0 2006.257.14:56:23.22#ibcon#end of sib2, iclass 14, count 0 2006.257.14:56:23.22#ibcon#*after write, iclass 14, count 0 2006.257.14:56:23.22#ibcon#*before return 0, iclass 14, count 0 2006.257.14:56:23.22#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:23.22#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.14:56:23.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.14:56:23.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.14:56:23.22$vck44/vblo=8,744.99 2006.257.14:56:23.22#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.14:56:23.22#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.14:56:23.22#ibcon#ireg 17 cls_cnt 0 2006.257.14:56:23.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:23.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:23.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:23.22#ibcon#enter wrdev, iclass 16, count 0 2006.257.14:56:23.22#ibcon#first serial, iclass 16, count 0 2006.257.14:56:23.22#ibcon#enter sib2, iclass 16, count 0 2006.257.14:56:23.22#ibcon#flushed, iclass 16, count 0 2006.257.14:56:23.22#ibcon#about to write, iclass 16, count 0 2006.257.14:56:23.22#ibcon#wrote, iclass 16, count 0 2006.257.14:56:23.22#ibcon#about to read 3, iclass 16, count 0 2006.257.14:56:23.24#ibcon#read 3, iclass 16, count 0 2006.257.14:56:23.24#ibcon#about to read 4, iclass 16, count 0 2006.257.14:56:23.24#ibcon#read 4, iclass 16, count 0 2006.257.14:56:23.24#ibcon#about to read 5, iclass 16, count 0 2006.257.14:56:23.24#ibcon#read 5, iclass 16, count 0 2006.257.14:56:23.24#ibcon#about to read 6, iclass 16, count 0 2006.257.14:56:23.24#ibcon#read 6, iclass 16, count 0 2006.257.14:56:23.24#ibcon#end of sib2, iclass 16, count 0 2006.257.14:56:23.24#ibcon#*mode == 0, iclass 16, count 0 2006.257.14:56:23.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.14:56:23.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.14:56:23.24#ibcon#*before write, iclass 16, count 0 2006.257.14:56:23.24#ibcon#enter sib2, iclass 16, count 0 2006.257.14:56:23.24#ibcon#flushed, iclass 16, count 0 2006.257.14:56:23.24#ibcon#about to write, iclass 16, count 0 2006.257.14:56:23.24#ibcon#wrote, iclass 16, count 0 2006.257.14:56:23.24#ibcon#about to read 3, iclass 16, count 0 2006.257.14:56:23.28#abcon#<5=/14 1.2 3.0 17.46 961014.2\r\n> 2006.257.14:56:23.28#ibcon#read 3, iclass 16, count 0 2006.257.14:56:23.28#ibcon#about to read 4, iclass 16, count 0 2006.257.14:56:23.28#ibcon#read 4, iclass 16, count 0 2006.257.14:56:23.28#ibcon#about to read 5, iclass 16, count 0 2006.257.14:56:23.28#ibcon#read 5, iclass 16, count 0 2006.257.14:56:23.28#ibcon#about to read 6, iclass 16, count 0 2006.257.14:56:23.28#ibcon#read 6, iclass 16, count 0 2006.257.14:56:23.28#ibcon#end of sib2, iclass 16, count 0 2006.257.14:56:23.28#ibcon#*after write, iclass 16, count 0 2006.257.14:56:23.28#ibcon#*before return 0, iclass 16, count 0 2006.257.14:56:23.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:23.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.14:56:23.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.14:56:23.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.14:56:23.28$vck44/vb=8,4 2006.257.14:56:23.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.14:56:23.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.14:56:23.28#ibcon#ireg 11 cls_cnt 2 2006.257.14:56:23.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:56:23.30#abcon#{5=INTERFACE CLEAR} 2006.257.14:56:23.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:56:23.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:56:23.34#ibcon#enter wrdev, iclass 21, count 2 2006.257.14:56:23.34#ibcon#first serial, iclass 21, count 2 2006.257.14:56:23.34#ibcon#enter sib2, iclass 21, count 2 2006.257.14:56:23.34#ibcon#flushed, iclass 21, count 2 2006.257.14:56:23.34#ibcon#about to write, iclass 21, count 2 2006.257.14:56:23.34#ibcon#wrote, iclass 21, count 2 2006.257.14:56:23.34#ibcon#about to read 3, iclass 21, count 2 2006.257.14:56:23.36#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:56:23.36#ibcon#read 3, iclass 21, count 2 2006.257.14:56:23.36#ibcon#about to read 4, iclass 21, count 2 2006.257.14:56:23.36#ibcon#read 4, iclass 21, count 2 2006.257.14:56:23.36#ibcon#about to read 5, iclass 21, count 2 2006.257.14:56:23.36#ibcon#read 5, iclass 21, count 2 2006.257.14:56:23.36#ibcon#about to read 6, iclass 21, count 2 2006.257.14:56:23.36#ibcon#read 6, iclass 21, count 2 2006.257.14:56:23.36#ibcon#end of sib2, iclass 21, count 2 2006.257.14:56:23.36#ibcon#*mode == 0, iclass 21, count 2 2006.257.14:56:23.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.14:56:23.36#ibcon#[27=AT08-04\r\n] 2006.257.14:56:23.36#ibcon#*before write, iclass 21, count 2 2006.257.14:56:23.36#ibcon#enter sib2, iclass 21, count 2 2006.257.14:56:23.36#ibcon#flushed, iclass 21, count 2 2006.257.14:56:23.36#ibcon#about to write, iclass 21, count 2 2006.257.14:56:23.36#ibcon#wrote, iclass 21, count 2 2006.257.14:56:23.40#ibcon#about to read 3, iclass 21, count 2 2006.257.14:56:23.40#ibcon#read 3, iclass 21, count 2 2006.257.14:56:23.40#ibcon#about to read 4, iclass 21, count 2 2006.257.14:56:23.40#ibcon#read 4, iclass 21, count 2 2006.257.14:56:23.40#ibcon#about to read 5, iclass 21, count 2 2006.257.14:56:23.40#ibcon#read 5, iclass 21, count 2 2006.257.14:56:23.40#ibcon#about to read 6, iclass 21, count 2 2006.257.14:56:23.40#ibcon#read 6, iclass 21, count 2 2006.257.14:56:23.40#ibcon#end of sib2, iclass 21, count 2 2006.257.14:56:23.40#ibcon#*after write, iclass 21, count 2 2006.257.14:56:23.40#ibcon#*before return 0, iclass 21, count 2 2006.257.14:56:23.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:56:23.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.14:56:23.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.14:56:23.40#ibcon#ireg 7 cls_cnt 0 2006.257.14:56:23.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:56:23.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:56:23.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:56:23.52#ibcon#enter wrdev, iclass 21, count 0 2006.257.14:56:23.52#ibcon#first serial, iclass 21, count 0 2006.257.14:56:23.52#ibcon#enter sib2, iclass 21, count 0 2006.257.14:56:23.52#ibcon#flushed, iclass 21, count 0 2006.257.14:56:23.52#ibcon#about to write, iclass 21, count 0 2006.257.14:56:23.52#ibcon#wrote, iclass 21, count 0 2006.257.14:56:23.52#ibcon#about to read 3, iclass 21, count 0 2006.257.14:56:23.54#ibcon#read 3, iclass 21, count 0 2006.257.14:56:23.54#ibcon#about to read 4, iclass 21, count 0 2006.257.14:56:23.54#ibcon#read 4, iclass 21, count 0 2006.257.14:56:23.54#ibcon#about to read 5, iclass 21, count 0 2006.257.14:56:23.54#ibcon#read 5, iclass 21, count 0 2006.257.14:56:23.54#ibcon#about to read 6, iclass 21, count 0 2006.257.14:56:23.54#ibcon#read 6, iclass 21, count 0 2006.257.14:56:23.54#ibcon#end of sib2, iclass 21, count 0 2006.257.14:56:23.54#ibcon#*mode == 0, iclass 21, count 0 2006.257.14:56:23.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.14:56:23.54#ibcon#[27=USB\r\n] 2006.257.14:56:23.54#ibcon#*before write, iclass 21, count 0 2006.257.14:56:23.54#ibcon#enter sib2, iclass 21, count 0 2006.257.14:56:23.54#ibcon#flushed, iclass 21, count 0 2006.257.14:56:23.54#ibcon#about to write, iclass 21, count 0 2006.257.14:56:23.54#ibcon#wrote, iclass 21, count 0 2006.257.14:56:23.54#ibcon#about to read 3, iclass 21, count 0 2006.257.14:56:23.57#ibcon#read 3, iclass 21, count 0 2006.257.14:56:23.57#ibcon#about to read 4, iclass 21, count 0 2006.257.14:56:23.57#ibcon#read 4, iclass 21, count 0 2006.257.14:56:23.57#ibcon#about to read 5, iclass 21, count 0 2006.257.14:56:23.57#ibcon#read 5, iclass 21, count 0 2006.257.14:56:23.57#ibcon#about to read 6, iclass 21, count 0 2006.257.14:56:23.57#ibcon#read 6, iclass 21, count 0 2006.257.14:56:23.57#ibcon#end of sib2, iclass 21, count 0 2006.257.14:56:23.57#ibcon#*after write, iclass 21, count 0 2006.257.14:56:23.57#ibcon#*before return 0, iclass 21, count 0 2006.257.14:56:23.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:56:23.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.14:56:23.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.14:56:23.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.14:56:23.57$vck44/vabw=wide 2006.257.14:56:23.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.14:56:23.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.14:56:23.57#ibcon#ireg 8 cls_cnt 0 2006.257.14:56:23.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:23.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:23.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:23.57#ibcon#enter wrdev, iclass 24, count 0 2006.257.14:56:23.57#ibcon#first serial, iclass 24, count 0 2006.257.14:56:23.57#ibcon#enter sib2, iclass 24, count 0 2006.257.14:56:23.57#ibcon#flushed, iclass 24, count 0 2006.257.14:56:23.57#ibcon#about to write, iclass 24, count 0 2006.257.14:56:23.57#ibcon#wrote, iclass 24, count 0 2006.257.14:56:23.57#ibcon#about to read 3, iclass 24, count 0 2006.257.14:56:23.59#ibcon#read 3, iclass 24, count 0 2006.257.14:56:23.59#ibcon#about to read 4, iclass 24, count 0 2006.257.14:56:23.59#ibcon#read 4, iclass 24, count 0 2006.257.14:56:23.59#ibcon#about to read 5, iclass 24, count 0 2006.257.14:56:23.59#ibcon#read 5, iclass 24, count 0 2006.257.14:56:23.59#ibcon#about to read 6, iclass 24, count 0 2006.257.14:56:23.59#ibcon#read 6, iclass 24, count 0 2006.257.14:56:23.59#ibcon#end of sib2, iclass 24, count 0 2006.257.14:56:23.59#ibcon#*mode == 0, iclass 24, count 0 2006.257.14:56:23.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.14:56:23.59#ibcon#[25=BW32\r\n] 2006.257.14:56:23.59#ibcon#*before write, iclass 24, count 0 2006.257.14:56:23.59#ibcon#enter sib2, iclass 24, count 0 2006.257.14:56:23.59#ibcon#flushed, iclass 24, count 0 2006.257.14:56:23.59#ibcon#about to write, iclass 24, count 0 2006.257.14:56:23.59#ibcon#wrote, iclass 24, count 0 2006.257.14:56:23.59#ibcon#about to read 3, iclass 24, count 0 2006.257.14:56:23.62#ibcon#read 3, iclass 24, count 0 2006.257.14:56:23.62#ibcon#about to read 4, iclass 24, count 0 2006.257.14:56:23.62#ibcon#read 4, iclass 24, count 0 2006.257.14:56:23.62#ibcon#about to read 5, iclass 24, count 0 2006.257.14:56:23.62#ibcon#read 5, iclass 24, count 0 2006.257.14:56:23.62#ibcon#about to read 6, iclass 24, count 0 2006.257.14:56:23.62#ibcon#read 6, iclass 24, count 0 2006.257.14:56:23.62#ibcon#end of sib2, iclass 24, count 0 2006.257.14:56:23.62#ibcon#*after write, iclass 24, count 0 2006.257.14:56:23.62#ibcon#*before return 0, iclass 24, count 0 2006.257.14:56:23.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:23.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.14:56:23.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.14:56:23.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.14:56:23.62$vck44/vbbw=wide 2006.257.14:56:23.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.14:56:23.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.14:56:23.62#ibcon#ireg 8 cls_cnt 0 2006.257.14:56:23.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:56:23.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:56:23.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:56:23.69#ibcon#enter wrdev, iclass 26, count 0 2006.257.14:56:23.69#ibcon#first serial, iclass 26, count 0 2006.257.14:56:23.69#ibcon#enter sib2, iclass 26, count 0 2006.257.14:56:23.69#ibcon#flushed, iclass 26, count 0 2006.257.14:56:23.69#ibcon#about to write, iclass 26, count 0 2006.257.14:56:23.69#ibcon#wrote, iclass 26, count 0 2006.257.14:56:23.69#ibcon#about to read 3, iclass 26, count 0 2006.257.14:56:23.71#ibcon#read 3, iclass 26, count 0 2006.257.14:56:23.71#ibcon#about to read 4, iclass 26, count 0 2006.257.14:56:23.71#ibcon#read 4, iclass 26, count 0 2006.257.14:56:23.71#ibcon#about to read 5, iclass 26, count 0 2006.257.14:56:23.71#ibcon#read 5, iclass 26, count 0 2006.257.14:56:23.71#ibcon#about to read 6, iclass 26, count 0 2006.257.14:56:23.71#ibcon#read 6, iclass 26, count 0 2006.257.14:56:23.71#ibcon#end of sib2, iclass 26, count 0 2006.257.14:56:23.71#ibcon#*mode == 0, iclass 26, count 0 2006.257.14:56:23.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.14:56:23.71#ibcon#[27=BW32\r\n] 2006.257.14:56:23.71#ibcon#*before write, iclass 26, count 0 2006.257.14:56:23.71#ibcon#enter sib2, iclass 26, count 0 2006.257.14:56:23.71#ibcon#flushed, iclass 26, count 0 2006.257.14:56:23.71#ibcon#about to write, iclass 26, count 0 2006.257.14:56:23.71#ibcon#wrote, iclass 26, count 0 2006.257.14:56:23.71#ibcon#about to read 3, iclass 26, count 0 2006.257.14:56:23.74#ibcon#read 3, iclass 26, count 0 2006.257.14:56:23.74#ibcon#about to read 4, iclass 26, count 0 2006.257.14:56:23.74#ibcon#read 4, iclass 26, count 0 2006.257.14:56:23.74#ibcon#about to read 5, iclass 26, count 0 2006.257.14:56:23.74#ibcon#read 5, iclass 26, count 0 2006.257.14:56:23.74#ibcon#about to read 6, iclass 26, count 0 2006.257.14:56:23.74#ibcon#read 6, iclass 26, count 0 2006.257.14:56:23.74#ibcon#end of sib2, iclass 26, count 0 2006.257.14:56:23.74#ibcon#*after write, iclass 26, count 0 2006.257.14:56:23.74#ibcon#*before return 0, iclass 26, count 0 2006.257.14:56:23.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:56:23.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.14:56:23.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.14:56:23.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.14:56:23.74$setupk4/ifdk4 2006.257.14:56:23.74$ifdk4/lo= 2006.257.14:56:23.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.14:56:23.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.14:56:23.74$ifdk4/patch= 2006.257.14:56:23.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.14:56:23.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.14:56:23.74$setupk4/!*+20s 2006.257.14:56:33.45#abcon#<5=/14 1.2 3.0 17.46 961014.2\r\n> 2006.257.14:56:33.47#abcon#{5=INTERFACE CLEAR} 2006.257.14:56:33.53#abcon#[5=S1D000X0/0*\r\n] 2006.257.14:56:38.19$setupk4/"tpicd 2006.257.14:56:38.19$setupk4/echo=off 2006.257.14:56:38.19$setupk4/xlog=off 2006.257.14:56:38.19:!2006.257.14:58:52 2006.257.14:57:09.14#trakl#Source acquired 2006.257.14:57:11.14#flagr#flagr/antenna,acquired 2006.257.14:58:52.00:preob 2006.257.14:58:52.14/onsource/TRACKING 2006.257.14:58:52.14:!2006.257.14:59:02 2006.257.14:59:02.00:"tape 2006.257.14:59:02.00:"st=record 2006.257.14:59:02.00:data_valid=on 2006.257.14:59:02.00:midob 2006.257.14:59:02.14/onsource/TRACKING 2006.257.14:59:02.14/wx/17.46,1014.1,97 2006.257.14:59:02.20/cable/+6.4826E-03 2006.257.14:59:03.29/va/01,08,usb,yes,34,36 2006.257.14:59:03.29/va/02,07,usb,yes,37,37 2006.257.14:59:03.29/va/03,08,usb,yes,33,35 2006.257.14:59:03.29/va/04,07,usb,yes,38,40 2006.257.14:59:03.29/va/05,04,usb,yes,34,34 2006.257.14:59:03.29/va/06,04,usb,yes,38,37 2006.257.14:59:03.29/va/07,04,usb,yes,39,39 2006.257.14:59:03.29/va/08,04,usb,yes,32,39 2006.257.14:59:03.52/valo/01,524.99,yes,locked 2006.257.14:59:03.52/valo/02,534.99,yes,locked 2006.257.14:59:03.52/valo/03,564.99,yes,locked 2006.257.14:59:03.52/valo/04,624.99,yes,locked 2006.257.14:59:03.52/valo/05,734.99,yes,locked 2006.257.14:59:03.52/valo/06,814.99,yes,locked 2006.257.14:59:03.52/valo/07,864.99,yes,locked 2006.257.14:59:03.52/valo/08,884.99,yes,locked 2006.257.14:59:04.61/vb/01,04,usb,yes,32,34 2006.257.14:59:04.61/vb/02,05,usb,yes,31,33 2006.257.14:59:04.61/vb/03,04,usb,yes,32,35 2006.257.14:59:04.61/vb/04,05,usb,yes,32,31 2006.257.14:59:04.61/vb/05,04,usb,yes,29,31 2006.257.14:59:04.61/vb/06,04,usb,yes,34,30 2006.257.14:59:04.61/vb/07,04,usb,yes,33,33 2006.257.14:59:04.61/vb/08,04,usb,yes,30,34 2006.257.14:59:04.84/vblo/01,629.99,yes,locked 2006.257.14:59:04.84/vblo/02,634.99,yes,locked 2006.257.14:59:04.84/vblo/03,649.99,yes,locked 2006.257.14:59:04.84/vblo/04,679.99,yes,locked 2006.257.14:59:04.84/vblo/05,709.99,yes,locked 2006.257.14:59:04.84/vblo/06,719.99,yes,locked 2006.257.14:59:04.84/vblo/07,734.99,yes,locked 2006.257.14:59:04.84/vblo/08,744.99,yes,locked 2006.257.14:59:04.99/vabw/8 2006.257.14:59:05.14/vbbw/8 2006.257.14:59:05.23/xfe/off,on,15.2 2006.257.14:59:05.61/ifatt/23,28,28,28 2006.257.14:59:06.08/fmout-gps/S +4.62E-07 2006.257.14:59:06.12:!2006.257.15:01:22 2006.257.15:01:22.00:data_valid=off 2006.257.15:01:22.00:"et 2006.257.15:01:22.00:!+3s 2006.257.15:01:25.02:"tape 2006.257.15:01:25.02:postob 2006.257.15:01:25.16/cable/+6.4835E-03 2006.257.15:01:25.16/wx/17.44,1014.1,97 2006.257.15:01:25.22/fmout-gps/S +4.62E-07 2006.257.15:01:25.22:scan_name=257-1503,jd0609,240 2006.257.15:01:25.22:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.257.15:01:26.14#flagr#flagr/antenna,new-source 2006.257.15:01:26.14:checkk5 2006.257.15:01:26.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:01:26.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:01:27.38/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:01:27.85/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:01:28.24/chk_obsdata//k5ts1/T2571459??a.dat file size is correct (nominal:560MB, actual:556MB). 2006.257.15:01:28.65/chk_obsdata//k5ts2/T2571459??b.dat file size is correct (nominal:560MB, actual:556MB). 2006.257.15:01:29.05/chk_obsdata//k5ts3/T2571459??c.dat file size is correct (nominal:560MB, actual:556MB). 2006.257.15:01:29.44/chk_obsdata//k5ts4/T2571459??d.dat file size is correct (nominal:560MB, actual:556MB). 2006.257.15:01:30.17/k5log//k5ts1_log_newline 2006.257.15:01:30.88/k5log//k5ts2_log_newline 2006.257.15:01:31.60/k5log//k5ts3_log_newline 2006.257.15:01:32.30/k5log//k5ts4_log_newline 2006.257.15:01:32.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:01:32.33:setupk4=1 2006.257.15:01:32.33$setupk4/echo=on 2006.257.15:01:32.33$setupk4/pcalon 2006.257.15:01:32.33$pcalon/"no phase cal control is implemented here 2006.257.15:01:32.33$setupk4/"tpicd=stop 2006.257.15:01:32.33$setupk4/"rec=synch_on 2006.257.15:01:32.33$setupk4/"rec_mode=128 2006.257.15:01:32.33$setupk4/!* 2006.257.15:01:32.33$setupk4/recpk4 2006.257.15:01:32.33$recpk4/recpatch= 2006.257.15:01:32.33$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:01:32.33$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:01:32.33$setupk4/vck44 2006.257.15:01:32.33$vck44/valo=1,524.99 2006.257.15:01:32.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.15:01:32.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.15:01:32.33#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:32.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:32.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:32.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:32.33#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:01:32.33#ibcon#first serial, iclass 5, count 0 2006.257.15:01:32.33#ibcon#enter sib2, iclass 5, count 0 2006.257.15:01:32.33#ibcon#flushed, iclass 5, count 0 2006.257.15:01:32.33#ibcon#about to write, iclass 5, count 0 2006.257.15:01:32.33#ibcon#wrote, iclass 5, count 0 2006.257.15:01:32.33#ibcon#about to read 3, iclass 5, count 0 2006.257.15:01:32.35#ibcon#read 3, iclass 5, count 0 2006.257.15:01:32.35#ibcon#about to read 4, iclass 5, count 0 2006.257.15:01:32.35#ibcon#read 4, iclass 5, count 0 2006.257.15:01:32.35#ibcon#about to read 5, iclass 5, count 0 2006.257.15:01:32.35#ibcon#read 5, iclass 5, count 0 2006.257.15:01:32.35#ibcon#about to read 6, iclass 5, count 0 2006.257.15:01:32.35#ibcon#read 6, iclass 5, count 0 2006.257.15:01:32.35#ibcon#end of sib2, iclass 5, count 0 2006.257.15:01:32.35#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:01:32.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:01:32.35#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:01:32.35#ibcon#*before write, iclass 5, count 0 2006.257.15:01:32.35#ibcon#enter sib2, iclass 5, count 0 2006.257.15:01:32.35#ibcon#flushed, iclass 5, count 0 2006.257.15:01:32.35#ibcon#about to write, iclass 5, count 0 2006.257.15:01:32.35#ibcon#wrote, iclass 5, count 0 2006.257.15:01:32.35#ibcon#about to read 3, iclass 5, count 0 2006.257.15:01:32.40#ibcon#read 3, iclass 5, count 0 2006.257.15:01:32.40#ibcon#about to read 4, iclass 5, count 0 2006.257.15:01:32.40#ibcon#read 4, iclass 5, count 0 2006.257.15:01:32.40#ibcon#about to read 5, iclass 5, count 0 2006.257.15:01:32.40#ibcon#read 5, iclass 5, count 0 2006.257.15:01:32.40#ibcon#about to read 6, iclass 5, count 0 2006.257.15:01:32.40#ibcon#read 6, iclass 5, count 0 2006.257.15:01:32.40#ibcon#end of sib2, iclass 5, count 0 2006.257.15:01:32.40#ibcon#*after write, iclass 5, count 0 2006.257.15:01:32.40#ibcon#*before return 0, iclass 5, count 0 2006.257.15:01:32.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:32.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:32.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:01:32.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:01:32.40$vck44/va=1,8 2006.257.15:01:32.40#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.15:01:32.40#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.15:01:32.40#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:32.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:32.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:32.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:32.40#ibcon#enter wrdev, iclass 7, count 2 2006.257.15:01:32.40#ibcon#first serial, iclass 7, count 2 2006.257.15:01:32.40#ibcon#enter sib2, iclass 7, count 2 2006.257.15:01:32.40#ibcon#flushed, iclass 7, count 2 2006.257.15:01:32.40#ibcon#about to write, iclass 7, count 2 2006.257.15:01:32.40#ibcon#wrote, iclass 7, count 2 2006.257.15:01:32.40#ibcon#about to read 3, iclass 7, count 2 2006.257.15:01:32.42#ibcon#read 3, iclass 7, count 2 2006.257.15:01:32.42#ibcon#about to read 4, iclass 7, count 2 2006.257.15:01:32.42#ibcon#read 4, iclass 7, count 2 2006.257.15:01:32.42#ibcon#about to read 5, iclass 7, count 2 2006.257.15:01:32.42#ibcon#read 5, iclass 7, count 2 2006.257.15:01:32.42#ibcon#about to read 6, iclass 7, count 2 2006.257.15:01:32.42#ibcon#read 6, iclass 7, count 2 2006.257.15:01:32.42#ibcon#end of sib2, iclass 7, count 2 2006.257.15:01:32.42#ibcon#*mode == 0, iclass 7, count 2 2006.257.15:01:32.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.15:01:32.42#ibcon#[25=AT01-08\r\n] 2006.257.15:01:32.42#ibcon#*before write, iclass 7, count 2 2006.257.15:01:32.42#ibcon#enter sib2, iclass 7, count 2 2006.257.15:01:32.42#ibcon#flushed, iclass 7, count 2 2006.257.15:01:32.42#ibcon#about to write, iclass 7, count 2 2006.257.15:01:32.42#ibcon#wrote, iclass 7, count 2 2006.257.15:01:32.42#ibcon#about to read 3, iclass 7, count 2 2006.257.15:01:32.45#ibcon#read 3, iclass 7, count 2 2006.257.15:01:32.45#ibcon#about to read 4, iclass 7, count 2 2006.257.15:01:32.45#ibcon#read 4, iclass 7, count 2 2006.257.15:01:32.45#ibcon#about to read 5, iclass 7, count 2 2006.257.15:01:32.45#ibcon#read 5, iclass 7, count 2 2006.257.15:01:32.45#ibcon#about to read 6, iclass 7, count 2 2006.257.15:01:32.45#ibcon#read 6, iclass 7, count 2 2006.257.15:01:32.45#ibcon#end of sib2, iclass 7, count 2 2006.257.15:01:32.45#ibcon#*after write, iclass 7, count 2 2006.257.15:01:32.45#ibcon#*before return 0, iclass 7, count 2 2006.257.15:01:32.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:32.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:32.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.15:01:32.45#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:32.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:32.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:32.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:32.57#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:01:32.57#ibcon#first serial, iclass 7, count 0 2006.257.15:01:32.57#ibcon#enter sib2, iclass 7, count 0 2006.257.15:01:32.57#ibcon#flushed, iclass 7, count 0 2006.257.15:01:32.57#ibcon#about to write, iclass 7, count 0 2006.257.15:01:32.57#ibcon#wrote, iclass 7, count 0 2006.257.15:01:32.57#ibcon#about to read 3, iclass 7, count 0 2006.257.15:01:32.59#ibcon#read 3, iclass 7, count 0 2006.257.15:01:32.59#ibcon#about to read 4, iclass 7, count 0 2006.257.15:01:32.59#ibcon#read 4, iclass 7, count 0 2006.257.15:01:32.59#ibcon#about to read 5, iclass 7, count 0 2006.257.15:01:32.59#ibcon#read 5, iclass 7, count 0 2006.257.15:01:32.59#ibcon#about to read 6, iclass 7, count 0 2006.257.15:01:32.59#ibcon#read 6, iclass 7, count 0 2006.257.15:01:32.59#ibcon#end of sib2, iclass 7, count 0 2006.257.15:01:32.59#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:01:32.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:01:32.59#ibcon#[25=USB\r\n] 2006.257.15:01:32.59#ibcon#*before write, iclass 7, count 0 2006.257.15:01:32.59#ibcon#enter sib2, iclass 7, count 0 2006.257.15:01:32.59#ibcon#flushed, iclass 7, count 0 2006.257.15:01:32.59#ibcon#about to write, iclass 7, count 0 2006.257.15:01:32.59#ibcon#wrote, iclass 7, count 0 2006.257.15:01:32.59#ibcon#about to read 3, iclass 7, count 0 2006.257.15:01:32.62#ibcon#read 3, iclass 7, count 0 2006.257.15:01:32.62#ibcon#about to read 4, iclass 7, count 0 2006.257.15:01:32.62#ibcon#read 4, iclass 7, count 0 2006.257.15:01:32.62#ibcon#about to read 5, iclass 7, count 0 2006.257.15:01:32.62#ibcon#read 5, iclass 7, count 0 2006.257.15:01:32.62#ibcon#about to read 6, iclass 7, count 0 2006.257.15:01:32.62#ibcon#read 6, iclass 7, count 0 2006.257.15:01:32.62#ibcon#end of sib2, iclass 7, count 0 2006.257.15:01:32.62#ibcon#*after write, iclass 7, count 0 2006.257.15:01:32.62#ibcon#*before return 0, iclass 7, count 0 2006.257.15:01:32.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:32.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:32.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:01:32.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:01:32.62$vck44/valo=2,534.99 2006.257.15:01:32.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.15:01:32.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.15:01:32.62#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:32.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:32.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:32.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:32.62#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:01:32.62#ibcon#first serial, iclass 11, count 0 2006.257.15:01:32.62#ibcon#enter sib2, iclass 11, count 0 2006.257.15:01:32.62#ibcon#flushed, iclass 11, count 0 2006.257.15:01:32.62#ibcon#about to write, iclass 11, count 0 2006.257.15:01:32.62#ibcon#wrote, iclass 11, count 0 2006.257.15:01:32.62#ibcon#about to read 3, iclass 11, count 0 2006.257.15:01:32.64#ibcon#read 3, iclass 11, count 0 2006.257.15:01:32.64#ibcon#about to read 4, iclass 11, count 0 2006.257.15:01:32.64#ibcon#read 4, iclass 11, count 0 2006.257.15:01:32.64#ibcon#about to read 5, iclass 11, count 0 2006.257.15:01:32.64#ibcon#read 5, iclass 11, count 0 2006.257.15:01:32.64#ibcon#about to read 6, iclass 11, count 0 2006.257.15:01:32.64#ibcon#read 6, iclass 11, count 0 2006.257.15:01:32.64#ibcon#end of sib2, iclass 11, count 0 2006.257.15:01:32.64#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:01:32.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:01:32.64#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:01:32.64#ibcon#*before write, iclass 11, count 0 2006.257.15:01:32.64#ibcon#enter sib2, iclass 11, count 0 2006.257.15:01:32.64#ibcon#flushed, iclass 11, count 0 2006.257.15:01:32.64#ibcon#about to write, iclass 11, count 0 2006.257.15:01:32.64#ibcon#wrote, iclass 11, count 0 2006.257.15:01:32.64#ibcon#about to read 3, iclass 11, count 0 2006.257.15:01:32.68#ibcon#read 3, iclass 11, count 0 2006.257.15:01:32.68#ibcon#about to read 4, iclass 11, count 0 2006.257.15:01:32.68#ibcon#read 4, iclass 11, count 0 2006.257.15:01:32.68#ibcon#about to read 5, iclass 11, count 0 2006.257.15:01:32.68#ibcon#read 5, iclass 11, count 0 2006.257.15:01:32.68#ibcon#about to read 6, iclass 11, count 0 2006.257.15:01:32.68#ibcon#read 6, iclass 11, count 0 2006.257.15:01:32.68#ibcon#end of sib2, iclass 11, count 0 2006.257.15:01:32.68#ibcon#*after write, iclass 11, count 0 2006.257.15:01:32.68#ibcon#*before return 0, iclass 11, count 0 2006.257.15:01:32.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:32.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:32.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:01:32.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:01:32.68$vck44/va=2,7 2006.257.15:01:32.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.15:01:32.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.15:01:32.68#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:32.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:32.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:32.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:32.74#ibcon#enter wrdev, iclass 13, count 2 2006.257.15:01:32.74#ibcon#first serial, iclass 13, count 2 2006.257.15:01:32.74#ibcon#enter sib2, iclass 13, count 2 2006.257.15:01:32.74#ibcon#flushed, iclass 13, count 2 2006.257.15:01:32.74#ibcon#about to write, iclass 13, count 2 2006.257.15:01:32.74#ibcon#wrote, iclass 13, count 2 2006.257.15:01:32.74#ibcon#about to read 3, iclass 13, count 2 2006.257.15:01:32.76#ibcon#read 3, iclass 13, count 2 2006.257.15:01:32.76#ibcon#about to read 4, iclass 13, count 2 2006.257.15:01:32.76#ibcon#read 4, iclass 13, count 2 2006.257.15:01:32.76#ibcon#about to read 5, iclass 13, count 2 2006.257.15:01:32.76#ibcon#read 5, iclass 13, count 2 2006.257.15:01:32.76#ibcon#about to read 6, iclass 13, count 2 2006.257.15:01:32.76#ibcon#read 6, iclass 13, count 2 2006.257.15:01:32.76#ibcon#end of sib2, iclass 13, count 2 2006.257.15:01:32.76#ibcon#*mode == 0, iclass 13, count 2 2006.257.15:01:32.76#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.15:01:32.76#ibcon#[25=AT02-07\r\n] 2006.257.15:01:32.76#ibcon#*before write, iclass 13, count 2 2006.257.15:01:32.76#ibcon#enter sib2, iclass 13, count 2 2006.257.15:01:32.76#ibcon#flushed, iclass 13, count 2 2006.257.15:01:32.76#ibcon#about to write, iclass 13, count 2 2006.257.15:01:32.76#ibcon#wrote, iclass 13, count 2 2006.257.15:01:32.76#ibcon#about to read 3, iclass 13, count 2 2006.257.15:01:32.79#ibcon#read 3, iclass 13, count 2 2006.257.15:01:32.79#ibcon#about to read 4, iclass 13, count 2 2006.257.15:01:32.79#ibcon#read 4, iclass 13, count 2 2006.257.15:01:32.79#ibcon#about to read 5, iclass 13, count 2 2006.257.15:01:32.79#ibcon#read 5, iclass 13, count 2 2006.257.15:01:32.79#ibcon#about to read 6, iclass 13, count 2 2006.257.15:01:32.79#ibcon#read 6, iclass 13, count 2 2006.257.15:01:32.79#ibcon#end of sib2, iclass 13, count 2 2006.257.15:01:32.79#ibcon#*after write, iclass 13, count 2 2006.257.15:01:32.79#ibcon#*before return 0, iclass 13, count 2 2006.257.15:01:32.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:32.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:32.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.15:01:32.79#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:32.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:32.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:32.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:32.91#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:01:32.91#ibcon#first serial, iclass 13, count 0 2006.257.15:01:32.91#ibcon#enter sib2, iclass 13, count 0 2006.257.15:01:32.91#ibcon#flushed, iclass 13, count 0 2006.257.15:01:32.91#ibcon#about to write, iclass 13, count 0 2006.257.15:01:32.91#ibcon#wrote, iclass 13, count 0 2006.257.15:01:32.91#ibcon#about to read 3, iclass 13, count 0 2006.257.15:01:32.93#ibcon#read 3, iclass 13, count 0 2006.257.15:01:32.93#ibcon#about to read 4, iclass 13, count 0 2006.257.15:01:32.93#ibcon#read 4, iclass 13, count 0 2006.257.15:01:32.93#ibcon#about to read 5, iclass 13, count 0 2006.257.15:01:32.93#ibcon#read 5, iclass 13, count 0 2006.257.15:01:32.93#ibcon#about to read 6, iclass 13, count 0 2006.257.15:01:32.93#ibcon#read 6, iclass 13, count 0 2006.257.15:01:32.93#ibcon#end of sib2, iclass 13, count 0 2006.257.15:01:32.93#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:01:32.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:01:32.93#ibcon#[25=USB\r\n] 2006.257.15:01:32.93#ibcon#*before write, iclass 13, count 0 2006.257.15:01:32.93#ibcon#enter sib2, iclass 13, count 0 2006.257.15:01:32.93#ibcon#flushed, iclass 13, count 0 2006.257.15:01:32.93#ibcon#about to write, iclass 13, count 0 2006.257.15:01:32.93#ibcon#wrote, iclass 13, count 0 2006.257.15:01:32.93#ibcon#about to read 3, iclass 13, count 0 2006.257.15:01:32.96#ibcon#read 3, iclass 13, count 0 2006.257.15:01:32.96#ibcon#about to read 4, iclass 13, count 0 2006.257.15:01:32.96#ibcon#read 4, iclass 13, count 0 2006.257.15:01:32.96#ibcon#about to read 5, iclass 13, count 0 2006.257.15:01:32.96#ibcon#read 5, iclass 13, count 0 2006.257.15:01:32.96#ibcon#about to read 6, iclass 13, count 0 2006.257.15:01:32.96#ibcon#read 6, iclass 13, count 0 2006.257.15:01:32.96#ibcon#end of sib2, iclass 13, count 0 2006.257.15:01:32.96#ibcon#*after write, iclass 13, count 0 2006.257.15:01:32.96#ibcon#*before return 0, iclass 13, count 0 2006.257.15:01:32.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:32.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:32.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:01:32.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:01:32.96$vck44/valo=3,564.99 2006.257.15:01:32.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.15:01:32.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.15:01:32.96#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:32.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:32.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:32.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:32.96#ibcon#enter wrdev, iclass 15, count 0 2006.257.15:01:32.96#ibcon#first serial, iclass 15, count 0 2006.257.15:01:32.96#ibcon#enter sib2, iclass 15, count 0 2006.257.15:01:32.96#ibcon#flushed, iclass 15, count 0 2006.257.15:01:32.96#ibcon#about to write, iclass 15, count 0 2006.257.15:01:32.96#ibcon#wrote, iclass 15, count 0 2006.257.15:01:32.96#ibcon#about to read 3, iclass 15, count 0 2006.257.15:01:32.98#ibcon#read 3, iclass 15, count 0 2006.257.15:01:32.98#ibcon#about to read 4, iclass 15, count 0 2006.257.15:01:32.98#ibcon#read 4, iclass 15, count 0 2006.257.15:01:32.98#ibcon#about to read 5, iclass 15, count 0 2006.257.15:01:32.98#ibcon#read 5, iclass 15, count 0 2006.257.15:01:32.98#ibcon#about to read 6, iclass 15, count 0 2006.257.15:01:32.98#ibcon#read 6, iclass 15, count 0 2006.257.15:01:32.98#ibcon#end of sib2, iclass 15, count 0 2006.257.15:01:32.98#ibcon#*mode == 0, iclass 15, count 0 2006.257.15:01:32.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.15:01:32.98#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:01:32.98#ibcon#*before write, iclass 15, count 0 2006.257.15:01:32.98#ibcon#enter sib2, iclass 15, count 0 2006.257.15:01:32.98#ibcon#flushed, iclass 15, count 0 2006.257.15:01:32.98#ibcon#about to write, iclass 15, count 0 2006.257.15:01:32.98#ibcon#wrote, iclass 15, count 0 2006.257.15:01:32.98#ibcon#about to read 3, iclass 15, count 0 2006.257.15:01:33.02#ibcon#read 3, iclass 15, count 0 2006.257.15:01:33.02#ibcon#about to read 4, iclass 15, count 0 2006.257.15:01:33.02#ibcon#read 4, iclass 15, count 0 2006.257.15:01:33.02#ibcon#about to read 5, iclass 15, count 0 2006.257.15:01:33.02#ibcon#read 5, iclass 15, count 0 2006.257.15:01:33.02#ibcon#about to read 6, iclass 15, count 0 2006.257.15:01:33.02#ibcon#read 6, iclass 15, count 0 2006.257.15:01:33.02#ibcon#end of sib2, iclass 15, count 0 2006.257.15:01:33.02#ibcon#*after write, iclass 15, count 0 2006.257.15:01:33.02#ibcon#*before return 0, iclass 15, count 0 2006.257.15:01:33.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:33.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:33.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.15:01:33.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.15:01:33.02$vck44/va=3,8 2006.257.15:01:33.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.15:01:33.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.15:01:33.02#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:33.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:33.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:33.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:33.08#ibcon#enter wrdev, iclass 17, count 2 2006.257.15:01:33.08#ibcon#first serial, iclass 17, count 2 2006.257.15:01:33.08#ibcon#enter sib2, iclass 17, count 2 2006.257.15:01:33.08#ibcon#flushed, iclass 17, count 2 2006.257.15:01:33.08#ibcon#about to write, iclass 17, count 2 2006.257.15:01:33.08#ibcon#wrote, iclass 17, count 2 2006.257.15:01:33.08#ibcon#about to read 3, iclass 17, count 2 2006.257.15:01:33.10#ibcon#read 3, iclass 17, count 2 2006.257.15:01:33.10#ibcon#about to read 4, iclass 17, count 2 2006.257.15:01:33.10#ibcon#read 4, iclass 17, count 2 2006.257.15:01:33.10#ibcon#about to read 5, iclass 17, count 2 2006.257.15:01:33.10#ibcon#read 5, iclass 17, count 2 2006.257.15:01:33.10#ibcon#about to read 6, iclass 17, count 2 2006.257.15:01:33.10#ibcon#read 6, iclass 17, count 2 2006.257.15:01:33.10#ibcon#end of sib2, iclass 17, count 2 2006.257.15:01:33.10#ibcon#*mode == 0, iclass 17, count 2 2006.257.15:01:33.10#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.15:01:33.10#ibcon#[25=AT03-08\r\n] 2006.257.15:01:33.10#ibcon#*before write, iclass 17, count 2 2006.257.15:01:33.10#ibcon#enter sib2, iclass 17, count 2 2006.257.15:01:33.10#ibcon#flushed, iclass 17, count 2 2006.257.15:01:33.10#ibcon#about to write, iclass 17, count 2 2006.257.15:01:33.10#ibcon#wrote, iclass 17, count 2 2006.257.15:01:33.10#ibcon#about to read 3, iclass 17, count 2 2006.257.15:01:33.13#ibcon#read 3, iclass 17, count 2 2006.257.15:01:33.13#ibcon#about to read 4, iclass 17, count 2 2006.257.15:01:33.13#ibcon#read 4, iclass 17, count 2 2006.257.15:01:33.13#ibcon#about to read 5, iclass 17, count 2 2006.257.15:01:33.13#ibcon#read 5, iclass 17, count 2 2006.257.15:01:33.13#ibcon#about to read 6, iclass 17, count 2 2006.257.15:01:33.13#ibcon#read 6, iclass 17, count 2 2006.257.15:01:33.13#ibcon#end of sib2, iclass 17, count 2 2006.257.15:01:33.13#ibcon#*after write, iclass 17, count 2 2006.257.15:01:33.13#ibcon#*before return 0, iclass 17, count 2 2006.257.15:01:33.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:33.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:33.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.15:01:33.13#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:33.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:33.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:33.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:33.25#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:01:33.25#ibcon#first serial, iclass 17, count 0 2006.257.15:01:33.25#ibcon#enter sib2, iclass 17, count 0 2006.257.15:01:33.25#ibcon#flushed, iclass 17, count 0 2006.257.15:01:33.25#ibcon#about to write, iclass 17, count 0 2006.257.15:01:33.25#ibcon#wrote, iclass 17, count 0 2006.257.15:01:33.25#ibcon#about to read 3, iclass 17, count 0 2006.257.15:01:33.27#ibcon#read 3, iclass 17, count 0 2006.257.15:01:33.27#ibcon#about to read 4, iclass 17, count 0 2006.257.15:01:33.27#ibcon#read 4, iclass 17, count 0 2006.257.15:01:33.27#ibcon#about to read 5, iclass 17, count 0 2006.257.15:01:33.27#ibcon#read 5, iclass 17, count 0 2006.257.15:01:33.27#ibcon#about to read 6, iclass 17, count 0 2006.257.15:01:33.27#ibcon#read 6, iclass 17, count 0 2006.257.15:01:33.27#ibcon#end of sib2, iclass 17, count 0 2006.257.15:01:33.27#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:01:33.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:01:33.27#ibcon#[25=USB\r\n] 2006.257.15:01:33.27#ibcon#*before write, iclass 17, count 0 2006.257.15:01:33.27#ibcon#enter sib2, iclass 17, count 0 2006.257.15:01:33.27#ibcon#flushed, iclass 17, count 0 2006.257.15:01:33.27#ibcon#about to write, iclass 17, count 0 2006.257.15:01:33.27#ibcon#wrote, iclass 17, count 0 2006.257.15:01:33.27#ibcon#about to read 3, iclass 17, count 0 2006.257.15:01:33.30#ibcon#read 3, iclass 17, count 0 2006.257.15:01:33.30#ibcon#about to read 4, iclass 17, count 0 2006.257.15:01:33.30#ibcon#read 4, iclass 17, count 0 2006.257.15:01:33.30#ibcon#about to read 5, iclass 17, count 0 2006.257.15:01:33.30#ibcon#read 5, iclass 17, count 0 2006.257.15:01:33.30#ibcon#about to read 6, iclass 17, count 0 2006.257.15:01:33.30#ibcon#read 6, iclass 17, count 0 2006.257.15:01:33.30#ibcon#end of sib2, iclass 17, count 0 2006.257.15:01:33.30#ibcon#*after write, iclass 17, count 0 2006.257.15:01:33.30#ibcon#*before return 0, iclass 17, count 0 2006.257.15:01:33.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:33.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:33.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:01:33.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:01:33.30$vck44/valo=4,624.99 2006.257.15:01:33.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.15:01:33.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.15:01:33.30#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:33.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:33.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:33.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:33.30#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:01:33.30#ibcon#first serial, iclass 19, count 0 2006.257.15:01:33.30#ibcon#enter sib2, iclass 19, count 0 2006.257.15:01:33.30#ibcon#flushed, iclass 19, count 0 2006.257.15:01:33.30#ibcon#about to write, iclass 19, count 0 2006.257.15:01:33.30#ibcon#wrote, iclass 19, count 0 2006.257.15:01:33.30#ibcon#about to read 3, iclass 19, count 0 2006.257.15:01:33.32#ibcon#read 3, iclass 19, count 0 2006.257.15:01:33.32#ibcon#about to read 4, iclass 19, count 0 2006.257.15:01:33.32#ibcon#read 4, iclass 19, count 0 2006.257.15:01:33.32#ibcon#about to read 5, iclass 19, count 0 2006.257.15:01:33.32#ibcon#read 5, iclass 19, count 0 2006.257.15:01:33.32#ibcon#about to read 6, iclass 19, count 0 2006.257.15:01:33.32#ibcon#read 6, iclass 19, count 0 2006.257.15:01:33.32#ibcon#end of sib2, iclass 19, count 0 2006.257.15:01:33.32#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:01:33.32#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:01:33.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:01:33.32#ibcon#*before write, iclass 19, count 0 2006.257.15:01:33.32#ibcon#enter sib2, iclass 19, count 0 2006.257.15:01:33.32#ibcon#flushed, iclass 19, count 0 2006.257.15:01:33.32#ibcon#about to write, iclass 19, count 0 2006.257.15:01:33.32#ibcon#wrote, iclass 19, count 0 2006.257.15:01:33.32#ibcon#about to read 3, iclass 19, count 0 2006.257.15:01:33.36#ibcon#read 3, iclass 19, count 0 2006.257.15:01:33.36#ibcon#about to read 4, iclass 19, count 0 2006.257.15:01:33.36#ibcon#read 4, iclass 19, count 0 2006.257.15:01:33.36#ibcon#about to read 5, iclass 19, count 0 2006.257.15:01:33.36#ibcon#read 5, iclass 19, count 0 2006.257.15:01:33.36#ibcon#about to read 6, iclass 19, count 0 2006.257.15:01:33.36#ibcon#read 6, iclass 19, count 0 2006.257.15:01:33.36#ibcon#end of sib2, iclass 19, count 0 2006.257.15:01:33.36#ibcon#*after write, iclass 19, count 0 2006.257.15:01:33.36#ibcon#*before return 0, iclass 19, count 0 2006.257.15:01:33.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:33.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:33.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:01:33.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:01:33.36$vck44/va=4,7 2006.257.15:01:33.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.15:01:33.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.15:01:33.36#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:33.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:33.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:33.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:33.42#ibcon#enter wrdev, iclass 21, count 2 2006.257.15:01:33.42#ibcon#first serial, iclass 21, count 2 2006.257.15:01:33.42#ibcon#enter sib2, iclass 21, count 2 2006.257.15:01:33.42#ibcon#flushed, iclass 21, count 2 2006.257.15:01:33.42#ibcon#about to write, iclass 21, count 2 2006.257.15:01:33.42#ibcon#wrote, iclass 21, count 2 2006.257.15:01:33.42#ibcon#about to read 3, iclass 21, count 2 2006.257.15:01:33.44#ibcon#read 3, iclass 21, count 2 2006.257.15:01:33.44#ibcon#about to read 4, iclass 21, count 2 2006.257.15:01:33.44#ibcon#read 4, iclass 21, count 2 2006.257.15:01:33.44#ibcon#about to read 5, iclass 21, count 2 2006.257.15:01:33.44#ibcon#read 5, iclass 21, count 2 2006.257.15:01:33.44#ibcon#about to read 6, iclass 21, count 2 2006.257.15:01:33.44#ibcon#read 6, iclass 21, count 2 2006.257.15:01:33.44#ibcon#end of sib2, iclass 21, count 2 2006.257.15:01:33.44#ibcon#*mode == 0, iclass 21, count 2 2006.257.15:01:33.44#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.15:01:33.44#ibcon#[25=AT04-07\r\n] 2006.257.15:01:33.44#ibcon#*before write, iclass 21, count 2 2006.257.15:01:33.44#ibcon#enter sib2, iclass 21, count 2 2006.257.15:01:33.44#ibcon#flushed, iclass 21, count 2 2006.257.15:01:33.44#ibcon#about to write, iclass 21, count 2 2006.257.15:01:33.44#ibcon#wrote, iclass 21, count 2 2006.257.15:01:33.44#ibcon#about to read 3, iclass 21, count 2 2006.257.15:01:33.47#ibcon#read 3, iclass 21, count 2 2006.257.15:01:33.47#ibcon#about to read 4, iclass 21, count 2 2006.257.15:01:33.47#ibcon#read 4, iclass 21, count 2 2006.257.15:01:33.47#ibcon#about to read 5, iclass 21, count 2 2006.257.15:01:33.47#ibcon#read 5, iclass 21, count 2 2006.257.15:01:33.47#ibcon#about to read 6, iclass 21, count 2 2006.257.15:01:33.47#ibcon#read 6, iclass 21, count 2 2006.257.15:01:33.47#ibcon#end of sib2, iclass 21, count 2 2006.257.15:01:33.47#ibcon#*after write, iclass 21, count 2 2006.257.15:01:33.47#ibcon#*before return 0, iclass 21, count 2 2006.257.15:01:33.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:33.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:33.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.15:01:33.47#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:33.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:33.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:33.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:33.59#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:01:33.59#ibcon#first serial, iclass 21, count 0 2006.257.15:01:33.59#ibcon#enter sib2, iclass 21, count 0 2006.257.15:01:33.59#ibcon#flushed, iclass 21, count 0 2006.257.15:01:33.59#ibcon#about to write, iclass 21, count 0 2006.257.15:01:33.59#ibcon#wrote, iclass 21, count 0 2006.257.15:01:33.59#ibcon#about to read 3, iclass 21, count 0 2006.257.15:01:33.61#ibcon#read 3, iclass 21, count 0 2006.257.15:01:33.61#ibcon#about to read 4, iclass 21, count 0 2006.257.15:01:33.61#ibcon#read 4, iclass 21, count 0 2006.257.15:01:33.61#ibcon#about to read 5, iclass 21, count 0 2006.257.15:01:33.61#ibcon#read 5, iclass 21, count 0 2006.257.15:01:33.61#ibcon#about to read 6, iclass 21, count 0 2006.257.15:01:33.61#ibcon#read 6, iclass 21, count 0 2006.257.15:01:33.61#ibcon#end of sib2, iclass 21, count 0 2006.257.15:01:33.61#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:01:33.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:01:33.61#ibcon#[25=USB\r\n] 2006.257.15:01:33.61#ibcon#*before write, iclass 21, count 0 2006.257.15:01:33.61#ibcon#enter sib2, iclass 21, count 0 2006.257.15:01:33.61#ibcon#flushed, iclass 21, count 0 2006.257.15:01:33.61#ibcon#about to write, iclass 21, count 0 2006.257.15:01:33.61#ibcon#wrote, iclass 21, count 0 2006.257.15:01:33.61#ibcon#about to read 3, iclass 21, count 0 2006.257.15:01:33.64#ibcon#read 3, iclass 21, count 0 2006.257.15:01:33.64#ibcon#about to read 4, iclass 21, count 0 2006.257.15:01:33.64#ibcon#read 4, iclass 21, count 0 2006.257.15:01:33.64#ibcon#about to read 5, iclass 21, count 0 2006.257.15:01:33.64#ibcon#read 5, iclass 21, count 0 2006.257.15:01:33.64#ibcon#about to read 6, iclass 21, count 0 2006.257.15:01:33.64#ibcon#read 6, iclass 21, count 0 2006.257.15:01:33.64#ibcon#end of sib2, iclass 21, count 0 2006.257.15:01:33.64#ibcon#*after write, iclass 21, count 0 2006.257.15:01:33.64#ibcon#*before return 0, iclass 21, count 0 2006.257.15:01:33.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:33.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:33.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:01:33.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:01:33.64$vck44/valo=5,734.99 2006.257.15:01:33.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.15:01:33.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.15:01:33.64#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:33.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:33.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:33.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:33.64#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:01:33.64#ibcon#first serial, iclass 23, count 0 2006.257.15:01:33.64#ibcon#enter sib2, iclass 23, count 0 2006.257.15:01:33.64#ibcon#flushed, iclass 23, count 0 2006.257.15:01:33.64#ibcon#about to write, iclass 23, count 0 2006.257.15:01:33.64#ibcon#wrote, iclass 23, count 0 2006.257.15:01:33.64#ibcon#about to read 3, iclass 23, count 0 2006.257.15:01:33.66#ibcon#read 3, iclass 23, count 0 2006.257.15:01:33.66#ibcon#about to read 4, iclass 23, count 0 2006.257.15:01:33.66#ibcon#read 4, iclass 23, count 0 2006.257.15:01:33.66#ibcon#about to read 5, iclass 23, count 0 2006.257.15:01:33.66#ibcon#read 5, iclass 23, count 0 2006.257.15:01:33.66#ibcon#about to read 6, iclass 23, count 0 2006.257.15:01:33.66#ibcon#read 6, iclass 23, count 0 2006.257.15:01:33.66#ibcon#end of sib2, iclass 23, count 0 2006.257.15:01:33.66#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:01:33.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:01:33.66#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:01:33.66#ibcon#*before write, iclass 23, count 0 2006.257.15:01:33.66#ibcon#enter sib2, iclass 23, count 0 2006.257.15:01:33.66#ibcon#flushed, iclass 23, count 0 2006.257.15:01:33.66#ibcon#about to write, iclass 23, count 0 2006.257.15:01:33.66#ibcon#wrote, iclass 23, count 0 2006.257.15:01:33.66#ibcon#about to read 3, iclass 23, count 0 2006.257.15:01:33.70#ibcon#read 3, iclass 23, count 0 2006.257.15:01:33.70#ibcon#about to read 4, iclass 23, count 0 2006.257.15:01:33.70#ibcon#read 4, iclass 23, count 0 2006.257.15:01:33.70#ibcon#about to read 5, iclass 23, count 0 2006.257.15:01:33.70#ibcon#read 5, iclass 23, count 0 2006.257.15:01:33.70#ibcon#about to read 6, iclass 23, count 0 2006.257.15:01:33.70#ibcon#read 6, iclass 23, count 0 2006.257.15:01:33.70#ibcon#end of sib2, iclass 23, count 0 2006.257.15:01:33.70#ibcon#*after write, iclass 23, count 0 2006.257.15:01:33.70#ibcon#*before return 0, iclass 23, count 0 2006.257.15:01:33.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:33.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:33.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:01:33.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:01:33.70$vck44/va=5,4 2006.257.15:01:33.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.15:01:33.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.15:01:33.70#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:33.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:33.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:33.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:33.76#ibcon#enter wrdev, iclass 25, count 2 2006.257.15:01:33.76#ibcon#first serial, iclass 25, count 2 2006.257.15:01:33.76#ibcon#enter sib2, iclass 25, count 2 2006.257.15:01:33.76#ibcon#flushed, iclass 25, count 2 2006.257.15:01:33.76#ibcon#about to write, iclass 25, count 2 2006.257.15:01:33.76#ibcon#wrote, iclass 25, count 2 2006.257.15:01:33.76#ibcon#about to read 3, iclass 25, count 2 2006.257.15:01:33.78#ibcon#read 3, iclass 25, count 2 2006.257.15:01:33.78#ibcon#about to read 4, iclass 25, count 2 2006.257.15:01:33.78#ibcon#read 4, iclass 25, count 2 2006.257.15:01:33.78#ibcon#about to read 5, iclass 25, count 2 2006.257.15:01:33.78#ibcon#read 5, iclass 25, count 2 2006.257.15:01:33.78#ibcon#about to read 6, iclass 25, count 2 2006.257.15:01:33.78#ibcon#read 6, iclass 25, count 2 2006.257.15:01:33.78#ibcon#end of sib2, iclass 25, count 2 2006.257.15:01:33.78#ibcon#*mode == 0, iclass 25, count 2 2006.257.15:01:33.78#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.15:01:33.78#ibcon#[25=AT05-04\r\n] 2006.257.15:01:33.78#ibcon#*before write, iclass 25, count 2 2006.257.15:01:33.78#ibcon#enter sib2, iclass 25, count 2 2006.257.15:01:33.78#ibcon#flushed, iclass 25, count 2 2006.257.15:01:33.78#ibcon#about to write, iclass 25, count 2 2006.257.15:01:33.78#ibcon#wrote, iclass 25, count 2 2006.257.15:01:33.78#ibcon#about to read 3, iclass 25, count 2 2006.257.15:01:33.81#ibcon#read 3, iclass 25, count 2 2006.257.15:01:33.81#ibcon#about to read 4, iclass 25, count 2 2006.257.15:01:33.81#ibcon#read 4, iclass 25, count 2 2006.257.15:01:33.81#ibcon#about to read 5, iclass 25, count 2 2006.257.15:01:33.81#ibcon#read 5, iclass 25, count 2 2006.257.15:01:33.81#ibcon#about to read 6, iclass 25, count 2 2006.257.15:01:33.81#ibcon#read 6, iclass 25, count 2 2006.257.15:01:33.81#ibcon#end of sib2, iclass 25, count 2 2006.257.15:01:33.81#ibcon#*after write, iclass 25, count 2 2006.257.15:01:33.81#ibcon#*before return 0, iclass 25, count 2 2006.257.15:01:33.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:33.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:33.81#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.15:01:33.81#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:33.81#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:33.93#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:33.93#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:33.93#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:01:33.93#ibcon#first serial, iclass 25, count 0 2006.257.15:01:33.93#ibcon#enter sib2, iclass 25, count 0 2006.257.15:01:33.93#ibcon#flushed, iclass 25, count 0 2006.257.15:01:33.93#ibcon#about to write, iclass 25, count 0 2006.257.15:01:33.93#ibcon#wrote, iclass 25, count 0 2006.257.15:01:33.93#ibcon#about to read 3, iclass 25, count 0 2006.257.15:01:33.95#ibcon#read 3, iclass 25, count 0 2006.257.15:01:33.95#ibcon#about to read 4, iclass 25, count 0 2006.257.15:01:33.95#ibcon#read 4, iclass 25, count 0 2006.257.15:01:33.95#ibcon#about to read 5, iclass 25, count 0 2006.257.15:01:33.95#ibcon#read 5, iclass 25, count 0 2006.257.15:01:33.95#ibcon#about to read 6, iclass 25, count 0 2006.257.15:01:33.95#ibcon#read 6, iclass 25, count 0 2006.257.15:01:33.95#ibcon#end of sib2, iclass 25, count 0 2006.257.15:01:33.95#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:01:33.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:01:33.95#ibcon#[25=USB\r\n] 2006.257.15:01:33.95#ibcon#*before write, iclass 25, count 0 2006.257.15:01:33.95#ibcon#enter sib2, iclass 25, count 0 2006.257.15:01:33.95#ibcon#flushed, iclass 25, count 0 2006.257.15:01:33.95#ibcon#about to write, iclass 25, count 0 2006.257.15:01:33.95#ibcon#wrote, iclass 25, count 0 2006.257.15:01:33.95#ibcon#about to read 3, iclass 25, count 0 2006.257.15:01:33.98#ibcon#read 3, iclass 25, count 0 2006.257.15:01:33.98#ibcon#about to read 4, iclass 25, count 0 2006.257.15:01:33.98#ibcon#read 4, iclass 25, count 0 2006.257.15:01:33.98#ibcon#about to read 5, iclass 25, count 0 2006.257.15:01:33.98#ibcon#read 5, iclass 25, count 0 2006.257.15:01:33.98#ibcon#about to read 6, iclass 25, count 0 2006.257.15:01:33.98#ibcon#read 6, iclass 25, count 0 2006.257.15:01:33.98#ibcon#end of sib2, iclass 25, count 0 2006.257.15:01:33.98#ibcon#*after write, iclass 25, count 0 2006.257.15:01:33.98#ibcon#*before return 0, iclass 25, count 0 2006.257.15:01:33.98#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:33.98#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:33.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:01:33.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:01:33.98$vck44/valo=6,814.99 2006.257.15:01:33.98#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.15:01:33.98#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.15:01:33.98#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:33.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:33.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:33.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:33.98#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:01:33.98#ibcon#first serial, iclass 27, count 0 2006.257.15:01:33.98#ibcon#enter sib2, iclass 27, count 0 2006.257.15:01:33.98#ibcon#flushed, iclass 27, count 0 2006.257.15:01:33.98#ibcon#about to write, iclass 27, count 0 2006.257.15:01:33.98#ibcon#wrote, iclass 27, count 0 2006.257.15:01:33.98#ibcon#about to read 3, iclass 27, count 0 2006.257.15:01:34.00#ibcon#read 3, iclass 27, count 0 2006.257.15:01:34.00#ibcon#about to read 4, iclass 27, count 0 2006.257.15:01:34.00#ibcon#read 4, iclass 27, count 0 2006.257.15:01:34.00#ibcon#about to read 5, iclass 27, count 0 2006.257.15:01:34.00#ibcon#read 5, iclass 27, count 0 2006.257.15:01:34.00#ibcon#about to read 6, iclass 27, count 0 2006.257.15:01:34.00#ibcon#read 6, iclass 27, count 0 2006.257.15:01:34.00#ibcon#end of sib2, iclass 27, count 0 2006.257.15:01:34.00#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:01:34.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:01:34.00#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:01:34.00#ibcon#*before write, iclass 27, count 0 2006.257.15:01:34.00#ibcon#enter sib2, iclass 27, count 0 2006.257.15:01:34.00#ibcon#flushed, iclass 27, count 0 2006.257.15:01:34.00#ibcon#about to write, iclass 27, count 0 2006.257.15:01:34.00#ibcon#wrote, iclass 27, count 0 2006.257.15:01:34.00#ibcon#about to read 3, iclass 27, count 0 2006.257.15:01:34.04#ibcon#read 3, iclass 27, count 0 2006.257.15:01:34.04#ibcon#about to read 4, iclass 27, count 0 2006.257.15:01:34.04#ibcon#read 4, iclass 27, count 0 2006.257.15:01:34.04#ibcon#about to read 5, iclass 27, count 0 2006.257.15:01:34.04#ibcon#read 5, iclass 27, count 0 2006.257.15:01:34.04#ibcon#about to read 6, iclass 27, count 0 2006.257.15:01:34.04#ibcon#read 6, iclass 27, count 0 2006.257.15:01:34.04#ibcon#end of sib2, iclass 27, count 0 2006.257.15:01:34.04#ibcon#*after write, iclass 27, count 0 2006.257.15:01:34.04#ibcon#*before return 0, iclass 27, count 0 2006.257.15:01:34.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:34.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:34.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:01:34.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:01:34.04$vck44/va=6,4 2006.257.15:01:34.04#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.15:01:34.04#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.15:01:34.04#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:34.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:34.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:34.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:34.10#ibcon#enter wrdev, iclass 29, count 2 2006.257.15:01:34.10#ibcon#first serial, iclass 29, count 2 2006.257.15:01:34.10#ibcon#enter sib2, iclass 29, count 2 2006.257.15:01:34.10#ibcon#flushed, iclass 29, count 2 2006.257.15:01:34.10#ibcon#about to write, iclass 29, count 2 2006.257.15:01:34.10#ibcon#wrote, iclass 29, count 2 2006.257.15:01:34.10#ibcon#about to read 3, iclass 29, count 2 2006.257.15:01:34.12#ibcon#read 3, iclass 29, count 2 2006.257.15:01:34.12#ibcon#about to read 4, iclass 29, count 2 2006.257.15:01:34.12#ibcon#read 4, iclass 29, count 2 2006.257.15:01:34.12#ibcon#about to read 5, iclass 29, count 2 2006.257.15:01:34.12#ibcon#read 5, iclass 29, count 2 2006.257.15:01:34.12#ibcon#about to read 6, iclass 29, count 2 2006.257.15:01:34.12#ibcon#read 6, iclass 29, count 2 2006.257.15:01:34.12#ibcon#end of sib2, iclass 29, count 2 2006.257.15:01:34.12#ibcon#*mode == 0, iclass 29, count 2 2006.257.15:01:34.12#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.15:01:34.12#ibcon#[25=AT06-04\r\n] 2006.257.15:01:34.12#ibcon#*before write, iclass 29, count 2 2006.257.15:01:34.12#ibcon#enter sib2, iclass 29, count 2 2006.257.15:01:34.12#ibcon#flushed, iclass 29, count 2 2006.257.15:01:34.12#ibcon#about to write, iclass 29, count 2 2006.257.15:01:34.12#ibcon#wrote, iclass 29, count 2 2006.257.15:01:34.12#ibcon#about to read 3, iclass 29, count 2 2006.257.15:01:34.15#ibcon#read 3, iclass 29, count 2 2006.257.15:01:34.15#ibcon#about to read 4, iclass 29, count 2 2006.257.15:01:34.15#ibcon#read 4, iclass 29, count 2 2006.257.15:01:34.15#ibcon#about to read 5, iclass 29, count 2 2006.257.15:01:34.15#ibcon#read 5, iclass 29, count 2 2006.257.15:01:34.15#ibcon#about to read 6, iclass 29, count 2 2006.257.15:01:34.15#ibcon#read 6, iclass 29, count 2 2006.257.15:01:34.15#ibcon#end of sib2, iclass 29, count 2 2006.257.15:01:34.15#ibcon#*after write, iclass 29, count 2 2006.257.15:01:34.15#ibcon#*before return 0, iclass 29, count 2 2006.257.15:01:34.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:34.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:34.15#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.15:01:34.15#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:34.15#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:34.27#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:34.27#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:34.27#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:01:34.27#ibcon#first serial, iclass 29, count 0 2006.257.15:01:34.27#ibcon#enter sib2, iclass 29, count 0 2006.257.15:01:34.27#ibcon#flushed, iclass 29, count 0 2006.257.15:01:34.27#ibcon#about to write, iclass 29, count 0 2006.257.15:01:34.27#ibcon#wrote, iclass 29, count 0 2006.257.15:01:34.27#ibcon#about to read 3, iclass 29, count 0 2006.257.15:01:34.29#ibcon#read 3, iclass 29, count 0 2006.257.15:01:34.29#ibcon#about to read 4, iclass 29, count 0 2006.257.15:01:34.29#ibcon#read 4, iclass 29, count 0 2006.257.15:01:34.29#ibcon#about to read 5, iclass 29, count 0 2006.257.15:01:34.29#ibcon#read 5, iclass 29, count 0 2006.257.15:01:34.29#ibcon#about to read 6, iclass 29, count 0 2006.257.15:01:34.29#ibcon#read 6, iclass 29, count 0 2006.257.15:01:34.29#ibcon#end of sib2, iclass 29, count 0 2006.257.15:01:34.29#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:01:34.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:01:34.29#ibcon#[25=USB\r\n] 2006.257.15:01:34.29#ibcon#*before write, iclass 29, count 0 2006.257.15:01:34.29#ibcon#enter sib2, iclass 29, count 0 2006.257.15:01:34.29#ibcon#flushed, iclass 29, count 0 2006.257.15:01:34.29#ibcon#about to write, iclass 29, count 0 2006.257.15:01:34.29#ibcon#wrote, iclass 29, count 0 2006.257.15:01:34.29#ibcon#about to read 3, iclass 29, count 0 2006.257.15:01:34.32#ibcon#read 3, iclass 29, count 0 2006.257.15:01:34.32#ibcon#about to read 4, iclass 29, count 0 2006.257.15:01:34.32#ibcon#read 4, iclass 29, count 0 2006.257.15:01:34.32#ibcon#about to read 5, iclass 29, count 0 2006.257.15:01:34.32#ibcon#read 5, iclass 29, count 0 2006.257.15:01:34.32#ibcon#about to read 6, iclass 29, count 0 2006.257.15:01:34.32#ibcon#read 6, iclass 29, count 0 2006.257.15:01:34.32#ibcon#end of sib2, iclass 29, count 0 2006.257.15:01:34.32#ibcon#*after write, iclass 29, count 0 2006.257.15:01:34.32#ibcon#*before return 0, iclass 29, count 0 2006.257.15:01:34.32#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:34.32#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:34.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:01:34.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:01:34.32$vck44/valo=7,864.99 2006.257.15:01:34.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.15:01:34.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.15:01:34.32#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:34.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:34.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:34.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:34.32#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:01:34.32#ibcon#first serial, iclass 31, count 0 2006.257.15:01:34.32#ibcon#enter sib2, iclass 31, count 0 2006.257.15:01:34.32#ibcon#flushed, iclass 31, count 0 2006.257.15:01:34.32#ibcon#about to write, iclass 31, count 0 2006.257.15:01:34.32#ibcon#wrote, iclass 31, count 0 2006.257.15:01:34.32#ibcon#about to read 3, iclass 31, count 0 2006.257.15:01:34.34#ibcon#read 3, iclass 31, count 0 2006.257.15:01:34.34#ibcon#about to read 4, iclass 31, count 0 2006.257.15:01:34.34#ibcon#read 4, iclass 31, count 0 2006.257.15:01:34.34#ibcon#about to read 5, iclass 31, count 0 2006.257.15:01:34.34#ibcon#read 5, iclass 31, count 0 2006.257.15:01:34.34#ibcon#about to read 6, iclass 31, count 0 2006.257.15:01:34.34#ibcon#read 6, iclass 31, count 0 2006.257.15:01:34.34#ibcon#end of sib2, iclass 31, count 0 2006.257.15:01:34.34#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:01:34.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:01:34.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:01:34.34#ibcon#*before write, iclass 31, count 0 2006.257.15:01:34.34#ibcon#enter sib2, iclass 31, count 0 2006.257.15:01:34.34#ibcon#flushed, iclass 31, count 0 2006.257.15:01:34.34#ibcon#about to write, iclass 31, count 0 2006.257.15:01:34.34#ibcon#wrote, iclass 31, count 0 2006.257.15:01:34.34#ibcon#about to read 3, iclass 31, count 0 2006.257.15:01:34.38#ibcon#read 3, iclass 31, count 0 2006.257.15:01:34.38#ibcon#about to read 4, iclass 31, count 0 2006.257.15:01:34.38#ibcon#read 4, iclass 31, count 0 2006.257.15:01:34.38#ibcon#about to read 5, iclass 31, count 0 2006.257.15:01:34.38#ibcon#read 5, iclass 31, count 0 2006.257.15:01:34.38#ibcon#about to read 6, iclass 31, count 0 2006.257.15:01:34.38#ibcon#read 6, iclass 31, count 0 2006.257.15:01:34.38#ibcon#end of sib2, iclass 31, count 0 2006.257.15:01:34.38#ibcon#*after write, iclass 31, count 0 2006.257.15:01:34.38#ibcon#*before return 0, iclass 31, count 0 2006.257.15:01:34.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:34.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:34.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:01:34.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:01:34.38$vck44/va=7,4 2006.257.15:01:34.38#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.15:01:34.38#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.15:01:34.38#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:34.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:34.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:34.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:34.44#ibcon#enter wrdev, iclass 33, count 2 2006.257.15:01:34.44#ibcon#first serial, iclass 33, count 2 2006.257.15:01:34.44#ibcon#enter sib2, iclass 33, count 2 2006.257.15:01:34.44#ibcon#flushed, iclass 33, count 2 2006.257.15:01:34.44#ibcon#about to write, iclass 33, count 2 2006.257.15:01:34.44#ibcon#wrote, iclass 33, count 2 2006.257.15:01:34.44#ibcon#about to read 3, iclass 33, count 2 2006.257.15:01:34.46#ibcon#read 3, iclass 33, count 2 2006.257.15:01:34.46#ibcon#about to read 4, iclass 33, count 2 2006.257.15:01:34.46#ibcon#read 4, iclass 33, count 2 2006.257.15:01:34.46#ibcon#about to read 5, iclass 33, count 2 2006.257.15:01:34.46#ibcon#read 5, iclass 33, count 2 2006.257.15:01:34.46#ibcon#about to read 6, iclass 33, count 2 2006.257.15:01:34.46#ibcon#read 6, iclass 33, count 2 2006.257.15:01:34.46#ibcon#end of sib2, iclass 33, count 2 2006.257.15:01:34.46#ibcon#*mode == 0, iclass 33, count 2 2006.257.15:01:34.46#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.15:01:34.46#ibcon#[25=AT07-04\r\n] 2006.257.15:01:34.46#ibcon#*before write, iclass 33, count 2 2006.257.15:01:34.46#ibcon#enter sib2, iclass 33, count 2 2006.257.15:01:34.46#ibcon#flushed, iclass 33, count 2 2006.257.15:01:34.46#ibcon#about to write, iclass 33, count 2 2006.257.15:01:34.46#ibcon#wrote, iclass 33, count 2 2006.257.15:01:34.46#ibcon#about to read 3, iclass 33, count 2 2006.257.15:01:34.49#ibcon#read 3, iclass 33, count 2 2006.257.15:01:34.49#ibcon#about to read 4, iclass 33, count 2 2006.257.15:01:34.49#ibcon#read 4, iclass 33, count 2 2006.257.15:01:34.49#ibcon#about to read 5, iclass 33, count 2 2006.257.15:01:34.49#ibcon#read 5, iclass 33, count 2 2006.257.15:01:34.49#ibcon#about to read 6, iclass 33, count 2 2006.257.15:01:34.49#ibcon#read 6, iclass 33, count 2 2006.257.15:01:34.49#ibcon#end of sib2, iclass 33, count 2 2006.257.15:01:34.49#ibcon#*after write, iclass 33, count 2 2006.257.15:01:34.49#ibcon#*before return 0, iclass 33, count 2 2006.257.15:01:34.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:34.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:34.49#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.15:01:34.49#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:34.49#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:34.61#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:34.61#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:34.61#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:01:34.61#ibcon#first serial, iclass 33, count 0 2006.257.15:01:34.61#ibcon#enter sib2, iclass 33, count 0 2006.257.15:01:34.61#ibcon#flushed, iclass 33, count 0 2006.257.15:01:34.61#ibcon#about to write, iclass 33, count 0 2006.257.15:01:34.61#ibcon#wrote, iclass 33, count 0 2006.257.15:01:34.61#ibcon#about to read 3, iclass 33, count 0 2006.257.15:01:34.63#ibcon#read 3, iclass 33, count 0 2006.257.15:01:34.63#ibcon#about to read 4, iclass 33, count 0 2006.257.15:01:34.63#ibcon#read 4, iclass 33, count 0 2006.257.15:01:34.63#ibcon#about to read 5, iclass 33, count 0 2006.257.15:01:34.63#ibcon#read 5, iclass 33, count 0 2006.257.15:01:34.63#ibcon#about to read 6, iclass 33, count 0 2006.257.15:01:34.63#ibcon#read 6, iclass 33, count 0 2006.257.15:01:34.63#ibcon#end of sib2, iclass 33, count 0 2006.257.15:01:34.63#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:01:34.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:01:34.63#ibcon#[25=USB\r\n] 2006.257.15:01:34.63#ibcon#*before write, iclass 33, count 0 2006.257.15:01:34.63#ibcon#enter sib2, iclass 33, count 0 2006.257.15:01:34.63#ibcon#flushed, iclass 33, count 0 2006.257.15:01:34.63#ibcon#about to write, iclass 33, count 0 2006.257.15:01:34.63#ibcon#wrote, iclass 33, count 0 2006.257.15:01:34.63#ibcon#about to read 3, iclass 33, count 0 2006.257.15:01:34.66#ibcon#read 3, iclass 33, count 0 2006.257.15:01:34.66#ibcon#about to read 4, iclass 33, count 0 2006.257.15:01:34.66#ibcon#read 4, iclass 33, count 0 2006.257.15:01:34.66#ibcon#about to read 5, iclass 33, count 0 2006.257.15:01:34.66#ibcon#read 5, iclass 33, count 0 2006.257.15:01:34.66#ibcon#about to read 6, iclass 33, count 0 2006.257.15:01:34.66#ibcon#read 6, iclass 33, count 0 2006.257.15:01:34.66#ibcon#end of sib2, iclass 33, count 0 2006.257.15:01:34.66#ibcon#*after write, iclass 33, count 0 2006.257.15:01:34.66#ibcon#*before return 0, iclass 33, count 0 2006.257.15:01:34.66#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:34.66#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:34.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:01:34.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:01:34.66$vck44/valo=8,884.99 2006.257.15:01:34.66#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.15:01:34.66#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.15:01:34.66#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:34.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:34.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:34.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:34.66#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:01:34.66#ibcon#first serial, iclass 35, count 0 2006.257.15:01:34.66#ibcon#enter sib2, iclass 35, count 0 2006.257.15:01:34.66#ibcon#flushed, iclass 35, count 0 2006.257.15:01:34.66#ibcon#about to write, iclass 35, count 0 2006.257.15:01:34.66#ibcon#wrote, iclass 35, count 0 2006.257.15:01:34.66#ibcon#about to read 3, iclass 35, count 0 2006.257.15:01:34.68#ibcon#read 3, iclass 35, count 0 2006.257.15:01:34.68#ibcon#about to read 4, iclass 35, count 0 2006.257.15:01:34.68#ibcon#read 4, iclass 35, count 0 2006.257.15:01:34.68#ibcon#about to read 5, iclass 35, count 0 2006.257.15:01:34.68#ibcon#read 5, iclass 35, count 0 2006.257.15:01:34.68#ibcon#about to read 6, iclass 35, count 0 2006.257.15:01:34.68#ibcon#read 6, iclass 35, count 0 2006.257.15:01:34.68#ibcon#end of sib2, iclass 35, count 0 2006.257.15:01:34.68#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:01:34.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:01:34.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:01:34.68#ibcon#*before write, iclass 35, count 0 2006.257.15:01:34.68#ibcon#enter sib2, iclass 35, count 0 2006.257.15:01:34.68#ibcon#flushed, iclass 35, count 0 2006.257.15:01:34.68#ibcon#about to write, iclass 35, count 0 2006.257.15:01:34.68#ibcon#wrote, iclass 35, count 0 2006.257.15:01:34.68#ibcon#about to read 3, iclass 35, count 0 2006.257.15:01:34.72#ibcon#read 3, iclass 35, count 0 2006.257.15:01:34.72#ibcon#about to read 4, iclass 35, count 0 2006.257.15:01:34.72#ibcon#read 4, iclass 35, count 0 2006.257.15:01:34.72#ibcon#about to read 5, iclass 35, count 0 2006.257.15:01:34.72#ibcon#read 5, iclass 35, count 0 2006.257.15:01:34.72#ibcon#about to read 6, iclass 35, count 0 2006.257.15:01:34.72#ibcon#read 6, iclass 35, count 0 2006.257.15:01:34.72#ibcon#end of sib2, iclass 35, count 0 2006.257.15:01:34.72#ibcon#*after write, iclass 35, count 0 2006.257.15:01:34.72#ibcon#*before return 0, iclass 35, count 0 2006.257.15:01:34.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:34.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:34.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:01:34.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:01:34.72$vck44/va=8,4 2006.257.15:01:34.72#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.15:01:34.72#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.15:01:34.72#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:34.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:01:34.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:01:34.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:01:34.78#ibcon#enter wrdev, iclass 37, count 2 2006.257.15:01:34.78#ibcon#first serial, iclass 37, count 2 2006.257.15:01:34.78#ibcon#enter sib2, iclass 37, count 2 2006.257.15:01:34.78#ibcon#flushed, iclass 37, count 2 2006.257.15:01:34.78#ibcon#about to write, iclass 37, count 2 2006.257.15:01:34.78#ibcon#wrote, iclass 37, count 2 2006.257.15:01:34.78#ibcon#about to read 3, iclass 37, count 2 2006.257.15:01:34.80#ibcon#read 3, iclass 37, count 2 2006.257.15:01:34.80#ibcon#about to read 4, iclass 37, count 2 2006.257.15:01:34.80#ibcon#read 4, iclass 37, count 2 2006.257.15:01:34.80#ibcon#about to read 5, iclass 37, count 2 2006.257.15:01:34.80#ibcon#read 5, iclass 37, count 2 2006.257.15:01:34.80#ibcon#about to read 6, iclass 37, count 2 2006.257.15:01:34.80#ibcon#read 6, iclass 37, count 2 2006.257.15:01:34.80#ibcon#end of sib2, iclass 37, count 2 2006.257.15:01:34.80#ibcon#*mode == 0, iclass 37, count 2 2006.257.15:01:34.80#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.15:01:34.80#ibcon#[25=AT08-04\r\n] 2006.257.15:01:34.80#ibcon#*before write, iclass 37, count 2 2006.257.15:01:34.80#ibcon#enter sib2, iclass 37, count 2 2006.257.15:01:34.80#ibcon#flushed, iclass 37, count 2 2006.257.15:01:34.80#ibcon#about to write, iclass 37, count 2 2006.257.15:01:34.80#ibcon#wrote, iclass 37, count 2 2006.257.15:01:34.80#ibcon#about to read 3, iclass 37, count 2 2006.257.15:01:34.83#ibcon#read 3, iclass 37, count 2 2006.257.15:01:34.83#ibcon#about to read 4, iclass 37, count 2 2006.257.15:01:34.83#ibcon#read 4, iclass 37, count 2 2006.257.15:01:34.83#ibcon#about to read 5, iclass 37, count 2 2006.257.15:01:34.83#ibcon#read 5, iclass 37, count 2 2006.257.15:01:34.83#ibcon#about to read 6, iclass 37, count 2 2006.257.15:01:34.83#ibcon#read 6, iclass 37, count 2 2006.257.15:01:34.83#ibcon#end of sib2, iclass 37, count 2 2006.257.15:01:34.83#ibcon#*after write, iclass 37, count 2 2006.257.15:01:34.83#ibcon#*before return 0, iclass 37, count 2 2006.257.15:01:34.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:01:34.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:01:34.83#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.15:01:34.83#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:34.83#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:01:34.95#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:01:34.95#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:01:34.95#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:01:34.95#ibcon#first serial, iclass 37, count 0 2006.257.15:01:34.95#ibcon#enter sib2, iclass 37, count 0 2006.257.15:01:34.95#ibcon#flushed, iclass 37, count 0 2006.257.15:01:34.95#ibcon#about to write, iclass 37, count 0 2006.257.15:01:34.95#ibcon#wrote, iclass 37, count 0 2006.257.15:01:34.95#ibcon#about to read 3, iclass 37, count 0 2006.257.15:01:34.97#ibcon#read 3, iclass 37, count 0 2006.257.15:01:34.97#ibcon#about to read 4, iclass 37, count 0 2006.257.15:01:34.97#ibcon#read 4, iclass 37, count 0 2006.257.15:01:34.97#ibcon#about to read 5, iclass 37, count 0 2006.257.15:01:34.97#ibcon#read 5, iclass 37, count 0 2006.257.15:01:34.97#ibcon#about to read 6, iclass 37, count 0 2006.257.15:01:34.97#ibcon#read 6, iclass 37, count 0 2006.257.15:01:34.97#ibcon#end of sib2, iclass 37, count 0 2006.257.15:01:34.97#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:01:34.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:01:34.97#ibcon#[25=USB\r\n] 2006.257.15:01:34.97#ibcon#*before write, iclass 37, count 0 2006.257.15:01:34.97#ibcon#enter sib2, iclass 37, count 0 2006.257.15:01:34.97#ibcon#flushed, iclass 37, count 0 2006.257.15:01:34.97#ibcon#about to write, iclass 37, count 0 2006.257.15:01:34.97#ibcon#wrote, iclass 37, count 0 2006.257.15:01:34.97#ibcon#about to read 3, iclass 37, count 0 2006.257.15:01:35.00#ibcon#read 3, iclass 37, count 0 2006.257.15:01:35.00#ibcon#about to read 4, iclass 37, count 0 2006.257.15:01:35.00#ibcon#read 4, iclass 37, count 0 2006.257.15:01:35.00#ibcon#about to read 5, iclass 37, count 0 2006.257.15:01:35.00#ibcon#read 5, iclass 37, count 0 2006.257.15:01:35.00#ibcon#about to read 6, iclass 37, count 0 2006.257.15:01:35.00#ibcon#read 6, iclass 37, count 0 2006.257.15:01:35.00#ibcon#end of sib2, iclass 37, count 0 2006.257.15:01:35.00#ibcon#*after write, iclass 37, count 0 2006.257.15:01:35.00#ibcon#*before return 0, iclass 37, count 0 2006.257.15:01:35.00#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:01:35.00#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:01:35.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:01:35.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:01:35.00$vck44/vblo=1,629.99 2006.257.15:01:35.00#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.15:01:35.00#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.15:01:35.00#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:35.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:01:35.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:01:35.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:01:35.00#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:01:35.00#ibcon#first serial, iclass 39, count 0 2006.257.15:01:35.00#ibcon#enter sib2, iclass 39, count 0 2006.257.15:01:35.00#ibcon#flushed, iclass 39, count 0 2006.257.15:01:35.00#ibcon#about to write, iclass 39, count 0 2006.257.15:01:35.00#ibcon#wrote, iclass 39, count 0 2006.257.15:01:35.00#ibcon#about to read 3, iclass 39, count 0 2006.257.15:01:35.02#ibcon#read 3, iclass 39, count 0 2006.257.15:01:35.02#ibcon#about to read 4, iclass 39, count 0 2006.257.15:01:35.02#ibcon#read 4, iclass 39, count 0 2006.257.15:01:35.02#ibcon#about to read 5, iclass 39, count 0 2006.257.15:01:35.02#ibcon#read 5, iclass 39, count 0 2006.257.15:01:35.02#ibcon#about to read 6, iclass 39, count 0 2006.257.15:01:35.02#ibcon#read 6, iclass 39, count 0 2006.257.15:01:35.02#ibcon#end of sib2, iclass 39, count 0 2006.257.15:01:35.02#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:01:35.02#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:01:35.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:01:35.02#ibcon#*before write, iclass 39, count 0 2006.257.15:01:35.02#ibcon#enter sib2, iclass 39, count 0 2006.257.15:01:35.02#ibcon#flushed, iclass 39, count 0 2006.257.15:01:35.02#ibcon#about to write, iclass 39, count 0 2006.257.15:01:35.02#ibcon#wrote, iclass 39, count 0 2006.257.15:01:35.02#ibcon#about to read 3, iclass 39, count 0 2006.257.15:01:35.06#ibcon#read 3, iclass 39, count 0 2006.257.15:01:35.06#ibcon#about to read 4, iclass 39, count 0 2006.257.15:01:35.06#ibcon#read 4, iclass 39, count 0 2006.257.15:01:35.06#ibcon#about to read 5, iclass 39, count 0 2006.257.15:01:35.06#ibcon#read 5, iclass 39, count 0 2006.257.15:01:35.06#ibcon#about to read 6, iclass 39, count 0 2006.257.15:01:35.06#ibcon#read 6, iclass 39, count 0 2006.257.15:01:35.06#ibcon#end of sib2, iclass 39, count 0 2006.257.15:01:35.06#ibcon#*after write, iclass 39, count 0 2006.257.15:01:35.06#ibcon#*before return 0, iclass 39, count 0 2006.257.15:01:35.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:01:35.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:01:35.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:01:35.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:01:35.06$vck44/vb=1,4 2006.257.15:01:35.06#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.15:01:35.06#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.15:01:35.06#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:35.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:01:35.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:01:35.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:01:35.06#ibcon#enter wrdev, iclass 3, count 2 2006.257.15:01:35.06#ibcon#first serial, iclass 3, count 2 2006.257.15:01:35.06#ibcon#enter sib2, iclass 3, count 2 2006.257.15:01:35.06#ibcon#flushed, iclass 3, count 2 2006.257.15:01:35.06#ibcon#about to write, iclass 3, count 2 2006.257.15:01:35.06#ibcon#wrote, iclass 3, count 2 2006.257.15:01:35.06#ibcon#about to read 3, iclass 3, count 2 2006.257.15:01:35.08#ibcon#read 3, iclass 3, count 2 2006.257.15:01:35.08#ibcon#about to read 4, iclass 3, count 2 2006.257.15:01:35.08#ibcon#read 4, iclass 3, count 2 2006.257.15:01:35.08#ibcon#about to read 5, iclass 3, count 2 2006.257.15:01:35.08#ibcon#read 5, iclass 3, count 2 2006.257.15:01:35.08#ibcon#about to read 6, iclass 3, count 2 2006.257.15:01:35.08#ibcon#read 6, iclass 3, count 2 2006.257.15:01:35.08#ibcon#end of sib2, iclass 3, count 2 2006.257.15:01:35.08#ibcon#*mode == 0, iclass 3, count 2 2006.257.15:01:35.08#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.15:01:35.08#ibcon#[27=AT01-04\r\n] 2006.257.15:01:35.08#ibcon#*before write, iclass 3, count 2 2006.257.15:01:35.08#ibcon#enter sib2, iclass 3, count 2 2006.257.15:01:35.08#ibcon#flushed, iclass 3, count 2 2006.257.15:01:35.08#ibcon#about to write, iclass 3, count 2 2006.257.15:01:35.08#ibcon#wrote, iclass 3, count 2 2006.257.15:01:35.08#ibcon#about to read 3, iclass 3, count 2 2006.257.15:01:35.11#ibcon#read 3, iclass 3, count 2 2006.257.15:01:35.11#ibcon#about to read 4, iclass 3, count 2 2006.257.15:01:35.11#ibcon#read 4, iclass 3, count 2 2006.257.15:01:35.11#ibcon#about to read 5, iclass 3, count 2 2006.257.15:01:35.11#ibcon#read 5, iclass 3, count 2 2006.257.15:01:35.11#ibcon#about to read 6, iclass 3, count 2 2006.257.15:01:35.11#ibcon#read 6, iclass 3, count 2 2006.257.15:01:35.11#ibcon#end of sib2, iclass 3, count 2 2006.257.15:01:35.11#ibcon#*after write, iclass 3, count 2 2006.257.15:01:35.11#ibcon#*before return 0, iclass 3, count 2 2006.257.15:01:35.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:01:35.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:01:35.11#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.15:01:35.11#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:35.11#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:01:35.23#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:01:35.23#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:01:35.23#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:01:35.23#ibcon#first serial, iclass 3, count 0 2006.257.15:01:35.23#ibcon#enter sib2, iclass 3, count 0 2006.257.15:01:35.23#ibcon#flushed, iclass 3, count 0 2006.257.15:01:35.23#ibcon#about to write, iclass 3, count 0 2006.257.15:01:35.23#ibcon#wrote, iclass 3, count 0 2006.257.15:01:35.23#ibcon#about to read 3, iclass 3, count 0 2006.257.15:01:35.25#ibcon#read 3, iclass 3, count 0 2006.257.15:01:35.25#ibcon#about to read 4, iclass 3, count 0 2006.257.15:01:35.25#ibcon#read 4, iclass 3, count 0 2006.257.15:01:35.25#ibcon#about to read 5, iclass 3, count 0 2006.257.15:01:35.25#ibcon#read 5, iclass 3, count 0 2006.257.15:01:35.25#ibcon#about to read 6, iclass 3, count 0 2006.257.15:01:35.25#ibcon#read 6, iclass 3, count 0 2006.257.15:01:35.25#ibcon#end of sib2, iclass 3, count 0 2006.257.15:01:35.25#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:01:35.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:01:35.25#ibcon#[27=USB\r\n] 2006.257.15:01:35.25#ibcon#*before write, iclass 3, count 0 2006.257.15:01:35.25#ibcon#enter sib2, iclass 3, count 0 2006.257.15:01:35.25#ibcon#flushed, iclass 3, count 0 2006.257.15:01:35.25#ibcon#about to write, iclass 3, count 0 2006.257.15:01:35.25#ibcon#wrote, iclass 3, count 0 2006.257.15:01:35.25#ibcon#about to read 3, iclass 3, count 0 2006.257.15:01:35.28#ibcon#read 3, iclass 3, count 0 2006.257.15:01:35.28#ibcon#about to read 4, iclass 3, count 0 2006.257.15:01:35.28#ibcon#read 4, iclass 3, count 0 2006.257.15:01:35.28#ibcon#about to read 5, iclass 3, count 0 2006.257.15:01:35.28#ibcon#read 5, iclass 3, count 0 2006.257.15:01:35.28#ibcon#about to read 6, iclass 3, count 0 2006.257.15:01:35.28#ibcon#read 6, iclass 3, count 0 2006.257.15:01:35.28#ibcon#end of sib2, iclass 3, count 0 2006.257.15:01:35.28#ibcon#*after write, iclass 3, count 0 2006.257.15:01:35.28#ibcon#*before return 0, iclass 3, count 0 2006.257.15:01:35.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:01:35.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:01:35.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:01:35.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:01:35.28$vck44/vblo=2,634.99 2006.257.15:01:35.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.15:01:35.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.15:01:35.28#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:35.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:35.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:35.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:35.28#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:01:35.28#ibcon#first serial, iclass 5, count 0 2006.257.15:01:35.28#ibcon#enter sib2, iclass 5, count 0 2006.257.15:01:35.28#ibcon#flushed, iclass 5, count 0 2006.257.15:01:35.28#ibcon#about to write, iclass 5, count 0 2006.257.15:01:35.28#ibcon#wrote, iclass 5, count 0 2006.257.15:01:35.28#ibcon#about to read 3, iclass 5, count 0 2006.257.15:01:35.30#ibcon#read 3, iclass 5, count 0 2006.257.15:01:35.30#ibcon#about to read 4, iclass 5, count 0 2006.257.15:01:35.30#ibcon#read 4, iclass 5, count 0 2006.257.15:01:35.30#ibcon#about to read 5, iclass 5, count 0 2006.257.15:01:35.30#ibcon#read 5, iclass 5, count 0 2006.257.15:01:35.30#ibcon#about to read 6, iclass 5, count 0 2006.257.15:01:35.30#ibcon#read 6, iclass 5, count 0 2006.257.15:01:35.30#ibcon#end of sib2, iclass 5, count 0 2006.257.15:01:35.30#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:01:35.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:01:35.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:01:35.30#ibcon#*before write, iclass 5, count 0 2006.257.15:01:35.30#ibcon#enter sib2, iclass 5, count 0 2006.257.15:01:35.30#ibcon#flushed, iclass 5, count 0 2006.257.15:01:35.30#ibcon#about to write, iclass 5, count 0 2006.257.15:01:35.30#ibcon#wrote, iclass 5, count 0 2006.257.15:01:35.30#ibcon#about to read 3, iclass 5, count 0 2006.257.15:01:35.34#ibcon#read 3, iclass 5, count 0 2006.257.15:01:35.34#ibcon#about to read 4, iclass 5, count 0 2006.257.15:01:35.34#ibcon#read 4, iclass 5, count 0 2006.257.15:01:35.34#ibcon#about to read 5, iclass 5, count 0 2006.257.15:01:35.34#ibcon#read 5, iclass 5, count 0 2006.257.15:01:35.34#ibcon#about to read 6, iclass 5, count 0 2006.257.15:01:35.34#ibcon#read 6, iclass 5, count 0 2006.257.15:01:35.34#ibcon#end of sib2, iclass 5, count 0 2006.257.15:01:35.34#ibcon#*after write, iclass 5, count 0 2006.257.15:01:35.34#ibcon#*before return 0, iclass 5, count 0 2006.257.15:01:35.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:35.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:01:35.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:01:35.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:01:35.34$vck44/vb=2,5 2006.257.15:01:35.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.15:01:35.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.15:01:35.34#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:35.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:35.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:35.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:35.40#ibcon#enter wrdev, iclass 7, count 2 2006.257.15:01:35.40#ibcon#first serial, iclass 7, count 2 2006.257.15:01:35.40#ibcon#enter sib2, iclass 7, count 2 2006.257.15:01:35.40#ibcon#flushed, iclass 7, count 2 2006.257.15:01:35.40#ibcon#about to write, iclass 7, count 2 2006.257.15:01:35.40#ibcon#wrote, iclass 7, count 2 2006.257.15:01:35.40#ibcon#about to read 3, iclass 7, count 2 2006.257.15:01:35.42#ibcon#read 3, iclass 7, count 2 2006.257.15:01:35.42#ibcon#about to read 4, iclass 7, count 2 2006.257.15:01:35.42#ibcon#read 4, iclass 7, count 2 2006.257.15:01:35.42#ibcon#about to read 5, iclass 7, count 2 2006.257.15:01:35.42#ibcon#read 5, iclass 7, count 2 2006.257.15:01:35.42#ibcon#about to read 6, iclass 7, count 2 2006.257.15:01:35.42#ibcon#read 6, iclass 7, count 2 2006.257.15:01:35.42#ibcon#end of sib2, iclass 7, count 2 2006.257.15:01:35.42#ibcon#*mode == 0, iclass 7, count 2 2006.257.15:01:35.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.15:01:35.42#ibcon#[27=AT02-05\r\n] 2006.257.15:01:35.42#ibcon#*before write, iclass 7, count 2 2006.257.15:01:35.42#ibcon#enter sib2, iclass 7, count 2 2006.257.15:01:35.42#ibcon#flushed, iclass 7, count 2 2006.257.15:01:35.42#ibcon#about to write, iclass 7, count 2 2006.257.15:01:35.42#ibcon#wrote, iclass 7, count 2 2006.257.15:01:35.42#ibcon#about to read 3, iclass 7, count 2 2006.257.15:01:35.45#ibcon#read 3, iclass 7, count 2 2006.257.15:01:35.45#ibcon#about to read 4, iclass 7, count 2 2006.257.15:01:35.45#ibcon#read 4, iclass 7, count 2 2006.257.15:01:35.45#ibcon#about to read 5, iclass 7, count 2 2006.257.15:01:35.45#ibcon#read 5, iclass 7, count 2 2006.257.15:01:35.45#ibcon#about to read 6, iclass 7, count 2 2006.257.15:01:35.45#ibcon#read 6, iclass 7, count 2 2006.257.15:01:35.45#ibcon#end of sib2, iclass 7, count 2 2006.257.15:01:35.45#ibcon#*after write, iclass 7, count 2 2006.257.15:01:35.45#ibcon#*before return 0, iclass 7, count 2 2006.257.15:01:35.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:35.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:01:35.53#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.15:01:35.53#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:35.53#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:35.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:35.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:35.57#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:01:35.57#ibcon#first serial, iclass 7, count 0 2006.257.15:01:35.57#ibcon#enter sib2, iclass 7, count 0 2006.257.15:01:35.57#ibcon#flushed, iclass 7, count 0 2006.257.15:01:35.57#ibcon#about to write, iclass 7, count 0 2006.257.15:01:35.57#ibcon#wrote, iclass 7, count 0 2006.257.15:01:35.57#ibcon#about to read 3, iclass 7, count 0 2006.257.15:01:35.59#ibcon#read 3, iclass 7, count 0 2006.257.15:01:35.59#ibcon#about to read 4, iclass 7, count 0 2006.257.15:01:35.59#ibcon#read 4, iclass 7, count 0 2006.257.15:01:35.59#ibcon#about to read 5, iclass 7, count 0 2006.257.15:01:35.59#ibcon#read 5, iclass 7, count 0 2006.257.15:01:35.59#ibcon#about to read 6, iclass 7, count 0 2006.257.15:01:35.59#ibcon#read 6, iclass 7, count 0 2006.257.15:01:35.59#ibcon#end of sib2, iclass 7, count 0 2006.257.15:01:35.59#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:01:35.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:01:35.59#ibcon#[27=USB\r\n] 2006.257.15:01:35.59#ibcon#*before write, iclass 7, count 0 2006.257.15:01:35.59#ibcon#enter sib2, iclass 7, count 0 2006.257.15:01:35.59#ibcon#flushed, iclass 7, count 0 2006.257.15:01:35.59#ibcon#about to write, iclass 7, count 0 2006.257.15:01:35.59#ibcon#wrote, iclass 7, count 0 2006.257.15:01:35.59#ibcon#about to read 3, iclass 7, count 0 2006.257.15:01:35.62#ibcon#read 3, iclass 7, count 0 2006.257.15:01:35.62#ibcon#about to read 4, iclass 7, count 0 2006.257.15:01:35.62#ibcon#read 4, iclass 7, count 0 2006.257.15:01:35.62#ibcon#about to read 5, iclass 7, count 0 2006.257.15:01:35.62#ibcon#read 5, iclass 7, count 0 2006.257.15:01:35.62#ibcon#about to read 6, iclass 7, count 0 2006.257.15:01:35.62#ibcon#read 6, iclass 7, count 0 2006.257.15:01:35.62#ibcon#end of sib2, iclass 7, count 0 2006.257.15:01:35.62#ibcon#*after write, iclass 7, count 0 2006.257.15:01:35.62#ibcon#*before return 0, iclass 7, count 0 2006.257.15:01:35.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:35.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:01:35.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:01:35.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:01:35.62$vck44/vblo=3,649.99 2006.257.15:01:35.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.15:01:35.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.15:01:35.62#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:35.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:35.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:35.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:35.62#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:01:35.62#ibcon#first serial, iclass 11, count 0 2006.257.15:01:35.62#ibcon#enter sib2, iclass 11, count 0 2006.257.15:01:35.62#ibcon#flushed, iclass 11, count 0 2006.257.15:01:35.62#ibcon#about to write, iclass 11, count 0 2006.257.15:01:35.62#ibcon#wrote, iclass 11, count 0 2006.257.15:01:35.62#ibcon#about to read 3, iclass 11, count 0 2006.257.15:01:35.64#ibcon#read 3, iclass 11, count 0 2006.257.15:01:35.64#ibcon#about to read 4, iclass 11, count 0 2006.257.15:01:35.64#ibcon#read 4, iclass 11, count 0 2006.257.15:01:35.64#ibcon#about to read 5, iclass 11, count 0 2006.257.15:01:35.64#ibcon#read 5, iclass 11, count 0 2006.257.15:01:35.64#ibcon#about to read 6, iclass 11, count 0 2006.257.15:01:35.64#ibcon#read 6, iclass 11, count 0 2006.257.15:01:35.64#ibcon#end of sib2, iclass 11, count 0 2006.257.15:01:35.64#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:01:35.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:01:35.64#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:01:35.64#ibcon#*before write, iclass 11, count 0 2006.257.15:01:35.64#ibcon#enter sib2, iclass 11, count 0 2006.257.15:01:35.64#ibcon#flushed, iclass 11, count 0 2006.257.15:01:35.64#ibcon#about to write, iclass 11, count 0 2006.257.15:01:35.64#ibcon#wrote, iclass 11, count 0 2006.257.15:01:35.64#ibcon#about to read 3, iclass 11, count 0 2006.257.15:01:35.68#ibcon#read 3, iclass 11, count 0 2006.257.15:01:35.68#ibcon#about to read 4, iclass 11, count 0 2006.257.15:01:35.68#ibcon#read 4, iclass 11, count 0 2006.257.15:01:35.68#ibcon#about to read 5, iclass 11, count 0 2006.257.15:01:35.68#ibcon#read 5, iclass 11, count 0 2006.257.15:01:35.68#ibcon#about to read 6, iclass 11, count 0 2006.257.15:01:35.68#ibcon#read 6, iclass 11, count 0 2006.257.15:01:35.68#ibcon#end of sib2, iclass 11, count 0 2006.257.15:01:35.68#ibcon#*after write, iclass 11, count 0 2006.257.15:01:35.68#ibcon#*before return 0, iclass 11, count 0 2006.257.15:01:35.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:35.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:01:35.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:01:35.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:01:35.68$vck44/vb=3,4 2006.257.15:01:35.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.15:01:35.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.15:01:35.68#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:35.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:35.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:35.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:35.74#ibcon#enter wrdev, iclass 13, count 2 2006.257.15:01:35.74#ibcon#first serial, iclass 13, count 2 2006.257.15:01:35.74#ibcon#enter sib2, iclass 13, count 2 2006.257.15:01:35.74#ibcon#flushed, iclass 13, count 2 2006.257.15:01:35.74#ibcon#about to write, iclass 13, count 2 2006.257.15:01:35.74#ibcon#wrote, iclass 13, count 2 2006.257.15:01:35.74#ibcon#about to read 3, iclass 13, count 2 2006.257.15:01:35.76#ibcon#read 3, iclass 13, count 2 2006.257.15:01:35.76#ibcon#about to read 4, iclass 13, count 2 2006.257.15:01:35.76#ibcon#read 4, iclass 13, count 2 2006.257.15:01:35.76#ibcon#about to read 5, iclass 13, count 2 2006.257.15:01:35.76#ibcon#read 5, iclass 13, count 2 2006.257.15:01:35.76#ibcon#about to read 6, iclass 13, count 2 2006.257.15:01:35.76#ibcon#read 6, iclass 13, count 2 2006.257.15:01:35.76#ibcon#end of sib2, iclass 13, count 2 2006.257.15:01:35.76#ibcon#*mode == 0, iclass 13, count 2 2006.257.15:01:35.76#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.15:01:35.76#ibcon#[27=AT03-04\r\n] 2006.257.15:01:35.76#ibcon#*before write, iclass 13, count 2 2006.257.15:01:35.76#ibcon#enter sib2, iclass 13, count 2 2006.257.15:01:35.76#ibcon#flushed, iclass 13, count 2 2006.257.15:01:35.76#ibcon#about to write, iclass 13, count 2 2006.257.15:01:35.76#ibcon#wrote, iclass 13, count 2 2006.257.15:01:35.76#ibcon#about to read 3, iclass 13, count 2 2006.257.15:01:35.79#ibcon#read 3, iclass 13, count 2 2006.257.15:01:35.79#ibcon#about to read 4, iclass 13, count 2 2006.257.15:01:35.79#ibcon#read 4, iclass 13, count 2 2006.257.15:01:35.79#ibcon#about to read 5, iclass 13, count 2 2006.257.15:01:35.79#ibcon#read 5, iclass 13, count 2 2006.257.15:01:35.79#ibcon#about to read 6, iclass 13, count 2 2006.257.15:01:35.79#ibcon#read 6, iclass 13, count 2 2006.257.15:01:35.79#ibcon#end of sib2, iclass 13, count 2 2006.257.15:01:35.79#ibcon#*after write, iclass 13, count 2 2006.257.15:01:35.79#ibcon#*before return 0, iclass 13, count 2 2006.257.15:01:35.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:35.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:01:35.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.15:01:35.79#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:35.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:35.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:35.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:35.91#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:01:35.91#ibcon#first serial, iclass 13, count 0 2006.257.15:01:35.91#ibcon#enter sib2, iclass 13, count 0 2006.257.15:01:35.91#ibcon#flushed, iclass 13, count 0 2006.257.15:01:35.91#ibcon#about to write, iclass 13, count 0 2006.257.15:01:35.91#ibcon#wrote, iclass 13, count 0 2006.257.15:01:35.91#ibcon#about to read 3, iclass 13, count 0 2006.257.15:01:35.93#ibcon#read 3, iclass 13, count 0 2006.257.15:01:35.93#ibcon#about to read 4, iclass 13, count 0 2006.257.15:01:35.93#ibcon#read 4, iclass 13, count 0 2006.257.15:01:35.93#ibcon#about to read 5, iclass 13, count 0 2006.257.15:01:35.93#ibcon#read 5, iclass 13, count 0 2006.257.15:01:35.93#ibcon#about to read 6, iclass 13, count 0 2006.257.15:01:35.93#ibcon#read 6, iclass 13, count 0 2006.257.15:01:35.93#ibcon#end of sib2, iclass 13, count 0 2006.257.15:01:35.93#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:01:35.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:01:35.93#ibcon#[27=USB\r\n] 2006.257.15:01:35.93#ibcon#*before write, iclass 13, count 0 2006.257.15:01:35.93#ibcon#enter sib2, iclass 13, count 0 2006.257.15:01:35.93#ibcon#flushed, iclass 13, count 0 2006.257.15:01:35.93#ibcon#about to write, iclass 13, count 0 2006.257.15:01:35.93#ibcon#wrote, iclass 13, count 0 2006.257.15:01:35.93#ibcon#about to read 3, iclass 13, count 0 2006.257.15:01:35.96#ibcon#read 3, iclass 13, count 0 2006.257.15:01:35.96#ibcon#about to read 4, iclass 13, count 0 2006.257.15:01:35.96#ibcon#read 4, iclass 13, count 0 2006.257.15:01:35.96#ibcon#about to read 5, iclass 13, count 0 2006.257.15:01:35.96#ibcon#read 5, iclass 13, count 0 2006.257.15:01:35.96#ibcon#about to read 6, iclass 13, count 0 2006.257.15:01:35.96#ibcon#read 6, iclass 13, count 0 2006.257.15:01:35.96#ibcon#end of sib2, iclass 13, count 0 2006.257.15:01:35.96#ibcon#*after write, iclass 13, count 0 2006.257.15:01:35.96#ibcon#*before return 0, iclass 13, count 0 2006.257.15:01:35.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:35.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:01:35.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:01:35.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:01:35.96$vck44/vblo=4,679.99 2006.257.15:01:35.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.15:01:35.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.15:01:35.96#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:35.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:35.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:35.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:35.96#ibcon#enter wrdev, iclass 15, count 0 2006.257.15:01:35.96#ibcon#first serial, iclass 15, count 0 2006.257.15:01:35.96#ibcon#enter sib2, iclass 15, count 0 2006.257.15:01:35.96#ibcon#flushed, iclass 15, count 0 2006.257.15:01:35.96#ibcon#about to write, iclass 15, count 0 2006.257.15:01:35.96#ibcon#wrote, iclass 15, count 0 2006.257.15:01:35.96#ibcon#about to read 3, iclass 15, count 0 2006.257.15:01:35.98#ibcon#read 3, iclass 15, count 0 2006.257.15:01:35.98#ibcon#about to read 4, iclass 15, count 0 2006.257.15:01:35.98#ibcon#read 4, iclass 15, count 0 2006.257.15:01:35.98#ibcon#about to read 5, iclass 15, count 0 2006.257.15:01:35.98#ibcon#read 5, iclass 15, count 0 2006.257.15:01:35.98#ibcon#about to read 6, iclass 15, count 0 2006.257.15:01:35.98#ibcon#read 6, iclass 15, count 0 2006.257.15:01:35.98#ibcon#end of sib2, iclass 15, count 0 2006.257.15:01:35.98#ibcon#*mode == 0, iclass 15, count 0 2006.257.15:01:35.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.15:01:35.98#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:01:35.98#ibcon#*before write, iclass 15, count 0 2006.257.15:01:35.98#ibcon#enter sib2, iclass 15, count 0 2006.257.15:01:35.98#ibcon#flushed, iclass 15, count 0 2006.257.15:01:35.98#ibcon#about to write, iclass 15, count 0 2006.257.15:01:35.98#ibcon#wrote, iclass 15, count 0 2006.257.15:01:35.98#ibcon#about to read 3, iclass 15, count 0 2006.257.15:01:36.02#ibcon#read 3, iclass 15, count 0 2006.257.15:01:36.02#ibcon#about to read 4, iclass 15, count 0 2006.257.15:01:36.02#ibcon#read 4, iclass 15, count 0 2006.257.15:01:36.02#ibcon#about to read 5, iclass 15, count 0 2006.257.15:01:36.02#ibcon#read 5, iclass 15, count 0 2006.257.15:01:36.02#ibcon#about to read 6, iclass 15, count 0 2006.257.15:01:36.02#ibcon#read 6, iclass 15, count 0 2006.257.15:01:36.02#ibcon#end of sib2, iclass 15, count 0 2006.257.15:01:36.02#ibcon#*after write, iclass 15, count 0 2006.257.15:01:36.02#ibcon#*before return 0, iclass 15, count 0 2006.257.15:01:36.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:36.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:01:36.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.15:01:36.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.15:01:36.02$vck44/vb=4,5 2006.257.15:01:36.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.15:01:36.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.15:01:36.02#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:36.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:36.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:36.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:36.08#ibcon#enter wrdev, iclass 17, count 2 2006.257.15:01:36.08#ibcon#first serial, iclass 17, count 2 2006.257.15:01:36.08#ibcon#enter sib2, iclass 17, count 2 2006.257.15:01:36.08#ibcon#flushed, iclass 17, count 2 2006.257.15:01:36.08#ibcon#about to write, iclass 17, count 2 2006.257.15:01:36.08#ibcon#wrote, iclass 17, count 2 2006.257.15:01:36.08#ibcon#about to read 3, iclass 17, count 2 2006.257.15:01:36.10#ibcon#read 3, iclass 17, count 2 2006.257.15:01:36.10#ibcon#about to read 4, iclass 17, count 2 2006.257.15:01:36.10#ibcon#read 4, iclass 17, count 2 2006.257.15:01:36.10#ibcon#about to read 5, iclass 17, count 2 2006.257.15:01:36.10#ibcon#read 5, iclass 17, count 2 2006.257.15:01:36.10#ibcon#about to read 6, iclass 17, count 2 2006.257.15:01:36.10#ibcon#read 6, iclass 17, count 2 2006.257.15:01:36.10#ibcon#end of sib2, iclass 17, count 2 2006.257.15:01:36.10#ibcon#*mode == 0, iclass 17, count 2 2006.257.15:01:36.10#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.15:01:36.10#ibcon#[27=AT04-05\r\n] 2006.257.15:01:36.10#ibcon#*before write, iclass 17, count 2 2006.257.15:01:36.10#ibcon#enter sib2, iclass 17, count 2 2006.257.15:01:36.10#ibcon#flushed, iclass 17, count 2 2006.257.15:01:36.10#ibcon#about to write, iclass 17, count 2 2006.257.15:01:36.10#ibcon#wrote, iclass 17, count 2 2006.257.15:01:36.10#ibcon#about to read 3, iclass 17, count 2 2006.257.15:01:36.13#ibcon#read 3, iclass 17, count 2 2006.257.15:01:36.13#ibcon#about to read 4, iclass 17, count 2 2006.257.15:01:36.13#ibcon#read 4, iclass 17, count 2 2006.257.15:01:36.13#ibcon#about to read 5, iclass 17, count 2 2006.257.15:01:36.13#ibcon#read 5, iclass 17, count 2 2006.257.15:01:36.13#ibcon#about to read 6, iclass 17, count 2 2006.257.15:01:36.13#ibcon#read 6, iclass 17, count 2 2006.257.15:01:36.13#ibcon#end of sib2, iclass 17, count 2 2006.257.15:01:36.13#ibcon#*after write, iclass 17, count 2 2006.257.15:01:36.13#ibcon#*before return 0, iclass 17, count 2 2006.257.15:01:36.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:36.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:01:36.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.15:01:36.13#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:36.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:36.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:36.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:36.25#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:01:36.25#ibcon#first serial, iclass 17, count 0 2006.257.15:01:36.25#ibcon#enter sib2, iclass 17, count 0 2006.257.15:01:36.25#ibcon#flushed, iclass 17, count 0 2006.257.15:01:36.25#ibcon#about to write, iclass 17, count 0 2006.257.15:01:36.25#ibcon#wrote, iclass 17, count 0 2006.257.15:01:36.25#ibcon#about to read 3, iclass 17, count 0 2006.257.15:01:36.27#ibcon#read 3, iclass 17, count 0 2006.257.15:01:36.27#ibcon#about to read 4, iclass 17, count 0 2006.257.15:01:36.27#ibcon#read 4, iclass 17, count 0 2006.257.15:01:36.27#ibcon#about to read 5, iclass 17, count 0 2006.257.15:01:36.27#ibcon#read 5, iclass 17, count 0 2006.257.15:01:36.27#ibcon#about to read 6, iclass 17, count 0 2006.257.15:01:36.27#ibcon#read 6, iclass 17, count 0 2006.257.15:01:36.27#ibcon#end of sib2, iclass 17, count 0 2006.257.15:01:36.27#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:01:36.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:01:36.27#ibcon#[27=USB\r\n] 2006.257.15:01:36.27#ibcon#*before write, iclass 17, count 0 2006.257.15:01:36.27#ibcon#enter sib2, iclass 17, count 0 2006.257.15:01:36.27#ibcon#flushed, iclass 17, count 0 2006.257.15:01:36.27#ibcon#about to write, iclass 17, count 0 2006.257.15:01:36.27#ibcon#wrote, iclass 17, count 0 2006.257.15:01:36.27#ibcon#about to read 3, iclass 17, count 0 2006.257.15:01:36.30#ibcon#read 3, iclass 17, count 0 2006.257.15:01:36.30#ibcon#about to read 4, iclass 17, count 0 2006.257.15:01:36.30#ibcon#read 4, iclass 17, count 0 2006.257.15:01:36.30#ibcon#about to read 5, iclass 17, count 0 2006.257.15:01:36.30#ibcon#read 5, iclass 17, count 0 2006.257.15:01:36.30#ibcon#about to read 6, iclass 17, count 0 2006.257.15:01:36.30#ibcon#read 6, iclass 17, count 0 2006.257.15:01:36.30#ibcon#end of sib2, iclass 17, count 0 2006.257.15:01:36.30#ibcon#*after write, iclass 17, count 0 2006.257.15:01:36.30#ibcon#*before return 0, iclass 17, count 0 2006.257.15:01:36.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:36.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:01:36.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:01:36.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:01:36.30$vck44/vblo=5,709.99 2006.257.15:01:36.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.15:01:36.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.15:01:36.30#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:36.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:36.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:36.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:36.30#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:01:36.30#ibcon#first serial, iclass 19, count 0 2006.257.15:01:36.30#ibcon#enter sib2, iclass 19, count 0 2006.257.15:01:36.30#ibcon#flushed, iclass 19, count 0 2006.257.15:01:36.30#ibcon#about to write, iclass 19, count 0 2006.257.15:01:36.30#ibcon#wrote, iclass 19, count 0 2006.257.15:01:36.30#ibcon#about to read 3, iclass 19, count 0 2006.257.15:01:36.32#ibcon#read 3, iclass 19, count 0 2006.257.15:01:36.32#ibcon#about to read 4, iclass 19, count 0 2006.257.15:01:36.32#ibcon#read 4, iclass 19, count 0 2006.257.15:01:36.32#ibcon#about to read 5, iclass 19, count 0 2006.257.15:01:36.32#ibcon#read 5, iclass 19, count 0 2006.257.15:01:36.32#ibcon#about to read 6, iclass 19, count 0 2006.257.15:01:36.32#ibcon#read 6, iclass 19, count 0 2006.257.15:01:36.32#ibcon#end of sib2, iclass 19, count 0 2006.257.15:01:36.32#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:01:36.32#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:01:36.32#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:01:36.32#ibcon#*before write, iclass 19, count 0 2006.257.15:01:36.32#ibcon#enter sib2, iclass 19, count 0 2006.257.15:01:36.32#ibcon#flushed, iclass 19, count 0 2006.257.15:01:36.32#ibcon#about to write, iclass 19, count 0 2006.257.15:01:36.32#ibcon#wrote, iclass 19, count 0 2006.257.15:01:36.32#ibcon#about to read 3, iclass 19, count 0 2006.257.15:01:36.36#ibcon#read 3, iclass 19, count 0 2006.257.15:01:36.36#ibcon#about to read 4, iclass 19, count 0 2006.257.15:01:36.36#ibcon#read 4, iclass 19, count 0 2006.257.15:01:36.36#ibcon#about to read 5, iclass 19, count 0 2006.257.15:01:36.36#ibcon#read 5, iclass 19, count 0 2006.257.15:01:36.36#ibcon#about to read 6, iclass 19, count 0 2006.257.15:01:36.36#ibcon#read 6, iclass 19, count 0 2006.257.15:01:36.36#ibcon#end of sib2, iclass 19, count 0 2006.257.15:01:36.36#ibcon#*after write, iclass 19, count 0 2006.257.15:01:36.36#ibcon#*before return 0, iclass 19, count 0 2006.257.15:01:36.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:36.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:01:36.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:01:36.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:01:36.36$vck44/vb=5,4 2006.257.15:01:36.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.15:01:36.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.15:01:36.36#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:36.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:36.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:36.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:36.42#ibcon#enter wrdev, iclass 21, count 2 2006.257.15:01:36.42#ibcon#first serial, iclass 21, count 2 2006.257.15:01:36.42#ibcon#enter sib2, iclass 21, count 2 2006.257.15:01:36.42#ibcon#flushed, iclass 21, count 2 2006.257.15:01:36.42#ibcon#about to write, iclass 21, count 2 2006.257.15:01:36.42#ibcon#wrote, iclass 21, count 2 2006.257.15:01:36.42#ibcon#about to read 3, iclass 21, count 2 2006.257.15:01:36.44#ibcon#read 3, iclass 21, count 2 2006.257.15:01:36.44#ibcon#about to read 4, iclass 21, count 2 2006.257.15:01:36.44#ibcon#read 4, iclass 21, count 2 2006.257.15:01:36.44#ibcon#about to read 5, iclass 21, count 2 2006.257.15:01:36.44#ibcon#read 5, iclass 21, count 2 2006.257.15:01:36.44#ibcon#about to read 6, iclass 21, count 2 2006.257.15:01:36.44#ibcon#read 6, iclass 21, count 2 2006.257.15:01:36.44#ibcon#end of sib2, iclass 21, count 2 2006.257.15:01:36.44#ibcon#*mode == 0, iclass 21, count 2 2006.257.15:01:36.44#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.15:01:36.44#ibcon#[27=AT05-04\r\n] 2006.257.15:01:36.44#ibcon#*before write, iclass 21, count 2 2006.257.15:01:36.44#ibcon#enter sib2, iclass 21, count 2 2006.257.15:01:36.44#ibcon#flushed, iclass 21, count 2 2006.257.15:01:36.44#ibcon#about to write, iclass 21, count 2 2006.257.15:01:36.44#ibcon#wrote, iclass 21, count 2 2006.257.15:01:36.44#ibcon#about to read 3, iclass 21, count 2 2006.257.15:01:36.47#ibcon#read 3, iclass 21, count 2 2006.257.15:01:36.47#ibcon#about to read 4, iclass 21, count 2 2006.257.15:01:36.47#ibcon#read 4, iclass 21, count 2 2006.257.15:01:36.47#ibcon#about to read 5, iclass 21, count 2 2006.257.15:01:36.47#ibcon#read 5, iclass 21, count 2 2006.257.15:01:36.47#ibcon#about to read 6, iclass 21, count 2 2006.257.15:01:36.47#ibcon#read 6, iclass 21, count 2 2006.257.15:01:36.47#ibcon#end of sib2, iclass 21, count 2 2006.257.15:01:36.47#ibcon#*after write, iclass 21, count 2 2006.257.15:01:36.47#ibcon#*before return 0, iclass 21, count 2 2006.257.15:01:36.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:36.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:01:36.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.15:01:36.47#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:36.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:36.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:36.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:36.59#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:01:36.59#ibcon#first serial, iclass 21, count 0 2006.257.15:01:36.59#ibcon#enter sib2, iclass 21, count 0 2006.257.15:01:36.59#ibcon#flushed, iclass 21, count 0 2006.257.15:01:36.59#ibcon#about to write, iclass 21, count 0 2006.257.15:01:36.59#ibcon#wrote, iclass 21, count 0 2006.257.15:01:36.59#ibcon#about to read 3, iclass 21, count 0 2006.257.15:01:36.61#ibcon#read 3, iclass 21, count 0 2006.257.15:01:36.61#ibcon#about to read 4, iclass 21, count 0 2006.257.15:01:36.61#ibcon#read 4, iclass 21, count 0 2006.257.15:01:36.61#ibcon#about to read 5, iclass 21, count 0 2006.257.15:01:36.61#ibcon#read 5, iclass 21, count 0 2006.257.15:01:36.61#ibcon#about to read 6, iclass 21, count 0 2006.257.15:01:36.61#ibcon#read 6, iclass 21, count 0 2006.257.15:01:36.61#ibcon#end of sib2, iclass 21, count 0 2006.257.15:01:36.61#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:01:36.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:01:36.61#ibcon#[27=USB\r\n] 2006.257.15:01:36.61#ibcon#*before write, iclass 21, count 0 2006.257.15:01:36.61#ibcon#enter sib2, iclass 21, count 0 2006.257.15:01:36.61#ibcon#flushed, iclass 21, count 0 2006.257.15:01:36.61#ibcon#about to write, iclass 21, count 0 2006.257.15:01:36.61#ibcon#wrote, iclass 21, count 0 2006.257.15:01:36.61#ibcon#about to read 3, iclass 21, count 0 2006.257.15:01:36.64#ibcon#read 3, iclass 21, count 0 2006.257.15:01:36.64#ibcon#about to read 4, iclass 21, count 0 2006.257.15:01:36.64#ibcon#read 4, iclass 21, count 0 2006.257.15:01:36.64#ibcon#about to read 5, iclass 21, count 0 2006.257.15:01:36.64#ibcon#read 5, iclass 21, count 0 2006.257.15:01:36.64#ibcon#about to read 6, iclass 21, count 0 2006.257.15:01:36.64#ibcon#read 6, iclass 21, count 0 2006.257.15:01:36.64#ibcon#end of sib2, iclass 21, count 0 2006.257.15:01:36.64#ibcon#*after write, iclass 21, count 0 2006.257.15:01:36.64#ibcon#*before return 0, iclass 21, count 0 2006.257.15:01:36.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:36.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:01:36.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:01:36.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:01:36.64$vck44/vblo=6,719.99 2006.257.15:01:36.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.15:01:36.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.15:01:36.64#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:36.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:36.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:36.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:36.64#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:01:36.64#ibcon#first serial, iclass 23, count 0 2006.257.15:01:36.64#ibcon#enter sib2, iclass 23, count 0 2006.257.15:01:36.64#ibcon#flushed, iclass 23, count 0 2006.257.15:01:36.64#ibcon#about to write, iclass 23, count 0 2006.257.15:01:36.64#ibcon#wrote, iclass 23, count 0 2006.257.15:01:36.64#ibcon#about to read 3, iclass 23, count 0 2006.257.15:01:36.66#ibcon#read 3, iclass 23, count 0 2006.257.15:01:36.66#ibcon#about to read 4, iclass 23, count 0 2006.257.15:01:36.66#ibcon#read 4, iclass 23, count 0 2006.257.15:01:36.66#ibcon#about to read 5, iclass 23, count 0 2006.257.15:01:36.66#ibcon#read 5, iclass 23, count 0 2006.257.15:01:36.66#ibcon#about to read 6, iclass 23, count 0 2006.257.15:01:36.66#ibcon#read 6, iclass 23, count 0 2006.257.15:01:36.66#ibcon#end of sib2, iclass 23, count 0 2006.257.15:01:36.66#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:01:36.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:01:36.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:01:36.66#ibcon#*before write, iclass 23, count 0 2006.257.15:01:36.66#ibcon#enter sib2, iclass 23, count 0 2006.257.15:01:36.66#ibcon#flushed, iclass 23, count 0 2006.257.15:01:36.66#ibcon#about to write, iclass 23, count 0 2006.257.15:01:36.66#ibcon#wrote, iclass 23, count 0 2006.257.15:01:36.66#ibcon#about to read 3, iclass 23, count 0 2006.257.15:01:36.70#ibcon#read 3, iclass 23, count 0 2006.257.15:01:36.70#ibcon#about to read 4, iclass 23, count 0 2006.257.15:01:36.70#ibcon#read 4, iclass 23, count 0 2006.257.15:01:36.70#ibcon#about to read 5, iclass 23, count 0 2006.257.15:01:36.70#ibcon#read 5, iclass 23, count 0 2006.257.15:01:36.70#ibcon#about to read 6, iclass 23, count 0 2006.257.15:01:36.70#ibcon#read 6, iclass 23, count 0 2006.257.15:01:36.70#ibcon#end of sib2, iclass 23, count 0 2006.257.15:01:36.70#ibcon#*after write, iclass 23, count 0 2006.257.15:01:36.70#ibcon#*before return 0, iclass 23, count 0 2006.257.15:01:36.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:36.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:01:36.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:01:36.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:01:36.70$vck44/vb=6,4 2006.257.15:01:36.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.15:01:36.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.15:01:36.70#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:36.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:36.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:36.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:36.76#ibcon#enter wrdev, iclass 25, count 2 2006.257.15:01:36.76#ibcon#first serial, iclass 25, count 2 2006.257.15:01:36.76#ibcon#enter sib2, iclass 25, count 2 2006.257.15:01:36.76#ibcon#flushed, iclass 25, count 2 2006.257.15:01:36.76#ibcon#about to write, iclass 25, count 2 2006.257.15:01:36.76#ibcon#wrote, iclass 25, count 2 2006.257.15:01:36.76#ibcon#about to read 3, iclass 25, count 2 2006.257.15:01:36.78#ibcon#read 3, iclass 25, count 2 2006.257.15:01:36.78#ibcon#about to read 4, iclass 25, count 2 2006.257.15:01:36.78#ibcon#read 4, iclass 25, count 2 2006.257.15:01:36.78#ibcon#about to read 5, iclass 25, count 2 2006.257.15:01:36.78#ibcon#read 5, iclass 25, count 2 2006.257.15:01:36.78#ibcon#about to read 6, iclass 25, count 2 2006.257.15:01:36.78#ibcon#read 6, iclass 25, count 2 2006.257.15:01:36.78#ibcon#end of sib2, iclass 25, count 2 2006.257.15:01:36.78#ibcon#*mode == 0, iclass 25, count 2 2006.257.15:01:36.78#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.15:01:36.78#ibcon#[27=AT06-04\r\n] 2006.257.15:01:36.78#ibcon#*before write, iclass 25, count 2 2006.257.15:01:36.78#ibcon#enter sib2, iclass 25, count 2 2006.257.15:01:36.78#ibcon#flushed, iclass 25, count 2 2006.257.15:01:36.78#ibcon#about to write, iclass 25, count 2 2006.257.15:01:36.78#ibcon#wrote, iclass 25, count 2 2006.257.15:01:36.78#ibcon#about to read 3, iclass 25, count 2 2006.257.15:01:36.81#ibcon#read 3, iclass 25, count 2 2006.257.15:01:36.81#ibcon#about to read 4, iclass 25, count 2 2006.257.15:01:36.81#ibcon#read 4, iclass 25, count 2 2006.257.15:01:36.81#ibcon#about to read 5, iclass 25, count 2 2006.257.15:01:36.81#ibcon#read 5, iclass 25, count 2 2006.257.15:01:36.81#ibcon#about to read 6, iclass 25, count 2 2006.257.15:01:36.81#ibcon#read 6, iclass 25, count 2 2006.257.15:01:36.81#ibcon#end of sib2, iclass 25, count 2 2006.257.15:01:36.81#ibcon#*after write, iclass 25, count 2 2006.257.15:01:36.81#ibcon#*before return 0, iclass 25, count 2 2006.257.15:01:36.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:36.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:01:36.81#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.15:01:36.81#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:36.81#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:36.93#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:36.93#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:36.93#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:01:36.93#ibcon#first serial, iclass 25, count 0 2006.257.15:01:36.93#ibcon#enter sib2, iclass 25, count 0 2006.257.15:01:36.93#ibcon#flushed, iclass 25, count 0 2006.257.15:01:36.93#ibcon#about to write, iclass 25, count 0 2006.257.15:01:36.93#ibcon#wrote, iclass 25, count 0 2006.257.15:01:36.93#ibcon#about to read 3, iclass 25, count 0 2006.257.15:01:36.95#ibcon#read 3, iclass 25, count 0 2006.257.15:01:36.95#ibcon#about to read 4, iclass 25, count 0 2006.257.15:01:36.95#ibcon#read 4, iclass 25, count 0 2006.257.15:01:36.95#ibcon#about to read 5, iclass 25, count 0 2006.257.15:01:36.95#ibcon#read 5, iclass 25, count 0 2006.257.15:01:36.95#ibcon#about to read 6, iclass 25, count 0 2006.257.15:01:36.95#ibcon#read 6, iclass 25, count 0 2006.257.15:01:36.95#ibcon#end of sib2, iclass 25, count 0 2006.257.15:01:36.95#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:01:36.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:01:36.95#ibcon#[27=USB\r\n] 2006.257.15:01:36.95#ibcon#*before write, iclass 25, count 0 2006.257.15:01:36.95#ibcon#enter sib2, iclass 25, count 0 2006.257.15:01:36.95#ibcon#flushed, iclass 25, count 0 2006.257.15:01:36.95#ibcon#about to write, iclass 25, count 0 2006.257.15:01:36.95#ibcon#wrote, iclass 25, count 0 2006.257.15:01:36.95#ibcon#about to read 3, iclass 25, count 0 2006.257.15:01:36.98#ibcon#read 3, iclass 25, count 0 2006.257.15:01:36.98#ibcon#about to read 4, iclass 25, count 0 2006.257.15:01:36.98#ibcon#read 4, iclass 25, count 0 2006.257.15:01:36.98#ibcon#about to read 5, iclass 25, count 0 2006.257.15:01:36.98#ibcon#read 5, iclass 25, count 0 2006.257.15:01:36.98#ibcon#about to read 6, iclass 25, count 0 2006.257.15:01:36.98#ibcon#read 6, iclass 25, count 0 2006.257.15:01:36.98#ibcon#end of sib2, iclass 25, count 0 2006.257.15:01:36.98#ibcon#*after write, iclass 25, count 0 2006.257.15:01:36.98#ibcon#*before return 0, iclass 25, count 0 2006.257.15:01:36.98#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:36.98#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:01:36.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:01:36.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:01:36.98$vck44/vblo=7,734.99 2006.257.15:01:36.98#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.15:01:36.98#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.15:01:36.98#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:36.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:36.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:36.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:36.98#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:01:36.98#ibcon#first serial, iclass 27, count 0 2006.257.15:01:36.98#ibcon#enter sib2, iclass 27, count 0 2006.257.15:01:36.98#ibcon#flushed, iclass 27, count 0 2006.257.15:01:36.98#ibcon#about to write, iclass 27, count 0 2006.257.15:01:36.98#ibcon#wrote, iclass 27, count 0 2006.257.15:01:36.98#ibcon#about to read 3, iclass 27, count 0 2006.257.15:01:37.00#ibcon#read 3, iclass 27, count 0 2006.257.15:01:37.00#ibcon#about to read 4, iclass 27, count 0 2006.257.15:01:37.00#ibcon#read 4, iclass 27, count 0 2006.257.15:01:37.00#ibcon#about to read 5, iclass 27, count 0 2006.257.15:01:37.00#ibcon#read 5, iclass 27, count 0 2006.257.15:01:37.00#ibcon#about to read 6, iclass 27, count 0 2006.257.15:01:37.00#ibcon#read 6, iclass 27, count 0 2006.257.15:01:37.00#ibcon#end of sib2, iclass 27, count 0 2006.257.15:01:37.00#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:01:37.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:01:37.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:01:37.00#ibcon#*before write, iclass 27, count 0 2006.257.15:01:37.00#ibcon#enter sib2, iclass 27, count 0 2006.257.15:01:37.00#ibcon#flushed, iclass 27, count 0 2006.257.15:01:37.00#ibcon#about to write, iclass 27, count 0 2006.257.15:01:37.00#ibcon#wrote, iclass 27, count 0 2006.257.15:01:37.00#ibcon#about to read 3, iclass 27, count 0 2006.257.15:01:37.04#ibcon#read 3, iclass 27, count 0 2006.257.15:01:37.04#ibcon#about to read 4, iclass 27, count 0 2006.257.15:01:37.04#ibcon#read 4, iclass 27, count 0 2006.257.15:01:37.04#ibcon#about to read 5, iclass 27, count 0 2006.257.15:01:37.04#ibcon#read 5, iclass 27, count 0 2006.257.15:01:37.04#ibcon#about to read 6, iclass 27, count 0 2006.257.15:01:37.04#ibcon#read 6, iclass 27, count 0 2006.257.15:01:37.04#ibcon#end of sib2, iclass 27, count 0 2006.257.15:01:37.04#ibcon#*after write, iclass 27, count 0 2006.257.15:01:37.04#ibcon#*before return 0, iclass 27, count 0 2006.257.15:01:37.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:37.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:01:37.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:01:37.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:01:37.04$vck44/vb=7,4 2006.257.15:01:37.04#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.15:01:37.04#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.15:01:37.04#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:37.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:37.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:37.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:37.10#ibcon#enter wrdev, iclass 29, count 2 2006.257.15:01:37.10#ibcon#first serial, iclass 29, count 2 2006.257.15:01:37.10#ibcon#enter sib2, iclass 29, count 2 2006.257.15:01:37.10#ibcon#flushed, iclass 29, count 2 2006.257.15:01:37.10#ibcon#about to write, iclass 29, count 2 2006.257.15:01:37.10#ibcon#wrote, iclass 29, count 2 2006.257.15:01:37.10#ibcon#about to read 3, iclass 29, count 2 2006.257.15:01:37.12#ibcon#read 3, iclass 29, count 2 2006.257.15:01:37.12#ibcon#about to read 4, iclass 29, count 2 2006.257.15:01:37.12#ibcon#read 4, iclass 29, count 2 2006.257.15:01:37.12#ibcon#about to read 5, iclass 29, count 2 2006.257.15:01:37.12#ibcon#read 5, iclass 29, count 2 2006.257.15:01:37.12#ibcon#about to read 6, iclass 29, count 2 2006.257.15:01:37.12#ibcon#read 6, iclass 29, count 2 2006.257.15:01:37.12#ibcon#end of sib2, iclass 29, count 2 2006.257.15:01:37.12#ibcon#*mode == 0, iclass 29, count 2 2006.257.15:01:37.12#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.15:01:37.12#ibcon#[27=AT07-04\r\n] 2006.257.15:01:37.12#ibcon#*before write, iclass 29, count 2 2006.257.15:01:37.12#ibcon#enter sib2, iclass 29, count 2 2006.257.15:01:37.12#ibcon#flushed, iclass 29, count 2 2006.257.15:01:37.12#ibcon#about to write, iclass 29, count 2 2006.257.15:01:37.12#ibcon#wrote, iclass 29, count 2 2006.257.15:01:37.12#ibcon#about to read 3, iclass 29, count 2 2006.257.15:01:37.15#ibcon#read 3, iclass 29, count 2 2006.257.15:01:37.15#ibcon#about to read 4, iclass 29, count 2 2006.257.15:01:37.15#ibcon#read 4, iclass 29, count 2 2006.257.15:01:37.15#ibcon#about to read 5, iclass 29, count 2 2006.257.15:01:37.15#ibcon#read 5, iclass 29, count 2 2006.257.15:01:37.15#ibcon#about to read 6, iclass 29, count 2 2006.257.15:01:37.15#ibcon#read 6, iclass 29, count 2 2006.257.15:01:37.15#ibcon#end of sib2, iclass 29, count 2 2006.257.15:01:37.15#ibcon#*after write, iclass 29, count 2 2006.257.15:01:37.15#ibcon#*before return 0, iclass 29, count 2 2006.257.15:01:37.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:37.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:01:37.15#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.15:01:37.15#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:37.15#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:37.27#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:37.27#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:37.27#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:01:37.27#ibcon#first serial, iclass 29, count 0 2006.257.15:01:37.27#ibcon#enter sib2, iclass 29, count 0 2006.257.15:01:37.27#ibcon#flushed, iclass 29, count 0 2006.257.15:01:37.27#ibcon#about to write, iclass 29, count 0 2006.257.15:01:37.27#ibcon#wrote, iclass 29, count 0 2006.257.15:01:37.27#ibcon#about to read 3, iclass 29, count 0 2006.257.15:01:37.29#ibcon#read 3, iclass 29, count 0 2006.257.15:01:37.29#ibcon#about to read 4, iclass 29, count 0 2006.257.15:01:37.29#ibcon#read 4, iclass 29, count 0 2006.257.15:01:37.29#ibcon#about to read 5, iclass 29, count 0 2006.257.15:01:37.29#ibcon#read 5, iclass 29, count 0 2006.257.15:01:37.29#ibcon#about to read 6, iclass 29, count 0 2006.257.15:01:37.29#ibcon#read 6, iclass 29, count 0 2006.257.15:01:37.29#ibcon#end of sib2, iclass 29, count 0 2006.257.15:01:37.29#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:01:37.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:01:37.29#ibcon#[27=USB\r\n] 2006.257.15:01:37.29#ibcon#*before write, iclass 29, count 0 2006.257.15:01:37.29#ibcon#enter sib2, iclass 29, count 0 2006.257.15:01:37.29#ibcon#flushed, iclass 29, count 0 2006.257.15:01:37.29#ibcon#about to write, iclass 29, count 0 2006.257.15:01:37.29#ibcon#wrote, iclass 29, count 0 2006.257.15:01:37.29#ibcon#about to read 3, iclass 29, count 0 2006.257.15:01:37.32#ibcon#read 3, iclass 29, count 0 2006.257.15:01:37.32#ibcon#about to read 4, iclass 29, count 0 2006.257.15:01:37.32#ibcon#read 4, iclass 29, count 0 2006.257.15:01:37.32#ibcon#about to read 5, iclass 29, count 0 2006.257.15:01:37.32#ibcon#read 5, iclass 29, count 0 2006.257.15:01:37.32#ibcon#about to read 6, iclass 29, count 0 2006.257.15:01:37.32#ibcon#read 6, iclass 29, count 0 2006.257.15:01:37.32#ibcon#end of sib2, iclass 29, count 0 2006.257.15:01:37.32#ibcon#*after write, iclass 29, count 0 2006.257.15:01:37.32#ibcon#*before return 0, iclass 29, count 0 2006.257.15:01:37.32#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:37.32#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:01:37.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:01:37.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:01:37.32$vck44/vblo=8,744.99 2006.257.15:01:37.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.15:01:37.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.15:01:37.32#ibcon#ireg 17 cls_cnt 0 2006.257.15:01:37.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:37.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:37.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:37.32#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:01:37.32#ibcon#first serial, iclass 31, count 0 2006.257.15:01:37.32#ibcon#enter sib2, iclass 31, count 0 2006.257.15:01:37.32#ibcon#flushed, iclass 31, count 0 2006.257.15:01:37.32#ibcon#about to write, iclass 31, count 0 2006.257.15:01:37.32#ibcon#wrote, iclass 31, count 0 2006.257.15:01:37.32#ibcon#about to read 3, iclass 31, count 0 2006.257.15:01:37.34#ibcon#read 3, iclass 31, count 0 2006.257.15:01:37.34#ibcon#about to read 4, iclass 31, count 0 2006.257.15:01:37.34#ibcon#read 4, iclass 31, count 0 2006.257.15:01:37.34#ibcon#about to read 5, iclass 31, count 0 2006.257.15:01:37.34#ibcon#read 5, iclass 31, count 0 2006.257.15:01:37.34#ibcon#about to read 6, iclass 31, count 0 2006.257.15:01:37.34#ibcon#read 6, iclass 31, count 0 2006.257.15:01:37.34#ibcon#end of sib2, iclass 31, count 0 2006.257.15:01:37.34#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:01:37.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:01:37.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:01:37.34#ibcon#*before write, iclass 31, count 0 2006.257.15:01:37.34#ibcon#enter sib2, iclass 31, count 0 2006.257.15:01:37.34#ibcon#flushed, iclass 31, count 0 2006.257.15:01:37.34#ibcon#about to write, iclass 31, count 0 2006.257.15:01:37.34#ibcon#wrote, iclass 31, count 0 2006.257.15:01:37.34#ibcon#about to read 3, iclass 31, count 0 2006.257.15:01:37.38#ibcon#read 3, iclass 31, count 0 2006.257.15:01:37.38#ibcon#about to read 4, iclass 31, count 0 2006.257.15:01:37.38#ibcon#read 4, iclass 31, count 0 2006.257.15:01:37.38#ibcon#about to read 5, iclass 31, count 0 2006.257.15:01:37.38#ibcon#read 5, iclass 31, count 0 2006.257.15:01:37.38#ibcon#about to read 6, iclass 31, count 0 2006.257.15:01:37.38#ibcon#read 6, iclass 31, count 0 2006.257.15:01:37.38#ibcon#end of sib2, iclass 31, count 0 2006.257.15:01:37.38#ibcon#*after write, iclass 31, count 0 2006.257.15:01:37.38#ibcon#*before return 0, iclass 31, count 0 2006.257.15:01:37.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:37.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:01:37.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:01:37.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:01:37.38$vck44/vb=8,4 2006.257.15:01:37.38#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.15:01:37.38#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.15:01:37.38#ibcon#ireg 11 cls_cnt 2 2006.257.15:01:37.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:37.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:37.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:37.44#ibcon#enter wrdev, iclass 33, count 2 2006.257.15:01:37.44#ibcon#first serial, iclass 33, count 2 2006.257.15:01:37.44#ibcon#enter sib2, iclass 33, count 2 2006.257.15:01:37.44#ibcon#flushed, iclass 33, count 2 2006.257.15:01:37.44#ibcon#about to write, iclass 33, count 2 2006.257.15:01:37.44#ibcon#wrote, iclass 33, count 2 2006.257.15:01:37.44#ibcon#about to read 3, iclass 33, count 2 2006.257.15:01:37.46#ibcon#read 3, iclass 33, count 2 2006.257.15:01:37.46#ibcon#about to read 4, iclass 33, count 2 2006.257.15:01:37.46#ibcon#read 4, iclass 33, count 2 2006.257.15:01:37.46#ibcon#about to read 5, iclass 33, count 2 2006.257.15:01:37.46#ibcon#read 5, iclass 33, count 2 2006.257.15:01:37.46#ibcon#about to read 6, iclass 33, count 2 2006.257.15:01:37.46#ibcon#read 6, iclass 33, count 2 2006.257.15:01:37.46#ibcon#end of sib2, iclass 33, count 2 2006.257.15:01:37.46#ibcon#*mode == 0, iclass 33, count 2 2006.257.15:01:37.46#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.15:01:37.46#ibcon#[27=AT08-04\r\n] 2006.257.15:01:37.46#ibcon#*before write, iclass 33, count 2 2006.257.15:01:37.46#ibcon#enter sib2, iclass 33, count 2 2006.257.15:01:37.46#ibcon#flushed, iclass 33, count 2 2006.257.15:01:37.46#ibcon#about to write, iclass 33, count 2 2006.257.15:01:37.46#ibcon#wrote, iclass 33, count 2 2006.257.15:01:37.46#ibcon#about to read 3, iclass 33, count 2 2006.257.15:01:37.49#ibcon#read 3, iclass 33, count 2 2006.257.15:01:37.49#ibcon#about to read 4, iclass 33, count 2 2006.257.15:01:37.49#ibcon#read 4, iclass 33, count 2 2006.257.15:01:37.49#ibcon#about to read 5, iclass 33, count 2 2006.257.15:01:37.49#ibcon#read 5, iclass 33, count 2 2006.257.15:01:37.49#ibcon#about to read 6, iclass 33, count 2 2006.257.15:01:37.49#ibcon#read 6, iclass 33, count 2 2006.257.15:01:37.49#ibcon#end of sib2, iclass 33, count 2 2006.257.15:01:37.49#ibcon#*after write, iclass 33, count 2 2006.257.15:01:37.49#ibcon#*before return 0, iclass 33, count 2 2006.257.15:01:37.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:37.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:01:37.49#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.15:01:37.49#ibcon#ireg 7 cls_cnt 0 2006.257.15:01:37.49#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:37.61#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:37.61#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:37.61#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:01:37.61#ibcon#first serial, iclass 33, count 0 2006.257.15:01:37.61#ibcon#enter sib2, iclass 33, count 0 2006.257.15:01:37.61#ibcon#flushed, iclass 33, count 0 2006.257.15:01:37.61#ibcon#about to write, iclass 33, count 0 2006.257.15:01:37.61#ibcon#wrote, iclass 33, count 0 2006.257.15:01:37.61#ibcon#about to read 3, iclass 33, count 0 2006.257.15:01:37.63#ibcon#read 3, iclass 33, count 0 2006.257.15:01:37.63#ibcon#about to read 4, iclass 33, count 0 2006.257.15:01:37.63#ibcon#read 4, iclass 33, count 0 2006.257.15:01:37.63#ibcon#about to read 5, iclass 33, count 0 2006.257.15:01:37.63#ibcon#read 5, iclass 33, count 0 2006.257.15:01:37.63#ibcon#about to read 6, iclass 33, count 0 2006.257.15:01:37.63#ibcon#read 6, iclass 33, count 0 2006.257.15:01:37.63#ibcon#end of sib2, iclass 33, count 0 2006.257.15:01:37.63#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:01:37.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:01:37.63#ibcon#[27=USB\r\n] 2006.257.15:01:37.63#ibcon#*before write, iclass 33, count 0 2006.257.15:01:37.63#ibcon#enter sib2, iclass 33, count 0 2006.257.15:01:37.63#ibcon#flushed, iclass 33, count 0 2006.257.15:01:37.63#ibcon#about to write, iclass 33, count 0 2006.257.15:01:37.63#ibcon#wrote, iclass 33, count 0 2006.257.15:01:37.63#ibcon#about to read 3, iclass 33, count 0 2006.257.15:01:37.66#ibcon#read 3, iclass 33, count 0 2006.257.15:01:37.66#ibcon#about to read 4, iclass 33, count 0 2006.257.15:01:37.66#ibcon#read 4, iclass 33, count 0 2006.257.15:01:37.66#ibcon#about to read 5, iclass 33, count 0 2006.257.15:01:37.66#ibcon#read 5, iclass 33, count 0 2006.257.15:01:37.66#ibcon#about to read 6, iclass 33, count 0 2006.257.15:01:37.66#ibcon#read 6, iclass 33, count 0 2006.257.15:01:37.66#ibcon#end of sib2, iclass 33, count 0 2006.257.15:01:37.66#ibcon#*after write, iclass 33, count 0 2006.257.15:01:37.66#ibcon#*before return 0, iclass 33, count 0 2006.257.15:01:37.66#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:37.66#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:01:37.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:01:37.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:01:37.66$vck44/vabw=wide 2006.257.15:01:37.66#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.15:01:37.66#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.15:01:37.66#ibcon#ireg 8 cls_cnt 0 2006.257.15:01:37.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:37.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:37.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:37.66#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:01:37.66#ibcon#first serial, iclass 35, count 0 2006.257.15:01:37.66#ibcon#enter sib2, iclass 35, count 0 2006.257.15:01:37.66#ibcon#flushed, iclass 35, count 0 2006.257.15:01:37.66#ibcon#about to write, iclass 35, count 0 2006.257.15:01:37.66#ibcon#wrote, iclass 35, count 0 2006.257.15:01:37.66#ibcon#about to read 3, iclass 35, count 0 2006.257.15:01:39.15#ibcon#read 3, iclass 35, count 0 2006.257.15:01:39.15#ibcon#about to read 4, iclass 35, count 0 2006.257.15:01:39.15#ibcon#read 4, iclass 35, count 0 2006.257.15:01:39.15#ibcon#about to read 5, iclass 35, count 0 2006.257.15:01:39.15#ibcon#read 5, iclass 35, count 0 2006.257.15:01:39.15#ibcon#about to read 6, iclass 35, count 0 2006.257.15:01:39.15#ibcon#read 6, iclass 35, count 0 2006.257.15:01:39.15#ibcon#end of sib2, iclass 35, count 0 2006.257.15:01:39.15#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:01:39.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:01:39.15#ibcon#[25=BW32\r\n] 2006.257.15:01:39.15#ibcon#*before write, iclass 35, count 0 2006.257.15:01:39.15#ibcon#enter sib2, iclass 35, count 0 2006.257.15:01:39.15#ibcon#flushed, iclass 35, count 0 2006.257.15:01:39.15#ibcon#about to write, iclass 35, count 0 2006.257.15:01:39.15#ibcon#wrote, iclass 35, count 0 2006.257.15:01:39.15#ibcon#about to read 3, iclass 35, count 0 2006.257.15:01:39.18#ibcon#read 3, iclass 35, count 0 2006.257.15:01:39.18#ibcon#about to read 4, iclass 35, count 0 2006.257.15:01:39.18#ibcon#read 4, iclass 35, count 0 2006.257.15:01:39.18#ibcon#about to read 5, iclass 35, count 0 2006.257.15:01:39.18#ibcon#read 5, iclass 35, count 0 2006.257.15:01:39.18#ibcon#about to read 6, iclass 35, count 0 2006.257.15:01:39.18#ibcon#read 6, iclass 35, count 0 2006.257.15:01:39.18#ibcon#end of sib2, iclass 35, count 0 2006.257.15:01:39.18#ibcon#*after write, iclass 35, count 0 2006.257.15:01:39.18#ibcon#*before return 0, iclass 35, count 0 2006.257.15:01:39.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:39.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:01:39.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:01:39.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:01:39.18$vck44/vbbw=wide 2006.257.15:01:39.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.15:01:39.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.15:01:39.18#ibcon#ireg 8 cls_cnt 0 2006.257.15:01:39.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:01:39.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:01:39.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:01:39.18#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:01:39.18#ibcon#first serial, iclass 38, count 0 2006.257.15:01:39.18#ibcon#enter sib2, iclass 38, count 0 2006.257.15:01:39.18#ibcon#flushed, iclass 38, count 0 2006.257.15:01:39.18#ibcon#about to write, iclass 38, count 0 2006.257.15:01:39.18#ibcon#wrote, iclass 38, count 0 2006.257.15:01:39.18#ibcon#about to read 3, iclass 38, count 0 2006.257.15:01:39.20#ibcon#read 3, iclass 38, count 0 2006.257.15:01:39.20#ibcon#about to read 4, iclass 38, count 0 2006.257.15:01:39.20#ibcon#read 4, iclass 38, count 0 2006.257.15:01:39.20#ibcon#about to read 5, iclass 38, count 0 2006.257.15:01:39.20#ibcon#read 5, iclass 38, count 0 2006.257.15:01:39.20#ibcon#about to read 6, iclass 38, count 0 2006.257.15:01:39.20#ibcon#read 6, iclass 38, count 0 2006.257.15:01:39.20#ibcon#end of sib2, iclass 38, count 0 2006.257.15:01:39.20#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:01:39.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:01:39.20#ibcon#[27=BW32\r\n] 2006.257.15:01:39.20#ibcon#*before write, iclass 38, count 0 2006.257.15:01:39.20#ibcon#enter sib2, iclass 38, count 0 2006.257.15:01:39.20#ibcon#flushed, iclass 38, count 0 2006.257.15:01:39.20#ibcon#about to write, iclass 38, count 0 2006.257.15:01:39.20#ibcon#wrote, iclass 38, count 0 2006.257.15:01:39.20#ibcon#about to read 3, iclass 38, count 0 2006.257.15:01:39.23#ibcon#read 3, iclass 38, count 0 2006.257.15:01:39.23#ibcon#about to read 4, iclass 38, count 0 2006.257.15:01:39.23#ibcon#read 4, iclass 38, count 0 2006.257.15:01:39.23#ibcon#about to read 5, iclass 38, count 0 2006.257.15:01:39.23#ibcon#read 5, iclass 38, count 0 2006.257.15:01:39.23#ibcon#about to read 6, iclass 38, count 0 2006.257.15:01:39.23#ibcon#read 6, iclass 38, count 0 2006.257.15:01:39.23#ibcon#end of sib2, iclass 38, count 0 2006.257.15:01:39.23#ibcon#*after write, iclass 38, count 0 2006.257.15:01:39.23#ibcon#*before return 0, iclass 38, count 0 2006.257.15:01:39.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:01:39.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:01:39.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:01:39.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:01:39.23$setupk4/ifdk4 2006.257.15:01:39.23$ifdk4/lo= 2006.257.15:01:39.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:01:39.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:01:39.23$ifdk4/patch= 2006.257.15:01:39.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:01:39.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:01:39.23$setupk4/!*+20s 2006.257.15:01:52.22#abcon#{5=INTERFACE CLEAR} 2006.257.15:01:52.28#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:01:52.34$setupk4/"tpicd 2006.257.15:01:52.34$setupk4/echo=off 2006.257.15:01:52.34$setupk4/xlog=off 2006.257.15:01:52.34:!2006.257.15:03:27 2006.257.15:02:00.14#trakl#Source acquired 2006.257.15:02:00.14#flagr#flagr/antenna,acquired 2006.257.15:03:27.02:preob 2006.257.15:03:28.14/onsource/TRACKING 2006.257.15:03:28.14:!2006.257.15:03:37 2006.257.15:03:37.02:"tape 2006.257.15:03:37.02:"st=record 2006.257.15:03:37.02:data_valid=on 2006.257.15:03:37.02:midob 2006.257.15:03:38.14/onsource/TRACKING 2006.257.15:03:38.14/wx/17.43,1014.0,97 2006.257.15:03:38.20/cable/+6.4838E-03 2006.257.15:03:39.29/va/01,08,usb,yes,32,35 2006.257.15:03:39.29/va/02,07,usb,yes,35,36 2006.257.15:03:39.29/va/03,08,usb,yes,31,33 2006.257.15:03:39.29/va/04,07,usb,yes,36,38 2006.257.15:03:39.29/va/05,04,usb,yes,32,33 2006.257.15:03:39.29/va/06,04,usb,yes,36,36 2006.257.15:03:39.29/va/07,04,usb,yes,37,37 2006.257.15:03:39.29/va/08,04,usb,yes,31,38 2006.257.15:03:39.52/valo/01,524.99,yes,locked 2006.257.15:03:39.52/valo/02,534.99,yes,locked 2006.257.15:03:39.52/valo/03,564.99,yes,locked 2006.257.15:03:39.52/valo/04,624.99,yes,locked 2006.257.15:03:39.52/valo/05,734.99,yes,locked 2006.257.15:03:39.52/valo/06,814.99,yes,locked 2006.257.15:03:39.52/valo/07,864.99,yes,locked 2006.257.15:03:39.52/valo/08,884.99,yes,locked 2006.257.15:03:40.61/vb/01,04,usb,yes,30,40 2006.257.15:03:40.61/vb/02,05,usb,yes,29,36 2006.257.15:03:40.61/vb/03,04,usb,yes,31,34 2006.257.15:03:40.61/vb/04,05,usb,yes,30,29 2006.257.15:03:40.61/vb/05,04,usb,yes,27,30 2006.257.15:03:40.61/vb/06,04,usb,yes,33,29 2006.257.15:03:40.61/vb/07,04,usb,yes,31,32 2006.257.15:03:40.61/vb/08,04,usb,yes,29,32 2006.257.15:03:40.84/vblo/01,629.99,yes,locked 2006.257.15:03:40.84/vblo/02,634.99,yes,locked 2006.257.15:03:40.84/vblo/03,649.99,yes,locked 2006.257.15:03:40.84/vblo/04,679.99,yes,locked 2006.257.15:03:40.84/vblo/05,709.99,yes,locked 2006.257.15:03:40.84/vblo/06,719.99,yes,locked 2006.257.15:03:40.84/vblo/07,734.99,yes,locked 2006.257.15:03:40.84/vblo/08,744.99,yes,locked 2006.257.15:03:40.99/vabw/8 2006.257.15:03:41.14/vbbw/8 2006.257.15:03:41.25/xfe/off,on,15.2 2006.257.15:03:41.63/ifatt/23,28,28,28 2006.257.15:03:42.07/fmout-gps/S +4.62E-07 2006.257.15:03:42.11:!2006.257.15:07:37 2006.257.15:07:37.01:data_valid=off 2006.257.15:07:37.01:"et 2006.257.15:07:37.02:!+3s 2006.257.15:07:40.04:"tape 2006.257.15:07:40.04:postob 2006.257.15:07:40.23/cable/+6.4829E-03 2006.257.15:07:40.23/wx/17.43,1014.0,97 2006.257.15:07:40.29/fmout-gps/S +4.62E-07 2006.257.15:07:40.29:scan_name=257-1508,jd0609,250 2006.257.15:07:40.29:source=1803+784,180045.68,782804.0,2000.0,ccw 2006.257.15:07:41.14#flagr#flagr/antenna,new-source 2006.257.15:07:41.14:checkk5 2006.257.15:07:41.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:07:41.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:07:42.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:07:42.80/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:07:43.19/chk_obsdata//k5ts1/T2571503??a.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.15:07:43.59/chk_obsdata//k5ts2/T2571503??b.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.15:07:44.00/chk_obsdata//k5ts3/T2571503??c.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.15:07:44.43/chk_obsdata//k5ts4/T2571503??d.dat file size is correct (nominal:960MB, actual:960MB). 2006.257.15:07:45.14/k5log//k5ts1_log_newline 2006.257.15:07:45.84/k5log//k5ts2_log_newline 2006.257.15:07:46.56/k5log//k5ts3_log_newline 2006.257.15:07:47.32/k5log//k5ts4_log_newline 2006.257.15:07:47.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:07:47.34:setupk4=1 2006.257.15:07:47.34$setupk4/echo=on 2006.257.15:07:47.34$setupk4/pcalon 2006.257.15:07:47.34$pcalon/"no phase cal control is implemented here 2006.257.15:07:47.34$setupk4/"tpicd=stop 2006.257.15:07:47.34$setupk4/"rec=synch_on 2006.257.15:07:47.34$setupk4/"rec_mode=128 2006.257.15:07:47.34$setupk4/!* 2006.257.15:07:47.34$setupk4/recpk4 2006.257.15:07:47.34$recpk4/recpatch= 2006.257.15:07:47.35$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:07:47.35$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:07:47.35$setupk4/vck44 2006.257.15:07:47.35$vck44/valo=1,524.99 2006.257.15:07:47.35#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.15:07:47.35#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.15:07:47.35#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:47.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:47.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:47.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:47.35#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:07:47.35#ibcon#first serial, iclass 37, count 0 2006.257.15:07:47.35#ibcon#enter sib2, iclass 37, count 0 2006.257.15:07:47.35#ibcon#flushed, iclass 37, count 0 2006.257.15:07:47.35#ibcon#about to write, iclass 37, count 0 2006.257.15:07:47.35#ibcon#wrote, iclass 37, count 0 2006.257.15:07:47.35#ibcon#about to read 3, iclass 37, count 0 2006.257.15:07:47.37#ibcon#read 3, iclass 37, count 0 2006.257.15:07:47.37#ibcon#about to read 4, iclass 37, count 0 2006.257.15:07:47.37#ibcon#read 4, iclass 37, count 0 2006.257.15:07:47.37#ibcon#about to read 5, iclass 37, count 0 2006.257.15:07:47.37#ibcon#read 5, iclass 37, count 0 2006.257.15:07:47.37#ibcon#about to read 6, iclass 37, count 0 2006.257.15:07:47.37#ibcon#read 6, iclass 37, count 0 2006.257.15:07:47.37#ibcon#end of sib2, iclass 37, count 0 2006.257.15:07:47.37#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:07:47.37#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:07:47.37#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:07:47.37#ibcon#*before write, iclass 37, count 0 2006.257.15:07:47.37#ibcon#enter sib2, iclass 37, count 0 2006.257.15:07:47.37#ibcon#flushed, iclass 37, count 0 2006.257.15:07:47.37#ibcon#about to write, iclass 37, count 0 2006.257.15:07:47.37#ibcon#wrote, iclass 37, count 0 2006.257.15:07:47.37#ibcon#about to read 3, iclass 37, count 0 2006.257.15:07:47.42#ibcon#read 3, iclass 37, count 0 2006.257.15:07:47.42#ibcon#about to read 4, iclass 37, count 0 2006.257.15:07:47.42#ibcon#read 4, iclass 37, count 0 2006.257.15:07:47.42#ibcon#about to read 5, iclass 37, count 0 2006.257.15:07:47.42#ibcon#read 5, iclass 37, count 0 2006.257.15:07:47.42#ibcon#about to read 6, iclass 37, count 0 2006.257.15:07:47.42#ibcon#read 6, iclass 37, count 0 2006.257.15:07:47.42#ibcon#end of sib2, iclass 37, count 0 2006.257.15:07:47.42#ibcon#*after write, iclass 37, count 0 2006.257.15:07:47.42#ibcon#*before return 0, iclass 37, count 0 2006.257.15:07:47.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:47.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:47.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:07:47.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:07:47.42$vck44/va=1,8 2006.257.15:07:47.42#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.15:07:47.42#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.15:07:47.42#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:47.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:47.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:47.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:47.42#ibcon#enter wrdev, iclass 39, count 2 2006.257.15:07:47.42#ibcon#first serial, iclass 39, count 2 2006.257.15:07:47.42#ibcon#enter sib2, iclass 39, count 2 2006.257.15:07:47.42#ibcon#flushed, iclass 39, count 2 2006.257.15:07:47.42#ibcon#about to write, iclass 39, count 2 2006.257.15:07:47.42#ibcon#wrote, iclass 39, count 2 2006.257.15:07:47.42#ibcon#about to read 3, iclass 39, count 2 2006.257.15:07:47.44#ibcon#read 3, iclass 39, count 2 2006.257.15:07:47.44#ibcon#about to read 4, iclass 39, count 2 2006.257.15:07:47.44#ibcon#read 4, iclass 39, count 2 2006.257.15:07:47.44#ibcon#about to read 5, iclass 39, count 2 2006.257.15:07:47.44#ibcon#read 5, iclass 39, count 2 2006.257.15:07:47.44#ibcon#about to read 6, iclass 39, count 2 2006.257.15:07:47.44#ibcon#read 6, iclass 39, count 2 2006.257.15:07:47.44#ibcon#end of sib2, iclass 39, count 2 2006.257.15:07:47.44#ibcon#*mode == 0, iclass 39, count 2 2006.257.15:07:47.44#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.15:07:47.44#ibcon#[25=AT01-08\r\n] 2006.257.15:07:47.44#ibcon#*before write, iclass 39, count 2 2006.257.15:07:47.44#ibcon#enter sib2, iclass 39, count 2 2006.257.15:07:47.44#ibcon#flushed, iclass 39, count 2 2006.257.15:07:47.44#ibcon#about to write, iclass 39, count 2 2006.257.15:07:47.44#ibcon#wrote, iclass 39, count 2 2006.257.15:07:47.44#ibcon#about to read 3, iclass 39, count 2 2006.257.15:07:47.47#ibcon#read 3, iclass 39, count 2 2006.257.15:07:47.47#ibcon#about to read 4, iclass 39, count 2 2006.257.15:07:47.47#ibcon#read 4, iclass 39, count 2 2006.257.15:07:47.47#ibcon#about to read 5, iclass 39, count 2 2006.257.15:07:47.47#ibcon#read 5, iclass 39, count 2 2006.257.15:07:47.47#ibcon#about to read 6, iclass 39, count 2 2006.257.15:07:47.47#ibcon#read 6, iclass 39, count 2 2006.257.15:07:47.47#ibcon#end of sib2, iclass 39, count 2 2006.257.15:07:47.47#ibcon#*after write, iclass 39, count 2 2006.257.15:07:47.47#ibcon#*before return 0, iclass 39, count 2 2006.257.15:07:47.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:47.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:47.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.15:07:47.47#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:47.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:47.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:47.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:47.59#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:07:47.59#ibcon#first serial, iclass 39, count 0 2006.257.15:07:47.59#ibcon#enter sib2, iclass 39, count 0 2006.257.15:07:47.59#ibcon#flushed, iclass 39, count 0 2006.257.15:07:47.59#ibcon#about to write, iclass 39, count 0 2006.257.15:07:47.59#ibcon#wrote, iclass 39, count 0 2006.257.15:07:47.59#ibcon#about to read 3, iclass 39, count 0 2006.257.15:07:47.61#ibcon#read 3, iclass 39, count 0 2006.257.15:07:47.61#ibcon#about to read 4, iclass 39, count 0 2006.257.15:07:47.61#ibcon#read 4, iclass 39, count 0 2006.257.15:07:47.61#ibcon#about to read 5, iclass 39, count 0 2006.257.15:07:47.61#ibcon#read 5, iclass 39, count 0 2006.257.15:07:47.61#ibcon#about to read 6, iclass 39, count 0 2006.257.15:07:47.61#ibcon#read 6, iclass 39, count 0 2006.257.15:07:47.61#ibcon#end of sib2, iclass 39, count 0 2006.257.15:07:47.61#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:07:47.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:07:47.61#ibcon#[25=USB\r\n] 2006.257.15:07:47.61#ibcon#*before write, iclass 39, count 0 2006.257.15:07:47.61#ibcon#enter sib2, iclass 39, count 0 2006.257.15:07:47.61#ibcon#flushed, iclass 39, count 0 2006.257.15:07:47.61#ibcon#about to write, iclass 39, count 0 2006.257.15:07:47.61#ibcon#wrote, iclass 39, count 0 2006.257.15:07:47.61#ibcon#about to read 3, iclass 39, count 0 2006.257.15:07:47.64#ibcon#read 3, iclass 39, count 0 2006.257.15:07:47.64#ibcon#about to read 4, iclass 39, count 0 2006.257.15:07:47.64#ibcon#read 4, iclass 39, count 0 2006.257.15:07:47.64#ibcon#about to read 5, iclass 39, count 0 2006.257.15:07:47.64#ibcon#read 5, iclass 39, count 0 2006.257.15:07:47.64#ibcon#about to read 6, iclass 39, count 0 2006.257.15:07:47.64#ibcon#read 6, iclass 39, count 0 2006.257.15:07:47.64#ibcon#end of sib2, iclass 39, count 0 2006.257.15:07:47.64#ibcon#*after write, iclass 39, count 0 2006.257.15:07:47.64#ibcon#*before return 0, iclass 39, count 0 2006.257.15:07:47.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:47.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:47.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:07:47.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:07:47.64$vck44/valo=2,534.99 2006.257.15:07:47.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.15:07:47.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.15:07:47.64#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:47.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:47.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:47.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:47.64#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:07:47.64#ibcon#first serial, iclass 3, count 0 2006.257.15:07:47.64#ibcon#enter sib2, iclass 3, count 0 2006.257.15:07:47.64#ibcon#flushed, iclass 3, count 0 2006.257.15:07:47.64#ibcon#about to write, iclass 3, count 0 2006.257.15:07:47.64#ibcon#wrote, iclass 3, count 0 2006.257.15:07:47.64#ibcon#about to read 3, iclass 3, count 0 2006.257.15:07:47.66#ibcon#read 3, iclass 3, count 0 2006.257.15:07:47.66#ibcon#about to read 4, iclass 3, count 0 2006.257.15:07:47.66#ibcon#read 4, iclass 3, count 0 2006.257.15:07:47.66#ibcon#about to read 5, iclass 3, count 0 2006.257.15:07:47.66#ibcon#read 5, iclass 3, count 0 2006.257.15:07:47.66#ibcon#about to read 6, iclass 3, count 0 2006.257.15:07:47.66#ibcon#read 6, iclass 3, count 0 2006.257.15:07:47.66#ibcon#end of sib2, iclass 3, count 0 2006.257.15:07:47.66#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:07:47.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:07:47.66#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:07:47.66#ibcon#*before write, iclass 3, count 0 2006.257.15:07:47.66#ibcon#enter sib2, iclass 3, count 0 2006.257.15:07:47.66#ibcon#flushed, iclass 3, count 0 2006.257.15:07:47.66#ibcon#about to write, iclass 3, count 0 2006.257.15:07:47.66#ibcon#wrote, iclass 3, count 0 2006.257.15:07:47.66#ibcon#about to read 3, iclass 3, count 0 2006.257.15:07:47.70#ibcon#read 3, iclass 3, count 0 2006.257.15:07:47.70#ibcon#about to read 4, iclass 3, count 0 2006.257.15:07:47.70#ibcon#read 4, iclass 3, count 0 2006.257.15:07:47.70#ibcon#about to read 5, iclass 3, count 0 2006.257.15:07:47.70#ibcon#read 5, iclass 3, count 0 2006.257.15:07:47.70#ibcon#about to read 6, iclass 3, count 0 2006.257.15:07:47.70#ibcon#read 6, iclass 3, count 0 2006.257.15:07:47.70#ibcon#end of sib2, iclass 3, count 0 2006.257.15:07:47.70#ibcon#*after write, iclass 3, count 0 2006.257.15:07:47.70#ibcon#*before return 0, iclass 3, count 0 2006.257.15:07:47.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:47.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:47.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:07:47.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:07:47.70$vck44/va=2,7 2006.257.15:07:47.70#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.15:07:47.70#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.15:07:47.70#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:47.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:47.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:47.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:47.76#ibcon#enter wrdev, iclass 5, count 2 2006.257.15:07:47.76#ibcon#first serial, iclass 5, count 2 2006.257.15:07:47.76#ibcon#enter sib2, iclass 5, count 2 2006.257.15:07:47.76#ibcon#flushed, iclass 5, count 2 2006.257.15:07:47.76#ibcon#about to write, iclass 5, count 2 2006.257.15:07:47.76#ibcon#wrote, iclass 5, count 2 2006.257.15:07:47.76#ibcon#about to read 3, iclass 5, count 2 2006.257.15:07:47.78#ibcon#read 3, iclass 5, count 2 2006.257.15:07:47.78#ibcon#about to read 4, iclass 5, count 2 2006.257.15:07:47.78#ibcon#read 4, iclass 5, count 2 2006.257.15:07:47.78#ibcon#about to read 5, iclass 5, count 2 2006.257.15:07:47.78#ibcon#read 5, iclass 5, count 2 2006.257.15:07:47.78#ibcon#about to read 6, iclass 5, count 2 2006.257.15:07:47.78#ibcon#read 6, iclass 5, count 2 2006.257.15:07:47.78#ibcon#end of sib2, iclass 5, count 2 2006.257.15:07:47.78#ibcon#*mode == 0, iclass 5, count 2 2006.257.15:07:47.78#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.15:07:47.78#ibcon#[25=AT02-07\r\n] 2006.257.15:07:47.78#ibcon#*before write, iclass 5, count 2 2006.257.15:07:47.78#ibcon#enter sib2, iclass 5, count 2 2006.257.15:07:47.78#ibcon#flushed, iclass 5, count 2 2006.257.15:07:47.78#ibcon#about to write, iclass 5, count 2 2006.257.15:07:47.78#ibcon#wrote, iclass 5, count 2 2006.257.15:07:47.78#ibcon#about to read 3, iclass 5, count 2 2006.257.15:07:47.81#ibcon#read 3, iclass 5, count 2 2006.257.15:07:47.81#ibcon#about to read 4, iclass 5, count 2 2006.257.15:07:47.81#ibcon#read 4, iclass 5, count 2 2006.257.15:07:47.81#ibcon#about to read 5, iclass 5, count 2 2006.257.15:07:47.81#ibcon#read 5, iclass 5, count 2 2006.257.15:07:47.81#ibcon#about to read 6, iclass 5, count 2 2006.257.15:07:47.81#ibcon#read 6, iclass 5, count 2 2006.257.15:07:47.81#ibcon#end of sib2, iclass 5, count 2 2006.257.15:07:47.81#ibcon#*after write, iclass 5, count 2 2006.257.15:07:47.81#ibcon#*before return 0, iclass 5, count 2 2006.257.15:07:47.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:47.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:47.81#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.15:07:47.81#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:47.81#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:47.93#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:47.93#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:47.93#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:07:47.93#ibcon#first serial, iclass 5, count 0 2006.257.15:07:47.93#ibcon#enter sib2, iclass 5, count 0 2006.257.15:07:47.93#ibcon#flushed, iclass 5, count 0 2006.257.15:07:47.93#ibcon#about to write, iclass 5, count 0 2006.257.15:07:47.93#ibcon#wrote, iclass 5, count 0 2006.257.15:07:47.93#ibcon#about to read 3, iclass 5, count 0 2006.257.15:07:47.95#ibcon#read 3, iclass 5, count 0 2006.257.15:07:47.95#ibcon#about to read 4, iclass 5, count 0 2006.257.15:07:47.95#ibcon#read 4, iclass 5, count 0 2006.257.15:07:47.95#ibcon#about to read 5, iclass 5, count 0 2006.257.15:07:47.95#ibcon#read 5, iclass 5, count 0 2006.257.15:07:47.95#ibcon#about to read 6, iclass 5, count 0 2006.257.15:07:47.95#ibcon#read 6, iclass 5, count 0 2006.257.15:07:47.95#ibcon#end of sib2, iclass 5, count 0 2006.257.15:07:47.95#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:07:47.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:07:47.95#ibcon#[25=USB\r\n] 2006.257.15:07:47.95#ibcon#*before write, iclass 5, count 0 2006.257.15:07:47.95#ibcon#enter sib2, iclass 5, count 0 2006.257.15:07:47.95#ibcon#flushed, iclass 5, count 0 2006.257.15:07:47.95#ibcon#about to write, iclass 5, count 0 2006.257.15:07:47.95#ibcon#wrote, iclass 5, count 0 2006.257.15:07:47.95#ibcon#about to read 3, iclass 5, count 0 2006.257.15:07:47.98#ibcon#read 3, iclass 5, count 0 2006.257.15:07:47.98#ibcon#about to read 4, iclass 5, count 0 2006.257.15:07:47.98#ibcon#read 4, iclass 5, count 0 2006.257.15:07:47.98#ibcon#about to read 5, iclass 5, count 0 2006.257.15:07:47.98#ibcon#read 5, iclass 5, count 0 2006.257.15:07:47.98#ibcon#about to read 6, iclass 5, count 0 2006.257.15:07:47.98#ibcon#read 6, iclass 5, count 0 2006.257.15:07:47.98#ibcon#end of sib2, iclass 5, count 0 2006.257.15:07:47.98#ibcon#*after write, iclass 5, count 0 2006.257.15:07:47.98#ibcon#*before return 0, iclass 5, count 0 2006.257.15:07:47.98#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:47.98#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:47.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:07:47.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:07:47.98$vck44/valo=3,564.99 2006.257.15:07:47.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.15:07:47.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.15:07:47.98#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:47.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:47.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:47.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:47.98#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:07:47.98#ibcon#first serial, iclass 7, count 0 2006.257.15:07:47.98#ibcon#enter sib2, iclass 7, count 0 2006.257.15:07:47.98#ibcon#flushed, iclass 7, count 0 2006.257.15:07:47.98#ibcon#about to write, iclass 7, count 0 2006.257.15:07:47.98#ibcon#wrote, iclass 7, count 0 2006.257.15:07:47.98#ibcon#about to read 3, iclass 7, count 0 2006.257.15:07:48.00#ibcon#read 3, iclass 7, count 0 2006.257.15:07:48.00#ibcon#about to read 4, iclass 7, count 0 2006.257.15:07:48.00#ibcon#read 4, iclass 7, count 0 2006.257.15:07:48.00#ibcon#about to read 5, iclass 7, count 0 2006.257.15:07:48.00#ibcon#read 5, iclass 7, count 0 2006.257.15:07:48.00#ibcon#about to read 6, iclass 7, count 0 2006.257.15:07:48.00#ibcon#read 6, iclass 7, count 0 2006.257.15:07:48.00#ibcon#end of sib2, iclass 7, count 0 2006.257.15:07:48.00#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:07:48.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:07:48.00#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:07:48.00#ibcon#*before write, iclass 7, count 0 2006.257.15:07:48.00#ibcon#enter sib2, iclass 7, count 0 2006.257.15:07:48.00#ibcon#flushed, iclass 7, count 0 2006.257.15:07:48.00#ibcon#about to write, iclass 7, count 0 2006.257.15:07:48.00#ibcon#wrote, iclass 7, count 0 2006.257.15:07:48.00#ibcon#about to read 3, iclass 7, count 0 2006.257.15:07:48.04#ibcon#read 3, iclass 7, count 0 2006.257.15:07:48.04#ibcon#about to read 4, iclass 7, count 0 2006.257.15:07:48.04#ibcon#read 4, iclass 7, count 0 2006.257.15:07:48.04#ibcon#about to read 5, iclass 7, count 0 2006.257.15:07:48.04#ibcon#read 5, iclass 7, count 0 2006.257.15:07:48.04#ibcon#about to read 6, iclass 7, count 0 2006.257.15:07:48.04#ibcon#read 6, iclass 7, count 0 2006.257.15:07:48.04#ibcon#end of sib2, iclass 7, count 0 2006.257.15:07:48.04#ibcon#*after write, iclass 7, count 0 2006.257.15:07:48.04#ibcon#*before return 0, iclass 7, count 0 2006.257.15:07:48.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:48.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:48.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:07:48.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:07:48.04$vck44/va=3,8 2006.257.15:07:48.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.15:07:48.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.15:07:48.04#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:48.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:48.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:48.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:48.10#ibcon#enter wrdev, iclass 11, count 2 2006.257.15:07:48.10#ibcon#first serial, iclass 11, count 2 2006.257.15:07:48.10#ibcon#enter sib2, iclass 11, count 2 2006.257.15:07:48.10#ibcon#flushed, iclass 11, count 2 2006.257.15:07:48.10#ibcon#about to write, iclass 11, count 2 2006.257.15:07:48.10#ibcon#wrote, iclass 11, count 2 2006.257.15:07:48.10#ibcon#about to read 3, iclass 11, count 2 2006.257.15:07:48.12#ibcon#read 3, iclass 11, count 2 2006.257.15:07:48.12#ibcon#about to read 4, iclass 11, count 2 2006.257.15:07:48.12#ibcon#read 4, iclass 11, count 2 2006.257.15:07:48.12#ibcon#about to read 5, iclass 11, count 2 2006.257.15:07:48.12#ibcon#read 5, iclass 11, count 2 2006.257.15:07:48.12#ibcon#about to read 6, iclass 11, count 2 2006.257.15:07:48.12#ibcon#read 6, iclass 11, count 2 2006.257.15:07:48.12#ibcon#end of sib2, iclass 11, count 2 2006.257.15:07:48.12#ibcon#*mode == 0, iclass 11, count 2 2006.257.15:07:48.12#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.15:07:48.12#ibcon#[25=AT03-08\r\n] 2006.257.15:07:48.12#ibcon#*before write, iclass 11, count 2 2006.257.15:07:48.12#ibcon#enter sib2, iclass 11, count 2 2006.257.15:07:48.12#ibcon#flushed, iclass 11, count 2 2006.257.15:07:48.12#ibcon#about to write, iclass 11, count 2 2006.257.15:07:48.12#ibcon#wrote, iclass 11, count 2 2006.257.15:07:48.12#ibcon#about to read 3, iclass 11, count 2 2006.257.15:07:48.14#abcon#<5=/14 1.6 3.8 17.43 971014.0\r\n> 2006.257.15:07:48.15#ibcon#read 3, iclass 11, count 2 2006.257.15:07:48.15#ibcon#about to read 4, iclass 11, count 2 2006.257.15:07:48.15#ibcon#read 4, iclass 11, count 2 2006.257.15:07:48.15#ibcon#about to read 5, iclass 11, count 2 2006.257.15:07:48.15#ibcon#read 5, iclass 11, count 2 2006.257.15:07:48.15#ibcon#about to read 6, iclass 11, count 2 2006.257.15:07:48.15#ibcon#read 6, iclass 11, count 2 2006.257.15:07:48.15#ibcon#end of sib2, iclass 11, count 2 2006.257.15:07:48.15#ibcon#*after write, iclass 11, count 2 2006.257.15:07:48.15#ibcon#*before return 0, iclass 11, count 2 2006.257.15:07:48.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:48.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:48.15#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.15:07:48.15#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:48.15#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:48.16#abcon#{5=INTERFACE CLEAR} 2006.257.15:07:48.22#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:07:48.27#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:48.27#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:48.27#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:07:48.27#ibcon#first serial, iclass 11, count 0 2006.257.15:07:48.27#ibcon#enter sib2, iclass 11, count 0 2006.257.15:07:48.27#ibcon#flushed, iclass 11, count 0 2006.257.15:07:48.27#ibcon#about to write, iclass 11, count 0 2006.257.15:07:48.27#ibcon#wrote, iclass 11, count 0 2006.257.15:07:48.27#ibcon#about to read 3, iclass 11, count 0 2006.257.15:07:48.29#ibcon#read 3, iclass 11, count 0 2006.257.15:07:48.29#ibcon#about to read 4, iclass 11, count 0 2006.257.15:07:48.29#ibcon#read 4, iclass 11, count 0 2006.257.15:07:48.29#ibcon#about to read 5, iclass 11, count 0 2006.257.15:07:48.29#ibcon#read 5, iclass 11, count 0 2006.257.15:07:48.29#ibcon#about to read 6, iclass 11, count 0 2006.257.15:07:48.29#ibcon#read 6, iclass 11, count 0 2006.257.15:07:48.29#ibcon#end of sib2, iclass 11, count 0 2006.257.15:07:48.29#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:07:48.29#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:07:48.29#ibcon#[25=USB\r\n] 2006.257.15:07:48.29#ibcon#*before write, iclass 11, count 0 2006.257.15:07:48.29#ibcon#enter sib2, iclass 11, count 0 2006.257.15:07:48.29#ibcon#flushed, iclass 11, count 0 2006.257.15:07:48.29#ibcon#about to write, iclass 11, count 0 2006.257.15:07:48.29#ibcon#wrote, iclass 11, count 0 2006.257.15:07:48.29#ibcon#about to read 3, iclass 11, count 0 2006.257.15:07:48.32#ibcon#read 3, iclass 11, count 0 2006.257.15:07:48.32#ibcon#about to read 4, iclass 11, count 0 2006.257.15:07:48.32#ibcon#read 4, iclass 11, count 0 2006.257.15:07:48.32#ibcon#about to read 5, iclass 11, count 0 2006.257.15:07:48.32#ibcon#read 5, iclass 11, count 0 2006.257.15:07:48.32#ibcon#about to read 6, iclass 11, count 0 2006.257.15:07:48.32#ibcon#read 6, iclass 11, count 0 2006.257.15:07:48.32#ibcon#end of sib2, iclass 11, count 0 2006.257.15:07:48.32#ibcon#*after write, iclass 11, count 0 2006.257.15:07:48.32#ibcon#*before return 0, iclass 11, count 0 2006.257.15:07:48.32#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:48.32#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:48.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:07:48.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:07:48.32$vck44/valo=4,624.99 2006.257.15:07:48.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.15:07:48.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.15:07:48.32#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:48.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:48.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:48.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:48.32#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:07:48.32#ibcon#first serial, iclass 17, count 0 2006.257.15:07:48.32#ibcon#enter sib2, iclass 17, count 0 2006.257.15:07:48.32#ibcon#flushed, iclass 17, count 0 2006.257.15:07:48.32#ibcon#about to write, iclass 17, count 0 2006.257.15:07:48.32#ibcon#wrote, iclass 17, count 0 2006.257.15:07:48.32#ibcon#about to read 3, iclass 17, count 0 2006.257.15:07:48.34#ibcon#read 3, iclass 17, count 0 2006.257.15:07:48.34#ibcon#about to read 4, iclass 17, count 0 2006.257.15:07:48.34#ibcon#read 4, iclass 17, count 0 2006.257.15:07:48.34#ibcon#about to read 5, iclass 17, count 0 2006.257.15:07:48.34#ibcon#read 5, iclass 17, count 0 2006.257.15:07:48.34#ibcon#about to read 6, iclass 17, count 0 2006.257.15:07:48.34#ibcon#read 6, iclass 17, count 0 2006.257.15:07:48.34#ibcon#end of sib2, iclass 17, count 0 2006.257.15:07:48.34#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:07:48.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:07:48.34#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:07:48.34#ibcon#*before write, iclass 17, count 0 2006.257.15:07:48.34#ibcon#enter sib2, iclass 17, count 0 2006.257.15:07:48.34#ibcon#flushed, iclass 17, count 0 2006.257.15:07:48.34#ibcon#about to write, iclass 17, count 0 2006.257.15:07:48.34#ibcon#wrote, iclass 17, count 0 2006.257.15:07:48.34#ibcon#about to read 3, iclass 17, count 0 2006.257.15:07:48.38#ibcon#read 3, iclass 17, count 0 2006.257.15:07:48.38#ibcon#about to read 4, iclass 17, count 0 2006.257.15:07:48.38#ibcon#read 4, iclass 17, count 0 2006.257.15:07:48.38#ibcon#about to read 5, iclass 17, count 0 2006.257.15:07:48.38#ibcon#read 5, iclass 17, count 0 2006.257.15:07:48.38#ibcon#about to read 6, iclass 17, count 0 2006.257.15:07:48.38#ibcon#read 6, iclass 17, count 0 2006.257.15:07:48.38#ibcon#end of sib2, iclass 17, count 0 2006.257.15:07:48.38#ibcon#*after write, iclass 17, count 0 2006.257.15:07:48.38#ibcon#*before return 0, iclass 17, count 0 2006.257.15:07:48.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:48.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:48.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:07:48.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:07:48.38$vck44/va=4,7 2006.257.15:07:48.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.15:07:48.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.15:07:48.38#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:48.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:48.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:48.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:48.44#ibcon#enter wrdev, iclass 19, count 2 2006.257.15:07:48.44#ibcon#first serial, iclass 19, count 2 2006.257.15:07:48.44#ibcon#enter sib2, iclass 19, count 2 2006.257.15:07:48.44#ibcon#flushed, iclass 19, count 2 2006.257.15:07:48.44#ibcon#about to write, iclass 19, count 2 2006.257.15:07:48.44#ibcon#wrote, iclass 19, count 2 2006.257.15:07:48.44#ibcon#about to read 3, iclass 19, count 2 2006.257.15:07:48.46#ibcon#read 3, iclass 19, count 2 2006.257.15:07:48.46#ibcon#about to read 4, iclass 19, count 2 2006.257.15:07:48.46#ibcon#read 4, iclass 19, count 2 2006.257.15:07:48.46#ibcon#about to read 5, iclass 19, count 2 2006.257.15:07:48.46#ibcon#read 5, iclass 19, count 2 2006.257.15:07:48.46#ibcon#about to read 6, iclass 19, count 2 2006.257.15:07:48.46#ibcon#read 6, iclass 19, count 2 2006.257.15:07:48.46#ibcon#end of sib2, iclass 19, count 2 2006.257.15:07:48.46#ibcon#*mode == 0, iclass 19, count 2 2006.257.15:07:48.46#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.15:07:48.46#ibcon#[25=AT04-07\r\n] 2006.257.15:07:48.46#ibcon#*before write, iclass 19, count 2 2006.257.15:07:48.46#ibcon#enter sib2, iclass 19, count 2 2006.257.15:07:48.46#ibcon#flushed, iclass 19, count 2 2006.257.15:07:48.46#ibcon#about to write, iclass 19, count 2 2006.257.15:07:48.46#ibcon#wrote, iclass 19, count 2 2006.257.15:07:48.46#ibcon#about to read 3, iclass 19, count 2 2006.257.15:07:48.49#ibcon#read 3, iclass 19, count 2 2006.257.15:07:48.50#ibcon#about to read 4, iclass 19, count 2 2006.257.15:07:48.50#ibcon#read 4, iclass 19, count 2 2006.257.15:07:48.50#ibcon#about to read 5, iclass 19, count 2 2006.257.15:07:48.50#ibcon#read 5, iclass 19, count 2 2006.257.15:07:48.50#ibcon#about to read 6, iclass 19, count 2 2006.257.15:07:48.50#ibcon#read 6, iclass 19, count 2 2006.257.15:07:48.50#ibcon#end of sib2, iclass 19, count 2 2006.257.15:07:48.50#ibcon#*after write, iclass 19, count 2 2006.257.15:07:48.50#ibcon#*before return 0, iclass 19, count 2 2006.257.15:07:48.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:48.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:48.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.15:07:48.50#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:48.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:48.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:48.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:48.62#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:07:48.62#ibcon#first serial, iclass 19, count 0 2006.257.15:07:48.62#ibcon#enter sib2, iclass 19, count 0 2006.257.15:07:48.62#ibcon#flushed, iclass 19, count 0 2006.257.15:07:48.62#ibcon#about to write, iclass 19, count 0 2006.257.15:07:48.62#ibcon#wrote, iclass 19, count 0 2006.257.15:07:48.62#ibcon#about to read 3, iclass 19, count 0 2006.257.15:07:48.64#ibcon#read 3, iclass 19, count 0 2006.257.15:07:48.64#ibcon#about to read 4, iclass 19, count 0 2006.257.15:07:48.64#ibcon#read 4, iclass 19, count 0 2006.257.15:07:48.64#ibcon#about to read 5, iclass 19, count 0 2006.257.15:07:48.64#ibcon#read 5, iclass 19, count 0 2006.257.15:07:48.64#ibcon#about to read 6, iclass 19, count 0 2006.257.15:07:48.64#ibcon#read 6, iclass 19, count 0 2006.257.15:07:48.64#ibcon#end of sib2, iclass 19, count 0 2006.257.15:07:48.64#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:07:48.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:07:48.64#ibcon#[25=USB\r\n] 2006.257.15:07:48.64#ibcon#*before write, iclass 19, count 0 2006.257.15:07:48.64#ibcon#enter sib2, iclass 19, count 0 2006.257.15:07:48.64#ibcon#flushed, iclass 19, count 0 2006.257.15:07:48.64#ibcon#about to write, iclass 19, count 0 2006.257.15:07:48.64#ibcon#wrote, iclass 19, count 0 2006.257.15:07:48.64#ibcon#about to read 3, iclass 19, count 0 2006.257.15:07:48.67#ibcon#read 3, iclass 19, count 0 2006.257.15:07:48.67#ibcon#about to read 4, iclass 19, count 0 2006.257.15:07:48.67#ibcon#read 4, iclass 19, count 0 2006.257.15:07:48.67#ibcon#about to read 5, iclass 19, count 0 2006.257.15:07:48.67#ibcon#read 5, iclass 19, count 0 2006.257.15:07:48.67#ibcon#about to read 6, iclass 19, count 0 2006.257.15:07:48.67#ibcon#read 6, iclass 19, count 0 2006.257.15:07:48.67#ibcon#end of sib2, iclass 19, count 0 2006.257.15:07:48.67#ibcon#*after write, iclass 19, count 0 2006.257.15:07:48.67#ibcon#*before return 0, iclass 19, count 0 2006.257.15:07:48.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:48.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:48.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:07:48.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:07:48.67$vck44/valo=5,734.99 2006.257.15:07:48.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.15:07:48.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.15:07:48.67#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:48.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:48.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:48.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:48.67#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:07:48.67#ibcon#first serial, iclass 21, count 0 2006.257.15:07:48.67#ibcon#enter sib2, iclass 21, count 0 2006.257.15:07:48.67#ibcon#flushed, iclass 21, count 0 2006.257.15:07:48.67#ibcon#about to write, iclass 21, count 0 2006.257.15:07:48.67#ibcon#wrote, iclass 21, count 0 2006.257.15:07:48.67#ibcon#about to read 3, iclass 21, count 0 2006.257.15:07:48.69#ibcon#read 3, iclass 21, count 0 2006.257.15:07:48.69#ibcon#about to read 4, iclass 21, count 0 2006.257.15:07:48.69#ibcon#read 4, iclass 21, count 0 2006.257.15:07:48.69#ibcon#about to read 5, iclass 21, count 0 2006.257.15:07:48.69#ibcon#read 5, iclass 21, count 0 2006.257.15:07:48.69#ibcon#about to read 6, iclass 21, count 0 2006.257.15:07:48.69#ibcon#read 6, iclass 21, count 0 2006.257.15:07:48.69#ibcon#end of sib2, iclass 21, count 0 2006.257.15:07:48.69#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:07:48.69#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:07:48.69#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:07:48.69#ibcon#*before write, iclass 21, count 0 2006.257.15:07:48.69#ibcon#enter sib2, iclass 21, count 0 2006.257.15:07:48.69#ibcon#flushed, iclass 21, count 0 2006.257.15:07:48.69#ibcon#about to write, iclass 21, count 0 2006.257.15:07:48.69#ibcon#wrote, iclass 21, count 0 2006.257.15:07:48.69#ibcon#about to read 3, iclass 21, count 0 2006.257.15:07:48.73#ibcon#read 3, iclass 21, count 0 2006.257.15:07:48.73#ibcon#about to read 4, iclass 21, count 0 2006.257.15:07:48.73#ibcon#read 4, iclass 21, count 0 2006.257.15:07:48.73#ibcon#about to read 5, iclass 21, count 0 2006.257.15:07:48.73#ibcon#read 5, iclass 21, count 0 2006.257.15:07:48.73#ibcon#about to read 6, iclass 21, count 0 2006.257.15:07:48.73#ibcon#read 6, iclass 21, count 0 2006.257.15:07:48.73#ibcon#end of sib2, iclass 21, count 0 2006.257.15:07:48.73#ibcon#*after write, iclass 21, count 0 2006.257.15:07:48.73#ibcon#*before return 0, iclass 21, count 0 2006.257.15:07:48.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:48.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:48.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:07:48.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:07:48.73$vck44/va=5,4 2006.257.15:07:48.73#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.15:07:48.73#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.15:07:48.73#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:48.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:48.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:48.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:48.79#ibcon#enter wrdev, iclass 23, count 2 2006.257.15:07:48.79#ibcon#first serial, iclass 23, count 2 2006.257.15:07:48.79#ibcon#enter sib2, iclass 23, count 2 2006.257.15:07:48.79#ibcon#flushed, iclass 23, count 2 2006.257.15:07:48.79#ibcon#about to write, iclass 23, count 2 2006.257.15:07:48.79#ibcon#wrote, iclass 23, count 2 2006.257.15:07:48.79#ibcon#about to read 3, iclass 23, count 2 2006.257.15:07:48.81#ibcon#read 3, iclass 23, count 2 2006.257.15:07:48.81#ibcon#about to read 4, iclass 23, count 2 2006.257.15:07:48.81#ibcon#read 4, iclass 23, count 2 2006.257.15:07:48.81#ibcon#about to read 5, iclass 23, count 2 2006.257.15:07:48.81#ibcon#read 5, iclass 23, count 2 2006.257.15:07:48.81#ibcon#about to read 6, iclass 23, count 2 2006.257.15:07:48.81#ibcon#read 6, iclass 23, count 2 2006.257.15:07:48.81#ibcon#end of sib2, iclass 23, count 2 2006.257.15:07:48.81#ibcon#*mode == 0, iclass 23, count 2 2006.257.15:07:48.81#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.15:07:48.81#ibcon#[25=AT05-04\r\n] 2006.257.15:07:48.81#ibcon#*before write, iclass 23, count 2 2006.257.15:07:48.81#ibcon#enter sib2, iclass 23, count 2 2006.257.15:07:48.81#ibcon#flushed, iclass 23, count 2 2006.257.15:07:48.81#ibcon#about to write, iclass 23, count 2 2006.257.15:07:48.81#ibcon#wrote, iclass 23, count 2 2006.257.15:07:48.81#ibcon#about to read 3, iclass 23, count 2 2006.257.15:07:48.84#ibcon#read 3, iclass 23, count 2 2006.257.15:07:48.84#ibcon#about to read 4, iclass 23, count 2 2006.257.15:07:48.84#ibcon#read 4, iclass 23, count 2 2006.257.15:07:48.84#ibcon#about to read 5, iclass 23, count 2 2006.257.15:07:48.84#ibcon#read 5, iclass 23, count 2 2006.257.15:07:48.84#ibcon#about to read 6, iclass 23, count 2 2006.257.15:07:48.84#ibcon#read 6, iclass 23, count 2 2006.257.15:07:48.84#ibcon#end of sib2, iclass 23, count 2 2006.257.15:07:48.84#ibcon#*after write, iclass 23, count 2 2006.257.15:07:48.84#ibcon#*before return 0, iclass 23, count 2 2006.257.15:07:48.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:48.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:48.84#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.15:07:48.84#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:48.84#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:48.96#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:48.96#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:48.96#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:07:48.96#ibcon#first serial, iclass 23, count 0 2006.257.15:07:48.96#ibcon#enter sib2, iclass 23, count 0 2006.257.15:07:48.96#ibcon#flushed, iclass 23, count 0 2006.257.15:07:48.96#ibcon#about to write, iclass 23, count 0 2006.257.15:07:48.96#ibcon#wrote, iclass 23, count 0 2006.257.15:07:48.96#ibcon#about to read 3, iclass 23, count 0 2006.257.15:07:48.98#ibcon#read 3, iclass 23, count 0 2006.257.15:07:48.98#ibcon#about to read 4, iclass 23, count 0 2006.257.15:07:48.98#ibcon#read 4, iclass 23, count 0 2006.257.15:07:48.98#ibcon#about to read 5, iclass 23, count 0 2006.257.15:07:48.98#ibcon#read 5, iclass 23, count 0 2006.257.15:07:48.98#ibcon#about to read 6, iclass 23, count 0 2006.257.15:07:48.98#ibcon#read 6, iclass 23, count 0 2006.257.15:07:48.98#ibcon#end of sib2, iclass 23, count 0 2006.257.15:07:48.98#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:07:48.98#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:07:48.98#ibcon#[25=USB\r\n] 2006.257.15:07:48.98#ibcon#*before write, iclass 23, count 0 2006.257.15:07:48.98#ibcon#enter sib2, iclass 23, count 0 2006.257.15:07:48.98#ibcon#flushed, iclass 23, count 0 2006.257.15:07:48.98#ibcon#about to write, iclass 23, count 0 2006.257.15:07:48.98#ibcon#wrote, iclass 23, count 0 2006.257.15:07:48.98#ibcon#about to read 3, iclass 23, count 0 2006.257.15:07:49.01#ibcon#read 3, iclass 23, count 0 2006.257.15:07:49.01#ibcon#about to read 4, iclass 23, count 0 2006.257.15:07:49.01#ibcon#read 4, iclass 23, count 0 2006.257.15:07:49.01#ibcon#about to read 5, iclass 23, count 0 2006.257.15:07:49.01#ibcon#read 5, iclass 23, count 0 2006.257.15:07:49.01#ibcon#about to read 6, iclass 23, count 0 2006.257.15:07:49.01#ibcon#read 6, iclass 23, count 0 2006.257.15:07:49.01#ibcon#end of sib2, iclass 23, count 0 2006.257.15:07:49.01#ibcon#*after write, iclass 23, count 0 2006.257.15:07:49.01#ibcon#*before return 0, iclass 23, count 0 2006.257.15:07:49.01#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:49.01#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:49.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:07:49.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:07:49.01$vck44/valo=6,814.99 2006.257.15:07:49.01#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.15:07:49.01#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.15:07:49.01#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:49.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:49.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:49.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:49.02#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:07:49.02#ibcon#first serial, iclass 25, count 0 2006.257.15:07:49.02#ibcon#enter sib2, iclass 25, count 0 2006.257.15:07:49.02#ibcon#flushed, iclass 25, count 0 2006.257.15:07:49.02#ibcon#about to write, iclass 25, count 0 2006.257.15:07:49.02#ibcon#wrote, iclass 25, count 0 2006.257.15:07:49.02#ibcon#about to read 3, iclass 25, count 0 2006.257.15:07:49.03#ibcon#read 3, iclass 25, count 0 2006.257.15:07:49.03#ibcon#about to read 4, iclass 25, count 0 2006.257.15:07:49.03#ibcon#read 4, iclass 25, count 0 2006.257.15:07:49.03#ibcon#about to read 5, iclass 25, count 0 2006.257.15:07:49.03#ibcon#read 5, iclass 25, count 0 2006.257.15:07:49.03#ibcon#about to read 6, iclass 25, count 0 2006.257.15:07:49.03#ibcon#read 6, iclass 25, count 0 2006.257.15:07:49.03#ibcon#end of sib2, iclass 25, count 0 2006.257.15:07:49.03#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:07:49.03#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:07:49.03#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:07:49.03#ibcon#*before write, iclass 25, count 0 2006.257.15:07:49.03#ibcon#enter sib2, iclass 25, count 0 2006.257.15:07:49.03#ibcon#flushed, iclass 25, count 0 2006.257.15:07:49.03#ibcon#about to write, iclass 25, count 0 2006.257.15:07:49.03#ibcon#wrote, iclass 25, count 0 2006.257.15:07:49.03#ibcon#about to read 3, iclass 25, count 0 2006.257.15:07:49.07#ibcon#read 3, iclass 25, count 0 2006.257.15:07:49.07#ibcon#about to read 4, iclass 25, count 0 2006.257.15:07:49.07#ibcon#read 4, iclass 25, count 0 2006.257.15:07:49.07#ibcon#about to read 5, iclass 25, count 0 2006.257.15:07:49.07#ibcon#read 5, iclass 25, count 0 2006.257.15:07:49.07#ibcon#about to read 6, iclass 25, count 0 2006.257.15:07:49.07#ibcon#read 6, iclass 25, count 0 2006.257.15:07:49.07#ibcon#end of sib2, iclass 25, count 0 2006.257.15:07:49.07#ibcon#*after write, iclass 25, count 0 2006.257.15:07:49.07#ibcon#*before return 0, iclass 25, count 0 2006.257.15:07:49.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:49.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:49.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:07:49.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:07:49.07$vck44/va=6,4 2006.257.15:07:49.07#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.15:07:49.07#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.15:07:49.07#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:49.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:49.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:49.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:49.13#ibcon#enter wrdev, iclass 27, count 2 2006.257.15:07:49.13#ibcon#first serial, iclass 27, count 2 2006.257.15:07:49.13#ibcon#enter sib2, iclass 27, count 2 2006.257.15:07:49.13#ibcon#flushed, iclass 27, count 2 2006.257.15:07:49.13#ibcon#about to write, iclass 27, count 2 2006.257.15:07:49.13#ibcon#wrote, iclass 27, count 2 2006.257.15:07:49.13#ibcon#about to read 3, iclass 27, count 2 2006.257.15:07:49.15#ibcon#read 3, iclass 27, count 2 2006.257.15:07:49.15#ibcon#about to read 4, iclass 27, count 2 2006.257.15:07:49.15#ibcon#read 4, iclass 27, count 2 2006.257.15:07:49.15#ibcon#about to read 5, iclass 27, count 2 2006.257.15:07:49.15#ibcon#read 5, iclass 27, count 2 2006.257.15:07:49.15#ibcon#about to read 6, iclass 27, count 2 2006.257.15:07:49.15#ibcon#read 6, iclass 27, count 2 2006.257.15:07:49.15#ibcon#end of sib2, iclass 27, count 2 2006.257.15:07:49.15#ibcon#*mode == 0, iclass 27, count 2 2006.257.15:07:49.15#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.15:07:49.15#ibcon#[25=AT06-04\r\n] 2006.257.15:07:49.15#ibcon#*before write, iclass 27, count 2 2006.257.15:07:49.15#ibcon#enter sib2, iclass 27, count 2 2006.257.15:07:49.15#ibcon#flushed, iclass 27, count 2 2006.257.15:07:49.15#ibcon#about to write, iclass 27, count 2 2006.257.15:07:49.15#ibcon#wrote, iclass 27, count 2 2006.257.15:07:49.15#ibcon#about to read 3, iclass 27, count 2 2006.257.15:07:49.18#ibcon#read 3, iclass 27, count 2 2006.257.15:07:49.18#ibcon#about to read 4, iclass 27, count 2 2006.257.15:07:49.18#ibcon#read 4, iclass 27, count 2 2006.257.15:07:49.18#ibcon#about to read 5, iclass 27, count 2 2006.257.15:07:49.18#ibcon#read 5, iclass 27, count 2 2006.257.15:07:49.18#ibcon#about to read 6, iclass 27, count 2 2006.257.15:07:49.18#ibcon#read 6, iclass 27, count 2 2006.257.15:07:49.18#ibcon#end of sib2, iclass 27, count 2 2006.257.15:07:49.18#ibcon#*after write, iclass 27, count 2 2006.257.15:07:49.18#ibcon#*before return 0, iclass 27, count 2 2006.257.15:07:49.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:49.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:49.18#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.15:07:49.18#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:49.18#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:49.30#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:49.30#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:49.30#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:07:49.30#ibcon#first serial, iclass 27, count 0 2006.257.15:07:49.30#ibcon#enter sib2, iclass 27, count 0 2006.257.15:07:49.30#ibcon#flushed, iclass 27, count 0 2006.257.15:07:49.30#ibcon#about to write, iclass 27, count 0 2006.257.15:07:49.30#ibcon#wrote, iclass 27, count 0 2006.257.15:07:49.30#ibcon#about to read 3, iclass 27, count 0 2006.257.15:07:49.32#ibcon#read 3, iclass 27, count 0 2006.257.15:07:49.32#ibcon#about to read 4, iclass 27, count 0 2006.257.15:07:49.32#ibcon#read 4, iclass 27, count 0 2006.257.15:07:49.32#ibcon#about to read 5, iclass 27, count 0 2006.257.15:07:49.32#ibcon#read 5, iclass 27, count 0 2006.257.15:07:49.32#ibcon#about to read 6, iclass 27, count 0 2006.257.15:07:49.32#ibcon#read 6, iclass 27, count 0 2006.257.15:07:49.32#ibcon#end of sib2, iclass 27, count 0 2006.257.15:07:49.32#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:07:49.32#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:07:49.32#ibcon#[25=USB\r\n] 2006.257.15:07:49.32#ibcon#*before write, iclass 27, count 0 2006.257.15:07:49.32#ibcon#enter sib2, iclass 27, count 0 2006.257.15:07:49.32#ibcon#flushed, iclass 27, count 0 2006.257.15:07:49.32#ibcon#about to write, iclass 27, count 0 2006.257.15:07:49.32#ibcon#wrote, iclass 27, count 0 2006.257.15:07:49.32#ibcon#about to read 3, iclass 27, count 0 2006.257.15:07:49.35#ibcon#read 3, iclass 27, count 0 2006.257.15:07:49.35#ibcon#about to read 4, iclass 27, count 0 2006.257.15:07:49.35#ibcon#read 4, iclass 27, count 0 2006.257.15:07:49.35#ibcon#about to read 5, iclass 27, count 0 2006.257.15:07:49.35#ibcon#read 5, iclass 27, count 0 2006.257.15:07:49.35#ibcon#about to read 6, iclass 27, count 0 2006.257.15:07:49.35#ibcon#read 6, iclass 27, count 0 2006.257.15:07:49.35#ibcon#end of sib2, iclass 27, count 0 2006.257.15:07:49.35#ibcon#*after write, iclass 27, count 0 2006.257.15:07:49.35#ibcon#*before return 0, iclass 27, count 0 2006.257.15:07:49.35#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:49.35#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:49.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:07:49.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:07:49.35$vck44/valo=7,864.99 2006.257.15:07:49.35#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.15:07:49.35#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.15:07:49.35#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:49.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:49.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:49.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:49.35#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:07:49.35#ibcon#first serial, iclass 29, count 0 2006.257.15:07:49.35#ibcon#enter sib2, iclass 29, count 0 2006.257.15:07:49.35#ibcon#flushed, iclass 29, count 0 2006.257.15:07:49.35#ibcon#about to write, iclass 29, count 0 2006.257.15:07:49.35#ibcon#wrote, iclass 29, count 0 2006.257.15:07:49.35#ibcon#about to read 3, iclass 29, count 0 2006.257.15:07:49.37#ibcon#read 3, iclass 29, count 0 2006.257.15:07:49.37#ibcon#about to read 4, iclass 29, count 0 2006.257.15:07:49.37#ibcon#read 4, iclass 29, count 0 2006.257.15:07:49.37#ibcon#about to read 5, iclass 29, count 0 2006.257.15:07:49.37#ibcon#read 5, iclass 29, count 0 2006.257.15:07:49.37#ibcon#about to read 6, iclass 29, count 0 2006.257.15:07:49.37#ibcon#read 6, iclass 29, count 0 2006.257.15:07:49.37#ibcon#end of sib2, iclass 29, count 0 2006.257.15:07:49.37#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:07:49.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:07:49.37#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:07:49.37#ibcon#*before write, iclass 29, count 0 2006.257.15:07:49.37#ibcon#enter sib2, iclass 29, count 0 2006.257.15:07:49.37#ibcon#flushed, iclass 29, count 0 2006.257.15:07:49.37#ibcon#about to write, iclass 29, count 0 2006.257.15:07:49.37#ibcon#wrote, iclass 29, count 0 2006.257.15:07:49.37#ibcon#about to read 3, iclass 29, count 0 2006.257.15:07:49.41#ibcon#read 3, iclass 29, count 0 2006.257.15:07:49.41#ibcon#about to read 4, iclass 29, count 0 2006.257.15:07:49.41#ibcon#read 4, iclass 29, count 0 2006.257.15:07:49.41#ibcon#about to read 5, iclass 29, count 0 2006.257.15:07:49.41#ibcon#read 5, iclass 29, count 0 2006.257.15:07:49.41#ibcon#about to read 6, iclass 29, count 0 2006.257.15:07:49.41#ibcon#read 6, iclass 29, count 0 2006.257.15:07:49.41#ibcon#end of sib2, iclass 29, count 0 2006.257.15:07:49.41#ibcon#*after write, iclass 29, count 0 2006.257.15:07:49.41#ibcon#*before return 0, iclass 29, count 0 2006.257.15:07:49.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:49.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:49.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:07:49.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:07:49.41$vck44/va=7,4 2006.257.15:07:49.41#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.15:07:49.41#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.15:07:49.41#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:49.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:49.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:49.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:49.47#ibcon#enter wrdev, iclass 31, count 2 2006.257.15:07:49.47#ibcon#first serial, iclass 31, count 2 2006.257.15:07:49.47#ibcon#enter sib2, iclass 31, count 2 2006.257.15:07:49.47#ibcon#flushed, iclass 31, count 2 2006.257.15:07:49.47#ibcon#about to write, iclass 31, count 2 2006.257.15:07:49.47#ibcon#wrote, iclass 31, count 2 2006.257.15:07:49.47#ibcon#about to read 3, iclass 31, count 2 2006.257.15:07:49.49#ibcon#read 3, iclass 31, count 2 2006.257.15:07:49.49#ibcon#about to read 4, iclass 31, count 2 2006.257.15:07:49.49#ibcon#read 4, iclass 31, count 2 2006.257.15:07:49.49#ibcon#about to read 5, iclass 31, count 2 2006.257.15:07:49.49#ibcon#read 5, iclass 31, count 2 2006.257.15:07:49.49#ibcon#about to read 6, iclass 31, count 2 2006.257.15:07:49.49#ibcon#read 6, iclass 31, count 2 2006.257.15:07:49.49#ibcon#end of sib2, iclass 31, count 2 2006.257.15:07:49.49#ibcon#*mode == 0, iclass 31, count 2 2006.257.15:07:49.49#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.15:07:49.49#ibcon#[25=AT07-04\r\n] 2006.257.15:07:49.49#ibcon#*before write, iclass 31, count 2 2006.257.15:07:49.49#ibcon#enter sib2, iclass 31, count 2 2006.257.15:07:49.49#ibcon#flushed, iclass 31, count 2 2006.257.15:07:49.49#ibcon#about to write, iclass 31, count 2 2006.257.15:07:49.49#ibcon#wrote, iclass 31, count 2 2006.257.15:07:49.49#ibcon#about to read 3, iclass 31, count 2 2006.257.15:07:49.52#ibcon#read 3, iclass 31, count 2 2006.257.15:07:49.52#ibcon#about to read 4, iclass 31, count 2 2006.257.15:07:49.52#ibcon#read 4, iclass 31, count 2 2006.257.15:07:49.52#ibcon#about to read 5, iclass 31, count 2 2006.257.15:07:49.52#ibcon#read 5, iclass 31, count 2 2006.257.15:07:49.52#ibcon#about to read 6, iclass 31, count 2 2006.257.15:07:49.52#ibcon#read 6, iclass 31, count 2 2006.257.15:07:49.52#ibcon#end of sib2, iclass 31, count 2 2006.257.15:07:49.52#ibcon#*after write, iclass 31, count 2 2006.257.15:07:49.52#ibcon#*before return 0, iclass 31, count 2 2006.257.15:07:49.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:49.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:49.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.15:07:49.52#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:49.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:49.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:49.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:49.64#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:07:49.64#ibcon#first serial, iclass 31, count 0 2006.257.15:07:49.64#ibcon#enter sib2, iclass 31, count 0 2006.257.15:07:49.64#ibcon#flushed, iclass 31, count 0 2006.257.15:07:49.64#ibcon#about to write, iclass 31, count 0 2006.257.15:07:49.64#ibcon#wrote, iclass 31, count 0 2006.257.15:07:49.64#ibcon#about to read 3, iclass 31, count 0 2006.257.15:07:49.66#ibcon#read 3, iclass 31, count 0 2006.257.15:07:49.66#ibcon#about to read 4, iclass 31, count 0 2006.257.15:07:49.66#ibcon#read 4, iclass 31, count 0 2006.257.15:07:49.66#ibcon#about to read 5, iclass 31, count 0 2006.257.15:07:49.66#ibcon#read 5, iclass 31, count 0 2006.257.15:07:49.66#ibcon#about to read 6, iclass 31, count 0 2006.257.15:07:49.66#ibcon#read 6, iclass 31, count 0 2006.257.15:07:49.66#ibcon#end of sib2, iclass 31, count 0 2006.257.15:07:49.66#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:07:49.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:07:49.66#ibcon#[25=USB\r\n] 2006.257.15:07:49.66#ibcon#*before write, iclass 31, count 0 2006.257.15:07:49.66#ibcon#enter sib2, iclass 31, count 0 2006.257.15:07:49.66#ibcon#flushed, iclass 31, count 0 2006.257.15:07:49.66#ibcon#about to write, iclass 31, count 0 2006.257.15:07:49.66#ibcon#wrote, iclass 31, count 0 2006.257.15:07:49.66#ibcon#about to read 3, iclass 31, count 0 2006.257.15:07:49.69#ibcon#read 3, iclass 31, count 0 2006.257.15:07:49.69#ibcon#about to read 4, iclass 31, count 0 2006.257.15:07:49.69#ibcon#read 4, iclass 31, count 0 2006.257.15:07:49.69#ibcon#about to read 5, iclass 31, count 0 2006.257.15:07:49.69#ibcon#read 5, iclass 31, count 0 2006.257.15:07:49.69#ibcon#about to read 6, iclass 31, count 0 2006.257.15:07:49.69#ibcon#read 6, iclass 31, count 0 2006.257.15:07:49.69#ibcon#end of sib2, iclass 31, count 0 2006.257.15:07:49.69#ibcon#*after write, iclass 31, count 0 2006.257.15:07:49.69#ibcon#*before return 0, iclass 31, count 0 2006.257.15:07:49.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:49.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:49.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:07:49.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:07:49.69$vck44/valo=8,884.99 2006.257.15:07:49.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.15:07:49.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.15:07:49.69#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:49.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:49.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:49.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:49.69#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:07:49.69#ibcon#first serial, iclass 33, count 0 2006.257.15:07:49.69#ibcon#enter sib2, iclass 33, count 0 2006.257.15:07:49.69#ibcon#flushed, iclass 33, count 0 2006.257.15:07:49.69#ibcon#about to write, iclass 33, count 0 2006.257.15:07:49.69#ibcon#wrote, iclass 33, count 0 2006.257.15:07:49.69#ibcon#about to read 3, iclass 33, count 0 2006.257.15:07:49.71#ibcon#read 3, iclass 33, count 0 2006.257.15:07:49.71#ibcon#about to read 4, iclass 33, count 0 2006.257.15:07:49.71#ibcon#read 4, iclass 33, count 0 2006.257.15:07:49.71#ibcon#about to read 5, iclass 33, count 0 2006.257.15:07:49.71#ibcon#read 5, iclass 33, count 0 2006.257.15:07:49.71#ibcon#about to read 6, iclass 33, count 0 2006.257.15:07:49.71#ibcon#read 6, iclass 33, count 0 2006.257.15:07:49.71#ibcon#end of sib2, iclass 33, count 0 2006.257.15:07:49.71#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:07:49.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:07:49.71#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:07:49.71#ibcon#*before write, iclass 33, count 0 2006.257.15:07:49.71#ibcon#enter sib2, iclass 33, count 0 2006.257.15:07:49.71#ibcon#flushed, iclass 33, count 0 2006.257.15:07:49.71#ibcon#about to write, iclass 33, count 0 2006.257.15:07:49.71#ibcon#wrote, iclass 33, count 0 2006.257.15:07:49.71#ibcon#about to read 3, iclass 33, count 0 2006.257.15:07:49.75#ibcon#read 3, iclass 33, count 0 2006.257.15:07:49.75#ibcon#about to read 4, iclass 33, count 0 2006.257.15:07:49.75#ibcon#read 4, iclass 33, count 0 2006.257.15:07:49.75#ibcon#about to read 5, iclass 33, count 0 2006.257.15:07:49.75#ibcon#read 5, iclass 33, count 0 2006.257.15:07:49.75#ibcon#about to read 6, iclass 33, count 0 2006.257.15:07:49.75#ibcon#read 6, iclass 33, count 0 2006.257.15:07:49.75#ibcon#end of sib2, iclass 33, count 0 2006.257.15:07:49.75#ibcon#*after write, iclass 33, count 0 2006.257.15:07:49.75#ibcon#*before return 0, iclass 33, count 0 2006.257.15:07:49.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:49.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:49.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:07:49.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:07:49.75$vck44/va=8,4 2006.257.15:07:49.75#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.15:07:49.75#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.15:07:49.75#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:49.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:07:49.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:07:49.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:07:49.81#ibcon#enter wrdev, iclass 35, count 2 2006.257.15:07:49.81#ibcon#first serial, iclass 35, count 2 2006.257.15:07:49.81#ibcon#enter sib2, iclass 35, count 2 2006.257.15:07:49.81#ibcon#flushed, iclass 35, count 2 2006.257.15:07:49.81#ibcon#about to write, iclass 35, count 2 2006.257.15:07:49.81#ibcon#wrote, iclass 35, count 2 2006.257.15:07:49.81#ibcon#about to read 3, iclass 35, count 2 2006.257.15:07:49.83#ibcon#read 3, iclass 35, count 2 2006.257.15:07:49.83#ibcon#about to read 4, iclass 35, count 2 2006.257.15:07:49.83#ibcon#read 4, iclass 35, count 2 2006.257.15:07:49.83#ibcon#about to read 5, iclass 35, count 2 2006.257.15:07:49.83#ibcon#read 5, iclass 35, count 2 2006.257.15:07:49.83#ibcon#about to read 6, iclass 35, count 2 2006.257.15:07:49.83#ibcon#read 6, iclass 35, count 2 2006.257.15:07:49.83#ibcon#end of sib2, iclass 35, count 2 2006.257.15:07:49.83#ibcon#*mode == 0, iclass 35, count 2 2006.257.15:07:49.83#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.15:07:49.83#ibcon#[25=AT08-04\r\n] 2006.257.15:07:49.83#ibcon#*before write, iclass 35, count 2 2006.257.15:07:49.83#ibcon#enter sib2, iclass 35, count 2 2006.257.15:07:49.83#ibcon#flushed, iclass 35, count 2 2006.257.15:07:49.83#ibcon#about to write, iclass 35, count 2 2006.257.15:07:49.83#ibcon#wrote, iclass 35, count 2 2006.257.15:07:49.83#ibcon#about to read 3, iclass 35, count 2 2006.257.15:07:49.86#ibcon#read 3, iclass 35, count 2 2006.257.15:07:49.86#ibcon#about to read 4, iclass 35, count 2 2006.257.15:07:49.86#ibcon#read 4, iclass 35, count 2 2006.257.15:07:49.86#ibcon#about to read 5, iclass 35, count 2 2006.257.15:07:49.86#ibcon#read 5, iclass 35, count 2 2006.257.15:07:49.86#ibcon#about to read 6, iclass 35, count 2 2006.257.15:07:49.86#ibcon#read 6, iclass 35, count 2 2006.257.15:07:49.86#ibcon#end of sib2, iclass 35, count 2 2006.257.15:07:49.86#ibcon#*after write, iclass 35, count 2 2006.257.15:07:49.86#ibcon#*before return 0, iclass 35, count 2 2006.257.15:07:49.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:07:49.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:07:49.86#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.15:07:49.86#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:49.86#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:07:49.98#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:07:49.98#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:07:49.98#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:07:49.98#ibcon#first serial, iclass 35, count 0 2006.257.15:07:49.98#ibcon#enter sib2, iclass 35, count 0 2006.257.15:07:49.98#ibcon#flushed, iclass 35, count 0 2006.257.15:07:49.98#ibcon#about to write, iclass 35, count 0 2006.257.15:07:49.98#ibcon#wrote, iclass 35, count 0 2006.257.15:07:49.98#ibcon#about to read 3, iclass 35, count 0 2006.257.15:07:50.00#ibcon#read 3, iclass 35, count 0 2006.257.15:07:50.00#ibcon#about to read 4, iclass 35, count 0 2006.257.15:07:50.00#ibcon#read 4, iclass 35, count 0 2006.257.15:07:50.00#ibcon#about to read 5, iclass 35, count 0 2006.257.15:07:50.00#ibcon#read 5, iclass 35, count 0 2006.257.15:07:50.00#ibcon#about to read 6, iclass 35, count 0 2006.257.15:07:50.00#ibcon#read 6, iclass 35, count 0 2006.257.15:07:50.00#ibcon#end of sib2, iclass 35, count 0 2006.257.15:07:50.00#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:07:50.00#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:07:50.00#ibcon#[25=USB\r\n] 2006.257.15:07:50.00#ibcon#*before write, iclass 35, count 0 2006.257.15:07:50.00#ibcon#enter sib2, iclass 35, count 0 2006.257.15:07:50.00#ibcon#flushed, iclass 35, count 0 2006.257.15:07:50.00#ibcon#about to write, iclass 35, count 0 2006.257.15:07:50.00#ibcon#wrote, iclass 35, count 0 2006.257.15:07:50.00#ibcon#about to read 3, iclass 35, count 0 2006.257.15:07:50.03#ibcon#read 3, iclass 35, count 0 2006.257.15:07:50.03#ibcon#about to read 4, iclass 35, count 0 2006.257.15:07:50.03#ibcon#read 4, iclass 35, count 0 2006.257.15:07:50.03#ibcon#about to read 5, iclass 35, count 0 2006.257.15:07:50.03#ibcon#read 5, iclass 35, count 0 2006.257.15:07:50.03#ibcon#about to read 6, iclass 35, count 0 2006.257.15:07:50.03#ibcon#read 6, iclass 35, count 0 2006.257.15:07:50.03#ibcon#end of sib2, iclass 35, count 0 2006.257.15:07:50.03#ibcon#*after write, iclass 35, count 0 2006.257.15:07:50.03#ibcon#*before return 0, iclass 35, count 0 2006.257.15:07:50.03#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:07:50.03#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:07:50.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:07:50.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:07:50.03$vck44/vblo=1,629.99 2006.257.15:07:50.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.15:07:50.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.15:07:50.03#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:50.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:50.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:50.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:50.03#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:07:50.03#ibcon#first serial, iclass 37, count 0 2006.257.15:07:50.03#ibcon#enter sib2, iclass 37, count 0 2006.257.15:07:50.03#ibcon#flushed, iclass 37, count 0 2006.257.15:07:50.03#ibcon#about to write, iclass 37, count 0 2006.257.15:07:50.03#ibcon#wrote, iclass 37, count 0 2006.257.15:07:50.03#ibcon#about to read 3, iclass 37, count 0 2006.257.15:07:50.05#ibcon#read 3, iclass 37, count 0 2006.257.15:07:50.05#ibcon#about to read 4, iclass 37, count 0 2006.257.15:07:50.05#ibcon#read 4, iclass 37, count 0 2006.257.15:07:50.05#ibcon#about to read 5, iclass 37, count 0 2006.257.15:07:50.05#ibcon#read 5, iclass 37, count 0 2006.257.15:07:50.05#ibcon#about to read 6, iclass 37, count 0 2006.257.15:07:50.05#ibcon#read 6, iclass 37, count 0 2006.257.15:07:50.05#ibcon#end of sib2, iclass 37, count 0 2006.257.15:07:50.05#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:07:50.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:07:50.05#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:07:50.05#ibcon#*before write, iclass 37, count 0 2006.257.15:07:50.05#ibcon#enter sib2, iclass 37, count 0 2006.257.15:07:50.05#ibcon#flushed, iclass 37, count 0 2006.257.15:07:50.05#ibcon#about to write, iclass 37, count 0 2006.257.15:07:50.05#ibcon#wrote, iclass 37, count 0 2006.257.15:07:50.05#ibcon#about to read 3, iclass 37, count 0 2006.257.15:07:50.09#ibcon#read 3, iclass 37, count 0 2006.257.15:07:50.09#ibcon#about to read 4, iclass 37, count 0 2006.257.15:07:50.09#ibcon#read 4, iclass 37, count 0 2006.257.15:07:50.09#ibcon#about to read 5, iclass 37, count 0 2006.257.15:07:50.09#ibcon#read 5, iclass 37, count 0 2006.257.15:07:50.09#ibcon#about to read 6, iclass 37, count 0 2006.257.15:07:50.09#ibcon#read 6, iclass 37, count 0 2006.257.15:07:50.09#ibcon#end of sib2, iclass 37, count 0 2006.257.15:07:50.09#ibcon#*after write, iclass 37, count 0 2006.257.15:07:50.09#ibcon#*before return 0, iclass 37, count 0 2006.257.15:07:50.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:50.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:07:50.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:07:50.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:07:50.09$vck44/vb=1,4 2006.257.15:07:50.09#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.15:07:50.09#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.15:07:50.09#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:50.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:50.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:50.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:50.09#ibcon#enter wrdev, iclass 39, count 2 2006.257.15:07:50.09#ibcon#first serial, iclass 39, count 2 2006.257.15:07:50.09#ibcon#enter sib2, iclass 39, count 2 2006.257.15:07:50.09#ibcon#flushed, iclass 39, count 2 2006.257.15:07:50.09#ibcon#about to write, iclass 39, count 2 2006.257.15:07:50.09#ibcon#wrote, iclass 39, count 2 2006.257.15:07:50.09#ibcon#about to read 3, iclass 39, count 2 2006.257.15:07:50.11#ibcon#read 3, iclass 39, count 2 2006.257.15:07:50.11#ibcon#about to read 4, iclass 39, count 2 2006.257.15:07:50.11#ibcon#read 4, iclass 39, count 2 2006.257.15:07:50.11#ibcon#about to read 5, iclass 39, count 2 2006.257.15:07:50.11#ibcon#read 5, iclass 39, count 2 2006.257.15:07:50.11#ibcon#about to read 6, iclass 39, count 2 2006.257.15:07:50.11#ibcon#read 6, iclass 39, count 2 2006.257.15:07:50.11#ibcon#end of sib2, iclass 39, count 2 2006.257.15:07:50.11#ibcon#*mode == 0, iclass 39, count 2 2006.257.15:07:50.11#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.15:07:50.11#ibcon#[27=AT01-04\r\n] 2006.257.15:07:50.11#ibcon#*before write, iclass 39, count 2 2006.257.15:07:50.11#ibcon#enter sib2, iclass 39, count 2 2006.257.15:07:50.11#ibcon#flushed, iclass 39, count 2 2006.257.15:07:50.11#ibcon#about to write, iclass 39, count 2 2006.257.15:07:50.11#ibcon#wrote, iclass 39, count 2 2006.257.15:07:50.11#ibcon#about to read 3, iclass 39, count 2 2006.257.15:07:50.14#ibcon#read 3, iclass 39, count 2 2006.257.15:07:50.14#ibcon#about to read 4, iclass 39, count 2 2006.257.15:07:50.14#ibcon#read 4, iclass 39, count 2 2006.257.15:07:50.14#ibcon#about to read 5, iclass 39, count 2 2006.257.15:07:50.14#ibcon#read 5, iclass 39, count 2 2006.257.15:07:50.14#ibcon#about to read 6, iclass 39, count 2 2006.257.15:07:50.14#ibcon#read 6, iclass 39, count 2 2006.257.15:07:50.14#ibcon#end of sib2, iclass 39, count 2 2006.257.15:07:50.14#ibcon#*after write, iclass 39, count 2 2006.257.15:07:50.14#ibcon#*before return 0, iclass 39, count 2 2006.257.15:07:50.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:50.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:07:50.14#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.15:07:50.14#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:50.14#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:50.26#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:50.26#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:50.26#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:07:50.26#ibcon#first serial, iclass 39, count 0 2006.257.15:07:50.26#ibcon#enter sib2, iclass 39, count 0 2006.257.15:07:50.26#ibcon#flushed, iclass 39, count 0 2006.257.15:07:50.26#ibcon#about to write, iclass 39, count 0 2006.257.15:07:50.26#ibcon#wrote, iclass 39, count 0 2006.257.15:07:50.26#ibcon#about to read 3, iclass 39, count 0 2006.257.15:07:50.28#ibcon#read 3, iclass 39, count 0 2006.257.15:07:50.28#ibcon#about to read 4, iclass 39, count 0 2006.257.15:07:50.28#ibcon#read 4, iclass 39, count 0 2006.257.15:07:50.28#ibcon#about to read 5, iclass 39, count 0 2006.257.15:07:50.28#ibcon#read 5, iclass 39, count 0 2006.257.15:07:50.28#ibcon#about to read 6, iclass 39, count 0 2006.257.15:07:50.28#ibcon#read 6, iclass 39, count 0 2006.257.15:07:50.28#ibcon#end of sib2, iclass 39, count 0 2006.257.15:07:50.28#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:07:50.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:07:50.28#ibcon#[27=USB\r\n] 2006.257.15:07:50.28#ibcon#*before write, iclass 39, count 0 2006.257.15:07:50.28#ibcon#enter sib2, iclass 39, count 0 2006.257.15:07:50.28#ibcon#flushed, iclass 39, count 0 2006.257.15:07:50.28#ibcon#about to write, iclass 39, count 0 2006.257.15:07:50.28#ibcon#wrote, iclass 39, count 0 2006.257.15:07:50.28#ibcon#about to read 3, iclass 39, count 0 2006.257.15:07:50.31#ibcon#read 3, iclass 39, count 0 2006.257.15:07:50.31#ibcon#about to read 4, iclass 39, count 0 2006.257.15:07:50.31#ibcon#read 4, iclass 39, count 0 2006.257.15:07:50.31#ibcon#about to read 5, iclass 39, count 0 2006.257.15:07:50.31#ibcon#read 5, iclass 39, count 0 2006.257.15:07:50.31#ibcon#about to read 6, iclass 39, count 0 2006.257.15:07:50.31#ibcon#read 6, iclass 39, count 0 2006.257.15:07:50.31#ibcon#end of sib2, iclass 39, count 0 2006.257.15:07:50.31#ibcon#*after write, iclass 39, count 0 2006.257.15:07:50.31#ibcon#*before return 0, iclass 39, count 0 2006.257.15:07:50.31#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:50.31#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:07:50.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:07:50.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:07:50.31$vck44/vblo=2,634.99 2006.257.15:07:50.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.15:07:50.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.15:07:50.31#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:50.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:50.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:50.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:50.31#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:07:50.31#ibcon#first serial, iclass 3, count 0 2006.257.15:07:50.31#ibcon#enter sib2, iclass 3, count 0 2006.257.15:07:50.31#ibcon#flushed, iclass 3, count 0 2006.257.15:07:50.31#ibcon#about to write, iclass 3, count 0 2006.257.15:07:50.31#ibcon#wrote, iclass 3, count 0 2006.257.15:07:50.31#ibcon#about to read 3, iclass 3, count 0 2006.257.15:07:50.33#ibcon#read 3, iclass 3, count 0 2006.257.15:07:50.33#ibcon#about to read 4, iclass 3, count 0 2006.257.15:07:50.33#ibcon#read 4, iclass 3, count 0 2006.257.15:07:50.33#ibcon#about to read 5, iclass 3, count 0 2006.257.15:07:50.33#ibcon#read 5, iclass 3, count 0 2006.257.15:07:50.33#ibcon#about to read 6, iclass 3, count 0 2006.257.15:07:50.33#ibcon#read 6, iclass 3, count 0 2006.257.15:07:50.33#ibcon#end of sib2, iclass 3, count 0 2006.257.15:07:50.33#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:07:50.33#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:07:50.33#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:07:50.33#ibcon#*before write, iclass 3, count 0 2006.257.15:07:50.33#ibcon#enter sib2, iclass 3, count 0 2006.257.15:07:50.33#ibcon#flushed, iclass 3, count 0 2006.257.15:07:50.33#ibcon#about to write, iclass 3, count 0 2006.257.15:07:50.33#ibcon#wrote, iclass 3, count 0 2006.257.15:07:50.33#ibcon#about to read 3, iclass 3, count 0 2006.257.15:07:50.37#ibcon#read 3, iclass 3, count 0 2006.257.15:07:50.37#ibcon#about to read 4, iclass 3, count 0 2006.257.15:07:50.37#ibcon#read 4, iclass 3, count 0 2006.257.15:07:50.37#ibcon#about to read 5, iclass 3, count 0 2006.257.15:07:50.37#ibcon#read 5, iclass 3, count 0 2006.257.15:07:50.37#ibcon#about to read 6, iclass 3, count 0 2006.257.15:07:50.37#ibcon#read 6, iclass 3, count 0 2006.257.15:07:50.37#ibcon#end of sib2, iclass 3, count 0 2006.257.15:07:50.37#ibcon#*after write, iclass 3, count 0 2006.257.15:07:50.37#ibcon#*before return 0, iclass 3, count 0 2006.257.15:07:50.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:50.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:07:50.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:07:50.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:07:50.37$vck44/vb=2,5 2006.257.15:07:50.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.15:07:50.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.15:07:50.37#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:50.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:50.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:50.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:50.43#ibcon#enter wrdev, iclass 5, count 2 2006.257.15:07:50.43#ibcon#first serial, iclass 5, count 2 2006.257.15:07:50.43#ibcon#enter sib2, iclass 5, count 2 2006.257.15:07:50.43#ibcon#flushed, iclass 5, count 2 2006.257.15:07:50.43#ibcon#about to write, iclass 5, count 2 2006.257.15:07:50.43#ibcon#wrote, iclass 5, count 2 2006.257.15:07:50.43#ibcon#about to read 3, iclass 5, count 2 2006.257.15:07:50.45#ibcon#read 3, iclass 5, count 2 2006.257.15:07:50.45#ibcon#about to read 4, iclass 5, count 2 2006.257.15:07:50.45#ibcon#read 4, iclass 5, count 2 2006.257.15:07:50.45#ibcon#about to read 5, iclass 5, count 2 2006.257.15:07:50.45#ibcon#read 5, iclass 5, count 2 2006.257.15:07:50.45#ibcon#about to read 6, iclass 5, count 2 2006.257.15:07:50.45#ibcon#read 6, iclass 5, count 2 2006.257.15:07:50.45#ibcon#end of sib2, iclass 5, count 2 2006.257.15:07:50.45#ibcon#*mode == 0, iclass 5, count 2 2006.257.15:07:50.45#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.15:07:50.45#ibcon#[27=AT02-05\r\n] 2006.257.15:07:50.45#ibcon#*before write, iclass 5, count 2 2006.257.15:07:50.45#ibcon#enter sib2, iclass 5, count 2 2006.257.15:07:50.45#ibcon#flushed, iclass 5, count 2 2006.257.15:07:50.45#ibcon#about to write, iclass 5, count 2 2006.257.15:07:50.45#ibcon#wrote, iclass 5, count 2 2006.257.15:07:50.45#ibcon#about to read 3, iclass 5, count 2 2006.257.15:07:50.48#ibcon#read 3, iclass 5, count 2 2006.257.15:07:50.48#ibcon#about to read 4, iclass 5, count 2 2006.257.15:07:50.48#ibcon#read 4, iclass 5, count 2 2006.257.15:07:50.48#ibcon#about to read 5, iclass 5, count 2 2006.257.15:07:50.48#ibcon#read 5, iclass 5, count 2 2006.257.15:07:50.48#ibcon#about to read 6, iclass 5, count 2 2006.257.15:07:50.48#ibcon#read 6, iclass 5, count 2 2006.257.15:07:50.48#ibcon#end of sib2, iclass 5, count 2 2006.257.15:07:50.48#ibcon#*after write, iclass 5, count 2 2006.257.15:07:50.48#ibcon#*before return 0, iclass 5, count 2 2006.257.15:07:50.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:50.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:07:50.48#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.15:07:50.48#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:50.48#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:50.60#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:50.60#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:50.60#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:07:50.60#ibcon#first serial, iclass 5, count 0 2006.257.15:07:50.60#ibcon#enter sib2, iclass 5, count 0 2006.257.15:07:50.60#ibcon#flushed, iclass 5, count 0 2006.257.15:07:50.60#ibcon#about to write, iclass 5, count 0 2006.257.15:07:50.60#ibcon#wrote, iclass 5, count 0 2006.257.15:07:50.60#ibcon#about to read 3, iclass 5, count 0 2006.257.15:07:50.62#ibcon#read 3, iclass 5, count 0 2006.257.15:07:50.62#ibcon#about to read 4, iclass 5, count 0 2006.257.15:07:50.62#ibcon#read 4, iclass 5, count 0 2006.257.15:07:50.62#ibcon#about to read 5, iclass 5, count 0 2006.257.15:07:50.62#ibcon#read 5, iclass 5, count 0 2006.257.15:07:50.62#ibcon#about to read 6, iclass 5, count 0 2006.257.15:07:50.62#ibcon#read 6, iclass 5, count 0 2006.257.15:07:50.62#ibcon#end of sib2, iclass 5, count 0 2006.257.15:07:50.62#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:07:50.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:07:50.62#ibcon#[27=USB\r\n] 2006.257.15:07:50.62#ibcon#*before write, iclass 5, count 0 2006.257.15:07:50.62#ibcon#enter sib2, iclass 5, count 0 2006.257.15:07:50.62#ibcon#flushed, iclass 5, count 0 2006.257.15:07:50.62#ibcon#about to write, iclass 5, count 0 2006.257.15:07:50.62#ibcon#wrote, iclass 5, count 0 2006.257.15:07:50.62#ibcon#about to read 3, iclass 5, count 0 2006.257.15:07:50.65#ibcon#read 3, iclass 5, count 0 2006.257.15:07:50.65#ibcon#about to read 4, iclass 5, count 0 2006.257.15:07:50.65#ibcon#read 4, iclass 5, count 0 2006.257.15:07:50.65#ibcon#about to read 5, iclass 5, count 0 2006.257.15:07:50.65#ibcon#read 5, iclass 5, count 0 2006.257.15:07:50.65#ibcon#about to read 6, iclass 5, count 0 2006.257.15:07:50.65#ibcon#read 6, iclass 5, count 0 2006.257.15:07:50.65#ibcon#end of sib2, iclass 5, count 0 2006.257.15:07:50.65#ibcon#*after write, iclass 5, count 0 2006.257.15:07:50.65#ibcon#*before return 0, iclass 5, count 0 2006.257.15:07:50.65#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:50.65#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:07:50.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:07:50.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:07:50.65$vck44/vblo=3,649.99 2006.257.15:07:50.65#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.15:07:50.65#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.15:07:50.65#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:50.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:50.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:50.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:50.65#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:07:50.66#ibcon#first serial, iclass 7, count 0 2006.257.15:07:50.66#ibcon#enter sib2, iclass 7, count 0 2006.257.15:07:50.66#ibcon#flushed, iclass 7, count 0 2006.257.15:07:50.66#ibcon#about to write, iclass 7, count 0 2006.257.15:07:50.66#ibcon#wrote, iclass 7, count 0 2006.257.15:07:50.66#ibcon#about to read 3, iclass 7, count 0 2006.257.15:07:50.67#ibcon#read 3, iclass 7, count 0 2006.257.15:07:50.67#ibcon#about to read 4, iclass 7, count 0 2006.257.15:07:50.67#ibcon#read 4, iclass 7, count 0 2006.257.15:07:50.67#ibcon#about to read 5, iclass 7, count 0 2006.257.15:07:50.67#ibcon#read 5, iclass 7, count 0 2006.257.15:07:50.67#ibcon#about to read 6, iclass 7, count 0 2006.257.15:07:50.67#ibcon#read 6, iclass 7, count 0 2006.257.15:07:50.67#ibcon#end of sib2, iclass 7, count 0 2006.257.15:07:50.67#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:07:50.67#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:07:50.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:07:50.67#ibcon#*before write, iclass 7, count 0 2006.257.15:07:50.67#ibcon#enter sib2, iclass 7, count 0 2006.257.15:07:50.67#ibcon#flushed, iclass 7, count 0 2006.257.15:07:50.67#ibcon#about to write, iclass 7, count 0 2006.257.15:07:50.67#ibcon#wrote, iclass 7, count 0 2006.257.15:07:50.67#ibcon#about to read 3, iclass 7, count 0 2006.257.15:07:50.71#ibcon#read 3, iclass 7, count 0 2006.257.15:07:50.71#ibcon#about to read 4, iclass 7, count 0 2006.257.15:07:50.71#ibcon#read 4, iclass 7, count 0 2006.257.15:07:50.71#ibcon#about to read 5, iclass 7, count 0 2006.257.15:07:50.71#ibcon#read 5, iclass 7, count 0 2006.257.15:07:50.71#ibcon#about to read 6, iclass 7, count 0 2006.257.15:07:50.71#ibcon#read 6, iclass 7, count 0 2006.257.15:07:50.71#ibcon#end of sib2, iclass 7, count 0 2006.257.15:07:50.71#ibcon#*after write, iclass 7, count 0 2006.257.15:07:50.71#ibcon#*before return 0, iclass 7, count 0 2006.257.15:07:50.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:50.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:07:50.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:07:50.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:07:50.71$vck44/vb=3,4 2006.257.15:07:50.71#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.15:07:50.71#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.15:07:50.71#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:50.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:50.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:50.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:50.77#ibcon#enter wrdev, iclass 11, count 2 2006.257.15:07:50.77#ibcon#first serial, iclass 11, count 2 2006.257.15:07:50.77#ibcon#enter sib2, iclass 11, count 2 2006.257.15:07:50.77#ibcon#flushed, iclass 11, count 2 2006.257.15:07:50.77#ibcon#about to write, iclass 11, count 2 2006.257.15:07:50.77#ibcon#wrote, iclass 11, count 2 2006.257.15:07:50.77#ibcon#about to read 3, iclass 11, count 2 2006.257.15:07:50.79#ibcon#read 3, iclass 11, count 2 2006.257.15:07:50.79#ibcon#about to read 4, iclass 11, count 2 2006.257.15:07:50.79#ibcon#read 4, iclass 11, count 2 2006.257.15:07:50.79#ibcon#about to read 5, iclass 11, count 2 2006.257.15:07:50.79#ibcon#read 5, iclass 11, count 2 2006.257.15:07:50.79#ibcon#about to read 6, iclass 11, count 2 2006.257.15:07:50.79#ibcon#read 6, iclass 11, count 2 2006.257.15:07:50.79#ibcon#end of sib2, iclass 11, count 2 2006.257.15:07:50.79#ibcon#*mode == 0, iclass 11, count 2 2006.257.15:07:50.79#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.15:07:50.79#ibcon#[27=AT03-04\r\n] 2006.257.15:07:50.79#ibcon#*before write, iclass 11, count 2 2006.257.15:07:50.79#ibcon#enter sib2, iclass 11, count 2 2006.257.15:07:50.79#ibcon#flushed, iclass 11, count 2 2006.257.15:07:50.79#ibcon#about to write, iclass 11, count 2 2006.257.15:07:50.79#ibcon#wrote, iclass 11, count 2 2006.257.15:07:50.79#ibcon#about to read 3, iclass 11, count 2 2006.257.15:07:50.82#ibcon#read 3, iclass 11, count 2 2006.257.15:07:50.82#ibcon#about to read 4, iclass 11, count 2 2006.257.15:07:50.82#ibcon#read 4, iclass 11, count 2 2006.257.15:07:50.82#ibcon#about to read 5, iclass 11, count 2 2006.257.15:07:50.82#ibcon#read 5, iclass 11, count 2 2006.257.15:07:50.82#ibcon#about to read 6, iclass 11, count 2 2006.257.15:07:50.82#ibcon#read 6, iclass 11, count 2 2006.257.15:07:50.82#ibcon#end of sib2, iclass 11, count 2 2006.257.15:07:50.82#ibcon#*after write, iclass 11, count 2 2006.257.15:07:50.82#ibcon#*before return 0, iclass 11, count 2 2006.257.15:07:50.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:50.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:07:50.82#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.15:07:50.82#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:50.82#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:50.94#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:50.94#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:50.94#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:07:50.94#ibcon#first serial, iclass 11, count 0 2006.257.15:07:50.94#ibcon#enter sib2, iclass 11, count 0 2006.257.15:07:50.94#ibcon#flushed, iclass 11, count 0 2006.257.15:07:50.94#ibcon#about to write, iclass 11, count 0 2006.257.15:07:50.94#ibcon#wrote, iclass 11, count 0 2006.257.15:07:50.94#ibcon#about to read 3, iclass 11, count 0 2006.257.15:07:50.96#ibcon#read 3, iclass 11, count 0 2006.257.15:07:50.96#ibcon#about to read 4, iclass 11, count 0 2006.257.15:07:50.96#ibcon#read 4, iclass 11, count 0 2006.257.15:07:50.96#ibcon#about to read 5, iclass 11, count 0 2006.257.15:07:50.96#ibcon#read 5, iclass 11, count 0 2006.257.15:07:50.96#ibcon#about to read 6, iclass 11, count 0 2006.257.15:07:50.96#ibcon#read 6, iclass 11, count 0 2006.257.15:07:50.96#ibcon#end of sib2, iclass 11, count 0 2006.257.15:07:50.96#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:07:50.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:07:50.96#ibcon#[27=USB\r\n] 2006.257.15:07:50.96#ibcon#*before write, iclass 11, count 0 2006.257.15:07:50.96#ibcon#enter sib2, iclass 11, count 0 2006.257.15:07:50.96#ibcon#flushed, iclass 11, count 0 2006.257.15:07:50.96#ibcon#about to write, iclass 11, count 0 2006.257.15:07:50.96#ibcon#wrote, iclass 11, count 0 2006.257.15:07:50.96#ibcon#about to read 3, iclass 11, count 0 2006.257.15:07:50.99#ibcon#read 3, iclass 11, count 0 2006.257.15:07:50.99#ibcon#about to read 4, iclass 11, count 0 2006.257.15:07:50.99#ibcon#read 4, iclass 11, count 0 2006.257.15:07:50.99#ibcon#about to read 5, iclass 11, count 0 2006.257.15:07:50.99#ibcon#read 5, iclass 11, count 0 2006.257.15:07:50.99#ibcon#about to read 6, iclass 11, count 0 2006.257.15:07:50.99#ibcon#read 6, iclass 11, count 0 2006.257.15:07:50.99#ibcon#end of sib2, iclass 11, count 0 2006.257.15:07:50.99#ibcon#*after write, iclass 11, count 0 2006.257.15:07:50.99#ibcon#*before return 0, iclass 11, count 0 2006.257.15:07:50.99#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:50.99#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:07:50.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:07:50.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:07:50.99$vck44/vblo=4,679.99 2006.257.15:07:50.99#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.15:07:50.99#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.15:07:50.99#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:50.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:07:50.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:07:50.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:07:50.99#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:07:50.99#ibcon#first serial, iclass 13, count 0 2006.257.15:07:50.99#ibcon#enter sib2, iclass 13, count 0 2006.257.15:07:50.99#ibcon#flushed, iclass 13, count 0 2006.257.15:07:50.99#ibcon#about to write, iclass 13, count 0 2006.257.15:07:50.99#ibcon#wrote, iclass 13, count 0 2006.257.15:07:50.99#ibcon#about to read 3, iclass 13, count 0 2006.257.15:07:51.01#ibcon#read 3, iclass 13, count 0 2006.257.15:07:51.01#ibcon#about to read 4, iclass 13, count 0 2006.257.15:07:51.01#ibcon#read 4, iclass 13, count 0 2006.257.15:07:51.01#ibcon#about to read 5, iclass 13, count 0 2006.257.15:07:51.01#ibcon#read 5, iclass 13, count 0 2006.257.15:07:51.01#ibcon#about to read 6, iclass 13, count 0 2006.257.15:07:51.01#ibcon#read 6, iclass 13, count 0 2006.257.15:07:51.01#ibcon#end of sib2, iclass 13, count 0 2006.257.15:07:51.01#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:07:51.01#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:07:51.01#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:07:51.01#ibcon#*before write, iclass 13, count 0 2006.257.15:07:51.01#ibcon#enter sib2, iclass 13, count 0 2006.257.15:07:51.01#ibcon#flushed, iclass 13, count 0 2006.257.15:07:51.01#ibcon#about to write, iclass 13, count 0 2006.257.15:07:51.01#ibcon#wrote, iclass 13, count 0 2006.257.15:07:51.01#ibcon#about to read 3, iclass 13, count 0 2006.257.15:07:51.05#ibcon#read 3, iclass 13, count 0 2006.257.15:07:51.05#ibcon#about to read 4, iclass 13, count 0 2006.257.15:07:51.05#ibcon#read 4, iclass 13, count 0 2006.257.15:07:51.05#ibcon#about to read 5, iclass 13, count 0 2006.257.15:07:51.05#ibcon#read 5, iclass 13, count 0 2006.257.15:07:51.05#ibcon#about to read 6, iclass 13, count 0 2006.257.15:07:51.05#ibcon#read 6, iclass 13, count 0 2006.257.15:07:51.05#ibcon#end of sib2, iclass 13, count 0 2006.257.15:07:51.05#ibcon#*after write, iclass 13, count 0 2006.257.15:07:51.05#ibcon#*before return 0, iclass 13, count 0 2006.257.15:07:51.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:07:51.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:07:51.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:07:51.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:07:51.05$vck44/vb=4,5 2006.257.15:07:51.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.15:07:51.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.15:07:51.05#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:51.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:07:51.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:07:51.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:07:51.11#ibcon#enter wrdev, iclass 15, count 2 2006.257.15:07:51.11#ibcon#first serial, iclass 15, count 2 2006.257.15:07:51.11#ibcon#enter sib2, iclass 15, count 2 2006.257.15:07:51.11#ibcon#flushed, iclass 15, count 2 2006.257.15:07:51.11#ibcon#about to write, iclass 15, count 2 2006.257.15:07:51.11#ibcon#wrote, iclass 15, count 2 2006.257.15:07:51.11#ibcon#about to read 3, iclass 15, count 2 2006.257.15:07:51.13#ibcon#read 3, iclass 15, count 2 2006.257.15:07:51.13#ibcon#about to read 4, iclass 15, count 2 2006.257.15:07:51.13#ibcon#read 4, iclass 15, count 2 2006.257.15:07:51.13#ibcon#about to read 5, iclass 15, count 2 2006.257.15:07:51.13#ibcon#read 5, iclass 15, count 2 2006.257.15:07:51.13#ibcon#about to read 6, iclass 15, count 2 2006.257.15:07:51.13#ibcon#read 6, iclass 15, count 2 2006.257.15:07:51.13#ibcon#end of sib2, iclass 15, count 2 2006.257.15:07:51.13#ibcon#*mode == 0, iclass 15, count 2 2006.257.15:07:51.13#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.15:07:51.13#ibcon#[27=AT04-05\r\n] 2006.257.15:07:51.13#ibcon#*before write, iclass 15, count 2 2006.257.15:07:51.13#ibcon#enter sib2, iclass 15, count 2 2006.257.15:07:51.13#ibcon#flushed, iclass 15, count 2 2006.257.15:07:51.13#ibcon#about to write, iclass 15, count 2 2006.257.15:07:51.13#ibcon#wrote, iclass 15, count 2 2006.257.15:07:51.13#ibcon#about to read 3, iclass 15, count 2 2006.257.15:07:51.16#ibcon#read 3, iclass 15, count 2 2006.257.15:07:51.16#ibcon#about to read 4, iclass 15, count 2 2006.257.15:07:51.16#ibcon#read 4, iclass 15, count 2 2006.257.15:07:51.16#ibcon#about to read 5, iclass 15, count 2 2006.257.15:07:51.16#ibcon#read 5, iclass 15, count 2 2006.257.15:07:51.16#ibcon#about to read 6, iclass 15, count 2 2006.257.15:07:51.16#ibcon#read 6, iclass 15, count 2 2006.257.15:07:51.16#ibcon#end of sib2, iclass 15, count 2 2006.257.15:07:51.16#ibcon#*after write, iclass 15, count 2 2006.257.15:07:51.16#ibcon#*before return 0, iclass 15, count 2 2006.257.15:07:51.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:07:51.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:07:51.16#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.15:07:51.16#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:51.16#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:07:51.28#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:07:51.28#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:07:51.28#ibcon#enter wrdev, iclass 15, count 0 2006.257.15:07:51.28#ibcon#first serial, iclass 15, count 0 2006.257.15:07:51.28#ibcon#enter sib2, iclass 15, count 0 2006.257.15:07:51.28#ibcon#flushed, iclass 15, count 0 2006.257.15:07:51.28#ibcon#about to write, iclass 15, count 0 2006.257.15:07:51.28#ibcon#wrote, iclass 15, count 0 2006.257.15:07:51.28#ibcon#about to read 3, iclass 15, count 0 2006.257.15:07:51.30#ibcon#read 3, iclass 15, count 0 2006.257.15:07:51.30#ibcon#about to read 4, iclass 15, count 0 2006.257.15:07:51.30#ibcon#read 4, iclass 15, count 0 2006.257.15:07:51.30#ibcon#about to read 5, iclass 15, count 0 2006.257.15:07:51.30#ibcon#read 5, iclass 15, count 0 2006.257.15:07:51.30#ibcon#about to read 6, iclass 15, count 0 2006.257.15:07:51.30#ibcon#read 6, iclass 15, count 0 2006.257.15:07:51.30#ibcon#end of sib2, iclass 15, count 0 2006.257.15:07:51.30#ibcon#*mode == 0, iclass 15, count 0 2006.257.15:07:51.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.15:07:51.30#ibcon#[27=USB\r\n] 2006.257.15:07:51.30#ibcon#*before write, iclass 15, count 0 2006.257.15:07:51.30#ibcon#enter sib2, iclass 15, count 0 2006.257.15:07:51.30#ibcon#flushed, iclass 15, count 0 2006.257.15:07:51.30#ibcon#about to write, iclass 15, count 0 2006.257.15:07:51.30#ibcon#wrote, iclass 15, count 0 2006.257.15:07:51.30#ibcon#about to read 3, iclass 15, count 0 2006.257.15:07:51.33#ibcon#read 3, iclass 15, count 0 2006.257.15:07:51.33#ibcon#about to read 4, iclass 15, count 0 2006.257.15:07:51.33#ibcon#read 4, iclass 15, count 0 2006.257.15:07:51.33#ibcon#about to read 5, iclass 15, count 0 2006.257.15:07:51.33#ibcon#read 5, iclass 15, count 0 2006.257.15:07:51.33#ibcon#about to read 6, iclass 15, count 0 2006.257.15:07:51.33#ibcon#read 6, iclass 15, count 0 2006.257.15:07:51.33#ibcon#end of sib2, iclass 15, count 0 2006.257.15:07:51.33#ibcon#*after write, iclass 15, count 0 2006.257.15:07:51.33#ibcon#*before return 0, iclass 15, count 0 2006.257.15:07:51.33#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:07:51.33#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:07:51.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.15:07:51.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.15:07:51.33$vck44/vblo=5,709.99 2006.257.15:07:51.33#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.15:07:51.33#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.15:07:51.33#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:51.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:51.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:51.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:51.33#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:07:51.33#ibcon#first serial, iclass 17, count 0 2006.257.15:07:51.33#ibcon#enter sib2, iclass 17, count 0 2006.257.15:07:51.33#ibcon#flushed, iclass 17, count 0 2006.257.15:07:51.33#ibcon#about to write, iclass 17, count 0 2006.257.15:07:51.33#ibcon#wrote, iclass 17, count 0 2006.257.15:07:51.33#ibcon#about to read 3, iclass 17, count 0 2006.257.15:07:51.35#ibcon#read 3, iclass 17, count 0 2006.257.15:07:51.35#ibcon#about to read 4, iclass 17, count 0 2006.257.15:07:51.35#ibcon#read 4, iclass 17, count 0 2006.257.15:07:51.35#ibcon#about to read 5, iclass 17, count 0 2006.257.15:07:51.35#ibcon#read 5, iclass 17, count 0 2006.257.15:07:51.35#ibcon#about to read 6, iclass 17, count 0 2006.257.15:07:51.35#ibcon#read 6, iclass 17, count 0 2006.257.15:07:51.35#ibcon#end of sib2, iclass 17, count 0 2006.257.15:07:51.35#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:07:51.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:07:51.35#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:07:51.35#ibcon#*before write, iclass 17, count 0 2006.257.15:07:51.35#ibcon#enter sib2, iclass 17, count 0 2006.257.15:07:51.35#ibcon#flushed, iclass 17, count 0 2006.257.15:07:51.35#ibcon#about to write, iclass 17, count 0 2006.257.15:07:51.35#ibcon#wrote, iclass 17, count 0 2006.257.15:07:51.35#ibcon#about to read 3, iclass 17, count 0 2006.257.15:07:51.39#ibcon#read 3, iclass 17, count 0 2006.257.15:07:51.39#ibcon#about to read 4, iclass 17, count 0 2006.257.15:07:51.39#ibcon#read 4, iclass 17, count 0 2006.257.15:07:51.39#ibcon#about to read 5, iclass 17, count 0 2006.257.15:07:51.39#ibcon#read 5, iclass 17, count 0 2006.257.15:07:51.39#ibcon#about to read 6, iclass 17, count 0 2006.257.15:07:51.39#ibcon#read 6, iclass 17, count 0 2006.257.15:07:51.39#ibcon#end of sib2, iclass 17, count 0 2006.257.15:07:51.39#ibcon#*after write, iclass 17, count 0 2006.257.15:07:51.39#ibcon#*before return 0, iclass 17, count 0 2006.257.15:07:51.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:51.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:07:51.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:07:51.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:07:51.39$vck44/vb=5,4 2006.257.15:07:51.39#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.15:07:51.39#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.15:07:51.39#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:51.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:51.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:51.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:51.45#ibcon#enter wrdev, iclass 19, count 2 2006.257.15:07:51.45#ibcon#first serial, iclass 19, count 2 2006.257.15:07:51.45#ibcon#enter sib2, iclass 19, count 2 2006.257.15:07:51.45#ibcon#flushed, iclass 19, count 2 2006.257.15:07:51.45#ibcon#about to write, iclass 19, count 2 2006.257.15:07:51.45#ibcon#wrote, iclass 19, count 2 2006.257.15:07:51.45#ibcon#about to read 3, iclass 19, count 2 2006.257.15:07:51.47#ibcon#read 3, iclass 19, count 2 2006.257.15:07:51.47#ibcon#about to read 4, iclass 19, count 2 2006.257.15:07:51.47#ibcon#read 4, iclass 19, count 2 2006.257.15:07:51.47#ibcon#about to read 5, iclass 19, count 2 2006.257.15:07:51.47#ibcon#read 5, iclass 19, count 2 2006.257.15:07:51.47#ibcon#about to read 6, iclass 19, count 2 2006.257.15:07:51.47#ibcon#read 6, iclass 19, count 2 2006.257.15:07:51.47#ibcon#end of sib2, iclass 19, count 2 2006.257.15:07:51.47#ibcon#*mode == 0, iclass 19, count 2 2006.257.15:07:51.47#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.15:07:51.47#ibcon#[27=AT05-04\r\n] 2006.257.15:07:51.47#ibcon#*before write, iclass 19, count 2 2006.257.15:07:51.47#ibcon#enter sib2, iclass 19, count 2 2006.257.15:07:51.47#ibcon#flushed, iclass 19, count 2 2006.257.15:07:51.47#ibcon#about to write, iclass 19, count 2 2006.257.15:07:51.47#ibcon#wrote, iclass 19, count 2 2006.257.15:07:51.47#ibcon#about to read 3, iclass 19, count 2 2006.257.15:07:51.50#ibcon#read 3, iclass 19, count 2 2006.257.15:07:51.50#ibcon#about to read 4, iclass 19, count 2 2006.257.15:07:51.50#ibcon#read 4, iclass 19, count 2 2006.257.15:07:51.50#ibcon#about to read 5, iclass 19, count 2 2006.257.15:07:51.50#ibcon#read 5, iclass 19, count 2 2006.257.15:07:51.50#ibcon#about to read 6, iclass 19, count 2 2006.257.15:07:51.50#ibcon#read 6, iclass 19, count 2 2006.257.15:07:51.50#ibcon#end of sib2, iclass 19, count 2 2006.257.15:07:51.50#ibcon#*after write, iclass 19, count 2 2006.257.15:07:51.50#ibcon#*before return 0, iclass 19, count 2 2006.257.15:07:51.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:51.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:07:51.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.15:07:51.50#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:51.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:51.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:51.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:51.62#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:07:51.62#ibcon#first serial, iclass 19, count 0 2006.257.15:07:51.62#ibcon#enter sib2, iclass 19, count 0 2006.257.15:07:51.62#ibcon#flushed, iclass 19, count 0 2006.257.15:07:51.62#ibcon#about to write, iclass 19, count 0 2006.257.15:07:51.62#ibcon#wrote, iclass 19, count 0 2006.257.15:07:51.62#ibcon#about to read 3, iclass 19, count 0 2006.257.15:07:51.64#ibcon#read 3, iclass 19, count 0 2006.257.15:07:51.64#ibcon#about to read 4, iclass 19, count 0 2006.257.15:07:51.64#ibcon#read 4, iclass 19, count 0 2006.257.15:07:51.64#ibcon#about to read 5, iclass 19, count 0 2006.257.15:07:51.64#ibcon#read 5, iclass 19, count 0 2006.257.15:07:51.64#ibcon#about to read 6, iclass 19, count 0 2006.257.15:07:51.64#ibcon#read 6, iclass 19, count 0 2006.257.15:07:51.64#ibcon#end of sib2, iclass 19, count 0 2006.257.15:07:51.64#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:07:51.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:07:51.64#ibcon#[27=USB\r\n] 2006.257.15:07:51.64#ibcon#*before write, iclass 19, count 0 2006.257.15:07:51.64#ibcon#enter sib2, iclass 19, count 0 2006.257.15:07:51.64#ibcon#flushed, iclass 19, count 0 2006.257.15:07:51.64#ibcon#about to write, iclass 19, count 0 2006.257.15:07:51.64#ibcon#wrote, iclass 19, count 0 2006.257.15:07:51.64#ibcon#about to read 3, iclass 19, count 0 2006.257.15:07:51.67#ibcon#read 3, iclass 19, count 0 2006.257.15:07:51.67#ibcon#about to read 4, iclass 19, count 0 2006.257.15:07:51.67#ibcon#read 4, iclass 19, count 0 2006.257.15:07:51.67#ibcon#about to read 5, iclass 19, count 0 2006.257.15:07:51.67#ibcon#read 5, iclass 19, count 0 2006.257.15:07:51.67#ibcon#about to read 6, iclass 19, count 0 2006.257.15:07:51.67#ibcon#read 6, iclass 19, count 0 2006.257.15:07:51.67#ibcon#end of sib2, iclass 19, count 0 2006.257.15:07:51.67#ibcon#*after write, iclass 19, count 0 2006.257.15:07:51.67#ibcon#*before return 0, iclass 19, count 0 2006.257.15:07:51.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:51.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:07:51.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:07:51.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:07:51.67$vck44/vblo=6,719.99 2006.257.15:07:51.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.15:07:51.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.15:07:51.67#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:51.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:51.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:51.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:51.67#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:07:51.67#ibcon#first serial, iclass 21, count 0 2006.257.15:07:51.67#ibcon#enter sib2, iclass 21, count 0 2006.257.15:07:51.67#ibcon#flushed, iclass 21, count 0 2006.257.15:07:51.67#ibcon#about to write, iclass 21, count 0 2006.257.15:07:51.67#ibcon#wrote, iclass 21, count 0 2006.257.15:07:51.67#ibcon#about to read 3, iclass 21, count 0 2006.257.15:07:51.69#ibcon#read 3, iclass 21, count 0 2006.257.15:07:51.69#ibcon#about to read 4, iclass 21, count 0 2006.257.15:07:51.69#ibcon#read 4, iclass 21, count 0 2006.257.15:07:51.69#ibcon#about to read 5, iclass 21, count 0 2006.257.15:07:51.69#ibcon#read 5, iclass 21, count 0 2006.257.15:07:51.69#ibcon#about to read 6, iclass 21, count 0 2006.257.15:07:51.69#ibcon#read 6, iclass 21, count 0 2006.257.15:07:51.69#ibcon#end of sib2, iclass 21, count 0 2006.257.15:07:51.69#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:07:51.69#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:07:51.69#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:07:51.69#ibcon#*before write, iclass 21, count 0 2006.257.15:07:51.69#ibcon#enter sib2, iclass 21, count 0 2006.257.15:07:51.69#ibcon#flushed, iclass 21, count 0 2006.257.15:07:51.69#ibcon#about to write, iclass 21, count 0 2006.257.15:07:51.69#ibcon#wrote, iclass 21, count 0 2006.257.15:07:51.69#ibcon#about to read 3, iclass 21, count 0 2006.257.15:07:51.73#ibcon#read 3, iclass 21, count 0 2006.257.15:07:51.73#ibcon#about to read 4, iclass 21, count 0 2006.257.15:07:51.73#ibcon#read 4, iclass 21, count 0 2006.257.15:07:51.73#ibcon#about to read 5, iclass 21, count 0 2006.257.15:07:51.73#ibcon#read 5, iclass 21, count 0 2006.257.15:07:51.73#ibcon#about to read 6, iclass 21, count 0 2006.257.15:07:51.73#ibcon#read 6, iclass 21, count 0 2006.257.15:07:51.73#ibcon#end of sib2, iclass 21, count 0 2006.257.15:07:51.73#ibcon#*after write, iclass 21, count 0 2006.257.15:07:51.73#ibcon#*before return 0, iclass 21, count 0 2006.257.15:07:51.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:51.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:07:51.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:07:51.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:07:51.73$vck44/vb=6,4 2006.257.15:07:51.73#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.15:07:51.73#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.15:07:51.73#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:51.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:51.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:51.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:51.79#ibcon#enter wrdev, iclass 23, count 2 2006.257.15:07:51.79#ibcon#first serial, iclass 23, count 2 2006.257.15:07:51.79#ibcon#enter sib2, iclass 23, count 2 2006.257.15:07:51.79#ibcon#flushed, iclass 23, count 2 2006.257.15:07:51.79#ibcon#about to write, iclass 23, count 2 2006.257.15:07:51.79#ibcon#wrote, iclass 23, count 2 2006.257.15:07:51.79#ibcon#about to read 3, iclass 23, count 2 2006.257.15:07:51.81#ibcon#read 3, iclass 23, count 2 2006.257.15:07:51.81#ibcon#about to read 4, iclass 23, count 2 2006.257.15:07:51.81#ibcon#read 4, iclass 23, count 2 2006.257.15:07:51.81#ibcon#about to read 5, iclass 23, count 2 2006.257.15:07:51.81#ibcon#read 5, iclass 23, count 2 2006.257.15:07:51.81#ibcon#about to read 6, iclass 23, count 2 2006.257.15:07:51.81#ibcon#read 6, iclass 23, count 2 2006.257.15:07:51.81#ibcon#end of sib2, iclass 23, count 2 2006.257.15:07:51.81#ibcon#*mode == 0, iclass 23, count 2 2006.257.15:07:51.81#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.15:07:51.81#ibcon#[27=AT06-04\r\n] 2006.257.15:07:51.81#ibcon#*before write, iclass 23, count 2 2006.257.15:07:51.81#ibcon#enter sib2, iclass 23, count 2 2006.257.15:07:51.81#ibcon#flushed, iclass 23, count 2 2006.257.15:07:51.81#ibcon#about to write, iclass 23, count 2 2006.257.15:07:51.81#ibcon#wrote, iclass 23, count 2 2006.257.15:07:51.81#ibcon#about to read 3, iclass 23, count 2 2006.257.15:07:51.84#ibcon#read 3, iclass 23, count 2 2006.257.15:07:51.84#ibcon#about to read 4, iclass 23, count 2 2006.257.15:07:51.84#ibcon#read 4, iclass 23, count 2 2006.257.15:07:51.84#ibcon#about to read 5, iclass 23, count 2 2006.257.15:07:51.84#ibcon#read 5, iclass 23, count 2 2006.257.15:07:51.84#ibcon#about to read 6, iclass 23, count 2 2006.257.15:07:51.84#ibcon#read 6, iclass 23, count 2 2006.257.15:07:51.84#ibcon#end of sib2, iclass 23, count 2 2006.257.15:07:51.84#ibcon#*after write, iclass 23, count 2 2006.257.15:07:51.84#ibcon#*before return 0, iclass 23, count 2 2006.257.15:07:51.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:51.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:07:51.84#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.15:07:51.84#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:51.84#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:51.96#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:51.96#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:51.96#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:07:51.96#ibcon#first serial, iclass 23, count 0 2006.257.15:07:51.96#ibcon#enter sib2, iclass 23, count 0 2006.257.15:07:51.96#ibcon#flushed, iclass 23, count 0 2006.257.15:07:51.96#ibcon#about to write, iclass 23, count 0 2006.257.15:07:51.96#ibcon#wrote, iclass 23, count 0 2006.257.15:07:51.96#ibcon#about to read 3, iclass 23, count 0 2006.257.15:07:51.98#ibcon#read 3, iclass 23, count 0 2006.257.15:07:51.98#ibcon#about to read 4, iclass 23, count 0 2006.257.15:07:51.98#ibcon#read 4, iclass 23, count 0 2006.257.15:07:51.98#ibcon#about to read 5, iclass 23, count 0 2006.257.15:07:51.98#ibcon#read 5, iclass 23, count 0 2006.257.15:07:51.98#ibcon#about to read 6, iclass 23, count 0 2006.257.15:07:51.98#ibcon#read 6, iclass 23, count 0 2006.257.15:07:51.98#ibcon#end of sib2, iclass 23, count 0 2006.257.15:07:51.98#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:07:51.98#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:07:51.98#ibcon#[27=USB\r\n] 2006.257.15:07:51.98#ibcon#*before write, iclass 23, count 0 2006.257.15:07:51.98#ibcon#enter sib2, iclass 23, count 0 2006.257.15:07:51.98#ibcon#flushed, iclass 23, count 0 2006.257.15:07:51.98#ibcon#about to write, iclass 23, count 0 2006.257.15:07:51.98#ibcon#wrote, iclass 23, count 0 2006.257.15:07:51.98#ibcon#about to read 3, iclass 23, count 0 2006.257.15:07:52.01#ibcon#read 3, iclass 23, count 0 2006.257.15:07:52.01#ibcon#about to read 4, iclass 23, count 0 2006.257.15:07:52.01#ibcon#read 4, iclass 23, count 0 2006.257.15:07:52.01#ibcon#about to read 5, iclass 23, count 0 2006.257.15:07:52.01#ibcon#read 5, iclass 23, count 0 2006.257.15:07:52.01#ibcon#about to read 6, iclass 23, count 0 2006.257.15:07:52.01#ibcon#read 6, iclass 23, count 0 2006.257.15:07:52.01#ibcon#end of sib2, iclass 23, count 0 2006.257.15:07:52.01#ibcon#*after write, iclass 23, count 0 2006.257.15:07:52.01#ibcon#*before return 0, iclass 23, count 0 2006.257.15:07:52.01#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:52.01#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:07:52.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:07:52.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:07:52.01$vck44/vblo=7,734.99 2006.257.15:07:52.01#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.15:07:52.01#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.15:07:52.01#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:52.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:52.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:52.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:52.01#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:07:52.01#ibcon#first serial, iclass 25, count 0 2006.257.15:07:52.01#ibcon#enter sib2, iclass 25, count 0 2006.257.15:07:52.01#ibcon#flushed, iclass 25, count 0 2006.257.15:07:52.01#ibcon#about to write, iclass 25, count 0 2006.257.15:07:52.01#ibcon#wrote, iclass 25, count 0 2006.257.15:07:52.01#ibcon#about to read 3, iclass 25, count 0 2006.257.15:07:52.03#ibcon#read 3, iclass 25, count 0 2006.257.15:07:52.03#ibcon#about to read 4, iclass 25, count 0 2006.257.15:07:52.03#ibcon#read 4, iclass 25, count 0 2006.257.15:07:52.03#ibcon#about to read 5, iclass 25, count 0 2006.257.15:07:52.03#ibcon#read 5, iclass 25, count 0 2006.257.15:07:52.03#ibcon#about to read 6, iclass 25, count 0 2006.257.15:07:52.03#ibcon#read 6, iclass 25, count 0 2006.257.15:07:52.03#ibcon#end of sib2, iclass 25, count 0 2006.257.15:07:52.03#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:07:52.03#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:07:52.03#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:07:52.03#ibcon#*before write, iclass 25, count 0 2006.257.15:07:52.03#ibcon#enter sib2, iclass 25, count 0 2006.257.15:07:52.03#ibcon#flushed, iclass 25, count 0 2006.257.15:07:52.03#ibcon#about to write, iclass 25, count 0 2006.257.15:07:52.03#ibcon#wrote, iclass 25, count 0 2006.257.15:07:52.03#ibcon#about to read 3, iclass 25, count 0 2006.257.15:07:52.07#ibcon#read 3, iclass 25, count 0 2006.257.15:07:52.07#ibcon#about to read 4, iclass 25, count 0 2006.257.15:07:52.07#ibcon#read 4, iclass 25, count 0 2006.257.15:07:52.07#ibcon#about to read 5, iclass 25, count 0 2006.257.15:07:52.07#ibcon#read 5, iclass 25, count 0 2006.257.15:07:52.07#ibcon#about to read 6, iclass 25, count 0 2006.257.15:07:52.07#ibcon#read 6, iclass 25, count 0 2006.257.15:07:52.07#ibcon#end of sib2, iclass 25, count 0 2006.257.15:07:52.07#ibcon#*after write, iclass 25, count 0 2006.257.15:07:52.07#ibcon#*before return 0, iclass 25, count 0 2006.257.15:07:52.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:52.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:07:52.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:07:52.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:07:52.07$vck44/vb=7,4 2006.257.15:07:52.07#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.15:07:52.07#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.15:07:52.07#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:52.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:52.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:52.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:52.13#ibcon#enter wrdev, iclass 27, count 2 2006.257.15:07:52.13#ibcon#first serial, iclass 27, count 2 2006.257.15:07:52.13#ibcon#enter sib2, iclass 27, count 2 2006.257.15:07:52.13#ibcon#flushed, iclass 27, count 2 2006.257.15:07:52.13#ibcon#about to write, iclass 27, count 2 2006.257.15:07:52.13#ibcon#wrote, iclass 27, count 2 2006.257.15:07:52.13#ibcon#about to read 3, iclass 27, count 2 2006.257.15:07:52.15#ibcon#read 3, iclass 27, count 2 2006.257.15:07:52.15#ibcon#about to read 4, iclass 27, count 2 2006.257.15:07:52.15#ibcon#read 4, iclass 27, count 2 2006.257.15:07:52.15#ibcon#about to read 5, iclass 27, count 2 2006.257.15:07:52.15#ibcon#read 5, iclass 27, count 2 2006.257.15:07:52.15#ibcon#about to read 6, iclass 27, count 2 2006.257.15:07:52.15#ibcon#read 6, iclass 27, count 2 2006.257.15:07:52.15#ibcon#end of sib2, iclass 27, count 2 2006.257.15:07:52.15#ibcon#*mode == 0, iclass 27, count 2 2006.257.15:07:52.15#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.15:07:52.15#ibcon#[27=AT07-04\r\n] 2006.257.15:07:52.15#ibcon#*before write, iclass 27, count 2 2006.257.15:07:52.15#ibcon#enter sib2, iclass 27, count 2 2006.257.15:07:52.15#ibcon#flushed, iclass 27, count 2 2006.257.15:07:52.15#ibcon#about to write, iclass 27, count 2 2006.257.15:07:52.15#ibcon#wrote, iclass 27, count 2 2006.257.15:07:52.15#ibcon#about to read 3, iclass 27, count 2 2006.257.15:07:52.18#ibcon#read 3, iclass 27, count 2 2006.257.15:07:52.18#ibcon#about to read 4, iclass 27, count 2 2006.257.15:07:52.18#ibcon#read 4, iclass 27, count 2 2006.257.15:07:52.18#ibcon#about to read 5, iclass 27, count 2 2006.257.15:07:52.18#ibcon#read 5, iclass 27, count 2 2006.257.15:07:52.18#ibcon#about to read 6, iclass 27, count 2 2006.257.15:07:52.18#ibcon#read 6, iclass 27, count 2 2006.257.15:07:52.18#ibcon#end of sib2, iclass 27, count 2 2006.257.15:07:52.18#ibcon#*after write, iclass 27, count 2 2006.257.15:07:52.18#ibcon#*before return 0, iclass 27, count 2 2006.257.15:07:52.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:52.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:07:52.18#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.15:07:52.18#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:52.18#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:52.30#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:52.30#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:52.30#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:07:52.30#ibcon#first serial, iclass 27, count 0 2006.257.15:07:52.30#ibcon#enter sib2, iclass 27, count 0 2006.257.15:07:52.30#ibcon#flushed, iclass 27, count 0 2006.257.15:07:52.30#ibcon#about to write, iclass 27, count 0 2006.257.15:07:52.30#ibcon#wrote, iclass 27, count 0 2006.257.15:07:52.30#ibcon#about to read 3, iclass 27, count 0 2006.257.15:07:52.32#ibcon#read 3, iclass 27, count 0 2006.257.15:07:52.32#ibcon#about to read 4, iclass 27, count 0 2006.257.15:07:52.32#ibcon#read 4, iclass 27, count 0 2006.257.15:07:52.32#ibcon#about to read 5, iclass 27, count 0 2006.257.15:07:52.32#ibcon#read 5, iclass 27, count 0 2006.257.15:07:52.32#ibcon#about to read 6, iclass 27, count 0 2006.257.15:07:52.32#ibcon#read 6, iclass 27, count 0 2006.257.15:07:52.32#ibcon#end of sib2, iclass 27, count 0 2006.257.15:07:52.32#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:07:52.32#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:07:52.32#ibcon#[27=USB\r\n] 2006.257.15:07:52.32#ibcon#*before write, iclass 27, count 0 2006.257.15:07:52.32#ibcon#enter sib2, iclass 27, count 0 2006.257.15:07:52.32#ibcon#flushed, iclass 27, count 0 2006.257.15:07:52.32#ibcon#about to write, iclass 27, count 0 2006.257.15:07:52.32#ibcon#wrote, iclass 27, count 0 2006.257.15:07:52.32#ibcon#about to read 3, iclass 27, count 0 2006.257.15:07:52.35#ibcon#read 3, iclass 27, count 0 2006.257.15:07:52.35#ibcon#about to read 4, iclass 27, count 0 2006.257.15:07:52.35#ibcon#read 4, iclass 27, count 0 2006.257.15:07:52.35#ibcon#about to read 5, iclass 27, count 0 2006.257.15:07:52.35#ibcon#read 5, iclass 27, count 0 2006.257.15:07:52.35#ibcon#about to read 6, iclass 27, count 0 2006.257.15:07:52.35#ibcon#read 6, iclass 27, count 0 2006.257.15:07:52.35#ibcon#end of sib2, iclass 27, count 0 2006.257.15:07:52.35#ibcon#*after write, iclass 27, count 0 2006.257.15:07:52.35#ibcon#*before return 0, iclass 27, count 0 2006.257.15:07:52.35#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:52.35#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:07:52.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:07:52.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:07:52.35$vck44/vblo=8,744.99 2006.257.15:07:52.35#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.15:07:52.35#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.15:07:52.35#ibcon#ireg 17 cls_cnt 0 2006.257.15:07:52.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:52.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:52.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:52.35#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:07:52.35#ibcon#first serial, iclass 29, count 0 2006.257.15:07:52.35#ibcon#enter sib2, iclass 29, count 0 2006.257.15:07:52.35#ibcon#flushed, iclass 29, count 0 2006.257.15:07:52.35#ibcon#about to write, iclass 29, count 0 2006.257.15:07:52.35#ibcon#wrote, iclass 29, count 0 2006.257.15:07:52.35#ibcon#about to read 3, iclass 29, count 0 2006.257.15:07:52.37#ibcon#read 3, iclass 29, count 0 2006.257.15:07:52.37#ibcon#about to read 4, iclass 29, count 0 2006.257.15:07:52.37#ibcon#read 4, iclass 29, count 0 2006.257.15:07:52.37#ibcon#about to read 5, iclass 29, count 0 2006.257.15:07:52.37#ibcon#read 5, iclass 29, count 0 2006.257.15:07:52.37#ibcon#about to read 6, iclass 29, count 0 2006.257.15:07:52.37#ibcon#read 6, iclass 29, count 0 2006.257.15:07:52.37#ibcon#end of sib2, iclass 29, count 0 2006.257.15:07:52.37#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:07:52.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:07:52.37#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:07:52.37#ibcon#*before write, iclass 29, count 0 2006.257.15:07:52.37#ibcon#enter sib2, iclass 29, count 0 2006.257.15:07:52.37#ibcon#flushed, iclass 29, count 0 2006.257.15:07:52.37#ibcon#about to write, iclass 29, count 0 2006.257.15:07:52.37#ibcon#wrote, iclass 29, count 0 2006.257.15:07:52.37#ibcon#about to read 3, iclass 29, count 0 2006.257.15:07:52.41#ibcon#read 3, iclass 29, count 0 2006.257.15:07:52.41#ibcon#about to read 4, iclass 29, count 0 2006.257.15:07:52.41#ibcon#read 4, iclass 29, count 0 2006.257.15:07:52.41#ibcon#about to read 5, iclass 29, count 0 2006.257.15:07:52.41#ibcon#read 5, iclass 29, count 0 2006.257.15:07:52.41#ibcon#about to read 6, iclass 29, count 0 2006.257.15:07:52.41#ibcon#read 6, iclass 29, count 0 2006.257.15:07:52.41#ibcon#end of sib2, iclass 29, count 0 2006.257.15:07:52.41#ibcon#*after write, iclass 29, count 0 2006.257.15:07:52.41#ibcon#*before return 0, iclass 29, count 0 2006.257.15:07:52.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:52.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:07:52.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:07:52.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:07:52.41$vck44/vb=8,4 2006.257.15:07:52.41#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.15:07:52.41#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.15:07:52.41#ibcon#ireg 11 cls_cnt 2 2006.257.15:07:52.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:52.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:52.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:52.47#ibcon#enter wrdev, iclass 31, count 2 2006.257.15:07:52.47#ibcon#first serial, iclass 31, count 2 2006.257.15:07:52.47#ibcon#enter sib2, iclass 31, count 2 2006.257.15:07:52.47#ibcon#flushed, iclass 31, count 2 2006.257.15:07:52.47#ibcon#about to write, iclass 31, count 2 2006.257.15:07:52.47#ibcon#wrote, iclass 31, count 2 2006.257.15:07:52.47#ibcon#about to read 3, iclass 31, count 2 2006.257.15:07:52.49#ibcon#read 3, iclass 31, count 2 2006.257.15:07:52.49#ibcon#about to read 4, iclass 31, count 2 2006.257.15:07:52.49#ibcon#read 4, iclass 31, count 2 2006.257.15:07:52.49#ibcon#about to read 5, iclass 31, count 2 2006.257.15:07:52.49#ibcon#read 5, iclass 31, count 2 2006.257.15:07:52.49#ibcon#about to read 6, iclass 31, count 2 2006.257.15:07:52.49#ibcon#read 6, iclass 31, count 2 2006.257.15:07:52.49#ibcon#end of sib2, iclass 31, count 2 2006.257.15:07:52.49#ibcon#*mode == 0, iclass 31, count 2 2006.257.15:07:52.49#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.15:07:52.49#ibcon#[27=AT08-04\r\n] 2006.257.15:07:52.49#ibcon#*before write, iclass 31, count 2 2006.257.15:07:52.49#ibcon#enter sib2, iclass 31, count 2 2006.257.15:07:52.49#ibcon#flushed, iclass 31, count 2 2006.257.15:07:52.49#ibcon#about to write, iclass 31, count 2 2006.257.15:07:52.49#ibcon#wrote, iclass 31, count 2 2006.257.15:07:52.49#ibcon#about to read 3, iclass 31, count 2 2006.257.15:07:52.52#ibcon#read 3, iclass 31, count 2 2006.257.15:07:52.52#ibcon#about to read 4, iclass 31, count 2 2006.257.15:07:52.52#ibcon#read 4, iclass 31, count 2 2006.257.15:07:52.52#ibcon#about to read 5, iclass 31, count 2 2006.257.15:07:52.52#ibcon#read 5, iclass 31, count 2 2006.257.15:07:52.52#ibcon#about to read 6, iclass 31, count 2 2006.257.15:07:52.52#ibcon#read 6, iclass 31, count 2 2006.257.15:07:52.52#ibcon#end of sib2, iclass 31, count 2 2006.257.15:07:52.52#ibcon#*after write, iclass 31, count 2 2006.257.15:07:52.52#ibcon#*before return 0, iclass 31, count 2 2006.257.15:07:52.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:52.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:07:52.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.15:07:52.52#ibcon#ireg 7 cls_cnt 0 2006.257.15:07:52.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:52.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:52.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:52.64#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:07:52.64#ibcon#first serial, iclass 31, count 0 2006.257.15:07:52.64#ibcon#enter sib2, iclass 31, count 0 2006.257.15:07:52.64#ibcon#flushed, iclass 31, count 0 2006.257.15:07:52.64#ibcon#about to write, iclass 31, count 0 2006.257.15:07:52.64#ibcon#wrote, iclass 31, count 0 2006.257.15:07:52.64#ibcon#about to read 3, iclass 31, count 0 2006.257.15:07:52.66#ibcon#read 3, iclass 31, count 0 2006.257.15:07:52.66#ibcon#about to read 4, iclass 31, count 0 2006.257.15:07:52.66#ibcon#read 4, iclass 31, count 0 2006.257.15:07:52.66#ibcon#about to read 5, iclass 31, count 0 2006.257.15:07:52.66#ibcon#read 5, iclass 31, count 0 2006.257.15:07:52.66#ibcon#about to read 6, iclass 31, count 0 2006.257.15:07:52.66#ibcon#read 6, iclass 31, count 0 2006.257.15:07:52.66#ibcon#end of sib2, iclass 31, count 0 2006.257.15:07:52.66#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:07:52.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:07:52.66#ibcon#[27=USB\r\n] 2006.257.15:07:52.66#ibcon#*before write, iclass 31, count 0 2006.257.15:07:52.66#ibcon#enter sib2, iclass 31, count 0 2006.257.15:07:52.66#ibcon#flushed, iclass 31, count 0 2006.257.15:07:52.66#ibcon#about to write, iclass 31, count 0 2006.257.15:07:52.66#ibcon#wrote, iclass 31, count 0 2006.257.15:07:52.66#ibcon#about to read 3, iclass 31, count 0 2006.257.15:07:52.69#ibcon#read 3, iclass 31, count 0 2006.257.15:07:52.69#ibcon#about to read 4, iclass 31, count 0 2006.257.15:07:52.69#ibcon#read 4, iclass 31, count 0 2006.257.15:07:52.69#ibcon#about to read 5, iclass 31, count 0 2006.257.15:07:52.69#ibcon#read 5, iclass 31, count 0 2006.257.15:07:52.69#ibcon#about to read 6, iclass 31, count 0 2006.257.15:07:52.69#ibcon#read 6, iclass 31, count 0 2006.257.15:07:52.69#ibcon#end of sib2, iclass 31, count 0 2006.257.15:07:52.69#ibcon#*after write, iclass 31, count 0 2006.257.15:07:52.69#ibcon#*before return 0, iclass 31, count 0 2006.257.15:07:52.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:52.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:07:52.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:07:52.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:07:52.69$vck44/vabw=wide 2006.257.15:07:52.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.15:07:52.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.15:07:52.69#ibcon#ireg 8 cls_cnt 0 2006.257.15:07:52.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:52.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:52.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:52.69#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:07:52.69#ibcon#first serial, iclass 33, count 0 2006.257.15:07:52.69#ibcon#enter sib2, iclass 33, count 0 2006.257.15:07:52.69#ibcon#flushed, iclass 33, count 0 2006.257.15:07:52.69#ibcon#about to write, iclass 33, count 0 2006.257.15:07:52.69#ibcon#wrote, iclass 33, count 0 2006.257.15:07:52.69#ibcon#about to read 3, iclass 33, count 0 2006.257.15:07:52.71#ibcon#read 3, iclass 33, count 0 2006.257.15:07:52.71#ibcon#about to read 4, iclass 33, count 0 2006.257.15:07:52.71#ibcon#read 4, iclass 33, count 0 2006.257.15:07:52.71#ibcon#about to read 5, iclass 33, count 0 2006.257.15:07:52.71#ibcon#read 5, iclass 33, count 0 2006.257.15:07:52.71#ibcon#about to read 6, iclass 33, count 0 2006.257.15:07:52.71#ibcon#read 6, iclass 33, count 0 2006.257.15:07:52.71#ibcon#end of sib2, iclass 33, count 0 2006.257.15:07:52.71#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:07:52.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:07:52.71#ibcon#[25=BW32\r\n] 2006.257.15:07:52.71#ibcon#*before write, iclass 33, count 0 2006.257.15:07:52.71#ibcon#enter sib2, iclass 33, count 0 2006.257.15:07:52.71#ibcon#flushed, iclass 33, count 0 2006.257.15:07:52.71#ibcon#about to write, iclass 33, count 0 2006.257.15:07:52.71#ibcon#wrote, iclass 33, count 0 2006.257.15:07:52.71#ibcon#about to read 3, iclass 33, count 0 2006.257.15:07:52.74#ibcon#read 3, iclass 33, count 0 2006.257.15:07:52.74#ibcon#about to read 4, iclass 33, count 0 2006.257.15:07:52.74#ibcon#read 4, iclass 33, count 0 2006.257.15:07:52.74#ibcon#about to read 5, iclass 33, count 0 2006.257.15:07:52.74#ibcon#read 5, iclass 33, count 0 2006.257.15:07:52.74#ibcon#about to read 6, iclass 33, count 0 2006.257.15:07:52.74#ibcon#read 6, iclass 33, count 0 2006.257.15:07:52.74#ibcon#end of sib2, iclass 33, count 0 2006.257.15:07:52.74#ibcon#*after write, iclass 33, count 0 2006.257.15:07:52.74#ibcon#*before return 0, iclass 33, count 0 2006.257.15:07:52.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:52.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:07:52.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:07:52.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:07:52.74$vck44/vbbw=wide 2006.257.15:07:52.74#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.15:07:52.74#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.15:07:52.74#ibcon#ireg 8 cls_cnt 0 2006.257.15:07:52.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:07:52.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:07:52.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:07:52.81#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:07:52.81#ibcon#first serial, iclass 35, count 0 2006.257.15:07:52.81#ibcon#enter sib2, iclass 35, count 0 2006.257.15:07:52.81#ibcon#flushed, iclass 35, count 0 2006.257.15:07:52.81#ibcon#about to write, iclass 35, count 0 2006.257.15:07:52.81#ibcon#wrote, iclass 35, count 0 2006.257.15:07:52.81#ibcon#about to read 3, iclass 35, count 0 2006.257.15:07:52.83#ibcon#read 3, iclass 35, count 0 2006.257.15:07:52.83#ibcon#about to read 4, iclass 35, count 0 2006.257.15:07:52.83#ibcon#read 4, iclass 35, count 0 2006.257.15:07:52.83#ibcon#about to read 5, iclass 35, count 0 2006.257.15:07:52.83#ibcon#read 5, iclass 35, count 0 2006.257.15:07:52.83#ibcon#about to read 6, iclass 35, count 0 2006.257.15:07:52.83#ibcon#read 6, iclass 35, count 0 2006.257.15:07:52.83#ibcon#end of sib2, iclass 35, count 0 2006.257.15:07:52.83#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:07:52.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:07:52.83#ibcon#[27=BW32\r\n] 2006.257.15:07:52.83#ibcon#*before write, iclass 35, count 0 2006.257.15:07:52.83#ibcon#enter sib2, iclass 35, count 0 2006.257.15:07:52.83#ibcon#flushed, iclass 35, count 0 2006.257.15:07:52.83#ibcon#about to write, iclass 35, count 0 2006.257.15:07:52.83#ibcon#wrote, iclass 35, count 0 2006.257.15:07:52.83#ibcon#about to read 3, iclass 35, count 0 2006.257.15:07:52.86#ibcon#read 3, iclass 35, count 0 2006.257.15:07:52.86#ibcon#about to read 4, iclass 35, count 0 2006.257.15:07:52.86#ibcon#read 4, iclass 35, count 0 2006.257.15:07:52.86#ibcon#about to read 5, iclass 35, count 0 2006.257.15:07:52.86#ibcon#read 5, iclass 35, count 0 2006.257.15:07:52.86#ibcon#about to read 6, iclass 35, count 0 2006.257.15:07:52.86#ibcon#read 6, iclass 35, count 0 2006.257.15:07:52.86#ibcon#end of sib2, iclass 35, count 0 2006.257.15:07:52.86#ibcon#*after write, iclass 35, count 0 2006.257.15:07:52.86#ibcon#*before return 0, iclass 35, count 0 2006.257.15:07:52.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:07:52.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:07:52.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:07:52.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:07:52.86$setupk4/ifdk4 2006.257.15:07:52.86$ifdk4/lo= 2006.257.15:07:52.86$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:07:52.86$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:07:52.86$ifdk4/patch= 2006.257.15:07:52.86$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:07:52.87$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:07:52.87$setupk4/!*+20s 2006.257.15:07:57.14#trakl#Source acquired 2006.257.15:07:57.14#flagr#flagr/antenna,acquired 2006.257.15:07:58.31#abcon#<5=/14 1.7 3.8 17.43 971014.0\r\n> 2006.257.15:07:58.33#abcon#{5=INTERFACE CLEAR} 2006.257.15:07:58.39#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:08:07.36$setupk4/"tpicd 2006.257.15:08:07.36$setupk4/echo=off 2006.257.15:08:07.36$setupk4/xlog=off 2006.257.15:08:07.36:!2006.257.15:08:16 2006.257.15:08:16.00:preob 2006.257.15:08:16.14/onsource/TRACKING 2006.257.15:08:16.14:!2006.257.15:08:26 2006.257.15:08:26.00:"tape 2006.257.15:08:26.00:"st=record 2006.257.15:08:26.00:data_valid=on 2006.257.15:08:26.00:midob 2006.257.15:08:27.14/onsource/TRACKING 2006.257.15:08:27.14/wx/17.44,1014.0,97 2006.257.15:08:27.20/cable/+6.4841E-03 2006.257.15:08:28.29/va/01,08,usb,yes,31,33 2006.257.15:08:28.29/va/02,07,usb,yes,33,34 2006.257.15:08:28.29/va/03,08,usb,yes,30,32 2006.257.15:08:28.29/va/04,07,usb,yes,35,36 2006.257.15:08:28.29/va/05,04,usb,yes,31,31 2006.257.15:08:28.29/va/06,04,usb,yes,34,34 2006.257.15:08:28.29/va/07,04,usb,yes,35,36 2006.257.15:08:28.29/va/08,04,usb,yes,29,36 2006.257.15:08:28.52/valo/01,524.99,yes,locked 2006.257.15:08:28.52/valo/02,534.99,yes,locked 2006.257.15:08:28.52/valo/03,564.99,yes,locked 2006.257.15:08:28.52/valo/04,624.99,yes,locked 2006.257.15:08:28.52/valo/05,734.99,yes,locked 2006.257.15:08:28.52/valo/06,814.99,yes,locked 2006.257.15:08:28.52/valo/07,864.99,yes,locked 2006.257.15:08:28.52/valo/08,884.99,yes,locked 2006.257.15:08:29.61/vb/01,04,usb,yes,31,29 2006.257.15:08:29.61/vb/02,05,usb,yes,29,29 2006.257.15:08:29.61/vb/03,04,usb,yes,30,33 2006.257.15:08:29.61/vb/04,05,usb,yes,30,29 2006.257.15:08:29.61/vb/05,04,usb,yes,27,29 2006.257.15:08:29.61/vb/06,04,usb,yes,31,27 2006.257.15:08:29.61/vb/07,04,usb,yes,31,31 2006.257.15:08:29.61/vb/08,04,usb,yes,28,32 2006.257.15:08:29.84/vblo/01,629.99,yes,locked 2006.257.15:08:29.84/vblo/02,634.99,yes,locked 2006.257.15:08:29.84/vblo/03,649.99,yes,locked 2006.257.15:08:29.84/vblo/04,679.99,yes,locked 2006.257.15:08:29.84/vblo/05,709.99,yes,locked 2006.257.15:08:29.84/vblo/06,719.99,yes,locked 2006.257.15:08:29.84/vblo/07,734.99,yes,locked 2006.257.15:08:29.84/vblo/08,744.99,yes,locked 2006.257.15:08:29.99/vabw/8 2006.257.15:08:30.14/vbbw/8 2006.257.15:08:30.23/xfe/off,on,15.2 2006.257.15:08:30.62/ifatt/23,28,28,28 2006.257.15:08:31.07/fmout-gps/S +4.62E-07 2006.257.15:08:31.11:!2006.257.15:12:36 2006.257.15:12:36.01:data_valid=off 2006.257.15:12:36.02:"et 2006.257.15:12:36.02:!+3s 2006.257.15:12:39.03:"tape 2006.257.15:12:39.04:postob 2006.257.15:12:39.12/cable/+6.4846E-03 2006.257.15:12:39.13/wx/17.44,1014.0,97 2006.257.15:12:39.18/fmout-gps/S +4.62E-07 2006.257.15:12:39.19:scan_name=257-1513,jd0609,784 2006.257.15:12:39.19:source=0804+499,080839.67,495036.5,2000.0,cw 2006.257.15:12:41.13#flagr#flagr/antenna,new-source 2006.257.15:12:41.14:checkk5 2006.257.15:12:41.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:12:41.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:12:42.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:12:42.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:12:43.16/chk_obsdata//k5ts1/T2571508??a.dat file size is correct (nominal:1000MB, actual:996MB). 2006.257.15:12:43.58/chk_obsdata//k5ts2/T2571508??b.dat file size is correct (nominal:1000MB, actual:996MB). 2006.257.15:12:43.98/chk_obsdata//k5ts3/T2571508??c.dat file size is correct (nominal:1000MB, actual:996MB). 2006.257.15:12:44.39/chk_obsdata//k5ts4/T2571508??d.dat file size is correct (nominal:1000MB, actual:996MB). 2006.257.15:12:45.14/k5log//k5ts1_log_newline 2006.257.15:12:45.87/k5log//k5ts2_log_newline 2006.257.15:12:46.59/k5log//k5ts3_log_newline 2006.257.15:12:47.32/k5log//k5ts4_log_newline 2006.257.15:12:47.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:12:47.34:setupk4=1 2006.257.15:12:47.34$setupk4/echo=on 2006.257.15:12:47.34$setupk4/pcalon 2006.257.15:12:47.34$pcalon/"no phase cal control is implemented here 2006.257.15:12:47.34$setupk4/"tpicd=stop 2006.257.15:12:47.34$setupk4/"rec=synch_on 2006.257.15:12:47.34$setupk4/"rec_mode=128 2006.257.15:12:47.34$setupk4/!* 2006.257.15:12:47.34$setupk4/recpk4 2006.257.15:12:47.34$recpk4/recpatch= 2006.257.15:12:47.34$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:12:47.35$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:12:47.35$setupk4/vck44 2006.257.15:12:47.35$vck44/valo=1,524.99 2006.257.15:12:47.35#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.15:12:47.35#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.15:12:47.35#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:47.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:47.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:47.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:47.35#ibcon#enter wrdev, iclass 12, count 0 2006.257.15:12:47.35#ibcon#first serial, iclass 12, count 0 2006.257.15:12:47.35#ibcon#enter sib2, iclass 12, count 0 2006.257.15:12:47.35#ibcon#flushed, iclass 12, count 0 2006.257.15:12:47.35#ibcon#about to write, iclass 12, count 0 2006.257.15:12:47.35#ibcon#wrote, iclass 12, count 0 2006.257.15:12:47.35#ibcon#about to read 3, iclass 12, count 0 2006.257.15:12:47.36#ibcon#read 3, iclass 12, count 0 2006.257.15:12:47.36#ibcon#about to read 4, iclass 12, count 0 2006.257.15:12:47.36#ibcon#read 4, iclass 12, count 0 2006.257.15:12:47.36#ibcon#about to read 5, iclass 12, count 0 2006.257.15:12:47.36#ibcon#read 5, iclass 12, count 0 2006.257.15:12:47.36#ibcon#about to read 6, iclass 12, count 0 2006.257.15:12:47.36#ibcon#read 6, iclass 12, count 0 2006.257.15:12:47.36#ibcon#end of sib2, iclass 12, count 0 2006.257.15:12:47.36#ibcon#*mode == 0, iclass 12, count 0 2006.257.15:12:47.36#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.15:12:47.36#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:12:47.36#ibcon#*before write, iclass 12, count 0 2006.257.15:12:47.36#ibcon#enter sib2, iclass 12, count 0 2006.257.15:12:47.36#ibcon#flushed, iclass 12, count 0 2006.257.15:12:47.36#ibcon#about to write, iclass 12, count 0 2006.257.15:12:47.36#ibcon#wrote, iclass 12, count 0 2006.257.15:12:47.36#ibcon#about to read 3, iclass 12, count 0 2006.257.15:12:47.41#ibcon#read 3, iclass 12, count 0 2006.257.15:12:47.41#ibcon#about to read 4, iclass 12, count 0 2006.257.15:12:47.41#ibcon#read 4, iclass 12, count 0 2006.257.15:12:47.41#ibcon#about to read 5, iclass 12, count 0 2006.257.15:12:47.41#ibcon#read 5, iclass 12, count 0 2006.257.15:12:47.41#ibcon#about to read 6, iclass 12, count 0 2006.257.15:12:47.41#ibcon#read 6, iclass 12, count 0 2006.257.15:12:47.41#ibcon#end of sib2, iclass 12, count 0 2006.257.15:12:47.41#ibcon#*after write, iclass 12, count 0 2006.257.15:12:47.41#ibcon#*before return 0, iclass 12, count 0 2006.257.15:12:47.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:47.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:47.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.15:12:47.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.15:12:47.41$vck44/va=1,8 2006.257.15:12:47.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.15:12:47.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.15:12:47.41#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:47.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:47.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:47.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:47.41#ibcon#enter wrdev, iclass 14, count 2 2006.257.15:12:47.41#ibcon#first serial, iclass 14, count 2 2006.257.15:12:47.41#ibcon#enter sib2, iclass 14, count 2 2006.257.15:12:47.41#ibcon#flushed, iclass 14, count 2 2006.257.15:12:47.41#ibcon#about to write, iclass 14, count 2 2006.257.15:12:47.41#ibcon#wrote, iclass 14, count 2 2006.257.15:12:47.41#ibcon#about to read 3, iclass 14, count 2 2006.257.15:12:47.43#ibcon#read 3, iclass 14, count 2 2006.257.15:12:47.43#ibcon#about to read 4, iclass 14, count 2 2006.257.15:12:47.43#ibcon#read 4, iclass 14, count 2 2006.257.15:12:47.43#ibcon#about to read 5, iclass 14, count 2 2006.257.15:12:47.43#ibcon#read 5, iclass 14, count 2 2006.257.15:12:47.43#ibcon#about to read 6, iclass 14, count 2 2006.257.15:12:47.43#ibcon#read 6, iclass 14, count 2 2006.257.15:12:47.43#ibcon#end of sib2, iclass 14, count 2 2006.257.15:12:47.43#ibcon#*mode == 0, iclass 14, count 2 2006.257.15:12:47.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.15:12:47.43#ibcon#[25=AT01-08\r\n] 2006.257.15:12:47.43#ibcon#*before write, iclass 14, count 2 2006.257.15:12:47.43#ibcon#enter sib2, iclass 14, count 2 2006.257.15:12:47.43#ibcon#flushed, iclass 14, count 2 2006.257.15:12:47.43#ibcon#about to write, iclass 14, count 2 2006.257.15:12:47.43#ibcon#wrote, iclass 14, count 2 2006.257.15:12:47.43#ibcon#about to read 3, iclass 14, count 2 2006.257.15:12:47.46#ibcon#read 3, iclass 14, count 2 2006.257.15:12:47.46#ibcon#about to read 4, iclass 14, count 2 2006.257.15:12:47.46#ibcon#read 4, iclass 14, count 2 2006.257.15:12:47.46#ibcon#about to read 5, iclass 14, count 2 2006.257.15:12:47.46#ibcon#read 5, iclass 14, count 2 2006.257.15:12:47.46#ibcon#about to read 6, iclass 14, count 2 2006.257.15:12:47.46#ibcon#read 6, iclass 14, count 2 2006.257.15:12:47.46#ibcon#end of sib2, iclass 14, count 2 2006.257.15:12:47.46#ibcon#*after write, iclass 14, count 2 2006.257.15:12:47.46#ibcon#*before return 0, iclass 14, count 2 2006.257.15:12:47.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:47.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:47.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.15:12:47.46#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:47.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:47.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:47.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:47.58#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:12:47.58#ibcon#first serial, iclass 14, count 0 2006.257.15:12:47.58#ibcon#enter sib2, iclass 14, count 0 2006.257.15:12:47.58#ibcon#flushed, iclass 14, count 0 2006.257.15:12:47.58#ibcon#about to write, iclass 14, count 0 2006.257.15:12:47.58#ibcon#wrote, iclass 14, count 0 2006.257.15:12:47.58#ibcon#about to read 3, iclass 14, count 0 2006.257.15:12:47.60#ibcon#read 3, iclass 14, count 0 2006.257.15:12:47.60#ibcon#about to read 4, iclass 14, count 0 2006.257.15:12:47.60#ibcon#read 4, iclass 14, count 0 2006.257.15:12:47.60#ibcon#about to read 5, iclass 14, count 0 2006.257.15:12:47.60#ibcon#read 5, iclass 14, count 0 2006.257.15:12:47.60#ibcon#about to read 6, iclass 14, count 0 2006.257.15:12:47.60#ibcon#read 6, iclass 14, count 0 2006.257.15:12:47.60#ibcon#end of sib2, iclass 14, count 0 2006.257.15:12:47.60#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:12:47.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:12:47.60#ibcon#[25=USB\r\n] 2006.257.15:12:47.60#ibcon#*before write, iclass 14, count 0 2006.257.15:12:47.60#ibcon#enter sib2, iclass 14, count 0 2006.257.15:12:47.60#ibcon#flushed, iclass 14, count 0 2006.257.15:12:47.60#ibcon#about to write, iclass 14, count 0 2006.257.15:12:47.60#ibcon#wrote, iclass 14, count 0 2006.257.15:12:47.60#ibcon#about to read 3, iclass 14, count 0 2006.257.15:12:47.63#ibcon#read 3, iclass 14, count 0 2006.257.15:12:47.63#ibcon#about to read 4, iclass 14, count 0 2006.257.15:12:47.63#ibcon#read 4, iclass 14, count 0 2006.257.15:12:47.63#ibcon#about to read 5, iclass 14, count 0 2006.257.15:12:47.63#ibcon#read 5, iclass 14, count 0 2006.257.15:12:47.63#ibcon#about to read 6, iclass 14, count 0 2006.257.15:12:47.63#ibcon#read 6, iclass 14, count 0 2006.257.15:12:47.63#ibcon#end of sib2, iclass 14, count 0 2006.257.15:12:47.63#ibcon#*after write, iclass 14, count 0 2006.257.15:12:47.63#ibcon#*before return 0, iclass 14, count 0 2006.257.15:12:47.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:47.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:47.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:12:47.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:12:47.63$vck44/valo=2,534.99 2006.257.15:12:47.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.15:12:47.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.15:12:47.63#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:47.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:47.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:47.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:47.63#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:12:47.63#ibcon#first serial, iclass 16, count 0 2006.257.15:12:47.63#ibcon#enter sib2, iclass 16, count 0 2006.257.15:12:47.63#ibcon#flushed, iclass 16, count 0 2006.257.15:12:47.63#ibcon#about to write, iclass 16, count 0 2006.257.15:12:47.63#ibcon#wrote, iclass 16, count 0 2006.257.15:12:47.63#ibcon#about to read 3, iclass 16, count 0 2006.257.15:12:47.65#ibcon#read 3, iclass 16, count 0 2006.257.15:12:47.65#ibcon#about to read 4, iclass 16, count 0 2006.257.15:12:47.65#ibcon#read 4, iclass 16, count 0 2006.257.15:12:47.65#ibcon#about to read 5, iclass 16, count 0 2006.257.15:12:47.65#ibcon#read 5, iclass 16, count 0 2006.257.15:12:47.65#ibcon#about to read 6, iclass 16, count 0 2006.257.15:12:47.65#ibcon#read 6, iclass 16, count 0 2006.257.15:12:47.65#ibcon#end of sib2, iclass 16, count 0 2006.257.15:12:47.65#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:12:47.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:12:47.65#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:12:47.65#ibcon#*before write, iclass 16, count 0 2006.257.15:12:47.65#ibcon#enter sib2, iclass 16, count 0 2006.257.15:12:47.65#ibcon#flushed, iclass 16, count 0 2006.257.15:12:47.65#ibcon#about to write, iclass 16, count 0 2006.257.15:12:47.65#ibcon#wrote, iclass 16, count 0 2006.257.15:12:47.65#ibcon#about to read 3, iclass 16, count 0 2006.257.15:12:47.69#ibcon#read 3, iclass 16, count 0 2006.257.15:12:47.69#ibcon#about to read 4, iclass 16, count 0 2006.257.15:12:47.69#ibcon#read 4, iclass 16, count 0 2006.257.15:12:47.69#ibcon#about to read 5, iclass 16, count 0 2006.257.15:12:47.69#ibcon#read 5, iclass 16, count 0 2006.257.15:12:47.69#ibcon#about to read 6, iclass 16, count 0 2006.257.15:12:47.69#ibcon#read 6, iclass 16, count 0 2006.257.15:12:47.69#ibcon#end of sib2, iclass 16, count 0 2006.257.15:12:47.69#ibcon#*after write, iclass 16, count 0 2006.257.15:12:47.69#ibcon#*before return 0, iclass 16, count 0 2006.257.15:12:47.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:47.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:47.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:12:47.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:12:47.69$vck44/va=2,7 2006.257.15:12:47.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.15:12:47.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.15:12:47.69#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:47.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:47.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:47.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:47.75#ibcon#enter wrdev, iclass 18, count 2 2006.257.15:12:47.75#ibcon#first serial, iclass 18, count 2 2006.257.15:12:47.75#ibcon#enter sib2, iclass 18, count 2 2006.257.15:12:47.75#ibcon#flushed, iclass 18, count 2 2006.257.15:12:47.75#ibcon#about to write, iclass 18, count 2 2006.257.15:12:47.75#ibcon#wrote, iclass 18, count 2 2006.257.15:12:47.75#ibcon#about to read 3, iclass 18, count 2 2006.257.15:12:47.77#ibcon#read 3, iclass 18, count 2 2006.257.15:12:47.77#ibcon#about to read 4, iclass 18, count 2 2006.257.15:12:47.77#ibcon#read 4, iclass 18, count 2 2006.257.15:12:47.77#ibcon#about to read 5, iclass 18, count 2 2006.257.15:12:47.77#ibcon#read 5, iclass 18, count 2 2006.257.15:12:47.77#ibcon#about to read 6, iclass 18, count 2 2006.257.15:12:47.77#ibcon#read 6, iclass 18, count 2 2006.257.15:12:47.77#ibcon#end of sib2, iclass 18, count 2 2006.257.15:12:47.77#ibcon#*mode == 0, iclass 18, count 2 2006.257.15:12:47.77#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.15:12:47.77#ibcon#[25=AT02-07\r\n] 2006.257.15:12:47.77#ibcon#*before write, iclass 18, count 2 2006.257.15:12:47.77#ibcon#enter sib2, iclass 18, count 2 2006.257.15:12:47.77#ibcon#flushed, iclass 18, count 2 2006.257.15:12:47.77#ibcon#about to write, iclass 18, count 2 2006.257.15:12:47.77#ibcon#wrote, iclass 18, count 2 2006.257.15:12:47.77#ibcon#about to read 3, iclass 18, count 2 2006.257.15:12:47.80#ibcon#read 3, iclass 18, count 2 2006.257.15:12:47.80#ibcon#about to read 4, iclass 18, count 2 2006.257.15:12:47.80#ibcon#read 4, iclass 18, count 2 2006.257.15:12:47.80#ibcon#about to read 5, iclass 18, count 2 2006.257.15:12:47.80#ibcon#read 5, iclass 18, count 2 2006.257.15:12:47.80#ibcon#about to read 6, iclass 18, count 2 2006.257.15:12:47.80#ibcon#read 6, iclass 18, count 2 2006.257.15:12:47.80#ibcon#end of sib2, iclass 18, count 2 2006.257.15:12:47.80#ibcon#*after write, iclass 18, count 2 2006.257.15:12:47.80#ibcon#*before return 0, iclass 18, count 2 2006.257.15:12:47.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:47.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:47.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.15:12:47.80#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:47.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:47.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:47.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:47.92#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:12:47.92#ibcon#first serial, iclass 18, count 0 2006.257.15:12:47.92#ibcon#enter sib2, iclass 18, count 0 2006.257.15:12:47.92#ibcon#flushed, iclass 18, count 0 2006.257.15:12:47.92#ibcon#about to write, iclass 18, count 0 2006.257.15:12:47.92#ibcon#wrote, iclass 18, count 0 2006.257.15:12:47.92#ibcon#about to read 3, iclass 18, count 0 2006.257.15:12:47.94#ibcon#read 3, iclass 18, count 0 2006.257.15:12:47.94#ibcon#about to read 4, iclass 18, count 0 2006.257.15:12:47.94#ibcon#read 4, iclass 18, count 0 2006.257.15:12:47.94#ibcon#about to read 5, iclass 18, count 0 2006.257.15:12:47.94#ibcon#read 5, iclass 18, count 0 2006.257.15:12:47.94#ibcon#about to read 6, iclass 18, count 0 2006.257.15:12:47.94#ibcon#read 6, iclass 18, count 0 2006.257.15:12:47.94#ibcon#end of sib2, iclass 18, count 0 2006.257.15:12:47.94#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:12:47.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:12:47.94#ibcon#[25=USB\r\n] 2006.257.15:12:47.94#ibcon#*before write, iclass 18, count 0 2006.257.15:12:47.94#ibcon#enter sib2, iclass 18, count 0 2006.257.15:12:47.94#ibcon#flushed, iclass 18, count 0 2006.257.15:12:47.94#ibcon#about to write, iclass 18, count 0 2006.257.15:12:47.94#ibcon#wrote, iclass 18, count 0 2006.257.15:12:47.94#ibcon#about to read 3, iclass 18, count 0 2006.257.15:12:47.97#ibcon#read 3, iclass 18, count 0 2006.257.15:12:47.97#ibcon#about to read 4, iclass 18, count 0 2006.257.15:12:47.97#ibcon#read 4, iclass 18, count 0 2006.257.15:12:47.97#ibcon#about to read 5, iclass 18, count 0 2006.257.15:12:47.97#ibcon#read 5, iclass 18, count 0 2006.257.15:12:47.97#ibcon#about to read 6, iclass 18, count 0 2006.257.15:12:47.97#ibcon#read 6, iclass 18, count 0 2006.257.15:12:47.97#ibcon#end of sib2, iclass 18, count 0 2006.257.15:12:47.97#ibcon#*after write, iclass 18, count 0 2006.257.15:12:47.97#ibcon#*before return 0, iclass 18, count 0 2006.257.15:12:47.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:47.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:47.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:12:47.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:12:47.97$vck44/valo=3,564.99 2006.257.15:12:47.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.15:12:47.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.15:12:47.97#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:47.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:47.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:47.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:47.97#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:12:47.97#ibcon#first serial, iclass 20, count 0 2006.257.15:12:47.97#ibcon#enter sib2, iclass 20, count 0 2006.257.15:12:47.97#ibcon#flushed, iclass 20, count 0 2006.257.15:12:47.97#ibcon#about to write, iclass 20, count 0 2006.257.15:12:47.97#ibcon#wrote, iclass 20, count 0 2006.257.15:12:47.97#ibcon#about to read 3, iclass 20, count 0 2006.257.15:12:47.99#ibcon#read 3, iclass 20, count 0 2006.257.15:12:47.99#ibcon#about to read 4, iclass 20, count 0 2006.257.15:12:47.99#ibcon#read 4, iclass 20, count 0 2006.257.15:12:47.99#ibcon#about to read 5, iclass 20, count 0 2006.257.15:12:47.99#ibcon#read 5, iclass 20, count 0 2006.257.15:12:47.99#ibcon#about to read 6, iclass 20, count 0 2006.257.15:12:47.99#ibcon#read 6, iclass 20, count 0 2006.257.15:12:47.99#ibcon#end of sib2, iclass 20, count 0 2006.257.15:12:47.99#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:12:47.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:12:47.99#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:12:47.99#ibcon#*before write, iclass 20, count 0 2006.257.15:12:47.99#ibcon#enter sib2, iclass 20, count 0 2006.257.15:12:47.99#ibcon#flushed, iclass 20, count 0 2006.257.15:12:47.99#ibcon#about to write, iclass 20, count 0 2006.257.15:12:47.99#ibcon#wrote, iclass 20, count 0 2006.257.15:12:47.99#ibcon#about to read 3, iclass 20, count 0 2006.257.15:12:48.03#ibcon#read 3, iclass 20, count 0 2006.257.15:12:48.03#ibcon#about to read 4, iclass 20, count 0 2006.257.15:12:48.03#ibcon#read 4, iclass 20, count 0 2006.257.15:12:48.03#ibcon#about to read 5, iclass 20, count 0 2006.257.15:12:48.03#ibcon#read 5, iclass 20, count 0 2006.257.15:12:48.03#ibcon#about to read 6, iclass 20, count 0 2006.257.15:12:48.03#ibcon#read 6, iclass 20, count 0 2006.257.15:12:48.03#ibcon#end of sib2, iclass 20, count 0 2006.257.15:12:48.03#ibcon#*after write, iclass 20, count 0 2006.257.15:12:48.03#ibcon#*before return 0, iclass 20, count 0 2006.257.15:12:48.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:48.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:48.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:12:48.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:12:48.03$vck44/va=3,8 2006.257.15:12:48.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.15:12:48.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.15:12:48.03#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:48.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:48.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:48.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:48.09#ibcon#enter wrdev, iclass 22, count 2 2006.257.15:12:48.09#ibcon#first serial, iclass 22, count 2 2006.257.15:12:48.09#ibcon#enter sib2, iclass 22, count 2 2006.257.15:12:48.09#ibcon#flushed, iclass 22, count 2 2006.257.15:12:48.09#ibcon#about to write, iclass 22, count 2 2006.257.15:12:48.09#ibcon#wrote, iclass 22, count 2 2006.257.15:12:48.09#ibcon#about to read 3, iclass 22, count 2 2006.257.15:12:48.11#ibcon#read 3, iclass 22, count 2 2006.257.15:12:48.11#ibcon#about to read 4, iclass 22, count 2 2006.257.15:12:48.11#ibcon#read 4, iclass 22, count 2 2006.257.15:12:48.11#ibcon#about to read 5, iclass 22, count 2 2006.257.15:12:48.11#ibcon#read 5, iclass 22, count 2 2006.257.15:12:48.11#ibcon#about to read 6, iclass 22, count 2 2006.257.15:12:48.11#ibcon#read 6, iclass 22, count 2 2006.257.15:12:48.11#ibcon#end of sib2, iclass 22, count 2 2006.257.15:12:48.11#ibcon#*mode == 0, iclass 22, count 2 2006.257.15:12:48.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.15:12:48.11#ibcon#[25=AT03-08\r\n] 2006.257.15:12:48.11#ibcon#*before write, iclass 22, count 2 2006.257.15:12:48.11#ibcon#enter sib2, iclass 22, count 2 2006.257.15:12:48.11#ibcon#flushed, iclass 22, count 2 2006.257.15:12:48.11#ibcon#about to write, iclass 22, count 2 2006.257.15:12:48.11#ibcon#wrote, iclass 22, count 2 2006.257.15:12:48.11#ibcon#about to read 3, iclass 22, count 2 2006.257.15:12:48.14#ibcon#read 3, iclass 22, count 2 2006.257.15:12:48.14#ibcon#about to read 4, iclass 22, count 2 2006.257.15:12:48.14#ibcon#read 4, iclass 22, count 2 2006.257.15:12:48.14#ibcon#about to read 5, iclass 22, count 2 2006.257.15:12:48.14#ibcon#read 5, iclass 22, count 2 2006.257.15:12:48.14#ibcon#about to read 6, iclass 22, count 2 2006.257.15:12:48.14#ibcon#read 6, iclass 22, count 2 2006.257.15:12:48.14#ibcon#end of sib2, iclass 22, count 2 2006.257.15:12:48.14#ibcon#*after write, iclass 22, count 2 2006.257.15:12:48.14#ibcon#*before return 0, iclass 22, count 2 2006.257.15:12:48.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:48.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:48.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.15:12:48.14#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:48.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:48.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:48.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:48.26#ibcon#enter wrdev, iclass 22, count 0 2006.257.15:12:48.26#ibcon#first serial, iclass 22, count 0 2006.257.15:12:48.26#ibcon#enter sib2, iclass 22, count 0 2006.257.15:12:48.26#ibcon#flushed, iclass 22, count 0 2006.257.15:12:48.26#ibcon#about to write, iclass 22, count 0 2006.257.15:12:48.26#ibcon#wrote, iclass 22, count 0 2006.257.15:12:48.26#ibcon#about to read 3, iclass 22, count 0 2006.257.15:12:48.28#ibcon#read 3, iclass 22, count 0 2006.257.15:12:48.28#ibcon#about to read 4, iclass 22, count 0 2006.257.15:12:48.28#ibcon#read 4, iclass 22, count 0 2006.257.15:12:48.28#ibcon#about to read 5, iclass 22, count 0 2006.257.15:12:48.28#ibcon#read 5, iclass 22, count 0 2006.257.15:12:48.28#ibcon#about to read 6, iclass 22, count 0 2006.257.15:12:48.28#ibcon#read 6, iclass 22, count 0 2006.257.15:12:48.28#ibcon#end of sib2, iclass 22, count 0 2006.257.15:12:48.28#ibcon#*mode == 0, iclass 22, count 0 2006.257.15:12:48.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.15:12:48.28#ibcon#[25=USB\r\n] 2006.257.15:12:48.28#ibcon#*before write, iclass 22, count 0 2006.257.15:12:48.28#ibcon#enter sib2, iclass 22, count 0 2006.257.15:12:48.28#ibcon#flushed, iclass 22, count 0 2006.257.15:12:48.28#ibcon#about to write, iclass 22, count 0 2006.257.15:12:48.28#ibcon#wrote, iclass 22, count 0 2006.257.15:12:48.28#ibcon#about to read 3, iclass 22, count 0 2006.257.15:12:48.31#ibcon#read 3, iclass 22, count 0 2006.257.15:12:48.31#ibcon#about to read 4, iclass 22, count 0 2006.257.15:12:48.31#ibcon#read 4, iclass 22, count 0 2006.257.15:12:48.31#ibcon#about to read 5, iclass 22, count 0 2006.257.15:12:48.31#ibcon#read 5, iclass 22, count 0 2006.257.15:12:48.31#ibcon#about to read 6, iclass 22, count 0 2006.257.15:12:48.31#ibcon#read 6, iclass 22, count 0 2006.257.15:12:48.31#ibcon#end of sib2, iclass 22, count 0 2006.257.15:12:48.31#ibcon#*after write, iclass 22, count 0 2006.257.15:12:48.31#ibcon#*before return 0, iclass 22, count 0 2006.257.15:12:48.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:48.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:48.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.15:12:48.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.15:12:48.31$vck44/valo=4,624.99 2006.257.15:12:48.31#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.15:12:48.31#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.15:12:48.31#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:48.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:48.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:48.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:48.31#ibcon#enter wrdev, iclass 24, count 0 2006.257.15:12:48.31#ibcon#first serial, iclass 24, count 0 2006.257.15:12:48.31#ibcon#enter sib2, iclass 24, count 0 2006.257.15:12:48.31#ibcon#flushed, iclass 24, count 0 2006.257.15:12:48.31#ibcon#about to write, iclass 24, count 0 2006.257.15:12:48.31#ibcon#wrote, iclass 24, count 0 2006.257.15:12:48.31#ibcon#about to read 3, iclass 24, count 0 2006.257.15:12:48.33#ibcon#read 3, iclass 24, count 0 2006.257.15:12:48.33#ibcon#about to read 4, iclass 24, count 0 2006.257.15:12:48.33#ibcon#read 4, iclass 24, count 0 2006.257.15:12:48.33#ibcon#about to read 5, iclass 24, count 0 2006.257.15:12:48.33#ibcon#read 5, iclass 24, count 0 2006.257.15:12:48.33#ibcon#about to read 6, iclass 24, count 0 2006.257.15:12:48.33#ibcon#read 6, iclass 24, count 0 2006.257.15:12:48.33#ibcon#end of sib2, iclass 24, count 0 2006.257.15:12:48.33#ibcon#*mode == 0, iclass 24, count 0 2006.257.15:12:48.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.15:12:48.33#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:12:48.33#ibcon#*before write, iclass 24, count 0 2006.257.15:12:48.33#ibcon#enter sib2, iclass 24, count 0 2006.257.15:12:48.33#ibcon#flushed, iclass 24, count 0 2006.257.15:12:48.33#ibcon#about to write, iclass 24, count 0 2006.257.15:12:48.33#ibcon#wrote, iclass 24, count 0 2006.257.15:12:48.33#ibcon#about to read 3, iclass 24, count 0 2006.257.15:12:48.37#ibcon#read 3, iclass 24, count 0 2006.257.15:12:48.37#ibcon#about to read 4, iclass 24, count 0 2006.257.15:12:48.37#ibcon#read 4, iclass 24, count 0 2006.257.15:12:48.37#ibcon#about to read 5, iclass 24, count 0 2006.257.15:12:48.37#ibcon#read 5, iclass 24, count 0 2006.257.15:12:48.37#ibcon#about to read 6, iclass 24, count 0 2006.257.15:12:48.37#ibcon#read 6, iclass 24, count 0 2006.257.15:12:48.37#ibcon#end of sib2, iclass 24, count 0 2006.257.15:12:48.37#ibcon#*after write, iclass 24, count 0 2006.257.15:12:48.37#ibcon#*before return 0, iclass 24, count 0 2006.257.15:12:48.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:48.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:48.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.15:12:48.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.15:12:48.37$vck44/va=4,7 2006.257.15:12:48.37#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.15:12:48.37#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.15:12:48.37#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:48.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:48.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:48.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:48.43#ibcon#enter wrdev, iclass 26, count 2 2006.257.15:12:48.43#ibcon#first serial, iclass 26, count 2 2006.257.15:12:48.43#ibcon#enter sib2, iclass 26, count 2 2006.257.15:12:48.43#ibcon#flushed, iclass 26, count 2 2006.257.15:12:48.43#ibcon#about to write, iclass 26, count 2 2006.257.15:12:48.43#ibcon#wrote, iclass 26, count 2 2006.257.15:12:48.43#ibcon#about to read 3, iclass 26, count 2 2006.257.15:12:48.45#ibcon#read 3, iclass 26, count 2 2006.257.15:12:48.45#ibcon#about to read 4, iclass 26, count 2 2006.257.15:12:48.45#ibcon#read 4, iclass 26, count 2 2006.257.15:12:48.45#ibcon#about to read 5, iclass 26, count 2 2006.257.15:12:48.45#ibcon#read 5, iclass 26, count 2 2006.257.15:12:48.45#ibcon#about to read 6, iclass 26, count 2 2006.257.15:12:48.45#ibcon#read 6, iclass 26, count 2 2006.257.15:12:48.45#ibcon#end of sib2, iclass 26, count 2 2006.257.15:12:48.45#ibcon#*mode == 0, iclass 26, count 2 2006.257.15:12:48.45#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.15:12:48.45#ibcon#[25=AT04-07\r\n] 2006.257.15:12:48.45#ibcon#*before write, iclass 26, count 2 2006.257.15:12:48.45#ibcon#enter sib2, iclass 26, count 2 2006.257.15:12:48.45#ibcon#flushed, iclass 26, count 2 2006.257.15:12:48.45#ibcon#about to write, iclass 26, count 2 2006.257.15:12:48.45#ibcon#wrote, iclass 26, count 2 2006.257.15:12:48.45#ibcon#about to read 3, iclass 26, count 2 2006.257.15:12:48.48#ibcon#read 3, iclass 26, count 2 2006.257.15:12:48.48#ibcon#about to read 4, iclass 26, count 2 2006.257.15:12:48.48#ibcon#read 4, iclass 26, count 2 2006.257.15:12:48.48#ibcon#about to read 5, iclass 26, count 2 2006.257.15:12:48.48#ibcon#read 5, iclass 26, count 2 2006.257.15:12:48.48#ibcon#about to read 6, iclass 26, count 2 2006.257.15:12:48.48#ibcon#read 6, iclass 26, count 2 2006.257.15:12:48.48#ibcon#end of sib2, iclass 26, count 2 2006.257.15:12:48.48#ibcon#*after write, iclass 26, count 2 2006.257.15:12:48.49#ibcon#*before return 0, iclass 26, count 2 2006.257.15:12:48.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:48.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:48.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.15:12:48.49#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:48.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:48.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:48.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:48.60#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:12:48.60#ibcon#first serial, iclass 26, count 0 2006.257.15:12:48.60#ibcon#enter sib2, iclass 26, count 0 2006.257.15:12:48.60#ibcon#flushed, iclass 26, count 0 2006.257.15:12:48.60#ibcon#about to write, iclass 26, count 0 2006.257.15:12:48.60#ibcon#wrote, iclass 26, count 0 2006.257.15:12:48.60#ibcon#about to read 3, iclass 26, count 0 2006.257.15:12:48.62#ibcon#read 3, iclass 26, count 0 2006.257.15:12:48.62#ibcon#about to read 4, iclass 26, count 0 2006.257.15:12:48.62#ibcon#read 4, iclass 26, count 0 2006.257.15:12:48.62#ibcon#about to read 5, iclass 26, count 0 2006.257.15:12:48.62#ibcon#read 5, iclass 26, count 0 2006.257.15:12:48.62#ibcon#about to read 6, iclass 26, count 0 2006.257.15:12:48.62#ibcon#read 6, iclass 26, count 0 2006.257.15:12:48.62#ibcon#end of sib2, iclass 26, count 0 2006.257.15:12:48.62#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:12:48.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:12:48.62#ibcon#[25=USB\r\n] 2006.257.15:12:48.62#ibcon#*before write, iclass 26, count 0 2006.257.15:12:48.62#ibcon#enter sib2, iclass 26, count 0 2006.257.15:12:48.62#ibcon#flushed, iclass 26, count 0 2006.257.15:12:48.62#ibcon#about to write, iclass 26, count 0 2006.257.15:12:48.62#ibcon#wrote, iclass 26, count 0 2006.257.15:12:48.62#ibcon#about to read 3, iclass 26, count 0 2006.257.15:12:48.65#ibcon#read 3, iclass 26, count 0 2006.257.15:12:48.65#ibcon#about to read 4, iclass 26, count 0 2006.257.15:12:48.65#ibcon#read 4, iclass 26, count 0 2006.257.15:12:48.65#ibcon#about to read 5, iclass 26, count 0 2006.257.15:12:48.65#ibcon#read 5, iclass 26, count 0 2006.257.15:12:48.65#ibcon#about to read 6, iclass 26, count 0 2006.257.15:12:48.65#ibcon#read 6, iclass 26, count 0 2006.257.15:12:48.65#ibcon#end of sib2, iclass 26, count 0 2006.257.15:12:48.65#ibcon#*after write, iclass 26, count 0 2006.257.15:12:48.65#ibcon#*before return 0, iclass 26, count 0 2006.257.15:12:48.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:48.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:48.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:12:48.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:12:48.65$vck44/valo=5,734.99 2006.257.15:12:48.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.15:12:48.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.15:12:48.65#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:48.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:48.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:48.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:48.65#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:12:48.65#ibcon#first serial, iclass 28, count 0 2006.257.15:12:48.65#ibcon#enter sib2, iclass 28, count 0 2006.257.15:12:48.65#ibcon#flushed, iclass 28, count 0 2006.257.15:12:48.65#ibcon#about to write, iclass 28, count 0 2006.257.15:12:48.65#ibcon#wrote, iclass 28, count 0 2006.257.15:12:48.65#ibcon#about to read 3, iclass 28, count 0 2006.257.15:12:48.67#ibcon#read 3, iclass 28, count 0 2006.257.15:12:48.67#ibcon#about to read 4, iclass 28, count 0 2006.257.15:12:48.67#ibcon#read 4, iclass 28, count 0 2006.257.15:12:48.67#ibcon#about to read 5, iclass 28, count 0 2006.257.15:12:48.67#ibcon#read 5, iclass 28, count 0 2006.257.15:12:48.67#ibcon#about to read 6, iclass 28, count 0 2006.257.15:12:48.67#ibcon#read 6, iclass 28, count 0 2006.257.15:12:48.67#ibcon#end of sib2, iclass 28, count 0 2006.257.15:12:48.67#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:12:48.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:12:48.67#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:12:48.67#ibcon#*before write, iclass 28, count 0 2006.257.15:12:48.67#ibcon#enter sib2, iclass 28, count 0 2006.257.15:12:48.67#ibcon#flushed, iclass 28, count 0 2006.257.15:12:48.67#ibcon#about to write, iclass 28, count 0 2006.257.15:12:48.67#ibcon#wrote, iclass 28, count 0 2006.257.15:12:48.67#ibcon#about to read 3, iclass 28, count 0 2006.257.15:12:48.71#ibcon#read 3, iclass 28, count 0 2006.257.15:12:48.71#ibcon#about to read 4, iclass 28, count 0 2006.257.15:12:48.71#ibcon#read 4, iclass 28, count 0 2006.257.15:12:48.71#ibcon#about to read 5, iclass 28, count 0 2006.257.15:12:48.71#ibcon#read 5, iclass 28, count 0 2006.257.15:12:48.71#ibcon#about to read 6, iclass 28, count 0 2006.257.15:12:48.71#ibcon#read 6, iclass 28, count 0 2006.257.15:12:48.71#ibcon#end of sib2, iclass 28, count 0 2006.257.15:12:48.71#ibcon#*after write, iclass 28, count 0 2006.257.15:12:48.71#ibcon#*before return 0, iclass 28, count 0 2006.257.15:12:48.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:48.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:48.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:12:48.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:12:48.71$vck44/va=5,4 2006.257.15:12:48.71#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.15:12:48.71#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.15:12:48.71#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:48.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:48.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:48.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:48.77#ibcon#enter wrdev, iclass 30, count 2 2006.257.15:12:48.77#ibcon#first serial, iclass 30, count 2 2006.257.15:12:48.77#ibcon#enter sib2, iclass 30, count 2 2006.257.15:12:48.77#ibcon#flushed, iclass 30, count 2 2006.257.15:12:48.77#ibcon#about to write, iclass 30, count 2 2006.257.15:12:48.77#ibcon#wrote, iclass 30, count 2 2006.257.15:12:48.77#ibcon#about to read 3, iclass 30, count 2 2006.257.15:12:48.79#ibcon#read 3, iclass 30, count 2 2006.257.15:12:48.79#ibcon#about to read 4, iclass 30, count 2 2006.257.15:12:48.79#ibcon#read 4, iclass 30, count 2 2006.257.15:12:48.79#ibcon#about to read 5, iclass 30, count 2 2006.257.15:12:48.79#ibcon#read 5, iclass 30, count 2 2006.257.15:12:48.79#ibcon#about to read 6, iclass 30, count 2 2006.257.15:12:48.79#ibcon#read 6, iclass 30, count 2 2006.257.15:12:48.79#ibcon#end of sib2, iclass 30, count 2 2006.257.15:12:48.79#ibcon#*mode == 0, iclass 30, count 2 2006.257.15:12:48.79#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.15:12:48.79#ibcon#[25=AT05-04\r\n] 2006.257.15:12:48.79#ibcon#*before write, iclass 30, count 2 2006.257.15:12:48.79#ibcon#enter sib2, iclass 30, count 2 2006.257.15:12:48.79#ibcon#flushed, iclass 30, count 2 2006.257.15:12:48.79#ibcon#about to write, iclass 30, count 2 2006.257.15:12:48.79#ibcon#wrote, iclass 30, count 2 2006.257.15:12:48.79#ibcon#about to read 3, iclass 30, count 2 2006.257.15:12:48.82#ibcon#read 3, iclass 30, count 2 2006.257.15:12:48.82#ibcon#about to read 4, iclass 30, count 2 2006.257.15:12:48.82#ibcon#read 4, iclass 30, count 2 2006.257.15:12:48.82#ibcon#about to read 5, iclass 30, count 2 2006.257.15:12:48.82#ibcon#read 5, iclass 30, count 2 2006.257.15:12:48.82#ibcon#about to read 6, iclass 30, count 2 2006.257.15:12:48.82#ibcon#read 6, iclass 30, count 2 2006.257.15:12:48.82#ibcon#end of sib2, iclass 30, count 2 2006.257.15:12:48.82#ibcon#*after write, iclass 30, count 2 2006.257.15:12:48.82#ibcon#*before return 0, iclass 30, count 2 2006.257.15:12:48.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:48.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:48.82#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.15:12:48.82#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:48.82#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:48.94#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:48.94#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:48.94#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:12:48.94#ibcon#first serial, iclass 30, count 0 2006.257.15:12:48.94#ibcon#enter sib2, iclass 30, count 0 2006.257.15:12:48.94#ibcon#flushed, iclass 30, count 0 2006.257.15:12:48.94#ibcon#about to write, iclass 30, count 0 2006.257.15:12:48.94#ibcon#wrote, iclass 30, count 0 2006.257.15:12:48.94#ibcon#about to read 3, iclass 30, count 0 2006.257.15:12:48.96#ibcon#read 3, iclass 30, count 0 2006.257.15:12:48.96#ibcon#about to read 4, iclass 30, count 0 2006.257.15:12:48.96#ibcon#read 4, iclass 30, count 0 2006.257.15:12:48.96#ibcon#about to read 5, iclass 30, count 0 2006.257.15:12:48.96#ibcon#read 5, iclass 30, count 0 2006.257.15:12:48.96#ibcon#about to read 6, iclass 30, count 0 2006.257.15:12:48.96#ibcon#read 6, iclass 30, count 0 2006.257.15:12:48.96#ibcon#end of sib2, iclass 30, count 0 2006.257.15:12:48.96#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:12:48.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:12:48.96#ibcon#[25=USB\r\n] 2006.257.15:12:48.96#ibcon#*before write, iclass 30, count 0 2006.257.15:12:48.96#ibcon#enter sib2, iclass 30, count 0 2006.257.15:12:48.96#ibcon#flushed, iclass 30, count 0 2006.257.15:12:48.96#ibcon#about to write, iclass 30, count 0 2006.257.15:12:48.96#ibcon#wrote, iclass 30, count 0 2006.257.15:12:48.96#ibcon#about to read 3, iclass 30, count 0 2006.257.15:12:48.99#ibcon#read 3, iclass 30, count 0 2006.257.15:12:48.99#ibcon#about to read 4, iclass 30, count 0 2006.257.15:12:48.99#ibcon#read 4, iclass 30, count 0 2006.257.15:12:48.99#ibcon#about to read 5, iclass 30, count 0 2006.257.15:12:48.99#ibcon#read 5, iclass 30, count 0 2006.257.15:12:48.99#ibcon#about to read 6, iclass 30, count 0 2006.257.15:12:48.99#ibcon#read 6, iclass 30, count 0 2006.257.15:12:48.99#ibcon#end of sib2, iclass 30, count 0 2006.257.15:12:48.99#ibcon#*after write, iclass 30, count 0 2006.257.15:12:48.99#ibcon#*before return 0, iclass 30, count 0 2006.257.15:12:48.99#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:48.99#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:48.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:12:48.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:12:48.99$vck44/valo=6,814.99 2006.257.15:12:48.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.15:12:48.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.15:12:48.99#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:48.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:48.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:48.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:48.99#ibcon#enter wrdev, iclass 32, count 0 2006.257.15:12:48.99#ibcon#first serial, iclass 32, count 0 2006.257.15:12:48.99#ibcon#enter sib2, iclass 32, count 0 2006.257.15:12:48.99#ibcon#flushed, iclass 32, count 0 2006.257.15:12:48.99#ibcon#about to write, iclass 32, count 0 2006.257.15:12:48.99#ibcon#wrote, iclass 32, count 0 2006.257.15:12:48.99#ibcon#about to read 3, iclass 32, count 0 2006.257.15:12:49.01#ibcon#read 3, iclass 32, count 0 2006.257.15:12:49.01#ibcon#about to read 4, iclass 32, count 0 2006.257.15:12:49.01#ibcon#read 4, iclass 32, count 0 2006.257.15:12:49.01#ibcon#about to read 5, iclass 32, count 0 2006.257.15:12:49.01#ibcon#read 5, iclass 32, count 0 2006.257.15:12:49.01#ibcon#about to read 6, iclass 32, count 0 2006.257.15:12:49.01#ibcon#read 6, iclass 32, count 0 2006.257.15:12:49.01#ibcon#end of sib2, iclass 32, count 0 2006.257.15:12:49.01#ibcon#*mode == 0, iclass 32, count 0 2006.257.15:12:49.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.15:12:49.01#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:12:49.01#ibcon#*before write, iclass 32, count 0 2006.257.15:12:49.01#ibcon#enter sib2, iclass 32, count 0 2006.257.15:12:49.01#ibcon#flushed, iclass 32, count 0 2006.257.15:12:49.01#ibcon#about to write, iclass 32, count 0 2006.257.15:12:49.01#ibcon#wrote, iclass 32, count 0 2006.257.15:12:49.01#ibcon#about to read 3, iclass 32, count 0 2006.257.15:12:49.05#ibcon#read 3, iclass 32, count 0 2006.257.15:12:49.05#ibcon#about to read 4, iclass 32, count 0 2006.257.15:12:49.05#ibcon#read 4, iclass 32, count 0 2006.257.15:12:49.05#ibcon#about to read 5, iclass 32, count 0 2006.257.15:12:49.05#ibcon#read 5, iclass 32, count 0 2006.257.15:12:49.05#ibcon#about to read 6, iclass 32, count 0 2006.257.15:12:49.05#ibcon#read 6, iclass 32, count 0 2006.257.15:12:49.05#ibcon#end of sib2, iclass 32, count 0 2006.257.15:12:49.05#ibcon#*after write, iclass 32, count 0 2006.257.15:12:49.05#ibcon#*before return 0, iclass 32, count 0 2006.257.15:12:49.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:49.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:49.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.15:12:49.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.15:12:49.05$vck44/va=6,4 2006.257.15:12:49.05#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.15:12:49.05#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.15:12:49.05#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:49.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:49.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:49.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:49.11#ibcon#enter wrdev, iclass 34, count 2 2006.257.15:12:49.11#ibcon#first serial, iclass 34, count 2 2006.257.15:12:49.11#ibcon#enter sib2, iclass 34, count 2 2006.257.15:12:49.11#ibcon#flushed, iclass 34, count 2 2006.257.15:12:49.11#ibcon#about to write, iclass 34, count 2 2006.257.15:12:49.11#ibcon#wrote, iclass 34, count 2 2006.257.15:12:49.11#ibcon#about to read 3, iclass 34, count 2 2006.257.15:12:49.13#ibcon#read 3, iclass 34, count 2 2006.257.15:12:49.13#ibcon#about to read 4, iclass 34, count 2 2006.257.15:12:49.13#ibcon#read 4, iclass 34, count 2 2006.257.15:12:49.13#ibcon#about to read 5, iclass 34, count 2 2006.257.15:12:49.13#ibcon#read 5, iclass 34, count 2 2006.257.15:12:49.13#ibcon#about to read 6, iclass 34, count 2 2006.257.15:12:49.13#ibcon#read 6, iclass 34, count 2 2006.257.15:12:49.13#ibcon#end of sib2, iclass 34, count 2 2006.257.15:12:49.13#ibcon#*mode == 0, iclass 34, count 2 2006.257.15:12:49.13#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.15:12:49.13#ibcon#[25=AT06-04\r\n] 2006.257.15:12:49.13#ibcon#*before write, iclass 34, count 2 2006.257.15:12:49.13#ibcon#enter sib2, iclass 34, count 2 2006.257.15:12:49.13#ibcon#flushed, iclass 34, count 2 2006.257.15:12:49.13#ibcon#about to write, iclass 34, count 2 2006.257.15:12:49.13#ibcon#wrote, iclass 34, count 2 2006.257.15:12:49.13#ibcon#about to read 3, iclass 34, count 2 2006.257.15:12:49.16#ibcon#read 3, iclass 34, count 2 2006.257.15:12:49.16#ibcon#about to read 4, iclass 34, count 2 2006.257.15:12:49.16#ibcon#read 4, iclass 34, count 2 2006.257.15:12:49.16#ibcon#about to read 5, iclass 34, count 2 2006.257.15:12:49.16#ibcon#read 5, iclass 34, count 2 2006.257.15:12:49.16#ibcon#about to read 6, iclass 34, count 2 2006.257.15:12:49.16#ibcon#read 6, iclass 34, count 2 2006.257.15:12:49.16#ibcon#end of sib2, iclass 34, count 2 2006.257.15:12:49.16#ibcon#*after write, iclass 34, count 2 2006.257.15:12:49.16#ibcon#*before return 0, iclass 34, count 2 2006.257.15:12:49.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:49.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:49.16#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.15:12:49.16#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:49.16#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:49.28#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:49.28#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:49.28#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:12:49.28#ibcon#first serial, iclass 34, count 0 2006.257.15:12:49.28#ibcon#enter sib2, iclass 34, count 0 2006.257.15:12:49.28#ibcon#flushed, iclass 34, count 0 2006.257.15:12:49.28#ibcon#about to write, iclass 34, count 0 2006.257.15:12:49.28#ibcon#wrote, iclass 34, count 0 2006.257.15:12:49.28#ibcon#about to read 3, iclass 34, count 0 2006.257.15:12:49.30#ibcon#read 3, iclass 34, count 0 2006.257.15:12:49.30#ibcon#about to read 4, iclass 34, count 0 2006.257.15:12:49.30#ibcon#read 4, iclass 34, count 0 2006.257.15:12:49.30#ibcon#about to read 5, iclass 34, count 0 2006.257.15:12:49.30#ibcon#read 5, iclass 34, count 0 2006.257.15:12:49.30#ibcon#about to read 6, iclass 34, count 0 2006.257.15:12:49.30#ibcon#read 6, iclass 34, count 0 2006.257.15:12:49.30#ibcon#end of sib2, iclass 34, count 0 2006.257.15:12:49.30#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:12:49.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:12:49.30#ibcon#[25=USB\r\n] 2006.257.15:12:49.30#ibcon#*before write, iclass 34, count 0 2006.257.15:12:49.30#ibcon#enter sib2, iclass 34, count 0 2006.257.15:12:49.30#ibcon#flushed, iclass 34, count 0 2006.257.15:12:49.30#ibcon#about to write, iclass 34, count 0 2006.257.15:12:49.30#ibcon#wrote, iclass 34, count 0 2006.257.15:12:49.30#ibcon#about to read 3, iclass 34, count 0 2006.257.15:12:49.33#ibcon#read 3, iclass 34, count 0 2006.257.15:12:49.33#ibcon#about to read 4, iclass 34, count 0 2006.257.15:12:49.33#ibcon#read 4, iclass 34, count 0 2006.257.15:12:49.33#ibcon#about to read 5, iclass 34, count 0 2006.257.15:12:49.33#ibcon#read 5, iclass 34, count 0 2006.257.15:12:49.33#ibcon#about to read 6, iclass 34, count 0 2006.257.15:12:49.33#ibcon#read 6, iclass 34, count 0 2006.257.15:12:49.33#ibcon#end of sib2, iclass 34, count 0 2006.257.15:12:49.33#ibcon#*after write, iclass 34, count 0 2006.257.15:12:49.33#ibcon#*before return 0, iclass 34, count 0 2006.257.15:12:49.33#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:49.33#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:49.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:12:49.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:12:49.33$vck44/valo=7,864.99 2006.257.15:12:49.33#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.15:12:49.33#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.15:12:49.33#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:49.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:49.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:49.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:49.33#ibcon#enter wrdev, iclass 36, count 0 2006.257.15:12:49.33#ibcon#first serial, iclass 36, count 0 2006.257.15:12:49.33#ibcon#enter sib2, iclass 36, count 0 2006.257.15:12:49.33#ibcon#flushed, iclass 36, count 0 2006.257.15:12:49.33#ibcon#about to write, iclass 36, count 0 2006.257.15:12:49.33#ibcon#wrote, iclass 36, count 0 2006.257.15:12:49.33#ibcon#about to read 3, iclass 36, count 0 2006.257.15:12:49.35#ibcon#read 3, iclass 36, count 0 2006.257.15:12:49.35#ibcon#about to read 4, iclass 36, count 0 2006.257.15:12:49.35#ibcon#read 4, iclass 36, count 0 2006.257.15:12:49.35#ibcon#about to read 5, iclass 36, count 0 2006.257.15:12:49.35#ibcon#read 5, iclass 36, count 0 2006.257.15:12:49.35#ibcon#about to read 6, iclass 36, count 0 2006.257.15:12:49.35#ibcon#read 6, iclass 36, count 0 2006.257.15:12:49.35#ibcon#end of sib2, iclass 36, count 0 2006.257.15:12:49.35#ibcon#*mode == 0, iclass 36, count 0 2006.257.15:12:49.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.15:12:49.35#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:12:49.35#ibcon#*before write, iclass 36, count 0 2006.257.15:12:49.35#ibcon#enter sib2, iclass 36, count 0 2006.257.15:12:49.35#ibcon#flushed, iclass 36, count 0 2006.257.15:12:49.35#ibcon#about to write, iclass 36, count 0 2006.257.15:12:49.35#ibcon#wrote, iclass 36, count 0 2006.257.15:12:49.35#ibcon#about to read 3, iclass 36, count 0 2006.257.15:12:49.39#ibcon#read 3, iclass 36, count 0 2006.257.15:12:49.39#ibcon#about to read 4, iclass 36, count 0 2006.257.15:12:49.39#ibcon#read 4, iclass 36, count 0 2006.257.15:12:49.39#ibcon#about to read 5, iclass 36, count 0 2006.257.15:12:49.39#ibcon#read 5, iclass 36, count 0 2006.257.15:12:49.39#ibcon#about to read 6, iclass 36, count 0 2006.257.15:12:49.39#ibcon#read 6, iclass 36, count 0 2006.257.15:12:49.39#ibcon#end of sib2, iclass 36, count 0 2006.257.15:12:49.39#ibcon#*after write, iclass 36, count 0 2006.257.15:12:49.39#ibcon#*before return 0, iclass 36, count 0 2006.257.15:12:49.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:49.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:49.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.15:12:49.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.15:12:49.39$vck44/va=7,4 2006.257.15:12:49.39#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.15:12:49.39#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.15:12:49.39#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:49.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:49.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:49.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:49.45#ibcon#enter wrdev, iclass 38, count 2 2006.257.15:12:49.45#ibcon#first serial, iclass 38, count 2 2006.257.15:12:49.45#ibcon#enter sib2, iclass 38, count 2 2006.257.15:12:49.45#ibcon#flushed, iclass 38, count 2 2006.257.15:12:49.45#ibcon#about to write, iclass 38, count 2 2006.257.15:12:49.45#ibcon#wrote, iclass 38, count 2 2006.257.15:12:49.45#ibcon#about to read 3, iclass 38, count 2 2006.257.15:12:49.47#ibcon#read 3, iclass 38, count 2 2006.257.15:12:49.47#ibcon#about to read 4, iclass 38, count 2 2006.257.15:12:49.47#ibcon#read 4, iclass 38, count 2 2006.257.15:12:49.47#ibcon#about to read 5, iclass 38, count 2 2006.257.15:12:49.47#ibcon#read 5, iclass 38, count 2 2006.257.15:12:49.47#ibcon#about to read 6, iclass 38, count 2 2006.257.15:12:49.47#ibcon#read 6, iclass 38, count 2 2006.257.15:12:49.47#ibcon#end of sib2, iclass 38, count 2 2006.257.15:12:49.47#ibcon#*mode == 0, iclass 38, count 2 2006.257.15:12:49.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.15:12:49.47#ibcon#[25=AT07-04\r\n] 2006.257.15:12:49.47#ibcon#*before write, iclass 38, count 2 2006.257.15:12:49.47#ibcon#enter sib2, iclass 38, count 2 2006.257.15:12:49.47#ibcon#flushed, iclass 38, count 2 2006.257.15:12:49.47#ibcon#about to write, iclass 38, count 2 2006.257.15:12:49.47#ibcon#wrote, iclass 38, count 2 2006.257.15:12:49.47#ibcon#about to read 3, iclass 38, count 2 2006.257.15:12:49.50#ibcon#read 3, iclass 38, count 2 2006.257.15:12:49.50#ibcon#about to read 4, iclass 38, count 2 2006.257.15:12:49.50#ibcon#read 4, iclass 38, count 2 2006.257.15:12:49.50#ibcon#about to read 5, iclass 38, count 2 2006.257.15:12:49.50#ibcon#read 5, iclass 38, count 2 2006.257.15:12:49.50#ibcon#about to read 6, iclass 38, count 2 2006.257.15:12:49.50#ibcon#read 6, iclass 38, count 2 2006.257.15:12:49.50#ibcon#end of sib2, iclass 38, count 2 2006.257.15:12:49.50#ibcon#*after write, iclass 38, count 2 2006.257.15:12:49.55#ibcon#*before return 0, iclass 38, count 2 2006.257.15:12:49.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:49.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:49.55#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.15:12:49.55#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:49.55#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:49.66#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:49.66#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:49.66#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:12:49.66#ibcon#first serial, iclass 38, count 0 2006.257.15:12:49.66#ibcon#enter sib2, iclass 38, count 0 2006.257.15:12:49.66#ibcon#flushed, iclass 38, count 0 2006.257.15:12:49.66#ibcon#about to write, iclass 38, count 0 2006.257.15:12:49.66#ibcon#wrote, iclass 38, count 0 2006.257.15:12:49.66#ibcon#about to read 3, iclass 38, count 0 2006.257.15:12:49.68#ibcon#read 3, iclass 38, count 0 2006.257.15:12:49.68#ibcon#about to read 4, iclass 38, count 0 2006.257.15:12:49.68#ibcon#read 4, iclass 38, count 0 2006.257.15:12:49.68#ibcon#about to read 5, iclass 38, count 0 2006.257.15:12:49.68#ibcon#read 5, iclass 38, count 0 2006.257.15:12:49.68#ibcon#about to read 6, iclass 38, count 0 2006.257.15:12:49.68#ibcon#read 6, iclass 38, count 0 2006.257.15:12:49.68#ibcon#end of sib2, iclass 38, count 0 2006.257.15:12:49.68#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:12:49.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:12:49.68#ibcon#[25=USB\r\n] 2006.257.15:12:49.68#ibcon#*before write, iclass 38, count 0 2006.257.15:12:49.68#ibcon#enter sib2, iclass 38, count 0 2006.257.15:12:49.68#ibcon#flushed, iclass 38, count 0 2006.257.15:12:49.68#ibcon#about to write, iclass 38, count 0 2006.257.15:12:49.68#ibcon#wrote, iclass 38, count 0 2006.257.15:12:49.68#ibcon#about to read 3, iclass 38, count 0 2006.257.15:12:49.71#ibcon#read 3, iclass 38, count 0 2006.257.15:12:49.71#ibcon#about to read 4, iclass 38, count 0 2006.257.15:12:49.71#ibcon#read 4, iclass 38, count 0 2006.257.15:12:49.71#ibcon#about to read 5, iclass 38, count 0 2006.257.15:12:49.71#ibcon#read 5, iclass 38, count 0 2006.257.15:12:49.71#ibcon#about to read 6, iclass 38, count 0 2006.257.15:12:49.71#ibcon#read 6, iclass 38, count 0 2006.257.15:12:49.71#ibcon#end of sib2, iclass 38, count 0 2006.257.15:12:49.71#ibcon#*after write, iclass 38, count 0 2006.257.15:12:49.71#ibcon#*before return 0, iclass 38, count 0 2006.257.15:12:49.71#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:49.71#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:49.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:12:49.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:12:49.71$vck44/valo=8,884.99 2006.257.15:12:49.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.15:12:49.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.15:12:49.71#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:49.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:49.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:49.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:49.71#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:12:49.71#ibcon#first serial, iclass 40, count 0 2006.257.15:12:49.71#ibcon#enter sib2, iclass 40, count 0 2006.257.15:12:49.71#ibcon#flushed, iclass 40, count 0 2006.257.15:12:49.71#ibcon#about to write, iclass 40, count 0 2006.257.15:12:49.71#ibcon#wrote, iclass 40, count 0 2006.257.15:12:49.71#ibcon#about to read 3, iclass 40, count 0 2006.257.15:12:49.73#ibcon#read 3, iclass 40, count 0 2006.257.15:12:49.73#ibcon#about to read 4, iclass 40, count 0 2006.257.15:12:49.73#ibcon#read 4, iclass 40, count 0 2006.257.15:12:49.73#ibcon#about to read 5, iclass 40, count 0 2006.257.15:12:49.73#ibcon#read 5, iclass 40, count 0 2006.257.15:12:49.73#ibcon#about to read 6, iclass 40, count 0 2006.257.15:12:49.73#ibcon#read 6, iclass 40, count 0 2006.257.15:12:49.73#ibcon#end of sib2, iclass 40, count 0 2006.257.15:12:49.73#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:12:49.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:12:49.73#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:12:49.73#ibcon#*before write, iclass 40, count 0 2006.257.15:12:49.73#ibcon#enter sib2, iclass 40, count 0 2006.257.15:12:49.73#ibcon#flushed, iclass 40, count 0 2006.257.15:12:49.73#ibcon#about to write, iclass 40, count 0 2006.257.15:12:49.73#ibcon#wrote, iclass 40, count 0 2006.257.15:12:49.73#ibcon#about to read 3, iclass 40, count 0 2006.257.15:12:49.77#ibcon#read 3, iclass 40, count 0 2006.257.15:12:49.77#ibcon#about to read 4, iclass 40, count 0 2006.257.15:12:49.77#ibcon#read 4, iclass 40, count 0 2006.257.15:12:49.77#ibcon#about to read 5, iclass 40, count 0 2006.257.15:12:49.77#ibcon#read 5, iclass 40, count 0 2006.257.15:12:49.77#ibcon#about to read 6, iclass 40, count 0 2006.257.15:12:49.77#ibcon#read 6, iclass 40, count 0 2006.257.15:12:49.77#ibcon#end of sib2, iclass 40, count 0 2006.257.15:12:49.77#ibcon#*after write, iclass 40, count 0 2006.257.15:12:49.77#ibcon#*before return 0, iclass 40, count 0 2006.257.15:12:49.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:49.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:49.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:12:49.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:12:49.77$vck44/va=8,4 2006.257.15:12:49.77#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.15:12:49.77#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.15:12:49.77#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:49.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:12:49.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:12:49.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:12:49.83#ibcon#enter wrdev, iclass 4, count 2 2006.257.15:12:49.83#ibcon#first serial, iclass 4, count 2 2006.257.15:12:49.83#ibcon#enter sib2, iclass 4, count 2 2006.257.15:12:49.83#ibcon#flushed, iclass 4, count 2 2006.257.15:12:49.83#ibcon#about to write, iclass 4, count 2 2006.257.15:12:49.83#ibcon#wrote, iclass 4, count 2 2006.257.15:12:49.83#ibcon#about to read 3, iclass 4, count 2 2006.257.15:12:49.85#ibcon#read 3, iclass 4, count 2 2006.257.15:12:49.85#ibcon#about to read 4, iclass 4, count 2 2006.257.15:12:49.85#ibcon#read 4, iclass 4, count 2 2006.257.15:12:49.85#ibcon#about to read 5, iclass 4, count 2 2006.257.15:12:49.85#ibcon#read 5, iclass 4, count 2 2006.257.15:12:49.85#ibcon#about to read 6, iclass 4, count 2 2006.257.15:12:49.85#ibcon#read 6, iclass 4, count 2 2006.257.15:12:49.85#ibcon#end of sib2, iclass 4, count 2 2006.257.15:12:49.85#ibcon#*mode == 0, iclass 4, count 2 2006.257.15:12:49.85#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.15:12:49.85#ibcon#[25=AT08-04\r\n] 2006.257.15:12:49.85#ibcon#*before write, iclass 4, count 2 2006.257.15:12:49.85#ibcon#enter sib2, iclass 4, count 2 2006.257.15:12:49.85#ibcon#flushed, iclass 4, count 2 2006.257.15:12:49.85#ibcon#about to write, iclass 4, count 2 2006.257.15:12:49.85#ibcon#wrote, iclass 4, count 2 2006.257.15:12:49.85#ibcon#about to read 3, iclass 4, count 2 2006.257.15:12:49.88#ibcon#read 3, iclass 4, count 2 2006.257.15:12:49.88#ibcon#about to read 4, iclass 4, count 2 2006.257.15:12:49.88#ibcon#read 4, iclass 4, count 2 2006.257.15:12:49.88#ibcon#about to read 5, iclass 4, count 2 2006.257.15:12:49.88#ibcon#read 5, iclass 4, count 2 2006.257.15:12:49.88#ibcon#about to read 6, iclass 4, count 2 2006.257.15:12:49.88#ibcon#read 6, iclass 4, count 2 2006.257.15:12:49.88#ibcon#end of sib2, iclass 4, count 2 2006.257.15:12:49.88#ibcon#*after write, iclass 4, count 2 2006.257.15:12:49.88#ibcon#*before return 0, iclass 4, count 2 2006.257.15:12:49.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:12:49.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:12:49.88#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.15:12:49.88#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:49.88#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:12:50.00#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:12:50.00#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:12:50.00#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:12:50.00#ibcon#first serial, iclass 4, count 0 2006.257.15:12:50.00#ibcon#enter sib2, iclass 4, count 0 2006.257.15:12:50.00#ibcon#flushed, iclass 4, count 0 2006.257.15:12:50.00#ibcon#about to write, iclass 4, count 0 2006.257.15:12:50.00#ibcon#wrote, iclass 4, count 0 2006.257.15:12:50.00#ibcon#about to read 3, iclass 4, count 0 2006.257.15:12:50.02#ibcon#read 3, iclass 4, count 0 2006.257.15:12:50.02#ibcon#about to read 4, iclass 4, count 0 2006.257.15:12:50.02#ibcon#read 4, iclass 4, count 0 2006.257.15:12:50.02#ibcon#about to read 5, iclass 4, count 0 2006.257.15:12:50.02#ibcon#read 5, iclass 4, count 0 2006.257.15:12:50.02#ibcon#about to read 6, iclass 4, count 0 2006.257.15:12:50.02#ibcon#read 6, iclass 4, count 0 2006.257.15:12:50.02#ibcon#end of sib2, iclass 4, count 0 2006.257.15:12:50.02#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:12:50.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:12:50.02#ibcon#[25=USB\r\n] 2006.257.15:12:50.02#ibcon#*before write, iclass 4, count 0 2006.257.15:12:50.02#ibcon#enter sib2, iclass 4, count 0 2006.257.15:12:50.02#ibcon#flushed, iclass 4, count 0 2006.257.15:12:50.02#ibcon#about to write, iclass 4, count 0 2006.257.15:12:50.02#ibcon#wrote, iclass 4, count 0 2006.257.15:12:50.02#ibcon#about to read 3, iclass 4, count 0 2006.257.15:12:50.05#ibcon#read 3, iclass 4, count 0 2006.257.15:12:50.05#ibcon#about to read 4, iclass 4, count 0 2006.257.15:12:50.05#ibcon#read 4, iclass 4, count 0 2006.257.15:12:50.05#ibcon#about to read 5, iclass 4, count 0 2006.257.15:12:50.05#ibcon#read 5, iclass 4, count 0 2006.257.15:12:50.05#ibcon#about to read 6, iclass 4, count 0 2006.257.15:12:50.05#ibcon#read 6, iclass 4, count 0 2006.257.15:12:50.05#ibcon#end of sib2, iclass 4, count 0 2006.257.15:12:50.05#ibcon#*after write, iclass 4, count 0 2006.257.15:12:50.05#ibcon#*before return 0, iclass 4, count 0 2006.257.15:12:50.05#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:12:50.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:12:50.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:12:50.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:12:50.05$vck44/vblo=1,629.99 2006.257.15:12:50.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.15:12:50.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.15:12:50.05#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:50.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:12:50.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:12:50.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:12:50.05#ibcon#enter wrdev, iclass 6, count 0 2006.257.15:12:50.05#ibcon#first serial, iclass 6, count 0 2006.257.15:12:50.05#ibcon#enter sib2, iclass 6, count 0 2006.257.15:12:50.05#ibcon#flushed, iclass 6, count 0 2006.257.15:12:50.05#ibcon#about to write, iclass 6, count 0 2006.257.15:12:50.05#ibcon#wrote, iclass 6, count 0 2006.257.15:12:50.05#ibcon#about to read 3, iclass 6, count 0 2006.257.15:12:50.07#ibcon#read 3, iclass 6, count 0 2006.257.15:12:50.07#ibcon#about to read 4, iclass 6, count 0 2006.257.15:12:50.07#ibcon#read 4, iclass 6, count 0 2006.257.15:12:50.07#ibcon#about to read 5, iclass 6, count 0 2006.257.15:12:50.07#ibcon#read 5, iclass 6, count 0 2006.257.15:12:50.07#ibcon#about to read 6, iclass 6, count 0 2006.257.15:12:50.07#ibcon#read 6, iclass 6, count 0 2006.257.15:12:50.07#ibcon#end of sib2, iclass 6, count 0 2006.257.15:12:50.07#ibcon#*mode == 0, iclass 6, count 0 2006.257.15:12:50.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.15:12:50.07#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:12:50.07#ibcon#*before write, iclass 6, count 0 2006.257.15:12:50.07#ibcon#enter sib2, iclass 6, count 0 2006.257.15:12:50.07#ibcon#flushed, iclass 6, count 0 2006.257.15:12:50.07#ibcon#about to write, iclass 6, count 0 2006.257.15:12:50.07#ibcon#wrote, iclass 6, count 0 2006.257.15:12:50.07#ibcon#about to read 3, iclass 6, count 0 2006.257.15:12:50.11#ibcon#read 3, iclass 6, count 0 2006.257.15:12:50.11#ibcon#about to read 4, iclass 6, count 0 2006.257.15:12:50.11#ibcon#read 4, iclass 6, count 0 2006.257.15:12:50.11#ibcon#about to read 5, iclass 6, count 0 2006.257.15:12:50.11#ibcon#read 5, iclass 6, count 0 2006.257.15:12:50.11#ibcon#about to read 6, iclass 6, count 0 2006.257.15:12:50.11#ibcon#read 6, iclass 6, count 0 2006.257.15:12:50.11#ibcon#end of sib2, iclass 6, count 0 2006.257.15:12:50.11#ibcon#*after write, iclass 6, count 0 2006.257.15:12:50.11#ibcon#*before return 0, iclass 6, count 0 2006.257.15:12:50.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:12:50.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:12:50.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.15:12:50.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.15:12:50.11$vck44/vb=1,4 2006.257.15:12:50.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.15:12:50.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.15:12:50.11#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:50.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:12:50.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:12:50.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:12:50.11#ibcon#enter wrdev, iclass 10, count 2 2006.257.15:12:50.11#ibcon#first serial, iclass 10, count 2 2006.257.15:12:50.11#ibcon#enter sib2, iclass 10, count 2 2006.257.15:12:50.11#ibcon#flushed, iclass 10, count 2 2006.257.15:12:50.11#ibcon#about to write, iclass 10, count 2 2006.257.15:12:50.11#ibcon#wrote, iclass 10, count 2 2006.257.15:12:50.11#ibcon#about to read 3, iclass 10, count 2 2006.257.15:12:50.13#ibcon#read 3, iclass 10, count 2 2006.257.15:12:50.13#ibcon#about to read 4, iclass 10, count 2 2006.257.15:12:50.13#ibcon#read 4, iclass 10, count 2 2006.257.15:12:50.13#ibcon#about to read 5, iclass 10, count 2 2006.257.15:12:50.13#ibcon#read 5, iclass 10, count 2 2006.257.15:12:50.13#ibcon#about to read 6, iclass 10, count 2 2006.257.15:12:50.13#ibcon#read 6, iclass 10, count 2 2006.257.15:12:50.13#ibcon#end of sib2, iclass 10, count 2 2006.257.15:12:50.13#ibcon#*mode == 0, iclass 10, count 2 2006.257.15:12:50.13#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.15:12:50.13#ibcon#[27=AT01-04\r\n] 2006.257.15:12:50.13#ibcon#*before write, iclass 10, count 2 2006.257.15:12:50.13#ibcon#enter sib2, iclass 10, count 2 2006.257.15:12:50.13#ibcon#flushed, iclass 10, count 2 2006.257.15:12:50.13#ibcon#about to write, iclass 10, count 2 2006.257.15:12:50.13#ibcon#wrote, iclass 10, count 2 2006.257.15:12:50.13#ibcon#about to read 3, iclass 10, count 2 2006.257.15:12:50.16#ibcon#read 3, iclass 10, count 2 2006.257.15:12:50.16#ibcon#about to read 4, iclass 10, count 2 2006.257.15:12:50.16#ibcon#read 4, iclass 10, count 2 2006.257.15:12:50.16#ibcon#about to read 5, iclass 10, count 2 2006.257.15:12:50.16#ibcon#read 5, iclass 10, count 2 2006.257.15:12:50.16#ibcon#about to read 6, iclass 10, count 2 2006.257.15:12:50.16#ibcon#read 6, iclass 10, count 2 2006.257.15:12:50.16#ibcon#end of sib2, iclass 10, count 2 2006.257.15:12:50.16#ibcon#*after write, iclass 10, count 2 2006.257.15:12:50.16#ibcon#*before return 0, iclass 10, count 2 2006.257.15:12:50.16#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:12:50.16#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:12:50.16#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.15:12:50.16#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:50.16#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:12:50.28#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:12:50.28#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:12:50.28#ibcon#enter wrdev, iclass 10, count 0 2006.257.15:12:50.28#ibcon#first serial, iclass 10, count 0 2006.257.15:12:50.28#ibcon#enter sib2, iclass 10, count 0 2006.257.15:12:50.28#ibcon#flushed, iclass 10, count 0 2006.257.15:12:50.28#ibcon#about to write, iclass 10, count 0 2006.257.15:12:50.28#ibcon#wrote, iclass 10, count 0 2006.257.15:12:50.28#ibcon#about to read 3, iclass 10, count 0 2006.257.15:12:50.30#ibcon#read 3, iclass 10, count 0 2006.257.15:12:50.30#ibcon#about to read 4, iclass 10, count 0 2006.257.15:12:50.30#ibcon#read 4, iclass 10, count 0 2006.257.15:12:50.30#ibcon#about to read 5, iclass 10, count 0 2006.257.15:12:50.30#ibcon#read 5, iclass 10, count 0 2006.257.15:12:50.30#ibcon#about to read 6, iclass 10, count 0 2006.257.15:12:50.30#ibcon#read 6, iclass 10, count 0 2006.257.15:12:50.30#ibcon#end of sib2, iclass 10, count 0 2006.257.15:12:50.30#ibcon#*mode == 0, iclass 10, count 0 2006.257.15:12:50.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.15:12:50.30#ibcon#[27=USB\r\n] 2006.257.15:12:50.30#ibcon#*before write, iclass 10, count 0 2006.257.15:12:50.30#ibcon#enter sib2, iclass 10, count 0 2006.257.15:12:50.30#ibcon#flushed, iclass 10, count 0 2006.257.15:12:50.30#ibcon#about to write, iclass 10, count 0 2006.257.15:12:50.30#ibcon#wrote, iclass 10, count 0 2006.257.15:12:50.30#ibcon#about to read 3, iclass 10, count 0 2006.257.15:12:50.33#ibcon#read 3, iclass 10, count 0 2006.257.15:12:50.33#ibcon#about to read 4, iclass 10, count 0 2006.257.15:12:50.33#ibcon#read 4, iclass 10, count 0 2006.257.15:12:50.33#ibcon#about to read 5, iclass 10, count 0 2006.257.15:12:50.33#ibcon#read 5, iclass 10, count 0 2006.257.15:12:50.33#ibcon#about to read 6, iclass 10, count 0 2006.257.15:12:50.33#ibcon#read 6, iclass 10, count 0 2006.257.15:12:50.33#ibcon#end of sib2, iclass 10, count 0 2006.257.15:12:50.33#ibcon#*after write, iclass 10, count 0 2006.257.15:12:50.33#ibcon#*before return 0, iclass 10, count 0 2006.257.15:12:50.33#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:12:50.33#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:12:50.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.15:12:50.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.15:12:50.33$vck44/vblo=2,634.99 2006.257.15:12:50.33#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.15:12:50.33#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.15:12:50.33#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:50.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:50.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:50.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:50.33#ibcon#enter wrdev, iclass 12, count 0 2006.257.15:12:50.33#ibcon#first serial, iclass 12, count 0 2006.257.15:12:50.33#ibcon#enter sib2, iclass 12, count 0 2006.257.15:12:50.33#ibcon#flushed, iclass 12, count 0 2006.257.15:12:50.33#ibcon#about to write, iclass 12, count 0 2006.257.15:12:50.33#ibcon#wrote, iclass 12, count 0 2006.257.15:12:50.33#ibcon#about to read 3, iclass 12, count 0 2006.257.15:12:50.35#ibcon#read 3, iclass 12, count 0 2006.257.15:12:50.35#ibcon#about to read 4, iclass 12, count 0 2006.257.15:12:50.35#ibcon#read 4, iclass 12, count 0 2006.257.15:12:50.35#ibcon#about to read 5, iclass 12, count 0 2006.257.15:12:50.35#ibcon#read 5, iclass 12, count 0 2006.257.15:12:50.35#ibcon#about to read 6, iclass 12, count 0 2006.257.15:12:50.35#ibcon#read 6, iclass 12, count 0 2006.257.15:12:50.35#ibcon#end of sib2, iclass 12, count 0 2006.257.15:12:50.35#ibcon#*mode == 0, iclass 12, count 0 2006.257.15:12:50.35#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.15:12:50.35#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:12:50.35#ibcon#*before write, iclass 12, count 0 2006.257.15:12:50.35#ibcon#enter sib2, iclass 12, count 0 2006.257.15:12:50.35#ibcon#flushed, iclass 12, count 0 2006.257.15:12:50.35#ibcon#about to write, iclass 12, count 0 2006.257.15:12:50.35#ibcon#wrote, iclass 12, count 0 2006.257.15:12:50.35#ibcon#about to read 3, iclass 12, count 0 2006.257.15:12:50.39#ibcon#read 3, iclass 12, count 0 2006.257.15:12:50.39#ibcon#about to read 4, iclass 12, count 0 2006.257.15:12:50.39#ibcon#read 4, iclass 12, count 0 2006.257.15:12:50.39#ibcon#about to read 5, iclass 12, count 0 2006.257.15:12:50.39#ibcon#read 5, iclass 12, count 0 2006.257.15:12:50.39#ibcon#about to read 6, iclass 12, count 0 2006.257.15:12:50.39#ibcon#read 6, iclass 12, count 0 2006.257.15:12:50.39#ibcon#end of sib2, iclass 12, count 0 2006.257.15:12:50.39#ibcon#*after write, iclass 12, count 0 2006.257.15:12:50.39#ibcon#*before return 0, iclass 12, count 0 2006.257.15:12:50.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:50.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:12:50.39#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.15:12:50.39#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.15:12:50.39$vck44/vb=2,5 2006.257.15:12:50.39#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.15:12:50.39#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.15:12:50.39#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:50.39#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:50.45#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:50.45#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:50.45#ibcon#enter wrdev, iclass 14, count 2 2006.257.15:12:50.45#ibcon#first serial, iclass 14, count 2 2006.257.15:12:50.45#ibcon#enter sib2, iclass 14, count 2 2006.257.15:12:50.45#ibcon#flushed, iclass 14, count 2 2006.257.15:12:50.45#ibcon#about to write, iclass 14, count 2 2006.257.15:12:50.45#ibcon#wrote, iclass 14, count 2 2006.257.15:12:50.45#ibcon#about to read 3, iclass 14, count 2 2006.257.15:12:50.47#ibcon#read 3, iclass 14, count 2 2006.257.15:12:50.47#ibcon#about to read 4, iclass 14, count 2 2006.257.15:12:50.47#ibcon#read 4, iclass 14, count 2 2006.257.15:12:50.47#ibcon#about to read 5, iclass 14, count 2 2006.257.15:12:50.47#ibcon#read 5, iclass 14, count 2 2006.257.15:12:50.47#ibcon#about to read 6, iclass 14, count 2 2006.257.15:12:50.47#ibcon#read 6, iclass 14, count 2 2006.257.15:12:50.47#ibcon#end of sib2, iclass 14, count 2 2006.257.15:12:50.47#ibcon#*mode == 0, iclass 14, count 2 2006.257.15:12:50.47#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.15:12:50.47#ibcon#[27=AT02-05\r\n] 2006.257.15:12:50.47#ibcon#*before write, iclass 14, count 2 2006.257.15:12:50.47#ibcon#enter sib2, iclass 14, count 2 2006.257.15:12:50.47#ibcon#flushed, iclass 14, count 2 2006.257.15:12:50.47#ibcon#about to write, iclass 14, count 2 2006.257.15:12:50.47#ibcon#wrote, iclass 14, count 2 2006.257.15:12:50.47#ibcon#about to read 3, iclass 14, count 2 2006.257.15:12:50.50#ibcon#read 3, iclass 14, count 2 2006.257.15:12:50.50#ibcon#about to read 4, iclass 14, count 2 2006.257.15:12:50.55#ibcon#read 4, iclass 14, count 2 2006.257.15:12:50.55#ibcon#about to read 5, iclass 14, count 2 2006.257.15:12:50.55#ibcon#read 5, iclass 14, count 2 2006.257.15:12:50.55#ibcon#about to read 6, iclass 14, count 2 2006.257.15:12:50.55#ibcon#read 6, iclass 14, count 2 2006.257.15:12:50.55#ibcon#end of sib2, iclass 14, count 2 2006.257.15:12:50.55#ibcon#*after write, iclass 14, count 2 2006.257.15:12:50.55#ibcon#*before return 0, iclass 14, count 2 2006.257.15:12:50.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:50.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:12:50.55#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.15:12:50.55#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:50.55#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:50.66#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:50.66#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:50.66#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:12:50.66#ibcon#first serial, iclass 14, count 0 2006.257.15:12:50.66#ibcon#enter sib2, iclass 14, count 0 2006.257.15:12:50.66#ibcon#flushed, iclass 14, count 0 2006.257.15:12:50.66#ibcon#about to write, iclass 14, count 0 2006.257.15:12:50.66#ibcon#wrote, iclass 14, count 0 2006.257.15:12:50.66#ibcon#about to read 3, iclass 14, count 0 2006.257.15:12:50.68#ibcon#read 3, iclass 14, count 0 2006.257.15:12:50.68#ibcon#about to read 4, iclass 14, count 0 2006.257.15:12:50.68#ibcon#read 4, iclass 14, count 0 2006.257.15:12:50.68#ibcon#about to read 5, iclass 14, count 0 2006.257.15:12:50.68#ibcon#read 5, iclass 14, count 0 2006.257.15:12:50.68#ibcon#about to read 6, iclass 14, count 0 2006.257.15:12:50.68#ibcon#read 6, iclass 14, count 0 2006.257.15:12:50.68#ibcon#end of sib2, iclass 14, count 0 2006.257.15:12:50.68#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:12:50.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:12:50.68#ibcon#[27=USB\r\n] 2006.257.15:12:50.68#ibcon#*before write, iclass 14, count 0 2006.257.15:12:50.68#ibcon#enter sib2, iclass 14, count 0 2006.257.15:12:50.68#ibcon#flushed, iclass 14, count 0 2006.257.15:12:50.68#ibcon#about to write, iclass 14, count 0 2006.257.15:12:50.68#ibcon#wrote, iclass 14, count 0 2006.257.15:12:50.68#ibcon#about to read 3, iclass 14, count 0 2006.257.15:12:50.71#ibcon#read 3, iclass 14, count 0 2006.257.15:12:50.71#ibcon#about to read 4, iclass 14, count 0 2006.257.15:12:50.71#ibcon#read 4, iclass 14, count 0 2006.257.15:12:50.71#ibcon#about to read 5, iclass 14, count 0 2006.257.15:12:50.71#ibcon#read 5, iclass 14, count 0 2006.257.15:12:50.71#ibcon#about to read 6, iclass 14, count 0 2006.257.15:12:50.71#ibcon#read 6, iclass 14, count 0 2006.257.15:12:50.71#ibcon#end of sib2, iclass 14, count 0 2006.257.15:12:50.71#ibcon#*after write, iclass 14, count 0 2006.257.15:12:50.71#ibcon#*before return 0, iclass 14, count 0 2006.257.15:12:50.71#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:50.71#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:12:50.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:12:50.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:12:50.71$vck44/vblo=3,649.99 2006.257.15:12:50.71#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.15:12:50.71#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.15:12:50.71#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:50.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:50.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:50.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:50.71#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:12:50.71#ibcon#first serial, iclass 16, count 0 2006.257.15:12:50.71#ibcon#enter sib2, iclass 16, count 0 2006.257.15:12:50.71#ibcon#flushed, iclass 16, count 0 2006.257.15:12:50.71#ibcon#about to write, iclass 16, count 0 2006.257.15:12:50.71#ibcon#wrote, iclass 16, count 0 2006.257.15:12:50.71#ibcon#about to read 3, iclass 16, count 0 2006.257.15:12:50.73#ibcon#read 3, iclass 16, count 0 2006.257.15:12:50.73#ibcon#about to read 4, iclass 16, count 0 2006.257.15:12:50.73#ibcon#read 4, iclass 16, count 0 2006.257.15:12:50.73#ibcon#about to read 5, iclass 16, count 0 2006.257.15:12:50.73#ibcon#read 5, iclass 16, count 0 2006.257.15:12:50.73#ibcon#about to read 6, iclass 16, count 0 2006.257.15:12:50.73#ibcon#read 6, iclass 16, count 0 2006.257.15:12:50.73#ibcon#end of sib2, iclass 16, count 0 2006.257.15:12:50.73#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:12:50.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:12:50.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:12:50.73#ibcon#*before write, iclass 16, count 0 2006.257.15:12:50.73#ibcon#enter sib2, iclass 16, count 0 2006.257.15:12:50.73#ibcon#flushed, iclass 16, count 0 2006.257.15:12:50.73#ibcon#about to write, iclass 16, count 0 2006.257.15:12:50.73#ibcon#wrote, iclass 16, count 0 2006.257.15:12:50.73#ibcon#about to read 3, iclass 16, count 0 2006.257.15:12:50.77#ibcon#read 3, iclass 16, count 0 2006.257.15:12:50.77#ibcon#about to read 4, iclass 16, count 0 2006.257.15:12:50.77#ibcon#read 4, iclass 16, count 0 2006.257.15:12:50.77#ibcon#about to read 5, iclass 16, count 0 2006.257.15:12:50.77#ibcon#read 5, iclass 16, count 0 2006.257.15:12:50.77#ibcon#about to read 6, iclass 16, count 0 2006.257.15:12:50.77#ibcon#read 6, iclass 16, count 0 2006.257.15:12:50.77#ibcon#end of sib2, iclass 16, count 0 2006.257.15:12:50.77#ibcon#*after write, iclass 16, count 0 2006.257.15:12:50.77#ibcon#*before return 0, iclass 16, count 0 2006.257.15:12:50.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:50.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:12:50.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:12:50.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:12:50.77$vck44/vb=3,4 2006.257.15:12:50.77#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.15:12:50.77#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.15:12:50.77#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:50.77#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:50.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:50.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:50.83#ibcon#enter wrdev, iclass 18, count 2 2006.257.15:12:50.83#ibcon#first serial, iclass 18, count 2 2006.257.15:12:50.83#ibcon#enter sib2, iclass 18, count 2 2006.257.15:12:50.83#ibcon#flushed, iclass 18, count 2 2006.257.15:12:50.83#ibcon#about to write, iclass 18, count 2 2006.257.15:12:50.83#ibcon#wrote, iclass 18, count 2 2006.257.15:12:50.83#ibcon#about to read 3, iclass 18, count 2 2006.257.15:12:50.85#ibcon#read 3, iclass 18, count 2 2006.257.15:12:50.85#ibcon#about to read 4, iclass 18, count 2 2006.257.15:12:50.85#ibcon#read 4, iclass 18, count 2 2006.257.15:12:50.85#ibcon#about to read 5, iclass 18, count 2 2006.257.15:12:50.85#ibcon#read 5, iclass 18, count 2 2006.257.15:12:50.85#ibcon#about to read 6, iclass 18, count 2 2006.257.15:12:50.85#ibcon#read 6, iclass 18, count 2 2006.257.15:12:50.85#ibcon#end of sib2, iclass 18, count 2 2006.257.15:12:50.85#ibcon#*mode == 0, iclass 18, count 2 2006.257.15:12:50.85#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.15:12:50.85#ibcon#[27=AT03-04\r\n] 2006.257.15:12:50.85#ibcon#*before write, iclass 18, count 2 2006.257.15:12:50.85#ibcon#enter sib2, iclass 18, count 2 2006.257.15:12:50.85#ibcon#flushed, iclass 18, count 2 2006.257.15:12:50.85#ibcon#about to write, iclass 18, count 2 2006.257.15:12:50.85#ibcon#wrote, iclass 18, count 2 2006.257.15:12:50.85#ibcon#about to read 3, iclass 18, count 2 2006.257.15:12:50.88#ibcon#read 3, iclass 18, count 2 2006.257.15:12:50.88#ibcon#about to read 4, iclass 18, count 2 2006.257.15:12:50.88#ibcon#read 4, iclass 18, count 2 2006.257.15:12:50.88#ibcon#about to read 5, iclass 18, count 2 2006.257.15:12:50.88#ibcon#read 5, iclass 18, count 2 2006.257.15:12:50.88#ibcon#about to read 6, iclass 18, count 2 2006.257.15:12:50.88#ibcon#read 6, iclass 18, count 2 2006.257.15:12:50.88#ibcon#end of sib2, iclass 18, count 2 2006.257.15:12:50.88#ibcon#*after write, iclass 18, count 2 2006.257.15:12:50.88#ibcon#*before return 0, iclass 18, count 2 2006.257.15:12:50.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:50.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:12:50.88#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.15:12:50.88#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:50.88#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:51.00#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:51.00#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:51.00#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:12:51.00#ibcon#first serial, iclass 18, count 0 2006.257.15:12:51.00#ibcon#enter sib2, iclass 18, count 0 2006.257.15:12:51.00#ibcon#flushed, iclass 18, count 0 2006.257.15:12:51.00#ibcon#about to write, iclass 18, count 0 2006.257.15:12:51.00#ibcon#wrote, iclass 18, count 0 2006.257.15:12:51.00#ibcon#about to read 3, iclass 18, count 0 2006.257.15:12:51.02#ibcon#read 3, iclass 18, count 0 2006.257.15:12:51.02#ibcon#about to read 4, iclass 18, count 0 2006.257.15:12:51.02#ibcon#read 4, iclass 18, count 0 2006.257.15:12:51.02#ibcon#about to read 5, iclass 18, count 0 2006.257.15:12:51.02#ibcon#read 5, iclass 18, count 0 2006.257.15:12:51.02#ibcon#about to read 6, iclass 18, count 0 2006.257.15:12:51.02#ibcon#read 6, iclass 18, count 0 2006.257.15:12:51.02#ibcon#end of sib2, iclass 18, count 0 2006.257.15:12:51.02#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:12:51.02#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:12:51.02#ibcon#[27=USB\r\n] 2006.257.15:12:51.02#ibcon#*before write, iclass 18, count 0 2006.257.15:12:51.02#ibcon#enter sib2, iclass 18, count 0 2006.257.15:12:51.02#ibcon#flushed, iclass 18, count 0 2006.257.15:12:51.02#ibcon#about to write, iclass 18, count 0 2006.257.15:12:51.02#ibcon#wrote, iclass 18, count 0 2006.257.15:12:51.02#ibcon#about to read 3, iclass 18, count 0 2006.257.15:12:51.05#ibcon#read 3, iclass 18, count 0 2006.257.15:12:51.05#ibcon#about to read 4, iclass 18, count 0 2006.257.15:12:51.05#ibcon#read 4, iclass 18, count 0 2006.257.15:12:51.05#ibcon#about to read 5, iclass 18, count 0 2006.257.15:12:51.05#ibcon#read 5, iclass 18, count 0 2006.257.15:12:51.05#ibcon#about to read 6, iclass 18, count 0 2006.257.15:12:51.05#ibcon#read 6, iclass 18, count 0 2006.257.15:12:51.05#ibcon#end of sib2, iclass 18, count 0 2006.257.15:12:51.05#ibcon#*after write, iclass 18, count 0 2006.257.15:12:51.05#ibcon#*before return 0, iclass 18, count 0 2006.257.15:12:51.05#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:51.05#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:12:51.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:12:51.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:12:51.05$vck44/vblo=4,679.99 2006.257.15:12:51.05#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.15:12:51.05#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.15:12:51.05#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:51.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:51.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:51.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:51.05#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:12:51.05#ibcon#first serial, iclass 20, count 0 2006.257.15:12:51.05#ibcon#enter sib2, iclass 20, count 0 2006.257.15:12:51.05#ibcon#flushed, iclass 20, count 0 2006.257.15:12:51.05#ibcon#about to write, iclass 20, count 0 2006.257.15:12:51.05#ibcon#wrote, iclass 20, count 0 2006.257.15:12:51.05#ibcon#about to read 3, iclass 20, count 0 2006.257.15:12:51.07#ibcon#read 3, iclass 20, count 0 2006.257.15:12:51.07#ibcon#about to read 4, iclass 20, count 0 2006.257.15:12:51.07#ibcon#read 4, iclass 20, count 0 2006.257.15:12:51.07#ibcon#about to read 5, iclass 20, count 0 2006.257.15:12:51.07#ibcon#read 5, iclass 20, count 0 2006.257.15:12:51.07#ibcon#about to read 6, iclass 20, count 0 2006.257.15:12:51.07#ibcon#read 6, iclass 20, count 0 2006.257.15:12:51.07#ibcon#end of sib2, iclass 20, count 0 2006.257.15:12:51.07#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:12:51.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:12:51.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:12:51.07#ibcon#*before write, iclass 20, count 0 2006.257.15:12:51.07#ibcon#enter sib2, iclass 20, count 0 2006.257.15:12:51.07#ibcon#flushed, iclass 20, count 0 2006.257.15:12:51.07#ibcon#about to write, iclass 20, count 0 2006.257.15:12:51.07#ibcon#wrote, iclass 20, count 0 2006.257.15:12:51.07#ibcon#about to read 3, iclass 20, count 0 2006.257.15:12:51.11#ibcon#read 3, iclass 20, count 0 2006.257.15:12:51.11#ibcon#about to read 4, iclass 20, count 0 2006.257.15:12:51.11#ibcon#read 4, iclass 20, count 0 2006.257.15:12:51.11#ibcon#about to read 5, iclass 20, count 0 2006.257.15:12:51.11#ibcon#read 5, iclass 20, count 0 2006.257.15:12:51.11#ibcon#about to read 6, iclass 20, count 0 2006.257.15:12:51.11#ibcon#read 6, iclass 20, count 0 2006.257.15:12:51.11#ibcon#end of sib2, iclass 20, count 0 2006.257.15:12:51.11#ibcon#*after write, iclass 20, count 0 2006.257.15:12:51.11#ibcon#*before return 0, iclass 20, count 0 2006.257.15:12:51.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:51.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:12:51.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:12:51.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:12:51.11$vck44/vb=4,5 2006.257.15:12:51.11#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.15:12:51.11#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.15:12:51.11#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:51.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:51.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:51.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:51.17#ibcon#enter wrdev, iclass 22, count 2 2006.257.15:12:51.17#ibcon#first serial, iclass 22, count 2 2006.257.15:12:51.17#ibcon#enter sib2, iclass 22, count 2 2006.257.15:12:51.17#ibcon#flushed, iclass 22, count 2 2006.257.15:12:51.17#ibcon#about to write, iclass 22, count 2 2006.257.15:12:51.17#ibcon#wrote, iclass 22, count 2 2006.257.15:12:51.17#ibcon#about to read 3, iclass 22, count 2 2006.257.15:12:51.19#ibcon#read 3, iclass 22, count 2 2006.257.15:12:51.19#ibcon#about to read 4, iclass 22, count 2 2006.257.15:12:51.19#ibcon#read 4, iclass 22, count 2 2006.257.15:12:51.19#ibcon#about to read 5, iclass 22, count 2 2006.257.15:12:51.19#ibcon#read 5, iclass 22, count 2 2006.257.15:12:51.19#ibcon#about to read 6, iclass 22, count 2 2006.257.15:12:51.19#ibcon#read 6, iclass 22, count 2 2006.257.15:12:51.19#ibcon#end of sib2, iclass 22, count 2 2006.257.15:12:51.19#ibcon#*mode == 0, iclass 22, count 2 2006.257.15:12:51.19#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.15:12:51.19#ibcon#[27=AT04-05\r\n] 2006.257.15:12:51.19#ibcon#*before write, iclass 22, count 2 2006.257.15:12:51.19#ibcon#enter sib2, iclass 22, count 2 2006.257.15:12:51.19#ibcon#flushed, iclass 22, count 2 2006.257.15:12:51.19#ibcon#about to write, iclass 22, count 2 2006.257.15:12:51.19#ibcon#wrote, iclass 22, count 2 2006.257.15:12:51.19#ibcon#about to read 3, iclass 22, count 2 2006.257.15:12:51.22#ibcon#read 3, iclass 22, count 2 2006.257.15:12:51.22#ibcon#about to read 4, iclass 22, count 2 2006.257.15:12:51.22#ibcon#read 4, iclass 22, count 2 2006.257.15:12:51.22#ibcon#about to read 5, iclass 22, count 2 2006.257.15:12:51.22#ibcon#read 5, iclass 22, count 2 2006.257.15:12:51.22#ibcon#about to read 6, iclass 22, count 2 2006.257.15:12:51.22#ibcon#read 6, iclass 22, count 2 2006.257.15:12:51.22#ibcon#end of sib2, iclass 22, count 2 2006.257.15:12:51.22#ibcon#*after write, iclass 22, count 2 2006.257.15:12:51.22#ibcon#*before return 0, iclass 22, count 2 2006.257.15:12:51.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:51.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:12:51.22#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.15:12:51.22#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:51.22#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:51.34#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:51.34#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:51.34#ibcon#enter wrdev, iclass 22, count 0 2006.257.15:12:51.34#ibcon#first serial, iclass 22, count 0 2006.257.15:12:51.34#ibcon#enter sib2, iclass 22, count 0 2006.257.15:12:51.34#ibcon#flushed, iclass 22, count 0 2006.257.15:12:51.34#ibcon#about to write, iclass 22, count 0 2006.257.15:12:51.34#ibcon#wrote, iclass 22, count 0 2006.257.15:12:51.34#ibcon#about to read 3, iclass 22, count 0 2006.257.15:12:51.36#ibcon#read 3, iclass 22, count 0 2006.257.15:12:51.36#ibcon#about to read 4, iclass 22, count 0 2006.257.15:12:51.36#ibcon#read 4, iclass 22, count 0 2006.257.15:12:51.36#ibcon#about to read 5, iclass 22, count 0 2006.257.15:12:51.36#ibcon#read 5, iclass 22, count 0 2006.257.15:12:51.36#ibcon#about to read 6, iclass 22, count 0 2006.257.15:12:51.36#ibcon#read 6, iclass 22, count 0 2006.257.15:12:51.36#ibcon#end of sib2, iclass 22, count 0 2006.257.15:12:51.36#ibcon#*mode == 0, iclass 22, count 0 2006.257.15:12:51.36#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.15:12:51.36#ibcon#[27=USB\r\n] 2006.257.15:12:51.36#ibcon#*before write, iclass 22, count 0 2006.257.15:12:51.36#ibcon#enter sib2, iclass 22, count 0 2006.257.15:12:51.36#ibcon#flushed, iclass 22, count 0 2006.257.15:12:51.36#ibcon#about to write, iclass 22, count 0 2006.257.15:12:51.36#ibcon#wrote, iclass 22, count 0 2006.257.15:12:51.36#ibcon#about to read 3, iclass 22, count 0 2006.257.15:12:51.39#ibcon#read 3, iclass 22, count 0 2006.257.15:12:51.39#ibcon#about to read 4, iclass 22, count 0 2006.257.15:12:51.39#ibcon#read 4, iclass 22, count 0 2006.257.15:12:51.39#ibcon#about to read 5, iclass 22, count 0 2006.257.15:12:51.39#ibcon#read 5, iclass 22, count 0 2006.257.15:12:51.39#ibcon#about to read 6, iclass 22, count 0 2006.257.15:12:51.39#ibcon#read 6, iclass 22, count 0 2006.257.15:12:51.39#ibcon#end of sib2, iclass 22, count 0 2006.257.15:12:51.39#ibcon#*after write, iclass 22, count 0 2006.257.15:12:51.39#ibcon#*before return 0, iclass 22, count 0 2006.257.15:12:51.39#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:51.39#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:12:51.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.15:12:51.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.15:12:51.39$vck44/vblo=5,709.99 2006.257.15:12:51.39#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.15:12:51.39#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.15:12:51.39#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:51.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:51.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:51.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:51.39#ibcon#enter wrdev, iclass 24, count 0 2006.257.15:12:51.39#ibcon#first serial, iclass 24, count 0 2006.257.15:12:51.39#ibcon#enter sib2, iclass 24, count 0 2006.257.15:12:51.39#ibcon#flushed, iclass 24, count 0 2006.257.15:12:51.39#ibcon#about to write, iclass 24, count 0 2006.257.15:12:51.39#ibcon#wrote, iclass 24, count 0 2006.257.15:12:51.39#ibcon#about to read 3, iclass 24, count 0 2006.257.15:12:51.41#ibcon#read 3, iclass 24, count 0 2006.257.15:12:51.41#ibcon#about to read 4, iclass 24, count 0 2006.257.15:12:51.41#ibcon#read 4, iclass 24, count 0 2006.257.15:12:51.41#ibcon#about to read 5, iclass 24, count 0 2006.257.15:12:51.41#ibcon#read 5, iclass 24, count 0 2006.257.15:12:51.41#ibcon#about to read 6, iclass 24, count 0 2006.257.15:12:51.41#ibcon#read 6, iclass 24, count 0 2006.257.15:12:51.41#ibcon#end of sib2, iclass 24, count 0 2006.257.15:12:51.41#ibcon#*mode == 0, iclass 24, count 0 2006.257.15:12:51.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.15:12:51.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:12:51.41#ibcon#*before write, iclass 24, count 0 2006.257.15:12:51.41#ibcon#enter sib2, iclass 24, count 0 2006.257.15:12:51.41#ibcon#flushed, iclass 24, count 0 2006.257.15:12:51.41#ibcon#about to write, iclass 24, count 0 2006.257.15:12:51.41#ibcon#wrote, iclass 24, count 0 2006.257.15:12:51.41#ibcon#about to read 3, iclass 24, count 0 2006.257.15:12:51.45#ibcon#read 3, iclass 24, count 0 2006.257.15:12:51.45#ibcon#about to read 4, iclass 24, count 0 2006.257.15:12:51.45#ibcon#read 4, iclass 24, count 0 2006.257.15:12:51.45#ibcon#about to read 5, iclass 24, count 0 2006.257.15:12:51.45#ibcon#read 5, iclass 24, count 0 2006.257.15:12:51.45#ibcon#about to read 6, iclass 24, count 0 2006.257.15:12:51.45#ibcon#read 6, iclass 24, count 0 2006.257.15:12:51.45#ibcon#end of sib2, iclass 24, count 0 2006.257.15:12:51.45#ibcon#*after write, iclass 24, count 0 2006.257.15:12:51.45#ibcon#*before return 0, iclass 24, count 0 2006.257.15:12:51.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:51.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:12:51.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.15:12:51.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.15:12:51.45$vck44/vb=5,4 2006.257.15:12:51.45#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.15:12:51.45#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.15:12:51.45#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:51.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:51.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:51.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:51.51#ibcon#enter wrdev, iclass 26, count 2 2006.257.15:12:51.51#ibcon#first serial, iclass 26, count 2 2006.257.15:12:51.51#ibcon#enter sib2, iclass 26, count 2 2006.257.15:12:51.51#ibcon#flushed, iclass 26, count 2 2006.257.15:12:51.51#ibcon#about to write, iclass 26, count 2 2006.257.15:12:51.51#ibcon#wrote, iclass 26, count 2 2006.257.15:12:51.51#ibcon#about to read 3, iclass 26, count 2 2006.257.15:12:51.53#ibcon#read 3, iclass 26, count 2 2006.257.15:12:51.53#ibcon#about to read 4, iclass 26, count 2 2006.257.15:12:51.53#ibcon#read 4, iclass 26, count 2 2006.257.15:12:51.53#ibcon#about to read 5, iclass 26, count 2 2006.257.15:12:51.53#ibcon#read 5, iclass 26, count 2 2006.257.15:12:51.53#ibcon#about to read 6, iclass 26, count 2 2006.257.15:12:51.53#ibcon#read 6, iclass 26, count 2 2006.257.15:12:51.53#ibcon#end of sib2, iclass 26, count 2 2006.257.15:12:51.53#ibcon#*mode == 0, iclass 26, count 2 2006.257.15:12:51.53#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.15:12:51.53#ibcon#[27=AT05-04\r\n] 2006.257.15:12:51.53#ibcon#*before write, iclass 26, count 2 2006.257.15:12:51.53#ibcon#enter sib2, iclass 26, count 2 2006.257.15:12:51.53#ibcon#flushed, iclass 26, count 2 2006.257.15:12:51.53#ibcon#about to write, iclass 26, count 2 2006.257.15:12:51.53#ibcon#wrote, iclass 26, count 2 2006.257.15:12:51.53#ibcon#about to read 3, iclass 26, count 2 2006.257.15:12:51.56#ibcon#read 3, iclass 26, count 2 2006.257.15:12:51.56#ibcon#about to read 4, iclass 26, count 2 2006.257.15:12:51.56#ibcon#read 4, iclass 26, count 2 2006.257.15:12:51.56#ibcon#about to read 5, iclass 26, count 2 2006.257.15:12:51.56#ibcon#read 5, iclass 26, count 2 2006.257.15:12:51.56#ibcon#about to read 6, iclass 26, count 2 2006.257.15:12:51.56#ibcon#read 6, iclass 26, count 2 2006.257.15:12:51.56#ibcon#end of sib2, iclass 26, count 2 2006.257.15:12:51.56#ibcon#*after write, iclass 26, count 2 2006.257.15:12:51.56#ibcon#*before return 0, iclass 26, count 2 2006.257.15:12:51.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:51.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:12:51.56#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.15:12:51.56#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:51.56#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:51.68#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:51.68#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:51.68#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:12:51.68#ibcon#first serial, iclass 26, count 0 2006.257.15:12:51.68#ibcon#enter sib2, iclass 26, count 0 2006.257.15:12:51.68#ibcon#flushed, iclass 26, count 0 2006.257.15:12:51.68#ibcon#about to write, iclass 26, count 0 2006.257.15:12:51.68#ibcon#wrote, iclass 26, count 0 2006.257.15:12:51.68#ibcon#about to read 3, iclass 26, count 0 2006.257.15:12:51.70#ibcon#read 3, iclass 26, count 0 2006.257.15:12:51.70#ibcon#about to read 4, iclass 26, count 0 2006.257.15:12:51.70#ibcon#read 4, iclass 26, count 0 2006.257.15:12:51.70#ibcon#about to read 5, iclass 26, count 0 2006.257.15:12:51.70#ibcon#read 5, iclass 26, count 0 2006.257.15:12:51.70#ibcon#about to read 6, iclass 26, count 0 2006.257.15:12:51.70#ibcon#read 6, iclass 26, count 0 2006.257.15:12:51.70#ibcon#end of sib2, iclass 26, count 0 2006.257.15:12:51.70#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:12:51.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:12:51.70#ibcon#[27=USB\r\n] 2006.257.15:12:51.70#ibcon#*before write, iclass 26, count 0 2006.257.15:12:51.70#ibcon#enter sib2, iclass 26, count 0 2006.257.15:12:51.70#ibcon#flushed, iclass 26, count 0 2006.257.15:12:51.70#ibcon#about to write, iclass 26, count 0 2006.257.15:12:51.70#ibcon#wrote, iclass 26, count 0 2006.257.15:12:51.70#ibcon#about to read 3, iclass 26, count 0 2006.257.15:12:51.73#ibcon#read 3, iclass 26, count 0 2006.257.15:12:51.73#ibcon#about to read 4, iclass 26, count 0 2006.257.15:12:51.73#ibcon#read 4, iclass 26, count 0 2006.257.15:12:51.73#ibcon#about to read 5, iclass 26, count 0 2006.257.15:12:51.73#ibcon#read 5, iclass 26, count 0 2006.257.15:12:51.73#ibcon#about to read 6, iclass 26, count 0 2006.257.15:12:51.73#ibcon#read 6, iclass 26, count 0 2006.257.15:12:51.73#ibcon#end of sib2, iclass 26, count 0 2006.257.15:12:51.73#ibcon#*after write, iclass 26, count 0 2006.257.15:12:51.73#ibcon#*before return 0, iclass 26, count 0 2006.257.15:12:51.73#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:51.73#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:12:51.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:12:51.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:12:51.73$vck44/vblo=6,719.99 2006.257.15:12:51.73#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.15:12:51.73#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.15:12:51.73#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:51.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:51.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:51.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:51.73#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:12:51.73#ibcon#first serial, iclass 28, count 0 2006.257.15:12:51.73#ibcon#enter sib2, iclass 28, count 0 2006.257.15:12:51.73#ibcon#flushed, iclass 28, count 0 2006.257.15:12:51.73#ibcon#about to write, iclass 28, count 0 2006.257.15:12:51.73#ibcon#wrote, iclass 28, count 0 2006.257.15:12:51.73#ibcon#about to read 3, iclass 28, count 0 2006.257.15:12:51.75#ibcon#read 3, iclass 28, count 0 2006.257.15:12:51.75#ibcon#about to read 4, iclass 28, count 0 2006.257.15:12:51.75#ibcon#read 4, iclass 28, count 0 2006.257.15:12:51.75#ibcon#about to read 5, iclass 28, count 0 2006.257.15:12:51.75#ibcon#read 5, iclass 28, count 0 2006.257.15:12:51.75#ibcon#about to read 6, iclass 28, count 0 2006.257.15:12:51.75#ibcon#read 6, iclass 28, count 0 2006.257.15:12:51.75#ibcon#end of sib2, iclass 28, count 0 2006.257.15:12:51.75#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:12:51.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:12:51.75#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:12:51.75#ibcon#*before write, iclass 28, count 0 2006.257.15:12:51.75#ibcon#enter sib2, iclass 28, count 0 2006.257.15:12:51.75#ibcon#flushed, iclass 28, count 0 2006.257.15:12:51.75#ibcon#about to write, iclass 28, count 0 2006.257.15:12:51.75#ibcon#wrote, iclass 28, count 0 2006.257.15:12:51.75#ibcon#about to read 3, iclass 28, count 0 2006.257.15:12:51.79#ibcon#read 3, iclass 28, count 0 2006.257.15:12:51.79#ibcon#about to read 4, iclass 28, count 0 2006.257.15:12:51.79#ibcon#read 4, iclass 28, count 0 2006.257.15:12:51.79#ibcon#about to read 5, iclass 28, count 0 2006.257.15:12:51.79#ibcon#read 5, iclass 28, count 0 2006.257.15:12:51.79#ibcon#about to read 6, iclass 28, count 0 2006.257.15:12:51.79#ibcon#read 6, iclass 28, count 0 2006.257.15:12:51.79#ibcon#end of sib2, iclass 28, count 0 2006.257.15:12:51.79#ibcon#*after write, iclass 28, count 0 2006.257.15:12:51.79#ibcon#*before return 0, iclass 28, count 0 2006.257.15:12:51.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:51.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:12:51.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:12:51.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:12:51.79$vck44/vb=6,4 2006.257.15:12:51.79#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.15:12:51.79#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.15:12:51.79#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:51.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:51.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:51.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:51.85#ibcon#enter wrdev, iclass 30, count 2 2006.257.15:12:51.85#ibcon#first serial, iclass 30, count 2 2006.257.15:12:51.85#ibcon#enter sib2, iclass 30, count 2 2006.257.15:12:51.85#ibcon#flushed, iclass 30, count 2 2006.257.15:12:51.85#ibcon#about to write, iclass 30, count 2 2006.257.15:12:51.85#ibcon#wrote, iclass 30, count 2 2006.257.15:12:51.85#ibcon#about to read 3, iclass 30, count 2 2006.257.15:12:51.87#ibcon#read 3, iclass 30, count 2 2006.257.15:12:51.87#ibcon#about to read 4, iclass 30, count 2 2006.257.15:12:51.87#ibcon#read 4, iclass 30, count 2 2006.257.15:12:51.87#ibcon#about to read 5, iclass 30, count 2 2006.257.15:12:51.87#ibcon#read 5, iclass 30, count 2 2006.257.15:12:51.87#ibcon#about to read 6, iclass 30, count 2 2006.257.15:12:51.87#ibcon#read 6, iclass 30, count 2 2006.257.15:12:51.87#ibcon#end of sib2, iclass 30, count 2 2006.257.15:12:51.87#ibcon#*mode == 0, iclass 30, count 2 2006.257.15:12:51.87#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.15:12:51.87#ibcon#[27=AT06-04\r\n] 2006.257.15:12:51.87#ibcon#*before write, iclass 30, count 2 2006.257.15:12:51.87#ibcon#enter sib2, iclass 30, count 2 2006.257.15:12:51.87#ibcon#flushed, iclass 30, count 2 2006.257.15:12:51.87#ibcon#about to write, iclass 30, count 2 2006.257.15:12:51.87#ibcon#wrote, iclass 30, count 2 2006.257.15:12:51.87#ibcon#about to read 3, iclass 30, count 2 2006.257.15:12:51.90#ibcon#read 3, iclass 30, count 2 2006.257.15:12:51.90#ibcon#about to read 4, iclass 30, count 2 2006.257.15:12:51.90#ibcon#read 4, iclass 30, count 2 2006.257.15:12:51.90#ibcon#about to read 5, iclass 30, count 2 2006.257.15:12:51.90#ibcon#read 5, iclass 30, count 2 2006.257.15:12:51.90#ibcon#about to read 6, iclass 30, count 2 2006.257.15:12:51.90#ibcon#read 6, iclass 30, count 2 2006.257.15:12:51.90#ibcon#end of sib2, iclass 30, count 2 2006.257.15:12:51.90#ibcon#*after write, iclass 30, count 2 2006.257.15:12:51.90#ibcon#*before return 0, iclass 30, count 2 2006.257.15:12:51.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:51.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:12:51.90#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.15:12:51.90#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:51.90#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:52.02#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:52.02#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:52.02#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:12:52.02#ibcon#first serial, iclass 30, count 0 2006.257.15:12:52.02#ibcon#enter sib2, iclass 30, count 0 2006.257.15:12:52.02#ibcon#flushed, iclass 30, count 0 2006.257.15:12:52.02#ibcon#about to write, iclass 30, count 0 2006.257.15:12:52.02#ibcon#wrote, iclass 30, count 0 2006.257.15:12:52.02#ibcon#about to read 3, iclass 30, count 0 2006.257.15:12:52.04#ibcon#read 3, iclass 30, count 0 2006.257.15:12:52.04#ibcon#about to read 4, iclass 30, count 0 2006.257.15:12:52.04#ibcon#read 4, iclass 30, count 0 2006.257.15:12:52.04#ibcon#about to read 5, iclass 30, count 0 2006.257.15:12:52.04#ibcon#read 5, iclass 30, count 0 2006.257.15:12:52.04#ibcon#about to read 6, iclass 30, count 0 2006.257.15:12:52.04#ibcon#read 6, iclass 30, count 0 2006.257.15:12:52.04#ibcon#end of sib2, iclass 30, count 0 2006.257.15:12:52.04#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:12:52.04#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:12:52.04#ibcon#[27=USB\r\n] 2006.257.15:12:52.04#ibcon#*before write, iclass 30, count 0 2006.257.15:12:52.04#ibcon#enter sib2, iclass 30, count 0 2006.257.15:12:52.04#ibcon#flushed, iclass 30, count 0 2006.257.15:12:52.04#ibcon#about to write, iclass 30, count 0 2006.257.15:12:52.04#ibcon#wrote, iclass 30, count 0 2006.257.15:12:52.04#ibcon#about to read 3, iclass 30, count 0 2006.257.15:12:52.07#ibcon#read 3, iclass 30, count 0 2006.257.15:12:52.07#ibcon#about to read 4, iclass 30, count 0 2006.257.15:12:52.07#ibcon#read 4, iclass 30, count 0 2006.257.15:12:52.07#ibcon#about to read 5, iclass 30, count 0 2006.257.15:12:52.07#ibcon#read 5, iclass 30, count 0 2006.257.15:12:52.07#ibcon#about to read 6, iclass 30, count 0 2006.257.15:12:52.07#ibcon#read 6, iclass 30, count 0 2006.257.15:12:52.07#ibcon#end of sib2, iclass 30, count 0 2006.257.15:12:52.07#ibcon#*after write, iclass 30, count 0 2006.257.15:12:52.07#ibcon#*before return 0, iclass 30, count 0 2006.257.15:12:52.07#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:52.07#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:12:52.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:12:52.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:12:52.07$vck44/vblo=7,734.99 2006.257.15:12:52.07#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.15:12:52.07#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.15:12:52.07#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:52.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:52.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:52.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:52.07#ibcon#enter wrdev, iclass 32, count 0 2006.257.15:12:52.07#ibcon#first serial, iclass 32, count 0 2006.257.15:12:52.07#ibcon#enter sib2, iclass 32, count 0 2006.257.15:12:52.07#ibcon#flushed, iclass 32, count 0 2006.257.15:12:52.07#ibcon#about to write, iclass 32, count 0 2006.257.15:12:52.07#ibcon#wrote, iclass 32, count 0 2006.257.15:12:52.07#ibcon#about to read 3, iclass 32, count 0 2006.257.15:12:52.09#ibcon#read 3, iclass 32, count 0 2006.257.15:12:52.09#ibcon#about to read 4, iclass 32, count 0 2006.257.15:12:52.09#ibcon#read 4, iclass 32, count 0 2006.257.15:12:52.09#ibcon#about to read 5, iclass 32, count 0 2006.257.15:12:52.09#ibcon#read 5, iclass 32, count 0 2006.257.15:12:52.09#ibcon#about to read 6, iclass 32, count 0 2006.257.15:12:52.09#ibcon#read 6, iclass 32, count 0 2006.257.15:12:52.09#ibcon#end of sib2, iclass 32, count 0 2006.257.15:12:52.09#ibcon#*mode == 0, iclass 32, count 0 2006.257.15:12:52.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.15:12:52.09#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:12:52.09#ibcon#*before write, iclass 32, count 0 2006.257.15:12:52.09#ibcon#enter sib2, iclass 32, count 0 2006.257.15:12:52.09#ibcon#flushed, iclass 32, count 0 2006.257.15:12:52.09#ibcon#about to write, iclass 32, count 0 2006.257.15:12:52.09#ibcon#wrote, iclass 32, count 0 2006.257.15:12:52.09#ibcon#about to read 3, iclass 32, count 0 2006.257.15:12:52.13#ibcon#read 3, iclass 32, count 0 2006.257.15:12:52.13#ibcon#about to read 4, iclass 32, count 0 2006.257.15:12:52.13#ibcon#read 4, iclass 32, count 0 2006.257.15:12:52.13#ibcon#about to read 5, iclass 32, count 0 2006.257.15:12:52.13#ibcon#read 5, iclass 32, count 0 2006.257.15:12:52.13#ibcon#about to read 6, iclass 32, count 0 2006.257.15:12:52.13#ibcon#read 6, iclass 32, count 0 2006.257.15:12:52.13#ibcon#end of sib2, iclass 32, count 0 2006.257.15:12:52.13#ibcon#*after write, iclass 32, count 0 2006.257.15:12:52.13#ibcon#*before return 0, iclass 32, count 0 2006.257.15:12:52.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:52.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:12:52.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.15:12:52.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.15:12:52.13$vck44/vb=7,4 2006.257.15:12:52.13#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.15:12:52.13#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.15:12:52.13#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:52.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:52.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:52.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:52.19#ibcon#enter wrdev, iclass 34, count 2 2006.257.15:12:52.19#ibcon#first serial, iclass 34, count 2 2006.257.15:12:52.19#ibcon#enter sib2, iclass 34, count 2 2006.257.15:12:52.19#ibcon#flushed, iclass 34, count 2 2006.257.15:12:52.19#ibcon#about to write, iclass 34, count 2 2006.257.15:12:52.19#ibcon#wrote, iclass 34, count 2 2006.257.15:12:52.19#ibcon#about to read 3, iclass 34, count 2 2006.257.15:12:52.21#ibcon#read 3, iclass 34, count 2 2006.257.15:12:52.21#ibcon#about to read 4, iclass 34, count 2 2006.257.15:12:52.21#ibcon#read 4, iclass 34, count 2 2006.257.15:12:52.21#ibcon#about to read 5, iclass 34, count 2 2006.257.15:12:52.21#ibcon#read 5, iclass 34, count 2 2006.257.15:12:52.21#ibcon#about to read 6, iclass 34, count 2 2006.257.15:12:52.21#ibcon#read 6, iclass 34, count 2 2006.257.15:12:52.21#ibcon#end of sib2, iclass 34, count 2 2006.257.15:12:52.21#ibcon#*mode == 0, iclass 34, count 2 2006.257.15:12:52.21#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.15:12:52.21#ibcon#[27=AT07-04\r\n] 2006.257.15:12:52.21#ibcon#*before write, iclass 34, count 2 2006.257.15:12:52.21#ibcon#enter sib2, iclass 34, count 2 2006.257.15:12:52.21#ibcon#flushed, iclass 34, count 2 2006.257.15:12:52.21#ibcon#about to write, iclass 34, count 2 2006.257.15:12:52.21#ibcon#wrote, iclass 34, count 2 2006.257.15:12:52.21#ibcon#about to read 3, iclass 34, count 2 2006.257.15:12:52.24#ibcon#read 3, iclass 34, count 2 2006.257.15:12:52.24#ibcon#about to read 4, iclass 34, count 2 2006.257.15:12:52.24#ibcon#read 4, iclass 34, count 2 2006.257.15:12:52.24#ibcon#about to read 5, iclass 34, count 2 2006.257.15:12:52.24#ibcon#read 5, iclass 34, count 2 2006.257.15:12:52.24#ibcon#about to read 6, iclass 34, count 2 2006.257.15:12:52.24#ibcon#read 6, iclass 34, count 2 2006.257.15:12:52.24#ibcon#end of sib2, iclass 34, count 2 2006.257.15:12:52.24#ibcon#*after write, iclass 34, count 2 2006.257.15:12:52.24#ibcon#*before return 0, iclass 34, count 2 2006.257.15:12:52.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:52.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:12:52.24#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.15:12:52.24#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:52.24#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:52.36#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:52.36#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:52.36#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:12:52.36#ibcon#first serial, iclass 34, count 0 2006.257.15:12:52.36#ibcon#enter sib2, iclass 34, count 0 2006.257.15:12:52.36#ibcon#flushed, iclass 34, count 0 2006.257.15:12:52.36#ibcon#about to write, iclass 34, count 0 2006.257.15:12:52.36#ibcon#wrote, iclass 34, count 0 2006.257.15:12:52.36#ibcon#about to read 3, iclass 34, count 0 2006.257.15:12:52.38#ibcon#read 3, iclass 34, count 0 2006.257.15:12:52.38#ibcon#about to read 4, iclass 34, count 0 2006.257.15:12:52.38#ibcon#read 4, iclass 34, count 0 2006.257.15:12:52.38#ibcon#about to read 5, iclass 34, count 0 2006.257.15:12:52.38#ibcon#read 5, iclass 34, count 0 2006.257.15:12:52.38#ibcon#about to read 6, iclass 34, count 0 2006.257.15:12:52.38#ibcon#read 6, iclass 34, count 0 2006.257.15:12:52.38#ibcon#end of sib2, iclass 34, count 0 2006.257.15:12:52.38#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:12:52.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:12:52.38#ibcon#[27=USB\r\n] 2006.257.15:12:52.38#ibcon#*before write, iclass 34, count 0 2006.257.15:12:52.38#ibcon#enter sib2, iclass 34, count 0 2006.257.15:12:52.38#ibcon#flushed, iclass 34, count 0 2006.257.15:12:52.38#ibcon#about to write, iclass 34, count 0 2006.257.15:12:52.38#ibcon#wrote, iclass 34, count 0 2006.257.15:12:52.38#ibcon#about to read 3, iclass 34, count 0 2006.257.15:12:52.41#ibcon#read 3, iclass 34, count 0 2006.257.15:12:52.41#ibcon#about to read 4, iclass 34, count 0 2006.257.15:12:52.41#ibcon#read 4, iclass 34, count 0 2006.257.15:12:52.41#ibcon#about to read 5, iclass 34, count 0 2006.257.15:12:52.41#ibcon#read 5, iclass 34, count 0 2006.257.15:12:52.41#ibcon#about to read 6, iclass 34, count 0 2006.257.15:12:52.41#ibcon#read 6, iclass 34, count 0 2006.257.15:12:52.41#ibcon#end of sib2, iclass 34, count 0 2006.257.15:12:52.41#ibcon#*after write, iclass 34, count 0 2006.257.15:12:52.41#ibcon#*before return 0, iclass 34, count 0 2006.257.15:12:52.41#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:52.41#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:12:52.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:12:52.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:12:52.41$vck44/vblo=8,744.99 2006.257.15:12:52.41#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.15:12:52.41#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.15:12:52.41#ibcon#ireg 17 cls_cnt 0 2006.257.15:12:52.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:52.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:52.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:52.41#ibcon#enter wrdev, iclass 36, count 0 2006.257.15:12:52.41#ibcon#first serial, iclass 36, count 0 2006.257.15:12:52.41#ibcon#enter sib2, iclass 36, count 0 2006.257.15:12:52.41#ibcon#flushed, iclass 36, count 0 2006.257.15:12:52.41#ibcon#about to write, iclass 36, count 0 2006.257.15:12:52.41#ibcon#wrote, iclass 36, count 0 2006.257.15:12:52.41#ibcon#about to read 3, iclass 36, count 0 2006.257.15:12:52.43#ibcon#read 3, iclass 36, count 0 2006.257.15:12:52.43#ibcon#about to read 4, iclass 36, count 0 2006.257.15:12:52.43#ibcon#read 4, iclass 36, count 0 2006.257.15:12:52.43#ibcon#about to read 5, iclass 36, count 0 2006.257.15:12:52.43#ibcon#read 5, iclass 36, count 0 2006.257.15:12:52.43#ibcon#about to read 6, iclass 36, count 0 2006.257.15:12:52.43#ibcon#read 6, iclass 36, count 0 2006.257.15:12:52.43#ibcon#end of sib2, iclass 36, count 0 2006.257.15:12:52.43#ibcon#*mode == 0, iclass 36, count 0 2006.257.15:12:52.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.15:12:52.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:12:52.43#ibcon#*before write, iclass 36, count 0 2006.257.15:12:52.43#ibcon#enter sib2, iclass 36, count 0 2006.257.15:12:52.43#ibcon#flushed, iclass 36, count 0 2006.257.15:12:52.43#ibcon#about to write, iclass 36, count 0 2006.257.15:12:52.43#ibcon#wrote, iclass 36, count 0 2006.257.15:12:52.43#ibcon#about to read 3, iclass 36, count 0 2006.257.15:12:52.47#ibcon#read 3, iclass 36, count 0 2006.257.15:12:52.47#ibcon#about to read 4, iclass 36, count 0 2006.257.15:12:52.47#ibcon#read 4, iclass 36, count 0 2006.257.15:12:52.47#ibcon#about to read 5, iclass 36, count 0 2006.257.15:12:52.47#ibcon#read 5, iclass 36, count 0 2006.257.15:12:52.47#ibcon#about to read 6, iclass 36, count 0 2006.257.15:12:52.47#ibcon#read 6, iclass 36, count 0 2006.257.15:12:52.47#ibcon#end of sib2, iclass 36, count 0 2006.257.15:12:52.47#ibcon#*after write, iclass 36, count 0 2006.257.15:12:52.47#ibcon#*before return 0, iclass 36, count 0 2006.257.15:12:52.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:52.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:12:52.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.15:12:52.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.15:12:52.47$vck44/vb=8,4 2006.257.15:12:52.47#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.15:12:52.47#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.15:12:52.47#ibcon#ireg 11 cls_cnt 2 2006.257.15:12:52.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:52.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:52.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:52.53#ibcon#enter wrdev, iclass 38, count 2 2006.257.15:12:52.53#ibcon#first serial, iclass 38, count 2 2006.257.15:12:52.53#ibcon#enter sib2, iclass 38, count 2 2006.257.15:12:52.53#ibcon#flushed, iclass 38, count 2 2006.257.15:12:52.53#ibcon#about to write, iclass 38, count 2 2006.257.15:12:52.53#ibcon#wrote, iclass 38, count 2 2006.257.15:12:52.53#ibcon#about to read 3, iclass 38, count 2 2006.257.15:12:52.55#ibcon#read 3, iclass 38, count 2 2006.257.15:12:52.55#ibcon#about to read 4, iclass 38, count 2 2006.257.15:12:52.55#ibcon#read 4, iclass 38, count 2 2006.257.15:12:52.55#ibcon#about to read 5, iclass 38, count 2 2006.257.15:12:52.55#ibcon#read 5, iclass 38, count 2 2006.257.15:12:52.55#ibcon#about to read 6, iclass 38, count 2 2006.257.15:12:52.55#ibcon#read 6, iclass 38, count 2 2006.257.15:12:52.55#ibcon#end of sib2, iclass 38, count 2 2006.257.15:12:52.55#ibcon#*mode == 0, iclass 38, count 2 2006.257.15:12:52.55#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.15:12:52.55#ibcon#[27=AT08-04\r\n] 2006.257.15:12:52.55#ibcon#*before write, iclass 38, count 2 2006.257.15:12:52.55#ibcon#enter sib2, iclass 38, count 2 2006.257.15:12:52.55#ibcon#flushed, iclass 38, count 2 2006.257.15:12:52.55#ibcon#about to write, iclass 38, count 2 2006.257.15:12:52.55#ibcon#wrote, iclass 38, count 2 2006.257.15:12:52.55#ibcon#about to read 3, iclass 38, count 2 2006.257.15:12:52.58#ibcon#read 3, iclass 38, count 2 2006.257.15:12:52.58#ibcon#about to read 4, iclass 38, count 2 2006.257.15:12:52.58#ibcon#read 4, iclass 38, count 2 2006.257.15:12:52.58#ibcon#about to read 5, iclass 38, count 2 2006.257.15:12:52.58#ibcon#read 5, iclass 38, count 2 2006.257.15:12:52.58#ibcon#about to read 6, iclass 38, count 2 2006.257.15:12:52.58#ibcon#read 6, iclass 38, count 2 2006.257.15:12:52.58#ibcon#end of sib2, iclass 38, count 2 2006.257.15:12:52.58#ibcon#*after write, iclass 38, count 2 2006.257.15:12:52.58#ibcon#*before return 0, iclass 38, count 2 2006.257.15:12:52.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:52.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:12:52.58#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.15:12:52.58#ibcon#ireg 7 cls_cnt 0 2006.257.15:12:52.58#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:52.70#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:52.70#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:52.70#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:12:52.70#ibcon#first serial, iclass 38, count 0 2006.257.15:12:52.70#ibcon#enter sib2, iclass 38, count 0 2006.257.15:12:52.70#ibcon#flushed, iclass 38, count 0 2006.257.15:12:52.70#ibcon#about to write, iclass 38, count 0 2006.257.15:12:52.70#ibcon#wrote, iclass 38, count 0 2006.257.15:12:52.70#ibcon#about to read 3, iclass 38, count 0 2006.257.15:12:52.72#ibcon#read 3, iclass 38, count 0 2006.257.15:12:52.72#ibcon#about to read 4, iclass 38, count 0 2006.257.15:12:52.72#ibcon#read 4, iclass 38, count 0 2006.257.15:12:52.72#ibcon#about to read 5, iclass 38, count 0 2006.257.15:12:52.72#ibcon#read 5, iclass 38, count 0 2006.257.15:12:52.72#ibcon#about to read 6, iclass 38, count 0 2006.257.15:12:52.72#ibcon#read 6, iclass 38, count 0 2006.257.15:12:52.72#ibcon#end of sib2, iclass 38, count 0 2006.257.15:12:52.72#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:12:52.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:12:52.72#ibcon#[27=USB\r\n] 2006.257.15:12:52.72#ibcon#*before write, iclass 38, count 0 2006.257.15:12:52.72#ibcon#enter sib2, iclass 38, count 0 2006.257.15:12:52.72#ibcon#flushed, iclass 38, count 0 2006.257.15:12:52.72#ibcon#about to write, iclass 38, count 0 2006.257.15:12:52.72#ibcon#wrote, iclass 38, count 0 2006.257.15:12:52.72#ibcon#about to read 3, iclass 38, count 0 2006.257.15:12:52.75#ibcon#read 3, iclass 38, count 0 2006.257.15:12:52.75#ibcon#about to read 4, iclass 38, count 0 2006.257.15:12:52.75#ibcon#read 4, iclass 38, count 0 2006.257.15:12:52.75#ibcon#about to read 5, iclass 38, count 0 2006.257.15:12:52.75#ibcon#read 5, iclass 38, count 0 2006.257.15:12:52.75#ibcon#about to read 6, iclass 38, count 0 2006.257.15:12:52.75#ibcon#read 6, iclass 38, count 0 2006.257.15:12:52.75#ibcon#end of sib2, iclass 38, count 0 2006.257.15:12:52.75#ibcon#*after write, iclass 38, count 0 2006.257.15:12:52.75#ibcon#*before return 0, iclass 38, count 0 2006.257.15:12:52.75#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:52.75#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:12:52.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:12:52.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:12:52.75$vck44/vabw=wide 2006.257.15:12:52.75#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.15:12:52.75#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.15:12:52.75#ibcon#ireg 8 cls_cnt 0 2006.257.15:12:52.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:52.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:52.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:52.75#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:12:52.75#ibcon#first serial, iclass 40, count 0 2006.257.15:12:52.75#ibcon#enter sib2, iclass 40, count 0 2006.257.15:12:52.75#ibcon#flushed, iclass 40, count 0 2006.257.15:12:52.75#ibcon#about to write, iclass 40, count 0 2006.257.15:12:52.75#ibcon#wrote, iclass 40, count 0 2006.257.15:12:52.75#ibcon#about to read 3, iclass 40, count 0 2006.257.15:12:52.77#ibcon#read 3, iclass 40, count 0 2006.257.15:12:52.77#ibcon#about to read 4, iclass 40, count 0 2006.257.15:12:52.77#ibcon#read 4, iclass 40, count 0 2006.257.15:12:52.77#ibcon#about to read 5, iclass 40, count 0 2006.257.15:12:52.77#ibcon#read 5, iclass 40, count 0 2006.257.15:12:52.77#ibcon#about to read 6, iclass 40, count 0 2006.257.15:12:52.77#ibcon#read 6, iclass 40, count 0 2006.257.15:12:52.77#ibcon#end of sib2, iclass 40, count 0 2006.257.15:12:52.77#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:12:52.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:12:52.77#ibcon#[25=BW32\r\n] 2006.257.15:12:52.77#ibcon#*before write, iclass 40, count 0 2006.257.15:12:52.77#ibcon#enter sib2, iclass 40, count 0 2006.257.15:12:52.77#ibcon#flushed, iclass 40, count 0 2006.257.15:12:52.77#ibcon#about to write, iclass 40, count 0 2006.257.15:12:52.77#ibcon#wrote, iclass 40, count 0 2006.257.15:12:52.77#ibcon#about to read 3, iclass 40, count 0 2006.257.15:12:52.80#ibcon#read 3, iclass 40, count 0 2006.257.15:12:52.80#ibcon#about to read 4, iclass 40, count 0 2006.257.15:12:52.80#ibcon#read 4, iclass 40, count 0 2006.257.15:12:52.80#ibcon#about to read 5, iclass 40, count 0 2006.257.15:12:52.80#ibcon#read 5, iclass 40, count 0 2006.257.15:12:52.80#ibcon#about to read 6, iclass 40, count 0 2006.257.15:12:52.80#ibcon#read 6, iclass 40, count 0 2006.257.15:12:52.80#ibcon#end of sib2, iclass 40, count 0 2006.257.15:12:52.80#ibcon#*after write, iclass 40, count 0 2006.257.15:12:52.80#ibcon#*before return 0, iclass 40, count 0 2006.257.15:12:52.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:52.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:12:52.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:12:52.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:12:52.80$vck44/vbbw=wide 2006.257.15:12:52.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.15:12:52.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.15:12:52.80#ibcon#ireg 8 cls_cnt 0 2006.257.15:12:52.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:12:52.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:12:52.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:12:52.87#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:12:52.87#ibcon#first serial, iclass 4, count 0 2006.257.15:12:52.87#ibcon#enter sib2, iclass 4, count 0 2006.257.15:12:52.87#ibcon#flushed, iclass 4, count 0 2006.257.15:12:52.87#ibcon#about to write, iclass 4, count 0 2006.257.15:12:52.87#ibcon#wrote, iclass 4, count 0 2006.257.15:12:52.87#ibcon#about to read 3, iclass 4, count 0 2006.257.15:12:52.89#ibcon#read 3, iclass 4, count 0 2006.257.15:12:52.89#ibcon#about to read 4, iclass 4, count 0 2006.257.15:12:52.89#ibcon#read 4, iclass 4, count 0 2006.257.15:12:52.89#ibcon#about to read 5, iclass 4, count 0 2006.257.15:12:52.89#ibcon#read 5, iclass 4, count 0 2006.257.15:12:52.89#ibcon#about to read 6, iclass 4, count 0 2006.257.15:12:52.89#ibcon#read 6, iclass 4, count 0 2006.257.15:12:52.89#ibcon#end of sib2, iclass 4, count 0 2006.257.15:12:52.89#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:12:52.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:12:52.89#ibcon#[27=BW32\r\n] 2006.257.15:12:52.89#ibcon#*before write, iclass 4, count 0 2006.257.15:12:52.89#ibcon#enter sib2, iclass 4, count 0 2006.257.15:12:52.89#ibcon#flushed, iclass 4, count 0 2006.257.15:12:52.89#ibcon#about to write, iclass 4, count 0 2006.257.15:12:52.89#ibcon#wrote, iclass 4, count 0 2006.257.15:12:52.89#ibcon#about to read 3, iclass 4, count 0 2006.257.15:12:52.92#ibcon#read 3, iclass 4, count 0 2006.257.15:12:52.92#ibcon#about to read 4, iclass 4, count 0 2006.257.15:12:52.92#ibcon#read 4, iclass 4, count 0 2006.257.15:12:52.92#ibcon#about to read 5, iclass 4, count 0 2006.257.15:12:52.92#ibcon#read 5, iclass 4, count 0 2006.257.15:12:52.92#ibcon#about to read 6, iclass 4, count 0 2006.257.15:12:52.92#ibcon#read 6, iclass 4, count 0 2006.257.15:12:52.92#ibcon#end of sib2, iclass 4, count 0 2006.257.15:12:52.92#ibcon#*after write, iclass 4, count 0 2006.257.15:12:52.92#ibcon#*before return 0, iclass 4, count 0 2006.257.15:12:52.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:12:52.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:12:52.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:12:52.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:12:52.92$setupk4/ifdk4 2006.257.15:12:52.92$ifdk4/lo= 2006.257.15:12:52.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:12:52.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:12:52.92$ifdk4/patch= 2006.257.15:12:52.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:12:52.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:12:52.92$setupk4/!*+20s 2006.257.15:12:53.42#abcon#<5=/14 2.1 4.6 17.44 971014.0\r\n> 2006.257.15:12:53.44#abcon#{5=INTERFACE CLEAR} 2006.257.15:12:53.50#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:13:03.59#abcon#<5=/14 2.1 4.6 17.44 971014.0\r\n> 2006.257.15:13:03.61#abcon#{5=INTERFACE CLEAR} 2006.257.15:13:03.67#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:13:06.13#trakl#Source acquired 2006.257.15:13:06.13#flagr#flagr/antenna,acquired 2006.257.15:13:07.35$setupk4/"tpicd 2006.257.15:13:07.35$setupk4/echo=off 2006.257.15:13:07.35$setupk4/xlog=off 2006.257.15:13:07.35:!2006.257.15:13:44 2006.257.15:13:44.00:preob 2006.257.15:13:44.14/onsource/TRACKING 2006.257.15:13:44.14:!2006.257.15:13:54 2006.257.15:13:54.00:"tape 2006.257.15:13:54.00:"st=record 2006.257.15:13:54.00:data_valid=on 2006.257.15:13:54.00:midob 2006.257.15:13:54.14/onsource/TRACKING 2006.257.15:13:54.14/wx/17.44,1014.0,97 2006.257.15:13:54.24/cable/+6.4817E-03 2006.257.15:13:55.33/va/01,08,usb,yes,34,37 2006.257.15:13:55.33/va/02,07,usb,yes,37,38 2006.257.15:13:55.33/va/03,08,usb,yes,33,35 2006.257.15:13:55.33/va/04,07,usb,yes,38,40 2006.257.15:13:55.33/va/05,04,usb,yes,34,35 2006.257.15:13:55.33/va/06,04,usb,yes,38,38 2006.257.15:13:55.33/va/07,04,usb,yes,39,40 2006.257.15:13:55.33/va/08,04,usb,yes,33,40 2006.257.15:13:55.56/valo/01,524.99,yes,locked 2006.257.15:13:55.56/valo/02,534.99,yes,locked 2006.257.15:13:55.56/valo/03,564.99,yes,locked 2006.257.15:13:55.56/valo/04,624.99,yes,locked 2006.257.15:13:55.56/valo/05,734.99,yes,locked 2006.257.15:13:55.56/valo/06,814.99,yes,locked 2006.257.15:13:55.56/valo/07,864.99,yes,locked 2006.257.15:13:55.56/valo/08,884.99,yes,locked 2006.257.15:13:56.65/vb/01,04,usb,yes,33,31 2006.257.15:13:56.65/vb/02,05,usb,yes,32,31 2006.257.15:13:56.65/vb/03,04,usb,yes,33,36 2006.257.15:13:56.65/vb/04,05,usb,yes,33,32 2006.257.15:13:56.65/vb/05,04,usb,yes,29,32 2006.257.15:13:56.65/vb/06,04,usb,yes,35,30 2006.257.15:13:56.65/vb/07,04,usb,yes,34,34 2006.257.15:13:56.65/vb/08,04,usb,yes,31,35 2006.257.15:13:56.89/vblo/01,629.99,yes,locked 2006.257.15:13:56.89/vblo/02,634.99,yes,locked 2006.257.15:13:56.89/vblo/03,649.99,yes,locked 2006.257.15:13:56.89/vblo/04,679.99,yes,locked 2006.257.15:13:56.89/vblo/05,709.99,yes,locked 2006.257.15:13:56.89/vblo/06,719.99,yes,locked 2006.257.15:13:56.89/vblo/07,734.99,yes,locked 2006.257.15:13:56.89/vblo/08,744.99,yes,locked 2006.257.15:13:57.04/vabw/8 2006.257.15:13:57.19/vbbw/8 2006.257.15:13:57.28/xfe/off,on,15.2 2006.257.15:13:57.65/ifatt/23,28,28,28 2006.257.15:13:58.07/fmout-gps/S +4.63E-07 2006.257.15:13:58.11:!2006.257.15:26:58 2006.257.15:26:58.00:data_valid=off 2006.257.15:26:58.00:"et 2006.257.15:26:58.00:!+3s 2006.257.15:27:01.01:"tape 2006.257.15:27:01.01:postob 2006.257.15:27:01.12/cable/+6.4818E-03 2006.257.15:27:01.12/wx/17.49,1013.9,96 2006.257.15:27:02.08/fmout-gps/S +4.57E-07 2006.257.15:27:02.08:scan_name=257-1528,jd0609,110 2006.257.15:27:02.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.257.15:27:03.14#flagr#flagr/antenna,new-source 2006.257.15:27:03.14:checkk5 2006.257.15:27:03.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:27:03.98/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:27:04.39/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:27:04.79/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:27:05.51/chk_obsdata//k5ts1/T2571513??a.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.257.15:27:06.21/chk_obsdata//k5ts2/T2571513??b.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.257.15:27:06.90/chk_obsdata//k5ts3/T2571513??c.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.257.15:27:07.61/chk_obsdata//k5ts4/T2571513??d.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.257.15:27:08.36/k5log//k5ts1_log_newline 2006.257.15:27:09.07/k5log//k5ts2_log_newline 2006.257.15:27:09.77/k5log//k5ts3_log_newline 2006.257.15:27:10.48/k5log//k5ts4_log_newline 2006.257.15:27:10.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:27:10.50:setupk4=1 2006.257.15:27:10.50$setupk4/echo=on 2006.257.15:27:10.50$setupk4/pcalon 2006.257.15:27:10.50$pcalon/"no phase cal control is implemented here 2006.257.15:27:10.50$setupk4/"tpicd=stop 2006.257.15:27:10.50$setupk4/"rec=synch_on 2006.257.15:27:10.50$setupk4/"rec_mode=128 2006.257.15:27:10.50$setupk4/!* 2006.257.15:27:10.50$setupk4/recpk4 2006.257.15:27:10.50$recpk4/recpatch= 2006.257.15:27:10.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:27:10.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:27:10.50$setupk4/vck44 2006.257.15:27:10.50$vck44/valo=1,524.99 2006.257.15:27:10.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.15:27:10.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.15:27:10.50#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:10.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:10.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:10.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:10.50#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:27:10.50#ibcon#first serial, iclass 18, count 0 2006.257.15:27:10.50#ibcon#enter sib2, iclass 18, count 0 2006.257.15:27:10.50#ibcon#flushed, iclass 18, count 0 2006.257.15:27:10.50#ibcon#about to write, iclass 18, count 0 2006.257.15:27:10.50#ibcon#wrote, iclass 18, count 0 2006.257.15:27:10.50#ibcon#about to read 3, iclass 18, count 0 2006.257.15:27:10.52#ibcon#read 3, iclass 18, count 0 2006.257.15:27:10.52#ibcon#about to read 4, iclass 18, count 0 2006.257.15:27:10.52#ibcon#read 4, iclass 18, count 0 2006.257.15:27:10.52#ibcon#about to read 5, iclass 18, count 0 2006.257.15:27:10.52#ibcon#read 5, iclass 18, count 0 2006.257.15:27:10.52#ibcon#about to read 6, iclass 18, count 0 2006.257.15:27:10.52#ibcon#read 6, iclass 18, count 0 2006.257.15:27:10.52#ibcon#end of sib2, iclass 18, count 0 2006.257.15:27:10.52#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:27:10.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:27:10.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:27:10.52#ibcon#*before write, iclass 18, count 0 2006.257.15:27:10.52#ibcon#enter sib2, iclass 18, count 0 2006.257.15:27:10.52#ibcon#flushed, iclass 18, count 0 2006.257.15:27:10.52#ibcon#about to write, iclass 18, count 0 2006.257.15:27:10.52#ibcon#wrote, iclass 18, count 0 2006.257.15:27:10.52#ibcon#about to read 3, iclass 18, count 0 2006.257.15:27:10.57#ibcon#read 3, iclass 18, count 0 2006.257.15:27:10.57#ibcon#about to read 4, iclass 18, count 0 2006.257.15:27:10.57#ibcon#read 4, iclass 18, count 0 2006.257.15:27:10.57#ibcon#about to read 5, iclass 18, count 0 2006.257.15:27:10.57#ibcon#read 5, iclass 18, count 0 2006.257.15:27:10.57#ibcon#about to read 6, iclass 18, count 0 2006.257.15:27:10.57#ibcon#read 6, iclass 18, count 0 2006.257.15:27:10.57#ibcon#end of sib2, iclass 18, count 0 2006.257.15:27:10.57#ibcon#*after write, iclass 18, count 0 2006.257.15:27:10.57#ibcon#*before return 0, iclass 18, count 0 2006.257.15:27:10.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:10.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:10.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:27:10.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:27:10.57$vck44/va=1,8 2006.257.15:27:10.57#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.15:27:10.57#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.15:27:10.57#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:10.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:10.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:10.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:10.57#ibcon#enter wrdev, iclass 20, count 2 2006.257.15:27:10.57#ibcon#first serial, iclass 20, count 2 2006.257.15:27:10.57#ibcon#enter sib2, iclass 20, count 2 2006.257.15:27:10.57#ibcon#flushed, iclass 20, count 2 2006.257.15:27:10.57#ibcon#about to write, iclass 20, count 2 2006.257.15:27:10.57#ibcon#wrote, iclass 20, count 2 2006.257.15:27:10.57#ibcon#about to read 3, iclass 20, count 2 2006.257.15:27:10.59#ibcon#read 3, iclass 20, count 2 2006.257.15:27:10.59#ibcon#about to read 4, iclass 20, count 2 2006.257.15:27:10.59#ibcon#read 4, iclass 20, count 2 2006.257.15:27:10.59#ibcon#about to read 5, iclass 20, count 2 2006.257.15:27:10.59#ibcon#read 5, iclass 20, count 2 2006.257.15:27:10.59#ibcon#about to read 6, iclass 20, count 2 2006.257.15:27:10.59#ibcon#read 6, iclass 20, count 2 2006.257.15:27:10.59#ibcon#end of sib2, iclass 20, count 2 2006.257.15:27:10.59#ibcon#*mode == 0, iclass 20, count 2 2006.257.15:27:10.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.15:27:10.59#ibcon#[25=AT01-08\r\n] 2006.257.15:27:10.59#ibcon#*before write, iclass 20, count 2 2006.257.15:27:10.59#ibcon#enter sib2, iclass 20, count 2 2006.257.15:27:10.59#ibcon#flushed, iclass 20, count 2 2006.257.15:27:10.59#ibcon#about to write, iclass 20, count 2 2006.257.15:27:10.59#ibcon#wrote, iclass 20, count 2 2006.257.15:27:10.59#ibcon#about to read 3, iclass 20, count 2 2006.257.15:27:10.62#ibcon#read 3, iclass 20, count 2 2006.257.15:27:10.62#ibcon#about to read 4, iclass 20, count 2 2006.257.15:27:10.62#ibcon#read 4, iclass 20, count 2 2006.257.15:27:10.62#ibcon#about to read 5, iclass 20, count 2 2006.257.15:27:10.62#ibcon#read 5, iclass 20, count 2 2006.257.15:27:10.62#ibcon#about to read 6, iclass 20, count 2 2006.257.15:27:10.62#ibcon#read 6, iclass 20, count 2 2006.257.15:27:10.62#ibcon#end of sib2, iclass 20, count 2 2006.257.15:27:10.62#ibcon#*after write, iclass 20, count 2 2006.257.15:27:10.62#ibcon#*before return 0, iclass 20, count 2 2006.257.15:27:10.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:10.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:10.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.15:27:10.62#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:10.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:10.69#abcon#<5=/14 1.0 2.2 17.49 961013.9\r\n> 2006.257.15:27:10.71#abcon#{5=INTERFACE CLEAR} 2006.257.15:27:10.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:10.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:10.74#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:27:10.74#ibcon#first serial, iclass 20, count 0 2006.257.15:27:10.74#ibcon#enter sib2, iclass 20, count 0 2006.257.15:27:10.74#ibcon#flushed, iclass 20, count 0 2006.257.15:27:10.74#ibcon#about to write, iclass 20, count 0 2006.257.15:27:10.74#ibcon#wrote, iclass 20, count 0 2006.257.15:27:10.74#ibcon#about to read 3, iclass 20, count 0 2006.257.15:27:10.76#ibcon#read 3, iclass 20, count 0 2006.257.15:27:10.76#ibcon#about to read 4, iclass 20, count 0 2006.257.15:27:10.76#ibcon#read 4, iclass 20, count 0 2006.257.15:27:10.76#ibcon#about to read 5, iclass 20, count 0 2006.257.15:27:10.76#ibcon#read 5, iclass 20, count 0 2006.257.15:27:10.76#ibcon#about to read 6, iclass 20, count 0 2006.257.15:27:10.76#ibcon#read 6, iclass 20, count 0 2006.257.15:27:10.76#ibcon#end of sib2, iclass 20, count 0 2006.257.15:27:10.76#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:27:10.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:27:10.76#ibcon#[25=USB\r\n] 2006.257.15:27:10.76#ibcon#*before write, iclass 20, count 0 2006.257.15:27:10.76#ibcon#enter sib2, iclass 20, count 0 2006.257.15:27:10.76#ibcon#flushed, iclass 20, count 0 2006.257.15:27:10.76#ibcon#about to write, iclass 20, count 0 2006.257.15:27:10.76#ibcon#wrote, iclass 20, count 0 2006.257.15:27:10.76#ibcon#about to read 3, iclass 20, count 0 2006.257.15:27:10.77#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:27:10.79#ibcon#read 3, iclass 20, count 0 2006.257.15:27:10.79#ibcon#about to read 4, iclass 20, count 0 2006.257.15:27:10.79#ibcon#read 4, iclass 20, count 0 2006.257.15:27:10.79#ibcon#about to read 5, iclass 20, count 0 2006.257.15:27:10.79#ibcon#read 5, iclass 20, count 0 2006.257.15:27:10.79#ibcon#about to read 6, iclass 20, count 0 2006.257.15:27:10.79#ibcon#read 6, iclass 20, count 0 2006.257.15:27:10.79#ibcon#end of sib2, iclass 20, count 0 2006.257.15:27:10.79#ibcon#*after write, iclass 20, count 0 2006.257.15:27:10.79#ibcon#*before return 0, iclass 20, count 0 2006.257.15:27:10.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:10.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:10.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:27:10.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:27:10.79$vck44/valo=2,534.99 2006.257.15:27:10.79#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.15:27:10.79#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.15:27:10.79#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:10.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:10.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:10.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:10.79#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:27:10.79#ibcon#first serial, iclass 26, count 0 2006.257.15:27:10.79#ibcon#enter sib2, iclass 26, count 0 2006.257.15:27:10.79#ibcon#flushed, iclass 26, count 0 2006.257.15:27:10.79#ibcon#about to write, iclass 26, count 0 2006.257.15:27:10.79#ibcon#wrote, iclass 26, count 0 2006.257.15:27:10.79#ibcon#about to read 3, iclass 26, count 0 2006.257.15:27:10.81#ibcon#read 3, iclass 26, count 0 2006.257.15:27:10.81#ibcon#about to read 4, iclass 26, count 0 2006.257.15:27:10.81#ibcon#read 4, iclass 26, count 0 2006.257.15:27:10.81#ibcon#about to read 5, iclass 26, count 0 2006.257.15:27:10.81#ibcon#read 5, iclass 26, count 0 2006.257.15:27:10.81#ibcon#about to read 6, iclass 26, count 0 2006.257.15:27:10.81#ibcon#read 6, iclass 26, count 0 2006.257.15:27:10.81#ibcon#end of sib2, iclass 26, count 0 2006.257.15:27:10.81#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:27:10.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:27:10.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:27:10.81#ibcon#*before write, iclass 26, count 0 2006.257.15:27:10.81#ibcon#enter sib2, iclass 26, count 0 2006.257.15:27:10.81#ibcon#flushed, iclass 26, count 0 2006.257.15:27:10.81#ibcon#about to write, iclass 26, count 0 2006.257.15:27:10.81#ibcon#wrote, iclass 26, count 0 2006.257.15:27:10.81#ibcon#about to read 3, iclass 26, count 0 2006.257.15:27:10.85#ibcon#read 3, iclass 26, count 0 2006.257.15:27:10.85#ibcon#about to read 4, iclass 26, count 0 2006.257.15:27:10.85#ibcon#read 4, iclass 26, count 0 2006.257.15:27:10.85#ibcon#about to read 5, iclass 26, count 0 2006.257.15:27:10.85#ibcon#read 5, iclass 26, count 0 2006.257.15:27:10.85#ibcon#about to read 6, iclass 26, count 0 2006.257.15:27:10.85#ibcon#read 6, iclass 26, count 0 2006.257.15:27:10.85#ibcon#end of sib2, iclass 26, count 0 2006.257.15:27:10.85#ibcon#*after write, iclass 26, count 0 2006.257.15:27:10.85#ibcon#*before return 0, iclass 26, count 0 2006.257.15:27:10.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:10.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:10.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:27:10.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:27:10.85$vck44/va=2,7 2006.257.15:27:10.85#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.15:27:10.85#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.15:27:10.85#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:10.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:10.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:10.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:10.91#ibcon#enter wrdev, iclass 28, count 2 2006.257.15:27:10.91#ibcon#first serial, iclass 28, count 2 2006.257.15:27:10.91#ibcon#enter sib2, iclass 28, count 2 2006.257.15:27:10.91#ibcon#flushed, iclass 28, count 2 2006.257.15:27:10.91#ibcon#about to write, iclass 28, count 2 2006.257.15:27:10.91#ibcon#wrote, iclass 28, count 2 2006.257.15:27:10.91#ibcon#about to read 3, iclass 28, count 2 2006.257.15:27:10.93#ibcon#read 3, iclass 28, count 2 2006.257.15:27:10.93#ibcon#about to read 4, iclass 28, count 2 2006.257.15:27:10.93#ibcon#read 4, iclass 28, count 2 2006.257.15:27:10.93#ibcon#about to read 5, iclass 28, count 2 2006.257.15:27:10.93#ibcon#read 5, iclass 28, count 2 2006.257.15:27:10.93#ibcon#about to read 6, iclass 28, count 2 2006.257.15:27:10.93#ibcon#read 6, iclass 28, count 2 2006.257.15:27:10.93#ibcon#end of sib2, iclass 28, count 2 2006.257.15:27:10.93#ibcon#*mode == 0, iclass 28, count 2 2006.257.15:27:10.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.15:27:10.93#ibcon#[25=AT02-07\r\n] 2006.257.15:27:10.93#ibcon#*before write, iclass 28, count 2 2006.257.15:27:10.93#ibcon#enter sib2, iclass 28, count 2 2006.257.15:27:10.93#ibcon#flushed, iclass 28, count 2 2006.257.15:27:10.93#ibcon#about to write, iclass 28, count 2 2006.257.15:27:10.93#ibcon#wrote, iclass 28, count 2 2006.257.15:27:10.93#ibcon#about to read 3, iclass 28, count 2 2006.257.15:27:10.96#ibcon#read 3, iclass 28, count 2 2006.257.15:27:10.96#ibcon#about to read 4, iclass 28, count 2 2006.257.15:27:10.96#ibcon#read 4, iclass 28, count 2 2006.257.15:27:10.96#ibcon#about to read 5, iclass 28, count 2 2006.257.15:27:10.96#ibcon#read 5, iclass 28, count 2 2006.257.15:27:10.96#ibcon#about to read 6, iclass 28, count 2 2006.257.15:27:10.96#ibcon#read 6, iclass 28, count 2 2006.257.15:27:10.96#ibcon#end of sib2, iclass 28, count 2 2006.257.15:27:10.96#ibcon#*after write, iclass 28, count 2 2006.257.15:27:10.96#ibcon#*before return 0, iclass 28, count 2 2006.257.15:27:10.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:10.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:10.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.15:27:10.96#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:10.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:11.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:11.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:11.08#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:27:11.08#ibcon#first serial, iclass 28, count 0 2006.257.15:27:11.08#ibcon#enter sib2, iclass 28, count 0 2006.257.15:27:11.08#ibcon#flushed, iclass 28, count 0 2006.257.15:27:11.08#ibcon#about to write, iclass 28, count 0 2006.257.15:27:11.08#ibcon#wrote, iclass 28, count 0 2006.257.15:27:11.08#ibcon#about to read 3, iclass 28, count 0 2006.257.15:27:11.10#ibcon#read 3, iclass 28, count 0 2006.257.15:27:11.10#ibcon#about to read 4, iclass 28, count 0 2006.257.15:27:11.10#ibcon#read 4, iclass 28, count 0 2006.257.15:27:11.10#ibcon#about to read 5, iclass 28, count 0 2006.257.15:27:11.10#ibcon#read 5, iclass 28, count 0 2006.257.15:27:11.10#ibcon#about to read 6, iclass 28, count 0 2006.257.15:27:11.10#ibcon#read 6, iclass 28, count 0 2006.257.15:27:11.10#ibcon#end of sib2, iclass 28, count 0 2006.257.15:27:11.10#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:27:11.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:27:11.10#ibcon#[25=USB\r\n] 2006.257.15:27:11.10#ibcon#*before write, iclass 28, count 0 2006.257.15:27:11.10#ibcon#enter sib2, iclass 28, count 0 2006.257.15:27:11.10#ibcon#flushed, iclass 28, count 0 2006.257.15:27:11.10#ibcon#about to write, iclass 28, count 0 2006.257.15:27:11.10#ibcon#wrote, iclass 28, count 0 2006.257.15:27:11.10#ibcon#about to read 3, iclass 28, count 0 2006.257.15:27:11.13#ibcon#read 3, iclass 28, count 0 2006.257.15:27:11.13#ibcon#about to read 4, iclass 28, count 0 2006.257.15:27:11.13#ibcon#read 4, iclass 28, count 0 2006.257.15:27:11.13#ibcon#about to read 5, iclass 28, count 0 2006.257.15:27:11.13#ibcon#read 5, iclass 28, count 0 2006.257.15:27:11.13#ibcon#about to read 6, iclass 28, count 0 2006.257.15:27:11.13#ibcon#read 6, iclass 28, count 0 2006.257.15:27:11.13#ibcon#end of sib2, iclass 28, count 0 2006.257.15:27:11.13#ibcon#*after write, iclass 28, count 0 2006.257.15:27:11.13#ibcon#*before return 0, iclass 28, count 0 2006.257.15:27:11.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:11.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:11.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:27:11.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:27:11.13$vck44/valo=3,564.99 2006.257.15:27:11.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.15:27:11.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.15:27:11.13#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:11.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:11.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:11.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:11.13#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:27:11.13#ibcon#first serial, iclass 30, count 0 2006.257.15:27:11.13#ibcon#enter sib2, iclass 30, count 0 2006.257.15:27:11.13#ibcon#flushed, iclass 30, count 0 2006.257.15:27:11.13#ibcon#about to write, iclass 30, count 0 2006.257.15:27:11.13#ibcon#wrote, iclass 30, count 0 2006.257.15:27:11.13#ibcon#about to read 3, iclass 30, count 0 2006.257.15:27:11.15#ibcon#read 3, iclass 30, count 0 2006.257.15:27:11.15#ibcon#about to read 4, iclass 30, count 0 2006.257.15:27:11.15#ibcon#read 4, iclass 30, count 0 2006.257.15:27:11.15#ibcon#about to read 5, iclass 30, count 0 2006.257.15:27:11.15#ibcon#read 5, iclass 30, count 0 2006.257.15:27:11.15#ibcon#about to read 6, iclass 30, count 0 2006.257.15:27:11.15#ibcon#read 6, iclass 30, count 0 2006.257.15:27:11.15#ibcon#end of sib2, iclass 30, count 0 2006.257.15:27:11.15#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:27:11.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:27:11.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:27:11.15#ibcon#*before write, iclass 30, count 0 2006.257.15:27:11.15#ibcon#enter sib2, iclass 30, count 0 2006.257.15:27:11.15#ibcon#flushed, iclass 30, count 0 2006.257.15:27:11.15#ibcon#about to write, iclass 30, count 0 2006.257.15:27:11.15#ibcon#wrote, iclass 30, count 0 2006.257.15:27:11.15#ibcon#about to read 3, iclass 30, count 0 2006.257.15:27:11.19#ibcon#read 3, iclass 30, count 0 2006.257.15:27:11.19#ibcon#about to read 4, iclass 30, count 0 2006.257.15:27:11.19#ibcon#read 4, iclass 30, count 0 2006.257.15:27:11.19#ibcon#about to read 5, iclass 30, count 0 2006.257.15:27:11.19#ibcon#read 5, iclass 30, count 0 2006.257.15:27:11.19#ibcon#about to read 6, iclass 30, count 0 2006.257.15:27:11.19#ibcon#read 6, iclass 30, count 0 2006.257.15:27:11.19#ibcon#end of sib2, iclass 30, count 0 2006.257.15:27:11.19#ibcon#*after write, iclass 30, count 0 2006.257.15:27:11.19#ibcon#*before return 0, iclass 30, count 0 2006.257.15:27:11.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:11.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:11.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:27:11.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:27:11.19$vck44/va=3,8 2006.257.15:27:11.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.15:27:11.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.15:27:11.19#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:11.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:11.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:11.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:11.25#ibcon#enter wrdev, iclass 32, count 2 2006.257.15:27:11.25#ibcon#first serial, iclass 32, count 2 2006.257.15:27:11.25#ibcon#enter sib2, iclass 32, count 2 2006.257.15:27:11.25#ibcon#flushed, iclass 32, count 2 2006.257.15:27:11.25#ibcon#about to write, iclass 32, count 2 2006.257.15:27:11.25#ibcon#wrote, iclass 32, count 2 2006.257.15:27:11.25#ibcon#about to read 3, iclass 32, count 2 2006.257.15:27:11.27#ibcon#read 3, iclass 32, count 2 2006.257.15:27:11.27#ibcon#about to read 4, iclass 32, count 2 2006.257.15:27:11.27#ibcon#read 4, iclass 32, count 2 2006.257.15:27:11.27#ibcon#about to read 5, iclass 32, count 2 2006.257.15:27:11.27#ibcon#read 5, iclass 32, count 2 2006.257.15:27:11.27#ibcon#about to read 6, iclass 32, count 2 2006.257.15:27:11.27#ibcon#read 6, iclass 32, count 2 2006.257.15:27:11.27#ibcon#end of sib2, iclass 32, count 2 2006.257.15:27:11.27#ibcon#*mode == 0, iclass 32, count 2 2006.257.15:27:11.27#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.15:27:11.27#ibcon#[25=AT03-08\r\n] 2006.257.15:27:11.27#ibcon#*before write, iclass 32, count 2 2006.257.15:27:11.27#ibcon#enter sib2, iclass 32, count 2 2006.257.15:27:11.27#ibcon#flushed, iclass 32, count 2 2006.257.15:27:11.27#ibcon#about to write, iclass 32, count 2 2006.257.15:27:11.27#ibcon#wrote, iclass 32, count 2 2006.257.15:27:11.27#ibcon#about to read 3, iclass 32, count 2 2006.257.15:27:11.30#ibcon#read 3, iclass 32, count 2 2006.257.15:27:11.30#ibcon#about to read 4, iclass 32, count 2 2006.257.15:27:11.30#ibcon#read 4, iclass 32, count 2 2006.257.15:27:11.30#ibcon#about to read 5, iclass 32, count 2 2006.257.15:27:11.30#ibcon#read 5, iclass 32, count 2 2006.257.15:27:11.30#ibcon#about to read 6, iclass 32, count 2 2006.257.15:27:11.30#ibcon#read 6, iclass 32, count 2 2006.257.15:27:11.30#ibcon#end of sib2, iclass 32, count 2 2006.257.15:27:11.30#ibcon#*after write, iclass 32, count 2 2006.257.15:27:11.30#ibcon#*before return 0, iclass 32, count 2 2006.257.15:27:11.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:11.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:11.30#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.15:27:11.30#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:11.30#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:11.42#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:11.42#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:11.42#ibcon#enter wrdev, iclass 32, count 0 2006.257.15:27:11.42#ibcon#first serial, iclass 32, count 0 2006.257.15:27:11.42#ibcon#enter sib2, iclass 32, count 0 2006.257.15:27:11.42#ibcon#flushed, iclass 32, count 0 2006.257.15:27:11.42#ibcon#about to write, iclass 32, count 0 2006.257.15:27:11.42#ibcon#wrote, iclass 32, count 0 2006.257.15:27:11.42#ibcon#about to read 3, iclass 32, count 0 2006.257.15:27:11.44#ibcon#read 3, iclass 32, count 0 2006.257.15:27:11.44#ibcon#about to read 4, iclass 32, count 0 2006.257.15:27:11.44#ibcon#read 4, iclass 32, count 0 2006.257.15:27:11.44#ibcon#about to read 5, iclass 32, count 0 2006.257.15:27:11.44#ibcon#read 5, iclass 32, count 0 2006.257.15:27:11.44#ibcon#about to read 6, iclass 32, count 0 2006.257.15:27:11.44#ibcon#read 6, iclass 32, count 0 2006.257.15:27:11.44#ibcon#end of sib2, iclass 32, count 0 2006.257.15:27:11.44#ibcon#*mode == 0, iclass 32, count 0 2006.257.15:27:11.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.15:27:11.44#ibcon#[25=USB\r\n] 2006.257.15:27:11.44#ibcon#*before write, iclass 32, count 0 2006.257.15:27:11.44#ibcon#enter sib2, iclass 32, count 0 2006.257.15:27:11.44#ibcon#flushed, iclass 32, count 0 2006.257.15:27:11.44#ibcon#about to write, iclass 32, count 0 2006.257.15:27:11.44#ibcon#wrote, iclass 32, count 0 2006.257.15:27:11.44#ibcon#about to read 3, iclass 32, count 0 2006.257.15:27:11.47#ibcon#read 3, iclass 32, count 0 2006.257.15:27:11.47#ibcon#about to read 4, iclass 32, count 0 2006.257.15:27:11.47#ibcon#read 4, iclass 32, count 0 2006.257.15:27:11.47#ibcon#about to read 5, iclass 32, count 0 2006.257.15:27:11.47#ibcon#read 5, iclass 32, count 0 2006.257.15:27:11.47#ibcon#about to read 6, iclass 32, count 0 2006.257.15:27:11.47#ibcon#read 6, iclass 32, count 0 2006.257.15:27:11.47#ibcon#end of sib2, iclass 32, count 0 2006.257.15:27:11.47#ibcon#*after write, iclass 32, count 0 2006.257.15:27:11.47#ibcon#*before return 0, iclass 32, count 0 2006.257.15:27:11.47#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:11.47#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:11.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.15:27:11.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.15:27:11.47$vck44/valo=4,624.99 2006.257.15:27:11.47#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.15:27:11.47#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.15:27:11.47#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:11.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:11.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:11.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:11.47#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:27:11.47#ibcon#first serial, iclass 34, count 0 2006.257.15:27:11.47#ibcon#enter sib2, iclass 34, count 0 2006.257.15:27:11.47#ibcon#flushed, iclass 34, count 0 2006.257.15:27:11.47#ibcon#about to write, iclass 34, count 0 2006.257.15:27:11.47#ibcon#wrote, iclass 34, count 0 2006.257.15:27:11.47#ibcon#about to read 3, iclass 34, count 0 2006.257.15:27:11.49#ibcon#read 3, iclass 34, count 0 2006.257.15:27:11.49#ibcon#about to read 4, iclass 34, count 0 2006.257.15:27:11.49#ibcon#read 4, iclass 34, count 0 2006.257.15:27:11.49#ibcon#about to read 5, iclass 34, count 0 2006.257.15:27:11.49#ibcon#read 5, iclass 34, count 0 2006.257.15:27:11.49#ibcon#about to read 6, iclass 34, count 0 2006.257.15:27:11.49#ibcon#read 6, iclass 34, count 0 2006.257.15:27:11.49#ibcon#end of sib2, iclass 34, count 0 2006.257.15:27:11.49#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:27:11.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:27:11.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:27:11.49#ibcon#*before write, iclass 34, count 0 2006.257.15:27:11.49#ibcon#enter sib2, iclass 34, count 0 2006.257.15:27:11.49#ibcon#flushed, iclass 34, count 0 2006.257.15:27:11.49#ibcon#about to write, iclass 34, count 0 2006.257.15:27:11.49#ibcon#wrote, iclass 34, count 0 2006.257.15:27:11.49#ibcon#about to read 3, iclass 34, count 0 2006.257.15:27:11.53#ibcon#read 3, iclass 34, count 0 2006.257.15:27:11.53#ibcon#about to read 4, iclass 34, count 0 2006.257.15:27:11.53#ibcon#read 4, iclass 34, count 0 2006.257.15:27:11.53#ibcon#about to read 5, iclass 34, count 0 2006.257.15:27:11.53#ibcon#read 5, iclass 34, count 0 2006.257.15:27:11.53#ibcon#about to read 6, iclass 34, count 0 2006.257.15:27:11.53#ibcon#read 6, iclass 34, count 0 2006.257.15:27:11.53#ibcon#end of sib2, iclass 34, count 0 2006.257.15:27:11.53#ibcon#*after write, iclass 34, count 0 2006.257.15:27:11.53#ibcon#*before return 0, iclass 34, count 0 2006.257.15:27:11.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:11.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:11.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:27:11.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:27:11.53$vck44/va=4,7 2006.257.15:27:11.53#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.15:27:11.53#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.15:27:11.53#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:11.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:11.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:11.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:11.59#ibcon#enter wrdev, iclass 36, count 2 2006.257.15:27:11.59#ibcon#first serial, iclass 36, count 2 2006.257.15:27:11.59#ibcon#enter sib2, iclass 36, count 2 2006.257.15:27:11.59#ibcon#flushed, iclass 36, count 2 2006.257.15:27:11.59#ibcon#about to write, iclass 36, count 2 2006.257.15:27:11.59#ibcon#wrote, iclass 36, count 2 2006.257.15:27:11.59#ibcon#about to read 3, iclass 36, count 2 2006.257.15:27:11.61#ibcon#read 3, iclass 36, count 2 2006.257.15:27:11.61#ibcon#about to read 4, iclass 36, count 2 2006.257.15:27:11.61#ibcon#read 4, iclass 36, count 2 2006.257.15:27:11.61#ibcon#about to read 5, iclass 36, count 2 2006.257.15:27:11.61#ibcon#read 5, iclass 36, count 2 2006.257.15:27:11.61#ibcon#about to read 6, iclass 36, count 2 2006.257.15:27:11.61#ibcon#read 6, iclass 36, count 2 2006.257.15:27:11.61#ibcon#end of sib2, iclass 36, count 2 2006.257.15:27:11.61#ibcon#*mode == 0, iclass 36, count 2 2006.257.15:27:11.61#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.15:27:11.61#ibcon#[25=AT04-07\r\n] 2006.257.15:27:11.61#ibcon#*before write, iclass 36, count 2 2006.257.15:27:11.61#ibcon#enter sib2, iclass 36, count 2 2006.257.15:27:11.61#ibcon#flushed, iclass 36, count 2 2006.257.15:27:11.61#ibcon#about to write, iclass 36, count 2 2006.257.15:27:11.61#ibcon#wrote, iclass 36, count 2 2006.257.15:27:11.61#ibcon#about to read 3, iclass 36, count 2 2006.257.15:27:11.64#ibcon#read 3, iclass 36, count 2 2006.257.15:27:11.64#ibcon#about to read 4, iclass 36, count 2 2006.257.15:27:11.64#ibcon#read 4, iclass 36, count 2 2006.257.15:27:11.64#ibcon#about to read 5, iclass 36, count 2 2006.257.15:27:11.64#ibcon#read 5, iclass 36, count 2 2006.257.15:27:11.64#ibcon#about to read 6, iclass 36, count 2 2006.257.15:27:11.64#ibcon#read 6, iclass 36, count 2 2006.257.15:27:11.64#ibcon#end of sib2, iclass 36, count 2 2006.257.15:27:11.64#ibcon#*after write, iclass 36, count 2 2006.257.15:27:11.64#ibcon#*before return 0, iclass 36, count 2 2006.257.15:27:11.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:11.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:11.64#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.15:27:11.64#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:11.64#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:11.76#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:11.76#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:11.76#ibcon#enter wrdev, iclass 36, count 0 2006.257.15:27:11.76#ibcon#first serial, iclass 36, count 0 2006.257.15:27:11.76#ibcon#enter sib2, iclass 36, count 0 2006.257.15:27:11.76#ibcon#flushed, iclass 36, count 0 2006.257.15:27:11.76#ibcon#about to write, iclass 36, count 0 2006.257.15:27:11.76#ibcon#wrote, iclass 36, count 0 2006.257.15:27:11.76#ibcon#about to read 3, iclass 36, count 0 2006.257.15:27:11.78#ibcon#read 3, iclass 36, count 0 2006.257.15:27:11.78#ibcon#about to read 4, iclass 36, count 0 2006.257.15:27:11.78#ibcon#read 4, iclass 36, count 0 2006.257.15:27:11.78#ibcon#about to read 5, iclass 36, count 0 2006.257.15:27:11.78#ibcon#read 5, iclass 36, count 0 2006.257.15:27:11.78#ibcon#about to read 6, iclass 36, count 0 2006.257.15:27:11.78#ibcon#read 6, iclass 36, count 0 2006.257.15:27:11.78#ibcon#end of sib2, iclass 36, count 0 2006.257.15:27:11.78#ibcon#*mode == 0, iclass 36, count 0 2006.257.15:27:11.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.15:27:11.78#ibcon#[25=USB\r\n] 2006.257.15:27:11.78#ibcon#*before write, iclass 36, count 0 2006.257.15:27:11.78#ibcon#enter sib2, iclass 36, count 0 2006.257.15:27:11.78#ibcon#flushed, iclass 36, count 0 2006.257.15:27:11.78#ibcon#about to write, iclass 36, count 0 2006.257.15:27:11.78#ibcon#wrote, iclass 36, count 0 2006.257.15:27:11.78#ibcon#about to read 3, iclass 36, count 0 2006.257.15:27:11.81#ibcon#read 3, iclass 36, count 0 2006.257.15:27:11.81#ibcon#about to read 4, iclass 36, count 0 2006.257.15:27:11.81#ibcon#read 4, iclass 36, count 0 2006.257.15:27:11.81#ibcon#about to read 5, iclass 36, count 0 2006.257.15:27:11.81#ibcon#read 5, iclass 36, count 0 2006.257.15:27:11.81#ibcon#about to read 6, iclass 36, count 0 2006.257.15:27:11.81#ibcon#read 6, iclass 36, count 0 2006.257.15:27:11.81#ibcon#end of sib2, iclass 36, count 0 2006.257.15:27:11.81#ibcon#*after write, iclass 36, count 0 2006.257.15:27:11.81#ibcon#*before return 0, iclass 36, count 0 2006.257.15:27:11.81#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:11.81#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:11.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.15:27:11.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.15:27:11.81$vck44/valo=5,734.99 2006.257.15:27:11.81#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.15:27:11.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.15:27:11.81#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:11.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:11.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:11.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:11.81#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:27:11.81#ibcon#first serial, iclass 38, count 0 2006.257.15:27:11.81#ibcon#enter sib2, iclass 38, count 0 2006.257.15:27:11.81#ibcon#flushed, iclass 38, count 0 2006.257.15:27:11.81#ibcon#about to write, iclass 38, count 0 2006.257.15:27:11.81#ibcon#wrote, iclass 38, count 0 2006.257.15:27:11.81#ibcon#about to read 3, iclass 38, count 0 2006.257.15:27:11.83#ibcon#read 3, iclass 38, count 0 2006.257.15:27:11.83#ibcon#about to read 4, iclass 38, count 0 2006.257.15:27:11.83#ibcon#read 4, iclass 38, count 0 2006.257.15:27:11.83#ibcon#about to read 5, iclass 38, count 0 2006.257.15:27:11.83#ibcon#read 5, iclass 38, count 0 2006.257.15:27:11.83#ibcon#about to read 6, iclass 38, count 0 2006.257.15:27:11.83#ibcon#read 6, iclass 38, count 0 2006.257.15:27:11.83#ibcon#end of sib2, iclass 38, count 0 2006.257.15:27:11.83#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:27:11.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:27:11.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:27:11.83#ibcon#*before write, iclass 38, count 0 2006.257.15:27:11.83#ibcon#enter sib2, iclass 38, count 0 2006.257.15:27:11.83#ibcon#flushed, iclass 38, count 0 2006.257.15:27:11.83#ibcon#about to write, iclass 38, count 0 2006.257.15:27:11.83#ibcon#wrote, iclass 38, count 0 2006.257.15:27:11.83#ibcon#about to read 3, iclass 38, count 0 2006.257.15:27:11.87#ibcon#read 3, iclass 38, count 0 2006.257.15:27:11.87#ibcon#about to read 4, iclass 38, count 0 2006.257.15:27:11.87#ibcon#read 4, iclass 38, count 0 2006.257.15:27:11.87#ibcon#about to read 5, iclass 38, count 0 2006.257.15:27:11.87#ibcon#read 5, iclass 38, count 0 2006.257.15:27:11.87#ibcon#about to read 6, iclass 38, count 0 2006.257.15:27:11.87#ibcon#read 6, iclass 38, count 0 2006.257.15:27:11.87#ibcon#end of sib2, iclass 38, count 0 2006.257.15:27:11.87#ibcon#*after write, iclass 38, count 0 2006.257.15:27:11.87#ibcon#*before return 0, iclass 38, count 0 2006.257.15:27:11.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:11.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:11.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:27:11.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:27:11.87$vck44/va=5,4 2006.257.15:27:11.87#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.15:27:11.87#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.15:27:11.87#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:11.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:11.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:11.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:11.93#ibcon#enter wrdev, iclass 40, count 2 2006.257.15:27:11.93#ibcon#first serial, iclass 40, count 2 2006.257.15:27:11.93#ibcon#enter sib2, iclass 40, count 2 2006.257.15:27:11.93#ibcon#flushed, iclass 40, count 2 2006.257.15:27:11.93#ibcon#about to write, iclass 40, count 2 2006.257.15:27:11.93#ibcon#wrote, iclass 40, count 2 2006.257.15:27:11.93#ibcon#about to read 3, iclass 40, count 2 2006.257.15:27:11.95#ibcon#read 3, iclass 40, count 2 2006.257.15:27:11.95#ibcon#about to read 4, iclass 40, count 2 2006.257.15:27:11.95#ibcon#read 4, iclass 40, count 2 2006.257.15:27:11.95#ibcon#about to read 5, iclass 40, count 2 2006.257.15:27:11.95#ibcon#read 5, iclass 40, count 2 2006.257.15:27:11.95#ibcon#about to read 6, iclass 40, count 2 2006.257.15:27:11.95#ibcon#read 6, iclass 40, count 2 2006.257.15:27:11.95#ibcon#end of sib2, iclass 40, count 2 2006.257.15:27:11.95#ibcon#*mode == 0, iclass 40, count 2 2006.257.15:27:11.95#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.15:27:11.95#ibcon#[25=AT05-04\r\n] 2006.257.15:27:11.95#ibcon#*before write, iclass 40, count 2 2006.257.15:27:11.95#ibcon#enter sib2, iclass 40, count 2 2006.257.15:27:11.95#ibcon#flushed, iclass 40, count 2 2006.257.15:27:11.95#ibcon#about to write, iclass 40, count 2 2006.257.15:27:11.95#ibcon#wrote, iclass 40, count 2 2006.257.15:27:11.95#ibcon#about to read 3, iclass 40, count 2 2006.257.15:27:11.98#ibcon#read 3, iclass 40, count 2 2006.257.15:27:11.98#ibcon#about to read 4, iclass 40, count 2 2006.257.15:27:11.98#ibcon#read 4, iclass 40, count 2 2006.257.15:27:11.98#ibcon#about to read 5, iclass 40, count 2 2006.257.15:27:11.98#ibcon#read 5, iclass 40, count 2 2006.257.15:27:11.98#ibcon#about to read 6, iclass 40, count 2 2006.257.15:27:11.98#ibcon#read 6, iclass 40, count 2 2006.257.15:27:11.98#ibcon#end of sib2, iclass 40, count 2 2006.257.15:27:11.98#ibcon#*after write, iclass 40, count 2 2006.257.15:27:11.98#ibcon#*before return 0, iclass 40, count 2 2006.257.15:27:11.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:11.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:11.98#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.15:27:11.98#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:11.98#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:12.10#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:12.10#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:12.10#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:27:12.10#ibcon#first serial, iclass 40, count 0 2006.257.15:27:12.10#ibcon#enter sib2, iclass 40, count 0 2006.257.15:27:12.10#ibcon#flushed, iclass 40, count 0 2006.257.15:27:12.10#ibcon#about to write, iclass 40, count 0 2006.257.15:27:12.10#ibcon#wrote, iclass 40, count 0 2006.257.15:27:12.10#ibcon#about to read 3, iclass 40, count 0 2006.257.15:27:12.12#ibcon#read 3, iclass 40, count 0 2006.257.15:27:12.12#ibcon#about to read 4, iclass 40, count 0 2006.257.15:27:12.12#ibcon#read 4, iclass 40, count 0 2006.257.15:27:12.12#ibcon#about to read 5, iclass 40, count 0 2006.257.15:27:12.12#ibcon#read 5, iclass 40, count 0 2006.257.15:27:12.12#ibcon#about to read 6, iclass 40, count 0 2006.257.15:27:12.12#ibcon#read 6, iclass 40, count 0 2006.257.15:27:12.12#ibcon#end of sib2, iclass 40, count 0 2006.257.15:27:12.12#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:27:12.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:27:12.12#ibcon#[25=USB\r\n] 2006.257.15:27:12.12#ibcon#*before write, iclass 40, count 0 2006.257.15:27:12.12#ibcon#enter sib2, iclass 40, count 0 2006.257.15:27:12.12#ibcon#flushed, iclass 40, count 0 2006.257.15:27:12.12#ibcon#about to write, iclass 40, count 0 2006.257.15:27:12.12#ibcon#wrote, iclass 40, count 0 2006.257.15:27:12.12#ibcon#about to read 3, iclass 40, count 0 2006.257.15:27:12.15#ibcon#read 3, iclass 40, count 0 2006.257.15:27:12.15#ibcon#about to read 4, iclass 40, count 0 2006.257.15:27:12.15#ibcon#read 4, iclass 40, count 0 2006.257.15:27:12.15#ibcon#about to read 5, iclass 40, count 0 2006.257.15:27:12.15#ibcon#read 5, iclass 40, count 0 2006.257.15:27:12.15#ibcon#about to read 6, iclass 40, count 0 2006.257.15:27:12.15#ibcon#read 6, iclass 40, count 0 2006.257.15:27:12.15#ibcon#end of sib2, iclass 40, count 0 2006.257.15:27:12.15#ibcon#*after write, iclass 40, count 0 2006.257.15:27:12.15#ibcon#*before return 0, iclass 40, count 0 2006.257.15:27:12.15#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:12.15#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:12.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:27:12.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:27:12.15$vck44/valo=6,814.99 2006.257.15:27:12.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.15:27:12.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.15:27:12.15#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:12.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:12.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:12.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:12.15#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:27:12.15#ibcon#first serial, iclass 4, count 0 2006.257.15:27:12.15#ibcon#enter sib2, iclass 4, count 0 2006.257.15:27:12.15#ibcon#flushed, iclass 4, count 0 2006.257.15:27:12.15#ibcon#about to write, iclass 4, count 0 2006.257.15:27:12.15#ibcon#wrote, iclass 4, count 0 2006.257.15:27:12.15#ibcon#about to read 3, iclass 4, count 0 2006.257.15:27:12.17#ibcon#read 3, iclass 4, count 0 2006.257.15:27:12.17#ibcon#about to read 4, iclass 4, count 0 2006.257.15:27:12.17#ibcon#read 4, iclass 4, count 0 2006.257.15:27:12.17#ibcon#about to read 5, iclass 4, count 0 2006.257.15:27:12.17#ibcon#read 5, iclass 4, count 0 2006.257.15:27:12.17#ibcon#about to read 6, iclass 4, count 0 2006.257.15:27:12.17#ibcon#read 6, iclass 4, count 0 2006.257.15:27:12.17#ibcon#end of sib2, iclass 4, count 0 2006.257.15:27:12.17#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:27:12.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:27:12.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:27:12.17#ibcon#*before write, iclass 4, count 0 2006.257.15:27:12.17#ibcon#enter sib2, iclass 4, count 0 2006.257.15:27:12.17#ibcon#flushed, iclass 4, count 0 2006.257.15:27:12.17#ibcon#about to write, iclass 4, count 0 2006.257.15:27:12.17#ibcon#wrote, iclass 4, count 0 2006.257.15:27:12.17#ibcon#about to read 3, iclass 4, count 0 2006.257.15:27:12.21#ibcon#read 3, iclass 4, count 0 2006.257.15:27:12.21#ibcon#about to read 4, iclass 4, count 0 2006.257.15:27:12.21#ibcon#read 4, iclass 4, count 0 2006.257.15:27:12.21#ibcon#about to read 5, iclass 4, count 0 2006.257.15:27:12.21#ibcon#read 5, iclass 4, count 0 2006.257.15:27:12.21#ibcon#about to read 6, iclass 4, count 0 2006.257.15:27:12.21#ibcon#read 6, iclass 4, count 0 2006.257.15:27:12.21#ibcon#end of sib2, iclass 4, count 0 2006.257.15:27:12.21#ibcon#*after write, iclass 4, count 0 2006.257.15:27:12.21#ibcon#*before return 0, iclass 4, count 0 2006.257.15:27:12.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:12.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:12.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:27:12.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:27:12.21$vck44/va=6,4 2006.257.15:27:12.21#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.15:27:12.21#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.15:27:12.21#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:12.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:12.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:12.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:12.27#ibcon#enter wrdev, iclass 6, count 2 2006.257.15:27:12.27#ibcon#first serial, iclass 6, count 2 2006.257.15:27:12.27#ibcon#enter sib2, iclass 6, count 2 2006.257.15:27:12.27#ibcon#flushed, iclass 6, count 2 2006.257.15:27:12.27#ibcon#about to write, iclass 6, count 2 2006.257.15:27:12.27#ibcon#wrote, iclass 6, count 2 2006.257.15:27:12.27#ibcon#about to read 3, iclass 6, count 2 2006.257.15:27:12.29#ibcon#read 3, iclass 6, count 2 2006.257.15:27:12.29#ibcon#about to read 4, iclass 6, count 2 2006.257.15:27:12.29#ibcon#read 4, iclass 6, count 2 2006.257.15:27:12.29#ibcon#about to read 5, iclass 6, count 2 2006.257.15:27:12.29#ibcon#read 5, iclass 6, count 2 2006.257.15:27:12.29#ibcon#about to read 6, iclass 6, count 2 2006.257.15:27:12.29#ibcon#read 6, iclass 6, count 2 2006.257.15:27:12.29#ibcon#end of sib2, iclass 6, count 2 2006.257.15:27:12.29#ibcon#*mode == 0, iclass 6, count 2 2006.257.15:27:12.29#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.15:27:12.29#ibcon#[25=AT06-04\r\n] 2006.257.15:27:12.29#ibcon#*before write, iclass 6, count 2 2006.257.15:27:12.29#ibcon#enter sib2, iclass 6, count 2 2006.257.15:27:12.29#ibcon#flushed, iclass 6, count 2 2006.257.15:27:12.29#ibcon#about to write, iclass 6, count 2 2006.257.15:27:12.29#ibcon#wrote, iclass 6, count 2 2006.257.15:27:12.29#ibcon#about to read 3, iclass 6, count 2 2006.257.15:27:12.32#ibcon#read 3, iclass 6, count 2 2006.257.15:27:12.32#ibcon#about to read 4, iclass 6, count 2 2006.257.15:27:12.32#ibcon#read 4, iclass 6, count 2 2006.257.15:27:12.32#ibcon#about to read 5, iclass 6, count 2 2006.257.15:27:12.32#ibcon#read 5, iclass 6, count 2 2006.257.15:27:12.32#ibcon#about to read 6, iclass 6, count 2 2006.257.15:27:12.32#ibcon#read 6, iclass 6, count 2 2006.257.15:27:12.32#ibcon#end of sib2, iclass 6, count 2 2006.257.15:27:12.32#ibcon#*after write, iclass 6, count 2 2006.257.15:27:12.32#ibcon#*before return 0, iclass 6, count 2 2006.257.15:27:12.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:12.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:12.32#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.15:27:12.32#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:12.32#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:12.44#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:12.44#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:12.44#ibcon#enter wrdev, iclass 6, count 0 2006.257.15:27:12.44#ibcon#first serial, iclass 6, count 0 2006.257.15:27:12.44#ibcon#enter sib2, iclass 6, count 0 2006.257.15:27:12.44#ibcon#flushed, iclass 6, count 0 2006.257.15:27:12.44#ibcon#about to write, iclass 6, count 0 2006.257.15:27:12.44#ibcon#wrote, iclass 6, count 0 2006.257.15:27:12.44#ibcon#about to read 3, iclass 6, count 0 2006.257.15:27:12.46#ibcon#read 3, iclass 6, count 0 2006.257.15:27:12.46#ibcon#about to read 4, iclass 6, count 0 2006.257.15:27:12.46#ibcon#read 4, iclass 6, count 0 2006.257.15:27:12.46#ibcon#about to read 5, iclass 6, count 0 2006.257.15:27:12.46#ibcon#read 5, iclass 6, count 0 2006.257.15:27:12.46#ibcon#about to read 6, iclass 6, count 0 2006.257.15:27:12.46#ibcon#read 6, iclass 6, count 0 2006.257.15:27:12.46#ibcon#end of sib2, iclass 6, count 0 2006.257.15:27:12.46#ibcon#*mode == 0, iclass 6, count 0 2006.257.15:27:12.46#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.15:27:12.46#ibcon#[25=USB\r\n] 2006.257.15:27:12.46#ibcon#*before write, iclass 6, count 0 2006.257.15:27:12.46#ibcon#enter sib2, iclass 6, count 0 2006.257.15:27:12.46#ibcon#flushed, iclass 6, count 0 2006.257.15:27:12.46#ibcon#about to write, iclass 6, count 0 2006.257.15:27:12.46#ibcon#wrote, iclass 6, count 0 2006.257.15:27:12.46#ibcon#about to read 3, iclass 6, count 0 2006.257.15:27:12.49#ibcon#read 3, iclass 6, count 0 2006.257.15:27:12.49#ibcon#about to read 4, iclass 6, count 0 2006.257.15:27:12.49#ibcon#read 4, iclass 6, count 0 2006.257.15:27:12.49#ibcon#about to read 5, iclass 6, count 0 2006.257.15:27:12.49#ibcon#read 5, iclass 6, count 0 2006.257.15:27:12.49#ibcon#about to read 6, iclass 6, count 0 2006.257.15:27:12.49#ibcon#read 6, iclass 6, count 0 2006.257.15:27:12.49#ibcon#end of sib2, iclass 6, count 0 2006.257.15:27:12.49#ibcon#*after write, iclass 6, count 0 2006.257.15:27:12.49#ibcon#*before return 0, iclass 6, count 0 2006.257.15:27:12.49#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:12.49#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:12.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.15:27:12.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.15:27:12.49$vck44/valo=7,864.99 2006.257.15:27:12.49#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.15:27:12.49#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.15:27:12.49#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:12.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:12.49#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:12.49#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:12.49#ibcon#enter wrdev, iclass 10, count 0 2006.257.15:27:12.49#ibcon#first serial, iclass 10, count 0 2006.257.15:27:12.49#ibcon#enter sib2, iclass 10, count 0 2006.257.15:27:12.49#ibcon#flushed, iclass 10, count 0 2006.257.15:27:12.49#ibcon#about to write, iclass 10, count 0 2006.257.15:27:12.49#ibcon#wrote, iclass 10, count 0 2006.257.15:27:12.49#ibcon#about to read 3, iclass 10, count 0 2006.257.15:27:12.51#ibcon#read 3, iclass 10, count 0 2006.257.15:27:12.51#ibcon#about to read 4, iclass 10, count 0 2006.257.15:27:12.51#ibcon#read 4, iclass 10, count 0 2006.257.15:27:12.51#ibcon#about to read 5, iclass 10, count 0 2006.257.15:27:12.51#ibcon#read 5, iclass 10, count 0 2006.257.15:27:12.51#ibcon#about to read 6, iclass 10, count 0 2006.257.15:27:12.51#ibcon#read 6, iclass 10, count 0 2006.257.15:27:12.51#ibcon#end of sib2, iclass 10, count 0 2006.257.15:27:12.51#ibcon#*mode == 0, iclass 10, count 0 2006.257.15:27:12.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.15:27:12.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:27:12.51#ibcon#*before write, iclass 10, count 0 2006.257.15:27:12.51#ibcon#enter sib2, iclass 10, count 0 2006.257.15:27:12.51#ibcon#flushed, iclass 10, count 0 2006.257.15:27:12.51#ibcon#about to write, iclass 10, count 0 2006.257.15:27:12.51#ibcon#wrote, iclass 10, count 0 2006.257.15:27:12.51#ibcon#about to read 3, iclass 10, count 0 2006.257.15:27:12.55#ibcon#read 3, iclass 10, count 0 2006.257.15:27:12.55#ibcon#about to read 4, iclass 10, count 0 2006.257.15:27:12.55#ibcon#read 4, iclass 10, count 0 2006.257.15:27:12.55#ibcon#about to read 5, iclass 10, count 0 2006.257.15:27:12.55#ibcon#read 5, iclass 10, count 0 2006.257.15:27:12.55#ibcon#about to read 6, iclass 10, count 0 2006.257.15:27:12.55#ibcon#read 6, iclass 10, count 0 2006.257.15:27:12.55#ibcon#end of sib2, iclass 10, count 0 2006.257.15:27:12.55#ibcon#*after write, iclass 10, count 0 2006.257.15:27:12.55#ibcon#*before return 0, iclass 10, count 0 2006.257.15:27:12.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:12.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:12.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.15:27:12.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.15:27:12.55$vck44/va=7,4 2006.257.15:27:12.55#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.15:27:12.55#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.15:27:12.55#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:12.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:12.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:12.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:12.61#ibcon#enter wrdev, iclass 12, count 2 2006.257.15:27:12.61#ibcon#first serial, iclass 12, count 2 2006.257.15:27:12.61#ibcon#enter sib2, iclass 12, count 2 2006.257.15:27:12.61#ibcon#flushed, iclass 12, count 2 2006.257.15:27:12.61#ibcon#about to write, iclass 12, count 2 2006.257.15:27:12.61#ibcon#wrote, iclass 12, count 2 2006.257.15:27:12.61#ibcon#about to read 3, iclass 12, count 2 2006.257.15:27:12.63#ibcon#read 3, iclass 12, count 2 2006.257.15:27:12.63#ibcon#about to read 4, iclass 12, count 2 2006.257.15:27:12.63#ibcon#read 4, iclass 12, count 2 2006.257.15:27:12.63#ibcon#about to read 5, iclass 12, count 2 2006.257.15:27:12.63#ibcon#read 5, iclass 12, count 2 2006.257.15:27:12.63#ibcon#about to read 6, iclass 12, count 2 2006.257.15:27:12.63#ibcon#read 6, iclass 12, count 2 2006.257.15:27:12.63#ibcon#end of sib2, iclass 12, count 2 2006.257.15:27:12.63#ibcon#*mode == 0, iclass 12, count 2 2006.257.15:27:12.63#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.15:27:12.63#ibcon#[25=AT07-04\r\n] 2006.257.15:27:12.63#ibcon#*before write, iclass 12, count 2 2006.257.15:27:12.63#ibcon#enter sib2, iclass 12, count 2 2006.257.15:27:12.63#ibcon#flushed, iclass 12, count 2 2006.257.15:27:12.63#ibcon#about to write, iclass 12, count 2 2006.257.15:27:12.63#ibcon#wrote, iclass 12, count 2 2006.257.15:27:12.63#ibcon#about to read 3, iclass 12, count 2 2006.257.15:27:12.66#ibcon#read 3, iclass 12, count 2 2006.257.15:27:12.66#ibcon#about to read 4, iclass 12, count 2 2006.257.15:27:12.66#ibcon#read 4, iclass 12, count 2 2006.257.15:27:12.66#ibcon#about to read 5, iclass 12, count 2 2006.257.15:27:12.66#ibcon#read 5, iclass 12, count 2 2006.257.15:27:12.66#ibcon#about to read 6, iclass 12, count 2 2006.257.15:27:12.66#ibcon#read 6, iclass 12, count 2 2006.257.15:27:12.66#ibcon#end of sib2, iclass 12, count 2 2006.257.15:27:12.66#ibcon#*after write, iclass 12, count 2 2006.257.15:27:12.66#ibcon#*before return 0, iclass 12, count 2 2006.257.15:27:12.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:12.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:12.66#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.15:27:12.66#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:12.66#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:12.78#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:12.78#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:12.78#ibcon#enter wrdev, iclass 12, count 0 2006.257.15:27:12.78#ibcon#first serial, iclass 12, count 0 2006.257.15:27:12.78#ibcon#enter sib2, iclass 12, count 0 2006.257.15:27:12.78#ibcon#flushed, iclass 12, count 0 2006.257.15:27:12.78#ibcon#about to write, iclass 12, count 0 2006.257.15:27:12.78#ibcon#wrote, iclass 12, count 0 2006.257.15:27:12.78#ibcon#about to read 3, iclass 12, count 0 2006.257.15:27:12.80#ibcon#read 3, iclass 12, count 0 2006.257.15:27:12.80#ibcon#about to read 4, iclass 12, count 0 2006.257.15:27:12.80#ibcon#read 4, iclass 12, count 0 2006.257.15:27:12.80#ibcon#about to read 5, iclass 12, count 0 2006.257.15:27:12.80#ibcon#read 5, iclass 12, count 0 2006.257.15:27:12.80#ibcon#about to read 6, iclass 12, count 0 2006.257.15:27:12.80#ibcon#read 6, iclass 12, count 0 2006.257.15:27:12.80#ibcon#end of sib2, iclass 12, count 0 2006.257.15:27:12.80#ibcon#*mode == 0, iclass 12, count 0 2006.257.15:27:12.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.15:27:12.80#ibcon#[25=USB\r\n] 2006.257.15:27:12.80#ibcon#*before write, iclass 12, count 0 2006.257.15:27:12.80#ibcon#enter sib2, iclass 12, count 0 2006.257.15:27:12.80#ibcon#flushed, iclass 12, count 0 2006.257.15:27:12.80#ibcon#about to write, iclass 12, count 0 2006.257.15:27:12.80#ibcon#wrote, iclass 12, count 0 2006.257.15:27:12.80#ibcon#about to read 3, iclass 12, count 0 2006.257.15:27:12.83#ibcon#read 3, iclass 12, count 0 2006.257.15:27:12.83#ibcon#about to read 4, iclass 12, count 0 2006.257.15:27:12.83#ibcon#read 4, iclass 12, count 0 2006.257.15:27:12.83#ibcon#about to read 5, iclass 12, count 0 2006.257.15:27:12.83#ibcon#read 5, iclass 12, count 0 2006.257.15:27:12.83#ibcon#about to read 6, iclass 12, count 0 2006.257.15:27:12.83#ibcon#read 6, iclass 12, count 0 2006.257.15:27:12.83#ibcon#end of sib2, iclass 12, count 0 2006.257.15:27:12.83#ibcon#*after write, iclass 12, count 0 2006.257.15:27:12.83#ibcon#*before return 0, iclass 12, count 0 2006.257.15:27:12.83#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:12.83#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:12.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.15:27:12.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.15:27:12.83$vck44/valo=8,884.99 2006.257.15:27:12.83#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.15:27:12.83#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.15:27:12.83#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:12.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:12.83#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:12.83#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:12.83#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:27:12.83#ibcon#first serial, iclass 14, count 0 2006.257.15:27:12.83#ibcon#enter sib2, iclass 14, count 0 2006.257.15:27:12.83#ibcon#flushed, iclass 14, count 0 2006.257.15:27:12.83#ibcon#about to write, iclass 14, count 0 2006.257.15:27:12.83#ibcon#wrote, iclass 14, count 0 2006.257.15:27:12.83#ibcon#about to read 3, iclass 14, count 0 2006.257.15:27:12.85#ibcon#read 3, iclass 14, count 0 2006.257.15:27:12.85#ibcon#about to read 4, iclass 14, count 0 2006.257.15:27:12.85#ibcon#read 4, iclass 14, count 0 2006.257.15:27:12.85#ibcon#about to read 5, iclass 14, count 0 2006.257.15:27:12.85#ibcon#read 5, iclass 14, count 0 2006.257.15:27:12.85#ibcon#about to read 6, iclass 14, count 0 2006.257.15:27:12.85#ibcon#read 6, iclass 14, count 0 2006.257.15:27:12.85#ibcon#end of sib2, iclass 14, count 0 2006.257.15:27:12.85#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:27:12.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:27:12.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:27:12.85#ibcon#*before write, iclass 14, count 0 2006.257.15:27:12.85#ibcon#enter sib2, iclass 14, count 0 2006.257.15:27:12.85#ibcon#flushed, iclass 14, count 0 2006.257.15:27:12.85#ibcon#about to write, iclass 14, count 0 2006.257.15:27:12.85#ibcon#wrote, iclass 14, count 0 2006.257.15:27:12.85#ibcon#about to read 3, iclass 14, count 0 2006.257.15:27:12.89#ibcon#read 3, iclass 14, count 0 2006.257.15:27:12.89#ibcon#about to read 4, iclass 14, count 0 2006.257.15:27:12.89#ibcon#read 4, iclass 14, count 0 2006.257.15:27:12.89#ibcon#about to read 5, iclass 14, count 0 2006.257.15:27:12.89#ibcon#read 5, iclass 14, count 0 2006.257.15:27:12.89#ibcon#about to read 6, iclass 14, count 0 2006.257.15:27:12.89#ibcon#read 6, iclass 14, count 0 2006.257.15:27:12.89#ibcon#end of sib2, iclass 14, count 0 2006.257.15:27:12.89#ibcon#*after write, iclass 14, count 0 2006.257.15:27:12.89#ibcon#*before return 0, iclass 14, count 0 2006.257.15:27:12.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:12.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:12.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:27:12.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:27:12.89$vck44/va=8,4 2006.257.15:27:12.89#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.15:27:12.89#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.15:27:12.89#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:12.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:27:12.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:27:12.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:27:12.95#ibcon#enter wrdev, iclass 16, count 2 2006.257.15:27:12.95#ibcon#first serial, iclass 16, count 2 2006.257.15:27:12.95#ibcon#enter sib2, iclass 16, count 2 2006.257.15:27:12.95#ibcon#flushed, iclass 16, count 2 2006.257.15:27:12.95#ibcon#about to write, iclass 16, count 2 2006.257.15:27:12.95#ibcon#wrote, iclass 16, count 2 2006.257.15:27:12.95#ibcon#about to read 3, iclass 16, count 2 2006.257.15:27:12.97#ibcon#read 3, iclass 16, count 2 2006.257.15:27:12.97#ibcon#about to read 4, iclass 16, count 2 2006.257.15:27:12.97#ibcon#read 4, iclass 16, count 2 2006.257.15:27:12.97#ibcon#about to read 5, iclass 16, count 2 2006.257.15:27:12.97#ibcon#read 5, iclass 16, count 2 2006.257.15:27:12.97#ibcon#about to read 6, iclass 16, count 2 2006.257.15:27:12.97#ibcon#read 6, iclass 16, count 2 2006.257.15:27:12.97#ibcon#end of sib2, iclass 16, count 2 2006.257.15:27:12.97#ibcon#*mode == 0, iclass 16, count 2 2006.257.15:27:12.97#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.15:27:12.97#ibcon#[25=AT08-04\r\n] 2006.257.15:27:12.97#ibcon#*before write, iclass 16, count 2 2006.257.15:27:12.97#ibcon#enter sib2, iclass 16, count 2 2006.257.15:27:12.97#ibcon#flushed, iclass 16, count 2 2006.257.15:27:12.97#ibcon#about to write, iclass 16, count 2 2006.257.15:27:12.97#ibcon#wrote, iclass 16, count 2 2006.257.15:27:12.97#ibcon#about to read 3, iclass 16, count 2 2006.257.15:27:13.00#ibcon#read 3, iclass 16, count 2 2006.257.15:27:13.00#ibcon#about to read 4, iclass 16, count 2 2006.257.15:27:13.00#ibcon#read 4, iclass 16, count 2 2006.257.15:27:13.00#ibcon#about to read 5, iclass 16, count 2 2006.257.15:27:13.00#ibcon#read 5, iclass 16, count 2 2006.257.15:27:13.00#ibcon#about to read 6, iclass 16, count 2 2006.257.15:27:13.00#ibcon#read 6, iclass 16, count 2 2006.257.15:27:13.00#ibcon#end of sib2, iclass 16, count 2 2006.257.15:27:13.00#ibcon#*after write, iclass 16, count 2 2006.257.15:27:13.00#ibcon#*before return 0, iclass 16, count 2 2006.257.15:27:13.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:27:13.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:27:13.00#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.15:27:13.00#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:13.00#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:27:13.12#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:27:13.12#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:27:13.12#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:27:13.12#ibcon#first serial, iclass 16, count 0 2006.257.15:27:13.12#ibcon#enter sib2, iclass 16, count 0 2006.257.15:27:13.12#ibcon#flushed, iclass 16, count 0 2006.257.15:27:13.12#ibcon#about to write, iclass 16, count 0 2006.257.15:27:13.12#ibcon#wrote, iclass 16, count 0 2006.257.15:27:13.12#ibcon#about to read 3, iclass 16, count 0 2006.257.15:27:13.14#ibcon#read 3, iclass 16, count 0 2006.257.15:27:13.14#ibcon#about to read 4, iclass 16, count 0 2006.257.15:27:13.14#ibcon#read 4, iclass 16, count 0 2006.257.15:27:13.14#ibcon#about to read 5, iclass 16, count 0 2006.257.15:27:13.14#ibcon#read 5, iclass 16, count 0 2006.257.15:27:13.14#ibcon#about to read 6, iclass 16, count 0 2006.257.15:27:13.14#ibcon#read 6, iclass 16, count 0 2006.257.15:27:13.14#ibcon#end of sib2, iclass 16, count 0 2006.257.15:27:13.14#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:27:13.14#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:27:13.14#ibcon#[25=USB\r\n] 2006.257.15:27:13.14#ibcon#*before write, iclass 16, count 0 2006.257.15:27:13.14#ibcon#enter sib2, iclass 16, count 0 2006.257.15:27:13.14#ibcon#flushed, iclass 16, count 0 2006.257.15:27:13.14#ibcon#about to write, iclass 16, count 0 2006.257.15:27:13.14#ibcon#wrote, iclass 16, count 0 2006.257.15:27:13.14#ibcon#about to read 3, iclass 16, count 0 2006.257.15:27:13.17#ibcon#read 3, iclass 16, count 0 2006.257.15:27:13.17#ibcon#about to read 4, iclass 16, count 0 2006.257.15:27:13.17#ibcon#read 4, iclass 16, count 0 2006.257.15:27:13.17#ibcon#about to read 5, iclass 16, count 0 2006.257.15:27:13.17#ibcon#read 5, iclass 16, count 0 2006.257.15:27:13.17#ibcon#about to read 6, iclass 16, count 0 2006.257.15:27:13.17#ibcon#read 6, iclass 16, count 0 2006.257.15:27:13.17#ibcon#end of sib2, iclass 16, count 0 2006.257.15:27:13.17#ibcon#*after write, iclass 16, count 0 2006.257.15:27:13.17#ibcon#*before return 0, iclass 16, count 0 2006.257.15:27:13.17#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:27:13.17#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:27:13.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:27:13.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:27:13.17$vck44/vblo=1,629.99 2006.257.15:27:13.17#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.15:27:13.17#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.15:27:13.17#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:13.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:13.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:13.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:13.17#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:27:13.17#ibcon#first serial, iclass 18, count 0 2006.257.15:27:13.17#ibcon#enter sib2, iclass 18, count 0 2006.257.15:27:13.17#ibcon#flushed, iclass 18, count 0 2006.257.15:27:13.17#ibcon#about to write, iclass 18, count 0 2006.257.15:27:13.17#ibcon#wrote, iclass 18, count 0 2006.257.15:27:13.17#ibcon#about to read 3, iclass 18, count 0 2006.257.15:27:13.19#ibcon#read 3, iclass 18, count 0 2006.257.15:27:13.19#ibcon#about to read 4, iclass 18, count 0 2006.257.15:27:13.19#ibcon#read 4, iclass 18, count 0 2006.257.15:27:13.19#ibcon#about to read 5, iclass 18, count 0 2006.257.15:27:13.19#ibcon#read 5, iclass 18, count 0 2006.257.15:27:13.19#ibcon#about to read 6, iclass 18, count 0 2006.257.15:27:13.19#ibcon#read 6, iclass 18, count 0 2006.257.15:27:13.19#ibcon#end of sib2, iclass 18, count 0 2006.257.15:27:13.19#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:27:13.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:27:13.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:27:13.19#ibcon#*before write, iclass 18, count 0 2006.257.15:27:13.19#ibcon#enter sib2, iclass 18, count 0 2006.257.15:27:13.19#ibcon#flushed, iclass 18, count 0 2006.257.15:27:13.19#ibcon#about to write, iclass 18, count 0 2006.257.15:27:13.19#ibcon#wrote, iclass 18, count 0 2006.257.15:27:13.19#ibcon#about to read 3, iclass 18, count 0 2006.257.15:27:13.23#ibcon#read 3, iclass 18, count 0 2006.257.15:27:13.23#ibcon#about to read 4, iclass 18, count 0 2006.257.15:27:13.23#ibcon#read 4, iclass 18, count 0 2006.257.15:27:13.23#ibcon#about to read 5, iclass 18, count 0 2006.257.15:27:13.23#ibcon#read 5, iclass 18, count 0 2006.257.15:27:13.23#ibcon#about to read 6, iclass 18, count 0 2006.257.15:27:13.23#ibcon#read 6, iclass 18, count 0 2006.257.15:27:13.23#ibcon#end of sib2, iclass 18, count 0 2006.257.15:27:13.23#ibcon#*after write, iclass 18, count 0 2006.257.15:27:13.23#ibcon#*before return 0, iclass 18, count 0 2006.257.15:27:13.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:13.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:27:13.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:27:13.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:27:13.23$vck44/vb=1,4 2006.257.15:27:13.23#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.15:27:13.23#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.15:27:13.23#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:13.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:13.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:13.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:13.23#ibcon#enter wrdev, iclass 20, count 2 2006.257.15:27:13.23#ibcon#first serial, iclass 20, count 2 2006.257.15:27:13.23#ibcon#enter sib2, iclass 20, count 2 2006.257.15:27:13.23#ibcon#flushed, iclass 20, count 2 2006.257.15:27:13.23#ibcon#about to write, iclass 20, count 2 2006.257.15:27:13.23#ibcon#wrote, iclass 20, count 2 2006.257.15:27:13.23#ibcon#about to read 3, iclass 20, count 2 2006.257.15:27:13.25#ibcon#read 3, iclass 20, count 2 2006.257.15:27:13.25#ibcon#about to read 4, iclass 20, count 2 2006.257.15:27:13.25#ibcon#read 4, iclass 20, count 2 2006.257.15:27:13.25#ibcon#about to read 5, iclass 20, count 2 2006.257.15:27:13.25#ibcon#read 5, iclass 20, count 2 2006.257.15:27:13.25#ibcon#about to read 6, iclass 20, count 2 2006.257.15:27:13.25#ibcon#read 6, iclass 20, count 2 2006.257.15:27:13.25#ibcon#end of sib2, iclass 20, count 2 2006.257.15:27:13.25#ibcon#*mode == 0, iclass 20, count 2 2006.257.15:27:13.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.15:27:13.25#ibcon#[27=AT01-04\r\n] 2006.257.15:27:13.25#ibcon#*before write, iclass 20, count 2 2006.257.15:27:13.25#ibcon#enter sib2, iclass 20, count 2 2006.257.15:27:13.25#ibcon#flushed, iclass 20, count 2 2006.257.15:27:13.25#ibcon#about to write, iclass 20, count 2 2006.257.15:27:13.25#ibcon#wrote, iclass 20, count 2 2006.257.15:27:13.25#ibcon#about to read 3, iclass 20, count 2 2006.257.15:27:13.28#ibcon#read 3, iclass 20, count 2 2006.257.15:27:13.28#ibcon#about to read 4, iclass 20, count 2 2006.257.15:27:13.28#ibcon#read 4, iclass 20, count 2 2006.257.15:27:13.28#ibcon#about to read 5, iclass 20, count 2 2006.257.15:27:13.28#ibcon#read 5, iclass 20, count 2 2006.257.15:27:13.28#ibcon#about to read 6, iclass 20, count 2 2006.257.15:27:13.28#ibcon#read 6, iclass 20, count 2 2006.257.15:27:13.28#ibcon#end of sib2, iclass 20, count 2 2006.257.15:27:13.28#ibcon#*after write, iclass 20, count 2 2006.257.15:27:13.28#ibcon#*before return 0, iclass 20, count 2 2006.257.15:27:13.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:13.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:27:13.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.15:27:13.28#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:13.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:13.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:13.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:13.40#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:27:13.40#ibcon#first serial, iclass 20, count 0 2006.257.15:27:13.40#ibcon#enter sib2, iclass 20, count 0 2006.257.15:27:13.40#ibcon#flushed, iclass 20, count 0 2006.257.15:27:13.40#ibcon#about to write, iclass 20, count 0 2006.257.15:27:13.40#ibcon#wrote, iclass 20, count 0 2006.257.15:27:13.40#ibcon#about to read 3, iclass 20, count 0 2006.257.15:27:13.42#ibcon#read 3, iclass 20, count 0 2006.257.15:27:13.42#ibcon#about to read 4, iclass 20, count 0 2006.257.15:27:13.42#ibcon#read 4, iclass 20, count 0 2006.257.15:27:13.42#ibcon#about to read 5, iclass 20, count 0 2006.257.15:27:13.42#ibcon#read 5, iclass 20, count 0 2006.257.15:27:13.42#ibcon#about to read 6, iclass 20, count 0 2006.257.15:27:13.42#ibcon#read 6, iclass 20, count 0 2006.257.15:27:13.42#ibcon#end of sib2, iclass 20, count 0 2006.257.15:27:13.42#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:27:13.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:27:13.42#ibcon#[27=USB\r\n] 2006.257.15:27:13.42#ibcon#*before write, iclass 20, count 0 2006.257.15:27:13.42#ibcon#enter sib2, iclass 20, count 0 2006.257.15:27:13.42#ibcon#flushed, iclass 20, count 0 2006.257.15:27:13.42#ibcon#about to write, iclass 20, count 0 2006.257.15:27:13.42#ibcon#wrote, iclass 20, count 0 2006.257.15:27:13.42#ibcon#about to read 3, iclass 20, count 0 2006.257.15:27:13.45#ibcon#read 3, iclass 20, count 0 2006.257.15:27:13.45#ibcon#about to read 4, iclass 20, count 0 2006.257.15:27:13.45#ibcon#read 4, iclass 20, count 0 2006.257.15:27:13.45#ibcon#about to read 5, iclass 20, count 0 2006.257.15:27:13.45#ibcon#read 5, iclass 20, count 0 2006.257.15:27:13.45#ibcon#about to read 6, iclass 20, count 0 2006.257.15:27:13.45#ibcon#read 6, iclass 20, count 0 2006.257.15:27:13.45#ibcon#end of sib2, iclass 20, count 0 2006.257.15:27:13.45#ibcon#*after write, iclass 20, count 0 2006.257.15:27:13.45#ibcon#*before return 0, iclass 20, count 0 2006.257.15:27:13.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:13.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:27:13.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:27:13.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:27:13.45$vck44/vblo=2,634.99 2006.257.15:27:13.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.15:27:13.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.15:27:13.45#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:13.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:27:13.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:27:13.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:27:13.45#ibcon#enter wrdev, iclass 22, count 0 2006.257.15:27:13.45#ibcon#first serial, iclass 22, count 0 2006.257.15:27:13.45#ibcon#enter sib2, iclass 22, count 0 2006.257.15:27:13.45#ibcon#flushed, iclass 22, count 0 2006.257.15:27:13.45#ibcon#about to write, iclass 22, count 0 2006.257.15:27:13.45#ibcon#wrote, iclass 22, count 0 2006.257.15:27:13.45#ibcon#about to read 3, iclass 22, count 0 2006.257.15:27:13.47#ibcon#read 3, iclass 22, count 0 2006.257.15:27:13.47#ibcon#about to read 4, iclass 22, count 0 2006.257.15:27:13.47#ibcon#read 4, iclass 22, count 0 2006.257.15:27:13.47#ibcon#about to read 5, iclass 22, count 0 2006.257.15:27:13.47#ibcon#read 5, iclass 22, count 0 2006.257.15:27:13.47#ibcon#about to read 6, iclass 22, count 0 2006.257.15:27:13.47#ibcon#read 6, iclass 22, count 0 2006.257.15:27:13.47#ibcon#end of sib2, iclass 22, count 0 2006.257.15:27:13.47#ibcon#*mode == 0, iclass 22, count 0 2006.257.15:27:13.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.15:27:13.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:27:13.47#ibcon#*before write, iclass 22, count 0 2006.257.15:27:13.47#ibcon#enter sib2, iclass 22, count 0 2006.257.15:27:13.47#ibcon#flushed, iclass 22, count 0 2006.257.15:27:13.47#ibcon#about to write, iclass 22, count 0 2006.257.15:27:13.47#ibcon#wrote, iclass 22, count 0 2006.257.15:27:13.47#ibcon#about to read 3, iclass 22, count 0 2006.257.15:27:13.51#ibcon#read 3, iclass 22, count 0 2006.257.15:27:13.51#ibcon#about to read 4, iclass 22, count 0 2006.257.15:27:13.51#ibcon#read 4, iclass 22, count 0 2006.257.15:27:13.51#ibcon#about to read 5, iclass 22, count 0 2006.257.15:27:13.51#ibcon#read 5, iclass 22, count 0 2006.257.15:27:13.51#ibcon#about to read 6, iclass 22, count 0 2006.257.15:27:13.51#ibcon#read 6, iclass 22, count 0 2006.257.15:27:13.51#ibcon#end of sib2, iclass 22, count 0 2006.257.15:27:13.51#ibcon#*after write, iclass 22, count 0 2006.257.15:27:13.51#ibcon#*before return 0, iclass 22, count 0 2006.257.15:27:13.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:27:13.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:27:13.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.15:27:13.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.15:27:13.51$vck44/vb=2,5 2006.257.15:27:13.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.15:27:13.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.15:27:13.51#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:13.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:27:13.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:27:13.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:27:13.57#ibcon#enter wrdev, iclass 24, count 2 2006.257.15:27:13.57#ibcon#first serial, iclass 24, count 2 2006.257.15:27:13.57#ibcon#enter sib2, iclass 24, count 2 2006.257.15:27:13.57#ibcon#flushed, iclass 24, count 2 2006.257.15:27:13.57#ibcon#about to write, iclass 24, count 2 2006.257.15:27:13.57#ibcon#wrote, iclass 24, count 2 2006.257.15:27:13.57#ibcon#about to read 3, iclass 24, count 2 2006.257.15:27:13.59#ibcon#read 3, iclass 24, count 2 2006.257.15:27:13.59#ibcon#about to read 4, iclass 24, count 2 2006.257.15:27:13.59#ibcon#read 4, iclass 24, count 2 2006.257.15:27:13.59#ibcon#about to read 5, iclass 24, count 2 2006.257.15:27:13.59#ibcon#read 5, iclass 24, count 2 2006.257.15:27:13.59#ibcon#about to read 6, iclass 24, count 2 2006.257.15:27:13.59#ibcon#read 6, iclass 24, count 2 2006.257.15:27:13.59#ibcon#end of sib2, iclass 24, count 2 2006.257.15:27:13.59#ibcon#*mode == 0, iclass 24, count 2 2006.257.15:27:13.59#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.15:27:13.59#ibcon#[27=AT02-05\r\n] 2006.257.15:27:13.59#ibcon#*before write, iclass 24, count 2 2006.257.15:27:13.59#ibcon#enter sib2, iclass 24, count 2 2006.257.15:27:13.59#ibcon#flushed, iclass 24, count 2 2006.257.15:27:13.59#ibcon#about to write, iclass 24, count 2 2006.257.15:27:13.59#ibcon#wrote, iclass 24, count 2 2006.257.15:27:13.59#ibcon#about to read 3, iclass 24, count 2 2006.257.15:27:13.62#ibcon#read 3, iclass 24, count 2 2006.257.15:27:13.62#ibcon#about to read 4, iclass 24, count 2 2006.257.15:27:13.62#ibcon#read 4, iclass 24, count 2 2006.257.15:27:13.62#ibcon#about to read 5, iclass 24, count 2 2006.257.15:27:13.62#ibcon#read 5, iclass 24, count 2 2006.257.15:27:13.62#ibcon#about to read 6, iclass 24, count 2 2006.257.15:27:13.62#ibcon#read 6, iclass 24, count 2 2006.257.15:27:13.62#ibcon#end of sib2, iclass 24, count 2 2006.257.15:27:13.62#ibcon#*after write, iclass 24, count 2 2006.257.15:27:13.62#ibcon#*before return 0, iclass 24, count 2 2006.257.15:27:13.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:27:13.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:27:13.62#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.15:27:13.62#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:13.62#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:27:13.74#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:27:13.74#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:27:13.74#ibcon#enter wrdev, iclass 24, count 0 2006.257.15:27:13.74#ibcon#first serial, iclass 24, count 0 2006.257.15:27:13.74#ibcon#enter sib2, iclass 24, count 0 2006.257.15:27:13.74#ibcon#flushed, iclass 24, count 0 2006.257.15:27:13.74#ibcon#about to write, iclass 24, count 0 2006.257.15:27:13.74#ibcon#wrote, iclass 24, count 0 2006.257.15:27:13.74#ibcon#about to read 3, iclass 24, count 0 2006.257.15:27:13.76#ibcon#read 3, iclass 24, count 0 2006.257.15:27:13.76#ibcon#about to read 4, iclass 24, count 0 2006.257.15:27:13.76#ibcon#read 4, iclass 24, count 0 2006.257.15:27:13.76#ibcon#about to read 5, iclass 24, count 0 2006.257.15:27:13.76#ibcon#read 5, iclass 24, count 0 2006.257.15:27:13.76#ibcon#about to read 6, iclass 24, count 0 2006.257.15:27:13.76#ibcon#read 6, iclass 24, count 0 2006.257.15:27:13.76#ibcon#end of sib2, iclass 24, count 0 2006.257.15:27:13.76#ibcon#*mode == 0, iclass 24, count 0 2006.257.15:27:13.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.15:27:13.76#ibcon#[27=USB\r\n] 2006.257.15:27:13.76#ibcon#*before write, iclass 24, count 0 2006.257.15:27:13.76#ibcon#enter sib2, iclass 24, count 0 2006.257.15:27:13.76#ibcon#flushed, iclass 24, count 0 2006.257.15:27:13.76#ibcon#about to write, iclass 24, count 0 2006.257.15:27:13.77#ibcon#wrote, iclass 24, count 0 2006.257.15:27:13.77#ibcon#about to read 3, iclass 24, count 0 2006.257.15:27:13.80#ibcon#read 3, iclass 24, count 0 2006.257.15:27:13.80#ibcon#about to read 4, iclass 24, count 0 2006.257.15:27:13.80#ibcon#read 4, iclass 24, count 0 2006.257.15:27:13.80#ibcon#about to read 5, iclass 24, count 0 2006.257.15:27:13.80#ibcon#read 5, iclass 24, count 0 2006.257.15:27:13.80#ibcon#about to read 6, iclass 24, count 0 2006.257.15:27:13.80#ibcon#read 6, iclass 24, count 0 2006.257.15:27:13.80#ibcon#end of sib2, iclass 24, count 0 2006.257.15:27:13.80#ibcon#*after write, iclass 24, count 0 2006.257.15:27:13.80#ibcon#*before return 0, iclass 24, count 0 2006.257.15:27:13.80#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:27:13.80#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:27:13.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.15:27:13.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.15:27:13.80$vck44/vblo=3,649.99 2006.257.15:27:13.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.15:27:13.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.15:27:13.80#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:13.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:13.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:13.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:13.80#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:27:13.80#ibcon#first serial, iclass 26, count 0 2006.257.15:27:13.80#ibcon#enter sib2, iclass 26, count 0 2006.257.15:27:13.80#ibcon#flushed, iclass 26, count 0 2006.257.15:27:13.80#ibcon#about to write, iclass 26, count 0 2006.257.15:27:13.80#ibcon#wrote, iclass 26, count 0 2006.257.15:27:13.80#ibcon#about to read 3, iclass 26, count 0 2006.257.15:27:13.82#ibcon#read 3, iclass 26, count 0 2006.257.15:27:13.82#ibcon#about to read 4, iclass 26, count 0 2006.257.15:27:13.82#ibcon#read 4, iclass 26, count 0 2006.257.15:27:13.82#ibcon#about to read 5, iclass 26, count 0 2006.257.15:27:13.82#ibcon#read 5, iclass 26, count 0 2006.257.15:27:13.82#ibcon#about to read 6, iclass 26, count 0 2006.257.15:27:13.82#ibcon#read 6, iclass 26, count 0 2006.257.15:27:13.82#ibcon#end of sib2, iclass 26, count 0 2006.257.15:27:13.82#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:27:13.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:27:13.82#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:27:13.82#ibcon#*before write, iclass 26, count 0 2006.257.15:27:13.82#ibcon#enter sib2, iclass 26, count 0 2006.257.15:27:13.82#ibcon#flushed, iclass 26, count 0 2006.257.15:27:13.82#ibcon#about to write, iclass 26, count 0 2006.257.15:27:13.82#ibcon#wrote, iclass 26, count 0 2006.257.15:27:13.82#ibcon#about to read 3, iclass 26, count 0 2006.257.15:27:13.86#ibcon#read 3, iclass 26, count 0 2006.257.15:27:13.86#ibcon#about to read 4, iclass 26, count 0 2006.257.15:27:13.86#ibcon#read 4, iclass 26, count 0 2006.257.15:27:13.86#ibcon#about to read 5, iclass 26, count 0 2006.257.15:27:13.86#ibcon#read 5, iclass 26, count 0 2006.257.15:27:13.86#ibcon#about to read 6, iclass 26, count 0 2006.257.15:27:13.86#ibcon#read 6, iclass 26, count 0 2006.257.15:27:13.86#ibcon#end of sib2, iclass 26, count 0 2006.257.15:27:13.86#ibcon#*after write, iclass 26, count 0 2006.257.15:27:13.86#ibcon#*before return 0, iclass 26, count 0 2006.257.15:27:13.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:13.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:27:13.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:27:13.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:27:13.86$vck44/vb=3,4 2006.257.15:27:13.86#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.15:27:13.86#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.15:27:13.86#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:13.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:13.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:13.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:13.92#ibcon#enter wrdev, iclass 28, count 2 2006.257.15:27:13.92#ibcon#first serial, iclass 28, count 2 2006.257.15:27:13.92#ibcon#enter sib2, iclass 28, count 2 2006.257.15:27:13.92#ibcon#flushed, iclass 28, count 2 2006.257.15:27:13.92#ibcon#about to write, iclass 28, count 2 2006.257.15:27:13.92#ibcon#wrote, iclass 28, count 2 2006.257.15:27:13.92#ibcon#about to read 3, iclass 28, count 2 2006.257.15:27:13.94#ibcon#read 3, iclass 28, count 2 2006.257.15:27:13.94#ibcon#about to read 4, iclass 28, count 2 2006.257.15:27:13.94#ibcon#read 4, iclass 28, count 2 2006.257.15:27:13.94#ibcon#about to read 5, iclass 28, count 2 2006.257.15:27:13.94#ibcon#read 5, iclass 28, count 2 2006.257.15:27:13.94#ibcon#about to read 6, iclass 28, count 2 2006.257.15:27:13.94#ibcon#read 6, iclass 28, count 2 2006.257.15:27:13.94#ibcon#end of sib2, iclass 28, count 2 2006.257.15:27:13.94#ibcon#*mode == 0, iclass 28, count 2 2006.257.15:27:13.94#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.15:27:13.94#ibcon#[27=AT03-04\r\n] 2006.257.15:27:13.94#ibcon#*before write, iclass 28, count 2 2006.257.15:27:13.94#ibcon#enter sib2, iclass 28, count 2 2006.257.15:27:13.94#ibcon#flushed, iclass 28, count 2 2006.257.15:27:13.94#ibcon#about to write, iclass 28, count 2 2006.257.15:27:13.94#ibcon#wrote, iclass 28, count 2 2006.257.15:27:13.94#ibcon#about to read 3, iclass 28, count 2 2006.257.15:27:13.97#ibcon#read 3, iclass 28, count 2 2006.257.15:27:13.97#ibcon#about to read 4, iclass 28, count 2 2006.257.15:27:13.97#ibcon#read 4, iclass 28, count 2 2006.257.15:27:13.97#ibcon#about to read 5, iclass 28, count 2 2006.257.15:27:13.97#ibcon#read 5, iclass 28, count 2 2006.257.15:27:13.97#ibcon#about to read 6, iclass 28, count 2 2006.257.15:27:13.97#ibcon#read 6, iclass 28, count 2 2006.257.15:27:13.97#ibcon#end of sib2, iclass 28, count 2 2006.257.15:27:13.97#ibcon#*after write, iclass 28, count 2 2006.257.15:27:13.97#ibcon#*before return 0, iclass 28, count 2 2006.257.15:27:13.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:13.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:27:13.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.15:27:13.97#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:13.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:14.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:14.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:14.09#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:27:14.09#ibcon#first serial, iclass 28, count 0 2006.257.15:27:14.09#ibcon#enter sib2, iclass 28, count 0 2006.257.15:27:14.09#ibcon#flushed, iclass 28, count 0 2006.257.15:27:14.09#ibcon#about to write, iclass 28, count 0 2006.257.15:27:14.09#ibcon#wrote, iclass 28, count 0 2006.257.15:27:14.09#ibcon#about to read 3, iclass 28, count 0 2006.257.15:27:14.11#ibcon#read 3, iclass 28, count 0 2006.257.15:27:14.11#ibcon#about to read 4, iclass 28, count 0 2006.257.15:27:14.11#ibcon#read 4, iclass 28, count 0 2006.257.15:27:14.11#ibcon#about to read 5, iclass 28, count 0 2006.257.15:27:14.11#ibcon#read 5, iclass 28, count 0 2006.257.15:27:14.11#ibcon#about to read 6, iclass 28, count 0 2006.257.15:27:14.11#ibcon#read 6, iclass 28, count 0 2006.257.15:27:14.11#ibcon#end of sib2, iclass 28, count 0 2006.257.15:27:14.11#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:27:14.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:27:14.11#ibcon#[27=USB\r\n] 2006.257.15:27:14.11#ibcon#*before write, iclass 28, count 0 2006.257.15:27:14.11#ibcon#enter sib2, iclass 28, count 0 2006.257.15:27:14.11#ibcon#flushed, iclass 28, count 0 2006.257.15:27:14.11#ibcon#about to write, iclass 28, count 0 2006.257.15:27:14.11#ibcon#wrote, iclass 28, count 0 2006.257.15:27:14.11#ibcon#about to read 3, iclass 28, count 0 2006.257.15:27:14.14#ibcon#read 3, iclass 28, count 0 2006.257.15:27:14.14#ibcon#about to read 4, iclass 28, count 0 2006.257.15:27:14.14#ibcon#read 4, iclass 28, count 0 2006.257.15:27:14.14#ibcon#about to read 5, iclass 28, count 0 2006.257.15:27:14.14#ibcon#read 5, iclass 28, count 0 2006.257.15:27:14.14#ibcon#about to read 6, iclass 28, count 0 2006.257.15:27:14.14#ibcon#read 6, iclass 28, count 0 2006.257.15:27:14.14#ibcon#end of sib2, iclass 28, count 0 2006.257.15:27:14.14#ibcon#*after write, iclass 28, count 0 2006.257.15:27:14.14#ibcon#*before return 0, iclass 28, count 0 2006.257.15:27:14.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:14.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:27:14.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:27:14.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:27:14.14$vck44/vblo=4,679.99 2006.257.15:27:14.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.15:27:14.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.15:27:14.14#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:14.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:14.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:14.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:14.14#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:27:14.14#ibcon#first serial, iclass 30, count 0 2006.257.15:27:14.14#ibcon#enter sib2, iclass 30, count 0 2006.257.15:27:14.14#ibcon#flushed, iclass 30, count 0 2006.257.15:27:14.14#ibcon#about to write, iclass 30, count 0 2006.257.15:27:14.14#ibcon#wrote, iclass 30, count 0 2006.257.15:27:14.14#ibcon#about to read 3, iclass 30, count 0 2006.257.15:27:14.16#ibcon#read 3, iclass 30, count 0 2006.257.15:27:14.16#ibcon#about to read 4, iclass 30, count 0 2006.257.15:27:14.16#ibcon#read 4, iclass 30, count 0 2006.257.15:27:14.16#ibcon#about to read 5, iclass 30, count 0 2006.257.15:27:14.16#ibcon#read 5, iclass 30, count 0 2006.257.15:27:14.16#ibcon#about to read 6, iclass 30, count 0 2006.257.15:27:14.16#ibcon#read 6, iclass 30, count 0 2006.257.15:27:14.16#ibcon#end of sib2, iclass 30, count 0 2006.257.15:27:14.16#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:27:14.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:27:14.16#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:27:14.16#ibcon#*before write, iclass 30, count 0 2006.257.15:27:14.16#ibcon#enter sib2, iclass 30, count 0 2006.257.15:27:14.16#ibcon#flushed, iclass 30, count 0 2006.257.15:27:14.16#ibcon#about to write, iclass 30, count 0 2006.257.15:27:14.16#ibcon#wrote, iclass 30, count 0 2006.257.15:27:14.16#ibcon#about to read 3, iclass 30, count 0 2006.257.15:27:14.20#ibcon#read 3, iclass 30, count 0 2006.257.15:27:14.20#ibcon#about to read 4, iclass 30, count 0 2006.257.15:27:14.20#ibcon#read 4, iclass 30, count 0 2006.257.15:27:14.20#ibcon#about to read 5, iclass 30, count 0 2006.257.15:27:14.20#ibcon#read 5, iclass 30, count 0 2006.257.15:27:14.20#ibcon#about to read 6, iclass 30, count 0 2006.257.15:27:14.20#ibcon#read 6, iclass 30, count 0 2006.257.15:27:14.20#ibcon#end of sib2, iclass 30, count 0 2006.257.15:27:14.20#ibcon#*after write, iclass 30, count 0 2006.257.15:27:14.20#ibcon#*before return 0, iclass 30, count 0 2006.257.15:27:14.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:14.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:27:14.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:27:14.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:27:14.20$vck44/vb=4,5 2006.257.15:27:14.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.15:27:14.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.15:27:14.20#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:14.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:14.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:14.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:14.26#ibcon#enter wrdev, iclass 32, count 2 2006.257.15:27:14.26#ibcon#first serial, iclass 32, count 2 2006.257.15:27:14.26#ibcon#enter sib2, iclass 32, count 2 2006.257.15:27:14.26#ibcon#flushed, iclass 32, count 2 2006.257.15:27:14.26#ibcon#about to write, iclass 32, count 2 2006.257.15:27:14.26#ibcon#wrote, iclass 32, count 2 2006.257.15:27:14.26#ibcon#about to read 3, iclass 32, count 2 2006.257.15:27:14.28#ibcon#read 3, iclass 32, count 2 2006.257.15:27:14.28#ibcon#about to read 4, iclass 32, count 2 2006.257.15:27:14.28#ibcon#read 4, iclass 32, count 2 2006.257.15:27:14.28#ibcon#about to read 5, iclass 32, count 2 2006.257.15:27:14.28#ibcon#read 5, iclass 32, count 2 2006.257.15:27:14.28#ibcon#about to read 6, iclass 32, count 2 2006.257.15:27:14.28#ibcon#read 6, iclass 32, count 2 2006.257.15:27:14.28#ibcon#end of sib2, iclass 32, count 2 2006.257.15:27:14.28#ibcon#*mode == 0, iclass 32, count 2 2006.257.15:27:14.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.15:27:14.28#ibcon#[27=AT04-05\r\n] 2006.257.15:27:14.28#ibcon#*before write, iclass 32, count 2 2006.257.15:27:14.28#ibcon#enter sib2, iclass 32, count 2 2006.257.15:27:14.28#ibcon#flushed, iclass 32, count 2 2006.257.15:27:14.28#ibcon#about to write, iclass 32, count 2 2006.257.15:27:14.28#ibcon#wrote, iclass 32, count 2 2006.257.15:27:14.28#ibcon#about to read 3, iclass 32, count 2 2006.257.15:27:14.31#ibcon#read 3, iclass 32, count 2 2006.257.15:27:14.31#ibcon#about to read 4, iclass 32, count 2 2006.257.15:27:14.31#ibcon#read 4, iclass 32, count 2 2006.257.15:27:14.31#ibcon#about to read 5, iclass 32, count 2 2006.257.15:27:14.31#ibcon#read 5, iclass 32, count 2 2006.257.15:27:14.31#ibcon#about to read 6, iclass 32, count 2 2006.257.15:27:14.31#ibcon#read 6, iclass 32, count 2 2006.257.15:27:14.31#ibcon#end of sib2, iclass 32, count 2 2006.257.15:27:14.31#ibcon#*after write, iclass 32, count 2 2006.257.15:27:14.31#ibcon#*before return 0, iclass 32, count 2 2006.257.15:27:14.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:14.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:27:14.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.15:27:14.31#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:14.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:14.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:14.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:14.43#ibcon#enter wrdev, iclass 32, count 0 2006.257.15:27:14.43#ibcon#first serial, iclass 32, count 0 2006.257.15:27:14.43#ibcon#enter sib2, iclass 32, count 0 2006.257.15:27:14.43#ibcon#flushed, iclass 32, count 0 2006.257.15:27:14.43#ibcon#about to write, iclass 32, count 0 2006.257.15:27:14.43#ibcon#wrote, iclass 32, count 0 2006.257.15:27:14.43#ibcon#about to read 3, iclass 32, count 0 2006.257.15:27:14.45#ibcon#read 3, iclass 32, count 0 2006.257.15:27:14.45#ibcon#about to read 4, iclass 32, count 0 2006.257.15:27:14.45#ibcon#read 4, iclass 32, count 0 2006.257.15:27:14.45#ibcon#about to read 5, iclass 32, count 0 2006.257.15:27:14.45#ibcon#read 5, iclass 32, count 0 2006.257.15:27:14.45#ibcon#about to read 6, iclass 32, count 0 2006.257.15:27:14.45#ibcon#read 6, iclass 32, count 0 2006.257.15:27:14.45#ibcon#end of sib2, iclass 32, count 0 2006.257.15:27:14.45#ibcon#*mode == 0, iclass 32, count 0 2006.257.15:27:14.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.15:27:14.45#ibcon#[27=USB\r\n] 2006.257.15:27:14.45#ibcon#*before write, iclass 32, count 0 2006.257.15:27:14.45#ibcon#enter sib2, iclass 32, count 0 2006.257.15:27:14.45#ibcon#flushed, iclass 32, count 0 2006.257.15:27:14.45#ibcon#about to write, iclass 32, count 0 2006.257.15:27:14.45#ibcon#wrote, iclass 32, count 0 2006.257.15:27:14.45#ibcon#about to read 3, iclass 32, count 0 2006.257.15:27:14.48#ibcon#read 3, iclass 32, count 0 2006.257.15:27:14.48#ibcon#about to read 4, iclass 32, count 0 2006.257.15:27:14.48#ibcon#read 4, iclass 32, count 0 2006.257.15:27:14.48#ibcon#about to read 5, iclass 32, count 0 2006.257.15:27:14.48#ibcon#read 5, iclass 32, count 0 2006.257.15:27:14.48#ibcon#about to read 6, iclass 32, count 0 2006.257.15:27:14.48#ibcon#read 6, iclass 32, count 0 2006.257.15:27:14.48#ibcon#end of sib2, iclass 32, count 0 2006.257.15:27:14.48#ibcon#*after write, iclass 32, count 0 2006.257.15:27:14.48#ibcon#*before return 0, iclass 32, count 0 2006.257.15:27:14.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:14.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:27:14.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.15:27:14.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.15:27:14.48$vck44/vblo=5,709.99 2006.257.15:27:14.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.15:27:14.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.15:27:14.48#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:14.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:14.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:14.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:14.48#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:27:14.48#ibcon#first serial, iclass 34, count 0 2006.257.15:27:14.48#ibcon#enter sib2, iclass 34, count 0 2006.257.15:27:14.48#ibcon#flushed, iclass 34, count 0 2006.257.15:27:14.48#ibcon#about to write, iclass 34, count 0 2006.257.15:27:14.48#ibcon#wrote, iclass 34, count 0 2006.257.15:27:14.48#ibcon#about to read 3, iclass 34, count 0 2006.257.15:27:14.50#ibcon#read 3, iclass 34, count 0 2006.257.15:27:14.50#ibcon#about to read 4, iclass 34, count 0 2006.257.15:27:14.50#ibcon#read 4, iclass 34, count 0 2006.257.15:27:14.50#ibcon#about to read 5, iclass 34, count 0 2006.257.15:27:14.50#ibcon#read 5, iclass 34, count 0 2006.257.15:27:14.50#ibcon#about to read 6, iclass 34, count 0 2006.257.15:27:14.50#ibcon#read 6, iclass 34, count 0 2006.257.15:27:14.50#ibcon#end of sib2, iclass 34, count 0 2006.257.15:27:14.50#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:27:14.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:27:14.50#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:27:14.50#ibcon#*before write, iclass 34, count 0 2006.257.15:27:14.50#ibcon#enter sib2, iclass 34, count 0 2006.257.15:27:14.50#ibcon#flushed, iclass 34, count 0 2006.257.15:27:14.50#ibcon#about to write, iclass 34, count 0 2006.257.15:27:14.50#ibcon#wrote, iclass 34, count 0 2006.257.15:27:14.50#ibcon#about to read 3, iclass 34, count 0 2006.257.15:27:14.54#ibcon#read 3, iclass 34, count 0 2006.257.15:27:14.54#ibcon#about to read 4, iclass 34, count 0 2006.257.15:27:14.54#ibcon#read 4, iclass 34, count 0 2006.257.15:27:14.54#ibcon#about to read 5, iclass 34, count 0 2006.257.15:27:14.54#ibcon#read 5, iclass 34, count 0 2006.257.15:27:14.54#ibcon#about to read 6, iclass 34, count 0 2006.257.15:27:14.54#ibcon#read 6, iclass 34, count 0 2006.257.15:27:14.54#ibcon#end of sib2, iclass 34, count 0 2006.257.15:27:14.54#ibcon#*after write, iclass 34, count 0 2006.257.15:27:14.54#ibcon#*before return 0, iclass 34, count 0 2006.257.15:27:14.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:14.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:27:14.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:27:14.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:27:14.54$vck44/vb=5,4 2006.257.15:27:14.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.15:27:14.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.15:27:14.54#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:14.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:14.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:14.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:14.60#ibcon#enter wrdev, iclass 36, count 2 2006.257.15:27:14.60#ibcon#first serial, iclass 36, count 2 2006.257.15:27:14.60#ibcon#enter sib2, iclass 36, count 2 2006.257.15:27:14.60#ibcon#flushed, iclass 36, count 2 2006.257.15:27:14.60#ibcon#about to write, iclass 36, count 2 2006.257.15:27:14.60#ibcon#wrote, iclass 36, count 2 2006.257.15:27:14.60#ibcon#about to read 3, iclass 36, count 2 2006.257.15:27:14.62#ibcon#read 3, iclass 36, count 2 2006.257.15:27:14.62#ibcon#about to read 4, iclass 36, count 2 2006.257.15:27:14.62#ibcon#read 4, iclass 36, count 2 2006.257.15:27:14.62#ibcon#about to read 5, iclass 36, count 2 2006.257.15:27:14.62#ibcon#read 5, iclass 36, count 2 2006.257.15:27:14.62#ibcon#about to read 6, iclass 36, count 2 2006.257.15:27:14.62#ibcon#read 6, iclass 36, count 2 2006.257.15:27:14.62#ibcon#end of sib2, iclass 36, count 2 2006.257.15:27:14.62#ibcon#*mode == 0, iclass 36, count 2 2006.257.15:27:14.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.15:27:14.62#ibcon#[27=AT05-04\r\n] 2006.257.15:27:14.62#ibcon#*before write, iclass 36, count 2 2006.257.15:27:14.62#ibcon#enter sib2, iclass 36, count 2 2006.257.15:27:14.62#ibcon#flushed, iclass 36, count 2 2006.257.15:27:14.62#ibcon#about to write, iclass 36, count 2 2006.257.15:27:14.62#ibcon#wrote, iclass 36, count 2 2006.257.15:27:14.62#ibcon#about to read 3, iclass 36, count 2 2006.257.15:27:14.65#ibcon#read 3, iclass 36, count 2 2006.257.15:27:14.65#ibcon#about to read 4, iclass 36, count 2 2006.257.15:27:14.65#ibcon#read 4, iclass 36, count 2 2006.257.15:27:14.65#ibcon#about to read 5, iclass 36, count 2 2006.257.15:27:14.65#ibcon#read 5, iclass 36, count 2 2006.257.15:27:14.65#ibcon#about to read 6, iclass 36, count 2 2006.257.15:27:14.65#ibcon#read 6, iclass 36, count 2 2006.257.15:27:14.65#ibcon#end of sib2, iclass 36, count 2 2006.257.15:27:14.65#ibcon#*after write, iclass 36, count 2 2006.257.15:27:14.65#ibcon#*before return 0, iclass 36, count 2 2006.257.15:27:14.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:14.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:27:14.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.15:27:14.65#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:14.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:14.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:14.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:14.77#ibcon#enter wrdev, iclass 36, count 0 2006.257.15:27:14.77#ibcon#first serial, iclass 36, count 0 2006.257.15:27:14.77#ibcon#enter sib2, iclass 36, count 0 2006.257.15:27:14.77#ibcon#flushed, iclass 36, count 0 2006.257.15:27:14.77#ibcon#about to write, iclass 36, count 0 2006.257.15:27:14.77#ibcon#wrote, iclass 36, count 0 2006.257.15:27:14.77#ibcon#about to read 3, iclass 36, count 0 2006.257.15:27:14.79#ibcon#read 3, iclass 36, count 0 2006.257.15:27:14.79#ibcon#about to read 4, iclass 36, count 0 2006.257.15:27:14.79#ibcon#read 4, iclass 36, count 0 2006.257.15:27:14.79#ibcon#about to read 5, iclass 36, count 0 2006.257.15:27:14.79#ibcon#read 5, iclass 36, count 0 2006.257.15:27:14.79#ibcon#about to read 6, iclass 36, count 0 2006.257.15:27:14.79#ibcon#read 6, iclass 36, count 0 2006.257.15:27:14.79#ibcon#end of sib2, iclass 36, count 0 2006.257.15:27:14.79#ibcon#*mode == 0, iclass 36, count 0 2006.257.15:27:14.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.15:27:14.79#ibcon#[27=USB\r\n] 2006.257.15:27:14.79#ibcon#*before write, iclass 36, count 0 2006.257.15:27:14.79#ibcon#enter sib2, iclass 36, count 0 2006.257.15:27:14.79#ibcon#flushed, iclass 36, count 0 2006.257.15:27:14.79#ibcon#about to write, iclass 36, count 0 2006.257.15:27:14.79#ibcon#wrote, iclass 36, count 0 2006.257.15:27:14.79#ibcon#about to read 3, iclass 36, count 0 2006.257.15:27:14.82#ibcon#read 3, iclass 36, count 0 2006.257.15:27:14.82#ibcon#about to read 4, iclass 36, count 0 2006.257.15:27:14.82#ibcon#read 4, iclass 36, count 0 2006.257.15:27:14.82#ibcon#about to read 5, iclass 36, count 0 2006.257.15:27:14.82#ibcon#read 5, iclass 36, count 0 2006.257.15:27:14.82#ibcon#about to read 6, iclass 36, count 0 2006.257.15:27:14.82#ibcon#read 6, iclass 36, count 0 2006.257.15:27:14.82#ibcon#end of sib2, iclass 36, count 0 2006.257.15:27:14.82#ibcon#*after write, iclass 36, count 0 2006.257.15:27:14.82#ibcon#*before return 0, iclass 36, count 0 2006.257.15:27:14.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:14.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:27:14.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.15:27:14.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.15:27:14.82$vck44/vblo=6,719.99 2006.257.15:27:14.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.15:27:14.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.15:27:14.82#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:14.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:14.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:14.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:14.82#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:27:14.82#ibcon#first serial, iclass 38, count 0 2006.257.15:27:14.82#ibcon#enter sib2, iclass 38, count 0 2006.257.15:27:14.82#ibcon#flushed, iclass 38, count 0 2006.257.15:27:14.82#ibcon#about to write, iclass 38, count 0 2006.257.15:27:14.82#ibcon#wrote, iclass 38, count 0 2006.257.15:27:14.82#ibcon#about to read 3, iclass 38, count 0 2006.257.15:27:14.84#ibcon#read 3, iclass 38, count 0 2006.257.15:27:14.84#ibcon#about to read 4, iclass 38, count 0 2006.257.15:27:14.84#ibcon#read 4, iclass 38, count 0 2006.257.15:27:14.84#ibcon#about to read 5, iclass 38, count 0 2006.257.15:27:14.84#ibcon#read 5, iclass 38, count 0 2006.257.15:27:14.84#ibcon#about to read 6, iclass 38, count 0 2006.257.15:27:14.84#ibcon#read 6, iclass 38, count 0 2006.257.15:27:14.84#ibcon#end of sib2, iclass 38, count 0 2006.257.15:27:14.84#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:27:14.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:27:14.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:27:14.84#ibcon#*before write, iclass 38, count 0 2006.257.15:27:14.84#ibcon#enter sib2, iclass 38, count 0 2006.257.15:27:14.84#ibcon#flushed, iclass 38, count 0 2006.257.15:27:14.84#ibcon#about to write, iclass 38, count 0 2006.257.15:27:14.84#ibcon#wrote, iclass 38, count 0 2006.257.15:27:14.84#ibcon#about to read 3, iclass 38, count 0 2006.257.15:27:14.88#ibcon#read 3, iclass 38, count 0 2006.257.15:27:14.88#ibcon#about to read 4, iclass 38, count 0 2006.257.15:27:14.88#ibcon#read 4, iclass 38, count 0 2006.257.15:27:14.88#ibcon#about to read 5, iclass 38, count 0 2006.257.15:27:14.88#ibcon#read 5, iclass 38, count 0 2006.257.15:27:14.88#ibcon#about to read 6, iclass 38, count 0 2006.257.15:27:14.88#ibcon#read 6, iclass 38, count 0 2006.257.15:27:14.88#ibcon#end of sib2, iclass 38, count 0 2006.257.15:27:14.88#ibcon#*after write, iclass 38, count 0 2006.257.15:27:14.88#ibcon#*before return 0, iclass 38, count 0 2006.257.15:27:14.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:14.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:27:14.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:27:14.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:27:14.88$vck44/vb=6,4 2006.257.15:27:14.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.15:27:14.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.15:27:14.88#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:14.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:14.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:14.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:14.94#ibcon#enter wrdev, iclass 40, count 2 2006.257.15:27:14.94#ibcon#first serial, iclass 40, count 2 2006.257.15:27:14.94#ibcon#enter sib2, iclass 40, count 2 2006.257.15:27:14.94#ibcon#flushed, iclass 40, count 2 2006.257.15:27:14.94#ibcon#about to write, iclass 40, count 2 2006.257.15:27:14.94#ibcon#wrote, iclass 40, count 2 2006.257.15:27:14.94#ibcon#about to read 3, iclass 40, count 2 2006.257.15:27:14.96#ibcon#read 3, iclass 40, count 2 2006.257.15:27:14.96#ibcon#about to read 4, iclass 40, count 2 2006.257.15:27:14.96#ibcon#read 4, iclass 40, count 2 2006.257.15:27:14.96#ibcon#about to read 5, iclass 40, count 2 2006.257.15:27:14.96#ibcon#read 5, iclass 40, count 2 2006.257.15:27:14.96#ibcon#about to read 6, iclass 40, count 2 2006.257.15:27:14.96#ibcon#read 6, iclass 40, count 2 2006.257.15:27:14.96#ibcon#end of sib2, iclass 40, count 2 2006.257.15:27:14.96#ibcon#*mode == 0, iclass 40, count 2 2006.257.15:27:14.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.15:27:14.96#ibcon#[27=AT06-04\r\n] 2006.257.15:27:14.96#ibcon#*before write, iclass 40, count 2 2006.257.15:27:14.96#ibcon#enter sib2, iclass 40, count 2 2006.257.15:27:14.96#ibcon#flushed, iclass 40, count 2 2006.257.15:27:14.96#ibcon#about to write, iclass 40, count 2 2006.257.15:27:14.96#ibcon#wrote, iclass 40, count 2 2006.257.15:27:14.96#ibcon#about to read 3, iclass 40, count 2 2006.257.15:27:14.99#ibcon#read 3, iclass 40, count 2 2006.257.15:27:14.99#ibcon#about to read 4, iclass 40, count 2 2006.257.15:27:14.99#ibcon#read 4, iclass 40, count 2 2006.257.15:27:14.99#ibcon#about to read 5, iclass 40, count 2 2006.257.15:27:14.99#ibcon#read 5, iclass 40, count 2 2006.257.15:27:14.99#ibcon#about to read 6, iclass 40, count 2 2006.257.15:27:14.99#ibcon#read 6, iclass 40, count 2 2006.257.15:27:14.99#ibcon#end of sib2, iclass 40, count 2 2006.257.15:27:14.99#ibcon#*after write, iclass 40, count 2 2006.257.15:27:14.99#ibcon#*before return 0, iclass 40, count 2 2006.257.15:27:14.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:14.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:27:14.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.15:27:14.99#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:14.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:15.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:15.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:15.11#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:27:15.11#ibcon#first serial, iclass 40, count 0 2006.257.15:27:15.11#ibcon#enter sib2, iclass 40, count 0 2006.257.15:27:15.11#ibcon#flushed, iclass 40, count 0 2006.257.15:27:15.11#ibcon#about to write, iclass 40, count 0 2006.257.15:27:15.11#ibcon#wrote, iclass 40, count 0 2006.257.15:27:15.11#ibcon#about to read 3, iclass 40, count 0 2006.257.15:27:15.13#ibcon#read 3, iclass 40, count 0 2006.257.15:27:15.13#ibcon#about to read 4, iclass 40, count 0 2006.257.15:27:15.13#ibcon#read 4, iclass 40, count 0 2006.257.15:27:15.13#ibcon#about to read 5, iclass 40, count 0 2006.257.15:27:15.13#ibcon#read 5, iclass 40, count 0 2006.257.15:27:15.13#ibcon#about to read 6, iclass 40, count 0 2006.257.15:27:15.13#ibcon#read 6, iclass 40, count 0 2006.257.15:27:15.13#ibcon#end of sib2, iclass 40, count 0 2006.257.15:27:15.13#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:27:15.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:27:15.13#ibcon#[27=USB\r\n] 2006.257.15:27:15.13#ibcon#*before write, iclass 40, count 0 2006.257.15:27:15.13#ibcon#enter sib2, iclass 40, count 0 2006.257.15:27:15.13#ibcon#flushed, iclass 40, count 0 2006.257.15:27:15.13#ibcon#about to write, iclass 40, count 0 2006.257.15:27:15.13#ibcon#wrote, iclass 40, count 0 2006.257.15:27:15.13#ibcon#about to read 3, iclass 40, count 0 2006.257.15:27:15.16#ibcon#read 3, iclass 40, count 0 2006.257.15:27:15.16#ibcon#about to read 4, iclass 40, count 0 2006.257.15:27:15.16#ibcon#read 4, iclass 40, count 0 2006.257.15:27:15.16#ibcon#about to read 5, iclass 40, count 0 2006.257.15:27:15.16#ibcon#read 5, iclass 40, count 0 2006.257.15:27:15.16#ibcon#about to read 6, iclass 40, count 0 2006.257.15:27:15.16#ibcon#read 6, iclass 40, count 0 2006.257.15:27:15.16#ibcon#end of sib2, iclass 40, count 0 2006.257.15:27:15.16#ibcon#*after write, iclass 40, count 0 2006.257.15:27:15.16#ibcon#*before return 0, iclass 40, count 0 2006.257.15:27:15.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:15.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:27:15.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:27:15.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:27:15.16$vck44/vblo=7,734.99 2006.257.15:27:15.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.15:27:15.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.15:27:15.16#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:15.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:15.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:15.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:15.16#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:27:15.16#ibcon#first serial, iclass 4, count 0 2006.257.15:27:15.16#ibcon#enter sib2, iclass 4, count 0 2006.257.15:27:15.16#ibcon#flushed, iclass 4, count 0 2006.257.15:27:15.16#ibcon#about to write, iclass 4, count 0 2006.257.15:27:15.16#ibcon#wrote, iclass 4, count 0 2006.257.15:27:15.16#ibcon#about to read 3, iclass 4, count 0 2006.257.15:27:15.18#ibcon#read 3, iclass 4, count 0 2006.257.15:27:15.18#ibcon#about to read 4, iclass 4, count 0 2006.257.15:27:15.18#ibcon#read 4, iclass 4, count 0 2006.257.15:27:15.18#ibcon#about to read 5, iclass 4, count 0 2006.257.15:27:15.18#ibcon#read 5, iclass 4, count 0 2006.257.15:27:15.18#ibcon#about to read 6, iclass 4, count 0 2006.257.15:27:15.18#ibcon#read 6, iclass 4, count 0 2006.257.15:27:15.18#ibcon#end of sib2, iclass 4, count 0 2006.257.15:27:15.18#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:27:15.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:27:15.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:27:15.18#ibcon#*before write, iclass 4, count 0 2006.257.15:27:15.18#ibcon#enter sib2, iclass 4, count 0 2006.257.15:27:15.18#ibcon#flushed, iclass 4, count 0 2006.257.15:27:15.18#ibcon#about to write, iclass 4, count 0 2006.257.15:27:15.18#ibcon#wrote, iclass 4, count 0 2006.257.15:27:15.18#ibcon#about to read 3, iclass 4, count 0 2006.257.15:27:15.22#ibcon#read 3, iclass 4, count 0 2006.257.15:27:15.22#ibcon#about to read 4, iclass 4, count 0 2006.257.15:27:15.22#ibcon#read 4, iclass 4, count 0 2006.257.15:27:15.22#ibcon#about to read 5, iclass 4, count 0 2006.257.15:27:15.22#ibcon#read 5, iclass 4, count 0 2006.257.15:27:15.22#ibcon#about to read 6, iclass 4, count 0 2006.257.15:27:15.22#ibcon#read 6, iclass 4, count 0 2006.257.15:27:15.22#ibcon#end of sib2, iclass 4, count 0 2006.257.15:27:15.22#ibcon#*after write, iclass 4, count 0 2006.257.15:27:15.22#ibcon#*before return 0, iclass 4, count 0 2006.257.15:27:15.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:15.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:27:15.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:27:15.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:27:15.22$vck44/vb=7,4 2006.257.15:27:15.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.15:27:15.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.15:27:15.22#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:15.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:15.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:15.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:15.28#ibcon#enter wrdev, iclass 6, count 2 2006.257.15:27:15.28#ibcon#first serial, iclass 6, count 2 2006.257.15:27:15.28#ibcon#enter sib2, iclass 6, count 2 2006.257.15:27:15.28#ibcon#flushed, iclass 6, count 2 2006.257.15:27:15.28#ibcon#about to write, iclass 6, count 2 2006.257.15:27:15.28#ibcon#wrote, iclass 6, count 2 2006.257.15:27:15.28#ibcon#about to read 3, iclass 6, count 2 2006.257.15:27:15.30#ibcon#read 3, iclass 6, count 2 2006.257.15:27:15.30#ibcon#about to read 4, iclass 6, count 2 2006.257.15:27:15.30#ibcon#read 4, iclass 6, count 2 2006.257.15:27:15.30#ibcon#about to read 5, iclass 6, count 2 2006.257.15:27:15.30#ibcon#read 5, iclass 6, count 2 2006.257.15:27:15.30#ibcon#about to read 6, iclass 6, count 2 2006.257.15:27:15.30#ibcon#read 6, iclass 6, count 2 2006.257.15:27:15.30#ibcon#end of sib2, iclass 6, count 2 2006.257.15:27:15.30#ibcon#*mode == 0, iclass 6, count 2 2006.257.15:27:15.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.15:27:15.30#ibcon#[27=AT07-04\r\n] 2006.257.15:27:15.30#ibcon#*before write, iclass 6, count 2 2006.257.15:27:15.30#ibcon#enter sib2, iclass 6, count 2 2006.257.15:27:15.30#ibcon#flushed, iclass 6, count 2 2006.257.15:27:15.30#ibcon#about to write, iclass 6, count 2 2006.257.15:27:15.30#ibcon#wrote, iclass 6, count 2 2006.257.15:27:15.30#ibcon#about to read 3, iclass 6, count 2 2006.257.15:27:15.33#ibcon#read 3, iclass 6, count 2 2006.257.15:27:15.33#ibcon#about to read 4, iclass 6, count 2 2006.257.15:27:15.33#ibcon#read 4, iclass 6, count 2 2006.257.15:27:15.33#ibcon#about to read 5, iclass 6, count 2 2006.257.15:27:15.33#ibcon#read 5, iclass 6, count 2 2006.257.15:27:15.33#ibcon#about to read 6, iclass 6, count 2 2006.257.15:27:15.33#ibcon#read 6, iclass 6, count 2 2006.257.15:27:15.33#ibcon#end of sib2, iclass 6, count 2 2006.257.15:27:15.33#ibcon#*after write, iclass 6, count 2 2006.257.15:27:15.33#ibcon#*before return 0, iclass 6, count 2 2006.257.15:27:15.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:15.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:27:15.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.15:27:15.33#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:15.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:15.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:15.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:15.45#ibcon#enter wrdev, iclass 6, count 0 2006.257.15:27:15.45#ibcon#first serial, iclass 6, count 0 2006.257.15:27:15.45#ibcon#enter sib2, iclass 6, count 0 2006.257.15:27:15.45#ibcon#flushed, iclass 6, count 0 2006.257.15:27:15.45#ibcon#about to write, iclass 6, count 0 2006.257.15:27:15.45#ibcon#wrote, iclass 6, count 0 2006.257.15:27:15.45#ibcon#about to read 3, iclass 6, count 0 2006.257.15:27:15.47#ibcon#read 3, iclass 6, count 0 2006.257.15:27:15.47#ibcon#about to read 4, iclass 6, count 0 2006.257.15:27:15.47#ibcon#read 4, iclass 6, count 0 2006.257.15:27:15.47#ibcon#about to read 5, iclass 6, count 0 2006.257.15:27:15.47#ibcon#read 5, iclass 6, count 0 2006.257.15:27:15.47#ibcon#about to read 6, iclass 6, count 0 2006.257.15:27:15.47#ibcon#read 6, iclass 6, count 0 2006.257.15:27:15.47#ibcon#end of sib2, iclass 6, count 0 2006.257.15:27:15.47#ibcon#*mode == 0, iclass 6, count 0 2006.257.15:27:15.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.15:27:15.47#ibcon#[27=USB\r\n] 2006.257.15:27:15.47#ibcon#*before write, iclass 6, count 0 2006.257.15:27:15.47#ibcon#enter sib2, iclass 6, count 0 2006.257.15:27:15.47#ibcon#flushed, iclass 6, count 0 2006.257.15:27:15.47#ibcon#about to write, iclass 6, count 0 2006.257.15:27:15.47#ibcon#wrote, iclass 6, count 0 2006.257.15:27:15.47#ibcon#about to read 3, iclass 6, count 0 2006.257.15:27:15.50#ibcon#read 3, iclass 6, count 0 2006.257.15:27:15.50#ibcon#about to read 4, iclass 6, count 0 2006.257.15:27:15.50#ibcon#read 4, iclass 6, count 0 2006.257.15:27:15.50#ibcon#about to read 5, iclass 6, count 0 2006.257.15:27:15.50#ibcon#read 5, iclass 6, count 0 2006.257.15:27:15.50#ibcon#about to read 6, iclass 6, count 0 2006.257.15:27:15.50#ibcon#read 6, iclass 6, count 0 2006.257.15:27:15.50#ibcon#end of sib2, iclass 6, count 0 2006.257.15:27:15.50#ibcon#*after write, iclass 6, count 0 2006.257.15:27:15.50#ibcon#*before return 0, iclass 6, count 0 2006.257.15:27:15.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:15.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:27:15.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.15:27:15.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.15:27:15.50$vck44/vblo=8,744.99 2006.257.15:27:15.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.15:27:15.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.15:27:15.50#ibcon#ireg 17 cls_cnt 0 2006.257.15:27:15.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:15.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:15.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:15.50#ibcon#enter wrdev, iclass 10, count 0 2006.257.15:27:15.50#ibcon#first serial, iclass 10, count 0 2006.257.15:27:15.50#ibcon#enter sib2, iclass 10, count 0 2006.257.15:27:15.50#ibcon#flushed, iclass 10, count 0 2006.257.15:27:15.50#ibcon#about to write, iclass 10, count 0 2006.257.15:27:15.50#ibcon#wrote, iclass 10, count 0 2006.257.15:27:15.50#ibcon#about to read 3, iclass 10, count 0 2006.257.15:27:15.52#ibcon#read 3, iclass 10, count 0 2006.257.15:27:15.52#ibcon#about to read 4, iclass 10, count 0 2006.257.15:27:15.52#ibcon#read 4, iclass 10, count 0 2006.257.15:27:15.52#ibcon#about to read 5, iclass 10, count 0 2006.257.15:27:15.52#ibcon#read 5, iclass 10, count 0 2006.257.15:27:15.52#ibcon#about to read 6, iclass 10, count 0 2006.257.15:27:15.52#ibcon#read 6, iclass 10, count 0 2006.257.15:27:15.52#ibcon#end of sib2, iclass 10, count 0 2006.257.15:27:15.52#ibcon#*mode == 0, iclass 10, count 0 2006.257.15:27:15.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.15:27:15.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:27:15.52#ibcon#*before write, iclass 10, count 0 2006.257.15:27:15.52#ibcon#enter sib2, iclass 10, count 0 2006.257.15:27:15.52#ibcon#flushed, iclass 10, count 0 2006.257.15:27:15.52#ibcon#about to write, iclass 10, count 0 2006.257.15:27:15.52#ibcon#wrote, iclass 10, count 0 2006.257.15:27:15.52#ibcon#about to read 3, iclass 10, count 0 2006.257.15:27:15.56#ibcon#read 3, iclass 10, count 0 2006.257.15:27:15.56#ibcon#about to read 4, iclass 10, count 0 2006.257.15:27:15.56#ibcon#read 4, iclass 10, count 0 2006.257.15:27:15.56#ibcon#about to read 5, iclass 10, count 0 2006.257.15:27:15.56#ibcon#read 5, iclass 10, count 0 2006.257.15:27:15.56#ibcon#about to read 6, iclass 10, count 0 2006.257.15:27:15.56#ibcon#read 6, iclass 10, count 0 2006.257.15:27:15.56#ibcon#end of sib2, iclass 10, count 0 2006.257.15:27:15.56#ibcon#*after write, iclass 10, count 0 2006.257.15:27:15.56#ibcon#*before return 0, iclass 10, count 0 2006.257.15:27:15.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:15.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:27:15.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.15:27:15.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.15:27:15.56$vck44/vb=8,4 2006.257.15:27:15.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.15:27:15.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.15:27:15.56#ibcon#ireg 11 cls_cnt 2 2006.257.15:27:15.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:15.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:15.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:15.62#ibcon#enter wrdev, iclass 12, count 2 2006.257.15:27:15.62#ibcon#first serial, iclass 12, count 2 2006.257.15:27:15.62#ibcon#enter sib2, iclass 12, count 2 2006.257.15:27:15.62#ibcon#flushed, iclass 12, count 2 2006.257.15:27:15.62#ibcon#about to write, iclass 12, count 2 2006.257.15:27:15.62#ibcon#wrote, iclass 12, count 2 2006.257.15:27:15.62#ibcon#about to read 3, iclass 12, count 2 2006.257.15:27:15.64#ibcon#read 3, iclass 12, count 2 2006.257.15:27:15.64#ibcon#about to read 4, iclass 12, count 2 2006.257.15:27:15.64#ibcon#read 4, iclass 12, count 2 2006.257.15:27:15.64#ibcon#about to read 5, iclass 12, count 2 2006.257.15:27:15.64#ibcon#read 5, iclass 12, count 2 2006.257.15:27:15.64#ibcon#about to read 6, iclass 12, count 2 2006.257.15:27:15.64#ibcon#read 6, iclass 12, count 2 2006.257.15:27:15.64#ibcon#end of sib2, iclass 12, count 2 2006.257.15:27:15.64#ibcon#*mode == 0, iclass 12, count 2 2006.257.15:27:15.64#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.15:27:15.64#ibcon#[27=AT08-04\r\n] 2006.257.15:27:15.64#ibcon#*before write, iclass 12, count 2 2006.257.15:27:15.64#ibcon#enter sib2, iclass 12, count 2 2006.257.15:27:15.64#ibcon#flushed, iclass 12, count 2 2006.257.15:27:15.64#ibcon#about to write, iclass 12, count 2 2006.257.15:27:15.64#ibcon#wrote, iclass 12, count 2 2006.257.15:27:15.64#ibcon#about to read 3, iclass 12, count 2 2006.257.15:27:15.67#ibcon#read 3, iclass 12, count 2 2006.257.15:27:15.67#ibcon#about to read 4, iclass 12, count 2 2006.257.15:27:15.67#ibcon#read 4, iclass 12, count 2 2006.257.15:27:15.67#ibcon#about to read 5, iclass 12, count 2 2006.257.15:27:15.67#ibcon#read 5, iclass 12, count 2 2006.257.15:27:15.67#ibcon#about to read 6, iclass 12, count 2 2006.257.15:27:15.67#ibcon#read 6, iclass 12, count 2 2006.257.15:27:15.67#ibcon#end of sib2, iclass 12, count 2 2006.257.15:27:15.67#ibcon#*after write, iclass 12, count 2 2006.257.15:27:15.67#ibcon#*before return 0, iclass 12, count 2 2006.257.15:27:15.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:15.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:27:15.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.15:27:15.67#ibcon#ireg 7 cls_cnt 0 2006.257.15:27:15.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:15.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:15.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:15.79#ibcon#enter wrdev, iclass 12, count 0 2006.257.15:27:15.79#ibcon#first serial, iclass 12, count 0 2006.257.15:27:15.79#ibcon#enter sib2, iclass 12, count 0 2006.257.15:27:15.79#ibcon#flushed, iclass 12, count 0 2006.257.15:27:15.79#ibcon#about to write, iclass 12, count 0 2006.257.15:27:15.79#ibcon#wrote, iclass 12, count 0 2006.257.15:27:15.79#ibcon#about to read 3, iclass 12, count 0 2006.257.15:27:15.81#ibcon#read 3, iclass 12, count 0 2006.257.15:27:15.81#ibcon#about to read 4, iclass 12, count 0 2006.257.15:27:15.81#ibcon#read 4, iclass 12, count 0 2006.257.15:27:15.81#ibcon#about to read 5, iclass 12, count 0 2006.257.15:27:15.81#ibcon#read 5, iclass 12, count 0 2006.257.15:27:15.81#ibcon#about to read 6, iclass 12, count 0 2006.257.15:27:15.81#ibcon#read 6, iclass 12, count 0 2006.257.15:27:15.81#ibcon#end of sib2, iclass 12, count 0 2006.257.15:27:15.81#ibcon#*mode == 0, iclass 12, count 0 2006.257.15:27:15.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.15:27:15.81#ibcon#[27=USB\r\n] 2006.257.15:27:15.81#ibcon#*before write, iclass 12, count 0 2006.257.15:27:15.81#ibcon#enter sib2, iclass 12, count 0 2006.257.15:27:15.81#ibcon#flushed, iclass 12, count 0 2006.257.15:27:15.81#ibcon#about to write, iclass 12, count 0 2006.257.15:27:15.81#ibcon#wrote, iclass 12, count 0 2006.257.15:27:15.81#ibcon#about to read 3, iclass 12, count 0 2006.257.15:27:15.84#ibcon#read 3, iclass 12, count 0 2006.257.15:27:15.84#ibcon#about to read 4, iclass 12, count 0 2006.257.15:27:15.84#ibcon#read 4, iclass 12, count 0 2006.257.15:27:15.84#ibcon#about to read 5, iclass 12, count 0 2006.257.15:27:15.84#ibcon#read 5, iclass 12, count 0 2006.257.15:27:15.84#ibcon#about to read 6, iclass 12, count 0 2006.257.15:27:15.84#ibcon#read 6, iclass 12, count 0 2006.257.15:27:15.84#ibcon#end of sib2, iclass 12, count 0 2006.257.15:27:15.84#ibcon#*after write, iclass 12, count 0 2006.257.15:27:15.84#ibcon#*before return 0, iclass 12, count 0 2006.257.15:27:15.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:15.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:27:15.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.15:27:15.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.15:27:15.84$vck44/vabw=wide 2006.257.15:27:15.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.15:27:15.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.15:27:15.84#ibcon#ireg 8 cls_cnt 0 2006.257.15:27:15.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:15.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:15.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:15.84#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:27:15.84#ibcon#first serial, iclass 14, count 0 2006.257.15:27:15.84#ibcon#enter sib2, iclass 14, count 0 2006.257.15:27:15.84#ibcon#flushed, iclass 14, count 0 2006.257.15:27:15.84#ibcon#about to write, iclass 14, count 0 2006.257.15:27:15.84#ibcon#wrote, iclass 14, count 0 2006.257.15:27:15.84#ibcon#about to read 3, iclass 14, count 0 2006.257.15:27:15.86#ibcon#read 3, iclass 14, count 0 2006.257.15:27:15.86#ibcon#about to read 4, iclass 14, count 0 2006.257.15:27:15.86#ibcon#read 4, iclass 14, count 0 2006.257.15:27:15.86#ibcon#about to read 5, iclass 14, count 0 2006.257.15:27:15.86#ibcon#read 5, iclass 14, count 0 2006.257.15:27:15.86#ibcon#about to read 6, iclass 14, count 0 2006.257.15:27:15.86#ibcon#read 6, iclass 14, count 0 2006.257.15:27:15.86#ibcon#end of sib2, iclass 14, count 0 2006.257.15:27:15.86#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:27:15.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:27:15.86#ibcon#[25=BW32\r\n] 2006.257.15:27:15.86#ibcon#*before write, iclass 14, count 0 2006.257.15:27:15.86#ibcon#enter sib2, iclass 14, count 0 2006.257.15:27:15.86#ibcon#flushed, iclass 14, count 0 2006.257.15:27:15.86#ibcon#about to write, iclass 14, count 0 2006.257.15:27:15.86#ibcon#wrote, iclass 14, count 0 2006.257.15:27:15.86#ibcon#about to read 3, iclass 14, count 0 2006.257.15:27:15.89#ibcon#read 3, iclass 14, count 0 2006.257.15:27:15.89#ibcon#about to read 4, iclass 14, count 0 2006.257.15:27:15.89#ibcon#read 4, iclass 14, count 0 2006.257.15:27:15.89#ibcon#about to read 5, iclass 14, count 0 2006.257.15:27:15.89#ibcon#read 5, iclass 14, count 0 2006.257.15:27:15.89#ibcon#about to read 6, iclass 14, count 0 2006.257.15:27:15.89#ibcon#read 6, iclass 14, count 0 2006.257.15:27:15.89#ibcon#end of sib2, iclass 14, count 0 2006.257.15:27:15.89#ibcon#*after write, iclass 14, count 0 2006.257.15:27:15.89#ibcon#*before return 0, iclass 14, count 0 2006.257.15:27:15.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:15.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:27:15.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:27:15.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:27:15.89$vck44/vbbw=wide 2006.257.15:27:15.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.15:27:15.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.15:27:15.89#ibcon#ireg 8 cls_cnt 0 2006.257.15:27:15.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:27:15.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:27:15.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:27:15.96#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:27:15.96#ibcon#first serial, iclass 16, count 0 2006.257.15:27:15.96#ibcon#enter sib2, iclass 16, count 0 2006.257.15:27:15.96#ibcon#flushed, iclass 16, count 0 2006.257.15:27:15.96#ibcon#about to write, iclass 16, count 0 2006.257.15:27:15.96#ibcon#wrote, iclass 16, count 0 2006.257.15:27:15.96#ibcon#about to read 3, iclass 16, count 0 2006.257.15:27:15.98#ibcon#read 3, iclass 16, count 0 2006.257.15:27:15.98#ibcon#about to read 4, iclass 16, count 0 2006.257.15:27:15.98#ibcon#read 4, iclass 16, count 0 2006.257.15:27:15.98#ibcon#about to read 5, iclass 16, count 0 2006.257.15:27:15.98#ibcon#read 5, iclass 16, count 0 2006.257.15:27:15.98#ibcon#about to read 6, iclass 16, count 0 2006.257.15:27:15.98#ibcon#read 6, iclass 16, count 0 2006.257.15:27:15.98#ibcon#end of sib2, iclass 16, count 0 2006.257.15:27:15.98#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:27:15.98#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:27:15.98#ibcon#[27=BW32\r\n] 2006.257.15:27:15.98#ibcon#*before write, iclass 16, count 0 2006.257.15:27:15.98#ibcon#enter sib2, iclass 16, count 0 2006.257.15:27:15.98#ibcon#flushed, iclass 16, count 0 2006.257.15:27:15.98#ibcon#about to write, iclass 16, count 0 2006.257.15:27:15.98#ibcon#wrote, iclass 16, count 0 2006.257.15:27:15.98#ibcon#about to read 3, iclass 16, count 0 2006.257.15:27:16.01#ibcon#read 3, iclass 16, count 0 2006.257.15:27:16.01#ibcon#about to read 4, iclass 16, count 0 2006.257.15:27:16.01#ibcon#read 4, iclass 16, count 0 2006.257.15:27:16.01#ibcon#about to read 5, iclass 16, count 0 2006.257.15:27:16.01#ibcon#read 5, iclass 16, count 0 2006.257.15:27:16.01#ibcon#about to read 6, iclass 16, count 0 2006.257.15:27:16.01#ibcon#read 6, iclass 16, count 0 2006.257.15:27:16.01#ibcon#end of sib2, iclass 16, count 0 2006.257.15:27:16.01#ibcon#*after write, iclass 16, count 0 2006.257.15:27:16.01#ibcon#*before return 0, iclass 16, count 0 2006.257.15:27:16.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:27:16.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:27:16.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:27:16.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:27:16.01$setupk4/ifdk4 2006.257.15:27:16.01$ifdk4/lo= 2006.257.15:27:16.01$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:27:16.01$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:27:16.01$ifdk4/patch= 2006.257.15:27:16.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:27:16.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:27:16.01$setupk4/!*+20s 2006.257.15:27:20.86#abcon#<5=/14 1.0 2.2 17.49 961013.9\r\n> 2006.257.15:27:20.88#abcon#{5=INTERFACE CLEAR} 2006.257.15:27:20.94#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:27:30.51$setupk4/"tpicd 2006.257.15:27:30.51$setupk4/echo=off 2006.257.15:27:30.51$setupk4/xlog=off 2006.257.15:27:30.51:!2006.257.15:28:10 2006.257.15:27:31.14#trakl#Source acquired 2006.257.15:27:31.14#flagr#flagr/antenna,acquired 2006.257.15:28:10.00:preob 2006.257.15:28:11.13/onsource/TRACKING 2006.257.15:28:11.13:!2006.257.15:28:20 2006.257.15:28:20.00:"tape 2006.257.15:28:20.00:"st=record 2006.257.15:28:20.00:data_valid=on 2006.257.15:28:20.00:midob 2006.257.15:28:20.13/onsource/TRACKING 2006.257.15:28:20.13/wx/17.49,1013.9,96 2006.257.15:28:20.23/cable/+6.4837E-03 2006.257.15:28:21.32/va/01,08,usb,yes,30,32 2006.257.15:28:21.32/va/02,07,usb,yes,33,33 2006.257.15:28:21.32/va/03,08,usb,yes,29,31 2006.257.15:28:21.32/va/04,07,usb,yes,34,35 2006.257.15:28:21.32/va/05,04,usb,yes,30,30 2006.257.15:28:21.32/va/06,04,usb,yes,34,33 2006.257.15:28:21.32/va/07,04,usb,yes,34,35 2006.257.15:28:21.32/va/08,04,usb,yes,29,35 2006.257.15:28:21.55/valo/01,524.99,yes,locked 2006.257.15:28:21.55/valo/02,534.99,yes,locked 2006.257.15:28:21.55/valo/03,564.99,yes,locked 2006.257.15:28:21.55/valo/04,624.99,yes,locked 2006.257.15:28:21.55/valo/05,734.99,yes,locked 2006.257.15:28:21.55/valo/06,814.99,yes,locked 2006.257.15:28:21.55/valo/07,864.99,yes,locked 2006.257.15:28:21.55/valo/08,884.99,yes,locked 2006.257.15:28:22.64/vb/01,04,usb,yes,30,28 2006.257.15:28:22.64/vb/02,05,usb,yes,28,28 2006.257.15:28:22.64/vb/03,04,usb,yes,29,32 2006.257.15:28:22.64/vb/04,05,usb,yes,29,28 2006.257.15:28:22.64/vb/05,04,usb,yes,26,28 2006.257.15:28:22.64/vb/06,04,usb,yes,30,27 2006.257.15:28:22.64/vb/07,04,usb,yes,30,30 2006.257.15:28:22.64/vb/08,04,usb,yes,28,31 2006.257.15:28:22.87/vblo/01,629.99,yes,locked 2006.257.15:28:22.87/vblo/02,634.99,yes,locked 2006.257.15:28:22.87/vblo/03,649.99,yes,locked 2006.257.15:28:22.87/vblo/04,679.99,yes,locked 2006.257.15:28:22.87/vblo/05,709.99,yes,locked 2006.257.15:28:22.87/vblo/06,719.99,yes,locked 2006.257.15:28:22.87/vblo/07,734.99,yes,locked 2006.257.15:28:22.87/vblo/08,744.99,yes,locked 2006.257.15:28:23.02/vabw/8 2006.257.15:28:23.17/vbbw/8 2006.257.15:28:23.26/xfe/off,on,15.2 2006.257.15:28:23.63/ifatt/23,28,28,28 2006.257.15:28:24.07/fmout-gps/S +4.58E-07 2006.257.15:28:24.11:!2006.257.15:30:10 2006.257.15:30:10.01:data_valid=off 2006.257.15:30:10.01:"et 2006.257.15:30:10.01:!+3s 2006.257.15:30:13.02:"tape 2006.257.15:30:13.02:postob 2006.257.15:30:13.19/cable/+6.4857E-03 2006.257.15:30:13.19/wx/17.48,1013.9,96 2006.257.15:30:13.25/fmout-gps/S +4.58E-07 2006.257.15:30:13.25:scan_name=257-1531,jd0609,50 2006.257.15:30:13.25:source=3c345,164258.81,394837.0,2000.0,ccw 2006.257.15:30:14.14#flagr#flagr/antenna,new-source 2006.257.15:30:14.14:checkk5 2006.257.15:30:14.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:30:14.91/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:30:15.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:30:15.74/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:30:16.13/chk_obsdata//k5ts1/T2571528??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.15:30:16.53/chk_obsdata//k5ts2/T2571528??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.15:30:16.93/chk_obsdata//k5ts3/T2571528??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.15:30:17.35/chk_obsdata//k5ts4/T2571528??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.15:30:18.07/k5log//k5ts1_log_newline 2006.257.15:30:18.78/k5log//k5ts2_log_newline 2006.257.15:30:19.50/k5log//k5ts3_log_newline 2006.257.15:30:20.21/k5log//k5ts4_log_newline 2006.257.15:30:20.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:30:20.24:setupk4=1 2006.257.15:30:20.24$setupk4/echo=on 2006.257.15:30:20.24$setupk4/pcalon 2006.257.15:30:20.24$pcalon/"no phase cal control is implemented here 2006.257.15:30:20.24$setupk4/"tpicd=stop 2006.257.15:30:20.24$setupk4/"rec=synch_on 2006.257.15:30:20.24$setupk4/"rec_mode=128 2006.257.15:30:20.24$setupk4/!* 2006.257.15:30:20.24$setupk4/recpk4 2006.257.15:30:20.24$recpk4/recpatch= 2006.257.15:30:20.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:30:20.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:30:20.24$setupk4/vck44 2006.257.15:30:20.25$vck44/valo=1,524.99 2006.257.15:30:20.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.15:30:20.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.15:30:20.25#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:20.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:20.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:20.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:20.25#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:30:20.25#ibcon#first serial, iclass 21, count 0 2006.257.15:30:20.25#ibcon#enter sib2, iclass 21, count 0 2006.257.15:30:20.25#ibcon#flushed, iclass 21, count 0 2006.257.15:30:20.25#ibcon#about to write, iclass 21, count 0 2006.257.15:30:20.25#ibcon#wrote, iclass 21, count 0 2006.257.15:30:20.25#ibcon#about to read 3, iclass 21, count 0 2006.257.15:30:20.26#ibcon#read 3, iclass 21, count 0 2006.257.15:30:20.26#ibcon#about to read 4, iclass 21, count 0 2006.257.15:30:20.26#ibcon#read 4, iclass 21, count 0 2006.257.15:30:20.26#ibcon#about to read 5, iclass 21, count 0 2006.257.15:30:20.26#ibcon#read 5, iclass 21, count 0 2006.257.15:30:20.26#ibcon#about to read 6, iclass 21, count 0 2006.257.15:30:20.26#ibcon#read 6, iclass 21, count 0 2006.257.15:30:20.26#ibcon#end of sib2, iclass 21, count 0 2006.257.15:30:20.26#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:30:20.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:30:20.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:30:20.26#ibcon#*before write, iclass 21, count 0 2006.257.15:30:20.26#ibcon#enter sib2, iclass 21, count 0 2006.257.15:30:20.26#ibcon#flushed, iclass 21, count 0 2006.257.15:30:20.26#ibcon#about to write, iclass 21, count 0 2006.257.15:30:20.26#ibcon#wrote, iclass 21, count 0 2006.257.15:30:20.26#ibcon#about to read 3, iclass 21, count 0 2006.257.15:30:20.31#ibcon#read 3, iclass 21, count 0 2006.257.15:30:20.31#ibcon#about to read 4, iclass 21, count 0 2006.257.15:30:20.31#ibcon#read 4, iclass 21, count 0 2006.257.15:30:20.31#ibcon#about to read 5, iclass 21, count 0 2006.257.15:30:20.31#ibcon#read 5, iclass 21, count 0 2006.257.15:30:20.31#ibcon#about to read 6, iclass 21, count 0 2006.257.15:30:20.31#ibcon#read 6, iclass 21, count 0 2006.257.15:30:20.31#ibcon#end of sib2, iclass 21, count 0 2006.257.15:30:20.31#ibcon#*after write, iclass 21, count 0 2006.257.15:30:20.31#ibcon#*before return 0, iclass 21, count 0 2006.257.15:30:20.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:20.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:20.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:30:20.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:30:20.31$vck44/va=1,8 2006.257.15:30:20.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.15:30:20.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.15:30:20.31#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:20.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:20.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:20.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:20.31#ibcon#enter wrdev, iclass 23, count 2 2006.257.15:30:20.31#ibcon#first serial, iclass 23, count 2 2006.257.15:30:20.31#ibcon#enter sib2, iclass 23, count 2 2006.257.15:30:20.31#ibcon#flushed, iclass 23, count 2 2006.257.15:30:20.31#ibcon#about to write, iclass 23, count 2 2006.257.15:30:20.31#ibcon#wrote, iclass 23, count 2 2006.257.15:30:20.31#ibcon#about to read 3, iclass 23, count 2 2006.257.15:30:20.33#ibcon#read 3, iclass 23, count 2 2006.257.15:30:20.33#ibcon#about to read 4, iclass 23, count 2 2006.257.15:30:20.33#ibcon#read 4, iclass 23, count 2 2006.257.15:30:20.33#ibcon#about to read 5, iclass 23, count 2 2006.257.15:30:20.33#ibcon#read 5, iclass 23, count 2 2006.257.15:30:20.33#ibcon#about to read 6, iclass 23, count 2 2006.257.15:30:20.33#ibcon#read 6, iclass 23, count 2 2006.257.15:30:20.33#ibcon#end of sib2, iclass 23, count 2 2006.257.15:30:20.33#ibcon#*mode == 0, iclass 23, count 2 2006.257.15:30:20.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.15:30:20.33#ibcon#[25=AT01-08\r\n] 2006.257.15:30:20.33#ibcon#*before write, iclass 23, count 2 2006.257.15:30:20.33#ibcon#enter sib2, iclass 23, count 2 2006.257.15:30:20.33#ibcon#flushed, iclass 23, count 2 2006.257.15:30:20.33#ibcon#about to write, iclass 23, count 2 2006.257.15:30:20.33#ibcon#wrote, iclass 23, count 2 2006.257.15:30:20.33#ibcon#about to read 3, iclass 23, count 2 2006.257.15:30:20.36#ibcon#read 3, iclass 23, count 2 2006.257.15:30:20.36#ibcon#about to read 4, iclass 23, count 2 2006.257.15:30:20.36#ibcon#read 4, iclass 23, count 2 2006.257.15:30:20.36#ibcon#about to read 5, iclass 23, count 2 2006.257.15:30:20.36#ibcon#read 5, iclass 23, count 2 2006.257.15:30:20.36#ibcon#about to read 6, iclass 23, count 2 2006.257.15:30:20.36#ibcon#read 6, iclass 23, count 2 2006.257.15:30:20.36#ibcon#end of sib2, iclass 23, count 2 2006.257.15:30:20.36#ibcon#*after write, iclass 23, count 2 2006.257.15:30:20.36#ibcon#*before return 0, iclass 23, count 2 2006.257.15:30:20.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:20.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:20.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.15:30:20.36#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:20.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:20.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:20.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:20.48#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:30:20.48#ibcon#first serial, iclass 23, count 0 2006.257.15:30:20.48#ibcon#enter sib2, iclass 23, count 0 2006.257.15:30:20.48#ibcon#flushed, iclass 23, count 0 2006.257.15:30:20.48#ibcon#about to write, iclass 23, count 0 2006.257.15:30:20.48#ibcon#wrote, iclass 23, count 0 2006.257.15:30:20.48#ibcon#about to read 3, iclass 23, count 0 2006.257.15:30:20.50#ibcon#read 3, iclass 23, count 0 2006.257.15:30:20.50#ibcon#about to read 4, iclass 23, count 0 2006.257.15:30:20.50#ibcon#read 4, iclass 23, count 0 2006.257.15:30:20.50#ibcon#about to read 5, iclass 23, count 0 2006.257.15:30:20.50#ibcon#read 5, iclass 23, count 0 2006.257.15:30:20.50#ibcon#about to read 6, iclass 23, count 0 2006.257.15:30:20.50#ibcon#read 6, iclass 23, count 0 2006.257.15:30:20.50#ibcon#end of sib2, iclass 23, count 0 2006.257.15:30:20.50#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:30:20.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:30:20.50#ibcon#[25=USB\r\n] 2006.257.15:30:20.50#ibcon#*before write, iclass 23, count 0 2006.257.15:30:20.50#ibcon#enter sib2, iclass 23, count 0 2006.257.15:30:20.50#ibcon#flushed, iclass 23, count 0 2006.257.15:30:20.50#ibcon#about to write, iclass 23, count 0 2006.257.15:30:20.50#ibcon#wrote, iclass 23, count 0 2006.257.15:30:20.50#ibcon#about to read 3, iclass 23, count 0 2006.257.15:30:20.53#ibcon#read 3, iclass 23, count 0 2006.257.15:30:20.53#ibcon#about to read 4, iclass 23, count 0 2006.257.15:30:20.53#ibcon#read 4, iclass 23, count 0 2006.257.15:30:20.53#ibcon#about to read 5, iclass 23, count 0 2006.257.15:30:20.53#ibcon#read 5, iclass 23, count 0 2006.257.15:30:20.53#ibcon#about to read 6, iclass 23, count 0 2006.257.15:30:20.53#ibcon#read 6, iclass 23, count 0 2006.257.15:30:20.53#ibcon#end of sib2, iclass 23, count 0 2006.257.15:30:20.53#ibcon#*after write, iclass 23, count 0 2006.257.15:30:20.53#ibcon#*before return 0, iclass 23, count 0 2006.257.15:30:20.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:20.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:20.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:30:20.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:30:20.53$vck44/valo=2,534.99 2006.257.15:30:20.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.15:30:20.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.15:30:20.53#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:20.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:20.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:20.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:20.53#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:30:20.53#ibcon#first serial, iclass 25, count 0 2006.257.15:30:20.53#ibcon#enter sib2, iclass 25, count 0 2006.257.15:30:20.53#ibcon#flushed, iclass 25, count 0 2006.257.15:30:20.53#ibcon#about to write, iclass 25, count 0 2006.257.15:30:20.53#ibcon#wrote, iclass 25, count 0 2006.257.15:30:20.53#ibcon#about to read 3, iclass 25, count 0 2006.257.15:30:20.55#ibcon#read 3, iclass 25, count 0 2006.257.15:30:20.55#ibcon#about to read 4, iclass 25, count 0 2006.257.15:30:20.55#ibcon#read 4, iclass 25, count 0 2006.257.15:30:20.55#ibcon#about to read 5, iclass 25, count 0 2006.257.15:30:20.55#ibcon#read 5, iclass 25, count 0 2006.257.15:30:20.55#ibcon#about to read 6, iclass 25, count 0 2006.257.15:30:20.55#ibcon#read 6, iclass 25, count 0 2006.257.15:30:20.55#ibcon#end of sib2, iclass 25, count 0 2006.257.15:30:20.55#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:30:20.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:30:20.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:30:20.55#ibcon#*before write, iclass 25, count 0 2006.257.15:30:20.55#ibcon#enter sib2, iclass 25, count 0 2006.257.15:30:20.55#ibcon#flushed, iclass 25, count 0 2006.257.15:30:20.55#ibcon#about to write, iclass 25, count 0 2006.257.15:30:20.55#ibcon#wrote, iclass 25, count 0 2006.257.15:30:20.55#ibcon#about to read 3, iclass 25, count 0 2006.257.15:30:20.59#ibcon#read 3, iclass 25, count 0 2006.257.15:30:20.59#ibcon#about to read 4, iclass 25, count 0 2006.257.15:30:20.59#ibcon#read 4, iclass 25, count 0 2006.257.15:30:20.59#ibcon#about to read 5, iclass 25, count 0 2006.257.15:30:20.59#ibcon#read 5, iclass 25, count 0 2006.257.15:30:20.59#ibcon#about to read 6, iclass 25, count 0 2006.257.15:30:20.59#ibcon#read 6, iclass 25, count 0 2006.257.15:30:20.59#ibcon#end of sib2, iclass 25, count 0 2006.257.15:30:20.59#ibcon#*after write, iclass 25, count 0 2006.257.15:30:20.59#ibcon#*before return 0, iclass 25, count 0 2006.257.15:30:20.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:20.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:20.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:30:20.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:30:20.59$vck44/va=2,7 2006.257.15:30:20.59#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.15:30:20.59#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.15:30:20.59#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:20.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:20.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:20.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:20.65#ibcon#enter wrdev, iclass 27, count 2 2006.257.15:30:20.65#ibcon#first serial, iclass 27, count 2 2006.257.15:30:20.65#ibcon#enter sib2, iclass 27, count 2 2006.257.15:30:20.65#ibcon#flushed, iclass 27, count 2 2006.257.15:30:20.65#ibcon#about to write, iclass 27, count 2 2006.257.15:30:20.65#ibcon#wrote, iclass 27, count 2 2006.257.15:30:20.65#ibcon#about to read 3, iclass 27, count 2 2006.257.15:30:20.67#ibcon#read 3, iclass 27, count 2 2006.257.15:30:20.67#ibcon#about to read 4, iclass 27, count 2 2006.257.15:30:20.67#ibcon#read 4, iclass 27, count 2 2006.257.15:30:20.67#ibcon#about to read 5, iclass 27, count 2 2006.257.15:30:20.67#ibcon#read 5, iclass 27, count 2 2006.257.15:30:20.67#ibcon#about to read 6, iclass 27, count 2 2006.257.15:30:20.67#ibcon#read 6, iclass 27, count 2 2006.257.15:30:20.67#ibcon#end of sib2, iclass 27, count 2 2006.257.15:30:20.67#ibcon#*mode == 0, iclass 27, count 2 2006.257.15:30:20.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.15:30:20.67#ibcon#[25=AT02-07\r\n] 2006.257.15:30:20.67#ibcon#*before write, iclass 27, count 2 2006.257.15:30:20.67#ibcon#enter sib2, iclass 27, count 2 2006.257.15:30:20.67#ibcon#flushed, iclass 27, count 2 2006.257.15:30:20.67#ibcon#about to write, iclass 27, count 2 2006.257.15:30:20.67#ibcon#wrote, iclass 27, count 2 2006.257.15:30:20.67#ibcon#about to read 3, iclass 27, count 2 2006.257.15:30:20.70#ibcon#read 3, iclass 27, count 2 2006.257.15:30:20.70#ibcon#about to read 4, iclass 27, count 2 2006.257.15:30:20.70#ibcon#read 4, iclass 27, count 2 2006.257.15:30:20.70#ibcon#about to read 5, iclass 27, count 2 2006.257.15:30:20.70#ibcon#read 5, iclass 27, count 2 2006.257.15:30:20.70#ibcon#about to read 6, iclass 27, count 2 2006.257.15:30:20.70#ibcon#read 6, iclass 27, count 2 2006.257.15:30:20.70#ibcon#end of sib2, iclass 27, count 2 2006.257.15:30:20.70#ibcon#*after write, iclass 27, count 2 2006.257.15:30:20.70#ibcon#*before return 0, iclass 27, count 2 2006.257.15:30:20.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:20.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:20.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.15:30:20.70#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:20.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:20.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:20.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:20.82#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:30:20.82#ibcon#first serial, iclass 27, count 0 2006.257.15:30:20.82#ibcon#enter sib2, iclass 27, count 0 2006.257.15:30:20.82#ibcon#flushed, iclass 27, count 0 2006.257.15:30:20.82#ibcon#about to write, iclass 27, count 0 2006.257.15:30:20.82#ibcon#wrote, iclass 27, count 0 2006.257.15:30:20.82#ibcon#about to read 3, iclass 27, count 0 2006.257.15:30:20.84#ibcon#read 3, iclass 27, count 0 2006.257.15:30:20.84#ibcon#about to read 4, iclass 27, count 0 2006.257.15:30:20.84#ibcon#read 4, iclass 27, count 0 2006.257.15:30:20.84#ibcon#about to read 5, iclass 27, count 0 2006.257.15:30:20.84#ibcon#read 5, iclass 27, count 0 2006.257.15:30:20.84#ibcon#about to read 6, iclass 27, count 0 2006.257.15:30:20.84#ibcon#read 6, iclass 27, count 0 2006.257.15:30:20.84#ibcon#end of sib2, iclass 27, count 0 2006.257.15:30:20.84#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:30:20.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:30:20.84#ibcon#[25=USB\r\n] 2006.257.15:30:20.84#ibcon#*before write, iclass 27, count 0 2006.257.15:30:20.84#ibcon#enter sib2, iclass 27, count 0 2006.257.15:30:20.84#ibcon#flushed, iclass 27, count 0 2006.257.15:30:20.84#ibcon#about to write, iclass 27, count 0 2006.257.15:30:20.84#ibcon#wrote, iclass 27, count 0 2006.257.15:30:20.84#ibcon#about to read 3, iclass 27, count 0 2006.257.15:30:20.87#ibcon#read 3, iclass 27, count 0 2006.257.15:30:20.87#ibcon#about to read 4, iclass 27, count 0 2006.257.15:30:20.87#ibcon#read 4, iclass 27, count 0 2006.257.15:30:20.87#ibcon#about to read 5, iclass 27, count 0 2006.257.15:30:20.87#ibcon#read 5, iclass 27, count 0 2006.257.15:30:20.87#ibcon#about to read 6, iclass 27, count 0 2006.257.15:30:20.87#ibcon#read 6, iclass 27, count 0 2006.257.15:30:20.87#ibcon#end of sib2, iclass 27, count 0 2006.257.15:30:20.87#ibcon#*after write, iclass 27, count 0 2006.257.15:30:20.87#ibcon#*before return 0, iclass 27, count 0 2006.257.15:30:20.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:20.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:20.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:30:20.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:30:20.87$vck44/valo=3,564.99 2006.257.15:30:20.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.15:30:20.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.15:30:20.87#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:20.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:30:20.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:30:20.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:30:20.87#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:30:20.87#ibcon#first serial, iclass 29, count 0 2006.257.15:30:20.87#ibcon#enter sib2, iclass 29, count 0 2006.257.15:30:20.87#ibcon#flushed, iclass 29, count 0 2006.257.15:30:20.87#ibcon#about to write, iclass 29, count 0 2006.257.15:30:20.87#ibcon#wrote, iclass 29, count 0 2006.257.15:30:20.87#ibcon#about to read 3, iclass 29, count 0 2006.257.15:30:20.89#ibcon#read 3, iclass 29, count 0 2006.257.15:30:20.89#ibcon#about to read 4, iclass 29, count 0 2006.257.15:30:20.89#ibcon#read 4, iclass 29, count 0 2006.257.15:30:20.89#ibcon#about to read 5, iclass 29, count 0 2006.257.15:30:20.89#ibcon#read 5, iclass 29, count 0 2006.257.15:30:20.89#ibcon#about to read 6, iclass 29, count 0 2006.257.15:30:20.89#ibcon#read 6, iclass 29, count 0 2006.257.15:30:20.89#ibcon#end of sib2, iclass 29, count 0 2006.257.15:30:20.89#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:30:20.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:30:20.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:30:20.89#ibcon#*before write, iclass 29, count 0 2006.257.15:30:20.89#ibcon#enter sib2, iclass 29, count 0 2006.257.15:30:20.89#ibcon#flushed, iclass 29, count 0 2006.257.15:30:20.89#ibcon#about to write, iclass 29, count 0 2006.257.15:30:20.89#ibcon#wrote, iclass 29, count 0 2006.257.15:30:20.89#ibcon#about to read 3, iclass 29, count 0 2006.257.15:30:20.93#ibcon#read 3, iclass 29, count 0 2006.257.15:30:20.93#ibcon#about to read 4, iclass 29, count 0 2006.257.15:30:20.93#ibcon#read 4, iclass 29, count 0 2006.257.15:30:20.93#ibcon#about to read 5, iclass 29, count 0 2006.257.15:30:20.93#ibcon#read 5, iclass 29, count 0 2006.257.15:30:20.93#ibcon#about to read 6, iclass 29, count 0 2006.257.15:30:20.93#ibcon#read 6, iclass 29, count 0 2006.257.15:30:20.93#ibcon#end of sib2, iclass 29, count 0 2006.257.15:30:20.93#ibcon#*after write, iclass 29, count 0 2006.257.15:30:20.93#ibcon#*before return 0, iclass 29, count 0 2006.257.15:30:20.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:30:20.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:30:20.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:30:20.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:30:20.93$vck44/va=3,8 2006.257.15:30:20.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.15:30:20.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.15:30:20.93#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:20.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:30:20.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:30:20.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:30:20.99#ibcon#enter wrdev, iclass 31, count 2 2006.257.15:30:20.99#ibcon#first serial, iclass 31, count 2 2006.257.15:30:20.99#ibcon#enter sib2, iclass 31, count 2 2006.257.15:30:20.99#ibcon#flushed, iclass 31, count 2 2006.257.15:30:20.99#ibcon#about to write, iclass 31, count 2 2006.257.15:30:20.99#ibcon#wrote, iclass 31, count 2 2006.257.15:30:20.99#ibcon#about to read 3, iclass 31, count 2 2006.257.15:30:21.01#ibcon#read 3, iclass 31, count 2 2006.257.15:30:21.01#ibcon#about to read 4, iclass 31, count 2 2006.257.15:30:21.01#ibcon#read 4, iclass 31, count 2 2006.257.15:30:21.01#ibcon#about to read 5, iclass 31, count 2 2006.257.15:30:21.01#ibcon#read 5, iclass 31, count 2 2006.257.15:30:21.01#ibcon#about to read 6, iclass 31, count 2 2006.257.15:30:21.01#ibcon#read 6, iclass 31, count 2 2006.257.15:30:21.01#ibcon#end of sib2, iclass 31, count 2 2006.257.15:30:21.01#ibcon#*mode == 0, iclass 31, count 2 2006.257.15:30:21.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.15:30:21.01#ibcon#[25=AT03-08\r\n] 2006.257.15:30:21.01#ibcon#*before write, iclass 31, count 2 2006.257.15:30:21.01#ibcon#enter sib2, iclass 31, count 2 2006.257.15:30:21.01#ibcon#flushed, iclass 31, count 2 2006.257.15:30:21.01#ibcon#about to write, iclass 31, count 2 2006.257.15:30:21.01#ibcon#wrote, iclass 31, count 2 2006.257.15:30:21.01#ibcon#about to read 3, iclass 31, count 2 2006.257.15:30:21.04#ibcon#read 3, iclass 31, count 2 2006.257.15:30:21.04#ibcon#about to read 4, iclass 31, count 2 2006.257.15:30:21.04#ibcon#read 4, iclass 31, count 2 2006.257.15:30:21.04#ibcon#about to read 5, iclass 31, count 2 2006.257.15:30:21.04#ibcon#read 5, iclass 31, count 2 2006.257.15:30:21.04#ibcon#about to read 6, iclass 31, count 2 2006.257.15:30:21.04#ibcon#read 6, iclass 31, count 2 2006.257.15:30:21.04#ibcon#end of sib2, iclass 31, count 2 2006.257.15:30:21.04#ibcon#*after write, iclass 31, count 2 2006.257.15:30:21.04#ibcon#*before return 0, iclass 31, count 2 2006.257.15:30:21.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:30:21.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:30:21.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.15:30:21.04#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:21.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:30:21.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:30:21.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:30:21.16#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:30:21.16#ibcon#first serial, iclass 31, count 0 2006.257.15:30:21.16#ibcon#enter sib2, iclass 31, count 0 2006.257.15:30:21.16#ibcon#flushed, iclass 31, count 0 2006.257.15:30:21.16#ibcon#about to write, iclass 31, count 0 2006.257.15:30:21.16#ibcon#wrote, iclass 31, count 0 2006.257.15:30:21.16#ibcon#about to read 3, iclass 31, count 0 2006.257.15:30:21.18#ibcon#read 3, iclass 31, count 0 2006.257.15:30:21.18#ibcon#about to read 4, iclass 31, count 0 2006.257.15:30:21.18#ibcon#read 4, iclass 31, count 0 2006.257.15:30:21.18#ibcon#about to read 5, iclass 31, count 0 2006.257.15:30:21.18#ibcon#read 5, iclass 31, count 0 2006.257.15:30:21.18#ibcon#about to read 6, iclass 31, count 0 2006.257.15:30:21.18#ibcon#read 6, iclass 31, count 0 2006.257.15:30:21.18#ibcon#end of sib2, iclass 31, count 0 2006.257.15:30:21.18#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:30:21.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:30:21.18#ibcon#[25=USB\r\n] 2006.257.15:30:21.18#ibcon#*before write, iclass 31, count 0 2006.257.15:30:21.18#ibcon#enter sib2, iclass 31, count 0 2006.257.15:30:21.18#ibcon#flushed, iclass 31, count 0 2006.257.15:30:21.18#ibcon#about to write, iclass 31, count 0 2006.257.15:30:21.18#ibcon#wrote, iclass 31, count 0 2006.257.15:30:21.18#ibcon#about to read 3, iclass 31, count 0 2006.257.15:30:21.21#ibcon#read 3, iclass 31, count 0 2006.257.15:30:21.21#ibcon#about to read 4, iclass 31, count 0 2006.257.15:30:21.21#ibcon#read 4, iclass 31, count 0 2006.257.15:30:21.21#ibcon#about to read 5, iclass 31, count 0 2006.257.15:30:21.21#ibcon#read 5, iclass 31, count 0 2006.257.15:30:21.21#ibcon#about to read 6, iclass 31, count 0 2006.257.15:30:21.21#ibcon#read 6, iclass 31, count 0 2006.257.15:30:21.21#ibcon#end of sib2, iclass 31, count 0 2006.257.15:30:21.21#ibcon#*after write, iclass 31, count 0 2006.257.15:30:21.21#ibcon#*before return 0, iclass 31, count 0 2006.257.15:30:21.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:30:21.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:30:21.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:30:21.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:30:21.21$vck44/valo=4,624.99 2006.257.15:30:21.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.15:30:21.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.15:30:21.21#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:21.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:30:21.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:30:21.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:30:21.21#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:30:21.21#ibcon#first serial, iclass 33, count 0 2006.257.15:30:21.21#ibcon#enter sib2, iclass 33, count 0 2006.257.15:30:21.21#ibcon#flushed, iclass 33, count 0 2006.257.15:30:21.21#ibcon#about to write, iclass 33, count 0 2006.257.15:30:21.21#ibcon#wrote, iclass 33, count 0 2006.257.15:30:21.21#ibcon#about to read 3, iclass 33, count 0 2006.257.15:30:21.23#ibcon#read 3, iclass 33, count 0 2006.257.15:30:21.23#ibcon#about to read 4, iclass 33, count 0 2006.257.15:30:21.23#ibcon#read 4, iclass 33, count 0 2006.257.15:30:21.23#ibcon#about to read 5, iclass 33, count 0 2006.257.15:30:21.23#ibcon#read 5, iclass 33, count 0 2006.257.15:30:21.23#ibcon#about to read 6, iclass 33, count 0 2006.257.15:30:21.23#ibcon#read 6, iclass 33, count 0 2006.257.15:30:21.23#ibcon#end of sib2, iclass 33, count 0 2006.257.15:30:21.23#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:30:21.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:30:21.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:30:21.23#ibcon#*before write, iclass 33, count 0 2006.257.15:30:21.23#ibcon#enter sib2, iclass 33, count 0 2006.257.15:30:21.23#ibcon#flushed, iclass 33, count 0 2006.257.15:30:21.23#ibcon#about to write, iclass 33, count 0 2006.257.15:30:21.23#ibcon#wrote, iclass 33, count 0 2006.257.15:30:21.23#ibcon#about to read 3, iclass 33, count 0 2006.257.15:30:21.27#ibcon#read 3, iclass 33, count 0 2006.257.15:30:21.27#ibcon#about to read 4, iclass 33, count 0 2006.257.15:30:21.27#ibcon#read 4, iclass 33, count 0 2006.257.15:30:21.27#ibcon#about to read 5, iclass 33, count 0 2006.257.15:30:21.27#ibcon#read 5, iclass 33, count 0 2006.257.15:30:21.27#ibcon#about to read 6, iclass 33, count 0 2006.257.15:30:21.27#ibcon#read 6, iclass 33, count 0 2006.257.15:30:21.27#ibcon#end of sib2, iclass 33, count 0 2006.257.15:30:21.27#ibcon#*after write, iclass 33, count 0 2006.257.15:30:21.27#ibcon#*before return 0, iclass 33, count 0 2006.257.15:30:21.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:30:21.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:30:21.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:30:21.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:30:21.27$vck44/va=4,7 2006.257.15:30:21.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.15:30:21.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.15:30:21.27#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:21.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:30:21.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:30:21.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:30:21.33#ibcon#enter wrdev, iclass 35, count 2 2006.257.15:30:21.33#ibcon#first serial, iclass 35, count 2 2006.257.15:30:21.33#ibcon#enter sib2, iclass 35, count 2 2006.257.15:30:21.33#ibcon#flushed, iclass 35, count 2 2006.257.15:30:21.33#ibcon#about to write, iclass 35, count 2 2006.257.15:30:21.33#ibcon#wrote, iclass 35, count 2 2006.257.15:30:21.33#ibcon#about to read 3, iclass 35, count 2 2006.257.15:30:21.35#ibcon#read 3, iclass 35, count 2 2006.257.15:30:21.35#ibcon#about to read 4, iclass 35, count 2 2006.257.15:30:21.35#ibcon#read 4, iclass 35, count 2 2006.257.15:30:21.35#ibcon#about to read 5, iclass 35, count 2 2006.257.15:30:21.35#ibcon#read 5, iclass 35, count 2 2006.257.15:30:21.35#ibcon#about to read 6, iclass 35, count 2 2006.257.15:30:21.35#ibcon#read 6, iclass 35, count 2 2006.257.15:30:21.35#ibcon#end of sib2, iclass 35, count 2 2006.257.15:30:21.35#ibcon#*mode == 0, iclass 35, count 2 2006.257.15:30:21.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.15:30:21.35#ibcon#[25=AT04-07\r\n] 2006.257.15:30:21.35#ibcon#*before write, iclass 35, count 2 2006.257.15:30:21.35#ibcon#enter sib2, iclass 35, count 2 2006.257.15:30:21.35#ibcon#flushed, iclass 35, count 2 2006.257.15:30:21.35#ibcon#about to write, iclass 35, count 2 2006.257.15:30:21.35#ibcon#wrote, iclass 35, count 2 2006.257.15:30:21.35#ibcon#about to read 3, iclass 35, count 2 2006.257.15:30:21.38#ibcon#read 3, iclass 35, count 2 2006.257.15:30:21.38#ibcon#about to read 4, iclass 35, count 2 2006.257.15:30:21.38#ibcon#read 4, iclass 35, count 2 2006.257.15:30:21.38#ibcon#about to read 5, iclass 35, count 2 2006.257.15:30:21.38#ibcon#read 5, iclass 35, count 2 2006.257.15:30:21.38#ibcon#about to read 6, iclass 35, count 2 2006.257.15:30:21.38#ibcon#read 6, iclass 35, count 2 2006.257.15:30:21.38#ibcon#end of sib2, iclass 35, count 2 2006.257.15:30:21.38#ibcon#*after write, iclass 35, count 2 2006.257.15:30:21.38#ibcon#*before return 0, iclass 35, count 2 2006.257.15:30:21.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:30:21.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:30:21.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.15:30:21.38#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:21.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:30:21.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:30:21.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:30:21.50#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:30:21.50#ibcon#first serial, iclass 35, count 0 2006.257.15:30:21.50#ibcon#enter sib2, iclass 35, count 0 2006.257.15:30:21.50#ibcon#flushed, iclass 35, count 0 2006.257.15:30:21.50#ibcon#about to write, iclass 35, count 0 2006.257.15:30:21.50#ibcon#wrote, iclass 35, count 0 2006.257.15:30:21.50#ibcon#about to read 3, iclass 35, count 0 2006.257.15:30:21.52#ibcon#read 3, iclass 35, count 0 2006.257.15:30:21.52#ibcon#about to read 4, iclass 35, count 0 2006.257.15:30:21.52#ibcon#read 4, iclass 35, count 0 2006.257.15:30:21.52#ibcon#about to read 5, iclass 35, count 0 2006.257.15:30:21.52#ibcon#read 5, iclass 35, count 0 2006.257.15:30:21.52#ibcon#about to read 6, iclass 35, count 0 2006.257.15:30:21.52#ibcon#read 6, iclass 35, count 0 2006.257.15:30:21.52#ibcon#end of sib2, iclass 35, count 0 2006.257.15:30:21.52#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:30:21.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:30:21.52#ibcon#[25=USB\r\n] 2006.257.15:30:21.52#ibcon#*before write, iclass 35, count 0 2006.257.15:30:21.52#ibcon#enter sib2, iclass 35, count 0 2006.257.15:30:21.52#ibcon#flushed, iclass 35, count 0 2006.257.15:30:21.52#ibcon#about to write, iclass 35, count 0 2006.257.15:30:21.52#ibcon#wrote, iclass 35, count 0 2006.257.15:30:21.52#ibcon#about to read 3, iclass 35, count 0 2006.257.15:30:21.55#ibcon#read 3, iclass 35, count 0 2006.257.15:30:21.55#ibcon#about to read 4, iclass 35, count 0 2006.257.15:30:21.55#ibcon#read 4, iclass 35, count 0 2006.257.15:30:21.55#ibcon#about to read 5, iclass 35, count 0 2006.257.15:30:21.55#ibcon#read 5, iclass 35, count 0 2006.257.15:30:21.55#ibcon#about to read 6, iclass 35, count 0 2006.257.15:30:21.55#ibcon#read 6, iclass 35, count 0 2006.257.15:30:21.55#ibcon#end of sib2, iclass 35, count 0 2006.257.15:30:21.55#ibcon#*after write, iclass 35, count 0 2006.257.15:30:21.55#ibcon#*before return 0, iclass 35, count 0 2006.257.15:30:21.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:30:21.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:30:21.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:30:21.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:30:21.55$vck44/valo=5,734.99 2006.257.15:30:21.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.15:30:21.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.15:30:21.55#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:21.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:21.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:21.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:21.55#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:30:21.55#ibcon#first serial, iclass 37, count 0 2006.257.15:30:21.55#ibcon#enter sib2, iclass 37, count 0 2006.257.15:30:21.55#ibcon#flushed, iclass 37, count 0 2006.257.15:30:21.55#ibcon#about to write, iclass 37, count 0 2006.257.15:30:21.55#ibcon#wrote, iclass 37, count 0 2006.257.15:30:21.55#ibcon#about to read 3, iclass 37, count 0 2006.257.15:30:21.57#ibcon#read 3, iclass 37, count 0 2006.257.15:30:21.57#ibcon#about to read 4, iclass 37, count 0 2006.257.15:30:21.57#ibcon#read 4, iclass 37, count 0 2006.257.15:30:21.57#ibcon#about to read 5, iclass 37, count 0 2006.257.15:30:21.57#ibcon#read 5, iclass 37, count 0 2006.257.15:30:21.57#ibcon#about to read 6, iclass 37, count 0 2006.257.15:30:21.57#ibcon#read 6, iclass 37, count 0 2006.257.15:30:21.57#ibcon#end of sib2, iclass 37, count 0 2006.257.15:30:21.57#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:30:21.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:30:21.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:30:21.57#ibcon#*before write, iclass 37, count 0 2006.257.15:30:21.57#ibcon#enter sib2, iclass 37, count 0 2006.257.15:30:21.57#ibcon#flushed, iclass 37, count 0 2006.257.15:30:21.57#ibcon#about to write, iclass 37, count 0 2006.257.15:30:21.57#ibcon#wrote, iclass 37, count 0 2006.257.15:30:21.57#ibcon#about to read 3, iclass 37, count 0 2006.257.15:30:21.61#ibcon#read 3, iclass 37, count 0 2006.257.15:30:21.61#ibcon#about to read 4, iclass 37, count 0 2006.257.15:30:21.61#ibcon#read 4, iclass 37, count 0 2006.257.15:30:21.61#ibcon#about to read 5, iclass 37, count 0 2006.257.15:30:21.61#ibcon#read 5, iclass 37, count 0 2006.257.15:30:21.61#ibcon#about to read 6, iclass 37, count 0 2006.257.15:30:21.61#ibcon#read 6, iclass 37, count 0 2006.257.15:30:21.61#ibcon#end of sib2, iclass 37, count 0 2006.257.15:30:21.61#ibcon#*after write, iclass 37, count 0 2006.257.15:30:21.61#ibcon#*before return 0, iclass 37, count 0 2006.257.15:30:21.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:21.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:21.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:30:21.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:30:21.61$vck44/va=5,4 2006.257.15:30:21.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.15:30:21.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.15:30:21.61#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:21.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:21.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:21.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:21.67#ibcon#enter wrdev, iclass 39, count 2 2006.257.15:30:21.67#ibcon#first serial, iclass 39, count 2 2006.257.15:30:21.67#ibcon#enter sib2, iclass 39, count 2 2006.257.15:30:21.67#ibcon#flushed, iclass 39, count 2 2006.257.15:30:21.67#ibcon#about to write, iclass 39, count 2 2006.257.15:30:21.67#ibcon#wrote, iclass 39, count 2 2006.257.15:30:21.67#ibcon#about to read 3, iclass 39, count 2 2006.257.15:30:21.69#ibcon#read 3, iclass 39, count 2 2006.257.15:30:21.69#ibcon#about to read 4, iclass 39, count 2 2006.257.15:30:21.69#ibcon#read 4, iclass 39, count 2 2006.257.15:30:21.69#ibcon#about to read 5, iclass 39, count 2 2006.257.15:30:21.69#ibcon#read 5, iclass 39, count 2 2006.257.15:30:21.69#ibcon#about to read 6, iclass 39, count 2 2006.257.15:30:21.69#ibcon#read 6, iclass 39, count 2 2006.257.15:30:21.69#ibcon#end of sib2, iclass 39, count 2 2006.257.15:30:21.69#ibcon#*mode == 0, iclass 39, count 2 2006.257.15:30:21.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.15:30:21.69#ibcon#[25=AT05-04\r\n] 2006.257.15:30:21.69#ibcon#*before write, iclass 39, count 2 2006.257.15:30:21.69#ibcon#enter sib2, iclass 39, count 2 2006.257.15:30:21.69#ibcon#flushed, iclass 39, count 2 2006.257.15:30:21.69#ibcon#about to write, iclass 39, count 2 2006.257.15:30:21.69#ibcon#wrote, iclass 39, count 2 2006.257.15:30:21.69#ibcon#about to read 3, iclass 39, count 2 2006.257.15:30:21.72#ibcon#read 3, iclass 39, count 2 2006.257.15:30:21.72#ibcon#about to read 4, iclass 39, count 2 2006.257.15:30:21.72#ibcon#read 4, iclass 39, count 2 2006.257.15:30:21.72#ibcon#about to read 5, iclass 39, count 2 2006.257.15:30:21.72#ibcon#read 5, iclass 39, count 2 2006.257.15:30:21.72#ibcon#about to read 6, iclass 39, count 2 2006.257.15:30:21.72#ibcon#read 6, iclass 39, count 2 2006.257.15:30:21.72#ibcon#end of sib2, iclass 39, count 2 2006.257.15:30:21.72#ibcon#*after write, iclass 39, count 2 2006.257.15:30:21.72#ibcon#*before return 0, iclass 39, count 2 2006.257.15:30:21.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:21.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:21.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.15:30:21.72#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:21.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:21.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:21.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:21.84#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:30:21.84#ibcon#first serial, iclass 39, count 0 2006.257.15:30:21.84#ibcon#enter sib2, iclass 39, count 0 2006.257.15:30:21.84#ibcon#flushed, iclass 39, count 0 2006.257.15:30:21.84#ibcon#about to write, iclass 39, count 0 2006.257.15:30:21.84#ibcon#wrote, iclass 39, count 0 2006.257.15:30:21.84#ibcon#about to read 3, iclass 39, count 0 2006.257.15:30:21.86#ibcon#read 3, iclass 39, count 0 2006.257.15:30:21.86#ibcon#about to read 4, iclass 39, count 0 2006.257.15:30:21.86#ibcon#read 4, iclass 39, count 0 2006.257.15:30:21.86#ibcon#about to read 5, iclass 39, count 0 2006.257.15:30:21.86#ibcon#read 5, iclass 39, count 0 2006.257.15:30:21.86#ibcon#about to read 6, iclass 39, count 0 2006.257.15:30:21.86#ibcon#read 6, iclass 39, count 0 2006.257.15:30:21.86#ibcon#end of sib2, iclass 39, count 0 2006.257.15:30:21.86#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:30:21.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:30:21.86#ibcon#[25=USB\r\n] 2006.257.15:30:21.86#ibcon#*before write, iclass 39, count 0 2006.257.15:30:21.86#ibcon#enter sib2, iclass 39, count 0 2006.257.15:30:21.86#ibcon#flushed, iclass 39, count 0 2006.257.15:30:21.86#ibcon#about to write, iclass 39, count 0 2006.257.15:30:21.86#ibcon#wrote, iclass 39, count 0 2006.257.15:30:21.86#ibcon#about to read 3, iclass 39, count 0 2006.257.15:30:21.89#ibcon#read 3, iclass 39, count 0 2006.257.15:30:21.89#ibcon#about to read 4, iclass 39, count 0 2006.257.15:30:21.89#ibcon#read 4, iclass 39, count 0 2006.257.15:30:21.89#ibcon#about to read 5, iclass 39, count 0 2006.257.15:30:21.89#ibcon#read 5, iclass 39, count 0 2006.257.15:30:21.89#ibcon#about to read 6, iclass 39, count 0 2006.257.15:30:21.89#ibcon#read 6, iclass 39, count 0 2006.257.15:30:21.89#ibcon#end of sib2, iclass 39, count 0 2006.257.15:30:21.89#ibcon#*after write, iclass 39, count 0 2006.257.15:30:21.89#ibcon#*before return 0, iclass 39, count 0 2006.257.15:30:21.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:21.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:21.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:30:21.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:30:21.89$vck44/valo=6,814.99 2006.257.15:30:21.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.15:30:21.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.15:30:21.89#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:21.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:21.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:21.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:21.89#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:30:21.89#ibcon#first serial, iclass 3, count 0 2006.257.15:30:21.89#ibcon#enter sib2, iclass 3, count 0 2006.257.15:30:21.89#ibcon#flushed, iclass 3, count 0 2006.257.15:30:21.89#ibcon#about to write, iclass 3, count 0 2006.257.15:30:21.89#ibcon#wrote, iclass 3, count 0 2006.257.15:30:21.89#ibcon#about to read 3, iclass 3, count 0 2006.257.15:30:21.91#ibcon#read 3, iclass 3, count 0 2006.257.15:30:21.91#ibcon#about to read 4, iclass 3, count 0 2006.257.15:30:21.91#ibcon#read 4, iclass 3, count 0 2006.257.15:30:21.91#ibcon#about to read 5, iclass 3, count 0 2006.257.15:30:21.91#ibcon#read 5, iclass 3, count 0 2006.257.15:30:21.91#ibcon#about to read 6, iclass 3, count 0 2006.257.15:30:21.91#ibcon#read 6, iclass 3, count 0 2006.257.15:30:21.91#ibcon#end of sib2, iclass 3, count 0 2006.257.15:30:21.91#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:30:21.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:30:21.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:30:21.91#ibcon#*before write, iclass 3, count 0 2006.257.15:30:21.91#ibcon#enter sib2, iclass 3, count 0 2006.257.15:30:21.91#ibcon#flushed, iclass 3, count 0 2006.257.15:30:21.91#ibcon#about to write, iclass 3, count 0 2006.257.15:30:21.91#ibcon#wrote, iclass 3, count 0 2006.257.15:30:21.91#ibcon#about to read 3, iclass 3, count 0 2006.257.15:30:21.95#ibcon#read 3, iclass 3, count 0 2006.257.15:30:21.95#ibcon#about to read 4, iclass 3, count 0 2006.257.15:30:21.95#ibcon#read 4, iclass 3, count 0 2006.257.15:30:21.95#ibcon#about to read 5, iclass 3, count 0 2006.257.15:30:21.95#ibcon#read 5, iclass 3, count 0 2006.257.15:30:21.95#ibcon#about to read 6, iclass 3, count 0 2006.257.15:30:21.95#ibcon#read 6, iclass 3, count 0 2006.257.15:30:21.95#ibcon#end of sib2, iclass 3, count 0 2006.257.15:30:21.95#ibcon#*after write, iclass 3, count 0 2006.257.15:30:21.95#ibcon#*before return 0, iclass 3, count 0 2006.257.15:30:21.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:21.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:21.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:30:21.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:30:21.95$vck44/va=6,4 2006.257.15:30:21.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.15:30:21.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.15:30:21.95#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:21.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:22.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:22.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:22.01#ibcon#enter wrdev, iclass 5, count 2 2006.257.15:30:22.01#ibcon#first serial, iclass 5, count 2 2006.257.15:30:22.01#ibcon#enter sib2, iclass 5, count 2 2006.257.15:30:22.01#ibcon#flushed, iclass 5, count 2 2006.257.15:30:22.01#ibcon#about to write, iclass 5, count 2 2006.257.15:30:22.01#ibcon#wrote, iclass 5, count 2 2006.257.15:30:22.01#ibcon#about to read 3, iclass 5, count 2 2006.257.15:30:22.03#ibcon#read 3, iclass 5, count 2 2006.257.15:30:22.03#ibcon#about to read 4, iclass 5, count 2 2006.257.15:30:22.03#ibcon#read 4, iclass 5, count 2 2006.257.15:30:22.03#ibcon#about to read 5, iclass 5, count 2 2006.257.15:30:22.03#ibcon#read 5, iclass 5, count 2 2006.257.15:30:22.03#ibcon#about to read 6, iclass 5, count 2 2006.257.15:30:22.03#ibcon#read 6, iclass 5, count 2 2006.257.15:30:22.03#ibcon#end of sib2, iclass 5, count 2 2006.257.15:30:22.03#ibcon#*mode == 0, iclass 5, count 2 2006.257.15:30:22.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.15:30:22.03#ibcon#[25=AT06-04\r\n] 2006.257.15:30:22.03#ibcon#*before write, iclass 5, count 2 2006.257.15:30:22.03#ibcon#enter sib2, iclass 5, count 2 2006.257.15:30:22.03#ibcon#flushed, iclass 5, count 2 2006.257.15:30:22.03#ibcon#about to write, iclass 5, count 2 2006.257.15:30:22.03#ibcon#wrote, iclass 5, count 2 2006.257.15:30:22.03#ibcon#about to read 3, iclass 5, count 2 2006.257.15:30:22.06#ibcon#read 3, iclass 5, count 2 2006.257.15:30:22.06#ibcon#about to read 4, iclass 5, count 2 2006.257.15:30:22.06#ibcon#read 4, iclass 5, count 2 2006.257.15:30:22.06#ibcon#about to read 5, iclass 5, count 2 2006.257.15:30:22.06#ibcon#read 5, iclass 5, count 2 2006.257.15:30:22.06#ibcon#about to read 6, iclass 5, count 2 2006.257.15:30:22.06#ibcon#read 6, iclass 5, count 2 2006.257.15:30:22.06#ibcon#end of sib2, iclass 5, count 2 2006.257.15:30:22.06#ibcon#*after write, iclass 5, count 2 2006.257.15:30:22.06#ibcon#*before return 0, iclass 5, count 2 2006.257.15:30:22.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:22.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:22.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.15:30:22.06#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:22.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:22.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:22.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:22.18#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:30:22.18#ibcon#first serial, iclass 5, count 0 2006.257.15:30:22.18#ibcon#enter sib2, iclass 5, count 0 2006.257.15:30:22.18#ibcon#flushed, iclass 5, count 0 2006.257.15:30:22.18#ibcon#about to write, iclass 5, count 0 2006.257.15:30:22.18#ibcon#wrote, iclass 5, count 0 2006.257.15:30:22.18#ibcon#about to read 3, iclass 5, count 0 2006.257.15:30:22.20#ibcon#read 3, iclass 5, count 0 2006.257.15:30:22.20#ibcon#about to read 4, iclass 5, count 0 2006.257.15:30:22.20#ibcon#read 4, iclass 5, count 0 2006.257.15:30:22.20#ibcon#about to read 5, iclass 5, count 0 2006.257.15:30:22.20#ibcon#read 5, iclass 5, count 0 2006.257.15:30:22.20#ibcon#about to read 6, iclass 5, count 0 2006.257.15:30:22.20#ibcon#read 6, iclass 5, count 0 2006.257.15:30:22.20#ibcon#end of sib2, iclass 5, count 0 2006.257.15:30:22.20#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:30:22.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:30:22.20#ibcon#[25=USB\r\n] 2006.257.15:30:22.20#ibcon#*before write, iclass 5, count 0 2006.257.15:30:22.20#ibcon#enter sib2, iclass 5, count 0 2006.257.15:30:22.20#ibcon#flushed, iclass 5, count 0 2006.257.15:30:22.20#ibcon#about to write, iclass 5, count 0 2006.257.15:30:22.20#ibcon#wrote, iclass 5, count 0 2006.257.15:30:22.20#ibcon#about to read 3, iclass 5, count 0 2006.257.15:30:22.23#ibcon#read 3, iclass 5, count 0 2006.257.15:30:22.23#ibcon#about to read 4, iclass 5, count 0 2006.257.15:30:22.23#ibcon#read 4, iclass 5, count 0 2006.257.15:30:22.23#ibcon#about to read 5, iclass 5, count 0 2006.257.15:30:22.23#ibcon#read 5, iclass 5, count 0 2006.257.15:30:22.23#ibcon#about to read 6, iclass 5, count 0 2006.257.15:30:22.23#ibcon#read 6, iclass 5, count 0 2006.257.15:30:22.23#ibcon#end of sib2, iclass 5, count 0 2006.257.15:30:22.23#ibcon#*after write, iclass 5, count 0 2006.257.15:30:22.23#ibcon#*before return 0, iclass 5, count 0 2006.257.15:30:22.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:22.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:22.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:30:22.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:30:22.23$vck44/valo=7,864.99 2006.257.15:30:22.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.15:30:22.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.15:30:22.23#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:22.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:22.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:22.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:22.23#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:30:22.23#ibcon#first serial, iclass 7, count 0 2006.257.15:30:22.23#ibcon#enter sib2, iclass 7, count 0 2006.257.15:30:22.23#ibcon#flushed, iclass 7, count 0 2006.257.15:30:22.23#ibcon#about to write, iclass 7, count 0 2006.257.15:30:22.23#ibcon#wrote, iclass 7, count 0 2006.257.15:30:22.23#ibcon#about to read 3, iclass 7, count 0 2006.257.15:30:22.25#ibcon#read 3, iclass 7, count 0 2006.257.15:30:22.25#ibcon#about to read 4, iclass 7, count 0 2006.257.15:30:22.25#ibcon#read 4, iclass 7, count 0 2006.257.15:30:22.25#ibcon#about to read 5, iclass 7, count 0 2006.257.15:30:22.25#ibcon#read 5, iclass 7, count 0 2006.257.15:30:22.25#ibcon#about to read 6, iclass 7, count 0 2006.257.15:30:22.25#ibcon#read 6, iclass 7, count 0 2006.257.15:30:22.25#ibcon#end of sib2, iclass 7, count 0 2006.257.15:30:22.25#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:30:22.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:30:22.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:30:22.25#ibcon#*before write, iclass 7, count 0 2006.257.15:30:22.25#ibcon#enter sib2, iclass 7, count 0 2006.257.15:30:22.25#ibcon#flushed, iclass 7, count 0 2006.257.15:30:22.25#ibcon#about to write, iclass 7, count 0 2006.257.15:30:22.25#ibcon#wrote, iclass 7, count 0 2006.257.15:30:22.25#ibcon#about to read 3, iclass 7, count 0 2006.257.15:30:22.29#ibcon#read 3, iclass 7, count 0 2006.257.15:30:22.29#ibcon#about to read 4, iclass 7, count 0 2006.257.15:30:22.29#ibcon#read 4, iclass 7, count 0 2006.257.15:30:22.29#ibcon#about to read 5, iclass 7, count 0 2006.257.15:30:22.29#ibcon#read 5, iclass 7, count 0 2006.257.15:30:22.29#ibcon#about to read 6, iclass 7, count 0 2006.257.15:30:22.29#ibcon#read 6, iclass 7, count 0 2006.257.15:30:22.29#ibcon#end of sib2, iclass 7, count 0 2006.257.15:30:22.29#ibcon#*after write, iclass 7, count 0 2006.257.15:30:22.29#ibcon#*before return 0, iclass 7, count 0 2006.257.15:30:22.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:22.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:22.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:30:22.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:30:22.29$vck44/va=7,4 2006.257.15:30:22.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.15:30:22.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.15:30:22.29#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:22.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:22.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:22.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:22.35#ibcon#enter wrdev, iclass 11, count 2 2006.257.15:30:22.35#ibcon#first serial, iclass 11, count 2 2006.257.15:30:22.35#ibcon#enter sib2, iclass 11, count 2 2006.257.15:30:22.35#ibcon#flushed, iclass 11, count 2 2006.257.15:30:22.35#ibcon#about to write, iclass 11, count 2 2006.257.15:30:22.35#ibcon#wrote, iclass 11, count 2 2006.257.15:30:22.35#ibcon#about to read 3, iclass 11, count 2 2006.257.15:30:22.37#ibcon#read 3, iclass 11, count 2 2006.257.15:30:22.37#ibcon#about to read 4, iclass 11, count 2 2006.257.15:30:22.37#ibcon#read 4, iclass 11, count 2 2006.257.15:30:22.37#ibcon#about to read 5, iclass 11, count 2 2006.257.15:30:22.37#ibcon#read 5, iclass 11, count 2 2006.257.15:30:22.37#ibcon#about to read 6, iclass 11, count 2 2006.257.15:30:22.37#ibcon#read 6, iclass 11, count 2 2006.257.15:30:22.37#ibcon#end of sib2, iclass 11, count 2 2006.257.15:30:22.37#ibcon#*mode == 0, iclass 11, count 2 2006.257.15:30:22.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.15:30:22.37#ibcon#[25=AT07-04\r\n] 2006.257.15:30:22.37#ibcon#*before write, iclass 11, count 2 2006.257.15:30:22.37#ibcon#enter sib2, iclass 11, count 2 2006.257.15:30:22.37#ibcon#flushed, iclass 11, count 2 2006.257.15:30:22.37#ibcon#about to write, iclass 11, count 2 2006.257.15:30:22.37#ibcon#wrote, iclass 11, count 2 2006.257.15:30:22.37#ibcon#about to read 3, iclass 11, count 2 2006.257.15:30:22.40#ibcon#read 3, iclass 11, count 2 2006.257.15:30:22.40#ibcon#about to read 4, iclass 11, count 2 2006.257.15:30:22.40#ibcon#read 4, iclass 11, count 2 2006.257.15:30:22.40#ibcon#about to read 5, iclass 11, count 2 2006.257.15:30:22.40#ibcon#read 5, iclass 11, count 2 2006.257.15:30:22.40#ibcon#about to read 6, iclass 11, count 2 2006.257.15:30:22.40#ibcon#read 6, iclass 11, count 2 2006.257.15:30:22.40#ibcon#end of sib2, iclass 11, count 2 2006.257.15:30:22.40#ibcon#*after write, iclass 11, count 2 2006.257.15:30:22.40#ibcon#*before return 0, iclass 11, count 2 2006.257.15:30:22.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:22.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:22.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.15:30:22.40#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:22.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:22.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:22.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:22.52#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:30:22.52#ibcon#first serial, iclass 11, count 0 2006.257.15:30:22.52#ibcon#enter sib2, iclass 11, count 0 2006.257.15:30:22.52#ibcon#flushed, iclass 11, count 0 2006.257.15:30:22.52#ibcon#about to write, iclass 11, count 0 2006.257.15:30:22.52#ibcon#wrote, iclass 11, count 0 2006.257.15:30:22.52#ibcon#about to read 3, iclass 11, count 0 2006.257.15:30:22.54#ibcon#read 3, iclass 11, count 0 2006.257.15:30:22.54#ibcon#about to read 4, iclass 11, count 0 2006.257.15:30:22.54#ibcon#read 4, iclass 11, count 0 2006.257.15:30:22.54#ibcon#about to read 5, iclass 11, count 0 2006.257.15:30:22.54#ibcon#read 5, iclass 11, count 0 2006.257.15:30:22.54#ibcon#about to read 6, iclass 11, count 0 2006.257.15:30:22.54#ibcon#read 6, iclass 11, count 0 2006.257.15:30:22.54#ibcon#end of sib2, iclass 11, count 0 2006.257.15:30:22.54#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:30:22.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:30:22.54#ibcon#[25=USB\r\n] 2006.257.15:30:22.54#ibcon#*before write, iclass 11, count 0 2006.257.15:30:22.54#ibcon#enter sib2, iclass 11, count 0 2006.257.15:30:22.54#ibcon#flushed, iclass 11, count 0 2006.257.15:30:22.54#ibcon#about to write, iclass 11, count 0 2006.257.15:30:22.54#ibcon#wrote, iclass 11, count 0 2006.257.15:30:22.54#ibcon#about to read 3, iclass 11, count 0 2006.257.15:30:22.57#ibcon#read 3, iclass 11, count 0 2006.257.15:30:22.57#ibcon#about to read 4, iclass 11, count 0 2006.257.15:30:22.57#ibcon#read 4, iclass 11, count 0 2006.257.15:30:22.57#ibcon#about to read 5, iclass 11, count 0 2006.257.15:30:22.57#ibcon#read 5, iclass 11, count 0 2006.257.15:30:22.57#ibcon#about to read 6, iclass 11, count 0 2006.257.15:30:22.57#ibcon#read 6, iclass 11, count 0 2006.257.15:30:22.57#ibcon#end of sib2, iclass 11, count 0 2006.257.15:30:22.57#ibcon#*after write, iclass 11, count 0 2006.257.15:30:22.57#ibcon#*before return 0, iclass 11, count 0 2006.257.15:30:22.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:22.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:22.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:30:22.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:30:22.57$vck44/valo=8,884.99 2006.257.15:30:22.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.15:30:22.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.15:30:22.57#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:22.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:22.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:22.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:22.57#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:30:22.57#ibcon#first serial, iclass 13, count 0 2006.257.15:30:22.57#ibcon#enter sib2, iclass 13, count 0 2006.257.15:30:22.57#ibcon#flushed, iclass 13, count 0 2006.257.15:30:22.57#ibcon#about to write, iclass 13, count 0 2006.257.15:30:22.57#ibcon#wrote, iclass 13, count 0 2006.257.15:30:22.57#ibcon#about to read 3, iclass 13, count 0 2006.257.15:30:22.59#ibcon#read 3, iclass 13, count 0 2006.257.15:30:22.59#ibcon#about to read 4, iclass 13, count 0 2006.257.15:30:22.59#ibcon#read 4, iclass 13, count 0 2006.257.15:30:22.59#ibcon#about to read 5, iclass 13, count 0 2006.257.15:30:22.59#ibcon#read 5, iclass 13, count 0 2006.257.15:30:22.59#ibcon#about to read 6, iclass 13, count 0 2006.257.15:30:22.59#ibcon#read 6, iclass 13, count 0 2006.257.15:30:22.59#ibcon#end of sib2, iclass 13, count 0 2006.257.15:30:22.59#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:30:22.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:30:22.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:30:22.59#ibcon#*before write, iclass 13, count 0 2006.257.15:30:22.59#ibcon#enter sib2, iclass 13, count 0 2006.257.15:30:22.59#ibcon#flushed, iclass 13, count 0 2006.257.15:30:22.59#ibcon#about to write, iclass 13, count 0 2006.257.15:30:22.59#ibcon#wrote, iclass 13, count 0 2006.257.15:30:22.59#ibcon#about to read 3, iclass 13, count 0 2006.257.15:30:22.63#ibcon#read 3, iclass 13, count 0 2006.257.15:30:22.63#ibcon#about to read 4, iclass 13, count 0 2006.257.15:30:22.63#ibcon#read 4, iclass 13, count 0 2006.257.15:30:22.63#ibcon#about to read 5, iclass 13, count 0 2006.257.15:30:22.63#ibcon#read 5, iclass 13, count 0 2006.257.15:30:22.63#ibcon#about to read 6, iclass 13, count 0 2006.257.15:30:22.63#ibcon#read 6, iclass 13, count 0 2006.257.15:30:22.63#ibcon#end of sib2, iclass 13, count 0 2006.257.15:30:22.63#ibcon#*after write, iclass 13, count 0 2006.257.15:30:22.63#ibcon#*before return 0, iclass 13, count 0 2006.257.15:30:22.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:22.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:22.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:30:22.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:30:22.63$vck44/va=8,4 2006.257.15:30:22.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.15:30:22.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.15:30:22.63#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:22.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:22.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:22.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:22.69#ibcon#enter wrdev, iclass 15, count 2 2006.257.15:30:22.69#ibcon#first serial, iclass 15, count 2 2006.257.15:30:22.69#ibcon#enter sib2, iclass 15, count 2 2006.257.15:30:22.69#ibcon#flushed, iclass 15, count 2 2006.257.15:30:22.69#ibcon#about to write, iclass 15, count 2 2006.257.15:30:22.69#ibcon#wrote, iclass 15, count 2 2006.257.15:30:22.69#ibcon#about to read 3, iclass 15, count 2 2006.257.15:30:22.71#ibcon#read 3, iclass 15, count 2 2006.257.15:30:22.71#ibcon#about to read 4, iclass 15, count 2 2006.257.15:30:22.71#ibcon#read 4, iclass 15, count 2 2006.257.15:30:22.71#ibcon#about to read 5, iclass 15, count 2 2006.257.15:30:22.71#ibcon#read 5, iclass 15, count 2 2006.257.15:30:22.71#ibcon#about to read 6, iclass 15, count 2 2006.257.15:30:22.71#ibcon#read 6, iclass 15, count 2 2006.257.15:30:22.71#ibcon#end of sib2, iclass 15, count 2 2006.257.15:30:22.71#ibcon#*mode == 0, iclass 15, count 2 2006.257.15:30:22.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.15:30:22.71#ibcon#[25=AT08-04\r\n] 2006.257.15:30:22.71#ibcon#*before write, iclass 15, count 2 2006.257.15:30:22.71#ibcon#enter sib2, iclass 15, count 2 2006.257.15:30:22.71#ibcon#flushed, iclass 15, count 2 2006.257.15:30:22.71#ibcon#about to write, iclass 15, count 2 2006.257.15:30:22.71#ibcon#wrote, iclass 15, count 2 2006.257.15:30:22.71#ibcon#about to read 3, iclass 15, count 2 2006.257.15:30:22.74#ibcon#read 3, iclass 15, count 2 2006.257.15:30:22.74#ibcon#about to read 4, iclass 15, count 2 2006.257.15:30:22.74#ibcon#read 4, iclass 15, count 2 2006.257.15:30:22.74#ibcon#about to read 5, iclass 15, count 2 2006.257.15:30:22.74#ibcon#read 5, iclass 15, count 2 2006.257.15:30:22.74#ibcon#about to read 6, iclass 15, count 2 2006.257.15:30:22.74#ibcon#read 6, iclass 15, count 2 2006.257.15:30:22.74#ibcon#end of sib2, iclass 15, count 2 2006.257.15:30:22.74#ibcon#*after write, iclass 15, count 2 2006.257.15:30:22.74#ibcon#*before return 0, iclass 15, count 2 2006.257.15:30:22.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:22.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:22.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.15:30:22.74#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:22.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:22.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:22.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:22.86#ibcon#enter wrdev, iclass 15, count 0 2006.257.15:30:22.86#ibcon#first serial, iclass 15, count 0 2006.257.15:30:22.86#ibcon#enter sib2, iclass 15, count 0 2006.257.15:30:22.86#ibcon#flushed, iclass 15, count 0 2006.257.15:30:22.86#ibcon#about to write, iclass 15, count 0 2006.257.15:30:22.86#ibcon#wrote, iclass 15, count 0 2006.257.15:30:22.86#ibcon#about to read 3, iclass 15, count 0 2006.257.15:30:22.88#ibcon#read 3, iclass 15, count 0 2006.257.15:30:22.88#ibcon#about to read 4, iclass 15, count 0 2006.257.15:30:22.88#ibcon#read 4, iclass 15, count 0 2006.257.15:30:22.88#ibcon#about to read 5, iclass 15, count 0 2006.257.15:30:22.88#ibcon#read 5, iclass 15, count 0 2006.257.15:30:22.88#ibcon#about to read 6, iclass 15, count 0 2006.257.15:30:22.88#ibcon#read 6, iclass 15, count 0 2006.257.15:30:22.88#ibcon#end of sib2, iclass 15, count 0 2006.257.15:30:22.88#ibcon#*mode == 0, iclass 15, count 0 2006.257.15:30:22.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.15:30:22.88#ibcon#[25=USB\r\n] 2006.257.15:30:22.88#ibcon#*before write, iclass 15, count 0 2006.257.15:30:22.88#ibcon#enter sib2, iclass 15, count 0 2006.257.15:30:22.88#ibcon#flushed, iclass 15, count 0 2006.257.15:30:22.88#ibcon#about to write, iclass 15, count 0 2006.257.15:30:22.88#ibcon#wrote, iclass 15, count 0 2006.257.15:30:22.88#ibcon#about to read 3, iclass 15, count 0 2006.257.15:30:22.91#ibcon#read 3, iclass 15, count 0 2006.257.15:30:22.91#ibcon#about to read 4, iclass 15, count 0 2006.257.15:30:22.91#ibcon#read 4, iclass 15, count 0 2006.257.15:30:22.91#ibcon#about to read 5, iclass 15, count 0 2006.257.15:30:22.91#ibcon#read 5, iclass 15, count 0 2006.257.15:30:22.91#ibcon#about to read 6, iclass 15, count 0 2006.257.15:30:22.91#ibcon#read 6, iclass 15, count 0 2006.257.15:30:22.91#ibcon#end of sib2, iclass 15, count 0 2006.257.15:30:22.91#ibcon#*after write, iclass 15, count 0 2006.257.15:30:22.91#ibcon#*before return 0, iclass 15, count 0 2006.257.15:30:22.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:22.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:22.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.15:30:22.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.15:30:22.91$vck44/vblo=1,629.99 2006.257.15:30:22.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.15:30:22.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.15:30:22.91#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:22.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:22.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:22.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:22.91#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:30:22.91#ibcon#first serial, iclass 17, count 0 2006.257.15:30:22.91#ibcon#enter sib2, iclass 17, count 0 2006.257.15:30:22.91#ibcon#flushed, iclass 17, count 0 2006.257.15:30:22.91#ibcon#about to write, iclass 17, count 0 2006.257.15:30:22.91#ibcon#wrote, iclass 17, count 0 2006.257.15:30:22.91#ibcon#about to read 3, iclass 17, count 0 2006.257.15:30:22.93#ibcon#read 3, iclass 17, count 0 2006.257.15:30:22.93#ibcon#about to read 4, iclass 17, count 0 2006.257.15:30:22.93#ibcon#read 4, iclass 17, count 0 2006.257.15:30:22.93#ibcon#about to read 5, iclass 17, count 0 2006.257.15:30:22.93#ibcon#read 5, iclass 17, count 0 2006.257.15:30:22.93#ibcon#about to read 6, iclass 17, count 0 2006.257.15:30:22.93#ibcon#read 6, iclass 17, count 0 2006.257.15:30:22.93#ibcon#end of sib2, iclass 17, count 0 2006.257.15:30:22.93#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:30:22.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:30:22.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:30:22.93#ibcon#*before write, iclass 17, count 0 2006.257.15:30:22.93#ibcon#enter sib2, iclass 17, count 0 2006.257.15:30:22.93#ibcon#flushed, iclass 17, count 0 2006.257.15:30:22.93#ibcon#about to write, iclass 17, count 0 2006.257.15:30:22.93#ibcon#wrote, iclass 17, count 0 2006.257.15:30:22.93#ibcon#about to read 3, iclass 17, count 0 2006.257.15:30:22.97#ibcon#read 3, iclass 17, count 0 2006.257.15:30:22.97#ibcon#about to read 4, iclass 17, count 0 2006.257.15:30:22.97#ibcon#read 4, iclass 17, count 0 2006.257.15:30:22.97#ibcon#about to read 5, iclass 17, count 0 2006.257.15:30:22.97#ibcon#read 5, iclass 17, count 0 2006.257.15:30:22.97#ibcon#about to read 6, iclass 17, count 0 2006.257.15:30:22.97#ibcon#read 6, iclass 17, count 0 2006.257.15:30:22.97#ibcon#end of sib2, iclass 17, count 0 2006.257.15:30:22.97#ibcon#*after write, iclass 17, count 0 2006.257.15:30:22.97#ibcon#*before return 0, iclass 17, count 0 2006.257.15:30:22.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:22.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:22.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:30:22.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:30:22.97$vck44/vb=1,4 2006.257.15:30:22.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.15:30:22.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.15:30:22.97#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:22.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:30:22.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:30:22.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:30:22.97#ibcon#enter wrdev, iclass 19, count 2 2006.257.15:30:22.97#ibcon#first serial, iclass 19, count 2 2006.257.15:30:22.97#ibcon#enter sib2, iclass 19, count 2 2006.257.15:30:22.97#ibcon#flushed, iclass 19, count 2 2006.257.15:30:22.97#ibcon#about to write, iclass 19, count 2 2006.257.15:30:22.97#ibcon#wrote, iclass 19, count 2 2006.257.15:30:22.97#ibcon#about to read 3, iclass 19, count 2 2006.257.15:30:22.99#ibcon#read 3, iclass 19, count 2 2006.257.15:30:22.99#ibcon#about to read 4, iclass 19, count 2 2006.257.15:30:22.99#ibcon#read 4, iclass 19, count 2 2006.257.15:30:22.99#ibcon#about to read 5, iclass 19, count 2 2006.257.15:30:22.99#ibcon#read 5, iclass 19, count 2 2006.257.15:30:22.99#ibcon#about to read 6, iclass 19, count 2 2006.257.15:30:22.99#ibcon#read 6, iclass 19, count 2 2006.257.15:30:22.99#ibcon#end of sib2, iclass 19, count 2 2006.257.15:30:22.99#ibcon#*mode == 0, iclass 19, count 2 2006.257.15:30:22.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.15:30:22.99#ibcon#[27=AT01-04\r\n] 2006.257.15:30:22.99#ibcon#*before write, iclass 19, count 2 2006.257.15:30:22.99#ibcon#enter sib2, iclass 19, count 2 2006.257.15:30:22.99#ibcon#flushed, iclass 19, count 2 2006.257.15:30:22.99#ibcon#about to write, iclass 19, count 2 2006.257.15:30:22.99#ibcon#wrote, iclass 19, count 2 2006.257.15:30:22.99#ibcon#about to read 3, iclass 19, count 2 2006.257.15:30:23.02#ibcon#read 3, iclass 19, count 2 2006.257.15:30:23.02#ibcon#about to read 4, iclass 19, count 2 2006.257.15:30:23.02#ibcon#read 4, iclass 19, count 2 2006.257.15:30:23.02#ibcon#about to read 5, iclass 19, count 2 2006.257.15:30:23.02#ibcon#read 5, iclass 19, count 2 2006.257.15:30:23.02#ibcon#about to read 6, iclass 19, count 2 2006.257.15:30:23.02#ibcon#read 6, iclass 19, count 2 2006.257.15:30:23.02#ibcon#end of sib2, iclass 19, count 2 2006.257.15:30:23.02#ibcon#*after write, iclass 19, count 2 2006.257.15:30:23.02#ibcon#*before return 0, iclass 19, count 2 2006.257.15:30:23.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:30:23.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:30:23.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.15:30:23.02#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:23.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:30:23.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:30:23.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:30:23.14#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:30:23.14#ibcon#first serial, iclass 19, count 0 2006.257.15:30:23.14#ibcon#enter sib2, iclass 19, count 0 2006.257.15:30:23.14#ibcon#flushed, iclass 19, count 0 2006.257.15:30:23.14#ibcon#about to write, iclass 19, count 0 2006.257.15:30:23.14#ibcon#wrote, iclass 19, count 0 2006.257.15:30:23.14#ibcon#about to read 3, iclass 19, count 0 2006.257.15:30:23.16#ibcon#read 3, iclass 19, count 0 2006.257.15:30:23.16#ibcon#about to read 4, iclass 19, count 0 2006.257.15:30:23.16#ibcon#read 4, iclass 19, count 0 2006.257.15:30:23.16#ibcon#about to read 5, iclass 19, count 0 2006.257.15:30:23.16#ibcon#read 5, iclass 19, count 0 2006.257.15:30:23.16#ibcon#about to read 6, iclass 19, count 0 2006.257.15:30:23.16#ibcon#read 6, iclass 19, count 0 2006.257.15:30:23.16#ibcon#end of sib2, iclass 19, count 0 2006.257.15:30:23.16#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:30:23.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:30:23.16#ibcon#[27=USB\r\n] 2006.257.15:30:23.16#ibcon#*before write, iclass 19, count 0 2006.257.15:30:23.16#ibcon#enter sib2, iclass 19, count 0 2006.257.15:30:23.16#ibcon#flushed, iclass 19, count 0 2006.257.15:30:23.16#ibcon#about to write, iclass 19, count 0 2006.257.15:30:23.16#ibcon#wrote, iclass 19, count 0 2006.257.15:30:23.16#ibcon#about to read 3, iclass 19, count 0 2006.257.15:30:23.19#ibcon#read 3, iclass 19, count 0 2006.257.15:30:23.19#ibcon#about to read 4, iclass 19, count 0 2006.257.15:30:23.19#ibcon#read 4, iclass 19, count 0 2006.257.15:30:23.19#ibcon#about to read 5, iclass 19, count 0 2006.257.15:30:23.19#ibcon#read 5, iclass 19, count 0 2006.257.15:30:23.19#ibcon#about to read 6, iclass 19, count 0 2006.257.15:30:23.19#ibcon#read 6, iclass 19, count 0 2006.257.15:30:23.19#ibcon#end of sib2, iclass 19, count 0 2006.257.15:30:23.19#ibcon#*after write, iclass 19, count 0 2006.257.15:30:23.19#ibcon#*before return 0, iclass 19, count 0 2006.257.15:30:23.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:30:23.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:30:23.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:30:23.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:30:23.19$vck44/vblo=2,634.99 2006.257.15:30:23.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.15:30:23.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.15:30:23.19#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:23.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:23.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:23.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:23.19#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:30:23.19#ibcon#first serial, iclass 21, count 0 2006.257.15:30:23.19#ibcon#enter sib2, iclass 21, count 0 2006.257.15:30:23.19#ibcon#flushed, iclass 21, count 0 2006.257.15:30:23.19#ibcon#about to write, iclass 21, count 0 2006.257.15:30:23.19#ibcon#wrote, iclass 21, count 0 2006.257.15:30:23.19#ibcon#about to read 3, iclass 21, count 0 2006.257.15:30:23.21#ibcon#read 3, iclass 21, count 0 2006.257.15:30:23.21#ibcon#about to read 4, iclass 21, count 0 2006.257.15:30:23.21#ibcon#read 4, iclass 21, count 0 2006.257.15:30:23.21#ibcon#about to read 5, iclass 21, count 0 2006.257.15:30:23.21#ibcon#read 5, iclass 21, count 0 2006.257.15:30:23.21#ibcon#about to read 6, iclass 21, count 0 2006.257.15:30:23.21#ibcon#read 6, iclass 21, count 0 2006.257.15:30:23.21#ibcon#end of sib2, iclass 21, count 0 2006.257.15:30:23.21#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:30:23.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:30:23.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:30:23.21#ibcon#*before write, iclass 21, count 0 2006.257.15:30:23.21#ibcon#enter sib2, iclass 21, count 0 2006.257.15:30:23.21#ibcon#flushed, iclass 21, count 0 2006.257.15:30:23.21#ibcon#about to write, iclass 21, count 0 2006.257.15:30:23.21#ibcon#wrote, iclass 21, count 0 2006.257.15:30:23.21#ibcon#about to read 3, iclass 21, count 0 2006.257.15:30:23.25#ibcon#read 3, iclass 21, count 0 2006.257.15:30:23.25#ibcon#about to read 4, iclass 21, count 0 2006.257.15:30:23.25#ibcon#read 4, iclass 21, count 0 2006.257.15:30:23.25#ibcon#about to read 5, iclass 21, count 0 2006.257.15:30:23.25#ibcon#read 5, iclass 21, count 0 2006.257.15:30:23.25#ibcon#about to read 6, iclass 21, count 0 2006.257.15:30:23.25#ibcon#read 6, iclass 21, count 0 2006.257.15:30:23.25#ibcon#end of sib2, iclass 21, count 0 2006.257.15:30:23.25#ibcon#*after write, iclass 21, count 0 2006.257.15:30:23.25#ibcon#*before return 0, iclass 21, count 0 2006.257.15:30:23.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:23.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:30:23.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:30:23.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:30:23.25$vck44/vb=2,5 2006.257.15:30:23.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.15:30:23.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.15:30:23.25#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:23.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:23.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:23.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:23.31#ibcon#enter wrdev, iclass 23, count 2 2006.257.15:30:23.31#ibcon#first serial, iclass 23, count 2 2006.257.15:30:23.31#ibcon#enter sib2, iclass 23, count 2 2006.257.15:30:23.31#ibcon#flushed, iclass 23, count 2 2006.257.15:30:23.31#ibcon#about to write, iclass 23, count 2 2006.257.15:30:23.31#ibcon#wrote, iclass 23, count 2 2006.257.15:30:23.31#ibcon#about to read 3, iclass 23, count 2 2006.257.15:30:23.33#ibcon#read 3, iclass 23, count 2 2006.257.15:30:23.33#ibcon#about to read 4, iclass 23, count 2 2006.257.15:30:23.33#ibcon#read 4, iclass 23, count 2 2006.257.15:30:23.33#ibcon#about to read 5, iclass 23, count 2 2006.257.15:30:23.33#ibcon#read 5, iclass 23, count 2 2006.257.15:30:23.33#ibcon#about to read 6, iclass 23, count 2 2006.257.15:30:23.33#ibcon#read 6, iclass 23, count 2 2006.257.15:30:23.33#ibcon#end of sib2, iclass 23, count 2 2006.257.15:30:23.33#ibcon#*mode == 0, iclass 23, count 2 2006.257.15:30:23.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.15:30:23.33#ibcon#[27=AT02-05\r\n] 2006.257.15:30:23.33#ibcon#*before write, iclass 23, count 2 2006.257.15:30:23.33#ibcon#enter sib2, iclass 23, count 2 2006.257.15:30:23.33#ibcon#flushed, iclass 23, count 2 2006.257.15:30:23.33#ibcon#about to write, iclass 23, count 2 2006.257.15:30:23.33#ibcon#wrote, iclass 23, count 2 2006.257.15:30:23.33#ibcon#about to read 3, iclass 23, count 2 2006.257.15:30:23.36#ibcon#read 3, iclass 23, count 2 2006.257.15:30:23.36#ibcon#about to read 4, iclass 23, count 2 2006.257.15:30:23.36#ibcon#read 4, iclass 23, count 2 2006.257.15:30:23.36#ibcon#about to read 5, iclass 23, count 2 2006.257.15:30:23.36#ibcon#read 5, iclass 23, count 2 2006.257.15:30:23.36#ibcon#about to read 6, iclass 23, count 2 2006.257.15:30:23.36#ibcon#read 6, iclass 23, count 2 2006.257.15:30:23.36#ibcon#end of sib2, iclass 23, count 2 2006.257.15:30:23.36#ibcon#*after write, iclass 23, count 2 2006.257.15:30:23.36#ibcon#*before return 0, iclass 23, count 2 2006.257.15:30:23.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:23.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:30:23.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.15:30:23.36#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:23.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:23.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:23.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:23.48#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:30:23.48#ibcon#first serial, iclass 23, count 0 2006.257.15:30:23.48#ibcon#enter sib2, iclass 23, count 0 2006.257.15:30:23.48#ibcon#flushed, iclass 23, count 0 2006.257.15:30:23.48#ibcon#about to write, iclass 23, count 0 2006.257.15:30:23.48#ibcon#wrote, iclass 23, count 0 2006.257.15:30:23.48#ibcon#about to read 3, iclass 23, count 0 2006.257.15:30:23.50#ibcon#read 3, iclass 23, count 0 2006.257.15:30:23.50#ibcon#about to read 4, iclass 23, count 0 2006.257.15:30:23.50#ibcon#read 4, iclass 23, count 0 2006.257.15:30:23.50#ibcon#about to read 5, iclass 23, count 0 2006.257.15:30:23.50#ibcon#read 5, iclass 23, count 0 2006.257.15:30:23.50#ibcon#about to read 6, iclass 23, count 0 2006.257.15:30:23.50#ibcon#read 6, iclass 23, count 0 2006.257.15:30:23.50#ibcon#end of sib2, iclass 23, count 0 2006.257.15:30:23.50#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:30:23.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:30:23.50#ibcon#[27=USB\r\n] 2006.257.15:30:23.50#ibcon#*before write, iclass 23, count 0 2006.257.15:30:23.50#ibcon#enter sib2, iclass 23, count 0 2006.257.15:30:23.50#ibcon#flushed, iclass 23, count 0 2006.257.15:30:23.50#ibcon#about to write, iclass 23, count 0 2006.257.15:30:23.50#ibcon#wrote, iclass 23, count 0 2006.257.15:30:23.50#ibcon#about to read 3, iclass 23, count 0 2006.257.15:30:23.53#ibcon#read 3, iclass 23, count 0 2006.257.15:30:23.53#ibcon#about to read 4, iclass 23, count 0 2006.257.15:30:23.53#ibcon#read 4, iclass 23, count 0 2006.257.15:30:23.53#ibcon#about to read 5, iclass 23, count 0 2006.257.15:30:23.53#ibcon#read 5, iclass 23, count 0 2006.257.15:30:23.53#ibcon#about to read 6, iclass 23, count 0 2006.257.15:30:23.53#ibcon#read 6, iclass 23, count 0 2006.257.15:30:23.53#ibcon#end of sib2, iclass 23, count 0 2006.257.15:30:23.53#ibcon#*after write, iclass 23, count 0 2006.257.15:30:23.53#ibcon#*before return 0, iclass 23, count 0 2006.257.15:30:23.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:23.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:30:23.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:30:23.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:30:23.53$vck44/vblo=3,649.99 2006.257.15:30:23.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.15:30:23.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.15:30:23.53#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:23.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:23.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:23.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:23.53#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:30:23.53#ibcon#first serial, iclass 25, count 0 2006.257.15:30:23.53#ibcon#enter sib2, iclass 25, count 0 2006.257.15:30:23.53#ibcon#flushed, iclass 25, count 0 2006.257.15:30:23.53#ibcon#about to write, iclass 25, count 0 2006.257.15:30:23.53#ibcon#wrote, iclass 25, count 0 2006.257.15:30:23.53#ibcon#about to read 3, iclass 25, count 0 2006.257.15:30:23.55#ibcon#read 3, iclass 25, count 0 2006.257.15:30:23.55#ibcon#about to read 4, iclass 25, count 0 2006.257.15:30:23.55#ibcon#read 4, iclass 25, count 0 2006.257.15:30:23.55#ibcon#about to read 5, iclass 25, count 0 2006.257.15:30:23.55#ibcon#read 5, iclass 25, count 0 2006.257.15:30:23.55#ibcon#about to read 6, iclass 25, count 0 2006.257.15:30:23.55#ibcon#read 6, iclass 25, count 0 2006.257.15:30:23.55#ibcon#end of sib2, iclass 25, count 0 2006.257.15:30:23.55#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:30:23.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:30:23.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:30:23.55#ibcon#*before write, iclass 25, count 0 2006.257.15:30:23.55#ibcon#enter sib2, iclass 25, count 0 2006.257.15:30:23.55#ibcon#flushed, iclass 25, count 0 2006.257.15:30:23.55#ibcon#about to write, iclass 25, count 0 2006.257.15:30:23.55#ibcon#wrote, iclass 25, count 0 2006.257.15:30:23.55#ibcon#about to read 3, iclass 25, count 0 2006.257.15:30:23.59#ibcon#read 3, iclass 25, count 0 2006.257.15:30:23.59#ibcon#about to read 4, iclass 25, count 0 2006.257.15:30:23.59#ibcon#read 4, iclass 25, count 0 2006.257.15:30:23.59#ibcon#about to read 5, iclass 25, count 0 2006.257.15:30:23.59#ibcon#read 5, iclass 25, count 0 2006.257.15:30:23.59#ibcon#about to read 6, iclass 25, count 0 2006.257.15:30:23.59#ibcon#read 6, iclass 25, count 0 2006.257.15:30:23.59#ibcon#end of sib2, iclass 25, count 0 2006.257.15:30:23.59#ibcon#*after write, iclass 25, count 0 2006.257.15:30:23.59#ibcon#*before return 0, iclass 25, count 0 2006.257.15:30:23.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:23.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:30:23.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:30:23.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:30:23.59$vck44/vb=3,4 2006.257.15:30:23.59#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.15:30:23.59#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.15:30:23.59#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:23.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:23.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:23.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:23.65#ibcon#enter wrdev, iclass 27, count 2 2006.257.15:30:23.65#ibcon#first serial, iclass 27, count 2 2006.257.15:30:23.65#ibcon#enter sib2, iclass 27, count 2 2006.257.15:30:23.65#ibcon#flushed, iclass 27, count 2 2006.257.15:30:23.65#ibcon#about to write, iclass 27, count 2 2006.257.15:30:23.65#ibcon#wrote, iclass 27, count 2 2006.257.15:30:23.65#ibcon#about to read 3, iclass 27, count 2 2006.257.15:30:23.67#ibcon#read 3, iclass 27, count 2 2006.257.15:30:23.67#ibcon#about to read 4, iclass 27, count 2 2006.257.15:30:23.67#ibcon#read 4, iclass 27, count 2 2006.257.15:30:23.67#ibcon#about to read 5, iclass 27, count 2 2006.257.15:30:23.67#ibcon#read 5, iclass 27, count 2 2006.257.15:30:23.67#ibcon#about to read 6, iclass 27, count 2 2006.257.15:30:23.67#ibcon#read 6, iclass 27, count 2 2006.257.15:30:23.67#ibcon#end of sib2, iclass 27, count 2 2006.257.15:30:23.67#ibcon#*mode == 0, iclass 27, count 2 2006.257.15:30:23.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.15:30:23.67#ibcon#[27=AT03-04\r\n] 2006.257.15:30:23.67#ibcon#*before write, iclass 27, count 2 2006.257.15:30:23.67#ibcon#enter sib2, iclass 27, count 2 2006.257.15:30:23.67#ibcon#flushed, iclass 27, count 2 2006.257.15:30:23.67#ibcon#about to write, iclass 27, count 2 2006.257.15:30:23.67#ibcon#wrote, iclass 27, count 2 2006.257.15:30:23.67#ibcon#about to read 3, iclass 27, count 2 2006.257.15:30:23.70#ibcon#read 3, iclass 27, count 2 2006.257.15:30:23.70#ibcon#about to read 4, iclass 27, count 2 2006.257.15:30:23.70#ibcon#read 4, iclass 27, count 2 2006.257.15:30:23.70#ibcon#about to read 5, iclass 27, count 2 2006.257.15:30:23.70#ibcon#read 5, iclass 27, count 2 2006.257.15:30:23.70#ibcon#about to read 6, iclass 27, count 2 2006.257.15:30:23.70#ibcon#read 6, iclass 27, count 2 2006.257.15:30:23.70#ibcon#end of sib2, iclass 27, count 2 2006.257.15:30:23.70#ibcon#*after write, iclass 27, count 2 2006.257.15:30:23.70#ibcon#*before return 0, iclass 27, count 2 2006.257.15:30:23.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:23.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:30:23.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.15:30:23.70#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:23.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:23.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:23.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:23.82#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:30:23.82#ibcon#first serial, iclass 27, count 0 2006.257.15:30:23.82#ibcon#enter sib2, iclass 27, count 0 2006.257.15:30:23.82#ibcon#flushed, iclass 27, count 0 2006.257.15:30:23.82#ibcon#about to write, iclass 27, count 0 2006.257.15:30:23.82#ibcon#wrote, iclass 27, count 0 2006.257.15:30:23.82#ibcon#about to read 3, iclass 27, count 0 2006.257.15:30:23.84#ibcon#read 3, iclass 27, count 0 2006.257.15:30:23.84#ibcon#about to read 4, iclass 27, count 0 2006.257.15:30:23.84#ibcon#read 4, iclass 27, count 0 2006.257.15:30:23.84#ibcon#about to read 5, iclass 27, count 0 2006.257.15:30:23.84#ibcon#read 5, iclass 27, count 0 2006.257.15:30:23.84#ibcon#about to read 6, iclass 27, count 0 2006.257.15:30:23.84#ibcon#read 6, iclass 27, count 0 2006.257.15:30:23.84#ibcon#end of sib2, iclass 27, count 0 2006.257.15:30:23.84#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:30:23.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:30:23.84#ibcon#[27=USB\r\n] 2006.257.15:30:23.84#ibcon#*before write, iclass 27, count 0 2006.257.15:30:23.84#ibcon#enter sib2, iclass 27, count 0 2006.257.15:30:23.84#ibcon#flushed, iclass 27, count 0 2006.257.15:30:23.84#ibcon#about to write, iclass 27, count 0 2006.257.15:30:23.84#ibcon#wrote, iclass 27, count 0 2006.257.15:30:23.84#ibcon#about to read 3, iclass 27, count 0 2006.257.15:30:23.87#ibcon#read 3, iclass 27, count 0 2006.257.15:30:23.87#ibcon#about to read 4, iclass 27, count 0 2006.257.15:30:23.87#ibcon#read 4, iclass 27, count 0 2006.257.15:30:23.87#ibcon#about to read 5, iclass 27, count 0 2006.257.15:30:23.87#ibcon#read 5, iclass 27, count 0 2006.257.15:30:23.87#ibcon#about to read 6, iclass 27, count 0 2006.257.15:30:23.87#ibcon#read 6, iclass 27, count 0 2006.257.15:30:23.87#ibcon#end of sib2, iclass 27, count 0 2006.257.15:30:23.87#ibcon#*after write, iclass 27, count 0 2006.257.15:30:23.87#ibcon#*before return 0, iclass 27, count 0 2006.257.15:30:23.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:23.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:30:23.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:30:23.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:30:23.87$vck44/vblo=4,679.99 2006.257.15:30:23.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.15:30:23.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.15:30:23.87#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:23.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:30:23.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:30:23.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:30:23.87#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:30:23.87#ibcon#first serial, iclass 30, count 0 2006.257.15:30:23.87#ibcon#enter sib2, iclass 30, count 0 2006.257.15:30:23.87#ibcon#flushed, iclass 30, count 0 2006.257.15:30:23.87#ibcon#about to write, iclass 30, count 0 2006.257.15:30:23.87#ibcon#wrote, iclass 30, count 0 2006.257.15:30:23.87#ibcon#about to read 3, iclass 30, count 0 2006.257.15:30:23.89#ibcon#read 3, iclass 30, count 0 2006.257.15:30:23.89#ibcon#about to read 4, iclass 30, count 0 2006.257.15:30:23.89#ibcon#read 4, iclass 30, count 0 2006.257.15:30:23.89#ibcon#about to read 5, iclass 30, count 0 2006.257.15:30:23.89#ibcon#read 5, iclass 30, count 0 2006.257.15:30:23.89#ibcon#about to read 6, iclass 30, count 0 2006.257.15:30:23.89#ibcon#read 6, iclass 30, count 0 2006.257.15:30:23.89#ibcon#end of sib2, iclass 30, count 0 2006.257.15:30:23.89#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:30:23.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:30:23.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:30:23.89#ibcon#*before write, iclass 30, count 0 2006.257.15:30:23.89#ibcon#enter sib2, iclass 30, count 0 2006.257.15:30:23.89#ibcon#flushed, iclass 30, count 0 2006.257.15:30:23.89#ibcon#about to write, iclass 30, count 0 2006.257.15:30:23.89#ibcon#wrote, iclass 30, count 0 2006.257.15:30:23.89#ibcon#about to read 3, iclass 30, count 0 2006.257.15:30:23.92#abcon#<5=/14 1.0 2.2 17.48 961013.9\r\n> 2006.257.15:30:23.93#ibcon#read 3, iclass 30, count 0 2006.257.15:30:23.93#ibcon#about to read 4, iclass 30, count 0 2006.257.15:30:23.93#ibcon#read 4, iclass 30, count 0 2006.257.15:30:23.93#ibcon#about to read 5, iclass 30, count 0 2006.257.15:30:23.93#ibcon#read 5, iclass 30, count 0 2006.257.15:30:23.93#ibcon#about to read 6, iclass 30, count 0 2006.257.15:30:23.93#ibcon#read 6, iclass 30, count 0 2006.257.15:30:23.93#ibcon#end of sib2, iclass 30, count 0 2006.257.15:30:23.93#ibcon#*after write, iclass 30, count 0 2006.257.15:30:23.93#ibcon#*before return 0, iclass 30, count 0 2006.257.15:30:23.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:30:23.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:30:23.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:30:23.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:30:23.93$vck44/vb=4,5 2006.257.15:30:23.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.15:30:23.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.15:30:23.93#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:23.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:30:23.94#abcon#{5=INTERFACE CLEAR} 2006.257.15:30:23.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:30:23.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:30:23.99#ibcon#enter wrdev, iclass 34, count 2 2006.257.15:30:23.99#ibcon#first serial, iclass 34, count 2 2006.257.15:30:23.99#ibcon#enter sib2, iclass 34, count 2 2006.257.15:30:23.99#ibcon#flushed, iclass 34, count 2 2006.257.15:30:23.99#ibcon#about to write, iclass 34, count 2 2006.257.15:30:23.99#ibcon#wrote, iclass 34, count 2 2006.257.15:30:23.99#ibcon#about to read 3, iclass 34, count 2 2006.257.15:30:24.00#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:30:24.01#ibcon#read 3, iclass 34, count 2 2006.257.15:30:24.01#ibcon#about to read 4, iclass 34, count 2 2006.257.15:30:24.01#ibcon#read 4, iclass 34, count 2 2006.257.15:30:24.01#ibcon#about to read 5, iclass 34, count 2 2006.257.15:30:24.01#ibcon#read 5, iclass 34, count 2 2006.257.15:30:24.01#ibcon#about to read 6, iclass 34, count 2 2006.257.15:30:24.01#ibcon#read 6, iclass 34, count 2 2006.257.15:30:24.01#ibcon#end of sib2, iclass 34, count 2 2006.257.15:30:24.01#ibcon#*mode == 0, iclass 34, count 2 2006.257.15:30:24.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.15:30:24.01#ibcon#[27=AT04-05\r\n] 2006.257.15:30:24.01#ibcon#*before write, iclass 34, count 2 2006.257.15:30:24.01#ibcon#enter sib2, iclass 34, count 2 2006.257.15:30:24.01#ibcon#flushed, iclass 34, count 2 2006.257.15:30:24.01#ibcon#about to write, iclass 34, count 2 2006.257.15:30:24.01#ibcon#wrote, iclass 34, count 2 2006.257.15:30:24.01#ibcon#about to read 3, iclass 34, count 2 2006.257.15:30:24.04#ibcon#read 3, iclass 34, count 2 2006.257.15:30:24.04#ibcon#about to read 4, iclass 34, count 2 2006.257.15:30:24.04#ibcon#read 4, iclass 34, count 2 2006.257.15:30:24.04#ibcon#about to read 5, iclass 34, count 2 2006.257.15:30:24.04#ibcon#read 5, iclass 34, count 2 2006.257.15:30:24.04#ibcon#about to read 6, iclass 34, count 2 2006.257.15:30:24.04#ibcon#read 6, iclass 34, count 2 2006.257.15:30:24.04#ibcon#end of sib2, iclass 34, count 2 2006.257.15:30:24.04#ibcon#*after write, iclass 34, count 2 2006.257.15:30:24.04#ibcon#*before return 0, iclass 34, count 2 2006.257.15:30:24.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:30:24.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:30:24.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.15:30:24.04#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:24.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:30:24.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:30:24.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:30:24.16#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:30:24.16#ibcon#first serial, iclass 34, count 0 2006.257.15:30:24.16#ibcon#enter sib2, iclass 34, count 0 2006.257.15:30:24.16#ibcon#flushed, iclass 34, count 0 2006.257.15:30:24.16#ibcon#about to write, iclass 34, count 0 2006.257.15:30:24.16#ibcon#wrote, iclass 34, count 0 2006.257.15:30:24.16#ibcon#about to read 3, iclass 34, count 0 2006.257.15:30:24.18#ibcon#read 3, iclass 34, count 0 2006.257.15:30:24.18#ibcon#about to read 4, iclass 34, count 0 2006.257.15:30:24.18#ibcon#read 4, iclass 34, count 0 2006.257.15:30:24.18#ibcon#about to read 5, iclass 34, count 0 2006.257.15:30:24.18#ibcon#read 5, iclass 34, count 0 2006.257.15:30:24.18#ibcon#about to read 6, iclass 34, count 0 2006.257.15:30:24.18#ibcon#read 6, iclass 34, count 0 2006.257.15:30:24.18#ibcon#end of sib2, iclass 34, count 0 2006.257.15:30:24.18#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:30:24.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:30:24.18#ibcon#[27=USB\r\n] 2006.257.15:30:24.18#ibcon#*before write, iclass 34, count 0 2006.257.15:30:24.18#ibcon#enter sib2, iclass 34, count 0 2006.257.15:30:24.18#ibcon#flushed, iclass 34, count 0 2006.257.15:30:24.18#ibcon#about to write, iclass 34, count 0 2006.257.15:30:24.18#ibcon#wrote, iclass 34, count 0 2006.257.15:30:24.18#ibcon#about to read 3, iclass 34, count 0 2006.257.15:30:24.21#ibcon#read 3, iclass 34, count 0 2006.257.15:30:24.21#ibcon#about to read 4, iclass 34, count 0 2006.257.15:30:24.21#ibcon#read 4, iclass 34, count 0 2006.257.15:30:24.21#ibcon#about to read 5, iclass 34, count 0 2006.257.15:30:24.21#ibcon#read 5, iclass 34, count 0 2006.257.15:30:24.21#ibcon#about to read 6, iclass 34, count 0 2006.257.15:30:24.21#ibcon#read 6, iclass 34, count 0 2006.257.15:30:24.21#ibcon#end of sib2, iclass 34, count 0 2006.257.15:30:24.21#ibcon#*after write, iclass 34, count 0 2006.257.15:30:24.21#ibcon#*before return 0, iclass 34, count 0 2006.257.15:30:24.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:30:24.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:30:24.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:30:24.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:30:24.21$vck44/vblo=5,709.99 2006.257.15:30:24.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.15:30:24.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.15:30:24.21#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:24.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:24.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:24.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:24.21#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:30:24.21#ibcon#first serial, iclass 37, count 0 2006.257.15:30:24.21#ibcon#enter sib2, iclass 37, count 0 2006.257.15:30:24.21#ibcon#flushed, iclass 37, count 0 2006.257.15:30:24.21#ibcon#about to write, iclass 37, count 0 2006.257.15:30:24.21#ibcon#wrote, iclass 37, count 0 2006.257.15:30:24.21#ibcon#about to read 3, iclass 37, count 0 2006.257.15:30:24.23#ibcon#read 3, iclass 37, count 0 2006.257.15:30:24.23#ibcon#about to read 4, iclass 37, count 0 2006.257.15:30:24.23#ibcon#read 4, iclass 37, count 0 2006.257.15:30:24.23#ibcon#about to read 5, iclass 37, count 0 2006.257.15:30:24.23#ibcon#read 5, iclass 37, count 0 2006.257.15:30:24.23#ibcon#about to read 6, iclass 37, count 0 2006.257.15:30:24.23#ibcon#read 6, iclass 37, count 0 2006.257.15:30:24.23#ibcon#end of sib2, iclass 37, count 0 2006.257.15:30:24.23#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:30:24.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:30:24.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:30:24.23#ibcon#*before write, iclass 37, count 0 2006.257.15:30:24.23#ibcon#enter sib2, iclass 37, count 0 2006.257.15:30:24.23#ibcon#flushed, iclass 37, count 0 2006.257.15:30:24.23#ibcon#about to write, iclass 37, count 0 2006.257.15:30:24.23#ibcon#wrote, iclass 37, count 0 2006.257.15:30:24.23#ibcon#about to read 3, iclass 37, count 0 2006.257.15:30:24.27#ibcon#read 3, iclass 37, count 0 2006.257.15:30:24.27#ibcon#about to read 4, iclass 37, count 0 2006.257.15:30:24.27#ibcon#read 4, iclass 37, count 0 2006.257.15:30:24.27#ibcon#about to read 5, iclass 37, count 0 2006.257.15:30:24.27#ibcon#read 5, iclass 37, count 0 2006.257.15:30:24.27#ibcon#about to read 6, iclass 37, count 0 2006.257.15:30:24.27#ibcon#read 6, iclass 37, count 0 2006.257.15:30:24.27#ibcon#end of sib2, iclass 37, count 0 2006.257.15:30:24.27#ibcon#*after write, iclass 37, count 0 2006.257.15:30:24.27#ibcon#*before return 0, iclass 37, count 0 2006.257.15:30:24.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:24.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:30:24.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:30:24.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:30:24.27$vck44/vb=5,4 2006.257.15:30:24.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.15:30:24.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.15:30:24.27#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:24.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:24.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:24.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:24.33#ibcon#enter wrdev, iclass 39, count 2 2006.257.15:30:24.33#ibcon#first serial, iclass 39, count 2 2006.257.15:30:24.33#ibcon#enter sib2, iclass 39, count 2 2006.257.15:30:24.33#ibcon#flushed, iclass 39, count 2 2006.257.15:30:24.33#ibcon#about to write, iclass 39, count 2 2006.257.15:30:24.33#ibcon#wrote, iclass 39, count 2 2006.257.15:30:24.33#ibcon#about to read 3, iclass 39, count 2 2006.257.15:30:24.35#ibcon#read 3, iclass 39, count 2 2006.257.15:30:24.35#ibcon#about to read 4, iclass 39, count 2 2006.257.15:30:24.35#ibcon#read 4, iclass 39, count 2 2006.257.15:30:24.35#ibcon#about to read 5, iclass 39, count 2 2006.257.15:30:24.35#ibcon#read 5, iclass 39, count 2 2006.257.15:30:24.35#ibcon#about to read 6, iclass 39, count 2 2006.257.15:30:24.35#ibcon#read 6, iclass 39, count 2 2006.257.15:30:24.35#ibcon#end of sib2, iclass 39, count 2 2006.257.15:30:24.35#ibcon#*mode == 0, iclass 39, count 2 2006.257.15:30:24.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.15:30:24.35#ibcon#[27=AT05-04\r\n] 2006.257.15:30:24.35#ibcon#*before write, iclass 39, count 2 2006.257.15:30:24.35#ibcon#enter sib2, iclass 39, count 2 2006.257.15:30:24.35#ibcon#flushed, iclass 39, count 2 2006.257.15:30:24.35#ibcon#about to write, iclass 39, count 2 2006.257.15:30:24.35#ibcon#wrote, iclass 39, count 2 2006.257.15:30:24.35#ibcon#about to read 3, iclass 39, count 2 2006.257.15:30:24.38#ibcon#read 3, iclass 39, count 2 2006.257.15:30:24.38#ibcon#about to read 4, iclass 39, count 2 2006.257.15:30:24.38#ibcon#read 4, iclass 39, count 2 2006.257.15:30:24.38#ibcon#about to read 5, iclass 39, count 2 2006.257.15:30:24.38#ibcon#read 5, iclass 39, count 2 2006.257.15:30:24.38#ibcon#about to read 6, iclass 39, count 2 2006.257.15:30:24.38#ibcon#read 6, iclass 39, count 2 2006.257.15:30:24.38#ibcon#end of sib2, iclass 39, count 2 2006.257.15:30:24.38#ibcon#*after write, iclass 39, count 2 2006.257.15:30:24.38#ibcon#*before return 0, iclass 39, count 2 2006.257.15:30:24.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:24.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:30:24.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.15:30:24.38#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:24.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:24.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:24.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:24.50#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:30:24.50#ibcon#first serial, iclass 39, count 0 2006.257.15:30:24.50#ibcon#enter sib2, iclass 39, count 0 2006.257.15:30:24.50#ibcon#flushed, iclass 39, count 0 2006.257.15:30:24.50#ibcon#about to write, iclass 39, count 0 2006.257.15:30:24.50#ibcon#wrote, iclass 39, count 0 2006.257.15:30:24.50#ibcon#about to read 3, iclass 39, count 0 2006.257.15:30:24.52#ibcon#read 3, iclass 39, count 0 2006.257.15:30:24.52#ibcon#about to read 4, iclass 39, count 0 2006.257.15:30:24.52#ibcon#read 4, iclass 39, count 0 2006.257.15:30:24.52#ibcon#about to read 5, iclass 39, count 0 2006.257.15:30:24.52#ibcon#read 5, iclass 39, count 0 2006.257.15:30:24.52#ibcon#about to read 6, iclass 39, count 0 2006.257.15:30:24.52#ibcon#read 6, iclass 39, count 0 2006.257.15:30:24.52#ibcon#end of sib2, iclass 39, count 0 2006.257.15:30:24.52#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:30:24.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:30:24.52#ibcon#[27=USB\r\n] 2006.257.15:30:24.52#ibcon#*before write, iclass 39, count 0 2006.257.15:30:24.52#ibcon#enter sib2, iclass 39, count 0 2006.257.15:30:24.52#ibcon#flushed, iclass 39, count 0 2006.257.15:30:24.52#ibcon#about to write, iclass 39, count 0 2006.257.15:30:24.52#ibcon#wrote, iclass 39, count 0 2006.257.15:30:24.52#ibcon#about to read 3, iclass 39, count 0 2006.257.15:30:24.55#ibcon#read 3, iclass 39, count 0 2006.257.15:30:24.55#ibcon#about to read 4, iclass 39, count 0 2006.257.15:30:24.55#ibcon#read 4, iclass 39, count 0 2006.257.15:30:24.55#ibcon#about to read 5, iclass 39, count 0 2006.257.15:30:24.55#ibcon#read 5, iclass 39, count 0 2006.257.15:30:24.55#ibcon#about to read 6, iclass 39, count 0 2006.257.15:30:24.55#ibcon#read 6, iclass 39, count 0 2006.257.15:30:24.55#ibcon#end of sib2, iclass 39, count 0 2006.257.15:30:24.55#ibcon#*after write, iclass 39, count 0 2006.257.15:30:24.55#ibcon#*before return 0, iclass 39, count 0 2006.257.15:30:24.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:24.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:30:24.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:30:24.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:30:24.55$vck44/vblo=6,719.99 2006.257.15:30:24.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.15:30:24.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.15:30:24.55#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:24.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:24.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:24.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:24.55#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:30:24.55#ibcon#first serial, iclass 3, count 0 2006.257.15:30:24.55#ibcon#enter sib2, iclass 3, count 0 2006.257.15:30:24.55#ibcon#flushed, iclass 3, count 0 2006.257.15:30:24.55#ibcon#about to write, iclass 3, count 0 2006.257.15:30:24.55#ibcon#wrote, iclass 3, count 0 2006.257.15:30:24.55#ibcon#about to read 3, iclass 3, count 0 2006.257.15:30:24.57#ibcon#read 3, iclass 3, count 0 2006.257.15:30:24.57#ibcon#about to read 4, iclass 3, count 0 2006.257.15:30:24.57#ibcon#read 4, iclass 3, count 0 2006.257.15:30:24.57#ibcon#about to read 5, iclass 3, count 0 2006.257.15:30:24.57#ibcon#read 5, iclass 3, count 0 2006.257.15:30:24.57#ibcon#about to read 6, iclass 3, count 0 2006.257.15:30:24.57#ibcon#read 6, iclass 3, count 0 2006.257.15:30:24.57#ibcon#end of sib2, iclass 3, count 0 2006.257.15:30:24.57#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:30:24.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:30:24.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:30:24.57#ibcon#*before write, iclass 3, count 0 2006.257.15:30:24.57#ibcon#enter sib2, iclass 3, count 0 2006.257.15:30:24.57#ibcon#flushed, iclass 3, count 0 2006.257.15:30:24.57#ibcon#about to write, iclass 3, count 0 2006.257.15:30:24.57#ibcon#wrote, iclass 3, count 0 2006.257.15:30:24.57#ibcon#about to read 3, iclass 3, count 0 2006.257.15:30:24.61#ibcon#read 3, iclass 3, count 0 2006.257.15:30:24.61#ibcon#about to read 4, iclass 3, count 0 2006.257.15:30:24.61#ibcon#read 4, iclass 3, count 0 2006.257.15:30:24.61#ibcon#about to read 5, iclass 3, count 0 2006.257.15:30:24.61#ibcon#read 5, iclass 3, count 0 2006.257.15:30:24.61#ibcon#about to read 6, iclass 3, count 0 2006.257.15:30:24.61#ibcon#read 6, iclass 3, count 0 2006.257.15:30:24.61#ibcon#end of sib2, iclass 3, count 0 2006.257.15:30:24.61#ibcon#*after write, iclass 3, count 0 2006.257.15:30:24.61#ibcon#*before return 0, iclass 3, count 0 2006.257.15:30:24.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:24.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:30:24.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:30:24.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:30:24.61$vck44/vb=6,4 2006.257.15:30:24.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.15:30:24.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.15:30:24.61#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:24.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:24.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:24.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:24.67#ibcon#enter wrdev, iclass 5, count 2 2006.257.15:30:24.67#ibcon#first serial, iclass 5, count 2 2006.257.15:30:24.67#ibcon#enter sib2, iclass 5, count 2 2006.257.15:30:24.67#ibcon#flushed, iclass 5, count 2 2006.257.15:30:24.67#ibcon#about to write, iclass 5, count 2 2006.257.15:30:24.67#ibcon#wrote, iclass 5, count 2 2006.257.15:30:24.67#ibcon#about to read 3, iclass 5, count 2 2006.257.15:30:24.69#ibcon#read 3, iclass 5, count 2 2006.257.15:30:24.69#ibcon#about to read 4, iclass 5, count 2 2006.257.15:30:24.69#ibcon#read 4, iclass 5, count 2 2006.257.15:30:24.69#ibcon#about to read 5, iclass 5, count 2 2006.257.15:30:24.69#ibcon#read 5, iclass 5, count 2 2006.257.15:30:24.69#ibcon#about to read 6, iclass 5, count 2 2006.257.15:30:24.69#ibcon#read 6, iclass 5, count 2 2006.257.15:30:24.69#ibcon#end of sib2, iclass 5, count 2 2006.257.15:30:24.69#ibcon#*mode == 0, iclass 5, count 2 2006.257.15:30:24.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.15:30:24.69#ibcon#[27=AT06-04\r\n] 2006.257.15:30:24.69#ibcon#*before write, iclass 5, count 2 2006.257.15:30:24.69#ibcon#enter sib2, iclass 5, count 2 2006.257.15:30:24.69#ibcon#flushed, iclass 5, count 2 2006.257.15:30:24.69#ibcon#about to write, iclass 5, count 2 2006.257.15:30:24.69#ibcon#wrote, iclass 5, count 2 2006.257.15:30:24.69#ibcon#about to read 3, iclass 5, count 2 2006.257.15:30:24.72#ibcon#read 3, iclass 5, count 2 2006.257.15:30:24.72#ibcon#about to read 4, iclass 5, count 2 2006.257.15:30:24.72#ibcon#read 4, iclass 5, count 2 2006.257.15:30:24.72#ibcon#about to read 5, iclass 5, count 2 2006.257.15:30:24.72#ibcon#read 5, iclass 5, count 2 2006.257.15:30:24.72#ibcon#about to read 6, iclass 5, count 2 2006.257.15:30:24.72#ibcon#read 6, iclass 5, count 2 2006.257.15:30:24.72#ibcon#end of sib2, iclass 5, count 2 2006.257.15:30:24.72#ibcon#*after write, iclass 5, count 2 2006.257.15:30:24.72#ibcon#*before return 0, iclass 5, count 2 2006.257.15:30:24.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:24.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:30:24.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.15:30:24.72#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:24.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:24.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:24.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:24.84#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:30:24.84#ibcon#first serial, iclass 5, count 0 2006.257.15:30:24.84#ibcon#enter sib2, iclass 5, count 0 2006.257.15:30:24.84#ibcon#flushed, iclass 5, count 0 2006.257.15:30:24.84#ibcon#about to write, iclass 5, count 0 2006.257.15:30:24.84#ibcon#wrote, iclass 5, count 0 2006.257.15:30:24.84#ibcon#about to read 3, iclass 5, count 0 2006.257.15:30:24.86#ibcon#read 3, iclass 5, count 0 2006.257.15:30:24.86#ibcon#about to read 4, iclass 5, count 0 2006.257.15:30:24.86#ibcon#read 4, iclass 5, count 0 2006.257.15:30:24.86#ibcon#about to read 5, iclass 5, count 0 2006.257.15:30:24.86#ibcon#read 5, iclass 5, count 0 2006.257.15:30:24.86#ibcon#about to read 6, iclass 5, count 0 2006.257.15:30:24.86#ibcon#read 6, iclass 5, count 0 2006.257.15:30:24.86#ibcon#end of sib2, iclass 5, count 0 2006.257.15:30:24.86#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:30:24.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:30:24.86#ibcon#[27=USB\r\n] 2006.257.15:30:24.86#ibcon#*before write, iclass 5, count 0 2006.257.15:30:24.86#ibcon#enter sib2, iclass 5, count 0 2006.257.15:30:24.86#ibcon#flushed, iclass 5, count 0 2006.257.15:30:24.86#ibcon#about to write, iclass 5, count 0 2006.257.15:30:24.86#ibcon#wrote, iclass 5, count 0 2006.257.15:30:24.86#ibcon#about to read 3, iclass 5, count 0 2006.257.15:30:24.89#ibcon#read 3, iclass 5, count 0 2006.257.15:30:24.89#ibcon#about to read 4, iclass 5, count 0 2006.257.15:30:24.89#ibcon#read 4, iclass 5, count 0 2006.257.15:30:24.89#ibcon#about to read 5, iclass 5, count 0 2006.257.15:30:24.89#ibcon#read 5, iclass 5, count 0 2006.257.15:30:24.89#ibcon#about to read 6, iclass 5, count 0 2006.257.15:30:24.89#ibcon#read 6, iclass 5, count 0 2006.257.15:30:24.89#ibcon#end of sib2, iclass 5, count 0 2006.257.15:30:24.89#ibcon#*after write, iclass 5, count 0 2006.257.15:30:24.89#ibcon#*before return 0, iclass 5, count 0 2006.257.15:30:24.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:24.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:30:24.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:30:24.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:30:24.89$vck44/vblo=7,734.99 2006.257.15:30:24.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.15:30:24.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.15:30:24.89#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:24.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:24.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:24.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:24.89#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:30:24.89#ibcon#first serial, iclass 7, count 0 2006.257.15:30:24.89#ibcon#enter sib2, iclass 7, count 0 2006.257.15:30:24.89#ibcon#flushed, iclass 7, count 0 2006.257.15:30:24.89#ibcon#about to write, iclass 7, count 0 2006.257.15:30:24.89#ibcon#wrote, iclass 7, count 0 2006.257.15:30:24.89#ibcon#about to read 3, iclass 7, count 0 2006.257.15:30:24.91#ibcon#read 3, iclass 7, count 0 2006.257.15:30:24.91#ibcon#about to read 4, iclass 7, count 0 2006.257.15:30:24.91#ibcon#read 4, iclass 7, count 0 2006.257.15:30:24.91#ibcon#about to read 5, iclass 7, count 0 2006.257.15:30:24.91#ibcon#read 5, iclass 7, count 0 2006.257.15:30:24.91#ibcon#about to read 6, iclass 7, count 0 2006.257.15:30:24.91#ibcon#read 6, iclass 7, count 0 2006.257.15:30:24.91#ibcon#end of sib2, iclass 7, count 0 2006.257.15:30:24.91#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:30:24.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:30:24.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:30:24.91#ibcon#*before write, iclass 7, count 0 2006.257.15:30:24.91#ibcon#enter sib2, iclass 7, count 0 2006.257.15:30:24.91#ibcon#flushed, iclass 7, count 0 2006.257.15:30:24.91#ibcon#about to write, iclass 7, count 0 2006.257.15:30:24.91#ibcon#wrote, iclass 7, count 0 2006.257.15:30:24.91#ibcon#about to read 3, iclass 7, count 0 2006.257.15:30:24.95#ibcon#read 3, iclass 7, count 0 2006.257.15:30:24.95#ibcon#about to read 4, iclass 7, count 0 2006.257.15:30:24.95#ibcon#read 4, iclass 7, count 0 2006.257.15:30:24.95#ibcon#about to read 5, iclass 7, count 0 2006.257.15:30:24.95#ibcon#read 5, iclass 7, count 0 2006.257.15:30:24.95#ibcon#about to read 6, iclass 7, count 0 2006.257.15:30:24.95#ibcon#read 6, iclass 7, count 0 2006.257.15:30:24.95#ibcon#end of sib2, iclass 7, count 0 2006.257.15:30:24.95#ibcon#*after write, iclass 7, count 0 2006.257.15:30:24.95#ibcon#*before return 0, iclass 7, count 0 2006.257.15:30:24.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:24.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:30:24.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:30:24.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:30:24.95$vck44/vb=7,4 2006.257.15:30:24.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.15:30:24.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.15:30:24.95#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:24.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:25.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:25.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:25.01#ibcon#enter wrdev, iclass 11, count 2 2006.257.15:30:25.01#ibcon#first serial, iclass 11, count 2 2006.257.15:30:25.01#ibcon#enter sib2, iclass 11, count 2 2006.257.15:30:25.01#ibcon#flushed, iclass 11, count 2 2006.257.15:30:25.01#ibcon#about to write, iclass 11, count 2 2006.257.15:30:25.01#ibcon#wrote, iclass 11, count 2 2006.257.15:30:25.01#ibcon#about to read 3, iclass 11, count 2 2006.257.15:30:25.03#ibcon#read 3, iclass 11, count 2 2006.257.15:30:25.03#ibcon#about to read 4, iclass 11, count 2 2006.257.15:30:25.03#ibcon#read 4, iclass 11, count 2 2006.257.15:30:25.03#ibcon#about to read 5, iclass 11, count 2 2006.257.15:30:25.03#ibcon#read 5, iclass 11, count 2 2006.257.15:30:25.03#ibcon#about to read 6, iclass 11, count 2 2006.257.15:30:25.03#ibcon#read 6, iclass 11, count 2 2006.257.15:30:25.03#ibcon#end of sib2, iclass 11, count 2 2006.257.15:30:25.03#ibcon#*mode == 0, iclass 11, count 2 2006.257.15:30:25.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.15:30:25.03#ibcon#[27=AT07-04\r\n] 2006.257.15:30:25.03#ibcon#*before write, iclass 11, count 2 2006.257.15:30:25.03#ibcon#enter sib2, iclass 11, count 2 2006.257.15:30:25.03#ibcon#flushed, iclass 11, count 2 2006.257.15:30:25.03#ibcon#about to write, iclass 11, count 2 2006.257.15:30:25.03#ibcon#wrote, iclass 11, count 2 2006.257.15:30:25.03#ibcon#about to read 3, iclass 11, count 2 2006.257.15:30:25.06#ibcon#read 3, iclass 11, count 2 2006.257.15:30:25.06#ibcon#about to read 4, iclass 11, count 2 2006.257.15:30:25.06#ibcon#read 4, iclass 11, count 2 2006.257.15:30:25.06#ibcon#about to read 5, iclass 11, count 2 2006.257.15:30:25.06#ibcon#read 5, iclass 11, count 2 2006.257.15:30:25.06#ibcon#about to read 6, iclass 11, count 2 2006.257.15:30:25.06#ibcon#read 6, iclass 11, count 2 2006.257.15:30:25.06#ibcon#end of sib2, iclass 11, count 2 2006.257.15:30:25.06#ibcon#*after write, iclass 11, count 2 2006.257.15:30:25.06#ibcon#*before return 0, iclass 11, count 2 2006.257.15:30:25.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:25.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:30:25.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.15:30:25.06#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:25.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:25.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:25.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:25.18#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:30:25.18#ibcon#first serial, iclass 11, count 0 2006.257.15:30:25.18#ibcon#enter sib2, iclass 11, count 0 2006.257.15:30:25.18#ibcon#flushed, iclass 11, count 0 2006.257.15:30:25.18#ibcon#about to write, iclass 11, count 0 2006.257.15:30:25.18#ibcon#wrote, iclass 11, count 0 2006.257.15:30:25.18#ibcon#about to read 3, iclass 11, count 0 2006.257.15:30:25.20#ibcon#read 3, iclass 11, count 0 2006.257.15:30:25.20#ibcon#about to read 4, iclass 11, count 0 2006.257.15:30:25.20#ibcon#read 4, iclass 11, count 0 2006.257.15:30:25.20#ibcon#about to read 5, iclass 11, count 0 2006.257.15:30:25.20#ibcon#read 5, iclass 11, count 0 2006.257.15:30:25.20#ibcon#about to read 6, iclass 11, count 0 2006.257.15:30:25.20#ibcon#read 6, iclass 11, count 0 2006.257.15:30:25.20#ibcon#end of sib2, iclass 11, count 0 2006.257.15:30:25.20#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:30:25.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:30:25.20#ibcon#[27=USB\r\n] 2006.257.15:30:25.20#ibcon#*before write, iclass 11, count 0 2006.257.15:30:25.20#ibcon#enter sib2, iclass 11, count 0 2006.257.15:30:25.20#ibcon#flushed, iclass 11, count 0 2006.257.15:30:25.20#ibcon#about to write, iclass 11, count 0 2006.257.15:30:25.20#ibcon#wrote, iclass 11, count 0 2006.257.15:30:25.20#ibcon#about to read 3, iclass 11, count 0 2006.257.15:30:25.23#ibcon#read 3, iclass 11, count 0 2006.257.15:30:25.23#ibcon#about to read 4, iclass 11, count 0 2006.257.15:30:25.23#ibcon#read 4, iclass 11, count 0 2006.257.15:30:25.23#ibcon#about to read 5, iclass 11, count 0 2006.257.15:30:25.23#ibcon#read 5, iclass 11, count 0 2006.257.15:30:25.23#ibcon#about to read 6, iclass 11, count 0 2006.257.15:30:25.23#ibcon#read 6, iclass 11, count 0 2006.257.15:30:25.23#ibcon#end of sib2, iclass 11, count 0 2006.257.15:30:25.23#ibcon#*after write, iclass 11, count 0 2006.257.15:30:25.23#ibcon#*before return 0, iclass 11, count 0 2006.257.15:30:25.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:25.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:30:25.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:30:25.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:30:25.23$vck44/vblo=8,744.99 2006.257.15:30:25.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.15:30:25.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.15:30:25.23#ibcon#ireg 17 cls_cnt 0 2006.257.15:30:25.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:25.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:25.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:25.23#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:30:25.23#ibcon#first serial, iclass 13, count 0 2006.257.15:30:25.23#ibcon#enter sib2, iclass 13, count 0 2006.257.15:30:25.23#ibcon#flushed, iclass 13, count 0 2006.257.15:30:25.23#ibcon#about to write, iclass 13, count 0 2006.257.15:30:25.23#ibcon#wrote, iclass 13, count 0 2006.257.15:30:25.23#ibcon#about to read 3, iclass 13, count 0 2006.257.15:30:25.25#ibcon#read 3, iclass 13, count 0 2006.257.15:30:25.25#ibcon#about to read 4, iclass 13, count 0 2006.257.15:30:25.25#ibcon#read 4, iclass 13, count 0 2006.257.15:30:25.25#ibcon#about to read 5, iclass 13, count 0 2006.257.15:30:25.25#ibcon#read 5, iclass 13, count 0 2006.257.15:30:25.25#ibcon#about to read 6, iclass 13, count 0 2006.257.15:30:25.25#ibcon#read 6, iclass 13, count 0 2006.257.15:30:25.25#ibcon#end of sib2, iclass 13, count 0 2006.257.15:30:25.25#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:30:25.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:30:25.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:30:25.25#ibcon#*before write, iclass 13, count 0 2006.257.15:30:25.25#ibcon#enter sib2, iclass 13, count 0 2006.257.15:30:25.25#ibcon#flushed, iclass 13, count 0 2006.257.15:30:25.25#ibcon#about to write, iclass 13, count 0 2006.257.15:30:25.25#ibcon#wrote, iclass 13, count 0 2006.257.15:30:25.25#ibcon#about to read 3, iclass 13, count 0 2006.257.15:30:25.29#ibcon#read 3, iclass 13, count 0 2006.257.15:30:25.29#ibcon#about to read 4, iclass 13, count 0 2006.257.15:30:25.29#ibcon#read 4, iclass 13, count 0 2006.257.15:30:25.29#ibcon#about to read 5, iclass 13, count 0 2006.257.15:30:25.29#ibcon#read 5, iclass 13, count 0 2006.257.15:30:25.29#ibcon#about to read 6, iclass 13, count 0 2006.257.15:30:25.29#ibcon#read 6, iclass 13, count 0 2006.257.15:30:25.29#ibcon#end of sib2, iclass 13, count 0 2006.257.15:30:25.29#ibcon#*after write, iclass 13, count 0 2006.257.15:30:25.29#ibcon#*before return 0, iclass 13, count 0 2006.257.15:30:25.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:25.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:30:25.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:30:25.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:30:25.29$vck44/vb=8,4 2006.257.15:30:25.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.15:30:25.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.15:30:25.29#ibcon#ireg 11 cls_cnt 2 2006.257.15:30:25.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:25.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:25.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:25.35#ibcon#enter wrdev, iclass 15, count 2 2006.257.15:30:25.35#ibcon#first serial, iclass 15, count 2 2006.257.15:30:25.35#ibcon#enter sib2, iclass 15, count 2 2006.257.15:30:25.35#ibcon#flushed, iclass 15, count 2 2006.257.15:30:25.35#ibcon#about to write, iclass 15, count 2 2006.257.15:30:25.35#ibcon#wrote, iclass 15, count 2 2006.257.15:30:25.35#ibcon#about to read 3, iclass 15, count 2 2006.257.15:30:25.37#ibcon#read 3, iclass 15, count 2 2006.257.15:30:25.37#ibcon#about to read 4, iclass 15, count 2 2006.257.15:30:25.37#ibcon#read 4, iclass 15, count 2 2006.257.15:30:25.37#ibcon#about to read 5, iclass 15, count 2 2006.257.15:30:25.37#ibcon#read 5, iclass 15, count 2 2006.257.15:30:25.37#ibcon#about to read 6, iclass 15, count 2 2006.257.15:30:25.37#ibcon#read 6, iclass 15, count 2 2006.257.15:30:25.37#ibcon#end of sib2, iclass 15, count 2 2006.257.15:30:25.37#ibcon#*mode == 0, iclass 15, count 2 2006.257.15:30:25.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.15:30:25.37#ibcon#[27=AT08-04\r\n] 2006.257.15:30:25.37#ibcon#*before write, iclass 15, count 2 2006.257.15:30:25.37#ibcon#enter sib2, iclass 15, count 2 2006.257.15:30:25.37#ibcon#flushed, iclass 15, count 2 2006.257.15:30:25.37#ibcon#about to write, iclass 15, count 2 2006.257.15:30:25.37#ibcon#wrote, iclass 15, count 2 2006.257.15:30:25.37#ibcon#about to read 3, iclass 15, count 2 2006.257.15:30:25.40#ibcon#read 3, iclass 15, count 2 2006.257.15:30:25.40#ibcon#about to read 4, iclass 15, count 2 2006.257.15:30:25.40#ibcon#read 4, iclass 15, count 2 2006.257.15:30:25.40#ibcon#about to read 5, iclass 15, count 2 2006.257.15:30:25.40#ibcon#read 5, iclass 15, count 2 2006.257.15:30:25.40#ibcon#about to read 6, iclass 15, count 2 2006.257.15:30:25.40#ibcon#read 6, iclass 15, count 2 2006.257.15:30:25.40#ibcon#end of sib2, iclass 15, count 2 2006.257.15:30:25.40#ibcon#*after write, iclass 15, count 2 2006.257.15:30:25.40#ibcon#*before return 0, iclass 15, count 2 2006.257.15:30:25.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:25.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:30:25.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.15:30:25.40#ibcon#ireg 7 cls_cnt 0 2006.257.15:30:25.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:25.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:25.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:25.52#ibcon#enter wrdev, iclass 15, count 0 2006.257.15:30:25.52#ibcon#first serial, iclass 15, count 0 2006.257.15:30:25.52#ibcon#enter sib2, iclass 15, count 0 2006.257.15:30:25.52#ibcon#flushed, iclass 15, count 0 2006.257.15:30:25.52#ibcon#about to write, iclass 15, count 0 2006.257.15:30:25.52#ibcon#wrote, iclass 15, count 0 2006.257.15:30:25.52#ibcon#about to read 3, iclass 15, count 0 2006.257.15:30:25.54#ibcon#read 3, iclass 15, count 0 2006.257.15:30:25.54#ibcon#about to read 4, iclass 15, count 0 2006.257.15:30:25.54#ibcon#read 4, iclass 15, count 0 2006.257.15:30:25.54#ibcon#about to read 5, iclass 15, count 0 2006.257.15:30:25.54#ibcon#read 5, iclass 15, count 0 2006.257.15:30:25.54#ibcon#about to read 6, iclass 15, count 0 2006.257.15:30:25.54#ibcon#read 6, iclass 15, count 0 2006.257.15:30:25.54#ibcon#end of sib2, iclass 15, count 0 2006.257.15:30:25.54#ibcon#*mode == 0, iclass 15, count 0 2006.257.15:30:25.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.15:30:25.54#ibcon#[27=USB\r\n] 2006.257.15:30:25.54#ibcon#*before write, iclass 15, count 0 2006.257.15:30:25.54#ibcon#enter sib2, iclass 15, count 0 2006.257.15:30:25.54#ibcon#flushed, iclass 15, count 0 2006.257.15:30:25.54#ibcon#about to write, iclass 15, count 0 2006.257.15:30:25.54#ibcon#wrote, iclass 15, count 0 2006.257.15:30:25.54#ibcon#about to read 3, iclass 15, count 0 2006.257.15:30:25.57#ibcon#read 3, iclass 15, count 0 2006.257.15:30:25.57#ibcon#about to read 4, iclass 15, count 0 2006.257.15:30:25.57#ibcon#read 4, iclass 15, count 0 2006.257.15:30:25.57#ibcon#about to read 5, iclass 15, count 0 2006.257.15:30:25.57#ibcon#read 5, iclass 15, count 0 2006.257.15:30:25.57#ibcon#about to read 6, iclass 15, count 0 2006.257.15:30:25.57#ibcon#read 6, iclass 15, count 0 2006.257.15:30:25.57#ibcon#end of sib2, iclass 15, count 0 2006.257.15:30:25.57#ibcon#*after write, iclass 15, count 0 2006.257.15:30:25.57#ibcon#*before return 0, iclass 15, count 0 2006.257.15:30:25.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:25.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:30:25.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.15:30:25.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.15:30:25.57$vck44/vabw=wide 2006.257.15:30:25.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.15:30:25.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.15:30:25.57#ibcon#ireg 8 cls_cnt 0 2006.257.15:30:25.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:25.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:25.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:25.57#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:30:25.57#ibcon#first serial, iclass 17, count 0 2006.257.15:30:25.57#ibcon#enter sib2, iclass 17, count 0 2006.257.15:30:25.57#ibcon#flushed, iclass 17, count 0 2006.257.15:30:25.57#ibcon#about to write, iclass 17, count 0 2006.257.15:30:25.57#ibcon#wrote, iclass 17, count 0 2006.257.15:30:25.57#ibcon#about to read 3, iclass 17, count 0 2006.257.15:30:25.59#ibcon#read 3, iclass 17, count 0 2006.257.15:30:25.59#ibcon#about to read 4, iclass 17, count 0 2006.257.15:30:25.59#ibcon#read 4, iclass 17, count 0 2006.257.15:30:25.59#ibcon#about to read 5, iclass 17, count 0 2006.257.15:30:25.59#ibcon#read 5, iclass 17, count 0 2006.257.15:30:25.59#ibcon#about to read 6, iclass 17, count 0 2006.257.15:30:25.59#ibcon#read 6, iclass 17, count 0 2006.257.15:30:25.59#ibcon#end of sib2, iclass 17, count 0 2006.257.15:30:25.59#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:30:25.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:30:25.59#ibcon#[25=BW32\r\n] 2006.257.15:30:25.59#ibcon#*before write, iclass 17, count 0 2006.257.15:30:25.59#ibcon#enter sib2, iclass 17, count 0 2006.257.15:30:25.59#ibcon#flushed, iclass 17, count 0 2006.257.15:30:25.59#ibcon#about to write, iclass 17, count 0 2006.257.15:30:25.59#ibcon#wrote, iclass 17, count 0 2006.257.15:30:25.59#ibcon#about to read 3, iclass 17, count 0 2006.257.15:30:25.62#ibcon#read 3, iclass 17, count 0 2006.257.15:30:25.62#ibcon#about to read 4, iclass 17, count 0 2006.257.15:30:25.62#ibcon#read 4, iclass 17, count 0 2006.257.15:30:25.62#ibcon#about to read 5, iclass 17, count 0 2006.257.15:30:25.62#ibcon#read 5, iclass 17, count 0 2006.257.15:30:25.62#ibcon#about to read 6, iclass 17, count 0 2006.257.15:30:25.62#ibcon#read 6, iclass 17, count 0 2006.257.15:30:25.62#ibcon#end of sib2, iclass 17, count 0 2006.257.15:30:25.62#ibcon#*after write, iclass 17, count 0 2006.257.15:30:25.62#ibcon#*before return 0, iclass 17, count 0 2006.257.15:30:25.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:25.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:30:25.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:30:25.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:30:25.62$vck44/vbbw=wide 2006.257.15:30:25.62#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.15:30:25.62#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.15:30:25.62#ibcon#ireg 8 cls_cnt 0 2006.257.15:30:25.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:30:25.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:30:25.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:30:25.69#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:30:25.69#ibcon#first serial, iclass 19, count 0 2006.257.15:30:25.69#ibcon#enter sib2, iclass 19, count 0 2006.257.15:30:25.69#ibcon#flushed, iclass 19, count 0 2006.257.15:30:25.69#ibcon#about to write, iclass 19, count 0 2006.257.15:30:25.69#ibcon#wrote, iclass 19, count 0 2006.257.15:30:25.69#ibcon#about to read 3, iclass 19, count 0 2006.257.15:30:25.71#ibcon#read 3, iclass 19, count 0 2006.257.15:30:25.71#ibcon#about to read 4, iclass 19, count 0 2006.257.15:30:25.71#ibcon#read 4, iclass 19, count 0 2006.257.15:30:25.71#ibcon#about to read 5, iclass 19, count 0 2006.257.15:30:25.71#ibcon#read 5, iclass 19, count 0 2006.257.15:30:25.71#ibcon#about to read 6, iclass 19, count 0 2006.257.15:30:25.71#ibcon#read 6, iclass 19, count 0 2006.257.15:30:25.71#ibcon#end of sib2, iclass 19, count 0 2006.257.15:30:25.71#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:30:25.71#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:30:25.71#ibcon#[27=BW32\r\n] 2006.257.15:30:25.71#ibcon#*before write, iclass 19, count 0 2006.257.15:30:25.71#ibcon#enter sib2, iclass 19, count 0 2006.257.15:30:25.71#ibcon#flushed, iclass 19, count 0 2006.257.15:30:25.71#ibcon#about to write, iclass 19, count 0 2006.257.15:30:25.71#ibcon#wrote, iclass 19, count 0 2006.257.15:30:25.71#ibcon#about to read 3, iclass 19, count 0 2006.257.15:30:25.74#ibcon#read 3, iclass 19, count 0 2006.257.15:30:25.74#ibcon#about to read 4, iclass 19, count 0 2006.257.15:30:25.74#ibcon#read 4, iclass 19, count 0 2006.257.15:30:25.74#ibcon#about to read 5, iclass 19, count 0 2006.257.15:30:25.74#ibcon#read 5, iclass 19, count 0 2006.257.15:30:25.74#ibcon#about to read 6, iclass 19, count 0 2006.257.15:30:25.74#ibcon#read 6, iclass 19, count 0 2006.257.15:30:25.74#ibcon#end of sib2, iclass 19, count 0 2006.257.15:30:25.74#ibcon#*after write, iclass 19, count 0 2006.257.15:30:25.74#ibcon#*before return 0, iclass 19, count 0 2006.257.15:30:25.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:30:25.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:30:25.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:30:25.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:30:25.74$setupk4/ifdk4 2006.257.15:30:25.74$ifdk4/lo= 2006.257.15:30:25.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:30:25.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:30:25.74$ifdk4/patch= 2006.257.15:30:25.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:30:25.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:30:25.74$setupk4/!*+20s 2006.257.15:30:34.09#abcon#<5=/14 1.1 2.2 17.48 961013.9\r\n> 2006.257.15:30:34.11#abcon#{5=INTERFACE CLEAR} 2006.257.15:30:34.17#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:30:40.25$setupk4/"tpicd 2006.257.15:30:40.25$setupk4/echo=off 2006.257.15:30:40.25$setupk4/xlog=off 2006.257.15:30:40.25:!2006.257.15:31:30 2006.257.15:30:45.14#trakl#Source acquired 2006.257.15:30:45.14#flagr#flagr/antenna,acquired 2006.257.15:31:30.00:preob 2006.257.15:31:31.14/onsource/TRACKING 2006.257.15:31:31.14:!2006.257.15:31:40 2006.257.15:31:40.00:"tape 2006.257.15:31:40.00:"st=record 2006.257.15:31:40.00:data_valid=on 2006.257.15:31:40.00:midob 2006.257.15:31:40.14/onsource/TRACKING 2006.257.15:31:40.14/wx/17.47,1013.9,96 2006.257.15:31:40.23/cable/+6.4843E-03 2006.257.15:31:41.32/va/01,08,usb,yes,48,51 2006.257.15:31:41.32/va/02,07,usb,yes,51,52 2006.257.15:31:41.32/va/03,08,usb,yes,46,49 2006.257.15:31:41.32/va/04,07,usb,yes,53,55 2006.257.15:31:41.32/va/05,04,usb,yes,47,48 2006.257.15:31:41.32/va/06,04,usb,yes,52,52 2006.257.15:31:41.32/va/07,04,usb,yes,53,54 2006.257.15:31:41.32/va/08,04,usb,yes,45,54 2006.257.15:31:41.55/valo/01,524.99,yes,locked 2006.257.15:31:41.55/valo/02,534.99,yes,locked 2006.257.15:31:41.55/valo/03,564.99,yes,locked 2006.257.15:31:41.55/valo/04,624.99,yes,locked 2006.257.15:31:41.55/valo/05,734.99,yes,locked 2006.257.15:31:41.55/valo/06,814.99,yes,locked 2006.257.15:31:41.55/valo/07,864.99,yes,locked 2006.257.15:31:41.55/valo/08,884.99,yes,locked 2006.257.15:31:42.64/vb/01,04,usb,yes,46,43 2006.257.15:31:42.64/vb/02,05,usb,yes,43,43 2006.257.15:31:42.64/vb/03,04,usb,yes,45,49 2006.257.15:31:42.64/vb/04,05,usb,yes,45,44 2006.257.15:31:42.64/vb/05,04,usb,yes,41,44 2006.257.15:31:42.64/vb/06,04,usb,yes,47,42 2006.257.15:31:42.64/vb/07,04,usb,yes,46,47 2006.257.15:31:42.64/vb/08,04,usb,yes,42,47 2006.257.15:31:42.88/vblo/01,629.99,yes,locked 2006.257.15:31:42.88/vblo/02,634.99,yes,locked 2006.257.15:31:42.88/vblo/03,649.99,yes,locked 2006.257.15:31:42.88/vblo/04,679.99,yes,locked 2006.257.15:31:42.88/vblo/05,709.99,yes,locked 2006.257.15:31:42.88/vblo/06,719.99,yes,locked 2006.257.15:31:42.88/vblo/07,734.99,yes,locked 2006.257.15:31:42.88/vblo/08,744.99,yes,locked 2006.257.15:31:43.03/vabw/8 2006.257.15:31:43.18/vbbw/8 2006.257.15:31:43.27/xfe/off,on,15.2 2006.257.15:31:43.65/ifatt/23,28,28,28 2006.257.15:31:44.07/fmout-gps/S +4.58E-07 2006.257.15:31:44.11:!2006.257.15:32:30 2006.257.15:32:30.00:data_valid=off 2006.257.15:32:30.00:"et 2006.257.15:32:30.00:!+3s 2006.257.15:32:33.02:"tape 2006.257.15:32:33.02:postob 2006.257.15:32:33.13/cable/+6.4857E-03 2006.257.15:32:33.13/wx/17.46,1013.9,96 2006.257.15:32:33.19/fmout-gps/S +4.57E-07 2006.257.15:32:33.19:scan_name=257-1534,jd0609,80 2006.257.15:32:33.19:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.15:32:34.14#flagr#flagr/antenna,new-source 2006.257.15:32:34.14:checkk5 2006.257.15:32:34.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:32:34.89/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:32:35.33/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:32:35.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:32:36.11/chk_obsdata//k5ts1/T2571531??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.15:32:36.51/chk_obsdata//k5ts2/T2571531??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.15:32:36.92/chk_obsdata//k5ts3/T2571531??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.15:32:37.31/chk_obsdata//k5ts4/T2571531??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.15:32:38.03/k5log//k5ts1_log_newline 2006.257.15:32:38.72/k5log//k5ts2_log_newline 2006.257.15:32:39.42/k5log//k5ts3_log_newline 2006.257.15:32:40.13/k5log//k5ts4_log_newline 2006.257.15:32:40.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:32:40.15:setupk4=1 2006.257.15:32:40.15$setupk4/echo=on 2006.257.15:32:40.15$setupk4/pcalon 2006.257.15:32:40.15$pcalon/"no phase cal control is implemented here 2006.257.15:32:40.16$setupk4/"tpicd=stop 2006.257.15:32:40.16$setupk4/"rec=synch_on 2006.257.15:32:40.16$setupk4/"rec_mode=128 2006.257.15:32:40.16$setupk4/!* 2006.257.15:32:40.16$setupk4/recpk4 2006.257.15:32:40.16$recpk4/recpatch= 2006.257.15:32:40.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:32:40.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:32:40.16$setupk4/vck44 2006.257.15:32:40.16$vck44/valo=1,524.99 2006.257.15:32:40.16#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.15:32:40.16#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.15:32:40.16#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:40.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:40.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:40.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:40.16#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:32:40.16#ibcon#first serial, iclass 40, count 0 2006.257.15:32:40.16#ibcon#enter sib2, iclass 40, count 0 2006.257.15:32:40.16#ibcon#flushed, iclass 40, count 0 2006.257.15:32:40.16#ibcon#about to write, iclass 40, count 0 2006.257.15:32:40.16#ibcon#wrote, iclass 40, count 0 2006.257.15:32:40.16#ibcon#about to read 3, iclass 40, count 0 2006.257.15:32:40.18#ibcon#read 3, iclass 40, count 0 2006.257.15:32:40.18#ibcon#about to read 4, iclass 40, count 0 2006.257.15:32:40.18#ibcon#read 4, iclass 40, count 0 2006.257.15:32:40.18#ibcon#about to read 5, iclass 40, count 0 2006.257.15:32:40.18#ibcon#read 5, iclass 40, count 0 2006.257.15:32:40.18#ibcon#about to read 6, iclass 40, count 0 2006.257.15:32:40.18#ibcon#read 6, iclass 40, count 0 2006.257.15:32:40.18#ibcon#end of sib2, iclass 40, count 0 2006.257.15:32:40.18#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:32:40.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:32:40.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:32:40.18#ibcon#*before write, iclass 40, count 0 2006.257.15:32:40.18#ibcon#enter sib2, iclass 40, count 0 2006.257.15:32:40.18#ibcon#flushed, iclass 40, count 0 2006.257.15:32:40.18#ibcon#about to write, iclass 40, count 0 2006.257.15:32:40.18#ibcon#wrote, iclass 40, count 0 2006.257.15:32:40.18#ibcon#about to read 3, iclass 40, count 0 2006.257.15:32:40.23#ibcon#read 3, iclass 40, count 0 2006.257.15:32:40.23#ibcon#about to read 4, iclass 40, count 0 2006.257.15:32:40.23#ibcon#read 4, iclass 40, count 0 2006.257.15:32:40.23#ibcon#about to read 5, iclass 40, count 0 2006.257.15:32:40.23#ibcon#read 5, iclass 40, count 0 2006.257.15:32:40.23#ibcon#about to read 6, iclass 40, count 0 2006.257.15:32:40.23#ibcon#read 6, iclass 40, count 0 2006.257.15:32:40.23#ibcon#end of sib2, iclass 40, count 0 2006.257.15:32:40.23#ibcon#*after write, iclass 40, count 0 2006.257.15:32:40.23#ibcon#*before return 0, iclass 40, count 0 2006.257.15:32:40.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:40.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:40.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:32:40.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:32:40.23$vck44/va=1,8 2006.257.15:32:40.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.15:32:40.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.15:32:40.23#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:40.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:40.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:40.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:40.23#ibcon#enter wrdev, iclass 4, count 2 2006.257.15:32:40.23#ibcon#first serial, iclass 4, count 2 2006.257.15:32:40.23#ibcon#enter sib2, iclass 4, count 2 2006.257.15:32:40.23#ibcon#flushed, iclass 4, count 2 2006.257.15:32:40.23#ibcon#about to write, iclass 4, count 2 2006.257.15:32:40.23#ibcon#wrote, iclass 4, count 2 2006.257.15:32:40.23#ibcon#about to read 3, iclass 4, count 2 2006.257.15:32:40.25#ibcon#read 3, iclass 4, count 2 2006.257.15:32:40.25#ibcon#about to read 4, iclass 4, count 2 2006.257.15:32:40.25#ibcon#read 4, iclass 4, count 2 2006.257.15:32:40.25#ibcon#about to read 5, iclass 4, count 2 2006.257.15:32:40.25#ibcon#read 5, iclass 4, count 2 2006.257.15:32:40.25#ibcon#about to read 6, iclass 4, count 2 2006.257.15:32:40.25#ibcon#read 6, iclass 4, count 2 2006.257.15:32:40.25#ibcon#end of sib2, iclass 4, count 2 2006.257.15:32:40.25#ibcon#*mode == 0, iclass 4, count 2 2006.257.15:32:40.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.15:32:40.25#ibcon#[25=AT01-08\r\n] 2006.257.15:32:40.25#ibcon#*before write, iclass 4, count 2 2006.257.15:32:40.25#ibcon#enter sib2, iclass 4, count 2 2006.257.15:32:40.25#ibcon#flushed, iclass 4, count 2 2006.257.15:32:40.25#ibcon#about to write, iclass 4, count 2 2006.257.15:32:40.25#ibcon#wrote, iclass 4, count 2 2006.257.15:32:40.25#ibcon#about to read 3, iclass 4, count 2 2006.257.15:32:40.28#ibcon#read 3, iclass 4, count 2 2006.257.15:32:40.28#ibcon#about to read 4, iclass 4, count 2 2006.257.15:32:40.28#ibcon#read 4, iclass 4, count 2 2006.257.15:32:40.28#ibcon#about to read 5, iclass 4, count 2 2006.257.15:32:40.28#ibcon#read 5, iclass 4, count 2 2006.257.15:32:40.28#ibcon#about to read 6, iclass 4, count 2 2006.257.15:32:40.28#ibcon#read 6, iclass 4, count 2 2006.257.15:32:40.28#ibcon#end of sib2, iclass 4, count 2 2006.257.15:32:40.28#ibcon#*after write, iclass 4, count 2 2006.257.15:32:40.28#ibcon#*before return 0, iclass 4, count 2 2006.257.15:32:40.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:40.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:40.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.15:32:40.28#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:40.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:40.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:40.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:40.40#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:32:40.40#ibcon#first serial, iclass 4, count 0 2006.257.15:32:40.40#ibcon#enter sib2, iclass 4, count 0 2006.257.15:32:40.40#ibcon#flushed, iclass 4, count 0 2006.257.15:32:40.40#ibcon#about to write, iclass 4, count 0 2006.257.15:32:40.40#ibcon#wrote, iclass 4, count 0 2006.257.15:32:40.40#ibcon#about to read 3, iclass 4, count 0 2006.257.15:32:40.42#ibcon#read 3, iclass 4, count 0 2006.257.15:32:40.42#ibcon#about to read 4, iclass 4, count 0 2006.257.15:32:40.42#ibcon#read 4, iclass 4, count 0 2006.257.15:32:40.42#ibcon#about to read 5, iclass 4, count 0 2006.257.15:32:40.42#ibcon#read 5, iclass 4, count 0 2006.257.15:32:40.42#ibcon#about to read 6, iclass 4, count 0 2006.257.15:32:40.42#ibcon#read 6, iclass 4, count 0 2006.257.15:32:40.42#ibcon#end of sib2, iclass 4, count 0 2006.257.15:32:40.42#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:32:40.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:32:40.42#ibcon#[25=USB\r\n] 2006.257.15:32:40.42#ibcon#*before write, iclass 4, count 0 2006.257.15:32:40.42#ibcon#enter sib2, iclass 4, count 0 2006.257.15:32:40.42#ibcon#flushed, iclass 4, count 0 2006.257.15:32:40.42#ibcon#about to write, iclass 4, count 0 2006.257.15:32:40.42#ibcon#wrote, iclass 4, count 0 2006.257.15:32:40.42#ibcon#about to read 3, iclass 4, count 0 2006.257.15:32:40.45#ibcon#read 3, iclass 4, count 0 2006.257.15:32:40.45#ibcon#about to read 4, iclass 4, count 0 2006.257.15:32:40.45#ibcon#read 4, iclass 4, count 0 2006.257.15:32:40.45#ibcon#about to read 5, iclass 4, count 0 2006.257.15:32:40.45#ibcon#read 5, iclass 4, count 0 2006.257.15:32:40.45#ibcon#about to read 6, iclass 4, count 0 2006.257.15:32:40.45#ibcon#read 6, iclass 4, count 0 2006.257.15:32:40.45#ibcon#end of sib2, iclass 4, count 0 2006.257.15:32:40.45#ibcon#*after write, iclass 4, count 0 2006.257.15:32:40.45#ibcon#*before return 0, iclass 4, count 0 2006.257.15:32:40.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:40.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:40.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:32:40.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:32:40.45$vck44/valo=2,534.99 2006.257.15:32:40.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.15:32:40.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.15:32:40.45#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:40.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:40.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:40.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:40.45#ibcon#enter wrdev, iclass 6, count 0 2006.257.15:32:40.45#ibcon#first serial, iclass 6, count 0 2006.257.15:32:40.45#ibcon#enter sib2, iclass 6, count 0 2006.257.15:32:40.45#ibcon#flushed, iclass 6, count 0 2006.257.15:32:40.45#ibcon#about to write, iclass 6, count 0 2006.257.15:32:40.45#ibcon#wrote, iclass 6, count 0 2006.257.15:32:40.45#ibcon#about to read 3, iclass 6, count 0 2006.257.15:32:40.47#ibcon#read 3, iclass 6, count 0 2006.257.15:32:40.47#ibcon#about to read 4, iclass 6, count 0 2006.257.15:32:40.47#ibcon#read 4, iclass 6, count 0 2006.257.15:32:40.47#ibcon#about to read 5, iclass 6, count 0 2006.257.15:32:40.47#ibcon#read 5, iclass 6, count 0 2006.257.15:32:40.47#ibcon#about to read 6, iclass 6, count 0 2006.257.15:32:40.47#ibcon#read 6, iclass 6, count 0 2006.257.15:32:40.47#ibcon#end of sib2, iclass 6, count 0 2006.257.15:32:40.47#ibcon#*mode == 0, iclass 6, count 0 2006.257.15:32:40.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.15:32:40.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:32:40.47#ibcon#*before write, iclass 6, count 0 2006.257.15:32:40.47#ibcon#enter sib2, iclass 6, count 0 2006.257.15:32:40.47#ibcon#flushed, iclass 6, count 0 2006.257.15:32:40.47#ibcon#about to write, iclass 6, count 0 2006.257.15:32:40.47#ibcon#wrote, iclass 6, count 0 2006.257.15:32:40.47#ibcon#about to read 3, iclass 6, count 0 2006.257.15:32:40.51#ibcon#read 3, iclass 6, count 0 2006.257.15:32:40.51#ibcon#about to read 4, iclass 6, count 0 2006.257.15:32:40.51#ibcon#read 4, iclass 6, count 0 2006.257.15:32:40.51#ibcon#about to read 5, iclass 6, count 0 2006.257.15:32:40.51#ibcon#read 5, iclass 6, count 0 2006.257.15:32:40.51#ibcon#about to read 6, iclass 6, count 0 2006.257.15:32:40.51#ibcon#read 6, iclass 6, count 0 2006.257.15:32:40.51#ibcon#end of sib2, iclass 6, count 0 2006.257.15:32:40.51#ibcon#*after write, iclass 6, count 0 2006.257.15:32:40.51#ibcon#*before return 0, iclass 6, count 0 2006.257.15:32:40.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:40.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:40.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.15:32:40.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.15:32:40.51$vck44/va=2,7 2006.257.15:32:40.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.15:32:40.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.15:32:40.51#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:40.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:40.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:40.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:40.57#ibcon#enter wrdev, iclass 10, count 2 2006.257.15:32:40.57#ibcon#first serial, iclass 10, count 2 2006.257.15:32:40.57#ibcon#enter sib2, iclass 10, count 2 2006.257.15:32:40.57#ibcon#flushed, iclass 10, count 2 2006.257.15:32:40.57#ibcon#about to write, iclass 10, count 2 2006.257.15:32:40.57#ibcon#wrote, iclass 10, count 2 2006.257.15:32:40.57#ibcon#about to read 3, iclass 10, count 2 2006.257.15:32:40.59#ibcon#read 3, iclass 10, count 2 2006.257.15:32:40.59#ibcon#about to read 4, iclass 10, count 2 2006.257.15:32:40.59#ibcon#read 4, iclass 10, count 2 2006.257.15:32:40.59#ibcon#about to read 5, iclass 10, count 2 2006.257.15:32:40.59#ibcon#read 5, iclass 10, count 2 2006.257.15:32:40.59#ibcon#about to read 6, iclass 10, count 2 2006.257.15:32:40.59#ibcon#read 6, iclass 10, count 2 2006.257.15:32:40.59#ibcon#end of sib2, iclass 10, count 2 2006.257.15:32:40.59#ibcon#*mode == 0, iclass 10, count 2 2006.257.15:32:40.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.15:32:40.59#ibcon#[25=AT02-07\r\n] 2006.257.15:32:40.59#ibcon#*before write, iclass 10, count 2 2006.257.15:32:40.59#ibcon#enter sib2, iclass 10, count 2 2006.257.15:32:40.59#ibcon#flushed, iclass 10, count 2 2006.257.15:32:40.59#ibcon#about to write, iclass 10, count 2 2006.257.15:32:40.59#ibcon#wrote, iclass 10, count 2 2006.257.15:32:40.59#ibcon#about to read 3, iclass 10, count 2 2006.257.15:32:40.62#ibcon#read 3, iclass 10, count 2 2006.257.15:32:40.62#ibcon#about to read 4, iclass 10, count 2 2006.257.15:32:40.62#ibcon#read 4, iclass 10, count 2 2006.257.15:32:40.62#ibcon#about to read 5, iclass 10, count 2 2006.257.15:32:40.62#ibcon#read 5, iclass 10, count 2 2006.257.15:32:40.62#ibcon#about to read 6, iclass 10, count 2 2006.257.15:32:40.62#ibcon#read 6, iclass 10, count 2 2006.257.15:32:40.62#ibcon#end of sib2, iclass 10, count 2 2006.257.15:32:40.62#ibcon#*after write, iclass 10, count 2 2006.257.15:32:40.62#ibcon#*before return 0, iclass 10, count 2 2006.257.15:32:40.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:40.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:40.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.15:32:40.62#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:40.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:40.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:40.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:40.74#ibcon#enter wrdev, iclass 10, count 0 2006.257.15:32:40.74#ibcon#first serial, iclass 10, count 0 2006.257.15:32:40.74#ibcon#enter sib2, iclass 10, count 0 2006.257.15:32:40.74#ibcon#flushed, iclass 10, count 0 2006.257.15:32:40.74#ibcon#about to write, iclass 10, count 0 2006.257.15:32:40.74#ibcon#wrote, iclass 10, count 0 2006.257.15:32:40.74#ibcon#about to read 3, iclass 10, count 0 2006.257.15:32:40.76#ibcon#read 3, iclass 10, count 0 2006.257.15:32:40.76#ibcon#about to read 4, iclass 10, count 0 2006.257.15:32:40.76#ibcon#read 4, iclass 10, count 0 2006.257.15:32:40.76#ibcon#about to read 5, iclass 10, count 0 2006.257.15:32:40.76#ibcon#read 5, iclass 10, count 0 2006.257.15:32:40.76#ibcon#about to read 6, iclass 10, count 0 2006.257.15:32:40.76#ibcon#read 6, iclass 10, count 0 2006.257.15:32:40.76#ibcon#end of sib2, iclass 10, count 0 2006.257.15:32:40.76#ibcon#*mode == 0, iclass 10, count 0 2006.257.15:32:40.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.15:32:40.76#ibcon#[25=USB\r\n] 2006.257.15:32:40.76#ibcon#*before write, iclass 10, count 0 2006.257.15:32:40.76#ibcon#enter sib2, iclass 10, count 0 2006.257.15:32:40.76#ibcon#flushed, iclass 10, count 0 2006.257.15:32:40.76#ibcon#about to write, iclass 10, count 0 2006.257.15:32:40.76#ibcon#wrote, iclass 10, count 0 2006.257.15:32:40.76#ibcon#about to read 3, iclass 10, count 0 2006.257.15:32:40.79#ibcon#read 3, iclass 10, count 0 2006.257.15:32:40.79#ibcon#about to read 4, iclass 10, count 0 2006.257.15:32:40.79#ibcon#read 4, iclass 10, count 0 2006.257.15:32:40.79#ibcon#about to read 5, iclass 10, count 0 2006.257.15:32:40.79#ibcon#read 5, iclass 10, count 0 2006.257.15:32:40.79#ibcon#about to read 6, iclass 10, count 0 2006.257.15:32:40.79#ibcon#read 6, iclass 10, count 0 2006.257.15:32:40.79#ibcon#end of sib2, iclass 10, count 0 2006.257.15:32:40.79#ibcon#*after write, iclass 10, count 0 2006.257.15:32:40.79#ibcon#*before return 0, iclass 10, count 0 2006.257.15:32:40.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:40.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:40.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.15:32:40.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.15:32:40.79$vck44/valo=3,564.99 2006.257.15:32:40.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.15:32:40.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.15:32:40.79#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:40.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:40.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:40.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:40.79#ibcon#enter wrdev, iclass 12, count 0 2006.257.15:32:40.79#ibcon#first serial, iclass 12, count 0 2006.257.15:32:40.79#ibcon#enter sib2, iclass 12, count 0 2006.257.15:32:40.79#ibcon#flushed, iclass 12, count 0 2006.257.15:32:40.79#ibcon#about to write, iclass 12, count 0 2006.257.15:32:40.79#ibcon#wrote, iclass 12, count 0 2006.257.15:32:40.79#ibcon#about to read 3, iclass 12, count 0 2006.257.15:32:40.81#ibcon#read 3, iclass 12, count 0 2006.257.15:32:40.81#ibcon#about to read 4, iclass 12, count 0 2006.257.15:32:40.81#ibcon#read 4, iclass 12, count 0 2006.257.15:32:40.81#ibcon#about to read 5, iclass 12, count 0 2006.257.15:32:40.81#ibcon#read 5, iclass 12, count 0 2006.257.15:32:40.81#ibcon#about to read 6, iclass 12, count 0 2006.257.15:32:40.81#ibcon#read 6, iclass 12, count 0 2006.257.15:32:40.81#ibcon#end of sib2, iclass 12, count 0 2006.257.15:32:40.81#ibcon#*mode == 0, iclass 12, count 0 2006.257.15:32:40.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.15:32:40.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:32:40.81#ibcon#*before write, iclass 12, count 0 2006.257.15:32:40.81#ibcon#enter sib2, iclass 12, count 0 2006.257.15:32:40.81#ibcon#flushed, iclass 12, count 0 2006.257.15:32:40.81#ibcon#about to write, iclass 12, count 0 2006.257.15:32:40.81#ibcon#wrote, iclass 12, count 0 2006.257.15:32:40.81#ibcon#about to read 3, iclass 12, count 0 2006.257.15:32:40.85#ibcon#read 3, iclass 12, count 0 2006.257.15:32:40.85#ibcon#about to read 4, iclass 12, count 0 2006.257.15:32:40.85#ibcon#read 4, iclass 12, count 0 2006.257.15:32:40.85#ibcon#about to read 5, iclass 12, count 0 2006.257.15:32:40.85#ibcon#read 5, iclass 12, count 0 2006.257.15:32:40.85#ibcon#about to read 6, iclass 12, count 0 2006.257.15:32:40.85#ibcon#read 6, iclass 12, count 0 2006.257.15:32:40.85#ibcon#end of sib2, iclass 12, count 0 2006.257.15:32:40.85#ibcon#*after write, iclass 12, count 0 2006.257.15:32:40.85#ibcon#*before return 0, iclass 12, count 0 2006.257.15:32:40.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:40.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:40.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.15:32:40.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.15:32:40.85$vck44/va=3,8 2006.257.15:32:40.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.15:32:40.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.15:32:40.85#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:40.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:40.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:40.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:40.91#ibcon#enter wrdev, iclass 14, count 2 2006.257.15:32:40.91#ibcon#first serial, iclass 14, count 2 2006.257.15:32:40.91#ibcon#enter sib2, iclass 14, count 2 2006.257.15:32:40.91#ibcon#flushed, iclass 14, count 2 2006.257.15:32:40.91#ibcon#about to write, iclass 14, count 2 2006.257.15:32:40.91#ibcon#wrote, iclass 14, count 2 2006.257.15:32:40.91#ibcon#about to read 3, iclass 14, count 2 2006.257.15:32:40.93#ibcon#read 3, iclass 14, count 2 2006.257.15:32:40.93#ibcon#about to read 4, iclass 14, count 2 2006.257.15:32:40.93#ibcon#read 4, iclass 14, count 2 2006.257.15:32:40.93#ibcon#about to read 5, iclass 14, count 2 2006.257.15:32:40.93#ibcon#read 5, iclass 14, count 2 2006.257.15:32:40.93#ibcon#about to read 6, iclass 14, count 2 2006.257.15:32:40.93#ibcon#read 6, iclass 14, count 2 2006.257.15:32:40.93#ibcon#end of sib2, iclass 14, count 2 2006.257.15:32:40.93#ibcon#*mode == 0, iclass 14, count 2 2006.257.15:32:40.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.15:32:40.93#ibcon#[25=AT03-08\r\n] 2006.257.15:32:40.93#ibcon#*before write, iclass 14, count 2 2006.257.15:32:40.93#ibcon#enter sib2, iclass 14, count 2 2006.257.15:32:40.93#ibcon#flushed, iclass 14, count 2 2006.257.15:32:40.93#ibcon#about to write, iclass 14, count 2 2006.257.15:32:40.93#ibcon#wrote, iclass 14, count 2 2006.257.15:32:40.93#ibcon#about to read 3, iclass 14, count 2 2006.257.15:32:40.96#ibcon#read 3, iclass 14, count 2 2006.257.15:32:40.96#ibcon#about to read 4, iclass 14, count 2 2006.257.15:32:40.96#ibcon#read 4, iclass 14, count 2 2006.257.15:32:40.96#ibcon#about to read 5, iclass 14, count 2 2006.257.15:32:40.96#ibcon#read 5, iclass 14, count 2 2006.257.15:32:40.96#ibcon#about to read 6, iclass 14, count 2 2006.257.15:32:40.96#ibcon#read 6, iclass 14, count 2 2006.257.15:32:40.96#ibcon#end of sib2, iclass 14, count 2 2006.257.15:32:40.96#ibcon#*after write, iclass 14, count 2 2006.257.15:32:40.96#ibcon#*before return 0, iclass 14, count 2 2006.257.15:32:40.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:40.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:40.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.15:32:40.96#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:40.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:41.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:41.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:41.08#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:32:41.08#ibcon#first serial, iclass 14, count 0 2006.257.15:32:41.08#ibcon#enter sib2, iclass 14, count 0 2006.257.15:32:41.08#ibcon#flushed, iclass 14, count 0 2006.257.15:32:41.08#ibcon#about to write, iclass 14, count 0 2006.257.15:32:41.08#ibcon#wrote, iclass 14, count 0 2006.257.15:32:41.08#ibcon#about to read 3, iclass 14, count 0 2006.257.15:32:41.10#ibcon#read 3, iclass 14, count 0 2006.257.15:32:41.10#ibcon#about to read 4, iclass 14, count 0 2006.257.15:32:41.10#ibcon#read 4, iclass 14, count 0 2006.257.15:32:41.10#ibcon#about to read 5, iclass 14, count 0 2006.257.15:32:41.10#ibcon#read 5, iclass 14, count 0 2006.257.15:32:41.10#ibcon#about to read 6, iclass 14, count 0 2006.257.15:32:41.10#ibcon#read 6, iclass 14, count 0 2006.257.15:32:41.10#ibcon#end of sib2, iclass 14, count 0 2006.257.15:32:41.10#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:32:41.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:32:41.10#ibcon#[25=USB\r\n] 2006.257.15:32:41.10#ibcon#*before write, iclass 14, count 0 2006.257.15:32:41.10#ibcon#enter sib2, iclass 14, count 0 2006.257.15:32:41.10#ibcon#flushed, iclass 14, count 0 2006.257.15:32:41.10#ibcon#about to write, iclass 14, count 0 2006.257.15:32:41.10#ibcon#wrote, iclass 14, count 0 2006.257.15:32:41.10#ibcon#about to read 3, iclass 14, count 0 2006.257.15:32:41.13#ibcon#read 3, iclass 14, count 0 2006.257.15:32:41.13#ibcon#about to read 4, iclass 14, count 0 2006.257.15:32:41.13#ibcon#read 4, iclass 14, count 0 2006.257.15:32:41.13#ibcon#about to read 5, iclass 14, count 0 2006.257.15:32:41.13#ibcon#read 5, iclass 14, count 0 2006.257.15:32:41.13#ibcon#about to read 6, iclass 14, count 0 2006.257.15:32:41.13#ibcon#read 6, iclass 14, count 0 2006.257.15:32:41.13#ibcon#end of sib2, iclass 14, count 0 2006.257.15:32:41.13#ibcon#*after write, iclass 14, count 0 2006.257.15:32:41.13#ibcon#*before return 0, iclass 14, count 0 2006.257.15:32:41.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:41.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:41.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:32:41.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:32:41.13$vck44/valo=4,624.99 2006.257.15:32:41.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.15:32:41.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.15:32:41.13#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:41.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:41.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:41.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:41.13#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:32:41.13#ibcon#first serial, iclass 16, count 0 2006.257.15:32:41.13#ibcon#enter sib2, iclass 16, count 0 2006.257.15:32:41.13#ibcon#flushed, iclass 16, count 0 2006.257.15:32:41.13#ibcon#about to write, iclass 16, count 0 2006.257.15:32:41.13#ibcon#wrote, iclass 16, count 0 2006.257.15:32:41.13#ibcon#about to read 3, iclass 16, count 0 2006.257.15:32:41.15#ibcon#read 3, iclass 16, count 0 2006.257.15:32:41.15#ibcon#about to read 4, iclass 16, count 0 2006.257.15:32:41.15#ibcon#read 4, iclass 16, count 0 2006.257.15:32:41.15#ibcon#about to read 5, iclass 16, count 0 2006.257.15:32:41.15#ibcon#read 5, iclass 16, count 0 2006.257.15:32:41.15#ibcon#about to read 6, iclass 16, count 0 2006.257.15:32:41.15#ibcon#read 6, iclass 16, count 0 2006.257.15:32:41.15#ibcon#end of sib2, iclass 16, count 0 2006.257.15:32:41.15#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:32:41.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:32:41.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:32:41.15#ibcon#*before write, iclass 16, count 0 2006.257.15:32:41.15#ibcon#enter sib2, iclass 16, count 0 2006.257.15:32:41.15#ibcon#flushed, iclass 16, count 0 2006.257.15:32:41.15#ibcon#about to write, iclass 16, count 0 2006.257.15:32:41.15#ibcon#wrote, iclass 16, count 0 2006.257.15:32:41.15#ibcon#about to read 3, iclass 16, count 0 2006.257.15:32:41.19#ibcon#read 3, iclass 16, count 0 2006.257.15:32:41.19#ibcon#about to read 4, iclass 16, count 0 2006.257.15:32:41.19#ibcon#read 4, iclass 16, count 0 2006.257.15:32:41.19#ibcon#about to read 5, iclass 16, count 0 2006.257.15:32:41.19#ibcon#read 5, iclass 16, count 0 2006.257.15:32:41.19#ibcon#about to read 6, iclass 16, count 0 2006.257.15:32:41.19#ibcon#read 6, iclass 16, count 0 2006.257.15:32:41.19#ibcon#end of sib2, iclass 16, count 0 2006.257.15:32:41.19#ibcon#*after write, iclass 16, count 0 2006.257.15:32:41.19#ibcon#*before return 0, iclass 16, count 0 2006.257.15:32:41.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:41.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:41.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:32:41.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:32:41.19$vck44/va=4,7 2006.257.15:32:41.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.15:32:41.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.15:32:41.19#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:41.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:41.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:41.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:41.25#ibcon#enter wrdev, iclass 18, count 2 2006.257.15:32:41.25#ibcon#first serial, iclass 18, count 2 2006.257.15:32:41.25#ibcon#enter sib2, iclass 18, count 2 2006.257.15:32:41.25#ibcon#flushed, iclass 18, count 2 2006.257.15:32:41.25#ibcon#about to write, iclass 18, count 2 2006.257.15:32:41.25#ibcon#wrote, iclass 18, count 2 2006.257.15:32:41.25#ibcon#about to read 3, iclass 18, count 2 2006.257.15:32:41.27#ibcon#read 3, iclass 18, count 2 2006.257.15:32:41.27#ibcon#about to read 4, iclass 18, count 2 2006.257.15:32:41.27#ibcon#read 4, iclass 18, count 2 2006.257.15:32:41.27#ibcon#about to read 5, iclass 18, count 2 2006.257.15:32:41.27#ibcon#read 5, iclass 18, count 2 2006.257.15:32:41.27#ibcon#about to read 6, iclass 18, count 2 2006.257.15:32:41.27#ibcon#read 6, iclass 18, count 2 2006.257.15:32:41.27#ibcon#end of sib2, iclass 18, count 2 2006.257.15:32:41.27#ibcon#*mode == 0, iclass 18, count 2 2006.257.15:32:41.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.15:32:41.27#ibcon#[25=AT04-07\r\n] 2006.257.15:32:41.27#ibcon#*before write, iclass 18, count 2 2006.257.15:32:41.27#ibcon#enter sib2, iclass 18, count 2 2006.257.15:32:41.27#ibcon#flushed, iclass 18, count 2 2006.257.15:32:41.27#ibcon#about to write, iclass 18, count 2 2006.257.15:32:41.27#ibcon#wrote, iclass 18, count 2 2006.257.15:32:41.27#ibcon#about to read 3, iclass 18, count 2 2006.257.15:32:41.30#ibcon#read 3, iclass 18, count 2 2006.257.15:32:41.30#ibcon#about to read 4, iclass 18, count 2 2006.257.15:32:41.30#ibcon#read 4, iclass 18, count 2 2006.257.15:32:41.30#ibcon#about to read 5, iclass 18, count 2 2006.257.15:32:41.30#ibcon#read 5, iclass 18, count 2 2006.257.15:32:41.30#ibcon#about to read 6, iclass 18, count 2 2006.257.15:32:41.30#ibcon#read 6, iclass 18, count 2 2006.257.15:32:41.30#ibcon#end of sib2, iclass 18, count 2 2006.257.15:32:41.30#ibcon#*after write, iclass 18, count 2 2006.257.15:32:41.30#ibcon#*before return 0, iclass 18, count 2 2006.257.15:32:41.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:41.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:41.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.15:32:41.30#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:41.30#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:41.42#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:41.42#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:41.42#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:32:41.42#ibcon#first serial, iclass 18, count 0 2006.257.15:32:41.42#ibcon#enter sib2, iclass 18, count 0 2006.257.15:32:41.42#ibcon#flushed, iclass 18, count 0 2006.257.15:32:41.42#ibcon#about to write, iclass 18, count 0 2006.257.15:32:41.42#ibcon#wrote, iclass 18, count 0 2006.257.15:32:41.42#ibcon#about to read 3, iclass 18, count 0 2006.257.15:32:41.44#ibcon#read 3, iclass 18, count 0 2006.257.15:32:41.44#ibcon#about to read 4, iclass 18, count 0 2006.257.15:32:41.44#ibcon#read 4, iclass 18, count 0 2006.257.15:32:41.44#ibcon#about to read 5, iclass 18, count 0 2006.257.15:32:41.44#ibcon#read 5, iclass 18, count 0 2006.257.15:32:41.44#ibcon#about to read 6, iclass 18, count 0 2006.257.15:32:41.44#ibcon#read 6, iclass 18, count 0 2006.257.15:32:41.44#ibcon#end of sib2, iclass 18, count 0 2006.257.15:32:41.44#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:32:41.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:32:41.44#ibcon#[25=USB\r\n] 2006.257.15:32:41.44#ibcon#*before write, iclass 18, count 0 2006.257.15:32:41.44#ibcon#enter sib2, iclass 18, count 0 2006.257.15:32:41.44#ibcon#flushed, iclass 18, count 0 2006.257.15:32:41.44#ibcon#about to write, iclass 18, count 0 2006.257.15:32:41.44#ibcon#wrote, iclass 18, count 0 2006.257.15:32:41.44#ibcon#about to read 3, iclass 18, count 0 2006.257.15:32:41.47#ibcon#read 3, iclass 18, count 0 2006.257.15:32:41.47#ibcon#about to read 4, iclass 18, count 0 2006.257.15:32:41.47#ibcon#read 4, iclass 18, count 0 2006.257.15:32:41.47#ibcon#about to read 5, iclass 18, count 0 2006.257.15:32:41.47#ibcon#read 5, iclass 18, count 0 2006.257.15:32:41.47#ibcon#about to read 6, iclass 18, count 0 2006.257.15:32:41.47#ibcon#read 6, iclass 18, count 0 2006.257.15:32:41.47#ibcon#end of sib2, iclass 18, count 0 2006.257.15:32:41.47#ibcon#*after write, iclass 18, count 0 2006.257.15:32:41.47#ibcon#*before return 0, iclass 18, count 0 2006.257.15:32:41.47#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:41.47#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:41.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:32:41.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:32:41.47$vck44/valo=5,734.99 2006.257.15:32:41.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.15:32:41.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.15:32:41.47#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:41.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:41.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:41.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:41.47#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:32:41.47#ibcon#first serial, iclass 20, count 0 2006.257.15:32:41.47#ibcon#enter sib2, iclass 20, count 0 2006.257.15:32:41.47#ibcon#flushed, iclass 20, count 0 2006.257.15:32:41.47#ibcon#about to write, iclass 20, count 0 2006.257.15:32:41.47#ibcon#wrote, iclass 20, count 0 2006.257.15:32:41.47#ibcon#about to read 3, iclass 20, count 0 2006.257.15:32:41.49#ibcon#read 3, iclass 20, count 0 2006.257.15:32:41.49#ibcon#about to read 4, iclass 20, count 0 2006.257.15:32:41.49#ibcon#read 4, iclass 20, count 0 2006.257.15:32:41.49#ibcon#about to read 5, iclass 20, count 0 2006.257.15:32:41.49#ibcon#read 5, iclass 20, count 0 2006.257.15:32:41.49#ibcon#about to read 6, iclass 20, count 0 2006.257.15:32:41.49#ibcon#read 6, iclass 20, count 0 2006.257.15:32:41.49#ibcon#end of sib2, iclass 20, count 0 2006.257.15:32:41.49#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:32:41.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:32:41.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:32:41.49#ibcon#*before write, iclass 20, count 0 2006.257.15:32:41.49#ibcon#enter sib2, iclass 20, count 0 2006.257.15:32:41.49#ibcon#flushed, iclass 20, count 0 2006.257.15:32:41.49#ibcon#about to write, iclass 20, count 0 2006.257.15:32:41.49#ibcon#wrote, iclass 20, count 0 2006.257.15:32:41.49#ibcon#about to read 3, iclass 20, count 0 2006.257.15:32:41.53#ibcon#read 3, iclass 20, count 0 2006.257.15:32:41.53#ibcon#about to read 4, iclass 20, count 0 2006.257.15:32:41.53#ibcon#read 4, iclass 20, count 0 2006.257.15:32:41.53#ibcon#about to read 5, iclass 20, count 0 2006.257.15:32:41.53#ibcon#read 5, iclass 20, count 0 2006.257.15:32:41.53#ibcon#about to read 6, iclass 20, count 0 2006.257.15:32:41.53#ibcon#read 6, iclass 20, count 0 2006.257.15:32:41.53#ibcon#end of sib2, iclass 20, count 0 2006.257.15:32:41.53#ibcon#*after write, iclass 20, count 0 2006.257.15:32:41.53#ibcon#*before return 0, iclass 20, count 0 2006.257.15:32:41.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:41.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:41.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:32:41.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:32:41.53$vck44/va=5,4 2006.257.15:32:41.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.15:32:41.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.15:32:41.53#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:41.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:41.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:41.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:41.59#ibcon#enter wrdev, iclass 22, count 2 2006.257.15:32:41.59#ibcon#first serial, iclass 22, count 2 2006.257.15:32:41.59#ibcon#enter sib2, iclass 22, count 2 2006.257.15:32:41.59#ibcon#flushed, iclass 22, count 2 2006.257.15:32:41.59#ibcon#about to write, iclass 22, count 2 2006.257.15:32:41.59#ibcon#wrote, iclass 22, count 2 2006.257.15:32:41.59#ibcon#about to read 3, iclass 22, count 2 2006.257.15:32:41.61#ibcon#read 3, iclass 22, count 2 2006.257.15:32:41.61#ibcon#about to read 4, iclass 22, count 2 2006.257.15:32:41.61#ibcon#read 4, iclass 22, count 2 2006.257.15:32:41.61#ibcon#about to read 5, iclass 22, count 2 2006.257.15:32:41.61#ibcon#read 5, iclass 22, count 2 2006.257.15:32:41.61#ibcon#about to read 6, iclass 22, count 2 2006.257.15:32:41.61#ibcon#read 6, iclass 22, count 2 2006.257.15:32:41.61#ibcon#end of sib2, iclass 22, count 2 2006.257.15:32:41.61#ibcon#*mode == 0, iclass 22, count 2 2006.257.15:32:41.61#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.15:32:41.61#ibcon#[25=AT05-04\r\n] 2006.257.15:32:41.61#ibcon#*before write, iclass 22, count 2 2006.257.15:32:41.61#ibcon#enter sib2, iclass 22, count 2 2006.257.15:32:41.61#ibcon#flushed, iclass 22, count 2 2006.257.15:32:41.61#ibcon#about to write, iclass 22, count 2 2006.257.15:32:41.61#ibcon#wrote, iclass 22, count 2 2006.257.15:32:41.61#ibcon#about to read 3, iclass 22, count 2 2006.257.15:32:41.64#ibcon#read 3, iclass 22, count 2 2006.257.15:32:41.64#ibcon#about to read 4, iclass 22, count 2 2006.257.15:32:41.64#ibcon#read 4, iclass 22, count 2 2006.257.15:32:41.64#ibcon#about to read 5, iclass 22, count 2 2006.257.15:32:41.64#ibcon#read 5, iclass 22, count 2 2006.257.15:32:41.64#ibcon#about to read 6, iclass 22, count 2 2006.257.15:32:41.64#ibcon#read 6, iclass 22, count 2 2006.257.15:32:41.64#ibcon#end of sib2, iclass 22, count 2 2006.257.15:32:41.64#ibcon#*after write, iclass 22, count 2 2006.257.15:32:41.64#ibcon#*before return 0, iclass 22, count 2 2006.257.15:32:41.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:41.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:41.64#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.15:32:41.64#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:41.64#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:41.76#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:41.76#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:41.76#ibcon#enter wrdev, iclass 22, count 0 2006.257.15:32:41.76#ibcon#first serial, iclass 22, count 0 2006.257.15:32:41.76#ibcon#enter sib2, iclass 22, count 0 2006.257.15:32:41.76#ibcon#flushed, iclass 22, count 0 2006.257.15:32:41.76#ibcon#about to write, iclass 22, count 0 2006.257.15:32:41.76#ibcon#wrote, iclass 22, count 0 2006.257.15:32:41.76#ibcon#about to read 3, iclass 22, count 0 2006.257.15:32:41.78#ibcon#read 3, iclass 22, count 0 2006.257.15:32:41.78#ibcon#about to read 4, iclass 22, count 0 2006.257.15:32:41.78#ibcon#read 4, iclass 22, count 0 2006.257.15:32:41.78#ibcon#about to read 5, iclass 22, count 0 2006.257.15:32:41.78#ibcon#read 5, iclass 22, count 0 2006.257.15:32:41.78#ibcon#about to read 6, iclass 22, count 0 2006.257.15:32:41.78#ibcon#read 6, iclass 22, count 0 2006.257.15:32:41.78#ibcon#end of sib2, iclass 22, count 0 2006.257.15:32:41.78#ibcon#*mode == 0, iclass 22, count 0 2006.257.15:32:41.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.15:32:41.78#ibcon#[25=USB\r\n] 2006.257.15:32:41.78#ibcon#*before write, iclass 22, count 0 2006.257.15:32:41.78#ibcon#enter sib2, iclass 22, count 0 2006.257.15:32:41.78#ibcon#flushed, iclass 22, count 0 2006.257.15:32:41.78#ibcon#about to write, iclass 22, count 0 2006.257.15:32:41.78#ibcon#wrote, iclass 22, count 0 2006.257.15:32:41.78#ibcon#about to read 3, iclass 22, count 0 2006.257.15:32:41.81#ibcon#read 3, iclass 22, count 0 2006.257.15:32:41.81#ibcon#about to read 4, iclass 22, count 0 2006.257.15:32:41.81#ibcon#read 4, iclass 22, count 0 2006.257.15:32:41.81#ibcon#about to read 5, iclass 22, count 0 2006.257.15:32:41.81#ibcon#read 5, iclass 22, count 0 2006.257.15:32:41.81#ibcon#about to read 6, iclass 22, count 0 2006.257.15:32:41.81#ibcon#read 6, iclass 22, count 0 2006.257.15:32:41.81#ibcon#end of sib2, iclass 22, count 0 2006.257.15:32:41.81#ibcon#*after write, iclass 22, count 0 2006.257.15:32:41.81#ibcon#*before return 0, iclass 22, count 0 2006.257.15:32:41.81#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:41.81#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:41.81#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.15:32:41.81#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.15:32:41.81$vck44/valo=6,814.99 2006.257.15:32:41.81#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.15:32:41.81#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.15:32:41.81#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:41.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:41.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:41.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:41.81#ibcon#enter wrdev, iclass 24, count 0 2006.257.15:32:41.81#ibcon#first serial, iclass 24, count 0 2006.257.15:32:41.81#ibcon#enter sib2, iclass 24, count 0 2006.257.15:32:41.81#ibcon#flushed, iclass 24, count 0 2006.257.15:32:41.81#ibcon#about to write, iclass 24, count 0 2006.257.15:32:41.81#ibcon#wrote, iclass 24, count 0 2006.257.15:32:41.81#ibcon#about to read 3, iclass 24, count 0 2006.257.15:32:41.83#ibcon#read 3, iclass 24, count 0 2006.257.15:32:41.83#ibcon#about to read 4, iclass 24, count 0 2006.257.15:32:41.83#ibcon#read 4, iclass 24, count 0 2006.257.15:32:41.83#ibcon#about to read 5, iclass 24, count 0 2006.257.15:32:41.83#ibcon#read 5, iclass 24, count 0 2006.257.15:32:41.83#ibcon#about to read 6, iclass 24, count 0 2006.257.15:32:41.83#ibcon#read 6, iclass 24, count 0 2006.257.15:32:41.83#ibcon#end of sib2, iclass 24, count 0 2006.257.15:32:41.83#ibcon#*mode == 0, iclass 24, count 0 2006.257.15:32:41.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.15:32:41.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:32:41.83#ibcon#*before write, iclass 24, count 0 2006.257.15:32:41.83#ibcon#enter sib2, iclass 24, count 0 2006.257.15:32:41.83#ibcon#flushed, iclass 24, count 0 2006.257.15:32:41.83#ibcon#about to write, iclass 24, count 0 2006.257.15:32:41.83#ibcon#wrote, iclass 24, count 0 2006.257.15:32:41.83#ibcon#about to read 3, iclass 24, count 0 2006.257.15:32:41.87#ibcon#read 3, iclass 24, count 0 2006.257.15:32:41.87#ibcon#about to read 4, iclass 24, count 0 2006.257.15:32:41.87#ibcon#read 4, iclass 24, count 0 2006.257.15:32:41.87#ibcon#about to read 5, iclass 24, count 0 2006.257.15:32:41.87#ibcon#read 5, iclass 24, count 0 2006.257.15:32:41.87#ibcon#about to read 6, iclass 24, count 0 2006.257.15:32:41.87#ibcon#read 6, iclass 24, count 0 2006.257.15:32:41.87#ibcon#end of sib2, iclass 24, count 0 2006.257.15:32:41.87#ibcon#*after write, iclass 24, count 0 2006.257.15:32:41.87#ibcon#*before return 0, iclass 24, count 0 2006.257.15:32:41.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:41.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:41.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.15:32:41.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.15:32:41.87$vck44/va=6,4 2006.257.15:32:41.87#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.15:32:41.87#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.15:32:41.87#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:41.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:41.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:41.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:41.93#ibcon#enter wrdev, iclass 26, count 2 2006.257.15:32:41.93#ibcon#first serial, iclass 26, count 2 2006.257.15:32:41.93#ibcon#enter sib2, iclass 26, count 2 2006.257.15:32:41.93#ibcon#flushed, iclass 26, count 2 2006.257.15:32:41.93#ibcon#about to write, iclass 26, count 2 2006.257.15:32:41.93#ibcon#wrote, iclass 26, count 2 2006.257.15:32:41.93#ibcon#about to read 3, iclass 26, count 2 2006.257.15:32:41.95#ibcon#read 3, iclass 26, count 2 2006.257.15:32:41.95#ibcon#about to read 4, iclass 26, count 2 2006.257.15:32:41.95#ibcon#read 4, iclass 26, count 2 2006.257.15:32:41.95#ibcon#about to read 5, iclass 26, count 2 2006.257.15:32:41.95#ibcon#read 5, iclass 26, count 2 2006.257.15:32:41.95#ibcon#about to read 6, iclass 26, count 2 2006.257.15:32:41.95#ibcon#read 6, iclass 26, count 2 2006.257.15:32:41.95#ibcon#end of sib2, iclass 26, count 2 2006.257.15:32:41.95#ibcon#*mode == 0, iclass 26, count 2 2006.257.15:32:41.95#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.15:32:41.95#ibcon#[25=AT06-04\r\n] 2006.257.15:32:41.95#ibcon#*before write, iclass 26, count 2 2006.257.15:32:41.95#ibcon#enter sib2, iclass 26, count 2 2006.257.15:32:41.95#ibcon#flushed, iclass 26, count 2 2006.257.15:32:41.95#ibcon#about to write, iclass 26, count 2 2006.257.15:32:41.95#ibcon#wrote, iclass 26, count 2 2006.257.15:32:41.95#ibcon#about to read 3, iclass 26, count 2 2006.257.15:32:41.98#ibcon#read 3, iclass 26, count 2 2006.257.15:32:41.98#ibcon#about to read 4, iclass 26, count 2 2006.257.15:32:41.98#ibcon#read 4, iclass 26, count 2 2006.257.15:32:41.98#ibcon#about to read 5, iclass 26, count 2 2006.257.15:32:41.98#ibcon#read 5, iclass 26, count 2 2006.257.15:32:41.98#ibcon#about to read 6, iclass 26, count 2 2006.257.15:32:41.98#ibcon#read 6, iclass 26, count 2 2006.257.15:32:41.98#ibcon#end of sib2, iclass 26, count 2 2006.257.15:32:41.98#ibcon#*after write, iclass 26, count 2 2006.257.15:32:41.98#ibcon#*before return 0, iclass 26, count 2 2006.257.15:32:41.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:41.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:41.98#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.15:32:41.98#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:41.98#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:42.10#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:42.10#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:42.10#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:32:42.10#ibcon#first serial, iclass 26, count 0 2006.257.15:32:42.10#ibcon#enter sib2, iclass 26, count 0 2006.257.15:32:42.10#ibcon#flushed, iclass 26, count 0 2006.257.15:32:42.10#ibcon#about to write, iclass 26, count 0 2006.257.15:32:42.10#ibcon#wrote, iclass 26, count 0 2006.257.15:32:42.10#ibcon#about to read 3, iclass 26, count 0 2006.257.15:32:42.12#ibcon#read 3, iclass 26, count 0 2006.257.15:32:42.12#ibcon#about to read 4, iclass 26, count 0 2006.257.15:32:42.12#ibcon#read 4, iclass 26, count 0 2006.257.15:32:42.12#ibcon#about to read 5, iclass 26, count 0 2006.257.15:32:42.12#ibcon#read 5, iclass 26, count 0 2006.257.15:32:42.12#ibcon#about to read 6, iclass 26, count 0 2006.257.15:32:42.12#ibcon#read 6, iclass 26, count 0 2006.257.15:32:42.12#ibcon#end of sib2, iclass 26, count 0 2006.257.15:32:42.12#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:32:42.12#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:32:42.12#ibcon#[25=USB\r\n] 2006.257.15:32:42.12#ibcon#*before write, iclass 26, count 0 2006.257.15:32:42.12#ibcon#enter sib2, iclass 26, count 0 2006.257.15:32:42.12#ibcon#flushed, iclass 26, count 0 2006.257.15:32:42.12#ibcon#about to write, iclass 26, count 0 2006.257.15:32:42.12#ibcon#wrote, iclass 26, count 0 2006.257.15:32:42.12#ibcon#about to read 3, iclass 26, count 0 2006.257.15:32:42.15#ibcon#read 3, iclass 26, count 0 2006.257.15:32:42.15#ibcon#about to read 4, iclass 26, count 0 2006.257.15:32:42.15#ibcon#read 4, iclass 26, count 0 2006.257.15:32:42.15#ibcon#about to read 5, iclass 26, count 0 2006.257.15:32:42.15#ibcon#read 5, iclass 26, count 0 2006.257.15:32:42.15#ibcon#about to read 6, iclass 26, count 0 2006.257.15:32:42.15#ibcon#read 6, iclass 26, count 0 2006.257.15:32:42.15#ibcon#end of sib2, iclass 26, count 0 2006.257.15:32:42.15#ibcon#*after write, iclass 26, count 0 2006.257.15:32:42.15#ibcon#*before return 0, iclass 26, count 0 2006.257.15:32:42.15#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:42.15#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:42.15#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:32:42.15#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:32:42.15$vck44/valo=7,864.99 2006.257.15:32:42.15#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.15:32:42.15#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.15:32:42.15#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:42.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:42.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:42.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:42.15#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:32:42.15#ibcon#first serial, iclass 28, count 0 2006.257.15:32:42.15#ibcon#enter sib2, iclass 28, count 0 2006.257.15:32:42.15#ibcon#flushed, iclass 28, count 0 2006.257.15:32:42.15#ibcon#about to write, iclass 28, count 0 2006.257.15:32:42.15#ibcon#wrote, iclass 28, count 0 2006.257.15:32:42.15#ibcon#about to read 3, iclass 28, count 0 2006.257.15:32:42.17#ibcon#read 3, iclass 28, count 0 2006.257.15:32:42.17#ibcon#about to read 4, iclass 28, count 0 2006.257.15:32:42.17#ibcon#read 4, iclass 28, count 0 2006.257.15:32:42.17#ibcon#about to read 5, iclass 28, count 0 2006.257.15:32:42.17#ibcon#read 5, iclass 28, count 0 2006.257.15:32:42.17#ibcon#about to read 6, iclass 28, count 0 2006.257.15:32:42.17#ibcon#read 6, iclass 28, count 0 2006.257.15:32:42.17#ibcon#end of sib2, iclass 28, count 0 2006.257.15:32:42.17#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:32:42.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:32:42.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:32:42.17#ibcon#*before write, iclass 28, count 0 2006.257.15:32:42.17#ibcon#enter sib2, iclass 28, count 0 2006.257.15:32:42.17#ibcon#flushed, iclass 28, count 0 2006.257.15:32:42.17#ibcon#about to write, iclass 28, count 0 2006.257.15:32:42.17#ibcon#wrote, iclass 28, count 0 2006.257.15:32:42.17#ibcon#about to read 3, iclass 28, count 0 2006.257.15:32:42.21#ibcon#read 3, iclass 28, count 0 2006.257.15:32:42.21#ibcon#about to read 4, iclass 28, count 0 2006.257.15:32:42.21#ibcon#read 4, iclass 28, count 0 2006.257.15:32:42.21#ibcon#about to read 5, iclass 28, count 0 2006.257.15:32:42.21#ibcon#read 5, iclass 28, count 0 2006.257.15:32:42.21#ibcon#about to read 6, iclass 28, count 0 2006.257.15:32:42.21#ibcon#read 6, iclass 28, count 0 2006.257.15:32:42.21#ibcon#end of sib2, iclass 28, count 0 2006.257.15:32:42.21#ibcon#*after write, iclass 28, count 0 2006.257.15:32:42.21#ibcon#*before return 0, iclass 28, count 0 2006.257.15:32:42.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:42.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:42.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:32:42.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:32:42.21$vck44/va=7,4 2006.257.15:32:42.21#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.15:32:42.21#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.15:32:42.21#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:42.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:42.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:42.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:42.27#ibcon#enter wrdev, iclass 30, count 2 2006.257.15:32:42.27#ibcon#first serial, iclass 30, count 2 2006.257.15:32:42.27#ibcon#enter sib2, iclass 30, count 2 2006.257.15:32:42.27#ibcon#flushed, iclass 30, count 2 2006.257.15:32:42.27#ibcon#about to write, iclass 30, count 2 2006.257.15:32:42.27#ibcon#wrote, iclass 30, count 2 2006.257.15:32:42.27#ibcon#about to read 3, iclass 30, count 2 2006.257.15:32:42.29#ibcon#read 3, iclass 30, count 2 2006.257.15:32:42.29#ibcon#about to read 4, iclass 30, count 2 2006.257.15:32:42.29#ibcon#read 4, iclass 30, count 2 2006.257.15:32:42.29#ibcon#about to read 5, iclass 30, count 2 2006.257.15:32:42.29#ibcon#read 5, iclass 30, count 2 2006.257.15:32:42.29#ibcon#about to read 6, iclass 30, count 2 2006.257.15:32:42.29#ibcon#read 6, iclass 30, count 2 2006.257.15:32:42.29#ibcon#end of sib2, iclass 30, count 2 2006.257.15:32:42.29#ibcon#*mode == 0, iclass 30, count 2 2006.257.15:32:42.29#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.15:32:42.29#ibcon#[25=AT07-04\r\n] 2006.257.15:32:42.29#ibcon#*before write, iclass 30, count 2 2006.257.15:32:42.29#ibcon#enter sib2, iclass 30, count 2 2006.257.15:32:42.29#ibcon#flushed, iclass 30, count 2 2006.257.15:32:42.29#ibcon#about to write, iclass 30, count 2 2006.257.15:32:42.29#ibcon#wrote, iclass 30, count 2 2006.257.15:32:42.29#ibcon#about to read 3, iclass 30, count 2 2006.257.15:32:42.32#ibcon#read 3, iclass 30, count 2 2006.257.15:32:42.32#ibcon#about to read 4, iclass 30, count 2 2006.257.15:32:42.32#ibcon#read 4, iclass 30, count 2 2006.257.15:32:42.32#ibcon#about to read 5, iclass 30, count 2 2006.257.15:32:42.32#ibcon#read 5, iclass 30, count 2 2006.257.15:32:42.32#ibcon#about to read 6, iclass 30, count 2 2006.257.15:32:42.32#ibcon#read 6, iclass 30, count 2 2006.257.15:32:42.32#ibcon#end of sib2, iclass 30, count 2 2006.257.15:32:42.32#ibcon#*after write, iclass 30, count 2 2006.257.15:32:42.32#ibcon#*before return 0, iclass 30, count 2 2006.257.15:32:42.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:42.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:42.32#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.15:32:42.32#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:42.32#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:42.44#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:42.44#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:42.44#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:32:42.44#ibcon#first serial, iclass 30, count 0 2006.257.15:32:42.44#ibcon#enter sib2, iclass 30, count 0 2006.257.15:32:42.44#ibcon#flushed, iclass 30, count 0 2006.257.15:32:42.44#ibcon#about to write, iclass 30, count 0 2006.257.15:32:42.44#ibcon#wrote, iclass 30, count 0 2006.257.15:32:42.44#ibcon#about to read 3, iclass 30, count 0 2006.257.15:32:42.46#ibcon#read 3, iclass 30, count 0 2006.257.15:32:42.46#ibcon#about to read 4, iclass 30, count 0 2006.257.15:32:42.46#ibcon#read 4, iclass 30, count 0 2006.257.15:32:42.46#ibcon#about to read 5, iclass 30, count 0 2006.257.15:32:42.46#ibcon#read 5, iclass 30, count 0 2006.257.15:32:42.46#ibcon#about to read 6, iclass 30, count 0 2006.257.15:32:42.46#ibcon#read 6, iclass 30, count 0 2006.257.15:32:42.46#ibcon#end of sib2, iclass 30, count 0 2006.257.15:32:42.46#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:32:42.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:32:42.46#ibcon#[25=USB\r\n] 2006.257.15:32:42.46#ibcon#*before write, iclass 30, count 0 2006.257.15:32:42.46#ibcon#enter sib2, iclass 30, count 0 2006.257.15:32:42.46#ibcon#flushed, iclass 30, count 0 2006.257.15:32:42.46#ibcon#about to write, iclass 30, count 0 2006.257.15:32:42.46#ibcon#wrote, iclass 30, count 0 2006.257.15:32:42.46#ibcon#about to read 3, iclass 30, count 0 2006.257.15:32:42.49#ibcon#read 3, iclass 30, count 0 2006.257.15:32:42.49#ibcon#about to read 4, iclass 30, count 0 2006.257.15:32:42.49#ibcon#read 4, iclass 30, count 0 2006.257.15:32:42.49#ibcon#about to read 5, iclass 30, count 0 2006.257.15:32:42.49#ibcon#read 5, iclass 30, count 0 2006.257.15:32:42.49#ibcon#about to read 6, iclass 30, count 0 2006.257.15:32:42.49#ibcon#read 6, iclass 30, count 0 2006.257.15:32:42.49#ibcon#end of sib2, iclass 30, count 0 2006.257.15:32:42.49#ibcon#*after write, iclass 30, count 0 2006.257.15:32:42.49#ibcon#*before return 0, iclass 30, count 0 2006.257.15:32:42.49#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:42.49#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:42.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:32:42.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:32:42.49$vck44/valo=8,884.99 2006.257.15:32:42.49#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.15:32:42.49#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.15:32:42.49#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:42.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:42.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:42.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:42.49#ibcon#enter wrdev, iclass 32, count 0 2006.257.15:32:42.49#ibcon#first serial, iclass 32, count 0 2006.257.15:32:42.49#ibcon#enter sib2, iclass 32, count 0 2006.257.15:32:42.49#ibcon#flushed, iclass 32, count 0 2006.257.15:32:42.49#ibcon#about to write, iclass 32, count 0 2006.257.15:32:42.49#ibcon#wrote, iclass 32, count 0 2006.257.15:32:42.49#ibcon#about to read 3, iclass 32, count 0 2006.257.15:32:42.51#ibcon#read 3, iclass 32, count 0 2006.257.15:32:42.51#ibcon#about to read 4, iclass 32, count 0 2006.257.15:32:42.51#ibcon#read 4, iclass 32, count 0 2006.257.15:32:42.51#ibcon#about to read 5, iclass 32, count 0 2006.257.15:32:42.51#ibcon#read 5, iclass 32, count 0 2006.257.15:32:42.51#ibcon#about to read 6, iclass 32, count 0 2006.257.15:32:42.51#ibcon#read 6, iclass 32, count 0 2006.257.15:32:42.51#ibcon#end of sib2, iclass 32, count 0 2006.257.15:32:42.51#ibcon#*mode == 0, iclass 32, count 0 2006.257.15:32:42.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.15:32:42.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:32:42.51#ibcon#*before write, iclass 32, count 0 2006.257.15:32:42.51#ibcon#enter sib2, iclass 32, count 0 2006.257.15:32:42.51#ibcon#flushed, iclass 32, count 0 2006.257.15:32:42.51#ibcon#about to write, iclass 32, count 0 2006.257.15:32:42.51#ibcon#wrote, iclass 32, count 0 2006.257.15:32:42.51#ibcon#about to read 3, iclass 32, count 0 2006.257.15:32:42.55#ibcon#read 3, iclass 32, count 0 2006.257.15:32:42.55#ibcon#about to read 4, iclass 32, count 0 2006.257.15:32:42.55#ibcon#read 4, iclass 32, count 0 2006.257.15:32:42.55#ibcon#about to read 5, iclass 32, count 0 2006.257.15:32:42.55#ibcon#read 5, iclass 32, count 0 2006.257.15:32:42.55#ibcon#about to read 6, iclass 32, count 0 2006.257.15:32:42.55#ibcon#read 6, iclass 32, count 0 2006.257.15:32:42.55#ibcon#end of sib2, iclass 32, count 0 2006.257.15:32:42.55#ibcon#*after write, iclass 32, count 0 2006.257.15:32:42.55#ibcon#*before return 0, iclass 32, count 0 2006.257.15:32:42.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:42.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:42.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.15:32:42.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.15:32:42.55$vck44/va=8,4 2006.257.15:32:42.55#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.15:32:42.55#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.15:32:42.55#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:42.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:32:42.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:32:42.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:32:42.61#ibcon#enter wrdev, iclass 34, count 2 2006.257.15:32:42.61#ibcon#first serial, iclass 34, count 2 2006.257.15:32:42.61#ibcon#enter sib2, iclass 34, count 2 2006.257.15:32:42.61#ibcon#flushed, iclass 34, count 2 2006.257.15:32:42.61#ibcon#about to write, iclass 34, count 2 2006.257.15:32:42.61#ibcon#wrote, iclass 34, count 2 2006.257.15:32:42.61#ibcon#about to read 3, iclass 34, count 2 2006.257.15:32:42.63#ibcon#read 3, iclass 34, count 2 2006.257.15:32:42.63#ibcon#about to read 4, iclass 34, count 2 2006.257.15:32:42.63#ibcon#read 4, iclass 34, count 2 2006.257.15:32:42.63#ibcon#about to read 5, iclass 34, count 2 2006.257.15:32:42.63#ibcon#read 5, iclass 34, count 2 2006.257.15:32:42.63#ibcon#about to read 6, iclass 34, count 2 2006.257.15:32:42.63#ibcon#read 6, iclass 34, count 2 2006.257.15:32:42.63#ibcon#end of sib2, iclass 34, count 2 2006.257.15:32:42.63#ibcon#*mode == 0, iclass 34, count 2 2006.257.15:32:42.63#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.15:32:42.63#ibcon#[25=AT08-04\r\n] 2006.257.15:32:42.63#ibcon#*before write, iclass 34, count 2 2006.257.15:32:42.63#ibcon#enter sib2, iclass 34, count 2 2006.257.15:32:42.63#ibcon#flushed, iclass 34, count 2 2006.257.15:32:42.63#ibcon#about to write, iclass 34, count 2 2006.257.15:32:42.63#ibcon#wrote, iclass 34, count 2 2006.257.15:32:42.63#ibcon#about to read 3, iclass 34, count 2 2006.257.15:32:42.66#ibcon#read 3, iclass 34, count 2 2006.257.15:32:42.66#ibcon#about to read 4, iclass 34, count 2 2006.257.15:32:42.66#ibcon#read 4, iclass 34, count 2 2006.257.15:32:42.66#ibcon#about to read 5, iclass 34, count 2 2006.257.15:32:42.66#ibcon#read 5, iclass 34, count 2 2006.257.15:32:42.66#ibcon#about to read 6, iclass 34, count 2 2006.257.15:32:42.66#ibcon#read 6, iclass 34, count 2 2006.257.15:32:42.66#ibcon#end of sib2, iclass 34, count 2 2006.257.15:32:42.66#ibcon#*after write, iclass 34, count 2 2006.257.15:32:42.66#ibcon#*before return 0, iclass 34, count 2 2006.257.15:32:42.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:32:42.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:32:42.66#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.15:32:42.66#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:42.66#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:32:42.78#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:32:42.78#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:32:42.78#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:32:42.78#ibcon#first serial, iclass 34, count 0 2006.257.15:32:42.78#ibcon#enter sib2, iclass 34, count 0 2006.257.15:32:42.78#ibcon#flushed, iclass 34, count 0 2006.257.15:32:42.78#ibcon#about to write, iclass 34, count 0 2006.257.15:32:42.78#ibcon#wrote, iclass 34, count 0 2006.257.15:32:42.78#ibcon#about to read 3, iclass 34, count 0 2006.257.15:32:42.80#ibcon#read 3, iclass 34, count 0 2006.257.15:32:42.80#ibcon#about to read 4, iclass 34, count 0 2006.257.15:32:42.80#ibcon#read 4, iclass 34, count 0 2006.257.15:32:42.80#ibcon#about to read 5, iclass 34, count 0 2006.257.15:32:42.80#ibcon#read 5, iclass 34, count 0 2006.257.15:32:42.80#ibcon#about to read 6, iclass 34, count 0 2006.257.15:32:42.80#ibcon#read 6, iclass 34, count 0 2006.257.15:32:42.80#ibcon#end of sib2, iclass 34, count 0 2006.257.15:32:42.80#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:32:42.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:32:42.80#ibcon#[25=USB\r\n] 2006.257.15:32:42.80#ibcon#*before write, iclass 34, count 0 2006.257.15:32:42.80#ibcon#enter sib2, iclass 34, count 0 2006.257.15:32:42.80#ibcon#flushed, iclass 34, count 0 2006.257.15:32:42.80#ibcon#about to write, iclass 34, count 0 2006.257.15:32:42.80#ibcon#wrote, iclass 34, count 0 2006.257.15:32:42.80#ibcon#about to read 3, iclass 34, count 0 2006.257.15:32:42.83#ibcon#read 3, iclass 34, count 0 2006.257.15:32:42.83#ibcon#about to read 4, iclass 34, count 0 2006.257.15:32:42.83#ibcon#read 4, iclass 34, count 0 2006.257.15:32:42.83#ibcon#about to read 5, iclass 34, count 0 2006.257.15:32:42.83#ibcon#read 5, iclass 34, count 0 2006.257.15:32:42.83#ibcon#about to read 6, iclass 34, count 0 2006.257.15:32:42.83#ibcon#read 6, iclass 34, count 0 2006.257.15:32:42.83#ibcon#end of sib2, iclass 34, count 0 2006.257.15:32:42.83#ibcon#*after write, iclass 34, count 0 2006.257.15:32:42.83#ibcon#*before return 0, iclass 34, count 0 2006.257.15:32:42.83#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:32:42.83#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:32:42.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:32:42.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:32:42.83$vck44/vblo=1,629.99 2006.257.15:32:42.83#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.15:32:42.83#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.15:32:42.83#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:42.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:32:42.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:32:42.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:32:42.83#ibcon#enter wrdev, iclass 36, count 0 2006.257.15:32:42.83#ibcon#first serial, iclass 36, count 0 2006.257.15:32:42.83#ibcon#enter sib2, iclass 36, count 0 2006.257.15:32:42.83#ibcon#flushed, iclass 36, count 0 2006.257.15:32:42.83#ibcon#about to write, iclass 36, count 0 2006.257.15:32:42.83#ibcon#wrote, iclass 36, count 0 2006.257.15:32:42.83#ibcon#about to read 3, iclass 36, count 0 2006.257.15:32:42.85#ibcon#read 3, iclass 36, count 0 2006.257.15:32:42.85#ibcon#about to read 4, iclass 36, count 0 2006.257.15:32:42.85#ibcon#read 4, iclass 36, count 0 2006.257.15:32:42.85#ibcon#about to read 5, iclass 36, count 0 2006.257.15:32:42.85#ibcon#read 5, iclass 36, count 0 2006.257.15:32:42.85#ibcon#about to read 6, iclass 36, count 0 2006.257.15:32:42.85#ibcon#read 6, iclass 36, count 0 2006.257.15:32:42.85#ibcon#end of sib2, iclass 36, count 0 2006.257.15:32:42.85#ibcon#*mode == 0, iclass 36, count 0 2006.257.15:32:42.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.15:32:42.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:32:42.85#ibcon#*before write, iclass 36, count 0 2006.257.15:32:42.85#ibcon#enter sib2, iclass 36, count 0 2006.257.15:32:42.85#ibcon#flushed, iclass 36, count 0 2006.257.15:32:42.85#ibcon#about to write, iclass 36, count 0 2006.257.15:32:42.85#ibcon#wrote, iclass 36, count 0 2006.257.15:32:42.85#ibcon#about to read 3, iclass 36, count 0 2006.257.15:32:42.89#ibcon#read 3, iclass 36, count 0 2006.257.15:32:42.89#ibcon#about to read 4, iclass 36, count 0 2006.257.15:32:42.89#ibcon#read 4, iclass 36, count 0 2006.257.15:32:42.89#ibcon#about to read 5, iclass 36, count 0 2006.257.15:32:42.89#ibcon#read 5, iclass 36, count 0 2006.257.15:32:42.89#ibcon#about to read 6, iclass 36, count 0 2006.257.15:32:42.89#ibcon#read 6, iclass 36, count 0 2006.257.15:32:42.89#ibcon#end of sib2, iclass 36, count 0 2006.257.15:32:42.89#ibcon#*after write, iclass 36, count 0 2006.257.15:32:42.89#ibcon#*before return 0, iclass 36, count 0 2006.257.15:32:42.89#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:32:42.89#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:32:42.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.15:32:42.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.15:32:42.89$vck44/vb=1,4 2006.257.15:32:42.89#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.15:32:42.89#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.15:32:42.89#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:42.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:32:42.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:32:42.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:32:42.89#ibcon#enter wrdev, iclass 38, count 2 2006.257.15:32:42.89#ibcon#first serial, iclass 38, count 2 2006.257.15:32:42.89#ibcon#enter sib2, iclass 38, count 2 2006.257.15:32:42.89#ibcon#flushed, iclass 38, count 2 2006.257.15:32:42.89#ibcon#about to write, iclass 38, count 2 2006.257.15:32:42.89#ibcon#wrote, iclass 38, count 2 2006.257.15:32:42.89#ibcon#about to read 3, iclass 38, count 2 2006.257.15:32:42.91#ibcon#read 3, iclass 38, count 2 2006.257.15:32:42.91#ibcon#about to read 4, iclass 38, count 2 2006.257.15:32:42.91#ibcon#read 4, iclass 38, count 2 2006.257.15:32:42.91#ibcon#about to read 5, iclass 38, count 2 2006.257.15:32:42.91#ibcon#read 5, iclass 38, count 2 2006.257.15:32:42.91#ibcon#about to read 6, iclass 38, count 2 2006.257.15:32:42.91#ibcon#read 6, iclass 38, count 2 2006.257.15:32:42.91#ibcon#end of sib2, iclass 38, count 2 2006.257.15:32:42.91#ibcon#*mode == 0, iclass 38, count 2 2006.257.15:32:42.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.15:32:42.91#ibcon#[27=AT01-04\r\n] 2006.257.15:32:42.91#ibcon#*before write, iclass 38, count 2 2006.257.15:32:42.91#ibcon#enter sib2, iclass 38, count 2 2006.257.15:32:42.91#ibcon#flushed, iclass 38, count 2 2006.257.15:32:42.91#ibcon#about to write, iclass 38, count 2 2006.257.15:32:42.91#ibcon#wrote, iclass 38, count 2 2006.257.15:32:42.91#ibcon#about to read 3, iclass 38, count 2 2006.257.15:32:42.94#ibcon#read 3, iclass 38, count 2 2006.257.15:32:42.94#ibcon#about to read 4, iclass 38, count 2 2006.257.15:32:42.94#ibcon#read 4, iclass 38, count 2 2006.257.15:32:42.94#ibcon#about to read 5, iclass 38, count 2 2006.257.15:32:42.94#ibcon#read 5, iclass 38, count 2 2006.257.15:32:42.94#ibcon#about to read 6, iclass 38, count 2 2006.257.15:32:42.94#ibcon#read 6, iclass 38, count 2 2006.257.15:32:42.94#ibcon#end of sib2, iclass 38, count 2 2006.257.15:32:42.94#ibcon#*after write, iclass 38, count 2 2006.257.15:32:42.94#ibcon#*before return 0, iclass 38, count 2 2006.257.15:32:42.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:32:42.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:32:42.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.15:32:42.94#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:42.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:32:43.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:32:43.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:32:43.06#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:32:43.06#ibcon#first serial, iclass 38, count 0 2006.257.15:32:43.06#ibcon#enter sib2, iclass 38, count 0 2006.257.15:32:43.06#ibcon#flushed, iclass 38, count 0 2006.257.15:32:43.06#ibcon#about to write, iclass 38, count 0 2006.257.15:32:43.06#ibcon#wrote, iclass 38, count 0 2006.257.15:32:43.06#ibcon#about to read 3, iclass 38, count 0 2006.257.15:32:43.08#ibcon#read 3, iclass 38, count 0 2006.257.15:32:43.08#ibcon#about to read 4, iclass 38, count 0 2006.257.15:32:43.08#ibcon#read 4, iclass 38, count 0 2006.257.15:32:43.08#ibcon#about to read 5, iclass 38, count 0 2006.257.15:32:43.08#ibcon#read 5, iclass 38, count 0 2006.257.15:32:43.08#ibcon#about to read 6, iclass 38, count 0 2006.257.15:32:43.08#ibcon#read 6, iclass 38, count 0 2006.257.15:32:43.08#ibcon#end of sib2, iclass 38, count 0 2006.257.15:32:43.08#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:32:43.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:32:43.08#ibcon#[27=USB\r\n] 2006.257.15:32:43.08#ibcon#*before write, iclass 38, count 0 2006.257.15:32:43.08#ibcon#enter sib2, iclass 38, count 0 2006.257.15:32:43.08#ibcon#flushed, iclass 38, count 0 2006.257.15:32:43.08#ibcon#about to write, iclass 38, count 0 2006.257.15:32:43.08#ibcon#wrote, iclass 38, count 0 2006.257.15:32:43.08#ibcon#about to read 3, iclass 38, count 0 2006.257.15:32:43.11#ibcon#read 3, iclass 38, count 0 2006.257.15:32:43.11#ibcon#about to read 4, iclass 38, count 0 2006.257.15:32:43.11#ibcon#read 4, iclass 38, count 0 2006.257.15:32:43.11#ibcon#about to read 5, iclass 38, count 0 2006.257.15:32:43.11#ibcon#read 5, iclass 38, count 0 2006.257.15:32:43.11#ibcon#about to read 6, iclass 38, count 0 2006.257.15:32:43.11#ibcon#read 6, iclass 38, count 0 2006.257.15:32:43.11#ibcon#end of sib2, iclass 38, count 0 2006.257.15:32:43.11#ibcon#*after write, iclass 38, count 0 2006.257.15:32:43.11#ibcon#*before return 0, iclass 38, count 0 2006.257.15:32:43.11#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:32:43.11#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:32:43.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:32:43.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:32:43.11$vck44/vblo=2,634.99 2006.257.15:32:43.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.15:32:43.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.15:32:43.11#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:43.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:43.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:43.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:43.11#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:32:43.11#ibcon#first serial, iclass 40, count 0 2006.257.15:32:43.11#ibcon#enter sib2, iclass 40, count 0 2006.257.15:32:43.11#ibcon#flushed, iclass 40, count 0 2006.257.15:32:43.11#ibcon#about to write, iclass 40, count 0 2006.257.15:32:43.11#ibcon#wrote, iclass 40, count 0 2006.257.15:32:43.11#ibcon#about to read 3, iclass 40, count 0 2006.257.15:32:43.13#ibcon#read 3, iclass 40, count 0 2006.257.15:32:43.13#ibcon#about to read 4, iclass 40, count 0 2006.257.15:32:43.13#ibcon#read 4, iclass 40, count 0 2006.257.15:32:43.13#ibcon#about to read 5, iclass 40, count 0 2006.257.15:32:43.13#ibcon#read 5, iclass 40, count 0 2006.257.15:32:43.13#ibcon#about to read 6, iclass 40, count 0 2006.257.15:32:43.13#ibcon#read 6, iclass 40, count 0 2006.257.15:32:43.13#ibcon#end of sib2, iclass 40, count 0 2006.257.15:32:43.13#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:32:43.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:32:43.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:32:43.13#ibcon#*before write, iclass 40, count 0 2006.257.15:32:43.13#ibcon#enter sib2, iclass 40, count 0 2006.257.15:32:43.13#ibcon#flushed, iclass 40, count 0 2006.257.15:32:43.13#ibcon#about to write, iclass 40, count 0 2006.257.15:32:43.13#ibcon#wrote, iclass 40, count 0 2006.257.15:32:43.13#ibcon#about to read 3, iclass 40, count 0 2006.257.15:32:43.17#ibcon#read 3, iclass 40, count 0 2006.257.15:32:43.17#ibcon#about to read 4, iclass 40, count 0 2006.257.15:32:43.17#ibcon#read 4, iclass 40, count 0 2006.257.15:32:43.17#ibcon#about to read 5, iclass 40, count 0 2006.257.15:32:43.17#ibcon#read 5, iclass 40, count 0 2006.257.15:32:43.17#ibcon#about to read 6, iclass 40, count 0 2006.257.15:32:43.17#ibcon#read 6, iclass 40, count 0 2006.257.15:32:43.17#ibcon#end of sib2, iclass 40, count 0 2006.257.15:32:43.17#ibcon#*after write, iclass 40, count 0 2006.257.15:32:43.17#ibcon#*before return 0, iclass 40, count 0 2006.257.15:32:43.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:43.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:32:43.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:32:43.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:32:43.17$vck44/vb=2,5 2006.257.15:32:43.17#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.15:32:43.17#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.15:32:43.17#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:43.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:43.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:43.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:43.23#ibcon#enter wrdev, iclass 4, count 2 2006.257.15:32:43.23#ibcon#first serial, iclass 4, count 2 2006.257.15:32:43.23#ibcon#enter sib2, iclass 4, count 2 2006.257.15:32:43.23#ibcon#flushed, iclass 4, count 2 2006.257.15:32:43.23#ibcon#about to write, iclass 4, count 2 2006.257.15:32:43.23#ibcon#wrote, iclass 4, count 2 2006.257.15:32:43.23#ibcon#about to read 3, iclass 4, count 2 2006.257.15:32:43.25#ibcon#read 3, iclass 4, count 2 2006.257.15:32:43.25#ibcon#about to read 4, iclass 4, count 2 2006.257.15:32:43.25#ibcon#read 4, iclass 4, count 2 2006.257.15:32:43.25#ibcon#about to read 5, iclass 4, count 2 2006.257.15:32:43.25#ibcon#read 5, iclass 4, count 2 2006.257.15:32:43.25#ibcon#about to read 6, iclass 4, count 2 2006.257.15:32:43.25#ibcon#read 6, iclass 4, count 2 2006.257.15:32:43.25#ibcon#end of sib2, iclass 4, count 2 2006.257.15:32:43.25#ibcon#*mode == 0, iclass 4, count 2 2006.257.15:32:43.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.15:32:43.25#ibcon#[27=AT02-05\r\n] 2006.257.15:32:43.25#ibcon#*before write, iclass 4, count 2 2006.257.15:32:43.25#ibcon#enter sib2, iclass 4, count 2 2006.257.15:32:43.25#ibcon#flushed, iclass 4, count 2 2006.257.15:32:43.25#ibcon#about to write, iclass 4, count 2 2006.257.15:32:43.25#ibcon#wrote, iclass 4, count 2 2006.257.15:32:43.25#ibcon#about to read 3, iclass 4, count 2 2006.257.15:32:43.28#ibcon#read 3, iclass 4, count 2 2006.257.15:32:43.28#ibcon#about to read 4, iclass 4, count 2 2006.257.15:32:43.28#ibcon#read 4, iclass 4, count 2 2006.257.15:32:43.28#ibcon#about to read 5, iclass 4, count 2 2006.257.15:32:43.28#ibcon#read 5, iclass 4, count 2 2006.257.15:32:43.28#ibcon#about to read 6, iclass 4, count 2 2006.257.15:32:43.28#ibcon#read 6, iclass 4, count 2 2006.257.15:32:43.28#ibcon#end of sib2, iclass 4, count 2 2006.257.15:32:43.28#ibcon#*after write, iclass 4, count 2 2006.257.15:32:43.28#ibcon#*before return 0, iclass 4, count 2 2006.257.15:32:43.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:43.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:32:43.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.15:32:43.28#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:43.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:43.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:43.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:43.40#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:32:43.40#ibcon#first serial, iclass 4, count 0 2006.257.15:32:43.40#ibcon#enter sib2, iclass 4, count 0 2006.257.15:32:43.40#ibcon#flushed, iclass 4, count 0 2006.257.15:32:43.40#ibcon#about to write, iclass 4, count 0 2006.257.15:32:43.40#ibcon#wrote, iclass 4, count 0 2006.257.15:32:43.40#ibcon#about to read 3, iclass 4, count 0 2006.257.15:32:43.42#ibcon#read 3, iclass 4, count 0 2006.257.15:32:43.42#ibcon#about to read 4, iclass 4, count 0 2006.257.15:32:43.42#ibcon#read 4, iclass 4, count 0 2006.257.15:32:43.42#ibcon#about to read 5, iclass 4, count 0 2006.257.15:32:43.42#ibcon#read 5, iclass 4, count 0 2006.257.15:32:43.42#ibcon#about to read 6, iclass 4, count 0 2006.257.15:32:43.42#ibcon#read 6, iclass 4, count 0 2006.257.15:32:43.42#ibcon#end of sib2, iclass 4, count 0 2006.257.15:32:43.42#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:32:43.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:32:43.42#ibcon#[27=USB\r\n] 2006.257.15:32:43.42#ibcon#*before write, iclass 4, count 0 2006.257.15:32:43.42#ibcon#enter sib2, iclass 4, count 0 2006.257.15:32:43.42#ibcon#flushed, iclass 4, count 0 2006.257.15:32:43.42#ibcon#about to write, iclass 4, count 0 2006.257.15:32:43.42#ibcon#wrote, iclass 4, count 0 2006.257.15:32:43.42#ibcon#about to read 3, iclass 4, count 0 2006.257.15:32:43.45#ibcon#read 3, iclass 4, count 0 2006.257.15:32:43.45#ibcon#about to read 4, iclass 4, count 0 2006.257.15:32:43.45#ibcon#read 4, iclass 4, count 0 2006.257.15:32:43.45#ibcon#about to read 5, iclass 4, count 0 2006.257.15:32:43.45#ibcon#read 5, iclass 4, count 0 2006.257.15:32:43.45#ibcon#about to read 6, iclass 4, count 0 2006.257.15:32:43.45#ibcon#read 6, iclass 4, count 0 2006.257.15:32:43.45#ibcon#end of sib2, iclass 4, count 0 2006.257.15:32:43.45#ibcon#*after write, iclass 4, count 0 2006.257.15:32:43.45#ibcon#*before return 0, iclass 4, count 0 2006.257.15:32:43.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:43.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:32:43.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:32:43.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:32:43.45$vck44/vblo=3,649.99 2006.257.15:32:43.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.15:32:43.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.15:32:43.45#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:43.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:43.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:43.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:43.45#ibcon#enter wrdev, iclass 6, count 0 2006.257.15:32:43.45#ibcon#first serial, iclass 6, count 0 2006.257.15:32:43.45#ibcon#enter sib2, iclass 6, count 0 2006.257.15:32:43.45#ibcon#flushed, iclass 6, count 0 2006.257.15:32:43.45#ibcon#about to write, iclass 6, count 0 2006.257.15:32:43.45#ibcon#wrote, iclass 6, count 0 2006.257.15:32:43.45#ibcon#about to read 3, iclass 6, count 0 2006.257.15:32:43.47#ibcon#read 3, iclass 6, count 0 2006.257.15:32:43.47#ibcon#about to read 4, iclass 6, count 0 2006.257.15:32:43.47#ibcon#read 4, iclass 6, count 0 2006.257.15:32:43.47#ibcon#about to read 5, iclass 6, count 0 2006.257.15:32:43.47#ibcon#read 5, iclass 6, count 0 2006.257.15:32:43.47#ibcon#about to read 6, iclass 6, count 0 2006.257.15:32:43.47#ibcon#read 6, iclass 6, count 0 2006.257.15:32:43.47#ibcon#end of sib2, iclass 6, count 0 2006.257.15:32:43.47#ibcon#*mode == 0, iclass 6, count 0 2006.257.15:32:43.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.15:32:43.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:32:43.47#ibcon#*before write, iclass 6, count 0 2006.257.15:32:43.47#ibcon#enter sib2, iclass 6, count 0 2006.257.15:32:43.47#ibcon#flushed, iclass 6, count 0 2006.257.15:32:43.47#ibcon#about to write, iclass 6, count 0 2006.257.15:32:43.47#ibcon#wrote, iclass 6, count 0 2006.257.15:32:43.47#ibcon#about to read 3, iclass 6, count 0 2006.257.15:32:43.51#ibcon#read 3, iclass 6, count 0 2006.257.15:32:43.51#ibcon#about to read 4, iclass 6, count 0 2006.257.15:32:43.51#ibcon#read 4, iclass 6, count 0 2006.257.15:32:43.51#ibcon#about to read 5, iclass 6, count 0 2006.257.15:32:43.51#ibcon#read 5, iclass 6, count 0 2006.257.15:32:43.51#ibcon#about to read 6, iclass 6, count 0 2006.257.15:32:43.51#ibcon#read 6, iclass 6, count 0 2006.257.15:32:43.51#ibcon#end of sib2, iclass 6, count 0 2006.257.15:32:43.51#ibcon#*after write, iclass 6, count 0 2006.257.15:32:43.51#ibcon#*before return 0, iclass 6, count 0 2006.257.15:32:43.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:43.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:32:43.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.15:32:43.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.15:32:43.51$vck44/vb=3,4 2006.257.15:32:43.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.15:32:43.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.15:32:43.51#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:43.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:43.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:43.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:43.57#ibcon#enter wrdev, iclass 10, count 2 2006.257.15:32:43.57#ibcon#first serial, iclass 10, count 2 2006.257.15:32:43.57#ibcon#enter sib2, iclass 10, count 2 2006.257.15:32:43.57#ibcon#flushed, iclass 10, count 2 2006.257.15:32:43.57#ibcon#about to write, iclass 10, count 2 2006.257.15:32:43.57#ibcon#wrote, iclass 10, count 2 2006.257.15:32:43.57#ibcon#about to read 3, iclass 10, count 2 2006.257.15:32:43.59#ibcon#read 3, iclass 10, count 2 2006.257.15:32:43.59#ibcon#about to read 4, iclass 10, count 2 2006.257.15:32:43.59#ibcon#read 4, iclass 10, count 2 2006.257.15:32:43.59#ibcon#about to read 5, iclass 10, count 2 2006.257.15:32:43.59#ibcon#read 5, iclass 10, count 2 2006.257.15:32:43.59#ibcon#about to read 6, iclass 10, count 2 2006.257.15:32:43.59#ibcon#read 6, iclass 10, count 2 2006.257.15:32:43.59#ibcon#end of sib2, iclass 10, count 2 2006.257.15:32:43.59#ibcon#*mode == 0, iclass 10, count 2 2006.257.15:32:43.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.15:32:43.59#ibcon#[27=AT03-04\r\n] 2006.257.15:32:43.59#ibcon#*before write, iclass 10, count 2 2006.257.15:32:43.59#ibcon#enter sib2, iclass 10, count 2 2006.257.15:32:43.59#ibcon#flushed, iclass 10, count 2 2006.257.15:32:43.59#ibcon#about to write, iclass 10, count 2 2006.257.15:32:43.59#ibcon#wrote, iclass 10, count 2 2006.257.15:32:43.59#ibcon#about to read 3, iclass 10, count 2 2006.257.15:32:43.62#ibcon#read 3, iclass 10, count 2 2006.257.15:32:43.62#ibcon#about to read 4, iclass 10, count 2 2006.257.15:32:43.62#ibcon#read 4, iclass 10, count 2 2006.257.15:32:43.62#ibcon#about to read 5, iclass 10, count 2 2006.257.15:32:43.62#ibcon#read 5, iclass 10, count 2 2006.257.15:32:43.62#ibcon#about to read 6, iclass 10, count 2 2006.257.15:32:43.62#ibcon#read 6, iclass 10, count 2 2006.257.15:32:43.62#ibcon#end of sib2, iclass 10, count 2 2006.257.15:32:43.62#ibcon#*after write, iclass 10, count 2 2006.257.15:32:43.62#ibcon#*before return 0, iclass 10, count 2 2006.257.15:32:43.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:43.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:32:43.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.15:32:43.62#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:43.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:43.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:43.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:43.74#ibcon#enter wrdev, iclass 10, count 0 2006.257.15:32:43.74#ibcon#first serial, iclass 10, count 0 2006.257.15:32:43.74#ibcon#enter sib2, iclass 10, count 0 2006.257.15:32:43.74#ibcon#flushed, iclass 10, count 0 2006.257.15:32:43.74#ibcon#about to write, iclass 10, count 0 2006.257.15:32:43.74#ibcon#wrote, iclass 10, count 0 2006.257.15:32:43.74#ibcon#about to read 3, iclass 10, count 0 2006.257.15:32:43.76#ibcon#read 3, iclass 10, count 0 2006.257.15:32:43.76#ibcon#about to read 4, iclass 10, count 0 2006.257.15:32:43.76#ibcon#read 4, iclass 10, count 0 2006.257.15:32:43.76#ibcon#about to read 5, iclass 10, count 0 2006.257.15:32:43.76#ibcon#read 5, iclass 10, count 0 2006.257.15:32:43.76#ibcon#about to read 6, iclass 10, count 0 2006.257.15:32:43.76#ibcon#read 6, iclass 10, count 0 2006.257.15:32:43.76#ibcon#end of sib2, iclass 10, count 0 2006.257.15:32:43.76#ibcon#*mode == 0, iclass 10, count 0 2006.257.15:32:43.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.15:32:43.76#ibcon#[27=USB\r\n] 2006.257.15:32:43.76#ibcon#*before write, iclass 10, count 0 2006.257.15:32:43.76#ibcon#enter sib2, iclass 10, count 0 2006.257.15:32:43.76#ibcon#flushed, iclass 10, count 0 2006.257.15:32:43.76#ibcon#about to write, iclass 10, count 0 2006.257.15:32:43.76#ibcon#wrote, iclass 10, count 0 2006.257.15:32:43.76#ibcon#about to read 3, iclass 10, count 0 2006.257.15:32:43.79#ibcon#read 3, iclass 10, count 0 2006.257.15:32:43.79#ibcon#about to read 4, iclass 10, count 0 2006.257.15:32:43.79#ibcon#read 4, iclass 10, count 0 2006.257.15:32:43.79#ibcon#about to read 5, iclass 10, count 0 2006.257.15:32:43.79#ibcon#read 5, iclass 10, count 0 2006.257.15:32:43.79#ibcon#about to read 6, iclass 10, count 0 2006.257.15:32:43.79#ibcon#read 6, iclass 10, count 0 2006.257.15:32:43.79#ibcon#end of sib2, iclass 10, count 0 2006.257.15:32:43.79#ibcon#*after write, iclass 10, count 0 2006.257.15:32:43.79#ibcon#*before return 0, iclass 10, count 0 2006.257.15:32:43.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:43.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:32:43.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.15:32:43.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.15:32:43.79$vck44/vblo=4,679.99 2006.257.15:32:43.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.15:32:43.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.15:32:43.79#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:43.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:43.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:43.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:43.79#ibcon#enter wrdev, iclass 12, count 0 2006.257.15:32:43.79#ibcon#first serial, iclass 12, count 0 2006.257.15:32:43.79#ibcon#enter sib2, iclass 12, count 0 2006.257.15:32:43.79#ibcon#flushed, iclass 12, count 0 2006.257.15:32:43.79#ibcon#about to write, iclass 12, count 0 2006.257.15:32:43.79#ibcon#wrote, iclass 12, count 0 2006.257.15:32:43.79#ibcon#about to read 3, iclass 12, count 0 2006.257.15:32:43.81#ibcon#read 3, iclass 12, count 0 2006.257.15:32:43.81#ibcon#about to read 4, iclass 12, count 0 2006.257.15:32:43.81#ibcon#read 4, iclass 12, count 0 2006.257.15:32:43.81#ibcon#about to read 5, iclass 12, count 0 2006.257.15:32:43.81#ibcon#read 5, iclass 12, count 0 2006.257.15:32:43.81#ibcon#about to read 6, iclass 12, count 0 2006.257.15:32:43.81#ibcon#read 6, iclass 12, count 0 2006.257.15:32:43.81#ibcon#end of sib2, iclass 12, count 0 2006.257.15:32:43.81#ibcon#*mode == 0, iclass 12, count 0 2006.257.15:32:43.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.15:32:43.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:32:43.81#ibcon#*before write, iclass 12, count 0 2006.257.15:32:43.81#ibcon#enter sib2, iclass 12, count 0 2006.257.15:32:43.81#ibcon#flushed, iclass 12, count 0 2006.257.15:32:43.81#ibcon#about to write, iclass 12, count 0 2006.257.15:32:43.81#ibcon#wrote, iclass 12, count 0 2006.257.15:32:43.81#ibcon#about to read 3, iclass 12, count 0 2006.257.15:32:43.85#ibcon#read 3, iclass 12, count 0 2006.257.15:32:43.85#ibcon#about to read 4, iclass 12, count 0 2006.257.15:32:43.85#ibcon#read 4, iclass 12, count 0 2006.257.15:32:43.85#ibcon#about to read 5, iclass 12, count 0 2006.257.15:32:43.85#ibcon#read 5, iclass 12, count 0 2006.257.15:32:43.85#ibcon#about to read 6, iclass 12, count 0 2006.257.15:32:43.85#ibcon#read 6, iclass 12, count 0 2006.257.15:32:43.85#ibcon#end of sib2, iclass 12, count 0 2006.257.15:32:43.85#ibcon#*after write, iclass 12, count 0 2006.257.15:32:43.85#ibcon#*before return 0, iclass 12, count 0 2006.257.15:32:43.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:43.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:32:43.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.15:32:43.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.15:32:43.85$vck44/vb=4,5 2006.257.15:32:43.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.15:32:43.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.15:32:43.85#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:43.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:43.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:43.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:43.91#ibcon#enter wrdev, iclass 14, count 2 2006.257.15:32:43.91#ibcon#first serial, iclass 14, count 2 2006.257.15:32:43.91#ibcon#enter sib2, iclass 14, count 2 2006.257.15:32:43.91#ibcon#flushed, iclass 14, count 2 2006.257.15:32:43.91#ibcon#about to write, iclass 14, count 2 2006.257.15:32:43.91#ibcon#wrote, iclass 14, count 2 2006.257.15:32:43.91#ibcon#about to read 3, iclass 14, count 2 2006.257.15:32:43.93#ibcon#read 3, iclass 14, count 2 2006.257.15:32:43.93#ibcon#about to read 4, iclass 14, count 2 2006.257.15:32:43.93#ibcon#read 4, iclass 14, count 2 2006.257.15:32:43.93#ibcon#about to read 5, iclass 14, count 2 2006.257.15:32:43.93#ibcon#read 5, iclass 14, count 2 2006.257.15:32:43.93#ibcon#about to read 6, iclass 14, count 2 2006.257.15:32:43.93#ibcon#read 6, iclass 14, count 2 2006.257.15:32:43.93#ibcon#end of sib2, iclass 14, count 2 2006.257.15:32:43.93#ibcon#*mode == 0, iclass 14, count 2 2006.257.15:32:43.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.15:32:43.93#ibcon#[27=AT04-05\r\n] 2006.257.15:32:43.93#ibcon#*before write, iclass 14, count 2 2006.257.15:32:43.93#ibcon#enter sib2, iclass 14, count 2 2006.257.15:32:43.93#ibcon#flushed, iclass 14, count 2 2006.257.15:32:43.93#ibcon#about to write, iclass 14, count 2 2006.257.15:32:43.93#ibcon#wrote, iclass 14, count 2 2006.257.15:32:43.93#ibcon#about to read 3, iclass 14, count 2 2006.257.15:32:43.96#ibcon#read 3, iclass 14, count 2 2006.257.15:32:43.96#ibcon#about to read 4, iclass 14, count 2 2006.257.15:32:43.96#ibcon#read 4, iclass 14, count 2 2006.257.15:32:43.96#ibcon#about to read 5, iclass 14, count 2 2006.257.15:32:43.96#ibcon#read 5, iclass 14, count 2 2006.257.15:32:43.96#ibcon#about to read 6, iclass 14, count 2 2006.257.15:32:43.96#ibcon#read 6, iclass 14, count 2 2006.257.15:32:43.96#ibcon#end of sib2, iclass 14, count 2 2006.257.15:32:43.96#ibcon#*after write, iclass 14, count 2 2006.257.15:32:43.96#ibcon#*before return 0, iclass 14, count 2 2006.257.15:32:43.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:43.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:32:43.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.15:32:43.96#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:43.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:44.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:44.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:44.08#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:32:44.08#ibcon#first serial, iclass 14, count 0 2006.257.15:32:44.08#ibcon#enter sib2, iclass 14, count 0 2006.257.15:32:44.08#ibcon#flushed, iclass 14, count 0 2006.257.15:32:44.08#ibcon#about to write, iclass 14, count 0 2006.257.15:32:44.08#ibcon#wrote, iclass 14, count 0 2006.257.15:32:44.08#ibcon#about to read 3, iclass 14, count 0 2006.257.15:32:44.10#ibcon#read 3, iclass 14, count 0 2006.257.15:32:44.10#ibcon#about to read 4, iclass 14, count 0 2006.257.15:32:44.10#ibcon#read 4, iclass 14, count 0 2006.257.15:32:44.10#ibcon#about to read 5, iclass 14, count 0 2006.257.15:32:44.10#ibcon#read 5, iclass 14, count 0 2006.257.15:32:44.10#ibcon#about to read 6, iclass 14, count 0 2006.257.15:32:44.10#ibcon#read 6, iclass 14, count 0 2006.257.15:32:44.10#ibcon#end of sib2, iclass 14, count 0 2006.257.15:32:44.10#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:32:44.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:32:44.10#ibcon#[27=USB\r\n] 2006.257.15:32:44.10#ibcon#*before write, iclass 14, count 0 2006.257.15:32:44.10#ibcon#enter sib2, iclass 14, count 0 2006.257.15:32:44.10#ibcon#flushed, iclass 14, count 0 2006.257.15:32:44.10#ibcon#about to write, iclass 14, count 0 2006.257.15:32:44.10#ibcon#wrote, iclass 14, count 0 2006.257.15:32:44.10#ibcon#about to read 3, iclass 14, count 0 2006.257.15:32:44.13#ibcon#read 3, iclass 14, count 0 2006.257.15:32:44.13#ibcon#about to read 4, iclass 14, count 0 2006.257.15:32:44.13#ibcon#read 4, iclass 14, count 0 2006.257.15:32:44.13#ibcon#about to read 5, iclass 14, count 0 2006.257.15:32:44.13#ibcon#read 5, iclass 14, count 0 2006.257.15:32:44.13#ibcon#about to read 6, iclass 14, count 0 2006.257.15:32:44.13#ibcon#read 6, iclass 14, count 0 2006.257.15:32:44.13#ibcon#end of sib2, iclass 14, count 0 2006.257.15:32:44.13#ibcon#*after write, iclass 14, count 0 2006.257.15:32:44.13#ibcon#*before return 0, iclass 14, count 0 2006.257.15:32:44.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:44.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:32:44.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:32:44.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:32:44.13$vck44/vblo=5,709.99 2006.257.15:32:44.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.15:32:44.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.15:32:44.13#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:44.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:44.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:44.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:44.13#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:32:44.13#ibcon#first serial, iclass 16, count 0 2006.257.15:32:44.13#ibcon#enter sib2, iclass 16, count 0 2006.257.15:32:44.13#ibcon#flushed, iclass 16, count 0 2006.257.15:32:44.13#ibcon#about to write, iclass 16, count 0 2006.257.15:32:44.13#ibcon#wrote, iclass 16, count 0 2006.257.15:32:44.13#ibcon#about to read 3, iclass 16, count 0 2006.257.15:32:44.15#ibcon#read 3, iclass 16, count 0 2006.257.15:32:44.15#ibcon#about to read 4, iclass 16, count 0 2006.257.15:32:44.15#ibcon#read 4, iclass 16, count 0 2006.257.15:32:44.15#ibcon#about to read 5, iclass 16, count 0 2006.257.15:32:44.15#ibcon#read 5, iclass 16, count 0 2006.257.15:32:44.15#ibcon#about to read 6, iclass 16, count 0 2006.257.15:32:44.15#ibcon#read 6, iclass 16, count 0 2006.257.15:32:44.15#ibcon#end of sib2, iclass 16, count 0 2006.257.15:32:44.15#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:32:44.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:32:44.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:32:44.15#ibcon#*before write, iclass 16, count 0 2006.257.15:32:44.15#ibcon#enter sib2, iclass 16, count 0 2006.257.15:32:44.15#ibcon#flushed, iclass 16, count 0 2006.257.15:32:44.15#ibcon#about to write, iclass 16, count 0 2006.257.15:32:44.15#ibcon#wrote, iclass 16, count 0 2006.257.15:32:44.15#ibcon#about to read 3, iclass 16, count 0 2006.257.15:32:44.19#ibcon#read 3, iclass 16, count 0 2006.257.15:32:44.19#ibcon#about to read 4, iclass 16, count 0 2006.257.15:32:44.19#ibcon#read 4, iclass 16, count 0 2006.257.15:32:44.19#ibcon#about to read 5, iclass 16, count 0 2006.257.15:32:44.19#ibcon#read 5, iclass 16, count 0 2006.257.15:32:44.19#ibcon#about to read 6, iclass 16, count 0 2006.257.15:32:44.19#ibcon#read 6, iclass 16, count 0 2006.257.15:32:44.19#ibcon#end of sib2, iclass 16, count 0 2006.257.15:32:44.19#ibcon#*after write, iclass 16, count 0 2006.257.15:32:44.19#ibcon#*before return 0, iclass 16, count 0 2006.257.15:32:44.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:44.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:32:44.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:32:44.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:32:44.19$vck44/vb=5,4 2006.257.15:32:44.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.15:32:44.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.15:32:44.19#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:44.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:44.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:44.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:44.25#ibcon#enter wrdev, iclass 18, count 2 2006.257.15:32:44.25#ibcon#first serial, iclass 18, count 2 2006.257.15:32:44.25#ibcon#enter sib2, iclass 18, count 2 2006.257.15:32:44.25#ibcon#flushed, iclass 18, count 2 2006.257.15:32:44.25#ibcon#about to write, iclass 18, count 2 2006.257.15:32:44.25#ibcon#wrote, iclass 18, count 2 2006.257.15:32:44.25#ibcon#about to read 3, iclass 18, count 2 2006.257.15:32:44.27#ibcon#read 3, iclass 18, count 2 2006.257.15:32:44.27#ibcon#about to read 4, iclass 18, count 2 2006.257.15:32:44.27#ibcon#read 4, iclass 18, count 2 2006.257.15:32:44.27#ibcon#about to read 5, iclass 18, count 2 2006.257.15:32:44.27#ibcon#read 5, iclass 18, count 2 2006.257.15:32:44.27#ibcon#about to read 6, iclass 18, count 2 2006.257.15:32:44.27#ibcon#read 6, iclass 18, count 2 2006.257.15:32:44.27#ibcon#end of sib2, iclass 18, count 2 2006.257.15:32:44.27#ibcon#*mode == 0, iclass 18, count 2 2006.257.15:32:44.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.15:32:44.27#ibcon#[27=AT05-04\r\n] 2006.257.15:32:44.27#ibcon#*before write, iclass 18, count 2 2006.257.15:32:44.27#ibcon#enter sib2, iclass 18, count 2 2006.257.15:32:44.27#ibcon#flushed, iclass 18, count 2 2006.257.15:32:44.27#ibcon#about to write, iclass 18, count 2 2006.257.15:32:44.27#ibcon#wrote, iclass 18, count 2 2006.257.15:32:44.27#ibcon#about to read 3, iclass 18, count 2 2006.257.15:32:44.30#ibcon#read 3, iclass 18, count 2 2006.257.15:32:44.30#ibcon#about to read 4, iclass 18, count 2 2006.257.15:32:44.30#ibcon#read 4, iclass 18, count 2 2006.257.15:32:44.30#ibcon#about to read 5, iclass 18, count 2 2006.257.15:32:44.30#ibcon#read 5, iclass 18, count 2 2006.257.15:32:44.30#ibcon#about to read 6, iclass 18, count 2 2006.257.15:32:44.30#ibcon#read 6, iclass 18, count 2 2006.257.15:32:44.30#ibcon#end of sib2, iclass 18, count 2 2006.257.15:32:44.30#ibcon#*after write, iclass 18, count 2 2006.257.15:32:44.30#ibcon#*before return 0, iclass 18, count 2 2006.257.15:32:44.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:44.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:32:44.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.15:32:44.30#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:44.30#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:44.42#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:44.42#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:44.42#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:32:44.42#ibcon#first serial, iclass 18, count 0 2006.257.15:32:44.42#ibcon#enter sib2, iclass 18, count 0 2006.257.15:32:44.42#ibcon#flushed, iclass 18, count 0 2006.257.15:32:44.42#ibcon#about to write, iclass 18, count 0 2006.257.15:32:44.42#ibcon#wrote, iclass 18, count 0 2006.257.15:32:44.42#ibcon#about to read 3, iclass 18, count 0 2006.257.15:32:44.44#ibcon#read 3, iclass 18, count 0 2006.257.15:32:44.44#ibcon#about to read 4, iclass 18, count 0 2006.257.15:32:44.44#ibcon#read 4, iclass 18, count 0 2006.257.15:32:44.44#ibcon#about to read 5, iclass 18, count 0 2006.257.15:32:44.44#ibcon#read 5, iclass 18, count 0 2006.257.15:32:44.44#ibcon#about to read 6, iclass 18, count 0 2006.257.15:32:44.44#ibcon#read 6, iclass 18, count 0 2006.257.15:32:44.44#ibcon#end of sib2, iclass 18, count 0 2006.257.15:32:44.44#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:32:44.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:32:44.44#ibcon#[27=USB\r\n] 2006.257.15:32:44.44#ibcon#*before write, iclass 18, count 0 2006.257.15:32:44.44#ibcon#enter sib2, iclass 18, count 0 2006.257.15:32:44.44#ibcon#flushed, iclass 18, count 0 2006.257.15:32:44.44#ibcon#about to write, iclass 18, count 0 2006.257.15:32:44.44#ibcon#wrote, iclass 18, count 0 2006.257.15:32:44.44#ibcon#about to read 3, iclass 18, count 0 2006.257.15:32:44.47#ibcon#read 3, iclass 18, count 0 2006.257.15:32:44.47#ibcon#about to read 4, iclass 18, count 0 2006.257.15:32:44.47#ibcon#read 4, iclass 18, count 0 2006.257.15:32:44.47#ibcon#about to read 5, iclass 18, count 0 2006.257.15:32:44.47#ibcon#read 5, iclass 18, count 0 2006.257.15:32:44.47#ibcon#about to read 6, iclass 18, count 0 2006.257.15:32:44.47#ibcon#read 6, iclass 18, count 0 2006.257.15:32:44.47#ibcon#end of sib2, iclass 18, count 0 2006.257.15:32:44.47#ibcon#*after write, iclass 18, count 0 2006.257.15:32:44.47#ibcon#*before return 0, iclass 18, count 0 2006.257.15:32:44.47#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:44.47#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:32:44.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:32:44.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:32:44.47$vck44/vblo=6,719.99 2006.257.15:32:44.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.15:32:44.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.15:32:44.47#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:44.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:44.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:44.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:44.47#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:32:44.47#ibcon#first serial, iclass 20, count 0 2006.257.15:32:44.47#ibcon#enter sib2, iclass 20, count 0 2006.257.15:32:44.47#ibcon#flushed, iclass 20, count 0 2006.257.15:32:44.47#ibcon#about to write, iclass 20, count 0 2006.257.15:32:44.47#ibcon#wrote, iclass 20, count 0 2006.257.15:32:44.47#ibcon#about to read 3, iclass 20, count 0 2006.257.15:32:44.49#ibcon#read 3, iclass 20, count 0 2006.257.15:32:44.49#ibcon#about to read 4, iclass 20, count 0 2006.257.15:32:44.49#ibcon#read 4, iclass 20, count 0 2006.257.15:32:44.49#ibcon#about to read 5, iclass 20, count 0 2006.257.15:32:44.49#ibcon#read 5, iclass 20, count 0 2006.257.15:32:44.49#ibcon#about to read 6, iclass 20, count 0 2006.257.15:32:44.49#ibcon#read 6, iclass 20, count 0 2006.257.15:32:44.49#ibcon#end of sib2, iclass 20, count 0 2006.257.15:32:44.49#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:32:44.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:32:44.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:32:44.49#ibcon#*before write, iclass 20, count 0 2006.257.15:32:44.49#ibcon#enter sib2, iclass 20, count 0 2006.257.15:32:44.49#ibcon#flushed, iclass 20, count 0 2006.257.15:32:44.49#ibcon#about to write, iclass 20, count 0 2006.257.15:32:44.49#ibcon#wrote, iclass 20, count 0 2006.257.15:32:44.49#ibcon#about to read 3, iclass 20, count 0 2006.257.15:32:44.53#ibcon#read 3, iclass 20, count 0 2006.257.15:32:44.53#ibcon#about to read 4, iclass 20, count 0 2006.257.15:32:44.53#ibcon#read 4, iclass 20, count 0 2006.257.15:32:44.53#ibcon#about to read 5, iclass 20, count 0 2006.257.15:32:44.53#ibcon#read 5, iclass 20, count 0 2006.257.15:32:44.53#ibcon#about to read 6, iclass 20, count 0 2006.257.15:32:44.53#ibcon#read 6, iclass 20, count 0 2006.257.15:32:44.53#ibcon#end of sib2, iclass 20, count 0 2006.257.15:32:44.53#ibcon#*after write, iclass 20, count 0 2006.257.15:32:44.53#ibcon#*before return 0, iclass 20, count 0 2006.257.15:32:44.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:44.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:32:44.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:32:44.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:32:44.53$vck44/vb=6,4 2006.257.15:32:44.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.15:32:44.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.15:32:44.53#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:44.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:44.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:44.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:44.59#ibcon#enter wrdev, iclass 22, count 2 2006.257.15:32:44.59#ibcon#first serial, iclass 22, count 2 2006.257.15:32:44.59#ibcon#enter sib2, iclass 22, count 2 2006.257.15:32:44.59#ibcon#flushed, iclass 22, count 2 2006.257.15:32:44.59#ibcon#about to write, iclass 22, count 2 2006.257.15:32:44.59#ibcon#wrote, iclass 22, count 2 2006.257.15:32:44.59#ibcon#about to read 3, iclass 22, count 2 2006.257.15:32:44.61#ibcon#read 3, iclass 22, count 2 2006.257.15:32:44.61#ibcon#about to read 4, iclass 22, count 2 2006.257.15:32:44.61#ibcon#read 4, iclass 22, count 2 2006.257.15:32:44.61#ibcon#about to read 5, iclass 22, count 2 2006.257.15:32:44.61#ibcon#read 5, iclass 22, count 2 2006.257.15:32:44.61#ibcon#about to read 6, iclass 22, count 2 2006.257.15:32:44.61#ibcon#read 6, iclass 22, count 2 2006.257.15:32:44.61#ibcon#end of sib2, iclass 22, count 2 2006.257.15:32:44.61#ibcon#*mode == 0, iclass 22, count 2 2006.257.15:32:44.61#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.15:32:44.61#ibcon#[27=AT06-04\r\n] 2006.257.15:32:44.61#ibcon#*before write, iclass 22, count 2 2006.257.15:32:44.61#ibcon#enter sib2, iclass 22, count 2 2006.257.15:32:44.61#ibcon#flushed, iclass 22, count 2 2006.257.15:32:44.61#ibcon#about to write, iclass 22, count 2 2006.257.15:32:44.61#ibcon#wrote, iclass 22, count 2 2006.257.15:32:44.61#ibcon#about to read 3, iclass 22, count 2 2006.257.15:32:44.64#ibcon#read 3, iclass 22, count 2 2006.257.15:32:44.64#ibcon#about to read 4, iclass 22, count 2 2006.257.15:32:44.64#ibcon#read 4, iclass 22, count 2 2006.257.15:32:44.64#ibcon#about to read 5, iclass 22, count 2 2006.257.15:32:44.64#ibcon#read 5, iclass 22, count 2 2006.257.15:32:44.64#ibcon#about to read 6, iclass 22, count 2 2006.257.15:32:44.64#ibcon#read 6, iclass 22, count 2 2006.257.15:32:44.64#ibcon#end of sib2, iclass 22, count 2 2006.257.15:32:44.64#ibcon#*after write, iclass 22, count 2 2006.257.15:32:44.64#ibcon#*before return 0, iclass 22, count 2 2006.257.15:32:44.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:44.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:32:44.64#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.15:32:44.64#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:44.64#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:44.76#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:44.76#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:44.76#ibcon#enter wrdev, iclass 22, count 0 2006.257.15:32:44.76#ibcon#first serial, iclass 22, count 0 2006.257.15:32:44.76#ibcon#enter sib2, iclass 22, count 0 2006.257.15:32:44.76#ibcon#flushed, iclass 22, count 0 2006.257.15:32:44.76#ibcon#about to write, iclass 22, count 0 2006.257.15:32:44.76#ibcon#wrote, iclass 22, count 0 2006.257.15:32:44.76#ibcon#about to read 3, iclass 22, count 0 2006.257.15:32:44.78#ibcon#read 3, iclass 22, count 0 2006.257.15:32:44.78#ibcon#about to read 4, iclass 22, count 0 2006.257.15:32:44.78#ibcon#read 4, iclass 22, count 0 2006.257.15:32:44.78#ibcon#about to read 5, iclass 22, count 0 2006.257.15:32:44.78#ibcon#read 5, iclass 22, count 0 2006.257.15:32:44.78#ibcon#about to read 6, iclass 22, count 0 2006.257.15:32:44.78#ibcon#read 6, iclass 22, count 0 2006.257.15:32:44.78#ibcon#end of sib2, iclass 22, count 0 2006.257.15:32:44.78#ibcon#*mode == 0, iclass 22, count 0 2006.257.15:32:44.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.15:32:44.78#ibcon#[27=USB\r\n] 2006.257.15:32:44.78#ibcon#*before write, iclass 22, count 0 2006.257.15:32:44.78#ibcon#enter sib2, iclass 22, count 0 2006.257.15:32:44.78#ibcon#flushed, iclass 22, count 0 2006.257.15:32:44.78#ibcon#about to write, iclass 22, count 0 2006.257.15:32:44.78#ibcon#wrote, iclass 22, count 0 2006.257.15:32:44.78#ibcon#about to read 3, iclass 22, count 0 2006.257.15:32:44.81#ibcon#read 3, iclass 22, count 0 2006.257.15:32:44.81#ibcon#about to read 4, iclass 22, count 0 2006.257.15:32:44.81#ibcon#read 4, iclass 22, count 0 2006.257.15:32:44.81#ibcon#about to read 5, iclass 22, count 0 2006.257.15:32:44.81#ibcon#read 5, iclass 22, count 0 2006.257.15:32:44.81#ibcon#about to read 6, iclass 22, count 0 2006.257.15:32:44.81#ibcon#read 6, iclass 22, count 0 2006.257.15:32:44.81#ibcon#end of sib2, iclass 22, count 0 2006.257.15:32:44.81#ibcon#*after write, iclass 22, count 0 2006.257.15:32:44.81#ibcon#*before return 0, iclass 22, count 0 2006.257.15:32:44.81#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:44.81#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:32:44.81#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.15:32:44.81#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.15:32:44.81$vck44/vblo=7,734.99 2006.257.15:32:44.81#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.15:32:44.81#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.15:32:44.81#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:44.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:44.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:44.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:44.81#ibcon#enter wrdev, iclass 24, count 0 2006.257.15:32:44.81#ibcon#first serial, iclass 24, count 0 2006.257.15:32:44.81#ibcon#enter sib2, iclass 24, count 0 2006.257.15:32:44.81#ibcon#flushed, iclass 24, count 0 2006.257.15:32:44.81#ibcon#about to write, iclass 24, count 0 2006.257.15:32:44.81#ibcon#wrote, iclass 24, count 0 2006.257.15:32:44.81#ibcon#about to read 3, iclass 24, count 0 2006.257.15:32:44.83#ibcon#read 3, iclass 24, count 0 2006.257.15:32:44.83#ibcon#about to read 4, iclass 24, count 0 2006.257.15:32:44.83#ibcon#read 4, iclass 24, count 0 2006.257.15:32:44.83#ibcon#about to read 5, iclass 24, count 0 2006.257.15:32:44.83#ibcon#read 5, iclass 24, count 0 2006.257.15:32:44.83#ibcon#about to read 6, iclass 24, count 0 2006.257.15:32:44.83#ibcon#read 6, iclass 24, count 0 2006.257.15:32:44.83#ibcon#end of sib2, iclass 24, count 0 2006.257.15:32:44.83#ibcon#*mode == 0, iclass 24, count 0 2006.257.15:32:44.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.15:32:44.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:32:44.83#ibcon#*before write, iclass 24, count 0 2006.257.15:32:44.83#ibcon#enter sib2, iclass 24, count 0 2006.257.15:32:44.83#ibcon#flushed, iclass 24, count 0 2006.257.15:32:44.83#ibcon#about to write, iclass 24, count 0 2006.257.15:32:44.83#ibcon#wrote, iclass 24, count 0 2006.257.15:32:44.83#ibcon#about to read 3, iclass 24, count 0 2006.257.15:32:44.87#ibcon#read 3, iclass 24, count 0 2006.257.15:32:44.87#ibcon#about to read 4, iclass 24, count 0 2006.257.15:32:44.87#ibcon#read 4, iclass 24, count 0 2006.257.15:32:44.87#ibcon#about to read 5, iclass 24, count 0 2006.257.15:32:44.87#ibcon#read 5, iclass 24, count 0 2006.257.15:32:44.87#ibcon#about to read 6, iclass 24, count 0 2006.257.15:32:44.87#ibcon#read 6, iclass 24, count 0 2006.257.15:32:44.87#ibcon#end of sib2, iclass 24, count 0 2006.257.15:32:44.87#ibcon#*after write, iclass 24, count 0 2006.257.15:32:44.87#ibcon#*before return 0, iclass 24, count 0 2006.257.15:32:44.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:44.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:32:44.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.15:32:44.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.15:32:44.87$vck44/vb=7,4 2006.257.15:32:44.87#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.15:32:44.87#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.15:32:44.87#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:44.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:44.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:44.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:44.93#ibcon#enter wrdev, iclass 26, count 2 2006.257.15:32:44.93#ibcon#first serial, iclass 26, count 2 2006.257.15:32:44.93#ibcon#enter sib2, iclass 26, count 2 2006.257.15:32:44.93#ibcon#flushed, iclass 26, count 2 2006.257.15:32:44.93#ibcon#about to write, iclass 26, count 2 2006.257.15:32:44.93#ibcon#wrote, iclass 26, count 2 2006.257.15:32:44.93#ibcon#about to read 3, iclass 26, count 2 2006.257.15:32:44.95#ibcon#read 3, iclass 26, count 2 2006.257.15:32:44.95#ibcon#about to read 4, iclass 26, count 2 2006.257.15:32:44.95#ibcon#read 4, iclass 26, count 2 2006.257.15:32:44.95#ibcon#about to read 5, iclass 26, count 2 2006.257.15:32:44.95#ibcon#read 5, iclass 26, count 2 2006.257.15:32:44.95#ibcon#about to read 6, iclass 26, count 2 2006.257.15:32:44.95#ibcon#read 6, iclass 26, count 2 2006.257.15:32:44.95#ibcon#end of sib2, iclass 26, count 2 2006.257.15:32:44.95#ibcon#*mode == 0, iclass 26, count 2 2006.257.15:32:44.95#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.15:32:44.95#ibcon#[27=AT07-04\r\n] 2006.257.15:32:44.95#ibcon#*before write, iclass 26, count 2 2006.257.15:32:44.95#ibcon#enter sib2, iclass 26, count 2 2006.257.15:32:44.95#ibcon#flushed, iclass 26, count 2 2006.257.15:32:44.95#ibcon#about to write, iclass 26, count 2 2006.257.15:32:44.95#ibcon#wrote, iclass 26, count 2 2006.257.15:32:44.95#ibcon#about to read 3, iclass 26, count 2 2006.257.15:32:44.98#ibcon#read 3, iclass 26, count 2 2006.257.15:32:44.98#ibcon#about to read 4, iclass 26, count 2 2006.257.15:32:44.98#ibcon#read 4, iclass 26, count 2 2006.257.15:32:44.98#ibcon#about to read 5, iclass 26, count 2 2006.257.15:32:44.98#ibcon#read 5, iclass 26, count 2 2006.257.15:32:44.98#ibcon#about to read 6, iclass 26, count 2 2006.257.15:32:44.98#ibcon#read 6, iclass 26, count 2 2006.257.15:32:44.98#ibcon#end of sib2, iclass 26, count 2 2006.257.15:32:44.98#ibcon#*after write, iclass 26, count 2 2006.257.15:32:44.98#ibcon#*before return 0, iclass 26, count 2 2006.257.15:32:44.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:44.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:32:44.98#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.15:32:44.98#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:44.98#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:45.10#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:45.10#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:45.10#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:32:45.10#ibcon#first serial, iclass 26, count 0 2006.257.15:32:45.10#ibcon#enter sib2, iclass 26, count 0 2006.257.15:32:45.10#ibcon#flushed, iclass 26, count 0 2006.257.15:32:45.10#ibcon#about to write, iclass 26, count 0 2006.257.15:32:45.10#ibcon#wrote, iclass 26, count 0 2006.257.15:32:45.10#ibcon#about to read 3, iclass 26, count 0 2006.257.15:32:45.12#ibcon#read 3, iclass 26, count 0 2006.257.15:32:45.12#ibcon#about to read 4, iclass 26, count 0 2006.257.15:32:45.12#ibcon#read 4, iclass 26, count 0 2006.257.15:32:45.12#ibcon#about to read 5, iclass 26, count 0 2006.257.15:32:45.12#ibcon#read 5, iclass 26, count 0 2006.257.15:32:45.12#ibcon#about to read 6, iclass 26, count 0 2006.257.15:32:45.12#ibcon#read 6, iclass 26, count 0 2006.257.15:32:45.12#ibcon#end of sib2, iclass 26, count 0 2006.257.15:32:45.12#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:32:45.12#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:32:45.12#ibcon#[27=USB\r\n] 2006.257.15:32:45.12#ibcon#*before write, iclass 26, count 0 2006.257.15:32:45.12#ibcon#enter sib2, iclass 26, count 0 2006.257.15:32:45.12#ibcon#flushed, iclass 26, count 0 2006.257.15:32:45.12#ibcon#about to write, iclass 26, count 0 2006.257.15:32:45.12#ibcon#wrote, iclass 26, count 0 2006.257.15:32:45.12#ibcon#about to read 3, iclass 26, count 0 2006.257.15:32:45.15#ibcon#read 3, iclass 26, count 0 2006.257.15:32:45.15#ibcon#about to read 4, iclass 26, count 0 2006.257.15:32:45.15#ibcon#read 4, iclass 26, count 0 2006.257.15:32:45.15#ibcon#about to read 5, iclass 26, count 0 2006.257.15:32:45.15#ibcon#read 5, iclass 26, count 0 2006.257.15:32:45.15#ibcon#about to read 6, iclass 26, count 0 2006.257.15:32:45.15#ibcon#read 6, iclass 26, count 0 2006.257.15:32:45.15#ibcon#end of sib2, iclass 26, count 0 2006.257.15:32:45.15#ibcon#*after write, iclass 26, count 0 2006.257.15:32:45.15#ibcon#*before return 0, iclass 26, count 0 2006.257.15:32:45.15#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:45.15#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:32:45.15#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:32:45.15#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:32:45.15$vck44/vblo=8,744.99 2006.257.15:32:45.15#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.15:32:45.15#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.15:32:45.15#ibcon#ireg 17 cls_cnt 0 2006.257.15:32:45.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:45.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:45.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:45.15#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:32:45.15#ibcon#first serial, iclass 28, count 0 2006.257.15:32:45.15#ibcon#enter sib2, iclass 28, count 0 2006.257.15:32:45.15#ibcon#flushed, iclass 28, count 0 2006.257.15:32:45.15#ibcon#about to write, iclass 28, count 0 2006.257.15:32:45.15#ibcon#wrote, iclass 28, count 0 2006.257.15:32:45.15#ibcon#about to read 3, iclass 28, count 0 2006.257.15:32:45.17#ibcon#read 3, iclass 28, count 0 2006.257.15:32:45.17#ibcon#about to read 4, iclass 28, count 0 2006.257.15:32:45.17#ibcon#read 4, iclass 28, count 0 2006.257.15:32:45.17#ibcon#about to read 5, iclass 28, count 0 2006.257.15:32:45.17#ibcon#read 5, iclass 28, count 0 2006.257.15:32:45.17#ibcon#about to read 6, iclass 28, count 0 2006.257.15:32:45.17#ibcon#read 6, iclass 28, count 0 2006.257.15:32:45.17#ibcon#end of sib2, iclass 28, count 0 2006.257.15:32:45.17#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:32:45.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:32:45.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:32:45.17#ibcon#*before write, iclass 28, count 0 2006.257.15:32:45.17#ibcon#enter sib2, iclass 28, count 0 2006.257.15:32:45.17#ibcon#flushed, iclass 28, count 0 2006.257.15:32:45.17#ibcon#about to write, iclass 28, count 0 2006.257.15:32:45.17#ibcon#wrote, iclass 28, count 0 2006.257.15:32:45.17#ibcon#about to read 3, iclass 28, count 0 2006.257.15:32:45.21#ibcon#read 3, iclass 28, count 0 2006.257.15:32:45.21#ibcon#about to read 4, iclass 28, count 0 2006.257.15:32:45.21#ibcon#read 4, iclass 28, count 0 2006.257.15:32:45.21#ibcon#about to read 5, iclass 28, count 0 2006.257.15:32:45.21#ibcon#read 5, iclass 28, count 0 2006.257.15:32:45.21#ibcon#about to read 6, iclass 28, count 0 2006.257.15:32:45.21#ibcon#read 6, iclass 28, count 0 2006.257.15:32:45.21#ibcon#end of sib2, iclass 28, count 0 2006.257.15:32:45.21#ibcon#*after write, iclass 28, count 0 2006.257.15:32:45.21#ibcon#*before return 0, iclass 28, count 0 2006.257.15:32:45.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:45.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:32:45.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:32:45.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:32:45.21$vck44/vb=8,4 2006.257.15:32:45.21#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.15:32:45.21#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.15:32:45.21#ibcon#ireg 11 cls_cnt 2 2006.257.15:32:45.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:45.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:45.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:45.27#ibcon#enter wrdev, iclass 30, count 2 2006.257.15:32:45.27#ibcon#first serial, iclass 30, count 2 2006.257.15:32:45.27#ibcon#enter sib2, iclass 30, count 2 2006.257.15:32:45.27#ibcon#flushed, iclass 30, count 2 2006.257.15:32:45.27#ibcon#about to write, iclass 30, count 2 2006.257.15:32:45.27#ibcon#wrote, iclass 30, count 2 2006.257.15:32:45.27#ibcon#about to read 3, iclass 30, count 2 2006.257.15:32:45.29#ibcon#read 3, iclass 30, count 2 2006.257.15:32:45.29#ibcon#about to read 4, iclass 30, count 2 2006.257.15:32:45.29#ibcon#read 4, iclass 30, count 2 2006.257.15:32:45.29#ibcon#about to read 5, iclass 30, count 2 2006.257.15:32:45.29#ibcon#read 5, iclass 30, count 2 2006.257.15:32:45.29#ibcon#about to read 6, iclass 30, count 2 2006.257.15:32:45.29#ibcon#read 6, iclass 30, count 2 2006.257.15:32:45.29#ibcon#end of sib2, iclass 30, count 2 2006.257.15:32:45.29#ibcon#*mode == 0, iclass 30, count 2 2006.257.15:32:45.29#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.15:32:45.29#ibcon#[27=AT08-04\r\n] 2006.257.15:32:45.29#ibcon#*before write, iclass 30, count 2 2006.257.15:32:45.29#ibcon#enter sib2, iclass 30, count 2 2006.257.15:32:45.29#ibcon#flushed, iclass 30, count 2 2006.257.15:32:45.29#ibcon#about to write, iclass 30, count 2 2006.257.15:32:45.29#ibcon#wrote, iclass 30, count 2 2006.257.15:32:45.29#ibcon#about to read 3, iclass 30, count 2 2006.257.15:32:45.32#ibcon#read 3, iclass 30, count 2 2006.257.15:32:45.32#ibcon#about to read 4, iclass 30, count 2 2006.257.15:32:45.32#ibcon#read 4, iclass 30, count 2 2006.257.15:32:45.32#ibcon#about to read 5, iclass 30, count 2 2006.257.15:32:45.32#ibcon#read 5, iclass 30, count 2 2006.257.15:32:45.32#ibcon#about to read 6, iclass 30, count 2 2006.257.15:32:45.32#ibcon#read 6, iclass 30, count 2 2006.257.15:32:45.32#ibcon#end of sib2, iclass 30, count 2 2006.257.15:32:45.32#ibcon#*after write, iclass 30, count 2 2006.257.15:32:45.32#ibcon#*before return 0, iclass 30, count 2 2006.257.15:32:45.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:45.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:32:45.32#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.15:32:45.32#ibcon#ireg 7 cls_cnt 0 2006.257.15:32:45.32#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:45.44#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:45.44#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:45.44#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:32:45.44#ibcon#first serial, iclass 30, count 0 2006.257.15:32:45.44#ibcon#enter sib2, iclass 30, count 0 2006.257.15:32:45.44#ibcon#flushed, iclass 30, count 0 2006.257.15:32:45.44#ibcon#about to write, iclass 30, count 0 2006.257.15:32:45.44#ibcon#wrote, iclass 30, count 0 2006.257.15:32:45.44#ibcon#about to read 3, iclass 30, count 0 2006.257.15:32:45.46#ibcon#read 3, iclass 30, count 0 2006.257.15:32:45.46#ibcon#about to read 4, iclass 30, count 0 2006.257.15:32:45.46#ibcon#read 4, iclass 30, count 0 2006.257.15:32:45.46#ibcon#about to read 5, iclass 30, count 0 2006.257.15:32:45.46#ibcon#read 5, iclass 30, count 0 2006.257.15:32:45.46#ibcon#about to read 6, iclass 30, count 0 2006.257.15:32:45.46#ibcon#read 6, iclass 30, count 0 2006.257.15:32:45.46#ibcon#end of sib2, iclass 30, count 0 2006.257.15:32:45.46#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:32:45.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:32:45.46#ibcon#[27=USB\r\n] 2006.257.15:32:45.46#ibcon#*before write, iclass 30, count 0 2006.257.15:32:45.46#ibcon#enter sib2, iclass 30, count 0 2006.257.15:32:45.46#ibcon#flushed, iclass 30, count 0 2006.257.15:32:45.46#ibcon#about to write, iclass 30, count 0 2006.257.15:32:45.46#ibcon#wrote, iclass 30, count 0 2006.257.15:32:45.46#ibcon#about to read 3, iclass 30, count 0 2006.257.15:32:45.49#ibcon#read 3, iclass 30, count 0 2006.257.15:32:45.49#ibcon#about to read 4, iclass 30, count 0 2006.257.15:32:45.49#ibcon#read 4, iclass 30, count 0 2006.257.15:32:45.49#ibcon#about to read 5, iclass 30, count 0 2006.257.15:32:45.49#ibcon#read 5, iclass 30, count 0 2006.257.15:32:45.49#ibcon#about to read 6, iclass 30, count 0 2006.257.15:32:45.49#ibcon#read 6, iclass 30, count 0 2006.257.15:32:45.49#ibcon#end of sib2, iclass 30, count 0 2006.257.15:32:45.49#ibcon#*after write, iclass 30, count 0 2006.257.15:32:45.49#ibcon#*before return 0, iclass 30, count 0 2006.257.15:32:45.49#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:45.49#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:32:45.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:32:45.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:32:45.49$vck44/vabw=wide 2006.257.15:32:45.49#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.15:32:45.49#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.15:32:45.49#ibcon#ireg 8 cls_cnt 0 2006.257.15:32:45.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:45.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:45.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:45.49#ibcon#enter wrdev, iclass 32, count 0 2006.257.15:32:45.49#ibcon#first serial, iclass 32, count 0 2006.257.15:32:45.49#ibcon#enter sib2, iclass 32, count 0 2006.257.15:32:45.49#ibcon#flushed, iclass 32, count 0 2006.257.15:32:45.49#ibcon#about to write, iclass 32, count 0 2006.257.15:32:45.49#ibcon#wrote, iclass 32, count 0 2006.257.15:32:45.49#ibcon#about to read 3, iclass 32, count 0 2006.257.15:32:45.51#ibcon#read 3, iclass 32, count 0 2006.257.15:32:45.51#ibcon#about to read 4, iclass 32, count 0 2006.257.15:32:45.51#ibcon#read 4, iclass 32, count 0 2006.257.15:32:45.51#ibcon#about to read 5, iclass 32, count 0 2006.257.15:32:45.51#ibcon#read 5, iclass 32, count 0 2006.257.15:32:45.51#ibcon#about to read 6, iclass 32, count 0 2006.257.15:32:45.51#ibcon#read 6, iclass 32, count 0 2006.257.15:32:45.51#ibcon#end of sib2, iclass 32, count 0 2006.257.15:32:45.51#ibcon#*mode == 0, iclass 32, count 0 2006.257.15:32:45.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.15:32:45.51#ibcon#[25=BW32\r\n] 2006.257.15:32:45.51#ibcon#*before write, iclass 32, count 0 2006.257.15:32:45.51#ibcon#enter sib2, iclass 32, count 0 2006.257.15:32:45.51#ibcon#flushed, iclass 32, count 0 2006.257.15:32:45.51#ibcon#about to write, iclass 32, count 0 2006.257.15:32:45.51#ibcon#wrote, iclass 32, count 0 2006.257.15:32:45.51#ibcon#about to read 3, iclass 32, count 0 2006.257.15:32:45.54#ibcon#read 3, iclass 32, count 0 2006.257.15:32:45.54#ibcon#about to read 4, iclass 32, count 0 2006.257.15:32:45.54#ibcon#read 4, iclass 32, count 0 2006.257.15:32:45.54#ibcon#about to read 5, iclass 32, count 0 2006.257.15:32:45.54#ibcon#read 5, iclass 32, count 0 2006.257.15:32:45.54#ibcon#about to read 6, iclass 32, count 0 2006.257.15:32:45.54#ibcon#read 6, iclass 32, count 0 2006.257.15:32:45.54#ibcon#end of sib2, iclass 32, count 0 2006.257.15:32:45.54#ibcon#*after write, iclass 32, count 0 2006.257.15:32:45.54#ibcon#*before return 0, iclass 32, count 0 2006.257.15:32:45.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:45.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:32:45.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.15:32:45.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.15:32:45.54$vck44/vbbw=wide 2006.257.15:32:45.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.15:32:45.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.15:32:45.54#ibcon#ireg 8 cls_cnt 0 2006.257.15:32:45.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:32:45.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:32:45.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:32:45.61#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:32:45.61#ibcon#first serial, iclass 34, count 0 2006.257.15:32:45.61#ibcon#enter sib2, iclass 34, count 0 2006.257.15:32:45.61#ibcon#flushed, iclass 34, count 0 2006.257.15:32:45.61#ibcon#about to write, iclass 34, count 0 2006.257.15:32:45.61#ibcon#wrote, iclass 34, count 0 2006.257.15:32:45.61#ibcon#about to read 3, iclass 34, count 0 2006.257.15:32:45.63#ibcon#read 3, iclass 34, count 0 2006.257.15:32:45.63#ibcon#about to read 4, iclass 34, count 0 2006.257.15:32:45.63#ibcon#read 4, iclass 34, count 0 2006.257.15:32:45.63#ibcon#about to read 5, iclass 34, count 0 2006.257.15:32:45.63#ibcon#read 5, iclass 34, count 0 2006.257.15:32:45.63#ibcon#about to read 6, iclass 34, count 0 2006.257.15:32:45.63#ibcon#read 6, iclass 34, count 0 2006.257.15:32:45.63#ibcon#end of sib2, iclass 34, count 0 2006.257.15:32:45.63#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:32:45.63#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:32:45.63#ibcon#[27=BW32\r\n] 2006.257.15:32:45.63#ibcon#*before write, iclass 34, count 0 2006.257.15:32:45.63#ibcon#enter sib2, iclass 34, count 0 2006.257.15:32:45.63#ibcon#flushed, iclass 34, count 0 2006.257.15:32:45.63#ibcon#about to write, iclass 34, count 0 2006.257.15:32:45.63#ibcon#wrote, iclass 34, count 0 2006.257.15:32:45.63#ibcon#about to read 3, iclass 34, count 0 2006.257.15:32:45.66#ibcon#read 3, iclass 34, count 0 2006.257.15:32:45.66#ibcon#about to read 4, iclass 34, count 0 2006.257.15:32:45.66#ibcon#read 4, iclass 34, count 0 2006.257.15:32:45.66#ibcon#about to read 5, iclass 34, count 0 2006.257.15:32:45.66#ibcon#read 5, iclass 34, count 0 2006.257.15:32:45.66#ibcon#about to read 6, iclass 34, count 0 2006.257.15:32:45.66#ibcon#read 6, iclass 34, count 0 2006.257.15:32:45.66#ibcon#end of sib2, iclass 34, count 0 2006.257.15:32:45.66#ibcon#*after write, iclass 34, count 0 2006.257.15:32:45.66#ibcon#*before return 0, iclass 34, count 0 2006.257.15:32:45.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:32:45.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:32:45.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:32:45.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:32:45.66$setupk4/ifdk4 2006.257.15:32:45.66$ifdk4/lo= 2006.257.15:32:45.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:32:45.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:32:45.66$ifdk4/patch= 2006.257.15:32:45.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:32:45.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:32:45.66$setupk4/!*+20s 2006.257.15:32:46.31#abcon#<5=/14 1.2 3.1 17.46 961013.9\r\n> 2006.257.15:32:46.33#abcon#{5=INTERFACE CLEAR} 2006.257.15:32:46.39#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:32:56.48#abcon#<5=/14 1.2 3.1 17.45 961013.9\r\n> 2006.257.15:32:56.50#abcon#{5=INTERFACE CLEAR} 2006.257.15:32:56.56#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:33:00.17$setupk4/"tpicd 2006.257.15:33:00.17$setupk4/echo=off 2006.257.15:33:00.17$setupk4/xlog=off 2006.257.15:33:00.17:!2006.257.15:33:57 2006.257.15:33:04.14#trakl#Source acquired 2006.257.15:33:05.14#flagr#flagr/antenna,acquired 2006.257.15:33:57.00:preob 2006.257.15:33:57.14/onsource/TRACKING 2006.257.15:33:57.14:!2006.257.15:34:07 2006.257.15:34:07.00:"tape 2006.257.15:34:07.00:"st=record 2006.257.15:34:07.00:data_valid=on 2006.257.15:34:07.00:midob 2006.257.15:34:08.14/onsource/TRACKING 2006.257.15:34:08.14/wx/17.44,1013.9,96 2006.257.15:34:08.24/cable/+6.4842E-03 2006.257.15:34:09.33/va/01,08,usb,yes,30,33 2006.257.15:34:09.33/va/02,07,usb,yes,33,33 2006.257.15:34:09.33/va/03,08,usb,yes,29,31 2006.257.15:34:09.33/va/04,07,usb,yes,34,35 2006.257.15:34:09.33/va/05,04,usb,yes,30,31 2006.257.15:34:09.33/va/06,04,usb,yes,34,33 2006.257.15:34:09.33/va/07,04,usb,yes,35,35 2006.257.15:34:09.33/va/08,04,usb,yes,29,36 2006.257.15:34:09.56/valo/01,524.99,yes,locked 2006.257.15:34:09.56/valo/02,534.99,yes,locked 2006.257.15:34:09.56/valo/03,564.99,yes,locked 2006.257.15:34:09.56/valo/04,624.99,yes,locked 2006.257.15:34:09.56/valo/05,734.99,yes,locked 2006.257.15:34:09.56/valo/06,814.99,yes,locked 2006.257.15:34:09.56/valo/07,864.99,yes,locked 2006.257.15:34:09.56/valo/08,884.99,yes,locked 2006.257.15:34:10.65/vb/01,04,usb,yes,30,28 2006.257.15:34:10.65/vb/02,05,usb,yes,28,28 2006.257.15:34:10.65/vb/03,04,usb,yes,29,32 2006.257.15:34:10.65/vb/04,05,usb,yes,30,28 2006.257.15:34:10.65/vb/05,04,usb,yes,26,28 2006.257.15:34:10.65/vb/06,04,usb,yes,31,27 2006.257.15:34:10.65/vb/07,04,usb,yes,30,30 2006.257.15:34:10.65/vb/08,04,usb,yes,28,31 2006.257.15:34:10.88/vblo/01,629.99,yes,locked 2006.257.15:34:10.88/vblo/02,634.99,yes,locked 2006.257.15:34:10.88/vblo/03,649.99,yes,locked 2006.257.15:34:10.88/vblo/04,679.99,yes,locked 2006.257.15:34:10.88/vblo/05,709.99,yes,locked 2006.257.15:34:10.88/vblo/06,719.99,yes,locked 2006.257.15:34:10.88/vblo/07,734.99,yes,locked 2006.257.15:34:10.88/vblo/08,744.99,yes,locked 2006.257.15:34:11.03/vabw/8 2006.257.15:34:11.18/vbbw/8 2006.257.15:34:11.27/xfe/off,on,15.2 2006.257.15:34:11.65/ifatt/23,28,28,28 2006.257.15:34:12.07/fmout-gps/S +4.56E-07 2006.257.15:34:12.11:!2006.257.15:35:27 2006.257.15:35:27.00:data_valid=off 2006.257.15:35:27.00:"et 2006.257.15:35:27.00:!+3s 2006.257.15:35:30.01:"tape 2006.257.15:35:30.01:postob 2006.257.15:35:30.17/cable/+6.4849E-03 2006.257.15:35:30.17/wx/17.43,1013.9,97 2006.257.15:35:31.07/fmout-gps/S +4.57E-07 2006.257.15:35:31.07:scan_name=257-1539,jd0609,170 2006.257.15:35:31.07:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.15:35:32.14#flagr#flagr/antenna,new-source 2006.257.15:35:32.14:checkk5 2006.257.15:35:32.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:35:32.94/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:35:33.37/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:35:33.75/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:35:34.14/chk_obsdata//k5ts1/T2571534??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.15:35:34.53/chk_obsdata//k5ts2/T2571534??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.15:35:34.94/chk_obsdata//k5ts3/T2571534??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.15:35:35.34/chk_obsdata//k5ts4/T2571534??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.15:35:36.05/k5log//k5ts1_log_newline 2006.257.15:35:36.76/k5log//k5ts2_log_newline 2006.257.15:35:37.49/k5log//k5ts3_log_newline 2006.257.15:35:38.21/k5log//k5ts4_log_newline 2006.257.15:35:38.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:35:38.23:setupk4=1 2006.257.15:35:38.23$setupk4/echo=on 2006.257.15:35:38.23$setupk4/pcalon 2006.257.15:35:38.23$pcalon/"no phase cal control is implemented here 2006.257.15:35:38.23$setupk4/"tpicd=stop 2006.257.15:35:38.23$setupk4/"rec=synch_on 2006.257.15:35:38.23$setupk4/"rec_mode=128 2006.257.15:35:38.23$setupk4/!* 2006.257.15:35:38.23$setupk4/recpk4 2006.257.15:35:38.23$recpk4/recpatch= 2006.257.15:35:38.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:35:38.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:35:38.24$setupk4/vck44 2006.257.15:35:38.24$vck44/valo=1,524.99 2006.257.15:35:38.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.15:35:38.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.15:35:38.24#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:38.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:38.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:38.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:38.24#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:35:38.24#ibcon#first serial, iclass 35, count 0 2006.257.15:35:38.24#ibcon#enter sib2, iclass 35, count 0 2006.257.15:35:38.24#ibcon#flushed, iclass 35, count 0 2006.257.15:35:38.24#ibcon#about to write, iclass 35, count 0 2006.257.15:35:38.24#ibcon#wrote, iclass 35, count 0 2006.257.15:35:38.24#ibcon#about to read 3, iclass 35, count 0 2006.257.15:35:38.26#ibcon#read 3, iclass 35, count 0 2006.257.15:35:38.26#ibcon#about to read 4, iclass 35, count 0 2006.257.15:35:38.26#ibcon#read 4, iclass 35, count 0 2006.257.15:35:38.26#ibcon#about to read 5, iclass 35, count 0 2006.257.15:35:38.26#ibcon#read 5, iclass 35, count 0 2006.257.15:35:38.26#ibcon#about to read 6, iclass 35, count 0 2006.257.15:35:38.26#ibcon#read 6, iclass 35, count 0 2006.257.15:35:38.26#ibcon#end of sib2, iclass 35, count 0 2006.257.15:35:38.26#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:35:38.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:35:38.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:35:38.26#ibcon#*before write, iclass 35, count 0 2006.257.15:35:38.26#ibcon#enter sib2, iclass 35, count 0 2006.257.15:35:38.26#ibcon#flushed, iclass 35, count 0 2006.257.15:35:38.26#ibcon#about to write, iclass 35, count 0 2006.257.15:35:38.26#ibcon#wrote, iclass 35, count 0 2006.257.15:35:38.26#ibcon#about to read 3, iclass 35, count 0 2006.257.15:35:38.31#ibcon#read 3, iclass 35, count 0 2006.257.15:35:38.31#ibcon#about to read 4, iclass 35, count 0 2006.257.15:35:38.31#ibcon#read 4, iclass 35, count 0 2006.257.15:35:38.31#ibcon#about to read 5, iclass 35, count 0 2006.257.15:35:38.31#ibcon#read 5, iclass 35, count 0 2006.257.15:35:38.31#ibcon#about to read 6, iclass 35, count 0 2006.257.15:35:38.31#ibcon#read 6, iclass 35, count 0 2006.257.15:35:38.31#ibcon#end of sib2, iclass 35, count 0 2006.257.15:35:38.31#ibcon#*after write, iclass 35, count 0 2006.257.15:35:38.31#ibcon#*before return 0, iclass 35, count 0 2006.257.15:35:38.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:38.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:38.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:35:38.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:35:38.31$vck44/va=1,8 2006.257.15:35:38.31#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.15:35:38.31#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.15:35:38.31#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:38.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:38.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:38.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:38.31#ibcon#enter wrdev, iclass 37, count 2 2006.257.15:35:38.31#ibcon#first serial, iclass 37, count 2 2006.257.15:35:38.31#ibcon#enter sib2, iclass 37, count 2 2006.257.15:35:38.31#ibcon#flushed, iclass 37, count 2 2006.257.15:35:38.31#ibcon#about to write, iclass 37, count 2 2006.257.15:35:38.31#ibcon#wrote, iclass 37, count 2 2006.257.15:35:38.31#ibcon#about to read 3, iclass 37, count 2 2006.257.15:35:38.33#ibcon#read 3, iclass 37, count 2 2006.257.15:35:38.33#ibcon#about to read 4, iclass 37, count 2 2006.257.15:35:38.33#ibcon#read 4, iclass 37, count 2 2006.257.15:35:38.33#ibcon#about to read 5, iclass 37, count 2 2006.257.15:35:38.33#ibcon#read 5, iclass 37, count 2 2006.257.15:35:38.33#ibcon#about to read 6, iclass 37, count 2 2006.257.15:35:38.33#ibcon#read 6, iclass 37, count 2 2006.257.15:35:38.33#ibcon#end of sib2, iclass 37, count 2 2006.257.15:35:38.33#ibcon#*mode == 0, iclass 37, count 2 2006.257.15:35:38.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.15:35:38.33#ibcon#[25=AT01-08\r\n] 2006.257.15:35:38.33#ibcon#*before write, iclass 37, count 2 2006.257.15:35:38.33#ibcon#enter sib2, iclass 37, count 2 2006.257.15:35:38.33#ibcon#flushed, iclass 37, count 2 2006.257.15:35:38.33#ibcon#about to write, iclass 37, count 2 2006.257.15:35:38.33#ibcon#wrote, iclass 37, count 2 2006.257.15:35:38.33#ibcon#about to read 3, iclass 37, count 2 2006.257.15:35:38.36#ibcon#read 3, iclass 37, count 2 2006.257.15:35:38.36#ibcon#about to read 4, iclass 37, count 2 2006.257.15:35:38.36#ibcon#read 4, iclass 37, count 2 2006.257.15:35:38.36#ibcon#about to read 5, iclass 37, count 2 2006.257.15:35:38.36#ibcon#read 5, iclass 37, count 2 2006.257.15:35:38.36#ibcon#about to read 6, iclass 37, count 2 2006.257.15:35:38.36#ibcon#read 6, iclass 37, count 2 2006.257.15:35:38.36#ibcon#end of sib2, iclass 37, count 2 2006.257.15:35:38.36#ibcon#*after write, iclass 37, count 2 2006.257.15:35:38.36#ibcon#*before return 0, iclass 37, count 2 2006.257.15:35:38.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:38.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:38.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.15:35:38.36#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:38.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:38.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:38.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:38.48#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:35:38.48#ibcon#first serial, iclass 37, count 0 2006.257.15:35:38.48#ibcon#enter sib2, iclass 37, count 0 2006.257.15:35:38.48#ibcon#flushed, iclass 37, count 0 2006.257.15:35:38.48#ibcon#about to write, iclass 37, count 0 2006.257.15:35:38.48#ibcon#wrote, iclass 37, count 0 2006.257.15:35:38.48#ibcon#about to read 3, iclass 37, count 0 2006.257.15:35:38.50#ibcon#read 3, iclass 37, count 0 2006.257.15:35:38.50#ibcon#about to read 4, iclass 37, count 0 2006.257.15:35:38.50#ibcon#read 4, iclass 37, count 0 2006.257.15:35:38.50#ibcon#about to read 5, iclass 37, count 0 2006.257.15:35:38.50#ibcon#read 5, iclass 37, count 0 2006.257.15:35:38.50#ibcon#about to read 6, iclass 37, count 0 2006.257.15:35:38.50#ibcon#read 6, iclass 37, count 0 2006.257.15:35:38.50#ibcon#end of sib2, iclass 37, count 0 2006.257.15:35:38.50#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:35:38.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:35:38.50#ibcon#[25=USB\r\n] 2006.257.15:35:38.50#ibcon#*before write, iclass 37, count 0 2006.257.15:35:38.50#ibcon#enter sib2, iclass 37, count 0 2006.257.15:35:38.50#ibcon#flushed, iclass 37, count 0 2006.257.15:35:38.50#ibcon#about to write, iclass 37, count 0 2006.257.15:35:38.50#ibcon#wrote, iclass 37, count 0 2006.257.15:35:38.50#ibcon#about to read 3, iclass 37, count 0 2006.257.15:35:38.53#ibcon#read 3, iclass 37, count 0 2006.257.15:35:38.53#ibcon#about to read 4, iclass 37, count 0 2006.257.15:35:38.53#ibcon#read 4, iclass 37, count 0 2006.257.15:35:38.53#ibcon#about to read 5, iclass 37, count 0 2006.257.15:35:38.53#ibcon#read 5, iclass 37, count 0 2006.257.15:35:38.53#ibcon#about to read 6, iclass 37, count 0 2006.257.15:35:38.53#ibcon#read 6, iclass 37, count 0 2006.257.15:35:38.53#ibcon#end of sib2, iclass 37, count 0 2006.257.15:35:38.53#ibcon#*after write, iclass 37, count 0 2006.257.15:35:38.53#ibcon#*before return 0, iclass 37, count 0 2006.257.15:35:38.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:38.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:38.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:35:38.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:35:38.53$vck44/valo=2,534.99 2006.257.15:35:38.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.15:35:38.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.15:35:38.53#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:38.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:38.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:38.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:38.53#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:35:38.53#ibcon#first serial, iclass 39, count 0 2006.257.15:35:38.53#ibcon#enter sib2, iclass 39, count 0 2006.257.15:35:38.53#ibcon#flushed, iclass 39, count 0 2006.257.15:35:38.53#ibcon#about to write, iclass 39, count 0 2006.257.15:35:38.53#ibcon#wrote, iclass 39, count 0 2006.257.15:35:38.53#ibcon#about to read 3, iclass 39, count 0 2006.257.15:35:38.55#ibcon#read 3, iclass 39, count 0 2006.257.15:35:38.55#ibcon#about to read 4, iclass 39, count 0 2006.257.15:35:38.55#ibcon#read 4, iclass 39, count 0 2006.257.15:35:38.55#ibcon#about to read 5, iclass 39, count 0 2006.257.15:35:38.55#ibcon#read 5, iclass 39, count 0 2006.257.15:35:38.55#ibcon#about to read 6, iclass 39, count 0 2006.257.15:35:38.55#ibcon#read 6, iclass 39, count 0 2006.257.15:35:38.55#ibcon#end of sib2, iclass 39, count 0 2006.257.15:35:38.55#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:35:38.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:35:38.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:35:38.55#ibcon#*before write, iclass 39, count 0 2006.257.15:35:38.55#ibcon#enter sib2, iclass 39, count 0 2006.257.15:35:38.55#ibcon#flushed, iclass 39, count 0 2006.257.15:35:38.55#ibcon#about to write, iclass 39, count 0 2006.257.15:35:38.55#ibcon#wrote, iclass 39, count 0 2006.257.15:35:38.55#ibcon#about to read 3, iclass 39, count 0 2006.257.15:35:38.59#ibcon#read 3, iclass 39, count 0 2006.257.15:35:38.59#ibcon#about to read 4, iclass 39, count 0 2006.257.15:35:38.59#ibcon#read 4, iclass 39, count 0 2006.257.15:35:38.59#ibcon#about to read 5, iclass 39, count 0 2006.257.15:35:38.59#ibcon#read 5, iclass 39, count 0 2006.257.15:35:38.59#ibcon#about to read 6, iclass 39, count 0 2006.257.15:35:38.59#ibcon#read 6, iclass 39, count 0 2006.257.15:35:38.59#ibcon#end of sib2, iclass 39, count 0 2006.257.15:35:38.59#ibcon#*after write, iclass 39, count 0 2006.257.15:35:38.59#ibcon#*before return 0, iclass 39, count 0 2006.257.15:35:38.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:38.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:38.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:35:38.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:35:38.59$vck44/va=2,7 2006.257.15:35:38.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.15:35:38.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.15:35:38.59#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:38.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:38.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:38.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:38.65#ibcon#enter wrdev, iclass 3, count 2 2006.257.15:35:38.65#ibcon#first serial, iclass 3, count 2 2006.257.15:35:38.65#ibcon#enter sib2, iclass 3, count 2 2006.257.15:35:38.65#ibcon#flushed, iclass 3, count 2 2006.257.15:35:38.65#ibcon#about to write, iclass 3, count 2 2006.257.15:35:38.65#ibcon#wrote, iclass 3, count 2 2006.257.15:35:38.65#ibcon#about to read 3, iclass 3, count 2 2006.257.15:35:38.67#ibcon#read 3, iclass 3, count 2 2006.257.15:35:38.67#ibcon#about to read 4, iclass 3, count 2 2006.257.15:35:38.67#ibcon#read 4, iclass 3, count 2 2006.257.15:35:38.67#ibcon#about to read 5, iclass 3, count 2 2006.257.15:35:38.67#ibcon#read 5, iclass 3, count 2 2006.257.15:35:38.67#ibcon#about to read 6, iclass 3, count 2 2006.257.15:35:38.67#ibcon#read 6, iclass 3, count 2 2006.257.15:35:38.67#ibcon#end of sib2, iclass 3, count 2 2006.257.15:35:38.67#ibcon#*mode == 0, iclass 3, count 2 2006.257.15:35:38.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.15:35:38.67#ibcon#[25=AT02-07\r\n] 2006.257.15:35:38.67#ibcon#*before write, iclass 3, count 2 2006.257.15:35:38.67#ibcon#enter sib2, iclass 3, count 2 2006.257.15:35:38.67#ibcon#flushed, iclass 3, count 2 2006.257.15:35:38.67#ibcon#about to write, iclass 3, count 2 2006.257.15:35:38.67#ibcon#wrote, iclass 3, count 2 2006.257.15:35:38.67#ibcon#about to read 3, iclass 3, count 2 2006.257.15:35:38.70#ibcon#read 3, iclass 3, count 2 2006.257.15:35:38.70#ibcon#about to read 4, iclass 3, count 2 2006.257.15:35:38.70#ibcon#read 4, iclass 3, count 2 2006.257.15:35:38.70#ibcon#about to read 5, iclass 3, count 2 2006.257.15:35:38.70#ibcon#read 5, iclass 3, count 2 2006.257.15:35:38.70#ibcon#about to read 6, iclass 3, count 2 2006.257.15:35:38.70#ibcon#read 6, iclass 3, count 2 2006.257.15:35:38.70#ibcon#end of sib2, iclass 3, count 2 2006.257.15:35:38.70#ibcon#*after write, iclass 3, count 2 2006.257.15:35:38.70#ibcon#*before return 0, iclass 3, count 2 2006.257.15:35:38.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:38.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:38.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.15:35:38.70#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:38.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:38.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:38.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:38.82#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:35:38.82#ibcon#first serial, iclass 3, count 0 2006.257.15:35:38.82#ibcon#enter sib2, iclass 3, count 0 2006.257.15:35:38.82#ibcon#flushed, iclass 3, count 0 2006.257.15:35:38.82#ibcon#about to write, iclass 3, count 0 2006.257.15:35:38.82#ibcon#wrote, iclass 3, count 0 2006.257.15:35:38.82#ibcon#about to read 3, iclass 3, count 0 2006.257.15:35:38.84#ibcon#read 3, iclass 3, count 0 2006.257.15:35:38.84#ibcon#about to read 4, iclass 3, count 0 2006.257.15:35:38.84#ibcon#read 4, iclass 3, count 0 2006.257.15:35:38.84#ibcon#about to read 5, iclass 3, count 0 2006.257.15:35:38.84#ibcon#read 5, iclass 3, count 0 2006.257.15:35:38.84#ibcon#about to read 6, iclass 3, count 0 2006.257.15:35:38.84#ibcon#read 6, iclass 3, count 0 2006.257.15:35:38.84#ibcon#end of sib2, iclass 3, count 0 2006.257.15:35:38.84#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:35:38.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:35:38.84#ibcon#[25=USB\r\n] 2006.257.15:35:38.84#ibcon#*before write, iclass 3, count 0 2006.257.15:35:38.84#ibcon#enter sib2, iclass 3, count 0 2006.257.15:35:38.84#ibcon#flushed, iclass 3, count 0 2006.257.15:35:38.84#ibcon#about to write, iclass 3, count 0 2006.257.15:35:38.84#ibcon#wrote, iclass 3, count 0 2006.257.15:35:38.84#ibcon#about to read 3, iclass 3, count 0 2006.257.15:35:38.87#ibcon#read 3, iclass 3, count 0 2006.257.15:35:38.87#ibcon#about to read 4, iclass 3, count 0 2006.257.15:35:38.87#ibcon#read 4, iclass 3, count 0 2006.257.15:35:38.87#ibcon#about to read 5, iclass 3, count 0 2006.257.15:35:38.87#ibcon#read 5, iclass 3, count 0 2006.257.15:35:38.87#ibcon#about to read 6, iclass 3, count 0 2006.257.15:35:38.87#ibcon#read 6, iclass 3, count 0 2006.257.15:35:38.87#ibcon#end of sib2, iclass 3, count 0 2006.257.15:35:38.87#ibcon#*after write, iclass 3, count 0 2006.257.15:35:38.87#ibcon#*before return 0, iclass 3, count 0 2006.257.15:35:38.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:38.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:38.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:35:38.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:35:38.87$vck44/valo=3,564.99 2006.257.15:35:38.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.15:35:38.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.15:35:38.87#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:38.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:38.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:38.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:38.87#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:35:38.87#ibcon#first serial, iclass 5, count 0 2006.257.15:35:38.87#ibcon#enter sib2, iclass 5, count 0 2006.257.15:35:38.87#ibcon#flushed, iclass 5, count 0 2006.257.15:35:38.87#ibcon#about to write, iclass 5, count 0 2006.257.15:35:38.87#ibcon#wrote, iclass 5, count 0 2006.257.15:35:38.87#ibcon#about to read 3, iclass 5, count 0 2006.257.15:35:38.89#ibcon#read 3, iclass 5, count 0 2006.257.15:35:38.89#ibcon#about to read 4, iclass 5, count 0 2006.257.15:35:38.89#ibcon#read 4, iclass 5, count 0 2006.257.15:35:38.89#ibcon#about to read 5, iclass 5, count 0 2006.257.15:35:38.89#ibcon#read 5, iclass 5, count 0 2006.257.15:35:38.89#ibcon#about to read 6, iclass 5, count 0 2006.257.15:35:38.89#ibcon#read 6, iclass 5, count 0 2006.257.15:35:38.89#ibcon#end of sib2, iclass 5, count 0 2006.257.15:35:38.89#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:35:38.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:35:38.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:35:38.89#ibcon#*before write, iclass 5, count 0 2006.257.15:35:38.89#ibcon#enter sib2, iclass 5, count 0 2006.257.15:35:38.89#ibcon#flushed, iclass 5, count 0 2006.257.15:35:38.89#ibcon#about to write, iclass 5, count 0 2006.257.15:35:38.89#ibcon#wrote, iclass 5, count 0 2006.257.15:35:38.89#ibcon#about to read 3, iclass 5, count 0 2006.257.15:35:38.93#ibcon#read 3, iclass 5, count 0 2006.257.15:35:38.93#ibcon#about to read 4, iclass 5, count 0 2006.257.15:35:38.93#ibcon#read 4, iclass 5, count 0 2006.257.15:35:38.93#ibcon#about to read 5, iclass 5, count 0 2006.257.15:35:38.93#ibcon#read 5, iclass 5, count 0 2006.257.15:35:38.93#ibcon#about to read 6, iclass 5, count 0 2006.257.15:35:38.93#ibcon#read 6, iclass 5, count 0 2006.257.15:35:38.93#ibcon#end of sib2, iclass 5, count 0 2006.257.15:35:38.93#ibcon#*after write, iclass 5, count 0 2006.257.15:35:38.93#ibcon#*before return 0, iclass 5, count 0 2006.257.15:35:38.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:38.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:38.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:35:38.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:35:38.93$vck44/va=3,8 2006.257.15:35:38.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.15:35:38.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.15:35:38.93#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:38.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:38.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:38.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:38.99#ibcon#enter wrdev, iclass 7, count 2 2006.257.15:35:38.99#ibcon#first serial, iclass 7, count 2 2006.257.15:35:38.99#ibcon#enter sib2, iclass 7, count 2 2006.257.15:35:38.99#ibcon#flushed, iclass 7, count 2 2006.257.15:35:38.99#ibcon#about to write, iclass 7, count 2 2006.257.15:35:38.99#ibcon#wrote, iclass 7, count 2 2006.257.15:35:38.99#ibcon#about to read 3, iclass 7, count 2 2006.257.15:35:39.01#ibcon#read 3, iclass 7, count 2 2006.257.15:35:39.01#ibcon#about to read 4, iclass 7, count 2 2006.257.15:35:39.01#ibcon#read 4, iclass 7, count 2 2006.257.15:35:39.01#ibcon#about to read 5, iclass 7, count 2 2006.257.15:35:39.01#ibcon#read 5, iclass 7, count 2 2006.257.15:35:39.01#ibcon#about to read 6, iclass 7, count 2 2006.257.15:35:39.01#ibcon#read 6, iclass 7, count 2 2006.257.15:35:39.01#ibcon#end of sib2, iclass 7, count 2 2006.257.15:35:39.01#ibcon#*mode == 0, iclass 7, count 2 2006.257.15:35:39.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.15:35:39.01#ibcon#[25=AT03-08\r\n] 2006.257.15:35:39.01#ibcon#*before write, iclass 7, count 2 2006.257.15:35:39.01#ibcon#enter sib2, iclass 7, count 2 2006.257.15:35:39.01#ibcon#flushed, iclass 7, count 2 2006.257.15:35:39.01#ibcon#about to write, iclass 7, count 2 2006.257.15:35:39.01#ibcon#wrote, iclass 7, count 2 2006.257.15:35:39.01#ibcon#about to read 3, iclass 7, count 2 2006.257.15:35:39.04#ibcon#read 3, iclass 7, count 2 2006.257.15:35:39.04#ibcon#about to read 4, iclass 7, count 2 2006.257.15:35:39.04#ibcon#read 4, iclass 7, count 2 2006.257.15:35:39.04#ibcon#about to read 5, iclass 7, count 2 2006.257.15:35:39.04#ibcon#read 5, iclass 7, count 2 2006.257.15:35:39.04#ibcon#about to read 6, iclass 7, count 2 2006.257.15:35:39.04#ibcon#read 6, iclass 7, count 2 2006.257.15:35:39.04#ibcon#end of sib2, iclass 7, count 2 2006.257.15:35:39.04#ibcon#*after write, iclass 7, count 2 2006.257.15:35:39.04#ibcon#*before return 0, iclass 7, count 2 2006.257.15:35:39.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:39.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:39.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.15:35:39.04#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:39.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:39.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:39.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:39.16#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:35:39.16#ibcon#first serial, iclass 7, count 0 2006.257.15:35:39.16#ibcon#enter sib2, iclass 7, count 0 2006.257.15:35:39.16#ibcon#flushed, iclass 7, count 0 2006.257.15:35:39.16#ibcon#about to write, iclass 7, count 0 2006.257.15:35:39.16#ibcon#wrote, iclass 7, count 0 2006.257.15:35:39.16#ibcon#about to read 3, iclass 7, count 0 2006.257.15:35:39.18#ibcon#read 3, iclass 7, count 0 2006.257.15:35:39.18#ibcon#about to read 4, iclass 7, count 0 2006.257.15:35:39.18#ibcon#read 4, iclass 7, count 0 2006.257.15:35:39.18#ibcon#about to read 5, iclass 7, count 0 2006.257.15:35:39.18#ibcon#read 5, iclass 7, count 0 2006.257.15:35:39.18#ibcon#about to read 6, iclass 7, count 0 2006.257.15:35:39.18#ibcon#read 6, iclass 7, count 0 2006.257.15:35:39.18#ibcon#end of sib2, iclass 7, count 0 2006.257.15:35:39.18#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:35:39.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:35:39.18#ibcon#[25=USB\r\n] 2006.257.15:35:39.18#ibcon#*before write, iclass 7, count 0 2006.257.15:35:39.18#ibcon#enter sib2, iclass 7, count 0 2006.257.15:35:39.18#ibcon#flushed, iclass 7, count 0 2006.257.15:35:39.18#ibcon#about to write, iclass 7, count 0 2006.257.15:35:39.18#ibcon#wrote, iclass 7, count 0 2006.257.15:35:39.18#ibcon#about to read 3, iclass 7, count 0 2006.257.15:35:39.21#ibcon#read 3, iclass 7, count 0 2006.257.15:35:39.21#ibcon#about to read 4, iclass 7, count 0 2006.257.15:35:39.21#ibcon#read 4, iclass 7, count 0 2006.257.15:35:39.21#ibcon#about to read 5, iclass 7, count 0 2006.257.15:35:39.21#ibcon#read 5, iclass 7, count 0 2006.257.15:35:39.21#ibcon#about to read 6, iclass 7, count 0 2006.257.15:35:39.21#ibcon#read 6, iclass 7, count 0 2006.257.15:35:39.21#ibcon#end of sib2, iclass 7, count 0 2006.257.15:35:39.21#ibcon#*after write, iclass 7, count 0 2006.257.15:35:39.21#ibcon#*before return 0, iclass 7, count 0 2006.257.15:35:39.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:39.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:39.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:35:39.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:35:39.21$vck44/valo=4,624.99 2006.257.15:35:39.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.15:35:39.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.15:35:39.21#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:39.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:39.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:39.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:39.21#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:35:39.21#ibcon#first serial, iclass 11, count 0 2006.257.15:35:39.21#ibcon#enter sib2, iclass 11, count 0 2006.257.15:35:39.21#ibcon#flushed, iclass 11, count 0 2006.257.15:35:39.21#ibcon#about to write, iclass 11, count 0 2006.257.15:35:39.21#ibcon#wrote, iclass 11, count 0 2006.257.15:35:39.21#ibcon#about to read 3, iclass 11, count 0 2006.257.15:35:39.23#ibcon#read 3, iclass 11, count 0 2006.257.15:35:39.23#ibcon#about to read 4, iclass 11, count 0 2006.257.15:35:39.23#ibcon#read 4, iclass 11, count 0 2006.257.15:35:39.23#ibcon#about to read 5, iclass 11, count 0 2006.257.15:35:39.23#ibcon#read 5, iclass 11, count 0 2006.257.15:35:39.23#ibcon#about to read 6, iclass 11, count 0 2006.257.15:35:39.23#ibcon#read 6, iclass 11, count 0 2006.257.15:35:39.23#ibcon#end of sib2, iclass 11, count 0 2006.257.15:35:39.23#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:35:39.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:35:39.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:35:39.23#ibcon#*before write, iclass 11, count 0 2006.257.15:35:39.23#ibcon#enter sib2, iclass 11, count 0 2006.257.15:35:39.23#ibcon#flushed, iclass 11, count 0 2006.257.15:35:39.23#ibcon#about to write, iclass 11, count 0 2006.257.15:35:39.23#ibcon#wrote, iclass 11, count 0 2006.257.15:35:39.23#ibcon#about to read 3, iclass 11, count 0 2006.257.15:35:39.27#ibcon#read 3, iclass 11, count 0 2006.257.15:35:39.27#ibcon#about to read 4, iclass 11, count 0 2006.257.15:35:39.27#ibcon#read 4, iclass 11, count 0 2006.257.15:35:39.27#ibcon#about to read 5, iclass 11, count 0 2006.257.15:35:39.27#ibcon#read 5, iclass 11, count 0 2006.257.15:35:39.27#ibcon#about to read 6, iclass 11, count 0 2006.257.15:35:39.27#ibcon#read 6, iclass 11, count 0 2006.257.15:35:39.27#ibcon#end of sib2, iclass 11, count 0 2006.257.15:35:39.27#ibcon#*after write, iclass 11, count 0 2006.257.15:35:39.27#ibcon#*before return 0, iclass 11, count 0 2006.257.15:35:39.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:39.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:39.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:35:39.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:35:39.27$vck44/va=4,7 2006.257.15:35:39.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.15:35:39.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.15:35:39.27#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:39.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:39.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:39.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:39.33#ibcon#enter wrdev, iclass 13, count 2 2006.257.15:35:39.33#ibcon#first serial, iclass 13, count 2 2006.257.15:35:39.33#ibcon#enter sib2, iclass 13, count 2 2006.257.15:35:39.33#ibcon#flushed, iclass 13, count 2 2006.257.15:35:39.33#ibcon#about to write, iclass 13, count 2 2006.257.15:35:39.33#ibcon#wrote, iclass 13, count 2 2006.257.15:35:39.33#ibcon#about to read 3, iclass 13, count 2 2006.257.15:35:39.34#abcon#<5=/14 1.2 3.1 17.43 971013.9\r\n> 2006.257.15:35:39.35#ibcon#read 3, iclass 13, count 2 2006.257.15:35:39.35#ibcon#about to read 4, iclass 13, count 2 2006.257.15:35:39.35#ibcon#read 4, iclass 13, count 2 2006.257.15:35:39.35#ibcon#about to read 5, iclass 13, count 2 2006.257.15:35:39.35#ibcon#read 5, iclass 13, count 2 2006.257.15:35:39.35#ibcon#about to read 6, iclass 13, count 2 2006.257.15:35:39.35#ibcon#read 6, iclass 13, count 2 2006.257.15:35:39.35#ibcon#end of sib2, iclass 13, count 2 2006.257.15:35:39.35#ibcon#*mode == 0, iclass 13, count 2 2006.257.15:35:39.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.15:35:39.35#ibcon#[25=AT04-07\r\n] 2006.257.15:35:39.35#ibcon#*before write, iclass 13, count 2 2006.257.15:35:39.35#ibcon#enter sib2, iclass 13, count 2 2006.257.15:35:39.35#ibcon#flushed, iclass 13, count 2 2006.257.15:35:39.35#ibcon#about to write, iclass 13, count 2 2006.257.15:35:39.35#ibcon#wrote, iclass 13, count 2 2006.257.15:35:39.35#ibcon#about to read 3, iclass 13, count 2 2006.257.15:35:39.36#abcon#{5=INTERFACE CLEAR} 2006.257.15:35:39.38#ibcon#read 3, iclass 13, count 2 2006.257.15:35:39.40#ibcon#about to read 4, iclass 13, count 2 2006.257.15:35:39.40#ibcon#read 4, iclass 13, count 2 2006.257.15:35:39.40#ibcon#about to read 5, iclass 13, count 2 2006.257.15:35:39.40#ibcon#read 5, iclass 13, count 2 2006.257.15:35:39.40#ibcon#about to read 6, iclass 13, count 2 2006.257.15:35:39.40#ibcon#read 6, iclass 13, count 2 2006.257.15:35:39.40#ibcon#end of sib2, iclass 13, count 2 2006.257.15:35:39.40#ibcon#*after write, iclass 13, count 2 2006.257.15:35:39.40#ibcon#*before return 0, iclass 13, count 2 2006.257.15:35:39.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:39.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:39.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.15:35:39.40#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:39.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:39.42#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:35:39.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:39.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:39.52#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:35:39.52#ibcon#first serial, iclass 13, count 0 2006.257.15:35:39.52#ibcon#enter sib2, iclass 13, count 0 2006.257.15:35:39.52#ibcon#flushed, iclass 13, count 0 2006.257.15:35:39.52#ibcon#about to write, iclass 13, count 0 2006.257.15:35:39.52#ibcon#wrote, iclass 13, count 0 2006.257.15:35:39.52#ibcon#about to read 3, iclass 13, count 0 2006.257.15:35:39.54#ibcon#read 3, iclass 13, count 0 2006.257.15:35:39.54#ibcon#about to read 4, iclass 13, count 0 2006.257.15:35:39.54#ibcon#read 4, iclass 13, count 0 2006.257.15:35:39.54#ibcon#about to read 5, iclass 13, count 0 2006.257.15:35:39.54#ibcon#read 5, iclass 13, count 0 2006.257.15:35:39.54#ibcon#about to read 6, iclass 13, count 0 2006.257.15:35:39.54#ibcon#read 6, iclass 13, count 0 2006.257.15:35:39.54#ibcon#end of sib2, iclass 13, count 0 2006.257.15:35:39.54#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:35:39.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:35:39.54#ibcon#[25=USB\r\n] 2006.257.15:35:39.54#ibcon#*before write, iclass 13, count 0 2006.257.15:35:39.54#ibcon#enter sib2, iclass 13, count 0 2006.257.15:35:39.54#ibcon#flushed, iclass 13, count 0 2006.257.15:35:39.54#ibcon#about to write, iclass 13, count 0 2006.257.15:35:39.54#ibcon#wrote, iclass 13, count 0 2006.257.15:35:39.54#ibcon#about to read 3, iclass 13, count 0 2006.257.15:35:39.57#ibcon#read 3, iclass 13, count 0 2006.257.15:35:39.57#ibcon#about to read 4, iclass 13, count 0 2006.257.15:35:39.57#ibcon#read 4, iclass 13, count 0 2006.257.15:35:39.57#ibcon#about to read 5, iclass 13, count 0 2006.257.15:35:39.57#ibcon#read 5, iclass 13, count 0 2006.257.15:35:39.57#ibcon#about to read 6, iclass 13, count 0 2006.257.15:35:39.57#ibcon#read 6, iclass 13, count 0 2006.257.15:35:39.57#ibcon#end of sib2, iclass 13, count 0 2006.257.15:35:39.57#ibcon#*after write, iclass 13, count 0 2006.257.15:35:39.57#ibcon#*before return 0, iclass 13, count 0 2006.257.15:35:39.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:39.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:39.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:35:39.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:35:39.57$vck44/valo=5,734.99 2006.257.15:35:39.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.15:35:39.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.15:35:39.57#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:39.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:39.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:39.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:39.57#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:35:39.57#ibcon#first serial, iclass 19, count 0 2006.257.15:35:39.57#ibcon#enter sib2, iclass 19, count 0 2006.257.15:35:39.57#ibcon#flushed, iclass 19, count 0 2006.257.15:35:39.57#ibcon#about to write, iclass 19, count 0 2006.257.15:35:39.57#ibcon#wrote, iclass 19, count 0 2006.257.15:35:39.57#ibcon#about to read 3, iclass 19, count 0 2006.257.15:35:39.59#ibcon#read 3, iclass 19, count 0 2006.257.15:35:39.59#ibcon#about to read 4, iclass 19, count 0 2006.257.15:35:39.59#ibcon#read 4, iclass 19, count 0 2006.257.15:35:39.59#ibcon#about to read 5, iclass 19, count 0 2006.257.15:35:39.59#ibcon#read 5, iclass 19, count 0 2006.257.15:35:39.59#ibcon#about to read 6, iclass 19, count 0 2006.257.15:35:39.59#ibcon#read 6, iclass 19, count 0 2006.257.15:35:39.59#ibcon#end of sib2, iclass 19, count 0 2006.257.15:35:39.59#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:35:39.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:35:39.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:35:39.59#ibcon#*before write, iclass 19, count 0 2006.257.15:35:39.59#ibcon#enter sib2, iclass 19, count 0 2006.257.15:35:39.59#ibcon#flushed, iclass 19, count 0 2006.257.15:35:39.59#ibcon#about to write, iclass 19, count 0 2006.257.15:35:39.59#ibcon#wrote, iclass 19, count 0 2006.257.15:35:39.59#ibcon#about to read 3, iclass 19, count 0 2006.257.15:35:39.63#ibcon#read 3, iclass 19, count 0 2006.257.15:35:39.63#ibcon#about to read 4, iclass 19, count 0 2006.257.15:35:39.63#ibcon#read 4, iclass 19, count 0 2006.257.15:35:39.63#ibcon#about to read 5, iclass 19, count 0 2006.257.15:35:39.63#ibcon#read 5, iclass 19, count 0 2006.257.15:35:39.63#ibcon#about to read 6, iclass 19, count 0 2006.257.15:35:39.63#ibcon#read 6, iclass 19, count 0 2006.257.15:35:39.63#ibcon#end of sib2, iclass 19, count 0 2006.257.15:35:39.63#ibcon#*after write, iclass 19, count 0 2006.257.15:35:39.63#ibcon#*before return 0, iclass 19, count 0 2006.257.15:35:39.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:39.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:39.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:35:39.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:35:39.63$vck44/va=5,4 2006.257.15:35:39.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.15:35:39.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.15:35:39.63#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:39.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:39.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:39.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:39.69#ibcon#enter wrdev, iclass 21, count 2 2006.257.15:35:39.69#ibcon#first serial, iclass 21, count 2 2006.257.15:35:39.69#ibcon#enter sib2, iclass 21, count 2 2006.257.15:35:39.69#ibcon#flushed, iclass 21, count 2 2006.257.15:35:39.69#ibcon#about to write, iclass 21, count 2 2006.257.15:35:39.69#ibcon#wrote, iclass 21, count 2 2006.257.15:35:39.69#ibcon#about to read 3, iclass 21, count 2 2006.257.15:35:39.71#ibcon#read 3, iclass 21, count 2 2006.257.15:35:39.71#ibcon#about to read 4, iclass 21, count 2 2006.257.15:35:39.71#ibcon#read 4, iclass 21, count 2 2006.257.15:35:39.71#ibcon#about to read 5, iclass 21, count 2 2006.257.15:35:39.71#ibcon#read 5, iclass 21, count 2 2006.257.15:35:39.71#ibcon#about to read 6, iclass 21, count 2 2006.257.15:35:39.71#ibcon#read 6, iclass 21, count 2 2006.257.15:35:39.71#ibcon#end of sib2, iclass 21, count 2 2006.257.15:35:39.71#ibcon#*mode == 0, iclass 21, count 2 2006.257.15:35:39.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.15:35:39.71#ibcon#[25=AT05-04\r\n] 2006.257.15:35:39.71#ibcon#*before write, iclass 21, count 2 2006.257.15:35:39.71#ibcon#enter sib2, iclass 21, count 2 2006.257.15:35:39.71#ibcon#flushed, iclass 21, count 2 2006.257.15:35:39.71#ibcon#about to write, iclass 21, count 2 2006.257.15:35:39.71#ibcon#wrote, iclass 21, count 2 2006.257.15:35:39.71#ibcon#about to read 3, iclass 21, count 2 2006.257.15:35:39.74#ibcon#read 3, iclass 21, count 2 2006.257.15:35:39.74#ibcon#about to read 4, iclass 21, count 2 2006.257.15:35:39.74#ibcon#read 4, iclass 21, count 2 2006.257.15:35:39.74#ibcon#about to read 5, iclass 21, count 2 2006.257.15:35:39.74#ibcon#read 5, iclass 21, count 2 2006.257.15:35:39.74#ibcon#about to read 6, iclass 21, count 2 2006.257.15:35:39.74#ibcon#read 6, iclass 21, count 2 2006.257.15:35:39.74#ibcon#end of sib2, iclass 21, count 2 2006.257.15:35:39.74#ibcon#*after write, iclass 21, count 2 2006.257.15:35:39.74#ibcon#*before return 0, iclass 21, count 2 2006.257.15:35:39.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:39.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:39.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.15:35:39.74#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:39.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:39.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:39.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:39.86#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:35:39.86#ibcon#first serial, iclass 21, count 0 2006.257.15:35:39.86#ibcon#enter sib2, iclass 21, count 0 2006.257.15:35:39.86#ibcon#flushed, iclass 21, count 0 2006.257.15:35:39.86#ibcon#about to write, iclass 21, count 0 2006.257.15:35:39.86#ibcon#wrote, iclass 21, count 0 2006.257.15:35:39.86#ibcon#about to read 3, iclass 21, count 0 2006.257.15:35:39.88#ibcon#read 3, iclass 21, count 0 2006.257.15:35:39.88#ibcon#about to read 4, iclass 21, count 0 2006.257.15:35:39.88#ibcon#read 4, iclass 21, count 0 2006.257.15:35:39.88#ibcon#about to read 5, iclass 21, count 0 2006.257.15:35:39.88#ibcon#read 5, iclass 21, count 0 2006.257.15:35:39.88#ibcon#about to read 6, iclass 21, count 0 2006.257.15:35:39.88#ibcon#read 6, iclass 21, count 0 2006.257.15:35:39.88#ibcon#end of sib2, iclass 21, count 0 2006.257.15:35:39.88#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:35:39.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:35:39.88#ibcon#[25=USB\r\n] 2006.257.15:35:39.88#ibcon#*before write, iclass 21, count 0 2006.257.15:35:39.88#ibcon#enter sib2, iclass 21, count 0 2006.257.15:35:39.88#ibcon#flushed, iclass 21, count 0 2006.257.15:35:39.88#ibcon#about to write, iclass 21, count 0 2006.257.15:35:39.88#ibcon#wrote, iclass 21, count 0 2006.257.15:35:39.88#ibcon#about to read 3, iclass 21, count 0 2006.257.15:35:39.91#ibcon#read 3, iclass 21, count 0 2006.257.15:35:39.91#ibcon#about to read 4, iclass 21, count 0 2006.257.15:35:39.91#ibcon#read 4, iclass 21, count 0 2006.257.15:35:39.91#ibcon#about to read 5, iclass 21, count 0 2006.257.15:35:39.91#ibcon#read 5, iclass 21, count 0 2006.257.15:35:39.91#ibcon#about to read 6, iclass 21, count 0 2006.257.15:35:39.91#ibcon#read 6, iclass 21, count 0 2006.257.15:35:39.91#ibcon#end of sib2, iclass 21, count 0 2006.257.15:35:39.91#ibcon#*after write, iclass 21, count 0 2006.257.15:35:39.91#ibcon#*before return 0, iclass 21, count 0 2006.257.15:35:39.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:39.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:39.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:35:39.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:35:39.91$vck44/valo=6,814.99 2006.257.15:35:39.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.15:35:39.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.15:35:39.91#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:39.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:39.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:39.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:39.91#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:35:39.91#ibcon#first serial, iclass 23, count 0 2006.257.15:35:39.91#ibcon#enter sib2, iclass 23, count 0 2006.257.15:35:39.91#ibcon#flushed, iclass 23, count 0 2006.257.15:35:39.91#ibcon#about to write, iclass 23, count 0 2006.257.15:35:39.91#ibcon#wrote, iclass 23, count 0 2006.257.15:35:39.91#ibcon#about to read 3, iclass 23, count 0 2006.257.15:35:39.93#ibcon#read 3, iclass 23, count 0 2006.257.15:35:39.93#ibcon#about to read 4, iclass 23, count 0 2006.257.15:35:39.93#ibcon#read 4, iclass 23, count 0 2006.257.15:35:39.93#ibcon#about to read 5, iclass 23, count 0 2006.257.15:35:39.93#ibcon#read 5, iclass 23, count 0 2006.257.15:35:39.93#ibcon#about to read 6, iclass 23, count 0 2006.257.15:35:39.93#ibcon#read 6, iclass 23, count 0 2006.257.15:35:39.93#ibcon#end of sib2, iclass 23, count 0 2006.257.15:35:39.93#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:35:39.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:35:39.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:35:39.93#ibcon#*before write, iclass 23, count 0 2006.257.15:35:39.93#ibcon#enter sib2, iclass 23, count 0 2006.257.15:35:39.93#ibcon#flushed, iclass 23, count 0 2006.257.15:35:39.93#ibcon#about to write, iclass 23, count 0 2006.257.15:35:39.93#ibcon#wrote, iclass 23, count 0 2006.257.15:35:39.93#ibcon#about to read 3, iclass 23, count 0 2006.257.15:35:39.97#ibcon#read 3, iclass 23, count 0 2006.257.15:35:39.97#ibcon#about to read 4, iclass 23, count 0 2006.257.15:35:39.97#ibcon#read 4, iclass 23, count 0 2006.257.15:35:39.97#ibcon#about to read 5, iclass 23, count 0 2006.257.15:35:39.97#ibcon#read 5, iclass 23, count 0 2006.257.15:35:39.97#ibcon#about to read 6, iclass 23, count 0 2006.257.15:35:39.97#ibcon#read 6, iclass 23, count 0 2006.257.15:35:39.97#ibcon#end of sib2, iclass 23, count 0 2006.257.15:35:39.97#ibcon#*after write, iclass 23, count 0 2006.257.15:35:39.97#ibcon#*before return 0, iclass 23, count 0 2006.257.15:35:39.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:39.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:39.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:35:39.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:35:39.97$vck44/va=6,4 2006.257.15:35:39.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.15:35:39.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.15:35:39.97#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:39.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:40.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:40.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:40.03#ibcon#enter wrdev, iclass 25, count 2 2006.257.15:35:40.03#ibcon#first serial, iclass 25, count 2 2006.257.15:35:40.03#ibcon#enter sib2, iclass 25, count 2 2006.257.15:35:40.03#ibcon#flushed, iclass 25, count 2 2006.257.15:35:40.03#ibcon#about to write, iclass 25, count 2 2006.257.15:35:40.03#ibcon#wrote, iclass 25, count 2 2006.257.15:35:40.03#ibcon#about to read 3, iclass 25, count 2 2006.257.15:35:40.05#ibcon#read 3, iclass 25, count 2 2006.257.15:35:40.05#ibcon#about to read 4, iclass 25, count 2 2006.257.15:35:40.05#ibcon#read 4, iclass 25, count 2 2006.257.15:35:40.05#ibcon#about to read 5, iclass 25, count 2 2006.257.15:35:40.05#ibcon#read 5, iclass 25, count 2 2006.257.15:35:40.05#ibcon#about to read 6, iclass 25, count 2 2006.257.15:35:40.05#ibcon#read 6, iclass 25, count 2 2006.257.15:35:40.05#ibcon#end of sib2, iclass 25, count 2 2006.257.15:35:40.05#ibcon#*mode == 0, iclass 25, count 2 2006.257.15:35:40.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.15:35:40.05#ibcon#[25=AT06-04\r\n] 2006.257.15:35:40.05#ibcon#*before write, iclass 25, count 2 2006.257.15:35:40.05#ibcon#enter sib2, iclass 25, count 2 2006.257.15:35:40.05#ibcon#flushed, iclass 25, count 2 2006.257.15:35:40.05#ibcon#about to write, iclass 25, count 2 2006.257.15:35:40.05#ibcon#wrote, iclass 25, count 2 2006.257.15:35:40.05#ibcon#about to read 3, iclass 25, count 2 2006.257.15:35:40.08#ibcon#read 3, iclass 25, count 2 2006.257.15:35:40.08#ibcon#about to read 4, iclass 25, count 2 2006.257.15:35:40.08#ibcon#read 4, iclass 25, count 2 2006.257.15:35:40.08#ibcon#about to read 5, iclass 25, count 2 2006.257.15:35:40.08#ibcon#read 5, iclass 25, count 2 2006.257.15:35:40.08#ibcon#about to read 6, iclass 25, count 2 2006.257.15:35:40.08#ibcon#read 6, iclass 25, count 2 2006.257.15:35:40.08#ibcon#end of sib2, iclass 25, count 2 2006.257.15:35:40.08#ibcon#*after write, iclass 25, count 2 2006.257.15:35:40.08#ibcon#*before return 0, iclass 25, count 2 2006.257.15:35:40.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:40.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:40.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.15:35:40.08#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:40.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:40.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:40.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:40.20#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:35:40.20#ibcon#first serial, iclass 25, count 0 2006.257.15:35:40.20#ibcon#enter sib2, iclass 25, count 0 2006.257.15:35:40.20#ibcon#flushed, iclass 25, count 0 2006.257.15:35:40.20#ibcon#about to write, iclass 25, count 0 2006.257.15:35:40.20#ibcon#wrote, iclass 25, count 0 2006.257.15:35:40.20#ibcon#about to read 3, iclass 25, count 0 2006.257.15:35:40.22#ibcon#read 3, iclass 25, count 0 2006.257.15:35:40.22#ibcon#about to read 4, iclass 25, count 0 2006.257.15:35:40.22#ibcon#read 4, iclass 25, count 0 2006.257.15:35:40.22#ibcon#about to read 5, iclass 25, count 0 2006.257.15:35:40.22#ibcon#read 5, iclass 25, count 0 2006.257.15:35:40.22#ibcon#about to read 6, iclass 25, count 0 2006.257.15:35:40.22#ibcon#read 6, iclass 25, count 0 2006.257.15:35:40.22#ibcon#end of sib2, iclass 25, count 0 2006.257.15:35:40.22#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:35:40.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:35:40.22#ibcon#[25=USB\r\n] 2006.257.15:35:40.22#ibcon#*before write, iclass 25, count 0 2006.257.15:35:40.22#ibcon#enter sib2, iclass 25, count 0 2006.257.15:35:40.22#ibcon#flushed, iclass 25, count 0 2006.257.15:35:40.22#ibcon#about to write, iclass 25, count 0 2006.257.15:35:40.22#ibcon#wrote, iclass 25, count 0 2006.257.15:35:40.22#ibcon#about to read 3, iclass 25, count 0 2006.257.15:35:40.25#ibcon#read 3, iclass 25, count 0 2006.257.15:35:40.25#ibcon#about to read 4, iclass 25, count 0 2006.257.15:35:40.25#ibcon#read 4, iclass 25, count 0 2006.257.15:35:40.25#ibcon#about to read 5, iclass 25, count 0 2006.257.15:35:40.25#ibcon#read 5, iclass 25, count 0 2006.257.15:35:40.25#ibcon#about to read 6, iclass 25, count 0 2006.257.15:35:40.25#ibcon#read 6, iclass 25, count 0 2006.257.15:35:40.25#ibcon#end of sib2, iclass 25, count 0 2006.257.15:35:40.25#ibcon#*after write, iclass 25, count 0 2006.257.15:35:40.25#ibcon#*before return 0, iclass 25, count 0 2006.257.15:35:40.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:40.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:40.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:35:40.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:35:40.25$vck44/valo=7,864.99 2006.257.15:35:40.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.15:35:40.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.15:35:40.25#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:40.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:40.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:40.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:40.25#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:35:40.25#ibcon#first serial, iclass 27, count 0 2006.257.15:35:40.25#ibcon#enter sib2, iclass 27, count 0 2006.257.15:35:40.25#ibcon#flushed, iclass 27, count 0 2006.257.15:35:40.25#ibcon#about to write, iclass 27, count 0 2006.257.15:35:40.25#ibcon#wrote, iclass 27, count 0 2006.257.15:35:40.25#ibcon#about to read 3, iclass 27, count 0 2006.257.15:35:40.27#ibcon#read 3, iclass 27, count 0 2006.257.15:35:40.27#ibcon#about to read 4, iclass 27, count 0 2006.257.15:35:40.27#ibcon#read 4, iclass 27, count 0 2006.257.15:35:40.27#ibcon#about to read 5, iclass 27, count 0 2006.257.15:35:40.27#ibcon#read 5, iclass 27, count 0 2006.257.15:35:40.27#ibcon#about to read 6, iclass 27, count 0 2006.257.15:35:40.27#ibcon#read 6, iclass 27, count 0 2006.257.15:35:40.27#ibcon#end of sib2, iclass 27, count 0 2006.257.15:35:40.27#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:35:40.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:35:40.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:35:40.27#ibcon#*before write, iclass 27, count 0 2006.257.15:35:40.27#ibcon#enter sib2, iclass 27, count 0 2006.257.15:35:40.27#ibcon#flushed, iclass 27, count 0 2006.257.15:35:40.27#ibcon#about to write, iclass 27, count 0 2006.257.15:35:40.27#ibcon#wrote, iclass 27, count 0 2006.257.15:35:40.27#ibcon#about to read 3, iclass 27, count 0 2006.257.15:35:40.31#ibcon#read 3, iclass 27, count 0 2006.257.15:35:40.31#ibcon#about to read 4, iclass 27, count 0 2006.257.15:35:40.31#ibcon#read 4, iclass 27, count 0 2006.257.15:35:40.31#ibcon#about to read 5, iclass 27, count 0 2006.257.15:35:40.31#ibcon#read 5, iclass 27, count 0 2006.257.15:35:40.31#ibcon#about to read 6, iclass 27, count 0 2006.257.15:35:40.31#ibcon#read 6, iclass 27, count 0 2006.257.15:35:40.31#ibcon#end of sib2, iclass 27, count 0 2006.257.15:35:40.31#ibcon#*after write, iclass 27, count 0 2006.257.15:35:40.31#ibcon#*before return 0, iclass 27, count 0 2006.257.15:35:40.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:40.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:40.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:35:40.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:35:40.31$vck44/va=7,4 2006.257.15:35:40.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.15:35:40.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.15:35:40.31#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:40.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:40.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:40.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:40.37#ibcon#enter wrdev, iclass 29, count 2 2006.257.15:35:40.37#ibcon#first serial, iclass 29, count 2 2006.257.15:35:40.37#ibcon#enter sib2, iclass 29, count 2 2006.257.15:35:40.37#ibcon#flushed, iclass 29, count 2 2006.257.15:35:40.37#ibcon#about to write, iclass 29, count 2 2006.257.15:35:40.37#ibcon#wrote, iclass 29, count 2 2006.257.15:35:40.37#ibcon#about to read 3, iclass 29, count 2 2006.257.15:35:40.39#ibcon#read 3, iclass 29, count 2 2006.257.15:35:40.39#ibcon#about to read 4, iclass 29, count 2 2006.257.15:35:40.39#ibcon#read 4, iclass 29, count 2 2006.257.15:35:40.39#ibcon#about to read 5, iclass 29, count 2 2006.257.15:35:40.39#ibcon#read 5, iclass 29, count 2 2006.257.15:35:40.39#ibcon#about to read 6, iclass 29, count 2 2006.257.15:35:40.39#ibcon#read 6, iclass 29, count 2 2006.257.15:35:40.39#ibcon#end of sib2, iclass 29, count 2 2006.257.15:35:40.39#ibcon#*mode == 0, iclass 29, count 2 2006.257.15:35:40.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.15:35:40.39#ibcon#[25=AT07-04\r\n] 2006.257.15:35:40.39#ibcon#*before write, iclass 29, count 2 2006.257.15:35:40.39#ibcon#enter sib2, iclass 29, count 2 2006.257.15:35:40.39#ibcon#flushed, iclass 29, count 2 2006.257.15:35:40.39#ibcon#about to write, iclass 29, count 2 2006.257.15:35:40.39#ibcon#wrote, iclass 29, count 2 2006.257.15:35:40.39#ibcon#about to read 3, iclass 29, count 2 2006.257.15:35:40.42#ibcon#read 3, iclass 29, count 2 2006.257.15:35:40.42#ibcon#about to read 4, iclass 29, count 2 2006.257.15:35:40.42#ibcon#read 4, iclass 29, count 2 2006.257.15:35:40.42#ibcon#about to read 5, iclass 29, count 2 2006.257.15:35:40.42#ibcon#read 5, iclass 29, count 2 2006.257.15:35:40.42#ibcon#about to read 6, iclass 29, count 2 2006.257.15:35:40.42#ibcon#read 6, iclass 29, count 2 2006.257.15:35:40.42#ibcon#end of sib2, iclass 29, count 2 2006.257.15:35:40.42#ibcon#*after write, iclass 29, count 2 2006.257.15:35:40.42#ibcon#*before return 0, iclass 29, count 2 2006.257.15:35:40.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:40.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:40.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.15:35:40.42#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:40.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:40.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:40.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:40.54#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:35:40.54#ibcon#first serial, iclass 29, count 0 2006.257.15:35:40.54#ibcon#enter sib2, iclass 29, count 0 2006.257.15:35:40.54#ibcon#flushed, iclass 29, count 0 2006.257.15:35:40.54#ibcon#about to write, iclass 29, count 0 2006.257.15:35:40.54#ibcon#wrote, iclass 29, count 0 2006.257.15:35:40.54#ibcon#about to read 3, iclass 29, count 0 2006.257.15:35:40.56#ibcon#read 3, iclass 29, count 0 2006.257.15:35:40.56#ibcon#about to read 4, iclass 29, count 0 2006.257.15:35:40.56#ibcon#read 4, iclass 29, count 0 2006.257.15:35:40.56#ibcon#about to read 5, iclass 29, count 0 2006.257.15:35:40.56#ibcon#read 5, iclass 29, count 0 2006.257.15:35:40.56#ibcon#about to read 6, iclass 29, count 0 2006.257.15:35:40.56#ibcon#read 6, iclass 29, count 0 2006.257.15:35:40.56#ibcon#end of sib2, iclass 29, count 0 2006.257.15:35:40.56#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:35:40.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:35:40.56#ibcon#[25=USB\r\n] 2006.257.15:35:40.56#ibcon#*before write, iclass 29, count 0 2006.257.15:35:40.56#ibcon#enter sib2, iclass 29, count 0 2006.257.15:35:40.56#ibcon#flushed, iclass 29, count 0 2006.257.15:35:40.56#ibcon#about to write, iclass 29, count 0 2006.257.15:35:40.56#ibcon#wrote, iclass 29, count 0 2006.257.15:35:40.56#ibcon#about to read 3, iclass 29, count 0 2006.257.15:35:40.59#ibcon#read 3, iclass 29, count 0 2006.257.15:35:40.59#ibcon#about to read 4, iclass 29, count 0 2006.257.15:35:40.59#ibcon#read 4, iclass 29, count 0 2006.257.15:35:40.59#ibcon#about to read 5, iclass 29, count 0 2006.257.15:35:40.59#ibcon#read 5, iclass 29, count 0 2006.257.15:35:40.59#ibcon#about to read 6, iclass 29, count 0 2006.257.15:35:40.59#ibcon#read 6, iclass 29, count 0 2006.257.15:35:40.59#ibcon#end of sib2, iclass 29, count 0 2006.257.15:35:40.59#ibcon#*after write, iclass 29, count 0 2006.257.15:35:40.59#ibcon#*before return 0, iclass 29, count 0 2006.257.15:35:40.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:40.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:40.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:35:40.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:35:40.59$vck44/valo=8,884.99 2006.257.15:35:40.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.15:35:40.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.15:35:40.59#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:40.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:40.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:40.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:40.59#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:35:40.59#ibcon#first serial, iclass 31, count 0 2006.257.15:35:40.59#ibcon#enter sib2, iclass 31, count 0 2006.257.15:35:40.59#ibcon#flushed, iclass 31, count 0 2006.257.15:35:40.59#ibcon#about to write, iclass 31, count 0 2006.257.15:35:40.59#ibcon#wrote, iclass 31, count 0 2006.257.15:35:40.59#ibcon#about to read 3, iclass 31, count 0 2006.257.15:35:40.61#ibcon#read 3, iclass 31, count 0 2006.257.15:35:40.61#ibcon#about to read 4, iclass 31, count 0 2006.257.15:35:40.61#ibcon#read 4, iclass 31, count 0 2006.257.15:35:40.61#ibcon#about to read 5, iclass 31, count 0 2006.257.15:35:40.61#ibcon#read 5, iclass 31, count 0 2006.257.15:35:40.61#ibcon#about to read 6, iclass 31, count 0 2006.257.15:35:40.61#ibcon#read 6, iclass 31, count 0 2006.257.15:35:40.61#ibcon#end of sib2, iclass 31, count 0 2006.257.15:35:40.61#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:35:40.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:35:40.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:35:40.61#ibcon#*before write, iclass 31, count 0 2006.257.15:35:40.61#ibcon#enter sib2, iclass 31, count 0 2006.257.15:35:40.61#ibcon#flushed, iclass 31, count 0 2006.257.15:35:40.61#ibcon#about to write, iclass 31, count 0 2006.257.15:35:40.61#ibcon#wrote, iclass 31, count 0 2006.257.15:35:40.61#ibcon#about to read 3, iclass 31, count 0 2006.257.15:35:40.65#ibcon#read 3, iclass 31, count 0 2006.257.15:35:40.65#ibcon#about to read 4, iclass 31, count 0 2006.257.15:35:40.65#ibcon#read 4, iclass 31, count 0 2006.257.15:35:40.65#ibcon#about to read 5, iclass 31, count 0 2006.257.15:35:40.65#ibcon#read 5, iclass 31, count 0 2006.257.15:35:40.65#ibcon#about to read 6, iclass 31, count 0 2006.257.15:35:40.65#ibcon#read 6, iclass 31, count 0 2006.257.15:35:40.65#ibcon#end of sib2, iclass 31, count 0 2006.257.15:35:40.65#ibcon#*after write, iclass 31, count 0 2006.257.15:35:40.65#ibcon#*before return 0, iclass 31, count 0 2006.257.15:35:40.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:40.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:40.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:35:40.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:35:40.65$vck44/va=8,4 2006.257.15:35:40.65#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.15:35:40.65#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.15:35:40.65#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:40.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:35:40.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:35:40.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:35:40.71#ibcon#enter wrdev, iclass 33, count 2 2006.257.15:35:40.71#ibcon#first serial, iclass 33, count 2 2006.257.15:35:40.71#ibcon#enter sib2, iclass 33, count 2 2006.257.15:35:40.71#ibcon#flushed, iclass 33, count 2 2006.257.15:35:40.71#ibcon#about to write, iclass 33, count 2 2006.257.15:35:40.71#ibcon#wrote, iclass 33, count 2 2006.257.15:35:40.71#ibcon#about to read 3, iclass 33, count 2 2006.257.15:35:40.73#ibcon#read 3, iclass 33, count 2 2006.257.15:35:40.73#ibcon#about to read 4, iclass 33, count 2 2006.257.15:35:40.73#ibcon#read 4, iclass 33, count 2 2006.257.15:35:40.73#ibcon#about to read 5, iclass 33, count 2 2006.257.15:35:40.73#ibcon#read 5, iclass 33, count 2 2006.257.15:35:40.73#ibcon#about to read 6, iclass 33, count 2 2006.257.15:35:40.73#ibcon#read 6, iclass 33, count 2 2006.257.15:35:40.73#ibcon#end of sib2, iclass 33, count 2 2006.257.15:35:40.73#ibcon#*mode == 0, iclass 33, count 2 2006.257.15:35:40.73#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.15:35:40.73#ibcon#[25=AT08-04\r\n] 2006.257.15:35:40.73#ibcon#*before write, iclass 33, count 2 2006.257.15:35:40.73#ibcon#enter sib2, iclass 33, count 2 2006.257.15:35:40.73#ibcon#flushed, iclass 33, count 2 2006.257.15:35:40.73#ibcon#about to write, iclass 33, count 2 2006.257.15:35:40.73#ibcon#wrote, iclass 33, count 2 2006.257.15:35:40.73#ibcon#about to read 3, iclass 33, count 2 2006.257.15:35:40.76#ibcon#read 3, iclass 33, count 2 2006.257.15:35:40.76#ibcon#about to read 4, iclass 33, count 2 2006.257.15:35:40.76#ibcon#read 4, iclass 33, count 2 2006.257.15:35:40.76#ibcon#about to read 5, iclass 33, count 2 2006.257.15:35:40.76#ibcon#read 5, iclass 33, count 2 2006.257.15:35:40.76#ibcon#about to read 6, iclass 33, count 2 2006.257.15:35:40.76#ibcon#read 6, iclass 33, count 2 2006.257.15:35:40.76#ibcon#end of sib2, iclass 33, count 2 2006.257.15:35:40.76#ibcon#*after write, iclass 33, count 2 2006.257.15:35:40.76#ibcon#*before return 0, iclass 33, count 2 2006.257.15:35:40.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:35:40.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:35:40.76#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.15:35:40.76#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:40.76#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:35:40.88#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:35:40.88#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:35:40.88#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:35:40.88#ibcon#first serial, iclass 33, count 0 2006.257.15:35:40.88#ibcon#enter sib2, iclass 33, count 0 2006.257.15:35:40.88#ibcon#flushed, iclass 33, count 0 2006.257.15:35:40.88#ibcon#about to write, iclass 33, count 0 2006.257.15:35:40.88#ibcon#wrote, iclass 33, count 0 2006.257.15:35:40.88#ibcon#about to read 3, iclass 33, count 0 2006.257.15:35:40.90#ibcon#read 3, iclass 33, count 0 2006.257.15:35:40.90#ibcon#about to read 4, iclass 33, count 0 2006.257.15:35:40.90#ibcon#read 4, iclass 33, count 0 2006.257.15:35:40.90#ibcon#about to read 5, iclass 33, count 0 2006.257.15:35:40.90#ibcon#read 5, iclass 33, count 0 2006.257.15:35:40.90#ibcon#about to read 6, iclass 33, count 0 2006.257.15:35:40.90#ibcon#read 6, iclass 33, count 0 2006.257.15:35:40.90#ibcon#end of sib2, iclass 33, count 0 2006.257.15:35:40.90#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:35:40.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:35:40.90#ibcon#[25=USB\r\n] 2006.257.15:35:40.90#ibcon#*before write, iclass 33, count 0 2006.257.15:35:40.90#ibcon#enter sib2, iclass 33, count 0 2006.257.15:35:40.90#ibcon#flushed, iclass 33, count 0 2006.257.15:35:40.90#ibcon#about to write, iclass 33, count 0 2006.257.15:35:40.90#ibcon#wrote, iclass 33, count 0 2006.257.15:35:40.90#ibcon#about to read 3, iclass 33, count 0 2006.257.15:35:40.93#ibcon#read 3, iclass 33, count 0 2006.257.15:35:40.93#ibcon#about to read 4, iclass 33, count 0 2006.257.15:35:40.93#ibcon#read 4, iclass 33, count 0 2006.257.15:35:40.93#ibcon#about to read 5, iclass 33, count 0 2006.257.15:35:40.93#ibcon#read 5, iclass 33, count 0 2006.257.15:35:40.93#ibcon#about to read 6, iclass 33, count 0 2006.257.15:35:40.93#ibcon#read 6, iclass 33, count 0 2006.257.15:35:40.93#ibcon#end of sib2, iclass 33, count 0 2006.257.15:35:40.93#ibcon#*after write, iclass 33, count 0 2006.257.15:35:40.93#ibcon#*before return 0, iclass 33, count 0 2006.257.15:35:40.93#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:35:40.93#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:35:40.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:35:40.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:35:40.93$vck44/vblo=1,629.99 2006.257.15:35:40.93#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.15:35:40.93#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.15:35:40.93#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:40.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:40.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:40.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:40.93#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:35:40.93#ibcon#first serial, iclass 35, count 0 2006.257.15:35:40.93#ibcon#enter sib2, iclass 35, count 0 2006.257.15:35:40.93#ibcon#flushed, iclass 35, count 0 2006.257.15:35:40.93#ibcon#about to write, iclass 35, count 0 2006.257.15:35:40.93#ibcon#wrote, iclass 35, count 0 2006.257.15:35:40.93#ibcon#about to read 3, iclass 35, count 0 2006.257.15:35:40.95#ibcon#read 3, iclass 35, count 0 2006.257.15:35:40.95#ibcon#about to read 4, iclass 35, count 0 2006.257.15:35:40.95#ibcon#read 4, iclass 35, count 0 2006.257.15:35:40.95#ibcon#about to read 5, iclass 35, count 0 2006.257.15:35:40.95#ibcon#read 5, iclass 35, count 0 2006.257.15:35:40.95#ibcon#about to read 6, iclass 35, count 0 2006.257.15:35:40.95#ibcon#read 6, iclass 35, count 0 2006.257.15:35:40.95#ibcon#end of sib2, iclass 35, count 0 2006.257.15:35:40.95#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:35:40.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:35:40.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:35:40.95#ibcon#*before write, iclass 35, count 0 2006.257.15:35:40.95#ibcon#enter sib2, iclass 35, count 0 2006.257.15:35:40.95#ibcon#flushed, iclass 35, count 0 2006.257.15:35:40.95#ibcon#about to write, iclass 35, count 0 2006.257.15:35:40.95#ibcon#wrote, iclass 35, count 0 2006.257.15:35:40.95#ibcon#about to read 3, iclass 35, count 0 2006.257.15:35:40.99#ibcon#read 3, iclass 35, count 0 2006.257.15:35:40.99#ibcon#about to read 4, iclass 35, count 0 2006.257.15:35:40.99#ibcon#read 4, iclass 35, count 0 2006.257.15:35:40.99#ibcon#about to read 5, iclass 35, count 0 2006.257.15:35:40.99#ibcon#read 5, iclass 35, count 0 2006.257.15:35:40.99#ibcon#about to read 6, iclass 35, count 0 2006.257.15:35:40.99#ibcon#read 6, iclass 35, count 0 2006.257.15:35:40.99#ibcon#end of sib2, iclass 35, count 0 2006.257.15:35:40.99#ibcon#*after write, iclass 35, count 0 2006.257.15:35:40.99#ibcon#*before return 0, iclass 35, count 0 2006.257.15:35:40.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:40.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:35:40.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:35:40.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:35:40.99$vck44/vb=1,4 2006.257.15:35:40.99#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.15:35:40.99#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.15:35:40.99#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:40.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:40.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:40.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:40.99#ibcon#enter wrdev, iclass 37, count 2 2006.257.15:35:40.99#ibcon#first serial, iclass 37, count 2 2006.257.15:35:40.99#ibcon#enter sib2, iclass 37, count 2 2006.257.15:35:40.99#ibcon#flushed, iclass 37, count 2 2006.257.15:35:40.99#ibcon#about to write, iclass 37, count 2 2006.257.15:35:40.99#ibcon#wrote, iclass 37, count 2 2006.257.15:35:40.99#ibcon#about to read 3, iclass 37, count 2 2006.257.15:35:41.01#ibcon#read 3, iclass 37, count 2 2006.257.15:35:41.01#ibcon#about to read 4, iclass 37, count 2 2006.257.15:35:41.01#ibcon#read 4, iclass 37, count 2 2006.257.15:35:41.01#ibcon#about to read 5, iclass 37, count 2 2006.257.15:35:41.01#ibcon#read 5, iclass 37, count 2 2006.257.15:35:41.01#ibcon#about to read 6, iclass 37, count 2 2006.257.15:35:41.01#ibcon#read 6, iclass 37, count 2 2006.257.15:35:41.01#ibcon#end of sib2, iclass 37, count 2 2006.257.15:35:41.01#ibcon#*mode == 0, iclass 37, count 2 2006.257.15:35:41.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.15:35:41.01#ibcon#[27=AT01-04\r\n] 2006.257.15:35:41.01#ibcon#*before write, iclass 37, count 2 2006.257.15:35:41.01#ibcon#enter sib2, iclass 37, count 2 2006.257.15:35:41.01#ibcon#flushed, iclass 37, count 2 2006.257.15:35:41.01#ibcon#about to write, iclass 37, count 2 2006.257.15:35:41.01#ibcon#wrote, iclass 37, count 2 2006.257.15:35:41.01#ibcon#about to read 3, iclass 37, count 2 2006.257.15:35:41.04#ibcon#read 3, iclass 37, count 2 2006.257.15:35:41.04#ibcon#about to read 4, iclass 37, count 2 2006.257.15:35:41.04#ibcon#read 4, iclass 37, count 2 2006.257.15:35:41.04#ibcon#about to read 5, iclass 37, count 2 2006.257.15:35:41.04#ibcon#read 5, iclass 37, count 2 2006.257.15:35:41.04#ibcon#about to read 6, iclass 37, count 2 2006.257.15:35:41.04#ibcon#read 6, iclass 37, count 2 2006.257.15:35:41.04#ibcon#end of sib2, iclass 37, count 2 2006.257.15:35:41.04#ibcon#*after write, iclass 37, count 2 2006.257.15:35:41.04#ibcon#*before return 0, iclass 37, count 2 2006.257.15:35:41.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:41.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:35:41.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.15:35:41.04#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:41.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:41.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:41.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:41.16#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:35:41.16#ibcon#first serial, iclass 37, count 0 2006.257.15:35:41.16#ibcon#enter sib2, iclass 37, count 0 2006.257.15:35:41.16#ibcon#flushed, iclass 37, count 0 2006.257.15:35:41.16#ibcon#about to write, iclass 37, count 0 2006.257.15:35:41.16#ibcon#wrote, iclass 37, count 0 2006.257.15:35:41.16#ibcon#about to read 3, iclass 37, count 0 2006.257.15:35:41.18#ibcon#read 3, iclass 37, count 0 2006.257.15:35:41.18#ibcon#about to read 4, iclass 37, count 0 2006.257.15:35:41.18#ibcon#read 4, iclass 37, count 0 2006.257.15:35:41.18#ibcon#about to read 5, iclass 37, count 0 2006.257.15:35:41.18#ibcon#read 5, iclass 37, count 0 2006.257.15:35:41.18#ibcon#about to read 6, iclass 37, count 0 2006.257.15:35:41.18#ibcon#read 6, iclass 37, count 0 2006.257.15:35:41.18#ibcon#end of sib2, iclass 37, count 0 2006.257.15:35:41.18#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:35:41.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:35:41.18#ibcon#[27=USB\r\n] 2006.257.15:35:41.18#ibcon#*before write, iclass 37, count 0 2006.257.15:35:41.18#ibcon#enter sib2, iclass 37, count 0 2006.257.15:35:41.18#ibcon#flushed, iclass 37, count 0 2006.257.15:35:41.18#ibcon#about to write, iclass 37, count 0 2006.257.15:35:41.18#ibcon#wrote, iclass 37, count 0 2006.257.15:35:41.18#ibcon#about to read 3, iclass 37, count 0 2006.257.15:35:41.21#ibcon#read 3, iclass 37, count 0 2006.257.15:35:41.21#ibcon#about to read 4, iclass 37, count 0 2006.257.15:35:41.21#ibcon#read 4, iclass 37, count 0 2006.257.15:35:41.21#ibcon#about to read 5, iclass 37, count 0 2006.257.15:35:41.21#ibcon#read 5, iclass 37, count 0 2006.257.15:35:41.21#ibcon#about to read 6, iclass 37, count 0 2006.257.15:35:41.21#ibcon#read 6, iclass 37, count 0 2006.257.15:35:41.21#ibcon#end of sib2, iclass 37, count 0 2006.257.15:35:41.21#ibcon#*after write, iclass 37, count 0 2006.257.15:35:41.21#ibcon#*before return 0, iclass 37, count 0 2006.257.15:35:41.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:41.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:35:41.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:35:41.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:35:41.21$vck44/vblo=2,634.99 2006.257.15:35:41.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.15:35:41.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.15:35:41.21#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:41.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:41.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:41.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:41.21#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:35:41.21#ibcon#first serial, iclass 39, count 0 2006.257.15:35:41.21#ibcon#enter sib2, iclass 39, count 0 2006.257.15:35:41.21#ibcon#flushed, iclass 39, count 0 2006.257.15:35:41.21#ibcon#about to write, iclass 39, count 0 2006.257.15:35:41.21#ibcon#wrote, iclass 39, count 0 2006.257.15:35:41.21#ibcon#about to read 3, iclass 39, count 0 2006.257.15:35:41.23#ibcon#read 3, iclass 39, count 0 2006.257.15:35:41.23#ibcon#about to read 4, iclass 39, count 0 2006.257.15:35:41.23#ibcon#read 4, iclass 39, count 0 2006.257.15:35:41.23#ibcon#about to read 5, iclass 39, count 0 2006.257.15:35:41.23#ibcon#read 5, iclass 39, count 0 2006.257.15:35:41.23#ibcon#about to read 6, iclass 39, count 0 2006.257.15:35:41.23#ibcon#read 6, iclass 39, count 0 2006.257.15:35:41.23#ibcon#end of sib2, iclass 39, count 0 2006.257.15:35:41.23#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:35:41.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:35:41.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:35:41.23#ibcon#*before write, iclass 39, count 0 2006.257.15:35:41.23#ibcon#enter sib2, iclass 39, count 0 2006.257.15:35:41.23#ibcon#flushed, iclass 39, count 0 2006.257.15:35:41.23#ibcon#about to write, iclass 39, count 0 2006.257.15:35:41.23#ibcon#wrote, iclass 39, count 0 2006.257.15:35:41.23#ibcon#about to read 3, iclass 39, count 0 2006.257.15:35:41.27#ibcon#read 3, iclass 39, count 0 2006.257.15:35:41.27#ibcon#about to read 4, iclass 39, count 0 2006.257.15:35:41.27#ibcon#read 4, iclass 39, count 0 2006.257.15:35:41.27#ibcon#about to read 5, iclass 39, count 0 2006.257.15:35:41.27#ibcon#read 5, iclass 39, count 0 2006.257.15:35:41.27#ibcon#about to read 6, iclass 39, count 0 2006.257.15:35:41.27#ibcon#read 6, iclass 39, count 0 2006.257.15:35:41.27#ibcon#end of sib2, iclass 39, count 0 2006.257.15:35:41.27#ibcon#*after write, iclass 39, count 0 2006.257.15:35:41.27#ibcon#*before return 0, iclass 39, count 0 2006.257.15:35:41.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:41.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:35:41.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:35:41.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:35:41.27$vck44/vb=2,5 2006.257.15:35:41.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.15:35:41.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.15:35:41.27#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:41.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:41.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:41.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:41.33#ibcon#enter wrdev, iclass 3, count 2 2006.257.15:35:41.33#ibcon#first serial, iclass 3, count 2 2006.257.15:35:41.33#ibcon#enter sib2, iclass 3, count 2 2006.257.15:35:41.33#ibcon#flushed, iclass 3, count 2 2006.257.15:35:41.33#ibcon#about to write, iclass 3, count 2 2006.257.15:35:41.33#ibcon#wrote, iclass 3, count 2 2006.257.15:35:41.33#ibcon#about to read 3, iclass 3, count 2 2006.257.15:35:41.35#ibcon#read 3, iclass 3, count 2 2006.257.15:35:41.35#ibcon#about to read 4, iclass 3, count 2 2006.257.15:35:41.35#ibcon#read 4, iclass 3, count 2 2006.257.15:35:41.35#ibcon#about to read 5, iclass 3, count 2 2006.257.15:35:41.35#ibcon#read 5, iclass 3, count 2 2006.257.15:35:41.35#ibcon#about to read 6, iclass 3, count 2 2006.257.15:35:41.35#ibcon#read 6, iclass 3, count 2 2006.257.15:35:41.35#ibcon#end of sib2, iclass 3, count 2 2006.257.15:35:41.35#ibcon#*mode == 0, iclass 3, count 2 2006.257.15:35:41.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.15:35:41.35#ibcon#[27=AT02-05\r\n] 2006.257.15:35:41.35#ibcon#*before write, iclass 3, count 2 2006.257.15:35:41.35#ibcon#enter sib2, iclass 3, count 2 2006.257.15:35:41.35#ibcon#flushed, iclass 3, count 2 2006.257.15:35:41.35#ibcon#about to write, iclass 3, count 2 2006.257.15:35:41.35#ibcon#wrote, iclass 3, count 2 2006.257.15:35:41.35#ibcon#about to read 3, iclass 3, count 2 2006.257.15:35:41.38#ibcon#read 3, iclass 3, count 2 2006.257.15:35:41.38#ibcon#about to read 4, iclass 3, count 2 2006.257.15:35:41.38#ibcon#read 4, iclass 3, count 2 2006.257.15:35:41.38#ibcon#about to read 5, iclass 3, count 2 2006.257.15:35:41.38#ibcon#read 5, iclass 3, count 2 2006.257.15:35:41.38#ibcon#about to read 6, iclass 3, count 2 2006.257.15:35:41.38#ibcon#read 6, iclass 3, count 2 2006.257.15:35:41.38#ibcon#end of sib2, iclass 3, count 2 2006.257.15:35:41.38#ibcon#*after write, iclass 3, count 2 2006.257.15:35:41.38#ibcon#*before return 0, iclass 3, count 2 2006.257.15:35:41.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:41.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:35:41.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.15:35:41.38#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:41.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:41.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:41.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:41.50#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:35:41.50#ibcon#first serial, iclass 3, count 0 2006.257.15:35:41.50#ibcon#enter sib2, iclass 3, count 0 2006.257.15:35:41.50#ibcon#flushed, iclass 3, count 0 2006.257.15:35:41.50#ibcon#about to write, iclass 3, count 0 2006.257.15:35:41.50#ibcon#wrote, iclass 3, count 0 2006.257.15:35:41.50#ibcon#about to read 3, iclass 3, count 0 2006.257.15:35:41.52#ibcon#read 3, iclass 3, count 0 2006.257.15:35:41.52#ibcon#about to read 4, iclass 3, count 0 2006.257.15:35:41.52#ibcon#read 4, iclass 3, count 0 2006.257.15:35:41.52#ibcon#about to read 5, iclass 3, count 0 2006.257.15:35:41.52#ibcon#read 5, iclass 3, count 0 2006.257.15:35:41.52#ibcon#about to read 6, iclass 3, count 0 2006.257.15:35:41.52#ibcon#read 6, iclass 3, count 0 2006.257.15:35:41.52#ibcon#end of sib2, iclass 3, count 0 2006.257.15:35:41.52#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:35:41.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:35:41.52#ibcon#[27=USB\r\n] 2006.257.15:35:41.52#ibcon#*before write, iclass 3, count 0 2006.257.15:35:41.52#ibcon#enter sib2, iclass 3, count 0 2006.257.15:35:41.52#ibcon#flushed, iclass 3, count 0 2006.257.15:35:41.52#ibcon#about to write, iclass 3, count 0 2006.257.15:35:41.52#ibcon#wrote, iclass 3, count 0 2006.257.15:35:41.52#ibcon#about to read 3, iclass 3, count 0 2006.257.15:35:41.55#ibcon#read 3, iclass 3, count 0 2006.257.15:35:41.55#ibcon#about to read 4, iclass 3, count 0 2006.257.15:35:41.55#ibcon#read 4, iclass 3, count 0 2006.257.15:35:41.55#ibcon#about to read 5, iclass 3, count 0 2006.257.15:35:41.55#ibcon#read 5, iclass 3, count 0 2006.257.15:35:41.55#ibcon#about to read 6, iclass 3, count 0 2006.257.15:35:41.55#ibcon#read 6, iclass 3, count 0 2006.257.15:35:41.55#ibcon#end of sib2, iclass 3, count 0 2006.257.15:35:41.55#ibcon#*after write, iclass 3, count 0 2006.257.15:35:41.55#ibcon#*before return 0, iclass 3, count 0 2006.257.15:35:41.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:41.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:35:41.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:35:41.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:35:41.55$vck44/vblo=3,649.99 2006.257.15:35:41.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.15:35:41.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.15:35:41.55#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:41.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:41.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:41.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:41.55#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:35:41.55#ibcon#first serial, iclass 5, count 0 2006.257.15:35:41.55#ibcon#enter sib2, iclass 5, count 0 2006.257.15:35:41.55#ibcon#flushed, iclass 5, count 0 2006.257.15:35:41.55#ibcon#about to write, iclass 5, count 0 2006.257.15:35:41.55#ibcon#wrote, iclass 5, count 0 2006.257.15:35:41.55#ibcon#about to read 3, iclass 5, count 0 2006.257.15:35:41.57#ibcon#read 3, iclass 5, count 0 2006.257.15:35:41.57#ibcon#about to read 4, iclass 5, count 0 2006.257.15:35:41.57#ibcon#read 4, iclass 5, count 0 2006.257.15:35:41.57#ibcon#about to read 5, iclass 5, count 0 2006.257.15:35:41.57#ibcon#read 5, iclass 5, count 0 2006.257.15:35:41.57#ibcon#about to read 6, iclass 5, count 0 2006.257.15:35:41.57#ibcon#read 6, iclass 5, count 0 2006.257.15:35:41.57#ibcon#end of sib2, iclass 5, count 0 2006.257.15:35:41.57#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:35:41.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:35:41.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:35:41.57#ibcon#*before write, iclass 5, count 0 2006.257.15:35:41.57#ibcon#enter sib2, iclass 5, count 0 2006.257.15:35:41.57#ibcon#flushed, iclass 5, count 0 2006.257.15:35:41.57#ibcon#about to write, iclass 5, count 0 2006.257.15:35:41.57#ibcon#wrote, iclass 5, count 0 2006.257.15:35:41.57#ibcon#about to read 3, iclass 5, count 0 2006.257.15:35:41.61#ibcon#read 3, iclass 5, count 0 2006.257.15:35:41.61#ibcon#about to read 4, iclass 5, count 0 2006.257.15:35:41.61#ibcon#read 4, iclass 5, count 0 2006.257.15:35:41.61#ibcon#about to read 5, iclass 5, count 0 2006.257.15:35:41.61#ibcon#read 5, iclass 5, count 0 2006.257.15:35:41.61#ibcon#about to read 6, iclass 5, count 0 2006.257.15:35:41.61#ibcon#read 6, iclass 5, count 0 2006.257.15:35:41.61#ibcon#end of sib2, iclass 5, count 0 2006.257.15:35:41.61#ibcon#*after write, iclass 5, count 0 2006.257.15:35:41.61#ibcon#*before return 0, iclass 5, count 0 2006.257.15:35:41.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:41.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:35:41.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:35:41.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:35:41.61$vck44/vb=3,4 2006.257.15:35:41.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.15:35:41.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.15:35:41.61#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:41.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:41.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:41.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:41.67#ibcon#enter wrdev, iclass 7, count 2 2006.257.15:35:41.67#ibcon#first serial, iclass 7, count 2 2006.257.15:35:41.67#ibcon#enter sib2, iclass 7, count 2 2006.257.15:35:41.67#ibcon#flushed, iclass 7, count 2 2006.257.15:35:41.67#ibcon#about to write, iclass 7, count 2 2006.257.15:35:41.67#ibcon#wrote, iclass 7, count 2 2006.257.15:35:41.67#ibcon#about to read 3, iclass 7, count 2 2006.257.15:35:41.69#ibcon#read 3, iclass 7, count 2 2006.257.15:35:41.69#ibcon#about to read 4, iclass 7, count 2 2006.257.15:35:41.69#ibcon#read 4, iclass 7, count 2 2006.257.15:35:41.69#ibcon#about to read 5, iclass 7, count 2 2006.257.15:35:41.69#ibcon#read 5, iclass 7, count 2 2006.257.15:35:41.69#ibcon#about to read 6, iclass 7, count 2 2006.257.15:35:41.69#ibcon#read 6, iclass 7, count 2 2006.257.15:35:41.69#ibcon#end of sib2, iclass 7, count 2 2006.257.15:35:41.69#ibcon#*mode == 0, iclass 7, count 2 2006.257.15:35:41.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.15:35:41.69#ibcon#[27=AT03-04\r\n] 2006.257.15:35:41.69#ibcon#*before write, iclass 7, count 2 2006.257.15:35:41.69#ibcon#enter sib2, iclass 7, count 2 2006.257.15:35:41.69#ibcon#flushed, iclass 7, count 2 2006.257.15:35:41.69#ibcon#about to write, iclass 7, count 2 2006.257.15:35:41.69#ibcon#wrote, iclass 7, count 2 2006.257.15:35:41.69#ibcon#about to read 3, iclass 7, count 2 2006.257.15:35:41.72#ibcon#read 3, iclass 7, count 2 2006.257.15:35:41.72#ibcon#about to read 4, iclass 7, count 2 2006.257.15:35:41.72#ibcon#read 4, iclass 7, count 2 2006.257.15:35:41.72#ibcon#about to read 5, iclass 7, count 2 2006.257.15:35:41.72#ibcon#read 5, iclass 7, count 2 2006.257.15:35:41.72#ibcon#about to read 6, iclass 7, count 2 2006.257.15:35:41.72#ibcon#read 6, iclass 7, count 2 2006.257.15:35:41.72#ibcon#end of sib2, iclass 7, count 2 2006.257.15:35:41.72#ibcon#*after write, iclass 7, count 2 2006.257.15:35:41.72#ibcon#*before return 0, iclass 7, count 2 2006.257.15:35:41.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:41.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:35:41.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.15:35:41.72#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:41.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:41.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:41.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:41.84#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:35:41.84#ibcon#first serial, iclass 7, count 0 2006.257.15:35:41.84#ibcon#enter sib2, iclass 7, count 0 2006.257.15:35:41.84#ibcon#flushed, iclass 7, count 0 2006.257.15:35:41.84#ibcon#about to write, iclass 7, count 0 2006.257.15:35:41.84#ibcon#wrote, iclass 7, count 0 2006.257.15:35:41.84#ibcon#about to read 3, iclass 7, count 0 2006.257.15:35:41.86#ibcon#read 3, iclass 7, count 0 2006.257.15:35:41.86#ibcon#about to read 4, iclass 7, count 0 2006.257.15:35:41.86#ibcon#read 4, iclass 7, count 0 2006.257.15:35:41.86#ibcon#about to read 5, iclass 7, count 0 2006.257.15:35:41.86#ibcon#read 5, iclass 7, count 0 2006.257.15:35:41.86#ibcon#about to read 6, iclass 7, count 0 2006.257.15:35:41.86#ibcon#read 6, iclass 7, count 0 2006.257.15:35:41.86#ibcon#end of sib2, iclass 7, count 0 2006.257.15:35:41.86#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:35:41.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:35:41.86#ibcon#[27=USB\r\n] 2006.257.15:35:41.86#ibcon#*before write, iclass 7, count 0 2006.257.15:35:41.86#ibcon#enter sib2, iclass 7, count 0 2006.257.15:35:41.86#ibcon#flushed, iclass 7, count 0 2006.257.15:35:41.86#ibcon#about to write, iclass 7, count 0 2006.257.15:35:41.86#ibcon#wrote, iclass 7, count 0 2006.257.15:35:41.86#ibcon#about to read 3, iclass 7, count 0 2006.257.15:35:41.89#ibcon#read 3, iclass 7, count 0 2006.257.15:35:41.89#ibcon#about to read 4, iclass 7, count 0 2006.257.15:35:41.89#ibcon#read 4, iclass 7, count 0 2006.257.15:35:41.89#ibcon#about to read 5, iclass 7, count 0 2006.257.15:35:41.89#ibcon#read 5, iclass 7, count 0 2006.257.15:35:41.89#ibcon#about to read 6, iclass 7, count 0 2006.257.15:35:41.89#ibcon#read 6, iclass 7, count 0 2006.257.15:35:41.89#ibcon#end of sib2, iclass 7, count 0 2006.257.15:35:41.89#ibcon#*after write, iclass 7, count 0 2006.257.15:35:41.89#ibcon#*before return 0, iclass 7, count 0 2006.257.15:35:41.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:41.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:35:41.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:35:41.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:35:41.89$vck44/vblo=4,679.99 2006.257.15:35:41.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.15:35:41.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.15:35:41.89#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:41.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:41.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:41.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:41.89#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:35:41.89#ibcon#first serial, iclass 11, count 0 2006.257.15:35:41.89#ibcon#enter sib2, iclass 11, count 0 2006.257.15:35:41.89#ibcon#flushed, iclass 11, count 0 2006.257.15:35:41.89#ibcon#about to write, iclass 11, count 0 2006.257.15:35:41.89#ibcon#wrote, iclass 11, count 0 2006.257.15:35:41.89#ibcon#about to read 3, iclass 11, count 0 2006.257.15:35:41.91#ibcon#read 3, iclass 11, count 0 2006.257.15:35:41.91#ibcon#about to read 4, iclass 11, count 0 2006.257.15:35:41.91#ibcon#read 4, iclass 11, count 0 2006.257.15:35:41.91#ibcon#about to read 5, iclass 11, count 0 2006.257.15:35:41.91#ibcon#read 5, iclass 11, count 0 2006.257.15:35:41.91#ibcon#about to read 6, iclass 11, count 0 2006.257.15:35:41.91#ibcon#read 6, iclass 11, count 0 2006.257.15:35:41.91#ibcon#end of sib2, iclass 11, count 0 2006.257.15:35:41.91#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:35:41.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:35:41.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:35:41.91#ibcon#*before write, iclass 11, count 0 2006.257.15:35:41.91#ibcon#enter sib2, iclass 11, count 0 2006.257.15:35:41.91#ibcon#flushed, iclass 11, count 0 2006.257.15:35:41.91#ibcon#about to write, iclass 11, count 0 2006.257.15:35:41.91#ibcon#wrote, iclass 11, count 0 2006.257.15:35:41.91#ibcon#about to read 3, iclass 11, count 0 2006.257.15:35:41.95#ibcon#read 3, iclass 11, count 0 2006.257.15:35:41.95#ibcon#about to read 4, iclass 11, count 0 2006.257.15:35:41.95#ibcon#read 4, iclass 11, count 0 2006.257.15:35:41.95#ibcon#about to read 5, iclass 11, count 0 2006.257.15:35:41.95#ibcon#read 5, iclass 11, count 0 2006.257.15:35:41.95#ibcon#about to read 6, iclass 11, count 0 2006.257.15:35:41.95#ibcon#read 6, iclass 11, count 0 2006.257.15:35:41.95#ibcon#end of sib2, iclass 11, count 0 2006.257.15:35:41.95#ibcon#*after write, iclass 11, count 0 2006.257.15:35:41.95#ibcon#*before return 0, iclass 11, count 0 2006.257.15:35:41.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:41.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:35:41.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:35:41.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:35:41.95$vck44/vb=4,5 2006.257.15:35:41.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.15:35:41.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.15:35:41.95#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:41.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:42.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:42.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:42.01#ibcon#enter wrdev, iclass 13, count 2 2006.257.15:35:42.01#ibcon#first serial, iclass 13, count 2 2006.257.15:35:42.01#ibcon#enter sib2, iclass 13, count 2 2006.257.15:35:42.01#ibcon#flushed, iclass 13, count 2 2006.257.15:35:42.01#ibcon#about to write, iclass 13, count 2 2006.257.15:35:42.01#ibcon#wrote, iclass 13, count 2 2006.257.15:35:42.01#ibcon#about to read 3, iclass 13, count 2 2006.257.15:35:42.03#ibcon#read 3, iclass 13, count 2 2006.257.15:35:42.03#ibcon#about to read 4, iclass 13, count 2 2006.257.15:35:42.03#ibcon#read 4, iclass 13, count 2 2006.257.15:35:42.03#ibcon#about to read 5, iclass 13, count 2 2006.257.15:35:42.03#ibcon#read 5, iclass 13, count 2 2006.257.15:35:42.03#ibcon#about to read 6, iclass 13, count 2 2006.257.15:35:42.03#ibcon#read 6, iclass 13, count 2 2006.257.15:35:42.03#ibcon#end of sib2, iclass 13, count 2 2006.257.15:35:42.03#ibcon#*mode == 0, iclass 13, count 2 2006.257.15:35:42.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.15:35:42.03#ibcon#[27=AT04-05\r\n] 2006.257.15:35:42.03#ibcon#*before write, iclass 13, count 2 2006.257.15:35:42.03#ibcon#enter sib2, iclass 13, count 2 2006.257.15:35:42.03#ibcon#flushed, iclass 13, count 2 2006.257.15:35:42.03#ibcon#about to write, iclass 13, count 2 2006.257.15:35:42.03#ibcon#wrote, iclass 13, count 2 2006.257.15:35:42.03#ibcon#about to read 3, iclass 13, count 2 2006.257.15:35:42.06#ibcon#read 3, iclass 13, count 2 2006.257.15:35:42.06#ibcon#about to read 4, iclass 13, count 2 2006.257.15:35:42.06#ibcon#read 4, iclass 13, count 2 2006.257.15:35:42.06#ibcon#about to read 5, iclass 13, count 2 2006.257.15:35:42.06#ibcon#read 5, iclass 13, count 2 2006.257.15:35:42.06#ibcon#about to read 6, iclass 13, count 2 2006.257.15:35:42.06#ibcon#read 6, iclass 13, count 2 2006.257.15:35:42.06#ibcon#end of sib2, iclass 13, count 2 2006.257.15:35:42.06#ibcon#*after write, iclass 13, count 2 2006.257.15:35:42.06#ibcon#*before return 0, iclass 13, count 2 2006.257.15:35:42.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:42.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:35:42.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.15:35:42.06#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:42.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:42.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:42.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:42.18#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:35:42.18#ibcon#first serial, iclass 13, count 0 2006.257.15:35:42.18#ibcon#enter sib2, iclass 13, count 0 2006.257.15:35:42.18#ibcon#flushed, iclass 13, count 0 2006.257.15:35:42.18#ibcon#about to write, iclass 13, count 0 2006.257.15:35:42.18#ibcon#wrote, iclass 13, count 0 2006.257.15:35:42.18#ibcon#about to read 3, iclass 13, count 0 2006.257.15:35:42.20#ibcon#read 3, iclass 13, count 0 2006.257.15:35:42.20#ibcon#about to read 4, iclass 13, count 0 2006.257.15:35:42.20#ibcon#read 4, iclass 13, count 0 2006.257.15:35:42.20#ibcon#about to read 5, iclass 13, count 0 2006.257.15:35:42.20#ibcon#read 5, iclass 13, count 0 2006.257.15:35:42.20#ibcon#about to read 6, iclass 13, count 0 2006.257.15:35:42.20#ibcon#read 6, iclass 13, count 0 2006.257.15:35:42.20#ibcon#end of sib2, iclass 13, count 0 2006.257.15:35:42.20#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:35:42.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:35:42.20#ibcon#[27=USB\r\n] 2006.257.15:35:42.20#ibcon#*before write, iclass 13, count 0 2006.257.15:35:42.20#ibcon#enter sib2, iclass 13, count 0 2006.257.15:35:42.20#ibcon#flushed, iclass 13, count 0 2006.257.15:35:42.20#ibcon#about to write, iclass 13, count 0 2006.257.15:35:42.20#ibcon#wrote, iclass 13, count 0 2006.257.15:35:42.20#ibcon#about to read 3, iclass 13, count 0 2006.257.15:35:42.23#ibcon#read 3, iclass 13, count 0 2006.257.15:35:42.23#ibcon#about to read 4, iclass 13, count 0 2006.257.15:35:42.23#ibcon#read 4, iclass 13, count 0 2006.257.15:35:42.23#ibcon#about to read 5, iclass 13, count 0 2006.257.15:35:42.23#ibcon#read 5, iclass 13, count 0 2006.257.15:35:42.23#ibcon#about to read 6, iclass 13, count 0 2006.257.15:35:42.23#ibcon#read 6, iclass 13, count 0 2006.257.15:35:42.23#ibcon#end of sib2, iclass 13, count 0 2006.257.15:35:42.23#ibcon#*after write, iclass 13, count 0 2006.257.15:35:42.23#ibcon#*before return 0, iclass 13, count 0 2006.257.15:35:42.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:42.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:35:42.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:35:42.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:35:42.23$vck44/vblo=5,709.99 2006.257.15:35:42.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.15:35:42.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.15:35:42.23#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:42.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:35:42.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:35:42.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:35:42.23#ibcon#enter wrdev, iclass 15, count 0 2006.257.15:35:42.23#ibcon#first serial, iclass 15, count 0 2006.257.15:35:42.23#ibcon#enter sib2, iclass 15, count 0 2006.257.15:35:42.23#ibcon#flushed, iclass 15, count 0 2006.257.15:35:42.23#ibcon#about to write, iclass 15, count 0 2006.257.15:35:42.23#ibcon#wrote, iclass 15, count 0 2006.257.15:35:42.23#ibcon#about to read 3, iclass 15, count 0 2006.257.15:35:42.25#ibcon#read 3, iclass 15, count 0 2006.257.15:35:42.25#ibcon#about to read 4, iclass 15, count 0 2006.257.15:35:42.25#ibcon#read 4, iclass 15, count 0 2006.257.15:35:42.25#ibcon#about to read 5, iclass 15, count 0 2006.257.15:35:42.25#ibcon#read 5, iclass 15, count 0 2006.257.15:35:42.25#ibcon#about to read 6, iclass 15, count 0 2006.257.15:35:42.25#ibcon#read 6, iclass 15, count 0 2006.257.15:35:42.25#ibcon#end of sib2, iclass 15, count 0 2006.257.15:35:42.25#ibcon#*mode == 0, iclass 15, count 0 2006.257.15:35:42.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.15:35:42.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:35:42.25#ibcon#*before write, iclass 15, count 0 2006.257.15:35:42.25#ibcon#enter sib2, iclass 15, count 0 2006.257.15:35:42.25#ibcon#flushed, iclass 15, count 0 2006.257.15:35:42.25#ibcon#about to write, iclass 15, count 0 2006.257.15:35:42.25#ibcon#wrote, iclass 15, count 0 2006.257.15:35:42.25#ibcon#about to read 3, iclass 15, count 0 2006.257.15:35:42.29#ibcon#read 3, iclass 15, count 0 2006.257.15:35:42.29#ibcon#about to read 4, iclass 15, count 0 2006.257.15:35:42.29#ibcon#read 4, iclass 15, count 0 2006.257.15:35:42.29#ibcon#about to read 5, iclass 15, count 0 2006.257.15:35:42.29#ibcon#read 5, iclass 15, count 0 2006.257.15:35:42.29#ibcon#about to read 6, iclass 15, count 0 2006.257.15:35:42.29#ibcon#read 6, iclass 15, count 0 2006.257.15:35:42.29#ibcon#end of sib2, iclass 15, count 0 2006.257.15:35:42.29#ibcon#*after write, iclass 15, count 0 2006.257.15:35:42.29#ibcon#*before return 0, iclass 15, count 0 2006.257.15:35:42.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:35:42.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:35:42.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.15:35:42.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.15:35:42.29$vck44/vb=5,4 2006.257.15:35:42.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.15:35:42.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.15:35:42.29#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:42.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:35:42.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:35:42.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:35:42.35#ibcon#enter wrdev, iclass 17, count 2 2006.257.15:35:42.35#ibcon#first serial, iclass 17, count 2 2006.257.15:35:42.35#ibcon#enter sib2, iclass 17, count 2 2006.257.15:35:42.35#ibcon#flushed, iclass 17, count 2 2006.257.15:35:42.35#ibcon#about to write, iclass 17, count 2 2006.257.15:35:42.35#ibcon#wrote, iclass 17, count 2 2006.257.15:35:42.35#ibcon#about to read 3, iclass 17, count 2 2006.257.15:35:42.37#ibcon#read 3, iclass 17, count 2 2006.257.15:35:42.37#ibcon#about to read 4, iclass 17, count 2 2006.257.15:35:42.37#ibcon#read 4, iclass 17, count 2 2006.257.15:35:42.37#ibcon#about to read 5, iclass 17, count 2 2006.257.15:35:42.37#ibcon#read 5, iclass 17, count 2 2006.257.15:35:42.37#ibcon#about to read 6, iclass 17, count 2 2006.257.15:35:42.37#ibcon#read 6, iclass 17, count 2 2006.257.15:35:42.37#ibcon#end of sib2, iclass 17, count 2 2006.257.15:35:42.37#ibcon#*mode == 0, iclass 17, count 2 2006.257.15:35:42.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.15:35:42.37#ibcon#[27=AT05-04\r\n] 2006.257.15:35:42.37#ibcon#*before write, iclass 17, count 2 2006.257.15:35:42.37#ibcon#enter sib2, iclass 17, count 2 2006.257.15:35:42.37#ibcon#flushed, iclass 17, count 2 2006.257.15:35:42.37#ibcon#about to write, iclass 17, count 2 2006.257.15:35:42.37#ibcon#wrote, iclass 17, count 2 2006.257.15:35:42.37#ibcon#about to read 3, iclass 17, count 2 2006.257.15:35:42.40#ibcon#read 3, iclass 17, count 2 2006.257.15:35:42.40#ibcon#about to read 4, iclass 17, count 2 2006.257.15:35:42.40#ibcon#read 4, iclass 17, count 2 2006.257.15:35:42.40#ibcon#about to read 5, iclass 17, count 2 2006.257.15:35:42.40#ibcon#read 5, iclass 17, count 2 2006.257.15:35:42.40#ibcon#about to read 6, iclass 17, count 2 2006.257.15:35:42.40#ibcon#read 6, iclass 17, count 2 2006.257.15:35:42.40#ibcon#end of sib2, iclass 17, count 2 2006.257.15:35:42.40#ibcon#*after write, iclass 17, count 2 2006.257.15:35:42.40#ibcon#*before return 0, iclass 17, count 2 2006.257.15:35:42.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:35:42.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:35:42.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.15:35:42.40#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:42.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:35:42.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:35:42.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:35:42.52#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:35:42.52#ibcon#first serial, iclass 17, count 0 2006.257.15:35:42.52#ibcon#enter sib2, iclass 17, count 0 2006.257.15:35:42.52#ibcon#flushed, iclass 17, count 0 2006.257.15:35:42.52#ibcon#about to write, iclass 17, count 0 2006.257.15:35:42.52#ibcon#wrote, iclass 17, count 0 2006.257.15:35:42.52#ibcon#about to read 3, iclass 17, count 0 2006.257.15:35:42.54#ibcon#read 3, iclass 17, count 0 2006.257.15:35:42.54#ibcon#about to read 4, iclass 17, count 0 2006.257.15:35:42.54#ibcon#read 4, iclass 17, count 0 2006.257.15:35:42.54#ibcon#about to read 5, iclass 17, count 0 2006.257.15:35:42.54#ibcon#read 5, iclass 17, count 0 2006.257.15:35:42.54#ibcon#about to read 6, iclass 17, count 0 2006.257.15:35:42.54#ibcon#read 6, iclass 17, count 0 2006.257.15:35:42.54#ibcon#end of sib2, iclass 17, count 0 2006.257.15:35:42.54#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:35:42.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:35:42.54#ibcon#[27=USB\r\n] 2006.257.15:35:42.54#ibcon#*before write, iclass 17, count 0 2006.257.15:35:42.54#ibcon#enter sib2, iclass 17, count 0 2006.257.15:35:42.54#ibcon#flushed, iclass 17, count 0 2006.257.15:35:42.54#ibcon#about to write, iclass 17, count 0 2006.257.15:35:42.54#ibcon#wrote, iclass 17, count 0 2006.257.15:35:42.54#ibcon#about to read 3, iclass 17, count 0 2006.257.15:35:42.57#ibcon#read 3, iclass 17, count 0 2006.257.15:35:42.57#ibcon#about to read 4, iclass 17, count 0 2006.257.15:35:42.57#ibcon#read 4, iclass 17, count 0 2006.257.15:35:42.57#ibcon#about to read 5, iclass 17, count 0 2006.257.15:35:42.57#ibcon#read 5, iclass 17, count 0 2006.257.15:35:42.57#ibcon#about to read 6, iclass 17, count 0 2006.257.15:35:42.57#ibcon#read 6, iclass 17, count 0 2006.257.15:35:42.57#ibcon#end of sib2, iclass 17, count 0 2006.257.15:35:42.57#ibcon#*after write, iclass 17, count 0 2006.257.15:35:42.57#ibcon#*before return 0, iclass 17, count 0 2006.257.15:35:42.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:35:42.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:35:42.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:35:42.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:35:42.57$vck44/vblo=6,719.99 2006.257.15:35:42.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.15:35:42.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.15:35:42.57#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:42.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:42.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:42.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:42.57#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:35:42.57#ibcon#first serial, iclass 19, count 0 2006.257.15:35:42.57#ibcon#enter sib2, iclass 19, count 0 2006.257.15:35:42.57#ibcon#flushed, iclass 19, count 0 2006.257.15:35:42.57#ibcon#about to write, iclass 19, count 0 2006.257.15:35:42.57#ibcon#wrote, iclass 19, count 0 2006.257.15:35:42.57#ibcon#about to read 3, iclass 19, count 0 2006.257.15:35:42.59#ibcon#read 3, iclass 19, count 0 2006.257.15:35:42.59#ibcon#about to read 4, iclass 19, count 0 2006.257.15:35:42.59#ibcon#read 4, iclass 19, count 0 2006.257.15:35:42.59#ibcon#about to read 5, iclass 19, count 0 2006.257.15:35:42.59#ibcon#read 5, iclass 19, count 0 2006.257.15:35:42.59#ibcon#about to read 6, iclass 19, count 0 2006.257.15:35:42.59#ibcon#read 6, iclass 19, count 0 2006.257.15:35:42.59#ibcon#end of sib2, iclass 19, count 0 2006.257.15:35:42.59#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:35:42.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:35:42.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:35:42.59#ibcon#*before write, iclass 19, count 0 2006.257.15:35:42.59#ibcon#enter sib2, iclass 19, count 0 2006.257.15:35:42.59#ibcon#flushed, iclass 19, count 0 2006.257.15:35:42.59#ibcon#about to write, iclass 19, count 0 2006.257.15:35:42.59#ibcon#wrote, iclass 19, count 0 2006.257.15:35:42.59#ibcon#about to read 3, iclass 19, count 0 2006.257.15:35:42.63#ibcon#read 3, iclass 19, count 0 2006.257.15:35:42.63#ibcon#about to read 4, iclass 19, count 0 2006.257.15:35:42.63#ibcon#read 4, iclass 19, count 0 2006.257.15:35:42.63#ibcon#about to read 5, iclass 19, count 0 2006.257.15:35:42.63#ibcon#read 5, iclass 19, count 0 2006.257.15:35:42.63#ibcon#about to read 6, iclass 19, count 0 2006.257.15:35:42.63#ibcon#read 6, iclass 19, count 0 2006.257.15:35:42.63#ibcon#end of sib2, iclass 19, count 0 2006.257.15:35:42.63#ibcon#*after write, iclass 19, count 0 2006.257.15:35:42.63#ibcon#*before return 0, iclass 19, count 0 2006.257.15:35:42.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:42.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:35:42.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:35:42.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:35:42.63$vck44/vb=6,4 2006.257.15:35:42.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.15:35:42.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.15:35:42.63#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:42.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:42.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:42.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:42.69#ibcon#enter wrdev, iclass 21, count 2 2006.257.15:35:42.69#ibcon#first serial, iclass 21, count 2 2006.257.15:35:42.69#ibcon#enter sib2, iclass 21, count 2 2006.257.15:35:42.69#ibcon#flushed, iclass 21, count 2 2006.257.15:35:42.69#ibcon#about to write, iclass 21, count 2 2006.257.15:35:42.69#ibcon#wrote, iclass 21, count 2 2006.257.15:35:42.69#ibcon#about to read 3, iclass 21, count 2 2006.257.15:35:42.71#ibcon#read 3, iclass 21, count 2 2006.257.15:35:42.71#ibcon#about to read 4, iclass 21, count 2 2006.257.15:35:42.71#ibcon#read 4, iclass 21, count 2 2006.257.15:35:42.71#ibcon#about to read 5, iclass 21, count 2 2006.257.15:35:42.71#ibcon#read 5, iclass 21, count 2 2006.257.15:35:42.71#ibcon#about to read 6, iclass 21, count 2 2006.257.15:35:42.71#ibcon#read 6, iclass 21, count 2 2006.257.15:35:42.71#ibcon#end of sib2, iclass 21, count 2 2006.257.15:35:42.71#ibcon#*mode == 0, iclass 21, count 2 2006.257.15:35:42.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.15:35:42.71#ibcon#[27=AT06-04\r\n] 2006.257.15:35:42.71#ibcon#*before write, iclass 21, count 2 2006.257.15:35:42.71#ibcon#enter sib2, iclass 21, count 2 2006.257.15:35:42.71#ibcon#flushed, iclass 21, count 2 2006.257.15:35:42.71#ibcon#about to write, iclass 21, count 2 2006.257.15:35:42.71#ibcon#wrote, iclass 21, count 2 2006.257.15:35:42.71#ibcon#about to read 3, iclass 21, count 2 2006.257.15:35:42.74#ibcon#read 3, iclass 21, count 2 2006.257.15:35:42.74#ibcon#about to read 4, iclass 21, count 2 2006.257.15:35:42.74#ibcon#read 4, iclass 21, count 2 2006.257.15:35:42.74#ibcon#about to read 5, iclass 21, count 2 2006.257.15:35:42.74#ibcon#read 5, iclass 21, count 2 2006.257.15:35:42.74#ibcon#about to read 6, iclass 21, count 2 2006.257.15:35:42.74#ibcon#read 6, iclass 21, count 2 2006.257.15:35:42.74#ibcon#end of sib2, iclass 21, count 2 2006.257.15:35:42.74#ibcon#*after write, iclass 21, count 2 2006.257.15:35:42.74#ibcon#*before return 0, iclass 21, count 2 2006.257.15:35:42.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:42.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:35:42.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.15:35:42.74#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:42.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:42.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:42.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:42.86#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:35:42.86#ibcon#first serial, iclass 21, count 0 2006.257.15:35:42.86#ibcon#enter sib2, iclass 21, count 0 2006.257.15:35:42.86#ibcon#flushed, iclass 21, count 0 2006.257.15:35:42.86#ibcon#about to write, iclass 21, count 0 2006.257.15:35:42.86#ibcon#wrote, iclass 21, count 0 2006.257.15:35:42.86#ibcon#about to read 3, iclass 21, count 0 2006.257.15:35:42.88#ibcon#read 3, iclass 21, count 0 2006.257.15:35:42.88#ibcon#about to read 4, iclass 21, count 0 2006.257.15:35:42.88#ibcon#read 4, iclass 21, count 0 2006.257.15:35:42.88#ibcon#about to read 5, iclass 21, count 0 2006.257.15:35:42.88#ibcon#read 5, iclass 21, count 0 2006.257.15:35:42.88#ibcon#about to read 6, iclass 21, count 0 2006.257.15:35:42.88#ibcon#read 6, iclass 21, count 0 2006.257.15:35:42.88#ibcon#end of sib2, iclass 21, count 0 2006.257.15:35:42.88#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:35:42.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:35:42.88#ibcon#[27=USB\r\n] 2006.257.15:35:42.88#ibcon#*before write, iclass 21, count 0 2006.257.15:35:42.88#ibcon#enter sib2, iclass 21, count 0 2006.257.15:35:42.88#ibcon#flushed, iclass 21, count 0 2006.257.15:35:42.88#ibcon#about to write, iclass 21, count 0 2006.257.15:35:42.88#ibcon#wrote, iclass 21, count 0 2006.257.15:35:42.88#ibcon#about to read 3, iclass 21, count 0 2006.257.15:35:42.91#ibcon#read 3, iclass 21, count 0 2006.257.15:35:42.91#ibcon#about to read 4, iclass 21, count 0 2006.257.15:35:42.91#ibcon#read 4, iclass 21, count 0 2006.257.15:35:42.91#ibcon#about to read 5, iclass 21, count 0 2006.257.15:35:42.91#ibcon#read 5, iclass 21, count 0 2006.257.15:35:42.91#ibcon#about to read 6, iclass 21, count 0 2006.257.15:35:42.91#ibcon#read 6, iclass 21, count 0 2006.257.15:35:42.91#ibcon#end of sib2, iclass 21, count 0 2006.257.15:35:42.91#ibcon#*after write, iclass 21, count 0 2006.257.15:35:42.91#ibcon#*before return 0, iclass 21, count 0 2006.257.15:35:42.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:42.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:35:42.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:35:42.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:35:42.91$vck44/vblo=7,734.99 2006.257.15:35:42.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.15:35:42.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.15:35:42.91#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:42.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:42.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:42.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:42.91#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:35:42.91#ibcon#first serial, iclass 23, count 0 2006.257.15:35:42.91#ibcon#enter sib2, iclass 23, count 0 2006.257.15:35:42.91#ibcon#flushed, iclass 23, count 0 2006.257.15:35:42.91#ibcon#about to write, iclass 23, count 0 2006.257.15:35:42.91#ibcon#wrote, iclass 23, count 0 2006.257.15:35:42.91#ibcon#about to read 3, iclass 23, count 0 2006.257.15:35:42.93#ibcon#read 3, iclass 23, count 0 2006.257.15:35:42.93#ibcon#about to read 4, iclass 23, count 0 2006.257.15:35:42.93#ibcon#read 4, iclass 23, count 0 2006.257.15:35:42.93#ibcon#about to read 5, iclass 23, count 0 2006.257.15:35:42.93#ibcon#read 5, iclass 23, count 0 2006.257.15:35:42.93#ibcon#about to read 6, iclass 23, count 0 2006.257.15:35:42.93#ibcon#read 6, iclass 23, count 0 2006.257.15:35:42.93#ibcon#end of sib2, iclass 23, count 0 2006.257.15:35:42.93#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:35:42.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:35:42.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:35:42.93#ibcon#*before write, iclass 23, count 0 2006.257.15:35:42.93#ibcon#enter sib2, iclass 23, count 0 2006.257.15:35:42.93#ibcon#flushed, iclass 23, count 0 2006.257.15:35:42.93#ibcon#about to write, iclass 23, count 0 2006.257.15:35:42.93#ibcon#wrote, iclass 23, count 0 2006.257.15:35:42.93#ibcon#about to read 3, iclass 23, count 0 2006.257.15:35:42.97#ibcon#read 3, iclass 23, count 0 2006.257.15:35:42.97#ibcon#about to read 4, iclass 23, count 0 2006.257.15:35:42.97#ibcon#read 4, iclass 23, count 0 2006.257.15:35:42.97#ibcon#about to read 5, iclass 23, count 0 2006.257.15:35:42.97#ibcon#read 5, iclass 23, count 0 2006.257.15:35:42.97#ibcon#about to read 6, iclass 23, count 0 2006.257.15:35:42.97#ibcon#read 6, iclass 23, count 0 2006.257.15:35:42.97#ibcon#end of sib2, iclass 23, count 0 2006.257.15:35:42.97#ibcon#*after write, iclass 23, count 0 2006.257.15:35:42.97#ibcon#*before return 0, iclass 23, count 0 2006.257.15:35:42.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:42.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:35:42.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:35:42.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:35:42.97$vck44/vb=7,4 2006.257.15:35:42.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.15:35:42.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.15:35:42.97#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:42.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:43.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:43.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:43.03#ibcon#enter wrdev, iclass 25, count 2 2006.257.15:35:43.03#ibcon#first serial, iclass 25, count 2 2006.257.15:35:43.03#ibcon#enter sib2, iclass 25, count 2 2006.257.15:35:43.03#ibcon#flushed, iclass 25, count 2 2006.257.15:35:43.03#ibcon#about to write, iclass 25, count 2 2006.257.15:35:43.03#ibcon#wrote, iclass 25, count 2 2006.257.15:35:43.03#ibcon#about to read 3, iclass 25, count 2 2006.257.15:35:43.05#ibcon#read 3, iclass 25, count 2 2006.257.15:35:43.05#ibcon#about to read 4, iclass 25, count 2 2006.257.15:35:43.05#ibcon#read 4, iclass 25, count 2 2006.257.15:35:43.05#ibcon#about to read 5, iclass 25, count 2 2006.257.15:35:43.05#ibcon#read 5, iclass 25, count 2 2006.257.15:35:43.05#ibcon#about to read 6, iclass 25, count 2 2006.257.15:35:43.05#ibcon#read 6, iclass 25, count 2 2006.257.15:35:43.05#ibcon#end of sib2, iclass 25, count 2 2006.257.15:35:43.05#ibcon#*mode == 0, iclass 25, count 2 2006.257.15:35:43.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.15:35:43.05#ibcon#[27=AT07-04\r\n] 2006.257.15:35:43.05#ibcon#*before write, iclass 25, count 2 2006.257.15:35:43.05#ibcon#enter sib2, iclass 25, count 2 2006.257.15:35:43.05#ibcon#flushed, iclass 25, count 2 2006.257.15:35:43.05#ibcon#about to write, iclass 25, count 2 2006.257.15:35:43.05#ibcon#wrote, iclass 25, count 2 2006.257.15:35:43.05#ibcon#about to read 3, iclass 25, count 2 2006.257.15:35:43.08#ibcon#read 3, iclass 25, count 2 2006.257.15:35:43.08#ibcon#about to read 4, iclass 25, count 2 2006.257.15:35:43.08#ibcon#read 4, iclass 25, count 2 2006.257.15:35:43.08#ibcon#about to read 5, iclass 25, count 2 2006.257.15:35:43.08#ibcon#read 5, iclass 25, count 2 2006.257.15:35:43.08#ibcon#about to read 6, iclass 25, count 2 2006.257.15:35:43.08#ibcon#read 6, iclass 25, count 2 2006.257.15:35:43.08#ibcon#end of sib2, iclass 25, count 2 2006.257.15:35:43.08#ibcon#*after write, iclass 25, count 2 2006.257.15:35:43.08#ibcon#*before return 0, iclass 25, count 2 2006.257.15:35:43.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:43.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:35:43.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.15:35:43.08#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:43.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:43.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:43.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:43.20#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:35:43.20#ibcon#first serial, iclass 25, count 0 2006.257.15:35:43.20#ibcon#enter sib2, iclass 25, count 0 2006.257.15:35:43.20#ibcon#flushed, iclass 25, count 0 2006.257.15:35:43.20#ibcon#about to write, iclass 25, count 0 2006.257.15:35:43.20#ibcon#wrote, iclass 25, count 0 2006.257.15:35:43.20#ibcon#about to read 3, iclass 25, count 0 2006.257.15:35:43.22#ibcon#read 3, iclass 25, count 0 2006.257.15:35:43.22#ibcon#about to read 4, iclass 25, count 0 2006.257.15:35:43.22#ibcon#read 4, iclass 25, count 0 2006.257.15:35:43.22#ibcon#about to read 5, iclass 25, count 0 2006.257.15:35:43.22#ibcon#read 5, iclass 25, count 0 2006.257.15:35:43.22#ibcon#about to read 6, iclass 25, count 0 2006.257.15:35:43.22#ibcon#read 6, iclass 25, count 0 2006.257.15:35:43.22#ibcon#end of sib2, iclass 25, count 0 2006.257.15:35:43.22#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:35:43.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:35:43.22#ibcon#[27=USB\r\n] 2006.257.15:35:43.22#ibcon#*before write, iclass 25, count 0 2006.257.15:35:43.22#ibcon#enter sib2, iclass 25, count 0 2006.257.15:35:43.22#ibcon#flushed, iclass 25, count 0 2006.257.15:35:43.22#ibcon#about to write, iclass 25, count 0 2006.257.15:35:43.22#ibcon#wrote, iclass 25, count 0 2006.257.15:35:43.22#ibcon#about to read 3, iclass 25, count 0 2006.257.15:35:43.25#ibcon#read 3, iclass 25, count 0 2006.257.15:35:43.25#ibcon#about to read 4, iclass 25, count 0 2006.257.15:35:43.25#ibcon#read 4, iclass 25, count 0 2006.257.15:35:43.25#ibcon#about to read 5, iclass 25, count 0 2006.257.15:35:43.25#ibcon#read 5, iclass 25, count 0 2006.257.15:35:43.25#ibcon#about to read 6, iclass 25, count 0 2006.257.15:35:43.25#ibcon#read 6, iclass 25, count 0 2006.257.15:35:43.25#ibcon#end of sib2, iclass 25, count 0 2006.257.15:35:43.25#ibcon#*after write, iclass 25, count 0 2006.257.15:35:43.25#ibcon#*before return 0, iclass 25, count 0 2006.257.15:35:43.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:43.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:35:43.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:35:43.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:35:43.25$vck44/vblo=8,744.99 2006.257.15:35:43.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.15:35:43.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.15:35:43.25#ibcon#ireg 17 cls_cnt 0 2006.257.15:35:43.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:43.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:43.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:43.25#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:35:43.25#ibcon#first serial, iclass 27, count 0 2006.257.15:35:43.25#ibcon#enter sib2, iclass 27, count 0 2006.257.15:35:43.25#ibcon#flushed, iclass 27, count 0 2006.257.15:35:43.25#ibcon#about to write, iclass 27, count 0 2006.257.15:35:43.25#ibcon#wrote, iclass 27, count 0 2006.257.15:35:43.25#ibcon#about to read 3, iclass 27, count 0 2006.257.15:35:43.27#ibcon#read 3, iclass 27, count 0 2006.257.15:35:43.27#ibcon#about to read 4, iclass 27, count 0 2006.257.15:35:43.27#ibcon#read 4, iclass 27, count 0 2006.257.15:35:43.27#ibcon#about to read 5, iclass 27, count 0 2006.257.15:35:43.27#ibcon#read 5, iclass 27, count 0 2006.257.15:35:43.27#ibcon#about to read 6, iclass 27, count 0 2006.257.15:35:43.27#ibcon#read 6, iclass 27, count 0 2006.257.15:35:43.27#ibcon#end of sib2, iclass 27, count 0 2006.257.15:35:43.27#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:35:43.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:35:43.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:35:43.27#ibcon#*before write, iclass 27, count 0 2006.257.15:35:43.27#ibcon#enter sib2, iclass 27, count 0 2006.257.15:35:43.27#ibcon#flushed, iclass 27, count 0 2006.257.15:35:43.27#ibcon#about to write, iclass 27, count 0 2006.257.15:35:43.27#ibcon#wrote, iclass 27, count 0 2006.257.15:35:43.27#ibcon#about to read 3, iclass 27, count 0 2006.257.15:35:43.31#ibcon#read 3, iclass 27, count 0 2006.257.15:35:43.31#ibcon#about to read 4, iclass 27, count 0 2006.257.15:35:43.31#ibcon#read 4, iclass 27, count 0 2006.257.15:35:43.31#ibcon#about to read 5, iclass 27, count 0 2006.257.15:35:43.31#ibcon#read 5, iclass 27, count 0 2006.257.15:35:43.31#ibcon#about to read 6, iclass 27, count 0 2006.257.15:35:43.31#ibcon#read 6, iclass 27, count 0 2006.257.15:35:43.31#ibcon#end of sib2, iclass 27, count 0 2006.257.15:35:43.31#ibcon#*after write, iclass 27, count 0 2006.257.15:35:43.31#ibcon#*before return 0, iclass 27, count 0 2006.257.15:35:43.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:43.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:35:43.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:35:43.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:35:43.31$vck44/vb=8,4 2006.257.15:35:43.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.15:35:43.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.15:35:43.31#ibcon#ireg 11 cls_cnt 2 2006.257.15:35:43.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:43.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:43.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:43.37#ibcon#enter wrdev, iclass 29, count 2 2006.257.15:35:43.37#ibcon#first serial, iclass 29, count 2 2006.257.15:35:43.37#ibcon#enter sib2, iclass 29, count 2 2006.257.15:35:43.37#ibcon#flushed, iclass 29, count 2 2006.257.15:35:43.37#ibcon#about to write, iclass 29, count 2 2006.257.15:35:43.37#ibcon#wrote, iclass 29, count 2 2006.257.15:35:43.37#ibcon#about to read 3, iclass 29, count 2 2006.257.15:35:43.39#ibcon#read 3, iclass 29, count 2 2006.257.15:35:43.39#ibcon#about to read 4, iclass 29, count 2 2006.257.15:35:43.39#ibcon#read 4, iclass 29, count 2 2006.257.15:35:43.39#ibcon#about to read 5, iclass 29, count 2 2006.257.15:35:43.39#ibcon#read 5, iclass 29, count 2 2006.257.15:35:43.39#ibcon#about to read 6, iclass 29, count 2 2006.257.15:35:43.39#ibcon#read 6, iclass 29, count 2 2006.257.15:35:43.39#ibcon#end of sib2, iclass 29, count 2 2006.257.15:35:43.39#ibcon#*mode == 0, iclass 29, count 2 2006.257.15:35:43.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.15:35:43.39#ibcon#[27=AT08-04\r\n] 2006.257.15:35:43.39#ibcon#*before write, iclass 29, count 2 2006.257.15:35:43.39#ibcon#enter sib2, iclass 29, count 2 2006.257.15:35:43.39#ibcon#flushed, iclass 29, count 2 2006.257.15:35:43.39#ibcon#about to write, iclass 29, count 2 2006.257.15:35:43.39#ibcon#wrote, iclass 29, count 2 2006.257.15:35:43.39#ibcon#about to read 3, iclass 29, count 2 2006.257.15:35:43.42#ibcon#read 3, iclass 29, count 2 2006.257.15:35:43.42#ibcon#about to read 4, iclass 29, count 2 2006.257.15:35:43.42#ibcon#read 4, iclass 29, count 2 2006.257.15:35:43.42#ibcon#about to read 5, iclass 29, count 2 2006.257.15:35:43.42#ibcon#read 5, iclass 29, count 2 2006.257.15:35:43.42#ibcon#about to read 6, iclass 29, count 2 2006.257.15:35:43.42#ibcon#read 6, iclass 29, count 2 2006.257.15:35:43.42#ibcon#end of sib2, iclass 29, count 2 2006.257.15:35:43.42#ibcon#*after write, iclass 29, count 2 2006.257.15:35:43.42#ibcon#*before return 0, iclass 29, count 2 2006.257.15:35:43.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:43.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:35:43.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.15:35:43.42#ibcon#ireg 7 cls_cnt 0 2006.257.15:35:43.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:43.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:43.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:43.54#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:35:43.54#ibcon#first serial, iclass 29, count 0 2006.257.15:35:43.54#ibcon#enter sib2, iclass 29, count 0 2006.257.15:35:43.54#ibcon#flushed, iclass 29, count 0 2006.257.15:35:43.54#ibcon#about to write, iclass 29, count 0 2006.257.15:35:43.54#ibcon#wrote, iclass 29, count 0 2006.257.15:35:43.54#ibcon#about to read 3, iclass 29, count 0 2006.257.15:35:43.56#ibcon#read 3, iclass 29, count 0 2006.257.15:35:43.56#ibcon#about to read 4, iclass 29, count 0 2006.257.15:35:43.56#ibcon#read 4, iclass 29, count 0 2006.257.15:35:43.56#ibcon#about to read 5, iclass 29, count 0 2006.257.15:35:43.56#ibcon#read 5, iclass 29, count 0 2006.257.15:35:43.56#ibcon#about to read 6, iclass 29, count 0 2006.257.15:35:43.56#ibcon#read 6, iclass 29, count 0 2006.257.15:35:43.56#ibcon#end of sib2, iclass 29, count 0 2006.257.15:35:43.56#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:35:43.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:35:43.56#ibcon#[27=USB\r\n] 2006.257.15:35:43.56#ibcon#*before write, iclass 29, count 0 2006.257.15:35:43.56#ibcon#enter sib2, iclass 29, count 0 2006.257.15:35:43.56#ibcon#flushed, iclass 29, count 0 2006.257.15:35:43.56#ibcon#about to write, iclass 29, count 0 2006.257.15:35:43.56#ibcon#wrote, iclass 29, count 0 2006.257.15:35:43.56#ibcon#about to read 3, iclass 29, count 0 2006.257.15:35:43.59#ibcon#read 3, iclass 29, count 0 2006.257.15:35:43.59#ibcon#about to read 4, iclass 29, count 0 2006.257.15:35:43.59#ibcon#read 4, iclass 29, count 0 2006.257.15:35:43.59#ibcon#about to read 5, iclass 29, count 0 2006.257.15:35:43.59#ibcon#read 5, iclass 29, count 0 2006.257.15:35:43.59#ibcon#about to read 6, iclass 29, count 0 2006.257.15:35:43.59#ibcon#read 6, iclass 29, count 0 2006.257.15:35:43.59#ibcon#end of sib2, iclass 29, count 0 2006.257.15:35:43.59#ibcon#*after write, iclass 29, count 0 2006.257.15:35:43.59#ibcon#*before return 0, iclass 29, count 0 2006.257.15:35:43.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:43.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:35:43.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:35:43.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:35:43.59$vck44/vabw=wide 2006.257.15:35:43.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.15:35:43.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.15:35:43.59#ibcon#ireg 8 cls_cnt 0 2006.257.15:35:43.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:43.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:43.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:43.59#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:35:43.59#ibcon#first serial, iclass 31, count 0 2006.257.15:35:43.59#ibcon#enter sib2, iclass 31, count 0 2006.257.15:35:43.59#ibcon#flushed, iclass 31, count 0 2006.257.15:35:43.59#ibcon#about to write, iclass 31, count 0 2006.257.15:35:43.59#ibcon#wrote, iclass 31, count 0 2006.257.15:35:43.59#ibcon#about to read 3, iclass 31, count 0 2006.257.15:35:43.61#ibcon#read 3, iclass 31, count 0 2006.257.15:35:43.61#ibcon#about to read 4, iclass 31, count 0 2006.257.15:35:43.61#ibcon#read 4, iclass 31, count 0 2006.257.15:35:43.61#ibcon#about to read 5, iclass 31, count 0 2006.257.15:35:43.61#ibcon#read 5, iclass 31, count 0 2006.257.15:35:43.61#ibcon#about to read 6, iclass 31, count 0 2006.257.15:35:43.61#ibcon#read 6, iclass 31, count 0 2006.257.15:35:43.61#ibcon#end of sib2, iclass 31, count 0 2006.257.15:35:43.61#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:35:43.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:35:43.61#ibcon#[25=BW32\r\n] 2006.257.15:35:43.61#ibcon#*before write, iclass 31, count 0 2006.257.15:35:43.61#ibcon#enter sib2, iclass 31, count 0 2006.257.15:35:43.61#ibcon#flushed, iclass 31, count 0 2006.257.15:35:43.61#ibcon#about to write, iclass 31, count 0 2006.257.15:35:43.61#ibcon#wrote, iclass 31, count 0 2006.257.15:35:43.61#ibcon#about to read 3, iclass 31, count 0 2006.257.15:35:43.64#ibcon#read 3, iclass 31, count 0 2006.257.15:35:43.64#ibcon#about to read 4, iclass 31, count 0 2006.257.15:35:43.64#ibcon#read 4, iclass 31, count 0 2006.257.15:35:43.64#ibcon#about to read 5, iclass 31, count 0 2006.257.15:35:43.64#ibcon#read 5, iclass 31, count 0 2006.257.15:35:43.64#ibcon#about to read 6, iclass 31, count 0 2006.257.15:35:43.64#ibcon#read 6, iclass 31, count 0 2006.257.15:35:43.64#ibcon#end of sib2, iclass 31, count 0 2006.257.15:35:43.64#ibcon#*after write, iclass 31, count 0 2006.257.15:35:43.64#ibcon#*before return 0, iclass 31, count 0 2006.257.15:35:43.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:43.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:35:43.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:35:43.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:35:43.64$vck44/vbbw=wide 2006.257.15:35:43.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.15:35:43.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.15:35:43.64#ibcon#ireg 8 cls_cnt 0 2006.257.15:35:43.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:35:43.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:35:43.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:35:43.71#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:35:43.71#ibcon#first serial, iclass 33, count 0 2006.257.15:35:43.71#ibcon#enter sib2, iclass 33, count 0 2006.257.15:35:43.71#ibcon#flushed, iclass 33, count 0 2006.257.15:35:43.71#ibcon#about to write, iclass 33, count 0 2006.257.15:35:43.71#ibcon#wrote, iclass 33, count 0 2006.257.15:35:43.71#ibcon#about to read 3, iclass 33, count 0 2006.257.15:35:43.73#ibcon#read 3, iclass 33, count 0 2006.257.15:35:43.73#ibcon#about to read 4, iclass 33, count 0 2006.257.15:35:43.73#ibcon#read 4, iclass 33, count 0 2006.257.15:35:43.73#ibcon#about to read 5, iclass 33, count 0 2006.257.15:35:43.73#ibcon#read 5, iclass 33, count 0 2006.257.15:35:43.73#ibcon#about to read 6, iclass 33, count 0 2006.257.15:35:43.73#ibcon#read 6, iclass 33, count 0 2006.257.15:35:43.73#ibcon#end of sib2, iclass 33, count 0 2006.257.15:35:43.73#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:35:43.73#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:35:43.73#ibcon#[27=BW32\r\n] 2006.257.15:35:43.73#ibcon#*before write, iclass 33, count 0 2006.257.15:35:43.73#ibcon#enter sib2, iclass 33, count 0 2006.257.15:35:43.73#ibcon#flushed, iclass 33, count 0 2006.257.15:35:43.73#ibcon#about to write, iclass 33, count 0 2006.257.15:35:43.73#ibcon#wrote, iclass 33, count 0 2006.257.15:35:43.73#ibcon#about to read 3, iclass 33, count 0 2006.257.15:35:43.76#ibcon#read 3, iclass 33, count 0 2006.257.15:35:43.76#ibcon#about to read 4, iclass 33, count 0 2006.257.15:35:43.76#ibcon#read 4, iclass 33, count 0 2006.257.15:35:43.76#ibcon#about to read 5, iclass 33, count 0 2006.257.15:35:43.76#ibcon#read 5, iclass 33, count 0 2006.257.15:35:43.76#ibcon#about to read 6, iclass 33, count 0 2006.257.15:35:43.76#ibcon#read 6, iclass 33, count 0 2006.257.15:35:43.76#ibcon#end of sib2, iclass 33, count 0 2006.257.15:35:43.76#ibcon#*after write, iclass 33, count 0 2006.257.15:35:43.76#ibcon#*before return 0, iclass 33, count 0 2006.257.15:35:43.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:35:43.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:35:43.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:35:43.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:35:43.76$setupk4/ifdk4 2006.257.15:35:43.76$ifdk4/lo= 2006.257.15:35:43.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:35:43.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:35:43.76$ifdk4/patch= 2006.257.15:35:43.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:35:43.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:35:43.76$setupk4/!*+20s 2006.257.15:35:49.51#abcon#<5=/14 1.2 3.1 17.43 971013.9\r\n> 2006.257.15:35:49.53#abcon#{5=INTERFACE CLEAR} 2006.257.15:35:49.59#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:35:53.14#trakl#Source acquired 2006.257.15:35:55.14#flagr#flagr/antenna,acquired 2006.257.15:35:58.24$setupk4/"tpicd 2006.257.15:35:58.24$setupk4/echo=off 2006.257.15:35:58.24$setupk4/xlog=off 2006.257.15:35:58.24:!2006.257.15:39:44 2006.257.15:39:44.02:preob 2006.257.15:39:45.15/onsource/TRACKING 2006.257.15:39:45.15:!2006.257.15:39:54 2006.257.15:39:54.02:"tape 2006.257.15:39:54.02:"st=record 2006.257.15:39:54.02:data_valid=on 2006.257.15:39:54.02:midob 2006.257.15:39:55.15/onsource/TRACKING 2006.257.15:39:55.15/wx/17.41,1013.9,97 2006.257.15:39:55.35/cable/+6.4848E-03 2006.257.15:39:56.44/va/01,08,usb,yes,31,33 2006.257.15:39:56.44/va/02,07,usb,yes,33,34 2006.257.15:39:56.44/va/03,08,usb,yes,30,32 2006.257.15:39:56.44/va/04,07,usb,yes,34,36 2006.257.15:39:56.44/va/05,04,usb,yes,31,31 2006.257.15:39:56.44/va/06,04,usb,yes,34,34 2006.257.15:39:56.44/va/07,04,usb,yes,35,36 2006.257.15:39:56.44/va/08,04,usb,yes,29,36 2006.257.15:39:56.67/valo/01,524.99,yes,locked 2006.257.15:39:56.67/valo/02,534.99,yes,locked 2006.257.15:39:56.67/valo/03,564.99,yes,locked 2006.257.15:39:56.67/valo/04,624.99,yes,locked 2006.257.15:39:56.67/valo/05,734.99,yes,locked 2006.257.15:39:56.67/valo/06,814.99,yes,locked 2006.257.15:39:56.67/valo/07,864.99,yes,locked 2006.257.15:39:56.67/valo/08,884.99,yes,locked 2006.257.15:39:57.76/vb/01,04,usb,yes,31,28 2006.257.15:39:57.76/vb/02,05,usb,yes,29,29 2006.257.15:39:57.76/vb/03,04,usb,yes,30,33 2006.257.15:39:57.76/vb/04,05,usb,yes,30,29 2006.257.15:39:57.76/vb/05,04,usb,yes,27,29 2006.257.15:39:57.76/vb/06,04,usb,yes,31,27 2006.257.15:39:57.76/vb/07,04,usb,yes,31,31 2006.257.15:39:57.76/vb/08,04,usb,yes,28,32 2006.257.15:39:58.00/vblo/01,629.99,yes,locked 2006.257.15:39:58.00/vblo/02,634.99,yes,locked 2006.257.15:39:58.00/vblo/03,649.99,yes,locked 2006.257.15:39:58.00/vblo/04,679.99,yes,locked 2006.257.15:39:58.00/vblo/05,709.99,yes,locked 2006.257.15:39:58.00/vblo/06,719.99,yes,locked 2006.257.15:39:58.00/vblo/07,734.99,yes,locked 2006.257.15:39:58.00/vblo/08,744.99,yes,locked 2006.257.15:39:58.15/vabw/8 2006.257.15:39:58.30/vbbw/8 2006.257.15:39:58.39/xfe/off,on,15.0 2006.257.15:39:58.76/ifatt/23,28,28,28 2006.257.15:39:59.07/fmout-gps/S +4.56E-07 2006.257.15:39:59.12:!2006.257.15:42:44 2006.257.15:42:44.01:data_valid=off 2006.257.15:42:44.02:"et 2006.257.15:42:44.02:!+3s 2006.257.15:42:47.03:"tape 2006.257.15:42:47.03:postob 2006.257.15:42:47.19/cable/+6.4837E-03 2006.257.15:42:47.19/wx/17.39,1013.9,97 2006.257.15:42:47.25/fmout-gps/S +4.57E-07 2006.257.15:42:47.25:scan_name=257-1545,jd0609,160 2006.257.15:42:47.26:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.257.15:42:49.14#flagr#flagr/antenna,new-source 2006.257.15:42:49.15:checkk5 2006.257.15:42:49.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:42:49.89/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:42:50.32/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:42:50.71/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:42:51.10/chk_obsdata//k5ts1/T2571539??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.257.15:42:51.50/chk_obsdata//k5ts2/T2571539??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.257.15:42:51.90/chk_obsdata//k5ts3/T2571539??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.257.15:42:52.32/chk_obsdata//k5ts4/T2571539??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.257.15:42:53.03/k5log//k5ts1_log_newline 2006.257.15:42:53.74/k5log//k5ts2_log_newline 2006.257.15:42:54.45/k5log//k5ts3_log_newline 2006.257.15:42:55.15/k5log//k5ts4_log_newline 2006.257.15:42:55.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:42:55.17:setupk4=1 2006.257.15:42:55.18$setupk4/echo=on 2006.257.15:42:55.18$setupk4/pcalon 2006.257.15:42:55.18$pcalon/"no phase cal control is implemented here 2006.257.15:42:55.18$setupk4/"tpicd=stop 2006.257.15:42:55.18$setupk4/"rec=synch_on 2006.257.15:42:55.18$setupk4/"rec_mode=128 2006.257.15:42:55.18$setupk4/!* 2006.257.15:42:55.18$setupk4/recpk4 2006.257.15:42:55.18$recpk4/recpatch= 2006.257.15:42:55.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:42:55.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:42:55.18$setupk4/vck44 2006.257.15:42:55.18$vck44/valo=1,524.99 2006.257.15:42:55.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.15:42:55.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.15:42:55.18#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:55.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:55.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:55.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:55.18#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:42:55.18#ibcon#first serial, iclass 26, count 0 2006.257.15:42:55.18#ibcon#enter sib2, iclass 26, count 0 2006.257.15:42:55.18#ibcon#flushed, iclass 26, count 0 2006.257.15:42:55.18#ibcon#about to write, iclass 26, count 0 2006.257.15:42:55.18#ibcon#wrote, iclass 26, count 0 2006.257.15:42:55.18#ibcon#about to read 3, iclass 26, count 0 2006.257.15:42:55.19#ibcon#read 3, iclass 26, count 0 2006.257.15:42:55.19#ibcon#about to read 4, iclass 26, count 0 2006.257.15:42:55.19#ibcon#read 4, iclass 26, count 0 2006.257.15:42:55.19#ibcon#about to read 5, iclass 26, count 0 2006.257.15:42:55.19#ibcon#read 5, iclass 26, count 0 2006.257.15:42:55.19#ibcon#about to read 6, iclass 26, count 0 2006.257.15:42:55.19#ibcon#read 6, iclass 26, count 0 2006.257.15:42:55.19#ibcon#end of sib2, iclass 26, count 0 2006.257.15:42:55.19#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:42:55.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:42:55.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:42:55.19#ibcon#*before write, iclass 26, count 0 2006.257.15:42:55.19#ibcon#enter sib2, iclass 26, count 0 2006.257.15:42:55.19#ibcon#flushed, iclass 26, count 0 2006.257.15:42:55.19#ibcon#about to write, iclass 26, count 0 2006.257.15:42:55.19#ibcon#wrote, iclass 26, count 0 2006.257.15:42:55.19#ibcon#about to read 3, iclass 26, count 0 2006.257.15:42:55.24#ibcon#read 3, iclass 26, count 0 2006.257.15:42:55.24#ibcon#about to read 4, iclass 26, count 0 2006.257.15:42:55.24#ibcon#read 4, iclass 26, count 0 2006.257.15:42:55.24#ibcon#about to read 5, iclass 26, count 0 2006.257.15:42:55.24#ibcon#read 5, iclass 26, count 0 2006.257.15:42:55.24#ibcon#about to read 6, iclass 26, count 0 2006.257.15:42:55.24#ibcon#read 6, iclass 26, count 0 2006.257.15:42:55.24#ibcon#end of sib2, iclass 26, count 0 2006.257.15:42:55.24#ibcon#*after write, iclass 26, count 0 2006.257.15:42:55.24#ibcon#*before return 0, iclass 26, count 0 2006.257.15:42:55.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:55.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:55.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:42:55.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:42:55.24$vck44/va=1,8 2006.257.15:42:55.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.15:42:55.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.15:42:55.24#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:55.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:55.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:55.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:55.24#ibcon#enter wrdev, iclass 28, count 2 2006.257.15:42:55.24#ibcon#first serial, iclass 28, count 2 2006.257.15:42:55.24#ibcon#enter sib2, iclass 28, count 2 2006.257.15:42:55.24#ibcon#flushed, iclass 28, count 2 2006.257.15:42:55.24#ibcon#about to write, iclass 28, count 2 2006.257.15:42:55.24#ibcon#wrote, iclass 28, count 2 2006.257.15:42:55.24#ibcon#about to read 3, iclass 28, count 2 2006.257.15:42:55.26#ibcon#read 3, iclass 28, count 2 2006.257.15:42:55.26#ibcon#about to read 4, iclass 28, count 2 2006.257.15:42:55.26#ibcon#read 4, iclass 28, count 2 2006.257.15:42:55.26#ibcon#about to read 5, iclass 28, count 2 2006.257.15:42:55.26#ibcon#read 5, iclass 28, count 2 2006.257.15:42:55.26#ibcon#about to read 6, iclass 28, count 2 2006.257.15:42:55.26#ibcon#read 6, iclass 28, count 2 2006.257.15:42:55.26#ibcon#end of sib2, iclass 28, count 2 2006.257.15:42:55.26#ibcon#*mode == 0, iclass 28, count 2 2006.257.15:42:55.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.15:42:55.26#ibcon#[25=AT01-08\r\n] 2006.257.15:42:55.26#ibcon#*before write, iclass 28, count 2 2006.257.15:42:55.26#ibcon#enter sib2, iclass 28, count 2 2006.257.15:42:55.26#ibcon#flushed, iclass 28, count 2 2006.257.15:42:55.26#ibcon#about to write, iclass 28, count 2 2006.257.15:42:55.26#ibcon#wrote, iclass 28, count 2 2006.257.15:42:55.26#ibcon#about to read 3, iclass 28, count 2 2006.257.15:42:55.29#ibcon#read 3, iclass 28, count 2 2006.257.15:42:55.29#ibcon#about to read 4, iclass 28, count 2 2006.257.15:42:55.29#ibcon#read 4, iclass 28, count 2 2006.257.15:42:55.29#ibcon#about to read 5, iclass 28, count 2 2006.257.15:42:55.29#ibcon#read 5, iclass 28, count 2 2006.257.15:42:55.29#ibcon#about to read 6, iclass 28, count 2 2006.257.15:42:55.29#ibcon#read 6, iclass 28, count 2 2006.257.15:42:55.29#ibcon#end of sib2, iclass 28, count 2 2006.257.15:42:55.29#ibcon#*after write, iclass 28, count 2 2006.257.15:42:55.29#ibcon#*before return 0, iclass 28, count 2 2006.257.15:42:55.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:55.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:55.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.15:42:55.29#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:55.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:55.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:55.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:55.41#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:42:55.41#ibcon#first serial, iclass 28, count 0 2006.257.15:42:55.41#ibcon#enter sib2, iclass 28, count 0 2006.257.15:42:55.41#ibcon#flushed, iclass 28, count 0 2006.257.15:42:55.41#ibcon#about to write, iclass 28, count 0 2006.257.15:42:55.41#ibcon#wrote, iclass 28, count 0 2006.257.15:42:55.41#ibcon#about to read 3, iclass 28, count 0 2006.257.15:42:55.43#ibcon#read 3, iclass 28, count 0 2006.257.15:42:55.43#ibcon#about to read 4, iclass 28, count 0 2006.257.15:42:55.43#ibcon#read 4, iclass 28, count 0 2006.257.15:42:55.43#ibcon#about to read 5, iclass 28, count 0 2006.257.15:42:55.43#ibcon#read 5, iclass 28, count 0 2006.257.15:42:55.43#ibcon#about to read 6, iclass 28, count 0 2006.257.15:42:55.43#ibcon#read 6, iclass 28, count 0 2006.257.15:42:55.43#ibcon#end of sib2, iclass 28, count 0 2006.257.15:42:55.43#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:42:55.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:42:55.43#ibcon#[25=USB\r\n] 2006.257.15:42:55.43#ibcon#*before write, iclass 28, count 0 2006.257.15:42:55.43#ibcon#enter sib2, iclass 28, count 0 2006.257.15:42:55.43#ibcon#flushed, iclass 28, count 0 2006.257.15:42:55.43#ibcon#about to write, iclass 28, count 0 2006.257.15:42:55.43#ibcon#wrote, iclass 28, count 0 2006.257.15:42:55.43#ibcon#about to read 3, iclass 28, count 0 2006.257.15:42:55.46#ibcon#read 3, iclass 28, count 0 2006.257.15:42:55.46#ibcon#about to read 4, iclass 28, count 0 2006.257.15:42:55.46#ibcon#read 4, iclass 28, count 0 2006.257.15:42:55.46#ibcon#about to read 5, iclass 28, count 0 2006.257.15:42:55.46#ibcon#read 5, iclass 28, count 0 2006.257.15:42:55.46#ibcon#about to read 6, iclass 28, count 0 2006.257.15:42:55.46#ibcon#read 6, iclass 28, count 0 2006.257.15:42:55.46#ibcon#end of sib2, iclass 28, count 0 2006.257.15:42:55.46#ibcon#*after write, iclass 28, count 0 2006.257.15:42:55.46#ibcon#*before return 0, iclass 28, count 0 2006.257.15:42:55.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:55.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:55.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:42:55.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:42:55.46$vck44/valo=2,534.99 2006.257.15:42:55.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.15:42:55.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.15:42:55.46#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:55.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:55.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:55.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:55.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:42:55.46#ibcon#first serial, iclass 30, count 0 2006.257.15:42:55.46#ibcon#enter sib2, iclass 30, count 0 2006.257.15:42:55.46#ibcon#flushed, iclass 30, count 0 2006.257.15:42:55.46#ibcon#about to write, iclass 30, count 0 2006.257.15:42:55.46#ibcon#wrote, iclass 30, count 0 2006.257.15:42:55.46#ibcon#about to read 3, iclass 30, count 0 2006.257.15:42:55.48#ibcon#read 3, iclass 30, count 0 2006.257.15:42:55.48#ibcon#about to read 4, iclass 30, count 0 2006.257.15:42:55.48#ibcon#read 4, iclass 30, count 0 2006.257.15:42:55.48#ibcon#about to read 5, iclass 30, count 0 2006.257.15:42:55.48#ibcon#read 5, iclass 30, count 0 2006.257.15:42:55.48#ibcon#about to read 6, iclass 30, count 0 2006.257.15:42:55.48#ibcon#read 6, iclass 30, count 0 2006.257.15:42:55.48#ibcon#end of sib2, iclass 30, count 0 2006.257.15:42:55.48#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:42:55.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:42:55.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:42:55.48#ibcon#*before write, iclass 30, count 0 2006.257.15:42:55.48#ibcon#enter sib2, iclass 30, count 0 2006.257.15:42:55.48#ibcon#flushed, iclass 30, count 0 2006.257.15:42:55.48#ibcon#about to write, iclass 30, count 0 2006.257.15:42:55.48#ibcon#wrote, iclass 30, count 0 2006.257.15:42:55.48#ibcon#about to read 3, iclass 30, count 0 2006.257.15:42:55.52#ibcon#read 3, iclass 30, count 0 2006.257.15:42:55.52#ibcon#about to read 4, iclass 30, count 0 2006.257.15:42:55.52#ibcon#read 4, iclass 30, count 0 2006.257.15:42:55.52#ibcon#about to read 5, iclass 30, count 0 2006.257.15:42:55.52#ibcon#read 5, iclass 30, count 0 2006.257.15:42:55.52#ibcon#about to read 6, iclass 30, count 0 2006.257.15:42:55.52#ibcon#read 6, iclass 30, count 0 2006.257.15:42:55.52#ibcon#end of sib2, iclass 30, count 0 2006.257.15:42:55.52#ibcon#*after write, iclass 30, count 0 2006.257.15:42:55.52#ibcon#*before return 0, iclass 30, count 0 2006.257.15:42:55.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:55.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:55.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:42:55.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:42:55.52$vck44/va=2,7 2006.257.15:42:55.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.15:42:55.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.15:42:55.52#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:55.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:55.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:55.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:55.58#ibcon#enter wrdev, iclass 32, count 2 2006.257.15:42:55.58#ibcon#first serial, iclass 32, count 2 2006.257.15:42:55.58#ibcon#enter sib2, iclass 32, count 2 2006.257.15:42:55.58#ibcon#flushed, iclass 32, count 2 2006.257.15:42:55.58#ibcon#about to write, iclass 32, count 2 2006.257.15:42:55.58#ibcon#wrote, iclass 32, count 2 2006.257.15:42:55.58#ibcon#about to read 3, iclass 32, count 2 2006.257.15:42:55.60#ibcon#read 3, iclass 32, count 2 2006.257.15:42:55.60#ibcon#about to read 4, iclass 32, count 2 2006.257.15:42:55.60#ibcon#read 4, iclass 32, count 2 2006.257.15:42:55.60#ibcon#about to read 5, iclass 32, count 2 2006.257.15:42:55.60#ibcon#read 5, iclass 32, count 2 2006.257.15:42:55.60#ibcon#about to read 6, iclass 32, count 2 2006.257.15:42:55.60#ibcon#read 6, iclass 32, count 2 2006.257.15:42:55.60#ibcon#end of sib2, iclass 32, count 2 2006.257.15:42:55.60#ibcon#*mode == 0, iclass 32, count 2 2006.257.15:42:55.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.15:42:55.60#ibcon#[25=AT02-07\r\n] 2006.257.15:42:55.60#ibcon#*before write, iclass 32, count 2 2006.257.15:42:55.60#ibcon#enter sib2, iclass 32, count 2 2006.257.15:42:55.60#ibcon#flushed, iclass 32, count 2 2006.257.15:42:55.60#ibcon#about to write, iclass 32, count 2 2006.257.15:42:55.60#ibcon#wrote, iclass 32, count 2 2006.257.15:42:55.60#ibcon#about to read 3, iclass 32, count 2 2006.257.15:42:55.63#ibcon#read 3, iclass 32, count 2 2006.257.15:42:55.63#ibcon#about to read 4, iclass 32, count 2 2006.257.15:42:55.63#ibcon#read 4, iclass 32, count 2 2006.257.15:42:55.63#ibcon#about to read 5, iclass 32, count 2 2006.257.15:42:55.63#ibcon#read 5, iclass 32, count 2 2006.257.15:42:55.63#ibcon#about to read 6, iclass 32, count 2 2006.257.15:42:55.63#ibcon#read 6, iclass 32, count 2 2006.257.15:42:55.63#ibcon#end of sib2, iclass 32, count 2 2006.257.15:42:55.63#ibcon#*after write, iclass 32, count 2 2006.257.15:42:55.63#ibcon#*before return 0, iclass 32, count 2 2006.257.15:42:55.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:55.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:55.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.15:42:55.63#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:55.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:55.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:55.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:55.75#ibcon#enter wrdev, iclass 32, count 0 2006.257.15:42:55.75#ibcon#first serial, iclass 32, count 0 2006.257.15:42:55.75#ibcon#enter sib2, iclass 32, count 0 2006.257.15:42:55.75#ibcon#flushed, iclass 32, count 0 2006.257.15:42:55.75#ibcon#about to write, iclass 32, count 0 2006.257.15:42:55.75#ibcon#wrote, iclass 32, count 0 2006.257.15:42:55.75#ibcon#about to read 3, iclass 32, count 0 2006.257.15:42:55.77#ibcon#read 3, iclass 32, count 0 2006.257.15:42:55.77#ibcon#about to read 4, iclass 32, count 0 2006.257.15:42:55.77#ibcon#read 4, iclass 32, count 0 2006.257.15:42:55.77#ibcon#about to read 5, iclass 32, count 0 2006.257.15:42:55.77#ibcon#read 5, iclass 32, count 0 2006.257.15:42:55.77#ibcon#about to read 6, iclass 32, count 0 2006.257.15:42:55.77#ibcon#read 6, iclass 32, count 0 2006.257.15:42:55.77#ibcon#end of sib2, iclass 32, count 0 2006.257.15:42:55.77#ibcon#*mode == 0, iclass 32, count 0 2006.257.15:42:55.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.15:42:55.77#ibcon#[25=USB\r\n] 2006.257.15:42:55.77#ibcon#*before write, iclass 32, count 0 2006.257.15:42:55.77#ibcon#enter sib2, iclass 32, count 0 2006.257.15:42:55.77#ibcon#flushed, iclass 32, count 0 2006.257.15:42:55.77#ibcon#about to write, iclass 32, count 0 2006.257.15:42:55.77#ibcon#wrote, iclass 32, count 0 2006.257.15:42:55.77#ibcon#about to read 3, iclass 32, count 0 2006.257.15:42:55.80#ibcon#read 3, iclass 32, count 0 2006.257.15:42:55.80#ibcon#about to read 4, iclass 32, count 0 2006.257.15:42:55.80#ibcon#read 4, iclass 32, count 0 2006.257.15:42:55.80#ibcon#about to read 5, iclass 32, count 0 2006.257.15:42:55.80#ibcon#read 5, iclass 32, count 0 2006.257.15:42:55.80#ibcon#about to read 6, iclass 32, count 0 2006.257.15:42:55.80#ibcon#read 6, iclass 32, count 0 2006.257.15:42:55.80#ibcon#end of sib2, iclass 32, count 0 2006.257.15:42:55.80#ibcon#*after write, iclass 32, count 0 2006.257.15:42:55.80#ibcon#*before return 0, iclass 32, count 0 2006.257.15:42:55.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:55.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:55.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.15:42:55.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.15:42:55.80$vck44/valo=3,564.99 2006.257.15:42:55.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.15:42:55.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.15:42:55.80#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:55.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:55.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:55.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:55.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:42:55.80#ibcon#first serial, iclass 34, count 0 2006.257.15:42:55.80#ibcon#enter sib2, iclass 34, count 0 2006.257.15:42:55.80#ibcon#flushed, iclass 34, count 0 2006.257.15:42:55.80#ibcon#about to write, iclass 34, count 0 2006.257.15:42:55.80#ibcon#wrote, iclass 34, count 0 2006.257.15:42:55.80#ibcon#about to read 3, iclass 34, count 0 2006.257.15:42:55.82#ibcon#read 3, iclass 34, count 0 2006.257.15:42:55.82#ibcon#about to read 4, iclass 34, count 0 2006.257.15:42:55.82#ibcon#read 4, iclass 34, count 0 2006.257.15:42:55.82#ibcon#about to read 5, iclass 34, count 0 2006.257.15:42:55.82#ibcon#read 5, iclass 34, count 0 2006.257.15:42:55.82#ibcon#about to read 6, iclass 34, count 0 2006.257.15:42:55.82#ibcon#read 6, iclass 34, count 0 2006.257.15:42:55.82#ibcon#end of sib2, iclass 34, count 0 2006.257.15:42:55.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:42:55.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:42:55.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:42:55.82#ibcon#*before write, iclass 34, count 0 2006.257.15:42:55.82#ibcon#enter sib2, iclass 34, count 0 2006.257.15:42:55.82#ibcon#flushed, iclass 34, count 0 2006.257.15:42:55.82#ibcon#about to write, iclass 34, count 0 2006.257.15:42:55.82#ibcon#wrote, iclass 34, count 0 2006.257.15:42:55.82#ibcon#about to read 3, iclass 34, count 0 2006.257.15:42:55.86#ibcon#read 3, iclass 34, count 0 2006.257.15:42:55.86#ibcon#about to read 4, iclass 34, count 0 2006.257.15:42:55.86#ibcon#read 4, iclass 34, count 0 2006.257.15:42:55.86#ibcon#about to read 5, iclass 34, count 0 2006.257.15:42:55.86#ibcon#read 5, iclass 34, count 0 2006.257.15:42:55.86#ibcon#about to read 6, iclass 34, count 0 2006.257.15:42:55.86#ibcon#read 6, iclass 34, count 0 2006.257.15:42:55.86#ibcon#end of sib2, iclass 34, count 0 2006.257.15:42:55.86#ibcon#*after write, iclass 34, count 0 2006.257.15:42:55.86#ibcon#*before return 0, iclass 34, count 0 2006.257.15:42:55.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:55.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:55.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:42:55.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:42:55.86$vck44/va=3,8 2006.257.15:42:55.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.15:42:55.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.15:42:55.86#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:55.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:55.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:55.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:55.92#ibcon#enter wrdev, iclass 36, count 2 2006.257.15:42:55.92#ibcon#first serial, iclass 36, count 2 2006.257.15:42:55.92#ibcon#enter sib2, iclass 36, count 2 2006.257.15:42:55.92#ibcon#flushed, iclass 36, count 2 2006.257.15:42:55.92#ibcon#about to write, iclass 36, count 2 2006.257.15:42:55.92#ibcon#wrote, iclass 36, count 2 2006.257.15:42:55.92#ibcon#about to read 3, iclass 36, count 2 2006.257.15:42:55.94#ibcon#read 3, iclass 36, count 2 2006.257.15:42:55.94#ibcon#about to read 4, iclass 36, count 2 2006.257.15:42:55.94#ibcon#read 4, iclass 36, count 2 2006.257.15:42:55.94#ibcon#about to read 5, iclass 36, count 2 2006.257.15:42:55.94#ibcon#read 5, iclass 36, count 2 2006.257.15:42:55.94#ibcon#about to read 6, iclass 36, count 2 2006.257.15:42:55.94#ibcon#read 6, iclass 36, count 2 2006.257.15:42:55.94#ibcon#end of sib2, iclass 36, count 2 2006.257.15:42:55.94#ibcon#*mode == 0, iclass 36, count 2 2006.257.15:42:55.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.15:42:55.94#ibcon#[25=AT03-08\r\n] 2006.257.15:42:55.94#ibcon#*before write, iclass 36, count 2 2006.257.15:42:55.94#ibcon#enter sib2, iclass 36, count 2 2006.257.15:42:55.94#ibcon#flushed, iclass 36, count 2 2006.257.15:42:55.94#ibcon#about to write, iclass 36, count 2 2006.257.15:42:55.94#ibcon#wrote, iclass 36, count 2 2006.257.15:42:55.94#ibcon#about to read 3, iclass 36, count 2 2006.257.15:42:55.97#ibcon#read 3, iclass 36, count 2 2006.257.15:42:55.97#ibcon#about to read 4, iclass 36, count 2 2006.257.15:42:55.97#ibcon#read 4, iclass 36, count 2 2006.257.15:42:55.97#ibcon#about to read 5, iclass 36, count 2 2006.257.15:42:55.97#ibcon#read 5, iclass 36, count 2 2006.257.15:42:55.97#ibcon#about to read 6, iclass 36, count 2 2006.257.15:42:55.97#ibcon#read 6, iclass 36, count 2 2006.257.15:42:55.97#ibcon#end of sib2, iclass 36, count 2 2006.257.15:42:55.97#ibcon#*after write, iclass 36, count 2 2006.257.15:42:55.97#ibcon#*before return 0, iclass 36, count 2 2006.257.15:42:55.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:55.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:55.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.15:42:55.97#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:55.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:56.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:56.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:56.09#ibcon#enter wrdev, iclass 36, count 0 2006.257.15:42:56.09#ibcon#first serial, iclass 36, count 0 2006.257.15:42:56.09#ibcon#enter sib2, iclass 36, count 0 2006.257.15:42:56.09#ibcon#flushed, iclass 36, count 0 2006.257.15:42:56.09#ibcon#about to write, iclass 36, count 0 2006.257.15:42:56.09#ibcon#wrote, iclass 36, count 0 2006.257.15:42:56.09#ibcon#about to read 3, iclass 36, count 0 2006.257.15:42:56.11#ibcon#read 3, iclass 36, count 0 2006.257.15:42:56.11#ibcon#about to read 4, iclass 36, count 0 2006.257.15:42:56.11#ibcon#read 4, iclass 36, count 0 2006.257.15:42:56.11#ibcon#about to read 5, iclass 36, count 0 2006.257.15:42:56.11#ibcon#read 5, iclass 36, count 0 2006.257.15:42:56.11#ibcon#about to read 6, iclass 36, count 0 2006.257.15:42:56.11#ibcon#read 6, iclass 36, count 0 2006.257.15:42:56.11#ibcon#end of sib2, iclass 36, count 0 2006.257.15:42:56.11#ibcon#*mode == 0, iclass 36, count 0 2006.257.15:42:56.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.15:42:56.11#ibcon#[25=USB\r\n] 2006.257.15:42:56.11#ibcon#*before write, iclass 36, count 0 2006.257.15:42:56.11#ibcon#enter sib2, iclass 36, count 0 2006.257.15:42:56.11#ibcon#flushed, iclass 36, count 0 2006.257.15:42:56.11#ibcon#about to write, iclass 36, count 0 2006.257.15:42:56.11#ibcon#wrote, iclass 36, count 0 2006.257.15:42:56.11#ibcon#about to read 3, iclass 36, count 0 2006.257.15:42:56.14#ibcon#read 3, iclass 36, count 0 2006.257.15:42:56.14#ibcon#about to read 4, iclass 36, count 0 2006.257.15:42:56.14#ibcon#read 4, iclass 36, count 0 2006.257.15:42:56.14#ibcon#about to read 5, iclass 36, count 0 2006.257.15:42:56.14#ibcon#read 5, iclass 36, count 0 2006.257.15:42:56.14#ibcon#about to read 6, iclass 36, count 0 2006.257.15:42:56.14#ibcon#read 6, iclass 36, count 0 2006.257.15:42:56.14#ibcon#end of sib2, iclass 36, count 0 2006.257.15:42:56.14#ibcon#*after write, iclass 36, count 0 2006.257.15:42:56.14#ibcon#*before return 0, iclass 36, count 0 2006.257.15:42:56.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:56.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:56.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.15:42:56.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.15:42:56.15$vck44/valo=4,624.99 2006.257.15:42:56.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.15:42:56.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.15:42:56.15#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:56.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:56.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:56.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:56.15#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:42:56.15#ibcon#first serial, iclass 38, count 0 2006.257.15:42:56.15#ibcon#enter sib2, iclass 38, count 0 2006.257.15:42:56.15#ibcon#flushed, iclass 38, count 0 2006.257.15:42:56.15#ibcon#about to write, iclass 38, count 0 2006.257.15:42:56.15#ibcon#wrote, iclass 38, count 0 2006.257.15:42:56.15#ibcon#about to read 3, iclass 38, count 0 2006.257.15:42:56.16#ibcon#read 3, iclass 38, count 0 2006.257.15:42:56.16#ibcon#about to read 4, iclass 38, count 0 2006.257.15:42:56.16#ibcon#read 4, iclass 38, count 0 2006.257.15:42:56.16#ibcon#about to read 5, iclass 38, count 0 2006.257.15:42:56.16#ibcon#read 5, iclass 38, count 0 2006.257.15:42:56.16#ibcon#about to read 6, iclass 38, count 0 2006.257.15:42:56.16#ibcon#read 6, iclass 38, count 0 2006.257.15:42:56.16#ibcon#end of sib2, iclass 38, count 0 2006.257.15:42:56.16#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:42:56.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:42:56.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:42:56.16#ibcon#*before write, iclass 38, count 0 2006.257.15:42:56.16#ibcon#enter sib2, iclass 38, count 0 2006.257.15:42:56.16#ibcon#flushed, iclass 38, count 0 2006.257.15:42:56.16#ibcon#about to write, iclass 38, count 0 2006.257.15:42:56.16#ibcon#wrote, iclass 38, count 0 2006.257.15:42:56.16#ibcon#about to read 3, iclass 38, count 0 2006.257.15:42:56.20#ibcon#read 3, iclass 38, count 0 2006.257.15:42:56.20#ibcon#about to read 4, iclass 38, count 0 2006.257.15:42:56.20#ibcon#read 4, iclass 38, count 0 2006.257.15:42:56.20#ibcon#about to read 5, iclass 38, count 0 2006.257.15:42:56.20#ibcon#read 5, iclass 38, count 0 2006.257.15:42:56.20#ibcon#about to read 6, iclass 38, count 0 2006.257.15:42:56.20#ibcon#read 6, iclass 38, count 0 2006.257.15:42:56.20#ibcon#end of sib2, iclass 38, count 0 2006.257.15:42:56.20#ibcon#*after write, iclass 38, count 0 2006.257.15:42:56.20#ibcon#*before return 0, iclass 38, count 0 2006.257.15:42:56.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:56.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:56.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:42:56.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:42:56.20$vck44/va=4,7 2006.257.15:42:56.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.15:42:56.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.15:42:56.20#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:56.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:56.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:56.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:56.26#ibcon#enter wrdev, iclass 40, count 2 2006.257.15:42:56.26#ibcon#first serial, iclass 40, count 2 2006.257.15:42:56.26#ibcon#enter sib2, iclass 40, count 2 2006.257.15:42:56.26#ibcon#flushed, iclass 40, count 2 2006.257.15:42:56.26#ibcon#about to write, iclass 40, count 2 2006.257.15:42:56.26#ibcon#wrote, iclass 40, count 2 2006.257.15:42:56.26#ibcon#about to read 3, iclass 40, count 2 2006.257.15:42:56.28#ibcon#read 3, iclass 40, count 2 2006.257.15:42:56.28#ibcon#about to read 4, iclass 40, count 2 2006.257.15:42:56.28#ibcon#read 4, iclass 40, count 2 2006.257.15:42:56.28#ibcon#about to read 5, iclass 40, count 2 2006.257.15:42:56.28#ibcon#read 5, iclass 40, count 2 2006.257.15:42:56.28#ibcon#about to read 6, iclass 40, count 2 2006.257.15:42:56.28#ibcon#read 6, iclass 40, count 2 2006.257.15:42:56.28#ibcon#end of sib2, iclass 40, count 2 2006.257.15:42:56.28#ibcon#*mode == 0, iclass 40, count 2 2006.257.15:42:56.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.15:42:56.28#ibcon#[25=AT04-07\r\n] 2006.257.15:42:56.28#ibcon#*before write, iclass 40, count 2 2006.257.15:42:56.28#ibcon#enter sib2, iclass 40, count 2 2006.257.15:42:56.28#ibcon#flushed, iclass 40, count 2 2006.257.15:42:56.28#ibcon#about to write, iclass 40, count 2 2006.257.15:42:56.28#ibcon#wrote, iclass 40, count 2 2006.257.15:42:56.28#ibcon#about to read 3, iclass 40, count 2 2006.257.15:42:56.31#ibcon#read 3, iclass 40, count 2 2006.257.15:42:56.31#ibcon#about to read 4, iclass 40, count 2 2006.257.15:42:56.31#ibcon#read 4, iclass 40, count 2 2006.257.15:42:56.31#ibcon#about to read 5, iclass 40, count 2 2006.257.15:42:56.31#ibcon#read 5, iclass 40, count 2 2006.257.15:42:56.31#ibcon#about to read 6, iclass 40, count 2 2006.257.15:42:56.31#ibcon#read 6, iclass 40, count 2 2006.257.15:42:56.31#ibcon#end of sib2, iclass 40, count 2 2006.257.15:42:56.31#ibcon#*after write, iclass 40, count 2 2006.257.15:42:56.31#ibcon#*before return 0, iclass 40, count 2 2006.257.15:42:56.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:56.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:56.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.15:42:56.31#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:56.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:56.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:56.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:56.43#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:42:56.43#ibcon#first serial, iclass 40, count 0 2006.257.15:42:56.43#ibcon#enter sib2, iclass 40, count 0 2006.257.15:42:56.43#ibcon#flushed, iclass 40, count 0 2006.257.15:42:56.43#ibcon#about to write, iclass 40, count 0 2006.257.15:42:56.43#ibcon#wrote, iclass 40, count 0 2006.257.15:42:56.43#ibcon#about to read 3, iclass 40, count 0 2006.257.15:42:56.45#ibcon#read 3, iclass 40, count 0 2006.257.15:42:56.45#ibcon#about to read 4, iclass 40, count 0 2006.257.15:42:56.45#ibcon#read 4, iclass 40, count 0 2006.257.15:42:56.45#ibcon#about to read 5, iclass 40, count 0 2006.257.15:42:56.45#ibcon#read 5, iclass 40, count 0 2006.257.15:42:56.45#ibcon#about to read 6, iclass 40, count 0 2006.257.15:42:56.45#ibcon#read 6, iclass 40, count 0 2006.257.15:42:56.45#ibcon#end of sib2, iclass 40, count 0 2006.257.15:42:56.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:42:56.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:42:56.45#ibcon#[25=USB\r\n] 2006.257.15:42:56.45#ibcon#*before write, iclass 40, count 0 2006.257.15:42:56.45#ibcon#enter sib2, iclass 40, count 0 2006.257.15:42:56.45#ibcon#flushed, iclass 40, count 0 2006.257.15:42:56.45#ibcon#about to write, iclass 40, count 0 2006.257.15:42:56.45#ibcon#wrote, iclass 40, count 0 2006.257.15:42:56.45#ibcon#about to read 3, iclass 40, count 0 2006.257.15:42:56.48#ibcon#read 3, iclass 40, count 0 2006.257.15:42:56.48#ibcon#about to read 4, iclass 40, count 0 2006.257.15:42:56.48#ibcon#read 4, iclass 40, count 0 2006.257.15:42:56.48#ibcon#about to read 5, iclass 40, count 0 2006.257.15:42:56.48#ibcon#read 5, iclass 40, count 0 2006.257.15:42:56.48#ibcon#about to read 6, iclass 40, count 0 2006.257.15:42:56.48#ibcon#read 6, iclass 40, count 0 2006.257.15:42:56.48#ibcon#end of sib2, iclass 40, count 0 2006.257.15:42:56.48#ibcon#*after write, iclass 40, count 0 2006.257.15:42:56.48#ibcon#*before return 0, iclass 40, count 0 2006.257.15:42:56.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:56.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:56.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:42:56.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:42:56.48$vck44/valo=5,734.99 2006.257.15:42:56.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.15:42:56.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.15:42:56.48#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:56.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:56.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:56.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:56.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:42:56.48#ibcon#first serial, iclass 4, count 0 2006.257.15:42:56.48#ibcon#enter sib2, iclass 4, count 0 2006.257.15:42:56.48#ibcon#flushed, iclass 4, count 0 2006.257.15:42:56.48#ibcon#about to write, iclass 4, count 0 2006.257.15:42:56.48#ibcon#wrote, iclass 4, count 0 2006.257.15:42:56.48#ibcon#about to read 3, iclass 4, count 0 2006.257.15:42:56.50#ibcon#read 3, iclass 4, count 0 2006.257.15:42:56.50#ibcon#about to read 4, iclass 4, count 0 2006.257.15:42:56.50#ibcon#read 4, iclass 4, count 0 2006.257.15:42:56.50#ibcon#about to read 5, iclass 4, count 0 2006.257.15:42:56.50#ibcon#read 5, iclass 4, count 0 2006.257.15:42:56.50#ibcon#about to read 6, iclass 4, count 0 2006.257.15:42:56.50#ibcon#read 6, iclass 4, count 0 2006.257.15:42:56.50#ibcon#end of sib2, iclass 4, count 0 2006.257.15:42:56.50#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:42:56.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:42:56.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:42:56.50#ibcon#*before write, iclass 4, count 0 2006.257.15:42:56.50#ibcon#enter sib2, iclass 4, count 0 2006.257.15:42:56.50#ibcon#flushed, iclass 4, count 0 2006.257.15:42:56.50#ibcon#about to write, iclass 4, count 0 2006.257.15:42:56.50#ibcon#wrote, iclass 4, count 0 2006.257.15:42:56.50#ibcon#about to read 3, iclass 4, count 0 2006.257.15:42:56.54#ibcon#read 3, iclass 4, count 0 2006.257.15:42:56.54#ibcon#about to read 4, iclass 4, count 0 2006.257.15:42:56.54#ibcon#read 4, iclass 4, count 0 2006.257.15:42:56.54#ibcon#about to read 5, iclass 4, count 0 2006.257.15:42:56.54#ibcon#read 5, iclass 4, count 0 2006.257.15:42:56.54#ibcon#about to read 6, iclass 4, count 0 2006.257.15:42:56.54#ibcon#read 6, iclass 4, count 0 2006.257.15:42:56.54#ibcon#end of sib2, iclass 4, count 0 2006.257.15:42:56.54#ibcon#*after write, iclass 4, count 0 2006.257.15:42:56.54#ibcon#*before return 0, iclass 4, count 0 2006.257.15:42:56.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:56.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:56.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:42:56.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:42:56.54$vck44/va=5,4 2006.257.15:42:56.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.15:42:56.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.15:42:56.54#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:56.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:56.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:56.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:56.60#ibcon#enter wrdev, iclass 6, count 2 2006.257.15:42:56.60#ibcon#first serial, iclass 6, count 2 2006.257.15:42:56.60#ibcon#enter sib2, iclass 6, count 2 2006.257.15:42:56.60#ibcon#flushed, iclass 6, count 2 2006.257.15:42:56.60#ibcon#about to write, iclass 6, count 2 2006.257.15:42:56.60#ibcon#wrote, iclass 6, count 2 2006.257.15:42:56.60#ibcon#about to read 3, iclass 6, count 2 2006.257.15:42:56.62#ibcon#read 3, iclass 6, count 2 2006.257.15:42:56.62#ibcon#about to read 4, iclass 6, count 2 2006.257.15:42:56.62#ibcon#read 4, iclass 6, count 2 2006.257.15:42:56.62#ibcon#about to read 5, iclass 6, count 2 2006.257.15:42:56.62#ibcon#read 5, iclass 6, count 2 2006.257.15:42:56.62#ibcon#about to read 6, iclass 6, count 2 2006.257.15:42:56.62#ibcon#read 6, iclass 6, count 2 2006.257.15:42:56.62#ibcon#end of sib2, iclass 6, count 2 2006.257.15:42:56.62#ibcon#*mode == 0, iclass 6, count 2 2006.257.15:42:56.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.15:42:56.62#ibcon#[25=AT05-04\r\n] 2006.257.15:42:56.62#ibcon#*before write, iclass 6, count 2 2006.257.15:42:56.62#ibcon#enter sib2, iclass 6, count 2 2006.257.15:42:56.62#ibcon#flushed, iclass 6, count 2 2006.257.15:42:56.62#ibcon#about to write, iclass 6, count 2 2006.257.15:42:56.62#ibcon#wrote, iclass 6, count 2 2006.257.15:42:56.62#ibcon#about to read 3, iclass 6, count 2 2006.257.15:42:56.64#abcon#<5=/14 0.9 2.9 17.39 971013.9\r\n> 2006.257.15:42:56.65#ibcon#read 3, iclass 6, count 2 2006.257.15:42:56.65#ibcon#about to read 4, iclass 6, count 2 2006.257.15:42:56.65#ibcon#read 4, iclass 6, count 2 2006.257.15:42:56.65#ibcon#about to read 5, iclass 6, count 2 2006.257.15:42:56.65#ibcon#read 5, iclass 6, count 2 2006.257.15:42:56.65#ibcon#about to read 6, iclass 6, count 2 2006.257.15:42:56.65#ibcon#read 6, iclass 6, count 2 2006.257.15:42:56.65#ibcon#end of sib2, iclass 6, count 2 2006.257.15:42:56.65#ibcon#*after write, iclass 6, count 2 2006.257.15:42:56.65#ibcon#*before return 0, iclass 6, count 2 2006.257.15:42:56.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:56.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:56.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.15:42:56.65#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:56.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:56.66#abcon#{5=INTERFACE CLEAR} 2006.257.15:42:56.72#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:42:56.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:56.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:56.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.15:42:56.77#ibcon#first serial, iclass 6, count 0 2006.257.15:42:56.77#ibcon#enter sib2, iclass 6, count 0 2006.257.15:42:56.77#ibcon#flushed, iclass 6, count 0 2006.257.15:42:56.77#ibcon#about to write, iclass 6, count 0 2006.257.15:42:56.77#ibcon#wrote, iclass 6, count 0 2006.257.15:42:56.77#ibcon#about to read 3, iclass 6, count 0 2006.257.15:42:56.79#ibcon#read 3, iclass 6, count 0 2006.257.15:42:56.79#ibcon#about to read 4, iclass 6, count 0 2006.257.15:42:56.79#ibcon#read 4, iclass 6, count 0 2006.257.15:42:56.79#ibcon#about to read 5, iclass 6, count 0 2006.257.15:42:56.79#ibcon#read 5, iclass 6, count 0 2006.257.15:42:56.79#ibcon#about to read 6, iclass 6, count 0 2006.257.15:42:56.79#ibcon#read 6, iclass 6, count 0 2006.257.15:42:56.79#ibcon#end of sib2, iclass 6, count 0 2006.257.15:42:56.79#ibcon#*mode == 0, iclass 6, count 0 2006.257.15:42:56.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.15:42:56.79#ibcon#[25=USB\r\n] 2006.257.15:42:56.79#ibcon#*before write, iclass 6, count 0 2006.257.15:42:56.79#ibcon#enter sib2, iclass 6, count 0 2006.257.15:42:56.79#ibcon#flushed, iclass 6, count 0 2006.257.15:42:56.79#ibcon#about to write, iclass 6, count 0 2006.257.15:42:56.79#ibcon#wrote, iclass 6, count 0 2006.257.15:42:56.79#ibcon#about to read 3, iclass 6, count 0 2006.257.15:42:56.82#ibcon#read 3, iclass 6, count 0 2006.257.15:42:56.82#ibcon#about to read 4, iclass 6, count 0 2006.257.15:42:56.82#ibcon#read 4, iclass 6, count 0 2006.257.15:42:56.82#ibcon#about to read 5, iclass 6, count 0 2006.257.15:42:56.82#ibcon#read 5, iclass 6, count 0 2006.257.15:42:56.82#ibcon#about to read 6, iclass 6, count 0 2006.257.15:42:56.82#ibcon#read 6, iclass 6, count 0 2006.257.15:42:56.82#ibcon#end of sib2, iclass 6, count 0 2006.257.15:42:56.82#ibcon#*after write, iclass 6, count 0 2006.257.15:42:56.82#ibcon#*before return 0, iclass 6, count 0 2006.257.15:42:56.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:56.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:56.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.15:42:56.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.15:42:56.82$vck44/valo=6,814.99 2006.257.15:42:56.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.15:42:56.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.15:42:56.82#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:56.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:56.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:56.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:56.82#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:42:56.82#ibcon#first serial, iclass 14, count 0 2006.257.15:42:56.82#ibcon#enter sib2, iclass 14, count 0 2006.257.15:42:56.82#ibcon#flushed, iclass 14, count 0 2006.257.15:42:56.82#ibcon#about to write, iclass 14, count 0 2006.257.15:42:56.82#ibcon#wrote, iclass 14, count 0 2006.257.15:42:56.82#ibcon#about to read 3, iclass 14, count 0 2006.257.15:42:56.84#ibcon#read 3, iclass 14, count 0 2006.257.15:42:56.84#ibcon#about to read 4, iclass 14, count 0 2006.257.15:42:56.84#ibcon#read 4, iclass 14, count 0 2006.257.15:42:56.84#ibcon#about to read 5, iclass 14, count 0 2006.257.15:42:56.84#ibcon#read 5, iclass 14, count 0 2006.257.15:42:56.84#ibcon#about to read 6, iclass 14, count 0 2006.257.15:42:56.84#ibcon#read 6, iclass 14, count 0 2006.257.15:42:56.84#ibcon#end of sib2, iclass 14, count 0 2006.257.15:42:56.84#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:42:56.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:42:56.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:42:56.84#ibcon#*before write, iclass 14, count 0 2006.257.15:42:56.84#ibcon#enter sib2, iclass 14, count 0 2006.257.15:42:56.84#ibcon#flushed, iclass 14, count 0 2006.257.15:42:56.84#ibcon#about to write, iclass 14, count 0 2006.257.15:42:56.84#ibcon#wrote, iclass 14, count 0 2006.257.15:42:56.84#ibcon#about to read 3, iclass 14, count 0 2006.257.15:42:56.88#ibcon#read 3, iclass 14, count 0 2006.257.15:42:56.88#ibcon#about to read 4, iclass 14, count 0 2006.257.15:42:56.88#ibcon#read 4, iclass 14, count 0 2006.257.15:42:56.88#ibcon#about to read 5, iclass 14, count 0 2006.257.15:42:56.88#ibcon#read 5, iclass 14, count 0 2006.257.15:42:56.88#ibcon#about to read 6, iclass 14, count 0 2006.257.15:42:56.88#ibcon#read 6, iclass 14, count 0 2006.257.15:42:56.88#ibcon#end of sib2, iclass 14, count 0 2006.257.15:42:56.88#ibcon#*after write, iclass 14, count 0 2006.257.15:42:56.88#ibcon#*before return 0, iclass 14, count 0 2006.257.15:42:56.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:56.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:56.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:42:56.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:42:56.88$vck44/va=6,4 2006.257.15:42:56.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.15:42:56.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.15:42:56.88#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:56.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:42:56.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:42:56.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:42:56.94#ibcon#enter wrdev, iclass 16, count 2 2006.257.15:42:56.94#ibcon#first serial, iclass 16, count 2 2006.257.15:42:56.94#ibcon#enter sib2, iclass 16, count 2 2006.257.15:42:56.94#ibcon#flushed, iclass 16, count 2 2006.257.15:42:56.94#ibcon#about to write, iclass 16, count 2 2006.257.15:42:56.94#ibcon#wrote, iclass 16, count 2 2006.257.15:42:56.94#ibcon#about to read 3, iclass 16, count 2 2006.257.15:42:56.96#ibcon#read 3, iclass 16, count 2 2006.257.15:42:56.96#ibcon#about to read 4, iclass 16, count 2 2006.257.15:42:56.96#ibcon#read 4, iclass 16, count 2 2006.257.15:42:56.96#ibcon#about to read 5, iclass 16, count 2 2006.257.15:42:56.96#ibcon#read 5, iclass 16, count 2 2006.257.15:42:56.96#ibcon#about to read 6, iclass 16, count 2 2006.257.15:42:56.96#ibcon#read 6, iclass 16, count 2 2006.257.15:42:56.96#ibcon#end of sib2, iclass 16, count 2 2006.257.15:42:56.96#ibcon#*mode == 0, iclass 16, count 2 2006.257.15:42:56.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.15:42:56.96#ibcon#[25=AT06-04\r\n] 2006.257.15:42:56.96#ibcon#*before write, iclass 16, count 2 2006.257.15:42:56.96#ibcon#enter sib2, iclass 16, count 2 2006.257.15:42:56.96#ibcon#flushed, iclass 16, count 2 2006.257.15:42:56.96#ibcon#about to write, iclass 16, count 2 2006.257.15:42:56.96#ibcon#wrote, iclass 16, count 2 2006.257.15:42:56.96#ibcon#about to read 3, iclass 16, count 2 2006.257.15:42:56.99#ibcon#read 3, iclass 16, count 2 2006.257.15:42:56.99#ibcon#about to read 4, iclass 16, count 2 2006.257.15:42:56.99#ibcon#read 4, iclass 16, count 2 2006.257.15:42:56.99#ibcon#about to read 5, iclass 16, count 2 2006.257.15:42:56.99#ibcon#read 5, iclass 16, count 2 2006.257.15:42:56.99#ibcon#about to read 6, iclass 16, count 2 2006.257.15:42:56.99#ibcon#read 6, iclass 16, count 2 2006.257.15:42:56.99#ibcon#end of sib2, iclass 16, count 2 2006.257.15:42:56.99#ibcon#*after write, iclass 16, count 2 2006.257.15:42:56.99#ibcon#*before return 0, iclass 16, count 2 2006.257.15:42:56.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:42:56.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:42:56.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.15:42:56.99#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:56.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:42:57.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:42:57.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:42:57.11#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:42:57.11#ibcon#first serial, iclass 16, count 0 2006.257.15:42:57.11#ibcon#enter sib2, iclass 16, count 0 2006.257.15:42:57.11#ibcon#flushed, iclass 16, count 0 2006.257.15:42:57.11#ibcon#about to write, iclass 16, count 0 2006.257.15:42:57.11#ibcon#wrote, iclass 16, count 0 2006.257.15:42:57.11#ibcon#about to read 3, iclass 16, count 0 2006.257.15:42:57.13#ibcon#read 3, iclass 16, count 0 2006.257.15:42:57.13#ibcon#about to read 4, iclass 16, count 0 2006.257.15:42:57.13#ibcon#read 4, iclass 16, count 0 2006.257.15:42:57.13#ibcon#about to read 5, iclass 16, count 0 2006.257.15:42:57.13#ibcon#read 5, iclass 16, count 0 2006.257.15:42:57.13#ibcon#about to read 6, iclass 16, count 0 2006.257.15:42:57.13#ibcon#read 6, iclass 16, count 0 2006.257.15:42:57.13#ibcon#end of sib2, iclass 16, count 0 2006.257.15:42:57.13#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:42:57.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:42:57.13#ibcon#[25=USB\r\n] 2006.257.15:42:57.13#ibcon#*before write, iclass 16, count 0 2006.257.15:42:57.13#ibcon#enter sib2, iclass 16, count 0 2006.257.15:42:57.13#ibcon#flushed, iclass 16, count 0 2006.257.15:42:57.13#ibcon#about to write, iclass 16, count 0 2006.257.15:42:57.13#ibcon#wrote, iclass 16, count 0 2006.257.15:42:57.13#ibcon#about to read 3, iclass 16, count 0 2006.257.15:42:57.16#ibcon#read 3, iclass 16, count 0 2006.257.15:42:57.16#ibcon#about to read 4, iclass 16, count 0 2006.257.15:42:57.16#ibcon#read 4, iclass 16, count 0 2006.257.15:42:57.16#ibcon#about to read 5, iclass 16, count 0 2006.257.15:42:57.16#ibcon#read 5, iclass 16, count 0 2006.257.15:42:57.16#ibcon#about to read 6, iclass 16, count 0 2006.257.15:42:57.16#ibcon#read 6, iclass 16, count 0 2006.257.15:42:57.16#ibcon#end of sib2, iclass 16, count 0 2006.257.15:42:57.16#ibcon#*after write, iclass 16, count 0 2006.257.15:42:57.16#ibcon#*before return 0, iclass 16, count 0 2006.257.15:42:57.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:42:57.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:42:57.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:42:57.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:42:57.16$vck44/valo=7,864.99 2006.257.15:42:57.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.15:42:57.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.15:42:57.16#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:57.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:42:57.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:42:57.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:42:57.16#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:42:57.16#ibcon#first serial, iclass 18, count 0 2006.257.15:42:57.16#ibcon#enter sib2, iclass 18, count 0 2006.257.15:42:57.16#ibcon#flushed, iclass 18, count 0 2006.257.15:42:57.16#ibcon#about to write, iclass 18, count 0 2006.257.15:42:57.16#ibcon#wrote, iclass 18, count 0 2006.257.15:42:57.16#ibcon#about to read 3, iclass 18, count 0 2006.257.15:42:57.18#ibcon#read 3, iclass 18, count 0 2006.257.15:42:57.18#ibcon#about to read 4, iclass 18, count 0 2006.257.15:42:57.18#ibcon#read 4, iclass 18, count 0 2006.257.15:42:57.18#ibcon#about to read 5, iclass 18, count 0 2006.257.15:42:57.18#ibcon#read 5, iclass 18, count 0 2006.257.15:42:57.18#ibcon#about to read 6, iclass 18, count 0 2006.257.15:42:57.18#ibcon#read 6, iclass 18, count 0 2006.257.15:42:57.18#ibcon#end of sib2, iclass 18, count 0 2006.257.15:42:57.18#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:42:57.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:42:57.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:42:57.18#ibcon#*before write, iclass 18, count 0 2006.257.15:42:57.18#ibcon#enter sib2, iclass 18, count 0 2006.257.15:42:57.18#ibcon#flushed, iclass 18, count 0 2006.257.15:42:57.18#ibcon#about to write, iclass 18, count 0 2006.257.15:42:57.18#ibcon#wrote, iclass 18, count 0 2006.257.15:42:57.18#ibcon#about to read 3, iclass 18, count 0 2006.257.15:42:57.22#ibcon#read 3, iclass 18, count 0 2006.257.15:42:57.22#ibcon#about to read 4, iclass 18, count 0 2006.257.15:42:57.22#ibcon#read 4, iclass 18, count 0 2006.257.15:42:57.22#ibcon#about to read 5, iclass 18, count 0 2006.257.15:42:57.22#ibcon#read 5, iclass 18, count 0 2006.257.15:42:57.22#ibcon#about to read 6, iclass 18, count 0 2006.257.15:42:57.22#ibcon#read 6, iclass 18, count 0 2006.257.15:42:57.22#ibcon#end of sib2, iclass 18, count 0 2006.257.15:42:57.22#ibcon#*after write, iclass 18, count 0 2006.257.15:42:57.22#ibcon#*before return 0, iclass 18, count 0 2006.257.15:42:57.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:42:57.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:42:57.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:42:57.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:42:57.22$vck44/va=7,4 2006.257.15:42:57.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.15:42:57.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.15:42:57.22#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:57.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:42:57.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:42:57.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:42:57.28#ibcon#enter wrdev, iclass 20, count 2 2006.257.15:42:57.28#ibcon#first serial, iclass 20, count 2 2006.257.15:42:57.28#ibcon#enter sib2, iclass 20, count 2 2006.257.15:42:57.28#ibcon#flushed, iclass 20, count 2 2006.257.15:42:57.28#ibcon#about to write, iclass 20, count 2 2006.257.15:42:57.28#ibcon#wrote, iclass 20, count 2 2006.257.15:42:57.28#ibcon#about to read 3, iclass 20, count 2 2006.257.15:42:57.30#ibcon#read 3, iclass 20, count 2 2006.257.15:42:57.30#ibcon#about to read 4, iclass 20, count 2 2006.257.15:42:57.30#ibcon#read 4, iclass 20, count 2 2006.257.15:42:57.30#ibcon#about to read 5, iclass 20, count 2 2006.257.15:42:57.30#ibcon#read 5, iclass 20, count 2 2006.257.15:42:57.30#ibcon#about to read 6, iclass 20, count 2 2006.257.15:42:57.30#ibcon#read 6, iclass 20, count 2 2006.257.15:42:57.30#ibcon#end of sib2, iclass 20, count 2 2006.257.15:42:57.30#ibcon#*mode == 0, iclass 20, count 2 2006.257.15:42:57.30#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.15:42:57.30#ibcon#[25=AT07-04\r\n] 2006.257.15:42:57.30#ibcon#*before write, iclass 20, count 2 2006.257.15:42:57.30#ibcon#enter sib2, iclass 20, count 2 2006.257.15:42:57.30#ibcon#flushed, iclass 20, count 2 2006.257.15:42:57.30#ibcon#about to write, iclass 20, count 2 2006.257.15:42:57.30#ibcon#wrote, iclass 20, count 2 2006.257.15:42:57.30#ibcon#about to read 3, iclass 20, count 2 2006.257.15:42:57.33#ibcon#read 3, iclass 20, count 2 2006.257.15:42:57.33#ibcon#about to read 4, iclass 20, count 2 2006.257.15:42:57.33#ibcon#read 4, iclass 20, count 2 2006.257.15:42:57.33#ibcon#about to read 5, iclass 20, count 2 2006.257.15:42:57.33#ibcon#read 5, iclass 20, count 2 2006.257.15:42:57.33#ibcon#about to read 6, iclass 20, count 2 2006.257.15:42:57.33#ibcon#read 6, iclass 20, count 2 2006.257.15:42:57.33#ibcon#end of sib2, iclass 20, count 2 2006.257.15:42:57.33#ibcon#*after write, iclass 20, count 2 2006.257.15:42:57.33#ibcon#*before return 0, iclass 20, count 2 2006.257.15:42:57.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:42:57.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:42:57.33#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.15:42:57.33#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:57.33#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:42:57.45#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:42:57.45#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:42:57.45#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:42:57.45#ibcon#first serial, iclass 20, count 0 2006.257.15:42:57.45#ibcon#enter sib2, iclass 20, count 0 2006.257.15:42:57.45#ibcon#flushed, iclass 20, count 0 2006.257.15:42:57.45#ibcon#about to write, iclass 20, count 0 2006.257.15:42:57.45#ibcon#wrote, iclass 20, count 0 2006.257.15:42:57.45#ibcon#about to read 3, iclass 20, count 0 2006.257.15:42:57.47#ibcon#read 3, iclass 20, count 0 2006.257.15:42:57.47#ibcon#about to read 4, iclass 20, count 0 2006.257.15:42:57.47#ibcon#read 4, iclass 20, count 0 2006.257.15:42:57.47#ibcon#about to read 5, iclass 20, count 0 2006.257.15:42:57.47#ibcon#read 5, iclass 20, count 0 2006.257.15:42:57.47#ibcon#about to read 6, iclass 20, count 0 2006.257.15:42:57.47#ibcon#read 6, iclass 20, count 0 2006.257.15:42:57.47#ibcon#end of sib2, iclass 20, count 0 2006.257.15:42:57.47#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:42:57.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:42:57.47#ibcon#[25=USB\r\n] 2006.257.15:42:57.47#ibcon#*before write, iclass 20, count 0 2006.257.15:42:57.47#ibcon#enter sib2, iclass 20, count 0 2006.257.15:42:57.47#ibcon#flushed, iclass 20, count 0 2006.257.15:42:57.47#ibcon#about to write, iclass 20, count 0 2006.257.15:42:57.47#ibcon#wrote, iclass 20, count 0 2006.257.15:42:57.47#ibcon#about to read 3, iclass 20, count 0 2006.257.15:42:57.50#ibcon#read 3, iclass 20, count 0 2006.257.15:42:57.50#ibcon#about to read 4, iclass 20, count 0 2006.257.15:42:57.50#ibcon#read 4, iclass 20, count 0 2006.257.15:42:57.50#ibcon#about to read 5, iclass 20, count 0 2006.257.15:42:57.50#ibcon#read 5, iclass 20, count 0 2006.257.15:42:57.50#ibcon#about to read 6, iclass 20, count 0 2006.257.15:42:57.50#ibcon#read 6, iclass 20, count 0 2006.257.15:42:57.50#ibcon#end of sib2, iclass 20, count 0 2006.257.15:42:57.50#ibcon#*after write, iclass 20, count 0 2006.257.15:42:57.50#ibcon#*before return 0, iclass 20, count 0 2006.257.15:42:57.50#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:42:57.50#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:42:57.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:42:57.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:42:57.50$vck44/valo=8,884.99 2006.257.15:42:57.50#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.15:42:57.50#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.15:42:57.50#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:57.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:42:57.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:42:57.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:42:57.50#ibcon#enter wrdev, iclass 22, count 0 2006.257.15:42:57.50#ibcon#first serial, iclass 22, count 0 2006.257.15:42:57.50#ibcon#enter sib2, iclass 22, count 0 2006.257.15:42:57.50#ibcon#flushed, iclass 22, count 0 2006.257.15:42:57.50#ibcon#about to write, iclass 22, count 0 2006.257.15:42:57.50#ibcon#wrote, iclass 22, count 0 2006.257.15:42:57.50#ibcon#about to read 3, iclass 22, count 0 2006.257.15:42:57.52#ibcon#read 3, iclass 22, count 0 2006.257.15:42:57.52#ibcon#about to read 4, iclass 22, count 0 2006.257.15:42:57.52#ibcon#read 4, iclass 22, count 0 2006.257.15:42:57.52#ibcon#about to read 5, iclass 22, count 0 2006.257.15:42:57.52#ibcon#read 5, iclass 22, count 0 2006.257.15:42:57.52#ibcon#about to read 6, iclass 22, count 0 2006.257.15:42:57.52#ibcon#read 6, iclass 22, count 0 2006.257.15:42:57.52#ibcon#end of sib2, iclass 22, count 0 2006.257.15:42:57.52#ibcon#*mode == 0, iclass 22, count 0 2006.257.15:42:57.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.15:42:57.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:42:57.52#ibcon#*before write, iclass 22, count 0 2006.257.15:42:57.52#ibcon#enter sib2, iclass 22, count 0 2006.257.15:42:57.52#ibcon#flushed, iclass 22, count 0 2006.257.15:42:57.52#ibcon#about to write, iclass 22, count 0 2006.257.15:42:57.52#ibcon#wrote, iclass 22, count 0 2006.257.15:42:57.52#ibcon#about to read 3, iclass 22, count 0 2006.257.15:42:57.56#ibcon#read 3, iclass 22, count 0 2006.257.15:42:57.56#ibcon#about to read 4, iclass 22, count 0 2006.257.15:42:57.56#ibcon#read 4, iclass 22, count 0 2006.257.15:42:57.56#ibcon#about to read 5, iclass 22, count 0 2006.257.15:42:57.56#ibcon#read 5, iclass 22, count 0 2006.257.15:42:57.56#ibcon#about to read 6, iclass 22, count 0 2006.257.15:42:57.56#ibcon#read 6, iclass 22, count 0 2006.257.15:42:57.56#ibcon#end of sib2, iclass 22, count 0 2006.257.15:42:57.56#ibcon#*after write, iclass 22, count 0 2006.257.15:42:57.56#ibcon#*before return 0, iclass 22, count 0 2006.257.15:42:57.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:42:57.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:42:57.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.15:42:57.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.15:42:57.56$vck44/va=8,4 2006.257.15:42:57.56#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.15:42:57.56#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.15:42:57.56#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:57.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:42:57.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:42:57.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:42:57.62#ibcon#enter wrdev, iclass 24, count 2 2006.257.15:42:57.62#ibcon#first serial, iclass 24, count 2 2006.257.15:42:57.62#ibcon#enter sib2, iclass 24, count 2 2006.257.15:42:57.62#ibcon#flushed, iclass 24, count 2 2006.257.15:42:57.62#ibcon#about to write, iclass 24, count 2 2006.257.15:42:57.62#ibcon#wrote, iclass 24, count 2 2006.257.15:42:57.62#ibcon#about to read 3, iclass 24, count 2 2006.257.15:42:57.64#ibcon#read 3, iclass 24, count 2 2006.257.15:42:57.64#ibcon#about to read 4, iclass 24, count 2 2006.257.15:42:57.64#ibcon#read 4, iclass 24, count 2 2006.257.15:42:57.64#ibcon#about to read 5, iclass 24, count 2 2006.257.15:42:57.64#ibcon#read 5, iclass 24, count 2 2006.257.15:42:57.64#ibcon#about to read 6, iclass 24, count 2 2006.257.15:42:57.64#ibcon#read 6, iclass 24, count 2 2006.257.15:42:57.64#ibcon#end of sib2, iclass 24, count 2 2006.257.15:42:57.64#ibcon#*mode == 0, iclass 24, count 2 2006.257.15:42:57.64#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.15:42:57.64#ibcon#[25=AT08-04\r\n] 2006.257.15:42:57.64#ibcon#*before write, iclass 24, count 2 2006.257.15:42:57.64#ibcon#enter sib2, iclass 24, count 2 2006.257.15:42:57.64#ibcon#flushed, iclass 24, count 2 2006.257.15:42:57.64#ibcon#about to write, iclass 24, count 2 2006.257.15:42:57.64#ibcon#wrote, iclass 24, count 2 2006.257.15:42:57.64#ibcon#about to read 3, iclass 24, count 2 2006.257.15:42:57.67#ibcon#read 3, iclass 24, count 2 2006.257.15:42:57.67#ibcon#about to read 4, iclass 24, count 2 2006.257.15:42:57.67#ibcon#read 4, iclass 24, count 2 2006.257.15:42:57.67#ibcon#about to read 5, iclass 24, count 2 2006.257.15:42:57.67#ibcon#read 5, iclass 24, count 2 2006.257.15:42:57.67#ibcon#about to read 6, iclass 24, count 2 2006.257.15:42:57.67#ibcon#read 6, iclass 24, count 2 2006.257.15:42:57.67#ibcon#end of sib2, iclass 24, count 2 2006.257.15:42:57.67#ibcon#*after write, iclass 24, count 2 2006.257.15:42:57.67#ibcon#*before return 0, iclass 24, count 2 2006.257.15:42:57.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:42:57.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.15:42:57.67#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.15:42:57.67#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:57.67#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:42:57.79#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:42:57.79#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:42:57.79#ibcon#enter wrdev, iclass 24, count 0 2006.257.15:42:57.79#ibcon#first serial, iclass 24, count 0 2006.257.15:42:57.79#ibcon#enter sib2, iclass 24, count 0 2006.257.15:42:57.79#ibcon#flushed, iclass 24, count 0 2006.257.15:42:57.79#ibcon#about to write, iclass 24, count 0 2006.257.15:42:57.79#ibcon#wrote, iclass 24, count 0 2006.257.15:42:57.79#ibcon#about to read 3, iclass 24, count 0 2006.257.15:42:57.81#ibcon#read 3, iclass 24, count 0 2006.257.15:42:57.81#ibcon#about to read 4, iclass 24, count 0 2006.257.15:42:57.81#ibcon#read 4, iclass 24, count 0 2006.257.15:42:57.81#ibcon#about to read 5, iclass 24, count 0 2006.257.15:42:57.81#ibcon#read 5, iclass 24, count 0 2006.257.15:42:57.81#ibcon#about to read 6, iclass 24, count 0 2006.257.15:42:57.81#ibcon#read 6, iclass 24, count 0 2006.257.15:42:57.81#ibcon#end of sib2, iclass 24, count 0 2006.257.15:42:57.81#ibcon#*mode == 0, iclass 24, count 0 2006.257.15:42:57.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.15:42:57.81#ibcon#[25=USB\r\n] 2006.257.15:42:57.81#ibcon#*before write, iclass 24, count 0 2006.257.15:42:57.81#ibcon#enter sib2, iclass 24, count 0 2006.257.15:42:57.81#ibcon#flushed, iclass 24, count 0 2006.257.15:42:57.81#ibcon#about to write, iclass 24, count 0 2006.257.15:42:57.81#ibcon#wrote, iclass 24, count 0 2006.257.15:42:57.81#ibcon#about to read 3, iclass 24, count 0 2006.257.15:42:57.84#ibcon#read 3, iclass 24, count 0 2006.257.15:42:57.84#ibcon#about to read 4, iclass 24, count 0 2006.257.15:42:57.84#ibcon#read 4, iclass 24, count 0 2006.257.15:42:57.84#ibcon#about to read 5, iclass 24, count 0 2006.257.15:42:57.84#ibcon#read 5, iclass 24, count 0 2006.257.15:42:57.84#ibcon#about to read 6, iclass 24, count 0 2006.257.15:42:57.84#ibcon#read 6, iclass 24, count 0 2006.257.15:42:57.84#ibcon#end of sib2, iclass 24, count 0 2006.257.15:42:57.84#ibcon#*after write, iclass 24, count 0 2006.257.15:42:57.84#ibcon#*before return 0, iclass 24, count 0 2006.257.15:42:57.84#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:42:57.84#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.15:42:57.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.15:42:57.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.15:42:57.84$vck44/vblo=1,629.99 2006.257.15:42:57.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.15:42:57.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.15:42:57.84#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:57.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:57.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:57.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:57.84#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:42:57.84#ibcon#first serial, iclass 26, count 0 2006.257.15:42:57.84#ibcon#enter sib2, iclass 26, count 0 2006.257.15:42:57.84#ibcon#flushed, iclass 26, count 0 2006.257.15:42:57.84#ibcon#about to write, iclass 26, count 0 2006.257.15:42:57.84#ibcon#wrote, iclass 26, count 0 2006.257.15:42:57.84#ibcon#about to read 3, iclass 26, count 0 2006.257.15:42:57.86#ibcon#read 3, iclass 26, count 0 2006.257.15:42:57.86#ibcon#about to read 4, iclass 26, count 0 2006.257.15:42:57.86#ibcon#read 4, iclass 26, count 0 2006.257.15:42:57.86#ibcon#about to read 5, iclass 26, count 0 2006.257.15:42:57.86#ibcon#read 5, iclass 26, count 0 2006.257.15:42:57.86#ibcon#about to read 6, iclass 26, count 0 2006.257.15:42:57.86#ibcon#read 6, iclass 26, count 0 2006.257.15:42:57.86#ibcon#end of sib2, iclass 26, count 0 2006.257.15:42:57.86#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:42:57.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:42:57.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:42:57.86#ibcon#*before write, iclass 26, count 0 2006.257.15:42:57.86#ibcon#enter sib2, iclass 26, count 0 2006.257.15:42:57.86#ibcon#flushed, iclass 26, count 0 2006.257.15:42:57.86#ibcon#about to write, iclass 26, count 0 2006.257.15:42:57.86#ibcon#wrote, iclass 26, count 0 2006.257.15:42:57.86#ibcon#about to read 3, iclass 26, count 0 2006.257.15:42:57.90#ibcon#read 3, iclass 26, count 0 2006.257.15:42:57.90#ibcon#about to read 4, iclass 26, count 0 2006.257.15:42:57.90#ibcon#read 4, iclass 26, count 0 2006.257.15:42:57.90#ibcon#about to read 5, iclass 26, count 0 2006.257.15:42:57.90#ibcon#read 5, iclass 26, count 0 2006.257.15:42:57.90#ibcon#about to read 6, iclass 26, count 0 2006.257.15:42:57.90#ibcon#read 6, iclass 26, count 0 2006.257.15:42:57.90#ibcon#end of sib2, iclass 26, count 0 2006.257.15:42:57.90#ibcon#*after write, iclass 26, count 0 2006.257.15:42:57.90#ibcon#*before return 0, iclass 26, count 0 2006.257.15:42:57.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:57.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.15:42:57.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:42:57.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:42:57.90$vck44/vb=1,4 2006.257.15:42:57.90#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.15:42:57.90#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.15:42:57.90#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:57.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:57.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:57.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:57.90#ibcon#enter wrdev, iclass 28, count 2 2006.257.15:42:57.90#ibcon#first serial, iclass 28, count 2 2006.257.15:42:57.90#ibcon#enter sib2, iclass 28, count 2 2006.257.15:42:57.90#ibcon#flushed, iclass 28, count 2 2006.257.15:42:57.90#ibcon#about to write, iclass 28, count 2 2006.257.15:42:57.90#ibcon#wrote, iclass 28, count 2 2006.257.15:42:57.90#ibcon#about to read 3, iclass 28, count 2 2006.257.15:42:57.92#ibcon#read 3, iclass 28, count 2 2006.257.15:42:57.92#ibcon#about to read 4, iclass 28, count 2 2006.257.15:42:57.92#ibcon#read 4, iclass 28, count 2 2006.257.15:42:57.92#ibcon#about to read 5, iclass 28, count 2 2006.257.15:42:57.92#ibcon#read 5, iclass 28, count 2 2006.257.15:42:57.92#ibcon#about to read 6, iclass 28, count 2 2006.257.15:42:57.92#ibcon#read 6, iclass 28, count 2 2006.257.15:42:57.92#ibcon#end of sib2, iclass 28, count 2 2006.257.15:42:57.92#ibcon#*mode == 0, iclass 28, count 2 2006.257.15:42:57.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.15:42:57.92#ibcon#[27=AT01-04\r\n] 2006.257.15:42:57.92#ibcon#*before write, iclass 28, count 2 2006.257.15:42:57.92#ibcon#enter sib2, iclass 28, count 2 2006.257.15:42:57.92#ibcon#flushed, iclass 28, count 2 2006.257.15:42:57.92#ibcon#about to write, iclass 28, count 2 2006.257.15:42:57.92#ibcon#wrote, iclass 28, count 2 2006.257.15:42:57.92#ibcon#about to read 3, iclass 28, count 2 2006.257.15:42:57.95#ibcon#read 3, iclass 28, count 2 2006.257.15:42:57.95#ibcon#about to read 4, iclass 28, count 2 2006.257.15:42:57.95#ibcon#read 4, iclass 28, count 2 2006.257.15:42:57.95#ibcon#about to read 5, iclass 28, count 2 2006.257.15:42:57.95#ibcon#read 5, iclass 28, count 2 2006.257.15:42:57.95#ibcon#about to read 6, iclass 28, count 2 2006.257.15:42:57.95#ibcon#read 6, iclass 28, count 2 2006.257.15:42:57.95#ibcon#end of sib2, iclass 28, count 2 2006.257.15:42:57.95#ibcon#*after write, iclass 28, count 2 2006.257.15:42:57.95#ibcon#*before return 0, iclass 28, count 2 2006.257.15:42:57.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:57.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.15:42:57.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.15:42:57.95#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:57.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:58.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:58.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:58.07#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:42:58.07#ibcon#first serial, iclass 28, count 0 2006.257.15:42:58.07#ibcon#enter sib2, iclass 28, count 0 2006.257.15:42:58.07#ibcon#flushed, iclass 28, count 0 2006.257.15:42:58.07#ibcon#about to write, iclass 28, count 0 2006.257.15:42:58.07#ibcon#wrote, iclass 28, count 0 2006.257.15:42:58.07#ibcon#about to read 3, iclass 28, count 0 2006.257.15:42:58.09#ibcon#read 3, iclass 28, count 0 2006.257.15:42:58.09#ibcon#about to read 4, iclass 28, count 0 2006.257.15:42:58.09#ibcon#read 4, iclass 28, count 0 2006.257.15:42:58.09#ibcon#about to read 5, iclass 28, count 0 2006.257.15:42:58.09#ibcon#read 5, iclass 28, count 0 2006.257.15:42:58.09#ibcon#about to read 6, iclass 28, count 0 2006.257.15:42:58.09#ibcon#read 6, iclass 28, count 0 2006.257.15:42:58.09#ibcon#end of sib2, iclass 28, count 0 2006.257.15:42:58.09#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:42:58.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:42:58.09#ibcon#[27=USB\r\n] 2006.257.15:42:58.09#ibcon#*before write, iclass 28, count 0 2006.257.15:42:58.09#ibcon#enter sib2, iclass 28, count 0 2006.257.15:42:58.09#ibcon#flushed, iclass 28, count 0 2006.257.15:42:58.09#ibcon#about to write, iclass 28, count 0 2006.257.15:42:58.09#ibcon#wrote, iclass 28, count 0 2006.257.15:42:58.09#ibcon#about to read 3, iclass 28, count 0 2006.257.15:42:58.12#ibcon#read 3, iclass 28, count 0 2006.257.15:42:58.12#ibcon#about to read 4, iclass 28, count 0 2006.257.15:42:58.12#ibcon#read 4, iclass 28, count 0 2006.257.15:42:58.12#ibcon#about to read 5, iclass 28, count 0 2006.257.15:42:58.12#ibcon#read 5, iclass 28, count 0 2006.257.15:42:58.12#ibcon#about to read 6, iclass 28, count 0 2006.257.15:42:58.12#ibcon#read 6, iclass 28, count 0 2006.257.15:42:58.12#ibcon#end of sib2, iclass 28, count 0 2006.257.15:42:58.12#ibcon#*after write, iclass 28, count 0 2006.257.15:42:58.12#ibcon#*before return 0, iclass 28, count 0 2006.257.15:42:58.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:58.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.15:42:58.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:42:58.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:42:58.12$vck44/vblo=2,634.99 2006.257.15:42:58.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.15:42:58.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.15:42:58.12#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:58.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:58.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:58.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:58.12#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:42:58.12#ibcon#first serial, iclass 30, count 0 2006.257.15:42:58.12#ibcon#enter sib2, iclass 30, count 0 2006.257.15:42:58.12#ibcon#flushed, iclass 30, count 0 2006.257.15:42:58.12#ibcon#about to write, iclass 30, count 0 2006.257.15:42:58.12#ibcon#wrote, iclass 30, count 0 2006.257.15:42:58.12#ibcon#about to read 3, iclass 30, count 0 2006.257.15:42:58.14#ibcon#read 3, iclass 30, count 0 2006.257.15:42:58.14#ibcon#about to read 4, iclass 30, count 0 2006.257.15:42:58.14#ibcon#read 4, iclass 30, count 0 2006.257.15:42:58.14#ibcon#about to read 5, iclass 30, count 0 2006.257.15:42:58.14#ibcon#read 5, iclass 30, count 0 2006.257.15:42:58.14#ibcon#about to read 6, iclass 30, count 0 2006.257.15:42:58.14#ibcon#read 6, iclass 30, count 0 2006.257.15:42:58.14#ibcon#end of sib2, iclass 30, count 0 2006.257.15:42:58.14#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:42:58.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:42:58.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:42:58.14#ibcon#*before write, iclass 30, count 0 2006.257.15:42:58.14#ibcon#enter sib2, iclass 30, count 0 2006.257.15:42:58.14#ibcon#flushed, iclass 30, count 0 2006.257.15:42:58.14#ibcon#about to write, iclass 30, count 0 2006.257.15:42:58.14#ibcon#wrote, iclass 30, count 0 2006.257.15:42:58.14#ibcon#about to read 3, iclass 30, count 0 2006.257.15:42:58.18#ibcon#read 3, iclass 30, count 0 2006.257.15:42:58.18#ibcon#about to read 4, iclass 30, count 0 2006.257.15:42:58.18#ibcon#read 4, iclass 30, count 0 2006.257.15:42:58.18#ibcon#about to read 5, iclass 30, count 0 2006.257.15:42:58.18#ibcon#read 5, iclass 30, count 0 2006.257.15:42:58.18#ibcon#about to read 6, iclass 30, count 0 2006.257.15:42:58.18#ibcon#read 6, iclass 30, count 0 2006.257.15:42:58.18#ibcon#end of sib2, iclass 30, count 0 2006.257.15:42:58.18#ibcon#*after write, iclass 30, count 0 2006.257.15:42:58.18#ibcon#*before return 0, iclass 30, count 0 2006.257.15:42:58.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:58.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.15:42:58.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:42:58.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:42:58.18$vck44/vb=2,5 2006.257.15:42:58.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.15:42:58.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.15:42:58.18#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:58.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:58.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:58.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:58.24#ibcon#enter wrdev, iclass 32, count 2 2006.257.15:42:58.24#ibcon#first serial, iclass 32, count 2 2006.257.15:42:58.24#ibcon#enter sib2, iclass 32, count 2 2006.257.15:42:58.24#ibcon#flushed, iclass 32, count 2 2006.257.15:42:58.24#ibcon#about to write, iclass 32, count 2 2006.257.15:42:58.24#ibcon#wrote, iclass 32, count 2 2006.257.15:42:58.24#ibcon#about to read 3, iclass 32, count 2 2006.257.15:42:58.26#ibcon#read 3, iclass 32, count 2 2006.257.15:42:58.26#ibcon#about to read 4, iclass 32, count 2 2006.257.15:42:58.26#ibcon#read 4, iclass 32, count 2 2006.257.15:42:58.26#ibcon#about to read 5, iclass 32, count 2 2006.257.15:42:58.26#ibcon#read 5, iclass 32, count 2 2006.257.15:42:58.26#ibcon#about to read 6, iclass 32, count 2 2006.257.15:42:58.26#ibcon#read 6, iclass 32, count 2 2006.257.15:42:58.26#ibcon#end of sib2, iclass 32, count 2 2006.257.15:42:58.26#ibcon#*mode == 0, iclass 32, count 2 2006.257.15:42:58.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.15:42:58.26#ibcon#[27=AT02-05\r\n] 2006.257.15:42:58.26#ibcon#*before write, iclass 32, count 2 2006.257.15:42:58.26#ibcon#enter sib2, iclass 32, count 2 2006.257.15:42:58.26#ibcon#flushed, iclass 32, count 2 2006.257.15:42:58.26#ibcon#about to write, iclass 32, count 2 2006.257.15:42:58.26#ibcon#wrote, iclass 32, count 2 2006.257.15:42:58.26#ibcon#about to read 3, iclass 32, count 2 2006.257.15:42:58.29#ibcon#read 3, iclass 32, count 2 2006.257.15:42:58.38#ibcon#about to read 4, iclass 32, count 2 2006.257.15:42:58.38#ibcon#read 4, iclass 32, count 2 2006.257.15:42:58.38#ibcon#about to read 5, iclass 32, count 2 2006.257.15:42:58.38#ibcon#read 5, iclass 32, count 2 2006.257.15:42:58.38#ibcon#about to read 6, iclass 32, count 2 2006.257.15:42:58.38#ibcon#read 6, iclass 32, count 2 2006.257.15:42:58.38#ibcon#end of sib2, iclass 32, count 2 2006.257.15:42:58.38#ibcon#*after write, iclass 32, count 2 2006.257.15:42:58.38#ibcon#*before return 0, iclass 32, count 2 2006.257.15:42:58.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:58.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.15:42:58.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.15:42:58.38#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:58.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:58.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:58.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:58.50#ibcon#enter wrdev, iclass 32, count 0 2006.257.15:42:58.50#ibcon#first serial, iclass 32, count 0 2006.257.15:42:58.50#ibcon#enter sib2, iclass 32, count 0 2006.257.15:42:58.50#ibcon#flushed, iclass 32, count 0 2006.257.15:42:58.50#ibcon#about to write, iclass 32, count 0 2006.257.15:42:58.50#ibcon#wrote, iclass 32, count 0 2006.257.15:42:58.50#ibcon#about to read 3, iclass 32, count 0 2006.257.15:42:58.52#ibcon#read 3, iclass 32, count 0 2006.257.15:42:58.52#ibcon#about to read 4, iclass 32, count 0 2006.257.15:42:58.52#ibcon#read 4, iclass 32, count 0 2006.257.15:42:58.52#ibcon#about to read 5, iclass 32, count 0 2006.257.15:42:58.52#ibcon#read 5, iclass 32, count 0 2006.257.15:42:58.52#ibcon#about to read 6, iclass 32, count 0 2006.257.15:42:58.52#ibcon#read 6, iclass 32, count 0 2006.257.15:42:58.52#ibcon#end of sib2, iclass 32, count 0 2006.257.15:42:58.52#ibcon#*mode == 0, iclass 32, count 0 2006.257.15:42:58.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.15:42:58.52#ibcon#[27=USB\r\n] 2006.257.15:42:58.52#ibcon#*before write, iclass 32, count 0 2006.257.15:42:58.52#ibcon#enter sib2, iclass 32, count 0 2006.257.15:42:58.52#ibcon#flushed, iclass 32, count 0 2006.257.15:42:58.52#ibcon#about to write, iclass 32, count 0 2006.257.15:42:58.52#ibcon#wrote, iclass 32, count 0 2006.257.15:42:58.52#ibcon#about to read 3, iclass 32, count 0 2006.257.15:42:58.55#ibcon#read 3, iclass 32, count 0 2006.257.15:42:58.55#ibcon#about to read 4, iclass 32, count 0 2006.257.15:42:58.55#ibcon#read 4, iclass 32, count 0 2006.257.15:42:58.55#ibcon#about to read 5, iclass 32, count 0 2006.257.15:42:58.55#ibcon#read 5, iclass 32, count 0 2006.257.15:42:58.55#ibcon#about to read 6, iclass 32, count 0 2006.257.15:42:58.55#ibcon#read 6, iclass 32, count 0 2006.257.15:42:58.55#ibcon#end of sib2, iclass 32, count 0 2006.257.15:42:58.55#ibcon#*after write, iclass 32, count 0 2006.257.15:42:58.55#ibcon#*before return 0, iclass 32, count 0 2006.257.15:42:58.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:58.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.15:42:58.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.15:42:58.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.15:42:58.55$vck44/vblo=3,649.99 2006.257.15:42:58.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.15:42:58.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.15:42:58.55#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:58.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:58.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:58.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:58.55#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:42:58.55#ibcon#first serial, iclass 34, count 0 2006.257.15:42:58.55#ibcon#enter sib2, iclass 34, count 0 2006.257.15:42:58.55#ibcon#flushed, iclass 34, count 0 2006.257.15:42:58.55#ibcon#about to write, iclass 34, count 0 2006.257.15:42:58.55#ibcon#wrote, iclass 34, count 0 2006.257.15:42:58.55#ibcon#about to read 3, iclass 34, count 0 2006.257.15:42:58.57#ibcon#read 3, iclass 34, count 0 2006.257.15:42:58.57#ibcon#about to read 4, iclass 34, count 0 2006.257.15:42:58.57#ibcon#read 4, iclass 34, count 0 2006.257.15:42:58.57#ibcon#about to read 5, iclass 34, count 0 2006.257.15:42:58.57#ibcon#read 5, iclass 34, count 0 2006.257.15:42:58.57#ibcon#about to read 6, iclass 34, count 0 2006.257.15:42:58.57#ibcon#read 6, iclass 34, count 0 2006.257.15:42:58.57#ibcon#end of sib2, iclass 34, count 0 2006.257.15:42:58.57#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:42:58.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:42:58.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:42:58.57#ibcon#*before write, iclass 34, count 0 2006.257.15:42:58.57#ibcon#enter sib2, iclass 34, count 0 2006.257.15:42:58.57#ibcon#flushed, iclass 34, count 0 2006.257.15:42:58.57#ibcon#about to write, iclass 34, count 0 2006.257.15:42:58.57#ibcon#wrote, iclass 34, count 0 2006.257.15:42:58.57#ibcon#about to read 3, iclass 34, count 0 2006.257.15:42:58.61#ibcon#read 3, iclass 34, count 0 2006.257.15:42:58.61#ibcon#about to read 4, iclass 34, count 0 2006.257.15:42:58.61#ibcon#read 4, iclass 34, count 0 2006.257.15:42:58.61#ibcon#about to read 5, iclass 34, count 0 2006.257.15:42:58.61#ibcon#read 5, iclass 34, count 0 2006.257.15:42:58.61#ibcon#about to read 6, iclass 34, count 0 2006.257.15:42:58.61#ibcon#read 6, iclass 34, count 0 2006.257.15:42:58.61#ibcon#end of sib2, iclass 34, count 0 2006.257.15:42:58.61#ibcon#*after write, iclass 34, count 0 2006.257.15:42:58.61#ibcon#*before return 0, iclass 34, count 0 2006.257.15:42:58.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:58.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.15:42:58.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:42:58.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:42:58.61$vck44/vb=3,4 2006.257.15:42:58.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.15:42:58.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.15:42:58.61#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:58.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:58.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:58.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:58.67#ibcon#enter wrdev, iclass 36, count 2 2006.257.15:42:58.67#ibcon#first serial, iclass 36, count 2 2006.257.15:42:58.67#ibcon#enter sib2, iclass 36, count 2 2006.257.15:42:58.67#ibcon#flushed, iclass 36, count 2 2006.257.15:42:58.67#ibcon#about to write, iclass 36, count 2 2006.257.15:42:58.67#ibcon#wrote, iclass 36, count 2 2006.257.15:42:58.67#ibcon#about to read 3, iclass 36, count 2 2006.257.15:42:58.69#ibcon#read 3, iclass 36, count 2 2006.257.15:42:58.69#ibcon#about to read 4, iclass 36, count 2 2006.257.15:42:58.69#ibcon#read 4, iclass 36, count 2 2006.257.15:42:58.69#ibcon#about to read 5, iclass 36, count 2 2006.257.15:42:58.69#ibcon#read 5, iclass 36, count 2 2006.257.15:42:58.69#ibcon#about to read 6, iclass 36, count 2 2006.257.15:42:58.69#ibcon#read 6, iclass 36, count 2 2006.257.15:42:58.69#ibcon#end of sib2, iclass 36, count 2 2006.257.15:42:58.69#ibcon#*mode == 0, iclass 36, count 2 2006.257.15:42:58.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.15:42:58.69#ibcon#[27=AT03-04\r\n] 2006.257.15:42:58.69#ibcon#*before write, iclass 36, count 2 2006.257.15:42:58.69#ibcon#enter sib2, iclass 36, count 2 2006.257.15:42:58.69#ibcon#flushed, iclass 36, count 2 2006.257.15:42:58.69#ibcon#about to write, iclass 36, count 2 2006.257.15:42:58.69#ibcon#wrote, iclass 36, count 2 2006.257.15:42:58.69#ibcon#about to read 3, iclass 36, count 2 2006.257.15:42:58.72#ibcon#read 3, iclass 36, count 2 2006.257.15:42:58.72#ibcon#about to read 4, iclass 36, count 2 2006.257.15:42:58.72#ibcon#read 4, iclass 36, count 2 2006.257.15:42:58.72#ibcon#about to read 5, iclass 36, count 2 2006.257.15:42:58.72#ibcon#read 5, iclass 36, count 2 2006.257.15:42:58.72#ibcon#about to read 6, iclass 36, count 2 2006.257.15:42:58.72#ibcon#read 6, iclass 36, count 2 2006.257.15:42:58.72#ibcon#end of sib2, iclass 36, count 2 2006.257.15:42:58.72#ibcon#*after write, iclass 36, count 2 2006.257.15:42:58.72#ibcon#*before return 0, iclass 36, count 2 2006.257.15:42:58.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:58.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.15:42:58.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.15:42:58.72#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:58.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:58.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:58.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:58.84#ibcon#enter wrdev, iclass 36, count 0 2006.257.15:42:58.84#ibcon#first serial, iclass 36, count 0 2006.257.15:42:58.84#ibcon#enter sib2, iclass 36, count 0 2006.257.15:42:58.84#ibcon#flushed, iclass 36, count 0 2006.257.15:42:58.84#ibcon#about to write, iclass 36, count 0 2006.257.15:42:58.84#ibcon#wrote, iclass 36, count 0 2006.257.15:42:58.84#ibcon#about to read 3, iclass 36, count 0 2006.257.15:42:58.86#ibcon#read 3, iclass 36, count 0 2006.257.15:42:58.86#ibcon#about to read 4, iclass 36, count 0 2006.257.15:42:58.86#ibcon#read 4, iclass 36, count 0 2006.257.15:42:58.86#ibcon#about to read 5, iclass 36, count 0 2006.257.15:42:58.86#ibcon#read 5, iclass 36, count 0 2006.257.15:42:58.86#ibcon#about to read 6, iclass 36, count 0 2006.257.15:42:58.86#ibcon#read 6, iclass 36, count 0 2006.257.15:42:58.86#ibcon#end of sib2, iclass 36, count 0 2006.257.15:42:58.86#ibcon#*mode == 0, iclass 36, count 0 2006.257.15:42:58.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.15:42:58.86#ibcon#[27=USB\r\n] 2006.257.15:42:58.86#ibcon#*before write, iclass 36, count 0 2006.257.15:42:58.86#ibcon#enter sib2, iclass 36, count 0 2006.257.15:42:58.86#ibcon#flushed, iclass 36, count 0 2006.257.15:42:58.86#ibcon#about to write, iclass 36, count 0 2006.257.15:42:58.86#ibcon#wrote, iclass 36, count 0 2006.257.15:42:58.86#ibcon#about to read 3, iclass 36, count 0 2006.257.15:42:58.89#ibcon#read 3, iclass 36, count 0 2006.257.15:42:58.89#ibcon#about to read 4, iclass 36, count 0 2006.257.15:42:58.89#ibcon#read 4, iclass 36, count 0 2006.257.15:42:58.89#ibcon#about to read 5, iclass 36, count 0 2006.257.15:42:58.89#ibcon#read 5, iclass 36, count 0 2006.257.15:42:58.89#ibcon#about to read 6, iclass 36, count 0 2006.257.15:42:58.89#ibcon#read 6, iclass 36, count 0 2006.257.15:42:58.89#ibcon#end of sib2, iclass 36, count 0 2006.257.15:42:58.89#ibcon#*after write, iclass 36, count 0 2006.257.15:42:58.89#ibcon#*before return 0, iclass 36, count 0 2006.257.15:42:58.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:58.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.15:42:58.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.15:42:58.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.15:42:58.89$vck44/vblo=4,679.99 2006.257.15:42:58.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.15:42:58.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.15:42:58.89#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:58.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:58.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:58.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:58.89#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:42:58.89#ibcon#first serial, iclass 38, count 0 2006.257.15:42:58.89#ibcon#enter sib2, iclass 38, count 0 2006.257.15:42:58.89#ibcon#flushed, iclass 38, count 0 2006.257.15:42:58.89#ibcon#about to write, iclass 38, count 0 2006.257.15:42:58.89#ibcon#wrote, iclass 38, count 0 2006.257.15:42:58.89#ibcon#about to read 3, iclass 38, count 0 2006.257.15:42:58.91#ibcon#read 3, iclass 38, count 0 2006.257.15:42:58.91#ibcon#about to read 4, iclass 38, count 0 2006.257.15:42:58.91#ibcon#read 4, iclass 38, count 0 2006.257.15:42:58.91#ibcon#about to read 5, iclass 38, count 0 2006.257.15:42:58.91#ibcon#read 5, iclass 38, count 0 2006.257.15:42:58.91#ibcon#about to read 6, iclass 38, count 0 2006.257.15:42:58.91#ibcon#read 6, iclass 38, count 0 2006.257.15:42:58.91#ibcon#end of sib2, iclass 38, count 0 2006.257.15:42:58.91#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:42:58.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:42:58.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:42:58.91#ibcon#*before write, iclass 38, count 0 2006.257.15:42:58.91#ibcon#enter sib2, iclass 38, count 0 2006.257.15:42:58.91#ibcon#flushed, iclass 38, count 0 2006.257.15:42:58.91#ibcon#about to write, iclass 38, count 0 2006.257.15:42:58.91#ibcon#wrote, iclass 38, count 0 2006.257.15:42:58.91#ibcon#about to read 3, iclass 38, count 0 2006.257.15:42:58.95#ibcon#read 3, iclass 38, count 0 2006.257.15:42:58.95#ibcon#about to read 4, iclass 38, count 0 2006.257.15:42:58.95#ibcon#read 4, iclass 38, count 0 2006.257.15:42:58.95#ibcon#about to read 5, iclass 38, count 0 2006.257.15:42:58.95#ibcon#read 5, iclass 38, count 0 2006.257.15:42:58.95#ibcon#about to read 6, iclass 38, count 0 2006.257.15:42:58.95#ibcon#read 6, iclass 38, count 0 2006.257.15:42:58.95#ibcon#end of sib2, iclass 38, count 0 2006.257.15:42:58.95#ibcon#*after write, iclass 38, count 0 2006.257.15:42:58.95#ibcon#*before return 0, iclass 38, count 0 2006.257.15:42:58.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:58.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.15:42:58.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:42:58.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:42:58.95$vck44/vb=4,5 2006.257.15:42:58.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.15:42:58.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.15:42:58.95#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:58.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:59.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:59.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:59.01#ibcon#enter wrdev, iclass 40, count 2 2006.257.15:42:59.01#ibcon#first serial, iclass 40, count 2 2006.257.15:42:59.01#ibcon#enter sib2, iclass 40, count 2 2006.257.15:42:59.01#ibcon#flushed, iclass 40, count 2 2006.257.15:42:59.01#ibcon#about to write, iclass 40, count 2 2006.257.15:42:59.01#ibcon#wrote, iclass 40, count 2 2006.257.15:42:59.01#ibcon#about to read 3, iclass 40, count 2 2006.257.15:42:59.03#ibcon#read 3, iclass 40, count 2 2006.257.15:42:59.03#ibcon#about to read 4, iclass 40, count 2 2006.257.15:42:59.03#ibcon#read 4, iclass 40, count 2 2006.257.15:42:59.03#ibcon#about to read 5, iclass 40, count 2 2006.257.15:42:59.03#ibcon#read 5, iclass 40, count 2 2006.257.15:42:59.03#ibcon#about to read 6, iclass 40, count 2 2006.257.15:42:59.03#ibcon#read 6, iclass 40, count 2 2006.257.15:42:59.03#ibcon#end of sib2, iclass 40, count 2 2006.257.15:42:59.03#ibcon#*mode == 0, iclass 40, count 2 2006.257.15:42:59.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.15:42:59.03#ibcon#[27=AT04-05\r\n] 2006.257.15:42:59.03#ibcon#*before write, iclass 40, count 2 2006.257.15:42:59.03#ibcon#enter sib2, iclass 40, count 2 2006.257.15:42:59.03#ibcon#flushed, iclass 40, count 2 2006.257.15:42:59.03#ibcon#about to write, iclass 40, count 2 2006.257.15:42:59.03#ibcon#wrote, iclass 40, count 2 2006.257.15:42:59.03#ibcon#about to read 3, iclass 40, count 2 2006.257.15:42:59.06#ibcon#read 3, iclass 40, count 2 2006.257.15:42:59.06#ibcon#about to read 4, iclass 40, count 2 2006.257.15:42:59.06#ibcon#read 4, iclass 40, count 2 2006.257.15:42:59.06#ibcon#about to read 5, iclass 40, count 2 2006.257.15:42:59.06#ibcon#read 5, iclass 40, count 2 2006.257.15:42:59.06#ibcon#about to read 6, iclass 40, count 2 2006.257.15:42:59.06#ibcon#read 6, iclass 40, count 2 2006.257.15:42:59.06#ibcon#end of sib2, iclass 40, count 2 2006.257.15:42:59.06#ibcon#*after write, iclass 40, count 2 2006.257.15:42:59.06#ibcon#*before return 0, iclass 40, count 2 2006.257.15:42:59.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:59.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.15:42:59.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.15:42:59.06#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:59.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:59.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:59.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:59.18#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:42:59.18#ibcon#first serial, iclass 40, count 0 2006.257.15:42:59.18#ibcon#enter sib2, iclass 40, count 0 2006.257.15:42:59.18#ibcon#flushed, iclass 40, count 0 2006.257.15:42:59.18#ibcon#about to write, iclass 40, count 0 2006.257.15:42:59.18#ibcon#wrote, iclass 40, count 0 2006.257.15:42:59.18#ibcon#about to read 3, iclass 40, count 0 2006.257.15:42:59.20#ibcon#read 3, iclass 40, count 0 2006.257.15:42:59.20#ibcon#about to read 4, iclass 40, count 0 2006.257.15:42:59.20#ibcon#read 4, iclass 40, count 0 2006.257.15:42:59.20#ibcon#about to read 5, iclass 40, count 0 2006.257.15:42:59.20#ibcon#read 5, iclass 40, count 0 2006.257.15:42:59.20#ibcon#about to read 6, iclass 40, count 0 2006.257.15:42:59.20#ibcon#read 6, iclass 40, count 0 2006.257.15:42:59.20#ibcon#end of sib2, iclass 40, count 0 2006.257.15:42:59.20#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:42:59.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:42:59.20#ibcon#[27=USB\r\n] 2006.257.15:42:59.20#ibcon#*before write, iclass 40, count 0 2006.257.15:42:59.20#ibcon#enter sib2, iclass 40, count 0 2006.257.15:42:59.20#ibcon#flushed, iclass 40, count 0 2006.257.15:42:59.20#ibcon#about to write, iclass 40, count 0 2006.257.15:42:59.20#ibcon#wrote, iclass 40, count 0 2006.257.15:42:59.20#ibcon#about to read 3, iclass 40, count 0 2006.257.15:42:59.23#ibcon#read 3, iclass 40, count 0 2006.257.15:42:59.23#ibcon#about to read 4, iclass 40, count 0 2006.257.15:42:59.23#ibcon#read 4, iclass 40, count 0 2006.257.15:42:59.23#ibcon#about to read 5, iclass 40, count 0 2006.257.15:42:59.23#ibcon#read 5, iclass 40, count 0 2006.257.15:42:59.23#ibcon#about to read 6, iclass 40, count 0 2006.257.15:42:59.23#ibcon#read 6, iclass 40, count 0 2006.257.15:42:59.23#ibcon#end of sib2, iclass 40, count 0 2006.257.15:42:59.23#ibcon#*after write, iclass 40, count 0 2006.257.15:42:59.23#ibcon#*before return 0, iclass 40, count 0 2006.257.15:42:59.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:59.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.15:42:59.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:42:59.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:42:59.23$vck44/vblo=5,709.99 2006.257.15:42:59.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.15:42:59.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.15:42:59.23#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:59.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:59.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:59.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:59.23#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:42:59.23#ibcon#first serial, iclass 4, count 0 2006.257.15:42:59.23#ibcon#enter sib2, iclass 4, count 0 2006.257.15:42:59.23#ibcon#flushed, iclass 4, count 0 2006.257.15:42:59.23#ibcon#about to write, iclass 4, count 0 2006.257.15:42:59.23#ibcon#wrote, iclass 4, count 0 2006.257.15:42:59.23#ibcon#about to read 3, iclass 4, count 0 2006.257.15:42:59.25#ibcon#read 3, iclass 4, count 0 2006.257.15:42:59.25#ibcon#about to read 4, iclass 4, count 0 2006.257.15:42:59.25#ibcon#read 4, iclass 4, count 0 2006.257.15:42:59.25#ibcon#about to read 5, iclass 4, count 0 2006.257.15:42:59.25#ibcon#read 5, iclass 4, count 0 2006.257.15:42:59.25#ibcon#about to read 6, iclass 4, count 0 2006.257.15:42:59.25#ibcon#read 6, iclass 4, count 0 2006.257.15:42:59.25#ibcon#end of sib2, iclass 4, count 0 2006.257.15:42:59.25#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:42:59.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:42:59.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:42:59.25#ibcon#*before write, iclass 4, count 0 2006.257.15:42:59.25#ibcon#enter sib2, iclass 4, count 0 2006.257.15:42:59.25#ibcon#flushed, iclass 4, count 0 2006.257.15:42:59.25#ibcon#about to write, iclass 4, count 0 2006.257.15:42:59.25#ibcon#wrote, iclass 4, count 0 2006.257.15:42:59.25#ibcon#about to read 3, iclass 4, count 0 2006.257.15:42:59.29#ibcon#read 3, iclass 4, count 0 2006.257.15:42:59.29#ibcon#about to read 4, iclass 4, count 0 2006.257.15:42:59.29#ibcon#read 4, iclass 4, count 0 2006.257.15:42:59.29#ibcon#about to read 5, iclass 4, count 0 2006.257.15:42:59.29#ibcon#read 5, iclass 4, count 0 2006.257.15:42:59.29#ibcon#about to read 6, iclass 4, count 0 2006.257.15:42:59.29#ibcon#read 6, iclass 4, count 0 2006.257.15:42:59.29#ibcon#end of sib2, iclass 4, count 0 2006.257.15:42:59.29#ibcon#*after write, iclass 4, count 0 2006.257.15:42:59.29#ibcon#*before return 0, iclass 4, count 0 2006.257.15:42:59.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:59.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.15:42:59.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:42:59.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:42:59.29$vck44/vb=5,4 2006.257.15:42:59.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.15:42:59.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.15:42:59.29#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:59.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:59.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:59.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:59.35#ibcon#enter wrdev, iclass 6, count 2 2006.257.15:42:59.35#ibcon#first serial, iclass 6, count 2 2006.257.15:42:59.35#ibcon#enter sib2, iclass 6, count 2 2006.257.15:42:59.35#ibcon#flushed, iclass 6, count 2 2006.257.15:42:59.35#ibcon#about to write, iclass 6, count 2 2006.257.15:42:59.35#ibcon#wrote, iclass 6, count 2 2006.257.15:42:59.35#ibcon#about to read 3, iclass 6, count 2 2006.257.15:42:59.37#ibcon#read 3, iclass 6, count 2 2006.257.15:42:59.37#ibcon#about to read 4, iclass 6, count 2 2006.257.15:42:59.37#ibcon#read 4, iclass 6, count 2 2006.257.15:42:59.37#ibcon#about to read 5, iclass 6, count 2 2006.257.15:42:59.37#ibcon#read 5, iclass 6, count 2 2006.257.15:42:59.37#ibcon#about to read 6, iclass 6, count 2 2006.257.15:42:59.37#ibcon#read 6, iclass 6, count 2 2006.257.15:42:59.37#ibcon#end of sib2, iclass 6, count 2 2006.257.15:42:59.37#ibcon#*mode == 0, iclass 6, count 2 2006.257.15:42:59.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.15:42:59.37#ibcon#[27=AT05-04\r\n] 2006.257.15:42:59.37#ibcon#*before write, iclass 6, count 2 2006.257.15:42:59.37#ibcon#enter sib2, iclass 6, count 2 2006.257.15:42:59.37#ibcon#flushed, iclass 6, count 2 2006.257.15:42:59.37#ibcon#about to write, iclass 6, count 2 2006.257.15:42:59.37#ibcon#wrote, iclass 6, count 2 2006.257.15:42:59.37#ibcon#about to read 3, iclass 6, count 2 2006.257.15:42:59.40#ibcon#read 3, iclass 6, count 2 2006.257.15:42:59.40#ibcon#about to read 4, iclass 6, count 2 2006.257.15:42:59.40#ibcon#read 4, iclass 6, count 2 2006.257.15:42:59.40#ibcon#about to read 5, iclass 6, count 2 2006.257.15:42:59.40#ibcon#read 5, iclass 6, count 2 2006.257.15:42:59.40#ibcon#about to read 6, iclass 6, count 2 2006.257.15:42:59.40#ibcon#read 6, iclass 6, count 2 2006.257.15:42:59.40#ibcon#end of sib2, iclass 6, count 2 2006.257.15:42:59.40#ibcon#*after write, iclass 6, count 2 2006.257.15:42:59.40#ibcon#*before return 0, iclass 6, count 2 2006.257.15:42:59.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:59.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.15:42:59.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.15:42:59.40#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:59.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:59.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:59.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:59.52#ibcon#enter wrdev, iclass 6, count 0 2006.257.15:42:59.52#ibcon#first serial, iclass 6, count 0 2006.257.15:42:59.52#ibcon#enter sib2, iclass 6, count 0 2006.257.15:42:59.52#ibcon#flushed, iclass 6, count 0 2006.257.15:42:59.52#ibcon#about to write, iclass 6, count 0 2006.257.15:42:59.52#ibcon#wrote, iclass 6, count 0 2006.257.15:42:59.52#ibcon#about to read 3, iclass 6, count 0 2006.257.15:42:59.54#ibcon#read 3, iclass 6, count 0 2006.257.15:42:59.54#ibcon#about to read 4, iclass 6, count 0 2006.257.15:42:59.54#ibcon#read 4, iclass 6, count 0 2006.257.15:42:59.54#ibcon#about to read 5, iclass 6, count 0 2006.257.15:42:59.54#ibcon#read 5, iclass 6, count 0 2006.257.15:42:59.54#ibcon#about to read 6, iclass 6, count 0 2006.257.15:42:59.54#ibcon#read 6, iclass 6, count 0 2006.257.15:42:59.54#ibcon#end of sib2, iclass 6, count 0 2006.257.15:42:59.54#ibcon#*mode == 0, iclass 6, count 0 2006.257.15:42:59.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.15:42:59.54#ibcon#[27=USB\r\n] 2006.257.15:42:59.54#ibcon#*before write, iclass 6, count 0 2006.257.15:42:59.54#ibcon#enter sib2, iclass 6, count 0 2006.257.15:42:59.54#ibcon#flushed, iclass 6, count 0 2006.257.15:42:59.54#ibcon#about to write, iclass 6, count 0 2006.257.15:42:59.54#ibcon#wrote, iclass 6, count 0 2006.257.15:42:59.54#ibcon#about to read 3, iclass 6, count 0 2006.257.15:42:59.57#ibcon#read 3, iclass 6, count 0 2006.257.15:42:59.57#ibcon#about to read 4, iclass 6, count 0 2006.257.15:42:59.57#ibcon#read 4, iclass 6, count 0 2006.257.15:42:59.57#ibcon#about to read 5, iclass 6, count 0 2006.257.15:42:59.57#ibcon#read 5, iclass 6, count 0 2006.257.15:42:59.57#ibcon#about to read 6, iclass 6, count 0 2006.257.15:42:59.57#ibcon#read 6, iclass 6, count 0 2006.257.15:42:59.57#ibcon#end of sib2, iclass 6, count 0 2006.257.15:42:59.57#ibcon#*after write, iclass 6, count 0 2006.257.15:42:59.57#ibcon#*before return 0, iclass 6, count 0 2006.257.15:42:59.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:59.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.15:42:59.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.15:42:59.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.15:42:59.57$vck44/vblo=6,719.99 2006.257.15:42:59.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.15:42:59.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.15:42:59.57#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:59.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:42:59.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:42:59.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:42:59.57#ibcon#enter wrdev, iclass 10, count 0 2006.257.15:42:59.57#ibcon#first serial, iclass 10, count 0 2006.257.15:42:59.57#ibcon#enter sib2, iclass 10, count 0 2006.257.15:42:59.57#ibcon#flushed, iclass 10, count 0 2006.257.15:42:59.57#ibcon#about to write, iclass 10, count 0 2006.257.15:42:59.57#ibcon#wrote, iclass 10, count 0 2006.257.15:42:59.57#ibcon#about to read 3, iclass 10, count 0 2006.257.15:42:59.59#ibcon#read 3, iclass 10, count 0 2006.257.15:42:59.59#ibcon#about to read 4, iclass 10, count 0 2006.257.15:42:59.59#ibcon#read 4, iclass 10, count 0 2006.257.15:42:59.59#ibcon#about to read 5, iclass 10, count 0 2006.257.15:42:59.59#ibcon#read 5, iclass 10, count 0 2006.257.15:42:59.59#ibcon#about to read 6, iclass 10, count 0 2006.257.15:42:59.59#ibcon#read 6, iclass 10, count 0 2006.257.15:42:59.59#ibcon#end of sib2, iclass 10, count 0 2006.257.15:42:59.59#ibcon#*mode == 0, iclass 10, count 0 2006.257.15:42:59.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.15:42:59.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:42:59.59#ibcon#*before write, iclass 10, count 0 2006.257.15:42:59.59#ibcon#enter sib2, iclass 10, count 0 2006.257.15:42:59.59#ibcon#flushed, iclass 10, count 0 2006.257.15:42:59.59#ibcon#about to write, iclass 10, count 0 2006.257.15:42:59.59#ibcon#wrote, iclass 10, count 0 2006.257.15:42:59.59#ibcon#about to read 3, iclass 10, count 0 2006.257.15:42:59.63#ibcon#read 3, iclass 10, count 0 2006.257.15:42:59.63#ibcon#about to read 4, iclass 10, count 0 2006.257.15:42:59.63#ibcon#read 4, iclass 10, count 0 2006.257.15:42:59.63#ibcon#about to read 5, iclass 10, count 0 2006.257.15:42:59.63#ibcon#read 5, iclass 10, count 0 2006.257.15:42:59.63#ibcon#about to read 6, iclass 10, count 0 2006.257.15:42:59.63#ibcon#read 6, iclass 10, count 0 2006.257.15:42:59.63#ibcon#end of sib2, iclass 10, count 0 2006.257.15:42:59.63#ibcon#*after write, iclass 10, count 0 2006.257.15:42:59.63#ibcon#*before return 0, iclass 10, count 0 2006.257.15:42:59.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:42:59.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.15:42:59.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.15:42:59.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.15:42:59.63$vck44/vb=6,4 2006.257.15:42:59.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.15:42:59.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.15:42:59.63#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:59.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:42:59.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:42:59.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:42:59.69#ibcon#enter wrdev, iclass 12, count 2 2006.257.15:42:59.69#ibcon#first serial, iclass 12, count 2 2006.257.15:42:59.69#ibcon#enter sib2, iclass 12, count 2 2006.257.15:42:59.69#ibcon#flushed, iclass 12, count 2 2006.257.15:42:59.69#ibcon#about to write, iclass 12, count 2 2006.257.15:42:59.69#ibcon#wrote, iclass 12, count 2 2006.257.15:42:59.69#ibcon#about to read 3, iclass 12, count 2 2006.257.15:42:59.71#ibcon#read 3, iclass 12, count 2 2006.257.15:42:59.71#ibcon#about to read 4, iclass 12, count 2 2006.257.15:42:59.71#ibcon#read 4, iclass 12, count 2 2006.257.15:42:59.71#ibcon#about to read 5, iclass 12, count 2 2006.257.15:42:59.71#ibcon#read 5, iclass 12, count 2 2006.257.15:42:59.71#ibcon#about to read 6, iclass 12, count 2 2006.257.15:42:59.71#ibcon#read 6, iclass 12, count 2 2006.257.15:42:59.71#ibcon#end of sib2, iclass 12, count 2 2006.257.15:42:59.71#ibcon#*mode == 0, iclass 12, count 2 2006.257.15:42:59.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.15:42:59.71#ibcon#[27=AT06-04\r\n] 2006.257.15:42:59.71#ibcon#*before write, iclass 12, count 2 2006.257.15:42:59.71#ibcon#enter sib2, iclass 12, count 2 2006.257.15:42:59.71#ibcon#flushed, iclass 12, count 2 2006.257.15:42:59.71#ibcon#about to write, iclass 12, count 2 2006.257.15:42:59.71#ibcon#wrote, iclass 12, count 2 2006.257.15:42:59.71#ibcon#about to read 3, iclass 12, count 2 2006.257.15:42:59.74#ibcon#read 3, iclass 12, count 2 2006.257.15:42:59.74#ibcon#about to read 4, iclass 12, count 2 2006.257.15:42:59.74#ibcon#read 4, iclass 12, count 2 2006.257.15:42:59.74#ibcon#about to read 5, iclass 12, count 2 2006.257.15:42:59.74#ibcon#read 5, iclass 12, count 2 2006.257.15:42:59.74#ibcon#about to read 6, iclass 12, count 2 2006.257.15:42:59.74#ibcon#read 6, iclass 12, count 2 2006.257.15:42:59.74#ibcon#end of sib2, iclass 12, count 2 2006.257.15:42:59.74#ibcon#*after write, iclass 12, count 2 2006.257.15:42:59.74#ibcon#*before return 0, iclass 12, count 2 2006.257.15:42:59.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:42:59.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.15:42:59.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.15:42:59.74#ibcon#ireg 7 cls_cnt 0 2006.257.15:42:59.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:42:59.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:42:59.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:42:59.86#ibcon#enter wrdev, iclass 12, count 0 2006.257.15:42:59.86#ibcon#first serial, iclass 12, count 0 2006.257.15:42:59.86#ibcon#enter sib2, iclass 12, count 0 2006.257.15:42:59.86#ibcon#flushed, iclass 12, count 0 2006.257.15:42:59.86#ibcon#about to write, iclass 12, count 0 2006.257.15:42:59.86#ibcon#wrote, iclass 12, count 0 2006.257.15:42:59.86#ibcon#about to read 3, iclass 12, count 0 2006.257.15:42:59.88#ibcon#read 3, iclass 12, count 0 2006.257.15:42:59.88#ibcon#about to read 4, iclass 12, count 0 2006.257.15:42:59.88#ibcon#read 4, iclass 12, count 0 2006.257.15:42:59.88#ibcon#about to read 5, iclass 12, count 0 2006.257.15:42:59.88#ibcon#read 5, iclass 12, count 0 2006.257.15:42:59.88#ibcon#about to read 6, iclass 12, count 0 2006.257.15:42:59.88#ibcon#read 6, iclass 12, count 0 2006.257.15:42:59.88#ibcon#end of sib2, iclass 12, count 0 2006.257.15:42:59.88#ibcon#*mode == 0, iclass 12, count 0 2006.257.15:42:59.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.15:42:59.88#ibcon#[27=USB\r\n] 2006.257.15:42:59.88#ibcon#*before write, iclass 12, count 0 2006.257.15:42:59.88#ibcon#enter sib2, iclass 12, count 0 2006.257.15:42:59.88#ibcon#flushed, iclass 12, count 0 2006.257.15:42:59.88#ibcon#about to write, iclass 12, count 0 2006.257.15:42:59.88#ibcon#wrote, iclass 12, count 0 2006.257.15:42:59.88#ibcon#about to read 3, iclass 12, count 0 2006.257.15:42:59.91#ibcon#read 3, iclass 12, count 0 2006.257.15:42:59.91#ibcon#about to read 4, iclass 12, count 0 2006.257.15:42:59.91#ibcon#read 4, iclass 12, count 0 2006.257.15:42:59.91#ibcon#about to read 5, iclass 12, count 0 2006.257.15:42:59.91#ibcon#read 5, iclass 12, count 0 2006.257.15:42:59.91#ibcon#about to read 6, iclass 12, count 0 2006.257.15:42:59.91#ibcon#read 6, iclass 12, count 0 2006.257.15:42:59.91#ibcon#end of sib2, iclass 12, count 0 2006.257.15:42:59.91#ibcon#*after write, iclass 12, count 0 2006.257.15:42:59.91#ibcon#*before return 0, iclass 12, count 0 2006.257.15:42:59.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:42:59.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.15:42:59.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.15:42:59.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.15:42:59.91$vck44/vblo=7,734.99 2006.257.15:42:59.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.15:42:59.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.15:42:59.91#ibcon#ireg 17 cls_cnt 0 2006.257.15:42:59.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:59.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:59.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:59.91#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:42:59.91#ibcon#first serial, iclass 14, count 0 2006.257.15:42:59.91#ibcon#enter sib2, iclass 14, count 0 2006.257.15:42:59.91#ibcon#flushed, iclass 14, count 0 2006.257.15:42:59.91#ibcon#about to write, iclass 14, count 0 2006.257.15:42:59.91#ibcon#wrote, iclass 14, count 0 2006.257.15:42:59.91#ibcon#about to read 3, iclass 14, count 0 2006.257.15:42:59.93#ibcon#read 3, iclass 14, count 0 2006.257.15:42:59.93#ibcon#about to read 4, iclass 14, count 0 2006.257.15:42:59.93#ibcon#read 4, iclass 14, count 0 2006.257.15:42:59.93#ibcon#about to read 5, iclass 14, count 0 2006.257.15:42:59.93#ibcon#read 5, iclass 14, count 0 2006.257.15:42:59.93#ibcon#about to read 6, iclass 14, count 0 2006.257.15:42:59.93#ibcon#read 6, iclass 14, count 0 2006.257.15:42:59.93#ibcon#end of sib2, iclass 14, count 0 2006.257.15:42:59.93#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:42:59.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:42:59.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:42:59.93#ibcon#*before write, iclass 14, count 0 2006.257.15:42:59.93#ibcon#enter sib2, iclass 14, count 0 2006.257.15:42:59.93#ibcon#flushed, iclass 14, count 0 2006.257.15:42:59.93#ibcon#about to write, iclass 14, count 0 2006.257.15:42:59.93#ibcon#wrote, iclass 14, count 0 2006.257.15:42:59.93#ibcon#about to read 3, iclass 14, count 0 2006.257.15:42:59.97#ibcon#read 3, iclass 14, count 0 2006.257.15:42:59.97#ibcon#about to read 4, iclass 14, count 0 2006.257.15:42:59.97#ibcon#read 4, iclass 14, count 0 2006.257.15:42:59.97#ibcon#about to read 5, iclass 14, count 0 2006.257.15:42:59.97#ibcon#read 5, iclass 14, count 0 2006.257.15:42:59.97#ibcon#about to read 6, iclass 14, count 0 2006.257.15:42:59.97#ibcon#read 6, iclass 14, count 0 2006.257.15:42:59.97#ibcon#end of sib2, iclass 14, count 0 2006.257.15:42:59.97#ibcon#*after write, iclass 14, count 0 2006.257.15:42:59.97#ibcon#*before return 0, iclass 14, count 0 2006.257.15:42:59.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:59.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.15:42:59.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:42:59.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:42:59.97$vck44/vb=7,4 2006.257.15:42:59.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.15:42:59.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.15:42:59.97#ibcon#ireg 11 cls_cnt 2 2006.257.15:42:59.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:43:00.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:43:00.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:43:00.03#ibcon#enter wrdev, iclass 16, count 2 2006.257.15:43:00.03#ibcon#first serial, iclass 16, count 2 2006.257.15:43:00.03#ibcon#enter sib2, iclass 16, count 2 2006.257.15:43:00.03#ibcon#flushed, iclass 16, count 2 2006.257.15:43:00.03#ibcon#about to write, iclass 16, count 2 2006.257.15:43:00.03#ibcon#wrote, iclass 16, count 2 2006.257.15:43:00.03#ibcon#about to read 3, iclass 16, count 2 2006.257.15:43:00.05#ibcon#read 3, iclass 16, count 2 2006.257.15:43:00.05#ibcon#about to read 4, iclass 16, count 2 2006.257.15:43:00.05#ibcon#read 4, iclass 16, count 2 2006.257.15:43:00.05#ibcon#about to read 5, iclass 16, count 2 2006.257.15:43:00.05#ibcon#read 5, iclass 16, count 2 2006.257.15:43:00.05#ibcon#about to read 6, iclass 16, count 2 2006.257.15:43:00.05#ibcon#read 6, iclass 16, count 2 2006.257.15:43:00.05#ibcon#end of sib2, iclass 16, count 2 2006.257.15:43:00.05#ibcon#*mode == 0, iclass 16, count 2 2006.257.15:43:00.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.15:43:00.05#ibcon#[27=AT07-04\r\n] 2006.257.15:43:00.05#ibcon#*before write, iclass 16, count 2 2006.257.15:43:00.05#ibcon#enter sib2, iclass 16, count 2 2006.257.15:43:00.05#ibcon#flushed, iclass 16, count 2 2006.257.15:43:00.05#ibcon#about to write, iclass 16, count 2 2006.257.15:43:00.05#ibcon#wrote, iclass 16, count 2 2006.257.15:43:00.05#ibcon#about to read 3, iclass 16, count 2 2006.257.15:43:00.08#ibcon#read 3, iclass 16, count 2 2006.257.15:43:00.08#ibcon#about to read 4, iclass 16, count 2 2006.257.15:43:00.08#ibcon#read 4, iclass 16, count 2 2006.257.15:43:00.08#ibcon#about to read 5, iclass 16, count 2 2006.257.15:43:00.08#ibcon#read 5, iclass 16, count 2 2006.257.15:43:00.08#ibcon#about to read 6, iclass 16, count 2 2006.257.15:43:00.08#ibcon#read 6, iclass 16, count 2 2006.257.15:43:00.08#ibcon#end of sib2, iclass 16, count 2 2006.257.15:43:00.08#ibcon#*after write, iclass 16, count 2 2006.257.15:43:00.08#ibcon#*before return 0, iclass 16, count 2 2006.257.15:43:00.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:43:00.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.15:43:00.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.15:43:00.08#ibcon#ireg 7 cls_cnt 0 2006.257.15:43:00.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:43:00.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:43:00.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:43:00.20#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:43:00.20#ibcon#first serial, iclass 16, count 0 2006.257.15:43:00.20#ibcon#enter sib2, iclass 16, count 0 2006.257.15:43:00.20#ibcon#flushed, iclass 16, count 0 2006.257.15:43:00.20#ibcon#about to write, iclass 16, count 0 2006.257.15:43:00.20#ibcon#wrote, iclass 16, count 0 2006.257.15:43:00.20#ibcon#about to read 3, iclass 16, count 0 2006.257.15:43:00.22#ibcon#read 3, iclass 16, count 0 2006.257.15:43:00.22#ibcon#about to read 4, iclass 16, count 0 2006.257.15:43:00.22#ibcon#read 4, iclass 16, count 0 2006.257.15:43:00.22#ibcon#about to read 5, iclass 16, count 0 2006.257.15:43:00.22#ibcon#read 5, iclass 16, count 0 2006.257.15:43:00.22#ibcon#about to read 6, iclass 16, count 0 2006.257.15:43:00.22#ibcon#read 6, iclass 16, count 0 2006.257.15:43:00.22#ibcon#end of sib2, iclass 16, count 0 2006.257.15:43:00.22#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:43:00.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:43:00.22#ibcon#[27=USB\r\n] 2006.257.15:43:00.22#ibcon#*before write, iclass 16, count 0 2006.257.15:43:00.22#ibcon#enter sib2, iclass 16, count 0 2006.257.15:43:00.22#ibcon#flushed, iclass 16, count 0 2006.257.15:43:00.22#ibcon#about to write, iclass 16, count 0 2006.257.15:43:00.22#ibcon#wrote, iclass 16, count 0 2006.257.15:43:00.22#ibcon#about to read 3, iclass 16, count 0 2006.257.15:43:00.25#ibcon#read 3, iclass 16, count 0 2006.257.15:43:00.25#ibcon#about to read 4, iclass 16, count 0 2006.257.15:43:00.25#ibcon#read 4, iclass 16, count 0 2006.257.15:43:00.25#ibcon#about to read 5, iclass 16, count 0 2006.257.15:43:00.25#ibcon#read 5, iclass 16, count 0 2006.257.15:43:00.25#ibcon#about to read 6, iclass 16, count 0 2006.257.15:43:00.25#ibcon#read 6, iclass 16, count 0 2006.257.15:43:00.25#ibcon#end of sib2, iclass 16, count 0 2006.257.15:43:00.25#ibcon#*after write, iclass 16, count 0 2006.257.15:43:00.25#ibcon#*before return 0, iclass 16, count 0 2006.257.15:43:00.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:43:00.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.15:43:00.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:43:00.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:43:00.25$vck44/vblo=8,744.99 2006.257.15:43:00.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.15:43:00.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.15:43:00.25#ibcon#ireg 17 cls_cnt 0 2006.257.15:43:00.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:43:00.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:43:00.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:43:00.25#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:43:00.25#ibcon#first serial, iclass 18, count 0 2006.257.15:43:00.25#ibcon#enter sib2, iclass 18, count 0 2006.257.15:43:00.25#ibcon#flushed, iclass 18, count 0 2006.257.15:43:00.25#ibcon#about to write, iclass 18, count 0 2006.257.15:43:00.25#ibcon#wrote, iclass 18, count 0 2006.257.15:43:00.25#ibcon#about to read 3, iclass 18, count 0 2006.257.15:43:00.27#ibcon#read 3, iclass 18, count 0 2006.257.15:43:00.27#ibcon#about to read 4, iclass 18, count 0 2006.257.15:43:00.27#ibcon#read 4, iclass 18, count 0 2006.257.15:43:00.27#ibcon#about to read 5, iclass 18, count 0 2006.257.15:43:00.27#ibcon#read 5, iclass 18, count 0 2006.257.15:43:00.27#ibcon#about to read 6, iclass 18, count 0 2006.257.15:43:00.27#ibcon#read 6, iclass 18, count 0 2006.257.15:43:00.27#ibcon#end of sib2, iclass 18, count 0 2006.257.15:43:00.27#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:43:00.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:43:00.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:43:00.27#ibcon#*before write, iclass 18, count 0 2006.257.15:43:00.27#ibcon#enter sib2, iclass 18, count 0 2006.257.15:43:00.27#ibcon#flushed, iclass 18, count 0 2006.257.15:43:00.27#ibcon#about to write, iclass 18, count 0 2006.257.15:43:00.27#ibcon#wrote, iclass 18, count 0 2006.257.15:43:00.27#ibcon#about to read 3, iclass 18, count 0 2006.257.15:43:00.31#ibcon#read 3, iclass 18, count 0 2006.257.15:43:00.31#ibcon#about to read 4, iclass 18, count 0 2006.257.15:43:00.31#ibcon#read 4, iclass 18, count 0 2006.257.15:43:00.31#ibcon#about to read 5, iclass 18, count 0 2006.257.15:43:00.31#ibcon#read 5, iclass 18, count 0 2006.257.15:43:00.31#ibcon#about to read 6, iclass 18, count 0 2006.257.15:43:00.31#ibcon#read 6, iclass 18, count 0 2006.257.15:43:00.31#ibcon#end of sib2, iclass 18, count 0 2006.257.15:43:00.31#ibcon#*after write, iclass 18, count 0 2006.257.15:43:00.31#ibcon#*before return 0, iclass 18, count 0 2006.257.15:43:00.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:43:00.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:43:00.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:43:00.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:43:00.31$vck44/vb=8,4 2006.257.15:43:00.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.15:43:00.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.15:43:00.31#ibcon#ireg 11 cls_cnt 2 2006.257.15:43:00.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:43:00.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:43:00.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:43:00.37#ibcon#enter wrdev, iclass 20, count 2 2006.257.15:43:00.37#ibcon#first serial, iclass 20, count 2 2006.257.15:43:00.37#ibcon#enter sib2, iclass 20, count 2 2006.257.15:43:00.37#ibcon#flushed, iclass 20, count 2 2006.257.15:43:00.37#ibcon#about to write, iclass 20, count 2 2006.257.15:43:00.37#ibcon#wrote, iclass 20, count 2 2006.257.15:43:00.37#ibcon#about to read 3, iclass 20, count 2 2006.257.15:43:00.39#ibcon#read 3, iclass 20, count 2 2006.257.15:43:00.39#ibcon#about to read 4, iclass 20, count 2 2006.257.15:43:00.39#ibcon#read 4, iclass 20, count 2 2006.257.15:43:00.39#ibcon#about to read 5, iclass 20, count 2 2006.257.15:43:00.39#ibcon#read 5, iclass 20, count 2 2006.257.15:43:00.39#ibcon#about to read 6, iclass 20, count 2 2006.257.15:43:00.39#ibcon#read 6, iclass 20, count 2 2006.257.15:43:00.39#ibcon#end of sib2, iclass 20, count 2 2006.257.15:43:00.39#ibcon#*mode == 0, iclass 20, count 2 2006.257.15:43:00.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.15:43:00.39#ibcon#[27=AT08-04\r\n] 2006.257.15:43:00.39#ibcon#*before write, iclass 20, count 2 2006.257.15:43:00.39#ibcon#enter sib2, iclass 20, count 2 2006.257.15:43:00.39#ibcon#flushed, iclass 20, count 2 2006.257.15:43:00.39#ibcon#about to write, iclass 20, count 2 2006.257.15:43:00.39#ibcon#wrote, iclass 20, count 2 2006.257.15:43:00.39#ibcon#about to read 3, iclass 20, count 2 2006.257.15:43:00.42#ibcon#read 3, iclass 20, count 2 2006.257.15:43:00.42#ibcon#about to read 4, iclass 20, count 2 2006.257.15:43:00.42#ibcon#read 4, iclass 20, count 2 2006.257.15:43:00.42#ibcon#about to read 5, iclass 20, count 2 2006.257.15:43:00.42#ibcon#read 5, iclass 20, count 2 2006.257.15:43:00.42#ibcon#about to read 6, iclass 20, count 2 2006.257.15:43:00.42#ibcon#read 6, iclass 20, count 2 2006.257.15:43:00.42#ibcon#end of sib2, iclass 20, count 2 2006.257.15:43:00.42#ibcon#*after write, iclass 20, count 2 2006.257.15:43:00.42#ibcon#*before return 0, iclass 20, count 2 2006.257.15:43:00.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:43:00.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.15:43:00.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.15:43:00.42#ibcon#ireg 7 cls_cnt 0 2006.257.15:43:00.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:43:00.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:43:00.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:43:00.54#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:43:00.54#ibcon#first serial, iclass 20, count 0 2006.257.15:43:00.54#ibcon#enter sib2, iclass 20, count 0 2006.257.15:43:00.54#ibcon#flushed, iclass 20, count 0 2006.257.15:43:00.54#ibcon#about to write, iclass 20, count 0 2006.257.15:43:00.54#ibcon#wrote, iclass 20, count 0 2006.257.15:43:00.54#ibcon#about to read 3, iclass 20, count 0 2006.257.15:43:00.56#ibcon#read 3, iclass 20, count 0 2006.257.15:43:00.56#ibcon#about to read 4, iclass 20, count 0 2006.257.15:43:00.56#ibcon#read 4, iclass 20, count 0 2006.257.15:43:00.56#ibcon#about to read 5, iclass 20, count 0 2006.257.15:43:00.56#ibcon#read 5, iclass 20, count 0 2006.257.15:43:00.56#ibcon#about to read 6, iclass 20, count 0 2006.257.15:43:00.56#ibcon#read 6, iclass 20, count 0 2006.257.15:43:00.56#ibcon#end of sib2, iclass 20, count 0 2006.257.15:43:00.56#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:43:00.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:43:00.56#ibcon#[27=USB\r\n] 2006.257.15:43:00.56#ibcon#*before write, iclass 20, count 0 2006.257.15:43:00.56#ibcon#enter sib2, iclass 20, count 0 2006.257.15:43:00.56#ibcon#flushed, iclass 20, count 0 2006.257.15:43:00.56#ibcon#about to write, iclass 20, count 0 2006.257.15:43:00.56#ibcon#wrote, iclass 20, count 0 2006.257.15:43:00.56#ibcon#about to read 3, iclass 20, count 0 2006.257.15:43:00.59#ibcon#read 3, iclass 20, count 0 2006.257.15:43:00.59#ibcon#about to read 4, iclass 20, count 0 2006.257.15:43:00.59#ibcon#read 4, iclass 20, count 0 2006.257.15:43:00.59#ibcon#about to read 5, iclass 20, count 0 2006.257.15:43:00.59#ibcon#read 5, iclass 20, count 0 2006.257.15:43:00.59#ibcon#about to read 6, iclass 20, count 0 2006.257.15:43:00.59#ibcon#read 6, iclass 20, count 0 2006.257.15:43:00.59#ibcon#end of sib2, iclass 20, count 0 2006.257.15:43:00.59#ibcon#*after write, iclass 20, count 0 2006.257.15:43:00.59#ibcon#*before return 0, iclass 20, count 0 2006.257.15:43:00.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:43:00.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.15:43:00.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:43:00.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:43:00.59$vck44/vabw=wide 2006.257.15:43:00.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.15:43:00.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.15:43:00.59#ibcon#ireg 8 cls_cnt 0 2006.257.15:43:00.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:43:00.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:43:00.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:43:00.59#ibcon#enter wrdev, iclass 22, count 0 2006.257.15:43:00.59#ibcon#first serial, iclass 22, count 0 2006.257.15:43:00.59#ibcon#enter sib2, iclass 22, count 0 2006.257.15:43:00.59#ibcon#flushed, iclass 22, count 0 2006.257.15:43:00.59#ibcon#about to write, iclass 22, count 0 2006.257.15:43:00.59#ibcon#wrote, iclass 22, count 0 2006.257.15:43:00.59#ibcon#about to read 3, iclass 22, count 0 2006.257.15:43:00.61#ibcon#read 3, iclass 22, count 0 2006.257.15:43:00.61#ibcon#about to read 4, iclass 22, count 0 2006.257.15:43:00.61#ibcon#read 4, iclass 22, count 0 2006.257.15:43:00.61#ibcon#about to read 5, iclass 22, count 0 2006.257.15:43:00.61#ibcon#read 5, iclass 22, count 0 2006.257.15:43:00.61#ibcon#about to read 6, iclass 22, count 0 2006.257.15:43:00.61#ibcon#read 6, iclass 22, count 0 2006.257.15:43:00.61#ibcon#end of sib2, iclass 22, count 0 2006.257.15:43:00.61#ibcon#*mode == 0, iclass 22, count 0 2006.257.15:43:00.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.15:43:00.61#ibcon#[25=BW32\r\n] 2006.257.15:43:00.61#ibcon#*before write, iclass 22, count 0 2006.257.15:43:00.61#ibcon#enter sib2, iclass 22, count 0 2006.257.15:43:00.61#ibcon#flushed, iclass 22, count 0 2006.257.15:43:00.61#ibcon#about to write, iclass 22, count 0 2006.257.15:43:00.61#ibcon#wrote, iclass 22, count 0 2006.257.15:43:00.61#ibcon#about to read 3, iclass 22, count 0 2006.257.15:43:00.64#ibcon#read 3, iclass 22, count 0 2006.257.15:43:00.64#ibcon#about to read 4, iclass 22, count 0 2006.257.15:43:00.64#ibcon#read 4, iclass 22, count 0 2006.257.15:43:00.64#ibcon#about to read 5, iclass 22, count 0 2006.257.15:43:00.64#ibcon#read 5, iclass 22, count 0 2006.257.15:43:00.64#ibcon#about to read 6, iclass 22, count 0 2006.257.15:43:00.64#ibcon#read 6, iclass 22, count 0 2006.257.15:43:00.64#ibcon#end of sib2, iclass 22, count 0 2006.257.15:43:00.64#ibcon#*after write, iclass 22, count 0 2006.257.15:43:00.64#ibcon#*before return 0, iclass 22, count 0 2006.257.15:43:00.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:43:00.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.15:43:00.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.15:43:00.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.15:43:00.64$vck44/vbbw=wide 2006.257.15:43:00.64#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.15:43:00.64#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.15:43:00.64#ibcon#ireg 8 cls_cnt 0 2006.257.15:43:00.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:43:00.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:43:00.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:43:00.71#ibcon#enter wrdev, iclass 24, count 0 2006.257.15:43:00.71#ibcon#first serial, iclass 24, count 0 2006.257.15:43:00.71#ibcon#enter sib2, iclass 24, count 0 2006.257.15:43:00.71#ibcon#flushed, iclass 24, count 0 2006.257.15:43:00.71#ibcon#about to write, iclass 24, count 0 2006.257.15:43:00.71#ibcon#wrote, iclass 24, count 0 2006.257.15:43:00.71#ibcon#about to read 3, iclass 24, count 0 2006.257.15:43:00.73#ibcon#read 3, iclass 24, count 0 2006.257.15:43:00.73#ibcon#about to read 4, iclass 24, count 0 2006.257.15:43:00.73#ibcon#read 4, iclass 24, count 0 2006.257.15:43:00.73#ibcon#about to read 5, iclass 24, count 0 2006.257.15:43:00.73#ibcon#read 5, iclass 24, count 0 2006.257.15:43:00.73#ibcon#about to read 6, iclass 24, count 0 2006.257.15:43:00.73#ibcon#read 6, iclass 24, count 0 2006.257.15:43:00.73#ibcon#end of sib2, iclass 24, count 0 2006.257.15:43:00.73#ibcon#*mode == 0, iclass 24, count 0 2006.257.15:43:00.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.15:43:00.73#ibcon#[27=BW32\r\n] 2006.257.15:43:00.73#ibcon#*before write, iclass 24, count 0 2006.257.15:43:00.73#ibcon#enter sib2, iclass 24, count 0 2006.257.15:43:00.73#ibcon#flushed, iclass 24, count 0 2006.257.15:43:00.73#ibcon#about to write, iclass 24, count 0 2006.257.15:43:00.73#ibcon#wrote, iclass 24, count 0 2006.257.15:43:00.73#ibcon#about to read 3, iclass 24, count 0 2006.257.15:43:00.76#ibcon#read 3, iclass 24, count 0 2006.257.15:43:00.76#ibcon#about to read 4, iclass 24, count 0 2006.257.15:43:00.76#ibcon#read 4, iclass 24, count 0 2006.257.15:43:00.76#ibcon#about to read 5, iclass 24, count 0 2006.257.15:43:00.76#ibcon#read 5, iclass 24, count 0 2006.257.15:43:00.76#ibcon#about to read 6, iclass 24, count 0 2006.257.15:43:00.76#ibcon#read 6, iclass 24, count 0 2006.257.15:43:00.76#ibcon#end of sib2, iclass 24, count 0 2006.257.15:43:00.76#ibcon#*after write, iclass 24, count 0 2006.257.15:43:00.76#ibcon#*before return 0, iclass 24, count 0 2006.257.15:43:00.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:43:00.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:43:00.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.15:43:00.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.15:43:00.76$setupk4/ifdk4 2006.257.15:43:00.76$ifdk4/lo= 2006.257.15:43:00.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:43:00.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:43:00.77$ifdk4/patch= 2006.257.15:43:00.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:43:00.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:43:00.77$setupk4/!*+20s 2006.257.15:43:06.81#abcon#<5=/14 0.8 2.6 17.39 971013.9\r\n> 2006.257.15:43:06.83#abcon#{5=INTERFACE CLEAR} 2006.257.15:43:06.89#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:43:14.14#trakl#Source acquired 2006.257.15:43:14.14#flagr#flagr/antenna,acquired 2006.257.15:43:15.20$setupk4/"tpicd 2006.257.15:43:15.20$setupk4/echo=off 2006.257.15:43:15.20$setupk4/xlog=off 2006.257.15:43:15.20:!2006.257.15:45:01 2006.257.15:45:01.00:preob 2006.257.15:45:01.13/onsource/TRACKING 2006.257.15:45:01.13:!2006.257.15:45:11 2006.257.15:45:11.00:"tape 2006.257.15:45:11.00:"st=record 2006.257.15:45:11.00:data_valid=on 2006.257.15:45:11.00:midob 2006.257.15:45:12.13/onsource/TRACKING 2006.257.15:45:12.13/wx/17.39,1013.9,97 2006.257.15:45:12.31/cable/+6.4855E-03 2006.257.15:45:13.40/va/01,08,usb,yes,30,32 2006.257.15:45:13.40/va/02,07,usb,yes,33,33 2006.257.15:45:13.40/va/03,08,usb,yes,29,31 2006.257.15:45:13.40/va/04,07,usb,yes,34,35 2006.257.15:45:13.40/va/05,04,usb,yes,30,30 2006.257.15:45:13.40/va/06,04,usb,yes,33,33 2006.257.15:45:13.40/va/07,04,usb,yes,34,35 2006.257.15:45:13.40/va/08,04,usb,yes,29,35 2006.257.15:45:13.63/valo/01,524.99,yes,locked 2006.257.15:45:13.63/valo/02,534.99,yes,locked 2006.257.15:45:13.63/valo/03,564.99,yes,locked 2006.257.15:45:13.63/valo/04,624.99,yes,locked 2006.257.15:45:13.63/valo/05,734.99,yes,locked 2006.257.15:45:13.63/valo/06,814.99,yes,locked 2006.257.15:45:13.63/valo/07,864.99,yes,locked 2006.257.15:45:13.63/valo/08,884.99,yes,locked 2006.257.15:45:14.72/vb/01,04,usb,yes,30,28 2006.257.15:45:14.72/vb/02,05,usb,yes,28,28 2006.257.15:45:14.72/vb/03,04,usb,yes,29,32 2006.257.15:45:14.72/vb/04,05,usb,yes,29,28 2006.257.15:45:14.72/vb/05,04,usb,yes,26,28 2006.257.15:45:14.72/vb/06,04,usb,yes,30,27 2006.257.15:45:14.72/vb/07,04,usb,yes,30,30 2006.257.15:45:14.72/vb/08,04,usb,yes,28,31 2006.257.15:45:14.95/vblo/01,629.99,yes,locked 2006.257.15:45:14.95/vblo/02,634.99,yes,locked 2006.257.15:45:14.95/vblo/03,649.99,yes,locked 2006.257.15:45:14.95/vblo/04,679.99,yes,locked 2006.257.15:45:14.95/vblo/05,709.99,yes,locked 2006.257.15:45:14.95/vblo/06,719.99,yes,locked 2006.257.15:45:14.95/vblo/07,734.99,yes,locked 2006.257.15:45:14.95/vblo/08,744.99,yes,locked 2006.257.15:45:15.10/vabw/8 2006.257.15:45:15.25/vbbw/8 2006.257.15:45:15.46/xfe/off,on,15.0 2006.257.15:45:15.84/ifatt/23,28,28,28 2006.257.15:45:16.07/fmout-gps/S +4.57E-07 2006.257.15:45:16.11:!2006.257.15:47:51 2006.257.15:47:51.01:data_valid=off 2006.257.15:47:51.02:"et 2006.257.15:47:51.02:!+3s 2006.257.15:47:54.03:"tape 2006.257.15:47:54.04:postob 2006.257.15:47:54.15/cable/+6.4852E-03 2006.257.15:47:54.16/wx/17.37,1013.9,97 2006.257.15:47:54.21/fmout-gps/S +4.56E-07 2006.257.15:47:54.22:scan_name=257-1553,jd0609,80 2006.257.15:47:54.22:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.15:47:56.14#flagr#flagr/antenna,new-source 2006.257.15:47:56.15:checkk5 2006.257.15:47:56.56/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:47:56.96/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:47:57.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:47:57.76/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:47:58.14/chk_obsdata//k5ts1/T2571545??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.15:47:58.55/chk_obsdata//k5ts2/T2571545??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.15:47:58.95/chk_obsdata//k5ts3/T2571545??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.15:47:59.35/chk_obsdata//k5ts4/T2571545??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.257.15:48:00.08/k5log//k5ts1_log_newline 2006.257.15:48:00.79/k5log//k5ts2_log_newline 2006.257.15:48:01.51/k5log//k5ts3_log_newline 2006.257.15:48:02.22/k5log//k5ts4_log_newline 2006.257.15:48:02.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:48:02.24:setupk4=1 2006.257.15:48:02.24$setupk4/echo=on 2006.257.15:48:02.24$setupk4/pcalon 2006.257.15:48:02.24$pcalon/"no phase cal control is implemented here 2006.257.15:48:02.24$setupk4/"tpicd=stop 2006.257.15:48:02.24$setupk4/"rec=synch_on 2006.257.15:48:02.24$setupk4/"rec_mode=128 2006.257.15:48:02.24$setupk4/!* 2006.257.15:48:02.24$setupk4/recpk4 2006.257.15:48:02.24$recpk4/recpatch= 2006.257.15:48:02.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:48:02.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:48:02.24$setupk4/vck44 2006.257.15:48:02.24$vck44/valo=1,524.99 2006.257.15:48:02.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.15:48:02.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.15:48:02.24#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:02.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:02.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:02.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:02.25#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:48:02.25#ibcon#first serial, iclass 3, count 0 2006.257.15:48:02.25#ibcon#enter sib2, iclass 3, count 0 2006.257.15:48:02.25#ibcon#flushed, iclass 3, count 0 2006.257.15:48:02.25#ibcon#about to write, iclass 3, count 0 2006.257.15:48:02.25#ibcon#wrote, iclass 3, count 0 2006.257.15:48:02.25#ibcon#about to read 3, iclass 3, count 0 2006.257.15:48:02.26#ibcon#read 3, iclass 3, count 0 2006.257.15:48:02.26#ibcon#about to read 4, iclass 3, count 0 2006.257.15:48:02.26#ibcon#read 4, iclass 3, count 0 2006.257.15:48:02.26#ibcon#about to read 5, iclass 3, count 0 2006.257.15:48:02.26#ibcon#read 5, iclass 3, count 0 2006.257.15:48:02.26#ibcon#about to read 6, iclass 3, count 0 2006.257.15:48:02.26#ibcon#read 6, iclass 3, count 0 2006.257.15:48:02.26#ibcon#end of sib2, iclass 3, count 0 2006.257.15:48:02.26#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:48:02.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:48:02.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:48:02.26#ibcon#*before write, iclass 3, count 0 2006.257.15:48:02.26#ibcon#enter sib2, iclass 3, count 0 2006.257.15:48:02.26#ibcon#flushed, iclass 3, count 0 2006.257.15:48:02.26#ibcon#about to write, iclass 3, count 0 2006.257.15:48:02.26#ibcon#wrote, iclass 3, count 0 2006.257.15:48:02.26#ibcon#about to read 3, iclass 3, count 0 2006.257.15:48:02.31#ibcon#read 3, iclass 3, count 0 2006.257.15:48:02.31#ibcon#about to read 4, iclass 3, count 0 2006.257.15:48:02.31#ibcon#read 4, iclass 3, count 0 2006.257.15:48:02.31#ibcon#about to read 5, iclass 3, count 0 2006.257.15:48:02.31#ibcon#read 5, iclass 3, count 0 2006.257.15:48:02.31#ibcon#about to read 6, iclass 3, count 0 2006.257.15:48:02.31#ibcon#read 6, iclass 3, count 0 2006.257.15:48:02.31#ibcon#end of sib2, iclass 3, count 0 2006.257.15:48:02.31#ibcon#*after write, iclass 3, count 0 2006.257.15:48:02.31#ibcon#*before return 0, iclass 3, count 0 2006.257.15:48:02.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:02.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:02.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:48:02.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:48:02.31$vck44/va=1,8 2006.257.15:48:02.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.15:48:02.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.15:48:02.31#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:02.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:02.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:02.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:02.31#ibcon#enter wrdev, iclass 5, count 2 2006.257.15:48:02.31#ibcon#first serial, iclass 5, count 2 2006.257.15:48:02.31#ibcon#enter sib2, iclass 5, count 2 2006.257.15:48:02.31#ibcon#flushed, iclass 5, count 2 2006.257.15:48:02.31#ibcon#about to write, iclass 5, count 2 2006.257.15:48:02.31#ibcon#wrote, iclass 5, count 2 2006.257.15:48:02.31#ibcon#about to read 3, iclass 5, count 2 2006.257.15:48:02.33#ibcon#read 3, iclass 5, count 2 2006.257.15:48:02.33#ibcon#about to read 4, iclass 5, count 2 2006.257.15:48:02.33#ibcon#read 4, iclass 5, count 2 2006.257.15:48:02.33#ibcon#about to read 5, iclass 5, count 2 2006.257.15:48:02.33#ibcon#read 5, iclass 5, count 2 2006.257.15:48:02.33#ibcon#about to read 6, iclass 5, count 2 2006.257.15:48:02.33#ibcon#read 6, iclass 5, count 2 2006.257.15:48:02.33#ibcon#end of sib2, iclass 5, count 2 2006.257.15:48:02.33#ibcon#*mode == 0, iclass 5, count 2 2006.257.15:48:02.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.15:48:02.33#ibcon#[25=AT01-08\r\n] 2006.257.15:48:02.33#ibcon#*before write, iclass 5, count 2 2006.257.15:48:02.33#ibcon#enter sib2, iclass 5, count 2 2006.257.15:48:02.33#ibcon#flushed, iclass 5, count 2 2006.257.15:48:02.33#ibcon#about to write, iclass 5, count 2 2006.257.15:48:02.33#ibcon#wrote, iclass 5, count 2 2006.257.15:48:02.33#ibcon#about to read 3, iclass 5, count 2 2006.257.15:48:02.36#ibcon#read 3, iclass 5, count 2 2006.257.15:48:02.36#ibcon#about to read 4, iclass 5, count 2 2006.257.15:48:02.36#ibcon#read 4, iclass 5, count 2 2006.257.15:48:02.36#ibcon#about to read 5, iclass 5, count 2 2006.257.15:48:02.36#ibcon#read 5, iclass 5, count 2 2006.257.15:48:02.36#ibcon#about to read 6, iclass 5, count 2 2006.257.15:48:02.36#ibcon#read 6, iclass 5, count 2 2006.257.15:48:02.36#ibcon#end of sib2, iclass 5, count 2 2006.257.15:48:02.36#ibcon#*after write, iclass 5, count 2 2006.257.15:48:02.36#ibcon#*before return 0, iclass 5, count 2 2006.257.15:48:02.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:02.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:02.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.15:48:02.36#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:02.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:02.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:02.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:02.48#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:48:02.48#ibcon#first serial, iclass 5, count 0 2006.257.15:48:02.48#ibcon#enter sib2, iclass 5, count 0 2006.257.15:48:02.48#ibcon#flushed, iclass 5, count 0 2006.257.15:48:02.48#ibcon#about to write, iclass 5, count 0 2006.257.15:48:02.48#ibcon#wrote, iclass 5, count 0 2006.257.15:48:02.48#ibcon#about to read 3, iclass 5, count 0 2006.257.15:48:02.50#ibcon#read 3, iclass 5, count 0 2006.257.15:48:02.50#ibcon#about to read 4, iclass 5, count 0 2006.257.15:48:02.50#ibcon#read 4, iclass 5, count 0 2006.257.15:48:02.50#ibcon#about to read 5, iclass 5, count 0 2006.257.15:48:02.50#ibcon#read 5, iclass 5, count 0 2006.257.15:48:02.50#ibcon#about to read 6, iclass 5, count 0 2006.257.15:48:02.50#ibcon#read 6, iclass 5, count 0 2006.257.15:48:02.50#ibcon#end of sib2, iclass 5, count 0 2006.257.15:48:02.50#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:48:02.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:48:02.50#ibcon#[25=USB\r\n] 2006.257.15:48:02.50#ibcon#*before write, iclass 5, count 0 2006.257.15:48:02.50#ibcon#enter sib2, iclass 5, count 0 2006.257.15:48:02.50#ibcon#flushed, iclass 5, count 0 2006.257.15:48:02.50#ibcon#about to write, iclass 5, count 0 2006.257.15:48:02.50#ibcon#wrote, iclass 5, count 0 2006.257.15:48:02.50#ibcon#about to read 3, iclass 5, count 0 2006.257.15:48:02.53#ibcon#read 3, iclass 5, count 0 2006.257.15:48:02.53#ibcon#about to read 4, iclass 5, count 0 2006.257.15:48:02.53#ibcon#read 4, iclass 5, count 0 2006.257.15:48:02.53#ibcon#about to read 5, iclass 5, count 0 2006.257.15:48:02.53#ibcon#read 5, iclass 5, count 0 2006.257.15:48:02.53#ibcon#about to read 6, iclass 5, count 0 2006.257.15:48:02.53#ibcon#read 6, iclass 5, count 0 2006.257.15:48:02.53#ibcon#end of sib2, iclass 5, count 0 2006.257.15:48:02.53#ibcon#*after write, iclass 5, count 0 2006.257.15:48:02.53#ibcon#*before return 0, iclass 5, count 0 2006.257.15:48:02.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:02.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:02.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:48:02.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:48:02.53$vck44/valo=2,534.99 2006.257.15:48:02.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.15:48:02.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.15:48:02.53#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:02.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:02.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:02.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:02.53#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:48:02.53#ibcon#first serial, iclass 7, count 0 2006.257.15:48:02.53#ibcon#enter sib2, iclass 7, count 0 2006.257.15:48:02.53#ibcon#flushed, iclass 7, count 0 2006.257.15:48:02.53#ibcon#about to write, iclass 7, count 0 2006.257.15:48:02.53#ibcon#wrote, iclass 7, count 0 2006.257.15:48:02.53#ibcon#about to read 3, iclass 7, count 0 2006.257.15:48:02.55#ibcon#read 3, iclass 7, count 0 2006.257.15:48:02.55#ibcon#about to read 4, iclass 7, count 0 2006.257.15:48:02.55#ibcon#read 4, iclass 7, count 0 2006.257.15:48:02.55#ibcon#about to read 5, iclass 7, count 0 2006.257.15:48:02.55#ibcon#read 5, iclass 7, count 0 2006.257.15:48:02.55#ibcon#about to read 6, iclass 7, count 0 2006.257.15:48:02.55#ibcon#read 6, iclass 7, count 0 2006.257.15:48:02.55#ibcon#end of sib2, iclass 7, count 0 2006.257.15:48:02.55#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:48:02.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:48:02.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:48:02.55#ibcon#*before write, iclass 7, count 0 2006.257.15:48:02.55#ibcon#enter sib2, iclass 7, count 0 2006.257.15:48:02.55#ibcon#flushed, iclass 7, count 0 2006.257.15:48:02.55#ibcon#about to write, iclass 7, count 0 2006.257.15:48:02.55#ibcon#wrote, iclass 7, count 0 2006.257.15:48:02.55#ibcon#about to read 3, iclass 7, count 0 2006.257.15:48:02.59#ibcon#read 3, iclass 7, count 0 2006.257.15:48:02.59#ibcon#about to read 4, iclass 7, count 0 2006.257.15:48:02.59#ibcon#read 4, iclass 7, count 0 2006.257.15:48:02.59#ibcon#about to read 5, iclass 7, count 0 2006.257.15:48:02.59#ibcon#read 5, iclass 7, count 0 2006.257.15:48:02.59#ibcon#about to read 6, iclass 7, count 0 2006.257.15:48:02.59#ibcon#read 6, iclass 7, count 0 2006.257.15:48:02.59#ibcon#end of sib2, iclass 7, count 0 2006.257.15:48:02.59#ibcon#*after write, iclass 7, count 0 2006.257.15:48:02.59#ibcon#*before return 0, iclass 7, count 0 2006.257.15:48:02.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:02.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:02.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:48:02.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:48:02.59$vck44/va=2,7 2006.257.15:48:02.59#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.15:48:02.59#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.15:48:02.59#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:02.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:02.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:02.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:02.65#ibcon#enter wrdev, iclass 11, count 2 2006.257.15:48:02.65#ibcon#first serial, iclass 11, count 2 2006.257.15:48:02.65#ibcon#enter sib2, iclass 11, count 2 2006.257.15:48:02.65#ibcon#flushed, iclass 11, count 2 2006.257.15:48:02.65#ibcon#about to write, iclass 11, count 2 2006.257.15:48:02.65#ibcon#wrote, iclass 11, count 2 2006.257.15:48:02.65#ibcon#about to read 3, iclass 11, count 2 2006.257.15:48:02.67#ibcon#read 3, iclass 11, count 2 2006.257.15:48:02.67#ibcon#about to read 4, iclass 11, count 2 2006.257.15:48:02.67#ibcon#read 4, iclass 11, count 2 2006.257.15:48:02.67#ibcon#about to read 5, iclass 11, count 2 2006.257.15:48:02.67#ibcon#read 5, iclass 11, count 2 2006.257.15:48:02.67#ibcon#about to read 6, iclass 11, count 2 2006.257.15:48:02.67#ibcon#read 6, iclass 11, count 2 2006.257.15:48:02.67#ibcon#end of sib2, iclass 11, count 2 2006.257.15:48:02.67#ibcon#*mode == 0, iclass 11, count 2 2006.257.15:48:02.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.15:48:02.67#ibcon#[25=AT02-07\r\n] 2006.257.15:48:02.67#ibcon#*before write, iclass 11, count 2 2006.257.15:48:02.67#ibcon#enter sib2, iclass 11, count 2 2006.257.15:48:02.67#ibcon#flushed, iclass 11, count 2 2006.257.15:48:02.67#ibcon#about to write, iclass 11, count 2 2006.257.15:48:02.67#ibcon#wrote, iclass 11, count 2 2006.257.15:48:02.67#ibcon#about to read 3, iclass 11, count 2 2006.257.15:48:02.70#ibcon#read 3, iclass 11, count 2 2006.257.15:48:02.70#ibcon#about to read 4, iclass 11, count 2 2006.257.15:48:02.70#ibcon#read 4, iclass 11, count 2 2006.257.15:48:02.70#ibcon#about to read 5, iclass 11, count 2 2006.257.15:48:02.70#ibcon#read 5, iclass 11, count 2 2006.257.15:48:02.70#ibcon#about to read 6, iclass 11, count 2 2006.257.15:48:02.70#ibcon#read 6, iclass 11, count 2 2006.257.15:48:02.70#ibcon#end of sib2, iclass 11, count 2 2006.257.15:48:02.70#ibcon#*after write, iclass 11, count 2 2006.257.15:48:02.70#ibcon#*before return 0, iclass 11, count 2 2006.257.15:48:02.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:02.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:02.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.15:48:02.70#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:02.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:02.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:02.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:02.82#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:48:02.82#ibcon#first serial, iclass 11, count 0 2006.257.15:48:02.82#ibcon#enter sib2, iclass 11, count 0 2006.257.15:48:02.82#ibcon#flushed, iclass 11, count 0 2006.257.15:48:02.82#ibcon#about to write, iclass 11, count 0 2006.257.15:48:02.82#ibcon#wrote, iclass 11, count 0 2006.257.15:48:02.82#ibcon#about to read 3, iclass 11, count 0 2006.257.15:48:02.84#ibcon#read 3, iclass 11, count 0 2006.257.15:48:02.84#ibcon#about to read 4, iclass 11, count 0 2006.257.15:48:02.84#ibcon#read 4, iclass 11, count 0 2006.257.15:48:02.84#ibcon#about to read 5, iclass 11, count 0 2006.257.15:48:02.84#ibcon#read 5, iclass 11, count 0 2006.257.15:48:02.84#ibcon#about to read 6, iclass 11, count 0 2006.257.15:48:02.84#ibcon#read 6, iclass 11, count 0 2006.257.15:48:02.84#ibcon#end of sib2, iclass 11, count 0 2006.257.15:48:02.84#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:48:02.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:48:02.84#ibcon#[25=USB\r\n] 2006.257.15:48:02.84#ibcon#*before write, iclass 11, count 0 2006.257.15:48:02.84#ibcon#enter sib2, iclass 11, count 0 2006.257.15:48:02.84#ibcon#flushed, iclass 11, count 0 2006.257.15:48:02.84#ibcon#about to write, iclass 11, count 0 2006.257.15:48:02.84#ibcon#wrote, iclass 11, count 0 2006.257.15:48:02.84#ibcon#about to read 3, iclass 11, count 0 2006.257.15:48:02.87#ibcon#read 3, iclass 11, count 0 2006.257.15:48:02.87#ibcon#about to read 4, iclass 11, count 0 2006.257.15:48:02.87#ibcon#read 4, iclass 11, count 0 2006.257.15:48:02.87#ibcon#about to read 5, iclass 11, count 0 2006.257.15:48:02.87#ibcon#read 5, iclass 11, count 0 2006.257.15:48:02.87#ibcon#about to read 6, iclass 11, count 0 2006.257.15:48:02.87#ibcon#read 6, iclass 11, count 0 2006.257.15:48:02.87#ibcon#end of sib2, iclass 11, count 0 2006.257.15:48:02.87#ibcon#*after write, iclass 11, count 0 2006.257.15:48:02.87#ibcon#*before return 0, iclass 11, count 0 2006.257.15:48:02.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:02.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:02.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:48:02.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:48:02.87$vck44/valo=3,564.99 2006.257.15:48:02.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.15:48:02.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.15:48:02.87#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:02.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:02.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:02.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:02.87#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:48:02.87#ibcon#first serial, iclass 13, count 0 2006.257.15:48:02.87#ibcon#enter sib2, iclass 13, count 0 2006.257.15:48:02.87#ibcon#flushed, iclass 13, count 0 2006.257.15:48:02.87#ibcon#about to write, iclass 13, count 0 2006.257.15:48:02.87#ibcon#wrote, iclass 13, count 0 2006.257.15:48:02.87#ibcon#about to read 3, iclass 13, count 0 2006.257.15:48:02.89#ibcon#read 3, iclass 13, count 0 2006.257.15:48:02.89#ibcon#about to read 4, iclass 13, count 0 2006.257.15:48:02.89#ibcon#read 4, iclass 13, count 0 2006.257.15:48:02.89#ibcon#about to read 5, iclass 13, count 0 2006.257.15:48:02.89#ibcon#read 5, iclass 13, count 0 2006.257.15:48:02.89#ibcon#about to read 6, iclass 13, count 0 2006.257.15:48:02.89#ibcon#read 6, iclass 13, count 0 2006.257.15:48:02.89#ibcon#end of sib2, iclass 13, count 0 2006.257.15:48:02.89#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:48:02.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:48:02.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:48:02.89#ibcon#*before write, iclass 13, count 0 2006.257.15:48:02.89#ibcon#enter sib2, iclass 13, count 0 2006.257.15:48:02.89#ibcon#flushed, iclass 13, count 0 2006.257.15:48:02.89#ibcon#about to write, iclass 13, count 0 2006.257.15:48:02.89#ibcon#wrote, iclass 13, count 0 2006.257.15:48:02.89#ibcon#about to read 3, iclass 13, count 0 2006.257.15:48:02.93#ibcon#read 3, iclass 13, count 0 2006.257.15:48:02.93#ibcon#about to read 4, iclass 13, count 0 2006.257.15:48:02.93#ibcon#read 4, iclass 13, count 0 2006.257.15:48:02.93#ibcon#about to read 5, iclass 13, count 0 2006.257.15:48:02.93#ibcon#read 5, iclass 13, count 0 2006.257.15:48:02.93#ibcon#about to read 6, iclass 13, count 0 2006.257.15:48:02.93#ibcon#read 6, iclass 13, count 0 2006.257.15:48:02.93#ibcon#end of sib2, iclass 13, count 0 2006.257.15:48:02.93#ibcon#*after write, iclass 13, count 0 2006.257.15:48:02.93#ibcon#*before return 0, iclass 13, count 0 2006.257.15:48:02.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:02.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:02.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:48:02.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:48:02.93$vck44/va=3,8 2006.257.15:48:02.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.15:48:02.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.15:48:02.93#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:02.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:02.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:02.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:02.99#ibcon#enter wrdev, iclass 15, count 2 2006.257.15:48:02.99#ibcon#first serial, iclass 15, count 2 2006.257.15:48:02.99#ibcon#enter sib2, iclass 15, count 2 2006.257.15:48:02.99#ibcon#flushed, iclass 15, count 2 2006.257.15:48:02.99#ibcon#about to write, iclass 15, count 2 2006.257.15:48:02.99#ibcon#wrote, iclass 15, count 2 2006.257.15:48:02.99#ibcon#about to read 3, iclass 15, count 2 2006.257.15:48:03.01#ibcon#read 3, iclass 15, count 2 2006.257.15:48:03.01#ibcon#about to read 4, iclass 15, count 2 2006.257.15:48:03.01#ibcon#read 4, iclass 15, count 2 2006.257.15:48:03.01#ibcon#about to read 5, iclass 15, count 2 2006.257.15:48:03.01#ibcon#read 5, iclass 15, count 2 2006.257.15:48:03.01#ibcon#about to read 6, iclass 15, count 2 2006.257.15:48:03.01#ibcon#read 6, iclass 15, count 2 2006.257.15:48:03.01#ibcon#end of sib2, iclass 15, count 2 2006.257.15:48:03.01#ibcon#*mode == 0, iclass 15, count 2 2006.257.15:48:03.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.15:48:03.01#ibcon#[25=AT03-08\r\n] 2006.257.15:48:03.01#ibcon#*before write, iclass 15, count 2 2006.257.15:48:03.01#ibcon#enter sib2, iclass 15, count 2 2006.257.15:48:03.01#ibcon#flushed, iclass 15, count 2 2006.257.15:48:03.01#ibcon#about to write, iclass 15, count 2 2006.257.15:48:03.01#ibcon#wrote, iclass 15, count 2 2006.257.15:48:03.01#ibcon#about to read 3, iclass 15, count 2 2006.257.15:48:03.04#ibcon#read 3, iclass 15, count 2 2006.257.15:48:03.04#ibcon#about to read 4, iclass 15, count 2 2006.257.15:48:03.04#ibcon#read 4, iclass 15, count 2 2006.257.15:48:03.04#ibcon#about to read 5, iclass 15, count 2 2006.257.15:48:03.04#ibcon#read 5, iclass 15, count 2 2006.257.15:48:03.04#ibcon#about to read 6, iclass 15, count 2 2006.257.15:48:03.04#ibcon#read 6, iclass 15, count 2 2006.257.15:48:03.04#ibcon#end of sib2, iclass 15, count 2 2006.257.15:48:03.04#ibcon#*after write, iclass 15, count 2 2006.257.15:48:03.04#ibcon#*before return 0, iclass 15, count 2 2006.257.15:48:03.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:03.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:03.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.15:48:03.04#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:03.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:03.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:03.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:03.16#ibcon#enter wrdev, iclass 15, count 0 2006.257.15:48:03.16#ibcon#first serial, iclass 15, count 0 2006.257.15:48:03.16#ibcon#enter sib2, iclass 15, count 0 2006.257.15:48:03.16#ibcon#flushed, iclass 15, count 0 2006.257.15:48:03.16#ibcon#about to write, iclass 15, count 0 2006.257.15:48:03.16#ibcon#wrote, iclass 15, count 0 2006.257.15:48:03.16#ibcon#about to read 3, iclass 15, count 0 2006.257.15:48:03.18#ibcon#read 3, iclass 15, count 0 2006.257.15:48:03.18#ibcon#about to read 4, iclass 15, count 0 2006.257.15:48:03.18#ibcon#read 4, iclass 15, count 0 2006.257.15:48:03.18#ibcon#about to read 5, iclass 15, count 0 2006.257.15:48:03.18#ibcon#read 5, iclass 15, count 0 2006.257.15:48:03.18#ibcon#about to read 6, iclass 15, count 0 2006.257.15:48:03.18#ibcon#read 6, iclass 15, count 0 2006.257.15:48:03.18#ibcon#end of sib2, iclass 15, count 0 2006.257.15:48:03.18#ibcon#*mode == 0, iclass 15, count 0 2006.257.15:48:03.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.15:48:03.18#ibcon#[25=USB\r\n] 2006.257.15:48:03.18#ibcon#*before write, iclass 15, count 0 2006.257.15:48:03.18#ibcon#enter sib2, iclass 15, count 0 2006.257.15:48:03.18#ibcon#flushed, iclass 15, count 0 2006.257.15:48:03.18#ibcon#about to write, iclass 15, count 0 2006.257.15:48:03.18#ibcon#wrote, iclass 15, count 0 2006.257.15:48:03.18#ibcon#about to read 3, iclass 15, count 0 2006.257.15:48:03.21#ibcon#read 3, iclass 15, count 0 2006.257.15:48:03.21#ibcon#about to read 4, iclass 15, count 0 2006.257.15:48:03.21#ibcon#read 4, iclass 15, count 0 2006.257.15:48:03.21#ibcon#about to read 5, iclass 15, count 0 2006.257.15:48:03.21#ibcon#read 5, iclass 15, count 0 2006.257.15:48:03.21#ibcon#about to read 6, iclass 15, count 0 2006.257.15:48:03.21#ibcon#read 6, iclass 15, count 0 2006.257.15:48:03.21#ibcon#end of sib2, iclass 15, count 0 2006.257.15:48:03.21#ibcon#*after write, iclass 15, count 0 2006.257.15:48:03.21#ibcon#*before return 0, iclass 15, count 0 2006.257.15:48:03.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:03.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:03.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.15:48:03.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.15:48:03.21$vck44/valo=4,624.99 2006.257.15:48:03.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.15:48:03.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.15:48:03.21#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:03.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:03.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:03.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:03.21#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:48:03.21#ibcon#first serial, iclass 17, count 0 2006.257.15:48:03.21#ibcon#enter sib2, iclass 17, count 0 2006.257.15:48:03.21#ibcon#flushed, iclass 17, count 0 2006.257.15:48:03.21#ibcon#about to write, iclass 17, count 0 2006.257.15:48:03.21#ibcon#wrote, iclass 17, count 0 2006.257.15:48:03.21#ibcon#about to read 3, iclass 17, count 0 2006.257.15:48:03.23#ibcon#read 3, iclass 17, count 0 2006.257.15:48:03.23#ibcon#about to read 4, iclass 17, count 0 2006.257.15:48:03.23#ibcon#read 4, iclass 17, count 0 2006.257.15:48:03.23#ibcon#about to read 5, iclass 17, count 0 2006.257.15:48:03.23#ibcon#read 5, iclass 17, count 0 2006.257.15:48:03.23#ibcon#about to read 6, iclass 17, count 0 2006.257.15:48:03.23#ibcon#read 6, iclass 17, count 0 2006.257.15:48:03.23#ibcon#end of sib2, iclass 17, count 0 2006.257.15:48:03.23#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:48:03.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:48:03.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:48:03.23#ibcon#*before write, iclass 17, count 0 2006.257.15:48:03.23#ibcon#enter sib2, iclass 17, count 0 2006.257.15:48:03.23#ibcon#flushed, iclass 17, count 0 2006.257.15:48:03.23#ibcon#about to write, iclass 17, count 0 2006.257.15:48:03.23#ibcon#wrote, iclass 17, count 0 2006.257.15:48:03.23#ibcon#about to read 3, iclass 17, count 0 2006.257.15:48:03.27#ibcon#read 3, iclass 17, count 0 2006.257.15:48:03.27#ibcon#about to read 4, iclass 17, count 0 2006.257.15:48:03.27#ibcon#read 4, iclass 17, count 0 2006.257.15:48:03.27#ibcon#about to read 5, iclass 17, count 0 2006.257.15:48:03.27#ibcon#read 5, iclass 17, count 0 2006.257.15:48:03.27#ibcon#about to read 6, iclass 17, count 0 2006.257.15:48:03.27#ibcon#read 6, iclass 17, count 0 2006.257.15:48:03.27#ibcon#end of sib2, iclass 17, count 0 2006.257.15:48:03.27#ibcon#*after write, iclass 17, count 0 2006.257.15:48:03.27#ibcon#*before return 0, iclass 17, count 0 2006.257.15:48:03.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:03.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:03.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:48:03.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:48:03.27$vck44/va=4,7 2006.257.15:48:03.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.15:48:03.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.15:48:03.27#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:03.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:03.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:03.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:03.33#ibcon#enter wrdev, iclass 19, count 2 2006.257.15:48:03.33#ibcon#first serial, iclass 19, count 2 2006.257.15:48:03.33#ibcon#enter sib2, iclass 19, count 2 2006.257.15:48:03.33#ibcon#flushed, iclass 19, count 2 2006.257.15:48:03.33#ibcon#about to write, iclass 19, count 2 2006.257.15:48:03.33#ibcon#wrote, iclass 19, count 2 2006.257.15:48:03.33#ibcon#about to read 3, iclass 19, count 2 2006.257.15:48:03.35#ibcon#read 3, iclass 19, count 2 2006.257.15:48:03.35#ibcon#about to read 4, iclass 19, count 2 2006.257.15:48:03.35#ibcon#read 4, iclass 19, count 2 2006.257.15:48:03.35#ibcon#about to read 5, iclass 19, count 2 2006.257.15:48:03.35#ibcon#read 5, iclass 19, count 2 2006.257.15:48:03.35#ibcon#about to read 6, iclass 19, count 2 2006.257.15:48:03.35#ibcon#read 6, iclass 19, count 2 2006.257.15:48:03.35#ibcon#end of sib2, iclass 19, count 2 2006.257.15:48:03.35#ibcon#*mode == 0, iclass 19, count 2 2006.257.15:48:03.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.15:48:03.35#ibcon#[25=AT04-07\r\n] 2006.257.15:48:03.35#ibcon#*before write, iclass 19, count 2 2006.257.15:48:03.35#ibcon#enter sib2, iclass 19, count 2 2006.257.15:48:03.35#ibcon#flushed, iclass 19, count 2 2006.257.15:48:03.35#ibcon#about to write, iclass 19, count 2 2006.257.15:48:03.35#ibcon#wrote, iclass 19, count 2 2006.257.15:48:03.35#ibcon#about to read 3, iclass 19, count 2 2006.257.15:48:03.38#ibcon#read 3, iclass 19, count 2 2006.257.15:48:03.38#ibcon#about to read 4, iclass 19, count 2 2006.257.15:48:03.40#ibcon#read 4, iclass 19, count 2 2006.257.15:48:03.40#ibcon#about to read 5, iclass 19, count 2 2006.257.15:48:03.40#ibcon#read 5, iclass 19, count 2 2006.257.15:48:03.40#ibcon#about to read 6, iclass 19, count 2 2006.257.15:48:03.40#ibcon#read 6, iclass 19, count 2 2006.257.15:48:03.40#ibcon#end of sib2, iclass 19, count 2 2006.257.15:48:03.40#ibcon#*after write, iclass 19, count 2 2006.257.15:48:03.40#ibcon#*before return 0, iclass 19, count 2 2006.257.15:48:03.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:03.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:03.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.15:48:03.40#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:03.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:03.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:03.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:03.52#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:48:03.52#ibcon#first serial, iclass 19, count 0 2006.257.15:48:03.52#ibcon#enter sib2, iclass 19, count 0 2006.257.15:48:03.52#ibcon#flushed, iclass 19, count 0 2006.257.15:48:03.52#ibcon#about to write, iclass 19, count 0 2006.257.15:48:03.52#ibcon#wrote, iclass 19, count 0 2006.257.15:48:03.52#ibcon#about to read 3, iclass 19, count 0 2006.257.15:48:03.54#ibcon#read 3, iclass 19, count 0 2006.257.15:48:03.54#ibcon#about to read 4, iclass 19, count 0 2006.257.15:48:03.54#ibcon#read 4, iclass 19, count 0 2006.257.15:48:03.54#ibcon#about to read 5, iclass 19, count 0 2006.257.15:48:03.54#ibcon#read 5, iclass 19, count 0 2006.257.15:48:03.54#ibcon#about to read 6, iclass 19, count 0 2006.257.15:48:03.54#ibcon#read 6, iclass 19, count 0 2006.257.15:48:03.54#ibcon#end of sib2, iclass 19, count 0 2006.257.15:48:03.54#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:48:03.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:48:03.54#ibcon#[25=USB\r\n] 2006.257.15:48:03.54#ibcon#*before write, iclass 19, count 0 2006.257.15:48:03.54#ibcon#enter sib2, iclass 19, count 0 2006.257.15:48:03.54#ibcon#flushed, iclass 19, count 0 2006.257.15:48:03.54#ibcon#about to write, iclass 19, count 0 2006.257.15:48:03.54#ibcon#wrote, iclass 19, count 0 2006.257.15:48:03.54#ibcon#about to read 3, iclass 19, count 0 2006.257.15:48:03.57#ibcon#read 3, iclass 19, count 0 2006.257.15:48:03.57#ibcon#about to read 4, iclass 19, count 0 2006.257.15:48:03.57#ibcon#read 4, iclass 19, count 0 2006.257.15:48:03.57#ibcon#about to read 5, iclass 19, count 0 2006.257.15:48:03.57#ibcon#read 5, iclass 19, count 0 2006.257.15:48:03.57#ibcon#about to read 6, iclass 19, count 0 2006.257.15:48:03.57#ibcon#read 6, iclass 19, count 0 2006.257.15:48:03.57#ibcon#end of sib2, iclass 19, count 0 2006.257.15:48:03.57#ibcon#*after write, iclass 19, count 0 2006.257.15:48:03.57#ibcon#*before return 0, iclass 19, count 0 2006.257.15:48:03.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:03.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:03.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:48:03.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:48:03.57$vck44/valo=5,734.99 2006.257.15:48:03.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.15:48:03.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.15:48:03.57#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:03.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:03.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:03.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:03.57#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:48:03.57#ibcon#first serial, iclass 21, count 0 2006.257.15:48:03.57#ibcon#enter sib2, iclass 21, count 0 2006.257.15:48:03.57#ibcon#flushed, iclass 21, count 0 2006.257.15:48:03.57#ibcon#about to write, iclass 21, count 0 2006.257.15:48:03.57#ibcon#wrote, iclass 21, count 0 2006.257.15:48:03.57#ibcon#about to read 3, iclass 21, count 0 2006.257.15:48:03.59#ibcon#read 3, iclass 21, count 0 2006.257.15:48:03.59#ibcon#about to read 4, iclass 21, count 0 2006.257.15:48:03.59#ibcon#read 4, iclass 21, count 0 2006.257.15:48:03.59#ibcon#about to read 5, iclass 21, count 0 2006.257.15:48:03.59#ibcon#read 5, iclass 21, count 0 2006.257.15:48:03.59#ibcon#about to read 6, iclass 21, count 0 2006.257.15:48:03.59#ibcon#read 6, iclass 21, count 0 2006.257.15:48:03.59#ibcon#end of sib2, iclass 21, count 0 2006.257.15:48:03.59#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:48:03.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:48:03.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:48:03.59#ibcon#*before write, iclass 21, count 0 2006.257.15:48:03.59#ibcon#enter sib2, iclass 21, count 0 2006.257.15:48:03.59#ibcon#flushed, iclass 21, count 0 2006.257.15:48:03.59#ibcon#about to write, iclass 21, count 0 2006.257.15:48:03.59#ibcon#wrote, iclass 21, count 0 2006.257.15:48:03.59#ibcon#about to read 3, iclass 21, count 0 2006.257.15:48:03.63#ibcon#read 3, iclass 21, count 0 2006.257.15:48:03.63#ibcon#about to read 4, iclass 21, count 0 2006.257.15:48:03.63#ibcon#read 4, iclass 21, count 0 2006.257.15:48:03.63#ibcon#about to read 5, iclass 21, count 0 2006.257.15:48:03.63#ibcon#read 5, iclass 21, count 0 2006.257.15:48:03.63#ibcon#about to read 6, iclass 21, count 0 2006.257.15:48:03.63#ibcon#read 6, iclass 21, count 0 2006.257.15:48:03.63#ibcon#end of sib2, iclass 21, count 0 2006.257.15:48:03.63#ibcon#*after write, iclass 21, count 0 2006.257.15:48:03.63#ibcon#*before return 0, iclass 21, count 0 2006.257.15:48:03.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:03.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:03.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:48:03.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:48:03.63$vck44/va=5,4 2006.257.15:48:03.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.15:48:03.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.15:48:03.63#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:03.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:03.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:03.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:03.69#ibcon#enter wrdev, iclass 23, count 2 2006.257.15:48:03.69#ibcon#first serial, iclass 23, count 2 2006.257.15:48:03.69#ibcon#enter sib2, iclass 23, count 2 2006.257.15:48:03.69#ibcon#flushed, iclass 23, count 2 2006.257.15:48:03.69#ibcon#about to write, iclass 23, count 2 2006.257.15:48:03.69#ibcon#wrote, iclass 23, count 2 2006.257.15:48:03.69#ibcon#about to read 3, iclass 23, count 2 2006.257.15:48:03.71#ibcon#read 3, iclass 23, count 2 2006.257.15:48:03.71#ibcon#about to read 4, iclass 23, count 2 2006.257.15:48:03.71#ibcon#read 4, iclass 23, count 2 2006.257.15:48:03.71#ibcon#about to read 5, iclass 23, count 2 2006.257.15:48:03.71#ibcon#read 5, iclass 23, count 2 2006.257.15:48:03.71#ibcon#about to read 6, iclass 23, count 2 2006.257.15:48:03.71#ibcon#read 6, iclass 23, count 2 2006.257.15:48:03.71#ibcon#end of sib2, iclass 23, count 2 2006.257.15:48:03.71#ibcon#*mode == 0, iclass 23, count 2 2006.257.15:48:03.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.15:48:03.71#ibcon#[25=AT05-04\r\n] 2006.257.15:48:03.71#ibcon#*before write, iclass 23, count 2 2006.257.15:48:03.71#ibcon#enter sib2, iclass 23, count 2 2006.257.15:48:03.71#ibcon#flushed, iclass 23, count 2 2006.257.15:48:03.71#ibcon#about to write, iclass 23, count 2 2006.257.15:48:03.71#ibcon#wrote, iclass 23, count 2 2006.257.15:48:03.71#ibcon#about to read 3, iclass 23, count 2 2006.257.15:48:03.74#ibcon#read 3, iclass 23, count 2 2006.257.15:48:03.74#ibcon#about to read 4, iclass 23, count 2 2006.257.15:48:03.74#ibcon#read 4, iclass 23, count 2 2006.257.15:48:03.74#ibcon#about to read 5, iclass 23, count 2 2006.257.15:48:03.74#ibcon#read 5, iclass 23, count 2 2006.257.15:48:03.74#ibcon#about to read 6, iclass 23, count 2 2006.257.15:48:03.74#ibcon#read 6, iclass 23, count 2 2006.257.15:48:03.74#ibcon#end of sib2, iclass 23, count 2 2006.257.15:48:03.74#ibcon#*after write, iclass 23, count 2 2006.257.15:48:03.74#ibcon#*before return 0, iclass 23, count 2 2006.257.15:48:03.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:03.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:03.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.15:48:03.74#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:03.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:03.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:03.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:03.86#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:48:03.86#ibcon#first serial, iclass 23, count 0 2006.257.15:48:03.86#ibcon#enter sib2, iclass 23, count 0 2006.257.15:48:03.86#ibcon#flushed, iclass 23, count 0 2006.257.15:48:03.86#ibcon#about to write, iclass 23, count 0 2006.257.15:48:03.86#ibcon#wrote, iclass 23, count 0 2006.257.15:48:03.86#ibcon#about to read 3, iclass 23, count 0 2006.257.15:48:03.88#ibcon#read 3, iclass 23, count 0 2006.257.15:48:03.88#ibcon#about to read 4, iclass 23, count 0 2006.257.15:48:03.88#ibcon#read 4, iclass 23, count 0 2006.257.15:48:03.88#ibcon#about to read 5, iclass 23, count 0 2006.257.15:48:03.88#ibcon#read 5, iclass 23, count 0 2006.257.15:48:03.88#ibcon#about to read 6, iclass 23, count 0 2006.257.15:48:03.88#ibcon#read 6, iclass 23, count 0 2006.257.15:48:03.88#ibcon#end of sib2, iclass 23, count 0 2006.257.15:48:03.88#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:48:03.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:48:03.88#ibcon#[25=USB\r\n] 2006.257.15:48:03.88#ibcon#*before write, iclass 23, count 0 2006.257.15:48:03.88#ibcon#enter sib2, iclass 23, count 0 2006.257.15:48:03.88#ibcon#flushed, iclass 23, count 0 2006.257.15:48:03.88#ibcon#about to write, iclass 23, count 0 2006.257.15:48:03.88#ibcon#wrote, iclass 23, count 0 2006.257.15:48:03.88#ibcon#about to read 3, iclass 23, count 0 2006.257.15:48:03.91#ibcon#read 3, iclass 23, count 0 2006.257.15:48:03.91#ibcon#about to read 4, iclass 23, count 0 2006.257.15:48:03.91#ibcon#read 4, iclass 23, count 0 2006.257.15:48:03.91#ibcon#about to read 5, iclass 23, count 0 2006.257.15:48:03.91#ibcon#read 5, iclass 23, count 0 2006.257.15:48:03.91#ibcon#about to read 6, iclass 23, count 0 2006.257.15:48:03.91#ibcon#read 6, iclass 23, count 0 2006.257.15:48:03.91#ibcon#end of sib2, iclass 23, count 0 2006.257.15:48:03.91#ibcon#*after write, iclass 23, count 0 2006.257.15:48:03.91#ibcon#*before return 0, iclass 23, count 0 2006.257.15:48:03.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:03.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:03.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:48:03.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:48:03.91$vck44/valo=6,814.99 2006.257.15:48:03.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.15:48:03.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.15:48:03.91#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:03.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:03.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:03.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:03.91#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:48:03.91#ibcon#first serial, iclass 25, count 0 2006.257.15:48:03.91#ibcon#enter sib2, iclass 25, count 0 2006.257.15:48:03.91#ibcon#flushed, iclass 25, count 0 2006.257.15:48:03.91#ibcon#about to write, iclass 25, count 0 2006.257.15:48:03.91#ibcon#wrote, iclass 25, count 0 2006.257.15:48:03.91#ibcon#about to read 3, iclass 25, count 0 2006.257.15:48:03.93#ibcon#read 3, iclass 25, count 0 2006.257.15:48:03.93#ibcon#about to read 4, iclass 25, count 0 2006.257.15:48:03.93#ibcon#read 4, iclass 25, count 0 2006.257.15:48:03.93#ibcon#about to read 5, iclass 25, count 0 2006.257.15:48:03.93#ibcon#read 5, iclass 25, count 0 2006.257.15:48:03.93#ibcon#about to read 6, iclass 25, count 0 2006.257.15:48:03.93#ibcon#read 6, iclass 25, count 0 2006.257.15:48:03.93#ibcon#end of sib2, iclass 25, count 0 2006.257.15:48:03.93#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:48:03.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:48:03.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:48:03.93#ibcon#*before write, iclass 25, count 0 2006.257.15:48:03.93#ibcon#enter sib2, iclass 25, count 0 2006.257.15:48:03.93#ibcon#flushed, iclass 25, count 0 2006.257.15:48:03.93#ibcon#about to write, iclass 25, count 0 2006.257.15:48:03.93#ibcon#wrote, iclass 25, count 0 2006.257.15:48:03.93#ibcon#about to read 3, iclass 25, count 0 2006.257.15:48:03.97#ibcon#read 3, iclass 25, count 0 2006.257.15:48:03.97#ibcon#about to read 4, iclass 25, count 0 2006.257.15:48:03.97#ibcon#read 4, iclass 25, count 0 2006.257.15:48:03.97#ibcon#about to read 5, iclass 25, count 0 2006.257.15:48:03.97#ibcon#read 5, iclass 25, count 0 2006.257.15:48:03.97#ibcon#about to read 6, iclass 25, count 0 2006.257.15:48:03.97#ibcon#read 6, iclass 25, count 0 2006.257.15:48:03.97#ibcon#end of sib2, iclass 25, count 0 2006.257.15:48:03.97#ibcon#*after write, iclass 25, count 0 2006.257.15:48:03.97#ibcon#*before return 0, iclass 25, count 0 2006.257.15:48:03.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:03.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:03.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:48:03.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:48:03.97$vck44/va=6,4 2006.257.15:48:03.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.15:48:03.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.15:48:03.97#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:03.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:04.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:04.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:04.03#ibcon#enter wrdev, iclass 27, count 2 2006.257.15:48:04.03#ibcon#first serial, iclass 27, count 2 2006.257.15:48:04.03#ibcon#enter sib2, iclass 27, count 2 2006.257.15:48:04.03#ibcon#flushed, iclass 27, count 2 2006.257.15:48:04.03#ibcon#about to write, iclass 27, count 2 2006.257.15:48:04.03#ibcon#wrote, iclass 27, count 2 2006.257.15:48:04.03#ibcon#about to read 3, iclass 27, count 2 2006.257.15:48:04.05#ibcon#read 3, iclass 27, count 2 2006.257.15:48:04.05#ibcon#about to read 4, iclass 27, count 2 2006.257.15:48:04.05#ibcon#read 4, iclass 27, count 2 2006.257.15:48:04.05#ibcon#about to read 5, iclass 27, count 2 2006.257.15:48:04.05#ibcon#read 5, iclass 27, count 2 2006.257.15:48:04.05#ibcon#about to read 6, iclass 27, count 2 2006.257.15:48:04.05#ibcon#read 6, iclass 27, count 2 2006.257.15:48:04.05#ibcon#end of sib2, iclass 27, count 2 2006.257.15:48:04.05#ibcon#*mode == 0, iclass 27, count 2 2006.257.15:48:04.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.15:48:04.05#ibcon#[25=AT06-04\r\n] 2006.257.15:48:04.05#ibcon#*before write, iclass 27, count 2 2006.257.15:48:04.05#ibcon#enter sib2, iclass 27, count 2 2006.257.15:48:04.05#ibcon#flushed, iclass 27, count 2 2006.257.15:48:04.05#ibcon#about to write, iclass 27, count 2 2006.257.15:48:04.05#ibcon#wrote, iclass 27, count 2 2006.257.15:48:04.05#ibcon#about to read 3, iclass 27, count 2 2006.257.15:48:04.08#ibcon#read 3, iclass 27, count 2 2006.257.15:48:04.08#ibcon#about to read 4, iclass 27, count 2 2006.257.15:48:04.08#ibcon#read 4, iclass 27, count 2 2006.257.15:48:04.08#ibcon#about to read 5, iclass 27, count 2 2006.257.15:48:04.08#ibcon#read 5, iclass 27, count 2 2006.257.15:48:04.08#ibcon#about to read 6, iclass 27, count 2 2006.257.15:48:04.08#ibcon#read 6, iclass 27, count 2 2006.257.15:48:04.08#ibcon#end of sib2, iclass 27, count 2 2006.257.15:48:04.08#ibcon#*after write, iclass 27, count 2 2006.257.15:48:04.08#ibcon#*before return 0, iclass 27, count 2 2006.257.15:48:04.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:04.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:04.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.15:48:04.08#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:04.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:04.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:04.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:04.20#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:48:04.20#ibcon#first serial, iclass 27, count 0 2006.257.15:48:04.20#ibcon#enter sib2, iclass 27, count 0 2006.257.15:48:04.20#ibcon#flushed, iclass 27, count 0 2006.257.15:48:04.20#ibcon#about to write, iclass 27, count 0 2006.257.15:48:04.20#ibcon#wrote, iclass 27, count 0 2006.257.15:48:04.20#ibcon#about to read 3, iclass 27, count 0 2006.257.15:48:04.22#ibcon#read 3, iclass 27, count 0 2006.257.15:48:04.22#ibcon#about to read 4, iclass 27, count 0 2006.257.15:48:04.22#ibcon#read 4, iclass 27, count 0 2006.257.15:48:04.22#ibcon#about to read 5, iclass 27, count 0 2006.257.15:48:04.22#ibcon#read 5, iclass 27, count 0 2006.257.15:48:04.22#ibcon#about to read 6, iclass 27, count 0 2006.257.15:48:04.22#ibcon#read 6, iclass 27, count 0 2006.257.15:48:04.22#ibcon#end of sib2, iclass 27, count 0 2006.257.15:48:04.22#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:48:04.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:48:04.22#ibcon#[25=USB\r\n] 2006.257.15:48:04.22#ibcon#*before write, iclass 27, count 0 2006.257.15:48:04.22#ibcon#enter sib2, iclass 27, count 0 2006.257.15:48:04.22#ibcon#flushed, iclass 27, count 0 2006.257.15:48:04.22#ibcon#about to write, iclass 27, count 0 2006.257.15:48:04.22#ibcon#wrote, iclass 27, count 0 2006.257.15:48:04.22#ibcon#about to read 3, iclass 27, count 0 2006.257.15:48:04.25#ibcon#read 3, iclass 27, count 0 2006.257.15:48:04.25#ibcon#about to read 4, iclass 27, count 0 2006.257.15:48:04.25#ibcon#read 4, iclass 27, count 0 2006.257.15:48:04.25#ibcon#about to read 5, iclass 27, count 0 2006.257.15:48:04.25#ibcon#read 5, iclass 27, count 0 2006.257.15:48:04.25#ibcon#about to read 6, iclass 27, count 0 2006.257.15:48:04.25#ibcon#read 6, iclass 27, count 0 2006.257.15:48:04.25#ibcon#end of sib2, iclass 27, count 0 2006.257.15:48:04.25#ibcon#*after write, iclass 27, count 0 2006.257.15:48:04.25#ibcon#*before return 0, iclass 27, count 0 2006.257.15:48:04.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:04.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:04.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:48:04.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:48:04.25$vck44/valo=7,864.99 2006.257.15:48:04.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.15:48:04.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.15:48:04.25#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:04.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:04.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:04.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:04.25#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:48:04.25#ibcon#first serial, iclass 29, count 0 2006.257.15:48:04.25#ibcon#enter sib2, iclass 29, count 0 2006.257.15:48:04.25#ibcon#flushed, iclass 29, count 0 2006.257.15:48:04.25#ibcon#about to write, iclass 29, count 0 2006.257.15:48:04.25#ibcon#wrote, iclass 29, count 0 2006.257.15:48:04.25#ibcon#about to read 3, iclass 29, count 0 2006.257.15:48:04.27#ibcon#read 3, iclass 29, count 0 2006.257.15:48:04.27#ibcon#about to read 4, iclass 29, count 0 2006.257.15:48:04.27#ibcon#read 4, iclass 29, count 0 2006.257.15:48:04.27#ibcon#about to read 5, iclass 29, count 0 2006.257.15:48:04.27#ibcon#read 5, iclass 29, count 0 2006.257.15:48:04.27#ibcon#about to read 6, iclass 29, count 0 2006.257.15:48:04.27#ibcon#read 6, iclass 29, count 0 2006.257.15:48:04.27#ibcon#end of sib2, iclass 29, count 0 2006.257.15:48:04.27#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:48:04.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:48:04.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:48:04.27#ibcon#*before write, iclass 29, count 0 2006.257.15:48:04.27#ibcon#enter sib2, iclass 29, count 0 2006.257.15:48:04.27#ibcon#flushed, iclass 29, count 0 2006.257.15:48:04.27#ibcon#about to write, iclass 29, count 0 2006.257.15:48:04.27#ibcon#wrote, iclass 29, count 0 2006.257.15:48:04.27#ibcon#about to read 3, iclass 29, count 0 2006.257.15:48:04.31#ibcon#read 3, iclass 29, count 0 2006.257.15:48:04.31#ibcon#about to read 4, iclass 29, count 0 2006.257.15:48:04.31#ibcon#read 4, iclass 29, count 0 2006.257.15:48:04.31#ibcon#about to read 5, iclass 29, count 0 2006.257.15:48:04.31#ibcon#read 5, iclass 29, count 0 2006.257.15:48:04.31#ibcon#about to read 6, iclass 29, count 0 2006.257.15:48:04.31#ibcon#read 6, iclass 29, count 0 2006.257.15:48:04.31#ibcon#end of sib2, iclass 29, count 0 2006.257.15:48:04.31#ibcon#*after write, iclass 29, count 0 2006.257.15:48:04.31#ibcon#*before return 0, iclass 29, count 0 2006.257.15:48:04.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:04.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:04.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:48:04.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:48:04.31$vck44/va=7,4 2006.257.15:48:04.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.15:48:04.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.15:48:04.31#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:04.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:04.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:04.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:04.37#ibcon#enter wrdev, iclass 31, count 2 2006.257.15:48:04.37#ibcon#first serial, iclass 31, count 2 2006.257.15:48:04.37#ibcon#enter sib2, iclass 31, count 2 2006.257.15:48:04.37#ibcon#flushed, iclass 31, count 2 2006.257.15:48:04.37#ibcon#about to write, iclass 31, count 2 2006.257.15:48:04.37#ibcon#wrote, iclass 31, count 2 2006.257.15:48:04.37#ibcon#about to read 3, iclass 31, count 2 2006.257.15:48:04.39#ibcon#read 3, iclass 31, count 2 2006.257.15:48:04.39#ibcon#about to read 4, iclass 31, count 2 2006.257.15:48:04.39#ibcon#read 4, iclass 31, count 2 2006.257.15:48:04.39#ibcon#about to read 5, iclass 31, count 2 2006.257.15:48:04.39#ibcon#read 5, iclass 31, count 2 2006.257.15:48:04.39#ibcon#about to read 6, iclass 31, count 2 2006.257.15:48:04.39#ibcon#read 6, iclass 31, count 2 2006.257.15:48:04.39#ibcon#end of sib2, iclass 31, count 2 2006.257.15:48:04.39#ibcon#*mode == 0, iclass 31, count 2 2006.257.15:48:04.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.15:48:04.39#ibcon#[25=AT07-04\r\n] 2006.257.15:48:04.39#ibcon#*before write, iclass 31, count 2 2006.257.15:48:04.39#ibcon#enter sib2, iclass 31, count 2 2006.257.15:48:04.39#ibcon#flushed, iclass 31, count 2 2006.257.15:48:04.39#ibcon#about to write, iclass 31, count 2 2006.257.15:48:04.39#ibcon#wrote, iclass 31, count 2 2006.257.15:48:04.39#ibcon#about to read 3, iclass 31, count 2 2006.257.15:48:04.42#ibcon#read 3, iclass 31, count 2 2006.257.15:48:04.42#ibcon#about to read 4, iclass 31, count 2 2006.257.15:48:04.42#ibcon#read 4, iclass 31, count 2 2006.257.15:48:04.42#ibcon#about to read 5, iclass 31, count 2 2006.257.15:48:04.42#ibcon#read 5, iclass 31, count 2 2006.257.15:48:04.42#ibcon#about to read 6, iclass 31, count 2 2006.257.15:48:04.42#ibcon#read 6, iclass 31, count 2 2006.257.15:48:04.42#ibcon#end of sib2, iclass 31, count 2 2006.257.15:48:04.42#ibcon#*after write, iclass 31, count 2 2006.257.15:48:04.45#ibcon#*before return 0, iclass 31, count 2 2006.257.15:48:04.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:04.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:04.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.15:48:04.46#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:04.46#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:04.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:04.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:04.56#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:48:04.56#ibcon#first serial, iclass 31, count 0 2006.257.15:48:04.56#ibcon#enter sib2, iclass 31, count 0 2006.257.15:48:04.56#ibcon#flushed, iclass 31, count 0 2006.257.15:48:04.56#ibcon#about to write, iclass 31, count 0 2006.257.15:48:04.56#ibcon#wrote, iclass 31, count 0 2006.257.15:48:04.56#ibcon#about to read 3, iclass 31, count 0 2006.257.15:48:04.58#ibcon#read 3, iclass 31, count 0 2006.257.15:48:04.58#ibcon#about to read 4, iclass 31, count 0 2006.257.15:48:04.58#ibcon#read 4, iclass 31, count 0 2006.257.15:48:04.58#ibcon#about to read 5, iclass 31, count 0 2006.257.15:48:04.58#ibcon#read 5, iclass 31, count 0 2006.257.15:48:04.58#ibcon#about to read 6, iclass 31, count 0 2006.257.15:48:04.58#ibcon#read 6, iclass 31, count 0 2006.257.15:48:04.58#ibcon#end of sib2, iclass 31, count 0 2006.257.15:48:04.58#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:48:04.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:48:04.58#ibcon#[25=USB\r\n] 2006.257.15:48:04.58#ibcon#*before write, iclass 31, count 0 2006.257.15:48:04.58#ibcon#enter sib2, iclass 31, count 0 2006.257.15:48:04.58#ibcon#flushed, iclass 31, count 0 2006.257.15:48:04.58#ibcon#about to write, iclass 31, count 0 2006.257.15:48:04.58#ibcon#wrote, iclass 31, count 0 2006.257.15:48:04.58#ibcon#about to read 3, iclass 31, count 0 2006.257.15:48:04.61#ibcon#read 3, iclass 31, count 0 2006.257.15:48:04.61#ibcon#about to read 4, iclass 31, count 0 2006.257.15:48:04.61#ibcon#read 4, iclass 31, count 0 2006.257.15:48:04.61#ibcon#about to read 5, iclass 31, count 0 2006.257.15:48:04.61#ibcon#read 5, iclass 31, count 0 2006.257.15:48:04.61#ibcon#about to read 6, iclass 31, count 0 2006.257.15:48:04.61#ibcon#read 6, iclass 31, count 0 2006.257.15:48:04.61#ibcon#end of sib2, iclass 31, count 0 2006.257.15:48:04.61#ibcon#*after write, iclass 31, count 0 2006.257.15:48:04.61#ibcon#*before return 0, iclass 31, count 0 2006.257.15:48:04.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:04.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:04.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:48:04.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:48:04.61$vck44/valo=8,884.99 2006.257.15:48:04.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.15:48:04.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.15:48:04.61#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:04.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:04.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:04.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:04.61#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:48:04.61#ibcon#first serial, iclass 33, count 0 2006.257.15:48:04.61#ibcon#enter sib2, iclass 33, count 0 2006.257.15:48:04.61#ibcon#flushed, iclass 33, count 0 2006.257.15:48:04.61#ibcon#about to write, iclass 33, count 0 2006.257.15:48:04.61#ibcon#wrote, iclass 33, count 0 2006.257.15:48:04.61#ibcon#about to read 3, iclass 33, count 0 2006.257.15:48:04.63#ibcon#read 3, iclass 33, count 0 2006.257.15:48:04.63#ibcon#about to read 4, iclass 33, count 0 2006.257.15:48:04.63#ibcon#read 4, iclass 33, count 0 2006.257.15:48:04.63#ibcon#about to read 5, iclass 33, count 0 2006.257.15:48:04.63#ibcon#read 5, iclass 33, count 0 2006.257.15:48:04.63#ibcon#about to read 6, iclass 33, count 0 2006.257.15:48:04.63#ibcon#read 6, iclass 33, count 0 2006.257.15:48:04.63#ibcon#end of sib2, iclass 33, count 0 2006.257.15:48:04.63#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:48:04.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:48:04.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:48:04.63#ibcon#*before write, iclass 33, count 0 2006.257.15:48:04.63#ibcon#enter sib2, iclass 33, count 0 2006.257.15:48:04.63#ibcon#flushed, iclass 33, count 0 2006.257.15:48:04.63#ibcon#about to write, iclass 33, count 0 2006.257.15:48:04.63#ibcon#wrote, iclass 33, count 0 2006.257.15:48:04.63#ibcon#about to read 3, iclass 33, count 0 2006.257.15:48:04.67#ibcon#read 3, iclass 33, count 0 2006.257.15:48:04.67#ibcon#about to read 4, iclass 33, count 0 2006.257.15:48:04.67#ibcon#read 4, iclass 33, count 0 2006.257.15:48:04.67#ibcon#about to read 5, iclass 33, count 0 2006.257.15:48:04.67#ibcon#read 5, iclass 33, count 0 2006.257.15:48:04.67#ibcon#about to read 6, iclass 33, count 0 2006.257.15:48:04.67#ibcon#read 6, iclass 33, count 0 2006.257.15:48:04.67#ibcon#end of sib2, iclass 33, count 0 2006.257.15:48:04.67#ibcon#*after write, iclass 33, count 0 2006.257.15:48:04.67#ibcon#*before return 0, iclass 33, count 0 2006.257.15:48:04.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:04.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:04.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:48:04.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:48:04.67$vck44/va=8,4 2006.257.15:48:04.67#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.15:48:04.67#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.15:48:04.67#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:04.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:48:04.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:48:04.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:48:04.73#ibcon#enter wrdev, iclass 35, count 2 2006.257.15:48:04.73#ibcon#first serial, iclass 35, count 2 2006.257.15:48:04.73#ibcon#enter sib2, iclass 35, count 2 2006.257.15:48:04.73#ibcon#flushed, iclass 35, count 2 2006.257.15:48:04.73#ibcon#about to write, iclass 35, count 2 2006.257.15:48:04.73#ibcon#wrote, iclass 35, count 2 2006.257.15:48:04.73#ibcon#about to read 3, iclass 35, count 2 2006.257.15:48:04.75#ibcon#read 3, iclass 35, count 2 2006.257.15:48:04.75#ibcon#about to read 4, iclass 35, count 2 2006.257.15:48:04.75#ibcon#read 4, iclass 35, count 2 2006.257.15:48:04.75#ibcon#about to read 5, iclass 35, count 2 2006.257.15:48:04.75#ibcon#read 5, iclass 35, count 2 2006.257.15:48:04.75#ibcon#about to read 6, iclass 35, count 2 2006.257.15:48:04.75#ibcon#read 6, iclass 35, count 2 2006.257.15:48:04.75#ibcon#end of sib2, iclass 35, count 2 2006.257.15:48:04.75#ibcon#*mode == 0, iclass 35, count 2 2006.257.15:48:04.75#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.15:48:04.75#ibcon#[25=AT08-04\r\n] 2006.257.15:48:04.75#ibcon#*before write, iclass 35, count 2 2006.257.15:48:04.75#ibcon#enter sib2, iclass 35, count 2 2006.257.15:48:04.75#ibcon#flushed, iclass 35, count 2 2006.257.15:48:04.75#ibcon#about to write, iclass 35, count 2 2006.257.15:48:04.75#ibcon#wrote, iclass 35, count 2 2006.257.15:48:04.75#ibcon#about to read 3, iclass 35, count 2 2006.257.15:48:04.78#ibcon#read 3, iclass 35, count 2 2006.257.15:48:04.78#ibcon#about to read 4, iclass 35, count 2 2006.257.15:48:04.78#ibcon#read 4, iclass 35, count 2 2006.257.15:48:04.78#ibcon#about to read 5, iclass 35, count 2 2006.257.15:48:04.78#ibcon#read 5, iclass 35, count 2 2006.257.15:48:04.78#ibcon#about to read 6, iclass 35, count 2 2006.257.15:48:04.78#ibcon#read 6, iclass 35, count 2 2006.257.15:48:04.78#ibcon#end of sib2, iclass 35, count 2 2006.257.15:48:04.78#ibcon#*after write, iclass 35, count 2 2006.257.15:48:04.78#ibcon#*before return 0, iclass 35, count 2 2006.257.15:48:04.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:48:04.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.15:48:04.78#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.15:48:04.78#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:04.78#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:48:04.90#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:48:04.90#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:48:04.90#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:48:04.90#ibcon#first serial, iclass 35, count 0 2006.257.15:48:04.90#ibcon#enter sib2, iclass 35, count 0 2006.257.15:48:04.90#ibcon#flushed, iclass 35, count 0 2006.257.15:48:04.90#ibcon#about to write, iclass 35, count 0 2006.257.15:48:04.90#ibcon#wrote, iclass 35, count 0 2006.257.15:48:04.90#ibcon#about to read 3, iclass 35, count 0 2006.257.15:48:04.92#ibcon#read 3, iclass 35, count 0 2006.257.15:48:04.92#ibcon#about to read 4, iclass 35, count 0 2006.257.15:48:04.92#ibcon#read 4, iclass 35, count 0 2006.257.15:48:04.92#ibcon#about to read 5, iclass 35, count 0 2006.257.15:48:04.92#ibcon#read 5, iclass 35, count 0 2006.257.15:48:04.92#ibcon#about to read 6, iclass 35, count 0 2006.257.15:48:04.92#ibcon#read 6, iclass 35, count 0 2006.257.15:48:04.92#ibcon#end of sib2, iclass 35, count 0 2006.257.15:48:04.92#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:48:04.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:48:04.92#ibcon#[25=USB\r\n] 2006.257.15:48:04.92#ibcon#*before write, iclass 35, count 0 2006.257.15:48:04.92#ibcon#enter sib2, iclass 35, count 0 2006.257.15:48:04.92#ibcon#flushed, iclass 35, count 0 2006.257.15:48:04.92#ibcon#about to write, iclass 35, count 0 2006.257.15:48:04.92#ibcon#wrote, iclass 35, count 0 2006.257.15:48:04.92#ibcon#about to read 3, iclass 35, count 0 2006.257.15:48:04.95#ibcon#read 3, iclass 35, count 0 2006.257.15:48:04.95#ibcon#about to read 4, iclass 35, count 0 2006.257.15:48:04.95#ibcon#read 4, iclass 35, count 0 2006.257.15:48:04.95#ibcon#about to read 5, iclass 35, count 0 2006.257.15:48:04.95#ibcon#read 5, iclass 35, count 0 2006.257.15:48:04.95#ibcon#about to read 6, iclass 35, count 0 2006.257.15:48:04.95#ibcon#read 6, iclass 35, count 0 2006.257.15:48:04.95#ibcon#end of sib2, iclass 35, count 0 2006.257.15:48:04.95#ibcon#*after write, iclass 35, count 0 2006.257.15:48:04.95#ibcon#*before return 0, iclass 35, count 0 2006.257.15:48:04.95#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:48:04.95#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.15:48:04.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:48:04.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:48:04.95$vck44/vblo=1,629.99 2006.257.15:48:04.95#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.15:48:04.95#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.15:48:04.95#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:04.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:48:04.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:48:04.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:48:04.95#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:48:04.95#ibcon#first serial, iclass 37, count 0 2006.257.15:48:04.95#ibcon#enter sib2, iclass 37, count 0 2006.257.15:48:04.95#ibcon#flushed, iclass 37, count 0 2006.257.15:48:04.95#ibcon#about to write, iclass 37, count 0 2006.257.15:48:04.95#ibcon#wrote, iclass 37, count 0 2006.257.15:48:04.95#ibcon#about to read 3, iclass 37, count 0 2006.257.15:48:04.97#ibcon#read 3, iclass 37, count 0 2006.257.15:48:04.97#ibcon#about to read 4, iclass 37, count 0 2006.257.15:48:04.97#ibcon#read 4, iclass 37, count 0 2006.257.15:48:04.97#ibcon#about to read 5, iclass 37, count 0 2006.257.15:48:04.97#ibcon#read 5, iclass 37, count 0 2006.257.15:48:04.97#ibcon#about to read 6, iclass 37, count 0 2006.257.15:48:04.97#ibcon#read 6, iclass 37, count 0 2006.257.15:48:04.97#ibcon#end of sib2, iclass 37, count 0 2006.257.15:48:04.97#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:48:04.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:48:04.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:48:04.97#ibcon#*before write, iclass 37, count 0 2006.257.15:48:04.97#ibcon#enter sib2, iclass 37, count 0 2006.257.15:48:04.97#ibcon#flushed, iclass 37, count 0 2006.257.15:48:04.97#ibcon#about to write, iclass 37, count 0 2006.257.15:48:04.97#ibcon#wrote, iclass 37, count 0 2006.257.15:48:04.97#ibcon#about to read 3, iclass 37, count 0 2006.257.15:48:05.01#ibcon#read 3, iclass 37, count 0 2006.257.15:48:05.01#ibcon#about to read 4, iclass 37, count 0 2006.257.15:48:05.01#ibcon#read 4, iclass 37, count 0 2006.257.15:48:05.01#ibcon#about to read 5, iclass 37, count 0 2006.257.15:48:05.01#ibcon#read 5, iclass 37, count 0 2006.257.15:48:05.01#ibcon#about to read 6, iclass 37, count 0 2006.257.15:48:05.01#ibcon#read 6, iclass 37, count 0 2006.257.15:48:05.01#ibcon#end of sib2, iclass 37, count 0 2006.257.15:48:05.01#ibcon#*after write, iclass 37, count 0 2006.257.15:48:05.01#ibcon#*before return 0, iclass 37, count 0 2006.257.15:48:05.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:48:05.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.15:48:05.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:48:05.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:48:05.01$vck44/vb=1,4 2006.257.15:48:05.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.15:48:05.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.15:48:05.01#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:05.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:48:05.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:48:05.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:48:05.01#ibcon#enter wrdev, iclass 39, count 2 2006.257.15:48:05.01#ibcon#first serial, iclass 39, count 2 2006.257.15:48:05.01#ibcon#enter sib2, iclass 39, count 2 2006.257.15:48:05.01#ibcon#flushed, iclass 39, count 2 2006.257.15:48:05.01#ibcon#about to write, iclass 39, count 2 2006.257.15:48:05.01#ibcon#wrote, iclass 39, count 2 2006.257.15:48:05.01#ibcon#about to read 3, iclass 39, count 2 2006.257.15:48:05.03#ibcon#read 3, iclass 39, count 2 2006.257.15:48:05.03#ibcon#about to read 4, iclass 39, count 2 2006.257.15:48:05.03#ibcon#read 4, iclass 39, count 2 2006.257.15:48:05.03#ibcon#about to read 5, iclass 39, count 2 2006.257.15:48:05.03#ibcon#read 5, iclass 39, count 2 2006.257.15:48:05.03#ibcon#about to read 6, iclass 39, count 2 2006.257.15:48:05.03#ibcon#read 6, iclass 39, count 2 2006.257.15:48:05.03#ibcon#end of sib2, iclass 39, count 2 2006.257.15:48:05.03#ibcon#*mode == 0, iclass 39, count 2 2006.257.15:48:05.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.15:48:05.03#ibcon#[27=AT01-04\r\n] 2006.257.15:48:05.03#ibcon#*before write, iclass 39, count 2 2006.257.15:48:05.03#ibcon#enter sib2, iclass 39, count 2 2006.257.15:48:05.03#ibcon#flushed, iclass 39, count 2 2006.257.15:48:05.03#ibcon#about to write, iclass 39, count 2 2006.257.15:48:05.03#ibcon#wrote, iclass 39, count 2 2006.257.15:48:05.03#ibcon#about to read 3, iclass 39, count 2 2006.257.15:48:05.06#ibcon#read 3, iclass 39, count 2 2006.257.15:48:05.06#ibcon#about to read 4, iclass 39, count 2 2006.257.15:48:05.06#ibcon#read 4, iclass 39, count 2 2006.257.15:48:05.06#ibcon#about to read 5, iclass 39, count 2 2006.257.15:48:05.06#ibcon#read 5, iclass 39, count 2 2006.257.15:48:05.06#ibcon#about to read 6, iclass 39, count 2 2006.257.15:48:05.06#ibcon#read 6, iclass 39, count 2 2006.257.15:48:05.06#ibcon#end of sib2, iclass 39, count 2 2006.257.15:48:05.06#ibcon#*after write, iclass 39, count 2 2006.257.15:48:05.06#ibcon#*before return 0, iclass 39, count 2 2006.257.15:48:05.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:48:05.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.15:48:05.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.15:48:05.06#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:05.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:48:05.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:48:05.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:48:05.18#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:48:05.18#ibcon#first serial, iclass 39, count 0 2006.257.15:48:05.18#ibcon#enter sib2, iclass 39, count 0 2006.257.15:48:05.18#ibcon#flushed, iclass 39, count 0 2006.257.15:48:05.18#ibcon#about to write, iclass 39, count 0 2006.257.15:48:05.18#ibcon#wrote, iclass 39, count 0 2006.257.15:48:05.18#ibcon#about to read 3, iclass 39, count 0 2006.257.15:48:05.20#ibcon#read 3, iclass 39, count 0 2006.257.15:48:05.20#ibcon#about to read 4, iclass 39, count 0 2006.257.15:48:05.20#ibcon#read 4, iclass 39, count 0 2006.257.15:48:05.20#ibcon#about to read 5, iclass 39, count 0 2006.257.15:48:05.20#ibcon#read 5, iclass 39, count 0 2006.257.15:48:05.20#ibcon#about to read 6, iclass 39, count 0 2006.257.15:48:05.20#ibcon#read 6, iclass 39, count 0 2006.257.15:48:05.20#ibcon#end of sib2, iclass 39, count 0 2006.257.15:48:05.20#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:48:05.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:48:05.20#ibcon#[27=USB\r\n] 2006.257.15:48:05.20#ibcon#*before write, iclass 39, count 0 2006.257.15:48:05.20#ibcon#enter sib2, iclass 39, count 0 2006.257.15:48:05.20#ibcon#flushed, iclass 39, count 0 2006.257.15:48:05.20#ibcon#about to write, iclass 39, count 0 2006.257.15:48:05.20#ibcon#wrote, iclass 39, count 0 2006.257.15:48:05.20#ibcon#about to read 3, iclass 39, count 0 2006.257.15:48:05.23#ibcon#read 3, iclass 39, count 0 2006.257.15:48:05.23#ibcon#about to read 4, iclass 39, count 0 2006.257.15:48:05.23#ibcon#read 4, iclass 39, count 0 2006.257.15:48:05.23#ibcon#about to read 5, iclass 39, count 0 2006.257.15:48:05.23#ibcon#read 5, iclass 39, count 0 2006.257.15:48:05.23#ibcon#about to read 6, iclass 39, count 0 2006.257.15:48:05.23#ibcon#read 6, iclass 39, count 0 2006.257.15:48:05.23#ibcon#end of sib2, iclass 39, count 0 2006.257.15:48:05.23#ibcon#*after write, iclass 39, count 0 2006.257.15:48:05.23#ibcon#*before return 0, iclass 39, count 0 2006.257.15:48:05.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:48:05.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.15:48:05.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:48:05.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:48:05.23$vck44/vblo=2,634.99 2006.257.15:48:05.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.15:48:05.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.15:48:05.23#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:05.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:05.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:05.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:05.23#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:48:05.23#ibcon#first serial, iclass 3, count 0 2006.257.15:48:05.23#ibcon#enter sib2, iclass 3, count 0 2006.257.15:48:05.23#ibcon#flushed, iclass 3, count 0 2006.257.15:48:05.23#ibcon#about to write, iclass 3, count 0 2006.257.15:48:05.23#ibcon#wrote, iclass 3, count 0 2006.257.15:48:05.23#ibcon#about to read 3, iclass 3, count 0 2006.257.15:48:05.25#ibcon#read 3, iclass 3, count 0 2006.257.15:48:05.25#ibcon#about to read 4, iclass 3, count 0 2006.257.15:48:05.25#ibcon#read 4, iclass 3, count 0 2006.257.15:48:05.25#ibcon#about to read 5, iclass 3, count 0 2006.257.15:48:05.25#ibcon#read 5, iclass 3, count 0 2006.257.15:48:05.25#ibcon#about to read 6, iclass 3, count 0 2006.257.15:48:05.25#ibcon#read 6, iclass 3, count 0 2006.257.15:48:05.25#ibcon#end of sib2, iclass 3, count 0 2006.257.15:48:05.25#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:48:05.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:48:05.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:48:05.25#ibcon#*before write, iclass 3, count 0 2006.257.15:48:05.25#ibcon#enter sib2, iclass 3, count 0 2006.257.15:48:05.25#ibcon#flushed, iclass 3, count 0 2006.257.15:48:05.25#ibcon#about to write, iclass 3, count 0 2006.257.15:48:05.25#ibcon#wrote, iclass 3, count 0 2006.257.15:48:05.25#ibcon#about to read 3, iclass 3, count 0 2006.257.15:48:05.29#ibcon#read 3, iclass 3, count 0 2006.257.15:48:05.29#ibcon#about to read 4, iclass 3, count 0 2006.257.15:48:05.29#ibcon#read 4, iclass 3, count 0 2006.257.15:48:05.29#ibcon#about to read 5, iclass 3, count 0 2006.257.15:48:05.29#ibcon#read 5, iclass 3, count 0 2006.257.15:48:05.29#ibcon#about to read 6, iclass 3, count 0 2006.257.15:48:05.29#ibcon#read 6, iclass 3, count 0 2006.257.15:48:05.29#ibcon#end of sib2, iclass 3, count 0 2006.257.15:48:05.29#ibcon#*after write, iclass 3, count 0 2006.257.15:48:05.29#ibcon#*before return 0, iclass 3, count 0 2006.257.15:48:05.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:05.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.15:48:05.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:48:05.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:48:05.29$vck44/vb=2,5 2006.257.15:48:05.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.15:48:05.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.15:48:05.29#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:05.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:05.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:05.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:05.35#ibcon#enter wrdev, iclass 5, count 2 2006.257.15:48:05.35#ibcon#first serial, iclass 5, count 2 2006.257.15:48:05.35#ibcon#enter sib2, iclass 5, count 2 2006.257.15:48:05.35#ibcon#flushed, iclass 5, count 2 2006.257.15:48:05.35#ibcon#about to write, iclass 5, count 2 2006.257.15:48:05.35#ibcon#wrote, iclass 5, count 2 2006.257.15:48:05.35#ibcon#about to read 3, iclass 5, count 2 2006.257.15:48:05.37#ibcon#read 3, iclass 5, count 2 2006.257.15:48:05.37#ibcon#about to read 4, iclass 5, count 2 2006.257.15:48:05.37#ibcon#read 4, iclass 5, count 2 2006.257.15:48:05.37#ibcon#about to read 5, iclass 5, count 2 2006.257.15:48:05.37#ibcon#read 5, iclass 5, count 2 2006.257.15:48:05.37#ibcon#about to read 6, iclass 5, count 2 2006.257.15:48:05.37#ibcon#read 6, iclass 5, count 2 2006.257.15:48:05.37#ibcon#end of sib2, iclass 5, count 2 2006.257.15:48:05.37#ibcon#*mode == 0, iclass 5, count 2 2006.257.15:48:05.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.15:48:05.37#ibcon#[27=AT02-05\r\n] 2006.257.15:48:05.37#ibcon#*before write, iclass 5, count 2 2006.257.15:48:05.37#ibcon#enter sib2, iclass 5, count 2 2006.257.15:48:05.37#ibcon#flushed, iclass 5, count 2 2006.257.15:48:05.37#ibcon#about to write, iclass 5, count 2 2006.257.15:48:05.37#ibcon#wrote, iclass 5, count 2 2006.257.15:48:05.37#ibcon#about to read 3, iclass 5, count 2 2006.257.15:48:05.40#ibcon#read 3, iclass 5, count 2 2006.257.15:48:05.40#ibcon#about to read 4, iclass 5, count 2 2006.257.15:48:05.40#ibcon#read 4, iclass 5, count 2 2006.257.15:48:05.40#ibcon#about to read 5, iclass 5, count 2 2006.257.15:48:05.40#ibcon#read 5, iclass 5, count 2 2006.257.15:48:05.40#ibcon#about to read 6, iclass 5, count 2 2006.257.15:48:05.40#ibcon#read 6, iclass 5, count 2 2006.257.15:48:05.40#ibcon#end of sib2, iclass 5, count 2 2006.257.15:48:05.40#ibcon#*after write, iclass 5, count 2 2006.257.15:48:05.40#ibcon#*before return 0, iclass 5, count 2 2006.257.15:48:05.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:05.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.15:48:05.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.15:48:05.40#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:05.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:05.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:05.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:05.52#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:48:05.52#ibcon#first serial, iclass 5, count 0 2006.257.15:48:05.52#ibcon#enter sib2, iclass 5, count 0 2006.257.15:48:05.52#ibcon#flushed, iclass 5, count 0 2006.257.15:48:05.52#ibcon#about to write, iclass 5, count 0 2006.257.15:48:05.52#ibcon#wrote, iclass 5, count 0 2006.257.15:48:05.52#ibcon#about to read 3, iclass 5, count 0 2006.257.15:48:05.54#ibcon#read 3, iclass 5, count 0 2006.257.15:48:05.54#ibcon#about to read 4, iclass 5, count 0 2006.257.15:48:05.54#ibcon#read 4, iclass 5, count 0 2006.257.15:48:05.54#ibcon#about to read 5, iclass 5, count 0 2006.257.15:48:05.54#ibcon#read 5, iclass 5, count 0 2006.257.15:48:05.54#ibcon#about to read 6, iclass 5, count 0 2006.257.15:48:05.54#ibcon#read 6, iclass 5, count 0 2006.257.15:48:05.54#ibcon#end of sib2, iclass 5, count 0 2006.257.15:48:05.54#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:48:05.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:48:05.54#ibcon#[27=USB\r\n] 2006.257.15:48:05.54#ibcon#*before write, iclass 5, count 0 2006.257.15:48:05.54#ibcon#enter sib2, iclass 5, count 0 2006.257.15:48:05.54#ibcon#flushed, iclass 5, count 0 2006.257.15:48:05.54#ibcon#about to write, iclass 5, count 0 2006.257.15:48:05.54#ibcon#wrote, iclass 5, count 0 2006.257.15:48:05.54#ibcon#about to read 3, iclass 5, count 0 2006.257.15:48:05.57#ibcon#read 3, iclass 5, count 0 2006.257.15:48:05.57#ibcon#about to read 4, iclass 5, count 0 2006.257.15:48:05.57#ibcon#read 4, iclass 5, count 0 2006.257.15:48:05.57#ibcon#about to read 5, iclass 5, count 0 2006.257.15:48:05.57#ibcon#read 5, iclass 5, count 0 2006.257.15:48:05.57#ibcon#about to read 6, iclass 5, count 0 2006.257.15:48:05.57#ibcon#read 6, iclass 5, count 0 2006.257.15:48:05.57#ibcon#end of sib2, iclass 5, count 0 2006.257.15:48:05.57#ibcon#*after write, iclass 5, count 0 2006.257.15:48:05.57#ibcon#*before return 0, iclass 5, count 0 2006.257.15:48:05.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:05.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.15:48:05.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:48:05.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:48:05.57$vck44/vblo=3,649.99 2006.257.15:48:05.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.15:48:05.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.15:48:05.57#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:05.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:05.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:05.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:05.57#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:48:05.57#ibcon#first serial, iclass 7, count 0 2006.257.15:48:05.57#ibcon#enter sib2, iclass 7, count 0 2006.257.15:48:05.57#ibcon#flushed, iclass 7, count 0 2006.257.15:48:05.57#ibcon#about to write, iclass 7, count 0 2006.257.15:48:05.57#ibcon#wrote, iclass 7, count 0 2006.257.15:48:05.57#ibcon#about to read 3, iclass 7, count 0 2006.257.15:48:05.59#ibcon#read 3, iclass 7, count 0 2006.257.15:48:05.59#ibcon#about to read 4, iclass 7, count 0 2006.257.15:48:05.59#ibcon#read 4, iclass 7, count 0 2006.257.15:48:05.59#ibcon#about to read 5, iclass 7, count 0 2006.257.15:48:05.59#ibcon#read 5, iclass 7, count 0 2006.257.15:48:05.59#ibcon#about to read 6, iclass 7, count 0 2006.257.15:48:05.59#ibcon#read 6, iclass 7, count 0 2006.257.15:48:05.59#ibcon#end of sib2, iclass 7, count 0 2006.257.15:48:05.59#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:48:05.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:48:05.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:48:05.59#ibcon#*before write, iclass 7, count 0 2006.257.15:48:05.59#ibcon#enter sib2, iclass 7, count 0 2006.257.15:48:05.59#ibcon#flushed, iclass 7, count 0 2006.257.15:48:05.59#ibcon#about to write, iclass 7, count 0 2006.257.15:48:05.59#ibcon#wrote, iclass 7, count 0 2006.257.15:48:05.59#ibcon#about to read 3, iclass 7, count 0 2006.257.15:48:05.63#ibcon#read 3, iclass 7, count 0 2006.257.15:48:05.63#ibcon#about to read 4, iclass 7, count 0 2006.257.15:48:05.63#ibcon#read 4, iclass 7, count 0 2006.257.15:48:05.63#ibcon#about to read 5, iclass 7, count 0 2006.257.15:48:05.63#ibcon#read 5, iclass 7, count 0 2006.257.15:48:05.63#ibcon#about to read 6, iclass 7, count 0 2006.257.15:48:05.63#ibcon#read 6, iclass 7, count 0 2006.257.15:48:05.63#ibcon#end of sib2, iclass 7, count 0 2006.257.15:48:05.63#ibcon#*after write, iclass 7, count 0 2006.257.15:48:05.63#ibcon#*before return 0, iclass 7, count 0 2006.257.15:48:05.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:05.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.15:48:05.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:48:05.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:48:05.63$vck44/vb=3,4 2006.257.15:48:05.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.15:48:05.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.15:48:05.63#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:05.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:05.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:05.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:05.69#ibcon#enter wrdev, iclass 11, count 2 2006.257.15:48:05.69#ibcon#first serial, iclass 11, count 2 2006.257.15:48:05.69#ibcon#enter sib2, iclass 11, count 2 2006.257.15:48:05.69#ibcon#flushed, iclass 11, count 2 2006.257.15:48:05.69#ibcon#about to write, iclass 11, count 2 2006.257.15:48:05.69#ibcon#wrote, iclass 11, count 2 2006.257.15:48:05.69#ibcon#about to read 3, iclass 11, count 2 2006.257.15:48:05.71#ibcon#read 3, iclass 11, count 2 2006.257.15:48:05.71#ibcon#about to read 4, iclass 11, count 2 2006.257.15:48:05.71#ibcon#read 4, iclass 11, count 2 2006.257.15:48:05.71#ibcon#about to read 5, iclass 11, count 2 2006.257.15:48:05.71#ibcon#read 5, iclass 11, count 2 2006.257.15:48:05.71#ibcon#about to read 6, iclass 11, count 2 2006.257.15:48:05.71#ibcon#read 6, iclass 11, count 2 2006.257.15:48:05.71#ibcon#end of sib2, iclass 11, count 2 2006.257.15:48:05.71#ibcon#*mode == 0, iclass 11, count 2 2006.257.15:48:05.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.15:48:05.71#ibcon#[27=AT03-04\r\n] 2006.257.15:48:05.71#ibcon#*before write, iclass 11, count 2 2006.257.15:48:05.71#ibcon#enter sib2, iclass 11, count 2 2006.257.15:48:05.71#ibcon#flushed, iclass 11, count 2 2006.257.15:48:05.71#ibcon#about to write, iclass 11, count 2 2006.257.15:48:05.71#ibcon#wrote, iclass 11, count 2 2006.257.15:48:05.71#ibcon#about to read 3, iclass 11, count 2 2006.257.15:48:05.74#ibcon#read 3, iclass 11, count 2 2006.257.15:48:05.74#ibcon#about to read 4, iclass 11, count 2 2006.257.15:48:05.74#ibcon#read 4, iclass 11, count 2 2006.257.15:48:05.74#ibcon#about to read 5, iclass 11, count 2 2006.257.15:48:05.74#ibcon#read 5, iclass 11, count 2 2006.257.15:48:05.74#ibcon#about to read 6, iclass 11, count 2 2006.257.15:48:05.74#ibcon#read 6, iclass 11, count 2 2006.257.15:48:05.74#ibcon#end of sib2, iclass 11, count 2 2006.257.15:48:05.74#ibcon#*after write, iclass 11, count 2 2006.257.15:48:05.74#ibcon#*before return 0, iclass 11, count 2 2006.257.15:48:05.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:05.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.15:48:05.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.15:48:05.74#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:05.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:05.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:05.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:05.86#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:48:05.86#ibcon#first serial, iclass 11, count 0 2006.257.15:48:05.86#ibcon#enter sib2, iclass 11, count 0 2006.257.15:48:05.86#ibcon#flushed, iclass 11, count 0 2006.257.15:48:05.86#ibcon#about to write, iclass 11, count 0 2006.257.15:48:05.86#ibcon#wrote, iclass 11, count 0 2006.257.15:48:05.86#ibcon#about to read 3, iclass 11, count 0 2006.257.15:48:05.88#ibcon#read 3, iclass 11, count 0 2006.257.15:48:05.88#ibcon#about to read 4, iclass 11, count 0 2006.257.15:48:05.88#ibcon#read 4, iclass 11, count 0 2006.257.15:48:05.88#ibcon#about to read 5, iclass 11, count 0 2006.257.15:48:05.88#ibcon#read 5, iclass 11, count 0 2006.257.15:48:05.88#ibcon#about to read 6, iclass 11, count 0 2006.257.15:48:05.88#ibcon#read 6, iclass 11, count 0 2006.257.15:48:05.88#ibcon#end of sib2, iclass 11, count 0 2006.257.15:48:05.88#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:48:05.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:48:05.88#ibcon#[27=USB\r\n] 2006.257.15:48:05.88#ibcon#*before write, iclass 11, count 0 2006.257.15:48:05.88#ibcon#enter sib2, iclass 11, count 0 2006.257.15:48:05.88#ibcon#flushed, iclass 11, count 0 2006.257.15:48:05.88#ibcon#about to write, iclass 11, count 0 2006.257.15:48:05.88#ibcon#wrote, iclass 11, count 0 2006.257.15:48:05.88#ibcon#about to read 3, iclass 11, count 0 2006.257.15:48:05.91#ibcon#read 3, iclass 11, count 0 2006.257.15:48:05.91#ibcon#about to read 4, iclass 11, count 0 2006.257.15:48:05.91#ibcon#read 4, iclass 11, count 0 2006.257.15:48:05.91#ibcon#about to read 5, iclass 11, count 0 2006.257.15:48:05.91#ibcon#read 5, iclass 11, count 0 2006.257.15:48:05.91#ibcon#about to read 6, iclass 11, count 0 2006.257.15:48:05.91#ibcon#read 6, iclass 11, count 0 2006.257.15:48:05.91#ibcon#end of sib2, iclass 11, count 0 2006.257.15:48:05.91#ibcon#*after write, iclass 11, count 0 2006.257.15:48:05.91#ibcon#*before return 0, iclass 11, count 0 2006.257.15:48:05.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:05.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.15:48:05.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:48:05.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:48:05.91$vck44/vblo=4,679.99 2006.257.15:48:05.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.15:48:05.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.15:48:05.91#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:05.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:05.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:05.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:05.91#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:48:05.91#ibcon#first serial, iclass 13, count 0 2006.257.15:48:05.91#ibcon#enter sib2, iclass 13, count 0 2006.257.15:48:05.91#ibcon#flushed, iclass 13, count 0 2006.257.15:48:05.91#ibcon#about to write, iclass 13, count 0 2006.257.15:48:05.91#ibcon#wrote, iclass 13, count 0 2006.257.15:48:05.91#ibcon#about to read 3, iclass 13, count 0 2006.257.15:48:05.93#ibcon#read 3, iclass 13, count 0 2006.257.15:48:05.93#ibcon#about to read 4, iclass 13, count 0 2006.257.15:48:05.93#ibcon#read 4, iclass 13, count 0 2006.257.15:48:05.93#ibcon#about to read 5, iclass 13, count 0 2006.257.15:48:05.93#ibcon#read 5, iclass 13, count 0 2006.257.15:48:05.93#ibcon#about to read 6, iclass 13, count 0 2006.257.15:48:05.93#ibcon#read 6, iclass 13, count 0 2006.257.15:48:05.93#ibcon#end of sib2, iclass 13, count 0 2006.257.15:48:05.93#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:48:05.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:48:05.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:48:05.93#ibcon#*before write, iclass 13, count 0 2006.257.15:48:05.93#ibcon#enter sib2, iclass 13, count 0 2006.257.15:48:05.93#ibcon#flushed, iclass 13, count 0 2006.257.15:48:05.93#ibcon#about to write, iclass 13, count 0 2006.257.15:48:05.93#ibcon#wrote, iclass 13, count 0 2006.257.15:48:05.93#ibcon#about to read 3, iclass 13, count 0 2006.257.15:48:05.97#ibcon#read 3, iclass 13, count 0 2006.257.15:48:05.97#ibcon#about to read 4, iclass 13, count 0 2006.257.15:48:05.97#ibcon#read 4, iclass 13, count 0 2006.257.15:48:05.97#ibcon#about to read 5, iclass 13, count 0 2006.257.15:48:05.97#ibcon#read 5, iclass 13, count 0 2006.257.15:48:05.97#ibcon#about to read 6, iclass 13, count 0 2006.257.15:48:05.97#ibcon#read 6, iclass 13, count 0 2006.257.15:48:05.97#ibcon#end of sib2, iclass 13, count 0 2006.257.15:48:05.97#ibcon#*after write, iclass 13, count 0 2006.257.15:48:05.97#ibcon#*before return 0, iclass 13, count 0 2006.257.15:48:05.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:05.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.15:48:05.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:48:05.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:48:05.97$vck44/vb=4,5 2006.257.15:48:05.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.15:48:05.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.15:48:05.97#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:05.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:06.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:06.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:06.03#ibcon#enter wrdev, iclass 15, count 2 2006.257.15:48:06.03#ibcon#first serial, iclass 15, count 2 2006.257.15:48:06.03#ibcon#enter sib2, iclass 15, count 2 2006.257.15:48:06.03#ibcon#flushed, iclass 15, count 2 2006.257.15:48:06.03#ibcon#about to write, iclass 15, count 2 2006.257.15:48:06.03#ibcon#wrote, iclass 15, count 2 2006.257.15:48:06.03#ibcon#about to read 3, iclass 15, count 2 2006.257.15:48:06.05#ibcon#read 3, iclass 15, count 2 2006.257.15:48:06.05#ibcon#about to read 4, iclass 15, count 2 2006.257.15:48:06.05#ibcon#read 4, iclass 15, count 2 2006.257.15:48:06.05#ibcon#about to read 5, iclass 15, count 2 2006.257.15:48:06.05#ibcon#read 5, iclass 15, count 2 2006.257.15:48:06.05#ibcon#about to read 6, iclass 15, count 2 2006.257.15:48:06.05#ibcon#read 6, iclass 15, count 2 2006.257.15:48:06.05#ibcon#end of sib2, iclass 15, count 2 2006.257.15:48:06.05#ibcon#*mode == 0, iclass 15, count 2 2006.257.15:48:06.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.15:48:06.05#ibcon#[27=AT04-05\r\n] 2006.257.15:48:06.05#ibcon#*before write, iclass 15, count 2 2006.257.15:48:06.05#ibcon#enter sib2, iclass 15, count 2 2006.257.15:48:06.05#ibcon#flushed, iclass 15, count 2 2006.257.15:48:06.05#ibcon#about to write, iclass 15, count 2 2006.257.15:48:06.05#ibcon#wrote, iclass 15, count 2 2006.257.15:48:06.05#ibcon#about to read 3, iclass 15, count 2 2006.257.15:48:06.08#ibcon#read 3, iclass 15, count 2 2006.257.15:48:06.08#ibcon#about to read 4, iclass 15, count 2 2006.257.15:48:06.08#ibcon#read 4, iclass 15, count 2 2006.257.15:48:06.08#ibcon#about to read 5, iclass 15, count 2 2006.257.15:48:06.08#ibcon#read 5, iclass 15, count 2 2006.257.15:48:06.08#ibcon#about to read 6, iclass 15, count 2 2006.257.15:48:06.08#ibcon#read 6, iclass 15, count 2 2006.257.15:48:06.08#ibcon#end of sib2, iclass 15, count 2 2006.257.15:48:06.08#ibcon#*after write, iclass 15, count 2 2006.257.15:48:06.08#ibcon#*before return 0, iclass 15, count 2 2006.257.15:48:06.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:06.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.15:48:06.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.15:48:06.08#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:06.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:06.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:06.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:06.20#ibcon#enter wrdev, iclass 15, count 0 2006.257.15:48:06.20#ibcon#first serial, iclass 15, count 0 2006.257.15:48:06.20#ibcon#enter sib2, iclass 15, count 0 2006.257.15:48:06.20#ibcon#flushed, iclass 15, count 0 2006.257.15:48:06.20#ibcon#about to write, iclass 15, count 0 2006.257.15:48:06.20#ibcon#wrote, iclass 15, count 0 2006.257.15:48:06.20#ibcon#about to read 3, iclass 15, count 0 2006.257.15:48:06.22#ibcon#read 3, iclass 15, count 0 2006.257.15:48:06.22#ibcon#about to read 4, iclass 15, count 0 2006.257.15:48:06.22#ibcon#read 4, iclass 15, count 0 2006.257.15:48:06.22#ibcon#about to read 5, iclass 15, count 0 2006.257.15:48:06.22#ibcon#read 5, iclass 15, count 0 2006.257.15:48:06.22#ibcon#about to read 6, iclass 15, count 0 2006.257.15:48:06.22#ibcon#read 6, iclass 15, count 0 2006.257.15:48:06.22#ibcon#end of sib2, iclass 15, count 0 2006.257.15:48:06.22#ibcon#*mode == 0, iclass 15, count 0 2006.257.15:48:06.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.15:48:06.22#ibcon#[27=USB\r\n] 2006.257.15:48:06.22#ibcon#*before write, iclass 15, count 0 2006.257.15:48:06.22#ibcon#enter sib2, iclass 15, count 0 2006.257.15:48:06.22#ibcon#flushed, iclass 15, count 0 2006.257.15:48:06.22#ibcon#about to write, iclass 15, count 0 2006.257.15:48:06.22#ibcon#wrote, iclass 15, count 0 2006.257.15:48:06.22#ibcon#about to read 3, iclass 15, count 0 2006.257.15:48:06.25#ibcon#read 3, iclass 15, count 0 2006.257.15:48:06.25#ibcon#about to read 4, iclass 15, count 0 2006.257.15:48:06.25#ibcon#read 4, iclass 15, count 0 2006.257.15:48:06.25#ibcon#about to read 5, iclass 15, count 0 2006.257.15:48:06.25#ibcon#read 5, iclass 15, count 0 2006.257.15:48:06.25#ibcon#about to read 6, iclass 15, count 0 2006.257.15:48:06.25#ibcon#read 6, iclass 15, count 0 2006.257.15:48:06.25#ibcon#end of sib2, iclass 15, count 0 2006.257.15:48:06.25#ibcon#*after write, iclass 15, count 0 2006.257.15:48:06.25#ibcon#*before return 0, iclass 15, count 0 2006.257.15:48:06.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:06.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.15:48:06.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.15:48:06.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.15:48:06.25$vck44/vblo=5,709.99 2006.257.15:48:06.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.15:48:06.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.15:48:06.25#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:06.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:06.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:06.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:06.25#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:48:06.25#ibcon#first serial, iclass 17, count 0 2006.257.15:48:06.25#ibcon#enter sib2, iclass 17, count 0 2006.257.15:48:06.25#ibcon#flushed, iclass 17, count 0 2006.257.15:48:06.25#ibcon#about to write, iclass 17, count 0 2006.257.15:48:06.25#ibcon#wrote, iclass 17, count 0 2006.257.15:48:06.25#ibcon#about to read 3, iclass 17, count 0 2006.257.15:48:06.27#ibcon#read 3, iclass 17, count 0 2006.257.15:48:06.27#ibcon#about to read 4, iclass 17, count 0 2006.257.15:48:06.27#ibcon#read 4, iclass 17, count 0 2006.257.15:48:06.27#ibcon#about to read 5, iclass 17, count 0 2006.257.15:48:06.27#ibcon#read 5, iclass 17, count 0 2006.257.15:48:06.27#ibcon#about to read 6, iclass 17, count 0 2006.257.15:48:06.27#ibcon#read 6, iclass 17, count 0 2006.257.15:48:06.27#ibcon#end of sib2, iclass 17, count 0 2006.257.15:48:06.27#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:48:06.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:48:06.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:48:06.27#ibcon#*before write, iclass 17, count 0 2006.257.15:48:06.27#ibcon#enter sib2, iclass 17, count 0 2006.257.15:48:06.27#ibcon#flushed, iclass 17, count 0 2006.257.15:48:06.27#ibcon#about to write, iclass 17, count 0 2006.257.15:48:06.27#ibcon#wrote, iclass 17, count 0 2006.257.15:48:06.27#ibcon#about to read 3, iclass 17, count 0 2006.257.15:48:06.31#ibcon#read 3, iclass 17, count 0 2006.257.15:48:06.31#ibcon#about to read 4, iclass 17, count 0 2006.257.15:48:06.31#ibcon#read 4, iclass 17, count 0 2006.257.15:48:06.31#ibcon#about to read 5, iclass 17, count 0 2006.257.15:48:06.31#ibcon#read 5, iclass 17, count 0 2006.257.15:48:06.31#ibcon#about to read 6, iclass 17, count 0 2006.257.15:48:06.31#ibcon#read 6, iclass 17, count 0 2006.257.15:48:06.31#ibcon#end of sib2, iclass 17, count 0 2006.257.15:48:06.31#ibcon#*after write, iclass 17, count 0 2006.257.15:48:06.31#ibcon#*before return 0, iclass 17, count 0 2006.257.15:48:06.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:06.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.15:48:06.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:48:06.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:48:06.31$vck44/vb=5,4 2006.257.15:48:06.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.15:48:06.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.15:48:06.31#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:06.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:06.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:06.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:06.37#ibcon#enter wrdev, iclass 19, count 2 2006.257.15:48:06.37#ibcon#first serial, iclass 19, count 2 2006.257.15:48:06.37#ibcon#enter sib2, iclass 19, count 2 2006.257.15:48:06.37#ibcon#flushed, iclass 19, count 2 2006.257.15:48:06.37#ibcon#about to write, iclass 19, count 2 2006.257.15:48:06.37#ibcon#wrote, iclass 19, count 2 2006.257.15:48:06.37#ibcon#about to read 3, iclass 19, count 2 2006.257.15:48:06.39#ibcon#read 3, iclass 19, count 2 2006.257.15:48:06.39#ibcon#about to read 4, iclass 19, count 2 2006.257.15:48:06.39#ibcon#read 4, iclass 19, count 2 2006.257.15:48:06.39#ibcon#about to read 5, iclass 19, count 2 2006.257.15:48:06.39#ibcon#read 5, iclass 19, count 2 2006.257.15:48:06.39#ibcon#about to read 6, iclass 19, count 2 2006.257.15:48:06.39#ibcon#read 6, iclass 19, count 2 2006.257.15:48:06.39#ibcon#end of sib2, iclass 19, count 2 2006.257.15:48:06.39#ibcon#*mode == 0, iclass 19, count 2 2006.257.15:48:06.39#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.15:48:06.39#ibcon#[27=AT05-04\r\n] 2006.257.15:48:06.39#ibcon#*before write, iclass 19, count 2 2006.257.15:48:06.39#ibcon#enter sib2, iclass 19, count 2 2006.257.15:48:06.39#ibcon#flushed, iclass 19, count 2 2006.257.15:48:06.39#ibcon#about to write, iclass 19, count 2 2006.257.15:48:06.39#ibcon#wrote, iclass 19, count 2 2006.257.15:48:06.39#ibcon#about to read 3, iclass 19, count 2 2006.257.15:48:06.42#ibcon#read 3, iclass 19, count 2 2006.257.15:48:06.42#ibcon#about to read 4, iclass 19, count 2 2006.257.15:48:06.42#ibcon#read 4, iclass 19, count 2 2006.257.15:48:06.42#ibcon#about to read 5, iclass 19, count 2 2006.257.15:48:06.42#ibcon#read 5, iclass 19, count 2 2006.257.15:48:06.42#ibcon#about to read 6, iclass 19, count 2 2006.257.15:48:06.42#ibcon#read 6, iclass 19, count 2 2006.257.15:48:06.42#ibcon#end of sib2, iclass 19, count 2 2006.257.15:48:06.42#ibcon#*after write, iclass 19, count 2 2006.257.15:48:06.42#ibcon#*before return 0, iclass 19, count 2 2006.257.15:48:06.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:06.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.15:48:06.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.15:48:06.42#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:06.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:06.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:06.54#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:06.54#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:48:06.54#ibcon#first serial, iclass 19, count 0 2006.257.15:48:06.54#ibcon#enter sib2, iclass 19, count 0 2006.257.15:48:06.54#ibcon#flushed, iclass 19, count 0 2006.257.15:48:06.54#ibcon#about to write, iclass 19, count 0 2006.257.15:48:06.54#ibcon#wrote, iclass 19, count 0 2006.257.15:48:06.54#ibcon#about to read 3, iclass 19, count 0 2006.257.15:48:06.56#ibcon#read 3, iclass 19, count 0 2006.257.15:48:06.56#ibcon#about to read 4, iclass 19, count 0 2006.257.15:48:06.56#ibcon#read 4, iclass 19, count 0 2006.257.15:48:06.56#ibcon#about to read 5, iclass 19, count 0 2006.257.15:48:06.56#ibcon#read 5, iclass 19, count 0 2006.257.15:48:06.56#ibcon#about to read 6, iclass 19, count 0 2006.257.15:48:06.56#ibcon#read 6, iclass 19, count 0 2006.257.15:48:06.56#ibcon#end of sib2, iclass 19, count 0 2006.257.15:48:06.56#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:48:06.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:48:06.56#ibcon#[27=USB\r\n] 2006.257.15:48:06.56#ibcon#*before write, iclass 19, count 0 2006.257.15:48:06.56#ibcon#enter sib2, iclass 19, count 0 2006.257.15:48:06.56#ibcon#flushed, iclass 19, count 0 2006.257.15:48:06.56#ibcon#about to write, iclass 19, count 0 2006.257.15:48:06.56#ibcon#wrote, iclass 19, count 0 2006.257.15:48:06.56#ibcon#about to read 3, iclass 19, count 0 2006.257.15:48:06.59#ibcon#read 3, iclass 19, count 0 2006.257.15:48:06.59#ibcon#about to read 4, iclass 19, count 0 2006.257.15:48:06.59#ibcon#read 4, iclass 19, count 0 2006.257.15:48:06.59#ibcon#about to read 5, iclass 19, count 0 2006.257.15:48:06.59#ibcon#read 5, iclass 19, count 0 2006.257.15:48:06.59#ibcon#about to read 6, iclass 19, count 0 2006.257.15:48:06.59#ibcon#read 6, iclass 19, count 0 2006.257.15:48:06.59#ibcon#end of sib2, iclass 19, count 0 2006.257.15:48:06.59#ibcon#*after write, iclass 19, count 0 2006.257.15:48:06.59#ibcon#*before return 0, iclass 19, count 0 2006.257.15:48:06.59#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:06.59#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.15:48:06.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:48:06.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:48:06.59$vck44/vblo=6,719.99 2006.257.15:48:06.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.15:48:06.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.15:48:06.59#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:06.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:06.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:06.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:06.59#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:48:06.59#ibcon#first serial, iclass 21, count 0 2006.257.15:48:06.59#ibcon#enter sib2, iclass 21, count 0 2006.257.15:48:06.59#ibcon#flushed, iclass 21, count 0 2006.257.15:48:06.59#ibcon#about to write, iclass 21, count 0 2006.257.15:48:06.59#ibcon#wrote, iclass 21, count 0 2006.257.15:48:06.59#ibcon#about to read 3, iclass 21, count 0 2006.257.15:48:06.61#ibcon#read 3, iclass 21, count 0 2006.257.15:48:06.61#ibcon#about to read 4, iclass 21, count 0 2006.257.15:48:06.61#ibcon#read 4, iclass 21, count 0 2006.257.15:48:06.61#ibcon#about to read 5, iclass 21, count 0 2006.257.15:48:06.61#ibcon#read 5, iclass 21, count 0 2006.257.15:48:06.61#ibcon#about to read 6, iclass 21, count 0 2006.257.15:48:06.61#ibcon#read 6, iclass 21, count 0 2006.257.15:48:06.61#ibcon#end of sib2, iclass 21, count 0 2006.257.15:48:06.61#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:48:06.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:48:06.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:48:06.61#ibcon#*before write, iclass 21, count 0 2006.257.15:48:06.61#ibcon#enter sib2, iclass 21, count 0 2006.257.15:48:06.61#ibcon#flushed, iclass 21, count 0 2006.257.15:48:06.61#ibcon#about to write, iclass 21, count 0 2006.257.15:48:06.61#ibcon#wrote, iclass 21, count 0 2006.257.15:48:06.61#ibcon#about to read 3, iclass 21, count 0 2006.257.15:48:06.65#ibcon#read 3, iclass 21, count 0 2006.257.15:48:06.65#ibcon#about to read 4, iclass 21, count 0 2006.257.15:48:06.65#ibcon#read 4, iclass 21, count 0 2006.257.15:48:06.65#ibcon#about to read 5, iclass 21, count 0 2006.257.15:48:06.65#ibcon#read 5, iclass 21, count 0 2006.257.15:48:06.65#ibcon#about to read 6, iclass 21, count 0 2006.257.15:48:06.65#ibcon#read 6, iclass 21, count 0 2006.257.15:48:06.65#ibcon#end of sib2, iclass 21, count 0 2006.257.15:48:06.65#ibcon#*after write, iclass 21, count 0 2006.257.15:48:06.65#ibcon#*before return 0, iclass 21, count 0 2006.257.15:48:06.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:06.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.15:48:06.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:48:06.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:48:06.65$vck44/vb=6,4 2006.257.15:48:06.65#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.15:48:06.65#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.15:48:06.65#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:06.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:06.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:06.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:06.71#ibcon#enter wrdev, iclass 23, count 2 2006.257.15:48:06.71#ibcon#first serial, iclass 23, count 2 2006.257.15:48:06.71#ibcon#enter sib2, iclass 23, count 2 2006.257.15:48:06.71#ibcon#flushed, iclass 23, count 2 2006.257.15:48:06.71#ibcon#about to write, iclass 23, count 2 2006.257.15:48:06.71#ibcon#wrote, iclass 23, count 2 2006.257.15:48:06.71#ibcon#about to read 3, iclass 23, count 2 2006.257.15:48:06.73#ibcon#read 3, iclass 23, count 2 2006.257.15:48:06.73#ibcon#about to read 4, iclass 23, count 2 2006.257.15:48:06.73#ibcon#read 4, iclass 23, count 2 2006.257.15:48:06.73#ibcon#about to read 5, iclass 23, count 2 2006.257.15:48:06.73#ibcon#read 5, iclass 23, count 2 2006.257.15:48:06.73#ibcon#about to read 6, iclass 23, count 2 2006.257.15:48:06.73#ibcon#read 6, iclass 23, count 2 2006.257.15:48:06.73#ibcon#end of sib2, iclass 23, count 2 2006.257.15:48:06.73#ibcon#*mode == 0, iclass 23, count 2 2006.257.15:48:06.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.15:48:06.73#ibcon#[27=AT06-04\r\n] 2006.257.15:48:06.73#ibcon#*before write, iclass 23, count 2 2006.257.15:48:06.73#ibcon#enter sib2, iclass 23, count 2 2006.257.15:48:06.73#ibcon#flushed, iclass 23, count 2 2006.257.15:48:06.73#ibcon#about to write, iclass 23, count 2 2006.257.15:48:06.73#ibcon#wrote, iclass 23, count 2 2006.257.15:48:06.73#ibcon#about to read 3, iclass 23, count 2 2006.257.15:48:06.76#ibcon#read 3, iclass 23, count 2 2006.257.15:48:06.76#ibcon#about to read 4, iclass 23, count 2 2006.257.15:48:06.76#ibcon#read 4, iclass 23, count 2 2006.257.15:48:06.76#ibcon#about to read 5, iclass 23, count 2 2006.257.15:48:06.76#ibcon#read 5, iclass 23, count 2 2006.257.15:48:06.76#ibcon#about to read 6, iclass 23, count 2 2006.257.15:48:06.76#ibcon#read 6, iclass 23, count 2 2006.257.15:48:06.76#ibcon#end of sib2, iclass 23, count 2 2006.257.15:48:06.76#ibcon#*after write, iclass 23, count 2 2006.257.15:48:06.76#ibcon#*before return 0, iclass 23, count 2 2006.257.15:48:06.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:06.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.15:48:06.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.15:48:06.76#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:06.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:06.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:06.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:06.88#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:48:06.88#ibcon#first serial, iclass 23, count 0 2006.257.15:48:06.88#ibcon#enter sib2, iclass 23, count 0 2006.257.15:48:06.88#ibcon#flushed, iclass 23, count 0 2006.257.15:48:06.88#ibcon#about to write, iclass 23, count 0 2006.257.15:48:06.88#ibcon#wrote, iclass 23, count 0 2006.257.15:48:06.88#ibcon#about to read 3, iclass 23, count 0 2006.257.15:48:06.90#ibcon#read 3, iclass 23, count 0 2006.257.15:48:06.90#ibcon#about to read 4, iclass 23, count 0 2006.257.15:48:06.90#ibcon#read 4, iclass 23, count 0 2006.257.15:48:06.90#ibcon#about to read 5, iclass 23, count 0 2006.257.15:48:06.90#ibcon#read 5, iclass 23, count 0 2006.257.15:48:06.90#ibcon#about to read 6, iclass 23, count 0 2006.257.15:48:06.90#ibcon#read 6, iclass 23, count 0 2006.257.15:48:06.90#ibcon#end of sib2, iclass 23, count 0 2006.257.15:48:06.90#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:48:06.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:48:06.90#ibcon#[27=USB\r\n] 2006.257.15:48:06.90#ibcon#*before write, iclass 23, count 0 2006.257.15:48:06.90#ibcon#enter sib2, iclass 23, count 0 2006.257.15:48:06.90#ibcon#flushed, iclass 23, count 0 2006.257.15:48:06.90#ibcon#about to write, iclass 23, count 0 2006.257.15:48:06.90#ibcon#wrote, iclass 23, count 0 2006.257.15:48:06.90#ibcon#about to read 3, iclass 23, count 0 2006.257.15:48:06.93#ibcon#read 3, iclass 23, count 0 2006.257.15:48:06.93#ibcon#about to read 4, iclass 23, count 0 2006.257.15:48:06.93#ibcon#read 4, iclass 23, count 0 2006.257.15:48:06.93#ibcon#about to read 5, iclass 23, count 0 2006.257.15:48:06.93#ibcon#read 5, iclass 23, count 0 2006.257.15:48:06.93#ibcon#about to read 6, iclass 23, count 0 2006.257.15:48:06.93#ibcon#read 6, iclass 23, count 0 2006.257.15:48:06.93#ibcon#end of sib2, iclass 23, count 0 2006.257.15:48:06.93#ibcon#*after write, iclass 23, count 0 2006.257.15:48:06.93#ibcon#*before return 0, iclass 23, count 0 2006.257.15:48:06.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:06.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.15:48:06.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:48:06.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:48:06.93$vck44/vblo=7,734.99 2006.257.15:48:06.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.15:48:06.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.15:48:06.93#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:06.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:06.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:06.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:06.93#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:48:06.93#ibcon#first serial, iclass 25, count 0 2006.257.15:48:06.93#ibcon#enter sib2, iclass 25, count 0 2006.257.15:48:06.93#ibcon#flushed, iclass 25, count 0 2006.257.15:48:06.93#ibcon#about to write, iclass 25, count 0 2006.257.15:48:06.93#ibcon#wrote, iclass 25, count 0 2006.257.15:48:06.93#ibcon#about to read 3, iclass 25, count 0 2006.257.15:48:06.95#ibcon#read 3, iclass 25, count 0 2006.257.15:48:06.95#ibcon#about to read 4, iclass 25, count 0 2006.257.15:48:06.95#ibcon#read 4, iclass 25, count 0 2006.257.15:48:06.95#ibcon#about to read 5, iclass 25, count 0 2006.257.15:48:06.95#ibcon#read 5, iclass 25, count 0 2006.257.15:48:06.95#ibcon#about to read 6, iclass 25, count 0 2006.257.15:48:06.95#ibcon#read 6, iclass 25, count 0 2006.257.15:48:06.95#ibcon#end of sib2, iclass 25, count 0 2006.257.15:48:06.95#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:48:06.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:48:06.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:48:06.95#ibcon#*before write, iclass 25, count 0 2006.257.15:48:06.95#ibcon#enter sib2, iclass 25, count 0 2006.257.15:48:06.95#ibcon#flushed, iclass 25, count 0 2006.257.15:48:06.95#ibcon#about to write, iclass 25, count 0 2006.257.15:48:06.95#ibcon#wrote, iclass 25, count 0 2006.257.15:48:06.95#ibcon#about to read 3, iclass 25, count 0 2006.257.15:48:06.99#ibcon#read 3, iclass 25, count 0 2006.257.15:48:06.99#ibcon#about to read 4, iclass 25, count 0 2006.257.15:48:06.99#ibcon#read 4, iclass 25, count 0 2006.257.15:48:06.99#ibcon#about to read 5, iclass 25, count 0 2006.257.15:48:06.99#ibcon#read 5, iclass 25, count 0 2006.257.15:48:06.99#ibcon#about to read 6, iclass 25, count 0 2006.257.15:48:06.99#ibcon#read 6, iclass 25, count 0 2006.257.15:48:06.99#ibcon#end of sib2, iclass 25, count 0 2006.257.15:48:06.99#ibcon#*after write, iclass 25, count 0 2006.257.15:48:06.99#ibcon#*before return 0, iclass 25, count 0 2006.257.15:48:06.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:06.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.15:48:06.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:48:06.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:48:06.99$vck44/vb=7,4 2006.257.15:48:06.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.15:48:06.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.15:48:06.99#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:06.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:07.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:07.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:07.05#ibcon#enter wrdev, iclass 27, count 2 2006.257.15:48:07.05#ibcon#first serial, iclass 27, count 2 2006.257.15:48:07.05#ibcon#enter sib2, iclass 27, count 2 2006.257.15:48:07.05#ibcon#flushed, iclass 27, count 2 2006.257.15:48:07.05#ibcon#about to write, iclass 27, count 2 2006.257.15:48:07.05#ibcon#wrote, iclass 27, count 2 2006.257.15:48:07.05#ibcon#about to read 3, iclass 27, count 2 2006.257.15:48:07.07#ibcon#read 3, iclass 27, count 2 2006.257.15:48:07.07#ibcon#about to read 4, iclass 27, count 2 2006.257.15:48:07.07#ibcon#read 4, iclass 27, count 2 2006.257.15:48:07.07#ibcon#about to read 5, iclass 27, count 2 2006.257.15:48:07.07#ibcon#read 5, iclass 27, count 2 2006.257.15:48:07.07#ibcon#about to read 6, iclass 27, count 2 2006.257.15:48:07.07#ibcon#read 6, iclass 27, count 2 2006.257.15:48:07.07#ibcon#end of sib2, iclass 27, count 2 2006.257.15:48:07.07#ibcon#*mode == 0, iclass 27, count 2 2006.257.15:48:07.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.15:48:07.07#ibcon#[27=AT07-04\r\n] 2006.257.15:48:07.07#ibcon#*before write, iclass 27, count 2 2006.257.15:48:07.07#ibcon#enter sib2, iclass 27, count 2 2006.257.15:48:07.07#ibcon#flushed, iclass 27, count 2 2006.257.15:48:07.07#ibcon#about to write, iclass 27, count 2 2006.257.15:48:07.07#ibcon#wrote, iclass 27, count 2 2006.257.15:48:07.07#ibcon#about to read 3, iclass 27, count 2 2006.257.15:48:07.10#ibcon#read 3, iclass 27, count 2 2006.257.15:48:07.10#ibcon#about to read 4, iclass 27, count 2 2006.257.15:48:07.10#ibcon#read 4, iclass 27, count 2 2006.257.15:48:07.10#ibcon#about to read 5, iclass 27, count 2 2006.257.15:48:07.10#ibcon#read 5, iclass 27, count 2 2006.257.15:48:07.10#ibcon#about to read 6, iclass 27, count 2 2006.257.15:48:07.10#ibcon#read 6, iclass 27, count 2 2006.257.15:48:07.10#ibcon#end of sib2, iclass 27, count 2 2006.257.15:48:07.10#ibcon#*after write, iclass 27, count 2 2006.257.15:48:07.10#ibcon#*before return 0, iclass 27, count 2 2006.257.15:48:07.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:07.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.15:48:07.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.15:48:07.10#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:07.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:07.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:07.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:07.22#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:48:07.22#ibcon#first serial, iclass 27, count 0 2006.257.15:48:07.22#ibcon#enter sib2, iclass 27, count 0 2006.257.15:48:07.22#ibcon#flushed, iclass 27, count 0 2006.257.15:48:07.22#ibcon#about to write, iclass 27, count 0 2006.257.15:48:07.22#ibcon#wrote, iclass 27, count 0 2006.257.15:48:07.22#ibcon#about to read 3, iclass 27, count 0 2006.257.15:48:07.24#ibcon#read 3, iclass 27, count 0 2006.257.15:48:07.24#ibcon#about to read 4, iclass 27, count 0 2006.257.15:48:07.24#ibcon#read 4, iclass 27, count 0 2006.257.15:48:07.24#ibcon#about to read 5, iclass 27, count 0 2006.257.15:48:07.24#ibcon#read 5, iclass 27, count 0 2006.257.15:48:07.24#ibcon#about to read 6, iclass 27, count 0 2006.257.15:48:07.24#ibcon#read 6, iclass 27, count 0 2006.257.15:48:07.24#ibcon#end of sib2, iclass 27, count 0 2006.257.15:48:07.24#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:48:07.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:48:07.24#ibcon#[27=USB\r\n] 2006.257.15:48:07.24#ibcon#*before write, iclass 27, count 0 2006.257.15:48:07.24#ibcon#enter sib2, iclass 27, count 0 2006.257.15:48:07.24#ibcon#flushed, iclass 27, count 0 2006.257.15:48:07.24#ibcon#about to write, iclass 27, count 0 2006.257.15:48:07.24#ibcon#wrote, iclass 27, count 0 2006.257.15:48:07.24#ibcon#about to read 3, iclass 27, count 0 2006.257.15:48:07.27#ibcon#read 3, iclass 27, count 0 2006.257.15:48:07.27#ibcon#about to read 4, iclass 27, count 0 2006.257.15:48:07.27#ibcon#read 4, iclass 27, count 0 2006.257.15:48:07.27#ibcon#about to read 5, iclass 27, count 0 2006.257.15:48:07.27#ibcon#read 5, iclass 27, count 0 2006.257.15:48:07.27#ibcon#about to read 6, iclass 27, count 0 2006.257.15:48:07.27#ibcon#read 6, iclass 27, count 0 2006.257.15:48:07.27#ibcon#end of sib2, iclass 27, count 0 2006.257.15:48:07.27#ibcon#*after write, iclass 27, count 0 2006.257.15:48:07.27#ibcon#*before return 0, iclass 27, count 0 2006.257.15:48:07.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:07.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.15:48:07.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:48:07.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:48:07.27$vck44/vblo=8,744.99 2006.257.15:48:07.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.15:48:07.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.15:48:07.27#ibcon#ireg 17 cls_cnt 0 2006.257.15:48:07.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:07.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:07.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:07.27#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:48:07.27#ibcon#first serial, iclass 29, count 0 2006.257.15:48:07.27#ibcon#enter sib2, iclass 29, count 0 2006.257.15:48:07.27#ibcon#flushed, iclass 29, count 0 2006.257.15:48:07.27#ibcon#about to write, iclass 29, count 0 2006.257.15:48:07.27#ibcon#wrote, iclass 29, count 0 2006.257.15:48:07.27#ibcon#about to read 3, iclass 29, count 0 2006.257.15:48:07.29#ibcon#read 3, iclass 29, count 0 2006.257.15:48:07.29#ibcon#about to read 4, iclass 29, count 0 2006.257.15:48:07.29#ibcon#read 4, iclass 29, count 0 2006.257.15:48:07.29#ibcon#about to read 5, iclass 29, count 0 2006.257.15:48:07.29#ibcon#read 5, iclass 29, count 0 2006.257.15:48:07.29#ibcon#about to read 6, iclass 29, count 0 2006.257.15:48:07.29#ibcon#read 6, iclass 29, count 0 2006.257.15:48:07.29#ibcon#end of sib2, iclass 29, count 0 2006.257.15:48:07.29#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:48:07.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:48:07.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:48:07.29#ibcon#*before write, iclass 29, count 0 2006.257.15:48:07.29#ibcon#enter sib2, iclass 29, count 0 2006.257.15:48:07.29#ibcon#flushed, iclass 29, count 0 2006.257.15:48:07.29#ibcon#about to write, iclass 29, count 0 2006.257.15:48:07.29#ibcon#wrote, iclass 29, count 0 2006.257.15:48:07.29#ibcon#about to read 3, iclass 29, count 0 2006.257.15:48:07.33#ibcon#read 3, iclass 29, count 0 2006.257.15:48:07.33#ibcon#about to read 4, iclass 29, count 0 2006.257.15:48:07.33#ibcon#read 4, iclass 29, count 0 2006.257.15:48:07.33#ibcon#about to read 5, iclass 29, count 0 2006.257.15:48:07.33#ibcon#read 5, iclass 29, count 0 2006.257.15:48:07.33#ibcon#about to read 6, iclass 29, count 0 2006.257.15:48:07.33#ibcon#read 6, iclass 29, count 0 2006.257.15:48:07.33#ibcon#end of sib2, iclass 29, count 0 2006.257.15:48:07.33#ibcon#*after write, iclass 29, count 0 2006.257.15:48:07.33#ibcon#*before return 0, iclass 29, count 0 2006.257.15:48:07.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:07.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.15:48:07.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:48:07.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:48:07.33$vck44/vb=8,4 2006.257.15:48:07.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.15:48:07.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.15:48:07.33#ibcon#ireg 11 cls_cnt 2 2006.257.15:48:07.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:07.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:07.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:07.39#ibcon#enter wrdev, iclass 31, count 2 2006.257.15:48:07.39#ibcon#first serial, iclass 31, count 2 2006.257.15:48:07.39#ibcon#enter sib2, iclass 31, count 2 2006.257.15:48:07.39#ibcon#flushed, iclass 31, count 2 2006.257.15:48:07.39#ibcon#about to write, iclass 31, count 2 2006.257.15:48:07.39#ibcon#wrote, iclass 31, count 2 2006.257.15:48:07.39#ibcon#about to read 3, iclass 31, count 2 2006.257.15:48:07.41#ibcon#read 3, iclass 31, count 2 2006.257.15:48:07.41#ibcon#about to read 4, iclass 31, count 2 2006.257.15:48:07.41#ibcon#read 4, iclass 31, count 2 2006.257.15:48:07.41#ibcon#about to read 5, iclass 31, count 2 2006.257.15:48:07.41#ibcon#read 5, iclass 31, count 2 2006.257.15:48:07.41#ibcon#about to read 6, iclass 31, count 2 2006.257.15:48:07.41#ibcon#read 6, iclass 31, count 2 2006.257.15:48:07.41#ibcon#end of sib2, iclass 31, count 2 2006.257.15:48:07.41#ibcon#*mode == 0, iclass 31, count 2 2006.257.15:48:07.41#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.15:48:07.41#ibcon#[27=AT08-04\r\n] 2006.257.15:48:07.41#ibcon#*before write, iclass 31, count 2 2006.257.15:48:07.41#ibcon#enter sib2, iclass 31, count 2 2006.257.15:48:07.41#ibcon#flushed, iclass 31, count 2 2006.257.15:48:07.41#ibcon#about to write, iclass 31, count 2 2006.257.15:48:07.41#ibcon#wrote, iclass 31, count 2 2006.257.15:48:07.41#ibcon#about to read 3, iclass 31, count 2 2006.257.15:48:07.44#ibcon#read 3, iclass 31, count 2 2006.257.15:48:07.44#ibcon#about to read 4, iclass 31, count 2 2006.257.15:48:07.44#ibcon#read 4, iclass 31, count 2 2006.257.15:48:07.44#ibcon#about to read 5, iclass 31, count 2 2006.257.15:48:07.44#ibcon#read 5, iclass 31, count 2 2006.257.15:48:07.44#ibcon#about to read 6, iclass 31, count 2 2006.257.15:48:07.44#ibcon#read 6, iclass 31, count 2 2006.257.15:48:07.44#ibcon#end of sib2, iclass 31, count 2 2006.257.15:48:07.44#ibcon#*after write, iclass 31, count 2 2006.257.15:48:07.44#ibcon#*before return 0, iclass 31, count 2 2006.257.15:48:07.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:07.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.15:48:07.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.15:48:07.44#ibcon#ireg 7 cls_cnt 0 2006.257.15:48:07.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:07.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:07.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:07.56#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:48:07.56#ibcon#first serial, iclass 31, count 0 2006.257.15:48:07.56#ibcon#enter sib2, iclass 31, count 0 2006.257.15:48:07.56#ibcon#flushed, iclass 31, count 0 2006.257.15:48:07.56#ibcon#about to write, iclass 31, count 0 2006.257.15:48:07.56#ibcon#wrote, iclass 31, count 0 2006.257.15:48:07.56#ibcon#about to read 3, iclass 31, count 0 2006.257.15:48:07.58#ibcon#read 3, iclass 31, count 0 2006.257.15:48:07.58#ibcon#about to read 4, iclass 31, count 0 2006.257.15:48:07.58#ibcon#read 4, iclass 31, count 0 2006.257.15:48:07.58#ibcon#about to read 5, iclass 31, count 0 2006.257.15:48:07.58#ibcon#read 5, iclass 31, count 0 2006.257.15:48:07.58#ibcon#about to read 6, iclass 31, count 0 2006.257.15:48:07.58#ibcon#read 6, iclass 31, count 0 2006.257.15:48:07.58#ibcon#end of sib2, iclass 31, count 0 2006.257.15:48:07.58#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:48:07.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:48:07.58#ibcon#[27=USB\r\n] 2006.257.15:48:07.58#ibcon#*before write, iclass 31, count 0 2006.257.15:48:07.58#ibcon#enter sib2, iclass 31, count 0 2006.257.15:48:07.58#ibcon#flushed, iclass 31, count 0 2006.257.15:48:07.58#ibcon#about to write, iclass 31, count 0 2006.257.15:48:07.58#ibcon#wrote, iclass 31, count 0 2006.257.15:48:07.58#ibcon#about to read 3, iclass 31, count 0 2006.257.15:48:07.61#ibcon#read 3, iclass 31, count 0 2006.257.15:48:07.61#ibcon#about to read 4, iclass 31, count 0 2006.257.15:48:07.61#ibcon#read 4, iclass 31, count 0 2006.257.15:48:07.61#ibcon#about to read 5, iclass 31, count 0 2006.257.15:48:07.61#ibcon#read 5, iclass 31, count 0 2006.257.15:48:07.61#ibcon#about to read 6, iclass 31, count 0 2006.257.15:48:07.61#ibcon#read 6, iclass 31, count 0 2006.257.15:48:07.61#ibcon#end of sib2, iclass 31, count 0 2006.257.15:48:07.61#ibcon#*after write, iclass 31, count 0 2006.257.15:48:07.61#ibcon#*before return 0, iclass 31, count 0 2006.257.15:48:07.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:07.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.15:48:07.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:48:07.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:48:07.61$vck44/vabw=wide 2006.257.15:48:07.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.15:48:07.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.15:48:07.61#ibcon#ireg 8 cls_cnt 0 2006.257.15:48:07.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:07.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:07.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:07.61#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:48:07.61#ibcon#first serial, iclass 33, count 0 2006.257.15:48:07.61#ibcon#enter sib2, iclass 33, count 0 2006.257.15:48:07.61#ibcon#flushed, iclass 33, count 0 2006.257.15:48:07.61#ibcon#about to write, iclass 33, count 0 2006.257.15:48:07.61#ibcon#wrote, iclass 33, count 0 2006.257.15:48:07.61#ibcon#about to read 3, iclass 33, count 0 2006.257.15:48:07.63#ibcon#read 3, iclass 33, count 0 2006.257.15:48:07.63#ibcon#about to read 4, iclass 33, count 0 2006.257.15:48:07.63#ibcon#read 4, iclass 33, count 0 2006.257.15:48:07.63#ibcon#about to read 5, iclass 33, count 0 2006.257.15:48:07.63#ibcon#read 5, iclass 33, count 0 2006.257.15:48:07.63#ibcon#about to read 6, iclass 33, count 0 2006.257.15:48:07.63#ibcon#read 6, iclass 33, count 0 2006.257.15:48:07.63#ibcon#end of sib2, iclass 33, count 0 2006.257.15:48:07.63#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:48:07.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:48:07.63#ibcon#[25=BW32\r\n] 2006.257.15:48:07.63#ibcon#*before write, iclass 33, count 0 2006.257.15:48:07.63#ibcon#enter sib2, iclass 33, count 0 2006.257.15:48:07.63#ibcon#flushed, iclass 33, count 0 2006.257.15:48:07.63#ibcon#about to write, iclass 33, count 0 2006.257.15:48:07.63#ibcon#wrote, iclass 33, count 0 2006.257.15:48:07.63#ibcon#about to read 3, iclass 33, count 0 2006.257.15:48:07.66#ibcon#read 3, iclass 33, count 0 2006.257.15:48:07.66#ibcon#about to read 4, iclass 33, count 0 2006.257.15:48:07.66#ibcon#read 4, iclass 33, count 0 2006.257.15:48:07.66#ibcon#about to read 5, iclass 33, count 0 2006.257.15:48:07.66#ibcon#read 5, iclass 33, count 0 2006.257.15:48:07.66#ibcon#about to read 6, iclass 33, count 0 2006.257.15:48:07.66#ibcon#read 6, iclass 33, count 0 2006.257.15:48:07.66#ibcon#end of sib2, iclass 33, count 0 2006.257.15:48:07.66#ibcon#*after write, iclass 33, count 0 2006.257.15:48:07.66#ibcon#*before return 0, iclass 33, count 0 2006.257.15:48:07.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:07.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.15:48:07.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:48:07.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:48:07.66$vck44/vbbw=wide 2006.257.15:48:07.66#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.15:48:07.66#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.15:48:07.66#ibcon#ireg 8 cls_cnt 0 2006.257.15:48:07.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:48:07.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:48:07.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:48:07.73#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:48:07.73#ibcon#first serial, iclass 35, count 0 2006.257.15:48:07.73#ibcon#enter sib2, iclass 35, count 0 2006.257.15:48:07.73#ibcon#flushed, iclass 35, count 0 2006.257.15:48:07.73#ibcon#about to write, iclass 35, count 0 2006.257.15:48:07.73#ibcon#wrote, iclass 35, count 0 2006.257.15:48:07.73#ibcon#about to read 3, iclass 35, count 0 2006.257.15:48:07.75#ibcon#read 3, iclass 35, count 0 2006.257.15:48:07.75#ibcon#about to read 4, iclass 35, count 0 2006.257.15:48:07.75#ibcon#read 4, iclass 35, count 0 2006.257.15:48:07.75#ibcon#about to read 5, iclass 35, count 0 2006.257.15:48:07.75#ibcon#read 5, iclass 35, count 0 2006.257.15:48:07.75#ibcon#about to read 6, iclass 35, count 0 2006.257.15:48:07.75#ibcon#read 6, iclass 35, count 0 2006.257.15:48:07.75#ibcon#end of sib2, iclass 35, count 0 2006.257.15:48:07.75#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:48:07.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:48:07.75#ibcon#[27=BW32\r\n] 2006.257.15:48:07.75#ibcon#*before write, iclass 35, count 0 2006.257.15:48:07.75#ibcon#enter sib2, iclass 35, count 0 2006.257.15:48:07.75#ibcon#flushed, iclass 35, count 0 2006.257.15:48:07.75#ibcon#about to write, iclass 35, count 0 2006.257.15:48:07.75#ibcon#wrote, iclass 35, count 0 2006.257.15:48:07.75#ibcon#about to read 3, iclass 35, count 0 2006.257.15:48:07.78#ibcon#read 3, iclass 35, count 0 2006.257.15:48:07.78#ibcon#about to read 4, iclass 35, count 0 2006.257.15:48:07.78#ibcon#read 4, iclass 35, count 0 2006.257.15:48:07.78#ibcon#about to read 5, iclass 35, count 0 2006.257.15:48:07.78#ibcon#read 5, iclass 35, count 0 2006.257.15:48:07.78#ibcon#about to read 6, iclass 35, count 0 2006.257.15:48:07.78#ibcon#read 6, iclass 35, count 0 2006.257.15:48:07.78#ibcon#end of sib2, iclass 35, count 0 2006.257.15:48:07.78#ibcon#*after write, iclass 35, count 0 2006.257.15:48:07.78#ibcon#*before return 0, iclass 35, count 0 2006.257.15:48:07.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:48:07.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:48:07.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:48:07.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:48:07.78$setupk4/ifdk4 2006.257.15:48:07.78$ifdk4/lo= 2006.257.15:48:07.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:48:07.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:48:07.78$ifdk4/patch= 2006.257.15:48:07.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:48:07.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:48:07.78$setupk4/!*+20s 2006.257.15:48:12.14#abcon#<5=/13 0.9 3.1 17.37 971013.9\r\n> 2006.257.15:48:12.16#abcon#{5=INTERFACE CLEAR} 2006.257.15:48:12.22#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:48:14.14#trakl#Source acquired 2006.257.15:48:15.14#flagr#flagr/antenna,acquired 2006.257.15:48:22.25$setupk4/"tpicd 2006.257.15:48:22.25$setupk4/echo=off 2006.257.15:48:22.25$setupk4/xlog=off 2006.257.15:48:22.25:!2006.257.15:53:18 2006.257.15:53:18.00:preob 2006.257.15:53:19.14/onsource/TRACKING 2006.257.15:53:19.14:!2006.257.15:53:28 2006.257.15:53:28.00:"tape 2006.257.15:53:28.00:"st=record 2006.257.15:53:28.00:data_valid=on 2006.257.15:53:28.00:midob 2006.257.15:53:28.14/onsource/TRACKING 2006.257.15:53:28.14/wx/17.35,1014.0,97 2006.257.15:53:28.20/cable/+6.4849E-03 2006.257.15:53:29.29/va/01,08,usb,yes,31,33 2006.257.15:53:29.29/va/02,07,usb,yes,33,34 2006.257.15:53:29.29/va/03,08,usb,yes,30,32 2006.257.15:53:29.29/va/04,07,usb,yes,34,36 2006.257.15:53:29.29/va/05,04,usb,yes,31,31 2006.257.15:53:29.29/va/06,04,usb,yes,34,34 2006.257.15:53:29.29/va/07,04,usb,yes,35,35 2006.257.15:53:29.29/va/08,04,usb,yes,29,36 2006.257.15:53:29.52/valo/01,524.99,yes,locked 2006.257.15:53:29.52/valo/02,534.99,yes,locked 2006.257.15:53:29.52/valo/03,564.99,yes,locked 2006.257.15:53:29.52/valo/04,624.99,yes,locked 2006.257.15:53:29.52/valo/05,734.99,yes,locked 2006.257.15:53:29.52/valo/06,814.99,yes,locked 2006.257.15:53:29.52/valo/07,864.99,yes,locked 2006.257.15:53:29.52/valo/08,884.99,yes,locked 2006.257.15:53:30.61/vb/01,04,usb,yes,30,28 2006.257.15:53:30.61/vb/02,05,usb,yes,29,29 2006.257.15:53:30.61/vb/03,04,usb,yes,30,33 2006.257.15:53:30.61/vb/04,05,usb,yes,30,29 2006.257.15:53:30.61/vb/05,04,usb,yes,26,29 2006.257.15:53:30.61/vb/06,04,usb,yes,31,27 2006.257.15:53:30.61/vb/07,04,usb,yes,31,31 2006.257.15:53:30.61/vb/08,04,usb,yes,28,32 2006.257.15:53:30.85/vblo/01,629.99,yes,locked 2006.257.15:53:30.85/vblo/02,634.99,yes,locked 2006.257.15:53:30.85/vblo/03,649.99,yes,locked 2006.257.15:53:30.85/vblo/04,679.99,yes,locked 2006.257.15:53:30.85/vblo/05,709.99,yes,locked 2006.257.15:53:30.85/vblo/06,719.99,yes,locked 2006.257.15:53:30.85/vblo/07,734.99,yes,locked 2006.257.15:53:30.85/vblo/08,744.99,yes,locked 2006.257.15:53:31.00/vabw/8 2006.257.15:53:31.15/vbbw/8 2006.257.15:53:31.35/xfe/off,on,15.0 2006.257.15:53:31.73/ifatt/23,28,28,28 2006.257.15:53:32.08/fmout-gps/S +4.55E-07 2006.257.15:53:32.12:!2006.257.15:54:48 2006.257.15:54:48.01:data_valid=off 2006.257.15:54:48.01:"et 2006.257.15:54:48.02:!+3s 2006.257.15:54:51.03:"tape 2006.257.15:54:51.03:postob 2006.257.15:54:51.19/cable/+6.4851E-03 2006.257.15:54:51.19/wx/17.34,1014.0,97 2006.257.15:54:51.25/fmout-gps/S +4.56E-07 2006.257.15:54:51.25:scan_name=257-1557,jd0609,120 2006.257.15:54:51.26:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.257.15:54:52.13#flagr#flagr/antenna,new-source 2006.257.15:54:52.13:checkk5 2006.257.15:54:52.55/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:54:52.95/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:54:53.36/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:54:53.77/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:54:54.16/chk_obsdata//k5ts1/T2571553??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.15:54:54.55/chk_obsdata//k5ts2/T2571553??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.15:54:54.95/chk_obsdata//k5ts3/T2571553??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.15:54:55.34/chk_obsdata//k5ts4/T2571553??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.15:54:56.06/k5log//k5ts1_log_newline 2006.257.15:54:56.78/k5log//k5ts2_log_newline 2006.257.15:54:57.49/k5log//k5ts3_log_newline 2006.257.15:54:58.20/k5log//k5ts4_log_newline 2006.257.15:54:58.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:54:58.22:setupk4=1 2006.257.15:54:58.22$setupk4/echo=on 2006.257.15:54:58.23$setupk4/pcalon 2006.257.15:54:58.23$pcalon/"no phase cal control is implemented here 2006.257.15:54:58.23$setupk4/"tpicd=stop 2006.257.15:54:58.23$setupk4/"rec=synch_on 2006.257.15:54:58.23$setupk4/"rec_mode=128 2006.257.15:54:58.23$setupk4/!* 2006.257.15:54:58.23$setupk4/recpk4 2006.257.15:54:58.23$recpk4/recpatch= 2006.257.15:54:58.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:54:58.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:54:58.23$setupk4/vck44 2006.257.15:54:58.23$vck44/valo=1,524.99 2006.257.15:54:58.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.15:54:58.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.15:54:58.23#ibcon#ireg 17 cls_cnt 0 2006.257.15:54:58.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:54:58.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:54:58.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:54:58.23#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:54:58.23#ibcon#first serial, iclass 20, count 0 2006.257.15:54:58.23#ibcon#enter sib2, iclass 20, count 0 2006.257.15:54:58.23#ibcon#flushed, iclass 20, count 0 2006.257.15:54:58.23#ibcon#about to write, iclass 20, count 0 2006.257.15:54:58.23#ibcon#wrote, iclass 20, count 0 2006.257.15:54:58.23#ibcon#about to read 3, iclass 20, count 0 2006.257.15:54:58.25#ibcon#read 3, iclass 20, count 0 2006.257.15:54:58.25#ibcon#about to read 4, iclass 20, count 0 2006.257.15:54:58.25#ibcon#read 4, iclass 20, count 0 2006.257.15:54:58.25#ibcon#about to read 5, iclass 20, count 0 2006.257.15:54:58.25#ibcon#read 5, iclass 20, count 0 2006.257.15:54:58.25#ibcon#about to read 6, iclass 20, count 0 2006.257.15:54:58.25#ibcon#read 6, iclass 20, count 0 2006.257.15:54:58.25#ibcon#end of sib2, iclass 20, count 0 2006.257.15:54:58.25#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:54:58.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:54:58.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:54:58.25#ibcon#*before write, iclass 20, count 0 2006.257.15:54:58.25#ibcon#enter sib2, iclass 20, count 0 2006.257.15:54:58.25#ibcon#flushed, iclass 20, count 0 2006.257.15:54:58.25#ibcon#about to write, iclass 20, count 0 2006.257.15:54:58.25#ibcon#wrote, iclass 20, count 0 2006.257.15:54:58.25#ibcon#about to read 3, iclass 20, count 0 2006.257.15:54:58.30#ibcon#read 3, iclass 20, count 0 2006.257.15:54:58.30#ibcon#about to read 4, iclass 20, count 0 2006.257.15:54:58.30#ibcon#read 4, iclass 20, count 0 2006.257.15:54:58.30#ibcon#about to read 5, iclass 20, count 0 2006.257.15:54:58.30#ibcon#read 5, iclass 20, count 0 2006.257.15:54:58.30#ibcon#about to read 6, iclass 20, count 0 2006.257.15:54:58.30#ibcon#read 6, iclass 20, count 0 2006.257.15:54:58.30#ibcon#end of sib2, iclass 20, count 0 2006.257.15:54:58.30#ibcon#*after write, iclass 20, count 0 2006.257.15:54:58.30#ibcon#*before return 0, iclass 20, count 0 2006.257.15:54:58.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:54:58.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:54:58.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:54:58.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:54:58.30$vck44/va=1,8 2006.257.15:54:58.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.15:54:58.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.15:54:58.30#ibcon#ireg 11 cls_cnt 2 2006.257.15:54:58.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:54:58.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:54:58.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:54:58.30#ibcon#enter wrdev, iclass 22, count 2 2006.257.15:54:58.30#ibcon#first serial, iclass 22, count 2 2006.257.15:54:58.30#ibcon#enter sib2, iclass 22, count 2 2006.257.15:54:58.30#ibcon#flushed, iclass 22, count 2 2006.257.15:54:58.30#ibcon#about to write, iclass 22, count 2 2006.257.15:54:58.30#ibcon#wrote, iclass 22, count 2 2006.257.15:54:58.30#ibcon#about to read 3, iclass 22, count 2 2006.257.15:54:58.32#ibcon#read 3, iclass 22, count 2 2006.257.15:54:58.32#ibcon#about to read 4, iclass 22, count 2 2006.257.15:54:58.32#ibcon#read 4, iclass 22, count 2 2006.257.15:54:58.32#ibcon#about to read 5, iclass 22, count 2 2006.257.15:54:58.32#ibcon#read 5, iclass 22, count 2 2006.257.15:54:58.32#ibcon#about to read 6, iclass 22, count 2 2006.257.15:54:58.32#ibcon#read 6, iclass 22, count 2 2006.257.15:54:58.32#ibcon#end of sib2, iclass 22, count 2 2006.257.15:54:58.32#ibcon#*mode == 0, iclass 22, count 2 2006.257.15:54:58.32#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.15:54:58.32#ibcon#[25=AT01-08\r\n] 2006.257.15:54:58.32#ibcon#*before write, iclass 22, count 2 2006.257.15:54:58.32#ibcon#enter sib2, iclass 22, count 2 2006.257.15:54:58.32#ibcon#flushed, iclass 22, count 2 2006.257.15:54:58.32#ibcon#about to write, iclass 22, count 2 2006.257.15:54:58.32#ibcon#wrote, iclass 22, count 2 2006.257.15:54:58.32#ibcon#about to read 3, iclass 22, count 2 2006.257.15:54:58.35#ibcon#read 3, iclass 22, count 2 2006.257.15:54:58.35#ibcon#about to read 4, iclass 22, count 2 2006.257.15:54:58.35#ibcon#read 4, iclass 22, count 2 2006.257.15:54:58.35#ibcon#about to read 5, iclass 22, count 2 2006.257.15:54:58.35#ibcon#read 5, iclass 22, count 2 2006.257.15:54:58.35#ibcon#about to read 6, iclass 22, count 2 2006.257.15:54:58.35#ibcon#read 6, iclass 22, count 2 2006.257.15:54:58.35#ibcon#end of sib2, iclass 22, count 2 2006.257.15:54:58.35#ibcon#*after write, iclass 22, count 2 2006.257.15:54:58.35#ibcon#*before return 0, iclass 22, count 2 2006.257.15:54:58.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:54:58.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:54:58.35#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.15:54:58.35#ibcon#ireg 7 cls_cnt 0 2006.257.15:54:58.35#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:54:58.47#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:54:58.47#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:54:58.47#ibcon#enter wrdev, iclass 22, count 0 2006.257.15:54:58.47#ibcon#first serial, iclass 22, count 0 2006.257.15:54:58.47#ibcon#enter sib2, iclass 22, count 0 2006.257.15:54:58.47#ibcon#flushed, iclass 22, count 0 2006.257.15:54:58.47#ibcon#about to write, iclass 22, count 0 2006.257.15:54:58.47#ibcon#wrote, iclass 22, count 0 2006.257.15:54:58.47#ibcon#about to read 3, iclass 22, count 0 2006.257.15:54:58.49#ibcon#read 3, iclass 22, count 0 2006.257.15:54:58.49#ibcon#about to read 4, iclass 22, count 0 2006.257.15:54:58.49#ibcon#read 4, iclass 22, count 0 2006.257.15:54:58.49#ibcon#about to read 5, iclass 22, count 0 2006.257.15:54:58.49#ibcon#read 5, iclass 22, count 0 2006.257.15:54:58.49#ibcon#about to read 6, iclass 22, count 0 2006.257.15:54:58.49#ibcon#read 6, iclass 22, count 0 2006.257.15:54:58.49#ibcon#end of sib2, iclass 22, count 0 2006.257.15:54:58.49#ibcon#*mode == 0, iclass 22, count 0 2006.257.15:54:58.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.15:54:58.49#ibcon#[25=USB\r\n] 2006.257.15:54:58.49#ibcon#*before write, iclass 22, count 0 2006.257.15:54:58.49#ibcon#enter sib2, iclass 22, count 0 2006.257.15:54:58.49#ibcon#flushed, iclass 22, count 0 2006.257.15:54:58.49#ibcon#about to write, iclass 22, count 0 2006.257.15:54:58.49#ibcon#wrote, iclass 22, count 0 2006.257.15:54:58.49#ibcon#about to read 3, iclass 22, count 0 2006.257.15:54:58.52#ibcon#read 3, iclass 22, count 0 2006.257.15:54:58.52#ibcon#about to read 4, iclass 22, count 0 2006.257.15:54:58.52#ibcon#read 4, iclass 22, count 0 2006.257.15:54:58.52#ibcon#about to read 5, iclass 22, count 0 2006.257.15:54:58.52#ibcon#read 5, iclass 22, count 0 2006.257.15:54:58.52#ibcon#about to read 6, iclass 22, count 0 2006.257.15:54:58.52#ibcon#read 6, iclass 22, count 0 2006.257.15:54:58.52#ibcon#end of sib2, iclass 22, count 0 2006.257.15:54:58.52#ibcon#*after write, iclass 22, count 0 2006.257.15:54:58.52#ibcon#*before return 0, iclass 22, count 0 2006.257.15:54:58.52#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:54:58.52#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:54:58.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.15:54:58.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.15:54:58.52$vck44/valo=2,534.99 2006.257.15:54:58.52#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.15:54:58.52#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.15:54:58.52#ibcon#ireg 17 cls_cnt 0 2006.257.15:54:58.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:54:58.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:54:58.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:54:58.52#ibcon#enter wrdev, iclass 24, count 0 2006.257.15:54:58.52#ibcon#first serial, iclass 24, count 0 2006.257.15:54:58.52#ibcon#enter sib2, iclass 24, count 0 2006.257.15:54:58.52#ibcon#flushed, iclass 24, count 0 2006.257.15:54:58.52#ibcon#about to write, iclass 24, count 0 2006.257.15:54:58.52#ibcon#wrote, iclass 24, count 0 2006.257.15:54:58.52#ibcon#about to read 3, iclass 24, count 0 2006.257.15:54:58.54#ibcon#read 3, iclass 24, count 0 2006.257.15:54:58.54#ibcon#about to read 4, iclass 24, count 0 2006.257.15:54:58.54#ibcon#read 4, iclass 24, count 0 2006.257.15:54:58.54#ibcon#about to read 5, iclass 24, count 0 2006.257.15:54:58.54#ibcon#read 5, iclass 24, count 0 2006.257.15:54:58.54#ibcon#about to read 6, iclass 24, count 0 2006.257.15:54:58.54#ibcon#read 6, iclass 24, count 0 2006.257.15:54:58.54#ibcon#end of sib2, iclass 24, count 0 2006.257.15:54:58.54#ibcon#*mode == 0, iclass 24, count 0 2006.257.15:54:58.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.15:54:58.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:54:58.54#ibcon#*before write, iclass 24, count 0 2006.257.15:54:58.54#ibcon#enter sib2, iclass 24, count 0 2006.257.15:54:58.54#ibcon#flushed, iclass 24, count 0 2006.257.15:54:58.54#ibcon#about to write, iclass 24, count 0 2006.257.15:54:58.54#ibcon#wrote, iclass 24, count 0 2006.257.15:54:58.54#ibcon#about to read 3, iclass 24, count 0 2006.257.15:54:58.58#ibcon#read 3, iclass 24, count 0 2006.257.15:54:58.58#ibcon#about to read 4, iclass 24, count 0 2006.257.15:54:58.58#ibcon#read 4, iclass 24, count 0 2006.257.15:54:58.58#ibcon#about to read 5, iclass 24, count 0 2006.257.15:54:58.58#ibcon#read 5, iclass 24, count 0 2006.257.15:54:58.58#ibcon#about to read 6, iclass 24, count 0 2006.257.15:54:58.58#ibcon#read 6, iclass 24, count 0 2006.257.15:54:58.58#ibcon#end of sib2, iclass 24, count 0 2006.257.15:54:58.58#ibcon#*after write, iclass 24, count 0 2006.257.15:54:58.58#ibcon#*before return 0, iclass 24, count 0 2006.257.15:54:58.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:54:58.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:54:58.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.15:54:58.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.15:54:58.58$vck44/va=2,7 2006.257.15:54:58.58#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.15:54:58.58#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.15:54:58.58#ibcon#ireg 11 cls_cnt 2 2006.257.15:54:58.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:54:58.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:54:58.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:54:58.64#ibcon#enter wrdev, iclass 26, count 2 2006.257.15:54:58.64#ibcon#first serial, iclass 26, count 2 2006.257.15:54:58.64#ibcon#enter sib2, iclass 26, count 2 2006.257.15:54:58.64#ibcon#flushed, iclass 26, count 2 2006.257.15:54:58.64#ibcon#about to write, iclass 26, count 2 2006.257.15:54:58.64#ibcon#wrote, iclass 26, count 2 2006.257.15:54:58.64#ibcon#about to read 3, iclass 26, count 2 2006.257.15:54:58.66#ibcon#read 3, iclass 26, count 2 2006.257.15:54:58.66#ibcon#about to read 4, iclass 26, count 2 2006.257.15:54:58.66#ibcon#read 4, iclass 26, count 2 2006.257.15:54:58.66#ibcon#about to read 5, iclass 26, count 2 2006.257.15:54:58.66#ibcon#read 5, iclass 26, count 2 2006.257.15:54:58.66#ibcon#about to read 6, iclass 26, count 2 2006.257.15:54:58.66#ibcon#read 6, iclass 26, count 2 2006.257.15:54:58.66#ibcon#end of sib2, iclass 26, count 2 2006.257.15:54:58.66#ibcon#*mode == 0, iclass 26, count 2 2006.257.15:54:58.66#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.15:54:58.66#ibcon#[25=AT02-07\r\n] 2006.257.15:54:58.66#ibcon#*before write, iclass 26, count 2 2006.257.15:54:58.66#ibcon#enter sib2, iclass 26, count 2 2006.257.15:54:58.66#ibcon#flushed, iclass 26, count 2 2006.257.15:54:58.66#ibcon#about to write, iclass 26, count 2 2006.257.15:54:58.66#ibcon#wrote, iclass 26, count 2 2006.257.15:54:58.66#ibcon#about to read 3, iclass 26, count 2 2006.257.15:54:58.69#ibcon#read 3, iclass 26, count 2 2006.257.15:54:58.69#ibcon#about to read 4, iclass 26, count 2 2006.257.15:54:58.69#ibcon#read 4, iclass 26, count 2 2006.257.15:54:58.69#ibcon#about to read 5, iclass 26, count 2 2006.257.15:54:58.69#ibcon#read 5, iclass 26, count 2 2006.257.15:54:58.69#ibcon#about to read 6, iclass 26, count 2 2006.257.15:54:58.69#ibcon#read 6, iclass 26, count 2 2006.257.15:54:58.69#ibcon#end of sib2, iclass 26, count 2 2006.257.15:54:58.69#ibcon#*after write, iclass 26, count 2 2006.257.15:54:58.69#ibcon#*before return 0, iclass 26, count 2 2006.257.15:54:58.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:54:58.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:54:58.69#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.15:54:58.69#ibcon#ireg 7 cls_cnt 0 2006.257.15:54:58.69#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:54:58.81#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:54:58.81#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:54:58.81#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:54:58.81#ibcon#first serial, iclass 26, count 0 2006.257.15:54:58.81#ibcon#enter sib2, iclass 26, count 0 2006.257.15:54:58.81#ibcon#flushed, iclass 26, count 0 2006.257.15:54:58.81#ibcon#about to write, iclass 26, count 0 2006.257.15:54:58.81#ibcon#wrote, iclass 26, count 0 2006.257.15:54:58.81#ibcon#about to read 3, iclass 26, count 0 2006.257.15:54:58.83#ibcon#read 3, iclass 26, count 0 2006.257.15:54:58.83#ibcon#about to read 4, iclass 26, count 0 2006.257.15:54:58.83#ibcon#read 4, iclass 26, count 0 2006.257.15:54:58.83#ibcon#about to read 5, iclass 26, count 0 2006.257.15:54:58.83#ibcon#read 5, iclass 26, count 0 2006.257.15:54:58.83#ibcon#about to read 6, iclass 26, count 0 2006.257.15:54:58.83#ibcon#read 6, iclass 26, count 0 2006.257.15:54:58.83#ibcon#end of sib2, iclass 26, count 0 2006.257.15:54:58.83#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:54:58.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:54:58.83#ibcon#[25=USB\r\n] 2006.257.15:54:58.83#ibcon#*before write, iclass 26, count 0 2006.257.15:54:58.83#ibcon#enter sib2, iclass 26, count 0 2006.257.15:54:58.83#ibcon#flushed, iclass 26, count 0 2006.257.15:54:58.83#ibcon#about to write, iclass 26, count 0 2006.257.15:54:58.83#ibcon#wrote, iclass 26, count 0 2006.257.15:54:58.83#ibcon#about to read 3, iclass 26, count 0 2006.257.15:54:58.86#ibcon#read 3, iclass 26, count 0 2006.257.15:54:58.86#ibcon#about to read 4, iclass 26, count 0 2006.257.15:54:58.86#ibcon#read 4, iclass 26, count 0 2006.257.15:54:58.86#ibcon#about to read 5, iclass 26, count 0 2006.257.15:54:58.86#ibcon#read 5, iclass 26, count 0 2006.257.15:54:58.86#ibcon#about to read 6, iclass 26, count 0 2006.257.15:54:58.86#ibcon#read 6, iclass 26, count 0 2006.257.15:54:58.86#ibcon#end of sib2, iclass 26, count 0 2006.257.15:54:58.86#ibcon#*after write, iclass 26, count 0 2006.257.15:54:58.86#ibcon#*before return 0, iclass 26, count 0 2006.257.15:54:58.86#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:54:58.86#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:54:58.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:54:58.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:54:58.86$vck44/valo=3,564.99 2006.257.15:54:58.86#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.15:54:58.86#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.15:54:58.86#ibcon#ireg 17 cls_cnt 0 2006.257.15:54:58.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:54:58.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:54:58.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:54:58.86#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:54:58.86#ibcon#first serial, iclass 28, count 0 2006.257.15:54:58.86#ibcon#enter sib2, iclass 28, count 0 2006.257.15:54:58.86#ibcon#flushed, iclass 28, count 0 2006.257.15:54:58.86#ibcon#about to write, iclass 28, count 0 2006.257.15:54:58.86#ibcon#wrote, iclass 28, count 0 2006.257.15:54:58.86#ibcon#about to read 3, iclass 28, count 0 2006.257.15:54:58.88#ibcon#read 3, iclass 28, count 0 2006.257.15:54:58.88#ibcon#about to read 4, iclass 28, count 0 2006.257.15:54:58.88#ibcon#read 4, iclass 28, count 0 2006.257.15:54:58.88#ibcon#about to read 5, iclass 28, count 0 2006.257.15:54:58.88#ibcon#read 5, iclass 28, count 0 2006.257.15:54:58.88#ibcon#about to read 6, iclass 28, count 0 2006.257.15:54:58.88#ibcon#read 6, iclass 28, count 0 2006.257.15:54:58.88#ibcon#end of sib2, iclass 28, count 0 2006.257.15:54:58.88#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:54:58.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:54:58.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:54:58.88#ibcon#*before write, iclass 28, count 0 2006.257.15:54:58.88#ibcon#enter sib2, iclass 28, count 0 2006.257.15:54:58.88#ibcon#flushed, iclass 28, count 0 2006.257.15:54:58.88#ibcon#about to write, iclass 28, count 0 2006.257.15:54:58.88#ibcon#wrote, iclass 28, count 0 2006.257.15:54:58.88#ibcon#about to read 3, iclass 28, count 0 2006.257.15:54:58.92#ibcon#read 3, iclass 28, count 0 2006.257.15:54:58.92#ibcon#about to read 4, iclass 28, count 0 2006.257.15:54:58.92#ibcon#read 4, iclass 28, count 0 2006.257.15:54:58.92#ibcon#about to read 5, iclass 28, count 0 2006.257.15:54:58.92#ibcon#read 5, iclass 28, count 0 2006.257.15:54:58.92#ibcon#about to read 6, iclass 28, count 0 2006.257.15:54:58.92#ibcon#read 6, iclass 28, count 0 2006.257.15:54:58.92#ibcon#end of sib2, iclass 28, count 0 2006.257.15:54:58.92#ibcon#*after write, iclass 28, count 0 2006.257.15:54:58.92#ibcon#*before return 0, iclass 28, count 0 2006.257.15:54:58.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:54:58.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:54:58.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:54:58.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:54:58.92$vck44/va=3,8 2006.257.15:54:58.92#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.15:54:58.92#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.15:54:58.92#ibcon#ireg 11 cls_cnt 2 2006.257.15:54:58.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:54:58.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:54:58.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:54:58.98#ibcon#enter wrdev, iclass 30, count 2 2006.257.15:54:58.98#ibcon#first serial, iclass 30, count 2 2006.257.15:54:58.98#ibcon#enter sib2, iclass 30, count 2 2006.257.15:54:58.98#ibcon#flushed, iclass 30, count 2 2006.257.15:54:58.98#ibcon#about to write, iclass 30, count 2 2006.257.15:54:58.98#ibcon#wrote, iclass 30, count 2 2006.257.15:54:58.98#ibcon#about to read 3, iclass 30, count 2 2006.257.15:54:58.99#abcon#<5=/13 1.2 3.7 17.34 971014.0\r\n> 2006.257.15:54:59.00#ibcon#read 3, iclass 30, count 2 2006.257.15:54:59.00#ibcon#about to read 4, iclass 30, count 2 2006.257.15:54:59.00#ibcon#read 4, iclass 30, count 2 2006.257.15:54:59.00#ibcon#about to read 5, iclass 30, count 2 2006.257.15:54:59.00#ibcon#read 5, iclass 30, count 2 2006.257.15:54:59.00#ibcon#about to read 6, iclass 30, count 2 2006.257.15:54:59.00#ibcon#read 6, iclass 30, count 2 2006.257.15:54:59.00#ibcon#end of sib2, iclass 30, count 2 2006.257.15:54:59.00#ibcon#*mode == 0, iclass 30, count 2 2006.257.15:54:59.00#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.15:54:59.00#ibcon#[25=AT03-08\r\n] 2006.257.15:54:59.00#ibcon#*before write, iclass 30, count 2 2006.257.15:54:59.00#ibcon#enter sib2, iclass 30, count 2 2006.257.15:54:59.00#ibcon#flushed, iclass 30, count 2 2006.257.15:54:59.00#ibcon#about to write, iclass 30, count 2 2006.257.15:54:59.00#ibcon#wrote, iclass 30, count 2 2006.257.15:54:59.00#ibcon#about to read 3, iclass 30, count 2 2006.257.15:54:59.01#abcon#{5=INTERFACE CLEAR} 2006.257.15:54:59.03#ibcon#read 3, iclass 30, count 2 2006.257.15:54:59.03#ibcon#about to read 4, iclass 30, count 2 2006.257.15:54:59.03#ibcon#read 4, iclass 30, count 2 2006.257.15:54:59.03#ibcon#about to read 5, iclass 30, count 2 2006.257.15:54:59.03#ibcon#read 5, iclass 30, count 2 2006.257.15:54:59.03#ibcon#about to read 6, iclass 30, count 2 2006.257.15:54:59.03#ibcon#read 6, iclass 30, count 2 2006.257.15:54:59.03#ibcon#end of sib2, iclass 30, count 2 2006.257.15:54:59.03#ibcon#*after write, iclass 30, count 2 2006.257.15:54:59.03#ibcon#*before return 0, iclass 30, count 2 2006.257.15:54:59.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:54:59.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:54:59.03#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.15:54:59.03#ibcon#ireg 7 cls_cnt 0 2006.257.15:54:59.03#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:54:59.07#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:54:59.15#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:54:59.15#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:54:59.15#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:54:59.15#ibcon#first serial, iclass 30, count 0 2006.257.15:54:59.15#ibcon#enter sib2, iclass 30, count 0 2006.257.15:54:59.15#ibcon#flushed, iclass 30, count 0 2006.257.15:54:59.15#ibcon#about to write, iclass 30, count 0 2006.257.15:54:59.15#ibcon#wrote, iclass 30, count 0 2006.257.15:54:59.15#ibcon#about to read 3, iclass 30, count 0 2006.257.15:54:59.17#ibcon#read 3, iclass 30, count 0 2006.257.15:54:59.17#ibcon#about to read 4, iclass 30, count 0 2006.257.15:54:59.17#ibcon#read 4, iclass 30, count 0 2006.257.15:54:59.17#ibcon#about to read 5, iclass 30, count 0 2006.257.15:54:59.17#ibcon#read 5, iclass 30, count 0 2006.257.15:54:59.17#ibcon#about to read 6, iclass 30, count 0 2006.257.15:54:59.17#ibcon#read 6, iclass 30, count 0 2006.257.15:54:59.17#ibcon#end of sib2, iclass 30, count 0 2006.257.15:54:59.17#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:54:59.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:54:59.17#ibcon#[25=USB\r\n] 2006.257.15:54:59.17#ibcon#*before write, iclass 30, count 0 2006.257.15:54:59.17#ibcon#enter sib2, iclass 30, count 0 2006.257.15:54:59.17#ibcon#flushed, iclass 30, count 0 2006.257.15:54:59.17#ibcon#about to write, iclass 30, count 0 2006.257.15:54:59.17#ibcon#wrote, iclass 30, count 0 2006.257.15:54:59.17#ibcon#about to read 3, iclass 30, count 0 2006.257.15:54:59.20#ibcon#read 3, iclass 30, count 0 2006.257.15:54:59.20#ibcon#about to read 4, iclass 30, count 0 2006.257.15:54:59.20#ibcon#read 4, iclass 30, count 0 2006.257.15:54:59.20#ibcon#about to read 5, iclass 30, count 0 2006.257.15:54:59.20#ibcon#read 5, iclass 30, count 0 2006.257.15:54:59.20#ibcon#about to read 6, iclass 30, count 0 2006.257.15:54:59.20#ibcon#read 6, iclass 30, count 0 2006.257.15:54:59.20#ibcon#end of sib2, iclass 30, count 0 2006.257.15:54:59.20#ibcon#*after write, iclass 30, count 0 2006.257.15:54:59.20#ibcon#*before return 0, iclass 30, count 0 2006.257.15:54:59.20#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:54:59.20#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:54:59.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:54:59.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:54:59.20$vck44/valo=4,624.99 2006.257.15:54:59.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.15:54:59.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.15:54:59.20#ibcon#ireg 17 cls_cnt 0 2006.257.15:54:59.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:54:59.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:54:59.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:54:59.20#ibcon#enter wrdev, iclass 36, count 0 2006.257.15:54:59.20#ibcon#first serial, iclass 36, count 0 2006.257.15:54:59.20#ibcon#enter sib2, iclass 36, count 0 2006.257.15:54:59.20#ibcon#flushed, iclass 36, count 0 2006.257.15:54:59.20#ibcon#about to write, iclass 36, count 0 2006.257.15:54:59.20#ibcon#wrote, iclass 36, count 0 2006.257.15:54:59.20#ibcon#about to read 3, iclass 36, count 0 2006.257.15:54:59.22#ibcon#read 3, iclass 36, count 0 2006.257.15:54:59.22#ibcon#about to read 4, iclass 36, count 0 2006.257.15:54:59.22#ibcon#read 4, iclass 36, count 0 2006.257.15:54:59.22#ibcon#about to read 5, iclass 36, count 0 2006.257.15:54:59.22#ibcon#read 5, iclass 36, count 0 2006.257.15:54:59.22#ibcon#about to read 6, iclass 36, count 0 2006.257.15:54:59.22#ibcon#read 6, iclass 36, count 0 2006.257.15:54:59.22#ibcon#end of sib2, iclass 36, count 0 2006.257.15:54:59.22#ibcon#*mode == 0, iclass 36, count 0 2006.257.15:54:59.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.15:54:59.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:54:59.22#ibcon#*before write, iclass 36, count 0 2006.257.15:54:59.22#ibcon#enter sib2, iclass 36, count 0 2006.257.15:54:59.22#ibcon#flushed, iclass 36, count 0 2006.257.15:54:59.22#ibcon#about to write, iclass 36, count 0 2006.257.15:54:59.22#ibcon#wrote, iclass 36, count 0 2006.257.15:54:59.22#ibcon#about to read 3, iclass 36, count 0 2006.257.15:54:59.26#ibcon#read 3, iclass 36, count 0 2006.257.15:54:59.26#ibcon#about to read 4, iclass 36, count 0 2006.257.15:54:59.26#ibcon#read 4, iclass 36, count 0 2006.257.15:54:59.26#ibcon#about to read 5, iclass 36, count 0 2006.257.15:54:59.26#ibcon#read 5, iclass 36, count 0 2006.257.15:54:59.26#ibcon#about to read 6, iclass 36, count 0 2006.257.15:54:59.26#ibcon#read 6, iclass 36, count 0 2006.257.15:54:59.26#ibcon#end of sib2, iclass 36, count 0 2006.257.15:54:59.26#ibcon#*after write, iclass 36, count 0 2006.257.15:54:59.26#ibcon#*before return 0, iclass 36, count 0 2006.257.15:54:59.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:54:59.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:54:59.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.15:54:59.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.15:54:59.26$vck44/va=4,7 2006.257.15:54:59.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.15:54:59.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.15:54:59.26#ibcon#ireg 11 cls_cnt 2 2006.257.15:54:59.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:54:59.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:54:59.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:54:59.32#ibcon#enter wrdev, iclass 38, count 2 2006.257.15:54:59.32#ibcon#first serial, iclass 38, count 2 2006.257.15:54:59.32#ibcon#enter sib2, iclass 38, count 2 2006.257.15:54:59.32#ibcon#flushed, iclass 38, count 2 2006.257.15:54:59.32#ibcon#about to write, iclass 38, count 2 2006.257.15:54:59.32#ibcon#wrote, iclass 38, count 2 2006.257.15:54:59.32#ibcon#about to read 3, iclass 38, count 2 2006.257.15:54:59.34#ibcon#read 3, iclass 38, count 2 2006.257.15:54:59.34#ibcon#about to read 4, iclass 38, count 2 2006.257.15:54:59.34#ibcon#read 4, iclass 38, count 2 2006.257.15:54:59.34#ibcon#about to read 5, iclass 38, count 2 2006.257.15:54:59.34#ibcon#read 5, iclass 38, count 2 2006.257.15:54:59.34#ibcon#about to read 6, iclass 38, count 2 2006.257.15:54:59.34#ibcon#read 6, iclass 38, count 2 2006.257.15:54:59.34#ibcon#end of sib2, iclass 38, count 2 2006.257.15:54:59.34#ibcon#*mode == 0, iclass 38, count 2 2006.257.15:54:59.34#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.15:54:59.34#ibcon#[25=AT04-07\r\n] 2006.257.15:54:59.34#ibcon#*before write, iclass 38, count 2 2006.257.15:54:59.34#ibcon#enter sib2, iclass 38, count 2 2006.257.15:54:59.34#ibcon#flushed, iclass 38, count 2 2006.257.15:54:59.34#ibcon#about to write, iclass 38, count 2 2006.257.15:54:59.35#ibcon#wrote, iclass 38, count 2 2006.257.15:54:59.35#ibcon#about to read 3, iclass 38, count 2 2006.257.15:54:59.38#ibcon#read 3, iclass 38, count 2 2006.257.15:54:59.38#ibcon#about to read 4, iclass 38, count 2 2006.257.15:54:59.38#ibcon#read 4, iclass 38, count 2 2006.257.15:54:59.38#ibcon#about to read 5, iclass 38, count 2 2006.257.15:54:59.38#ibcon#read 5, iclass 38, count 2 2006.257.15:54:59.38#ibcon#about to read 6, iclass 38, count 2 2006.257.15:54:59.38#ibcon#read 6, iclass 38, count 2 2006.257.15:54:59.38#ibcon#end of sib2, iclass 38, count 2 2006.257.15:54:59.38#ibcon#*after write, iclass 38, count 2 2006.257.15:54:59.38#ibcon#*before return 0, iclass 38, count 2 2006.257.15:54:59.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:54:59.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:54:59.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.15:54:59.38#ibcon#ireg 7 cls_cnt 0 2006.257.15:54:59.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:54:59.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:54:59.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:54:59.50#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:54:59.50#ibcon#first serial, iclass 38, count 0 2006.257.15:54:59.50#ibcon#enter sib2, iclass 38, count 0 2006.257.15:54:59.50#ibcon#flushed, iclass 38, count 0 2006.257.15:54:59.50#ibcon#about to write, iclass 38, count 0 2006.257.15:54:59.50#ibcon#wrote, iclass 38, count 0 2006.257.15:54:59.50#ibcon#about to read 3, iclass 38, count 0 2006.257.15:54:59.52#ibcon#read 3, iclass 38, count 0 2006.257.15:54:59.52#ibcon#about to read 4, iclass 38, count 0 2006.257.15:54:59.52#ibcon#read 4, iclass 38, count 0 2006.257.15:54:59.52#ibcon#about to read 5, iclass 38, count 0 2006.257.15:54:59.52#ibcon#read 5, iclass 38, count 0 2006.257.15:54:59.52#ibcon#about to read 6, iclass 38, count 0 2006.257.15:54:59.52#ibcon#read 6, iclass 38, count 0 2006.257.15:54:59.52#ibcon#end of sib2, iclass 38, count 0 2006.257.15:54:59.52#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:54:59.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:54:59.52#ibcon#[25=USB\r\n] 2006.257.15:54:59.52#ibcon#*before write, iclass 38, count 0 2006.257.15:54:59.52#ibcon#enter sib2, iclass 38, count 0 2006.257.15:54:59.52#ibcon#flushed, iclass 38, count 0 2006.257.15:54:59.52#ibcon#about to write, iclass 38, count 0 2006.257.15:54:59.52#ibcon#wrote, iclass 38, count 0 2006.257.15:54:59.52#ibcon#about to read 3, iclass 38, count 0 2006.257.15:54:59.55#ibcon#read 3, iclass 38, count 0 2006.257.15:54:59.55#ibcon#about to read 4, iclass 38, count 0 2006.257.15:54:59.55#ibcon#read 4, iclass 38, count 0 2006.257.15:54:59.55#ibcon#about to read 5, iclass 38, count 0 2006.257.15:54:59.55#ibcon#read 5, iclass 38, count 0 2006.257.15:54:59.55#ibcon#about to read 6, iclass 38, count 0 2006.257.15:54:59.55#ibcon#read 6, iclass 38, count 0 2006.257.15:54:59.55#ibcon#end of sib2, iclass 38, count 0 2006.257.15:54:59.55#ibcon#*after write, iclass 38, count 0 2006.257.15:54:59.55#ibcon#*before return 0, iclass 38, count 0 2006.257.15:54:59.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:54:59.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:54:59.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:54:59.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:54:59.55$vck44/valo=5,734.99 2006.257.15:54:59.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.15:54:59.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.15:54:59.55#ibcon#ireg 17 cls_cnt 0 2006.257.15:54:59.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:54:59.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:54:59.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:54:59.55#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:54:59.55#ibcon#first serial, iclass 40, count 0 2006.257.15:54:59.55#ibcon#enter sib2, iclass 40, count 0 2006.257.15:54:59.55#ibcon#flushed, iclass 40, count 0 2006.257.15:54:59.55#ibcon#about to write, iclass 40, count 0 2006.257.15:54:59.55#ibcon#wrote, iclass 40, count 0 2006.257.15:54:59.55#ibcon#about to read 3, iclass 40, count 0 2006.257.15:54:59.57#ibcon#read 3, iclass 40, count 0 2006.257.15:54:59.57#ibcon#about to read 4, iclass 40, count 0 2006.257.15:54:59.57#ibcon#read 4, iclass 40, count 0 2006.257.15:54:59.57#ibcon#about to read 5, iclass 40, count 0 2006.257.15:54:59.57#ibcon#read 5, iclass 40, count 0 2006.257.15:54:59.57#ibcon#about to read 6, iclass 40, count 0 2006.257.15:54:59.57#ibcon#read 6, iclass 40, count 0 2006.257.15:54:59.57#ibcon#end of sib2, iclass 40, count 0 2006.257.15:54:59.57#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:54:59.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:54:59.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:54:59.57#ibcon#*before write, iclass 40, count 0 2006.257.15:54:59.57#ibcon#enter sib2, iclass 40, count 0 2006.257.15:54:59.57#ibcon#flushed, iclass 40, count 0 2006.257.15:54:59.57#ibcon#about to write, iclass 40, count 0 2006.257.15:54:59.57#ibcon#wrote, iclass 40, count 0 2006.257.15:54:59.57#ibcon#about to read 3, iclass 40, count 0 2006.257.15:54:59.61#ibcon#read 3, iclass 40, count 0 2006.257.15:54:59.61#ibcon#about to read 4, iclass 40, count 0 2006.257.15:54:59.61#ibcon#read 4, iclass 40, count 0 2006.257.15:54:59.61#ibcon#about to read 5, iclass 40, count 0 2006.257.15:54:59.61#ibcon#read 5, iclass 40, count 0 2006.257.15:54:59.61#ibcon#about to read 6, iclass 40, count 0 2006.257.15:54:59.61#ibcon#read 6, iclass 40, count 0 2006.257.15:54:59.61#ibcon#end of sib2, iclass 40, count 0 2006.257.15:54:59.61#ibcon#*after write, iclass 40, count 0 2006.257.15:54:59.61#ibcon#*before return 0, iclass 40, count 0 2006.257.15:54:59.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:54:59.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:54:59.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:54:59.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:54:59.61$vck44/va=5,4 2006.257.15:54:59.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.15:54:59.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.15:54:59.61#ibcon#ireg 11 cls_cnt 2 2006.257.15:54:59.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:54:59.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:54:59.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:54:59.67#ibcon#enter wrdev, iclass 4, count 2 2006.257.15:54:59.67#ibcon#first serial, iclass 4, count 2 2006.257.15:54:59.67#ibcon#enter sib2, iclass 4, count 2 2006.257.15:54:59.67#ibcon#flushed, iclass 4, count 2 2006.257.15:54:59.67#ibcon#about to write, iclass 4, count 2 2006.257.15:54:59.67#ibcon#wrote, iclass 4, count 2 2006.257.15:54:59.67#ibcon#about to read 3, iclass 4, count 2 2006.257.15:54:59.69#ibcon#read 3, iclass 4, count 2 2006.257.15:54:59.69#ibcon#about to read 4, iclass 4, count 2 2006.257.15:54:59.69#ibcon#read 4, iclass 4, count 2 2006.257.15:54:59.69#ibcon#about to read 5, iclass 4, count 2 2006.257.15:54:59.69#ibcon#read 5, iclass 4, count 2 2006.257.15:54:59.69#ibcon#about to read 6, iclass 4, count 2 2006.257.15:54:59.69#ibcon#read 6, iclass 4, count 2 2006.257.15:54:59.69#ibcon#end of sib2, iclass 4, count 2 2006.257.15:54:59.69#ibcon#*mode == 0, iclass 4, count 2 2006.257.15:54:59.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.15:54:59.69#ibcon#[25=AT05-04\r\n] 2006.257.15:54:59.69#ibcon#*before write, iclass 4, count 2 2006.257.15:54:59.69#ibcon#enter sib2, iclass 4, count 2 2006.257.15:54:59.69#ibcon#flushed, iclass 4, count 2 2006.257.15:54:59.69#ibcon#about to write, iclass 4, count 2 2006.257.15:54:59.69#ibcon#wrote, iclass 4, count 2 2006.257.15:54:59.69#ibcon#about to read 3, iclass 4, count 2 2006.257.15:54:59.72#ibcon#read 3, iclass 4, count 2 2006.257.15:54:59.72#ibcon#about to read 4, iclass 4, count 2 2006.257.15:54:59.72#ibcon#read 4, iclass 4, count 2 2006.257.15:54:59.72#ibcon#about to read 5, iclass 4, count 2 2006.257.15:54:59.72#ibcon#read 5, iclass 4, count 2 2006.257.15:54:59.72#ibcon#about to read 6, iclass 4, count 2 2006.257.15:54:59.72#ibcon#read 6, iclass 4, count 2 2006.257.15:54:59.72#ibcon#end of sib2, iclass 4, count 2 2006.257.15:54:59.72#ibcon#*after write, iclass 4, count 2 2006.257.15:54:59.72#ibcon#*before return 0, iclass 4, count 2 2006.257.15:54:59.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:54:59.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:54:59.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.15:54:59.72#ibcon#ireg 7 cls_cnt 0 2006.257.15:54:59.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:54:59.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:54:59.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:54:59.84#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:54:59.84#ibcon#first serial, iclass 4, count 0 2006.257.15:54:59.84#ibcon#enter sib2, iclass 4, count 0 2006.257.15:54:59.84#ibcon#flushed, iclass 4, count 0 2006.257.15:54:59.84#ibcon#about to write, iclass 4, count 0 2006.257.15:54:59.84#ibcon#wrote, iclass 4, count 0 2006.257.15:54:59.84#ibcon#about to read 3, iclass 4, count 0 2006.257.15:54:59.86#ibcon#read 3, iclass 4, count 0 2006.257.15:54:59.86#ibcon#about to read 4, iclass 4, count 0 2006.257.15:54:59.86#ibcon#read 4, iclass 4, count 0 2006.257.15:54:59.86#ibcon#about to read 5, iclass 4, count 0 2006.257.15:54:59.86#ibcon#read 5, iclass 4, count 0 2006.257.15:54:59.86#ibcon#about to read 6, iclass 4, count 0 2006.257.15:54:59.86#ibcon#read 6, iclass 4, count 0 2006.257.15:54:59.86#ibcon#end of sib2, iclass 4, count 0 2006.257.15:54:59.86#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:54:59.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:54:59.86#ibcon#[25=USB\r\n] 2006.257.15:54:59.86#ibcon#*before write, iclass 4, count 0 2006.257.15:54:59.86#ibcon#enter sib2, iclass 4, count 0 2006.257.15:54:59.86#ibcon#flushed, iclass 4, count 0 2006.257.15:54:59.86#ibcon#about to write, iclass 4, count 0 2006.257.15:54:59.86#ibcon#wrote, iclass 4, count 0 2006.257.15:54:59.86#ibcon#about to read 3, iclass 4, count 0 2006.257.15:54:59.89#ibcon#read 3, iclass 4, count 0 2006.257.15:54:59.89#ibcon#about to read 4, iclass 4, count 0 2006.257.15:54:59.89#ibcon#read 4, iclass 4, count 0 2006.257.15:54:59.89#ibcon#about to read 5, iclass 4, count 0 2006.257.15:54:59.89#ibcon#read 5, iclass 4, count 0 2006.257.15:54:59.89#ibcon#about to read 6, iclass 4, count 0 2006.257.15:54:59.89#ibcon#read 6, iclass 4, count 0 2006.257.15:54:59.89#ibcon#end of sib2, iclass 4, count 0 2006.257.15:54:59.89#ibcon#*after write, iclass 4, count 0 2006.257.15:54:59.89#ibcon#*before return 0, iclass 4, count 0 2006.257.15:54:59.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:54:59.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:54:59.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:54:59.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:54:59.89$vck44/valo=6,814.99 2006.257.15:54:59.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.15:54:59.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.15:54:59.89#ibcon#ireg 17 cls_cnt 0 2006.257.15:54:59.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:54:59.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:54:59.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:54:59.89#ibcon#enter wrdev, iclass 6, count 0 2006.257.15:54:59.89#ibcon#first serial, iclass 6, count 0 2006.257.15:54:59.89#ibcon#enter sib2, iclass 6, count 0 2006.257.15:54:59.89#ibcon#flushed, iclass 6, count 0 2006.257.15:54:59.89#ibcon#about to write, iclass 6, count 0 2006.257.15:54:59.89#ibcon#wrote, iclass 6, count 0 2006.257.15:54:59.89#ibcon#about to read 3, iclass 6, count 0 2006.257.15:54:59.91#ibcon#read 3, iclass 6, count 0 2006.257.15:54:59.91#ibcon#about to read 4, iclass 6, count 0 2006.257.15:54:59.91#ibcon#read 4, iclass 6, count 0 2006.257.15:54:59.91#ibcon#about to read 5, iclass 6, count 0 2006.257.15:54:59.91#ibcon#read 5, iclass 6, count 0 2006.257.15:54:59.91#ibcon#about to read 6, iclass 6, count 0 2006.257.15:54:59.91#ibcon#read 6, iclass 6, count 0 2006.257.15:54:59.91#ibcon#end of sib2, iclass 6, count 0 2006.257.15:54:59.91#ibcon#*mode == 0, iclass 6, count 0 2006.257.15:54:59.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.15:54:59.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:54:59.91#ibcon#*before write, iclass 6, count 0 2006.257.15:54:59.91#ibcon#enter sib2, iclass 6, count 0 2006.257.15:54:59.91#ibcon#flushed, iclass 6, count 0 2006.257.15:54:59.91#ibcon#about to write, iclass 6, count 0 2006.257.15:54:59.91#ibcon#wrote, iclass 6, count 0 2006.257.15:54:59.91#ibcon#about to read 3, iclass 6, count 0 2006.257.15:54:59.95#ibcon#read 3, iclass 6, count 0 2006.257.15:54:59.95#ibcon#about to read 4, iclass 6, count 0 2006.257.15:54:59.95#ibcon#read 4, iclass 6, count 0 2006.257.15:54:59.95#ibcon#about to read 5, iclass 6, count 0 2006.257.15:54:59.95#ibcon#read 5, iclass 6, count 0 2006.257.15:54:59.95#ibcon#about to read 6, iclass 6, count 0 2006.257.15:54:59.95#ibcon#read 6, iclass 6, count 0 2006.257.15:54:59.95#ibcon#end of sib2, iclass 6, count 0 2006.257.15:54:59.95#ibcon#*after write, iclass 6, count 0 2006.257.15:54:59.95#ibcon#*before return 0, iclass 6, count 0 2006.257.15:54:59.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:54:59.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:54:59.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.15:54:59.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.15:54:59.95$vck44/va=6,4 2006.257.15:54:59.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.15:54:59.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.15:54:59.95#ibcon#ireg 11 cls_cnt 2 2006.257.15:54:59.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:00.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:00.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:00.01#ibcon#enter wrdev, iclass 10, count 2 2006.257.15:55:00.01#ibcon#first serial, iclass 10, count 2 2006.257.15:55:00.01#ibcon#enter sib2, iclass 10, count 2 2006.257.15:55:00.01#ibcon#flushed, iclass 10, count 2 2006.257.15:55:00.01#ibcon#about to write, iclass 10, count 2 2006.257.15:55:00.01#ibcon#wrote, iclass 10, count 2 2006.257.15:55:00.01#ibcon#about to read 3, iclass 10, count 2 2006.257.15:55:00.03#ibcon#read 3, iclass 10, count 2 2006.257.15:55:00.03#ibcon#about to read 4, iclass 10, count 2 2006.257.15:55:00.03#ibcon#read 4, iclass 10, count 2 2006.257.15:55:00.03#ibcon#about to read 5, iclass 10, count 2 2006.257.15:55:00.03#ibcon#read 5, iclass 10, count 2 2006.257.15:55:00.03#ibcon#about to read 6, iclass 10, count 2 2006.257.15:55:00.03#ibcon#read 6, iclass 10, count 2 2006.257.15:55:00.03#ibcon#end of sib2, iclass 10, count 2 2006.257.15:55:00.03#ibcon#*mode == 0, iclass 10, count 2 2006.257.15:55:00.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.15:55:00.03#ibcon#[25=AT06-04\r\n] 2006.257.15:55:00.03#ibcon#*before write, iclass 10, count 2 2006.257.15:55:00.03#ibcon#enter sib2, iclass 10, count 2 2006.257.15:55:00.03#ibcon#flushed, iclass 10, count 2 2006.257.15:55:00.03#ibcon#about to write, iclass 10, count 2 2006.257.15:55:00.03#ibcon#wrote, iclass 10, count 2 2006.257.15:55:00.03#ibcon#about to read 3, iclass 10, count 2 2006.257.15:55:00.06#ibcon#read 3, iclass 10, count 2 2006.257.15:55:00.06#ibcon#about to read 4, iclass 10, count 2 2006.257.15:55:00.06#ibcon#read 4, iclass 10, count 2 2006.257.15:55:00.06#ibcon#about to read 5, iclass 10, count 2 2006.257.15:55:00.06#ibcon#read 5, iclass 10, count 2 2006.257.15:55:00.06#ibcon#about to read 6, iclass 10, count 2 2006.257.15:55:00.06#ibcon#read 6, iclass 10, count 2 2006.257.15:55:00.06#ibcon#end of sib2, iclass 10, count 2 2006.257.15:55:00.06#ibcon#*after write, iclass 10, count 2 2006.257.15:55:00.06#ibcon#*before return 0, iclass 10, count 2 2006.257.15:55:00.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:00.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:00.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.15:55:00.06#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:00.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:00.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:00.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:00.18#ibcon#enter wrdev, iclass 10, count 0 2006.257.15:55:00.18#ibcon#first serial, iclass 10, count 0 2006.257.15:55:00.18#ibcon#enter sib2, iclass 10, count 0 2006.257.15:55:00.18#ibcon#flushed, iclass 10, count 0 2006.257.15:55:00.18#ibcon#about to write, iclass 10, count 0 2006.257.15:55:00.18#ibcon#wrote, iclass 10, count 0 2006.257.15:55:00.18#ibcon#about to read 3, iclass 10, count 0 2006.257.15:55:00.20#ibcon#read 3, iclass 10, count 0 2006.257.15:55:00.20#ibcon#about to read 4, iclass 10, count 0 2006.257.15:55:00.20#ibcon#read 4, iclass 10, count 0 2006.257.15:55:00.20#ibcon#about to read 5, iclass 10, count 0 2006.257.15:55:00.20#ibcon#read 5, iclass 10, count 0 2006.257.15:55:00.20#ibcon#about to read 6, iclass 10, count 0 2006.257.15:55:00.20#ibcon#read 6, iclass 10, count 0 2006.257.15:55:00.20#ibcon#end of sib2, iclass 10, count 0 2006.257.15:55:00.20#ibcon#*mode == 0, iclass 10, count 0 2006.257.15:55:00.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.15:55:00.20#ibcon#[25=USB\r\n] 2006.257.15:55:00.20#ibcon#*before write, iclass 10, count 0 2006.257.15:55:00.20#ibcon#enter sib2, iclass 10, count 0 2006.257.15:55:00.20#ibcon#flushed, iclass 10, count 0 2006.257.15:55:00.20#ibcon#about to write, iclass 10, count 0 2006.257.15:55:00.20#ibcon#wrote, iclass 10, count 0 2006.257.15:55:00.20#ibcon#about to read 3, iclass 10, count 0 2006.257.15:55:00.23#ibcon#read 3, iclass 10, count 0 2006.257.15:55:00.23#ibcon#about to read 4, iclass 10, count 0 2006.257.15:55:00.23#ibcon#read 4, iclass 10, count 0 2006.257.15:55:00.23#ibcon#about to read 5, iclass 10, count 0 2006.257.15:55:00.23#ibcon#read 5, iclass 10, count 0 2006.257.15:55:00.23#ibcon#about to read 6, iclass 10, count 0 2006.257.15:55:00.23#ibcon#read 6, iclass 10, count 0 2006.257.15:55:00.23#ibcon#end of sib2, iclass 10, count 0 2006.257.15:55:00.23#ibcon#*after write, iclass 10, count 0 2006.257.15:55:00.23#ibcon#*before return 0, iclass 10, count 0 2006.257.15:55:00.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:00.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:00.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.15:55:00.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.15:55:00.23$vck44/valo=7,864.99 2006.257.15:55:00.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.15:55:00.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.15:55:00.23#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:00.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:00.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:00.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:00.23#ibcon#enter wrdev, iclass 12, count 0 2006.257.15:55:00.23#ibcon#first serial, iclass 12, count 0 2006.257.15:55:00.23#ibcon#enter sib2, iclass 12, count 0 2006.257.15:55:00.23#ibcon#flushed, iclass 12, count 0 2006.257.15:55:00.23#ibcon#about to write, iclass 12, count 0 2006.257.15:55:00.23#ibcon#wrote, iclass 12, count 0 2006.257.15:55:00.23#ibcon#about to read 3, iclass 12, count 0 2006.257.15:55:00.25#ibcon#read 3, iclass 12, count 0 2006.257.15:55:00.25#ibcon#about to read 4, iclass 12, count 0 2006.257.15:55:00.25#ibcon#read 4, iclass 12, count 0 2006.257.15:55:00.25#ibcon#about to read 5, iclass 12, count 0 2006.257.15:55:00.25#ibcon#read 5, iclass 12, count 0 2006.257.15:55:00.25#ibcon#about to read 6, iclass 12, count 0 2006.257.15:55:00.25#ibcon#read 6, iclass 12, count 0 2006.257.15:55:00.25#ibcon#end of sib2, iclass 12, count 0 2006.257.15:55:00.25#ibcon#*mode == 0, iclass 12, count 0 2006.257.15:55:00.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.15:55:00.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:55:00.25#ibcon#*before write, iclass 12, count 0 2006.257.15:55:00.25#ibcon#enter sib2, iclass 12, count 0 2006.257.15:55:00.25#ibcon#flushed, iclass 12, count 0 2006.257.15:55:00.25#ibcon#about to write, iclass 12, count 0 2006.257.15:55:00.25#ibcon#wrote, iclass 12, count 0 2006.257.15:55:00.25#ibcon#about to read 3, iclass 12, count 0 2006.257.15:55:00.29#ibcon#read 3, iclass 12, count 0 2006.257.15:55:00.29#ibcon#about to read 4, iclass 12, count 0 2006.257.15:55:00.29#ibcon#read 4, iclass 12, count 0 2006.257.15:55:00.29#ibcon#about to read 5, iclass 12, count 0 2006.257.15:55:00.29#ibcon#read 5, iclass 12, count 0 2006.257.15:55:00.29#ibcon#about to read 6, iclass 12, count 0 2006.257.15:55:00.29#ibcon#read 6, iclass 12, count 0 2006.257.15:55:00.29#ibcon#end of sib2, iclass 12, count 0 2006.257.15:55:00.29#ibcon#*after write, iclass 12, count 0 2006.257.15:55:00.29#ibcon#*before return 0, iclass 12, count 0 2006.257.15:55:00.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:00.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:00.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.15:55:00.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.15:55:00.29$vck44/va=7,4 2006.257.15:55:00.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.15:55:00.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.15:55:00.29#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:00.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:00.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:00.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:00.35#ibcon#enter wrdev, iclass 14, count 2 2006.257.15:55:00.35#ibcon#first serial, iclass 14, count 2 2006.257.15:55:00.35#ibcon#enter sib2, iclass 14, count 2 2006.257.15:55:00.35#ibcon#flushed, iclass 14, count 2 2006.257.15:55:00.35#ibcon#about to write, iclass 14, count 2 2006.257.15:55:00.35#ibcon#wrote, iclass 14, count 2 2006.257.15:55:00.35#ibcon#about to read 3, iclass 14, count 2 2006.257.15:55:00.37#ibcon#read 3, iclass 14, count 2 2006.257.15:55:00.37#ibcon#about to read 4, iclass 14, count 2 2006.257.15:55:00.37#ibcon#read 4, iclass 14, count 2 2006.257.15:55:00.37#ibcon#about to read 5, iclass 14, count 2 2006.257.15:55:00.37#ibcon#read 5, iclass 14, count 2 2006.257.15:55:00.37#ibcon#about to read 6, iclass 14, count 2 2006.257.15:55:00.37#ibcon#read 6, iclass 14, count 2 2006.257.15:55:00.37#ibcon#end of sib2, iclass 14, count 2 2006.257.15:55:00.37#ibcon#*mode == 0, iclass 14, count 2 2006.257.15:55:00.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.15:55:00.37#ibcon#[25=AT07-04\r\n] 2006.257.15:55:00.37#ibcon#*before write, iclass 14, count 2 2006.257.15:55:00.37#ibcon#enter sib2, iclass 14, count 2 2006.257.15:55:00.37#ibcon#flushed, iclass 14, count 2 2006.257.15:55:00.37#ibcon#about to write, iclass 14, count 2 2006.257.15:55:00.37#ibcon#wrote, iclass 14, count 2 2006.257.15:55:00.37#ibcon#about to read 3, iclass 14, count 2 2006.257.15:55:00.40#ibcon#read 3, iclass 14, count 2 2006.257.15:55:00.40#ibcon#about to read 4, iclass 14, count 2 2006.257.15:55:00.40#ibcon#read 4, iclass 14, count 2 2006.257.15:55:00.40#ibcon#about to read 5, iclass 14, count 2 2006.257.15:55:00.40#ibcon#read 5, iclass 14, count 2 2006.257.15:55:00.40#ibcon#about to read 6, iclass 14, count 2 2006.257.15:55:00.40#ibcon#read 6, iclass 14, count 2 2006.257.15:55:00.40#ibcon#end of sib2, iclass 14, count 2 2006.257.15:55:00.40#ibcon#*after write, iclass 14, count 2 2006.257.15:55:00.40#ibcon#*before return 0, iclass 14, count 2 2006.257.15:55:00.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:00.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:00.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.15:55:00.40#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:00.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:00.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:00.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:00.52#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:55:00.52#ibcon#first serial, iclass 14, count 0 2006.257.15:55:00.52#ibcon#enter sib2, iclass 14, count 0 2006.257.15:55:00.52#ibcon#flushed, iclass 14, count 0 2006.257.15:55:00.52#ibcon#about to write, iclass 14, count 0 2006.257.15:55:00.52#ibcon#wrote, iclass 14, count 0 2006.257.15:55:00.52#ibcon#about to read 3, iclass 14, count 0 2006.257.15:55:00.54#ibcon#read 3, iclass 14, count 0 2006.257.15:55:00.54#ibcon#about to read 4, iclass 14, count 0 2006.257.15:55:00.54#ibcon#read 4, iclass 14, count 0 2006.257.15:55:00.54#ibcon#about to read 5, iclass 14, count 0 2006.257.15:55:00.54#ibcon#read 5, iclass 14, count 0 2006.257.15:55:00.54#ibcon#about to read 6, iclass 14, count 0 2006.257.15:55:00.54#ibcon#read 6, iclass 14, count 0 2006.257.15:55:00.54#ibcon#end of sib2, iclass 14, count 0 2006.257.15:55:00.54#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:55:00.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:55:00.54#ibcon#[25=USB\r\n] 2006.257.15:55:00.54#ibcon#*before write, iclass 14, count 0 2006.257.15:55:00.54#ibcon#enter sib2, iclass 14, count 0 2006.257.15:55:00.54#ibcon#flushed, iclass 14, count 0 2006.257.15:55:00.54#ibcon#about to write, iclass 14, count 0 2006.257.15:55:00.54#ibcon#wrote, iclass 14, count 0 2006.257.15:55:00.54#ibcon#about to read 3, iclass 14, count 0 2006.257.15:55:00.57#ibcon#read 3, iclass 14, count 0 2006.257.15:55:00.57#ibcon#about to read 4, iclass 14, count 0 2006.257.15:55:00.57#ibcon#read 4, iclass 14, count 0 2006.257.15:55:00.57#ibcon#about to read 5, iclass 14, count 0 2006.257.15:55:00.57#ibcon#read 5, iclass 14, count 0 2006.257.15:55:00.57#ibcon#about to read 6, iclass 14, count 0 2006.257.15:55:00.57#ibcon#read 6, iclass 14, count 0 2006.257.15:55:00.57#ibcon#end of sib2, iclass 14, count 0 2006.257.15:55:00.57#ibcon#*after write, iclass 14, count 0 2006.257.15:55:00.57#ibcon#*before return 0, iclass 14, count 0 2006.257.15:55:00.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:00.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:00.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:55:00.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:55:00.57$vck44/valo=8,884.99 2006.257.15:55:00.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.15:55:00.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.15:55:00.57#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:00.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:00.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:00.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:00.57#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:55:00.57#ibcon#first serial, iclass 16, count 0 2006.257.15:55:00.57#ibcon#enter sib2, iclass 16, count 0 2006.257.15:55:00.57#ibcon#flushed, iclass 16, count 0 2006.257.15:55:00.57#ibcon#about to write, iclass 16, count 0 2006.257.15:55:00.57#ibcon#wrote, iclass 16, count 0 2006.257.15:55:00.57#ibcon#about to read 3, iclass 16, count 0 2006.257.15:55:00.59#ibcon#read 3, iclass 16, count 0 2006.257.15:55:00.59#ibcon#about to read 4, iclass 16, count 0 2006.257.15:55:00.59#ibcon#read 4, iclass 16, count 0 2006.257.15:55:00.59#ibcon#about to read 5, iclass 16, count 0 2006.257.15:55:00.59#ibcon#read 5, iclass 16, count 0 2006.257.15:55:00.59#ibcon#about to read 6, iclass 16, count 0 2006.257.15:55:00.59#ibcon#read 6, iclass 16, count 0 2006.257.15:55:00.59#ibcon#end of sib2, iclass 16, count 0 2006.257.15:55:00.59#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:55:00.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:55:00.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:55:00.59#ibcon#*before write, iclass 16, count 0 2006.257.15:55:00.59#ibcon#enter sib2, iclass 16, count 0 2006.257.15:55:00.59#ibcon#flushed, iclass 16, count 0 2006.257.15:55:00.59#ibcon#about to write, iclass 16, count 0 2006.257.15:55:00.59#ibcon#wrote, iclass 16, count 0 2006.257.15:55:00.59#ibcon#about to read 3, iclass 16, count 0 2006.257.15:55:00.63#ibcon#read 3, iclass 16, count 0 2006.257.15:55:00.63#ibcon#about to read 4, iclass 16, count 0 2006.257.15:55:00.63#ibcon#read 4, iclass 16, count 0 2006.257.15:55:00.63#ibcon#about to read 5, iclass 16, count 0 2006.257.15:55:00.63#ibcon#read 5, iclass 16, count 0 2006.257.15:55:00.63#ibcon#about to read 6, iclass 16, count 0 2006.257.15:55:00.63#ibcon#read 6, iclass 16, count 0 2006.257.15:55:00.63#ibcon#end of sib2, iclass 16, count 0 2006.257.15:55:00.63#ibcon#*after write, iclass 16, count 0 2006.257.15:55:00.63#ibcon#*before return 0, iclass 16, count 0 2006.257.15:55:00.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:00.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:00.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:55:00.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:55:00.63$vck44/va=8,4 2006.257.15:55:00.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.15:55:00.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.15:55:00.63#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:00.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:55:00.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:55:00.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:55:00.69#ibcon#enter wrdev, iclass 18, count 2 2006.257.15:55:00.69#ibcon#first serial, iclass 18, count 2 2006.257.15:55:00.69#ibcon#enter sib2, iclass 18, count 2 2006.257.15:55:00.69#ibcon#flushed, iclass 18, count 2 2006.257.15:55:00.69#ibcon#about to write, iclass 18, count 2 2006.257.15:55:00.69#ibcon#wrote, iclass 18, count 2 2006.257.15:55:00.69#ibcon#about to read 3, iclass 18, count 2 2006.257.15:55:00.71#ibcon#read 3, iclass 18, count 2 2006.257.15:55:00.71#ibcon#about to read 4, iclass 18, count 2 2006.257.15:55:00.71#ibcon#read 4, iclass 18, count 2 2006.257.15:55:00.71#ibcon#about to read 5, iclass 18, count 2 2006.257.15:55:00.71#ibcon#read 5, iclass 18, count 2 2006.257.15:55:00.71#ibcon#about to read 6, iclass 18, count 2 2006.257.15:55:00.71#ibcon#read 6, iclass 18, count 2 2006.257.15:55:00.71#ibcon#end of sib2, iclass 18, count 2 2006.257.15:55:00.71#ibcon#*mode == 0, iclass 18, count 2 2006.257.15:55:00.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.15:55:00.71#ibcon#[25=AT08-04\r\n] 2006.257.15:55:00.71#ibcon#*before write, iclass 18, count 2 2006.257.15:55:00.71#ibcon#enter sib2, iclass 18, count 2 2006.257.15:55:00.71#ibcon#flushed, iclass 18, count 2 2006.257.15:55:00.71#ibcon#about to write, iclass 18, count 2 2006.257.15:55:00.71#ibcon#wrote, iclass 18, count 2 2006.257.15:55:00.71#ibcon#about to read 3, iclass 18, count 2 2006.257.15:55:00.74#ibcon#read 3, iclass 18, count 2 2006.257.15:55:00.74#ibcon#about to read 4, iclass 18, count 2 2006.257.15:55:00.74#ibcon#read 4, iclass 18, count 2 2006.257.15:55:00.74#ibcon#about to read 5, iclass 18, count 2 2006.257.15:55:00.74#ibcon#read 5, iclass 18, count 2 2006.257.15:55:00.74#ibcon#about to read 6, iclass 18, count 2 2006.257.15:55:00.74#ibcon#read 6, iclass 18, count 2 2006.257.15:55:00.74#ibcon#end of sib2, iclass 18, count 2 2006.257.15:55:00.74#ibcon#*after write, iclass 18, count 2 2006.257.15:55:00.74#ibcon#*before return 0, iclass 18, count 2 2006.257.15:55:00.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:55:00.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.15:55:00.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.15:55:00.74#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:00.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:55:00.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:55:00.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:55:00.86#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:55:00.86#ibcon#first serial, iclass 18, count 0 2006.257.15:55:00.86#ibcon#enter sib2, iclass 18, count 0 2006.257.15:55:00.86#ibcon#flushed, iclass 18, count 0 2006.257.15:55:00.86#ibcon#about to write, iclass 18, count 0 2006.257.15:55:00.86#ibcon#wrote, iclass 18, count 0 2006.257.15:55:00.86#ibcon#about to read 3, iclass 18, count 0 2006.257.15:55:00.88#ibcon#read 3, iclass 18, count 0 2006.257.15:55:00.88#ibcon#about to read 4, iclass 18, count 0 2006.257.15:55:00.88#ibcon#read 4, iclass 18, count 0 2006.257.15:55:00.88#ibcon#about to read 5, iclass 18, count 0 2006.257.15:55:00.88#ibcon#read 5, iclass 18, count 0 2006.257.15:55:00.88#ibcon#about to read 6, iclass 18, count 0 2006.257.15:55:00.88#ibcon#read 6, iclass 18, count 0 2006.257.15:55:00.88#ibcon#end of sib2, iclass 18, count 0 2006.257.15:55:00.88#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:55:00.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:55:00.88#ibcon#[25=USB\r\n] 2006.257.15:55:00.88#ibcon#*before write, iclass 18, count 0 2006.257.15:55:00.88#ibcon#enter sib2, iclass 18, count 0 2006.257.15:55:00.88#ibcon#flushed, iclass 18, count 0 2006.257.15:55:00.88#ibcon#about to write, iclass 18, count 0 2006.257.15:55:00.88#ibcon#wrote, iclass 18, count 0 2006.257.15:55:00.88#ibcon#about to read 3, iclass 18, count 0 2006.257.15:55:00.91#ibcon#read 3, iclass 18, count 0 2006.257.15:55:00.91#ibcon#about to read 4, iclass 18, count 0 2006.257.15:55:00.91#ibcon#read 4, iclass 18, count 0 2006.257.15:55:00.91#ibcon#about to read 5, iclass 18, count 0 2006.257.15:55:00.91#ibcon#read 5, iclass 18, count 0 2006.257.15:55:00.91#ibcon#about to read 6, iclass 18, count 0 2006.257.15:55:00.91#ibcon#read 6, iclass 18, count 0 2006.257.15:55:00.91#ibcon#end of sib2, iclass 18, count 0 2006.257.15:55:00.91#ibcon#*after write, iclass 18, count 0 2006.257.15:55:00.91#ibcon#*before return 0, iclass 18, count 0 2006.257.15:55:00.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:55:00.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.15:55:00.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:55:00.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:55:00.91$vck44/vblo=1,629.99 2006.257.15:55:00.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.15:55:00.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.15:55:00.91#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:00.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:55:00.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:55:00.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:55:00.91#ibcon#enter wrdev, iclass 20, count 0 2006.257.15:55:00.91#ibcon#first serial, iclass 20, count 0 2006.257.15:55:00.91#ibcon#enter sib2, iclass 20, count 0 2006.257.15:55:00.91#ibcon#flushed, iclass 20, count 0 2006.257.15:55:00.91#ibcon#about to write, iclass 20, count 0 2006.257.15:55:00.91#ibcon#wrote, iclass 20, count 0 2006.257.15:55:00.91#ibcon#about to read 3, iclass 20, count 0 2006.257.15:55:00.93#ibcon#read 3, iclass 20, count 0 2006.257.15:55:00.93#ibcon#about to read 4, iclass 20, count 0 2006.257.15:55:00.93#ibcon#read 4, iclass 20, count 0 2006.257.15:55:00.93#ibcon#about to read 5, iclass 20, count 0 2006.257.15:55:00.93#ibcon#read 5, iclass 20, count 0 2006.257.15:55:00.93#ibcon#about to read 6, iclass 20, count 0 2006.257.15:55:00.93#ibcon#read 6, iclass 20, count 0 2006.257.15:55:00.93#ibcon#end of sib2, iclass 20, count 0 2006.257.15:55:00.93#ibcon#*mode == 0, iclass 20, count 0 2006.257.15:55:00.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.15:55:00.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:55:00.93#ibcon#*before write, iclass 20, count 0 2006.257.15:55:00.93#ibcon#enter sib2, iclass 20, count 0 2006.257.15:55:00.93#ibcon#flushed, iclass 20, count 0 2006.257.15:55:00.93#ibcon#about to write, iclass 20, count 0 2006.257.15:55:00.93#ibcon#wrote, iclass 20, count 0 2006.257.15:55:00.93#ibcon#about to read 3, iclass 20, count 0 2006.257.15:55:00.97#ibcon#read 3, iclass 20, count 0 2006.257.15:55:00.97#ibcon#about to read 4, iclass 20, count 0 2006.257.15:55:00.97#ibcon#read 4, iclass 20, count 0 2006.257.15:55:00.97#ibcon#about to read 5, iclass 20, count 0 2006.257.15:55:00.97#ibcon#read 5, iclass 20, count 0 2006.257.15:55:00.97#ibcon#about to read 6, iclass 20, count 0 2006.257.15:55:00.97#ibcon#read 6, iclass 20, count 0 2006.257.15:55:00.97#ibcon#end of sib2, iclass 20, count 0 2006.257.15:55:00.97#ibcon#*after write, iclass 20, count 0 2006.257.15:55:00.97#ibcon#*before return 0, iclass 20, count 0 2006.257.15:55:00.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:55:00.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.15:55:00.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.15:55:00.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.15:55:00.97$vck44/vb=1,4 2006.257.15:55:00.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.15:55:00.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.15:55:00.97#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:00.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:55:00.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:55:00.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:55:00.97#ibcon#enter wrdev, iclass 22, count 2 2006.257.15:55:00.97#ibcon#first serial, iclass 22, count 2 2006.257.15:55:00.97#ibcon#enter sib2, iclass 22, count 2 2006.257.15:55:00.97#ibcon#flushed, iclass 22, count 2 2006.257.15:55:00.97#ibcon#about to write, iclass 22, count 2 2006.257.15:55:00.97#ibcon#wrote, iclass 22, count 2 2006.257.15:55:00.97#ibcon#about to read 3, iclass 22, count 2 2006.257.15:55:00.99#ibcon#read 3, iclass 22, count 2 2006.257.15:55:00.99#ibcon#about to read 4, iclass 22, count 2 2006.257.15:55:00.99#ibcon#read 4, iclass 22, count 2 2006.257.15:55:00.99#ibcon#about to read 5, iclass 22, count 2 2006.257.15:55:00.99#ibcon#read 5, iclass 22, count 2 2006.257.15:55:00.99#ibcon#about to read 6, iclass 22, count 2 2006.257.15:55:00.99#ibcon#read 6, iclass 22, count 2 2006.257.15:55:00.99#ibcon#end of sib2, iclass 22, count 2 2006.257.15:55:00.99#ibcon#*mode == 0, iclass 22, count 2 2006.257.15:55:00.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.15:55:00.99#ibcon#[27=AT01-04\r\n] 2006.257.15:55:00.99#ibcon#*before write, iclass 22, count 2 2006.257.15:55:00.99#ibcon#enter sib2, iclass 22, count 2 2006.257.15:55:00.99#ibcon#flushed, iclass 22, count 2 2006.257.15:55:00.99#ibcon#about to write, iclass 22, count 2 2006.257.15:55:00.99#ibcon#wrote, iclass 22, count 2 2006.257.15:55:00.99#ibcon#about to read 3, iclass 22, count 2 2006.257.15:55:01.02#ibcon#read 3, iclass 22, count 2 2006.257.15:55:01.02#ibcon#about to read 4, iclass 22, count 2 2006.257.15:55:01.02#ibcon#read 4, iclass 22, count 2 2006.257.15:55:01.02#ibcon#about to read 5, iclass 22, count 2 2006.257.15:55:01.02#ibcon#read 5, iclass 22, count 2 2006.257.15:55:01.02#ibcon#about to read 6, iclass 22, count 2 2006.257.15:55:01.02#ibcon#read 6, iclass 22, count 2 2006.257.15:55:01.02#ibcon#end of sib2, iclass 22, count 2 2006.257.15:55:01.02#ibcon#*after write, iclass 22, count 2 2006.257.15:55:01.02#ibcon#*before return 0, iclass 22, count 2 2006.257.15:55:01.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:55:01.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.15:55:01.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.15:55:01.02#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:01.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:55:01.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:55:01.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:55:01.14#ibcon#enter wrdev, iclass 22, count 0 2006.257.15:55:01.14#ibcon#first serial, iclass 22, count 0 2006.257.15:55:01.14#ibcon#enter sib2, iclass 22, count 0 2006.257.15:55:01.14#ibcon#flushed, iclass 22, count 0 2006.257.15:55:01.14#ibcon#about to write, iclass 22, count 0 2006.257.15:55:01.14#ibcon#wrote, iclass 22, count 0 2006.257.15:55:01.14#ibcon#about to read 3, iclass 22, count 0 2006.257.15:55:01.16#ibcon#read 3, iclass 22, count 0 2006.257.15:55:01.16#ibcon#about to read 4, iclass 22, count 0 2006.257.15:55:01.16#ibcon#read 4, iclass 22, count 0 2006.257.15:55:01.16#ibcon#about to read 5, iclass 22, count 0 2006.257.15:55:01.16#ibcon#read 5, iclass 22, count 0 2006.257.15:55:01.16#ibcon#about to read 6, iclass 22, count 0 2006.257.15:55:01.16#ibcon#read 6, iclass 22, count 0 2006.257.15:55:01.16#ibcon#end of sib2, iclass 22, count 0 2006.257.15:55:01.16#ibcon#*mode == 0, iclass 22, count 0 2006.257.15:55:01.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.15:55:01.16#ibcon#[27=USB\r\n] 2006.257.15:55:01.16#ibcon#*before write, iclass 22, count 0 2006.257.15:55:01.16#ibcon#enter sib2, iclass 22, count 0 2006.257.15:55:01.16#ibcon#flushed, iclass 22, count 0 2006.257.15:55:01.16#ibcon#about to write, iclass 22, count 0 2006.257.15:55:01.16#ibcon#wrote, iclass 22, count 0 2006.257.15:55:01.16#ibcon#about to read 3, iclass 22, count 0 2006.257.15:55:01.19#ibcon#read 3, iclass 22, count 0 2006.257.15:55:01.19#ibcon#about to read 4, iclass 22, count 0 2006.257.15:55:01.19#ibcon#read 4, iclass 22, count 0 2006.257.15:55:01.19#ibcon#about to read 5, iclass 22, count 0 2006.257.15:55:01.19#ibcon#read 5, iclass 22, count 0 2006.257.15:55:01.19#ibcon#about to read 6, iclass 22, count 0 2006.257.15:55:01.19#ibcon#read 6, iclass 22, count 0 2006.257.15:55:01.19#ibcon#end of sib2, iclass 22, count 0 2006.257.15:55:01.19#ibcon#*after write, iclass 22, count 0 2006.257.15:55:01.19#ibcon#*before return 0, iclass 22, count 0 2006.257.15:55:01.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:55:01.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.15:55:01.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.15:55:01.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.15:55:01.19$vck44/vblo=2,634.99 2006.257.15:55:01.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.15:55:01.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.15:55:01.19#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:01.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:55:01.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:55:01.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:55:01.19#ibcon#enter wrdev, iclass 24, count 0 2006.257.15:55:01.19#ibcon#first serial, iclass 24, count 0 2006.257.15:55:01.19#ibcon#enter sib2, iclass 24, count 0 2006.257.15:55:01.19#ibcon#flushed, iclass 24, count 0 2006.257.15:55:01.19#ibcon#about to write, iclass 24, count 0 2006.257.15:55:01.19#ibcon#wrote, iclass 24, count 0 2006.257.15:55:01.19#ibcon#about to read 3, iclass 24, count 0 2006.257.15:55:01.21#ibcon#read 3, iclass 24, count 0 2006.257.15:55:01.21#ibcon#about to read 4, iclass 24, count 0 2006.257.15:55:01.21#ibcon#read 4, iclass 24, count 0 2006.257.15:55:01.21#ibcon#about to read 5, iclass 24, count 0 2006.257.15:55:01.21#ibcon#read 5, iclass 24, count 0 2006.257.15:55:01.21#ibcon#about to read 6, iclass 24, count 0 2006.257.15:55:01.21#ibcon#read 6, iclass 24, count 0 2006.257.15:55:01.21#ibcon#end of sib2, iclass 24, count 0 2006.257.15:55:01.21#ibcon#*mode == 0, iclass 24, count 0 2006.257.15:55:01.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.15:55:01.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:55:01.21#ibcon#*before write, iclass 24, count 0 2006.257.15:55:01.21#ibcon#enter sib2, iclass 24, count 0 2006.257.15:55:01.21#ibcon#flushed, iclass 24, count 0 2006.257.15:55:01.21#ibcon#about to write, iclass 24, count 0 2006.257.15:55:01.21#ibcon#wrote, iclass 24, count 0 2006.257.15:55:01.21#ibcon#about to read 3, iclass 24, count 0 2006.257.15:55:01.25#ibcon#read 3, iclass 24, count 0 2006.257.15:55:01.25#ibcon#about to read 4, iclass 24, count 0 2006.257.15:55:01.25#ibcon#read 4, iclass 24, count 0 2006.257.15:55:01.25#ibcon#about to read 5, iclass 24, count 0 2006.257.15:55:01.25#ibcon#read 5, iclass 24, count 0 2006.257.15:55:01.25#ibcon#about to read 6, iclass 24, count 0 2006.257.15:55:01.25#ibcon#read 6, iclass 24, count 0 2006.257.15:55:01.25#ibcon#end of sib2, iclass 24, count 0 2006.257.15:55:01.25#ibcon#*after write, iclass 24, count 0 2006.257.15:55:01.25#ibcon#*before return 0, iclass 24, count 0 2006.257.15:55:01.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:55:01.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.15:55:01.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.15:55:01.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.15:55:01.25$vck44/vb=2,5 2006.257.15:55:01.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.15:55:01.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.15:55:01.25#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:01.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:55:01.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:55:01.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:55:01.31#ibcon#enter wrdev, iclass 26, count 2 2006.257.15:55:01.31#ibcon#first serial, iclass 26, count 2 2006.257.15:55:01.31#ibcon#enter sib2, iclass 26, count 2 2006.257.15:55:01.31#ibcon#flushed, iclass 26, count 2 2006.257.15:55:01.31#ibcon#about to write, iclass 26, count 2 2006.257.15:55:01.31#ibcon#wrote, iclass 26, count 2 2006.257.15:55:01.31#ibcon#about to read 3, iclass 26, count 2 2006.257.15:55:01.33#ibcon#read 3, iclass 26, count 2 2006.257.15:55:01.33#ibcon#about to read 4, iclass 26, count 2 2006.257.15:55:01.33#ibcon#read 4, iclass 26, count 2 2006.257.15:55:01.33#ibcon#about to read 5, iclass 26, count 2 2006.257.15:55:01.33#ibcon#read 5, iclass 26, count 2 2006.257.15:55:01.33#ibcon#about to read 6, iclass 26, count 2 2006.257.15:55:01.33#ibcon#read 6, iclass 26, count 2 2006.257.15:55:01.33#ibcon#end of sib2, iclass 26, count 2 2006.257.15:55:01.33#ibcon#*mode == 0, iclass 26, count 2 2006.257.15:55:01.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.15:55:01.33#ibcon#[27=AT02-05\r\n] 2006.257.15:55:01.33#ibcon#*before write, iclass 26, count 2 2006.257.15:55:01.33#ibcon#enter sib2, iclass 26, count 2 2006.257.15:55:01.33#ibcon#flushed, iclass 26, count 2 2006.257.15:55:01.33#ibcon#about to write, iclass 26, count 2 2006.257.15:55:01.33#ibcon#wrote, iclass 26, count 2 2006.257.15:55:01.33#ibcon#about to read 3, iclass 26, count 2 2006.257.15:55:01.36#ibcon#read 3, iclass 26, count 2 2006.257.15:55:01.36#ibcon#about to read 4, iclass 26, count 2 2006.257.15:55:01.36#ibcon#read 4, iclass 26, count 2 2006.257.15:55:01.36#ibcon#about to read 5, iclass 26, count 2 2006.257.15:55:01.36#ibcon#read 5, iclass 26, count 2 2006.257.15:55:01.36#ibcon#about to read 6, iclass 26, count 2 2006.257.15:55:01.36#ibcon#read 6, iclass 26, count 2 2006.257.15:55:01.36#ibcon#end of sib2, iclass 26, count 2 2006.257.15:55:01.36#ibcon#*after write, iclass 26, count 2 2006.257.15:55:01.36#ibcon#*before return 0, iclass 26, count 2 2006.257.15:55:01.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:55:01.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.15:55:01.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.15:55:01.36#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:01.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:55:01.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:55:01.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:55:01.48#ibcon#enter wrdev, iclass 26, count 0 2006.257.15:55:01.48#ibcon#first serial, iclass 26, count 0 2006.257.15:55:01.48#ibcon#enter sib2, iclass 26, count 0 2006.257.15:55:01.48#ibcon#flushed, iclass 26, count 0 2006.257.15:55:01.48#ibcon#about to write, iclass 26, count 0 2006.257.15:55:01.48#ibcon#wrote, iclass 26, count 0 2006.257.15:55:01.48#ibcon#about to read 3, iclass 26, count 0 2006.257.15:55:01.50#ibcon#read 3, iclass 26, count 0 2006.257.15:55:01.50#ibcon#about to read 4, iclass 26, count 0 2006.257.15:55:01.50#ibcon#read 4, iclass 26, count 0 2006.257.15:55:01.50#ibcon#about to read 5, iclass 26, count 0 2006.257.15:55:01.50#ibcon#read 5, iclass 26, count 0 2006.257.15:55:01.50#ibcon#about to read 6, iclass 26, count 0 2006.257.15:55:01.50#ibcon#read 6, iclass 26, count 0 2006.257.15:55:01.50#ibcon#end of sib2, iclass 26, count 0 2006.257.15:55:01.50#ibcon#*mode == 0, iclass 26, count 0 2006.257.15:55:01.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.15:55:01.50#ibcon#[27=USB\r\n] 2006.257.15:55:01.50#ibcon#*before write, iclass 26, count 0 2006.257.15:55:01.50#ibcon#enter sib2, iclass 26, count 0 2006.257.15:55:01.50#ibcon#flushed, iclass 26, count 0 2006.257.15:55:01.50#ibcon#about to write, iclass 26, count 0 2006.257.15:55:01.50#ibcon#wrote, iclass 26, count 0 2006.257.15:55:01.50#ibcon#about to read 3, iclass 26, count 0 2006.257.15:55:01.53#ibcon#read 3, iclass 26, count 0 2006.257.15:55:01.53#ibcon#about to read 4, iclass 26, count 0 2006.257.15:55:01.53#ibcon#read 4, iclass 26, count 0 2006.257.15:55:01.53#ibcon#about to read 5, iclass 26, count 0 2006.257.15:55:01.53#ibcon#read 5, iclass 26, count 0 2006.257.15:55:01.53#ibcon#about to read 6, iclass 26, count 0 2006.257.15:55:01.53#ibcon#read 6, iclass 26, count 0 2006.257.15:55:01.53#ibcon#end of sib2, iclass 26, count 0 2006.257.15:55:01.53#ibcon#*after write, iclass 26, count 0 2006.257.15:55:01.53#ibcon#*before return 0, iclass 26, count 0 2006.257.15:55:01.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:55:01.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.15:55:01.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.15:55:01.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.15:55:01.53$vck44/vblo=3,649.99 2006.257.15:55:01.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.15:55:01.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.15:55:01.53#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:01.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:55:01.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:55:01.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:55:01.53#ibcon#enter wrdev, iclass 28, count 0 2006.257.15:55:01.53#ibcon#first serial, iclass 28, count 0 2006.257.15:55:01.53#ibcon#enter sib2, iclass 28, count 0 2006.257.15:55:01.53#ibcon#flushed, iclass 28, count 0 2006.257.15:55:01.53#ibcon#about to write, iclass 28, count 0 2006.257.15:55:01.53#ibcon#wrote, iclass 28, count 0 2006.257.15:55:01.53#ibcon#about to read 3, iclass 28, count 0 2006.257.15:55:01.55#ibcon#read 3, iclass 28, count 0 2006.257.15:55:01.55#ibcon#about to read 4, iclass 28, count 0 2006.257.15:55:01.55#ibcon#read 4, iclass 28, count 0 2006.257.15:55:01.55#ibcon#about to read 5, iclass 28, count 0 2006.257.15:55:01.55#ibcon#read 5, iclass 28, count 0 2006.257.15:55:01.55#ibcon#about to read 6, iclass 28, count 0 2006.257.15:55:01.55#ibcon#read 6, iclass 28, count 0 2006.257.15:55:01.55#ibcon#end of sib2, iclass 28, count 0 2006.257.15:55:01.55#ibcon#*mode == 0, iclass 28, count 0 2006.257.15:55:01.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.15:55:01.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:55:01.55#ibcon#*before write, iclass 28, count 0 2006.257.15:55:01.55#ibcon#enter sib2, iclass 28, count 0 2006.257.15:55:01.55#ibcon#flushed, iclass 28, count 0 2006.257.15:55:01.55#ibcon#about to write, iclass 28, count 0 2006.257.15:55:01.55#ibcon#wrote, iclass 28, count 0 2006.257.15:55:01.55#ibcon#about to read 3, iclass 28, count 0 2006.257.15:55:01.59#ibcon#read 3, iclass 28, count 0 2006.257.15:55:01.59#ibcon#about to read 4, iclass 28, count 0 2006.257.15:55:01.59#ibcon#read 4, iclass 28, count 0 2006.257.15:55:01.59#ibcon#about to read 5, iclass 28, count 0 2006.257.15:55:01.59#ibcon#read 5, iclass 28, count 0 2006.257.15:55:01.59#ibcon#about to read 6, iclass 28, count 0 2006.257.15:55:01.59#ibcon#read 6, iclass 28, count 0 2006.257.15:55:01.59#ibcon#end of sib2, iclass 28, count 0 2006.257.15:55:01.59#ibcon#*after write, iclass 28, count 0 2006.257.15:55:01.59#ibcon#*before return 0, iclass 28, count 0 2006.257.15:55:01.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:55:01.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.15:55:01.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.15:55:01.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.15:55:01.59$vck44/vb=3,4 2006.257.15:55:01.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.15:55:01.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.15:55:01.59#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:01.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:55:01.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:55:01.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:55:01.65#ibcon#enter wrdev, iclass 30, count 2 2006.257.15:55:01.65#ibcon#first serial, iclass 30, count 2 2006.257.15:55:01.65#ibcon#enter sib2, iclass 30, count 2 2006.257.15:55:01.65#ibcon#flushed, iclass 30, count 2 2006.257.15:55:01.65#ibcon#about to write, iclass 30, count 2 2006.257.15:55:01.65#ibcon#wrote, iclass 30, count 2 2006.257.15:55:01.65#ibcon#about to read 3, iclass 30, count 2 2006.257.15:55:01.67#ibcon#read 3, iclass 30, count 2 2006.257.15:55:01.67#ibcon#about to read 4, iclass 30, count 2 2006.257.15:55:01.67#ibcon#read 4, iclass 30, count 2 2006.257.15:55:01.67#ibcon#about to read 5, iclass 30, count 2 2006.257.15:55:01.67#ibcon#read 5, iclass 30, count 2 2006.257.15:55:01.67#ibcon#about to read 6, iclass 30, count 2 2006.257.15:55:01.67#ibcon#read 6, iclass 30, count 2 2006.257.15:55:01.67#ibcon#end of sib2, iclass 30, count 2 2006.257.15:55:01.67#ibcon#*mode == 0, iclass 30, count 2 2006.257.15:55:01.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.15:55:01.67#ibcon#[27=AT03-04\r\n] 2006.257.15:55:01.67#ibcon#*before write, iclass 30, count 2 2006.257.15:55:01.67#ibcon#enter sib2, iclass 30, count 2 2006.257.15:55:01.67#ibcon#flushed, iclass 30, count 2 2006.257.15:55:01.67#ibcon#about to write, iclass 30, count 2 2006.257.15:55:01.67#ibcon#wrote, iclass 30, count 2 2006.257.15:55:01.67#ibcon#about to read 3, iclass 30, count 2 2006.257.15:55:01.70#ibcon#read 3, iclass 30, count 2 2006.257.15:55:01.70#ibcon#about to read 4, iclass 30, count 2 2006.257.15:55:01.70#ibcon#read 4, iclass 30, count 2 2006.257.15:55:01.70#ibcon#about to read 5, iclass 30, count 2 2006.257.15:55:01.70#ibcon#read 5, iclass 30, count 2 2006.257.15:55:01.70#ibcon#about to read 6, iclass 30, count 2 2006.257.15:55:01.70#ibcon#read 6, iclass 30, count 2 2006.257.15:55:01.70#ibcon#end of sib2, iclass 30, count 2 2006.257.15:55:01.70#ibcon#*after write, iclass 30, count 2 2006.257.15:55:01.70#ibcon#*before return 0, iclass 30, count 2 2006.257.15:55:01.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:55:01.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.15:55:01.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.15:55:01.70#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:01.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:55:01.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:55:01.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:55:01.82#ibcon#enter wrdev, iclass 30, count 0 2006.257.15:55:01.82#ibcon#first serial, iclass 30, count 0 2006.257.15:55:01.82#ibcon#enter sib2, iclass 30, count 0 2006.257.15:55:01.82#ibcon#flushed, iclass 30, count 0 2006.257.15:55:01.82#ibcon#about to write, iclass 30, count 0 2006.257.15:55:01.82#ibcon#wrote, iclass 30, count 0 2006.257.15:55:01.82#ibcon#about to read 3, iclass 30, count 0 2006.257.15:55:01.84#ibcon#read 3, iclass 30, count 0 2006.257.15:55:01.84#ibcon#about to read 4, iclass 30, count 0 2006.257.15:55:01.84#ibcon#read 4, iclass 30, count 0 2006.257.15:55:01.84#ibcon#about to read 5, iclass 30, count 0 2006.257.15:55:01.84#ibcon#read 5, iclass 30, count 0 2006.257.15:55:01.84#ibcon#about to read 6, iclass 30, count 0 2006.257.15:55:01.84#ibcon#read 6, iclass 30, count 0 2006.257.15:55:01.84#ibcon#end of sib2, iclass 30, count 0 2006.257.15:55:01.84#ibcon#*mode == 0, iclass 30, count 0 2006.257.15:55:01.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.15:55:01.84#ibcon#[27=USB\r\n] 2006.257.15:55:01.84#ibcon#*before write, iclass 30, count 0 2006.257.15:55:01.84#ibcon#enter sib2, iclass 30, count 0 2006.257.15:55:01.84#ibcon#flushed, iclass 30, count 0 2006.257.15:55:01.84#ibcon#about to write, iclass 30, count 0 2006.257.15:55:01.84#ibcon#wrote, iclass 30, count 0 2006.257.15:55:01.84#ibcon#about to read 3, iclass 30, count 0 2006.257.15:55:01.87#ibcon#read 3, iclass 30, count 0 2006.257.15:55:01.87#ibcon#about to read 4, iclass 30, count 0 2006.257.15:55:01.87#ibcon#read 4, iclass 30, count 0 2006.257.15:55:01.87#ibcon#about to read 5, iclass 30, count 0 2006.257.15:55:01.87#ibcon#read 5, iclass 30, count 0 2006.257.15:55:01.87#ibcon#about to read 6, iclass 30, count 0 2006.257.15:55:01.87#ibcon#read 6, iclass 30, count 0 2006.257.15:55:01.87#ibcon#end of sib2, iclass 30, count 0 2006.257.15:55:01.87#ibcon#*after write, iclass 30, count 0 2006.257.15:55:01.87#ibcon#*before return 0, iclass 30, count 0 2006.257.15:55:01.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:55:01.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.15:55:01.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.15:55:01.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.15:55:01.87$vck44/vblo=4,679.99 2006.257.15:55:01.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.15:55:01.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.15:55:01.87#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:01.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:55:01.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:55:01.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:55:01.87#ibcon#enter wrdev, iclass 32, count 0 2006.257.15:55:01.87#ibcon#first serial, iclass 32, count 0 2006.257.15:55:01.87#ibcon#enter sib2, iclass 32, count 0 2006.257.15:55:01.87#ibcon#flushed, iclass 32, count 0 2006.257.15:55:01.87#ibcon#about to write, iclass 32, count 0 2006.257.15:55:01.87#ibcon#wrote, iclass 32, count 0 2006.257.15:55:01.87#ibcon#about to read 3, iclass 32, count 0 2006.257.15:55:01.89#ibcon#read 3, iclass 32, count 0 2006.257.15:55:01.89#ibcon#about to read 4, iclass 32, count 0 2006.257.15:55:01.89#ibcon#read 4, iclass 32, count 0 2006.257.15:55:01.89#ibcon#about to read 5, iclass 32, count 0 2006.257.15:55:01.89#ibcon#read 5, iclass 32, count 0 2006.257.15:55:01.89#ibcon#about to read 6, iclass 32, count 0 2006.257.15:55:01.89#ibcon#read 6, iclass 32, count 0 2006.257.15:55:01.89#ibcon#end of sib2, iclass 32, count 0 2006.257.15:55:01.89#ibcon#*mode == 0, iclass 32, count 0 2006.257.15:55:01.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.15:55:01.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:55:01.89#ibcon#*before write, iclass 32, count 0 2006.257.15:55:01.89#ibcon#enter sib2, iclass 32, count 0 2006.257.15:55:01.89#ibcon#flushed, iclass 32, count 0 2006.257.15:55:01.89#ibcon#about to write, iclass 32, count 0 2006.257.15:55:01.89#ibcon#wrote, iclass 32, count 0 2006.257.15:55:01.89#ibcon#about to read 3, iclass 32, count 0 2006.257.15:55:01.93#ibcon#read 3, iclass 32, count 0 2006.257.15:55:01.93#ibcon#about to read 4, iclass 32, count 0 2006.257.15:55:01.93#ibcon#read 4, iclass 32, count 0 2006.257.15:55:01.93#ibcon#about to read 5, iclass 32, count 0 2006.257.15:55:01.93#ibcon#read 5, iclass 32, count 0 2006.257.15:55:01.93#ibcon#about to read 6, iclass 32, count 0 2006.257.15:55:01.93#ibcon#read 6, iclass 32, count 0 2006.257.15:55:01.93#ibcon#end of sib2, iclass 32, count 0 2006.257.15:55:01.93#ibcon#*after write, iclass 32, count 0 2006.257.15:55:01.93#ibcon#*before return 0, iclass 32, count 0 2006.257.15:55:01.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:55:01.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.15:55:01.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.15:55:01.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.15:55:01.93$vck44/vb=4,5 2006.257.15:55:01.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.15:55:01.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.15:55:01.93#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:01.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:55:01.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:55:01.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:55:01.99#ibcon#enter wrdev, iclass 34, count 2 2006.257.15:55:01.99#ibcon#first serial, iclass 34, count 2 2006.257.15:55:01.99#ibcon#enter sib2, iclass 34, count 2 2006.257.15:55:01.99#ibcon#flushed, iclass 34, count 2 2006.257.15:55:01.99#ibcon#about to write, iclass 34, count 2 2006.257.15:55:01.99#ibcon#wrote, iclass 34, count 2 2006.257.15:55:01.99#ibcon#about to read 3, iclass 34, count 2 2006.257.15:55:02.01#ibcon#read 3, iclass 34, count 2 2006.257.15:55:02.01#ibcon#about to read 4, iclass 34, count 2 2006.257.15:55:02.01#ibcon#read 4, iclass 34, count 2 2006.257.15:55:02.01#ibcon#about to read 5, iclass 34, count 2 2006.257.15:55:02.01#ibcon#read 5, iclass 34, count 2 2006.257.15:55:02.01#ibcon#about to read 6, iclass 34, count 2 2006.257.15:55:02.01#ibcon#read 6, iclass 34, count 2 2006.257.15:55:02.01#ibcon#end of sib2, iclass 34, count 2 2006.257.15:55:02.01#ibcon#*mode == 0, iclass 34, count 2 2006.257.15:55:02.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.15:55:02.01#ibcon#[27=AT04-05\r\n] 2006.257.15:55:02.01#ibcon#*before write, iclass 34, count 2 2006.257.15:55:02.01#ibcon#enter sib2, iclass 34, count 2 2006.257.15:55:02.01#ibcon#flushed, iclass 34, count 2 2006.257.15:55:02.01#ibcon#about to write, iclass 34, count 2 2006.257.15:55:02.01#ibcon#wrote, iclass 34, count 2 2006.257.15:55:02.01#ibcon#about to read 3, iclass 34, count 2 2006.257.15:55:02.04#ibcon#read 3, iclass 34, count 2 2006.257.15:55:02.04#ibcon#about to read 4, iclass 34, count 2 2006.257.15:55:02.04#ibcon#read 4, iclass 34, count 2 2006.257.15:55:02.04#ibcon#about to read 5, iclass 34, count 2 2006.257.15:55:02.04#ibcon#read 5, iclass 34, count 2 2006.257.15:55:02.04#ibcon#about to read 6, iclass 34, count 2 2006.257.15:55:02.04#ibcon#read 6, iclass 34, count 2 2006.257.15:55:02.04#ibcon#end of sib2, iclass 34, count 2 2006.257.15:55:02.04#ibcon#*after write, iclass 34, count 2 2006.257.15:55:02.04#ibcon#*before return 0, iclass 34, count 2 2006.257.15:55:02.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:55:02.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.15:55:02.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.15:55:02.04#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:02.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:55:02.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:55:02.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:55:02.16#ibcon#enter wrdev, iclass 34, count 0 2006.257.15:55:02.16#ibcon#first serial, iclass 34, count 0 2006.257.15:55:02.16#ibcon#enter sib2, iclass 34, count 0 2006.257.15:55:02.16#ibcon#flushed, iclass 34, count 0 2006.257.15:55:02.16#ibcon#about to write, iclass 34, count 0 2006.257.15:55:02.16#ibcon#wrote, iclass 34, count 0 2006.257.15:55:02.16#ibcon#about to read 3, iclass 34, count 0 2006.257.15:55:02.18#ibcon#read 3, iclass 34, count 0 2006.257.15:55:02.18#ibcon#about to read 4, iclass 34, count 0 2006.257.15:55:02.18#ibcon#read 4, iclass 34, count 0 2006.257.15:55:02.18#ibcon#about to read 5, iclass 34, count 0 2006.257.15:55:02.18#ibcon#read 5, iclass 34, count 0 2006.257.15:55:02.18#ibcon#about to read 6, iclass 34, count 0 2006.257.15:55:02.18#ibcon#read 6, iclass 34, count 0 2006.257.15:55:02.18#ibcon#end of sib2, iclass 34, count 0 2006.257.15:55:02.18#ibcon#*mode == 0, iclass 34, count 0 2006.257.15:55:02.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.15:55:02.18#ibcon#[27=USB\r\n] 2006.257.15:55:02.18#ibcon#*before write, iclass 34, count 0 2006.257.15:55:02.18#ibcon#enter sib2, iclass 34, count 0 2006.257.15:55:02.18#ibcon#flushed, iclass 34, count 0 2006.257.15:55:02.18#ibcon#about to write, iclass 34, count 0 2006.257.15:55:02.18#ibcon#wrote, iclass 34, count 0 2006.257.15:55:02.18#ibcon#about to read 3, iclass 34, count 0 2006.257.15:55:02.21#ibcon#read 3, iclass 34, count 0 2006.257.15:55:02.21#ibcon#about to read 4, iclass 34, count 0 2006.257.15:55:02.21#ibcon#read 4, iclass 34, count 0 2006.257.15:55:02.21#ibcon#about to read 5, iclass 34, count 0 2006.257.15:55:02.21#ibcon#read 5, iclass 34, count 0 2006.257.15:55:02.21#ibcon#about to read 6, iclass 34, count 0 2006.257.15:55:02.21#ibcon#read 6, iclass 34, count 0 2006.257.15:55:02.21#ibcon#end of sib2, iclass 34, count 0 2006.257.15:55:02.21#ibcon#*after write, iclass 34, count 0 2006.257.15:55:02.21#ibcon#*before return 0, iclass 34, count 0 2006.257.15:55:02.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:55:02.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.15:55:02.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.15:55:02.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.15:55:02.21$vck44/vblo=5,709.99 2006.257.15:55:02.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.15:55:02.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.15:55:02.21#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:02.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:55:02.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:55:02.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:55:02.21#ibcon#enter wrdev, iclass 36, count 0 2006.257.15:55:02.21#ibcon#first serial, iclass 36, count 0 2006.257.15:55:02.21#ibcon#enter sib2, iclass 36, count 0 2006.257.15:55:02.21#ibcon#flushed, iclass 36, count 0 2006.257.15:55:02.21#ibcon#about to write, iclass 36, count 0 2006.257.15:55:02.21#ibcon#wrote, iclass 36, count 0 2006.257.15:55:02.21#ibcon#about to read 3, iclass 36, count 0 2006.257.15:55:02.23#ibcon#read 3, iclass 36, count 0 2006.257.15:55:02.23#ibcon#about to read 4, iclass 36, count 0 2006.257.15:55:02.23#ibcon#read 4, iclass 36, count 0 2006.257.15:55:02.23#ibcon#about to read 5, iclass 36, count 0 2006.257.15:55:02.23#ibcon#read 5, iclass 36, count 0 2006.257.15:55:02.23#ibcon#about to read 6, iclass 36, count 0 2006.257.15:55:02.23#ibcon#read 6, iclass 36, count 0 2006.257.15:55:02.23#ibcon#end of sib2, iclass 36, count 0 2006.257.15:55:02.23#ibcon#*mode == 0, iclass 36, count 0 2006.257.15:55:02.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.15:55:02.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.15:55:02.23#ibcon#*before write, iclass 36, count 0 2006.257.15:55:02.23#ibcon#enter sib2, iclass 36, count 0 2006.257.15:55:02.23#ibcon#flushed, iclass 36, count 0 2006.257.15:55:02.23#ibcon#about to write, iclass 36, count 0 2006.257.15:55:02.23#ibcon#wrote, iclass 36, count 0 2006.257.15:55:02.23#ibcon#about to read 3, iclass 36, count 0 2006.257.15:55:02.27#ibcon#read 3, iclass 36, count 0 2006.257.15:55:02.27#ibcon#about to read 4, iclass 36, count 0 2006.257.15:55:02.27#ibcon#read 4, iclass 36, count 0 2006.257.15:55:02.27#ibcon#about to read 5, iclass 36, count 0 2006.257.15:55:02.27#ibcon#read 5, iclass 36, count 0 2006.257.15:55:02.27#ibcon#about to read 6, iclass 36, count 0 2006.257.15:55:02.27#ibcon#read 6, iclass 36, count 0 2006.257.15:55:02.27#ibcon#end of sib2, iclass 36, count 0 2006.257.15:55:02.27#ibcon#*after write, iclass 36, count 0 2006.257.15:55:02.27#ibcon#*before return 0, iclass 36, count 0 2006.257.15:55:02.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:55:02.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.15:55:02.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.15:55:02.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.15:55:02.27$vck44/vb=5,4 2006.257.15:55:02.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.15:55:02.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.15:55:02.27#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:02.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:55:02.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:55:02.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:55:02.33#ibcon#enter wrdev, iclass 38, count 2 2006.257.15:55:02.33#ibcon#first serial, iclass 38, count 2 2006.257.15:55:02.33#ibcon#enter sib2, iclass 38, count 2 2006.257.15:55:02.33#ibcon#flushed, iclass 38, count 2 2006.257.15:55:02.33#ibcon#about to write, iclass 38, count 2 2006.257.15:55:02.33#ibcon#wrote, iclass 38, count 2 2006.257.15:55:02.33#ibcon#about to read 3, iclass 38, count 2 2006.257.15:55:02.35#ibcon#read 3, iclass 38, count 2 2006.257.15:55:02.35#ibcon#about to read 4, iclass 38, count 2 2006.257.15:55:02.35#ibcon#read 4, iclass 38, count 2 2006.257.15:55:02.35#ibcon#about to read 5, iclass 38, count 2 2006.257.15:55:02.35#ibcon#read 5, iclass 38, count 2 2006.257.15:55:02.35#ibcon#about to read 6, iclass 38, count 2 2006.257.15:55:02.35#ibcon#read 6, iclass 38, count 2 2006.257.15:55:02.35#ibcon#end of sib2, iclass 38, count 2 2006.257.15:55:02.35#ibcon#*mode == 0, iclass 38, count 2 2006.257.15:55:02.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.15:55:02.35#ibcon#[27=AT05-04\r\n] 2006.257.15:55:02.35#ibcon#*before write, iclass 38, count 2 2006.257.15:55:02.35#ibcon#enter sib2, iclass 38, count 2 2006.257.15:55:02.35#ibcon#flushed, iclass 38, count 2 2006.257.15:55:02.35#ibcon#about to write, iclass 38, count 2 2006.257.15:55:02.35#ibcon#wrote, iclass 38, count 2 2006.257.15:55:02.35#ibcon#about to read 3, iclass 38, count 2 2006.257.15:55:02.38#ibcon#read 3, iclass 38, count 2 2006.257.15:55:02.38#ibcon#about to read 4, iclass 38, count 2 2006.257.15:55:02.38#ibcon#read 4, iclass 38, count 2 2006.257.15:55:02.38#ibcon#about to read 5, iclass 38, count 2 2006.257.15:55:02.38#ibcon#read 5, iclass 38, count 2 2006.257.15:55:02.38#ibcon#about to read 6, iclass 38, count 2 2006.257.15:55:02.38#ibcon#read 6, iclass 38, count 2 2006.257.15:55:02.38#ibcon#end of sib2, iclass 38, count 2 2006.257.15:55:02.38#ibcon#*after write, iclass 38, count 2 2006.257.15:55:02.38#ibcon#*before return 0, iclass 38, count 2 2006.257.15:55:02.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:55:02.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.15:55:02.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.15:55:02.38#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:02.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:55:02.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:55:02.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:55:02.50#ibcon#enter wrdev, iclass 38, count 0 2006.257.15:55:02.50#ibcon#first serial, iclass 38, count 0 2006.257.15:55:02.50#ibcon#enter sib2, iclass 38, count 0 2006.257.15:55:02.50#ibcon#flushed, iclass 38, count 0 2006.257.15:55:02.50#ibcon#about to write, iclass 38, count 0 2006.257.15:55:02.50#ibcon#wrote, iclass 38, count 0 2006.257.15:55:02.50#ibcon#about to read 3, iclass 38, count 0 2006.257.15:55:02.52#ibcon#read 3, iclass 38, count 0 2006.257.15:55:02.52#ibcon#about to read 4, iclass 38, count 0 2006.257.15:55:02.52#ibcon#read 4, iclass 38, count 0 2006.257.15:55:02.52#ibcon#about to read 5, iclass 38, count 0 2006.257.15:55:02.52#ibcon#read 5, iclass 38, count 0 2006.257.15:55:02.52#ibcon#about to read 6, iclass 38, count 0 2006.257.15:55:02.52#ibcon#read 6, iclass 38, count 0 2006.257.15:55:02.52#ibcon#end of sib2, iclass 38, count 0 2006.257.15:55:02.52#ibcon#*mode == 0, iclass 38, count 0 2006.257.15:55:02.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.15:55:02.52#ibcon#[27=USB\r\n] 2006.257.15:55:02.52#ibcon#*before write, iclass 38, count 0 2006.257.15:55:02.52#ibcon#enter sib2, iclass 38, count 0 2006.257.15:55:02.52#ibcon#flushed, iclass 38, count 0 2006.257.15:55:02.52#ibcon#about to write, iclass 38, count 0 2006.257.15:55:02.52#ibcon#wrote, iclass 38, count 0 2006.257.15:55:02.52#ibcon#about to read 3, iclass 38, count 0 2006.257.15:55:02.55#ibcon#read 3, iclass 38, count 0 2006.257.15:55:02.55#ibcon#about to read 4, iclass 38, count 0 2006.257.15:55:02.55#ibcon#read 4, iclass 38, count 0 2006.257.15:55:02.55#ibcon#about to read 5, iclass 38, count 0 2006.257.15:55:02.55#ibcon#read 5, iclass 38, count 0 2006.257.15:55:02.55#ibcon#about to read 6, iclass 38, count 0 2006.257.15:55:02.55#ibcon#read 6, iclass 38, count 0 2006.257.15:55:02.55#ibcon#end of sib2, iclass 38, count 0 2006.257.15:55:02.55#ibcon#*after write, iclass 38, count 0 2006.257.15:55:02.55#ibcon#*before return 0, iclass 38, count 0 2006.257.15:55:02.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:55:02.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.15:55:02.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.15:55:02.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.15:55:02.55$vck44/vblo=6,719.99 2006.257.15:55:02.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.15:55:02.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.15:55:02.55#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:02.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:55:02.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:55:02.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:55:02.55#ibcon#enter wrdev, iclass 40, count 0 2006.257.15:55:02.55#ibcon#first serial, iclass 40, count 0 2006.257.15:55:02.55#ibcon#enter sib2, iclass 40, count 0 2006.257.15:55:02.55#ibcon#flushed, iclass 40, count 0 2006.257.15:55:02.55#ibcon#about to write, iclass 40, count 0 2006.257.15:55:02.55#ibcon#wrote, iclass 40, count 0 2006.257.15:55:02.55#ibcon#about to read 3, iclass 40, count 0 2006.257.15:55:02.57#ibcon#read 3, iclass 40, count 0 2006.257.15:55:02.57#ibcon#about to read 4, iclass 40, count 0 2006.257.15:55:02.57#ibcon#read 4, iclass 40, count 0 2006.257.15:55:02.57#ibcon#about to read 5, iclass 40, count 0 2006.257.15:55:02.57#ibcon#read 5, iclass 40, count 0 2006.257.15:55:02.57#ibcon#about to read 6, iclass 40, count 0 2006.257.15:55:02.57#ibcon#read 6, iclass 40, count 0 2006.257.15:55:02.57#ibcon#end of sib2, iclass 40, count 0 2006.257.15:55:02.57#ibcon#*mode == 0, iclass 40, count 0 2006.257.15:55:02.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.15:55:02.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.15:55:02.57#ibcon#*before write, iclass 40, count 0 2006.257.15:55:02.57#ibcon#enter sib2, iclass 40, count 0 2006.257.15:55:02.57#ibcon#flushed, iclass 40, count 0 2006.257.15:55:02.57#ibcon#about to write, iclass 40, count 0 2006.257.15:55:02.57#ibcon#wrote, iclass 40, count 0 2006.257.15:55:02.57#ibcon#about to read 3, iclass 40, count 0 2006.257.15:55:02.61#ibcon#read 3, iclass 40, count 0 2006.257.15:55:02.61#ibcon#about to read 4, iclass 40, count 0 2006.257.15:55:02.61#ibcon#read 4, iclass 40, count 0 2006.257.15:55:02.61#ibcon#about to read 5, iclass 40, count 0 2006.257.15:55:02.61#ibcon#read 5, iclass 40, count 0 2006.257.15:55:02.61#ibcon#about to read 6, iclass 40, count 0 2006.257.15:55:02.61#ibcon#read 6, iclass 40, count 0 2006.257.15:55:02.61#ibcon#end of sib2, iclass 40, count 0 2006.257.15:55:02.61#ibcon#*after write, iclass 40, count 0 2006.257.15:55:02.61#ibcon#*before return 0, iclass 40, count 0 2006.257.15:55:02.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:55:02.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.15:55:02.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.15:55:02.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.15:55:02.61$vck44/vb=6,4 2006.257.15:55:02.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.15:55:02.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.15:55:02.61#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:02.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:55:02.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:55:02.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:55:02.67#ibcon#enter wrdev, iclass 4, count 2 2006.257.15:55:02.67#ibcon#first serial, iclass 4, count 2 2006.257.15:55:02.67#ibcon#enter sib2, iclass 4, count 2 2006.257.15:55:02.67#ibcon#flushed, iclass 4, count 2 2006.257.15:55:02.67#ibcon#about to write, iclass 4, count 2 2006.257.15:55:02.67#ibcon#wrote, iclass 4, count 2 2006.257.15:55:02.67#ibcon#about to read 3, iclass 4, count 2 2006.257.15:55:02.69#ibcon#read 3, iclass 4, count 2 2006.257.15:55:02.69#ibcon#about to read 4, iclass 4, count 2 2006.257.15:55:02.69#ibcon#read 4, iclass 4, count 2 2006.257.15:55:02.69#ibcon#about to read 5, iclass 4, count 2 2006.257.15:55:02.69#ibcon#read 5, iclass 4, count 2 2006.257.15:55:02.69#ibcon#about to read 6, iclass 4, count 2 2006.257.15:55:02.69#ibcon#read 6, iclass 4, count 2 2006.257.15:55:02.69#ibcon#end of sib2, iclass 4, count 2 2006.257.15:55:02.69#ibcon#*mode == 0, iclass 4, count 2 2006.257.15:55:02.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.15:55:02.69#ibcon#[27=AT06-04\r\n] 2006.257.15:55:02.69#ibcon#*before write, iclass 4, count 2 2006.257.15:55:02.69#ibcon#enter sib2, iclass 4, count 2 2006.257.15:55:02.69#ibcon#flushed, iclass 4, count 2 2006.257.15:55:02.69#ibcon#about to write, iclass 4, count 2 2006.257.15:55:02.69#ibcon#wrote, iclass 4, count 2 2006.257.15:55:02.69#ibcon#about to read 3, iclass 4, count 2 2006.257.15:55:02.72#ibcon#read 3, iclass 4, count 2 2006.257.15:55:02.72#ibcon#about to read 4, iclass 4, count 2 2006.257.15:55:02.72#ibcon#read 4, iclass 4, count 2 2006.257.15:55:02.72#ibcon#about to read 5, iclass 4, count 2 2006.257.15:55:02.72#ibcon#read 5, iclass 4, count 2 2006.257.15:55:02.72#ibcon#about to read 6, iclass 4, count 2 2006.257.15:55:02.72#ibcon#read 6, iclass 4, count 2 2006.257.15:55:02.72#ibcon#end of sib2, iclass 4, count 2 2006.257.15:55:02.72#ibcon#*after write, iclass 4, count 2 2006.257.15:55:02.72#ibcon#*before return 0, iclass 4, count 2 2006.257.15:55:02.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:55:02.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.15:55:02.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.15:55:02.72#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:02.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:55:02.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:55:02.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:55:02.84#ibcon#enter wrdev, iclass 4, count 0 2006.257.15:55:02.84#ibcon#first serial, iclass 4, count 0 2006.257.15:55:02.84#ibcon#enter sib2, iclass 4, count 0 2006.257.15:55:02.84#ibcon#flushed, iclass 4, count 0 2006.257.15:55:02.84#ibcon#about to write, iclass 4, count 0 2006.257.15:55:02.84#ibcon#wrote, iclass 4, count 0 2006.257.15:55:02.84#ibcon#about to read 3, iclass 4, count 0 2006.257.15:55:02.86#ibcon#read 3, iclass 4, count 0 2006.257.15:55:02.86#ibcon#about to read 4, iclass 4, count 0 2006.257.15:55:02.86#ibcon#read 4, iclass 4, count 0 2006.257.15:55:02.86#ibcon#about to read 5, iclass 4, count 0 2006.257.15:55:02.86#ibcon#read 5, iclass 4, count 0 2006.257.15:55:02.86#ibcon#about to read 6, iclass 4, count 0 2006.257.15:55:02.86#ibcon#read 6, iclass 4, count 0 2006.257.15:55:02.86#ibcon#end of sib2, iclass 4, count 0 2006.257.15:55:02.86#ibcon#*mode == 0, iclass 4, count 0 2006.257.15:55:02.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.15:55:02.86#ibcon#[27=USB\r\n] 2006.257.15:55:02.86#ibcon#*before write, iclass 4, count 0 2006.257.15:55:02.86#ibcon#enter sib2, iclass 4, count 0 2006.257.15:55:02.86#ibcon#flushed, iclass 4, count 0 2006.257.15:55:02.86#ibcon#about to write, iclass 4, count 0 2006.257.15:55:02.86#ibcon#wrote, iclass 4, count 0 2006.257.15:55:02.86#ibcon#about to read 3, iclass 4, count 0 2006.257.15:55:02.89#ibcon#read 3, iclass 4, count 0 2006.257.15:55:02.89#ibcon#about to read 4, iclass 4, count 0 2006.257.15:55:02.89#ibcon#read 4, iclass 4, count 0 2006.257.15:55:02.89#ibcon#about to read 5, iclass 4, count 0 2006.257.15:55:02.89#ibcon#read 5, iclass 4, count 0 2006.257.15:55:02.89#ibcon#about to read 6, iclass 4, count 0 2006.257.15:55:02.89#ibcon#read 6, iclass 4, count 0 2006.257.15:55:02.89#ibcon#end of sib2, iclass 4, count 0 2006.257.15:55:02.89#ibcon#*after write, iclass 4, count 0 2006.257.15:55:02.89#ibcon#*before return 0, iclass 4, count 0 2006.257.15:55:02.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:55:02.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.15:55:02.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.15:55:02.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.15:55:02.89$vck44/vblo=7,734.99 2006.257.15:55:02.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.15:55:02.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.15:55:02.89#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:02.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:55:02.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:55:02.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:55:02.89#ibcon#enter wrdev, iclass 6, count 0 2006.257.15:55:02.89#ibcon#first serial, iclass 6, count 0 2006.257.15:55:02.89#ibcon#enter sib2, iclass 6, count 0 2006.257.15:55:02.89#ibcon#flushed, iclass 6, count 0 2006.257.15:55:02.89#ibcon#about to write, iclass 6, count 0 2006.257.15:55:02.89#ibcon#wrote, iclass 6, count 0 2006.257.15:55:02.89#ibcon#about to read 3, iclass 6, count 0 2006.257.15:55:02.91#ibcon#read 3, iclass 6, count 0 2006.257.15:55:02.91#ibcon#about to read 4, iclass 6, count 0 2006.257.15:55:02.91#ibcon#read 4, iclass 6, count 0 2006.257.15:55:02.91#ibcon#about to read 5, iclass 6, count 0 2006.257.15:55:02.91#ibcon#read 5, iclass 6, count 0 2006.257.15:55:02.91#ibcon#about to read 6, iclass 6, count 0 2006.257.15:55:02.91#ibcon#read 6, iclass 6, count 0 2006.257.15:55:02.91#ibcon#end of sib2, iclass 6, count 0 2006.257.15:55:02.91#ibcon#*mode == 0, iclass 6, count 0 2006.257.15:55:02.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.15:55:02.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.15:55:02.91#ibcon#*before write, iclass 6, count 0 2006.257.15:55:02.91#ibcon#enter sib2, iclass 6, count 0 2006.257.15:55:02.91#ibcon#flushed, iclass 6, count 0 2006.257.15:55:02.91#ibcon#about to write, iclass 6, count 0 2006.257.15:55:02.91#ibcon#wrote, iclass 6, count 0 2006.257.15:55:02.91#ibcon#about to read 3, iclass 6, count 0 2006.257.15:55:02.95#ibcon#read 3, iclass 6, count 0 2006.257.15:55:02.95#ibcon#about to read 4, iclass 6, count 0 2006.257.15:55:02.95#ibcon#read 4, iclass 6, count 0 2006.257.15:55:02.95#ibcon#about to read 5, iclass 6, count 0 2006.257.15:55:02.95#ibcon#read 5, iclass 6, count 0 2006.257.15:55:02.95#ibcon#about to read 6, iclass 6, count 0 2006.257.15:55:02.95#ibcon#read 6, iclass 6, count 0 2006.257.15:55:02.95#ibcon#end of sib2, iclass 6, count 0 2006.257.15:55:02.95#ibcon#*after write, iclass 6, count 0 2006.257.15:55:02.95#ibcon#*before return 0, iclass 6, count 0 2006.257.15:55:02.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:55:02.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.15:55:02.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.15:55:02.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.15:55:02.95$vck44/vb=7,4 2006.257.15:55:02.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.15:55:02.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.15:55:02.95#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:02.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:03.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:03.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:03.01#ibcon#enter wrdev, iclass 10, count 2 2006.257.15:55:03.01#ibcon#first serial, iclass 10, count 2 2006.257.15:55:03.01#ibcon#enter sib2, iclass 10, count 2 2006.257.15:55:03.01#ibcon#flushed, iclass 10, count 2 2006.257.15:55:03.01#ibcon#about to write, iclass 10, count 2 2006.257.15:55:03.01#ibcon#wrote, iclass 10, count 2 2006.257.15:55:03.01#ibcon#about to read 3, iclass 10, count 2 2006.257.15:55:03.03#ibcon#read 3, iclass 10, count 2 2006.257.15:55:03.03#ibcon#about to read 4, iclass 10, count 2 2006.257.15:55:03.03#ibcon#read 4, iclass 10, count 2 2006.257.15:55:03.03#ibcon#about to read 5, iclass 10, count 2 2006.257.15:55:03.03#ibcon#read 5, iclass 10, count 2 2006.257.15:55:03.03#ibcon#about to read 6, iclass 10, count 2 2006.257.15:55:03.03#ibcon#read 6, iclass 10, count 2 2006.257.15:55:03.03#ibcon#end of sib2, iclass 10, count 2 2006.257.15:55:03.03#ibcon#*mode == 0, iclass 10, count 2 2006.257.15:55:03.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.15:55:03.03#ibcon#[27=AT07-04\r\n] 2006.257.15:55:03.03#ibcon#*before write, iclass 10, count 2 2006.257.15:55:03.03#ibcon#enter sib2, iclass 10, count 2 2006.257.15:55:03.03#ibcon#flushed, iclass 10, count 2 2006.257.15:55:03.03#ibcon#about to write, iclass 10, count 2 2006.257.15:55:03.03#ibcon#wrote, iclass 10, count 2 2006.257.15:55:03.03#ibcon#about to read 3, iclass 10, count 2 2006.257.15:55:03.06#ibcon#read 3, iclass 10, count 2 2006.257.15:55:03.06#ibcon#about to read 4, iclass 10, count 2 2006.257.15:55:03.06#ibcon#read 4, iclass 10, count 2 2006.257.15:55:03.06#ibcon#about to read 5, iclass 10, count 2 2006.257.15:55:03.06#ibcon#read 5, iclass 10, count 2 2006.257.15:55:03.06#ibcon#about to read 6, iclass 10, count 2 2006.257.15:55:03.06#ibcon#read 6, iclass 10, count 2 2006.257.15:55:03.06#ibcon#end of sib2, iclass 10, count 2 2006.257.15:55:03.06#ibcon#*after write, iclass 10, count 2 2006.257.15:55:03.06#ibcon#*before return 0, iclass 10, count 2 2006.257.15:55:03.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:03.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.15:55:03.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.15:55:03.06#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:03.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:03.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:03.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:03.18#ibcon#enter wrdev, iclass 10, count 0 2006.257.15:55:03.18#ibcon#first serial, iclass 10, count 0 2006.257.15:55:03.18#ibcon#enter sib2, iclass 10, count 0 2006.257.15:55:03.18#ibcon#flushed, iclass 10, count 0 2006.257.15:55:03.18#ibcon#about to write, iclass 10, count 0 2006.257.15:55:03.18#ibcon#wrote, iclass 10, count 0 2006.257.15:55:03.18#ibcon#about to read 3, iclass 10, count 0 2006.257.15:55:03.20#ibcon#read 3, iclass 10, count 0 2006.257.15:55:03.20#ibcon#about to read 4, iclass 10, count 0 2006.257.15:55:03.20#ibcon#read 4, iclass 10, count 0 2006.257.15:55:03.20#ibcon#about to read 5, iclass 10, count 0 2006.257.15:55:03.20#ibcon#read 5, iclass 10, count 0 2006.257.15:55:03.20#ibcon#about to read 6, iclass 10, count 0 2006.257.15:55:03.20#ibcon#read 6, iclass 10, count 0 2006.257.15:55:03.20#ibcon#end of sib2, iclass 10, count 0 2006.257.15:55:03.20#ibcon#*mode == 0, iclass 10, count 0 2006.257.15:55:03.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.15:55:03.20#ibcon#[27=USB\r\n] 2006.257.15:55:03.20#ibcon#*before write, iclass 10, count 0 2006.257.15:55:03.20#ibcon#enter sib2, iclass 10, count 0 2006.257.15:55:03.20#ibcon#flushed, iclass 10, count 0 2006.257.15:55:03.20#ibcon#about to write, iclass 10, count 0 2006.257.15:55:03.20#ibcon#wrote, iclass 10, count 0 2006.257.15:55:03.20#ibcon#about to read 3, iclass 10, count 0 2006.257.15:55:03.23#ibcon#read 3, iclass 10, count 0 2006.257.15:55:03.23#ibcon#about to read 4, iclass 10, count 0 2006.257.15:55:03.23#ibcon#read 4, iclass 10, count 0 2006.257.15:55:03.23#ibcon#about to read 5, iclass 10, count 0 2006.257.15:55:03.23#ibcon#read 5, iclass 10, count 0 2006.257.15:55:03.23#ibcon#about to read 6, iclass 10, count 0 2006.257.15:55:03.23#ibcon#read 6, iclass 10, count 0 2006.257.15:55:03.23#ibcon#end of sib2, iclass 10, count 0 2006.257.15:55:03.23#ibcon#*after write, iclass 10, count 0 2006.257.15:55:03.23#ibcon#*before return 0, iclass 10, count 0 2006.257.15:55:03.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:03.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.15:55:03.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.15:55:03.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.15:55:03.23$vck44/vblo=8,744.99 2006.257.15:55:03.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.15:55:03.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.15:55:03.23#ibcon#ireg 17 cls_cnt 0 2006.257.15:55:03.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:03.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:03.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:03.23#ibcon#enter wrdev, iclass 12, count 0 2006.257.15:55:03.23#ibcon#first serial, iclass 12, count 0 2006.257.15:55:03.23#ibcon#enter sib2, iclass 12, count 0 2006.257.15:55:03.23#ibcon#flushed, iclass 12, count 0 2006.257.15:55:03.23#ibcon#about to write, iclass 12, count 0 2006.257.15:55:03.23#ibcon#wrote, iclass 12, count 0 2006.257.15:55:03.23#ibcon#about to read 3, iclass 12, count 0 2006.257.15:55:03.25#ibcon#read 3, iclass 12, count 0 2006.257.15:55:03.25#ibcon#about to read 4, iclass 12, count 0 2006.257.15:55:03.25#ibcon#read 4, iclass 12, count 0 2006.257.15:55:03.25#ibcon#about to read 5, iclass 12, count 0 2006.257.15:55:03.25#ibcon#read 5, iclass 12, count 0 2006.257.15:55:03.25#ibcon#about to read 6, iclass 12, count 0 2006.257.15:55:03.25#ibcon#read 6, iclass 12, count 0 2006.257.15:55:03.25#ibcon#end of sib2, iclass 12, count 0 2006.257.15:55:03.25#ibcon#*mode == 0, iclass 12, count 0 2006.257.15:55:03.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.15:55:03.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.15:55:03.25#ibcon#*before write, iclass 12, count 0 2006.257.15:55:03.25#ibcon#enter sib2, iclass 12, count 0 2006.257.15:55:03.25#ibcon#flushed, iclass 12, count 0 2006.257.15:55:03.25#ibcon#about to write, iclass 12, count 0 2006.257.15:55:03.25#ibcon#wrote, iclass 12, count 0 2006.257.15:55:03.25#ibcon#about to read 3, iclass 12, count 0 2006.257.15:55:03.29#ibcon#read 3, iclass 12, count 0 2006.257.15:55:03.29#ibcon#about to read 4, iclass 12, count 0 2006.257.15:55:03.29#ibcon#read 4, iclass 12, count 0 2006.257.15:55:03.29#ibcon#about to read 5, iclass 12, count 0 2006.257.15:55:03.29#ibcon#read 5, iclass 12, count 0 2006.257.15:55:03.29#ibcon#about to read 6, iclass 12, count 0 2006.257.15:55:03.29#ibcon#read 6, iclass 12, count 0 2006.257.15:55:03.29#ibcon#end of sib2, iclass 12, count 0 2006.257.15:55:03.29#ibcon#*after write, iclass 12, count 0 2006.257.15:55:03.29#ibcon#*before return 0, iclass 12, count 0 2006.257.15:55:03.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:03.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.15:55:03.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.15:55:03.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.15:55:03.29$vck44/vb=8,4 2006.257.15:55:03.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.15:55:03.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.15:55:03.29#ibcon#ireg 11 cls_cnt 2 2006.257.15:55:03.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:03.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:03.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:03.35#ibcon#enter wrdev, iclass 14, count 2 2006.257.15:55:03.35#ibcon#first serial, iclass 14, count 2 2006.257.15:55:03.35#ibcon#enter sib2, iclass 14, count 2 2006.257.15:55:03.35#ibcon#flushed, iclass 14, count 2 2006.257.15:55:03.35#ibcon#about to write, iclass 14, count 2 2006.257.15:55:03.35#ibcon#wrote, iclass 14, count 2 2006.257.15:55:03.35#ibcon#about to read 3, iclass 14, count 2 2006.257.15:55:03.37#ibcon#read 3, iclass 14, count 2 2006.257.15:55:03.37#ibcon#about to read 4, iclass 14, count 2 2006.257.15:55:03.37#ibcon#read 4, iclass 14, count 2 2006.257.15:55:03.37#ibcon#about to read 5, iclass 14, count 2 2006.257.15:55:03.37#ibcon#read 5, iclass 14, count 2 2006.257.15:55:03.37#ibcon#about to read 6, iclass 14, count 2 2006.257.15:55:03.37#ibcon#read 6, iclass 14, count 2 2006.257.15:55:03.37#ibcon#end of sib2, iclass 14, count 2 2006.257.15:55:03.37#ibcon#*mode == 0, iclass 14, count 2 2006.257.15:55:03.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.15:55:03.37#ibcon#[27=AT08-04\r\n] 2006.257.15:55:03.37#ibcon#*before write, iclass 14, count 2 2006.257.15:55:03.37#ibcon#enter sib2, iclass 14, count 2 2006.257.15:55:03.37#ibcon#flushed, iclass 14, count 2 2006.257.15:55:03.37#ibcon#about to write, iclass 14, count 2 2006.257.15:55:03.37#ibcon#wrote, iclass 14, count 2 2006.257.15:55:03.37#ibcon#about to read 3, iclass 14, count 2 2006.257.15:55:03.40#ibcon#read 3, iclass 14, count 2 2006.257.15:55:03.40#ibcon#about to read 4, iclass 14, count 2 2006.257.15:55:03.40#ibcon#read 4, iclass 14, count 2 2006.257.15:55:03.40#ibcon#about to read 5, iclass 14, count 2 2006.257.15:55:03.40#ibcon#read 5, iclass 14, count 2 2006.257.15:55:03.40#ibcon#about to read 6, iclass 14, count 2 2006.257.15:55:03.40#ibcon#read 6, iclass 14, count 2 2006.257.15:55:03.40#ibcon#end of sib2, iclass 14, count 2 2006.257.15:55:03.40#ibcon#*after write, iclass 14, count 2 2006.257.15:55:03.40#ibcon#*before return 0, iclass 14, count 2 2006.257.15:55:03.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:03.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.15:55:03.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.15:55:03.40#ibcon#ireg 7 cls_cnt 0 2006.257.15:55:03.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:03.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:03.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:03.52#ibcon#enter wrdev, iclass 14, count 0 2006.257.15:55:03.52#ibcon#first serial, iclass 14, count 0 2006.257.15:55:03.52#ibcon#enter sib2, iclass 14, count 0 2006.257.15:55:03.52#ibcon#flushed, iclass 14, count 0 2006.257.15:55:03.52#ibcon#about to write, iclass 14, count 0 2006.257.15:55:03.52#ibcon#wrote, iclass 14, count 0 2006.257.15:55:03.52#ibcon#about to read 3, iclass 14, count 0 2006.257.15:55:03.54#ibcon#read 3, iclass 14, count 0 2006.257.15:55:03.54#ibcon#about to read 4, iclass 14, count 0 2006.257.15:55:03.54#ibcon#read 4, iclass 14, count 0 2006.257.15:55:03.54#ibcon#about to read 5, iclass 14, count 0 2006.257.15:55:03.54#ibcon#read 5, iclass 14, count 0 2006.257.15:55:03.54#ibcon#about to read 6, iclass 14, count 0 2006.257.15:55:03.54#ibcon#read 6, iclass 14, count 0 2006.257.15:55:03.54#ibcon#end of sib2, iclass 14, count 0 2006.257.15:55:03.54#ibcon#*mode == 0, iclass 14, count 0 2006.257.15:55:03.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.15:55:03.54#ibcon#[27=USB\r\n] 2006.257.15:55:03.54#ibcon#*before write, iclass 14, count 0 2006.257.15:55:03.54#ibcon#enter sib2, iclass 14, count 0 2006.257.15:55:03.54#ibcon#flushed, iclass 14, count 0 2006.257.15:55:03.54#ibcon#about to write, iclass 14, count 0 2006.257.15:55:03.54#ibcon#wrote, iclass 14, count 0 2006.257.15:55:03.54#ibcon#about to read 3, iclass 14, count 0 2006.257.15:55:03.57#ibcon#read 3, iclass 14, count 0 2006.257.15:55:03.57#ibcon#about to read 4, iclass 14, count 0 2006.257.15:55:03.57#ibcon#read 4, iclass 14, count 0 2006.257.15:55:03.57#ibcon#about to read 5, iclass 14, count 0 2006.257.15:55:03.57#ibcon#read 5, iclass 14, count 0 2006.257.15:55:03.57#ibcon#about to read 6, iclass 14, count 0 2006.257.15:55:03.57#ibcon#read 6, iclass 14, count 0 2006.257.15:55:03.57#ibcon#end of sib2, iclass 14, count 0 2006.257.15:55:03.57#ibcon#*after write, iclass 14, count 0 2006.257.15:55:03.57#ibcon#*before return 0, iclass 14, count 0 2006.257.15:55:03.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:03.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.15:55:03.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.15:55:03.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.15:55:03.57$vck44/vabw=wide 2006.257.15:55:03.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.15:55:03.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.15:55:03.57#ibcon#ireg 8 cls_cnt 0 2006.257.15:55:03.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:03.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:03.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:03.57#ibcon#enter wrdev, iclass 16, count 0 2006.257.15:55:03.57#ibcon#first serial, iclass 16, count 0 2006.257.15:55:03.57#ibcon#enter sib2, iclass 16, count 0 2006.257.15:55:03.57#ibcon#flushed, iclass 16, count 0 2006.257.15:55:03.57#ibcon#about to write, iclass 16, count 0 2006.257.15:55:03.57#ibcon#wrote, iclass 16, count 0 2006.257.15:55:03.57#ibcon#about to read 3, iclass 16, count 0 2006.257.15:55:03.59#ibcon#read 3, iclass 16, count 0 2006.257.15:55:03.59#ibcon#about to read 4, iclass 16, count 0 2006.257.15:55:03.59#ibcon#read 4, iclass 16, count 0 2006.257.15:55:03.59#ibcon#about to read 5, iclass 16, count 0 2006.257.15:55:03.59#ibcon#read 5, iclass 16, count 0 2006.257.15:55:03.59#ibcon#about to read 6, iclass 16, count 0 2006.257.15:55:03.59#ibcon#read 6, iclass 16, count 0 2006.257.15:55:03.59#ibcon#end of sib2, iclass 16, count 0 2006.257.15:55:03.59#ibcon#*mode == 0, iclass 16, count 0 2006.257.15:55:03.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.15:55:03.59#ibcon#[25=BW32\r\n] 2006.257.15:55:03.59#ibcon#*before write, iclass 16, count 0 2006.257.15:55:03.59#ibcon#enter sib2, iclass 16, count 0 2006.257.15:55:03.59#ibcon#flushed, iclass 16, count 0 2006.257.15:55:03.59#ibcon#about to write, iclass 16, count 0 2006.257.15:55:03.59#ibcon#wrote, iclass 16, count 0 2006.257.15:55:03.59#ibcon#about to read 3, iclass 16, count 0 2006.257.15:55:03.62#ibcon#read 3, iclass 16, count 0 2006.257.15:55:03.62#ibcon#about to read 4, iclass 16, count 0 2006.257.15:55:03.62#ibcon#read 4, iclass 16, count 0 2006.257.15:55:03.62#ibcon#about to read 5, iclass 16, count 0 2006.257.15:55:03.62#ibcon#read 5, iclass 16, count 0 2006.257.15:55:03.62#ibcon#about to read 6, iclass 16, count 0 2006.257.15:55:03.62#ibcon#read 6, iclass 16, count 0 2006.257.15:55:03.62#ibcon#end of sib2, iclass 16, count 0 2006.257.15:55:03.62#ibcon#*after write, iclass 16, count 0 2006.257.15:55:03.62#ibcon#*before return 0, iclass 16, count 0 2006.257.15:55:03.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:03.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.15:55:03.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.15:55:03.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.15:55:03.62$vck44/vbbw=wide 2006.257.15:55:03.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.15:55:03.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.15:55:03.62#ibcon#ireg 8 cls_cnt 0 2006.257.15:55:03.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:55:03.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:55:03.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:55:03.69#ibcon#enter wrdev, iclass 18, count 0 2006.257.15:55:03.69#ibcon#first serial, iclass 18, count 0 2006.257.15:55:03.69#ibcon#enter sib2, iclass 18, count 0 2006.257.15:55:03.69#ibcon#flushed, iclass 18, count 0 2006.257.15:55:03.69#ibcon#about to write, iclass 18, count 0 2006.257.15:55:03.69#ibcon#wrote, iclass 18, count 0 2006.257.15:55:03.69#ibcon#about to read 3, iclass 18, count 0 2006.257.15:55:03.71#ibcon#read 3, iclass 18, count 0 2006.257.15:55:03.71#ibcon#about to read 4, iclass 18, count 0 2006.257.15:55:03.71#ibcon#read 4, iclass 18, count 0 2006.257.15:55:03.71#ibcon#about to read 5, iclass 18, count 0 2006.257.15:55:03.71#ibcon#read 5, iclass 18, count 0 2006.257.15:55:03.71#ibcon#about to read 6, iclass 18, count 0 2006.257.15:55:03.71#ibcon#read 6, iclass 18, count 0 2006.257.15:55:03.71#ibcon#end of sib2, iclass 18, count 0 2006.257.15:55:03.71#ibcon#*mode == 0, iclass 18, count 0 2006.257.15:55:03.71#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.15:55:03.71#ibcon#[27=BW32\r\n] 2006.257.15:55:03.71#ibcon#*before write, iclass 18, count 0 2006.257.15:55:03.71#ibcon#enter sib2, iclass 18, count 0 2006.257.15:55:03.71#ibcon#flushed, iclass 18, count 0 2006.257.15:55:03.71#ibcon#about to write, iclass 18, count 0 2006.257.15:55:03.71#ibcon#wrote, iclass 18, count 0 2006.257.15:55:03.71#ibcon#about to read 3, iclass 18, count 0 2006.257.15:55:03.74#ibcon#read 3, iclass 18, count 0 2006.257.15:55:03.74#ibcon#about to read 4, iclass 18, count 0 2006.257.15:55:03.75#ibcon#read 4, iclass 18, count 0 2006.257.15:55:03.75#ibcon#about to read 5, iclass 18, count 0 2006.257.15:55:03.75#ibcon#read 5, iclass 18, count 0 2006.257.15:55:03.75#ibcon#about to read 6, iclass 18, count 0 2006.257.15:55:03.75#ibcon#read 6, iclass 18, count 0 2006.257.15:55:03.75#ibcon#end of sib2, iclass 18, count 0 2006.257.15:55:03.75#ibcon#*after write, iclass 18, count 0 2006.257.15:55:03.75#ibcon#*before return 0, iclass 18, count 0 2006.257.15:55:03.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:55:03.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.15:55:03.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.15:55:03.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.15:55:03.75$setupk4/ifdk4 2006.257.15:55:03.75$ifdk4/lo= 2006.257.15:55:03.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.15:55:03.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.15:55:03.75$ifdk4/patch= 2006.257.15:55:03.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.15:55:03.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.15:55:03.75$setupk4/!*+20s 2006.257.15:55:09.16#abcon#<5=/13 1.2 3.7 17.33 971014.0\r\n> 2006.257.15:55:09.18#abcon#{5=INTERFACE CLEAR} 2006.257.15:55:09.24#abcon#[5=S1D000X0/0*\r\n] 2006.257.15:55:18.24$setupk4/"tpicd 2006.257.15:55:18.24$setupk4/echo=off 2006.257.15:55:18.24$setupk4/xlog=off 2006.257.15:55:18.24:!2006.257.15:57:36 2006.257.15:55:51.14#trakl#Source acquired 2006.257.15:55:53.14#flagr#flagr/antenna,acquired 2006.257.15:57:36.00:preob 2006.257.15:57:36.14/onsource/TRACKING 2006.257.15:57:36.14:!2006.257.15:57:46 2006.257.15:57:46.00:"tape 2006.257.15:57:46.00:"st=record 2006.257.15:57:46.00:data_valid=on 2006.257.15:57:46.00:midob 2006.257.15:57:47.14/onsource/TRACKING 2006.257.15:57:47.14/wx/17.32,1014.0,97 2006.257.15:57:47.28/cable/+6.4834E-03 2006.257.15:57:48.37/va/01,08,usb,yes,31,34 2006.257.15:57:48.37/va/02,07,usb,yes,34,35 2006.257.15:57:48.37/va/03,08,usb,yes,30,32 2006.257.15:57:48.37/va/04,07,usb,yes,35,37 2006.257.15:57:48.37/va/05,04,usb,yes,31,32 2006.257.15:57:48.37/va/06,04,usb,yes,35,35 2006.257.15:57:48.37/va/07,04,usb,yes,36,36 2006.257.15:57:48.37/va/08,04,usb,yes,30,37 2006.257.15:57:48.60/valo/01,524.99,yes,locked 2006.257.15:57:48.60/valo/02,534.99,yes,locked 2006.257.15:57:48.60/valo/03,564.99,yes,locked 2006.257.15:57:48.60/valo/04,624.99,yes,locked 2006.257.15:57:48.60/valo/05,734.99,yes,locked 2006.257.15:57:48.60/valo/06,814.99,yes,locked 2006.257.15:57:48.60/valo/07,864.99,yes,locked 2006.257.15:57:48.60/valo/08,884.99,yes,locked 2006.257.15:57:49.69/vb/01,04,usb,yes,31,29 2006.257.15:57:49.69/vb/02,05,usb,yes,29,29 2006.257.15:57:49.69/vb/03,04,usb,yes,30,33 2006.257.15:57:49.69/vb/04,05,usb,yes,31,30 2006.257.15:57:49.69/vb/05,04,usb,yes,27,30 2006.257.15:57:49.69/vb/06,04,usb,yes,32,28 2006.257.15:57:49.69/vb/07,04,usb,yes,31,31 2006.257.15:57:49.69/vb/08,04,usb,yes,29,32 2006.257.15:57:49.93/vblo/01,629.99,yes,locked 2006.257.15:57:49.93/vblo/02,634.99,yes,locked 2006.257.15:57:49.93/vblo/03,649.99,yes,locked 2006.257.15:57:49.93/vblo/04,679.99,yes,locked 2006.257.15:57:49.93/vblo/05,709.99,yes,locked 2006.257.15:57:49.93/vblo/06,719.99,yes,locked 2006.257.15:57:49.93/vblo/07,734.99,yes,locked 2006.257.15:57:49.93/vblo/08,744.99,yes,locked 2006.257.15:57:50.08/vabw/8 2006.257.15:57:50.23/vbbw/8 2006.257.15:57:50.34/xfe/off,on,15.0 2006.257.15:57:50.72/ifatt/23,28,28,28 2006.257.15:57:51.08/fmout-gps/S +4.55E-07 2006.257.15:57:51.12:!2006.257.15:59:46 2006.257.15:59:46.01:data_valid=off 2006.257.15:59:46.01:"et 2006.257.15:59:46.02:!+3s 2006.257.15:59:49.03:"tape 2006.257.15:59:49.03:postob 2006.257.15:59:49.15/cable/+6.4834E-03 2006.257.15:59:49.15/wx/17.31,1014.1,97 2006.257.15:59:49.21/fmout-gps/S +4.56E-07 2006.257.15:59:49.21:scan_name=257-1602,jd0609,50 2006.257.15:59:49.22:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.15:59:50.14#flagr#flagr/antenna,new-source 2006.257.15:59:50.14:checkk5 2006.257.15:59:50.54/chk_autoobs//k5ts1/ autoobs is running! 2006.257.15:59:50.93/chk_autoobs//k5ts2/ autoobs is running! 2006.257.15:59:51.34/chk_autoobs//k5ts3/ autoobs is running! 2006.257.15:59:51.73/chk_autoobs//k5ts4/ autoobs is running! 2006.257.15:59:52.13/chk_obsdata//k5ts1/T2571557??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.15:59:52.53/chk_obsdata//k5ts2/T2571557??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.15:59:52.94/chk_obsdata//k5ts3/T2571557??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.15:59:53.33/chk_obsdata//k5ts4/T2571557??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.15:59:54.05/k5log//k5ts1_log_newline 2006.257.15:59:54.77/k5log//k5ts2_log_newline 2006.257.15:59:55.48/k5log//k5ts3_log_newline 2006.257.15:59:56.18/k5log//k5ts4_log_newline 2006.257.15:59:56.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.15:59:56.21:setupk4=1 2006.257.15:59:56.21$setupk4/echo=on 2006.257.15:59:56.21$setupk4/pcalon 2006.257.15:59:56.21$pcalon/"no phase cal control is implemented here 2006.257.15:59:56.21$setupk4/"tpicd=stop 2006.257.15:59:56.21$setupk4/"rec=synch_on 2006.257.15:59:56.21$setupk4/"rec_mode=128 2006.257.15:59:56.21$setupk4/!* 2006.257.15:59:56.21$setupk4/recpk4 2006.257.15:59:56.21$recpk4/recpatch= 2006.257.15:59:56.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.15:59:56.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.15:59:56.21$setupk4/vck44 2006.257.15:59:56.21$vck44/valo=1,524.99 2006.257.15:59:56.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.15:59:56.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.15:59:56.21#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:56.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:56.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:56.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:56.21#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:59:56.21#ibcon#first serial, iclass 31, count 0 2006.257.15:59:56.21#ibcon#enter sib2, iclass 31, count 0 2006.257.15:59:56.21#ibcon#flushed, iclass 31, count 0 2006.257.15:59:56.21#ibcon#about to write, iclass 31, count 0 2006.257.15:59:56.21#ibcon#wrote, iclass 31, count 0 2006.257.15:59:56.21#ibcon#about to read 3, iclass 31, count 0 2006.257.15:59:56.23#ibcon#read 3, iclass 31, count 0 2006.257.15:59:56.23#ibcon#about to read 4, iclass 31, count 0 2006.257.15:59:56.23#ibcon#read 4, iclass 31, count 0 2006.257.15:59:56.23#ibcon#about to read 5, iclass 31, count 0 2006.257.15:59:56.23#ibcon#read 5, iclass 31, count 0 2006.257.15:59:56.23#ibcon#about to read 6, iclass 31, count 0 2006.257.15:59:56.23#ibcon#read 6, iclass 31, count 0 2006.257.15:59:56.23#ibcon#end of sib2, iclass 31, count 0 2006.257.15:59:56.23#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:59:56.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:59:56.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.15:59:56.23#ibcon#*before write, iclass 31, count 0 2006.257.15:59:56.23#ibcon#enter sib2, iclass 31, count 0 2006.257.15:59:56.23#ibcon#flushed, iclass 31, count 0 2006.257.15:59:56.23#ibcon#about to write, iclass 31, count 0 2006.257.15:59:56.23#ibcon#wrote, iclass 31, count 0 2006.257.15:59:56.23#ibcon#about to read 3, iclass 31, count 0 2006.257.15:59:56.28#ibcon#read 3, iclass 31, count 0 2006.257.15:59:56.28#ibcon#about to read 4, iclass 31, count 0 2006.257.15:59:56.28#ibcon#read 4, iclass 31, count 0 2006.257.15:59:56.28#ibcon#about to read 5, iclass 31, count 0 2006.257.15:59:56.28#ibcon#read 5, iclass 31, count 0 2006.257.15:59:56.28#ibcon#about to read 6, iclass 31, count 0 2006.257.15:59:56.28#ibcon#read 6, iclass 31, count 0 2006.257.15:59:56.28#ibcon#end of sib2, iclass 31, count 0 2006.257.15:59:56.28#ibcon#*after write, iclass 31, count 0 2006.257.15:59:56.28#ibcon#*before return 0, iclass 31, count 0 2006.257.15:59:56.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:56.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:56.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:59:56.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:59:56.28$vck44/va=1,8 2006.257.15:59:56.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.15:59:56.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.15:59:56.28#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:56.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:56.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:56.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:56.28#ibcon#enter wrdev, iclass 33, count 2 2006.257.15:59:56.28#ibcon#first serial, iclass 33, count 2 2006.257.15:59:56.28#ibcon#enter sib2, iclass 33, count 2 2006.257.15:59:56.28#ibcon#flushed, iclass 33, count 2 2006.257.15:59:56.28#ibcon#about to write, iclass 33, count 2 2006.257.15:59:56.28#ibcon#wrote, iclass 33, count 2 2006.257.15:59:56.28#ibcon#about to read 3, iclass 33, count 2 2006.257.15:59:56.30#ibcon#read 3, iclass 33, count 2 2006.257.15:59:56.30#ibcon#about to read 4, iclass 33, count 2 2006.257.15:59:56.30#ibcon#read 4, iclass 33, count 2 2006.257.15:59:56.30#ibcon#about to read 5, iclass 33, count 2 2006.257.15:59:56.30#ibcon#read 5, iclass 33, count 2 2006.257.15:59:56.30#ibcon#about to read 6, iclass 33, count 2 2006.257.15:59:56.30#ibcon#read 6, iclass 33, count 2 2006.257.15:59:56.30#ibcon#end of sib2, iclass 33, count 2 2006.257.15:59:56.30#ibcon#*mode == 0, iclass 33, count 2 2006.257.15:59:56.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.15:59:56.30#ibcon#[25=AT01-08\r\n] 2006.257.15:59:56.30#ibcon#*before write, iclass 33, count 2 2006.257.15:59:56.30#ibcon#enter sib2, iclass 33, count 2 2006.257.15:59:56.30#ibcon#flushed, iclass 33, count 2 2006.257.15:59:56.30#ibcon#about to write, iclass 33, count 2 2006.257.15:59:56.30#ibcon#wrote, iclass 33, count 2 2006.257.15:59:56.30#ibcon#about to read 3, iclass 33, count 2 2006.257.15:59:56.33#ibcon#read 3, iclass 33, count 2 2006.257.15:59:56.33#ibcon#about to read 4, iclass 33, count 2 2006.257.15:59:56.33#ibcon#read 4, iclass 33, count 2 2006.257.15:59:56.33#ibcon#about to read 5, iclass 33, count 2 2006.257.15:59:56.33#ibcon#read 5, iclass 33, count 2 2006.257.15:59:56.33#ibcon#about to read 6, iclass 33, count 2 2006.257.15:59:56.33#ibcon#read 6, iclass 33, count 2 2006.257.15:59:56.33#ibcon#end of sib2, iclass 33, count 2 2006.257.15:59:56.33#ibcon#*after write, iclass 33, count 2 2006.257.15:59:56.33#ibcon#*before return 0, iclass 33, count 2 2006.257.15:59:56.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:56.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:56.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.15:59:56.33#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:56.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:56.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:56.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:56.45#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:59:56.45#ibcon#first serial, iclass 33, count 0 2006.257.15:59:56.45#ibcon#enter sib2, iclass 33, count 0 2006.257.15:59:56.45#ibcon#flushed, iclass 33, count 0 2006.257.15:59:56.45#ibcon#about to write, iclass 33, count 0 2006.257.15:59:56.45#ibcon#wrote, iclass 33, count 0 2006.257.15:59:56.45#ibcon#about to read 3, iclass 33, count 0 2006.257.15:59:56.47#ibcon#read 3, iclass 33, count 0 2006.257.15:59:56.47#ibcon#about to read 4, iclass 33, count 0 2006.257.15:59:56.47#ibcon#read 4, iclass 33, count 0 2006.257.15:59:56.47#ibcon#about to read 5, iclass 33, count 0 2006.257.15:59:56.47#ibcon#read 5, iclass 33, count 0 2006.257.15:59:56.47#ibcon#about to read 6, iclass 33, count 0 2006.257.15:59:56.47#ibcon#read 6, iclass 33, count 0 2006.257.15:59:56.47#ibcon#end of sib2, iclass 33, count 0 2006.257.15:59:56.47#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:59:56.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:59:56.47#ibcon#[25=USB\r\n] 2006.257.15:59:56.47#ibcon#*before write, iclass 33, count 0 2006.257.15:59:56.47#ibcon#enter sib2, iclass 33, count 0 2006.257.15:59:56.47#ibcon#flushed, iclass 33, count 0 2006.257.15:59:56.47#ibcon#about to write, iclass 33, count 0 2006.257.15:59:56.47#ibcon#wrote, iclass 33, count 0 2006.257.15:59:56.47#ibcon#about to read 3, iclass 33, count 0 2006.257.15:59:56.50#ibcon#read 3, iclass 33, count 0 2006.257.15:59:56.50#ibcon#about to read 4, iclass 33, count 0 2006.257.15:59:56.50#ibcon#read 4, iclass 33, count 0 2006.257.15:59:56.50#ibcon#about to read 5, iclass 33, count 0 2006.257.15:59:56.50#ibcon#read 5, iclass 33, count 0 2006.257.15:59:56.50#ibcon#about to read 6, iclass 33, count 0 2006.257.15:59:56.50#ibcon#read 6, iclass 33, count 0 2006.257.15:59:56.50#ibcon#end of sib2, iclass 33, count 0 2006.257.15:59:56.50#ibcon#*after write, iclass 33, count 0 2006.257.15:59:56.50#ibcon#*before return 0, iclass 33, count 0 2006.257.15:59:56.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:56.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:56.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:59:56.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:59:56.50$vck44/valo=2,534.99 2006.257.15:59:56.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.15:59:56.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.15:59:56.50#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:56.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:56.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:56.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:56.50#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:59:56.50#ibcon#first serial, iclass 35, count 0 2006.257.15:59:56.50#ibcon#enter sib2, iclass 35, count 0 2006.257.15:59:56.50#ibcon#flushed, iclass 35, count 0 2006.257.15:59:56.50#ibcon#about to write, iclass 35, count 0 2006.257.15:59:56.50#ibcon#wrote, iclass 35, count 0 2006.257.15:59:56.50#ibcon#about to read 3, iclass 35, count 0 2006.257.15:59:56.52#ibcon#read 3, iclass 35, count 0 2006.257.15:59:56.52#ibcon#about to read 4, iclass 35, count 0 2006.257.15:59:56.52#ibcon#read 4, iclass 35, count 0 2006.257.15:59:56.52#ibcon#about to read 5, iclass 35, count 0 2006.257.15:59:56.52#ibcon#read 5, iclass 35, count 0 2006.257.15:59:56.52#ibcon#about to read 6, iclass 35, count 0 2006.257.15:59:56.52#ibcon#read 6, iclass 35, count 0 2006.257.15:59:56.52#ibcon#end of sib2, iclass 35, count 0 2006.257.15:59:56.52#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:59:56.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:59:56.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.15:59:56.52#ibcon#*before write, iclass 35, count 0 2006.257.15:59:56.52#ibcon#enter sib2, iclass 35, count 0 2006.257.15:59:56.52#ibcon#flushed, iclass 35, count 0 2006.257.15:59:56.52#ibcon#about to write, iclass 35, count 0 2006.257.15:59:56.52#ibcon#wrote, iclass 35, count 0 2006.257.15:59:56.52#ibcon#about to read 3, iclass 35, count 0 2006.257.15:59:56.56#ibcon#read 3, iclass 35, count 0 2006.257.15:59:56.56#ibcon#about to read 4, iclass 35, count 0 2006.257.15:59:56.56#ibcon#read 4, iclass 35, count 0 2006.257.15:59:56.56#ibcon#about to read 5, iclass 35, count 0 2006.257.15:59:56.56#ibcon#read 5, iclass 35, count 0 2006.257.15:59:56.56#ibcon#about to read 6, iclass 35, count 0 2006.257.15:59:56.56#ibcon#read 6, iclass 35, count 0 2006.257.15:59:56.56#ibcon#end of sib2, iclass 35, count 0 2006.257.15:59:56.56#ibcon#*after write, iclass 35, count 0 2006.257.15:59:56.56#ibcon#*before return 0, iclass 35, count 0 2006.257.15:59:56.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:56.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:56.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:59:56.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:59:56.56$vck44/va=2,7 2006.257.15:59:56.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.15:59:56.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.15:59:56.56#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:56.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:56.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:56.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:56.62#ibcon#enter wrdev, iclass 37, count 2 2006.257.15:59:56.62#ibcon#first serial, iclass 37, count 2 2006.257.15:59:56.62#ibcon#enter sib2, iclass 37, count 2 2006.257.15:59:56.62#ibcon#flushed, iclass 37, count 2 2006.257.15:59:56.62#ibcon#about to write, iclass 37, count 2 2006.257.15:59:56.62#ibcon#wrote, iclass 37, count 2 2006.257.15:59:56.62#ibcon#about to read 3, iclass 37, count 2 2006.257.15:59:56.64#ibcon#read 3, iclass 37, count 2 2006.257.15:59:56.64#ibcon#about to read 4, iclass 37, count 2 2006.257.15:59:56.64#ibcon#read 4, iclass 37, count 2 2006.257.15:59:56.64#ibcon#about to read 5, iclass 37, count 2 2006.257.15:59:56.64#ibcon#read 5, iclass 37, count 2 2006.257.15:59:56.64#ibcon#about to read 6, iclass 37, count 2 2006.257.15:59:56.64#ibcon#read 6, iclass 37, count 2 2006.257.15:59:56.64#ibcon#end of sib2, iclass 37, count 2 2006.257.15:59:56.64#ibcon#*mode == 0, iclass 37, count 2 2006.257.15:59:56.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.15:59:56.64#ibcon#[25=AT02-07\r\n] 2006.257.15:59:56.64#ibcon#*before write, iclass 37, count 2 2006.257.15:59:56.64#ibcon#enter sib2, iclass 37, count 2 2006.257.15:59:56.64#ibcon#flushed, iclass 37, count 2 2006.257.15:59:56.64#ibcon#about to write, iclass 37, count 2 2006.257.15:59:56.64#ibcon#wrote, iclass 37, count 2 2006.257.15:59:56.64#ibcon#about to read 3, iclass 37, count 2 2006.257.15:59:56.67#ibcon#read 3, iclass 37, count 2 2006.257.15:59:56.67#ibcon#about to read 4, iclass 37, count 2 2006.257.15:59:56.67#ibcon#read 4, iclass 37, count 2 2006.257.15:59:56.67#ibcon#about to read 5, iclass 37, count 2 2006.257.15:59:56.67#ibcon#read 5, iclass 37, count 2 2006.257.15:59:56.67#ibcon#about to read 6, iclass 37, count 2 2006.257.15:59:56.67#ibcon#read 6, iclass 37, count 2 2006.257.15:59:56.67#ibcon#end of sib2, iclass 37, count 2 2006.257.15:59:56.67#ibcon#*after write, iclass 37, count 2 2006.257.15:59:56.67#ibcon#*before return 0, iclass 37, count 2 2006.257.15:59:56.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:56.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:56.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.15:59:56.67#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:56.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:56.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:56.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:56.79#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:59:56.79#ibcon#first serial, iclass 37, count 0 2006.257.15:59:56.79#ibcon#enter sib2, iclass 37, count 0 2006.257.15:59:56.79#ibcon#flushed, iclass 37, count 0 2006.257.15:59:56.79#ibcon#about to write, iclass 37, count 0 2006.257.15:59:56.79#ibcon#wrote, iclass 37, count 0 2006.257.15:59:56.79#ibcon#about to read 3, iclass 37, count 0 2006.257.15:59:56.81#ibcon#read 3, iclass 37, count 0 2006.257.15:59:56.81#ibcon#about to read 4, iclass 37, count 0 2006.257.15:59:56.81#ibcon#read 4, iclass 37, count 0 2006.257.15:59:56.81#ibcon#about to read 5, iclass 37, count 0 2006.257.15:59:56.81#ibcon#read 5, iclass 37, count 0 2006.257.15:59:56.81#ibcon#about to read 6, iclass 37, count 0 2006.257.15:59:56.81#ibcon#read 6, iclass 37, count 0 2006.257.15:59:56.81#ibcon#end of sib2, iclass 37, count 0 2006.257.15:59:56.81#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:59:56.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:59:56.81#ibcon#[25=USB\r\n] 2006.257.15:59:56.81#ibcon#*before write, iclass 37, count 0 2006.257.15:59:56.81#ibcon#enter sib2, iclass 37, count 0 2006.257.15:59:56.81#ibcon#flushed, iclass 37, count 0 2006.257.15:59:56.81#ibcon#about to write, iclass 37, count 0 2006.257.15:59:56.81#ibcon#wrote, iclass 37, count 0 2006.257.15:59:56.81#ibcon#about to read 3, iclass 37, count 0 2006.257.15:59:56.84#ibcon#read 3, iclass 37, count 0 2006.257.15:59:56.84#ibcon#about to read 4, iclass 37, count 0 2006.257.15:59:56.84#ibcon#read 4, iclass 37, count 0 2006.257.15:59:56.84#ibcon#about to read 5, iclass 37, count 0 2006.257.15:59:56.84#ibcon#read 5, iclass 37, count 0 2006.257.15:59:56.84#ibcon#about to read 6, iclass 37, count 0 2006.257.15:59:56.84#ibcon#read 6, iclass 37, count 0 2006.257.15:59:56.84#ibcon#end of sib2, iclass 37, count 0 2006.257.15:59:56.84#ibcon#*after write, iclass 37, count 0 2006.257.15:59:56.84#ibcon#*before return 0, iclass 37, count 0 2006.257.15:59:56.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:56.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:56.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:59:56.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:59:56.84$vck44/valo=3,564.99 2006.257.15:59:56.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.15:59:56.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.15:59:56.84#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:56.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:56.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:56.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:56.84#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:59:56.84#ibcon#first serial, iclass 39, count 0 2006.257.15:59:56.84#ibcon#enter sib2, iclass 39, count 0 2006.257.15:59:56.84#ibcon#flushed, iclass 39, count 0 2006.257.15:59:56.84#ibcon#about to write, iclass 39, count 0 2006.257.15:59:56.84#ibcon#wrote, iclass 39, count 0 2006.257.15:59:56.84#ibcon#about to read 3, iclass 39, count 0 2006.257.15:59:56.86#ibcon#read 3, iclass 39, count 0 2006.257.15:59:56.86#ibcon#about to read 4, iclass 39, count 0 2006.257.15:59:56.86#ibcon#read 4, iclass 39, count 0 2006.257.15:59:56.86#ibcon#about to read 5, iclass 39, count 0 2006.257.15:59:56.86#ibcon#read 5, iclass 39, count 0 2006.257.15:59:56.86#ibcon#about to read 6, iclass 39, count 0 2006.257.15:59:56.86#ibcon#read 6, iclass 39, count 0 2006.257.15:59:56.86#ibcon#end of sib2, iclass 39, count 0 2006.257.15:59:56.86#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:59:56.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:59:56.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.15:59:56.86#ibcon#*before write, iclass 39, count 0 2006.257.15:59:56.86#ibcon#enter sib2, iclass 39, count 0 2006.257.15:59:56.86#ibcon#flushed, iclass 39, count 0 2006.257.15:59:56.86#ibcon#about to write, iclass 39, count 0 2006.257.15:59:56.86#ibcon#wrote, iclass 39, count 0 2006.257.15:59:56.86#ibcon#about to read 3, iclass 39, count 0 2006.257.15:59:56.90#ibcon#read 3, iclass 39, count 0 2006.257.15:59:56.90#ibcon#about to read 4, iclass 39, count 0 2006.257.15:59:56.90#ibcon#read 4, iclass 39, count 0 2006.257.15:59:56.90#ibcon#about to read 5, iclass 39, count 0 2006.257.15:59:56.90#ibcon#read 5, iclass 39, count 0 2006.257.15:59:56.90#ibcon#about to read 6, iclass 39, count 0 2006.257.15:59:56.90#ibcon#read 6, iclass 39, count 0 2006.257.15:59:56.90#ibcon#end of sib2, iclass 39, count 0 2006.257.15:59:56.90#ibcon#*after write, iclass 39, count 0 2006.257.15:59:56.90#ibcon#*before return 0, iclass 39, count 0 2006.257.15:59:56.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:56.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:56.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:59:56.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:59:56.90$vck44/va=3,8 2006.257.15:59:56.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.15:59:56.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.15:59:56.90#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:56.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:59:56.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:59:56.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:59:56.96#ibcon#enter wrdev, iclass 3, count 2 2006.257.15:59:56.96#ibcon#first serial, iclass 3, count 2 2006.257.15:59:56.96#ibcon#enter sib2, iclass 3, count 2 2006.257.15:59:56.96#ibcon#flushed, iclass 3, count 2 2006.257.15:59:56.96#ibcon#about to write, iclass 3, count 2 2006.257.15:59:56.96#ibcon#wrote, iclass 3, count 2 2006.257.15:59:56.96#ibcon#about to read 3, iclass 3, count 2 2006.257.15:59:56.98#ibcon#read 3, iclass 3, count 2 2006.257.15:59:56.98#ibcon#about to read 4, iclass 3, count 2 2006.257.15:59:56.98#ibcon#read 4, iclass 3, count 2 2006.257.15:59:56.98#ibcon#about to read 5, iclass 3, count 2 2006.257.15:59:56.98#ibcon#read 5, iclass 3, count 2 2006.257.15:59:56.98#ibcon#about to read 6, iclass 3, count 2 2006.257.15:59:56.98#ibcon#read 6, iclass 3, count 2 2006.257.15:59:56.98#ibcon#end of sib2, iclass 3, count 2 2006.257.15:59:56.98#ibcon#*mode == 0, iclass 3, count 2 2006.257.15:59:56.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.15:59:56.98#ibcon#[25=AT03-08\r\n] 2006.257.15:59:56.98#ibcon#*before write, iclass 3, count 2 2006.257.15:59:56.98#ibcon#enter sib2, iclass 3, count 2 2006.257.15:59:56.98#ibcon#flushed, iclass 3, count 2 2006.257.15:59:56.98#ibcon#about to write, iclass 3, count 2 2006.257.15:59:56.98#ibcon#wrote, iclass 3, count 2 2006.257.15:59:56.98#ibcon#about to read 3, iclass 3, count 2 2006.257.15:59:57.01#ibcon#read 3, iclass 3, count 2 2006.257.15:59:57.01#ibcon#about to read 4, iclass 3, count 2 2006.257.15:59:57.01#ibcon#read 4, iclass 3, count 2 2006.257.15:59:57.01#ibcon#about to read 5, iclass 3, count 2 2006.257.15:59:57.01#ibcon#read 5, iclass 3, count 2 2006.257.15:59:57.01#ibcon#about to read 6, iclass 3, count 2 2006.257.15:59:57.01#ibcon#read 6, iclass 3, count 2 2006.257.15:59:57.01#ibcon#end of sib2, iclass 3, count 2 2006.257.15:59:57.01#ibcon#*after write, iclass 3, count 2 2006.257.15:59:57.01#ibcon#*before return 0, iclass 3, count 2 2006.257.15:59:57.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:59:57.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:59:57.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.15:59:57.01#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:57.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:59:57.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:59:57.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:59:57.13#ibcon#enter wrdev, iclass 3, count 0 2006.257.15:59:57.13#ibcon#first serial, iclass 3, count 0 2006.257.15:59:57.13#ibcon#enter sib2, iclass 3, count 0 2006.257.15:59:57.13#ibcon#flushed, iclass 3, count 0 2006.257.15:59:57.13#ibcon#about to write, iclass 3, count 0 2006.257.15:59:57.13#ibcon#wrote, iclass 3, count 0 2006.257.15:59:57.13#ibcon#about to read 3, iclass 3, count 0 2006.257.15:59:57.15#ibcon#read 3, iclass 3, count 0 2006.257.15:59:57.15#ibcon#about to read 4, iclass 3, count 0 2006.257.15:59:57.15#ibcon#read 4, iclass 3, count 0 2006.257.15:59:57.15#ibcon#about to read 5, iclass 3, count 0 2006.257.15:59:57.15#ibcon#read 5, iclass 3, count 0 2006.257.15:59:57.15#ibcon#about to read 6, iclass 3, count 0 2006.257.15:59:57.15#ibcon#read 6, iclass 3, count 0 2006.257.15:59:57.15#ibcon#end of sib2, iclass 3, count 0 2006.257.15:59:57.15#ibcon#*mode == 0, iclass 3, count 0 2006.257.15:59:57.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.15:59:57.15#ibcon#[25=USB\r\n] 2006.257.15:59:57.15#ibcon#*before write, iclass 3, count 0 2006.257.15:59:57.15#ibcon#enter sib2, iclass 3, count 0 2006.257.15:59:57.15#ibcon#flushed, iclass 3, count 0 2006.257.15:59:57.15#ibcon#about to write, iclass 3, count 0 2006.257.15:59:57.15#ibcon#wrote, iclass 3, count 0 2006.257.15:59:57.15#ibcon#about to read 3, iclass 3, count 0 2006.257.15:59:57.18#ibcon#read 3, iclass 3, count 0 2006.257.15:59:57.18#ibcon#about to read 4, iclass 3, count 0 2006.257.15:59:57.18#ibcon#read 4, iclass 3, count 0 2006.257.15:59:57.18#ibcon#about to read 5, iclass 3, count 0 2006.257.15:59:57.18#ibcon#read 5, iclass 3, count 0 2006.257.15:59:57.18#ibcon#about to read 6, iclass 3, count 0 2006.257.15:59:57.18#ibcon#read 6, iclass 3, count 0 2006.257.15:59:57.18#ibcon#end of sib2, iclass 3, count 0 2006.257.15:59:57.18#ibcon#*after write, iclass 3, count 0 2006.257.15:59:57.18#ibcon#*before return 0, iclass 3, count 0 2006.257.15:59:57.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:59:57.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.15:59:57.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.15:59:57.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.15:59:57.18$vck44/valo=4,624.99 2006.257.15:59:57.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.15:59:57.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.15:59:57.18#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:57.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:59:57.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:59:57.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:59:57.18#ibcon#enter wrdev, iclass 5, count 0 2006.257.15:59:57.18#ibcon#first serial, iclass 5, count 0 2006.257.15:59:57.18#ibcon#enter sib2, iclass 5, count 0 2006.257.15:59:57.18#ibcon#flushed, iclass 5, count 0 2006.257.15:59:57.18#ibcon#about to write, iclass 5, count 0 2006.257.15:59:57.18#ibcon#wrote, iclass 5, count 0 2006.257.15:59:57.18#ibcon#about to read 3, iclass 5, count 0 2006.257.15:59:57.20#ibcon#read 3, iclass 5, count 0 2006.257.15:59:57.20#ibcon#about to read 4, iclass 5, count 0 2006.257.15:59:57.20#ibcon#read 4, iclass 5, count 0 2006.257.15:59:57.20#ibcon#about to read 5, iclass 5, count 0 2006.257.15:59:57.20#ibcon#read 5, iclass 5, count 0 2006.257.15:59:57.20#ibcon#about to read 6, iclass 5, count 0 2006.257.15:59:57.20#ibcon#read 6, iclass 5, count 0 2006.257.15:59:57.20#ibcon#end of sib2, iclass 5, count 0 2006.257.15:59:57.20#ibcon#*mode == 0, iclass 5, count 0 2006.257.15:59:57.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.15:59:57.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.15:59:57.20#ibcon#*before write, iclass 5, count 0 2006.257.15:59:57.20#ibcon#enter sib2, iclass 5, count 0 2006.257.15:59:57.20#ibcon#flushed, iclass 5, count 0 2006.257.15:59:57.20#ibcon#about to write, iclass 5, count 0 2006.257.15:59:57.20#ibcon#wrote, iclass 5, count 0 2006.257.15:59:57.20#ibcon#about to read 3, iclass 5, count 0 2006.257.15:59:57.24#ibcon#read 3, iclass 5, count 0 2006.257.15:59:57.24#ibcon#about to read 4, iclass 5, count 0 2006.257.15:59:57.24#ibcon#read 4, iclass 5, count 0 2006.257.15:59:57.24#ibcon#about to read 5, iclass 5, count 0 2006.257.15:59:57.24#ibcon#read 5, iclass 5, count 0 2006.257.15:59:57.24#ibcon#about to read 6, iclass 5, count 0 2006.257.15:59:57.24#ibcon#read 6, iclass 5, count 0 2006.257.15:59:57.24#ibcon#end of sib2, iclass 5, count 0 2006.257.15:59:57.24#ibcon#*after write, iclass 5, count 0 2006.257.15:59:57.24#ibcon#*before return 0, iclass 5, count 0 2006.257.15:59:57.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:59:57.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.15:59:57.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.15:59:57.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.15:59:57.24$vck44/va=4,7 2006.257.15:59:57.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.15:59:57.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.15:59:57.24#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:57.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:59:57.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:59:57.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:59:57.30#ibcon#enter wrdev, iclass 7, count 2 2006.257.15:59:57.30#ibcon#first serial, iclass 7, count 2 2006.257.15:59:57.30#ibcon#enter sib2, iclass 7, count 2 2006.257.15:59:57.30#ibcon#flushed, iclass 7, count 2 2006.257.15:59:57.30#ibcon#about to write, iclass 7, count 2 2006.257.15:59:57.30#ibcon#wrote, iclass 7, count 2 2006.257.15:59:57.30#ibcon#about to read 3, iclass 7, count 2 2006.257.15:59:57.32#ibcon#read 3, iclass 7, count 2 2006.257.15:59:57.32#ibcon#about to read 4, iclass 7, count 2 2006.257.15:59:57.32#ibcon#read 4, iclass 7, count 2 2006.257.15:59:57.32#ibcon#about to read 5, iclass 7, count 2 2006.257.15:59:57.32#ibcon#read 5, iclass 7, count 2 2006.257.15:59:57.32#ibcon#about to read 6, iclass 7, count 2 2006.257.15:59:57.32#ibcon#read 6, iclass 7, count 2 2006.257.15:59:57.32#ibcon#end of sib2, iclass 7, count 2 2006.257.15:59:57.32#ibcon#*mode == 0, iclass 7, count 2 2006.257.15:59:57.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.15:59:57.32#ibcon#[25=AT04-07\r\n] 2006.257.15:59:57.32#ibcon#*before write, iclass 7, count 2 2006.257.15:59:57.32#ibcon#enter sib2, iclass 7, count 2 2006.257.15:59:57.32#ibcon#flushed, iclass 7, count 2 2006.257.15:59:57.32#ibcon#about to write, iclass 7, count 2 2006.257.15:59:57.32#ibcon#wrote, iclass 7, count 2 2006.257.15:59:57.32#ibcon#about to read 3, iclass 7, count 2 2006.257.15:59:57.35#ibcon#read 3, iclass 7, count 2 2006.257.15:59:57.35#ibcon#about to read 4, iclass 7, count 2 2006.257.15:59:57.35#ibcon#read 4, iclass 7, count 2 2006.257.15:59:57.35#ibcon#about to read 5, iclass 7, count 2 2006.257.15:59:57.35#ibcon#read 5, iclass 7, count 2 2006.257.15:59:57.35#ibcon#about to read 6, iclass 7, count 2 2006.257.15:59:57.35#ibcon#read 6, iclass 7, count 2 2006.257.15:59:57.35#ibcon#end of sib2, iclass 7, count 2 2006.257.15:59:57.35#ibcon#*after write, iclass 7, count 2 2006.257.15:59:57.35#ibcon#*before return 0, iclass 7, count 2 2006.257.15:59:57.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:59:57.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.15:59:57.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.15:59:57.36#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:57.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:59:57.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:59:57.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:59:57.47#ibcon#enter wrdev, iclass 7, count 0 2006.257.15:59:57.47#ibcon#first serial, iclass 7, count 0 2006.257.15:59:57.47#ibcon#enter sib2, iclass 7, count 0 2006.257.15:59:57.47#ibcon#flushed, iclass 7, count 0 2006.257.15:59:57.47#ibcon#about to write, iclass 7, count 0 2006.257.15:59:57.47#ibcon#wrote, iclass 7, count 0 2006.257.15:59:57.47#ibcon#about to read 3, iclass 7, count 0 2006.257.15:59:57.49#ibcon#read 3, iclass 7, count 0 2006.257.15:59:57.49#ibcon#about to read 4, iclass 7, count 0 2006.257.15:59:57.49#ibcon#read 4, iclass 7, count 0 2006.257.15:59:57.49#ibcon#about to read 5, iclass 7, count 0 2006.257.15:59:57.49#ibcon#read 5, iclass 7, count 0 2006.257.15:59:57.49#ibcon#about to read 6, iclass 7, count 0 2006.257.15:59:57.49#ibcon#read 6, iclass 7, count 0 2006.257.15:59:57.49#ibcon#end of sib2, iclass 7, count 0 2006.257.15:59:57.49#ibcon#*mode == 0, iclass 7, count 0 2006.257.15:59:57.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.15:59:57.49#ibcon#[25=USB\r\n] 2006.257.15:59:57.49#ibcon#*before write, iclass 7, count 0 2006.257.15:59:57.49#ibcon#enter sib2, iclass 7, count 0 2006.257.15:59:57.49#ibcon#flushed, iclass 7, count 0 2006.257.15:59:57.49#ibcon#about to write, iclass 7, count 0 2006.257.15:59:57.49#ibcon#wrote, iclass 7, count 0 2006.257.15:59:57.49#ibcon#about to read 3, iclass 7, count 0 2006.257.15:59:57.52#ibcon#read 3, iclass 7, count 0 2006.257.15:59:57.52#ibcon#about to read 4, iclass 7, count 0 2006.257.15:59:57.52#ibcon#read 4, iclass 7, count 0 2006.257.15:59:57.52#ibcon#about to read 5, iclass 7, count 0 2006.257.15:59:57.52#ibcon#read 5, iclass 7, count 0 2006.257.15:59:57.52#ibcon#about to read 6, iclass 7, count 0 2006.257.15:59:57.52#ibcon#read 6, iclass 7, count 0 2006.257.15:59:57.52#ibcon#end of sib2, iclass 7, count 0 2006.257.15:59:57.52#ibcon#*after write, iclass 7, count 0 2006.257.15:59:57.52#ibcon#*before return 0, iclass 7, count 0 2006.257.15:59:57.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:59:57.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.15:59:57.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.15:59:57.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.15:59:57.52$vck44/valo=5,734.99 2006.257.15:59:57.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.15:59:57.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.15:59:57.52#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:57.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:59:57.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:59:57.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:59:57.52#ibcon#enter wrdev, iclass 11, count 0 2006.257.15:59:57.52#ibcon#first serial, iclass 11, count 0 2006.257.15:59:57.52#ibcon#enter sib2, iclass 11, count 0 2006.257.15:59:57.52#ibcon#flushed, iclass 11, count 0 2006.257.15:59:57.52#ibcon#about to write, iclass 11, count 0 2006.257.15:59:57.52#ibcon#wrote, iclass 11, count 0 2006.257.15:59:57.52#ibcon#about to read 3, iclass 11, count 0 2006.257.15:59:57.54#ibcon#read 3, iclass 11, count 0 2006.257.15:59:57.54#ibcon#about to read 4, iclass 11, count 0 2006.257.15:59:57.54#ibcon#read 4, iclass 11, count 0 2006.257.15:59:57.54#ibcon#about to read 5, iclass 11, count 0 2006.257.15:59:57.54#ibcon#read 5, iclass 11, count 0 2006.257.15:59:57.54#ibcon#about to read 6, iclass 11, count 0 2006.257.15:59:57.54#ibcon#read 6, iclass 11, count 0 2006.257.15:59:57.54#ibcon#end of sib2, iclass 11, count 0 2006.257.15:59:57.54#ibcon#*mode == 0, iclass 11, count 0 2006.257.15:59:57.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.15:59:57.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.15:59:57.54#ibcon#*before write, iclass 11, count 0 2006.257.15:59:57.54#ibcon#enter sib2, iclass 11, count 0 2006.257.15:59:57.54#ibcon#flushed, iclass 11, count 0 2006.257.15:59:57.54#ibcon#about to write, iclass 11, count 0 2006.257.15:59:57.54#ibcon#wrote, iclass 11, count 0 2006.257.15:59:57.54#ibcon#about to read 3, iclass 11, count 0 2006.257.15:59:57.58#ibcon#read 3, iclass 11, count 0 2006.257.15:59:57.58#ibcon#about to read 4, iclass 11, count 0 2006.257.15:59:57.58#ibcon#read 4, iclass 11, count 0 2006.257.15:59:57.58#ibcon#about to read 5, iclass 11, count 0 2006.257.15:59:57.58#ibcon#read 5, iclass 11, count 0 2006.257.15:59:57.58#ibcon#about to read 6, iclass 11, count 0 2006.257.15:59:57.58#ibcon#read 6, iclass 11, count 0 2006.257.15:59:57.58#ibcon#end of sib2, iclass 11, count 0 2006.257.15:59:57.58#ibcon#*after write, iclass 11, count 0 2006.257.15:59:57.58#ibcon#*before return 0, iclass 11, count 0 2006.257.15:59:57.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:59:57.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.15:59:57.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.15:59:57.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.15:59:57.58$vck44/va=5,4 2006.257.15:59:57.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.15:59:57.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.15:59:57.58#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:57.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:59:57.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:59:57.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:59:57.64#ibcon#enter wrdev, iclass 13, count 2 2006.257.15:59:57.64#ibcon#first serial, iclass 13, count 2 2006.257.15:59:57.64#ibcon#enter sib2, iclass 13, count 2 2006.257.15:59:57.64#ibcon#flushed, iclass 13, count 2 2006.257.15:59:57.64#ibcon#about to write, iclass 13, count 2 2006.257.15:59:57.64#ibcon#wrote, iclass 13, count 2 2006.257.15:59:57.64#ibcon#about to read 3, iclass 13, count 2 2006.257.15:59:57.66#ibcon#read 3, iclass 13, count 2 2006.257.15:59:57.66#ibcon#about to read 4, iclass 13, count 2 2006.257.15:59:57.66#ibcon#read 4, iclass 13, count 2 2006.257.15:59:57.66#ibcon#about to read 5, iclass 13, count 2 2006.257.15:59:57.66#ibcon#read 5, iclass 13, count 2 2006.257.15:59:57.66#ibcon#about to read 6, iclass 13, count 2 2006.257.15:59:57.66#ibcon#read 6, iclass 13, count 2 2006.257.15:59:57.66#ibcon#end of sib2, iclass 13, count 2 2006.257.15:59:57.66#ibcon#*mode == 0, iclass 13, count 2 2006.257.15:59:57.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.15:59:57.66#ibcon#[25=AT05-04\r\n] 2006.257.15:59:57.66#ibcon#*before write, iclass 13, count 2 2006.257.15:59:57.66#ibcon#enter sib2, iclass 13, count 2 2006.257.15:59:57.66#ibcon#flushed, iclass 13, count 2 2006.257.15:59:57.66#ibcon#about to write, iclass 13, count 2 2006.257.15:59:57.66#ibcon#wrote, iclass 13, count 2 2006.257.15:59:57.66#ibcon#about to read 3, iclass 13, count 2 2006.257.15:59:57.69#ibcon#read 3, iclass 13, count 2 2006.257.15:59:57.69#ibcon#about to read 4, iclass 13, count 2 2006.257.15:59:57.69#ibcon#read 4, iclass 13, count 2 2006.257.15:59:57.69#ibcon#about to read 5, iclass 13, count 2 2006.257.15:59:57.69#ibcon#read 5, iclass 13, count 2 2006.257.15:59:57.69#ibcon#about to read 6, iclass 13, count 2 2006.257.15:59:57.69#ibcon#read 6, iclass 13, count 2 2006.257.15:59:57.69#ibcon#end of sib2, iclass 13, count 2 2006.257.15:59:57.69#ibcon#*after write, iclass 13, count 2 2006.257.15:59:57.69#ibcon#*before return 0, iclass 13, count 2 2006.257.15:59:57.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:59:57.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.15:59:57.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.15:59:57.69#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:57.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:59:57.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:59:57.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:59:57.81#ibcon#enter wrdev, iclass 13, count 0 2006.257.15:59:57.81#ibcon#first serial, iclass 13, count 0 2006.257.15:59:57.81#ibcon#enter sib2, iclass 13, count 0 2006.257.15:59:57.81#ibcon#flushed, iclass 13, count 0 2006.257.15:59:57.81#ibcon#about to write, iclass 13, count 0 2006.257.15:59:57.81#ibcon#wrote, iclass 13, count 0 2006.257.15:59:57.81#ibcon#about to read 3, iclass 13, count 0 2006.257.15:59:57.83#ibcon#read 3, iclass 13, count 0 2006.257.15:59:57.83#ibcon#about to read 4, iclass 13, count 0 2006.257.15:59:57.83#ibcon#read 4, iclass 13, count 0 2006.257.15:59:57.83#ibcon#about to read 5, iclass 13, count 0 2006.257.15:59:57.83#ibcon#read 5, iclass 13, count 0 2006.257.15:59:57.83#ibcon#about to read 6, iclass 13, count 0 2006.257.15:59:57.83#ibcon#read 6, iclass 13, count 0 2006.257.15:59:57.83#ibcon#end of sib2, iclass 13, count 0 2006.257.15:59:57.83#ibcon#*mode == 0, iclass 13, count 0 2006.257.15:59:57.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.15:59:57.83#ibcon#[25=USB\r\n] 2006.257.15:59:57.83#ibcon#*before write, iclass 13, count 0 2006.257.15:59:57.83#ibcon#enter sib2, iclass 13, count 0 2006.257.15:59:57.83#ibcon#flushed, iclass 13, count 0 2006.257.15:59:57.83#ibcon#about to write, iclass 13, count 0 2006.257.15:59:57.83#ibcon#wrote, iclass 13, count 0 2006.257.15:59:57.83#ibcon#about to read 3, iclass 13, count 0 2006.257.15:59:57.86#ibcon#read 3, iclass 13, count 0 2006.257.15:59:57.86#ibcon#about to read 4, iclass 13, count 0 2006.257.15:59:57.86#ibcon#read 4, iclass 13, count 0 2006.257.15:59:57.86#ibcon#about to read 5, iclass 13, count 0 2006.257.15:59:57.86#ibcon#read 5, iclass 13, count 0 2006.257.15:59:57.86#ibcon#about to read 6, iclass 13, count 0 2006.257.15:59:57.86#ibcon#read 6, iclass 13, count 0 2006.257.15:59:57.86#ibcon#end of sib2, iclass 13, count 0 2006.257.15:59:57.86#ibcon#*after write, iclass 13, count 0 2006.257.15:59:57.86#ibcon#*before return 0, iclass 13, count 0 2006.257.15:59:57.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:59:57.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.15:59:57.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.15:59:57.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.15:59:57.86$vck44/valo=6,814.99 2006.257.15:59:57.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.15:59:57.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.15:59:57.86#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:57.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:59:57.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:59:57.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:59:57.86#ibcon#enter wrdev, iclass 15, count 0 2006.257.15:59:57.86#ibcon#first serial, iclass 15, count 0 2006.257.15:59:57.86#ibcon#enter sib2, iclass 15, count 0 2006.257.15:59:57.86#ibcon#flushed, iclass 15, count 0 2006.257.15:59:57.86#ibcon#about to write, iclass 15, count 0 2006.257.15:59:57.86#ibcon#wrote, iclass 15, count 0 2006.257.15:59:57.86#ibcon#about to read 3, iclass 15, count 0 2006.257.15:59:57.88#ibcon#read 3, iclass 15, count 0 2006.257.15:59:57.88#ibcon#about to read 4, iclass 15, count 0 2006.257.15:59:57.88#ibcon#read 4, iclass 15, count 0 2006.257.15:59:57.88#ibcon#about to read 5, iclass 15, count 0 2006.257.15:59:57.88#ibcon#read 5, iclass 15, count 0 2006.257.15:59:57.88#ibcon#about to read 6, iclass 15, count 0 2006.257.15:59:57.88#ibcon#read 6, iclass 15, count 0 2006.257.15:59:57.88#ibcon#end of sib2, iclass 15, count 0 2006.257.15:59:57.88#ibcon#*mode == 0, iclass 15, count 0 2006.257.15:59:57.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.15:59:57.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.15:59:57.88#ibcon#*before write, iclass 15, count 0 2006.257.15:59:57.88#ibcon#enter sib2, iclass 15, count 0 2006.257.15:59:57.88#ibcon#flushed, iclass 15, count 0 2006.257.15:59:57.88#ibcon#about to write, iclass 15, count 0 2006.257.15:59:57.88#ibcon#wrote, iclass 15, count 0 2006.257.15:59:57.88#ibcon#about to read 3, iclass 15, count 0 2006.257.15:59:57.92#ibcon#read 3, iclass 15, count 0 2006.257.15:59:57.92#ibcon#about to read 4, iclass 15, count 0 2006.257.15:59:57.92#ibcon#read 4, iclass 15, count 0 2006.257.15:59:57.92#ibcon#about to read 5, iclass 15, count 0 2006.257.15:59:57.92#ibcon#read 5, iclass 15, count 0 2006.257.15:59:57.92#ibcon#about to read 6, iclass 15, count 0 2006.257.15:59:57.92#ibcon#read 6, iclass 15, count 0 2006.257.15:59:57.92#ibcon#end of sib2, iclass 15, count 0 2006.257.15:59:57.92#ibcon#*after write, iclass 15, count 0 2006.257.15:59:57.92#ibcon#*before return 0, iclass 15, count 0 2006.257.15:59:57.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:59:57.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.15:59:57.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.15:59:57.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.15:59:57.92$vck44/va=6,4 2006.257.15:59:57.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.15:59:57.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.15:59:57.92#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:57.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:59:57.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:59:57.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:59:57.98#ibcon#enter wrdev, iclass 17, count 2 2006.257.15:59:57.98#ibcon#first serial, iclass 17, count 2 2006.257.15:59:57.98#ibcon#enter sib2, iclass 17, count 2 2006.257.15:59:57.98#ibcon#flushed, iclass 17, count 2 2006.257.15:59:57.98#ibcon#about to write, iclass 17, count 2 2006.257.15:59:57.98#ibcon#wrote, iclass 17, count 2 2006.257.15:59:57.98#ibcon#about to read 3, iclass 17, count 2 2006.257.15:59:58.00#ibcon#read 3, iclass 17, count 2 2006.257.15:59:58.00#ibcon#about to read 4, iclass 17, count 2 2006.257.15:59:58.00#ibcon#read 4, iclass 17, count 2 2006.257.15:59:58.00#ibcon#about to read 5, iclass 17, count 2 2006.257.15:59:58.00#ibcon#read 5, iclass 17, count 2 2006.257.15:59:58.00#ibcon#about to read 6, iclass 17, count 2 2006.257.15:59:58.00#ibcon#read 6, iclass 17, count 2 2006.257.15:59:58.00#ibcon#end of sib2, iclass 17, count 2 2006.257.15:59:58.00#ibcon#*mode == 0, iclass 17, count 2 2006.257.15:59:58.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.15:59:58.00#ibcon#[25=AT06-04\r\n] 2006.257.15:59:58.00#ibcon#*before write, iclass 17, count 2 2006.257.15:59:58.00#ibcon#enter sib2, iclass 17, count 2 2006.257.15:59:58.00#ibcon#flushed, iclass 17, count 2 2006.257.15:59:58.00#ibcon#about to write, iclass 17, count 2 2006.257.15:59:58.00#ibcon#wrote, iclass 17, count 2 2006.257.15:59:58.00#ibcon#about to read 3, iclass 17, count 2 2006.257.15:59:58.03#ibcon#read 3, iclass 17, count 2 2006.257.15:59:58.03#ibcon#about to read 4, iclass 17, count 2 2006.257.15:59:58.03#ibcon#read 4, iclass 17, count 2 2006.257.15:59:58.03#ibcon#about to read 5, iclass 17, count 2 2006.257.15:59:58.03#ibcon#read 5, iclass 17, count 2 2006.257.15:59:58.03#ibcon#about to read 6, iclass 17, count 2 2006.257.15:59:58.03#ibcon#read 6, iclass 17, count 2 2006.257.15:59:58.03#ibcon#end of sib2, iclass 17, count 2 2006.257.15:59:58.03#ibcon#*after write, iclass 17, count 2 2006.257.15:59:58.03#ibcon#*before return 0, iclass 17, count 2 2006.257.15:59:58.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:59:58.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.15:59:58.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.15:59:58.03#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:58.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:59:58.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:59:58.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:59:58.15#ibcon#enter wrdev, iclass 17, count 0 2006.257.15:59:58.15#ibcon#first serial, iclass 17, count 0 2006.257.15:59:58.15#ibcon#enter sib2, iclass 17, count 0 2006.257.15:59:58.15#ibcon#flushed, iclass 17, count 0 2006.257.15:59:58.15#ibcon#about to write, iclass 17, count 0 2006.257.15:59:58.15#ibcon#wrote, iclass 17, count 0 2006.257.15:59:58.15#ibcon#about to read 3, iclass 17, count 0 2006.257.15:59:58.17#ibcon#read 3, iclass 17, count 0 2006.257.15:59:58.17#ibcon#about to read 4, iclass 17, count 0 2006.257.15:59:58.17#ibcon#read 4, iclass 17, count 0 2006.257.15:59:58.17#ibcon#about to read 5, iclass 17, count 0 2006.257.15:59:58.17#ibcon#read 5, iclass 17, count 0 2006.257.15:59:58.17#ibcon#about to read 6, iclass 17, count 0 2006.257.15:59:58.17#ibcon#read 6, iclass 17, count 0 2006.257.15:59:58.17#ibcon#end of sib2, iclass 17, count 0 2006.257.15:59:58.17#ibcon#*mode == 0, iclass 17, count 0 2006.257.15:59:58.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.15:59:58.17#ibcon#[25=USB\r\n] 2006.257.15:59:58.17#ibcon#*before write, iclass 17, count 0 2006.257.15:59:58.17#ibcon#enter sib2, iclass 17, count 0 2006.257.15:59:58.17#ibcon#flushed, iclass 17, count 0 2006.257.15:59:58.17#ibcon#about to write, iclass 17, count 0 2006.257.15:59:58.17#ibcon#wrote, iclass 17, count 0 2006.257.15:59:58.17#ibcon#about to read 3, iclass 17, count 0 2006.257.15:59:58.20#ibcon#read 3, iclass 17, count 0 2006.257.15:59:58.20#ibcon#about to read 4, iclass 17, count 0 2006.257.15:59:58.20#ibcon#read 4, iclass 17, count 0 2006.257.15:59:58.20#ibcon#about to read 5, iclass 17, count 0 2006.257.15:59:58.20#ibcon#read 5, iclass 17, count 0 2006.257.15:59:58.20#ibcon#about to read 6, iclass 17, count 0 2006.257.15:59:58.20#ibcon#read 6, iclass 17, count 0 2006.257.15:59:58.20#ibcon#end of sib2, iclass 17, count 0 2006.257.15:59:58.20#ibcon#*after write, iclass 17, count 0 2006.257.15:59:58.20#ibcon#*before return 0, iclass 17, count 0 2006.257.15:59:58.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:59:58.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.15:59:58.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.15:59:58.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.15:59:58.20$vck44/valo=7,864.99 2006.257.15:59:58.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.15:59:58.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.15:59:58.20#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:58.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:59:58.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:59:58.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:59:58.20#ibcon#enter wrdev, iclass 19, count 0 2006.257.15:59:58.20#ibcon#first serial, iclass 19, count 0 2006.257.15:59:58.20#ibcon#enter sib2, iclass 19, count 0 2006.257.15:59:58.20#ibcon#flushed, iclass 19, count 0 2006.257.15:59:58.20#ibcon#about to write, iclass 19, count 0 2006.257.15:59:58.20#ibcon#wrote, iclass 19, count 0 2006.257.15:59:58.20#ibcon#about to read 3, iclass 19, count 0 2006.257.15:59:58.22#ibcon#read 3, iclass 19, count 0 2006.257.15:59:58.22#ibcon#about to read 4, iclass 19, count 0 2006.257.15:59:58.22#ibcon#read 4, iclass 19, count 0 2006.257.15:59:58.22#ibcon#about to read 5, iclass 19, count 0 2006.257.15:59:58.22#ibcon#read 5, iclass 19, count 0 2006.257.15:59:58.22#ibcon#about to read 6, iclass 19, count 0 2006.257.15:59:58.22#ibcon#read 6, iclass 19, count 0 2006.257.15:59:58.22#ibcon#end of sib2, iclass 19, count 0 2006.257.15:59:58.22#ibcon#*mode == 0, iclass 19, count 0 2006.257.15:59:58.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.15:59:58.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.15:59:58.22#ibcon#*before write, iclass 19, count 0 2006.257.15:59:58.22#ibcon#enter sib2, iclass 19, count 0 2006.257.15:59:58.22#ibcon#flushed, iclass 19, count 0 2006.257.15:59:58.22#ibcon#about to write, iclass 19, count 0 2006.257.15:59:58.22#ibcon#wrote, iclass 19, count 0 2006.257.15:59:58.22#ibcon#about to read 3, iclass 19, count 0 2006.257.15:59:58.26#ibcon#read 3, iclass 19, count 0 2006.257.15:59:58.26#ibcon#about to read 4, iclass 19, count 0 2006.257.15:59:58.26#ibcon#read 4, iclass 19, count 0 2006.257.15:59:58.26#ibcon#about to read 5, iclass 19, count 0 2006.257.15:59:58.26#ibcon#read 5, iclass 19, count 0 2006.257.15:59:58.26#ibcon#about to read 6, iclass 19, count 0 2006.257.15:59:58.26#ibcon#read 6, iclass 19, count 0 2006.257.15:59:58.26#ibcon#end of sib2, iclass 19, count 0 2006.257.15:59:58.26#ibcon#*after write, iclass 19, count 0 2006.257.15:59:58.26#ibcon#*before return 0, iclass 19, count 0 2006.257.15:59:58.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:59:58.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.15:59:58.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.15:59:58.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.15:59:58.26$vck44/va=7,4 2006.257.15:59:58.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.15:59:58.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.15:59:58.26#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:58.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:59:58.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:59:58.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:59:58.32#ibcon#enter wrdev, iclass 21, count 2 2006.257.15:59:58.32#ibcon#first serial, iclass 21, count 2 2006.257.15:59:58.32#ibcon#enter sib2, iclass 21, count 2 2006.257.15:59:58.32#ibcon#flushed, iclass 21, count 2 2006.257.15:59:58.32#ibcon#about to write, iclass 21, count 2 2006.257.15:59:58.32#ibcon#wrote, iclass 21, count 2 2006.257.15:59:58.32#ibcon#about to read 3, iclass 21, count 2 2006.257.15:59:58.34#ibcon#read 3, iclass 21, count 2 2006.257.15:59:58.34#ibcon#about to read 4, iclass 21, count 2 2006.257.15:59:58.34#ibcon#read 4, iclass 21, count 2 2006.257.15:59:58.34#ibcon#about to read 5, iclass 21, count 2 2006.257.15:59:58.34#ibcon#read 5, iclass 21, count 2 2006.257.15:59:58.34#ibcon#about to read 6, iclass 21, count 2 2006.257.15:59:58.34#ibcon#read 6, iclass 21, count 2 2006.257.15:59:58.34#ibcon#end of sib2, iclass 21, count 2 2006.257.15:59:58.34#ibcon#*mode == 0, iclass 21, count 2 2006.257.15:59:58.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.15:59:58.34#ibcon#[25=AT07-04\r\n] 2006.257.15:59:58.34#ibcon#*before write, iclass 21, count 2 2006.257.15:59:58.34#ibcon#enter sib2, iclass 21, count 2 2006.257.15:59:58.34#ibcon#flushed, iclass 21, count 2 2006.257.15:59:58.34#ibcon#about to write, iclass 21, count 2 2006.257.15:59:58.34#ibcon#wrote, iclass 21, count 2 2006.257.15:59:58.34#ibcon#about to read 3, iclass 21, count 2 2006.257.15:59:58.37#ibcon#read 3, iclass 21, count 2 2006.257.15:59:58.37#ibcon#about to read 4, iclass 21, count 2 2006.257.15:59:58.37#ibcon#read 4, iclass 21, count 2 2006.257.15:59:58.37#ibcon#about to read 5, iclass 21, count 2 2006.257.15:59:58.37#ibcon#read 5, iclass 21, count 2 2006.257.15:59:58.37#ibcon#about to read 6, iclass 21, count 2 2006.257.15:59:58.37#ibcon#read 6, iclass 21, count 2 2006.257.15:59:58.37#ibcon#end of sib2, iclass 21, count 2 2006.257.15:59:58.37#ibcon#*after write, iclass 21, count 2 2006.257.15:59:58.37#ibcon#*before return 0, iclass 21, count 2 2006.257.15:59:58.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:59:58.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.15:59:58.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.15:59:58.37#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:58.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:59:58.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:59:58.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:59:58.49#ibcon#enter wrdev, iclass 21, count 0 2006.257.15:59:58.49#ibcon#first serial, iclass 21, count 0 2006.257.15:59:58.49#ibcon#enter sib2, iclass 21, count 0 2006.257.15:59:58.49#ibcon#flushed, iclass 21, count 0 2006.257.15:59:58.49#ibcon#about to write, iclass 21, count 0 2006.257.15:59:58.49#ibcon#wrote, iclass 21, count 0 2006.257.15:59:58.49#ibcon#about to read 3, iclass 21, count 0 2006.257.15:59:58.51#ibcon#read 3, iclass 21, count 0 2006.257.15:59:58.51#ibcon#about to read 4, iclass 21, count 0 2006.257.15:59:58.51#ibcon#read 4, iclass 21, count 0 2006.257.15:59:58.51#ibcon#about to read 5, iclass 21, count 0 2006.257.15:59:58.51#ibcon#read 5, iclass 21, count 0 2006.257.15:59:58.51#ibcon#about to read 6, iclass 21, count 0 2006.257.15:59:58.51#ibcon#read 6, iclass 21, count 0 2006.257.15:59:58.51#ibcon#end of sib2, iclass 21, count 0 2006.257.15:59:58.51#ibcon#*mode == 0, iclass 21, count 0 2006.257.15:59:58.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.15:59:58.51#ibcon#[25=USB\r\n] 2006.257.15:59:58.51#ibcon#*before write, iclass 21, count 0 2006.257.15:59:58.51#ibcon#enter sib2, iclass 21, count 0 2006.257.15:59:58.51#ibcon#flushed, iclass 21, count 0 2006.257.15:59:58.51#ibcon#about to write, iclass 21, count 0 2006.257.15:59:58.51#ibcon#wrote, iclass 21, count 0 2006.257.15:59:58.51#ibcon#about to read 3, iclass 21, count 0 2006.257.15:59:58.54#ibcon#read 3, iclass 21, count 0 2006.257.15:59:58.54#ibcon#about to read 4, iclass 21, count 0 2006.257.15:59:58.54#ibcon#read 4, iclass 21, count 0 2006.257.15:59:58.54#ibcon#about to read 5, iclass 21, count 0 2006.257.15:59:58.54#ibcon#read 5, iclass 21, count 0 2006.257.15:59:58.54#ibcon#about to read 6, iclass 21, count 0 2006.257.15:59:58.54#ibcon#read 6, iclass 21, count 0 2006.257.15:59:58.54#ibcon#end of sib2, iclass 21, count 0 2006.257.15:59:58.54#ibcon#*after write, iclass 21, count 0 2006.257.15:59:58.54#ibcon#*before return 0, iclass 21, count 0 2006.257.15:59:58.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:59:58.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.15:59:58.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.15:59:58.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.15:59:58.54$vck44/valo=8,884.99 2006.257.15:59:58.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.15:59:58.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.15:59:58.54#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:58.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:59:58.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:59:58.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:59:58.54#ibcon#enter wrdev, iclass 23, count 0 2006.257.15:59:58.54#ibcon#first serial, iclass 23, count 0 2006.257.15:59:58.54#ibcon#enter sib2, iclass 23, count 0 2006.257.15:59:58.54#ibcon#flushed, iclass 23, count 0 2006.257.15:59:58.54#ibcon#about to write, iclass 23, count 0 2006.257.15:59:58.54#ibcon#wrote, iclass 23, count 0 2006.257.15:59:58.54#ibcon#about to read 3, iclass 23, count 0 2006.257.15:59:58.56#ibcon#read 3, iclass 23, count 0 2006.257.15:59:58.56#ibcon#about to read 4, iclass 23, count 0 2006.257.15:59:58.56#ibcon#read 4, iclass 23, count 0 2006.257.15:59:58.56#ibcon#about to read 5, iclass 23, count 0 2006.257.15:59:58.56#ibcon#read 5, iclass 23, count 0 2006.257.15:59:58.56#ibcon#about to read 6, iclass 23, count 0 2006.257.15:59:58.56#ibcon#read 6, iclass 23, count 0 2006.257.15:59:58.56#ibcon#end of sib2, iclass 23, count 0 2006.257.15:59:58.56#ibcon#*mode == 0, iclass 23, count 0 2006.257.15:59:58.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.15:59:58.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.15:59:58.56#ibcon#*before write, iclass 23, count 0 2006.257.15:59:58.56#ibcon#enter sib2, iclass 23, count 0 2006.257.15:59:58.56#ibcon#flushed, iclass 23, count 0 2006.257.15:59:58.56#ibcon#about to write, iclass 23, count 0 2006.257.15:59:58.56#ibcon#wrote, iclass 23, count 0 2006.257.15:59:58.56#ibcon#about to read 3, iclass 23, count 0 2006.257.15:59:58.60#ibcon#read 3, iclass 23, count 0 2006.257.15:59:58.60#ibcon#about to read 4, iclass 23, count 0 2006.257.15:59:58.60#ibcon#read 4, iclass 23, count 0 2006.257.15:59:58.60#ibcon#about to read 5, iclass 23, count 0 2006.257.15:59:58.60#ibcon#read 5, iclass 23, count 0 2006.257.15:59:58.60#ibcon#about to read 6, iclass 23, count 0 2006.257.15:59:58.60#ibcon#read 6, iclass 23, count 0 2006.257.15:59:58.60#ibcon#end of sib2, iclass 23, count 0 2006.257.15:59:58.60#ibcon#*after write, iclass 23, count 0 2006.257.15:59:58.60#ibcon#*before return 0, iclass 23, count 0 2006.257.15:59:58.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:59:58.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.15:59:58.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.15:59:58.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.15:59:58.60$vck44/va=8,4 2006.257.15:59:58.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.15:59:58.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.15:59:58.60#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:58.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:59:58.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:59:58.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:59:58.66#ibcon#enter wrdev, iclass 25, count 2 2006.257.15:59:58.66#ibcon#first serial, iclass 25, count 2 2006.257.15:59:58.66#ibcon#enter sib2, iclass 25, count 2 2006.257.15:59:58.66#ibcon#flushed, iclass 25, count 2 2006.257.15:59:58.66#ibcon#about to write, iclass 25, count 2 2006.257.15:59:58.66#ibcon#wrote, iclass 25, count 2 2006.257.15:59:58.66#ibcon#about to read 3, iclass 25, count 2 2006.257.15:59:58.68#ibcon#read 3, iclass 25, count 2 2006.257.15:59:58.68#ibcon#about to read 4, iclass 25, count 2 2006.257.15:59:58.68#ibcon#read 4, iclass 25, count 2 2006.257.15:59:58.68#ibcon#about to read 5, iclass 25, count 2 2006.257.15:59:58.68#ibcon#read 5, iclass 25, count 2 2006.257.15:59:58.68#ibcon#about to read 6, iclass 25, count 2 2006.257.15:59:58.68#ibcon#read 6, iclass 25, count 2 2006.257.15:59:58.68#ibcon#end of sib2, iclass 25, count 2 2006.257.15:59:58.68#ibcon#*mode == 0, iclass 25, count 2 2006.257.15:59:58.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.15:59:58.68#ibcon#[25=AT08-04\r\n] 2006.257.15:59:58.68#ibcon#*before write, iclass 25, count 2 2006.257.15:59:58.68#ibcon#enter sib2, iclass 25, count 2 2006.257.15:59:58.68#ibcon#flushed, iclass 25, count 2 2006.257.15:59:58.68#ibcon#about to write, iclass 25, count 2 2006.257.15:59:58.68#ibcon#wrote, iclass 25, count 2 2006.257.15:59:58.68#ibcon#about to read 3, iclass 25, count 2 2006.257.15:59:58.71#ibcon#read 3, iclass 25, count 2 2006.257.15:59:58.71#ibcon#about to read 4, iclass 25, count 2 2006.257.15:59:58.71#ibcon#read 4, iclass 25, count 2 2006.257.15:59:58.71#ibcon#about to read 5, iclass 25, count 2 2006.257.15:59:58.71#ibcon#read 5, iclass 25, count 2 2006.257.15:59:58.71#ibcon#about to read 6, iclass 25, count 2 2006.257.15:59:58.71#ibcon#read 6, iclass 25, count 2 2006.257.15:59:58.71#ibcon#end of sib2, iclass 25, count 2 2006.257.15:59:58.71#ibcon#*after write, iclass 25, count 2 2006.257.15:59:58.71#ibcon#*before return 0, iclass 25, count 2 2006.257.15:59:58.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:59:58.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.15:59:58.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.15:59:58.71#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:58.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:59:58.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:59:58.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:59:58.83#ibcon#enter wrdev, iclass 25, count 0 2006.257.15:59:58.83#ibcon#first serial, iclass 25, count 0 2006.257.15:59:58.83#ibcon#enter sib2, iclass 25, count 0 2006.257.15:59:58.83#ibcon#flushed, iclass 25, count 0 2006.257.15:59:58.83#ibcon#about to write, iclass 25, count 0 2006.257.15:59:58.83#ibcon#wrote, iclass 25, count 0 2006.257.15:59:58.83#ibcon#about to read 3, iclass 25, count 0 2006.257.15:59:58.85#ibcon#read 3, iclass 25, count 0 2006.257.15:59:58.85#ibcon#about to read 4, iclass 25, count 0 2006.257.15:59:58.85#ibcon#read 4, iclass 25, count 0 2006.257.15:59:58.85#ibcon#about to read 5, iclass 25, count 0 2006.257.15:59:58.85#ibcon#read 5, iclass 25, count 0 2006.257.15:59:58.85#ibcon#about to read 6, iclass 25, count 0 2006.257.15:59:58.85#ibcon#read 6, iclass 25, count 0 2006.257.15:59:58.85#ibcon#end of sib2, iclass 25, count 0 2006.257.15:59:58.85#ibcon#*mode == 0, iclass 25, count 0 2006.257.15:59:58.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.15:59:58.85#ibcon#[25=USB\r\n] 2006.257.15:59:58.85#ibcon#*before write, iclass 25, count 0 2006.257.15:59:58.85#ibcon#enter sib2, iclass 25, count 0 2006.257.15:59:58.85#ibcon#flushed, iclass 25, count 0 2006.257.15:59:58.85#ibcon#about to write, iclass 25, count 0 2006.257.15:59:58.85#ibcon#wrote, iclass 25, count 0 2006.257.15:59:58.85#ibcon#about to read 3, iclass 25, count 0 2006.257.15:59:58.88#ibcon#read 3, iclass 25, count 0 2006.257.15:59:58.88#ibcon#about to read 4, iclass 25, count 0 2006.257.15:59:58.88#ibcon#read 4, iclass 25, count 0 2006.257.15:59:58.88#ibcon#about to read 5, iclass 25, count 0 2006.257.15:59:58.88#ibcon#read 5, iclass 25, count 0 2006.257.15:59:58.88#ibcon#about to read 6, iclass 25, count 0 2006.257.15:59:58.88#ibcon#read 6, iclass 25, count 0 2006.257.15:59:58.88#ibcon#end of sib2, iclass 25, count 0 2006.257.15:59:58.88#ibcon#*after write, iclass 25, count 0 2006.257.15:59:58.88#ibcon#*before return 0, iclass 25, count 0 2006.257.15:59:58.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:59:58.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.15:59:58.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.15:59:58.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.15:59:58.88$vck44/vblo=1,629.99 2006.257.15:59:58.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.15:59:58.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.15:59:58.88#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:58.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:59:58.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:59:58.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:59:58.88#ibcon#enter wrdev, iclass 27, count 0 2006.257.15:59:58.88#ibcon#first serial, iclass 27, count 0 2006.257.15:59:58.88#ibcon#enter sib2, iclass 27, count 0 2006.257.15:59:58.88#ibcon#flushed, iclass 27, count 0 2006.257.15:59:58.88#ibcon#about to write, iclass 27, count 0 2006.257.15:59:58.88#ibcon#wrote, iclass 27, count 0 2006.257.15:59:58.88#ibcon#about to read 3, iclass 27, count 0 2006.257.15:59:58.90#ibcon#read 3, iclass 27, count 0 2006.257.15:59:58.90#ibcon#about to read 4, iclass 27, count 0 2006.257.15:59:58.90#ibcon#read 4, iclass 27, count 0 2006.257.15:59:58.90#ibcon#about to read 5, iclass 27, count 0 2006.257.15:59:58.90#ibcon#read 5, iclass 27, count 0 2006.257.15:59:58.90#ibcon#about to read 6, iclass 27, count 0 2006.257.15:59:58.90#ibcon#read 6, iclass 27, count 0 2006.257.15:59:58.90#ibcon#end of sib2, iclass 27, count 0 2006.257.15:59:58.90#ibcon#*mode == 0, iclass 27, count 0 2006.257.15:59:58.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.15:59:58.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.15:59:58.90#ibcon#*before write, iclass 27, count 0 2006.257.15:59:58.90#ibcon#enter sib2, iclass 27, count 0 2006.257.15:59:58.90#ibcon#flushed, iclass 27, count 0 2006.257.15:59:58.90#ibcon#about to write, iclass 27, count 0 2006.257.15:59:58.90#ibcon#wrote, iclass 27, count 0 2006.257.15:59:58.90#ibcon#about to read 3, iclass 27, count 0 2006.257.15:59:58.94#ibcon#read 3, iclass 27, count 0 2006.257.15:59:58.94#ibcon#about to read 4, iclass 27, count 0 2006.257.15:59:58.94#ibcon#read 4, iclass 27, count 0 2006.257.15:59:58.94#ibcon#about to read 5, iclass 27, count 0 2006.257.15:59:58.94#ibcon#read 5, iclass 27, count 0 2006.257.15:59:58.94#ibcon#about to read 6, iclass 27, count 0 2006.257.15:59:58.94#ibcon#read 6, iclass 27, count 0 2006.257.15:59:58.94#ibcon#end of sib2, iclass 27, count 0 2006.257.15:59:58.94#ibcon#*after write, iclass 27, count 0 2006.257.15:59:58.94#ibcon#*before return 0, iclass 27, count 0 2006.257.15:59:58.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:59:58.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.15:59:58.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.15:59:58.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.15:59:58.94$vck44/vb=1,4 2006.257.15:59:58.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.15:59:58.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.15:59:58.94#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:58.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:59:58.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:59:58.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:59:58.94#ibcon#enter wrdev, iclass 29, count 2 2006.257.15:59:58.94#ibcon#first serial, iclass 29, count 2 2006.257.15:59:58.94#ibcon#enter sib2, iclass 29, count 2 2006.257.15:59:58.94#ibcon#flushed, iclass 29, count 2 2006.257.15:59:58.94#ibcon#about to write, iclass 29, count 2 2006.257.15:59:58.94#ibcon#wrote, iclass 29, count 2 2006.257.15:59:58.94#ibcon#about to read 3, iclass 29, count 2 2006.257.15:59:58.96#ibcon#read 3, iclass 29, count 2 2006.257.15:59:58.96#ibcon#about to read 4, iclass 29, count 2 2006.257.15:59:58.96#ibcon#read 4, iclass 29, count 2 2006.257.15:59:58.96#ibcon#about to read 5, iclass 29, count 2 2006.257.15:59:58.96#ibcon#read 5, iclass 29, count 2 2006.257.15:59:58.96#ibcon#about to read 6, iclass 29, count 2 2006.257.15:59:58.96#ibcon#read 6, iclass 29, count 2 2006.257.15:59:58.96#ibcon#end of sib2, iclass 29, count 2 2006.257.15:59:58.96#ibcon#*mode == 0, iclass 29, count 2 2006.257.15:59:58.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.15:59:58.96#ibcon#[27=AT01-04\r\n] 2006.257.15:59:58.96#ibcon#*before write, iclass 29, count 2 2006.257.15:59:58.96#ibcon#enter sib2, iclass 29, count 2 2006.257.15:59:58.96#ibcon#flushed, iclass 29, count 2 2006.257.15:59:58.96#ibcon#about to write, iclass 29, count 2 2006.257.15:59:58.96#ibcon#wrote, iclass 29, count 2 2006.257.15:59:58.96#ibcon#about to read 3, iclass 29, count 2 2006.257.15:59:58.99#ibcon#read 3, iclass 29, count 2 2006.257.15:59:58.99#ibcon#about to read 4, iclass 29, count 2 2006.257.15:59:58.99#ibcon#read 4, iclass 29, count 2 2006.257.15:59:58.99#ibcon#about to read 5, iclass 29, count 2 2006.257.15:59:58.99#ibcon#read 5, iclass 29, count 2 2006.257.15:59:58.99#ibcon#about to read 6, iclass 29, count 2 2006.257.15:59:58.99#ibcon#read 6, iclass 29, count 2 2006.257.15:59:58.99#ibcon#end of sib2, iclass 29, count 2 2006.257.15:59:58.99#ibcon#*after write, iclass 29, count 2 2006.257.15:59:58.99#ibcon#*before return 0, iclass 29, count 2 2006.257.15:59:58.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:59:58.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.15:59:58.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.15:59:58.99#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:58.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:59:59.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:59:59.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:59:59.11#ibcon#enter wrdev, iclass 29, count 0 2006.257.15:59:59.11#ibcon#first serial, iclass 29, count 0 2006.257.15:59:59.11#ibcon#enter sib2, iclass 29, count 0 2006.257.15:59:59.11#ibcon#flushed, iclass 29, count 0 2006.257.15:59:59.11#ibcon#about to write, iclass 29, count 0 2006.257.15:59:59.11#ibcon#wrote, iclass 29, count 0 2006.257.15:59:59.11#ibcon#about to read 3, iclass 29, count 0 2006.257.15:59:59.13#ibcon#read 3, iclass 29, count 0 2006.257.15:59:59.13#ibcon#about to read 4, iclass 29, count 0 2006.257.15:59:59.13#ibcon#read 4, iclass 29, count 0 2006.257.15:59:59.13#ibcon#about to read 5, iclass 29, count 0 2006.257.15:59:59.13#ibcon#read 5, iclass 29, count 0 2006.257.15:59:59.13#ibcon#about to read 6, iclass 29, count 0 2006.257.15:59:59.13#ibcon#read 6, iclass 29, count 0 2006.257.15:59:59.13#ibcon#end of sib2, iclass 29, count 0 2006.257.15:59:59.13#ibcon#*mode == 0, iclass 29, count 0 2006.257.15:59:59.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.15:59:59.13#ibcon#[27=USB\r\n] 2006.257.15:59:59.13#ibcon#*before write, iclass 29, count 0 2006.257.15:59:59.13#ibcon#enter sib2, iclass 29, count 0 2006.257.15:59:59.13#ibcon#flushed, iclass 29, count 0 2006.257.15:59:59.13#ibcon#about to write, iclass 29, count 0 2006.257.15:59:59.13#ibcon#wrote, iclass 29, count 0 2006.257.15:59:59.13#ibcon#about to read 3, iclass 29, count 0 2006.257.15:59:59.16#ibcon#read 3, iclass 29, count 0 2006.257.15:59:59.16#ibcon#about to read 4, iclass 29, count 0 2006.257.15:59:59.16#ibcon#read 4, iclass 29, count 0 2006.257.15:59:59.16#ibcon#about to read 5, iclass 29, count 0 2006.257.15:59:59.16#ibcon#read 5, iclass 29, count 0 2006.257.15:59:59.16#ibcon#about to read 6, iclass 29, count 0 2006.257.15:59:59.16#ibcon#read 6, iclass 29, count 0 2006.257.15:59:59.16#ibcon#end of sib2, iclass 29, count 0 2006.257.15:59:59.16#ibcon#*after write, iclass 29, count 0 2006.257.15:59:59.16#ibcon#*before return 0, iclass 29, count 0 2006.257.15:59:59.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:59:59.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.15:59:59.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.15:59:59.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.15:59:59.16$vck44/vblo=2,634.99 2006.257.15:59:59.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.15:59:59.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.15:59:59.16#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:59.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:59.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:59.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:59.16#ibcon#enter wrdev, iclass 31, count 0 2006.257.15:59:59.16#ibcon#first serial, iclass 31, count 0 2006.257.15:59:59.16#ibcon#enter sib2, iclass 31, count 0 2006.257.15:59:59.16#ibcon#flushed, iclass 31, count 0 2006.257.15:59:59.16#ibcon#about to write, iclass 31, count 0 2006.257.15:59:59.16#ibcon#wrote, iclass 31, count 0 2006.257.15:59:59.16#ibcon#about to read 3, iclass 31, count 0 2006.257.15:59:59.18#ibcon#read 3, iclass 31, count 0 2006.257.15:59:59.18#ibcon#about to read 4, iclass 31, count 0 2006.257.15:59:59.18#ibcon#read 4, iclass 31, count 0 2006.257.15:59:59.18#ibcon#about to read 5, iclass 31, count 0 2006.257.15:59:59.18#ibcon#read 5, iclass 31, count 0 2006.257.15:59:59.18#ibcon#about to read 6, iclass 31, count 0 2006.257.15:59:59.18#ibcon#read 6, iclass 31, count 0 2006.257.15:59:59.18#ibcon#end of sib2, iclass 31, count 0 2006.257.15:59:59.18#ibcon#*mode == 0, iclass 31, count 0 2006.257.15:59:59.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.15:59:59.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.15:59:59.18#ibcon#*before write, iclass 31, count 0 2006.257.15:59:59.18#ibcon#enter sib2, iclass 31, count 0 2006.257.15:59:59.18#ibcon#flushed, iclass 31, count 0 2006.257.15:59:59.18#ibcon#about to write, iclass 31, count 0 2006.257.15:59:59.18#ibcon#wrote, iclass 31, count 0 2006.257.15:59:59.18#ibcon#about to read 3, iclass 31, count 0 2006.257.15:59:59.22#ibcon#read 3, iclass 31, count 0 2006.257.15:59:59.22#ibcon#about to read 4, iclass 31, count 0 2006.257.15:59:59.22#ibcon#read 4, iclass 31, count 0 2006.257.15:59:59.22#ibcon#about to read 5, iclass 31, count 0 2006.257.15:59:59.22#ibcon#read 5, iclass 31, count 0 2006.257.15:59:59.22#ibcon#about to read 6, iclass 31, count 0 2006.257.15:59:59.22#ibcon#read 6, iclass 31, count 0 2006.257.15:59:59.22#ibcon#end of sib2, iclass 31, count 0 2006.257.15:59:59.22#ibcon#*after write, iclass 31, count 0 2006.257.15:59:59.22#ibcon#*before return 0, iclass 31, count 0 2006.257.15:59:59.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:59.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.15:59:59.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.15:59:59.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.15:59:59.22$vck44/vb=2,5 2006.257.15:59:59.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.15:59:59.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.15:59:59.22#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:59.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:59.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:59.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:59.28#ibcon#enter wrdev, iclass 33, count 2 2006.257.15:59:59.28#ibcon#first serial, iclass 33, count 2 2006.257.15:59:59.28#ibcon#enter sib2, iclass 33, count 2 2006.257.15:59:59.28#ibcon#flushed, iclass 33, count 2 2006.257.15:59:59.28#ibcon#about to write, iclass 33, count 2 2006.257.15:59:59.28#ibcon#wrote, iclass 33, count 2 2006.257.15:59:59.28#ibcon#about to read 3, iclass 33, count 2 2006.257.15:59:59.30#ibcon#read 3, iclass 33, count 2 2006.257.15:59:59.30#ibcon#about to read 4, iclass 33, count 2 2006.257.15:59:59.30#ibcon#read 4, iclass 33, count 2 2006.257.15:59:59.30#ibcon#about to read 5, iclass 33, count 2 2006.257.15:59:59.30#ibcon#read 5, iclass 33, count 2 2006.257.15:59:59.30#ibcon#about to read 6, iclass 33, count 2 2006.257.15:59:59.30#ibcon#read 6, iclass 33, count 2 2006.257.15:59:59.30#ibcon#end of sib2, iclass 33, count 2 2006.257.15:59:59.30#ibcon#*mode == 0, iclass 33, count 2 2006.257.15:59:59.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.15:59:59.30#ibcon#[27=AT02-05\r\n] 2006.257.15:59:59.30#ibcon#*before write, iclass 33, count 2 2006.257.15:59:59.30#ibcon#enter sib2, iclass 33, count 2 2006.257.15:59:59.30#ibcon#flushed, iclass 33, count 2 2006.257.15:59:59.30#ibcon#about to write, iclass 33, count 2 2006.257.15:59:59.30#ibcon#wrote, iclass 33, count 2 2006.257.15:59:59.30#ibcon#about to read 3, iclass 33, count 2 2006.257.15:59:59.33#ibcon#read 3, iclass 33, count 2 2006.257.15:59:59.33#ibcon#about to read 4, iclass 33, count 2 2006.257.15:59:59.33#ibcon#read 4, iclass 33, count 2 2006.257.15:59:59.33#ibcon#about to read 5, iclass 33, count 2 2006.257.15:59:59.33#ibcon#read 5, iclass 33, count 2 2006.257.15:59:59.33#ibcon#about to read 6, iclass 33, count 2 2006.257.15:59:59.33#ibcon#read 6, iclass 33, count 2 2006.257.15:59:59.33#ibcon#end of sib2, iclass 33, count 2 2006.257.15:59:59.33#ibcon#*after write, iclass 33, count 2 2006.257.15:59:59.33#ibcon#*before return 0, iclass 33, count 2 2006.257.15:59:59.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:59.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.15:59:59.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.15:59:59.33#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:59.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:59.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:59.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:59.45#ibcon#enter wrdev, iclass 33, count 0 2006.257.15:59:59.45#ibcon#first serial, iclass 33, count 0 2006.257.15:59:59.45#ibcon#enter sib2, iclass 33, count 0 2006.257.15:59:59.45#ibcon#flushed, iclass 33, count 0 2006.257.15:59:59.45#ibcon#about to write, iclass 33, count 0 2006.257.15:59:59.45#ibcon#wrote, iclass 33, count 0 2006.257.15:59:59.45#ibcon#about to read 3, iclass 33, count 0 2006.257.15:59:59.47#ibcon#read 3, iclass 33, count 0 2006.257.15:59:59.47#ibcon#about to read 4, iclass 33, count 0 2006.257.15:59:59.47#ibcon#read 4, iclass 33, count 0 2006.257.15:59:59.47#ibcon#about to read 5, iclass 33, count 0 2006.257.15:59:59.47#ibcon#read 5, iclass 33, count 0 2006.257.15:59:59.47#ibcon#about to read 6, iclass 33, count 0 2006.257.15:59:59.47#ibcon#read 6, iclass 33, count 0 2006.257.15:59:59.47#ibcon#end of sib2, iclass 33, count 0 2006.257.15:59:59.47#ibcon#*mode == 0, iclass 33, count 0 2006.257.15:59:59.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.15:59:59.47#ibcon#[27=USB\r\n] 2006.257.15:59:59.47#ibcon#*before write, iclass 33, count 0 2006.257.15:59:59.47#ibcon#enter sib2, iclass 33, count 0 2006.257.15:59:59.47#ibcon#flushed, iclass 33, count 0 2006.257.15:59:59.47#ibcon#about to write, iclass 33, count 0 2006.257.15:59:59.47#ibcon#wrote, iclass 33, count 0 2006.257.15:59:59.47#ibcon#about to read 3, iclass 33, count 0 2006.257.15:59:59.50#ibcon#read 3, iclass 33, count 0 2006.257.15:59:59.50#ibcon#about to read 4, iclass 33, count 0 2006.257.15:59:59.50#ibcon#read 4, iclass 33, count 0 2006.257.15:59:59.50#ibcon#about to read 5, iclass 33, count 0 2006.257.15:59:59.50#ibcon#read 5, iclass 33, count 0 2006.257.15:59:59.50#ibcon#about to read 6, iclass 33, count 0 2006.257.15:59:59.50#ibcon#read 6, iclass 33, count 0 2006.257.15:59:59.50#ibcon#end of sib2, iclass 33, count 0 2006.257.15:59:59.50#ibcon#*after write, iclass 33, count 0 2006.257.15:59:59.50#ibcon#*before return 0, iclass 33, count 0 2006.257.15:59:59.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:59.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.15:59:59.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.15:59:59.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.15:59:59.50$vck44/vblo=3,649.99 2006.257.15:59:59.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.15:59:59.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.15:59:59.50#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:59.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:59.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:59.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:59.50#ibcon#enter wrdev, iclass 35, count 0 2006.257.15:59:59.50#ibcon#first serial, iclass 35, count 0 2006.257.15:59:59.50#ibcon#enter sib2, iclass 35, count 0 2006.257.15:59:59.50#ibcon#flushed, iclass 35, count 0 2006.257.15:59:59.50#ibcon#about to write, iclass 35, count 0 2006.257.15:59:59.50#ibcon#wrote, iclass 35, count 0 2006.257.15:59:59.50#ibcon#about to read 3, iclass 35, count 0 2006.257.15:59:59.52#ibcon#read 3, iclass 35, count 0 2006.257.15:59:59.52#ibcon#about to read 4, iclass 35, count 0 2006.257.15:59:59.52#ibcon#read 4, iclass 35, count 0 2006.257.15:59:59.52#ibcon#about to read 5, iclass 35, count 0 2006.257.15:59:59.52#ibcon#read 5, iclass 35, count 0 2006.257.15:59:59.52#ibcon#about to read 6, iclass 35, count 0 2006.257.15:59:59.52#ibcon#read 6, iclass 35, count 0 2006.257.15:59:59.52#ibcon#end of sib2, iclass 35, count 0 2006.257.15:59:59.52#ibcon#*mode == 0, iclass 35, count 0 2006.257.15:59:59.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.15:59:59.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.15:59:59.52#ibcon#*before write, iclass 35, count 0 2006.257.15:59:59.52#ibcon#enter sib2, iclass 35, count 0 2006.257.15:59:59.52#ibcon#flushed, iclass 35, count 0 2006.257.15:59:59.52#ibcon#about to write, iclass 35, count 0 2006.257.15:59:59.52#ibcon#wrote, iclass 35, count 0 2006.257.15:59:59.52#ibcon#about to read 3, iclass 35, count 0 2006.257.15:59:59.56#ibcon#read 3, iclass 35, count 0 2006.257.15:59:59.56#ibcon#about to read 4, iclass 35, count 0 2006.257.15:59:59.56#ibcon#read 4, iclass 35, count 0 2006.257.15:59:59.56#ibcon#about to read 5, iclass 35, count 0 2006.257.15:59:59.56#ibcon#read 5, iclass 35, count 0 2006.257.15:59:59.56#ibcon#about to read 6, iclass 35, count 0 2006.257.15:59:59.56#ibcon#read 6, iclass 35, count 0 2006.257.15:59:59.56#ibcon#end of sib2, iclass 35, count 0 2006.257.15:59:59.56#ibcon#*after write, iclass 35, count 0 2006.257.15:59:59.56#ibcon#*before return 0, iclass 35, count 0 2006.257.15:59:59.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:59.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.15:59:59.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.15:59:59.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.15:59:59.56$vck44/vb=3,4 2006.257.15:59:59.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.15:59:59.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.15:59:59.56#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:59.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:59.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:59.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:59.62#ibcon#enter wrdev, iclass 37, count 2 2006.257.15:59:59.62#ibcon#first serial, iclass 37, count 2 2006.257.15:59:59.62#ibcon#enter sib2, iclass 37, count 2 2006.257.15:59:59.62#ibcon#flushed, iclass 37, count 2 2006.257.15:59:59.62#ibcon#about to write, iclass 37, count 2 2006.257.15:59:59.62#ibcon#wrote, iclass 37, count 2 2006.257.15:59:59.62#ibcon#about to read 3, iclass 37, count 2 2006.257.15:59:59.64#ibcon#read 3, iclass 37, count 2 2006.257.15:59:59.64#ibcon#about to read 4, iclass 37, count 2 2006.257.15:59:59.64#ibcon#read 4, iclass 37, count 2 2006.257.15:59:59.64#ibcon#about to read 5, iclass 37, count 2 2006.257.15:59:59.64#ibcon#read 5, iclass 37, count 2 2006.257.15:59:59.64#ibcon#about to read 6, iclass 37, count 2 2006.257.15:59:59.64#ibcon#read 6, iclass 37, count 2 2006.257.15:59:59.64#ibcon#end of sib2, iclass 37, count 2 2006.257.15:59:59.64#ibcon#*mode == 0, iclass 37, count 2 2006.257.15:59:59.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.15:59:59.64#ibcon#[27=AT03-04\r\n] 2006.257.15:59:59.64#ibcon#*before write, iclass 37, count 2 2006.257.15:59:59.64#ibcon#enter sib2, iclass 37, count 2 2006.257.15:59:59.64#ibcon#flushed, iclass 37, count 2 2006.257.15:59:59.64#ibcon#about to write, iclass 37, count 2 2006.257.15:59:59.64#ibcon#wrote, iclass 37, count 2 2006.257.15:59:59.64#ibcon#about to read 3, iclass 37, count 2 2006.257.15:59:59.67#ibcon#read 3, iclass 37, count 2 2006.257.15:59:59.67#ibcon#about to read 4, iclass 37, count 2 2006.257.15:59:59.67#ibcon#read 4, iclass 37, count 2 2006.257.15:59:59.67#ibcon#about to read 5, iclass 37, count 2 2006.257.15:59:59.67#ibcon#read 5, iclass 37, count 2 2006.257.15:59:59.67#ibcon#about to read 6, iclass 37, count 2 2006.257.15:59:59.67#ibcon#read 6, iclass 37, count 2 2006.257.15:59:59.67#ibcon#end of sib2, iclass 37, count 2 2006.257.15:59:59.67#ibcon#*after write, iclass 37, count 2 2006.257.15:59:59.67#ibcon#*before return 0, iclass 37, count 2 2006.257.15:59:59.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:59.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.15:59:59.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.15:59:59.67#ibcon#ireg 7 cls_cnt 0 2006.257.15:59:59.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:59.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:59.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:59.79#ibcon#enter wrdev, iclass 37, count 0 2006.257.15:59:59.79#ibcon#first serial, iclass 37, count 0 2006.257.15:59:59.79#ibcon#enter sib2, iclass 37, count 0 2006.257.15:59:59.79#ibcon#flushed, iclass 37, count 0 2006.257.15:59:59.79#ibcon#about to write, iclass 37, count 0 2006.257.15:59:59.79#ibcon#wrote, iclass 37, count 0 2006.257.15:59:59.79#ibcon#about to read 3, iclass 37, count 0 2006.257.15:59:59.81#ibcon#read 3, iclass 37, count 0 2006.257.15:59:59.81#ibcon#about to read 4, iclass 37, count 0 2006.257.15:59:59.81#ibcon#read 4, iclass 37, count 0 2006.257.15:59:59.81#ibcon#about to read 5, iclass 37, count 0 2006.257.15:59:59.81#ibcon#read 5, iclass 37, count 0 2006.257.15:59:59.81#ibcon#about to read 6, iclass 37, count 0 2006.257.15:59:59.81#ibcon#read 6, iclass 37, count 0 2006.257.15:59:59.81#ibcon#end of sib2, iclass 37, count 0 2006.257.15:59:59.81#ibcon#*mode == 0, iclass 37, count 0 2006.257.15:59:59.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.15:59:59.81#ibcon#[27=USB\r\n] 2006.257.15:59:59.81#ibcon#*before write, iclass 37, count 0 2006.257.15:59:59.81#ibcon#enter sib2, iclass 37, count 0 2006.257.15:59:59.81#ibcon#flushed, iclass 37, count 0 2006.257.15:59:59.81#ibcon#about to write, iclass 37, count 0 2006.257.15:59:59.81#ibcon#wrote, iclass 37, count 0 2006.257.15:59:59.81#ibcon#about to read 3, iclass 37, count 0 2006.257.15:59:59.84#ibcon#read 3, iclass 37, count 0 2006.257.15:59:59.84#ibcon#about to read 4, iclass 37, count 0 2006.257.15:59:59.84#ibcon#read 4, iclass 37, count 0 2006.257.15:59:59.84#ibcon#about to read 5, iclass 37, count 0 2006.257.15:59:59.84#ibcon#read 5, iclass 37, count 0 2006.257.15:59:59.84#ibcon#about to read 6, iclass 37, count 0 2006.257.15:59:59.84#ibcon#read 6, iclass 37, count 0 2006.257.15:59:59.84#ibcon#end of sib2, iclass 37, count 0 2006.257.15:59:59.84#ibcon#*after write, iclass 37, count 0 2006.257.15:59:59.84#ibcon#*before return 0, iclass 37, count 0 2006.257.15:59:59.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:59.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.15:59:59.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.15:59:59.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.15:59:59.84$vck44/vblo=4,679.99 2006.257.15:59:59.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.15:59:59.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.15:59:59.84#ibcon#ireg 17 cls_cnt 0 2006.257.15:59:59.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:59.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:59.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:59.84#ibcon#enter wrdev, iclass 39, count 0 2006.257.15:59:59.84#ibcon#first serial, iclass 39, count 0 2006.257.15:59:59.84#ibcon#enter sib2, iclass 39, count 0 2006.257.15:59:59.84#ibcon#flushed, iclass 39, count 0 2006.257.15:59:59.84#ibcon#about to write, iclass 39, count 0 2006.257.15:59:59.84#ibcon#wrote, iclass 39, count 0 2006.257.15:59:59.84#ibcon#about to read 3, iclass 39, count 0 2006.257.15:59:59.86#ibcon#read 3, iclass 39, count 0 2006.257.15:59:59.86#ibcon#about to read 4, iclass 39, count 0 2006.257.15:59:59.86#ibcon#read 4, iclass 39, count 0 2006.257.15:59:59.86#ibcon#about to read 5, iclass 39, count 0 2006.257.15:59:59.86#ibcon#read 5, iclass 39, count 0 2006.257.15:59:59.86#ibcon#about to read 6, iclass 39, count 0 2006.257.15:59:59.86#ibcon#read 6, iclass 39, count 0 2006.257.15:59:59.86#ibcon#end of sib2, iclass 39, count 0 2006.257.15:59:59.86#ibcon#*mode == 0, iclass 39, count 0 2006.257.15:59:59.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.15:59:59.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.15:59:59.86#ibcon#*before write, iclass 39, count 0 2006.257.15:59:59.86#ibcon#enter sib2, iclass 39, count 0 2006.257.15:59:59.86#ibcon#flushed, iclass 39, count 0 2006.257.15:59:59.86#ibcon#about to write, iclass 39, count 0 2006.257.15:59:59.86#ibcon#wrote, iclass 39, count 0 2006.257.15:59:59.86#ibcon#about to read 3, iclass 39, count 0 2006.257.15:59:59.90#ibcon#read 3, iclass 39, count 0 2006.257.15:59:59.90#ibcon#about to read 4, iclass 39, count 0 2006.257.15:59:59.90#ibcon#read 4, iclass 39, count 0 2006.257.15:59:59.90#ibcon#about to read 5, iclass 39, count 0 2006.257.15:59:59.90#ibcon#read 5, iclass 39, count 0 2006.257.15:59:59.90#ibcon#about to read 6, iclass 39, count 0 2006.257.15:59:59.90#ibcon#read 6, iclass 39, count 0 2006.257.15:59:59.90#ibcon#end of sib2, iclass 39, count 0 2006.257.15:59:59.90#ibcon#*after write, iclass 39, count 0 2006.257.15:59:59.90#ibcon#*before return 0, iclass 39, count 0 2006.257.15:59:59.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:59.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.15:59:59.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.15:59:59.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.15:59:59.90$vck44/vb=4,5 2006.257.15:59:59.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.15:59:59.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.15:59:59.90#ibcon#ireg 11 cls_cnt 2 2006.257.15:59:59.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:59:59.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:59:59.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.15:59:59.96#ibcon#enter wrdev, iclass 3, count 2 2006.257.15:59:59.96#ibcon#first serial, iclass 3, count 2 2006.257.15:59:59.96#ibcon#enter sib2, iclass 3, count 2 2006.257.15:59:59.96#ibcon#flushed, iclass 3, count 2 2006.257.15:59:59.96#ibcon#about to write, iclass 3, count 2 2006.257.15:59:59.96#ibcon#wrote, iclass 3, count 2 2006.257.15:59:59.96#ibcon#about to read 3, iclass 3, count 2 2006.257.15:59:59.98#ibcon#read 3, iclass 3, count 2 2006.257.15:59:59.98#ibcon#about to read 4, iclass 3, count 2 2006.257.15:59:59.98#ibcon#read 4, iclass 3, count 2 2006.257.15:59:59.98#ibcon#about to read 5, iclass 3, count 2 2006.257.15:59:59.98#ibcon#read 5, iclass 3, count 2 2006.257.15:59:59.98#ibcon#about to read 6, iclass 3, count 2 2006.257.15:59:59.98#ibcon#read 6, iclass 3, count 2 2006.257.15:59:59.98#ibcon#end of sib2, iclass 3, count 2 2006.257.15:59:59.98#ibcon#*mode == 0, iclass 3, count 2 2006.257.15:59:59.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.15:59:59.98#ibcon#[27=AT04-05\r\n] 2006.257.15:59:59.98#ibcon#*before write, iclass 3, count 2 2006.257.15:59:59.98#ibcon#enter sib2, iclass 3, count 2 2006.257.15:59:59.98#ibcon#flushed, iclass 3, count 2 2006.257.15:59:59.98#ibcon#about to write, iclass 3, count 2 2006.257.15:59:59.98#ibcon#wrote, iclass 3, count 2 2006.257.15:59:59.98#ibcon#about to read 3, iclass 3, count 2 2006.257.16:00:00.01#ibcon#read 3, iclass 3, count 2 2006.257.16:00:00.01#ibcon#about to read 4, iclass 3, count 2 2006.257.16:00:00.01#ibcon#read 4, iclass 3, count 2 2006.257.16:00:00.01#ibcon#about to read 5, iclass 3, count 2 2006.257.16:00:00.01#ibcon#read 5, iclass 3, count 2 2006.257.16:00:00.01#ibcon#about to read 6, iclass 3, count 2 2006.257.16:00:00.01#ibcon#read 6, iclass 3, count 2 2006.257.16:00:00.01#ibcon#end of sib2, iclass 3, count 2 2006.257.16:00:00.01#ibcon#*after write, iclass 3, count 2 2006.257.16:00:00.01#ibcon#*before return 0, iclass 3, count 2 2006.257.16:00:00.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:00:00.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:00:00.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.16:00:00.01#ibcon#ireg 7 cls_cnt 0 2006.257.16:00:00.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:00:00.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:00:00.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:00:00.13#ibcon#enter wrdev, iclass 3, count 0 2006.257.16:00:00.13#ibcon#first serial, iclass 3, count 0 2006.257.16:00:00.13#ibcon#enter sib2, iclass 3, count 0 2006.257.16:00:00.13#ibcon#flushed, iclass 3, count 0 2006.257.16:00:00.13#ibcon#about to write, iclass 3, count 0 2006.257.16:00:00.13#ibcon#wrote, iclass 3, count 0 2006.257.16:00:00.13#ibcon#about to read 3, iclass 3, count 0 2006.257.16:00:00.15#ibcon#read 3, iclass 3, count 0 2006.257.16:00:00.15#ibcon#about to read 4, iclass 3, count 0 2006.257.16:00:00.15#ibcon#read 4, iclass 3, count 0 2006.257.16:00:00.15#ibcon#about to read 5, iclass 3, count 0 2006.257.16:00:00.15#ibcon#read 5, iclass 3, count 0 2006.257.16:00:00.15#ibcon#about to read 6, iclass 3, count 0 2006.257.16:00:00.15#ibcon#read 6, iclass 3, count 0 2006.257.16:00:00.15#ibcon#end of sib2, iclass 3, count 0 2006.257.16:00:00.15#ibcon#*mode == 0, iclass 3, count 0 2006.257.16:00:00.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.16:00:00.15#ibcon#[27=USB\r\n] 2006.257.16:00:00.15#ibcon#*before write, iclass 3, count 0 2006.257.16:00:00.15#ibcon#enter sib2, iclass 3, count 0 2006.257.16:00:00.15#ibcon#flushed, iclass 3, count 0 2006.257.16:00:00.15#ibcon#about to write, iclass 3, count 0 2006.257.16:00:00.15#ibcon#wrote, iclass 3, count 0 2006.257.16:00:00.15#ibcon#about to read 3, iclass 3, count 0 2006.257.16:00:00.18#ibcon#read 3, iclass 3, count 0 2006.257.16:00:00.18#ibcon#about to read 4, iclass 3, count 0 2006.257.16:00:00.18#ibcon#read 4, iclass 3, count 0 2006.257.16:00:00.18#ibcon#about to read 5, iclass 3, count 0 2006.257.16:00:00.18#ibcon#read 5, iclass 3, count 0 2006.257.16:00:00.18#ibcon#about to read 6, iclass 3, count 0 2006.257.16:00:00.18#ibcon#read 6, iclass 3, count 0 2006.257.16:00:00.18#ibcon#end of sib2, iclass 3, count 0 2006.257.16:00:00.18#ibcon#*after write, iclass 3, count 0 2006.257.16:00:00.18#ibcon#*before return 0, iclass 3, count 0 2006.257.16:00:00.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:00:00.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:00:00.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.16:00:00.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.16:00:00.18$vck44/vblo=5,709.99 2006.257.16:00:00.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.16:00:00.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.16:00:00.18#ibcon#ireg 17 cls_cnt 0 2006.257.16:00:00.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:00:00.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:00:00.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:00:00.18#ibcon#enter wrdev, iclass 5, count 0 2006.257.16:00:00.18#ibcon#first serial, iclass 5, count 0 2006.257.16:00:00.18#ibcon#enter sib2, iclass 5, count 0 2006.257.16:00:00.18#ibcon#flushed, iclass 5, count 0 2006.257.16:00:00.18#ibcon#about to write, iclass 5, count 0 2006.257.16:00:00.18#ibcon#wrote, iclass 5, count 0 2006.257.16:00:00.18#ibcon#about to read 3, iclass 5, count 0 2006.257.16:00:00.20#ibcon#read 3, iclass 5, count 0 2006.257.16:00:00.20#ibcon#about to read 4, iclass 5, count 0 2006.257.16:00:00.20#ibcon#read 4, iclass 5, count 0 2006.257.16:00:00.20#ibcon#about to read 5, iclass 5, count 0 2006.257.16:00:00.20#ibcon#read 5, iclass 5, count 0 2006.257.16:00:00.20#ibcon#about to read 6, iclass 5, count 0 2006.257.16:00:00.20#ibcon#read 6, iclass 5, count 0 2006.257.16:00:00.20#ibcon#end of sib2, iclass 5, count 0 2006.257.16:00:00.20#ibcon#*mode == 0, iclass 5, count 0 2006.257.16:00:00.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.16:00:00.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:00:00.20#ibcon#*before write, iclass 5, count 0 2006.257.16:00:00.20#ibcon#enter sib2, iclass 5, count 0 2006.257.16:00:00.20#ibcon#flushed, iclass 5, count 0 2006.257.16:00:00.20#ibcon#about to write, iclass 5, count 0 2006.257.16:00:00.20#ibcon#wrote, iclass 5, count 0 2006.257.16:00:00.20#ibcon#about to read 3, iclass 5, count 0 2006.257.16:00:00.24#ibcon#read 3, iclass 5, count 0 2006.257.16:00:00.24#ibcon#about to read 4, iclass 5, count 0 2006.257.16:00:00.24#ibcon#read 4, iclass 5, count 0 2006.257.16:00:00.24#ibcon#about to read 5, iclass 5, count 0 2006.257.16:00:00.24#ibcon#read 5, iclass 5, count 0 2006.257.16:00:00.24#ibcon#about to read 6, iclass 5, count 0 2006.257.16:00:00.24#ibcon#read 6, iclass 5, count 0 2006.257.16:00:00.24#ibcon#end of sib2, iclass 5, count 0 2006.257.16:00:00.24#ibcon#*after write, iclass 5, count 0 2006.257.16:00:00.24#ibcon#*before return 0, iclass 5, count 0 2006.257.16:00:00.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:00:00.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:00:00.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.16:00:00.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.16:00:00.24$vck44/vb=5,4 2006.257.16:00:00.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.16:00:00.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.16:00:00.24#ibcon#ireg 11 cls_cnt 2 2006.257.16:00:00.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:00:00.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:00:00.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:00:00.30#ibcon#enter wrdev, iclass 7, count 2 2006.257.16:00:00.30#ibcon#first serial, iclass 7, count 2 2006.257.16:00:00.30#ibcon#enter sib2, iclass 7, count 2 2006.257.16:00:00.30#ibcon#flushed, iclass 7, count 2 2006.257.16:00:00.30#ibcon#about to write, iclass 7, count 2 2006.257.16:00:00.30#ibcon#wrote, iclass 7, count 2 2006.257.16:00:00.30#ibcon#about to read 3, iclass 7, count 2 2006.257.16:00:00.32#ibcon#read 3, iclass 7, count 2 2006.257.16:00:00.32#ibcon#about to read 4, iclass 7, count 2 2006.257.16:00:00.32#ibcon#read 4, iclass 7, count 2 2006.257.16:00:00.32#ibcon#about to read 5, iclass 7, count 2 2006.257.16:00:00.32#ibcon#read 5, iclass 7, count 2 2006.257.16:00:00.32#ibcon#about to read 6, iclass 7, count 2 2006.257.16:00:00.32#ibcon#read 6, iclass 7, count 2 2006.257.16:00:00.32#ibcon#end of sib2, iclass 7, count 2 2006.257.16:00:00.32#ibcon#*mode == 0, iclass 7, count 2 2006.257.16:00:00.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.16:00:00.32#ibcon#[27=AT05-04\r\n] 2006.257.16:00:00.32#ibcon#*before write, iclass 7, count 2 2006.257.16:00:00.32#ibcon#enter sib2, iclass 7, count 2 2006.257.16:00:00.32#ibcon#flushed, iclass 7, count 2 2006.257.16:00:00.32#ibcon#about to write, iclass 7, count 2 2006.257.16:00:00.32#ibcon#wrote, iclass 7, count 2 2006.257.16:00:00.32#ibcon#about to read 3, iclass 7, count 2 2006.257.16:00:00.35#ibcon#read 3, iclass 7, count 2 2006.257.16:00:00.35#ibcon#about to read 4, iclass 7, count 2 2006.257.16:00:00.35#ibcon#read 4, iclass 7, count 2 2006.257.16:00:00.35#ibcon#about to read 5, iclass 7, count 2 2006.257.16:00:00.35#ibcon#read 5, iclass 7, count 2 2006.257.16:00:00.35#ibcon#about to read 6, iclass 7, count 2 2006.257.16:00:00.35#ibcon#read 6, iclass 7, count 2 2006.257.16:00:00.35#ibcon#end of sib2, iclass 7, count 2 2006.257.16:00:00.35#ibcon#*after write, iclass 7, count 2 2006.257.16:00:00.35#ibcon#*before return 0, iclass 7, count 2 2006.257.16:00:00.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:00:00.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:00:00.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.16:00:00.35#ibcon#ireg 7 cls_cnt 0 2006.257.16:00:00.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:00:00.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:00:00.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:00:00.47#ibcon#enter wrdev, iclass 7, count 0 2006.257.16:00:00.47#ibcon#first serial, iclass 7, count 0 2006.257.16:00:00.47#ibcon#enter sib2, iclass 7, count 0 2006.257.16:00:00.47#ibcon#flushed, iclass 7, count 0 2006.257.16:00:00.47#ibcon#about to write, iclass 7, count 0 2006.257.16:00:00.47#ibcon#wrote, iclass 7, count 0 2006.257.16:00:00.47#ibcon#about to read 3, iclass 7, count 0 2006.257.16:00:00.49#ibcon#read 3, iclass 7, count 0 2006.257.16:00:00.49#ibcon#about to read 4, iclass 7, count 0 2006.257.16:00:00.49#ibcon#read 4, iclass 7, count 0 2006.257.16:00:00.49#ibcon#about to read 5, iclass 7, count 0 2006.257.16:00:00.49#ibcon#read 5, iclass 7, count 0 2006.257.16:00:00.49#ibcon#about to read 6, iclass 7, count 0 2006.257.16:00:00.49#ibcon#read 6, iclass 7, count 0 2006.257.16:00:00.49#ibcon#end of sib2, iclass 7, count 0 2006.257.16:00:00.49#ibcon#*mode == 0, iclass 7, count 0 2006.257.16:00:00.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.16:00:00.49#ibcon#[27=USB\r\n] 2006.257.16:00:00.49#ibcon#*before write, iclass 7, count 0 2006.257.16:00:00.49#ibcon#enter sib2, iclass 7, count 0 2006.257.16:00:00.49#ibcon#flushed, iclass 7, count 0 2006.257.16:00:00.49#ibcon#about to write, iclass 7, count 0 2006.257.16:00:00.49#ibcon#wrote, iclass 7, count 0 2006.257.16:00:00.49#ibcon#about to read 3, iclass 7, count 0 2006.257.16:00:00.52#ibcon#read 3, iclass 7, count 0 2006.257.16:00:00.52#ibcon#about to read 4, iclass 7, count 0 2006.257.16:00:00.52#ibcon#read 4, iclass 7, count 0 2006.257.16:00:00.52#ibcon#about to read 5, iclass 7, count 0 2006.257.16:00:00.52#ibcon#read 5, iclass 7, count 0 2006.257.16:00:00.52#ibcon#about to read 6, iclass 7, count 0 2006.257.16:00:00.52#ibcon#read 6, iclass 7, count 0 2006.257.16:00:00.52#ibcon#end of sib2, iclass 7, count 0 2006.257.16:00:00.52#ibcon#*after write, iclass 7, count 0 2006.257.16:00:00.52#ibcon#*before return 0, iclass 7, count 0 2006.257.16:00:00.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:00:00.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:00:00.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.16:00:00.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.16:00:00.52$vck44/vblo=6,719.99 2006.257.16:00:00.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.16:00:00.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.16:00:00.52#ibcon#ireg 17 cls_cnt 0 2006.257.16:00:00.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:00:00.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:00:00.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:00:00.52#ibcon#enter wrdev, iclass 11, count 0 2006.257.16:00:00.52#ibcon#first serial, iclass 11, count 0 2006.257.16:00:00.52#ibcon#enter sib2, iclass 11, count 0 2006.257.16:00:00.52#ibcon#flushed, iclass 11, count 0 2006.257.16:00:00.52#ibcon#about to write, iclass 11, count 0 2006.257.16:00:00.52#ibcon#wrote, iclass 11, count 0 2006.257.16:00:00.52#ibcon#about to read 3, iclass 11, count 0 2006.257.16:00:00.54#ibcon#read 3, iclass 11, count 0 2006.257.16:00:00.54#ibcon#about to read 4, iclass 11, count 0 2006.257.16:00:00.54#ibcon#read 4, iclass 11, count 0 2006.257.16:00:00.54#ibcon#about to read 5, iclass 11, count 0 2006.257.16:00:00.54#ibcon#read 5, iclass 11, count 0 2006.257.16:00:00.54#ibcon#about to read 6, iclass 11, count 0 2006.257.16:00:00.54#ibcon#read 6, iclass 11, count 0 2006.257.16:00:00.54#ibcon#end of sib2, iclass 11, count 0 2006.257.16:00:00.54#ibcon#*mode == 0, iclass 11, count 0 2006.257.16:00:00.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.16:00:00.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:00:00.54#ibcon#*before write, iclass 11, count 0 2006.257.16:00:00.54#ibcon#enter sib2, iclass 11, count 0 2006.257.16:00:00.54#ibcon#flushed, iclass 11, count 0 2006.257.16:00:00.54#ibcon#about to write, iclass 11, count 0 2006.257.16:00:00.54#ibcon#wrote, iclass 11, count 0 2006.257.16:00:00.54#ibcon#about to read 3, iclass 11, count 0 2006.257.16:00:00.58#ibcon#read 3, iclass 11, count 0 2006.257.16:00:00.58#ibcon#about to read 4, iclass 11, count 0 2006.257.16:00:00.58#ibcon#read 4, iclass 11, count 0 2006.257.16:00:00.58#ibcon#about to read 5, iclass 11, count 0 2006.257.16:00:00.58#ibcon#read 5, iclass 11, count 0 2006.257.16:00:00.58#ibcon#about to read 6, iclass 11, count 0 2006.257.16:00:00.58#ibcon#read 6, iclass 11, count 0 2006.257.16:00:00.58#ibcon#end of sib2, iclass 11, count 0 2006.257.16:00:00.58#ibcon#*after write, iclass 11, count 0 2006.257.16:00:00.58#ibcon#*before return 0, iclass 11, count 0 2006.257.16:00:00.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:00:00.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:00:00.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.16:00:00.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.16:00:00.58$vck44/vb=6,4 2006.257.16:00:00.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.16:00:00.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.16:00:00.58#ibcon#ireg 11 cls_cnt 2 2006.257.16:00:00.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:00:00.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:00:00.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:00:00.64#ibcon#enter wrdev, iclass 13, count 2 2006.257.16:00:00.64#ibcon#first serial, iclass 13, count 2 2006.257.16:00:00.64#ibcon#enter sib2, iclass 13, count 2 2006.257.16:00:00.64#ibcon#flushed, iclass 13, count 2 2006.257.16:00:00.64#ibcon#about to write, iclass 13, count 2 2006.257.16:00:00.64#ibcon#wrote, iclass 13, count 2 2006.257.16:00:00.64#ibcon#about to read 3, iclass 13, count 2 2006.257.16:00:00.66#ibcon#read 3, iclass 13, count 2 2006.257.16:00:00.66#ibcon#about to read 4, iclass 13, count 2 2006.257.16:00:00.66#ibcon#read 4, iclass 13, count 2 2006.257.16:00:00.66#ibcon#about to read 5, iclass 13, count 2 2006.257.16:00:00.66#ibcon#read 5, iclass 13, count 2 2006.257.16:00:00.66#ibcon#about to read 6, iclass 13, count 2 2006.257.16:00:00.66#ibcon#read 6, iclass 13, count 2 2006.257.16:00:00.66#ibcon#end of sib2, iclass 13, count 2 2006.257.16:00:00.66#ibcon#*mode == 0, iclass 13, count 2 2006.257.16:00:00.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.16:00:00.66#ibcon#[27=AT06-04\r\n] 2006.257.16:00:00.66#ibcon#*before write, iclass 13, count 2 2006.257.16:00:00.66#ibcon#enter sib2, iclass 13, count 2 2006.257.16:00:00.66#ibcon#flushed, iclass 13, count 2 2006.257.16:00:00.66#ibcon#about to write, iclass 13, count 2 2006.257.16:00:00.66#ibcon#wrote, iclass 13, count 2 2006.257.16:00:00.66#ibcon#about to read 3, iclass 13, count 2 2006.257.16:00:00.69#ibcon#read 3, iclass 13, count 2 2006.257.16:00:00.69#ibcon#about to read 4, iclass 13, count 2 2006.257.16:00:00.69#ibcon#read 4, iclass 13, count 2 2006.257.16:00:00.69#ibcon#about to read 5, iclass 13, count 2 2006.257.16:00:00.69#ibcon#read 5, iclass 13, count 2 2006.257.16:00:00.69#ibcon#about to read 6, iclass 13, count 2 2006.257.16:00:00.69#ibcon#read 6, iclass 13, count 2 2006.257.16:00:00.69#ibcon#end of sib2, iclass 13, count 2 2006.257.16:00:00.69#ibcon#*after write, iclass 13, count 2 2006.257.16:00:00.69#ibcon#*before return 0, iclass 13, count 2 2006.257.16:00:00.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:00:00.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:00:00.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.16:00:00.69#ibcon#ireg 7 cls_cnt 0 2006.257.16:00:00.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:00:00.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:00:00.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:00:00.81#ibcon#enter wrdev, iclass 13, count 0 2006.257.16:00:00.81#ibcon#first serial, iclass 13, count 0 2006.257.16:00:00.81#ibcon#enter sib2, iclass 13, count 0 2006.257.16:00:00.81#ibcon#flushed, iclass 13, count 0 2006.257.16:00:00.81#ibcon#about to write, iclass 13, count 0 2006.257.16:00:00.81#ibcon#wrote, iclass 13, count 0 2006.257.16:00:00.81#ibcon#about to read 3, iclass 13, count 0 2006.257.16:00:00.83#ibcon#read 3, iclass 13, count 0 2006.257.16:00:00.83#ibcon#about to read 4, iclass 13, count 0 2006.257.16:00:00.83#ibcon#read 4, iclass 13, count 0 2006.257.16:00:00.83#ibcon#about to read 5, iclass 13, count 0 2006.257.16:00:00.83#ibcon#read 5, iclass 13, count 0 2006.257.16:00:00.83#ibcon#about to read 6, iclass 13, count 0 2006.257.16:00:00.83#ibcon#read 6, iclass 13, count 0 2006.257.16:00:00.83#ibcon#end of sib2, iclass 13, count 0 2006.257.16:00:00.83#ibcon#*mode == 0, iclass 13, count 0 2006.257.16:00:00.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.16:00:00.83#ibcon#[27=USB\r\n] 2006.257.16:00:00.83#ibcon#*before write, iclass 13, count 0 2006.257.16:00:00.83#ibcon#enter sib2, iclass 13, count 0 2006.257.16:00:00.83#ibcon#flushed, iclass 13, count 0 2006.257.16:00:00.83#ibcon#about to write, iclass 13, count 0 2006.257.16:00:00.83#ibcon#wrote, iclass 13, count 0 2006.257.16:00:00.83#ibcon#about to read 3, iclass 13, count 0 2006.257.16:00:00.86#ibcon#read 3, iclass 13, count 0 2006.257.16:00:00.86#ibcon#about to read 4, iclass 13, count 0 2006.257.16:00:00.86#ibcon#read 4, iclass 13, count 0 2006.257.16:00:00.86#ibcon#about to read 5, iclass 13, count 0 2006.257.16:00:00.86#ibcon#read 5, iclass 13, count 0 2006.257.16:00:00.86#ibcon#about to read 6, iclass 13, count 0 2006.257.16:00:00.86#ibcon#read 6, iclass 13, count 0 2006.257.16:00:00.86#ibcon#end of sib2, iclass 13, count 0 2006.257.16:00:00.86#ibcon#*after write, iclass 13, count 0 2006.257.16:00:00.86#ibcon#*before return 0, iclass 13, count 0 2006.257.16:00:00.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:00:00.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:00:00.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.16:00:00.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.16:00:00.86$vck44/vblo=7,734.99 2006.257.16:00:00.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.16:00:00.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.16:00:00.86#ibcon#ireg 17 cls_cnt 0 2006.257.16:00:00.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:00:00.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:00:00.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:00:00.86#ibcon#enter wrdev, iclass 15, count 0 2006.257.16:00:00.86#ibcon#first serial, iclass 15, count 0 2006.257.16:00:00.86#ibcon#enter sib2, iclass 15, count 0 2006.257.16:00:00.86#ibcon#flushed, iclass 15, count 0 2006.257.16:00:00.86#ibcon#about to write, iclass 15, count 0 2006.257.16:00:00.86#ibcon#wrote, iclass 15, count 0 2006.257.16:00:00.86#ibcon#about to read 3, iclass 15, count 0 2006.257.16:00:00.88#ibcon#read 3, iclass 15, count 0 2006.257.16:00:00.88#ibcon#about to read 4, iclass 15, count 0 2006.257.16:00:00.88#ibcon#read 4, iclass 15, count 0 2006.257.16:00:00.88#ibcon#about to read 5, iclass 15, count 0 2006.257.16:00:00.88#ibcon#read 5, iclass 15, count 0 2006.257.16:00:00.88#ibcon#about to read 6, iclass 15, count 0 2006.257.16:00:00.88#ibcon#read 6, iclass 15, count 0 2006.257.16:00:00.88#ibcon#end of sib2, iclass 15, count 0 2006.257.16:00:00.88#ibcon#*mode == 0, iclass 15, count 0 2006.257.16:00:00.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.16:00:00.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:00:00.88#ibcon#*before write, iclass 15, count 0 2006.257.16:00:00.88#ibcon#enter sib2, iclass 15, count 0 2006.257.16:00:00.88#ibcon#flushed, iclass 15, count 0 2006.257.16:00:00.88#ibcon#about to write, iclass 15, count 0 2006.257.16:00:00.88#ibcon#wrote, iclass 15, count 0 2006.257.16:00:00.88#ibcon#about to read 3, iclass 15, count 0 2006.257.16:00:00.92#ibcon#read 3, iclass 15, count 0 2006.257.16:00:00.92#ibcon#about to read 4, iclass 15, count 0 2006.257.16:00:00.92#ibcon#read 4, iclass 15, count 0 2006.257.16:00:00.92#ibcon#about to read 5, iclass 15, count 0 2006.257.16:00:00.92#ibcon#read 5, iclass 15, count 0 2006.257.16:00:00.92#ibcon#about to read 6, iclass 15, count 0 2006.257.16:00:00.92#ibcon#read 6, iclass 15, count 0 2006.257.16:00:00.92#ibcon#end of sib2, iclass 15, count 0 2006.257.16:00:00.92#ibcon#*after write, iclass 15, count 0 2006.257.16:00:00.92#ibcon#*before return 0, iclass 15, count 0 2006.257.16:00:00.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:00:00.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:00:00.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.16:00:00.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.16:00:00.92$vck44/vb=7,4 2006.257.16:00:00.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.16:00:00.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.16:00:00.92#ibcon#ireg 11 cls_cnt 2 2006.257.16:00:00.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:00:00.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:00:00.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:00:00.98#ibcon#enter wrdev, iclass 17, count 2 2006.257.16:00:00.98#ibcon#first serial, iclass 17, count 2 2006.257.16:00:00.98#ibcon#enter sib2, iclass 17, count 2 2006.257.16:00:00.98#ibcon#flushed, iclass 17, count 2 2006.257.16:00:00.98#ibcon#about to write, iclass 17, count 2 2006.257.16:00:00.98#ibcon#wrote, iclass 17, count 2 2006.257.16:00:00.98#ibcon#about to read 3, iclass 17, count 2 2006.257.16:00:01.00#ibcon#read 3, iclass 17, count 2 2006.257.16:00:01.00#ibcon#about to read 4, iclass 17, count 2 2006.257.16:00:01.00#ibcon#read 4, iclass 17, count 2 2006.257.16:00:01.00#ibcon#about to read 5, iclass 17, count 2 2006.257.16:00:01.00#ibcon#read 5, iclass 17, count 2 2006.257.16:00:01.00#ibcon#about to read 6, iclass 17, count 2 2006.257.16:00:01.00#ibcon#read 6, iclass 17, count 2 2006.257.16:00:01.00#ibcon#end of sib2, iclass 17, count 2 2006.257.16:00:01.00#ibcon#*mode == 0, iclass 17, count 2 2006.257.16:00:01.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.16:00:01.00#ibcon#[27=AT07-04\r\n] 2006.257.16:00:01.00#ibcon#*before write, iclass 17, count 2 2006.257.16:00:01.00#ibcon#enter sib2, iclass 17, count 2 2006.257.16:00:01.00#ibcon#flushed, iclass 17, count 2 2006.257.16:00:01.00#ibcon#about to write, iclass 17, count 2 2006.257.16:00:01.00#ibcon#wrote, iclass 17, count 2 2006.257.16:00:01.00#ibcon#about to read 3, iclass 17, count 2 2006.257.16:00:01.03#ibcon#read 3, iclass 17, count 2 2006.257.16:00:01.03#ibcon#about to read 4, iclass 17, count 2 2006.257.16:00:01.03#ibcon#read 4, iclass 17, count 2 2006.257.16:00:01.03#ibcon#about to read 5, iclass 17, count 2 2006.257.16:00:01.03#ibcon#read 5, iclass 17, count 2 2006.257.16:00:01.03#ibcon#about to read 6, iclass 17, count 2 2006.257.16:00:01.03#ibcon#read 6, iclass 17, count 2 2006.257.16:00:01.03#ibcon#end of sib2, iclass 17, count 2 2006.257.16:00:01.03#ibcon#*after write, iclass 17, count 2 2006.257.16:00:01.03#ibcon#*before return 0, iclass 17, count 2 2006.257.16:00:01.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:00:01.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:00:01.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.16:00:01.03#ibcon#ireg 7 cls_cnt 0 2006.257.16:00:01.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:00:01.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:00:01.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:00:01.15#ibcon#enter wrdev, iclass 17, count 0 2006.257.16:00:01.15#ibcon#first serial, iclass 17, count 0 2006.257.16:00:01.15#ibcon#enter sib2, iclass 17, count 0 2006.257.16:00:01.15#ibcon#flushed, iclass 17, count 0 2006.257.16:00:01.15#ibcon#about to write, iclass 17, count 0 2006.257.16:00:01.15#ibcon#wrote, iclass 17, count 0 2006.257.16:00:01.15#ibcon#about to read 3, iclass 17, count 0 2006.257.16:00:01.17#ibcon#read 3, iclass 17, count 0 2006.257.16:00:01.17#ibcon#about to read 4, iclass 17, count 0 2006.257.16:00:01.17#ibcon#read 4, iclass 17, count 0 2006.257.16:00:01.17#ibcon#about to read 5, iclass 17, count 0 2006.257.16:00:01.17#ibcon#read 5, iclass 17, count 0 2006.257.16:00:01.17#ibcon#about to read 6, iclass 17, count 0 2006.257.16:00:01.17#ibcon#read 6, iclass 17, count 0 2006.257.16:00:01.17#ibcon#end of sib2, iclass 17, count 0 2006.257.16:00:01.17#ibcon#*mode == 0, iclass 17, count 0 2006.257.16:00:01.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.16:00:01.17#ibcon#[27=USB\r\n] 2006.257.16:00:01.17#ibcon#*before write, iclass 17, count 0 2006.257.16:00:01.17#ibcon#enter sib2, iclass 17, count 0 2006.257.16:00:01.17#ibcon#flushed, iclass 17, count 0 2006.257.16:00:01.17#ibcon#about to write, iclass 17, count 0 2006.257.16:00:01.17#ibcon#wrote, iclass 17, count 0 2006.257.16:00:01.17#ibcon#about to read 3, iclass 17, count 0 2006.257.16:00:01.20#ibcon#read 3, iclass 17, count 0 2006.257.16:00:01.20#ibcon#about to read 4, iclass 17, count 0 2006.257.16:00:01.20#ibcon#read 4, iclass 17, count 0 2006.257.16:00:01.20#ibcon#about to read 5, iclass 17, count 0 2006.257.16:00:01.20#ibcon#read 5, iclass 17, count 0 2006.257.16:00:01.20#ibcon#about to read 6, iclass 17, count 0 2006.257.16:00:01.20#ibcon#read 6, iclass 17, count 0 2006.257.16:00:01.20#ibcon#end of sib2, iclass 17, count 0 2006.257.16:00:01.20#ibcon#*after write, iclass 17, count 0 2006.257.16:00:01.20#ibcon#*before return 0, iclass 17, count 0 2006.257.16:00:01.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:00:01.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:00:01.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.16:00:01.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.16:00:01.20$vck44/vblo=8,744.99 2006.257.16:00:01.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.16:00:01.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.16:00:01.20#ibcon#ireg 17 cls_cnt 0 2006.257.16:00:01.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:00:01.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:00:01.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:00:01.20#ibcon#enter wrdev, iclass 19, count 0 2006.257.16:00:01.20#ibcon#first serial, iclass 19, count 0 2006.257.16:00:01.20#ibcon#enter sib2, iclass 19, count 0 2006.257.16:00:01.20#ibcon#flushed, iclass 19, count 0 2006.257.16:00:01.20#ibcon#about to write, iclass 19, count 0 2006.257.16:00:01.20#ibcon#wrote, iclass 19, count 0 2006.257.16:00:01.20#ibcon#about to read 3, iclass 19, count 0 2006.257.16:00:01.22#ibcon#read 3, iclass 19, count 0 2006.257.16:00:01.22#ibcon#about to read 4, iclass 19, count 0 2006.257.16:00:01.22#ibcon#read 4, iclass 19, count 0 2006.257.16:00:01.22#ibcon#about to read 5, iclass 19, count 0 2006.257.16:00:01.22#ibcon#read 5, iclass 19, count 0 2006.257.16:00:01.22#ibcon#about to read 6, iclass 19, count 0 2006.257.16:00:01.22#ibcon#read 6, iclass 19, count 0 2006.257.16:00:01.22#ibcon#end of sib2, iclass 19, count 0 2006.257.16:00:01.22#ibcon#*mode == 0, iclass 19, count 0 2006.257.16:00:01.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.16:00:01.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:00:01.22#ibcon#*before write, iclass 19, count 0 2006.257.16:00:01.22#ibcon#enter sib2, iclass 19, count 0 2006.257.16:00:01.22#ibcon#flushed, iclass 19, count 0 2006.257.16:00:01.22#ibcon#about to write, iclass 19, count 0 2006.257.16:00:01.22#ibcon#wrote, iclass 19, count 0 2006.257.16:00:01.22#ibcon#about to read 3, iclass 19, count 0 2006.257.16:00:01.26#ibcon#read 3, iclass 19, count 0 2006.257.16:00:01.26#ibcon#about to read 4, iclass 19, count 0 2006.257.16:00:01.26#ibcon#read 4, iclass 19, count 0 2006.257.16:00:01.26#ibcon#about to read 5, iclass 19, count 0 2006.257.16:00:01.26#ibcon#read 5, iclass 19, count 0 2006.257.16:00:01.26#ibcon#about to read 6, iclass 19, count 0 2006.257.16:00:01.26#ibcon#read 6, iclass 19, count 0 2006.257.16:00:01.26#ibcon#end of sib2, iclass 19, count 0 2006.257.16:00:01.26#ibcon#*after write, iclass 19, count 0 2006.257.16:00:01.26#ibcon#*before return 0, iclass 19, count 0 2006.257.16:00:01.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:00:01.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:00:01.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.16:00:01.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.16:00:01.26$vck44/vb=8,4 2006.257.16:00:01.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.16:00:01.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.16:00:01.26#ibcon#ireg 11 cls_cnt 2 2006.257.16:00:01.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:00:01.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:00:01.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:00:01.32#ibcon#enter wrdev, iclass 21, count 2 2006.257.16:00:01.32#ibcon#first serial, iclass 21, count 2 2006.257.16:00:01.32#ibcon#enter sib2, iclass 21, count 2 2006.257.16:00:01.32#ibcon#flushed, iclass 21, count 2 2006.257.16:00:01.32#ibcon#about to write, iclass 21, count 2 2006.257.16:00:01.32#ibcon#wrote, iclass 21, count 2 2006.257.16:00:01.32#ibcon#about to read 3, iclass 21, count 2 2006.257.16:00:01.34#ibcon#read 3, iclass 21, count 2 2006.257.16:00:01.34#ibcon#about to read 4, iclass 21, count 2 2006.257.16:00:01.34#ibcon#read 4, iclass 21, count 2 2006.257.16:00:01.34#ibcon#about to read 5, iclass 21, count 2 2006.257.16:00:01.34#ibcon#read 5, iclass 21, count 2 2006.257.16:00:01.34#ibcon#about to read 6, iclass 21, count 2 2006.257.16:00:01.34#ibcon#read 6, iclass 21, count 2 2006.257.16:00:01.34#ibcon#end of sib2, iclass 21, count 2 2006.257.16:00:01.34#ibcon#*mode == 0, iclass 21, count 2 2006.257.16:00:01.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.16:00:01.34#ibcon#[27=AT08-04\r\n] 2006.257.16:00:01.34#ibcon#*before write, iclass 21, count 2 2006.257.16:00:01.34#ibcon#enter sib2, iclass 21, count 2 2006.257.16:00:01.34#ibcon#flushed, iclass 21, count 2 2006.257.16:00:01.34#ibcon#about to write, iclass 21, count 2 2006.257.16:00:01.34#ibcon#wrote, iclass 21, count 2 2006.257.16:00:01.34#ibcon#about to read 3, iclass 21, count 2 2006.257.16:00:01.37#ibcon#read 3, iclass 21, count 2 2006.257.16:00:01.37#ibcon#about to read 4, iclass 21, count 2 2006.257.16:00:01.37#ibcon#read 4, iclass 21, count 2 2006.257.16:00:01.37#ibcon#about to read 5, iclass 21, count 2 2006.257.16:00:01.37#ibcon#read 5, iclass 21, count 2 2006.257.16:00:01.37#ibcon#about to read 6, iclass 21, count 2 2006.257.16:00:01.37#ibcon#read 6, iclass 21, count 2 2006.257.16:00:01.37#ibcon#end of sib2, iclass 21, count 2 2006.257.16:00:01.37#ibcon#*after write, iclass 21, count 2 2006.257.16:00:01.37#ibcon#*before return 0, iclass 21, count 2 2006.257.16:00:01.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:00:01.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:00:01.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.16:00:01.37#ibcon#ireg 7 cls_cnt 0 2006.257.16:00:01.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:00:01.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:00:01.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:00:01.49#ibcon#enter wrdev, iclass 21, count 0 2006.257.16:00:01.49#ibcon#first serial, iclass 21, count 0 2006.257.16:00:01.49#ibcon#enter sib2, iclass 21, count 0 2006.257.16:00:01.49#ibcon#flushed, iclass 21, count 0 2006.257.16:00:01.49#ibcon#about to write, iclass 21, count 0 2006.257.16:00:01.49#ibcon#wrote, iclass 21, count 0 2006.257.16:00:01.49#ibcon#about to read 3, iclass 21, count 0 2006.257.16:00:01.51#ibcon#read 3, iclass 21, count 0 2006.257.16:00:01.51#ibcon#about to read 4, iclass 21, count 0 2006.257.16:00:01.51#ibcon#read 4, iclass 21, count 0 2006.257.16:00:01.51#ibcon#about to read 5, iclass 21, count 0 2006.257.16:00:01.51#ibcon#read 5, iclass 21, count 0 2006.257.16:00:01.51#ibcon#about to read 6, iclass 21, count 0 2006.257.16:00:01.51#ibcon#read 6, iclass 21, count 0 2006.257.16:00:01.51#ibcon#end of sib2, iclass 21, count 0 2006.257.16:00:01.51#ibcon#*mode == 0, iclass 21, count 0 2006.257.16:00:01.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.16:00:01.51#ibcon#[27=USB\r\n] 2006.257.16:00:01.51#ibcon#*before write, iclass 21, count 0 2006.257.16:00:01.51#ibcon#enter sib2, iclass 21, count 0 2006.257.16:00:01.51#ibcon#flushed, iclass 21, count 0 2006.257.16:00:01.51#ibcon#about to write, iclass 21, count 0 2006.257.16:00:01.51#ibcon#wrote, iclass 21, count 0 2006.257.16:00:01.51#ibcon#about to read 3, iclass 21, count 0 2006.257.16:00:01.54#ibcon#read 3, iclass 21, count 0 2006.257.16:00:01.54#ibcon#about to read 4, iclass 21, count 0 2006.257.16:00:01.54#ibcon#read 4, iclass 21, count 0 2006.257.16:00:01.54#ibcon#about to read 5, iclass 21, count 0 2006.257.16:00:01.54#ibcon#read 5, iclass 21, count 0 2006.257.16:00:01.54#ibcon#about to read 6, iclass 21, count 0 2006.257.16:00:01.54#ibcon#read 6, iclass 21, count 0 2006.257.16:00:01.54#ibcon#end of sib2, iclass 21, count 0 2006.257.16:00:01.54#ibcon#*after write, iclass 21, count 0 2006.257.16:00:01.54#ibcon#*before return 0, iclass 21, count 0 2006.257.16:00:01.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:00:01.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:00:01.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.16:00:01.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.16:00:01.54$vck44/vabw=wide 2006.257.16:00:01.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.16:00:01.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.16:00:01.54#ibcon#ireg 8 cls_cnt 0 2006.257.16:00:01.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:00:01.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:00:01.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:00:01.54#ibcon#enter wrdev, iclass 23, count 0 2006.257.16:00:01.54#ibcon#first serial, iclass 23, count 0 2006.257.16:00:01.54#ibcon#enter sib2, iclass 23, count 0 2006.257.16:00:01.54#ibcon#flushed, iclass 23, count 0 2006.257.16:00:01.54#ibcon#about to write, iclass 23, count 0 2006.257.16:00:01.54#ibcon#wrote, iclass 23, count 0 2006.257.16:00:01.54#ibcon#about to read 3, iclass 23, count 0 2006.257.16:00:01.56#ibcon#read 3, iclass 23, count 0 2006.257.16:00:01.56#ibcon#about to read 4, iclass 23, count 0 2006.257.16:00:01.56#ibcon#read 4, iclass 23, count 0 2006.257.16:00:01.56#ibcon#about to read 5, iclass 23, count 0 2006.257.16:00:01.56#ibcon#read 5, iclass 23, count 0 2006.257.16:00:01.56#ibcon#about to read 6, iclass 23, count 0 2006.257.16:00:01.56#ibcon#read 6, iclass 23, count 0 2006.257.16:00:01.56#ibcon#end of sib2, iclass 23, count 0 2006.257.16:00:01.56#ibcon#*mode == 0, iclass 23, count 0 2006.257.16:00:01.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.16:00:01.56#ibcon#[25=BW32\r\n] 2006.257.16:00:01.56#ibcon#*before write, iclass 23, count 0 2006.257.16:00:01.56#ibcon#enter sib2, iclass 23, count 0 2006.257.16:00:01.56#ibcon#flushed, iclass 23, count 0 2006.257.16:00:01.56#ibcon#about to write, iclass 23, count 0 2006.257.16:00:01.56#ibcon#wrote, iclass 23, count 0 2006.257.16:00:01.56#ibcon#about to read 3, iclass 23, count 0 2006.257.16:00:01.59#ibcon#read 3, iclass 23, count 0 2006.257.16:00:01.59#ibcon#about to read 4, iclass 23, count 0 2006.257.16:00:01.59#ibcon#read 4, iclass 23, count 0 2006.257.16:00:01.59#ibcon#about to read 5, iclass 23, count 0 2006.257.16:00:01.59#ibcon#read 5, iclass 23, count 0 2006.257.16:00:01.59#ibcon#about to read 6, iclass 23, count 0 2006.257.16:00:01.59#ibcon#read 6, iclass 23, count 0 2006.257.16:00:01.59#ibcon#end of sib2, iclass 23, count 0 2006.257.16:00:01.59#ibcon#*after write, iclass 23, count 0 2006.257.16:00:01.59#ibcon#*before return 0, iclass 23, count 0 2006.257.16:00:01.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:00:01.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:00:01.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.16:00:01.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.16:00:01.59$vck44/vbbw=wide 2006.257.16:00:01.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.16:00:01.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.16:00:01.59#ibcon#ireg 8 cls_cnt 0 2006.257.16:00:01.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:00:01.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:00:01.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:00:01.66#ibcon#enter wrdev, iclass 25, count 0 2006.257.16:00:01.66#ibcon#first serial, iclass 25, count 0 2006.257.16:00:01.66#ibcon#enter sib2, iclass 25, count 0 2006.257.16:00:01.66#ibcon#flushed, iclass 25, count 0 2006.257.16:00:01.66#ibcon#about to write, iclass 25, count 0 2006.257.16:00:01.66#ibcon#wrote, iclass 25, count 0 2006.257.16:00:01.66#ibcon#about to read 3, iclass 25, count 0 2006.257.16:00:01.68#ibcon#read 3, iclass 25, count 0 2006.257.16:00:01.68#ibcon#about to read 4, iclass 25, count 0 2006.257.16:00:01.68#ibcon#read 4, iclass 25, count 0 2006.257.16:00:01.68#ibcon#about to read 5, iclass 25, count 0 2006.257.16:00:01.68#ibcon#read 5, iclass 25, count 0 2006.257.16:00:01.68#ibcon#about to read 6, iclass 25, count 0 2006.257.16:00:01.68#ibcon#read 6, iclass 25, count 0 2006.257.16:00:01.68#ibcon#end of sib2, iclass 25, count 0 2006.257.16:00:01.68#ibcon#*mode == 0, iclass 25, count 0 2006.257.16:00:01.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.16:00:01.68#ibcon#[27=BW32\r\n] 2006.257.16:00:01.68#ibcon#*before write, iclass 25, count 0 2006.257.16:00:01.68#ibcon#enter sib2, iclass 25, count 0 2006.257.16:00:01.68#ibcon#flushed, iclass 25, count 0 2006.257.16:00:01.68#ibcon#about to write, iclass 25, count 0 2006.257.16:00:01.68#ibcon#wrote, iclass 25, count 0 2006.257.16:00:01.68#ibcon#about to read 3, iclass 25, count 0 2006.257.16:00:01.71#ibcon#read 3, iclass 25, count 0 2006.257.16:00:01.71#ibcon#about to read 4, iclass 25, count 0 2006.257.16:00:01.71#ibcon#read 4, iclass 25, count 0 2006.257.16:00:01.71#ibcon#about to read 5, iclass 25, count 0 2006.257.16:00:01.71#ibcon#read 5, iclass 25, count 0 2006.257.16:00:01.71#ibcon#about to read 6, iclass 25, count 0 2006.257.16:00:01.71#ibcon#read 6, iclass 25, count 0 2006.257.16:00:01.71#ibcon#end of sib2, iclass 25, count 0 2006.257.16:00:01.71#ibcon#*after write, iclass 25, count 0 2006.257.16:00:01.71#ibcon#*before return 0, iclass 25, count 0 2006.257.16:00:01.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:00:01.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:00:01.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.16:00:01.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.16:00:01.71$setupk4/ifdk4 2006.257.16:00:01.71$ifdk4/lo= 2006.257.16:00:01.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:00:01.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:00:01.71$ifdk4/patch= 2006.257.16:00:01.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:00:01.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:00:01.71$setupk4/!*+20s 2006.257.16:00:04.09#abcon#<5=/13 1.4 4.2 17.32 971014.0\r\n> 2006.257.16:00:04.11#abcon#{5=INTERFACE CLEAR} 2006.257.16:00:04.17#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:00:09.14#trakl#Source acquired 2006.257.16:00:10.14#flagr#flagr/antenna,acquired 2006.257.16:00:14.26#abcon#<5=/13 1.4 4.2 17.31 971014.0\r\n> 2006.257.16:00:14.28#abcon#{5=INTERFACE CLEAR} 2006.257.16:00:14.34#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:00:16.22$setupk4/"tpicd 2006.257.16:00:16.22$setupk4/echo=off 2006.257.16:00:16.22$setupk4/xlog=off 2006.257.16:00:16.22:!2006.257.16:02:33 2006.257.16:02:33.00:preob 2006.257.16:02:33.14/onsource/TRACKING 2006.257.16:02:33.14:!2006.257.16:02:43 2006.257.16:02:43.00:"tape 2006.257.16:02:43.00:"st=record 2006.257.16:02:43.00:data_valid=on 2006.257.16:02:43.00:midob 2006.257.16:02:43.13/onsource/TRACKING 2006.257.16:02:43.13/wx/17.32,1014.0,97 2006.257.16:02:43.27/cable/+6.4812E-03 2006.257.16:02:44.36/va/01,08,usb,yes,31,33 2006.257.16:02:44.36/va/02,07,usb,yes,33,34 2006.257.16:02:44.36/va/03,08,usb,yes,30,32 2006.257.16:02:44.36/va/04,07,usb,yes,34,36 2006.257.16:02:44.36/va/05,04,usb,yes,31,31 2006.257.16:02:44.36/va/06,04,usb,yes,34,34 2006.257.16:02:44.36/va/07,04,usb,yes,35,36 2006.257.16:02:44.36/va/08,04,usb,yes,29,36 2006.257.16:02:44.59/valo/01,524.99,yes,locked 2006.257.16:02:44.59/valo/02,534.99,yes,locked 2006.257.16:02:44.59/valo/03,564.99,yes,locked 2006.257.16:02:44.59/valo/04,624.99,yes,locked 2006.257.16:02:44.59/valo/05,734.99,yes,locked 2006.257.16:02:44.59/valo/06,814.99,yes,locked 2006.257.16:02:44.59/valo/07,864.99,yes,locked 2006.257.16:02:44.59/valo/08,884.99,yes,locked 2006.257.16:02:45.68/vb/01,04,usb,yes,31,29 2006.257.16:02:45.68/vb/02,05,usb,yes,29,29 2006.257.16:02:45.68/vb/03,04,usb,yes,30,33 2006.257.16:02:45.68/vb/04,05,usb,yes,30,29 2006.257.16:02:45.68/vb/05,04,usb,yes,27,29 2006.257.16:02:45.68/vb/06,04,usb,yes,31,28 2006.257.16:02:45.68/vb/07,04,usb,yes,31,31 2006.257.16:02:45.68/vb/08,04,usb,yes,29,32 2006.257.16:02:45.91/vblo/01,629.99,yes,locked 2006.257.16:02:45.91/vblo/02,634.99,yes,locked 2006.257.16:02:45.91/vblo/03,649.99,yes,locked 2006.257.16:02:45.91/vblo/04,679.99,yes,locked 2006.257.16:02:45.91/vblo/05,709.99,yes,locked 2006.257.16:02:45.91/vblo/06,719.99,yes,locked 2006.257.16:02:45.91/vblo/07,734.99,yes,locked 2006.257.16:02:45.91/vblo/08,744.99,yes,locked 2006.257.16:02:46.06/vabw/8 2006.257.16:02:46.21/vbbw/8 2006.257.16:02:46.30/xfe/off,on,15.0 2006.257.16:02:46.67/ifatt/23,28,28,28 2006.257.16:02:47.07/fmout-gps/S +4.58E-07 2006.257.16:02:47.11:!2006.257.16:03:33 2006.257.16:03:33.00:data_valid=off 2006.257.16:03:33.00:"et 2006.257.16:03:33.01:!+3s 2006.257.16:03:36.02:"tape 2006.257.16:03:36.02:postob 2006.257.16:03:36.24/cable/+6.4834E-03 2006.257.16:03:36.24/wx/17.33,1014.0,97 2006.257.16:03:36.30/fmout-gps/S +4.58E-07 2006.257.16:03:36.30:scan_name=257-1606,jd0609,320 2006.257.16:03:36.31:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.257.16:03:37.13#flagr#flagr/antenna,new-source 2006.257.16:03:37.13:checkk5 2006.257.16:03:37.53/chk_autoobs//k5ts1/ autoobs is running! 2006.257.16:03:37.92/chk_autoobs//k5ts2/ autoobs is running! 2006.257.16:03:38.33/chk_autoobs//k5ts3/ autoobs is running! 2006.257.16:03:38.72/chk_autoobs//k5ts4/ autoobs is running! 2006.257.16:03:39.12/chk_obsdata//k5ts1/T2571602??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.16:03:39.52/chk_obsdata//k5ts2/T2571602??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.16:03:39.92/chk_obsdata//k5ts3/T2571602??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.16:03:40.33/chk_obsdata//k5ts4/T2571602??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.16:03:41.06/k5log//k5ts1_log_newline 2006.257.16:03:41.77/k5log//k5ts2_log_newline 2006.257.16:03:42.49/k5log//k5ts3_log_newline 2006.257.16:03:43.20/k5log//k5ts4_log_newline 2006.257.16:03:43.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.16:03:43.22:setupk4=1 2006.257.16:03:43.22$setupk4/echo=on 2006.257.16:03:43.22$setupk4/pcalon 2006.257.16:03:43.22$pcalon/"no phase cal control is implemented here 2006.257.16:03:43.22$setupk4/"tpicd=stop 2006.257.16:03:43.22$setupk4/"rec=synch_on 2006.257.16:03:43.22$setupk4/"rec_mode=128 2006.257.16:03:43.22$setupk4/!* 2006.257.16:03:43.23$setupk4/recpk4 2006.257.16:03:43.23$recpk4/recpatch= 2006.257.16:03:43.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.16:03:43.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.16:03:43.23$setupk4/vck44 2006.257.16:03:43.23$vck44/valo=1,524.99 2006.257.16:03:43.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.16:03:43.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.16:03:43.23#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:43.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:43.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:43.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:43.23#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:03:43.23#ibcon#first serial, iclass 10, count 0 2006.257.16:03:43.23#ibcon#enter sib2, iclass 10, count 0 2006.257.16:03:43.23#ibcon#flushed, iclass 10, count 0 2006.257.16:03:43.23#ibcon#about to write, iclass 10, count 0 2006.257.16:03:43.23#ibcon#wrote, iclass 10, count 0 2006.257.16:03:43.23#ibcon#about to read 3, iclass 10, count 0 2006.257.16:03:43.25#ibcon#read 3, iclass 10, count 0 2006.257.16:03:43.25#ibcon#about to read 4, iclass 10, count 0 2006.257.16:03:43.25#ibcon#read 4, iclass 10, count 0 2006.257.16:03:43.25#ibcon#about to read 5, iclass 10, count 0 2006.257.16:03:43.25#ibcon#read 5, iclass 10, count 0 2006.257.16:03:43.25#ibcon#about to read 6, iclass 10, count 0 2006.257.16:03:43.25#ibcon#read 6, iclass 10, count 0 2006.257.16:03:43.25#ibcon#end of sib2, iclass 10, count 0 2006.257.16:03:43.25#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:03:43.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:03:43.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.16:03:43.25#ibcon#*before write, iclass 10, count 0 2006.257.16:03:43.25#ibcon#enter sib2, iclass 10, count 0 2006.257.16:03:43.25#ibcon#flushed, iclass 10, count 0 2006.257.16:03:43.25#ibcon#about to write, iclass 10, count 0 2006.257.16:03:43.25#ibcon#wrote, iclass 10, count 0 2006.257.16:03:43.25#ibcon#about to read 3, iclass 10, count 0 2006.257.16:03:43.30#ibcon#read 3, iclass 10, count 0 2006.257.16:03:43.30#ibcon#about to read 4, iclass 10, count 0 2006.257.16:03:43.30#ibcon#read 4, iclass 10, count 0 2006.257.16:03:43.30#ibcon#about to read 5, iclass 10, count 0 2006.257.16:03:43.30#ibcon#read 5, iclass 10, count 0 2006.257.16:03:43.30#ibcon#about to read 6, iclass 10, count 0 2006.257.16:03:43.30#ibcon#read 6, iclass 10, count 0 2006.257.16:03:43.30#ibcon#end of sib2, iclass 10, count 0 2006.257.16:03:43.30#ibcon#*after write, iclass 10, count 0 2006.257.16:03:43.30#ibcon#*before return 0, iclass 10, count 0 2006.257.16:03:43.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:43.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:43.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:03:43.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:03:43.30$vck44/va=1,8 2006.257.16:03:43.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.16:03:43.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.16:03:43.30#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:43.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:43.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:43.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:43.30#ibcon#enter wrdev, iclass 12, count 2 2006.257.16:03:43.30#ibcon#first serial, iclass 12, count 2 2006.257.16:03:43.30#ibcon#enter sib2, iclass 12, count 2 2006.257.16:03:43.30#ibcon#flushed, iclass 12, count 2 2006.257.16:03:43.30#ibcon#about to write, iclass 12, count 2 2006.257.16:03:43.30#ibcon#wrote, iclass 12, count 2 2006.257.16:03:43.30#ibcon#about to read 3, iclass 12, count 2 2006.257.16:03:43.32#ibcon#read 3, iclass 12, count 2 2006.257.16:03:43.32#ibcon#about to read 4, iclass 12, count 2 2006.257.16:03:43.32#ibcon#read 4, iclass 12, count 2 2006.257.16:03:43.32#ibcon#about to read 5, iclass 12, count 2 2006.257.16:03:43.32#ibcon#read 5, iclass 12, count 2 2006.257.16:03:43.32#ibcon#about to read 6, iclass 12, count 2 2006.257.16:03:43.32#ibcon#read 6, iclass 12, count 2 2006.257.16:03:43.32#ibcon#end of sib2, iclass 12, count 2 2006.257.16:03:43.32#ibcon#*mode == 0, iclass 12, count 2 2006.257.16:03:43.32#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.16:03:43.32#ibcon#[25=AT01-08\r\n] 2006.257.16:03:43.32#ibcon#*before write, iclass 12, count 2 2006.257.16:03:43.32#ibcon#enter sib2, iclass 12, count 2 2006.257.16:03:43.32#ibcon#flushed, iclass 12, count 2 2006.257.16:03:43.32#ibcon#about to write, iclass 12, count 2 2006.257.16:03:43.32#ibcon#wrote, iclass 12, count 2 2006.257.16:03:43.32#ibcon#about to read 3, iclass 12, count 2 2006.257.16:03:43.35#ibcon#read 3, iclass 12, count 2 2006.257.16:03:43.35#ibcon#about to read 4, iclass 12, count 2 2006.257.16:03:43.35#ibcon#read 4, iclass 12, count 2 2006.257.16:03:43.35#ibcon#about to read 5, iclass 12, count 2 2006.257.16:03:43.35#ibcon#read 5, iclass 12, count 2 2006.257.16:03:43.35#ibcon#about to read 6, iclass 12, count 2 2006.257.16:03:43.35#ibcon#read 6, iclass 12, count 2 2006.257.16:03:43.35#ibcon#end of sib2, iclass 12, count 2 2006.257.16:03:43.35#ibcon#*after write, iclass 12, count 2 2006.257.16:03:43.35#ibcon#*before return 0, iclass 12, count 2 2006.257.16:03:43.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:43.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:43.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.16:03:43.35#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:43.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:43.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:43.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:43.47#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:03:43.47#ibcon#first serial, iclass 12, count 0 2006.257.16:03:43.47#ibcon#enter sib2, iclass 12, count 0 2006.257.16:03:43.47#ibcon#flushed, iclass 12, count 0 2006.257.16:03:43.47#ibcon#about to write, iclass 12, count 0 2006.257.16:03:43.47#ibcon#wrote, iclass 12, count 0 2006.257.16:03:43.47#ibcon#about to read 3, iclass 12, count 0 2006.257.16:03:43.49#ibcon#read 3, iclass 12, count 0 2006.257.16:03:43.49#ibcon#about to read 4, iclass 12, count 0 2006.257.16:03:43.49#ibcon#read 4, iclass 12, count 0 2006.257.16:03:43.49#ibcon#about to read 5, iclass 12, count 0 2006.257.16:03:43.49#ibcon#read 5, iclass 12, count 0 2006.257.16:03:43.49#ibcon#about to read 6, iclass 12, count 0 2006.257.16:03:43.49#ibcon#read 6, iclass 12, count 0 2006.257.16:03:43.49#ibcon#end of sib2, iclass 12, count 0 2006.257.16:03:43.49#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:03:43.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:03:43.49#ibcon#[25=USB\r\n] 2006.257.16:03:43.49#ibcon#*before write, iclass 12, count 0 2006.257.16:03:43.49#ibcon#enter sib2, iclass 12, count 0 2006.257.16:03:43.49#ibcon#flushed, iclass 12, count 0 2006.257.16:03:43.49#ibcon#about to write, iclass 12, count 0 2006.257.16:03:43.49#ibcon#wrote, iclass 12, count 0 2006.257.16:03:43.49#ibcon#about to read 3, iclass 12, count 0 2006.257.16:03:43.52#ibcon#read 3, iclass 12, count 0 2006.257.16:03:43.52#ibcon#about to read 4, iclass 12, count 0 2006.257.16:03:43.52#ibcon#read 4, iclass 12, count 0 2006.257.16:03:43.52#ibcon#about to read 5, iclass 12, count 0 2006.257.16:03:43.52#ibcon#read 5, iclass 12, count 0 2006.257.16:03:43.52#ibcon#about to read 6, iclass 12, count 0 2006.257.16:03:43.52#ibcon#read 6, iclass 12, count 0 2006.257.16:03:43.52#ibcon#end of sib2, iclass 12, count 0 2006.257.16:03:43.52#ibcon#*after write, iclass 12, count 0 2006.257.16:03:43.52#ibcon#*before return 0, iclass 12, count 0 2006.257.16:03:43.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:43.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:43.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:03:43.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:03:43.52$vck44/valo=2,534.99 2006.257.16:03:43.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.16:03:43.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.16:03:43.52#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:43.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:43.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:43.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:43.52#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:03:43.52#ibcon#first serial, iclass 14, count 0 2006.257.16:03:43.52#ibcon#enter sib2, iclass 14, count 0 2006.257.16:03:43.52#ibcon#flushed, iclass 14, count 0 2006.257.16:03:43.52#ibcon#about to write, iclass 14, count 0 2006.257.16:03:43.52#ibcon#wrote, iclass 14, count 0 2006.257.16:03:43.52#ibcon#about to read 3, iclass 14, count 0 2006.257.16:03:43.54#ibcon#read 3, iclass 14, count 0 2006.257.16:03:43.54#ibcon#about to read 4, iclass 14, count 0 2006.257.16:03:43.54#ibcon#read 4, iclass 14, count 0 2006.257.16:03:43.54#ibcon#about to read 5, iclass 14, count 0 2006.257.16:03:43.54#ibcon#read 5, iclass 14, count 0 2006.257.16:03:43.54#ibcon#about to read 6, iclass 14, count 0 2006.257.16:03:43.54#ibcon#read 6, iclass 14, count 0 2006.257.16:03:43.54#ibcon#end of sib2, iclass 14, count 0 2006.257.16:03:43.54#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:03:43.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:03:43.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.16:03:43.54#ibcon#*before write, iclass 14, count 0 2006.257.16:03:43.54#ibcon#enter sib2, iclass 14, count 0 2006.257.16:03:43.54#ibcon#flushed, iclass 14, count 0 2006.257.16:03:43.54#ibcon#about to write, iclass 14, count 0 2006.257.16:03:43.54#ibcon#wrote, iclass 14, count 0 2006.257.16:03:43.54#ibcon#about to read 3, iclass 14, count 0 2006.257.16:03:43.58#ibcon#read 3, iclass 14, count 0 2006.257.16:03:43.58#ibcon#about to read 4, iclass 14, count 0 2006.257.16:03:43.58#ibcon#read 4, iclass 14, count 0 2006.257.16:03:43.58#ibcon#about to read 5, iclass 14, count 0 2006.257.16:03:43.58#ibcon#read 5, iclass 14, count 0 2006.257.16:03:43.58#ibcon#about to read 6, iclass 14, count 0 2006.257.16:03:43.58#ibcon#read 6, iclass 14, count 0 2006.257.16:03:43.58#ibcon#end of sib2, iclass 14, count 0 2006.257.16:03:43.58#ibcon#*after write, iclass 14, count 0 2006.257.16:03:43.58#ibcon#*before return 0, iclass 14, count 0 2006.257.16:03:43.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:43.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:43.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:03:43.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:03:43.58$vck44/va=2,7 2006.257.16:03:43.58#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.16:03:43.58#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.16:03:43.58#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:43.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:43.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:43.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:43.64#ibcon#enter wrdev, iclass 16, count 2 2006.257.16:03:43.64#ibcon#first serial, iclass 16, count 2 2006.257.16:03:43.64#ibcon#enter sib2, iclass 16, count 2 2006.257.16:03:43.64#ibcon#flushed, iclass 16, count 2 2006.257.16:03:43.64#ibcon#about to write, iclass 16, count 2 2006.257.16:03:43.64#ibcon#wrote, iclass 16, count 2 2006.257.16:03:43.64#ibcon#about to read 3, iclass 16, count 2 2006.257.16:03:43.66#ibcon#read 3, iclass 16, count 2 2006.257.16:03:43.66#ibcon#about to read 4, iclass 16, count 2 2006.257.16:03:43.66#ibcon#read 4, iclass 16, count 2 2006.257.16:03:43.66#ibcon#about to read 5, iclass 16, count 2 2006.257.16:03:43.66#ibcon#read 5, iclass 16, count 2 2006.257.16:03:43.66#ibcon#about to read 6, iclass 16, count 2 2006.257.16:03:43.66#ibcon#read 6, iclass 16, count 2 2006.257.16:03:43.66#ibcon#end of sib2, iclass 16, count 2 2006.257.16:03:43.66#ibcon#*mode == 0, iclass 16, count 2 2006.257.16:03:43.66#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.16:03:43.66#ibcon#[25=AT02-07\r\n] 2006.257.16:03:43.66#ibcon#*before write, iclass 16, count 2 2006.257.16:03:43.66#ibcon#enter sib2, iclass 16, count 2 2006.257.16:03:43.66#ibcon#flushed, iclass 16, count 2 2006.257.16:03:43.66#ibcon#about to write, iclass 16, count 2 2006.257.16:03:43.66#ibcon#wrote, iclass 16, count 2 2006.257.16:03:43.66#ibcon#about to read 3, iclass 16, count 2 2006.257.16:03:43.69#ibcon#read 3, iclass 16, count 2 2006.257.16:03:43.69#ibcon#about to read 4, iclass 16, count 2 2006.257.16:03:43.69#ibcon#read 4, iclass 16, count 2 2006.257.16:03:43.69#ibcon#about to read 5, iclass 16, count 2 2006.257.16:03:43.69#ibcon#read 5, iclass 16, count 2 2006.257.16:03:43.69#ibcon#about to read 6, iclass 16, count 2 2006.257.16:03:43.69#ibcon#read 6, iclass 16, count 2 2006.257.16:03:43.69#ibcon#end of sib2, iclass 16, count 2 2006.257.16:03:43.69#ibcon#*after write, iclass 16, count 2 2006.257.16:03:43.69#ibcon#*before return 0, iclass 16, count 2 2006.257.16:03:43.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:43.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:43.69#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.16:03:43.69#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:43.69#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:43.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:43.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:43.81#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:03:43.81#ibcon#first serial, iclass 16, count 0 2006.257.16:03:43.81#ibcon#enter sib2, iclass 16, count 0 2006.257.16:03:43.81#ibcon#flushed, iclass 16, count 0 2006.257.16:03:43.81#ibcon#about to write, iclass 16, count 0 2006.257.16:03:43.81#ibcon#wrote, iclass 16, count 0 2006.257.16:03:43.81#ibcon#about to read 3, iclass 16, count 0 2006.257.16:03:43.83#ibcon#read 3, iclass 16, count 0 2006.257.16:03:43.83#ibcon#about to read 4, iclass 16, count 0 2006.257.16:03:43.83#ibcon#read 4, iclass 16, count 0 2006.257.16:03:43.83#ibcon#about to read 5, iclass 16, count 0 2006.257.16:03:43.83#ibcon#read 5, iclass 16, count 0 2006.257.16:03:43.83#ibcon#about to read 6, iclass 16, count 0 2006.257.16:03:43.83#ibcon#read 6, iclass 16, count 0 2006.257.16:03:43.83#ibcon#end of sib2, iclass 16, count 0 2006.257.16:03:43.83#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:03:43.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:03:43.83#ibcon#[25=USB\r\n] 2006.257.16:03:43.83#ibcon#*before write, iclass 16, count 0 2006.257.16:03:43.83#ibcon#enter sib2, iclass 16, count 0 2006.257.16:03:43.83#ibcon#flushed, iclass 16, count 0 2006.257.16:03:43.83#ibcon#about to write, iclass 16, count 0 2006.257.16:03:43.83#ibcon#wrote, iclass 16, count 0 2006.257.16:03:43.83#ibcon#about to read 3, iclass 16, count 0 2006.257.16:03:43.86#ibcon#read 3, iclass 16, count 0 2006.257.16:03:43.86#ibcon#about to read 4, iclass 16, count 0 2006.257.16:03:43.86#ibcon#read 4, iclass 16, count 0 2006.257.16:03:43.86#ibcon#about to read 5, iclass 16, count 0 2006.257.16:03:43.86#ibcon#read 5, iclass 16, count 0 2006.257.16:03:43.86#ibcon#about to read 6, iclass 16, count 0 2006.257.16:03:43.86#ibcon#read 6, iclass 16, count 0 2006.257.16:03:43.86#ibcon#end of sib2, iclass 16, count 0 2006.257.16:03:43.86#ibcon#*after write, iclass 16, count 0 2006.257.16:03:43.86#ibcon#*before return 0, iclass 16, count 0 2006.257.16:03:43.86#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:43.86#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:43.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:03:43.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:03:43.86$vck44/valo=3,564.99 2006.257.16:03:43.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.16:03:43.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.16:03:43.86#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:43.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:43.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:43.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:43.86#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:03:43.86#ibcon#first serial, iclass 18, count 0 2006.257.16:03:43.86#ibcon#enter sib2, iclass 18, count 0 2006.257.16:03:43.86#ibcon#flushed, iclass 18, count 0 2006.257.16:03:43.86#ibcon#about to write, iclass 18, count 0 2006.257.16:03:43.86#ibcon#wrote, iclass 18, count 0 2006.257.16:03:43.86#ibcon#about to read 3, iclass 18, count 0 2006.257.16:03:43.88#ibcon#read 3, iclass 18, count 0 2006.257.16:03:43.88#ibcon#about to read 4, iclass 18, count 0 2006.257.16:03:43.88#ibcon#read 4, iclass 18, count 0 2006.257.16:03:43.88#ibcon#about to read 5, iclass 18, count 0 2006.257.16:03:43.88#ibcon#read 5, iclass 18, count 0 2006.257.16:03:43.88#ibcon#about to read 6, iclass 18, count 0 2006.257.16:03:43.88#ibcon#read 6, iclass 18, count 0 2006.257.16:03:43.88#ibcon#end of sib2, iclass 18, count 0 2006.257.16:03:43.88#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:03:43.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:03:43.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.16:03:43.88#ibcon#*before write, iclass 18, count 0 2006.257.16:03:43.88#ibcon#enter sib2, iclass 18, count 0 2006.257.16:03:43.88#ibcon#flushed, iclass 18, count 0 2006.257.16:03:43.88#ibcon#about to write, iclass 18, count 0 2006.257.16:03:43.88#ibcon#wrote, iclass 18, count 0 2006.257.16:03:43.88#ibcon#about to read 3, iclass 18, count 0 2006.257.16:03:43.92#ibcon#read 3, iclass 18, count 0 2006.257.16:03:43.92#ibcon#about to read 4, iclass 18, count 0 2006.257.16:03:43.92#ibcon#read 4, iclass 18, count 0 2006.257.16:03:43.92#ibcon#about to read 5, iclass 18, count 0 2006.257.16:03:43.92#ibcon#read 5, iclass 18, count 0 2006.257.16:03:43.92#ibcon#about to read 6, iclass 18, count 0 2006.257.16:03:43.92#ibcon#read 6, iclass 18, count 0 2006.257.16:03:43.92#ibcon#end of sib2, iclass 18, count 0 2006.257.16:03:43.92#ibcon#*after write, iclass 18, count 0 2006.257.16:03:43.92#ibcon#*before return 0, iclass 18, count 0 2006.257.16:03:43.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:43.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:43.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:03:43.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:03:43.92$vck44/va=3,8 2006.257.16:03:43.92#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.16:03:43.92#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.16:03:43.92#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:43.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:43.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:43.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:43.98#ibcon#enter wrdev, iclass 20, count 2 2006.257.16:03:43.98#ibcon#first serial, iclass 20, count 2 2006.257.16:03:43.98#ibcon#enter sib2, iclass 20, count 2 2006.257.16:03:43.98#ibcon#flushed, iclass 20, count 2 2006.257.16:03:43.98#ibcon#about to write, iclass 20, count 2 2006.257.16:03:43.98#ibcon#wrote, iclass 20, count 2 2006.257.16:03:43.98#ibcon#about to read 3, iclass 20, count 2 2006.257.16:03:44.00#ibcon#read 3, iclass 20, count 2 2006.257.16:03:44.00#ibcon#about to read 4, iclass 20, count 2 2006.257.16:03:44.00#ibcon#read 4, iclass 20, count 2 2006.257.16:03:44.00#ibcon#about to read 5, iclass 20, count 2 2006.257.16:03:44.00#ibcon#read 5, iclass 20, count 2 2006.257.16:03:44.00#ibcon#about to read 6, iclass 20, count 2 2006.257.16:03:44.00#ibcon#read 6, iclass 20, count 2 2006.257.16:03:44.00#ibcon#end of sib2, iclass 20, count 2 2006.257.16:03:44.00#ibcon#*mode == 0, iclass 20, count 2 2006.257.16:03:44.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.16:03:44.00#ibcon#[25=AT03-08\r\n] 2006.257.16:03:44.00#ibcon#*before write, iclass 20, count 2 2006.257.16:03:44.00#ibcon#enter sib2, iclass 20, count 2 2006.257.16:03:44.00#ibcon#flushed, iclass 20, count 2 2006.257.16:03:44.00#ibcon#about to write, iclass 20, count 2 2006.257.16:03:44.00#ibcon#wrote, iclass 20, count 2 2006.257.16:03:44.00#ibcon#about to read 3, iclass 20, count 2 2006.257.16:03:44.03#ibcon#read 3, iclass 20, count 2 2006.257.16:03:44.03#ibcon#about to read 4, iclass 20, count 2 2006.257.16:03:44.03#ibcon#read 4, iclass 20, count 2 2006.257.16:03:44.03#ibcon#about to read 5, iclass 20, count 2 2006.257.16:03:44.03#ibcon#read 5, iclass 20, count 2 2006.257.16:03:44.03#ibcon#about to read 6, iclass 20, count 2 2006.257.16:03:44.03#ibcon#read 6, iclass 20, count 2 2006.257.16:03:44.03#ibcon#end of sib2, iclass 20, count 2 2006.257.16:03:44.03#ibcon#*after write, iclass 20, count 2 2006.257.16:03:44.03#ibcon#*before return 0, iclass 20, count 2 2006.257.16:03:44.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:44.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:44.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.16:03:44.03#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:44.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:44.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:44.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:44.15#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:03:44.15#ibcon#first serial, iclass 20, count 0 2006.257.16:03:44.15#ibcon#enter sib2, iclass 20, count 0 2006.257.16:03:44.15#ibcon#flushed, iclass 20, count 0 2006.257.16:03:44.15#ibcon#about to write, iclass 20, count 0 2006.257.16:03:44.15#ibcon#wrote, iclass 20, count 0 2006.257.16:03:44.15#ibcon#about to read 3, iclass 20, count 0 2006.257.16:03:44.17#ibcon#read 3, iclass 20, count 0 2006.257.16:03:44.17#ibcon#about to read 4, iclass 20, count 0 2006.257.16:03:44.17#ibcon#read 4, iclass 20, count 0 2006.257.16:03:44.17#ibcon#about to read 5, iclass 20, count 0 2006.257.16:03:44.17#ibcon#read 5, iclass 20, count 0 2006.257.16:03:44.17#ibcon#about to read 6, iclass 20, count 0 2006.257.16:03:44.17#ibcon#read 6, iclass 20, count 0 2006.257.16:03:44.17#ibcon#end of sib2, iclass 20, count 0 2006.257.16:03:44.17#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:03:44.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:03:44.17#ibcon#[25=USB\r\n] 2006.257.16:03:44.17#ibcon#*before write, iclass 20, count 0 2006.257.16:03:44.17#ibcon#enter sib2, iclass 20, count 0 2006.257.16:03:44.17#ibcon#flushed, iclass 20, count 0 2006.257.16:03:44.17#ibcon#about to write, iclass 20, count 0 2006.257.16:03:44.17#ibcon#wrote, iclass 20, count 0 2006.257.16:03:44.17#ibcon#about to read 3, iclass 20, count 0 2006.257.16:03:44.20#ibcon#read 3, iclass 20, count 0 2006.257.16:03:44.20#ibcon#about to read 4, iclass 20, count 0 2006.257.16:03:44.20#ibcon#read 4, iclass 20, count 0 2006.257.16:03:44.20#ibcon#about to read 5, iclass 20, count 0 2006.257.16:03:44.20#ibcon#read 5, iclass 20, count 0 2006.257.16:03:44.20#ibcon#about to read 6, iclass 20, count 0 2006.257.16:03:44.20#ibcon#read 6, iclass 20, count 0 2006.257.16:03:44.20#ibcon#end of sib2, iclass 20, count 0 2006.257.16:03:44.20#ibcon#*after write, iclass 20, count 0 2006.257.16:03:44.20#ibcon#*before return 0, iclass 20, count 0 2006.257.16:03:44.20#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:44.20#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:44.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:03:44.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:03:44.20$vck44/valo=4,624.99 2006.257.16:03:44.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.16:03:44.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.16:03:44.20#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:44.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:44.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:44.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:44.20#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:03:44.20#ibcon#first serial, iclass 22, count 0 2006.257.16:03:44.20#ibcon#enter sib2, iclass 22, count 0 2006.257.16:03:44.20#ibcon#flushed, iclass 22, count 0 2006.257.16:03:44.20#ibcon#about to write, iclass 22, count 0 2006.257.16:03:44.20#ibcon#wrote, iclass 22, count 0 2006.257.16:03:44.20#ibcon#about to read 3, iclass 22, count 0 2006.257.16:03:44.22#ibcon#read 3, iclass 22, count 0 2006.257.16:03:44.22#ibcon#about to read 4, iclass 22, count 0 2006.257.16:03:44.22#ibcon#read 4, iclass 22, count 0 2006.257.16:03:44.22#ibcon#about to read 5, iclass 22, count 0 2006.257.16:03:44.22#ibcon#read 5, iclass 22, count 0 2006.257.16:03:44.22#ibcon#about to read 6, iclass 22, count 0 2006.257.16:03:44.22#ibcon#read 6, iclass 22, count 0 2006.257.16:03:44.22#ibcon#end of sib2, iclass 22, count 0 2006.257.16:03:44.22#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:03:44.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:03:44.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.16:03:44.22#ibcon#*before write, iclass 22, count 0 2006.257.16:03:44.22#ibcon#enter sib2, iclass 22, count 0 2006.257.16:03:44.22#ibcon#flushed, iclass 22, count 0 2006.257.16:03:44.22#ibcon#about to write, iclass 22, count 0 2006.257.16:03:44.22#ibcon#wrote, iclass 22, count 0 2006.257.16:03:44.22#ibcon#about to read 3, iclass 22, count 0 2006.257.16:03:44.26#ibcon#read 3, iclass 22, count 0 2006.257.16:03:44.26#ibcon#about to read 4, iclass 22, count 0 2006.257.16:03:44.26#ibcon#read 4, iclass 22, count 0 2006.257.16:03:44.26#ibcon#about to read 5, iclass 22, count 0 2006.257.16:03:44.26#ibcon#read 5, iclass 22, count 0 2006.257.16:03:44.26#ibcon#about to read 6, iclass 22, count 0 2006.257.16:03:44.26#ibcon#read 6, iclass 22, count 0 2006.257.16:03:44.26#ibcon#end of sib2, iclass 22, count 0 2006.257.16:03:44.26#ibcon#*after write, iclass 22, count 0 2006.257.16:03:44.26#ibcon#*before return 0, iclass 22, count 0 2006.257.16:03:44.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:44.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:44.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:03:44.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:03:44.26$vck44/va=4,7 2006.257.16:03:44.26#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.16:03:44.26#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.16:03:44.26#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:44.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:44.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:44.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:44.32#ibcon#enter wrdev, iclass 24, count 2 2006.257.16:03:44.32#ibcon#first serial, iclass 24, count 2 2006.257.16:03:44.32#ibcon#enter sib2, iclass 24, count 2 2006.257.16:03:44.32#ibcon#flushed, iclass 24, count 2 2006.257.16:03:44.32#ibcon#about to write, iclass 24, count 2 2006.257.16:03:44.32#ibcon#wrote, iclass 24, count 2 2006.257.16:03:44.32#ibcon#about to read 3, iclass 24, count 2 2006.257.16:03:44.34#ibcon#read 3, iclass 24, count 2 2006.257.16:03:44.34#ibcon#about to read 4, iclass 24, count 2 2006.257.16:03:44.34#ibcon#read 4, iclass 24, count 2 2006.257.16:03:44.34#ibcon#about to read 5, iclass 24, count 2 2006.257.16:03:44.34#ibcon#read 5, iclass 24, count 2 2006.257.16:03:44.34#ibcon#about to read 6, iclass 24, count 2 2006.257.16:03:44.34#ibcon#read 6, iclass 24, count 2 2006.257.16:03:44.34#ibcon#end of sib2, iclass 24, count 2 2006.257.16:03:44.34#ibcon#*mode == 0, iclass 24, count 2 2006.257.16:03:44.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.16:03:44.34#ibcon#[25=AT04-07\r\n] 2006.257.16:03:44.34#ibcon#*before write, iclass 24, count 2 2006.257.16:03:44.34#ibcon#enter sib2, iclass 24, count 2 2006.257.16:03:44.34#ibcon#flushed, iclass 24, count 2 2006.257.16:03:44.34#ibcon#about to write, iclass 24, count 2 2006.257.16:03:44.34#ibcon#wrote, iclass 24, count 2 2006.257.16:03:44.34#ibcon#about to read 3, iclass 24, count 2 2006.257.16:03:44.37#ibcon#read 3, iclass 24, count 2 2006.257.16:03:44.43#ibcon#about to read 4, iclass 24, count 2 2006.257.16:03:44.43#ibcon#read 4, iclass 24, count 2 2006.257.16:03:44.43#ibcon#about to read 5, iclass 24, count 2 2006.257.16:03:44.43#ibcon#read 5, iclass 24, count 2 2006.257.16:03:44.43#ibcon#about to read 6, iclass 24, count 2 2006.257.16:03:44.43#ibcon#read 6, iclass 24, count 2 2006.257.16:03:44.43#ibcon#end of sib2, iclass 24, count 2 2006.257.16:03:44.43#ibcon#*after write, iclass 24, count 2 2006.257.16:03:44.43#ibcon#*before return 0, iclass 24, count 2 2006.257.16:03:44.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:44.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:44.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.16:03:44.43#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:44.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:44.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:44.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:44.55#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:03:44.55#ibcon#first serial, iclass 24, count 0 2006.257.16:03:44.55#ibcon#enter sib2, iclass 24, count 0 2006.257.16:03:44.55#ibcon#flushed, iclass 24, count 0 2006.257.16:03:44.55#ibcon#about to write, iclass 24, count 0 2006.257.16:03:44.55#ibcon#wrote, iclass 24, count 0 2006.257.16:03:44.55#ibcon#about to read 3, iclass 24, count 0 2006.257.16:03:44.57#ibcon#read 3, iclass 24, count 0 2006.257.16:03:44.57#ibcon#about to read 4, iclass 24, count 0 2006.257.16:03:44.57#ibcon#read 4, iclass 24, count 0 2006.257.16:03:44.57#ibcon#about to read 5, iclass 24, count 0 2006.257.16:03:44.57#ibcon#read 5, iclass 24, count 0 2006.257.16:03:44.57#ibcon#about to read 6, iclass 24, count 0 2006.257.16:03:44.57#ibcon#read 6, iclass 24, count 0 2006.257.16:03:44.57#ibcon#end of sib2, iclass 24, count 0 2006.257.16:03:44.57#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:03:44.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:03:44.57#ibcon#[25=USB\r\n] 2006.257.16:03:44.57#ibcon#*before write, iclass 24, count 0 2006.257.16:03:44.57#ibcon#enter sib2, iclass 24, count 0 2006.257.16:03:44.57#ibcon#flushed, iclass 24, count 0 2006.257.16:03:44.57#ibcon#about to write, iclass 24, count 0 2006.257.16:03:44.57#ibcon#wrote, iclass 24, count 0 2006.257.16:03:44.57#ibcon#about to read 3, iclass 24, count 0 2006.257.16:03:44.60#ibcon#read 3, iclass 24, count 0 2006.257.16:03:44.60#ibcon#about to read 4, iclass 24, count 0 2006.257.16:03:44.60#ibcon#read 4, iclass 24, count 0 2006.257.16:03:44.60#ibcon#about to read 5, iclass 24, count 0 2006.257.16:03:44.60#ibcon#read 5, iclass 24, count 0 2006.257.16:03:44.60#ibcon#about to read 6, iclass 24, count 0 2006.257.16:03:44.60#ibcon#read 6, iclass 24, count 0 2006.257.16:03:44.60#ibcon#end of sib2, iclass 24, count 0 2006.257.16:03:44.60#ibcon#*after write, iclass 24, count 0 2006.257.16:03:44.60#ibcon#*before return 0, iclass 24, count 0 2006.257.16:03:44.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:44.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:44.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:03:44.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:03:44.60$vck44/valo=5,734.99 2006.257.16:03:44.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.16:03:44.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.16:03:44.60#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:44.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:44.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:44.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:44.60#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:03:44.60#ibcon#first serial, iclass 26, count 0 2006.257.16:03:44.60#ibcon#enter sib2, iclass 26, count 0 2006.257.16:03:44.60#ibcon#flushed, iclass 26, count 0 2006.257.16:03:44.60#ibcon#about to write, iclass 26, count 0 2006.257.16:03:44.60#ibcon#wrote, iclass 26, count 0 2006.257.16:03:44.60#ibcon#about to read 3, iclass 26, count 0 2006.257.16:03:44.62#ibcon#read 3, iclass 26, count 0 2006.257.16:03:44.62#ibcon#about to read 4, iclass 26, count 0 2006.257.16:03:44.62#ibcon#read 4, iclass 26, count 0 2006.257.16:03:44.62#ibcon#about to read 5, iclass 26, count 0 2006.257.16:03:44.62#ibcon#read 5, iclass 26, count 0 2006.257.16:03:44.62#ibcon#about to read 6, iclass 26, count 0 2006.257.16:03:44.62#ibcon#read 6, iclass 26, count 0 2006.257.16:03:44.62#ibcon#end of sib2, iclass 26, count 0 2006.257.16:03:44.62#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:03:44.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:03:44.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.16:03:44.62#ibcon#*before write, iclass 26, count 0 2006.257.16:03:44.62#ibcon#enter sib2, iclass 26, count 0 2006.257.16:03:44.62#ibcon#flushed, iclass 26, count 0 2006.257.16:03:44.62#ibcon#about to write, iclass 26, count 0 2006.257.16:03:44.62#ibcon#wrote, iclass 26, count 0 2006.257.16:03:44.62#ibcon#about to read 3, iclass 26, count 0 2006.257.16:03:44.66#ibcon#read 3, iclass 26, count 0 2006.257.16:03:44.66#ibcon#about to read 4, iclass 26, count 0 2006.257.16:03:44.66#ibcon#read 4, iclass 26, count 0 2006.257.16:03:44.66#ibcon#about to read 5, iclass 26, count 0 2006.257.16:03:44.66#ibcon#read 5, iclass 26, count 0 2006.257.16:03:44.66#ibcon#about to read 6, iclass 26, count 0 2006.257.16:03:44.66#ibcon#read 6, iclass 26, count 0 2006.257.16:03:44.66#ibcon#end of sib2, iclass 26, count 0 2006.257.16:03:44.66#ibcon#*after write, iclass 26, count 0 2006.257.16:03:44.66#ibcon#*before return 0, iclass 26, count 0 2006.257.16:03:44.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:44.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:44.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:03:44.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:03:44.66$vck44/va=5,4 2006.257.16:03:44.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.16:03:44.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.16:03:44.66#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:44.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:44.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:44.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:44.72#ibcon#enter wrdev, iclass 28, count 2 2006.257.16:03:44.72#ibcon#first serial, iclass 28, count 2 2006.257.16:03:44.72#ibcon#enter sib2, iclass 28, count 2 2006.257.16:03:44.72#ibcon#flushed, iclass 28, count 2 2006.257.16:03:44.72#ibcon#about to write, iclass 28, count 2 2006.257.16:03:44.72#ibcon#wrote, iclass 28, count 2 2006.257.16:03:44.72#ibcon#about to read 3, iclass 28, count 2 2006.257.16:03:44.74#ibcon#read 3, iclass 28, count 2 2006.257.16:03:44.74#ibcon#about to read 4, iclass 28, count 2 2006.257.16:03:44.74#ibcon#read 4, iclass 28, count 2 2006.257.16:03:44.74#ibcon#about to read 5, iclass 28, count 2 2006.257.16:03:44.74#ibcon#read 5, iclass 28, count 2 2006.257.16:03:44.74#ibcon#about to read 6, iclass 28, count 2 2006.257.16:03:44.74#ibcon#read 6, iclass 28, count 2 2006.257.16:03:44.74#ibcon#end of sib2, iclass 28, count 2 2006.257.16:03:44.74#ibcon#*mode == 0, iclass 28, count 2 2006.257.16:03:44.74#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.16:03:44.74#ibcon#[25=AT05-04\r\n] 2006.257.16:03:44.74#ibcon#*before write, iclass 28, count 2 2006.257.16:03:44.74#ibcon#enter sib2, iclass 28, count 2 2006.257.16:03:44.74#ibcon#flushed, iclass 28, count 2 2006.257.16:03:44.74#ibcon#about to write, iclass 28, count 2 2006.257.16:03:44.74#ibcon#wrote, iclass 28, count 2 2006.257.16:03:44.74#ibcon#about to read 3, iclass 28, count 2 2006.257.16:03:44.77#ibcon#read 3, iclass 28, count 2 2006.257.16:03:44.77#ibcon#about to read 4, iclass 28, count 2 2006.257.16:03:44.77#ibcon#read 4, iclass 28, count 2 2006.257.16:03:44.77#ibcon#about to read 5, iclass 28, count 2 2006.257.16:03:44.77#ibcon#read 5, iclass 28, count 2 2006.257.16:03:44.77#ibcon#about to read 6, iclass 28, count 2 2006.257.16:03:44.77#ibcon#read 6, iclass 28, count 2 2006.257.16:03:44.77#ibcon#end of sib2, iclass 28, count 2 2006.257.16:03:44.77#ibcon#*after write, iclass 28, count 2 2006.257.16:03:44.77#ibcon#*before return 0, iclass 28, count 2 2006.257.16:03:44.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:44.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:44.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.16:03:44.77#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:44.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:44.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:44.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:44.89#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:03:44.89#ibcon#first serial, iclass 28, count 0 2006.257.16:03:44.89#ibcon#enter sib2, iclass 28, count 0 2006.257.16:03:44.89#ibcon#flushed, iclass 28, count 0 2006.257.16:03:44.89#ibcon#about to write, iclass 28, count 0 2006.257.16:03:44.89#ibcon#wrote, iclass 28, count 0 2006.257.16:03:44.89#ibcon#about to read 3, iclass 28, count 0 2006.257.16:03:44.91#ibcon#read 3, iclass 28, count 0 2006.257.16:03:44.91#ibcon#about to read 4, iclass 28, count 0 2006.257.16:03:44.91#ibcon#read 4, iclass 28, count 0 2006.257.16:03:44.91#ibcon#about to read 5, iclass 28, count 0 2006.257.16:03:44.91#ibcon#read 5, iclass 28, count 0 2006.257.16:03:44.91#ibcon#about to read 6, iclass 28, count 0 2006.257.16:03:44.91#ibcon#read 6, iclass 28, count 0 2006.257.16:03:44.91#ibcon#end of sib2, iclass 28, count 0 2006.257.16:03:44.91#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:03:44.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:03:44.91#ibcon#[25=USB\r\n] 2006.257.16:03:44.91#ibcon#*before write, iclass 28, count 0 2006.257.16:03:44.91#ibcon#enter sib2, iclass 28, count 0 2006.257.16:03:44.91#ibcon#flushed, iclass 28, count 0 2006.257.16:03:44.91#ibcon#about to write, iclass 28, count 0 2006.257.16:03:44.91#ibcon#wrote, iclass 28, count 0 2006.257.16:03:44.91#ibcon#about to read 3, iclass 28, count 0 2006.257.16:03:44.94#ibcon#read 3, iclass 28, count 0 2006.257.16:03:44.94#ibcon#about to read 4, iclass 28, count 0 2006.257.16:03:44.94#ibcon#read 4, iclass 28, count 0 2006.257.16:03:44.94#ibcon#about to read 5, iclass 28, count 0 2006.257.16:03:44.94#ibcon#read 5, iclass 28, count 0 2006.257.16:03:44.94#ibcon#about to read 6, iclass 28, count 0 2006.257.16:03:44.94#ibcon#read 6, iclass 28, count 0 2006.257.16:03:44.94#ibcon#end of sib2, iclass 28, count 0 2006.257.16:03:44.94#ibcon#*after write, iclass 28, count 0 2006.257.16:03:44.94#ibcon#*before return 0, iclass 28, count 0 2006.257.16:03:44.94#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:44.94#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:44.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:03:44.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:03:44.94$vck44/valo=6,814.99 2006.257.16:03:44.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.16:03:44.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.16:03:44.94#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:44.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:03:44.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:03:44.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:03:44.94#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:03:44.94#ibcon#first serial, iclass 30, count 0 2006.257.16:03:44.94#ibcon#enter sib2, iclass 30, count 0 2006.257.16:03:44.94#ibcon#flushed, iclass 30, count 0 2006.257.16:03:44.94#ibcon#about to write, iclass 30, count 0 2006.257.16:03:44.94#ibcon#wrote, iclass 30, count 0 2006.257.16:03:44.94#ibcon#about to read 3, iclass 30, count 0 2006.257.16:03:44.96#ibcon#read 3, iclass 30, count 0 2006.257.16:03:44.96#ibcon#about to read 4, iclass 30, count 0 2006.257.16:03:44.96#ibcon#read 4, iclass 30, count 0 2006.257.16:03:44.96#ibcon#about to read 5, iclass 30, count 0 2006.257.16:03:44.96#ibcon#read 5, iclass 30, count 0 2006.257.16:03:44.96#ibcon#about to read 6, iclass 30, count 0 2006.257.16:03:44.96#ibcon#read 6, iclass 30, count 0 2006.257.16:03:44.96#ibcon#end of sib2, iclass 30, count 0 2006.257.16:03:44.96#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:03:44.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:03:44.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.16:03:44.96#ibcon#*before write, iclass 30, count 0 2006.257.16:03:44.96#ibcon#enter sib2, iclass 30, count 0 2006.257.16:03:44.96#ibcon#flushed, iclass 30, count 0 2006.257.16:03:44.96#ibcon#about to write, iclass 30, count 0 2006.257.16:03:44.96#ibcon#wrote, iclass 30, count 0 2006.257.16:03:44.96#ibcon#about to read 3, iclass 30, count 0 2006.257.16:03:45.00#ibcon#read 3, iclass 30, count 0 2006.257.16:03:45.00#ibcon#about to read 4, iclass 30, count 0 2006.257.16:03:45.00#ibcon#read 4, iclass 30, count 0 2006.257.16:03:45.00#ibcon#about to read 5, iclass 30, count 0 2006.257.16:03:45.00#ibcon#read 5, iclass 30, count 0 2006.257.16:03:45.00#ibcon#about to read 6, iclass 30, count 0 2006.257.16:03:45.00#ibcon#read 6, iclass 30, count 0 2006.257.16:03:45.00#ibcon#end of sib2, iclass 30, count 0 2006.257.16:03:45.00#ibcon#*after write, iclass 30, count 0 2006.257.16:03:45.00#ibcon#*before return 0, iclass 30, count 0 2006.257.16:03:45.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:03:45.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:03:45.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:03:45.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:03:45.00$vck44/va=6,4 2006.257.16:03:45.00#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.16:03:45.00#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.16:03:45.00#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:45.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:03:45.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:03:45.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:03:45.06#ibcon#enter wrdev, iclass 32, count 2 2006.257.16:03:45.06#ibcon#first serial, iclass 32, count 2 2006.257.16:03:45.06#ibcon#enter sib2, iclass 32, count 2 2006.257.16:03:45.06#ibcon#flushed, iclass 32, count 2 2006.257.16:03:45.06#ibcon#about to write, iclass 32, count 2 2006.257.16:03:45.06#ibcon#wrote, iclass 32, count 2 2006.257.16:03:45.06#ibcon#about to read 3, iclass 32, count 2 2006.257.16:03:45.08#ibcon#read 3, iclass 32, count 2 2006.257.16:03:45.08#ibcon#about to read 4, iclass 32, count 2 2006.257.16:03:45.08#ibcon#read 4, iclass 32, count 2 2006.257.16:03:45.08#ibcon#about to read 5, iclass 32, count 2 2006.257.16:03:45.08#ibcon#read 5, iclass 32, count 2 2006.257.16:03:45.08#ibcon#about to read 6, iclass 32, count 2 2006.257.16:03:45.08#ibcon#read 6, iclass 32, count 2 2006.257.16:03:45.08#ibcon#end of sib2, iclass 32, count 2 2006.257.16:03:45.08#ibcon#*mode == 0, iclass 32, count 2 2006.257.16:03:45.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.16:03:45.08#ibcon#[25=AT06-04\r\n] 2006.257.16:03:45.08#ibcon#*before write, iclass 32, count 2 2006.257.16:03:45.08#ibcon#enter sib2, iclass 32, count 2 2006.257.16:03:45.08#ibcon#flushed, iclass 32, count 2 2006.257.16:03:45.08#ibcon#about to write, iclass 32, count 2 2006.257.16:03:45.08#ibcon#wrote, iclass 32, count 2 2006.257.16:03:45.08#ibcon#about to read 3, iclass 32, count 2 2006.257.16:03:45.11#ibcon#read 3, iclass 32, count 2 2006.257.16:03:45.11#ibcon#about to read 4, iclass 32, count 2 2006.257.16:03:45.11#ibcon#read 4, iclass 32, count 2 2006.257.16:03:45.11#ibcon#about to read 5, iclass 32, count 2 2006.257.16:03:45.11#ibcon#read 5, iclass 32, count 2 2006.257.16:03:45.11#ibcon#about to read 6, iclass 32, count 2 2006.257.16:03:45.11#ibcon#read 6, iclass 32, count 2 2006.257.16:03:45.11#ibcon#end of sib2, iclass 32, count 2 2006.257.16:03:45.11#ibcon#*after write, iclass 32, count 2 2006.257.16:03:45.11#ibcon#*before return 0, iclass 32, count 2 2006.257.16:03:45.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:03:45.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:03:45.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.16:03:45.11#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:45.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:03:45.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:03:45.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:03:45.23#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:03:45.23#ibcon#first serial, iclass 32, count 0 2006.257.16:03:45.23#ibcon#enter sib2, iclass 32, count 0 2006.257.16:03:45.23#ibcon#flushed, iclass 32, count 0 2006.257.16:03:45.23#ibcon#about to write, iclass 32, count 0 2006.257.16:03:45.23#ibcon#wrote, iclass 32, count 0 2006.257.16:03:45.23#ibcon#about to read 3, iclass 32, count 0 2006.257.16:03:45.25#ibcon#read 3, iclass 32, count 0 2006.257.16:03:45.25#ibcon#about to read 4, iclass 32, count 0 2006.257.16:03:45.25#ibcon#read 4, iclass 32, count 0 2006.257.16:03:45.25#ibcon#about to read 5, iclass 32, count 0 2006.257.16:03:45.25#ibcon#read 5, iclass 32, count 0 2006.257.16:03:45.25#ibcon#about to read 6, iclass 32, count 0 2006.257.16:03:45.25#ibcon#read 6, iclass 32, count 0 2006.257.16:03:45.25#ibcon#end of sib2, iclass 32, count 0 2006.257.16:03:45.25#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:03:45.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:03:45.25#ibcon#[25=USB\r\n] 2006.257.16:03:45.25#ibcon#*before write, iclass 32, count 0 2006.257.16:03:45.25#ibcon#enter sib2, iclass 32, count 0 2006.257.16:03:45.25#ibcon#flushed, iclass 32, count 0 2006.257.16:03:45.25#ibcon#about to write, iclass 32, count 0 2006.257.16:03:45.25#ibcon#wrote, iclass 32, count 0 2006.257.16:03:45.25#ibcon#about to read 3, iclass 32, count 0 2006.257.16:03:45.28#ibcon#read 3, iclass 32, count 0 2006.257.16:03:45.28#ibcon#about to read 4, iclass 32, count 0 2006.257.16:03:45.28#ibcon#read 4, iclass 32, count 0 2006.257.16:03:45.28#ibcon#about to read 5, iclass 32, count 0 2006.257.16:03:45.28#ibcon#read 5, iclass 32, count 0 2006.257.16:03:45.28#ibcon#about to read 6, iclass 32, count 0 2006.257.16:03:45.28#ibcon#read 6, iclass 32, count 0 2006.257.16:03:45.28#ibcon#end of sib2, iclass 32, count 0 2006.257.16:03:45.28#ibcon#*after write, iclass 32, count 0 2006.257.16:03:45.28#ibcon#*before return 0, iclass 32, count 0 2006.257.16:03:45.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:03:45.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:03:45.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:03:45.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:03:45.28$vck44/valo=7,864.99 2006.257.16:03:45.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.16:03:45.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.16:03:45.28#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:45.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:45.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:45.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:45.28#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:03:45.28#ibcon#first serial, iclass 34, count 0 2006.257.16:03:45.28#ibcon#enter sib2, iclass 34, count 0 2006.257.16:03:45.28#ibcon#flushed, iclass 34, count 0 2006.257.16:03:45.28#ibcon#about to write, iclass 34, count 0 2006.257.16:03:45.28#ibcon#wrote, iclass 34, count 0 2006.257.16:03:45.28#ibcon#about to read 3, iclass 34, count 0 2006.257.16:03:45.30#ibcon#read 3, iclass 34, count 0 2006.257.16:03:45.30#ibcon#about to read 4, iclass 34, count 0 2006.257.16:03:45.30#ibcon#read 4, iclass 34, count 0 2006.257.16:03:45.30#ibcon#about to read 5, iclass 34, count 0 2006.257.16:03:45.30#ibcon#read 5, iclass 34, count 0 2006.257.16:03:45.30#ibcon#about to read 6, iclass 34, count 0 2006.257.16:03:45.30#ibcon#read 6, iclass 34, count 0 2006.257.16:03:45.30#ibcon#end of sib2, iclass 34, count 0 2006.257.16:03:45.30#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:03:45.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:03:45.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.16:03:45.30#ibcon#*before write, iclass 34, count 0 2006.257.16:03:45.30#ibcon#enter sib2, iclass 34, count 0 2006.257.16:03:45.30#ibcon#flushed, iclass 34, count 0 2006.257.16:03:45.30#ibcon#about to write, iclass 34, count 0 2006.257.16:03:45.30#ibcon#wrote, iclass 34, count 0 2006.257.16:03:45.30#ibcon#about to read 3, iclass 34, count 0 2006.257.16:03:45.34#ibcon#read 3, iclass 34, count 0 2006.257.16:03:45.34#ibcon#about to read 4, iclass 34, count 0 2006.257.16:03:45.34#ibcon#read 4, iclass 34, count 0 2006.257.16:03:45.34#ibcon#about to read 5, iclass 34, count 0 2006.257.16:03:45.34#ibcon#read 5, iclass 34, count 0 2006.257.16:03:45.34#ibcon#about to read 6, iclass 34, count 0 2006.257.16:03:45.34#ibcon#read 6, iclass 34, count 0 2006.257.16:03:45.34#ibcon#end of sib2, iclass 34, count 0 2006.257.16:03:45.34#ibcon#*after write, iclass 34, count 0 2006.257.16:03:45.34#ibcon#*before return 0, iclass 34, count 0 2006.257.16:03:45.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:45.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:45.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:03:45.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:03:45.34$vck44/va=7,4 2006.257.16:03:45.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.16:03:45.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.16:03:45.34#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:45.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:45.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:45.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:45.40#ibcon#enter wrdev, iclass 36, count 2 2006.257.16:03:45.40#ibcon#first serial, iclass 36, count 2 2006.257.16:03:45.40#ibcon#enter sib2, iclass 36, count 2 2006.257.16:03:45.40#ibcon#flushed, iclass 36, count 2 2006.257.16:03:45.40#ibcon#about to write, iclass 36, count 2 2006.257.16:03:45.40#ibcon#wrote, iclass 36, count 2 2006.257.16:03:45.40#ibcon#about to read 3, iclass 36, count 2 2006.257.16:03:45.42#ibcon#read 3, iclass 36, count 2 2006.257.16:03:45.42#ibcon#about to read 4, iclass 36, count 2 2006.257.16:03:45.42#ibcon#read 4, iclass 36, count 2 2006.257.16:03:45.42#ibcon#about to read 5, iclass 36, count 2 2006.257.16:03:45.42#ibcon#read 5, iclass 36, count 2 2006.257.16:03:45.42#ibcon#about to read 6, iclass 36, count 2 2006.257.16:03:45.42#ibcon#read 6, iclass 36, count 2 2006.257.16:03:45.42#ibcon#end of sib2, iclass 36, count 2 2006.257.16:03:45.42#ibcon#*mode == 0, iclass 36, count 2 2006.257.16:03:45.42#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.16:03:45.42#ibcon#[25=AT07-04\r\n] 2006.257.16:03:45.42#ibcon#*before write, iclass 36, count 2 2006.257.16:03:45.42#ibcon#enter sib2, iclass 36, count 2 2006.257.16:03:45.42#ibcon#flushed, iclass 36, count 2 2006.257.16:03:45.42#ibcon#about to write, iclass 36, count 2 2006.257.16:03:45.42#ibcon#wrote, iclass 36, count 2 2006.257.16:03:45.42#ibcon#about to read 3, iclass 36, count 2 2006.257.16:03:45.45#ibcon#read 3, iclass 36, count 2 2006.257.16:03:45.45#ibcon#about to read 4, iclass 36, count 2 2006.257.16:03:45.45#ibcon#read 4, iclass 36, count 2 2006.257.16:03:45.45#ibcon#about to read 5, iclass 36, count 2 2006.257.16:03:45.45#ibcon#read 5, iclass 36, count 2 2006.257.16:03:45.45#ibcon#about to read 6, iclass 36, count 2 2006.257.16:03:45.45#ibcon#read 6, iclass 36, count 2 2006.257.16:03:45.45#ibcon#end of sib2, iclass 36, count 2 2006.257.16:03:45.45#ibcon#*after write, iclass 36, count 2 2006.257.16:03:45.45#ibcon#*before return 0, iclass 36, count 2 2006.257.16:03:45.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:45.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:45.50#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.16:03:45.50#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:45.50#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:45.62#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:45.62#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:45.62#ibcon#enter wrdev, iclass 36, count 0 2006.257.16:03:45.62#ibcon#first serial, iclass 36, count 0 2006.257.16:03:45.62#ibcon#enter sib2, iclass 36, count 0 2006.257.16:03:45.62#ibcon#flushed, iclass 36, count 0 2006.257.16:03:45.62#ibcon#about to write, iclass 36, count 0 2006.257.16:03:45.62#ibcon#wrote, iclass 36, count 0 2006.257.16:03:45.62#ibcon#about to read 3, iclass 36, count 0 2006.257.16:03:45.64#ibcon#read 3, iclass 36, count 0 2006.257.16:03:45.64#ibcon#about to read 4, iclass 36, count 0 2006.257.16:03:45.64#ibcon#read 4, iclass 36, count 0 2006.257.16:03:45.64#ibcon#about to read 5, iclass 36, count 0 2006.257.16:03:45.64#ibcon#read 5, iclass 36, count 0 2006.257.16:03:45.64#ibcon#about to read 6, iclass 36, count 0 2006.257.16:03:45.64#ibcon#read 6, iclass 36, count 0 2006.257.16:03:45.64#ibcon#end of sib2, iclass 36, count 0 2006.257.16:03:45.64#ibcon#*mode == 0, iclass 36, count 0 2006.257.16:03:45.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.16:03:45.64#ibcon#[25=USB\r\n] 2006.257.16:03:45.64#ibcon#*before write, iclass 36, count 0 2006.257.16:03:45.64#ibcon#enter sib2, iclass 36, count 0 2006.257.16:03:45.64#ibcon#flushed, iclass 36, count 0 2006.257.16:03:45.64#ibcon#about to write, iclass 36, count 0 2006.257.16:03:45.64#ibcon#wrote, iclass 36, count 0 2006.257.16:03:45.64#ibcon#about to read 3, iclass 36, count 0 2006.257.16:03:45.67#ibcon#read 3, iclass 36, count 0 2006.257.16:03:45.67#ibcon#about to read 4, iclass 36, count 0 2006.257.16:03:45.67#ibcon#read 4, iclass 36, count 0 2006.257.16:03:45.67#ibcon#about to read 5, iclass 36, count 0 2006.257.16:03:45.67#ibcon#read 5, iclass 36, count 0 2006.257.16:03:45.67#ibcon#about to read 6, iclass 36, count 0 2006.257.16:03:45.67#ibcon#read 6, iclass 36, count 0 2006.257.16:03:45.67#ibcon#end of sib2, iclass 36, count 0 2006.257.16:03:45.67#ibcon#*after write, iclass 36, count 0 2006.257.16:03:45.67#ibcon#*before return 0, iclass 36, count 0 2006.257.16:03:45.67#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:45.67#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:45.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.16:03:45.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.16:03:45.67$vck44/valo=8,884.99 2006.257.16:03:45.67#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.16:03:45.67#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.16:03:45.67#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:45.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:45.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:45.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:45.67#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:03:45.67#ibcon#first serial, iclass 38, count 0 2006.257.16:03:45.67#ibcon#enter sib2, iclass 38, count 0 2006.257.16:03:45.67#ibcon#flushed, iclass 38, count 0 2006.257.16:03:45.67#ibcon#about to write, iclass 38, count 0 2006.257.16:03:45.67#ibcon#wrote, iclass 38, count 0 2006.257.16:03:45.67#ibcon#about to read 3, iclass 38, count 0 2006.257.16:03:45.69#ibcon#read 3, iclass 38, count 0 2006.257.16:03:45.69#ibcon#about to read 4, iclass 38, count 0 2006.257.16:03:45.69#ibcon#read 4, iclass 38, count 0 2006.257.16:03:45.69#ibcon#about to read 5, iclass 38, count 0 2006.257.16:03:45.69#ibcon#read 5, iclass 38, count 0 2006.257.16:03:45.69#ibcon#about to read 6, iclass 38, count 0 2006.257.16:03:45.69#ibcon#read 6, iclass 38, count 0 2006.257.16:03:45.69#ibcon#end of sib2, iclass 38, count 0 2006.257.16:03:45.69#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:03:45.69#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:03:45.69#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.16:03:45.69#ibcon#*before write, iclass 38, count 0 2006.257.16:03:45.69#ibcon#enter sib2, iclass 38, count 0 2006.257.16:03:45.69#ibcon#flushed, iclass 38, count 0 2006.257.16:03:45.69#ibcon#about to write, iclass 38, count 0 2006.257.16:03:45.69#ibcon#wrote, iclass 38, count 0 2006.257.16:03:45.69#ibcon#about to read 3, iclass 38, count 0 2006.257.16:03:45.73#ibcon#read 3, iclass 38, count 0 2006.257.16:03:45.73#ibcon#about to read 4, iclass 38, count 0 2006.257.16:03:45.73#ibcon#read 4, iclass 38, count 0 2006.257.16:03:45.73#ibcon#about to read 5, iclass 38, count 0 2006.257.16:03:45.73#ibcon#read 5, iclass 38, count 0 2006.257.16:03:45.73#ibcon#about to read 6, iclass 38, count 0 2006.257.16:03:45.73#ibcon#read 6, iclass 38, count 0 2006.257.16:03:45.73#ibcon#end of sib2, iclass 38, count 0 2006.257.16:03:45.73#ibcon#*after write, iclass 38, count 0 2006.257.16:03:45.73#ibcon#*before return 0, iclass 38, count 0 2006.257.16:03:45.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:45.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:45.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:03:45.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:03:45.73$vck44/va=8,4 2006.257.16:03:45.73#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.16:03:45.73#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.16:03:45.73#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:45.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:45.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:45.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:45.79#ibcon#enter wrdev, iclass 40, count 2 2006.257.16:03:45.79#ibcon#first serial, iclass 40, count 2 2006.257.16:03:45.79#ibcon#enter sib2, iclass 40, count 2 2006.257.16:03:45.79#ibcon#flushed, iclass 40, count 2 2006.257.16:03:45.79#ibcon#about to write, iclass 40, count 2 2006.257.16:03:45.79#ibcon#wrote, iclass 40, count 2 2006.257.16:03:45.79#ibcon#about to read 3, iclass 40, count 2 2006.257.16:03:45.81#ibcon#read 3, iclass 40, count 2 2006.257.16:03:45.81#ibcon#about to read 4, iclass 40, count 2 2006.257.16:03:45.81#ibcon#read 4, iclass 40, count 2 2006.257.16:03:45.81#ibcon#about to read 5, iclass 40, count 2 2006.257.16:03:45.81#ibcon#read 5, iclass 40, count 2 2006.257.16:03:45.81#ibcon#about to read 6, iclass 40, count 2 2006.257.16:03:45.81#ibcon#read 6, iclass 40, count 2 2006.257.16:03:45.81#ibcon#end of sib2, iclass 40, count 2 2006.257.16:03:45.81#ibcon#*mode == 0, iclass 40, count 2 2006.257.16:03:45.81#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.16:03:45.81#ibcon#[25=AT08-04\r\n] 2006.257.16:03:45.81#ibcon#*before write, iclass 40, count 2 2006.257.16:03:45.81#ibcon#enter sib2, iclass 40, count 2 2006.257.16:03:45.81#ibcon#flushed, iclass 40, count 2 2006.257.16:03:45.81#ibcon#about to write, iclass 40, count 2 2006.257.16:03:45.81#ibcon#wrote, iclass 40, count 2 2006.257.16:03:45.81#ibcon#about to read 3, iclass 40, count 2 2006.257.16:03:45.84#ibcon#read 3, iclass 40, count 2 2006.257.16:03:45.84#ibcon#about to read 4, iclass 40, count 2 2006.257.16:03:45.84#ibcon#read 4, iclass 40, count 2 2006.257.16:03:45.84#ibcon#about to read 5, iclass 40, count 2 2006.257.16:03:45.84#ibcon#read 5, iclass 40, count 2 2006.257.16:03:45.84#ibcon#about to read 6, iclass 40, count 2 2006.257.16:03:45.84#ibcon#read 6, iclass 40, count 2 2006.257.16:03:45.84#ibcon#end of sib2, iclass 40, count 2 2006.257.16:03:45.84#ibcon#*after write, iclass 40, count 2 2006.257.16:03:45.84#ibcon#*before return 0, iclass 40, count 2 2006.257.16:03:45.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:45.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:45.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.16:03:45.84#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:45.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:45.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:45.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:45.96#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:03:45.96#ibcon#first serial, iclass 40, count 0 2006.257.16:03:45.96#ibcon#enter sib2, iclass 40, count 0 2006.257.16:03:45.96#ibcon#flushed, iclass 40, count 0 2006.257.16:03:45.96#ibcon#about to write, iclass 40, count 0 2006.257.16:03:45.96#ibcon#wrote, iclass 40, count 0 2006.257.16:03:45.96#ibcon#about to read 3, iclass 40, count 0 2006.257.16:03:45.98#ibcon#read 3, iclass 40, count 0 2006.257.16:03:45.98#ibcon#about to read 4, iclass 40, count 0 2006.257.16:03:45.98#ibcon#read 4, iclass 40, count 0 2006.257.16:03:45.98#ibcon#about to read 5, iclass 40, count 0 2006.257.16:03:45.98#ibcon#read 5, iclass 40, count 0 2006.257.16:03:45.98#ibcon#about to read 6, iclass 40, count 0 2006.257.16:03:45.98#ibcon#read 6, iclass 40, count 0 2006.257.16:03:45.98#ibcon#end of sib2, iclass 40, count 0 2006.257.16:03:45.98#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:03:45.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:03:45.98#ibcon#[25=USB\r\n] 2006.257.16:03:45.98#ibcon#*before write, iclass 40, count 0 2006.257.16:03:45.98#ibcon#enter sib2, iclass 40, count 0 2006.257.16:03:45.98#ibcon#flushed, iclass 40, count 0 2006.257.16:03:45.98#ibcon#about to write, iclass 40, count 0 2006.257.16:03:45.98#ibcon#wrote, iclass 40, count 0 2006.257.16:03:45.98#ibcon#about to read 3, iclass 40, count 0 2006.257.16:03:46.01#ibcon#read 3, iclass 40, count 0 2006.257.16:03:46.01#ibcon#about to read 4, iclass 40, count 0 2006.257.16:03:46.01#ibcon#read 4, iclass 40, count 0 2006.257.16:03:46.01#ibcon#about to read 5, iclass 40, count 0 2006.257.16:03:46.01#ibcon#read 5, iclass 40, count 0 2006.257.16:03:46.01#ibcon#about to read 6, iclass 40, count 0 2006.257.16:03:46.01#ibcon#read 6, iclass 40, count 0 2006.257.16:03:46.01#ibcon#end of sib2, iclass 40, count 0 2006.257.16:03:46.01#ibcon#*after write, iclass 40, count 0 2006.257.16:03:46.01#ibcon#*before return 0, iclass 40, count 0 2006.257.16:03:46.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:46.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:46.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:03:46.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:03:46.01$vck44/vblo=1,629.99 2006.257.16:03:46.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.16:03:46.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.16:03:46.01#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:46.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:46.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:46.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:46.01#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:03:46.01#ibcon#first serial, iclass 4, count 0 2006.257.16:03:46.01#ibcon#enter sib2, iclass 4, count 0 2006.257.16:03:46.01#ibcon#flushed, iclass 4, count 0 2006.257.16:03:46.01#ibcon#about to write, iclass 4, count 0 2006.257.16:03:46.01#ibcon#wrote, iclass 4, count 0 2006.257.16:03:46.01#ibcon#about to read 3, iclass 4, count 0 2006.257.16:03:46.03#ibcon#read 3, iclass 4, count 0 2006.257.16:03:46.03#ibcon#about to read 4, iclass 4, count 0 2006.257.16:03:46.03#ibcon#read 4, iclass 4, count 0 2006.257.16:03:46.03#ibcon#about to read 5, iclass 4, count 0 2006.257.16:03:46.03#ibcon#read 5, iclass 4, count 0 2006.257.16:03:46.03#ibcon#about to read 6, iclass 4, count 0 2006.257.16:03:46.03#ibcon#read 6, iclass 4, count 0 2006.257.16:03:46.03#ibcon#end of sib2, iclass 4, count 0 2006.257.16:03:46.03#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:03:46.03#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:03:46.03#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.16:03:46.03#ibcon#*before write, iclass 4, count 0 2006.257.16:03:46.03#ibcon#enter sib2, iclass 4, count 0 2006.257.16:03:46.03#ibcon#flushed, iclass 4, count 0 2006.257.16:03:46.03#ibcon#about to write, iclass 4, count 0 2006.257.16:03:46.03#ibcon#wrote, iclass 4, count 0 2006.257.16:03:46.03#ibcon#about to read 3, iclass 4, count 0 2006.257.16:03:46.07#ibcon#read 3, iclass 4, count 0 2006.257.16:03:46.07#ibcon#about to read 4, iclass 4, count 0 2006.257.16:03:46.07#ibcon#read 4, iclass 4, count 0 2006.257.16:03:46.07#ibcon#about to read 5, iclass 4, count 0 2006.257.16:03:46.07#ibcon#read 5, iclass 4, count 0 2006.257.16:03:46.07#ibcon#about to read 6, iclass 4, count 0 2006.257.16:03:46.07#ibcon#read 6, iclass 4, count 0 2006.257.16:03:46.07#ibcon#end of sib2, iclass 4, count 0 2006.257.16:03:46.07#ibcon#*after write, iclass 4, count 0 2006.257.16:03:46.07#ibcon#*before return 0, iclass 4, count 0 2006.257.16:03:46.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:46.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:46.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:03:46.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:03:46.07$vck44/vb=1,4 2006.257.16:03:46.07#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.16:03:46.07#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.16:03:46.07#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:46.07#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:03:46.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:03:46.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:03:46.07#ibcon#enter wrdev, iclass 6, count 2 2006.257.16:03:46.07#ibcon#first serial, iclass 6, count 2 2006.257.16:03:46.07#ibcon#enter sib2, iclass 6, count 2 2006.257.16:03:46.07#ibcon#flushed, iclass 6, count 2 2006.257.16:03:46.07#ibcon#about to write, iclass 6, count 2 2006.257.16:03:46.07#ibcon#wrote, iclass 6, count 2 2006.257.16:03:46.07#ibcon#about to read 3, iclass 6, count 2 2006.257.16:03:46.09#ibcon#read 3, iclass 6, count 2 2006.257.16:03:46.09#ibcon#about to read 4, iclass 6, count 2 2006.257.16:03:46.09#ibcon#read 4, iclass 6, count 2 2006.257.16:03:46.09#ibcon#about to read 5, iclass 6, count 2 2006.257.16:03:46.09#ibcon#read 5, iclass 6, count 2 2006.257.16:03:46.09#ibcon#about to read 6, iclass 6, count 2 2006.257.16:03:46.09#ibcon#read 6, iclass 6, count 2 2006.257.16:03:46.09#ibcon#end of sib2, iclass 6, count 2 2006.257.16:03:46.09#ibcon#*mode == 0, iclass 6, count 2 2006.257.16:03:46.09#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.16:03:46.09#ibcon#[27=AT01-04\r\n] 2006.257.16:03:46.09#ibcon#*before write, iclass 6, count 2 2006.257.16:03:46.09#ibcon#enter sib2, iclass 6, count 2 2006.257.16:03:46.09#ibcon#flushed, iclass 6, count 2 2006.257.16:03:46.09#ibcon#about to write, iclass 6, count 2 2006.257.16:03:46.09#ibcon#wrote, iclass 6, count 2 2006.257.16:03:46.09#ibcon#about to read 3, iclass 6, count 2 2006.257.16:03:46.12#ibcon#read 3, iclass 6, count 2 2006.257.16:03:46.12#ibcon#about to read 4, iclass 6, count 2 2006.257.16:03:46.12#ibcon#read 4, iclass 6, count 2 2006.257.16:03:46.12#ibcon#about to read 5, iclass 6, count 2 2006.257.16:03:46.12#ibcon#read 5, iclass 6, count 2 2006.257.16:03:46.12#ibcon#about to read 6, iclass 6, count 2 2006.257.16:03:46.12#ibcon#read 6, iclass 6, count 2 2006.257.16:03:46.12#ibcon#end of sib2, iclass 6, count 2 2006.257.16:03:46.12#ibcon#*after write, iclass 6, count 2 2006.257.16:03:46.12#ibcon#*before return 0, iclass 6, count 2 2006.257.16:03:46.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:03:46.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:03:46.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.16:03:46.12#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:46.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:03:46.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:03:46.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:03:46.24#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:03:46.24#ibcon#first serial, iclass 6, count 0 2006.257.16:03:46.24#ibcon#enter sib2, iclass 6, count 0 2006.257.16:03:46.24#ibcon#flushed, iclass 6, count 0 2006.257.16:03:46.24#ibcon#about to write, iclass 6, count 0 2006.257.16:03:46.24#ibcon#wrote, iclass 6, count 0 2006.257.16:03:46.24#ibcon#about to read 3, iclass 6, count 0 2006.257.16:03:46.26#ibcon#read 3, iclass 6, count 0 2006.257.16:03:46.26#ibcon#about to read 4, iclass 6, count 0 2006.257.16:03:46.26#ibcon#read 4, iclass 6, count 0 2006.257.16:03:46.26#ibcon#about to read 5, iclass 6, count 0 2006.257.16:03:46.26#ibcon#read 5, iclass 6, count 0 2006.257.16:03:46.26#ibcon#about to read 6, iclass 6, count 0 2006.257.16:03:46.26#ibcon#read 6, iclass 6, count 0 2006.257.16:03:46.26#ibcon#end of sib2, iclass 6, count 0 2006.257.16:03:46.26#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:03:46.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:03:46.26#ibcon#[27=USB\r\n] 2006.257.16:03:46.26#ibcon#*before write, iclass 6, count 0 2006.257.16:03:46.26#ibcon#enter sib2, iclass 6, count 0 2006.257.16:03:46.26#ibcon#flushed, iclass 6, count 0 2006.257.16:03:46.26#ibcon#about to write, iclass 6, count 0 2006.257.16:03:46.26#ibcon#wrote, iclass 6, count 0 2006.257.16:03:46.26#ibcon#about to read 3, iclass 6, count 0 2006.257.16:03:46.29#ibcon#read 3, iclass 6, count 0 2006.257.16:03:46.29#ibcon#about to read 4, iclass 6, count 0 2006.257.16:03:46.29#ibcon#read 4, iclass 6, count 0 2006.257.16:03:46.29#ibcon#about to read 5, iclass 6, count 0 2006.257.16:03:46.29#ibcon#read 5, iclass 6, count 0 2006.257.16:03:46.29#ibcon#about to read 6, iclass 6, count 0 2006.257.16:03:46.29#ibcon#read 6, iclass 6, count 0 2006.257.16:03:46.29#ibcon#end of sib2, iclass 6, count 0 2006.257.16:03:46.29#ibcon#*after write, iclass 6, count 0 2006.257.16:03:46.29#ibcon#*before return 0, iclass 6, count 0 2006.257.16:03:46.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:03:46.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:03:46.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:03:46.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:03:46.29$vck44/vblo=2,634.99 2006.257.16:03:46.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.16:03:46.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.16:03:46.29#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:46.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:46.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:46.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:46.29#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:03:46.29#ibcon#first serial, iclass 10, count 0 2006.257.16:03:46.29#ibcon#enter sib2, iclass 10, count 0 2006.257.16:03:46.29#ibcon#flushed, iclass 10, count 0 2006.257.16:03:46.29#ibcon#about to write, iclass 10, count 0 2006.257.16:03:46.29#ibcon#wrote, iclass 10, count 0 2006.257.16:03:46.29#ibcon#about to read 3, iclass 10, count 0 2006.257.16:03:46.31#ibcon#read 3, iclass 10, count 0 2006.257.16:03:46.31#ibcon#about to read 4, iclass 10, count 0 2006.257.16:03:46.31#ibcon#read 4, iclass 10, count 0 2006.257.16:03:46.31#ibcon#about to read 5, iclass 10, count 0 2006.257.16:03:46.31#ibcon#read 5, iclass 10, count 0 2006.257.16:03:46.31#ibcon#about to read 6, iclass 10, count 0 2006.257.16:03:46.31#ibcon#read 6, iclass 10, count 0 2006.257.16:03:46.31#ibcon#end of sib2, iclass 10, count 0 2006.257.16:03:46.31#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:03:46.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:03:46.31#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.16:03:46.31#ibcon#*before write, iclass 10, count 0 2006.257.16:03:46.31#ibcon#enter sib2, iclass 10, count 0 2006.257.16:03:46.31#ibcon#flushed, iclass 10, count 0 2006.257.16:03:46.31#ibcon#about to write, iclass 10, count 0 2006.257.16:03:46.31#ibcon#wrote, iclass 10, count 0 2006.257.16:03:46.31#ibcon#about to read 3, iclass 10, count 0 2006.257.16:03:46.35#ibcon#read 3, iclass 10, count 0 2006.257.16:03:46.35#ibcon#about to read 4, iclass 10, count 0 2006.257.16:03:46.35#ibcon#read 4, iclass 10, count 0 2006.257.16:03:46.35#ibcon#about to read 5, iclass 10, count 0 2006.257.16:03:46.35#ibcon#read 5, iclass 10, count 0 2006.257.16:03:46.35#ibcon#about to read 6, iclass 10, count 0 2006.257.16:03:46.35#ibcon#read 6, iclass 10, count 0 2006.257.16:03:46.35#ibcon#end of sib2, iclass 10, count 0 2006.257.16:03:46.35#ibcon#*after write, iclass 10, count 0 2006.257.16:03:46.35#ibcon#*before return 0, iclass 10, count 0 2006.257.16:03:46.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:46.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:03:46.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:03:46.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:03:46.35$vck44/vb=2,5 2006.257.16:03:46.35#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.16:03:46.35#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.16:03:46.35#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:46.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:46.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:46.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:46.41#ibcon#enter wrdev, iclass 12, count 2 2006.257.16:03:46.41#ibcon#first serial, iclass 12, count 2 2006.257.16:03:46.41#ibcon#enter sib2, iclass 12, count 2 2006.257.16:03:46.41#ibcon#flushed, iclass 12, count 2 2006.257.16:03:46.41#ibcon#about to write, iclass 12, count 2 2006.257.16:03:46.41#ibcon#wrote, iclass 12, count 2 2006.257.16:03:46.41#ibcon#about to read 3, iclass 12, count 2 2006.257.16:03:46.43#ibcon#read 3, iclass 12, count 2 2006.257.16:03:46.43#ibcon#about to read 4, iclass 12, count 2 2006.257.16:03:46.43#ibcon#read 4, iclass 12, count 2 2006.257.16:03:46.43#ibcon#about to read 5, iclass 12, count 2 2006.257.16:03:46.43#ibcon#read 5, iclass 12, count 2 2006.257.16:03:46.43#ibcon#about to read 6, iclass 12, count 2 2006.257.16:03:46.43#ibcon#read 6, iclass 12, count 2 2006.257.16:03:46.43#ibcon#end of sib2, iclass 12, count 2 2006.257.16:03:46.43#ibcon#*mode == 0, iclass 12, count 2 2006.257.16:03:46.43#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.16:03:46.43#ibcon#[27=AT02-05\r\n] 2006.257.16:03:46.43#ibcon#*before write, iclass 12, count 2 2006.257.16:03:46.43#ibcon#enter sib2, iclass 12, count 2 2006.257.16:03:46.43#ibcon#flushed, iclass 12, count 2 2006.257.16:03:46.43#ibcon#about to write, iclass 12, count 2 2006.257.16:03:46.43#ibcon#wrote, iclass 12, count 2 2006.257.16:03:46.43#ibcon#about to read 3, iclass 12, count 2 2006.257.16:03:46.46#ibcon#read 3, iclass 12, count 2 2006.257.16:03:46.46#ibcon#about to read 4, iclass 12, count 2 2006.257.16:03:46.46#ibcon#read 4, iclass 12, count 2 2006.257.16:03:46.46#ibcon#about to read 5, iclass 12, count 2 2006.257.16:03:46.46#ibcon#read 5, iclass 12, count 2 2006.257.16:03:46.46#ibcon#about to read 6, iclass 12, count 2 2006.257.16:03:46.46#ibcon#read 6, iclass 12, count 2 2006.257.16:03:46.46#ibcon#end of sib2, iclass 12, count 2 2006.257.16:03:46.46#ibcon#*after write, iclass 12, count 2 2006.257.16:03:46.46#ibcon#*before return 0, iclass 12, count 2 2006.257.16:03:46.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:46.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:03:46.46#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.16:03:46.46#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:46.46#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:46.58#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:46.58#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:46.58#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:03:46.58#ibcon#first serial, iclass 12, count 0 2006.257.16:03:46.58#ibcon#enter sib2, iclass 12, count 0 2006.257.16:03:46.58#ibcon#flushed, iclass 12, count 0 2006.257.16:03:46.58#ibcon#about to write, iclass 12, count 0 2006.257.16:03:46.58#ibcon#wrote, iclass 12, count 0 2006.257.16:03:46.58#ibcon#about to read 3, iclass 12, count 0 2006.257.16:03:46.60#ibcon#read 3, iclass 12, count 0 2006.257.16:03:46.60#ibcon#about to read 4, iclass 12, count 0 2006.257.16:03:46.60#ibcon#read 4, iclass 12, count 0 2006.257.16:03:46.60#ibcon#about to read 5, iclass 12, count 0 2006.257.16:03:46.60#ibcon#read 5, iclass 12, count 0 2006.257.16:03:46.60#ibcon#about to read 6, iclass 12, count 0 2006.257.16:03:46.60#ibcon#read 6, iclass 12, count 0 2006.257.16:03:46.60#ibcon#end of sib2, iclass 12, count 0 2006.257.16:03:46.60#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:03:46.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:03:46.60#ibcon#[27=USB\r\n] 2006.257.16:03:46.60#ibcon#*before write, iclass 12, count 0 2006.257.16:03:46.60#ibcon#enter sib2, iclass 12, count 0 2006.257.16:03:46.60#ibcon#flushed, iclass 12, count 0 2006.257.16:03:46.60#ibcon#about to write, iclass 12, count 0 2006.257.16:03:46.60#ibcon#wrote, iclass 12, count 0 2006.257.16:03:46.60#ibcon#about to read 3, iclass 12, count 0 2006.257.16:03:46.63#ibcon#read 3, iclass 12, count 0 2006.257.16:03:46.63#ibcon#about to read 4, iclass 12, count 0 2006.257.16:03:46.63#ibcon#read 4, iclass 12, count 0 2006.257.16:03:46.63#ibcon#about to read 5, iclass 12, count 0 2006.257.16:03:46.63#ibcon#read 5, iclass 12, count 0 2006.257.16:03:46.63#ibcon#about to read 6, iclass 12, count 0 2006.257.16:03:46.63#ibcon#read 6, iclass 12, count 0 2006.257.16:03:46.63#ibcon#end of sib2, iclass 12, count 0 2006.257.16:03:46.63#ibcon#*after write, iclass 12, count 0 2006.257.16:03:46.63#ibcon#*before return 0, iclass 12, count 0 2006.257.16:03:46.63#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:46.63#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:03:46.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:03:46.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:03:46.63$vck44/vblo=3,649.99 2006.257.16:03:46.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.16:03:46.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.16:03:46.63#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:46.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:46.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:46.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:46.63#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:03:46.63#ibcon#first serial, iclass 14, count 0 2006.257.16:03:46.63#ibcon#enter sib2, iclass 14, count 0 2006.257.16:03:46.63#ibcon#flushed, iclass 14, count 0 2006.257.16:03:46.63#ibcon#about to write, iclass 14, count 0 2006.257.16:03:46.63#ibcon#wrote, iclass 14, count 0 2006.257.16:03:46.63#ibcon#about to read 3, iclass 14, count 0 2006.257.16:03:46.65#ibcon#read 3, iclass 14, count 0 2006.257.16:03:46.65#ibcon#about to read 4, iclass 14, count 0 2006.257.16:03:46.65#ibcon#read 4, iclass 14, count 0 2006.257.16:03:46.65#ibcon#about to read 5, iclass 14, count 0 2006.257.16:03:46.65#ibcon#read 5, iclass 14, count 0 2006.257.16:03:46.65#ibcon#about to read 6, iclass 14, count 0 2006.257.16:03:46.65#ibcon#read 6, iclass 14, count 0 2006.257.16:03:46.65#ibcon#end of sib2, iclass 14, count 0 2006.257.16:03:46.65#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:03:46.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:03:46.65#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.16:03:46.65#ibcon#*before write, iclass 14, count 0 2006.257.16:03:46.65#ibcon#enter sib2, iclass 14, count 0 2006.257.16:03:46.65#ibcon#flushed, iclass 14, count 0 2006.257.16:03:46.65#ibcon#about to write, iclass 14, count 0 2006.257.16:03:46.65#ibcon#wrote, iclass 14, count 0 2006.257.16:03:46.65#ibcon#about to read 3, iclass 14, count 0 2006.257.16:03:46.69#ibcon#read 3, iclass 14, count 0 2006.257.16:03:46.69#ibcon#about to read 4, iclass 14, count 0 2006.257.16:03:46.69#ibcon#read 4, iclass 14, count 0 2006.257.16:03:46.69#ibcon#about to read 5, iclass 14, count 0 2006.257.16:03:46.69#ibcon#read 5, iclass 14, count 0 2006.257.16:03:46.69#ibcon#about to read 6, iclass 14, count 0 2006.257.16:03:46.69#ibcon#read 6, iclass 14, count 0 2006.257.16:03:46.69#ibcon#end of sib2, iclass 14, count 0 2006.257.16:03:46.69#ibcon#*after write, iclass 14, count 0 2006.257.16:03:46.69#ibcon#*before return 0, iclass 14, count 0 2006.257.16:03:46.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:46.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:03:46.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:03:46.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:03:46.69$vck44/vb=3,4 2006.257.16:03:46.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.16:03:46.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.16:03:46.69#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:46.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:46.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:46.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:46.75#ibcon#enter wrdev, iclass 16, count 2 2006.257.16:03:46.75#ibcon#first serial, iclass 16, count 2 2006.257.16:03:46.75#ibcon#enter sib2, iclass 16, count 2 2006.257.16:03:46.75#ibcon#flushed, iclass 16, count 2 2006.257.16:03:46.75#ibcon#about to write, iclass 16, count 2 2006.257.16:03:46.75#ibcon#wrote, iclass 16, count 2 2006.257.16:03:46.75#ibcon#about to read 3, iclass 16, count 2 2006.257.16:03:46.77#ibcon#read 3, iclass 16, count 2 2006.257.16:03:46.77#ibcon#about to read 4, iclass 16, count 2 2006.257.16:03:46.77#ibcon#read 4, iclass 16, count 2 2006.257.16:03:46.77#ibcon#about to read 5, iclass 16, count 2 2006.257.16:03:46.77#ibcon#read 5, iclass 16, count 2 2006.257.16:03:46.77#ibcon#about to read 6, iclass 16, count 2 2006.257.16:03:46.77#ibcon#read 6, iclass 16, count 2 2006.257.16:03:46.77#ibcon#end of sib2, iclass 16, count 2 2006.257.16:03:46.77#ibcon#*mode == 0, iclass 16, count 2 2006.257.16:03:46.77#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.16:03:46.77#ibcon#[27=AT03-04\r\n] 2006.257.16:03:46.77#ibcon#*before write, iclass 16, count 2 2006.257.16:03:46.77#ibcon#enter sib2, iclass 16, count 2 2006.257.16:03:46.77#ibcon#flushed, iclass 16, count 2 2006.257.16:03:46.77#ibcon#about to write, iclass 16, count 2 2006.257.16:03:46.77#ibcon#wrote, iclass 16, count 2 2006.257.16:03:46.77#ibcon#about to read 3, iclass 16, count 2 2006.257.16:03:46.80#ibcon#read 3, iclass 16, count 2 2006.257.16:03:46.80#ibcon#about to read 4, iclass 16, count 2 2006.257.16:03:46.80#ibcon#read 4, iclass 16, count 2 2006.257.16:03:46.80#ibcon#about to read 5, iclass 16, count 2 2006.257.16:03:46.80#ibcon#read 5, iclass 16, count 2 2006.257.16:03:46.80#ibcon#about to read 6, iclass 16, count 2 2006.257.16:03:46.80#ibcon#read 6, iclass 16, count 2 2006.257.16:03:46.80#ibcon#end of sib2, iclass 16, count 2 2006.257.16:03:46.80#ibcon#*after write, iclass 16, count 2 2006.257.16:03:46.80#ibcon#*before return 0, iclass 16, count 2 2006.257.16:03:46.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:46.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:03:46.80#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.16:03:46.80#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:46.80#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:46.92#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:46.92#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:46.92#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:03:46.92#ibcon#first serial, iclass 16, count 0 2006.257.16:03:46.92#ibcon#enter sib2, iclass 16, count 0 2006.257.16:03:46.92#ibcon#flushed, iclass 16, count 0 2006.257.16:03:46.92#ibcon#about to write, iclass 16, count 0 2006.257.16:03:46.92#ibcon#wrote, iclass 16, count 0 2006.257.16:03:46.92#ibcon#about to read 3, iclass 16, count 0 2006.257.16:03:46.94#ibcon#read 3, iclass 16, count 0 2006.257.16:03:46.94#ibcon#about to read 4, iclass 16, count 0 2006.257.16:03:46.94#ibcon#read 4, iclass 16, count 0 2006.257.16:03:46.94#ibcon#about to read 5, iclass 16, count 0 2006.257.16:03:46.94#ibcon#read 5, iclass 16, count 0 2006.257.16:03:46.94#ibcon#about to read 6, iclass 16, count 0 2006.257.16:03:46.94#ibcon#read 6, iclass 16, count 0 2006.257.16:03:46.94#ibcon#end of sib2, iclass 16, count 0 2006.257.16:03:46.94#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:03:46.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:03:46.94#ibcon#[27=USB\r\n] 2006.257.16:03:46.94#ibcon#*before write, iclass 16, count 0 2006.257.16:03:46.94#ibcon#enter sib2, iclass 16, count 0 2006.257.16:03:46.94#ibcon#flushed, iclass 16, count 0 2006.257.16:03:46.94#ibcon#about to write, iclass 16, count 0 2006.257.16:03:46.94#ibcon#wrote, iclass 16, count 0 2006.257.16:03:46.94#ibcon#about to read 3, iclass 16, count 0 2006.257.16:03:46.97#ibcon#read 3, iclass 16, count 0 2006.257.16:03:46.97#ibcon#about to read 4, iclass 16, count 0 2006.257.16:03:46.97#ibcon#read 4, iclass 16, count 0 2006.257.16:03:46.97#ibcon#about to read 5, iclass 16, count 0 2006.257.16:03:46.97#ibcon#read 5, iclass 16, count 0 2006.257.16:03:46.97#ibcon#about to read 6, iclass 16, count 0 2006.257.16:03:46.97#ibcon#read 6, iclass 16, count 0 2006.257.16:03:46.97#ibcon#end of sib2, iclass 16, count 0 2006.257.16:03:46.97#ibcon#*after write, iclass 16, count 0 2006.257.16:03:46.97#ibcon#*before return 0, iclass 16, count 0 2006.257.16:03:46.97#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:46.97#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:03:46.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:03:46.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:03:46.97$vck44/vblo=4,679.99 2006.257.16:03:46.97#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.16:03:46.97#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.16:03:46.97#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:46.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:46.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:46.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:46.97#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:03:46.97#ibcon#first serial, iclass 18, count 0 2006.257.16:03:46.97#ibcon#enter sib2, iclass 18, count 0 2006.257.16:03:46.97#ibcon#flushed, iclass 18, count 0 2006.257.16:03:46.97#ibcon#about to write, iclass 18, count 0 2006.257.16:03:46.97#ibcon#wrote, iclass 18, count 0 2006.257.16:03:46.97#ibcon#about to read 3, iclass 18, count 0 2006.257.16:03:46.99#ibcon#read 3, iclass 18, count 0 2006.257.16:03:46.99#ibcon#about to read 4, iclass 18, count 0 2006.257.16:03:46.99#ibcon#read 4, iclass 18, count 0 2006.257.16:03:46.99#ibcon#about to read 5, iclass 18, count 0 2006.257.16:03:46.99#ibcon#read 5, iclass 18, count 0 2006.257.16:03:46.99#ibcon#about to read 6, iclass 18, count 0 2006.257.16:03:46.99#ibcon#read 6, iclass 18, count 0 2006.257.16:03:46.99#ibcon#end of sib2, iclass 18, count 0 2006.257.16:03:46.99#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:03:46.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:03:46.99#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.16:03:46.99#ibcon#*before write, iclass 18, count 0 2006.257.16:03:46.99#ibcon#enter sib2, iclass 18, count 0 2006.257.16:03:46.99#ibcon#flushed, iclass 18, count 0 2006.257.16:03:46.99#ibcon#about to write, iclass 18, count 0 2006.257.16:03:46.99#ibcon#wrote, iclass 18, count 0 2006.257.16:03:46.99#ibcon#about to read 3, iclass 18, count 0 2006.257.16:03:47.03#ibcon#read 3, iclass 18, count 0 2006.257.16:03:47.03#ibcon#about to read 4, iclass 18, count 0 2006.257.16:03:47.03#ibcon#read 4, iclass 18, count 0 2006.257.16:03:47.03#ibcon#about to read 5, iclass 18, count 0 2006.257.16:03:47.03#ibcon#read 5, iclass 18, count 0 2006.257.16:03:47.03#ibcon#about to read 6, iclass 18, count 0 2006.257.16:03:47.03#ibcon#read 6, iclass 18, count 0 2006.257.16:03:47.03#ibcon#end of sib2, iclass 18, count 0 2006.257.16:03:47.03#ibcon#*after write, iclass 18, count 0 2006.257.16:03:47.03#ibcon#*before return 0, iclass 18, count 0 2006.257.16:03:47.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:47.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:03:47.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:03:47.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:03:47.03$vck44/vb=4,5 2006.257.16:03:47.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.16:03:47.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.16:03:47.03#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:47.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:47.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:47.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:47.09#ibcon#enter wrdev, iclass 20, count 2 2006.257.16:03:47.09#ibcon#first serial, iclass 20, count 2 2006.257.16:03:47.09#ibcon#enter sib2, iclass 20, count 2 2006.257.16:03:47.09#ibcon#flushed, iclass 20, count 2 2006.257.16:03:47.09#ibcon#about to write, iclass 20, count 2 2006.257.16:03:47.09#ibcon#wrote, iclass 20, count 2 2006.257.16:03:47.09#ibcon#about to read 3, iclass 20, count 2 2006.257.16:03:47.11#ibcon#read 3, iclass 20, count 2 2006.257.16:03:47.11#ibcon#about to read 4, iclass 20, count 2 2006.257.16:03:47.11#ibcon#read 4, iclass 20, count 2 2006.257.16:03:47.11#ibcon#about to read 5, iclass 20, count 2 2006.257.16:03:47.11#ibcon#read 5, iclass 20, count 2 2006.257.16:03:47.11#ibcon#about to read 6, iclass 20, count 2 2006.257.16:03:47.11#ibcon#read 6, iclass 20, count 2 2006.257.16:03:47.11#ibcon#end of sib2, iclass 20, count 2 2006.257.16:03:47.11#ibcon#*mode == 0, iclass 20, count 2 2006.257.16:03:47.11#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.16:03:47.11#ibcon#[27=AT04-05\r\n] 2006.257.16:03:47.11#ibcon#*before write, iclass 20, count 2 2006.257.16:03:47.11#ibcon#enter sib2, iclass 20, count 2 2006.257.16:03:47.11#ibcon#flushed, iclass 20, count 2 2006.257.16:03:47.11#ibcon#about to write, iclass 20, count 2 2006.257.16:03:47.11#ibcon#wrote, iclass 20, count 2 2006.257.16:03:47.11#ibcon#about to read 3, iclass 20, count 2 2006.257.16:03:47.14#ibcon#read 3, iclass 20, count 2 2006.257.16:03:47.14#ibcon#about to read 4, iclass 20, count 2 2006.257.16:03:47.14#ibcon#read 4, iclass 20, count 2 2006.257.16:03:47.14#ibcon#about to read 5, iclass 20, count 2 2006.257.16:03:47.14#ibcon#read 5, iclass 20, count 2 2006.257.16:03:47.14#ibcon#about to read 6, iclass 20, count 2 2006.257.16:03:47.14#ibcon#read 6, iclass 20, count 2 2006.257.16:03:47.14#ibcon#end of sib2, iclass 20, count 2 2006.257.16:03:47.14#ibcon#*after write, iclass 20, count 2 2006.257.16:03:47.14#ibcon#*before return 0, iclass 20, count 2 2006.257.16:03:47.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:47.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:03:47.14#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.16:03:47.14#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:47.14#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:47.26#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:47.26#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:47.26#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:03:47.26#ibcon#first serial, iclass 20, count 0 2006.257.16:03:47.26#ibcon#enter sib2, iclass 20, count 0 2006.257.16:03:47.26#ibcon#flushed, iclass 20, count 0 2006.257.16:03:47.26#ibcon#about to write, iclass 20, count 0 2006.257.16:03:47.26#ibcon#wrote, iclass 20, count 0 2006.257.16:03:47.26#ibcon#about to read 3, iclass 20, count 0 2006.257.16:03:47.28#ibcon#read 3, iclass 20, count 0 2006.257.16:03:47.28#ibcon#about to read 4, iclass 20, count 0 2006.257.16:03:47.28#ibcon#read 4, iclass 20, count 0 2006.257.16:03:47.28#ibcon#about to read 5, iclass 20, count 0 2006.257.16:03:47.28#ibcon#read 5, iclass 20, count 0 2006.257.16:03:47.28#ibcon#about to read 6, iclass 20, count 0 2006.257.16:03:47.28#ibcon#read 6, iclass 20, count 0 2006.257.16:03:47.28#ibcon#end of sib2, iclass 20, count 0 2006.257.16:03:47.28#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:03:47.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:03:47.28#ibcon#[27=USB\r\n] 2006.257.16:03:47.28#ibcon#*before write, iclass 20, count 0 2006.257.16:03:47.28#ibcon#enter sib2, iclass 20, count 0 2006.257.16:03:47.28#ibcon#flushed, iclass 20, count 0 2006.257.16:03:47.28#ibcon#about to write, iclass 20, count 0 2006.257.16:03:47.28#ibcon#wrote, iclass 20, count 0 2006.257.16:03:47.28#ibcon#about to read 3, iclass 20, count 0 2006.257.16:03:47.31#ibcon#read 3, iclass 20, count 0 2006.257.16:03:47.31#ibcon#about to read 4, iclass 20, count 0 2006.257.16:03:47.31#ibcon#read 4, iclass 20, count 0 2006.257.16:03:47.31#ibcon#about to read 5, iclass 20, count 0 2006.257.16:03:47.31#ibcon#read 5, iclass 20, count 0 2006.257.16:03:47.31#ibcon#about to read 6, iclass 20, count 0 2006.257.16:03:47.31#ibcon#read 6, iclass 20, count 0 2006.257.16:03:47.31#ibcon#end of sib2, iclass 20, count 0 2006.257.16:03:47.31#ibcon#*after write, iclass 20, count 0 2006.257.16:03:47.31#ibcon#*before return 0, iclass 20, count 0 2006.257.16:03:47.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:47.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:03:47.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:03:47.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:03:47.31$vck44/vblo=5,709.99 2006.257.16:03:47.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.16:03:47.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.16:03:47.31#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:47.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:47.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:47.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:47.31#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:03:47.31#ibcon#first serial, iclass 22, count 0 2006.257.16:03:47.31#ibcon#enter sib2, iclass 22, count 0 2006.257.16:03:47.31#ibcon#flushed, iclass 22, count 0 2006.257.16:03:47.31#ibcon#about to write, iclass 22, count 0 2006.257.16:03:47.31#ibcon#wrote, iclass 22, count 0 2006.257.16:03:47.31#ibcon#about to read 3, iclass 22, count 0 2006.257.16:03:47.33#ibcon#read 3, iclass 22, count 0 2006.257.16:03:47.33#ibcon#about to read 4, iclass 22, count 0 2006.257.16:03:47.33#ibcon#read 4, iclass 22, count 0 2006.257.16:03:47.33#ibcon#about to read 5, iclass 22, count 0 2006.257.16:03:47.33#ibcon#read 5, iclass 22, count 0 2006.257.16:03:47.33#ibcon#about to read 6, iclass 22, count 0 2006.257.16:03:47.33#ibcon#read 6, iclass 22, count 0 2006.257.16:03:47.33#ibcon#end of sib2, iclass 22, count 0 2006.257.16:03:47.33#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:03:47.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:03:47.33#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:03:47.33#ibcon#*before write, iclass 22, count 0 2006.257.16:03:47.33#ibcon#enter sib2, iclass 22, count 0 2006.257.16:03:47.33#ibcon#flushed, iclass 22, count 0 2006.257.16:03:47.33#ibcon#about to write, iclass 22, count 0 2006.257.16:03:47.33#ibcon#wrote, iclass 22, count 0 2006.257.16:03:47.33#ibcon#about to read 3, iclass 22, count 0 2006.257.16:03:47.37#ibcon#read 3, iclass 22, count 0 2006.257.16:03:47.37#ibcon#about to read 4, iclass 22, count 0 2006.257.16:03:47.37#ibcon#read 4, iclass 22, count 0 2006.257.16:03:47.37#ibcon#about to read 5, iclass 22, count 0 2006.257.16:03:47.37#ibcon#read 5, iclass 22, count 0 2006.257.16:03:47.37#ibcon#about to read 6, iclass 22, count 0 2006.257.16:03:47.37#ibcon#read 6, iclass 22, count 0 2006.257.16:03:47.37#ibcon#end of sib2, iclass 22, count 0 2006.257.16:03:47.37#ibcon#*after write, iclass 22, count 0 2006.257.16:03:47.37#ibcon#*before return 0, iclass 22, count 0 2006.257.16:03:47.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:47.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:03:47.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:03:47.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:03:47.37$vck44/vb=5,4 2006.257.16:03:47.37#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.16:03:47.37#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.16:03:47.37#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:47.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:47.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:47.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:47.43#ibcon#enter wrdev, iclass 24, count 2 2006.257.16:03:47.43#ibcon#first serial, iclass 24, count 2 2006.257.16:03:47.43#ibcon#enter sib2, iclass 24, count 2 2006.257.16:03:47.43#ibcon#flushed, iclass 24, count 2 2006.257.16:03:47.43#ibcon#about to write, iclass 24, count 2 2006.257.16:03:47.43#ibcon#wrote, iclass 24, count 2 2006.257.16:03:47.43#ibcon#about to read 3, iclass 24, count 2 2006.257.16:03:47.45#ibcon#read 3, iclass 24, count 2 2006.257.16:03:47.45#ibcon#about to read 4, iclass 24, count 2 2006.257.16:03:47.45#ibcon#read 4, iclass 24, count 2 2006.257.16:03:47.45#ibcon#about to read 5, iclass 24, count 2 2006.257.16:03:47.45#ibcon#read 5, iclass 24, count 2 2006.257.16:03:47.45#ibcon#about to read 6, iclass 24, count 2 2006.257.16:03:47.45#ibcon#read 6, iclass 24, count 2 2006.257.16:03:47.45#ibcon#end of sib2, iclass 24, count 2 2006.257.16:03:47.45#ibcon#*mode == 0, iclass 24, count 2 2006.257.16:03:47.45#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.16:03:47.45#ibcon#[27=AT05-04\r\n] 2006.257.16:03:47.45#ibcon#*before write, iclass 24, count 2 2006.257.16:03:47.45#ibcon#enter sib2, iclass 24, count 2 2006.257.16:03:47.45#ibcon#flushed, iclass 24, count 2 2006.257.16:03:47.45#ibcon#about to write, iclass 24, count 2 2006.257.16:03:47.45#ibcon#wrote, iclass 24, count 2 2006.257.16:03:47.45#ibcon#about to read 3, iclass 24, count 2 2006.257.16:03:47.48#ibcon#read 3, iclass 24, count 2 2006.257.16:03:47.48#ibcon#about to read 4, iclass 24, count 2 2006.257.16:03:47.48#ibcon#read 4, iclass 24, count 2 2006.257.16:03:47.48#ibcon#about to read 5, iclass 24, count 2 2006.257.16:03:47.48#ibcon#read 5, iclass 24, count 2 2006.257.16:03:47.48#ibcon#about to read 6, iclass 24, count 2 2006.257.16:03:47.48#ibcon#read 6, iclass 24, count 2 2006.257.16:03:47.48#ibcon#end of sib2, iclass 24, count 2 2006.257.16:03:47.48#ibcon#*after write, iclass 24, count 2 2006.257.16:03:47.48#ibcon#*before return 0, iclass 24, count 2 2006.257.16:03:47.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:47.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:03:47.48#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.16:03:47.48#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:47.48#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:47.60#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:47.60#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:47.60#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:03:47.60#ibcon#first serial, iclass 24, count 0 2006.257.16:03:47.60#ibcon#enter sib2, iclass 24, count 0 2006.257.16:03:47.60#ibcon#flushed, iclass 24, count 0 2006.257.16:03:47.60#ibcon#about to write, iclass 24, count 0 2006.257.16:03:47.60#ibcon#wrote, iclass 24, count 0 2006.257.16:03:47.60#ibcon#about to read 3, iclass 24, count 0 2006.257.16:03:47.62#ibcon#read 3, iclass 24, count 0 2006.257.16:03:47.62#ibcon#about to read 4, iclass 24, count 0 2006.257.16:03:47.62#ibcon#read 4, iclass 24, count 0 2006.257.16:03:47.62#ibcon#about to read 5, iclass 24, count 0 2006.257.16:03:47.62#ibcon#read 5, iclass 24, count 0 2006.257.16:03:47.62#ibcon#about to read 6, iclass 24, count 0 2006.257.16:03:47.62#ibcon#read 6, iclass 24, count 0 2006.257.16:03:47.62#ibcon#end of sib2, iclass 24, count 0 2006.257.16:03:47.62#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:03:47.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:03:47.62#ibcon#[27=USB\r\n] 2006.257.16:03:47.62#ibcon#*before write, iclass 24, count 0 2006.257.16:03:47.62#ibcon#enter sib2, iclass 24, count 0 2006.257.16:03:47.62#ibcon#flushed, iclass 24, count 0 2006.257.16:03:47.62#ibcon#about to write, iclass 24, count 0 2006.257.16:03:47.62#ibcon#wrote, iclass 24, count 0 2006.257.16:03:47.62#ibcon#about to read 3, iclass 24, count 0 2006.257.16:03:47.65#ibcon#read 3, iclass 24, count 0 2006.257.16:03:47.65#ibcon#about to read 4, iclass 24, count 0 2006.257.16:03:47.65#ibcon#read 4, iclass 24, count 0 2006.257.16:03:47.65#ibcon#about to read 5, iclass 24, count 0 2006.257.16:03:47.65#ibcon#read 5, iclass 24, count 0 2006.257.16:03:47.65#ibcon#about to read 6, iclass 24, count 0 2006.257.16:03:47.65#ibcon#read 6, iclass 24, count 0 2006.257.16:03:47.65#ibcon#end of sib2, iclass 24, count 0 2006.257.16:03:47.65#ibcon#*after write, iclass 24, count 0 2006.257.16:03:47.65#ibcon#*before return 0, iclass 24, count 0 2006.257.16:03:47.65#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:47.65#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:03:47.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:03:47.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:03:47.65$vck44/vblo=6,719.99 2006.257.16:03:47.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.16:03:47.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.16:03:47.65#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:47.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:47.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:47.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:47.65#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:03:47.65#ibcon#first serial, iclass 26, count 0 2006.257.16:03:47.65#ibcon#enter sib2, iclass 26, count 0 2006.257.16:03:47.65#ibcon#flushed, iclass 26, count 0 2006.257.16:03:47.65#ibcon#about to write, iclass 26, count 0 2006.257.16:03:47.65#ibcon#wrote, iclass 26, count 0 2006.257.16:03:47.65#ibcon#about to read 3, iclass 26, count 0 2006.257.16:03:47.67#ibcon#read 3, iclass 26, count 0 2006.257.16:03:47.67#ibcon#about to read 4, iclass 26, count 0 2006.257.16:03:47.67#ibcon#read 4, iclass 26, count 0 2006.257.16:03:47.67#ibcon#about to read 5, iclass 26, count 0 2006.257.16:03:47.67#ibcon#read 5, iclass 26, count 0 2006.257.16:03:47.67#ibcon#about to read 6, iclass 26, count 0 2006.257.16:03:47.67#ibcon#read 6, iclass 26, count 0 2006.257.16:03:47.67#ibcon#end of sib2, iclass 26, count 0 2006.257.16:03:47.67#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:03:47.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:03:47.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:03:47.67#ibcon#*before write, iclass 26, count 0 2006.257.16:03:47.67#ibcon#enter sib2, iclass 26, count 0 2006.257.16:03:47.67#ibcon#flushed, iclass 26, count 0 2006.257.16:03:47.67#ibcon#about to write, iclass 26, count 0 2006.257.16:03:47.67#ibcon#wrote, iclass 26, count 0 2006.257.16:03:47.67#ibcon#about to read 3, iclass 26, count 0 2006.257.16:03:47.71#ibcon#read 3, iclass 26, count 0 2006.257.16:03:47.71#ibcon#about to read 4, iclass 26, count 0 2006.257.16:03:47.71#ibcon#read 4, iclass 26, count 0 2006.257.16:03:47.71#ibcon#about to read 5, iclass 26, count 0 2006.257.16:03:47.71#ibcon#read 5, iclass 26, count 0 2006.257.16:03:47.71#ibcon#about to read 6, iclass 26, count 0 2006.257.16:03:47.71#ibcon#read 6, iclass 26, count 0 2006.257.16:03:47.71#ibcon#end of sib2, iclass 26, count 0 2006.257.16:03:47.71#ibcon#*after write, iclass 26, count 0 2006.257.16:03:47.71#ibcon#*before return 0, iclass 26, count 0 2006.257.16:03:47.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:47.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:03:47.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:03:47.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:03:47.71$vck44/vb=6,4 2006.257.16:03:47.71#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.16:03:47.71#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.16:03:47.71#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:47.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:47.77#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:47.77#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:47.77#ibcon#enter wrdev, iclass 28, count 2 2006.257.16:03:47.77#ibcon#first serial, iclass 28, count 2 2006.257.16:03:47.77#ibcon#enter sib2, iclass 28, count 2 2006.257.16:03:47.77#ibcon#flushed, iclass 28, count 2 2006.257.16:03:47.77#ibcon#about to write, iclass 28, count 2 2006.257.16:03:47.77#ibcon#wrote, iclass 28, count 2 2006.257.16:03:47.77#ibcon#about to read 3, iclass 28, count 2 2006.257.16:03:47.79#ibcon#read 3, iclass 28, count 2 2006.257.16:03:47.79#ibcon#about to read 4, iclass 28, count 2 2006.257.16:03:47.79#ibcon#read 4, iclass 28, count 2 2006.257.16:03:47.79#ibcon#about to read 5, iclass 28, count 2 2006.257.16:03:47.79#ibcon#read 5, iclass 28, count 2 2006.257.16:03:47.79#ibcon#about to read 6, iclass 28, count 2 2006.257.16:03:47.79#ibcon#read 6, iclass 28, count 2 2006.257.16:03:47.79#ibcon#end of sib2, iclass 28, count 2 2006.257.16:03:47.79#ibcon#*mode == 0, iclass 28, count 2 2006.257.16:03:47.79#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.16:03:47.79#ibcon#[27=AT06-04\r\n] 2006.257.16:03:47.79#ibcon#*before write, iclass 28, count 2 2006.257.16:03:47.79#ibcon#enter sib2, iclass 28, count 2 2006.257.16:03:47.79#ibcon#flushed, iclass 28, count 2 2006.257.16:03:47.79#ibcon#about to write, iclass 28, count 2 2006.257.16:03:47.79#ibcon#wrote, iclass 28, count 2 2006.257.16:03:47.79#ibcon#about to read 3, iclass 28, count 2 2006.257.16:03:47.82#ibcon#read 3, iclass 28, count 2 2006.257.16:03:47.82#ibcon#about to read 4, iclass 28, count 2 2006.257.16:03:47.82#ibcon#read 4, iclass 28, count 2 2006.257.16:03:47.82#ibcon#about to read 5, iclass 28, count 2 2006.257.16:03:47.82#ibcon#read 5, iclass 28, count 2 2006.257.16:03:47.82#ibcon#about to read 6, iclass 28, count 2 2006.257.16:03:47.82#ibcon#read 6, iclass 28, count 2 2006.257.16:03:47.82#ibcon#end of sib2, iclass 28, count 2 2006.257.16:03:47.82#ibcon#*after write, iclass 28, count 2 2006.257.16:03:47.82#ibcon#*before return 0, iclass 28, count 2 2006.257.16:03:47.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:47.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:03:47.82#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.16:03:47.82#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:47.82#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:47.83#abcon#<5=/14 1.6 4.2 17.33 971014.0\r\n> 2006.257.16:03:47.85#abcon#{5=INTERFACE CLEAR} 2006.257.16:03:47.91#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:03:47.94#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:47.94#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:47.94#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:03:47.94#ibcon#first serial, iclass 28, count 0 2006.257.16:03:47.94#ibcon#enter sib2, iclass 28, count 0 2006.257.16:03:47.94#ibcon#flushed, iclass 28, count 0 2006.257.16:03:47.94#ibcon#about to write, iclass 28, count 0 2006.257.16:03:47.94#ibcon#wrote, iclass 28, count 0 2006.257.16:03:47.94#ibcon#about to read 3, iclass 28, count 0 2006.257.16:03:47.96#ibcon#read 3, iclass 28, count 0 2006.257.16:03:47.96#ibcon#about to read 4, iclass 28, count 0 2006.257.16:03:47.96#ibcon#read 4, iclass 28, count 0 2006.257.16:03:47.96#ibcon#about to read 5, iclass 28, count 0 2006.257.16:03:47.96#ibcon#read 5, iclass 28, count 0 2006.257.16:03:47.96#ibcon#about to read 6, iclass 28, count 0 2006.257.16:03:47.96#ibcon#read 6, iclass 28, count 0 2006.257.16:03:47.96#ibcon#end of sib2, iclass 28, count 0 2006.257.16:03:47.96#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:03:47.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:03:47.96#ibcon#[27=USB\r\n] 2006.257.16:03:47.96#ibcon#*before write, iclass 28, count 0 2006.257.16:03:47.96#ibcon#enter sib2, iclass 28, count 0 2006.257.16:03:47.96#ibcon#flushed, iclass 28, count 0 2006.257.16:03:47.96#ibcon#about to write, iclass 28, count 0 2006.257.16:03:47.96#ibcon#wrote, iclass 28, count 0 2006.257.16:03:47.96#ibcon#about to read 3, iclass 28, count 0 2006.257.16:03:47.99#ibcon#read 3, iclass 28, count 0 2006.257.16:03:47.99#ibcon#about to read 4, iclass 28, count 0 2006.257.16:03:47.99#ibcon#read 4, iclass 28, count 0 2006.257.16:03:47.99#ibcon#about to read 5, iclass 28, count 0 2006.257.16:03:47.99#ibcon#read 5, iclass 28, count 0 2006.257.16:03:47.99#ibcon#about to read 6, iclass 28, count 0 2006.257.16:03:47.99#ibcon#read 6, iclass 28, count 0 2006.257.16:03:47.99#ibcon#end of sib2, iclass 28, count 0 2006.257.16:03:47.99#ibcon#*after write, iclass 28, count 0 2006.257.16:03:47.99#ibcon#*before return 0, iclass 28, count 0 2006.257.16:03:47.99#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:47.99#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:03:47.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:03:47.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:03:47.99$vck44/vblo=7,734.99 2006.257.16:03:47.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.16:03:47.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.16:03:47.99#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:47.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:47.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:47.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:47.99#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:03:47.99#ibcon#first serial, iclass 34, count 0 2006.257.16:03:47.99#ibcon#enter sib2, iclass 34, count 0 2006.257.16:03:47.99#ibcon#flushed, iclass 34, count 0 2006.257.16:03:47.99#ibcon#about to write, iclass 34, count 0 2006.257.16:03:47.99#ibcon#wrote, iclass 34, count 0 2006.257.16:03:47.99#ibcon#about to read 3, iclass 34, count 0 2006.257.16:03:48.01#ibcon#read 3, iclass 34, count 0 2006.257.16:03:48.01#ibcon#about to read 4, iclass 34, count 0 2006.257.16:03:48.01#ibcon#read 4, iclass 34, count 0 2006.257.16:03:48.01#ibcon#about to read 5, iclass 34, count 0 2006.257.16:03:48.01#ibcon#read 5, iclass 34, count 0 2006.257.16:03:48.01#ibcon#about to read 6, iclass 34, count 0 2006.257.16:03:48.01#ibcon#read 6, iclass 34, count 0 2006.257.16:03:48.01#ibcon#end of sib2, iclass 34, count 0 2006.257.16:03:48.01#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:03:48.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:03:48.01#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:03:48.01#ibcon#*before write, iclass 34, count 0 2006.257.16:03:48.01#ibcon#enter sib2, iclass 34, count 0 2006.257.16:03:48.01#ibcon#flushed, iclass 34, count 0 2006.257.16:03:48.01#ibcon#about to write, iclass 34, count 0 2006.257.16:03:48.01#ibcon#wrote, iclass 34, count 0 2006.257.16:03:48.01#ibcon#about to read 3, iclass 34, count 0 2006.257.16:03:48.05#ibcon#read 3, iclass 34, count 0 2006.257.16:03:48.05#ibcon#about to read 4, iclass 34, count 0 2006.257.16:03:48.05#ibcon#read 4, iclass 34, count 0 2006.257.16:03:48.05#ibcon#about to read 5, iclass 34, count 0 2006.257.16:03:48.05#ibcon#read 5, iclass 34, count 0 2006.257.16:03:48.05#ibcon#about to read 6, iclass 34, count 0 2006.257.16:03:48.05#ibcon#read 6, iclass 34, count 0 2006.257.16:03:48.05#ibcon#end of sib2, iclass 34, count 0 2006.257.16:03:48.05#ibcon#*after write, iclass 34, count 0 2006.257.16:03:48.05#ibcon#*before return 0, iclass 34, count 0 2006.257.16:03:48.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:48.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:03:48.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:03:48.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:03:48.05$vck44/vb=7,4 2006.257.16:03:48.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.16:03:48.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.16:03:48.05#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:48.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:48.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:48.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:48.11#ibcon#enter wrdev, iclass 36, count 2 2006.257.16:03:48.11#ibcon#first serial, iclass 36, count 2 2006.257.16:03:48.11#ibcon#enter sib2, iclass 36, count 2 2006.257.16:03:48.11#ibcon#flushed, iclass 36, count 2 2006.257.16:03:48.11#ibcon#about to write, iclass 36, count 2 2006.257.16:03:48.11#ibcon#wrote, iclass 36, count 2 2006.257.16:03:48.11#ibcon#about to read 3, iclass 36, count 2 2006.257.16:03:48.13#ibcon#read 3, iclass 36, count 2 2006.257.16:03:48.13#ibcon#about to read 4, iclass 36, count 2 2006.257.16:03:48.13#ibcon#read 4, iclass 36, count 2 2006.257.16:03:48.13#ibcon#about to read 5, iclass 36, count 2 2006.257.16:03:48.13#ibcon#read 5, iclass 36, count 2 2006.257.16:03:48.13#ibcon#about to read 6, iclass 36, count 2 2006.257.16:03:48.13#ibcon#read 6, iclass 36, count 2 2006.257.16:03:48.13#ibcon#end of sib2, iclass 36, count 2 2006.257.16:03:48.13#ibcon#*mode == 0, iclass 36, count 2 2006.257.16:03:48.13#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.16:03:48.13#ibcon#[27=AT07-04\r\n] 2006.257.16:03:48.13#ibcon#*before write, iclass 36, count 2 2006.257.16:03:48.13#ibcon#enter sib2, iclass 36, count 2 2006.257.16:03:48.13#ibcon#flushed, iclass 36, count 2 2006.257.16:03:48.13#ibcon#about to write, iclass 36, count 2 2006.257.16:03:48.13#ibcon#wrote, iclass 36, count 2 2006.257.16:03:48.13#ibcon#about to read 3, iclass 36, count 2 2006.257.16:03:48.16#ibcon#read 3, iclass 36, count 2 2006.257.16:03:48.16#ibcon#about to read 4, iclass 36, count 2 2006.257.16:03:48.16#ibcon#read 4, iclass 36, count 2 2006.257.16:03:48.16#ibcon#about to read 5, iclass 36, count 2 2006.257.16:03:48.16#ibcon#read 5, iclass 36, count 2 2006.257.16:03:48.16#ibcon#about to read 6, iclass 36, count 2 2006.257.16:03:48.16#ibcon#read 6, iclass 36, count 2 2006.257.16:03:48.16#ibcon#end of sib2, iclass 36, count 2 2006.257.16:03:48.16#ibcon#*after write, iclass 36, count 2 2006.257.16:03:48.16#ibcon#*before return 0, iclass 36, count 2 2006.257.16:03:48.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:48.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:03:48.16#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.16:03:48.16#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:48.16#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:48.28#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:48.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:48.28#ibcon#enter wrdev, iclass 36, count 0 2006.257.16:03:48.28#ibcon#first serial, iclass 36, count 0 2006.257.16:03:48.28#ibcon#enter sib2, iclass 36, count 0 2006.257.16:03:48.28#ibcon#flushed, iclass 36, count 0 2006.257.16:03:48.28#ibcon#about to write, iclass 36, count 0 2006.257.16:03:48.28#ibcon#wrote, iclass 36, count 0 2006.257.16:03:48.28#ibcon#about to read 3, iclass 36, count 0 2006.257.16:03:48.30#ibcon#read 3, iclass 36, count 0 2006.257.16:03:48.30#ibcon#about to read 4, iclass 36, count 0 2006.257.16:03:48.30#ibcon#read 4, iclass 36, count 0 2006.257.16:03:48.30#ibcon#about to read 5, iclass 36, count 0 2006.257.16:03:48.30#ibcon#read 5, iclass 36, count 0 2006.257.16:03:48.30#ibcon#about to read 6, iclass 36, count 0 2006.257.16:03:48.30#ibcon#read 6, iclass 36, count 0 2006.257.16:03:48.30#ibcon#end of sib2, iclass 36, count 0 2006.257.16:03:48.30#ibcon#*mode == 0, iclass 36, count 0 2006.257.16:03:48.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.16:03:48.30#ibcon#[27=USB\r\n] 2006.257.16:03:48.30#ibcon#*before write, iclass 36, count 0 2006.257.16:03:48.30#ibcon#enter sib2, iclass 36, count 0 2006.257.16:03:48.30#ibcon#flushed, iclass 36, count 0 2006.257.16:03:48.30#ibcon#about to write, iclass 36, count 0 2006.257.16:03:48.30#ibcon#wrote, iclass 36, count 0 2006.257.16:03:48.30#ibcon#about to read 3, iclass 36, count 0 2006.257.16:03:48.33#ibcon#read 3, iclass 36, count 0 2006.257.16:03:48.33#ibcon#about to read 4, iclass 36, count 0 2006.257.16:03:48.33#ibcon#read 4, iclass 36, count 0 2006.257.16:03:48.33#ibcon#about to read 5, iclass 36, count 0 2006.257.16:03:48.33#ibcon#read 5, iclass 36, count 0 2006.257.16:03:48.33#ibcon#about to read 6, iclass 36, count 0 2006.257.16:03:48.33#ibcon#read 6, iclass 36, count 0 2006.257.16:03:48.33#ibcon#end of sib2, iclass 36, count 0 2006.257.16:03:48.33#ibcon#*after write, iclass 36, count 0 2006.257.16:03:48.33#ibcon#*before return 0, iclass 36, count 0 2006.257.16:03:48.33#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:48.33#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:03:48.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.16:03:48.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.16:03:48.33$vck44/vblo=8,744.99 2006.257.16:03:48.33#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.16:03:48.33#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.16:03:48.33#ibcon#ireg 17 cls_cnt 0 2006.257.16:03:48.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:48.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:48.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:48.33#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:03:48.33#ibcon#first serial, iclass 38, count 0 2006.257.16:03:48.33#ibcon#enter sib2, iclass 38, count 0 2006.257.16:03:48.33#ibcon#flushed, iclass 38, count 0 2006.257.16:03:48.33#ibcon#about to write, iclass 38, count 0 2006.257.16:03:48.33#ibcon#wrote, iclass 38, count 0 2006.257.16:03:48.33#ibcon#about to read 3, iclass 38, count 0 2006.257.16:03:48.35#ibcon#read 3, iclass 38, count 0 2006.257.16:03:48.35#ibcon#about to read 4, iclass 38, count 0 2006.257.16:03:48.35#ibcon#read 4, iclass 38, count 0 2006.257.16:03:48.35#ibcon#about to read 5, iclass 38, count 0 2006.257.16:03:48.35#ibcon#read 5, iclass 38, count 0 2006.257.16:03:48.35#ibcon#about to read 6, iclass 38, count 0 2006.257.16:03:48.35#ibcon#read 6, iclass 38, count 0 2006.257.16:03:48.35#ibcon#end of sib2, iclass 38, count 0 2006.257.16:03:48.35#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:03:48.35#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:03:48.35#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:03:48.35#ibcon#*before write, iclass 38, count 0 2006.257.16:03:48.35#ibcon#enter sib2, iclass 38, count 0 2006.257.16:03:48.35#ibcon#flushed, iclass 38, count 0 2006.257.16:03:48.35#ibcon#about to write, iclass 38, count 0 2006.257.16:03:48.35#ibcon#wrote, iclass 38, count 0 2006.257.16:03:48.35#ibcon#about to read 3, iclass 38, count 0 2006.257.16:03:48.39#ibcon#read 3, iclass 38, count 0 2006.257.16:03:48.39#ibcon#about to read 4, iclass 38, count 0 2006.257.16:03:48.39#ibcon#read 4, iclass 38, count 0 2006.257.16:03:48.39#ibcon#about to read 5, iclass 38, count 0 2006.257.16:03:48.39#ibcon#read 5, iclass 38, count 0 2006.257.16:03:48.39#ibcon#about to read 6, iclass 38, count 0 2006.257.16:03:48.39#ibcon#read 6, iclass 38, count 0 2006.257.16:03:48.39#ibcon#end of sib2, iclass 38, count 0 2006.257.16:03:48.39#ibcon#*after write, iclass 38, count 0 2006.257.16:03:48.39#ibcon#*before return 0, iclass 38, count 0 2006.257.16:03:48.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:48.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:03:48.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:03:48.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:03:48.39$vck44/vb=8,4 2006.257.16:03:48.39#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.16:03:48.39#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.16:03:48.39#ibcon#ireg 11 cls_cnt 2 2006.257.16:03:48.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:48.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:48.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:48.45#ibcon#enter wrdev, iclass 40, count 2 2006.257.16:03:48.45#ibcon#first serial, iclass 40, count 2 2006.257.16:03:48.45#ibcon#enter sib2, iclass 40, count 2 2006.257.16:03:48.45#ibcon#flushed, iclass 40, count 2 2006.257.16:03:48.45#ibcon#about to write, iclass 40, count 2 2006.257.16:03:48.45#ibcon#wrote, iclass 40, count 2 2006.257.16:03:48.45#ibcon#about to read 3, iclass 40, count 2 2006.257.16:03:48.47#ibcon#read 3, iclass 40, count 2 2006.257.16:03:48.47#ibcon#about to read 4, iclass 40, count 2 2006.257.16:03:48.47#ibcon#read 4, iclass 40, count 2 2006.257.16:03:48.47#ibcon#about to read 5, iclass 40, count 2 2006.257.16:03:48.47#ibcon#read 5, iclass 40, count 2 2006.257.16:03:48.47#ibcon#about to read 6, iclass 40, count 2 2006.257.16:03:48.47#ibcon#read 6, iclass 40, count 2 2006.257.16:03:48.47#ibcon#end of sib2, iclass 40, count 2 2006.257.16:03:48.47#ibcon#*mode == 0, iclass 40, count 2 2006.257.16:03:48.47#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.16:03:48.47#ibcon#[27=AT08-04\r\n] 2006.257.16:03:48.47#ibcon#*before write, iclass 40, count 2 2006.257.16:03:48.47#ibcon#enter sib2, iclass 40, count 2 2006.257.16:03:48.47#ibcon#flushed, iclass 40, count 2 2006.257.16:03:48.47#ibcon#about to write, iclass 40, count 2 2006.257.16:03:48.47#ibcon#wrote, iclass 40, count 2 2006.257.16:03:48.47#ibcon#about to read 3, iclass 40, count 2 2006.257.16:03:48.50#ibcon#read 3, iclass 40, count 2 2006.257.16:03:48.50#ibcon#about to read 4, iclass 40, count 2 2006.257.16:03:48.50#ibcon#read 4, iclass 40, count 2 2006.257.16:03:48.50#ibcon#about to read 5, iclass 40, count 2 2006.257.16:03:48.50#ibcon#read 5, iclass 40, count 2 2006.257.16:03:48.50#ibcon#about to read 6, iclass 40, count 2 2006.257.16:03:48.50#ibcon#read 6, iclass 40, count 2 2006.257.16:03:48.50#ibcon#end of sib2, iclass 40, count 2 2006.257.16:03:48.50#ibcon#*after write, iclass 40, count 2 2006.257.16:03:48.50#ibcon#*before return 0, iclass 40, count 2 2006.257.16:03:48.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:48.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:03:48.50#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.16:03:48.50#ibcon#ireg 7 cls_cnt 0 2006.257.16:03:48.50#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:48.62#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:48.62#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:48.62#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:03:48.62#ibcon#first serial, iclass 40, count 0 2006.257.16:03:48.62#ibcon#enter sib2, iclass 40, count 0 2006.257.16:03:48.62#ibcon#flushed, iclass 40, count 0 2006.257.16:03:48.62#ibcon#about to write, iclass 40, count 0 2006.257.16:03:48.62#ibcon#wrote, iclass 40, count 0 2006.257.16:03:48.62#ibcon#about to read 3, iclass 40, count 0 2006.257.16:03:48.64#ibcon#read 3, iclass 40, count 0 2006.257.16:03:48.64#ibcon#about to read 4, iclass 40, count 0 2006.257.16:03:48.64#ibcon#read 4, iclass 40, count 0 2006.257.16:03:48.64#ibcon#about to read 5, iclass 40, count 0 2006.257.16:03:48.64#ibcon#read 5, iclass 40, count 0 2006.257.16:03:48.64#ibcon#about to read 6, iclass 40, count 0 2006.257.16:03:48.64#ibcon#read 6, iclass 40, count 0 2006.257.16:03:48.64#ibcon#end of sib2, iclass 40, count 0 2006.257.16:03:48.64#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:03:48.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:03:48.64#ibcon#[27=USB\r\n] 2006.257.16:03:48.64#ibcon#*before write, iclass 40, count 0 2006.257.16:03:48.64#ibcon#enter sib2, iclass 40, count 0 2006.257.16:03:48.64#ibcon#flushed, iclass 40, count 0 2006.257.16:03:48.64#ibcon#about to write, iclass 40, count 0 2006.257.16:03:48.64#ibcon#wrote, iclass 40, count 0 2006.257.16:03:48.64#ibcon#about to read 3, iclass 40, count 0 2006.257.16:03:48.67#ibcon#read 3, iclass 40, count 0 2006.257.16:03:48.67#ibcon#about to read 4, iclass 40, count 0 2006.257.16:03:48.67#ibcon#read 4, iclass 40, count 0 2006.257.16:03:48.67#ibcon#about to read 5, iclass 40, count 0 2006.257.16:03:48.67#ibcon#read 5, iclass 40, count 0 2006.257.16:03:48.67#ibcon#about to read 6, iclass 40, count 0 2006.257.16:03:48.67#ibcon#read 6, iclass 40, count 0 2006.257.16:03:48.67#ibcon#end of sib2, iclass 40, count 0 2006.257.16:03:48.67#ibcon#*after write, iclass 40, count 0 2006.257.16:03:48.67#ibcon#*before return 0, iclass 40, count 0 2006.257.16:03:48.67#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:48.67#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:03:48.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:03:48.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:03:48.67$vck44/vabw=wide 2006.257.16:03:48.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.16:03:48.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.16:03:48.67#ibcon#ireg 8 cls_cnt 0 2006.257.16:03:48.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:48.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:48.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:48.67#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:03:48.67#ibcon#first serial, iclass 4, count 0 2006.257.16:03:48.67#ibcon#enter sib2, iclass 4, count 0 2006.257.16:03:48.67#ibcon#flushed, iclass 4, count 0 2006.257.16:03:48.67#ibcon#about to write, iclass 4, count 0 2006.257.16:03:48.67#ibcon#wrote, iclass 4, count 0 2006.257.16:03:48.67#ibcon#about to read 3, iclass 4, count 0 2006.257.16:03:48.69#ibcon#read 3, iclass 4, count 0 2006.257.16:03:48.69#ibcon#about to read 4, iclass 4, count 0 2006.257.16:03:48.69#ibcon#read 4, iclass 4, count 0 2006.257.16:03:48.69#ibcon#about to read 5, iclass 4, count 0 2006.257.16:03:48.69#ibcon#read 5, iclass 4, count 0 2006.257.16:03:48.69#ibcon#about to read 6, iclass 4, count 0 2006.257.16:03:48.69#ibcon#read 6, iclass 4, count 0 2006.257.16:03:48.69#ibcon#end of sib2, iclass 4, count 0 2006.257.16:03:48.69#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:03:48.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:03:48.69#ibcon#[25=BW32\r\n] 2006.257.16:03:48.69#ibcon#*before write, iclass 4, count 0 2006.257.16:03:48.69#ibcon#enter sib2, iclass 4, count 0 2006.257.16:03:48.69#ibcon#flushed, iclass 4, count 0 2006.257.16:03:48.69#ibcon#about to write, iclass 4, count 0 2006.257.16:03:48.69#ibcon#wrote, iclass 4, count 0 2006.257.16:03:48.69#ibcon#about to read 3, iclass 4, count 0 2006.257.16:03:48.72#ibcon#read 3, iclass 4, count 0 2006.257.16:03:48.72#ibcon#about to read 4, iclass 4, count 0 2006.257.16:03:48.72#ibcon#read 4, iclass 4, count 0 2006.257.16:03:48.72#ibcon#about to read 5, iclass 4, count 0 2006.257.16:03:48.72#ibcon#read 5, iclass 4, count 0 2006.257.16:03:48.72#ibcon#about to read 6, iclass 4, count 0 2006.257.16:03:48.72#ibcon#read 6, iclass 4, count 0 2006.257.16:03:48.72#ibcon#end of sib2, iclass 4, count 0 2006.257.16:03:48.72#ibcon#*after write, iclass 4, count 0 2006.257.16:03:48.72#ibcon#*before return 0, iclass 4, count 0 2006.257.16:03:48.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:48.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:03:48.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:03:48.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:03:48.72$vck44/vbbw=wide 2006.257.16:03:48.72#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.16:03:48.72#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.16:03:48.72#ibcon#ireg 8 cls_cnt 0 2006.257.16:03:48.72#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:03:48.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:03:48.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:03:48.79#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:03:48.79#ibcon#first serial, iclass 6, count 0 2006.257.16:03:48.79#ibcon#enter sib2, iclass 6, count 0 2006.257.16:03:48.79#ibcon#flushed, iclass 6, count 0 2006.257.16:03:48.79#ibcon#about to write, iclass 6, count 0 2006.257.16:03:48.79#ibcon#wrote, iclass 6, count 0 2006.257.16:03:48.79#ibcon#about to read 3, iclass 6, count 0 2006.257.16:03:48.81#ibcon#read 3, iclass 6, count 0 2006.257.16:03:48.81#ibcon#about to read 4, iclass 6, count 0 2006.257.16:03:48.81#ibcon#read 4, iclass 6, count 0 2006.257.16:03:48.81#ibcon#about to read 5, iclass 6, count 0 2006.257.16:03:48.81#ibcon#read 5, iclass 6, count 0 2006.257.16:03:48.81#ibcon#about to read 6, iclass 6, count 0 2006.257.16:03:48.81#ibcon#read 6, iclass 6, count 0 2006.257.16:03:48.81#ibcon#end of sib2, iclass 6, count 0 2006.257.16:03:48.81#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:03:48.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:03:48.81#ibcon#[27=BW32\r\n] 2006.257.16:03:48.81#ibcon#*before write, iclass 6, count 0 2006.257.16:03:48.81#ibcon#enter sib2, iclass 6, count 0 2006.257.16:03:48.81#ibcon#flushed, iclass 6, count 0 2006.257.16:03:48.81#ibcon#about to write, iclass 6, count 0 2006.257.16:03:48.81#ibcon#wrote, iclass 6, count 0 2006.257.16:03:48.81#ibcon#about to read 3, iclass 6, count 0 2006.257.16:03:48.84#ibcon#read 3, iclass 6, count 0 2006.257.16:03:48.84#ibcon#about to read 4, iclass 6, count 0 2006.257.16:03:48.84#ibcon#read 4, iclass 6, count 0 2006.257.16:03:48.84#ibcon#about to read 5, iclass 6, count 0 2006.257.16:03:48.84#ibcon#read 5, iclass 6, count 0 2006.257.16:03:48.84#ibcon#about to read 6, iclass 6, count 0 2006.257.16:03:48.84#ibcon#read 6, iclass 6, count 0 2006.257.16:03:48.84#ibcon#end of sib2, iclass 6, count 0 2006.257.16:03:48.84#ibcon#*after write, iclass 6, count 0 2006.257.16:03:48.84#ibcon#*before return 0, iclass 6, count 0 2006.257.16:03:48.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:03:48.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:03:48.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:03:48.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:03:48.84$setupk4/ifdk4 2006.257.16:03:48.84$ifdk4/lo= 2006.257.16:03:48.84$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:03:48.84$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:03:48.84$ifdk4/patch= 2006.257.16:03:48.84$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:03:48.84$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:03:48.84$setupk4/!*+20s 2006.257.16:03:55.13#trakl#Source acquired 2006.257.16:03:57.13#flagr#flagr/antenna,acquired 2006.257.16:03:58.00#abcon#<5=/13 1.6 4.2 17.33 971014.0\r\n> 2006.257.16:03:58.02#abcon#{5=INTERFACE CLEAR} 2006.257.16:03:58.08#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:04:03.23$setupk4/"tpicd 2006.257.16:04:03.23$setupk4/echo=off 2006.257.16:04:03.23$setupk4/xlog=off 2006.257.16:04:03.23:!2006.257.16:06:40 2006.257.16:06:40.00:preob 2006.257.16:06:40.14/onsource/TRACKING 2006.257.16:06:40.14:!2006.257.16:06:50 2006.257.16:06:50.00:"tape 2006.257.16:06:50.00:"st=record 2006.257.16:06:50.00:data_valid=on 2006.257.16:06:50.00:midob 2006.257.16:06:51.14/onsource/TRACKING 2006.257.16:06:51.14/wx/17.33,1014.0,97 2006.257.16:06:51.27/cable/+6.4847E-03 2006.257.16:06:52.36/va/01,08,usb,yes,30,33 2006.257.16:06:52.36/va/02,07,usb,yes,33,33 2006.257.16:06:52.36/va/03,08,usb,yes,29,31 2006.257.16:06:52.36/va/04,07,usb,yes,34,35 2006.257.16:06:52.36/va/05,04,usb,yes,30,31 2006.257.16:06:52.36/va/06,04,usb,yes,34,33 2006.257.16:06:52.36/va/07,04,usb,yes,35,35 2006.257.16:06:52.36/va/08,04,usb,yes,29,35 2006.257.16:06:52.59/valo/01,524.99,yes,locked 2006.257.16:06:52.59/valo/02,534.99,yes,locked 2006.257.16:06:52.59/valo/03,564.99,yes,locked 2006.257.16:06:52.59/valo/04,624.99,yes,locked 2006.257.16:06:52.59/valo/05,734.99,yes,locked 2006.257.16:06:52.59/valo/06,814.99,yes,locked 2006.257.16:06:52.59/valo/07,864.99,yes,locked 2006.257.16:06:52.59/valo/08,884.99,yes,locked 2006.257.16:06:53.68/vb/01,04,usb,yes,30,28 2006.257.16:06:53.68/vb/02,05,usb,yes,29,28 2006.257.16:06:53.68/vb/03,04,usb,yes,30,33 2006.257.16:06:53.68/vb/04,05,usb,yes,30,29 2006.257.16:06:53.68/vb/05,04,usb,yes,26,29 2006.257.16:06:53.68/vb/06,04,usb,yes,31,27 2006.257.16:06:53.68/vb/07,04,usb,yes,31,30 2006.257.16:06:53.68/vb/08,04,usb,yes,28,31 2006.257.16:06:53.91/vblo/01,629.99,yes,locked 2006.257.16:06:53.91/vblo/02,634.99,yes,locked 2006.257.16:06:53.91/vblo/03,649.99,yes,locked 2006.257.16:06:53.91/vblo/04,679.99,yes,locked 2006.257.16:06:53.91/vblo/05,709.99,yes,locked 2006.257.16:06:53.91/vblo/06,719.99,yes,locked 2006.257.16:06:53.91/vblo/07,734.99,yes,locked 2006.257.16:06:53.91/vblo/08,744.99,yes,locked 2006.257.16:06:54.06/vabw/8 2006.257.16:06:54.21/vbbw/8 2006.257.16:06:54.30/xfe/off,on,15.0 2006.257.16:06:54.68/ifatt/23,28,28,28 2006.257.16:06:55.07/fmout-gps/S +4.57E-07 2006.257.16:06:55.11:!2006.257.16:12:10 2006.257.16:12:10.00:data_valid=off 2006.257.16:12:10.00:"et 2006.257.16:12:10.00:!+3s 2006.257.16:12:13.01:"tape 2006.257.16:12:13.01:postob 2006.257.16:12:13.20/cable/+6.4814E-03 2006.257.16:12:13.20/wx/17.30,1014.0,97 2006.257.16:12:14.08/fmout-gps/S +4.58E-07 2006.257.16:12:14.08:scan_name=257-1617,jd0609,80 2006.257.16:12:14.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.16:12:15.13#flagr#flagr/antenna,new-source 2006.257.16:12:15.13:checkk5 2006.257.16:12:15.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.16:12:15.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.16:12:16.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.16:12:16.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.16:12:16.84/chk_obsdata//k5ts1/T2571606??a.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.257.16:12:17.17/chk_obsdata//k5ts2/T2571606??b.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.257.16:12:17.50/chk_obsdata//k5ts3/T2571606??c.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.257.16:12:17.83/chk_obsdata//k5ts4/T2571606??d.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.257.16:12:18.50/k5log//k5ts1_log_newline 2006.257.16:12:19.15/k5log//k5ts2_log_newline 2006.257.16:12:19.80/k5log//k5ts3_log_newline 2006.257.16:12:20.45/k5log//k5ts4_log_newline 2006.257.16:12:20.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.16:12:20.48:setupk4=1 2006.257.16:12:20.48$setupk4/echo=on 2006.257.16:12:20.48$setupk4/pcalon 2006.257.16:12:20.48$pcalon/"no phase cal control is implemented here 2006.257.16:12:20.48$setupk4/"tpicd=stop 2006.257.16:12:20.48$setupk4/"rec=synch_on 2006.257.16:12:20.48$setupk4/"rec_mode=128 2006.257.16:12:20.48$setupk4/!* 2006.257.16:12:20.48$setupk4/recpk4 2006.257.16:12:20.48$recpk4/recpatch= 2006.257.16:12:20.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.16:12:20.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.16:12:20.48$setupk4/vck44 2006.257.16:12:20.48$vck44/valo=1,524.99 2006.257.16:12:20.48#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.16:12:20.48#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.16:12:20.48#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:20.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:20.48#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:20.48#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:20.48#ibcon#enter wrdev, iclass 33, count 0 2006.257.16:12:20.48#ibcon#first serial, iclass 33, count 0 2006.257.16:12:20.48#ibcon#enter sib2, iclass 33, count 0 2006.257.16:12:20.48#ibcon#flushed, iclass 33, count 0 2006.257.16:12:20.48#ibcon#about to write, iclass 33, count 0 2006.257.16:12:20.48#ibcon#wrote, iclass 33, count 0 2006.257.16:12:20.48#ibcon#about to read 3, iclass 33, count 0 2006.257.16:12:20.50#ibcon#read 3, iclass 33, count 0 2006.257.16:12:20.50#ibcon#about to read 4, iclass 33, count 0 2006.257.16:12:20.50#ibcon#read 4, iclass 33, count 0 2006.257.16:12:20.50#ibcon#about to read 5, iclass 33, count 0 2006.257.16:12:20.50#ibcon#read 5, iclass 33, count 0 2006.257.16:12:20.50#ibcon#about to read 6, iclass 33, count 0 2006.257.16:12:20.50#ibcon#read 6, iclass 33, count 0 2006.257.16:12:20.50#ibcon#end of sib2, iclass 33, count 0 2006.257.16:12:20.50#ibcon#*mode == 0, iclass 33, count 0 2006.257.16:12:20.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.16:12:20.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.16:12:20.50#ibcon#*before write, iclass 33, count 0 2006.257.16:12:20.50#ibcon#enter sib2, iclass 33, count 0 2006.257.16:12:20.50#ibcon#flushed, iclass 33, count 0 2006.257.16:12:20.50#ibcon#about to write, iclass 33, count 0 2006.257.16:12:20.50#ibcon#wrote, iclass 33, count 0 2006.257.16:12:20.50#ibcon#about to read 3, iclass 33, count 0 2006.257.16:12:20.55#ibcon#read 3, iclass 33, count 0 2006.257.16:12:20.55#ibcon#about to read 4, iclass 33, count 0 2006.257.16:12:20.55#ibcon#read 4, iclass 33, count 0 2006.257.16:12:20.55#ibcon#about to read 5, iclass 33, count 0 2006.257.16:12:20.55#ibcon#read 5, iclass 33, count 0 2006.257.16:12:20.55#ibcon#about to read 6, iclass 33, count 0 2006.257.16:12:20.55#ibcon#read 6, iclass 33, count 0 2006.257.16:12:20.55#ibcon#end of sib2, iclass 33, count 0 2006.257.16:12:20.55#ibcon#*after write, iclass 33, count 0 2006.257.16:12:20.55#ibcon#*before return 0, iclass 33, count 0 2006.257.16:12:20.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:20.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:20.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.16:12:20.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.16:12:20.55$vck44/va=1,8 2006.257.16:12:20.55#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.16:12:20.55#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.16:12:20.55#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:20.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:20.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:20.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:20.55#ibcon#enter wrdev, iclass 35, count 2 2006.257.16:12:20.55#ibcon#first serial, iclass 35, count 2 2006.257.16:12:20.55#ibcon#enter sib2, iclass 35, count 2 2006.257.16:12:20.55#ibcon#flushed, iclass 35, count 2 2006.257.16:12:20.55#ibcon#about to write, iclass 35, count 2 2006.257.16:12:20.55#ibcon#wrote, iclass 35, count 2 2006.257.16:12:20.55#ibcon#about to read 3, iclass 35, count 2 2006.257.16:12:20.57#ibcon#read 3, iclass 35, count 2 2006.257.16:12:20.57#ibcon#about to read 4, iclass 35, count 2 2006.257.16:12:20.57#ibcon#read 4, iclass 35, count 2 2006.257.16:12:20.57#ibcon#about to read 5, iclass 35, count 2 2006.257.16:12:20.57#ibcon#read 5, iclass 35, count 2 2006.257.16:12:20.57#ibcon#about to read 6, iclass 35, count 2 2006.257.16:12:20.57#ibcon#read 6, iclass 35, count 2 2006.257.16:12:20.57#ibcon#end of sib2, iclass 35, count 2 2006.257.16:12:20.57#ibcon#*mode == 0, iclass 35, count 2 2006.257.16:12:20.57#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.16:12:20.57#ibcon#[25=AT01-08\r\n] 2006.257.16:12:20.57#ibcon#*before write, iclass 35, count 2 2006.257.16:12:20.57#ibcon#enter sib2, iclass 35, count 2 2006.257.16:12:20.57#ibcon#flushed, iclass 35, count 2 2006.257.16:12:20.57#ibcon#about to write, iclass 35, count 2 2006.257.16:12:20.57#ibcon#wrote, iclass 35, count 2 2006.257.16:12:20.57#ibcon#about to read 3, iclass 35, count 2 2006.257.16:12:20.60#ibcon#read 3, iclass 35, count 2 2006.257.16:12:20.60#ibcon#about to read 4, iclass 35, count 2 2006.257.16:12:20.60#ibcon#read 4, iclass 35, count 2 2006.257.16:12:20.60#ibcon#about to read 5, iclass 35, count 2 2006.257.16:12:20.60#ibcon#read 5, iclass 35, count 2 2006.257.16:12:20.60#ibcon#about to read 6, iclass 35, count 2 2006.257.16:12:20.60#ibcon#read 6, iclass 35, count 2 2006.257.16:12:20.60#ibcon#end of sib2, iclass 35, count 2 2006.257.16:12:20.60#ibcon#*after write, iclass 35, count 2 2006.257.16:12:20.60#ibcon#*before return 0, iclass 35, count 2 2006.257.16:12:20.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:20.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:20.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.16:12:20.60#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:20.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:20.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:20.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:20.72#ibcon#enter wrdev, iclass 35, count 0 2006.257.16:12:20.72#ibcon#first serial, iclass 35, count 0 2006.257.16:12:20.72#ibcon#enter sib2, iclass 35, count 0 2006.257.16:12:20.72#ibcon#flushed, iclass 35, count 0 2006.257.16:12:20.72#ibcon#about to write, iclass 35, count 0 2006.257.16:12:20.72#ibcon#wrote, iclass 35, count 0 2006.257.16:12:20.72#ibcon#about to read 3, iclass 35, count 0 2006.257.16:12:20.74#ibcon#read 3, iclass 35, count 0 2006.257.16:12:20.74#ibcon#about to read 4, iclass 35, count 0 2006.257.16:12:20.74#ibcon#read 4, iclass 35, count 0 2006.257.16:12:20.74#ibcon#about to read 5, iclass 35, count 0 2006.257.16:12:20.74#ibcon#read 5, iclass 35, count 0 2006.257.16:12:20.74#ibcon#about to read 6, iclass 35, count 0 2006.257.16:12:20.74#ibcon#read 6, iclass 35, count 0 2006.257.16:12:20.74#ibcon#end of sib2, iclass 35, count 0 2006.257.16:12:20.74#ibcon#*mode == 0, iclass 35, count 0 2006.257.16:12:20.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.16:12:20.74#ibcon#[25=USB\r\n] 2006.257.16:12:20.74#ibcon#*before write, iclass 35, count 0 2006.257.16:12:20.74#ibcon#enter sib2, iclass 35, count 0 2006.257.16:12:20.74#ibcon#flushed, iclass 35, count 0 2006.257.16:12:20.74#ibcon#about to write, iclass 35, count 0 2006.257.16:12:20.74#ibcon#wrote, iclass 35, count 0 2006.257.16:12:20.74#ibcon#about to read 3, iclass 35, count 0 2006.257.16:12:20.77#ibcon#read 3, iclass 35, count 0 2006.257.16:12:20.77#ibcon#about to read 4, iclass 35, count 0 2006.257.16:12:20.77#ibcon#read 4, iclass 35, count 0 2006.257.16:12:20.77#ibcon#about to read 5, iclass 35, count 0 2006.257.16:12:20.77#ibcon#read 5, iclass 35, count 0 2006.257.16:12:20.77#ibcon#about to read 6, iclass 35, count 0 2006.257.16:12:20.77#ibcon#read 6, iclass 35, count 0 2006.257.16:12:20.77#ibcon#end of sib2, iclass 35, count 0 2006.257.16:12:20.77#ibcon#*after write, iclass 35, count 0 2006.257.16:12:20.77#ibcon#*before return 0, iclass 35, count 0 2006.257.16:12:20.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:20.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:20.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.16:12:20.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.16:12:20.77$vck44/valo=2,534.99 2006.257.16:12:20.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.16:12:20.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.16:12:20.77#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:20.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:20.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:20.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:20.77#ibcon#enter wrdev, iclass 37, count 0 2006.257.16:12:20.77#ibcon#first serial, iclass 37, count 0 2006.257.16:12:20.77#ibcon#enter sib2, iclass 37, count 0 2006.257.16:12:20.77#ibcon#flushed, iclass 37, count 0 2006.257.16:12:20.77#ibcon#about to write, iclass 37, count 0 2006.257.16:12:20.77#ibcon#wrote, iclass 37, count 0 2006.257.16:12:20.77#ibcon#about to read 3, iclass 37, count 0 2006.257.16:12:20.79#ibcon#read 3, iclass 37, count 0 2006.257.16:12:20.79#ibcon#about to read 4, iclass 37, count 0 2006.257.16:12:20.79#ibcon#read 4, iclass 37, count 0 2006.257.16:12:20.79#ibcon#about to read 5, iclass 37, count 0 2006.257.16:12:20.79#ibcon#read 5, iclass 37, count 0 2006.257.16:12:20.79#ibcon#about to read 6, iclass 37, count 0 2006.257.16:12:20.79#ibcon#read 6, iclass 37, count 0 2006.257.16:12:20.79#ibcon#end of sib2, iclass 37, count 0 2006.257.16:12:20.79#ibcon#*mode == 0, iclass 37, count 0 2006.257.16:12:20.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.16:12:20.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.16:12:20.79#ibcon#*before write, iclass 37, count 0 2006.257.16:12:20.79#ibcon#enter sib2, iclass 37, count 0 2006.257.16:12:20.79#ibcon#flushed, iclass 37, count 0 2006.257.16:12:20.79#ibcon#about to write, iclass 37, count 0 2006.257.16:12:20.79#ibcon#wrote, iclass 37, count 0 2006.257.16:12:20.79#ibcon#about to read 3, iclass 37, count 0 2006.257.16:12:20.83#ibcon#read 3, iclass 37, count 0 2006.257.16:12:20.83#ibcon#about to read 4, iclass 37, count 0 2006.257.16:12:20.83#ibcon#read 4, iclass 37, count 0 2006.257.16:12:20.83#ibcon#about to read 5, iclass 37, count 0 2006.257.16:12:20.83#ibcon#read 5, iclass 37, count 0 2006.257.16:12:20.83#ibcon#about to read 6, iclass 37, count 0 2006.257.16:12:20.83#ibcon#read 6, iclass 37, count 0 2006.257.16:12:20.83#ibcon#end of sib2, iclass 37, count 0 2006.257.16:12:20.83#ibcon#*after write, iclass 37, count 0 2006.257.16:12:20.83#ibcon#*before return 0, iclass 37, count 0 2006.257.16:12:20.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:20.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:20.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.16:12:20.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.16:12:20.83$vck44/va=2,7 2006.257.16:12:20.83#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.16:12:20.83#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.16:12:20.83#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:20.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:20.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:20.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:20.89#ibcon#enter wrdev, iclass 39, count 2 2006.257.16:12:20.89#ibcon#first serial, iclass 39, count 2 2006.257.16:12:20.89#ibcon#enter sib2, iclass 39, count 2 2006.257.16:12:20.89#ibcon#flushed, iclass 39, count 2 2006.257.16:12:20.89#ibcon#about to write, iclass 39, count 2 2006.257.16:12:20.89#ibcon#wrote, iclass 39, count 2 2006.257.16:12:20.89#ibcon#about to read 3, iclass 39, count 2 2006.257.16:12:20.91#ibcon#read 3, iclass 39, count 2 2006.257.16:12:20.91#ibcon#about to read 4, iclass 39, count 2 2006.257.16:12:20.91#ibcon#read 4, iclass 39, count 2 2006.257.16:12:20.91#ibcon#about to read 5, iclass 39, count 2 2006.257.16:12:20.91#ibcon#read 5, iclass 39, count 2 2006.257.16:12:20.91#ibcon#about to read 6, iclass 39, count 2 2006.257.16:12:20.91#ibcon#read 6, iclass 39, count 2 2006.257.16:12:20.91#ibcon#end of sib2, iclass 39, count 2 2006.257.16:12:20.91#ibcon#*mode == 0, iclass 39, count 2 2006.257.16:12:20.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.16:12:20.91#ibcon#[25=AT02-07\r\n] 2006.257.16:12:20.91#ibcon#*before write, iclass 39, count 2 2006.257.16:12:20.91#ibcon#enter sib2, iclass 39, count 2 2006.257.16:12:20.91#ibcon#flushed, iclass 39, count 2 2006.257.16:12:20.91#ibcon#about to write, iclass 39, count 2 2006.257.16:12:20.91#ibcon#wrote, iclass 39, count 2 2006.257.16:12:20.91#ibcon#about to read 3, iclass 39, count 2 2006.257.16:12:20.94#ibcon#read 3, iclass 39, count 2 2006.257.16:12:20.94#ibcon#about to read 4, iclass 39, count 2 2006.257.16:12:20.94#ibcon#read 4, iclass 39, count 2 2006.257.16:12:20.94#ibcon#about to read 5, iclass 39, count 2 2006.257.16:12:20.94#ibcon#read 5, iclass 39, count 2 2006.257.16:12:20.94#ibcon#about to read 6, iclass 39, count 2 2006.257.16:12:20.94#ibcon#read 6, iclass 39, count 2 2006.257.16:12:20.94#ibcon#end of sib2, iclass 39, count 2 2006.257.16:12:20.94#ibcon#*after write, iclass 39, count 2 2006.257.16:12:20.94#ibcon#*before return 0, iclass 39, count 2 2006.257.16:12:20.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:20.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:20.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.16:12:20.94#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:20.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:21.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:21.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:21.06#ibcon#enter wrdev, iclass 39, count 0 2006.257.16:12:21.06#ibcon#first serial, iclass 39, count 0 2006.257.16:12:21.06#ibcon#enter sib2, iclass 39, count 0 2006.257.16:12:21.06#ibcon#flushed, iclass 39, count 0 2006.257.16:12:21.06#ibcon#about to write, iclass 39, count 0 2006.257.16:12:21.06#ibcon#wrote, iclass 39, count 0 2006.257.16:12:21.06#ibcon#about to read 3, iclass 39, count 0 2006.257.16:12:21.08#ibcon#read 3, iclass 39, count 0 2006.257.16:12:21.08#ibcon#about to read 4, iclass 39, count 0 2006.257.16:12:21.08#ibcon#read 4, iclass 39, count 0 2006.257.16:12:21.08#ibcon#about to read 5, iclass 39, count 0 2006.257.16:12:21.08#ibcon#read 5, iclass 39, count 0 2006.257.16:12:21.08#ibcon#about to read 6, iclass 39, count 0 2006.257.16:12:21.08#ibcon#read 6, iclass 39, count 0 2006.257.16:12:21.08#ibcon#end of sib2, iclass 39, count 0 2006.257.16:12:21.08#ibcon#*mode == 0, iclass 39, count 0 2006.257.16:12:21.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.16:12:21.08#ibcon#[25=USB\r\n] 2006.257.16:12:21.08#ibcon#*before write, iclass 39, count 0 2006.257.16:12:21.08#ibcon#enter sib2, iclass 39, count 0 2006.257.16:12:21.08#ibcon#flushed, iclass 39, count 0 2006.257.16:12:21.08#ibcon#about to write, iclass 39, count 0 2006.257.16:12:21.08#ibcon#wrote, iclass 39, count 0 2006.257.16:12:21.08#ibcon#about to read 3, iclass 39, count 0 2006.257.16:12:21.11#ibcon#read 3, iclass 39, count 0 2006.257.16:12:21.11#ibcon#about to read 4, iclass 39, count 0 2006.257.16:12:21.11#ibcon#read 4, iclass 39, count 0 2006.257.16:12:21.11#ibcon#about to read 5, iclass 39, count 0 2006.257.16:12:21.11#ibcon#read 5, iclass 39, count 0 2006.257.16:12:21.11#ibcon#about to read 6, iclass 39, count 0 2006.257.16:12:21.11#ibcon#read 6, iclass 39, count 0 2006.257.16:12:21.11#ibcon#end of sib2, iclass 39, count 0 2006.257.16:12:21.11#ibcon#*after write, iclass 39, count 0 2006.257.16:12:21.11#ibcon#*before return 0, iclass 39, count 0 2006.257.16:12:21.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:21.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:21.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.16:12:21.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.16:12:21.11$vck44/valo=3,564.99 2006.257.16:12:21.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.16:12:21.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.16:12:21.11#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:21.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:21.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:21.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:21.11#ibcon#enter wrdev, iclass 3, count 0 2006.257.16:12:21.11#ibcon#first serial, iclass 3, count 0 2006.257.16:12:21.11#ibcon#enter sib2, iclass 3, count 0 2006.257.16:12:21.11#ibcon#flushed, iclass 3, count 0 2006.257.16:12:21.11#ibcon#about to write, iclass 3, count 0 2006.257.16:12:21.11#ibcon#wrote, iclass 3, count 0 2006.257.16:12:21.11#ibcon#about to read 3, iclass 3, count 0 2006.257.16:12:21.13#ibcon#read 3, iclass 3, count 0 2006.257.16:12:21.13#ibcon#about to read 4, iclass 3, count 0 2006.257.16:12:21.13#ibcon#read 4, iclass 3, count 0 2006.257.16:12:21.13#ibcon#about to read 5, iclass 3, count 0 2006.257.16:12:21.13#ibcon#read 5, iclass 3, count 0 2006.257.16:12:21.13#ibcon#about to read 6, iclass 3, count 0 2006.257.16:12:21.13#ibcon#read 6, iclass 3, count 0 2006.257.16:12:21.13#ibcon#end of sib2, iclass 3, count 0 2006.257.16:12:21.13#ibcon#*mode == 0, iclass 3, count 0 2006.257.16:12:21.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.16:12:21.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.16:12:21.13#ibcon#*before write, iclass 3, count 0 2006.257.16:12:21.13#ibcon#enter sib2, iclass 3, count 0 2006.257.16:12:21.13#ibcon#flushed, iclass 3, count 0 2006.257.16:12:21.13#ibcon#about to write, iclass 3, count 0 2006.257.16:12:21.13#ibcon#wrote, iclass 3, count 0 2006.257.16:12:21.13#ibcon#about to read 3, iclass 3, count 0 2006.257.16:12:21.17#ibcon#read 3, iclass 3, count 0 2006.257.16:12:21.17#ibcon#about to read 4, iclass 3, count 0 2006.257.16:12:21.17#ibcon#read 4, iclass 3, count 0 2006.257.16:12:21.17#ibcon#about to read 5, iclass 3, count 0 2006.257.16:12:21.17#ibcon#read 5, iclass 3, count 0 2006.257.16:12:21.17#ibcon#about to read 6, iclass 3, count 0 2006.257.16:12:21.17#ibcon#read 6, iclass 3, count 0 2006.257.16:12:21.17#ibcon#end of sib2, iclass 3, count 0 2006.257.16:12:21.17#ibcon#*after write, iclass 3, count 0 2006.257.16:12:21.17#ibcon#*before return 0, iclass 3, count 0 2006.257.16:12:21.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:21.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:21.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.16:12:21.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.16:12:21.17$vck44/va=3,8 2006.257.16:12:21.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.16:12:21.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.16:12:21.17#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:21.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:21.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:21.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:21.23#ibcon#enter wrdev, iclass 5, count 2 2006.257.16:12:21.23#ibcon#first serial, iclass 5, count 2 2006.257.16:12:21.23#ibcon#enter sib2, iclass 5, count 2 2006.257.16:12:21.23#ibcon#flushed, iclass 5, count 2 2006.257.16:12:21.23#ibcon#about to write, iclass 5, count 2 2006.257.16:12:21.23#ibcon#wrote, iclass 5, count 2 2006.257.16:12:21.23#ibcon#about to read 3, iclass 5, count 2 2006.257.16:12:21.25#ibcon#read 3, iclass 5, count 2 2006.257.16:12:21.25#ibcon#about to read 4, iclass 5, count 2 2006.257.16:12:21.25#ibcon#read 4, iclass 5, count 2 2006.257.16:12:21.25#ibcon#about to read 5, iclass 5, count 2 2006.257.16:12:21.25#ibcon#read 5, iclass 5, count 2 2006.257.16:12:21.25#ibcon#about to read 6, iclass 5, count 2 2006.257.16:12:21.25#ibcon#read 6, iclass 5, count 2 2006.257.16:12:21.25#ibcon#end of sib2, iclass 5, count 2 2006.257.16:12:21.25#ibcon#*mode == 0, iclass 5, count 2 2006.257.16:12:21.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.16:12:21.25#ibcon#[25=AT03-08\r\n] 2006.257.16:12:21.25#ibcon#*before write, iclass 5, count 2 2006.257.16:12:21.25#ibcon#enter sib2, iclass 5, count 2 2006.257.16:12:21.25#ibcon#flushed, iclass 5, count 2 2006.257.16:12:21.25#ibcon#about to write, iclass 5, count 2 2006.257.16:12:21.25#ibcon#wrote, iclass 5, count 2 2006.257.16:12:21.25#ibcon#about to read 3, iclass 5, count 2 2006.257.16:12:21.28#ibcon#read 3, iclass 5, count 2 2006.257.16:12:21.28#ibcon#about to read 4, iclass 5, count 2 2006.257.16:12:21.28#ibcon#read 4, iclass 5, count 2 2006.257.16:12:21.28#ibcon#about to read 5, iclass 5, count 2 2006.257.16:12:21.28#ibcon#read 5, iclass 5, count 2 2006.257.16:12:21.28#ibcon#about to read 6, iclass 5, count 2 2006.257.16:12:21.28#ibcon#read 6, iclass 5, count 2 2006.257.16:12:21.28#ibcon#end of sib2, iclass 5, count 2 2006.257.16:12:21.28#ibcon#*after write, iclass 5, count 2 2006.257.16:12:21.28#ibcon#*before return 0, iclass 5, count 2 2006.257.16:12:21.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:21.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:21.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.16:12:21.28#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:21.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:21.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:21.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:21.40#ibcon#enter wrdev, iclass 5, count 0 2006.257.16:12:21.40#ibcon#first serial, iclass 5, count 0 2006.257.16:12:21.40#ibcon#enter sib2, iclass 5, count 0 2006.257.16:12:21.40#ibcon#flushed, iclass 5, count 0 2006.257.16:12:21.40#ibcon#about to write, iclass 5, count 0 2006.257.16:12:21.40#ibcon#wrote, iclass 5, count 0 2006.257.16:12:21.40#ibcon#about to read 3, iclass 5, count 0 2006.257.16:12:21.42#ibcon#read 3, iclass 5, count 0 2006.257.16:12:21.42#ibcon#about to read 4, iclass 5, count 0 2006.257.16:12:21.42#ibcon#read 4, iclass 5, count 0 2006.257.16:12:21.42#ibcon#about to read 5, iclass 5, count 0 2006.257.16:12:21.42#ibcon#read 5, iclass 5, count 0 2006.257.16:12:21.42#ibcon#about to read 6, iclass 5, count 0 2006.257.16:12:21.42#ibcon#read 6, iclass 5, count 0 2006.257.16:12:21.42#ibcon#end of sib2, iclass 5, count 0 2006.257.16:12:21.42#ibcon#*mode == 0, iclass 5, count 0 2006.257.16:12:21.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.16:12:21.42#ibcon#[25=USB\r\n] 2006.257.16:12:21.42#ibcon#*before write, iclass 5, count 0 2006.257.16:12:21.42#ibcon#enter sib2, iclass 5, count 0 2006.257.16:12:21.42#ibcon#flushed, iclass 5, count 0 2006.257.16:12:21.42#ibcon#about to write, iclass 5, count 0 2006.257.16:12:21.42#ibcon#wrote, iclass 5, count 0 2006.257.16:12:21.42#ibcon#about to read 3, iclass 5, count 0 2006.257.16:12:21.45#ibcon#read 3, iclass 5, count 0 2006.257.16:12:21.45#ibcon#about to read 4, iclass 5, count 0 2006.257.16:12:21.45#ibcon#read 4, iclass 5, count 0 2006.257.16:12:21.45#ibcon#about to read 5, iclass 5, count 0 2006.257.16:12:21.45#ibcon#read 5, iclass 5, count 0 2006.257.16:12:21.45#ibcon#about to read 6, iclass 5, count 0 2006.257.16:12:21.45#ibcon#read 6, iclass 5, count 0 2006.257.16:12:21.45#ibcon#end of sib2, iclass 5, count 0 2006.257.16:12:21.45#ibcon#*after write, iclass 5, count 0 2006.257.16:12:21.45#ibcon#*before return 0, iclass 5, count 0 2006.257.16:12:21.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:21.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:21.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.16:12:21.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.16:12:21.45$vck44/valo=4,624.99 2006.257.16:12:21.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.16:12:21.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.16:12:21.45#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:21.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:21.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:21.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:21.45#ibcon#enter wrdev, iclass 7, count 0 2006.257.16:12:21.45#ibcon#first serial, iclass 7, count 0 2006.257.16:12:21.45#ibcon#enter sib2, iclass 7, count 0 2006.257.16:12:21.45#ibcon#flushed, iclass 7, count 0 2006.257.16:12:21.45#ibcon#about to write, iclass 7, count 0 2006.257.16:12:21.45#ibcon#wrote, iclass 7, count 0 2006.257.16:12:21.45#ibcon#about to read 3, iclass 7, count 0 2006.257.16:12:21.47#ibcon#read 3, iclass 7, count 0 2006.257.16:12:21.47#ibcon#about to read 4, iclass 7, count 0 2006.257.16:12:21.47#ibcon#read 4, iclass 7, count 0 2006.257.16:12:21.47#ibcon#about to read 5, iclass 7, count 0 2006.257.16:12:21.47#ibcon#read 5, iclass 7, count 0 2006.257.16:12:21.47#ibcon#about to read 6, iclass 7, count 0 2006.257.16:12:21.47#ibcon#read 6, iclass 7, count 0 2006.257.16:12:21.47#ibcon#end of sib2, iclass 7, count 0 2006.257.16:12:21.47#ibcon#*mode == 0, iclass 7, count 0 2006.257.16:12:21.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.16:12:21.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.16:12:21.47#ibcon#*before write, iclass 7, count 0 2006.257.16:12:21.47#ibcon#enter sib2, iclass 7, count 0 2006.257.16:12:21.47#ibcon#flushed, iclass 7, count 0 2006.257.16:12:21.47#ibcon#about to write, iclass 7, count 0 2006.257.16:12:21.47#ibcon#wrote, iclass 7, count 0 2006.257.16:12:21.47#ibcon#about to read 3, iclass 7, count 0 2006.257.16:12:21.51#ibcon#read 3, iclass 7, count 0 2006.257.16:12:21.51#ibcon#about to read 4, iclass 7, count 0 2006.257.16:12:21.51#ibcon#read 4, iclass 7, count 0 2006.257.16:12:21.51#ibcon#about to read 5, iclass 7, count 0 2006.257.16:12:21.51#ibcon#read 5, iclass 7, count 0 2006.257.16:12:21.51#ibcon#about to read 6, iclass 7, count 0 2006.257.16:12:21.51#ibcon#read 6, iclass 7, count 0 2006.257.16:12:21.51#ibcon#end of sib2, iclass 7, count 0 2006.257.16:12:21.51#ibcon#*after write, iclass 7, count 0 2006.257.16:12:21.51#ibcon#*before return 0, iclass 7, count 0 2006.257.16:12:21.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:21.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:21.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.16:12:21.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.16:12:21.51$vck44/va=4,7 2006.257.16:12:21.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.16:12:21.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.16:12:21.51#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:21.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:21.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:21.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:21.57#ibcon#enter wrdev, iclass 11, count 2 2006.257.16:12:21.57#ibcon#first serial, iclass 11, count 2 2006.257.16:12:21.57#ibcon#enter sib2, iclass 11, count 2 2006.257.16:12:21.57#ibcon#flushed, iclass 11, count 2 2006.257.16:12:21.57#ibcon#about to write, iclass 11, count 2 2006.257.16:12:21.57#ibcon#wrote, iclass 11, count 2 2006.257.16:12:21.57#ibcon#about to read 3, iclass 11, count 2 2006.257.16:12:21.59#ibcon#read 3, iclass 11, count 2 2006.257.16:12:21.59#ibcon#about to read 4, iclass 11, count 2 2006.257.16:12:21.59#ibcon#read 4, iclass 11, count 2 2006.257.16:12:21.59#ibcon#about to read 5, iclass 11, count 2 2006.257.16:12:21.59#ibcon#read 5, iclass 11, count 2 2006.257.16:12:21.59#ibcon#about to read 6, iclass 11, count 2 2006.257.16:12:21.59#ibcon#read 6, iclass 11, count 2 2006.257.16:12:21.59#ibcon#end of sib2, iclass 11, count 2 2006.257.16:12:21.59#ibcon#*mode == 0, iclass 11, count 2 2006.257.16:12:21.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.16:12:21.59#ibcon#[25=AT04-07\r\n] 2006.257.16:12:21.59#ibcon#*before write, iclass 11, count 2 2006.257.16:12:21.59#ibcon#enter sib2, iclass 11, count 2 2006.257.16:12:21.59#ibcon#flushed, iclass 11, count 2 2006.257.16:12:21.59#ibcon#about to write, iclass 11, count 2 2006.257.16:12:21.59#ibcon#wrote, iclass 11, count 2 2006.257.16:12:21.59#ibcon#about to read 3, iclass 11, count 2 2006.257.16:12:21.62#ibcon#read 3, iclass 11, count 2 2006.257.16:12:21.62#ibcon#about to read 4, iclass 11, count 2 2006.257.16:12:21.62#ibcon#read 4, iclass 11, count 2 2006.257.16:12:21.62#ibcon#about to read 5, iclass 11, count 2 2006.257.16:12:21.62#ibcon#read 5, iclass 11, count 2 2006.257.16:12:21.62#ibcon#about to read 6, iclass 11, count 2 2006.257.16:12:21.62#ibcon#read 6, iclass 11, count 2 2006.257.16:12:21.62#ibcon#end of sib2, iclass 11, count 2 2006.257.16:12:21.62#ibcon#*after write, iclass 11, count 2 2006.257.16:12:21.62#ibcon#*before return 0, iclass 11, count 2 2006.257.16:12:21.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:21.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:21.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.16:12:21.62#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:21.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:21.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:21.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:21.74#ibcon#enter wrdev, iclass 11, count 0 2006.257.16:12:21.74#ibcon#first serial, iclass 11, count 0 2006.257.16:12:21.74#ibcon#enter sib2, iclass 11, count 0 2006.257.16:12:21.74#ibcon#flushed, iclass 11, count 0 2006.257.16:12:21.74#ibcon#about to write, iclass 11, count 0 2006.257.16:12:21.74#ibcon#wrote, iclass 11, count 0 2006.257.16:12:21.74#ibcon#about to read 3, iclass 11, count 0 2006.257.16:12:21.76#ibcon#read 3, iclass 11, count 0 2006.257.16:12:21.76#ibcon#about to read 4, iclass 11, count 0 2006.257.16:12:21.76#ibcon#read 4, iclass 11, count 0 2006.257.16:12:21.76#ibcon#about to read 5, iclass 11, count 0 2006.257.16:12:21.76#ibcon#read 5, iclass 11, count 0 2006.257.16:12:21.76#ibcon#about to read 6, iclass 11, count 0 2006.257.16:12:21.76#ibcon#read 6, iclass 11, count 0 2006.257.16:12:21.76#ibcon#end of sib2, iclass 11, count 0 2006.257.16:12:21.76#ibcon#*mode == 0, iclass 11, count 0 2006.257.16:12:21.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.16:12:21.76#ibcon#[25=USB\r\n] 2006.257.16:12:21.76#ibcon#*before write, iclass 11, count 0 2006.257.16:12:21.76#ibcon#enter sib2, iclass 11, count 0 2006.257.16:12:21.76#ibcon#flushed, iclass 11, count 0 2006.257.16:12:21.76#ibcon#about to write, iclass 11, count 0 2006.257.16:12:21.76#ibcon#wrote, iclass 11, count 0 2006.257.16:12:21.76#ibcon#about to read 3, iclass 11, count 0 2006.257.16:12:21.79#ibcon#read 3, iclass 11, count 0 2006.257.16:12:21.79#ibcon#about to read 4, iclass 11, count 0 2006.257.16:12:21.79#ibcon#read 4, iclass 11, count 0 2006.257.16:12:21.79#ibcon#about to read 5, iclass 11, count 0 2006.257.16:12:21.79#ibcon#read 5, iclass 11, count 0 2006.257.16:12:21.79#ibcon#about to read 6, iclass 11, count 0 2006.257.16:12:21.79#ibcon#read 6, iclass 11, count 0 2006.257.16:12:21.79#ibcon#end of sib2, iclass 11, count 0 2006.257.16:12:21.79#ibcon#*after write, iclass 11, count 0 2006.257.16:12:21.79#ibcon#*before return 0, iclass 11, count 0 2006.257.16:12:21.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:21.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:21.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.16:12:21.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.16:12:21.79$vck44/valo=5,734.99 2006.257.16:12:21.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.16:12:21.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.16:12:21.79#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:21.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:21.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:21.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:21.79#ibcon#enter wrdev, iclass 13, count 0 2006.257.16:12:21.79#ibcon#first serial, iclass 13, count 0 2006.257.16:12:21.79#ibcon#enter sib2, iclass 13, count 0 2006.257.16:12:21.79#ibcon#flushed, iclass 13, count 0 2006.257.16:12:21.79#ibcon#about to write, iclass 13, count 0 2006.257.16:12:21.79#ibcon#wrote, iclass 13, count 0 2006.257.16:12:21.79#ibcon#about to read 3, iclass 13, count 0 2006.257.16:12:21.81#ibcon#read 3, iclass 13, count 0 2006.257.16:12:21.81#ibcon#about to read 4, iclass 13, count 0 2006.257.16:12:21.81#ibcon#read 4, iclass 13, count 0 2006.257.16:12:21.81#ibcon#about to read 5, iclass 13, count 0 2006.257.16:12:21.81#ibcon#read 5, iclass 13, count 0 2006.257.16:12:21.81#ibcon#about to read 6, iclass 13, count 0 2006.257.16:12:21.81#ibcon#read 6, iclass 13, count 0 2006.257.16:12:21.81#ibcon#end of sib2, iclass 13, count 0 2006.257.16:12:21.81#ibcon#*mode == 0, iclass 13, count 0 2006.257.16:12:21.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.16:12:21.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.16:12:21.81#ibcon#*before write, iclass 13, count 0 2006.257.16:12:21.81#ibcon#enter sib2, iclass 13, count 0 2006.257.16:12:21.81#ibcon#flushed, iclass 13, count 0 2006.257.16:12:21.81#ibcon#about to write, iclass 13, count 0 2006.257.16:12:21.81#ibcon#wrote, iclass 13, count 0 2006.257.16:12:21.81#ibcon#about to read 3, iclass 13, count 0 2006.257.16:12:21.85#ibcon#read 3, iclass 13, count 0 2006.257.16:12:21.85#ibcon#about to read 4, iclass 13, count 0 2006.257.16:12:21.85#ibcon#read 4, iclass 13, count 0 2006.257.16:12:21.85#ibcon#about to read 5, iclass 13, count 0 2006.257.16:12:21.85#ibcon#read 5, iclass 13, count 0 2006.257.16:12:21.85#ibcon#about to read 6, iclass 13, count 0 2006.257.16:12:21.85#ibcon#read 6, iclass 13, count 0 2006.257.16:12:21.85#ibcon#end of sib2, iclass 13, count 0 2006.257.16:12:21.85#ibcon#*after write, iclass 13, count 0 2006.257.16:12:21.85#ibcon#*before return 0, iclass 13, count 0 2006.257.16:12:21.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:21.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:21.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.16:12:21.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.16:12:21.85$vck44/va=5,4 2006.257.16:12:21.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.16:12:21.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.16:12:21.85#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:21.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:21.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:21.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:21.91#ibcon#enter wrdev, iclass 15, count 2 2006.257.16:12:21.91#ibcon#first serial, iclass 15, count 2 2006.257.16:12:21.91#ibcon#enter sib2, iclass 15, count 2 2006.257.16:12:21.91#ibcon#flushed, iclass 15, count 2 2006.257.16:12:21.91#ibcon#about to write, iclass 15, count 2 2006.257.16:12:21.91#ibcon#wrote, iclass 15, count 2 2006.257.16:12:21.91#ibcon#about to read 3, iclass 15, count 2 2006.257.16:12:21.93#ibcon#read 3, iclass 15, count 2 2006.257.16:12:21.93#ibcon#about to read 4, iclass 15, count 2 2006.257.16:12:21.93#ibcon#read 4, iclass 15, count 2 2006.257.16:12:21.93#ibcon#about to read 5, iclass 15, count 2 2006.257.16:12:21.93#ibcon#read 5, iclass 15, count 2 2006.257.16:12:21.93#ibcon#about to read 6, iclass 15, count 2 2006.257.16:12:21.93#ibcon#read 6, iclass 15, count 2 2006.257.16:12:21.93#ibcon#end of sib2, iclass 15, count 2 2006.257.16:12:21.93#ibcon#*mode == 0, iclass 15, count 2 2006.257.16:12:21.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.16:12:21.93#ibcon#[25=AT05-04\r\n] 2006.257.16:12:21.93#ibcon#*before write, iclass 15, count 2 2006.257.16:12:21.93#ibcon#enter sib2, iclass 15, count 2 2006.257.16:12:21.93#ibcon#flushed, iclass 15, count 2 2006.257.16:12:21.93#ibcon#about to write, iclass 15, count 2 2006.257.16:12:21.93#ibcon#wrote, iclass 15, count 2 2006.257.16:12:21.93#ibcon#about to read 3, iclass 15, count 2 2006.257.16:12:21.96#ibcon#read 3, iclass 15, count 2 2006.257.16:12:21.96#ibcon#about to read 4, iclass 15, count 2 2006.257.16:12:21.96#ibcon#read 4, iclass 15, count 2 2006.257.16:12:21.96#ibcon#about to read 5, iclass 15, count 2 2006.257.16:12:21.96#ibcon#read 5, iclass 15, count 2 2006.257.16:12:21.96#ibcon#about to read 6, iclass 15, count 2 2006.257.16:12:21.96#ibcon#read 6, iclass 15, count 2 2006.257.16:12:21.96#ibcon#end of sib2, iclass 15, count 2 2006.257.16:12:21.96#ibcon#*after write, iclass 15, count 2 2006.257.16:12:21.96#ibcon#*before return 0, iclass 15, count 2 2006.257.16:12:21.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:21.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:21.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.16:12:21.96#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:21.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:22.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:22.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:22.08#ibcon#enter wrdev, iclass 15, count 0 2006.257.16:12:22.08#ibcon#first serial, iclass 15, count 0 2006.257.16:12:22.08#ibcon#enter sib2, iclass 15, count 0 2006.257.16:12:22.08#ibcon#flushed, iclass 15, count 0 2006.257.16:12:22.08#ibcon#about to write, iclass 15, count 0 2006.257.16:12:22.08#ibcon#wrote, iclass 15, count 0 2006.257.16:12:22.08#ibcon#about to read 3, iclass 15, count 0 2006.257.16:12:22.10#ibcon#read 3, iclass 15, count 0 2006.257.16:12:22.10#ibcon#about to read 4, iclass 15, count 0 2006.257.16:12:22.10#ibcon#read 4, iclass 15, count 0 2006.257.16:12:22.10#ibcon#about to read 5, iclass 15, count 0 2006.257.16:12:22.10#ibcon#read 5, iclass 15, count 0 2006.257.16:12:22.10#ibcon#about to read 6, iclass 15, count 0 2006.257.16:12:22.10#ibcon#read 6, iclass 15, count 0 2006.257.16:12:22.10#ibcon#end of sib2, iclass 15, count 0 2006.257.16:12:22.10#ibcon#*mode == 0, iclass 15, count 0 2006.257.16:12:22.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.16:12:22.10#ibcon#[25=USB\r\n] 2006.257.16:12:22.10#ibcon#*before write, iclass 15, count 0 2006.257.16:12:22.10#ibcon#enter sib2, iclass 15, count 0 2006.257.16:12:22.10#ibcon#flushed, iclass 15, count 0 2006.257.16:12:22.10#ibcon#about to write, iclass 15, count 0 2006.257.16:12:22.10#ibcon#wrote, iclass 15, count 0 2006.257.16:12:22.10#ibcon#about to read 3, iclass 15, count 0 2006.257.16:12:22.13#ibcon#read 3, iclass 15, count 0 2006.257.16:12:22.13#ibcon#about to read 4, iclass 15, count 0 2006.257.16:12:22.13#ibcon#read 4, iclass 15, count 0 2006.257.16:12:22.13#ibcon#about to read 5, iclass 15, count 0 2006.257.16:12:22.13#ibcon#read 5, iclass 15, count 0 2006.257.16:12:22.13#ibcon#about to read 6, iclass 15, count 0 2006.257.16:12:22.13#ibcon#read 6, iclass 15, count 0 2006.257.16:12:22.13#ibcon#end of sib2, iclass 15, count 0 2006.257.16:12:22.13#ibcon#*after write, iclass 15, count 0 2006.257.16:12:22.13#ibcon#*before return 0, iclass 15, count 0 2006.257.16:12:22.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:22.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:22.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.16:12:22.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.16:12:22.13$vck44/valo=6,814.99 2006.257.16:12:22.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.16:12:22.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.16:12:22.13#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:22.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:22.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:22.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:22.13#ibcon#enter wrdev, iclass 17, count 0 2006.257.16:12:22.13#ibcon#first serial, iclass 17, count 0 2006.257.16:12:22.13#ibcon#enter sib2, iclass 17, count 0 2006.257.16:12:22.13#ibcon#flushed, iclass 17, count 0 2006.257.16:12:22.13#ibcon#about to write, iclass 17, count 0 2006.257.16:12:22.13#ibcon#wrote, iclass 17, count 0 2006.257.16:12:22.13#ibcon#about to read 3, iclass 17, count 0 2006.257.16:12:22.15#ibcon#read 3, iclass 17, count 0 2006.257.16:12:22.15#ibcon#about to read 4, iclass 17, count 0 2006.257.16:12:22.15#ibcon#read 4, iclass 17, count 0 2006.257.16:12:22.15#ibcon#about to read 5, iclass 17, count 0 2006.257.16:12:22.15#ibcon#read 5, iclass 17, count 0 2006.257.16:12:22.15#ibcon#about to read 6, iclass 17, count 0 2006.257.16:12:22.15#ibcon#read 6, iclass 17, count 0 2006.257.16:12:22.15#ibcon#end of sib2, iclass 17, count 0 2006.257.16:12:22.15#ibcon#*mode == 0, iclass 17, count 0 2006.257.16:12:22.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.16:12:22.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.16:12:22.15#ibcon#*before write, iclass 17, count 0 2006.257.16:12:22.15#ibcon#enter sib2, iclass 17, count 0 2006.257.16:12:22.15#ibcon#flushed, iclass 17, count 0 2006.257.16:12:22.15#ibcon#about to write, iclass 17, count 0 2006.257.16:12:22.15#ibcon#wrote, iclass 17, count 0 2006.257.16:12:22.15#ibcon#about to read 3, iclass 17, count 0 2006.257.16:12:22.19#ibcon#read 3, iclass 17, count 0 2006.257.16:12:22.19#ibcon#about to read 4, iclass 17, count 0 2006.257.16:12:22.19#ibcon#read 4, iclass 17, count 0 2006.257.16:12:22.19#ibcon#about to read 5, iclass 17, count 0 2006.257.16:12:22.19#ibcon#read 5, iclass 17, count 0 2006.257.16:12:22.19#ibcon#about to read 6, iclass 17, count 0 2006.257.16:12:22.19#ibcon#read 6, iclass 17, count 0 2006.257.16:12:22.19#ibcon#end of sib2, iclass 17, count 0 2006.257.16:12:22.19#ibcon#*after write, iclass 17, count 0 2006.257.16:12:22.19#ibcon#*before return 0, iclass 17, count 0 2006.257.16:12:22.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:22.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:22.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.16:12:22.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.16:12:22.19$vck44/va=6,4 2006.257.16:12:22.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.16:12:22.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.16:12:22.19#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:22.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:22.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:22.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:22.25#ibcon#enter wrdev, iclass 19, count 2 2006.257.16:12:22.25#ibcon#first serial, iclass 19, count 2 2006.257.16:12:22.25#ibcon#enter sib2, iclass 19, count 2 2006.257.16:12:22.25#ibcon#flushed, iclass 19, count 2 2006.257.16:12:22.25#ibcon#about to write, iclass 19, count 2 2006.257.16:12:22.25#ibcon#wrote, iclass 19, count 2 2006.257.16:12:22.25#ibcon#about to read 3, iclass 19, count 2 2006.257.16:12:22.27#ibcon#read 3, iclass 19, count 2 2006.257.16:12:22.27#ibcon#about to read 4, iclass 19, count 2 2006.257.16:12:22.27#ibcon#read 4, iclass 19, count 2 2006.257.16:12:22.27#ibcon#about to read 5, iclass 19, count 2 2006.257.16:12:22.27#ibcon#read 5, iclass 19, count 2 2006.257.16:12:22.27#ibcon#about to read 6, iclass 19, count 2 2006.257.16:12:22.27#ibcon#read 6, iclass 19, count 2 2006.257.16:12:22.27#ibcon#end of sib2, iclass 19, count 2 2006.257.16:12:22.27#ibcon#*mode == 0, iclass 19, count 2 2006.257.16:12:22.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.16:12:22.27#ibcon#[25=AT06-04\r\n] 2006.257.16:12:22.27#ibcon#*before write, iclass 19, count 2 2006.257.16:12:22.27#ibcon#enter sib2, iclass 19, count 2 2006.257.16:12:22.27#ibcon#flushed, iclass 19, count 2 2006.257.16:12:22.27#ibcon#about to write, iclass 19, count 2 2006.257.16:12:22.27#ibcon#wrote, iclass 19, count 2 2006.257.16:12:22.27#ibcon#about to read 3, iclass 19, count 2 2006.257.16:12:22.30#ibcon#read 3, iclass 19, count 2 2006.257.16:12:22.30#ibcon#about to read 4, iclass 19, count 2 2006.257.16:12:22.30#ibcon#read 4, iclass 19, count 2 2006.257.16:12:22.30#ibcon#about to read 5, iclass 19, count 2 2006.257.16:12:22.30#ibcon#read 5, iclass 19, count 2 2006.257.16:12:22.30#ibcon#about to read 6, iclass 19, count 2 2006.257.16:12:22.30#ibcon#read 6, iclass 19, count 2 2006.257.16:12:22.30#ibcon#end of sib2, iclass 19, count 2 2006.257.16:12:22.30#ibcon#*after write, iclass 19, count 2 2006.257.16:12:22.30#ibcon#*before return 0, iclass 19, count 2 2006.257.16:12:22.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:22.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:22.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.16:12:22.30#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:22.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:22.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:22.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:22.42#ibcon#enter wrdev, iclass 19, count 0 2006.257.16:12:22.42#ibcon#first serial, iclass 19, count 0 2006.257.16:12:22.42#ibcon#enter sib2, iclass 19, count 0 2006.257.16:12:22.42#ibcon#flushed, iclass 19, count 0 2006.257.16:12:22.42#ibcon#about to write, iclass 19, count 0 2006.257.16:12:22.42#ibcon#wrote, iclass 19, count 0 2006.257.16:12:22.42#ibcon#about to read 3, iclass 19, count 0 2006.257.16:12:22.44#ibcon#read 3, iclass 19, count 0 2006.257.16:12:22.44#ibcon#about to read 4, iclass 19, count 0 2006.257.16:12:22.44#ibcon#read 4, iclass 19, count 0 2006.257.16:12:22.44#ibcon#about to read 5, iclass 19, count 0 2006.257.16:12:22.44#ibcon#read 5, iclass 19, count 0 2006.257.16:12:22.44#ibcon#about to read 6, iclass 19, count 0 2006.257.16:12:22.44#ibcon#read 6, iclass 19, count 0 2006.257.16:12:22.44#ibcon#end of sib2, iclass 19, count 0 2006.257.16:12:22.44#ibcon#*mode == 0, iclass 19, count 0 2006.257.16:12:22.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.16:12:22.44#ibcon#[25=USB\r\n] 2006.257.16:12:22.44#ibcon#*before write, iclass 19, count 0 2006.257.16:12:22.44#ibcon#enter sib2, iclass 19, count 0 2006.257.16:12:22.44#ibcon#flushed, iclass 19, count 0 2006.257.16:12:22.44#ibcon#about to write, iclass 19, count 0 2006.257.16:12:22.44#ibcon#wrote, iclass 19, count 0 2006.257.16:12:22.44#ibcon#about to read 3, iclass 19, count 0 2006.257.16:12:22.47#ibcon#read 3, iclass 19, count 0 2006.257.16:12:22.47#ibcon#about to read 4, iclass 19, count 0 2006.257.16:12:22.47#ibcon#read 4, iclass 19, count 0 2006.257.16:12:22.47#ibcon#about to read 5, iclass 19, count 0 2006.257.16:12:22.47#ibcon#read 5, iclass 19, count 0 2006.257.16:12:22.47#ibcon#about to read 6, iclass 19, count 0 2006.257.16:12:22.47#ibcon#read 6, iclass 19, count 0 2006.257.16:12:22.47#ibcon#end of sib2, iclass 19, count 0 2006.257.16:12:22.47#ibcon#*after write, iclass 19, count 0 2006.257.16:12:22.47#ibcon#*before return 0, iclass 19, count 0 2006.257.16:12:22.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:22.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:22.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.16:12:22.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.16:12:22.47$vck44/valo=7,864.99 2006.257.16:12:22.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.16:12:22.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.16:12:22.47#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:22.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:22.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:22.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:22.47#ibcon#enter wrdev, iclass 21, count 0 2006.257.16:12:22.47#ibcon#first serial, iclass 21, count 0 2006.257.16:12:22.47#ibcon#enter sib2, iclass 21, count 0 2006.257.16:12:22.47#ibcon#flushed, iclass 21, count 0 2006.257.16:12:22.47#ibcon#about to write, iclass 21, count 0 2006.257.16:12:22.47#ibcon#wrote, iclass 21, count 0 2006.257.16:12:22.47#ibcon#about to read 3, iclass 21, count 0 2006.257.16:12:22.49#ibcon#read 3, iclass 21, count 0 2006.257.16:12:22.49#ibcon#about to read 4, iclass 21, count 0 2006.257.16:12:22.49#ibcon#read 4, iclass 21, count 0 2006.257.16:12:22.49#ibcon#about to read 5, iclass 21, count 0 2006.257.16:12:22.49#ibcon#read 5, iclass 21, count 0 2006.257.16:12:22.49#ibcon#about to read 6, iclass 21, count 0 2006.257.16:12:22.49#ibcon#read 6, iclass 21, count 0 2006.257.16:12:22.49#ibcon#end of sib2, iclass 21, count 0 2006.257.16:12:22.49#ibcon#*mode == 0, iclass 21, count 0 2006.257.16:12:22.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.16:12:22.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.16:12:22.49#ibcon#*before write, iclass 21, count 0 2006.257.16:12:22.49#ibcon#enter sib2, iclass 21, count 0 2006.257.16:12:22.49#ibcon#flushed, iclass 21, count 0 2006.257.16:12:22.49#ibcon#about to write, iclass 21, count 0 2006.257.16:12:22.49#ibcon#wrote, iclass 21, count 0 2006.257.16:12:22.49#ibcon#about to read 3, iclass 21, count 0 2006.257.16:12:22.53#ibcon#read 3, iclass 21, count 0 2006.257.16:12:22.53#ibcon#about to read 4, iclass 21, count 0 2006.257.16:12:22.53#ibcon#read 4, iclass 21, count 0 2006.257.16:12:22.53#ibcon#about to read 5, iclass 21, count 0 2006.257.16:12:22.53#ibcon#read 5, iclass 21, count 0 2006.257.16:12:22.53#ibcon#about to read 6, iclass 21, count 0 2006.257.16:12:22.53#ibcon#read 6, iclass 21, count 0 2006.257.16:12:22.53#ibcon#end of sib2, iclass 21, count 0 2006.257.16:12:22.53#ibcon#*after write, iclass 21, count 0 2006.257.16:12:22.53#ibcon#*before return 0, iclass 21, count 0 2006.257.16:12:22.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:22.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:22.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.16:12:22.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.16:12:22.53$vck44/va=7,4 2006.257.16:12:22.53#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.16:12:22.53#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.16:12:22.53#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:22.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:22.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:22.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:22.59#ibcon#enter wrdev, iclass 23, count 2 2006.257.16:12:22.59#ibcon#first serial, iclass 23, count 2 2006.257.16:12:22.59#ibcon#enter sib2, iclass 23, count 2 2006.257.16:12:22.59#ibcon#flushed, iclass 23, count 2 2006.257.16:12:22.59#ibcon#about to write, iclass 23, count 2 2006.257.16:12:22.59#ibcon#wrote, iclass 23, count 2 2006.257.16:12:22.59#ibcon#about to read 3, iclass 23, count 2 2006.257.16:12:22.61#ibcon#read 3, iclass 23, count 2 2006.257.16:12:22.61#ibcon#about to read 4, iclass 23, count 2 2006.257.16:12:22.61#ibcon#read 4, iclass 23, count 2 2006.257.16:12:22.61#ibcon#about to read 5, iclass 23, count 2 2006.257.16:12:22.61#ibcon#read 5, iclass 23, count 2 2006.257.16:12:22.61#ibcon#about to read 6, iclass 23, count 2 2006.257.16:12:22.61#ibcon#read 6, iclass 23, count 2 2006.257.16:12:22.61#ibcon#end of sib2, iclass 23, count 2 2006.257.16:12:22.61#ibcon#*mode == 0, iclass 23, count 2 2006.257.16:12:22.61#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.16:12:22.61#ibcon#[25=AT07-04\r\n] 2006.257.16:12:22.61#ibcon#*before write, iclass 23, count 2 2006.257.16:12:22.61#ibcon#enter sib2, iclass 23, count 2 2006.257.16:12:22.61#ibcon#flushed, iclass 23, count 2 2006.257.16:12:22.61#ibcon#about to write, iclass 23, count 2 2006.257.16:12:22.61#ibcon#wrote, iclass 23, count 2 2006.257.16:12:22.61#ibcon#about to read 3, iclass 23, count 2 2006.257.16:12:22.64#ibcon#read 3, iclass 23, count 2 2006.257.16:12:22.64#ibcon#about to read 4, iclass 23, count 2 2006.257.16:12:22.64#ibcon#read 4, iclass 23, count 2 2006.257.16:12:22.64#ibcon#about to read 5, iclass 23, count 2 2006.257.16:12:22.64#ibcon#read 5, iclass 23, count 2 2006.257.16:12:22.64#ibcon#about to read 6, iclass 23, count 2 2006.257.16:12:22.64#ibcon#read 6, iclass 23, count 2 2006.257.16:12:22.64#ibcon#end of sib2, iclass 23, count 2 2006.257.16:12:22.64#ibcon#*after write, iclass 23, count 2 2006.257.16:12:22.64#ibcon#*before return 0, iclass 23, count 2 2006.257.16:12:22.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:22.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:22.64#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.16:12:22.64#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:22.64#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:22.76#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:22.76#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:22.76#ibcon#enter wrdev, iclass 23, count 0 2006.257.16:12:22.76#ibcon#first serial, iclass 23, count 0 2006.257.16:12:22.76#ibcon#enter sib2, iclass 23, count 0 2006.257.16:12:22.76#ibcon#flushed, iclass 23, count 0 2006.257.16:12:22.76#ibcon#about to write, iclass 23, count 0 2006.257.16:12:22.76#ibcon#wrote, iclass 23, count 0 2006.257.16:12:22.76#ibcon#about to read 3, iclass 23, count 0 2006.257.16:12:22.78#ibcon#read 3, iclass 23, count 0 2006.257.16:12:22.78#ibcon#about to read 4, iclass 23, count 0 2006.257.16:12:22.78#ibcon#read 4, iclass 23, count 0 2006.257.16:12:22.78#ibcon#about to read 5, iclass 23, count 0 2006.257.16:12:22.78#ibcon#read 5, iclass 23, count 0 2006.257.16:12:22.78#ibcon#about to read 6, iclass 23, count 0 2006.257.16:12:22.78#ibcon#read 6, iclass 23, count 0 2006.257.16:12:22.78#ibcon#end of sib2, iclass 23, count 0 2006.257.16:12:22.78#ibcon#*mode == 0, iclass 23, count 0 2006.257.16:12:22.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.16:12:22.78#ibcon#[25=USB\r\n] 2006.257.16:12:22.78#ibcon#*before write, iclass 23, count 0 2006.257.16:12:22.78#ibcon#enter sib2, iclass 23, count 0 2006.257.16:12:22.78#ibcon#flushed, iclass 23, count 0 2006.257.16:12:22.78#ibcon#about to write, iclass 23, count 0 2006.257.16:12:22.78#ibcon#wrote, iclass 23, count 0 2006.257.16:12:22.78#ibcon#about to read 3, iclass 23, count 0 2006.257.16:12:22.81#ibcon#read 3, iclass 23, count 0 2006.257.16:12:22.81#ibcon#about to read 4, iclass 23, count 0 2006.257.16:12:22.81#ibcon#read 4, iclass 23, count 0 2006.257.16:12:22.81#ibcon#about to read 5, iclass 23, count 0 2006.257.16:12:22.81#ibcon#read 5, iclass 23, count 0 2006.257.16:12:22.81#ibcon#about to read 6, iclass 23, count 0 2006.257.16:12:22.81#ibcon#read 6, iclass 23, count 0 2006.257.16:12:22.81#ibcon#end of sib2, iclass 23, count 0 2006.257.16:12:22.81#ibcon#*after write, iclass 23, count 0 2006.257.16:12:22.81#ibcon#*before return 0, iclass 23, count 0 2006.257.16:12:22.81#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:22.81#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:22.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.16:12:22.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.16:12:22.81$vck44/valo=8,884.99 2006.257.16:12:22.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.16:12:22.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.16:12:22.81#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:22.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:22.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:22.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:22.81#ibcon#enter wrdev, iclass 25, count 0 2006.257.16:12:22.81#ibcon#first serial, iclass 25, count 0 2006.257.16:12:22.81#ibcon#enter sib2, iclass 25, count 0 2006.257.16:12:22.81#ibcon#flushed, iclass 25, count 0 2006.257.16:12:22.81#ibcon#about to write, iclass 25, count 0 2006.257.16:12:22.81#ibcon#wrote, iclass 25, count 0 2006.257.16:12:22.81#ibcon#about to read 3, iclass 25, count 0 2006.257.16:12:22.83#ibcon#read 3, iclass 25, count 0 2006.257.16:12:22.83#ibcon#about to read 4, iclass 25, count 0 2006.257.16:12:22.83#ibcon#read 4, iclass 25, count 0 2006.257.16:12:22.83#ibcon#about to read 5, iclass 25, count 0 2006.257.16:12:22.83#ibcon#read 5, iclass 25, count 0 2006.257.16:12:22.83#ibcon#about to read 6, iclass 25, count 0 2006.257.16:12:22.83#ibcon#read 6, iclass 25, count 0 2006.257.16:12:22.83#ibcon#end of sib2, iclass 25, count 0 2006.257.16:12:22.83#ibcon#*mode == 0, iclass 25, count 0 2006.257.16:12:22.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.16:12:22.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.16:12:22.83#ibcon#*before write, iclass 25, count 0 2006.257.16:12:22.83#ibcon#enter sib2, iclass 25, count 0 2006.257.16:12:22.83#ibcon#flushed, iclass 25, count 0 2006.257.16:12:22.83#ibcon#about to write, iclass 25, count 0 2006.257.16:12:22.83#ibcon#wrote, iclass 25, count 0 2006.257.16:12:22.83#ibcon#about to read 3, iclass 25, count 0 2006.257.16:12:22.87#ibcon#read 3, iclass 25, count 0 2006.257.16:12:22.87#ibcon#about to read 4, iclass 25, count 0 2006.257.16:12:22.87#ibcon#read 4, iclass 25, count 0 2006.257.16:12:22.87#ibcon#about to read 5, iclass 25, count 0 2006.257.16:12:22.87#ibcon#read 5, iclass 25, count 0 2006.257.16:12:22.87#ibcon#about to read 6, iclass 25, count 0 2006.257.16:12:22.87#ibcon#read 6, iclass 25, count 0 2006.257.16:12:22.87#ibcon#end of sib2, iclass 25, count 0 2006.257.16:12:22.87#ibcon#*after write, iclass 25, count 0 2006.257.16:12:22.87#ibcon#*before return 0, iclass 25, count 0 2006.257.16:12:22.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:22.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:22.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.16:12:22.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.16:12:22.87$vck44/va=8,4 2006.257.16:12:22.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.16:12:22.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.16:12:22.87#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:22.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:12:22.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:12:22.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:12:22.93#ibcon#enter wrdev, iclass 27, count 2 2006.257.16:12:22.93#ibcon#first serial, iclass 27, count 2 2006.257.16:12:22.93#ibcon#enter sib2, iclass 27, count 2 2006.257.16:12:22.93#ibcon#flushed, iclass 27, count 2 2006.257.16:12:22.93#ibcon#about to write, iclass 27, count 2 2006.257.16:12:22.93#ibcon#wrote, iclass 27, count 2 2006.257.16:12:22.93#ibcon#about to read 3, iclass 27, count 2 2006.257.16:12:22.95#ibcon#read 3, iclass 27, count 2 2006.257.16:12:22.95#ibcon#about to read 4, iclass 27, count 2 2006.257.16:12:22.95#ibcon#read 4, iclass 27, count 2 2006.257.16:12:22.95#ibcon#about to read 5, iclass 27, count 2 2006.257.16:12:22.95#ibcon#read 5, iclass 27, count 2 2006.257.16:12:22.95#ibcon#about to read 6, iclass 27, count 2 2006.257.16:12:22.95#ibcon#read 6, iclass 27, count 2 2006.257.16:12:22.95#ibcon#end of sib2, iclass 27, count 2 2006.257.16:12:22.95#ibcon#*mode == 0, iclass 27, count 2 2006.257.16:12:22.95#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.16:12:22.95#ibcon#[25=AT08-04\r\n] 2006.257.16:12:22.95#ibcon#*before write, iclass 27, count 2 2006.257.16:12:22.95#ibcon#enter sib2, iclass 27, count 2 2006.257.16:12:22.95#ibcon#flushed, iclass 27, count 2 2006.257.16:12:22.95#ibcon#about to write, iclass 27, count 2 2006.257.16:12:22.95#ibcon#wrote, iclass 27, count 2 2006.257.16:12:22.95#ibcon#about to read 3, iclass 27, count 2 2006.257.16:12:22.98#ibcon#read 3, iclass 27, count 2 2006.257.16:12:22.98#ibcon#about to read 4, iclass 27, count 2 2006.257.16:12:22.98#ibcon#read 4, iclass 27, count 2 2006.257.16:12:22.98#ibcon#about to read 5, iclass 27, count 2 2006.257.16:12:22.98#ibcon#read 5, iclass 27, count 2 2006.257.16:12:22.98#ibcon#about to read 6, iclass 27, count 2 2006.257.16:12:22.98#ibcon#read 6, iclass 27, count 2 2006.257.16:12:22.98#ibcon#end of sib2, iclass 27, count 2 2006.257.16:12:22.98#ibcon#*after write, iclass 27, count 2 2006.257.16:12:22.98#ibcon#*before return 0, iclass 27, count 2 2006.257.16:12:22.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:12:22.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:12:22.98#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.16:12:22.98#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:22.98#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:12:23.10#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:12:23.10#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:12:23.10#ibcon#enter wrdev, iclass 27, count 0 2006.257.16:12:23.10#ibcon#first serial, iclass 27, count 0 2006.257.16:12:23.10#ibcon#enter sib2, iclass 27, count 0 2006.257.16:12:23.10#ibcon#flushed, iclass 27, count 0 2006.257.16:12:23.10#ibcon#about to write, iclass 27, count 0 2006.257.16:12:23.10#ibcon#wrote, iclass 27, count 0 2006.257.16:12:23.10#ibcon#about to read 3, iclass 27, count 0 2006.257.16:12:23.12#ibcon#read 3, iclass 27, count 0 2006.257.16:12:23.12#ibcon#about to read 4, iclass 27, count 0 2006.257.16:12:23.12#ibcon#read 4, iclass 27, count 0 2006.257.16:12:23.12#ibcon#about to read 5, iclass 27, count 0 2006.257.16:12:23.12#ibcon#read 5, iclass 27, count 0 2006.257.16:12:23.12#ibcon#about to read 6, iclass 27, count 0 2006.257.16:12:23.12#ibcon#read 6, iclass 27, count 0 2006.257.16:12:23.12#ibcon#end of sib2, iclass 27, count 0 2006.257.16:12:23.12#ibcon#*mode == 0, iclass 27, count 0 2006.257.16:12:23.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.16:12:23.12#ibcon#[25=USB\r\n] 2006.257.16:12:23.12#ibcon#*before write, iclass 27, count 0 2006.257.16:12:23.12#ibcon#enter sib2, iclass 27, count 0 2006.257.16:12:23.12#ibcon#flushed, iclass 27, count 0 2006.257.16:12:23.12#ibcon#about to write, iclass 27, count 0 2006.257.16:12:23.12#ibcon#wrote, iclass 27, count 0 2006.257.16:12:23.12#ibcon#about to read 3, iclass 27, count 0 2006.257.16:12:23.15#ibcon#read 3, iclass 27, count 0 2006.257.16:12:23.15#ibcon#about to read 4, iclass 27, count 0 2006.257.16:12:23.15#ibcon#read 4, iclass 27, count 0 2006.257.16:12:23.15#ibcon#about to read 5, iclass 27, count 0 2006.257.16:12:23.15#ibcon#read 5, iclass 27, count 0 2006.257.16:12:23.15#ibcon#about to read 6, iclass 27, count 0 2006.257.16:12:23.15#ibcon#read 6, iclass 27, count 0 2006.257.16:12:23.15#ibcon#end of sib2, iclass 27, count 0 2006.257.16:12:23.15#ibcon#*after write, iclass 27, count 0 2006.257.16:12:23.15#ibcon#*before return 0, iclass 27, count 0 2006.257.16:12:23.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:12:23.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:12:23.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.16:12:23.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.16:12:23.15$vck44/vblo=1,629.99 2006.257.16:12:23.15#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.16:12:23.15#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.16:12:23.15#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:23.15#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:12:23.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:12:23.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:12:23.15#ibcon#enter wrdev, iclass 29, count 0 2006.257.16:12:23.15#ibcon#first serial, iclass 29, count 0 2006.257.16:12:23.15#ibcon#enter sib2, iclass 29, count 0 2006.257.16:12:23.15#ibcon#flushed, iclass 29, count 0 2006.257.16:12:23.15#ibcon#about to write, iclass 29, count 0 2006.257.16:12:23.15#ibcon#wrote, iclass 29, count 0 2006.257.16:12:23.15#ibcon#about to read 3, iclass 29, count 0 2006.257.16:12:23.17#ibcon#read 3, iclass 29, count 0 2006.257.16:12:23.17#ibcon#about to read 4, iclass 29, count 0 2006.257.16:12:23.17#ibcon#read 4, iclass 29, count 0 2006.257.16:12:23.17#ibcon#about to read 5, iclass 29, count 0 2006.257.16:12:23.17#ibcon#read 5, iclass 29, count 0 2006.257.16:12:23.17#ibcon#about to read 6, iclass 29, count 0 2006.257.16:12:23.17#ibcon#read 6, iclass 29, count 0 2006.257.16:12:23.17#ibcon#end of sib2, iclass 29, count 0 2006.257.16:12:23.17#ibcon#*mode == 0, iclass 29, count 0 2006.257.16:12:23.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.16:12:23.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.16:12:23.17#ibcon#*before write, iclass 29, count 0 2006.257.16:12:23.17#ibcon#enter sib2, iclass 29, count 0 2006.257.16:12:23.17#ibcon#flushed, iclass 29, count 0 2006.257.16:12:23.17#ibcon#about to write, iclass 29, count 0 2006.257.16:12:23.17#ibcon#wrote, iclass 29, count 0 2006.257.16:12:23.17#ibcon#about to read 3, iclass 29, count 0 2006.257.16:12:23.21#ibcon#read 3, iclass 29, count 0 2006.257.16:12:23.21#ibcon#about to read 4, iclass 29, count 0 2006.257.16:12:23.21#ibcon#read 4, iclass 29, count 0 2006.257.16:12:23.21#ibcon#about to read 5, iclass 29, count 0 2006.257.16:12:23.21#ibcon#read 5, iclass 29, count 0 2006.257.16:12:23.21#ibcon#about to read 6, iclass 29, count 0 2006.257.16:12:23.21#ibcon#read 6, iclass 29, count 0 2006.257.16:12:23.21#ibcon#end of sib2, iclass 29, count 0 2006.257.16:12:23.21#ibcon#*after write, iclass 29, count 0 2006.257.16:12:23.21#ibcon#*before return 0, iclass 29, count 0 2006.257.16:12:23.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:12:23.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:12:23.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.16:12:23.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.16:12:23.21$vck44/vb=1,4 2006.257.16:12:23.21#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.16:12:23.21#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.16:12:23.21#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:23.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:12:23.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:12:23.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:12:23.21#ibcon#enter wrdev, iclass 31, count 2 2006.257.16:12:23.21#ibcon#first serial, iclass 31, count 2 2006.257.16:12:23.21#ibcon#enter sib2, iclass 31, count 2 2006.257.16:12:23.21#ibcon#flushed, iclass 31, count 2 2006.257.16:12:23.21#ibcon#about to write, iclass 31, count 2 2006.257.16:12:23.21#ibcon#wrote, iclass 31, count 2 2006.257.16:12:23.21#ibcon#about to read 3, iclass 31, count 2 2006.257.16:12:23.23#ibcon#read 3, iclass 31, count 2 2006.257.16:12:23.23#ibcon#about to read 4, iclass 31, count 2 2006.257.16:12:23.23#ibcon#read 4, iclass 31, count 2 2006.257.16:12:23.23#ibcon#about to read 5, iclass 31, count 2 2006.257.16:12:23.23#ibcon#read 5, iclass 31, count 2 2006.257.16:12:23.23#ibcon#about to read 6, iclass 31, count 2 2006.257.16:12:23.23#ibcon#read 6, iclass 31, count 2 2006.257.16:12:23.23#ibcon#end of sib2, iclass 31, count 2 2006.257.16:12:23.23#ibcon#*mode == 0, iclass 31, count 2 2006.257.16:12:23.23#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.16:12:23.23#ibcon#[27=AT01-04\r\n] 2006.257.16:12:23.23#ibcon#*before write, iclass 31, count 2 2006.257.16:12:23.23#ibcon#enter sib2, iclass 31, count 2 2006.257.16:12:23.23#ibcon#flushed, iclass 31, count 2 2006.257.16:12:23.23#ibcon#about to write, iclass 31, count 2 2006.257.16:12:23.23#ibcon#wrote, iclass 31, count 2 2006.257.16:12:23.23#ibcon#about to read 3, iclass 31, count 2 2006.257.16:12:23.26#ibcon#read 3, iclass 31, count 2 2006.257.16:12:23.26#ibcon#about to read 4, iclass 31, count 2 2006.257.16:12:23.26#ibcon#read 4, iclass 31, count 2 2006.257.16:12:23.26#ibcon#about to read 5, iclass 31, count 2 2006.257.16:12:23.26#ibcon#read 5, iclass 31, count 2 2006.257.16:12:23.26#ibcon#about to read 6, iclass 31, count 2 2006.257.16:12:23.26#ibcon#read 6, iclass 31, count 2 2006.257.16:12:23.26#ibcon#end of sib2, iclass 31, count 2 2006.257.16:12:23.26#ibcon#*after write, iclass 31, count 2 2006.257.16:12:23.26#ibcon#*before return 0, iclass 31, count 2 2006.257.16:12:23.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:12:23.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:12:23.26#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.16:12:23.26#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:23.26#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:12:23.38#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:12:23.38#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:12:23.38#ibcon#enter wrdev, iclass 31, count 0 2006.257.16:12:23.38#ibcon#first serial, iclass 31, count 0 2006.257.16:12:23.38#ibcon#enter sib2, iclass 31, count 0 2006.257.16:12:23.38#ibcon#flushed, iclass 31, count 0 2006.257.16:12:23.38#ibcon#about to write, iclass 31, count 0 2006.257.16:12:23.38#ibcon#wrote, iclass 31, count 0 2006.257.16:12:23.38#ibcon#about to read 3, iclass 31, count 0 2006.257.16:12:23.40#ibcon#read 3, iclass 31, count 0 2006.257.16:12:23.40#ibcon#about to read 4, iclass 31, count 0 2006.257.16:12:23.40#ibcon#read 4, iclass 31, count 0 2006.257.16:12:23.40#ibcon#about to read 5, iclass 31, count 0 2006.257.16:12:23.40#ibcon#read 5, iclass 31, count 0 2006.257.16:12:23.40#ibcon#about to read 6, iclass 31, count 0 2006.257.16:12:23.40#ibcon#read 6, iclass 31, count 0 2006.257.16:12:23.40#ibcon#end of sib2, iclass 31, count 0 2006.257.16:12:23.40#ibcon#*mode == 0, iclass 31, count 0 2006.257.16:12:23.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.16:12:23.40#ibcon#[27=USB\r\n] 2006.257.16:12:23.40#ibcon#*before write, iclass 31, count 0 2006.257.16:12:23.40#ibcon#enter sib2, iclass 31, count 0 2006.257.16:12:23.40#ibcon#flushed, iclass 31, count 0 2006.257.16:12:23.40#ibcon#about to write, iclass 31, count 0 2006.257.16:12:23.40#ibcon#wrote, iclass 31, count 0 2006.257.16:12:23.40#ibcon#about to read 3, iclass 31, count 0 2006.257.16:12:23.43#ibcon#read 3, iclass 31, count 0 2006.257.16:12:23.43#ibcon#about to read 4, iclass 31, count 0 2006.257.16:12:23.43#ibcon#read 4, iclass 31, count 0 2006.257.16:12:23.43#ibcon#about to read 5, iclass 31, count 0 2006.257.16:12:23.43#ibcon#read 5, iclass 31, count 0 2006.257.16:12:23.43#ibcon#about to read 6, iclass 31, count 0 2006.257.16:12:23.43#ibcon#read 6, iclass 31, count 0 2006.257.16:12:23.43#ibcon#end of sib2, iclass 31, count 0 2006.257.16:12:23.43#ibcon#*after write, iclass 31, count 0 2006.257.16:12:23.43#ibcon#*before return 0, iclass 31, count 0 2006.257.16:12:23.43#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:12:23.43#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:12:23.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.16:12:23.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.16:12:23.43$vck44/vblo=2,634.99 2006.257.16:12:23.43#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.16:12:23.43#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.16:12:23.43#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:23.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:23.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:23.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:23.43#ibcon#enter wrdev, iclass 33, count 0 2006.257.16:12:23.43#ibcon#first serial, iclass 33, count 0 2006.257.16:12:23.43#ibcon#enter sib2, iclass 33, count 0 2006.257.16:12:23.43#ibcon#flushed, iclass 33, count 0 2006.257.16:12:23.43#ibcon#about to write, iclass 33, count 0 2006.257.16:12:23.43#ibcon#wrote, iclass 33, count 0 2006.257.16:12:23.43#ibcon#about to read 3, iclass 33, count 0 2006.257.16:12:23.45#ibcon#read 3, iclass 33, count 0 2006.257.16:12:23.45#ibcon#about to read 4, iclass 33, count 0 2006.257.16:12:23.45#ibcon#read 4, iclass 33, count 0 2006.257.16:12:23.45#ibcon#about to read 5, iclass 33, count 0 2006.257.16:12:23.45#ibcon#read 5, iclass 33, count 0 2006.257.16:12:23.45#ibcon#about to read 6, iclass 33, count 0 2006.257.16:12:23.45#ibcon#read 6, iclass 33, count 0 2006.257.16:12:23.45#ibcon#end of sib2, iclass 33, count 0 2006.257.16:12:23.45#ibcon#*mode == 0, iclass 33, count 0 2006.257.16:12:23.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.16:12:23.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.16:12:23.45#ibcon#*before write, iclass 33, count 0 2006.257.16:12:23.45#ibcon#enter sib2, iclass 33, count 0 2006.257.16:12:23.45#ibcon#flushed, iclass 33, count 0 2006.257.16:12:23.45#ibcon#about to write, iclass 33, count 0 2006.257.16:12:23.45#ibcon#wrote, iclass 33, count 0 2006.257.16:12:23.45#ibcon#about to read 3, iclass 33, count 0 2006.257.16:12:23.49#ibcon#read 3, iclass 33, count 0 2006.257.16:12:23.49#ibcon#about to read 4, iclass 33, count 0 2006.257.16:12:23.49#ibcon#read 4, iclass 33, count 0 2006.257.16:12:23.49#ibcon#about to read 5, iclass 33, count 0 2006.257.16:12:23.49#ibcon#read 5, iclass 33, count 0 2006.257.16:12:23.49#ibcon#about to read 6, iclass 33, count 0 2006.257.16:12:23.49#ibcon#read 6, iclass 33, count 0 2006.257.16:12:23.49#ibcon#end of sib2, iclass 33, count 0 2006.257.16:12:23.49#ibcon#*after write, iclass 33, count 0 2006.257.16:12:23.49#ibcon#*before return 0, iclass 33, count 0 2006.257.16:12:23.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:23.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:12:23.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.16:12:23.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.16:12:23.49$vck44/vb=2,5 2006.257.16:12:23.49#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.16:12:23.49#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.16:12:23.49#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:23.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:23.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:23.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:23.55#ibcon#enter wrdev, iclass 35, count 2 2006.257.16:12:23.55#ibcon#first serial, iclass 35, count 2 2006.257.16:12:23.55#ibcon#enter sib2, iclass 35, count 2 2006.257.16:12:23.55#ibcon#flushed, iclass 35, count 2 2006.257.16:12:23.55#ibcon#about to write, iclass 35, count 2 2006.257.16:12:23.55#ibcon#wrote, iclass 35, count 2 2006.257.16:12:23.55#ibcon#about to read 3, iclass 35, count 2 2006.257.16:12:23.57#ibcon#read 3, iclass 35, count 2 2006.257.16:12:23.57#ibcon#about to read 4, iclass 35, count 2 2006.257.16:12:23.57#ibcon#read 4, iclass 35, count 2 2006.257.16:12:23.57#ibcon#about to read 5, iclass 35, count 2 2006.257.16:12:23.57#ibcon#read 5, iclass 35, count 2 2006.257.16:12:23.57#ibcon#about to read 6, iclass 35, count 2 2006.257.16:12:23.57#ibcon#read 6, iclass 35, count 2 2006.257.16:12:23.57#ibcon#end of sib2, iclass 35, count 2 2006.257.16:12:23.57#ibcon#*mode == 0, iclass 35, count 2 2006.257.16:12:23.57#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.16:12:23.57#ibcon#[27=AT02-05\r\n] 2006.257.16:12:23.57#ibcon#*before write, iclass 35, count 2 2006.257.16:12:23.57#ibcon#enter sib2, iclass 35, count 2 2006.257.16:12:23.57#ibcon#flushed, iclass 35, count 2 2006.257.16:12:23.57#ibcon#about to write, iclass 35, count 2 2006.257.16:12:23.57#ibcon#wrote, iclass 35, count 2 2006.257.16:12:23.57#ibcon#about to read 3, iclass 35, count 2 2006.257.16:12:23.60#ibcon#read 3, iclass 35, count 2 2006.257.16:12:23.60#ibcon#about to read 4, iclass 35, count 2 2006.257.16:12:23.60#ibcon#read 4, iclass 35, count 2 2006.257.16:12:23.60#ibcon#about to read 5, iclass 35, count 2 2006.257.16:12:23.60#ibcon#read 5, iclass 35, count 2 2006.257.16:12:23.60#ibcon#about to read 6, iclass 35, count 2 2006.257.16:12:23.60#ibcon#read 6, iclass 35, count 2 2006.257.16:12:23.60#ibcon#end of sib2, iclass 35, count 2 2006.257.16:12:23.60#ibcon#*after write, iclass 35, count 2 2006.257.16:12:23.60#ibcon#*before return 0, iclass 35, count 2 2006.257.16:12:23.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:23.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:12:23.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.16:12:23.60#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:23.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:23.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:23.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:23.72#ibcon#enter wrdev, iclass 35, count 0 2006.257.16:12:23.72#ibcon#first serial, iclass 35, count 0 2006.257.16:12:23.72#ibcon#enter sib2, iclass 35, count 0 2006.257.16:12:23.72#ibcon#flushed, iclass 35, count 0 2006.257.16:12:23.72#ibcon#about to write, iclass 35, count 0 2006.257.16:12:23.72#ibcon#wrote, iclass 35, count 0 2006.257.16:12:23.72#ibcon#about to read 3, iclass 35, count 0 2006.257.16:12:23.74#ibcon#read 3, iclass 35, count 0 2006.257.16:12:23.74#ibcon#about to read 4, iclass 35, count 0 2006.257.16:12:23.74#ibcon#read 4, iclass 35, count 0 2006.257.16:12:23.74#ibcon#about to read 5, iclass 35, count 0 2006.257.16:12:23.74#ibcon#read 5, iclass 35, count 0 2006.257.16:12:23.74#ibcon#about to read 6, iclass 35, count 0 2006.257.16:12:23.74#ibcon#read 6, iclass 35, count 0 2006.257.16:12:23.74#ibcon#end of sib2, iclass 35, count 0 2006.257.16:12:23.74#ibcon#*mode == 0, iclass 35, count 0 2006.257.16:12:23.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.16:12:23.74#ibcon#[27=USB\r\n] 2006.257.16:12:23.74#ibcon#*before write, iclass 35, count 0 2006.257.16:12:23.74#ibcon#enter sib2, iclass 35, count 0 2006.257.16:12:23.74#ibcon#flushed, iclass 35, count 0 2006.257.16:12:23.74#ibcon#about to write, iclass 35, count 0 2006.257.16:12:23.74#ibcon#wrote, iclass 35, count 0 2006.257.16:12:23.74#ibcon#about to read 3, iclass 35, count 0 2006.257.16:12:23.77#ibcon#read 3, iclass 35, count 0 2006.257.16:12:23.77#ibcon#about to read 4, iclass 35, count 0 2006.257.16:12:23.77#ibcon#read 4, iclass 35, count 0 2006.257.16:12:23.77#ibcon#about to read 5, iclass 35, count 0 2006.257.16:12:23.77#ibcon#read 5, iclass 35, count 0 2006.257.16:12:23.77#ibcon#about to read 6, iclass 35, count 0 2006.257.16:12:23.77#ibcon#read 6, iclass 35, count 0 2006.257.16:12:23.77#ibcon#end of sib2, iclass 35, count 0 2006.257.16:12:23.77#ibcon#*after write, iclass 35, count 0 2006.257.16:12:23.77#ibcon#*before return 0, iclass 35, count 0 2006.257.16:12:23.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:23.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:12:23.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.16:12:23.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.16:12:23.77$vck44/vblo=3,649.99 2006.257.16:12:23.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.16:12:23.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.16:12:23.77#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:23.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:23.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:23.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:23.77#ibcon#enter wrdev, iclass 37, count 0 2006.257.16:12:23.77#ibcon#first serial, iclass 37, count 0 2006.257.16:12:23.77#ibcon#enter sib2, iclass 37, count 0 2006.257.16:12:23.77#ibcon#flushed, iclass 37, count 0 2006.257.16:12:23.77#ibcon#about to write, iclass 37, count 0 2006.257.16:12:23.77#ibcon#wrote, iclass 37, count 0 2006.257.16:12:23.77#ibcon#about to read 3, iclass 37, count 0 2006.257.16:12:23.79#ibcon#read 3, iclass 37, count 0 2006.257.16:12:23.79#ibcon#about to read 4, iclass 37, count 0 2006.257.16:12:23.79#ibcon#read 4, iclass 37, count 0 2006.257.16:12:23.79#ibcon#about to read 5, iclass 37, count 0 2006.257.16:12:23.79#ibcon#read 5, iclass 37, count 0 2006.257.16:12:23.79#ibcon#about to read 6, iclass 37, count 0 2006.257.16:12:23.79#ibcon#read 6, iclass 37, count 0 2006.257.16:12:23.79#ibcon#end of sib2, iclass 37, count 0 2006.257.16:12:23.79#ibcon#*mode == 0, iclass 37, count 0 2006.257.16:12:23.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.16:12:23.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.16:12:23.79#ibcon#*before write, iclass 37, count 0 2006.257.16:12:23.79#ibcon#enter sib2, iclass 37, count 0 2006.257.16:12:23.79#ibcon#flushed, iclass 37, count 0 2006.257.16:12:23.79#ibcon#about to write, iclass 37, count 0 2006.257.16:12:23.79#ibcon#wrote, iclass 37, count 0 2006.257.16:12:23.79#ibcon#about to read 3, iclass 37, count 0 2006.257.16:12:23.83#ibcon#read 3, iclass 37, count 0 2006.257.16:12:23.83#ibcon#about to read 4, iclass 37, count 0 2006.257.16:12:23.83#ibcon#read 4, iclass 37, count 0 2006.257.16:12:23.83#ibcon#about to read 5, iclass 37, count 0 2006.257.16:12:23.83#ibcon#read 5, iclass 37, count 0 2006.257.16:12:23.83#ibcon#about to read 6, iclass 37, count 0 2006.257.16:12:23.83#ibcon#read 6, iclass 37, count 0 2006.257.16:12:23.83#ibcon#end of sib2, iclass 37, count 0 2006.257.16:12:23.83#ibcon#*after write, iclass 37, count 0 2006.257.16:12:23.83#ibcon#*before return 0, iclass 37, count 0 2006.257.16:12:23.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:23.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:12:23.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.16:12:23.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.16:12:23.83$vck44/vb=3,4 2006.257.16:12:23.83#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.16:12:23.83#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.16:12:23.83#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:23.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:23.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:23.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:23.89#ibcon#enter wrdev, iclass 39, count 2 2006.257.16:12:23.89#ibcon#first serial, iclass 39, count 2 2006.257.16:12:23.89#ibcon#enter sib2, iclass 39, count 2 2006.257.16:12:23.89#ibcon#flushed, iclass 39, count 2 2006.257.16:12:23.89#ibcon#about to write, iclass 39, count 2 2006.257.16:12:23.89#ibcon#wrote, iclass 39, count 2 2006.257.16:12:23.89#ibcon#about to read 3, iclass 39, count 2 2006.257.16:12:23.91#ibcon#read 3, iclass 39, count 2 2006.257.16:12:23.91#ibcon#about to read 4, iclass 39, count 2 2006.257.16:12:23.91#ibcon#read 4, iclass 39, count 2 2006.257.16:12:23.91#ibcon#about to read 5, iclass 39, count 2 2006.257.16:12:23.91#ibcon#read 5, iclass 39, count 2 2006.257.16:12:23.91#ibcon#about to read 6, iclass 39, count 2 2006.257.16:12:23.91#ibcon#read 6, iclass 39, count 2 2006.257.16:12:23.91#ibcon#end of sib2, iclass 39, count 2 2006.257.16:12:23.91#ibcon#*mode == 0, iclass 39, count 2 2006.257.16:12:23.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.16:12:23.91#ibcon#[27=AT03-04\r\n] 2006.257.16:12:23.91#ibcon#*before write, iclass 39, count 2 2006.257.16:12:23.91#ibcon#enter sib2, iclass 39, count 2 2006.257.16:12:23.91#ibcon#flushed, iclass 39, count 2 2006.257.16:12:23.91#ibcon#about to write, iclass 39, count 2 2006.257.16:12:23.91#ibcon#wrote, iclass 39, count 2 2006.257.16:12:23.91#ibcon#about to read 3, iclass 39, count 2 2006.257.16:12:23.94#ibcon#read 3, iclass 39, count 2 2006.257.16:12:23.94#ibcon#about to read 4, iclass 39, count 2 2006.257.16:12:23.94#ibcon#read 4, iclass 39, count 2 2006.257.16:12:23.94#ibcon#about to read 5, iclass 39, count 2 2006.257.16:12:23.94#ibcon#read 5, iclass 39, count 2 2006.257.16:12:23.94#ibcon#about to read 6, iclass 39, count 2 2006.257.16:12:23.94#ibcon#read 6, iclass 39, count 2 2006.257.16:12:23.94#ibcon#end of sib2, iclass 39, count 2 2006.257.16:12:23.94#ibcon#*after write, iclass 39, count 2 2006.257.16:12:23.94#ibcon#*before return 0, iclass 39, count 2 2006.257.16:12:23.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:23.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:12:23.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.16:12:23.94#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:23.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:24.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:24.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:24.06#ibcon#enter wrdev, iclass 39, count 0 2006.257.16:12:24.06#ibcon#first serial, iclass 39, count 0 2006.257.16:12:24.06#ibcon#enter sib2, iclass 39, count 0 2006.257.16:12:24.06#ibcon#flushed, iclass 39, count 0 2006.257.16:12:24.06#ibcon#about to write, iclass 39, count 0 2006.257.16:12:24.06#ibcon#wrote, iclass 39, count 0 2006.257.16:12:24.06#ibcon#about to read 3, iclass 39, count 0 2006.257.16:12:24.08#ibcon#read 3, iclass 39, count 0 2006.257.16:12:24.08#ibcon#about to read 4, iclass 39, count 0 2006.257.16:12:24.08#ibcon#read 4, iclass 39, count 0 2006.257.16:12:24.08#ibcon#about to read 5, iclass 39, count 0 2006.257.16:12:24.08#ibcon#read 5, iclass 39, count 0 2006.257.16:12:24.08#ibcon#about to read 6, iclass 39, count 0 2006.257.16:12:24.08#ibcon#read 6, iclass 39, count 0 2006.257.16:12:24.08#ibcon#end of sib2, iclass 39, count 0 2006.257.16:12:24.08#ibcon#*mode == 0, iclass 39, count 0 2006.257.16:12:24.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.16:12:24.08#ibcon#[27=USB\r\n] 2006.257.16:12:24.08#ibcon#*before write, iclass 39, count 0 2006.257.16:12:24.08#ibcon#enter sib2, iclass 39, count 0 2006.257.16:12:24.08#ibcon#flushed, iclass 39, count 0 2006.257.16:12:24.08#ibcon#about to write, iclass 39, count 0 2006.257.16:12:24.08#ibcon#wrote, iclass 39, count 0 2006.257.16:12:24.08#ibcon#about to read 3, iclass 39, count 0 2006.257.16:12:24.11#ibcon#read 3, iclass 39, count 0 2006.257.16:12:24.11#ibcon#about to read 4, iclass 39, count 0 2006.257.16:12:24.11#ibcon#read 4, iclass 39, count 0 2006.257.16:12:24.11#ibcon#about to read 5, iclass 39, count 0 2006.257.16:12:24.11#ibcon#read 5, iclass 39, count 0 2006.257.16:12:24.11#ibcon#about to read 6, iclass 39, count 0 2006.257.16:12:24.11#ibcon#read 6, iclass 39, count 0 2006.257.16:12:24.11#ibcon#end of sib2, iclass 39, count 0 2006.257.16:12:24.11#ibcon#*after write, iclass 39, count 0 2006.257.16:12:24.11#ibcon#*before return 0, iclass 39, count 0 2006.257.16:12:24.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:24.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:12:24.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.16:12:24.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.16:12:24.11$vck44/vblo=4,679.99 2006.257.16:12:24.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.16:12:24.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.16:12:24.11#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:24.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:24.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:24.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:24.11#ibcon#enter wrdev, iclass 3, count 0 2006.257.16:12:24.11#ibcon#first serial, iclass 3, count 0 2006.257.16:12:24.11#ibcon#enter sib2, iclass 3, count 0 2006.257.16:12:24.11#ibcon#flushed, iclass 3, count 0 2006.257.16:12:24.11#ibcon#about to write, iclass 3, count 0 2006.257.16:12:24.11#ibcon#wrote, iclass 3, count 0 2006.257.16:12:24.11#ibcon#about to read 3, iclass 3, count 0 2006.257.16:12:24.13#ibcon#read 3, iclass 3, count 0 2006.257.16:12:24.13#ibcon#about to read 4, iclass 3, count 0 2006.257.16:12:24.13#ibcon#read 4, iclass 3, count 0 2006.257.16:12:24.13#ibcon#about to read 5, iclass 3, count 0 2006.257.16:12:24.13#ibcon#read 5, iclass 3, count 0 2006.257.16:12:24.13#ibcon#about to read 6, iclass 3, count 0 2006.257.16:12:24.13#ibcon#read 6, iclass 3, count 0 2006.257.16:12:24.13#ibcon#end of sib2, iclass 3, count 0 2006.257.16:12:24.13#ibcon#*mode == 0, iclass 3, count 0 2006.257.16:12:24.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.16:12:24.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.16:12:24.13#ibcon#*before write, iclass 3, count 0 2006.257.16:12:24.13#ibcon#enter sib2, iclass 3, count 0 2006.257.16:12:24.13#ibcon#flushed, iclass 3, count 0 2006.257.16:12:24.13#ibcon#about to write, iclass 3, count 0 2006.257.16:12:24.13#ibcon#wrote, iclass 3, count 0 2006.257.16:12:24.13#ibcon#about to read 3, iclass 3, count 0 2006.257.16:12:24.17#ibcon#read 3, iclass 3, count 0 2006.257.16:12:24.17#ibcon#about to read 4, iclass 3, count 0 2006.257.16:12:24.17#ibcon#read 4, iclass 3, count 0 2006.257.16:12:24.17#ibcon#about to read 5, iclass 3, count 0 2006.257.16:12:24.17#ibcon#read 5, iclass 3, count 0 2006.257.16:12:24.17#ibcon#about to read 6, iclass 3, count 0 2006.257.16:12:24.17#ibcon#read 6, iclass 3, count 0 2006.257.16:12:24.17#ibcon#end of sib2, iclass 3, count 0 2006.257.16:12:24.17#ibcon#*after write, iclass 3, count 0 2006.257.16:12:24.17#ibcon#*before return 0, iclass 3, count 0 2006.257.16:12:24.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:24.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:12:24.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.16:12:24.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.16:12:24.17$vck44/vb=4,5 2006.257.16:12:24.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.16:12:24.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.16:12:24.17#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:24.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:24.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:24.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:24.23#ibcon#enter wrdev, iclass 5, count 2 2006.257.16:12:24.23#ibcon#first serial, iclass 5, count 2 2006.257.16:12:24.23#ibcon#enter sib2, iclass 5, count 2 2006.257.16:12:24.23#ibcon#flushed, iclass 5, count 2 2006.257.16:12:24.23#ibcon#about to write, iclass 5, count 2 2006.257.16:12:24.23#ibcon#wrote, iclass 5, count 2 2006.257.16:12:24.23#ibcon#about to read 3, iclass 5, count 2 2006.257.16:12:24.25#ibcon#read 3, iclass 5, count 2 2006.257.16:12:24.25#ibcon#about to read 4, iclass 5, count 2 2006.257.16:12:24.25#ibcon#read 4, iclass 5, count 2 2006.257.16:12:24.25#ibcon#about to read 5, iclass 5, count 2 2006.257.16:12:24.25#ibcon#read 5, iclass 5, count 2 2006.257.16:12:24.25#ibcon#about to read 6, iclass 5, count 2 2006.257.16:12:24.25#ibcon#read 6, iclass 5, count 2 2006.257.16:12:24.25#ibcon#end of sib2, iclass 5, count 2 2006.257.16:12:24.25#ibcon#*mode == 0, iclass 5, count 2 2006.257.16:12:24.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.16:12:24.25#ibcon#[27=AT04-05\r\n] 2006.257.16:12:24.25#ibcon#*before write, iclass 5, count 2 2006.257.16:12:24.25#ibcon#enter sib2, iclass 5, count 2 2006.257.16:12:24.25#ibcon#flushed, iclass 5, count 2 2006.257.16:12:24.25#ibcon#about to write, iclass 5, count 2 2006.257.16:12:24.25#ibcon#wrote, iclass 5, count 2 2006.257.16:12:24.25#ibcon#about to read 3, iclass 5, count 2 2006.257.16:12:24.28#ibcon#read 3, iclass 5, count 2 2006.257.16:12:24.28#ibcon#about to read 4, iclass 5, count 2 2006.257.16:12:24.28#ibcon#read 4, iclass 5, count 2 2006.257.16:12:24.28#ibcon#about to read 5, iclass 5, count 2 2006.257.16:12:24.28#ibcon#read 5, iclass 5, count 2 2006.257.16:12:24.28#ibcon#about to read 6, iclass 5, count 2 2006.257.16:12:24.28#ibcon#read 6, iclass 5, count 2 2006.257.16:12:24.28#ibcon#end of sib2, iclass 5, count 2 2006.257.16:12:24.28#ibcon#*after write, iclass 5, count 2 2006.257.16:12:24.28#ibcon#*before return 0, iclass 5, count 2 2006.257.16:12:24.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:24.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:12:24.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.16:12:24.28#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:24.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:24.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:24.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:24.40#ibcon#enter wrdev, iclass 5, count 0 2006.257.16:12:24.40#ibcon#first serial, iclass 5, count 0 2006.257.16:12:24.40#ibcon#enter sib2, iclass 5, count 0 2006.257.16:12:24.40#ibcon#flushed, iclass 5, count 0 2006.257.16:12:24.40#ibcon#about to write, iclass 5, count 0 2006.257.16:12:24.40#ibcon#wrote, iclass 5, count 0 2006.257.16:12:24.40#ibcon#about to read 3, iclass 5, count 0 2006.257.16:12:24.42#ibcon#read 3, iclass 5, count 0 2006.257.16:12:24.42#ibcon#about to read 4, iclass 5, count 0 2006.257.16:12:24.42#ibcon#read 4, iclass 5, count 0 2006.257.16:12:24.42#ibcon#about to read 5, iclass 5, count 0 2006.257.16:12:24.42#ibcon#read 5, iclass 5, count 0 2006.257.16:12:24.42#ibcon#about to read 6, iclass 5, count 0 2006.257.16:12:24.42#ibcon#read 6, iclass 5, count 0 2006.257.16:12:24.42#ibcon#end of sib2, iclass 5, count 0 2006.257.16:12:24.42#ibcon#*mode == 0, iclass 5, count 0 2006.257.16:12:24.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.16:12:24.42#ibcon#[27=USB\r\n] 2006.257.16:12:24.42#ibcon#*before write, iclass 5, count 0 2006.257.16:12:24.42#ibcon#enter sib2, iclass 5, count 0 2006.257.16:12:24.42#ibcon#flushed, iclass 5, count 0 2006.257.16:12:24.42#ibcon#about to write, iclass 5, count 0 2006.257.16:12:24.42#ibcon#wrote, iclass 5, count 0 2006.257.16:12:24.42#ibcon#about to read 3, iclass 5, count 0 2006.257.16:12:24.45#ibcon#read 3, iclass 5, count 0 2006.257.16:12:24.45#ibcon#about to read 4, iclass 5, count 0 2006.257.16:12:24.45#ibcon#read 4, iclass 5, count 0 2006.257.16:12:24.45#ibcon#about to read 5, iclass 5, count 0 2006.257.16:12:24.45#ibcon#read 5, iclass 5, count 0 2006.257.16:12:24.45#ibcon#about to read 6, iclass 5, count 0 2006.257.16:12:24.45#ibcon#read 6, iclass 5, count 0 2006.257.16:12:24.45#ibcon#end of sib2, iclass 5, count 0 2006.257.16:12:24.45#ibcon#*after write, iclass 5, count 0 2006.257.16:12:24.45#ibcon#*before return 0, iclass 5, count 0 2006.257.16:12:24.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:24.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:12:24.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.16:12:24.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.16:12:24.45$vck44/vblo=5,709.99 2006.257.16:12:24.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.16:12:24.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.16:12:24.45#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:24.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:24.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:24.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:24.45#ibcon#enter wrdev, iclass 7, count 0 2006.257.16:12:24.45#ibcon#first serial, iclass 7, count 0 2006.257.16:12:24.45#ibcon#enter sib2, iclass 7, count 0 2006.257.16:12:24.45#ibcon#flushed, iclass 7, count 0 2006.257.16:12:24.45#ibcon#about to write, iclass 7, count 0 2006.257.16:12:24.45#ibcon#wrote, iclass 7, count 0 2006.257.16:12:24.45#ibcon#about to read 3, iclass 7, count 0 2006.257.16:12:24.47#ibcon#read 3, iclass 7, count 0 2006.257.16:12:24.47#ibcon#about to read 4, iclass 7, count 0 2006.257.16:12:24.47#ibcon#read 4, iclass 7, count 0 2006.257.16:12:24.47#ibcon#about to read 5, iclass 7, count 0 2006.257.16:12:24.47#ibcon#read 5, iclass 7, count 0 2006.257.16:12:24.47#ibcon#about to read 6, iclass 7, count 0 2006.257.16:12:24.47#ibcon#read 6, iclass 7, count 0 2006.257.16:12:24.47#ibcon#end of sib2, iclass 7, count 0 2006.257.16:12:24.47#ibcon#*mode == 0, iclass 7, count 0 2006.257.16:12:24.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.16:12:24.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:12:24.47#ibcon#*before write, iclass 7, count 0 2006.257.16:12:24.47#ibcon#enter sib2, iclass 7, count 0 2006.257.16:12:24.47#ibcon#flushed, iclass 7, count 0 2006.257.16:12:24.47#ibcon#about to write, iclass 7, count 0 2006.257.16:12:24.47#ibcon#wrote, iclass 7, count 0 2006.257.16:12:24.47#ibcon#about to read 3, iclass 7, count 0 2006.257.16:12:24.51#ibcon#read 3, iclass 7, count 0 2006.257.16:12:24.51#ibcon#about to read 4, iclass 7, count 0 2006.257.16:12:24.51#ibcon#read 4, iclass 7, count 0 2006.257.16:12:24.51#ibcon#about to read 5, iclass 7, count 0 2006.257.16:12:24.51#ibcon#read 5, iclass 7, count 0 2006.257.16:12:24.51#ibcon#about to read 6, iclass 7, count 0 2006.257.16:12:24.51#ibcon#read 6, iclass 7, count 0 2006.257.16:12:24.51#ibcon#end of sib2, iclass 7, count 0 2006.257.16:12:24.51#ibcon#*after write, iclass 7, count 0 2006.257.16:12:24.51#ibcon#*before return 0, iclass 7, count 0 2006.257.16:12:24.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:24.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:12:24.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.16:12:24.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.16:12:24.51$vck44/vb=5,4 2006.257.16:12:24.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.16:12:24.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.16:12:24.51#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:24.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:24.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:24.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:24.57#ibcon#enter wrdev, iclass 11, count 2 2006.257.16:12:24.57#ibcon#first serial, iclass 11, count 2 2006.257.16:12:24.57#ibcon#enter sib2, iclass 11, count 2 2006.257.16:12:24.57#ibcon#flushed, iclass 11, count 2 2006.257.16:12:24.57#ibcon#about to write, iclass 11, count 2 2006.257.16:12:24.57#ibcon#wrote, iclass 11, count 2 2006.257.16:12:24.57#ibcon#about to read 3, iclass 11, count 2 2006.257.16:12:24.59#ibcon#read 3, iclass 11, count 2 2006.257.16:12:24.59#ibcon#about to read 4, iclass 11, count 2 2006.257.16:12:24.59#ibcon#read 4, iclass 11, count 2 2006.257.16:12:24.59#ibcon#about to read 5, iclass 11, count 2 2006.257.16:12:24.59#ibcon#read 5, iclass 11, count 2 2006.257.16:12:24.59#ibcon#about to read 6, iclass 11, count 2 2006.257.16:12:24.59#ibcon#read 6, iclass 11, count 2 2006.257.16:12:24.59#ibcon#end of sib2, iclass 11, count 2 2006.257.16:12:24.59#ibcon#*mode == 0, iclass 11, count 2 2006.257.16:12:24.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.16:12:24.59#ibcon#[27=AT05-04\r\n] 2006.257.16:12:24.59#ibcon#*before write, iclass 11, count 2 2006.257.16:12:24.59#ibcon#enter sib2, iclass 11, count 2 2006.257.16:12:24.59#ibcon#flushed, iclass 11, count 2 2006.257.16:12:24.59#ibcon#about to write, iclass 11, count 2 2006.257.16:12:24.59#ibcon#wrote, iclass 11, count 2 2006.257.16:12:24.59#ibcon#about to read 3, iclass 11, count 2 2006.257.16:12:24.62#ibcon#read 3, iclass 11, count 2 2006.257.16:12:24.62#ibcon#about to read 4, iclass 11, count 2 2006.257.16:12:24.62#ibcon#read 4, iclass 11, count 2 2006.257.16:12:24.62#ibcon#about to read 5, iclass 11, count 2 2006.257.16:12:24.62#ibcon#read 5, iclass 11, count 2 2006.257.16:12:24.62#ibcon#about to read 6, iclass 11, count 2 2006.257.16:12:24.62#ibcon#read 6, iclass 11, count 2 2006.257.16:12:24.62#ibcon#end of sib2, iclass 11, count 2 2006.257.16:12:24.62#ibcon#*after write, iclass 11, count 2 2006.257.16:12:24.62#ibcon#*before return 0, iclass 11, count 2 2006.257.16:12:24.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:24.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:12:24.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.16:12:24.62#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:24.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:24.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:24.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:24.74#ibcon#enter wrdev, iclass 11, count 0 2006.257.16:12:24.74#ibcon#first serial, iclass 11, count 0 2006.257.16:12:24.74#ibcon#enter sib2, iclass 11, count 0 2006.257.16:12:24.74#ibcon#flushed, iclass 11, count 0 2006.257.16:12:24.74#ibcon#about to write, iclass 11, count 0 2006.257.16:12:24.74#ibcon#wrote, iclass 11, count 0 2006.257.16:12:24.74#ibcon#about to read 3, iclass 11, count 0 2006.257.16:12:24.76#ibcon#read 3, iclass 11, count 0 2006.257.16:12:24.76#ibcon#about to read 4, iclass 11, count 0 2006.257.16:12:24.76#ibcon#read 4, iclass 11, count 0 2006.257.16:12:24.76#ibcon#about to read 5, iclass 11, count 0 2006.257.16:12:24.76#ibcon#read 5, iclass 11, count 0 2006.257.16:12:24.76#ibcon#about to read 6, iclass 11, count 0 2006.257.16:12:24.76#ibcon#read 6, iclass 11, count 0 2006.257.16:12:24.76#ibcon#end of sib2, iclass 11, count 0 2006.257.16:12:24.76#ibcon#*mode == 0, iclass 11, count 0 2006.257.16:12:24.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.16:12:24.76#ibcon#[27=USB\r\n] 2006.257.16:12:24.76#ibcon#*before write, iclass 11, count 0 2006.257.16:12:24.76#ibcon#enter sib2, iclass 11, count 0 2006.257.16:12:24.76#ibcon#flushed, iclass 11, count 0 2006.257.16:12:24.76#ibcon#about to write, iclass 11, count 0 2006.257.16:12:24.76#ibcon#wrote, iclass 11, count 0 2006.257.16:12:24.76#ibcon#about to read 3, iclass 11, count 0 2006.257.16:12:24.79#ibcon#read 3, iclass 11, count 0 2006.257.16:12:24.79#ibcon#about to read 4, iclass 11, count 0 2006.257.16:12:24.79#ibcon#read 4, iclass 11, count 0 2006.257.16:12:24.79#ibcon#about to read 5, iclass 11, count 0 2006.257.16:12:24.79#ibcon#read 5, iclass 11, count 0 2006.257.16:12:24.79#ibcon#about to read 6, iclass 11, count 0 2006.257.16:12:24.79#ibcon#read 6, iclass 11, count 0 2006.257.16:12:24.79#ibcon#end of sib2, iclass 11, count 0 2006.257.16:12:24.79#ibcon#*after write, iclass 11, count 0 2006.257.16:12:24.79#ibcon#*before return 0, iclass 11, count 0 2006.257.16:12:24.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:24.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:12:24.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.16:12:24.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.16:12:24.79$vck44/vblo=6,719.99 2006.257.16:12:24.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.16:12:24.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.16:12:24.79#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:24.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:24.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:24.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:24.79#ibcon#enter wrdev, iclass 13, count 0 2006.257.16:12:24.79#ibcon#first serial, iclass 13, count 0 2006.257.16:12:24.79#ibcon#enter sib2, iclass 13, count 0 2006.257.16:12:24.79#ibcon#flushed, iclass 13, count 0 2006.257.16:12:24.79#ibcon#about to write, iclass 13, count 0 2006.257.16:12:24.79#ibcon#wrote, iclass 13, count 0 2006.257.16:12:24.79#ibcon#about to read 3, iclass 13, count 0 2006.257.16:12:24.81#ibcon#read 3, iclass 13, count 0 2006.257.16:12:24.81#ibcon#about to read 4, iclass 13, count 0 2006.257.16:12:24.81#ibcon#read 4, iclass 13, count 0 2006.257.16:12:24.81#ibcon#about to read 5, iclass 13, count 0 2006.257.16:12:24.81#ibcon#read 5, iclass 13, count 0 2006.257.16:12:24.81#ibcon#about to read 6, iclass 13, count 0 2006.257.16:12:24.81#ibcon#read 6, iclass 13, count 0 2006.257.16:12:24.81#ibcon#end of sib2, iclass 13, count 0 2006.257.16:12:24.81#ibcon#*mode == 0, iclass 13, count 0 2006.257.16:12:24.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.16:12:24.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:12:24.81#ibcon#*before write, iclass 13, count 0 2006.257.16:12:24.81#ibcon#enter sib2, iclass 13, count 0 2006.257.16:12:24.81#ibcon#flushed, iclass 13, count 0 2006.257.16:12:24.81#ibcon#about to write, iclass 13, count 0 2006.257.16:12:24.81#ibcon#wrote, iclass 13, count 0 2006.257.16:12:24.81#ibcon#about to read 3, iclass 13, count 0 2006.257.16:12:24.85#ibcon#read 3, iclass 13, count 0 2006.257.16:12:24.85#ibcon#about to read 4, iclass 13, count 0 2006.257.16:12:24.85#ibcon#read 4, iclass 13, count 0 2006.257.16:12:24.85#ibcon#about to read 5, iclass 13, count 0 2006.257.16:12:24.85#ibcon#read 5, iclass 13, count 0 2006.257.16:12:24.85#ibcon#about to read 6, iclass 13, count 0 2006.257.16:12:24.85#ibcon#read 6, iclass 13, count 0 2006.257.16:12:24.85#ibcon#end of sib2, iclass 13, count 0 2006.257.16:12:24.85#ibcon#*after write, iclass 13, count 0 2006.257.16:12:24.85#ibcon#*before return 0, iclass 13, count 0 2006.257.16:12:24.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:24.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:12:24.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.16:12:24.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.16:12:24.85$vck44/vb=6,4 2006.257.16:12:24.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.16:12:24.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.16:12:24.85#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:24.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:24.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:24.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:24.91#ibcon#enter wrdev, iclass 15, count 2 2006.257.16:12:24.91#ibcon#first serial, iclass 15, count 2 2006.257.16:12:24.91#ibcon#enter sib2, iclass 15, count 2 2006.257.16:12:24.91#ibcon#flushed, iclass 15, count 2 2006.257.16:12:24.91#ibcon#about to write, iclass 15, count 2 2006.257.16:12:24.91#ibcon#wrote, iclass 15, count 2 2006.257.16:12:24.91#ibcon#about to read 3, iclass 15, count 2 2006.257.16:12:24.93#ibcon#read 3, iclass 15, count 2 2006.257.16:12:24.93#ibcon#about to read 4, iclass 15, count 2 2006.257.16:12:24.93#ibcon#read 4, iclass 15, count 2 2006.257.16:12:24.93#ibcon#about to read 5, iclass 15, count 2 2006.257.16:12:24.93#ibcon#read 5, iclass 15, count 2 2006.257.16:12:24.93#ibcon#about to read 6, iclass 15, count 2 2006.257.16:12:24.93#ibcon#read 6, iclass 15, count 2 2006.257.16:12:24.93#ibcon#end of sib2, iclass 15, count 2 2006.257.16:12:24.93#ibcon#*mode == 0, iclass 15, count 2 2006.257.16:12:24.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.16:12:24.93#ibcon#[27=AT06-04\r\n] 2006.257.16:12:24.93#ibcon#*before write, iclass 15, count 2 2006.257.16:12:24.93#ibcon#enter sib2, iclass 15, count 2 2006.257.16:12:24.93#ibcon#flushed, iclass 15, count 2 2006.257.16:12:24.93#ibcon#about to write, iclass 15, count 2 2006.257.16:12:24.93#ibcon#wrote, iclass 15, count 2 2006.257.16:12:24.93#ibcon#about to read 3, iclass 15, count 2 2006.257.16:12:24.96#ibcon#read 3, iclass 15, count 2 2006.257.16:12:24.96#ibcon#about to read 4, iclass 15, count 2 2006.257.16:12:24.96#ibcon#read 4, iclass 15, count 2 2006.257.16:12:24.96#ibcon#about to read 5, iclass 15, count 2 2006.257.16:12:24.96#ibcon#read 5, iclass 15, count 2 2006.257.16:12:24.96#ibcon#about to read 6, iclass 15, count 2 2006.257.16:12:24.96#ibcon#read 6, iclass 15, count 2 2006.257.16:12:24.96#ibcon#end of sib2, iclass 15, count 2 2006.257.16:12:24.96#ibcon#*after write, iclass 15, count 2 2006.257.16:12:24.96#ibcon#*before return 0, iclass 15, count 2 2006.257.16:12:24.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:24.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:12:24.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.16:12:24.96#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:24.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:25.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:25.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:25.08#ibcon#enter wrdev, iclass 15, count 0 2006.257.16:12:25.08#ibcon#first serial, iclass 15, count 0 2006.257.16:12:25.08#ibcon#enter sib2, iclass 15, count 0 2006.257.16:12:25.08#ibcon#flushed, iclass 15, count 0 2006.257.16:12:25.08#ibcon#about to write, iclass 15, count 0 2006.257.16:12:25.08#ibcon#wrote, iclass 15, count 0 2006.257.16:12:25.08#ibcon#about to read 3, iclass 15, count 0 2006.257.16:12:25.10#ibcon#read 3, iclass 15, count 0 2006.257.16:12:25.10#ibcon#about to read 4, iclass 15, count 0 2006.257.16:12:25.10#ibcon#read 4, iclass 15, count 0 2006.257.16:12:25.10#ibcon#about to read 5, iclass 15, count 0 2006.257.16:12:25.10#ibcon#read 5, iclass 15, count 0 2006.257.16:12:25.10#ibcon#about to read 6, iclass 15, count 0 2006.257.16:12:25.10#ibcon#read 6, iclass 15, count 0 2006.257.16:12:25.10#ibcon#end of sib2, iclass 15, count 0 2006.257.16:12:25.10#ibcon#*mode == 0, iclass 15, count 0 2006.257.16:12:25.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.16:12:25.10#ibcon#[27=USB\r\n] 2006.257.16:12:25.10#ibcon#*before write, iclass 15, count 0 2006.257.16:12:25.10#ibcon#enter sib2, iclass 15, count 0 2006.257.16:12:25.10#ibcon#flushed, iclass 15, count 0 2006.257.16:12:25.10#ibcon#about to write, iclass 15, count 0 2006.257.16:12:25.10#ibcon#wrote, iclass 15, count 0 2006.257.16:12:25.10#ibcon#about to read 3, iclass 15, count 0 2006.257.16:12:25.13#ibcon#read 3, iclass 15, count 0 2006.257.16:12:25.13#ibcon#about to read 4, iclass 15, count 0 2006.257.16:12:25.13#ibcon#read 4, iclass 15, count 0 2006.257.16:12:25.13#ibcon#about to read 5, iclass 15, count 0 2006.257.16:12:25.13#ibcon#read 5, iclass 15, count 0 2006.257.16:12:25.13#ibcon#about to read 6, iclass 15, count 0 2006.257.16:12:25.13#ibcon#read 6, iclass 15, count 0 2006.257.16:12:25.13#ibcon#end of sib2, iclass 15, count 0 2006.257.16:12:25.13#ibcon#*after write, iclass 15, count 0 2006.257.16:12:25.13#ibcon#*before return 0, iclass 15, count 0 2006.257.16:12:25.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:25.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:12:25.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.16:12:25.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.16:12:25.13$vck44/vblo=7,734.99 2006.257.16:12:25.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.16:12:25.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.16:12:25.13#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:25.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:25.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:25.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:25.13#ibcon#enter wrdev, iclass 17, count 0 2006.257.16:12:25.13#ibcon#first serial, iclass 17, count 0 2006.257.16:12:25.13#ibcon#enter sib2, iclass 17, count 0 2006.257.16:12:25.13#ibcon#flushed, iclass 17, count 0 2006.257.16:12:25.13#ibcon#about to write, iclass 17, count 0 2006.257.16:12:25.13#ibcon#wrote, iclass 17, count 0 2006.257.16:12:25.13#ibcon#about to read 3, iclass 17, count 0 2006.257.16:12:25.15#ibcon#read 3, iclass 17, count 0 2006.257.16:12:25.15#ibcon#about to read 4, iclass 17, count 0 2006.257.16:12:25.15#ibcon#read 4, iclass 17, count 0 2006.257.16:12:25.15#ibcon#about to read 5, iclass 17, count 0 2006.257.16:12:25.15#ibcon#read 5, iclass 17, count 0 2006.257.16:12:25.15#ibcon#about to read 6, iclass 17, count 0 2006.257.16:12:25.15#ibcon#read 6, iclass 17, count 0 2006.257.16:12:25.15#ibcon#end of sib2, iclass 17, count 0 2006.257.16:12:25.15#ibcon#*mode == 0, iclass 17, count 0 2006.257.16:12:25.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.16:12:25.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:12:25.15#ibcon#*before write, iclass 17, count 0 2006.257.16:12:25.15#ibcon#enter sib2, iclass 17, count 0 2006.257.16:12:25.15#ibcon#flushed, iclass 17, count 0 2006.257.16:12:25.15#ibcon#about to write, iclass 17, count 0 2006.257.16:12:25.15#ibcon#wrote, iclass 17, count 0 2006.257.16:12:25.15#ibcon#about to read 3, iclass 17, count 0 2006.257.16:12:25.19#ibcon#read 3, iclass 17, count 0 2006.257.16:12:25.19#ibcon#about to read 4, iclass 17, count 0 2006.257.16:12:25.19#ibcon#read 4, iclass 17, count 0 2006.257.16:12:25.19#ibcon#about to read 5, iclass 17, count 0 2006.257.16:12:25.19#ibcon#read 5, iclass 17, count 0 2006.257.16:12:25.19#ibcon#about to read 6, iclass 17, count 0 2006.257.16:12:25.19#ibcon#read 6, iclass 17, count 0 2006.257.16:12:25.19#ibcon#end of sib2, iclass 17, count 0 2006.257.16:12:25.19#ibcon#*after write, iclass 17, count 0 2006.257.16:12:25.19#ibcon#*before return 0, iclass 17, count 0 2006.257.16:12:25.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:25.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:12:25.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.16:12:25.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.16:12:25.19$vck44/vb=7,4 2006.257.16:12:25.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.16:12:25.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.16:12:25.19#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:25.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:25.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:25.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:25.25#ibcon#enter wrdev, iclass 19, count 2 2006.257.16:12:25.25#ibcon#first serial, iclass 19, count 2 2006.257.16:12:25.25#ibcon#enter sib2, iclass 19, count 2 2006.257.16:12:25.25#ibcon#flushed, iclass 19, count 2 2006.257.16:12:25.25#ibcon#about to write, iclass 19, count 2 2006.257.16:12:25.25#ibcon#wrote, iclass 19, count 2 2006.257.16:12:25.25#ibcon#about to read 3, iclass 19, count 2 2006.257.16:12:25.27#ibcon#read 3, iclass 19, count 2 2006.257.16:12:25.27#ibcon#about to read 4, iclass 19, count 2 2006.257.16:12:25.27#ibcon#read 4, iclass 19, count 2 2006.257.16:12:25.27#ibcon#about to read 5, iclass 19, count 2 2006.257.16:12:25.27#ibcon#read 5, iclass 19, count 2 2006.257.16:12:25.27#ibcon#about to read 6, iclass 19, count 2 2006.257.16:12:25.27#ibcon#read 6, iclass 19, count 2 2006.257.16:12:25.27#ibcon#end of sib2, iclass 19, count 2 2006.257.16:12:25.27#ibcon#*mode == 0, iclass 19, count 2 2006.257.16:12:25.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.16:12:25.27#ibcon#[27=AT07-04\r\n] 2006.257.16:12:25.27#ibcon#*before write, iclass 19, count 2 2006.257.16:12:25.27#ibcon#enter sib2, iclass 19, count 2 2006.257.16:12:25.27#ibcon#flushed, iclass 19, count 2 2006.257.16:12:25.27#ibcon#about to write, iclass 19, count 2 2006.257.16:12:25.27#ibcon#wrote, iclass 19, count 2 2006.257.16:12:25.27#ibcon#about to read 3, iclass 19, count 2 2006.257.16:12:25.30#ibcon#read 3, iclass 19, count 2 2006.257.16:12:25.30#ibcon#about to read 4, iclass 19, count 2 2006.257.16:12:25.30#ibcon#read 4, iclass 19, count 2 2006.257.16:12:25.30#ibcon#about to read 5, iclass 19, count 2 2006.257.16:12:25.30#ibcon#read 5, iclass 19, count 2 2006.257.16:12:25.30#ibcon#about to read 6, iclass 19, count 2 2006.257.16:12:25.30#ibcon#read 6, iclass 19, count 2 2006.257.16:12:25.30#ibcon#end of sib2, iclass 19, count 2 2006.257.16:12:25.30#ibcon#*after write, iclass 19, count 2 2006.257.16:12:25.30#ibcon#*before return 0, iclass 19, count 2 2006.257.16:12:25.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:25.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:12:25.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.16:12:25.30#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:25.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:25.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:25.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:25.42#ibcon#enter wrdev, iclass 19, count 0 2006.257.16:12:25.42#ibcon#first serial, iclass 19, count 0 2006.257.16:12:25.42#ibcon#enter sib2, iclass 19, count 0 2006.257.16:12:25.42#ibcon#flushed, iclass 19, count 0 2006.257.16:12:25.42#ibcon#about to write, iclass 19, count 0 2006.257.16:12:25.42#ibcon#wrote, iclass 19, count 0 2006.257.16:12:25.42#ibcon#about to read 3, iclass 19, count 0 2006.257.16:12:25.44#ibcon#read 3, iclass 19, count 0 2006.257.16:12:25.44#ibcon#about to read 4, iclass 19, count 0 2006.257.16:12:25.44#ibcon#read 4, iclass 19, count 0 2006.257.16:12:25.44#ibcon#about to read 5, iclass 19, count 0 2006.257.16:12:25.44#ibcon#read 5, iclass 19, count 0 2006.257.16:12:25.44#ibcon#about to read 6, iclass 19, count 0 2006.257.16:12:25.44#ibcon#read 6, iclass 19, count 0 2006.257.16:12:25.44#ibcon#end of sib2, iclass 19, count 0 2006.257.16:12:25.44#ibcon#*mode == 0, iclass 19, count 0 2006.257.16:12:25.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.16:12:25.44#ibcon#[27=USB\r\n] 2006.257.16:12:25.44#ibcon#*before write, iclass 19, count 0 2006.257.16:12:25.44#ibcon#enter sib2, iclass 19, count 0 2006.257.16:12:25.44#ibcon#flushed, iclass 19, count 0 2006.257.16:12:25.44#ibcon#about to write, iclass 19, count 0 2006.257.16:12:25.44#ibcon#wrote, iclass 19, count 0 2006.257.16:12:25.44#ibcon#about to read 3, iclass 19, count 0 2006.257.16:12:25.47#ibcon#read 3, iclass 19, count 0 2006.257.16:12:25.47#ibcon#about to read 4, iclass 19, count 0 2006.257.16:12:25.47#ibcon#read 4, iclass 19, count 0 2006.257.16:12:25.47#ibcon#about to read 5, iclass 19, count 0 2006.257.16:12:25.47#ibcon#read 5, iclass 19, count 0 2006.257.16:12:25.47#ibcon#about to read 6, iclass 19, count 0 2006.257.16:12:25.47#ibcon#read 6, iclass 19, count 0 2006.257.16:12:25.47#ibcon#end of sib2, iclass 19, count 0 2006.257.16:12:25.47#ibcon#*after write, iclass 19, count 0 2006.257.16:12:25.47#ibcon#*before return 0, iclass 19, count 0 2006.257.16:12:25.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:25.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:12:25.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.16:12:25.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.16:12:25.47$vck44/vblo=8,744.99 2006.257.16:12:25.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.16:12:25.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.16:12:25.47#ibcon#ireg 17 cls_cnt 0 2006.257.16:12:25.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:25.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:25.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:25.47#ibcon#enter wrdev, iclass 21, count 0 2006.257.16:12:25.47#ibcon#first serial, iclass 21, count 0 2006.257.16:12:25.47#ibcon#enter sib2, iclass 21, count 0 2006.257.16:12:25.47#ibcon#flushed, iclass 21, count 0 2006.257.16:12:25.47#ibcon#about to write, iclass 21, count 0 2006.257.16:12:25.47#ibcon#wrote, iclass 21, count 0 2006.257.16:12:25.47#ibcon#about to read 3, iclass 21, count 0 2006.257.16:12:25.49#ibcon#read 3, iclass 21, count 0 2006.257.16:12:25.49#ibcon#about to read 4, iclass 21, count 0 2006.257.16:12:25.49#ibcon#read 4, iclass 21, count 0 2006.257.16:12:25.49#ibcon#about to read 5, iclass 21, count 0 2006.257.16:12:25.49#ibcon#read 5, iclass 21, count 0 2006.257.16:12:25.49#ibcon#about to read 6, iclass 21, count 0 2006.257.16:12:25.49#ibcon#read 6, iclass 21, count 0 2006.257.16:12:25.49#ibcon#end of sib2, iclass 21, count 0 2006.257.16:12:25.49#ibcon#*mode == 0, iclass 21, count 0 2006.257.16:12:25.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.16:12:25.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:12:25.49#ibcon#*before write, iclass 21, count 0 2006.257.16:12:25.49#ibcon#enter sib2, iclass 21, count 0 2006.257.16:12:25.49#ibcon#flushed, iclass 21, count 0 2006.257.16:12:25.49#ibcon#about to write, iclass 21, count 0 2006.257.16:12:25.49#ibcon#wrote, iclass 21, count 0 2006.257.16:12:25.49#ibcon#about to read 3, iclass 21, count 0 2006.257.16:12:25.53#ibcon#read 3, iclass 21, count 0 2006.257.16:12:25.53#ibcon#about to read 4, iclass 21, count 0 2006.257.16:12:25.53#ibcon#read 4, iclass 21, count 0 2006.257.16:12:25.53#ibcon#about to read 5, iclass 21, count 0 2006.257.16:12:25.53#ibcon#read 5, iclass 21, count 0 2006.257.16:12:25.53#ibcon#about to read 6, iclass 21, count 0 2006.257.16:12:25.53#ibcon#read 6, iclass 21, count 0 2006.257.16:12:25.53#ibcon#end of sib2, iclass 21, count 0 2006.257.16:12:25.53#ibcon#*after write, iclass 21, count 0 2006.257.16:12:25.53#ibcon#*before return 0, iclass 21, count 0 2006.257.16:12:25.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:25.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:12:25.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.16:12:25.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.16:12:25.53$vck44/vb=8,4 2006.257.16:12:25.53#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.16:12:25.53#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.16:12:25.53#ibcon#ireg 11 cls_cnt 2 2006.257.16:12:25.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:25.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:25.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:25.59#ibcon#enter wrdev, iclass 23, count 2 2006.257.16:12:25.59#ibcon#first serial, iclass 23, count 2 2006.257.16:12:25.59#ibcon#enter sib2, iclass 23, count 2 2006.257.16:12:25.59#ibcon#flushed, iclass 23, count 2 2006.257.16:12:25.59#ibcon#about to write, iclass 23, count 2 2006.257.16:12:25.59#ibcon#wrote, iclass 23, count 2 2006.257.16:12:25.59#ibcon#about to read 3, iclass 23, count 2 2006.257.16:12:25.61#ibcon#read 3, iclass 23, count 2 2006.257.16:12:25.61#ibcon#about to read 4, iclass 23, count 2 2006.257.16:12:25.61#ibcon#read 4, iclass 23, count 2 2006.257.16:12:25.61#ibcon#about to read 5, iclass 23, count 2 2006.257.16:12:25.61#ibcon#read 5, iclass 23, count 2 2006.257.16:12:25.61#ibcon#about to read 6, iclass 23, count 2 2006.257.16:12:25.61#ibcon#read 6, iclass 23, count 2 2006.257.16:12:25.61#ibcon#end of sib2, iclass 23, count 2 2006.257.16:12:25.61#ibcon#*mode == 0, iclass 23, count 2 2006.257.16:12:25.61#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.16:12:25.61#ibcon#[27=AT08-04\r\n] 2006.257.16:12:25.61#ibcon#*before write, iclass 23, count 2 2006.257.16:12:25.61#ibcon#enter sib2, iclass 23, count 2 2006.257.16:12:25.61#ibcon#flushed, iclass 23, count 2 2006.257.16:12:25.61#ibcon#about to write, iclass 23, count 2 2006.257.16:12:25.61#ibcon#wrote, iclass 23, count 2 2006.257.16:12:25.61#ibcon#about to read 3, iclass 23, count 2 2006.257.16:12:25.64#ibcon#read 3, iclass 23, count 2 2006.257.16:12:25.64#ibcon#about to read 4, iclass 23, count 2 2006.257.16:12:25.64#ibcon#read 4, iclass 23, count 2 2006.257.16:12:25.64#ibcon#about to read 5, iclass 23, count 2 2006.257.16:12:25.64#ibcon#read 5, iclass 23, count 2 2006.257.16:12:25.64#ibcon#about to read 6, iclass 23, count 2 2006.257.16:12:25.64#ibcon#read 6, iclass 23, count 2 2006.257.16:12:25.64#ibcon#end of sib2, iclass 23, count 2 2006.257.16:12:25.64#ibcon#*after write, iclass 23, count 2 2006.257.16:12:25.64#ibcon#*before return 0, iclass 23, count 2 2006.257.16:12:25.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:25.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:12:25.64#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.16:12:25.64#ibcon#ireg 7 cls_cnt 0 2006.257.16:12:25.64#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:25.76#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:25.76#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:25.76#ibcon#enter wrdev, iclass 23, count 0 2006.257.16:12:25.76#ibcon#first serial, iclass 23, count 0 2006.257.16:12:25.76#ibcon#enter sib2, iclass 23, count 0 2006.257.16:12:25.76#ibcon#flushed, iclass 23, count 0 2006.257.16:12:25.76#ibcon#about to write, iclass 23, count 0 2006.257.16:12:25.76#ibcon#wrote, iclass 23, count 0 2006.257.16:12:25.76#ibcon#about to read 3, iclass 23, count 0 2006.257.16:12:25.78#ibcon#read 3, iclass 23, count 0 2006.257.16:12:25.78#ibcon#about to read 4, iclass 23, count 0 2006.257.16:12:25.78#ibcon#read 4, iclass 23, count 0 2006.257.16:12:25.78#ibcon#about to read 5, iclass 23, count 0 2006.257.16:12:25.78#ibcon#read 5, iclass 23, count 0 2006.257.16:12:25.78#ibcon#about to read 6, iclass 23, count 0 2006.257.16:12:25.78#ibcon#read 6, iclass 23, count 0 2006.257.16:12:25.78#ibcon#end of sib2, iclass 23, count 0 2006.257.16:12:25.78#ibcon#*mode == 0, iclass 23, count 0 2006.257.16:12:25.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.16:12:25.78#ibcon#[27=USB\r\n] 2006.257.16:12:25.78#ibcon#*before write, iclass 23, count 0 2006.257.16:12:25.78#ibcon#enter sib2, iclass 23, count 0 2006.257.16:12:25.78#ibcon#flushed, iclass 23, count 0 2006.257.16:12:25.78#ibcon#about to write, iclass 23, count 0 2006.257.16:12:25.78#ibcon#wrote, iclass 23, count 0 2006.257.16:12:25.78#ibcon#about to read 3, iclass 23, count 0 2006.257.16:12:25.81#ibcon#read 3, iclass 23, count 0 2006.257.16:12:25.81#ibcon#about to read 4, iclass 23, count 0 2006.257.16:12:25.81#ibcon#read 4, iclass 23, count 0 2006.257.16:12:25.81#ibcon#about to read 5, iclass 23, count 0 2006.257.16:12:25.81#ibcon#read 5, iclass 23, count 0 2006.257.16:12:25.81#ibcon#about to read 6, iclass 23, count 0 2006.257.16:12:25.81#ibcon#read 6, iclass 23, count 0 2006.257.16:12:25.81#ibcon#end of sib2, iclass 23, count 0 2006.257.16:12:25.81#ibcon#*after write, iclass 23, count 0 2006.257.16:12:25.81#ibcon#*before return 0, iclass 23, count 0 2006.257.16:12:25.81#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:25.81#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:12:25.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.16:12:25.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.16:12:25.81$vck44/vabw=wide 2006.257.16:12:25.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.16:12:25.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.16:12:25.81#ibcon#ireg 8 cls_cnt 0 2006.257.16:12:25.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:25.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:25.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:25.81#ibcon#enter wrdev, iclass 25, count 0 2006.257.16:12:25.81#ibcon#first serial, iclass 25, count 0 2006.257.16:12:25.81#ibcon#enter sib2, iclass 25, count 0 2006.257.16:12:25.81#ibcon#flushed, iclass 25, count 0 2006.257.16:12:25.81#ibcon#about to write, iclass 25, count 0 2006.257.16:12:25.81#ibcon#wrote, iclass 25, count 0 2006.257.16:12:25.81#ibcon#about to read 3, iclass 25, count 0 2006.257.16:12:25.83#ibcon#read 3, iclass 25, count 0 2006.257.16:12:25.83#ibcon#about to read 4, iclass 25, count 0 2006.257.16:12:25.83#ibcon#read 4, iclass 25, count 0 2006.257.16:12:25.83#ibcon#about to read 5, iclass 25, count 0 2006.257.16:12:25.83#ibcon#read 5, iclass 25, count 0 2006.257.16:12:25.83#ibcon#about to read 6, iclass 25, count 0 2006.257.16:12:25.83#ibcon#read 6, iclass 25, count 0 2006.257.16:12:25.83#ibcon#end of sib2, iclass 25, count 0 2006.257.16:12:25.83#ibcon#*mode == 0, iclass 25, count 0 2006.257.16:12:25.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.16:12:25.83#ibcon#[25=BW32\r\n] 2006.257.16:12:25.83#ibcon#*before write, iclass 25, count 0 2006.257.16:12:25.83#ibcon#enter sib2, iclass 25, count 0 2006.257.16:12:25.83#ibcon#flushed, iclass 25, count 0 2006.257.16:12:25.83#ibcon#about to write, iclass 25, count 0 2006.257.16:12:25.83#ibcon#wrote, iclass 25, count 0 2006.257.16:12:25.83#ibcon#about to read 3, iclass 25, count 0 2006.257.16:12:25.86#ibcon#read 3, iclass 25, count 0 2006.257.16:12:25.86#ibcon#about to read 4, iclass 25, count 0 2006.257.16:12:25.86#ibcon#read 4, iclass 25, count 0 2006.257.16:12:25.86#ibcon#about to read 5, iclass 25, count 0 2006.257.16:12:25.86#ibcon#read 5, iclass 25, count 0 2006.257.16:12:25.86#ibcon#about to read 6, iclass 25, count 0 2006.257.16:12:25.86#ibcon#read 6, iclass 25, count 0 2006.257.16:12:25.86#ibcon#end of sib2, iclass 25, count 0 2006.257.16:12:25.86#ibcon#*after write, iclass 25, count 0 2006.257.16:12:25.86#ibcon#*before return 0, iclass 25, count 0 2006.257.16:12:25.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:25.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:12:25.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.16:12:25.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.16:12:25.86$vck44/vbbw=wide 2006.257.16:12:25.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.16:12:25.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.16:12:25.86#ibcon#ireg 8 cls_cnt 0 2006.257.16:12:25.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:12:25.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:12:25.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:12:25.93#ibcon#enter wrdev, iclass 27, count 0 2006.257.16:12:25.93#ibcon#first serial, iclass 27, count 0 2006.257.16:12:25.93#ibcon#enter sib2, iclass 27, count 0 2006.257.16:12:25.93#ibcon#flushed, iclass 27, count 0 2006.257.16:12:25.93#ibcon#about to write, iclass 27, count 0 2006.257.16:12:25.93#ibcon#wrote, iclass 27, count 0 2006.257.16:12:25.93#ibcon#about to read 3, iclass 27, count 0 2006.257.16:12:25.95#ibcon#read 3, iclass 27, count 0 2006.257.16:12:25.95#ibcon#about to read 4, iclass 27, count 0 2006.257.16:12:25.95#ibcon#read 4, iclass 27, count 0 2006.257.16:12:25.95#ibcon#about to read 5, iclass 27, count 0 2006.257.16:12:25.95#ibcon#read 5, iclass 27, count 0 2006.257.16:12:25.95#ibcon#about to read 6, iclass 27, count 0 2006.257.16:12:25.95#ibcon#read 6, iclass 27, count 0 2006.257.16:12:25.95#ibcon#end of sib2, iclass 27, count 0 2006.257.16:12:25.95#ibcon#*mode == 0, iclass 27, count 0 2006.257.16:12:25.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.16:12:25.95#ibcon#[27=BW32\r\n] 2006.257.16:12:25.95#ibcon#*before write, iclass 27, count 0 2006.257.16:12:25.95#ibcon#enter sib2, iclass 27, count 0 2006.257.16:12:25.95#ibcon#flushed, iclass 27, count 0 2006.257.16:12:25.95#ibcon#about to write, iclass 27, count 0 2006.257.16:12:25.95#ibcon#wrote, iclass 27, count 0 2006.257.16:12:25.95#ibcon#about to read 3, iclass 27, count 0 2006.257.16:12:25.98#ibcon#read 3, iclass 27, count 0 2006.257.16:12:25.98#ibcon#about to read 4, iclass 27, count 0 2006.257.16:12:25.98#ibcon#read 4, iclass 27, count 0 2006.257.16:12:25.98#ibcon#about to read 5, iclass 27, count 0 2006.257.16:12:25.98#ibcon#read 5, iclass 27, count 0 2006.257.16:12:25.98#ibcon#about to read 6, iclass 27, count 0 2006.257.16:12:25.98#ibcon#read 6, iclass 27, count 0 2006.257.16:12:25.98#ibcon#end of sib2, iclass 27, count 0 2006.257.16:12:25.98#ibcon#*after write, iclass 27, count 0 2006.257.16:12:25.98#ibcon#*before return 0, iclass 27, count 0 2006.257.16:12:25.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:12:25.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:12:25.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.16:12:25.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.16:12:25.98$setupk4/ifdk4 2006.257.16:12:25.98$ifdk4/lo= 2006.257.16:12:25.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:12:25.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:12:25.98$ifdk4/patch= 2006.257.16:12:25.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:12:25.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:12:25.98$setupk4/!*+20s 2006.257.16:12:26.73#abcon#<5=/14 1.4 4.2 17.30 971014.0\r\n> 2006.257.16:12:26.75#abcon#{5=INTERFACE CLEAR} 2006.257.16:12:26.81#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:12:36.90#abcon#<5=/14 1.4 4.2 17.30 971014.0\r\n> 2006.257.16:12:36.92#abcon#{5=INTERFACE CLEAR} 2006.257.16:12:36.98#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:12:40.49$setupk4/"tpicd 2006.257.16:12:40.49$setupk4/echo=off 2006.257.16:12:40.49$setupk4/xlog=off 2006.257.16:12:40.49:!2006.257.16:17:32 2006.257.16:13:29.14#trakl#Source acquired 2006.257.16:13:29.14#flagr#flagr/antenna,acquired 2006.257.16:17:32.01:preob 2006.257.16:17:33.14/onsource/TRACKING 2006.257.16:17:33.14:!2006.257.16:17:42 2006.257.16:17:42.00:"tape 2006.257.16:17:42.00:"st=record 2006.257.16:17:42.00:data_valid=on 2006.257.16:17:42.01:midob 2006.257.16:17:42.14/onsource/TRACKING 2006.257.16:17:42.15/wx/17.23,1014.1,97 2006.257.16:17:42.20/cable/+6.4869E-03 2006.257.16:17:43.29/va/01,08,usb,yes,30,33 2006.257.16:17:43.29/va/02,07,usb,yes,33,33 2006.257.16:17:43.29/va/03,08,usb,yes,29,31 2006.257.16:17:43.29/va/04,07,usb,yes,34,36 2006.257.16:17:43.29/va/05,04,usb,yes,30,31 2006.257.16:17:43.29/va/06,04,usb,yes,34,33 2006.257.16:17:43.29/va/07,04,usb,yes,35,35 2006.257.16:17:43.29/va/08,04,usb,yes,29,36 2006.257.16:17:43.52/valo/01,524.99,yes,locked 2006.257.16:17:43.52/valo/02,534.99,yes,locked 2006.257.16:17:43.52/valo/03,564.99,yes,locked 2006.257.16:17:43.52/valo/04,624.99,yes,locked 2006.257.16:17:43.52/valo/05,734.99,yes,locked 2006.257.16:17:43.52/valo/06,814.99,yes,locked 2006.257.16:17:43.52/valo/07,864.99,yes,locked 2006.257.16:17:43.52/valo/08,884.99,yes,locked 2006.257.16:17:44.61/vb/01,04,usb,yes,30,28 2006.257.16:17:44.61/vb/02,05,usb,yes,29,29 2006.257.16:17:44.61/vb/03,04,usb,yes,30,33 2006.257.16:17:44.61/vb/04,05,usb,yes,30,29 2006.257.16:17:44.61/vb/05,04,usb,yes,26,29 2006.257.16:17:44.61/vb/06,04,usb,yes,31,27 2006.257.16:17:44.61/vb/07,04,usb,yes,31,31 2006.257.16:17:44.61/vb/08,04,usb,yes,28,32 2006.257.16:17:44.85/vblo/01,629.99,yes,locked 2006.257.16:17:44.85/vblo/02,634.99,yes,locked 2006.257.16:17:44.85/vblo/03,649.99,yes,locked 2006.257.16:17:44.85/vblo/04,679.99,yes,locked 2006.257.16:17:44.85/vblo/05,709.99,yes,locked 2006.257.16:17:44.85/vblo/06,719.99,yes,locked 2006.257.16:17:44.85/vblo/07,734.99,yes,locked 2006.257.16:17:44.85/vblo/08,744.99,yes,locked 2006.257.16:17:45.00/vabw/8 2006.257.16:17:45.15/vbbw/8 2006.257.16:17:45.24/xfe/off,on,14.5 2006.257.16:17:45.61/ifatt/23,28,28,28 2006.257.16:17:46.07/fmout-gps/S +4.59E-07 2006.257.16:17:46.11:!2006.257.16:19:02 2006.257.16:19:02.01:data_valid=off 2006.257.16:19:02.01:"et 2006.257.16:19:02.02:!+3s 2006.257.16:19:05.04:"tape 2006.257.16:19:05.04:postob 2006.257.16:19:05.19/cable/+6.4841E-03 2006.257.16:19:05.19/wx/17.21,1014.1,97 2006.257.16:19:05.25/fmout-gps/S +4.58E-07 2006.257.16:19:05.25:scan_name=257-1623,jd0609,170 2006.257.16:19:05.25:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.16:19:06.14#flagr#flagr/antenna,new-source 2006.257.16:19:06.14:checkk5 2006.257.16:19:06.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.16:19:06.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.16:19:07.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.16:19:07.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.16:19:07.85/chk_obsdata//k5ts1/T2571617??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.16:19:08.19/chk_obsdata//k5ts2/T2571617??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.16:19:08.54/chk_obsdata//k5ts3/T2571617??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.16:19:08.87/chk_obsdata//k5ts4/T2571617??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.257.16:19:09.52/k5log//k5ts1_log_newline 2006.257.16:19:10.19/k5log//k5ts2_log_newline 2006.257.16:19:10.86/k5log//k5ts3_log_newline 2006.257.16:19:11.51/k5log//k5ts4_log_newline 2006.257.16:19:11.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.16:19:11.54:setupk4=1 2006.257.16:19:11.54$setupk4/echo=on 2006.257.16:19:11.54$setupk4/pcalon 2006.257.16:19:11.54$pcalon/"no phase cal control is implemented here 2006.257.16:19:11.54$setupk4/"tpicd=stop 2006.257.16:19:11.54$setupk4/"rec=synch_on 2006.257.16:19:11.54$setupk4/"rec_mode=128 2006.257.16:19:11.54$setupk4/!* 2006.257.16:19:11.54$setupk4/recpk4 2006.257.16:19:11.54$recpk4/recpatch= 2006.257.16:19:11.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.16:19:11.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.16:19:11.55$setupk4/vck44 2006.257.16:19:11.55$vck44/valo=1,524.99 2006.257.16:19:11.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.16:19:11.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.16:19:11.55#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:11.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:11.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:11.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:11.55#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:19:11.55#ibcon#first serial, iclass 12, count 0 2006.257.16:19:11.55#ibcon#enter sib2, iclass 12, count 0 2006.257.16:19:11.55#ibcon#flushed, iclass 12, count 0 2006.257.16:19:11.55#ibcon#about to write, iclass 12, count 0 2006.257.16:19:11.55#ibcon#wrote, iclass 12, count 0 2006.257.16:19:11.55#ibcon#about to read 3, iclass 12, count 0 2006.257.16:19:11.56#ibcon#read 3, iclass 12, count 0 2006.257.16:19:11.56#ibcon#about to read 4, iclass 12, count 0 2006.257.16:19:11.56#ibcon#read 4, iclass 12, count 0 2006.257.16:19:11.56#ibcon#about to read 5, iclass 12, count 0 2006.257.16:19:11.56#ibcon#read 5, iclass 12, count 0 2006.257.16:19:11.56#ibcon#about to read 6, iclass 12, count 0 2006.257.16:19:11.56#ibcon#read 6, iclass 12, count 0 2006.257.16:19:11.56#ibcon#end of sib2, iclass 12, count 0 2006.257.16:19:11.56#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:19:11.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:19:11.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.16:19:11.56#ibcon#*before write, iclass 12, count 0 2006.257.16:19:11.56#ibcon#enter sib2, iclass 12, count 0 2006.257.16:19:11.56#ibcon#flushed, iclass 12, count 0 2006.257.16:19:11.56#ibcon#about to write, iclass 12, count 0 2006.257.16:19:11.56#ibcon#wrote, iclass 12, count 0 2006.257.16:19:11.56#ibcon#about to read 3, iclass 12, count 0 2006.257.16:19:11.61#ibcon#read 3, iclass 12, count 0 2006.257.16:19:11.61#ibcon#about to read 4, iclass 12, count 0 2006.257.16:19:11.61#ibcon#read 4, iclass 12, count 0 2006.257.16:19:11.61#ibcon#about to read 5, iclass 12, count 0 2006.257.16:19:11.61#ibcon#read 5, iclass 12, count 0 2006.257.16:19:11.61#ibcon#about to read 6, iclass 12, count 0 2006.257.16:19:11.61#ibcon#read 6, iclass 12, count 0 2006.257.16:19:11.61#ibcon#end of sib2, iclass 12, count 0 2006.257.16:19:11.61#ibcon#*after write, iclass 12, count 0 2006.257.16:19:11.61#ibcon#*before return 0, iclass 12, count 0 2006.257.16:19:11.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:11.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:11.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:19:11.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:19:11.61$vck44/va=1,8 2006.257.16:19:11.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.16:19:11.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.16:19:11.61#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:11.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:11.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:11.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:11.61#ibcon#enter wrdev, iclass 14, count 2 2006.257.16:19:11.61#ibcon#first serial, iclass 14, count 2 2006.257.16:19:11.61#ibcon#enter sib2, iclass 14, count 2 2006.257.16:19:11.61#ibcon#flushed, iclass 14, count 2 2006.257.16:19:11.61#ibcon#about to write, iclass 14, count 2 2006.257.16:19:11.61#ibcon#wrote, iclass 14, count 2 2006.257.16:19:11.61#ibcon#about to read 3, iclass 14, count 2 2006.257.16:19:11.63#ibcon#read 3, iclass 14, count 2 2006.257.16:19:11.63#ibcon#about to read 4, iclass 14, count 2 2006.257.16:19:11.63#ibcon#read 4, iclass 14, count 2 2006.257.16:19:11.63#ibcon#about to read 5, iclass 14, count 2 2006.257.16:19:11.63#ibcon#read 5, iclass 14, count 2 2006.257.16:19:11.63#ibcon#about to read 6, iclass 14, count 2 2006.257.16:19:11.63#ibcon#read 6, iclass 14, count 2 2006.257.16:19:11.63#ibcon#end of sib2, iclass 14, count 2 2006.257.16:19:11.63#ibcon#*mode == 0, iclass 14, count 2 2006.257.16:19:11.63#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.16:19:11.63#ibcon#[25=AT01-08\r\n] 2006.257.16:19:11.63#ibcon#*before write, iclass 14, count 2 2006.257.16:19:11.63#ibcon#enter sib2, iclass 14, count 2 2006.257.16:19:11.63#ibcon#flushed, iclass 14, count 2 2006.257.16:19:11.63#ibcon#about to write, iclass 14, count 2 2006.257.16:19:11.63#ibcon#wrote, iclass 14, count 2 2006.257.16:19:11.63#ibcon#about to read 3, iclass 14, count 2 2006.257.16:19:11.66#ibcon#read 3, iclass 14, count 2 2006.257.16:19:11.66#ibcon#about to read 4, iclass 14, count 2 2006.257.16:19:11.66#ibcon#read 4, iclass 14, count 2 2006.257.16:19:11.66#ibcon#about to read 5, iclass 14, count 2 2006.257.16:19:11.66#ibcon#read 5, iclass 14, count 2 2006.257.16:19:11.66#ibcon#about to read 6, iclass 14, count 2 2006.257.16:19:11.66#ibcon#read 6, iclass 14, count 2 2006.257.16:19:11.66#ibcon#end of sib2, iclass 14, count 2 2006.257.16:19:11.66#ibcon#*after write, iclass 14, count 2 2006.257.16:19:11.66#ibcon#*before return 0, iclass 14, count 2 2006.257.16:19:11.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:11.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:11.66#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.16:19:11.66#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:11.66#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:11.78#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:11.78#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:11.78#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:19:11.78#ibcon#first serial, iclass 14, count 0 2006.257.16:19:11.78#ibcon#enter sib2, iclass 14, count 0 2006.257.16:19:11.78#ibcon#flushed, iclass 14, count 0 2006.257.16:19:11.78#ibcon#about to write, iclass 14, count 0 2006.257.16:19:11.78#ibcon#wrote, iclass 14, count 0 2006.257.16:19:11.78#ibcon#about to read 3, iclass 14, count 0 2006.257.16:19:11.80#ibcon#read 3, iclass 14, count 0 2006.257.16:19:11.80#ibcon#about to read 4, iclass 14, count 0 2006.257.16:19:11.80#ibcon#read 4, iclass 14, count 0 2006.257.16:19:11.80#ibcon#about to read 5, iclass 14, count 0 2006.257.16:19:11.80#ibcon#read 5, iclass 14, count 0 2006.257.16:19:11.80#ibcon#about to read 6, iclass 14, count 0 2006.257.16:19:11.80#ibcon#read 6, iclass 14, count 0 2006.257.16:19:11.80#ibcon#end of sib2, iclass 14, count 0 2006.257.16:19:11.80#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:19:11.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:19:11.80#ibcon#[25=USB\r\n] 2006.257.16:19:11.80#ibcon#*before write, iclass 14, count 0 2006.257.16:19:11.80#ibcon#enter sib2, iclass 14, count 0 2006.257.16:19:11.80#ibcon#flushed, iclass 14, count 0 2006.257.16:19:11.80#ibcon#about to write, iclass 14, count 0 2006.257.16:19:11.80#ibcon#wrote, iclass 14, count 0 2006.257.16:19:11.80#ibcon#about to read 3, iclass 14, count 0 2006.257.16:19:11.83#ibcon#read 3, iclass 14, count 0 2006.257.16:19:11.83#ibcon#about to read 4, iclass 14, count 0 2006.257.16:19:11.83#ibcon#read 4, iclass 14, count 0 2006.257.16:19:11.83#ibcon#about to read 5, iclass 14, count 0 2006.257.16:19:11.83#ibcon#read 5, iclass 14, count 0 2006.257.16:19:11.83#ibcon#about to read 6, iclass 14, count 0 2006.257.16:19:11.83#ibcon#read 6, iclass 14, count 0 2006.257.16:19:11.83#ibcon#end of sib2, iclass 14, count 0 2006.257.16:19:11.83#ibcon#*after write, iclass 14, count 0 2006.257.16:19:11.83#ibcon#*before return 0, iclass 14, count 0 2006.257.16:19:11.83#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:11.83#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:11.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:19:11.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:19:11.83$vck44/valo=2,534.99 2006.257.16:19:11.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.16:19:11.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.16:19:11.83#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:11.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:11.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:11.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:11.83#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:19:11.83#ibcon#first serial, iclass 16, count 0 2006.257.16:19:11.83#ibcon#enter sib2, iclass 16, count 0 2006.257.16:19:11.83#ibcon#flushed, iclass 16, count 0 2006.257.16:19:11.83#ibcon#about to write, iclass 16, count 0 2006.257.16:19:11.83#ibcon#wrote, iclass 16, count 0 2006.257.16:19:11.83#ibcon#about to read 3, iclass 16, count 0 2006.257.16:19:11.85#ibcon#read 3, iclass 16, count 0 2006.257.16:19:11.85#ibcon#about to read 4, iclass 16, count 0 2006.257.16:19:11.85#ibcon#read 4, iclass 16, count 0 2006.257.16:19:11.85#ibcon#about to read 5, iclass 16, count 0 2006.257.16:19:11.85#ibcon#read 5, iclass 16, count 0 2006.257.16:19:11.85#ibcon#about to read 6, iclass 16, count 0 2006.257.16:19:11.85#ibcon#read 6, iclass 16, count 0 2006.257.16:19:11.85#ibcon#end of sib2, iclass 16, count 0 2006.257.16:19:11.85#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:19:11.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:19:11.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.16:19:11.85#ibcon#*before write, iclass 16, count 0 2006.257.16:19:11.85#ibcon#enter sib2, iclass 16, count 0 2006.257.16:19:11.85#ibcon#flushed, iclass 16, count 0 2006.257.16:19:11.85#ibcon#about to write, iclass 16, count 0 2006.257.16:19:11.85#ibcon#wrote, iclass 16, count 0 2006.257.16:19:11.85#ibcon#about to read 3, iclass 16, count 0 2006.257.16:19:11.89#ibcon#read 3, iclass 16, count 0 2006.257.16:19:11.89#ibcon#about to read 4, iclass 16, count 0 2006.257.16:19:11.89#ibcon#read 4, iclass 16, count 0 2006.257.16:19:11.89#ibcon#about to read 5, iclass 16, count 0 2006.257.16:19:11.89#ibcon#read 5, iclass 16, count 0 2006.257.16:19:11.89#ibcon#about to read 6, iclass 16, count 0 2006.257.16:19:11.89#ibcon#read 6, iclass 16, count 0 2006.257.16:19:11.89#ibcon#end of sib2, iclass 16, count 0 2006.257.16:19:11.89#ibcon#*after write, iclass 16, count 0 2006.257.16:19:11.89#ibcon#*before return 0, iclass 16, count 0 2006.257.16:19:11.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:11.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:11.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:19:11.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:19:11.89$vck44/va=2,7 2006.257.16:19:11.89#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.16:19:11.89#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.16:19:11.89#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:11.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:11.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:11.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:11.95#ibcon#enter wrdev, iclass 18, count 2 2006.257.16:19:11.95#ibcon#first serial, iclass 18, count 2 2006.257.16:19:11.95#ibcon#enter sib2, iclass 18, count 2 2006.257.16:19:11.95#ibcon#flushed, iclass 18, count 2 2006.257.16:19:11.95#ibcon#about to write, iclass 18, count 2 2006.257.16:19:11.95#ibcon#wrote, iclass 18, count 2 2006.257.16:19:11.95#ibcon#about to read 3, iclass 18, count 2 2006.257.16:19:11.97#ibcon#read 3, iclass 18, count 2 2006.257.16:19:11.97#ibcon#about to read 4, iclass 18, count 2 2006.257.16:19:11.97#ibcon#read 4, iclass 18, count 2 2006.257.16:19:11.97#ibcon#about to read 5, iclass 18, count 2 2006.257.16:19:11.97#ibcon#read 5, iclass 18, count 2 2006.257.16:19:11.97#ibcon#about to read 6, iclass 18, count 2 2006.257.16:19:11.97#ibcon#read 6, iclass 18, count 2 2006.257.16:19:11.97#ibcon#end of sib2, iclass 18, count 2 2006.257.16:19:11.97#ibcon#*mode == 0, iclass 18, count 2 2006.257.16:19:11.97#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.16:19:11.97#ibcon#[25=AT02-07\r\n] 2006.257.16:19:11.97#ibcon#*before write, iclass 18, count 2 2006.257.16:19:11.97#ibcon#enter sib2, iclass 18, count 2 2006.257.16:19:11.97#ibcon#flushed, iclass 18, count 2 2006.257.16:19:11.97#ibcon#about to write, iclass 18, count 2 2006.257.16:19:11.97#ibcon#wrote, iclass 18, count 2 2006.257.16:19:11.97#ibcon#about to read 3, iclass 18, count 2 2006.257.16:19:12.00#ibcon#read 3, iclass 18, count 2 2006.257.16:19:12.00#ibcon#about to read 4, iclass 18, count 2 2006.257.16:19:12.00#ibcon#read 4, iclass 18, count 2 2006.257.16:19:12.00#ibcon#about to read 5, iclass 18, count 2 2006.257.16:19:12.00#ibcon#read 5, iclass 18, count 2 2006.257.16:19:12.00#ibcon#about to read 6, iclass 18, count 2 2006.257.16:19:12.00#ibcon#read 6, iclass 18, count 2 2006.257.16:19:12.00#ibcon#end of sib2, iclass 18, count 2 2006.257.16:19:12.00#ibcon#*after write, iclass 18, count 2 2006.257.16:19:12.00#ibcon#*before return 0, iclass 18, count 2 2006.257.16:19:12.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:12.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:12.00#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.16:19:12.00#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:12.00#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:12.12#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:12.12#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:12.12#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:19:12.12#ibcon#first serial, iclass 18, count 0 2006.257.16:19:12.12#ibcon#enter sib2, iclass 18, count 0 2006.257.16:19:12.12#ibcon#flushed, iclass 18, count 0 2006.257.16:19:12.12#ibcon#about to write, iclass 18, count 0 2006.257.16:19:12.12#ibcon#wrote, iclass 18, count 0 2006.257.16:19:12.12#ibcon#about to read 3, iclass 18, count 0 2006.257.16:19:12.14#ibcon#read 3, iclass 18, count 0 2006.257.16:19:12.14#ibcon#about to read 4, iclass 18, count 0 2006.257.16:19:12.14#ibcon#read 4, iclass 18, count 0 2006.257.16:19:12.14#ibcon#about to read 5, iclass 18, count 0 2006.257.16:19:12.14#ibcon#read 5, iclass 18, count 0 2006.257.16:19:12.14#ibcon#about to read 6, iclass 18, count 0 2006.257.16:19:12.14#ibcon#read 6, iclass 18, count 0 2006.257.16:19:12.14#ibcon#end of sib2, iclass 18, count 0 2006.257.16:19:12.14#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:19:12.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:19:12.14#ibcon#[25=USB\r\n] 2006.257.16:19:12.14#ibcon#*before write, iclass 18, count 0 2006.257.16:19:12.14#ibcon#enter sib2, iclass 18, count 0 2006.257.16:19:12.14#ibcon#flushed, iclass 18, count 0 2006.257.16:19:12.14#ibcon#about to write, iclass 18, count 0 2006.257.16:19:12.14#ibcon#wrote, iclass 18, count 0 2006.257.16:19:12.14#ibcon#about to read 3, iclass 18, count 0 2006.257.16:19:12.17#ibcon#read 3, iclass 18, count 0 2006.257.16:19:12.17#ibcon#about to read 4, iclass 18, count 0 2006.257.16:19:12.17#ibcon#read 4, iclass 18, count 0 2006.257.16:19:12.17#ibcon#about to read 5, iclass 18, count 0 2006.257.16:19:12.17#ibcon#read 5, iclass 18, count 0 2006.257.16:19:12.17#ibcon#about to read 6, iclass 18, count 0 2006.257.16:19:12.17#ibcon#read 6, iclass 18, count 0 2006.257.16:19:12.17#ibcon#end of sib2, iclass 18, count 0 2006.257.16:19:12.17#ibcon#*after write, iclass 18, count 0 2006.257.16:19:12.17#ibcon#*before return 0, iclass 18, count 0 2006.257.16:19:12.17#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:12.17#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:12.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:19:12.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:19:12.17$vck44/valo=3,564.99 2006.257.16:19:12.17#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.16:19:12.17#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.16:19:12.17#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:12.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:12.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:12.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:12.17#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:19:12.17#ibcon#first serial, iclass 20, count 0 2006.257.16:19:12.17#ibcon#enter sib2, iclass 20, count 0 2006.257.16:19:12.17#ibcon#flushed, iclass 20, count 0 2006.257.16:19:12.17#ibcon#about to write, iclass 20, count 0 2006.257.16:19:12.17#ibcon#wrote, iclass 20, count 0 2006.257.16:19:12.17#ibcon#about to read 3, iclass 20, count 0 2006.257.16:19:12.19#ibcon#read 3, iclass 20, count 0 2006.257.16:19:12.19#ibcon#about to read 4, iclass 20, count 0 2006.257.16:19:12.19#ibcon#read 4, iclass 20, count 0 2006.257.16:19:12.19#ibcon#about to read 5, iclass 20, count 0 2006.257.16:19:12.19#ibcon#read 5, iclass 20, count 0 2006.257.16:19:12.19#ibcon#about to read 6, iclass 20, count 0 2006.257.16:19:12.19#ibcon#read 6, iclass 20, count 0 2006.257.16:19:12.19#ibcon#end of sib2, iclass 20, count 0 2006.257.16:19:12.19#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:19:12.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:19:12.19#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.16:19:12.19#ibcon#*before write, iclass 20, count 0 2006.257.16:19:12.19#ibcon#enter sib2, iclass 20, count 0 2006.257.16:19:12.19#ibcon#flushed, iclass 20, count 0 2006.257.16:19:12.19#ibcon#about to write, iclass 20, count 0 2006.257.16:19:12.19#ibcon#wrote, iclass 20, count 0 2006.257.16:19:12.19#ibcon#about to read 3, iclass 20, count 0 2006.257.16:19:12.23#ibcon#read 3, iclass 20, count 0 2006.257.16:19:12.23#ibcon#about to read 4, iclass 20, count 0 2006.257.16:19:12.23#ibcon#read 4, iclass 20, count 0 2006.257.16:19:12.23#ibcon#about to read 5, iclass 20, count 0 2006.257.16:19:12.23#ibcon#read 5, iclass 20, count 0 2006.257.16:19:12.23#ibcon#about to read 6, iclass 20, count 0 2006.257.16:19:12.23#ibcon#read 6, iclass 20, count 0 2006.257.16:19:12.23#ibcon#end of sib2, iclass 20, count 0 2006.257.16:19:12.23#ibcon#*after write, iclass 20, count 0 2006.257.16:19:12.23#ibcon#*before return 0, iclass 20, count 0 2006.257.16:19:12.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:12.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:12.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:19:12.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:19:12.23$vck44/va=3,8 2006.257.16:19:12.23#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.16:19:12.23#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.16:19:12.23#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:12.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:12.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:12.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:12.29#ibcon#enter wrdev, iclass 22, count 2 2006.257.16:19:12.29#ibcon#first serial, iclass 22, count 2 2006.257.16:19:12.29#ibcon#enter sib2, iclass 22, count 2 2006.257.16:19:12.29#ibcon#flushed, iclass 22, count 2 2006.257.16:19:12.29#ibcon#about to write, iclass 22, count 2 2006.257.16:19:12.29#ibcon#wrote, iclass 22, count 2 2006.257.16:19:12.29#ibcon#about to read 3, iclass 22, count 2 2006.257.16:19:12.31#ibcon#read 3, iclass 22, count 2 2006.257.16:19:12.31#ibcon#about to read 4, iclass 22, count 2 2006.257.16:19:12.31#ibcon#read 4, iclass 22, count 2 2006.257.16:19:12.31#ibcon#about to read 5, iclass 22, count 2 2006.257.16:19:12.31#ibcon#read 5, iclass 22, count 2 2006.257.16:19:12.31#ibcon#about to read 6, iclass 22, count 2 2006.257.16:19:12.31#ibcon#read 6, iclass 22, count 2 2006.257.16:19:12.31#ibcon#end of sib2, iclass 22, count 2 2006.257.16:19:12.31#ibcon#*mode == 0, iclass 22, count 2 2006.257.16:19:12.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.16:19:12.31#ibcon#[25=AT03-08\r\n] 2006.257.16:19:12.31#ibcon#*before write, iclass 22, count 2 2006.257.16:19:12.31#ibcon#enter sib2, iclass 22, count 2 2006.257.16:19:12.31#ibcon#flushed, iclass 22, count 2 2006.257.16:19:12.31#ibcon#about to write, iclass 22, count 2 2006.257.16:19:12.31#ibcon#wrote, iclass 22, count 2 2006.257.16:19:12.31#ibcon#about to read 3, iclass 22, count 2 2006.257.16:19:12.34#ibcon#read 3, iclass 22, count 2 2006.257.16:19:12.34#ibcon#about to read 4, iclass 22, count 2 2006.257.16:19:12.34#ibcon#read 4, iclass 22, count 2 2006.257.16:19:12.34#ibcon#about to read 5, iclass 22, count 2 2006.257.16:19:12.34#ibcon#read 5, iclass 22, count 2 2006.257.16:19:12.34#ibcon#about to read 6, iclass 22, count 2 2006.257.16:19:12.34#ibcon#read 6, iclass 22, count 2 2006.257.16:19:12.34#ibcon#end of sib2, iclass 22, count 2 2006.257.16:19:12.34#ibcon#*after write, iclass 22, count 2 2006.257.16:19:12.34#ibcon#*before return 0, iclass 22, count 2 2006.257.16:19:12.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:12.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:12.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.16:19:12.34#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:12.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:12.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:12.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:12.46#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:19:12.46#ibcon#first serial, iclass 22, count 0 2006.257.16:19:12.46#ibcon#enter sib2, iclass 22, count 0 2006.257.16:19:12.46#ibcon#flushed, iclass 22, count 0 2006.257.16:19:12.46#ibcon#about to write, iclass 22, count 0 2006.257.16:19:12.46#ibcon#wrote, iclass 22, count 0 2006.257.16:19:12.46#ibcon#about to read 3, iclass 22, count 0 2006.257.16:19:12.48#ibcon#read 3, iclass 22, count 0 2006.257.16:19:12.48#ibcon#about to read 4, iclass 22, count 0 2006.257.16:19:12.48#ibcon#read 4, iclass 22, count 0 2006.257.16:19:12.48#ibcon#about to read 5, iclass 22, count 0 2006.257.16:19:12.48#ibcon#read 5, iclass 22, count 0 2006.257.16:19:12.48#ibcon#about to read 6, iclass 22, count 0 2006.257.16:19:12.48#ibcon#read 6, iclass 22, count 0 2006.257.16:19:12.48#ibcon#end of sib2, iclass 22, count 0 2006.257.16:19:12.48#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:19:12.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:19:12.48#ibcon#[25=USB\r\n] 2006.257.16:19:12.48#ibcon#*before write, iclass 22, count 0 2006.257.16:19:12.48#ibcon#enter sib2, iclass 22, count 0 2006.257.16:19:12.48#ibcon#flushed, iclass 22, count 0 2006.257.16:19:12.48#ibcon#about to write, iclass 22, count 0 2006.257.16:19:12.48#ibcon#wrote, iclass 22, count 0 2006.257.16:19:12.48#ibcon#about to read 3, iclass 22, count 0 2006.257.16:19:12.51#ibcon#read 3, iclass 22, count 0 2006.257.16:19:12.51#ibcon#about to read 4, iclass 22, count 0 2006.257.16:19:12.51#ibcon#read 4, iclass 22, count 0 2006.257.16:19:12.51#ibcon#about to read 5, iclass 22, count 0 2006.257.16:19:12.51#ibcon#read 5, iclass 22, count 0 2006.257.16:19:12.51#ibcon#about to read 6, iclass 22, count 0 2006.257.16:19:12.51#ibcon#read 6, iclass 22, count 0 2006.257.16:19:12.51#ibcon#end of sib2, iclass 22, count 0 2006.257.16:19:12.51#ibcon#*after write, iclass 22, count 0 2006.257.16:19:12.51#ibcon#*before return 0, iclass 22, count 0 2006.257.16:19:12.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:12.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:12.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:19:12.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:19:12.51$vck44/valo=4,624.99 2006.257.16:19:12.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.16:19:12.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.16:19:12.51#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:12.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:12.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:12.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:12.51#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:19:12.51#ibcon#first serial, iclass 24, count 0 2006.257.16:19:12.51#ibcon#enter sib2, iclass 24, count 0 2006.257.16:19:12.51#ibcon#flushed, iclass 24, count 0 2006.257.16:19:12.51#ibcon#about to write, iclass 24, count 0 2006.257.16:19:12.51#ibcon#wrote, iclass 24, count 0 2006.257.16:19:12.51#ibcon#about to read 3, iclass 24, count 0 2006.257.16:19:12.53#ibcon#read 3, iclass 24, count 0 2006.257.16:19:12.53#ibcon#about to read 4, iclass 24, count 0 2006.257.16:19:12.53#ibcon#read 4, iclass 24, count 0 2006.257.16:19:12.53#ibcon#about to read 5, iclass 24, count 0 2006.257.16:19:12.53#ibcon#read 5, iclass 24, count 0 2006.257.16:19:12.53#ibcon#about to read 6, iclass 24, count 0 2006.257.16:19:12.53#ibcon#read 6, iclass 24, count 0 2006.257.16:19:12.53#ibcon#end of sib2, iclass 24, count 0 2006.257.16:19:12.53#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:19:12.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:19:12.53#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.16:19:12.53#ibcon#*before write, iclass 24, count 0 2006.257.16:19:12.53#ibcon#enter sib2, iclass 24, count 0 2006.257.16:19:12.53#ibcon#flushed, iclass 24, count 0 2006.257.16:19:12.53#ibcon#about to write, iclass 24, count 0 2006.257.16:19:12.53#ibcon#wrote, iclass 24, count 0 2006.257.16:19:12.53#ibcon#about to read 3, iclass 24, count 0 2006.257.16:19:12.57#ibcon#read 3, iclass 24, count 0 2006.257.16:19:12.57#ibcon#about to read 4, iclass 24, count 0 2006.257.16:19:12.57#ibcon#read 4, iclass 24, count 0 2006.257.16:19:12.57#ibcon#about to read 5, iclass 24, count 0 2006.257.16:19:12.57#ibcon#read 5, iclass 24, count 0 2006.257.16:19:12.57#ibcon#about to read 6, iclass 24, count 0 2006.257.16:19:12.57#ibcon#read 6, iclass 24, count 0 2006.257.16:19:12.57#ibcon#end of sib2, iclass 24, count 0 2006.257.16:19:12.57#ibcon#*after write, iclass 24, count 0 2006.257.16:19:12.57#ibcon#*before return 0, iclass 24, count 0 2006.257.16:19:12.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:12.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:12.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:19:12.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:19:12.57$vck44/va=4,7 2006.257.16:19:12.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.16:19:12.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.16:19:12.57#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:12.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:12.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:12.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:12.63#ibcon#enter wrdev, iclass 26, count 2 2006.257.16:19:12.63#ibcon#first serial, iclass 26, count 2 2006.257.16:19:12.63#ibcon#enter sib2, iclass 26, count 2 2006.257.16:19:12.63#ibcon#flushed, iclass 26, count 2 2006.257.16:19:12.63#ibcon#about to write, iclass 26, count 2 2006.257.16:19:12.63#ibcon#wrote, iclass 26, count 2 2006.257.16:19:12.63#ibcon#about to read 3, iclass 26, count 2 2006.257.16:19:12.65#ibcon#read 3, iclass 26, count 2 2006.257.16:19:12.65#ibcon#about to read 4, iclass 26, count 2 2006.257.16:19:12.65#ibcon#read 4, iclass 26, count 2 2006.257.16:19:12.65#ibcon#about to read 5, iclass 26, count 2 2006.257.16:19:12.65#ibcon#read 5, iclass 26, count 2 2006.257.16:19:12.65#ibcon#about to read 6, iclass 26, count 2 2006.257.16:19:12.65#ibcon#read 6, iclass 26, count 2 2006.257.16:19:12.65#ibcon#end of sib2, iclass 26, count 2 2006.257.16:19:12.65#ibcon#*mode == 0, iclass 26, count 2 2006.257.16:19:12.65#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.16:19:12.65#ibcon#[25=AT04-07\r\n] 2006.257.16:19:12.65#ibcon#*before write, iclass 26, count 2 2006.257.16:19:12.65#ibcon#enter sib2, iclass 26, count 2 2006.257.16:19:12.65#ibcon#flushed, iclass 26, count 2 2006.257.16:19:12.65#ibcon#about to write, iclass 26, count 2 2006.257.16:19:12.65#ibcon#wrote, iclass 26, count 2 2006.257.16:19:12.65#ibcon#about to read 3, iclass 26, count 2 2006.257.16:19:12.68#ibcon#read 3, iclass 26, count 2 2006.257.16:19:12.68#ibcon#about to read 4, iclass 26, count 2 2006.257.16:19:12.68#ibcon#read 4, iclass 26, count 2 2006.257.16:19:12.68#ibcon#about to read 5, iclass 26, count 2 2006.257.16:19:12.68#ibcon#read 5, iclass 26, count 2 2006.257.16:19:12.68#ibcon#about to read 6, iclass 26, count 2 2006.257.16:19:12.68#ibcon#read 6, iclass 26, count 2 2006.257.16:19:12.68#ibcon#end of sib2, iclass 26, count 2 2006.257.16:19:12.68#ibcon#*after write, iclass 26, count 2 2006.257.16:19:12.68#ibcon#*before return 0, iclass 26, count 2 2006.257.16:19:12.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:12.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:12.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.16:19:12.68#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:12.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:12.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:12.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:12.80#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:19:12.80#ibcon#first serial, iclass 26, count 0 2006.257.16:19:12.80#ibcon#enter sib2, iclass 26, count 0 2006.257.16:19:12.80#ibcon#flushed, iclass 26, count 0 2006.257.16:19:12.80#ibcon#about to write, iclass 26, count 0 2006.257.16:19:12.80#ibcon#wrote, iclass 26, count 0 2006.257.16:19:12.80#ibcon#about to read 3, iclass 26, count 0 2006.257.16:19:12.82#ibcon#read 3, iclass 26, count 0 2006.257.16:19:12.82#ibcon#about to read 4, iclass 26, count 0 2006.257.16:19:12.82#ibcon#read 4, iclass 26, count 0 2006.257.16:19:12.82#ibcon#about to read 5, iclass 26, count 0 2006.257.16:19:12.82#ibcon#read 5, iclass 26, count 0 2006.257.16:19:12.82#ibcon#about to read 6, iclass 26, count 0 2006.257.16:19:12.82#ibcon#read 6, iclass 26, count 0 2006.257.16:19:12.82#ibcon#end of sib2, iclass 26, count 0 2006.257.16:19:12.82#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:19:12.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:19:12.82#ibcon#[25=USB\r\n] 2006.257.16:19:12.82#ibcon#*before write, iclass 26, count 0 2006.257.16:19:12.82#ibcon#enter sib2, iclass 26, count 0 2006.257.16:19:12.82#ibcon#flushed, iclass 26, count 0 2006.257.16:19:12.82#ibcon#about to write, iclass 26, count 0 2006.257.16:19:12.82#ibcon#wrote, iclass 26, count 0 2006.257.16:19:12.82#ibcon#about to read 3, iclass 26, count 0 2006.257.16:19:12.85#ibcon#read 3, iclass 26, count 0 2006.257.16:19:12.85#ibcon#about to read 4, iclass 26, count 0 2006.257.16:19:12.85#ibcon#read 4, iclass 26, count 0 2006.257.16:19:12.85#ibcon#about to read 5, iclass 26, count 0 2006.257.16:19:12.85#ibcon#read 5, iclass 26, count 0 2006.257.16:19:12.85#ibcon#about to read 6, iclass 26, count 0 2006.257.16:19:12.85#ibcon#read 6, iclass 26, count 0 2006.257.16:19:12.85#ibcon#end of sib2, iclass 26, count 0 2006.257.16:19:12.85#ibcon#*after write, iclass 26, count 0 2006.257.16:19:12.85#ibcon#*before return 0, iclass 26, count 0 2006.257.16:19:12.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:12.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:12.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:19:12.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:19:12.85$vck44/valo=5,734.99 2006.257.16:19:12.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.16:19:12.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.16:19:12.85#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:12.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:12.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:12.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:12.85#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:19:12.85#ibcon#first serial, iclass 28, count 0 2006.257.16:19:12.85#ibcon#enter sib2, iclass 28, count 0 2006.257.16:19:12.85#ibcon#flushed, iclass 28, count 0 2006.257.16:19:12.85#ibcon#about to write, iclass 28, count 0 2006.257.16:19:12.85#ibcon#wrote, iclass 28, count 0 2006.257.16:19:12.85#ibcon#about to read 3, iclass 28, count 0 2006.257.16:19:12.87#ibcon#read 3, iclass 28, count 0 2006.257.16:19:12.87#ibcon#about to read 4, iclass 28, count 0 2006.257.16:19:12.87#ibcon#read 4, iclass 28, count 0 2006.257.16:19:12.87#ibcon#about to read 5, iclass 28, count 0 2006.257.16:19:12.87#ibcon#read 5, iclass 28, count 0 2006.257.16:19:12.87#ibcon#about to read 6, iclass 28, count 0 2006.257.16:19:12.87#ibcon#read 6, iclass 28, count 0 2006.257.16:19:12.87#ibcon#end of sib2, iclass 28, count 0 2006.257.16:19:12.87#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:19:12.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:19:12.87#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.16:19:12.87#ibcon#*before write, iclass 28, count 0 2006.257.16:19:12.87#ibcon#enter sib2, iclass 28, count 0 2006.257.16:19:12.87#ibcon#flushed, iclass 28, count 0 2006.257.16:19:12.87#ibcon#about to write, iclass 28, count 0 2006.257.16:19:12.87#ibcon#wrote, iclass 28, count 0 2006.257.16:19:12.87#ibcon#about to read 3, iclass 28, count 0 2006.257.16:19:12.91#ibcon#read 3, iclass 28, count 0 2006.257.16:19:12.91#ibcon#about to read 4, iclass 28, count 0 2006.257.16:19:12.91#ibcon#read 4, iclass 28, count 0 2006.257.16:19:12.91#ibcon#about to read 5, iclass 28, count 0 2006.257.16:19:12.91#ibcon#read 5, iclass 28, count 0 2006.257.16:19:12.91#ibcon#about to read 6, iclass 28, count 0 2006.257.16:19:12.91#ibcon#read 6, iclass 28, count 0 2006.257.16:19:12.91#ibcon#end of sib2, iclass 28, count 0 2006.257.16:19:12.91#ibcon#*after write, iclass 28, count 0 2006.257.16:19:12.91#ibcon#*before return 0, iclass 28, count 0 2006.257.16:19:12.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:12.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:12.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:19:12.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:19:12.91$vck44/va=5,4 2006.257.16:19:12.91#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.16:19:12.91#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.16:19:12.91#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:12.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:12.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:12.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:12.97#ibcon#enter wrdev, iclass 30, count 2 2006.257.16:19:12.97#ibcon#first serial, iclass 30, count 2 2006.257.16:19:12.97#ibcon#enter sib2, iclass 30, count 2 2006.257.16:19:12.97#ibcon#flushed, iclass 30, count 2 2006.257.16:19:12.97#ibcon#about to write, iclass 30, count 2 2006.257.16:19:12.97#ibcon#wrote, iclass 30, count 2 2006.257.16:19:12.97#ibcon#about to read 3, iclass 30, count 2 2006.257.16:19:12.99#ibcon#read 3, iclass 30, count 2 2006.257.16:19:12.99#ibcon#about to read 4, iclass 30, count 2 2006.257.16:19:12.99#ibcon#read 4, iclass 30, count 2 2006.257.16:19:12.99#ibcon#about to read 5, iclass 30, count 2 2006.257.16:19:12.99#ibcon#read 5, iclass 30, count 2 2006.257.16:19:12.99#ibcon#about to read 6, iclass 30, count 2 2006.257.16:19:12.99#ibcon#read 6, iclass 30, count 2 2006.257.16:19:12.99#ibcon#end of sib2, iclass 30, count 2 2006.257.16:19:12.99#ibcon#*mode == 0, iclass 30, count 2 2006.257.16:19:12.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.16:19:12.99#ibcon#[25=AT05-04\r\n] 2006.257.16:19:12.99#ibcon#*before write, iclass 30, count 2 2006.257.16:19:12.99#ibcon#enter sib2, iclass 30, count 2 2006.257.16:19:12.99#ibcon#flushed, iclass 30, count 2 2006.257.16:19:12.99#ibcon#about to write, iclass 30, count 2 2006.257.16:19:12.99#ibcon#wrote, iclass 30, count 2 2006.257.16:19:12.99#ibcon#about to read 3, iclass 30, count 2 2006.257.16:19:13.02#ibcon#read 3, iclass 30, count 2 2006.257.16:19:13.02#ibcon#about to read 4, iclass 30, count 2 2006.257.16:19:13.02#ibcon#read 4, iclass 30, count 2 2006.257.16:19:13.02#ibcon#about to read 5, iclass 30, count 2 2006.257.16:19:13.02#ibcon#read 5, iclass 30, count 2 2006.257.16:19:13.02#ibcon#about to read 6, iclass 30, count 2 2006.257.16:19:13.02#ibcon#read 6, iclass 30, count 2 2006.257.16:19:13.02#ibcon#end of sib2, iclass 30, count 2 2006.257.16:19:13.02#ibcon#*after write, iclass 30, count 2 2006.257.16:19:13.02#ibcon#*before return 0, iclass 30, count 2 2006.257.16:19:13.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:13.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:13.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.16:19:13.02#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:13.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:13.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:13.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:13.14#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:19:13.14#ibcon#first serial, iclass 30, count 0 2006.257.16:19:13.14#ibcon#enter sib2, iclass 30, count 0 2006.257.16:19:13.14#ibcon#flushed, iclass 30, count 0 2006.257.16:19:13.14#ibcon#about to write, iclass 30, count 0 2006.257.16:19:13.14#ibcon#wrote, iclass 30, count 0 2006.257.16:19:13.14#ibcon#about to read 3, iclass 30, count 0 2006.257.16:19:13.16#ibcon#read 3, iclass 30, count 0 2006.257.16:19:13.16#ibcon#about to read 4, iclass 30, count 0 2006.257.16:19:13.16#ibcon#read 4, iclass 30, count 0 2006.257.16:19:13.16#ibcon#about to read 5, iclass 30, count 0 2006.257.16:19:13.16#ibcon#read 5, iclass 30, count 0 2006.257.16:19:13.16#ibcon#about to read 6, iclass 30, count 0 2006.257.16:19:13.16#ibcon#read 6, iclass 30, count 0 2006.257.16:19:13.16#ibcon#end of sib2, iclass 30, count 0 2006.257.16:19:13.16#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:19:13.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:19:13.16#ibcon#[25=USB\r\n] 2006.257.16:19:13.16#ibcon#*before write, iclass 30, count 0 2006.257.16:19:13.16#ibcon#enter sib2, iclass 30, count 0 2006.257.16:19:13.16#ibcon#flushed, iclass 30, count 0 2006.257.16:19:13.16#ibcon#about to write, iclass 30, count 0 2006.257.16:19:13.16#ibcon#wrote, iclass 30, count 0 2006.257.16:19:13.16#ibcon#about to read 3, iclass 30, count 0 2006.257.16:19:13.19#ibcon#read 3, iclass 30, count 0 2006.257.16:19:13.19#ibcon#about to read 4, iclass 30, count 0 2006.257.16:19:13.19#ibcon#read 4, iclass 30, count 0 2006.257.16:19:13.19#ibcon#about to read 5, iclass 30, count 0 2006.257.16:19:13.19#ibcon#read 5, iclass 30, count 0 2006.257.16:19:13.19#ibcon#about to read 6, iclass 30, count 0 2006.257.16:19:13.19#ibcon#read 6, iclass 30, count 0 2006.257.16:19:13.19#ibcon#end of sib2, iclass 30, count 0 2006.257.16:19:13.19#ibcon#*after write, iclass 30, count 0 2006.257.16:19:13.19#ibcon#*before return 0, iclass 30, count 0 2006.257.16:19:13.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:13.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:13.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:19:13.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:19:13.19$vck44/valo=6,814.99 2006.257.16:19:13.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.16:19:13.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.16:19:13.19#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:13.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:13.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:13.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:13.19#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:19:13.19#ibcon#first serial, iclass 32, count 0 2006.257.16:19:13.19#ibcon#enter sib2, iclass 32, count 0 2006.257.16:19:13.19#ibcon#flushed, iclass 32, count 0 2006.257.16:19:13.19#ibcon#about to write, iclass 32, count 0 2006.257.16:19:13.19#ibcon#wrote, iclass 32, count 0 2006.257.16:19:13.19#ibcon#about to read 3, iclass 32, count 0 2006.257.16:19:13.21#ibcon#read 3, iclass 32, count 0 2006.257.16:19:13.21#ibcon#about to read 4, iclass 32, count 0 2006.257.16:19:13.21#ibcon#read 4, iclass 32, count 0 2006.257.16:19:13.21#ibcon#about to read 5, iclass 32, count 0 2006.257.16:19:13.21#ibcon#read 5, iclass 32, count 0 2006.257.16:19:13.21#ibcon#about to read 6, iclass 32, count 0 2006.257.16:19:13.21#ibcon#read 6, iclass 32, count 0 2006.257.16:19:13.21#ibcon#end of sib2, iclass 32, count 0 2006.257.16:19:13.21#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:19:13.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:19:13.21#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.16:19:13.21#ibcon#*before write, iclass 32, count 0 2006.257.16:19:13.21#ibcon#enter sib2, iclass 32, count 0 2006.257.16:19:13.21#ibcon#flushed, iclass 32, count 0 2006.257.16:19:13.21#ibcon#about to write, iclass 32, count 0 2006.257.16:19:13.21#ibcon#wrote, iclass 32, count 0 2006.257.16:19:13.21#ibcon#about to read 3, iclass 32, count 0 2006.257.16:19:13.25#ibcon#read 3, iclass 32, count 0 2006.257.16:19:13.25#ibcon#about to read 4, iclass 32, count 0 2006.257.16:19:13.25#ibcon#read 4, iclass 32, count 0 2006.257.16:19:13.25#ibcon#about to read 5, iclass 32, count 0 2006.257.16:19:13.25#ibcon#read 5, iclass 32, count 0 2006.257.16:19:13.25#ibcon#about to read 6, iclass 32, count 0 2006.257.16:19:13.25#ibcon#read 6, iclass 32, count 0 2006.257.16:19:13.25#ibcon#end of sib2, iclass 32, count 0 2006.257.16:19:13.25#ibcon#*after write, iclass 32, count 0 2006.257.16:19:13.25#ibcon#*before return 0, iclass 32, count 0 2006.257.16:19:13.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:13.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:13.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:19:13.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:19:13.25$vck44/va=6,4 2006.257.16:19:13.25#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.16:19:13.25#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.16:19:13.25#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:13.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:13.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:13.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:13.31#ibcon#enter wrdev, iclass 34, count 2 2006.257.16:19:13.31#ibcon#first serial, iclass 34, count 2 2006.257.16:19:13.31#ibcon#enter sib2, iclass 34, count 2 2006.257.16:19:13.31#ibcon#flushed, iclass 34, count 2 2006.257.16:19:13.31#ibcon#about to write, iclass 34, count 2 2006.257.16:19:13.31#ibcon#wrote, iclass 34, count 2 2006.257.16:19:13.31#ibcon#about to read 3, iclass 34, count 2 2006.257.16:19:13.33#ibcon#read 3, iclass 34, count 2 2006.257.16:19:13.33#ibcon#about to read 4, iclass 34, count 2 2006.257.16:19:13.33#ibcon#read 4, iclass 34, count 2 2006.257.16:19:13.33#ibcon#about to read 5, iclass 34, count 2 2006.257.16:19:13.33#ibcon#read 5, iclass 34, count 2 2006.257.16:19:13.33#ibcon#about to read 6, iclass 34, count 2 2006.257.16:19:13.33#ibcon#read 6, iclass 34, count 2 2006.257.16:19:13.33#ibcon#end of sib2, iclass 34, count 2 2006.257.16:19:13.33#ibcon#*mode == 0, iclass 34, count 2 2006.257.16:19:13.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.16:19:13.33#ibcon#[25=AT06-04\r\n] 2006.257.16:19:13.33#ibcon#*before write, iclass 34, count 2 2006.257.16:19:13.33#ibcon#enter sib2, iclass 34, count 2 2006.257.16:19:13.33#ibcon#flushed, iclass 34, count 2 2006.257.16:19:13.33#ibcon#about to write, iclass 34, count 2 2006.257.16:19:13.33#ibcon#wrote, iclass 34, count 2 2006.257.16:19:13.33#ibcon#about to read 3, iclass 34, count 2 2006.257.16:19:13.36#ibcon#read 3, iclass 34, count 2 2006.257.16:19:13.36#ibcon#about to read 4, iclass 34, count 2 2006.257.16:19:13.36#ibcon#read 4, iclass 34, count 2 2006.257.16:19:13.36#ibcon#about to read 5, iclass 34, count 2 2006.257.16:19:13.36#ibcon#read 5, iclass 34, count 2 2006.257.16:19:13.36#ibcon#about to read 6, iclass 34, count 2 2006.257.16:19:13.36#ibcon#read 6, iclass 34, count 2 2006.257.16:19:13.36#ibcon#end of sib2, iclass 34, count 2 2006.257.16:19:13.36#ibcon#*after write, iclass 34, count 2 2006.257.16:19:13.36#ibcon#*before return 0, iclass 34, count 2 2006.257.16:19:13.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:13.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:13.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.16:19:13.36#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:13.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:13.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:13.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:13.48#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:19:13.48#ibcon#first serial, iclass 34, count 0 2006.257.16:19:13.48#ibcon#enter sib2, iclass 34, count 0 2006.257.16:19:13.48#ibcon#flushed, iclass 34, count 0 2006.257.16:19:13.48#ibcon#about to write, iclass 34, count 0 2006.257.16:19:13.48#ibcon#wrote, iclass 34, count 0 2006.257.16:19:13.48#ibcon#about to read 3, iclass 34, count 0 2006.257.16:19:13.50#ibcon#read 3, iclass 34, count 0 2006.257.16:19:13.50#ibcon#about to read 4, iclass 34, count 0 2006.257.16:19:13.50#ibcon#read 4, iclass 34, count 0 2006.257.16:19:13.50#ibcon#about to read 5, iclass 34, count 0 2006.257.16:19:13.50#ibcon#read 5, iclass 34, count 0 2006.257.16:19:13.50#ibcon#about to read 6, iclass 34, count 0 2006.257.16:19:13.50#ibcon#read 6, iclass 34, count 0 2006.257.16:19:13.50#ibcon#end of sib2, iclass 34, count 0 2006.257.16:19:13.50#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:19:13.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:19:13.50#ibcon#[25=USB\r\n] 2006.257.16:19:13.50#ibcon#*before write, iclass 34, count 0 2006.257.16:19:13.50#ibcon#enter sib2, iclass 34, count 0 2006.257.16:19:13.50#ibcon#flushed, iclass 34, count 0 2006.257.16:19:13.50#ibcon#about to write, iclass 34, count 0 2006.257.16:19:13.50#ibcon#wrote, iclass 34, count 0 2006.257.16:19:13.50#ibcon#about to read 3, iclass 34, count 0 2006.257.16:19:13.53#ibcon#read 3, iclass 34, count 0 2006.257.16:19:13.53#ibcon#about to read 4, iclass 34, count 0 2006.257.16:19:13.53#ibcon#read 4, iclass 34, count 0 2006.257.16:19:13.53#ibcon#about to read 5, iclass 34, count 0 2006.257.16:19:13.53#ibcon#read 5, iclass 34, count 0 2006.257.16:19:13.53#ibcon#about to read 6, iclass 34, count 0 2006.257.16:19:13.53#ibcon#read 6, iclass 34, count 0 2006.257.16:19:13.53#ibcon#end of sib2, iclass 34, count 0 2006.257.16:19:13.53#ibcon#*after write, iclass 34, count 0 2006.257.16:19:13.53#ibcon#*before return 0, iclass 34, count 0 2006.257.16:19:13.53#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:13.53#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:13.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:19:13.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:19:13.53$vck44/valo=7,864.99 2006.257.16:19:13.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.16:19:13.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.16:19:13.53#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:13.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:19:13.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:19:13.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:19:13.53#ibcon#enter wrdev, iclass 37, count 0 2006.257.16:19:13.53#ibcon#first serial, iclass 37, count 0 2006.257.16:19:13.53#ibcon#enter sib2, iclass 37, count 0 2006.257.16:19:13.53#ibcon#flushed, iclass 37, count 0 2006.257.16:19:13.53#ibcon#about to write, iclass 37, count 0 2006.257.16:19:13.53#ibcon#wrote, iclass 37, count 0 2006.257.16:19:13.53#ibcon#about to read 3, iclass 37, count 0 2006.257.16:19:13.55#ibcon#read 3, iclass 37, count 0 2006.257.16:19:13.55#ibcon#about to read 4, iclass 37, count 0 2006.257.16:19:13.55#ibcon#read 4, iclass 37, count 0 2006.257.16:19:13.55#ibcon#about to read 5, iclass 37, count 0 2006.257.16:19:13.55#ibcon#read 5, iclass 37, count 0 2006.257.16:19:13.55#ibcon#about to read 6, iclass 37, count 0 2006.257.16:19:13.55#ibcon#read 6, iclass 37, count 0 2006.257.16:19:13.55#ibcon#end of sib2, iclass 37, count 0 2006.257.16:19:13.55#ibcon#*mode == 0, iclass 37, count 0 2006.257.16:19:13.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.16:19:13.55#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.16:19:13.55#ibcon#*before write, iclass 37, count 0 2006.257.16:19:13.55#ibcon#enter sib2, iclass 37, count 0 2006.257.16:19:13.55#ibcon#flushed, iclass 37, count 0 2006.257.16:19:13.55#ibcon#about to write, iclass 37, count 0 2006.257.16:19:13.55#ibcon#wrote, iclass 37, count 0 2006.257.16:19:13.55#ibcon#about to read 3, iclass 37, count 0 2006.257.16:19:13.56#abcon#<5=/14 1.2 3.2 17.21 971014.1\r\n> 2006.257.16:19:13.58#abcon#{5=INTERFACE CLEAR} 2006.257.16:19:13.59#ibcon#read 3, iclass 37, count 0 2006.257.16:19:13.59#ibcon#about to read 4, iclass 37, count 0 2006.257.16:19:13.59#ibcon#read 4, iclass 37, count 0 2006.257.16:19:13.59#ibcon#about to read 5, iclass 37, count 0 2006.257.16:19:13.59#ibcon#read 5, iclass 37, count 0 2006.257.16:19:13.59#ibcon#about to read 6, iclass 37, count 0 2006.257.16:19:13.59#ibcon#read 6, iclass 37, count 0 2006.257.16:19:13.59#ibcon#end of sib2, iclass 37, count 0 2006.257.16:19:13.59#ibcon#*after write, iclass 37, count 0 2006.257.16:19:13.59#ibcon#*before return 0, iclass 37, count 0 2006.257.16:19:13.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:19:13.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:19:13.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.16:19:13.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.16:19:13.59$vck44/va=7,4 2006.257.16:19:13.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.16:19:13.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.16:19:13.59#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:13.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:19:13.64#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:19:13.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:19:13.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:19:13.65#ibcon#enter wrdev, iclass 3, count 2 2006.257.16:19:13.65#ibcon#first serial, iclass 3, count 2 2006.257.16:19:13.65#ibcon#enter sib2, iclass 3, count 2 2006.257.16:19:13.65#ibcon#flushed, iclass 3, count 2 2006.257.16:19:13.65#ibcon#about to write, iclass 3, count 2 2006.257.16:19:13.65#ibcon#wrote, iclass 3, count 2 2006.257.16:19:13.65#ibcon#about to read 3, iclass 3, count 2 2006.257.16:19:13.67#ibcon#read 3, iclass 3, count 2 2006.257.16:19:13.67#ibcon#about to read 4, iclass 3, count 2 2006.257.16:19:13.67#ibcon#read 4, iclass 3, count 2 2006.257.16:19:13.67#ibcon#about to read 5, iclass 3, count 2 2006.257.16:19:13.67#ibcon#read 5, iclass 3, count 2 2006.257.16:19:13.67#ibcon#about to read 6, iclass 3, count 2 2006.257.16:19:13.67#ibcon#read 6, iclass 3, count 2 2006.257.16:19:13.67#ibcon#end of sib2, iclass 3, count 2 2006.257.16:19:13.67#ibcon#*mode == 0, iclass 3, count 2 2006.257.16:19:13.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.16:19:13.67#ibcon#[25=AT07-04\r\n] 2006.257.16:19:13.67#ibcon#*before write, iclass 3, count 2 2006.257.16:19:13.67#ibcon#enter sib2, iclass 3, count 2 2006.257.16:19:13.67#ibcon#flushed, iclass 3, count 2 2006.257.16:19:13.67#ibcon#about to write, iclass 3, count 2 2006.257.16:19:13.67#ibcon#wrote, iclass 3, count 2 2006.257.16:19:13.67#ibcon#about to read 3, iclass 3, count 2 2006.257.16:19:13.70#ibcon#read 3, iclass 3, count 2 2006.257.16:19:13.70#ibcon#about to read 4, iclass 3, count 2 2006.257.16:19:13.70#ibcon#read 4, iclass 3, count 2 2006.257.16:19:13.70#ibcon#about to read 5, iclass 3, count 2 2006.257.16:19:13.70#ibcon#read 5, iclass 3, count 2 2006.257.16:19:13.70#ibcon#about to read 6, iclass 3, count 2 2006.257.16:19:13.70#ibcon#read 6, iclass 3, count 2 2006.257.16:19:13.70#ibcon#end of sib2, iclass 3, count 2 2006.257.16:19:13.70#ibcon#*after write, iclass 3, count 2 2006.257.16:19:13.70#ibcon#*before return 0, iclass 3, count 2 2006.257.16:19:13.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:19:13.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:19:13.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.16:19:13.70#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:13.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:19:13.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:19:13.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:19:13.82#ibcon#enter wrdev, iclass 3, count 0 2006.257.16:19:13.82#ibcon#first serial, iclass 3, count 0 2006.257.16:19:13.82#ibcon#enter sib2, iclass 3, count 0 2006.257.16:19:13.82#ibcon#flushed, iclass 3, count 0 2006.257.16:19:13.82#ibcon#about to write, iclass 3, count 0 2006.257.16:19:13.82#ibcon#wrote, iclass 3, count 0 2006.257.16:19:13.82#ibcon#about to read 3, iclass 3, count 0 2006.257.16:19:13.84#ibcon#read 3, iclass 3, count 0 2006.257.16:19:13.84#ibcon#about to read 4, iclass 3, count 0 2006.257.16:19:13.84#ibcon#read 4, iclass 3, count 0 2006.257.16:19:13.84#ibcon#about to read 5, iclass 3, count 0 2006.257.16:19:13.84#ibcon#read 5, iclass 3, count 0 2006.257.16:19:13.84#ibcon#about to read 6, iclass 3, count 0 2006.257.16:19:13.84#ibcon#read 6, iclass 3, count 0 2006.257.16:19:13.84#ibcon#end of sib2, iclass 3, count 0 2006.257.16:19:13.84#ibcon#*mode == 0, iclass 3, count 0 2006.257.16:19:13.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.16:19:13.84#ibcon#[25=USB\r\n] 2006.257.16:19:13.84#ibcon#*before write, iclass 3, count 0 2006.257.16:19:13.84#ibcon#enter sib2, iclass 3, count 0 2006.257.16:19:13.84#ibcon#flushed, iclass 3, count 0 2006.257.16:19:13.84#ibcon#about to write, iclass 3, count 0 2006.257.16:19:13.84#ibcon#wrote, iclass 3, count 0 2006.257.16:19:13.84#ibcon#about to read 3, iclass 3, count 0 2006.257.16:19:13.87#ibcon#read 3, iclass 3, count 0 2006.257.16:19:13.87#ibcon#about to read 4, iclass 3, count 0 2006.257.16:19:13.87#ibcon#read 4, iclass 3, count 0 2006.257.16:19:13.87#ibcon#about to read 5, iclass 3, count 0 2006.257.16:19:13.87#ibcon#read 5, iclass 3, count 0 2006.257.16:19:13.87#ibcon#about to read 6, iclass 3, count 0 2006.257.16:19:13.87#ibcon#read 6, iclass 3, count 0 2006.257.16:19:13.87#ibcon#end of sib2, iclass 3, count 0 2006.257.16:19:13.87#ibcon#*after write, iclass 3, count 0 2006.257.16:19:13.87#ibcon#*before return 0, iclass 3, count 0 2006.257.16:19:13.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:19:13.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:19:13.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.16:19:13.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.16:19:13.87$vck44/valo=8,884.99 2006.257.16:19:13.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.16:19:13.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.16:19:13.87#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:13.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:13.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:13.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:13.87#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:19:13.87#ibcon#first serial, iclass 6, count 0 2006.257.16:19:13.87#ibcon#enter sib2, iclass 6, count 0 2006.257.16:19:13.87#ibcon#flushed, iclass 6, count 0 2006.257.16:19:13.87#ibcon#about to write, iclass 6, count 0 2006.257.16:19:13.87#ibcon#wrote, iclass 6, count 0 2006.257.16:19:13.87#ibcon#about to read 3, iclass 6, count 0 2006.257.16:19:13.89#ibcon#read 3, iclass 6, count 0 2006.257.16:19:13.89#ibcon#about to read 4, iclass 6, count 0 2006.257.16:19:13.89#ibcon#read 4, iclass 6, count 0 2006.257.16:19:13.89#ibcon#about to read 5, iclass 6, count 0 2006.257.16:19:13.89#ibcon#read 5, iclass 6, count 0 2006.257.16:19:13.89#ibcon#about to read 6, iclass 6, count 0 2006.257.16:19:13.89#ibcon#read 6, iclass 6, count 0 2006.257.16:19:13.89#ibcon#end of sib2, iclass 6, count 0 2006.257.16:19:13.89#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:19:13.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:19:13.89#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.16:19:13.89#ibcon#*before write, iclass 6, count 0 2006.257.16:19:13.89#ibcon#enter sib2, iclass 6, count 0 2006.257.16:19:13.89#ibcon#flushed, iclass 6, count 0 2006.257.16:19:13.89#ibcon#about to write, iclass 6, count 0 2006.257.16:19:13.89#ibcon#wrote, iclass 6, count 0 2006.257.16:19:13.89#ibcon#about to read 3, iclass 6, count 0 2006.257.16:19:13.93#ibcon#read 3, iclass 6, count 0 2006.257.16:19:13.93#ibcon#about to read 4, iclass 6, count 0 2006.257.16:19:13.93#ibcon#read 4, iclass 6, count 0 2006.257.16:19:13.93#ibcon#about to read 5, iclass 6, count 0 2006.257.16:19:13.93#ibcon#read 5, iclass 6, count 0 2006.257.16:19:13.93#ibcon#about to read 6, iclass 6, count 0 2006.257.16:19:13.93#ibcon#read 6, iclass 6, count 0 2006.257.16:19:13.93#ibcon#end of sib2, iclass 6, count 0 2006.257.16:19:13.93#ibcon#*after write, iclass 6, count 0 2006.257.16:19:13.93#ibcon#*before return 0, iclass 6, count 0 2006.257.16:19:13.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:13.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:13.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:19:13.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:19:13.93$vck44/va=8,4 2006.257.16:19:13.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.16:19:13.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.16:19:13.93#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:13.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:19:13.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:19:13.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:19:13.99#ibcon#enter wrdev, iclass 10, count 2 2006.257.16:19:13.99#ibcon#first serial, iclass 10, count 2 2006.257.16:19:13.99#ibcon#enter sib2, iclass 10, count 2 2006.257.16:19:13.99#ibcon#flushed, iclass 10, count 2 2006.257.16:19:13.99#ibcon#about to write, iclass 10, count 2 2006.257.16:19:13.99#ibcon#wrote, iclass 10, count 2 2006.257.16:19:13.99#ibcon#about to read 3, iclass 10, count 2 2006.257.16:19:14.01#ibcon#read 3, iclass 10, count 2 2006.257.16:19:14.01#ibcon#about to read 4, iclass 10, count 2 2006.257.16:19:14.01#ibcon#read 4, iclass 10, count 2 2006.257.16:19:14.01#ibcon#about to read 5, iclass 10, count 2 2006.257.16:19:14.01#ibcon#read 5, iclass 10, count 2 2006.257.16:19:14.01#ibcon#about to read 6, iclass 10, count 2 2006.257.16:19:14.01#ibcon#read 6, iclass 10, count 2 2006.257.16:19:14.01#ibcon#end of sib2, iclass 10, count 2 2006.257.16:19:14.01#ibcon#*mode == 0, iclass 10, count 2 2006.257.16:19:14.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.16:19:14.01#ibcon#[25=AT08-04\r\n] 2006.257.16:19:14.01#ibcon#*before write, iclass 10, count 2 2006.257.16:19:14.01#ibcon#enter sib2, iclass 10, count 2 2006.257.16:19:14.01#ibcon#flushed, iclass 10, count 2 2006.257.16:19:14.01#ibcon#about to write, iclass 10, count 2 2006.257.16:19:14.01#ibcon#wrote, iclass 10, count 2 2006.257.16:19:14.01#ibcon#about to read 3, iclass 10, count 2 2006.257.16:19:14.04#ibcon#read 3, iclass 10, count 2 2006.257.16:19:14.04#ibcon#about to read 4, iclass 10, count 2 2006.257.16:19:14.04#ibcon#read 4, iclass 10, count 2 2006.257.16:19:14.04#ibcon#about to read 5, iclass 10, count 2 2006.257.16:19:14.04#ibcon#read 5, iclass 10, count 2 2006.257.16:19:14.04#ibcon#about to read 6, iclass 10, count 2 2006.257.16:19:14.04#ibcon#read 6, iclass 10, count 2 2006.257.16:19:14.04#ibcon#end of sib2, iclass 10, count 2 2006.257.16:19:14.04#ibcon#*after write, iclass 10, count 2 2006.257.16:19:14.04#ibcon#*before return 0, iclass 10, count 2 2006.257.16:19:14.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:19:14.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:19:14.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.16:19:14.04#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:14.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:19:14.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:19:14.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:19:14.16#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:19:14.16#ibcon#first serial, iclass 10, count 0 2006.257.16:19:14.16#ibcon#enter sib2, iclass 10, count 0 2006.257.16:19:14.16#ibcon#flushed, iclass 10, count 0 2006.257.16:19:14.16#ibcon#about to write, iclass 10, count 0 2006.257.16:19:14.16#ibcon#wrote, iclass 10, count 0 2006.257.16:19:14.16#ibcon#about to read 3, iclass 10, count 0 2006.257.16:19:14.18#ibcon#read 3, iclass 10, count 0 2006.257.16:19:14.18#ibcon#about to read 4, iclass 10, count 0 2006.257.16:19:14.18#ibcon#read 4, iclass 10, count 0 2006.257.16:19:14.18#ibcon#about to read 5, iclass 10, count 0 2006.257.16:19:14.18#ibcon#read 5, iclass 10, count 0 2006.257.16:19:14.18#ibcon#about to read 6, iclass 10, count 0 2006.257.16:19:14.18#ibcon#read 6, iclass 10, count 0 2006.257.16:19:14.18#ibcon#end of sib2, iclass 10, count 0 2006.257.16:19:14.18#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:19:14.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:19:14.18#ibcon#[25=USB\r\n] 2006.257.16:19:14.18#ibcon#*before write, iclass 10, count 0 2006.257.16:19:14.18#ibcon#enter sib2, iclass 10, count 0 2006.257.16:19:14.18#ibcon#flushed, iclass 10, count 0 2006.257.16:19:14.18#ibcon#about to write, iclass 10, count 0 2006.257.16:19:14.18#ibcon#wrote, iclass 10, count 0 2006.257.16:19:14.18#ibcon#about to read 3, iclass 10, count 0 2006.257.16:19:14.21#ibcon#read 3, iclass 10, count 0 2006.257.16:19:14.21#ibcon#about to read 4, iclass 10, count 0 2006.257.16:19:14.21#ibcon#read 4, iclass 10, count 0 2006.257.16:19:14.21#ibcon#about to read 5, iclass 10, count 0 2006.257.16:19:14.21#ibcon#read 5, iclass 10, count 0 2006.257.16:19:14.21#ibcon#about to read 6, iclass 10, count 0 2006.257.16:19:14.21#ibcon#read 6, iclass 10, count 0 2006.257.16:19:14.21#ibcon#end of sib2, iclass 10, count 0 2006.257.16:19:14.21#ibcon#*after write, iclass 10, count 0 2006.257.16:19:14.21#ibcon#*before return 0, iclass 10, count 0 2006.257.16:19:14.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:19:14.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:19:14.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:19:14.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:19:14.21$vck44/vblo=1,629.99 2006.257.16:19:14.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.16:19:14.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.16:19:14.21#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:14.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:14.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:14.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:14.21#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:19:14.21#ibcon#first serial, iclass 12, count 0 2006.257.16:19:14.21#ibcon#enter sib2, iclass 12, count 0 2006.257.16:19:14.21#ibcon#flushed, iclass 12, count 0 2006.257.16:19:14.21#ibcon#about to write, iclass 12, count 0 2006.257.16:19:14.21#ibcon#wrote, iclass 12, count 0 2006.257.16:19:14.21#ibcon#about to read 3, iclass 12, count 0 2006.257.16:19:14.23#ibcon#read 3, iclass 12, count 0 2006.257.16:19:14.23#ibcon#about to read 4, iclass 12, count 0 2006.257.16:19:14.23#ibcon#read 4, iclass 12, count 0 2006.257.16:19:14.23#ibcon#about to read 5, iclass 12, count 0 2006.257.16:19:14.23#ibcon#read 5, iclass 12, count 0 2006.257.16:19:14.23#ibcon#about to read 6, iclass 12, count 0 2006.257.16:19:14.23#ibcon#read 6, iclass 12, count 0 2006.257.16:19:14.23#ibcon#end of sib2, iclass 12, count 0 2006.257.16:19:14.23#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:19:14.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:19:14.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.16:19:14.23#ibcon#*before write, iclass 12, count 0 2006.257.16:19:14.23#ibcon#enter sib2, iclass 12, count 0 2006.257.16:19:14.23#ibcon#flushed, iclass 12, count 0 2006.257.16:19:14.23#ibcon#about to write, iclass 12, count 0 2006.257.16:19:14.23#ibcon#wrote, iclass 12, count 0 2006.257.16:19:14.23#ibcon#about to read 3, iclass 12, count 0 2006.257.16:19:14.27#ibcon#read 3, iclass 12, count 0 2006.257.16:19:14.27#ibcon#about to read 4, iclass 12, count 0 2006.257.16:19:14.27#ibcon#read 4, iclass 12, count 0 2006.257.16:19:14.27#ibcon#about to read 5, iclass 12, count 0 2006.257.16:19:14.27#ibcon#read 5, iclass 12, count 0 2006.257.16:19:14.27#ibcon#about to read 6, iclass 12, count 0 2006.257.16:19:14.27#ibcon#read 6, iclass 12, count 0 2006.257.16:19:14.27#ibcon#end of sib2, iclass 12, count 0 2006.257.16:19:14.27#ibcon#*after write, iclass 12, count 0 2006.257.16:19:14.27#ibcon#*before return 0, iclass 12, count 0 2006.257.16:19:14.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:14.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:19:14.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:19:14.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:19:14.27$vck44/vb=1,4 2006.257.16:19:14.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.16:19:14.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.16:19:14.27#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:14.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:14.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:14.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:14.27#ibcon#enter wrdev, iclass 14, count 2 2006.257.16:19:14.27#ibcon#first serial, iclass 14, count 2 2006.257.16:19:14.27#ibcon#enter sib2, iclass 14, count 2 2006.257.16:19:14.27#ibcon#flushed, iclass 14, count 2 2006.257.16:19:14.27#ibcon#about to write, iclass 14, count 2 2006.257.16:19:14.27#ibcon#wrote, iclass 14, count 2 2006.257.16:19:14.27#ibcon#about to read 3, iclass 14, count 2 2006.257.16:19:14.29#ibcon#read 3, iclass 14, count 2 2006.257.16:19:14.29#ibcon#about to read 4, iclass 14, count 2 2006.257.16:19:14.29#ibcon#read 4, iclass 14, count 2 2006.257.16:19:14.29#ibcon#about to read 5, iclass 14, count 2 2006.257.16:19:14.29#ibcon#read 5, iclass 14, count 2 2006.257.16:19:14.29#ibcon#about to read 6, iclass 14, count 2 2006.257.16:19:14.29#ibcon#read 6, iclass 14, count 2 2006.257.16:19:14.29#ibcon#end of sib2, iclass 14, count 2 2006.257.16:19:14.29#ibcon#*mode == 0, iclass 14, count 2 2006.257.16:19:14.29#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.16:19:14.29#ibcon#[27=AT01-04\r\n] 2006.257.16:19:14.29#ibcon#*before write, iclass 14, count 2 2006.257.16:19:14.29#ibcon#enter sib2, iclass 14, count 2 2006.257.16:19:14.29#ibcon#flushed, iclass 14, count 2 2006.257.16:19:14.29#ibcon#about to write, iclass 14, count 2 2006.257.16:19:14.29#ibcon#wrote, iclass 14, count 2 2006.257.16:19:14.29#ibcon#about to read 3, iclass 14, count 2 2006.257.16:19:14.32#ibcon#read 3, iclass 14, count 2 2006.257.16:19:14.32#ibcon#about to read 4, iclass 14, count 2 2006.257.16:19:14.32#ibcon#read 4, iclass 14, count 2 2006.257.16:19:14.32#ibcon#about to read 5, iclass 14, count 2 2006.257.16:19:14.32#ibcon#read 5, iclass 14, count 2 2006.257.16:19:14.32#ibcon#about to read 6, iclass 14, count 2 2006.257.16:19:14.32#ibcon#read 6, iclass 14, count 2 2006.257.16:19:14.32#ibcon#end of sib2, iclass 14, count 2 2006.257.16:19:14.32#ibcon#*after write, iclass 14, count 2 2006.257.16:19:14.32#ibcon#*before return 0, iclass 14, count 2 2006.257.16:19:14.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:14.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:19:14.32#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.16:19:14.32#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:14.32#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:14.44#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:14.44#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:14.44#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:19:14.44#ibcon#first serial, iclass 14, count 0 2006.257.16:19:14.44#ibcon#enter sib2, iclass 14, count 0 2006.257.16:19:14.44#ibcon#flushed, iclass 14, count 0 2006.257.16:19:14.44#ibcon#about to write, iclass 14, count 0 2006.257.16:19:14.44#ibcon#wrote, iclass 14, count 0 2006.257.16:19:14.44#ibcon#about to read 3, iclass 14, count 0 2006.257.16:19:14.46#ibcon#read 3, iclass 14, count 0 2006.257.16:19:14.46#ibcon#about to read 4, iclass 14, count 0 2006.257.16:19:14.46#ibcon#read 4, iclass 14, count 0 2006.257.16:19:14.46#ibcon#about to read 5, iclass 14, count 0 2006.257.16:19:14.46#ibcon#read 5, iclass 14, count 0 2006.257.16:19:14.46#ibcon#about to read 6, iclass 14, count 0 2006.257.16:19:14.46#ibcon#read 6, iclass 14, count 0 2006.257.16:19:14.46#ibcon#end of sib2, iclass 14, count 0 2006.257.16:19:14.46#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:19:14.46#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:19:14.46#ibcon#[27=USB\r\n] 2006.257.16:19:14.46#ibcon#*before write, iclass 14, count 0 2006.257.16:19:14.46#ibcon#enter sib2, iclass 14, count 0 2006.257.16:19:14.46#ibcon#flushed, iclass 14, count 0 2006.257.16:19:14.46#ibcon#about to write, iclass 14, count 0 2006.257.16:19:14.46#ibcon#wrote, iclass 14, count 0 2006.257.16:19:14.46#ibcon#about to read 3, iclass 14, count 0 2006.257.16:19:14.49#ibcon#read 3, iclass 14, count 0 2006.257.16:19:14.49#ibcon#about to read 4, iclass 14, count 0 2006.257.16:19:14.49#ibcon#read 4, iclass 14, count 0 2006.257.16:19:14.49#ibcon#about to read 5, iclass 14, count 0 2006.257.16:19:14.49#ibcon#read 5, iclass 14, count 0 2006.257.16:19:14.49#ibcon#about to read 6, iclass 14, count 0 2006.257.16:19:14.49#ibcon#read 6, iclass 14, count 0 2006.257.16:19:14.49#ibcon#end of sib2, iclass 14, count 0 2006.257.16:19:14.49#ibcon#*after write, iclass 14, count 0 2006.257.16:19:14.49#ibcon#*before return 0, iclass 14, count 0 2006.257.16:19:14.49#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:14.49#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:19:14.49#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:19:14.49#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:19:14.49$vck44/vblo=2,634.99 2006.257.16:19:14.49#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.16:19:14.49#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.16:19:14.49#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:14.49#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:14.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:14.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:14.49#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:19:14.49#ibcon#first serial, iclass 16, count 0 2006.257.16:19:14.49#ibcon#enter sib2, iclass 16, count 0 2006.257.16:19:14.49#ibcon#flushed, iclass 16, count 0 2006.257.16:19:14.49#ibcon#about to write, iclass 16, count 0 2006.257.16:19:14.49#ibcon#wrote, iclass 16, count 0 2006.257.16:19:14.49#ibcon#about to read 3, iclass 16, count 0 2006.257.16:19:14.51#ibcon#read 3, iclass 16, count 0 2006.257.16:19:14.51#ibcon#about to read 4, iclass 16, count 0 2006.257.16:19:14.51#ibcon#read 4, iclass 16, count 0 2006.257.16:19:14.51#ibcon#about to read 5, iclass 16, count 0 2006.257.16:19:14.51#ibcon#read 5, iclass 16, count 0 2006.257.16:19:14.51#ibcon#about to read 6, iclass 16, count 0 2006.257.16:19:14.51#ibcon#read 6, iclass 16, count 0 2006.257.16:19:14.51#ibcon#end of sib2, iclass 16, count 0 2006.257.16:19:14.51#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:19:14.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:19:14.51#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.16:19:14.51#ibcon#*before write, iclass 16, count 0 2006.257.16:19:14.51#ibcon#enter sib2, iclass 16, count 0 2006.257.16:19:14.51#ibcon#flushed, iclass 16, count 0 2006.257.16:19:14.51#ibcon#about to write, iclass 16, count 0 2006.257.16:19:14.51#ibcon#wrote, iclass 16, count 0 2006.257.16:19:14.51#ibcon#about to read 3, iclass 16, count 0 2006.257.16:19:14.55#ibcon#read 3, iclass 16, count 0 2006.257.16:19:14.55#ibcon#about to read 4, iclass 16, count 0 2006.257.16:19:14.55#ibcon#read 4, iclass 16, count 0 2006.257.16:19:14.55#ibcon#about to read 5, iclass 16, count 0 2006.257.16:19:14.55#ibcon#read 5, iclass 16, count 0 2006.257.16:19:14.55#ibcon#about to read 6, iclass 16, count 0 2006.257.16:19:14.55#ibcon#read 6, iclass 16, count 0 2006.257.16:19:14.55#ibcon#end of sib2, iclass 16, count 0 2006.257.16:19:14.55#ibcon#*after write, iclass 16, count 0 2006.257.16:19:14.55#ibcon#*before return 0, iclass 16, count 0 2006.257.16:19:14.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:14.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:19:14.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:19:14.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:19:14.55$vck44/vb=2,5 2006.257.16:19:14.55#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.16:19:14.55#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.16:19:14.55#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:14.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:14.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:14.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:14.61#ibcon#enter wrdev, iclass 18, count 2 2006.257.16:19:14.61#ibcon#first serial, iclass 18, count 2 2006.257.16:19:14.61#ibcon#enter sib2, iclass 18, count 2 2006.257.16:19:14.61#ibcon#flushed, iclass 18, count 2 2006.257.16:19:14.61#ibcon#about to write, iclass 18, count 2 2006.257.16:19:14.61#ibcon#wrote, iclass 18, count 2 2006.257.16:19:14.61#ibcon#about to read 3, iclass 18, count 2 2006.257.16:19:14.63#ibcon#read 3, iclass 18, count 2 2006.257.16:19:14.63#ibcon#about to read 4, iclass 18, count 2 2006.257.16:19:14.63#ibcon#read 4, iclass 18, count 2 2006.257.16:19:14.63#ibcon#about to read 5, iclass 18, count 2 2006.257.16:19:14.63#ibcon#read 5, iclass 18, count 2 2006.257.16:19:14.63#ibcon#about to read 6, iclass 18, count 2 2006.257.16:19:14.63#ibcon#read 6, iclass 18, count 2 2006.257.16:19:14.63#ibcon#end of sib2, iclass 18, count 2 2006.257.16:19:14.63#ibcon#*mode == 0, iclass 18, count 2 2006.257.16:19:14.63#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.16:19:14.63#ibcon#[27=AT02-05\r\n] 2006.257.16:19:14.63#ibcon#*before write, iclass 18, count 2 2006.257.16:19:14.63#ibcon#enter sib2, iclass 18, count 2 2006.257.16:19:14.63#ibcon#flushed, iclass 18, count 2 2006.257.16:19:14.63#ibcon#about to write, iclass 18, count 2 2006.257.16:19:14.63#ibcon#wrote, iclass 18, count 2 2006.257.16:19:14.63#ibcon#about to read 3, iclass 18, count 2 2006.257.16:19:14.66#ibcon#read 3, iclass 18, count 2 2006.257.16:19:14.66#ibcon#about to read 4, iclass 18, count 2 2006.257.16:19:14.66#ibcon#read 4, iclass 18, count 2 2006.257.16:19:14.66#ibcon#about to read 5, iclass 18, count 2 2006.257.16:19:14.66#ibcon#read 5, iclass 18, count 2 2006.257.16:19:14.66#ibcon#about to read 6, iclass 18, count 2 2006.257.16:19:14.66#ibcon#read 6, iclass 18, count 2 2006.257.16:19:14.66#ibcon#end of sib2, iclass 18, count 2 2006.257.16:19:14.66#ibcon#*after write, iclass 18, count 2 2006.257.16:19:14.66#ibcon#*before return 0, iclass 18, count 2 2006.257.16:19:14.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:14.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:19:14.66#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.16:19:14.66#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:14.66#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:14.78#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:14.78#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:14.78#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:19:14.78#ibcon#first serial, iclass 18, count 0 2006.257.16:19:14.78#ibcon#enter sib2, iclass 18, count 0 2006.257.16:19:14.78#ibcon#flushed, iclass 18, count 0 2006.257.16:19:14.78#ibcon#about to write, iclass 18, count 0 2006.257.16:19:14.78#ibcon#wrote, iclass 18, count 0 2006.257.16:19:14.78#ibcon#about to read 3, iclass 18, count 0 2006.257.16:19:14.80#ibcon#read 3, iclass 18, count 0 2006.257.16:19:14.80#ibcon#about to read 4, iclass 18, count 0 2006.257.16:19:14.80#ibcon#read 4, iclass 18, count 0 2006.257.16:19:14.80#ibcon#about to read 5, iclass 18, count 0 2006.257.16:19:14.80#ibcon#read 5, iclass 18, count 0 2006.257.16:19:14.80#ibcon#about to read 6, iclass 18, count 0 2006.257.16:19:14.80#ibcon#read 6, iclass 18, count 0 2006.257.16:19:14.80#ibcon#end of sib2, iclass 18, count 0 2006.257.16:19:14.80#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:19:14.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:19:14.80#ibcon#[27=USB\r\n] 2006.257.16:19:14.80#ibcon#*before write, iclass 18, count 0 2006.257.16:19:14.80#ibcon#enter sib2, iclass 18, count 0 2006.257.16:19:14.80#ibcon#flushed, iclass 18, count 0 2006.257.16:19:14.80#ibcon#about to write, iclass 18, count 0 2006.257.16:19:14.80#ibcon#wrote, iclass 18, count 0 2006.257.16:19:14.80#ibcon#about to read 3, iclass 18, count 0 2006.257.16:19:14.83#ibcon#read 3, iclass 18, count 0 2006.257.16:19:14.83#ibcon#about to read 4, iclass 18, count 0 2006.257.16:19:14.83#ibcon#read 4, iclass 18, count 0 2006.257.16:19:14.83#ibcon#about to read 5, iclass 18, count 0 2006.257.16:19:14.83#ibcon#read 5, iclass 18, count 0 2006.257.16:19:14.83#ibcon#about to read 6, iclass 18, count 0 2006.257.16:19:14.83#ibcon#read 6, iclass 18, count 0 2006.257.16:19:14.83#ibcon#end of sib2, iclass 18, count 0 2006.257.16:19:14.83#ibcon#*after write, iclass 18, count 0 2006.257.16:19:14.83#ibcon#*before return 0, iclass 18, count 0 2006.257.16:19:14.83#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:14.83#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:19:14.83#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:19:14.83#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:19:14.83$vck44/vblo=3,649.99 2006.257.16:19:14.83#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.16:19:14.83#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.16:19:14.83#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:14.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:14.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:14.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:14.83#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:19:14.83#ibcon#first serial, iclass 20, count 0 2006.257.16:19:14.83#ibcon#enter sib2, iclass 20, count 0 2006.257.16:19:14.83#ibcon#flushed, iclass 20, count 0 2006.257.16:19:14.83#ibcon#about to write, iclass 20, count 0 2006.257.16:19:14.83#ibcon#wrote, iclass 20, count 0 2006.257.16:19:14.83#ibcon#about to read 3, iclass 20, count 0 2006.257.16:19:14.85#ibcon#read 3, iclass 20, count 0 2006.257.16:19:14.85#ibcon#about to read 4, iclass 20, count 0 2006.257.16:19:14.85#ibcon#read 4, iclass 20, count 0 2006.257.16:19:14.85#ibcon#about to read 5, iclass 20, count 0 2006.257.16:19:14.85#ibcon#read 5, iclass 20, count 0 2006.257.16:19:14.85#ibcon#about to read 6, iclass 20, count 0 2006.257.16:19:14.85#ibcon#read 6, iclass 20, count 0 2006.257.16:19:14.85#ibcon#end of sib2, iclass 20, count 0 2006.257.16:19:14.85#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:19:14.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:19:14.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.16:19:14.85#ibcon#*before write, iclass 20, count 0 2006.257.16:19:14.85#ibcon#enter sib2, iclass 20, count 0 2006.257.16:19:14.85#ibcon#flushed, iclass 20, count 0 2006.257.16:19:14.85#ibcon#about to write, iclass 20, count 0 2006.257.16:19:14.85#ibcon#wrote, iclass 20, count 0 2006.257.16:19:14.85#ibcon#about to read 3, iclass 20, count 0 2006.257.16:19:14.89#ibcon#read 3, iclass 20, count 0 2006.257.16:19:14.89#ibcon#about to read 4, iclass 20, count 0 2006.257.16:19:14.89#ibcon#read 4, iclass 20, count 0 2006.257.16:19:14.89#ibcon#about to read 5, iclass 20, count 0 2006.257.16:19:14.89#ibcon#read 5, iclass 20, count 0 2006.257.16:19:14.89#ibcon#about to read 6, iclass 20, count 0 2006.257.16:19:14.89#ibcon#read 6, iclass 20, count 0 2006.257.16:19:14.89#ibcon#end of sib2, iclass 20, count 0 2006.257.16:19:14.89#ibcon#*after write, iclass 20, count 0 2006.257.16:19:14.89#ibcon#*before return 0, iclass 20, count 0 2006.257.16:19:14.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:14.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:19:14.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:19:14.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:19:14.89$vck44/vb=3,4 2006.257.16:19:14.89#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.16:19:14.89#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.16:19:14.89#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:14.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:14.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:14.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:14.95#ibcon#enter wrdev, iclass 22, count 2 2006.257.16:19:14.95#ibcon#first serial, iclass 22, count 2 2006.257.16:19:14.95#ibcon#enter sib2, iclass 22, count 2 2006.257.16:19:14.95#ibcon#flushed, iclass 22, count 2 2006.257.16:19:14.95#ibcon#about to write, iclass 22, count 2 2006.257.16:19:14.95#ibcon#wrote, iclass 22, count 2 2006.257.16:19:14.95#ibcon#about to read 3, iclass 22, count 2 2006.257.16:19:14.97#ibcon#read 3, iclass 22, count 2 2006.257.16:19:14.97#ibcon#about to read 4, iclass 22, count 2 2006.257.16:19:14.97#ibcon#read 4, iclass 22, count 2 2006.257.16:19:14.97#ibcon#about to read 5, iclass 22, count 2 2006.257.16:19:14.97#ibcon#read 5, iclass 22, count 2 2006.257.16:19:14.97#ibcon#about to read 6, iclass 22, count 2 2006.257.16:19:14.97#ibcon#read 6, iclass 22, count 2 2006.257.16:19:14.97#ibcon#end of sib2, iclass 22, count 2 2006.257.16:19:14.97#ibcon#*mode == 0, iclass 22, count 2 2006.257.16:19:14.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.16:19:14.97#ibcon#[27=AT03-04\r\n] 2006.257.16:19:14.97#ibcon#*before write, iclass 22, count 2 2006.257.16:19:14.97#ibcon#enter sib2, iclass 22, count 2 2006.257.16:19:14.97#ibcon#flushed, iclass 22, count 2 2006.257.16:19:14.97#ibcon#about to write, iclass 22, count 2 2006.257.16:19:14.97#ibcon#wrote, iclass 22, count 2 2006.257.16:19:14.97#ibcon#about to read 3, iclass 22, count 2 2006.257.16:19:15.00#ibcon#read 3, iclass 22, count 2 2006.257.16:19:15.00#ibcon#about to read 4, iclass 22, count 2 2006.257.16:19:15.00#ibcon#read 4, iclass 22, count 2 2006.257.16:19:15.00#ibcon#about to read 5, iclass 22, count 2 2006.257.16:19:15.00#ibcon#read 5, iclass 22, count 2 2006.257.16:19:15.00#ibcon#about to read 6, iclass 22, count 2 2006.257.16:19:15.00#ibcon#read 6, iclass 22, count 2 2006.257.16:19:15.00#ibcon#end of sib2, iclass 22, count 2 2006.257.16:19:15.00#ibcon#*after write, iclass 22, count 2 2006.257.16:19:15.00#ibcon#*before return 0, iclass 22, count 2 2006.257.16:19:15.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:15.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:19:15.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.16:19:15.00#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:15.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:15.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:15.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:15.12#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:19:15.12#ibcon#first serial, iclass 22, count 0 2006.257.16:19:15.12#ibcon#enter sib2, iclass 22, count 0 2006.257.16:19:15.12#ibcon#flushed, iclass 22, count 0 2006.257.16:19:15.12#ibcon#about to write, iclass 22, count 0 2006.257.16:19:15.12#ibcon#wrote, iclass 22, count 0 2006.257.16:19:15.12#ibcon#about to read 3, iclass 22, count 0 2006.257.16:19:15.14#ibcon#read 3, iclass 22, count 0 2006.257.16:19:15.14#ibcon#about to read 4, iclass 22, count 0 2006.257.16:19:15.14#ibcon#read 4, iclass 22, count 0 2006.257.16:19:15.14#ibcon#about to read 5, iclass 22, count 0 2006.257.16:19:15.14#ibcon#read 5, iclass 22, count 0 2006.257.16:19:15.14#ibcon#about to read 6, iclass 22, count 0 2006.257.16:19:15.14#ibcon#read 6, iclass 22, count 0 2006.257.16:19:15.14#ibcon#end of sib2, iclass 22, count 0 2006.257.16:19:15.14#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:19:15.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:19:15.14#ibcon#[27=USB\r\n] 2006.257.16:19:15.14#ibcon#*before write, iclass 22, count 0 2006.257.16:19:15.14#ibcon#enter sib2, iclass 22, count 0 2006.257.16:19:15.14#ibcon#flushed, iclass 22, count 0 2006.257.16:19:15.14#ibcon#about to write, iclass 22, count 0 2006.257.16:19:15.14#ibcon#wrote, iclass 22, count 0 2006.257.16:19:15.14#ibcon#about to read 3, iclass 22, count 0 2006.257.16:19:15.17#ibcon#read 3, iclass 22, count 0 2006.257.16:19:15.17#ibcon#about to read 4, iclass 22, count 0 2006.257.16:19:15.17#ibcon#read 4, iclass 22, count 0 2006.257.16:19:15.17#ibcon#about to read 5, iclass 22, count 0 2006.257.16:19:15.17#ibcon#read 5, iclass 22, count 0 2006.257.16:19:15.17#ibcon#about to read 6, iclass 22, count 0 2006.257.16:19:15.17#ibcon#read 6, iclass 22, count 0 2006.257.16:19:15.17#ibcon#end of sib2, iclass 22, count 0 2006.257.16:19:15.17#ibcon#*after write, iclass 22, count 0 2006.257.16:19:15.17#ibcon#*before return 0, iclass 22, count 0 2006.257.16:19:15.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:15.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:19:15.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:19:15.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:19:15.17$vck44/vblo=4,679.99 2006.257.16:19:15.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.16:19:15.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.16:19:15.17#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:15.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:15.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:15.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:15.17#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:19:15.17#ibcon#first serial, iclass 24, count 0 2006.257.16:19:15.17#ibcon#enter sib2, iclass 24, count 0 2006.257.16:19:15.17#ibcon#flushed, iclass 24, count 0 2006.257.16:19:15.17#ibcon#about to write, iclass 24, count 0 2006.257.16:19:15.17#ibcon#wrote, iclass 24, count 0 2006.257.16:19:15.17#ibcon#about to read 3, iclass 24, count 0 2006.257.16:19:15.19#ibcon#read 3, iclass 24, count 0 2006.257.16:19:15.19#ibcon#about to read 4, iclass 24, count 0 2006.257.16:19:15.19#ibcon#read 4, iclass 24, count 0 2006.257.16:19:15.19#ibcon#about to read 5, iclass 24, count 0 2006.257.16:19:15.19#ibcon#read 5, iclass 24, count 0 2006.257.16:19:15.19#ibcon#about to read 6, iclass 24, count 0 2006.257.16:19:15.19#ibcon#read 6, iclass 24, count 0 2006.257.16:19:15.19#ibcon#end of sib2, iclass 24, count 0 2006.257.16:19:15.19#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:19:15.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:19:15.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.16:19:15.19#ibcon#*before write, iclass 24, count 0 2006.257.16:19:15.19#ibcon#enter sib2, iclass 24, count 0 2006.257.16:19:15.19#ibcon#flushed, iclass 24, count 0 2006.257.16:19:15.19#ibcon#about to write, iclass 24, count 0 2006.257.16:19:15.19#ibcon#wrote, iclass 24, count 0 2006.257.16:19:15.19#ibcon#about to read 3, iclass 24, count 0 2006.257.16:19:15.23#ibcon#read 3, iclass 24, count 0 2006.257.16:19:15.23#ibcon#about to read 4, iclass 24, count 0 2006.257.16:19:15.23#ibcon#read 4, iclass 24, count 0 2006.257.16:19:15.23#ibcon#about to read 5, iclass 24, count 0 2006.257.16:19:15.23#ibcon#read 5, iclass 24, count 0 2006.257.16:19:15.23#ibcon#about to read 6, iclass 24, count 0 2006.257.16:19:15.23#ibcon#read 6, iclass 24, count 0 2006.257.16:19:15.23#ibcon#end of sib2, iclass 24, count 0 2006.257.16:19:15.23#ibcon#*after write, iclass 24, count 0 2006.257.16:19:15.23#ibcon#*before return 0, iclass 24, count 0 2006.257.16:19:15.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:15.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:19:15.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:19:15.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:19:15.23$vck44/vb=4,5 2006.257.16:19:15.23#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.16:19:15.23#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.16:19:15.23#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:15.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:15.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:15.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:15.29#ibcon#enter wrdev, iclass 26, count 2 2006.257.16:19:15.29#ibcon#first serial, iclass 26, count 2 2006.257.16:19:15.29#ibcon#enter sib2, iclass 26, count 2 2006.257.16:19:15.29#ibcon#flushed, iclass 26, count 2 2006.257.16:19:15.29#ibcon#about to write, iclass 26, count 2 2006.257.16:19:15.29#ibcon#wrote, iclass 26, count 2 2006.257.16:19:15.29#ibcon#about to read 3, iclass 26, count 2 2006.257.16:19:15.31#ibcon#read 3, iclass 26, count 2 2006.257.16:19:15.31#ibcon#about to read 4, iclass 26, count 2 2006.257.16:19:15.31#ibcon#read 4, iclass 26, count 2 2006.257.16:19:15.31#ibcon#about to read 5, iclass 26, count 2 2006.257.16:19:15.31#ibcon#read 5, iclass 26, count 2 2006.257.16:19:15.31#ibcon#about to read 6, iclass 26, count 2 2006.257.16:19:15.31#ibcon#read 6, iclass 26, count 2 2006.257.16:19:15.31#ibcon#end of sib2, iclass 26, count 2 2006.257.16:19:15.31#ibcon#*mode == 0, iclass 26, count 2 2006.257.16:19:15.31#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.16:19:15.31#ibcon#[27=AT04-05\r\n] 2006.257.16:19:15.31#ibcon#*before write, iclass 26, count 2 2006.257.16:19:15.31#ibcon#enter sib2, iclass 26, count 2 2006.257.16:19:15.31#ibcon#flushed, iclass 26, count 2 2006.257.16:19:15.31#ibcon#about to write, iclass 26, count 2 2006.257.16:19:15.31#ibcon#wrote, iclass 26, count 2 2006.257.16:19:15.31#ibcon#about to read 3, iclass 26, count 2 2006.257.16:19:15.34#ibcon#read 3, iclass 26, count 2 2006.257.16:19:15.34#ibcon#about to read 4, iclass 26, count 2 2006.257.16:19:15.34#ibcon#read 4, iclass 26, count 2 2006.257.16:19:15.34#ibcon#about to read 5, iclass 26, count 2 2006.257.16:19:15.34#ibcon#read 5, iclass 26, count 2 2006.257.16:19:15.34#ibcon#about to read 6, iclass 26, count 2 2006.257.16:19:15.34#ibcon#read 6, iclass 26, count 2 2006.257.16:19:15.34#ibcon#end of sib2, iclass 26, count 2 2006.257.16:19:15.34#ibcon#*after write, iclass 26, count 2 2006.257.16:19:15.34#ibcon#*before return 0, iclass 26, count 2 2006.257.16:19:15.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:15.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:19:15.34#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.16:19:15.34#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:15.34#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:15.46#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:15.46#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:15.46#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:19:15.46#ibcon#first serial, iclass 26, count 0 2006.257.16:19:15.46#ibcon#enter sib2, iclass 26, count 0 2006.257.16:19:15.46#ibcon#flushed, iclass 26, count 0 2006.257.16:19:15.46#ibcon#about to write, iclass 26, count 0 2006.257.16:19:15.46#ibcon#wrote, iclass 26, count 0 2006.257.16:19:15.46#ibcon#about to read 3, iclass 26, count 0 2006.257.16:19:15.48#ibcon#read 3, iclass 26, count 0 2006.257.16:19:15.48#ibcon#about to read 4, iclass 26, count 0 2006.257.16:19:15.48#ibcon#read 4, iclass 26, count 0 2006.257.16:19:15.48#ibcon#about to read 5, iclass 26, count 0 2006.257.16:19:15.48#ibcon#read 5, iclass 26, count 0 2006.257.16:19:15.48#ibcon#about to read 6, iclass 26, count 0 2006.257.16:19:15.48#ibcon#read 6, iclass 26, count 0 2006.257.16:19:15.48#ibcon#end of sib2, iclass 26, count 0 2006.257.16:19:15.48#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:19:15.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:19:15.48#ibcon#[27=USB\r\n] 2006.257.16:19:15.48#ibcon#*before write, iclass 26, count 0 2006.257.16:19:15.48#ibcon#enter sib2, iclass 26, count 0 2006.257.16:19:15.48#ibcon#flushed, iclass 26, count 0 2006.257.16:19:15.48#ibcon#about to write, iclass 26, count 0 2006.257.16:19:15.48#ibcon#wrote, iclass 26, count 0 2006.257.16:19:15.48#ibcon#about to read 3, iclass 26, count 0 2006.257.16:19:15.51#ibcon#read 3, iclass 26, count 0 2006.257.16:19:15.51#ibcon#about to read 4, iclass 26, count 0 2006.257.16:19:15.51#ibcon#read 4, iclass 26, count 0 2006.257.16:19:15.51#ibcon#about to read 5, iclass 26, count 0 2006.257.16:19:15.51#ibcon#read 5, iclass 26, count 0 2006.257.16:19:15.51#ibcon#about to read 6, iclass 26, count 0 2006.257.16:19:15.51#ibcon#read 6, iclass 26, count 0 2006.257.16:19:15.51#ibcon#end of sib2, iclass 26, count 0 2006.257.16:19:15.51#ibcon#*after write, iclass 26, count 0 2006.257.16:19:15.51#ibcon#*before return 0, iclass 26, count 0 2006.257.16:19:15.51#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:15.51#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:19:15.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:19:15.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:19:15.51$vck44/vblo=5,709.99 2006.257.16:19:15.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.16:19:15.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.16:19:15.51#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:15.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:15.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:15.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:15.51#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:19:15.51#ibcon#first serial, iclass 28, count 0 2006.257.16:19:15.51#ibcon#enter sib2, iclass 28, count 0 2006.257.16:19:15.51#ibcon#flushed, iclass 28, count 0 2006.257.16:19:15.51#ibcon#about to write, iclass 28, count 0 2006.257.16:19:15.51#ibcon#wrote, iclass 28, count 0 2006.257.16:19:15.51#ibcon#about to read 3, iclass 28, count 0 2006.257.16:19:15.53#ibcon#read 3, iclass 28, count 0 2006.257.16:19:15.53#ibcon#about to read 4, iclass 28, count 0 2006.257.16:19:15.53#ibcon#read 4, iclass 28, count 0 2006.257.16:19:15.53#ibcon#about to read 5, iclass 28, count 0 2006.257.16:19:15.53#ibcon#read 5, iclass 28, count 0 2006.257.16:19:15.53#ibcon#about to read 6, iclass 28, count 0 2006.257.16:19:15.53#ibcon#read 6, iclass 28, count 0 2006.257.16:19:15.53#ibcon#end of sib2, iclass 28, count 0 2006.257.16:19:15.53#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:19:15.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:19:15.53#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:19:15.53#ibcon#*before write, iclass 28, count 0 2006.257.16:19:15.53#ibcon#enter sib2, iclass 28, count 0 2006.257.16:19:15.53#ibcon#flushed, iclass 28, count 0 2006.257.16:19:15.53#ibcon#about to write, iclass 28, count 0 2006.257.16:19:15.53#ibcon#wrote, iclass 28, count 0 2006.257.16:19:15.53#ibcon#about to read 3, iclass 28, count 0 2006.257.16:19:15.57#ibcon#read 3, iclass 28, count 0 2006.257.16:19:15.57#ibcon#about to read 4, iclass 28, count 0 2006.257.16:19:15.57#ibcon#read 4, iclass 28, count 0 2006.257.16:19:15.57#ibcon#about to read 5, iclass 28, count 0 2006.257.16:19:15.57#ibcon#read 5, iclass 28, count 0 2006.257.16:19:15.57#ibcon#about to read 6, iclass 28, count 0 2006.257.16:19:15.57#ibcon#read 6, iclass 28, count 0 2006.257.16:19:15.57#ibcon#end of sib2, iclass 28, count 0 2006.257.16:19:15.57#ibcon#*after write, iclass 28, count 0 2006.257.16:19:15.57#ibcon#*before return 0, iclass 28, count 0 2006.257.16:19:15.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:15.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:19:15.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:19:15.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:19:15.57$vck44/vb=5,4 2006.257.16:19:15.57#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.16:19:15.57#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.16:19:15.57#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:15.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:15.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:15.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:15.63#ibcon#enter wrdev, iclass 30, count 2 2006.257.16:19:15.63#ibcon#first serial, iclass 30, count 2 2006.257.16:19:15.63#ibcon#enter sib2, iclass 30, count 2 2006.257.16:19:15.63#ibcon#flushed, iclass 30, count 2 2006.257.16:19:15.63#ibcon#about to write, iclass 30, count 2 2006.257.16:19:15.63#ibcon#wrote, iclass 30, count 2 2006.257.16:19:15.63#ibcon#about to read 3, iclass 30, count 2 2006.257.16:19:15.65#ibcon#read 3, iclass 30, count 2 2006.257.16:19:15.65#ibcon#about to read 4, iclass 30, count 2 2006.257.16:19:15.65#ibcon#read 4, iclass 30, count 2 2006.257.16:19:15.65#ibcon#about to read 5, iclass 30, count 2 2006.257.16:19:15.65#ibcon#read 5, iclass 30, count 2 2006.257.16:19:15.65#ibcon#about to read 6, iclass 30, count 2 2006.257.16:19:15.65#ibcon#read 6, iclass 30, count 2 2006.257.16:19:15.65#ibcon#end of sib2, iclass 30, count 2 2006.257.16:19:15.65#ibcon#*mode == 0, iclass 30, count 2 2006.257.16:19:15.65#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.16:19:15.65#ibcon#[27=AT05-04\r\n] 2006.257.16:19:15.65#ibcon#*before write, iclass 30, count 2 2006.257.16:19:15.65#ibcon#enter sib2, iclass 30, count 2 2006.257.16:19:15.65#ibcon#flushed, iclass 30, count 2 2006.257.16:19:15.65#ibcon#about to write, iclass 30, count 2 2006.257.16:19:15.65#ibcon#wrote, iclass 30, count 2 2006.257.16:19:15.65#ibcon#about to read 3, iclass 30, count 2 2006.257.16:19:15.68#ibcon#read 3, iclass 30, count 2 2006.257.16:19:15.68#ibcon#about to read 4, iclass 30, count 2 2006.257.16:19:15.68#ibcon#read 4, iclass 30, count 2 2006.257.16:19:15.68#ibcon#about to read 5, iclass 30, count 2 2006.257.16:19:15.68#ibcon#read 5, iclass 30, count 2 2006.257.16:19:15.68#ibcon#about to read 6, iclass 30, count 2 2006.257.16:19:15.68#ibcon#read 6, iclass 30, count 2 2006.257.16:19:15.68#ibcon#end of sib2, iclass 30, count 2 2006.257.16:19:15.68#ibcon#*after write, iclass 30, count 2 2006.257.16:19:15.68#ibcon#*before return 0, iclass 30, count 2 2006.257.16:19:15.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:15.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:19:15.68#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.16:19:15.68#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:15.68#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:15.80#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:15.80#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:15.80#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:19:15.80#ibcon#first serial, iclass 30, count 0 2006.257.16:19:15.80#ibcon#enter sib2, iclass 30, count 0 2006.257.16:19:15.80#ibcon#flushed, iclass 30, count 0 2006.257.16:19:15.80#ibcon#about to write, iclass 30, count 0 2006.257.16:19:15.80#ibcon#wrote, iclass 30, count 0 2006.257.16:19:15.80#ibcon#about to read 3, iclass 30, count 0 2006.257.16:19:15.82#ibcon#read 3, iclass 30, count 0 2006.257.16:19:15.82#ibcon#about to read 4, iclass 30, count 0 2006.257.16:19:15.82#ibcon#read 4, iclass 30, count 0 2006.257.16:19:15.82#ibcon#about to read 5, iclass 30, count 0 2006.257.16:19:15.82#ibcon#read 5, iclass 30, count 0 2006.257.16:19:15.82#ibcon#about to read 6, iclass 30, count 0 2006.257.16:19:15.82#ibcon#read 6, iclass 30, count 0 2006.257.16:19:15.82#ibcon#end of sib2, iclass 30, count 0 2006.257.16:19:15.82#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:19:15.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:19:15.82#ibcon#[27=USB\r\n] 2006.257.16:19:15.82#ibcon#*before write, iclass 30, count 0 2006.257.16:19:15.82#ibcon#enter sib2, iclass 30, count 0 2006.257.16:19:15.82#ibcon#flushed, iclass 30, count 0 2006.257.16:19:15.82#ibcon#about to write, iclass 30, count 0 2006.257.16:19:15.82#ibcon#wrote, iclass 30, count 0 2006.257.16:19:15.82#ibcon#about to read 3, iclass 30, count 0 2006.257.16:19:15.85#ibcon#read 3, iclass 30, count 0 2006.257.16:19:15.85#ibcon#about to read 4, iclass 30, count 0 2006.257.16:19:15.85#ibcon#read 4, iclass 30, count 0 2006.257.16:19:15.85#ibcon#about to read 5, iclass 30, count 0 2006.257.16:19:15.85#ibcon#read 5, iclass 30, count 0 2006.257.16:19:15.85#ibcon#about to read 6, iclass 30, count 0 2006.257.16:19:15.85#ibcon#read 6, iclass 30, count 0 2006.257.16:19:15.85#ibcon#end of sib2, iclass 30, count 0 2006.257.16:19:15.85#ibcon#*after write, iclass 30, count 0 2006.257.16:19:15.85#ibcon#*before return 0, iclass 30, count 0 2006.257.16:19:15.85#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:15.85#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:19:15.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:19:15.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:19:15.85$vck44/vblo=6,719.99 2006.257.16:19:15.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.16:19:15.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.16:19:15.85#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:15.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:15.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:15.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:15.85#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:19:15.85#ibcon#first serial, iclass 32, count 0 2006.257.16:19:15.85#ibcon#enter sib2, iclass 32, count 0 2006.257.16:19:15.85#ibcon#flushed, iclass 32, count 0 2006.257.16:19:15.85#ibcon#about to write, iclass 32, count 0 2006.257.16:19:15.85#ibcon#wrote, iclass 32, count 0 2006.257.16:19:15.85#ibcon#about to read 3, iclass 32, count 0 2006.257.16:19:15.87#ibcon#read 3, iclass 32, count 0 2006.257.16:19:15.87#ibcon#about to read 4, iclass 32, count 0 2006.257.16:19:15.87#ibcon#read 4, iclass 32, count 0 2006.257.16:19:15.87#ibcon#about to read 5, iclass 32, count 0 2006.257.16:19:15.87#ibcon#read 5, iclass 32, count 0 2006.257.16:19:15.87#ibcon#about to read 6, iclass 32, count 0 2006.257.16:19:15.87#ibcon#read 6, iclass 32, count 0 2006.257.16:19:15.87#ibcon#end of sib2, iclass 32, count 0 2006.257.16:19:15.87#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:19:15.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:19:15.87#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:19:15.87#ibcon#*before write, iclass 32, count 0 2006.257.16:19:15.87#ibcon#enter sib2, iclass 32, count 0 2006.257.16:19:15.87#ibcon#flushed, iclass 32, count 0 2006.257.16:19:15.87#ibcon#about to write, iclass 32, count 0 2006.257.16:19:15.87#ibcon#wrote, iclass 32, count 0 2006.257.16:19:15.87#ibcon#about to read 3, iclass 32, count 0 2006.257.16:19:15.91#ibcon#read 3, iclass 32, count 0 2006.257.16:19:15.91#ibcon#about to read 4, iclass 32, count 0 2006.257.16:19:15.91#ibcon#read 4, iclass 32, count 0 2006.257.16:19:15.91#ibcon#about to read 5, iclass 32, count 0 2006.257.16:19:15.91#ibcon#read 5, iclass 32, count 0 2006.257.16:19:15.91#ibcon#about to read 6, iclass 32, count 0 2006.257.16:19:15.91#ibcon#read 6, iclass 32, count 0 2006.257.16:19:15.91#ibcon#end of sib2, iclass 32, count 0 2006.257.16:19:15.91#ibcon#*after write, iclass 32, count 0 2006.257.16:19:15.91#ibcon#*before return 0, iclass 32, count 0 2006.257.16:19:15.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:15.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:19:15.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:19:15.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:19:15.91$vck44/vb=6,4 2006.257.16:19:15.91#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.16:19:15.91#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.16:19:15.91#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:15.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:15.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:15.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:15.97#ibcon#enter wrdev, iclass 34, count 2 2006.257.16:19:15.97#ibcon#first serial, iclass 34, count 2 2006.257.16:19:15.97#ibcon#enter sib2, iclass 34, count 2 2006.257.16:19:15.97#ibcon#flushed, iclass 34, count 2 2006.257.16:19:15.97#ibcon#about to write, iclass 34, count 2 2006.257.16:19:15.97#ibcon#wrote, iclass 34, count 2 2006.257.16:19:15.97#ibcon#about to read 3, iclass 34, count 2 2006.257.16:19:15.99#ibcon#read 3, iclass 34, count 2 2006.257.16:19:15.99#ibcon#about to read 4, iclass 34, count 2 2006.257.16:19:15.99#ibcon#read 4, iclass 34, count 2 2006.257.16:19:15.99#ibcon#about to read 5, iclass 34, count 2 2006.257.16:19:15.99#ibcon#read 5, iclass 34, count 2 2006.257.16:19:15.99#ibcon#about to read 6, iclass 34, count 2 2006.257.16:19:15.99#ibcon#read 6, iclass 34, count 2 2006.257.16:19:15.99#ibcon#end of sib2, iclass 34, count 2 2006.257.16:19:15.99#ibcon#*mode == 0, iclass 34, count 2 2006.257.16:19:15.99#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.16:19:15.99#ibcon#[27=AT06-04\r\n] 2006.257.16:19:15.99#ibcon#*before write, iclass 34, count 2 2006.257.16:19:15.99#ibcon#enter sib2, iclass 34, count 2 2006.257.16:19:15.99#ibcon#flushed, iclass 34, count 2 2006.257.16:19:15.99#ibcon#about to write, iclass 34, count 2 2006.257.16:19:15.99#ibcon#wrote, iclass 34, count 2 2006.257.16:19:15.99#ibcon#about to read 3, iclass 34, count 2 2006.257.16:19:16.02#ibcon#read 3, iclass 34, count 2 2006.257.16:19:16.02#ibcon#about to read 4, iclass 34, count 2 2006.257.16:19:16.02#ibcon#read 4, iclass 34, count 2 2006.257.16:19:16.02#ibcon#about to read 5, iclass 34, count 2 2006.257.16:19:16.02#ibcon#read 5, iclass 34, count 2 2006.257.16:19:16.02#ibcon#about to read 6, iclass 34, count 2 2006.257.16:19:16.02#ibcon#read 6, iclass 34, count 2 2006.257.16:19:16.02#ibcon#end of sib2, iclass 34, count 2 2006.257.16:19:16.02#ibcon#*after write, iclass 34, count 2 2006.257.16:19:16.02#ibcon#*before return 0, iclass 34, count 2 2006.257.16:19:16.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:16.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:19:16.02#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.16:19:16.02#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:16.02#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:16.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:16.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:16.14#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:19:16.14#ibcon#first serial, iclass 34, count 0 2006.257.16:19:16.14#ibcon#enter sib2, iclass 34, count 0 2006.257.16:19:16.14#ibcon#flushed, iclass 34, count 0 2006.257.16:19:16.14#ibcon#about to write, iclass 34, count 0 2006.257.16:19:16.14#ibcon#wrote, iclass 34, count 0 2006.257.16:19:16.14#ibcon#about to read 3, iclass 34, count 0 2006.257.16:19:16.16#ibcon#read 3, iclass 34, count 0 2006.257.16:19:16.16#ibcon#about to read 4, iclass 34, count 0 2006.257.16:19:16.16#ibcon#read 4, iclass 34, count 0 2006.257.16:19:16.16#ibcon#about to read 5, iclass 34, count 0 2006.257.16:19:16.16#ibcon#read 5, iclass 34, count 0 2006.257.16:19:16.16#ibcon#about to read 6, iclass 34, count 0 2006.257.16:19:16.16#ibcon#read 6, iclass 34, count 0 2006.257.16:19:16.16#ibcon#end of sib2, iclass 34, count 0 2006.257.16:19:16.16#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:19:16.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:19:16.16#ibcon#[27=USB\r\n] 2006.257.16:19:16.16#ibcon#*before write, iclass 34, count 0 2006.257.16:19:16.16#ibcon#enter sib2, iclass 34, count 0 2006.257.16:19:16.16#ibcon#flushed, iclass 34, count 0 2006.257.16:19:16.16#ibcon#about to write, iclass 34, count 0 2006.257.16:19:16.16#ibcon#wrote, iclass 34, count 0 2006.257.16:19:16.16#ibcon#about to read 3, iclass 34, count 0 2006.257.16:19:16.19#ibcon#read 3, iclass 34, count 0 2006.257.16:19:16.19#ibcon#about to read 4, iclass 34, count 0 2006.257.16:19:16.19#ibcon#read 4, iclass 34, count 0 2006.257.16:19:16.19#ibcon#about to read 5, iclass 34, count 0 2006.257.16:19:16.19#ibcon#read 5, iclass 34, count 0 2006.257.16:19:16.19#ibcon#about to read 6, iclass 34, count 0 2006.257.16:19:16.19#ibcon#read 6, iclass 34, count 0 2006.257.16:19:16.19#ibcon#end of sib2, iclass 34, count 0 2006.257.16:19:16.19#ibcon#*after write, iclass 34, count 0 2006.257.16:19:16.19#ibcon#*before return 0, iclass 34, count 0 2006.257.16:19:16.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:16.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:19:16.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:19:16.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:19:16.19$vck44/vblo=7,734.99 2006.257.16:19:16.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.16:19:16.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.16:19:16.19#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:16.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:19:16.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:19:16.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:19:16.19#ibcon#enter wrdev, iclass 36, count 0 2006.257.16:19:16.19#ibcon#first serial, iclass 36, count 0 2006.257.16:19:16.19#ibcon#enter sib2, iclass 36, count 0 2006.257.16:19:16.19#ibcon#flushed, iclass 36, count 0 2006.257.16:19:16.19#ibcon#about to write, iclass 36, count 0 2006.257.16:19:16.19#ibcon#wrote, iclass 36, count 0 2006.257.16:19:16.19#ibcon#about to read 3, iclass 36, count 0 2006.257.16:19:16.21#ibcon#read 3, iclass 36, count 0 2006.257.16:19:16.21#ibcon#about to read 4, iclass 36, count 0 2006.257.16:19:16.21#ibcon#read 4, iclass 36, count 0 2006.257.16:19:16.21#ibcon#about to read 5, iclass 36, count 0 2006.257.16:19:16.21#ibcon#read 5, iclass 36, count 0 2006.257.16:19:16.21#ibcon#about to read 6, iclass 36, count 0 2006.257.16:19:16.21#ibcon#read 6, iclass 36, count 0 2006.257.16:19:16.21#ibcon#end of sib2, iclass 36, count 0 2006.257.16:19:16.21#ibcon#*mode == 0, iclass 36, count 0 2006.257.16:19:16.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.16:19:16.21#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:19:16.21#ibcon#*before write, iclass 36, count 0 2006.257.16:19:16.21#ibcon#enter sib2, iclass 36, count 0 2006.257.16:19:16.21#ibcon#flushed, iclass 36, count 0 2006.257.16:19:16.21#ibcon#about to write, iclass 36, count 0 2006.257.16:19:16.21#ibcon#wrote, iclass 36, count 0 2006.257.16:19:16.21#ibcon#about to read 3, iclass 36, count 0 2006.257.16:19:16.25#ibcon#read 3, iclass 36, count 0 2006.257.16:19:16.25#ibcon#about to read 4, iclass 36, count 0 2006.257.16:19:16.25#ibcon#read 4, iclass 36, count 0 2006.257.16:19:16.25#ibcon#about to read 5, iclass 36, count 0 2006.257.16:19:16.25#ibcon#read 5, iclass 36, count 0 2006.257.16:19:16.25#ibcon#about to read 6, iclass 36, count 0 2006.257.16:19:16.25#ibcon#read 6, iclass 36, count 0 2006.257.16:19:16.25#ibcon#end of sib2, iclass 36, count 0 2006.257.16:19:16.25#ibcon#*after write, iclass 36, count 0 2006.257.16:19:16.25#ibcon#*before return 0, iclass 36, count 0 2006.257.16:19:16.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:19:16.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:19:16.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.16:19:16.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.16:19:16.25$vck44/vb=7,4 2006.257.16:19:16.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.16:19:16.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.16:19:16.25#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:16.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:19:16.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:19:16.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:19:16.31#ibcon#enter wrdev, iclass 38, count 2 2006.257.16:19:16.31#ibcon#first serial, iclass 38, count 2 2006.257.16:19:16.31#ibcon#enter sib2, iclass 38, count 2 2006.257.16:19:16.31#ibcon#flushed, iclass 38, count 2 2006.257.16:19:16.31#ibcon#about to write, iclass 38, count 2 2006.257.16:19:16.31#ibcon#wrote, iclass 38, count 2 2006.257.16:19:16.31#ibcon#about to read 3, iclass 38, count 2 2006.257.16:19:16.33#ibcon#read 3, iclass 38, count 2 2006.257.16:19:16.33#ibcon#about to read 4, iclass 38, count 2 2006.257.16:19:16.33#ibcon#read 4, iclass 38, count 2 2006.257.16:19:16.33#ibcon#about to read 5, iclass 38, count 2 2006.257.16:19:16.33#ibcon#read 5, iclass 38, count 2 2006.257.16:19:16.33#ibcon#about to read 6, iclass 38, count 2 2006.257.16:19:16.33#ibcon#read 6, iclass 38, count 2 2006.257.16:19:16.33#ibcon#end of sib2, iclass 38, count 2 2006.257.16:19:16.33#ibcon#*mode == 0, iclass 38, count 2 2006.257.16:19:16.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.16:19:16.33#ibcon#[27=AT07-04\r\n] 2006.257.16:19:16.33#ibcon#*before write, iclass 38, count 2 2006.257.16:19:16.33#ibcon#enter sib2, iclass 38, count 2 2006.257.16:19:16.33#ibcon#flushed, iclass 38, count 2 2006.257.16:19:16.33#ibcon#about to write, iclass 38, count 2 2006.257.16:19:16.33#ibcon#wrote, iclass 38, count 2 2006.257.16:19:16.33#ibcon#about to read 3, iclass 38, count 2 2006.257.16:19:16.36#ibcon#read 3, iclass 38, count 2 2006.257.16:19:16.36#ibcon#about to read 4, iclass 38, count 2 2006.257.16:19:16.36#ibcon#read 4, iclass 38, count 2 2006.257.16:19:16.36#ibcon#about to read 5, iclass 38, count 2 2006.257.16:19:16.36#ibcon#read 5, iclass 38, count 2 2006.257.16:19:16.36#ibcon#about to read 6, iclass 38, count 2 2006.257.16:19:16.36#ibcon#read 6, iclass 38, count 2 2006.257.16:19:16.36#ibcon#end of sib2, iclass 38, count 2 2006.257.16:19:16.36#ibcon#*after write, iclass 38, count 2 2006.257.16:19:16.36#ibcon#*before return 0, iclass 38, count 2 2006.257.16:19:16.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:19:16.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:19:16.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.16:19:16.36#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:16.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:19:16.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:19:16.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:19:16.48#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:19:16.48#ibcon#first serial, iclass 38, count 0 2006.257.16:19:16.48#ibcon#enter sib2, iclass 38, count 0 2006.257.16:19:16.48#ibcon#flushed, iclass 38, count 0 2006.257.16:19:16.48#ibcon#about to write, iclass 38, count 0 2006.257.16:19:16.48#ibcon#wrote, iclass 38, count 0 2006.257.16:19:16.48#ibcon#about to read 3, iclass 38, count 0 2006.257.16:19:16.50#ibcon#read 3, iclass 38, count 0 2006.257.16:19:16.50#ibcon#about to read 4, iclass 38, count 0 2006.257.16:19:16.50#ibcon#read 4, iclass 38, count 0 2006.257.16:19:16.50#ibcon#about to read 5, iclass 38, count 0 2006.257.16:19:16.50#ibcon#read 5, iclass 38, count 0 2006.257.16:19:16.50#ibcon#about to read 6, iclass 38, count 0 2006.257.16:19:16.50#ibcon#read 6, iclass 38, count 0 2006.257.16:19:16.50#ibcon#end of sib2, iclass 38, count 0 2006.257.16:19:16.50#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:19:16.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:19:16.50#ibcon#[27=USB\r\n] 2006.257.16:19:16.50#ibcon#*before write, iclass 38, count 0 2006.257.16:19:16.50#ibcon#enter sib2, iclass 38, count 0 2006.257.16:19:16.50#ibcon#flushed, iclass 38, count 0 2006.257.16:19:16.50#ibcon#about to write, iclass 38, count 0 2006.257.16:19:16.50#ibcon#wrote, iclass 38, count 0 2006.257.16:19:16.50#ibcon#about to read 3, iclass 38, count 0 2006.257.16:19:16.53#ibcon#read 3, iclass 38, count 0 2006.257.16:19:16.53#ibcon#about to read 4, iclass 38, count 0 2006.257.16:19:16.53#ibcon#read 4, iclass 38, count 0 2006.257.16:19:16.53#ibcon#about to read 5, iclass 38, count 0 2006.257.16:19:16.53#ibcon#read 5, iclass 38, count 0 2006.257.16:19:16.53#ibcon#about to read 6, iclass 38, count 0 2006.257.16:19:16.53#ibcon#read 6, iclass 38, count 0 2006.257.16:19:16.53#ibcon#end of sib2, iclass 38, count 0 2006.257.16:19:16.53#ibcon#*after write, iclass 38, count 0 2006.257.16:19:16.53#ibcon#*before return 0, iclass 38, count 0 2006.257.16:19:16.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:19:16.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:19:16.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:19:16.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:19:16.53$vck44/vblo=8,744.99 2006.257.16:19:16.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.16:19:16.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.16:19:16.53#ibcon#ireg 17 cls_cnt 0 2006.257.16:19:16.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:19:16.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:19:16.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:19:16.53#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:19:16.53#ibcon#first serial, iclass 40, count 0 2006.257.16:19:16.53#ibcon#enter sib2, iclass 40, count 0 2006.257.16:19:16.53#ibcon#flushed, iclass 40, count 0 2006.257.16:19:16.53#ibcon#about to write, iclass 40, count 0 2006.257.16:19:16.53#ibcon#wrote, iclass 40, count 0 2006.257.16:19:16.53#ibcon#about to read 3, iclass 40, count 0 2006.257.16:19:16.55#ibcon#read 3, iclass 40, count 0 2006.257.16:19:16.55#ibcon#about to read 4, iclass 40, count 0 2006.257.16:19:16.55#ibcon#read 4, iclass 40, count 0 2006.257.16:19:16.55#ibcon#about to read 5, iclass 40, count 0 2006.257.16:19:16.55#ibcon#read 5, iclass 40, count 0 2006.257.16:19:16.55#ibcon#about to read 6, iclass 40, count 0 2006.257.16:19:16.55#ibcon#read 6, iclass 40, count 0 2006.257.16:19:16.55#ibcon#end of sib2, iclass 40, count 0 2006.257.16:19:16.55#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:19:16.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:19:16.55#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:19:16.55#ibcon#*before write, iclass 40, count 0 2006.257.16:19:16.55#ibcon#enter sib2, iclass 40, count 0 2006.257.16:19:16.55#ibcon#flushed, iclass 40, count 0 2006.257.16:19:16.55#ibcon#about to write, iclass 40, count 0 2006.257.16:19:16.55#ibcon#wrote, iclass 40, count 0 2006.257.16:19:16.55#ibcon#about to read 3, iclass 40, count 0 2006.257.16:19:16.59#ibcon#read 3, iclass 40, count 0 2006.257.16:19:16.59#ibcon#about to read 4, iclass 40, count 0 2006.257.16:19:16.59#ibcon#read 4, iclass 40, count 0 2006.257.16:19:16.59#ibcon#about to read 5, iclass 40, count 0 2006.257.16:19:16.59#ibcon#read 5, iclass 40, count 0 2006.257.16:19:16.59#ibcon#about to read 6, iclass 40, count 0 2006.257.16:19:16.59#ibcon#read 6, iclass 40, count 0 2006.257.16:19:16.59#ibcon#end of sib2, iclass 40, count 0 2006.257.16:19:16.59#ibcon#*after write, iclass 40, count 0 2006.257.16:19:16.59#ibcon#*before return 0, iclass 40, count 0 2006.257.16:19:16.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:19:16.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:19:16.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:19:16.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:19:16.59$vck44/vb=8,4 2006.257.16:19:16.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.16:19:16.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.16:19:16.59#ibcon#ireg 11 cls_cnt 2 2006.257.16:19:16.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:19:16.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:19:16.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:19:16.65#ibcon#enter wrdev, iclass 4, count 2 2006.257.16:19:16.65#ibcon#first serial, iclass 4, count 2 2006.257.16:19:16.65#ibcon#enter sib2, iclass 4, count 2 2006.257.16:19:16.65#ibcon#flushed, iclass 4, count 2 2006.257.16:19:16.65#ibcon#about to write, iclass 4, count 2 2006.257.16:19:16.65#ibcon#wrote, iclass 4, count 2 2006.257.16:19:16.65#ibcon#about to read 3, iclass 4, count 2 2006.257.16:19:16.67#ibcon#read 3, iclass 4, count 2 2006.257.16:19:16.67#ibcon#about to read 4, iclass 4, count 2 2006.257.16:19:16.67#ibcon#read 4, iclass 4, count 2 2006.257.16:19:16.67#ibcon#about to read 5, iclass 4, count 2 2006.257.16:19:16.67#ibcon#read 5, iclass 4, count 2 2006.257.16:19:16.67#ibcon#about to read 6, iclass 4, count 2 2006.257.16:19:16.67#ibcon#read 6, iclass 4, count 2 2006.257.16:19:16.67#ibcon#end of sib2, iclass 4, count 2 2006.257.16:19:16.67#ibcon#*mode == 0, iclass 4, count 2 2006.257.16:19:16.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.16:19:16.67#ibcon#[27=AT08-04\r\n] 2006.257.16:19:16.67#ibcon#*before write, iclass 4, count 2 2006.257.16:19:16.67#ibcon#enter sib2, iclass 4, count 2 2006.257.16:19:16.67#ibcon#flushed, iclass 4, count 2 2006.257.16:19:16.67#ibcon#about to write, iclass 4, count 2 2006.257.16:19:16.67#ibcon#wrote, iclass 4, count 2 2006.257.16:19:16.67#ibcon#about to read 3, iclass 4, count 2 2006.257.16:19:16.70#ibcon#read 3, iclass 4, count 2 2006.257.16:19:16.70#ibcon#about to read 4, iclass 4, count 2 2006.257.16:19:16.70#ibcon#read 4, iclass 4, count 2 2006.257.16:19:16.70#ibcon#about to read 5, iclass 4, count 2 2006.257.16:19:16.70#ibcon#read 5, iclass 4, count 2 2006.257.16:19:16.70#ibcon#about to read 6, iclass 4, count 2 2006.257.16:19:16.70#ibcon#read 6, iclass 4, count 2 2006.257.16:19:16.70#ibcon#end of sib2, iclass 4, count 2 2006.257.16:19:16.70#ibcon#*after write, iclass 4, count 2 2006.257.16:19:16.70#ibcon#*before return 0, iclass 4, count 2 2006.257.16:19:16.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:19:16.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:19:16.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.16:19:16.70#ibcon#ireg 7 cls_cnt 0 2006.257.16:19:16.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:19:16.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:19:16.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:19:16.82#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:19:16.82#ibcon#first serial, iclass 4, count 0 2006.257.16:19:16.82#ibcon#enter sib2, iclass 4, count 0 2006.257.16:19:16.82#ibcon#flushed, iclass 4, count 0 2006.257.16:19:16.82#ibcon#about to write, iclass 4, count 0 2006.257.16:19:16.82#ibcon#wrote, iclass 4, count 0 2006.257.16:19:16.82#ibcon#about to read 3, iclass 4, count 0 2006.257.16:19:16.84#ibcon#read 3, iclass 4, count 0 2006.257.16:19:16.84#ibcon#about to read 4, iclass 4, count 0 2006.257.16:19:16.84#ibcon#read 4, iclass 4, count 0 2006.257.16:19:16.84#ibcon#about to read 5, iclass 4, count 0 2006.257.16:19:16.84#ibcon#read 5, iclass 4, count 0 2006.257.16:19:16.84#ibcon#about to read 6, iclass 4, count 0 2006.257.16:19:16.84#ibcon#read 6, iclass 4, count 0 2006.257.16:19:16.84#ibcon#end of sib2, iclass 4, count 0 2006.257.16:19:16.84#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:19:16.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:19:16.84#ibcon#[27=USB\r\n] 2006.257.16:19:16.84#ibcon#*before write, iclass 4, count 0 2006.257.16:19:16.84#ibcon#enter sib2, iclass 4, count 0 2006.257.16:19:16.84#ibcon#flushed, iclass 4, count 0 2006.257.16:19:16.84#ibcon#about to write, iclass 4, count 0 2006.257.16:19:16.84#ibcon#wrote, iclass 4, count 0 2006.257.16:19:16.84#ibcon#about to read 3, iclass 4, count 0 2006.257.16:19:16.87#ibcon#read 3, iclass 4, count 0 2006.257.16:19:16.87#ibcon#about to read 4, iclass 4, count 0 2006.257.16:19:16.87#ibcon#read 4, iclass 4, count 0 2006.257.16:19:16.87#ibcon#about to read 5, iclass 4, count 0 2006.257.16:19:16.87#ibcon#read 5, iclass 4, count 0 2006.257.16:19:16.87#ibcon#about to read 6, iclass 4, count 0 2006.257.16:19:16.87#ibcon#read 6, iclass 4, count 0 2006.257.16:19:16.87#ibcon#end of sib2, iclass 4, count 0 2006.257.16:19:16.87#ibcon#*after write, iclass 4, count 0 2006.257.16:19:16.87#ibcon#*before return 0, iclass 4, count 0 2006.257.16:19:16.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:19:16.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:19:16.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:19:16.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:19:16.87$vck44/vabw=wide 2006.257.16:19:16.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.16:19:16.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.16:19:16.87#ibcon#ireg 8 cls_cnt 0 2006.257.16:19:16.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:16.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:16.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:16.87#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:19:16.87#ibcon#first serial, iclass 6, count 0 2006.257.16:19:16.87#ibcon#enter sib2, iclass 6, count 0 2006.257.16:19:16.87#ibcon#flushed, iclass 6, count 0 2006.257.16:19:16.87#ibcon#about to write, iclass 6, count 0 2006.257.16:19:16.87#ibcon#wrote, iclass 6, count 0 2006.257.16:19:16.87#ibcon#about to read 3, iclass 6, count 0 2006.257.16:19:16.89#ibcon#read 3, iclass 6, count 0 2006.257.16:19:16.89#ibcon#about to read 4, iclass 6, count 0 2006.257.16:19:16.89#ibcon#read 4, iclass 6, count 0 2006.257.16:19:16.89#ibcon#about to read 5, iclass 6, count 0 2006.257.16:19:16.89#ibcon#read 5, iclass 6, count 0 2006.257.16:19:16.89#ibcon#about to read 6, iclass 6, count 0 2006.257.16:19:16.89#ibcon#read 6, iclass 6, count 0 2006.257.16:19:16.89#ibcon#end of sib2, iclass 6, count 0 2006.257.16:19:16.89#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:19:16.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:19:16.89#ibcon#[25=BW32\r\n] 2006.257.16:19:16.89#ibcon#*before write, iclass 6, count 0 2006.257.16:19:16.89#ibcon#enter sib2, iclass 6, count 0 2006.257.16:19:16.89#ibcon#flushed, iclass 6, count 0 2006.257.16:19:16.89#ibcon#about to write, iclass 6, count 0 2006.257.16:19:16.89#ibcon#wrote, iclass 6, count 0 2006.257.16:19:16.89#ibcon#about to read 3, iclass 6, count 0 2006.257.16:19:16.92#ibcon#read 3, iclass 6, count 0 2006.257.16:19:16.92#ibcon#about to read 4, iclass 6, count 0 2006.257.16:19:16.92#ibcon#read 4, iclass 6, count 0 2006.257.16:19:16.92#ibcon#about to read 5, iclass 6, count 0 2006.257.16:19:16.92#ibcon#read 5, iclass 6, count 0 2006.257.16:19:16.92#ibcon#about to read 6, iclass 6, count 0 2006.257.16:19:16.92#ibcon#read 6, iclass 6, count 0 2006.257.16:19:16.92#ibcon#end of sib2, iclass 6, count 0 2006.257.16:19:16.92#ibcon#*after write, iclass 6, count 0 2006.257.16:19:16.92#ibcon#*before return 0, iclass 6, count 0 2006.257.16:19:16.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:16.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:19:16.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:19:16.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:19:16.92$vck44/vbbw=wide 2006.257.16:19:16.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.16:19:16.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.16:19:16.92#ibcon#ireg 8 cls_cnt 0 2006.257.16:19:16.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:19:16.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:19:16.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:19:16.99#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:19:16.99#ibcon#first serial, iclass 10, count 0 2006.257.16:19:16.99#ibcon#enter sib2, iclass 10, count 0 2006.257.16:19:16.99#ibcon#flushed, iclass 10, count 0 2006.257.16:19:16.99#ibcon#about to write, iclass 10, count 0 2006.257.16:19:16.99#ibcon#wrote, iclass 10, count 0 2006.257.16:19:16.99#ibcon#about to read 3, iclass 10, count 0 2006.257.16:19:17.01#ibcon#read 3, iclass 10, count 0 2006.257.16:19:17.01#ibcon#about to read 4, iclass 10, count 0 2006.257.16:19:17.01#ibcon#read 4, iclass 10, count 0 2006.257.16:19:17.01#ibcon#about to read 5, iclass 10, count 0 2006.257.16:19:17.01#ibcon#read 5, iclass 10, count 0 2006.257.16:19:17.01#ibcon#about to read 6, iclass 10, count 0 2006.257.16:19:17.01#ibcon#read 6, iclass 10, count 0 2006.257.16:19:17.01#ibcon#end of sib2, iclass 10, count 0 2006.257.16:19:17.01#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:19:17.01#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:19:17.01#ibcon#[27=BW32\r\n] 2006.257.16:19:17.01#ibcon#*before write, iclass 10, count 0 2006.257.16:19:17.01#ibcon#enter sib2, iclass 10, count 0 2006.257.16:19:17.01#ibcon#flushed, iclass 10, count 0 2006.257.16:19:17.01#ibcon#about to write, iclass 10, count 0 2006.257.16:19:17.01#ibcon#wrote, iclass 10, count 0 2006.257.16:19:17.01#ibcon#about to read 3, iclass 10, count 0 2006.257.16:19:17.04#ibcon#read 3, iclass 10, count 0 2006.257.16:19:17.04#ibcon#about to read 4, iclass 10, count 0 2006.257.16:19:17.04#ibcon#read 4, iclass 10, count 0 2006.257.16:19:17.04#ibcon#about to read 5, iclass 10, count 0 2006.257.16:19:17.04#ibcon#read 5, iclass 10, count 0 2006.257.16:19:17.04#ibcon#about to read 6, iclass 10, count 0 2006.257.16:19:17.04#ibcon#read 6, iclass 10, count 0 2006.257.16:19:17.04#ibcon#end of sib2, iclass 10, count 0 2006.257.16:19:17.04#ibcon#*after write, iclass 10, count 0 2006.257.16:19:17.04#ibcon#*before return 0, iclass 10, count 0 2006.257.16:19:17.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:19:17.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:19:17.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:19:17.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:19:17.04$setupk4/ifdk4 2006.257.16:19:17.04$ifdk4/lo= 2006.257.16:19:17.04$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:19:17.04$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:19:17.04$ifdk4/patch= 2006.257.16:19:17.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:19:17.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:19:17.05$setupk4/!*+20s 2006.257.16:19:23.73#abcon#<5=/14 1.3 3.3 17.21 971014.0\r\n> 2006.257.16:19:23.75#abcon#{5=INTERFACE CLEAR} 2006.257.16:19:23.81#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:19:24.13#trakl#Source acquired 2006.257.16:19:25.14#flagr#flagr/antenna,acquired 2006.257.16:19:31.56$setupk4/"tpicd 2006.257.16:19:31.56$setupk4/echo=off 2006.257.16:19:31.56$setupk4/xlog=off 2006.257.16:19:31.56:!2006.257.16:23:29 2006.257.16:23:29.00:preob 2006.257.16:23:29.14/onsource/TRACKING 2006.257.16:23:29.14:!2006.257.16:23:39 2006.257.16:23:39.00:"tape 2006.257.16:23:39.00:"st=record 2006.257.16:23:39.00:data_valid=on 2006.257.16:23:39.00:midob 2006.257.16:23:40.14/onsource/TRACKING 2006.257.16:23:40.14/wx/17.17,1014.1,97 2006.257.16:23:40.28/cable/+6.4849E-03 2006.257.16:23:41.37/va/01,08,usb,yes,31,33 2006.257.16:23:41.37/va/02,07,usb,yes,34,34 2006.257.16:23:41.37/va/03,08,usb,yes,30,32 2006.257.16:23:41.37/va/04,07,usb,yes,35,36 2006.257.16:23:41.37/va/05,04,usb,yes,31,31 2006.257.16:23:41.37/va/06,04,usb,yes,34,34 2006.257.16:23:41.37/va/07,04,usb,yes,35,36 2006.257.16:23:41.37/va/08,04,usb,yes,30,36 2006.257.16:23:41.60/valo/01,524.99,yes,locked 2006.257.16:23:41.60/valo/02,534.99,yes,locked 2006.257.16:23:41.60/valo/03,564.99,yes,locked 2006.257.16:23:41.60/valo/04,624.99,yes,locked 2006.257.16:23:41.60/valo/05,734.99,yes,locked 2006.257.16:23:41.60/valo/06,814.99,yes,locked 2006.257.16:23:41.60/valo/07,864.99,yes,locked 2006.257.16:23:41.60/valo/08,884.99,yes,locked 2006.257.16:23:42.69/vb/01,04,usb,yes,49,31 2006.257.16:23:42.69/vb/02,05,usb,yes,32,43 2006.257.16:23:42.69/vb/03,04,usb,yes,31,40 2006.257.16:23:42.69/vb/04,05,usb,yes,30,29 2006.257.16:23:42.69/vb/05,04,usb,yes,27,29 2006.257.16:23:42.69/vb/06,04,usb,yes,31,27 2006.257.16:23:42.69/vb/07,04,usb,yes,31,31 2006.257.16:23:42.69/vb/08,04,usb,yes,29,32 2006.257.16:23:42.92/vblo/01,629.99,yes,locked 2006.257.16:23:42.92/vblo/02,634.99,yes,locked 2006.257.16:23:42.92/vblo/03,649.99,yes,locked 2006.257.16:23:42.92/vblo/04,679.99,yes,locked 2006.257.16:23:42.92/vblo/05,709.99,yes,locked 2006.257.16:23:42.92/vblo/06,719.99,yes,locked 2006.257.16:23:42.92/vblo/07,734.99,yes,locked 2006.257.16:23:42.92/vblo/08,744.99,yes,locked 2006.257.16:23:43.07/vabw/8 2006.257.16:23:43.22/vbbw/8 2006.257.16:23:43.31/xfe/off,on,17.0 2006.257.16:23:43.69/ifatt/23,28,28,28 2006.257.16:23:44.07/fmout-gps/S +4.61E-07 2006.257.16:23:44.11:!2006.257.16:26:29 2006.257.16:26:29.01:data_valid=off 2006.257.16:26:29.02:"et 2006.257.16:26:29.02:!+3s 2006.257.16:26:32.03:"tape 2006.257.16:26:32.04:postob 2006.257.16:26:32.24/cable/+6.4844E-03 2006.257.16:26:32.25/wx/17.15,1014.1,97 2006.257.16:26:32.30/fmout-gps/S +4.62E-07 2006.257.16:26:32.30:scan_name=257-1629,jd0609,110 2006.257.16:26:32.31:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.257.16:26:33.14#flagr#flagr/antenna,new-source 2006.257.16:26:33.15:checkk5 2006.257.16:26:33.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.16:26:33.86/chk_autoobs//k5ts2/ autoobs is running! 2006.257.16:26:34.20/chk_autoobs//k5ts3/ autoobs is running! 2006.257.16:26:34.54/chk_autoobs//k5ts4/ autoobs is running! 2006.257.16:26:34.88/chk_obsdata//k5ts1/T2571623??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.16:26:35.22/chk_obsdata//k5ts2/T2571623??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.16:26:35.55/chk_obsdata//k5ts3/T2571623??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.16:26:35.89/chk_obsdata//k5ts4/T2571623??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.16:26:36.55/k5log//k5ts1_log_newline 2006.257.16:26:37.20/k5log//k5ts2_log_newline 2006.257.16:26:37.85/k5log//k5ts3_log_newline 2006.257.16:26:38.51/k5log//k5ts4_log_newline 2006.257.16:26:38.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.16:26:38.54:setupk4=1 2006.257.16:26:38.54$setupk4/echo=on 2006.257.16:26:38.54$setupk4/pcalon 2006.257.16:26:38.54$pcalon/"no phase cal control is implemented here 2006.257.16:26:38.54$setupk4/"tpicd=stop 2006.257.16:26:38.54$setupk4/"rec=synch_on 2006.257.16:26:38.54$setupk4/"rec_mode=128 2006.257.16:26:38.54$setupk4/!* 2006.257.16:26:38.54$setupk4/recpk4 2006.257.16:26:38.54$recpk4/recpatch= 2006.257.16:26:38.54$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.16:26:38.54$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.16:26:38.54$setupk4/vck44 2006.257.16:26:38.54$vck44/valo=1,524.99 2006.257.16:26:38.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.16:26:38.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.16:26:38.54#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:38.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:38.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:38.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:38.54#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:26:38.54#ibcon#first serial, iclass 38, count 0 2006.257.16:26:38.54#ibcon#enter sib2, iclass 38, count 0 2006.257.16:26:38.54#ibcon#flushed, iclass 38, count 0 2006.257.16:26:38.54#ibcon#about to write, iclass 38, count 0 2006.257.16:26:38.54#ibcon#wrote, iclass 38, count 0 2006.257.16:26:38.54#ibcon#about to read 3, iclass 38, count 0 2006.257.16:26:38.56#ibcon#read 3, iclass 38, count 0 2006.257.16:26:38.56#ibcon#about to read 4, iclass 38, count 0 2006.257.16:26:38.56#ibcon#read 4, iclass 38, count 0 2006.257.16:26:38.56#ibcon#about to read 5, iclass 38, count 0 2006.257.16:26:38.56#ibcon#read 5, iclass 38, count 0 2006.257.16:26:38.56#ibcon#about to read 6, iclass 38, count 0 2006.257.16:26:38.56#ibcon#read 6, iclass 38, count 0 2006.257.16:26:38.56#ibcon#end of sib2, iclass 38, count 0 2006.257.16:26:38.56#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:26:38.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:26:38.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.16:26:38.56#ibcon#*before write, iclass 38, count 0 2006.257.16:26:38.56#ibcon#enter sib2, iclass 38, count 0 2006.257.16:26:38.56#ibcon#flushed, iclass 38, count 0 2006.257.16:26:38.56#ibcon#about to write, iclass 38, count 0 2006.257.16:26:38.56#ibcon#wrote, iclass 38, count 0 2006.257.16:26:38.56#ibcon#about to read 3, iclass 38, count 0 2006.257.16:26:38.61#ibcon#read 3, iclass 38, count 0 2006.257.16:26:38.61#ibcon#about to read 4, iclass 38, count 0 2006.257.16:26:38.61#ibcon#read 4, iclass 38, count 0 2006.257.16:26:38.61#ibcon#about to read 5, iclass 38, count 0 2006.257.16:26:38.61#ibcon#read 5, iclass 38, count 0 2006.257.16:26:38.61#ibcon#about to read 6, iclass 38, count 0 2006.257.16:26:38.61#ibcon#read 6, iclass 38, count 0 2006.257.16:26:38.61#ibcon#end of sib2, iclass 38, count 0 2006.257.16:26:38.61#ibcon#*after write, iclass 38, count 0 2006.257.16:26:38.61#ibcon#*before return 0, iclass 38, count 0 2006.257.16:26:38.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:38.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:38.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:26:38.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:26:38.61$vck44/va=1,8 2006.257.16:26:38.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.16:26:38.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.16:26:38.61#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:38.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:38.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:38.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:38.61#ibcon#enter wrdev, iclass 40, count 2 2006.257.16:26:38.61#ibcon#first serial, iclass 40, count 2 2006.257.16:26:38.61#ibcon#enter sib2, iclass 40, count 2 2006.257.16:26:38.61#ibcon#flushed, iclass 40, count 2 2006.257.16:26:38.61#ibcon#about to write, iclass 40, count 2 2006.257.16:26:38.61#ibcon#wrote, iclass 40, count 2 2006.257.16:26:38.61#ibcon#about to read 3, iclass 40, count 2 2006.257.16:26:38.63#ibcon#read 3, iclass 40, count 2 2006.257.16:26:38.63#ibcon#about to read 4, iclass 40, count 2 2006.257.16:26:38.63#ibcon#read 4, iclass 40, count 2 2006.257.16:26:38.63#ibcon#about to read 5, iclass 40, count 2 2006.257.16:26:38.63#ibcon#read 5, iclass 40, count 2 2006.257.16:26:38.63#ibcon#about to read 6, iclass 40, count 2 2006.257.16:26:38.63#ibcon#read 6, iclass 40, count 2 2006.257.16:26:38.63#ibcon#end of sib2, iclass 40, count 2 2006.257.16:26:38.63#ibcon#*mode == 0, iclass 40, count 2 2006.257.16:26:38.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.16:26:38.63#ibcon#[25=AT01-08\r\n] 2006.257.16:26:38.63#ibcon#*before write, iclass 40, count 2 2006.257.16:26:38.63#ibcon#enter sib2, iclass 40, count 2 2006.257.16:26:38.63#ibcon#flushed, iclass 40, count 2 2006.257.16:26:38.63#ibcon#about to write, iclass 40, count 2 2006.257.16:26:38.63#ibcon#wrote, iclass 40, count 2 2006.257.16:26:38.63#ibcon#about to read 3, iclass 40, count 2 2006.257.16:26:38.66#ibcon#read 3, iclass 40, count 2 2006.257.16:26:38.66#ibcon#about to read 4, iclass 40, count 2 2006.257.16:26:38.66#ibcon#read 4, iclass 40, count 2 2006.257.16:26:38.66#ibcon#about to read 5, iclass 40, count 2 2006.257.16:26:38.66#ibcon#read 5, iclass 40, count 2 2006.257.16:26:38.66#ibcon#about to read 6, iclass 40, count 2 2006.257.16:26:38.66#ibcon#read 6, iclass 40, count 2 2006.257.16:26:38.66#ibcon#end of sib2, iclass 40, count 2 2006.257.16:26:38.66#ibcon#*after write, iclass 40, count 2 2006.257.16:26:38.66#ibcon#*before return 0, iclass 40, count 2 2006.257.16:26:38.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:38.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:38.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.16:26:38.66#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:38.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:38.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:38.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:38.78#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:26:38.78#ibcon#first serial, iclass 40, count 0 2006.257.16:26:38.78#ibcon#enter sib2, iclass 40, count 0 2006.257.16:26:38.78#ibcon#flushed, iclass 40, count 0 2006.257.16:26:38.78#ibcon#about to write, iclass 40, count 0 2006.257.16:26:38.78#ibcon#wrote, iclass 40, count 0 2006.257.16:26:38.78#ibcon#about to read 3, iclass 40, count 0 2006.257.16:26:38.80#ibcon#read 3, iclass 40, count 0 2006.257.16:26:38.80#ibcon#about to read 4, iclass 40, count 0 2006.257.16:26:38.80#ibcon#read 4, iclass 40, count 0 2006.257.16:26:38.80#ibcon#about to read 5, iclass 40, count 0 2006.257.16:26:38.80#ibcon#read 5, iclass 40, count 0 2006.257.16:26:38.80#ibcon#about to read 6, iclass 40, count 0 2006.257.16:26:38.80#ibcon#read 6, iclass 40, count 0 2006.257.16:26:38.80#ibcon#end of sib2, iclass 40, count 0 2006.257.16:26:38.80#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:26:38.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:26:38.80#ibcon#[25=USB\r\n] 2006.257.16:26:38.80#ibcon#*before write, iclass 40, count 0 2006.257.16:26:38.80#ibcon#enter sib2, iclass 40, count 0 2006.257.16:26:38.80#ibcon#flushed, iclass 40, count 0 2006.257.16:26:38.80#ibcon#about to write, iclass 40, count 0 2006.257.16:26:38.80#ibcon#wrote, iclass 40, count 0 2006.257.16:26:38.80#ibcon#about to read 3, iclass 40, count 0 2006.257.16:26:38.83#ibcon#read 3, iclass 40, count 0 2006.257.16:26:38.83#ibcon#about to read 4, iclass 40, count 0 2006.257.16:26:38.83#ibcon#read 4, iclass 40, count 0 2006.257.16:26:38.83#ibcon#about to read 5, iclass 40, count 0 2006.257.16:26:38.83#ibcon#read 5, iclass 40, count 0 2006.257.16:26:38.83#ibcon#about to read 6, iclass 40, count 0 2006.257.16:26:38.83#ibcon#read 6, iclass 40, count 0 2006.257.16:26:38.83#ibcon#end of sib2, iclass 40, count 0 2006.257.16:26:38.83#ibcon#*after write, iclass 40, count 0 2006.257.16:26:38.83#ibcon#*before return 0, iclass 40, count 0 2006.257.16:26:38.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:38.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:38.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:26:38.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:26:38.83$vck44/valo=2,534.99 2006.257.16:26:38.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.16:26:38.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.16:26:38.83#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:38.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:38.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:38.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:38.83#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:26:38.83#ibcon#first serial, iclass 4, count 0 2006.257.16:26:38.83#ibcon#enter sib2, iclass 4, count 0 2006.257.16:26:38.83#ibcon#flushed, iclass 4, count 0 2006.257.16:26:38.83#ibcon#about to write, iclass 4, count 0 2006.257.16:26:38.83#ibcon#wrote, iclass 4, count 0 2006.257.16:26:38.83#ibcon#about to read 3, iclass 4, count 0 2006.257.16:26:38.85#ibcon#read 3, iclass 4, count 0 2006.257.16:26:38.85#ibcon#about to read 4, iclass 4, count 0 2006.257.16:26:38.85#ibcon#read 4, iclass 4, count 0 2006.257.16:26:38.85#ibcon#about to read 5, iclass 4, count 0 2006.257.16:26:38.85#ibcon#read 5, iclass 4, count 0 2006.257.16:26:38.85#ibcon#about to read 6, iclass 4, count 0 2006.257.16:26:38.85#ibcon#read 6, iclass 4, count 0 2006.257.16:26:38.85#ibcon#end of sib2, iclass 4, count 0 2006.257.16:26:38.85#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:26:38.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:26:38.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.16:26:38.85#ibcon#*before write, iclass 4, count 0 2006.257.16:26:38.85#ibcon#enter sib2, iclass 4, count 0 2006.257.16:26:38.85#ibcon#flushed, iclass 4, count 0 2006.257.16:26:38.85#ibcon#about to write, iclass 4, count 0 2006.257.16:26:38.85#ibcon#wrote, iclass 4, count 0 2006.257.16:26:38.85#ibcon#about to read 3, iclass 4, count 0 2006.257.16:26:38.89#ibcon#read 3, iclass 4, count 0 2006.257.16:26:38.89#ibcon#about to read 4, iclass 4, count 0 2006.257.16:26:38.89#ibcon#read 4, iclass 4, count 0 2006.257.16:26:38.89#ibcon#about to read 5, iclass 4, count 0 2006.257.16:26:38.89#ibcon#read 5, iclass 4, count 0 2006.257.16:26:38.89#ibcon#about to read 6, iclass 4, count 0 2006.257.16:26:38.89#ibcon#read 6, iclass 4, count 0 2006.257.16:26:38.89#ibcon#end of sib2, iclass 4, count 0 2006.257.16:26:38.89#ibcon#*after write, iclass 4, count 0 2006.257.16:26:38.89#ibcon#*before return 0, iclass 4, count 0 2006.257.16:26:38.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:38.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:38.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:26:38.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:26:38.89$vck44/va=2,7 2006.257.16:26:38.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.16:26:38.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.16:26:38.89#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:38.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:38.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:38.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:38.95#ibcon#enter wrdev, iclass 6, count 2 2006.257.16:26:38.95#ibcon#first serial, iclass 6, count 2 2006.257.16:26:38.95#ibcon#enter sib2, iclass 6, count 2 2006.257.16:26:38.95#ibcon#flushed, iclass 6, count 2 2006.257.16:26:38.95#ibcon#about to write, iclass 6, count 2 2006.257.16:26:38.95#ibcon#wrote, iclass 6, count 2 2006.257.16:26:38.95#ibcon#about to read 3, iclass 6, count 2 2006.257.16:26:38.97#ibcon#read 3, iclass 6, count 2 2006.257.16:26:38.97#ibcon#about to read 4, iclass 6, count 2 2006.257.16:26:38.97#ibcon#read 4, iclass 6, count 2 2006.257.16:26:38.97#ibcon#about to read 5, iclass 6, count 2 2006.257.16:26:38.97#ibcon#read 5, iclass 6, count 2 2006.257.16:26:38.97#ibcon#about to read 6, iclass 6, count 2 2006.257.16:26:38.97#ibcon#read 6, iclass 6, count 2 2006.257.16:26:38.97#ibcon#end of sib2, iclass 6, count 2 2006.257.16:26:38.97#ibcon#*mode == 0, iclass 6, count 2 2006.257.16:26:38.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.16:26:38.97#ibcon#[25=AT02-07\r\n] 2006.257.16:26:38.97#ibcon#*before write, iclass 6, count 2 2006.257.16:26:38.97#ibcon#enter sib2, iclass 6, count 2 2006.257.16:26:38.97#ibcon#flushed, iclass 6, count 2 2006.257.16:26:38.97#ibcon#about to write, iclass 6, count 2 2006.257.16:26:38.97#ibcon#wrote, iclass 6, count 2 2006.257.16:26:38.97#ibcon#about to read 3, iclass 6, count 2 2006.257.16:26:39.00#ibcon#read 3, iclass 6, count 2 2006.257.16:26:39.00#ibcon#about to read 4, iclass 6, count 2 2006.257.16:26:39.00#ibcon#read 4, iclass 6, count 2 2006.257.16:26:39.00#ibcon#about to read 5, iclass 6, count 2 2006.257.16:26:39.00#ibcon#read 5, iclass 6, count 2 2006.257.16:26:39.00#ibcon#about to read 6, iclass 6, count 2 2006.257.16:26:39.00#ibcon#read 6, iclass 6, count 2 2006.257.16:26:39.00#ibcon#end of sib2, iclass 6, count 2 2006.257.16:26:39.00#ibcon#*after write, iclass 6, count 2 2006.257.16:26:39.00#ibcon#*before return 0, iclass 6, count 2 2006.257.16:26:39.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:39.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:39.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.16:26:39.00#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:39.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:39.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:39.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:39.12#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:26:39.12#ibcon#first serial, iclass 6, count 0 2006.257.16:26:39.12#ibcon#enter sib2, iclass 6, count 0 2006.257.16:26:39.12#ibcon#flushed, iclass 6, count 0 2006.257.16:26:39.12#ibcon#about to write, iclass 6, count 0 2006.257.16:26:39.12#ibcon#wrote, iclass 6, count 0 2006.257.16:26:39.12#ibcon#about to read 3, iclass 6, count 0 2006.257.16:26:39.14#ibcon#read 3, iclass 6, count 0 2006.257.16:26:39.14#ibcon#about to read 4, iclass 6, count 0 2006.257.16:26:39.14#ibcon#read 4, iclass 6, count 0 2006.257.16:26:39.14#ibcon#about to read 5, iclass 6, count 0 2006.257.16:26:39.14#ibcon#read 5, iclass 6, count 0 2006.257.16:26:39.14#ibcon#about to read 6, iclass 6, count 0 2006.257.16:26:39.14#ibcon#read 6, iclass 6, count 0 2006.257.16:26:39.14#ibcon#end of sib2, iclass 6, count 0 2006.257.16:26:39.14#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:26:39.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:26:39.14#ibcon#[25=USB\r\n] 2006.257.16:26:39.14#ibcon#*before write, iclass 6, count 0 2006.257.16:26:39.14#ibcon#enter sib2, iclass 6, count 0 2006.257.16:26:39.14#ibcon#flushed, iclass 6, count 0 2006.257.16:26:39.14#ibcon#about to write, iclass 6, count 0 2006.257.16:26:39.14#ibcon#wrote, iclass 6, count 0 2006.257.16:26:39.14#ibcon#about to read 3, iclass 6, count 0 2006.257.16:26:39.17#ibcon#read 3, iclass 6, count 0 2006.257.16:26:39.17#ibcon#about to read 4, iclass 6, count 0 2006.257.16:26:39.17#ibcon#read 4, iclass 6, count 0 2006.257.16:26:39.17#ibcon#about to read 5, iclass 6, count 0 2006.257.16:26:39.17#ibcon#read 5, iclass 6, count 0 2006.257.16:26:39.17#ibcon#about to read 6, iclass 6, count 0 2006.257.16:26:39.17#ibcon#read 6, iclass 6, count 0 2006.257.16:26:39.17#ibcon#end of sib2, iclass 6, count 0 2006.257.16:26:39.17#ibcon#*after write, iclass 6, count 0 2006.257.16:26:39.17#ibcon#*before return 0, iclass 6, count 0 2006.257.16:26:39.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:39.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:39.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:26:39.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:26:39.17$vck44/valo=3,564.99 2006.257.16:26:39.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.16:26:39.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.16:26:39.17#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:39.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:39.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:39.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:39.17#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:26:39.17#ibcon#first serial, iclass 10, count 0 2006.257.16:26:39.17#ibcon#enter sib2, iclass 10, count 0 2006.257.16:26:39.17#ibcon#flushed, iclass 10, count 0 2006.257.16:26:39.17#ibcon#about to write, iclass 10, count 0 2006.257.16:26:39.17#ibcon#wrote, iclass 10, count 0 2006.257.16:26:39.17#ibcon#about to read 3, iclass 10, count 0 2006.257.16:26:39.19#ibcon#read 3, iclass 10, count 0 2006.257.16:26:39.19#ibcon#about to read 4, iclass 10, count 0 2006.257.16:26:39.19#ibcon#read 4, iclass 10, count 0 2006.257.16:26:39.19#ibcon#about to read 5, iclass 10, count 0 2006.257.16:26:39.19#ibcon#read 5, iclass 10, count 0 2006.257.16:26:39.19#ibcon#about to read 6, iclass 10, count 0 2006.257.16:26:39.19#ibcon#read 6, iclass 10, count 0 2006.257.16:26:39.19#ibcon#end of sib2, iclass 10, count 0 2006.257.16:26:39.19#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:26:39.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:26:39.19#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.16:26:39.19#ibcon#*before write, iclass 10, count 0 2006.257.16:26:39.19#ibcon#enter sib2, iclass 10, count 0 2006.257.16:26:39.19#ibcon#flushed, iclass 10, count 0 2006.257.16:26:39.19#ibcon#about to write, iclass 10, count 0 2006.257.16:26:39.19#ibcon#wrote, iclass 10, count 0 2006.257.16:26:39.19#ibcon#about to read 3, iclass 10, count 0 2006.257.16:26:39.23#ibcon#read 3, iclass 10, count 0 2006.257.16:26:39.23#ibcon#about to read 4, iclass 10, count 0 2006.257.16:26:39.23#ibcon#read 4, iclass 10, count 0 2006.257.16:26:39.23#ibcon#about to read 5, iclass 10, count 0 2006.257.16:26:39.23#ibcon#read 5, iclass 10, count 0 2006.257.16:26:39.23#ibcon#about to read 6, iclass 10, count 0 2006.257.16:26:39.23#ibcon#read 6, iclass 10, count 0 2006.257.16:26:39.23#ibcon#end of sib2, iclass 10, count 0 2006.257.16:26:39.23#ibcon#*after write, iclass 10, count 0 2006.257.16:26:39.23#ibcon#*before return 0, iclass 10, count 0 2006.257.16:26:39.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:39.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:39.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:26:39.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:26:39.23$vck44/va=3,8 2006.257.16:26:39.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.16:26:39.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.16:26:39.23#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:39.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:39.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:39.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:39.29#ibcon#enter wrdev, iclass 12, count 2 2006.257.16:26:39.29#ibcon#first serial, iclass 12, count 2 2006.257.16:26:39.29#ibcon#enter sib2, iclass 12, count 2 2006.257.16:26:39.29#ibcon#flushed, iclass 12, count 2 2006.257.16:26:39.29#ibcon#about to write, iclass 12, count 2 2006.257.16:26:39.29#ibcon#wrote, iclass 12, count 2 2006.257.16:26:39.29#ibcon#about to read 3, iclass 12, count 2 2006.257.16:26:39.31#ibcon#read 3, iclass 12, count 2 2006.257.16:26:39.31#ibcon#about to read 4, iclass 12, count 2 2006.257.16:26:39.31#ibcon#read 4, iclass 12, count 2 2006.257.16:26:39.31#ibcon#about to read 5, iclass 12, count 2 2006.257.16:26:39.31#ibcon#read 5, iclass 12, count 2 2006.257.16:26:39.31#ibcon#about to read 6, iclass 12, count 2 2006.257.16:26:39.31#ibcon#read 6, iclass 12, count 2 2006.257.16:26:39.31#ibcon#end of sib2, iclass 12, count 2 2006.257.16:26:39.31#ibcon#*mode == 0, iclass 12, count 2 2006.257.16:26:39.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.16:26:39.31#ibcon#[25=AT03-08\r\n] 2006.257.16:26:39.31#ibcon#*before write, iclass 12, count 2 2006.257.16:26:39.31#ibcon#enter sib2, iclass 12, count 2 2006.257.16:26:39.31#ibcon#flushed, iclass 12, count 2 2006.257.16:26:39.31#ibcon#about to write, iclass 12, count 2 2006.257.16:26:39.31#ibcon#wrote, iclass 12, count 2 2006.257.16:26:39.31#ibcon#about to read 3, iclass 12, count 2 2006.257.16:26:39.34#ibcon#read 3, iclass 12, count 2 2006.257.16:26:39.34#ibcon#about to read 4, iclass 12, count 2 2006.257.16:26:39.34#ibcon#read 4, iclass 12, count 2 2006.257.16:26:39.34#ibcon#about to read 5, iclass 12, count 2 2006.257.16:26:39.34#ibcon#read 5, iclass 12, count 2 2006.257.16:26:39.34#ibcon#about to read 6, iclass 12, count 2 2006.257.16:26:39.34#ibcon#read 6, iclass 12, count 2 2006.257.16:26:39.34#ibcon#end of sib2, iclass 12, count 2 2006.257.16:26:39.34#ibcon#*after write, iclass 12, count 2 2006.257.16:26:39.34#ibcon#*before return 0, iclass 12, count 2 2006.257.16:26:39.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:39.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:39.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.16:26:39.34#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:39.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:39.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:39.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:39.46#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:26:39.46#ibcon#first serial, iclass 12, count 0 2006.257.16:26:39.46#ibcon#enter sib2, iclass 12, count 0 2006.257.16:26:39.46#ibcon#flushed, iclass 12, count 0 2006.257.16:26:39.46#ibcon#about to write, iclass 12, count 0 2006.257.16:26:39.46#ibcon#wrote, iclass 12, count 0 2006.257.16:26:39.46#ibcon#about to read 3, iclass 12, count 0 2006.257.16:26:39.48#ibcon#read 3, iclass 12, count 0 2006.257.16:26:39.48#ibcon#about to read 4, iclass 12, count 0 2006.257.16:26:39.48#ibcon#read 4, iclass 12, count 0 2006.257.16:26:39.48#ibcon#about to read 5, iclass 12, count 0 2006.257.16:26:39.48#ibcon#read 5, iclass 12, count 0 2006.257.16:26:39.48#ibcon#about to read 6, iclass 12, count 0 2006.257.16:26:39.48#ibcon#read 6, iclass 12, count 0 2006.257.16:26:39.48#ibcon#end of sib2, iclass 12, count 0 2006.257.16:26:39.48#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:26:39.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:26:39.48#ibcon#[25=USB\r\n] 2006.257.16:26:39.48#ibcon#*before write, iclass 12, count 0 2006.257.16:26:39.48#ibcon#enter sib2, iclass 12, count 0 2006.257.16:26:39.48#ibcon#flushed, iclass 12, count 0 2006.257.16:26:39.48#ibcon#about to write, iclass 12, count 0 2006.257.16:26:39.48#ibcon#wrote, iclass 12, count 0 2006.257.16:26:39.48#ibcon#about to read 3, iclass 12, count 0 2006.257.16:26:39.51#ibcon#read 3, iclass 12, count 0 2006.257.16:26:39.51#ibcon#about to read 4, iclass 12, count 0 2006.257.16:26:39.51#ibcon#read 4, iclass 12, count 0 2006.257.16:26:39.51#ibcon#about to read 5, iclass 12, count 0 2006.257.16:26:39.51#ibcon#read 5, iclass 12, count 0 2006.257.16:26:39.51#ibcon#about to read 6, iclass 12, count 0 2006.257.16:26:39.51#ibcon#read 6, iclass 12, count 0 2006.257.16:26:39.51#ibcon#end of sib2, iclass 12, count 0 2006.257.16:26:39.51#ibcon#*after write, iclass 12, count 0 2006.257.16:26:39.51#ibcon#*before return 0, iclass 12, count 0 2006.257.16:26:39.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:39.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:39.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:26:39.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:26:39.51$vck44/valo=4,624.99 2006.257.16:26:39.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.16:26:39.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.16:26:39.51#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:39.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:39.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:39.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:39.51#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:26:39.51#ibcon#first serial, iclass 14, count 0 2006.257.16:26:39.51#ibcon#enter sib2, iclass 14, count 0 2006.257.16:26:39.51#ibcon#flushed, iclass 14, count 0 2006.257.16:26:39.51#ibcon#about to write, iclass 14, count 0 2006.257.16:26:39.51#ibcon#wrote, iclass 14, count 0 2006.257.16:26:39.51#ibcon#about to read 3, iclass 14, count 0 2006.257.16:26:39.53#ibcon#read 3, iclass 14, count 0 2006.257.16:26:39.53#ibcon#about to read 4, iclass 14, count 0 2006.257.16:26:39.53#ibcon#read 4, iclass 14, count 0 2006.257.16:26:39.53#ibcon#about to read 5, iclass 14, count 0 2006.257.16:26:39.53#ibcon#read 5, iclass 14, count 0 2006.257.16:26:39.53#ibcon#about to read 6, iclass 14, count 0 2006.257.16:26:39.53#ibcon#read 6, iclass 14, count 0 2006.257.16:26:39.53#ibcon#end of sib2, iclass 14, count 0 2006.257.16:26:39.53#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:26:39.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:26:39.53#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.16:26:39.53#ibcon#*before write, iclass 14, count 0 2006.257.16:26:39.53#ibcon#enter sib2, iclass 14, count 0 2006.257.16:26:39.53#ibcon#flushed, iclass 14, count 0 2006.257.16:26:39.53#ibcon#about to write, iclass 14, count 0 2006.257.16:26:39.53#ibcon#wrote, iclass 14, count 0 2006.257.16:26:39.53#ibcon#about to read 3, iclass 14, count 0 2006.257.16:26:39.57#ibcon#read 3, iclass 14, count 0 2006.257.16:26:39.57#ibcon#about to read 4, iclass 14, count 0 2006.257.16:26:39.57#ibcon#read 4, iclass 14, count 0 2006.257.16:26:39.57#ibcon#about to read 5, iclass 14, count 0 2006.257.16:26:39.57#ibcon#read 5, iclass 14, count 0 2006.257.16:26:39.57#ibcon#about to read 6, iclass 14, count 0 2006.257.16:26:39.57#ibcon#read 6, iclass 14, count 0 2006.257.16:26:39.57#ibcon#end of sib2, iclass 14, count 0 2006.257.16:26:39.57#ibcon#*after write, iclass 14, count 0 2006.257.16:26:39.57#ibcon#*before return 0, iclass 14, count 0 2006.257.16:26:39.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:39.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:39.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:26:39.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:26:39.57$vck44/va=4,7 2006.257.16:26:39.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.16:26:39.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.16:26:39.57#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:39.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:39.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:39.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:39.63#ibcon#enter wrdev, iclass 16, count 2 2006.257.16:26:39.63#ibcon#first serial, iclass 16, count 2 2006.257.16:26:39.63#ibcon#enter sib2, iclass 16, count 2 2006.257.16:26:39.63#ibcon#flushed, iclass 16, count 2 2006.257.16:26:39.63#ibcon#about to write, iclass 16, count 2 2006.257.16:26:39.63#ibcon#wrote, iclass 16, count 2 2006.257.16:26:39.63#ibcon#about to read 3, iclass 16, count 2 2006.257.16:26:39.65#ibcon#read 3, iclass 16, count 2 2006.257.16:26:39.65#ibcon#about to read 4, iclass 16, count 2 2006.257.16:26:39.65#ibcon#read 4, iclass 16, count 2 2006.257.16:26:39.65#ibcon#about to read 5, iclass 16, count 2 2006.257.16:26:39.65#ibcon#read 5, iclass 16, count 2 2006.257.16:26:39.65#ibcon#about to read 6, iclass 16, count 2 2006.257.16:26:39.65#ibcon#read 6, iclass 16, count 2 2006.257.16:26:39.65#ibcon#end of sib2, iclass 16, count 2 2006.257.16:26:39.65#ibcon#*mode == 0, iclass 16, count 2 2006.257.16:26:39.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.16:26:39.65#ibcon#[25=AT04-07\r\n] 2006.257.16:26:39.65#ibcon#*before write, iclass 16, count 2 2006.257.16:26:39.65#ibcon#enter sib2, iclass 16, count 2 2006.257.16:26:39.65#ibcon#flushed, iclass 16, count 2 2006.257.16:26:39.65#ibcon#about to write, iclass 16, count 2 2006.257.16:26:39.65#ibcon#wrote, iclass 16, count 2 2006.257.16:26:39.65#ibcon#about to read 3, iclass 16, count 2 2006.257.16:26:39.68#ibcon#read 3, iclass 16, count 2 2006.257.16:26:39.68#ibcon#about to read 4, iclass 16, count 2 2006.257.16:26:39.68#ibcon#read 4, iclass 16, count 2 2006.257.16:26:39.68#ibcon#about to read 5, iclass 16, count 2 2006.257.16:26:39.68#ibcon#read 5, iclass 16, count 2 2006.257.16:26:39.68#ibcon#about to read 6, iclass 16, count 2 2006.257.16:26:39.68#ibcon#read 6, iclass 16, count 2 2006.257.16:26:39.68#ibcon#end of sib2, iclass 16, count 2 2006.257.16:26:39.68#ibcon#*after write, iclass 16, count 2 2006.257.16:26:39.68#ibcon#*before return 0, iclass 16, count 2 2006.257.16:26:39.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:39.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:39.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.16:26:39.68#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:39.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:39.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:39.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:39.80#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:26:39.80#ibcon#first serial, iclass 16, count 0 2006.257.16:26:39.80#ibcon#enter sib2, iclass 16, count 0 2006.257.16:26:39.80#ibcon#flushed, iclass 16, count 0 2006.257.16:26:39.80#ibcon#about to write, iclass 16, count 0 2006.257.16:26:39.80#ibcon#wrote, iclass 16, count 0 2006.257.16:26:39.80#ibcon#about to read 3, iclass 16, count 0 2006.257.16:26:39.82#ibcon#read 3, iclass 16, count 0 2006.257.16:26:39.82#ibcon#about to read 4, iclass 16, count 0 2006.257.16:26:39.82#ibcon#read 4, iclass 16, count 0 2006.257.16:26:39.82#ibcon#about to read 5, iclass 16, count 0 2006.257.16:26:39.82#ibcon#read 5, iclass 16, count 0 2006.257.16:26:39.82#ibcon#about to read 6, iclass 16, count 0 2006.257.16:26:39.82#ibcon#read 6, iclass 16, count 0 2006.257.16:26:39.82#ibcon#end of sib2, iclass 16, count 0 2006.257.16:26:39.82#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:26:39.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:26:39.82#ibcon#[25=USB\r\n] 2006.257.16:26:39.82#ibcon#*before write, iclass 16, count 0 2006.257.16:26:39.82#ibcon#enter sib2, iclass 16, count 0 2006.257.16:26:39.82#ibcon#flushed, iclass 16, count 0 2006.257.16:26:39.82#ibcon#about to write, iclass 16, count 0 2006.257.16:26:39.82#ibcon#wrote, iclass 16, count 0 2006.257.16:26:39.82#ibcon#about to read 3, iclass 16, count 0 2006.257.16:26:39.85#ibcon#read 3, iclass 16, count 0 2006.257.16:26:39.85#ibcon#about to read 4, iclass 16, count 0 2006.257.16:26:39.85#ibcon#read 4, iclass 16, count 0 2006.257.16:26:39.85#ibcon#about to read 5, iclass 16, count 0 2006.257.16:26:39.85#ibcon#read 5, iclass 16, count 0 2006.257.16:26:39.85#ibcon#about to read 6, iclass 16, count 0 2006.257.16:26:39.85#ibcon#read 6, iclass 16, count 0 2006.257.16:26:39.85#ibcon#end of sib2, iclass 16, count 0 2006.257.16:26:39.85#ibcon#*after write, iclass 16, count 0 2006.257.16:26:39.85#ibcon#*before return 0, iclass 16, count 0 2006.257.16:26:39.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:39.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:39.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:26:39.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:26:39.85$vck44/valo=5,734.99 2006.257.16:26:39.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.16:26:39.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.16:26:39.85#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:39.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:39.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:39.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:39.85#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:26:39.85#ibcon#first serial, iclass 18, count 0 2006.257.16:26:39.85#ibcon#enter sib2, iclass 18, count 0 2006.257.16:26:39.85#ibcon#flushed, iclass 18, count 0 2006.257.16:26:39.85#ibcon#about to write, iclass 18, count 0 2006.257.16:26:39.85#ibcon#wrote, iclass 18, count 0 2006.257.16:26:39.85#ibcon#about to read 3, iclass 18, count 0 2006.257.16:26:39.87#ibcon#read 3, iclass 18, count 0 2006.257.16:26:39.87#ibcon#about to read 4, iclass 18, count 0 2006.257.16:26:39.87#ibcon#read 4, iclass 18, count 0 2006.257.16:26:39.87#ibcon#about to read 5, iclass 18, count 0 2006.257.16:26:39.87#ibcon#read 5, iclass 18, count 0 2006.257.16:26:39.87#ibcon#about to read 6, iclass 18, count 0 2006.257.16:26:39.87#ibcon#read 6, iclass 18, count 0 2006.257.16:26:39.87#ibcon#end of sib2, iclass 18, count 0 2006.257.16:26:39.87#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:26:39.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:26:39.87#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.16:26:39.87#ibcon#*before write, iclass 18, count 0 2006.257.16:26:39.87#ibcon#enter sib2, iclass 18, count 0 2006.257.16:26:39.87#ibcon#flushed, iclass 18, count 0 2006.257.16:26:39.87#ibcon#about to write, iclass 18, count 0 2006.257.16:26:39.87#ibcon#wrote, iclass 18, count 0 2006.257.16:26:39.87#ibcon#about to read 3, iclass 18, count 0 2006.257.16:26:39.91#ibcon#read 3, iclass 18, count 0 2006.257.16:26:39.91#ibcon#about to read 4, iclass 18, count 0 2006.257.16:26:39.91#ibcon#read 4, iclass 18, count 0 2006.257.16:26:39.91#ibcon#about to read 5, iclass 18, count 0 2006.257.16:26:39.91#ibcon#read 5, iclass 18, count 0 2006.257.16:26:39.91#ibcon#about to read 6, iclass 18, count 0 2006.257.16:26:39.91#ibcon#read 6, iclass 18, count 0 2006.257.16:26:39.91#ibcon#end of sib2, iclass 18, count 0 2006.257.16:26:39.91#ibcon#*after write, iclass 18, count 0 2006.257.16:26:39.91#ibcon#*before return 0, iclass 18, count 0 2006.257.16:26:39.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:39.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:39.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:26:39.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:26:39.91$vck44/va=5,4 2006.257.16:26:39.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.16:26:39.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.16:26:39.91#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:39.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:39.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:39.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:39.97#ibcon#enter wrdev, iclass 20, count 2 2006.257.16:26:39.97#ibcon#first serial, iclass 20, count 2 2006.257.16:26:39.97#ibcon#enter sib2, iclass 20, count 2 2006.257.16:26:39.97#ibcon#flushed, iclass 20, count 2 2006.257.16:26:39.97#ibcon#about to write, iclass 20, count 2 2006.257.16:26:39.97#ibcon#wrote, iclass 20, count 2 2006.257.16:26:39.97#ibcon#about to read 3, iclass 20, count 2 2006.257.16:26:39.99#ibcon#read 3, iclass 20, count 2 2006.257.16:26:39.99#ibcon#about to read 4, iclass 20, count 2 2006.257.16:26:39.99#ibcon#read 4, iclass 20, count 2 2006.257.16:26:39.99#ibcon#about to read 5, iclass 20, count 2 2006.257.16:26:39.99#ibcon#read 5, iclass 20, count 2 2006.257.16:26:39.99#ibcon#about to read 6, iclass 20, count 2 2006.257.16:26:39.99#ibcon#read 6, iclass 20, count 2 2006.257.16:26:39.99#ibcon#end of sib2, iclass 20, count 2 2006.257.16:26:39.99#ibcon#*mode == 0, iclass 20, count 2 2006.257.16:26:39.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.16:26:39.99#ibcon#[25=AT05-04\r\n] 2006.257.16:26:39.99#ibcon#*before write, iclass 20, count 2 2006.257.16:26:39.99#ibcon#enter sib2, iclass 20, count 2 2006.257.16:26:39.99#ibcon#flushed, iclass 20, count 2 2006.257.16:26:39.99#ibcon#about to write, iclass 20, count 2 2006.257.16:26:39.99#ibcon#wrote, iclass 20, count 2 2006.257.16:26:39.99#ibcon#about to read 3, iclass 20, count 2 2006.257.16:26:40.02#ibcon#read 3, iclass 20, count 2 2006.257.16:26:40.02#ibcon#about to read 4, iclass 20, count 2 2006.257.16:26:40.02#ibcon#read 4, iclass 20, count 2 2006.257.16:26:40.02#ibcon#about to read 5, iclass 20, count 2 2006.257.16:26:40.02#ibcon#read 5, iclass 20, count 2 2006.257.16:26:40.02#ibcon#about to read 6, iclass 20, count 2 2006.257.16:26:40.02#ibcon#read 6, iclass 20, count 2 2006.257.16:26:40.02#ibcon#end of sib2, iclass 20, count 2 2006.257.16:26:40.02#ibcon#*after write, iclass 20, count 2 2006.257.16:26:40.02#ibcon#*before return 0, iclass 20, count 2 2006.257.16:26:40.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:40.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:40.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.16:26:40.02#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:40.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:40.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:40.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:40.14#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:26:40.14#ibcon#first serial, iclass 20, count 0 2006.257.16:26:40.14#ibcon#enter sib2, iclass 20, count 0 2006.257.16:26:40.14#ibcon#flushed, iclass 20, count 0 2006.257.16:26:40.14#ibcon#about to write, iclass 20, count 0 2006.257.16:26:40.14#ibcon#wrote, iclass 20, count 0 2006.257.16:26:40.14#ibcon#about to read 3, iclass 20, count 0 2006.257.16:26:40.16#ibcon#read 3, iclass 20, count 0 2006.257.16:26:40.16#ibcon#about to read 4, iclass 20, count 0 2006.257.16:26:40.16#ibcon#read 4, iclass 20, count 0 2006.257.16:26:40.16#ibcon#about to read 5, iclass 20, count 0 2006.257.16:26:40.16#ibcon#read 5, iclass 20, count 0 2006.257.16:26:40.16#ibcon#about to read 6, iclass 20, count 0 2006.257.16:26:40.16#ibcon#read 6, iclass 20, count 0 2006.257.16:26:40.16#ibcon#end of sib2, iclass 20, count 0 2006.257.16:26:40.16#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:26:40.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:26:40.16#ibcon#[25=USB\r\n] 2006.257.16:26:40.16#ibcon#*before write, iclass 20, count 0 2006.257.16:26:40.16#ibcon#enter sib2, iclass 20, count 0 2006.257.16:26:40.16#ibcon#flushed, iclass 20, count 0 2006.257.16:26:40.16#ibcon#about to write, iclass 20, count 0 2006.257.16:26:40.16#ibcon#wrote, iclass 20, count 0 2006.257.16:26:40.16#ibcon#about to read 3, iclass 20, count 0 2006.257.16:26:40.19#ibcon#read 3, iclass 20, count 0 2006.257.16:26:40.19#ibcon#about to read 4, iclass 20, count 0 2006.257.16:26:40.19#ibcon#read 4, iclass 20, count 0 2006.257.16:26:40.19#ibcon#about to read 5, iclass 20, count 0 2006.257.16:26:40.19#ibcon#read 5, iclass 20, count 0 2006.257.16:26:40.19#ibcon#about to read 6, iclass 20, count 0 2006.257.16:26:40.19#ibcon#read 6, iclass 20, count 0 2006.257.16:26:40.19#ibcon#end of sib2, iclass 20, count 0 2006.257.16:26:40.19#ibcon#*after write, iclass 20, count 0 2006.257.16:26:40.19#ibcon#*before return 0, iclass 20, count 0 2006.257.16:26:40.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:40.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:40.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:26:40.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:26:40.19$vck44/valo=6,814.99 2006.257.16:26:40.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.16:26:40.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.16:26:40.19#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:40.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:40.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:40.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:40.19#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:26:40.19#ibcon#first serial, iclass 22, count 0 2006.257.16:26:40.19#ibcon#enter sib2, iclass 22, count 0 2006.257.16:26:40.19#ibcon#flushed, iclass 22, count 0 2006.257.16:26:40.19#ibcon#about to write, iclass 22, count 0 2006.257.16:26:40.19#ibcon#wrote, iclass 22, count 0 2006.257.16:26:40.19#ibcon#about to read 3, iclass 22, count 0 2006.257.16:26:40.21#ibcon#read 3, iclass 22, count 0 2006.257.16:26:40.21#ibcon#about to read 4, iclass 22, count 0 2006.257.16:26:40.21#ibcon#read 4, iclass 22, count 0 2006.257.16:26:40.21#ibcon#about to read 5, iclass 22, count 0 2006.257.16:26:40.21#ibcon#read 5, iclass 22, count 0 2006.257.16:26:40.21#ibcon#about to read 6, iclass 22, count 0 2006.257.16:26:40.21#ibcon#read 6, iclass 22, count 0 2006.257.16:26:40.21#ibcon#end of sib2, iclass 22, count 0 2006.257.16:26:40.21#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:26:40.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:26:40.21#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.16:26:40.21#ibcon#*before write, iclass 22, count 0 2006.257.16:26:40.21#ibcon#enter sib2, iclass 22, count 0 2006.257.16:26:40.21#ibcon#flushed, iclass 22, count 0 2006.257.16:26:40.21#ibcon#about to write, iclass 22, count 0 2006.257.16:26:40.21#ibcon#wrote, iclass 22, count 0 2006.257.16:26:40.21#ibcon#about to read 3, iclass 22, count 0 2006.257.16:26:40.25#ibcon#read 3, iclass 22, count 0 2006.257.16:26:40.25#ibcon#about to read 4, iclass 22, count 0 2006.257.16:26:40.25#ibcon#read 4, iclass 22, count 0 2006.257.16:26:40.25#ibcon#about to read 5, iclass 22, count 0 2006.257.16:26:40.25#ibcon#read 5, iclass 22, count 0 2006.257.16:26:40.25#ibcon#about to read 6, iclass 22, count 0 2006.257.16:26:40.25#ibcon#read 6, iclass 22, count 0 2006.257.16:26:40.25#ibcon#end of sib2, iclass 22, count 0 2006.257.16:26:40.25#ibcon#*after write, iclass 22, count 0 2006.257.16:26:40.25#ibcon#*before return 0, iclass 22, count 0 2006.257.16:26:40.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:40.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:40.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:26:40.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:26:40.25$vck44/va=6,4 2006.257.16:26:40.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.16:26:40.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.16:26:40.25#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:40.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:40.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:40.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:40.31#ibcon#enter wrdev, iclass 24, count 2 2006.257.16:26:40.31#ibcon#first serial, iclass 24, count 2 2006.257.16:26:40.31#ibcon#enter sib2, iclass 24, count 2 2006.257.16:26:40.31#ibcon#flushed, iclass 24, count 2 2006.257.16:26:40.31#ibcon#about to write, iclass 24, count 2 2006.257.16:26:40.31#ibcon#wrote, iclass 24, count 2 2006.257.16:26:40.31#ibcon#about to read 3, iclass 24, count 2 2006.257.16:26:40.33#ibcon#read 3, iclass 24, count 2 2006.257.16:26:40.33#ibcon#about to read 4, iclass 24, count 2 2006.257.16:26:40.33#ibcon#read 4, iclass 24, count 2 2006.257.16:26:40.33#ibcon#about to read 5, iclass 24, count 2 2006.257.16:26:40.33#ibcon#read 5, iclass 24, count 2 2006.257.16:26:40.33#ibcon#about to read 6, iclass 24, count 2 2006.257.16:26:40.33#ibcon#read 6, iclass 24, count 2 2006.257.16:26:40.33#ibcon#end of sib2, iclass 24, count 2 2006.257.16:26:40.33#ibcon#*mode == 0, iclass 24, count 2 2006.257.16:26:40.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.16:26:40.33#ibcon#[25=AT06-04\r\n] 2006.257.16:26:40.33#ibcon#*before write, iclass 24, count 2 2006.257.16:26:40.33#ibcon#enter sib2, iclass 24, count 2 2006.257.16:26:40.33#ibcon#flushed, iclass 24, count 2 2006.257.16:26:40.33#ibcon#about to write, iclass 24, count 2 2006.257.16:26:40.33#ibcon#wrote, iclass 24, count 2 2006.257.16:26:40.33#ibcon#about to read 3, iclass 24, count 2 2006.257.16:26:40.36#ibcon#read 3, iclass 24, count 2 2006.257.16:26:40.36#ibcon#about to read 4, iclass 24, count 2 2006.257.16:26:40.36#ibcon#read 4, iclass 24, count 2 2006.257.16:26:40.36#ibcon#about to read 5, iclass 24, count 2 2006.257.16:26:40.36#ibcon#read 5, iclass 24, count 2 2006.257.16:26:40.36#ibcon#about to read 6, iclass 24, count 2 2006.257.16:26:40.36#ibcon#read 6, iclass 24, count 2 2006.257.16:26:40.36#ibcon#end of sib2, iclass 24, count 2 2006.257.16:26:40.36#ibcon#*after write, iclass 24, count 2 2006.257.16:26:40.36#ibcon#*before return 0, iclass 24, count 2 2006.257.16:26:40.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:40.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:40.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.16:26:40.36#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:40.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:40.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:40.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:40.48#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:26:40.48#ibcon#first serial, iclass 24, count 0 2006.257.16:26:40.48#ibcon#enter sib2, iclass 24, count 0 2006.257.16:26:40.48#ibcon#flushed, iclass 24, count 0 2006.257.16:26:40.48#ibcon#about to write, iclass 24, count 0 2006.257.16:26:40.48#ibcon#wrote, iclass 24, count 0 2006.257.16:26:40.48#ibcon#about to read 3, iclass 24, count 0 2006.257.16:26:40.50#ibcon#read 3, iclass 24, count 0 2006.257.16:26:40.50#ibcon#about to read 4, iclass 24, count 0 2006.257.16:26:40.50#ibcon#read 4, iclass 24, count 0 2006.257.16:26:40.50#ibcon#about to read 5, iclass 24, count 0 2006.257.16:26:40.50#ibcon#read 5, iclass 24, count 0 2006.257.16:26:40.50#ibcon#about to read 6, iclass 24, count 0 2006.257.16:26:40.50#ibcon#read 6, iclass 24, count 0 2006.257.16:26:40.50#ibcon#end of sib2, iclass 24, count 0 2006.257.16:26:40.50#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:26:40.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:26:40.50#ibcon#[25=USB\r\n] 2006.257.16:26:40.50#ibcon#*before write, iclass 24, count 0 2006.257.16:26:40.50#ibcon#enter sib2, iclass 24, count 0 2006.257.16:26:40.50#ibcon#flushed, iclass 24, count 0 2006.257.16:26:40.50#ibcon#about to write, iclass 24, count 0 2006.257.16:26:40.50#ibcon#wrote, iclass 24, count 0 2006.257.16:26:40.50#ibcon#about to read 3, iclass 24, count 0 2006.257.16:26:40.53#ibcon#read 3, iclass 24, count 0 2006.257.16:26:40.53#ibcon#about to read 4, iclass 24, count 0 2006.257.16:26:40.53#ibcon#read 4, iclass 24, count 0 2006.257.16:26:40.53#ibcon#about to read 5, iclass 24, count 0 2006.257.16:26:40.53#ibcon#read 5, iclass 24, count 0 2006.257.16:26:40.53#ibcon#about to read 6, iclass 24, count 0 2006.257.16:26:40.53#ibcon#read 6, iclass 24, count 0 2006.257.16:26:40.53#ibcon#end of sib2, iclass 24, count 0 2006.257.16:26:40.53#ibcon#*after write, iclass 24, count 0 2006.257.16:26:40.53#ibcon#*before return 0, iclass 24, count 0 2006.257.16:26:40.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:40.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:40.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:26:40.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:26:40.53$vck44/valo=7,864.99 2006.257.16:26:40.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.16:26:40.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.16:26:40.53#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:40.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:40.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:40.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:40.53#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:26:40.53#ibcon#first serial, iclass 26, count 0 2006.257.16:26:40.53#ibcon#enter sib2, iclass 26, count 0 2006.257.16:26:40.53#ibcon#flushed, iclass 26, count 0 2006.257.16:26:40.53#ibcon#about to write, iclass 26, count 0 2006.257.16:26:40.53#ibcon#wrote, iclass 26, count 0 2006.257.16:26:40.53#ibcon#about to read 3, iclass 26, count 0 2006.257.16:26:40.55#ibcon#read 3, iclass 26, count 0 2006.257.16:26:40.55#ibcon#about to read 4, iclass 26, count 0 2006.257.16:26:40.55#ibcon#read 4, iclass 26, count 0 2006.257.16:26:40.55#ibcon#about to read 5, iclass 26, count 0 2006.257.16:26:40.55#ibcon#read 5, iclass 26, count 0 2006.257.16:26:40.55#ibcon#about to read 6, iclass 26, count 0 2006.257.16:26:40.55#ibcon#read 6, iclass 26, count 0 2006.257.16:26:40.55#ibcon#end of sib2, iclass 26, count 0 2006.257.16:26:40.55#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:26:40.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:26:40.55#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.16:26:40.55#ibcon#*before write, iclass 26, count 0 2006.257.16:26:40.55#ibcon#enter sib2, iclass 26, count 0 2006.257.16:26:40.55#ibcon#flushed, iclass 26, count 0 2006.257.16:26:40.55#ibcon#about to write, iclass 26, count 0 2006.257.16:26:40.55#ibcon#wrote, iclass 26, count 0 2006.257.16:26:40.55#ibcon#about to read 3, iclass 26, count 0 2006.257.16:26:40.59#ibcon#read 3, iclass 26, count 0 2006.257.16:26:40.59#ibcon#about to read 4, iclass 26, count 0 2006.257.16:26:40.59#ibcon#read 4, iclass 26, count 0 2006.257.16:26:40.59#ibcon#about to read 5, iclass 26, count 0 2006.257.16:26:40.59#ibcon#read 5, iclass 26, count 0 2006.257.16:26:40.59#ibcon#about to read 6, iclass 26, count 0 2006.257.16:26:40.59#ibcon#read 6, iclass 26, count 0 2006.257.16:26:40.59#ibcon#end of sib2, iclass 26, count 0 2006.257.16:26:40.59#ibcon#*after write, iclass 26, count 0 2006.257.16:26:40.59#ibcon#*before return 0, iclass 26, count 0 2006.257.16:26:40.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:40.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:40.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:26:40.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:26:40.59$vck44/va=7,4 2006.257.16:26:40.59#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.16:26:40.59#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.16:26:40.59#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:40.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:40.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:40.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:40.65#ibcon#enter wrdev, iclass 28, count 2 2006.257.16:26:40.65#ibcon#first serial, iclass 28, count 2 2006.257.16:26:40.65#ibcon#enter sib2, iclass 28, count 2 2006.257.16:26:40.65#ibcon#flushed, iclass 28, count 2 2006.257.16:26:40.65#ibcon#about to write, iclass 28, count 2 2006.257.16:26:40.65#ibcon#wrote, iclass 28, count 2 2006.257.16:26:40.65#ibcon#about to read 3, iclass 28, count 2 2006.257.16:26:40.67#ibcon#read 3, iclass 28, count 2 2006.257.16:26:40.67#ibcon#about to read 4, iclass 28, count 2 2006.257.16:26:40.67#ibcon#read 4, iclass 28, count 2 2006.257.16:26:40.67#ibcon#about to read 5, iclass 28, count 2 2006.257.16:26:40.67#ibcon#read 5, iclass 28, count 2 2006.257.16:26:40.67#ibcon#about to read 6, iclass 28, count 2 2006.257.16:26:40.67#ibcon#read 6, iclass 28, count 2 2006.257.16:26:40.67#ibcon#end of sib2, iclass 28, count 2 2006.257.16:26:40.67#ibcon#*mode == 0, iclass 28, count 2 2006.257.16:26:40.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.16:26:40.67#ibcon#[25=AT07-04\r\n] 2006.257.16:26:40.67#ibcon#*before write, iclass 28, count 2 2006.257.16:26:40.67#ibcon#enter sib2, iclass 28, count 2 2006.257.16:26:40.67#ibcon#flushed, iclass 28, count 2 2006.257.16:26:40.67#ibcon#about to write, iclass 28, count 2 2006.257.16:26:40.67#ibcon#wrote, iclass 28, count 2 2006.257.16:26:40.67#ibcon#about to read 3, iclass 28, count 2 2006.257.16:26:40.70#ibcon#read 3, iclass 28, count 2 2006.257.16:26:40.70#ibcon#about to read 4, iclass 28, count 2 2006.257.16:26:40.70#ibcon#read 4, iclass 28, count 2 2006.257.16:26:40.70#ibcon#about to read 5, iclass 28, count 2 2006.257.16:26:40.70#ibcon#read 5, iclass 28, count 2 2006.257.16:26:40.70#ibcon#about to read 6, iclass 28, count 2 2006.257.16:26:40.70#ibcon#read 6, iclass 28, count 2 2006.257.16:26:40.70#ibcon#end of sib2, iclass 28, count 2 2006.257.16:26:40.70#ibcon#*after write, iclass 28, count 2 2006.257.16:26:40.70#ibcon#*before return 0, iclass 28, count 2 2006.257.16:26:40.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:40.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:40.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.16:26:40.70#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:40.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:40.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:40.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:40.82#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:26:40.82#ibcon#first serial, iclass 28, count 0 2006.257.16:26:40.82#ibcon#enter sib2, iclass 28, count 0 2006.257.16:26:40.82#ibcon#flushed, iclass 28, count 0 2006.257.16:26:40.82#ibcon#about to write, iclass 28, count 0 2006.257.16:26:40.82#ibcon#wrote, iclass 28, count 0 2006.257.16:26:40.82#ibcon#about to read 3, iclass 28, count 0 2006.257.16:26:40.84#ibcon#read 3, iclass 28, count 0 2006.257.16:26:40.84#ibcon#about to read 4, iclass 28, count 0 2006.257.16:26:40.84#ibcon#read 4, iclass 28, count 0 2006.257.16:26:40.84#ibcon#about to read 5, iclass 28, count 0 2006.257.16:26:40.84#ibcon#read 5, iclass 28, count 0 2006.257.16:26:40.84#ibcon#about to read 6, iclass 28, count 0 2006.257.16:26:40.84#ibcon#read 6, iclass 28, count 0 2006.257.16:26:40.84#ibcon#end of sib2, iclass 28, count 0 2006.257.16:26:40.84#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:26:40.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:26:40.84#ibcon#[25=USB\r\n] 2006.257.16:26:40.84#ibcon#*before write, iclass 28, count 0 2006.257.16:26:40.84#ibcon#enter sib2, iclass 28, count 0 2006.257.16:26:40.84#ibcon#flushed, iclass 28, count 0 2006.257.16:26:40.84#ibcon#about to write, iclass 28, count 0 2006.257.16:26:40.84#ibcon#wrote, iclass 28, count 0 2006.257.16:26:40.84#ibcon#about to read 3, iclass 28, count 0 2006.257.16:26:40.87#ibcon#read 3, iclass 28, count 0 2006.257.16:26:40.87#ibcon#about to read 4, iclass 28, count 0 2006.257.16:26:40.87#ibcon#read 4, iclass 28, count 0 2006.257.16:26:40.87#ibcon#about to read 5, iclass 28, count 0 2006.257.16:26:40.87#ibcon#read 5, iclass 28, count 0 2006.257.16:26:40.87#ibcon#about to read 6, iclass 28, count 0 2006.257.16:26:40.87#ibcon#read 6, iclass 28, count 0 2006.257.16:26:40.87#ibcon#end of sib2, iclass 28, count 0 2006.257.16:26:40.87#ibcon#*after write, iclass 28, count 0 2006.257.16:26:40.87#ibcon#*before return 0, iclass 28, count 0 2006.257.16:26:40.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:40.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:40.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:26:40.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:26:40.87$vck44/valo=8,884.99 2006.257.16:26:40.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.16:26:40.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.16:26:40.87#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:40.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:40.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:40.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:40.87#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:26:40.87#ibcon#first serial, iclass 30, count 0 2006.257.16:26:40.87#ibcon#enter sib2, iclass 30, count 0 2006.257.16:26:40.87#ibcon#flushed, iclass 30, count 0 2006.257.16:26:40.87#ibcon#about to write, iclass 30, count 0 2006.257.16:26:40.87#ibcon#wrote, iclass 30, count 0 2006.257.16:26:40.87#ibcon#about to read 3, iclass 30, count 0 2006.257.16:26:40.89#ibcon#read 3, iclass 30, count 0 2006.257.16:26:40.89#ibcon#about to read 4, iclass 30, count 0 2006.257.16:26:40.89#ibcon#read 4, iclass 30, count 0 2006.257.16:26:40.89#ibcon#about to read 5, iclass 30, count 0 2006.257.16:26:40.89#ibcon#read 5, iclass 30, count 0 2006.257.16:26:40.89#ibcon#about to read 6, iclass 30, count 0 2006.257.16:26:40.89#ibcon#read 6, iclass 30, count 0 2006.257.16:26:40.89#ibcon#end of sib2, iclass 30, count 0 2006.257.16:26:40.89#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:26:40.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:26:40.89#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.16:26:40.89#ibcon#*before write, iclass 30, count 0 2006.257.16:26:40.89#ibcon#enter sib2, iclass 30, count 0 2006.257.16:26:40.89#ibcon#flushed, iclass 30, count 0 2006.257.16:26:40.89#ibcon#about to write, iclass 30, count 0 2006.257.16:26:40.89#ibcon#wrote, iclass 30, count 0 2006.257.16:26:40.89#ibcon#about to read 3, iclass 30, count 0 2006.257.16:26:40.93#ibcon#read 3, iclass 30, count 0 2006.257.16:26:40.93#ibcon#about to read 4, iclass 30, count 0 2006.257.16:26:40.93#ibcon#read 4, iclass 30, count 0 2006.257.16:26:40.93#ibcon#about to read 5, iclass 30, count 0 2006.257.16:26:40.93#ibcon#read 5, iclass 30, count 0 2006.257.16:26:40.93#ibcon#about to read 6, iclass 30, count 0 2006.257.16:26:40.93#ibcon#read 6, iclass 30, count 0 2006.257.16:26:40.93#ibcon#end of sib2, iclass 30, count 0 2006.257.16:26:40.93#ibcon#*after write, iclass 30, count 0 2006.257.16:26:40.93#ibcon#*before return 0, iclass 30, count 0 2006.257.16:26:40.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:40.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:40.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:26:40.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:26:40.93$vck44/va=8,4 2006.257.16:26:40.93#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.16:26:40.93#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.16:26:40.93#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:40.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:26:40.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:26:40.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:26:40.99#ibcon#enter wrdev, iclass 32, count 2 2006.257.16:26:40.99#ibcon#first serial, iclass 32, count 2 2006.257.16:26:40.99#ibcon#enter sib2, iclass 32, count 2 2006.257.16:26:40.99#ibcon#flushed, iclass 32, count 2 2006.257.16:26:40.99#ibcon#about to write, iclass 32, count 2 2006.257.16:26:40.99#ibcon#wrote, iclass 32, count 2 2006.257.16:26:40.99#ibcon#about to read 3, iclass 32, count 2 2006.257.16:26:41.01#ibcon#read 3, iclass 32, count 2 2006.257.16:26:41.01#ibcon#about to read 4, iclass 32, count 2 2006.257.16:26:41.01#ibcon#read 4, iclass 32, count 2 2006.257.16:26:41.01#ibcon#about to read 5, iclass 32, count 2 2006.257.16:26:41.01#ibcon#read 5, iclass 32, count 2 2006.257.16:26:41.01#ibcon#about to read 6, iclass 32, count 2 2006.257.16:26:41.01#ibcon#read 6, iclass 32, count 2 2006.257.16:26:41.01#ibcon#end of sib2, iclass 32, count 2 2006.257.16:26:41.01#ibcon#*mode == 0, iclass 32, count 2 2006.257.16:26:41.01#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.16:26:41.01#ibcon#[25=AT08-04\r\n] 2006.257.16:26:41.01#ibcon#*before write, iclass 32, count 2 2006.257.16:26:41.01#ibcon#enter sib2, iclass 32, count 2 2006.257.16:26:41.01#ibcon#flushed, iclass 32, count 2 2006.257.16:26:41.01#ibcon#about to write, iclass 32, count 2 2006.257.16:26:41.01#ibcon#wrote, iclass 32, count 2 2006.257.16:26:41.01#ibcon#about to read 3, iclass 32, count 2 2006.257.16:26:41.04#ibcon#read 3, iclass 32, count 2 2006.257.16:26:41.04#ibcon#about to read 4, iclass 32, count 2 2006.257.16:26:41.04#ibcon#read 4, iclass 32, count 2 2006.257.16:26:41.04#ibcon#about to read 5, iclass 32, count 2 2006.257.16:26:41.04#ibcon#read 5, iclass 32, count 2 2006.257.16:26:41.04#ibcon#about to read 6, iclass 32, count 2 2006.257.16:26:41.04#ibcon#read 6, iclass 32, count 2 2006.257.16:26:41.04#ibcon#end of sib2, iclass 32, count 2 2006.257.16:26:41.04#ibcon#*after write, iclass 32, count 2 2006.257.16:26:41.04#ibcon#*before return 0, iclass 32, count 2 2006.257.16:26:41.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:26:41.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:26:41.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.16:26:41.04#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:41.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:26:41.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:26:41.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:26:41.16#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:26:41.16#ibcon#first serial, iclass 32, count 0 2006.257.16:26:41.16#ibcon#enter sib2, iclass 32, count 0 2006.257.16:26:41.16#ibcon#flushed, iclass 32, count 0 2006.257.16:26:41.16#ibcon#about to write, iclass 32, count 0 2006.257.16:26:41.16#ibcon#wrote, iclass 32, count 0 2006.257.16:26:41.16#ibcon#about to read 3, iclass 32, count 0 2006.257.16:26:41.18#ibcon#read 3, iclass 32, count 0 2006.257.16:26:41.18#ibcon#about to read 4, iclass 32, count 0 2006.257.16:26:41.18#ibcon#read 4, iclass 32, count 0 2006.257.16:26:41.18#ibcon#about to read 5, iclass 32, count 0 2006.257.16:26:41.18#ibcon#read 5, iclass 32, count 0 2006.257.16:26:41.18#ibcon#about to read 6, iclass 32, count 0 2006.257.16:26:41.18#ibcon#read 6, iclass 32, count 0 2006.257.16:26:41.18#ibcon#end of sib2, iclass 32, count 0 2006.257.16:26:41.18#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:26:41.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:26:41.18#ibcon#[25=USB\r\n] 2006.257.16:26:41.18#ibcon#*before write, iclass 32, count 0 2006.257.16:26:41.18#ibcon#enter sib2, iclass 32, count 0 2006.257.16:26:41.18#ibcon#flushed, iclass 32, count 0 2006.257.16:26:41.18#ibcon#about to write, iclass 32, count 0 2006.257.16:26:41.18#ibcon#wrote, iclass 32, count 0 2006.257.16:26:41.18#ibcon#about to read 3, iclass 32, count 0 2006.257.16:26:41.21#ibcon#read 3, iclass 32, count 0 2006.257.16:26:41.21#ibcon#about to read 4, iclass 32, count 0 2006.257.16:26:41.21#ibcon#read 4, iclass 32, count 0 2006.257.16:26:41.21#ibcon#about to read 5, iclass 32, count 0 2006.257.16:26:41.21#ibcon#read 5, iclass 32, count 0 2006.257.16:26:41.21#ibcon#about to read 6, iclass 32, count 0 2006.257.16:26:41.21#ibcon#read 6, iclass 32, count 0 2006.257.16:26:41.21#ibcon#end of sib2, iclass 32, count 0 2006.257.16:26:41.21#ibcon#*after write, iclass 32, count 0 2006.257.16:26:41.21#ibcon#*before return 0, iclass 32, count 0 2006.257.16:26:41.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:26:41.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:26:41.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:26:41.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:26:41.21$vck44/vblo=1,629.99 2006.257.16:26:41.21#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.16:26:41.21#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.16:26:41.21#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:41.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:26:41.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:26:41.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:26:41.21#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:26:41.21#ibcon#first serial, iclass 34, count 0 2006.257.16:26:41.21#ibcon#enter sib2, iclass 34, count 0 2006.257.16:26:41.21#ibcon#flushed, iclass 34, count 0 2006.257.16:26:41.21#ibcon#about to write, iclass 34, count 0 2006.257.16:26:41.21#ibcon#wrote, iclass 34, count 0 2006.257.16:26:41.21#ibcon#about to read 3, iclass 34, count 0 2006.257.16:26:41.23#ibcon#read 3, iclass 34, count 0 2006.257.16:26:41.23#ibcon#about to read 4, iclass 34, count 0 2006.257.16:26:41.23#ibcon#read 4, iclass 34, count 0 2006.257.16:26:41.23#ibcon#about to read 5, iclass 34, count 0 2006.257.16:26:41.23#ibcon#read 5, iclass 34, count 0 2006.257.16:26:41.23#ibcon#about to read 6, iclass 34, count 0 2006.257.16:26:41.23#ibcon#read 6, iclass 34, count 0 2006.257.16:26:41.23#ibcon#end of sib2, iclass 34, count 0 2006.257.16:26:41.23#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:26:41.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:26:41.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.16:26:41.23#ibcon#*before write, iclass 34, count 0 2006.257.16:26:41.23#ibcon#enter sib2, iclass 34, count 0 2006.257.16:26:41.23#ibcon#flushed, iclass 34, count 0 2006.257.16:26:41.23#ibcon#about to write, iclass 34, count 0 2006.257.16:26:41.23#ibcon#wrote, iclass 34, count 0 2006.257.16:26:41.23#ibcon#about to read 3, iclass 34, count 0 2006.257.16:26:41.27#ibcon#read 3, iclass 34, count 0 2006.257.16:26:41.27#ibcon#about to read 4, iclass 34, count 0 2006.257.16:26:41.27#ibcon#read 4, iclass 34, count 0 2006.257.16:26:41.27#ibcon#about to read 5, iclass 34, count 0 2006.257.16:26:41.27#ibcon#read 5, iclass 34, count 0 2006.257.16:26:41.27#ibcon#about to read 6, iclass 34, count 0 2006.257.16:26:41.27#ibcon#read 6, iclass 34, count 0 2006.257.16:26:41.27#ibcon#end of sib2, iclass 34, count 0 2006.257.16:26:41.27#ibcon#*after write, iclass 34, count 0 2006.257.16:26:41.27#ibcon#*before return 0, iclass 34, count 0 2006.257.16:26:41.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:26:41.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:26:41.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:26:41.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:26:41.27$vck44/vb=1,4 2006.257.16:26:41.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.16:26:41.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.16:26:41.27#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:41.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:26:41.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:26:41.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:26:41.27#ibcon#enter wrdev, iclass 36, count 2 2006.257.16:26:41.27#ibcon#first serial, iclass 36, count 2 2006.257.16:26:41.27#ibcon#enter sib2, iclass 36, count 2 2006.257.16:26:41.27#ibcon#flushed, iclass 36, count 2 2006.257.16:26:41.27#ibcon#about to write, iclass 36, count 2 2006.257.16:26:41.27#ibcon#wrote, iclass 36, count 2 2006.257.16:26:41.27#ibcon#about to read 3, iclass 36, count 2 2006.257.16:26:41.29#ibcon#read 3, iclass 36, count 2 2006.257.16:26:41.29#ibcon#about to read 4, iclass 36, count 2 2006.257.16:26:41.29#ibcon#read 4, iclass 36, count 2 2006.257.16:26:41.29#ibcon#about to read 5, iclass 36, count 2 2006.257.16:26:41.29#ibcon#read 5, iclass 36, count 2 2006.257.16:26:41.29#ibcon#about to read 6, iclass 36, count 2 2006.257.16:26:41.29#ibcon#read 6, iclass 36, count 2 2006.257.16:26:41.29#ibcon#end of sib2, iclass 36, count 2 2006.257.16:26:41.29#ibcon#*mode == 0, iclass 36, count 2 2006.257.16:26:41.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.16:26:41.29#ibcon#[27=AT01-04\r\n] 2006.257.16:26:41.29#ibcon#*before write, iclass 36, count 2 2006.257.16:26:41.29#ibcon#enter sib2, iclass 36, count 2 2006.257.16:26:41.29#ibcon#flushed, iclass 36, count 2 2006.257.16:26:41.29#ibcon#about to write, iclass 36, count 2 2006.257.16:26:41.29#ibcon#wrote, iclass 36, count 2 2006.257.16:26:41.29#ibcon#about to read 3, iclass 36, count 2 2006.257.16:26:41.32#ibcon#read 3, iclass 36, count 2 2006.257.16:26:41.32#ibcon#about to read 4, iclass 36, count 2 2006.257.16:26:41.32#ibcon#read 4, iclass 36, count 2 2006.257.16:26:41.32#ibcon#about to read 5, iclass 36, count 2 2006.257.16:26:41.32#ibcon#read 5, iclass 36, count 2 2006.257.16:26:41.32#ibcon#about to read 6, iclass 36, count 2 2006.257.16:26:41.32#ibcon#read 6, iclass 36, count 2 2006.257.16:26:41.32#ibcon#end of sib2, iclass 36, count 2 2006.257.16:26:41.32#ibcon#*after write, iclass 36, count 2 2006.257.16:26:41.32#ibcon#*before return 0, iclass 36, count 2 2006.257.16:26:41.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:26:41.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:26:41.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.16:26:41.32#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:41.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:26:41.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:26:41.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:26:41.44#ibcon#enter wrdev, iclass 36, count 0 2006.257.16:26:41.44#ibcon#first serial, iclass 36, count 0 2006.257.16:26:41.44#ibcon#enter sib2, iclass 36, count 0 2006.257.16:26:41.44#ibcon#flushed, iclass 36, count 0 2006.257.16:26:41.44#ibcon#about to write, iclass 36, count 0 2006.257.16:26:41.44#ibcon#wrote, iclass 36, count 0 2006.257.16:26:41.44#ibcon#about to read 3, iclass 36, count 0 2006.257.16:26:41.46#ibcon#read 3, iclass 36, count 0 2006.257.16:26:41.46#ibcon#about to read 4, iclass 36, count 0 2006.257.16:26:41.46#ibcon#read 4, iclass 36, count 0 2006.257.16:26:41.46#ibcon#about to read 5, iclass 36, count 0 2006.257.16:26:41.46#ibcon#read 5, iclass 36, count 0 2006.257.16:26:41.46#ibcon#about to read 6, iclass 36, count 0 2006.257.16:26:41.46#ibcon#read 6, iclass 36, count 0 2006.257.16:26:41.46#ibcon#end of sib2, iclass 36, count 0 2006.257.16:26:41.46#ibcon#*mode == 0, iclass 36, count 0 2006.257.16:26:41.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.16:26:41.46#ibcon#[27=USB\r\n] 2006.257.16:26:41.46#ibcon#*before write, iclass 36, count 0 2006.257.16:26:41.46#ibcon#enter sib2, iclass 36, count 0 2006.257.16:26:41.46#ibcon#flushed, iclass 36, count 0 2006.257.16:26:41.46#ibcon#about to write, iclass 36, count 0 2006.257.16:26:41.46#ibcon#wrote, iclass 36, count 0 2006.257.16:26:41.46#ibcon#about to read 3, iclass 36, count 0 2006.257.16:26:41.49#ibcon#read 3, iclass 36, count 0 2006.257.16:26:41.49#ibcon#about to read 4, iclass 36, count 0 2006.257.16:26:41.49#ibcon#read 4, iclass 36, count 0 2006.257.16:26:41.49#ibcon#about to read 5, iclass 36, count 0 2006.257.16:26:41.49#ibcon#read 5, iclass 36, count 0 2006.257.16:26:41.49#ibcon#about to read 6, iclass 36, count 0 2006.257.16:26:41.49#ibcon#read 6, iclass 36, count 0 2006.257.16:26:41.49#ibcon#end of sib2, iclass 36, count 0 2006.257.16:26:41.49#ibcon#*after write, iclass 36, count 0 2006.257.16:26:41.49#ibcon#*before return 0, iclass 36, count 0 2006.257.16:26:41.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:26:41.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:26:41.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.16:26:41.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.16:26:41.49$vck44/vblo=2,634.99 2006.257.16:26:41.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.16:26:41.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.16:26:41.49#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:41.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:41.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:41.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:41.49#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:26:41.49#ibcon#first serial, iclass 38, count 0 2006.257.16:26:41.49#ibcon#enter sib2, iclass 38, count 0 2006.257.16:26:41.49#ibcon#flushed, iclass 38, count 0 2006.257.16:26:41.49#ibcon#about to write, iclass 38, count 0 2006.257.16:26:41.49#ibcon#wrote, iclass 38, count 0 2006.257.16:26:41.49#ibcon#about to read 3, iclass 38, count 0 2006.257.16:26:41.51#ibcon#read 3, iclass 38, count 0 2006.257.16:26:41.51#ibcon#about to read 4, iclass 38, count 0 2006.257.16:26:41.51#ibcon#read 4, iclass 38, count 0 2006.257.16:26:41.51#ibcon#about to read 5, iclass 38, count 0 2006.257.16:26:41.51#ibcon#read 5, iclass 38, count 0 2006.257.16:26:41.51#ibcon#about to read 6, iclass 38, count 0 2006.257.16:26:41.51#ibcon#read 6, iclass 38, count 0 2006.257.16:26:41.51#ibcon#end of sib2, iclass 38, count 0 2006.257.16:26:41.51#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:26:41.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:26:41.51#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.16:26:41.51#ibcon#*before write, iclass 38, count 0 2006.257.16:26:41.51#ibcon#enter sib2, iclass 38, count 0 2006.257.16:26:41.51#ibcon#flushed, iclass 38, count 0 2006.257.16:26:41.51#ibcon#about to write, iclass 38, count 0 2006.257.16:26:41.51#ibcon#wrote, iclass 38, count 0 2006.257.16:26:41.51#ibcon#about to read 3, iclass 38, count 0 2006.257.16:26:41.55#ibcon#read 3, iclass 38, count 0 2006.257.16:26:41.55#ibcon#about to read 4, iclass 38, count 0 2006.257.16:26:41.55#ibcon#read 4, iclass 38, count 0 2006.257.16:26:41.55#ibcon#about to read 5, iclass 38, count 0 2006.257.16:26:41.55#ibcon#read 5, iclass 38, count 0 2006.257.16:26:41.55#ibcon#about to read 6, iclass 38, count 0 2006.257.16:26:41.55#ibcon#read 6, iclass 38, count 0 2006.257.16:26:41.55#ibcon#end of sib2, iclass 38, count 0 2006.257.16:26:41.55#ibcon#*after write, iclass 38, count 0 2006.257.16:26:41.55#ibcon#*before return 0, iclass 38, count 0 2006.257.16:26:41.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:41.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:26:41.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:26:41.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:26:41.55$vck44/vb=2,5 2006.257.16:26:41.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.16:26:41.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.16:26:41.55#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:41.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:41.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:41.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:41.61#ibcon#enter wrdev, iclass 40, count 2 2006.257.16:26:41.61#ibcon#first serial, iclass 40, count 2 2006.257.16:26:41.61#ibcon#enter sib2, iclass 40, count 2 2006.257.16:26:41.61#ibcon#flushed, iclass 40, count 2 2006.257.16:26:41.61#ibcon#about to write, iclass 40, count 2 2006.257.16:26:41.61#ibcon#wrote, iclass 40, count 2 2006.257.16:26:41.61#ibcon#about to read 3, iclass 40, count 2 2006.257.16:26:41.63#ibcon#read 3, iclass 40, count 2 2006.257.16:26:41.63#ibcon#about to read 4, iclass 40, count 2 2006.257.16:26:41.63#ibcon#read 4, iclass 40, count 2 2006.257.16:26:41.63#ibcon#about to read 5, iclass 40, count 2 2006.257.16:26:41.63#ibcon#read 5, iclass 40, count 2 2006.257.16:26:41.63#ibcon#about to read 6, iclass 40, count 2 2006.257.16:26:41.63#ibcon#read 6, iclass 40, count 2 2006.257.16:26:41.63#ibcon#end of sib2, iclass 40, count 2 2006.257.16:26:41.63#ibcon#*mode == 0, iclass 40, count 2 2006.257.16:26:41.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.16:26:41.63#ibcon#[27=AT02-05\r\n] 2006.257.16:26:41.63#ibcon#*before write, iclass 40, count 2 2006.257.16:26:41.63#ibcon#enter sib2, iclass 40, count 2 2006.257.16:26:41.63#ibcon#flushed, iclass 40, count 2 2006.257.16:26:41.63#ibcon#about to write, iclass 40, count 2 2006.257.16:26:41.63#ibcon#wrote, iclass 40, count 2 2006.257.16:26:41.63#ibcon#about to read 3, iclass 40, count 2 2006.257.16:26:41.66#ibcon#read 3, iclass 40, count 2 2006.257.16:26:41.66#ibcon#about to read 4, iclass 40, count 2 2006.257.16:26:41.66#ibcon#read 4, iclass 40, count 2 2006.257.16:26:41.66#ibcon#about to read 5, iclass 40, count 2 2006.257.16:26:41.66#ibcon#read 5, iclass 40, count 2 2006.257.16:26:41.66#ibcon#about to read 6, iclass 40, count 2 2006.257.16:26:41.66#ibcon#read 6, iclass 40, count 2 2006.257.16:26:41.66#ibcon#end of sib2, iclass 40, count 2 2006.257.16:26:41.66#ibcon#*after write, iclass 40, count 2 2006.257.16:26:41.66#ibcon#*before return 0, iclass 40, count 2 2006.257.16:26:41.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:41.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:26:41.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.16:26:41.66#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:41.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:41.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:41.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:41.78#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:26:41.78#ibcon#first serial, iclass 40, count 0 2006.257.16:26:41.78#ibcon#enter sib2, iclass 40, count 0 2006.257.16:26:41.78#ibcon#flushed, iclass 40, count 0 2006.257.16:26:41.78#ibcon#about to write, iclass 40, count 0 2006.257.16:26:41.78#ibcon#wrote, iclass 40, count 0 2006.257.16:26:41.78#ibcon#about to read 3, iclass 40, count 0 2006.257.16:26:41.80#ibcon#read 3, iclass 40, count 0 2006.257.16:26:41.80#ibcon#about to read 4, iclass 40, count 0 2006.257.16:26:41.80#ibcon#read 4, iclass 40, count 0 2006.257.16:26:41.80#ibcon#about to read 5, iclass 40, count 0 2006.257.16:26:41.80#ibcon#read 5, iclass 40, count 0 2006.257.16:26:41.80#ibcon#about to read 6, iclass 40, count 0 2006.257.16:26:41.80#ibcon#read 6, iclass 40, count 0 2006.257.16:26:41.80#ibcon#end of sib2, iclass 40, count 0 2006.257.16:26:41.80#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:26:41.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:26:41.80#ibcon#[27=USB\r\n] 2006.257.16:26:41.80#ibcon#*before write, iclass 40, count 0 2006.257.16:26:41.80#ibcon#enter sib2, iclass 40, count 0 2006.257.16:26:41.80#ibcon#flushed, iclass 40, count 0 2006.257.16:26:41.80#ibcon#about to write, iclass 40, count 0 2006.257.16:26:41.80#ibcon#wrote, iclass 40, count 0 2006.257.16:26:41.80#ibcon#about to read 3, iclass 40, count 0 2006.257.16:26:41.83#ibcon#read 3, iclass 40, count 0 2006.257.16:26:41.83#ibcon#about to read 4, iclass 40, count 0 2006.257.16:26:41.83#ibcon#read 4, iclass 40, count 0 2006.257.16:26:41.83#ibcon#about to read 5, iclass 40, count 0 2006.257.16:26:41.83#ibcon#read 5, iclass 40, count 0 2006.257.16:26:41.83#ibcon#about to read 6, iclass 40, count 0 2006.257.16:26:41.83#ibcon#read 6, iclass 40, count 0 2006.257.16:26:41.83#ibcon#end of sib2, iclass 40, count 0 2006.257.16:26:41.83#ibcon#*after write, iclass 40, count 0 2006.257.16:26:41.83#ibcon#*before return 0, iclass 40, count 0 2006.257.16:26:41.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:41.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:26:41.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:26:41.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:26:41.83$vck44/vblo=3,649.99 2006.257.16:26:41.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.16:26:41.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.16:26:41.83#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:41.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:41.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:41.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:41.83#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:26:41.83#ibcon#first serial, iclass 4, count 0 2006.257.16:26:41.83#ibcon#enter sib2, iclass 4, count 0 2006.257.16:26:41.83#ibcon#flushed, iclass 4, count 0 2006.257.16:26:41.83#ibcon#about to write, iclass 4, count 0 2006.257.16:26:41.83#ibcon#wrote, iclass 4, count 0 2006.257.16:26:41.83#ibcon#about to read 3, iclass 4, count 0 2006.257.16:26:41.85#ibcon#read 3, iclass 4, count 0 2006.257.16:26:41.85#ibcon#about to read 4, iclass 4, count 0 2006.257.16:26:41.85#ibcon#read 4, iclass 4, count 0 2006.257.16:26:41.85#ibcon#about to read 5, iclass 4, count 0 2006.257.16:26:41.85#ibcon#read 5, iclass 4, count 0 2006.257.16:26:41.85#ibcon#about to read 6, iclass 4, count 0 2006.257.16:26:41.85#ibcon#read 6, iclass 4, count 0 2006.257.16:26:41.85#ibcon#end of sib2, iclass 4, count 0 2006.257.16:26:41.85#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:26:41.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:26:41.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.16:26:41.85#ibcon#*before write, iclass 4, count 0 2006.257.16:26:41.85#ibcon#enter sib2, iclass 4, count 0 2006.257.16:26:41.85#ibcon#flushed, iclass 4, count 0 2006.257.16:26:41.85#ibcon#about to write, iclass 4, count 0 2006.257.16:26:41.85#ibcon#wrote, iclass 4, count 0 2006.257.16:26:41.85#ibcon#about to read 3, iclass 4, count 0 2006.257.16:26:41.89#ibcon#read 3, iclass 4, count 0 2006.257.16:26:41.89#ibcon#about to read 4, iclass 4, count 0 2006.257.16:26:41.89#ibcon#read 4, iclass 4, count 0 2006.257.16:26:41.89#ibcon#about to read 5, iclass 4, count 0 2006.257.16:26:41.89#ibcon#read 5, iclass 4, count 0 2006.257.16:26:41.89#ibcon#about to read 6, iclass 4, count 0 2006.257.16:26:41.89#ibcon#read 6, iclass 4, count 0 2006.257.16:26:41.89#ibcon#end of sib2, iclass 4, count 0 2006.257.16:26:41.89#ibcon#*after write, iclass 4, count 0 2006.257.16:26:41.89#ibcon#*before return 0, iclass 4, count 0 2006.257.16:26:41.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:41.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:26:41.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:26:41.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:26:41.89$vck44/vb=3,4 2006.257.16:26:41.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.16:26:41.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.16:26:41.89#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:41.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:41.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:41.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:41.95#ibcon#enter wrdev, iclass 6, count 2 2006.257.16:26:41.95#ibcon#first serial, iclass 6, count 2 2006.257.16:26:41.95#ibcon#enter sib2, iclass 6, count 2 2006.257.16:26:41.95#ibcon#flushed, iclass 6, count 2 2006.257.16:26:41.95#ibcon#about to write, iclass 6, count 2 2006.257.16:26:41.95#ibcon#wrote, iclass 6, count 2 2006.257.16:26:41.95#ibcon#about to read 3, iclass 6, count 2 2006.257.16:26:41.97#ibcon#read 3, iclass 6, count 2 2006.257.16:26:41.97#ibcon#about to read 4, iclass 6, count 2 2006.257.16:26:41.97#ibcon#read 4, iclass 6, count 2 2006.257.16:26:41.97#ibcon#about to read 5, iclass 6, count 2 2006.257.16:26:41.97#ibcon#read 5, iclass 6, count 2 2006.257.16:26:41.97#ibcon#about to read 6, iclass 6, count 2 2006.257.16:26:41.97#ibcon#read 6, iclass 6, count 2 2006.257.16:26:41.97#ibcon#end of sib2, iclass 6, count 2 2006.257.16:26:41.97#ibcon#*mode == 0, iclass 6, count 2 2006.257.16:26:41.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.16:26:41.97#ibcon#[27=AT03-04\r\n] 2006.257.16:26:41.97#ibcon#*before write, iclass 6, count 2 2006.257.16:26:41.97#ibcon#enter sib2, iclass 6, count 2 2006.257.16:26:41.97#ibcon#flushed, iclass 6, count 2 2006.257.16:26:41.97#ibcon#about to write, iclass 6, count 2 2006.257.16:26:41.97#ibcon#wrote, iclass 6, count 2 2006.257.16:26:41.97#ibcon#about to read 3, iclass 6, count 2 2006.257.16:26:42.00#ibcon#read 3, iclass 6, count 2 2006.257.16:26:42.00#ibcon#about to read 4, iclass 6, count 2 2006.257.16:26:42.00#ibcon#read 4, iclass 6, count 2 2006.257.16:26:42.00#ibcon#about to read 5, iclass 6, count 2 2006.257.16:26:42.00#ibcon#read 5, iclass 6, count 2 2006.257.16:26:42.00#ibcon#about to read 6, iclass 6, count 2 2006.257.16:26:42.00#ibcon#read 6, iclass 6, count 2 2006.257.16:26:42.00#ibcon#end of sib2, iclass 6, count 2 2006.257.16:26:42.00#ibcon#*after write, iclass 6, count 2 2006.257.16:26:42.00#ibcon#*before return 0, iclass 6, count 2 2006.257.16:26:42.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:42.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:26:42.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.16:26:42.00#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:42.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:42.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:42.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:42.12#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:26:42.12#ibcon#first serial, iclass 6, count 0 2006.257.16:26:42.12#ibcon#enter sib2, iclass 6, count 0 2006.257.16:26:42.12#ibcon#flushed, iclass 6, count 0 2006.257.16:26:42.12#ibcon#about to write, iclass 6, count 0 2006.257.16:26:42.12#ibcon#wrote, iclass 6, count 0 2006.257.16:26:42.12#ibcon#about to read 3, iclass 6, count 0 2006.257.16:26:42.14#ibcon#read 3, iclass 6, count 0 2006.257.16:26:42.14#ibcon#about to read 4, iclass 6, count 0 2006.257.16:26:42.14#ibcon#read 4, iclass 6, count 0 2006.257.16:26:42.14#ibcon#about to read 5, iclass 6, count 0 2006.257.16:26:42.14#ibcon#read 5, iclass 6, count 0 2006.257.16:26:42.14#ibcon#about to read 6, iclass 6, count 0 2006.257.16:26:42.14#ibcon#read 6, iclass 6, count 0 2006.257.16:26:42.14#ibcon#end of sib2, iclass 6, count 0 2006.257.16:26:42.14#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:26:42.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:26:42.14#ibcon#[27=USB\r\n] 2006.257.16:26:42.14#ibcon#*before write, iclass 6, count 0 2006.257.16:26:42.14#ibcon#enter sib2, iclass 6, count 0 2006.257.16:26:42.14#ibcon#flushed, iclass 6, count 0 2006.257.16:26:42.14#ibcon#about to write, iclass 6, count 0 2006.257.16:26:42.14#ibcon#wrote, iclass 6, count 0 2006.257.16:26:42.14#ibcon#about to read 3, iclass 6, count 0 2006.257.16:26:42.17#ibcon#read 3, iclass 6, count 0 2006.257.16:26:42.17#ibcon#about to read 4, iclass 6, count 0 2006.257.16:26:42.17#ibcon#read 4, iclass 6, count 0 2006.257.16:26:42.17#ibcon#about to read 5, iclass 6, count 0 2006.257.16:26:42.17#ibcon#read 5, iclass 6, count 0 2006.257.16:26:42.17#ibcon#about to read 6, iclass 6, count 0 2006.257.16:26:42.17#ibcon#read 6, iclass 6, count 0 2006.257.16:26:42.17#ibcon#end of sib2, iclass 6, count 0 2006.257.16:26:42.17#ibcon#*after write, iclass 6, count 0 2006.257.16:26:42.17#ibcon#*before return 0, iclass 6, count 0 2006.257.16:26:42.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:42.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:26:42.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:26:42.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:26:42.17$vck44/vblo=4,679.99 2006.257.16:26:42.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.16:26:42.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.16:26:42.17#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:42.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:42.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:42.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:42.17#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:26:42.17#ibcon#first serial, iclass 10, count 0 2006.257.16:26:42.17#ibcon#enter sib2, iclass 10, count 0 2006.257.16:26:42.17#ibcon#flushed, iclass 10, count 0 2006.257.16:26:42.17#ibcon#about to write, iclass 10, count 0 2006.257.16:26:42.17#ibcon#wrote, iclass 10, count 0 2006.257.16:26:42.17#ibcon#about to read 3, iclass 10, count 0 2006.257.16:26:42.19#ibcon#read 3, iclass 10, count 0 2006.257.16:26:42.19#ibcon#about to read 4, iclass 10, count 0 2006.257.16:26:42.19#ibcon#read 4, iclass 10, count 0 2006.257.16:26:42.19#ibcon#about to read 5, iclass 10, count 0 2006.257.16:26:42.19#ibcon#read 5, iclass 10, count 0 2006.257.16:26:42.19#ibcon#about to read 6, iclass 10, count 0 2006.257.16:26:42.19#ibcon#read 6, iclass 10, count 0 2006.257.16:26:42.19#ibcon#end of sib2, iclass 10, count 0 2006.257.16:26:42.19#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:26:42.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:26:42.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.16:26:42.19#ibcon#*before write, iclass 10, count 0 2006.257.16:26:42.19#ibcon#enter sib2, iclass 10, count 0 2006.257.16:26:42.19#ibcon#flushed, iclass 10, count 0 2006.257.16:26:42.19#ibcon#about to write, iclass 10, count 0 2006.257.16:26:42.19#ibcon#wrote, iclass 10, count 0 2006.257.16:26:42.19#ibcon#about to read 3, iclass 10, count 0 2006.257.16:26:42.23#ibcon#read 3, iclass 10, count 0 2006.257.16:26:42.23#ibcon#about to read 4, iclass 10, count 0 2006.257.16:26:42.23#ibcon#read 4, iclass 10, count 0 2006.257.16:26:42.23#ibcon#about to read 5, iclass 10, count 0 2006.257.16:26:42.23#ibcon#read 5, iclass 10, count 0 2006.257.16:26:42.23#ibcon#about to read 6, iclass 10, count 0 2006.257.16:26:42.23#ibcon#read 6, iclass 10, count 0 2006.257.16:26:42.23#ibcon#end of sib2, iclass 10, count 0 2006.257.16:26:42.23#ibcon#*after write, iclass 10, count 0 2006.257.16:26:42.23#ibcon#*before return 0, iclass 10, count 0 2006.257.16:26:42.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:42.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:26:42.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:26:42.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:26:42.23$vck44/vb=4,5 2006.257.16:26:42.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.16:26:42.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.16:26:42.23#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:42.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:42.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:42.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:42.29#ibcon#enter wrdev, iclass 12, count 2 2006.257.16:26:42.29#ibcon#first serial, iclass 12, count 2 2006.257.16:26:42.29#ibcon#enter sib2, iclass 12, count 2 2006.257.16:26:42.29#ibcon#flushed, iclass 12, count 2 2006.257.16:26:42.29#ibcon#about to write, iclass 12, count 2 2006.257.16:26:42.29#ibcon#wrote, iclass 12, count 2 2006.257.16:26:42.29#ibcon#about to read 3, iclass 12, count 2 2006.257.16:26:42.31#ibcon#read 3, iclass 12, count 2 2006.257.16:26:42.31#ibcon#about to read 4, iclass 12, count 2 2006.257.16:26:42.31#ibcon#read 4, iclass 12, count 2 2006.257.16:26:42.31#ibcon#about to read 5, iclass 12, count 2 2006.257.16:26:42.31#ibcon#read 5, iclass 12, count 2 2006.257.16:26:42.31#ibcon#about to read 6, iclass 12, count 2 2006.257.16:26:42.31#ibcon#read 6, iclass 12, count 2 2006.257.16:26:42.31#ibcon#end of sib2, iclass 12, count 2 2006.257.16:26:42.31#ibcon#*mode == 0, iclass 12, count 2 2006.257.16:26:42.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.16:26:42.31#ibcon#[27=AT04-05\r\n] 2006.257.16:26:42.31#ibcon#*before write, iclass 12, count 2 2006.257.16:26:42.31#ibcon#enter sib2, iclass 12, count 2 2006.257.16:26:42.31#ibcon#flushed, iclass 12, count 2 2006.257.16:26:42.31#ibcon#about to write, iclass 12, count 2 2006.257.16:26:42.31#ibcon#wrote, iclass 12, count 2 2006.257.16:26:42.31#ibcon#about to read 3, iclass 12, count 2 2006.257.16:26:42.34#ibcon#read 3, iclass 12, count 2 2006.257.16:26:42.34#ibcon#about to read 4, iclass 12, count 2 2006.257.16:26:42.34#ibcon#read 4, iclass 12, count 2 2006.257.16:26:42.34#ibcon#about to read 5, iclass 12, count 2 2006.257.16:26:42.34#ibcon#read 5, iclass 12, count 2 2006.257.16:26:42.34#ibcon#about to read 6, iclass 12, count 2 2006.257.16:26:42.34#ibcon#read 6, iclass 12, count 2 2006.257.16:26:42.34#ibcon#end of sib2, iclass 12, count 2 2006.257.16:26:42.34#ibcon#*after write, iclass 12, count 2 2006.257.16:26:42.34#ibcon#*before return 0, iclass 12, count 2 2006.257.16:26:42.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:42.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:26:42.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.16:26:42.34#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:42.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:42.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:42.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:42.46#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:26:42.46#ibcon#first serial, iclass 12, count 0 2006.257.16:26:42.46#ibcon#enter sib2, iclass 12, count 0 2006.257.16:26:42.46#ibcon#flushed, iclass 12, count 0 2006.257.16:26:42.46#ibcon#about to write, iclass 12, count 0 2006.257.16:26:42.46#ibcon#wrote, iclass 12, count 0 2006.257.16:26:42.46#ibcon#about to read 3, iclass 12, count 0 2006.257.16:26:42.48#ibcon#read 3, iclass 12, count 0 2006.257.16:26:42.48#ibcon#about to read 4, iclass 12, count 0 2006.257.16:26:42.48#ibcon#read 4, iclass 12, count 0 2006.257.16:26:42.48#ibcon#about to read 5, iclass 12, count 0 2006.257.16:26:42.48#ibcon#read 5, iclass 12, count 0 2006.257.16:26:42.48#ibcon#about to read 6, iclass 12, count 0 2006.257.16:26:42.48#ibcon#read 6, iclass 12, count 0 2006.257.16:26:42.48#ibcon#end of sib2, iclass 12, count 0 2006.257.16:26:42.48#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:26:42.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:26:42.48#ibcon#[27=USB\r\n] 2006.257.16:26:42.48#ibcon#*before write, iclass 12, count 0 2006.257.16:26:42.48#ibcon#enter sib2, iclass 12, count 0 2006.257.16:26:42.48#ibcon#flushed, iclass 12, count 0 2006.257.16:26:42.48#ibcon#about to write, iclass 12, count 0 2006.257.16:26:42.48#ibcon#wrote, iclass 12, count 0 2006.257.16:26:42.48#ibcon#about to read 3, iclass 12, count 0 2006.257.16:26:42.51#ibcon#read 3, iclass 12, count 0 2006.257.16:26:42.51#ibcon#about to read 4, iclass 12, count 0 2006.257.16:26:42.51#ibcon#read 4, iclass 12, count 0 2006.257.16:26:42.51#ibcon#about to read 5, iclass 12, count 0 2006.257.16:26:42.51#ibcon#read 5, iclass 12, count 0 2006.257.16:26:42.51#ibcon#about to read 6, iclass 12, count 0 2006.257.16:26:42.51#ibcon#read 6, iclass 12, count 0 2006.257.16:26:42.51#ibcon#end of sib2, iclass 12, count 0 2006.257.16:26:42.51#ibcon#*after write, iclass 12, count 0 2006.257.16:26:42.51#ibcon#*before return 0, iclass 12, count 0 2006.257.16:26:42.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:42.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:26:42.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:26:42.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:26:42.51$vck44/vblo=5,709.99 2006.257.16:26:42.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.16:26:42.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.16:26:42.51#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:42.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:42.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:42.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:42.51#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:26:42.51#ibcon#first serial, iclass 14, count 0 2006.257.16:26:42.51#ibcon#enter sib2, iclass 14, count 0 2006.257.16:26:42.51#ibcon#flushed, iclass 14, count 0 2006.257.16:26:42.51#ibcon#about to write, iclass 14, count 0 2006.257.16:26:42.51#ibcon#wrote, iclass 14, count 0 2006.257.16:26:42.51#ibcon#about to read 3, iclass 14, count 0 2006.257.16:26:42.53#ibcon#read 3, iclass 14, count 0 2006.257.16:26:42.53#ibcon#about to read 4, iclass 14, count 0 2006.257.16:26:42.53#ibcon#read 4, iclass 14, count 0 2006.257.16:26:42.53#ibcon#about to read 5, iclass 14, count 0 2006.257.16:26:42.53#ibcon#read 5, iclass 14, count 0 2006.257.16:26:42.53#ibcon#about to read 6, iclass 14, count 0 2006.257.16:26:42.53#ibcon#read 6, iclass 14, count 0 2006.257.16:26:42.53#ibcon#end of sib2, iclass 14, count 0 2006.257.16:26:42.53#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:26:42.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:26:42.53#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:26:42.53#ibcon#*before write, iclass 14, count 0 2006.257.16:26:42.53#ibcon#enter sib2, iclass 14, count 0 2006.257.16:26:42.53#ibcon#flushed, iclass 14, count 0 2006.257.16:26:42.53#ibcon#about to write, iclass 14, count 0 2006.257.16:26:42.53#ibcon#wrote, iclass 14, count 0 2006.257.16:26:42.53#ibcon#about to read 3, iclass 14, count 0 2006.257.16:26:42.57#ibcon#read 3, iclass 14, count 0 2006.257.16:26:42.57#ibcon#about to read 4, iclass 14, count 0 2006.257.16:26:42.57#ibcon#read 4, iclass 14, count 0 2006.257.16:26:42.57#ibcon#about to read 5, iclass 14, count 0 2006.257.16:26:42.57#ibcon#read 5, iclass 14, count 0 2006.257.16:26:42.57#ibcon#about to read 6, iclass 14, count 0 2006.257.16:26:42.57#ibcon#read 6, iclass 14, count 0 2006.257.16:26:42.57#ibcon#end of sib2, iclass 14, count 0 2006.257.16:26:42.57#ibcon#*after write, iclass 14, count 0 2006.257.16:26:42.57#ibcon#*before return 0, iclass 14, count 0 2006.257.16:26:42.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:42.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:26:42.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:26:42.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:26:42.57$vck44/vb=5,4 2006.257.16:26:42.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.16:26:42.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.16:26:42.57#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:42.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:42.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:42.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:42.63#ibcon#enter wrdev, iclass 16, count 2 2006.257.16:26:42.63#ibcon#first serial, iclass 16, count 2 2006.257.16:26:42.63#ibcon#enter sib2, iclass 16, count 2 2006.257.16:26:42.63#ibcon#flushed, iclass 16, count 2 2006.257.16:26:42.63#ibcon#about to write, iclass 16, count 2 2006.257.16:26:42.63#ibcon#wrote, iclass 16, count 2 2006.257.16:26:42.63#ibcon#about to read 3, iclass 16, count 2 2006.257.16:26:42.65#ibcon#read 3, iclass 16, count 2 2006.257.16:26:42.65#ibcon#about to read 4, iclass 16, count 2 2006.257.16:26:42.65#ibcon#read 4, iclass 16, count 2 2006.257.16:26:42.65#ibcon#about to read 5, iclass 16, count 2 2006.257.16:26:42.65#ibcon#read 5, iclass 16, count 2 2006.257.16:26:42.65#ibcon#about to read 6, iclass 16, count 2 2006.257.16:26:42.65#ibcon#read 6, iclass 16, count 2 2006.257.16:26:42.65#ibcon#end of sib2, iclass 16, count 2 2006.257.16:26:42.65#ibcon#*mode == 0, iclass 16, count 2 2006.257.16:26:42.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.16:26:42.65#ibcon#[27=AT05-04\r\n] 2006.257.16:26:42.65#ibcon#*before write, iclass 16, count 2 2006.257.16:26:42.65#ibcon#enter sib2, iclass 16, count 2 2006.257.16:26:42.65#ibcon#flushed, iclass 16, count 2 2006.257.16:26:42.65#ibcon#about to write, iclass 16, count 2 2006.257.16:26:42.65#ibcon#wrote, iclass 16, count 2 2006.257.16:26:42.65#ibcon#about to read 3, iclass 16, count 2 2006.257.16:26:42.68#ibcon#read 3, iclass 16, count 2 2006.257.16:26:42.68#ibcon#about to read 4, iclass 16, count 2 2006.257.16:26:42.68#ibcon#read 4, iclass 16, count 2 2006.257.16:26:42.68#ibcon#about to read 5, iclass 16, count 2 2006.257.16:26:42.68#ibcon#read 5, iclass 16, count 2 2006.257.16:26:42.68#ibcon#about to read 6, iclass 16, count 2 2006.257.16:26:42.68#ibcon#read 6, iclass 16, count 2 2006.257.16:26:42.68#ibcon#end of sib2, iclass 16, count 2 2006.257.16:26:42.68#ibcon#*after write, iclass 16, count 2 2006.257.16:26:42.68#ibcon#*before return 0, iclass 16, count 2 2006.257.16:26:42.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:42.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:26:42.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.16:26:42.68#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:42.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:42.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:42.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:42.80#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:26:42.80#ibcon#first serial, iclass 16, count 0 2006.257.16:26:42.80#ibcon#enter sib2, iclass 16, count 0 2006.257.16:26:42.80#ibcon#flushed, iclass 16, count 0 2006.257.16:26:42.80#ibcon#about to write, iclass 16, count 0 2006.257.16:26:42.80#ibcon#wrote, iclass 16, count 0 2006.257.16:26:42.80#ibcon#about to read 3, iclass 16, count 0 2006.257.16:26:42.82#ibcon#read 3, iclass 16, count 0 2006.257.16:26:42.82#ibcon#about to read 4, iclass 16, count 0 2006.257.16:26:42.82#ibcon#read 4, iclass 16, count 0 2006.257.16:26:42.82#ibcon#about to read 5, iclass 16, count 0 2006.257.16:26:42.82#ibcon#read 5, iclass 16, count 0 2006.257.16:26:42.82#ibcon#about to read 6, iclass 16, count 0 2006.257.16:26:42.82#ibcon#read 6, iclass 16, count 0 2006.257.16:26:42.82#ibcon#end of sib2, iclass 16, count 0 2006.257.16:26:42.82#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:26:42.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:26:42.82#ibcon#[27=USB\r\n] 2006.257.16:26:42.82#ibcon#*before write, iclass 16, count 0 2006.257.16:26:42.82#ibcon#enter sib2, iclass 16, count 0 2006.257.16:26:42.82#ibcon#flushed, iclass 16, count 0 2006.257.16:26:42.82#ibcon#about to write, iclass 16, count 0 2006.257.16:26:42.82#ibcon#wrote, iclass 16, count 0 2006.257.16:26:42.82#ibcon#about to read 3, iclass 16, count 0 2006.257.16:26:42.85#ibcon#read 3, iclass 16, count 0 2006.257.16:26:42.85#ibcon#about to read 4, iclass 16, count 0 2006.257.16:26:42.85#ibcon#read 4, iclass 16, count 0 2006.257.16:26:42.85#ibcon#about to read 5, iclass 16, count 0 2006.257.16:26:42.85#ibcon#read 5, iclass 16, count 0 2006.257.16:26:42.85#ibcon#about to read 6, iclass 16, count 0 2006.257.16:26:42.85#ibcon#read 6, iclass 16, count 0 2006.257.16:26:42.85#ibcon#end of sib2, iclass 16, count 0 2006.257.16:26:42.85#ibcon#*after write, iclass 16, count 0 2006.257.16:26:42.85#ibcon#*before return 0, iclass 16, count 0 2006.257.16:26:42.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:42.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:26:42.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:26:42.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:26:42.85$vck44/vblo=6,719.99 2006.257.16:26:42.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.16:26:42.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.16:26:42.85#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:42.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:42.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:42.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:42.85#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:26:42.85#ibcon#first serial, iclass 18, count 0 2006.257.16:26:42.85#ibcon#enter sib2, iclass 18, count 0 2006.257.16:26:42.85#ibcon#flushed, iclass 18, count 0 2006.257.16:26:42.85#ibcon#about to write, iclass 18, count 0 2006.257.16:26:42.85#ibcon#wrote, iclass 18, count 0 2006.257.16:26:42.85#ibcon#about to read 3, iclass 18, count 0 2006.257.16:26:42.87#ibcon#read 3, iclass 18, count 0 2006.257.16:26:42.87#ibcon#about to read 4, iclass 18, count 0 2006.257.16:26:42.87#ibcon#read 4, iclass 18, count 0 2006.257.16:26:42.87#ibcon#about to read 5, iclass 18, count 0 2006.257.16:26:42.87#ibcon#read 5, iclass 18, count 0 2006.257.16:26:42.87#ibcon#about to read 6, iclass 18, count 0 2006.257.16:26:42.87#ibcon#read 6, iclass 18, count 0 2006.257.16:26:42.87#ibcon#end of sib2, iclass 18, count 0 2006.257.16:26:42.87#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:26:42.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:26:42.87#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:26:42.87#ibcon#*before write, iclass 18, count 0 2006.257.16:26:42.87#ibcon#enter sib2, iclass 18, count 0 2006.257.16:26:42.87#ibcon#flushed, iclass 18, count 0 2006.257.16:26:42.87#ibcon#about to write, iclass 18, count 0 2006.257.16:26:42.87#ibcon#wrote, iclass 18, count 0 2006.257.16:26:42.87#ibcon#about to read 3, iclass 18, count 0 2006.257.16:26:42.91#ibcon#read 3, iclass 18, count 0 2006.257.16:26:42.91#ibcon#about to read 4, iclass 18, count 0 2006.257.16:26:42.91#ibcon#read 4, iclass 18, count 0 2006.257.16:26:42.91#ibcon#about to read 5, iclass 18, count 0 2006.257.16:26:42.91#ibcon#read 5, iclass 18, count 0 2006.257.16:26:42.91#ibcon#about to read 6, iclass 18, count 0 2006.257.16:26:42.91#ibcon#read 6, iclass 18, count 0 2006.257.16:26:42.91#ibcon#end of sib2, iclass 18, count 0 2006.257.16:26:42.91#ibcon#*after write, iclass 18, count 0 2006.257.16:26:42.91#ibcon#*before return 0, iclass 18, count 0 2006.257.16:26:42.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:42.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:26:42.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:26:42.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:26:42.91$vck44/vb=6,4 2006.257.16:26:42.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.16:26:42.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.16:26:42.91#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:42.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:42.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:42.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:42.97#ibcon#enter wrdev, iclass 20, count 2 2006.257.16:26:42.97#ibcon#first serial, iclass 20, count 2 2006.257.16:26:42.97#ibcon#enter sib2, iclass 20, count 2 2006.257.16:26:42.97#ibcon#flushed, iclass 20, count 2 2006.257.16:26:42.97#ibcon#about to write, iclass 20, count 2 2006.257.16:26:42.97#ibcon#wrote, iclass 20, count 2 2006.257.16:26:42.97#ibcon#about to read 3, iclass 20, count 2 2006.257.16:26:42.99#ibcon#read 3, iclass 20, count 2 2006.257.16:26:42.99#ibcon#about to read 4, iclass 20, count 2 2006.257.16:26:42.99#ibcon#read 4, iclass 20, count 2 2006.257.16:26:42.99#ibcon#about to read 5, iclass 20, count 2 2006.257.16:26:42.99#ibcon#read 5, iclass 20, count 2 2006.257.16:26:42.99#ibcon#about to read 6, iclass 20, count 2 2006.257.16:26:42.99#ibcon#read 6, iclass 20, count 2 2006.257.16:26:42.99#ibcon#end of sib2, iclass 20, count 2 2006.257.16:26:42.99#ibcon#*mode == 0, iclass 20, count 2 2006.257.16:26:42.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.16:26:42.99#ibcon#[27=AT06-04\r\n] 2006.257.16:26:42.99#ibcon#*before write, iclass 20, count 2 2006.257.16:26:42.99#ibcon#enter sib2, iclass 20, count 2 2006.257.16:26:42.99#ibcon#flushed, iclass 20, count 2 2006.257.16:26:42.99#ibcon#about to write, iclass 20, count 2 2006.257.16:26:42.99#ibcon#wrote, iclass 20, count 2 2006.257.16:26:42.99#ibcon#about to read 3, iclass 20, count 2 2006.257.16:26:43.02#ibcon#read 3, iclass 20, count 2 2006.257.16:26:43.02#ibcon#about to read 4, iclass 20, count 2 2006.257.16:26:43.02#ibcon#read 4, iclass 20, count 2 2006.257.16:26:43.02#ibcon#about to read 5, iclass 20, count 2 2006.257.16:26:43.02#ibcon#read 5, iclass 20, count 2 2006.257.16:26:43.02#ibcon#about to read 6, iclass 20, count 2 2006.257.16:26:43.02#ibcon#read 6, iclass 20, count 2 2006.257.16:26:43.02#ibcon#end of sib2, iclass 20, count 2 2006.257.16:26:43.02#ibcon#*after write, iclass 20, count 2 2006.257.16:26:43.02#ibcon#*before return 0, iclass 20, count 2 2006.257.16:26:43.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:43.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:26:43.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.16:26:43.02#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:43.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:43.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:43.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:43.14#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:26:43.14#ibcon#first serial, iclass 20, count 0 2006.257.16:26:43.14#ibcon#enter sib2, iclass 20, count 0 2006.257.16:26:43.14#ibcon#flushed, iclass 20, count 0 2006.257.16:26:43.14#ibcon#about to write, iclass 20, count 0 2006.257.16:26:43.14#ibcon#wrote, iclass 20, count 0 2006.257.16:26:43.14#ibcon#about to read 3, iclass 20, count 0 2006.257.16:26:43.16#ibcon#read 3, iclass 20, count 0 2006.257.16:26:43.16#ibcon#about to read 4, iclass 20, count 0 2006.257.16:26:43.16#ibcon#read 4, iclass 20, count 0 2006.257.16:26:43.16#ibcon#about to read 5, iclass 20, count 0 2006.257.16:26:43.16#ibcon#read 5, iclass 20, count 0 2006.257.16:26:43.16#ibcon#about to read 6, iclass 20, count 0 2006.257.16:26:43.16#ibcon#read 6, iclass 20, count 0 2006.257.16:26:43.16#ibcon#end of sib2, iclass 20, count 0 2006.257.16:26:43.16#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:26:43.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:26:43.16#ibcon#[27=USB\r\n] 2006.257.16:26:43.16#ibcon#*before write, iclass 20, count 0 2006.257.16:26:43.16#ibcon#enter sib2, iclass 20, count 0 2006.257.16:26:43.16#ibcon#flushed, iclass 20, count 0 2006.257.16:26:43.16#ibcon#about to write, iclass 20, count 0 2006.257.16:26:43.16#ibcon#wrote, iclass 20, count 0 2006.257.16:26:43.16#ibcon#about to read 3, iclass 20, count 0 2006.257.16:26:43.19#ibcon#read 3, iclass 20, count 0 2006.257.16:26:43.19#ibcon#about to read 4, iclass 20, count 0 2006.257.16:26:43.19#ibcon#read 4, iclass 20, count 0 2006.257.16:26:43.19#ibcon#about to read 5, iclass 20, count 0 2006.257.16:26:43.19#ibcon#read 5, iclass 20, count 0 2006.257.16:26:43.19#ibcon#about to read 6, iclass 20, count 0 2006.257.16:26:43.19#ibcon#read 6, iclass 20, count 0 2006.257.16:26:43.19#ibcon#end of sib2, iclass 20, count 0 2006.257.16:26:43.19#ibcon#*after write, iclass 20, count 0 2006.257.16:26:43.19#ibcon#*before return 0, iclass 20, count 0 2006.257.16:26:43.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:43.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:26:43.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:26:43.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:26:43.19$vck44/vblo=7,734.99 2006.257.16:26:43.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.16:26:43.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.16:26:43.19#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:43.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:43.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:43.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:43.19#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:26:43.19#ibcon#first serial, iclass 22, count 0 2006.257.16:26:43.19#ibcon#enter sib2, iclass 22, count 0 2006.257.16:26:43.19#ibcon#flushed, iclass 22, count 0 2006.257.16:26:43.19#ibcon#about to write, iclass 22, count 0 2006.257.16:26:43.19#ibcon#wrote, iclass 22, count 0 2006.257.16:26:43.19#ibcon#about to read 3, iclass 22, count 0 2006.257.16:26:43.21#ibcon#read 3, iclass 22, count 0 2006.257.16:26:43.21#ibcon#about to read 4, iclass 22, count 0 2006.257.16:26:43.21#ibcon#read 4, iclass 22, count 0 2006.257.16:26:43.21#ibcon#about to read 5, iclass 22, count 0 2006.257.16:26:43.21#ibcon#read 5, iclass 22, count 0 2006.257.16:26:43.21#ibcon#about to read 6, iclass 22, count 0 2006.257.16:26:43.21#ibcon#read 6, iclass 22, count 0 2006.257.16:26:43.21#ibcon#end of sib2, iclass 22, count 0 2006.257.16:26:43.21#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:26:43.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:26:43.21#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:26:43.21#ibcon#*before write, iclass 22, count 0 2006.257.16:26:43.21#ibcon#enter sib2, iclass 22, count 0 2006.257.16:26:43.21#ibcon#flushed, iclass 22, count 0 2006.257.16:26:43.21#ibcon#about to write, iclass 22, count 0 2006.257.16:26:43.21#ibcon#wrote, iclass 22, count 0 2006.257.16:26:43.21#ibcon#about to read 3, iclass 22, count 0 2006.257.16:26:43.25#ibcon#read 3, iclass 22, count 0 2006.257.16:26:43.25#ibcon#about to read 4, iclass 22, count 0 2006.257.16:26:43.25#ibcon#read 4, iclass 22, count 0 2006.257.16:26:43.25#ibcon#about to read 5, iclass 22, count 0 2006.257.16:26:43.25#ibcon#read 5, iclass 22, count 0 2006.257.16:26:43.25#ibcon#about to read 6, iclass 22, count 0 2006.257.16:26:43.25#ibcon#read 6, iclass 22, count 0 2006.257.16:26:43.25#ibcon#end of sib2, iclass 22, count 0 2006.257.16:26:43.25#ibcon#*after write, iclass 22, count 0 2006.257.16:26:43.25#ibcon#*before return 0, iclass 22, count 0 2006.257.16:26:43.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:43.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:26:43.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:26:43.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:26:43.25$vck44/vb=7,4 2006.257.16:26:43.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.16:26:43.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.16:26:43.25#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:43.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:43.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:43.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:43.31#ibcon#enter wrdev, iclass 24, count 2 2006.257.16:26:43.31#ibcon#first serial, iclass 24, count 2 2006.257.16:26:43.31#ibcon#enter sib2, iclass 24, count 2 2006.257.16:26:43.31#ibcon#flushed, iclass 24, count 2 2006.257.16:26:43.31#ibcon#about to write, iclass 24, count 2 2006.257.16:26:43.31#ibcon#wrote, iclass 24, count 2 2006.257.16:26:43.31#ibcon#about to read 3, iclass 24, count 2 2006.257.16:26:43.33#ibcon#read 3, iclass 24, count 2 2006.257.16:26:43.33#ibcon#about to read 4, iclass 24, count 2 2006.257.16:26:43.33#ibcon#read 4, iclass 24, count 2 2006.257.16:26:43.33#ibcon#about to read 5, iclass 24, count 2 2006.257.16:26:43.33#ibcon#read 5, iclass 24, count 2 2006.257.16:26:43.33#ibcon#about to read 6, iclass 24, count 2 2006.257.16:26:43.33#ibcon#read 6, iclass 24, count 2 2006.257.16:26:43.33#ibcon#end of sib2, iclass 24, count 2 2006.257.16:26:43.33#ibcon#*mode == 0, iclass 24, count 2 2006.257.16:26:43.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.16:26:43.33#ibcon#[27=AT07-04\r\n] 2006.257.16:26:43.33#ibcon#*before write, iclass 24, count 2 2006.257.16:26:43.33#ibcon#enter sib2, iclass 24, count 2 2006.257.16:26:43.33#ibcon#flushed, iclass 24, count 2 2006.257.16:26:43.33#ibcon#about to write, iclass 24, count 2 2006.257.16:26:43.33#ibcon#wrote, iclass 24, count 2 2006.257.16:26:43.33#ibcon#about to read 3, iclass 24, count 2 2006.257.16:26:43.36#ibcon#read 3, iclass 24, count 2 2006.257.16:26:43.36#ibcon#about to read 4, iclass 24, count 2 2006.257.16:26:43.36#ibcon#read 4, iclass 24, count 2 2006.257.16:26:43.36#ibcon#about to read 5, iclass 24, count 2 2006.257.16:26:43.36#ibcon#read 5, iclass 24, count 2 2006.257.16:26:43.36#ibcon#about to read 6, iclass 24, count 2 2006.257.16:26:43.36#ibcon#read 6, iclass 24, count 2 2006.257.16:26:43.36#ibcon#end of sib2, iclass 24, count 2 2006.257.16:26:43.36#ibcon#*after write, iclass 24, count 2 2006.257.16:26:43.36#ibcon#*before return 0, iclass 24, count 2 2006.257.16:26:43.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:43.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:26:43.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.16:26:43.36#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:43.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:43.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:43.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:43.48#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:26:43.48#ibcon#first serial, iclass 24, count 0 2006.257.16:26:43.48#ibcon#enter sib2, iclass 24, count 0 2006.257.16:26:43.48#ibcon#flushed, iclass 24, count 0 2006.257.16:26:43.48#ibcon#about to write, iclass 24, count 0 2006.257.16:26:43.48#ibcon#wrote, iclass 24, count 0 2006.257.16:26:43.48#ibcon#about to read 3, iclass 24, count 0 2006.257.16:26:43.50#ibcon#read 3, iclass 24, count 0 2006.257.16:26:43.50#ibcon#about to read 4, iclass 24, count 0 2006.257.16:26:43.50#ibcon#read 4, iclass 24, count 0 2006.257.16:26:43.50#ibcon#about to read 5, iclass 24, count 0 2006.257.16:26:43.50#ibcon#read 5, iclass 24, count 0 2006.257.16:26:43.50#ibcon#about to read 6, iclass 24, count 0 2006.257.16:26:43.50#ibcon#read 6, iclass 24, count 0 2006.257.16:26:43.50#ibcon#end of sib2, iclass 24, count 0 2006.257.16:26:43.50#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:26:43.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:26:43.50#ibcon#[27=USB\r\n] 2006.257.16:26:43.50#ibcon#*before write, iclass 24, count 0 2006.257.16:26:43.50#ibcon#enter sib2, iclass 24, count 0 2006.257.16:26:43.50#ibcon#flushed, iclass 24, count 0 2006.257.16:26:43.50#ibcon#about to write, iclass 24, count 0 2006.257.16:26:43.50#ibcon#wrote, iclass 24, count 0 2006.257.16:26:43.50#ibcon#about to read 3, iclass 24, count 0 2006.257.16:26:43.53#ibcon#read 3, iclass 24, count 0 2006.257.16:26:43.53#ibcon#about to read 4, iclass 24, count 0 2006.257.16:26:43.53#ibcon#read 4, iclass 24, count 0 2006.257.16:26:43.53#ibcon#about to read 5, iclass 24, count 0 2006.257.16:26:43.53#ibcon#read 5, iclass 24, count 0 2006.257.16:26:43.53#ibcon#about to read 6, iclass 24, count 0 2006.257.16:26:43.53#ibcon#read 6, iclass 24, count 0 2006.257.16:26:43.53#ibcon#end of sib2, iclass 24, count 0 2006.257.16:26:43.53#ibcon#*after write, iclass 24, count 0 2006.257.16:26:43.53#ibcon#*before return 0, iclass 24, count 0 2006.257.16:26:43.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:43.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:26:43.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:26:43.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:26:43.53$vck44/vblo=8,744.99 2006.257.16:26:43.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.16:26:43.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.16:26:43.53#ibcon#ireg 17 cls_cnt 0 2006.257.16:26:43.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:43.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:43.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:43.53#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:26:43.53#ibcon#first serial, iclass 26, count 0 2006.257.16:26:43.53#ibcon#enter sib2, iclass 26, count 0 2006.257.16:26:43.53#ibcon#flushed, iclass 26, count 0 2006.257.16:26:43.53#ibcon#about to write, iclass 26, count 0 2006.257.16:26:43.53#ibcon#wrote, iclass 26, count 0 2006.257.16:26:43.53#ibcon#about to read 3, iclass 26, count 0 2006.257.16:26:43.55#ibcon#read 3, iclass 26, count 0 2006.257.16:26:43.55#ibcon#about to read 4, iclass 26, count 0 2006.257.16:26:43.55#ibcon#read 4, iclass 26, count 0 2006.257.16:26:43.55#ibcon#about to read 5, iclass 26, count 0 2006.257.16:26:43.55#ibcon#read 5, iclass 26, count 0 2006.257.16:26:43.55#ibcon#about to read 6, iclass 26, count 0 2006.257.16:26:43.55#ibcon#read 6, iclass 26, count 0 2006.257.16:26:43.55#ibcon#end of sib2, iclass 26, count 0 2006.257.16:26:43.55#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:26:43.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:26:43.55#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:26:43.55#ibcon#*before write, iclass 26, count 0 2006.257.16:26:43.55#ibcon#enter sib2, iclass 26, count 0 2006.257.16:26:43.55#ibcon#flushed, iclass 26, count 0 2006.257.16:26:43.55#ibcon#about to write, iclass 26, count 0 2006.257.16:26:43.55#ibcon#wrote, iclass 26, count 0 2006.257.16:26:43.55#ibcon#about to read 3, iclass 26, count 0 2006.257.16:26:43.59#ibcon#read 3, iclass 26, count 0 2006.257.16:26:43.59#ibcon#about to read 4, iclass 26, count 0 2006.257.16:26:43.59#ibcon#read 4, iclass 26, count 0 2006.257.16:26:43.59#ibcon#about to read 5, iclass 26, count 0 2006.257.16:26:43.59#ibcon#read 5, iclass 26, count 0 2006.257.16:26:43.59#ibcon#about to read 6, iclass 26, count 0 2006.257.16:26:43.59#ibcon#read 6, iclass 26, count 0 2006.257.16:26:43.59#ibcon#end of sib2, iclass 26, count 0 2006.257.16:26:43.59#ibcon#*after write, iclass 26, count 0 2006.257.16:26:43.59#ibcon#*before return 0, iclass 26, count 0 2006.257.16:26:43.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:43.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:26:43.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:26:43.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:26:43.59$vck44/vb=8,4 2006.257.16:26:43.59#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.16:26:43.59#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.16:26:43.59#ibcon#ireg 11 cls_cnt 2 2006.257.16:26:43.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:43.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:43.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:43.65#ibcon#enter wrdev, iclass 28, count 2 2006.257.16:26:43.65#ibcon#first serial, iclass 28, count 2 2006.257.16:26:43.65#ibcon#enter sib2, iclass 28, count 2 2006.257.16:26:43.65#ibcon#flushed, iclass 28, count 2 2006.257.16:26:43.65#ibcon#about to write, iclass 28, count 2 2006.257.16:26:43.65#ibcon#wrote, iclass 28, count 2 2006.257.16:26:43.65#ibcon#about to read 3, iclass 28, count 2 2006.257.16:26:43.67#ibcon#read 3, iclass 28, count 2 2006.257.16:26:43.67#ibcon#about to read 4, iclass 28, count 2 2006.257.16:26:43.67#ibcon#read 4, iclass 28, count 2 2006.257.16:26:43.67#ibcon#about to read 5, iclass 28, count 2 2006.257.16:26:43.67#ibcon#read 5, iclass 28, count 2 2006.257.16:26:43.67#ibcon#about to read 6, iclass 28, count 2 2006.257.16:26:43.67#ibcon#read 6, iclass 28, count 2 2006.257.16:26:43.67#ibcon#end of sib2, iclass 28, count 2 2006.257.16:26:43.67#ibcon#*mode == 0, iclass 28, count 2 2006.257.16:26:43.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.16:26:43.67#ibcon#[27=AT08-04\r\n] 2006.257.16:26:43.67#ibcon#*before write, iclass 28, count 2 2006.257.16:26:43.67#ibcon#enter sib2, iclass 28, count 2 2006.257.16:26:43.67#ibcon#flushed, iclass 28, count 2 2006.257.16:26:43.67#ibcon#about to write, iclass 28, count 2 2006.257.16:26:43.67#ibcon#wrote, iclass 28, count 2 2006.257.16:26:43.67#ibcon#about to read 3, iclass 28, count 2 2006.257.16:26:43.70#ibcon#read 3, iclass 28, count 2 2006.257.16:26:43.70#ibcon#about to read 4, iclass 28, count 2 2006.257.16:26:43.70#ibcon#read 4, iclass 28, count 2 2006.257.16:26:43.70#ibcon#about to read 5, iclass 28, count 2 2006.257.16:26:43.70#ibcon#read 5, iclass 28, count 2 2006.257.16:26:43.70#ibcon#about to read 6, iclass 28, count 2 2006.257.16:26:43.70#ibcon#read 6, iclass 28, count 2 2006.257.16:26:43.70#ibcon#end of sib2, iclass 28, count 2 2006.257.16:26:43.70#ibcon#*after write, iclass 28, count 2 2006.257.16:26:43.70#ibcon#*before return 0, iclass 28, count 2 2006.257.16:26:43.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:43.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:26:43.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.16:26:43.70#ibcon#ireg 7 cls_cnt 0 2006.257.16:26:43.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:43.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:43.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:43.82#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:26:43.82#ibcon#first serial, iclass 28, count 0 2006.257.16:26:43.82#ibcon#enter sib2, iclass 28, count 0 2006.257.16:26:43.82#ibcon#flushed, iclass 28, count 0 2006.257.16:26:43.82#ibcon#about to write, iclass 28, count 0 2006.257.16:26:43.82#ibcon#wrote, iclass 28, count 0 2006.257.16:26:43.82#ibcon#about to read 3, iclass 28, count 0 2006.257.16:26:43.84#ibcon#read 3, iclass 28, count 0 2006.257.16:26:43.84#ibcon#about to read 4, iclass 28, count 0 2006.257.16:26:43.84#ibcon#read 4, iclass 28, count 0 2006.257.16:26:43.84#ibcon#about to read 5, iclass 28, count 0 2006.257.16:26:43.84#ibcon#read 5, iclass 28, count 0 2006.257.16:26:43.84#ibcon#about to read 6, iclass 28, count 0 2006.257.16:26:43.84#ibcon#read 6, iclass 28, count 0 2006.257.16:26:43.84#ibcon#end of sib2, iclass 28, count 0 2006.257.16:26:43.84#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:26:43.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:26:43.84#ibcon#[27=USB\r\n] 2006.257.16:26:43.84#ibcon#*before write, iclass 28, count 0 2006.257.16:26:43.84#ibcon#enter sib2, iclass 28, count 0 2006.257.16:26:43.84#ibcon#flushed, iclass 28, count 0 2006.257.16:26:43.84#ibcon#about to write, iclass 28, count 0 2006.257.16:26:43.84#ibcon#wrote, iclass 28, count 0 2006.257.16:26:43.84#ibcon#about to read 3, iclass 28, count 0 2006.257.16:26:43.87#ibcon#read 3, iclass 28, count 0 2006.257.16:26:43.87#ibcon#about to read 4, iclass 28, count 0 2006.257.16:26:43.87#ibcon#read 4, iclass 28, count 0 2006.257.16:26:43.87#ibcon#about to read 5, iclass 28, count 0 2006.257.16:26:43.87#ibcon#read 5, iclass 28, count 0 2006.257.16:26:43.87#ibcon#about to read 6, iclass 28, count 0 2006.257.16:26:43.87#ibcon#read 6, iclass 28, count 0 2006.257.16:26:43.87#ibcon#end of sib2, iclass 28, count 0 2006.257.16:26:43.87#ibcon#*after write, iclass 28, count 0 2006.257.16:26:43.87#ibcon#*before return 0, iclass 28, count 0 2006.257.16:26:43.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:43.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:26:43.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:26:43.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:26:43.87$vck44/vabw=wide 2006.257.16:26:43.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.16:26:43.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.16:26:43.87#ibcon#ireg 8 cls_cnt 0 2006.257.16:26:43.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:43.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:43.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:43.87#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:26:43.87#ibcon#first serial, iclass 30, count 0 2006.257.16:26:43.87#ibcon#enter sib2, iclass 30, count 0 2006.257.16:26:43.87#ibcon#flushed, iclass 30, count 0 2006.257.16:26:43.87#ibcon#about to write, iclass 30, count 0 2006.257.16:26:43.87#ibcon#wrote, iclass 30, count 0 2006.257.16:26:43.87#ibcon#about to read 3, iclass 30, count 0 2006.257.16:26:43.89#ibcon#read 3, iclass 30, count 0 2006.257.16:26:43.89#ibcon#about to read 4, iclass 30, count 0 2006.257.16:26:43.89#ibcon#read 4, iclass 30, count 0 2006.257.16:26:43.89#ibcon#about to read 5, iclass 30, count 0 2006.257.16:26:43.89#ibcon#read 5, iclass 30, count 0 2006.257.16:26:43.89#ibcon#about to read 6, iclass 30, count 0 2006.257.16:26:43.89#ibcon#read 6, iclass 30, count 0 2006.257.16:26:43.89#ibcon#end of sib2, iclass 30, count 0 2006.257.16:26:43.89#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:26:43.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:26:43.89#ibcon#[25=BW32\r\n] 2006.257.16:26:43.89#ibcon#*before write, iclass 30, count 0 2006.257.16:26:43.89#ibcon#enter sib2, iclass 30, count 0 2006.257.16:26:43.89#ibcon#flushed, iclass 30, count 0 2006.257.16:26:43.89#ibcon#about to write, iclass 30, count 0 2006.257.16:26:43.89#ibcon#wrote, iclass 30, count 0 2006.257.16:26:43.89#ibcon#about to read 3, iclass 30, count 0 2006.257.16:26:43.92#ibcon#read 3, iclass 30, count 0 2006.257.16:26:43.92#ibcon#about to read 4, iclass 30, count 0 2006.257.16:26:43.92#ibcon#read 4, iclass 30, count 0 2006.257.16:26:43.92#ibcon#about to read 5, iclass 30, count 0 2006.257.16:26:43.92#ibcon#read 5, iclass 30, count 0 2006.257.16:26:43.92#ibcon#about to read 6, iclass 30, count 0 2006.257.16:26:43.92#ibcon#read 6, iclass 30, count 0 2006.257.16:26:43.92#ibcon#end of sib2, iclass 30, count 0 2006.257.16:26:43.92#ibcon#*after write, iclass 30, count 0 2006.257.16:26:43.92#ibcon#*before return 0, iclass 30, count 0 2006.257.16:26:43.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:43.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:26:43.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:26:43.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:26:43.92$vck44/vbbw=wide 2006.257.16:26:43.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.16:26:43.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.16:26:43.92#ibcon#ireg 8 cls_cnt 0 2006.257.16:26:43.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:26:43.97#abcon#<5=/14 1.2 2.9 17.14 971014.1\r\n> 2006.257.16:26:43.99#abcon#{5=INTERFACE CLEAR} 2006.257.16:26:43.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:26:43.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:26:43.99#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:26:43.99#ibcon#first serial, iclass 32, count 0 2006.257.16:26:43.99#ibcon#enter sib2, iclass 32, count 0 2006.257.16:26:43.99#ibcon#flushed, iclass 32, count 0 2006.257.16:26:43.99#ibcon#about to write, iclass 32, count 0 2006.257.16:26:43.99#ibcon#wrote, iclass 32, count 0 2006.257.16:26:43.99#ibcon#about to read 3, iclass 32, count 0 2006.257.16:26:44.01#ibcon#read 3, iclass 32, count 0 2006.257.16:26:44.01#ibcon#about to read 4, iclass 32, count 0 2006.257.16:26:44.01#ibcon#read 4, iclass 32, count 0 2006.257.16:26:44.01#ibcon#about to read 5, iclass 32, count 0 2006.257.16:26:44.01#ibcon#read 5, iclass 32, count 0 2006.257.16:26:44.01#ibcon#about to read 6, iclass 32, count 0 2006.257.16:26:44.01#ibcon#read 6, iclass 32, count 0 2006.257.16:26:44.01#ibcon#end of sib2, iclass 32, count 0 2006.257.16:26:44.01#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:26:44.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:26:44.01#ibcon#[27=BW32\r\n] 2006.257.16:26:44.01#ibcon#*before write, iclass 32, count 0 2006.257.16:26:44.01#ibcon#enter sib2, iclass 32, count 0 2006.257.16:26:44.01#ibcon#flushed, iclass 32, count 0 2006.257.16:26:44.01#ibcon#about to write, iclass 32, count 0 2006.257.16:26:44.01#ibcon#wrote, iclass 32, count 0 2006.257.16:26:44.01#ibcon#about to read 3, iclass 32, count 0 2006.257.16:26:44.04#ibcon#read 3, iclass 32, count 0 2006.257.16:26:44.04#ibcon#about to read 4, iclass 32, count 0 2006.257.16:26:44.04#ibcon#read 4, iclass 32, count 0 2006.257.16:26:44.04#ibcon#about to read 5, iclass 32, count 0 2006.257.16:26:44.04#ibcon#read 5, iclass 32, count 0 2006.257.16:26:44.04#ibcon#about to read 6, iclass 32, count 0 2006.257.16:26:44.04#ibcon#read 6, iclass 32, count 0 2006.257.16:26:44.04#ibcon#end of sib2, iclass 32, count 0 2006.257.16:26:44.04#ibcon#*after write, iclass 32, count 0 2006.257.16:26:44.04#ibcon#*before return 0, iclass 32, count 0 2006.257.16:26:44.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:26:44.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:26:44.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:26:44.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:26:44.04$setupk4/ifdk4 2006.257.16:26:44.04$ifdk4/lo= 2006.257.16:26:44.04$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:26:44.04$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:26:44.04$ifdk4/patch= 2006.257.16:26:44.04$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:26:44.04$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:26:44.04$setupk4/!*+20s 2006.257.16:26:44.05#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:26:54.14#abcon#<5=/14 1.2 2.9 17.14 981014.1\r\n> 2006.257.16:26:54.16#abcon#{5=INTERFACE CLEAR} 2006.257.16:26:54.22#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:26:58.55$setupk4/"tpicd 2006.257.16:26:58.55$setupk4/echo=off 2006.257.16:26:58.55$setupk4/xlog=off 2006.257.16:26:58.55:!2006.257.16:29:21 2006.257.16:27:19.14#trakl#Source acquired 2006.257.16:27:19.14#flagr#flagr/antenna,acquired 2006.257.16:29:21.00:preob 2006.257.16:29:21.13/onsource/TRACKING 2006.257.16:29:21.13:!2006.257.16:29:31 2006.257.16:29:31.00:"tape 2006.257.16:29:31.00:"st=record 2006.257.16:29:31.00:data_valid=on 2006.257.16:29:31.00:midob 2006.257.16:29:31.13/onsource/TRACKING 2006.257.16:29:31.13/wx/17.12,1014.1,98 2006.257.16:29:31.23/cable/+6.4842E-03 2006.257.16:29:32.32/va/01,08,usb,yes,30,32 2006.257.16:29:32.32/va/02,07,usb,yes,32,33 2006.257.16:29:32.32/va/03,08,usb,yes,29,31 2006.257.16:29:32.32/va/04,07,usb,yes,33,35 2006.257.16:29:32.32/va/05,04,usb,yes,30,30 2006.257.16:29:32.32/va/06,04,usb,yes,33,33 2006.257.16:29:32.32/va/07,04,usb,yes,34,35 2006.257.16:29:32.32/va/08,04,usb,yes,29,35 2006.257.16:29:32.55/valo/01,524.99,yes,locked 2006.257.16:29:32.55/valo/02,534.99,yes,locked 2006.257.16:29:32.55/valo/03,564.99,yes,locked 2006.257.16:29:32.55/valo/04,624.99,yes,locked 2006.257.16:29:32.55/valo/05,734.99,yes,locked 2006.257.16:29:32.55/valo/06,814.99,yes,locked 2006.257.16:29:32.55/valo/07,864.99,yes,locked 2006.257.16:29:32.55/valo/08,884.99,yes,locked 2006.257.16:29:33.64/vb/01,04,usb,yes,30,28 2006.257.16:29:33.64/vb/02,05,usb,yes,28,28 2006.257.16:29:33.64/vb/03,04,usb,yes,29,32 2006.257.16:29:33.64/vb/04,05,usb,yes,30,28 2006.257.16:29:33.64/vb/05,04,usb,yes,26,28 2006.257.16:29:33.64/vb/06,04,usb,yes,31,27 2006.257.16:29:33.64/vb/07,04,usb,yes,30,30 2006.257.16:29:33.64/vb/08,04,usb,yes,28,31 2006.257.16:29:33.88/vblo/01,629.99,yes,locked 2006.257.16:29:33.88/vblo/02,634.99,yes,locked 2006.257.16:29:33.88/vblo/03,649.99,yes,locked 2006.257.16:29:33.88/vblo/04,679.99,yes,locked 2006.257.16:29:33.88/vblo/05,709.99,yes,locked 2006.257.16:29:33.88/vblo/06,719.99,yes,locked 2006.257.16:29:33.88/vblo/07,734.99,yes,locked 2006.257.16:29:33.88/vblo/08,744.99,yes,locked 2006.257.16:29:34.03/vabw/8 2006.257.16:29:34.18/vbbw/8 2006.257.16:29:34.28/xfe/off,on,15.0 2006.257.16:29:34.65/ifatt/23,28,28,28 2006.257.16:29:35.07/fmout-gps/S +4.59E-07 2006.257.16:29:35.11:!2006.257.16:31:21 2006.257.16:31:21.01:data_valid=off 2006.257.16:31:21.01:"et 2006.257.16:31:21.01:!+3s 2006.257.16:31:24.02:"tape 2006.257.16:31:24.02:postob 2006.257.16:31:24.15/cable/+6.4829E-03 2006.257.16:31:24.15/wx/17.12,1014.1,98 2006.257.16:31:24.21/fmout-gps/S +4.59E-07 2006.257.16:31:24.21:scan_name=257-1633,jd0609,230 2006.257.16:31:24.21:source=1044+719,104827.62,714335.9,2000.0,cw 2006.257.16:31:25.14#flagr#flagr/antenna,new-source 2006.257.16:31:25.14:checkk5 2006.257.16:31:25.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.16:31:25.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.16:31:26.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.16:31:26.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.16:31:26.84/chk_obsdata//k5ts1/T2571629??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.16:31:27.18/chk_obsdata//k5ts2/T2571629??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.16:31:27.51/chk_obsdata//k5ts3/T2571629??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.16:31:27.85/chk_obsdata//k5ts4/T2571629??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.16:31:28.50/k5log//k5ts1_log_newline 2006.257.16:31:29.17/k5log//k5ts2_log_newline 2006.257.16:31:29.82/k5log//k5ts3_log_newline 2006.257.16:31:30.47/k5log//k5ts4_log_newline 2006.257.16:31:30.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.16:31:30.50:setupk4=1 2006.257.16:31:30.50$setupk4/echo=on 2006.257.16:31:30.50$setupk4/pcalon 2006.257.16:31:30.50$pcalon/"no phase cal control is implemented here 2006.257.16:31:30.50$setupk4/"tpicd=stop 2006.257.16:31:30.50$setupk4/"rec=synch_on 2006.257.16:31:30.50$setupk4/"rec_mode=128 2006.257.16:31:30.50$setupk4/!* 2006.257.16:31:30.50$setupk4/recpk4 2006.257.16:31:30.50$recpk4/recpatch= 2006.257.16:31:30.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.16:31:30.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.16:31:30.50$setupk4/vck44 2006.257.16:31:30.50$vck44/valo=1,524.99 2006.257.16:31:30.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.16:31:30.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.16:31:30.50#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:30.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:31:30.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:31:30.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:31:30.50#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:31:30.50#ibcon#first serial, iclass 38, count 0 2006.257.16:31:30.50#ibcon#enter sib2, iclass 38, count 0 2006.257.16:31:30.50#ibcon#flushed, iclass 38, count 0 2006.257.16:31:30.50#ibcon#about to write, iclass 38, count 0 2006.257.16:31:30.50#ibcon#wrote, iclass 38, count 0 2006.257.16:31:30.50#ibcon#about to read 3, iclass 38, count 0 2006.257.16:31:30.52#ibcon#read 3, iclass 38, count 0 2006.257.16:31:30.52#ibcon#about to read 4, iclass 38, count 0 2006.257.16:31:30.52#ibcon#read 4, iclass 38, count 0 2006.257.16:31:30.52#ibcon#about to read 5, iclass 38, count 0 2006.257.16:31:30.52#ibcon#read 5, iclass 38, count 0 2006.257.16:31:30.52#ibcon#about to read 6, iclass 38, count 0 2006.257.16:31:30.52#ibcon#read 6, iclass 38, count 0 2006.257.16:31:30.52#ibcon#end of sib2, iclass 38, count 0 2006.257.16:31:30.52#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:31:30.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:31:30.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.16:31:30.52#ibcon#*before write, iclass 38, count 0 2006.257.16:31:30.52#ibcon#enter sib2, iclass 38, count 0 2006.257.16:31:30.52#ibcon#flushed, iclass 38, count 0 2006.257.16:31:30.52#ibcon#about to write, iclass 38, count 0 2006.257.16:31:30.52#ibcon#wrote, iclass 38, count 0 2006.257.16:31:30.52#ibcon#about to read 3, iclass 38, count 0 2006.257.16:31:30.57#ibcon#read 3, iclass 38, count 0 2006.257.16:31:30.57#ibcon#about to read 4, iclass 38, count 0 2006.257.16:31:30.57#ibcon#read 4, iclass 38, count 0 2006.257.16:31:30.57#ibcon#about to read 5, iclass 38, count 0 2006.257.16:31:30.57#ibcon#read 5, iclass 38, count 0 2006.257.16:31:30.57#ibcon#about to read 6, iclass 38, count 0 2006.257.16:31:30.57#ibcon#read 6, iclass 38, count 0 2006.257.16:31:30.57#ibcon#end of sib2, iclass 38, count 0 2006.257.16:31:30.57#ibcon#*after write, iclass 38, count 0 2006.257.16:31:30.57#ibcon#*before return 0, iclass 38, count 0 2006.257.16:31:30.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:31:30.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:31:30.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:31:30.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:31:30.57$vck44/va=1,8 2006.257.16:31:30.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.16:31:30.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.16:31:30.57#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:30.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:31:30.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:31:30.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:31:30.57#ibcon#enter wrdev, iclass 40, count 2 2006.257.16:31:30.57#ibcon#first serial, iclass 40, count 2 2006.257.16:31:30.57#ibcon#enter sib2, iclass 40, count 2 2006.257.16:31:30.57#ibcon#flushed, iclass 40, count 2 2006.257.16:31:30.57#ibcon#about to write, iclass 40, count 2 2006.257.16:31:30.57#ibcon#wrote, iclass 40, count 2 2006.257.16:31:30.57#ibcon#about to read 3, iclass 40, count 2 2006.257.16:31:30.59#ibcon#read 3, iclass 40, count 2 2006.257.16:31:30.59#ibcon#about to read 4, iclass 40, count 2 2006.257.16:31:30.59#ibcon#read 4, iclass 40, count 2 2006.257.16:31:30.59#ibcon#about to read 5, iclass 40, count 2 2006.257.16:31:30.59#ibcon#read 5, iclass 40, count 2 2006.257.16:31:30.59#ibcon#about to read 6, iclass 40, count 2 2006.257.16:31:30.59#ibcon#read 6, iclass 40, count 2 2006.257.16:31:30.59#ibcon#end of sib2, iclass 40, count 2 2006.257.16:31:30.59#ibcon#*mode == 0, iclass 40, count 2 2006.257.16:31:30.59#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.16:31:30.59#ibcon#[25=AT01-08\r\n] 2006.257.16:31:30.59#ibcon#*before write, iclass 40, count 2 2006.257.16:31:30.59#ibcon#enter sib2, iclass 40, count 2 2006.257.16:31:30.59#ibcon#flushed, iclass 40, count 2 2006.257.16:31:30.59#ibcon#about to write, iclass 40, count 2 2006.257.16:31:30.59#ibcon#wrote, iclass 40, count 2 2006.257.16:31:30.59#ibcon#about to read 3, iclass 40, count 2 2006.257.16:31:30.62#ibcon#read 3, iclass 40, count 2 2006.257.16:31:30.62#ibcon#about to read 4, iclass 40, count 2 2006.257.16:31:30.62#ibcon#read 4, iclass 40, count 2 2006.257.16:31:30.62#ibcon#about to read 5, iclass 40, count 2 2006.257.16:31:30.62#ibcon#read 5, iclass 40, count 2 2006.257.16:31:30.62#ibcon#about to read 6, iclass 40, count 2 2006.257.16:31:30.62#ibcon#read 6, iclass 40, count 2 2006.257.16:31:30.62#ibcon#end of sib2, iclass 40, count 2 2006.257.16:31:30.62#ibcon#*after write, iclass 40, count 2 2006.257.16:31:30.62#ibcon#*before return 0, iclass 40, count 2 2006.257.16:31:30.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:31:30.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:31:30.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.16:31:30.62#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:30.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:31:30.74#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:31:30.74#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:31:30.74#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:31:30.74#ibcon#first serial, iclass 40, count 0 2006.257.16:31:30.74#ibcon#enter sib2, iclass 40, count 0 2006.257.16:31:30.74#ibcon#flushed, iclass 40, count 0 2006.257.16:31:30.74#ibcon#about to write, iclass 40, count 0 2006.257.16:31:30.74#ibcon#wrote, iclass 40, count 0 2006.257.16:31:30.74#ibcon#about to read 3, iclass 40, count 0 2006.257.16:31:30.76#ibcon#read 3, iclass 40, count 0 2006.257.16:31:30.76#ibcon#about to read 4, iclass 40, count 0 2006.257.16:31:30.76#ibcon#read 4, iclass 40, count 0 2006.257.16:31:30.76#ibcon#about to read 5, iclass 40, count 0 2006.257.16:31:30.76#ibcon#read 5, iclass 40, count 0 2006.257.16:31:30.76#ibcon#about to read 6, iclass 40, count 0 2006.257.16:31:30.76#ibcon#read 6, iclass 40, count 0 2006.257.16:31:30.76#ibcon#end of sib2, iclass 40, count 0 2006.257.16:31:30.76#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:31:30.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:31:30.76#ibcon#[25=USB\r\n] 2006.257.16:31:30.76#ibcon#*before write, iclass 40, count 0 2006.257.16:31:30.76#ibcon#enter sib2, iclass 40, count 0 2006.257.16:31:30.76#ibcon#flushed, iclass 40, count 0 2006.257.16:31:30.76#ibcon#about to write, iclass 40, count 0 2006.257.16:31:30.76#ibcon#wrote, iclass 40, count 0 2006.257.16:31:30.76#ibcon#about to read 3, iclass 40, count 0 2006.257.16:31:30.79#ibcon#read 3, iclass 40, count 0 2006.257.16:31:30.79#ibcon#about to read 4, iclass 40, count 0 2006.257.16:31:30.79#ibcon#read 4, iclass 40, count 0 2006.257.16:31:30.79#ibcon#about to read 5, iclass 40, count 0 2006.257.16:31:30.79#ibcon#read 5, iclass 40, count 0 2006.257.16:31:30.79#ibcon#about to read 6, iclass 40, count 0 2006.257.16:31:30.79#ibcon#read 6, iclass 40, count 0 2006.257.16:31:30.79#ibcon#end of sib2, iclass 40, count 0 2006.257.16:31:30.79#ibcon#*after write, iclass 40, count 0 2006.257.16:31:30.79#ibcon#*before return 0, iclass 40, count 0 2006.257.16:31:30.79#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:31:30.79#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:31:30.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:31:30.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:31:30.79$vck44/valo=2,534.99 2006.257.16:31:30.79#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.16:31:30.79#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.16:31:30.79#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:30.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:31:30.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:31:30.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:31:30.79#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:31:30.79#ibcon#first serial, iclass 4, count 0 2006.257.16:31:30.79#ibcon#enter sib2, iclass 4, count 0 2006.257.16:31:30.79#ibcon#flushed, iclass 4, count 0 2006.257.16:31:30.79#ibcon#about to write, iclass 4, count 0 2006.257.16:31:30.79#ibcon#wrote, iclass 4, count 0 2006.257.16:31:30.79#ibcon#about to read 3, iclass 4, count 0 2006.257.16:31:30.81#ibcon#read 3, iclass 4, count 0 2006.257.16:31:30.81#ibcon#about to read 4, iclass 4, count 0 2006.257.16:31:30.81#ibcon#read 4, iclass 4, count 0 2006.257.16:31:30.81#ibcon#about to read 5, iclass 4, count 0 2006.257.16:31:30.81#ibcon#read 5, iclass 4, count 0 2006.257.16:31:30.81#ibcon#about to read 6, iclass 4, count 0 2006.257.16:31:30.81#ibcon#read 6, iclass 4, count 0 2006.257.16:31:30.81#ibcon#end of sib2, iclass 4, count 0 2006.257.16:31:30.81#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:31:30.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:31:30.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.16:31:30.81#ibcon#*before write, iclass 4, count 0 2006.257.16:31:30.81#ibcon#enter sib2, iclass 4, count 0 2006.257.16:31:30.81#ibcon#flushed, iclass 4, count 0 2006.257.16:31:30.81#ibcon#about to write, iclass 4, count 0 2006.257.16:31:30.81#ibcon#wrote, iclass 4, count 0 2006.257.16:31:30.81#ibcon#about to read 3, iclass 4, count 0 2006.257.16:31:30.85#ibcon#read 3, iclass 4, count 0 2006.257.16:31:30.85#ibcon#about to read 4, iclass 4, count 0 2006.257.16:31:30.85#ibcon#read 4, iclass 4, count 0 2006.257.16:31:30.85#ibcon#about to read 5, iclass 4, count 0 2006.257.16:31:30.85#ibcon#read 5, iclass 4, count 0 2006.257.16:31:30.85#ibcon#about to read 6, iclass 4, count 0 2006.257.16:31:30.85#ibcon#read 6, iclass 4, count 0 2006.257.16:31:30.85#ibcon#end of sib2, iclass 4, count 0 2006.257.16:31:30.85#ibcon#*after write, iclass 4, count 0 2006.257.16:31:30.85#ibcon#*before return 0, iclass 4, count 0 2006.257.16:31:30.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:31:30.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:31:30.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:31:30.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:31:30.85$vck44/va=2,7 2006.257.16:31:30.85#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.16:31:30.85#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.16:31:30.85#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:30.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:31:30.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:31:30.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:31:30.91#ibcon#enter wrdev, iclass 6, count 2 2006.257.16:31:30.91#ibcon#first serial, iclass 6, count 2 2006.257.16:31:30.91#ibcon#enter sib2, iclass 6, count 2 2006.257.16:31:30.91#ibcon#flushed, iclass 6, count 2 2006.257.16:31:30.91#ibcon#about to write, iclass 6, count 2 2006.257.16:31:30.91#ibcon#wrote, iclass 6, count 2 2006.257.16:31:30.91#ibcon#about to read 3, iclass 6, count 2 2006.257.16:31:30.93#ibcon#read 3, iclass 6, count 2 2006.257.16:31:30.93#ibcon#about to read 4, iclass 6, count 2 2006.257.16:31:30.93#ibcon#read 4, iclass 6, count 2 2006.257.16:31:30.93#ibcon#about to read 5, iclass 6, count 2 2006.257.16:31:30.93#ibcon#read 5, iclass 6, count 2 2006.257.16:31:30.93#ibcon#about to read 6, iclass 6, count 2 2006.257.16:31:30.93#ibcon#read 6, iclass 6, count 2 2006.257.16:31:30.93#ibcon#end of sib2, iclass 6, count 2 2006.257.16:31:30.93#ibcon#*mode == 0, iclass 6, count 2 2006.257.16:31:30.93#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.16:31:30.93#ibcon#[25=AT02-07\r\n] 2006.257.16:31:30.93#ibcon#*before write, iclass 6, count 2 2006.257.16:31:30.93#ibcon#enter sib2, iclass 6, count 2 2006.257.16:31:30.93#ibcon#flushed, iclass 6, count 2 2006.257.16:31:30.93#ibcon#about to write, iclass 6, count 2 2006.257.16:31:30.93#ibcon#wrote, iclass 6, count 2 2006.257.16:31:30.93#ibcon#about to read 3, iclass 6, count 2 2006.257.16:31:30.96#ibcon#read 3, iclass 6, count 2 2006.257.16:31:30.96#ibcon#about to read 4, iclass 6, count 2 2006.257.16:31:30.96#ibcon#read 4, iclass 6, count 2 2006.257.16:31:30.96#ibcon#about to read 5, iclass 6, count 2 2006.257.16:31:30.96#ibcon#read 5, iclass 6, count 2 2006.257.16:31:30.96#ibcon#about to read 6, iclass 6, count 2 2006.257.16:31:30.96#ibcon#read 6, iclass 6, count 2 2006.257.16:31:30.96#ibcon#end of sib2, iclass 6, count 2 2006.257.16:31:30.96#ibcon#*after write, iclass 6, count 2 2006.257.16:31:30.96#ibcon#*before return 0, iclass 6, count 2 2006.257.16:31:30.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:31:30.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:31:30.96#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.16:31:30.96#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:30.96#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:31:31.08#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:31:31.08#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:31:31.08#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:31:31.08#ibcon#first serial, iclass 6, count 0 2006.257.16:31:31.08#ibcon#enter sib2, iclass 6, count 0 2006.257.16:31:31.08#ibcon#flushed, iclass 6, count 0 2006.257.16:31:31.08#ibcon#about to write, iclass 6, count 0 2006.257.16:31:31.08#ibcon#wrote, iclass 6, count 0 2006.257.16:31:31.08#ibcon#about to read 3, iclass 6, count 0 2006.257.16:31:31.10#ibcon#read 3, iclass 6, count 0 2006.257.16:31:31.10#ibcon#about to read 4, iclass 6, count 0 2006.257.16:31:31.10#ibcon#read 4, iclass 6, count 0 2006.257.16:31:31.10#ibcon#about to read 5, iclass 6, count 0 2006.257.16:31:31.10#ibcon#read 5, iclass 6, count 0 2006.257.16:31:31.10#ibcon#about to read 6, iclass 6, count 0 2006.257.16:31:31.10#ibcon#read 6, iclass 6, count 0 2006.257.16:31:31.10#ibcon#end of sib2, iclass 6, count 0 2006.257.16:31:31.10#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:31:31.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:31:31.10#ibcon#[25=USB\r\n] 2006.257.16:31:31.10#ibcon#*before write, iclass 6, count 0 2006.257.16:31:31.10#ibcon#enter sib2, iclass 6, count 0 2006.257.16:31:31.10#ibcon#flushed, iclass 6, count 0 2006.257.16:31:31.10#ibcon#about to write, iclass 6, count 0 2006.257.16:31:31.10#ibcon#wrote, iclass 6, count 0 2006.257.16:31:31.10#ibcon#about to read 3, iclass 6, count 0 2006.257.16:31:31.13#ibcon#read 3, iclass 6, count 0 2006.257.16:31:31.13#ibcon#about to read 4, iclass 6, count 0 2006.257.16:31:31.13#ibcon#read 4, iclass 6, count 0 2006.257.16:31:31.13#ibcon#about to read 5, iclass 6, count 0 2006.257.16:31:31.13#ibcon#read 5, iclass 6, count 0 2006.257.16:31:31.13#ibcon#about to read 6, iclass 6, count 0 2006.257.16:31:31.13#ibcon#read 6, iclass 6, count 0 2006.257.16:31:31.13#ibcon#end of sib2, iclass 6, count 0 2006.257.16:31:31.13#ibcon#*after write, iclass 6, count 0 2006.257.16:31:31.13#ibcon#*before return 0, iclass 6, count 0 2006.257.16:31:31.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:31:31.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:31:31.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:31:31.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:31:31.13$vck44/valo=3,564.99 2006.257.16:31:31.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.16:31:31.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.16:31:31.13#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:31.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:31:31.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:31:31.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:31:31.13#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:31:31.13#ibcon#first serial, iclass 10, count 0 2006.257.16:31:31.13#ibcon#enter sib2, iclass 10, count 0 2006.257.16:31:31.13#ibcon#flushed, iclass 10, count 0 2006.257.16:31:31.13#ibcon#about to write, iclass 10, count 0 2006.257.16:31:31.13#ibcon#wrote, iclass 10, count 0 2006.257.16:31:31.13#ibcon#about to read 3, iclass 10, count 0 2006.257.16:31:31.15#ibcon#read 3, iclass 10, count 0 2006.257.16:31:31.15#ibcon#about to read 4, iclass 10, count 0 2006.257.16:31:31.15#ibcon#read 4, iclass 10, count 0 2006.257.16:31:31.15#ibcon#about to read 5, iclass 10, count 0 2006.257.16:31:31.15#ibcon#read 5, iclass 10, count 0 2006.257.16:31:31.15#ibcon#about to read 6, iclass 10, count 0 2006.257.16:31:31.15#ibcon#read 6, iclass 10, count 0 2006.257.16:31:31.15#ibcon#end of sib2, iclass 10, count 0 2006.257.16:31:31.15#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:31:31.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:31:31.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.16:31:31.15#ibcon#*before write, iclass 10, count 0 2006.257.16:31:31.15#ibcon#enter sib2, iclass 10, count 0 2006.257.16:31:31.15#ibcon#flushed, iclass 10, count 0 2006.257.16:31:31.15#ibcon#about to write, iclass 10, count 0 2006.257.16:31:31.15#ibcon#wrote, iclass 10, count 0 2006.257.16:31:31.15#ibcon#about to read 3, iclass 10, count 0 2006.257.16:31:31.19#ibcon#read 3, iclass 10, count 0 2006.257.16:31:31.19#ibcon#about to read 4, iclass 10, count 0 2006.257.16:31:31.19#ibcon#read 4, iclass 10, count 0 2006.257.16:31:31.19#ibcon#about to read 5, iclass 10, count 0 2006.257.16:31:31.19#ibcon#read 5, iclass 10, count 0 2006.257.16:31:31.19#ibcon#about to read 6, iclass 10, count 0 2006.257.16:31:31.19#ibcon#read 6, iclass 10, count 0 2006.257.16:31:31.19#ibcon#end of sib2, iclass 10, count 0 2006.257.16:31:31.19#ibcon#*after write, iclass 10, count 0 2006.257.16:31:31.19#ibcon#*before return 0, iclass 10, count 0 2006.257.16:31:31.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:31:31.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:31:31.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:31:31.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:31:31.19$vck44/va=3,8 2006.257.16:31:31.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.16:31:31.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.16:31:31.19#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:31.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:31:31.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:31:31.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:31:31.25#ibcon#enter wrdev, iclass 12, count 2 2006.257.16:31:31.25#ibcon#first serial, iclass 12, count 2 2006.257.16:31:31.25#ibcon#enter sib2, iclass 12, count 2 2006.257.16:31:31.25#ibcon#flushed, iclass 12, count 2 2006.257.16:31:31.25#ibcon#about to write, iclass 12, count 2 2006.257.16:31:31.25#ibcon#wrote, iclass 12, count 2 2006.257.16:31:31.25#ibcon#about to read 3, iclass 12, count 2 2006.257.16:31:31.27#ibcon#read 3, iclass 12, count 2 2006.257.16:31:31.27#ibcon#about to read 4, iclass 12, count 2 2006.257.16:31:31.27#ibcon#read 4, iclass 12, count 2 2006.257.16:31:31.27#ibcon#about to read 5, iclass 12, count 2 2006.257.16:31:31.27#ibcon#read 5, iclass 12, count 2 2006.257.16:31:31.27#ibcon#about to read 6, iclass 12, count 2 2006.257.16:31:31.27#ibcon#read 6, iclass 12, count 2 2006.257.16:31:31.27#ibcon#end of sib2, iclass 12, count 2 2006.257.16:31:31.27#ibcon#*mode == 0, iclass 12, count 2 2006.257.16:31:31.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.16:31:31.27#ibcon#[25=AT03-08\r\n] 2006.257.16:31:31.27#ibcon#*before write, iclass 12, count 2 2006.257.16:31:31.27#ibcon#enter sib2, iclass 12, count 2 2006.257.16:31:31.27#ibcon#flushed, iclass 12, count 2 2006.257.16:31:31.27#ibcon#about to write, iclass 12, count 2 2006.257.16:31:31.27#ibcon#wrote, iclass 12, count 2 2006.257.16:31:31.27#ibcon#about to read 3, iclass 12, count 2 2006.257.16:31:31.30#ibcon#read 3, iclass 12, count 2 2006.257.16:31:31.30#ibcon#about to read 4, iclass 12, count 2 2006.257.16:31:31.30#ibcon#read 4, iclass 12, count 2 2006.257.16:31:31.30#ibcon#about to read 5, iclass 12, count 2 2006.257.16:31:31.30#ibcon#read 5, iclass 12, count 2 2006.257.16:31:31.30#ibcon#about to read 6, iclass 12, count 2 2006.257.16:31:31.30#ibcon#read 6, iclass 12, count 2 2006.257.16:31:31.30#ibcon#end of sib2, iclass 12, count 2 2006.257.16:31:31.30#ibcon#*after write, iclass 12, count 2 2006.257.16:31:31.30#ibcon#*before return 0, iclass 12, count 2 2006.257.16:31:31.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:31:31.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:31:31.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.16:31:31.30#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:31.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:31:31.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:31:31.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:31:31.42#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:31:31.42#ibcon#first serial, iclass 12, count 0 2006.257.16:31:31.42#ibcon#enter sib2, iclass 12, count 0 2006.257.16:31:31.42#ibcon#flushed, iclass 12, count 0 2006.257.16:31:31.42#ibcon#about to write, iclass 12, count 0 2006.257.16:31:31.42#ibcon#wrote, iclass 12, count 0 2006.257.16:31:31.42#ibcon#about to read 3, iclass 12, count 0 2006.257.16:31:31.44#ibcon#read 3, iclass 12, count 0 2006.257.16:31:31.44#ibcon#about to read 4, iclass 12, count 0 2006.257.16:31:31.44#ibcon#read 4, iclass 12, count 0 2006.257.16:31:31.44#ibcon#about to read 5, iclass 12, count 0 2006.257.16:31:31.44#ibcon#read 5, iclass 12, count 0 2006.257.16:31:31.44#ibcon#about to read 6, iclass 12, count 0 2006.257.16:31:31.44#ibcon#read 6, iclass 12, count 0 2006.257.16:31:31.44#ibcon#end of sib2, iclass 12, count 0 2006.257.16:31:31.44#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:31:31.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:31:31.44#ibcon#[25=USB\r\n] 2006.257.16:31:31.44#ibcon#*before write, iclass 12, count 0 2006.257.16:31:31.44#ibcon#enter sib2, iclass 12, count 0 2006.257.16:31:31.44#ibcon#flushed, iclass 12, count 0 2006.257.16:31:31.44#ibcon#about to write, iclass 12, count 0 2006.257.16:31:31.44#ibcon#wrote, iclass 12, count 0 2006.257.16:31:31.44#ibcon#about to read 3, iclass 12, count 0 2006.257.16:31:31.47#ibcon#read 3, iclass 12, count 0 2006.257.16:31:31.47#ibcon#about to read 4, iclass 12, count 0 2006.257.16:31:31.47#ibcon#read 4, iclass 12, count 0 2006.257.16:31:31.47#ibcon#about to read 5, iclass 12, count 0 2006.257.16:31:31.47#ibcon#read 5, iclass 12, count 0 2006.257.16:31:31.47#ibcon#about to read 6, iclass 12, count 0 2006.257.16:31:31.47#ibcon#read 6, iclass 12, count 0 2006.257.16:31:31.47#ibcon#end of sib2, iclass 12, count 0 2006.257.16:31:31.47#ibcon#*after write, iclass 12, count 0 2006.257.16:31:31.47#ibcon#*before return 0, iclass 12, count 0 2006.257.16:31:31.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:31:31.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:31:31.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:31:31.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:31:31.47$vck44/valo=4,624.99 2006.257.16:31:31.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.16:31:31.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.16:31:31.47#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:31.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:31:31.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:31:31.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:31:31.47#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:31:31.47#ibcon#first serial, iclass 14, count 0 2006.257.16:31:31.47#ibcon#enter sib2, iclass 14, count 0 2006.257.16:31:31.47#ibcon#flushed, iclass 14, count 0 2006.257.16:31:31.47#ibcon#about to write, iclass 14, count 0 2006.257.16:31:31.47#ibcon#wrote, iclass 14, count 0 2006.257.16:31:31.47#ibcon#about to read 3, iclass 14, count 0 2006.257.16:31:31.49#ibcon#read 3, iclass 14, count 0 2006.257.16:31:31.49#ibcon#about to read 4, iclass 14, count 0 2006.257.16:31:31.49#ibcon#read 4, iclass 14, count 0 2006.257.16:31:31.49#ibcon#about to read 5, iclass 14, count 0 2006.257.16:31:31.49#ibcon#read 5, iclass 14, count 0 2006.257.16:31:31.49#ibcon#about to read 6, iclass 14, count 0 2006.257.16:31:31.49#ibcon#read 6, iclass 14, count 0 2006.257.16:31:31.49#ibcon#end of sib2, iclass 14, count 0 2006.257.16:31:31.49#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:31:31.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:31:31.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.16:31:31.49#ibcon#*before write, iclass 14, count 0 2006.257.16:31:31.49#ibcon#enter sib2, iclass 14, count 0 2006.257.16:31:31.49#ibcon#flushed, iclass 14, count 0 2006.257.16:31:31.49#ibcon#about to write, iclass 14, count 0 2006.257.16:31:31.49#ibcon#wrote, iclass 14, count 0 2006.257.16:31:31.49#ibcon#about to read 3, iclass 14, count 0 2006.257.16:31:31.53#ibcon#read 3, iclass 14, count 0 2006.257.16:31:31.53#ibcon#about to read 4, iclass 14, count 0 2006.257.16:31:31.53#ibcon#read 4, iclass 14, count 0 2006.257.16:31:31.53#ibcon#about to read 5, iclass 14, count 0 2006.257.16:31:31.53#ibcon#read 5, iclass 14, count 0 2006.257.16:31:31.53#ibcon#about to read 6, iclass 14, count 0 2006.257.16:31:31.53#ibcon#read 6, iclass 14, count 0 2006.257.16:31:31.53#ibcon#end of sib2, iclass 14, count 0 2006.257.16:31:31.53#ibcon#*after write, iclass 14, count 0 2006.257.16:31:31.53#ibcon#*before return 0, iclass 14, count 0 2006.257.16:31:31.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:31:31.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:31:31.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:31:31.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:31:31.53$vck44/va=4,7 2006.257.16:31:31.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.16:31:31.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.16:31:31.53#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:31.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:31:31.58#abcon#{5=INTERFACE CLEAR} 2006.257.16:31:31.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:31:31.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:31:31.59#ibcon#enter wrdev, iclass 16, count 2 2006.257.16:31:31.59#ibcon#first serial, iclass 16, count 2 2006.257.16:31:31.59#ibcon#enter sib2, iclass 16, count 2 2006.257.16:31:31.59#ibcon#flushed, iclass 16, count 2 2006.257.16:31:31.59#ibcon#about to write, iclass 16, count 2 2006.257.16:31:31.59#ibcon#wrote, iclass 16, count 2 2006.257.16:31:31.59#ibcon#about to read 3, iclass 16, count 2 2006.257.16:31:31.61#ibcon#read 3, iclass 16, count 2 2006.257.16:31:31.61#ibcon#about to read 4, iclass 16, count 2 2006.257.16:31:31.61#ibcon#read 4, iclass 16, count 2 2006.257.16:31:31.61#ibcon#about to read 5, iclass 16, count 2 2006.257.16:31:31.61#ibcon#read 5, iclass 16, count 2 2006.257.16:31:31.61#ibcon#about to read 6, iclass 16, count 2 2006.257.16:31:31.61#ibcon#read 6, iclass 16, count 2 2006.257.16:31:31.61#ibcon#end of sib2, iclass 16, count 2 2006.257.16:31:31.61#ibcon#*mode == 0, iclass 16, count 2 2006.257.16:31:31.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.16:31:31.61#ibcon#[25=AT04-07\r\n] 2006.257.16:31:31.61#ibcon#*before write, iclass 16, count 2 2006.257.16:31:31.61#ibcon#enter sib2, iclass 16, count 2 2006.257.16:31:31.61#ibcon#flushed, iclass 16, count 2 2006.257.16:31:31.61#ibcon#about to write, iclass 16, count 2 2006.257.16:31:31.61#ibcon#wrote, iclass 16, count 2 2006.257.16:31:31.61#ibcon#about to read 3, iclass 16, count 2 2006.257.16:31:31.64#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:31:31.64#ibcon#read 3, iclass 16, count 2 2006.257.16:31:31.64#ibcon#about to read 4, iclass 16, count 2 2006.257.16:31:31.64#ibcon#read 4, iclass 16, count 2 2006.257.16:31:31.64#ibcon#about to read 5, iclass 16, count 2 2006.257.16:31:31.64#ibcon#read 5, iclass 16, count 2 2006.257.16:31:31.64#ibcon#about to read 6, iclass 16, count 2 2006.257.16:31:31.64#ibcon#read 6, iclass 16, count 2 2006.257.16:31:31.64#ibcon#end of sib2, iclass 16, count 2 2006.257.16:31:31.64#ibcon#*after write, iclass 16, count 2 2006.257.16:31:31.64#ibcon#*before return 0, iclass 16, count 2 2006.257.16:31:31.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:31:31.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:31:31.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.16:31:31.64#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:31.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:31:31.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:31:31.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:31:31.76#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:31:31.76#ibcon#first serial, iclass 16, count 0 2006.257.16:31:31.76#ibcon#enter sib2, iclass 16, count 0 2006.257.16:31:31.76#ibcon#flushed, iclass 16, count 0 2006.257.16:31:31.76#ibcon#about to write, iclass 16, count 0 2006.257.16:31:31.76#ibcon#wrote, iclass 16, count 0 2006.257.16:31:31.76#ibcon#about to read 3, iclass 16, count 0 2006.257.16:31:31.78#ibcon#read 3, iclass 16, count 0 2006.257.16:31:31.78#ibcon#about to read 4, iclass 16, count 0 2006.257.16:31:31.78#ibcon#read 4, iclass 16, count 0 2006.257.16:31:31.78#ibcon#about to read 5, iclass 16, count 0 2006.257.16:31:31.78#ibcon#read 5, iclass 16, count 0 2006.257.16:31:31.78#ibcon#about to read 6, iclass 16, count 0 2006.257.16:31:31.78#ibcon#read 6, iclass 16, count 0 2006.257.16:31:31.78#ibcon#end of sib2, iclass 16, count 0 2006.257.16:31:31.78#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:31:31.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:31:31.78#ibcon#[25=USB\r\n] 2006.257.16:31:31.78#ibcon#*before write, iclass 16, count 0 2006.257.16:31:31.78#ibcon#enter sib2, iclass 16, count 0 2006.257.16:31:31.78#ibcon#flushed, iclass 16, count 0 2006.257.16:31:31.78#ibcon#about to write, iclass 16, count 0 2006.257.16:31:31.78#ibcon#wrote, iclass 16, count 0 2006.257.16:31:31.78#ibcon#about to read 3, iclass 16, count 0 2006.257.16:31:31.81#ibcon#read 3, iclass 16, count 0 2006.257.16:31:31.81#ibcon#about to read 4, iclass 16, count 0 2006.257.16:31:31.81#ibcon#read 4, iclass 16, count 0 2006.257.16:31:31.81#ibcon#about to read 5, iclass 16, count 0 2006.257.16:31:31.81#ibcon#read 5, iclass 16, count 0 2006.257.16:31:31.81#ibcon#about to read 6, iclass 16, count 0 2006.257.16:31:31.81#ibcon#read 6, iclass 16, count 0 2006.257.16:31:31.81#ibcon#end of sib2, iclass 16, count 0 2006.257.16:31:31.81#ibcon#*after write, iclass 16, count 0 2006.257.16:31:31.81#ibcon#*before return 0, iclass 16, count 0 2006.257.16:31:31.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:31:31.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:31:31.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:31:31.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:31:31.81$vck44/valo=5,734.99 2006.257.16:31:31.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.16:31:31.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.16:31:31.81#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:31.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:31.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:31.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:31.81#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:31:31.81#ibcon#first serial, iclass 20, count 0 2006.257.16:31:31.81#ibcon#enter sib2, iclass 20, count 0 2006.257.16:31:31.81#ibcon#flushed, iclass 20, count 0 2006.257.16:31:31.81#ibcon#about to write, iclass 20, count 0 2006.257.16:31:31.81#ibcon#wrote, iclass 20, count 0 2006.257.16:31:31.81#ibcon#about to read 3, iclass 20, count 0 2006.257.16:31:31.83#ibcon#read 3, iclass 20, count 0 2006.257.16:31:31.83#ibcon#about to read 4, iclass 20, count 0 2006.257.16:31:31.83#ibcon#read 4, iclass 20, count 0 2006.257.16:31:31.83#ibcon#about to read 5, iclass 20, count 0 2006.257.16:31:31.83#ibcon#read 5, iclass 20, count 0 2006.257.16:31:31.83#ibcon#about to read 6, iclass 20, count 0 2006.257.16:31:31.83#ibcon#read 6, iclass 20, count 0 2006.257.16:31:31.83#ibcon#end of sib2, iclass 20, count 0 2006.257.16:31:31.83#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:31:31.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:31:31.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.16:31:31.83#ibcon#*before write, iclass 20, count 0 2006.257.16:31:31.83#ibcon#enter sib2, iclass 20, count 0 2006.257.16:31:31.83#ibcon#flushed, iclass 20, count 0 2006.257.16:31:31.83#ibcon#about to write, iclass 20, count 0 2006.257.16:31:31.83#ibcon#wrote, iclass 20, count 0 2006.257.16:31:31.83#ibcon#about to read 3, iclass 20, count 0 2006.257.16:31:31.87#ibcon#read 3, iclass 20, count 0 2006.257.16:31:31.87#ibcon#about to read 4, iclass 20, count 0 2006.257.16:31:31.87#ibcon#read 4, iclass 20, count 0 2006.257.16:31:31.87#ibcon#about to read 5, iclass 20, count 0 2006.257.16:31:31.87#ibcon#read 5, iclass 20, count 0 2006.257.16:31:31.87#ibcon#about to read 6, iclass 20, count 0 2006.257.16:31:31.87#ibcon#read 6, iclass 20, count 0 2006.257.16:31:31.87#ibcon#end of sib2, iclass 20, count 0 2006.257.16:31:31.87#ibcon#*after write, iclass 20, count 0 2006.257.16:31:31.87#ibcon#*before return 0, iclass 20, count 0 2006.257.16:31:31.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:31.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:31.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:31:31.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:31:31.87$vck44/va=5,4 2006.257.16:31:31.87#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.16:31:31.87#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.16:31:31.87#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:31.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:31.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:31.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:31.93#ibcon#enter wrdev, iclass 22, count 2 2006.257.16:31:31.93#ibcon#first serial, iclass 22, count 2 2006.257.16:31:31.93#ibcon#enter sib2, iclass 22, count 2 2006.257.16:31:31.93#ibcon#flushed, iclass 22, count 2 2006.257.16:31:31.93#ibcon#about to write, iclass 22, count 2 2006.257.16:31:31.93#ibcon#wrote, iclass 22, count 2 2006.257.16:31:31.93#ibcon#about to read 3, iclass 22, count 2 2006.257.16:31:31.95#ibcon#read 3, iclass 22, count 2 2006.257.16:31:31.95#ibcon#about to read 4, iclass 22, count 2 2006.257.16:31:31.95#ibcon#read 4, iclass 22, count 2 2006.257.16:31:31.95#ibcon#about to read 5, iclass 22, count 2 2006.257.16:31:31.95#ibcon#read 5, iclass 22, count 2 2006.257.16:31:31.95#ibcon#about to read 6, iclass 22, count 2 2006.257.16:31:31.95#ibcon#read 6, iclass 22, count 2 2006.257.16:31:31.95#ibcon#end of sib2, iclass 22, count 2 2006.257.16:31:31.95#ibcon#*mode == 0, iclass 22, count 2 2006.257.16:31:31.95#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.16:31:31.95#ibcon#[25=AT05-04\r\n] 2006.257.16:31:31.95#ibcon#*before write, iclass 22, count 2 2006.257.16:31:31.95#ibcon#enter sib2, iclass 22, count 2 2006.257.16:31:31.95#ibcon#flushed, iclass 22, count 2 2006.257.16:31:31.95#ibcon#about to write, iclass 22, count 2 2006.257.16:31:31.95#ibcon#wrote, iclass 22, count 2 2006.257.16:31:31.95#ibcon#about to read 3, iclass 22, count 2 2006.257.16:31:31.98#ibcon#read 3, iclass 22, count 2 2006.257.16:31:31.98#ibcon#about to read 4, iclass 22, count 2 2006.257.16:31:31.98#ibcon#read 4, iclass 22, count 2 2006.257.16:31:31.98#ibcon#about to read 5, iclass 22, count 2 2006.257.16:31:31.98#ibcon#read 5, iclass 22, count 2 2006.257.16:31:31.98#ibcon#about to read 6, iclass 22, count 2 2006.257.16:31:31.98#ibcon#read 6, iclass 22, count 2 2006.257.16:31:31.98#ibcon#end of sib2, iclass 22, count 2 2006.257.16:31:31.98#ibcon#*after write, iclass 22, count 2 2006.257.16:31:31.98#ibcon#*before return 0, iclass 22, count 2 2006.257.16:31:31.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:31.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:31.98#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.16:31:31.98#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:31.98#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:32.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:32.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:32.10#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:31:32.10#ibcon#first serial, iclass 22, count 0 2006.257.16:31:32.10#ibcon#enter sib2, iclass 22, count 0 2006.257.16:31:32.10#ibcon#flushed, iclass 22, count 0 2006.257.16:31:32.10#ibcon#about to write, iclass 22, count 0 2006.257.16:31:32.10#ibcon#wrote, iclass 22, count 0 2006.257.16:31:32.10#ibcon#about to read 3, iclass 22, count 0 2006.257.16:31:32.12#ibcon#read 3, iclass 22, count 0 2006.257.16:31:32.12#ibcon#about to read 4, iclass 22, count 0 2006.257.16:31:32.12#ibcon#read 4, iclass 22, count 0 2006.257.16:31:32.12#ibcon#about to read 5, iclass 22, count 0 2006.257.16:31:32.12#ibcon#read 5, iclass 22, count 0 2006.257.16:31:32.12#ibcon#about to read 6, iclass 22, count 0 2006.257.16:31:32.12#ibcon#read 6, iclass 22, count 0 2006.257.16:31:32.12#ibcon#end of sib2, iclass 22, count 0 2006.257.16:31:32.12#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:31:32.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:31:32.12#ibcon#[25=USB\r\n] 2006.257.16:31:32.12#ibcon#*before write, iclass 22, count 0 2006.257.16:31:32.12#ibcon#enter sib2, iclass 22, count 0 2006.257.16:31:32.12#ibcon#flushed, iclass 22, count 0 2006.257.16:31:32.12#ibcon#about to write, iclass 22, count 0 2006.257.16:31:32.12#ibcon#wrote, iclass 22, count 0 2006.257.16:31:32.12#ibcon#about to read 3, iclass 22, count 0 2006.257.16:31:32.15#ibcon#read 3, iclass 22, count 0 2006.257.16:31:32.15#ibcon#about to read 4, iclass 22, count 0 2006.257.16:31:32.15#ibcon#read 4, iclass 22, count 0 2006.257.16:31:32.15#ibcon#about to read 5, iclass 22, count 0 2006.257.16:31:32.15#ibcon#read 5, iclass 22, count 0 2006.257.16:31:32.15#ibcon#about to read 6, iclass 22, count 0 2006.257.16:31:32.15#ibcon#read 6, iclass 22, count 0 2006.257.16:31:32.15#ibcon#end of sib2, iclass 22, count 0 2006.257.16:31:32.15#ibcon#*after write, iclass 22, count 0 2006.257.16:31:32.15#ibcon#*before return 0, iclass 22, count 0 2006.257.16:31:32.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:32.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:32.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:31:32.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:31:32.15$vck44/valo=6,814.99 2006.257.16:31:32.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.16:31:32.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.16:31:32.15#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:32.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:32.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:32.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:32.15#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:31:32.15#ibcon#first serial, iclass 24, count 0 2006.257.16:31:32.15#ibcon#enter sib2, iclass 24, count 0 2006.257.16:31:32.15#ibcon#flushed, iclass 24, count 0 2006.257.16:31:32.15#ibcon#about to write, iclass 24, count 0 2006.257.16:31:32.15#ibcon#wrote, iclass 24, count 0 2006.257.16:31:32.15#ibcon#about to read 3, iclass 24, count 0 2006.257.16:31:32.17#ibcon#read 3, iclass 24, count 0 2006.257.16:31:32.17#ibcon#about to read 4, iclass 24, count 0 2006.257.16:31:32.17#ibcon#read 4, iclass 24, count 0 2006.257.16:31:32.17#ibcon#about to read 5, iclass 24, count 0 2006.257.16:31:32.17#ibcon#read 5, iclass 24, count 0 2006.257.16:31:32.17#ibcon#about to read 6, iclass 24, count 0 2006.257.16:31:32.17#ibcon#read 6, iclass 24, count 0 2006.257.16:31:32.17#ibcon#end of sib2, iclass 24, count 0 2006.257.16:31:32.17#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:31:32.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:31:32.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.16:31:32.17#ibcon#*before write, iclass 24, count 0 2006.257.16:31:32.17#ibcon#enter sib2, iclass 24, count 0 2006.257.16:31:32.17#ibcon#flushed, iclass 24, count 0 2006.257.16:31:32.17#ibcon#about to write, iclass 24, count 0 2006.257.16:31:32.17#ibcon#wrote, iclass 24, count 0 2006.257.16:31:32.17#ibcon#about to read 3, iclass 24, count 0 2006.257.16:31:32.21#ibcon#read 3, iclass 24, count 0 2006.257.16:31:32.21#ibcon#about to read 4, iclass 24, count 0 2006.257.16:31:32.21#ibcon#read 4, iclass 24, count 0 2006.257.16:31:32.21#ibcon#about to read 5, iclass 24, count 0 2006.257.16:31:32.21#ibcon#read 5, iclass 24, count 0 2006.257.16:31:32.21#ibcon#about to read 6, iclass 24, count 0 2006.257.16:31:32.21#ibcon#read 6, iclass 24, count 0 2006.257.16:31:32.21#ibcon#end of sib2, iclass 24, count 0 2006.257.16:31:32.21#ibcon#*after write, iclass 24, count 0 2006.257.16:31:32.21#ibcon#*before return 0, iclass 24, count 0 2006.257.16:31:32.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:32.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:32.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:31:32.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:31:32.21$vck44/va=6,4 2006.257.16:31:32.21#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.16:31:32.21#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.16:31:32.21#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:32.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:32.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:32.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:32.27#ibcon#enter wrdev, iclass 26, count 2 2006.257.16:31:32.27#ibcon#first serial, iclass 26, count 2 2006.257.16:31:32.27#ibcon#enter sib2, iclass 26, count 2 2006.257.16:31:32.27#ibcon#flushed, iclass 26, count 2 2006.257.16:31:32.27#ibcon#about to write, iclass 26, count 2 2006.257.16:31:32.27#ibcon#wrote, iclass 26, count 2 2006.257.16:31:32.27#ibcon#about to read 3, iclass 26, count 2 2006.257.16:31:32.29#ibcon#read 3, iclass 26, count 2 2006.257.16:31:32.29#ibcon#about to read 4, iclass 26, count 2 2006.257.16:31:32.29#ibcon#read 4, iclass 26, count 2 2006.257.16:31:32.29#ibcon#about to read 5, iclass 26, count 2 2006.257.16:31:32.29#ibcon#read 5, iclass 26, count 2 2006.257.16:31:32.29#ibcon#about to read 6, iclass 26, count 2 2006.257.16:31:32.29#ibcon#read 6, iclass 26, count 2 2006.257.16:31:32.29#ibcon#end of sib2, iclass 26, count 2 2006.257.16:31:32.29#ibcon#*mode == 0, iclass 26, count 2 2006.257.16:31:32.29#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.16:31:32.29#ibcon#[25=AT06-04\r\n] 2006.257.16:31:32.29#ibcon#*before write, iclass 26, count 2 2006.257.16:31:32.29#ibcon#enter sib2, iclass 26, count 2 2006.257.16:31:32.29#ibcon#flushed, iclass 26, count 2 2006.257.16:31:32.29#ibcon#about to write, iclass 26, count 2 2006.257.16:31:32.29#ibcon#wrote, iclass 26, count 2 2006.257.16:31:32.29#ibcon#about to read 3, iclass 26, count 2 2006.257.16:31:32.32#ibcon#read 3, iclass 26, count 2 2006.257.16:31:32.32#ibcon#about to read 4, iclass 26, count 2 2006.257.16:31:32.32#ibcon#read 4, iclass 26, count 2 2006.257.16:31:32.32#ibcon#about to read 5, iclass 26, count 2 2006.257.16:31:32.32#ibcon#read 5, iclass 26, count 2 2006.257.16:31:32.32#ibcon#about to read 6, iclass 26, count 2 2006.257.16:31:32.32#ibcon#read 6, iclass 26, count 2 2006.257.16:31:32.32#ibcon#end of sib2, iclass 26, count 2 2006.257.16:31:32.32#ibcon#*after write, iclass 26, count 2 2006.257.16:31:32.32#ibcon#*before return 0, iclass 26, count 2 2006.257.16:31:32.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:32.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:32.32#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.16:31:32.32#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:32.32#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:32.44#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:32.44#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:32.44#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:31:32.44#ibcon#first serial, iclass 26, count 0 2006.257.16:31:32.44#ibcon#enter sib2, iclass 26, count 0 2006.257.16:31:32.44#ibcon#flushed, iclass 26, count 0 2006.257.16:31:32.44#ibcon#about to write, iclass 26, count 0 2006.257.16:31:32.44#ibcon#wrote, iclass 26, count 0 2006.257.16:31:32.44#ibcon#about to read 3, iclass 26, count 0 2006.257.16:31:32.46#ibcon#read 3, iclass 26, count 0 2006.257.16:31:32.46#ibcon#about to read 4, iclass 26, count 0 2006.257.16:31:32.46#ibcon#read 4, iclass 26, count 0 2006.257.16:31:32.46#ibcon#about to read 5, iclass 26, count 0 2006.257.16:31:32.46#ibcon#read 5, iclass 26, count 0 2006.257.16:31:32.46#ibcon#about to read 6, iclass 26, count 0 2006.257.16:31:32.46#ibcon#read 6, iclass 26, count 0 2006.257.16:31:32.46#ibcon#end of sib2, iclass 26, count 0 2006.257.16:31:32.46#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:31:32.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:31:32.46#ibcon#[25=USB\r\n] 2006.257.16:31:32.46#ibcon#*before write, iclass 26, count 0 2006.257.16:31:32.46#ibcon#enter sib2, iclass 26, count 0 2006.257.16:31:32.46#ibcon#flushed, iclass 26, count 0 2006.257.16:31:32.46#ibcon#about to write, iclass 26, count 0 2006.257.16:31:32.46#ibcon#wrote, iclass 26, count 0 2006.257.16:31:32.46#ibcon#about to read 3, iclass 26, count 0 2006.257.16:31:32.49#ibcon#read 3, iclass 26, count 0 2006.257.16:31:32.49#ibcon#about to read 4, iclass 26, count 0 2006.257.16:31:32.49#ibcon#read 4, iclass 26, count 0 2006.257.16:31:32.49#ibcon#about to read 5, iclass 26, count 0 2006.257.16:31:32.49#ibcon#read 5, iclass 26, count 0 2006.257.16:31:32.49#ibcon#about to read 6, iclass 26, count 0 2006.257.16:31:32.49#ibcon#read 6, iclass 26, count 0 2006.257.16:31:32.49#ibcon#end of sib2, iclass 26, count 0 2006.257.16:31:32.49#ibcon#*after write, iclass 26, count 0 2006.257.16:31:32.49#ibcon#*before return 0, iclass 26, count 0 2006.257.16:31:32.49#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:32.49#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:32.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:31:32.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:31:32.49$vck44/valo=7,864.99 2006.257.16:31:32.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.16:31:32.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.16:31:32.49#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:32.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:32.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:32.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:32.49#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:31:32.49#ibcon#first serial, iclass 28, count 0 2006.257.16:31:32.49#ibcon#enter sib2, iclass 28, count 0 2006.257.16:31:32.49#ibcon#flushed, iclass 28, count 0 2006.257.16:31:32.49#ibcon#about to write, iclass 28, count 0 2006.257.16:31:32.49#ibcon#wrote, iclass 28, count 0 2006.257.16:31:32.49#ibcon#about to read 3, iclass 28, count 0 2006.257.16:31:32.51#ibcon#read 3, iclass 28, count 0 2006.257.16:31:32.51#ibcon#about to read 4, iclass 28, count 0 2006.257.16:31:32.51#ibcon#read 4, iclass 28, count 0 2006.257.16:31:32.51#ibcon#about to read 5, iclass 28, count 0 2006.257.16:31:32.51#ibcon#read 5, iclass 28, count 0 2006.257.16:31:32.51#ibcon#about to read 6, iclass 28, count 0 2006.257.16:31:32.51#ibcon#read 6, iclass 28, count 0 2006.257.16:31:32.51#ibcon#end of sib2, iclass 28, count 0 2006.257.16:31:32.51#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:31:32.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:31:32.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.16:31:32.51#ibcon#*before write, iclass 28, count 0 2006.257.16:31:32.51#ibcon#enter sib2, iclass 28, count 0 2006.257.16:31:32.51#ibcon#flushed, iclass 28, count 0 2006.257.16:31:32.51#ibcon#about to write, iclass 28, count 0 2006.257.16:31:32.51#ibcon#wrote, iclass 28, count 0 2006.257.16:31:32.51#ibcon#about to read 3, iclass 28, count 0 2006.257.16:31:32.55#ibcon#read 3, iclass 28, count 0 2006.257.16:31:32.55#ibcon#about to read 4, iclass 28, count 0 2006.257.16:31:32.55#ibcon#read 4, iclass 28, count 0 2006.257.16:31:32.55#ibcon#about to read 5, iclass 28, count 0 2006.257.16:31:32.55#ibcon#read 5, iclass 28, count 0 2006.257.16:31:32.55#ibcon#about to read 6, iclass 28, count 0 2006.257.16:31:32.55#ibcon#read 6, iclass 28, count 0 2006.257.16:31:32.55#ibcon#end of sib2, iclass 28, count 0 2006.257.16:31:32.55#ibcon#*after write, iclass 28, count 0 2006.257.16:31:32.55#ibcon#*before return 0, iclass 28, count 0 2006.257.16:31:32.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:32.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:32.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:31:32.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:31:32.55$vck44/va=7,4 2006.257.16:31:32.55#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.16:31:32.55#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.16:31:32.55#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:32.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:32.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:32.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:32.61#ibcon#enter wrdev, iclass 30, count 2 2006.257.16:31:32.61#ibcon#first serial, iclass 30, count 2 2006.257.16:31:32.61#ibcon#enter sib2, iclass 30, count 2 2006.257.16:31:32.61#ibcon#flushed, iclass 30, count 2 2006.257.16:31:32.61#ibcon#about to write, iclass 30, count 2 2006.257.16:31:32.61#ibcon#wrote, iclass 30, count 2 2006.257.16:31:32.61#ibcon#about to read 3, iclass 30, count 2 2006.257.16:31:32.63#ibcon#read 3, iclass 30, count 2 2006.257.16:31:32.63#ibcon#about to read 4, iclass 30, count 2 2006.257.16:31:32.63#ibcon#read 4, iclass 30, count 2 2006.257.16:31:32.63#ibcon#about to read 5, iclass 30, count 2 2006.257.16:31:32.63#ibcon#read 5, iclass 30, count 2 2006.257.16:31:32.63#ibcon#about to read 6, iclass 30, count 2 2006.257.16:31:32.63#ibcon#read 6, iclass 30, count 2 2006.257.16:31:32.63#ibcon#end of sib2, iclass 30, count 2 2006.257.16:31:32.63#ibcon#*mode == 0, iclass 30, count 2 2006.257.16:31:32.63#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.16:31:32.63#ibcon#[25=AT07-04\r\n] 2006.257.16:31:32.63#ibcon#*before write, iclass 30, count 2 2006.257.16:31:32.63#ibcon#enter sib2, iclass 30, count 2 2006.257.16:31:32.63#ibcon#flushed, iclass 30, count 2 2006.257.16:31:32.63#ibcon#about to write, iclass 30, count 2 2006.257.16:31:32.63#ibcon#wrote, iclass 30, count 2 2006.257.16:31:32.63#ibcon#about to read 3, iclass 30, count 2 2006.257.16:31:32.66#ibcon#read 3, iclass 30, count 2 2006.257.16:31:32.66#ibcon#about to read 4, iclass 30, count 2 2006.257.16:31:32.66#ibcon#read 4, iclass 30, count 2 2006.257.16:31:32.66#ibcon#about to read 5, iclass 30, count 2 2006.257.16:31:32.66#ibcon#read 5, iclass 30, count 2 2006.257.16:31:32.66#ibcon#about to read 6, iclass 30, count 2 2006.257.16:31:32.66#ibcon#read 6, iclass 30, count 2 2006.257.16:31:32.66#ibcon#end of sib2, iclass 30, count 2 2006.257.16:31:32.66#ibcon#*after write, iclass 30, count 2 2006.257.16:31:32.66#ibcon#*before return 0, iclass 30, count 2 2006.257.16:31:32.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:32.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:32.66#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.16:31:32.66#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:32.66#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:32.78#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:32.78#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:32.78#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:31:32.78#ibcon#first serial, iclass 30, count 0 2006.257.16:31:32.78#ibcon#enter sib2, iclass 30, count 0 2006.257.16:31:32.78#ibcon#flushed, iclass 30, count 0 2006.257.16:31:32.78#ibcon#about to write, iclass 30, count 0 2006.257.16:31:32.78#ibcon#wrote, iclass 30, count 0 2006.257.16:31:32.78#ibcon#about to read 3, iclass 30, count 0 2006.257.16:31:32.80#ibcon#read 3, iclass 30, count 0 2006.257.16:31:32.80#ibcon#about to read 4, iclass 30, count 0 2006.257.16:31:32.80#ibcon#read 4, iclass 30, count 0 2006.257.16:31:32.80#ibcon#about to read 5, iclass 30, count 0 2006.257.16:31:32.80#ibcon#read 5, iclass 30, count 0 2006.257.16:31:32.80#ibcon#about to read 6, iclass 30, count 0 2006.257.16:31:32.80#ibcon#read 6, iclass 30, count 0 2006.257.16:31:32.80#ibcon#end of sib2, iclass 30, count 0 2006.257.16:31:32.80#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:31:32.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:31:32.80#ibcon#[25=USB\r\n] 2006.257.16:31:32.80#ibcon#*before write, iclass 30, count 0 2006.257.16:31:32.80#ibcon#enter sib2, iclass 30, count 0 2006.257.16:31:32.80#ibcon#flushed, iclass 30, count 0 2006.257.16:31:32.80#ibcon#about to write, iclass 30, count 0 2006.257.16:31:32.80#ibcon#wrote, iclass 30, count 0 2006.257.16:31:32.80#ibcon#about to read 3, iclass 30, count 0 2006.257.16:31:32.83#ibcon#read 3, iclass 30, count 0 2006.257.16:31:32.83#ibcon#about to read 4, iclass 30, count 0 2006.257.16:31:32.83#ibcon#read 4, iclass 30, count 0 2006.257.16:31:32.83#ibcon#about to read 5, iclass 30, count 0 2006.257.16:31:32.83#ibcon#read 5, iclass 30, count 0 2006.257.16:31:32.83#ibcon#about to read 6, iclass 30, count 0 2006.257.16:31:32.83#ibcon#read 6, iclass 30, count 0 2006.257.16:31:32.83#ibcon#end of sib2, iclass 30, count 0 2006.257.16:31:32.83#ibcon#*after write, iclass 30, count 0 2006.257.16:31:32.83#ibcon#*before return 0, iclass 30, count 0 2006.257.16:31:32.83#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:32.83#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:32.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:31:32.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:31:32.83$vck44/valo=8,884.99 2006.257.16:31:32.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.16:31:32.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.16:31:32.83#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:32.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:32.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:32.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:32.83#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:31:32.83#ibcon#first serial, iclass 32, count 0 2006.257.16:31:32.83#ibcon#enter sib2, iclass 32, count 0 2006.257.16:31:32.83#ibcon#flushed, iclass 32, count 0 2006.257.16:31:32.83#ibcon#about to write, iclass 32, count 0 2006.257.16:31:32.83#ibcon#wrote, iclass 32, count 0 2006.257.16:31:32.83#ibcon#about to read 3, iclass 32, count 0 2006.257.16:31:32.85#ibcon#read 3, iclass 32, count 0 2006.257.16:31:32.85#ibcon#about to read 4, iclass 32, count 0 2006.257.16:31:32.85#ibcon#read 4, iclass 32, count 0 2006.257.16:31:32.85#ibcon#about to read 5, iclass 32, count 0 2006.257.16:31:32.85#ibcon#read 5, iclass 32, count 0 2006.257.16:31:32.85#ibcon#about to read 6, iclass 32, count 0 2006.257.16:31:32.85#ibcon#read 6, iclass 32, count 0 2006.257.16:31:32.85#ibcon#end of sib2, iclass 32, count 0 2006.257.16:31:32.85#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:31:32.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:31:32.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.16:31:32.85#ibcon#*before write, iclass 32, count 0 2006.257.16:31:32.85#ibcon#enter sib2, iclass 32, count 0 2006.257.16:31:32.85#ibcon#flushed, iclass 32, count 0 2006.257.16:31:32.85#ibcon#about to write, iclass 32, count 0 2006.257.16:31:32.85#ibcon#wrote, iclass 32, count 0 2006.257.16:31:32.85#ibcon#about to read 3, iclass 32, count 0 2006.257.16:31:32.89#ibcon#read 3, iclass 32, count 0 2006.257.16:31:32.89#ibcon#about to read 4, iclass 32, count 0 2006.257.16:31:32.89#ibcon#read 4, iclass 32, count 0 2006.257.16:31:32.89#ibcon#about to read 5, iclass 32, count 0 2006.257.16:31:32.89#ibcon#read 5, iclass 32, count 0 2006.257.16:31:32.89#ibcon#about to read 6, iclass 32, count 0 2006.257.16:31:32.89#ibcon#read 6, iclass 32, count 0 2006.257.16:31:32.89#ibcon#end of sib2, iclass 32, count 0 2006.257.16:31:32.89#ibcon#*after write, iclass 32, count 0 2006.257.16:31:32.89#ibcon#*before return 0, iclass 32, count 0 2006.257.16:31:32.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:32.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:32.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:31:32.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:31:32.89$vck44/va=8,4 2006.257.16:31:32.89#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.16:31:32.89#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.16:31:32.89#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:32.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:31:32.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:31:32.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:31:32.95#ibcon#enter wrdev, iclass 34, count 2 2006.257.16:31:32.95#ibcon#first serial, iclass 34, count 2 2006.257.16:31:32.95#ibcon#enter sib2, iclass 34, count 2 2006.257.16:31:32.95#ibcon#flushed, iclass 34, count 2 2006.257.16:31:32.95#ibcon#about to write, iclass 34, count 2 2006.257.16:31:32.95#ibcon#wrote, iclass 34, count 2 2006.257.16:31:32.95#ibcon#about to read 3, iclass 34, count 2 2006.257.16:31:32.97#ibcon#read 3, iclass 34, count 2 2006.257.16:31:32.97#ibcon#about to read 4, iclass 34, count 2 2006.257.16:31:32.97#ibcon#read 4, iclass 34, count 2 2006.257.16:31:32.97#ibcon#about to read 5, iclass 34, count 2 2006.257.16:31:32.97#ibcon#read 5, iclass 34, count 2 2006.257.16:31:32.97#ibcon#about to read 6, iclass 34, count 2 2006.257.16:31:32.97#ibcon#read 6, iclass 34, count 2 2006.257.16:31:32.97#ibcon#end of sib2, iclass 34, count 2 2006.257.16:31:32.97#ibcon#*mode == 0, iclass 34, count 2 2006.257.16:31:32.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.16:31:32.97#ibcon#[25=AT08-04\r\n] 2006.257.16:31:32.97#ibcon#*before write, iclass 34, count 2 2006.257.16:31:32.97#ibcon#enter sib2, iclass 34, count 2 2006.257.16:31:32.97#ibcon#flushed, iclass 34, count 2 2006.257.16:31:32.97#ibcon#about to write, iclass 34, count 2 2006.257.16:31:32.97#ibcon#wrote, iclass 34, count 2 2006.257.16:31:32.97#ibcon#about to read 3, iclass 34, count 2 2006.257.16:31:33.00#ibcon#read 3, iclass 34, count 2 2006.257.16:31:33.00#ibcon#about to read 4, iclass 34, count 2 2006.257.16:31:33.00#ibcon#read 4, iclass 34, count 2 2006.257.16:31:33.00#ibcon#about to read 5, iclass 34, count 2 2006.257.16:31:33.00#ibcon#read 5, iclass 34, count 2 2006.257.16:31:33.00#ibcon#about to read 6, iclass 34, count 2 2006.257.16:31:33.00#ibcon#read 6, iclass 34, count 2 2006.257.16:31:33.00#ibcon#end of sib2, iclass 34, count 2 2006.257.16:31:33.00#ibcon#*after write, iclass 34, count 2 2006.257.16:31:33.00#ibcon#*before return 0, iclass 34, count 2 2006.257.16:31:33.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:31:33.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:31:33.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.16:31:33.00#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:33.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:31:33.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:31:33.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:31:33.12#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:31:33.12#ibcon#first serial, iclass 34, count 0 2006.257.16:31:33.12#ibcon#enter sib2, iclass 34, count 0 2006.257.16:31:33.12#ibcon#flushed, iclass 34, count 0 2006.257.16:31:33.12#ibcon#about to write, iclass 34, count 0 2006.257.16:31:33.12#ibcon#wrote, iclass 34, count 0 2006.257.16:31:33.12#ibcon#about to read 3, iclass 34, count 0 2006.257.16:31:33.14#ibcon#read 3, iclass 34, count 0 2006.257.16:31:33.14#ibcon#about to read 4, iclass 34, count 0 2006.257.16:31:33.14#ibcon#read 4, iclass 34, count 0 2006.257.16:31:33.14#ibcon#about to read 5, iclass 34, count 0 2006.257.16:31:33.14#ibcon#read 5, iclass 34, count 0 2006.257.16:31:33.14#ibcon#about to read 6, iclass 34, count 0 2006.257.16:31:33.14#ibcon#read 6, iclass 34, count 0 2006.257.16:31:33.14#ibcon#end of sib2, iclass 34, count 0 2006.257.16:31:33.14#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:31:33.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:31:33.14#ibcon#[25=USB\r\n] 2006.257.16:31:33.14#ibcon#*before write, iclass 34, count 0 2006.257.16:31:33.14#ibcon#enter sib2, iclass 34, count 0 2006.257.16:31:33.14#ibcon#flushed, iclass 34, count 0 2006.257.16:31:33.14#ibcon#about to write, iclass 34, count 0 2006.257.16:31:33.14#ibcon#wrote, iclass 34, count 0 2006.257.16:31:33.14#ibcon#about to read 3, iclass 34, count 0 2006.257.16:31:33.17#ibcon#read 3, iclass 34, count 0 2006.257.16:31:33.17#ibcon#about to read 4, iclass 34, count 0 2006.257.16:31:33.17#ibcon#read 4, iclass 34, count 0 2006.257.16:31:33.17#ibcon#about to read 5, iclass 34, count 0 2006.257.16:31:33.17#ibcon#read 5, iclass 34, count 0 2006.257.16:31:33.17#ibcon#about to read 6, iclass 34, count 0 2006.257.16:31:33.17#ibcon#read 6, iclass 34, count 0 2006.257.16:31:33.17#ibcon#end of sib2, iclass 34, count 0 2006.257.16:31:33.17#ibcon#*after write, iclass 34, count 0 2006.257.16:31:33.17#ibcon#*before return 0, iclass 34, count 0 2006.257.16:31:33.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:31:33.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:31:33.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:31:33.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:31:33.17$vck44/vblo=1,629.99 2006.257.16:31:33.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.16:31:33.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.16:31:33.17#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:33.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:31:33.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:31:33.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:31:33.17#ibcon#enter wrdev, iclass 36, count 0 2006.257.16:31:33.17#ibcon#first serial, iclass 36, count 0 2006.257.16:31:33.17#ibcon#enter sib2, iclass 36, count 0 2006.257.16:31:33.17#ibcon#flushed, iclass 36, count 0 2006.257.16:31:33.17#ibcon#about to write, iclass 36, count 0 2006.257.16:31:33.17#ibcon#wrote, iclass 36, count 0 2006.257.16:31:33.17#ibcon#about to read 3, iclass 36, count 0 2006.257.16:31:33.19#ibcon#read 3, iclass 36, count 0 2006.257.16:31:33.19#ibcon#about to read 4, iclass 36, count 0 2006.257.16:31:33.19#ibcon#read 4, iclass 36, count 0 2006.257.16:31:33.19#ibcon#about to read 5, iclass 36, count 0 2006.257.16:31:33.19#ibcon#read 5, iclass 36, count 0 2006.257.16:31:33.19#ibcon#about to read 6, iclass 36, count 0 2006.257.16:31:33.19#ibcon#read 6, iclass 36, count 0 2006.257.16:31:33.19#ibcon#end of sib2, iclass 36, count 0 2006.257.16:31:33.19#ibcon#*mode == 0, iclass 36, count 0 2006.257.16:31:33.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.16:31:33.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.16:31:33.19#ibcon#*before write, iclass 36, count 0 2006.257.16:31:33.19#ibcon#enter sib2, iclass 36, count 0 2006.257.16:31:33.19#ibcon#flushed, iclass 36, count 0 2006.257.16:31:33.19#ibcon#about to write, iclass 36, count 0 2006.257.16:31:33.19#ibcon#wrote, iclass 36, count 0 2006.257.16:31:33.19#ibcon#about to read 3, iclass 36, count 0 2006.257.16:31:33.23#ibcon#read 3, iclass 36, count 0 2006.257.16:31:33.23#ibcon#about to read 4, iclass 36, count 0 2006.257.16:31:33.23#ibcon#read 4, iclass 36, count 0 2006.257.16:31:33.23#ibcon#about to read 5, iclass 36, count 0 2006.257.16:31:33.23#ibcon#read 5, iclass 36, count 0 2006.257.16:31:33.23#ibcon#about to read 6, iclass 36, count 0 2006.257.16:31:33.23#ibcon#read 6, iclass 36, count 0 2006.257.16:31:33.23#ibcon#end of sib2, iclass 36, count 0 2006.257.16:31:33.23#ibcon#*after write, iclass 36, count 0 2006.257.16:31:33.23#ibcon#*before return 0, iclass 36, count 0 2006.257.16:31:33.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:31:33.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:31:33.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.16:31:33.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.16:31:33.23$vck44/vb=1,4 2006.257.16:31:33.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.16:31:33.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.16:31:33.23#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:33.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:31:33.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:31:33.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:31:33.23#ibcon#enter wrdev, iclass 38, count 2 2006.257.16:31:33.23#ibcon#first serial, iclass 38, count 2 2006.257.16:31:33.23#ibcon#enter sib2, iclass 38, count 2 2006.257.16:31:33.23#ibcon#flushed, iclass 38, count 2 2006.257.16:31:33.23#ibcon#about to write, iclass 38, count 2 2006.257.16:31:33.23#ibcon#wrote, iclass 38, count 2 2006.257.16:31:33.23#ibcon#about to read 3, iclass 38, count 2 2006.257.16:31:33.25#ibcon#read 3, iclass 38, count 2 2006.257.16:31:33.25#ibcon#about to read 4, iclass 38, count 2 2006.257.16:31:33.25#ibcon#read 4, iclass 38, count 2 2006.257.16:31:33.25#ibcon#about to read 5, iclass 38, count 2 2006.257.16:31:33.25#ibcon#read 5, iclass 38, count 2 2006.257.16:31:33.25#ibcon#about to read 6, iclass 38, count 2 2006.257.16:31:33.25#ibcon#read 6, iclass 38, count 2 2006.257.16:31:33.25#ibcon#end of sib2, iclass 38, count 2 2006.257.16:31:33.25#ibcon#*mode == 0, iclass 38, count 2 2006.257.16:31:33.25#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.16:31:33.25#ibcon#[27=AT01-04\r\n] 2006.257.16:31:33.25#ibcon#*before write, iclass 38, count 2 2006.257.16:31:33.25#ibcon#enter sib2, iclass 38, count 2 2006.257.16:31:33.25#ibcon#flushed, iclass 38, count 2 2006.257.16:31:33.25#ibcon#about to write, iclass 38, count 2 2006.257.16:31:33.25#ibcon#wrote, iclass 38, count 2 2006.257.16:31:33.25#ibcon#about to read 3, iclass 38, count 2 2006.257.16:31:33.28#ibcon#read 3, iclass 38, count 2 2006.257.16:31:33.28#ibcon#about to read 4, iclass 38, count 2 2006.257.16:31:33.28#ibcon#read 4, iclass 38, count 2 2006.257.16:31:33.28#ibcon#about to read 5, iclass 38, count 2 2006.257.16:31:33.28#ibcon#read 5, iclass 38, count 2 2006.257.16:31:33.28#ibcon#about to read 6, iclass 38, count 2 2006.257.16:31:33.28#ibcon#read 6, iclass 38, count 2 2006.257.16:31:33.28#ibcon#end of sib2, iclass 38, count 2 2006.257.16:31:33.28#ibcon#*after write, iclass 38, count 2 2006.257.16:31:33.28#ibcon#*before return 0, iclass 38, count 2 2006.257.16:31:33.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:31:33.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:31:33.28#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.16:31:33.28#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:33.28#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:31:33.40#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:31:33.40#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:31:33.40#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:31:33.40#ibcon#first serial, iclass 38, count 0 2006.257.16:31:33.40#ibcon#enter sib2, iclass 38, count 0 2006.257.16:31:33.40#ibcon#flushed, iclass 38, count 0 2006.257.16:31:33.40#ibcon#about to write, iclass 38, count 0 2006.257.16:31:33.40#ibcon#wrote, iclass 38, count 0 2006.257.16:31:33.40#ibcon#about to read 3, iclass 38, count 0 2006.257.16:31:33.42#ibcon#read 3, iclass 38, count 0 2006.257.16:31:33.42#ibcon#about to read 4, iclass 38, count 0 2006.257.16:31:33.42#ibcon#read 4, iclass 38, count 0 2006.257.16:31:33.42#ibcon#about to read 5, iclass 38, count 0 2006.257.16:31:33.42#ibcon#read 5, iclass 38, count 0 2006.257.16:31:33.42#ibcon#about to read 6, iclass 38, count 0 2006.257.16:31:33.42#ibcon#read 6, iclass 38, count 0 2006.257.16:31:33.42#ibcon#end of sib2, iclass 38, count 0 2006.257.16:31:33.42#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:31:33.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:31:33.42#ibcon#[27=USB\r\n] 2006.257.16:31:33.42#ibcon#*before write, iclass 38, count 0 2006.257.16:31:33.42#ibcon#enter sib2, iclass 38, count 0 2006.257.16:31:33.42#ibcon#flushed, iclass 38, count 0 2006.257.16:31:33.42#ibcon#about to write, iclass 38, count 0 2006.257.16:31:33.42#ibcon#wrote, iclass 38, count 0 2006.257.16:31:33.42#ibcon#about to read 3, iclass 38, count 0 2006.257.16:31:33.45#ibcon#read 3, iclass 38, count 0 2006.257.16:31:33.45#ibcon#about to read 4, iclass 38, count 0 2006.257.16:31:33.45#ibcon#read 4, iclass 38, count 0 2006.257.16:31:33.45#ibcon#about to read 5, iclass 38, count 0 2006.257.16:31:33.45#ibcon#read 5, iclass 38, count 0 2006.257.16:31:33.45#ibcon#about to read 6, iclass 38, count 0 2006.257.16:31:33.45#ibcon#read 6, iclass 38, count 0 2006.257.16:31:33.45#ibcon#end of sib2, iclass 38, count 0 2006.257.16:31:33.45#ibcon#*after write, iclass 38, count 0 2006.257.16:31:33.45#ibcon#*before return 0, iclass 38, count 0 2006.257.16:31:33.45#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:31:33.45#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:31:33.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:31:33.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:31:33.45$vck44/vblo=2,634.99 2006.257.16:31:33.45#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.16:31:33.45#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.16:31:33.45#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:33.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:31:33.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:31:33.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:31:33.45#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:31:33.45#ibcon#first serial, iclass 40, count 0 2006.257.16:31:33.45#ibcon#enter sib2, iclass 40, count 0 2006.257.16:31:33.45#ibcon#flushed, iclass 40, count 0 2006.257.16:31:33.45#ibcon#about to write, iclass 40, count 0 2006.257.16:31:33.45#ibcon#wrote, iclass 40, count 0 2006.257.16:31:33.45#ibcon#about to read 3, iclass 40, count 0 2006.257.16:31:33.47#ibcon#read 3, iclass 40, count 0 2006.257.16:31:33.47#ibcon#about to read 4, iclass 40, count 0 2006.257.16:31:33.47#ibcon#read 4, iclass 40, count 0 2006.257.16:31:33.47#ibcon#about to read 5, iclass 40, count 0 2006.257.16:31:33.47#ibcon#read 5, iclass 40, count 0 2006.257.16:31:33.47#ibcon#about to read 6, iclass 40, count 0 2006.257.16:31:33.47#ibcon#read 6, iclass 40, count 0 2006.257.16:31:33.47#ibcon#end of sib2, iclass 40, count 0 2006.257.16:31:33.47#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:31:33.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:31:33.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.16:31:33.47#ibcon#*before write, iclass 40, count 0 2006.257.16:31:33.47#ibcon#enter sib2, iclass 40, count 0 2006.257.16:31:33.47#ibcon#flushed, iclass 40, count 0 2006.257.16:31:33.47#ibcon#about to write, iclass 40, count 0 2006.257.16:31:33.47#ibcon#wrote, iclass 40, count 0 2006.257.16:31:33.47#ibcon#about to read 3, iclass 40, count 0 2006.257.16:31:33.51#ibcon#read 3, iclass 40, count 0 2006.257.16:31:33.51#ibcon#about to read 4, iclass 40, count 0 2006.257.16:31:33.51#ibcon#read 4, iclass 40, count 0 2006.257.16:31:33.51#ibcon#about to read 5, iclass 40, count 0 2006.257.16:31:33.51#ibcon#read 5, iclass 40, count 0 2006.257.16:31:33.51#ibcon#about to read 6, iclass 40, count 0 2006.257.16:31:33.51#ibcon#read 6, iclass 40, count 0 2006.257.16:31:33.51#ibcon#end of sib2, iclass 40, count 0 2006.257.16:31:33.51#ibcon#*after write, iclass 40, count 0 2006.257.16:31:33.51#ibcon#*before return 0, iclass 40, count 0 2006.257.16:31:33.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:31:33.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:31:33.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:31:33.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:31:33.51$vck44/vb=2,5 2006.257.16:31:33.51#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.16:31:33.51#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.16:31:33.51#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:33.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:31:33.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:31:33.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:31:33.57#ibcon#enter wrdev, iclass 4, count 2 2006.257.16:31:33.57#ibcon#first serial, iclass 4, count 2 2006.257.16:31:33.57#ibcon#enter sib2, iclass 4, count 2 2006.257.16:31:33.57#ibcon#flushed, iclass 4, count 2 2006.257.16:31:33.57#ibcon#about to write, iclass 4, count 2 2006.257.16:31:33.57#ibcon#wrote, iclass 4, count 2 2006.257.16:31:33.57#ibcon#about to read 3, iclass 4, count 2 2006.257.16:31:33.59#ibcon#read 3, iclass 4, count 2 2006.257.16:31:33.59#ibcon#about to read 4, iclass 4, count 2 2006.257.16:31:33.59#ibcon#read 4, iclass 4, count 2 2006.257.16:31:33.59#ibcon#about to read 5, iclass 4, count 2 2006.257.16:31:33.59#ibcon#read 5, iclass 4, count 2 2006.257.16:31:33.59#ibcon#about to read 6, iclass 4, count 2 2006.257.16:31:33.59#ibcon#read 6, iclass 4, count 2 2006.257.16:31:33.59#ibcon#end of sib2, iclass 4, count 2 2006.257.16:31:33.59#ibcon#*mode == 0, iclass 4, count 2 2006.257.16:31:33.59#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.16:31:33.59#ibcon#[27=AT02-05\r\n] 2006.257.16:31:33.59#ibcon#*before write, iclass 4, count 2 2006.257.16:31:33.59#ibcon#enter sib2, iclass 4, count 2 2006.257.16:31:33.59#ibcon#flushed, iclass 4, count 2 2006.257.16:31:33.59#ibcon#about to write, iclass 4, count 2 2006.257.16:31:33.59#ibcon#wrote, iclass 4, count 2 2006.257.16:31:33.59#ibcon#about to read 3, iclass 4, count 2 2006.257.16:31:33.62#ibcon#read 3, iclass 4, count 2 2006.257.16:31:33.62#ibcon#about to read 4, iclass 4, count 2 2006.257.16:31:33.62#ibcon#read 4, iclass 4, count 2 2006.257.16:31:33.62#ibcon#about to read 5, iclass 4, count 2 2006.257.16:31:33.62#ibcon#read 5, iclass 4, count 2 2006.257.16:31:33.62#ibcon#about to read 6, iclass 4, count 2 2006.257.16:31:33.62#ibcon#read 6, iclass 4, count 2 2006.257.16:31:33.62#ibcon#end of sib2, iclass 4, count 2 2006.257.16:31:33.62#ibcon#*after write, iclass 4, count 2 2006.257.16:31:33.62#ibcon#*before return 0, iclass 4, count 2 2006.257.16:31:33.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:31:33.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:31:33.62#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.16:31:33.62#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:33.62#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:31:33.74#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:31:33.74#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:31:33.74#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:31:33.74#ibcon#first serial, iclass 4, count 0 2006.257.16:31:33.74#ibcon#enter sib2, iclass 4, count 0 2006.257.16:31:33.74#ibcon#flushed, iclass 4, count 0 2006.257.16:31:33.74#ibcon#about to write, iclass 4, count 0 2006.257.16:31:33.74#ibcon#wrote, iclass 4, count 0 2006.257.16:31:33.74#ibcon#about to read 3, iclass 4, count 0 2006.257.16:31:33.76#ibcon#read 3, iclass 4, count 0 2006.257.16:31:33.76#ibcon#about to read 4, iclass 4, count 0 2006.257.16:31:33.76#ibcon#read 4, iclass 4, count 0 2006.257.16:31:33.76#ibcon#about to read 5, iclass 4, count 0 2006.257.16:31:33.76#ibcon#read 5, iclass 4, count 0 2006.257.16:31:33.76#ibcon#about to read 6, iclass 4, count 0 2006.257.16:31:33.76#ibcon#read 6, iclass 4, count 0 2006.257.16:31:33.76#ibcon#end of sib2, iclass 4, count 0 2006.257.16:31:33.76#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:31:33.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:31:33.76#ibcon#[27=USB\r\n] 2006.257.16:31:33.76#ibcon#*before write, iclass 4, count 0 2006.257.16:31:33.76#ibcon#enter sib2, iclass 4, count 0 2006.257.16:31:33.76#ibcon#flushed, iclass 4, count 0 2006.257.16:31:33.76#ibcon#about to write, iclass 4, count 0 2006.257.16:31:33.76#ibcon#wrote, iclass 4, count 0 2006.257.16:31:33.76#ibcon#about to read 3, iclass 4, count 0 2006.257.16:31:33.79#ibcon#read 3, iclass 4, count 0 2006.257.16:31:33.79#ibcon#about to read 4, iclass 4, count 0 2006.257.16:31:33.79#ibcon#read 4, iclass 4, count 0 2006.257.16:31:33.79#ibcon#about to read 5, iclass 4, count 0 2006.257.16:31:33.79#ibcon#read 5, iclass 4, count 0 2006.257.16:31:33.79#ibcon#about to read 6, iclass 4, count 0 2006.257.16:31:33.79#ibcon#read 6, iclass 4, count 0 2006.257.16:31:33.79#ibcon#end of sib2, iclass 4, count 0 2006.257.16:31:33.79#ibcon#*after write, iclass 4, count 0 2006.257.16:31:33.79#ibcon#*before return 0, iclass 4, count 0 2006.257.16:31:33.79#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:31:33.79#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:31:33.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:31:33.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:31:33.79$vck44/vblo=3,649.99 2006.257.16:31:33.79#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.16:31:33.79#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.16:31:33.79#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:33.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:31:33.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:31:33.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:31:33.79#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:31:33.79#ibcon#first serial, iclass 6, count 0 2006.257.16:31:33.79#ibcon#enter sib2, iclass 6, count 0 2006.257.16:31:33.79#ibcon#flushed, iclass 6, count 0 2006.257.16:31:33.79#ibcon#about to write, iclass 6, count 0 2006.257.16:31:33.79#ibcon#wrote, iclass 6, count 0 2006.257.16:31:33.79#ibcon#about to read 3, iclass 6, count 0 2006.257.16:31:33.81#ibcon#read 3, iclass 6, count 0 2006.257.16:31:33.81#ibcon#about to read 4, iclass 6, count 0 2006.257.16:31:33.81#ibcon#read 4, iclass 6, count 0 2006.257.16:31:33.81#ibcon#about to read 5, iclass 6, count 0 2006.257.16:31:33.81#ibcon#read 5, iclass 6, count 0 2006.257.16:31:33.81#ibcon#about to read 6, iclass 6, count 0 2006.257.16:31:33.81#ibcon#read 6, iclass 6, count 0 2006.257.16:31:33.81#ibcon#end of sib2, iclass 6, count 0 2006.257.16:31:33.81#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:31:33.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:31:33.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.16:31:33.81#ibcon#*before write, iclass 6, count 0 2006.257.16:31:33.81#ibcon#enter sib2, iclass 6, count 0 2006.257.16:31:33.81#ibcon#flushed, iclass 6, count 0 2006.257.16:31:33.81#ibcon#about to write, iclass 6, count 0 2006.257.16:31:33.81#ibcon#wrote, iclass 6, count 0 2006.257.16:31:33.81#ibcon#about to read 3, iclass 6, count 0 2006.257.16:31:33.85#ibcon#read 3, iclass 6, count 0 2006.257.16:31:33.85#ibcon#about to read 4, iclass 6, count 0 2006.257.16:31:33.85#ibcon#read 4, iclass 6, count 0 2006.257.16:31:33.85#ibcon#about to read 5, iclass 6, count 0 2006.257.16:31:33.85#ibcon#read 5, iclass 6, count 0 2006.257.16:31:33.85#ibcon#about to read 6, iclass 6, count 0 2006.257.16:31:33.85#ibcon#read 6, iclass 6, count 0 2006.257.16:31:33.85#ibcon#end of sib2, iclass 6, count 0 2006.257.16:31:33.85#ibcon#*after write, iclass 6, count 0 2006.257.16:31:33.85#ibcon#*before return 0, iclass 6, count 0 2006.257.16:31:33.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:31:33.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:31:33.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:31:33.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:31:33.85$vck44/vb=3,4 2006.257.16:31:33.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.16:31:33.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.16:31:33.85#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:33.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:31:33.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:31:33.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:31:33.91#ibcon#enter wrdev, iclass 10, count 2 2006.257.16:31:33.91#ibcon#first serial, iclass 10, count 2 2006.257.16:31:33.91#ibcon#enter sib2, iclass 10, count 2 2006.257.16:31:33.91#ibcon#flushed, iclass 10, count 2 2006.257.16:31:33.91#ibcon#about to write, iclass 10, count 2 2006.257.16:31:33.91#ibcon#wrote, iclass 10, count 2 2006.257.16:31:33.91#ibcon#about to read 3, iclass 10, count 2 2006.257.16:31:33.93#ibcon#read 3, iclass 10, count 2 2006.257.16:31:33.93#ibcon#about to read 4, iclass 10, count 2 2006.257.16:31:33.93#ibcon#read 4, iclass 10, count 2 2006.257.16:31:33.93#ibcon#about to read 5, iclass 10, count 2 2006.257.16:31:33.93#ibcon#read 5, iclass 10, count 2 2006.257.16:31:33.93#ibcon#about to read 6, iclass 10, count 2 2006.257.16:31:33.93#ibcon#read 6, iclass 10, count 2 2006.257.16:31:33.93#ibcon#end of sib2, iclass 10, count 2 2006.257.16:31:33.93#ibcon#*mode == 0, iclass 10, count 2 2006.257.16:31:33.93#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.16:31:33.93#ibcon#[27=AT03-04\r\n] 2006.257.16:31:33.93#ibcon#*before write, iclass 10, count 2 2006.257.16:31:33.93#ibcon#enter sib2, iclass 10, count 2 2006.257.16:31:33.93#ibcon#flushed, iclass 10, count 2 2006.257.16:31:33.93#ibcon#about to write, iclass 10, count 2 2006.257.16:31:33.93#ibcon#wrote, iclass 10, count 2 2006.257.16:31:33.93#ibcon#about to read 3, iclass 10, count 2 2006.257.16:31:33.96#ibcon#read 3, iclass 10, count 2 2006.257.16:31:33.96#ibcon#about to read 4, iclass 10, count 2 2006.257.16:31:33.96#ibcon#read 4, iclass 10, count 2 2006.257.16:31:33.96#ibcon#about to read 5, iclass 10, count 2 2006.257.16:31:33.96#ibcon#read 5, iclass 10, count 2 2006.257.16:31:33.96#ibcon#about to read 6, iclass 10, count 2 2006.257.16:31:33.96#ibcon#read 6, iclass 10, count 2 2006.257.16:31:33.96#ibcon#end of sib2, iclass 10, count 2 2006.257.16:31:33.96#ibcon#*after write, iclass 10, count 2 2006.257.16:31:33.96#ibcon#*before return 0, iclass 10, count 2 2006.257.16:31:33.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:31:33.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:31:33.96#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.16:31:33.96#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:33.96#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:31:34.08#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:31:34.08#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:31:34.08#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:31:34.08#ibcon#first serial, iclass 10, count 0 2006.257.16:31:34.08#ibcon#enter sib2, iclass 10, count 0 2006.257.16:31:34.08#ibcon#flushed, iclass 10, count 0 2006.257.16:31:34.08#ibcon#about to write, iclass 10, count 0 2006.257.16:31:34.08#ibcon#wrote, iclass 10, count 0 2006.257.16:31:34.08#ibcon#about to read 3, iclass 10, count 0 2006.257.16:31:34.10#ibcon#read 3, iclass 10, count 0 2006.257.16:31:34.10#ibcon#about to read 4, iclass 10, count 0 2006.257.16:31:34.10#ibcon#read 4, iclass 10, count 0 2006.257.16:31:34.10#ibcon#about to read 5, iclass 10, count 0 2006.257.16:31:34.10#ibcon#read 5, iclass 10, count 0 2006.257.16:31:34.10#ibcon#about to read 6, iclass 10, count 0 2006.257.16:31:34.10#ibcon#read 6, iclass 10, count 0 2006.257.16:31:34.10#ibcon#end of sib2, iclass 10, count 0 2006.257.16:31:34.10#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:31:34.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:31:34.10#ibcon#[27=USB\r\n] 2006.257.16:31:34.10#ibcon#*before write, iclass 10, count 0 2006.257.16:31:34.10#ibcon#enter sib2, iclass 10, count 0 2006.257.16:31:34.10#ibcon#flushed, iclass 10, count 0 2006.257.16:31:34.10#ibcon#about to write, iclass 10, count 0 2006.257.16:31:34.10#ibcon#wrote, iclass 10, count 0 2006.257.16:31:34.10#ibcon#about to read 3, iclass 10, count 0 2006.257.16:31:34.13#ibcon#read 3, iclass 10, count 0 2006.257.16:31:34.13#ibcon#about to read 4, iclass 10, count 0 2006.257.16:31:34.13#ibcon#read 4, iclass 10, count 0 2006.257.16:31:34.13#ibcon#about to read 5, iclass 10, count 0 2006.257.16:31:34.13#ibcon#read 5, iclass 10, count 0 2006.257.16:31:34.13#ibcon#about to read 6, iclass 10, count 0 2006.257.16:31:34.13#ibcon#read 6, iclass 10, count 0 2006.257.16:31:34.13#ibcon#end of sib2, iclass 10, count 0 2006.257.16:31:34.13#ibcon#*after write, iclass 10, count 0 2006.257.16:31:34.13#ibcon#*before return 0, iclass 10, count 0 2006.257.16:31:34.13#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:31:34.13#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:31:34.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:31:34.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:31:34.13$vck44/vblo=4,679.99 2006.257.16:31:34.13#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.16:31:34.13#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.16:31:34.13#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:34.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:31:34.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:31:34.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:31:34.13#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:31:34.13#ibcon#first serial, iclass 12, count 0 2006.257.16:31:34.13#ibcon#enter sib2, iclass 12, count 0 2006.257.16:31:34.13#ibcon#flushed, iclass 12, count 0 2006.257.16:31:34.13#ibcon#about to write, iclass 12, count 0 2006.257.16:31:34.13#ibcon#wrote, iclass 12, count 0 2006.257.16:31:34.13#ibcon#about to read 3, iclass 12, count 0 2006.257.16:31:34.15#ibcon#read 3, iclass 12, count 0 2006.257.16:31:34.15#ibcon#about to read 4, iclass 12, count 0 2006.257.16:31:34.15#ibcon#read 4, iclass 12, count 0 2006.257.16:31:34.15#ibcon#about to read 5, iclass 12, count 0 2006.257.16:31:34.15#ibcon#read 5, iclass 12, count 0 2006.257.16:31:34.15#ibcon#about to read 6, iclass 12, count 0 2006.257.16:31:34.15#ibcon#read 6, iclass 12, count 0 2006.257.16:31:34.15#ibcon#end of sib2, iclass 12, count 0 2006.257.16:31:34.15#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:31:34.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:31:34.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.16:31:34.15#ibcon#*before write, iclass 12, count 0 2006.257.16:31:34.15#ibcon#enter sib2, iclass 12, count 0 2006.257.16:31:34.15#ibcon#flushed, iclass 12, count 0 2006.257.16:31:34.15#ibcon#about to write, iclass 12, count 0 2006.257.16:31:34.15#ibcon#wrote, iclass 12, count 0 2006.257.16:31:34.15#ibcon#about to read 3, iclass 12, count 0 2006.257.16:31:34.19#ibcon#read 3, iclass 12, count 0 2006.257.16:31:34.19#ibcon#about to read 4, iclass 12, count 0 2006.257.16:31:34.19#ibcon#read 4, iclass 12, count 0 2006.257.16:31:34.19#ibcon#about to read 5, iclass 12, count 0 2006.257.16:31:34.19#ibcon#read 5, iclass 12, count 0 2006.257.16:31:34.19#ibcon#about to read 6, iclass 12, count 0 2006.257.16:31:34.19#ibcon#read 6, iclass 12, count 0 2006.257.16:31:34.19#ibcon#end of sib2, iclass 12, count 0 2006.257.16:31:34.19#ibcon#*after write, iclass 12, count 0 2006.257.16:31:34.19#ibcon#*before return 0, iclass 12, count 0 2006.257.16:31:34.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:31:34.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:31:34.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:31:34.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:31:34.19$vck44/vb=4,5 2006.257.16:31:34.19#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.16:31:34.19#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.16:31:34.19#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:34.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:31:34.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:31:34.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:31:34.25#ibcon#enter wrdev, iclass 14, count 2 2006.257.16:31:34.25#ibcon#first serial, iclass 14, count 2 2006.257.16:31:34.25#ibcon#enter sib2, iclass 14, count 2 2006.257.16:31:34.25#ibcon#flushed, iclass 14, count 2 2006.257.16:31:34.25#ibcon#about to write, iclass 14, count 2 2006.257.16:31:34.25#ibcon#wrote, iclass 14, count 2 2006.257.16:31:34.25#ibcon#about to read 3, iclass 14, count 2 2006.257.16:31:34.27#ibcon#read 3, iclass 14, count 2 2006.257.16:31:34.27#ibcon#about to read 4, iclass 14, count 2 2006.257.16:31:34.27#ibcon#read 4, iclass 14, count 2 2006.257.16:31:34.27#ibcon#about to read 5, iclass 14, count 2 2006.257.16:31:34.27#ibcon#read 5, iclass 14, count 2 2006.257.16:31:34.27#ibcon#about to read 6, iclass 14, count 2 2006.257.16:31:34.27#ibcon#read 6, iclass 14, count 2 2006.257.16:31:34.27#ibcon#end of sib2, iclass 14, count 2 2006.257.16:31:34.27#ibcon#*mode == 0, iclass 14, count 2 2006.257.16:31:34.27#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.16:31:34.27#ibcon#[27=AT04-05\r\n] 2006.257.16:31:34.27#ibcon#*before write, iclass 14, count 2 2006.257.16:31:34.27#ibcon#enter sib2, iclass 14, count 2 2006.257.16:31:34.27#ibcon#flushed, iclass 14, count 2 2006.257.16:31:34.27#ibcon#about to write, iclass 14, count 2 2006.257.16:31:34.27#ibcon#wrote, iclass 14, count 2 2006.257.16:31:34.27#ibcon#about to read 3, iclass 14, count 2 2006.257.16:31:34.30#ibcon#read 3, iclass 14, count 2 2006.257.16:31:34.30#ibcon#about to read 4, iclass 14, count 2 2006.257.16:31:34.30#ibcon#read 4, iclass 14, count 2 2006.257.16:31:34.30#ibcon#about to read 5, iclass 14, count 2 2006.257.16:31:34.30#ibcon#read 5, iclass 14, count 2 2006.257.16:31:34.30#ibcon#about to read 6, iclass 14, count 2 2006.257.16:31:34.30#ibcon#read 6, iclass 14, count 2 2006.257.16:31:34.30#ibcon#end of sib2, iclass 14, count 2 2006.257.16:31:34.30#ibcon#*after write, iclass 14, count 2 2006.257.16:31:34.30#ibcon#*before return 0, iclass 14, count 2 2006.257.16:31:34.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:31:34.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:31:34.30#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.16:31:34.30#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:34.30#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:31:34.42#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:31:34.42#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:31:34.42#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:31:34.42#ibcon#first serial, iclass 14, count 0 2006.257.16:31:34.42#ibcon#enter sib2, iclass 14, count 0 2006.257.16:31:34.42#ibcon#flushed, iclass 14, count 0 2006.257.16:31:34.42#ibcon#about to write, iclass 14, count 0 2006.257.16:31:34.42#ibcon#wrote, iclass 14, count 0 2006.257.16:31:34.42#ibcon#about to read 3, iclass 14, count 0 2006.257.16:31:34.44#ibcon#read 3, iclass 14, count 0 2006.257.16:31:34.44#ibcon#about to read 4, iclass 14, count 0 2006.257.16:31:34.44#ibcon#read 4, iclass 14, count 0 2006.257.16:31:34.44#ibcon#about to read 5, iclass 14, count 0 2006.257.16:31:34.44#ibcon#read 5, iclass 14, count 0 2006.257.16:31:34.44#ibcon#about to read 6, iclass 14, count 0 2006.257.16:31:34.44#ibcon#read 6, iclass 14, count 0 2006.257.16:31:34.44#ibcon#end of sib2, iclass 14, count 0 2006.257.16:31:34.44#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:31:34.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:31:34.44#ibcon#[27=USB\r\n] 2006.257.16:31:34.44#ibcon#*before write, iclass 14, count 0 2006.257.16:31:34.44#ibcon#enter sib2, iclass 14, count 0 2006.257.16:31:34.44#ibcon#flushed, iclass 14, count 0 2006.257.16:31:34.44#ibcon#about to write, iclass 14, count 0 2006.257.16:31:34.44#ibcon#wrote, iclass 14, count 0 2006.257.16:31:34.44#ibcon#about to read 3, iclass 14, count 0 2006.257.16:31:34.47#ibcon#read 3, iclass 14, count 0 2006.257.16:31:34.47#ibcon#about to read 4, iclass 14, count 0 2006.257.16:31:34.47#ibcon#read 4, iclass 14, count 0 2006.257.16:31:34.47#ibcon#about to read 5, iclass 14, count 0 2006.257.16:31:34.47#ibcon#read 5, iclass 14, count 0 2006.257.16:31:34.47#ibcon#about to read 6, iclass 14, count 0 2006.257.16:31:34.47#ibcon#read 6, iclass 14, count 0 2006.257.16:31:34.47#ibcon#end of sib2, iclass 14, count 0 2006.257.16:31:34.47#ibcon#*after write, iclass 14, count 0 2006.257.16:31:34.47#ibcon#*before return 0, iclass 14, count 0 2006.257.16:31:34.47#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:31:34.47#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:31:34.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:31:34.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:31:34.47$vck44/vblo=5,709.99 2006.257.16:31:34.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.16:31:34.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.16:31:34.47#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:34.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:31:34.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:31:34.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:31:34.47#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:31:34.47#ibcon#first serial, iclass 16, count 0 2006.257.16:31:34.47#ibcon#enter sib2, iclass 16, count 0 2006.257.16:31:34.47#ibcon#flushed, iclass 16, count 0 2006.257.16:31:34.47#ibcon#about to write, iclass 16, count 0 2006.257.16:31:34.47#ibcon#wrote, iclass 16, count 0 2006.257.16:31:34.47#ibcon#about to read 3, iclass 16, count 0 2006.257.16:31:34.49#ibcon#read 3, iclass 16, count 0 2006.257.16:31:34.49#ibcon#about to read 4, iclass 16, count 0 2006.257.16:31:34.49#ibcon#read 4, iclass 16, count 0 2006.257.16:31:34.49#ibcon#about to read 5, iclass 16, count 0 2006.257.16:31:34.49#ibcon#read 5, iclass 16, count 0 2006.257.16:31:34.49#ibcon#about to read 6, iclass 16, count 0 2006.257.16:31:34.49#ibcon#read 6, iclass 16, count 0 2006.257.16:31:34.49#ibcon#end of sib2, iclass 16, count 0 2006.257.16:31:34.49#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:31:34.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:31:34.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:31:34.49#ibcon#*before write, iclass 16, count 0 2006.257.16:31:34.49#ibcon#enter sib2, iclass 16, count 0 2006.257.16:31:34.49#ibcon#flushed, iclass 16, count 0 2006.257.16:31:34.49#ibcon#about to write, iclass 16, count 0 2006.257.16:31:34.49#ibcon#wrote, iclass 16, count 0 2006.257.16:31:34.49#ibcon#about to read 3, iclass 16, count 0 2006.257.16:31:34.53#ibcon#read 3, iclass 16, count 0 2006.257.16:31:34.53#ibcon#about to read 4, iclass 16, count 0 2006.257.16:31:34.53#ibcon#read 4, iclass 16, count 0 2006.257.16:31:34.53#ibcon#about to read 5, iclass 16, count 0 2006.257.16:31:34.53#ibcon#read 5, iclass 16, count 0 2006.257.16:31:34.53#ibcon#about to read 6, iclass 16, count 0 2006.257.16:31:34.53#ibcon#read 6, iclass 16, count 0 2006.257.16:31:34.53#ibcon#end of sib2, iclass 16, count 0 2006.257.16:31:34.53#ibcon#*after write, iclass 16, count 0 2006.257.16:31:34.53#ibcon#*before return 0, iclass 16, count 0 2006.257.16:31:34.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:31:34.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:31:34.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:31:34.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:31:34.53$vck44/vb=5,4 2006.257.16:31:34.53#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.16:31:34.53#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.16:31:34.53#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:34.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:31:34.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:31:34.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:31:34.59#ibcon#enter wrdev, iclass 18, count 2 2006.257.16:31:34.59#ibcon#first serial, iclass 18, count 2 2006.257.16:31:34.59#ibcon#enter sib2, iclass 18, count 2 2006.257.16:31:34.59#ibcon#flushed, iclass 18, count 2 2006.257.16:31:34.59#ibcon#about to write, iclass 18, count 2 2006.257.16:31:34.59#ibcon#wrote, iclass 18, count 2 2006.257.16:31:34.59#ibcon#about to read 3, iclass 18, count 2 2006.257.16:31:34.61#ibcon#read 3, iclass 18, count 2 2006.257.16:31:34.61#ibcon#about to read 4, iclass 18, count 2 2006.257.16:31:34.61#ibcon#read 4, iclass 18, count 2 2006.257.16:31:34.61#ibcon#about to read 5, iclass 18, count 2 2006.257.16:31:34.61#ibcon#read 5, iclass 18, count 2 2006.257.16:31:34.61#ibcon#about to read 6, iclass 18, count 2 2006.257.16:31:34.61#ibcon#read 6, iclass 18, count 2 2006.257.16:31:34.61#ibcon#end of sib2, iclass 18, count 2 2006.257.16:31:34.61#ibcon#*mode == 0, iclass 18, count 2 2006.257.16:31:34.61#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.16:31:34.61#ibcon#[27=AT05-04\r\n] 2006.257.16:31:34.61#ibcon#*before write, iclass 18, count 2 2006.257.16:31:34.61#ibcon#enter sib2, iclass 18, count 2 2006.257.16:31:34.61#ibcon#flushed, iclass 18, count 2 2006.257.16:31:34.61#ibcon#about to write, iclass 18, count 2 2006.257.16:31:34.61#ibcon#wrote, iclass 18, count 2 2006.257.16:31:34.61#ibcon#about to read 3, iclass 18, count 2 2006.257.16:31:34.64#ibcon#read 3, iclass 18, count 2 2006.257.16:31:34.64#ibcon#about to read 4, iclass 18, count 2 2006.257.16:31:34.64#ibcon#read 4, iclass 18, count 2 2006.257.16:31:34.64#ibcon#about to read 5, iclass 18, count 2 2006.257.16:31:34.64#ibcon#read 5, iclass 18, count 2 2006.257.16:31:34.64#ibcon#about to read 6, iclass 18, count 2 2006.257.16:31:34.64#ibcon#read 6, iclass 18, count 2 2006.257.16:31:34.64#ibcon#end of sib2, iclass 18, count 2 2006.257.16:31:34.64#ibcon#*after write, iclass 18, count 2 2006.257.16:31:34.64#ibcon#*before return 0, iclass 18, count 2 2006.257.16:31:34.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:31:34.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:31:34.64#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.16:31:34.64#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:34.64#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:31:34.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:31:34.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:31:34.76#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:31:34.76#ibcon#first serial, iclass 18, count 0 2006.257.16:31:34.76#ibcon#enter sib2, iclass 18, count 0 2006.257.16:31:34.76#ibcon#flushed, iclass 18, count 0 2006.257.16:31:34.76#ibcon#about to write, iclass 18, count 0 2006.257.16:31:34.76#ibcon#wrote, iclass 18, count 0 2006.257.16:31:34.76#ibcon#about to read 3, iclass 18, count 0 2006.257.16:31:34.78#ibcon#read 3, iclass 18, count 0 2006.257.16:31:34.78#ibcon#about to read 4, iclass 18, count 0 2006.257.16:31:34.78#ibcon#read 4, iclass 18, count 0 2006.257.16:31:34.78#ibcon#about to read 5, iclass 18, count 0 2006.257.16:31:34.78#ibcon#read 5, iclass 18, count 0 2006.257.16:31:34.78#ibcon#about to read 6, iclass 18, count 0 2006.257.16:31:34.78#ibcon#read 6, iclass 18, count 0 2006.257.16:31:34.78#ibcon#end of sib2, iclass 18, count 0 2006.257.16:31:34.78#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:31:34.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:31:34.78#ibcon#[27=USB\r\n] 2006.257.16:31:34.78#ibcon#*before write, iclass 18, count 0 2006.257.16:31:34.78#ibcon#enter sib2, iclass 18, count 0 2006.257.16:31:34.78#ibcon#flushed, iclass 18, count 0 2006.257.16:31:34.78#ibcon#about to write, iclass 18, count 0 2006.257.16:31:34.78#ibcon#wrote, iclass 18, count 0 2006.257.16:31:34.78#ibcon#about to read 3, iclass 18, count 0 2006.257.16:31:34.81#ibcon#read 3, iclass 18, count 0 2006.257.16:31:34.81#ibcon#about to read 4, iclass 18, count 0 2006.257.16:31:34.81#ibcon#read 4, iclass 18, count 0 2006.257.16:31:34.81#ibcon#about to read 5, iclass 18, count 0 2006.257.16:31:34.81#ibcon#read 5, iclass 18, count 0 2006.257.16:31:34.81#ibcon#about to read 6, iclass 18, count 0 2006.257.16:31:34.81#ibcon#read 6, iclass 18, count 0 2006.257.16:31:34.81#ibcon#end of sib2, iclass 18, count 0 2006.257.16:31:34.81#ibcon#*after write, iclass 18, count 0 2006.257.16:31:34.81#ibcon#*before return 0, iclass 18, count 0 2006.257.16:31:34.81#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:31:34.81#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:31:34.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:31:34.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:31:34.81$vck44/vblo=6,719.99 2006.257.16:31:34.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.16:31:34.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.16:31:34.81#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:34.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:34.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:34.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:34.81#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:31:34.81#ibcon#first serial, iclass 20, count 0 2006.257.16:31:34.81#ibcon#enter sib2, iclass 20, count 0 2006.257.16:31:34.81#ibcon#flushed, iclass 20, count 0 2006.257.16:31:34.81#ibcon#about to write, iclass 20, count 0 2006.257.16:31:34.81#ibcon#wrote, iclass 20, count 0 2006.257.16:31:34.81#ibcon#about to read 3, iclass 20, count 0 2006.257.16:31:34.83#ibcon#read 3, iclass 20, count 0 2006.257.16:31:34.83#ibcon#about to read 4, iclass 20, count 0 2006.257.16:31:34.83#ibcon#read 4, iclass 20, count 0 2006.257.16:31:34.83#ibcon#about to read 5, iclass 20, count 0 2006.257.16:31:34.83#ibcon#read 5, iclass 20, count 0 2006.257.16:31:34.83#ibcon#about to read 6, iclass 20, count 0 2006.257.16:31:34.83#ibcon#read 6, iclass 20, count 0 2006.257.16:31:34.83#ibcon#end of sib2, iclass 20, count 0 2006.257.16:31:34.83#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:31:34.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:31:34.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:31:34.83#ibcon#*before write, iclass 20, count 0 2006.257.16:31:34.83#ibcon#enter sib2, iclass 20, count 0 2006.257.16:31:34.83#ibcon#flushed, iclass 20, count 0 2006.257.16:31:34.83#ibcon#about to write, iclass 20, count 0 2006.257.16:31:34.83#ibcon#wrote, iclass 20, count 0 2006.257.16:31:34.83#ibcon#about to read 3, iclass 20, count 0 2006.257.16:31:34.87#ibcon#read 3, iclass 20, count 0 2006.257.16:31:34.87#ibcon#about to read 4, iclass 20, count 0 2006.257.16:31:34.87#ibcon#read 4, iclass 20, count 0 2006.257.16:31:34.87#ibcon#about to read 5, iclass 20, count 0 2006.257.16:31:34.87#ibcon#read 5, iclass 20, count 0 2006.257.16:31:34.87#ibcon#about to read 6, iclass 20, count 0 2006.257.16:31:34.87#ibcon#read 6, iclass 20, count 0 2006.257.16:31:34.87#ibcon#end of sib2, iclass 20, count 0 2006.257.16:31:34.87#ibcon#*after write, iclass 20, count 0 2006.257.16:31:34.87#ibcon#*before return 0, iclass 20, count 0 2006.257.16:31:34.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:34.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:31:34.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:31:34.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:31:34.87$vck44/vb=6,4 2006.257.16:31:34.87#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.16:31:34.87#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.16:31:34.87#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:34.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:34.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:34.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:34.93#ibcon#enter wrdev, iclass 22, count 2 2006.257.16:31:34.93#ibcon#first serial, iclass 22, count 2 2006.257.16:31:34.93#ibcon#enter sib2, iclass 22, count 2 2006.257.16:31:34.93#ibcon#flushed, iclass 22, count 2 2006.257.16:31:34.93#ibcon#about to write, iclass 22, count 2 2006.257.16:31:34.93#ibcon#wrote, iclass 22, count 2 2006.257.16:31:34.93#ibcon#about to read 3, iclass 22, count 2 2006.257.16:31:34.95#ibcon#read 3, iclass 22, count 2 2006.257.16:31:34.95#ibcon#about to read 4, iclass 22, count 2 2006.257.16:31:34.95#ibcon#read 4, iclass 22, count 2 2006.257.16:31:34.95#ibcon#about to read 5, iclass 22, count 2 2006.257.16:31:34.95#ibcon#read 5, iclass 22, count 2 2006.257.16:31:34.95#ibcon#about to read 6, iclass 22, count 2 2006.257.16:31:34.95#ibcon#read 6, iclass 22, count 2 2006.257.16:31:34.95#ibcon#end of sib2, iclass 22, count 2 2006.257.16:31:34.95#ibcon#*mode == 0, iclass 22, count 2 2006.257.16:31:34.95#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.16:31:34.95#ibcon#[27=AT06-04\r\n] 2006.257.16:31:34.95#ibcon#*before write, iclass 22, count 2 2006.257.16:31:34.95#ibcon#enter sib2, iclass 22, count 2 2006.257.16:31:34.95#ibcon#flushed, iclass 22, count 2 2006.257.16:31:34.95#ibcon#about to write, iclass 22, count 2 2006.257.16:31:34.95#ibcon#wrote, iclass 22, count 2 2006.257.16:31:34.95#ibcon#about to read 3, iclass 22, count 2 2006.257.16:31:34.98#ibcon#read 3, iclass 22, count 2 2006.257.16:31:34.98#ibcon#about to read 4, iclass 22, count 2 2006.257.16:31:34.98#ibcon#read 4, iclass 22, count 2 2006.257.16:31:34.98#ibcon#about to read 5, iclass 22, count 2 2006.257.16:31:34.98#ibcon#read 5, iclass 22, count 2 2006.257.16:31:34.98#ibcon#about to read 6, iclass 22, count 2 2006.257.16:31:34.98#ibcon#read 6, iclass 22, count 2 2006.257.16:31:34.98#ibcon#end of sib2, iclass 22, count 2 2006.257.16:31:34.98#ibcon#*after write, iclass 22, count 2 2006.257.16:31:34.98#ibcon#*before return 0, iclass 22, count 2 2006.257.16:31:34.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:34.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:31:34.98#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.16:31:34.98#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:34.98#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:35.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:35.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:35.10#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:31:35.10#ibcon#first serial, iclass 22, count 0 2006.257.16:31:35.10#ibcon#enter sib2, iclass 22, count 0 2006.257.16:31:35.10#ibcon#flushed, iclass 22, count 0 2006.257.16:31:35.10#ibcon#about to write, iclass 22, count 0 2006.257.16:31:35.10#ibcon#wrote, iclass 22, count 0 2006.257.16:31:35.10#ibcon#about to read 3, iclass 22, count 0 2006.257.16:31:35.12#ibcon#read 3, iclass 22, count 0 2006.257.16:31:35.12#ibcon#about to read 4, iclass 22, count 0 2006.257.16:31:35.12#ibcon#read 4, iclass 22, count 0 2006.257.16:31:35.12#ibcon#about to read 5, iclass 22, count 0 2006.257.16:31:35.12#ibcon#read 5, iclass 22, count 0 2006.257.16:31:35.12#ibcon#about to read 6, iclass 22, count 0 2006.257.16:31:35.12#ibcon#read 6, iclass 22, count 0 2006.257.16:31:35.12#ibcon#end of sib2, iclass 22, count 0 2006.257.16:31:35.12#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:31:35.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:31:35.12#ibcon#[27=USB\r\n] 2006.257.16:31:35.12#ibcon#*before write, iclass 22, count 0 2006.257.16:31:35.12#ibcon#enter sib2, iclass 22, count 0 2006.257.16:31:35.12#ibcon#flushed, iclass 22, count 0 2006.257.16:31:35.12#ibcon#about to write, iclass 22, count 0 2006.257.16:31:35.12#ibcon#wrote, iclass 22, count 0 2006.257.16:31:35.12#ibcon#about to read 3, iclass 22, count 0 2006.257.16:31:35.15#ibcon#read 3, iclass 22, count 0 2006.257.16:31:35.15#ibcon#about to read 4, iclass 22, count 0 2006.257.16:31:35.15#ibcon#read 4, iclass 22, count 0 2006.257.16:31:35.15#ibcon#about to read 5, iclass 22, count 0 2006.257.16:31:35.15#ibcon#read 5, iclass 22, count 0 2006.257.16:31:35.15#ibcon#about to read 6, iclass 22, count 0 2006.257.16:31:35.15#ibcon#read 6, iclass 22, count 0 2006.257.16:31:35.15#ibcon#end of sib2, iclass 22, count 0 2006.257.16:31:35.15#ibcon#*after write, iclass 22, count 0 2006.257.16:31:35.15#ibcon#*before return 0, iclass 22, count 0 2006.257.16:31:35.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:35.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:31:35.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:31:35.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:31:35.15$vck44/vblo=7,734.99 2006.257.16:31:35.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.16:31:35.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.16:31:35.15#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:35.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:35.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:35.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:35.15#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:31:35.15#ibcon#first serial, iclass 24, count 0 2006.257.16:31:35.15#ibcon#enter sib2, iclass 24, count 0 2006.257.16:31:35.15#ibcon#flushed, iclass 24, count 0 2006.257.16:31:35.15#ibcon#about to write, iclass 24, count 0 2006.257.16:31:35.15#ibcon#wrote, iclass 24, count 0 2006.257.16:31:35.15#ibcon#about to read 3, iclass 24, count 0 2006.257.16:31:35.17#ibcon#read 3, iclass 24, count 0 2006.257.16:31:35.17#ibcon#about to read 4, iclass 24, count 0 2006.257.16:31:35.17#ibcon#read 4, iclass 24, count 0 2006.257.16:31:35.17#ibcon#about to read 5, iclass 24, count 0 2006.257.16:31:35.17#ibcon#read 5, iclass 24, count 0 2006.257.16:31:35.17#ibcon#about to read 6, iclass 24, count 0 2006.257.16:31:35.17#ibcon#read 6, iclass 24, count 0 2006.257.16:31:35.17#ibcon#end of sib2, iclass 24, count 0 2006.257.16:31:35.17#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:31:35.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:31:35.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:31:35.17#ibcon#*before write, iclass 24, count 0 2006.257.16:31:35.17#ibcon#enter sib2, iclass 24, count 0 2006.257.16:31:35.17#ibcon#flushed, iclass 24, count 0 2006.257.16:31:35.17#ibcon#about to write, iclass 24, count 0 2006.257.16:31:35.17#ibcon#wrote, iclass 24, count 0 2006.257.16:31:35.17#ibcon#about to read 3, iclass 24, count 0 2006.257.16:31:35.21#ibcon#read 3, iclass 24, count 0 2006.257.16:31:35.21#ibcon#about to read 4, iclass 24, count 0 2006.257.16:31:35.21#ibcon#read 4, iclass 24, count 0 2006.257.16:31:35.21#ibcon#about to read 5, iclass 24, count 0 2006.257.16:31:35.21#ibcon#read 5, iclass 24, count 0 2006.257.16:31:35.21#ibcon#about to read 6, iclass 24, count 0 2006.257.16:31:35.21#ibcon#read 6, iclass 24, count 0 2006.257.16:31:35.21#ibcon#end of sib2, iclass 24, count 0 2006.257.16:31:35.21#ibcon#*after write, iclass 24, count 0 2006.257.16:31:35.21#ibcon#*before return 0, iclass 24, count 0 2006.257.16:31:35.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:35.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:31:35.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:31:35.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:31:35.21$vck44/vb=7,4 2006.257.16:31:35.21#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.16:31:35.21#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.16:31:35.21#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:35.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:35.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:35.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:35.27#ibcon#enter wrdev, iclass 26, count 2 2006.257.16:31:35.27#ibcon#first serial, iclass 26, count 2 2006.257.16:31:35.27#ibcon#enter sib2, iclass 26, count 2 2006.257.16:31:35.27#ibcon#flushed, iclass 26, count 2 2006.257.16:31:35.27#ibcon#about to write, iclass 26, count 2 2006.257.16:31:35.27#ibcon#wrote, iclass 26, count 2 2006.257.16:31:35.27#ibcon#about to read 3, iclass 26, count 2 2006.257.16:31:35.29#ibcon#read 3, iclass 26, count 2 2006.257.16:31:35.29#ibcon#about to read 4, iclass 26, count 2 2006.257.16:31:35.29#ibcon#read 4, iclass 26, count 2 2006.257.16:31:35.29#ibcon#about to read 5, iclass 26, count 2 2006.257.16:31:35.29#ibcon#read 5, iclass 26, count 2 2006.257.16:31:35.29#ibcon#about to read 6, iclass 26, count 2 2006.257.16:31:35.29#ibcon#read 6, iclass 26, count 2 2006.257.16:31:35.29#ibcon#end of sib2, iclass 26, count 2 2006.257.16:31:35.29#ibcon#*mode == 0, iclass 26, count 2 2006.257.16:31:35.29#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.16:31:35.29#ibcon#[27=AT07-04\r\n] 2006.257.16:31:35.29#ibcon#*before write, iclass 26, count 2 2006.257.16:31:35.29#ibcon#enter sib2, iclass 26, count 2 2006.257.16:31:35.29#ibcon#flushed, iclass 26, count 2 2006.257.16:31:35.29#ibcon#about to write, iclass 26, count 2 2006.257.16:31:35.29#ibcon#wrote, iclass 26, count 2 2006.257.16:31:35.29#ibcon#about to read 3, iclass 26, count 2 2006.257.16:31:35.32#ibcon#read 3, iclass 26, count 2 2006.257.16:31:35.32#ibcon#about to read 4, iclass 26, count 2 2006.257.16:31:35.32#ibcon#read 4, iclass 26, count 2 2006.257.16:31:35.32#ibcon#about to read 5, iclass 26, count 2 2006.257.16:31:35.32#ibcon#read 5, iclass 26, count 2 2006.257.16:31:35.32#ibcon#about to read 6, iclass 26, count 2 2006.257.16:31:35.32#ibcon#read 6, iclass 26, count 2 2006.257.16:31:35.32#ibcon#end of sib2, iclass 26, count 2 2006.257.16:31:35.32#ibcon#*after write, iclass 26, count 2 2006.257.16:31:35.32#ibcon#*before return 0, iclass 26, count 2 2006.257.16:31:35.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:35.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:31:35.32#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.16:31:35.32#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:35.32#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:35.44#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:35.44#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:35.44#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:31:35.44#ibcon#first serial, iclass 26, count 0 2006.257.16:31:35.44#ibcon#enter sib2, iclass 26, count 0 2006.257.16:31:35.44#ibcon#flushed, iclass 26, count 0 2006.257.16:31:35.44#ibcon#about to write, iclass 26, count 0 2006.257.16:31:35.44#ibcon#wrote, iclass 26, count 0 2006.257.16:31:35.44#ibcon#about to read 3, iclass 26, count 0 2006.257.16:31:35.46#ibcon#read 3, iclass 26, count 0 2006.257.16:31:35.46#ibcon#about to read 4, iclass 26, count 0 2006.257.16:31:35.46#ibcon#read 4, iclass 26, count 0 2006.257.16:31:35.46#ibcon#about to read 5, iclass 26, count 0 2006.257.16:31:35.46#ibcon#read 5, iclass 26, count 0 2006.257.16:31:35.46#ibcon#about to read 6, iclass 26, count 0 2006.257.16:31:35.46#ibcon#read 6, iclass 26, count 0 2006.257.16:31:35.46#ibcon#end of sib2, iclass 26, count 0 2006.257.16:31:35.46#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:31:35.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:31:35.46#ibcon#[27=USB\r\n] 2006.257.16:31:35.46#ibcon#*before write, iclass 26, count 0 2006.257.16:31:35.46#ibcon#enter sib2, iclass 26, count 0 2006.257.16:31:35.46#ibcon#flushed, iclass 26, count 0 2006.257.16:31:35.46#ibcon#about to write, iclass 26, count 0 2006.257.16:31:35.46#ibcon#wrote, iclass 26, count 0 2006.257.16:31:35.46#ibcon#about to read 3, iclass 26, count 0 2006.257.16:31:35.49#ibcon#read 3, iclass 26, count 0 2006.257.16:31:35.49#ibcon#about to read 4, iclass 26, count 0 2006.257.16:31:35.49#ibcon#read 4, iclass 26, count 0 2006.257.16:31:35.49#ibcon#about to read 5, iclass 26, count 0 2006.257.16:31:35.49#ibcon#read 5, iclass 26, count 0 2006.257.16:31:35.49#ibcon#about to read 6, iclass 26, count 0 2006.257.16:31:35.49#ibcon#read 6, iclass 26, count 0 2006.257.16:31:35.49#ibcon#end of sib2, iclass 26, count 0 2006.257.16:31:35.49#ibcon#*after write, iclass 26, count 0 2006.257.16:31:35.49#ibcon#*before return 0, iclass 26, count 0 2006.257.16:31:35.49#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:35.49#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:31:35.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:31:35.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:31:35.49$vck44/vblo=8,744.99 2006.257.16:31:35.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.16:31:35.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.16:31:35.49#ibcon#ireg 17 cls_cnt 0 2006.257.16:31:35.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:35.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:35.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:35.49#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:31:35.49#ibcon#first serial, iclass 28, count 0 2006.257.16:31:35.49#ibcon#enter sib2, iclass 28, count 0 2006.257.16:31:35.49#ibcon#flushed, iclass 28, count 0 2006.257.16:31:35.49#ibcon#about to write, iclass 28, count 0 2006.257.16:31:35.49#ibcon#wrote, iclass 28, count 0 2006.257.16:31:35.49#ibcon#about to read 3, iclass 28, count 0 2006.257.16:31:35.51#ibcon#read 3, iclass 28, count 0 2006.257.16:31:35.51#ibcon#about to read 4, iclass 28, count 0 2006.257.16:31:35.51#ibcon#read 4, iclass 28, count 0 2006.257.16:31:35.51#ibcon#about to read 5, iclass 28, count 0 2006.257.16:31:35.51#ibcon#read 5, iclass 28, count 0 2006.257.16:31:35.51#ibcon#about to read 6, iclass 28, count 0 2006.257.16:31:35.51#ibcon#read 6, iclass 28, count 0 2006.257.16:31:35.51#ibcon#end of sib2, iclass 28, count 0 2006.257.16:31:35.51#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:31:35.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:31:35.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:31:35.51#ibcon#*before write, iclass 28, count 0 2006.257.16:31:35.51#ibcon#enter sib2, iclass 28, count 0 2006.257.16:31:35.51#ibcon#flushed, iclass 28, count 0 2006.257.16:31:35.51#ibcon#about to write, iclass 28, count 0 2006.257.16:31:35.51#ibcon#wrote, iclass 28, count 0 2006.257.16:31:35.51#ibcon#about to read 3, iclass 28, count 0 2006.257.16:31:35.55#ibcon#read 3, iclass 28, count 0 2006.257.16:31:35.55#ibcon#about to read 4, iclass 28, count 0 2006.257.16:31:35.55#ibcon#read 4, iclass 28, count 0 2006.257.16:31:35.55#ibcon#about to read 5, iclass 28, count 0 2006.257.16:31:35.55#ibcon#read 5, iclass 28, count 0 2006.257.16:31:35.55#ibcon#about to read 6, iclass 28, count 0 2006.257.16:31:35.55#ibcon#read 6, iclass 28, count 0 2006.257.16:31:35.55#ibcon#end of sib2, iclass 28, count 0 2006.257.16:31:35.55#ibcon#*after write, iclass 28, count 0 2006.257.16:31:35.55#ibcon#*before return 0, iclass 28, count 0 2006.257.16:31:35.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:35.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:31:35.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:31:35.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:31:35.55$vck44/vb=8,4 2006.257.16:31:35.55#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.16:31:35.55#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.16:31:35.55#ibcon#ireg 11 cls_cnt 2 2006.257.16:31:35.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:35.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:35.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:35.61#ibcon#enter wrdev, iclass 30, count 2 2006.257.16:31:35.61#ibcon#first serial, iclass 30, count 2 2006.257.16:31:35.61#ibcon#enter sib2, iclass 30, count 2 2006.257.16:31:35.61#ibcon#flushed, iclass 30, count 2 2006.257.16:31:35.61#ibcon#about to write, iclass 30, count 2 2006.257.16:31:35.61#ibcon#wrote, iclass 30, count 2 2006.257.16:31:35.61#ibcon#about to read 3, iclass 30, count 2 2006.257.16:31:35.63#ibcon#read 3, iclass 30, count 2 2006.257.16:31:35.63#ibcon#about to read 4, iclass 30, count 2 2006.257.16:31:35.63#ibcon#read 4, iclass 30, count 2 2006.257.16:31:35.63#ibcon#about to read 5, iclass 30, count 2 2006.257.16:31:35.63#ibcon#read 5, iclass 30, count 2 2006.257.16:31:35.63#ibcon#about to read 6, iclass 30, count 2 2006.257.16:31:35.63#ibcon#read 6, iclass 30, count 2 2006.257.16:31:35.63#ibcon#end of sib2, iclass 30, count 2 2006.257.16:31:35.63#ibcon#*mode == 0, iclass 30, count 2 2006.257.16:31:35.63#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.16:31:35.63#ibcon#[27=AT08-04\r\n] 2006.257.16:31:35.63#ibcon#*before write, iclass 30, count 2 2006.257.16:31:35.63#ibcon#enter sib2, iclass 30, count 2 2006.257.16:31:35.63#ibcon#flushed, iclass 30, count 2 2006.257.16:31:35.63#ibcon#about to write, iclass 30, count 2 2006.257.16:31:35.63#ibcon#wrote, iclass 30, count 2 2006.257.16:31:35.63#ibcon#about to read 3, iclass 30, count 2 2006.257.16:31:35.66#ibcon#read 3, iclass 30, count 2 2006.257.16:31:35.66#ibcon#about to read 4, iclass 30, count 2 2006.257.16:31:35.66#ibcon#read 4, iclass 30, count 2 2006.257.16:31:35.66#ibcon#about to read 5, iclass 30, count 2 2006.257.16:31:35.66#ibcon#read 5, iclass 30, count 2 2006.257.16:31:35.66#ibcon#about to read 6, iclass 30, count 2 2006.257.16:31:35.66#ibcon#read 6, iclass 30, count 2 2006.257.16:31:35.66#ibcon#end of sib2, iclass 30, count 2 2006.257.16:31:35.66#ibcon#*after write, iclass 30, count 2 2006.257.16:31:35.66#ibcon#*before return 0, iclass 30, count 2 2006.257.16:31:35.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:35.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:31:35.66#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.16:31:35.66#ibcon#ireg 7 cls_cnt 0 2006.257.16:31:35.66#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:35.78#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:35.78#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:35.78#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:31:35.78#ibcon#first serial, iclass 30, count 0 2006.257.16:31:35.78#ibcon#enter sib2, iclass 30, count 0 2006.257.16:31:35.78#ibcon#flushed, iclass 30, count 0 2006.257.16:31:35.78#ibcon#about to write, iclass 30, count 0 2006.257.16:31:35.78#ibcon#wrote, iclass 30, count 0 2006.257.16:31:35.78#ibcon#about to read 3, iclass 30, count 0 2006.257.16:31:35.80#ibcon#read 3, iclass 30, count 0 2006.257.16:31:35.80#ibcon#about to read 4, iclass 30, count 0 2006.257.16:31:35.80#ibcon#read 4, iclass 30, count 0 2006.257.16:31:35.80#ibcon#about to read 5, iclass 30, count 0 2006.257.16:31:35.80#ibcon#read 5, iclass 30, count 0 2006.257.16:31:35.80#ibcon#about to read 6, iclass 30, count 0 2006.257.16:31:35.80#ibcon#read 6, iclass 30, count 0 2006.257.16:31:35.80#ibcon#end of sib2, iclass 30, count 0 2006.257.16:31:35.80#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:31:35.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:31:35.80#ibcon#[27=USB\r\n] 2006.257.16:31:35.80#ibcon#*before write, iclass 30, count 0 2006.257.16:31:35.80#ibcon#enter sib2, iclass 30, count 0 2006.257.16:31:35.80#ibcon#flushed, iclass 30, count 0 2006.257.16:31:35.80#ibcon#about to write, iclass 30, count 0 2006.257.16:31:35.80#ibcon#wrote, iclass 30, count 0 2006.257.16:31:35.80#ibcon#about to read 3, iclass 30, count 0 2006.257.16:31:35.83#ibcon#read 3, iclass 30, count 0 2006.257.16:31:35.83#ibcon#about to read 4, iclass 30, count 0 2006.257.16:31:35.83#ibcon#read 4, iclass 30, count 0 2006.257.16:31:35.83#ibcon#about to read 5, iclass 30, count 0 2006.257.16:31:35.83#ibcon#read 5, iclass 30, count 0 2006.257.16:31:35.83#ibcon#about to read 6, iclass 30, count 0 2006.257.16:31:35.83#ibcon#read 6, iclass 30, count 0 2006.257.16:31:35.83#ibcon#end of sib2, iclass 30, count 0 2006.257.16:31:35.83#ibcon#*after write, iclass 30, count 0 2006.257.16:31:35.83#ibcon#*before return 0, iclass 30, count 0 2006.257.16:31:35.83#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:35.83#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:31:35.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:31:35.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:31:35.83$vck44/vabw=wide 2006.257.16:31:35.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.16:31:35.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.16:31:35.83#ibcon#ireg 8 cls_cnt 0 2006.257.16:31:35.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:35.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:35.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:35.83#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:31:35.83#ibcon#first serial, iclass 32, count 0 2006.257.16:31:35.83#ibcon#enter sib2, iclass 32, count 0 2006.257.16:31:35.83#ibcon#flushed, iclass 32, count 0 2006.257.16:31:35.83#ibcon#about to write, iclass 32, count 0 2006.257.16:31:35.83#ibcon#wrote, iclass 32, count 0 2006.257.16:31:35.83#ibcon#about to read 3, iclass 32, count 0 2006.257.16:31:35.85#ibcon#read 3, iclass 32, count 0 2006.257.16:31:35.85#ibcon#about to read 4, iclass 32, count 0 2006.257.16:31:35.85#ibcon#read 4, iclass 32, count 0 2006.257.16:31:35.85#ibcon#about to read 5, iclass 32, count 0 2006.257.16:31:35.85#ibcon#read 5, iclass 32, count 0 2006.257.16:31:35.85#ibcon#about to read 6, iclass 32, count 0 2006.257.16:31:35.85#ibcon#read 6, iclass 32, count 0 2006.257.16:31:35.85#ibcon#end of sib2, iclass 32, count 0 2006.257.16:31:35.85#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:31:35.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:31:35.85#ibcon#[25=BW32\r\n] 2006.257.16:31:35.85#ibcon#*before write, iclass 32, count 0 2006.257.16:31:35.85#ibcon#enter sib2, iclass 32, count 0 2006.257.16:31:35.85#ibcon#flushed, iclass 32, count 0 2006.257.16:31:35.85#ibcon#about to write, iclass 32, count 0 2006.257.16:31:35.85#ibcon#wrote, iclass 32, count 0 2006.257.16:31:35.85#ibcon#about to read 3, iclass 32, count 0 2006.257.16:31:35.88#ibcon#read 3, iclass 32, count 0 2006.257.16:31:35.88#ibcon#about to read 4, iclass 32, count 0 2006.257.16:31:35.88#ibcon#read 4, iclass 32, count 0 2006.257.16:31:35.88#ibcon#about to read 5, iclass 32, count 0 2006.257.16:31:35.88#ibcon#read 5, iclass 32, count 0 2006.257.16:31:35.88#ibcon#about to read 6, iclass 32, count 0 2006.257.16:31:35.88#ibcon#read 6, iclass 32, count 0 2006.257.16:31:35.88#ibcon#end of sib2, iclass 32, count 0 2006.257.16:31:35.88#ibcon#*after write, iclass 32, count 0 2006.257.16:31:35.88#ibcon#*before return 0, iclass 32, count 0 2006.257.16:31:35.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:35.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:31:35.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:31:35.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:31:35.88$vck44/vbbw=wide 2006.257.16:31:35.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.16:31:35.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.16:31:35.88#ibcon#ireg 8 cls_cnt 0 2006.257.16:31:35.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:31:35.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:31:35.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:31:35.95#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:31:35.95#ibcon#first serial, iclass 34, count 0 2006.257.16:31:35.95#ibcon#enter sib2, iclass 34, count 0 2006.257.16:31:35.95#ibcon#flushed, iclass 34, count 0 2006.257.16:31:35.95#ibcon#about to write, iclass 34, count 0 2006.257.16:31:35.95#ibcon#wrote, iclass 34, count 0 2006.257.16:31:35.95#ibcon#about to read 3, iclass 34, count 0 2006.257.16:31:35.97#ibcon#read 3, iclass 34, count 0 2006.257.16:31:35.97#ibcon#about to read 4, iclass 34, count 0 2006.257.16:31:35.97#ibcon#read 4, iclass 34, count 0 2006.257.16:31:35.97#ibcon#about to read 5, iclass 34, count 0 2006.257.16:31:35.97#ibcon#read 5, iclass 34, count 0 2006.257.16:31:35.97#ibcon#about to read 6, iclass 34, count 0 2006.257.16:31:35.97#ibcon#read 6, iclass 34, count 0 2006.257.16:31:35.97#ibcon#end of sib2, iclass 34, count 0 2006.257.16:31:35.97#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:31:35.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:31:35.97#ibcon#[27=BW32\r\n] 2006.257.16:31:35.97#ibcon#*before write, iclass 34, count 0 2006.257.16:31:35.97#ibcon#enter sib2, iclass 34, count 0 2006.257.16:31:35.97#ibcon#flushed, iclass 34, count 0 2006.257.16:31:35.97#ibcon#about to write, iclass 34, count 0 2006.257.16:31:35.97#ibcon#wrote, iclass 34, count 0 2006.257.16:31:35.97#ibcon#about to read 3, iclass 34, count 0 2006.257.16:31:36.00#ibcon#read 3, iclass 34, count 0 2006.257.16:31:36.00#ibcon#about to read 4, iclass 34, count 0 2006.257.16:31:36.00#ibcon#read 4, iclass 34, count 0 2006.257.16:31:36.00#ibcon#about to read 5, iclass 34, count 0 2006.257.16:31:36.00#ibcon#read 5, iclass 34, count 0 2006.257.16:31:36.00#ibcon#about to read 6, iclass 34, count 0 2006.257.16:31:36.00#ibcon#read 6, iclass 34, count 0 2006.257.16:31:36.00#ibcon#end of sib2, iclass 34, count 0 2006.257.16:31:36.00#ibcon#*after write, iclass 34, count 0 2006.257.16:31:36.00#ibcon#*before return 0, iclass 34, count 0 2006.257.16:31:36.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:31:36.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:31:36.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:31:36.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:31:36.00$setupk4/ifdk4 2006.257.16:31:36.00$ifdk4/lo= 2006.257.16:31:36.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:31:36.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:31:36.00$ifdk4/patch= 2006.257.16:31:36.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:31:36.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:31:36.00$setupk4/!*+20s 2006.257.16:31:41.73#abcon#<5=/14 1.1 2.9 17.12 981014.1\r\n> 2006.257.16:31:41.75#abcon#{5=INTERFACE CLEAR} 2006.257.16:31:41.81#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:31:50.51$setupk4/"tpicd 2006.257.16:31:50.51$setupk4/echo=off 2006.257.16:31:50.51$setupk4/xlog=off 2006.257.16:31:50.51:!2006.257.16:33:48 2006.257.16:31:52.14#trakl#Source acquired 2006.257.16:31:53.14#flagr#flagr/antenna,acquired 2006.257.16:33:48.00:preob 2006.257.16:33:48.14/onsource/TRACKING 2006.257.16:33:48.14:!2006.257.16:33:58 2006.257.16:33:58.00:"tape 2006.257.16:33:58.00:"st=record 2006.257.16:33:58.00:data_valid=on 2006.257.16:33:58.00:midob 2006.257.16:33:59.14/onsource/TRACKING 2006.257.16:33:59.14/wx/17.14,1014.1,98 2006.257.16:33:59.27/cable/+6.4821E-03 2006.257.16:34:00.36/va/01,08,usb,yes,31,34 2006.257.16:34:00.36/va/02,07,usb,yes,34,35 2006.257.16:34:00.36/va/03,08,usb,yes,31,32 2006.257.16:34:00.36/va/04,07,usb,yes,35,37 2006.257.16:34:00.36/va/05,04,usb,yes,31,32 2006.257.16:34:00.36/va/06,04,usb,yes,35,35 2006.257.16:34:00.36/va/07,04,usb,yes,36,36 2006.257.16:34:00.36/va/08,04,usb,yes,30,37 2006.257.16:34:00.59/valo/01,524.99,yes,locked 2006.257.16:34:00.59/valo/02,534.99,yes,locked 2006.257.16:34:00.59/valo/03,564.99,yes,locked 2006.257.16:34:00.59/valo/04,624.99,yes,locked 2006.257.16:34:00.59/valo/05,734.99,yes,locked 2006.257.16:34:00.59/valo/06,814.99,yes,locked 2006.257.16:34:00.59/valo/07,864.99,yes,locked 2006.257.16:34:00.59/valo/08,884.99,yes,locked 2006.257.16:34:01.68/vb/01,04,usb,yes,31,29 2006.257.16:34:01.68/vb/02,05,usb,yes,30,30 2006.257.16:34:01.68/vb/03,04,usb,yes,31,34 2006.257.16:34:01.68/vb/04,05,usb,yes,31,30 2006.257.16:34:01.68/vb/05,04,usb,yes,27,30 2006.257.16:34:01.68/vb/06,04,usb,yes,32,28 2006.257.16:34:01.68/vb/07,04,usb,yes,32,32 2006.257.16:34:01.68/vb/08,04,usb,yes,29,33 2006.257.16:34:01.92/vblo/01,629.99,yes,locked 2006.257.16:34:01.92/vblo/02,634.99,yes,locked 2006.257.16:34:01.92/vblo/03,649.99,yes,locked 2006.257.16:34:01.92/vblo/04,679.99,yes,locked 2006.257.16:34:01.92/vblo/05,709.99,yes,locked 2006.257.16:34:01.92/vblo/06,719.99,yes,locked 2006.257.16:34:01.92/vblo/07,734.99,yes,locked 2006.257.16:34:01.92/vblo/08,744.99,yes,locked 2006.257.16:34:02.07/vabw/8 2006.257.16:34:02.22/vbbw/8 2006.257.16:34:02.31/xfe/off,on,15.0 2006.257.16:34:02.69/ifatt/23,28,28,28 2006.257.16:34:03.07/fmout-gps/S +4.61E-07 2006.257.16:34:03.11:!2006.257.16:37:48 2006.257.16:37:48.01:data_valid=off 2006.257.16:37:48.01:"et 2006.257.16:37:48.01:!+3s 2006.257.16:37:51.02:"tape 2006.257.16:37:51.02:postob 2006.257.16:37:51.12/cable/+6.4834E-03 2006.257.16:37:51.12/wx/17.20,1014.2,97 2006.257.16:37:51.18/fmout-gps/S +4.59E-07 2006.257.16:37:51.18:scan_name=257-1643,jd0609,110 2006.257.16:37:51.18:source=0528+134,053056.42,133155.1,2000.0,cw 2006.257.16:37:52.13#flagr#flagr/antenna,new-source 2006.257.16:37:52.13:checkk5 2006.257.16:37:52.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.16:37:52.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.16:37:53.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.16:37:53.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.16:37:53.84/chk_obsdata//k5ts1/T2571633??a.dat file size is correct (nominal:920MB, actual:920MB). 2006.257.16:37:54.17/chk_obsdata//k5ts2/T2571633??b.dat file size is correct (nominal:920MB, actual:920MB). 2006.257.16:37:54.51/chk_obsdata//k5ts3/T2571633??c.dat file size is correct (nominal:920MB, actual:920MB). 2006.257.16:37:54.84/chk_obsdata//k5ts4/T2571633??d.dat file size is correct (nominal:920MB, actual:920MB). 2006.257.16:37:55.49/k5log//k5ts1_log_newline 2006.257.16:37:56.14/k5log//k5ts2_log_newline 2006.257.16:37:56.81/k5log//k5ts3_log_newline 2006.257.16:37:57.46/k5log//k5ts4_log_newline 2006.257.16:37:57.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.16:37:57.48:setupk4=1 2006.257.16:37:57.48$setupk4/echo=on 2006.257.16:37:57.48$setupk4/pcalon 2006.257.16:37:57.48$pcalon/"no phase cal control is implemented here 2006.257.16:37:57.48$setupk4/"tpicd=stop 2006.257.16:37:57.48$setupk4/"rec=synch_on 2006.257.16:37:57.48$setupk4/"rec_mode=128 2006.257.16:37:57.48$setupk4/!* 2006.257.16:37:57.48$setupk4/recpk4 2006.257.16:37:57.48$recpk4/recpatch= 2006.257.16:37:57.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.16:37:57.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.16:37:57.48$setupk4/vck44 2006.257.16:37:57.48$vck44/valo=1,524.99 2006.257.16:37:57.48#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.16:37:57.48#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.16:37:57.48#ibcon#ireg 17 cls_cnt 0 2006.257.16:37:57.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:37:57.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:37:57.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:37:57.48#ibcon#enter wrdev, iclass 5, count 0 2006.257.16:37:57.48#ibcon#first serial, iclass 5, count 0 2006.257.16:37:57.48#ibcon#enter sib2, iclass 5, count 0 2006.257.16:37:57.48#ibcon#flushed, iclass 5, count 0 2006.257.16:37:57.48#ibcon#about to write, iclass 5, count 0 2006.257.16:37:57.48#ibcon#wrote, iclass 5, count 0 2006.257.16:37:57.48#ibcon#about to read 3, iclass 5, count 0 2006.257.16:37:57.50#ibcon#read 3, iclass 5, count 0 2006.257.16:37:57.50#ibcon#about to read 4, iclass 5, count 0 2006.257.16:37:57.50#ibcon#read 4, iclass 5, count 0 2006.257.16:37:57.50#ibcon#about to read 5, iclass 5, count 0 2006.257.16:37:57.50#ibcon#read 5, iclass 5, count 0 2006.257.16:37:57.50#ibcon#about to read 6, iclass 5, count 0 2006.257.16:37:57.50#ibcon#read 6, iclass 5, count 0 2006.257.16:37:57.50#ibcon#end of sib2, iclass 5, count 0 2006.257.16:37:57.50#ibcon#*mode == 0, iclass 5, count 0 2006.257.16:37:57.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.16:37:57.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.16:37:57.50#ibcon#*before write, iclass 5, count 0 2006.257.16:37:57.50#ibcon#enter sib2, iclass 5, count 0 2006.257.16:37:57.50#ibcon#flushed, iclass 5, count 0 2006.257.16:37:57.50#ibcon#about to write, iclass 5, count 0 2006.257.16:37:57.50#ibcon#wrote, iclass 5, count 0 2006.257.16:37:57.50#ibcon#about to read 3, iclass 5, count 0 2006.257.16:37:57.55#ibcon#read 3, iclass 5, count 0 2006.257.16:37:57.55#ibcon#about to read 4, iclass 5, count 0 2006.257.16:37:57.55#ibcon#read 4, iclass 5, count 0 2006.257.16:37:57.55#ibcon#about to read 5, iclass 5, count 0 2006.257.16:37:57.55#ibcon#read 5, iclass 5, count 0 2006.257.16:37:57.55#ibcon#about to read 6, iclass 5, count 0 2006.257.16:37:57.55#ibcon#read 6, iclass 5, count 0 2006.257.16:37:57.55#ibcon#end of sib2, iclass 5, count 0 2006.257.16:37:57.55#ibcon#*after write, iclass 5, count 0 2006.257.16:37:57.55#ibcon#*before return 0, iclass 5, count 0 2006.257.16:37:57.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:37:57.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:37:57.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.16:37:57.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.16:37:57.55$vck44/va=1,8 2006.257.16:37:57.55#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.16:37:57.55#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.16:37:57.55#ibcon#ireg 11 cls_cnt 2 2006.257.16:37:57.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:37:57.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:37:57.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:37:57.55#ibcon#enter wrdev, iclass 7, count 2 2006.257.16:37:57.55#ibcon#first serial, iclass 7, count 2 2006.257.16:37:57.55#ibcon#enter sib2, iclass 7, count 2 2006.257.16:37:57.55#ibcon#flushed, iclass 7, count 2 2006.257.16:37:57.55#ibcon#about to write, iclass 7, count 2 2006.257.16:37:57.55#ibcon#wrote, iclass 7, count 2 2006.257.16:37:57.55#ibcon#about to read 3, iclass 7, count 2 2006.257.16:37:57.57#ibcon#read 3, iclass 7, count 2 2006.257.16:37:57.57#ibcon#about to read 4, iclass 7, count 2 2006.257.16:37:57.57#ibcon#read 4, iclass 7, count 2 2006.257.16:37:57.57#ibcon#about to read 5, iclass 7, count 2 2006.257.16:37:57.57#ibcon#read 5, iclass 7, count 2 2006.257.16:37:57.57#ibcon#about to read 6, iclass 7, count 2 2006.257.16:37:57.57#ibcon#read 6, iclass 7, count 2 2006.257.16:37:57.57#ibcon#end of sib2, iclass 7, count 2 2006.257.16:37:57.57#ibcon#*mode == 0, iclass 7, count 2 2006.257.16:37:57.57#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.16:37:57.57#ibcon#[25=AT01-08\r\n] 2006.257.16:37:57.57#ibcon#*before write, iclass 7, count 2 2006.257.16:37:57.57#ibcon#enter sib2, iclass 7, count 2 2006.257.16:37:57.57#ibcon#flushed, iclass 7, count 2 2006.257.16:37:57.57#ibcon#about to write, iclass 7, count 2 2006.257.16:37:57.57#ibcon#wrote, iclass 7, count 2 2006.257.16:37:57.57#ibcon#about to read 3, iclass 7, count 2 2006.257.16:37:57.60#ibcon#read 3, iclass 7, count 2 2006.257.16:37:57.60#ibcon#about to read 4, iclass 7, count 2 2006.257.16:37:57.60#ibcon#read 4, iclass 7, count 2 2006.257.16:37:57.60#ibcon#about to read 5, iclass 7, count 2 2006.257.16:37:57.60#ibcon#read 5, iclass 7, count 2 2006.257.16:37:57.60#ibcon#about to read 6, iclass 7, count 2 2006.257.16:37:57.60#ibcon#read 6, iclass 7, count 2 2006.257.16:37:57.60#ibcon#end of sib2, iclass 7, count 2 2006.257.16:37:57.60#ibcon#*after write, iclass 7, count 2 2006.257.16:37:57.60#ibcon#*before return 0, iclass 7, count 2 2006.257.16:37:57.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:37:57.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:37:57.60#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.16:37:57.60#ibcon#ireg 7 cls_cnt 0 2006.257.16:37:57.60#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:37:57.72#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:37:57.72#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:37:57.72#ibcon#enter wrdev, iclass 7, count 0 2006.257.16:37:57.72#ibcon#first serial, iclass 7, count 0 2006.257.16:37:57.72#ibcon#enter sib2, iclass 7, count 0 2006.257.16:37:57.72#ibcon#flushed, iclass 7, count 0 2006.257.16:37:57.72#ibcon#about to write, iclass 7, count 0 2006.257.16:37:57.72#ibcon#wrote, iclass 7, count 0 2006.257.16:37:57.72#ibcon#about to read 3, iclass 7, count 0 2006.257.16:37:57.74#ibcon#read 3, iclass 7, count 0 2006.257.16:37:57.74#ibcon#about to read 4, iclass 7, count 0 2006.257.16:37:57.74#ibcon#read 4, iclass 7, count 0 2006.257.16:37:57.74#ibcon#about to read 5, iclass 7, count 0 2006.257.16:37:57.74#ibcon#read 5, iclass 7, count 0 2006.257.16:37:57.74#ibcon#about to read 6, iclass 7, count 0 2006.257.16:37:57.74#ibcon#read 6, iclass 7, count 0 2006.257.16:37:57.74#ibcon#end of sib2, iclass 7, count 0 2006.257.16:37:57.74#ibcon#*mode == 0, iclass 7, count 0 2006.257.16:37:57.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.16:37:57.74#ibcon#[25=USB\r\n] 2006.257.16:37:57.74#ibcon#*before write, iclass 7, count 0 2006.257.16:37:57.74#ibcon#enter sib2, iclass 7, count 0 2006.257.16:37:57.74#ibcon#flushed, iclass 7, count 0 2006.257.16:37:57.74#ibcon#about to write, iclass 7, count 0 2006.257.16:37:57.74#ibcon#wrote, iclass 7, count 0 2006.257.16:37:57.74#ibcon#about to read 3, iclass 7, count 0 2006.257.16:37:57.77#ibcon#read 3, iclass 7, count 0 2006.257.16:37:57.77#ibcon#about to read 4, iclass 7, count 0 2006.257.16:37:57.77#ibcon#read 4, iclass 7, count 0 2006.257.16:37:57.77#ibcon#about to read 5, iclass 7, count 0 2006.257.16:37:57.77#ibcon#read 5, iclass 7, count 0 2006.257.16:37:57.77#ibcon#about to read 6, iclass 7, count 0 2006.257.16:37:57.77#ibcon#read 6, iclass 7, count 0 2006.257.16:37:57.77#ibcon#end of sib2, iclass 7, count 0 2006.257.16:37:57.77#ibcon#*after write, iclass 7, count 0 2006.257.16:37:57.77#ibcon#*before return 0, iclass 7, count 0 2006.257.16:37:57.77#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:37:57.77#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:37:57.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.16:37:57.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.16:37:57.77$vck44/valo=2,534.99 2006.257.16:37:57.77#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.16:37:57.77#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.16:37:57.77#ibcon#ireg 17 cls_cnt 0 2006.257.16:37:57.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:37:57.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:37:57.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:37:57.77#ibcon#enter wrdev, iclass 11, count 0 2006.257.16:37:57.77#ibcon#first serial, iclass 11, count 0 2006.257.16:37:57.77#ibcon#enter sib2, iclass 11, count 0 2006.257.16:37:57.77#ibcon#flushed, iclass 11, count 0 2006.257.16:37:57.77#ibcon#about to write, iclass 11, count 0 2006.257.16:37:57.77#ibcon#wrote, iclass 11, count 0 2006.257.16:37:57.77#ibcon#about to read 3, iclass 11, count 0 2006.257.16:37:57.79#ibcon#read 3, iclass 11, count 0 2006.257.16:37:57.79#ibcon#about to read 4, iclass 11, count 0 2006.257.16:37:57.79#ibcon#read 4, iclass 11, count 0 2006.257.16:37:57.79#ibcon#about to read 5, iclass 11, count 0 2006.257.16:37:57.79#ibcon#read 5, iclass 11, count 0 2006.257.16:37:57.79#ibcon#about to read 6, iclass 11, count 0 2006.257.16:37:57.79#ibcon#read 6, iclass 11, count 0 2006.257.16:37:57.79#ibcon#end of sib2, iclass 11, count 0 2006.257.16:37:57.79#ibcon#*mode == 0, iclass 11, count 0 2006.257.16:37:57.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.16:37:57.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.16:37:57.79#ibcon#*before write, iclass 11, count 0 2006.257.16:37:57.79#ibcon#enter sib2, iclass 11, count 0 2006.257.16:37:57.79#ibcon#flushed, iclass 11, count 0 2006.257.16:37:57.79#ibcon#about to write, iclass 11, count 0 2006.257.16:37:57.79#ibcon#wrote, iclass 11, count 0 2006.257.16:37:57.79#ibcon#about to read 3, iclass 11, count 0 2006.257.16:37:57.83#ibcon#read 3, iclass 11, count 0 2006.257.16:37:57.83#ibcon#about to read 4, iclass 11, count 0 2006.257.16:37:57.83#ibcon#read 4, iclass 11, count 0 2006.257.16:37:57.83#ibcon#about to read 5, iclass 11, count 0 2006.257.16:37:57.83#ibcon#read 5, iclass 11, count 0 2006.257.16:37:57.83#ibcon#about to read 6, iclass 11, count 0 2006.257.16:37:57.83#ibcon#read 6, iclass 11, count 0 2006.257.16:37:57.83#ibcon#end of sib2, iclass 11, count 0 2006.257.16:37:57.83#ibcon#*after write, iclass 11, count 0 2006.257.16:37:57.83#ibcon#*before return 0, iclass 11, count 0 2006.257.16:37:57.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:37:57.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:37:57.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.16:37:57.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.16:37:57.83$vck44/va=2,7 2006.257.16:37:57.83#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.16:37:57.83#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.16:37:57.83#ibcon#ireg 11 cls_cnt 2 2006.257.16:37:57.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:37:57.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:37:57.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:37:57.89#ibcon#enter wrdev, iclass 13, count 2 2006.257.16:37:57.89#ibcon#first serial, iclass 13, count 2 2006.257.16:37:57.89#ibcon#enter sib2, iclass 13, count 2 2006.257.16:37:57.89#ibcon#flushed, iclass 13, count 2 2006.257.16:37:57.89#ibcon#about to write, iclass 13, count 2 2006.257.16:37:57.89#ibcon#wrote, iclass 13, count 2 2006.257.16:37:57.89#ibcon#about to read 3, iclass 13, count 2 2006.257.16:37:57.91#ibcon#read 3, iclass 13, count 2 2006.257.16:37:57.91#ibcon#about to read 4, iclass 13, count 2 2006.257.16:37:57.91#ibcon#read 4, iclass 13, count 2 2006.257.16:37:57.91#ibcon#about to read 5, iclass 13, count 2 2006.257.16:37:57.91#ibcon#read 5, iclass 13, count 2 2006.257.16:37:57.91#ibcon#about to read 6, iclass 13, count 2 2006.257.16:37:57.91#ibcon#read 6, iclass 13, count 2 2006.257.16:37:57.91#ibcon#end of sib2, iclass 13, count 2 2006.257.16:37:57.91#ibcon#*mode == 0, iclass 13, count 2 2006.257.16:37:57.91#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.16:37:57.91#ibcon#[25=AT02-07\r\n] 2006.257.16:37:57.91#ibcon#*before write, iclass 13, count 2 2006.257.16:37:57.91#ibcon#enter sib2, iclass 13, count 2 2006.257.16:37:57.91#ibcon#flushed, iclass 13, count 2 2006.257.16:37:57.91#ibcon#about to write, iclass 13, count 2 2006.257.16:37:57.91#ibcon#wrote, iclass 13, count 2 2006.257.16:37:57.91#ibcon#about to read 3, iclass 13, count 2 2006.257.16:37:57.94#ibcon#read 3, iclass 13, count 2 2006.257.16:37:57.94#ibcon#about to read 4, iclass 13, count 2 2006.257.16:37:57.94#ibcon#read 4, iclass 13, count 2 2006.257.16:37:57.94#ibcon#about to read 5, iclass 13, count 2 2006.257.16:37:57.94#ibcon#read 5, iclass 13, count 2 2006.257.16:37:57.94#ibcon#about to read 6, iclass 13, count 2 2006.257.16:37:57.94#ibcon#read 6, iclass 13, count 2 2006.257.16:37:57.94#ibcon#end of sib2, iclass 13, count 2 2006.257.16:37:57.94#ibcon#*after write, iclass 13, count 2 2006.257.16:37:57.94#ibcon#*before return 0, iclass 13, count 2 2006.257.16:37:57.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:37:57.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:37:57.94#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.16:37:57.94#ibcon#ireg 7 cls_cnt 0 2006.257.16:37:57.94#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:37:58.06#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:37:58.06#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:37:58.06#ibcon#enter wrdev, iclass 13, count 0 2006.257.16:37:58.06#ibcon#first serial, iclass 13, count 0 2006.257.16:37:58.06#ibcon#enter sib2, iclass 13, count 0 2006.257.16:37:58.06#ibcon#flushed, iclass 13, count 0 2006.257.16:37:58.06#ibcon#about to write, iclass 13, count 0 2006.257.16:37:58.06#ibcon#wrote, iclass 13, count 0 2006.257.16:37:58.06#ibcon#about to read 3, iclass 13, count 0 2006.257.16:37:58.08#ibcon#read 3, iclass 13, count 0 2006.257.16:37:58.08#ibcon#about to read 4, iclass 13, count 0 2006.257.16:37:58.08#ibcon#read 4, iclass 13, count 0 2006.257.16:37:58.08#ibcon#about to read 5, iclass 13, count 0 2006.257.16:37:58.08#ibcon#read 5, iclass 13, count 0 2006.257.16:37:58.08#ibcon#about to read 6, iclass 13, count 0 2006.257.16:37:58.08#ibcon#read 6, iclass 13, count 0 2006.257.16:37:58.08#ibcon#end of sib2, iclass 13, count 0 2006.257.16:37:58.08#ibcon#*mode == 0, iclass 13, count 0 2006.257.16:37:58.08#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.16:37:58.08#ibcon#[25=USB\r\n] 2006.257.16:37:58.08#ibcon#*before write, iclass 13, count 0 2006.257.16:37:58.08#ibcon#enter sib2, iclass 13, count 0 2006.257.16:37:58.08#ibcon#flushed, iclass 13, count 0 2006.257.16:37:58.08#ibcon#about to write, iclass 13, count 0 2006.257.16:37:58.08#ibcon#wrote, iclass 13, count 0 2006.257.16:37:58.08#ibcon#about to read 3, iclass 13, count 0 2006.257.16:37:58.11#abcon#<5=/14 1.8 4.8 17.20 971014.1\r\n> 2006.257.16:37:58.11#ibcon#read 3, iclass 13, count 0 2006.257.16:37:58.11#ibcon#about to read 4, iclass 13, count 0 2006.257.16:37:58.11#ibcon#read 4, iclass 13, count 0 2006.257.16:37:58.11#ibcon#about to read 5, iclass 13, count 0 2006.257.16:37:58.11#ibcon#read 5, iclass 13, count 0 2006.257.16:37:58.11#ibcon#about to read 6, iclass 13, count 0 2006.257.16:37:58.11#ibcon#read 6, iclass 13, count 0 2006.257.16:37:58.11#ibcon#end of sib2, iclass 13, count 0 2006.257.16:37:58.11#ibcon#*after write, iclass 13, count 0 2006.257.16:37:58.11#ibcon#*before return 0, iclass 13, count 0 2006.257.16:37:58.11#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:37:58.11#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:37:58.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.16:37:58.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.16:37:58.11$vck44/valo=3,564.99 2006.257.16:37:58.11#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.16:37:58.11#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.16:37:58.11#ibcon#ireg 17 cls_cnt 0 2006.257.16:37:58.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:37:58.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:37:58.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:37:58.11#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:37:58.11#ibcon#first serial, iclass 18, count 0 2006.257.16:37:58.11#ibcon#enter sib2, iclass 18, count 0 2006.257.16:37:58.11#ibcon#flushed, iclass 18, count 0 2006.257.16:37:58.11#ibcon#about to write, iclass 18, count 0 2006.257.16:37:58.11#ibcon#wrote, iclass 18, count 0 2006.257.16:37:58.11#ibcon#about to read 3, iclass 18, count 0 2006.257.16:37:58.13#abcon#{5=INTERFACE CLEAR} 2006.257.16:37:58.13#ibcon#read 3, iclass 18, count 0 2006.257.16:37:58.13#ibcon#about to read 4, iclass 18, count 0 2006.257.16:37:58.13#ibcon#read 4, iclass 18, count 0 2006.257.16:37:58.13#ibcon#about to read 5, iclass 18, count 0 2006.257.16:37:58.13#ibcon#read 5, iclass 18, count 0 2006.257.16:37:58.13#ibcon#about to read 6, iclass 18, count 0 2006.257.16:37:58.13#ibcon#read 6, iclass 18, count 0 2006.257.16:37:58.13#ibcon#end of sib2, iclass 18, count 0 2006.257.16:37:58.13#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:37:58.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:37:58.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.16:37:58.13#ibcon#*before write, iclass 18, count 0 2006.257.16:37:58.13#ibcon#enter sib2, iclass 18, count 0 2006.257.16:37:58.13#ibcon#flushed, iclass 18, count 0 2006.257.16:37:58.13#ibcon#about to write, iclass 18, count 0 2006.257.16:37:58.13#ibcon#wrote, iclass 18, count 0 2006.257.16:37:58.13#ibcon#about to read 3, iclass 18, count 0 2006.257.16:37:58.17#ibcon#read 3, iclass 18, count 0 2006.257.16:37:58.17#ibcon#about to read 4, iclass 18, count 0 2006.257.16:37:58.17#ibcon#read 4, iclass 18, count 0 2006.257.16:37:58.17#ibcon#about to read 5, iclass 18, count 0 2006.257.16:37:58.17#ibcon#read 5, iclass 18, count 0 2006.257.16:37:58.17#ibcon#about to read 6, iclass 18, count 0 2006.257.16:37:58.17#ibcon#read 6, iclass 18, count 0 2006.257.16:37:58.17#ibcon#end of sib2, iclass 18, count 0 2006.257.16:37:58.17#ibcon#*after write, iclass 18, count 0 2006.257.16:37:58.17#ibcon#*before return 0, iclass 18, count 0 2006.257.16:37:58.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:37:58.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:37:58.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:37:58.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:37:58.17$vck44/va=3,8 2006.257.16:37:58.17#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.16:37:58.17#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.16:37:58.17#ibcon#ireg 11 cls_cnt 2 2006.257.16:37:58.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:37:58.19#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:37:58.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:37:58.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:37:58.23#ibcon#enter wrdev, iclass 20, count 2 2006.257.16:37:58.23#ibcon#first serial, iclass 20, count 2 2006.257.16:37:58.23#ibcon#enter sib2, iclass 20, count 2 2006.257.16:37:58.23#ibcon#flushed, iclass 20, count 2 2006.257.16:37:58.23#ibcon#about to write, iclass 20, count 2 2006.257.16:37:58.23#ibcon#wrote, iclass 20, count 2 2006.257.16:37:58.23#ibcon#about to read 3, iclass 20, count 2 2006.257.16:37:58.25#ibcon#read 3, iclass 20, count 2 2006.257.16:37:58.25#ibcon#about to read 4, iclass 20, count 2 2006.257.16:37:58.25#ibcon#read 4, iclass 20, count 2 2006.257.16:37:58.25#ibcon#about to read 5, iclass 20, count 2 2006.257.16:37:58.25#ibcon#read 5, iclass 20, count 2 2006.257.16:37:58.25#ibcon#about to read 6, iclass 20, count 2 2006.257.16:37:58.25#ibcon#read 6, iclass 20, count 2 2006.257.16:37:58.25#ibcon#end of sib2, iclass 20, count 2 2006.257.16:37:58.25#ibcon#*mode == 0, iclass 20, count 2 2006.257.16:37:58.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.16:37:58.25#ibcon#[25=AT03-08\r\n] 2006.257.16:37:58.25#ibcon#*before write, iclass 20, count 2 2006.257.16:37:58.25#ibcon#enter sib2, iclass 20, count 2 2006.257.16:37:58.25#ibcon#flushed, iclass 20, count 2 2006.257.16:37:58.25#ibcon#about to write, iclass 20, count 2 2006.257.16:37:58.25#ibcon#wrote, iclass 20, count 2 2006.257.16:37:58.25#ibcon#about to read 3, iclass 20, count 2 2006.257.16:37:58.28#ibcon#read 3, iclass 20, count 2 2006.257.16:37:58.28#ibcon#about to read 4, iclass 20, count 2 2006.257.16:37:58.28#ibcon#read 4, iclass 20, count 2 2006.257.16:37:58.28#ibcon#about to read 5, iclass 20, count 2 2006.257.16:37:58.28#ibcon#read 5, iclass 20, count 2 2006.257.16:37:58.28#ibcon#about to read 6, iclass 20, count 2 2006.257.16:37:58.28#ibcon#read 6, iclass 20, count 2 2006.257.16:37:58.28#ibcon#end of sib2, iclass 20, count 2 2006.257.16:37:58.28#ibcon#*after write, iclass 20, count 2 2006.257.16:37:58.28#ibcon#*before return 0, iclass 20, count 2 2006.257.16:37:58.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:37:58.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:37:58.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.16:37:58.28#ibcon#ireg 7 cls_cnt 0 2006.257.16:37:58.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:37:58.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:37:58.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:37:58.40#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:37:58.40#ibcon#first serial, iclass 20, count 0 2006.257.16:37:58.40#ibcon#enter sib2, iclass 20, count 0 2006.257.16:37:58.40#ibcon#flushed, iclass 20, count 0 2006.257.16:37:58.40#ibcon#about to write, iclass 20, count 0 2006.257.16:37:58.40#ibcon#wrote, iclass 20, count 0 2006.257.16:37:58.40#ibcon#about to read 3, iclass 20, count 0 2006.257.16:37:58.42#ibcon#read 3, iclass 20, count 0 2006.257.16:37:58.42#ibcon#about to read 4, iclass 20, count 0 2006.257.16:37:58.42#ibcon#read 4, iclass 20, count 0 2006.257.16:37:58.42#ibcon#about to read 5, iclass 20, count 0 2006.257.16:37:58.42#ibcon#read 5, iclass 20, count 0 2006.257.16:37:58.42#ibcon#about to read 6, iclass 20, count 0 2006.257.16:37:58.42#ibcon#read 6, iclass 20, count 0 2006.257.16:37:58.42#ibcon#end of sib2, iclass 20, count 0 2006.257.16:37:58.42#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:37:58.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:37:58.42#ibcon#[25=USB\r\n] 2006.257.16:37:58.42#ibcon#*before write, iclass 20, count 0 2006.257.16:37:58.42#ibcon#enter sib2, iclass 20, count 0 2006.257.16:37:58.42#ibcon#flushed, iclass 20, count 0 2006.257.16:37:58.42#ibcon#about to write, iclass 20, count 0 2006.257.16:37:58.42#ibcon#wrote, iclass 20, count 0 2006.257.16:37:58.42#ibcon#about to read 3, iclass 20, count 0 2006.257.16:37:58.45#ibcon#read 3, iclass 20, count 0 2006.257.16:37:58.45#ibcon#about to read 4, iclass 20, count 0 2006.257.16:37:58.45#ibcon#read 4, iclass 20, count 0 2006.257.16:37:58.45#ibcon#about to read 5, iclass 20, count 0 2006.257.16:37:58.45#ibcon#read 5, iclass 20, count 0 2006.257.16:37:58.45#ibcon#about to read 6, iclass 20, count 0 2006.257.16:37:58.45#ibcon#read 6, iclass 20, count 0 2006.257.16:37:58.45#ibcon#end of sib2, iclass 20, count 0 2006.257.16:37:58.45#ibcon#*after write, iclass 20, count 0 2006.257.16:37:58.45#ibcon#*before return 0, iclass 20, count 0 2006.257.16:37:58.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:37:58.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:37:58.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:37:58.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:37:58.45$vck44/valo=4,624.99 2006.257.16:37:58.45#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.16:37:58.45#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.16:37:58.45#ibcon#ireg 17 cls_cnt 0 2006.257.16:37:58.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:37:58.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:37:58.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:37:58.45#ibcon#enter wrdev, iclass 23, count 0 2006.257.16:37:58.45#ibcon#first serial, iclass 23, count 0 2006.257.16:37:58.45#ibcon#enter sib2, iclass 23, count 0 2006.257.16:37:58.45#ibcon#flushed, iclass 23, count 0 2006.257.16:37:58.45#ibcon#about to write, iclass 23, count 0 2006.257.16:37:58.45#ibcon#wrote, iclass 23, count 0 2006.257.16:37:58.45#ibcon#about to read 3, iclass 23, count 0 2006.257.16:37:58.47#ibcon#read 3, iclass 23, count 0 2006.257.16:37:58.47#ibcon#about to read 4, iclass 23, count 0 2006.257.16:37:58.47#ibcon#read 4, iclass 23, count 0 2006.257.16:37:58.47#ibcon#about to read 5, iclass 23, count 0 2006.257.16:37:58.47#ibcon#read 5, iclass 23, count 0 2006.257.16:37:58.47#ibcon#about to read 6, iclass 23, count 0 2006.257.16:37:58.47#ibcon#read 6, iclass 23, count 0 2006.257.16:37:58.47#ibcon#end of sib2, iclass 23, count 0 2006.257.16:37:58.47#ibcon#*mode == 0, iclass 23, count 0 2006.257.16:37:58.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.16:37:58.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.16:37:58.47#ibcon#*before write, iclass 23, count 0 2006.257.16:37:58.47#ibcon#enter sib2, iclass 23, count 0 2006.257.16:37:58.47#ibcon#flushed, iclass 23, count 0 2006.257.16:37:58.47#ibcon#about to write, iclass 23, count 0 2006.257.16:37:58.47#ibcon#wrote, iclass 23, count 0 2006.257.16:37:58.47#ibcon#about to read 3, iclass 23, count 0 2006.257.16:37:58.51#ibcon#read 3, iclass 23, count 0 2006.257.16:37:58.51#ibcon#about to read 4, iclass 23, count 0 2006.257.16:37:58.51#ibcon#read 4, iclass 23, count 0 2006.257.16:37:58.51#ibcon#about to read 5, iclass 23, count 0 2006.257.16:37:58.51#ibcon#read 5, iclass 23, count 0 2006.257.16:37:58.51#ibcon#about to read 6, iclass 23, count 0 2006.257.16:37:58.51#ibcon#read 6, iclass 23, count 0 2006.257.16:37:58.51#ibcon#end of sib2, iclass 23, count 0 2006.257.16:37:58.51#ibcon#*after write, iclass 23, count 0 2006.257.16:37:58.51#ibcon#*before return 0, iclass 23, count 0 2006.257.16:37:58.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:37:58.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:37:58.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.16:37:58.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.16:37:58.51$vck44/va=4,7 2006.257.16:37:58.51#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.16:37:58.51#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.16:37:58.51#ibcon#ireg 11 cls_cnt 2 2006.257.16:37:58.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:37:58.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:37:58.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:37:58.57#ibcon#enter wrdev, iclass 25, count 2 2006.257.16:37:58.57#ibcon#first serial, iclass 25, count 2 2006.257.16:37:58.57#ibcon#enter sib2, iclass 25, count 2 2006.257.16:37:58.57#ibcon#flushed, iclass 25, count 2 2006.257.16:37:58.57#ibcon#about to write, iclass 25, count 2 2006.257.16:37:58.57#ibcon#wrote, iclass 25, count 2 2006.257.16:37:58.57#ibcon#about to read 3, iclass 25, count 2 2006.257.16:37:58.59#ibcon#read 3, iclass 25, count 2 2006.257.16:37:58.59#ibcon#about to read 4, iclass 25, count 2 2006.257.16:37:58.59#ibcon#read 4, iclass 25, count 2 2006.257.16:37:58.59#ibcon#about to read 5, iclass 25, count 2 2006.257.16:37:58.59#ibcon#read 5, iclass 25, count 2 2006.257.16:37:58.59#ibcon#about to read 6, iclass 25, count 2 2006.257.16:37:58.59#ibcon#read 6, iclass 25, count 2 2006.257.16:37:58.59#ibcon#end of sib2, iclass 25, count 2 2006.257.16:37:58.59#ibcon#*mode == 0, iclass 25, count 2 2006.257.16:37:58.59#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.16:37:58.59#ibcon#[25=AT04-07\r\n] 2006.257.16:37:58.59#ibcon#*before write, iclass 25, count 2 2006.257.16:37:58.59#ibcon#enter sib2, iclass 25, count 2 2006.257.16:37:58.59#ibcon#flushed, iclass 25, count 2 2006.257.16:37:58.59#ibcon#about to write, iclass 25, count 2 2006.257.16:37:58.59#ibcon#wrote, iclass 25, count 2 2006.257.16:37:58.59#ibcon#about to read 3, iclass 25, count 2 2006.257.16:37:58.62#ibcon#read 3, iclass 25, count 2 2006.257.16:37:58.62#ibcon#about to read 4, iclass 25, count 2 2006.257.16:37:58.62#ibcon#read 4, iclass 25, count 2 2006.257.16:37:58.62#ibcon#about to read 5, iclass 25, count 2 2006.257.16:37:58.62#ibcon#read 5, iclass 25, count 2 2006.257.16:37:58.62#ibcon#about to read 6, iclass 25, count 2 2006.257.16:37:58.62#ibcon#read 6, iclass 25, count 2 2006.257.16:37:58.62#ibcon#end of sib2, iclass 25, count 2 2006.257.16:37:58.62#ibcon#*after write, iclass 25, count 2 2006.257.16:37:58.62#ibcon#*before return 0, iclass 25, count 2 2006.257.16:37:58.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:37:58.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:37:58.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.16:37:58.62#ibcon#ireg 7 cls_cnt 0 2006.257.16:37:58.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:37:58.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:37:58.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:37:58.74#ibcon#enter wrdev, iclass 25, count 0 2006.257.16:37:58.74#ibcon#first serial, iclass 25, count 0 2006.257.16:37:58.74#ibcon#enter sib2, iclass 25, count 0 2006.257.16:37:58.74#ibcon#flushed, iclass 25, count 0 2006.257.16:37:58.74#ibcon#about to write, iclass 25, count 0 2006.257.16:37:58.74#ibcon#wrote, iclass 25, count 0 2006.257.16:37:58.74#ibcon#about to read 3, iclass 25, count 0 2006.257.16:37:58.76#ibcon#read 3, iclass 25, count 0 2006.257.16:37:58.76#ibcon#about to read 4, iclass 25, count 0 2006.257.16:37:58.76#ibcon#read 4, iclass 25, count 0 2006.257.16:37:58.76#ibcon#about to read 5, iclass 25, count 0 2006.257.16:37:58.76#ibcon#read 5, iclass 25, count 0 2006.257.16:37:58.76#ibcon#about to read 6, iclass 25, count 0 2006.257.16:37:58.76#ibcon#read 6, iclass 25, count 0 2006.257.16:37:58.76#ibcon#end of sib2, iclass 25, count 0 2006.257.16:37:58.76#ibcon#*mode == 0, iclass 25, count 0 2006.257.16:37:58.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.16:37:58.76#ibcon#[25=USB\r\n] 2006.257.16:37:58.76#ibcon#*before write, iclass 25, count 0 2006.257.16:37:58.76#ibcon#enter sib2, iclass 25, count 0 2006.257.16:37:58.76#ibcon#flushed, iclass 25, count 0 2006.257.16:37:58.76#ibcon#about to write, iclass 25, count 0 2006.257.16:37:58.76#ibcon#wrote, iclass 25, count 0 2006.257.16:37:58.76#ibcon#about to read 3, iclass 25, count 0 2006.257.16:37:58.79#ibcon#read 3, iclass 25, count 0 2006.257.16:37:58.79#ibcon#about to read 4, iclass 25, count 0 2006.257.16:37:58.79#ibcon#read 4, iclass 25, count 0 2006.257.16:37:58.79#ibcon#about to read 5, iclass 25, count 0 2006.257.16:37:58.79#ibcon#read 5, iclass 25, count 0 2006.257.16:37:58.79#ibcon#about to read 6, iclass 25, count 0 2006.257.16:37:58.79#ibcon#read 6, iclass 25, count 0 2006.257.16:37:58.79#ibcon#end of sib2, iclass 25, count 0 2006.257.16:37:58.79#ibcon#*after write, iclass 25, count 0 2006.257.16:37:58.79#ibcon#*before return 0, iclass 25, count 0 2006.257.16:37:58.79#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:37:58.79#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:37:58.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.16:37:58.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.16:37:58.79$vck44/valo=5,734.99 2006.257.16:37:58.79#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.16:37:58.79#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.16:37:58.79#ibcon#ireg 17 cls_cnt 0 2006.257.16:37:58.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:37:58.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:37:58.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:37:58.79#ibcon#enter wrdev, iclass 27, count 0 2006.257.16:37:58.79#ibcon#first serial, iclass 27, count 0 2006.257.16:37:58.79#ibcon#enter sib2, iclass 27, count 0 2006.257.16:37:58.79#ibcon#flushed, iclass 27, count 0 2006.257.16:37:58.79#ibcon#about to write, iclass 27, count 0 2006.257.16:37:58.79#ibcon#wrote, iclass 27, count 0 2006.257.16:37:58.79#ibcon#about to read 3, iclass 27, count 0 2006.257.16:37:58.81#ibcon#read 3, iclass 27, count 0 2006.257.16:37:58.81#ibcon#about to read 4, iclass 27, count 0 2006.257.16:37:58.81#ibcon#read 4, iclass 27, count 0 2006.257.16:37:58.81#ibcon#about to read 5, iclass 27, count 0 2006.257.16:37:58.81#ibcon#read 5, iclass 27, count 0 2006.257.16:37:58.81#ibcon#about to read 6, iclass 27, count 0 2006.257.16:37:58.81#ibcon#read 6, iclass 27, count 0 2006.257.16:37:58.81#ibcon#end of sib2, iclass 27, count 0 2006.257.16:37:58.81#ibcon#*mode == 0, iclass 27, count 0 2006.257.16:37:58.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.16:37:58.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.16:37:58.81#ibcon#*before write, iclass 27, count 0 2006.257.16:37:58.81#ibcon#enter sib2, iclass 27, count 0 2006.257.16:37:58.81#ibcon#flushed, iclass 27, count 0 2006.257.16:37:58.81#ibcon#about to write, iclass 27, count 0 2006.257.16:37:58.81#ibcon#wrote, iclass 27, count 0 2006.257.16:37:58.81#ibcon#about to read 3, iclass 27, count 0 2006.257.16:37:58.85#ibcon#read 3, iclass 27, count 0 2006.257.16:37:58.85#ibcon#about to read 4, iclass 27, count 0 2006.257.16:37:58.85#ibcon#read 4, iclass 27, count 0 2006.257.16:37:58.85#ibcon#about to read 5, iclass 27, count 0 2006.257.16:37:58.85#ibcon#read 5, iclass 27, count 0 2006.257.16:37:58.85#ibcon#about to read 6, iclass 27, count 0 2006.257.16:37:58.85#ibcon#read 6, iclass 27, count 0 2006.257.16:37:58.85#ibcon#end of sib2, iclass 27, count 0 2006.257.16:37:58.85#ibcon#*after write, iclass 27, count 0 2006.257.16:37:58.85#ibcon#*before return 0, iclass 27, count 0 2006.257.16:37:58.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:37:58.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:37:58.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.16:37:58.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.16:37:58.85$vck44/va=5,4 2006.257.16:37:58.85#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.16:37:58.85#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.16:37:58.85#ibcon#ireg 11 cls_cnt 2 2006.257.16:37:58.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:37:58.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:37:58.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:37:58.91#ibcon#enter wrdev, iclass 29, count 2 2006.257.16:37:58.91#ibcon#first serial, iclass 29, count 2 2006.257.16:37:58.91#ibcon#enter sib2, iclass 29, count 2 2006.257.16:37:58.91#ibcon#flushed, iclass 29, count 2 2006.257.16:37:58.91#ibcon#about to write, iclass 29, count 2 2006.257.16:37:58.91#ibcon#wrote, iclass 29, count 2 2006.257.16:37:58.91#ibcon#about to read 3, iclass 29, count 2 2006.257.16:37:58.93#ibcon#read 3, iclass 29, count 2 2006.257.16:37:58.93#ibcon#about to read 4, iclass 29, count 2 2006.257.16:37:58.93#ibcon#read 4, iclass 29, count 2 2006.257.16:37:58.93#ibcon#about to read 5, iclass 29, count 2 2006.257.16:37:58.93#ibcon#read 5, iclass 29, count 2 2006.257.16:37:58.93#ibcon#about to read 6, iclass 29, count 2 2006.257.16:37:58.93#ibcon#read 6, iclass 29, count 2 2006.257.16:37:58.93#ibcon#end of sib2, iclass 29, count 2 2006.257.16:37:58.93#ibcon#*mode == 0, iclass 29, count 2 2006.257.16:37:58.93#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.16:37:58.93#ibcon#[25=AT05-04\r\n] 2006.257.16:37:58.93#ibcon#*before write, iclass 29, count 2 2006.257.16:37:58.93#ibcon#enter sib2, iclass 29, count 2 2006.257.16:37:58.93#ibcon#flushed, iclass 29, count 2 2006.257.16:37:58.93#ibcon#about to write, iclass 29, count 2 2006.257.16:37:58.93#ibcon#wrote, iclass 29, count 2 2006.257.16:37:58.93#ibcon#about to read 3, iclass 29, count 2 2006.257.16:37:58.96#ibcon#read 3, iclass 29, count 2 2006.257.16:37:58.96#ibcon#about to read 4, iclass 29, count 2 2006.257.16:37:58.96#ibcon#read 4, iclass 29, count 2 2006.257.16:37:58.96#ibcon#about to read 5, iclass 29, count 2 2006.257.16:37:58.96#ibcon#read 5, iclass 29, count 2 2006.257.16:37:58.96#ibcon#about to read 6, iclass 29, count 2 2006.257.16:37:58.96#ibcon#read 6, iclass 29, count 2 2006.257.16:37:58.96#ibcon#end of sib2, iclass 29, count 2 2006.257.16:37:58.96#ibcon#*after write, iclass 29, count 2 2006.257.16:37:58.96#ibcon#*before return 0, iclass 29, count 2 2006.257.16:37:58.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:37:58.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:37:58.96#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.16:37:58.96#ibcon#ireg 7 cls_cnt 0 2006.257.16:37:58.96#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:37:59.08#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:37:59.08#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:37:59.08#ibcon#enter wrdev, iclass 29, count 0 2006.257.16:37:59.08#ibcon#first serial, iclass 29, count 0 2006.257.16:37:59.08#ibcon#enter sib2, iclass 29, count 0 2006.257.16:37:59.08#ibcon#flushed, iclass 29, count 0 2006.257.16:37:59.08#ibcon#about to write, iclass 29, count 0 2006.257.16:37:59.08#ibcon#wrote, iclass 29, count 0 2006.257.16:37:59.08#ibcon#about to read 3, iclass 29, count 0 2006.257.16:37:59.10#ibcon#read 3, iclass 29, count 0 2006.257.16:37:59.10#ibcon#about to read 4, iclass 29, count 0 2006.257.16:37:59.10#ibcon#read 4, iclass 29, count 0 2006.257.16:37:59.10#ibcon#about to read 5, iclass 29, count 0 2006.257.16:37:59.10#ibcon#read 5, iclass 29, count 0 2006.257.16:37:59.10#ibcon#about to read 6, iclass 29, count 0 2006.257.16:37:59.10#ibcon#read 6, iclass 29, count 0 2006.257.16:37:59.10#ibcon#end of sib2, iclass 29, count 0 2006.257.16:37:59.10#ibcon#*mode == 0, iclass 29, count 0 2006.257.16:37:59.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.16:37:59.10#ibcon#[25=USB\r\n] 2006.257.16:37:59.10#ibcon#*before write, iclass 29, count 0 2006.257.16:37:59.10#ibcon#enter sib2, iclass 29, count 0 2006.257.16:37:59.10#ibcon#flushed, iclass 29, count 0 2006.257.16:37:59.10#ibcon#about to write, iclass 29, count 0 2006.257.16:37:59.10#ibcon#wrote, iclass 29, count 0 2006.257.16:37:59.10#ibcon#about to read 3, iclass 29, count 0 2006.257.16:37:59.13#ibcon#read 3, iclass 29, count 0 2006.257.16:37:59.13#ibcon#about to read 4, iclass 29, count 0 2006.257.16:37:59.13#ibcon#read 4, iclass 29, count 0 2006.257.16:37:59.13#ibcon#about to read 5, iclass 29, count 0 2006.257.16:37:59.13#ibcon#read 5, iclass 29, count 0 2006.257.16:37:59.13#ibcon#about to read 6, iclass 29, count 0 2006.257.16:37:59.13#ibcon#read 6, iclass 29, count 0 2006.257.16:37:59.13#ibcon#end of sib2, iclass 29, count 0 2006.257.16:37:59.13#ibcon#*after write, iclass 29, count 0 2006.257.16:37:59.13#ibcon#*before return 0, iclass 29, count 0 2006.257.16:37:59.13#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:37:59.13#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:37:59.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.16:37:59.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.16:37:59.13$vck44/valo=6,814.99 2006.257.16:37:59.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.16:37:59.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.16:37:59.13#ibcon#ireg 17 cls_cnt 0 2006.257.16:37:59.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:37:59.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:37:59.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:37:59.13#ibcon#enter wrdev, iclass 31, count 0 2006.257.16:37:59.13#ibcon#first serial, iclass 31, count 0 2006.257.16:37:59.13#ibcon#enter sib2, iclass 31, count 0 2006.257.16:37:59.13#ibcon#flushed, iclass 31, count 0 2006.257.16:37:59.13#ibcon#about to write, iclass 31, count 0 2006.257.16:37:59.13#ibcon#wrote, iclass 31, count 0 2006.257.16:37:59.13#ibcon#about to read 3, iclass 31, count 0 2006.257.16:37:59.15#ibcon#read 3, iclass 31, count 0 2006.257.16:37:59.15#ibcon#about to read 4, iclass 31, count 0 2006.257.16:37:59.15#ibcon#read 4, iclass 31, count 0 2006.257.16:37:59.15#ibcon#about to read 5, iclass 31, count 0 2006.257.16:37:59.15#ibcon#read 5, iclass 31, count 0 2006.257.16:37:59.15#ibcon#about to read 6, iclass 31, count 0 2006.257.16:37:59.15#ibcon#read 6, iclass 31, count 0 2006.257.16:37:59.15#ibcon#end of sib2, iclass 31, count 0 2006.257.16:37:59.15#ibcon#*mode == 0, iclass 31, count 0 2006.257.16:37:59.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.16:37:59.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.16:37:59.15#ibcon#*before write, iclass 31, count 0 2006.257.16:37:59.15#ibcon#enter sib2, iclass 31, count 0 2006.257.16:37:59.15#ibcon#flushed, iclass 31, count 0 2006.257.16:37:59.15#ibcon#about to write, iclass 31, count 0 2006.257.16:37:59.15#ibcon#wrote, iclass 31, count 0 2006.257.16:37:59.15#ibcon#about to read 3, iclass 31, count 0 2006.257.16:37:59.19#ibcon#read 3, iclass 31, count 0 2006.257.16:37:59.19#ibcon#about to read 4, iclass 31, count 0 2006.257.16:37:59.19#ibcon#read 4, iclass 31, count 0 2006.257.16:37:59.19#ibcon#about to read 5, iclass 31, count 0 2006.257.16:37:59.19#ibcon#read 5, iclass 31, count 0 2006.257.16:37:59.19#ibcon#about to read 6, iclass 31, count 0 2006.257.16:37:59.19#ibcon#read 6, iclass 31, count 0 2006.257.16:37:59.19#ibcon#end of sib2, iclass 31, count 0 2006.257.16:37:59.19#ibcon#*after write, iclass 31, count 0 2006.257.16:37:59.19#ibcon#*before return 0, iclass 31, count 0 2006.257.16:37:59.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:37:59.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:37:59.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.16:37:59.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.16:37:59.19$vck44/va=6,4 2006.257.16:37:59.19#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.16:37:59.19#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.16:37:59.19#ibcon#ireg 11 cls_cnt 2 2006.257.16:37:59.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:37:59.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:37:59.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:37:59.25#ibcon#enter wrdev, iclass 33, count 2 2006.257.16:37:59.25#ibcon#first serial, iclass 33, count 2 2006.257.16:37:59.25#ibcon#enter sib2, iclass 33, count 2 2006.257.16:37:59.25#ibcon#flushed, iclass 33, count 2 2006.257.16:37:59.25#ibcon#about to write, iclass 33, count 2 2006.257.16:37:59.25#ibcon#wrote, iclass 33, count 2 2006.257.16:37:59.25#ibcon#about to read 3, iclass 33, count 2 2006.257.16:37:59.27#ibcon#read 3, iclass 33, count 2 2006.257.16:37:59.27#ibcon#about to read 4, iclass 33, count 2 2006.257.16:37:59.27#ibcon#read 4, iclass 33, count 2 2006.257.16:37:59.27#ibcon#about to read 5, iclass 33, count 2 2006.257.16:37:59.27#ibcon#read 5, iclass 33, count 2 2006.257.16:37:59.27#ibcon#about to read 6, iclass 33, count 2 2006.257.16:37:59.27#ibcon#read 6, iclass 33, count 2 2006.257.16:37:59.27#ibcon#end of sib2, iclass 33, count 2 2006.257.16:37:59.27#ibcon#*mode == 0, iclass 33, count 2 2006.257.16:37:59.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.16:37:59.27#ibcon#[25=AT06-04\r\n] 2006.257.16:37:59.27#ibcon#*before write, iclass 33, count 2 2006.257.16:37:59.27#ibcon#enter sib2, iclass 33, count 2 2006.257.16:37:59.27#ibcon#flushed, iclass 33, count 2 2006.257.16:37:59.27#ibcon#about to write, iclass 33, count 2 2006.257.16:37:59.27#ibcon#wrote, iclass 33, count 2 2006.257.16:37:59.27#ibcon#about to read 3, iclass 33, count 2 2006.257.16:37:59.30#ibcon#read 3, iclass 33, count 2 2006.257.16:37:59.30#ibcon#about to read 4, iclass 33, count 2 2006.257.16:37:59.30#ibcon#read 4, iclass 33, count 2 2006.257.16:37:59.30#ibcon#about to read 5, iclass 33, count 2 2006.257.16:37:59.30#ibcon#read 5, iclass 33, count 2 2006.257.16:37:59.30#ibcon#about to read 6, iclass 33, count 2 2006.257.16:37:59.30#ibcon#read 6, iclass 33, count 2 2006.257.16:37:59.30#ibcon#end of sib2, iclass 33, count 2 2006.257.16:37:59.30#ibcon#*after write, iclass 33, count 2 2006.257.16:37:59.30#ibcon#*before return 0, iclass 33, count 2 2006.257.16:37:59.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:37:59.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:37:59.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.16:37:59.30#ibcon#ireg 7 cls_cnt 0 2006.257.16:37:59.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:37:59.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:37:59.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:37:59.42#ibcon#enter wrdev, iclass 33, count 0 2006.257.16:37:59.42#ibcon#first serial, iclass 33, count 0 2006.257.16:37:59.42#ibcon#enter sib2, iclass 33, count 0 2006.257.16:37:59.42#ibcon#flushed, iclass 33, count 0 2006.257.16:37:59.42#ibcon#about to write, iclass 33, count 0 2006.257.16:37:59.42#ibcon#wrote, iclass 33, count 0 2006.257.16:37:59.42#ibcon#about to read 3, iclass 33, count 0 2006.257.16:37:59.44#ibcon#read 3, iclass 33, count 0 2006.257.16:37:59.44#ibcon#about to read 4, iclass 33, count 0 2006.257.16:37:59.44#ibcon#read 4, iclass 33, count 0 2006.257.16:37:59.44#ibcon#about to read 5, iclass 33, count 0 2006.257.16:37:59.44#ibcon#read 5, iclass 33, count 0 2006.257.16:37:59.44#ibcon#about to read 6, iclass 33, count 0 2006.257.16:37:59.44#ibcon#read 6, iclass 33, count 0 2006.257.16:37:59.44#ibcon#end of sib2, iclass 33, count 0 2006.257.16:37:59.44#ibcon#*mode == 0, iclass 33, count 0 2006.257.16:37:59.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.16:37:59.44#ibcon#[25=USB\r\n] 2006.257.16:37:59.44#ibcon#*before write, iclass 33, count 0 2006.257.16:37:59.44#ibcon#enter sib2, iclass 33, count 0 2006.257.16:37:59.44#ibcon#flushed, iclass 33, count 0 2006.257.16:37:59.44#ibcon#about to write, iclass 33, count 0 2006.257.16:37:59.44#ibcon#wrote, iclass 33, count 0 2006.257.16:37:59.44#ibcon#about to read 3, iclass 33, count 0 2006.257.16:37:59.47#ibcon#read 3, iclass 33, count 0 2006.257.16:37:59.47#ibcon#about to read 4, iclass 33, count 0 2006.257.16:37:59.47#ibcon#read 4, iclass 33, count 0 2006.257.16:37:59.47#ibcon#about to read 5, iclass 33, count 0 2006.257.16:37:59.47#ibcon#read 5, iclass 33, count 0 2006.257.16:37:59.47#ibcon#about to read 6, iclass 33, count 0 2006.257.16:37:59.47#ibcon#read 6, iclass 33, count 0 2006.257.16:37:59.47#ibcon#end of sib2, iclass 33, count 0 2006.257.16:37:59.47#ibcon#*after write, iclass 33, count 0 2006.257.16:37:59.47#ibcon#*before return 0, iclass 33, count 0 2006.257.16:37:59.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:37:59.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:37:59.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.16:37:59.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.16:37:59.47$vck44/valo=7,864.99 2006.257.16:37:59.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.16:37:59.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.16:37:59.47#ibcon#ireg 17 cls_cnt 0 2006.257.16:37:59.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:37:59.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:37:59.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:37:59.47#ibcon#enter wrdev, iclass 35, count 0 2006.257.16:37:59.47#ibcon#first serial, iclass 35, count 0 2006.257.16:37:59.47#ibcon#enter sib2, iclass 35, count 0 2006.257.16:37:59.47#ibcon#flushed, iclass 35, count 0 2006.257.16:37:59.47#ibcon#about to write, iclass 35, count 0 2006.257.16:37:59.47#ibcon#wrote, iclass 35, count 0 2006.257.16:37:59.47#ibcon#about to read 3, iclass 35, count 0 2006.257.16:37:59.49#ibcon#read 3, iclass 35, count 0 2006.257.16:37:59.49#ibcon#about to read 4, iclass 35, count 0 2006.257.16:37:59.49#ibcon#read 4, iclass 35, count 0 2006.257.16:37:59.49#ibcon#about to read 5, iclass 35, count 0 2006.257.16:37:59.49#ibcon#read 5, iclass 35, count 0 2006.257.16:37:59.49#ibcon#about to read 6, iclass 35, count 0 2006.257.16:37:59.49#ibcon#read 6, iclass 35, count 0 2006.257.16:37:59.49#ibcon#end of sib2, iclass 35, count 0 2006.257.16:37:59.49#ibcon#*mode == 0, iclass 35, count 0 2006.257.16:37:59.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.16:37:59.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.16:37:59.49#ibcon#*before write, iclass 35, count 0 2006.257.16:37:59.49#ibcon#enter sib2, iclass 35, count 0 2006.257.16:37:59.49#ibcon#flushed, iclass 35, count 0 2006.257.16:37:59.49#ibcon#about to write, iclass 35, count 0 2006.257.16:37:59.49#ibcon#wrote, iclass 35, count 0 2006.257.16:37:59.49#ibcon#about to read 3, iclass 35, count 0 2006.257.16:37:59.53#ibcon#read 3, iclass 35, count 0 2006.257.16:37:59.53#ibcon#about to read 4, iclass 35, count 0 2006.257.16:37:59.53#ibcon#read 4, iclass 35, count 0 2006.257.16:37:59.53#ibcon#about to read 5, iclass 35, count 0 2006.257.16:37:59.53#ibcon#read 5, iclass 35, count 0 2006.257.16:37:59.53#ibcon#about to read 6, iclass 35, count 0 2006.257.16:37:59.53#ibcon#read 6, iclass 35, count 0 2006.257.16:37:59.53#ibcon#end of sib2, iclass 35, count 0 2006.257.16:37:59.53#ibcon#*after write, iclass 35, count 0 2006.257.16:37:59.53#ibcon#*before return 0, iclass 35, count 0 2006.257.16:37:59.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:37:59.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:37:59.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.16:37:59.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.16:37:59.53$vck44/va=7,4 2006.257.16:37:59.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.16:37:59.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.16:37:59.53#ibcon#ireg 11 cls_cnt 2 2006.257.16:37:59.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:37:59.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:37:59.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:37:59.59#ibcon#enter wrdev, iclass 37, count 2 2006.257.16:37:59.59#ibcon#first serial, iclass 37, count 2 2006.257.16:37:59.59#ibcon#enter sib2, iclass 37, count 2 2006.257.16:37:59.59#ibcon#flushed, iclass 37, count 2 2006.257.16:37:59.59#ibcon#about to write, iclass 37, count 2 2006.257.16:37:59.59#ibcon#wrote, iclass 37, count 2 2006.257.16:37:59.59#ibcon#about to read 3, iclass 37, count 2 2006.257.16:37:59.61#ibcon#read 3, iclass 37, count 2 2006.257.16:37:59.61#ibcon#about to read 4, iclass 37, count 2 2006.257.16:37:59.61#ibcon#read 4, iclass 37, count 2 2006.257.16:37:59.61#ibcon#about to read 5, iclass 37, count 2 2006.257.16:37:59.61#ibcon#read 5, iclass 37, count 2 2006.257.16:37:59.61#ibcon#about to read 6, iclass 37, count 2 2006.257.16:37:59.61#ibcon#read 6, iclass 37, count 2 2006.257.16:37:59.61#ibcon#end of sib2, iclass 37, count 2 2006.257.16:37:59.61#ibcon#*mode == 0, iclass 37, count 2 2006.257.16:37:59.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.16:37:59.61#ibcon#[25=AT07-04\r\n] 2006.257.16:37:59.61#ibcon#*before write, iclass 37, count 2 2006.257.16:37:59.61#ibcon#enter sib2, iclass 37, count 2 2006.257.16:37:59.61#ibcon#flushed, iclass 37, count 2 2006.257.16:37:59.61#ibcon#about to write, iclass 37, count 2 2006.257.16:37:59.61#ibcon#wrote, iclass 37, count 2 2006.257.16:37:59.61#ibcon#about to read 3, iclass 37, count 2 2006.257.16:37:59.64#ibcon#read 3, iclass 37, count 2 2006.257.16:37:59.64#ibcon#about to read 4, iclass 37, count 2 2006.257.16:37:59.64#ibcon#read 4, iclass 37, count 2 2006.257.16:37:59.64#ibcon#about to read 5, iclass 37, count 2 2006.257.16:37:59.64#ibcon#read 5, iclass 37, count 2 2006.257.16:37:59.64#ibcon#about to read 6, iclass 37, count 2 2006.257.16:37:59.64#ibcon#read 6, iclass 37, count 2 2006.257.16:37:59.64#ibcon#end of sib2, iclass 37, count 2 2006.257.16:37:59.64#ibcon#*after write, iclass 37, count 2 2006.257.16:37:59.64#ibcon#*before return 0, iclass 37, count 2 2006.257.16:37:59.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:37:59.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:37:59.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.16:37:59.64#ibcon#ireg 7 cls_cnt 0 2006.257.16:37:59.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:37:59.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:37:59.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:37:59.76#ibcon#enter wrdev, iclass 37, count 0 2006.257.16:37:59.76#ibcon#first serial, iclass 37, count 0 2006.257.16:37:59.76#ibcon#enter sib2, iclass 37, count 0 2006.257.16:37:59.76#ibcon#flushed, iclass 37, count 0 2006.257.16:37:59.76#ibcon#about to write, iclass 37, count 0 2006.257.16:37:59.76#ibcon#wrote, iclass 37, count 0 2006.257.16:37:59.76#ibcon#about to read 3, iclass 37, count 0 2006.257.16:37:59.78#ibcon#read 3, iclass 37, count 0 2006.257.16:37:59.78#ibcon#about to read 4, iclass 37, count 0 2006.257.16:37:59.78#ibcon#read 4, iclass 37, count 0 2006.257.16:37:59.78#ibcon#about to read 5, iclass 37, count 0 2006.257.16:37:59.78#ibcon#read 5, iclass 37, count 0 2006.257.16:37:59.78#ibcon#about to read 6, iclass 37, count 0 2006.257.16:37:59.78#ibcon#read 6, iclass 37, count 0 2006.257.16:37:59.78#ibcon#end of sib2, iclass 37, count 0 2006.257.16:37:59.78#ibcon#*mode == 0, iclass 37, count 0 2006.257.16:37:59.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.16:37:59.78#ibcon#[25=USB\r\n] 2006.257.16:37:59.78#ibcon#*before write, iclass 37, count 0 2006.257.16:37:59.78#ibcon#enter sib2, iclass 37, count 0 2006.257.16:37:59.78#ibcon#flushed, iclass 37, count 0 2006.257.16:37:59.78#ibcon#about to write, iclass 37, count 0 2006.257.16:37:59.78#ibcon#wrote, iclass 37, count 0 2006.257.16:37:59.78#ibcon#about to read 3, iclass 37, count 0 2006.257.16:37:59.81#ibcon#read 3, iclass 37, count 0 2006.257.16:37:59.81#ibcon#about to read 4, iclass 37, count 0 2006.257.16:37:59.81#ibcon#read 4, iclass 37, count 0 2006.257.16:37:59.81#ibcon#about to read 5, iclass 37, count 0 2006.257.16:37:59.81#ibcon#read 5, iclass 37, count 0 2006.257.16:37:59.81#ibcon#about to read 6, iclass 37, count 0 2006.257.16:37:59.81#ibcon#read 6, iclass 37, count 0 2006.257.16:37:59.81#ibcon#end of sib2, iclass 37, count 0 2006.257.16:37:59.81#ibcon#*after write, iclass 37, count 0 2006.257.16:37:59.81#ibcon#*before return 0, iclass 37, count 0 2006.257.16:37:59.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:37:59.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:37:59.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.16:37:59.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.16:37:59.81$vck44/valo=8,884.99 2006.257.16:37:59.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.16:37:59.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.16:37:59.81#ibcon#ireg 17 cls_cnt 0 2006.257.16:37:59.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:37:59.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:37:59.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:37:59.81#ibcon#enter wrdev, iclass 39, count 0 2006.257.16:37:59.81#ibcon#first serial, iclass 39, count 0 2006.257.16:37:59.81#ibcon#enter sib2, iclass 39, count 0 2006.257.16:37:59.81#ibcon#flushed, iclass 39, count 0 2006.257.16:37:59.81#ibcon#about to write, iclass 39, count 0 2006.257.16:37:59.81#ibcon#wrote, iclass 39, count 0 2006.257.16:37:59.81#ibcon#about to read 3, iclass 39, count 0 2006.257.16:37:59.83#ibcon#read 3, iclass 39, count 0 2006.257.16:37:59.83#ibcon#about to read 4, iclass 39, count 0 2006.257.16:37:59.83#ibcon#read 4, iclass 39, count 0 2006.257.16:37:59.83#ibcon#about to read 5, iclass 39, count 0 2006.257.16:37:59.83#ibcon#read 5, iclass 39, count 0 2006.257.16:37:59.83#ibcon#about to read 6, iclass 39, count 0 2006.257.16:37:59.83#ibcon#read 6, iclass 39, count 0 2006.257.16:37:59.83#ibcon#end of sib2, iclass 39, count 0 2006.257.16:37:59.83#ibcon#*mode == 0, iclass 39, count 0 2006.257.16:37:59.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.16:37:59.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.16:37:59.83#ibcon#*before write, iclass 39, count 0 2006.257.16:37:59.83#ibcon#enter sib2, iclass 39, count 0 2006.257.16:37:59.83#ibcon#flushed, iclass 39, count 0 2006.257.16:37:59.83#ibcon#about to write, iclass 39, count 0 2006.257.16:37:59.83#ibcon#wrote, iclass 39, count 0 2006.257.16:37:59.83#ibcon#about to read 3, iclass 39, count 0 2006.257.16:37:59.87#ibcon#read 3, iclass 39, count 0 2006.257.16:37:59.87#ibcon#about to read 4, iclass 39, count 0 2006.257.16:37:59.87#ibcon#read 4, iclass 39, count 0 2006.257.16:37:59.87#ibcon#about to read 5, iclass 39, count 0 2006.257.16:37:59.87#ibcon#read 5, iclass 39, count 0 2006.257.16:37:59.87#ibcon#about to read 6, iclass 39, count 0 2006.257.16:37:59.87#ibcon#read 6, iclass 39, count 0 2006.257.16:37:59.87#ibcon#end of sib2, iclass 39, count 0 2006.257.16:37:59.87#ibcon#*after write, iclass 39, count 0 2006.257.16:37:59.87#ibcon#*before return 0, iclass 39, count 0 2006.257.16:37:59.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:37:59.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:37:59.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.16:37:59.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.16:37:59.87$vck44/va=8,4 2006.257.16:37:59.87#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.16:37:59.87#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.16:37:59.87#ibcon#ireg 11 cls_cnt 2 2006.257.16:37:59.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:37:59.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:37:59.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:37:59.93#ibcon#enter wrdev, iclass 3, count 2 2006.257.16:37:59.93#ibcon#first serial, iclass 3, count 2 2006.257.16:37:59.93#ibcon#enter sib2, iclass 3, count 2 2006.257.16:37:59.93#ibcon#flushed, iclass 3, count 2 2006.257.16:37:59.93#ibcon#about to write, iclass 3, count 2 2006.257.16:37:59.93#ibcon#wrote, iclass 3, count 2 2006.257.16:37:59.93#ibcon#about to read 3, iclass 3, count 2 2006.257.16:37:59.95#ibcon#read 3, iclass 3, count 2 2006.257.16:37:59.95#ibcon#about to read 4, iclass 3, count 2 2006.257.16:37:59.95#ibcon#read 4, iclass 3, count 2 2006.257.16:37:59.95#ibcon#about to read 5, iclass 3, count 2 2006.257.16:37:59.95#ibcon#read 5, iclass 3, count 2 2006.257.16:37:59.95#ibcon#about to read 6, iclass 3, count 2 2006.257.16:37:59.95#ibcon#read 6, iclass 3, count 2 2006.257.16:37:59.95#ibcon#end of sib2, iclass 3, count 2 2006.257.16:37:59.95#ibcon#*mode == 0, iclass 3, count 2 2006.257.16:37:59.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.16:37:59.95#ibcon#[25=AT08-04\r\n] 2006.257.16:37:59.95#ibcon#*before write, iclass 3, count 2 2006.257.16:37:59.95#ibcon#enter sib2, iclass 3, count 2 2006.257.16:37:59.95#ibcon#flushed, iclass 3, count 2 2006.257.16:37:59.95#ibcon#about to write, iclass 3, count 2 2006.257.16:37:59.95#ibcon#wrote, iclass 3, count 2 2006.257.16:37:59.95#ibcon#about to read 3, iclass 3, count 2 2006.257.16:37:59.98#ibcon#read 3, iclass 3, count 2 2006.257.16:37:59.98#ibcon#about to read 4, iclass 3, count 2 2006.257.16:37:59.98#ibcon#read 4, iclass 3, count 2 2006.257.16:37:59.98#ibcon#about to read 5, iclass 3, count 2 2006.257.16:37:59.98#ibcon#read 5, iclass 3, count 2 2006.257.16:37:59.98#ibcon#about to read 6, iclass 3, count 2 2006.257.16:37:59.98#ibcon#read 6, iclass 3, count 2 2006.257.16:37:59.98#ibcon#end of sib2, iclass 3, count 2 2006.257.16:37:59.98#ibcon#*after write, iclass 3, count 2 2006.257.16:37:59.98#ibcon#*before return 0, iclass 3, count 2 2006.257.16:37:59.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:37:59.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.16:37:59.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.16:37:59.98#ibcon#ireg 7 cls_cnt 0 2006.257.16:37:59.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:38:00.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:38:00.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:38:00.10#ibcon#enter wrdev, iclass 3, count 0 2006.257.16:38:00.10#ibcon#first serial, iclass 3, count 0 2006.257.16:38:00.10#ibcon#enter sib2, iclass 3, count 0 2006.257.16:38:00.10#ibcon#flushed, iclass 3, count 0 2006.257.16:38:00.10#ibcon#about to write, iclass 3, count 0 2006.257.16:38:00.10#ibcon#wrote, iclass 3, count 0 2006.257.16:38:00.10#ibcon#about to read 3, iclass 3, count 0 2006.257.16:38:00.12#ibcon#read 3, iclass 3, count 0 2006.257.16:38:00.12#ibcon#about to read 4, iclass 3, count 0 2006.257.16:38:00.12#ibcon#read 4, iclass 3, count 0 2006.257.16:38:00.12#ibcon#about to read 5, iclass 3, count 0 2006.257.16:38:00.12#ibcon#read 5, iclass 3, count 0 2006.257.16:38:00.12#ibcon#about to read 6, iclass 3, count 0 2006.257.16:38:00.12#ibcon#read 6, iclass 3, count 0 2006.257.16:38:00.12#ibcon#end of sib2, iclass 3, count 0 2006.257.16:38:00.12#ibcon#*mode == 0, iclass 3, count 0 2006.257.16:38:00.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.16:38:00.12#ibcon#[25=USB\r\n] 2006.257.16:38:00.12#ibcon#*before write, iclass 3, count 0 2006.257.16:38:00.12#ibcon#enter sib2, iclass 3, count 0 2006.257.16:38:00.12#ibcon#flushed, iclass 3, count 0 2006.257.16:38:00.12#ibcon#about to write, iclass 3, count 0 2006.257.16:38:00.12#ibcon#wrote, iclass 3, count 0 2006.257.16:38:00.12#ibcon#about to read 3, iclass 3, count 0 2006.257.16:38:00.15#ibcon#read 3, iclass 3, count 0 2006.257.16:38:00.15#ibcon#about to read 4, iclass 3, count 0 2006.257.16:38:00.15#ibcon#read 4, iclass 3, count 0 2006.257.16:38:00.15#ibcon#about to read 5, iclass 3, count 0 2006.257.16:38:00.15#ibcon#read 5, iclass 3, count 0 2006.257.16:38:00.15#ibcon#about to read 6, iclass 3, count 0 2006.257.16:38:00.15#ibcon#read 6, iclass 3, count 0 2006.257.16:38:00.15#ibcon#end of sib2, iclass 3, count 0 2006.257.16:38:00.15#ibcon#*after write, iclass 3, count 0 2006.257.16:38:00.15#ibcon#*before return 0, iclass 3, count 0 2006.257.16:38:00.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:38:00.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.16:38:00.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.16:38:00.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.16:38:00.15$vck44/vblo=1,629.99 2006.257.16:38:00.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.16:38:00.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.16:38:00.15#ibcon#ireg 17 cls_cnt 0 2006.257.16:38:00.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:38:00.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:38:00.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:38:00.15#ibcon#enter wrdev, iclass 5, count 0 2006.257.16:38:00.15#ibcon#first serial, iclass 5, count 0 2006.257.16:38:00.15#ibcon#enter sib2, iclass 5, count 0 2006.257.16:38:00.15#ibcon#flushed, iclass 5, count 0 2006.257.16:38:00.15#ibcon#about to write, iclass 5, count 0 2006.257.16:38:00.15#ibcon#wrote, iclass 5, count 0 2006.257.16:38:00.15#ibcon#about to read 3, iclass 5, count 0 2006.257.16:38:00.17#ibcon#read 3, iclass 5, count 0 2006.257.16:38:00.17#ibcon#about to read 4, iclass 5, count 0 2006.257.16:38:00.17#ibcon#read 4, iclass 5, count 0 2006.257.16:38:00.17#ibcon#about to read 5, iclass 5, count 0 2006.257.16:38:00.17#ibcon#read 5, iclass 5, count 0 2006.257.16:38:00.17#ibcon#about to read 6, iclass 5, count 0 2006.257.16:38:00.17#ibcon#read 6, iclass 5, count 0 2006.257.16:38:00.17#ibcon#end of sib2, iclass 5, count 0 2006.257.16:38:00.17#ibcon#*mode == 0, iclass 5, count 0 2006.257.16:38:00.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.16:38:00.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.16:38:00.17#ibcon#*before write, iclass 5, count 0 2006.257.16:38:00.17#ibcon#enter sib2, iclass 5, count 0 2006.257.16:38:00.17#ibcon#flushed, iclass 5, count 0 2006.257.16:38:00.17#ibcon#about to write, iclass 5, count 0 2006.257.16:38:00.17#ibcon#wrote, iclass 5, count 0 2006.257.16:38:00.17#ibcon#about to read 3, iclass 5, count 0 2006.257.16:38:00.21#ibcon#read 3, iclass 5, count 0 2006.257.16:38:00.21#ibcon#about to read 4, iclass 5, count 0 2006.257.16:38:00.21#ibcon#read 4, iclass 5, count 0 2006.257.16:38:00.21#ibcon#about to read 5, iclass 5, count 0 2006.257.16:38:00.21#ibcon#read 5, iclass 5, count 0 2006.257.16:38:00.21#ibcon#about to read 6, iclass 5, count 0 2006.257.16:38:00.21#ibcon#read 6, iclass 5, count 0 2006.257.16:38:00.21#ibcon#end of sib2, iclass 5, count 0 2006.257.16:38:00.21#ibcon#*after write, iclass 5, count 0 2006.257.16:38:00.21#ibcon#*before return 0, iclass 5, count 0 2006.257.16:38:00.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:38:00.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.16:38:00.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.16:38:00.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.16:38:00.21$vck44/vb=1,4 2006.257.16:38:00.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.16:38:00.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.16:38:00.21#ibcon#ireg 11 cls_cnt 2 2006.257.16:38:00.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:38:00.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:38:00.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:38:00.21#ibcon#enter wrdev, iclass 7, count 2 2006.257.16:38:00.21#ibcon#first serial, iclass 7, count 2 2006.257.16:38:00.21#ibcon#enter sib2, iclass 7, count 2 2006.257.16:38:00.21#ibcon#flushed, iclass 7, count 2 2006.257.16:38:00.21#ibcon#about to write, iclass 7, count 2 2006.257.16:38:00.21#ibcon#wrote, iclass 7, count 2 2006.257.16:38:00.21#ibcon#about to read 3, iclass 7, count 2 2006.257.16:38:00.23#ibcon#read 3, iclass 7, count 2 2006.257.16:38:00.23#ibcon#about to read 4, iclass 7, count 2 2006.257.16:38:00.23#ibcon#read 4, iclass 7, count 2 2006.257.16:38:00.23#ibcon#about to read 5, iclass 7, count 2 2006.257.16:38:00.23#ibcon#read 5, iclass 7, count 2 2006.257.16:38:00.23#ibcon#about to read 6, iclass 7, count 2 2006.257.16:38:00.23#ibcon#read 6, iclass 7, count 2 2006.257.16:38:00.23#ibcon#end of sib2, iclass 7, count 2 2006.257.16:38:00.23#ibcon#*mode == 0, iclass 7, count 2 2006.257.16:38:00.23#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.16:38:00.23#ibcon#[27=AT01-04\r\n] 2006.257.16:38:00.23#ibcon#*before write, iclass 7, count 2 2006.257.16:38:00.23#ibcon#enter sib2, iclass 7, count 2 2006.257.16:38:00.23#ibcon#flushed, iclass 7, count 2 2006.257.16:38:00.23#ibcon#about to write, iclass 7, count 2 2006.257.16:38:00.23#ibcon#wrote, iclass 7, count 2 2006.257.16:38:00.23#ibcon#about to read 3, iclass 7, count 2 2006.257.16:38:00.26#ibcon#read 3, iclass 7, count 2 2006.257.16:38:00.26#ibcon#about to read 4, iclass 7, count 2 2006.257.16:38:00.26#ibcon#read 4, iclass 7, count 2 2006.257.16:38:00.26#ibcon#about to read 5, iclass 7, count 2 2006.257.16:38:00.26#ibcon#read 5, iclass 7, count 2 2006.257.16:38:00.26#ibcon#about to read 6, iclass 7, count 2 2006.257.16:38:00.26#ibcon#read 6, iclass 7, count 2 2006.257.16:38:00.26#ibcon#end of sib2, iclass 7, count 2 2006.257.16:38:00.26#ibcon#*after write, iclass 7, count 2 2006.257.16:38:00.26#ibcon#*before return 0, iclass 7, count 2 2006.257.16:38:00.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:38:00.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.16:38:00.26#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.16:38:00.26#ibcon#ireg 7 cls_cnt 0 2006.257.16:38:00.26#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:38:00.38#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:38:00.38#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:38:00.38#ibcon#enter wrdev, iclass 7, count 0 2006.257.16:38:00.38#ibcon#first serial, iclass 7, count 0 2006.257.16:38:00.38#ibcon#enter sib2, iclass 7, count 0 2006.257.16:38:00.38#ibcon#flushed, iclass 7, count 0 2006.257.16:38:00.38#ibcon#about to write, iclass 7, count 0 2006.257.16:38:00.38#ibcon#wrote, iclass 7, count 0 2006.257.16:38:00.38#ibcon#about to read 3, iclass 7, count 0 2006.257.16:38:00.40#ibcon#read 3, iclass 7, count 0 2006.257.16:38:00.40#ibcon#about to read 4, iclass 7, count 0 2006.257.16:38:00.40#ibcon#read 4, iclass 7, count 0 2006.257.16:38:00.40#ibcon#about to read 5, iclass 7, count 0 2006.257.16:38:00.40#ibcon#read 5, iclass 7, count 0 2006.257.16:38:00.40#ibcon#about to read 6, iclass 7, count 0 2006.257.16:38:00.40#ibcon#read 6, iclass 7, count 0 2006.257.16:38:00.40#ibcon#end of sib2, iclass 7, count 0 2006.257.16:38:00.40#ibcon#*mode == 0, iclass 7, count 0 2006.257.16:38:00.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.16:38:00.40#ibcon#[27=USB\r\n] 2006.257.16:38:00.40#ibcon#*before write, iclass 7, count 0 2006.257.16:38:00.40#ibcon#enter sib2, iclass 7, count 0 2006.257.16:38:00.40#ibcon#flushed, iclass 7, count 0 2006.257.16:38:00.40#ibcon#about to write, iclass 7, count 0 2006.257.16:38:00.40#ibcon#wrote, iclass 7, count 0 2006.257.16:38:00.40#ibcon#about to read 3, iclass 7, count 0 2006.257.16:38:00.43#ibcon#read 3, iclass 7, count 0 2006.257.16:38:00.43#ibcon#about to read 4, iclass 7, count 0 2006.257.16:38:00.43#ibcon#read 4, iclass 7, count 0 2006.257.16:38:00.43#ibcon#about to read 5, iclass 7, count 0 2006.257.16:38:00.43#ibcon#read 5, iclass 7, count 0 2006.257.16:38:00.43#ibcon#about to read 6, iclass 7, count 0 2006.257.16:38:00.43#ibcon#read 6, iclass 7, count 0 2006.257.16:38:00.43#ibcon#end of sib2, iclass 7, count 0 2006.257.16:38:00.43#ibcon#*after write, iclass 7, count 0 2006.257.16:38:00.43#ibcon#*before return 0, iclass 7, count 0 2006.257.16:38:00.43#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:38:00.43#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.16:38:00.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.16:38:00.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.16:38:00.43$vck44/vblo=2,634.99 2006.257.16:38:00.43#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.16:38:00.43#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.16:38:00.43#ibcon#ireg 17 cls_cnt 0 2006.257.16:38:00.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:38:00.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:38:00.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:38:00.43#ibcon#enter wrdev, iclass 11, count 0 2006.257.16:38:00.43#ibcon#first serial, iclass 11, count 0 2006.257.16:38:00.43#ibcon#enter sib2, iclass 11, count 0 2006.257.16:38:00.43#ibcon#flushed, iclass 11, count 0 2006.257.16:38:00.43#ibcon#about to write, iclass 11, count 0 2006.257.16:38:00.43#ibcon#wrote, iclass 11, count 0 2006.257.16:38:00.43#ibcon#about to read 3, iclass 11, count 0 2006.257.16:38:00.45#ibcon#read 3, iclass 11, count 0 2006.257.16:38:00.45#ibcon#about to read 4, iclass 11, count 0 2006.257.16:38:00.45#ibcon#read 4, iclass 11, count 0 2006.257.16:38:00.45#ibcon#about to read 5, iclass 11, count 0 2006.257.16:38:00.45#ibcon#read 5, iclass 11, count 0 2006.257.16:38:00.45#ibcon#about to read 6, iclass 11, count 0 2006.257.16:38:00.45#ibcon#read 6, iclass 11, count 0 2006.257.16:38:00.45#ibcon#end of sib2, iclass 11, count 0 2006.257.16:38:00.45#ibcon#*mode == 0, iclass 11, count 0 2006.257.16:38:00.45#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.16:38:00.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.16:38:00.45#ibcon#*before write, iclass 11, count 0 2006.257.16:38:00.45#ibcon#enter sib2, iclass 11, count 0 2006.257.16:38:00.45#ibcon#flushed, iclass 11, count 0 2006.257.16:38:00.45#ibcon#about to write, iclass 11, count 0 2006.257.16:38:00.45#ibcon#wrote, iclass 11, count 0 2006.257.16:38:00.45#ibcon#about to read 3, iclass 11, count 0 2006.257.16:38:00.49#ibcon#read 3, iclass 11, count 0 2006.257.16:38:00.49#ibcon#about to read 4, iclass 11, count 0 2006.257.16:38:00.49#ibcon#read 4, iclass 11, count 0 2006.257.16:38:00.49#ibcon#about to read 5, iclass 11, count 0 2006.257.16:38:00.49#ibcon#read 5, iclass 11, count 0 2006.257.16:38:00.49#ibcon#about to read 6, iclass 11, count 0 2006.257.16:38:00.49#ibcon#read 6, iclass 11, count 0 2006.257.16:38:00.49#ibcon#end of sib2, iclass 11, count 0 2006.257.16:38:00.49#ibcon#*after write, iclass 11, count 0 2006.257.16:38:00.49#ibcon#*before return 0, iclass 11, count 0 2006.257.16:38:00.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:38:00.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.16:38:00.49#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.16:38:00.49#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.16:38:00.49$vck44/vb=2,5 2006.257.16:38:00.49#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.16:38:00.49#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.16:38:00.49#ibcon#ireg 11 cls_cnt 2 2006.257.16:38:00.49#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:38:00.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:38:00.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:38:00.55#ibcon#enter wrdev, iclass 13, count 2 2006.257.16:38:00.55#ibcon#first serial, iclass 13, count 2 2006.257.16:38:00.55#ibcon#enter sib2, iclass 13, count 2 2006.257.16:38:00.55#ibcon#flushed, iclass 13, count 2 2006.257.16:38:00.55#ibcon#about to write, iclass 13, count 2 2006.257.16:38:00.55#ibcon#wrote, iclass 13, count 2 2006.257.16:38:00.55#ibcon#about to read 3, iclass 13, count 2 2006.257.16:38:00.57#ibcon#read 3, iclass 13, count 2 2006.257.16:38:00.57#ibcon#about to read 4, iclass 13, count 2 2006.257.16:38:00.57#ibcon#read 4, iclass 13, count 2 2006.257.16:38:00.57#ibcon#about to read 5, iclass 13, count 2 2006.257.16:38:00.57#ibcon#read 5, iclass 13, count 2 2006.257.16:38:00.57#ibcon#about to read 6, iclass 13, count 2 2006.257.16:38:00.57#ibcon#read 6, iclass 13, count 2 2006.257.16:38:00.57#ibcon#end of sib2, iclass 13, count 2 2006.257.16:38:00.57#ibcon#*mode == 0, iclass 13, count 2 2006.257.16:38:00.57#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.16:38:00.57#ibcon#[27=AT02-05\r\n] 2006.257.16:38:00.57#ibcon#*before write, iclass 13, count 2 2006.257.16:38:00.57#ibcon#enter sib2, iclass 13, count 2 2006.257.16:38:00.57#ibcon#flushed, iclass 13, count 2 2006.257.16:38:00.57#ibcon#about to write, iclass 13, count 2 2006.257.16:38:00.57#ibcon#wrote, iclass 13, count 2 2006.257.16:38:00.57#ibcon#about to read 3, iclass 13, count 2 2006.257.16:38:00.60#ibcon#read 3, iclass 13, count 2 2006.257.16:38:00.60#ibcon#about to read 4, iclass 13, count 2 2006.257.16:38:00.60#ibcon#read 4, iclass 13, count 2 2006.257.16:38:00.60#ibcon#about to read 5, iclass 13, count 2 2006.257.16:38:00.60#ibcon#read 5, iclass 13, count 2 2006.257.16:38:00.60#ibcon#about to read 6, iclass 13, count 2 2006.257.16:38:00.60#ibcon#read 6, iclass 13, count 2 2006.257.16:38:00.60#ibcon#end of sib2, iclass 13, count 2 2006.257.16:38:00.60#ibcon#*after write, iclass 13, count 2 2006.257.16:38:00.60#ibcon#*before return 0, iclass 13, count 2 2006.257.16:38:00.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:38:00.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.16:38:00.60#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.16:38:00.60#ibcon#ireg 7 cls_cnt 0 2006.257.16:38:00.60#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:38:00.72#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:38:00.72#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:38:00.72#ibcon#enter wrdev, iclass 13, count 0 2006.257.16:38:00.72#ibcon#first serial, iclass 13, count 0 2006.257.16:38:00.72#ibcon#enter sib2, iclass 13, count 0 2006.257.16:38:00.72#ibcon#flushed, iclass 13, count 0 2006.257.16:38:00.72#ibcon#about to write, iclass 13, count 0 2006.257.16:38:00.72#ibcon#wrote, iclass 13, count 0 2006.257.16:38:00.72#ibcon#about to read 3, iclass 13, count 0 2006.257.16:38:00.74#ibcon#read 3, iclass 13, count 0 2006.257.16:38:00.74#ibcon#about to read 4, iclass 13, count 0 2006.257.16:38:00.74#ibcon#read 4, iclass 13, count 0 2006.257.16:38:00.74#ibcon#about to read 5, iclass 13, count 0 2006.257.16:38:00.74#ibcon#read 5, iclass 13, count 0 2006.257.16:38:00.74#ibcon#about to read 6, iclass 13, count 0 2006.257.16:38:00.74#ibcon#read 6, iclass 13, count 0 2006.257.16:38:00.74#ibcon#end of sib2, iclass 13, count 0 2006.257.16:38:00.74#ibcon#*mode == 0, iclass 13, count 0 2006.257.16:38:00.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.16:38:00.74#ibcon#[27=USB\r\n] 2006.257.16:38:00.74#ibcon#*before write, iclass 13, count 0 2006.257.16:38:00.74#ibcon#enter sib2, iclass 13, count 0 2006.257.16:38:00.74#ibcon#flushed, iclass 13, count 0 2006.257.16:38:00.74#ibcon#about to write, iclass 13, count 0 2006.257.16:38:00.74#ibcon#wrote, iclass 13, count 0 2006.257.16:38:00.74#ibcon#about to read 3, iclass 13, count 0 2006.257.16:38:00.77#ibcon#read 3, iclass 13, count 0 2006.257.16:38:00.77#ibcon#about to read 4, iclass 13, count 0 2006.257.16:38:00.77#ibcon#read 4, iclass 13, count 0 2006.257.16:38:00.77#ibcon#about to read 5, iclass 13, count 0 2006.257.16:38:00.77#ibcon#read 5, iclass 13, count 0 2006.257.16:38:00.77#ibcon#about to read 6, iclass 13, count 0 2006.257.16:38:00.77#ibcon#read 6, iclass 13, count 0 2006.257.16:38:00.77#ibcon#end of sib2, iclass 13, count 0 2006.257.16:38:00.77#ibcon#*after write, iclass 13, count 0 2006.257.16:38:00.77#ibcon#*before return 0, iclass 13, count 0 2006.257.16:38:00.77#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:38:00.77#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.16:38:00.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.16:38:00.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.16:38:00.77$vck44/vblo=3,649.99 2006.257.16:38:00.77#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.16:38:00.77#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.16:38:00.77#ibcon#ireg 17 cls_cnt 0 2006.257.16:38:00.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:38:00.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:38:00.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:38:00.77#ibcon#enter wrdev, iclass 15, count 0 2006.257.16:38:00.77#ibcon#first serial, iclass 15, count 0 2006.257.16:38:00.77#ibcon#enter sib2, iclass 15, count 0 2006.257.16:38:00.77#ibcon#flushed, iclass 15, count 0 2006.257.16:38:00.77#ibcon#about to write, iclass 15, count 0 2006.257.16:38:00.77#ibcon#wrote, iclass 15, count 0 2006.257.16:38:00.77#ibcon#about to read 3, iclass 15, count 0 2006.257.16:38:00.79#ibcon#read 3, iclass 15, count 0 2006.257.16:38:00.79#ibcon#about to read 4, iclass 15, count 0 2006.257.16:38:00.79#ibcon#read 4, iclass 15, count 0 2006.257.16:38:00.79#ibcon#about to read 5, iclass 15, count 0 2006.257.16:38:00.79#ibcon#read 5, iclass 15, count 0 2006.257.16:38:00.79#ibcon#about to read 6, iclass 15, count 0 2006.257.16:38:00.79#ibcon#read 6, iclass 15, count 0 2006.257.16:38:00.79#ibcon#end of sib2, iclass 15, count 0 2006.257.16:38:00.79#ibcon#*mode == 0, iclass 15, count 0 2006.257.16:38:00.79#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.16:38:00.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.16:38:00.79#ibcon#*before write, iclass 15, count 0 2006.257.16:38:00.79#ibcon#enter sib2, iclass 15, count 0 2006.257.16:38:00.79#ibcon#flushed, iclass 15, count 0 2006.257.16:38:00.79#ibcon#about to write, iclass 15, count 0 2006.257.16:38:00.79#ibcon#wrote, iclass 15, count 0 2006.257.16:38:00.79#ibcon#about to read 3, iclass 15, count 0 2006.257.16:38:00.83#ibcon#read 3, iclass 15, count 0 2006.257.16:38:00.83#ibcon#about to read 4, iclass 15, count 0 2006.257.16:38:00.83#ibcon#read 4, iclass 15, count 0 2006.257.16:38:00.83#ibcon#about to read 5, iclass 15, count 0 2006.257.16:38:00.83#ibcon#read 5, iclass 15, count 0 2006.257.16:38:00.83#ibcon#about to read 6, iclass 15, count 0 2006.257.16:38:00.83#ibcon#read 6, iclass 15, count 0 2006.257.16:38:00.83#ibcon#end of sib2, iclass 15, count 0 2006.257.16:38:00.83#ibcon#*after write, iclass 15, count 0 2006.257.16:38:00.83#ibcon#*before return 0, iclass 15, count 0 2006.257.16:38:00.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:38:00.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.16:38:00.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.16:38:00.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.16:38:00.83$vck44/vb=3,4 2006.257.16:38:00.83#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.16:38:00.83#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.16:38:00.83#ibcon#ireg 11 cls_cnt 2 2006.257.16:38:00.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:38:00.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:38:00.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:38:00.89#ibcon#enter wrdev, iclass 17, count 2 2006.257.16:38:00.89#ibcon#first serial, iclass 17, count 2 2006.257.16:38:00.89#ibcon#enter sib2, iclass 17, count 2 2006.257.16:38:00.89#ibcon#flushed, iclass 17, count 2 2006.257.16:38:00.89#ibcon#about to write, iclass 17, count 2 2006.257.16:38:00.89#ibcon#wrote, iclass 17, count 2 2006.257.16:38:00.89#ibcon#about to read 3, iclass 17, count 2 2006.257.16:38:00.91#ibcon#read 3, iclass 17, count 2 2006.257.16:38:00.91#ibcon#about to read 4, iclass 17, count 2 2006.257.16:38:00.91#ibcon#read 4, iclass 17, count 2 2006.257.16:38:00.91#ibcon#about to read 5, iclass 17, count 2 2006.257.16:38:00.91#ibcon#read 5, iclass 17, count 2 2006.257.16:38:00.91#ibcon#about to read 6, iclass 17, count 2 2006.257.16:38:00.91#ibcon#read 6, iclass 17, count 2 2006.257.16:38:00.91#ibcon#end of sib2, iclass 17, count 2 2006.257.16:38:00.91#ibcon#*mode == 0, iclass 17, count 2 2006.257.16:38:00.91#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.16:38:00.91#ibcon#[27=AT03-04\r\n] 2006.257.16:38:00.91#ibcon#*before write, iclass 17, count 2 2006.257.16:38:00.91#ibcon#enter sib2, iclass 17, count 2 2006.257.16:38:00.91#ibcon#flushed, iclass 17, count 2 2006.257.16:38:00.91#ibcon#about to write, iclass 17, count 2 2006.257.16:38:00.91#ibcon#wrote, iclass 17, count 2 2006.257.16:38:00.91#ibcon#about to read 3, iclass 17, count 2 2006.257.16:38:00.94#ibcon#read 3, iclass 17, count 2 2006.257.16:38:00.94#ibcon#about to read 4, iclass 17, count 2 2006.257.16:38:00.94#ibcon#read 4, iclass 17, count 2 2006.257.16:38:00.94#ibcon#about to read 5, iclass 17, count 2 2006.257.16:38:00.94#ibcon#read 5, iclass 17, count 2 2006.257.16:38:00.94#ibcon#about to read 6, iclass 17, count 2 2006.257.16:38:00.94#ibcon#read 6, iclass 17, count 2 2006.257.16:38:00.94#ibcon#end of sib2, iclass 17, count 2 2006.257.16:38:00.94#ibcon#*after write, iclass 17, count 2 2006.257.16:38:00.94#ibcon#*before return 0, iclass 17, count 2 2006.257.16:38:00.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:38:00.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.16:38:00.94#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.16:38:00.94#ibcon#ireg 7 cls_cnt 0 2006.257.16:38:00.94#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:38:01.06#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:38:01.06#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:38:01.06#ibcon#enter wrdev, iclass 17, count 0 2006.257.16:38:01.06#ibcon#first serial, iclass 17, count 0 2006.257.16:38:01.06#ibcon#enter sib2, iclass 17, count 0 2006.257.16:38:01.06#ibcon#flushed, iclass 17, count 0 2006.257.16:38:01.06#ibcon#about to write, iclass 17, count 0 2006.257.16:38:01.06#ibcon#wrote, iclass 17, count 0 2006.257.16:38:01.06#ibcon#about to read 3, iclass 17, count 0 2006.257.16:38:01.08#ibcon#read 3, iclass 17, count 0 2006.257.16:38:01.08#ibcon#about to read 4, iclass 17, count 0 2006.257.16:38:01.08#ibcon#read 4, iclass 17, count 0 2006.257.16:38:01.08#ibcon#about to read 5, iclass 17, count 0 2006.257.16:38:01.08#ibcon#read 5, iclass 17, count 0 2006.257.16:38:01.08#ibcon#about to read 6, iclass 17, count 0 2006.257.16:38:01.08#ibcon#read 6, iclass 17, count 0 2006.257.16:38:01.08#ibcon#end of sib2, iclass 17, count 0 2006.257.16:38:01.08#ibcon#*mode == 0, iclass 17, count 0 2006.257.16:38:01.08#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.16:38:01.08#ibcon#[27=USB\r\n] 2006.257.16:38:01.08#ibcon#*before write, iclass 17, count 0 2006.257.16:38:01.08#ibcon#enter sib2, iclass 17, count 0 2006.257.16:38:01.08#ibcon#flushed, iclass 17, count 0 2006.257.16:38:01.08#ibcon#about to write, iclass 17, count 0 2006.257.16:38:01.08#ibcon#wrote, iclass 17, count 0 2006.257.16:38:01.08#ibcon#about to read 3, iclass 17, count 0 2006.257.16:38:01.11#ibcon#read 3, iclass 17, count 0 2006.257.16:38:01.11#ibcon#about to read 4, iclass 17, count 0 2006.257.16:38:01.11#ibcon#read 4, iclass 17, count 0 2006.257.16:38:01.11#ibcon#about to read 5, iclass 17, count 0 2006.257.16:38:01.11#ibcon#read 5, iclass 17, count 0 2006.257.16:38:01.11#ibcon#about to read 6, iclass 17, count 0 2006.257.16:38:01.11#ibcon#read 6, iclass 17, count 0 2006.257.16:38:01.11#ibcon#end of sib2, iclass 17, count 0 2006.257.16:38:01.11#ibcon#*after write, iclass 17, count 0 2006.257.16:38:01.11#ibcon#*before return 0, iclass 17, count 0 2006.257.16:38:01.11#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:38:01.11#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.16:38:01.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.16:38:01.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.16:38:01.11$vck44/vblo=4,679.99 2006.257.16:38:01.11#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.16:38:01.11#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.16:38:01.11#ibcon#ireg 17 cls_cnt 0 2006.257.16:38:01.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:38:01.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:38:01.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:38:01.11#ibcon#enter wrdev, iclass 19, count 0 2006.257.16:38:01.11#ibcon#first serial, iclass 19, count 0 2006.257.16:38:01.11#ibcon#enter sib2, iclass 19, count 0 2006.257.16:38:01.11#ibcon#flushed, iclass 19, count 0 2006.257.16:38:01.11#ibcon#about to write, iclass 19, count 0 2006.257.16:38:01.11#ibcon#wrote, iclass 19, count 0 2006.257.16:38:01.11#ibcon#about to read 3, iclass 19, count 0 2006.257.16:38:01.13#ibcon#read 3, iclass 19, count 0 2006.257.16:38:01.13#ibcon#about to read 4, iclass 19, count 0 2006.257.16:38:01.13#ibcon#read 4, iclass 19, count 0 2006.257.16:38:01.13#ibcon#about to read 5, iclass 19, count 0 2006.257.16:38:01.13#ibcon#read 5, iclass 19, count 0 2006.257.16:38:01.13#ibcon#about to read 6, iclass 19, count 0 2006.257.16:38:01.13#ibcon#read 6, iclass 19, count 0 2006.257.16:38:01.13#ibcon#end of sib2, iclass 19, count 0 2006.257.16:38:01.13#ibcon#*mode == 0, iclass 19, count 0 2006.257.16:38:01.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.16:38:01.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.16:38:01.13#ibcon#*before write, iclass 19, count 0 2006.257.16:38:01.13#ibcon#enter sib2, iclass 19, count 0 2006.257.16:38:01.13#ibcon#flushed, iclass 19, count 0 2006.257.16:38:01.13#ibcon#about to write, iclass 19, count 0 2006.257.16:38:01.13#ibcon#wrote, iclass 19, count 0 2006.257.16:38:01.13#ibcon#about to read 3, iclass 19, count 0 2006.257.16:38:01.17#ibcon#read 3, iclass 19, count 0 2006.257.16:38:01.17#ibcon#about to read 4, iclass 19, count 0 2006.257.16:38:01.17#ibcon#read 4, iclass 19, count 0 2006.257.16:38:01.17#ibcon#about to read 5, iclass 19, count 0 2006.257.16:38:01.17#ibcon#read 5, iclass 19, count 0 2006.257.16:38:01.17#ibcon#about to read 6, iclass 19, count 0 2006.257.16:38:01.17#ibcon#read 6, iclass 19, count 0 2006.257.16:38:01.17#ibcon#end of sib2, iclass 19, count 0 2006.257.16:38:01.17#ibcon#*after write, iclass 19, count 0 2006.257.16:38:01.17#ibcon#*before return 0, iclass 19, count 0 2006.257.16:38:01.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:38:01.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.16:38:01.17#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.16:38:01.17#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.16:38:01.17$vck44/vb=4,5 2006.257.16:38:01.17#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.16:38:01.17#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.16:38:01.17#ibcon#ireg 11 cls_cnt 2 2006.257.16:38:01.17#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:38:01.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:38:01.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:38:01.23#ibcon#enter wrdev, iclass 21, count 2 2006.257.16:38:01.23#ibcon#first serial, iclass 21, count 2 2006.257.16:38:01.23#ibcon#enter sib2, iclass 21, count 2 2006.257.16:38:01.23#ibcon#flushed, iclass 21, count 2 2006.257.16:38:01.23#ibcon#about to write, iclass 21, count 2 2006.257.16:38:01.23#ibcon#wrote, iclass 21, count 2 2006.257.16:38:01.23#ibcon#about to read 3, iclass 21, count 2 2006.257.16:38:01.25#ibcon#read 3, iclass 21, count 2 2006.257.16:38:01.25#ibcon#about to read 4, iclass 21, count 2 2006.257.16:38:01.25#ibcon#read 4, iclass 21, count 2 2006.257.16:38:01.25#ibcon#about to read 5, iclass 21, count 2 2006.257.16:38:01.25#ibcon#read 5, iclass 21, count 2 2006.257.16:38:01.25#ibcon#about to read 6, iclass 21, count 2 2006.257.16:38:01.25#ibcon#read 6, iclass 21, count 2 2006.257.16:38:01.25#ibcon#end of sib2, iclass 21, count 2 2006.257.16:38:01.25#ibcon#*mode == 0, iclass 21, count 2 2006.257.16:38:01.25#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.16:38:01.25#ibcon#[27=AT04-05\r\n] 2006.257.16:38:01.25#ibcon#*before write, iclass 21, count 2 2006.257.16:38:01.25#ibcon#enter sib2, iclass 21, count 2 2006.257.16:38:01.25#ibcon#flushed, iclass 21, count 2 2006.257.16:38:01.25#ibcon#about to write, iclass 21, count 2 2006.257.16:38:01.25#ibcon#wrote, iclass 21, count 2 2006.257.16:38:01.25#ibcon#about to read 3, iclass 21, count 2 2006.257.16:38:01.28#ibcon#read 3, iclass 21, count 2 2006.257.16:38:01.28#ibcon#about to read 4, iclass 21, count 2 2006.257.16:38:01.28#ibcon#read 4, iclass 21, count 2 2006.257.16:38:01.28#ibcon#about to read 5, iclass 21, count 2 2006.257.16:38:01.28#ibcon#read 5, iclass 21, count 2 2006.257.16:38:01.28#ibcon#about to read 6, iclass 21, count 2 2006.257.16:38:01.28#ibcon#read 6, iclass 21, count 2 2006.257.16:38:01.28#ibcon#end of sib2, iclass 21, count 2 2006.257.16:38:01.28#ibcon#*after write, iclass 21, count 2 2006.257.16:38:01.28#ibcon#*before return 0, iclass 21, count 2 2006.257.16:38:01.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:38:01.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.16:38:01.28#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.16:38:01.28#ibcon#ireg 7 cls_cnt 0 2006.257.16:38:01.28#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:38:01.40#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:38:01.40#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:38:01.40#ibcon#enter wrdev, iclass 21, count 0 2006.257.16:38:01.40#ibcon#first serial, iclass 21, count 0 2006.257.16:38:01.40#ibcon#enter sib2, iclass 21, count 0 2006.257.16:38:01.40#ibcon#flushed, iclass 21, count 0 2006.257.16:38:01.40#ibcon#about to write, iclass 21, count 0 2006.257.16:38:01.40#ibcon#wrote, iclass 21, count 0 2006.257.16:38:01.40#ibcon#about to read 3, iclass 21, count 0 2006.257.16:38:01.42#ibcon#read 3, iclass 21, count 0 2006.257.16:38:01.42#ibcon#about to read 4, iclass 21, count 0 2006.257.16:38:01.42#ibcon#read 4, iclass 21, count 0 2006.257.16:38:01.42#ibcon#about to read 5, iclass 21, count 0 2006.257.16:38:01.42#ibcon#read 5, iclass 21, count 0 2006.257.16:38:01.42#ibcon#about to read 6, iclass 21, count 0 2006.257.16:38:01.42#ibcon#read 6, iclass 21, count 0 2006.257.16:38:01.42#ibcon#end of sib2, iclass 21, count 0 2006.257.16:38:01.42#ibcon#*mode == 0, iclass 21, count 0 2006.257.16:38:01.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.16:38:01.42#ibcon#[27=USB\r\n] 2006.257.16:38:01.42#ibcon#*before write, iclass 21, count 0 2006.257.16:38:01.42#ibcon#enter sib2, iclass 21, count 0 2006.257.16:38:01.42#ibcon#flushed, iclass 21, count 0 2006.257.16:38:01.42#ibcon#about to write, iclass 21, count 0 2006.257.16:38:01.42#ibcon#wrote, iclass 21, count 0 2006.257.16:38:01.42#ibcon#about to read 3, iclass 21, count 0 2006.257.16:38:01.45#ibcon#read 3, iclass 21, count 0 2006.257.16:38:01.45#ibcon#about to read 4, iclass 21, count 0 2006.257.16:38:01.45#ibcon#read 4, iclass 21, count 0 2006.257.16:38:01.45#ibcon#about to read 5, iclass 21, count 0 2006.257.16:38:01.45#ibcon#read 5, iclass 21, count 0 2006.257.16:38:01.45#ibcon#about to read 6, iclass 21, count 0 2006.257.16:38:01.45#ibcon#read 6, iclass 21, count 0 2006.257.16:38:01.45#ibcon#end of sib2, iclass 21, count 0 2006.257.16:38:01.45#ibcon#*after write, iclass 21, count 0 2006.257.16:38:01.45#ibcon#*before return 0, iclass 21, count 0 2006.257.16:38:01.45#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:38:01.45#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.16:38:01.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.16:38:01.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.16:38:01.45$vck44/vblo=5,709.99 2006.257.16:38:01.45#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.16:38:01.45#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.16:38:01.45#ibcon#ireg 17 cls_cnt 0 2006.257.16:38:01.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:38:01.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:38:01.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:38:01.45#ibcon#enter wrdev, iclass 23, count 0 2006.257.16:38:01.45#ibcon#first serial, iclass 23, count 0 2006.257.16:38:01.45#ibcon#enter sib2, iclass 23, count 0 2006.257.16:38:01.45#ibcon#flushed, iclass 23, count 0 2006.257.16:38:01.45#ibcon#about to write, iclass 23, count 0 2006.257.16:38:01.45#ibcon#wrote, iclass 23, count 0 2006.257.16:38:01.45#ibcon#about to read 3, iclass 23, count 0 2006.257.16:38:01.47#ibcon#read 3, iclass 23, count 0 2006.257.16:38:01.47#ibcon#about to read 4, iclass 23, count 0 2006.257.16:38:01.47#ibcon#read 4, iclass 23, count 0 2006.257.16:38:01.47#ibcon#about to read 5, iclass 23, count 0 2006.257.16:38:01.47#ibcon#read 5, iclass 23, count 0 2006.257.16:38:01.47#ibcon#about to read 6, iclass 23, count 0 2006.257.16:38:01.47#ibcon#read 6, iclass 23, count 0 2006.257.16:38:01.47#ibcon#end of sib2, iclass 23, count 0 2006.257.16:38:01.47#ibcon#*mode == 0, iclass 23, count 0 2006.257.16:38:01.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.16:38:01.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:38:01.47#ibcon#*before write, iclass 23, count 0 2006.257.16:38:01.47#ibcon#enter sib2, iclass 23, count 0 2006.257.16:38:01.47#ibcon#flushed, iclass 23, count 0 2006.257.16:38:01.47#ibcon#about to write, iclass 23, count 0 2006.257.16:38:01.47#ibcon#wrote, iclass 23, count 0 2006.257.16:38:01.47#ibcon#about to read 3, iclass 23, count 0 2006.257.16:38:01.51#ibcon#read 3, iclass 23, count 0 2006.257.16:38:01.51#ibcon#about to read 4, iclass 23, count 0 2006.257.16:38:01.51#ibcon#read 4, iclass 23, count 0 2006.257.16:38:01.51#ibcon#about to read 5, iclass 23, count 0 2006.257.16:38:01.51#ibcon#read 5, iclass 23, count 0 2006.257.16:38:01.51#ibcon#about to read 6, iclass 23, count 0 2006.257.16:38:01.51#ibcon#read 6, iclass 23, count 0 2006.257.16:38:01.51#ibcon#end of sib2, iclass 23, count 0 2006.257.16:38:01.51#ibcon#*after write, iclass 23, count 0 2006.257.16:38:01.51#ibcon#*before return 0, iclass 23, count 0 2006.257.16:38:01.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:38:01.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:38:01.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.16:38:01.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.16:38:01.51$vck44/vb=5,4 2006.257.16:38:01.51#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.16:38:01.51#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.16:38:01.51#ibcon#ireg 11 cls_cnt 2 2006.257.16:38:01.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:38:01.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:38:01.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:38:01.57#ibcon#enter wrdev, iclass 25, count 2 2006.257.16:38:01.57#ibcon#first serial, iclass 25, count 2 2006.257.16:38:01.57#ibcon#enter sib2, iclass 25, count 2 2006.257.16:38:01.57#ibcon#flushed, iclass 25, count 2 2006.257.16:38:01.57#ibcon#about to write, iclass 25, count 2 2006.257.16:38:01.57#ibcon#wrote, iclass 25, count 2 2006.257.16:38:01.57#ibcon#about to read 3, iclass 25, count 2 2006.257.16:38:01.59#ibcon#read 3, iclass 25, count 2 2006.257.16:38:01.59#ibcon#about to read 4, iclass 25, count 2 2006.257.16:38:01.59#ibcon#read 4, iclass 25, count 2 2006.257.16:38:01.59#ibcon#about to read 5, iclass 25, count 2 2006.257.16:38:01.59#ibcon#read 5, iclass 25, count 2 2006.257.16:38:01.59#ibcon#about to read 6, iclass 25, count 2 2006.257.16:38:01.59#ibcon#read 6, iclass 25, count 2 2006.257.16:38:01.59#ibcon#end of sib2, iclass 25, count 2 2006.257.16:38:01.59#ibcon#*mode == 0, iclass 25, count 2 2006.257.16:38:01.59#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.16:38:01.59#ibcon#[27=AT05-04\r\n] 2006.257.16:38:01.59#ibcon#*before write, iclass 25, count 2 2006.257.16:38:01.59#ibcon#enter sib2, iclass 25, count 2 2006.257.16:38:01.59#ibcon#flushed, iclass 25, count 2 2006.257.16:38:01.59#ibcon#about to write, iclass 25, count 2 2006.257.16:38:01.59#ibcon#wrote, iclass 25, count 2 2006.257.16:38:01.59#ibcon#about to read 3, iclass 25, count 2 2006.257.16:38:01.62#ibcon#read 3, iclass 25, count 2 2006.257.16:38:01.62#ibcon#about to read 4, iclass 25, count 2 2006.257.16:38:01.62#ibcon#read 4, iclass 25, count 2 2006.257.16:38:01.62#ibcon#about to read 5, iclass 25, count 2 2006.257.16:38:01.62#ibcon#read 5, iclass 25, count 2 2006.257.16:38:01.62#ibcon#about to read 6, iclass 25, count 2 2006.257.16:38:01.62#ibcon#read 6, iclass 25, count 2 2006.257.16:38:01.62#ibcon#end of sib2, iclass 25, count 2 2006.257.16:38:01.62#ibcon#*after write, iclass 25, count 2 2006.257.16:38:01.62#ibcon#*before return 0, iclass 25, count 2 2006.257.16:38:01.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:38:01.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.16:38:01.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.16:38:01.62#ibcon#ireg 7 cls_cnt 0 2006.257.16:38:01.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:38:01.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:38:01.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:38:01.74#ibcon#enter wrdev, iclass 25, count 0 2006.257.16:38:01.74#ibcon#first serial, iclass 25, count 0 2006.257.16:38:01.74#ibcon#enter sib2, iclass 25, count 0 2006.257.16:38:01.74#ibcon#flushed, iclass 25, count 0 2006.257.16:38:01.74#ibcon#about to write, iclass 25, count 0 2006.257.16:38:01.74#ibcon#wrote, iclass 25, count 0 2006.257.16:38:01.74#ibcon#about to read 3, iclass 25, count 0 2006.257.16:38:01.76#ibcon#read 3, iclass 25, count 0 2006.257.16:38:01.76#ibcon#about to read 4, iclass 25, count 0 2006.257.16:38:01.76#ibcon#read 4, iclass 25, count 0 2006.257.16:38:01.76#ibcon#about to read 5, iclass 25, count 0 2006.257.16:38:01.76#ibcon#read 5, iclass 25, count 0 2006.257.16:38:01.76#ibcon#about to read 6, iclass 25, count 0 2006.257.16:38:01.76#ibcon#read 6, iclass 25, count 0 2006.257.16:38:01.76#ibcon#end of sib2, iclass 25, count 0 2006.257.16:38:01.76#ibcon#*mode == 0, iclass 25, count 0 2006.257.16:38:01.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.16:38:01.76#ibcon#[27=USB\r\n] 2006.257.16:38:01.76#ibcon#*before write, iclass 25, count 0 2006.257.16:38:01.76#ibcon#enter sib2, iclass 25, count 0 2006.257.16:38:01.76#ibcon#flushed, iclass 25, count 0 2006.257.16:38:01.76#ibcon#about to write, iclass 25, count 0 2006.257.16:38:01.76#ibcon#wrote, iclass 25, count 0 2006.257.16:38:01.76#ibcon#about to read 3, iclass 25, count 0 2006.257.16:38:01.79#ibcon#read 3, iclass 25, count 0 2006.257.16:38:01.79#ibcon#about to read 4, iclass 25, count 0 2006.257.16:38:01.79#ibcon#read 4, iclass 25, count 0 2006.257.16:38:01.79#ibcon#about to read 5, iclass 25, count 0 2006.257.16:38:01.79#ibcon#read 5, iclass 25, count 0 2006.257.16:38:01.79#ibcon#about to read 6, iclass 25, count 0 2006.257.16:38:01.79#ibcon#read 6, iclass 25, count 0 2006.257.16:38:01.79#ibcon#end of sib2, iclass 25, count 0 2006.257.16:38:01.79#ibcon#*after write, iclass 25, count 0 2006.257.16:38:01.79#ibcon#*before return 0, iclass 25, count 0 2006.257.16:38:01.79#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:38:01.79#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.16:38:01.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.16:38:01.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.16:38:01.79$vck44/vblo=6,719.99 2006.257.16:38:01.79#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.16:38:01.79#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.16:38:01.79#ibcon#ireg 17 cls_cnt 0 2006.257.16:38:01.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:38:01.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:38:01.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:38:01.79#ibcon#enter wrdev, iclass 27, count 0 2006.257.16:38:01.79#ibcon#first serial, iclass 27, count 0 2006.257.16:38:01.79#ibcon#enter sib2, iclass 27, count 0 2006.257.16:38:01.79#ibcon#flushed, iclass 27, count 0 2006.257.16:38:01.79#ibcon#about to write, iclass 27, count 0 2006.257.16:38:01.79#ibcon#wrote, iclass 27, count 0 2006.257.16:38:01.79#ibcon#about to read 3, iclass 27, count 0 2006.257.16:38:01.81#ibcon#read 3, iclass 27, count 0 2006.257.16:38:01.81#ibcon#about to read 4, iclass 27, count 0 2006.257.16:38:01.81#ibcon#read 4, iclass 27, count 0 2006.257.16:38:01.81#ibcon#about to read 5, iclass 27, count 0 2006.257.16:38:01.81#ibcon#read 5, iclass 27, count 0 2006.257.16:38:01.81#ibcon#about to read 6, iclass 27, count 0 2006.257.16:38:01.81#ibcon#read 6, iclass 27, count 0 2006.257.16:38:01.81#ibcon#end of sib2, iclass 27, count 0 2006.257.16:38:01.81#ibcon#*mode == 0, iclass 27, count 0 2006.257.16:38:01.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.16:38:01.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:38:01.81#ibcon#*before write, iclass 27, count 0 2006.257.16:38:01.81#ibcon#enter sib2, iclass 27, count 0 2006.257.16:38:01.81#ibcon#flushed, iclass 27, count 0 2006.257.16:38:01.81#ibcon#about to write, iclass 27, count 0 2006.257.16:38:01.81#ibcon#wrote, iclass 27, count 0 2006.257.16:38:01.81#ibcon#about to read 3, iclass 27, count 0 2006.257.16:38:01.85#ibcon#read 3, iclass 27, count 0 2006.257.16:38:01.85#ibcon#about to read 4, iclass 27, count 0 2006.257.16:38:01.85#ibcon#read 4, iclass 27, count 0 2006.257.16:38:01.85#ibcon#about to read 5, iclass 27, count 0 2006.257.16:38:01.85#ibcon#read 5, iclass 27, count 0 2006.257.16:38:01.85#ibcon#about to read 6, iclass 27, count 0 2006.257.16:38:01.85#ibcon#read 6, iclass 27, count 0 2006.257.16:38:01.85#ibcon#end of sib2, iclass 27, count 0 2006.257.16:38:01.85#ibcon#*after write, iclass 27, count 0 2006.257.16:38:01.85#ibcon#*before return 0, iclass 27, count 0 2006.257.16:38:01.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:38:01.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.16:38:01.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.16:38:01.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.16:38:01.85$vck44/vb=6,4 2006.257.16:38:01.85#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.16:38:01.85#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.16:38:01.85#ibcon#ireg 11 cls_cnt 2 2006.257.16:38:01.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:38:01.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:38:01.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:38:01.91#ibcon#enter wrdev, iclass 29, count 2 2006.257.16:38:01.91#ibcon#first serial, iclass 29, count 2 2006.257.16:38:01.91#ibcon#enter sib2, iclass 29, count 2 2006.257.16:38:01.91#ibcon#flushed, iclass 29, count 2 2006.257.16:38:01.91#ibcon#about to write, iclass 29, count 2 2006.257.16:38:01.91#ibcon#wrote, iclass 29, count 2 2006.257.16:38:01.91#ibcon#about to read 3, iclass 29, count 2 2006.257.16:38:01.93#ibcon#read 3, iclass 29, count 2 2006.257.16:38:01.93#ibcon#about to read 4, iclass 29, count 2 2006.257.16:38:01.93#ibcon#read 4, iclass 29, count 2 2006.257.16:38:01.93#ibcon#about to read 5, iclass 29, count 2 2006.257.16:38:01.93#ibcon#read 5, iclass 29, count 2 2006.257.16:38:01.93#ibcon#about to read 6, iclass 29, count 2 2006.257.16:38:01.93#ibcon#read 6, iclass 29, count 2 2006.257.16:38:01.93#ibcon#end of sib2, iclass 29, count 2 2006.257.16:38:01.93#ibcon#*mode == 0, iclass 29, count 2 2006.257.16:38:01.93#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.16:38:01.93#ibcon#[27=AT06-04\r\n] 2006.257.16:38:01.93#ibcon#*before write, iclass 29, count 2 2006.257.16:38:01.93#ibcon#enter sib2, iclass 29, count 2 2006.257.16:38:01.93#ibcon#flushed, iclass 29, count 2 2006.257.16:38:01.93#ibcon#about to write, iclass 29, count 2 2006.257.16:38:01.93#ibcon#wrote, iclass 29, count 2 2006.257.16:38:01.93#ibcon#about to read 3, iclass 29, count 2 2006.257.16:38:01.96#ibcon#read 3, iclass 29, count 2 2006.257.16:38:01.96#ibcon#about to read 4, iclass 29, count 2 2006.257.16:38:01.96#ibcon#read 4, iclass 29, count 2 2006.257.16:38:01.96#ibcon#about to read 5, iclass 29, count 2 2006.257.16:38:01.96#ibcon#read 5, iclass 29, count 2 2006.257.16:38:01.96#ibcon#about to read 6, iclass 29, count 2 2006.257.16:38:01.96#ibcon#read 6, iclass 29, count 2 2006.257.16:38:01.96#ibcon#end of sib2, iclass 29, count 2 2006.257.16:38:01.96#ibcon#*after write, iclass 29, count 2 2006.257.16:38:01.96#ibcon#*before return 0, iclass 29, count 2 2006.257.16:38:01.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:38:01.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.16:38:01.96#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.16:38:01.96#ibcon#ireg 7 cls_cnt 0 2006.257.16:38:01.96#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:38:02.08#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:38:02.08#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:38:02.08#ibcon#enter wrdev, iclass 29, count 0 2006.257.16:38:02.08#ibcon#first serial, iclass 29, count 0 2006.257.16:38:02.08#ibcon#enter sib2, iclass 29, count 0 2006.257.16:38:02.08#ibcon#flushed, iclass 29, count 0 2006.257.16:38:02.08#ibcon#about to write, iclass 29, count 0 2006.257.16:38:02.08#ibcon#wrote, iclass 29, count 0 2006.257.16:38:02.08#ibcon#about to read 3, iclass 29, count 0 2006.257.16:38:02.10#ibcon#read 3, iclass 29, count 0 2006.257.16:38:02.10#ibcon#about to read 4, iclass 29, count 0 2006.257.16:38:02.10#ibcon#read 4, iclass 29, count 0 2006.257.16:38:02.10#ibcon#about to read 5, iclass 29, count 0 2006.257.16:38:02.10#ibcon#read 5, iclass 29, count 0 2006.257.16:38:02.10#ibcon#about to read 6, iclass 29, count 0 2006.257.16:38:02.10#ibcon#read 6, iclass 29, count 0 2006.257.16:38:02.10#ibcon#end of sib2, iclass 29, count 0 2006.257.16:38:02.10#ibcon#*mode == 0, iclass 29, count 0 2006.257.16:38:02.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.16:38:02.10#ibcon#[27=USB\r\n] 2006.257.16:38:02.10#ibcon#*before write, iclass 29, count 0 2006.257.16:38:02.10#ibcon#enter sib2, iclass 29, count 0 2006.257.16:38:02.10#ibcon#flushed, iclass 29, count 0 2006.257.16:38:02.10#ibcon#about to write, iclass 29, count 0 2006.257.16:38:02.10#ibcon#wrote, iclass 29, count 0 2006.257.16:38:02.10#ibcon#about to read 3, iclass 29, count 0 2006.257.16:38:02.13#ibcon#read 3, iclass 29, count 0 2006.257.16:38:02.13#ibcon#about to read 4, iclass 29, count 0 2006.257.16:38:02.13#ibcon#read 4, iclass 29, count 0 2006.257.16:38:02.13#ibcon#about to read 5, iclass 29, count 0 2006.257.16:38:02.13#ibcon#read 5, iclass 29, count 0 2006.257.16:38:02.13#ibcon#about to read 6, iclass 29, count 0 2006.257.16:38:02.13#ibcon#read 6, iclass 29, count 0 2006.257.16:38:02.13#ibcon#end of sib2, iclass 29, count 0 2006.257.16:38:02.13#ibcon#*after write, iclass 29, count 0 2006.257.16:38:02.13#ibcon#*before return 0, iclass 29, count 0 2006.257.16:38:02.13#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:38:02.13#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.16:38:02.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.16:38:02.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.16:38:02.13$vck44/vblo=7,734.99 2006.257.16:38:02.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.16:38:02.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.16:38:02.13#ibcon#ireg 17 cls_cnt 0 2006.257.16:38:02.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:38:02.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:38:02.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:38:02.13#ibcon#enter wrdev, iclass 31, count 0 2006.257.16:38:02.13#ibcon#first serial, iclass 31, count 0 2006.257.16:38:02.13#ibcon#enter sib2, iclass 31, count 0 2006.257.16:38:02.13#ibcon#flushed, iclass 31, count 0 2006.257.16:38:02.13#ibcon#about to write, iclass 31, count 0 2006.257.16:38:02.13#ibcon#wrote, iclass 31, count 0 2006.257.16:38:02.13#ibcon#about to read 3, iclass 31, count 0 2006.257.16:38:02.15#ibcon#read 3, iclass 31, count 0 2006.257.16:38:02.15#ibcon#about to read 4, iclass 31, count 0 2006.257.16:38:02.15#ibcon#read 4, iclass 31, count 0 2006.257.16:38:02.15#ibcon#about to read 5, iclass 31, count 0 2006.257.16:38:02.15#ibcon#read 5, iclass 31, count 0 2006.257.16:38:02.15#ibcon#about to read 6, iclass 31, count 0 2006.257.16:38:02.15#ibcon#read 6, iclass 31, count 0 2006.257.16:38:02.15#ibcon#end of sib2, iclass 31, count 0 2006.257.16:38:02.15#ibcon#*mode == 0, iclass 31, count 0 2006.257.16:38:02.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.16:38:02.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:38:02.15#ibcon#*before write, iclass 31, count 0 2006.257.16:38:02.15#ibcon#enter sib2, iclass 31, count 0 2006.257.16:38:02.15#ibcon#flushed, iclass 31, count 0 2006.257.16:38:02.15#ibcon#about to write, iclass 31, count 0 2006.257.16:38:02.15#ibcon#wrote, iclass 31, count 0 2006.257.16:38:02.15#ibcon#about to read 3, iclass 31, count 0 2006.257.16:38:02.19#ibcon#read 3, iclass 31, count 0 2006.257.16:38:02.19#ibcon#about to read 4, iclass 31, count 0 2006.257.16:38:02.19#ibcon#read 4, iclass 31, count 0 2006.257.16:38:02.19#ibcon#about to read 5, iclass 31, count 0 2006.257.16:38:02.19#ibcon#read 5, iclass 31, count 0 2006.257.16:38:02.19#ibcon#about to read 6, iclass 31, count 0 2006.257.16:38:02.19#ibcon#read 6, iclass 31, count 0 2006.257.16:38:02.19#ibcon#end of sib2, iclass 31, count 0 2006.257.16:38:02.19#ibcon#*after write, iclass 31, count 0 2006.257.16:38:02.19#ibcon#*before return 0, iclass 31, count 0 2006.257.16:38:02.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:38:02.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.16:38:02.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.16:38:02.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.16:38:02.19$vck44/vb=7,4 2006.257.16:38:02.19#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.16:38:02.19#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.16:38:02.19#ibcon#ireg 11 cls_cnt 2 2006.257.16:38:02.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:38:02.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:38:02.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:38:02.25#ibcon#enter wrdev, iclass 33, count 2 2006.257.16:38:02.25#ibcon#first serial, iclass 33, count 2 2006.257.16:38:02.25#ibcon#enter sib2, iclass 33, count 2 2006.257.16:38:02.25#ibcon#flushed, iclass 33, count 2 2006.257.16:38:02.25#ibcon#about to write, iclass 33, count 2 2006.257.16:38:02.25#ibcon#wrote, iclass 33, count 2 2006.257.16:38:02.25#ibcon#about to read 3, iclass 33, count 2 2006.257.16:38:02.27#ibcon#read 3, iclass 33, count 2 2006.257.16:38:02.27#ibcon#about to read 4, iclass 33, count 2 2006.257.16:38:02.27#ibcon#read 4, iclass 33, count 2 2006.257.16:38:02.27#ibcon#about to read 5, iclass 33, count 2 2006.257.16:38:02.27#ibcon#read 5, iclass 33, count 2 2006.257.16:38:02.27#ibcon#about to read 6, iclass 33, count 2 2006.257.16:38:02.27#ibcon#read 6, iclass 33, count 2 2006.257.16:38:02.27#ibcon#end of sib2, iclass 33, count 2 2006.257.16:38:02.27#ibcon#*mode == 0, iclass 33, count 2 2006.257.16:38:02.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.16:38:02.27#ibcon#[27=AT07-04\r\n] 2006.257.16:38:02.27#ibcon#*before write, iclass 33, count 2 2006.257.16:38:02.27#ibcon#enter sib2, iclass 33, count 2 2006.257.16:38:02.27#ibcon#flushed, iclass 33, count 2 2006.257.16:38:02.27#ibcon#about to write, iclass 33, count 2 2006.257.16:38:02.27#ibcon#wrote, iclass 33, count 2 2006.257.16:38:02.27#ibcon#about to read 3, iclass 33, count 2 2006.257.16:38:02.30#ibcon#read 3, iclass 33, count 2 2006.257.16:38:02.30#ibcon#about to read 4, iclass 33, count 2 2006.257.16:38:02.30#ibcon#read 4, iclass 33, count 2 2006.257.16:38:02.30#ibcon#about to read 5, iclass 33, count 2 2006.257.16:38:02.30#ibcon#read 5, iclass 33, count 2 2006.257.16:38:02.30#ibcon#about to read 6, iclass 33, count 2 2006.257.16:38:02.30#ibcon#read 6, iclass 33, count 2 2006.257.16:38:02.30#ibcon#end of sib2, iclass 33, count 2 2006.257.16:38:02.30#ibcon#*after write, iclass 33, count 2 2006.257.16:38:02.30#ibcon#*before return 0, iclass 33, count 2 2006.257.16:38:02.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:38:02.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.16:38:02.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.16:38:02.30#ibcon#ireg 7 cls_cnt 0 2006.257.16:38:02.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:38:02.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:38:02.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:38:02.42#ibcon#enter wrdev, iclass 33, count 0 2006.257.16:38:02.42#ibcon#first serial, iclass 33, count 0 2006.257.16:38:02.42#ibcon#enter sib2, iclass 33, count 0 2006.257.16:38:02.42#ibcon#flushed, iclass 33, count 0 2006.257.16:38:02.42#ibcon#about to write, iclass 33, count 0 2006.257.16:38:02.42#ibcon#wrote, iclass 33, count 0 2006.257.16:38:02.42#ibcon#about to read 3, iclass 33, count 0 2006.257.16:38:02.44#ibcon#read 3, iclass 33, count 0 2006.257.16:38:02.44#ibcon#about to read 4, iclass 33, count 0 2006.257.16:38:02.44#ibcon#read 4, iclass 33, count 0 2006.257.16:38:02.44#ibcon#about to read 5, iclass 33, count 0 2006.257.16:38:02.44#ibcon#read 5, iclass 33, count 0 2006.257.16:38:02.44#ibcon#about to read 6, iclass 33, count 0 2006.257.16:38:02.44#ibcon#read 6, iclass 33, count 0 2006.257.16:38:02.44#ibcon#end of sib2, iclass 33, count 0 2006.257.16:38:02.44#ibcon#*mode == 0, iclass 33, count 0 2006.257.16:38:02.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.16:38:02.44#ibcon#[27=USB\r\n] 2006.257.16:38:02.44#ibcon#*before write, iclass 33, count 0 2006.257.16:38:02.44#ibcon#enter sib2, iclass 33, count 0 2006.257.16:38:02.44#ibcon#flushed, iclass 33, count 0 2006.257.16:38:02.44#ibcon#about to write, iclass 33, count 0 2006.257.16:38:02.44#ibcon#wrote, iclass 33, count 0 2006.257.16:38:02.44#ibcon#about to read 3, iclass 33, count 0 2006.257.16:38:02.47#ibcon#read 3, iclass 33, count 0 2006.257.16:38:02.47#ibcon#about to read 4, iclass 33, count 0 2006.257.16:38:02.47#ibcon#read 4, iclass 33, count 0 2006.257.16:38:02.47#ibcon#about to read 5, iclass 33, count 0 2006.257.16:38:02.47#ibcon#read 5, iclass 33, count 0 2006.257.16:38:02.47#ibcon#about to read 6, iclass 33, count 0 2006.257.16:38:02.47#ibcon#read 6, iclass 33, count 0 2006.257.16:38:02.47#ibcon#end of sib2, iclass 33, count 0 2006.257.16:38:02.47#ibcon#*after write, iclass 33, count 0 2006.257.16:38:02.47#ibcon#*before return 0, iclass 33, count 0 2006.257.16:38:02.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:38:02.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.16:38:02.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.16:38:02.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.16:38:02.47$vck44/vblo=8,744.99 2006.257.16:38:02.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.16:38:02.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.16:38:02.47#ibcon#ireg 17 cls_cnt 0 2006.257.16:38:02.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:38:02.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:38:02.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:38:02.47#ibcon#enter wrdev, iclass 35, count 0 2006.257.16:38:02.47#ibcon#first serial, iclass 35, count 0 2006.257.16:38:02.47#ibcon#enter sib2, iclass 35, count 0 2006.257.16:38:02.47#ibcon#flushed, iclass 35, count 0 2006.257.16:38:02.47#ibcon#about to write, iclass 35, count 0 2006.257.16:38:02.47#ibcon#wrote, iclass 35, count 0 2006.257.16:38:02.47#ibcon#about to read 3, iclass 35, count 0 2006.257.16:38:02.49#ibcon#read 3, iclass 35, count 0 2006.257.16:38:02.49#ibcon#about to read 4, iclass 35, count 0 2006.257.16:38:02.49#ibcon#read 4, iclass 35, count 0 2006.257.16:38:02.49#ibcon#about to read 5, iclass 35, count 0 2006.257.16:38:02.49#ibcon#read 5, iclass 35, count 0 2006.257.16:38:02.49#ibcon#about to read 6, iclass 35, count 0 2006.257.16:38:02.49#ibcon#read 6, iclass 35, count 0 2006.257.16:38:02.49#ibcon#end of sib2, iclass 35, count 0 2006.257.16:38:02.49#ibcon#*mode == 0, iclass 35, count 0 2006.257.16:38:02.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.16:38:02.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:38:02.49#ibcon#*before write, iclass 35, count 0 2006.257.16:38:02.49#ibcon#enter sib2, iclass 35, count 0 2006.257.16:38:02.49#ibcon#flushed, iclass 35, count 0 2006.257.16:38:02.49#ibcon#about to write, iclass 35, count 0 2006.257.16:38:02.49#ibcon#wrote, iclass 35, count 0 2006.257.16:38:02.49#ibcon#about to read 3, iclass 35, count 0 2006.257.16:38:02.53#ibcon#read 3, iclass 35, count 0 2006.257.16:38:02.53#ibcon#about to read 4, iclass 35, count 0 2006.257.16:38:02.53#ibcon#read 4, iclass 35, count 0 2006.257.16:38:02.53#ibcon#about to read 5, iclass 35, count 0 2006.257.16:38:02.53#ibcon#read 5, iclass 35, count 0 2006.257.16:38:02.53#ibcon#about to read 6, iclass 35, count 0 2006.257.16:38:02.53#ibcon#read 6, iclass 35, count 0 2006.257.16:38:02.53#ibcon#end of sib2, iclass 35, count 0 2006.257.16:38:02.53#ibcon#*after write, iclass 35, count 0 2006.257.16:38:02.53#ibcon#*before return 0, iclass 35, count 0 2006.257.16:38:02.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:38:02.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.16:38:02.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.16:38:02.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.16:38:02.53$vck44/vb=8,4 2006.257.16:38:02.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.16:38:02.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.16:38:02.53#ibcon#ireg 11 cls_cnt 2 2006.257.16:38:02.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:38:02.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:38:02.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:38:02.59#ibcon#enter wrdev, iclass 37, count 2 2006.257.16:38:02.59#ibcon#first serial, iclass 37, count 2 2006.257.16:38:02.59#ibcon#enter sib2, iclass 37, count 2 2006.257.16:38:02.59#ibcon#flushed, iclass 37, count 2 2006.257.16:38:02.59#ibcon#about to write, iclass 37, count 2 2006.257.16:38:02.59#ibcon#wrote, iclass 37, count 2 2006.257.16:38:02.59#ibcon#about to read 3, iclass 37, count 2 2006.257.16:38:02.61#ibcon#read 3, iclass 37, count 2 2006.257.16:38:02.61#ibcon#about to read 4, iclass 37, count 2 2006.257.16:38:02.61#ibcon#read 4, iclass 37, count 2 2006.257.16:38:02.61#ibcon#about to read 5, iclass 37, count 2 2006.257.16:38:02.61#ibcon#read 5, iclass 37, count 2 2006.257.16:38:02.61#ibcon#about to read 6, iclass 37, count 2 2006.257.16:38:02.61#ibcon#read 6, iclass 37, count 2 2006.257.16:38:02.61#ibcon#end of sib2, iclass 37, count 2 2006.257.16:38:02.61#ibcon#*mode == 0, iclass 37, count 2 2006.257.16:38:02.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.16:38:02.61#ibcon#[27=AT08-04\r\n] 2006.257.16:38:02.61#ibcon#*before write, iclass 37, count 2 2006.257.16:38:02.61#ibcon#enter sib2, iclass 37, count 2 2006.257.16:38:02.61#ibcon#flushed, iclass 37, count 2 2006.257.16:38:02.61#ibcon#about to write, iclass 37, count 2 2006.257.16:38:02.61#ibcon#wrote, iclass 37, count 2 2006.257.16:38:02.61#ibcon#about to read 3, iclass 37, count 2 2006.257.16:38:02.64#ibcon#read 3, iclass 37, count 2 2006.257.16:38:02.64#ibcon#about to read 4, iclass 37, count 2 2006.257.16:38:02.64#ibcon#read 4, iclass 37, count 2 2006.257.16:38:02.64#ibcon#about to read 5, iclass 37, count 2 2006.257.16:38:02.64#ibcon#read 5, iclass 37, count 2 2006.257.16:38:02.64#ibcon#about to read 6, iclass 37, count 2 2006.257.16:38:02.64#ibcon#read 6, iclass 37, count 2 2006.257.16:38:02.64#ibcon#end of sib2, iclass 37, count 2 2006.257.16:38:02.64#ibcon#*after write, iclass 37, count 2 2006.257.16:38:02.64#ibcon#*before return 0, iclass 37, count 2 2006.257.16:38:02.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:38:02.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.16:38:02.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.16:38:02.64#ibcon#ireg 7 cls_cnt 0 2006.257.16:38:02.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:38:02.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:38:02.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:38:02.76#ibcon#enter wrdev, iclass 37, count 0 2006.257.16:38:02.76#ibcon#first serial, iclass 37, count 0 2006.257.16:38:02.76#ibcon#enter sib2, iclass 37, count 0 2006.257.16:38:02.76#ibcon#flushed, iclass 37, count 0 2006.257.16:38:02.76#ibcon#about to write, iclass 37, count 0 2006.257.16:38:02.76#ibcon#wrote, iclass 37, count 0 2006.257.16:38:02.76#ibcon#about to read 3, iclass 37, count 0 2006.257.16:38:02.78#ibcon#read 3, iclass 37, count 0 2006.257.16:38:02.78#ibcon#about to read 4, iclass 37, count 0 2006.257.16:38:02.78#ibcon#read 4, iclass 37, count 0 2006.257.16:38:02.78#ibcon#about to read 5, iclass 37, count 0 2006.257.16:38:02.78#ibcon#read 5, iclass 37, count 0 2006.257.16:38:02.78#ibcon#about to read 6, iclass 37, count 0 2006.257.16:38:02.78#ibcon#read 6, iclass 37, count 0 2006.257.16:38:02.78#ibcon#end of sib2, iclass 37, count 0 2006.257.16:38:02.78#ibcon#*mode == 0, iclass 37, count 0 2006.257.16:38:02.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.16:38:02.78#ibcon#[27=USB\r\n] 2006.257.16:38:02.78#ibcon#*before write, iclass 37, count 0 2006.257.16:38:02.78#ibcon#enter sib2, iclass 37, count 0 2006.257.16:38:02.78#ibcon#flushed, iclass 37, count 0 2006.257.16:38:02.78#ibcon#about to write, iclass 37, count 0 2006.257.16:38:02.78#ibcon#wrote, iclass 37, count 0 2006.257.16:38:02.78#ibcon#about to read 3, iclass 37, count 0 2006.257.16:38:02.81#ibcon#read 3, iclass 37, count 0 2006.257.16:38:02.81#ibcon#about to read 4, iclass 37, count 0 2006.257.16:38:02.81#ibcon#read 4, iclass 37, count 0 2006.257.16:38:02.81#ibcon#about to read 5, iclass 37, count 0 2006.257.16:38:02.81#ibcon#read 5, iclass 37, count 0 2006.257.16:38:02.81#ibcon#about to read 6, iclass 37, count 0 2006.257.16:38:02.81#ibcon#read 6, iclass 37, count 0 2006.257.16:38:02.81#ibcon#end of sib2, iclass 37, count 0 2006.257.16:38:02.81#ibcon#*after write, iclass 37, count 0 2006.257.16:38:02.81#ibcon#*before return 0, iclass 37, count 0 2006.257.16:38:02.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:38:02.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.16:38:02.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.16:38:02.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.16:38:02.81$vck44/vabw=wide 2006.257.16:38:02.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.16:38:02.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.16:38:02.81#ibcon#ireg 8 cls_cnt 0 2006.257.16:38:02.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:38:02.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:38:02.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:38:02.81#ibcon#enter wrdev, iclass 39, count 0 2006.257.16:38:02.81#ibcon#first serial, iclass 39, count 0 2006.257.16:38:02.81#ibcon#enter sib2, iclass 39, count 0 2006.257.16:38:02.81#ibcon#flushed, iclass 39, count 0 2006.257.16:38:02.81#ibcon#about to write, iclass 39, count 0 2006.257.16:38:02.81#ibcon#wrote, iclass 39, count 0 2006.257.16:38:02.81#ibcon#about to read 3, iclass 39, count 0 2006.257.16:38:02.83#ibcon#read 3, iclass 39, count 0 2006.257.16:38:02.83#ibcon#about to read 4, iclass 39, count 0 2006.257.16:38:02.83#ibcon#read 4, iclass 39, count 0 2006.257.16:38:02.83#ibcon#about to read 5, iclass 39, count 0 2006.257.16:38:02.83#ibcon#read 5, iclass 39, count 0 2006.257.16:38:02.83#ibcon#about to read 6, iclass 39, count 0 2006.257.16:38:02.83#ibcon#read 6, iclass 39, count 0 2006.257.16:38:02.83#ibcon#end of sib2, iclass 39, count 0 2006.257.16:38:02.83#ibcon#*mode == 0, iclass 39, count 0 2006.257.16:38:02.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.16:38:02.83#ibcon#[25=BW32\r\n] 2006.257.16:38:02.83#ibcon#*before write, iclass 39, count 0 2006.257.16:38:02.83#ibcon#enter sib2, iclass 39, count 0 2006.257.16:38:02.83#ibcon#flushed, iclass 39, count 0 2006.257.16:38:02.83#ibcon#about to write, iclass 39, count 0 2006.257.16:38:02.83#ibcon#wrote, iclass 39, count 0 2006.257.16:38:02.83#ibcon#about to read 3, iclass 39, count 0 2006.257.16:38:02.86#ibcon#read 3, iclass 39, count 0 2006.257.16:38:02.86#ibcon#about to read 4, iclass 39, count 0 2006.257.16:38:02.86#ibcon#read 4, iclass 39, count 0 2006.257.16:38:02.86#ibcon#about to read 5, iclass 39, count 0 2006.257.16:38:02.86#ibcon#read 5, iclass 39, count 0 2006.257.16:38:02.86#ibcon#about to read 6, iclass 39, count 0 2006.257.16:38:02.86#ibcon#read 6, iclass 39, count 0 2006.257.16:38:02.86#ibcon#end of sib2, iclass 39, count 0 2006.257.16:38:02.86#ibcon#*after write, iclass 39, count 0 2006.257.16:38:02.86#ibcon#*before return 0, iclass 39, count 0 2006.257.16:38:02.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:38:02.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.16:38:02.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.16:38:02.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.16:38:02.86$vck44/vbbw=wide 2006.257.16:38:02.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.16:38:02.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.16:38:02.86#ibcon#ireg 8 cls_cnt 0 2006.257.16:38:02.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:38:02.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:38:02.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:38:02.93#ibcon#enter wrdev, iclass 3, count 0 2006.257.16:38:02.93#ibcon#first serial, iclass 3, count 0 2006.257.16:38:02.93#ibcon#enter sib2, iclass 3, count 0 2006.257.16:38:02.93#ibcon#flushed, iclass 3, count 0 2006.257.16:38:02.93#ibcon#about to write, iclass 3, count 0 2006.257.16:38:02.93#ibcon#wrote, iclass 3, count 0 2006.257.16:38:02.93#ibcon#about to read 3, iclass 3, count 0 2006.257.16:38:02.95#ibcon#read 3, iclass 3, count 0 2006.257.16:38:02.95#ibcon#about to read 4, iclass 3, count 0 2006.257.16:38:02.95#ibcon#read 4, iclass 3, count 0 2006.257.16:38:02.95#ibcon#about to read 5, iclass 3, count 0 2006.257.16:38:02.95#ibcon#read 5, iclass 3, count 0 2006.257.16:38:02.95#ibcon#about to read 6, iclass 3, count 0 2006.257.16:38:02.95#ibcon#read 6, iclass 3, count 0 2006.257.16:38:02.95#ibcon#end of sib2, iclass 3, count 0 2006.257.16:38:02.95#ibcon#*mode == 0, iclass 3, count 0 2006.257.16:38:02.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.16:38:02.95#ibcon#[27=BW32\r\n] 2006.257.16:38:02.95#ibcon#*before write, iclass 3, count 0 2006.257.16:38:02.95#ibcon#enter sib2, iclass 3, count 0 2006.257.16:38:02.95#ibcon#flushed, iclass 3, count 0 2006.257.16:38:02.95#ibcon#about to write, iclass 3, count 0 2006.257.16:38:02.95#ibcon#wrote, iclass 3, count 0 2006.257.16:38:02.95#ibcon#about to read 3, iclass 3, count 0 2006.257.16:38:02.98#ibcon#read 3, iclass 3, count 0 2006.257.16:38:02.98#ibcon#about to read 4, iclass 3, count 0 2006.257.16:38:02.98#ibcon#read 4, iclass 3, count 0 2006.257.16:38:02.98#ibcon#about to read 5, iclass 3, count 0 2006.257.16:38:02.98#ibcon#read 5, iclass 3, count 0 2006.257.16:38:02.98#ibcon#about to read 6, iclass 3, count 0 2006.257.16:38:02.98#ibcon#read 6, iclass 3, count 0 2006.257.16:38:02.98#ibcon#end of sib2, iclass 3, count 0 2006.257.16:38:02.98#ibcon#*after write, iclass 3, count 0 2006.257.16:38:02.98#ibcon#*before return 0, iclass 3, count 0 2006.257.16:38:02.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:38:02.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:38:02.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.16:38:02.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.16:38:02.98$setupk4/ifdk4 2006.257.16:38:02.98$ifdk4/lo= 2006.257.16:38:02.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:38:02.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:38:02.98$ifdk4/patch= 2006.257.16:38:02.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:38:02.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:38:02.98$setupk4/!*+20s 2006.257.16:38:08.28#abcon#<5=/14 1.8 4.8 17.20 971014.1\r\n> 2006.257.16:38:08.30#abcon#{5=INTERFACE CLEAR} 2006.257.16:38:08.36#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:38:17.49$setupk4/"tpicd 2006.257.16:38:17.49$setupk4/echo=off 2006.257.16:38:17.49$setupk4/xlog=off 2006.257.16:38:17.49:!2006.257.16:42:51 2006.257.16:38:28.14#trakl#Source acquired 2006.257.16:38:29.14#flagr#flagr/antenna,acquired 2006.257.16:42:51.00:preob 2006.257.16:42:51.14/onsource/TRACKING 2006.257.16:42:51.14:!2006.257.16:43:01 2006.257.16:43:01.00:"tape 2006.257.16:43:01.00:"st=record 2006.257.16:43:01.00:data_valid=on 2006.257.16:43:01.00:midob 2006.257.16:43:02.14/onsource/TRACKING 2006.257.16:43:02.14/wx/17.28,1014.1,96 2006.257.16:43:02.20/cable/+6.4842E-03 2006.257.16:43:03.29/va/01,08,usb,yes,31,33 2006.257.16:43:03.29/va/02,07,usb,yes,33,34 2006.257.16:43:03.29/va/03,08,usb,yes,30,32 2006.257.16:43:03.29/va/04,07,usb,yes,34,36 2006.257.16:43:03.29/va/05,04,usb,yes,31,31 2006.257.16:43:03.29/va/06,04,usb,yes,34,34 2006.257.16:43:03.29/va/07,04,usb,yes,35,35 2006.257.16:43:03.29/va/08,04,usb,yes,29,36 2006.257.16:43:03.52/valo/01,524.99,yes,locked 2006.257.16:43:03.52/valo/02,534.99,yes,locked 2006.257.16:43:03.52/valo/03,564.99,yes,locked 2006.257.16:43:03.52/valo/04,624.99,yes,locked 2006.257.16:43:03.52/valo/05,734.99,yes,locked 2006.257.16:43:03.52/valo/06,814.99,yes,locked 2006.257.16:43:03.52/valo/07,864.99,yes,locked 2006.257.16:43:03.52/valo/08,884.99,yes,locked 2006.257.16:43:04.61/vb/01,04,usb,yes,30,28 2006.257.16:43:04.61/vb/02,05,usb,yes,29,29 2006.257.16:43:04.61/vb/03,04,usb,yes,30,33 2006.257.16:43:04.61/vb/04,05,usb,yes,30,29 2006.257.16:43:04.61/vb/05,04,usb,yes,27,29 2006.257.16:43:04.61/vb/06,04,usb,yes,31,27 2006.257.16:43:04.61/vb/07,04,usb,yes,31,31 2006.257.16:43:04.61/vb/08,04,usb,yes,28,32 2006.257.16:43:04.84/vblo/01,629.99,yes,locked 2006.257.16:43:04.84/vblo/02,634.99,yes,locked 2006.257.16:43:04.84/vblo/03,649.99,yes,locked 2006.257.16:43:04.84/vblo/04,679.99,yes,locked 2006.257.16:43:04.84/vblo/05,709.99,yes,locked 2006.257.16:43:04.84/vblo/06,719.99,yes,locked 2006.257.16:43:04.84/vblo/07,734.99,yes,locked 2006.257.16:43:04.84/vblo/08,744.99,yes,locked 2006.257.16:43:04.99/vabw/8 2006.257.16:43:05.14/vbbw/8 2006.257.16:43:05.23/xfe/off,on,15.0 2006.257.16:43:05.63/ifatt/23,28,28,28 2006.257.16:43:06.08/fmout-gps/S +4.61E-07 2006.257.16:43:06.12:!2006.257.16:44:51 2006.257.16:44:51.00:data_valid=off 2006.257.16:44:51.00:"et 2006.257.16:44:51.00:!+3s 2006.257.16:44:54.01:"tape 2006.257.16:44:54.01:postob 2006.257.16:44:54.08/cable/+6.4852E-03 2006.257.16:44:54.08/wx/17.29,1014.1,96 2006.257.16:44:55.08/fmout-gps/S +4.61E-07 2006.257.16:44:55.08:scan_name=257-1647,jd0609,90 2006.257.16:44:55.08:source=2121+053,212344.52,053522.1,2000.0,cw 2006.257.16:44:56.13#flagr#flagr/antenna,new-source 2006.257.16:44:56.13:checkk5 2006.257.16:44:56.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.16:44:56.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.16:44:57.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.16:44:57.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.16:44:57.83/chk_obsdata//k5ts1/T2571643??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.257.16:44:58.17/chk_obsdata//k5ts2/T2571643??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.257.16:44:58.50/chk_obsdata//k5ts3/T2571643??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.257.16:44:58.84/chk_obsdata//k5ts4/T2571643??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.257.16:44:59.50/k5log//k5ts1_log_newline 2006.257.16:45:00.15/k5log//k5ts2_log_newline 2006.257.16:45:00.81/k5log//k5ts3_log_newline 2006.257.16:45:01.48/k5log//k5ts4_log_newline 2006.257.16:45:01.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.16:45:01.50:setupk4=1 2006.257.16:45:01.50$setupk4/echo=on 2006.257.16:45:01.50$setupk4/pcalon 2006.257.16:45:01.50$pcalon/"no phase cal control is implemented here 2006.257.16:45:01.50$setupk4/"tpicd=stop 2006.257.16:45:01.50$setupk4/"rec=synch_on 2006.257.16:45:01.50$setupk4/"rec_mode=128 2006.257.16:45:01.50$setupk4/!* 2006.257.16:45:01.50$setupk4/recpk4 2006.257.16:45:01.50$recpk4/recpatch= 2006.257.16:45:01.51$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.16:45:01.51$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.16:45:01.51$setupk4/vck44 2006.257.16:45:01.51$vck44/valo=1,524.99 2006.257.16:45:01.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.16:45:01.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.16:45:01.51#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:01.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:01.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:01.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:01.51#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:45:01.51#ibcon#first serial, iclass 30, count 0 2006.257.16:45:01.51#ibcon#enter sib2, iclass 30, count 0 2006.257.16:45:01.51#ibcon#flushed, iclass 30, count 0 2006.257.16:45:01.51#ibcon#about to write, iclass 30, count 0 2006.257.16:45:01.51#ibcon#wrote, iclass 30, count 0 2006.257.16:45:01.51#ibcon#about to read 3, iclass 30, count 0 2006.257.16:45:01.53#ibcon#read 3, iclass 30, count 0 2006.257.16:45:01.53#ibcon#about to read 4, iclass 30, count 0 2006.257.16:45:01.53#ibcon#read 4, iclass 30, count 0 2006.257.16:45:01.53#ibcon#about to read 5, iclass 30, count 0 2006.257.16:45:01.53#ibcon#read 5, iclass 30, count 0 2006.257.16:45:01.53#ibcon#about to read 6, iclass 30, count 0 2006.257.16:45:01.53#ibcon#read 6, iclass 30, count 0 2006.257.16:45:01.53#ibcon#end of sib2, iclass 30, count 0 2006.257.16:45:01.53#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:45:01.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:45:01.53#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.16:45:01.53#ibcon#*before write, iclass 30, count 0 2006.257.16:45:01.53#ibcon#enter sib2, iclass 30, count 0 2006.257.16:45:01.53#ibcon#flushed, iclass 30, count 0 2006.257.16:45:01.53#ibcon#about to write, iclass 30, count 0 2006.257.16:45:01.53#ibcon#wrote, iclass 30, count 0 2006.257.16:45:01.53#ibcon#about to read 3, iclass 30, count 0 2006.257.16:45:01.58#ibcon#read 3, iclass 30, count 0 2006.257.16:45:01.58#ibcon#about to read 4, iclass 30, count 0 2006.257.16:45:01.58#ibcon#read 4, iclass 30, count 0 2006.257.16:45:01.58#ibcon#about to read 5, iclass 30, count 0 2006.257.16:45:01.58#ibcon#read 5, iclass 30, count 0 2006.257.16:45:01.58#ibcon#about to read 6, iclass 30, count 0 2006.257.16:45:01.58#ibcon#read 6, iclass 30, count 0 2006.257.16:45:01.58#ibcon#end of sib2, iclass 30, count 0 2006.257.16:45:01.58#ibcon#*after write, iclass 30, count 0 2006.257.16:45:01.58#ibcon#*before return 0, iclass 30, count 0 2006.257.16:45:01.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:01.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:01.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:45:01.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:45:01.58$vck44/va=1,8 2006.257.16:45:01.58#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.16:45:01.58#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.16:45:01.58#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:01.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:01.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:01.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:01.58#ibcon#enter wrdev, iclass 32, count 2 2006.257.16:45:01.58#ibcon#first serial, iclass 32, count 2 2006.257.16:45:01.58#ibcon#enter sib2, iclass 32, count 2 2006.257.16:45:01.58#ibcon#flushed, iclass 32, count 2 2006.257.16:45:01.58#ibcon#about to write, iclass 32, count 2 2006.257.16:45:01.58#ibcon#wrote, iclass 32, count 2 2006.257.16:45:01.58#ibcon#about to read 3, iclass 32, count 2 2006.257.16:45:01.60#ibcon#read 3, iclass 32, count 2 2006.257.16:45:01.60#ibcon#about to read 4, iclass 32, count 2 2006.257.16:45:01.60#ibcon#read 4, iclass 32, count 2 2006.257.16:45:01.60#ibcon#about to read 5, iclass 32, count 2 2006.257.16:45:01.60#ibcon#read 5, iclass 32, count 2 2006.257.16:45:01.60#ibcon#about to read 6, iclass 32, count 2 2006.257.16:45:01.60#ibcon#read 6, iclass 32, count 2 2006.257.16:45:01.60#ibcon#end of sib2, iclass 32, count 2 2006.257.16:45:01.60#ibcon#*mode == 0, iclass 32, count 2 2006.257.16:45:01.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.16:45:01.60#ibcon#[25=AT01-08\r\n] 2006.257.16:45:01.60#ibcon#*before write, iclass 32, count 2 2006.257.16:45:01.60#ibcon#enter sib2, iclass 32, count 2 2006.257.16:45:01.60#ibcon#flushed, iclass 32, count 2 2006.257.16:45:01.60#ibcon#about to write, iclass 32, count 2 2006.257.16:45:01.60#ibcon#wrote, iclass 32, count 2 2006.257.16:45:01.60#ibcon#about to read 3, iclass 32, count 2 2006.257.16:45:01.63#ibcon#read 3, iclass 32, count 2 2006.257.16:45:01.63#ibcon#about to read 4, iclass 32, count 2 2006.257.16:45:01.63#ibcon#read 4, iclass 32, count 2 2006.257.16:45:01.63#ibcon#about to read 5, iclass 32, count 2 2006.257.16:45:01.63#ibcon#read 5, iclass 32, count 2 2006.257.16:45:01.63#ibcon#about to read 6, iclass 32, count 2 2006.257.16:45:01.63#ibcon#read 6, iclass 32, count 2 2006.257.16:45:01.63#ibcon#end of sib2, iclass 32, count 2 2006.257.16:45:01.63#ibcon#*after write, iclass 32, count 2 2006.257.16:45:01.63#ibcon#*before return 0, iclass 32, count 2 2006.257.16:45:01.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:01.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:01.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.16:45:01.63#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:01.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:01.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:01.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:01.75#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:45:01.75#ibcon#first serial, iclass 32, count 0 2006.257.16:45:01.75#ibcon#enter sib2, iclass 32, count 0 2006.257.16:45:01.75#ibcon#flushed, iclass 32, count 0 2006.257.16:45:01.75#ibcon#about to write, iclass 32, count 0 2006.257.16:45:01.75#ibcon#wrote, iclass 32, count 0 2006.257.16:45:01.75#ibcon#about to read 3, iclass 32, count 0 2006.257.16:45:01.77#ibcon#read 3, iclass 32, count 0 2006.257.16:45:01.77#ibcon#about to read 4, iclass 32, count 0 2006.257.16:45:01.77#ibcon#read 4, iclass 32, count 0 2006.257.16:45:01.77#ibcon#about to read 5, iclass 32, count 0 2006.257.16:45:01.77#ibcon#read 5, iclass 32, count 0 2006.257.16:45:01.77#ibcon#about to read 6, iclass 32, count 0 2006.257.16:45:01.77#ibcon#read 6, iclass 32, count 0 2006.257.16:45:01.77#ibcon#end of sib2, iclass 32, count 0 2006.257.16:45:01.77#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:45:01.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:45:01.77#ibcon#[25=USB\r\n] 2006.257.16:45:01.77#ibcon#*before write, iclass 32, count 0 2006.257.16:45:01.77#ibcon#enter sib2, iclass 32, count 0 2006.257.16:45:01.77#ibcon#flushed, iclass 32, count 0 2006.257.16:45:01.77#ibcon#about to write, iclass 32, count 0 2006.257.16:45:01.77#ibcon#wrote, iclass 32, count 0 2006.257.16:45:01.77#ibcon#about to read 3, iclass 32, count 0 2006.257.16:45:01.80#ibcon#read 3, iclass 32, count 0 2006.257.16:45:01.80#ibcon#about to read 4, iclass 32, count 0 2006.257.16:45:01.80#ibcon#read 4, iclass 32, count 0 2006.257.16:45:01.80#ibcon#about to read 5, iclass 32, count 0 2006.257.16:45:01.80#ibcon#read 5, iclass 32, count 0 2006.257.16:45:01.80#ibcon#about to read 6, iclass 32, count 0 2006.257.16:45:01.80#ibcon#read 6, iclass 32, count 0 2006.257.16:45:01.80#ibcon#end of sib2, iclass 32, count 0 2006.257.16:45:01.80#ibcon#*after write, iclass 32, count 0 2006.257.16:45:01.80#ibcon#*before return 0, iclass 32, count 0 2006.257.16:45:01.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:01.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:01.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:45:01.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:45:01.80$vck44/valo=2,534.99 2006.257.16:45:01.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.16:45:01.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.16:45:01.80#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:01.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:01.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:01.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:01.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:45:01.80#ibcon#first serial, iclass 34, count 0 2006.257.16:45:01.80#ibcon#enter sib2, iclass 34, count 0 2006.257.16:45:01.80#ibcon#flushed, iclass 34, count 0 2006.257.16:45:01.80#ibcon#about to write, iclass 34, count 0 2006.257.16:45:01.80#ibcon#wrote, iclass 34, count 0 2006.257.16:45:01.80#ibcon#about to read 3, iclass 34, count 0 2006.257.16:45:01.82#ibcon#read 3, iclass 34, count 0 2006.257.16:45:01.82#ibcon#about to read 4, iclass 34, count 0 2006.257.16:45:01.82#ibcon#read 4, iclass 34, count 0 2006.257.16:45:01.82#ibcon#about to read 5, iclass 34, count 0 2006.257.16:45:01.82#ibcon#read 5, iclass 34, count 0 2006.257.16:45:01.82#ibcon#about to read 6, iclass 34, count 0 2006.257.16:45:01.82#ibcon#read 6, iclass 34, count 0 2006.257.16:45:01.82#ibcon#end of sib2, iclass 34, count 0 2006.257.16:45:01.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:45:01.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:45:01.82#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.16:45:01.82#ibcon#*before write, iclass 34, count 0 2006.257.16:45:01.82#ibcon#enter sib2, iclass 34, count 0 2006.257.16:45:01.82#ibcon#flushed, iclass 34, count 0 2006.257.16:45:01.82#ibcon#about to write, iclass 34, count 0 2006.257.16:45:01.82#ibcon#wrote, iclass 34, count 0 2006.257.16:45:01.82#ibcon#about to read 3, iclass 34, count 0 2006.257.16:45:01.86#ibcon#read 3, iclass 34, count 0 2006.257.16:45:01.86#ibcon#about to read 4, iclass 34, count 0 2006.257.16:45:01.86#ibcon#read 4, iclass 34, count 0 2006.257.16:45:01.86#ibcon#about to read 5, iclass 34, count 0 2006.257.16:45:01.86#ibcon#read 5, iclass 34, count 0 2006.257.16:45:01.86#ibcon#about to read 6, iclass 34, count 0 2006.257.16:45:01.86#ibcon#read 6, iclass 34, count 0 2006.257.16:45:01.86#ibcon#end of sib2, iclass 34, count 0 2006.257.16:45:01.86#ibcon#*after write, iclass 34, count 0 2006.257.16:45:01.86#ibcon#*before return 0, iclass 34, count 0 2006.257.16:45:01.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:01.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:01.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:45:01.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:45:01.86$vck44/va=2,7 2006.257.16:45:01.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.16:45:01.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.16:45:01.86#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:01.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:01.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:01.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:01.92#ibcon#enter wrdev, iclass 36, count 2 2006.257.16:45:01.92#ibcon#first serial, iclass 36, count 2 2006.257.16:45:01.92#ibcon#enter sib2, iclass 36, count 2 2006.257.16:45:01.92#ibcon#flushed, iclass 36, count 2 2006.257.16:45:01.92#ibcon#about to write, iclass 36, count 2 2006.257.16:45:01.92#ibcon#wrote, iclass 36, count 2 2006.257.16:45:01.92#ibcon#about to read 3, iclass 36, count 2 2006.257.16:45:01.94#ibcon#read 3, iclass 36, count 2 2006.257.16:45:01.94#ibcon#about to read 4, iclass 36, count 2 2006.257.16:45:01.94#ibcon#read 4, iclass 36, count 2 2006.257.16:45:01.94#ibcon#about to read 5, iclass 36, count 2 2006.257.16:45:01.94#ibcon#read 5, iclass 36, count 2 2006.257.16:45:01.94#ibcon#about to read 6, iclass 36, count 2 2006.257.16:45:01.94#ibcon#read 6, iclass 36, count 2 2006.257.16:45:01.94#ibcon#end of sib2, iclass 36, count 2 2006.257.16:45:01.94#ibcon#*mode == 0, iclass 36, count 2 2006.257.16:45:01.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.16:45:01.94#ibcon#[25=AT02-07\r\n] 2006.257.16:45:01.94#ibcon#*before write, iclass 36, count 2 2006.257.16:45:01.94#ibcon#enter sib2, iclass 36, count 2 2006.257.16:45:01.94#ibcon#flushed, iclass 36, count 2 2006.257.16:45:01.94#ibcon#about to write, iclass 36, count 2 2006.257.16:45:01.94#ibcon#wrote, iclass 36, count 2 2006.257.16:45:01.94#ibcon#about to read 3, iclass 36, count 2 2006.257.16:45:01.97#ibcon#read 3, iclass 36, count 2 2006.257.16:45:01.97#ibcon#about to read 4, iclass 36, count 2 2006.257.16:45:01.97#ibcon#read 4, iclass 36, count 2 2006.257.16:45:01.97#ibcon#about to read 5, iclass 36, count 2 2006.257.16:45:01.97#ibcon#read 5, iclass 36, count 2 2006.257.16:45:01.97#ibcon#about to read 6, iclass 36, count 2 2006.257.16:45:01.97#ibcon#read 6, iclass 36, count 2 2006.257.16:45:01.97#ibcon#end of sib2, iclass 36, count 2 2006.257.16:45:01.97#ibcon#*after write, iclass 36, count 2 2006.257.16:45:01.97#ibcon#*before return 0, iclass 36, count 2 2006.257.16:45:01.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:01.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:01.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.16:45:01.97#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:01.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:02.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:02.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:02.09#ibcon#enter wrdev, iclass 36, count 0 2006.257.16:45:02.09#ibcon#first serial, iclass 36, count 0 2006.257.16:45:02.09#ibcon#enter sib2, iclass 36, count 0 2006.257.16:45:02.09#ibcon#flushed, iclass 36, count 0 2006.257.16:45:02.09#ibcon#about to write, iclass 36, count 0 2006.257.16:45:02.09#ibcon#wrote, iclass 36, count 0 2006.257.16:45:02.09#ibcon#about to read 3, iclass 36, count 0 2006.257.16:45:02.11#ibcon#read 3, iclass 36, count 0 2006.257.16:45:02.11#ibcon#about to read 4, iclass 36, count 0 2006.257.16:45:02.11#ibcon#read 4, iclass 36, count 0 2006.257.16:45:02.11#ibcon#about to read 5, iclass 36, count 0 2006.257.16:45:02.11#ibcon#read 5, iclass 36, count 0 2006.257.16:45:02.11#ibcon#about to read 6, iclass 36, count 0 2006.257.16:45:02.11#ibcon#read 6, iclass 36, count 0 2006.257.16:45:02.11#ibcon#end of sib2, iclass 36, count 0 2006.257.16:45:02.11#ibcon#*mode == 0, iclass 36, count 0 2006.257.16:45:02.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.16:45:02.11#ibcon#[25=USB\r\n] 2006.257.16:45:02.11#ibcon#*before write, iclass 36, count 0 2006.257.16:45:02.11#ibcon#enter sib2, iclass 36, count 0 2006.257.16:45:02.11#ibcon#flushed, iclass 36, count 0 2006.257.16:45:02.11#ibcon#about to write, iclass 36, count 0 2006.257.16:45:02.11#ibcon#wrote, iclass 36, count 0 2006.257.16:45:02.11#ibcon#about to read 3, iclass 36, count 0 2006.257.16:45:02.14#ibcon#read 3, iclass 36, count 0 2006.257.16:45:02.14#ibcon#about to read 4, iclass 36, count 0 2006.257.16:45:02.14#ibcon#read 4, iclass 36, count 0 2006.257.16:45:02.14#ibcon#about to read 5, iclass 36, count 0 2006.257.16:45:02.14#ibcon#read 5, iclass 36, count 0 2006.257.16:45:02.14#ibcon#about to read 6, iclass 36, count 0 2006.257.16:45:02.14#ibcon#read 6, iclass 36, count 0 2006.257.16:45:02.14#ibcon#end of sib2, iclass 36, count 0 2006.257.16:45:02.14#ibcon#*after write, iclass 36, count 0 2006.257.16:45:02.14#ibcon#*before return 0, iclass 36, count 0 2006.257.16:45:02.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:02.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:02.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.16:45:02.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.16:45:02.14$vck44/valo=3,564.99 2006.257.16:45:02.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.16:45:02.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.16:45:02.14#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:02.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:02.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:02.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:02.14#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:45:02.14#ibcon#first serial, iclass 38, count 0 2006.257.16:45:02.14#ibcon#enter sib2, iclass 38, count 0 2006.257.16:45:02.14#ibcon#flushed, iclass 38, count 0 2006.257.16:45:02.14#ibcon#about to write, iclass 38, count 0 2006.257.16:45:02.14#ibcon#wrote, iclass 38, count 0 2006.257.16:45:02.14#ibcon#about to read 3, iclass 38, count 0 2006.257.16:45:02.16#ibcon#read 3, iclass 38, count 0 2006.257.16:45:02.16#ibcon#about to read 4, iclass 38, count 0 2006.257.16:45:02.16#ibcon#read 4, iclass 38, count 0 2006.257.16:45:02.16#ibcon#about to read 5, iclass 38, count 0 2006.257.16:45:02.16#ibcon#read 5, iclass 38, count 0 2006.257.16:45:02.16#ibcon#about to read 6, iclass 38, count 0 2006.257.16:45:02.16#ibcon#read 6, iclass 38, count 0 2006.257.16:45:02.16#ibcon#end of sib2, iclass 38, count 0 2006.257.16:45:02.16#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:45:02.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:45:02.16#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.16:45:02.16#ibcon#*before write, iclass 38, count 0 2006.257.16:45:02.16#ibcon#enter sib2, iclass 38, count 0 2006.257.16:45:02.16#ibcon#flushed, iclass 38, count 0 2006.257.16:45:02.16#ibcon#about to write, iclass 38, count 0 2006.257.16:45:02.16#ibcon#wrote, iclass 38, count 0 2006.257.16:45:02.16#ibcon#about to read 3, iclass 38, count 0 2006.257.16:45:02.20#ibcon#read 3, iclass 38, count 0 2006.257.16:45:02.20#ibcon#about to read 4, iclass 38, count 0 2006.257.16:45:02.20#ibcon#read 4, iclass 38, count 0 2006.257.16:45:02.20#ibcon#about to read 5, iclass 38, count 0 2006.257.16:45:02.20#ibcon#read 5, iclass 38, count 0 2006.257.16:45:02.20#ibcon#about to read 6, iclass 38, count 0 2006.257.16:45:02.20#ibcon#read 6, iclass 38, count 0 2006.257.16:45:02.20#ibcon#end of sib2, iclass 38, count 0 2006.257.16:45:02.20#ibcon#*after write, iclass 38, count 0 2006.257.16:45:02.20#ibcon#*before return 0, iclass 38, count 0 2006.257.16:45:02.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:02.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:02.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:45:02.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:45:02.20$vck44/va=3,8 2006.257.16:45:02.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.16:45:02.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.16:45:02.20#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:02.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:02.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:02.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:02.26#ibcon#enter wrdev, iclass 40, count 2 2006.257.16:45:02.26#ibcon#first serial, iclass 40, count 2 2006.257.16:45:02.26#ibcon#enter sib2, iclass 40, count 2 2006.257.16:45:02.26#ibcon#flushed, iclass 40, count 2 2006.257.16:45:02.26#ibcon#about to write, iclass 40, count 2 2006.257.16:45:02.26#ibcon#wrote, iclass 40, count 2 2006.257.16:45:02.26#ibcon#about to read 3, iclass 40, count 2 2006.257.16:45:02.28#ibcon#read 3, iclass 40, count 2 2006.257.16:45:02.28#ibcon#about to read 4, iclass 40, count 2 2006.257.16:45:02.28#ibcon#read 4, iclass 40, count 2 2006.257.16:45:02.28#ibcon#about to read 5, iclass 40, count 2 2006.257.16:45:02.28#ibcon#read 5, iclass 40, count 2 2006.257.16:45:02.28#ibcon#about to read 6, iclass 40, count 2 2006.257.16:45:02.28#ibcon#read 6, iclass 40, count 2 2006.257.16:45:02.28#ibcon#end of sib2, iclass 40, count 2 2006.257.16:45:02.28#ibcon#*mode == 0, iclass 40, count 2 2006.257.16:45:02.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.16:45:02.28#ibcon#[25=AT03-08\r\n] 2006.257.16:45:02.28#ibcon#*before write, iclass 40, count 2 2006.257.16:45:02.28#ibcon#enter sib2, iclass 40, count 2 2006.257.16:45:02.28#ibcon#flushed, iclass 40, count 2 2006.257.16:45:02.28#ibcon#about to write, iclass 40, count 2 2006.257.16:45:02.28#ibcon#wrote, iclass 40, count 2 2006.257.16:45:02.28#ibcon#about to read 3, iclass 40, count 2 2006.257.16:45:02.31#ibcon#read 3, iclass 40, count 2 2006.257.16:45:02.31#ibcon#about to read 4, iclass 40, count 2 2006.257.16:45:02.31#ibcon#read 4, iclass 40, count 2 2006.257.16:45:02.31#ibcon#about to read 5, iclass 40, count 2 2006.257.16:45:02.31#ibcon#read 5, iclass 40, count 2 2006.257.16:45:02.31#ibcon#about to read 6, iclass 40, count 2 2006.257.16:45:02.31#ibcon#read 6, iclass 40, count 2 2006.257.16:45:02.31#ibcon#end of sib2, iclass 40, count 2 2006.257.16:45:02.31#ibcon#*after write, iclass 40, count 2 2006.257.16:45:02.31#ibcon#*before return 0, iclass 40, count 2 2006.257.16:45:02.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:02.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:02.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.16:45:02.31#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:02.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:02.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:02.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:02.43#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:45:02.43#ibcon#first serial, iclass 40, count 0 2006.257.16:45:02.43#ibcon#enter sib2, iclass 40, count 0 2006.257.16:45:02.43#ibcon#flushed, iclass 40, count 0 2006.257.16:45:02.43#ibcon#about to write, iclass 40, count 0 2006.257.16:45:02.43#ibcon#wrote, iclass 40, count 0 2006.257.16:45:02.43#ibcon#about to read 3, iclass 40, count 0 2006.257.16:45:02.45#ibcon#read 3, iclass 40, count 0 2006.257.16:45:02.45#ibcon#about to read 4, iclass 40, count 0 2006.257.16:45:02.45#ibcon#read 4, iclass 40, count 0 2006.257.16:45:02.45#ibcon#about to read 5, iclass 40, count 0 2006.257.16:45:02.45#ibcon#read 5, iclass 40, count 0 2006.257.16:45:02.45#ibcon#about to read 6, iclass 40, count 0 2006.257.16:45:02.45#ibcon#read 6, iclass 40, count 0 2006.257.16:45:02.45#ibcon#end of sib2, iclass 40, count 0 2006.257.16:45:02.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:45:02.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:45:02.45#ibcon#[25=USB\r\n] 2006.257.16:45:02.45#ibcon#*before write, iclass 40, count 0 2006.257.16:45:02.45#ibcon#enter sib2, iclass 40, count 0 2006.257.16:45:02.45#ibcon#flushed, iclass 40, count 0 2006.257.16:45:02.45#ibcon#about to write, iclass 40, count 0 2006.257.16:45:02.45#ibcon#wrote, iclass 40, count 0 2006.257.16:45:02.45#ibcon#about to read 3, iclass 40, count 0 2006.257.16:45:02.48#ibcon#read 3, iclass 40, count 0 2006.257.16:45:02.48#ibcon#about to read 4, iclass 40, count 0 2006.257.16:45:02.48#ibcon#read 4, iclass 40, count 0 2006.257.16:45:02.48#ibcon#about to read 5, iclass 40, count 0 2006.257.16:45:02.48#ibcon#read 5, iclass 40, count 0 2006.257.16:45:02.48#ibcon#about to read 6, iclass 40, count 0 2006.257.16:45:02.48#ibcon#read 6, iclass 40, count 0 2006.257.16:45:02.48#ibcon#end of sib2, iclass 40, count 0 2006.257.16:45:02.48#ibcon#*after write, iclass 40, count 0 2006.257.16:45:02.48#ibcon#*before return 0, iclass 40, count 0 2006.257.16:45:02.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:02.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:02.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:45:02.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:45:02.48$vck44/valo=4,624.99 2006.257.16:45:02.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.16:45:02.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.16:45:02.48#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:02.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:45:02.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:45:02.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:45:02.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:45:02.48#ibcon#first serial, iclass 4, count 0 2006.257.16:45:02.48#ibcon#enter sib2, iclass 4, count 0 2006.257.16:45:02.48#ibcon#flushed, iclass 4, count 0 2006.257.16:45:02.48#ibcon#about to write, iclass 4, count 0 2006.257.16:45:02.48#ibcon#wrote, iclass 4, count 0 2006.257.16:45:02.48#ibcon#about to read 3, iclass 4, count 0 2006.257.16:45:02.50#ibcon#read 3, iclass 4, count 0 2006.257.16:45:02.50#ibcon#about to read 4, iclass 4, count 0 2006.257.16:45:02.50#ibcon#read 4, iclass 4, count 0 2006.257.16:45:02.50#ibcon#about to read 5, iclass 4, count 0 2006.257.16:45:02.50#ibcon#read 5, iclass 4, count 0 2006.257.16:45:02.50#ibcon#about to read 6, iclass 4, count 0 2006.257.16:45:02.50#ibcon#read 6, iclass 4, count 0 2006.257.16:45:02.50#ibcon#end of sib2, iclass 4, count 0 2006.257.16:45:02.50#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:45:02.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:45:02.50#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.16:45:02.50#ibcon#*before write, iclass 4, count 0 2006.257.16:45:02.50#ibcon#enter sib2, iclass 4, count 0 2006.257.16:45:02.50#ibcon#flushed, iclass 4, count 0 2006.257.16:45:02.50#ibcon#about to write, iclass 4, count 0 2006.257.16:45:02.50#ibcon#wrote, iclass 4, count 0 2006.257.16:45:02.50#ibcon#about to read 3, iclass 4, count 0 2006.257.16:45:02.54#ibcon#read 3, iclass 4, count 0 2006.257.16:45:02.54#ibcon#about to read 4, iclass 4, count 0 2006.257.16:45:02.54#ibcon#read 4, iclass 4, count 0 2006.257.16:45:02.54#ibcon#about to read 5, iclass 4, count 0 2006.257.16:45:02.54#ibcon#read 5, iclass 4, count 0 2006.257.16:45:02.54#ibcon#about to read 6, iclass 4, count 0 2006.257.16:45:02.54#ibcon#read 6, iclass 4, count 0 2006.257.16:45:02.54#ibcon#end of sib2, iclass 4, count 0 2006.257.16:45:02.54#ibcon#*after write, iclass 4, count 0 2006.257.16:45:02.54#ibcon#*before return 0, iclass 4, count 0 2006.257.16:45:02.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:45:02.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.16:45:02.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:45:02.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:45:02.54$vck44/va=4,7 2006.257.16:45:02.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.16:45:02.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.16:45:02.54#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:02.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:45:02.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:45:02.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:45:02.60#ibcon#enter wrdev, iclass 6, count 2 2006.257.16:45:02.60#ibcon#first serial, iclass 6, count 2 2006.257.16:45:02.60#ibcon#enter sib2, iclass 6, count 2 2006.257.16:45:02.60#ibcon#flushed, iclass 6, count 2 2006.257.16:45:02.60#ibcon#about to write, iclass 6, count 2 2006.257.16:45:02.60#ibcon#wrote, iclass 6, count 2 2006.257.16:45:02.60#ibcon#about to read 3, iclass 6, count 2 2006.257.16:45:02.62#ibcon#read 3, iclass 6, count 2 2006.257.16:45:02.62#ibcon#about to read 4, iclass 6, count 2 2006.257.16:45:02.62#ibcon#read 4, iclass 6, count 2 2006.257.16:45:02.62#ibcon#about to read 5, iclass 6, count 2 2006.257.16:45:02.62#ibcon#read 5, iclass 6, count 2 2006.257.16:45:02.62#ibcon#about to read 6, iclass 6, count 2 2006.257.16:45:02.62#ibcon#read 6, iclass 6, count 2 2006.257.16:45:02.62#ibcon#end of sib2, iclass 6, count 2 2006.257.16:45:02.62#ibcon#*mode == 0, iclass 6, count 2 2006.257.16:45:02.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.16:45:02.62#ibcon#[25=AT04-07\r\n] 2006.257.16:45:02.62#ibcon#*before write, iclass 6, count 2 2006.257.16:45:02.62#ibcon#enter sib2, iclass 6, count 2 2006.257.16:45:02.62#ibcon#flushed, iclass 6, count 2 2006.257.16:45:02.62#ibcon#about to write, iclass 6, count 2 2006.257.16:45:02.62#ibcon#wrote, iclass 6, count 2 2006.257.16:45:02.62#ibcon#about to read 3, iclass 6, count 2 2006.257.16:45:02.65#ibcon#read 3, iclass 6, count 2 2006.257.16:45:02.65#ibcon#about to read 4, iclass 6, count 2 2006.257.16:45:02.65#ibcon#read 4, iclass 6, count 2 2006.257.16:45:02.65#ibcon#about to read 5, iclass 6, count 2 2006.257.16:45:02.65#ibcon#read 5, iclass 6, count 2 2006.257.16:45:02.65#ibcon#about to read 6, iclass 6, count 2 2006.257.16:45:02.65#ibcon#read 6, iclass 6, count 2 2006.257.16:45:02.65#ibcon#end of sib2, iclass 6, count 2 2006.257.16:45:02.65#ibcon#*after write, iclass 6, count 2 2006.257.16:45:02.65#ibcon#*before return 0, iclass 6, count 2 2006.257.16:45:02.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:45:02.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.16:45:02.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.16:45:02.65#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:02.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:45:02.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:45:02.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:45:02.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:45:02.77#ibcon#first serial, iclass 6, count 0 2006.257.16:45:02.77#ibcon#enter sib2, iclass 6, count 0 2006.257.16:45:02.77#ibcon#flushed, iclass 6, count 0 2006.257.16:45:02.77#ibcon#about to write, iclass 6, count 0 2006.257.16:45:02.77#ibcon#wrote, iclass 6, count 0 2006.257.16:45:02.77#ibcon#about to read 3, iclass 6, count 0 2006.257.16:45:02.79#ibcon#read 3, iclass 6, count 0 2006.257.16:45:02.79#ibcon#about to read 4, iclass 6, count 0 2006.257.16:45:02.79#ibcon#read 4, iclass 6, count 0 2006.257.16:45:02.79#ibcon#about to read 5, iclass 6, count 0 2006.257.16:45:02.79#ibcon#read 5, iclass 6, count 0 2006.257.16:45:02.79#ibcon#about to read 6, iclass 6, count 0 2006.257.16:45:02.79#ibcon#read 6, iclass 6, count 0 2006.257.16:45:02.79#ibcon#end of sib2, iclass 6, count 0 2006.257.16:45:02.79#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:45:02.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:45:02.79#ibcon#[25=USB\r\n] 2006.257.16:45:02.79#ibcon#*before write, iclass 6, count 0 2006.257.16:45:02.79#ibcon#enter sib2, iclass 6, count 0 2006.257.16:45:02.79#ibcon#flushed, iclass 6, count 0 2006.257.16:45:02.79#ibcon#about to write, iclass 6, count 0 2006.257.16:45:02.79#ibcon#wrote, iclass 6, count 0 2006.257.16:45:02.79#ibcon#about to read 3, iclass 6, count 0 2006.257.16:45:02.82#ibcon#read 3, iclass 6, count 0 2006.257.16:45:02.82#ibcon#about to read 4, iclass 6, count 0 2006.257.16:45:02.82#ibcon#read 4, iclass 6, count 0 2006.257.16:45:02.82#ibcon#about to read 5, iclass 6, count 0 2006.257.16:45:02.82#ibcon#read 5, iclass 6, count 0 2006.257.16:45:02.82#ibcon#about to read 6, iclass 6, count 0 2006.257.16:45:02.82#ibcon#read 6, iclass 6, count 0 2006.257.16:45:02.82#ibcon#end of sib2, iclass 6, count 0 2006.257.16:45:02.82#ibcon#*after write, iclass 6, count 0 2006.257.16:45:02.82#ibcon#*before return 0, iclass 6, count 0 2006.257.16:45:02.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:45:02.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.16:45:02.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:45:02.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:45:02.82$vck44/valo=5,734.99 2006.257.16:45:02.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.16:45:02.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.16:45:02.82#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:02.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:45:02.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:45:02.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:45:02.82#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:45:02.82#ibcon#first serial, iclass 10, count 0 2006.257.16:45:02.82#ibcon#enter sib2, iclass 10, count 0 2006.257.16:45:02.82#ibcon#flushed, iclass 10, count 0 2006.257.16:45:02.82#ibcon#about to write, iclass 10, count 0 2006.257.16:45:02.82#ibcon#wrote, iclass 10, count 0 2006.257.16:45:02.82#ibcon#about to read 3, iclass 10, count 0 2006.257.16:45:02.84#ibcon#read 3, iclass 10, count 0 2006.257.16:45:02.84#ibcon#about to read 4, iclass 10, count 0 2006.257.16:45:02.84#ibcon#read 4, iclass 10, count 0 2006.257.16:45:02.84#ibcon#about to read 5, iclass 10, count 0 2006.257.16:45:02.84#ibcon#read 5, iclass 10, count 0 2006.257.16:45:02.84#ibcon#about to read 6, iclass 10, count 0 2006.257.16:45:02.84#ibcon#read 6, iclass 10, count 0 2006.257.16:45:02.84#ibcon#end of sib2, iclass 10, count 0 2006.257.16:45:02.84#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:45:02.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:45:02.84#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.16:45:02.84#ibcon#*before write, iclass 10, count 0 2006.257.16:45:02.84#ibcon#enter sib2, iclass 10, count 0 2006.257.16:45:02.84#ibcon#flushed, iclass 10, count 0 2006.257.16:45:02.84#ibcon#about to write, iclass 10, count 0 2006.257.16:45:02.84#ibcon#wrote, iclass 10, count 0 2006.257.16:45:02.84#ibcon#about to read 3, iclass 10, count 0 2006.257.16:45:02.88#ibcon#read 3, iclass 10, count 0 2006.257.16:45:02.88#ibcon#about to read 4, iclass 10, count 0 2006.257.16:45:02.88#ibcon#read 4, iclass 10, count 0 2006.257.16:45:02.88#ibcon#about to read 5, iclass 10, count 0 2006.257.16:45:02.88#ibcon#read 5, iclass 10, count 0 2006.257.16:45:02.88#ibcon#about to read 6, iclass 10, count 0 2006.257.16:45:02.88#ibcon#read 6, iclass 10, count 0 2006.257.16:45:02.88#ibcon#end of sib2, iclass 10, count 0 2006.257.16:45:02.88#ibcon#*after write, iclass 10, count 0 2006.257.16:45:02.88#ibcon#*before return 0, iclass 10, count 0 2006.257.16:45:02.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:45:02.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.16:45:02.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:45:02.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:45:02.88$vck44/va=5,4 2006.257.16:45:02.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.16:45:02.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.16:45:02.88#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:02.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:02.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:02.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:02.94#ibcon#enter wrdev, iclass 12, count 2 2006.257.16:45:02.94#ibcon#first serial, iclass 12, count 2 2006.257.16:45:02.94#ibcon#enter sib2, iclass 12, count 2 2006.257.16:45:02.94#ibcon#flushed, iclass 12, count 2 2006.257.16:45:02.94#ibcon#about to write, iclass 12, count 2 2006.257.16:45:02.94#ibcon#wrote, iclass 12, count 2 2006.257.16:45:02.94#ibcon#about to read 3, iclass 12, count 2 2006.257.16:45:02.96#ibcon#read 3, iclass 12, count 2 2006.257.16:45:02.96#ibcon#about to read 4, iclass 12, count 2 2006.257.16:45:02.96#ibcon#read 4, iclass 12, count 2 2006.257.16:45:02.96#ibcon#about to read 5, iclass 12, count 2 2006.257.16:45:02.96#ibcon#read 5, iclass 12, count 2 2006.257.16:45:02.96#ibcon#about to read 6, iclass 12, count 2 2006.257.16:45:02.96#ibcon#read 6, iclass 12, count 2 2006.257.16:45:02.96#ibcon#end of sib2, iclass 12, count 2 2006.257.16:45:02.96#ibcon#*mode == 0, iclass 12, count 2 2006.257.16:45:02.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.16:45:02.96#ibcon#[25=AT05-04\r\n] 2006.257.16:45:02.96#ibcon#*before write, iclass 12, count 2 2006.257.16:45:02.96#ibcon#enter sib2, iclass 12, count 2 2006.257.16:45:02.96#ibcon#flushed, iclass 12, count 2 2006.257.16:45:02.96#ibcon#about to write, iclass 12, count 2 2006.257.16:45:02.96#ibcon#wrote, iclass 12, count 2 2006.257.16:45:02.96#ibcon#about to read 3, iclass 12, count 2 2006.257.16:45:02.99#ibcon#read 3, iclass 12, count 2 2006.257.16:45:02.99#ibcon#about to read 4, iclass 12, count 2 2006.257.16:45:02.99#ibcon#read 4, iclass 12, count 2 2006.257.16:45:02.99#ibcon#about to read 5, iclass 12, count 2 2006.257.16:45:02.99#ibcon#read 5, iclass 12, count 2 2006.257.16:45:02.99#ibcon#about to read 6, iclass 12, count 2 2006.257.16:45:02.99#ibcon#read 6, iclass 12, count 2 2006.257.16:45:02.99#ibcon#end of sib2, iclass 12, count 2 2006.257.16:45:02.99#ibcon#*after write, iclass 12, count 2 2006.257.16:45:02.99#ibcon#*before return 0, iclass 12, count 2 2006.257.16:45:02.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:02.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:02.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.16:45:02.99#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:02.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:03.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:03.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:03.11#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:45:03.11#ibcon#first serial, iclass 12, count 0 2006.257.16:45:03.11#ibcon#enter sib2, iclass 12, count 0 2006.257.16:45:03.11#ibcon#flushed, iclass 12, count 0 2006.257.16:45:03.11#ibcon#about to write, iclass 12, count 0 2006.257.16:45:03.11#ibcon#wrote, iclass 12, count 0 2006.257.16:45:03.11#ibcon#about to read 3, iclass 12, count 0 2006.257.16:45:03.13#ibcon#read 3, iclass 12, count 0 2006.257.16:45:03.13#ibcon#about to read 4, iclass 12, count 0 2006.257.16:45:03.13#ibcon#read 4, iclass 12, count 0 2006.257.16:45:03.13#ibcon#about to read 5, iclass 12, count 0 2006.257.16:45:03.13#ibcon#read 5, iclass 12, count 0 2006.257.16:45:03.13#ibcon#about to read 6, iclass 12, count 0 2006.257.16:45:03.13#ibcon#read 6, iclass 12, count 0 2006.257.16:45:03.13#ibcon#end of sib2, iclass 12, count 0 2006.257.16:45:03.13#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:45:03.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:45:03.13#ibcon#[25=USB\r\n] 2006.257.16:45:03.13#ibcon#*before write, iclass 12, count 0 2006.257.16:45:03.13#ibcon#enter sib2, iclass 12, count 0 2006.257.16:45:03.13#ibcon#flushed, iclass 12, count 0 2006.257.16:45:03.13#ibcon#about to write, iclass 12, count 0 2006.257.16:45:03.13#ibcon#wrote, iclass 12, count 0 2006.257.16:45:03.13#ibcon#about to read 3, iclass 12, count 0 2006.257.16:45:03.16#ibcon#read 3, iclass 12, count 0 2006.257.16:45:03.16#ibcon#about to read 4, iclass 12, count 0 2006.257.16:45:03.16#ibcon#read 4, iclass 12, count 0 2006.257.16:45:03.16#ibcon#about to read 5, iclass 12, count 0 2006.257.16:45:03.16#ibcon#read 5, iclass 12, count 0 2006.257.16:45:03.16#ibcon#about to read 6, iclass 12, count 0 2006.257.16:45:03.16#ibcon#read 6, iclass 12, count 0 2006.257.16:45:03.16#ibcon#end of sib2, iclass 12, count 0 2006.257.16:45:03.16#ibcon#*after write, iclass 12, count 0 2006.257.16:45:03.16#ibcon#*before return 0, iclass 12, count 0 2006.257.16:45:03.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:03.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:03.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:45:03.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:45:03.16$vck44/valo=6,814.99 2006.257.16:45:03.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.16:45:03.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.16:45:03.16#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:03.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:03.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:03.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:03.16#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:45:03.16#ibcon#first serial, iclass 14, count 0 2006.257.16:45:03.16#ibcon#enter sib2, iclass 14, count 0 2006.257.16:45:03.16#ibcon#flushed, iclass 14, count 0 2006.257.16:45:03.16#ibcon#about to write, iclass 14, count 0 2006.257.16:45:03.16#ibcon#wrote, iclass 14, count 0 2006.257.16:45:03.16#ibcon#about to read 3, iclass 14, count 0 2006.257.16:45:03.18#ibcon#read 3, iclass 14, count 0 2006.257.16:45:03.18#ibcon#about to read 4, iclass 14, count 0 2006.257.16:45:03.18#ibcon#read 4, iclass 14, count 0 2006.257.16:45:03.18#ibcon#about to read 5, iclass 14, count 0 2006.257.16:45:03.18#ibcon#read 5, iclass 14, count 0 2006.257.16:45:03.18#ibcon#about to read 6, iclass 14, count 0 2006.257.16:45:03.18#ibcon#read 6, iclass 14, count 0 2006.257.16:45:03.18#ibcon#end of sib2, iclass 14, count 0 2006.257.16:45:03.18#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:45:03.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:45:03.18#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.16:45:03.18#ibcon#*before write, iclass 14, count 0 2006.257.16:45:03.18#ibcon#enter sib2, iclass 14, count 0 2006.257.16:45:03.18#ibcon#flushed, iclass 14, count 0 2006.257.16:45:03.18#ibcon#about to write, iclass 14, count 0 2006.257.16:45:03.18#ibcon#wrote, iclass 14, count 0 2006.257.16:45:03.18#ibcon#about to read 3, iclass 14, count 0 2006.257.16:45:03.22#ibcon#read 3, iclass 14, count 0 2006.257.16:45:03.22#ibcon#about to read 4, iclass 14, count 0 2006.257.16:45:03.22#ibcon#read 4, iclass 14, count 0 2006.257.16:45:03.22#ibcon#about to read 5, iclass 14, count 0 2006.257.16:45:03.22#ibcon#read 5, iclass 14, count 0 2006.257.16:45:03.22#ibcon#about to read 6, iclass 14, count 0 2006.257.16:45:03.22#ibcon#read 6, iclass 14, count 0 2006.257.16:45:03.22#ibcon#end of sib2, iclass 14, count 0 2006.257.16:45:03.22#ibcon#*after write, iclass 14, count 0 2006.257.16:45:03.22#ibcon#*before return 0, iclass 14, count 0 2006.257.16:45:03.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:03.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:03.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:45:03.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:45:03.22$vck44/va=6,4 2006.257.16:45:03.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.16:45:03.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.16:45:03.22#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:03.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:03.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:03.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:03.28#ibcon#enter wrdev, iclass 16, count 2 2006.257.16:45:03.28#ibcon#first serial, iclass 16, count 2 2006.257.16:45:03.28#ibcon#enter sib2, iclass 16, count 2 2006.257.16:45:03.28#ibcon#flushed, iclass 16, count 2 2006.257.16:45:03.28#ibcon#about to write, iclass 16, count 2 2006.257.16:45:03.28#ibcon#wrote, iclass 16, count 2 2006.257.16:45:03.28#ibcon#about to read 3, iclass 16, count 2 2006.257.16:45:03.30#ibcon#read 3, iclass 16, count 2 2006.257.16:45:03.30#ibcon#about to read 4, iclass 16, count 2 2006.257.16:45:03.30#ibcon#read 4, iclass 16, count 2 2006.257.16:45:03.30#ibcon#about to read 5, iclass 16, count 2 2006.257.16:45:03.30#ibcon#read 5, iclass 16, count 2 2006.257.16:45:03.30#ibcon#about to read 6, iclass 16, count 2 2006.257.16:45:03.30#ibcon#read 6, iclass 16, count 2 2006.257.16:45:03.30#ibcon#end of sib2, iclass 16, count 2 2006.257.16:45:03.30#ibcon#*mode == 0, iclass 16, count 2 2006.257.16:45:03.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.16:45:03.30#ibcon#[25=AT06-04\r\n] 2006.257.16:45:03.30#ibcon#*before write, iclass 16, count 2 2006.257.16:45:03.30#ibcon#enter sib2, iclass 16, count 2 2006.257.16:45:03.30#ibcon#flushed, iclass 16, count 2 2006.257.16:45:03.30#ibcon#about to write, iclass 16, count 2 2006.257.16:45:03.30#ibcon#wrote, iclass 16, count 2 2006.257.16:45:03.30#ibcon#about to read 3, iclass 16, count 2 2006.257.16:45:03.33#ibcon#read 3, iclass 16, count 2 2006.257.16:45:03.33#ibcon#about to read 4, iclass 16, count 2 2006.257.16:45:03.33#ibcon#read 4, iclass 16, count 2 2006.257.16:45:03.33#ibcon#about to read 5, iclass 16, count 2 2006.257.16:45:03.33#ibcon#read 5, iclass 16, count 2 2006.257.16:45:03.33#ibcon#about to read 6, iclass 16, count 2 2006.257.16:45:03.33#ibcon#read 6, iclass 16, count 2 2006.257.16:45:03.33#ibcon#end of sib2, iclass 16, count 2 2006.257.16:45:03.33#ibcon#*after write, iclass 16, count 2 2006.257.16:45:03.33#ibcon#*before return 0, iclass 16, count 2 2006.257.16:45:03.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:03.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:03.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.16:45:03.33#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:03.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:03.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:03.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:03.45#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:45:03.45#ibcon#first serial, iclass 16, count 0 2006.257.16:45:03.45#ibcon#enter sib2, iclass 16, count 0 2006.257.16:45:03.45#ibcon#flushed, iclass 16, count 0 2006.257.16:45:03.45#ibcon#about to write, iclass 16, count 0 2006.257.16:45:03.45#ibcon#wrote, iclass 16, count 0 2006.257.16:45:03.45#ibcon#about to read 3, iclass 16, count 0 2006.257.16:45:03.47#ibcon#read 3, iclass 16, count 0 2006.257.16:45:03.47#ibcon#about to read 4, iclass 16, count 0 2006.257.16:45:03.47#ibcon#read 4, iclass 16, count 0 2006.257.16:45:03.47#ibcon#about to read 5, iclass 16, count 0 2006.257.16:45:03.47#ibcon#read 5, iclass 16, count 0 2006.257.16:45:03.47#ibcon#about to read 6, iclass 16, count 0 2006.257.16:45:03.47#ibcon#read 6, iclass 16, count 0 2006.257.16:45:03.47#ibcon#end of sib2, iclass 16, count 0 2006.257.16:45:03.47#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:45:03.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:45:03.47#ibcon#[25=USB\r\n] 2006.257.16:45:03.47#ibcon#*before write, iclass 16, count 0 2006.257.16:45:03.47#ibcon#enter sib2, iclass 16, count 0 2006.257.16:45:03.47#ibcon#flushed, iclass 16, count 0 2006.257.16:45:03.47#ibcon#about to write, iclass 16, count 0 2006.257.16:45:03.47#ibcon#wrote, iclass 16, count 0 2006.257.16:45:03.47#ibcon#about to read 3, iclass 16, count 0 2006.257.16:45:03.50#ibcon#read 3, iclass 16, count 0 2006.257.16:45:03.50#ibcon#about to read 4, iclass 16, count 0 2006.257.16:45:03.50#ibcon#read 4, iclass 16, count 0 2006.257.16:45:03.50#ibcon#about to read 5, iclass 16, count 0 2006.257.16:45:03.50#ibcon#read 5, iclass 16, count 0 2006.257.16:45:03.50#ibcon#about to read 6, iclass 16, count 0 2006.257.16:45:03.50#ibcon#read 6, iclass 16, count 0 2006.257.16:45:03.50#ibcon#end of sib2, iclass 16, count 0 2006.257.16:45:03.50#ibcon#*after write, iclass 16, count 0 2006.257.16:45:03.50#ibcon#*before return 0, iclass 16, count 0 2006.257.16:45:03.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:03.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:03.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:45:03.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:45:03.50$vck44/valo=7,864.99 2006.257.16:45:03.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.16:45:03.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.16:45:03.50#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:03.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:03.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:03.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:03.50#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:45:03.50#ibcon#first serial, iclass 18, count 0 2006.257.16:45:03.50#ibcon#enter sib2, iclass 18, count 0 2006.257.16:45:03.50#ibcon#flushed, iclass 18, count 0 2006.257.16:45:03.50#ibcon#about to write, iclass 18, count 0 2006.257.16:45:03.50#ibcon#wrote, iclass 18, count 0 2006.257.16:45:03.50#ibcon#about to read 3, iclass 18, count 0 2006.257.16:45:03.52#ibcon#read 3, iclass 18, count 0 2006.257.16:45:03.52#ibcon#about to read 4, iclass 18, count 0 2006.257.16:45:03.52#ibcon#read 4, iclass 18, count 0 2006.257.16:45:03.52#ibcon#about to read 5, iclass 18, count 0 2006.257.16:45:03.52#ibcon#read 5, iclass 18, count 0 2006.257.16:45:03.52#ibcon#about to read 6, iclass 18, count 0 2006.257.16:45:03.52#ibcon#read 6, iclass 18, count 0 2006.257.16:45:03.52#ibcon#end of sib2, iclass 18, count 0 2006.257.16:45:03.52#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:45:03.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:45:03.52#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.16:45:03.52#ibcon#*before write, iclass 18, count 0 2006.257.16:45:03.52#ibcon#enter sib2, iclass 18, count 0 2006.257.16:45:03.52#ibcon#flushed, iclass 18, count 0 2006.257.16:45:03.52#ibcon#about to write, iclass 18, count 0 2006.257.16:45:03.52#ibcon#wrote, iclass 18, count 0 2006.257.16:45:03.52#ibcon#about to read 3, iclass 18, count 0 2006.257.16:45:03.56#ibcon#read 3, iclass 18, count 0 2006.257.16:45:03.56#ibcon#about to read 4, iclass 18, count 0 2006.257.16:45:03.56#ibcon#read 4, iclass 18, count 0 2006.257.16:45:03.56#ibcon#about to read 5, iclass 18, count 0 2006.257.16:45:03.56#ibcon#read 5, iclass 18, count 0 2006.257.16:45:03.56#ibcon#about to read 6, iclass 18, count 0 2006.257.16:45:03.56#ibcon#read 6, iclass 18, count 0 2006.257.16:45:03.56#ibcon#end of sib2, iclass 18, count 0 2006.257.16:45:03.56#ibcon#*after write, iclass 18, count 0 2006.257.16:45:03.56#ibcon#*before return 0, iclass 18, count 0 2006.257.16:45:03.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:03.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:03.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:45:03.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:45:03.56$vck44/va=7,4 2006.257.16:45:03.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.16:45:03.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.16:45:03.56#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:03.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:03.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:03.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:03.62#ibcon#enter wrdev, iclass 20, count 2 2006.257.16:45:03.62#ibcon#first serial, iclass 20, count 2 2006.257.16:45:03.62#ibcon#enter sib2, iclass 20, count 2 2006.257.16:45:03.62#ibcon#flushed, iclass 20, count 2 2006.257.16:45:03.62#ibcon#about to write, iclass 20, count 2 2006.257.16:45:03.62#ibcon#wrote, iclass 20, count 2 2006.257.16:45:03.62#ibcon#about to read 3, iclass 20, count 2 2006.257.16:45:03.64#ibcon#read 3, iclass 20, count 2 2006.257.16:45:03.64#ibcon#about to read 4, iclass 20, count 2 2006.257.16:45:03.64#ibcon#read 4, iclass 20, count 2 2006.257.16:45:03.64#ibcon#about to read 5, iclass 20, count 2 2006.257.16:45:03.64#ibcon#read 5, iclass 20, count 2 2006.257.16:45:03.64#ibcon#about to read 6, iclass 20, count 2 2006.257.16:45:03.64#ibcon#read 6, iclass 20, count 2 2006.257.16:45:03.64#ibcon#end of sib2, iclass 20, count 2 2006.257.16:45:03.64#ibcon#*mode == 0, iclass 20, count 2 2006.257.16:45:03.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.16:45:03.64#ibcon#[25=AT07-04\r\n] 2006.257.16:45:03.64#ibcon#*before write, iclass 20, count 2 2006.257.16:45:03.64#ibcon#enter sib2, iclass 20, count 2 2006.257.16:45:03.64#ibcon#flushed, iclass 20, count 2 2006.257.16:45:03.64#ibcon#about to write, iclass 20, count 2 2006.257.16:45:03.64#ibcon#wrote, iclass 20, count 2 2006.257.16:45:03.64#ibcon#about to read 3, iclass 20, count 2 2006.257.16:45:03.67#ibcon#read 3, iclass 20, count 2 2006.257.16:45:03.67#ibcon#about to read 4, iclass 20, count 2 2006.257.16:45:03.67#ibcon#read 4, iclass 20, count 2 2006.257.16:45:03.67#ibcon#about to read 5, iclass 20, count 2 2006.257.16:45:03.67#ibcon#read 5, iclass 20, count 2 2006.257.16:45:03.67#ibcon#about to read 6, iclass 20, count 2 2006.257.16:45:03.67#ibcon#read 6, iclass 20, count 2 2006.257.16:45:03.67#ibcon#end of sib2, iclass 20, count 2 2006.257.16:45:03.67#ibcon#*after write, iclass 20, count 2 2006.257.16:45:03.67#ibcon#*before return 0, iclass 20, count 2 2006.257.16:45:03.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:03.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:03.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.16:45:03.67#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:03.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:03.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:03.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:03.79#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:45:03.79#ibcon#first serial, iclass 20, count 0 2006.257.16:45:03.79#ibcon#enter sib2, iclass 20, count 0 2006.257.16:45:03.79#ibcon#flushed, iclass 20, count 0 2006.257.16:45:03.79#ibcon#about to write, iclass 20, count 0 2006.257.16:45:03.79#ibcon#wrote, iclass 20, count 0 2006.257.16:45:03.79#ibcon#about to read 3, iclass 20, count 0 2006.257.16:45:03.81#ibcon#read 3, iclass 20, count 0 2006.257.16:45:03.81#ibcon#about to read 4, iclass 20, count 0 2006.257.16:45:03.81#ibcon#read 4, iclass 20, count 0 2006.257.16:45:03.81#ibcon#about to read 5, iclass 20, count 0 2006.257.16:45:03.81#ibcon#read 5, iclass 20, count 0 2006.257.16:45:03.81#ibcon#about to read 6, iclass 20, count 0 2006.257.16:45:03.81#ibcon#read 6, iclass 20, count 0 2006.257.16:45:03.81#ibcon#end of sib2, iclass 20, count 0 2006.257.16:45:03.81#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:45:03.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:45:03.81#ibcon#[25=USB\r\n] 2006.257.16:45:03.81#ibcon#*before write, iclass 20, count 0 2006.257.16:45:03.81#ibcon#enter sib2, iclass 20, count 0 2006.257.16:45:03.81#ibcon#flushed, iclass 20, count 0 2006.257.16:45:03.81#ibcon#about to write, iclass 20, count 0 2006.257.16:45:03.81#ibcon#wrote, iclass 20, count 0 2006.257.16:45:03.81#ibcon#about to read 3, iclass 20, count 0 2006.257.16:45:03.84#ibcon#read 3, iclass 20, count 0 2006.257.16:45:03.84#ibcon#about to read 4, iclass 20, count 0 2006.257.16:45:03.84#ibcon#read 4, iclass 20, count 0 2006.257.16:45:03.84#ibcon#about to read 5, iclass 20, count 0 2006.257.16:45:03.84#ibcon#read 5, iclass 20, count 0 2006.257.16:45:03.84#ibcon#about to read 6, iclass 20, count 0 2006.257.16:45:03.84#ibcon#read 6, iclass 20, count 0 2006.257.16:45:03.84#ibcon#end of sib2, iclass 20, count 0 2006.257.16:45:03.84#ibcon#*after write, iclass 20, count 0 2006.257.16:45:03.84#ibcon#*before return 0, iclass 20, count 0 2006.257.16:45:03.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:03.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:03.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:45:03.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:45:03.84$vck44/valo=8,884.99 2006.257.16:45:03.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.16:45:03.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.16:45:03.84#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:03.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:03.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:03.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:03.84#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:45:03.84#ibcon#first serial, iclass 22, count 0 2006.257.16:45:03.84#ibcon#enter sib2, iclass 22, count 0 2006.257.16:45:03.84#ibcon#flushed, iclass 22, count 0 2006.257.16:45:03.84#ibcon#about to write, iclass 22, count 0 2006.257.16:45:03.84#ibcon#wrote, iclass 22, count 0 2006.257.16:45:03.84#ibcon#about to read 3, iclass 22, count 0 2006.257.16:45:03.86#ibcon#read 3, iclass 22, count 0 2006.257.16:45:03.86#ibcon#about to read 4, iclass 22, count 0 2006.257.16:45:03.86#ibcon#read 4, iclass 22, count 0 2006.257.16:45:03.86#ibcon#about to read 5, iclass 22, count 0 2006.257.16:45:03.86#ibcon#read 5, iclass 22, count 0 2006.257.16:45:03.86#ibcon#about to read 6, iclass 22, count 0 2006.257.16:45:03.86#ibcon#read 6, iclass 22, count 0 2006.257.16:45:03.86#ibcon#end of sib2, iclass 22, count 0 2006.257.16:45:03.86#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:45:03.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:45:03.86#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.16:45:03.86#ibcon#*before write, iclass 22, count 0 2006.257.16:45:03.86#ibcon#enter sib2, iclass 22, count 0 2006.257.16:45:03.86#ibcon#flushed, iclass 22, count 0 2006.257.16:45:03.86#ibcon#about to write, iclass 22, count 0 2006.257.16:45:03.86#ibcon#wrote, iclass 22, count 0 2006.257.16:45:03.86#ibcon#about to read 3, iclass 22, count 0 2006.257.16:45:03.90#ibcon#read 3, iclass 22, count 0 2006.257.16:45:03.90#ibcon#about to read 4, iclass 22, count 0 2006.257.16:45:03.90#ibcon#read 4, iclass 22, count 0 2006.257.16:45:03.90#ibcon#about to read 5, iclass 22, count 0 2006.257.16:45:03.90#ibcon#read 5, iclass 22, count 0 2006.257.16:45:03.90#ibcon#about to read 6, iclass 22, count 0 2006.257.16:45:03.90#ibcon#read 6, iclass 22, count 0 2006.257.16:45:03.90#ibcon#end of sib2, iclass 22, count 0 2006.257.16:45:03.90#ibcon#*after write, iclass 22, count 0 2006.257.16:45:03.90#ibcon#*before return 0, iclass 22, count 0 2006.257.16:45:03.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:03.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:03.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:45:03.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:45:03.90$vck44/va=8,4 2006.257.16:45:03.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.16:45:03.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.16:45:03.90#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:03.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:03.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:03.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:03.96#ibcon#enter wrdev, iclass 24, count 2 2006.257.16:45:03.96#ibcon#first serial, iclass 24, count 2 2006.257.16:45:03.96#ibcon#enter sib2, iclass 24, count 2 2006.257.16:45:03.96#ibcon#flushed, iclass 24, count 2 2006.257.16:45:03.96#ibcon#about to write, iclass 24, count 2 2006.257.16:45:03.96#ibcon#wrote, iclass 24, count 2 2006.257.16:45:03.96#ibcon#about to read 3, iclass 24, count 2 2006.257.16:45:03.98#ibcon#read 3, iclass 24, count 2 2006.257.16:45:03.98#ibcon#about to read 4, iclass 24, count 2 2006.257.16:45:03.98#ibcon#read 4, iclass 24, count 2 2006.257.16:45:03.98#ibcon#about to read 5, iclass 24, count 2 2006.257.16:45:03.98#ibcon#read 5, iclass 24, count 2 2006.257.16:45:03.98#ibcon#about to read 6, iclass 24, count 2 2006.257.16:45:03.98#ibcon#read 6, iclass 24, count 2 2006.257.16:45:03.98#ibcon#end of sib2, iclass 24, count 2 2006.257.16:45:03.98#ibcon#*mode == 0, iclass 24, count 2 2006.257.16:45:03.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.16:45:03.98#ibcon#[25=AT08-04\r\n] 2006.257.16:45:03.98#ibcon#*before write, iclass 24, count 2 2006.257.16:45:03.98#ibcon#enter sib2, iclass 24, count 2 2006.257.16:45:03.98#ibcon#flushed, iclass 24, count 2 2006.257.16:45:03.98#ibcon#about to write, iclass 24, count 2 2006.257.16:45:03.98#ibcon#wrote, iclass 24, count 2 2006.257.16:45:03.98#ibcon#about to read 3, iclass 24, count 2 2006.257.16:45:04.01#ibcon#read 3, iclass 24, count 2 2006.257.16:45:04.01#ibcon#about to read 4, iclass 24, count 2 2006.257.16:45:04.01#ibcon#read 4, iclass 24, count 2 2006.257.16:45:04.01#ibcon#about to read 5, iclass 24, count 2 2006.257.16:45:04.01#ibcon#read 5, iclass 24, count 2 2006.257.16:45:04.01#ibcon#about to read 6, iclass 24, count 2 2006.257.16:45:04.01#ibcon#read 6, iclass 24, count 2 2006.257.16:45:04.01#ibcon#end of sib2, iclass 24, count 2 2006.257.16:45:04.01#ibcon#*after write, iclass 24, count 2 2006.257.16:45:04.01#ibcon#*before return 0, iclass 24, count 2 2006.257.16:45:04.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:04.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:04.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.16:45:04.01#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:04.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:04.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:04.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:04.13#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:45:04.13#ibcon#first serial, iclass 24, count 0 2006.257.16:45:04.13#ibcon#enter sib2, iclass 24, count 0 2006.257.16:45:04.13#ibcon#flushed, iclass 24, count 0 2006.257.16:45:04.13#ibcon#about to write, iclass 24, count 0 2006.257.16:45:04.13#ibcon#wrote, iclass 24, count 0 2006.257.16:45:04.13#ibcon#about to read 3, iclass 24, count 0 2006.257.16:45:04.15#ibcon#read 3, iclass 24, count 0 2006.257.16:45:04.15#ibcon#about to read 4, iclass 24, count 0 2006.257.16:45:04.15#ibcon#read 4, iclass 24, count 0 2006.257.16:45:04.15#ibcon#about to read 5, iclass 24, count 0 2006.257.16:45:04.15#ibcon#read 5, iclass 24, count 0 2006.257.16:45:04.15#ibcon#about to read 6, iclass 24, count 0 2006.257.16:45:04.15#ibcon#read 6, iclass 24, count 0 2006.257.16:45:04.15#ibcon#end of sib2, iclass 24, count 0 2006.257.16:45:04.15#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:45:04.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:45:04.15#ibcon#[25=USB\r\n] 2006.257.16:45:04.15#ibcon#*before write, iclass 24, count 0 2006.257.16:45:04.15#ibcon#enter sib2, iclass 24, count 0 2006.257.16:45:04.15#ibcon#flushed, iclass 24, count 0 2006.257.16:45:04.15#ibcon#about to write, iclass 24, count 0 2006.257.16:45:04.15#ibcon#wrote, iclass 24, count 0 2006.257.16:45:04.15#ibcon#about to read 3, iclass 24, count 0 2006.257.16:45:04.18#ibcon#read 3, iclass 24, count 0 2006.257.16:45:04.18#ibcon#about to read 4, iclass 24, count 0 2006.257.16:45:04.18#ibcon#read 4, iclass 24, count 0 2006.257.16:45:04.18#ibcon#about to read 5, iclass 24, count 0 2006.257.16:45:04.18#ibcon#read 5, iclass 24, count 0 2006.257.16:45:04.18#ibcon#about to read 6, iclass 24, count 0 2006.257.16:45:04.18#ibcon#read 6, iclass 24, count 0 2006.257.16:45:04.18#ibcon#end of sib2, iclass 24, count 0 2006.257.16:45:04.18#ibcon#*after write, iclass 24, count 0 2006.257.16:45:04.18#ibcon#*before return 0, iclass 24, count 0 2006.257.16:45:04.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:04.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:04.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:45:04.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:45:04.18$vck44/vblo=1,629.99 2006.257.16:45:04.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.16:45:04.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.16:45:04.18#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:04.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:04.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:04.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:04.18#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:45:04.18#ibcon#first serial, iclass 26, count 0 2006.257.16:45:04.18#ibcon#enter sib2, iclass 26, count 0 2006.257.16:45:04.18#ibcon#flushed, iclass 26, count 0 2006.257.16:45:04.18#ibcon#about to write, iclass 26, count 0 2006.257.16:45:04.18#ibcon#wrote, iclass 26, count 0 2006.257.16:45:04.18#ibcon#about to read 3, iclass 26, count 0 2006.257.16:45:04.20#ibcon#read 3, iclass 26, count 0 2006.257.16:45:04.20#ibcon#about to read 4, iclass 26, count 0 2006.257.16:45:04.20#ibcon#read 4, iclass 26, count 0 2006.257.16:45:04.20#ibcon#about to read 5, iclass 26, count 0 2006.257.16:45:04.20#ibcon#read 5, iclass 26, count 0 2006.257.16:45:04.20#ibcon#about to read 6, iclass 26, count 0 2006.257.16:45:04.20#ibcon#read 6, iclass 26, count 0 2006.257.16:45:04.20#ibcon#end of sib2, iclass 26, count 0 2006.257.16:45:04.20#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:45:04.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:45:04.20#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.16:45:04.20#ibcon#*before write, iclass 26, count 0 2006.257.16:45:04.20#ibcon#enter sib2, iclass 26, count 0 2006.257.16:45:04.20#ibcon#flushed, iclass 26, count 0 2006.257.16:45:04.20#ibcon#about to write, iclass 26, count 0 2006.257.16:45:04.20#ibcon#wrote, iclass 26, count 0 2006.257.16:45:04.20#ibcon#about to read 3, iclass 26, count 0 2006.257.16:45:04.24#ibcon#read 3, iclass 26, count 0 2006.257.16:45:04.24#ibcon#about to read 4, iclass 26, count 0 2006.257.16:45:04.24#ibcon#read 4, iclass 26, count 0 2006.257.16:45:04.24#ibcon#about to read 5, iclass 26, count 0 2006.257.16:45:04.24#ibcon#read 5, iclass 26, count 0 2006.257.16:45:04.24#ibcon#about to read 6, iclass 26, count 0 2006.257.16:45:04.24#ibcon#read 6, iclass 26, count 0 2006.257.16:45:04.24#ibcon#end of sib2, iclass 26, count 0 2006.257.16:45:04.24#ibcon#*after write, iclass 26, count 0 2006.257.16:45:04.24#ibcon#*before return 0, iclass 26, count 0 2006.257.16:45:04.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:04.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:04.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:45:04.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:45:04.24$vck44/vb=1,4 2006.257.16:45:04.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.16:45:04.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.16:45:04.24#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:04.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:45:04.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:45:04.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:45:04.24#ibcon#enter wrdev, iclass 28, count 2 2006.257.16:45:04.24#ibcon#first serial, iclass 28, count 2 2006.257.16:45:04.24#ibcon#enter sib2, iclass 28, count 2 2006.257.16:45:04.24#ibcon#flushed, iclass 28, count 2 2006.257.16:45:04.24#ibcon#about to write, iclass 28, count 2 2006.257.16:45:04.24#ibcon#wrote, iclass 28, count 2 2006.257.16:45:04.24#ibcon#about to read 3, iclass 28, count 2 2006.257.16:45:04.26#ibcon#read 3, iclass 28, count 2 2006.257.16:45:04.26#ibcon#about to read 4, iclass 28, count 2 2006.257.16:45:04.26#ibcon#read 4, iclass 28, count 2 2006.257.16:45:04.26#ibcon#about to read 5, iclass 28, count 2 2006.257.16:45:04.26#ibcon#read 5, iclass 28, count 2 2006.257.16:45:04.26#ibcon#about to read 6, iclass 28, count 2 2006.257.16:45:04.26#ibcon#read 6, iclass 28, count 2 2006.257.16:45:04.26#ibcon#end of sib2, iclass 28, count 2 2006.257.16:45:04.26#ibcon#*mode == 0, iclass 28, count 2 2006.257.16:45:04.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.16:45:04.26#ibcon#[27=AT01-04\r\n] 2006.257.16:45:04.26#ibcon#*before write, iclass 28, count 2 2006.257.16:45:04.26#ibcon#enter sib2, iclass 28, count 2 2006.257.16:45:04.26#ibcon#flushed, iclass 28, count 2 2006.257.16:45:04.26#ibcon#about to write, iclass 28, count 2 2006.257.16:45:04.26#ibcon#wrote, iclass 28, count 2 2006.257.16:45:04.26#ibcon#about to read 3, iclass 28, count 2 2006.257.16:45:04.29#ibcon#read 3, iclass 28, count 2 2006.257.16:45:04.29#ibcon#about to read 4, iclass 28, count 2 2006.257.16:45:04.29#ibcon#read 4, iclass 28, count 2 2006.257.16:45:04.29#ibcon#about to read 5, iclass 28, count 2 2006.257.16:45:04.29#ibcon#read 5, iclass 28, count 2 2006.257.16:45:04.29#ibcon#about to read 6, iclass 28, count 2 2006.257.16:45:04.29#ibcon#read 6, iclass 28, count 2 2006.257.16:45:04.29#ibcon#end of sib2, iclass 28, count 2 2006.257.16:45:04.29#ibcon#*after write, iclass 28, count 2 2006.257.16:45:04.29#ibcon#*before return 0, iclass 28, count 2 2006.257.16:45:04.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:45:04.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.16:45:04.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.16:45:04.29#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:04.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:45:04.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:45:04.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:45:04.41#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:45:04.41#ibcon#first serial, iclass 28, count 0 2006.257.16:45:04.41#ibcon#enter sib2, iclass 28, count 0 2006.257.16:45:04.41#ibcon#flushed, iclass 28, count 0 2006.257.16:45:04.41#ibcon#about to write, iclass 28, count 0 2006.257.16:45:04.41#ibcon#wrote, iclass 28, count 0 2006.257.16:45:04.41#ibcon#about to read 3, iclass 28, count 0 2006.257.16:45:04.43#ibcon#read 3, iclass 28, count 0 2006.257.16:45:04.43#ibcon#about to read 4, iclass 28, count 0 2006.257.16:45:04.43#ibcon#read 4, iclass 28, count 0 2006.257.16:45:04.43#ibcon#about to read 5, iclass 28, count 0 2006.257.16:45:04.43#ibcon#read 5, iclass 28, count 0 2006.257.16:45:04.43#ibcon#about to read 6, iclass 28, count 0 2006.257.16:45:04.43#ibcon#read 6, iclass 28, count 0 2006.257.16:45:04.43#ibcon#end of sib2, iclass 28, count 0 2006.257.16:45:04.43#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:45:04.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:45:04.43#ibcon#[27=USB\r\n] 2006.257.16:45:04.43#ibcon#*before write, iclass 28, count 0 2006.257.16:45:04.43#ibcon#enter sib2, iclass 28, count 0 2006.257.16:45:04.43#ibcon#flushed, iclass 28, count 0 2006.257.16:45:04.43#ibcon#about to write, iclass 28, count 0 2006.257.16:45:04.43#ibcon#wrote, iclass 28, count 0 2006.257.16:45:04.43#ibcon#about to read 3, iclass 28, count 0 2006.257.16:45:04.46#ibcon#read 3, iclass 28, count 0 2006.257.16:45:04.46#ibcon#about to read 4, iclass 28, count 0 2006.257.16:45:04.46#ibcon#read 4, iclass 28, count 0 2006.257.16:45:04.46#ibcon#about to read 5, iclass 28, count 0 2006.257.16:45:04.46#ibcon#read 5, iclass 28, count 0 2006.257.16:45:04.46#ibcon#about to read 6, iclass 28, count 0 2006.257.16:45:04.46#ibcon#read 6, iclass 28, count 0 2006.257.16:45:04.46#ibcon#end of sib2, iclass 28, count 0 2006.257.16:45:04.46#ibcon#*after write, iclass 28, count 0 2006.257.16:45:04.46#ibcon#*before return 0, iclass 28, count 0 2006.257.16:45:04.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:45:04.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.16:45:04.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:45:04.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:45:04.46$vck44/vblo=2,634.99 2006.257.16:45:04.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.16:45:04.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.16:45:04.46#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:04.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:04.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:04.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:04.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:45:04.46#ibcon#first serial, iclass 30, count 0 2006.257.16:45:04.46#ibcon#enter sib2, iclass 30, count 0 2006.257.16:45:04.46#ibcon#flushed, iclass 30, count 0 2006.257.16:45:04.46#ibcon#about to write, iclass 30, count 0 2006.257.16:45:04.46#ibcon#wrote, iclass 30, count 0 2006.257.16:45:04.46#ibcon#about to read 3, iclass 30, count 0 2006.257.16:45:04.48#ibcon#read 3, iclass 30, count 0 2006.257.16:45:04.48#ibcon#about to read 4, iclass 30, count 0 2006.257.16:45:04.48#ibcon#read 4, iclass 30, count 0 2006.257.16:45:04.48#ibcon#about to read 5, iclass 30, count 0 2006.257.16:45:04.48#ibcon#read 5, iclass 30, count 0 2006.257.16:45:04.48#ibcon#about to read 6, iclass 30, count 0 2006.257.16:45:04.48#ibcon#read 6, iclass 30, count 0 2006.257.16:45:04.48#ibcon#end of sib2, iclass 30, count 0 2006.257.16:45:04.48#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:45:04.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:45:04.48#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.16:45:04.48#ibcon#*before write, iclass 30, count 0 2006.257.16:45:04.48#ibcon#enter sib2, iclass 30, count 0 2006.257.16:45:04.48#ibcon#flushed, iclass 30, count 0 2006.257.16:45:04.48#ibcon#about to write, iclass 30, count 0 2006.257.16:45:04.48#ibcon#wrote, iclass 30, count 0 2006.257.16:45:04.48#ibcon#about to read 3, iclass 30, count 0 2006.257.16:45:04.52#ibcon#read 3, iclass 30, count 0 2006.257.16:45:04.52#ibcon#about to read 4, iclass 30, count 0 2006.257.16:45:04.52#ibcon#read 4, iclass 30, count 0 2006.257.16:45:04.52#ibcon#about to read 5, iclass 30, count 0 2006.257.16:45:04.52#ibcon#read 5, iclass 30, count 0 2006.257.16:45:04.52#ibcon#about to read 6, iclass 30, count 0 2006.257.16:45:04.52#ibcon#read 6, iclass 30, count 0 2006.257.16:45:04.52#ibcon#end of sib2, iclass 30, count 0 2006.257.16:45:04.52#ibcon#*after write, iclass 30, count 0 2006.257.16:45:04.52#ibcon#*before return 0, iclass 30, count 0 2006.257.16:45:04.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:04.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.16:45:04.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:45:04.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:45:04.52$vck44/vb=2,5 2006.257.16:45:04.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.16:45:04.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.16:45:04.52#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:04.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:04.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:04.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:04.58#ibcon#enter wrdev, iclass 32, count 2 2006.257.16:45:04.58#ibcon#first serial, iclass 32, count 2 2006.257.16:45:04.58#ibcon#enter sib2, iclass 32, count 2 2006.257.16:45:04.58#ibcon#flushed, iclass 32, count 2 2006.257.16:45:04.58#ibcon#about to write, iclass 32, count 2 2006.257.16:45:04.58#ibcon#wrote, iclass 32, count 2 2006.257.16:45:04.58#ibcon#about to read 3, iclass 32, count 2 2006.257.16:45:04.60#ibcon#read 3, iclass 32, count 2 2006.257.16:45:04.60#ibcon#about to read 4, iclass 32, count 2 2006.257.16:45:04.60#ibcon#read 4, iclass 32, count 2 2006.257.16:45:04.60#ibcon#about to read 5, iclass 32, count 2 2006.257.16:45:04.60#ibcon#read 5, iclass 32, count 2 2006.257.16:45:04.60#ibcon#about to read 6, iclass 32, count 2 2006.257.16:45:04.60#ibcon#read 6, iclass 32, count 2 2006.257.16:45:04.60#ibcon#end of sib2, iclass 32, count 2 2006.257.16:45:04.60#ibcon#*mode == 0, iclass 32, count 2 2006.257.16:45:04.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.16:45:04.60#ibcon#[27=AT02-05\r\n] 2006.257.16:45:04.60#ibcon#*before write, iclass 32, count 2 2006.257.16:45:04.60#ibcon#enter sib2, iclass 32, count 2 2006.257.16:45:04.60#ibcon#flushed, iclass 32, count 2 2006.257.16:45:04.60#ibcon#about to write, iclass 32, count 2 2006.257.16:45:04.60#ibcon#wrote, iclass 32, count 2 2006.257.16:45:04.60#ibcon#about to read 3, iclass 32, count 2 2006.257.16:45:04.63#ibcon#read 3, iclass 32, count 2 2006.257.16:45:04.63#ibcon#about to read 4, iclass 32, count 2 2006.257.16:45:04.63#ibcon#read 4, iclass 32, count 2 2006.257.16:45:04.63#ibcon#about to read 5, iclass 32, count 2 2006.257.16:45:04.63#ibcon#read 5, iclass 32, count 2 2006.257.16:45:04.63#ibcon#about to read 6, iclass 32, count 2 2006.257.16:45:04.63#ibcon#read 6, iclass 32, count 2 2006.257.16:45:04.63#ibcon#end of sib2, iclass 32, count 2 2006.257.16:45:04.63#ibcon#*after write, iclass 32, count 2 2006.257.16:45:04.63#ibcon#*before return 0, iclass 32, count 2 2006.257.16:45:04.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:04.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.16:45:04.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.16:45:04.63#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:04.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:04.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:04.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:04.75#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:45:04.75#ibcon#first serial, iclass 32, count 0 2006.257.16:45:04.75#ibcon#enter sib2, iclass 32, count 0 2006.257.16:45:04.75#ibcon#flushed, iclass 32, count 0 2006.257.16:45:04.75#ibcon#about to write, iclass 32, count 0 2006.257.16:45:04.75#ibcon#wrote, iclass 32, count 0 2006.257.16:45:04.75#ibcon#about to read 3, iclass 32, count 0 2006.257.16:45:04.77#ibcon#read 3, iclass 32, count 0 2006.257.16:45:04.77#ibcon#about to read 4, iclass 32, count 0 2006.257.16:45:04.77#ibcon#read 4, iclass 32, count 0 2006.257.16:45:04.77#ibcon#about to read 5, iclass 32, count 0 2006.257.16:45:04.77#ibcon#read 5, iclass 32, count 0 2006.257.16:45:04.77#ibcon#about to read 6, iclass 32, count 0 2006.257.16:45:04.77#ibcon#read 6, iclass 32, count 0 2006.257.16:45:04.77#ibcon#end of sib2, iclass 32, count 0 2006.257.16:45:04.77#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:45:04.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:45:04.77#ibcon#[27=USB\r\n] 2006.257.16:45:04.77#ibcon#*before write, iclass 32, count 0 2006.257.16:45:04.77#ibcon#enter sib2, iclass 32, count 0 2006.257.16:45:04.77#ibcon#flushed, iclass 32, count 0 2006.257.16:45:04.77#ibcon#about to write, iclass 32, count 0 2006.257.16:45:04.77#ibcon#wrote, iclass 32, count 0 2006.257.16:45:04.77#ibcon#about to read 3, iclass 32, count 0 2006.257.16:45:04.80#ibcon#read 3, iclass 32, count 0 2006.257.16:45:04.80#ibcon#about to read 4, iclass 32, count 0 2006.257.16:45:04.80#ibcon#read 4, iclass 32, count 0 2006.257.16:45:04.80#ibcon#about to read 5, iclass 32, count 0 2006.257.16:45:04.80#ibcon#read 5, iclass 32, count 0 2006.257.16:45:04.80#ibcon#about to read 6, iclass 32, count 0 2006.257.16:45:04.80#ibcon#read 6, iclass 32, count 0 2006.257.16:45:04.80#ibcon#end of sib2, iclass 32, count 0 2006.257.16:45:04.80#ibcon#*after write, iclass 32, count 0 2006.257.16:45:04.80#ibcon#*before return 0, iclass 32, count 0 2006.257.16:45:04.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:04.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.16:45:04.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:45:04.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:45:04.80$vck44/vblo=3,649.99 2006.257.16:45:04.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.16:45:04.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.16:45:04.80#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:04.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:04.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:04.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:04.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:45:04.80#ibcon#first serial, iclass 34, count 0 2006.257.16:45:04.80#ibcon#enter sib2, iclass 34, count 0 2006.257.16:45:04.80#ibcon#flushed, iclass 34, count 0 2006.257.16:45:04.80#ibcon#about to write, iclass 34, count 0 2006.257.16:45:04.80#ibcon#wrote, iclass 34, count 0 2006.257.16:45:04.80#ibcon#about to read 3, iclass 34, count 0 2006.257.16:45:04.82#ibcon#read 3, iclass 34, count 0 2006.257.16:45:04.82#ibcon#about to read 4, iclass 34, count 0 2006.257.16:45:04.82#ibcon#read 4, iclass 34, count 0 2006.257.16:45:04.82#ibcon#about to read 5, iclass 34, count 0 2006.257.16:45:04.82#ibcon#read 5, iclass 34, count 0 2006.257.16:45:04.82#ibcon#about to read 6, iclass 34, count 0 2006.257.16:45:04.82#ibcon#read 6, iclass 34, count 0 2006.257.16:45:04.82#ibcon#end of sib2, iclass 34, count 0 2006.257.16:45:04.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:45:04.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:45:04.82#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.16:45:04.82#ibcon#*before write, iclass 34, count 0 2006.257.16:45:04.82#ibcon#enter sib2, iclass 34, count 0 2006.257.16:45:04.82#ibcon#flushed, iclass 34, count 0 2006.257.16:45:04.82#ibcon#about to write, iclass 34, count 0 2006.257.16:45:04.82#ibcon#wrote, iclass 34, count 0 2006.257.16:45:04.82#ibcon#about to read 3, iclass 34, count 0 2006.257.16:45:04.86#ibcon#read 3, iclass 34, count 0 2006.257.16:45:04.86#ibcon#about to read 4, iclass 34, count 0 2006.257.16:45:04.86#ibcon#read 4, iclass 34, count 0 2006.257.16:45:04.86#ibcon#about to read 5, iclass 34, count 0 2006.257.16:45:04.86#ibcon#read 5, iclass 34, count 0 2006.257.16:45:04.86#ibcon#about to read 6, iclass 34, count 0 2006.257.16:45:04.86#ibcon#read 6, iclass 34, count 0 2006.257.16:45:04.86#ibcon#end of sib2, iclass 34, count 0 2006.257.16:45:04.86#ibcon#*after write, iclass 34, count 0 2006.257.16:45:04.86#ibcon#*before return 0, iclass 34, count 0 2006.257.16:45:04.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:04.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.16:45:04.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:45:04.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:45:04.86$vck44/vb=3,4 2006.257.16:45:04.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.16:45:04.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.16:45:04.86#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:04.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:04.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:04.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:04.92#ibcon#enter wrdev, iclass 36, count 2 2006.257.16:45:04.92#ibcon#first serial, iclass 36, count 2 2006.257.16:45:04.92#ibcon#enter sib2, iclass 36, count 2 2006.257.16:45:04.92#ibcon#flushed, iclass 36, count 2 2006.257.16:45:04.92#ibcon#about to write, iclass 36, count 2 2006.257.16:45:04.92#ibcon#wrote, iclass 36, count 2 2006.257.16:45:04.92#ibcon#about to read 3, iclass 36, count 2 2006.257.16:45:04.94#ibcon#read 3, iclass 36, count 2 2006.257.16:45:04.94#ibcon#about to read 4, iclass 36, count 2 2006.257.16:45:04.94#ibcon#read 4, iclass 36, count 2 2006.257.16:45:04.94#ibcon#about to read 5, iclass 36, count 2 2006.257.16:45:04.94#ibcon#read 5, iclass 36, count 2 2006.257.16:45:04.94#ibcon#about to read 6, iclass 36, count 2 2006.257.16:45:04.94#ibcon#read 6, iclass 36, count 2 2006.257.16:45:04.94#ibcon#end of sib2, iclass 36, count 2 2006.257.16:45:04.94#ibcon#*mode == 0, iclass 36, count 2 2006.257.16:45:04.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.16:45:04.94#ibcon#[27=AT03-04\r\n] 2006.257.16:45:04.94#ibcon#*before write, iclass 36, count 2 2006.257.16:45:04.94#ibcon#enter sib2, iclass 36, count 2 2006.257.16:45:04.94#ibcon#flushed, iclass 36, count 2 2006.257.16:45:04.94#ibcon#about to write, iclass 36, count 2 2006.257.16:45:04.94#ibcon#wrote, iclass 36, count 2 2006.257.16:45:04.94#ibcon#about to read 3, iclass 36, count 2 2006.257.16:45:04.97#ibcon#read 3, iclass 36, count 2 2006.257.16:45:04.97#ibcon#about to read 4, iclass 36, count 2 2006.257.16:45:04.97#ibcon#read 4, iclass 36, count 2 2006.257.16:45:04.97#ibcon#about to read 5, iclass 36, count 2 2006.257.16:45:04.97#ibcon#read 5, iclass 36, count 2 2006.257.16:45:04.97#ibcon#about to read 6, iclass 36, count 2 2006.257.16:45:04.97#ibcon#read 6, iclass 36, count 2 2006.257.16:45:04.97#ibcon#end of sib2, iclass 36, count 2 2006.257.16:45:04.97#ibcon#*after write, iclass 36, count 2 2006.257.16:45:04.97#ibcon#*before return 0, iclass 36, count 2 2006.257.16:45:04.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:04.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.16:45:04.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.16:45:04.97#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:04.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:05.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:05.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:05.09#ibcon#enter wrdev, iclass 36, count 0 2006.257.16:45:05.09#ibcon#first serial, iclass 36, count 0 2006.257.16:45:05.09#ibcon#enter sib2, iclass 36, count 0 2006.257.16:45:05.09#ibcon#flushed, iclass 36, count 0 2006.257.16:45:05.09#ibcon#about to write, iclass 36, count 0 2006.257.16:45:05.09#ibcon#wrote, iclass 36, count 0 2006.257.16:45:05.09#ibcon#about to read 3, iclass 36, count 0 2006.257.16:45:05.11#ibcon#read 3, iclass 36, count 0 2006.257.16:45:05.11#ibcon#about to read 4, iclass 36, count 0 2006.257.16:45:05.11#ibcon#read 4, iclass 36, count 0 2006.257.16:45:05.11#ibcon#about to read 5, iclass 36, count 0 2006.257.16:45:05.11#ibcon#read 5, iclass 36, count 0 2006.257.16:45:05.11#ibcon#about to read 6, iclass 36, count 0 2006.257.16:45:05.11#ibcon#read 6, iclass 36, count 0 2006.257.16:45:05.11#ibcon#end of sib2, iclass 36, count 0 2006.257.16:45:05.11#ibcon#*mode == 0, iclass 36, count 0 2006.257.16:45:05.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.16:45:05.11#ibcon#[27=USB\r\n] 2006.257.16:45:05.11#ibcon#*before write, iclass 36, count 0 2006.257.16:45:05.11#ibcon#enter sib2, iclass 36, count 0 2006.257.16:45:05.11#ibcon#flushed, iclass 36, count 0 2006.257.16:45:05.11#ibcon#about to write, iclass 36, count 0 2006.257.16:45:05.11#ibcon#wrote, iclass 36, count 0 2006.257.16:45:05.11#ibcon#about to read 3, iclass 36, count 0 2006.257.16:45:05.14#ibcon#read 3, iclass 36, count 0 2006.257.16:45:05.14#ibcon#about to read 4, iclass 36, count 0 2006.257.16:45:05.14#ibcon#read 4, iclass 36, count 0 2006.257.16:45:05.14#ibcon#about to read 5, iclass 36, count 0 2006.257.16:45:05.14#ibcon#read 5, iclass 36, count 0 2006.257.16:45:05.14#ibcon#about to read 6, iclass 36, count 0 2006.257.16:45:05.14#ibcon#read 6, iclass 36, count 0 2006.257.16:45:05.14#ibcon#end of sib2, iclass 36, count 0 2006.257.16:45:05.14#ibcon#*after write, iclass 36, count 0 2006.257.16:45:05.14#ibcon#*before return 0, iclass 36, count 0 2006.257.16:45:05.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:05.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.16:45:05.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.16:45:05.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.16:45:05.14$vck44/vblo=4,679.99 2006.257.16:45:05.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.16:45:05.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.16:45:05.14#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:05.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:05.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:05.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:05.14#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:45:05.14#ibcon#first serial, iclass 38, count 0 2006.257.16:45:05.14#ibcon#enter sib2, iclass 38, count 0 2006.257.16:45:05.14#ibcon#flushed, iclass 38, count 0 2006.257.16:45:05.14#ibcon#about to write, iclass 38, count 0 2006.257.16:45:05.14#ibcon#wrote, iclass 38, count 0 2006.257.16:45:05.14#ibcon#about to read 3, iclass 38, count 0 2006.257.16:45:05.16#ibcon#read 3, iclass 38, count 0 2006.257.16:45:05.16#ibcon#about to read 4, iclass 38, count 0 2006.257.16:45:05.16#ibcon#read 4, iclass 38, count 0 2006.257.16:45:05.16#ibcon#about to read 5, iclass 38, count 0 2006.257.16:45:05.16#ibcon#read 5, iclass 38, count 0 2006.257.16:45:05.16#ibcon#about to read 6, iclass 38, count 0 2006.257.16:45:05.16#ibcon#read 6, iclass 38, count 0 2006.257.16:45:05.16#ibcon#end of sib2, iclass 38, count 0 2006.257.16:45:05.16#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:45:05.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:45:05.16#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.16:45:05.16#ibcon#*before write, iclass 38, count 0 2006.257.16:45:05.16#ibcon#enter sib2, iclass 38, count 0 2006.257.16:45:05.16#ibcon#flushed, iclass 38, count 0 2006.257.16:45:05.16#ibcon#about to write, iclass 38, count 0 2006.257.16:45:05.16#ibcon#wrote, iclass 38, count 0 2006.257.16:45:05.16#ibcon#about to read 3, iclass 38, count 0 2006.257.16:45:05.20#ibcon#read 3, iclass 38, count 0 2006.257.16:45:05.20#ibcon#about to read 4, iclass 38, count 0 2006.257.16:45:05.20#ibcon#read 4, iclass 38, count 0 2006.257.16:45:05.20#ibcon#about to read 5, iclass 38, count 0 2006.257.16:45:05.20#ibcon#read 5, iclass 38, count 0 2006.257.16:45:05.20#ibcon#about to read 6, iclass 38, count 0 2006.257.16:45:05.20#ibcon#read 6, iclass 38, count 0 2006.257.16:45:05.20#ibcon#end of sib2, iclass 38, count 0 2006.257.16:45:05.20#ibcon#*after write, iclass 38, count 0 2006.257.16:45:05.20#ibcon#*before return 0, iclass 38, count 0 2006.257.16:45:05.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:05.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.16:45:05.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:45:05.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:45:05.20$vck44/vb=4,5 2006.257.16:45:05.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.16:45:05.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.16:45:05.20#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:05.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:05.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:05.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:05.26#ibcon#enter wrdev, iclass 40, count 2 2006.257.16:45:05.26#ibcon#first serial, iclass 40, count 2 2006.257.16:45:05.26#ibcon#enter sib2, iclass 40, count 2 2006.257.16:45:05.26#ibcon#flushed, iclass 40, count 2 2006.257.16:45:05.26#ibcon#about to write, iclass 40, count 2 2006.257.16:45:05.26#ibcon#wrote, iclass 40, count 2 2006.257.16:45:05.26#ibcon#about to read 3, iclass 40, count 2 2006.257.16:45:05.28#ibcon#read 3, iclass 40, count 2 2006.257.16:45:05.28#ibcon#about to read 4, iclass 40, count 2 2006.257.16:45:05.28#ibcon#read 4, iclass 40, count 2 2006.257.16:45:05.28#ibcon#about to read 5, iclass 40, count 2 2006.257.16:45:05.28#ibcon#read 5, iclass 40, count 2 2006.257.16:45:05.28#ibcon#about to read 6, iclass 40, count 2 2006.257.16:45:05.28#ibcon#read 6, iclass 40, count 2 2006.257.16:45:05.28#ibcon#end of sib2, iclass 40, count 2 2006.257.16:45:05.28#ibcon#*mode == 0, iclass 40, count 2 2006.257.16:45:05.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.16:45:05.28#ibcon#[27=AT04-05\r\n] 2006.257.16:45:05.28#ibcon#*before write, iclass 40, count 2 2006.257.16:45:05.28#ibcon#enter sib2, iclass 40, count 2 2006.257.16:45:05.28#ibcon#flushed, iclass 40, count 2 2006.257.16:45:05.28#ibcon#about to write, iclass 40, count 2 2006.257.16:45:05.28#ibcon#wrote, iclass 40, count 2 2006.257.16:45:05.28#ibcon#about to read 3, iclass 40, count 2 2006.257.16:45:05.31#ibcon#read 3, iclass 40, count 2 2006.257.16:45:05.31#ibcon#about to read 4, iclass 40, count 2 2006.257.16:45:05.31#ibcon#read 4, iclass 40, count 2 2006.257.16:45:05.31#ibcon#about to read 5, iclass 40, count 2 2006.257.16:45:05.31#ibcon#read 5, iclass 40, count 2 2006.257.16:45:05.31#ibcon#about to read 6, iclass 40, count 2 2006.257.16:45:05.31#ibcon#read 6, iclass 40, count 2 2006.257.16:45:05.31#ibcon#end of sib2, iclass 40, count 2 2006.257.16:45:05.31#ibcon#*after write, iclass 40, count 2 2006.257.16:45:05.31#ibcon#*before return 0, iclass 40, count 2 2006.257.16:45:05.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:05.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.16:45:05.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.16:45:05.31#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:05.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:05.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:05.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:05.43#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:45:05.43#ibcon#first serial, iclass 40, count 0 2006.257.16:45:05.43#ibcon#enter sib2, iclass 40, count 0 2006.257.16:45:05.43#ibcon#flushed, iclass 40, count 0 2006.257.16:45:05.43#ibcon#about to write, iclass 40, count 0 2006.257.16:45:05.43#ibcon#wrote, iclass 40, count 0 2006.257.16:45:05.43#ibcon#about to read 3, iclass 40, count 0 2006.257.16:45:05.44#abcon#<5=/14 1.9 4.7 17.30 961014.1\r\n> 2006.257.16:45:05.45#ibcon#read 3, iclass 40, count 0 2006.257.16:45:05.45#ibcon#about to read 4, iclass 40, count 0 2006.257.16:45:05.45#ibcon#read 4, iclass 40, count 0 2006.257.16:45:05.45#ibcon#about to read 5, iclass 40, count 0 2006.257.16:45:05.45#ibcon#read 5, iclass 40, count 0 2006.257.16:45:05.45#ibcon#about to read 6, iclass 40, count 0 2006.257.16:45:05.45#ibcon#read 6, iclass 40, count 0 2006.257.16:45:05.45#ibcon#end of sib2, iclass 40, count 0 2006.257.16:45:05.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:45:05.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:45:05.45#ibcon#[27=USB\r\n] 2006.257.16:45:05.45#ibcon#*before write, iclass 40, count 0 2006.257.16:45:05.45#ibcon#enter sib2, iclass 40, count 0 2006.257.16:45:05.45#ibcon#flushed, iclass 40, count 0 2006.257.16:45:05.45#ibcon#about to write, iclass 40, count 0 2006.257.16:45:05.45#ibcon#wrote, iclass 40, count 0 2006.257.16:45:05.45#ibcon#about to read 3, iclass 40, count 0 2006.257.16:45:05.46#abcon#{5=INTERFACE CLEAR} 2006.257.16:45:05.48#ibcon#read 3, iclass 40, count 0 2006.257.16:45:05.48#ibcon#about to read 4, iclass 40, count 0 2006.257.16:45:05.48#ibcon#read 4, iclass 40, count 0 2006.257.16:45:05.48#ibcon#about to read 5, iclass 40, count 0 2006.257.16:45:05.48#ibcon#read 5, iclass 40, count 0 2006.257.16:45:05.48#ibcon#about to read 6, iclass 40, count 0 2006.257.16:45:05.48#ibcon#read 6, iclass 40, count 0 2006.257.16:45:05.48#ibcon#end of sib2, iclass 40, count 0 2006.257.16:45:05.48#ibcon#*after write, iclass 40, count 0 2006.257.16:45:05.48#ibcon#*before return 0, iclass 40, count 0 2006.257.16:45:05.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:05.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.16:45:05.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:45:05.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:45:05.48$vck44/vblo=5,709.99 2006.257.16:45:05.48#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.16:45:05.48#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.16:45:05.48#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:05.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:45:05.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:45:05.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:45:05.48#ibcon#enter wrdev, iclass 7, count 0 2006.257.16:45:05.48#ibcon#first serial, iclass 7, count 0 2006.257.16:45:05.48#ibcon#enter sib2, iclass 7, count 0 2006.257.16:45:05.48#ibcon#flushed, iclass 7, count 0 2006.257.16:45:05.48#ibcon#about to write, iclass 7, count 0 2006.257.16:45:05.48#ibcon#wrote, iclass 7, count 0 2006.257.16:45:05.48#ibcon#about to read 3, iclass 7, count 0 2006.257.16:45:05.50#ibcon#read 3, iclass 7, count 0 2006.257.16:45:05.50#ibcon#about to read 4, iclass 7, count 0 2006.257.16:45:05.50#ibcon#read 4, iclass 7, count 0 2006.257.16:45:05.50#ibcon#about to read 5, iclass 7, count 0 2006.257.16:45:05.50#ibcon#read 5, iclass 7, count 0 2006.257.16:45:05.50#ibcon#about to read 6, iclass 7, count 0 2006.257.16:45:05.50#ibcon#read 6, iclass 7, count 0 2006.257.16:45:05.50#ibcon#end of sib2, iclass 7, count 0 2006.257.16:45:05.50#ibcon#*mode == 0, iclass 7, count 0 2006.257.16:45:05.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.16:45:05.50#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:45:05.50#ibcon#*before write, iclass 7, count 0 2006.257.16:45:05.50#ibcon#enter sib2, iclass 7, count 0 2006.257.16:45:05.50#ibcon#flushed, iclass 7, count 0 2006.257.16:45:05.50#ibcon#about to write, iclass 7, count 0 2006.257.16:45:05.50#ibcon#wrote, iclass 7, count 0 2006.257.16:45:05.50#ibcon#about to read 3, iclass 7, count 0 2006.257.16:45:05.52#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:45:05.54#ibcon#read 3, iclass 7, count 0 2006.257.16:45:05.54#ibcon#about to read 4, iclass 7, count 0 2006.257.16:45:05.54#ibcon#read 4, iclass 7, count 0 2006.257.16:45:05.54#ibcon#about to read 5, iclass 7, count 0 2006.257.16:45:05.54#ibcon#read 5, iclass 7, count 0 2006.257.16:45:05.54#ibcon#about to read 6, iclass 7, count 0 2006.257.16:45:05.54#ibcon#read 6, iclass 7, count 0 2006.257.16:45:05.54#ibcon#end of sib2, iclass 7, count 0 2006.257.16:45:05.54#ibcon#*after write, iclass 7, count 0 2006.257.16:45:05.54#ibcon#*before return 0, iclass 7, count 0 2006.257.16:45:05.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:45:05.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:45:05.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.16:45:05.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.16:45:05.54$vck44/vb=5,4 2006.257.16:45:05.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.16:45:05.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.16:45:05.54#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:05.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:05.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:05.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:05.60#ibcon#enter wrdev, iclass 12, count 2 2006.257.16:45:05.60#ibcon#first serial, iclass 12, count 2 2006.257.16:45:05.60#ibcon#enter sib2, iclass 12, count 2 2006.257.16:45:05.60#ibcon#flushed, iclass 12, count 2 2006.257.16:45:05.60#ibcon#about to write, iclass 12, count 2 2006.257.16:45:05.60#ibcon#wrote, iclass 12, count 2 2006.257.16:45:05.60#ibcon#about to read 3, iclass 12, count 2 2006.257.16:45:05.62#ibcon#read 3, iclass 12, count 2 2006.257.16:45:05.62#ibcon#about to read 4, iclass 12, count 2 2006.257.16:45:05.62#ibcon#read 4, iclass 12, count 2 2006.257.16:45:05.62#ibcon#about to read 5, iclass 12, count 2 2006.257.16:45:05.62#ibcon#read 5, iclass 12, count 2 2006.257.16:45:05.62#ibcon#about to read 6, iclass 12, count 2 2006.257.16:45:05.62#ibcon#read 6, iclass 12, count 2 2006.257.16:45:05.62#ibcon#end of sib2, iclass 12, count 2 2006.257.16:45:05.62#ibcon#*mode == 0, iclass 12, count 2 2006.257.16:45:05.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.16:45:05.62#ibcon#[27=AT05-04\r\n] 2006.257.16:45:05.62#ibcon#*before write, iclass 12, count 2 2006.257.16:45:05.62#ibcon#enter sib2, iclass 12, count 2 2006.257.16:45:05.62#ibcon#flushed, iclass 12, count 2 2006.257.16:45:05.62#ibcon#about to write, iclass 12, count 2 2006.257.16:45:05.62#ibcon#wrote, iclass 12, count 2 2006.257.16:45:05.62#ibcon#about to read 3, iclass 12, count 2 2006.257.16:45:05.65#ibcon#read 3, iclass 12, count 2 2006.257.16:45:05.65#ibcon#about to read 4, iclass 12, count 2 2006.257.16:45:05.65#ibcon#read 4, iclass 12, count 2 2006.257.16:45:05.65#ibcon#about to read 5, iclass 12, count 2 2006.257.16:45:05.65#ibcon#read 5, iclass 12, count 2 2006.257.16:45:05.65#ibcon#about to read 6, iclass 12, count 2 2006.257.16:45:05.65#ibcon#read 6, iclass 12, count 2 2006.257.16:45:05.65#ibcon#end of sib2, iclass 12, count 2 2006.257.16:45:05.65#ibcon#*after write, iclass 12, count 2 2006.257.16:45:05.65#ibcon#*before return 0, iclass 12, count 2 2006.257.16:45:05.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:05.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.16:45:05.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.16:45:05.65#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:05.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:05.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:05.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:05.77#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:45:05.77#ibcon#first serial, iclass 12, count 0 2006.257.16:45:05.77#ibcon#enter sib2, iclass 12, count 0 2006.257.16:45:05.77#ibcon#flushed, iclass 12, count 0 2006.257.16:45:05.77#ibcon#about to write, iclass 12, count 0 2006.257.16:45:05.77#ibcon#wrote, iclass 12, count 0 2006.257.16:45:05.77#ibcon#about to read 3, iclass 12, count 0 2006.257.16:45:05.79#ibcon#read 3, iclass 12, count 0 2006.257.16:45:05.79#ibcon#about to read 4, iclass 12, count 0 2006.257.16:45:05.79#ibcon#read 4, iclass 12, count 0 2006.257.16:45:05.79#ibcon#about to read 5, iclass 12, count 0 2006.257.16:45:05.79#ibcon#read 5, iclass 12, count 0 2006.257.16:45:05.79#ibcon#about to read 6, iclass 12, count 0 2006.257.16:45:05.79#ibcon#read 6, iclass 12, count 0 2006.257.16:45:05.79#ibcon#end of sib2, iclass 12, count 0 2006.257.16:45:05.79#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:45:05.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:45:05.79#ibcon#[27=USB\r\n] 2006.257.16:45:05.79#ibcon#*before write, iclass 12, count 0 2006.257.16:45:05.79#ibcon#enter sib2, iclass 12, count 0 2006.257.16:45:05.79#ibcon#flushed, iclass 12, count 0 2006.257.16:45:05.79#ibcon#about to write, iclass 12, count 0 2006.257.16:45:05.79#ibcon#wrote, iclass 12, count 0 2006.257.16:45:05.79#ibcon#about to read 3, iclass 12, count 0 2006.257.16:45:05.82#ibcon#read 3, iclass 12, count 0 2006.257.16:45:05.82#ibcon#about to read 4, iclass 12, count 0 2006.257.16:45:05.82#ibcon#read 4, iclass 12, count 0 2006.257.16:45:05.82#ibcon#about to read 5, iclass 12, count 0 2006.257.16:45:05.82#ibcon#read 5, iclass 12, count 0 2006.257.16:45:05.82#ibcon#about to read 6, iclass 12, count 0 2006.257.16:45:05.82#ibcon#read 6, iclass 12, count 0 2006.257.16:45:05.82#ibcon#end of sib2, iclass 12, count 0 2006.257.16:45:05.82#ibcon#*after write, iclass 12, count 0 2006.257.16:45:05.82#ibcon#*before return 0, iclass 12, count 0 2006.257.16:45:05.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:05.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.16:45:05.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:45:05.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:45:05.82$vck44/vblo=6,719.99 2006.257.16:45:05.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.16:45:05.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.16:45:05.82#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:05.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:05.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:05.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:05.82#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:45:05.82#ibcon#first serial, iclass 14, count 0 2006.257.16:45:05.82#ibcon#enter sib2, iclass 14, count 0 2006.257.16:45:05.82#ibcon#flushed, iclass 14, count 0 2006.257.16:45:05.82#ibcon#about to write, iclass 14, count 0 2006.257.16:45:05.82#ibcon#wrote, iclass 14, count 0 2006.257.16:45:05.82#ibcon#about to read 3, iclass 14, count 0 2006.257.16:45:05.84#ibcon#read 3, iclass 14, count 0 2006.257.16:45:05.84#ibcon#about to read 4, iclass 14, count 0 2006.257.16:45:05.84#ibcon#read 4, iclass 14, count 0 2006.257.16:45:05.84#ibcon#about to read 5, iclass 14, count 0 2006.257.16:45:05.84#ibcon#read 5, iclass 14, count 0 2006.257.16:45:05.84#ibcon#about to read 6, iclass 14, count 0 2006.257.16:45:05.84#ibcon#read 6, iclass 14, count 0 2006.257.16:45:05.84#ibcon#end of sib2, iclass 14, count 0 2006.257.16:45:05.84#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:45:05.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:45:05.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:45:05.84#ibcon#*before write, iclass 14, count 0 2006.257.16:45:05.84#ibcon#enter sib2, iclass 14, count 0 2006.257.16:45:05.84#ibcon#flushed, iclass 14, count 0 2006.257.16:45:05.84#ibcon#about to write, iclass 14, count 0 2006.257.16:45:05.84#ibcon#wrote, iclass 14, count 0 2006.257.16:45:05.84#ibcon#about to read 3, iclass 14, count 0 2006.257.16:45:05.88#ibcon#read 3, iclass 14, count 0 2006.257.16:45:05.88#ibcon#about to read 4, iclass 14, count 0 2006.257.16:45:05.88#ibcon#read 4, iclass 14, count 0 2006.257.16:45:05.88#ibcon#about to read 5, iclass 14, count 0 2006.257.16:45:05.88#ibcon#read 5, iclass 14, count 0 2006.257.16:45:05.88#ibcon#about to read 6, iclass 14, count 0 2006.257.16:45:05.88#ibcon#read 6, iclass 14, count 0 2006.257.16:45:05.88#ibcon#end of sib2, iclass 14, count 0 2006.257.16:45:05.88#ibcon#*after write, iclass 14, count 0 2006.257.16:45:05.88#ibcon#*before return 0, iclass 14, count 0 2006.257.16:45:05.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:05.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.16:45:05.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:45:05.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:45:05.88$vck44/vb=6,4 2006.257.16:45:05.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.16:45:05.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.16:45:05.88#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:05.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:05.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:05.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:05.94#ibcon#enter wrdev, iclass 16, count 2 2006.257.16:45:05.94#ibcon#first serial, iclass 16, count 2 2006.257.16:45:05.94#ibcon#enter sib2, iclass 16, count 2 2006.257.16:45:05.94#ibcon#flushed, iclass 16, count 2 2006.257.16:45:05.94#ibcon#about to write, iclass 16, count 2 2006.257.16:45:05.94#ibcon#wrote, iclass 16, count 2 2006.257.16:45:05.94#ibcon#about to read 3, iclass 16, count 2 2006.257.16:45:05.96#ibcon#read 3, iclass 16, count 2 2006.257.16:45:05.96#ibcon#about to read 4, iclass 16, count 2 2006.257.16:45:05.96#ibcon#read 4, iclass 16, count 2 2006.257.16:45:05.96#ibcon#about to read 5, iclass 16, count 2 2006.257.16:45:05.96#ibcon#read 5, iclass 16, count 2 2006.257.16:45:05.96#ibcon#about to read 6, iclass 16, count 2 2006.257.16:45:05.96#ibcon#read 6, iclass 16, count 2 2006.257.16:45:05.96#ibcon#end of sib2, iclass 16, count 2 2006.257.16:45:05.96#ibcon#*mode == 0, iclass 16, count 2 2006.257.16:45:05.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.16:45:05.96#ibcon#[27=AT06-04\r\n] 2006.257.16:45:05.96#ibcon#*before write, iclass 16, count 2 2006.257.16:45:05.96#ibcon#enter sib2, iclass 16, count 2 2006.257.16:45:05.96#ibcon#flushed, iclass 16, count 2 2006.257.16:45:05.96#ibcon#about to write, iclass 16, count 2 2006.257.16:45:05.96#ibcon#wrote, iclass 16, count 2 2006.257.16:45:05.96#ibcon#about to read 3, iclass 16, count 2 2006.257.16:45:05.99#ibcon#read 3, iclass 16, count 2 2006.257.16:45:05.99#ibcon#about to read 4, iclass 16, count 2 2006.257.16:45:05.99#ibcon#read 4, iclass 16, count 2 2006.257.16:45:05.99#ibcon#about to read 5, iclass 16, count 2 2006.257.16:45:05.99#ibcon#read 5, iclass 16, count 2 2006.257.16:45:05.99#ibcon#about to read 6, iclass 16, count 2 2006.257.16:45:05.99#ibcon#read 6, iclass 16, count 2 2006.257.16:45:05.99#ibcon#end of sib2, iclass 16, count 2 2006.257.16:45:05.99#ibcon#*after write, iclass 16, count 2 2006.257.16:45:05.99#ibcon#*before return 0, iclass 16, count 2 2006.257.16:45:05.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:05.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.16:45:05.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.16:45:05.99#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:05.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:06.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:06.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:06.11#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:45:06.11#ibcon#first serial, iclass 16, count 0 2006.257.16:45:06.11#ibcon#enter sib2, iclass 16, count 0 2006.257.16:45:06.11#ibcon#flushed, iclass 16, count 0 2006.257.16:45:06.11#ibcon#about to write, iclass 16, count 0 2006.257.16:45:06.11#ibcon#wrote, iclass 16, count 0 2006.257.16:45:06.11#ibcon#about to read 3, iclass 16, count 0 2006.257.16:45:06.13#ibcon#read 3, iclass 16, count 0 2006.257.16:45:06.13#ibcon#about to read 4, iclass 16, count 0 2006.257.16:45:06.13#ibcon#read 4, iclass 16, count 0 2006.257.16:45:06.13#ibcon#about to read 5, iclass 16, count 0 2006.257.16:45:06.13#ibcon#read 5, iclass 16, count 0 2006.257.16:45:06.13#ibcon#about to read 6, iclass 16, count 0 2006.257.16:45:06.13#ibcon#read 6, iclass 16, count 0 2006.257.16:45:06.13#ibcon#end of sib2, iclass 16, count 0 2006.257.16:45:06.13#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:45:06.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:45:06.13#ibcon#[27=USB\r\n] 2006.257.16:45:06.13#ibcon#*before write, iclass 16, count 0 2006.257.16:45:06.13#ibcon#enter sib2, iclass 16, count 0 2006.257.16:45:06.13#ibcon#flushed, iclass 16, count 0 2006.257.16:45:06.13#ibcon#about to write, iclass 16, count 0 2006.257.16:45:06.13#ibcon#wrote, iclass 16, count 0 2006.257.16:45:06.13#ibcon#about to read 3, iclass 16, count 0 2006.257.16:45:06.16#ibcon#read 3, iclass 16, count 0 2006.257.16:45:06.16#ibcon#about to read 4, iclass 16, count 0 2006.257.16:45:06.16#ibcon#read 4, iclass 16, count 0 2006.257.16:45:06.16#ibcon#about to read 5, iclass 16, count 0 2006.257.16:45:06.16#ibcon#read 5, iclass 16, count 0 2006.257.16:45:06.16#ibcon#about to read 6, iclass 16, count 0 2006.257.16:45:06.16#ibcon#read 6, iclass 16, count 0 2006.257.16:45:06.16#ibcon#end of sib2, iclass 16, count 0 2006.257.16:45:06.16#ibcon#*after write, iclass 16, count 0 2006.257.16:45:06.16#ibcon#*before return 0, iclass 16, count 0 2006.257.16:45:06.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:06.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.16:45:06.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:45:06.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:45:06.16$vck44/vblo=7,734.99 2006.257.16:45:06.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.16:45:06.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.16:45:06.16#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:06.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:06.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:06.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:06.16#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:45:06.16#ibcon#first serial, iclass 18, count 0 2006.257.16:45:06.16#ibcon#enter sib2, iclass 18, count 0 2006.257.16:45:06.16#ibcon#flushed, iclass 18, count 0 2006.257.16:45:06.16#ibcon#about to write, iclass 18, count 0 2006.257.16:45:06.16#ibcon#wrote, iclass 18, count 0 2006.257.16:45:06.16#ibcon#about to read 3, iclass 18, count 0 2006.257.16:45:06.18#ibcon#read 3, iclass 18, count 0 2006.257.16:45:06.18#ibcon#about to read 4, iclass 18, count 0 2006.257.16:45:06.18#ibcon#read 4, iclass 18, count 0 2006.257.16:45:06.18#ibcon#about to read 5, iclass 18, count 0 2006.257.16:45:06.18#ibcon#read 5, iclass 18, count 0 2006.257.16:45:06.18#ibcon#about to read 6, iclass 18, count 0 2006.257.16:45:06.18#ibcon#read 6, iclass 18, count 0 2006.257.16:45:06.18#ibcon#end of sib2, iclass 18, count 0 2006.257.16:45:06.18#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:45:06.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:45:06.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:45:06.18#ibcon#*before write, iclass 18, count 0 2006.257.16:45:06.18#ibcon#enter sib2, iclass 18, count 0 2006.257.16:45:06.18#ibcon#flushed, iclass 18, count 0 2006.257.16:45:06.18#ibcon#about to write, iclass 18, count 0 2006.257.16:45:06.18#ibcon#wrote, iclass 18, count 0 2006.257.16:45:06.18#ibcon#about to read 3, iclass 18, count 0 2006.257.16:45:06.22#ibcon#read 3, iclass 18, count 0 2006.257.16:45:06.22#ibcon#about to read 4, iclass 18, count 0 2006.257.16:45:06.22#ibcon#read 4, iclass 18, count 0 2006.257.16:45:06.22#ibcon#about to read 5, iclass 18, count 0 2006.257.16:45:06.22#ibcon#read 5, iclass 18, count 0 2006.257.16:45:06.22#ibcon#about to read 6, iclass 18, count 0 2006.257.16:45:06.22#ibcon#read 6, iclass 18, count 0 2006.257.16:45:06.22#ibcon#end of sib2, iclass 18, count 0 2006.257.16:45:06.22#ibcon#*after write, iclass 18, count 0 2006.257.16:45:06.22#ibcon#*before return 0, iclass 18, count 0 2006.257.16:45:06.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:06.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.16:45:06.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:45:06.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:45:06.22$vck44/vb=7,4 2006.257.16:45:06.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.16:45:06.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.16:45:06.22#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:06.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:06.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:06.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:06.28#ibcon#enter wrdev, iclass 20, count 2 2006.257.16:45:06.28#ibcon#first serial, iclass 20, count 2 2006.257.16:45:06.28#ibcon#enter sib2, iclass 20, count 2 2006.257.16:45:06.28#ibcon#flushed, iclass 20, count 2 2006.257.16:45:06.28#ibcon#about to write, iclass 20, count 2 2006.257.16:45:06.28#ibcon#wrote, iclass 20, count 2 2006.257.16:45:06.28#ibcon#about to read 3, iclass 20, count 2 2006.257.16:45:06.30#ibcon#read 3, iclass 20, count 2 2006.257.16:45:06.30#ibcon#about to read 4, iclass 20, count 2 2006.257.16:45:06.30#ibcon#read 4, iclass 20, count 2 2006.257.16:45:06.30#ibcon#about to read 5, iclass 20, count 2 2006.257.16:45:06.30#ibcon#read 5, iclass 20, count 2 2006.257.16:45:06.30#ibcon#about to read 6, iclass 20, count 2 2006.257.16:45:06.30#ibcon#read 6, iclass 20, count 2 2006.257.16:45:06.30#ibcon#end of sib2, iclass 20, count 2 2006.257.16:45:06.30#ibcon#*mode == 0, iclass 20, count 2 2006.257.16:45:06.30#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.16:45:06.30#ibcon#[27=AT07-04\r\n] 2006.257.16:45:06.30#ibcon#*before write, iclass 20, count 2 2006.257.16:45:06.30#ibcon#enter sib2, iclass 20, count 2 2006.257.16:45:06.30#ibcon#flushed, iclass 20, count 2 2006.257.16:45:06.30#ibcon#about to write, iclass 20, count 2 2006.257.16:45:06.30#ibcon#wrote, iclass 20, count 2 2006.257.16:45:06.30#ibcon#about to read 3, iclass 20, count 2 2006.257.16:45:06.33#ibcon#read 3, iclass 20, count 2 2006.257.16:45:06.33#ibcon#about to read 4, iclass 20, count 2 2006.257.16:45:06.33#ibcon#read 4, iclass 20, count 2 2006.257.16:45:06.33#ibcon#about to read 5, iclass 20, count 2 2006.257.16:45:06.33#ibcon#read 5, iclass 20, count 2 2006.257.16:45:06.33#ibcon#about to read 6, iclass 20, count 2 2006.257.16:45:06.33#ibcon#read 6, iclass 20, count 2 2006.257.16:45:06.33#ibcon#end of sib2, iclass 20, count 2 2006.257.16:45:06.33#ibcon#*after write, iclass 20, count 2 2006.257.16:45:06.33#ibcon#*before return 0, iclass 20, count 2 2006.257.16:45:06.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:06.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.16:45:06.33#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.16:45:06.33#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:06.33#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:06.45#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:06.45#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:06.45#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:45:06.45#ibcon#first serial, iclass 20, count 0 2006.257.16:45:06.45#ibcon#enter sib2, iclass 20, count 0 2006.257.16:45:06.45#ibcon#flushed, iclass 20, count 0 2006.257.16:45:06.45#ibcon#about to write, iclass 20, count 0 2006.257.16:45:06.45#ibcon#wrote, iclass 20, count 0 2006.257.16:45:06.45#ibcon#about to read 3, iclass 20, count 0 2006.257.16:45:06.47#ibcon#read 3, iclass 20, count 0 2006.257.16:45:06.47#ibcon#about to read 4, iclass 20, count 0 2006.257.16:45:06.47#ibcon#read 4, iclass 20, count 0 2006.257.16:45:06.47#ibcon#about to read 5, iclass 20, count 0 2006.257.16:45:06.47#ibcon#read 5, iclass 20, count 0 2006.257.16:45:06.47#ibcon#about to read 6, iclass 20, count 0 2006.257.16:45:06.47#ibcon#read 6, iclass 20, count 0 2006.257.16:45:06.47#ibcon#end of sib2, iclass 20, count 0 2006.257.16:45:06.47#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:45:06.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:45:06.47#ibcon#[27=USB\r\n] 2006.257.16:45:06.47#ibcon#*before write, iclass 20, count 0 2006.257.16:45:06.47#ibcon#enter sib2, iclass 20, count 0 2006.257.16:45:06.47#ibcon#flushed, iclass 20, count 0 2006.257.16:45:06.47#ibcon#about to write, iclass 20, count 0 2006.257.16:45:06.47#ibcon#wrote, iclass 20, count 0 2006.257.16:45:06.47#ibcon#about to read 3, iclass 20, count 0 2006.257.16:45:06.50#ibcon#read 3, iclass 20, count 0 2006.257.16:45:06.50#ibcon#about to read 4, iclass 20, count 0 2006.257.16:45:06.50#ibcon#read 4, iclass 20, count 0 2006.257.16:45:06.50#ibcon#about to read 5, iclass 20, count 0 2006.257.16:45:06.50#ibcon#read 5, iclass 20, count 0 2006.257.16:45:06.50#ibcon#about to read 6, iclass 20, count 0 2006.257.16:45:06.50#ibcon#read 6, iclass 20, count 0 2006.257.16:45:06.50#ibcon#end of sib2, iclass 20, count 0 2006.257.16:45:06.50#ibcon#*after write, iclass 20, count 0 2006.257.16:45:06.50#ibcon#*before return 0, iclass 20, count 0 2006.257.16:45:06.50#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:06.50#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.16:45:06.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:45:06.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:45:06.50$vck44/vblo=8,744.99 2006.257.16:45:06.50#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.16:45:06.50#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.16:45:06.50#ibcon#ireg 17 cls_cnt 0 2006.257.16:45:06.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:06.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:06.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:06.50#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:45:06.50#ibcon#first serial, iclass 22, count 0 2006.257.16:45:06.50#ibcon#enter sib2, iclass 22, count 0 2006.257.16:45:06.50#ibcon#flushed, iclass 22, count 0 2006.257.16:45:06.50#ibcon#about to write, iclass 22, count 0 2006.257.16:45:06.50#ibcon#wrote, iclass 22, count 0 2006.257.16:45:06.50#ibcon#about to read 3, iclass 22, count 0 2006.257.16:45:06.52#ibcon#read 3, iclass 22, count 0 2006.257.16:45:06.52#ibcon#about to read 4, iclass 22, count 0 2006.257.16:45:06.52#ibcon#read 4, iclass 22, count 0 2006.257.16:45:06.52#ibcon#about to read 5, iclass 22, count 0 2006.257.16:45:06.52#ibcon#read 5, iclass 22, count 0 2006.257.16:45:06.52#ibcon#about to read 6, iclass 22, count 0 2006.257.16:45:06.52#ibcon#read 6, iclass 22, count 0 2006.257.16:45:06.52#ibcon#end of sib2, iclass 22, count 0 2006.257.16:45:06.52#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:45:06.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:45:06.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:45:06.52#ibcon#*before write, iclass 22, count 0 2006.257.16:45:06.52#ibcon#enter sib2, iclass 22, count 0 2006.257.16:45:06.52#ibcon#flushed, iclass 22, count 0 2006.257.16:45:06.52#ibcon#about to write, iclass 22, count 0 2006.257.16:45:06.52#ibcon#wrote, iclass 22, count 0 2006.257.16:45:06.52#ibcon#about to read 3, iclass 22, count 0 2006.257.16:45:06.56#ibcon#read 3, iclass 22, count 0 2006.257.16:45:06.56#ibcon#about to read 4, iclass 22, count 0 2006.257.16:45:06.56#ibcon#read 4, iclass 22, count 0 2006.257.16:45:06.56#ibcon#about to read 5, iclass 22, count 0 2006.257.16:45:06.56#ibcon#read 5, iclass 22, count 0 2006.257.16:45:06.56#ibcon#about to read 6, iclass 22, count 0 2006.257.16:45:06.56#ibcon#read 6, iclass 22, count 0 2006.257.16:45:06.56#ibcon#end of sib2, iclass 22, count 0 2006.257.16:45:06.56#ibcon#*after write, iclass 22, count 0 2006.257.16:45:06.56#ibcon#*before return 0, iclass 22, count 0 2006.257.16:45:06.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:06.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:45:06.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:45:06.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:45:06.56$vck44/vb=8,4 2006.257.16:45:06.56#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.16:45:06.56#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.16:45:06.56#ibcon#ireg 11 cls_cnt 2 2006.257.16:45:06.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:06.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:06.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:06.62#ibcon#enter wrdev, iclass 24, count 2 2006.257.16:45:06.62#ibcon#first serial, iclass 24, count 2 2006.257.16:45:06.62#ibcon#enter sib2, iclass 24, count 2 2006.257.16:45:06.62#ibcon#flushed, iclass 24, count 2 2006.257.16:45:06.62#ibcon#about to write, iclass 24, count 2 2006.257.16:45:06.62#ibcon#wrote, iclass 24, count 2 2006.257.16:45:06.62#ibcon#about to read 3, iclass 24, count 2 2006.257.16:45:06.64#ibcon#read 3, iclass 24, count 2 2006.257.16:45:06.64#ibcon#about to read 4, iclass 24, count 2 2006.257.16:45:06.64#ibcon#read 4, iclass 24, count 2 2006.257.16:45:06.64#ibcon#about to read 5, iclass 24, count 2 2006.257.16:45:06.64#ibcon#read 5, iclass 24, count 2 2006.257.16:45:06.64#ibcon#about to read 6, iclass 24, count 2 2006.257.16:45:06.64#ibcon#read 6, iclass 24, count 2 2006.257.16:45:06.64#ibcon#end of sib2, iclass 24, count 2 2006.257.16:45:06.64#ibcon#*mode == 0, iclass 24, count 2 2006.257.16:45:06.64#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.16:45:06.64#ibcon#[27=AT08-04\r\n] 2006.257.16:45:06.64#ibcon#*before write, iclass 24, count 2 2006.257.16:45:06.64#ibcon#enter sib2, iclass 24, count 2 2006.257.16:45:06.64#ibcon#flushed, iclass 24, count 2 2006.257.16:45:06.64#ibcon#about to write, iclass 24, count 2 2006.257.16:45:06.64#ibcon#wrote, iclass 24, count 2 2006.257.16:45:06.64#ibcon#about to read 3, iclass 24, count 2 2006.257.16:45:06.67#ibcon#read 3, iclass 24, count 2 2006.257.16:45:06.67#ibcon#about to read 4, iclass 24, count 2 2006.257.16:45:06.67#ibcon#read 4, iclass 24, count 2 2006.257.16:45:06.67#ibcon#about to read 5, iclass 24, count 2 2006.257.16:45:06.67#ibcon#read 5, iclass 24, count 2 2006.257.16:45:06.67#ibcon#about to read 6, iclass 24, count 2 2006.257.16:45:06.67#ibcon#read 6, iclass 24, count 2 2006.257.16:45:06.67#ibcon#end of sib2, iclass 24, count 2 2006.257.16:45:06.67#ibcon#*after write, iclass 24, count 2 2006.257.16:45:06.67#ibcon#*before return 0, iclass 24, count 2 2006.257.16:45:06.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:06.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.16:45:06.67#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.16:45:06.67#ibcon#ireg 7 cls_cnt 0 2006.257.16:45:06.67#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:06.79#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:06.79#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:06.79#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:45:06.79#ibcon#first serial, iclass 24, count 0 2006.257.16:45:06.79#ibcon#enter sib2, iclass 24, count 0 2006.257.16:45:06.79#ibcon#flushed, iclass 24, count 0 2006.257.16:45:06.79#ibcon#about to write, iclass 24, count 0 2006.257.16:45:06.79#ibcon#wrote, iclass 24, count 0 2006.257.16:45:06.79#ibcon#about to read 3, iclass 24, count 0 2006.257.16:45:06.81#ibcon#read 3, iclass 24, count 0 2006.257.16:45:06.81#ibcon#about to read 4, iclass 24, count 0 2006.257.16:45:06.81#ibcon#read 4, iclass 24, count 0 2006.257.16:45:06.81#ibcon#about to read 5, iclass 24, count 0 2006.257.16:45:06.81#ibcon#read 5, iclass 24, count 0 2006.257.16:45:06.81#ibcon#about to read 6, iclass 24, count 0 2006.257.16:45:06.81#ibcon#read 6, iclass 24, count 0 2006.257.16:45:06.81#ibcon#end of sib2, iclass 24, count 0 2006.257.16:45:06.81#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:45:06.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:45:06.81#ibcon#[27=USB\r\n] 2006.257.16:45:06.81#ibcon#*before write, iclass 24, count 0 2006.257.16:45:06.81#ibcon#enter sib2, iclass 24, count 0 2006.257.16:45:06.81#ibcon#flushed, iclass 24, count 0 2006.257.16:45:06.81#ibcon#about to write, iclass 24, count 0 2006.257.16:45:06.81#ibcon#wrote, iclass 24, count 0 2006.257.16:45:06.81#ibcon#about to read 3, iclass 24, count 0 2006.257.16:45:06.84#ibcon#read 3, iclass 24, count 0 2006.257.16:45:06.84#ibcon#about to read 4, iclass 24, count 0 2006.257.16:45:06.84#ibcon#read 4, iclass 24, count 0 2006.257.16:45:06.84#ibcon#about to read 5, iclass 24, count 0 2006.257.16:45:06.84#ibcon#read 5, iclass 24, count 0 2006.257.16:45:06.84#ibcon#about to read 6, iclass 24, count 0 2006.257.16:45:06.84#ibcon#read 6, iclass 24, count 0 2006.257.16:45:06.84#ibcon#end of sib2, iclass 24, count 0 2006.257.16:45:06.84#ibcon#*after write, iclass 24, count 0 2006.257.16:45:06.84#ibcon#*before return 0, iclass 24, count 0 2006.257.16:45:06.84#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:06.84#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.16:45:06.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:45:06.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:45:06.84$vck44/vabw=wide 2006.257.16:45:06.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.16:45:06.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.16:45:06.84#ibcon#ireg 8 cls_cnt 0 2006.257.16:45:06.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:06.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:06.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:06.84#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:45:06.84#ibcon#first serial, iclass 26, count 0 2006.257.16:45:06.84#ibcon#enter sib2, iclass 26, count 0 2006.257.16:45:06.84#ibcon#flushed, iclass 26, count 0 2006.257.16:45:06.84#ibcon#about to write, iclass 26, count 0 2006.257.16:45:06.84#ibcon#wrote, iclass 26, count 0 2006.257.16:45:06.84#ibcon#about to read 3, iclass 26, count 0 2006.257.16:45:06.86#ibcon#read 3, iclass 26, count 0 2006.257.16:45:06.86#ibcon#about to read 4, iclass 26, count 0 2006.257.16:45:06.86#ibcon#read 4, iclass 26, count 0 2006.257.16:45:06.86#ibcon#about to read 5, iclass 26, count 0 2006.257.16:45:06.86#ibcon#read 5, iclass 26, count 0 2006.257.16:45:06.86#ibcon#about to read 6, iclass 26, count 0 2006.257.16:45:06.86#ibcon#read 6, iclass 26, count 0 2006.257.16:45:06.86#ibcon#end of sib2, iclass 26, count 0 2006.257.16:45:06.86#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:45:06.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:45:06.86#ibcon#[25=BW32\r\n] 2006.257.16:45:06.86#ibcon#*before write, iclass 26, count 0 2006.257.16:45:06.86#ibcon#enter sib2, iclass 26, count 0 2006.257.16:45:06.86#ibcon#flushed, iclass 26, count 0 2006.257.16:45:06.86#ibcon#about to write, iclass 26, count 0 2006.257.16:45:06.86#ibcon#wrote, iclass 26, count 0 2006.257.16:45:06.86#ibcon#about to read 3, iclass 26, count 0 2006.257.16:45:06.89#ibcon#read 3, iclass 26, count 0 2006.257.16:45:06.89#ibcon#about to read 4, iclass 26, count 0 2006.257.16:45:06.89#ibcon#read 4, iclass 26, count 0 2006.257.16:45:06.89#ibcon#about to read 5, iclass 26, count 0 2006.257.16:45:06.89#ibcon#read 5, iclass 26, count 0 2006.257.16:45:06.89#ibcon#about to read 6, iclass 26, count 0 2006.257.16:45:06.89#ibcon#read 6, iclass 26, count 0 2006.257.16:45:06.89#ibcon#end of sib2, iclass 26, count 0 2006.257.16:45:06.89#ibcon#*after write, iclass 26, count 0 2006.257.16:45:06.89#ibcon#*before return 0, iclass 26, count 0 2006.257.16:45:06.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:06.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.16:45:06.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:45:06.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:45:06.89$vck44/vbbw=wide 2006.257.16:45:06.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.16:45:06.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.16:45:06.89#ibcon#ireg 8 cls_cnt 0 2006.257.16:45:06.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:45:06.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:45:06.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:45:06.96#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:45:06.96#ibcon#first serial, iclass 28, count 0 2006.257.16:45:06.96#ibcon#enter sib2, iclass 28, count 0 2006.257.16:45:06.96#ibcon#flushed, iclass 28, count 0 2006.257.16:45:06.96#ibcon#about to write, iclass 28, count 0 2006.257.16:45:06.96#ibcon#wrote, iclass 28, count 0 2006.257.16:45:06.96#ibcon#about to read 3, iclass 28, count 0 2006.257.16:45:06.98#ibcon#read 3, iclass 28, count 0 2006.257.16:45:06.98#ibcon#about to read 4, iclass 28, count 0 2006.257.16:45:06.98#ibcon#read 4, iclass 28, count 0 2006.257.16:45:06.98#ibcon#about to read 5, iclass 28, count 0 2006.257.16:45:06.98#ibcon#read 5, iclass 28, count 0 2006.257.16:45:06.98#ibcon#about to read 6, iclass 28, count 0 2006.257.16:45:06.98#ibcon#read 6, iclass 28, count 0 2006.257.16:45:06.98#ibcon#end of sib2, iclass 28, count 0 2006.257.16:45:06.98#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:45:06.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:45:06.98#ibcon#[27=BW32\r\n] 2006.257.16:45:06.98#ibcon#*before write, iclass 28, count 0 2006.257.16:45:06.98#ibcon#enter sib2, iclass 28, count 0 2006.257.16:45:06.98#ibcon#flushed, iclass 28, count 0 2006.257.16:45:06.98#ibcon#about to write, iclass 28, count 0 2006.257.16:45:06.98#ibcon#wrote, iclass 28, count 0 2006.257.16:45:06.98#ibcon#about to read 3, iclass 28, count 0 2006.257.16:45:07.01#ibcon#read 3, iclass 28, count 0 2006.257.16:45:07.01#ibcon#about to read 4, iclass 28, count 0 2006.257.16:45:07.01#ibcon#read 4, iclass 28, count 0 2006.257.16:45:07.01#ibcon#about to read 5, iclass 28, count 0 2006.257.16:45:07.01#ibcon#read 5, iclass 28, count 0 2006.257.16:45:07.01#ibcon#about to read 6, iclass 28, count 0 2006.257.16:45:07.01#ibcon#read 6, iclass 28, count 0 2006.257.16:45:07.01#ibcon#end of sib2, iclass 28, count 0 2006.257.16:45:07.01#ibcon#*after write, iclass 28, count 0 2006.257.16:45:07.01#ibcon#*before return 0, iclass 28, count 0 2006.257.16:45:07.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:45:07.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:45:07.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:45:07.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:45:07.01$setupk4/ifdk4 2006.257.16:45:07.01$ifdk4/lo= 2006.257.16:45:07.01$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:45:07.01$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:45:07.01$ifdk4/patch= 2006.257.16:45:07.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:45:07.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:45:07.01$setupk4/!*+20s 2006.257.16:45:15.61#abcon#<5=/14 1.9 4.7 17.30 961014.2\r\n> 2006.257.16:45:15.63#abcon#{5=INTERFACE CLEAR} 2006.257.16:45:15.69#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:45:21.51$setupk4/"tpicd 2006.257.16:45:21.51$setupk4/echo=off 2006.257.16:45:21.51$setupk4/xlog=off 2006.257.16:45:21.51:!2006.257.16:47:41 2006.257.16:45:55.13#trakl#Source acquired 2006.257.16:45:55.13#flagr#flagr/antenna,acquired 2006.257.16:47:41.00:preob 2006.257.16:47:41.14/onsource/TRACKING 2006.257.16:47:41.14:!2006.257.16:47:51 2006.257.16:47:51.00:"tape 2006.257.16:47:51.00:"st=record 2006.257.16:47:51.00:data_valid=on 2006.257.16:47:51.00:midob 2006.257.16:47:52.14/onsource/TRACKING 2006.257.16:47:52.14/wx/17.32,1014.2,96 2006.257.16:47:52.27/cable/+6.4850E-03 2006.257.16:47:53.36/va/01,08,usb,yes,31,34 2006.257.16:47:53.36/va/02,07,usb,yes,34,34 2006.257.16:47:53.36/va/03,08,usb,yes,30,32 2006.257.16:47:53.36/va/04,07,usb,yes,35,37 2006.257.16:47:53.36/va/05,04,usb,yes,31,32 2006.257.16:47:53.36/va/06,04,usb,yes,35,34 2006.257.16:47:53.36/va/07,04,usb,yes,36,36 2006.257.16:47:53.36/va/08,04,usb,yes,30,36 2006.257.16:47:53.59/valo/01,524.99,yes,locked 2006.257.16:47:53.59/valo/02,534.99,yes,locked 2006.257.16:47:53.59/valo/03,564.99,yes,locked 2006.257.16:47:53.59/valo/04,624.99,yes,locked 2006.257.16:47:53.59/valo/05,734.99,yes,locked 2006.257.16:47:53.59/valo/06,814.99,yes,locked 2006.257.16:47:53.59/valo/07,864.99,yes,locked 2006.257.16:47:53.59/valo/08,884.99,yes,locked 2006.257.16:47:54.68/vb/01,04,usb,yes,31,29 2006.257.16:47:54.68/vb/02,05,usb,yes,30,29 2006.257.16:47:54.68/vb/03,04,usb,yes,31,34 2006.257.16:47:54.68/vb/04,05,usb,yes,31,30 2006.257.16:47:54.68/vb/05,04,usb,yes,27,30 2006.257.16:47:54.68/vb/06,04,usb,yes,32,28 2006.257.16:47:54.68/vb/07,04,usb,yes,32,31 2006.257.16:47:54.68/vb/08,04,usb,yes,29,33 2006.257.16:47:54.91/vblo/01,629.99,yes,locked 2006.257.16:47:54.91/vblo/02,634.99,yes,locked 2006.257.16:47:54.91/vblo/03,649.99,yes,locked 2006.257.16:47:54.91/vblo/04,679.99,yes,locked 2006.257.16:47:54.91/vblo/05,709.99,yes,locked 2006.257.16:47:54.91/vblo/06,719.99,yes,locked 2006.257.16:47:54.91/vblo/07,734.99,yes,locked 2006.257.16:47:54.91/vblo/08,744.99,yes,locked 2006.257.16:47:55.06/vabw/8 2006.257.16:47:55.21/vbbw/8 2006.257.16:47:55.30/xfe/off,on,15.5 2006.257.16:47:55.67/ifatt/23,28,28,28 2006.257.16:47:56.08/fmout-gps/S +4.59E-07 2006.257.16:47:56.11:!2006.257.16:49:21 2006.257.16:49:21.00:data_valid=off 2006.257.16:49:21.00:"et 2006.257.16:49:21.00:!+3s 2006.257.16:49:24.01:"tape 2006.257.16:49:24.01:postob 2006.257.16:49:24.20/cable/+6.4851E-03 2006.257.16:49:24.20/wx/17.33,1014.2,96 2006.257.16:49:25.07/fmout-gps/S +4.61E-07 2006.257.16:49:25.07:scan_name=257-1651,jd0609,170 2006.257.16:49:25.07:source=2201+315,220314.98,314538.3,2000.0,cw 2006.257.16:49:25.14#flagr#flagr/antenna,new-source 2006.257.16:49:26.14:checkk5 2006.257.16:49:26.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.16:49:26.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.16:49:27.14/chk_autoobs//k5ts3/ autoobs is running! 2006.257.16:49:27.49/chk_autoobs//k5ts4/ autoobs is running! 2006.257.16:49:27.82/chk_obsdata//k5ts1/T2571647??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.16:49:28.16/chk_obsdata//k5ts2/T2571647??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.16:49:28.48/chk_obsdata//k5ts3/T2571647??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.16:49:28.82/chk_obsdata//k5ts4/T2571647??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.16:49:29.47/k5log//k5ts1_log_newline 2006.257.16:49:30.14/k5log//k5ts2_log_newline 2006.257.16:49:30.79/k5log//k5ts3_log_newline 2006.257.16:49:31.45/k5log//k5ts4_log_newline 2006.257.16:49:31.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.16:49:31.47:setupk4=1 2006.257.16:49:31.47$setupk4/echo=on 2006.257.16:49:31.47$setupk4/pcalon 2006.257.16:49:31.47$pcalon/"no phase cal control is implemented here 2006.257.16:49:31.47$setupk4/"tpicd=stop 2006.257.16:49:31.47$setupk4/"rec=synch_on 2006.257.16:49:31.47$setupk4/"rec_mode=128 2006.257.16:49:31.47$setupk4/!* 2006.257.16:49:31.47$setupk4/recpk4 2006.257.16:49:31.47$recpk4/recpatch= 2006.257.16:49:31.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.16:49:31.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.16:49:31.48$setupk4/vck44 2006.257.16:49:31.48$vck44/valo=1,524.99 2006.257.16:49:31.48#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.16:49:31.48#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.16:49:31.48#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:31.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:31.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:31.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:31.48#ibcon#enter wrdev, iclass 29, count 0 2006.257.16:49:31.48#ibcon#first serial, iclass 29, count 0 2006.257.16:49:31.48#ibcon#enter sib2, iclass 29, count 0 2006.257.16:49:31.48#ibcon#flushed, iclass 29, count 0 2006.257.16:49:31.48#ibcon#about to write, iclass 29, count 0 2006.257.16:49:31.48#ibcon#wrote, iclass 29, count 0 2006.257.16:49:31.48#ibcon#about to read 3, iclass 29, count 0 2006.257.16:49:31.50#ibcon#read 3, iclass 29, count 0 2006.257.16:49:31.50#ibcon#about to read 4, iclass 29, count 0 2006.257.16:49:31.50#ibcon#read 4, iclass 29, count 0 2006.257.16:49:31.50#ibcon#about to read 5, iclass 29, count 0 2006.257.16:49:31.50#ibcon#read 5, iclass 29, count 0 2006.257.16:49:31.50#ibcon#about to read 6, iclass 29, count 0 2006.257.16:49:31.50#ibcon#read 6, iclass 29, count 0 2006.257.16:49:31.50#ibcon#end of sib2, iclass 29, count 0 2006.257.16:49:31.50#ibcon#*mode == 0, iclass 29, count 0 2006.257.16:49:31.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.16:49:31.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.16:49:31.50#ibcon#*before write, iclass 29, count 0 2006.257.16:49:31.50#ibcon#enter sib2, iclass 29, count 0 2006.257.16:49:31.50#ibcon#flushed, iclass 29, count 0 2006.257.16:49:31.50#ibcon#about to write, iclass 29, count 0 2006.257.16:49:31.50#ibcon#wrote, iclass 29, count 0 2006.257.16:49:31.50#ibcon#about to read 3, iclass 29, count 0 2006.257.16:49:31.55#ibcon#read 3, iclass 29, count 0 2006.257.16:49:31.55#ibcon#about to read 4, iclass 29, count 0 2006.257.16:49:31.55#ibcon#read 4, iclass 29, count 0 2006.257.16:49:31.55#ibcon#about to read 5, iclass 29, count 0 2006.257.16:49:31.55#ibcon#read 5, iclass 29, count 0 2006.257.16:49:31.55#ibcon#about to read 6, iclass 29, count 0 2006.257.16:49:31.55#ibcon#read 6, iclass 29, count 0 2006.257.16:49:31.55#ibcon#end of sib2, iclass 29, count 0 2006.257.16:49:31.55#ibcon#*after write, iclass 29, count 0 2006.257.16:49:31.55#ibcon#*before return 0, iclass 29, count 0 2006.257.16:49:31.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:31.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:31.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.16:49:31.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.16:49:31.55$vck44/va=1,8 2006.257.16:49:31.55#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.16:49:31.55#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.16:49:31.55#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:31.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:31.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:31.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:31.55#ibcon#enter wrdev, iclass 31, count 2 2006.257.16:49:31.55#ibcon#first serial, iclass 31, count 2 2006.257.16:49:31.55#ibcon#enter sib2, iclass 31, count 2 2006.257.16:49:31.55#ibcon#flushed, iclass 31, count 2 2006.257.16:49:31.55#ibcon#about to write, iclass 31, count 2 2006.257.16:49:31.55#ibcon#wrote, iclass 31, count 2 2006.257.16:49:31.55#ibcon#about to read 3, iclass 31, count 2 2006.257.16:49:31.57#ibcon#read 3, iclass 31, count 2 2006.257.16:49:31.57#ibcon#about to read 4, iclass 31, count 2 2006.257.16:49:31.57#ibcon#read 4, iclass 31, count 2 2006.257.16:49:31.57#ibcon#about to read 5, iclass 31, count 2 2006.257.16:49:31.57#ibcon#read 5, iclass 31, count 2 2006.257.16:49:31.57#ibcon#about to read 6, iclass 31, count 2 2006.257.16:49:31.57#ibcon#read 6, iclass 31, count 2 2006.257.16:49:31.57#ibcon#end of sib2, iclass 31, count 2 2006.257.16:49:31.57#ibcon#*mode == 0, iclass 31, count 2 2006.257.16:49:31.57#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.16:49:31.57#ibcon#[25=AT01-08\r\n] 2006.257.16:49:31.57#ibcon#*before write, iclass 31, count 2 2006.257.16:49:31.57#ibcon#enter sib2, iclass 31, count 2 2006.257.16:49:31.57#ibcon#flushed, iclass 31, count 2 2006.257.16:49:31.57#ibcon#about to write, iclass 31, count 2 2006.257.16:49:31.57#ibcon#wrote, iclass 31, count 2 2006.257.16:49:31.57#ibcon#about to read 3, iclass 31, count 2 2006.257.16:49:31.60#ibcon#read 3, iclass 31, count 2 2006.257.16:49:31.60#ibcon#about to read 4, iclass 31, count 2 2006.257.16:49:31.60#ibcon#read 4, iclass 31, count 2 2006.257.16:49:31.60#ibcon#about to read 5, iclass 31, count 2 2006.257.16:49:31.60#ibcon#read 5, iclass 31, count 2 2006.257.16:49:31.60#ibcon#about to read 6, iclass 31, count 2 2006.257.16:49:31.60#ibcon#read 6, iclass 31, count 2 2006.257.16:49:31.60#ibcon#end of sib2, iclass 31, count 2 2006.257.16:49:31.60#ibcon#*after write, iclass 31, count 2 2006.257.16:49:31.60#ibcon#*before return 0, iclass 31, count 2 2006.257.16:49:31.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:31.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:31.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.16:49:31.60#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:31.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:31.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:31.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:31.72#ibcon#enter wrdev, iclass 31, count 0 2006.257.16:49:31.72#ibcon#first serial, iclass 31, count 0 2006.257.16:49:31.72#ibcon#enter sib2, iclass 31, count 0 2006.257.16:49:31.72#ibcon#flushed, iclass 31, count 0 2006.257.16:49:31.72#ibcon#about to write, iclass 31, count 0 2006.257.16:49:31.72#ibcon#wrote, iclass 31, count 0 2006.257.16:49:31.72#ibcon#about to read 3, iclass 31, count 0 2006.257.16:49:31.74#ibcon#read 3, iclass 31, count 0 2006.257.16:49:31.74#ibcon#about to read 4, iclass 31, count 0 2006.257.16:49:31.74#ibcon#read 4, iclass 31, count 0 2006.257.16:49:31.74#ibcon#about to read 5, iclass 31, count 0 2006.257.16:49:31.74#ibcon#read 5, iclass 31, count 0 2006.257.16:49:31.74#ibcon#about to read 6, iclass 31, count 0 2006.257.16:49:31.74#ibcon#read 6, iclass 31, count 0 2006.257.16:49:31.74#ibcon#end of sib2, iclass 31, count 0 2006.257.16:49:31.74#ibcon#*mode == 0, iclass 31, count 0 2006.257.16:49:31.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.16:49:31.74#ibcon#[25=USB\r\n] 2006.257.16:49:31.74#ibcon#*before write, iclass 31, count 0 2006.257.16:49:31.74#ibcon#enter sib2, iclass 31, count 0 2006.257.16:49:31.74#ibcon#flushed, iclass 31, count 0 2006.257.16:49:31.74#ibcon#about to write, iclass 31, count 0 2006.257.16:49:31.74#ibcon#wrote, iclass 31, count 0 2006.257.16:49:31.74#ibcon#about to read 3, iclass 31, count 0 2006.257.16:49:31.77#ibcon#read 3, iclass 31, count 0 2006.257.16:49:31.77#ibcon#about to read 4, iclass 31, count 0 2006.257.16:49:31.77#ibcon#read 4, iclass 31, count 0 2006.257.16:49:31.77#ibcon#about to read 5, iclass 31, count 0 2006.257.16:49:31.77#ibcon#read 5, iclass 31, count 0 2006.257.16:49:31.77#ibcon#about to read 6, iclass 31, count 0 2006.257.16:49:31.77#ibcon#read 6, iclass 31, count 0 2006.257.16:49:31.77#ibcon#end of sib2, iclass 31, count 0 2006.257.16:49:31.77#ibcon#*after write, iclass 31, count 0 2006.257.16:49:31.77#ibcon#*before return 0, iclass 31, count 0 2006.257.16:49:31.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:31.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:31.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.16:49:31.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.16:49:31.77$vck44/valo=2,534.99 2006.257.16:49:31.77#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.16:49:31.77#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.16:49:31.77#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:31.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:31.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:31.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:31.77#ibcon#enter wrdev, iclass 33, count 0 2006.257.16:49:31.77#ibcon#first serial, iclass 33, count 0 2006.257.16:49:31.77#ibcon#enter sib2, iclass 33, count 0 2006.257.16:49:31.77#ibcon#flushed, iclass 33, count 0 2006.257.16:49:31.77#ibcon#about to write, iclass 33, count 0 2006.257.16:49:31.77#ibcon#wrote, iclass 33, count 0 2006.257.16:49:31.77#ibcon#about to read 3, iclass 33, count 0 2006.257.16:49:31.79#ibcon#read 3, iclass 33, count 0 2006.257.16:49:31.79#ibcon#about to read 4, iclass 33, count 0 2006.257.16:49:31.79#ibcon#read 4, iclass 33, count 0 2006.257.16:49:31.79#ibcon#about to read 5, iclass 33, count 0 2006.257.16:49:31.79#ibcon#read 5, iclass 33, count 0 2006.257.16:49:31.79#ibcon#about to read 6, iclass 33, count 0 2006.257.16:49:31.79#ibcon#read 6, iclass 33, count 0 2006.257.16:49:31.79#ibcon#end of sib2, iclass 33, count 0 2006.257.16:49:31.79#ibcon#*mode == 0, iclass 33, count 0 2006.257.16:49:31.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.16:49:31.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.16:49:31.79#ibcon#*before write, iclass 33, count 0 2006.257.16:49:31.79#ibcon#enter sib2, iclass 33, count 0 2006.257.16:49:31.79#ibcon#flushed, iclass 33, count 0 2006.257.16:49:31.79#ibcon#about to write, iclass 33, count 0 2006.257.16:49:31.79#ibcon#wrote, iclass 33, count 0 2006.257.16:49:31.79#ibcon#about to read 3, iclass 33, count 0 2006.257.16:49:31.83#ibcon#read 3, iclass 33, count 0 2006.257.16:49:31.83#ibcon#about to read 4, iclass 33, count 0 2006.257.16:49:31.83#ibcon#read 4, iclass 33, count 0 2006.257.16:49:31.83#ibcon#about to read 5, iclass 33, count 0 2006.257.16:49:31.83#ibcon#read 5, iclass 33, count 0 2006.257.16:49:31.83#ibcon#about to read 6, iclass 33, count 0 2006.257.16:49:31.83#ibcon#read 6, iclass 33, count 0 2006.257.16:49:31.83#ibcon#end of sib2, iclass 33, count 0 2006.257.16:49:31.83#ibcon#*after write, iclass 33, count 0 2006.257.16:49:31.83#ibcon#*before return 0, iclass 33, count 0 2006.257.16:49:31.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:31.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:31.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.16:49:31.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.16:49:31.83$vck44/va=2,7 2006.257.16:49:31.83#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.16:49:31.83#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.16:49:31.83#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:31.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:31.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:31.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:31.89#ibcon#enter wrdev, iclass 35, count 2 2006.257.16:49:31.89#ibcon#first serial, iclass 35, count 2 2006.257.16:49:31.89#ibcon#enter sib2, iclass 35, count 2 2006.257.16:49:31.89#ibcon#flushed, iclass 35, count 2 2006.257.16:49:31.89#ibcon#about to write, iclass 35, count 2 2006.257.16:49:31.89#ibcon#wrote, iclass 35, count 2 2006.257.16:49:31.89#ibcon#about to read 3, iclass 35, count 2 2006.257.16:49:31.91#ibcon#read 3, iclass 35, count 2 2006.257.16:49:31.91#ibcon#about to read 4, iclass 35, count 2 2006.257.16:49:31.91#ibcon#read 4, iclass 35, count 2 2006.257.16:49:31.91#ibcon#about to read 5, iclass 35, count 2 2006.257.16:49:31.91#ibcon#read 5, iclass 35, count 2 2006.257.16:49:31.91#ibcon#about to read 6, iclass 35, count 2 2006.257.16:49:31.91#ibcon#read 6, iclass 35, count 2 2006.257.16:49:31.91#ibcon#end of sib2, iclass 35, count 2 2006.257.16:49:31.91#ibcon#*mode == 0, iclass 35, count 2 2006.257.16:49:31.91#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.16:49:31.91#ibcon#[25=AT02-07\r\n] 2006.257.16:49:31.91#ibcon#*before write, iclass 35, count 2 2006.257.16:49:31.91#ibcon#enter sib2, iclass 35, count 2 2006.257.16:49:31.91#ibcon#flushed, iclass 35, count 2 2006.257.16:49:31.91#ibcon#about to write, iclass 35, count 2 2006.257.16:49:31.91#ibcon#wrote, iclass 35, count 2 2006.257.16:49:31.91#ibcon#about to read 3, iclass 35, count 2 2006.257.16:49:31.94#ibcon#read 3, iclass 35, count 2 2006.257.16:49:31.94#ibcon#about to read 4, iclass 35, count 2 2006.257.16:49:31.94#ibcon#read 4, iclass 35, count 2 2006.257.16:49:31.94#ibcon#about to read 5, iclass 35, count 2 2006.257.16:49:31.94#ibcon#read 5, iclass 35, count 2 2006.257.16:49:31.94#ibcon#about to read 6, iclass 35, count 2 2006.257.16:49:31.94#ibcon#read 6, iclass 35, count 2 2006.257.16:49:31.94#ibcon#end of sib2, iclass 35, count 2 2006.257.16:49:31.94#ibcon#*after write, iclass 35, count 2 2006.257.16:49:31.94#ibcon#*before return 0, iclass 35, count 2 2006.257.16:49:31.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:31.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:31.94#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.16:49:31.94#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:31.94#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:32.06#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:32.06#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:32.06#ibcon#enter wrdev, iclass 35, count 0 2006.257.16:49:32.06#ibcon#first serial, iclass 35, count 0 2006.257.16:49:32.06#ibcon#enter sib2, iclass 35, count 0 2006.257.16:49:32.06#ibcon#flushed, iclass 35, count 0 2006.257.16:49:32.06#ibcon#about to write, iclass 35, count 0 2006.257.16:49:32.06#ibcon#wrote, iclass 35, count 0 2006.257.16:49:32.06#ibcon#about to read 3, iclass 35, count 0 2006.257.16:49:32.08#ibcon#read 3, iclass 35, count 0 2006.257.16:49:32.08#ibcon#about to read 4, iclass 35, count 0 2006.257.16:49:32.08#ibcon#read 4, iclass 35, count 0 2006.257.16:49:32.08#ibcon#about to read 5, iclass 35, count 0 2006.257.16:49:32.08#ibcon#read 5, iclass 35, count 0 2006.257.16:49:32.08#ibcon#about to read 6, iclass 35, count 0 2006.257.16:49:32.08#ibcon#read 6, iclass 35, count 0 2006.257.16:49:32.08#ibcon#end of sib2, iclass 35, count 0 2006.257.16:49:32.08#ibcon#*mode == 0, iclass 35, count 0 2006.257.16:49:32.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.16:49:32.08#ibcon#[25=USB\r\n] 2006.257.16:49:32.08#ibcon#*before write, iclass 35, count 0 2006.257.16:49:32.08#ibcon#enter sib2, iclass 35, count 0 2006.257.16:49:32.08#ibcon#flushed, iclass 35, count 0 2006.257.16:49:32.08#ibcon#about to write, iclass 35, count 0 2006.257.16:49:32.08#ibcon#wrote, iclass 35, count 0 2006.257.16:49:32.08#ibcon#about to read 3, iclass 35, count 0 2006.257.16:49:32.11#ibcon#read 3, iclass 35, count 0 2006.257.16:49:32.11#ibcon#about to read 4, iclass 35, count 0 2006.257.16:49:32.11#ibcon#read 4, iclass 35, count 0 2006.257.16:49:32.11#ibcon#about to read 5, iclass 35, count 0 2006.257.16:49:32.11#ibcon#read 5, iclass 35, count 0 2006.257.16:49:32.11#ibcon#about to read 6, iclass 35, count 0 2006.257.16:49:32.11#ibcon#read 6, iclass 35, count 0 2006.257.16:49:32.11#ibcon#end of sib2, iclass 35, count 0 2006.257.16:49:32.11#ibcon#*after write, iclass 35, count 0 2006.257.16:49:32.11#ibcon#*before return 0, iclass 35, count 0 2006.257.16:49:32.11#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:32.11#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:32.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.16:49:32.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.16:49:32.11$vck44/valo=3,564.99 2006.257.16:49:32.11#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.16:49:32.11#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.16:49:32.11#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:32.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:32.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:32.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:32.11#ibcon#enter wrdev, iclass 37, count 0 2006.257.16:49:32.11#ibcon#first serial, iclass 37, count 0 2006.257.16:49:32.11#ibcon#enter sib2, iclass 37, count 0 2006.257.16:49:32.11#ibcon#flushed, iclass 37, count 0 2006.257.16:49:32.11#ibcon#about to write, iclass 37, count 0 2006.257.16:49:32.11#ibcon#wrote, iclass 37, count 0 2006.257.16:49:32.11#ibcon#about to read 3, iclass 37, count 0 2006.257.16:49:32.13#ibcon#read 3, iclass 37, count 0 2006.257.16:49:32.13#ibcon#about to read 4, iclass 37, count 0 2006.257.16:49:32.13#ibcon#read 4, iclass 37, count 0 2006.257.16:49:32.13#ibcon#about to read 5, iclass 37, count 0 2006.257.16:49:32.13#ibcon#read 5, iclass 37, count 0 2006.257.16:49:32.13#ibcon#about to read 6, iclass 37, count 0 2006.257.16:49:32.13#ibcon#read 6, iclass 37, count 0 2006.257.16:49:32.13#ibcon#end of sib2, iclass 37, count 0 2006.257.16:49:32.13#ibcon#*mode == 0, iclass 37, count 0 2006.257.16:49:32.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.16:49:32.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.16:49:32.13#ibcon#*before write, iclass 37, count 0 2006.257.16:49:32.13#ibcon#enter sib2, iclass 37, count 0 2006.257.16:49:32.13#ibcon#flushed, iclass 37, count 0 2006.257.16:49:32.13#ibcon#about to write, iclass 37, count 0 2006.257.16:49:32.13#ibcon#wrote, iclass 37, count 0 2006.257.16:49:32.13#ibcon#about to read 3, iclass 37, count 0 2006.257.16:49:32.17#ibcon#read 3, iclass 37, count 0 2006.257.16:49:32.17#ibcon#about to read 4, iclass 37, count 0 2006.257.16:49:32.17#ibcon#read 4, iclass 37, count 0 2006.257.16:49:32.17#ibcon#about to read 5, iclass 37, count 0 2006.257.16:49:32.17#ibcon#read 5, iclass 37, count 0 2006.257.16:49:32.17#ibcon#about to read 6, iclass 37, count 0 2006.257.16:49:32.17#ibcon#read 6, iclass 37, count 0 2006.257.16:49:32.17#ibcon#end of sib2, iclass 37, count 0 2006.257.16:49:32.17#ibcon#*after write, iclass 37, count 0 2006.257.16:49:32.17#ibcon#*before return 0, iclass 37, count 0 2006.257.16:49:32.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:32.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:32.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.16:49:32.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.16:49:32.17$vck44/va=3,8 2006.257.16:49:32.17#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.16:49:32.17#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.16:49:32.17#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:32.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:32.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:32.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:32.23#ibcon#enter wrdev, iclass 39, count 2 2006.257.16:49:32.23#ibcon#first serial, iclass 39, count 2 2006.257.16:49:32.23#ibcon#enter sib2, iclass 39, count 2 2006.257.16:49:32.23#ibcon#flushed, iclass 39, count 2 2006.257.16:49:32.23#ibcon#about to write, iclass 39, count 2 2006.257.16:49:32.23#ibcon#wrote, iclass 39, count 2 2006.257.16:49:32.23#ibcon#about to read 3, iclass 39, count 2 2006.257.16:49:32.25#ibcon#read 3, iclass 39, count 2 2006.257.16:49:32.25#ibcon#about to read 4, iclass 39, count 2 2006.257.16:49:32.25#ibcon#read 4, iclass 39, count 2 2006.257.16:49:32.25#ibcon#about to read 5, iclass 39, count 2 2006.257.16:49:32.25#ibcon#read 5, iclass 39, count 2 2006.257.16:49:32.25#ibcon#about to read 6, iclass 39, count 2 2006.257.16:49:32.25#ibcon#read 6, iclass 39, count 2 2006.257.16:49:32.25#ibcon#end of sib2, iclass 39, count 2 2006.257.16:49:32.25#ibcon#*mode == 0, iclass 39, count 2 2006.257.16:49:32.25#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.16:49:32.25#ibcon#[25=AT03-08\r\n] 2006.257.16:49:32.25#ibcon#*before write, iclass 39, count 2 2006.257.16:49:32.25#ibcon#enter sib2, iclass 39, count 2 2006.257.16:49:32.25#ibcon#flushed, iclass 39, count 2 2006.257.16:49:32.25#ibcon#about to write, iclass 39, count 2 2006.257.16:49:32.25#ibcon#wrote, iclass 39, count 2 2006.257.16:49:32.25#ibcon#about to read 3, iclass 39, count 2 2006.257.16:49:32.28#ibcon#read 3, iclass 39, count 2 2006.257.16:49:32.28#ibcon#about to read 4, iclass 39, count 2 2006.257.16:49:32.28#ibcon#read 4, iclass 39, count 2 2006.257.16:49:32.28#ibcon#about to read 5, iclass 39, count 2 2006.257.16:49:32.28#ibcon#read 5, iclass 39, count 2 2006.257.16:49:32.28#ibcon#about to read 6, iclass 39, count 2 2006.257.16:49:32.28#ibcon#read 6, iclass 39, count 2 2006.257.16:49:32.28#ibcon#end of sib2, iclass 39, count 2 2006.257.16:49:32.28#ibcon#*after write, iclass 39, count 2 2006.257.16:49:32.28#ibcon#*before return 0, iclass 39, count 2 2006.257.16:49:32.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:32.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:32.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.16:49:32.28#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:32.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:32.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:32.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:32.40#ibcon#enter wrdev, iclass 39, count 0 2006.257.16:49:32.40#ibcon#first serial, iclass 39, count 0 2006.257.16:49:32.40#ibcon#enter sib2, iclass 39, count 0 2006.257.16:49:32.40#ibcon#flushed, iclass 39, count 0 2006.257.16:49:32.40#ibcon#about to write, iclass 39, count 0 2006.257.16:49:32.40#ibcon#wrote, iclass 39, count 0 2006.257.16:49:32.40#ibcon#about to read 3, iclass 39, count 0 2006.257.16:49:32.42#ibcon#read 3, iclass 39, count 0 2006.257.16:49:32.42#ibcon#about to read 4, iclass 39, count 0 2006.257.16:49:32.42#ibcon#read 4, iclass 39, count 0 2006.257.16:49:32.42#ibcon#about to read 5, iclass 39, count 0 2006.257.16:49:32.42#ibcon#read 5, iclass 39, count 0 2006.257.16:49:32.42#ibcon#about to read 6, iclass 39, count 0 2006.257.16:49:32.42#ibcon#read 6, iclass 39, count 0 2006.257.16:49:32.42#ibcon#end of sib2, iclass 39, count 0 2006.257.16:49:32.42#ibcon#*mode == 0, iclass 39, count 0 2006.257.16:49:32.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.16:49:32.42#ibcon#[25=USB\r\n] 2006.257.16:49:32.42#ibcon#*before write, iclass 39, count 0 2006.257.16:49:32.42#ibcon#enter sib2, iclass 39, count 0 2006.257.16:49:32.42#ibcon#flushed, iclass 39, count 0 2006.257.16:49:32.42#ibcon#about to write, iclass 39, count 0 2006.257.16:49:32.42#ibcon#wrote, iclass 39, count 0 2006.257.16:49:32.42#ibcon#about to read 3, iclass 39, count 0 2006.257.16:49:32.45#ibcon#read 3, iclass 39, count 0 2006.257.16:49:32.45#ibcon#about to read 4, iclass 39, count 0 2006.257.16:49:32.45#ibcon#read 4, iclass 39, count 0 2006.257.16:49:32.45#ibcon#about to read 5, iclass 39, count 0 2006.257.16:49:32.45#ibcon#read 5, iclass 39, count 0 2006.257.16:49:32.45#ibcon#about to read 6, iclass 39, count 0 2006.257.16:49:32.45#ibcon#read 6, iclass 39, count 0 2006.257.16:49:32.45#ibcon#end of sib2, iclass 39, count 0 2006.257.16:49:32.45#ibcon#*after write, iclass 39, count 0 2006.257.16:49:32.45#ibcon#*before return 0, iclass 39, count 0 2006.257.16:49:32.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:32.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:32.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.16:49:32.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.16:49:32.45$vck44/valo=4,624.99 2006.257.16:49:32.45#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.16:49:32.45#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.16:49:32.45#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:32.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:32.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:32.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:32.45#ibcon#enter wrdev, iclass 3, count 0 2006.257.16:49:32.45#ibcon#first serial, iclass 3, count 0 2006.257.16:49:32.45#ibcon#enter sib2, iclass 3, count 0 2006.257.16:49:32.45#ibcon#flushed, iclass 3, count 0 2006.257.16:49:32.45#ibcon#about to write, iclass 3, count 0 2006.257.16:49:32.45#ibcon#wrote, iclass 3, count 0 2006.257.16:49:32.45#ibcon#about to read 3, iclass 3, count 0 2006.257.16:49:32.47#ibcon#read 3, iclass 3, count 0 2006.257.16:49:32.47#ibcon#about to read 4, iclass 3, count 0 2006.257.16:49:32.47#ibcon#read 4, iclass 3, count 0 2006.257.16:49:32.47#ibcon#about to read 5, iclass 3, count 0 2006.257.16:49:32.47#ibcon#read 5, iclass 3, count 0 2006.257.16:49:32.47#ibcon#about to read 6, iclass 3, count 0 2006.257.16:49:32.47#ibcon#read 6, iclass 3, count 0 2006.257.16:49:32.47#ibcon#end of sib2, iclass 3, count 0 2006.257.16:49:32.47#ibcon#*mode == 0, iclass 3, count 0 2006.257.16:49:32.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.16:49:32.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.16:49:32.47#ibcon#*before write, iclass 3, count 0 2006.257.16:49:32.47#ibcon#enter sib2, iclass 3, count 0 2006.257.16:49:32.47#ibcon#flushed, iclass 3, count 0 2006.257.16:49:32.47#ibcon#about to write, iclass 3, count 0 2006.257.16:49:32.47#ibcon#wrote, iclass 3, count 0 2006.257.16:49:32.47#ibcon#about to read 3, iclass 3, count 0 2006.257.16:49:32.51#ibcon#read 3, iclass 3, count 0 2006.257.16:49:32.51#ibcon#about to read 4, iclass 3, count 0 2006.257.16:49:32.51#ibcon#read 4, iclass 3, count 0 2006.257.16:49:32.51#ibcon#about to read 5, iclass 3, count 0 2006.257.16:49:32.51#ibcon#read 5, iclass 3, count 0 2006.257.16:49:32.51#ibcon#about to read 6, iclass 3, count 0 2006.257.16:49:32.51#ibcon#read 6, iclass 3, count 0 2006.257.16:49:32.51#ibcon#end of sib2, iclass 3, count 0 2006.257.16:49:32.51#ibcon#*after write, iclass 3, count 0 2006.257.16:49:32.51#ibcon#*before return 0, iclass 3, count 0 2006.257.16:49:32.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:32.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:32.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.16:49:32.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.16:49:32.51$vck44/va=4,7 2006.257.16:49:32.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.16:49:32.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.16:49:32.51#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:32.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:32.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:32.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:32.57#ibcon#enter wrdev, iclass 5, count 2 2006.257.16:49:32.57#ibcon#first serial, iclass 5, count 2 2006.257.16:49:32.57#ibcon#enter sib2, iclass 5, count 2 2006.257.16:49:32.57#ibcon#flushed, iclass 5, count 2 2006.257.16:49:32.57#ibcon#about to write, iclass 5, count 2 2006.257.16:49:32.57#ibcon#wrote, iclass 5, count 2 2006.257.16:49:32.57#ibcon#about to read 3, iclass 5, count 2 2006.257.16:49:32.59#ibcon#read 3, iclass 5, count 2 2006.257.16:49:32.59#ibcon#about to read 4, iclass 5, count 2 2006.257.16:49:32.59#ibcon#read 4, iclass 5, count 2 2006.257.16:49:32.59#ibcon#about to read 5, iclass 5, count 2 2006.257.16:49:32.59#ibcon#read 5, iclass 5, count 2 2006.257.16:49:32.59#ibcon#about to read 6, iclass 5, count 2 2006.257.16:49:32.59#ibcon#read 6, iclass 5, count 2 2006.257.16:49:32.59#ibcon#end of sib2, iclass 5, count 2 2006.257.16:49:32.59#ibcon#*mode == 0, iclass 5, count 2 2006.257.16:49:32.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.16:49:32.59#ibcon#[25=AT04-07\r\n] 2006.257.16:49:32.59#ibcon#*before write, iclass 5, count 2 2006.257.16:49:32.59#ibcon#enter sib2, iclass 5, count 2 2006.257.16:49:32.59#ibcon#flushed, iclass 5, count 2 2006.257.16:49:32.59#ibcon#about to write, iclass 5, count 2 2006.257.16:49:32.59#ibcon#wrote, iclass 5, count 2 2006.257.16:49:32.59#ibcon#about to read 3, iclass 5, count 2 2006.257.16:49:32.62#ibcon#read 3, iclass 5, count 2 2006.257.16:49:32.62#ibcon#about to read 4, iclass 5, count 2 2006.257.16:49:32.62#ibcon#read 4, iclass 5, count 2 2006.257.16:49:32.62#ibcon#about to read 5, iclass 5, count 2 2006.257.16:49:32.62#ibcon#read 5, iclass 5, count 2 2006.257.16:49:32.62#ibcon#about to read 6, iclass 5, count 2 2006.257.16:49:32.62#ibcon#read 6, iclass 5, count 2 2006.257.16:49:32.62#ibcon#end of sib2, iclass 5, count 2 2006.257.16:49:32.62#ibcon#*after write, iclass 5, count 2 2006.257.16:49:32.62#ibcon#*before return 0, iclass 5, count 2 2006.257.16:49:32.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:32.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:32.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.16:49:32.62#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:32.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:32.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:32.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:32.74#ibcon#enter wrdev, iclass 5, count 0 2006.257.16:49:32.74#ibcon#first serial, iclass 5, count 0 2006.257.16:49:32.74#ibcon#enter sib2, iclass 5, count 0 2006.257.16:49:32.74#ibcon#flushed, iclass 5, count 0 2006.257.16:49:32.74#ibcon#about to write, iclass 5, count 0 2006.257.16:49:32.74#ibcon#wrote, iclass 5, count 0 2006.257.16:49:32.74#ibcon#about to read 3, iclass 5, count 0 2006.257.16:49:32.76#ibcon#read 3, iclass 5, count 0 2006.257.16:49:32.76#ibcon#about to read 4, iclass 5, count 0 2006.257.16:49:32.76#ibcon#read 4, iclass 5, count 0 2006.257.16:49:32.76#ibcon#about to read 5, iclass 5, count 0 2006.257.16:49:32.76#ibcon#read 5, iclass 5, count 0 2006.257.16:49:32.76#ibcon#about to read 6, iclass 5, count 0 2006.257.16:49:32.76#ibcon#read 6, iclass 5, count 0 2006.257.16:49:32.76#ibcon#end of sib2, iclass 5, count 0 2006.257.16:49:32.76#ibcon#*mode == 0, iclass 5, count 0 2006.257.16:49:32.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.16:49:32.76#ibcon#[25=USB\r\n] 2006.257.16:49:32.76#ibcon#*before write, iclass 5, count 0 2006.257.16:49:32.76#ibcon#enter sib2, iclass 5, count 0 2006.257.16:49:32.76#ibcon#flushed, iclass 5, count 0 2006.257.16:49:32.76#ibcon#about to write, iclass 5, count 0 2006.257.16:49:32.76#ibcon#wrote, iclass 5, count 0 2006.257.16:49:32.76#ibcon#about to read 3, iclass 5, count 0 2006.257.16:49:32.79#ibcon#read 3, iclass 5, count 0 2006.257.16:49:32.79#ibcon#about to read 4, iclass 5, count 0 2006.257.16:49:32.79#ibcon#read 4, iclass 5, count 0 2006.257.16:49:32.79#ibcon#about to read 5, iclass 5, count 0 2006.257.16:49:32.79#ibcon#read 5, iclass 5, count 0 2006.257.16:49:32.79#ibcon#about to read 6, iclass 5, count 0 2006.257.16:49:32.79#ibcon#read 6, iclass 5, count 0 2006.257.16:49:32.79#ibcon#end of sib2, iclass 5, count 0 2006.257.16:49:32.79#ibcon#*after write, iclass 5, count 0 2006.257.16:49:32.79#ibcon#*before return 0, iclass 5, count 0 2006.257.16:49:32.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:32.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:32.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.16:49:32.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.16:49:32.79$vck44/valo=5,734.99 2006.257.16:49:32.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.16:49:32.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.16:49:32.79#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:32.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:32.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:32.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:32.79#ibcon#enter wrdev, iclass 7, count 0 2006.257.16:49:32.79#ibcon#first serial, iclass 7, count 0 2006.257.16:49:32.79#ibcon#enter sib2, iclass 7, count 0 2006.257.16:49:32.79#ibcon#flushed, iclass 7, count 0 2006.257.16:49:32.79#ibcon#about to write, iclass 7, count 0 2006.257.16:49:32.79#ibcon#wrote, iclass 7, count 0 2006.257.16:49:32.79#ibcon#about to read 3, iclass 7, count 0 2006.257.16:49:32.81#ibcon#read 3, iclass 7, count 0 2006.257.16:49:32.81#ibcon#about to read 4, iclass 7, count 0 2006.257.16:49:32.81#ibcon#read 4, iclass 7, count 0 2006.257.16:49:32.81#ibcon#about to read 5, iclass 7, count 0 2006.257.16:49:32.81#ibcon#read 5, iclass 7, count 0 2006.257.16:49:32.81#ibcon#about to read 6, iclass 7, count 0 2006.257.16:49:32.81#ibcon#read 6, iclass 7, count 0 2006.257.16:49:32.81#ibcon#end of sib2, iclass 7, count 0 2006.257.16:49:32.81#ibcon#*mode == 0, iclass 7, count 0 2006.257.16:49:32.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.16:49:32.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.16:49:32.81#ibcon#*before write, iclass 7, count 0 2006.257.16:49:32.81#ibcon#enter sib2, iclass 7, count 0 2006.257.16:49:32.81#ibcon#flushed, iclass 7, count 0 2006.257.16:49:32.81#ibcon#about to write, iclass 7, count 0 2006.257.16:49:32.81#ibcon#wrote, iclass 7, count 0 2006.257.16:49:32.81#ibcon#about to read 3, iclass 7, count 0 2006.257.16:49:32.85#ibcon#read 3, iclass 7, count 0 2006.257.16:49:32.85#ibcon#about to read 4, iclass 7, count 0 2006.257.16:49:32.85#ibcon#read 4, iclass 7, count 0 2006.257.16:49:32.85#ibcon#about to read 5, iclass 7, count 0 2006.257.16:49:32.85#ibcon#read 5, iclass 7, count 0 2006.257.16:49:32.85#ibcon#about to read 6, iclass 7, count 0 2006.257.16:49:32.85#ibcon#read 6, iclass 7, count 0 2006.257.16:49:32.85#ibcon#end of sib2, iclass 7, count 0 2006.257.16:49:32.85#ibcon#*after write, iclass 7, count 0 2006.257.16:49:32.85#ibcon#*before return 0, iclass 7, count 0 2006.257.16:49:32.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:32.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:32.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.16:49:32.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.16:49:32.85$vck44/va=5,4 2006.257.16:49:32.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.16:49:32.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.16:49:32.85#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:32.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:32.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:32.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:32.91#ibcon#enter wrdev, iclass 11, count 2 2006.257.16:49:32.91#ibcon#first serial, iclass 11, count 2 2006.257.16:49:32.91#ibcon#enter sib2, iclass 11, count 2 2006.257.16:49:32.91#ibcon#flushed, iclass 11, count 2 2006.257.16:49:32.91#ibcon#about to write, iclass 11, count 2 2006.257.16:49:32.91#ibcon#wrote, iclass 11, count 2 2006.257.16:49:32.91#ibcon#about to read 3, iclass 11, count 2 2006.257.16:49:32.93#ibcon#read 3, iclass 11, count 2 2006.257.16:49:32.93#ibcon#about to read 4, iclass 11, count 2 2006.257.16:49:32.93#ibcon#read 4, iclass 11, count 2 2006.257.16:49:32.93#ibcon#about to read 5, iclass 11, count 2 2006.257.16:49:32.93#ibcon#read 5, iclass 11, count 2 2006.257.16:49:32.93#ibcon#about to read 6, iclass 11, count 2 2006.257.16:49:32.93#ibcon#read 6, iclass 11, count 2 2006.257.16:49:32.93#ibcon#end of sib2, iclass 11, count 2 2006.257.16:49:32.93#ibcon#*mode == 0, iclass 11, count 2 2006.257.16:49:32.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.16:49:32.93#ibcon#[25=AT05-04\r\n] 2006.257.16:49:32.93#ibcon#*before write, iclass 11, count 2 2006.257.16:49:32.93#ibcon#enter sib2, iclass 11, count 2 2006.257.16:49:32.93#ibcon#flushed, iclass 11, count 2 2006.257.16:49:32.93#ibcon#about to write, iclass 11, count 2 2006.257.16:49:32.93#ibcon#wrote, iclass 11, count 2 2006.257.16:49:32.93#ibcon#about to read 3, iclass 11, count 2 2006.257.16:49:32.96#ibcon#read 3, iclass 11, count 2 2006.257.16:49:32.96#ibcon#about to read 4, iclass 11, count 2 2006.257.16:49:32.96#ibcon#read 4, iclass 11, count 2 2006.257.16:49:32.96#ibcon#about to read 5, iclass 11, count 2 2006.257.16:49:32.96#ibcon#read 5, iclass 11, count 2 2006.257.16:49:32.96#ibcon#about to read 6, iclass 11, count 2 2006.257.16:49:32.96#ibcon#read 6, iclass 11, count 2 2006.257.16:49:32.96#ibcon#end of sib2, iclass 11, count 2 2006.257.16:49:32.96#ibcon#*after write, iclass 11, count 2 2006.257.16:49:32.96#ibcon#*before return 0, iclass 11, count 2 2006.257.16:49:32.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:32.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:32.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.16:49:32.96#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:32.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:33.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:33.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:33.08#ibcon#enter wrdev, iclass 11, count 0 2006.257.16:49:33.08#ibcon#first serial, iclass 11, count 0 2006.257.16:49:33.08#ibcon#enter sib2, iclass 11, count 0 2006.257.16:49:33.08#ibcon#flushed, iclass 11, count 0 2006.257.16:49:33.08#ibcon#about to write, iclass 11, count 0 2006.257.16:49:33.08#ibcon#wrote, iclass 11, count 0 2006.257.16:49:33.08#ibcon#about to read 3, iclass 11, count 0 2006.257.16:49:33.10#ibcon#read 3, iclass 11, count 0 2006.257.16:49:33.10#ibcon#about to read 4, iclass 11, count 0 2006.257.16:49:33.10#ibcon#read 4, iclass 11, count 0 2006.257.16:49:33.10#ibcon#about to read 5, iclass 11, count 0 2006.257.16:49:33.10#ibcon#read 5, iclass 11, count 0 2006.257.16:49:33.10#ibcon#about to read 6, iclass 11, count 0 2006.257.16:49:33.10#ibcon#read 6, iclass 11, count 0 2006.257.16:49:33.10#ibcon#end of sib2, iclass 11, count 0 2006.257.16:49:33.10#ibcon#*mode == 0, iclass 11, count 0 2006.257.16:49:33.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.16:49:33.10#ibcon#[25=USB\r\n] 2006.257.16:49:33.10#ibcon#*before write, iclass 11, count 0 2006.257.16:49:33.10#ibcon#enter sib2, iclass 11, count 0 2006.257.16:49:33.10#ibcon#flushed, iclass 11, count 0 2006.257.16:49:33.10#ibcon#about to write, iclass 11, count 0 2006.257.16:49:33.10#ibcon#wrote, iclass 11, count 0 2006.257.16:49:33.10#ibcon#about to read 3, iclass 11, count 0 2006.257.16:49:33.13#ibcon#read 3, iclass 11, count 0 2006.257.16:49:33.13#ibcon#about to read 4, iclass 11, count 0 2006.257.16:49:33.13#ibcon#read 4, iclass 11, count 0 2006.257.16:49:33.13#ibcon#about to read 5, iclass 11, count 0 2006.257.16:49:33.13#ibcon#read 5, iclass 11, count 0 2006.257.16:49:33.13#ibcon#about to read 6, iclass 11, count 0 2006.257.16:49:33.13#ibcon#read 6, iclass 11, count 0 2006.257.16:49:33.13#ibcon#end of sib2, iclass 11, count 0 2006.257.16:49:33.13#ibcon#*after write, iclass 11, count 0 2006.257.16:49:33.13#ibcon#*before return 0, iclass 11, count 0 2006.257.16:49:33.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:33.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:33.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.16:49:33.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.16:49:33.13$vck44/valo=6,814.99 2006.257.16:49:33.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.16:49:33.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.16:49:33.13#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:33.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:33.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:33.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:33.13#ibcon#enter wrdev, iclass 13, count 0 2006.257.16:49:33.13#ibcon#first serial, iclass 13, count 0 2006.257.16:49:33.13#ibcon#enter sib2, iclass 13, count 0 2006.257.16:49:33.13#ibcon#flushed, iclass 13, count 0 2006.257.16:49:33.13#ibcon#about to write, iclass 13, count 0 2006.257.16:49:33.13#ibcon#wrote, iclass 13, count 0 2006.257.16:49:33.13#ibcon#about to read 3, iclass 13, count 0 2006.257.16:49:33.15#ibcon#read 3, iclass 13, count 0 2006.257.16:49:33.15#ibcon#about to read 4, iclass 13, count 0 2006.257.16:49:33.15#ibcon#read 4, iclass 13, count 0 2006.257.16:49:33.15#ibcon#about to read 5, iclass 13, count 0 2006.257.16:49:33.15#ibcon#read 5, iclass 13, count 0 2006.257.16:49:33.15#ibcon#about to read 6, iclass 13, count 0 2006.257.16:49:33.15#ibcon#read 6, iclass 13, count 0 2006.257.16:49:33.15#ibcon#end of sib2, iclass 13, count 0 2006.257.16:49:33.15#ibcon#*mode == 0, iclass 13, count 0 2006.257.16:49:33.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.16:49:33.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.16:49:33.15#ibcon#*before write, iclass 13, count 0 2006.257.16:49:33.15#ibcon#enter sib2, iclass 13, count 0 2006.257.16:49:33.15#ibcon#flushed, iclass 13, count 0 2006.257.16:49:33.15#ibcon#about to write, iclass 13, count 0 2006.257.16:49:33.15#ibcon#wrote, iclass 13, count 0 2006.257.16:49:33.15#ibcon#about to read 3, iclass 13, count 0 2006.257.16:49:33.19#ibcon#read 3, iclass 13, count 0 2006.257.16:49:33.19#ibcon#about to read 4, iclass 13, count 0 2006.257.16:49:33.19#ibcon#read 4, iclass 13, count 0 2006.257.16:49:33.19#ibcon#about to read 5, iclass 13, count 0 2006.257.16:49:33.19#ibcon#read 5, iclass 13, count 0 2006.257.16:49:33.19#ibcon#about to read 6, iclass 13, count 0 2006.257.16:49:33.19#ibcon#read 6, iclass 13, count 0 2006.257.16:49:33.19#ibcon#end of sib2, iclass 13, count 0 2006.257.16:49:33.19#ibcon#*after write, iclass 13, count 0 2006.257.16:49:33.19#ibcon#*before return 0, iclass 13, count 0 2006.257.16:49:33.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:33.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:33.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.16:49:33.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.16:49:33.19$vck44/va=6,4 2006.257.16:49:33.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.16:49:33.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.16:49:33.19#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:33.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:33.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:33.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:33.25#ibcon#enter wrdev, iclass 15, count 2 2006.257.16:49:33.25#ibcon#first serial, iclass 15, count 2 2006.257.16:49:33.25#ibcon#enter sib2, iclass 15, count 2 2006.257.16:49:33.25#ibcon#flushed, iclass 15, count 2 2006.257.16:49:33.25#ibcon#about to write, iclass 15, count 2 2006.257.16:49:33.25#ibcon#wrote, iclass 15, count 2 2006.257.16:49:33.25#ibcon#about to read 3, iclass 15, count 2 2006.257.16:49:33.27#ibcon#read 3, iclass 15, count 2 2006.257.16:49:33.27#ibcon#about to read 4, iclass 15, count 2 2006.257.16:49:33.27#ibcon#read 4, iclass 15, count 2 2006.257.16:49:33.27#ibcon#about to read 5, iclass 15, count 2 2006.257.16:49:33.27#ibcon#read 5, iclass 15, count 2 2006.257.16:49:33.27#ibcon#about to read 6, iclass 15, count 2 2006.257.16:49:33.27#ibcon#read 6, iclass 15, count 2 2006.257.16:49:33.27#ibcon#end of sib2, iclass 15, count 2 2006.257.16:49:33.27#ibcon#*mode == 0, iclass 15, count 2 2006.257.16:49:33.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.16:49:33.27#ibcon#[25=AT06-04\r\n] 2006.257.16:49:33.27#ibcon#*before write, iclass 15, count 2 2006.257.16:49:33.27#ibcon#enter sib2, iclass 15, count 2 2006.257.16:49:33.27#ibcon#flushed, iclass 15, count 2 2006.257.16:49:33.27#ibcon#about to write, iclass 15, count 2 2006.257.16:49:33.27#ibcon#wrote, iclass 15, count 2 2006.257.16:49:33.27#ibcon#about to read 3, iclass 15, count 2 2006.257.16:49:33.30#ibcon#read 3, iclass 15, count 2 2006.257.16:49:33.30#ibcon#about to read 4, iclass 15, count 2 2006.257.16:49:33.30#ibcon#read 4, iclass 15, count 2 2006.257.16:49:33.30#ibcon#about to read 5, iclass 15, count 2 2006.257.16:49:33.30#ibcon#read 5, iclass 15, count 2 2006.257.16:49:33.30#ibcon#about to read 6, iclass 15, count 2 2006.257.16:49:33.30#ibcon#read 6, iclass 15, count 2 2006.257.16:49:33.30#ibcon#end of sib2, iclass 15, count 2 2006.257.16:49:33.30#ibcon#*after write, iclass 15, count 2 2006.257.16:49:33.30#ibcon#*before return 0, iclass 15, count 2 2006.257.16:49:33.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:33.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:33.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.16:49:33.30#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:33.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:33.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:33.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:33.42#ibcon#enter wrdev, iclass 15, count 0 2006.257.16:49:33.42#ibcon#first serial, iclass 15, count 0 2006.257.16:49:33.42#ibcon#enter sib2, iclass 15, count 0 2006.257.16:49:33.42#ibcon#flushed, iclass 15, count 0 2006.257.16:49:33.42#ibcon#about to write, iclass 15, count 0 2006.257.16:49:33.42#ibcon#wrote, iclass 15, count 0 2006.257.16:49:33.42#ibcon#about to read 3, iclass 15, count 0 2006.257.16:49:33.44#ibcon#read 3, iclass 15, count 0 2006.257.16:49:33.44#ibcon#about to read 4, iclass 15, count 0 2006.257.16:49:33.44#ibcon#read 4, iclass 15, count 0 2006.257.16:49:33.44#ibcon#about to read 5, iclass 15, count 0 2006.257.16:49:33.44#ibcon#read 5, iclass 15, count 0 2006.257.16:49:33.44#ibcon#about to read 6, iclass 15, count 0 2006.257.16:49:33.44#ibcon#read 6, iclass 15, count 0 2006.257.16:49:33.44#ibcon#end of sib2, iclass 15, count 0 2006.257.16:49:33.44#ibcon#*mode == 0, iclass 15, count 0 2006.257.16:49:33.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.16:49:33.44#ibcon#[25=USB\r\n] 2006.257.16:49:33.44#ibcon#*before write, iclass 15, count 0 2006.257.16:49:33.44#ibcon#enter sib2, iclass 15, count 0 2006.257.16:49:33.44#ibcon#flushed, iclass 15, count 0 2006.257.16:49:33.44#ibcon#about to write, iclass 15, count 0 2006.257.16:49:33.44#ibcon#wrote, iclass 15, count 0 2006.257.16:49:33.44#ibcon#about to read 3, iclass 15, count 0 2006.257.16:49:33.47#ibcon#read 3, iclass 15, count 0 2006.257.16:49:33.47#ibcon#about to read 4, iclass 15, count 0 2006.257.16:49:33.47#ibcon#read 4, iclass 15, count 0 2006.257.16:49:33.47#ibcon#about to read 5, iclass 15, count 0 2006.257.16:49:33.47#ibcon#read 5, iclass 15, count 0 2006.257.16:49:33.47#ibcon#about to read 6, iclass 15, count 0 2006.257.16:49:33.47#ibcon#read 6, iclass 15, count 0 2006.257.16:49:33.47#ibcon#end of sib2, iclass 15, count 0 2006.257.16:49:33.47#ibcon#*after write, iclass 15, count 0 2006.257.16:49:33.47#ibcon#*before return 0, iclass 15, count 0 2006.257.16:49:33.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:33.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:33.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.16:49:33.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.16:49:33.47$vck44/valo=7,864.99 2006.257.16:49:33.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.16:49:33.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.16:49:33.47#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:33.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:33.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:33.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:33.47#ibcon#enter wrdev, iclass 17, count 0 2006.257.16:49:33.47#ibcon#first serial, iclass 17, count 0 2006.257.16:49:33.47#ibcon#enter sib2, iclass 17, count 0 2006.257.16:49:33.47#ibcon#flushed, iclass 17, count 0 2006.257.16:49:33.47#ibcon#about to write, iclass 17, count 0 2006.257.16:49:33.47#ibcon#wrote, iclass 17, count 0 2006.257.16:49:33.47#ibcon#about to read 3, iclass 17, count 0 2006.257.16:49:33.49#ibcon#read 3, iclass 17, count 0 2006.257.16:49:33.49#ibcon#about to read 4, iclass 17, count 0 2006.257.16:49:33.49#ibcon#read 4, iclass 17, count 0 2006.257.16:49:33.49#ibcon#about to read 5, iclass 17, count 0 2006.257.16:49:33.49#ibcon#read 5, iclass 17, count 0 2006.257.16:49:33.49#ibcon#about to read 6, iclass 17, count 0 2006.257.16:49:33.49#ibcon#read 6, iclass 17, count 0 2006.257.16:49:33.49#ibcon#end of sib2, iclass 17, count 0 2006.257.16:49:33.49#ibcon#*mode == 0, iclass 17, count 0 2006.257.16:49:33.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.16:49:33.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.16:49:33.49#ibcon#*before write, iclass 17, count 0 2006.257.16:49:33.49#ibcon#enter sib2, iclass 17, count 0 2006.257.16:49:33.49#ibcon#flushed, iclass 17, count 0 2006.257.16:49:33.49#ibcon#about to write, iclass 17, count 0 2006.257.16:49:33.49#ibcon#wrote, iclass 17, count 0 2006.257.16:49:33.49#ibcon#about to read 3, iclass 17, count 0 2006.257.16:49:33.53#ibcon#read 3, iclass 17, count 0 2006.257.16:49:33.53#ibcon#about to read 4, iclass 17, count 0 2006.257.16:49:33.53#ibcon#read 4, iclass 17, count 0 2006.257.16:49:33.53#ibcon#about to read 5, iclass 17, count 0 2006.257.16:49:33.53#ibcon#read 5, iclass 17, count 0 2006.257.16:49:33.53#ibcon#about to read 6, iclass 17, count 0 2006.257.16:49:33.53#ibcon#read 6, iclass 17, count 0 2006.257.16:49:33.53#ibcon#end of sib2, iclass 17, count 0 2006.257.16:49:33.53#ibcon#*after write, iclass 17, count 0 2006.257.16:49:33.53#ibcon#*before return 0, iclass 17, count 0 2006.257.16:49:33.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:33.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:33.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.16:49:33.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.16:49:33.53$vck44/va=7,4 2006.257.16:49:33.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.16:49:33.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.16:49:33.53#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:33.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:33.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:33.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:33.59#ibcon#enter wrdev, iclass 19, count 2 2006.257.16:49:33.59#ibcon#first serial, iclass 19, count 2 2006.257.16:49:33.59#ibcon#enter sib2, iclass 19, count 2 2006.257.16:49:33.59#ibcon#flushed, iclass 19, count 2 2006.257.16:49:33.59#ibcon#about to write, iclass 19, count 2 2006.257.16:49:33.59#ibcon#wrote, iclass 19, count 2 2006.257.16:49:33.59#ibcon#about to read 3, iclass 19, count 2 2006.257.16:49:33.61#ibcon#read 3, iclass 19, count 2 2006.257.16:49:33.61#ibcon#about to read 4, iclass 19, count 2 2006.257.16:49:33.61#ibcon#read 4, iclass 19, count 2 2006.257.16:49:33.61#ibcon#about to read 5, iclass 19, count 2 2006.257.16:49:33.61#ibcon#read 5, iclass 19, count 2 2006.257.16:49:33.61#ibcon#about to read 6, iclass 19, count 2 2006.257.16:49:33.61#ibcon#read 6, iclass 19, count 2 2006.257.16:49:33.61#ibcon#end of sib2, iclass 19, count 2 2006.257.16:49:33.61#ibcon#*mode == 0, iclass 19, count 2 2006.257.16:49:33.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.16:49:33.61#ibcon#[25=AT07-04\r\n] 2006.257.16:49:33.61#ibcon#*before write, iclass 19, count 2 2006.257.16:49:33.61#ibcon#enter sib2, iclass 19, count 2 2006.257.16:49:33.61#ibcon#flushed, iclass 19, count 2 2006.257.16:49:33.61#ibcon#about to write, iclass 19, count 2 2006.257.16:49:33.61#ibcon#wrote, iclass 19, count 2 2006.257.16:49:33.61#ibcon#about to read 3, iclass 19, count 2 2006.257.16:49:33.64#ibcon#read 3, iclass 19, count 2 2006.257.16:49:33.64#ibcon#about to read 4, iclass 19, count 2 2006.257.16:49:33.64#ibcon#read 4, iclass 19, count 2 2006.257.16:49:33.64#ibcon#about to read 5, iclass 19, count 2 2006.257.16:49:33.64#ibcon#read 5, iclass 19, count 2 2006.257.16:49:33.64#ibcon#about to read 6, iclass 19, count 2 2006.257.16:49:33.64#ibcon#read 6, iclass 19, count 2 2006.257.16:49:33.64#ibcon#end of sib2, iclass 19, count 2 2006.257.16:49:33.64#ibcon#*after write, iclass 19, count 2 2006.257.16:49:33.64#ibcon#*before return 0, iclass 19, count 2 2006.257.16:49:33.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:33.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:33.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.16:49:33.64#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:33.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:33.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:33.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:33.76#ibcon#enter wrdev, iclass 19, count 0 2006.257.16:49:33.76#ibcon#first serial, iclass 19, count 0 2006.257.16:49:33.76#ibcon#enter sib2, iclass 19, count 0 2006.257.16:49:33.76#ibcon#flushed, iclass 19, count 0 2006.257.16:49:33.76#ibcon#about to write, iclass 19, count 0 2006.257.16:49:33.76#ibcon#wrote, iclass 19, count 0 2006.257.16:49:33.76#ibcon#about to read 3, iclass 19, count 0 2006.257.16:49:33.78#ibcon#read 3, iclass 19, count 0 2006.257.16:49:33.78#ibcon#about to read 4, iclass 19, count 0 2006.257.16:49:33.78#ibcon#read 4, iclass 19, count 0 2006.257.16:49:33.78#ibcon#about to read 5, iclass 19, count 0 2006.257.16:49:33.78#ibcon#read 5, iclass 19, count 0 2006.257.16:49:33.78#ibcon#about to read 6, iclass 19, count 0 2006.257.16:49:33.78#ibcon#read 6, iclass 19, count 0 2006.257.16:49:33.78#ibcon#end of sib2, iclass 19, count 0 2006.257.16:49:33.78#ibcon#*mode == 0, iclass 19, count 0 2006.257.16:49:33.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.16:49:33.78#ibcon#[25=USB\r\n] 2006.257.16:49:33.78#ibcon#*before write, iclass 19, count 0 2006.257.16:49:33.78#ibcon#enter sib2, iclass 19, count 0 2006.257.16:49:33.78#ibcon#flushed, iclass 19, count 0 2006.257.16:49:33.78#ibcon#about to write, iclass 19, count 0 2006.257.16:49:33.78#ibcon#wrote, iclass 19, count 0 2006.257.16:49:33.78#ibcon#about to read 3, iclass 19, count 0 2006.257.16:49:33.81#ibcon#read 3, iclass 19, count 0 2006.257.16:49:33.81#ibcon#about to read 4, iclass 19, count 0 2006.257.16:49:33.81#ibcon#read 4, iclass 19, count 0 2006.257.16:49:33.81#ibcon#about to read 5, iclass 19, count 0 2006.257.16:49:33.81#ibcon#read 5, iclass 19, count 0 2006.257.16:49:33.81#ibcon#about to read 6, iclass 19, count 0 2006.257.16:49:33.81#ibcon#read 6, iclass 19, count 0 2006.257.16:49:33.81#ibcon#end of sib2, iclass 19, count 0 2006.257.16:49:33.81#ibcon#*after write, iclass 19, count 0 2006.257.16:49:33.81#ibcon#*before return 0, iclass 19, count 0 2006.257.16:49:33.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:33.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:33.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.16:49:33.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.16:49:33.81$vck44/valo=8,884.99 2006.257.16:49:33.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.16:49:33.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.16:49:33.81#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:33.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:33.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:33.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:33.81#ibcon#enter wrdev, iclass 21, count 0 2006.257.16:49:33.81#ibcon#first serial, iclass 21, count 0 2006.257.16:49:33.81#ibcon#enter sib2, iclass 21, count 0 2006.257.16:49:33.81#ibcon#flushed, iclass 21, count 0 2006.257.16:49:33.81#ibcon#about to write, iclass 21, count 0 2006.257.16:49:33.81#ibcon#wrote, iclass 21, count 0 2006.257.16:49:33.81#ibcon#about to read 3, iclass 21, count 0 2006.257.16:49:33.83#ibcon#read 3, iclass 21, count 0 2006.257.16:49:33.83#ibcon#about to read 4, iclass 21, count 0 2006.257.16:49:33.83#ibcon#read 4, iclass 21, count 0 2006.257.16:49:33.83#ibcon#about to read 5, iclass 21, count 0 2006.257.16:49:33.83#ibcon#read 5, iclass 21, count 0 2006.257.16:49:33.83#ibcon#about to read 6, iclass 21, count 0 2006.257.16:49:33.83#ibcon#read 6, iclass 21, count 0 2006.257.16:49:33.83#ibcon#end of sib2, iclass 21, count 0 2006.257.16:49:33.83#ibcon#*mode == 0, iclass 21, count 0 2006.257.16:49:33.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.16:49:33.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.16:49:33.83#ibcon#*before write, iclass 21, count 0 2006.257.16:49:33.83#ibcon#enter sib2, iclass 21, count 0 2006.257.16:49:33.83#ibcon#flushed, iclass 21, count 0 2006.257.16:49:33.83#ibcon#about to write, iclass 21, count 0 2006.257.16:49:33.83#ibcon#wrote, iclass 21, count 0 2006.257.16:49:33.83#ibcon#about to read 3, iclass 21, count 0 2006.257.16:49:33.87#ibcon#read 3, iclass 21, count 0 2006.257.16:49:33.87#ibcon#about to read 4, iclass 21, count 0 2006.257.16:49:33.87#ibcon#read 4, iclass 21, count 0 2006.257.16:49:33.87#ibcon#about to read 5, iclass 21, count 0 2006.257.16:49:33.87#ibcon#read 5, iclass 21, count 0 2006.257.16:49:33.87#ibcon#about to read 6, iclass 21, count 0 2006.257.16:49:33.87#ibcon#read 6, iclass 21, count 0 2006.257.16:49:33.87#ibcon#end of sib2, iclass 21, count 0 2006.257.16:49:33.87#ibcon#*after write, iclass 21, count 0 2006.257.16:49:33.87#ibcon#*before return 0, iclass 21, count 0 2006.257.16:49:33.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:33.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:33.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.16:49:33.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.16:49:33.87$vck44/va=8,4 2006.257.16:49:33.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.16:49:33.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.16:49:33.87#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:33.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:49:33.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:49:33.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:49:33.93#ibcon#enter wrdev, iclass 23, count 2 2006.257.16:49:33.93#ibcon#first serial, iclass 23, count 2 2006.257.16:49:33.93#ibcon#enter sib2, iclass 23, count 2 2006.257.16:49:33.93#ibcon#flushed, iclass 23, count 2 2006.257.16:49:33.93#ibcon#about to write, iclass 23, count 2 2006.257.16:49:33.93#ibcon#wrote, iclass 23, count 2 2006.257.16:49:33.93#ibcon#about to read 3, iclass 23, count 2 2006.257.16:49:33.95#ibcon#read 3, iclass 23, count 2 2006.257.16:49:33.95#ibcon#about to read 4, iclass 23, count 2 2006.257.16:49:33.95#ibcon#read 4, iclass 23, count 2 2006.257.16:49:33.95#ibcon#about to read 5, iclass 23, count 2 2006.257.16:49:33.95#ibcon#read 5, iclass 23, count 2 2006.257.16:49:33.95#ibcon#about to read 6, iclass 23, count 2 2006.257.16:49:33.95#ibcon#read 6, iclass 23, count 2 2006.257.16:49:33.95#ibcon#end of sib2, iclass 23, count 2 2006.257.16:49:33.95#ibcon#*mode == 0, iclass 23, count 2 2006.257.16:49:33.95#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.16:49:33.95#ibcon#[25=AT08-04\r\n] 2006.257.16:49:33.95#ibcon#*before write, iclass 23, count 2 2006.257.16:49:33.95#ibcon#enter sib2, iclass 23, count 2 2006.257.16:49:33.95#ibcon#flushed, iclass 23, count 2 2006.257.16:49:33.95#ibcon#about to write, iclass 23, count 2 2006.257.16:49:33.95#ibcon#wrote, iclass 23, count 2 2006.257.16:49:33.95#ibcon#about to read 3, iclass 23, count 2 2006.257.16:49:33.98#ibcon#read 3, iclass 23, count 2 2006.257.16:49:33.98#ibcon#about to read 4, iclass 23, count 2 2006.257.16:49:33.98#ibcon#read 4, iclass 23, count 2 2006.257.16:49:33.98#ibcon#about to read 5, iclass 23, count 2 2006.257.16:49:33.98#ibcon#read 5, iclass 23, count 2 2006.257.16:49:33.98#ibcon#about to read 6, iclass 23, count 2 2006.257.16:49:33.98#ibcon#read 6, iclass 23, count 2 2006.257.16:49:33.98#ibcon#end of sib2, iclass 23, count 2 2006.257.16:49:33.98#ibcon#*after write, iclass 23, count 2 2006.257.16:49:33.98#ibcon#*before return 0, iclass 23, count 2 2006.257.16:49:33.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:49:33.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.16:49:33.98#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.16:49:33.98#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:33.98#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:49:34.10#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:49:34.10#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:49:34.10#ibcon#enter wrdev, iclass 23, count 0 2006.257.16:49:34.10#ibcon#first serial, iclass 23, count 0 2006.257.16:49:34.10#ibcon#enter sib2, iclass 23, count 0 2006.257.16:49:34.10#ibcon#flushed, iclass 23, count 0 2006.257.16:49:34.10#ibcon#about to write, iclass 23, count 0 2006.257.16:49:34.10#ibcon#wrote, iclass 23, count 0 2006.257.16:49:34.10#ibcon#about to read 3, iclass 23, count 0 2006.257.16:49:34.12#ibcon#read 3, iclass 23, count 0 2006.257.16:49:34.12#ibcon#about to read 4, iclass 23, count 0 2006.257.16:49:34.12#ibcon#read 4, iclass 23, count 0 2006.257.16:49:34.12#ibcon#about to read 5, iclass 23, count 0 2006.257.16:49:34.12#ibcon#read 5, iclass 23, count 0 2006.257.16:49:34.12#ibcon#about to read 6, iclass 23, count 0 2006.257.16:49:34.12#ibcon#read 6, iclass 23, count 0 2006.257.16:49:34.12#ibcon#end of sib2, iclass 23, count 0 2006.257.16:49:34.12#ibcon#*mode == 0, iclass 23, count 0 2006.257.16:49:34.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.16:49:34.12#ibcon#[25=USB\r\n] 2006.257.16:49:34.12#ibcon#*before write, iclass 23, count 0 2006.257.16:49:34.12#ibcon#enter sib2, iclass 23, count 0 2006.257.16:49:34.12#ibcon#flushed, iclass 23, count 0 2006.257.16:49:34.12#ibcon#about to write, iclass 23, count 0 2006.257.16:49:34.12#ibcon#wrote, iclass 23, count 0 2006.257.16:49:34.12#ibcon#about to read 3, iclass 23, count 0 2006.257.16:49:34.15#ibcon#read 3, iclass 23, count 0 2006.257.16:49:34.15#ibcon#about to read 4, iclass 23, count 0 2006.257.16:49:34.15#ibcon#read 4, iclass 23, count 0 2006.257.16:49:34.15#ibcon#about to read 5, iclass 23, count 0 2006.257.16:49:34.15#ibcon#read 5, iclass 23, count 0 2006.257.16:49:34.15#ibcon#about to read 6, iclass 23, count 0 2006.257.16:49:34.15#ibcon#read 6, iclass 23, count 0 2006.257.16:49:34.15#ibcon#end of sib2, iclass 23, count 0 2006.257.16:49:34.15#ibcon#*after write, iclass 23, count 0 2006.257.16:49:34.15#ibcon#*before return 0, iclass 23, count 0 2006.257.16:49:34.15#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:49:34.15#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.16:49:34.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.16:49:34.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.16:49:34.15$vck44/vblo=1,629.99 2006.257.16:49:34.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.16:49:34.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.16:49:34.15#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:34.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:49:34.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:49:34.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:49:34.15#ibcon#enter wrdev, iclass 25, count 0 2006.257.16:49:34.15#ibcon#first serial, iclass 25, count 0 2006.257.16:49:34.15#ibcon#enter sib2, iclass 25, count 0 2006.257.16:49:34.15#ibcon#flushed, iclass 25, count 0 2006.257.16:49:34.15#ibcon#about to write, iclass 25, count 0 2006.257.16:49:34.15#ibcon#wrote, iclass 25, count 0 2006.257.16:49:34.15#ibcon#about to read 3, iclass 25, count 0 2006.257.16:49:34.17#ibcon#read 3, iclass 25, count 0 2006.257.16:49:34.17#ibcon#about to read 4, iclass 25, count 0 2006.257.16:49:34.17#ibcon#read 4, iclass 25, count 0 2006.257.16:49:34.17#ibcon#about to read 5, iclass 25, count 0 2006.257.16:49:34.17#ibcon#read 5, iclass 25, count 0 2006.257.16:49:34.17#ibcon#about to read 6, iclass 25, count 0 2006.257.16:49:34.17#ibcon#read 6, iclass 25, count 0 2006.257.16:49:34.17#ibcon#end of sib2, iclass 25, count 0 2006.257.16:49:34.17#ibcon#*mode == 0, iclass 25, count 0 2006.257.16:49:34.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.16:49:34.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.16:49:34.17#ibcon#*before write, iclass 25, count 0 2006.257.16:49:34.17#ibcon#enter sib2, iclass 25, count 0 2006.257.16:49:34.17#ibcon#flushed, iclass 25, count 0 2006.257.16:49:34.17#ibcon#about to write, iclass 25, count 0 2006.257.16:49:34.17#ibcon#wrote, iclass 25, count 0 2006.257.16:49:34.17#ibcon#about to read 3, iclass 25, count 0 2006.257.16:49:34.21#ibcon#read 3, iclass 25, count 0 2006.257.16:49:34.21#ibcon#about to read 4, iclass 25, count 0 2006.257.16:49:34.21#ibcon#read 4, iclass 25, count 0 2006.257.16:49:34.21#ibcon#about to read 5, iclass 25, count 0 2006.257.16:49:34.21#ibcon#read 5, iclass 25, count 0 2006.257.16:49:34.21#ibcon#about to read 6, iclass 25, count 0 2006.257.16:49:34.21#ibcon#read 6, iclass 25, count 0 2006.257.16:49:34.21#ibcon#end of sib2, iclass 25, count 0 2006.257.16:49:34.21#ibcon#*after write, iclass 25, count 0 2006.257.16:49:34.21#ibcon#*before return 0, iclass 25, count 0 2006.257.16:49:34.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:49:34.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.16:49:34.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.16:49:34.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.16:49:34.21$vck44/vb=1,4 2006.257.16:49:34.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.16:49:34.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.16:49:34.21#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:34.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:49:34.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:49:34.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:49:34.21#ibcon#enter wrdev, iclass 27, count 2 2006.257.16:49:34.21#ibcon#first serial, iclass 27, count 2 2006.257.16:49:34.21#ibcon#enter sib2, iclass 27, count 2 2006.257.16:49:34.21#ibcon#flushed, iclass 27, count 2 2006.257.16:49:34.21#ibcon#about to write, iclass 27, count 2 2006.257.16:49:34.21#ibcon#wrote, iclass 27, count 2 2006.257.16:49:34.21#ibcon#about to read 3, iclass 27, count 2 2006.257.16:49:34.23#ibcon#read 3, iclass 27, count 2 2006.257.16:49:34.23#ibcon#about to read 4, iclass 27, count 2 2006.257.16:49:34.23#ibcon#read 4, iclass 27, count 2 2006.257.16:49:34.23#ibcon#about to read 5, iclass 27, count 2 2006.257.16:49:34.23#ibcon#read 5, iclass 27, count 2 2006.257.16:49:34.23#ibcon#about to read 6, iclass 27, count 2 2006.257.16:49:34.23#ibcon#read 6, iclass 27, count 2 2006.257.16:49:34.23#ibcon#end of sib2, iclass 27, count 2 2006.257.16:49:34.23#ibcon#*mode == 0, iclass 27, count 2 2006.257.16:49:34.23#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.16:49:34.23#ibcon#[27=AT01-04\r\n] 2006.257.16:49:34.23#ibcon#*before write, iclass 27, count 2 2006.257.16:49:34.23#ibcon#enter sib2, iclass 27, count 2 2006.257.16:49:34.23#ibcon#flushed, iclass 27, count 2 2006.257.16:49:34.23#ibcon#about to write, iclass 27, count 2 2006.257.16:49:34.23#ibcon#wrote, iclass 27, count 2 2006.257.16:49:34.23#ibcon#about to read 3, iclass 27, count 2 2006.257.16:49:34.26#ibcon#read 3, iclass 27, count 2 2006.257.16:49:34.26#ibcon#about to read 4, iclass 27, count 2 2006.257.16:49:34.26#ibcon#read 4, iclass 27, count 2 2006.257.16:49:34.26#ibcon#about to read 5, iclass 27, count 2 2006.257.16:49:34.26#ibcon#read 5, iclass 27, count 2 2006.257.16:49:34.26#ibcon#about to read 6, iclass 27, count 2 2006.257.16:49:34.26#ibcon#read 6, iclass 27, count 2 2006.257.16:49:34.26#ibcon#end of sib2, iclass 27, count 2 2006.257.16:49:34.26#ibcon#*after write, iclass 27, count 2 2006.257.16:49:34.26#ibcon#*before return 0, iclass 27, count 2 2006.257.16:49:34.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:49:34.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.16:49:34.26#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.16:49:34.26#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:34.26#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:49:34.38#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:49:34.38#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:49:34.38#ibcon#enter wrdev, iclass 27, count 0 2006.257.16:49:34.38#ibcon#first serial, iclass 27, count 0 2006.257.16:49:34.38#ibcon#enter sib2, iclass 27, count 0 2006.257.16:49:34.38#ibcon#flushed, iclass 27, count 0 2006.257.16:49:34.38#ibcon#about to write, iclass 27, count 0 2006.257.16:49:34.38#ibcon#wrote, iclass 27, count 0 2006.257.16:49:34.38#ibcon#about to read 3, iclass 27, count 0 2006.257.16:49:34.40#ibcon#read 3, iclass 27, count 0 2006.257.16:49:34.40#ibcon#about to read 4, iclass 27, count 0 2006.257.16:49:34.40#ibcon#read 4, iclass 27, count 0 2006.257.16:49:34.40#ibcon#about to read 5, iclass 27, count 0 2006.257.16:49:34.40#ibcon#read 5, iclass 27, count 0 2006.257.16:49:34.40#ibcon#about to read 6, iclass 27, count 0 2006.257.16:49:34.40#ibcon#read 6, iclass 27, count 0 2006.257.16:49:34.40#ibcon#end of sib2, iclass 27, count 0 2006.257.16:49:34.40#ibcon#*mode == 0, iclass 27, count 0 2006.257.16:49:34.40#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.16:49:34.40#ibcon#[27=USB\r\n] 2006.257.16:49:34.40#ibcon#*before write, iclass 27, count 0 2006.257.16:49:34.40#ibcon#enter sib2, iclass 27, count 0 2006.257.16:49:34.40#ibcon#flushed, iclass 27, count 0 2006.257.16:49:34.40#ibcon#about to write, iclass 27, count 0 2006.257.16:49:34.40#ibcon#wrote, iclass 27, count 0 2006.257.16:49:34.40#ibcon#about to read 3, iclass 27, count 0 2006.257.16:49:34.43#ibcon#read 3, iclass 27, count 0 2006.257.16:49:34.43#ibcon#about to read 4, iclass 27, count 0 2006.257.16:49:34.43#ibcon#read 4, iclass 27, count 0 2006.257.16:49:34.43#ibcon#about to read 5, iclass 27, count 0 2006.257.16:49:34.43#ibcon#read 5, iclass 27, count 0 2006.257.16:49:34.43#ibcon#about to read 6, iclass 27, count 0 2006.257.16:49:34.43#ibcon#read 6, iclass 27, count 0 2006.257.16:49:34.43#ibcon#end of sib2, iclass 27, count 0 2006.257.16:49:34.43#ibcon#*after write, iclass 27, count 0 2006.257.16:49:34.43#ibcon#*before return 0, iclass 27, count 0 2006.257.16:49:34.43#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:49:34.43#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.16:49:34.43#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.16:49:34.43#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.16:49:34.43$vck44/vblo=2,634.99 2006.257.16:49:34.43#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.16:49:34.43#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.16:49:34.43#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:34.43#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:34.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:34.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:34.43#ibcon#enter wrdev, iclass 29, count 0 2006.257.16:49:34.43#ibcon#first serial, iclass 29, count 0 2006.257.16:49:34.43#ibcon#enter sib2, iclass 29, count 0 2006.257.16:49:34.43#ibcon#flushed, iclass 29, count 0 2006.257.16:49:34.43#ibcon#about to write, iclass 29, count 0 2006.257.16:49:34.43#ibcon#wrote, iclass 29, count 0 2006.257.16:49:34.43#ibcon#about to read 3, iclass 29, count 0 2006.257.16:49:34.45#ibcon#read 3, iclass 29, count 0 2006.257.16:49:34.45#ibcon#about to read 4, iclass 29, count 0 2006.257.16:49:34.45#ibcon#read 4, iclass 29, count 0 2006.257.16:49:34.45#ibcon#about to read 5, iclass 29, count 0 2006.257.16:49:34.45#ibcon#read 5, iclass 29, count 0 2006.257.16:49:34.45#ibcon#about to read 6, iclass 29, count 0 2006.257.16:49:34.45#ibcon#read 6, iclass 29, count 0 2006.257.16:49:34.45#ibcon#end of sib2, iclass 29, count 0 2006.257.16:49:34.45#ibcon#*mode == 0, iclass 29, count 0 2006.257.16:49:34.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.16:49:34.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.16:49:34.45#ibcon#*before write, iclass 29, count 0 2006.257.16:49:34.45#ibcon#enter sib2, iclass 29, count 0 2006.257.16:49:34.45#ibcon#flushed, iclass 29, count 0 2006.257.16:49:34.45#ibcon#about to write, iclass 29, count 0 2006.257.16:49:34.45#ibcon#wrote, iclass 29, count 0 2006.257.16:49:34.45#ibcon#about to read 3, iclass 29, count 0 2006.257.16:49:34.49#ibcon#read 3, iclass 29, count 0 2006.257.16:49:34.49#ibcon#about to read 4, iclass 29, count 0 2006.257.16:49:34.49#ibcon#read 4, iclass 29, count 0 2006.257.16:49:34.49#ibcon#about to read 5, iclass 29, count 0 2006.257.16:49:34.49#ibcon#read 5, iclass 29, count 0 2006.257.16:49:34.49#ibcon#about to read 6, iclass 29, count 0 2006.257.16:49:34.49#ibcon#read 6, iclass 29, count 0 2006.257.16:49:34.49#ibcon#end of sib2, iclass 29, count 0 2006.257.16:49:34.49#ibcon#*after write, iclass 29, count 0 2006.257.16:49:34.49#ibcon#*before return 0, iclass 29, count 0 2006.257.16:49:34.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:34.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.16:49:34.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.16:49:34.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.16:49:34.49$vck44/vb=2,5 2006.257.16:49:34.49#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.16:49:34.49#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.16:49:34.49#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:34.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:34.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:34.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:34.55#ibcon#enter wrdev, iclass 31, count 2 2006.257.16:49:34.55#ibcon#first serial, iclass 31, count 2 2006.257.16:49:34.55#ibcon#enter sib2, iclass 31, count 2 2006.257.16:49:34.55#ibcon#flushed, iclass 31, count 2 2006.257.16:49:34.55#ibcon#about to write, iclass 31, count 2 2006.257.16:49:34.55#ibcon#wrote, iclass 31, count 2 2006.257.16:49:34.55#ibcon#about to read 3, iclass 31, count 2 2006.257.16:49:34.57#ibcon#read 3, iclass 31, count 2 2006.257.16:49:34.57#ibcon#about to read 4, iclass 31, count 2 2006.257.16:49:34.57#ibcon#read 4, iclass 31, count 2 2006.257.16:49:34.57#ibcon#about to read 5, iclass 31, count 2 2006.257.16:49:34.57#ibcon#read 5, iclass 31, count 2 2006.257.16:49:34.57#ibcon#about to read 6, iclass 31, count 2 2006.257.16:49:34.57#ibcon#read 6, iclass 31, count 2 2006.257.16:49:34.57#ibcon#end of sib2, iclass 31, count 2 2006.257.16:49:34.57#ibcon#*mode == 0, iclass 31, count 2 2006.257.16:49:34.57#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.16:49:34.57#ibcon#[27=AT02-05\r\n] 2006.257.16:49:34.57#ibcon#*before write, iclass 31, count 2 2006.257.16:49:34.57#ibcon#enter sib2, iclass 31, count 2 2006.257.16:49:34.57#ibcon#flushed, iclass 31, count 2 2006.257.16:49:34.57#ibcon#about to write, iclass 31, count 2 2006.257.16:49:34.57#ibcon#wrote, iclass 31, count 2 2006.257.16:49:34.57#ibcon#about to read 3, iclass 31, count 2 2006.257.16:49:34.60#ibcon#read 3, iclass 31, count 2 2006.257.16:49:34.60#ibcon#about to read 4, iclass 31, count 2 2006.257.16:49:34.60#ibcon#read 4, iclass 31, count 2 2006.257.16:49:34.60#ibcon#about to read 5, iclass 31, count 2 2006.257.16:49:34.60#ibcon#read 5, iclass 31, count 2 2006.257.16:49:34.60#ibcon#about to read 6, iclass 31, count 2 2006.257.16:49:34.60#ibcon#read 6, iclass 31, count 2 2006.257.16:49:34.60#ibcon#end of sib2, iclass 31, count 2 2006.257.16:49:34.60#ibcon#*after write, iclass 31, count 2 2006.257.16:49:34.60#ibcon#*before return 0, iclass 31, count 2 2006.257.16:49:34.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:34.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.16:49:34.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.16:49:34.60#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:34.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:34.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:34.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:34.72#ibcon#enter wrdev, iclass 31, count 0 2006.257.16:49:34.72#ibcon#first serial, iclass 31, count 0 2006.257.16:49:34.72#ibcon#enter sib2, iclass 31, count 0 2006.257.16:49:34.72#ibcon#flushed, iclass 31, count 0 2006.257.16:49:34.72#ibcon#about to write, iclass 31, count 0 2006.257.16:49:34.72#ibcon#wrote, iclass 31, count 0 2006.257.16:49:34.72#ibcon#about to read 3, iclass 31, count 0 2006.257.16:49:34.74#ibcon#read 3, iclass 31, count 0 2006.257.16:49:34.74#ibcon#about to read 4, iclass 31, count 0 2006.257.16:49:34.74#ibcon#read 4, iclass 31, count 0 2006.257.16:49:34.74#ibcon#about to read 5, iclass 31, count 0 2006.257.16:49:34.74#ibcon#read 5, iclass 31, count 0 2006.257.16:49:34.74#ibcon#about to read 6, iclass 31, count 0 2006.257.16:49:34.74#ibcon#read 6, iclass 31, count 0 2006.257.16:49:34.74#ibcon#end of sib2, iclass 31, count 0 2006.257.16:49:34.74#ibcon#*mode == 0, iclass 31, count 0 2006.257.16:49:34.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.16:49:34.74#ibcon#[27=USB\r\n] 2006.257.16:49:34.74#ibcon#*before write, iclass 31, count 0 2006.257.16:49:34.74#ibcon#enter sib2, iclass 31, count 0 2006.257.16:49:34.74#ibcon#flushed, iclass 31, count 0 2006.257.16:49:34.74#ibcon#about to write, iclass 31, count 0 2006.257.16:49:34.74#ibcon#wrote, iclass 31, count 0 2006.257.16:49:34.74#ibcon#about to read 3, iclass 31, count 0 2006.257.16:49:34.77#ibcon#read 3, iclass 31, count 0 2006.257.16:49:34.77#ibcon#about to read 4, iclass 31, count 0 2006.257.16:49:34.77#ibcon#read 4, iclass 31, count 0 2006.257.16:49:34.77#ibcon#about to read 5, iclass 31, count 0 2006.257.16:49:34.77#ibcon#read 5, iclass 31, count 0 2006.257.16:49:34.77#ibcon#about to read 6, iclass 31, count 0 2006.257.16:49:34.77#ibcon#read 6, iclass 31, count 0 2006.257.16:49:34.77#ibcon#end of sib2, iclass 31, count 0 2006.257.16:49:34.77#ibcon#*after write, iclass 31, count 0 2006.257.16:49:34.77#ibcon#*before return 0, iclass 31, count 0 2006.257.16:49:34.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:34.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.16:49:34.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.16:49:34.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.16:49:34.77$vck44/vblo=3,649.99 2006.257.16:49:34.77#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.16:49:34.77#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.16:49:34.77#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:34.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:34.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:34.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:34.77#ibcon#enter wrdev, iclass 33, count 0 2006.257.16:49:34.77#ibcon#first serial, iclass 33, count 0 2006.257.16:49:34.77#ibcon#enter sib2, iclass 33, count 0 2006.257.16:49:34.77#ibcon#flushed, iclass 33, count 0 2006.257.16:49:34.77#ibcon#about to write, iclass 33, count 0 2006.257.16:49:34.77#ibcon#wrote, iclass 33, count 0 2006.257.16:49:34.77#ibcon#about to read 3, iclass 33, count 0 2006.257.16:49:34.79#ibcon#read 3, iclass 33, count 0 2006.257.16:49:34.79#ibcon#about to read 4, iclass 33, count 0 2006.257.16:49:34.79#ibcon#read 4, iclass 33, count 0 2006.257.16:49:34.79#ibcon#about to read 5, iclass 33, count 0 2006.257.16:49:34.79#ibcon#read 5, iclass 33, count 0 2006.257.16:49:34.79#ibcon#about to read 6, iclass 33, count 0 2006.257.16:49:34.79#ibcon#read 6, iclass 33, count 0 2006.257.16:49:34.79#ibcon#end of sib2, iclass 33, count 0 2006.257.16:49:34.79#ibcon#*mode == 0, iclass 33, count 0 2006.257.16:49:34.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.16:49:34.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.16:49:34.79#ibcon#*before write, iclass 33, count 0 2006.257.16:49:34.79#ibcon#enter sib2, iclass 33, count 0 2006.257.16:49:34.79#ibcon#flushed, iclass 33, count 0 2006.257.16:49:34.79#ibcon#about to write, iclass 33, count 0 2006.257.16:49:34.79#ibcon#wrote, iclass 33, count 0 2006.257.16:49:34.79#ibcon#about to read 3, iclass 33, count 0 2006.257.16:49:34.83#ibcon#read 3, iclass 33, count 0 2006.257.16:49:34.83#ibcon#about to read 4, iclass 33, count 0 2006.257.16:49:34.83#ibcon#read 4, iclass 33, count 0 2006.257.16:49:34.83#ibcon#about to read 5, iclass 33, count 0 2006.257.16:49:34.83#ibcon#read 5, iclass 33, count 0 2006.257.16:49:34.83#ibcon#about to read 6, iclass 33, count 0 2006.257.16:49:34.83#ibcon#read 6, iclass 33, count 0 2006.257.16:49:34.83#ibcon#end of sib2, iclass 33, count 0 2006.257.16:49:34.83#ibcon#*after write, iclass 33, count 0 2006.257.16:49:34.83#ibcon#*before return 0, iclass 33, count 0 2006.257.16:49:34.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:34.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.16:49:34.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.16:49:34.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.16:49:34.83$vck44/vb=3,4 2006.257.16:49:34.83#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.16:49:34.83#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.16:49:34.83#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:34.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:34.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:34.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:34.89#ibcon#enter wrdev, iclass 35, count 2 2006.257.16:49:34.89#ibcon#first serial, iclass 35, count 2 2006.257.16:49:34.89#ibcon#enter sib2, iclass 35, count 2 2006.257.16:49:34.89#ibcon#flushed, iclass 35, count 2 2006.257.16:49:34.89#ibcon#about to write, iclass 35, count 2 2006.257.16:49:34.89#ibcon#wrote, iclass 35, count 2 2006.257.16:49:34.89#ibcon#about to read 3, iclass 35, count 2 2006.257.16:49:34.91#ibcon#read 3, iclass 35, count 2 2006.257.16:49:34.91#ibcon#about to read 4, iclass 35, count 2 2006.257.16:49:34.91#ibcon#read 4, iclass 35, count 2 2006.257.16:49:34.91#ibcon#about to read 5, iclass 35, count 2 2006.257.16:49:34.91#ibcon#read 5, iclass 35, count 2 2006.257.16:49:34.91#ibcon#about to read 6, iclass 35, count 2 2006.257.16:49:34.91#ibcon#read 6, iclass 35, count 2 2006.257.16:49:34.91#ibcon#end of sib2, iclass 35, count 2 2006.257.16:49:34.91#ibcon#*mode == 0, iclass 35, count 2 2006.257.16:49:34.91#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.16:49:34.91#ibcon#[27=AT03-04\r\n] 2006.257.16:49:34.91#ibcon#*before write, iclass 35, count 2 2006.257.16:49:34.91#ibcon#enter sib2, iclass 35, count 2 2006.257.16:49:34.91#ibcon#flushed, iclass 35, count 2 2006.257.16:49:34.91#ibcon#about to write, iclass 35, count 2 2006.257.16:49:34.91#ibcon#wrote, iclass 35, count 2 2006.257.16:49:34.91#ibcon#about to read 3, iclass 35, count 2 2006.257.16:49:34.94#ibcon#read 3, iclass 35, count 2 2006.257.16:49:34.94#ibcon#about to read 4, iclass 35, count 2 2006.257.16:49:34.94#ibcon#read 4, iclass 35, count 2 2006.257.16:49:34.94#ibcon#about to read 5, iclass 35, count 2 2006.257.16:49:34.94#ibcon#read 5, iclass 35, count 2 2006.257.16:49:34.94#ibcon#about to read 6, iclass 35, count 2 2006.257.16:49:34.94#ibcon#read 6, iclass 35, count 2 2006.257.16:49:34.94#ibcon#end of sib2, iclass 35, count 2 2006.257.16:49:34.94#ibcon#*after write, iclass 35, count 2 2006.257.16:49:34.94#ibcon#*before return 0, iclass 35, count 2 2006.257.16:49:34.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:34.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.16:49:34.94#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.16:49:34.94#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:34.94#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:35.06#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:35.06#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:35.06#ibcon#enter wrdev, iclass 35, count 0 2006.257.16:49:35.06#ibcon#first serial, iclass 35, count 0 2006.257.16:49:35.06#ibcon#enter sib2, iclass 35, count 0 2006.257.16:49:35.06#ibcon#flushed, iclass 35, count 0 2006.257.16:49:35.06#ibcon#about to write, iclass 35, count 0 2006.257.16:49:35.06#ibcon#wrote, iclass 35, count 0 2006.257.16:49:35.06#ibcon#about to read 3, iclass 35, count 0 2006.257.16:49:35.08#ibcon#read 3, iclass 35, count 0 2006.257.16:49:35.08#ibcon#about to read 4, iclass 35, count 0 2006.257.16:49:35.08#ibcon#read 4, iclass 35, count 0 2006.257.16:49:35.08#ibcon#about to read 5, iclass 35, count 0 2006.257.16:49:35.08#ibcon#read 5, iclass 35, count 0 2006.257.16:49:35.08#ibcon#about to read 6, iclass 35, count 0 2006.257.16:49:35.08#ibcon#read 6, iclass 35, count 0 2006.257.16:49:35.08#ibcon#end of sib2, iclass 35, count 0 2006.257.16:49:35.08#ibcon#*mode == 0, iclass 35, count 0 2006.257.16:49:35.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.16:49:35.08#ibcon#[27=USB\r\n] 2006.257.16:49:35.08#ibcon#*before write, iclass 35, count 0 2006.257.16:49:35.08#ibcon#enter sib2, iclass 35, count 0 2006.257.16:49:35.08#ibcon#flushed, iclass 35, count 0 2006.257.16:49:35.08#ibcon#about to write, iclass 35, count 0 2006.257.16:49:35.08#ibcon#wrote, iclass 35, count 0 2006.257.16:49:35.08#ibcon#about to read 3, iclass 35, count 0 2006.257.16:49:35.11#ibcon#read 3, iclass 35, count 0 2006.257.16:49:35.11#ibcon#about to read 4, iclass 35, count 0 2006.257.16:49:35.11#ibcon#read 4, iclass 35, count 0 2006.257.16:49:35.11#ibcon#about to read 5, iclass 35, count 0 2006.257.16:49:35.11#ibcon#read 5, iclass 35, count 0 2006.257.16:49:35.11#ibcon#about to read 6, iclass 35, count 0 2006.257.16:49:35.11#ibcon#read 6, iclass 35, count 0 2006.257.16:49:35.11#ibcon#end of sib2, iclass 35, count 0 2006.257.16:49:35.11#ibcon#*after write, iclass 35, count 0 2006.257.16:49:35.11#ibcon#*before return 0, iclass 35, count 0 2006.257.16:49:35.11#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:35.11#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.16:49:35.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.16:49:35.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.16:49:35.11$vck44/vblo=4,679.99 2006.257.16:49:35.11#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.16:49:35.11#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.16:49:35.11#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:35.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:35.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:35.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:35.11#ibcon#enter wrdev, iclass 37, count 0 2006.257.16:49:35.11#ibcon#first serial, iclass 37, count 0 2006.257.16:49:35.11#ibcon#enter sib2, iclass 37, count 0 2006.257.16:49:35.11#ibcon#flushed, iclass 37, count 0 2006.257.16:49:35.11#ibcon#about to write, iclass 37, count 0 2006.257.16:49:35.11#ibcon#wrote, iclass 37, count 0 2006.257.16:49:35.11#ibcon#about to read 3, iclass 37, count 0 2006.257.16:49:35.13#ibcon#read 3, iclass 37, count 0 2006.257.16:49:35.13#ibcon#about to read 4, iclass 37, count 0 2006.257.16:49:35.13#ibcon#read 4, iclass 37, count 0 2006.257.16:49:35.13#ibcon#about to read 5, iclass 37, count 0 2006.257.16:49:35.13#ibcon#read 5, iclass 37, count 0 2006.257.16:49:35.13#ibcon#about to read 6, iclass 37, count 0 2006.257.16:49:35.13#ibcon#read 6, iclass 37, count 0 2006.257.16:49:35.13#ibcon#end of sib2, iclass 37, count 0 2006.257.16:49:35.13#ibcon#*mode == 0, iclass 37, count 0 2006.257.16:49:35.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.16:49:35.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.16:49:35.13#ibcon#*before write, iclass 37, count 0 2006.257.16:49:35.13#ibcon#enter sib2, iclass 37, count 0 2006.257.16:49:35.13#ibcon#flushed, iclass 37, count 0 2006.257.16:49:35.13#ibcon#about to write, iclass 37, count 0 2006.257.16:49:35.13#ibcon#wrote, iclass 37, count 0 2006.257.16:49:35.13#ibcon#about to read 3, iclass 37, count 0 2006.257.16:49:35.17#ibcon#read 3, iclass 37, count 0 2006.257.16:49:35.17#ibcon#about to read 4, iclass 37, count 0 2006.257.16:49:35.17#ibcon#read 4, iclass 37, count 0 2006.257.16:49:35.17#ibcon#about to read 5, iclass 37, count 0 2006.257.16:49:35.17#ibcon#read 5, iclass 37, count 0 2006.257.16:49:35.17#ibcon#about to read 6, iclass 37, count 0 2006.257.16:49:35.17#ibcon#read 6, iclass 37, count 0 2006.257.16:49:35.17#ibcon#end of sib2, iclass 37, count 0 2006.257.16:49:35.17#ibcon#*after write, iclass 37, count 0 2006.257.16:49:35.17#ibcon#*before return 0, iclass 37, count 0 2006.257.16:49:35.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:35.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.16:49:35.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.16:49:35.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.16:49:35.17$vck44/vb=4,5 2006.257.16:49:35.17#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.16:49:35.17#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.16:49:35.17#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:35.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:35.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:35.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:35.23#ibcon#enter wrdev, iclass 39, count 2 2006.257.16:49:35.23#ibcon#first serial, iclass 39, count 2 2006.257.16:49:35.23#ibcon#enter sib2, iclass 39, count 2 2006.257.16:49:35.23#ibcon#flushed, iclass 39, count 2 2006.257.16:49:35.23#ibcon#about to write, iclass 39, count 2 2006.257.16:49:35.23#ibcon#wrote, iclass 39, count 2 2006.257.16:49:35.23#ibcon#about to read 3, iclass 39, count 2 2006.257.16:49:35.25#ibcon#read 3, iclass 39, count 2 2006.257.16:49:35.25#ibcon#about to read 4, iclass 39, count 2 2006.257.16:49:35.25#ibcon#read 4, iclass 39, count 2 2006.257.16:49:35.25#ibcon#about to read 5, iclass 39, count 2 2006.257.16:49:35.25#ibcon#read 5, iclass 39, count 2 2006.257.16:49:35.25#ibcon#about to read 6, iclass 39, count 2 2006.257.16:49:35.25#ibcon#read 6, iclass 39, count 2 2006.257.16:49:35.25#ibcon#end of sib2, iclass 39, count 2 2006.257.16:49:35.25#ibcon#*mode == 0, iclass 39, count 2 2006.257.16:49:35.25#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.16:49:35.25#ibcon#[27=AT04-05\r\n] 2006.257.16:49:35.25#ibcon#*before write, iclass 39, count 2 2006.257.16:49:35.25#ibcon#enter sib2, iclass 39, count 2 2006.257.16:49:35.25#ibcon#flushed, iclass 39, count 2 2006.257.16:49:35.25#ibcon#about to write, iclass 39, count 2 2006.257.16:49:35.25#ibcon#wrote, iclass 39, count 2 2006.257.16:49:35.25#ibcon#about to read 3, iclass 39, count 2 2006.257.16:49:35.28#ibcon#read 3, iclass 39, count 2 2006.257.16:49:35.28#ibcon#about to read 4, iclass 39, count 2 2006.257.16:49:35.28#ibcon#read 4, iclass 39, count 2 2006.257.16:49:35.28#ibcon#about to read 5, iclass 39, count 2 2006.257.16:49:35.28#ibcon#read 5, iclass 39, count 2 2006.257.16:49:35.28#ibcon#about to read 6, iclass 39, count 2 2006.257.16:49:35.28#ibcon#read 6, iclass 39, count 2 2006.257.16:49:35.28#ibcon#end of sib2, iclass 39, count 2 2006.257.16:49:35.28#ibcon#*after write, iclass 39, count 2 2006.257.16:49:35.28#ibcon#*before return 0, iclass 39, count 2 2006.257.16:49:35.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:35.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.16:49:35.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.16:49:35.28#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:35.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:35.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:35.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:35.40#ibcon#enter wrdev, iclass 39, count 0 2006.257.16:49:35.40#ibcon#first serial, iclass 39, count 0 2006.257.16:49:35.40#ibcon#enter sib2, iclass 39, count 0 2006.257.16:49:35.40#ibcon#flushed, iclass 39, count 0 2006.257.16:49:35.40#ibcon#about to write, iclass 39, count 0 2006.257.16:49:35.40#ibcon#wrote, iclass 39, count 0 2006.257.16:49:35.40#ibcon#about to read 3, iclass 39, count 0 2006.257.16:49:35.42#ibcon#read 3, iclass 39, count 0 2006.257.16:49:35.42#ibcon#about to read 4, iclass 39, count 0 2006.257.16:49:35.42#ibcon#read 4, iclass 39, count 0 2006.257.16:49:35.42#ibcon#about to read 5, iclass 39, count 0 2006.257.16:49:35.42#ibcon#read 5, iclass 39, count 0 2006.257.16:49:35.42#ibcon#about to read 6, iclass 39, count 0 2006.257.16:49:35.42#ibcon#read 6, iclass 39, count 0 2006.257.16:49:35.42#ibcon#end of sib2, iclass 39, count 0 2006.257.16:49:35.42#ibcon#*mode == 0, iclass 39, count 0 2006.257.16:49:35.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.16:49:35.42#ibcon#[27=USB\r\n] 2006.257.16:49:35.42#ibcon#*before write, iclass 39, count 0 2006.257.16:49:35.42#ibcon#enter sib2, iclass 39, count 0 2006.257.16:49:35.42#ibcon#flushed, iclass 39, count 0 2006.257.16:49:35.42#ibcon#about to write, iclass 39, count 0 2006.257.16:49:35.42#ibcon#wrote, iclass 39, count 0 2006.257.16:49:35.42#ibcon#about to read 3, iclass 39, count 0 2006.257.16:49:35.45#ibcon#read 3, iclass 39, count 0 2006.257.16:49:35.45#ibcon#about to read 4, iclass 39, count 0 2006.257.16:49:35.45#ibcon#read 4, iclass 39, count 0 2006.257.16:49:35.45#ibcon#about to read 5, iclass 39, count 0 2006.257.16:49:35.45#ibcon#read 5, iclass 39, count 0 2006.257.16:49:35.45#ibcon#about to read 6, iclass 39, count 0 2006.257.16:49:35.45#ibcon#read 6, iclass 39, count 0 2006.257.16:49:35.45#ibcon#end of sib2, iclass 39, count 0 2006.257.16:49:35.45#ibcon#*after write, iclass 39, count 0 2006.257.16:49:35.45#ibcon#*before return 0, iclass 39, count 0 2006.257.16:49:35.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:35.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.16:49:35.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.16:49:35.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.16:49:35.45$vck44/vblo=5,709.99 2006.257.16:49:35.45#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.16:49:35.45#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.16:49:35.45#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:35.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:35.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:35.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:35.45#ibcon#enter wrdev, iclass 3, count 0 2006.257.16:49:35.45#ibcon#first serial, iclass 3, count 0 2006.257.16:49:35.45#ibcon#enter sib2, iclass 3, count 0 2006.257.16:49:35.45#ibcon#flushed, iclass 3, count 0 2006.257.16:49:35.45#ibcon#about to write, iclass 3, count 0 2006.257.16:49:35.45#ibcon#wrote, iclass 3, count 0 2006.257.16:49:35.45#ibcon#about to read 3, iclass 3, count 0 2006.257.16:49:35.47#ibcon#read 3, iclass 3, count 0 2006.257.16:49:35.47#ibcon#about to read 4, iclass 3, count 0 2006.257.16:49:35.47#ibcon#read 4, iclass 3, count 0 2006.257.16:49:35.47#ibcon#about to read 5, iclass 3, count 0 2006.257.16:49:35.47#ibcon#read 5, iclass 3, count 0 2006.257.16:49:35.47#ibcon#about to read 6, iclass 3, count 0 2006.257.16:49:35.47#ibcon#read 6, iclass 3, count 0 2006.257.16:49:35.47#ibcon#end of sib2, iclass 3, count 0 2006.257.16:49:35.47#ibcon#*mode == 0, iclass 3, count 0 2006.257.16:49:35.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.16:49:35.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:49:35.47#ibcon#*before write, iclass 3, count 0 2006.257.16:49:35.47#ibcon#enter sib2, iclass 3, count 0 2006.257.16:49:35.47#ibcon#flushed, iclass 3, count 0 2006.257.16:49:35.47#ibcon#about to write, iclass 3, count 0 2006.257.16:49:35.47#ibcon#wrote, iclass 3, count 0 2006.257.16:49:35.47#ibcon#about to read 3, iclass 3, count 0 2006.257.16:49:35.51#ibcon#read 3, iclass 3, count 0 2006.257.16:49:35.51#ibcon#about to read 4, iclass 3, count 0 2006.257.16:49:35.51#ibcon#read 4, iclass 3, count 0 2006.257.16:49:35.51#ibcon#about to read 5, iclass 3, count 0 2006.257.16:49:35.51#ibcon#read 5, iclass 3, count 0 2006.257.16:49:35.51#ibcon#about to read 6, iclass 3, count 0 2006.257.16:49:35.51#ibcon#read 6, iclass 3, count 0 2006.257.16:49:35.51#ibcon#end of sib2, iclass 3, count 0 2006.257.16:49:35.51#ibcon#*after write, iclass 3, count 0 2006.257.16:49:35.51#ibcon#*before return 0, iclass 3, count 0 2006.257.16:49:35.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:35.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.16:49:35.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.16:49:35.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.16:49:35.51$vck44/vb=5,4 2006.257.16:49:35.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.16:49:35.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.16:49:35.51#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:35.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:35.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:35.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:35.57#ibcon#enter wrdev, iclass 5, count 2 2006.257.16:49:35.57#ibcon#first serial, iclass 5, count 2 2006.257.16:49:35.57#ibcon#enter sib2, iclass 5, count 2 2006.257.16:49:35.57#ibcon#flushed, iclass 5, count 2 2006.257.16:49:35.57#ibcon#about to write, iclass 5, count 2 2006.257.16:49:35.57#ibcon#wrote, iclass 5, count 2 2006.257.16:49:35.57#ibcon#about to read 3, iclass 5, count 2 2006.257.16:49:35.59#ibcon#read 3, iclass 5, count 2 2006.257.16:49:35.59#ibcon#about to read 4, iclass 5, count 2 2006.257.16:49:35.59#ibcon#read 4, iclass 5, count 2 2006.257.16:49:35.59#ibcon#about to read 5, iclass 5, count 2 2006.257.16:49:35.59#ibcon#read 5, iclass 5, count 2 2006.257.16:49:35.59#ibcon#about to read 6, iclass 5, count 2 2006.257.16:49:35.59#ibcon#read 6, iclass 5, count 2 2006.257.16:49:35.59#ibcon#end of sib2, iclass 5, count 2 2006.257.16:49:35.59#ibcon#*mode == 0, iclass 5, count 2 2006.257.16:49:35.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.16:49:35.59#ibcon#[27=AT05-04\r\n] 2006.257.16:49:35.59#ibcon#*before write, iclass 5, count 2 2006.257.16:49:35.59#ibcon#enter sib2, iclass 5, count 2 2006.257.16:49:35.59#ibcon#flushed, iclass 5, count 2 2006.257.16:49:35.59#ibcon#about to write, iclass 5, count 2 2006.257.16:49:35.59#ibcon#wrote, iclass 5, count 2 2006.257.16:49:35.59#ibcon#about to read 3, iclass 5, count 2 2006.257.16:49:35.62#ibcon#read 3, iclass 5, count 2 2006.257.16:49:35.62#ibcon#about to read 4, iclass 5, count 2 2006.257.16:49:35.62#ibcon#read 4, iclass 5, count 2 2006.257.16:49:35.62#ibcon#about to read 5, iclass 5, count 2 2006.257.16:49:35.62#ibcon#read 5, iclass 5, count 2 2006.257.16:49:35.62#ibcon#about to read 6, iclass 5, count 2 2006.257.16:49:35.62#ibcon#read 6, iclass 5, count 2 2006.257.16:49:35.62#ibcon#end of sib2, iclass 5, count 2 2006.257.16:49:35.62#ibcon#*after write, iclass 5, count 2 2006.257.16:49:35.62#ibcon#*before return 0, iclass 5, count 2 2006.257.16:49:35.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:35.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.16:49:35.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.16:49:35.62#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:35.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:35.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:35.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:35.74#ibcon#enter wrdev, iclass 5, count 0 2006.257.16:49:35.74#ibcon#first serial, iclass 5, count 0 2006.257.16:49:35.74#ibcon#enter sib2, iclass 5, count 0 2006.257.16:49:35.74#ibcon#flushed, iclass 5, count 0 2006.257.16:49:35.74#ibcon#about to write, iclass 5, count 0 2006.257.16:49:35.74#ibcon#wrote, iclass 5, count 0 2006.257.16:49:35.74#ibcon#about to read 3, iclass 5, count 0 2006.257.16:49:35.76#ibcon#read 3, iclass 5, count 0 2006.257.16:49:35.76#ibcon#about to read 4, iclass 5, count 0 2006.257.16:49:35.76#ibcon#read 4, iclass 5, count 0 2006.257.16:49:35.76#ibcon#about to read 5, iclass 5, count 0 2006.257.16:49:35.76#ibcon#read 5, iclass 5, count 0 2006.257.16:49:35.76#ibcon#about to read 6, iclass 5, count 0 2006.257.16:49:35.76#ibcon#read 6, iclass 5, count 0 2006.257.16:49:35.76#ibcon#end of sib2, iclass 5, count 0 2006.257.16:49:35.76#ibcon#*mode == 0, iclass 5, count 0 2006.257.16:49:35.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.16:49:35.76#ibcon#[27=USB\r\n] 2006.257.16:49:35.76#ibcon#*before write, iclass 5, count 0 2006.257.16:49:35.76#ibcon#enter sib2, iclass 5, count 0 2006.257.16:49:35.76#ibcon#flushed, iclass 5, count 0 2006.257.16:49:35.76#ibcon#about to write, iclass 5, count 0 2006.257.16:49:35.76#ibcon#wrote, iclass 5, count 0 2006.257.16:49:35.76#ibcon#about to read 3, iclass 5, count 0 2006.257.16:49:35.79#ibcon#read 3, iclass 5, count 0 2006.257.16:49:35.79#ibcon#about to read 4, iclass 5, count 0 2006.257.16:49:35.79#ibcon#read 4, iclass 5, count 0 2006.257.16:49:35.79#ibcon#about to read 5, iclass 5, count 0 2006.257.16:49:35.79#ibcon#read 5, iclass 5, count 0 2006.257.16:49:35.79#ibcon#about to read 6, iclass 5, count 0 2006.257.16:49:35.79#ibcon#read 6, iclass 5, count 0 2006.257.16:49:35.79#ibcon#end of sib2, iclass 5, count 0 2006.257.16:49:35.79#ibcon#*after write, iclass 5, count 0 2006.257.16:49:35.79#ibcon#*before return 0, iclass 5, count 0 2006.257.16:49:35.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:35.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.16:49:35.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.16:49:35.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.16:49:35.79$vck44/vblo=6,719.99 2006.257.16:49:35.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.16:49:35.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.16:49:35.79#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:35.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:35.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:35.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:35.79#ibcon#enter wrdev, iclass 7, count 0 2006.257.16:49:35.79#ibcon#first serial, iclass 7, count 0 2006.257.16:49:35.79#ibcon#enter sib2, iclass 7, count 0 2006.257.16:49:35.79#ibcon#flushed, iclass 7, count 0 2006.257.16:49:35.79#ibcon#about to write, iclass 7, count 0 2006.257.16:49:35.79#ibcon#wrote, iclass 7, count 0 2006.257.16:49:35.79#ibcon#about to read 3, iclass 7, count 0 2006.257.16:49:35.81#ibcon#read 3, iclass 7, count 0 2006.257.16:49:35.81#ibcon#about to read 4, iclass 7, count 0 2006.257.16:49:35.81#ibcon#read 4, iclass 7, count 0 2006.257.16:49:35.81#ibcon#about to read 5, iclass 7, count 0 2006.257.16:49:35.81#ibcon#read 5, iclass 7, count 0 2006.257.16:49:35.81#ibcon#about to read 6, iclass 7, count 0 2006.257.16:49:35.81#ibcon#read 6, iclass 7, count 0 2006.257.16:49:35.81#ibcon#end of sib2, iclass 7, count 0 2006.257.16:49:35.81#ibcon#*mode == 0, iclass 7, count 0 2006.257.16:49:35.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.16:49:35.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:49:35.81#ibcon#*before write, iclass 7, count 0 2006.257.16:49:35.81#ibcon#enter sib2, iclass 7, count 0 2006.257.16:49:35.81#ibcon#flushed, iclass 7, count 0 2006.257.16:49:35.81#ibcon#about to write, iclass 7, count 0 2006.257.16:49:35.81#ibcon#wrote, iclass 7, count 0 2006.257.16:49:35.81#ibcon#about to read 3, iclass 7, count 0 2006.257.16:49:35.85#ibcon#read 3, iclass 7, count 0 2006.257.16:49:35.85#ibcon#about to read 4, iclass 7, count 0 2006.257.16:49:35.85#ibcon#read 4, iclass 7, count 0 2006.257.16:49:35.85#ibcon#about to read 5, iclass 7, count 0 2006.257.16:49:35.85#ibcon#read 5, iclass 7, count 0 2006.257.16:49:35.85#ibcon#about to read 6, iclass 7, count 0 2006.257.16:49:35.85#ibcon#read 6, iclass 7, count 0 2006.257.16:49:35.85#ibcon#end of sib2, iclass 7, count 0 2006.257.16:49:35.85#ibcon#*after write, iclass 7, count 0 2006.257.16:49:35.85#ibcon#*before return 0, iclass 7, count 0 2006.257.16:49:35.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:35.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.16:49:35.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.16:49:35.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.16:49:35.85$vck44/vb=6,4 2006.257.16:49:35.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.16:49:35.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.16:49:35.85#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:35.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:35.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:35.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:35.91#ibcon#enter wrdev, iclass 11, count 2 2006.257.16:49:35.91#ibcon#first serial, iclass 11, count 2 2006.257.16:49:35.91#ibcon#enter sib2, iclass 11, count 2 2006.257.16:49:35.91#ibcon#flushed, iclass 11, count 2 2006.257.16:49:35.91#ibcon#about to write, iclass 11, count 2 2006.257.16:49:35.91#ibcon#wrote, iclass 11, count 2 2006.257.16:49:35.91#ibcon#about to read 3, iclass 11, count 2 2006.257.16:49:35.93#ibcon#read 3, iclass 11, count 2 2006.257.16:49:35.93#ibcon#about to read 4, iclass 11, count 2 2006.257.16:49:35.93#ibcon#read 4, iclass 11, count 2 2006.257.16:49:35.93#ibcon#about to read 5, iclass 11, count 2 2006.257.16:49:35.93#ibcon#read 5, iclass 11, count 2 2006.257.16:49:35.93#ibcon#about to read 6, iclass 11, count 2 2006.257.16:49:35.93#ibcon#read 6, iclass 11, count 2 2006.257.16:49:35.93#ibcon#end of sib2, iclass 11, count 2 2006.257.16:49:35.93#ibcon#*mode == 0, iclass 11, count 2 2006.257.16:49:35.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.16:49:35.93#ibcon#[27=AT06-04\r\n] 2006.257.16:49:35.93#ibcon#*before write, iclass 11, count 2 2006.257.16:49:35.93#ibcon#enter sib2, iclass 11, count 2 2006.257.16:49:35.93#ibcon#flushed, iclass 11, count 2 2006.257.16:49:35.93#ibcon#about to write, iclass 11, count 2 2006.257.16:49:35.93#ibcon#wrote, iclass 11, count 2 2006.257.16:49:35.93#ibcon#about to read 3, iclass 11, count 2 2006.257.16:49:35.96#ibcon#read 3, iclass 11, count 2 2006.257.16:49:35.96#ibcon#about to read 4, iclass 11, count 2 2006.257.16:49:35.96#ibcon#read 4, iclass 11, count 2 2006.257.16:49:35.96#ibcon#about to read 5, iclass 11, count 2 2006.257.16:49:35.96#ibcon#read 5, iclass 11, count 2 2006.257.16:49:35.96#ibcon#about to read 6, iclass 11, count 2 2006.257.16:49:35.96#ibcon#read 6, iclass 11, count 2 2006.257.16:49:35.96#ibcon#end of sib2, iclass 11, count 2 2006.257.16:49:35.96#ibcon#*after write, iclass 11, count 2 2006.257.16:49:35.96#ibcon#*before return 0, iclass 11, count 2 2006.257.16:49:35.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:35.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.16:49:35.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.16:49:35.96#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:35.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:36.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:36.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:36.08#ibcon#enter wrdev, iclass 11, count 0 2006.257.16:49:36.08#ibcon#first serial, iclass 11, count 0 2006.257.16:49:36.08#ibcon#enter sib2, iclass 11, count 0 2006.257.16:49:36.08#ibcon#flushed, iclass 11, count 0 2006.257.16:49:36.08#ibcon#about to write, iclass 11, count 0 2006.257.16:49:36.08#ibcon#wrote, iclass 11, count 0 2006.257.16:49:36.08#ibcon#about to read 3, iclass 11, count 0 2006.257.16:49:36.10#ibcon#read 3, iclass 11, count 0 2006.257.16:49:36.10#ibcon#about to read 4, iclass 11, count 0 2006.257.16:49:36.10#ibcon#read 4, iclass 11, count 0 2006.257.16:49:36.10#ibcon#about to read 5, iclass 11, count 0 2006.257.16:49:36.10#ibcon#read 5, iclass 11, count 0 2006.257.16:49:36.10#ibcon#about to read 6, iclass 11, count 0 2006.257.16:49:36.10#ibcon#read 6, iclass 11, count 0 2006.257.16:49:36.10#ibcon#end of sib2, iclass 11, count 0 2006.257.16:49:36.10#ibcon#*mode == 0, iclass 11, count 0 2006.257.16:49:36.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.16:49:36.10#ibcon#[27=USB\r\n] 2006.257.16:49:36.10#ibcon#*before write, iclass 11, count 0 2006.257.16:49:36.10#ibcon#enter sib2, iclass 11, count 0 2006.257.16:49:36.10#ibcon#flushed, iclass 11, count 0 2006.257.16:49:36.10#ibcon#about to write, iclass 11, count 0 2006.257.16:49:36.10#ibcon#wrote, iclass 11, count 0 2006.257.16:49:36.10#ibcon#about to read 3, iclass 11, count 0 2006.257.16:49:36.13#ibcon#read 3, iclass 11, count 0 2006.257.16:49:36.13#ibcon#about to read 4, iclass 11, count 0 2006.257.16:49:36.13#ibcon#read 4, iclass 11, count 0 2006.257.16:49:36.13#ibcon#about to read 5, iclass 11, count 0 2006.257.16:49:36.13#ibcon#read 5, iclass 11, count 0 2006.257.16:49:36.13#ibcon#about to read 6, iclass 11, count 0 2006.257.16:49:36.13#ibcon#read 6, iclass 11, count 0 2006.257.16:49:36.13#ibcon#end of sib2, iclass 11, count 0 2006.257.16:49:36.13#ibcon#*after write, iclass 11, count 0 2006.257.16:49:36.13#ibcon#*before return 0, iclass 11, count 0 2006.257.16:49:36.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:36.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.16:49:36.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.16:49:36.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.16:49:36.13$vck44/vblo=7,734.99 2006.257.16:49:36.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.16:49:36.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.16:49:36.13#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:36.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:36.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:36.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:36.13#ibcon#enter wrdev, iclass 13, count 0 2006.257.16:49:36.13#ibcon#first serial, iclass 13, count 0 2006.257.16:49:36.13#ibcon#enter sib2, iclass 13, count 0 2006.257.16:49:36.13#ibcon#flushed, iclass 13, count 0 2006.257.16:49:36.13#ibcon#about to write, iclass 13, count 0 2006.257.16:49:36.13#ibcon#wrote, iclass 13, count 0 2006.257.16:49:36.13#ibcon#about to read 3, iclass 13, count 0 2006.257.16:49:36.15#ibcon#read 3, iclass 13, count 0 2006.257.16:49:36.15#ibcon#about to read 4, iclass 13, count 0 2006.257.16:49:36.15#ibcon#read 4, iclass 13, count 0 2006.257.16:49:36.15#ibcon#about to read 5, iclass 13, count 0 2006.257.16:49:36.15#ibcon#read 5, iclass 13, count 0 2006.257.16:49:36.15#ibcon#about to read 6, iclass 13, count 0 2006.257.16:49:36.15#ibcon#read 6, iclass 13, count 0 2006.257.16:49:36.15#ibcon#end of sib2, iclass 13, count 0 2006.257.16:49:36.15#ibcon#*mode == 0, iclass 13, count 0 2006.257.16:49:36.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.16:49:36.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:49:36.15#ibcon#*before write, iclass 13, count 0 2006.257.16:49:36.15#ibcon#enter sib2, iclass 13, count 0 2006.257.16:49:36.15#ibcon#flushed, iclass 13, count 0 2006.257.16:49:36.15#ibcon#about to write, iclass 13, count 0 2006.257.16:49:36.15#ibcon#wrote, iclass 13, count 0 2006.257.16:49:36.15#ibcon#about to read 3, iclass 13, count 0 2006.257.16:49:36.19#ibcon#read 3, iclass 13, count 0 2006.257.16:49:36.19#ibcon#about to read 4, iclass 13, count 0 2006.257.16:49:36.19#ibcon#read 4, iclass 13, count 0 2006.257.16:49:36.19#ibcon#about to read 5, iclass 13, count 0 2006.257.16:49:36.19#ibcon#read 5, iclass 13, count 0 2006.257.16:49:36.19#ibcon#about to read 6, iclass 13, count 0 2006.257.16:49:36.19#ibcon#read 6, iclass 13, count 0 2006.257.16:49:36.19#ibcon#end of sib2, iclass 13, count 0 2006.257.16:49:36.19#ibcon#*after write, iclass 13, count 0 2006.257.16:49:36.19#ibcon#*before return 0, iclass 13, count 0 2006.257.16:49:36.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:36.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.16:49:36.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.16:49:36.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.16:49:36.19$vck44/vb=7,4 2006.257.16:49:36.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.16:49:36.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.16:49:36.19#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:36.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:36.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:36.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:36.25#ibcon#enter wrdev, iclass 15, count 2 2006.257.16:49:36.25#ibcon#first serial, iclass 15, count 2 2006.257.16:49:36.25#ibcon#enter sib2, iclass 15, count 2 2006.257.16:49:36.25#ibcon#flushed, iclass 15, count 2 2006.257.16:49:36.25#ibcon#about to write, iclass 15, count 2 2006.257.16:49:36.25#ibcon#wrote, iclass 15, count 2 2006.257.16:49:36.25#ibcon#about to read 3, iclass 15, count 2 2006.257.16:49:36.27#ibcon#read 3, iclass 15, count 2 2006.257.16:49:36.27#ibcon#about to read 4, iclass 15, count 2 2006.257.16:49:36.27#ibcon#read 4, iclass 15, count 2 2006.257.16:49:36.27#ibcon#about to read 5, iclass 15, count 2 2006.257.16:49:36.27#ibcon#read 5, iclass 15, count 2 2006.257.16:49:36.27#ibcon#about to read 6, iclass 15, count 2 2006.257.16:49:36.27#ibcon#read 6, iclass 15, count 2 2006.257.16:49:36.27#ibcon#end of sib2, iclass 15, count 2 2006.257.16:49:36.27#ibcon#*mode == 0, iclass 15, count 2 2006.257.16:49:36.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.16:49:36.27#ibcon#[27=AT07-04\r\n] 2006.257.16:49:36.27#ibcon#*before write, iclass 15, count 2 2006.257.16:49:36.27#ibcon#enter sib2, iclass 15, count 2 2006.257.16:49:36.27#ibcon#flushed, iclass 15, count 2 2006.257.16:49:36.27#ibcon#about to write, iclass 15, count 2 2006.257.16:49:36.27#ibcon#wrote, iclass 15, count 2 2006.257.16:49:36.27#ibcon#about to read 3, iclass 15, count 2 2006.257.16:49:36.30#ibcon#read 3, iclass 15, count 2 2006.257.16:49:36.30#ibcon#about to read 4, iclass 15, count 2 2006.257.16:49:36.30#ibcon#read 4, iclass 15, count 2 2006.257.16:49:36.30#ibcon#about to read 5, iclass 15, count 2 2006.257.16:49:36.30#ibcon#read 5, iclass 15, count 2 2006.257.16:49:36.30#ibcon#about to read 6, iclass 15, count 2 2006.257.16:49:36.30#ibcon#read 6, iclass 15, count 2 2006.257.16:49:36.30#ibcon#end of sib2, iclass 15, count 2 2006.257.16:49:36.30#ibcon#*after write, iclass 15, count 2 2006.257.16:49:36.30#ibcon#*before return 0, iclass 15, count 2 2006.257.16:49:36.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:36.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.16:49:36.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.16:49:36.30#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:36.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:36.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:36.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:36.42#ibcon#enter wrdev, iclass 15, count 0 2006.257.16:49:36.42#ibcon#first serial, iclass 15, count 0 2006.257.16:49:36.42#ibcon#enter sib2, iclass 15, count 0 2006.257.16:49:36.42#ibcon#flushed, iclass 15, count 0 2006.257.16:49:36.42#ibcon#about to write, iclass 15, count 0 2006.257.16:49:36.42#ibcon#wrote, iclass 15, count 0 2006.257.16:49:36.42#ibcon#about to read 3, iclass 15, count 0 2006.257.16:49:36.44#ibcon#read 3, iclass 15, count 0 2006.257.16:49:36.44#ibcon#about to read 4, iclass 15, count 0 2006.257.16:49:36.44#ibcon#read 4, iclass 15, count 0 2006.257.16:49:36.44#ibcon#about to read 5, iclass 15, count 0 2006.257.16:49:36.44#ibcon#read 5, iclass 15, count 0 2006.257.16:49:36.44#ibcon#about to read 6, iclass 15, count 0 2006.257.16:49:36.44#ibcon#read 6, iclass 15, count 0 2006.257.16:49:36.44#ibcon#end of sib2, iclass 15, count 0 2006.257.16:49:36.44#ibcon#*mode == 0, iclass 15, count 0 2006.257.16:49:36.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.16:49:36.44#ibcon#[27=USB\r\n] 2006.257.16:49:36.44#ibcon#*before write, iclass 15, count 0 2006.257.16:49:36.44#ibcon#enter sib2, iclass 15, count 0 2006.257.16:49:36.44#ibcon#flushed, iclass 15, count 0 2006.257.16:49:36.44#ibcon#about to write, iclass 15, count 0 2006.257.16:49:36.44#ibcon#wrote, iclass 15, count 0 2006.257.16:49:36.44#ibcon#about to read 3, iclass 15, count 0 2006.257.16:49:36.47#ibcon#read 3, iclass 15, count 0 2006.257.16:49:36.47#ibcon#about to read 4, iclass 15, count 0 2006.257.16:49:36.47#ibcon#read 4, iclass 15, count 0 2006.257.16:49:36.47#ibcon#about to read 5, iclass 15, count 0 2006.257.16:49:36.47#ibcon#read 5, iclass 15, count 0 2006.257.16:49:36.47#ibcon#about to read 6, iclass 15, count 0 2006.257.16:49:36.47#ibcon#read 6, iclass 15, count 0 2006.257.16:49:36.47#ibcon#end of sib2, iclass 15, count 0 2006.257.16:49:36.47#ibcon#*after write, iclass 15, count 0 2006.257.16:49:36.47#ibcon#*before return 0, iclass 15, count 0 2006.257.16:49:36.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:36.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.16:49:36.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.16:49:36.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.16:49:36.47$vck44/vblo=8,744.99 2006.257.16:49:36.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.16:49:36.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.16:49:36.47#ibcon#ireg 17 cls_cnt 0 2006.257.16:49:36.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:36.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:36.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:36.47#ibcon#enter wrdev, iclass 17, count 0 2006.257.16:49:36.47#ibcon#first serial, iclass 17, count 0 2006.257.16:49:36.47#ibcon#enter sib2, iclass 17, count 0 2006.257.16:49:36.47#ibcon#flushed, iclass 17, count 0 2006.257.16:49:36.47#ibcon#about to write, iclass 17, count 0 2006.257.16:49:36.47#ibcon#wrote, iclass 17, count 0 2006.257.16:49:36.47#ibcon#about to read 3, iclass 17, count 0 2006.257.16:49:36.49#ibcon#read 3, iclass 17, count 0 2006.257.16:49:36.49#ibcon#about to read 4, iclass 17, count 0 2006.257.16:49:36.49#ibcon#read 4, iclass 17, count 0 2006.257.16:49:36.49#ibcon#about to read 5, iclass 17, count 0 2006.257.16:49:36.49#ibcon#read 5, iclass 17, count 0 2006.257.16:49:36.49#ibcon#about to read 6, iclass 17, count 0 2006.257.16:49:36.49#ibcon#read 6, iclass 17, count 0 2006.257.16:49:36.49#ibcon#end of sib2, iclass 17, count 0 2006.257.16:49:36.49#ibcon#*mode == 0, iclass 17, count 0 2006.257.16:49:36.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.16:49:36.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:49:36.49#ibcon#*before write, iclass 17, count 0 2006.257.16:49:36.49#ibcon#enter sib2, iclass 17, count 0 2006.257.16:49:36.49#ibcon#flushed, iclass 17, count 0 2006.257.16:49:36.49#ibcon#about to write, iclass 17, count 0 2006.257.16:49:36.49#ibcon#wrote, iclass 17, count 0 2006.257.16:49:36.49#ibcon#about to read 3, iclass 17, count 0 2006.257.16:49:36.53#ibcon#read 3, iclass 17, count 0 2006.257.16:49:36.53#ibcon#about to read 4, iclass 17, count 0 2006.257.16:49:36.53#ibcon#read 4, iclass 17, count 0 2006.257.16:49:36.53#ibcon#about to read 5, iclass 17, count 0 2006.257.16:49:36.53#ibcon#read 5, iclass 17, count 0 2006.257.16:49:36.53#ibcon#about to read 6, iclass 17, count 0 2006.257.16:49:36.53#ibcon#read 6, iclass 17, count 0 2006.257.16:49:36.53#ibcon#end of sib2, iclass 17, count 0 2006.257.16:49:36.53#ibcon#*after write, iclass 17, count 0 2006.257.16:49:36.53#ibcon#*before return 0, iclass 17, count 0 2006.257.16:49:36.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:36.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.16:49:36.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.16:49:36.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.16:49:36.53$vck44/vb=8,4 2006.257.16:49:36.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.16:49:36.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.16:49:36.53#ibcon#ireg 11 cls_cnt 2 2006.257.16:49:36.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:36.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:36.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:36.59#ibcon#enter wrdev, iclass 19, count 2 2006.257.16:49:36.59#ibcon#first serial, iclass 19, count 2 2006.257.16:49:36.59#ibcon#enter sib2, iclass 19, count 2 2006.257.16:49:36.59#ibcon#flushed, iclass 19, count 2 2006.257.16:49:36.59#ibcon#about to write, iclass 19, count 2 2006.257.16:49:36.59#ibcon#wrote, iclass 19, count 2 2006.257.16:49:36.59#ibcon#about to read 3, iclass 19, count 2 2006.257.16:49:36.61#ibcon#read 3, iclass 19, count 2 2006.257.16:49:36.61#ibcon#about to read 4, iclass 19, count 2 2006.257.16:49:36.61#ibcon#read 4, iclass 19, count 2 2006.257.16:49:36.61#ibcon#about to read 5, iclass 19, count 2 2006.257.16:49:36.61#ibcon#read 5, iclass 19, count 2 2006.257.16:49:36.61#ibcon#about to read 6, iclass 19, count 2 2006.257.16:49:36.61#ibcon#read 6, iclass 19, count 2 2006.257.16:49:36.61#ibcon#end of sib2, iclass 19, count 2 2006.257.16:49:36.61#ibcon#*mode == 0, iclass 19, count 2 2006.257.16:49:36.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.16:49:36.61#ibcon#[27=AT08-04\r\n] 2006.257.16:49:36.61#ibcon#*before write, iclass 19, count 2 2006.257.16:49:36.61#ibcon#enter sib2, iclass 19, count 2 2006.257.16:49:36.61#ibcon#flushed, iclass 19, count 2 2006.257.16:49:36.61#ibcon#about to write, iclass 19, count 2 2006.257.16:49:36.61#ibcon#wrote, iclass 19, count 2 2006.257.16:49:36.61#ibcon#about to read 3, iclass 19, count 2 2006.257.16:49:36.64#ibcon#read 3, iclass 19, count 2 2006.257.16:49:36.64#ibcon#about to read 4, iclass 19, count 2 2006.257.16:49:36.64#ibcon#read 4, iclass 19, count 2 2006.257.16:49:36.64#ibcon#about to read 5, iclass 19, count 2 2006.257.16:49:36.64#ibcon#read 5, iclass 19, count 2 2006.257.16:49:36.64#ibcon#about to read 6, iclass 19, count 2 2006.257.16:49:36.64#ibcon#read 6, iclass 19, count 2 2006.257.16:49:36.64#ibcon#end of sib2, iclass 19, count 2 2006.257.16:49:36.64#ibcon#*after write, iclass 19, count 2 2006.257.16:49:36.64#ibcon#*before return 0, iclass 19, count 2 2006.257.16:49:36.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:36.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.16:49:36.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.16:49:36.64#ibcon#ireg 7 cls_cnt 0 2006.257.16:49:36.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:36.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:36.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:36.76#ibcon#enter wrdev, iclass 19, count 0 2006.257.16:49:36.76#ibcon#first serial, iclass 19, count 0 2006.257.16:49:36.76#ibcon#enter sib2, iclass 19, count 0 2006.257.16:49:36.76#ibcon#flushed, iclass 19, count 0 2006.257.16:49:36.76#ibcon#about to write, iclass 19, count 0 2006.257.16:49:36.76#ibcon#wrote, iclass 19, count 0 2006.257.16:49:36.76#ibcon#about to read 3, iclass 19, count 0 2006.257.16:49:36.78#ibcon#read 3, iclass 19, count 0 2006.257.16:49:36.78#ibcon#about to read 4, iclass 19, count 0 2006.257.16:49:36.78#ibcon#read 4, iclass 19, count 0 2006.257.16:49:36.78#ibcon#about to read 5, iclass 19, count 0 2006.257.16:49:36.78#ibcon#read 5, iclass 19, count 0 2006.257.16:49:36.78#ibcon#about to read 6, iclass 19, count 0 2006.257.16:49:36.78#ibcon#read 6, iclass 19, count 0 2006.257.16:49:36.78#ibcon#end of sib2, iclass 19, count 0 2006.257.16:49:36.78#ibcon#*mode == 0, iclass 19, count 0 2006.257.16:49:36.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.16:49:36.78#ibcon#[27=USB\r\n] 2006.257.16:49:36.78#ibcon#*before write, iclass 19, count 0 2006.257.16:49:36.78#ibcon#enter sib2, iclass 19, count 0 2006.257.16:49:36.78#ibcon#flushed, iclass 19, count 0 2006.257.16:49:36.78#ibcon#about to write, iclass 19, count 0 2006.257.16:49:36.78#ibcon#wrote, iclass 19, count 0 2006.257.16:49:36.78#ibcon#about to read 3, iclass 19, count 0 2006.257.16:49:36.81#ibcon#read 3, iclass 19, count 0 2006.257.16:49:36.81#ibcon#about to read 4, iclass 19, count 0 2006.257.16:49:36.81#ibcon#read 4, iclass 19, count 0 2006.257.16:49:36.81#ibcon#about to read 5, iclass 19, count 0 2006.257.16:49:36.81#ibcon#read 5, iclass 19, count 0 2006.257.16:49:36.81#ibcon#about to read 6, iclass 19, count 0 2006.257.16:49:36.81#ibcon#read 6, iclass 19, count 0 2006.257.16:49:36.81#ibcon#end of sib2, iclass 19, count 0 2006.257.16:49:36.81#ibcon#*after write, iclass 19, count 0 2006.257.16:49:36.81#ibcon#*before return 0, iclass 19, count 0 2006.257.16:49:36.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:36.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.16:49:36.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.16:49:36.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.16:49:36.81$vck44/vabw=wide 2006.257.16:49:36.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.16:49:36.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.16:49:36.81#ibcon#ireg 8 cls_cnt 0 2006.257.16:49:36.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:36.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:36.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:36.81#ibcon#enter wrdev, iclass 21, count 0 2006.257.16:49:36.81#ibcon#first serial, iclass 21, count 0 2006.257.16:49:36.81#ibcon#enter sib2, iclass 21, count 0 2006.257.16:49:36.81#ibcon#flushed, iclass 21, count 0 2006.257.16:49:36.81#ibcon#about to write, iclass 21, count 0 2006.257.16:49:36.81#ibcon#wrote, iclass 21, count 0 2006.257.16:49:36.81#ibcon#about to read 3, iclass 21, count 0 2006.257.16:49:36.83#ibcon#read 3, iclass 21, count 0 2006.257.16:49:36.83#ibcon#about to read 4, iclass 21, count 0 2006.257.16:49:36.83#ibcon#read 4, iclass 21, count 0 2006.257.16:49:36.83#ibcon#about to read 5, iclass 21, count 0 2006.257.16:49:36.83#ibcon#read 5, iclass 21, count 0 2006.257.16:49:36.83#ibcon#about to read 6, iclass 21, count 0 2006.257.16:49:36.83#ibcon#read 6, iclass 21, count 0 2006.257.16:49:36.83#ibcon#end of sib2, iclass 21, count 0 2006.257.16:49:36.83#ibcon#*mode == 0, iclass 21, count 0 2006.257.16:49:36.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.16:49:36.83#ibcon#[25=BW32\r\n] 2006.257.16:49:36.83#ibcon#*before write, iclass 21, count 0 2006.257.16:49:36.83#ibcon#enter sib2, iclass 21, count 0 2006.257.16:49:36.83#ibcon#flushed, iclass 21, count 0 2006.257.16:49:36.83#ibcon#about to write, iclass 21, count 0 2006.257.16:49:36.83#ibcon#wrote, iclass 21, count 0 2006.257.16:49:36.83#ibcon#about to read 3, iclass 21, count 0 2006.257.16:49:36.86#ibcon#read 3, iclass 21, count 0 2006.257.16:49:36.86#ibcon#about to read 4, iclass 21, count 0 2006.257.16:49:36.86#ibcon#read 4, iclass 21, count 0 2006.257.16:49:36.86#ibcon#about to read 5, iclass 21, count 0 2006.257.16:49:36.86#ibcon#read 5, iclass 21, count 0 2006.257.16:49:36.86#ibcon#about to read 6, iclass 21, count 0 2006.257.16:49:36.86#ibcon#read 6, iclass 21, count 0 2006.257.16:49:36.86#ibcon#end of sib2, iclass 21, count 0 2006.257.16:49:36.86#ibcon#*after write, iclass 21, count 0 2006.257.16:49:36.86#ibcon#*before return 0, iclass 21, count 0 2006.257.16:49:36.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:36.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.16:49:36.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.16:49:36.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.16:49:36.86$vck44/vbbw=wide 2006.257.16:49:36.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.16:49:36.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.16:49:36.86#ibcon#ireg 8 cls_cnt 0 2006.257.16:49:36.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:49:36.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:49:36.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:49:36.93#ibcon#enter wrdev, iclass 23, count 0 2006.257.16:49:36.93#ibcon#first serial, iclass 23, count 0 2006.257.16:49:36.93#ibcon#enter sib2, iclass 23, count 0 2006.257.16:49:36.93#ibcon#flushed, iclass 23, count 0 2006.257.16:49:36.93#ibcon#about to write, iclass 23, count 0 2006.257.16:49:36.93#ibcon#wrote, iclass 23, count 0 2006.257.16:49:36.93#ibcon#about to read 3, iclass 23, count 0 2006.257.16:49:36.95#ibcon#read 3, iclass 23, count 0 2006.257.16:49:36.95#ibcon#about to read 4, iclass 23, count 0 2006.257.16:49:36.95#ibcon#read 4, iclass 23, count 0 2006.257.16:49:36.95#ibcon#about to read 5, iclass 23, count 0 2006.257.16:49:36.95#ibcon#read 5, iclass 23, count 0 2006.257.16:49:36.95#ibcon#about to read 6, iclass 23, count 0 2006.257.16:49:36.95#ibcon#read 6, iclass 23, count 0 2006.257.16:49:36.95#ibcon#end of sib2, iclass 23, count 0 2006.257.16:49:36.95#ibcon#*mode == 0, iclass 23, count 0 2006.257.16:49:36.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.16:49:36.95#ibcon#[27=BW32\r\n] 2006.257.16:49:36.95#ibcon#*before write, iclass 23, count 0 2006.257.16:49:36.95#ibcon#enter sib2, iclass 23, count 0 2006.257.16:49:36.95#ibcon#flushed, iclass 23, count 0 2006.257.16:49:36.95#ibcon#about to write, iclass 23, count 0 2006.257.16:49:36.95#ibcon#wrote, iclass 23, count 0 2006.257.16:49:36.95#ibcon#about to read 3, iclass 23, count 0 2006.257.16:49:36.98#ibcon#read 3, iclass 23, count 0 2006.257.16:49:36.98#ibcon#about to read 4, iclass 23, count 0 2006.257.16:49:36.98#ibcon#read 4, iclass 23, count 0 2006.257.16:49:36.98#ibcon#about to read 5, iclass 23, count 0 2006.257.16:49:36.98#ibcon#read 5, iclass 23, count 0 2006.257.16:49:36.98#ibcon#about to read 6, iclass 23, count 0 2006.257.16:49:36.98#ibcon#read 6, iclass 23, count 0 2006.257.16:49:36.98#ibcon#end of sib2, iclass 23, count 0 2006.257.16:49:36.98#ibcon#*after write, iclass 23, count 0 2006.257.16:49:36.98#ibcon#*before return 0, iclass 23, count 0 2006.257.16:49:36.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:49:36.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.16:49:36.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.16:49:36.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.16:49:36.98$setupk4/ifdk4 2006.257.16:49:36.98$ifdk4/lo= 2006.257.16:49:36.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:49:36.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:49:36.98$ifdk4/patch= 2006.257.16:49:36.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:49:36.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:49:36.98$setupk4/!*+20s 2006.257.16:49:40.18#abcon#<5=/14 1.8 4.9 17.33 961014.2\r\n> 2006.257.16:49:40.20#abcon#{5=INTERFACE CLEAR} 2006.257.16:49:40.26#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:49:43.14#trakl#Source acquired 2006.257.16:49:43.14#flagr#flagr/antenna,acquired 2006.257.16:49:50.35#abcon#<5=/14 1.8 4.9 17.33 961014.2\r\n> 2006.257.16:49:50.37#abcon#{5=INTERFACE CLEAR} 2006.257.16:49:50.43#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:49:51.48$setupk4/"tpicd 2006.257.16:49:51.48$setupk4/echo=off 2006.257.16:49:51.48$setupk4/xlog=off 2006.257.16:49:51.48:!2006.257.16:50:58 2006.257.16:50:58.02:preob 2006.257.16:50:59.14/onsource/TRACKING 2006.257.16:50:59.14:!2006.257.16:51:08 2006.257.16:51:08.02:"tape 2006.257.16:51:08.02:"st=record 2006.257.16:51:08.02:data_valid=on 2006.257.16:51:08.02:midob 2006.257.16:51:09.15/onsource/TRACKING 2006.257.16:51:09.15/wx/17.34,1014.2,96 2006.257.16:51:09.23/cable/+6.4850E-03 2006.257.16:51:10.31/va/01,08,usb,yes,30,32 2006.257.16:51:10.32/va/02,07,usb,yes,33,33 2006.257.16:51:10.32/va/03,08,usb,yes,29,31 2006.257.16:51:10.32/va/04,07,usb,yes,34,35 2006.257.16:51:10.32/va/05,04,usb,yes,30,31 2006.257.16:51:10.32/va/06,04,usb,yes,34,33 2006.257.16:51:10.32/va/07,04,usb,yes,34,35 2006.257.16:51:10.32/va/08,04,usb,yes,29,35 2006.257.16:51:10.55/valo/01,524.99,yes,locked 2006.257.16:51:10.55/valo/02,534.99,yes,locked 2006.257.16:51:10.55/valo/03,564.99,yes,locked 2006.257.16:51:10.55/valo/04,624.99,yes,locked 2006.257.16:51:10.55/valo/05,734.99,yes,locked 2006.257.16:51:10.55/valo/06,814.99,yes,locked 2006.257.16:51:10.55/valo/07,864.99,yes,locked 2006.257.16:51:10.55/valo/08,884.99,yes,locked 2006.257.16:51:11.63/vb/01,04,usb,yes,30,28 2006.257.16:51:11.63/vb/02,05,usb,yes,28,28 2006.257.16:51:11.64/vb/03,04,usb,yes,29,32 2006.257.16:51:11.64/vb/04,05,usb,yes,30,28 2006.257.16:51:11.64/vb/05,04,usb,yes,26,28 2006.257.16:51:11.64/vb/06,04,usb,yes,31,27 2006.257.16:51:11.64/vb/07,04,usb,yes,30,30 2006.257.16:51:11.64/vb/08,04,usb,yes,28,31 2006.257.16:51:11.87/vblo/01,629.99,yes,locked 2006.257.16:51:11.87/vblo/02,634.99,yes,locked 2006.257.16:51:11.88/vblo/03,649.99,yes,locked 2006.257.16:51:11.88/vblo/04,679.99,yes,locked 2006.257.16:51:11.88/vblo/05,709.99,yes,locked 2006.257.16:51:11.88/vblo/06,719.99,yes,locked 2006.257.16:51:11.88/vblo/07,734.99,yes,locked 2006.257.16:51:11.88/vblo/08,744.99,yes,locked 2006.257.16:51:12.02/vabw/8 2006.257.16:51:12.17/vbbw/8 2006.257.16:51:12.26/xfe/off,on,15.2 2006.257.16:51:12.63/ifatt/23,28,28,28 2006.257.16:51:13.07/fmout-gps/S +4.60E-07 2006.257.16:51:13.11:!2006.257.16:53:58 2006.257.16:53:58.01:data_valid=off 2006.257.16:53:58.02:"et 2006.257.16:53:58.02:!+3s 2006.257.16:54:01.04:"tape 2006.257.16:54:01.04:postob 2006.257.16:54:01.11/cable/+6.4840E-03 2006.257.16:54:01.11/wx/17.34,1014.2,96 2006.257.16:54:01.17/fmout-gps/S +4.59E-07 2006.257.16:54:01.17:scan_name=257-1700,jd0609,50 2006.257.16:54:01.18:source=0552+398,055530.81,394849.2,2000.0,cw 2006.257.16:54:03.13#flagr#flagr/antenna,new-source 2006.257.16:54:03.14:checkk5 2006.257.16:54:03.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.16:54:03.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.16:54:04.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.16:54:04.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.16:54:04.84/chk_obsdata//k5ts1/T2571651??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.16:54:05.18/chk_obsdata//k5ts2/T2571651??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.16:54:05.51/chk_obsdata//k5ts3/T2571651??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.16:54:05.84/chk_obsdata//k5ts4/T2571651??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.16:54:06.49/k5log//k5ts1_log_newline 2006.257.16:54:07.16/k5log//k5ts2_log_newline 2006.257.16:54:07.81/k5log//k5ts3_log_newline 2006.257.16:54:08.46/k5log//k5ts4_log_newline 2006.257.16:54:08.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.16:54:08.48:setupk4=1 2006.257.16:54:08.48$setupk4/echo=on 2006.257.16:54:08.48$setupk4/pcalon 2006.257.16:54:08.48$pcalon/"no phase cal control is implemented here 2006.257.16:54:08.48$setupk4/"tpicd=stop 2006.257.16:54:08.48$setupk4/"rec=synch_on 2006.257.16:54:08.48$setupk4/"rec_mode=128 2006.257.16:54:08.48$setupk4/!* 2006.257.16:54:08.48$setupk4/recpk4 2006.257.16:54:08.49$recpk4/recpatch= 2006.257.16:54:08.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.16:54:08.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.16:54:08.49$setupk4/vck44 2006.257.16:54:08.49$vck44/valo=1,524.99 2006.257.16:54:08.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.16:54:08.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.16:54:08.49#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:08.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:08.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:08.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:08.49#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:54:08.49#ibcon#first serial, iclass 28, count 0 2006.257.16:54:08.49#ibcon#enter sib2, iclass 28, count 0 2006.257.16:54:08.49#ibcon#flushed, iclass 28, count 0 2006.257.16:54:08.49#ibcon#about to write, iclass 28, count 0 2006.257.16:54:08.49#ibcon#wrote, iclass 28, count 0 2006.257.16:54:08.49#ibcon#about to read 3, iclass 28, count 0 2006.257.16:54:08.50#ibcon#read 3, iclass 28, count 0 2006.257.16:54:08.50#ibcon#about to read 4, iclass 28, count 0 2006.257.16:54:08.50#ibcon#read 4, iclass 28, count 0 2006.257.16:54:08.50#ibcon#about to read 5, iclass 28, count 0 2006.257.16:54:08.50#ibcon#read 5, iclass 28, count 0 2006.257.16:54:08.50#ibcon#about to read 6, iclass 28, count 0 2006.257.16:54:08.50#ibcon#read 6, iclass 28, count 0 2006.257.16:54:08.50#ibcon#end of sib2, iclass 28, count 0 2006.257.16:54:08.50#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:54:08.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:54:08.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.16:54:08.50#ibcon#*before write, iclass 28, count 0 2006.257.16:54:08.50#ibcon#enter sib2, iclass 28, count 0 2006.257.16:54:08.50#ibcon#flushed, iclass 28, count 0 2006.257.16:54:08.50#ibcon#about to write, iclass 28, count 0 2006.257.16:54:08.50#ibcon#wrote, iclass 28, count 0 2006.257.16:54:08.50#ibcon#about to read 3, iclass 28, count 0 2006.257.16:54:08.55#ibcon#read 3, iclass 28, count 0 2006.257.16:54:08.55#ibcon#about to read 4, iclass 28, count 0 2006.257.16:54:08.55#ibcon#read 4, iclass 28, count 0 2006.257.16:54:08.55#ibcon#about to read 5, iclass 28, count 0 2006.257.16:54:08.55#ibcon#read 5, iclass 28, count 0 2006.257.16:54:08.55#ibcon#about to read 6, iclass 28, count 0 2006.257.16:54:08.55#ibcon#read 6, iclass 28, count 0 2006.257.16:54:08.55#ibcon#end of sib2, iclass 28, count 0 2006.257.16:54:08.55#ibcon#*after write, iclass 28, count 0 2006.257.16:54:08.55#ibcon#*before return 0, iclass 28, count 0 2006.257.16:54:08.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:08.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:08.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:54:08.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:54:08.55$vck44/va=1,8 2006.257.16:54:08.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.16:54:08.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.16:54:08.56#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:08.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:08.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:08.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:08.56#ibcon#enter wrdev, iclass 30, count 2 2006.257.16:54:08.56#ibcon#first serial, iclass 30, count 2 2006.257.16:54:08.56#ibcon#enter sib2, iclass 30, count 2 2006.257.16:54:08.56#ibcon#flushed, iclass 30, count 2 2006.257.16:54:08.56#ibcon#about to write, iclass 30, count 2 2006.257.16:54:08.56#ibcon#wrote, iclass 30, count 2 2006.257.16:54:08.56#ibcon#about to read 3, iclass 30, count 2 2006.257.16:54:08.57#ibcon#read 3, iclass 30, count 2 2006.257.16:54:08.57#ibcon#about to read 4, iclass 30, count 2 2006.257.16:54:08.57#ibcon#read 4, iclass 30, count 2 2006.257.16:54:08.57#ibcon#about to read 5, iclass 30, count 2 2006.257.16:54:08.57#ibcon#read 5, iclass 30, count 2 2006.257.16:54:08.57#ibcon#about to read 6, iclass 30, count 2 2006.257.16:54:08.57#ibcon#read 6, iclass 30, count 2 2006.257.16:54:08.57#ibcon#end of sib2, iclass 30, count 2 2006.257.16:54:08.57#ibcon#*mode == 0, iclass 30, count 2 2006.257.16:54:08.57#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.16:54:08.57#ibcon#[25=AT01-08\r\n] 2006.257.16:54:08.57#ibcon#*before write, iclass 30, count 2 2006.257.16:54:08.57#ibcon#enter sib2, iclass 30, count 2 2006.257.16:54:08.57#ibcon#flushed, iclass 30, count 2 2006.257.16:54:08.57#ibcon#about to write, iclass 30, count 2 2006.257.16:54:08.57#ibcon#wrote, iclass 30, count 2 2006.257.16:54:08.57#ibcon#about to read 3, iclass 30, count 2 2006.257.16:54:08.60#ibcon#read 3, iclass 30, count 2 2006.257.16:54:08.60#ibcon#about to read 4, iclass 30, count 2 2006.257.16:54:08.60#ibcon#read 4, iclass 30, count 2 2006.257.16:54:08.60#ibcon#about to read 5, iclass 30, count 2 2006.257.16:54:08.60#ibcon#read 5, iclass 30, count 2 2006.257.16:54:08.60#ibcon#about to read 6, iclass 30, count 2 2006.257.16:54:08.60#ibcon#read 6, iclass 30, count 2 2006.257.16:54:08.60#ibcon#end of sib2, iclass 30, count 2 2006.257.16:54:08.60#ibcon#*after write, iclass 30, count 2 2006.257.16:54:08.60#ibcon#*before return 0, iclass 30, count 2 2006.257.16:54:08.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:08.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:08.60#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.16:54:08.60#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:08.60#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:08.72#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:08.72#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:08.72#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:54:08.72#ibcon#first serial, iclass 30, count 0 2006.257.16:54:08.72#ibcon#enter sib2, iclass 30, count 0 2006.257.16:54:08.72#ibcon#flushed, iclass 30, count 0 2006.257.16:54:08.72#ibcon#about to write, iclass 30, count 0 2006.257.16:54:08.72#ibcon#wrote, iclass 30, count 0 2006.257.16:54:08.72#ibcon#about to read 3, iclass 30, count 0 2006.257.16:54:08.74#ibcon#read 3, iclass 30, count 0 2006.257.16:54:08.74#ibcon#about to read 4, iclass 30, count 0 2006.257.16:54:08.74#ibcon#read 4, iclass 30, count 0 2006.257.16:54:08.74#ibcon#about to read 5, iclass 30, count 0 2006.257.16:54:08.74#ibcon#read 5, iclass 30, count 0 2006.257.16:54:08.74#ibcon#about to read 6, iclass 30, count 0 2006.257.16:54:08.74#ibcon#read 6, iclass 30, count 0 2006.257.16:54:08.74#ibcon#end of sib2, iclass 30, count 0 2006.257.16:54:08.74#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:54:08.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:54:08.74#ibcon#[25=USB\r\n] 2006.257.16:54:08.74#ibcon#*before write, iclass 30, count 0 2006.257.16:54:08.74#ibcon#enter sib2, iclass 30, count 0 2006.257.16:54:08.74#ibcon#flushed, iclass 30, count 0 2006.257.16:54:08.74#ibcon#about to write, iclass 30, count 0 2006.257.16:54:08.74#ibcon#wrote, iclass 30, count 0 2006.257.16:54:08.74#ibcon#about to read 3, iclass 30, count 0 2006.257.16:54:08.77#ibcon#read 3, iclass 30, count 0 2006.257.16:54:08.77#ibcon#about to read 4, iclass 30, count 0 2006.257.16:54:08.77#ibcon#read 4, iclass 30, count 0 2006.257.16:54:08.77#ibcon#about to read 5, iclass 30, count 0 2006.257.16:54:08.77#ibcon#read 5, iclass 30, count 0 2006.257.16:54:08.77#ibcon#about to read 6, iclass 30, count 0 2006.257.16:54:08.77#ibcon#read 6, iclass 30, count 0 2006.257.16:54:08.77#ibcon#end of sib2, iclass 30, count 0 2006.257.16:54:08.77#ibcon#*after write, iclass 30, count 0 2006.257.16:54:08.77#ibcon#*before return 0, iclass 30, count 0 2006.257.16:54:08.77#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:08.77#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:08.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:54:08.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:54:08.77$vck44/valo=2,534.99 2006.257.16:54:08.78#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.16:54:08.78#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.16:54:08.78#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:08.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:08.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:08.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:08.78#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:54:08.78#ibcon#first serial, iclass 32, count 0 2006.257.16:54:08.78#ibcon#enter sib2, iclass 32, count 0 2006.257.16:54:08.78#ibcon#flushed, iclass 32, count 0 2006.257.16:54:08.78#ibcon#about to write, iclass 32, count 0 2006.257.16:54:08.78#ibcon#wrote, iclass 32, count 0 2006.257.16:54:08.78#ibcon#about to read 3, iclass 32, count 0 2006.257.16:54:08.79#ibcon#read 3, iclass 32, count 0 2006.257.16:54:08.79#ibcon#about to read 4, iclass 32, count 0 2006.257.16:54:08.79#ibcon#read 4, iclass 32, count 0 2006.257.16:54:08.79#ibcon#about to read 5, iclass 32, count 0 2006.257.16:54:08.79#ibcon#read 5, iclass 32, count 0 2006.257.16:54:08.79#ibcon#about to read 6, iclass 32, count 0 2006.257.16:54:08.79#ibcon#read 6, iclass 32, count 0 2006.257.16:54:08.79#ibcon#end of sib2, iclass 32, count 0 2006.257.16:54:08.79#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:54:08.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:54:08.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.16:54:08.79#ibcon#*before write, iclass 32, count 0 2006.257.16:54:08.79#ibcon#enter sib2, iclass 32, count 0 2006.257.16:54:08.79#ibcon#flushed, iclass 32, count 0 2006.257.16:54:08.79#ibcon#about to write, iclass 32, count 0 2006.257.16:54:08.79#ibcon#wrote, iclass 32, count 0 2006.257.16:54:08.79#ibcon#about to read 3, iclass 32, count 0 2006.257.16:54:08.83#ibcon#read 3, iclass 32, count 0 2006.257.16:54:08.83#ibcon#about to read 4, iclass 32, count 0 2006.257.16:54:08.83#ibcon#read 4, iclass 32, count 0 2006.257.16:54:08.83#ibcon#about to read 5, iclass 32, count 0 2006.257.16:54:08.83#ibcon#read 5, iclass 32, count 0 2006.257.16:54:08.83#ibcon#about to read 6, iclass 32, count 0 2006.257.16:54:08.83#ibcon#read 6, iclass 32, count 0 2006.257.16:54:08.83#ibcon#end of sib2, iclass 32, count 0 2006.257.16:54:08.83#ibcon#*after write, iclass 32, count 0 2006.257.16:54:08.83#ibcon#*before return 0, iclass 32, count 0 2006.257.16:54:08.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:08.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:08.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:54:08.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:54:08.83$vck44/va=2,7 2006.257.16:54:08.84#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.16:54:08.84#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.16:54:08.84#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:08.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:08.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:08.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:08.88#ibcon#enter wrdev, iclass 34, count 2 2006.257.16:54:08.88#ibcon#first serial, iclass 34, count 2 2006.257.16:54:08.88#ibcon#enter sib2, iclass 34, count 2 2006.257.16:54:08.88#ibcon#flushed, iclass 34, count 2 2006.257.16:54:08.88#ibcon#about to write, iclass 34, count 2 2006.257.16:54:08.88#ibcon#wrote, iclass 34, count 2 2006.257.16:54:08.88#ibcon#about to read 3, iclass 34, count 2 2006.257.16:54:08.90#ibcon#read 3, iclass 34, count 2 2006.257.16:54:08.90#ibcon#about to read 4, iclass 34, count 2 2006.257.16:54:08.90#ibcon#read 4, iclass 34, count 2 2006.257.16:54:08.90#ibcon#about to read 5, iclass 34, count 2 2006.257.16:54:08.90#ibcon#read 5, iclass 34, count 2 2006.257.16:54:08.90#ibcon#about to read 6, iclass 34, count 2 2006.257.16:54:08.90#ibcon#read 6, iclass 34, count 2 2006.257.16:54:08.90#ibcon#end of sib2, iclass 34, count 2 2006.257.16:54:08.90#ibcon#*mode == 0, iclass 34, count 2 2006.257.16:54:08.90#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.16:54:08.90#ibcon#[25=AT02-07\r\n] 2006.257.16:54:08.90#ibcon#*before write, iclass 34, count 2 2006.257.16:54:08.90#ibcon#enter sib2, iclass 34, count 2 2006.257.16:54:08.90#ibcon#flushed, iclass 34, count 2 2006.257.16:54:08.90#ibcon#about to write, iclass 34, count 2 2006.257.16:54:08.90#ibcon#wrote, iclass 34, count 2 2006.257.16:54:08.90#ibcon#about to read 3, iclass 34, count 2 2006.257.16:54:08.93#ibcon#read 3, iclass 34, count 2 2006.257.16:54:08.93#ibcon#about to read 4, iclass 34, count 2 2006.257.16:54:08.93#ibcon#read 4, iclass 34, count 2 2006.257.16:54:08.93#ibcon#about to read 5, iclass 34, count 2 2006.257.16:54:08.93#ibcon#read 5, iclass 34, count 2 2006.257.16:54:08.93#ibcon#about to read 6, iclass 34, count 2 2006.257.16:54:08.93#ibcon#read 6, iclass 34, count 2 2006.257.16:54:08.93#ibcon#end of sib2, iclass 34, count 2 2006.257.16:54:08.93#ibcon#*after write, iclass 34, count 2 2006.257.16:54:08.93#ibcon#*before return 0, iclass 34, count 2 2006.257.16:54:08.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:08.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:08.93#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.16:54:08.93#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:08.93#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:09.05#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:09.05#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:09.05#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:54:09.05#ibcon#first serial, iclass 34, count 0 2006.257.16:54:09.05#ibcon#enter sib2, iclass 34, count 0 2006.257.16:54:09.05#ibcon#flushed, iclass 34, count 0 2006.257.16:54:09.05#ibcon#about to write, iclass 34, count 0 2006.257.16:54:09.05#ibcon#wrote, iclass 34, count 0 2006.257.16:54:09.05#ibcon#about to read 3, iclass 34, count 0 2006.257.16:54:09.07#ibcon#read 3, iclass 34, count 0 2006.257.16:54:09.07#ibcon#about to read 4, iclass 34, count 0 2006.257.16:54:09.07#ibcon#read 4, iclass 34, count 0 2006.257.16:54:09.07#ibcon#about to read 5, iclass 34, count 0 2006.257.16:54:09.07#ibcon#read 5, iclass 34, count 0 2006.257.16:54:09.07#ibcon#about to read 6, iclass 34, count 0 2006.257.16:54:09.07#ibcon#read 6, iclass 34, count 0 2006.257.16:54:09.07#ibcon#end of sib2, iclass 34, count 0 2006.257.16:54:09.07#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:54:09.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:54:09.07#ibcon#[25=USB\r\n] 2006.257.16:54:09.07#ibcon#*before write, iclass 34, count 0 2006.257.16:54:09.07#ibcon#enter sib2, iclass 34, count 0 2006.257.16:54:09.07#ibcon#flushed, iclass 34, count 0 2006.257.16:54:09.07#ibcon#about to write, iclass 34, count 0 2006.257.16:54:09.07#ibcon#wrote, iclass 34, count 0 2006.257.16:54:09.07#ibcon#about to read 3, iclass 34, count 0 2006.257.16:54:09.10#ibcon#read 3, iclass 34, count 0 2006.257.16:54:09.10#ibcon#about to read 4, iclass 34, count 0 2006.257.16:54:09.10#ibcon#read 4, iclass 34, count 0 2006.257.16:54:09.10#ibcon#about to read 5, iclass 34, count 0 2006.257.16:54:09.10#ibcon#read 5, iclass 34, count 0 2006.257.16:54:09.10#ibcon#about to read 6, iclass 34, count 0 2006.257.16:54:09.10#ibcon#read 6, iclass 34, count 0 2006.257.16:54:09.10#ibcon#end of sib2, iclass 34, count 0 2006.257.16:54:09.10#ibcon#*after write, iclass 34, count 0 2006.257.16:54:09.10#ibcon#*before return 0, iclass 34, count 0 2006.257.16:54:09.10#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:09.10#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:09.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:54:09.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:54:09.10$vck44/valo=3,564.99 2006.257.16:54:09.11#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.16:54:09.11#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.16:54:09.11#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:09.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:09.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:09.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:09.11#ibcon#enter wrdev, iclass 36, count 0 2006.257.16:54:09.11#ibcon#first serial, iclass 36, count 0 2006.257.16:54:09.11#ibcon#enter sib2, iclass 36, count 0 2006.257.16:54:09.11#ibcon#flushed, iclass 36, count 0 2006.257.16:54:09.11#ibcon#about to write, iclass 36, count 0 2006.257.16:54:09.11#ibcon#wrote, iclass 36, count 0 2006.257.16:54:09.11#ibcon#about to read 3, iclass 36, count 0 2006.257.16:54:09.12#ibcon#read 3, iclass 36, count 0 2006.257.16:54:09.12#ibcon#about to read 4, iclass 36, count 0 2006.257.16:54:09.12#ibcon#read 4, iclass 36, count 0 2006.257.16:54:09.12#ibcon#about to read 5, iclass 36, count 0 2006.257.16:54:09.12#ibcon#read 5, iclass 36, count 0 2006.257.16:54:09.12#ibcon#about to read 6, iclass 36, count 0 2006.257.16:54:09.12#ibcon#read 6, iclass 36, count 0 2006.257.16:54:09.12#ibcon#end of sib2, iclass 36, count 0 2006.257.16:54:09.12#ibcon#*mode == 0, iclass 36, count 0 2006.257.16:54:09.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.16:54:09.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.16:54:09.12#ibcon#*before write, iclass 36, count 0 2006.257.16:54:09.12#ibcon#enter sib2, iclass 36, count 0 2006.257.16:54:09.12#ibcon#flushed, iclass 36, count 0 2006.257.16:54:09.12#ibcon#about to write, iclass 36, count 0 2006.257.16:54:09.12#ibcon#wrote, iclass 36, count 0 2006.257.16:54:09.12#ibcon#about to read 3, iclass 36, count 0 2006.257.16:54:09.16#ibcon#read 3, iclass 36, count 0 2006.257.16:54:09.16#ibcon#about to read 4, iclass 36, count 0 2006.257.16:54:09.16#ibcon#read 4, iclass 36, count 0 2006.257.16:54:09.16#ibcon#about to read 5, iclass 36, count 0 2006.257.16:54:09.16#ibcon#read 5, iclass 36, count 0 2006.257.16:54:09.16#ibcon#about to read 6, iclass 36, count 0 2006.257.16:54:09.16#ibcon#read 6, iclass 36, count 0 2006.257.16:54:09.16#ibcon#end of sib2, iclass 36, count 0 2006.257.16:54:09.16#ibcon#*after write, iclass 36, count 0 2006.257.16:54:09.16#ibcon#*before return 0, iclass 36, count 0 2006.257.16:54:09.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:09.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:09.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.16:54:09.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.16:54:09.16$vck44/va=3,8 2006.257.16:54:09.17#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.16:54:09.17#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.16:54:09.17#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:09.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:09.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:09.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:09.21#ibcon#enter wrdev, iclass 38, count 2 2006.257.16:54:09.21#ibcon#first serial, iclass 38, count 2 2006.257.16:54:09.21#ibcon#enter sib2, iclass 38, count 2 2006.257.16:54:09.21#ibcon#flushed, iclass 38, count 2 2006.257.16:54:09.21#ibcon#about to write, iclass 38, count 2 2006.257.16:54:09.21#ibcon#wrote, iclass 38, count 2 2006.257.16:54:09.21#ibcon#about to read 3, iclass 38, count 2 2006.257.16:54:09.23#ibcon#read 3, iclass 38, count 2 2006.257.16:54:09.23#ibcon#about to read 4, iclass 38, count 2 2006.257.16:54:09.23#ibcon#read 4, iclass 38, count 2 2006.257.16:54:09.23#ibcon#about to read 5, iclass 38, count 2 2006.257.16:54:09.23#ibcon#read 5, iclass 38, count 2 2006.257.16:54:09.23#ibcon#about to read 6, iclass 38, count 2 2006.257.16:54:09.23#ibcon#read 6, iclass 38, count 2 2006.257.16:54:09.23#ibcon#end of sib2, iclass 38, count 2 2006.257.16:54:09.23#ibcon#*mode == 0, iclass 38, count 2 2006.257.16:54:09.23#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.16:54:09.23#ibcon#[25=AT03-08\r\n] 2006.257.16:54:09.23#ibcon#*before write, iclass 38, count 2 2006.257.16:54:09.23#ibcon#enter sib2, iclass 38, count 2 2006.257.16:54:09.23#ibcon#flushed, iclass 38, count 2 2006.257.16:54:09.23#ibcon#about to write, iclass 38, count 2 2006.257.16:54:09.23#ibcon#wrote, iclass 38, count 2 2006.257.16:54:09.23#ibcon#about to read 3, iclass 38, count 2 2006.257.16:54:09.26#ibcon#read 3, iclass 38, count 2 2006.257.16:54:09.26#ibcon#about to read 4, iclass 38, count 2 2006.257.16:54:09.26#ibcon#read 4, iclass 38, count 2 2006.257.16:54:09.26#ibcon#about to read 5, iclass 38, count 2 2006.257.16:54:09.26#ibcon#read 5, iclass 38, count 2 2006.257.16:54:09.26#ibcon#about to read 6, iclass 38, count 2 2006.257.16:54:09.26#ibcon#read 6, iclass 38, count 2 2006.257.16:54:09.26#ibcon#end of sib2, iclass 38, count 2 2006.257.16:54:09.26#ibcon#*after write, iclass 38, count 2 2006.257.16:54:09.26#ibcon#*before return 0, iclass 38, count 2 2006.257.16:54:09.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:09.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:09.26#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.16:54:09.26#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:09.26#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:09.38#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:09.38#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:09.38#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:54:09.38#ibcon#first serial, iclass 38, count 0 2006.257.16:54:09.38#ibcon#enter sib2, iclass 38, count 0 2006.257.16:54:09.38#ibcon#flushed, iclass 38, count 0 2006.257.16:54:09.38#ibcon#about to write, iclass 38, count 0 2006.257.16:54:09.38#ibcon#wrote, iclass 38, count 0 2006.257.16:54:09.38#ibcon#about to read 3, iclass 38, count 0 2006.257.16:54:09.40#ibcon#read 3, iclass 38, count 0 2006.257.16:54:09.40#ibcon#about to read 4, iclass 38, count 0 2006.257.16:54:09.40#ibcon#read 4, iclass 38, count 0 2006.257.16:54:09.40#ibcon#about to read 5, iclass 38, count 0 2006.257.16:54:09.40#ibcon#read 5, iclass 38, count 0 2006.257.16:54:09.40#ibcon#about to read 6, iclass 38, count 0 2006.257.16:54:09.40#ibcon#read 6, iclass 38, count 0 2006.257.16:54:09.40#ibcon#end of sib2, iclass 38, count 0 2006.257.16:54:09.40#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:54:09.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:54:09.40#ibcon#[25=USB\r\n] 2006.257.16:54:09.40#ibcon#*before write, iclass 38, count 0 2006.257.16:54:09.40#ibcon#enter sib2, iclass 38, count 0 2006.257.16:54:09.40#ibcon#flushed, iclass 38, count 0 2006.257.16:54:09.40#ibcon#about to write, iclass 38, count 0 2006.257.16:54:09.40#ibcon#wrote, iclass 38, count 0 2006.257.16:54:09.40#ibcon#about to read 3, iclass 38, count 0 2006.257.16:54:09.43#ibcon#read 3, iclass 38, count 0 2006.257.16:54:09.43#ibcon#about to read 4, iclass 38, count 0 2006.257.16:54:09.43#ibcon#read 4, iclass 38, count 0 2006.257.16:54:09.43#ibcon#about to read 5, iclass 38, count 0 2006.257.16:54:09.43#ibcon#read 5, iclass 38, count 0 2006.257.16:54:09.43#ibcon#about to read 6, iclass 38, count 0 2006.257.16:54:09.43#ibcon#read 6, iclass 38, count 0 2006.257.16:54:09.43#ibcon#end of sib2, iclass 38, count 0 2006.257.16:54:09.43#ibcon#*after write, iclass 38, count 0 2006.257.16:54:09.43#ibcon#*before return 0, iclass 38, count 0 2006.257.16:54:09.43#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:09.43#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:09.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:54:09.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:54:09.43$vck44/valo=4,624.99 2006.257.16:54:09.44#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.16:54:09.44#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.16:54:09.44#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:09.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:09.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:09.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:09.44#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:54:09.44#ibcon#first serial, iclass 40, count 0 2006.257.16:54:09.44#ibcon#enter sib2, iclass 40, count 0 2006.257.16:54:09.44#ibcon#flushed, iclass 40, count 0 2006.257.16:54:09.44#ibcon#about to write, iclass 40, count 0 2006.257.16:54:09.44#ibcon#wrote, iclass 40, count 0 2006.257.16:54:09.44#ibcon#about to read 3, iclass 40, count 0 2006.257.16:54:09.45#ibcon#read 3, iclass 40, count 0 2006.257.16:54:09.45#ibcon#about to read 4, iclass 40, count 0 2006.257.16:54:09.45#ibcon#read 4, iclass 40, count 0 2006.257.16:54:09.45#ibcon#about to read 5, iclass 40, count 0 2006.257.16:54:09.45#ibcon#read 5, iclass 40, count 0 2006.257.16:54:09.45#ibcon#about to read 6, iclass 40, count 0 2006.257.16:54:09.45#ibcon#read 6, iclass 40, count 0 2006.257.16:54:09.45#ibcon#end of sib2, iclass 40, count 0 2006.257.16:54:09.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:54:09.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:54:09.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.16:54:09.45#ibcon#*before write, iclass 40, count 0 2006.257.16:54:09.45#ibcon#enter sib2, iclass 40, count 0 2006.257.16:54:09.45#ibcon#flushed, iclass 40, count 0 2006.257.16:54:09.45#ibcon#about to write, iclass 40, count 0 2006.257.16:54:09.45#ibcon#wrote, iclass 40, count 0 2006.257.16:54:09.45#ibcon#about to read 3, iclass 40, count 0 2006.257.16:54:09.49#ibcon#read 3, iclass 40, count 0 2006.257.16:54:09.49#ibcon#about to read 4, iclass 40, count 0 2006.257.16:54:09.49#ibcon#read 4, iclass 40, count 0 2006.257.16:54:09.49#ibcon#about to read 5, iclass 40, count 0 2006.257.16:54:09.49#ibcon#read 5, iclass 40, count 0 2006.257.16:54:09.49#ibcon#about to read 6, iclass 40, count 0 2006.257.16:54:09.49#ibcon#read 6, iclass 40, count 0 2006.257.16:54:09.49#ibcon#end of sib2, iclass 40, count 0 2006.257.16:54:09.49#ibcon#*after write, iclass 40, count 0 2006.257.16:54:09.49#ibcon#*before return 0, iclass 40, count 0 2006.257.16:54:09.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:09.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:09.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:54:09.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:54:09.49$vck44/va=4,7 2006.257.16:54:09.50#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.16:54:09.50#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.16:54:09.50#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:09.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:09.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:09.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:09.54#ibcon#enter wrdev, iclass 4, count 2 2006.257.16:54:09.54#ibcon#first serial, iclass 4, count 2 2006.257.16:54:09.54#ibcon#enter sib2, iclass 4, count 2 2006.257.16:54:09.54#ibcon#flushed, iclass 4, count 2 2006.257.16:54:09.54#ibcon#about to write, iclass 4, count 2 2006.257.16:54:09.54#ibcon#wrote, iclass 4, count 2 2006.257.16:54:09.54#ibcon#about to read 3, iclass 4, count 2 2006.257.16:54:09.56#ibcon#read 3, iclass 4, count 2 2006.257.16:54:09.56#ibcon#about to read 4, iclass 4, count 2 2006.257.16:54:09.56#ibcon#read 4, iclass 4, count 2 2006.257.16:54:09.56#ibcon#about to read 5, iclass 4, count 2 2006.257.16:54:09.56#ibcon#read 5, iclass 4, count 2 2006.257.16:54:09.56#ibcon#about to read 6, iclass 4, count 2 2006.257.16:54:09.56#ibcon#read 6, iclass 4, count 2 2006.257.16:54:09.56#ibcon#end of sib2, iclass 4, count 2 2006.257.16:54:09.56#ibcon#*mode == 0, iclass 4, count 2 2006.257.16:54:09.56#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.16:54:09.56#ibcon#[25=AT04-07\r\n] 2006.257.16:54:09.56#ibcon#*before write, iclass 4, count 2 2006.257.16:54:09.56#ibcon#enter sib2, iclass 4, count 2 2006.257.16:54:09.56#ibcon#flushed, iclass 4, count 2 2006.257.16:54:09.56#ibcon#about to write, iclass 4, count 2 2006.257.16:54:09.56#ibcon#wrote, iclass 4, count 2 2006.257.16:54:09.56#ibcon#about to read 3, iclass 4, count 2 2006.257.16:54:09.59#ibcon#read 3, iclass 4, count 2 2006.257.16:54:09.59#ibcon#about to read 4, iclass 4, count 2 2006.257.16:54:09.59#ibcon#read 4, iclass 4, count 2 2006.257.16:54:09.59#ibcon#about to read 5, iclass 4, count 2 2006.257.16:54:09.59#ibcon#read 5, iclass 4, count 2 2006.257.16:54:09.59#ibcon#about to read 6, iclass 4, count 2 2006.257.16:54:09.59#ibcon#read 6, iclass 4, count 2 2006.257.16:54:09.59#ibcon#end of sib2, iclass 4, count 2 2006.257.16:54:09.59#ibcon#*after write, iclass 4, count 2 2006.257.16:54:09.59#ibcon#*before return 0, iclass 4, count 2 2006.257.16:54:09.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:09.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:09.59#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.16:54:09.59#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:09.59#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:09.71#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:09.71#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:09.71#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:54:09.71#ibcon#first serial, iclass 4, count 0 2006.257.16:54:09.71#ibcon#enter sib2, iclass 4, count 0 2006.257.16:54:09.71#ibcon#flushed, iclass 4, count 0 2006.257.16:54:09.71#ibcon#about to write, iclass 4, count 0 2006.257.16:54:09.71#ibcon#wrote, iclass 4, count 0 2006.257.16:54:09.71#ibcon#about to read 3, iclass 4, count 0 2006.257.16:54:09.73#ibcon#read 3, iclass 4, count 0 2006.257.16:54:09.73#ibcon#about to read 4, iclass 4, count 0 2006.257.16:54:09.73#ibcon#read 4, iclass 4, count 0 2006.257.16:54:09.73#ibcon#about to read 5, iclass 4, count 0 2006.257.16:54:09.73#ibcon#read 5, iclass 4, count 0 2006.257.16:54:09.73#ibcon#about to read 6, iclass 4, count 0 2006.257.16:54:09.73#ibcon#read 6, iclass 4, count 0 2006.257.16:54:09.73#ibcon#end of sib2, iclass 4, count 0 2006.257.16:54:09.73#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:54:09.73#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:54:09.73#ibcon#[25=USB\r\n] 2006.257.16:54:09.73#ibcon#*before write, iclass 4, count 0 2006.257.16:54:09.73#ibcon#enter sib2, iclass 4, count 0 2006.257.16:54:09.73#ibcon#flushed, iclass 4, count 0 2006.257.16:54:09.73#ibcon#about to write, iclass 4, count 0 2006.257.16:54:09.73#ibcon#wrote, iclass 4, count 0 2006.257.16:54:09.73#ibcon#about to read 3, iclass 4, count 0 2006.257.16:54:09.76#ibcon#read 3, iclass 4, count 0 2006.257.16:54:09.76#ibcon#about to read 4, iclass 4, count 0 2006.257.16:54:09.76#ibcon#read 4, iclass 4, count 0 2006.257.16:54:09.76#ibcon#about to read 5, iclass 4, count 0 2006.257.16:54:09.76#ibcon#read 5, iclass 4, count 0 2006.257.16:54:09.76#ibcon#about to read 6, iclass 4, count 0 2006.257.16:54:09.76#ibcon#read 6, iclass 4, count 0 2006.257.16:54:09.76#ibcon#end of sib2, iclass 4, count 0 2006.257.16:54:09.76#ibcon#*after write, iclass 4, count 0 2006.257.16:54:09.76#ibcon#*before return 0, iclass 4, count 0 2006.257.16:54:09.76#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:09.76#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:09.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:54:09.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:54:09.76$vck44/valo=5,734.99 2006.257.16:54:09.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.16:54:09.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.16:54:09.77#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:09.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:09.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:09.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:09.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:54:09.77#ibcon#first serial, iclass 6, count 0 2006.257.16:54:09.77#ibcon#enter sib2, iclass 6, count 0 2006.257.16:54:09.77#ibcon#flushed, iclass 6, count 0 2006.257.16:54:09.77#ibcon#about to write, iclass 6, count 0 2006.257.16:54:09.77#ibcon#wrote, iclass 6, count 0 2006.257.16:54:09.77#ibcon#about to read 3, iclass 6, count 0 2006.257.16:54:09.78#ibcon#read 3, iclass 6, count 0 2006.257.16:54:09.78#ibcon#about to read 4, iclass 6, count 0 2006.257.16:54:09.78#ibcon#read 4, iclass 6, count 0 2006.257.16:54:09.78#ibcon#about to read 5, iclass 6, count 0 2006.257.16:54:09.78#ibcon#read 5, iclass 6, count 0 2006.257.16:54:09.78#ibcon#about to read 6, iclass 6, count 0 2006.257.16:54:09.78#ibcon#read 6, iclass 6, count 0 2006.257.16:54:09.78#ibcon#end of sib2, iclass 6, count 0 2006.257.16:54:09.78#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:54:09.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:54:09.78#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.16:54:09.78#ibcon#*before write, iclass 6, count 0 2006.257.16:54:09.78#ibcon#enter sib2, iclass 6, count 0 2006.257.16:54:09.78#ibcon#flushed, iclass 6, count 0 2006.257.16:54:09.78#ibcon#about to write, iclass 6, count 0 2006.257.16:54:09.78#ibcon#wrote, iclass 6, count 0 2006.257.16:54:09.78#ibcon#about to read 3, iclass 6, count 0 2006.257.16:54:09.82#ibcon#read 3, iclass 6, count 0 2006.257.16:54:09.82#ibcon#about to read 4, iclass 6, count 0 2006.257.16:54:09.82#ibcon#read 4, iclass 6, count 0 2006.257.16:54:09.82#ibcon#about to read 5, iclass 6, count 0 2006.257.16:54:09.82#ibcon#read 5, iclass 6, count 0 2006.257.16:54:09.82#ibcon#about to read 6, iclass 6, count 0 2006.257.16:54:09.82#ibcon#read 6, iclass 6, count 0 2006.257.16:54:09.82#ibcon#end of sib2, iclass 6, count 0 2006.257.16:54:09.82#ibcon#*after write, iclass 6, count 0 2006.257.16:54:09.82#ibcon#*before return 0, iclass 6, count 0 2006.257.16:54:09.82#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:09.82#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:09.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:54:09.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:54:09.82$vck44/va=5,4 2006.257.16:54:09.83#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.16:54:09.83#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.16:54:09.83#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:09.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:09.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:09.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:09.87#ibcon#enter wrdev, iclass 10, count 2 2006.257.16:54:09.87#ibcon#first serial, iclass 10, count 2 2006.257.16:54:09.87#ibcon#enter sib2, iclass 10, count 2 2006.257.16:54:09.87#ibcon#flushed, iclass 10, count 2 2006.257.16:54:09.87#ibcon#about to write, iclass 10, count 2 2006.257.16:54:09.87#ibcon#wrote, iclass 10, count 2 2006.257.16:54:09.87#ibcon#about to read 3, iclass 10, count 2 2006.257.16:54:09.89#ibcon#read 3, iclass 10, count 2 2006.257.16:54:09.89#ibcon#about to read 4, iclass 10, count 2 2006.257.16:54:09.89#ibcon#read 4, iclass 10, count 2 2006.257.16:54:09.89#ibcon#about to read 5, iclass 10, count 2 2006.257.16:54:09.89#ibcon#read 5, iclass 10, count 2 2006.257.16:54:09.89#ibcon#about to read 6, iclass 10, count 2 2006.257.16:54:09.89#ibcon#read 6, iclass 10, count 2 2006.257.16:54:09.89#ibcon#end of sib2, iclass 10, count 2 2006.257.16:54:09.89#ibcon#*mode == 0, iclass 10, count 2 2006.257.16:54:09.89#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.16:54:09.89#ibcon#[25=AT05-04\r\n] 2006.257.16:54:09.89#ibcon#*before write, iclass 10, count 2 2006.257.16:54:09.89#ibcon#enter sib2, iclass 10, count 2 2006.257.16:54:09.89#ibcon#flushed, iclass 10, count 2 2006.257.16:54:09.89#ibcon#about to write, iclass 10, count 2 2006.257.16:54:09.89#ibcon#wrote, iclass 10, count 2 2006.257.16:54:09.89#ibcon#about to read 3, iclass 10, count 2 2006.257.16:54:09.92#ibcon#read 3, iclass 10, count 2 2006.257.16:54:09.92#ibcon#about to read 4, iclass 10, count 2 2006.257.16:54:09.92#ibcon#read 4, iclass 10, count 2 2006.257.16:54:09.92#ibcon#about to read 5, iclass 10, count 2 2006.257.16:54:09.92#ibcon#read 5, iclass 10, count 2 2006.257.16:54:09.92#ibcon#about to read 6, iclass 10, count 2 2006.257.16:54:09.92#ibcon#read 6, iclass 10, count 2 2006.257.16:54:09.92#ibcon#end of sib2, iclass 10, count 2 2006.257.16:54:09.92#ibcon#*after write, iclass 10, count 2 2006.257.16:54:09.92#ibcon#*before return 0, iclass 10, count 2 2006.257.16:54:09.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:09.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:09.92#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.16:54:09.92#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:09.92#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:10.04#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:10.04#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:10.04#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:54:10.04#ibcon#first serial, iclass 10, count 0 2006.257.16:54:10.04#ibcon#enter sib2, iclass 10, count 0 2006.257.16:54:10.04#ibcon#flushed, iclass 10, count 0 2006.257.16:54:10.04#ibcon#about to write, iclass 10, count 0 2006.257.16:54:10.04#ibcon#wrote, iclass 10, count 0 2006.257.16:54:10.04#ibcon#about to read 3, iclass 10, count 0 2006.257.16:54:10.06#ibcon#read 3, iclass 10, count 0 2006.257.16:54:10.06#ibcon#about to read 4, iclass 10, count 0 2006.257.16:54:10.06#ibcon#read 4, iclass 10, count 0 2006.257.16:54:10.06#ibcon#about to read 5, iclass 10, count 0 2006.257.16:54:10.06#ibcon#read 5, iclass 10, count 0 2006.257.16:54:10.06#ibcon#about to read 6, iclass 10, count 0 2006.257.16:54:10.06#ibcon#read 6, iclass 10, count 0 2006.257.16:54:10.06#ibcon#end of sib2, iclass 10, count 0 2006.257.16:54:10.06#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:54:10.06#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:54:10.06#ibcon#[25=USB\r\n] 2006.257.16:54:10.06#ibcon#*before write, iclass 10, count 0 2006.257.16:54:10.06#ibcon#enter sib2, iclass 10, count 0 2006.257.16:54:10.06#ibcon#flushed, iclass 10, count 0 2006.257.16:54:10.06#ibcon#about to write, iclass 10, count 0 2006.257.16:54:10.06#ibcon#wrote, iclass 10, count 0 2006.257.16:54:10.06#ibcon#about to read 3, iclass 10, count 0 2006.257.16:54:10.09#ibcon#read 3, iclass 10, count 0 2006.257.16:54:10.09#ibcon#about to read 4, iclass 10, count 0 2006.257.16:54:10.09#ibcon#read 4, iclass 10, count 0 2006.257.16:54:10.09#ibcon#about to read 5, iclass 10, count 0 2006.257.16:54:10.09#ibcon#read 5, iclass 10, count 0 2006.257.16:54:10.09#ibcon#about to read 6, iclass 10, count 0 2006.257.16:54:10.09#ibcon#read 6, iclass 10, count 0 2006.257.16:54:10.09#ibcon#end of sib2, iclass 10, count 0 2006.257.16:54:10.09#ibcon#*after write, iclass 10, count 0 2006.257.16:54:10.09#ibcon#*before return 0, iclass 10, count 0 2006.257.16:54:10.09#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:10.09#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:10.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:54:10.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:54:10.09$vck44/valo=6,814.99 2006.257.16:54:10.09#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.16:54:10.09#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.16:54:10.09#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:10.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:10.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:10.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:10.09#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:54:10.09#ibcon#first serial, iclass 12, count 0 2006.257.16:54:10.09#ibcon#enter sib2, iclass 12, count 0 2006.257.16:54:10.09#ibcon#flushed, iclass 12, count 0 2006.257.16:54:10.09#ibcon#about to write, iclass 12, count 0 2006.257.16:54:10.09#ibcon#wrote, iclass 12, count 0 2006.257.16:54:10.09#ibcon#about to read 3, iclass 12, count 0 2006.257.16:54:10.11#ibcon#read 3, iclass 12, count 0 2006.257.16:54:10.11#ibcon#about to read 4, iclass 12, count 0 2006.257.16:54:10.11#ibcon#read 4, iclass 12, count 0 2006.257.16:54:10.11#ibcon#about to read 5, iclass 12, count 0 2006.257.16:54:10.11#ibcon#read 5, iclass 12, count 0 2006.257.16:54:10.11#ibcon#about to read 6, iclass 12, count 0 2006.257.16:54:10.11#ibcon#read 6, iclass 12, count 0 2006.257.16:54:10.11#ibcon#end of sib2, iclass 12, count 0 2006.257.16:54:10.11#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:54:10.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:54:10.11#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.16:54:10.11#ibcon#*before write, iclass 12, count 0 2006.257.16:54:10.11#ibcon#enter sib2, iclass 12, count 0 2006.257.16:54:10.11#ibcon#flushed, iclass 12, count 0 2006.257.16:54:10.11#ibcon#about to write, iclass 12, count 0 2006.257.16:54:10.11#ibcon#wrote, iclass 12, count 0 2006.257.16:54:10.11#ibcon#about to read 3, iclass 12, count 0 2006.257.16:54:10.15#ibcon#read 3, iclass 12, count 0 2006.257.16:54:10.15#ibcon#about to read 4, iclass 12, count 0 2006.257.16:54:10.15#ibcon#read 4, iclass 12, count 0 2006.257.16:54:10.15#ibcon#about to read 5, iclass 12, count 0 2006.257.16:54:10.15#ibcon#read 5, iclass 12, count 0 2006.257.16:54:10.15#ibcon#about to read 6, iclass 12, count 0 2006.257.16:54:10.15#ibcon#read 6, iclass 12, count 0 2006.257.16:54:10.15#ibcon#end of sib2, iclass 12, count 0 2006.257.16:54:10.15#ibcon#*after write, iclass 12, count 0 2006.257.16:54:10.15#ibcon#*before return 0, iclass 12, count 0 2006.257.16:54:10.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:10.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:10.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:54:10.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:54:10.15$vck44/va=6,4 2006.257.16:54:10.15#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.16:54:10.15#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.16:54:10.15#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:10.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:10.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:10.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:10.21#ibcon#enter wrdev, iclass 14, count 2 2006.257.16:54:10.21#ibcon#first serial, iclass 14, count 2 2006.257.16:54:10.21#ibcon#enter sib2, iclass 14, count 2 2006.257.16:54:10.21#ibcon#flushed, iclass 14, count 2 2006.257.16:54:10.21#ibcon#about to write, iclass 14, count 2 2006.257.16:54:10.21#ibcon#wrote, iclass 14, count 2 2006.257.16:54:10.21#ibcon#about to read 3, iclass 14, count 2 2006.257.16:54:10.23#ibcon#read 3, iclass 14, count 2 2006.257.16:54:10.23#ibcon#about to read 4, iclass 14, count 2 2006.257.16:54:10.23#ibcon#read 4, iclass 14, count 2 2006.257.16:54:10.23#ibcon#about to read 5, iclass 14, count 2 2006.257.16:54:10.23#ibcon#read 5, iclass 14, count 2 2006.257.16:54:10.23#ibcon#about to read 6, iclass 14, count 2 2006.257.16:54:10.23#ibcon#read 6, iclass 14, count 2 2006.257.16:54:10.23#ibcon#end of sib2, iclass 14, count 2 2006.257.16:54:10.23#ibcon#*mode == 0, iclass 14, count 2 2006.257.16:54:10.23#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.16:54:10.23#ibcon#[25=AT06-04\r\n] 2006.257.16:54:10.23#ibcon#*before write, iclass 14, count 2 2006.257.16:54:10.23#ibcon#enter sib2, iclass 14, count 2 2006.257.16:54:10.23#ibcon#flushed, iclass 14, count 2 2006.257.16:54:10.23#ibcon#about to write, iclass 14, count 2 2006.257.16:54:10.23#ibcon#wrote, iclass 14, count 2 2006.257.16:54:10.23#ibcon#about to read 3, iclass 14, count 2 2006.257.16:54:10.26#ibcon#read 3, iclass 14, count 2 2006.257.16:54:10.26#ibcon#about to read 4, iclass 14, count 2 2006.257.16:54:10.26#ibcon#read 4, iclass 14, count 2 2006.257.16:54:10.26#ibcon#about to read 5, iclass 14, count 2 2006.257.16:54:10.26#ibcon#read 5, iclass 14, count 2 2006.257.16:54:10.26#ibcon#about to read 6, iclass 14, count 2 2006.257.16:54:10.26#ibcon#read 6, iclass 14, count 2 2006.257.16:54:10.26#ibcon#end of sib2, iclass 14, count 2 2006.257.16:54:10.26#ibcon#*after write, iclass 14, count 2 2006.257.16:54:10.26#ibcon#*before return 0, iclass 14, count 2 2006.257.16:54:10.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:10.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:10.26#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.16:54:10.26#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:10.26#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:10.38#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:10.38#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:10.38#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:54:10.38#ibcon#first serial, iclass 14, count 0 2006.257.16:54:10.38#ibcon#enter sib2, iclass 14, count 0 2006.257.16:54:10.38#ibcon#flushed, iclass 14, count 0 2006.257.16:54:10.38#ibcon#about to write, iclass 14, count 0 2006.257.16:54:10.38#ibcon#wrote, iclass 14, count 0 2006.257.16:54:10.38#ibcon#about to read 3, iclass 14, count 0 2006.257.16:54:10.40#ibcon#read 3, iclass 14, count 0 2006.257.16:54:10.40#ibcon#about to read 4, iclass 14, count 0 2006.257.16:54:10.40#ibcon#read 4, iclass 14, count 0 2006.257.16:54:10.40#ibcon#about to read 5, iclass 14, count 0 2006.257.16:54:10.40#ibcon#read 5, iclass 14, count 0 2006.257.16:54:10.40#ibcon#about to read 6, iclass 14, count 0 2006.257.16:54:10.40#ibcon#read 6, iclass 14, count 0 2006.257.16:54:10.40#ibcon#end of sib2, iclass 14, count 0 2006.257.16:54:10.40#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:54:10.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:54:10.40#ibcon#[25=USB\r\n] 2006.257.16:54:10.40#ibcon#*before write, iclass 14, count 0 2006.257.16:54:10.40#ibcon#enter sib2, iclass 14, count 0 2006.257.16:54:10.40#ibcon#flushed, iclass 14, count 0 2006.257.16:54:10.40#ibcon#about to write, iclass 14, count 0 2006.257.16:54:10.40#ibcon#wrote, iclass 14, count 0 2006.257.16:54:10.40#ibcon#about to read 3, iclass 14, count 0 2006.257.16:54:10.43#ibcon#read 3, iclass 14, count 0 2006.257.16:54:10.43#ibcon#about to read 4, iclass 14, count 0 2006.257.16:54:10.43#ibcon#read 4, iclass 14, count 0 2006.257.16:54:10.43#ibcon#about to read 5, iclass 14, count 0 2006.257.16:54:10.43#ibcon#read 5, iclass 14, count 0 2006.257.16:54:10.43#ibcon#about to read 6, iclass 14, count 0 2006.257.16:54:10.43#ibcon#read 6, iclass 14, count 0 2006.257.16:54:10.43#ibcon#end of sib2, iclass 14, count 0 2006.257.16:54:10.43#ibcon#*after write, iclass 14, count 0 2006.257.16:54:10.43#ibcon#*before return 0, iclass 14, count 0 2006.257.16:54:10.43#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:10.43#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:10.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:54:10.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:54:10.43$vck44/valo=7,864.99 2006.257.16:54:10.43#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.16:54:10.43#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.16:54:10.43#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:10.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:10.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:10.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:10.43#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:54:10.43#ibcon#first serial, iclass 16, count 0 2006.257.16:54:10.43#ibcon#enter sib2, iclass 16, count 0 2006.257.16:54:10.43#ibcon#flushed, iclass 16, count 0 2006.257.16:54:10.43#ibcon#about to write, iclass 16, count 0 2006.257.16:54:10.43#ibcon#wrote, iclass 16, count 0 2006.257.16:54:10.43#ibcon#about to read 3, iclass 16, count 0 2006.257.16:54:10.45#ibcon#read 3, iclass 16, count 0 2006.257.16:54:10.45#ibcon#about to read 4, iclass 16, count 0 2006.257.16:54:10.45#ibcon#read 4, iclass 16, count 0 2006.257.16:54:10.45#ibcon#about to read 5, iclass 16, count 0 2006.257.16:54:10.45#ibcon#read 5, iclass 16, count 0 2006.257.16:54:10.45#ibcon#about to read 6, iclass 16, count 0 2006.257.16:54:10.45#ibcon#read 6, iclass 16, count 0 2006.257.16:54:10.45#ibcon#end of sib2, iclass 16, count 0 2006.257.16:54:10.45#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:54:10.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:54:10.45#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.16:54:10.45#ibcon#*before write, iclass 16, count 0 2006.257.16:54:10.45#ibcon#enter sib2, iclass 16, count 0 2006.257.16:54:10.45#ibcon#flushed, iclass 16, count 0 2006.257.16:54:10.45#ibcon#about to write, iclass 16, count 0 2006.257.16:54:10.45#ibcon#wrote, iclass 16, count 0 2006.257.16:54:10.45#ibcon#about to read 3, iclass 16, count 0 2006.257.16:54:10.49#ibcon#read 3, iclass 16, count 0 2006.257.16:54:10.49#ibcon#about to read 4, iclass 16, count 0 2006.257.16:54:10.49#ibcon#read 4, iclass 16, count 0 2006.257.16:54:10.49#ibcon#about to read 5, iclass 16, count 0 2006.257.16:54:10.49#ibcon#read 5, iclass 16, count 0 2006.257.16:54:10.49#ibcon#about to read 6, iclass 16, count 0 2006.257.16:54:10.49#ibcon#read 6, iclass 16, count 0 2006.257.16:54:10.49#ibcon#end of sib2, iclass 16, count 0 2006.257.16:54:10.49#ibcon#*after write, iclass 16, count 0 2006.257.16:54:10.49#ibcon#*before return 0, iclass 16, count 0 2006.257.16:54:10.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:10.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:10.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:54:10.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:54:10.49$vck44/va=7,4 2006.257.16:54:10.49#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.16:54:10.49#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.16:54:10.49#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:10.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:10.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:10.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:10.55#ibcon#enter wrdev, iclass 18, count 2 2006.257.16:54:10.55#ibcon#first serial, iclass 18, count 2 2006.257.16:54:10.55#ibcon#enter sib2, iclass 18, count 2 2006.257.16:54:10.55#ibcon#flushed, iclass 18, count 2 2006.257.16:54:10.55#ibcon#about to write, iclass 18, count 2 2006.257.16:54:10.55#ibcon#wrote, iclass 18, count 2 2006.257.16:54:10.55#ibcon#about to read 3, iclass 18, count 2 2006.257.16:54:10.57#ibcon#read 3, iclass 18, count 2 2006.257.16:54:10.57#ibcon#about to read 4, iclass 18, count 2 2006.257.16:54:10.57#ibcon#read 4, iclass 18, count 2 2006.257.16:54:10.57#ibcon#about to read 5, iclass 18, count 2 2006.257.16:54:10.57#ibcon#read 5, iclass 18, count 2 2006.257.16:54:10.57#ibcon#about to read 6, iclass 18, count 2 2006.257.16:54:10.57#ibcon#read 6, iclass 18, count 2 2006.257.16:54:10.57#ibcon#end of sib2, iclass 18, count 2 2006.257.16:54:10.57#ibcon#*mode == 0, iclass 18, count 2 2006.257.16:54:10.57#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.16:54:10.57#ibcon#[25=AT07-04\r\n] 2006.257.16:54:10.57#ibcon#*before write, iclass 18, count 2 2006.257.16:54:10.57#ibcon#enter sib2, iclass 18, count 2 2006.257.16:54:10.57#ibcon#flushed, iclass 18, count 2 2006.257.16:54:10.57#ibcon#about to write, iclass 18, count 2 2006.257.16:54:10.57#ibcon#wrote, iclass 18, count 2 2006.257.16:54:10.57#ibcon#about to read 3, iclass 18, count 2 2006.257.16:54:10.60#ibcon#read 3, iclass 18, count 2 2006.257.16:54:10.60#ibcon#about to read 4, iclass 18, count 2 2006.257.16:54:10.60#ibcon#read 4, iclass 18, count 2 2006.257.16:54:10.60#ibcon#about to read 5, iclass 18, count 2 2006.257.16:54:10.60#ibcon#read 5, iclass 18, count 2 2006.257.16:54:10.60#ibcon#about to read 6, iclass 18, count 2 2006.257.16:54:10.60#ibcon#read 6, iclass 18, count 2 2006.257.16:54:10.60#ibcon#end of sib2, iclass 18, count 2 2006.257.16:54:10.60#ibcon#*after write, iclass 18, count 2 2006.257.16:54:10.60#ibcon#*before return 0, iclass 18, count 2 2006.257.16:54:10.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:10.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:10.60#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.16:54:10.60#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:10.60#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:10.72#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:10.72#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:10.72#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:54:10.72#ibcon#first serial, iclass 18, count 0 2006.257.16:54:10.72#ibcon#enter sib2, iclass 18, count 0 2006.257.16:54:10.72#ibcon#flushed, iclass 18, count 0 2006.257.16:54:10.72#ibcon#about to write, iclass 18, count 0 2006.257.16:54:10.72#ibcon#wrote, iclass 18, count 0 2006.257.16:54:10.72#ibcon#about to read 3, iclass 18, count 0 2006.257.16:54:10.74#ibcon#read 3, iclass 18, count 0 2006.257.16:54:10.74#ibcon#about to read 4, iclass 18, count 0 2006.257.16:54:10.74#ibcon#read 4, iclass 18, count 0 2006.257.16:54:10.74#ibcon#about to read 5, iclass 18, count 0 2006.257.16:54:10.74#ibcon#read 5, iclass 18, count 0 2006.257.16:54:10.74#ibcon#about to read 6, iclass 18, count 0 2006.257.16:54:10.74#ibcon#read 6, iclass 18, count 0 2006.257.16:54:10.74#ibcon#end of sib2, iclass 18, count 0 2006.257.16:54:10.74#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:54:10.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:54:10.74#ibcon#[25=USB\r\n] 2006.257.16:54:10.74#ibcon#*before write, iclass 18, count 0 2006.257.16:54:10.74#ibcon#enter sib2, iclass 18, count 0 2006.257.16:54:10.74#ibcon#flushed, iclass 18, count 0 2006.257.16:54:10.74#ibcon#about to write, iclass 18, count 0 2006.257.16:54:10.74#ibcon#wrote, iclass 18, count 0 2006.257.16:54:10.74#ibcon#about to read 3, iclass 18, count 0 2006.257.16:54:10.77#ibcon#read 3, iclass 18, count 0 2006.257.16:54:10.77#ibcon#about to read 4, iclass 18, count 0 2006.257.16:54:10.77#ibcon#read 4, iclass 18, count 0 2006.257.16:54:10.77#ibcon#about to read 5, iclass 18, count 0 2006.257.16:54:10.77#ibcon#read 5, iclass 18, count 0 2006.257.16:54:10.77#ibcon#about to read 6, iclass 18, count 0 2006.257.16:54:10.77#ibcon#read 6, iclass 18, count 0 2006.257.16:54:10.77#ibcon#end of sib2, iclass 18, count 0 2006.257.16:54:10.77#ibcon#*after write, iclass 18, count 0 2006.257.16:54:10.77#ibcon#*before return 0, iclass 18, count 0 2006.257.16:54:10.77#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:10.77#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:10.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:54:10.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:54:10.77$vck44/valo=8,884.99 2006.257.16:54:10.77#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.16:54:10.77#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.16:54:10.77#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:10.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:10.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:10.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:10.77#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:54:10.77#ibcon#first serial, iclass 20, count 0 2006.257.16:54:10.77#ibcon#enter sib2, iclass 20, count 0 2006.257.16:54:10.77#ibcon#flushed, iclass 20, count 0 2006.257.16:54:10.77#ibcon#about to write, iclass 20, count 0 2006.257.16:54:10.77#ibcon#wrote, iclass 20, count 0 2006.257.16:54:10.77#ibcon#about to read 3, iclass 20, count 0 2006.257.16:54:10.79#ibcon#read 3, iclass 20, count 0 2006.257.16:54:10.79#ibcon#about to read 4, iclass 20, count 0 2006.257.16:54:10.79#ibcon#read 4, iclass 20, count 0 2006.257.16:54:10.79#ibcon#about to read 5, iclass 20, count 0 2006.257.16:54:10.79#ibcon#read 5, iclass 20, count 0 2006.257.16:54:10.79#ibcon#about to read 6, iclass 20, count 0 2006.257.16:54:10.79#ibcon#read 6, iclass 20, count 0 2006.257.16:54:10.79#ibcon#end of sib2, iclass 20, count 0 2006.257.16:54:10.79#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:54:10.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:54:10.79#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.16:54:10.79#ibcon#*before write, iclass 20, count 0 2006.257.16:54:10.79#ibcon#enter sib2, iclass 20, count 0 2006.257.16:54:10.79#ibcon#flushed, iclass 20, count 0 2006.257.16:54:10.79#ibcon#about to write, iclass 20, count 0 2006.257.16:54:10.79#ibcon#wrote, iclass 20, count 0 2006.257.16:54:10.79#ibcon#about to read 3, iclass 20, count 0 2006.257.16:54:10.83#ibcon#read 3, iclass 20, count 0 2006.257.16:54:10.83#ibcon#about to read 4, iclass 20, count 0 2006.257.16:54:10.83#ibcon#read 4, iclass 20, count 0 2006.257.16:54:10.83#ibcon#about to read 5, iclass 20, count 0 2006.257.16:54:10.83#ibcon#read 5, iclass 20, count 0 2006.257.16:54:10.83#ibcon#about to read 6, iclass 20, count 0 2006.257.16:54:10.83#ibcon#read 6, iclass 20, count 0 2006.257.16:54:10.83#ibcon#end of sib2, iclass 20, count 0 2006.257.16:54:10.83#ibcon#*after write, iclass 20, count 0 2006.257.16:54:10.83#ibcon#*before return 0, iclass 20, count 0 2006.257.16:54:10.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:10.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:10.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:54:10.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:54:10.83$vck44/va=8,4 2006.257.16:54:10.83#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.16:54:10.83#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.16:54:10.83#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:10.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:54:10.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:54:10.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:54:10.89#ibcon#enter wrdev, iclass 22, count 2 2006.257.16:54:10.89#ibcon#first serial, iclass 22, count 2 2006.257.16:54:10.89#ibcon#enter sib2, iclass 22, count 2 2006.257.16:54:10.89#ibcon#flushed, iclass 22, count 2 2006.257.16:54:10.89#ibcon#about to write, iclass 22, count 2 2006.257.16:54:10.89#ibcon#wrote, iclass 22, count 2 2006.257.16:54:10.89#ibcon#about to read 3, iclass 22, count 2 2006.257.16:54:10.91#ibcon#read 3, iclass 22, count 2 2006.257.16:54:10.91#ibcon#about to read 4, iclass 22, count 2 2006.257.16:54:10.91#ibcon#read 4, iclass 22, count 2 2006.257.16:54:10.91#ibcon#about to read 5, iclass 22, count 2 2006.257.16:54:10.91#ibcon#read 5, iclass 22, count 2 2006.257.16:54:10.91#ibcon#about to read 6, iclass 22, count 2 2006.257.16:54:10.91#ibcon#read 6, iclass 22, count 2 2006.257.16:54:10.91#ibcon#end of sib2, iclass 22, count 2 2006.257.16:54:10.91#ibcon#*mode == 0, iclass 22, count 2 2006.257.16:54:10.91#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.16:54:10.91#ibcon#[25=AT08-04\r\n] 2006.257.16:54:10.91#ibcon#*before write, iclass 22, count 2 2006.257.16:54:10.91#ibcon#enter sib2, iclass 22, count 2 2006.257.16:54:10.91#ibcon#flushed, iclass 22, count 2 2006.257.16:54:10.91#ibcon#about to write, iclass 22, count 2 2006.257.16:54:10.91#ibcon#wrote, iclass 22, count 2 2006.257.16:54:10.91#ibcon#about to read 3, iclass 22, count 2 2006.257.16:54:10.94#ibcon#read 3, iclass 22, count 2 2006.257.16:54:10.94#ibcon#about to read 4, iclass 22, count 2 2006.257.16:54:10.94#ibcon#read 4, iclass 22, count 2 2006.257.16:54:10.94#ibcon#about to read 5, iclass 22, count 2 2006.257.16:54:10.94#ibcon#read 5, iclass 22, count 2 2006.257.16:54:10.94#ibcon#about to read 6, iclass 22, count 2 2006.257.16:54:10.94#ibcon#read 6, iclass 22, count 2 2006.257.16:54:10.94#ibcon#end of sib2, iclass 22, count 2 2006.257.16:54:10.94#ibcon#*after write, iclass 22, count 2 2006.257.16:54:10.94#ibcon#*before return 0, iclass 22, count 2 2006.257.16:54:10.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:54:10.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.16:54:10.94#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.16:54:10.94#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:10.94#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:54:11.06#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:54:11.06#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:54:11.06#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:54:11.06#ibcon#first serial, iclass 22, count 0 2006.257.16:54:11.06#ibcon#enter sib2, iclass 22, count 0 2006.257.16:54:11.06#ibcon#flushed, iclass 22, count 0 2006.257.16:54:11.06#ibcon#about to write, iclass 22, count 0 2006.257.16:54:11.06#ibcon#wrote, iclass 22, count 0 2006.257.16:54:11.06#ibcon#about to read 3, iclass 22, count 0 2006.257.16:54:11.08#ibcon#read 3, iclass 22, count 0 2006.257.16:54:11.08#ibcon#about to read 4, iclass 22, count 0 2006.257.16:54:11.08#ibcon#read 4, iclass 22, count 0 2006.257.16:54:11.08#ibcon#about to read 5, iclass 22, count 0 2006.257.16:54:11.08#ibcon#read 5, iclass 22, count 0 2006.257.16:54:11.08#ibcon#about to read 6, iclass 22, count 0 2006.257.16:54:11.08#ibcon#read 6, iclass 22, count 0 2006.257.16:54:11.08#ibcon#end of sib2, iclass 22, count 0 2006.257.16:54:11.08#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:54:11.08#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:54:11.08#ibcon#[25=USB\r\n] 2006.257.16:54:11.08#ibcon#*before write, iclass 22, count 0 2006.257.16:54:11.08#ibcon#enter sib2, iclass 22, count 0 2006.257.16:54:11.08#ibcon#flushed, iclass 22, count 0 2006.257.16:54:11.08#ibcon#about to write, iclass 22, count 0 2006.257.16:54:11.08#ibcon#wrote, iclass 22, count 0 2006.257.16:54:11.08#ibcon#about to read 3, iclass 22, count 0 2006.257.16:54:11.11#ibcon#read 3, iclass 22, count 0 2006.257.16:54:11.11#ibcon#about to read 4, iclass 22, count 0 2006.257.16:54:11.11#ibcon#read 4, iclass 22, count 0 2006.257.16:54:11.11#ibcon#about to read 5, iclass 22, count 0 2006.257.16:54:11.11#ibcon#read 5, iclass 22, count 0 2006.257.16:54:11.11#ibcon#about to read 6, iclass 22, count 0 2006.257.16:54:11.11#ibcon#read 6, iclass 22, count 0 2006.257.16:54:11.11#ibcon#end of sib2, iclass 22, count 0 2006.257.16:54:11.11#ibcon#*after write, iclass 22, count 0 2006.257.16:54:11.11#ibcon#*before return 0, iclass 22, count 0 2006.257.16:54:11.11#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:54:11.11#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.16:54:11.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:54:11.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:54:11.11$vck44/vblo=1,629.99 2006.257.16:54:11.11#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.16:54:11.11#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.16:54:11.11#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:11.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:54:11.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:54:11.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:54:11.11#ibcon#enter wrdev, iclass 24, count 0 2006.257.16:54:11.11#ibcon#first serial, iclass 24, count 0 2006.257.16:54:11.11#ibcon#enter sib2, iclass 24, count 0 2006.257.16:54:11.11#ibcon#flushed, iclass 24, count 0 2006.257.16:54:11.11#ibcon#about to write, iclass 24, count 0 2006.257.16:54:11.11#ibcon#wrote, iclass 24, count 0 2006.257.16:54:11.11#ibcon#about to read 3, iclass 24, count 0 2006.257.16:54:11.13#ibcon#read 3, iclass 24, count 0 2006.257.16:54:11.13#ibcon#about to read 4, iclass 24, count 0 2006.257.16:54:11.13#ibcon#read 4, iclass 24, count 0 2006.257.16:54:11.13#ibcon#about to read 5, iclass 24, count 0 2006.257.16:54:11.13#ibcon#read 5, iclass 24, count 0 2006.257.16:54:11.13#ibcon#about to read 6, iclass 24, count 0 2006.257.16:54:11.13#ibcon#read 6, iclass 24, count 0 2006.257.16:54:11.13#ibcon#end of sib2, iclass 24, count 0 2006.257.16:54:11.13#ibcon#*mode == 0, iclass 24, count 0 2006.257.16:54:11.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.16:54:11.13#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.16:54:11.13#ibcon#*before write, iclass 24, count 0 2006.257.16:54:11.13#ibcon#enter sib2, iclass 24, count 0 2006.257.16:54:11.13#ibcon#flushed, iclass 24, count 0 2006.257.16:54:11.13#ibcon#about to write, iclass 24, count 0 2006.257.16:54:11.13#ibcon#wrote, iclass 24, count 0 2006.257.16:54:11.13#ibcon#about to read 3, iclass 24, count 0 2006.257.16:54:11.17#ibcon#read 3, iclass 24, count 0 2006.257.16:54:11.17#ibcon#about to read 4, iclass 24, count 0 2006.257.16:54:11.17#ibcon#read 4, iclass 24, count 0 2006.257.16:54:11.17#ibcon#about to read 5, iclass 24, count 0 2006.257.16:54:11.17#ibcon#read 5, iclass 24, count 0 2006.257.16:54:11.17#ibcon#about to read 6, iclass 24, count 0 2006.257.16:54:11.17#ibcon#read 6, iclass 24, count 0 2006.257.16:54:11.17#ibcon#end of sib2, iclass 24, count 0 2006.257.16:54:11.17#ibcon#*after write, iclass 24, count 0 2006.257.16:54:11.17#ibcon#*before return 0, iclass 24, count 0 2006.257.16:54:11.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:54:11.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.16:54:11.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.16:54:11.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.16:54:11.17$vck44/vb=1,4 2006.257.16:54:11.17#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.16:54:11.17#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.16:54:11.17#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:11.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:54:11.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:54:11.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:54:11.17#ibcon#enter wrdev, iclass 26, count 2 2006.257.16:54:11.17#ibcon#first serial, iclass 26, count 2 2006.257.16:54:11.17#ibcon#enter sib2, iclass 26, count 2 2006.257.16:54:11.17#ibcon#flushed, iclass 26, count 2 2006.257.16:54:11.17#ibcon#about to write, iclass 26, count 2 2006.257.16:54:11.17#ibcon#wrote, iclass 26, count 2 2006.257.16:54:11.17#ibcon#about to read 3, iclass 26, count 2 2006.257.16:54:11.19#ibcon#read 3, iclass 26, count 2 2006.257.16:54:11.19#ibcon#about to read 4, iclass 26, count 2 2006.257.16:54:11.19#ibcon#read 4, iclass 26, count 2 2006.257.16:54:11.19#ibcon#about to read 5, iclass 26, count 2 2006.257.16:54:11.19#ibcon#read 5, iclass 26, count 2 2006.257.16:54:11.19#ibcon#about to read 6, iclass 26, count 2 2006.257.16:54:11.19#ibcon#read 6, iclass 26, count 2 2006.257.16:54:11.19#ibcon#end of sib2, iclass 26, count 2 2006.257.16:54:11.19#ibcon#*mode == 0, iclass 26, count 2 2006.257.16:54:11.19#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.16:54:11.19#ibcon#[27=AT01-04\r\n] 2006.257.16:54:11.19#ibcon#*before write, iclass 26, count 2 2006.257.16:54:11.19#ibcon#enter sib2, iclass 26, count 2 2006.257.16:54:11.19#ibcon#flushed, iclass 26, count 2 2006.257.16:54:11.19#ibcon#about to write, iclass 26, count 2 2006.257.16:54:11.19#ibcon#wrote, iclass 26, count 2 2006.257.16:54:11.19#ibcon#about to read 3, iclass 26, count 2 2006.257.16:54:11.22#ibcon#read 3, iclass 26, count 2 2006.257.16:54:11.22#ibcon#about to read 4, iclass 26, count 2 2006.257.16:54:11.22#ibcon#read 4, iclass 26, count 2 2006.257.16:54:11.22#ibcon#about to read 5, iclass 26, count 2 2006.257.16:54:11.22#ibcon#read 5, iclass 26, count 2 2006.257.16:54:11.22#ibcon#about to read 6, iclass 26, count 2 2006.257.16:54:11.22#ibcon#read 6, iclass 26, count 2 2006.257.16:54:11.22#ibcon#end of sib2, iclass 26, count 2 2006.257.16:54:11.22#ibcon#*after write, iclass 26, count 2 2006.257.16:54:11.22#ibcon#*before return 0, iclass 26, count 2 2006.257.16:54:11.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:54:11.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.16:54:11.22#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.16:54:11.22#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:11.22#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:54:11.34#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:54:11.34#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:54:11.34#ibcon#enter wrdev, iclass 26, count 0 2006.257.16:54:11.34#ibcon#first serial, iclass 26, count 0 2006.257.16:54:11.34#ibcon#enter sib2, iclass 26, count 0 2006.257.16:54:11.34#ibcon#flushed, iclass 26, count 0 2006.257.16:54:11.34#ibcon#about to write, iclass 26, count 0 2006.257.16:54:11.34#ibcon#wrote, iclass 26, count 0 2006.257.16:54:11.34#ibcon#about to read 3, iclass 26, count 0 2006.257.16:54:11.36#ibcon#read 3, iclass 26, count 0 2006.257.16:54:11.36#ibcon#about to read 4, iclass 26, count 0 2006.257.16:54:11.36#ibcon#read 4, iclass 26, count 0 2006.257.16:54:11.36#ibcon#about to read 5, iclass 26, count 0 2006.257.16:54:11.36#ibcon#read 5, iclass 26, count 0 2006.257.16:54:11.36#ibcon#about to read 6, iclass 26, count 0 2006.257.16:54:11.36#ibcon#read 6, iclass 26, count 0 2006.257.16:54:11.36#ibcon#end of sib2, iclass 26, count 0 2006.257.16:54:11.36#ibcon#*mode == 0, iclass 26, count 0 2006.257.16:54:11.36#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.16:54:11.36#ibcon#[27=USB\r\n] 2006.257.16:54:11.36#ibcon#*before write, iclass 26, count 0 2006.257.16:54:11.36#ibcon#enter sib2, iclass 26, count 0 2006.257.16:54:11.36#ibcon#flushed, iclass 26, count 0 2006.257.16:54:11.36#ibcon#about to write, iclass 26, count 0 2006.257.16:54:11.36#ibcon#wrote, iclass 26, count 0 2006.257.16:54:11.36#ibcon#about to read 3, iclass 26, count 0 2006.257.16:54:11.39#ibcon#read 3, iclass 26, count 0 2006.257.16:54:11.39#ibcon#about to read 4, iclass 26, count 0 2006.257.16:54:11.39#ibcon#read 4, iclass 26, count 0 2006.257.16:54:11.39#ibcon#about to read 5, iclass 26, count 0 2006.257.16:54:11.39#ibcon#read 5, iclass 26, count 0 2006.257.16:54:11.39#ibcon#about to read 6, iclass 26, count 0 2006.257.16:54:11.39#ibcon#read 6, iclass 26, count 0 2006.257.16:54:11.39#ibcon#end of sib2, iclass 26, count 0 2006.257.16:54:11.39#ibcon#*after write, iclass 26, count 0 2006.257.16:54:11.39#ibcon#*before return 0, iclass 26, count 0 2006.257.16:54:11.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:54:11.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.16:54:11.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.16:54:11.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.16:54:11.39$vck44/vblo=2,634.99 2006.257.16:54:11.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.16:54:11.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.16:54:11.39#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:11.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:11.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:11.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:11.39#ibcon#enter wrdev, iclass 28, count 0 2006.257.16:54:11.39#ibcon#first serial, iclass 28, count 0 2006.257.16:54:11.39#ibcon#enter sib2, iclass 28, count 0 2006.257.16:54:11.39#ibcon#flushed, iclass 28, count 0 2006.257.16:54:11.39#ibcon#about to write, iclass 28, count 0 2006.257.16:54:11.39#ibcon#wrote, iclass 28, count 0 2006.257.16:54:11.39#ibcon#about to read 3, iclass 28, count 0 2006.257.16:54:11.41#ibcon#read 3, iclass 28, count 0 2006.257.16:54:11.41#ibcon#about to read 4, iclass 28, count 0 2006.257.16:54:11.41#ibcon#read 4, iclass 28, count 0 2006.257.16:54:11.41#ibcon#about to read 5, iclass 28, count 0 2006.257.16:54:11.41#ibcon#read 5, iclass 28, count 0 2006.257.16:54:11.41#ibcon#about to read 6, iclass 28, count 0 2006.257.16:54:11.41#ibcon#read 6, iclass 28, count 0 2006.257.16:54:11.41#ibcon#end of sib2, iclass 28, count 0 2006.257.16:54:11.41#ibcon#*mode == 0, iclass 28, count 0 2006.257.16:54:11.41#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.16:54:11.41#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.16:54:11.41#ibcon#*before write, iclass 28, count 0 2006.257.16:54:11.41#ibcon#enter sib2, iclass 28, count 0 2006.257.16:54:11.41#ibcon#flushed, iclass 28, count 0 2006.257.16:54:11.41#ibcon#about to write, iclass 28, count 0 2006.257.16:54:11.41#ibcon#wrote, iclass 28, count 0 2006.257.16:54:11.41#ibcon#about to read 3, iclass 28, count 0 2006.257.16:54:11.45#ibcon#read 3, iclass 28, count 0 2006.257.16:54:11.45#ibcon#about to read 4, iclass 28, count 0 2006.257.16:54:11.45#ibcon#read 4, iclass 28, count 0 2006.257.16:54:11.45#ibcon#about to read 5, iclass 28, count 0 2006.257.16:54:11.45#ibcon#read 5, iclass 28, count 0 2006.257.16:54:11.45#ibcon#about to read 6, iclass 28, count 0 2006.257.16:54:11.45#ibcon#read 6, iclass 28, count 0 2006.257.16:54:11.45#ibcon#end of sib2, iclass 28, count 0 2006.257.16:54:11.45#ibcon#*after write, iclass 28, count 0 2006.257.16:54:11.45#ibcon#*before return 0, iclass 28, count 0 2006.257.16:54:11.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:11.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.16:54:11.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.16:54:11.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.16:54:11.45$vck44/vb=2,5 2006.257.16:54:11.45#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.16:54:11.45#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.16:54:11.45#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:11.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:11.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:11.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:11.51#ibcon#enter wrdev, iclass 30, count 2 2006.257.16:54:11.51#ibcon#first serial, iclass 30, count 2 2006.257.16:54:11.51#ibcon#enter sib2, iclass 30, count 2 2006.257.16:54:11.51#ibcon#flushed, iclass 30, count 2 2006.257.16:54:11.51#ibcon#about to write, iclass 30, count 2 2006.257.16:54:11.51#ibcon#wrote, iclass 30, count 2 2006.257.16:54:11.51#ibcon#about to read 3, iclass 30, count 2 2006.257.16:54:11.53#ibcon#read 3, iclass 30, count 2 2006.257.16:54:11.53#ibcon#about to read 4, iclass 30, count 2 2006.257.16:54:11.53#ibcon#read 4, iclass 30, count 2 2006.257.16:54:11.53#ibcon#about to read 5, iclass 30, count 2 2006.257.16:54:11.53#ibcon#read 5, iclass 30, count 2 2006.257.16:54:11.53#ibcon#about to read 6, iclass 30, count 2 2006.257.16:54:11.53#ibcon#read 6, iclass 30, count 2 2006.257.16:54:11.53#ibcon#end of sib2, iclass 30, count 2 2006.257.16:54:11.53#ibcon#*mode == 0, iclass 30, count 2 2006.257.16:54:11.53#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.16:54:11.53#ibcon#[27=AT02-05\r\n] 2006.257.16:54:11.53#ibcon#*before write, iclass 30, count 2 2006.257.16:54:11.53#ibcon#enter sib2, iclass 30, count 2 2006.257.16:54:11.53#ibcon#flushed, iclass 30, count 2 2006.257.16:54:11.53#ibcon#about to write, iclass 30, count 2 2006.257.16:54:11.53#ibcon#wrote, iclass 30, count 2 2006.257.16:54:11.53#ibcon#about to read 3, iclass 30, count 2 2006.257.16:54:11.56#ibcon#read 3, iclass 30, count 2 2006.257.16:54:11.56#ibcon#about to read 4, iclass 30, count 2 2006.257.16:54:11.56#ibcon#read 4, iclass 30, count 2 2006.257.16:54:11.56#ibcon#about to read 5, iclass 30, count 2 2006.257.16:54:11.56#ibcon#read 5, iclass 30, count 2 2006.257.16:54:11.56#ibcon#about to read 6, iclass 30, count 2 2006.257.16:54:11.56#ibcon#read 6, iclass 30, count 2 2006.257.16:54:11.56#ibcon#end of sib2, iclass 30, count 2 2006.257.16:54:11.56#ibcon#*after write, iclass 30, count 2 2006.257.16:54:11.56#ibcon#*before return 0, iclass 30, count 2 2006.257.16:54:11.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:11.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.16:54:11.56#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.16:54:11.56#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:11.56#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:11.68#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:11.68#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:11.68#ibcon#enter wrdev, iclass 30, count 0 2006.257.16:54:11.68#ibcon#first serial, iclass 30, count 0 2006.257.16:54:11.68#ibcon#enter sib2, iclass 30, count 0 2006.257.16:54:11.68#ibcon#flushed, iclass 30, count 0 2006.257.16:54:11.68#ibcon#about to write, iclass 30, count 0 2006.257.16:54:11.68#ibcon#wrote, iclass 30, count 0 2006.257.16:54:11.68#ibcon#about to read 3, iclass 30, count 0 2006.257.16:54:11.70#ibcon#read 3, iclass 30, count 0 2006.257.16:54:11.70#ibcon#about to read 4, iclass 30, count 0 2006.257.16:54:11.70#ibcon#read 4, iclass 30, count 0 2006.257.16:54:11.70#ibcon#about to read 5, iclass 30, count 0 2006.257.16:54:11.70#ibcon#read 5, iclass 30, count 0 2006.257.16:54:11.70#ibcon#about to read 6, iclass 30, count 0 2006.257.16:54:11.70#ibcon#read 6, iclass 30, count 0 2006.257.16:54:11.70#ibcon#end of sib2, iclass 30, count 0 2006.257.16:54:11.70#ibcon#*mode == 0, iclass 30, count 0 2006.257.16:54:11.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.16:54:11.70#ibcon#[27=USB\r\n] 2006.257.16:54:11.70#ibcon#*before write, iclass 30, count 0 2006.257.16:54:11.70#ibcon#enter sib2, iclass 30, count 0 2006.257.16:54:11.70#ibcon#flushed, iclass 30, count 0 2006.257.16:54:11.70#ibcon#about to write, iclass 30, count 0 2006.257.16:54:11.70#ibcon#wrote, iclass 30, count 0 2006.257.16:54:11.70#ibcon#about to read 3, iclass 30, count 0 2006.257.16:54:11.73#ibcon#read 3, iclass 30, count 0 2006.257.16:54:11.73#ibcon#about to read 4, iclass 30, count 0 2006.257.16:54:11.73#ibcon#read 4, iclass 30, count 0 2006.257.16:54:11.73#ibcon#about to read 5, iclass 30, count 0 2006.257.16:54:11.73#ibcon#read 5, iclass 30, count 0 2006.257.16:54:11.73#ibcon#about to read 6, iclass 30, count 0 2006.257.16:54:11.73#ibcon#read 6, iclass 30, count 0 2006.257.16:54:11.73#ibcon#end of sib2, iclass 30, count 0 2006.257.16:54:11.73#ibcon#*after write, iclass 30, count 0 2006.257.16:54:11.73#ibcon#*before return 0, iclass 30, count 0 2006.257.16:54:11.73#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:11.73#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.16:54:11.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.16:54:11.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.16:54:11.73$vck44/vblo=3,649.99 2006.257.16:54:11.73#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.16:54:11.73#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.16:54:11.73#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:11.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:11.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:11.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:11.73#ibcon#enter wrdev, iclass 32, count 0 2006.257.16:54:11.73#ibcon#first serial, iclass 32, count 0 2006.257.16:54:11.73#ibcon#enter sib2, iclass 32, count 0 2006.257.16:54:11.73#ibcon#flushed, iclass 32, count 0 2006.257.16:54:11.73#ibcon#about to write, iclass 32, count 0 2006.257.16:54:11.73#ibcon#wrote, iclass 32, count 0 2006.257.16:54:11.73#ibcon#about to read 3, iclass 32, count 0 2006.257.16:54:11.75#ibcon#read 3, iclass 32, count 0 2006.257.16:54:11.75#ibcon#about to read 4, iclass 32, count 0 2006.257.16:54:11.75#ibcon#read 4, iclass 32, count 0 2006.257.16:54:11.75#ibcon#about to read 5, iclass 32, count 0 2006.257.16:54:11.75#ibcon#read 5, iclass 32, count 0 2006.257.16:54:11.75#ibcon#about to read 6, iclass 32, count 0 2006.257.16:54:11.75#ibcon#read 6, iclass 32, count 0 2006.257.16:54:11.75#ibcon#end of sib2, iclass 32, count 0 2006.257.16:54:11.75#ibcon#*mode == 0, iclass 32, count 0 2006.257.16:54:11.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.16:54:11.75#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.16:54:11.75#ibcon#*before write, iclass 32, count 0 2006.257.16:54:11.75#ibcon#enter sib2, iclass 32, count 0 2006.257.16:54:11.75#ibcon#flushed, iclass 32, count 0 2006.257.16:54:11.75#ibcon#about to write, iclass 32, count 0 2006.257.16:54:11.75#ibcon#wrote, iclass 32, count 0 2006.257.16:54:11.75#ibcon#about to read 3, iclass 32, count 0 2006.257.16:54:11.79#ibcon#read 3, iclass 32, count 0 2006.257.16:54:11.79#ibcon#about to read 4, iclass 32, count 0 2006.257.16:54:11.79#ibcon#read 4, iclass 32, count 0 2006.257.16:54:11.79#ibcon#about to read 5, iclass 32, count 0 2006.257.16:54:11.79#ibcon#read 5, iclass 32, count 0 2006.257.16:54:11.79#ibcon#about to read 6, iclass 32, count 0 2006.257.16:54:11.79#ibcon#read 6, iclass 32, count 0 2006.257.16:54:11.79#ibcon#end of sib2, iclass 32, count 0 2006.257.16:54:11.79#ibcon#*after write, iclass 32, count 0 2006.257.16:54:11.79#ibcon#*before return 0, iclass 32, count 0 2006.257.16:54:11.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:11.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.16:54:11.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.16:54:11.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.16:54:11.79$vck44/vb=3,4 2006.257.16:54:11.79#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.16:54:11.79#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.16:54:11.79#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:11.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:11.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:11.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:11.85#ibcon#enter wrdev, iclass 34, count 2 2006.257.16:54:11.85#ibcon#first serial, iclass 34, count 2 2006.257.16:54:11.85#ibcon#enter sib2, iclass 34, count 2 2006.257.16:54:11.85#ibcon#flushed, iclass 34, count 2 2006.257.16:54:11.85#ibcon#about to write, iclass 34, count 2 2006.257.16:54:11.85#ibcon#wrote, iclass 34, count 2 2006.257.16:54:11.85#ibcon#about to read 3, iclass 34, count 2 2006.257.16:54:11.87#ibcon#read 3, iclass 34, count 2 2006.257.16:54:11.87#ibcon#about to read 4, iclass 34, count 2 2006.257.16:54:11.87#ibcon#read 4, iclass 34, count 2 2006.257.16:54:11.87#ibcon#about to read 5, iclass 34, count 2 2006.257.16:54:11.87#ibcon#read 5, iclass 34, count 2 2006.257.16:54:11.87#ibcon#about to read 6, iclass 34, count 2 2006.257.16:54:11.87#ibcon#read 6, iclass 34, count 2 2006.257.16:54:11.87#ibcon#end of sib2, iclass 34, count 2 2006.257.16:54:11.87#ibcon#*mode == 0, iclass 34, count 2 2006.257.16:54:11.87#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.16:54:11.87#ibcon#[27=AT03-04\r\n] 2006.257.16:54:11.87#ibcon#*before write, iclass 34, count 2 2006.257.16:54:11.87#ibcon#enter sib2, iclass 34, count 2 2006.257.16:54:11.87#ibcon#flushed, iclass 34, count 2 2006.257.16:54:11.87#ibcon#about to write, iclass 34, count 2 2006.257.16:54:11.87#ibcon#wrote, iclass 34, count 2 2006.257.16:54:11.87#ibcon#about to read 3, iclass 34, count 2 2006.257.16:54:11.90#ibcon#read 3, iclass 34, count 2 2006.257.16:54:11.90#ibcon#about to read 4, iclass 34, count 2 2006.257.16:54:11.90#ibcon#read 4, iclass 34, count 2 2006.257.16:54:11.90#ibcon#about to read 5, iclass 34, count 2 2006.257.16:54:11.90#ibcon#read 5, iclass 34, count 2 2006.257.16:54:11.90#ibcon#about to read 6, iclass 34, count 2 2006.257.16:54:11.90#ibcon#read 6, iclass 34, count 2 2006.257.16:54:11.90#ibcon#end of sib2, iclass 34, count 2 2006.257.16:54:11.90#ibcon#*after write, iclass 34, count 2 2006.257.16:54:11.90#ibcon#*before return 0, iclass 34, count 2 2006.257.16:54:11.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:11.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.16:54:11.90#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.16:54:11.90#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:11.90#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:12.02#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:12.02#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:12.02#ibcon#enter wrdev, iclass 34, count 0 2006.257.16:54:12.02#ibcon#first serial, iclass 34, count 0 2006.257.16:54:12.02#ibcon#enter sib2, iclass 34, count 0 2006.257.16:54:12.02#ibcon#flushed, iclass 34, count 0 2006.257.16:54:12.02#ibcon#about to write, iclass 34, count 0 2006.257.16:54:12.02#ibcon#wrote, iclass 34, count 0 2006.257.16:54:12.02#ibcon#about to read 3, iclass 34, count 0 2006.257.16:54:12.04#ibcon#read 3, iclass 34, count 0 2006.257.16:54:12.04#ibcon#about to read 4, iclass 34, count 0 2006.257.16:54:12.04#ibcon#read 4, iclass 34, count 0 2006.257.16:54:12.04#ibcon#about to read 5, iclass 34, count 0 2006.257.16:54:12.04#ibcon#read 5, iclass 34, count 0 2006.257.16:54:12.04#ibcon#about to read 6, iclass 34, count 0 2006.257.16:54:12.04#ibcon#read 6, iclass 34, count 0 2006.257.16:54:12.04#ibcon#end of sib2, iclass 34, count 0 2006.257.16:54:12.04#ibcon#*mode == 0, iclass 34, count 0 2006.257.16:54:12.04#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.16:54:12.04#ibcon#[27=USB\r\n] 2006.257.16:54:12.04#ibcon#*before write, iclass 34, count 0 2006.257.16:54:12.04#ibcon#enter sib2, iclass 34, count 0 2006.257.16:54:12.04#ibcon#flushed, iclass 34, count 0 2006.257.16:54:12.04#ibcon#about to write, iclass 34, count 0 2006.257.16:54:12.04#ibcon#wrote, iclass 34, count 0 2006.257.16:54:12.04#ibcon#about to read 3, iclass 34, count 0 2006.257.16:54:12.07#ibcon#read 3, iclass 34, count 0 2006.257.16:54:12.07#ibcon#about to read 4, iclass 34, count 0 2006.257.16:54:12.07#ibcon#read 4, iclass 34, count 0 2006.257.16:54:12.07#ibcon#about to read 5, iclass 34, count 0 2006.257.16:54:12.07#ibcon#read 5, iclass 34, count 0 2006.257.16:54:12.07#ibcon#about to read 6, iclass 34, count 0 2006.257.16:54:12.07#ibcon#read 6, iclass 34, count 0 2006.257.16:54:12.07#ibcon#end of sib2, iclass 34, count 0 2006.257.16:54:12.07#ibcon#*after write, iclass 34, count 0 2006.257.16:54:12.07#ibcon#*before return 0, iclass 34, count 0 2006.257.16:54:12.07#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:12.07#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.16:54:12.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.16:54:12.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.16:54:12.07$vck44/vblo=4,679.99 2006.257.16:54:12.07#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.16:54:12.07#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.16:54:12.07#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:12.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:12.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:12.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:12.07#ibcon#enter wrdev, iclass 36, count 0 2006.257.16:54:12.07#ibcon#first serial, iclass 36, count 0 2006.257.16:54:12.07#ibcon#enter sib2, iclass 36, count 0 2006.257.16:54:12.07#ibcon#flushed, iclass 36, count 0 2006.257.16:54:12.07#ibcon#about to write, iclass 36, count 0 2006.257.16:54:12.07#ibcon#wrote, iclass 36, count 0 2006.257.16:54:12.07#ibcon#about to read 3, iclass 36, count 0 2006.257.16:54:12.09#ibcon#read 3, iclass 36, count 0 2006.257.16:54:12.09#ibcon#about to read 4, iclass 36, count 0 2006.257.16:54:12.09#ibcon#read 4, iclass 36, count 0 2006.257.16:54:12.09#ibcon#about to read 5, iclass 36, count 0 2006.257.16:54:12.09#ibcon#read 5, iclass 36, count 0 2006.257.16:54:12.09#ibcon#about to read 6, iclass 36, count 0 2006.257.16:54:12.09#ibcon#read 6, iclass 36, count 0 2006.257.16:54:12.09#ibcon#end of sib2, iclass 36, count 0 2006.257.16:54:12.09#ibcon#*mode == 0, iclass 36, count 0 2006.257.16:54:12.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.16:54:12.09#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.16:54:12.09#ibcon#*before write, iclass 36, count 0 2006.257.16:54:12.09#ibcon#enter sib2, iclass 36, count 0 2006.257.16:54:12.09#ibcon#flushed, iclass 36, count 0 2006.257.16:54:12.09#ibcon#about to write, iclass 36, count 0 2006.257.16:54:12.09#ibcon#wrote, iclass 36, count 0 2006.257.16:54:12.09#ibcon#about to read 3, iclass 36, count 0 2006.257.16:54:12.13#ibcon#read 3, iclass 36, count 0 2006.257.16:54:12.13#ibcon#about to read 4, iclass 36, count 0 2006.257.16:54:12.13#ibcon#read 4, iclass 36, count 0 2006.257.16:54:12.13#ibcon#about to read 5, iclass 36, count 0 2006.257.16:54:12.13#ibcon#read 5, iclass 36, count 0 2006.257.16:54:12.13#ibcon#about to read 6, iclass 36, count 0 2006.257.16:54:12.13#ibcon#read 6, iclass 36, count 0 2006.257.16:54:12.13#ibcon#end of sib2, iclass 36, count 0 2006.257.16:54:12.13#ibcon#*after write, iclass 36, count 0 2006.257.16:54:12.13#ibcon#*before return 0, iclass 36, count 0 2006.257.16:54:12.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:12.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.16:54:12.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.16:54:12.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.16:54:12.13$vck44/vb=4,5 2006.257.16:54:12.13#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.16:54:12.13#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.16:54:12.13#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:12.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:12.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:12.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:12.19#ibcon#enter wrdev, iclass 38, count 2 2006.257.16:54:12.19#ibcon#first serial, iclass 38, count 2 2006.257.16:54:12.19#ibcon#enter sib2, iclass 38, count 2 2006.257.16:54:12.19#ibcon#flushed, iclass 38, count 2 2006.257.16:54:12.19#ibcon#about to write, iclass 38, count 2 2006.257.16:54:12.19#ibcon#wrote, iclass 38, count 2 2006.257.16:54:12.19#ibcon#about to read 3, iclass 38, count 2 2006.257.16:54:12.21#ibcon#read 3, iclass 38, count 2 2006.257.16:54:12.21#ibcon#about to read 4, iclass 38, count 2 2006.257.16:54:12.21#ibcon#read 4, iclass 38, count 2 2006.257.16:54:12.21#ibcon#about to read 5, iclass 38, count 2 2006.257.16:54:12.21#ibcon#read 5, iclass 38, count 2 2006.257.16:54:12.21#ibcon#about to read 6, iclass 38, count 2 2006.257.16:54:12.21#ibcon#read 6, iclass 38, count 2 2006.257.16:54:12.21#ibcon#end of sib2, iclass 38, count 2 2006.257.16:54:12.21#ibcon#*mode == 0, iclass 38, count 2 2006.257.16:54:12.21#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.16:54:12.21#ibcon#[27=AT04-05\r\n] 2006.257.16:54:12.21#ibcon#*before write, iclass 38, count 2 2006.257.16:54:12.21#ibcon#enter sib2, iclass 38, count 2 2006.257.16:54:12.21#ibcon#flushed, iclass 38, count 2 2006.257.16:54:12.21#ibcon#about to write, iclass 38, count 2 2006.257.16:54:12.21#ibcon#wrote, iclass 38, count 2 2006.257.16:54:12.21#ibcon#about to read 3, iclass 38, count 2 2006.257.16:54:12.24#ibcon#read 3, iclass 38, count 2 2006.257.16:54:12.24#ibcon#about to read 4, iclass 38, count 2 2006.257.16:54:12.24#ibcon#read 4, iclass 38, count 2 2006.257.16:54:12.24#ibcon#about to read 5, iclass 38, count 2 2006.257.16:54:12.24#ibcon#read 5, iclass 38, count 2 2006.257.16:54:12.24#ibcon#about to read 6, iclass 38, count 2 2006.257.16:54:12.24#ibcon#read 6, iclass 38, count 2 2006.257.16:54:12.24#ibcon#end of sib2, iclass 38, count 2 2006.257.16:54:12.24#ibcon#*after write, iclass 38, count 2 2006.257.16:54:12.24#ibcon#*before return 0, iclass 38, count 2 2006.257.16:54:12.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:12.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.16:54:12.24#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.16:54:12.24#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:12.24#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:12.36#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:12.36#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:12.36#ibcon#enter wrdev, iclass 38, count 0 2006.257.16:54:12.36#ibcon#first serial, iclass 38, count 0 2006.257.16:54:12.36#ibcon#enter sib2, iclass 38, count 0 2006.257.16:54:12.36#ibcon#flushed, iclass 38, count 0 2006.257.16:54:12.36#ibcon#about to write, iclass 38, count 0 2006.257.16:54:12.36#ibcon#wrote, iclass 38, count 0 2006.257.16:54:12.36#ibcon#about to read 3, iclass 38, count 0 2006.257.16:54:12.38#ibcon#read 3, iclass 38, count 0 2006.257.16:54:12.38#ibcon#about to read 4, iclass 38, count 0 2006.257.16:54:12.38#ibcon#read 4, iclass 38, count 0 2006.257.16:54:12.38#ibcon#about to read 5, iclass 38, count 0 2006.257.16:54:12.38#ibcon#read 5, iclass 38, count 0 2006.257.16:54:12.38#ibcon#about to read 6, iclass 38, count 0 2006.257.16:54:12.38#ibcon#read 6, iclass 38, count 0 2006.257.16:54:12.38#ibcon#end of sib2, iclass 38, count 0 2006.257.16:54:12.38#ibcon#*mode == 0, iclass 38, count 0 2006.257.16:54:12.38#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.16:54:12.38#ibcon#[27=USB\r\n] 2006.257.16:54:12.38#ibcon#*before write, iclass 38, count 0 2006.257.16:54:12.38#ibcon#enter sib2, iclass 38, count 0 2006.257.16:54:12.38#ibcon#flushed, iclass 38, count 0 2006.257.16:54:12.38#ibcon#about to write, iclass 38, count 0 2006.257.16:54:12.38#ibcon#wrote, iclass 38, count 0 2006.257.16:54:12.38#ibcon#about to read 3, iclass 38, count 0 2006.257.16:54:12.41#ibcon#read 3, iclass 38, count 0 2006.257.16:54:12.41#ibcon#about to read 4, iclass 38, count 0 2006.257.16:54:12.41#ibcon#read 4, iclass 38, count 0 2006.257.16:54:12.41#ibcon#about to read 5, iclass 38, count 0 2006.257.16:54:12.41#ibcon#read 5, iclass 38, count 0 2006.257.16:54:12.41#ibcon#about to read 6, iclass 38, count 0 2006.257.16:54:12.41#ibcon#read 6, iclass 38, count 0 2006.257.16:54:12.41#ibcon#end of sib2, iclass 38, count 0 2006.257.16:54:12.41#ibcon#*after write, iclass 38, count 0 2006.257.16:54:12.41#ibcon#*before return 0, iclass 38, count 0 2006.257.16:54:12.41#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:12.41#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.16:54:12.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.16:54:12.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.16:54:12.41$vck44/vblo=5,709.99 2006.257.16:54:12.41#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.16:54:12.41#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.16:54:12.41#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:12.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:12.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:12.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:12.41#ibcon#enter wrdev, iclass 40, count 0 2006.257.16:54:12.41#ibcon#first serial, iclass 40, count 0 2006.257.16:54:12.41#ibcon#enter sib2, iclass 40, count 0 2006.257.16:54:12.41#ibcon#flushed, iclass 40, count 0 2006.257.16:54:12.41#ibcon#about to write, iclass 40, count 0 2006.257.16:54:12.41#ibcon#wrote, iclass 40, count 0 2006.257.16:54:12.41#ibcon#about to read 3, iclass 40, count 0 2006.257.16:54:12.43#ibcon#read 3, iclass 40, count 0 2006.257.16:54:12.43#ibcon#about to read 4, iclass 40, count 0 2006.257.16:54:12.43#ibcon#read 4, iclass 40, count 0 2006.257.16:54:12.43#ibcon#about to read 5, iclass 40, count 0 2006.257.16:54:12.43#ibcon#read 5, iclass 40, count 0 2006.257.16:54:12.43#ibcon#about to read 6, iclass 40, count 0 2006.257.16:54:12.43#ibcon#read 6, iclass 40, count 0 2006.257.16:54:12.43#ibcon#end of sib2, iclass 40, count 0 2006.257.16:54:12.43#ibcon#*mode == 0, iclass 40, count 0 2006.257.16:54:12.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.16:54:12.43#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.16:54:12.43#ibcon#*before write, iclass 40, count 0 2006.257.16:54:12.43#ibcon#enter sib2, iclass 40, count 0 2006.257.16:54:12.43#ibcon#flushed, iclass 40, count 0 2006.257.16:54:12.43#ibcon#about to write, iclass 40, count 0 2006.257.16:54:12.43#ibcon#wrote, iclass 40, count 0 2006.257.16:54:12.43#ibcon#about to read 3, iclass 40, count 0 2006.257.16:54:12.47#ibcon#read 3, iclass 40, count 0 2006.257.16:54:12.47#ibcon#about to read 4, iclass 40, count 0 2006.257.16:54:12.47#ibcon#read 4, iclass 40, count 0 2006.257.16:54:12.47#ibcon#about to read 5, iclass 40, count 0 2006.257.16:54:12.47#ibcon#read 5, iclass 40, count 0 2006.257.16:54:12.47#ibcon#about to read 6, iclass 40, count 0 2006.257.16:54:12.47#ibcon#read 6, iclass 40, count 0 2006.257.16:54:12.47#ibcon#end of sib2, iclass 40, count 0 2006.257.16:54:12.47#ibcon#*after write, iclass 40, count 0 2006.257.16:54:12.47#ibcon#*before return 0, iclass 40, count 0 2006.257.16:54:12.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:12.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.16:54:12.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.16:54:12.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.16:54:12.47$vck44/vb=5,4 2006.257.16:54:12.47#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.16:54:12.47#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.16:54:12.47#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:12.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:12.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:12.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:12.53#ibcon#enter wrdev, iclass 4, count 2 2006.257.16:54:12.53#ibcon#first serial, iclass 4, count 2 2006.257.16:54:12.53#ibcon#enter sib2, iclass 4, count 2 2006.257.16:54:12.53#ibcon#flushed, iclass 4, count 2 2006.257.16:54:12.53#ibcon#about to write, iclass 4, count 2 2006.257.16:54:12.53#ibcon#wrote, iclass 4, count 2 2006.257.16:54:12.53#ibcon#about to read 3, iclass 4, count 2 2006.257.16:54:12.55#ibcon#read 3, iclass 4, count 2 2006.257.16:54:12.55#ibcon#about to read 4, iclass 4, count 2 2006.257.16:54:12.55#ibcon#read 4, iclass 4, count 2 2006.257.16:54:12.55#ibcon#about to read 5, iclass 4, count 2 2006.257.16:54:12.55#ibcon#read 5, iclass 4, count 2 2006.257.16:54:12.55#ibcon#about to read 6, iclass 4, count 2 2006.257.16:54:12.55#ibcon#read 6, iclass 4, count 2 2006.257.16:54:12.55#ibcon#end of sib2, iclass 4, count 2 2006.257.16:54:12.55#ibcon#*mode == 0, iclass 4, count 2 2006.257.16:54:12.55#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.16:54:12.55#ibcon#[27=AT05-04\r\n] 2006.257.16:54:12.55#ibcon#*before write, iclass 4, count 2 2006.257.16:54:12.55#ibcon#enter sib2, iclass 4, count 2 2006.257.16:54:12.55#ibcon#flushed, iclass 4, count 2 2006.257.16:54:12.55#ibcon#about to write, iclass 4, count 2 2006.257.16:54:12.55#ibcon#wrote, iclass 4, count 2 2006.257.16:54:12.55#ibcon#about to read 3, iclass 4, count 2 2006.257.16:54:12.58#ibcon#read 3, iclass 4, count 2 2006.257.16:54:12.58#ibcon#about to read 4, iclass 4, count 2 2006.257.16:54:12.58#ibcon#read 4, iclass 4, count 2 2006.257.16:54:12.58#ibcon#about to read 5, iclass 4, count 2 2006.257.16:54:12.58#ibcon#read 5, iclass 4, count 2 2006.257.16:54:12.58#ibcon#about to read 6, iclass 4, count 2 2006.257.16:54:12.58#ibcon#read 6, iclass 4, count 2 2006.257.16:54:12.58#ibcon#end of sib2, iclass 4, count 2 2006.257.16:54:12.58#ibcon#*after write, iclass 4, count 2 2006.257.16:54:12.58#ibcon#*before return 0, iclass 4, count 2 2006.257.16:54:12.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:12.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.16:54:12.58#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.16:54:12.58#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:12.58#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:12.70#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:12.70#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:12.70#ibcon#enter wrdev, iclass 4, count 0 2006.257.16:54:12.70#ibcon#first serial, iclass 4, count 0 2006.257.16:54:12.70#ibcon#enter sib2, iclass 4, count 0 2006.257.16:54:12.70#ibcon#flushed, iclass 4, count 0 2006.257.16:54:12.70#ibcon#about to write, iclass 4, count 0 2006.257.16:54:12.70#ibcon#wrote, iclass 4, count 0 2006.257.16:54:12.70#ibcon#about to read 3, iclass 4, count 0 2006.257.16:54:12.72#ibcon#read 3, iclass 4, count 0 2006.257.16:54:12.72#ibcon#about to read 4, iclass 4, count 0 2006.257.16:54:12.72#ibcon#read 4, iclass 4, count 0 2006.257.16:54:12.72#ibcon#about to read 5, iclass 4, count 0 2006.257.16:54:12.72#ibcon#read 5, iclass 4, count 0 2006.257.16:54:12.72#ibcon#about to read 6, iclass 4, count 0 2006.257.16:54:12.72#ibcon#read 6, iclass 4, count 0 2006.257.16:54:12.72#ibcon#end of sib2, iclass 4, count 0 2006.257.16:54:12.72#ibcon#*mode == 0, iclass 4, count 0 2006.257.16:54:12.72#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.16:54:12.72#ibcon#[27=USB\r\n] 2006.257.16:54:12.72#ibcon#*before write, iclass 4, count 0 2006.257.16:54:12.72#ibcon#enter sib2, iclass 4, count 0 2006.257.16:54:12.72#ibcon#flushed, iclass 4, count 0 2006.257.16:54:12.72#ibcon#about to write, iclass 4, count 0 2006.257.16:54:12.72#ibcon#wrote, iclass 4, count 0 2006.257.16:54:12.72#ibcon#about to read 3, iclass 4, count 0 2006.257.16:54:12.75#ibcon#read 3, iclass 4, count 0 2006.257.16:54:12.75#ibcon#about to read 4, iclass 4, count 0 2006.257.16:54:12.75#ibcon#read 4, iclass 4, count 0 2006.257.16:54:12.75#ibcon#about to read 5, iclass 4, count 0 2006.257.16:54:12.75#ibcon#read 5, iclass 4, count 0 2006.257.16:54:12.75#ibcon#about to read 6, iclass 4, count 0 2006.257.16:54:12.75#ibcon#read 6, iclass 4, count 0 2006.257.16:54:12.75#ibcon#end of sib2, iclass 4, count 0 2006.257.16:54:12.75#ibcon#*after write, iclass 4, count 0 2006.257.16:54:12.75#ibcon#*before return 0, iclass 4, count 0 2006.257.16:54:12.75#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:12.75#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.16:54:12.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.16:54:12.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.16:54:12.75$vck44/vblo=6,719.99 2006.257.16:54:12.75#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.16:54:12.75#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.16:54:12.75#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:12.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:12.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:12.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:12.75#ibcon#enter wrdev, iclass 6, count 0 2006.257.16:54:12.75#ibcon#first serial, iclass 6, count 0 2006.257.16:54:12.75#ibcon#enter sib2, iclass 6, count 0 2006.257.16:54:12.75#ibcon#flushed, iclass 6, count 0 2006.257.16:54:12.75#ibcon#about to write, iclass 6, count 0 2006.257.16:54:12.75#ibcon#wrote, iclass 6, count 0 2006.257.16:54:12.75#ibcon#about to read 3, iclass 6, count 0 2006.257.16:54:12.77#ibcon#read 3, iclass 6, count 0 2006.257.16:54:12.77#ibcon#about to read 4, iclass 6, count 0 2006.257.16:54:12.77#ibcon#read 4, iclass 6, count 0 2006.257.16:54:12.77#ibcon#about to read 5, iclass 6, count 0 2006.257.16:54:12.77#ibcon#read 5, iclass 6, count 0 2006.257.16:54:12.77#ibcon#about to read 6, iclass 6, count 0 2006.257.16:54:12.77#ibcon#read 6, iclass 6, count 0 2006.257.16:54:12.77#ibcon#end of sib2, iclass 6, count 0 2006.257.16:54:12.77#ibcon#*mode == 0, iclass 6, count 0 2006.257.16:54:12.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.16:54:12.77#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.16:54:12.77#ibcon#*before write, iclass 6, count 0 2006.257.16:54:12.77#ibcon#enter sib2, iclass 6, count 0 2006.257.16:54:12.77#ibcon#flushed, iclass 6, count 0 2006.257.16:54:12.77#ibcon#about to write, iclass 6, count 0 2006.257.16:54:12.77#ibcon#wrote, iclass 6, count 0 2006.257.16:54:12.77#ibcon#about to read 3, iclass 6, count 0 2006.257.16:54:12.81#ibcon#read 3, iclass 6, count 0 2006.257.16:54:12.81#ibcon#about to read 4, iclass 6, count 0 2006.257.16:54:12.81#ibcon#read 4, iclass 6, count 0 2006.257.16:54:12.81#ibcon#about to read 5, iclass 6, count 0 2006.257.16:54:12.81#ibcon#read 5, iclass 6, count 0 2006.257.16:54:12.81#ibcon#about to read 6, iclass 6, count 0 2006.257.16:54:12.81#ibcon#read 6, iclass 6, count 0 2006.257.16:54:12.81#ibcon#end of sib2, iclass 6, count 0 2006.257.16:54:12.81#ibcon#*after write, iclass 6, count 0 2006.257.16:54:12.81#ibcon#*before return 0, iclass 6, count 0 2006.257.16:54:12.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:12.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.16:54:12.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.16:54:12.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.16:54:12.81$vck44/vb=6,4 2006.257.16:54:12.81#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.16:54:12.81#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.16:54:12.81#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:12.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:12.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:12.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:12.87#ibcon#enter wrdev, iclass 10, count 2 2006.257.16:54:12.87#ibcon#first serial, iclass 10, count 2 2006.257.16:54:12.87#ibcon#enter sib2, iclass 10, count 2 2006.257.16:54:12.87#ibcon#flushed, iclass 10, count 2 2006.257.16:54:12.87#ibcon#about to write, iclass 10, count 2 2006.257.16:54:12.87#ibcon#wrote, iclass 10, count 2 2006.257.16:54:12.87#ibcon#about to read 3, iclass 10, count 2 2006.257.16:54:12.89#ibcon#read 3, iclass 10, count 2 2006.257.16:54:12.89#ibcon#about to read 4, iclass 10, count 2 2006.257.16:54:12.89#ibcon#read 4, iclass 10, count 2 2006.257.16:54:12.89#ibcon#about to read 5, iclass 10, count 2 2006.257.16:54:12.89#ibcon#read 5, iclass 10, count 2 2006.257.16:54:12.89#ibcon#about to read 6, iclass 10, count 2 2006.257.16:54:12.89#ibcon#read 6, iclass 10, count 2 2006.257.16:54:12.89#ibcon#end of sib2, iclass 10, count 2 2006.257.16:54:12.89#ibcon#*mode == 0, iclass 10, count 2 2006.257.16:54:12.89#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.16:54:12.89#ibcon#[27=AT06-04\r\n] 2006.257.16:54:12.89#ibcon#*before write, iclass 10, count 2 2006.257.16:54:12.89#ibcon#enter sib2, iclass 10, count 2 2006.257.16:54:12.89#ibcon#flushed, iclass 10, count 2 2006.257.16:54:12.89#ibcon#about to write, iclass 10, count 2 2006.257.16:54:12.89#ibcon#wrote, iclass 10, count 2 2006.257.16:54:12.89#ibcon#about to read 3, iclass 10, count 2 2006.257.16:54:12.92#ibcon#read 3, iclass 10, count 2 2006.257.16:54:12.92#ibcon#about to read 4, iclass 10, count 2 2006.257.16:54:12.92#ibcon#read 4, iclass 10, count 2 2006.257.16:54:12.92#ibcon#about to read 5, iclass 10, count 2 2006.257.16:54:12.92#ibcon#read 5, iclass 10, count 2 2006.257.16:54:12.92#ibcon#about to read 6, iclass 10, count 2 2006.257.16:54:12.92#ibcon#read 6, iclass 10, count 2 2006.257.16:54:12.92#ibcon#end of sib2, iclass 10, count 2 2006.257.16:54:12.92#ibcon#*after write, iclass 10, count 2 2006.257.16:54:12.92#ibcon#*before return 0, iclass 10, count 2 2006.257.16:54:12.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:12.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.16:54:12.92#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.16:54:12.92#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:12.92#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:13.04#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:13.04#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:13.04#ibcon#enter wrdev, iclass 10, count 0 2006.257.16:54:13.04#ibcon#first serial, iclass 10, count 0 2006.257.16:54:13.04#ibcon#enter sib2, iclass 10, count 0 2006.257.16:54:13.04#ibcon#flushed, iclass 10, count 0 2006.257.16:54:13.04#ibcon#about to write, iclass 10, count 0 2006.257.16:54:13.04#ibcon#wrote, iclass 10, count 0 2006.257.16:54:13.04#ibcon#about to read 3, iclass 10, count 0 2006.257.16:54:13.06#ibcon#read 3, iclass 10, count 0 2006.257.16:54:13.06#ibcon#about to read 4, iclass 10, count 0 2006.257.16:54:13.06#ibcon#read 4, iclass 10, count 0 2006.257.16:54:13.06#ibcon#about to read 5, iclass 10, count 0 2006.257.16:54:13.06#ibcon#read 5, iclass 10, count 0 2006.257.16:54:13.06#ibcon#about to read 6, iclass 10, count 0 2006.257.16:54:13.06#ibcon#read 6, iclass 10, count 0 2006.257.16:54:13.06#ibcon#end of sib2, iclass 10, count 0 2006.257.16:54:13.06#ibcon#*mode == 0, iclass 10, count 0 2006.257.16:54:13.06#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.16:54:13.06#ibcon#[27=USB\r\n] 2006.257.16:54:13.06#ibcon#*before write, iclass 10, count 0 2006.257.16:54:13.06#ibcon#enter sib2, iclass 10, count 0 2006.257.16:54:13.06#ibcon#flushed, iclass 10, count 0 2006.257.16:54:13.06#ibcon#about to write, iclass 10, count 0 2006.257.16:54:13.06#ibcon#wrote, iclass 10, count 0 2006.257.16:54:13.06#ibcon#about to read 3, iclass 10, count 0 2006.257.16:54:13.09#ibcon#read 3, iclass 10, count 0 2006.257.16:54:13.09#ibcon#about to read 4, iclass 10, count 0 2006.257.16:54:13.09#ibcon#read 4, iclass 10, count 0 2006.257.16:54:13.09#ibcon#about to read 5, iclass 10, count 0 2006.257.16:54:13.09#ibcon#read 5, iclass 10, count 0 2006.257.16:54:13.09#ibcon#about to read 6, iclass 10, count 0 2006.257.16:54:13.09#ibcon#read 6, iclass 10, count 0 2006.257.16:54:13.09#ibcon#end of sib2, iclass 10, count 0 2006.257.16:54:13.09#ibcon#*after write, iclass 10, count 0 2006.257.16:54:13.09#ibcon#*before return 0, iclass 10, count 0 2006.257.16:54:13.09#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:13.09#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.16:54:13.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.16:54:13.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.16:54:13.09$vck44/vblo=7,734.99 2006.257.16:54:13.09#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.16:54:13.09#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.16:54:13.09#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:13.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:13.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:13.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:13.09#ibcon#enter wrdev, iclass 12, count 0 2006.257.16:54:13.09#ibcon#first serial, iclass 12, count 0 2006.257.16:54:13.09#ibcon#enter sib2, iclass 12, count 0 2006.257.16:54:13.09#ibcon#flushed, iclass 12, count 0 2006.257.16:54:13.09#ibcon#about to write, iclass 12, count 0 2006.257.16:54:13.09#ibcon#wrote, iclass 12, count 0 2006.257.16:54:13.09#ibcon#about to read 3, iclass 12, count 0 2006.257.16:54:13.11#ibcon#read 3, iclass 12, count 0 2006.257.16:54:13.11#ibcon#about to read 4, iclass 12, count 0 2006.257.16:54:13.11#ibcon#read 4, iclass 12, count 0 2006.257.16:54:13.11#ibcon#about to read 5, iclass 12, count 0 2006.257.16:54:13.11#ibcon#read 5, iclass 12, count 0 2006.257.16:54:13.11#ibcon#about to read 6, iclass 12, count 0 2006.257.16:54:13.11#ibcon#read 6, iclass 12, count 0 2006.257.16:54:13.11#ibcon#end of sib2, iclass 12, count 0 2006.257.16:54:13.11#ibcon#*mode == 0, iclass 12, count 0 2006.257.16:54:13.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.16:54:13.11#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.16:54:13.11#ibcon#*before write, iclass 12, count 0 2006.257.16:54:13.11#ibcon#enter sib2, iclass 12, count 0 2006.257.16:54:13.11#ibcon#flushed, iclass 12, count 0 2006.257.16:54:13.11#ibcon#about to write, iclass 12, count 0 2006.257.16:54:13.11#ibcon#wrote, iclass 12, count 0 2006.257.16:54:13.11#ibcon#about to read 3, iclass 12, count 0 2006.257.16:54:13.15#ibcon#read 3, iclass 12, count 0 2006.257.16:54:13.15#ibcon#about to read 4, iclass 12, count 0 2006.257.16:54:13.15#ibcon#read 4, iclass 12, count 0 2006.257.16:54:13.15#ibcon#about to read 5, iclass 12, count 0 2006.257.16:54:13.15#ibcon#read 5, iclass 12, count 0 2006.257.16:54:13.15#ibcon#about to read 6, iclass 12, count 0 2006.257.16:54:13.15#ibcon#read 6, iclass 12, count 0 2006.257.16:54:13.15#ibcon#end of sib2, iclass 12, count 0 2006.257.16:54:13.15#ibcon#*after write, iclass 12, count 0 2006.257.16:54:13.15#ibcon#*before return 0, iclass 12, count 0 2006.257.16:54:13.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:13.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.16:54:13.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.16:54:13.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.16:54:13.15$vck44/vb=7,4 2006.257.16:54:13.15#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.16:54:13.15#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.16:54:13.15#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:13.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:13.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:13.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:13.21#ibcon#enter wrdev, iclass 14, count 2 2006.257.16:54:13.21#ibcon#first serial, iclass 14, count 2 2006.257.16:54:13.21#ibcon#enter sib2, iclass 14, count 2 2006.257.16:54:13.21#ibcon#flushed, iclass 14, count 2 2006.257.16:54:13.21#ibcon#about to write, iclass 14, count 2 2006.257.16:54:13.21#ibcon#wrote, iclass 14, count 2 2006.257.16:54:13.21#ibcon#about to read 3, iclass 14, count 2 2006.257.16:54:13.23#ibcon#read 3, iclass 14, count 2 2006.257.16:54:13.23#ibcon#about to read 4, iclass 14, count 2 2006.257.16:54:13.23#ibcon#read 4, iclass 14, count 2 2006.257.16:54:13.23#ibcon#about to read 5, iclass 14, count 2 2006.257.16:54:13.23#ibcon#read 5, iclass 14, count 2 2006.257.16:54:13.23#ibcon#about to read 6, iclass 14, count 2 2006.257.16:54:13.23#ibcon#read 6, iclass 14, count 2 2006.257.16:54:13.23#ibcon#end of sib2, iclass 14, count 2 2006.257.16:54:13.23#ibcon#*mode == 0, iclass 14, count 2 2006.257.16:54:13.23#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.16:54:13.23#ibcon#[27=AT07-04\r\n] 2006.257.16:54:13.23#ibcon#*before write, iclass 14, count 2 2006.257.16:54:13.23#ibcon#enter sib2, iclass 14, count 2 2006.257.16:54:13.23#ibcon#flushed, iclass 14, count 2 2006.257.16:54:13.23#ibcon#about to write, iclass 14, count 2 2006.257.16:54:13.23#ibcon#wrote, iclass 14, count 2 2006.257.16:54:13.23#ibcon#about to read 3, iclass 14, count 2 2006.257.16:54:13.26#ibcon#read 3, iclass 14, count 2 2006.257.16:54:13.26#ibcon#about to read 4, iclass 14, count 2 2006.257.16:54:13.26#ibcon#read 4, iclass 14, count 2 2006.257.16:54:13.26#ibcon#about to read 5, iclass 14, count 2 2006.257.16:54:13.26#ibcon#read 5, iclass 14, count 2 2006.257.16:54:13.26#ibcon#about to read 6, iclass 14, count 2 2006.257.16:54:13.26#ibcon#read 6, iclass 14, count 2 2006.257.16:54:13.26#ibcon#end of sib2, iclass 14, count 2 2006.257.16:54:13.26#ibcon#*after write, iclass 14, count 2 2006.257.16:54:13.26#ibcon#*before return 0, iclass 14, count 2 2006.257.16:54:13.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:13.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.16:54:13.26#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.16:54:13.26#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:13.26#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:13.38#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:13.38#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:13.38#ibcon#enter wrdev, iclass 14, count 0 2006.257.16:54:13.38#ibcon#first serial, iclass 14, count 0 2006.257.16:54:13.38#ibcon#enter sib2, iclass 14, count 0 2006.257.16:54:13.38#ibcon#flushed, iclass 14, count 0 2006.257.16:54:13.38#ibcon#about to write, iclass 14, count 0 2006.257.16:54:13.38#ibcon#wrote, iclass 14, count 0 2006.257.16:54:13.38#ibcon#about to read 3, iclass 14, count 0 2006.257.16:54:13.40#ibcon#read 3, iclass 14, count 0 2006.257.16:54:13.40#ibcon#about to read 4, iclass 14, count 0 2006.257.16:54:13.40#ibcon#read 4, iclass 14, count 0 2006.257.16:54:13.40#ibcon#about to read 5, iclass 14, count 0 2006.257.16:54:13.40#ibcon#read 5, iclass 14, count 0 2006.257.16:54:13.40#ibcon#about to read 6, iclass 14, count 0 2006.257.16:54:13.40#ibcon#read 6, iclass 14, count 0 2006.257.16:54:13.40#ibcon#end of sib2, iclass 14, count 0 2006.257.16:54:13.40#ibcon#*mode == 0, iclass 14, count 0 2006.257.16:54:13.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.16:54:13.40#ibcon#[27=USB\r\n] 2006.257.16:54:13.40#ibcon#*before write, iclass 14, count 0 2006.257.16:54:13.40#ibcon#enter sib2, iclass 14, count 0 2006.257.16:54:13.40#ibcon#flushed, iclass 14, count 0 2006.257.16:54:13.40#ibcon#about to write, iclass 14, count 0 2006.257.16:54:13.40#ibcon#wrote, iclass 14, count 0 2006.257.16:54:13.40#ibcon#about to read 3, iclass 14, count 0 2006.257.16:54:13.43#ibcon#read 3, iclass 14, count 0 2006.257.16:54:13.43#ibcon#about to read 4, iclass 14, count 0 2006.257.16:54:13.43#ibcon#read 4, iclass 14, count 0 2006.257.16:54:13.43#ibcon#about to read 5, iclass 14, count 0 2006.257.16:54:13.43#ibcon#read 5, iclass 14, count 0 2006.257.16:54:13.43#ibcon#about to read 6, iclass 14, count 0 2006.257.16:54:13.43#ibcon#read 6, iclass 14, count 0 2006.257.16:54:13.43#ibcon#end of sib2, iclass 14, count 0 2006.257.16:54:13.43#ibcon#*after write, iclass 14, count 0 2006.257.16:54:13.43#ibcon#*before return 0, iclass 14, count 0 2006.257.16:54:13.43#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:13.43#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.16:54:13.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.16:54:13.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.16:54:13.43$vck44/vblo=8,744.99 2006.257.16:54:13.43#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.16:54:13.43#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.16:54:13.43#ibcon#ireg 17 cls_cnt 0 2006.257.16:54:13.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:13.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:13.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:13.43#ibcon#enter wrdev, iclass 16, count 0 2006.257.16:54:13.43#ibcon#first serial, iclass 16, count 0 2006.257.16:54:13.43#ibcon#enter sib2, iclass 16, count 0 2006.257.16:54:13.43#ibcon#flushed, iclass 16, count 0 2006.257.16:54:13.43#ibcon#about to write, iclass 16, count 0 2006.257.16:54:13.43#ibcon#wrote, iclass 16, count 0 2006.257.16:54:13.43#ibcon#about to read 3, iclass 16, count 0 2006.257.16:54:13.45#ibcon#read 3, iclass 16, count 0 2006.257.16:54:13.45#ibcon#about to read 4, iclass 16, count 0 2006.257.16:54:13.45#ibcon#read 4, iclass 16, count 0 2006.257.16:54:13.45#ibcon#about to read 5, iclass 16, count 0 2006.257.16:54:13.45#ibcon#read 5, iclass 16, count 0 2006.257.16:54:13.45#ibcon#about to read 6, iclass 16, count 0 2006.257.16:54:13.45#ibcon#read 6, iclass 16, count 0 2006.257.16:54:13.45#ibcon#end of sib2, iclass 16, count 0 2006.257.16:54:13.45#ibcon#*mode == 0, iclass 16, count 0 2006.257.16:54:13.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.16:54:13.45#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.16:54:13.45#ibcon#*before write, iclass 16, count 0 2006.257.16:54:13.45#ibcon#enter sib2, iclass 16, count 0 2006.257.16:54:13.45#ibcon#flushed, iclass 16, count 0 2006.257.16:54:13.45#ibcon#about to write, iclass 16, count 0 2006.257.16:54:13.45#ibcon#wrote, iclass 16, count 0 2006.257.16:54:13.45#ibcon#about to read 3, iclass 16, count 0 2006.257.16:54:13.49#ibcon#read 3, iclass 16, count 0 2006.257.16:54:13.49#ibcon#about to read 4, iclass 16, count 0 2006.257.16:54:13.49#ibcon#read 4, iclass 16, count 0 2006.257.16:54:13.49#ibcon#about to read 5, iclass 16, count 0 2006.257.16:54:13.49#ibcon#read 5, iclass 16, count 0 2006.257.16:54:13.49#ibcon#about to read 6, iclass 16, count 0 2006.257.16:54:13.49#ibcon#read 6, iclass 16, count 0 2006.257.16:54:13.49#ibcon#end of sib2, iclass 16, count 0 2006.257.16:54:13.49#ibcon#*after write, iclass 16, count 0 2006.257.16:54:13.49#ibcon#*before return 0, iclass 16, count 0 2006.257.16:54:13.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:13.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.16:54:13.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.16:54:13.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.16:54:13.49$vck44/vb=8,4 2006.257.16:54:13.49#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.16:54:13.49#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.16:54:13.49#ibcon#ireg 11 cls_cnt 2 2006.257.16:54:13.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:13.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:13.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:13.55#ibcon#enter wrdev, iclass 18, count 2 2006.257.16:54:13.55#ibcon#first serial, iclass 18, count 2 2006.257.16:54:13.55#ibcon#enter sib2, iclass 18, count 2 2006.257.16:54:13.55#ibcon#flushed, iclass 18, count 2 2006.257.16:54:13.55#ibcon#about to write, iclass 18, count 2 2006.257.16:54:13.55#ibcon#wrote, iclass 18, count 2 2006.257.16:54:13.55#ibcon#about to read 3, iclass 18, count 2 2006.257.16:54:13.57#ibcon#read 3, iclass 18, count 2 2006.257.16:54:13.57#ibcon#about to read 4, iclass 18, count 2 2006.257.16:54:13.57#ibcon#read 4, iclass 18, count 2 2006.257.16:54:13.57#ibcon#about to read 5, iclass 18, count 2 2006.257.16:54:13.57#ibcon#read 5, iclass 18, count 2 2006.257.16:54:13.57#ibcon#about to read 6, iclass 18, count 2 2006.257.16:54:13.57#ibcon#read 6, iclass 18, count 2 2006.257.16:54:13.57#ibcon#end of sib2, iclass 18, count 2 2006.257.16:54:13.57#ibcon#*mode == 0, iclass 18, count 2 2006.257.16:54:13.57#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.16:54:13.57#ibcon#[27=AT08-04\r\n] 2006.257.16:54:13.57#ibcon#*before write, iclass 18, count 2 2006.257.16:54:13.57#ibcon#enter sib2, iclass 18, count 2 2006.257.16:54:13.57#ibcon#flushed, iclass 18, count 2 2006.257.16:54:13.57#ibcon#about to write, iclass 18, count 2 2006.257.16:54:13.57#ibcon#wrote, iclass 18, count 2 2006.257.16:54:13.57#ibcon#about to read 3, iclass 18, count 2 2006.257.16:54:13.60#ibcon#read 3, iclass 18, count 2 2006.257.16:54:13.60#ibcon#about to read 4, iclass 18, count 2 2006.257.16:54:13.60#ibcon#read 4, iclass 18, count 2 2006.257.16:54:13.60#ibcon#about to read 5, iclass 18, count 2 2006.257.16:54:13.60#ibcon#read 5, iclass 18, count 2 2006.257.16:54:13.60#ibcon#about to read 6, iclass 18, count 2 2006.257.16:54:13.60#ibcon#read 6, iclass 18, count 2 2006.257.16:54:13.60#ibcon#end of sib2, iclass 18, count 2 2006.257.16:54:13.60#ibcon#*after write, iclass 18, count 2 2006.257.16:54:13.60#ibcon#*before return 0, iclass 18, count 2 2006.257.16:54:13.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:13.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.16:54:13.60#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.16:54:13.60#ibcon#ireg 7 cls_cnt 0 2006.257.16:54:13.60#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:13.72#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:13.72#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:13.72#ibcon#enter wrdev, iclass 18, count 0 2006.257.16:54:13.72#ibcon#first serial, iclass 18, count 0 2006.257.16:54:13.72#ibcon#enter sib2, iclass 18, count 0 2006.257.16:54:13.72#ibcon#flushed, iclass 18, count 0 2006.257.16:54:13.72#ibcon#about to write, iclass 18, count 0 2006.257.16:54:13.72#ibcon#wrote, iclass 18, count 0 2006.257.16:54:13.72#ibcon#about to read 3, iclass 18, count 0 2006.257.16:54:13.74#ibcon#read 3, iclass 18, count 0 2006.257.16:54:13.74#ibcon#about to read 4, iclass 18, count 0 2006.257.16:54:13.74#ibcon#read 4, iclass 18, count 0 2006.257.16:54:13.74#ibcon#about to read 5, iclass 18, count 0 2006.257.16:54:13.74#ibcon#read 5, iclass 18, count 0 2006.257.16:54:13.74#ibcon#about to read 6, iclass 18, count 0 2006.257.16:54:13.74#ibcon#read 6, iclass 18, count 0 2006.257.16:54:13.74#ibcon#end of sib2, iclass 18, count 0 2006.257.16:54:13.74#ibcon#*mode == 0, iclass 18, count 0 2006.257.16:54:13.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.16:54:13.74#ibcon#[27=USB\r\n] 2006.257.16:54:13.74#ibcon#*before write, iclass 18, count 0 2006.257.16:54:13.74#ibcon#enter sib2, iclass 18, count 0 2006.257.16:54:13.74#ibcon#flushed, iclass 18, count 0 2006.257.16:54:13.74#ibcon#about to write, iclass 18, count 0 2006.257.16:54:13.74#ibcon#wrote, iclass 18, count 0 2006.257.16:54:13.74#ibcon#about to read 3, iclass 18, count 0 2006.257.16:54:13.77#ibcon#read 3, iclass 18, count 0 2006.257.16:54:13.77#ibcon#about to read 4, iclass 18, count 0 2006.257.16:54:13.77#ibcon#read 4, iclass 18, count 0 2006.257.16:54:13.77#ibcon#about to read 5, iclass 18, count 0 2006.257.16:54:13.77#ibcon#read 5, iclass 18, count 0 2006.257.16:54:13.77#ibcon#about to read 6, iclass 18, count 0 2006.257.16:54:13.77#ibcon#read 6, iclass 18, count 0 2006.257.16:54:13.77#ibcon#end of sib2, iclass 18, count 0 2006.257.16:54:13.77#ibcon#*after write, iclass 18, count 0 2006.257.16:54:13.77#ibcon#*before return 0, iclass 18, count 0 2006.257.16:54:13.77#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:13.77#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.16:54:13.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.16:54:13.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.16:54:13.77$vck44/vabw=wide 2006.257.16:54:13.77#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.16:54:13.77#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.16:54:13.77#ibcon#ireg 8 cls_cnt 0 2006.257.16:54:13.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:13.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:13.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:13.77#ibcon#enter wrdev, iclass 20, count 0 2006.257.16:54:13.77#ibcon#first serial, iclass 20, count 0 2006.257.16:54:13.77#ibcon#enter sib2, iclass 20, count 0 2006.257.16:54:13.77#ibcon#flushed, iclass 20, count 0 2006.257.16:54:13.77#ibcon#about to write, iclass 20, count 0 2006.257.16:54:13.77#ibcon#wrote, iclass 20, count 0 2006.257.16:54:13.77#ibcon#about to read 3, iclass 20, count 0 2006.257.16:54:13.79#ibcon#read 3, iclass 20, count 0 2006.257.16:54:13.79#ibcon#about to read 4, iclass 20, count 0 2006.257.16:54:13.79#ibcon#read 4, iclass 20, count 0 2006.257.16:54:13.79#ibcon#about to read 5, iclass 20, count 0 2006.257.16:54:13.79#ibcon#read 5, iclass 20, count 0 2006.257.16:54:13.79#ibcon#about to read 6, iclass 20, count 0 2006.257.16:54:13.79#ibcon#read 6, iclass 20, count 0 2006.257.16:54:13.79#ibcon#end of sib2, iclass 20, count 0 2006.257.16:54:13.79#ibcon#*mode == 0, iclass 20, count 0 2006.257.16:54:13.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.16:54:13.79#ibcon#[25=BW32\r\n] 2006.257.16:54:13.79#ibcon#*before write, iclass 20, count 0 2006.257.16:54:13.79#ibcon#enter sib2, iclass 20, count 0 2006.257.16:54:13.79#ibcon#flushed, iclass 20, count 0 2006.257.16:54:13.79#ibcon#about to write, iclass 20, count 0 2006.257.16:54:13.79#ibcon#wrote, iclass 20, count 0 2006.257.16:54:13.79#ibcon#about to read 3, iclass 20, count 0 2006.257.16:54:13.82#ibcon#read 3, iclass 20, count 0 2006.257.16:54:13.82#ibcon#about to read 4, iclass 20, count 0 2006.257.16:54:13.82#ibcon#read 4, iclass 20, count 0 2006.257.16:54:13.82#ibcon#about to read 5, iclass 20, count 0 2006.257.16:54:13.82#ibcon#read 5, iclass 20, count 0 2006.257.16:54:13.82#ibcon#about to read 6, iclass 20, count 0 2006.257.16:54:13.82#ibcon#read 6, iclass 20, count 0 2006.257.16:54:13.82#ibcon#end of sib2, iclass 20, count 0 2006.257.16:54:13.82#ibcon#*after write, iclass 20, count 0 2006.257.16:54:13.82#ibcon#*before return 0, iclass 20, count 0 2006.257.16:54:13.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:13.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.16:54:13.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.16:54:13.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.16:54:13.82$vck44/vbbw=wide 2006.257.16:54:13.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.16:54:13.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.16:54:13.82#ibcon#ireg 8 cls_cnt 0 2006.257.16:54:13.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:54:13.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:54:13.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:54:13.89#ibcon#enter wrdev, iclass 22, count 0 2006.257.16:54:13.89#ibcon#first serial, iclass 22, count 0 2006.257.16:54:13.89#ibcon#enter sib2, iclass 22, count 0 2006.257.16:54:13.89#ibcon#flushed, iclass 22, count 0 2006.257.16:54:13.89#ibcon#about to write, iclass 22, count 0 2006.257.16:54:13.89#ibcon#wrote, iclass 22, count 0 2006.257.16:54:13.89#ibcon#about to read 3, iclass 22, count 0 2006.257.16:54:13.91#ibcon#read 3, iclass 22, count 0 2006.257.16:54:13.91#ibcon#about to read 4, iclass 22, count 0 2006.257.16:54:13.91#ibcon#read 4, iclass 22, count 0 2006.257.16:54:13.91#ibcon#about to read 5, iclass 22, count 0 2006.257.16:54:13.91#ibcon#read 5, iclass 22, count 0 2006.257.16:54:13.91#ibcon#about to read 6, iclass 22, count 0 2006.257.16:54:13.91#ibcon#read 6, iclass 22, count 0 2006.257.16:54:13.91#ibcon#end of sib2, iclass 22, count 0 2006.257.16:54:13.91#ibcon#*mode == 0, iclass 22, count 0 2006.257.16:54:13.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.16:54:13.91#ibcon#[27=BW32\r\n] 2006.257.16:54:13.91#ibcon#*before write, iclass 22, count 0 2006.257.16:54:13.91#ibcon#enter sib2, iclass 22, count 0 2006.257.16:54:13.91#ibcon#flushed, iclass 22, count 0 2006.257.16:54:13.91#ibcon#about to write, iclass 22, count 0 2006.257.16:54:13.91#ibcon#wrote, iclass 22, count 0 2006.257.16:54:13.91#ibcon#about to read 3, iclass 22, count 0 2006.257.16:54:13.94#ibcon#read 3, iclass 22, count 0 2006.257.16:54:13.94#ibcon#about to read 4, iclass 22, count 0 2006.257.16:54:13.94#ibcon#read 4, iclass 22, count 0 2006.257.16:54:13.94#ibcon#about to read 5, iclass 22, count 0 2006.257.16:54:13.94#ibcon#read 5, iclass 22, count 0 2006.257.16:54:13.94#ibcon#about to read 6, iclass 22, count 0 2006.257.16:54:13.94#ibcon#read 6, iclass 22, count 0 2006.257.16:54:13.94#ibcon#end of sib2, iclass 22, count 0 2006.257.16:54:13.94#ibcon#*after write, iclass 22, count 0 2006.257.16:54:13.94#ibcon#*before return 0, iclass 22, count 0 2006.257.16:54:13.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:54:13.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.16:54:13.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.16:54:13.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.16:54:13.94$setupk4/ifdk4 2006.257.16:54:13.94$ifdk4/lo= 2006.257.16:54:13.94$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.16:54:13.95$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.16:54:13.95$ifdk4/patch= 2006.257.16:54:13.95$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.16:54:13.95$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.16:54:13.95$setupk4/!*+20s 2006.257.16:54:14.77#abcon#<5=/14 1.7 4.9 17.34 961014.2\r\n> 2006.257.16:54:14.79#abcon#{5=INTERFACE CLEAR} 2006.257.16:54:14.85#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:54:24.94#abcon#<5=/14 1.7 4.9 17.34 961014.2\r\n> 2006.257.16:54:24.96#abcon#{5=INTERFACE CLEAR} 2006.257.16:54:25.02#abcon#[5=S1D000X0/0*\r\n] 2006.257.16:54:28.50$setupk4/"tpicd 2006.257.16:54:28.50$setupk4/echo=off 2006.257.16:54:28.50$setupk4/xlog=off 2006.257.16:54:28.50:!2006.257.17:00:32 2006.257.16:55:19.14#trakl#Source acquired 2006.257.16:55:19.14#flagr#flagr/antenna,acquired 2006.257.17:00:32.00:preob 2006.257.17:00:32.14/onsource/TRACKING 2006.257.17:00:32.14:!2006.257.17:00:42 2006.257.17:00:42.00:"tape 2006.257.17:00:42.00:"st=record 2006.257.17:00:42.00:data_valid=on 2006.257.17:00:42.00:midob 2006.257.17:00:43.14/onsource/TRACKING 2006.257.17:00:43.14/wx/17.35,1014.2,96 2006.257.17:00:43.20/cable/+6.4836E-03 2006.257.17:00:44.29/va/01,08,usb,yes,30,33 2006.257.17:00:44.29/va/02,07,usb,yes,33,33 2006.257.17:00:44.29/va/03,08,usb,yes,29,31 2006.257.17:00:44.29/va/04,07,usb,yes,34,35 2006.257.17:00:44.29/va/05,04,usb,yes,30,31 2006.257.17:00:44.29/va/06,04,usb,yes,34,33 2006.257.17:00:44.29/va/07,04,usb,yes,35,35 2006.257.17:00:44.29/va/08,04,usb,yes,29,35 2006.257.17:00:44.52/valo/01,524.99,yes,locked 2006.257.17:00:44.52/valo/02,534.99,yes,locked 2006.257.17:00:44.52/valo/03,564.99,yes,locked 2006.257.17:00:44.52/valo/04,624.99,yes,locked 2006.257.17:00:44.52/valo/05,734.99,yes,locked 2006.257.17:00:44.52/valo/06,814.99,yes,locked 2006.257.17:00:44.52/valo/07,864.99,yes,locked 2006.257.17:00:44.52/valo/08,884.99,yes,locked 2006.257.17:00:45.61/vb/01,04,usb,yes,30,28 2006.257.17:00:45.61/vb/02,05,usb,yes,29,29 2006.257.17:00:45.61/vb/03,04,usb,yes,30,33 2006.257.17:00:45.61/vb/04,05,usb,yes,30,29 2006.257.17:00:45.61/vb/05,04,usb,yes,26,29 2006.257.17:00:45.61/vb/06,04,usb,yes,31,27 2006.257.17:00:45.61/vb/07,04,usb,yes,31,31 2006.257.17:00:45.61/vb/08,04,usb,yes,28,32 2006.257.17:00:45.84/vblo/01,629.99,yes,locked 2006.257.17:00:45.84/vblo/02,634.99,yes,locked 2006.257.17:00:45.84/vblo/03,649.99,yes,locked 2006.257.17:00:45.84/vblo/04,679.99,yes,locked 2006.257.17:00:45.84/vblo/05,709.99,yes,locked 2006.257.17:00:45.84/vblo/06,719.99,yes,locked 2006.257.17:00:45.84/vblo/07,734.99,yes,locked 2006.257.17:00:45.84/vblo/08,744.99,yes,locked 2006.257.17:00:45.99/vabw/8 2006.257.17:00:46.14/vbbw/8 2006.257.17:00:46.23/xfe/off,on,15.2 2006.257.17:00:46.60/ifatt/23,28,28,28 2006.257.17:00:47.07/fmout-gps/S +4.55E-07 2006.257.17:00:47.11:!2006.257.17:01:32 2006.257.17:01:32.01:data_valid=off 2006.257.17:01:32.01:"et 2006.257.17:01:32.01:!+3s 2006.257.17:01:35.02:"tape 2006.257.17:01:35.02:postob 2006.257.17:01:35.11/cable/+6.4839E-03 2006.257.17:01:35.11/wx/17.35,1014.2,96 2006.257.17:01:35.17/fmout-gps/S +4.55E-07 2006.257.17:01:35.17:scan_name=257-1704,jd0609,90 2006.257.17:01:35.17:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.257.17:01:36.13#flagr#flagr/antenna,new-source 2006.257.17:01:36.13:checkk5 2006.257.17:01:36.46/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:01:36.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:01:37.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:01:37.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:01:37.83/chk_obsdata//k5ts1/T2571700??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.17:01:38.16/chk_obsdata//k5ts2/T2571700??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.17:01:38.49/chk_obsdata//k5ts3/T2571700??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.17:01:38.82/chk_obsdata//k5ts4/T2571700??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.17:01:39.47/k5log//k5ts1_log_newline 2006.257.17:01:40.12/k5log//k5ts2_log_newline 2006.257.17:01:40.78/k5log//k5ts3_log_newline 2006.257.17:01:41.43/k5log//k5ts4_log_newline 2006.257.17:01:41.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:01:41.45:setupk4=1 2006.257.17:01:41.45$setupk4/echo=on 2006.257.17:01:41.45$setupk4/pcalon 2006.257.17:01:41.45$pcalon/"no phase cal control is implemented here 2006.257.17:01:41.45$setupk4/"tpicd=stop 2006.257.17:01:41.45$setupk4/"rec=synch_on 2006.257.17:01:41.45$setupk4/"rec_mode=128 2006.257.17:01:41.46$setupk4/!* 2006.257.17:01:41.46$setupk4/recpk4 2006.257.17:01:41.46$recpk4/recpatch= 2006.257.17:01:41.46$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:01:41.46$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:01:41.46$setupk4/vck44 2006.257.17:01:41.46$vck44/valo=1,524.99 2006.257.17:01:41.46#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.17:01:41.46#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.17:01:41.46#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:41.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:41.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:41.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:41.46#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:01:41.46#ibcon#first serial, iclass 23, count 0 2006.257.17:01:41.46#ibcon#enter sib2, iclass 23, count 0 2006.257.17:01:41.46#ibcon#flushed, iclass 23, count 0 2006.257.17:01:41.46#ibcon#about to write, iclass 23, count 0 2006.257.17:01:41.46#ibcon#wrote, iclass 23, count 0 2006.257.17:01:41.46#ibcon#about to read 3, iclass 23, count 0 2006.257.17:01:41.47#ibcon#read 3, iclass 23, count 0 2006.257.17:01:41.47#ibcon#about to read 4, iclass 23, count 0 2006.257.17:01:41.47#ibcon#read 4, iclass 23, count 0 2006.257.17:01:41.47#ibcon#about to read 5, iclass 23, count 0 2006.257.17:01:41.47#ibcon#read 5, iclass 23, count 0 2006.257.17:01:41.47#ibcon#about to read 6, iclass 23, count 0 2006.257.17:01:41.47#ibcon#read 6, iclass 23, count 0 2006.257.17:01:41.47#ibcon#end of sib2, iclass 23, count 0 2006.257.17:01:41.47#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:01:41.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:01:41.47#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:01:41.47#ibcon#*before write, iclass 23, count 0 2006.257.17:01:41.47#ibcon#enter sib2, iclass 23, count 0 2006.257.17:01:41.47#ibcon#flushed, iclass 23, count 0 2006.257.17:01:41.47#ibcon#about to write, iclass 23, count 0 2006.257.17:01:41.47#ibcon#wrote, iclass 23, count 0 2006.257.17:01:41.47#ibcon#about to read 3, iclass 23, count 0 2006.257.17:01:41.52#ibcon#read 3, iclass 23, count 0 2006.257.17:01:41.52#ibcon#about to read 4, iclass 23, count 0 2006.257.17:01:41.52#ibcon#read 4, iclass 23, count 0 2006.257.17:01:41.52#ibcon#about to read 5, iclass 23, count 0 2006.257.17:01:41.52#ibcon#read 5, iclass 23, count 0 2006.257.17:01:41.52#ibcon#about to read 6, iclass 23, count 0 2006.257.17:01:41.52#ibcon#read 6, iclass 23, count 0 2006.257.17:01:41.52#ibcon#end of sib2, iclass 23, count 0 2006.257.17:01:41.52#ibcon#*after write, iclass 23, count 0 2006.257.17:01:41.52#ibcon#*before return 0, iclass 23, count 0 2006.257.17:01:41.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:41.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:41.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:01:41.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:01:41.52$vck44/va=1,8 2006.257.17:01:41.52#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.17:01:41.52#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.17:01:41.52#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:41.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:41.52#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:41.52#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:41.52#ibcon#enter wrdev, iclass 25, count 2 2006.257.17:01:41.52#ibcon#first serial, iclass 25, count 2 2006.257.17:01:41.52#ibcon#enter sib2, iclass 25, count 2 2006.257.17:01:41.52#ibcon#flushed, iclass 25, count 2 2006.257.17:01:41.52#ibcon#about to write, iclass 25, count 2 2006.257.17:01:41.52#ibcon#wrote, iclass 25, count 2 2006.257.17:01:41.52#ibcon#about to read 3, iclass 25, count 2 2006.257.17:01:41.54#ibcon#read 3, iclass 25, count 2 2006.257.17:01:41.54#ibcon#about to read 4, iclass 25, count 2 2006.257.17:01:41.54#ibcon#read 4, iclass 25, count 2 2006.257.17:01:41.54#ibcon#about to read 5, iclass 25, count 2 2006.257.17:01:41.54#ibcon#read 5, iclass 25, count 2 2006.257.17:01:41.54#ibcon#about to read 6, iclass 25, count 2 2006.257.17:01:41.54#ibcon#read 6, iclass 25, count 2 2006.257.17:01:41.54#ibcon#end of sib2, iclass 25, count 2 2006.257.17:01:41.54#ibcon#*mode == 0, iclass 25, count 2 2006.257.17:01:41.54#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.17:01:41.54#ibcon#[25=AT01-08\r\n] 2006.257.17:01:41.54#ibcon#*before write, iclass 25, count 2 2006.257.17:01:41.54#ibcon#enter sib2, iclass 25, count 2 2006.257.17:01:41.54#ibcon#flushed, iclass 25, count 2 2006.257.17:01:41.54#ibcon#about to write, iclass 25, count 2 2006.257.17:01:41.54#ibcon#wrote, iclass 25, count 2 2006.257.17:01:41.54#ibcon#about to read 3, iclass 25, count 2 2006.257.17:01:41.57#ibcon#read 3, iclass 25, count 2 2006.257.17:01:41.57#ibcon#about to read 4, iclass 25, count 2 2006.257.17:01:41.57#ibcon#read 4, iclass 25, count 2 2006.257.17:01:41.57#ibcon#about to read 5, iclass 25, count 2 2006.257.17:01:41.57#ibcon#read 5, iclass 25, count 2 2006.257.17:01:41.57#ibcon#about to read 6, iclass 25, count 2 2006.257.17:01:41.57#ibcon#read 6, iclass 25, count 2 2006.257.17:01:41.57#ibcon#end of sib2, iclass 25, count 2 2006.257.17:01:41.57#ibcon#*after write, iclass 25, count 2 2006.257.17:01:41.57#ibcon#*before return 0, iclass 25, count 2 2006.257.17:01:41.57#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:41.57#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:41.57#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.17:01:41.57#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:41.57#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:41.69#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:41.69#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:41.69#ibcon#enter wrdev, iclass 25, count 0 2006.257.17:01:41.69#ibcon#first serial, iclass 25, count 0 2006.257.17:01:41.69#ibcon#enter sib2, iclass 25, count 0 2006.257.17:01:41.69#ibcon#flushed, iclass 25, count 0 2006.257.17:01:41.69#ibcon#about to write, iclass 25, count 0 2006.257.17:01:41.69#ibcon#wrote, iclass 25, count 0 2006.257.17:01:41.69#ibcon#about to read 3, iclass 25, count 0 2006.257.17:01:41.71#ibcon#read 3, iclass 25, count 0 2006.257.17:01:41.71#ibcon#about to read 4, iclass 25, count 0 2006.257.17:01:41.71#ibcon#read 4, iclass 25, count 0 2006.257.17:01:41.71#ibcon#about to read 5, iclass 25, count 0 2006.257.17:01:41.71#ibcon#read 5, iclass 25, count 0 2006.257.17:01:41.71#ibcon#about to read 6, iclass 25, count 0 2006.257.17:01:41.71#ibcon#read 6, iclass 25, count 0 2006.257.17:01:41.71#ibcon#end of sib2, iclass 25, count 0 2006.257.17:01:41.71#ibcon#*mode == 0, iclass 25, count 0 2006.257.17:01:41.71#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.17:01:41.71#ibcon#[25=USB\r\n] 2006.257.17:01:41.71#ibcon#*before write, iclass 25, count 0 2006.257.17:01:41.71#ibcon#enter sib2, iclass 25, count 0 2006.257.17:01:41.71#ibcon#flushed, iclass 25, count 0 2006.257.17:01:41.71#ibcon#about to write, iclass 25, count 0 2006.257.17:01:41.71#ibcon#wrote, iclass 25, count 0 2006.257.17:01:41.71#ibcon#about to read 3, iclass 25, count 0 2006.257.17:01:41.74#ibcon#read 3, iclass 25, count 0 2006.257.17:01:41.74#ibcon#about to read 4, iclass 25, count 0 2006.257.17:01:41.74#ibcon#read 4, iclass 25, count 0 2006.257.17:01:41.74#ibcon#about to read 5, iclass 25, count 0 2006.257.17:01:41.74#ibcon#read 5, iclass 25, count 0 2006.257.17:01:41.74#ibcon#about to read 6, iclass 25, count 0 2006.257.17:01:41.74#ibcon#read 6, iclass 25, count 0 2006.257.17:01:41.74#ibcon#end of sib2, iclass 25, count 0 2006.257.17:01:41.74#ibcon#*after write, iclass 25, count 0 2006.257.17:01:41.74#ibcon#*before return 0, iclass 25, count 0 2006.257.17:01:41.74#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:41.74#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:41.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.17:01:41.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.17:01:41.74$vck44/valo=2,534.99 2006.257.17:01:41.74#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.17:01:41.74#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.17:01:41.74#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:41.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:41.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:41.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:41.74#ibcon#enter wrdev, iclass 27, count 0 2006.257.17:01:41.74#ibcon#first serial, iclass 27, count 0 2006.257.17:01:41.74#ibcon#enter sib2, iclass 27, count 0 2006.257.17:01:41.74#ibcon#flushed, iclass 27, count 0 2006.257.17:01:41.74#ibcon#about to write, iclass 27, count 0 2006.257.17:01:41.74#ibcon#wrote, iclass 27, count 0 2006.257.17:01:41.74#ibcon#about to read 3, iclass 27, count 0 2006.257.17:01:41.76#ibcon#read 3, iclass 27, count 0 2006.257.17:01:41.76#ibcon#about to read 4, iclass 27, count 0 2006.257.17:01:41.76#ibcon#read 4, iclass 27, count 0 2006.257.17:01:41.76#ibcon#about to read 5, iclass 27, count 0 2006.257.17:01:41.76#ibcon#read 5, iclass 27, count 0 2006.257.17:01:41.76#ibcon#about to read 6, iclass 27, count 0 2006.257.17:01:41.76#ibcon#read 6, iclass 27, count 0 2006.257.17:01:41.76#ibcon#end of sib2, iclass 27, count 0 2006.257.17:01:41.76#ibcon#*mode == 0, iclass 27, count 0 2006.257.17:01:41.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.17:01:41.76#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:01:41.76#ibcon#*before write, iclass 27, count 0 2006.257.17:01:41.76#ibcon#enter sib2, iclass 27, count 0 2006.257.17:01:41.76#ibcon#flushed, iclass 27, count 0 2006.257.17:01:41.76#ibcon#about to write, iclass 27, count 0 2006.257.17:01:41.76#ibcon#wrote, iclass 27, count 0 2006.257.17:01:41.76#ibcon#about to read 3, iclass 27, count 0 2006.257.17:01:41.80#ibcon#read 3, iclass 27, count 0 2006.257.17:01:41.80#ibcon#about to read 4, iclass 27, count 0 2006.257.17:01:41.80#ibcon#read 4, iclass 27, count 0 2006.257.17:01:41.80#ibcon#about to read 5, iclass 27, count 0 2006.257.17:01:41.80#ibcon#read 5, iclass 27, count 0 2006.257.17:01:41.80#ibcon#about to read 6, iclass 27, count 0 2006.257.17:01:41.80#ibcon#read 6, iclass 27, count 0 2006.257.17:01:41.80#ibcon#end of sib2, iclass 27, count 0 2006.257.17:01:41.80#ibcon#*after write, iclass 27, count 0 2006.257.17:01:41.80#ibcon#*before return 0, iclass 27, count 0 2006.257.17:01:41.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:41.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:41.80#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.17:01:41.80#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.17:01:41.80$vck44/va=2,7 2006.257.17:01:41.80#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.17:01:41.80#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.17:01:41.80#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:41.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:41.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:41.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:41.86#ibcon#enter wrdev, iclass 29, count 2 2006.257.17:01:41.86#ibcon#first serial, iclass 29, count 2 2006.257.17:01:41.86#ibcon#enter sib2, iclass 29, count 2 2006.257.17:01:41.86#ibcon#flushed, iclass 29, count 2 2006.257.17:01:41.86#ibcon#about to write, iclass 29, count 2 2006.257.17:01:41.86#ibcon#wrote, iclass 29, count 2 2006.257.17:01:41.86#ibcon#about to read 3, iclass 29, count 2 2006.257.17:01:41.88#ibcon#read 3, iclass 29, count 2 2006.257.17:01:41.88#ibcon#about to read 4, iclass 29, count 2 2006.257.17:01:41.88#ibcon#read 4, iclass 29, count 2 2006.257.17:01:41.88#ibcon#about to read 5, iclass 29, count 2 2006.257.17:01:41.88#ibcon#read 5, iclass 29, count 2 2006.257.17:01:41.88#ibcon#about to read 6, iclass 29, count 2 2006.257.17:01:41.88#ibcon#read 6, iclass 29, count 2 2006.257.17:01:41.88#ibcon#end of sib2, iclass 29, count 2 2006.257.17:01:41.88#ibcon#*mode == 0, iclass 29, count 2 2006.257.17:01:41.88#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.17:01:41.88#ibcon#[25=AT02-07\r\n] 2006.257.17:01:41.88#ibcon#*before write, iclass 29, count 2 2006.257.17:01:41.88#ibcon#enter sib2, iclass 29, count 2 2006.257.17:01:41.88#ibcon#flushed, iclass 29, count 2 2006.257.17:01:41.88#ibcon#about to write, iclass 29, count 2 2006.257.17:01:41.88#ibcon#wrote, iclass 29, count 2 2006.257.17:01:41.88#ibcon#about to read 3, iclass 29, count 2 2006.257.17:01:41.91#ibcon#read 3, iclass 29, count 2 2006.257.17:01:41.91#ibcon#about to read 4, iclass 29, count 2 2006.257.17:01:41.91#ibcon#read 4, iclass 29, count 2 2006.257.17:01:41.91#ibcon#about to read 5, iclass 29, count 2 2006.257.17:01:41.91#ibcon#read 5, iclass 29, count 2 2006.257.17:01:41.91#ibcon#about to read 6, iclass 29, count 2 2006.257.17:01:41.91#ibcon#read 6, iclass 29, count 2 2006.257.17:01:41.91#ibcon#end of sib2, iclass 29, count 2 2006.257.17:01:41.91#ibcon#*after write, iclass 29, count 2 2006.257.17:01:41.91#ibcon#*before return 0, iclass 29, count 2 2006.257.17:01:41.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:41.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:41.91#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.17:01:41.91#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:41.91#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:42.03#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:42.03#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:42.03#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:01:42.03#ibcon#first serial, iclass 29, count 0 2006.257.17:01:42.03#ibcon#enter sib2, iclass 29, count 0 2006.257.17:01:42.03#ibcon#flushed, iclass 29, count 0 2006.257.17:01:42.03#ibcon#about to write, iclass 29, count 0 2006.257.17:01:42.03#ibcon#wrote, iclass 29, count 0 2006.257.17:01:42.03#ibcon#about to read 3, iclass 29, count 0 2006.257.17:01:42.05#ibcon#read 3, iclass 29, count 0 2006.257.17:01:42.05#ibcon#about to read 4, iclass 29, count 0 2006.257.17:01:42.05#ibcon#read 4, iclass 29, count 0 2006.257.17:01:42.05#ibcon#about to read 5, iclass 29, count 0 2006.257.17:01:42.05#ibcon#read 5, iclass 29, count 0 2006.257.17:01:42.05#ibcon#about to read 6, iclass 29, count 0 2006.257.17:01:42.05#ibcon#read 6, iclass 29, count 0 2006.257.17:01:42.05#ibcon#end of sib2, iclass 29, count 0 2006.257.17:01:42.05#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:01:42.05#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:01:42.05#ibcon#[25=USB\r\n] 2006.257.17:01:42.05#ibcon#*before write, iclass 29, count 0 2006.257.17:01:42.05#ibcon#enter sib2, iclass 29, count 0 2006.257.17:01:42.05#ibcon#flushed, iclass 29, count 0 2006.257.17:01:42.05#ibcon#about to write, iclass 29, count 0 2006.257.17:01:42.05#ibcon#wrote, iclass 29, count 0 2006.257.17:01:42.05#ibcon#about to read 3, iclass 29, count 0 2006.257.17:01:42.08#ibcon#read 3, iclass 29, count 0 2006.257.17:01:42.08#ibcon#about to read 4, iclass 29, count 0 2006.257.17:01:42.08#ibcon#read 4, iclass 29, count 0 2006.257.17:01:42.08#ibcon#about to read 5, iclass 29, count 0 2006.257.17:01:42.08#ibcon#read 5, iclass 29, count 0 2006.257.17:01:42.08#ibcon#about to read 6, iclass 29, count 0 2006.257.17:01:42.08#ibcon#read 6, iclass 29, count 0 2006.257.17:01:42.08#ibcon#end of sib2, iclass 29, count 0 2006.257.17:01:42.08#ibcon#*after write, iclass 29, count 0 2006.257.17:01:42.08#ibcon#*before return 0, iclass 29, count 0 2006.257.17:01:42.08#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:42.08#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:42.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:01:42.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:01:42.08$vck44/valo=3,564.99 2006.257.17:01:42.08#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.17:01:42.08#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.17:01:42.08#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:42.08#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:42.08#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:42.08#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:42.08#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:01:42.08#ibcon#first serial, iclass 31, count 0 2006.257.17:01:42.08#ibcon#enter sib2, iclass 31, count 0 2006.257.17:01:42.08#ibcon#flushed, iclass 31, count 0 2006.257.17:01:42.08#ibcon#about to write, iclass 31, count 0 2006.257.17:01:42.08#ibcon#wrote, iclass 31, count 0 2006.257.17:01:42.08#ibcon#about to read 3, iclass 31, count 0 2006.257.17:01:42.10#ibcon#read 3, iclass 31, count 0 2006.257.17:01:42.10#ibcon#about to read 4, iclass 31, count 0 2006.257.17:01:42.10#ibcon#read 4, iclass 31, count 0 2006.257.17:01:42.10#ibcon#about to read 5, iclass 31, count 0 2006.257.17:01:42.10#ibcon#read 5, iclass 31, count 0 2006.257.17:01:42.10#ibcon#about to read 6, iclass 31, count 0 2006.257.17:01:42.10#ibcon#read 6, iclass 31, count 0 2006.257.17:01:42.10#ibcon#end of sib2, iclass 31, count 0 2006.257.17:01:42.10#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:01:42.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:01:42.10#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:01:42.10#ibcon#*before write, iclass 31, count 0 2006.257.17:01:42.10#ibcon#enter sib2, iclass 31, count 0 2006.257.17:01:42.10#ibcon#flushed, iclass 31, count 0 2006.257.17:01:42.10#ibcon#about to write, iclass 31, count 0 2006.257.17:01:42.10#ibcon#wrote, iclass 31, count 0 2006.257.17:01:42.10#ibcon#about to read 3, iclass 31, count 0 2006.257.17:01:42.14#ibcon#read 3, iclass 31, count 0 2006.257.17:01:42.14#ibcon#about to read 4, iclass 31, count 0 2006.257.17:01:42.14#ibcon#read 4, iclass 31, count 0 2006.257.17:01:42.14#ibcon#about to read 5, iclass 31, count 0 2006.257.17:01:42.14#ibcon#read 5, iclass 31, count 0 2006.257.17:01:42.14#ibcon#about to read 6, iclass 31, count 0 2006.257.17:01:42.14#ibcon#read 6, iclass 31, count 0 2006.257.17:01:42.14#ibcon#end of sib2, iclass 31, count 0 2006.257.17:01:42.14#ibcon#*after write, iclass 31, count 0 2006.257.17:01:42.14#ibcon#*before return 0, iclass 31, count 0 2006.257.17:01:42.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:42.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:42.14#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:01:42.14#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:01:42.14$vck44/va=3,8 2006.257.17:01:42.14#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.17:01:42.14#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.17:01:42.14#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:42.14#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:42.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:42.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:42.20#ibcon#enter wrdev, iclass 33, count 2 2006.257.17:01:42.20#ibcon#first serial, iclass 33, count 2 2006.257.17:01:42.20#ibcon#enter sib2, iclass 33, count 2 2006.257.17:01:42.20#ibcon#flushed, iclass 33, count 2 2006.257.17:01:42.20#ibcon#about to write, iclass 33, count 2 2006.257.17:01:42.20#ibcon#wrote, iclass 33, count 2 2006.257.17:01:42.20#ibcon#about to read 3, iclass 33, count 2 2006.257.17:01:42.22#ibcon#read 3, iclass 33, count 2 2006.257.17:01:42.22#ibcon#about to read 4, iclass 33, count 2 2006.257.17:01:42.22#ibcon#read 4, iclass 33, count 2 2006.257.17:01:42.22#ibcon#about to read 5, iclass 33, count 2 2006.257.17:01:42.22#ibcon#read 5, iclass 33, count 2 2006.257.17:01:42.22#ibcon#about to read 6, iclass 33, count 2 2006.257.17:01:42.22#ibcon#read 6, iclass 33, count 2 2006.257.17:01:42.22#ibcon#end of sib2, iclass 33, count 2 2006.257.17:01:42.22#ibcon#*mode == 0, iclass 33, count 2 2006.257.17:01:42.22#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.17:01:42.22#ibcon#[25=AT03-08\r\n] 2006.257.17:01:42.22#ibcon#*before write, iclass 33, count 2 2006.257.17:01:42.22#ibcon#enter sib2, iclass 33, count 2 2006.257.17:01:42.22#ibcon#flushed, iclass 33, count 2 2006.257.17:01:42.22#ibcon#about to write, iclass 33, count 2 2006.257.17:01:42.22#ibcon#wrote, iclass 33, count 2 2006.257.17:01:42.22#ibcon#about to read 3, iclass 33, count 2 2006.257.17:01:42.25#ibcon#read 3, iclass 33, count 2 2006.257.17:01:42.25#ibcon#about to read 4, iclass 33, count 2 2006.257.17:01:42.25#ibcon#read 4, iclass 33, count 2 2006.257.17:01:42.25#ibcon#about to read 5, iclass 33, count 2 2006.257.17:01:42.25#ibcon#read 5, iclass 33, count 2 2006.257.17:01:42.25#ibcon#about to read 6, iclass 33, count 2 2006.257.17:01:42.25#ibcon#read 6, iclass 33, count 2 2006.257.17:01:42.25#ibcon#end of sib2, iclass 33, count 2 2006.257.17:01:42.25#ibcon#*after write, iclass 33, count 2 2006.257.17:01:42.25#ibcon#*before return 0, iclass 33, count 2 2006.257.17:01:42.25#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:42.25#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:42.25#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.17:01:42.25#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:42.25#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:42.37#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:42.37#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:42.37#ibcon#enter wrdev, iclass 33, count 0 2006.257.17:01:42.37#ibcon#first serial, iclass 33, count 0 2006.257.17:01:42.37#ibcon#enter sib2, iclass 33, count 0 2006.257.17:01:42.37#ibcon#flushed, iclass 33, count 0 2006.257.17:01:42.37#ibcon#about to write, iclass 33, count 0 2006.257.17:01:42.37#ibcon#wrote, iclass 33, count 0 2006.257.17:01:42.37#ibcon#about to read 3, iclass 33, count 0 2006.257.17:01:42.38#abcon#<5=/14 1.5 5.3 17.36 961014.2\r\n> 2006.257.17:01:42.39#ibcon#read 3, iclass 33, count 0 2006.257.17:01:42.39#ibcon#about to read 4, iclass 33, count 0 2006.257.17:01:42.39#ibcon#read 4, iclass 33, count 0 2006.257.17:01:42.39#ibcon#about to read 5, iclass 33, count 0 2006.257.17:01:42.39#ibcon#read 5, iclass 33, count 0 2006.257.17:01:42.39#ibcon#about to read 6, iclass 33, count 0 2006.257.17:01:42.39#ibcon#read 6, iclass 33, count 0 2006.257.17:01:42.39#ibcon#end of sib2, iclass 33, count 0 2006.257.17:01:42.39#ibcon#*mode == 0, iclass 33, count 0 2006.257.17:01:42.39#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.17:01:42.39#ibcon#[25=USB\r\n] 2006.257.17:01:42.39#ibcon#*before write, iclass 33, count 0 2006.257.17:01:42.39#ibcon#enter sib2, iclass 33, count 0 2006.257.17:01:42.39#ibcon#flushed, iclass 33, count 0 2006.257.17:01:42.39#ibcon#about to write, iclass 33, count 0 2006.257.17:01:42.39#ibcon#wrote, iclass 33, count 0 2006.257.17:01:42.39#ibcon#about to read 3, iclass 33, count 0 2006.257.17:01:42.40#abcon#{5=INTERFACE CLEAR} 2006.257.17:01:42.42#ibcon#read 3, iclass 33, count 0 2006.257.17:01:42.42#ibcon#about to read 4, iclass 33, count 0 2006.257.17:01:42.42#ibcon#read 4, iclass 33, count 0 2006.257.17:01:42.42#ibcon#about to read 5, iclass 33, count 0 2006.257.17:01:42.42#ibcon#read 5, iclass 33, count 0 2006.257.17:01:42.42#ibcon#about to read 6, iclass 33, count 0 2006.257.17:01:42.42#ibcon#read 6, iclass 33, count 0 2006.257.17:01:42.42#ibcon#end of sib2, iclass 33, count 0 2006.257.17:01:42.42#ibcon#*after write, iclass 33, count 0 2006.257.17:01:42.42#ibcon#*before return 0, iclass 33, count 0 2006.257.17:01:42.42#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:42.42#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:42.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.17:01:42.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.17:01:42.42$vck44/valo=4,624.99 2006.257.17:01:42.42#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.17:01:42.42#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.17:01:42.42#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:42.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:01:42.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:01:42.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:01:42.42#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:01:42.42#ibcon#first serial, iclass 38, count 0 2006.257.17:01:42.42#ibcon#enter sib2, iclass 38, count 0 2006.257.17:01:42.42#ibcon#flushed, iclass 38, count 0 2006.257.17:01:42.42#ibcon#about to write, iclass 38, count 0 2006.257.17:01:42.42#ibcon#wrote, iclass 38, count 0 2006.257.17:01:42.42#ibcon#about to read 3, iclass 38, count 0 2006.257.17:01:42.44#ibcon#read 3, iclass 38, count 0 2006.257.17:01:42.44#ibcon#about to read 4, iclass 38, count 0 2006.257.17:01:42.44#ibcon#read 4, iclass 38, count 0 2006.257.17:01:42.44#ibcon#about to read 5, iclass 38, count 0 2006.257.17:01:42.44#ibcon#read 5, iclass 38, count 0 2006.257.17:01:42.44#ibcon#about to read 6, iclass 38, count 0 2006.257.17:01:42.44#ibcon#read 6, iclass 38, count 0 2006.257.17:01:42.44#ibcon#end of sib2, iclass 38, count 0 2006.257.17:01:42.44#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:01:42.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:01:42.44#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:01:42.44#ibcon#*before write, iclass 38, count 0 2006.257.17:01:42.44#ibcon#enter sib2, iclass 38, count 0 2006.257.17:01:42.44#ibcon#flushed, iclass 38, count 0 2006.257.17:01:42.44#ibcon#about to write, iclass 38, count 0 2006.257.17:01:42.44#ibcon#wrote, iclass 38, count 0 2006.257.17:01:42.44#ibcon#about to read 3, iclass 38, count 0 2006.257.17:01:42.46#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:01:42.48#ibcon#read 3, iclass 38, count 0 2006.257.17:01:42.48#ibcon#about to read 4, iclass 38, count 0 2006.257.17:01:42.48#ibcon#read 4, iclass 38, count 0 2006.257.17:01:42.48#ibcon#about to read 5, iclass 38, count 0 2006.257.17:01:42.48#ibcon#read 5, iclass 38, count 0 2006.257.17:01:42.48#ibcon#about to read 6, iclass 38, count 0 2006.257.17:01:42.48#ibcon#read 6, iclass 38, count 0 2006.257.17:01:42.48#ibcon#end of sib2, iclass 38, count 0 2006.257.17:01:42.48#ibcon#*after write, iclass 38, count 0 2006.257.17:01:42.48#ibcon#*before return 0, iclass 38, count 0 2006.257.17:01:42.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:01:42.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:01:42.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:01:42.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:01:42.48$vck44/va=4,7 2006.257.17:01:42.48#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.17:01:42.48#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.17:01:42.48#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:42.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:42.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:42.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:42.54#ibcon#enter wrdev, iclass 3, count 2 2006.257.17:01:42.54#ibcon#first serial, iclass 3, count 2 2006.257.17:01:42.54#ibcon#enter sib2, iclass 3, count 2 2006.257.17:01:42.54#ibcon#flushed, iclass 3, count 2 2006.257.17:01:42.54#ibcon#about to write, iclass 3, count 2 2006.257.17:01:42.54#ibcon#wrote, iclass 3, count 2 2006.257.17:01:42.54#ibcon#about to read 3, iclass 3, count 2 2006.257.17:01:42.56#ibcon#read 3, iclass 3, count 2 2006.257.17:01:42.56#ibcon#about to read 4, iclass 3, count 2 2006.257.17:01:42.56#ibcon#read 4, iclass 3, count 2 2006.257.17:01:42.56#ibcon#about to read 5, iclass 3, count 2 2006.257.17:01:42.56#ibcon#read 5, iclass 3, count 2 2006.257.17:01:42.56#ibcon#about to read 6, iclass 3, count 2 2006.257.17:01:42.56#ibcon#read 6, iclass 3, count 2 2006.257.17:01:42.56#ibcon#end of sib2, iclass 3, count 2 2006.257.17:01:42.56#ibcon#*mode == 0, iclass 3, count 2 2006.257.17:01:42.56#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.17:01:42.56#ibcon#[25=AT04-07\r\n] 2006.257.17:01:42.56#ibcon#*before write, iclass 3, count 2 2006.257.17:01:42.56#ibcon#enter sib2, iclass 3, count 2 2006.257.17:01:42.56#ibcon#flushed, iclass 3, count 2 2006.257.17:01:42.56#ibcon#about to write, iclass 3, count 2 2006.257.17:01:42.56#ibcon#wrote, iclass 3, count 2 2006.257.17:01:42.56#ibcon#about to read 3, iclass 3, count 2 2006.257.17:01:42.59#ibcon#read 3, iclass 3, count 2 2006.257.17:01:42.59#ibcon#about to read 4, iclass 3, count 2 2006.257.17:01:42.59#ibcon#read 4, iclass 3, count 2 2006.257.17:01:42.59#ibcon#about to read 5, iclass 3, count 2 2006.257.17:01:42.59#ibcon#read 5, iclass 3, count 2 2006.257.17:01:42.59#ibcon#about to read 6, iclass 3, count 2 2006.257.17:01:42.59#ibcon#read 6, iclass 3, count 2 2006.257.17:01:42.59#ibcon#end of sib2, iclass 3, count 2 2006.257.17:01:42.59#ibcon#*after write, iclass 3, count 2 2006.257.17:01:42.59#ibcon#*before return 0, iclass 3, count 2 2006.257.17:01:42.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:42.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:42.59#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.17:01:42.59#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:42.59#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:42.71#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:42.71#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:42.71#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:01:42.71#ibcon#first serial, iclass 3, count 0 2006.257.17:01:42.71#ibcon#enter sib2, iclass 3, count 0 2006.257.17:01:42.71#ibcon#flushed, iclass 3, count 0 2006.257.17:01:42.71#ibcon#about to write, iclass 3, count 0 2006.257.17:01:42.71#ibcon#wrote, iclass 3, count 0 2006.257.17:01:42.71#ibcon#about to read 3, iclass 3, count 0 2006.257.17:01:42.73#ibcon#read 3, iclass 3, count 0 2006.257.17:01:42.73#ibcon#about to read 4, iclass 3, count 0 2006.257.17:01:42.73#ibcon#read 4, iclass 3, count 0 2006.257.17:01:42.73#ibcon#about to read 5, iclass 3, count 0 2006.257.17:01:42.73#ibcon#read 5, iclass 3, count 0 2006.257.17:01:42.73#ibcon#about to read 6, iclass 3, count 0 2006.257.17:01:42.73#ibcon#read 6, iclass 3, count 0 2006.257.17:01:42.73#ibcon#end of sib2, iclass 3, count 0 2006.257.17:01:42.73#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:01:42.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:01:42.73#ibcon#[25=USB\r\n] 2006.257.17:01:42.73#ibcon#*before write, iclass 3, count 0 2006.257.17:01:42.73#ibcon#enter sib2, iclass 3, count 0 2006.257.17:01:42.73#ibcon#flushed, iclass 3, count 0 2006.257.17:01:42.73#ibcon#about to write, iclass 3, count 0 2006.257.17:01:42.73#ibcon#wrote, iclass 3, count 0 2006.257.17:01:42.73#ibcon#about to read 3, iclass 3, count 0 2006.257.17:01:42.76#ibcon#read 3, iclass 3, count 0 2006.257.17:01:42.76#ibcon#about to read 4, iclass 3, count 0 2006.257.17:01:42.76#ibcon#read 4, iclass 3, count 0 2006.257.17:01:42.76#ibcon#about to read 5, iclass 3, count 0 2006.257.17:01:42.76#ibcon#read 5, iclass 3, count 0 2006.257.17:01:42.76#ibcon#about to read 6, iclass 3, count 0 2006.257.17:01:42.76#ibcon#read 6, iclass 3, count 0 2006.257.17:01:42.76#ibcon#end of sib2, iclass 3, count 0 2006.257.17:01:42.76#ibcon#*after write, iclass 3, count 0 2006.257.17:01:42.76#ibcon#*before return 0, iclass 3, count 0 2006.257.17:01:42.76#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:42.76#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:42.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:01:42.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:01:42.76$vck44/valo=5,734.99 2006.257.17:01:42.76#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.17:01:42.76#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.17:01:42.76#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:42.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:42.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:42.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:42.76#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:01:42.76#ibcon#first serial, iclass 5, count 0 2006.257.17:01:42.76#ibcon#enter sib2, iclass 5, count 0 2006.257.17:01:42.76#ibcon#flushed, iclass 5, count 0 2006.257.17:01:42.76#ibcon#about to write, iclass 5, count 0 2006.257.17:01:42.76#ibcon#wrote, iclass 5, count 0 2006.257.17:01:42.76#ibcon#about to read 3, iclass 5, count 0 2006.257.17:01:42.78#ibcon#read 3, iclass 5, count 0 2006.257.17:01:42.78#ibcon#about to read 4, iclass 5, count 0 2006.257.17:01:42.78#ibcon#read 4, iclass 5, count 0 2006.257.17:01:42.78#ibcon#about to read 5, iclass 5, count 0 2006.257.17:01:42.78#ibcon#read 5, iclass 5, count 0 2006.257.17:01:42.78#ibcon#about to read 6, iclass 5, count 0 2006.257.17:01:42.78#ibcon#read 6, iclass 5, count 0 2006.257.17:01:42.78#ibcon#end of sib2, iclass 5, count 0 2006.257.17:01:42.78#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:01:42.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:01:42.78#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:01:42.78#ibcon#*before write, iclass 5, count 0 2006.257.17:01:42.78#ibcon#enter sib2, iclass 5, count 0 2006.257.17:01:42.78#ibcon#flushed, iclass 5, count 0 2006.257.17:01:42.78#ibcon#about to write, iclass 5, count 0 2006.257.17:01:42.78#ibcon#wrote, iclass 5, count 0 2006.257.17:01:42.78#ibcon#about to read 3, iclass 5, count 0 2006.257.17:01:42.82#ibcon#read 3, iclass 5, count 0 2006.257.17:01:42.82#ibcon#about to read 4, iclass 5, count 0 2006.257.17:01:42.82#ibcon#read 4, iclass 5, count 0 2006.257.17:01:42.82#ibcon#about to read 5, iclass 5, count 0 2006.257.17:01:42.82#ibcon#read 5, iclass 5, count 0 2006.257.17:01:42.82#ibcon#about to read 6, iclass 5, count 0 2006.257.17:01:42.82#ibcon#read 6, iclass 5, count 0 2006.257.17:01:42.82#ibcon#end of sib2, iclass 5, count 0 2006.257.17:01:42.82#ibcon#*after write, iclass 5, count 0 2006.257.17:01:42.82#ibcon#*before return 0, iclass 5, count 0 2006.257.17:01:42.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:42.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:42.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:01:42.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:01:42.82$vck44/va=5,4 2006.257.17:01:42.82#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.17:01:42.82#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.17:01:42.82#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:42.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:42.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:42.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:42.88#ibcon#enter wrdev, iclass 7, count 2 2006.257.17:01:42.88#ibcon#first serial, iclass 7, count 2 2006.257.17:01:42.88#ibcon#enter sib2, iclass 7, count 2 2006.257.17:01:42.88#ibcon#flushed, iclass 7, count 2 2006.257.17:01:42.88#ibcon#about to write, iclass 7, count 2 2006.257.17:01:42.88#ibcon#wrote, iclass 7, count 2 2006.257.17:01:42.88#ibcon#about to read 3, iclass 7, count 2 2006.257.17:01:42.90#ibcon#read 3, iclass 7, count 2 2006.257.17:01:42.90#ibcon#about to read 4, iclass 7, count 2 2006.257.17:01:42.90#ibcon#read 4, iclass 7, count 2 2006.257.17:01:42.90#ibcon#about to read 5, iclass 7, count 2 2006.257.17:01:42.90#ibcon#read 5, iclass 7, count 2 2006.257.17:01:42.90#ibcon#about to read 6, iclass 7, count 2 2006.257.17:01:42.90#ibcon#read 6, iclass 7, count 2 2006.257.17:01:42.90#ibcon#end of sib2, iclass 7, count 2 2006.257.17:01:42.90#ibcon#*mode == 0, iclass 7, count 2 2006.257.17:01:42.90#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.17:01:42.90#ibcon#[25=AT05-04\r\n] 2006.257.17:01:42.90#ibcon#*before write, iclass 7, count 2 2006.257.17:01:42.90#ibcon#enter sib2, iclass 7, count 2 2006.257.17:01:42.90#ibcon#flushed, iclass 7, count 2 2006.257.17:01:42.90#ibcon#about to write, iclass 7, count 2 2006.257.17:01:42.90#ibcon#wrote, iclass 7, count 2 2006.257.17:01:42.90#ibcon#about to read 3, iclass 7, count 2 2006.257.17:01:42.93#ibcon#read 3, iclass 7, count 2 2006.257.17:01:42.93#ibcon#about to read 4, iclass 7, count 2 2006.257.17:01:42.93#ibcon#read 4, iclass 7, count 2 2006.257.17:01:42.93#ibcon#about to read 5, iclass 7, count 2 2006.257.17:01:42.93#ibcon#read 5, iclass 7, count 2 2006.257.17:01:42.93#ibcon#about to read 6, iclass 7, count 2 2006.257.17:01:42.93#ibcon#read 6, iclass 7, count 2 2006.257.17:01:42.93#ibcon#end of sib2, iclass 7, count 2 2006.257.17:01:42.93#ibcon#*after write, iclass 7, count 2 2006.257.17:01:42.93#ibcon#*before return 0, iclass 7, count 2 2006.257.17:01:42.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:42.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:42.93#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.17:01:42.93#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:42.93#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:43.05#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:43.05#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:43.05#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:01:43.05#ibcon#first serial, iclass 7, count 0 2006.257.17:01:43.05#ibcon#enter sib2, iclass 7, count 0 2006.257.17:01:43.05#ibcon#flushed, iclass 7, count 0 2006.257.17:01:43.05#ibcon#about to write, iclass 7, count 0 2006.257.17:01:43.05#ibcon#wrote, iclass 7, count 0 2006.257.17:01:43.05#ibcon#about to read 3, iclass 7, count 0 2006.257.17:01:43.07#ibcon#read 3, iclass 7, count 0 2006.257.17:01:43.07#ibcon#about to read 4, iclass 7, count 0 2006.257.17:01:43.07#ibcon#read 4, iclass 7, count 0 2006.257.17:01:43.07#ibcon#about to read 5, iclass 7, count 0 2006.257.17:01:43.07#ibcon#read 5, iclass 7, count 0 2006.257.17:01:43.07#ibcon#about to read 6, iclass 7, count 0 2006.257.17:01:43.07#ibcon#read 6, iclass 7, count 0 2006.257.17:01:43.07#ibcon#end of sib2, iclass 7, count 0 2006.257.17:01:43.07#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:01:43.07#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:01:43.07#ibcon#[25=USB\r\n] 2006.257.17:01:43.07#ibcon#*before write, iclass 7, count 0 2006.257.17:01:43.07#ibcon#enter sib2, iclass 7, count 0 2006.257.17:01:43.07#ibcon#flushed, iclass 7, count 0 2006.257.17:01:43.07#ibcon#about to write, iclass 7, count 0 2006.257.17:01:43.07#ibcon#wrote, iclass 7, count 0 2006.257.17:01:43.07#ibcon#about to read 3, iclass 7, count 0 2006.257.17:01:43.10#ibcon#read 3, iclass 7, count 0 2006.257.17:01:43.10#ibcon#about to read 4, iclass 7, count 0 2006.257.17:01:43.10#ibcon#read 4, iclass 7, count 0 2006.257.17:01:43.10#ibcon#about to read 5, iclass 7, count 0 2006.257.17:01:43.10#ibcon#read 5, iclass 7, count 0 2006.257.17:01:43.10#ibcon#about to read 6, iclass 7, count 0 2006.257.17:01:43.10#ibcon#read 6, iclass 7, count 0 2006.257.17:01:43.10#ibcon#end of sib2, iclass 7, count 0 2006.257.17:01:43.10#ibcon#*after write, iclass 7, count 0 2006.257.17:01:43.10#ibcon#*before return 0, iclass 7, count 0 2006.257.17:01:43.10#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:43.10#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:43.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:01:43.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:01:43.10$vck44/valo=6,814.99 2006.257.17:01:43.10#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.17:01:43.10#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.17:01:43.10#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:43.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:43.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:43.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:43.10#ibcon#enter wrdev, iclass 11, count 0 2006.257.17:01:43.10#ibcon#first serial, iclass 11, count 0 2006.257.17:01:43.10#ibcon#enter sib2, iclass 11, count 0 2006.257.17:01:43.10#ibcon#flushed, iclass 11, count 0 2006.257.17:01:43.10#ibcon#about to write, iclass 11, count 0 2006.257.17:01:43.10#ibcon#wrote, iclass 11, count 0 2006.257.17:01:43.10#ibcon#about to read 3, iclass 11, count 0 2006.257.17:01:43.12#ibcon#read 3, iclass 11, count 0 2006.257.17:01:43.12#ibcon#about to read 4, iclass 11, count 0 2006.257.17:01:43.12#ibcon#read 4, iclass 11, count 0 2006.257.17:01:43.12#ibcon#about to read 5, iclass 11, count 0 2006.257.17:01:43.12#ibcon#read 5, iclass 11, count 0 2006.257.17:01:43.12#ibcon#about to read 6, iclass 11, count 0 2006.257.17:01:43.12#ibcon#read 6, iclass 11, count 0 2006.257.17:01:43.12#ibcon#end of sib2, iclass 11, count 0 2006.257.17:01:43.12#ibcon#*mode == 0, iclass 11, count 0 2006.257.17:01:43.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.17:01:43.12#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:01:43.12#ibcon#*before write, iclass 11, count 0 2006.257.17:01:43.12#ibcon#enter sib2, iclass 11, count 0 2006.257.17:01:43.12#ibcon#flushed, iclass 11, count 0 2006.257.17:01:43.12#ibcon#about to write, iclass 11, count 0 2006.257.17:01:43.12#ibcon#wrote, iclass 11, count 0 2006.257.17:01:43.12#ibcon#about to read 3, iclass 11, count 0 2006.257.17:01:43.16#ibcon#read 3, iclass 11, count 0 2006.257.17:01:43.16#ibcon#about to read 4, iclass 11, count 0 2006.257.17:01:43.16#ibcon#read 4, iclass 11, count 0 2006.257.17:01:43.16#ibcon#about to read 5, iclass 11, count 0 2006.257.17:01:43.16#ibcon#read 5, iclass 11, count 0 2006.257.17:01:43.16#ibcon#about to read 6, iclass 11, count 0 2006.257.17:01:43.16#ibcon#read 6, iclass 11, count 0 2006.257.17:01:43.16#ibcon#end of sib2, iclass 11, count 0 2006.257.17:01:43.16#ibcon#*after write, iclass 11, count 0 2006.257.17:01:43.16#ibcon#*before return 0, iclass 11, count 0 2006.257.17:01:43.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:43.16#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:43.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.17:01:43.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.17:01:43.16$vck44/va=6,4 2006.257.17:01:43.16#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.17:01:43.16#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.17:01:43.16#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:43.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:43.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:43.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:43.22#ibcon#enter wrdev, iclass 13, count 2 2006.257.17:01:43.22#ibcon#first serial, iclass 13, count 2 2006.257.17:01:43.22#ibcon#enter sib2, iclass 13, count 2 2006.257.17:01:43.22#ibcon#flushed, iclass 13, count 2 2006.257.17:01:43.22#ibcon#about to write, iclass 13, count 2 2006.257.17:01:43.22#ibcon#wrote, iclass 13, count 2 2006.257.17:01:43.22#ibcon#about to read 3, iclass 13, count 2 2006.257.17:01:43.24#ibcon#read 3, iclass 13, count 2 2006.257.17:01:43.24#ibcon#about to read 4, iclass 13, count 2 2006.257.17:01:43.24#ibcon#read 4, iclass 13, count 2 2006.257.17:01:43.24#ibcon#about to read 5, iclass 13, count 2 2006.257.17:01:43.24#ibcon#read 5, iclass 13, count 2 2006.257.17:01:43.24#ibcon#about to read 6, iclass 13, count 2 2006.257.17:01:43.24#ibcon#read 6, iclass 13, count 2 2006.257.17:01:43.24#ibcon#end of sib2, iclass 13, count 2 2006.257.17:01:43.24#ibcon#*mode == 0, iclass 13, count 2 2006.257.17:01:43.24#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.17:01:43.24#ibcon#[25=AT06-04\r\n] 2006.257.17:01:43.24#ibcon#*before write, iclass 13, count 2 2006.257.17:01:43.24#ibcon#enter sib2, iclass 13, count 2 2006.257.17:01:43.24#ibcon#flushed, iclass 13, count 2 2006.257.17:01:43.24#ibcon#about to write, iclass 13, count 2 2006.257.17:01:43.24#ibcon#wrote, iclass 13, count 2 2006.257.17:01:43.24#ibcon#about to read 3, iclass 13, count 2 2006.257.17:01:43.27#ibcon#read 3, iclass 13, count 2 2006.257.17:01:43.27#ibcon#about to read 4, iclass 13, count 2 2006.257.17:01:43.27#ibcon#read 4, iclass 13, count 2 2006.257.17:01:43.27#ibcon#about to read 5, iclass 13, count 2 2006.257.17:01:43.27#ibcon#read 5, iclass 13, count 2 2006.257.17:01:43.27#ibcon#about to read 6, iclass 13, count 2 2006.257.17:01:43.27#ibcon#read 6, iclass 13, count 2 2006.257.17:01:43.27#ibcon#end of sib2, iclass 13, count 2 2006.257.17:01:43.27#ibcon#*after write, iclass 13, count 2 2006.257.17:01:43.27#ibcon#*before return 0, iclass 13, count 2 2006.257.17:01:43.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:43.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:43.27#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.17:01:43.27#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:43.27#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:43.39#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:43.39#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:43.39#ibcon#enter wrdev, iclass 13, count 0 2006.257.17:01:43.39#ibcon#first serial, iclass 13, count 0 2006.257.17:01:43.39#ibcon#enter sib2, iclass 13, count 0 2006.257.17:01:43.39#ibcon#flushed, iclass 13, count 0 2006.257.17:01:43.39#ibcon#about to write, iclass 13, count 0 2006.257.17:01:43.39#ibcon#wrote, iclass 13, count 0 2006.257.17:01:43.39#ibcon#about to read 3, iclass 13, count 0 2006.257.17:01:43.41#ibcon#read 3, iclass 13, count 0 2006.257.17:01:43.41#ibcon#about to read 4, iclass 13, count 0 2006.257.17:01:43.41#ibcon#read 4, iclass 13, count 0 2006.257.17:01:43.41#ibcon#about to read 5, iclass 13, count 0 2006.257.17:01:43.41#ibcon#read 5, iclass 13, count 0 2006.257.17:01:43.41#ibcon#about to read 6, iclass 13, count 0 2006.257.17:01:43.41#ibcon#read 6, iclass 13, count 0 2006.257.17:01:43.41#ibcon#end of sib2, iclass 13, count 0 2006.257.17:01:43.41#ibcon#*mode == 0, iclass 13, count 0 2006.257.17:01:43.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.17:01:43.41#ibcon#[25=USB\r\n] 2006.257.17:01:43.41#ibcon#*before write, iclass 13, count 0 2006.257.17:01:43.41#ibcon#enter sib2, iclass 13, count 0 2006.257.17:01:43.41#ibcon#flushed, iclass 13, count 0 2006.257.17:01:43.41#ibcon#about to write, iclass 13, count 0 2006.257.17:01:43.41#ibcon#wrote, iclass 13, count 0 2006.257.17:01:43.41#ibcon#about to read 3, iclass 13, count 0 2006.257.17:01:43.44#ibcon#read 3, iclass 13, count 0 2006.257.17:01:43.44#ibcon#about to read 4, iclass 13, count 0 2006.257.17:01:43.44#ibcon#read 4, iclass 13, count 0 2006.257.17:01:43.44#ibcon#about to read 5, iclass 13, count 0 2006.257.17:01:43.44#ibcon#read 5, iclass 13, count 0 2006.257.17:01:43.44#ibcon#about to read 6, iclass 13, count 0 2006.257.17:01:43.44#ibcon#read 6, iclass 13, count 0 2006.257.17:01:43.44#ibcon#end of sib2, iclass 13, count 0 2006.257.17:01:43.44#ibcon#*after write, iclass 13, count 0 2006.257.17:01:43.44#ibcon#*before return 0, iclass 13, count 0 2006.257.17:01:43.44#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:43.44#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:43.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.17:01:43.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.17:01:43.44$vck44/valo=7,864.99 2006.257.17:01:43.44#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.17:01:43.44#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.17:01:43.44#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:43.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:43.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:43.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:43.44#ibcon#enter wrdev, iclass 15, count 0 2006.257.17:01:43.44#ibcon#first serial, iclass 15, count 0 2006.257.17:01:43.44#ibcon#enter sib2, iclass 15, count 0 2006.257.17:01:43.44#ibcon#flushed, iclass 15, count 0 2006.257.17:01:43.44#ibcon#about to write, iclass 15, count 0 2006.257.17:01:43.44#ibcon#wrote, iclass 15, count 0 2006.257.17:01:43.44#ibcon#about to read 3, iclass 15, count 0 2006.257.17:01:43.46#ibcon#read 3, iclass 15, count 0 2006.257.17:01:43.46#ibcon#about to read 4, iclass 15, count 0 2006.257.17:01:43.46#ibcon#read 4, iclass 15, count 0 2006.257.17:01:43.46#ibcon#about to read 5, iclass 15, count 0 2006.257.17:01:43.46#ibcon#read 5, iclass 15, count 0 2006.257.17:01:43.46#ibcon#about to read 6, iclass 15, count 0 2006.257.17:01:43.46#ibcon#read 6, iclass 15, count 0 2006.257.17:01:43.46#ibcon#end of sib2, iclass 15, count 0 2006.257.17:01:43.46#ibcon#*mode == 0, iclass 15, count 0 2006.257.17:01:43.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.17:01:43.46#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:01:43.46#ibcon#*before write, iclass 15, count 0 2006.257.17:01:43.46#ibcon#enter sib2, iclass 15, count 0 2006.257.17:01:43.46#ibcon#flushed, iclass 15, count 0 2006.257.17:01:43.46#ibcon#about to write, iclass 15, count 0 2006.257.17:01:43.46#ibcon#wrote, iclass 15, count 0 2006.257.17:01:43.46#ibcon#about to read 3, iclass 15, count 0 2006.257.17:01:43.50#ibcon#read 3, iclass 15, count 0 2006.257.17:01:43.50#ibcon#about to read 4, iclass 15, count 0 2006.257.17:01:43.50#ibcon#read 4, iclass 15, count 0 2006.257.17:01:43.50#ibcon#about to read 5, iclass 15, count 0 2006.257.17:01:43.50#ibcon#read 5, iclass 15, count 0 2006.257.17:01:43.50#ibcon#about to read 6, iclass 15, count 0 2006.257.17:01:43.50#ibcon#read 6, iclass 15, count 0 2006.257.17:01:43.50#ibcon#end of sib2, iclass 15, count 0 2006.257.17:01:43.50#ibcon#*after write, iclass 15, count 0 2006.257.17:01:43.50#ibcon#*before return 0, iclass 15, count 0 2006.257.17:01:43.50#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:43.50#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:43.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.17:01:43.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.17:01:43.50$vck44/va=7,4 2006.257.17:01:43.50#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.17:01:43.50#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.17:01:43.50#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:43.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:43.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:43.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:43.56#ibcon#enter wrdev, iclass 17, count 2 2006.257.17:01:43.56#ibcon#first serial, iclass 17, count 2 2006.257.17:01:43.56#ibcon#enter sib2, iclass 17, count 2 2006.257.17:01:43.56#ibcon#flushed, iclass 17, count 2 2006.257.17:01:43.56#ibcon#about to write, iclass 17, count 2 2006.257.17:01:43.56#ibcon#wrote, iclass 17, count 2 2006.257.17:01:43.56#ibcon#about to read 3, iclass 17, count 2 2006.257.17:01:43.58#ibcon#read 3, iclass 17, count 2 2006.257.17:01:43.58#ibcon#about to read 4, iclass 17, count 2 2006.257.17:01:43.58#ibcon#read 4, iclass 17, count 2 2006.257.17:01:43.58#ibcon#about to read 5, iclass 17, count 2 2006.257.17:01:43.58#ibcon#read 5, iclass 17, count 2 2006.257.17:01:43.58#ibcon#about to read 6, iclass 17, count 2 2006.257.17:01:43.58#ibcon#read 6, iclass 17, count 2 2006.257.17:01:43.58#ibcon#end of sib2, iclass 17, count 2 2006.257.17:01:43.58#ibcon#*mode == 0, iclass 17, count 2 2006.257.17:01:43.58#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.17:01:43.58#ibcon#[25=AT07-04\r\n] 2006.257.17:01:43.58#ibcon#*before write, iclass 17, count 2 2006.257.17:01:43.58#ibcon#enter sib2, iclass 17, count 2 2006.257.17:01:43.58#ibcon#flushed, iclass 17, count 2 2006.257.17:01:43.58#ibcon#about to write, iclass 17, count 2 2006.257.17:01:43.58#ibcon#wrote, iclass 17, count 2 2006.257.17:01:43.58#ibcon#about to read 3, iclass 17, count 2 2006.257.17:01:43.61#ibcon#read 3, iclass 17, count 2 2006.257.17:01:43.61#ibcon#about to read 4, iclass 17, count 2 2006.257.17:01:43.61#ibcon#read 4, iclass 17, count 2 2006.257.17:01:43.61#ibcon#about to read 5, iclass 17, count 2 2006.257.17:01:43.61#ibcon#read 5, iclass 17, count 2 2006.257.17:01:43.61#ibcon#about to read 6, iclass 17, count 2 2006.257.17:01:43.61#ibcon#read 6, iclass 17, count 2 2006.257.17:01:43.61#ibcon#end of sib2, iclass 17, count 2 2006.257.17:01:43.61#ibcon#*after write, iclass 17, count 2 2006.257.17:01:43.61#ibcon#*before return 0, iclass 17, count 2 2006.257.17:01:43.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:43.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:43.61#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.17:01:43.61#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:43.61#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:43.73#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:43.73#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:43.73#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:01:43.73#ibcon#first serial, iclass 17, count 0 2006.257.17:01:43.73#ibcon#enter sib2, iclass 17, count 0 2006.257.17:01:43.73#ibcon#flushed, iclass 17, count 0 2006.257.17:01:43.73#ibcon#about to write, iclass 17, count 0 2006.257.17:01:43.73#ibcon#wrote, iclass 17, count 0 2006.257.17:01:43.73#ibcon#about to read 3, iclass 17, count 0 2006.257.17:01:43.75#ibcon#read 3, iclass 17, count 0 2006.257.17:01:43.75#ibcon#about to read 4, iclass 17, count 0 2006.257.17:01:43.75#ibcon#read 4, iclass 17, count 0 2006.257.17:01:43.75#ibcon#about to read 5, iclass 17, count 0 2006.257.17:01:43.75#ibcon#read 5, iclass 17, count 0 2006.257.17:01:43.75#ibcon#about to read 6, iclass 17, count 0 2006.257.17:01:43.75#ibcon#read 6, iclass 17, count 0 2006.257.17:01:43.75#ibcon#end of sib2, iclass 17, count 0 2006.257.17:01:43.75#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:01:43.75#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:01:43.75#ibcon#[25=USB\r\n] 2006.257.17:01:43.75#ibcon#*before write, iclass 17, count 0 2006.257.17:01:43.75#ibcon#enter sib2, iclass 17, count 0 2006.257.17:01:43.75#ibcon#flushed, iclass 17, count 0 2006.257.17:01:43.75#ibcon#about to write, iclass 17, count 0 2006.257.17:01:43.75#ibcon#wrote, iclass 17, count 0 2006.257.17:01:43.75#ibcon#about to read 3, iclass 17, count 0 2006.257.17:01:43.78#ibcon#read 3, iclass 17, count 0 2006.257.17:01:43.78#ibcon#about to read 4, iclass 17, count 0 2006.257.17:01:43.78#ibcon#read 4, iclass 17, count 0 2006.257.17:01:43.78#ibcon#about to read 5, iclass 17, count 0 2006.257.17:01:43.78#ibcon#read 5, iclass 17, count 0 2006.257.17:01:43.78#ibcon#about to read 6, iclass 17, count 0 2006.257.17:01:43.78#ibcon#read 6, iclass 17, count 0 2006.257.17:01:43.78#ibcon#end of sib2, iclass 17, count 0 2006.257.17:01:43.78#ibcon#*after write, iclass 17, count 0 2006.257.17:01:43.78#ibcon#*before return 0, iclass 17, count 0 2006.257.17:01:43.78#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:43.78#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:43.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:01:43.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:01:43.78$vck44/valo=8,884.99 2006.257.17:01:43.78#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.17:01:43.78#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.17:01:43.78#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:43.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:43.78#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:43.78#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:43.78#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:01:43.78#ibcon#first serial, iclass 19, count 0 2006.257.17:01:43.78#ibcon#enter sib2, iclass 19, count 0 2006.257.17:01:43.78#ibcon#flushed, iclass 19, count 0 2006.257.17:01:43.78#ibcon#about to write, iclass 19, count 0 2006.257.17:01:43.78#ibcon#wrote, iclass 19, count 0 2006.257.17:01:43.78#ibcon#about to read 3, iclass 19, count 0 2006.257.17:01:43.80#ibcon#read 3, iclass 19, count 0 2006.257.17:01:43.80#ibcon#about to read 4, iclass 19, count 0 2006.257.17:01:43.80#ibcon#read 4, iclass 19, count 0 2006.257.17:01:43.80#ibcon#about to read 5, iclass 19, count 0 2006.257.17:01:43.80#ibcon#read 5, iclass 19, count 0 2006.257.17:01:43.80#ibcon#about to read 6, iclass 19, count 0 2006.257.17:01:43.80#ibcon#read 6, iclass 19, count 0 2006.257.17:01:43.80#ibcon#end of sib2, iclass 19, count 0 2006.257.17:01:43.80#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:01:43.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:01:43.80#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:01:43.80#ibcon#*before write, iclass 19, count 0 2006.257.17:01:43.80#ibcon#enter sib2, iclass 19, count 0 2006.257.17:01:43.80#ibcon#flushed, iclass 19, count 0 2006.257.17:01:43.80#ibcon#about to write, iclass 19, count 0 2006.257.17:01:43.80#ibcon#wrote, iclass 19, count 0 2006.257.17:01:43.80#ibcon#about to read 3, iclass 19, count 0 2006.257.17:01:43.84#ibcon#read 3, iclass 19, count 0 2006.257.17:01:43.84#ibcon#about to read 4, iclass 19, count 0 2006.257.17:01:43.84#ibcon#read 4, iclass 19, count 0 2006.257.17:01:43.84#ibcon#about to read 5, iclass 19, count 0 2006.257.17:01:43.84#ibcon#read 5, iclass 19, count 0 2006.257.17:01:43.84#ibcon#about to read 6, iclass 19, count 0 2006.257.17:01:43.84#ibcon#read 6, iclass 19, count 0 2006.257.17:01:43.84#ibcon#end of sib2, iclass 19, count 0 2006.257.17:01:43.84#ibcon#*after write, iclass 19, count 0 2006.257.17:01:43.84#ibcon#*before return 0, iclass 19, count 0 2006.257.17:01:43.84#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:43.84#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:43.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:01:43.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:01:43.84$vck44/va=8,4 2006.257.17:01:43.84#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.17:01:43.84#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.17:01:43.84#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:43.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:01:43.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:01:43.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:01:43.90#ibcon#enter wrdev, iclass 21, count 2 2006.257.17:01:43.90#ibcon#first serial, iclass 21, count 2 2006.257.17:01:43.90#ibcon#enter sib2, iclass 21, count 2 2006.257.17:01:43.90#ibcon#flushed, iclass 21, count 2 2006.257.17:01:43.90#ibcon#about to write, iclass 21, count 2 2006.257.17:01:43.90#ibcon#wrote, iclass 21, count 2 2006.257.17:01:43.90#ibcon#about to read 3, iclass 21, count 2 2006.257.17:01:43.92#ibcon#read 3, iclass 21, count 2 2006.257.17:01:43.92#ibcon#about to read 4, iclass 21, count 2 2006.257.17:01:43.92#ibcon#read 4, iclass 21, count 2 2006.257.17:01:43.92#ibcon#about to read 5, iclass 21, count 2 2006.257.17:01:43.92#ibcon#read 5, iclass 21, count 2 2006.257.17:01:43.92#ibcon#about to read 6, iclass 21, count 2 2006.257.17:01:43.92#ibcon#read 6, iclass 21, count 2 2006.257.17:01:43.92#ibcon#end of sib2, iclass 21, count 2 2006.257.17:01:43.92#ibcon#*mode == 0, iclass 21, count 2 2006.257.17:01:43.92#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.17:01:43.92#ibcon#[25=AT08-04\r\n] 2006.257.17:01:43.92#ibcon#*before write, iclass 21, count 2 2006.257.17:01:43.92#ibcon#enter sib2, iclass 21, count 2 2006.257.17:01:43.92#ibcon#flushed, iclass 21, count 2 2006.257.17:01:43.92#ibcon#about to write, iclass 21, count 2 2006.257.17:01:43.92#ibcon#wrote, iclass 21, count 2 2006.257.17:01:43.92#ibcon#about to read 3, iclass 21, count 2 2006.257.17:01:43.95#ibcon#read 3, iclass 21, count 2 2006.257.17:01:43.95#ibcon#about to read 4, iclass 21, count 2 2006.257.17:01:43.95#ibcon#read 4, iclass 21, count 2 2006.257.17:01:43.95#ibcon#about to read 5, iclass 21, count 2 2006.257.17:01:43.95#ibcon#read 5, iclass 21, count 2 2006.257.17:01:43.95#ibcon#about to read 6, iclass 21, count 2 2006.257.17:01:43.95#ibcon#read 6, iclass 21, count 2 2006.257.17:01:43.95#ibcon#end of sib2, iclass 21, count 2 2006.257.17:01:43.95#ibcon#*after write, iclass 21, count 2 2006.257.17:01:43.95#ibcon#*before return 0, iclass 21, count 2 2006.257.17:01:43.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:01:43.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:01:43.95#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.17:01:43.95#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:43.95#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:01:44.07#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:01:44.07#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:01:44.07#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:01:44.07#ibcon#first serial, iclass 21, count 0 2006.257.17:01:44.07#ibcon#enter sib2, iclass 21, count 0 2006.257.17:01:44.07#ibcon#flushed, iclass 21, count 0 2006.257.17:01:44.07#ibcon#about to write, iclass 21, count 0 2006.257.17:01:44.07#ibcon#wrote, iclass 21, count 0 2006.257.17:01:44.07#ibcon#about to read 3, iclass 21, count 0 2006.257.17:01:44.09#ibcon#read 3, iclass 21, count 0 2006.257.17:01:44.09#ibcon#about to read 4, iclass 21, count 0 2006.257.17:01:44.09#ibcon#read 4, iclass 21, count 0 2006.257.17:01:44.09#ibcon#about to read 5, iclass 21, count 0 2006.257.17:01:44.09#ibcon#read 5, iclass 21, count 0 2006.257.17:01:44.09#ibcon#about to read 6, iclass 21, count 0 2006.257.17:01:44.09#ibcon#read 6, iclass 21, count 0 2006.257.17:01:44.09#ibcon#end of sib2, iclass 21, count 0 2006.257.17:01:44.09#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:01:44.09#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:01:44.09#ibcon#[25=USB\r\n] 2006.257.17:01:44.09#ibcon#*before write, iclass 21, count 0 2006.257.17:01:44.09#ibcon#enter sib2, iclass 21, count 0 2006.257.17:01:44.09#ibcon#flushed, iclass 21, count 0 2006.257.17:01:44.09#ibcon#about to write, iclass 21, count 0 2006.257.17:01:44.09#ibcon#wrote, iclass 21, count 0 2006.257.17:01:44.09#ibcon#about to read 3, iclass 21, count 0 2006.257.17:01:44.12#ibcon#read 3, iclass 21, count 0 2006.257.17:01:44.12#ibcon#about to read 4, iclass 21, count 0 2006.257.17:01:44.12#ibcon#read 4, iclass 21, count 0 2006.257.17:01:44.12#ibcon#about to read 5, iclass 21, count 0 2006.257.17:01:44.12#ibcon#read 5, iclass 21, count 0 2006.257.17:01:44.12#ibcon#about to read 6, iclass 21, count 0 2006.257.17:01:44.12#ibcon#read 6, iclass 21, count 0 2006.257.17:01:44.12#ibcon#end of sib2, iclass 21, count 0 2006.257.17:01:44.12#ibcon#*after write, iclass 21, count 0 2006.257.17:01:44.12#ibcon#*before return 0, iclass 21, count 0 2006.257.17:01:44.12#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:01:44.12#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:01:44.12#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:01:44.12#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:01:44.12$vck44/vblo=1,629.99 2006.257.17:01:44.12#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.17:01:44.12#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.17:01:44.12#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:44.12#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:44.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:44.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:44.12#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:01:44.12#ibcon#first serial, iclass 23, count 0 2006.257.17:01:44.12#ibcon#enter sib2, iclass 23, count 0 2006.257.17:01:44.12#ibcon#flushed, iclass 23, count 0 2006.257.17:01:44.12#ibcon#about to write, iclass 23, count 0 2006.257.17:01:44.12#ibcon#wrote, iclass 23, count 0 2006.257.17:01:44.12#ibcon#about to read 3, iclass 23, count 0 2006.257.17:01:44.14#ibcon#read 3, iclass 23, count 0 2006.257.17:01:44.14#ibcon#about to read 4, iclass 23, count 0 2006.257.17:01:44.14#ibcon#read 4, iclass 23, count 0 2006.257.17:01:44.14#ibcon#about to read 5, iclass 23, count 0 2006.257.17:01:44.14#ibcon#read 5, iclass 23, count 0 2006.257.17:01:44.14#ibcon#about to read 6, iclass 23, count 0 2006.257.17:01:44.14#ibcon#read 6, iclass 23, count 0 2006.257.17:01:44.14#ibcon#end of sib2, iclass 23, count 0 2006.257.17:01:44.14#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:01:44.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:01:44.14#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:01:44.14#ibcon#*before write, iclass 23, count 0 2006.257.17:01:44.14#ibcon#enter sib2, iclass 23, count 0 2006.257.17:01:44.14#ibcon#flushed, iclass 23, count 0 2006.257.17:01:44.14#ibcon#about to write, iclass 23, count 0 2006.257.17:01:44.14#ibcon#wrote, iclass 23, count 0 2006.257.17:01:44.14#ibcon#about to read 3, iclass 23, count 0 2006.257.17:01:44.18#ibcon#read 3, iclass 23, count 0 2006.257.17:01:44.18#ibcon#about to read 4, iclass 23, count 0 2006.257.17:01:44.18#ibcon#read 4, iclass 23, count 0 2006.257.17:01:44.18#ibcon#about to read 5, iclass 23, count 0 2006.257.17:01:44.18#ibcon#read 5, iclass 23, count 0 2006.257.17:01:44.18#ibcon#about to read 6, iclass 23, count 0 2006.257.17:01:44.18#ibcon#read 6, iclass 23, count 0 2006.257.17:01:44.18#ibcon#end of sib2, iclass 23, count 0 2006.257.17:01:44.18#ibcon#*after write, iclass 23, count 0 2006.257.17:01:44.18#ibcon#*before return 0, iclass 23, count 0 2006.257.17:01:44.18#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:44.18#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:01:44.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:01:44.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:01:44.18$vck44/vb=1,4 2006.257.17:01:44.18#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.17:01:44.18#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.17:01:44.18#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:44.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:44.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:44.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:44.18#ibcon#enter wrdev, iclass 25, count 2 2006.257.17:01:44.18#ibcon#first serial, iclass 25, count 2 2006.257.17:01:44.18#ibcon#enter sib2, iclass 25, count 2 2006.257.17:01:44.18#ibcon#flushed, iclass 25, count 2 2006.257.17:01:44.18#ibcon#about to write, iclass 25, count 2 2006.257.17:01:44.18#ibcon#wrote, iclass 25, count 2 2006.257.17:01:44.18#ibcon#about to read 3, iclass 25, count 2 2006.257.17:01:44.20#ibcon#read 3, iclass 25, count 2 2006.257.17:01:44.20#ibcon#about to read 4, iclass 25, count 2 2006.257.17:01:44.20#ibcon#read 4, iclass 25, count 2 2006.257.17:01:44.20#ibcon#about to read 5, iclass 25, count 2 2006.257.17:01:44.20#ibcon#read 5, iclass 25, count 2 2006.257.17:01:44.20#ibcon#about to read 6, iclass 25, count 2 2006.257.17:01:44.20#ibcon#read 6, iclass 25, count 2 2006.257.17:01:44.20#ibcon#end of sib2, iclass 25, count 2 2006.257.17:01:44.20#ibcon#*mode == 0, iclass 25, count 2 2006.257.17:01:44.20#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.17:01:44.20#ibcon#[27=AT01-04\r\n] 2006.257.17:01:44.20#ibcon#*before write, iclass 25, count 2 2006.257.17:01:44.20#ibcon#enter sib2, iclass 25, count 2 2006.257.17:01:44.20#ibcon#flushed, iclass 25, count 2 2006.257.17:01:44.20#ibcon#about to write, iclass 25, count 2 2006.257.17:01:44.20#ibcon#wrote, iclass 25, count 2 2006.257.17:01:44.20#ibcon#about to read 3, iclass 25, count 2 2006.257.17:01:44.23#ibcon#read 3, iclass 25, count 2 2006.257.17:01:44.23#ibcon#about to read 4, iclass 25, count 2 2006.257.17:01:44.23#ibcon#read 4, iclass 25, count 2 2006.257.17:01:44.23#ibcon#about to read 5, iclass 25, count 2 2006.257.17:01:44.23#ibcon#read 5, iclass 25, count 2 2006.257.17:01:44.23#ibcon#about to read 6, iclass 25, count 2 2006.257.17:01:44.23#ibcon#read 6, iclass 25, count 2 2006.257.17:01:44.23#ibcon#end of sib2, iclass 25, count 2 2006.257.17:01:44.23#ibcon#*after write, iclass 25, count 2 2006.257.17:01:44.23#ibcon#*before return 0, iclass 25, count 2 2006.257.17:01:44.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:44.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:01:44.23#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.17:01:44.23#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:44.23#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:44.35#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:44.35#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:44.35#ibcon#enter wrdev, iclass 25, count 0 2006.257.17:01:44.35#ibcon#first serial, iclass 25, count 0 2006.257.17:01:44.35#ibcon#enter sib2, iclass 25, count 0 2006.257.17:01:44.35#ibcon#flushed, iclass 25, count 0 2006.257.17:01:44.35#ibcon#about to write, iclass 25, count 0 2006.257.17:01:44.35#ibcon#wrote, iclass 25, count 0 2006.257.17:01:44.35#ibcon#about to read 3, iclass 25, count 0 2006.257.17:01:44.37#ibcon#read 3, iclass 25, count 0 2006.257.17:01:44.37#ibcon#about to read 4, iclass 25, count 0 2006.257.17:01:44.37#ibcon#read 4, iclass 25, count 0 2006.257.17:01:44.37#ibcon#about to read 5, iclass 25, count 0 2006.257.17:01:44.37#ibcon#read 5, iclass 25, count 0 2006.257.17:01:44.37#ibcon#about to read 6, iclass 25, count 0 2006.257.17:01:44.37#ibcon#read 6, iclass 25, count 0 2006.257.17:01:44.37#ibcon#end of sib2, iclass 25, count 0 2006.257.17:01:44.37#ibcon#*mode == 0, iclass 25, count 0 2006.257.17:01:44.37#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.17:01:44.37#ibcon#[27=USB\r\n] 2006.257.17:01:44.37#ibcon#*before write, iclass 25, count 0 2006.257.17:01:44.37#ibcon#enter sib2, iclass 25, count 0 2006.257.17:01:44.37#ibcon#flushed, iclass 25, count 0 2006.257.17:01:44.37#ibcon#about to write, iclass 25, count 0 2006.257.17:01:44.37#ibcon#wrote, iclass 25, count 0 2006.257.17:01:44.37#ibcon#about to read 3, iclass 25, count 0 2006.257.17:01:44.40#ibcon#read 3, iclass 25, count 0 2006.257.17:01:44.40#ibcon#about to read 4, iclass 25, count 0 2006.257.17:01:44.40#ibcon#read 4, iclass 25, count 0 2006.257.17:01:44.40#ibcon#about to read 5, iclass 25, count 0 2006.257.17:01:44.40#ibcon#read 5, iclass 25, count 0 2006.257.17:01:44.40#ibcon#about to read 6, iclass 25, count 0 2006.257.17:01:44.40#ibcon#read 6, iclass 25, count 0 2006.257.17:01:44.40#ibcon#end of sib2, iclass 25, count 0 2006.257.17:01:44.40#ibcon#*after write, iclass 25, count 0 2006.257.17:01:44.40#ibcon#*before return 0, iclass 25, count 0 2006.257.17:01:44.40#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:44.40#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:01:44.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.17:01:44.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.17:01:44.40$vck44/vblo=2,634.99 2006.257.17:01:44.40#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.17:01:44.40#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.17:01:44.40#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:44.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:44.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:44.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:44.40#ibcon#enter wrdev, iclass 27, count 0 2006.257.17:01:44.40#ibcon#first serial, iclass 27, count 0 2006.257.17:01:44.40#ibcon#enter sib2, iclass 27, count 0 2006.257.17:01:44.40#ibcon#flushed, iclass 27, count 0 2006.257.17:01:44.40#ibcon#about to write, iclass 27, count 0 2006.257.17:01:44.40#ibcon#wrote, iclass 27, count 0 2006.257.17:01:44.40#ibcon#about to read 3, iclass 27, count 0 2006.257.17:01:44.42#ibcon#read 3, iclass 27, count 0 2006.257.17:01:44.42#ibcon#about to read 4, iclass 27, count 0 2006.257.17:01:44.42#ibcon#read 4, iclass 27, count 0 2006.257.17:01:44.42#ibcon#about to read 5, iclass 27, count 0 2006.257.17:01:44.42#ibcon#read 5, iclass 27, count 0 2006.257.17:01:44.42#ibcon#about to read 6, iclass 27, count 0 2006.257.17:01:44.42#ibcon#read 6, iclass 27, count 0 2006.257.17:01:44.42#ibcon#end of sib2, iclass 27, count 0 2006.257.17:01:44.42#ibcon#*mode == 0, iclass 27, count 0 2006.257.17:01:44.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.17:01:44.42#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:01:44.42#ibcon#*before write, iclass 27, count 0 2006.257.17:01:44.42#ibcon#enter sib2, iclass 27, count 0 2006.257.17:01:44.42#ibcon#flushed, iclass 27, count 0 2006.257.17:01:44.42#ibcon#about to write, iclass 27, count 0 2006.257.17:01:44.42#ibcon#wrote, iclass 27, count 0 2006.257.17:01:44.42#ibcon#about to read 3, iclass 27, count 0 2006.257.17:01:44.46#ibcon#read 3, iclass 27, count 0 2006.257.17:01:44.46#ibcon#about to read 4, iclass 27, count 0 2006.257.17:01:44.46#ibcon#read 4, iclass 27, count 0 2006.257.17:01:44.46#ibcon#about to read 5, iclass 27, count 0 2006.257.17:01:44.46#ibcon#read 5, iclass 27, count 0 2006.257.17:01:44.46#ibcon#about to read 6, iclass 27, count 0 2006.257.17:01:44.46#ibcon#read 6, iclass 27, count 0 2006.257.17:01:44.46#ibcon#end of sib2, iclass 27, count 0 2006.257.17:01:44.46#ibcon#*after write, iclass 27, count 0 2006.257.17:01:44.46#ibcon#*before return 0, iclass 27, count 0 2006.257.17:01:44.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:44.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:01:44.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.17:01:44.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.17:01:44.46$vck44/vb=2,5 2006.257.17:01:44.46#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.17:01:44.46#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.17:01:44.46#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:44.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:44.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:44.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:44.52#ibcon#enter wrdev, iclass 29, count 2 2006.257.17:01:44.52#ibcon#first serial, iclass 29, count 2 2006.257.17:01:44.52#ibcon#enter sib2, iclass 29, count 2 2006.257.17:01:44.52#ibcon#flushed, iclass 29, count 2 2006.257.17:01:44.52#ibcon#about to write, iclass 29, count 2 2006.257.17:01:44.52#ibcon#wrote, iclass 29, count 2 2006.257.17:01:44.52#ibcon#about to read 3, iclass 29, count 2 2006.257.17:01:44.54#ibcon#read 3, iclass 29, count 2 2006.257.17:01:44.54#ibcon#about to read 4, iclass 29, count 2 2006.257.17:01:44.54#ibcon#read 4, iclass 29, count 2 2006.257.17:01:44.54#ibcon#about to read 5, iclass 29, count 2 2006.257.17:01:44.54#ibcon#read 5, iclass 29, count 2 2006.257.17:01:44.54#ibcon#about to read 6, iclass 29, count 2 2006.257.17:01:44.54#ibcon#read 6, iclass 29, count 2 2006.257.17:01:44.54#ibcon#end of sib2, iclass 29, count 2 2006.257.17:01:44.54#ibcon#*mode == 0, iclass 29, count 2 2006.257.17:01:44.54#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.17:01:44.54#ibcon#[27=AT02-05\r\n] 2006.257.17:01:44.54#ibcon#*before write, iclass 29, count 2 2006.257.17:01:44.54#ibcon#enter sib2, iclass 29, count 2 2006.257.17:01:44.54#ibcon#flushed, iclass 29, count 2 2006.257.17:01:44.54#ibcon#about to write, iclass 29, count 2 2006.257.17:01:44.54#ibcon#wrote, iclass 29, count 2 2006.257.17:01:44.54#ibcon#about to read 3, iclass 29, count 2 2006.257.17:01:44.57#ibcon#read 3, iclass 29, count 2 2006.257.17:01:44.57#ibcon#about to read 4, iclass 29, count 2 2006.257.17:01:44.57#ibcon#read 4, iclass 29, count 2 2006.257.17:01:44.57#ibcon#about to read 5, iclass 29, count 2 2006.257.17:01:44.57#ibcon#read 5, iclass 29, count 2 2006.257.17:01:44.57#ibcon#about to read 6, iclass 29, count 2 2006.257.17:01:44.57#ibcon#read 6, iclass 29, count 2 2006.257.17:01:44.57#ibcon#end of sib2, iclass 29, count 2 2006.257.17:01:44.57#ibcon#*after write, iclass 29, count 2 2006.257.17:01:44.57#ibcon#*before return 0, iclass 29, count 2 2006.257.17:01:44.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:44.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:01:44.57#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.17:01:44.57#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:44.57#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:44.69#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:44.69#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:44.69#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:01:44.69#ibcon#first serial, iclass 29, count 0 2006.257.17:01:44.69#ibcon#enter sib2, iclass 29, count 0 2006.257.17:01:44.69#ibcon#flushed, iclass 29, count 0 2006.257.17:01:44.69#ibcon#about to write, iclass 29, count 0 2006.257.17:01:44.69#ibcon#wrote, iclass 29, count 0 2006.257.17:01:44.69#ibcon#about to read 3, iclass 29, count 0 2006.257.17:01:44.71#ibcon#read 3, iclass 29, count 0 2006.257.17:01:44.71#ibcon#about to read 4, iclass 29, count 0 2006.257.17:01:44.71#ibcon#read 4, iclass 29, count 0 2006.257.17:01:44.71#ibcon#about to read 5, iclass 29, count 0 2006.257.17:01:44.71#ibcon#read 5, iclass 29, count 0 2006.257.17:01:44.71#ibcon#about to read 6, iclass 29, count 0 2006.257.17:01:44.71#ibcon#read 6, iclass 29, count 0 2006.257.17:01:44.71#ibcon#end of sib2, iclass 29, count 0 2006.257.17:01:44.71#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:01:44.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:01:44.71#ibcon#[27=USB\r\n] 2006.257.17:01:44.71#ibcon#*before write, iclass 29, count 0 2006.257.17:01:44.71#ibcon#enter sib2, iclass 29, count 0 2006.257.17:01:44.71#ibcon#flushed, iclass 29, count 0 2006.257.17:01:44.71#ibcon#about to write, iclass 29, count 0 2006.257.17:01:44.71#ibcon#wrote, iclass 29, count 0 2006.257.17:01:44.71#ibcon#about to read 3, iclass 29, count 0 2006.257.17:01:44.74#ibcon#read 3, iclass 29, count 0 2006.257.17:01:44.74#ibcon#about to read 4, iclass 29, count 0 2006.257.17:01:44.74#ibcon#read 4, iclass 29, count 0 2006.257.17:01:44.74#ibcon#about to read 5, iclass 29, count 0 2006.257.17:01:44.74#ibcon#read 5, iclass 29, count 0 2006.257.17:01:44.74#ibcon#about to read 6, iclass 29, count 0 2006.257.17:01:44.74#ibcon#read 6, iclass 29, count 0 2006.257.17:01:44.74#ibcon#end of sib2, iclass 29, count 0 2006.257.17:01:44.74#ibcon#*after write, iclass 29, count 0 2006.257.17:01:44.74#ibcon#*before return 0, iclass 29, count 0 2006.257.17:01:44.74#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:44.74#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:01:44.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:01:44.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:01:44.74$vck44/vblo=3,649.99 2006.257.17:01:44.74#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.17:01:44.74#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.17:01:44.74#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:44.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:44.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:44.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:44.74#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:01:44.74#ibcon#first serial, iclass 31, count 0 2006.257.17:01:44.74#ibcon#enter sib2, iclass 31, count 0 2006.257.17:01:44.74#ibcon#flushed, iclass 31, count 0 2006.257.17:01:44.74#ibcon#about to write, iclass 31, count 0 2006.257.17:01:44.74#ibcon#wrote, iclass 31, count 0 2006.257.17:01:44.74#ibcon#about to read 3, iclass 31, count 0 2006.257.17:01:44.76#ibcon#read 3, iclass 31, count 0 2006.257.17:01:44.76#ibcon#about to read 4, iclass 31, count 0 2006.257.17:01:44.76#ibcon#read 4, iclass 31, count 0 2006.257.17:01:44.76#ibcon#about to read 5, iclass 31, count 0 2006.257.17:01:44.76#ibcon#read 5, iclass 31, count 0 2006.257.17:01:44.76#ibcon#about to read 6, iclass 31, count 0 2006.257.17:01:44.76#ibcon#read 6, iclass 31, count 0 2006.257.17:01:44.76#ibcon#end of sib2, iclass 31, count 0 2006.257.17:01:44.76#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:01:44.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:01:44.76#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:01:44.76#ibcon#*before write, iclass 31, count 0 2006.257.17:01:44.76#ibcon#enter sib2, iclass 31, count 0 2006.257.17:01:44.76#ibcon#flushed, iclass 31, count 0 2006.257.17:01:44.76#ibcon#about to write, iclass 31, count 0 2006.257.17:01:44.76#ibcon#wrote, iclass 31, count 0 2006.257.17:01:44.76#ibcon#about to read 3, iclass 31, count 0 2006.257.17:01:44.80#ibcon#read 3, iclass 31, count 0 2006.257.17:01:44.80#ibcon#about to read 4, iclass 31, count 0 2006.257.17:01:44.80#ibcon#read 4, iclass 31, count 0 2006.257.17:01:44.80#ibcon#about to read 5, iclass 31, count 0 2006.257.17:01:44.80#ibcon#read 5, iclass 31, count 0 2006.257.17:01:44.80#ibcon#about to read 6, iclass 31, count 0 2006.257.17:01:44.80#ibcon#read 6, iclass 31, count 0 2006.257.17:01:44.80#ibcon#end of sib2, iclass 31, count 0 2006.257.17:01:44.80#ibcon#*after write, iclass 31, count 0 2006.257.17:01:44.80#ibcon#*before return 0, iclass 31, count 0 2006.257.17:01:44.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:44.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:01:44.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:01:44.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:01:44.80$vck44/vb=3,4 2006.257.17:01:44.80#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.17:01:44.80#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.17:01:44.80#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:44.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:44.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:44.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:44.86#ibcon#enter wrdev, iclass 33, count 2 2006.257.17:01:44.86#ibcon#first serial, iclass 33, count 2 2006.257.17:01:44.86#ibcon#enter sib2, iclass 33, count 2 2006.257.17:01:44.86#ibcon#flushed, iclass 33, count 2 2006.257.17:01:44.86#ibcon#about to write, iclass 33, count 2 2006.257.17:01:44.86#ibcon#wrote, iclass 33, count 2 2006.257.17:01:44.86#ibcon#about to read 3, iclass 33, count 2 2006.257.17:01:44.88#ibcon#read 3, iclass 33, count 2 2006.257.17:01:44.88#ibcon#about to read 4, iclass 33, count 2 2006.257.17:01:44.88#ibcon#read 4, iclass 33, count 2 2006.257.17:01:44.88#ibcon#about to read 5, iclass 33, count 2 2006.257.17:01:44.88#ibcon#read 5, iclass 33, count 2 2006.257.17:01:44.88#ibcon#about to read 6, iclass 33, count 2 2006.257.17:01:44.88#ibcon#read 6, iclass 33, count 2 2006.257.17:01:44.88#ibcon#end of sib2, iclass 33, count 2 2006.257.17:01:44.88#ibcon#*mode == 0, iclass 33, count 2 2006.257.17:01:44.88#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.17:01:44.88#ibcon#[27=AT03-04\r\n] 2006.257.17:01:44.88#ibcon#*before write, iclass 33, count 2 2006.257.17:01:44.88#ibcon#enter sib2, iclass 33, count 2 2006.257.17:01:44.88#ibcon#flushed, iclass 33, count 2 2006.257.17:01:44.88#ibcon#about to write, iclass 33, count 2 2006.257.17:01:44.88#ibcon#wrote, iclass 33, count 2 2006.257.17:01:44.88#ibcon#about to read 3, iclass 33, count 2 2006.257.17:01:44.91#ibcon#read 3, iclass 33, count 2 2006.257.17:01:44.91#ibcon#about to read 4, iclass 33, count 2 2006.257.17:01:44.91#ibcon#read 4, iclass 33, count 2 2006.257.17:01:44.91#ibcon#about to read 5, iclass 33, count 2 2006.257.17:01:44.91#ibcon#read 5, iclass 33, count 2 2006.257.17:01:44.91#ibcon#about to read 6, iclass 33, count 2 2006.257.17:01:44.91#ibcon#read 6, iclass 33, count 2 2006.257.17:01:44.91#ibcon#end of sib2, iclass 33, count 2 2006.257.17:01:44.91#ibcon#*after write, iclass 33, count 2 2006.257.17:01:44.91#ibcon#*before return 0, iclass 33, count 2 2006.257.17:01:44.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:44.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:01:44.91#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.17:01:44.91#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:44.91#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:45.03#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:45.03#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:45.03#ibcon#enter wrdev, iclass 33, count 0 2006.257.17:01:45.03#ibcon#first serial, iclass 33, count 0 2006.257.17:01:45.03#ibcon#enter sib2, iclass 33, count 0 2006.257.17:01:45.03#ibcon#flushed, iclass 33, count 0 2006.257.17:01:45.03#ibcon#about to write, iclass 33, count 0 2006.257.17:01:45.03#ibcon#wrote, iclass 33, count 0 2006.257.17:01:45.03#ibcon#about to read 3, iclass 33, count 0 2006.257.17:01:45.05#ibcon#read 3, iclass 33, count 0 2006.257.17:01:45.05#ibcon#about to read 4, iclass 33, count 0 2006.257.17:01:45.05#ibcon#read 4, iclass 33, count 0 2006.257.17:01:45.05#ibcon#about to read 5, iclass 33, count 0 2006.257.17:01:45.05#ibcon#read 5, iclass 33, count 0 2006.257.17:01:45.05#ibcon#about to read 6, iclass 33, count 0 2006.257.17:01:45.05#ibcon#read 6, iclass 33, count 0 2006.257.17:01:45.05#ibcon#end of sib2, iclass 33, count 0 2006.257.17:01:45.05#ibcon#*mode == 0, iclass 33, count 0 2006.257.17:01:45.05#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.17:01:45.05#ibcon#[27=USB\r\n] 2006.257.17:01:45.05#ibcon#*before write, iclass 33, count 0 2006.257.17:01:45.05#ibcon#enter sib2, iclass 33, count 0 2006.257.17:01:45.05#ibcon#flushed, iclass 33, count 0 2006.257.17:01:45.05#ibcon#about to write, iclass 33, count 0 2006.257.17:01:45.05#ibcon#wrote, iclass 33, count 0 2006.257.17:01:45.05#ibcon#about to read 3, iclass 33, count 0 2006.257.17:01:45.08#ibcon#read 3, iclass 33, count 0 2006.257.17:01:45.08#ibcon#about to read 4, iclass 33, count 0 2006.257.17:01:45.08#ibcon#read 4, iclass 33, count 0 2006.257.17:01:45.08#ibcon#about to read 5, iclass 33, count 0 2006.257.17:01:45.08#ibcon#read 5, iclass 33, count 0 2006.257.17:01:45.08#ibcon#about to read 6, iclass 33, count 0 2006.257.17:01:45.08#ibcon#read 6, iclass 33, count 0 2006.257.17:01:45.08#ibcon#end of sib2, iclass 33, count 0 2006.257.17:01:45.08#ibcon#*after write, iclass 33, count 0 2006.257.17:01:45.08#ibcon#*before return 0, iclass 33, count 0 2006.257.17:01:45.08#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:45.08#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:01:45.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.17:01:45.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.17:01:45.08$vck44/vblo=4,679.99 2006.257.17:01:45.08#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.17:01:45.08#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.17:01:45.08#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:45.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:01:45.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:01:45.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:01:45.08#ibcon#enter wrdev, iclass 35, count 0 2006.257.17:01:45.08#ibcon#first serial, iclass 35, count 0 2006.257.17:01:45.08#ibcon#enter sib2, iclass 35, count 0 2006.257.17:01:45.08#ibcon#flushed, iclass 35, count 0 2006.257.17:01:45.08#ibcon#about to write, iclass 35, count 0 2006.257.17:01:45.08#ibcon#wrote, iclass 35, count 0 2006.257.17:01:45.08#ibcon#about to read 3, iclass 35, count 0 2006.257.17:01:45.10#ibcon#read 3, iclass 35, count 0 2006.257.17:01:45.10#ibcon#about to read 4, iclass 35, count 0 2006.257.17:01:45.10#ibcon#read 4, iclass 35, count 0 2006.257.17:01:45.10#ibcon#about to read 5, iclass 35, count 0 2006.257.17:01:45.10#ibcon#read 5, iclass 35, count 0 2006.257.17:01:45.10#ibcon#about to read 6, iclass 35, count 0 2006.257.17:01:45.10#ibcon#read 6, iclass 35, count 0 2006.257.17:01:45.10#ibcon#end of sib2, iclass 35, count 0 2006.257.17:01:45.10#ibcon#*mode == 0, iclass 35, count 0 2006.257.17:01:45.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.17:01:45.10#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:01:45.10#ibcon#*before write, iclass 35, count 0 2006.257.17:01:45.10#ibcon#enter sib2, iclass 35, count 0 2006.257.17:01:45.10#ibcon#flushed, iclass 35, count 0 2006.257.17:01:45.10#ibcon#about to write, iclass 35, count 0 2006.257.17:01:45.10#ibcon#wrote, iclass 35, count 0 2006.257.17:01:45.10#ibcon#about to read 3, iclass 35, count 0 2006.257.17:01:45.14#ibcon#read 3, iclass 35, count 0 2006.257.17:01:45.14#ibcon#about to read 4, iclass 35, count 0 2006.257.17:01:45.14#ibcon#read 4, iclass 35, count 0 2006.257.17:01:45.14#ibcon#about to read 5, iclass 35, count 0 2006.257.17:01:45.14#ibcon#read 5, iclass 35, count 0 2006.257.17:01:45.14#ibcon#about to read 6, iclass 35, count 0 2006.257.17:01:45.14#ibcon#read 6, iclass 35, count 0 2006.257.17:01:45.14#ibcon#end of sib2, iclass 35, count 0 2006.257.17:01:45.14#ibcon#*after write, iclass 35, count 0 2006.257.17:01:45.14#ibcon#*before return 0, iclass 35, count 0 2006.257.17:01:45.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:01:45.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:01:45.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.17:01:45.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.17:01:45.14$vck44/vb=4,5 2006.257.17:01:45.14#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.17:01:45.14#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.17:01:45.14#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:45.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:01:45.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:01:45.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:01:45.20#ibcon#enter wrdev, iclass 37, count 2 2006.257.17:01:45.20#ibcon#first serial, iclass 37, count 2 2006.257.17:01:45.20#ibcon#enter sib2, iclass 37, count 2 2006.257.17:01:45.20#ibcon#flushed, iclass 37, count 2 2006.257.17:01:45.20#ibcon#about to write, iclass 37, count 2 2006.257.17:01:45.20#ibcon#wrote, iclass 37, count 2 2006.257.17:01:45.20#ibcon#about to read 3, iclass 37, count 2 2006.257.17:01:45.22#ibcon#read 3, iclass 37, count 2 2006.257.17:01:45.22#ibcon#about to read 4, iclass 37, count 2 2006.257.17:01:45.22#ibcon#read 4, iclass 37, count 2 2006.257.17:01:45.22#ibcon#about to read 5, iclass 37, count 2 2006.257.17:01:45.22#ibcon#read 5, iclass 37, count 2 2006.257.17:01:45.22#ibcon#about to read 6, iclass 37, count 2 2006.257.17:01:45.22#ibcon#read 6, iclass 37, count 2 2006.257.17:01:45.22#ibcon#end of sib2, iclass 37, count 2 2006.257.17:01:45.22#ibcon#*mode == 0, iclass 37, count 2 2006.257.17:01:45.22#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.17:01:45.22#ibcon#[27=AT04-05\r\n] 2006.257.17:01:45.22#ibcon#*before write, iclass 37, count 2 2006.257.17:01:45.22#ibcon#enter sib2, iclass 37, count 2 2006.257.17:01:45.22#ibcon#flushed, iclass 37, count 2 2006.257.17:01:45.22#ibcon#about to write, iclass 37, count 2 2006.257.17:01:45.22#ibcon#wrote, iclass 37, count 2 2006.257.17:01:45.22#ibcon#about to read 3, iclass 37, count 2 2006.257.17:01:45.25#ibcon#read 3, iclass 37, count 2 2006.257.17:01:45.25#ibcon#about to read 4, iclass 37, count 2 2006.257.17:01:45.25#ibcon#read 4, iclass 37, count 2 2006.257.17:01:45.25#ibcon#about to read 5, iclass 37, count 2 2006.257.17:01:45.25#ibcon#read 5, iclass 37, count 2 2006.257.17:01:45.25#ibcon#about to read 6, iclass 37, count 2 2006.257.17:01:45.25#ibcon#read 6, iclass 37, count 2 2006.257.17:01:45.25#ibcon#end of sib2, iclass 37, count 2 2006.257.17:01:45.25#ibcon#*after write, iclass 37, count 2 2006.257.17:01:45.25#ibcon#*before return 0, iclass 37, count 2 2006.257.17:01:45.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:01:45.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:01:45.25#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.17:01:45.25#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:45.25#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:01:45.37#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:01:45.37#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:01:45.37#ibcon#enter wrdev, iclass 37, count 0 2006.257.17:01:45.37#ibcon#first serial, iclass 37, count 0 2006.257.17:01:45.37#ibcon#enter sib2, iclass 37, count 0 2006.257.17:01:45.37#ibcon#flushed, iclass 37, count 0 2006.257.17:01:45.37#ibcon#about to write, iclass 37, count 0 2006.257.17:01:45.37#ibcon#wrote, iclass 37, count 0 2006.257.17:01:45.37#ibcon#about to read 3, iclass 37, count 0 2006.257.17:01:45.39#ibcon#read 3, iclass 37, count 0 2006.257.17:01:45.39#ibcon#about to read 4, iclass 37, count 0 2006.257.17:01:45.39#ibcon#read 4, iclass 37, count 0 2006.257.17:01:45.39#ibcon#about to read 5, iclass 37, count 0 2006.257.17:01:45.39#ibcon#read 5, iclass 37, count 0 2006.257.17:01:45.39#ibcon#about to read 6, iclass 37, count 0 2006.257.17:01:45.39#ibcon#read 6, iclass 37, count 0 2006.257.17:01:45.39#ibcon#end of sib2, iclass 37, count 0 2006.257.17:01:45.39#ibcon#*mode == 0, iclass 37, count 0 2006.257.17:01:45.39#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.17:01:45.39#ibcon#[27=USB\r\n] 2006.257.17:01:45.39#ibcon#*before write, iclass 37, count 0 2006.257.17:01:45.39#ibcon#enter sib2, iclass 37, count 0 2006.257.17:01:45.39#ibcon#flushed, iclass 37, count 0 2006.257.17:01:45.39#ibcon#about to write, iclass 37, count 0 2006.257.17:01:45.39#ibcon#wrote, iclass 37, count 0 2006.257.17:01:45.39#ibcon#about to read 3, iclass 37, count 0 2006.257.17:01:45.42#ibcon#read 3, iclass 37, count 0 2006.257.17:01:45.42#ibcon#about to read 4, iclass 37, count 0 2006.257.17:01:45.42#ibcon#read 4, iclass 37, count 0 2006.257.17:01:45.42#ibcon#about to read 5, iclass 37, count 0 2006.257.17:01:45.42#ibcon#read 5, iclass 37, count 0 2006.257.17:01:45.42#ibcon#about to read 6, iclass 37, count 0 2006.257.17:01:45.42#ibcon#read 6, iclass 37, count 0 2006.257.17:01:45.42#ibcon#end of sib2, iclass 37, count 0 2006.257.17:01:45.42#ibcon#*after write, iclass 37, count 0 2006.257.17:01:45.42#ibcon#*before return 0, iclass 37, count 0 2006.257.17:01:45.42#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:01:45.42#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:01:45.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.17:01:45.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.17:01:45.42$vck44/vblo=5,709.99 2006.257.17:01:45.42#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.17:01:45.42#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.17:01:45.42#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:45.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:01:45.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:01:45.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:01:45.42#ibcon#enter wrdev, iclass 39, count 0 2006.257.17:01:45.42#ibcon#first serial, iclass 39, count 0 2006.257.17:01:45.42#ibcon#enter sib2, iclass 39, count 0 2006.257.17:01:45.42#ibcon#flushed, iclass 39, count 0 2006.257.17:01:45.42#ibcon#about to write, iclass 39, count 0 2006.257.17:01:45.42#ibcon#wrote, iclass 39, count 0 2006.257.17:01:45.42#ibcon#about to read 3, iclass 39, count 0 2006.257.17:01:45.44#ibcon#read 3, iclass 39, count 0 2006.257.17:01:45.44#ibcon#about to read 4, iclass 39, count 0 2006.257.17:01:45.44#ibcon#read 4, iclass 39, count 0 2006.257.17:01:45.44#ibcon#about to read 5, iclass 39, count 0 2006.257.17:01:45.44#ibcon#read 5, iclass 39, count 0 2006.257.17:01:45.44#ibcon#about to read 6, iclass 39, count 0 2006.257.17:01:45.44#ibcon#read 6, iclass 39, count 0 2006.257.17:01:45.44#ibcon#end of sib2, iclass 39, count 0 2006.257.17:01:45.44#ibcon#*mode == 0, iclass 39, count 0 2006.257.17:01:45.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.17:01:45.44#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:01:45.44#ibcon#*before write, iclass 39, count 0 2006.257.17:01:45.44#ibcon#enter sib2, iclass 39, count 0 2006.257.17:01:45.44#ibcon#flushed, iclass 39, count 0 2006.257.17:01:45.44#ibcon#about to write, iclass 39, count 0 2006.257.17:01:45.44#ibcon#wrote, iclass 39, count 0 2006.257.17:01:45.44#ibcon#about to read 3, iclass 39, count 0 2006.257.17:01:45.48#ibcon#read 3, iclass 39, count 0 2006.257.17:01:45.48#ibcon#about to read 4, iclass 39, count 0 2006.257.17:01:45.48#ibcon#read 4, iclass 39, count 0 2006.257.17:01:45.48#ibcon#about to read 5, iclass 39, count 0 2006.257.17:01:45.48#ibcon#read 5, iclass 39, count 0 2006.257.17:01:45.48#ibcon#about to read 6, iclass 39, count 0 2006.257.17:01:45.48#ibcon#read 6, iclass 39, count 0 2006.257.17:01:45.48#ibcon#end of sib2, iclass 39, count 0 2006.257.17:01:45.48#ibcon#*after write, iclass 39, count 0 2006.257.17:01:45.48#ibcon#*before return 0, iclass 39, count 0 2006.257.17:01:45.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:01:45.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:01:45.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.17:01:45.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.17:01:45.48$vck44/vb=5,4 2006.257.17:01:45.48#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.17:01:45.48#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.17:01:45.48#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:45.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:45.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:45.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:45.54#ibcon#enter wrdev, iclass 3, count 2 2006.257.17:01:45.54#ibcon#first serial, iclass 3, count 2 2006.257.17:01:45.54#ibcon#enter sib2, iclass 3, count 2 2006.257.17:01:45.54#ibcon#flushed, iclass 3, count 2 2006.257.17:01:45.54#ibcon#about to write, iclass 3, count 2 2006.257.17:01:45.54#ibcon#wrote, iclass 3, count 2 2006.257.17:01:45.54#ibcon#about to read 3, iclass 3, count 2 2006.257.17:01:45.56#ibcon#read 3, iclass 3, count 2 2006.257.17:01:45.56#ibcon#about to read 4, iclass 3, count 2 2006.257.17:01:45.56#ibcon#read 4, iclass 3, count 2 2006.257.17:01:45.56#ibcon#about to read 5, iclass 3, count 2 2006.257.17:01:45.56#ibcon#read 5, iclass 3, count 2 2006.257.17:01:45.56#ibcon#about to read 6, iclass 3, count 2 2006.257.17:01:45.56#ibcon#read 6, iclass 3, count 2 2006.257.17:01:45.56#ibcon#end of sib2, iclass 3, count 2 2006.257.17:01:45.56#ibcon#*mode == 0, iclass 3, count 2 2006.257.17:01:45.56#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.17:01:45.56#ibcon#[27=AT05-04\r\n] 2006.257.17:01:45.56#ibcon#*before write, iclass 3, count 2 2006.257.17:01:45.56#ibcon#enter sib2, iclass 3, count 2 2006.257.17:01:45.56#ibcon#flushed, iclass 3, count 2 2006.257.17:01:45.56#ibcon#about to write, iclass 3, count 2 2006.257.17:01:45.56#ibcon#wrote, iclass 3, count 2 2006.257.17:01:45.56#ibcon#about to read 3, iclass 3, count 2 2006.257.17:01:45.59#ibcon#read 3, iclass 3, count 2 2006.257.17:01:45.59#ibcon#about to read 4, iclass 3, count 2 2006.257.17:01:45.59#ibcon#read 4, iclass 3, count 2 2006.257.17:01:45.59#ibcon#about to read 5, iclass 3, count 2 2006.257.17:01:45.59#ibcon#read 5, iclass 3, count 2 2006.257.17:01:45.59#ibcon#about to read 6, iclass 3, count 2 2006.257.17:01:45.59#ibcon#read 6, iclass 3, count 2 2006.257.17:01:45.59#ibcon#end of sib2, iclass 3, count 2 2006.257.17:01:45.59#ibcon#*after write, iclass 3, count 2 2006.257.17:01:45.59#ibcon#*before return 0, iclass 3, count 2 2006.257.17:01:45.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:45.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:01:45.59#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.17:01:45.59#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:45.59#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:45.71#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:45.71#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:45.71#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:01:45.71#ibcon#first serial, iclass 3, count 0 2006.257.17:01:45.71#ibcon#enter sib2, iclass 3, count 0 2006.257.17:01:45.71#ibcon#flushed, iclass 3, count 0 2006.257.17:01:45.71#ibcon#about to write, iclass 3, count 0 2006.257.17:01:45.71#ibcon#wrote, iclass 3, count 0 2006.257.17:01:45.71#ibcon#about to read 3, iclass 3, count 0 2006.257.17:01:45.73#ibcon#read 3, iclass 3, count 0 2006.257.17:01:45.73#ibcon#about to read 4, iclass 3, count 0 2006.257.17:01:45.73#ibcon#read 4, iclass 3, count 0 2006.257.17:01:45.73#ibcon#about to read 5, iclass 3, count 0 2006.257.17:01:45.73#ibcon#read 5, iclass 3, count 0 2006.257.17:01:45.73#ibcon#about to read 6, iclass 3, count 0 2006.257.17:01:45.73#ibcon#read 6, iclass 3, count 0 2006.257.17:01:45.73#ibcon#end of sib2, iclass 3, count 0 2006.257.17:01:45.73#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:01:45.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:01:45.73#ibcon#[27=USB\r\n] 2006.257.17:01:45.73#ibcon#*before write, iclass 3, count 0 2006.257.17:01:45.73#ibcon#enter sib2, iclass 3, count 0 2006.257.17:01:45.73#ibcon#flushed, iclass 3, count 0 2006.257.17:01:45.73#ibcon#about to write, iclass 3, count 0 2006.257.17:01:45.73#ibcon#wrote, iclass 3, count 0 2006.257.17:01:45.73#ibcon#about to read 3, iclass 3, count 0 2006.257.17:01:45.76#ibcon#read 3, iclass 3, count 0 2006.257.17:01:45.76#ibcon#about to read 4, iclass 3, count 0 2006.257.17:01:45.76#ibcon#read 4, iclass 3, count 0 2006.257.17:01:45.76#ibcon#about to read 5, iclass 3, count 0 2006.257.17:01:45.76#ibcon#read 5, iclass 3, count 0 2006.257.17:01:45.76#ibcon#about to read 6, iclass 3, count 0 2006.257.17:01:45.76#ibcon#read 6, iclass 3, count 0 2006.257.17:01:45.76#ibcon#end of sib2, iclass 3, count 0 2006.257.17:01:45.76#ibcon#*after write, iclass 3, count 0 2006.257.17:01:45.76#ibcon#*before return 0, iclass 3, count 0 2006.257.17:01:45.76#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:45.76#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:01:45.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:01:45.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:01:45.76$vck44/vblo=6,719.99 2006.257.17:01:45.76#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.17:01:45.76#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.17:01:45.76#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:45.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:45.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:45.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:45.76#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:01:45.76#ibcon#first serial, iclass 5, count 0 2006.257.17:01:45.76#ibcon#enter sib2, iclass 5, count 0 2006.257.17:01:45.76#ibcon#flushed, iclass 5, count 0 2006.257.17:01:45.76#ibcon#about to write, iclass 5, count 0 2006.257.17:01:45.76#ibcon#wrote, iclass 5, count 0 2006.257.17:01:45.76#ibcon#about to read 3, iclass 5, count 0 2006.257.17:01:45.78#ibcon#read 3, iclass 5, count 0 2006.257.17:01:45.78#ibcon#about to read 4, iclass 5, count 0 2006.257.17:01:45.78#ibcon#read 4, iclass 5, count 0 2006.257.17:01:45.78#ibcon#about to read 5, iclass 5, count 0 2006.257.17:01:45.78#ibcon#read 5, iclass 5, count 0 2006.257.17:01:45.78#ibcon#about to read 6, iclass 5, count 0 2006.257.17:01:45.78#ibcon#read 6, iclass 5, count 0 2006.257.17:01:45.78#ibcon#end of sib2, iclass 5, count 0 2006.257.17:01:45.78#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:01:45.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:01:45.78#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:01:45.78#ibcon#*before write, iclass 5, count 0 2006.257.17:01:45.78#ibcon#enter sib2, iclass 5, count 0 2006.257.17:01:45.78#ibcon#flushed, iclass 5, count 0 2006.257.17:01:45.78#ibcon#about to write, iclass 5, count 0 2006.257.17:01:45.78#ibcon#wrote, iclass 5, count 0 2006.257.17:01:45.78#ibcon#about to read 3, iclass 5, count 0 2006.257.17:01:45.82#ibcon#read 3, iclass 5, count 0 2006.257.17:01:45.82#ibcon#about to read 4, iclass 5, count 0 2006.257.17:01:45.82#ibcon#read 4, iclass 5, count 0 2006.257.17:01:45.82#ibcon#about to read 5, iclass 5, count 0 2006.257.17:01:45.82#ibcon#read 5, iclass 5, count 0 2006.257.17:01:45.82#ibcon#about to read 6, iclass 5, count 0 2006.257.17:01:45.82#ibcon#read 6, iclass 5, count 0 2006.257.17:01:45.82#ibcon#end of sib2, iclass 5, count 0 2006.257.17:01:45.82#ibcon#*after write, iclass 5, count 0 2006.257.17:01:45.82#ibcon#*before return 0, iclass 5, count 0 2006.257.17:01:45.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:45.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:01:45.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:01:45.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:01:45.82$vck44/vb=6,4 2006.257.17:01:45.82#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.17:01:45.82#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.17:01:45.82#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:45.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:45.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:45.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:45.88#ibcon#enter wrdev, iclass 7, count 2 2006.257.17:01:45.88#ibcon#first serial, iclass 7, count 2 2006.257.17:01:45.88#ibcon#enter sib2, iclass 7, count 2 2006.257.17:01:45.88#ibcon#flushed, iclass 7, count 2 2006.257.17:01:45.88#ibcon#about to write, iclass 7, count 2 2006.257.17:01:45.88#ibcon#wrote, iclass 7, count 2 2006.257.17:01:45.88#ibcon#about to read 3, iclass 7, count 2 2006.257.17:01:45.90#ibcon#read 3, iclass 7, count 2 2006.257.17:01:45.90#ibcon#about to read 4, iclass 7, count 2 2006.257.17:01:45.90#ibcon#read 4, iclass 7, count 2 2006.257.17:01:45.90#ibcon#about to read 5, iclass 7, count 2 2006.257.17:01:45.90#ibcon#read 5, iclass 7, count 2 2006.257.17:01:45.90#ibcon#about to read 6, iclass 7, count 2 2006.257.17:01:45.90#ibcon#read 6, iclass 7, count 2 2006.257.17:01:45.90#ibcon#end of sib2, iclass 7, count 2 2006.257.17:01:45.90#ibcon#*mode == 0, iclass 7, count 2 2006.257.17:01:45.90#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.17:01:45.90#ibcon#[27=AT06-04\r\n] 2006.257.17:01:45.90#ibcon#*before write, iclass 7, count 2 2006.257.17:01:45.90#ibcon#enter sib2, iclass 7, count 2 2006.257.17:01:45.90#ibcon#flushed, iclass 7, count 2 2006.257.17:01:45.90#ibcon#about to write, iclass 7, count 2 2006.257.17:01:45.90#ibcon#wrote, iclass 7, count 2 2006.257.17:01:45.90#ibcon#about to read 3, iclass 7, count 2 2006.257.17:01:45.93#ibcon#read 3, iclass 7, count 2 2006.257.17:01:45.93#ibcon#about to read 4, iclass 7, count 2 2006.257.17:01:45.93#ibcon#read 4, iclass 7, count 2 2006.257.17:01:45.93#ibcon#about to read 5, iclass 7, count 2 2006.257.17:01:45.93#ibcon#read 5, iclass 7, count 2 2006.257.17:01:45.93#ibcon#about to read 6, iclass 7, count 2 2006.257.17:01:45.93#ibcon#read 6, iclass 7, count 2 2006.257.17:01:45.93#ibcon#end of sib2, iclass 7, count 2 2006.257.17:01:45.93#ibcon#*after write, iclass 7, count 2 2006.257.17:01:45.93#ibcon#*before return 0, iclass 7, count 2 2006.257.17:01:45.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:45.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:01:45.93#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.17:01:45.93#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:45.93#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:46.05#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:46.05#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:46.05#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:01:46.05#ibcon#first serial, iclass 7, count 0 2006.257.17:01:46.05#ibcon#enter sib2, iclass 7, count 0 2006.257.17:01:46.05#ibcon#flushed, iclass 7, count 0 2006.257.17:01:46.05#ibcon#about to write, iclass 7, count 0 2006.257.17:01:46.05#ibcon#wrote, iclass 7, count 0 2006.257.17:01:46.05#ibcon#about to read 3, iclass 7, count 0 2006.257.17:01:46.07#ibcon#read 3, iclass 7, count 0 2006.257.17:01:46.07#ibcon#about to read 4, iclass 7, count 0 2006.257.17:01:46.07#ibcon#read 4, iclass 7, count 0 2006.257.17:01:46.07#ibcon#about to read 5, iclass 7, count 0 2006.257.17:01:46.07#ibcon#read 5, iclass 7, count 0 2006.257.17:01:46.07#ibcon#about to read 6, iclass 7, count 0 2006.257.17:01:46.07#ibcon#read 6, iclass 7, count 0 2006.257.17:01:46.07#ibcon#end of sib2, iclass 7, count 0 2006.257.17:01:46.07#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:01:46.07#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:01:46.07#ibcon#[27=USB\r\n] 2006.257.17:01:46.07#ibcon#*before write, iclass 7, count 0 2006.257.17:01:46.07#ibcon#enter sib2, iclass 7, count 0 2006.257.17:01:46.07#ibcon#flushed, iclass 7, count 0 2006.257.17:01:46.07#ibcon#about to write, iclass 7, count 0 2006.257.17:01:46.07#ibcon#wrote, iclass 7, count 0 2006.257.17:01:46.07#ibcon#about to read 3, iclass 7, count 0 2006.257.17:01:46.10#ibcon#read 3, iclass 7, count 0 2006.257.17:01:46.10#ibcon#about to read 4, iclass 7, count 0 2006.257.17:01:46.10#ibcon#read 4, iclass 7, count 0 2006.257.17:01:46.10#ibcon#about to read 5, iclass 7, count 0 2006.257.17:01:46.10#ibcon#read 5, iclass 7, count 0 2006.257.17:01:46.10#ibcon#about to read 6, iclass 7, count 0 2006.257.17:01:46.10#ibcon#read 6, iclass 7, count 0 2006.257.17:01:46.10#ibcon#end of sib2, iclass 7, count 0 2006.257.17:01:46.10#ibcon#*after write, iclass 7, count 0 2006.257.17:01:46.10#ibcon#*before return 0, iclass 7, count 0 2006.257.17:01:46.10#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:46.10#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:01:46.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:01:46.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:01:46.10$vck44/vblo=7,734.99 2006.257.17:01:46.10#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.17:01:46.10#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.17:01:46.10#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:46.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:46.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:46.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:46.10#ibcon#enter wrdev, iclass 11, count 0 2006.257.17:01:46.10#ibcon#first serial, iclass 11, count 0 2006.257.17:01:46.10#ibcon#enter sib2, iclass 11, count 0 2006.257.17:01:46.10#ibcon#flushed, iclass 11, count 0 2006.257.17:01:46.10#ibcon#about to write, iclass 11, count 0 2006.257.17:01:46.10#ibcon#wrote, iclass 11, count 0 2006.257.17:01:46.10#ibcon#about to read 3, iclass 11, count 0 2006.257.17:01:46.12#ibcon#read 3, iclass 11, count 0 2006.257.17:01:46.12#ibcon#about to read 4, iclass 11, count 0 2006.257.17:01:46.12#ibcon#read 4, iclass 11, count 0 2006.257.17:01:46.12#ibcon#about to read 5, iclass 11, count 0 2006.257.17:01:46.12#ibcon#read 5, iclass 11, count 0 2006.257.17:01:46.12#ibcon#about to read 6, iclass 11, count 0 2006.257.17:01:46.12#ibcon#read 6, iclass 11, count 0 2006.257.17:01:46.12#ibcon#end of sib2, iclass 11, count 0 2006.257.17:01:46.12#ibcon#*mode == 0, iclass 11, count 0 2006.257.17:01:46.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.17:01:46.12#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:01:46.12#ibcon#*before write, iclass 11, count 0 2006.257.17:01:46.12#ibcon#enter sib2, iclass 11, count 0 2006.257.17:01:46.12#ibcon#flushed, iclass 11, count 0 2006.257.17:01:46.12#ibcon#about to write, iclass 11, count 0 2006.257.17:01:46.12#ibcon#wrote, iclass 11, count 0 2006.257.17:01:46.12#ibcon#about to read 3, iclass 11, count 0 2006.257.17:01:46.16#ibcon#read 3, iclass 11, count 0 2006.257.17:01:46.16#ibcon#about to read 4, iclass 11, count 0 2006.257.17:01:46.16#ibcon#read 4, iclass 11, count 0 2006.257.17:01:46.16#ibcon#about to read 5, iclass 11, count 0 2006.257.17:01:46.16#ibcon#read 5, iclass 11, count 0 2006.257.17:01:46.16#ibcon#about to read 6, iclass 11, count 0 2006.257.17:01:46.16#ibcon#read 6, iclass 11, count 0 2006.257.17:01:46.16#ibcon#end of sib2, iclass 11, count 0 2006.257.17:01:46.16#ibcon#*after write, iclass 11, count 0 2006.257.17:01:46.16#ibcon#*before return 0, iclass 11, count 0 2006.257.17:01:46.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:46.16#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:01:46.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.17:01:46.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.17:01:46.16$vck44/vb=7,4 2006.257.17:01:46.16#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.17:01:46.16#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.17:01:46.16#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:46.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:46.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:46.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:46.22#ibcon#enter wrdev, iclass 13, count 2 2006.257.17:01:46.22#ibcon#first serial, iclass 13, count 2 2006.257.17:01:46.22#ibcon#enter sib2, iclass 13, count 2 2006.257.17:01:46.22#ibcon#flushed, iclass 13, count 2 2006.257.17:01:46.22#ibcon#about to write, iclass 13, count 2 2006.257.17:01:46.22#ibcon#wrote, iclass 13, count 2 2006.257.17:01:46.22#ibcon#about to read 3, iclass 13, count 2 2006.257.17:01:46.24#ibcon#read 3, iclass 13, count 2 2006.257.17:01:46.24#ibcon#about to read 4, iclass 13, count 2 2006.257.17:01:46.24#ibcon#read 4, iclass 13, count 2 2006.257.17:01:46.24#ibcon#about to read 5, iclass 13, count 2 2006.257.17:01:46.24#ibcon#read 5, iclass 13, count 2 2006.257.17:01:46.24#ibcon#about to read 6, iclass 13, count 2 2006.257.17:01:46.24#ibcon#read 6, iclass 13, count 2 2006.257.17:01:46.24#ibcon#end of sib2, iclass 13, count 2 2006.257.17:01:46.24#ibcon#*mode == 0, iclass 13, count 2 2006.257.17:01:46.24#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.17:01:46.24#ibcon#[27=AT07-04\r\n] 2006.257.17:01:46.24#ibcon#*before write, iclass 13, count 2 2006.257.17:01:46.24#ibcon#enter sib2, iclass 13, count 2 2006.257.17:01:46.24#ibcon#flushed, iclass 13, count 2 2006.257.17:01:46.24#ibcon#about to write, iclass 13, count 2 2006.257.17:01:46.24#ibcon#wrote, iclass 13, count 2 2006.257.17:01:46.24#ibcon#about to read 3, iclass 13, count 2 2006.257.17:01:46.27#ibcon#read 3, iclass 13, count 2 2006.257.17:01:46.27#ibcon#about to read 4, iclass 13, count 2 2006.257.17:01:46.27#ibcon#read 4, iclass 13, count 2 2006.257.17:01:46.27#ibcon#about to read 5, iclass 13, count 2 2006.257.17:01:46.27#ibcon#read 5, iclass 13, count 2 2006.257.17:01:46.27#ibcon#about to read 6, iclass 13, count 2 2006.257.17:01:46.27#ibcon#read 6, iclass 13, count 2 2006.257.17:01:46.27#ibcon#end of sib2, iclass 13, count 2 2006.257.17:01:46.27#ibcon#*after write, iclass 13, count 2 2006.257.17:01:46.27#ibcon#*before return 0, iclass 13, count 2 2006.257.17:01:46.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:46.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:01:46.27#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.17:01:46.27#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:46.27#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:46.39#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:46.39#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:46.39#ibcon#enter wrdev, iclass 13, count 0 2006.257.17:01:46.39#ibcon#first serial, iclass 13, count 0 2006.257.17:01:46.39#ibcon#enter sib2, iclass 13, count 0 2006.257.17:01:46.39#ibcon#flushed, iclass 13, count 0 2006.257.17:01:46.39#ibcon#about to write, iclass 13, count 0 2006.257.17:01:46.39#ibcon#wrote, iclass 13, count 0 2006.257.17:01:46.39#ibcon#about to read 3, iclass 13, count 0 2006.257.17:01:46.41#ibcon#read 3, iclass 13, count 0 2006.257.17:01:46.41#ibcon#about to read 4, iclass 13, count 0 2006.257.17:01:46.41#ibcon#read 4, iclass 13, count 0 2006.257.17:01:46.41#ibcon#about to read 5, iclass 13, count 0 2006.257.17:01:46.41#ibcon#read 5, iclass 13, count 0 2006.257.17:01:46.41#ibcon#about to read 6, iclass 13, count 0 2006.257.17:01:46.41#ibcon#read 6, iclass 13, count 0 2006.257.17:01:46.41#ibcon#end of sib2, iclass 13, count 0 2006.257.17:01:46.41#ibcon#*mode == 0, iclass 13, count 0 2006.257.17:01:46.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.17:01:46.41#ibcon#[27=USB\r\n] 2006.257.17:01:46.41#ibcon#*before write, iclass 13, count 0 2006.257.17:01:46.41#ibcon#enter sib2, iclass 13, count 0 2006.257.17:01:46.41#ibcon#flushed, iclass 13, count 0 2006.257.17:01:46.41#ibcon#about to write, iclass 13, count 0 2006.257.17:01:46.41#ibcon#wrote, iclass 13, count 0 2006.257.17:01:46.41#ibcon#about to read 3, iclass 13, count 0 2006.257.17:01:46.44#ibcon#read 3, iclass 13, count 0 2006.257.17:01:46.44#ibcon#about to read 4, iclass 13, count 0 2006.257.17:01:46.44#ibcon#read 4, iclass 13, count 0 2006.257.17:01:46.44#ibcon#about to read 5, iclass 13, count 0 2006.257.17:01:46.44#ibcon#read 5, iclass 13, count 0 2006.257.17:01:46.44#ibcon#about to read 6, iclass 13, count 0 2006.257.17:01:46.44#ibcon#read 6, iclass 13, count 0 2006.257.17:01:46.44#ibcon#end of sib2, iclass 13, count 0 2006.257.17:01:46.44#ibcon#*after write, iclass 13, count 0 2006.257.17:01:46.44#ibcon#*before return 0, iclass 13, count 0 2006.257.17:01:46.44#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:46.44#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:01:46.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.17:01:46.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.17:01:46.44$vck44/vblo=8,744.99 2006.257.17:01:46.44#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.17:01:46.44#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.17:01:46.44#ibcon#ireg 17 cls_cnt 0 2006.257.17:01:46.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:46.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:46.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:46.44#ibcon#enter wrdev, iclass 15, count 0 2006.257.17:01:46.44#ibcon#first serial, iclass 15, count 0 2006.257.17:01:46.44#ibcon#enter sib2, iclass 15, count 0 2006.257.17:01:46.44#ibcon#flushed, iclass 15, count 0 2006.257.17:01:46.44#ibcon#about to write, iclass 15, count 0 2006.257.17:01:46.44#ibcon#wrote, iclass 15, count 0 2006.257.17:01:46.44#ibcon#about to read 3, iclass 15, count 0 2006.257.17:01:46.46#ibcon#read 3, iclass 15, count 0 2006.257.17:01:46.46#ibcon#about to read 4, iclass 15, count 0 2006.257.17:01:46.46#ibcon#read 4, iclass 15, count 0 2006.257.17:01:46.46#ibcon#about to read 5, iclass 15, count 0 2006.257.17:01:46.46#ibcon#read 5, iclass 15, count 0 2006.257.17:01:46.46#ibcon#about to read 6, iclass 15, count 0 2006.257.17:01:46.46#ibcon#read 6, iclass 15, count 0 2006.257.17:01:46.46#ibcon#end of sib2, iclass 15, count 0 2006.257.17:01:46.46#ibcon#*mode == 0, iclass 15, count 0 2006.257.17:01:46.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.17:01:46.46#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:01:46.46#ibcon#*before write, iclass 15, count 0 2006.257.17:01:46.46#ibcon#enter sib2, iclass 15, count 0 2006.257.17:01:46.46#ibcon#flushed, iclass 15, count 0 2006.257.17:01:46.46#ibcon#about to write, iclass 15, count 0 2006.257.17:01:46.46#ibcon#wrote, iclass 15, count 0 2006.257.17:01:46.46#ibcon#about to read 3, iclass 15, count 0 2006.257.17:01:46.50#ibcon#read 3, iclass 15, count 0 2006.257.17:01:46.50#ibcon#about to read 4, iclass 15, count 0 2006.257.17:01:46.50#ibcon#read 4, iclass 15, count 0 2006.257.17:01:46.50#ibcon#about to read 5, iclass 15, count 0 2006.257.17:01:46.50#ibcon#read 5, iclass 15, count 0 2006.257.17:01:46.50#ibcon#about to read 6, iclass 15, count 0 2006.257.17:01:46.50#ibcon#read 6, iclass 15, count 0 2006.257.17:01:46.50#ibcon#end of sib2, iclass 15, count 0 2006.257.17:01:46.50#ibcon#*after write, iclass 15, count 0 2006.257.17:01:46.50#ibcon#*before return 0, iclass 15, count 0 2006.257.17:01:46.50#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:46.50#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:01:46.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.17:01:46.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.17:01:46.50$vck44/vb=8,4 2006.257.17:01:46.50#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.17:01:46.50#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.17:01:46.50#ibcon#ireg 11 cls_cnt 2 2006.257.17:01:46.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:46.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:46.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:46.56#ibcon#enter wrdev, iclass 17, count 2 2006.257.17:01:46.56#ibcon#first serial, iclass 17, count 2 2006.257.17:01:46.56#ibcon#enter sib2, iclass 17, count 2 2006.257.17:01:46.56#ibcon#flushed, iclass 17, count 2 2006.257.17:01:46.56#ibcon#about to write, iclass 17, count 2 2006.257.17:01:46.56#ibcon#wrote, iclass 17, count 2 2006.257.17:01:46.56#ibcon#about to read 3, iclass 17, count 2 2006.257.17:01:46.58#ibcon#read 3, iclass 17, count 2 2006.257.17:01:46.58#ibcon#about to read 4, iclass 17, count 2 2006.257.17:01:46.58#ibcon#read 4, iclass 17, count 2 2006.257.17:01:46.58#ibcon#about to read 5, iclass 17, count 2 2006.257.17:01:46.58#ibcon#read 5, iclass 17, count 2 2006.257.17:01:46.58#ibcon#about to read 6, iclass 17, count 2 2006.257.17:01:46.58#ibcon#read 6, iclass 17, count 2 2006.257.17:01:46.58#ibcon#end of sib2, iclass 17, count 2 2006.257.17:01:46.58#ibcon#*mode == 0, iclass 17, count 2 2006.257.17:01:46.58#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.17:01:46.58#ibcon#[27=AT08-04\r\n] 2006.257.17:01:46.58#ibcon#*before write, iclass 17, count 2 2006.257.17:01:46.58#ibcon#enter sib2, iclass 17, count 2 2006.257.17:01:46.58#ibcon#flushed, iclass 17, count 2 2006.257.17:01:46.58#ibcon#about to write, iclass 17, count 2 2006.257.17:01:46.58#ibcon#wrote, iclass 17, count 2 2006.257.17:01:46.58#ibcon#about to read 3, iclass 17, count 2 2006.257.17:01:46.61#ibcon#read 3, iclass 17, count 2 2006.257.17:01:46.61#ibcon#about to read 4, iclass 17, count 2 2006.257.17:01:46.61#ibcon#read 4, iclass 17, count 2 2006.257.17:01:46.61#ibcon#about to read 5, iclass 17, count 2 2006.257.17:01:46.61#ibcon#read 5, iclass 17, count 2 2006.257.17:01:46.61#ibcon#about to read 6, iclass 17, count 2 2006.257.17:01:46.61#ibcon#read 6, iclass 17, count 2 2006.257.17:01:46.61#ibcon#end of sib2, iclass 17, count 2 2006.257.17:01:46.61#ibcon#*after write, iclass 17, count 2 2006.257.17:01:46.61#ibcon#*before return 0, iclass 17, count 2 2006.257.17:01:46.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:46.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:01:46.61#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.17:01:46.61#ibcon#ireg 7 cls_cnt 0 2006.257.17:01:46.61#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:46.73#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:46.73#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:46.73#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:01:46.73#ibcon#first serial, iclass 17, count 0 2006.257.17:01:46.73#ibcon#enter sib2, iclass 17, count 0 2006.257.17:01:46.73#ibcon#flushed, iclass 17, count 0 2006.257.17:01:46.73#ibcon#about to write, iclass 17, count 0 2006.257.17:01:46.73#ibcon#wrote, iclass 17, count 0 2006.257.17:01:46.73#ibcon#about to read 3, iclass 17, count 0 2006.257.17:01:46.75#ibcon#read 3, iclass 17, count 0 2006.257.17:01:46.75#ibcon#about to read 4, iclass 17, count 0 2006.257.17:01:46.75#ibcon#read 4, iclass 17, count 0 2006.257.17:01:46.75#ibcon#about to read 5, iclass 17, count 0 2006.257.17:01:46.75#ibcon#read 5, iclass 17, count 0 2006.257.17:01:46.75#ibcon#about to read 6, iclass 17, count 0 2006.257.17:01:46.75#ibcon#read 6, iclass 17, count 0 2006.257.17:01:46.75#ibcon#end of sib2, iclass 17, count 0 2006.257.17:01:46.75#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:01:46.75#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:01:46.75#ibcon#[27=USB\r\n] 2006.257.17:01:46.75#ibcon#*before write, iclass 17, count 0 2006.257.17:01:46.75#ibcon#enter sib2, iclass 17, count 0 2006.257.17:01:46.75#ibcon#flushed, iclass 17, count 0 2006.257.17:01:46.75#ibcon#about to write, iclass 17, count 0 2006.257.17:01:46.75#ibcon#wrote, iclass 17, count 0 2006.257.17:01:46.75#ibcon#about to read 3, iclass 17, count 0 2006.257.17:01:46.78#ibcon#read 3, iclass 17, count 0 2006.257.17:01:46.78#ibcon#about to read 4, iclass 17, count 0 2006.257.17:01:46.78#ibcon#read 4, iclass 17, count 0 2006.257.17:01:46.78#ibcon#about to read 5, iclass 17, count 0 2006.257.17:01:46.78#ibcon#read 5, iclass 17, count 0 2006.257.17:01:46.78#ibcon#about to read 6, iclass 17, count 0 2006.257.17:01:46.78#ibcon#read 6, iclass 17, count 0 2006.257.17:01:46.78#ibcon#end of sib2, iclass 17, count 0 2006.257.17:01:46.78#ibcon#*after write, iclass 17, count 0 2006.257.17:01:46.78#ibcon#*before return 0, iclass 17, count 0 2006.257.17:01:46.78#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:46.78#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:01:46.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:01:46.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:01:46.78$vck44/vabw=wide 2006.257.17:01:46.78#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.17:01:46.78#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.17:01:46.78#ibcon#ireg 8 cls_cnt 0 2006.257.17:01:46.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:46.78#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:46.78#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:46.78#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:01:46.78#ibcon#first serial, iclass 19, count 0 2006.257.17:01:46.78#ibcon#enter sib2, iclass 19, count 0 2006.257.17:01:46.78#ibcon#flushed, iclass 19, count 0 2006.257.17:01:46.78#ibcon#about to write, iclass 19, count 0 2006.257.17:01:46.78#ibcon#wrote, iclass 19, count 0 2006.257.17:01:46.78#ibcon#about to read 3, iclass 19, count 0 2006.257.17:01:46.80#ibcon#read 3, iclass 19, count 0 2006.257.17:01:46.80#ibcon#about to read 4, iclass 19, count 0 2006.257.17:01:46.80#ibcon#read 4, iclass 19, count 0 2006.257.17:01:46.80#ibcon#about to read 5, iclass 19, count 0 2006.257.17:01:46.80#ibcon#read 5, iclass 19, count 0 2006.257.17:01:46.80#ibcon#about to read 6, iclass 19, count 0 2006.257.17:01:46.80#ibcon#read 6, iclass 19, count 0 2006.257.17:01:46.80#ibcon#end of sib2, iclass 19, count 0 2006.257.17:01:46.80#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:01:46.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:01:46.80#ibcon#[25=BW32\r\n] 2006.257.17:01:46.80#ibcon#*before write, iclass 19, count 0 2006.257.17:01:46.80#ibcon#enter sib2, iclass 19, count 0 2006.257.17:01:46.80#ibcon#flushed, iclass 19, count 0 2006.257.17:01:46.80#ibcon#about to write, iclass 19, count 0 2006.257.17:01:46.80#ibcon#wrote, iclass 19, count 0 2006.257.17:01:46.80#ibcon#about to read 3, iclass 19, count 0 2006.257.17:01:46.83#ibcon#read 3, iclass 19, count 0 2006.257.17:01:46.83#ibcon#about to read 4, iclass 19, count 0 2006.257.17:01:46.83#ibcon#read 4, iclass 19, count 0 2006.257.17:01:46.83#ibcon#about to read 5, iclass 19, count 0 2006.257.17:01:46.83#ibcon#read 5, iclass 19, count 0 2006.257.17:01:46.83#ibcon#about to read 6, iclass 19, count 0 2006.257.17:01:46.83#ibcon#read 6, iclass 19, count 0 2006.257.17:01:46.83#ibcon#end of sib2, iclass 19, count 0 2006.257.17:01:46.83#ibcon#*after write, iclass 19, count 0 2006.257.17:01:46.83#ibcon#*before return 0, iclass 19, count 0 2006.257.17:01:46.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:46.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:01:46.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:01:46.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:01:46.83$vck44/vbbw=wide 2006.257.17:01:46.83#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.17:01:46.83#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.17:01:46.83#ibcon#ireg 8 cls_cnt 0 2006.257.17:01:46.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:01:46.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:01:46.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:01:46.90#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:01:46.90#ibcon#first serial, iclass 21, count 0 2006.257.17:01:46.90#ibcon#enter sib2, iclass 21, count 0 2006.257.17:01:46.90#ibcon#flushed, iclass 21, count 0 2006.257.17:01:46.90#ibcon#about to write, iclass 21, count 0 2006.257.17:01:46.90#ibcon#wrote, iclass 21, count 0 2006.257.17:01:46.90#ibcon#about to read 3, iclass 21, count 0 2006.257.17:01:46.92#ibcon#read 3, iclass 21, count 0 2006.257.17:01:46.92#ibcon#about to read 4, iclass 21, count 0 2006.257.17:01:46.92#ibcon#read 4, iclass 21, count 0 2006.257.17:01:46.92#ibcon#about to read 5, iclass 21, count 0 2006.257.17:01:46.92#ibcon#read 5, iclass 21, count 0 2006.257.17:01:46.92#ibcon#about to read 6, iclass 21, count 0 2006.257.17:01:46.92#ibcon#read 6, iclass 21, count 0 2006.257.17:01:46.92#ibcon#end of sib2, iclass 21, count 0 2006.257.17:01:46.92#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:01:46.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:01:46.92#ibcon#[27=BW32\r\n] 2006.257.17:01:46.92#ibcon#*before write, iclass 21, count 0 2006.257.17:01:46.92#ibcon#enter sib2, iclass 21, count 0 2006.257.17:01:46.92#ibcon#flushed, iclass 21, count 0 2006.257.17:01:46.92#ibcon#about to write, iclass 21, count 0 2006.257.17:01:46.92#ibcon#wrote, iclass 21, count 0 2006.257.17:01:46.92#ibcon#about to read 3, iclass 21, count 0 2006.257.17:01:46.95#ibcon#read 3, iclass 21, count 0 2006.257.17:01:46.95#ibcon#about to read 4, iclass 21, count 0 2006.257.17:01:46.95#ibcon#read 4, iclass 21, count 0 2006.257.17:01:46.95#ibcon#about to read 5, iclass 21, count 0 2006.257.17:01:46.95#ibcon#read 5, iclass 21, count 0 2006.257.17:01:46.95#ibcon#about to read 6, iclass 21, count 0 2006.257.17:01:46.95#ibcon#read 6, iclass 21, count 0 2006.257.17:01:46.95#ibcon#end of sib2, iclass 21, count 0 2006.257.17:01:46.95#ibcon#*after write, iclass 21, count 0 2006.257.17:01:46.95#ibcon#*before return 0, iclass 21, count 0 2006.257.17:01:46.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:01:46.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:01:46.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:01:46.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:01:46.95$setupk4/ifdk4 2006.257.17:01:46.95$ifdk4/lo= 2006.257.17:01:46.95$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:01:46.95$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:01:46.95$ifdk4/patch= 2006.257.17:01:46.95$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:01:46.95$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:01:46.95$setupk4/!*+20s 2006.257.17:01:52.55#abcon#<5=/14 1.5 5.3 17.35 961014.2\r\n> 2006.257.17:01:52.57#abcon#{5=INTERFACE CLEAR} 2006.257.17:01:52.63#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:02:01.47$setupk4/"tpicd 2006.257.17:02:01.47$setupk4/echo=off 2006.257.17:02:01.47$setupk4/xlog=off 2006.257.17:02:01.47:!2006.257.17:04:41 2006.257.17:02:37.13#trakl#Source acquired 2006.257.17:02:37.13#flagr#flagr/antenna,acquired 2006.257.17:04:41.00:preob 2006.257.17:04:41.14/onsource/TRACKING 2006.257.17:04:41.14:!2006.257.17:04:51 2006.257.17:04:51.00:"tape 2006.257.17:04:51.00:"st=record 2006.257.17:04:51.00:data_valid=on 2006.257.17:04:51.00:midob 2006.257.17:04:52.14/onsource/TRACKING 2006.257.17:04:52.14/wx/17.36,1014.2,96 2006.257.17:04:52.32/cable/+6.4861E-03 2006.257.17:04:53.41/va/01,08,usb,yes,31,33 2006.257.17:04:53.41/va/02,07,usb,yes,33,34 2006.257.17:04:53.41/va/03,08,usb,yes,30,32 2006.257.17:04:53.41/va/04,07,usb,yes,34,36 2006.257.17:04:53.41/va/05,04,usb,yes,31,31 2006.257.17:04:53.41/va/06,04,usb,yes,34,34 2006.257.17:04:53.41/va/07,04,usb,yes,35,36 2006.257.17:04:53.41/va/08,04,usb,yes,29,36 2006.257.17:04:53.64/valo/01,524.99,yes,locked 2006.257.17:04:53.64/valo/02,534.99,yes,locked 2006.257.17:04:53.64/valo/03,564.99,yes,locked 2006.257.17:04:53.64/valo/04,624.99,yes,locked 2006.257.17:04:53.64/valo/05,734.99,yes,locked 2006.257.17:04:53.64/valo/06,814.99,yes,locked 2006.257.17:04:53.64/valo/07,864.99,yes,locked 2006.257.17:04:53.64/valo/08,884.99,yes,locked 2006.257.17:04:54.73/vb/01,04,usb,yes,30,28 2006.257.17:04:54.73/vb/02,05,usb,yes,28,28 2006.257.17:04:54.73/vb/03,04,usb,yes,29,32 2006.257.17:04:54.73/vb/04,05,usb,yes,30,28 2006.257.17:04:54.73/vb/05,04,usb,yes,26,28 2006.257.17:04:54.73/vb/06,04,usb,yes,30,27 2006.257.17:04:54.73/vb/07,04,usb,yes,30,30 2006.257.17:04:54.73/vb/08,04,usb,yes,28,31 2006.257.17:04:54.96/vblo/01,629.99,yes,locked 2006.257.17:04:54.96/vblo/02,634.99,yes,locked 2006.257.17:04:54.96/vblo/03,649.99,yes,locked 2006.257.17:04:54.96/vblo/04,679.99,yes,locked 2006.257.17:04:54.96/vblo/05,709.99,yes,locked 2006.257.17:04:54.96/vblo/06,719.99,yes,locked 2006.257.17:04:54.96/vblo/07,734.99,yes,locked 2006.257.17:04:54.96/vblo/08,744.99,yes,locked 2006.257.17:04:55.11/vabw/8 2006.257.17:04:55.26/vbbw/8 2006.257.17:04:55.35/xfe/off,on,15.0 2006.257.17:04:55.74/ifatt/23,28,28,28 2006.257.17:04:56.07/fmout-gps/S +4.54E-07 2006.257.17:04:56.11:!2006.257.17:06:21 2006.257.17:06:21.01:data_valid=off 2006.257.17:06:21.01:"et 2006.257.17:06:21.01:!+3s 2006.257.17:06:24.02:"tape 2006.257.17:06:24.02:postob 2006.257.17:06:24.12/cable/+6.4843E-03 2006.257.17:06:24.12/wx/17.36,1014.2,96 2006.257.17:06:24.18/fmout-gps/S +4.53E-07 2006.257.17:06:24.18:scan_name=257-1710,jd0609,190 2006.257.17:06:24.18:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.257.17:06:25.14#flagr#flagr/antenna,new-source 2006.257.17:06:25.14:checkk5 2006.257.17:06:25.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:06:25.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:06:26.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:06:26.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:06:26.84/chk_obsdata//k5ts1/T2571704??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.17:06:27.17/chk_obsdata//k5ts2/T2571704??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.17:06:27.51/chk_obsdata//k5ts3/T2571704??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.17:06:27.84/chk_obsdata//k5ts4/T2571704??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.17:06:28.50/k5log//k5ts1_log_newline 2006.257.17:06:29.16/k5log//k5ts2_log_newline 2006.257.17:06:29.81/k5log//k5ts3_log_newline 2006.257.17:06:30.46/k5log//k5ts4_log_newline 2006.257.17:06:30.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:06:30.48:setupk4=1 2006.257.17:06:30.49$setupk4/echo=on 2006.257.17:06:30.49$setupk4/pcalon 2006.257.17:06:30.49$pcalon/"no phase cal control is implemented here 2006.257.17:06:30.49$setupk4/"tpicd=stop 2006.257.17:06:30.49$setupk4/"rec=synch_on 2006.257.17:06:30.49$setupk4/"rec_mode=128 2006.257.17:06:30.49$setupk4/!* 2006.257.17:06:30.49$setupk4/recpk4 2006.257.17:06:30.49$recpk4/recpatch= 2006.257.17:06:30.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:06:30.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:06:30.49$setupk4/vck44 2006.257.17:06:30.49$vck44/valo=1,524.99 2006.257.17:06:30.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.17:06:30.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.17:06:30.49#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:30.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:30.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:30.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:30.49#ibcon#enter wrdev, iclass 30, count 0 2006.257.17:06:30.49#ibcon#first serial, iclass 30, count 0 2006.257.17:06:30.49#ibcon#enter sib2, iclass 30, count 0 2006.257.17:06:30.49#ibcon#flushed, iclass 30, count 0 2006.257.17:06:30.49#ibcon#about to write, iclass 30, count 0 2006.257.17:06:30.49#ibcon#wrote, iclass 30, count 0 2006.257.17:06:30.49#ibcon#about to read 3, iclass 30, count 0 2006.257.17:06:30.51#ibcon#read 3, iclass 30, count 0 2006.257.17:06:30.51#ibcon#about to read 4, iclass 30, count 0 2006.257.17:06:30.51#ibcon#read 4, iclass 30, count 0 2006.257.17:06:30.51#ibcon#about to read 5, iclass 30, count 0 2006.257.17:06:30.51#ibcon#read 5, iclass 30, count 0 2006.257.17:06:30.51#ibcon#about to read 6, iclass 30, count 0 2006.257.17:06:30.51#ibcon#read 6, iclass 30, count 0 2006.257.17:06:30.51#ibcon#end of sib2, iclass 30, count 0 2006.257.17:06:30.51#ibcon#*mode == 0, iclass 30, count 0 2006.257.17:06:30.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.17:06:30.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:06:30.51#ibcon#*before write, iclass 30, count 0 2006.257.17:06:30.51#ibcon#enter sib2, iclass 30, count 0 2006.257.17:06:30.51#ibcon#flushed, iclass 30, count 0 2006.257.17:06:30.51#ibcon#about to write, iclass 30, count 0 2006.257.17:06:30.51#ibcon#wrote, iclass 30, count 0 2006.257.17:06:30.51#ibcon#about to read 3, iclass 30, count 0 2006.257.17:06:30.56#ibcon#read 3, iclass 30, count 0 2006.257.17:06:30.56#ibcon#about to read 4, iclass 30, count 0 2006.257.17:06:30.56#ibcon#read 4, iclass 30, count 0 2006.257.17:06:30.56#ibcon#about to read 5, iclass 30, count 0 2006.257.17:06:30.56#ibcon#read 5, iclass 30, count 0 2006.257.17:06:30.56#ibcon#about to read 6, iclass 30, count 0 2006.257.17:06:30.56#ibcon#read 6, iclass 30, count 0 2006.257.17:06:30.56#ibcon#end of sib2, iclass 30, count 0 2006.257.17:06:30.56#ibcon#*after write, iclass 30, count 0 2006.257.17:06:30.56#ibcon#*before return 0, iclass 30, count 0 2006.257.17:06:30.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:30.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:30.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.17:06:30.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.17:06:30.56$vck44/va=1,8 2006.257.17:06:30.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.17:06:30.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.17:06:30.56#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:30.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:30.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:30.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:30.56#ibcon#enter wrdev, iclass 32, count 2 2006.257.17:06:30.56#ibcon#first serial, iclass 32, count 2 2006.257.17:06:30.56#ibcon#enter sib2, iclass 32, count 2 2006.257.17:06:30.56#ibcon#flushed, iclass 32, count 2 2006.257.17:06:30.56#ibcon#about to write, iclass 32, count 2 2006.257.17:06:30.56#ibcon#wrote, iclass 32, count 2 2006.257.17:06:30.56#ibcon#about to read 3, iclass 32, count 2 2006.257.17:06:30.58#ibcon#read 3, iclass 32, count 2 2006.257.17:06:30.58#ibcon#about to read 4, iclass 32, count 2 2006.257.17:06:30.58#ibcon#read 4, iclass 32, count 2 2006.257.17:06:30.58#ibcon#about to read 5, iclass 32, count 2 2006.257.17:06:30.58#ibcon#read 5, iclass 32, count 2 2006.257.17:06:30.58#ibcon#about to read 6, iclass 32, count 2 2006.257.17:06:30.58#ibcon#read 6, iclass 32, count 2 2006.257.17:06:30.58#ibcon#end of sib2, iclass 32, count 2 2006.257.17:06:30.58#ibcon#*mode == 0, iclass 32, count 2 2006.257.17:06:30.58#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.17:06:30.58#ibcon#[25=AT01-08\r\n] 2006.257.17:06:30.58#ibcon#*before write, iclass 32, count 2 2006.257.17:06:30.58#ibcon#enter sib2, iclass 32, count 2 2006.257.17:06:30.58#ibcon#flushed, iclass 32, count 2 2006.257.17:06:30.58#ibcon#about to write, iclass 32, count 2 2006.257.17:06:30.58#ibcon#wrote, iclass 32, count 2 2006.257.17:06:30.58#ibcon#about to read 3, iclass 32, count 2 2006.257.17:06:30.61#ibcon#read 3, iclass 32, count 2 2006.257.17:06:30.61#ibcon#about to read 4, iclass 32, count 2 2006.257.17:06:30.61#ibcon#read 4, iclass 32, count 2 2006.257.17:06:30.61#ibcon#about to read 5, iclass 32, count 2 2006.257.17:06:30.61#ibcon#read 5, iclass 32, count 2 2006.257.17:06:30.61#ibcon#about to read 6, iclass 32, count 2 2006.257.17:06:30.61#ibcon#read 6, iclass 32, count 2 2006.257.17:06:30.61#ibcon#end of sib2, iclass 32, count 2 2006.257.17:06:30.61#ibcon#*after write, iclass 32, count 2 2006.257.17:06:30.61#ibcon#*before return 0, iclass 32, count 2 2006.257.17:06:30.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:30.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:30.61#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.17:06:30.61#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:30.61#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:30.73#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:30.73#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:30.73#ibcon#enter wrdev, iclass 32, count 0 2006.257.17:06:30.73#ibcon#first serial, iclass 32, count 0 2006.257.17:06:30.73#ibcon#enter sib2, iclass 32, count 0 2006.257.17:06:30.73#ibcon#flushed, iclass 32, count 0 2006.257.17:06:30.73#ibcon#about to write, iclass 32, count 0 2006.257.17:06:30.73#ibcon#wrote, iclass 32, count 0 2006.257.17:06:30.73#ibcon#about to read 3, iclass 32, count 0 2006.257.17:06:30.75#ibcon#read 3, iclass 32, count 0 2006.257.17:06:30.75#ibcon#about to read 4, iclass 32, count 0 2006.257.17:06:30.75#ibcon#read 4, iclass 32, count 0 2006.257.17:06:30.75#ibcon#about to read 5, iclass 32, count 0 2006.257.17:06:30.75#ibcon#read 5, iclass 32, count 0 2006.257.17:06:30.75#ibcon#about to read 6, iclass 32, count 0 2006.257.17:06:30.75#ibcon#read 6, iclass 32, count 0 2006.257.17:06:30.75#ibcon#end of sib2, iclass 32, count 0 2006.257.17:06:30.75#ibcon#*mode == 0, iclass 32, count 0 2006.257.17:06:30.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.17:06:30.75#ibcon#[25=USB\r\n] 2006.257.17:06:30.75#ibcon#*before write, iclass 32, count 0 2006.257.17:06:30.75#ibcon#enter sib2, iclass 32, count 0 2006.257.17:06:30.75#ibcon#flushed, iclass 32, count 0 2006.257.17:06:30.75#ibcon#about to write, iclass 32, count 0 2006.257.17:06:30.75#ibcon#wrote, iclass 32, count 0 2006.257.17:06:30.75#ibcon#about to read 3, iclass 32, count 0 2006.257.17:06:30.78#ibcon#read 3, iclass 32, count 0 2006.257.17:06:30.78#ibcon#about to read 4, iclass 32, count 0 2006.257.17:06:30.78#ibcon#read 4, iclass 32, count 0 2006.257.17:06:30.78#ibcon#about to read 5, iclass 32, count 0 2006.257.17:06:30.78#ibcon#read 5, iclass 32, count 0 2006.257.17:06:30.78#ibcon#about to read 6, iclass 32, count 0 2006.257.17:06:30.78#ibcon#read 6, iclass 32, count 0 2006.257.17:06:30.78#ibcon#end of sib2, iclass 32, count 0 2006.257.17:06:30.78#ibcon#*after write, iclass 32, count 0 2006.257.17:06:30.78#ibcon#*before return 0, iclass 32, count 0 2006.257.17:06:30.78#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:30.78#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:30.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.17:06:30.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.17:06:30.78$vck44/valo=2,534.99 2006.257.17:06:30.78#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.17:06:30.78#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.17:06:30.78#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:30.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:30.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:30.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:30.78#ibcon#enter wrdev, iclass 34, count 0 2006.257.17:06:30.78#ibcon#first serial, iclass 34, count 0 2006.257.17:06:30.78#ibcon#enter sib2, iclass 34, count 0 2006.257.17:06:30.78#ibcon#flushed, iclass 34, count 0 2006.257.17:06:30.78#ibcon#about to write, iclass 34, count 0 2006.257.17:06:30.78#ibcon#wrote, iclass 34, count 0 2006.257.17:06:30.78#ibcon#about to read 3, iclass 34, count 0 2006.257.17:06:30.80#ibcon#read 3, iclass 34, count 0 2006.257.17:06:30.80#ibcon#about to read 4, iclass 34, count 0 2006.257.17:06:30.80#ibcon#read 4, iclass 34, count 0 2006.257.17:06:30.80#ibcon#about to read 5, iclass 34, count 0 2006.257.17:06:30.80#ibcon#read 5, iclass 34, count 0 2006.257.17:06:30.80#ibcon#about to read 6, iclass 34, count 0 2006.257.17:06:30.80#ibcon#read 6, iclass 34, count 0 2006.257.17:06:30.80#ibcon#end of sib2, iclass 34, count 0 2006.257.17:06:30.80#ibcon#*mode == 0, iclass 34, count 0 2006.257.17:06:30.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.17:06:30.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:06:30.80#ibcon#*before write, iclass 34, count 0 2006.257.17:06:30.80#ibcon#enter sib2, iclass 34, count 0 2006.257.17:06:30.80#ibcon#flushed, iclass 34, count 0 2006.257.17:06:30.80#ibcon#about to write, iclass 34, count 0 2006.257.17:06:30.80#ibcon#wrote, iclass 34, count 0 2006.257.17:06:30.80#ibcon#about to read 3, iclass 34, count 0 2006.257.17:06:30.84#ibcon#read 3, iclass 34, count 0 2006.257.17:06:30.84#ibcon#about to read 4, iclass 34, count 0 2006.257.17:06:30.84#ibcon#read 4, iclass 34, count 0 2006.257.17:06:30.84#ibcon#about to read 5, iclass 34, count 0 2006.257.17:06:30.84#ibcon#read 5, iclass 34, count 0 2006.257.17:06:30.84#ibcon#about to read 6, iclass 34, count 0 2006.257.17:06:30.84#ibcon#read 6, iclass 34, count 0 2006.257.17:06:30.84#ibcon#end of sib2, iclass 34, count 0 2006.257.17:06:30.84#ibcon#*after write, iclass 34, count 0 2006.257.17:06:30.84#ibcon#*before return 0, iclass 34, count 0 2006.257.17:06:30.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:30.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:30.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.17:06:30.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.17:06:30.84$vck44/va=2,7 2006.257.17:06:30.84#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.17:06:30.84#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.17:06:30.84#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:30.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:30.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:30.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:30.90#ibcon#enter wrdev, iclass 36, count 2 2006.257.17:06:30.90#ibcon#first serial, iclass 36, count 2 2006.257.17:06:30.90#ibcon#enter sib2, iclass 36, count 2 2006.257.17:06:30.90#ibcon#flushed, iclass 36, count 2 2006.257.17:06:30.90#ibcon#about to write, iclass 36, count 2 2006.257.17:06:30.90#ibcon#wrote, iclass 36, count 2 2006.257.17:06:30.90#ibcon#about to read 3, iclass 36, count 2 2006.257.17:06:30.92#ibcon#read 3, iclass 36, count 2 2006.257.17:06:30.92#ibcon#about to read 4, iclass 36, count 2 2006.257.17:06:30.92#ibcon#read 4, iclass 36, count 2 2006.257.17:06:30.92#ibcon#about to read 5, iclass 36, count 2 2006.257.17:06:30.92#ibcon#read 5, iclass 36, count 2 2006.257.17:06:30.92#ibcon#about to read 6, iclass 36, count 2 2006.257.17:06:30.92#ibcon#read 6, iclass 36, count 2 2006.257.17:06:30.92#ibcon#end of sib2, iclass 36, count 2 2006.257.17:06:30.92#ibcon#*mode == 0, iclass 36, count 2 2006.257.17:06:30.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.17:06:30.92#ibcon#[25=AT02-07\r\n] 2006.257.17:06:30.92#ibcon#*before write, iclass 36, count 2 2006.257.17:06:30.92#ibcon#enter sib2, iclass 36, count 2 2006.257.17:06:30.92#ibcon#flushed, iclass 36, count 2 2006.257.17:06:30.92#ibcon#about to write, iclass 36, count 2 2006.257.17:06:30.92#ibcon#wrote, iclass 36, count 2 2006.257.17:06:30.92#ibcon#about to read 3, iclass 36, count 2 2006.257.17:06:30.95#ibcon#read 3, iclass 36, count 2 2006.257.17:06:30.95#ibcon#about to read 4, iclass 36, count 2 2006.257.17:06:30.95#ibcon#read 4, iclass 36, count 2 2006.257.17:06:30.95#ibcon#about to read 5, iclass 36, count 2 2006.257.17:06:30.95#ibcon#read 5, iclass 36, count 2 2006.257.17:06:30.95#ibcon#about to read 6, iclass 36, count 2 2006.257.17:06:30.95#ibcon#read 6, iclass 36, count 2 2006.257.17:06:30.95#ibcon#end of sib2, iclass 36, count 2 2006.257.17:06:30.95#ibcon#*after write, iclass 36, count 2 2006.257.17:06:30.95#ibcon#*before return 0, iclass 36, count 2 2006.257.17:06:30.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:30.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:30.95#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.17:06:30.95#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:30.95#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:31.07#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:31.07#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:31.07#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:06:31.07#ibcon#first serial, iclass 36, count 0 2006.257.17:06:31.07#ibcon#enter sib2, iclass 36, count 0 2006.257.17:06:31.07#ibcon#flushed, iclass 36, count 0 2006.257.17:06:31.07#ibcon#about to write, iclass 36, count 0 2006.257.17:06:31.07#ibcon#wrote, iclass 36, count 0 2006.257.17:06:31.07#ibcon#about to read 3, iclass 36, count 0 2006.257.17:06:31.09#ibcon#read 3, iclass 36, count 0 2006.257.17:06:31.09#ibcon#about to read 4, iclass 36, count 0 2006.257.17:06:31.09#ibcon#read 4, iclass 36, count 0 2006.257.17:06:31.09#ibcon#about to read 5, iclass 36, count 0 2006.257.17:06:31.09#ibcon#read 5, iclass 36, count 0 2006.257.17:06:31.09#ibcon#about to read 6, iclass 36, count 0 2006.257.17:06:31.09#ibcon#read 6, iclass 36, count 0 2006.257.17:06:31.09#ibcon#end of sib2, iclass 36, count 0 2006.257.17:06:31.09#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:06:31.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:06:31.09#ibcon#[25=USB\r\n] 2006.257.17:06:31.09#ibcon#*before write, iclass 36, count 0 2006.257.17:06:31.09#ibcon#enter sib2, iclass 36, count 0 2006.257.17:06:31.09#ibcon#flushed, iclass 36, count 0 2006.257.17:06:31.09#ibcon#about to write, iclass 36, count 0 2006.257.17:06:31.09#ibcon#wrote, iclass 36, count 0 2006.257.17:06:31.09#ibcon#about to read 3, iclass 36, count 0 2006.257.17:06:31.12#ibcon#read 3, iclass 36, count 0 2006.257.17:06:31.12#ibcon#about to read 4, iclass 36, count 0 2006.257.17:06:31.12#ibcon#read 4, iclass 36, count 0 2006.257.17:06:31.12#ibcon#about to read 5, iclass 36, count 0 2006.257.17:06:31.12#ibcon#read 5, iclass 36, count 0 2006.257.17:06:31.12#ibcon#about to read 6, iclass 36, count 0 2006.257.17:06:31.12#ibcon#read 6, iclass 36, count 0 2006.257.17:06:31.12#ibcon#end of sib2, iclass 36, count 0 2006.257.17:06:31.12#ibcon#*after write, iclass 36, count 0 2006.257.17:06:31.12#ibcon#*before return 0, iclass 36, count 0 2006.257.17:06:31.12#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:31.12#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:31.12#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:06:31.12#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:06:31.12$vck44/valo=3,564.99 2006.257.17:06:31.12#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.17:06:31.12#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.17:06:31.12#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:31.12#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:31.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:31.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:31.12#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:06:31.12#ibcon#first serial, iclass 38, count 0 2006.257.17:06:31.12#ibcon#enter sib2, iclass 38, count 0 2006.257.17:06:31.12#ibcon#flushed, iclass 38, count 0 2006.257.17:06:31.12#ibcon#about to write, iclass 38, count 0 2006.257.17:06:31.12#ibcon#wrote, iclass 38, count 0 2006.257.17:06:31.12#ibcon#about to read 3, iclass 38, count 0 2006.257.17:06:31.14#ibcon#read 3, iclass 38, count 0 2006.257.17:06:31.14#ibcon#about to read 4, iclass 38, count 0 2006.257.17:06:31.14#ibcon#read 4, iclass 38, count 0 2006.257.17:06:31.14#ibcon#about to read 5, iclass 38, count 0 2006.257.17:06:31.14#ibcon#read 5, iclass 38, count 0 2006.257.17:06:31.14#ibcon#about to read 6, iclass 38, count 0 2006.257.17:06:31.14#ibcon#read 6, iclass 38, count 0 2006.257.17:06:31.14#ibcon#end of sib2, iclass 38, count 0 2006.257.17:06:31.14#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:06:31.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:06:31.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:06:31.14#ibcon#*before write, iclass 38, count 0 2006.257.17:06:31.14#ibcon#enter sib2, iclass 38, count 0 2006.257.17:06:31.14#ibcon#flushed, iclass 38, count 0 2006.257.17:06:31.14#ibcon#about to write, iclass 38, count 0 2006.257.17:06:31.14#ibcon#wrote, iclass 38, count 0 2006.257.17:06:31.14#ibcon#about to read 3, iclass 38, count 0 2006.257.17:06:31.18#ibcon#read 3, iclass 38, count 0 2006.257.17:06:31.18#ibcon#about to read 4, iclass 38, count 0 2006.257.17:06:31.18#ibcon#read 4, iclass 38, count 0 2006.257.17:06:31.18#ibcon#about to read 5, iclass 38, count 0 2006.257.17:06:31.18#ibcon#read 5, iclass 38, count 0 2006.257.17:06:31.18#ibcon#about to read 6, iclass 38, count 0 2006.257.17:06:31.18#ibcon#read 6, iclass 38, count 0 2006.257.17:06:31.18#ibcon#end of sib2, iclass 38, count 0 2006.257.17:06:31.18#ibcon#*after write, iclass 38, count 0 2006.257.17:06:31.18#ibcon#*before return 0, iclass 38, count 0 2006.257.17:06:31.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:31.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:31.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:06:31.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:06:31.18$vck44/va=3,8 2006.257.17:06:31.18#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.17:06:31.18#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.17:06:31.18#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:31.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:31.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:31.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:31.24#ibcon#enter wrdev, iclass 40, count 2 2006.257.17:06:31.24#ibcon#first serial, iclass 40, count 2 2006.257.17:06:31.24#ibcon#enter sib2, iclass 40, count 2 2006.257.17:06:31.24#ibcon#flushed, iclass 40, count 2 2006.257.17:06:31.24#ibcon#about to write, iclass 40, count 2 2006.257.17:06:31.24#ibcon#wrote, iclass 40, count 2 2006.257.17:06:31.24#ibcon#about to read 3, iclass 40, count 2 2006.257.17:06:31.26#ibcon#read 3, iclass 40, count 2 2006.257.17:06:31.26#ibcon#about to read 4, iclass 40, count 2 2006.257.17:06:31.26#ibcon#read 4, iclass 40, count 2 2006.257.17:06:31.26#ibcon#about to read 5, iclass 40, count 2 2006.257.17:06:31.26#ibcon#read 5, iclass 40, count 2 2006.257.17:06:31.26#ibcon#about to read 6, iclass 40, count 2 2006.257.17:06:31.26#ibcon#read 6, iclass 40, count 2 2006.257.17:06:31.26#ibcon#end of sib2, iclass 40, count 2 2006.257.17:06:31.26#ibcon#*mode == 0, iclass 40, count 2 2006.257.17:06:31.26#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.17:06:31.26#ibcon#[25=AT03-08\r\n] 2006.257.17:06:31.26#ibcon#*before write, iclass 40, count 2 2006.257.17:06:31.26#ibcon#enter sib2, iclass 40, count 2 2006.257.17:06:31.26#ibcon#flushed, iclass 40, count 2 2006.257.17:06:31.26#ibcon#about to write, iclass 40, count 2 2006.257.17:06:31.26#ibcon#wrote, iclass 40, count 2 2006.257.17:06:31.26#ibcon#about to read 3, iclass 40, count 2 2006.257.17:06:31.29#ibcon#read 3, iclass 40, count 2 2006.257.17:06:31.29#ibcon#about to read 4, iclass 40, count 2 2006.257.17:06:31.29#ibcon#read 4, iclass 40, count 2 2006.257.17:06:31.29#ibcon#about to read 5, iclass 40, count 2 2006.257.17:06:31.29#ibcon#read 5, iclass 40, count 2 2006.257.17:06:31.29#ibcon#about to read 6, iclass 40, count 2 2006.257.17:06:31.29#ibcon#read 6, iclass 40, count 2 2006.257.17:06:31.29#ibcon#end of sib2, iclass 40, count 2 2006.257.17:06:31.29#ibcon#*after write, iclass 40, count 2 2006.257.17:06:31.29#ibcon#*before return 0, iclass 40, count 2 2006.257.17:06:31.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:31.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:31.29#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.17:06:31.29#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:31.29#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:31.41#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:31.41#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:31.41#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:06:31.41#ibcon#first serial, iclass 40, count 0 2006.257.17:06:31.41#ibcon#enter sib2, iclass 40, count 0 2006.257.17:06:31.41#ibcon#flushed, iclass 40, count 0 2006.257.17:06:31.41#ibcon#about to write, iclass 40, count 0 2006.257.17:06:31.41#ibcon#wrote, iclass 40, count 0 2006.257.17:06:31.41#ibcon#about to read 3, iclass 40, count 0 2006.257.17:06:31.43#ibcon#read 3, iclass 40, count 0 2006.257.17:06:31.43#ibcon#about to read 4, iclass 40, count 0 2006.257.17:06:31.43#ibcon#read 4, iclass 40, count 0 2006.257.17:06:31.43#ibcon#about to read 5, iclass 40, count 0 2006.257.17:06:31.43#ibcon#read 5, iclass 40, count 0 2006.257.17:06:31.43#ibcon#about to read 6, iclass 40, count 0 2006.257.17:06:31.43#ibcon#read 6, iclass 40, count 0 2006.257.17:06:31.43#ibcon#end of sib2, iclass 40, count 0 2006.257.17:06:31.43#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:06:31.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:06:31.43#ibcon#[25=USB\r\n] 2006.257.17:06:31.43#ibcon#*before write, iclass 40, count 0 2006.257.17:06:31.43#ibcon#enter sib2, iclass 40, count 0 2006.257.17:06:31.43#ibcon#flushed, iclass 40, count 0 2006.257.17:06:31.43#ibcon#about to write, iclass 40, count 0 2006.257.17:06:31.43#ibcon#wrote, iclass 40, count 0 2006.257.17:06:31.43#ibcon#about to read 3, iclass 40, count 0 2006.257.17:06:31.46#ibcon#read 3, iclass 40, count 0 2006.257.17:06:31.46#ibcon#about to read 4, iclass 40, count 0 2006.257.17:06:31.46#ibcon#read 4, iclass 40, count 0 2006.257.17:06:31.46#ibcon#about to read 5, iclass 40, count 0 2006.257.17:06:31.46#ibcon#read 5, iclass 40, count 0 2006.257.17:06:31.46#ibcon#about to read 6, iclass 40, count 0 2006.257.17:06:31.46#ibcon#read 6, iclass 40, count 0 2006.257.17:06:31.46#ibcon#end of sib2, iclass 40, count 0 2006.257.17:06:31.46#ibcon#*after write, iclass 40, count 0 2006.257.17:06:31.46#ibcon#*before return 0, iclass 40, count 0 2006.257.17:06:31.46#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:31.46#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:31.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:06:31.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:06:31.46$vck44/valo=4,624.99 2006.257.17:06:31.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.17:06:31.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.17:06:31.46#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:31.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:31.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:31.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:31.46#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:06:31.46#ibcon#first serial, iclass 4, count 0 2006.257.17:06:31.46#ibcon#enter sib2, iclass 4, count 0 2006.257.17:06:31.46#ibcon#flushed, iclass 4, count 0 2006.257.17:06:31.46#ibcon#about to write, iclass 4, count 0 2006.257.17:06:31.46#ibcon#wrote, iclass 4, count 0 2006.257.17:06:31.46#ibcon#about to read 3, iclass 4, count 0 2006.257.17:06:31.48#ibcon#read 3, iclass 4, count 0 2006.257.17:06:31.48#ibcon#about to read 4, iclass 4, count 0 2006.257.17:06:31.48#ibcon#read 4, iclass 4, count 0 2006.257.17:06:31.48#ibcon#about to read 5, iclass 4, count 0 2006.257.17:06:31.48#ibcon#read 5, iclass 4, count 0 2006.257.17:06:31.48#ibcon#about to read 6, iclass 4, count 0 2006.257.17:06:31.48#ibcon#read 6, iclass 4, count 0 2006.257.17:06:31.48#ibcon#end of sib2, iclass 4, count 0 2006.257.17:06:31.48#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:06:31.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:06:31.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:06:31.48#ibcon#*before write, iclass 4, count 0 2006.257.17:06:31.48#ibcon#enter sib2, iclass 4, count 0 2006.257.17:06:31.48#ibcon#flushed, iclass 4, count 0 2006.257.17:06:31.48#ibcon#about to write, iclass 4, count 0 2006.257.17:06:31.48#ibcon#wrote, iclass 4, count 0 2006.257.17:06:31.48#ibcon#about to read 3, iclass 4, count 0 2006.257.17:06:31.52#ibcon#read 3, iclass 4, count 0 2006.257.17:06:31.52#ibcon#about to read 4, iclass 4, count 0 2006.257.17:06:31.52#ibcon#read 4, iclass 4, count 0 2006.257.17:06:31.52#ibcon#about to read 5, iclass 4, count 0 2006.257.17:06:31.52#ibcon#read 5, iclass 4, count 0 2006.257.17:06:31.52#ibcon#about to read 6, iclass 4, count 0 2006.257.17:06:31.52#ibcon#read 6, iclass 4, count 0 2006.257.17:06:31.52#ibcon#end of sib2, iclass 4, count 0 2006.257.17:06:31.52#ibcon#*after write, iclass 4, count 0 2006.257.17:06:31.52#ibcon#*before return 0, iclass 4, count 0 2006.257.17:06:31.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:31.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:31.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:06:31.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:06:31.52$vck44/va=4,7 2006.257.17:06:31.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.17:06:31.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.17:06:31.52#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:31.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:31.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:31.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:31.58#ibcon#enter wrdev, iclass 6, count 2 2006.257.17:06:31.58#ibcon#first serial, iclass 6, count 2 2006.257.17:06:31.58#ibcon#enter sib2, iclass 6, count 2 2006.257.17:06:31.58#ibcon#flushed, iclass 6, count 2 2006.257.17:06:31.58#ibcon#about to write, iclass 6, count 2 2006.257.17:06:31.58#ibcon#wrote, iclass 6, count 2 2006.257.17:06:31.58#ibcon#about to read 3, iclass 6, count 2 2006.257.17:06:31.60#ibcon#read 3, iclass 6, count 2 2006.257.17:06:31.60#ibcon#about to read 4, iclass 6, count 2 2006.257.17:06:31.60#ibcon#read 4, iclass 6, count 2 2006.257.17:06:31.60#ibcon#about to read 5, iclass 6, count 2 2006.257.17:06:31.60#ibcon#read 5, iclass 6, count 2 2006.257.17:06:31.60#ibcon#about to read 6, iclass 6, count 2 2006.257.17:06:31.60#ibcon#read 6, iclass 6, count 2 2006.257.17:06:31.60#ibcon#end of sib2, iclass 6, count 2 2006.257.17:06:31.60#ibcon#*mode == 0, iclass 6, count 2 2006.257.17:06:31.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.17:06:31.60#ibcon#[25=AT04-07\r\n] 2006.257.17:06:31.60#ibcon#*before write, iclass 6, count 2 2006.257.17:06:31.60#ibcon#enter sib2, iclass 6, count 2 2006.257.17:06:31.60#ibcon#flushed, iclass 6, count 2 2006.257.17:06:31.60#ibcon#about to write, iclass 6, count 2 2006.257.17:06:31.60#ibcon#wrote, iclass 6, count 2 2006.257.17:06:31.60#ibcon#about to read 3, iclass 6, count 2 2006.257.17:06:31.63#ibcon#read 3, iclass 6, count 2 2006.257.17:06:31.63#ibcon#about to read 4, iclass 6, count 2 2006.257.17:06:31.63#ibcon#read 4, iclass 6, count 2 2006.257.17:06:31.63#ibcon#about to read 5, iclass 6, count 2 2006.257.17:06:31.63#ibcon#read 5, iclass 6, count 2 2006.257.17:06:31.63#ibcon#about to read 6, iclass 6, count 2 2006.257.17:06:31.63#ibcon#read 6, iclass 6, count 2 2006.257.17:06:31.63#ibcon#end of sib2, iclass 6, count 2 2006.257.17:06:31.63#ibcon#*after write, iclass 6, count 2 2006.257.17:06:31.63#ibcon#*before return 0, iclass 6, count 2 2006.257.17:06:31.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:31.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:31.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.17:06:31.63#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:31.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:31.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:31.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:31.75#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:06:31.75#ibcon#first serial, iclass 6, count 0 2006.257.17:06:31.75#ibcon#enter sib2, iclass 6, count 0 2006.257.17:06:31.75#ibcon#flushed, iclass 6, count 0 2006.257.17:06:31.75#ibcon#about to write, iclass 6, count 0 2006.257.17:06:31.75#ibcon#wrote, iclass 6, count 0 2006.257.17:06:31.75#ibcon#about to read 3, iclass 6, count 0 2006.257.17:06:31.77#ibcon#read 3, iclass 6, count 0 2006.257.17:06:31.77#ibcon#about to read 4, iclass 6, count 0 2006.257.17:06:31.77#ibcon#read 4, iclass 6, count 0 2006.257.17:06:31.77#ibcon#about to read 5, iclass 6, count 0 2006.257.17:06:31.77#ibcon#read 5, iclass 6, count 0 2006.257.17:06:31.77#ibcon#about to read 6, iclass 6, count 0 2006.257.17:06:31.77#ibcon#read 6, iclass 6, count 0 2006.257.17:06:31.77#ibcon#end of sib2, iclass 6, count 0 2006.257.17:06:31.77#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:06:31.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:06:31.77#ibcon#[25=USB\r\n] 2006.257.17:06:31.77#ibcon#*before write, iclass 6, count 0 2006.257.17:06:31.77#ibcon#enter sib2, iclass 6, count 0 2006.257.17:06:31.77#ibcon#flushed, iclass 6, count 0 2006.257.17:06:31.77#ibcon#about to write, iclass 6, count 0 2006.257.17:06:31.77#ibcon#wrote, iclass 6, count 0 2006.257.17:06:31.77#ibcon#about to read 3, iclass 6, count 0 2006.257.17:06:31.80#ibcon#read 3, iclass 6, count 0 2006.257.17:06:31.80#ibcon#about to read 4, iclass 6, count 0 2006.257.17:06:31.80#ibcon#read 4, iclass 6, count 0 2006.257.17:06:31.80#ibcon#about to read 5, iclass 6, count 0 2006.257.17:06:31.80#ibcon#read 5, iclass 6, count 0 2006.257.17:06:31.80#ibcon#about to read 6, iclass 6, count 0 2006.257.17:06:31.80#ibcon#read 6, iclass 6, count 0 2006.257.17:06:31.80#ibcon#end of sib2, iclass 6, count 0 2006.257.17:06:31.80#ibcon#*after write, iclass 6, count 0 2006.257.17:06:31.80#ibcon#*before return 0, iclass 6, count 0 2006.257.17:06:31.80#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:31.80#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:31.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:06:31.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:06:31.80$vck44/valo=5,734.99 2006.257.17:06:31.80#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.17:06:31.80#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.17:06:31.80#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:31.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:31.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:31.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:31.80#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:06:31.80#ibcon#first serial, iclass 10, count 0 2006.257.17:06:31.80#ibcon#enter sib2, iclass 10, count 0 2006.257.17:06:31.80#ibcon#flushed, iclass 10, count 0 2006.257.17:06:31.80#ibcon#about to write, iclass 10, count 0 2006.257.17:06:31.80#ibcon#wrote, iclass 10, count 0 2006.257.17:06:31.80#ibcon#about to read 3, iclass 10, count 0 2006.257.17:06:31.82#ibcon#read 3, iclass 10, count 0 2006.257.17:06:31.82#ibcon#about to read 4, iclass 10, count 0 2006.257.17:06:31.82#ibcon#read 4, iclass 10, count 0 2006.257.17:06:31.82#ibcon#about to read 5, iclass 10, count 0 2006.257.17:06:31.82#ibcon#read 5, iclass 10, count 0 2006.257.17:06:31.82#ibcon#about to read 6, iclass 10, count 0 2006.257.17:06:31.82#ibcon#read 6, iclass 10, count 0 2006.257.17:06:31.82#ibcon#end of sib2, iclass 10, count 0 2006.257.17:06:31.82#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:06:31.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:06:31.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:06:31.82#ibcon#*before write, iclass 10, count 0 2006.257.17:06:31.82#ibcon#enter sib2, iclass 10, count 0 2006.257.17:06:31.82#ibcon#flushed, iclass 10, count 0 2006.257.17:06:31.82#ibcon#about to write, iclass 10, count 0 2006.257.17:06:31.82#ibcon#wrote, iclass 10, count 0 2006.257.17:06:31.82#ibcon#about to read 3, iclass 10, count 0 2006.257.17:06:31.86#ibcon#read 3, iclass 10, count 0 2006.257.17:06:31.86#ibcon#about to read 4, iclass 10, count 0 2006.257.17:06:31.86#ibcon#read 4, iclass 10, count 0 2006.257.17:06:31.86#ibcon#about to read 5, iclass 10, count 0 2006.257.17:06:31.86#ibcon#read 5, iclass 10, count 0 2006.257.17:06:31.86#ibcon#about to read 6, iclass 10, count 0 2006.257.17:06:31.86#ibcon#read 6, iclass 10, count 0 2006.257.17:06:31.86#ibcon#end of sib2, iclass 10, count 0 2006.257.17:06:31.86#ibcon#*after write, iclass 10, count 0 2006.257.17:06:31.86#ibcon#*before return 0, iclass 10, count 0 2006.257.17:06:31.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:31.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:31.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:06:31.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:06:31.86$vck44/va=5,4 2006.257.17:06:31.86#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.17:06:31.86#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.17:06:31.86#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:31.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:31.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:31.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:31.92#ibcon#enter wrdev, iclass 12, count 2 2006.257.17:06:31.92#ibcon#first serial, iclass 12, count 2 2006.257.17:06:31.92#ibcon#enter sib2, iclass 12, count 2 2006.257.17:06:31.92#ibcon#flushed, iclass 12, count 2 2006.257.17:06:31.92#ibcon#about to write, iclass 12, count 2 2006.257.17:06:31.92#ibcon#wrote, iclass 12, count 2 2006.257.17:06:31.92#ibcon#about to read 3, iclass 12, count 2 2006.257.17:06:31.94#ibcon#read 3, iclass 12, count 2 2006.257.17:06:31.94#ibcon#about to read 4, iclass 12, count 2 2006.257.17:06:31.94#ibcon#read 4, iclass 12, count 2 2006.257.17:06:31.94#ibcon#about to read 5, iclass 12, count 2 2006.257.17:06:31.94#ibcon#read 5, iclass 12, count 2 2006.257.17:06:31.94#ibcon#about to read 6, iclass 12, count 2 2006.257.17:06:31.94#ibcon#read 6, iclass 12, count 2 2006.257.17:06:31.94#ibcon#end of sib2, iclass 12, count 2 2006.257.17:06:31.94#ibcon#*mode == 0, iclass 12, count 2 2006.257.17:06:31.94#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.17:06:31.94#ibcon#[25=AT05-04\r\n] 2006.257.17:06:31.94#ibcon#*before write, iclass 12, count 2 2006.257.17:06:31.94#ibcon#enter sib2, iclass 12, count 2 2006.257.17:06:31.94#ibcon#flushed, iclass 12, count 2 2006.257.17:06:31.94#ibcon#about to write, iclass 12, count 2 2006.257.17:06:31.94#ibcon#wrote, iclass 12, count 2 2006.257.17:06:31.94#ibcon#about to read 3, iclass 12, count 2 2006.257.17:06:31.97#ibcon#read 3, iclass 12, count 2 2006.257.17:06:31.97#ibcon#about to read 4, iclass 12, count 2 2006.257.17:06:31.97#ibcon#read 4, iclass 12, count 2 2006.257.17:06:31.97#ibcon#about to read 5, iclass 12, count 2 2006.257.17:06:31.97#ibcon#read 5, iclass 12, count 2 2006.257.17:06:31.97#ibcon#about to read 6, iclass 12, count 2 2006.257.17:06:31.97#ibcon#read 6, iclass 12, count 2 2006.257.17:06:31.97#ibcon#end of sib2, iclass 12, count 2 2006.257.17:06:31.97#ibcon#*after write, iclass 12, count 2 2006.257.17:06:31.97#ibcon#*before return 0, iclass 12, count 2 2006.257.17:06:31.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:31.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:31.97#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.17:06:31.97#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:31.97#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:32.09#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:32.09#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:32.09#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:06:32.09#ibcon#first serial, iclass 12, count 0 2006.257.17:06:32.09#ibcon#enter sib2, iclass 12, count 0 2006.257.17:06:32.09#ibcon#flushed, iclass 12, count 0 2006.257.17:06:32.09#ibcon#about to write, iclass 12, count 0 2006.257.17:06:32.09#ibcon#wrote, iclass 12, count 0 2006.257.17:06:32.09#ibcon#about to read 3, iclass 12, count 0 2006.257.17:06:32.11#ibcon#read 3, iclass 12, count 0 2006.257.17:06:32.11#ibcon#about to read 4, iclass 12, count 0 2006.257.17:06:32.11#ibcon#read 4, iclass 12, count 0 2006.257.17:06:32.11#ibcon#about to read 5, iclass 12, count 0 2006.257.17:06:32.11#ibcon#read 5, iclass 12, count 0 2006.257.17:06:32.11#ibcon#about to read 6, iclass 12, count 0 2006.257.17:06:32.11#ibcon#read 6, iclass 12, count 0 2006.257.17:06:32.11#ibcon#end of sib2, iclass 12, count 0 2006.257.17:06:32.11#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:06:32.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:06:32.11#ibcon#[25=USB\r\n] 2006.257.17:06:32.11#ibcon#*before write, iclass 12, count 0 2006.257.17:06:32.11#ibcon#enter sib2, iclass 12, count 0 2006.257.17:06:32.11#ibcon#flushed, iclass 12, count 0 2006.257.17:06:32.11#ibcon#about to write, iclass 12, count 0 2006.257.17:06:32.11#ibcon#wrote, iclass 12, count 0 2006.257.17:06:32.11#ibcon#about to read 3, iclass 12, count 0 2006.257.17:06:32.14#ibcon#read 3, iclass 12, count 0 2006.257.17:06:32.14#ibcon#about to read 4, iclass 12, count 0 2006.257.17:06:32.14#ibcon#read 4, iclass 12, count 0 2006.257.17:06:32.14#ibcon#about to read 5, iclass 12, count 0 2006.257.17:06:32.14#ibcon#read 5, iclass 12, count 0 2006.257.17:06:32.14#ibcon#about to read 6, iclass 12, count 0 2006.257.17:06:32.14#ibcon#read 6, iclass 12, count 0 2006.257.17:06:32.14#ibcon#end of sib2, iclass 12, count 0 2006.257.17:06:32.14#ibcon#*after write, iclass 12, count 0 2006.257.17:06:32.14#ibcon#*before return 0, iclass 12, count 0 2006.257.17:06:32.14#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:32.14#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:32.14#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:06:32.14#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:06:32.14$vck44/valo=6,814.99 2006.257.17:06:32.14#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.17:06:32.14#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.17:06:32.14#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:32.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:32.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:32.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:32.14#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:06:32.14#ibcon#first serial, iclass 14, count 0 2006.257.17:06:32.14#ibcon#enter sib2, iclass 14, count 0 2006.257.17:06:32.14#ibcon#flushed, iclass 14, count 0 2006.257.17:06:32.14#ibcon#about to write, iclass 14, count 0 2006.257.17:06:32.14#ibcon#wrote, iclass 14, count 0 2006.257.17:06:32.14#ibcon#about to read 3, iclass 14, count 0 2006.257.17:06:32.16#ibcon#read 3, iclass 14, count 0 2006.257.17:06:32.16#ibcon#about to read 4, iclass 14, count 0 2006.257.17:06:32.16#ibcon#read 4, iclass 14, count 0 2006.257.17:06:32.16#ibcon#about to read 5, iclass 14, count 0 2006.257.17:06:32.16#ibcon#read 5, iclass 14, count 0 2006.257.17:06:32.16#ibcon#about to read 6, iclass 14, count 0 2006.257.17:06:32.16#ibcon#read 6, iclass 14, count 0 2006.257.17:06:32.16#ibcon#end of sib2, iclass 14, count 0 2006.257.17:06:32.16#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:06:32.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:06:32.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:06:32.16#ibcon#*before write, iclass 14, count 0 2006.257.17:06:32.16#ibcon#enter sib2, iclass 14, count 0 2006.257.17:06:32.16#ibcon#flushed, iclass 14, count 0 2006.257.17:06:32.16#ibcon#about to write, iclass 14, count 0 2006.257.17:06:32.16#ibcon#wrote, iclass 14, count 0 2006.257.17:06:32.16#ibcon#about to read 3, iclass 14, count 0 2006.257.17:06:32.20#ibcon#read 3, iclass 14, count 0 2006.257.17:06:32.20#ibcon#about to read 4, iclass 14, count 0 2006.257.17:06:32.20#ibcon#read 4, iclass 14, count 0 2006.257.17:06:32.20#ibcon#about to read 5, iclass 14, count 0 2006.257.17:06:32.20#ibcon#read 5, iclass 14, count 0 2006.257.17:06:32.20#ibcon#about to read 6, iclass 14, count 0 2006.257.17:06:32.20#ibcon#read 6, iclass 14, count 0 2006.257.17:06:32.20#ibcon#end of sib2, iclass 14, count 0 2006.257.17:06:32.20#ibcon#*after write, iclass 14, count 0 2006.257.17:06:32.20#ibcon#*before return 0, iclass 14, count 0 2006.257.17:06:32.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:32.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:32.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:06:32.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:06:32.20$vck44/va=6,4 2006.257.17:06:32.20#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.17:06:32.20#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.17:06:32.20#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:32.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:32.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:32.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:32.26#ibcon#enter wrdev, iclass 16, count 2 2006.257.17:06:32.26#ibcon#first serial, iclass 16, count 2 2006.257.17:06:32.26#ibcon#enter sib2, iclass 16, count 2 2006.257.17:06:32.26#ibcon#flushed, iclass 16, count 2 2006.257.17:06:32.26#ibcon#about to write, iclass 16, count 2 2006.257.17:06:32.26#ibcon#wrote, iclass 16, count 2 2006.257.17:06:32.26#ibcon#about to read 3, iclass 16, count 2 2006.257.17:06:32.28#ibcon#read 3, iclass 16, count 2 2006.257.17:06:32.28#ibcon#about to read 4, iclass 16, count 2 2006.257.17:06:32.28#ibcon#read 4, iclass 16, count 2 2006.257.17:06:32.28#ibcon#about to read 5, iclass 16, count 2 2006.257.17:06:32.28#ibcon#read 5, iclass 16, count 2 2006.257.17:06:32.28#ibcon#about to read 6, iclass 16, count 2 2006.257.17:06:32.28#ibcon#read 6, iclass 16, count 2 2006.257.17:06:32.28#ibcon#end of sib2, iclass 16, count 2 2006.257.17:06:32.28#ibcon#*mode == 0, iclass 16, count 2 2006.257.17:06:32.28#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.17:06:32.28#ibcon#[25=AT06-04\r\n] 2006.257.17:06:32.28#ibcon#*before write, iclass 16, count 2 2006.257.17:06:32.28#ibcon#enter sib2, iclass 16, count 2 2006.257.17:06:32.28#ibcon#flushed, iclass 16, count 2 2006.257.17:06:32.28#ibcon#about to write, iclass 16, count 2 2006.257.17:06:32.28#ibcon#wrote, iclass 16, count 2 2006.257.17:06:32.28#ibcon#about to read 3, iclass 16, count 2 2006.257.17:06:32.31#ibcon#read 3, iclass 16, count 2 2006.257.17:06:32.31#ibcon#about to read 4, iclass 16, count 2 2006.257.17:06:32.31#ibcon#read 4, iclass 16, count 2 2006.257.17:06:32.31#ibcon#about to read 5, iclass 16, count 2 2006.257.17:06:32.31#ibcon#read 5, iclass 16, count 2 2006.257.17:06:32.31#ibcon#about to read 6, iclass 16, count 2 2006.257.17:06:32.31#ibcon#read 6, iclass 16, count 2 2006.257.17:06:32.31#ibcon#end of sib2, iclass 16, count 2 2006.257.17:06:32.31#ibcon#*after write, iclass 16, count 2 2006.257.17:06:32.31#ibcon#*before return 0, iclass 16, count 2 2006.257.17:06:32.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:32.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:32.31#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.17:06:32.31#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:32.31#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:32.43#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:32.43#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:32.43#ibcon#enter wrdev, iclass 16, count 0 2006.257.17:06:32.43#ibcon#first serial, iclass 16, count 0 2006.257.17:06:32.43#ibcon#enter sib2, iclass 16, count 0 2006.257.17:06:32.43#ibcon#flushed, iclass 16, count 0 2006.257.17:06:32.43#ibcon#about to write, iclass 16, count 0 2006.257.17:06:32.43#ibcon#wrote, iclass 16, count 0 2006.257.17:06:32.43#ibcon#about to read 3, iclass 16, count 0 2006.257.17:06:32.45#ibcon#read 3, iclass 16, count 0 2006.257.17:06:32.45#ibcon#about to read 4, iclass 16, count 0 2006.257.17:06:32.45#ibcon#read 4, iclass 16, count 0 2006.257.17:06:32.45#ibcon#about to read 5, iclass 16, count 0 2006.257.17:06:32.45#ibcon#read 5, iclass 16, count 0 2006.257.17:06:32.45#ibcon#about to read 6, iclass 16, count 0 2006.257.17:06:32.45#ibcon#read 6, iclass 16, count 0 2006.257.17:06:32.45#ibcon#end of sib2, iclass 16, count 0 2006.257.17:06:32.45#ibcon#*mode == 0, iclass 16, count 0 2006.257.17:06:32.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.17:06:32.45#ibcon#[25=USB\r\n] 2006.257.17:06:32.45#ibcon#*before write, iclass 16, count 0 2006.257.17:06:32.45#ibcon#enter sib2, iclass 16, count 0 2006.257.17:06:32.45#ibcon#flushed, iclass 16, count 0 2006.257.17:06:32.45#ibcon#about to write, iclass 16, count 0 2006.257.17:06:32.45#ibcon#wrote, iclass 16, count 0 2006.257.17:06:32.45#ibcon#about to read 3, iclass 16, count 0 2006.257.17:06:32.48#ibcon#read 3, iclass 16, count 0 2006.257.17:06:32.48#ibcon#about to read 4, iclass 16, count 0 2006.257.17:06:32.48#ibcon#read 4, iclass 16, count 0 2006.257.17:06:32.48#ibcon#about to read 5, iclass 16, count 0 2006.257.17:06:32.48#ibcon#read 5, iclass 16, count 0 2006.257.17:06:32.48#ibcon#about to read 6, iclass 16, count 0 2006.257.17:06:32.48#ibcon#read 6, iclass 16, count 0 2006.257.17:06:32.48#ibcon#end of sib2, iclass 16, count 0 2006.257.17:06:32.48#ibcon#*after write, iclass 16, count 0 2006.257.17:06:32.48#ibcon#*before return 0, iclass 16, count 0 2006.257.17:06:32.48#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:32.48#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:32.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.17:06:32.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.17:06:32.48$vck44/valo=7,864.99 2006.257.17:06:32.48#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.17:06:32.48#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.17:06:32.48#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:32.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:32.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:32.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:32.48#ibcon#enter wrdev, iclass 18, count 0 2006.257.17:06:32.48#ibcon#first serial, iclass 18, count 0 2006.257.17:06:32.48#ibcon#enter sib2, iclass 18, count 0 2006.257.17:06:32.48#ibcon#flushed, iclass 18, count 0 2006.257.17:06:32.48#ibcon#about to write, iclass 18, count 0 2006.257.17:06:32.48#ibcon#wrote, iclass 18, count 0 2006.257.17:06:32.48#ibcon#about to read 3, iclass 18, count 0 2006.257.17:06:32.50#ibcon#read 3, iclass 18, count 0 2006.257.17:06:32.50#ibcon#about to read 4, iclass 18, count 0 2006.257.17:06:32.50#ibcon#read 4, iclass 18, count 0 2006.257.17:06:32.50#ibcon#about to read 5, iclass 18, count 0 2006.257.17:06:32.50#ibcon#read 5, iclass 18, count 0 2006.257.17:06:32.50#ibcon#about to read 6, iclass 18, count 0 2006.257.17:06:32.50#ibcon#read 6, iclass 18, count 0 2006.257.17:06:32.50#ibcon#end of sib2, iclass 18, count 0 2006.257.17:06:32.50#ibcon#*mode == 0, iclass 18, count 0 2006.257.17:06:32.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.17:06:32.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:06:32.50#ibcon#*before write, iclass 18, count 0 2006.257.17:06:32.50#ibcon#enter sib2, iclass 18, count 0 2006.257.17:06:32.50#ibcon#flushed, iclass 18, count 0 2006.257.17:06:32.50#ibcon#about to write, iclass 18, count 0 2006.257.17:06:32.50#ibcon#wrote, iclass 18, count 0 2006.257.17:06:32.50#ibcon#about to read 3, iclass 18, count 0 2006.257.17:06:32.54#ibcon#read 3, iclass 18, count 0 2006.257.17:06:32.54#ibcon#about to read 4, iclass 18, count 0 2006.257.17:06:32.54#ibcon#read 4, iclass 18, count 0 2006.257.17:06:32.54#ibcon#about to read 5, iclass 18, count 0 2006.257.17:06:32.54#ibcon#read 5, iclass 18, count 0 2006.257.17:06:32.54#ibcon#about to read 6, iclass 18, count 0 2006.257.17:06:32.54#ibcon#read 6, iclass 18, count 0 2006.257.17:06:32.54#ibcon#end of sib2, iclass 18, count 0 2006.257.17:06:32.54#ibcon#*after write, iclass 18, count 0 2006.257.17:06:32.54#ibcon#*before return 0, iclass 18, count 0 2006.257.17:06:32.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:32.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:32.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.17:06:32.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.17:06:32.54$vck44/va=7,4 2006.257.17:06:32.54#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.17:06:32.54#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.17:06:32.54#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:32.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:32.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:32.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:32.60#ibcon#enter wrdev, iclass 20, count 2 2006.257.17:06:32.60#ibcon#first serial, iclass 20, count 2 2006.257.17:06:32.60#ibcon#enter sib2, iclass 20, count 2 2006.257.17:06:32.60#ibcon#flushed, iclass 20, count 2 2006.257.17:06:32.60#ibcon#about to write, iclass 20, count 2 2006.257.17:06:32.60#ibcon#wrote, iclass 20, count 2 2006.257.17:06:32.60#ibcon#about to read 3, iclass 20, count 2 2006.257.17:06:32.62#ibcon#read 3, iclass 20, count 2 2006.257.17:06:32.62#ibcon#about to read 4, iclass 20, count 2 2006.257.17:06:32.62#ibcon#read 4, iclass 20, count 2 2006.257.17:06:32.62#ibcon#about to read 5, iclass 20, count 2 2006.257.17:06:32.62#ibcon#read 5, iclass 20, count 2 2006.257.17:06:32.62#ibcon#about to read 6, iclass 20, count 2 2006.257.17:06:32.62#ibcon#read 6, iclass 20, count 2 2006.257.17:06:32.62#ibcon#end of sib2, iclass 20, count 2 2006.257.17:06:32.62#ibcon#*mode == 0, iclass 20, count 2 2006.257.17:06:32.62#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.17:06:32.62#ibcon#[25=AT07-04\r\n] 2006.257.17:06:32.62#ibcon#*before write, iclass 20, count 2 2006.257.17:06:32.62#ibcon#enter sib2, iclass 20, count 2 2006.257.17:06:32.62#ibcon#flushed, iclass 20, count 2 2006.257.17:06:32.62#ibcon#about to write, iclass 20, count 2 2006.257.17:06:32.62#ibcon#wrote, iclass 20, count 2 2006.257.17:06:32.62#ibcon#about to read 3, iclass 20, count 2 2006.257.17:06:32.65#ibcon#read 3, iclass 20, count 2 2006.257.17:06:32.65#ibcon#about to read 4, iclass 20, count 2 2006.257.17:06:32.65#ibcon#read 4, iclass 20, count 2 2006.257.17:06:32.65#ibcon#about to read 5, iclass 20, count 2 2006.257.17:06:32.65#ibcon#read 5, iclass 20, count 2 2006.257.17:06:32.65#ibcon#about to read 6, iclass 20, count 2 2006.257.17:06:32.65#ibcon#read 6, iclass 20, count 2 2006.257.17:06:32.65#ibcon#end of sib2, iclass 20, count 2 2006.257.17:06:32.65#ibcon#*after write, iclass 20, count 2 2006.257.17:06:32.65#ibcon#*before return 0, iclass 20, count 2 2006.257.17:06:32.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:32.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:32.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.17:06:32.65#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:32.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:32.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:32.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:32.77#ibcon#enter wrdev, iclass 20, count 0 2006.257.17:06:32.77#ibcon#first serial, iclass 20, count 0 2006.257.17:06:32.77#ibcon#enter sib2, iclass 20, count 0 2006.257.17:06:32.77#ibcon#flushed, iclass 20, count 0 2006.257.17:06:32.77#ibcon#about to write, iclass 20, count 0 2006.257.17:06:32.77#ibcon#wrote, iclass 20, count 0 2006.257.17:06:32.77#ibcon#about to read 3, iclass 20, count 0 2006.257.17:06:32.79#ibcon#read 3, iclass 20, count 0 2006.257.17:06:32.79#ibcon#about to read 4, iclass 20, count 0 2006.257.17:06:32.79#ibcon#read 4, iclass 20, count 0 2006.257.17:06:32.79#ibcon#about to read 5, iclass 20, count 0 2006.257.17:06:32.79#ibcon#read 5, iclass 20, count 0 2006.257.17:06:32.79#ibcon#about to read 6, iclass 20, count 0 2006.257.17:06:32.79#ibcon#read 6, iclass 20, count 0 2006.257.17:06:32.79#ibcon#end of sib2, iclass 20, count 0 2006.257.17:06:32.79#ibcon#*mode == 0, iclass 20, count 0 2006.257.17:06:32.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.17:06:32.79#ibcon#[25=USB\r\n] 2006.257.17:06:32.79#ibcon#*before write, iclass 20, count 0 2006.257.17:06:32.79#ibcon#enter sib2, iclass 20, count 0 2006.257.17:06:32.79#ibcon#flushed, iclass 20, count 0 2006.257.17:06:32.79#ibcon#about to write, iclass 20, count 0 2006.257.17:06:32.79#ibcon#wrote, iclass 20, count 0 2006.257.17:06:32.79#ibcon#about to read 3, iclass 20, count 0 2006.257.17:06:32.82#ibcon#read 3, iclass 20, count 0 2006.257.17:06:32.82#ibcon#about to read 4, iclass 20, count 0 2006.257.17:06:32.82#ibcon#read 4, iclass 20, count 0 2006.257.17:06:32.82#ibcon#about to read 5, iclass 20, count 0 2006.257.17:06:32.82#ibcon#read 5, iclass 20, count 0 2006.257.17:06:32.82#ibcon#about to read 6, iclass 20, count 0 2006.257.17:06:32.82#ibcon#read 6, iclass 20, count 0 2006.257.17:06:32.82#ibcon#end of sib2, iclass 20, count 0 2006.257.17:06:32.82#ibcon#*after write, iclass 20, count 0 2006.257.17:06:32.82#ibcon#*before return 0, iclass 20, count 0 2006.257.17:06:32.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:32.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:32.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.17:06:32.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.17:06:32.82$vck44/valo=8,884.99 2006.257.17:06:32.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.17:06:32.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.17:06:32.82#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:32.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:32.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:32.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:32.82#ibcon#enter wrdev, iclass 22, count 0 2006.257.17:06:32.82#ibcon#first serial, iclass 22, count 0 2006.257.17:06:32.82#ibcon#enter sib2, iclass 22, count 0 2006.257.17:06:32.82#ibcon#flushed, iclass 22, count 0 2006.257.17:06:32.82#ibcon#about to write, iclass 22, count 0 2006.257.17:06:32.82#ibcon#wrote, iclass 22, count 0 2006.257.17:06:32.82#ibcon#about to read 3, iclass 22, count 0 2006.257.17:06:32.84#ibcon#read 3, iclass 22, count 0 2006.257.17:06:32.84#ibcon#about to read 4, iclass 22, count 0 2006.257.17:06:32.84#ibcon#read 4, iclass 22, count 0 2006.257.17:06:32.84#ibcon#about to read 5, iclass 22, count 0 2006.257.17:06:32.84#ibcon#read 5, iclass 22, count 0 2006.257.17:06:32.84#ibcon#about to read 6, iclass 22, count 0 2006.257.17:06:32.84#ibcon#read 6, iclass 22, count 0 2006.257.17:06:32.84#ibcon#end of sib2, iclass 22, count 0 2006.257.17:06:32.84#ibcon#*mode == 0, iclass 22, count 0 2006.257.17:06:32.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.17:06:32.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:06:32.84#ibcon#*before write, iclass 22, count 0 2006.257.17:06:32.84#ibcon#enter sib2, iclass 22, count 0 2006.257.17:06:32.84#ibcon#flushed, iclass 22, count 0 2006.257.17:06:32.84#ibcon#about to write, iclass 22, count 0 2006.257.17:06:32.84#ibcon#wrote, iclass 22, count 0 2006.257.17:06:32.84#ibcon#about to read 3, iclass 22, count 0 2006.257.17:06:32.88#ibcon#read 3, iclass 22, count 0 2006.257.17:06:32.88#ibcon#about to read 4, iclass 22, count 0 2006.257.17:06:32.88#ibcon#read 4, iclass 22, count 0 2006.257.17:06:32.88#ibcon#about to read 5, iclass 22, count 0 2006.257.17:06:32.88#ibcon#read 5, iclass 22, count 0 2006.257.17:06:32.88#ibcon#about to read 6, iclass 22, count 0 2006.257.17:06:32.88#ibcon#read 6, iclass 22, count 0 2006.257.17:06:32.88#ibcon#end of sib2, iclass 22, count 0 2006.257.17:06:32.88#ibcon#*after write, iclass 22, count 0 2006.257.17:06:32.88#ibcon#*before return 0, iclass 22, count 0 2006.257.17:06:32.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:32.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:32.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.17:06:32.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.17:06:32.88$vck44/va=8,4 2006.257.17:06:32.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.17:06:32.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.17:06:32.88#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:32.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:06:32.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:06:32.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:06:32.94#ibcon#enter wrdev, iclass 24, count 2 2006.257.17:06:32.94#ibcon#first serial, iclass 24, count 2 2006.257.17:06:32.94#ibcon#enter sib2, iclass 24, count 2 2006.257.17:06:32.94#ibcon#flushed, iclass 24, count 2 2006.257.17:06:32.94#ibcon#about to write, iclass 24, count 2 2006.257.17:06:32.94#ibcon#wrote, iclass 24, count 2 2006.257.17:06:32.94#ibcon#about to read 3, iclass 24, count 2 2006.257.17:06:32.96#ibcon#read 3, iclass 24, count 2 2006.257.17:06:32.96#ibcon#about to read 4, iclass 24, count 2 2006.257.17:06:32.96#ibcon#read 4, iclass 24, count 2 2006.257.17:06:32.96#ibcon#about to read 5, iclass 24, count 2 2006.257.17:06:32.96#ibcon#read 5, iclass 24, count 2 2006.257.17:06:32.96#ibcon#about to read 6, iclass 24, count 2 2006.257.17:06:32.96#ibcon#read 6, iclass 24, count 2 2006.257.17:06:32.96#ibcon#end of sib2, iclass 24, count 2 2006.257.17:06:32.96#ibcon#*mode == 0, iclass 24, count 2 2006.257.17:06:32.96#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.17:06:32.96#ibcon#[25=AT08-04\r\n] 2006.257.17:06:32.96#ibcon#*before write, iclass 24, count 2 2006.257.17:06:32.96#ibcon#enter sib2, iclass 24, count 2 2006.257.17:06:32.96#ibcon#flushed, iclass 24, count 2 2006.257.17:06:32.96#ibcon#about to write, iclass 24, count 2 2006.257.17:06:32.96#ibcon#wrote, iclass 24, count 2 2006.257.17:06:32.96#ibcon#about to read 3, iclass 24, count 2 2006.257.17:06:32.99#ibcon#read 3, iclass 24, count 2 2006.257.17:06:32.99#ibcon#about to read 4, iclass 24, count 2 2006.257.17:06:32.99#ibcon#read 4, iclass 24, count 2 2006.257.17:06:32.99#ibcon#about to read 5, iclass 24, count 2 2006.257.17:06:32.99#ibcon#read 5, iclass 24, count 2 2006.257.17:06:32.99#ibcon#about to read 6, iclass 24, count 2 2006.257.17:06:32.99#ibcon#read 6, iclass 24, count 2 2006.257.17:06:32.99#ibcon#end of sib2, iclass 24, count 2 2006.257.17:06:32.99#ibcon#*after write, iclass 24, count 2 2006.257.17:06:32.99#ibcon#*before return 0, iclass 24, count 2 2006.257.17:06:32.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:06:32.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:06:32.99#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.17:06:32.99#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:32.99#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:06:33.11#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:06:33.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:06:33.11#ibcon#enter wrdev, iclass 24, count 0 2006.257.17:06:33.11#ibcon#first serial, iclass 24, count 0 2006.257.17:06:33.11#ibcon#enter sib2, iclass 24, count 0 2006.257.17:06:33.11#ibcon#flushed, iclass 24, count 0 2006.257.17:06:33.11#ibcon#about to write, iclass 24, count 0 2006.257.17:06:33.11#ibcon#wrote, iclass 24, count 0 2006.257.17:06:33.11#ibcon#about to read 3, iclass 24, count 0 2006.257.17:06:33.13#ibcon#read 3, iclass 24, count 0 2006.257.17:06:33.13#ibcon#about to read 4, iclass 24, count 0 2006.257.17:06:33.13#ibcon#read 4, iclass 24, count 0 2006.257.17:06:33.13#ibcon#about to read 5, iclass 24, count 0 2006.257.17:06:33.13#ibcon#read 5, iclass 24, count 0 2006.257.17:06:33.13#ibcon#about to read 6, iclass 24, count 0 2006.257.17:06:33.13#ibcon#read 6, iclass 24, count 0 2006.257.17:06:33.13#ibcon#end of sib2, iclass 24, count 0 2006.257.17:06:33.13#ibcon#*mode == 0, iclass 24, count 0 2006.257.17:06:33.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.17:06:33.13#ibcon#[25=USB\r\n] 2006.257.17:06:33.13#ibcon#*before write, iclass 24, count 0 2006.257.17:06:33.13#ibcon#enter sib2, iclass 24, count 0 2006.257.17:06:33.13#ibcon#flushed, iclass 24, count 0 2006.257.17:06:33.13#ibcon#about to write, iclass 24, count 0 2006.257.17:06:33.13#ibcon#wrote, iclass 24, count 0 2006.257.17:06:33.13#ibcon#about to read 3, iclass 24, count 0 2006.257.17:06:33.16#ibcon#read 3, iclass 24, count 0 2006.257.17:06:33.16#ibcon#about to read 4, iclass 24, count 0 2006.257.17:06:33.16#ibcon#read 4, iclass 24, count 0 2006.257.17:06:33.16#ibcon#about to read 5, iclass 24, count 0 2006.257.17:06:33.16#ibcon#read 5, iclass 24, count 0 2006.257.17:06:33.16#ibcon#about to read 6, iclass 24, count 0 2006.257.17:06:33.16#ibcon#read 6, iclass 24, count 0 2006.257.17:06:33.16#ibcon#end of sib2, iclass 24, count 0 2006.257.17:06:33.16#ibcon#*after write, iclass 24, count 0 2006.257.17:06:33.16#ibcon#*before return 0, iclass 24, count 0 2006.257.17:06:33.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:06:33.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:06:33.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.17:06:33.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.17:06:33.16$vck44/vblo=1,629.99 2006.257.17:06:33.16#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.17:06:33.16#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.17:06:33.16#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:33.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:06:33.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:06:33.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:06:33.16#ibcon#enter wrdev, iclass 26, count 0 2006.257.17:06:33.16#ibcon#first serial, iclass 26, count 0 2006.257.17:06:33.16#ibcon#enter sib2, iclass 26, count 0 2006.257.17:06:33.16#ibcon#flushed, iclass 26, count 0 2006.257.17:06:33.16#ibcon#about to write, iclass 26, count 0 2006.257.17:06:33.16#ibcon#wrote, iclass 26, count 0 2006.257.17:06:33.16#ibcon#about to read 3, iclass 26, count 0 2006.257.17:06:33.18#ibcon#read 3, iclass 26, count 0 2006.257.17:06:33.18#ibcon#about to read 4, iclass 26, count 0 2006.257.17:06:33.18#ibcon#read 4, iclass 26, count 0 2006.257.17:06:33.18#ibcon#about to read 5, iclass 26, count 0 2006.257.17:06:33.18#ibcon#read 5, iclass 26, count 0 2006.257.17:06:33.18#ibcon#about to read 6, iclass 26, count 0 2006.257.17:06:33.18#ibcon#read 6, iclass 26, count 0 2006.257.17:06:33.18#ibcon#end of sib2, iclass 26, count 0 2006.257.17:06:33.18#ibcon#*mode == 0, iclass 26, count 0 2006.257.17:06:33.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.17:06:33.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:06:33.18#ibcon#*before write, iclass 26, count 0 2006.257.17:06:33.18#ibcon#enter sib2, iclass 26, count 0 2006.257.17:06:33.18#ibcon#flushed, iclass 26, count 0 2006.257.17:06:33.18#ibcon#about to write, iclass 26, count 0 2006.257.17:06:33.18#ibcon#wrote, iclass 26, count 0 2006.257.17:06:33.18#ibcon#about to read 3, iclass 26, count 0 2006.257.17:06:33.22#ibcon#read 3, iclass 26, count 0 2006.257.17:06:33.22#ibcon#about to read 4, iclass 26, count 0 2006.257.17:06:33.22#ibcon#read 4, iclass 26, count 0 2006.257.17:06:33.22#ibcon#about to read 5, iclass 26, count 0 2006.257.17:06:33.22#ibcon#read 5, iclass 26, count 0 2006.257.17:06:33.22#ibcon#about to read 6, iclass 26, count 0 2006.257.17:06:33.22#ibcon#read 6, iclass 26, count 0 2006.257.17:06:33.22#ibcon#end of sib2, iclass 26, count 0 2006.257.17:06:33.22#ibcon#*after write, iclass 26, count 0 2006.257.17:06:33.22#ibcon#*before return 0, iclass 26, count 0 2006.257.17:06:33.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:06:33.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:06:33.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.17:06:33.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.17:06:33.22$vck44/vb=1,4 2006.257.17:06:33.22#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.17:06:33.22#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.17:06:33.22#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:33.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:06:33.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:06:33.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:06:33.22#ibcon#enter wrdev, iclass 28, count 2 2006.257.17:06:33.22#ibcon#first serial, iclass 28, count 2 2006.257.17:06:33.22#ibcon#enter sib2, iclass 28, count 2 2006.257.17:06:33.22#ibcon#flushed, iclass 28, count 2 2006.257.17:06:33.22#ibcon#about to write, iclass 28, count 2 2006.257.17:06:33.22#ibcon#wrote, iclass 28, count 2 2006.257.17:06:33.22#ibcon#about to read 3, iclass 28, count 2 2006.257.17:06:33.24#ibcon#read 3, iclass 28, count 2 2006.257.17:06:33.24#ibcon#about to read 4, iclass 28, count 2 2006.257.17:06:33.24#ibcon#read 4, iclass 28, count 2 2006.257.17:06:33.24#ibcon#about to read 5, iclass 28, count 2 2006.257.17:06:33.24#ibcon#read 5, iclass 28, count 2 2006.257.17:06:33.24#ibcon#about to read 6, iclass 28, count 2 2006.257.17:06:33.24#ibcon#read 6, iclass 28, count 2 2006.257.17:06:33.24#ibcon#end of sib2, iclass 28, count 2 2006.257.17:06:33.24#ibcon#*mode == 0, iclass 28, count 2 2006.257.17:06:33.24#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.17:06:33.24#ibcon#[27=AT01-04\r\n] 2006.257.17:06:33.24#ibcon#*before write, iclass 28, count 2 2006.257.17:06:33.24#ibcon#enter sib2, iclass 28, count 2 2006.257.17:06:33.24#ibcon#flushed, iclass 28, count 2 2006.257.17:06:33.24#ibcon#about to write, iclass 28, count 2 2006.257.17:06:33.24#ibcon#wrote, iclass 28, count 2 2006.257.17:06:33.24#ibcon#about to read 3, iclass 28, count 2 2006.257.17:06:33.27#ibcon#read 3, iclass 28, count 2 2006.257.17:06:33.27#ibcon#about to read 4, iclass 28, count 2 2006.257.17:06:33.27#ibcon#read 4, iclass 28, count 2 2006.257.17:06:33.27#ibcon#about to read 5, iclass 28, count 2 2006.257.17:06:33.27#ibcon#read 5, iclass 28, count 2 2006.257.17:06:33.27#ibcon#about to read 6, iclass 28, count 2 2006.257.17:06:33.27#ibcon#read 6, iclass 28, count 2 2006.257.17:06:33.27#ibcon#end of sib2, iclass 28, count 2 2006.257.17:06:33.27#ibcon#*after write, iclass 28, count 2 2006.257.17:06:33.27#ibcon#*before return 0, iclass 28, count 2 2006.257.17:06:33.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:06:33.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:06:33.27#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.17:06:33.27#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:33.27#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:06:33.39#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:06:33.39#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:06:33.39#ibcon#enter wrdev, iclass 28, count 0 2006.257.17:06:33.39#ibcon#first serial, iclass 28, count 0 2006.257.17:06:33.39#ibcon#enter sib2, iclass 28, count 0 2006.257.17:06:33.39#ibcon#flushed, iclass 28, count 0 2006.257.17:06:33.39#ibcon#about to write, iclass 28, count 0 2006.257.17:06:33.39#ibcon#wrote, iclass 28, count 0 2006.257.17:06:33.39#ibcon#about to read 3, iclass 28, count 0 2006.257.17:06:33.41#ibcon#read 3, iclass 28, count 0 2006.257.17:06:33.41#ibcon#about to read 4, iclass 28, count 0 2006.257.17:06:33.41#ibcon#read 4, iclass 28, count 0 2006.257.17:06:33.41#ibcon#about to read 5, iclass 28, count 0 2006.257.17:06:33.41#ibcon#read 5, iclass 28, count 0 2006.257.17:06:33.41#ibcon#about to read 6, iclass 28, count 0 2006.257.17:06:33.41#ibcon#read 6, iclass 28, count 0 2006.257.17:06:33.41#ibcon#end of sib2, iclass 28, count 0 2006.257.17:06:33.41#ibcon#*mode == 0, iclass 28, count 0 2006.257.17:06:33.41#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.17:06:33.41#ibcon#[27=USB\r\n] 2006.257.17:06:33.41#ibcon#*before write, iclass 28, count 0 2006.257.17:06:33.41#ibcon#enter sib2, iclass 28, count 0 2006.257.17:06:33.41#ibcon#flushed, iclass 28, count 0 2006.257.17:06:33.41#ibcon#about to write, iclass 28, count 0 2006.257.17:06:33.41#ibcon#wrote, iclass 28, count 0 2006.257.17:06:33.41#ibcon#about to read 3, iclass 28, count 0 2006.257.17:06:33.44#ibcon#read 3, iclass 28, count 0 2006.257.17:06:33.44#ibcon#about to read 4, iclass 28, count 0 2006.257.17:06:33.44#ibcon#read 4, iclass 28, count 0 2006.257.17:06:33.44#ibcon#about to read 5, iclass 28, count 0 2006.257.17:06:33.44#ibcon#read 5, iclass 28, count 0 2006.257.17:06:33.44#ibcon#about to read 6, iclass 28, count 0 2006.257.17:06:33.44#ibcon#read 6, iclass 28, count 0 2006.257.17:06:33.44#ibcon#end of sib2, iclass 28, count 0 2006.257.17:06:33.44#ibcon#*after write, iclass 28, count 0 2006.257.17:06:33.44#ibcon#*before return 0, iclass 28, count 0 2006.257.17:06:33.44#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:06:33.44#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:06:33.44#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.17:06:33.44#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.17:06:33.44$vck44/vblo=2,634.99 2006.257.17:06:33.44#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.17:06:33.44#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.17:06:33.44#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:33.44#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:33.44#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:33.44#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:33.44#ibcon#enter wrdev, iclass 30, count 0 2006.257.17:06:33.44#ibcon#first serial, iclass 30, count 0 2006.257.17:06:33.44#ibcon#enter sib2, iclass 30, count 0 2006.257.17:06:33.44#ibcon#flushed, iclass 30, count 0 2006.257.17:06:33.44#ibcon#about to write, iclass 30, count 0 2006.257.17:06:33.44#ibcon#wrote, iclass 30, count 0 2006.257.17:06:33.44#ibcon#about to read 3, iclass 30, count 0 2006.257.17:06:33.46#ibcon#read 3, iclass 30, count 0 2006.257.17:06:33.46#ibcon#about to read 4, iclass 30, count 0 2006.257.17:06:33.46#ibcon#read 4, iclass 30, count 0 2006.257.17:06:33.46#ibcon#about to read 5, iclass 30, count 0 2006.257.17:06:33.46#ibcon#read 5, iclass 30, count 0 2006.257.17:06:33.46#ibcon#about to read 6, iclass 30, count 0 2006.257.17:06:33.46#ibcon#read 6, iclass 30, count 0 2006.257.17:06:33.46#ibcon#end of sib2, iclass 30, count 0 2006.257.17:06:33.46#ibcon#*mode == 0, iclass 30, count 0 2006.257.17:06:33.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.17:06:33.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:06:33.46#ibcon#*before write, iclass 30, count 0 2006.257.17:06:33.46#ibcon#enter sib2, iclass 30, count 0 2006.257.17:06:33.46#ibcon#flushed, iclass 30, count 0 2006.257.17:06:33.46#ibcon#about to write, iclass 30, count 0 2006.257.17:06:33.46#ibcon#wrote, iclass 30, count 0 2006.257.17:06:33.46#ibcon#about to read 3, iclass 30, count 0 2006.257.17:06:33.50#ibcon#read 3, iclass 30, count 0 2006.257.17:06:33.50#ibcon#about to read 4, iclass 30, count 0 2006.257.17:06:33.50#ibcon#read 4, iclass 30, count 0 2006.257.17:06:33.50#ibcon#about to read 5, iclass 30, count 0 2006.257.17:06:33.50#ibcon#read 5, iclass 30, count 0 2006.257.17:06:33.50#ibcon#about to read 6, iclass 30, count 0 2006.257.17:06:33.50#ibcon#read 6, iclass 30, count 0 2006.257.17:06:33.50#ibcon#end of sib2, iclass 30, count 0 2006.257.17:06:33.50#ibcon#*after write, iclass 30, count 0 2006.257.17:06:33.50#ibcon#*before return 0, iclass 30, count 0 2006.257.17:06:33.50#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:33.50#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:06:33.50#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.17:06:33.50#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.17:06:33.50$vck44/vb=2,5 2006.257.17:06:33.50#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.17:06:33.50#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.17:06:33.50#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:33.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:33.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:33.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:33.56#ibcon#enter wrdev, iclass 32, count 2 2006.257.17:06:33.56#ibcon#first serial, iclass 32, count 2 2006.257.17:06:33.56#ibcon#enter sib2, iclass 32, count 2 2006.257.17:06:33.56#ibcon#flushed, iclass 32, count 2 2006.257.17:06:33.56#ibcon#about to write, iclass 32, count 2 2006.257.17:06:33.56#ibcon#wrote, iclass 32, count 2 2006.257.17:06:33.56#ibcon#about to read 3, iclass 32, count 2 2006.257.17:06:33.58#ibcon#read 3, iclass 32, count 2 2006.257.17:06:33.58#ibcon#about to read 4, iclass 32, count 2 2006.257.17:06:33.58#ibcon#read 4, iclass 32, count 2 2006.257.17:06:33.58#ibcon#about to read 5, iclass 32, count 2 2006.257.17:06:33.58#ibcon#read 5, iclass 32, count 2 2006.257.17:06:33.58#ibcon#about to read 6, iclass 32, count 2 2006.257.17:06:33.58#ibcon#read 6, iclass 32, count 2 2006.257.17:06:33.58#ibcon#end of sib2, iclass 32, count 2 2006.257.17:06:33.58#ibcon#*mode == 0, iclass 32, count 2 2006.257.17:06:33.58#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.17:06:33.58#ibcon#[27=AT02-05\r\n] 2006.257.17:06:33.58#ibcon#*before write, iclass 32, count 2 2006.257.17:06:33.58#ibcon#enter sib2, iclass 32, count 2 2006.257.17:06:33.58#ibcon#flushed, iclass 32, count 2 2006.257.17:06:33.58#ibcon#about to write, iclass 32, count 2 2006.257.17:06:33.58#ibcon#wrote, iclass 32, count 2 2006.257.17:06:33.58#ibcon#about to read 3, iclass 32, count 2 2006.257.17:06:33.61#ibcon#read 3, iclass 32, count 2 2006.257.17:06:33.61#ibcon#about to read 4, iclass 32, count 2 2006.257.17:06:33.61#ibcon#read 4, iclass 32, count 2 2006.257.17:06:33.61#ibcon#about to read 5, iclass 32, count 2 2006.257.17:06:33.61#ibcon#read 5, iclass 32, count 2 2006.257.17:06:33.61#ibcon#about to read 6, iclass 32, count 2 2006.257.17:06:33.61#ibcon#read 6, iclass 32, count 2 2006.257.17:06:33.61#ibcon#end of sib2, iclass 32, count 2 2006.257.17:06:33.61#ibcon#*after write, iclass 32, count 2 2006.257.17:06:33.61#ibcon#*before return 0, iclass 32, count 2 2006.257.17:06:33.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:33.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:06:33.61#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.17:06:33.61#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:33.61#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:33.73#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:33.73#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:33.73#ibcon#enter wrdev, iclass 32, count 0 2006.257.17:06:33.73#ibcon#first serial, iclass 32, count 0 2006.257.17:06:33.73#ibcon#enter sib2, iclass 32, count 0 2006.257.17:06:33.73#ibcon#flushed, iclass 32, count 0 2006.257.17:06:33.73#ibcon#about to write, iclass 32, count 0 2006.257.17:06:33.73#ibcon#wrote, iclass 32, count 0 2006.257.17:06:33.73#ibcon#about to read 3, iclass 32, count 0 2006.257.17:06:33.75#ibcon#read 3, iclass 32, count 0 2006.257.17:06:33.75#ibcon#about to read 4, iclass 32, count 0 2006.257.17:06:33.75#ibcon#read 4, iclass 32, count 0 2006.257.17:06:33.75#ibcon#about to read 5, iclass 32, count 0 2006.257.17:06:33.75#ibcon#read 5, iclass 32, count 0 2006.257.17:06:33.75#ibcon#about to read 6, iclass 32, count 0 2006.257.17:06:33.75#ibcon#read 6, iclass 32, count 0 2006.257.17:06:33.75#ibcon#end of sib2, iclass 32, count 0 2006.257.17:06:33.75#ibcon#*mode == 0, iclass 32, count 0 2006.257.17:06:33.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.17:06:33.75#ibcon#[27=USB\r\n] 2006.257.17:06:33.75#ibcon#*before write, iclass 32, count 0 2006.257.17:06:33.75#ibcon#enter sib2, iclass 32, count 0 2006.257.17:06:33.75#ibcon#flushed, iclass 32, count 0 2006.257.17:06:33.75#ibcon#about to write, iclass 32, count 0 2006.257.17:06:33.75#ibcon#wrote, iclass 32, count 0 2006.257.17:06:33.75#ibcon#about to read 3, iclass 32, count 0 2006.257.17:06:33.78#ibcon#read 3, iclass 32, count 0 2006.257.17:06:33.78#ibcon#about to read 4, iclass 32, count 0 2006.257.17:06:33.78#ibcon#read 4, iclass 32, count 0 2006.257.17:06:33.78#ibcon#about to read 5, iclass 32, count 0 2006.257.17:06:33.78#ibcon#read 5, iclass 32, count 0 2006.257.17:06:33.78#ibcon#about to read 6, iclass 32, count 0 2006.257.17:06:33.78#ibcon#read 6, iclass 32, count 0 2006.257.17:06:33.78#ibcon#end of sib2, iclass 32, count 0 2006.257.17:06:33.78#ibcon#*after write, iclass 32, count 0 2006.257.17:06:33.78#ibcon#*before return 0, iclass 32, count 0 2006.257.17:06:33.78#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:33.78#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:06:33.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.17:06:33.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.17:06:33.78$vck44/vblo=3,649.99 2006.257.17:06:33.78#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.17:06:33.78#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.17:06:33.78#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:33.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:33.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:33.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:33.78#ibcon#enter wrdev, iclass 34, count 0 2006.257.17:06:33.78#ibcon#first serial, iclass 34, count 0 2006.257.17:06:33.78#ibcon#enter sib2, iclass 34, count 0 2006.257.17:06:33.78#ibcon#flushed, iclass 34, count 0 2006.257.17:06:33.78#ibcon#about to write, iclass 34, count 0 2006.257.17:06:33.78#ibcon#wrote, iclass 34, count 0 2006.257.17:06:33.78#ibcon#about to read 3, iclass 34, count 0 2006.257.17:06:33.80#ibcon#read 3, iclass 34, count 0 2006.257.17:06:33.80#ibcon#about to read 4, iclass 34, count 0 2006.257.17:06:33.80#ibcon#read 4, iclass 34, count 0 2006.257.17:06:33.80#ibcon#about to read 5, iclass 34, count 0 2006.257.17:06:33.80#ibcon#read 5, iclass 34, count 0 2006.257.17:06:33.80#ibcon#about to read 6, iclass 34, count 0 2006.257.17:06:33.80#ibcon#read 6, iclass 34, count 0 2006.257.17:06:33.80#ibcon#end of sib2, iclass 34, count 0 2006.257.17:06:33.80#ibcon#*mode == 0, iclass 34, count 0 2006.257.17:06:33.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.17:06:33.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:06:33.80#ibcon#*before write, iclass 34, count 0 2006.257.17:06:33.80#ibcon#enter sib2, iclass 34, count 0 2006.257.17:06:33.80#ibcon#flushed, iclass 34, count 0 2006.257.17:06:33.80#ibcon#about to write, iclass 34, count 0 2006.257.17:06:33.80#ibcon#wrote, iclass 34, count 0 2006.257.17:06:33.80#ibcon#about to read 3, iclass 34, count 0 2006.257.17:06:33.84#ibcon#read 3, iclass 34, count 0 2006.257.17:06:33.84#ibcon#about to read 4, iclass 34, count 0 2006.257.17:06:33.84#ibcon#read 4, iclass 34, count 0 2006.257.17:06:33.84#ibcon#about to read 5, iclass 34, count 0 2006.257.17:06:33.84#ibcon#read 5, iclass 34, count 0 2006.257.17:06:33.84#ibcon#about to read 6, iclass 34, count 0 2006.257.17:06:33.84#ibcon#read 6, iclass 34, count 0 2006.257.17:06:33.84#ibcon#end of sib2, iclass 34, count 0 2006.257.17:06:33.84#ibcon#*after write, iclass 34, count 0 2006.257.17:06:33.84#ibcon#*before return 0, iclass 34, count 0 2006.257.17:06:33.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:33.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:06:33.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.17:06:33.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.17:06:33.84$vck44/vb=3,4 2006.257.17:06:33.84#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.17:06:33.84#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.17:06:33.84#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:33.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:33.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:33.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:33.90#ibcon#enter wrdev, iclass 36, count 2 2006.257.17:06:33.90#ibcon#first serial, iclass 36, count 2 2006.257.17:06:33.90#ibcon#enter sib2, iclass 36, count 2 2006.257.17:06:33.90#ibcon#flushed, iclass 36, count 2 2006.257.17:06:33.90#ibcon#about to write, iclass 36, count 2 2006.257.17:06:33.90#ibcon#wrote, iclass 36, count 2 2006.257.17:06:33.90#ibcon#about to read 3, iclass 36, count 2 2006.257.17:06:33.92#ibcon#read 3, iclass 36, count 2 2006.257.17:06:33.92#ibcon#about to read 4, iclass 36, count 2 2006.257.17:06:33.92#ibcon#read 4, iclass 36, count 2 2006.257.17:06:33.92#ibcon#about to read 5, iclass 36, count 2 2006.257.17:06:33.92#ibcon#read 5, iclass 36, count 2 2006.257.17:06:33.92#ibcon#about to read 6, iclass 36, count 2 2006.257.17:06:33.92#ibcon#read 6, iclass 36, count 2 2006.257.17:06:33.92#ibcon#end of sib2, iclass 36, count 2 2006.257.17:06:33.92#ibcon#*mode == 0, iclass 36, count 2 2006.257.17:06:33.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.17:06:33.92#ibcon#[27=AT03-04\r\n] 2006.257.17:06:33.92#ibcon#*before write, iclass 36, count 2 2006.257.17:06:33.92#ibcon#enter sib2, iclass 36, count 2 2006.257.17:06:33.92#ibcon#flushed, iclass 36, count 2 2006.257.17:06:33.92#ibcon#about to write, iclass 36, count 2 2006.257.17:06:33.92#ibcon#wrote, iclass 36, count 2 2006.257.17:06:33.92#ibcon#about to read 3, iclass 36, count 2 2006.257.17:06:33.95#ibcon#read 3, iclass 36, count 2 2006.257.17:06:33.95#ibcon#about to read 4, iclass 36, count 2 2006.257.17:06:33.95#ibcon#read 4, iclass 36, count 2 2006.257.17:06:33.95#ibcon#about to read 5, iclass 36, count 2 2006.257.17:06:33.95#ibcon#read 5, iclass 36, count 2 2006.257.17:06:33.95#ibcon#about to read 6, iclass 36, count 2 2006.257.17:06:33.95#ibcon#read 6, iclass 36, count 2 2006.257.17:06:33.95#ibcon#end of sib2, iclass 36, count 2 2006.257.17:06:33.95#ibcon#*after write, iclass 36, count 2 2006.257.17:06:33.95#ibcon#*before return 0, iclass 36, count 2 2006.257.17:06:33.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:33.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:06:33.95#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.17:06:33.95#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:33.95#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:34.07#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:34.07#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:34.07#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:06:34.07#ibcon#first serial, iclass 36, count 0 2006.257.17:06:34.07#ibcon#enter sib2, iclass 36, count 0 2006.257.17:06:34.07#ibcon#flushed, iclass 36, count 0 2006.257.17:06:34.07#ibcon#about to write, iclass 36, count 0 2006.257.17:06:34.07#ibcon#wrote, iclass 36, count 0 2006.257.17:06:34.07#ibcon#about to read 3, iclass 36, count 0 2006.257.17:06:34.09#ibcon#read 3, iclass 36, count 0 2006.257.17:06:34.09#ibcon#about to read 4, iclass 36, count 0 2006.257.17:06:34.09#ibcon#read 4, iclass 36, count 0 2006.257.17:06:34.09#ibcon#about to read 5, iclass 36, count 0 2006.257.17:06:34.09#ibcon#read 5, iclass 36, count 0 2006.257.17:06:34.09#ibcon#about to read 6, iclass 36, count 0 2006.257.17:06:34.09#ibcon#read 6, iclass 36, count 0 2006.257.17:06:34.09#ibcon#end of sib2, iclass 36, count 0 2006.257.17:06:34.09#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:06:34.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:06:34.09#ibcon#[27=USB\r\n] 2006.257.17:06:34.09#ibcon#*before write, iclass 36, count 0 2006.257.17:06:34.09#ibcon#enter sib2, iclass 36, count 0 2006.257.17:06:34.09#ibcon#flushed, iclass 36, count 0 2006.257.17:06:34.09#ibcon#about to write, iclass 36, count 0 2006.257.17:06:34.09#ibcon#wrote, iclass 36, count 0 2006.257.17:06:34.09#ibcon#about to read 3, iclass 36, count 0 2006.257.17:06:34.12#ibcon#read 3, iclass 36, count 0 2006.257.17:06:34.12#ibcon#about to read 4, iclass 36, count 0 2006.257.17:06:34.12#ibcon#read 4, iclass 36, count 0 2006.257.17:06:34.12#ibcon#about to read 5, iclass 36, count 0 2006.257.17:06:34.12#ibcon#read 5, iclass 36, count 0 2006.257.17:06:34.12#ibcon#about to read 6, iclass 36, count 0 2006.257.17:06:34.12#ibcon#read 6, iclass 36, count 0 2006.257.17:06:34.12#ibcon#end of sib2, iclass 36, count 0 2006.257.17:06:34.12#ibcon#*after write, iclass 36, count 0 2006.257.17:06:34.12#ibcon#*before return 0, iclass 36, count 0 2006.257.17:06:34.12#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:34.12#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:06:34.12#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:06:34.12#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:06:34.12$vck44/vblo=4,679.99 2006.257.17:06:34.12#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.17:06:34.12#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.17:06:34.12#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:34.12#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:34.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:34.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:34.12#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:06:34.12#ibcon#first serial, iclass 38, count 0 2006.257.17:06:34.12#ibcon#enter sib2, iclass 38, count 0 2006.257.17:06:34.12#ibcon#flushed, iclass 38, count 0 2006.257.17:06:34.12#ibcon#about to write, iclass 38, count 0 2006.257.17:06:34.12#ibcon#wrote, iclass 38, count 0 2006.257.17:06:34.12#ibcon#about to read 3, iclass 38, count 0 2006.257.17:06:34.14#ibcon#read 3, iclass 38, count 0 2006.257.17:06:34.14#ibcon#about to read 4, iclass 38, count 0 2006.257.17:06:34.14#ibcon#read 4, iclass 38, count 0 2006.257.17:06:34.14#ibcon#about to read 5, iclass 38, count 0 2006.257.17:06:34.14#ibcon#read 5, iclass 38, count 0 2006.257.17:06:34.14#ibcon#about to read 6, iclass 38, count 0 2006.257.17:06:34.14#ibcon#read 6, iclass 38, count 0 2006.257.17:06:34.14#ibcon#end of sib2, iclass 38, count 0 2006.257.17:06:34.14#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:06:34.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:06:34.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:06:34.14#ibcon#*before write, iclass 38, count 0 2006.257.17:06:34.14#ibcon#enter sib2, iclass 38, count 0 2006.257.17:06:34.14#ibcon#flushed, iclass 38, count 0 2006.257.17:06:34.14#ibcon#about to write, iclass 38, count 0 2006.257.17:06:34.14#ibcon#wrote, iclass 38, count 0 2006.257.17:06:34.14#ibcon#about to read 3, iclass 38, count 0 2006.257.17:06:34.18#ibcon#read 3, iclass 38, count 0 2006.257.17:06:34.18#ibcon#about to read 4, iclass 38, count 0 2006.257.17:06:34.18#ibcon#read 4, iclass 38, count 0 2006.257.17:06:34.18#ibcon#about to read 5, iclass 38, count 0 2006.257.17:06:34.18#ibcon#read 5, iclass 38, count 0 2006.257.17:06:34.18#ibcon#about to read 6, iclass 38, count 0 2006.257.17:06:34.18#ibcon#read 6, iclass 38, count 0 2006.257.17:06:34.18#ibcon#end of sib2, iclass 38, count 0 2006.257.17:06:34.18#ibcon#*after write, iclass 38, count 0 2006.257.17:06:34.18#ibcon#*before return 0, iclass 38, count 0 2006.257.17:06:34.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:34.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:06:34.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:06:34.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:06:34.18$vck44/vb=4,5 2006.257.17:06:34.18#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.17:06:34.18#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.17:06:34.18#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:34.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:34.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:34.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:34.24#ibcon#enter wrdev, iclass 40, count 2 2006.257.17:06:34.24#ibcon#first serial, iclass 40, count 2 2006.257.17:06:34.24#ibcon#enter sib2, iclass 40, count 2 2006.257.17:06:34.24#ibcon#flushed, iclass 40, count 2 2006.257.17:06:34.24#ibcon#about to write, iclass 40, count 2 2006.257.17:06:34.24#ibcon#wrote, iclass 40, count 2 2006.257.17:06:34.24#ibcon#about to read 3, iclass 40, count 2 2006.257.17:06:34.26#ibcon#read 3, iclass 40, count 2 2006.257.17:06:34.26#ibcon#about to read 4, iclass 40, count 2 2006.257.17:06:34.26#ibcon#read 4, iclass 40, count 2 2006.257.17:06:34.26#ibcon#about to read 5, iclass 40, count 2 2006.257.17:06:34.26#ibcon#read 5, iclass 40, count 2 2006.257.17:06:34.26#ibcon#about to read 6, iclass 40, count 2 2006.257.17:06:34.26#ibcon#read 6, iclass 40, count 2 2006.257.17:06:34.26#ibcon#end of sib2, iclass 40, count 2 2006.257.17:06:34.26#ibcon#*mode == 0, iclass 40, count 2 2006.257.17:06:34.26#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.17:06:34.26#ibcon#[27=AT04-05\r\n] 2006.257.17:06:34.26#ibcon#*before write, iclass 40, count 2 2006.257.17:06:34.26#ibcon#enter sib2, iclass 40, count 2 2006.257.17:06:34.26#ibcon#flushed, iclass 40, count 2 2006.257.17:06:34.26#ibcon#about to write, iclass 40, count 2 2006.257.17:06:34.26#ibcon#wrote, iclass 40, count 2 2006.257.17:06:34.26#ibcon#about to read 3, iclass 40, count 2 2006.257.17:06:34.29#ibcon#read 3, iclass 40, count 2 2006.257.17:06:34.29#ibcon#about to read 4, iclass 40, count 2 2006.257.17:06:34.29#ibcon#read 4, iclass 40, count 2 2006.257.17:06:34.29#ibcon#about to read 5, iclass 40, count 2 2006.257.17:06:34.29#ibcon#read 5, iclass 40, count 2 2006.257.17:06:34.29#ibcon#about to read 6, iclass 40, count 2 2006.257.17:06:34.29#ibcon#read 6, iclass 40, count 2 2006.257.17:06:34.29#ibcon#end of sib2, iclass 40, count 2 2006.257.17:06:34.29#ibcon#*after write, iclass 40, count 2 2006.257.17:06:34.29#ibcon#*before return 0, iclass 40, count 2 2006.257.17:06:34.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:34.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:06:34.29#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.17:06:34.29#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:34.29#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:34.41#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:34.41#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:34.41#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:06:34.41#ibcon#first serial, iclass 40, count 0 2006.257.17:06:34.41#ibcon#enter sib2, iclass 40, count 0 2006.257.17:06:34.41#ibcon#flushed, iclass 40, count 0 2006.257.17:06:34.41#ibcon#about to write, iclass 40, count 0 2006.257.17:06:34.41#ibcon#wrote, iclass 40, count 0 2006.257.17:06:34.41#ibcon#about to read 3, iclass 40, count 0 2006.257.17:06:34.43#ibcon#read 3, iclass 40, count 0 2006.257.17:06:34.43#ibcon#about to read 4, iclass 40, count 0 2006.257.17:06:34.43#ibcon#read 4, iclass 40, count 0 2006.257.17:06:34.43#ibcon#about to read 5, iclass 40, count 0 2006.257.17:06:34.43#ibcon#read 5, iclass 40, count 0 2006.257.17:06:34.43#ibcon#about to read 6, iclass 40, count 0 2006.257.17:06:34.43#ibcon#read 6, iclass 40, count 0 2006.257.17:06:34.43#ibcon#end of sib2, iclass 40, count 0 2006.257.17:06:34.43#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:06:34.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:06:34.43#ibcon#[27=USB\r\n] 2006.257.17:06:34.43#ibcon#*before write, iclass 40, count 0 2006.257.17:06:34.43#ibcon#enter sib2, iclass 40, count 0 2006.257.17:06:34.43#ibcon#flushed, iclass 40, count 0 2006.257.17:06:34.43#ibcon#about to write, iclass 40, count 0 2006.257.17:06:34.43#ibcon#wrote, iclass 40, count 0 2006.257.17:06:34.43#ibcon#about to read 3, iclass 40, count 0 2006.257.17:06:34.46#ibcon#read 3, iclass 40, count 0 2006.257.17:06:34.46#ibcon#about to read 4, iclass 40, count 0 2006.257.17:06:34.46#ibcon#read 4, iclass 40, count 0 2006.257.17:06:34.46#ibcon#about to read 5, iclass 40, count 0 2006.257.17:06:34.46#ibcon#read 5, iclass 40, count 0 2006.257.17:06:34.46#ibcon#about to read 6, iclass 40, count 0 2006.257.17:06:34.46#ibcon#read 6, iclass 40, count 0 2006.257.17:06:34.46#ibcon#end of sib2, iclass 40, count 0 2006.257.17:06:34.46#ibcon#*after write, iclass 40, count 0 2006.257.17:06:34.46#ibcon#*before return 0, iclass 40, count 0 2006.257.17:06:34.46#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:34.46#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:06:34.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:06:34.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:06:34.46$vck44/vblo=5,709.99 2006.257.17:06:34.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.17:06:34.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.17:06:34.46#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:34.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:34.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:34.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:34.46#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:06:34.46#ibcon#first serial, iclass 4, count 0 2006.257.17:06:34.46#ibcon#enter sib2, iclass 4, count 0 2006.257.17:06:34.46#ibcon#flushed, iclass 4, count 0 2006.257.17:06:34.46#ibcon#about to write, iclass 4, count 0 2006.257.17:06:34.46#ibcon#wrote, iclass 4, count 0 2006.257.17:06:34.46#ibcon#about to read 3, iclass 4, count 0 2006.257.17:06:34.48#ibcon#read 3, iclass 4, count 0 2006.257.17:06:34.48#ibcon#about to read 4, iclass 4, count 0 2006.257.17:06:34.48#ibcon#read 4, iclass 4, count 0 2006.257.17:06:34.48#ibcon#about to read 5, iclass 4, count 0 2006.257.17:06:34.48#ibcon#read 5, iclass 4, count 0 2006.257.17:06:34.48#ibcon#about to read 6, iclass 4, count 0 2006.257.17:06:34.48#ibcon#read 6, iclass 4, count 0 2006.257.17:06:34.48#ibcon#end of sib2, iclass 4, count 0 2006.257.17:06:34.48#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:06:34.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:06:34.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:06:34.48#ibcon#*before write, iclass 4, count 0 2006.257.17:06:34.48#ibcon#enter sib2, iclass 4, count 0 2006.257.17:06:34.48#ibcon#flushed, iclass 4, count 0 2006.257.17:06:34.48#ibcon#about to write, iclass 4, count 0 2006.257.17:06:34.48#ibcon#wrote, iclass 4, count 0 2006.257.17:06:34.48#ibcon#about to read 3, iclass 4, count 0 2006.257.17:06:34.52#ibcon#read 3, iclass 4, count 0 2006.257.17:06:34.52#ibcon#about to read 4, iclass 4, count 0 2006.257.17:06:34.52#ibcon#read 4, iclass 4, count 0 2006.257.17:06:34.52#ibcon#about to read 5, iclass 4, count 0 2006.257.17:06:34.52#ibcon#read 5, iclass 4, count 0 2006.257.17:06:34.52#ibcon#about to read 6, iclass 4, count 0 2006.257.17:06:34.52#ibcon#read 6, iclass 4, count 0 2006.257.17:06:34.52#ibcon#end of sib2, iclass 4, count 0 2006.257.17:06:34.52#ibcon#*after write, iclass 4, count 0 2006.257.17:06:34.52#ibcon#*before return 0, iclass 4, count 0 2006.257.17:06:34.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:34.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:06:34.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:06:34.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:06:34.52$vck44/vb=5,4 2006.257.17:06:34.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.17:06:34.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.17:06:34.52#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:34.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:34.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:34.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:34.58#ibcon#enter wrdev, iclass 6, count 2 2006.257.17:06:34.58#ibcon#first serial, iclass 6, count 2 2006.257.17:06:34.58#ibcon#enter sib2, iclass 6, count 2 2006.257.17:06:34.58#ibcon#flushed, iclass 6, count 2 2006.257.17:06:34.58#ibcon#about to write, iclass 6, count 2 2006.257.17:06:34.58#ibcon#wrote, iclass 6, count 2 2006.257.17:06:34.58#ibcon#about to read 3, iclass 6, count 2 2006.257.17:06:34.60#ibcon#read 3, iclass 6, count 2 2006.257.17:06:34.60#ibcon#about to read 4, iclass 6, count 2 2006.257.17:06:34.60#ibcon#read 4, iclass 6, count 2 2006.257.17:06:34.60#ibcon#about to read 5, iclass 6, count 2 2006.257.17:06:34.60#ibcon#read 5, iclass 6, count 2 2006.257.17:06:34.60#ibcon#about to read 6, iclass 6, count 2 2006.257.17:06:34.60#ibcon#read 6, iclass 6, count 2 2006.257.17:06:34.60#ibcon#end of sib2, iclass 6, count 2 2006.257.17:06:34.60#ibcon#*mode == 0, iclass 6, count 2 2006.257.17:06:34.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.17:06:34.60#ibcon#[27=AT05-04\r\n] 2006.257.17:06:34.60#ibcon#*before write, iclass 6, count 2 2006.257.17:06:34.60#ibcon#enter sib2, iclass 6, count 2 2006.257.17:06:34.60#ibcon#flushed, iclass 6, count 2 2006.257.17:06:34.60#ibcon#about to write, iclass 6, count 2 2006.257.17:06:34.60#ibcon#wrote, iclass 6, count 2 2006.257.17:06:34.60#ibcon#about to read 3, iclass 6, count 2 2006.257.17:06:34.63#ibcon#read 3, iclass 6, count 2 2006.257.17:06:34.63#ibcon#about to read 4, iclass 6, count 2 2006.257.17:06:34.63#ibcon#read 4, iclass 6, count 2 2006.257.17:06:34.63#ibcon#about to read 5, iclass 6, count 2 2006.257.17:06:34.63#ibcon#read 5, iclass 6, count 2 2006.257.17:06:34.63#ibcon#about to read 6, iclass 6, count 2 2006.257.17:06:34.63#ibcon#read 6, iclass 6, count 2 2006.257.17:06:34.63#ibcon#end of sib2, iclass 6, count 2 2006.257.17:06:34.63#ibcon#*after write, iclass 6, count 2 2006.257.17:06:34.63#ibcon#*before return 0, iclass 6, count 2 2006.257.17:06:34.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:34.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:06:34.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.17:06:34.63#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:34.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:34.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:34.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:34.75#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:06:34.75#ibcon#first serial, iclass 6, count 0 2006.257.17:06:34.75#ibcon#enter sib2, iclass 6, count 0 2006.257.17:06:34.75#ibcon#flushed, iclass 6, count 0 2006.257.17:06:34.75#ibcon#about to write, iclass 6, count 0 2006.257.17:06:34.75#ibcon#wrote, iclass 6, count 0 2006.257.17:06:34.75#ibcon#about to read 3, iclass 6, count 0 2006.257.17:06:34.77#ibcon#read 3, iclass 6, count 0 2006.257.17:06:34.77#ibcon#about to read 4, iclass 6, count 0 2006.257.17:06:34.77#ibcon#read 4, iclass 6, count 0 2006.257.17:06:34.77#ibcon#about to read 5, iclass 6, count 0 2006.257.17:06:34.77#ibcon#read 5, iclass 6, count 0 2006.257.17:06:34.77#ibcon#about to read 6, iclass 6, count 0 2006.257.17:06:34.77#ibcon#read 6, iclass 6, count 0 2006.257.17:06:34.77#ibcon#end of sib2, iclass 6, count 0 2006.257.17:06:34.77#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:06:34.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:06:34.77#ibcon#[27=USB\r\n] 2006.257.17:06:34.77#ibcon#*before write, iclass 6, count 0 2006.257.17:06:34.77#ibcon#enter sib2, iclass 6, count 0 2006.257.17:06:34.77#ibcon#flushed, iclass 6, count 0 2006.257.17:06:34.77#ibcon#about to write, iclass 6, count 0 2006.257.17:06:34.77#ibcon#wrote, iclass 6, count 0 2006.257.17:06:34.77#ibcon#about to read 3, iclass 6, count 0 2006.257.17:06:34.80#ibcon#read 3, iclass 6, count 0 2006.257.17:06:34.80#ibcon#about to read 4, iclass 6, count 0 2006.257.17:06:34.80#ibcon#read 4, iclass 6, count 0 2006.257.17:06:34.80#ibcon#about to read 5, iclass 6, count 0 2006.257.17:06:34.80#ibcon#read 5, iclass 6, count 0 2006.257.17:06:34.80#ibcon#about to read 6, iclass 6, count 0 2006.257.17:06:34.80#ibcon#read 6, iclass 6, count 0 2006.257.17:06:34.80#ibcon#end of sib2, iclass 6, count 0 2006.257.17:06:34.80#ibcon#*after write, iclass 6, count 0 2006.257.17:06:34.80#ibcon#*before return 0, iclass 6, count 0 2006.257.17:06:34.80#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:34.80#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:06:34.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:06:34.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:06:34.80$vck44/vblo=6,719.99 2006.257.17:06:34.80#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.17:06:34.80#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.17:06:34.80#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:34.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:34.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:34.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:34.80#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:06:34.80#ibcon#first serial, iclass 10, count 0 2006.257.17:06:34.80#ibcon#enter sib2, iclass 10, count 0 2006.257.17:06:34.80#ibcon#flushed, iclass 10, count 0 2006.257.17:06:34.80#ibcon#about to write, iclass 10, count 0 2006.257.17:06:34.80#ibcon#wrote, iclass 10, count 0 2006.257.17:06:34.80#ibcon#about to read 3, iclass 10, count 0 2006.257.17:06:34.82#ibcon#read 3, iclass 10, count 0 2006.257.17:06:34.82#ibcon#about to read 4, iclass 10, count 0 2006.257.17:06:34.82#ibcon#read 4, iclass 10, count 0 2006.257.17:06:34.82#ibcon#about to read 5, iclass 10, count 0 2006.257.17:06:34.82#ibcon#read 5, iclass 10, count 0 2006.257.17:06:34.82#ibcon#about to read 6, iclass 10, count 0 2006.257.17:06:34.82#ibcon#read 6, iclass 10, count 0 2006.257.17:06:34.82#ibcon#end of sib2, iclass 10, count 0 2006.257.17:06:34.82#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:06:34.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:06:34.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:06:34.82#ibcon#*before write, iclass 10, count 0 2006.257.17:06:34.82#ibcon#enter sib2, iclass 10, count 0 2006.257.17:06:34.82#ibcon#flushed, iclass 10, count 0 2006.257.17:06:34.82#ibcon#about to write, iclass 10, count 0 2006.257.17:06:34.82#ibcon#wrote, iclass 10, count 0 2006.257.17:06:34.82#ibcon#about to read 3, iclass 10, count 0 2006.257.17:06:34.86#ibcon#read 3, iclass 10, count 0 2006.257.17:06:34.86#ibcon#about to read 4, iclass 10, count 0 2006.257.17:06:34.86#ibcon#read 4, iclass 10, count 0 2006.257.17:06:34.86#ibcon#about to read 5, iclass 10, count 0 2006.257.17:06:34.86#ibcon#read 5, iclass 10, count 0 2006.257.17:06:34.86#ibcon#about to read 6, iclass 10, count 0 2006.257.17:06:34.86#ibcon#read 6, iclass 10, count 0 2006.257.17:06:34.86#ibcon#end of sib2, iclass 10, count 0 2006.257.17:06:34.86#ibcon#*after write, iclass 10, count 0 2006.257.17:06:34.86#ibcon#*before return 0, iclass 10, count 0 2006.257.17:06:34.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:34.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:06:34.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:06:34.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:06:34.86$vck44/vb=6,4 2006.257.17:06:34.86#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.17:06:34.86#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.17:06:34.86#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:34.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:34.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:34.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:34.92#ibcon#enter wrdev, iclass 12, count 2 2006.257.17:06:34.92#ibcon#first serial, iclass 12, count 2 2006.257.17:06:34.92#ibcon#enter sib2, iclass 12, count 2 2006.257.17:06:34.92#ibcon#flushed, iclass 12, count 2 2006.257.17:06:34.92#ibcon#about to write, iclass 12, count 2 2006.257.17:06:34.92#ibcon#wrote, iclass 12, count 2 2006.257.17:06:34.92#ibcon#about to read 3, iclass 12, count 2 2006.257.17:06:34.94#ibcon#read 3, iclass 12, count 2 2006.257.17:06:34.94#ibcon#about to read 4, iclass 12, count 2 2006.257.17:06:34.94#ibcon#read 4, iclass 12, count 2 2006.257.17:06:34.94#ibcon#about to read 5, iclass 12, count 2 2006.257.17:06:34.94#ibcon#read 5, iclass 12, count 2 2006.257.17:06:34.94#ibcon#about to read 6, iclass 12, count 2 2006.257.17:06:34.94#ibcon#read 6, iclass 12, count 2 2006.257.17:06:34.94#ibcon#end of sib2, iclass 12, count 2 2006.257.17:06:34.94#ibcon#*mode == 0, iclass 12, count 2 2006.257.17:06:34.94#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.17:06:34.94#ibcon#[27=AT06-04\r\n] 2006.257.17:06:34.94#ibcon#*before write, iclass 12, count 2 2006.257.17:06:34.94#ibcon#enter sib2, iclass 12, count 2 2006.257.17:06:34.94#ibcon#flushed, iclass 12, count 2 2006.257.17:06:34.94#ibcon#about to write, iclass 12, count 2 2006.257.17:06:34.94#ibcon#wrote, iclass 12, count 2 2006.257.17:06:34.94#ibcon#about to read 3, iclass 12, count 2 2006.257.17:06:34.97#ibcon#read 3, iclass 12, count 2 2006.257.17:06:34.97#ibcon#about to read 4, iclass 12, count 2 2006.257.17:06:34.97#ibcon#read 4, iclass 12, count 2 2006.257.17:06:34.97#ibcon#about to read 5, iclass 12, count 2 2006.257.17:06:34.97#ibcon#read 5, iclass 12, count 2 2006.257.17:06:34.97#ibcon#about to read 6, iclass 12, count 2 2006.257.17:06:34.97#ibcon#read 6, iclass 12, count 2 2006.257.17:06:34.97#ibcon#end of sib2, iclass 12, count 2 2006.257.17:06:34.97#ibcon#*after write, iclass 12, count 2 2006.257.17:06:34.97#ibcon#*before return 0, iclass 12, count 2 2006.257.17:06:34.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:34.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:06:34.97#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.17:06:34.97#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:34.97#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:35.09#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:35.09#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:35.09#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:06:35.09#ibcon#first serial, iclass 12, count 0 2006.257.17:06:35.09#ibcon#enter sib2, iclass 12, count 0 2006.257.17:06:35.09#ibcon#flushed, iclass 12, count 0 2006.257.17:06:35.09#ibcon#about to write, iclass 12, count 0 2006.257.17:06:35.09#ibcon#wrote, iclass 12, count 0 2006.257.17:06:35.09#ibcon#about to read 3, iclass 12, count 0 2006.257.17:06:35.11#ibcon#read 3, iclass 12, count 0 2006.257.17:06:35.11#ibcon#about to read 4, iclass 12, count 0 2006.257.17:06:35.11#ibcon#read 4, iclass 12, count 0 2006.257.17:06:35.11#ibcon#about to read 5, iclass 12, count 0 2006.257.17:06:35.11#ibcon#read 5, iclass 12, count 0 2006.257.17:06:35.11#ibcon#about to read 6, iclass 12, count 0 2006.257.17:06:35.11#ibcon#read 6, iclass 12, count 0 2006.257.17:06:35.11#ibcon#end of sib2, iclass 12, count 0 2006.257.17:06:35.11#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:06:35.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:06:35.11#ibcon#[27=USB\r\n] 2006.257.17:06:35.11#ibcon#*before write, iclass 12, count 0 2006.257.17:06:35.11#ibcon#enter sib2, iclass 12, count 0 2006.257.17:06:35.11#ibcon#flushed, iclass 12, count 0 2006.257.17:06:35.11#ibcon#about to write, iclass 12, count 0 2006.257.17:06:35.11#ibcon#wrote, iclass 12, count 0 2006.257.17:06:35.11#ibcon#about to read 3, iclass 12, count 0 2006.257.17:06:35.14#ibcon#read 3, iclass 12, count 0 2006.257.17:06:35.14#ibcon#about to read 4, iclass 12, count 0 2006.257.17:06:35.14#ibcon#read 4, iclass 12, count 0 2006.257.17:06:35.14#ibcon#about to read 5, iclass 12, count 0 2006.257.17:06:35.14#ibcon#read 5, iclass 12, count 0 2006.257.17:06:35.14#ibcon#about to read 6, iclass 12, count 0 2006.257.17:06:35.14#ibcon#read 6, iclass 12, count 0 2006.257.17:06:35.14#ibcon#end of sib2, iclass 12, count 0 2006.257.17:06:35.14#ibcon#*after write, iclass 12, count 0 2006.257.17:06:35.14#ibcon#*before return 0, iclass 12, count 0 2006.257.17:06:35.14#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:35.14#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:06:35.14#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:06:35.14#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:06:35.14$vck44/vblo=7,734.99 2006.257.17:06:35.14#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.17:06:35.14#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.17:06:35.14#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:35.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:35.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:35.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:35.14#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:06:35.14#ibcon#first serial, iclass 14, count 0 2006.257.17:06:35.14#ibcon#enter sib2, iclass 14, count 0 2006.257.17:06:35.14#ibcon#flushed, iclass 14, count 0 2006.257.17:06:35.14#ibcon#about to write, iclass 14, count 0 2006.257.17:06:35.14#ibcon#wrote, iclass 14, count 0 2006.257.17:06:35.14#ibcon#about to read 3, iclass 14, count 0 2006.257.17:06:35.16#ibcon#read 3, iclass 14, count 0 2006.257.17:06:35.16#ibcon#about to read 4, iclass 14, count 0 2006.257.17:06:35.16#ibcon#read 4, iclass 14, count 0 2006.257.17:06:35.16#ibcon#about to read 5, iclass 14, count 0 2006.257.17:06:35.16#ibcon#read 5, iclass 14, count 0 2006.257.17:06:35.16#ibcon#about to read 6, iclass 14, count 0 2006.257.17:06:35.16#ibcon#read 6, iclass 14, count 0 2006.257.17:06:35.16#ibcon#end of sib2, iclass 14, count 0 2006.257.17:06:35.16#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:06:35.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:06:35.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:06:35.16#ibcon#*before write, iclass 14, count 0 2006.257.17:06:35.16#ibcon#enter sib2, iclass 14, count 0 2006.257.17:06:35.16#ibcon#flushed, iclass 14, count 0 2006.257.17:06:35.16#ibcon#about to write, iclass 14, count 0 2006.257.17:06:35.16#ibcon#wrote, iclass 14, count 0 2006.257.17:06:35.16#ibcon#about to read 3, iclass 14, count 0 2006.257.17:06:35.20#ibcon#read 3, iclass 14, count 0 2006.257.17:06:35.20#ibcon#about to read 4, iclass 14, count 0 2006.257.17:06:35.20#ibcon#read 4, iclass 14, count 0 2006.257.17:06:35.20#ibcon#about to read 5, iclass 14, count 0 2006.257.17:06:35.20#ibcon#read 5, iclass 14, count 0 2006.257.17:06:35.20#ibcon#about to read 6, iclass 14, count 0 2006.257.17:06:35.20#ibcon#read 6, iclass 14, count 0 2006.257.17:06:35.20#ibcon#end of sib2, iclass 14, count 0 2006.257.17:06:35.20#ibcon#*after write, iclass 14, count 0 2006.257.17:06:35.20#ibcon#*before return 0, iclass 14, count 0 2006.257.17:06:35.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:35.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:06:35.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:06:35.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:06:35.20$vck44/vb=7,4 2006.257.17:06:35.20#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.17:06:35.20#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.17:06:35.20#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:35.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:35.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:35.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:35.26#ibcon#enter wrdev, iclass 16, count 2 2006.257.17:06:35.26#ibcon#first serial, iclass 16, count 2 2006.257.17:06:35.26#ibcon#enter sib2, iclass 16, count 2 2006.257.17:06:35.26#ibcon#flushed, iclass 16, count 2 2006.257.17:06:35.26#ibcon#about to write, iclass 16, count 2 2006.257.17:06:35.26#ibcon#wrote, iclass 16, count 2 2006.257.17:06:35.26#ibcon#about to read 3, iclass 16, count 2 2006.257.17:06:35.28#ibcon#read 3, iclass 16, count 2 2006.257.17:06:35.28#ibcon#about to read 4, iclass 16, count 2 2006.257.17:06:35.28#ibcon#read 4, iclass 16, count 2 2006.257.17:06:35.28#ibcon#about to read 5, iclass 16, count 2 2006.257.17:06:35.28#ibcon#read 5, iclass 16, count 2 2006.257.17:06:35.28#ibcon#about to read 6, iclass 16, count 2 2006.257.17:06:35.28#ibcon#read 6, iclass 16, count 2 2006.257.17:06:35.28#ibcon#end of sib2, iclass 16, count 2 2006.257.17:06:35.28#ibcon#*mode == 0, iclass 16, count 2 2006.257.17:06:35.28#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.17:06:35.28#ibcon#[27=AT07-04\r\n] 2006.257.17:06:35.28#ibcon#*before write, iclass 16, count 2 2006.257.17:06:35.28#ibcon#enter sib2, iclass 16, count 2 2006.257.17:06:35.28#ibcon#flushed, iclass 16, count 2 2006.257.17:06:35.28#ibcon#about to write, iclass 16, count 2 2006.257.17:06:35.28#ibcon#wrote, iclass 16, count 2 2006.257.17:06:35.28#ibcon#about to read 3, iclass 16, count 2 2006.257.17:06:35.31#ibcon#read 3, iclass 16, count 2 2006.257.17:06:35.31#ibcon#about to read 4, iclass 16, count 2 2006.257.17:06:35.31#ibcon#read 4, iclass 16, count 2 2006.257.17:06:35.31#ibcon#about to read 5, iclass 16, count 2 2006.257.17:06:35.31#ibcon#read 5, iclass 16, count 2 2006.257.17:06:35.31#ibcon#about to read 6, iclass 16, count 2 2006.257.17:06:35.31#ibcon#read 6, iclass 16, count 2 2006.257.17:06:35.31#ibcon#end of sib2, iclass 16, count 2 2006.257.17:06:35.31#ibcon#*after write, iclass 16, count 2 2006.257.17:06:35.31#ibcon#*before return 0, iclass 16, count 2 2006.257.17:06:35.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:35.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:06:35.31#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.17:06:35.31#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:35.31#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:35.43#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:35.43#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:35.43#ibcon#enter wrdev, iclass 16, count 0 2006.257.17:06:35.43#ibcon#first serial, iclass 16, count 0 2006.257.17:06:35.43#ibcon#enter sib2, iclass 16, count 0 2006.257.17:06:35.43#ibcon#flushed, iclass 16, count 0 2006.257.17:06:35.43#ibcon#about to write, iclass 16, count 0 2006.257.17:06:35.43#ibcon#wrote, iclass 16, count 0 2006.257.17:06:35.43#ibcon#about to read 3, iclass 16, count 0 2006.257.17:06:35.45#ibcon#read 3, iclass 16, count 0 2006.257.17:06:35.45#ibcon#about to read 4, iclass 16, count 0 2006.257.17:06:35.45#ibcon#read 4, iclass 16, count 0 2006.257.17:06:35.45#ibcon#about to read 5, iclass 16, count 0 2006.257.17:06:35.45#ibcon#read 5, iclass 16, count 0 2006.257.17:06:35.45#ibcon#about to read 6, iclass 16, count 0 2006.257.17:06:35.45#ibcon#read 6, iclass 16, count 0 2006.257.17:06:35.45#ibcon#end of sib2, iclass 16, count 0 2006.257.17:06:35.45#ibcon#*mode == 0, iclass 16, count 0 2006.257.17:06:35.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.17:06:35.45#ibcon#[27=USB\r\n] 2006.257.17:06:35.45#ibcon#*before write, iclass 16, count 0 2006.257.17:06:35.45#ibcon#enter sib2, iclass 16, count 0 2006.257.17:06:35.45#ibcon#flushed, iclass 16, count 0 2006.257.17:06:35.45#ibcon#about to write, iclass 16, count 0 2006.257.17:06:35.45#ibcon#wrote, iclass 16, count 0 2006.257.17:06:35.45#ibcon#about to read 3, iclass 16, count 0 2006.257.17:06:35.48#ibcon#read 3, iclass 16, count 0 2006.257.17:06:35.48#ibcon#about to read 4, iclass 16, count 0 2006.257.17:06:35.48#ibcon#read 4, iclass 16, count 0 2006.257.17:06:35.48#ibcon#about to read 5, iclass 16, count 0 2006.257.17:06:35.48#ibcon#read 5, iclass 16, count 0 2006.257.17:06:35.48#ibcon#about to read 6, iclass 16, count 0 2006.257.17:06:35.48#ibcon#read 6, iclass 16, count 0 2006.257.17:06:35.48#ibcon#end of sib2, iclass 16, count 0 2006.257.17:06:35.48#ibcon#*after write, iclass 16, count 0 2006.257.17:06:35.48#ibcon#*before return 0, iclass 16, count 0 2006.257.17:06:35.48#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:35.48#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:06:35.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.17:06:35.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.17:06:35.48$vck44/vblo=8,744.99 2006.257.17:06:35.48#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.17:06:35.48#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.17:06:35.48#ibcon#ireg 17 cls_cnt 0 2006.257.17:06:35.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:35.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:35.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:35.48#ibcon#enter wrdev, iclass 18, count 0 2006.257.17:06:35.48#ibcon#first serial, iclass 18, count 0 2006.257.17:06:35.48#ibcon#enter sib2, iclass 18, count 0 2006.257.17:06:35.48#ibcon#flushed, iclass 18, count 0 2006.257.17:06:35.48#ibcon#about to write, iclass 18, count 0 2006.257.17:06:35.48#ibcon#wrote, iclass 18, count 0 2006.257.17:06:35.48#ibcon#about to read 3, iclass 18, count 0 2006.257.17:06:35.50#ibcon#read 3, iclass 18, count 0 2006.257.17:06:35.50#ibcon#about to read 4, iclass 18, count 0 2006.257.17:06:35.50#ibcon#read 4, iclass 18, count 0 2006.257.17:06:35.50#ibcon#about to read 5, iclass 18, count 0 2006.257.17:06:35.50#ibcon#read 5, iclass 18, count 0 2006.257.17:06:35.50#ibcon#about to read 6, iclass 18, count 0 2006.257.17:06:35.50#ibcon#read 6, iclass 18, count 0 2006.257.17:06:35.50#ibcon#end of sib2, iclass 18, count 0 2006.257.17:06:35.50#ibcon#*mode == 0, iclass 18, count 0 2006.257.17:06:35.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.17:06:35.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:06:35.50#ibcon#*before write, iclass 18, count 0 2006.257.17:06:35.50#ibcon#enter sib2, iclass 18, count 0 2006.257.17:06:35.50#ibcon#flushed, iclass 18, count 0 2006.257.17:06:35.50#ibcon#about to write, iclass 18, count 0 2006.257.17:06:35.50#ibcon#wrote, iclass 18, count 0 2006.257.17:06:35.50#ibcon#about to read 3, iclass 18, count 0 2006.257.17:06:35.54#ibcon#read 3, iclass 18, count 0 2006.257.17:06:35.54#ibcon#about to read 4, iclass 18, count 0 2006.257.17:06:35.54#ibcon#read 4, iclass 18, count 0 2006.257.17:06:35.54#ibcon#about to read 5, iclass 18, count 0 2006.257.17:06:35.54#ibcon#read 5, iclass 18, count 0 2006.257.17:06:35.54#ibcon#about to read 6, iclass 18, count 0 2006.257.17:06:35.54#ibcon#read 6, iclass 18, count 0 2006.257.17:06:35.54#ibcon#end of sib2, iclass 18, count 0 2006.257.17:06:35.54#ibcon#*after write, iclass 18, count 0 2006.257.17:06:35.54#ibcon#*before return 0, iclass 18, count 0 2006.257.17:06:35.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:35.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:06:35.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.17:06:35.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.17:06:35.54$vck44/vb=8,4 2006.257.17:06:35.54#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.17:06:35.54#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.17:06:35.54#ibcon#ireg 11 cls_cnt 2 2006.257.17:06:35.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:35.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:35.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:35.60#ibcon#enter wrdev, iclass 20, count 2 2006.257.17:06:35.60#ibcon#first serial, iclass 20, count 2 2006.257.17:06:35.60#ibcon#enter sib2, iclass 20, count 2 2006.257.17:06:35.60#ibcon#flushed, iclass 20, count 2 2006.257.17:06:35.60#ibcon#about to write, iclass 20, count 2 2006.257.17:06:35.60#ibcon#wrote, iclass 20, count 2 2006.257.17:06:35.60#ibcon#about to read 3, iclass 20, count 2 2006.257.17:06:35.62#ibcon#read 3, iclass 20, count 2 2006.257.17:06:35.62#ibcon#about to read 4, iclass 20, count 2 2006.257.17:06:35.62#ibcon#read 4, iclass 20, count 2 2006.257.17:06:35.62#ibcon#about to read 5, iclass 20, count 2 2006.257.17:06:35.62#ibcon#read 5, iclass 20, count 2 2006.257.17:06:35.62#ibcon#about to read 6, iclass 20, count 2 2006.257.17:06:35.62#ibcon#read 6, iclass 20, count 2 2006.257.17:06:35.62#ibcon#end of sib2, iclass 20, count 2 2006.257.17:06:35.62#ibcon#*mode == 0, iclass 20, count 2 2006.257.17:06:35.62#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.17:06:35.62#ibcon#[27=AT08-04\r\n] 2006.257.17:06:35.62#ibcon#*before write, iclass 20, count 2 2006.257.17:06:35.62#ibcon#enter sib2, iclass 20, count 2 2006.257.17:06:35.62#ibcon#flushed, iclass 20, count 2 2006.257.17:06:35.62#ibcon#about to write, iclass 20, count 2 2006.257.17:06:35.62#ibcon#wrote, iclass 20, count 2 2006.257.17:06:35.62#ibcon#about to read 3, iclass 20, count 2 2006.257.17:06:35.65#ibcon#read 3, iclass 20, count 2 2006.257.17:06:35.65#ibcon#about to read 4, iclass 20, count 2 2006.257.17:06:35.65#ibcon#read 4, iclass 20, count 2 2006.257.17:06:35.65#ibcon#about to read 5, iclass 20, count 2 2006.257.17:06:35.65#ibcon#read 5, iclass 20, count 2 2006.257.17:06:35.65#ibcon#about to read 6, iclass 20, count 2 2006.257.17:06:35.65#ibcon#read 6, iclass 20, count 2 2006.257.17:06:35.65#ibcon#end of sib2, iclass 20, count 2 2006.257.17:06:35.65#ibcon#*after write, iclass 20, count 2 2006.257.17:06:35.65#ibcon#*before return 0, iclass 20, count 2 2006.257.17:06:35.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:35.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:06:35.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.17:06:35.65#ibcon#ireg 7 cls_cnt 0 2006.257.17:06:35.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:35.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:35.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:35.77#ibcon#enter wrdev, iclass 20, count 0 2006.257.17:06:35.77#ibcon#first serial, iclass 20, count 0 2006.257.17:06:35.77#ibcon#enter sib2, iclass 20, count 0 2006.257.17:06:35.77#ibcon#flushed, iclass 20, count 0 2006.257.17:06:35.77#ibcon#about to write, iclass 20, count 0 2006.257.17:06:35.77#ibcon#wrote, iclass 20, count 0 2006.257.17:06:35.77#ibcon#about to read 3, iclass 20, count 0 2006.257.17:06:35.79#ibcon#read 3, iclass 20, count 0 2006.257.17:06:35.79#ibcon#about to read 4, iclass 20, count 0 2006.257.17:06:35.79#ibcon#read 4, iclass 20, count 0 2006.257.17:06:35.79#ibcon#about to read 5, iclass 20, count 0 2006.257.17:06:35.79#ibcon#read 5, iclass 20, count 0 2006.257.17:06:35.79#ibcon#about to read 6, iclass 20, count 0 2006.257.17:06:35.79#ibcon#read 6, iclass 20, count 0 2006.257.17:06:35.79#ibcon#end of sib2, iclass 20, count 0 2006.257.17:06:35.79#ibcon#*mode == 0, iclass 20, count 0 2006.257.17:06:35.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.17:06:35.79#ibcon#[27=USB\r\n] 2006.257.17:06:35.79#ibcon#*before write, iclass 20, count 0 2006.257.17:06:35.79#ibcon#enter sib2, iclass 20, count 0 2006.257.17:06:35.79#ibcon#flushed, iclass 20, count 0 2006.257.17:06:35.79#ibcon#about to write, iclass 20, count 0 2006.257.17:06:35.79#ibcon#wrote, iclass 20, count 0 2006.257.17:06:35.79#ibcon#about to read 3, iclass 20, count 0 2006.257.17:06:35.82#ibcon#read 3, iclass 20, count 0 2006.257.17:06:35.82#ibcon#about to read 4, iclass 20, count 0 2006.257.17:06:35.82#ibcon#read 4, iclass 20, count 0 2006.257.17:06:35.82#ibcon#about to read 5, iclass 20, count 0 2006.257.17:06:35.82#ibcon#read 5, iclass 20, count 0 2006.257.17:06:35.82#ibcon#about to read 6, iclass 20, count 0 2006.257.17:06:35.82#ibcon#read 6, iclass 20, count 0 2006.257.17:06:35.82#ibcon#end of sib2, iclass 20, count 0 2006.257.17:06:35.82#ibcon#*after write, iclass 20, count 0 2006.257.17:06:35.82#ibcon#*before return 0, iclass 20, count 0 2006.257.17:06:35.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:35.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:06:35.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.17:06:35.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.17:06:35.82$vck44/vabw=wide 2006.257.17:06:35.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.17:06:35.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.17:06:35.82#ibcon#ireg 8 cls_cnt 0 2006.257.17:06:35.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:35.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:35.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:35.82#ibcon#enter wrdev, iclass 22, count 0 2006.257.17:06:35.82#ibcon#first serial, iclass 22, count 0 2006.257.17:06:35.82#ibcon#enter sib2, iclass 22, count 0 2006.257.17:06:35.82#ibcon#flushed, iclass 22, count 0 2006.257.17:06:35.82#ibcon#about to write, iclass 22, count 0 2006.257.17:06:35.82#ibcon#wrote, iclass 22, count 0 2006.257.17:06:35.82#ibcon#about to read 3, iclass 22, count 0 2006.257.17:06:35.84#ibcon#read 3, iclass 22, count 0 2006.257.17:06:35.84#ibcon#about to read 4, iclass 22, count 0 2006.257.17:06:35.84#ibcon#read 4, iclass 22, count 0 2006.257.17:06:35.84#ibcon#about to read 5, iclass 22, count 0 2006.257.17:06:35.84#ibcon#read 5, iclass 22, count 0 2006.257.17:06:35.84#ibcon#about to read 6, iclass 22, count 0 2006.257.17:06:35.84#ibcon#read 6, iclass 22, count 0 2006.257.17:06:35.84#ibcon#end of sib2, iclass 22, count 0 2006.257.17:06:35.84#ibcon#*mode == 0, iclass 22, count 0 2006.257.17:06:35.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.17:06:35.84#ibcon#[25=BW32\r\n] 2006.257.17:06:35.84#ibcon#*before write, iclass 22, count 0 2006.257.17:06:35.84#ibcon#enter sib2, iclass 22, count 0 2006.257.17:06:35.84#ibcon#flushed, iclass 22, count 0 2006.257.17:06:35.84#ibcon#about to write, iclass 22, count 0 2006.257.17:06:35.84#ibcon#wrote, iclass 22, count 0 2006.257.17:06:35.84#ibcon#about to read 3, iclass 22, count 0 2006.257.17:06:35.87#ibcon#read 3, iclass 22, count 0 2006.257.17:06:35.87#ibcon#about to read 4, iclass 22, count 0 2006.257.17:06:35.87#ibcon#read 4, iclass 22, count 0 2006.257.17:06:35.87#ibcon#about to read 5, iclass 22, count 0 2006.257.17:06:35.87#ibcon#read 5, iclass 22, count 0 2006.257.17:06:35.87#ibcon#about to read 6, iclass 22, count 0 2006.257.17:06:35.87#ibcon#read 6, iclass 22, count 0 2006.257.17:06:35.87#ibcon#end of sib2, iclass 22, count 0 2006.257.17:06:35.87#ibcon#*after write, iclass 22, count 0 2006.257.17:06:35.87#ibcon#*before return 0, iclass 22, count 0 2006.257.17:06:35.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:35.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:06:35.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.17:06:35.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.17:06:35.87$vck44/vbbw=wide 2006.257.17:06:35.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.17:06:35.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.17:06:35.87#ibcon#ireg 8 cls_cnt 0 2006.257.17:06:35.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:06:35.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:06:35.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:06:35.94#ibcon#enter wrdev, iclass 24, count 0 2006.257.17:06:35.94#ibcon#first serial, iclass 24, count 0 2006.257.17:06:35.94#ibcon#enter sib2, iclass 24, count 0 2006.257.17:06:35.94#ibcon#flushed, iclass 24, count 0 2006.257.17:06:35.94#ibcon#about to write, iclass 24, count 0 2006.257.17:06:35.94#ibcon#wrote, iclass 24, count 0 2006.257.17:06:35.94#ibcon#about to read 3, iclass 24, count 0 2006.257.17:06:35.96#ibcon#read 3, iclass 24, count 0 2006.257.17:06:35.96#ibcon#about to read 4, iclass 24, count 0 2006.257.17:06:35.96#ibcon#read 4, iclass 24, count 0 2006.257.17:06:35.96#ibcon#about to read 5, iclass 24, count 0 2006.257.17:06:35.96#ibcon#read 5, iclass 24, count 0 2006.257.17:06:35.96#ibcon#about to read 6, iclass 24, count 0 2006.257.17:06:35.96#ibcon#read 6, iclass 24, count 0 2006.257.17:06:35.96#ibcon#end of sib2, iclass 24, count 0 2006.257.17:06:35.96#ibcon#*mode == 0, iclass 24, count 0 2006.257.17:06:35.96#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.17:06:35.96#ibcon#[27=BW32\r\n] 2006.257.17:06:35.96#ibcon#*before write, iclass 24, count 0 2006.257.17:06:35.96#ibcon#enter sib2, iclass 24, count 0 2006.257.17:06:35.96#ibcon#flushed, iclass 24, count 0 2006.257.17:06:35.96#ibcon#about to write, iclass 24, count 0 2006.257.17:06:35.96#ibcon#wrote, iclass 24, count 0 2006.257.17:06:35.96#ibcon#about to read 3, iclass 24, count 0 2006.257.17:06:35.99#ibcon#read 3, iclass 24, count 0 2006.257.17:06:35.99#ibcon#about to read 4, iclass 24, count 0 2006.257.17:06:35.99#ibcon#read 4, iclass 24, count 0 2006.257.17:06:35.99#ibcon#about to read 5, iclass 24, count 0 2006.257.17:06:35.99#ibcon#read 5, iclass 24, count 0 2006.257.17:06:35.99#ibcon#about to read 6, iclass 24, count 0 2006.257.17:06:35.99#ibcon#read 6, iclass 24, count 0 2006.257.17:06:35.99#ibcon#end of sib2, iclass 24, count 0 2006.257.17:06:35.99#ibcon#*after write, iclass 24, count 0 2006.257.17:06:35.99#ibcon#*before return 0, iclass 24, count 0 2006.257.17:06:35.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:06:35.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:06:35.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.17:06:35.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.17:06:35.99$setupk4/ifdk4 2006.257.17:06:35.99$ifdk4/lo= 2006.257.17:06:35.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:06:35.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:06:35.99$ifdk4/patch= 2006.257.17:06:35.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:06:35.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:06:35.99$setupk4/!*+20s 2006.257.17:06:37.58#abcon#<5=/14 1.6 4.5 17.37 961014.2\r\n> 2006.257.17:06:37.60#abcon#{5=INTERFACE CLEAR} 2006.257.17:06:37.66#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:06:45.14#trakl#Source acquired 2006.257.17:06:45.14#flagr#flagr/antenna,acquired 2006.257.17:06:47.75#abcon#<5=/14 1.6 4.6 17.36 961014.2\r\n> 2006.257.17:06:47.77#abcon#{5=INTERFACE CLEAR} 2006.257.17:06:47.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:06:50.50$setupk4/"tpicd 2006.257.17:06:50.50$setupk4/echo=off 2006.257.17:06:50.50$setupk4/xlog=off 2006.257.17:06:50.50:!2006.257.17:10:38 2006.257.17:10:38.00:preob 2006.257.17:10:38.13/onsource/TRACKING 2006.257.17:10:38.13:!2006.257.17:10:48 2006.257.17:10:48.00:"tape 2006.257.17:10:48.00:"st=record 2006.257.17:10:48.00:data_valid=on 2006.257.17:10:48.00:midob 2006.257.17:10:48.13/onsource/TRACKING 2006.257.17:10:48.13/wx/17.36,1014.2,97 2006.257.17:10:48.27/cable/+6.4864E-03 2006.257.17:10:49.36/va/01,08,usb,yes,31,34 2006.257.17:10:49.36/va/02,07,usb,yes,34,34 2006.257.17:10:49.36/va/03,08,usb,yes,30,32 2006.257.17:10:49.36/va/04,07,usb,yes,35,37 2006.257.17:10:49.36/va/05,04,usb,yes,31,32 2006.257.17:10:49.36/va/06,04,usb,yes,35,35 2006.257.17:10:49.36/va/07,04,usb,yes,36,36 2006.257.17:10:49.36/va/08,04,usb,yes,30,37 2006.257.17:10:49.59/valo/01,524.99,yes,locked 2006.257.17:10:49.59/valo/02,534.99,yes,locked 2006.257.17:10:49.59/valo/03,564.99,yes,locked 2006.257.17:10:49.59/valo/04,624.99,yes,locked 2006.257.17:10:49.59/valo/05,734.99,yes,locked 2006.257.17:10:49.59/valo/06,814.99,yes,locked 2006.257.17:10:49.59/valo/07,864.99,yes,locked 2006.257.17:10:49.59/valo/08,884.99,yes,locked 2006.257.17:10:50.68/vb/01,04,usb,yes,31,29 2006.257.17:10:50.68/vb/02,05,usb,yes,30,29 2006.257.17:10:50.68/vb/03,04,usb,yes,30,34 2006.257.17:10:50.68/vb/04,05,usb,yes,31,30 2006.257.17:10:50.68/vb/05,04,usb,yes,27,30 2006.257.17:10:50.68/vb/06,04,usb,yes,32,28 2006.257.17:10:50.68/vb/07,04,usb,yes,32,31 2006.257.17:10:50.68/vb/08,04,usb,yes,29,32 2006.257.17:10:50.91/vblo/01,629.99,yes,locked 2006.257.17:10:50.91/vblo/02,634.99,yes,locked 2006.257.17:10:50.91/vblo/03,649.99,yes,locked 2006.257.17:10:50.91/vblo/04,679.99,yes,locked 2006.257.17:10:50.91/vblo/05,709.99,yes,locked 2006.257.17:10:50.91/vblo/06,719.99,yes,locked 2006.257.17:10:50.91/vblo/07,734.99,yes,locked 2006.257.17:10:50.91/vblo/08,744.99,yes,locked 2006.257.17:10:51.06/vabw/8 2006.257.17:10:51.21/vbbw/8 2006.257.17:10:51.30/xfe/off,on,15.0 2006.257.17:10:51.68/ifatt/23,28,28,28 2006.257.17:10:52.08/fmout-gps/S +4.54E-07 2006.257.17:10:52.12:!2006.257.17:13:58 2006.257.17:13:58.00:data_valid=off 2006.257.17:13:58.00:"et 2006.257.17:13:58.01:!+3s 2006.257.17:14:01.03:"tape 2006.257.17:14:01.03:postob 2006.257.17:14:01.12/cable/+6.4846E-03 2006.257.17:14:01.12/wx/17.37,1014.3,96 2006.257.17:14:01.18/fmout-gps/S +4.54E-07 2006.257.17:14:01.18:scan_name=257-1716,jd0609,40 2006.257.17:14:01.19:source=2128-123,213135.26,-120704.8,2000.0,ccw 2006.257.17:14:03.14#flagr#flagr/antenna,new-source 2006.257.17:14:03.14:checkk5 2006.257.17:14:03.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:14:03.84/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:14:04.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:14:04.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:14:04.85/chk_obsdata//k5ts1/T2571710??a.dat file size is correct (nominal:760MB, actual:760MB). 2006.257.17:14:05.18/chk_obsdata//k5ts2/T2571710??b.dat file size is correct (nominal:760MB, actual:760MB). 2006.257.17:14:05.52/chk_obsdata//k5ts3/T2571710??c.dat file size is correct (nominal:760MB, actual:760MB). 2006.257.17:14:05.85/chk_obsdata//k5ts4/T2571710??d.dat file size is correct (nominal:760MB, actual:760MB). 2006.257.17:14:06.52/k5log//k5ts1_log_newline 2006.257.17:14:07.18/k5log//k5ts2_log_newline 2006.257.17:14:07.83/k5log//k5ts3_log_newline 2006.257.17:14:08.48/k5log//k5ts4_log_newline 2006.257.17:14:08.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:14:08.51:setupk4=1 2006.257.17:14:08.51$setupk4/echo=on 2006.257.17:14:08.51$setupk4/pcalon 2006.257.17:14:08.51$pcalon/"no phase cal control is implemented here 2006.257.17:14:08.51$setupk4/"tpicd=stop 2006.257.17:14:08.51$setupk4/"rec=synch_on 2006.257.17:14:08.51$setupk4/"rec_mode=128 2006.257.17:14:08.51$setupk4/!* 2006.257.17:14:08.51$setupk4/recpk4 2006.257.17:14:08.51$recpk4/recpatch= 2006.257.17:14:08.51$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:14:08.51$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:14:08.51$setupk4/vck44 2006.257.17:14:08.51$vck44/valo=1,524.99 2006.257.17:14:08.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.17:14:08.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.17:14:08.51#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:08.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:08.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:08.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:08.51#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:14:08.51#ibcon#first serial, iclass 29, count 0 2006.257.17:14:08.51#ibcon#enter sib2, iclass 29, count 0 2006.257.17:14:08.51#ibcon#flushed, iclass 29, count 0 2006.257.17:14:08.51#ibcon#about to write, iclass 29, count 0 2006.257.17:14:08.51#ibcon#wrote, iclass 29, count 0 2006.257.17:14:08.51#ibcon#about to read 3, iclass 29, count 0 2006.257.17:14:08.53#ibcon#read 3, iclass 29, count 0 2006.257.17:14:08.53#ibcon#about to read 4, iclass 29, count 0 2006.257.17:14:08.53#ibcon#read 4, iclass 29, count 0 2006.257.17:14:08.53#ibcon#about to read 5, iclass 29, count 0 2006.257.17:14:08.53#ibcon#read 5, iclass 29, count 0 2006.257.17:14:08.53#ibcon#about to read 6, iclass 29, count 0 2006.257.17:14:08.53#ibcon#read 6, iclass 29, count 0 2006.257.17:14:08.53#ibcon#end of sib2, iclass 29, count 0 2006.257.17:14:08.53#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:14:08.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:14:08.53#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:14:08.53#ibcon#*before write, iclass 29, count 0 2006.257.17:14:08.53#ibcon#enter sib2, iclass 29, count 0 2006.257.17:14:08.53#ibcon#flushed, iclass 29, count 0 2006.257.17:14:08.53#ibcon#about to write, iclass 29, count 0 2006.257.17:14:08.53#ibcon#wrote, iclass 29, count 0 2006.257.17:14:08.53#ibcon#about to read 3, iclass 29, count 0 2006.257.17:14:08.58#ibcon#read 3, iclass 29, count 0 2006.257.17:14:08.58#ibcon#about to read 4, iclass 29, count 0 2006.257.17:14:08.58#ibcon#read 4, iclass 29, count 0 2006.257.17:14:08.58#ibcon#about to read 5, iclass 29, count 0 2006.257.17:14:08.58#ibcon#read 5, iclass 29, count 0 2006.257.17:14:08.58#ibcon#about to read 6, iclass 29, count 0 2006.257.17:14:08.58#ibcon#read 6, iclass 29, count 0 2006.257.17:14:08.58#ibcon#end of sib2, iclass 29, count 0 2006.257.17:14:08.58#ibcon#*after write, iclass 29, count 0 2006.257.17:14:08.58#ibcon#*before return 0, iclass 29, count 0 2006.257.17:14:08.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:08.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:08.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:14:08.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:14:08.58$vck44/va=1,8 2006.257.17:14:08.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.17:14:08.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.17:14:08.58#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:08.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:08.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:08.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:08.58#ibcon#enter wrdev, iclass 31, count 2 2006.257.17:14:08.58#ibcon#first serial, iclass 31, count 2 2006.257.17:14:08.58#ibcon#enter sib2, iclass 31, count 2 2006.257.17:14:08.58#ibcon#flushed, iclass 31, count 2 2006.257.17:14:08.58#ibcon#about to write, iclass 31, count 2 2006.257.17:14:08.58#ibcon#wrote, iclass 31, count 2 2006.257.17:14:08.58#ibcon#about to read 3, iclass 31, count 2 2006.257.17:14:08.60#ibcon#read 3, iclass 31, count 2 2006.257.17:14:08.60#ibcon#about to read 4, iclass 31, count 2 2006.257.17:14:08.60#ibcon#read 4, iclass 31, count 2 2006.257.17:14:08.60#ibcon#about to read 5, iclass 31, count 2 2006.257.17:14:08.60#ibcon#read 5, iclass 31, count 2 2006.257.17:14:08.60#ibcon#about to read 6, iclass 31, count 2 2006.257.17:14:08.60#ibcon#read 6, iclass 31, count 2 2006.257.17:14:08.60#ibcon#end of sib2, iclass 31, count 2 2006.257.17:14:08.60#ibcon#*mode == 0, iclass 31, count 2 2006.257.17:14:08.60#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.17:14:08.60#ibcon#[25=AT01-08\r\n] 2006.257.17:14:08.60#ibcon#*before write, iclass 31, count 2 2006.257.17:14:08.60#ibcon#enter sib2, iclass 31, count 2 2006.257.17:14:08.60#ibcon#flushed, iclass 31, count 2 2006.257.17:14:08.60#ibcon#about to write, iclass 31, count 2 2006.257.17:14:08.60#ibcon#wrote, iclass 31, count 2 2006.257.17:14:08.60#ibcon#about to read 3, iclass 31, count 2 2006.257.17:14:08.63#ibcon#read 3, iclass 31, count 2 2006.257.17:14:08.63#ibcon#about to read 4, iclass 31, count 2 2006.257.17:14:08.63#ibcon#read 4, iclass 31, count 2 2006.257.17:14:08.63#ibcon#about to read 5, iclass 31, count 2 2006.257.17:14:08.63#ibcon#read 5, iclass 31, count 2 2006.257.17:14:08.63#ibcon#about to read 6, iclass 31, count 2 2006.257.17:14:08.63#ibcon#read 6, iclass 31, count 2 2006.257.17:14:08.63#ibcon#end of sib2, iclass 31, count 2 2006.257.17:14:08.63#ibcon#*after write, iclass 31, count 2 2006.257.17:14:08.63#ibcon#*before return 0, iclass 31, count 2 2006.257.17:14:08.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:08.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:08.63#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.17:14:08.63#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:08.63#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:08.75#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:08.75#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:08.75#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:14:08.75#ibcon#first serial, iclass 31, count 0 2006.257.17:14:08.75#ibcon#enter sib2, iclass 31, count 0 2006.257.17:14:08.75#ibcon#flushed, iclass 31, count 0 2006.257.17:14:08.75#ibcon#about to write, iclass 31, count 0 2006.257.17:14:08.75#ibcon#wrote, iclass 31, count 0 2006.257.17:14:08.75#ibcon#about to read 3, iclass 31, count 0 2006.257.17:14:08.77#ibcon#read 3, iclass 31, count 0 2006.257.17:14:08.77#ibcon#about to read 4, iclass 31, count 0 2006.257.17:14:08.77#ibcon#read 4, iclass 31, count 0 2006.257.17:14:08.77#ibcon#about to read 5, iclass 31, count 0 2006.257.17:14:08.77#ibcon#read 5, iclass 31, count 0 2006.257.17:14:08.77#ibcon#about to read 6, iclass 31, count 0 2006.257.17:14:08.77#ibcon#read 6, iclass 31, count 0 2006.257.17:14:08.77#ibcon#end of sib2, iclass 31, count 0 2006.257.17:14:08.77#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:14:08.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:14:08.77#ibcon#[25=USB\r\n] 2006.257.17:14:08.77#ibcon#*before write, iclass 31, count 0 2006.257.17:14:08.77#ibcon#enter sib2, iclass 31, count 0 2006.257.17:14:08.77#ibcon#flushed, iclass 31, count 0 2006.257.17:14:08.77#ibcon#about to write, iclass 31, count 0 2006.257.17:14:08.77#ibcon#wrote, iclass 31, count 0 2006.257.17:14:08.77#ibcon#about to read 3, iclass 31, count 0 2006.257.17:14:08.80#ibcon#read 3, iclass 31, count 0 2006.257.17:14:08.80#ibcon#about to read 4, iclass 31, count 0 2006.257.17:14:08.80#ibcon#read 4, iclass 31, count 0 2006.257.17:14:08.80#ibcon#about to read 5, iclass 31, count 0 2006.257.17:14:08.80#ibcon#read 5, iclass 31, count 0 2006.257.17:14:08.80#ibcon#about to read 6, iclass 31, count 0 2006.257.17:14:08.80#ibcon#read 6, iclass 31, count 0 2006.257.17:14:08.80#ibcon#end of sib2, iclass 31, count 0 2006.257.17:14:08.80#ibcon#*after write, iclass 31, count 0 2006.257.17:14:08.80#ibcon#*before return 0, iclass 31, count 0 2006.257.17:14:08.80#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:08.80#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:08.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:14:08.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:14:08.80$vck44/valo=2,534.99 2006.257.17:14:08.80#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.17:14:08.80#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.17:14:08.80#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:08.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:08.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:08.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:08.80#ibcon#enter wrdev, iclass 33, count 0 2006.257.17:14:08.80#ibcon#first serial, iclass 33, count 0 2006.257.17:14:08.80#ibcon#enter sib2, iclass 33, count 0 2006.257.17:14:08.80#ibcon#flushed, iclass 33, count 0 2006.257.17:14:08.80#ibcon#about to write, iclass 33, count 0 2006.257.17:14:08.80#ibcon#wrote, iclass 33, count 0 2006.257.17:14:08.80#ibcon#about to read 3, iclass 33, count 0 2006.257.17:14:08.82#ibcon#read 3, iclass 33, count 0 2006.257.17:14:08.82#ibcon#about to read 4, iclass 33, count 0 2006.257.17:14:08.82#ibcon#read 4, iclass 33, count 0 2006.257.17:14:08.82#ibcon#about to read 5, iclass 33, count 0 2006.257.17:14:08.82#ibcon#read 5, iclass 33, count 0 2006.257.17:14:08.82#ibcon#about to read 6, iclass 33, count 0 2006.257.17:14:08.82#ibcon#read 6, iclass 33, count 0 2006.257.17:14:08.82#ibcon#end of sib2, iclass 33, count 0 2006.257.17:14:08.82#ibcon#*mode == 0, iclass 33, count 0 2006.257.17:14:08.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.17:14:08.82#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:14:08.82#ibcon#*before write, iclass 33, count 0 2006.257.17:14:08.82#ibcon#enter sib2, iclass 33, count 0 2006.257.17:14:08.82#ibcon#flushed, iclass 33, count 0 2006.257.17:14:08.82#ibcon#about to write, iclass 33, count 0 2006.257.17:14:08.82#ibcon#wrote, iclass 33, count 0 2006.257.17:14:08.82#ibcon#about to read 3, iclass 33, count 0 2006.257.17:14:08.86#ibcon#read 3, iclass 33, count 0 2006.257.17:14:08.86#ibcon#about to read 4, iclass 33, count 0 2006.257.17:14:08.86#ibcon#read 4, iclass 33, count 0 2006.257.17:14:08.86#ibcon#about to read 5, iclass 33, count 0 2006.257.17:14:08.86#ibcon#read 5, iclass 33, count 0 2006.257.17:14:08.86#ibcon#about to read 6, iclass 33, count 0 2006.257.17:14:08.86#ibcon#read 6, iclass 33, count 0 2006.257.17:14:08.86#ibcon#end of sib2, iclass 33, count 0 2006.257.17:14:08.86#ibcon#*after write, iclass 33, count 0 2006.257.17:14:08.86#ibcon#*before return 0, iclass 33, count 0 2006.257.17:14:08.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:08.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:08.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.17:14:08.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.17:14:08.86$vck44/va=2,7 2006.257.17:14:08.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.17:14:08.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.17:14:08.86#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:08.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:08.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:08.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:08.92#ibcon#enter wrdev, iclass 35, count 2 2006.257.17:14:08.92#ibcon#first serial, iclass 35, count 2 2006.257.17:14:08.92#ibcon#enter sib2, iclass 35, count 2 2006.257.17:14:08.92#ibcon#flushed, iclass 35, count 2 2006.257.17:14:08.92#ibcon#about to write, iclass 35, count 2 2006.257.17:14:08.92#ibcon#wrote, iclass 35, count 2 2006.257.17:14:08.92#ibcon#about to read 3, iclass 35, count 2 2006.257.17:14:08.94#ibcon#read 3, iclass 35, count 2 2006.257.17:14:08.94#ibcon#about to read 4, iclass 35, count 2 2006.257.17:14:08.94#ibcon#read 4, iclass 35, count 2 2006.257.17:14:08.94#ibcon#about to read 5, iclass 35, count 2 2006.257.17:14:08.94#ibcon#read 5, iclass 35, count 2 2006.257.17:14:08.94#ibcon#about to read 6, iclass 35, count 2 2006.257.17:14:08.94#ibcon#read 6, iclass 35, count 2 2006.257.17:14:08.94#ibcon#end of sib2, iclass 35, count 2 2006.257.17:14:08.94#ibcon#*mode == 0, iclass 35, count 2 2006.257.17:14:08.94#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.17:14:08.94#ibcon#[25=AT02-07\r\n] 2006.257.17:14:08.94#ibcon#*before write, iclass 35, count 2 2006.257.17:14:08.94#ibcon#enter sib2, iclass 35, count 2 2006.257.17:14:08.94#ibcon#flushed, iclass 35, count 2 2006.257.17:14:08.94#ibcon#about to write, iclass 35, count 2 2006.257.17:14:08.94#ibcon#wrote, iclass 35, count 2 2006.257.17:14:08.94#ibcon#about to read 3, iclass 35, count 2 2006.257.17:14:08.97#ibcon#read 3, iclass 35, count 2 2006.257.17:14:08.97#ibcon#about to read 4, iclass 35, count 2 2006.257.17:14:08.97#ibcon#read 4, iclass 35, count 2 2006.257.17:14:08.97#ibcon#about to read 5, iclass 35, count 2 2006.257.17:14:08.97#ibcon#read 5, iclass 35, count 2 2006.257.17:14:08.97#ibcon#about to read 6, iclass 35, count 2 2006.257.17:14:08.97#ibcon#read 6, iclass 35, count 2 2006.257.17:14:08.97#ibcon#end of sib2, iclass 35, count 2 2006.257.17:14:08.97#ibcon#*after write, iclass 35, count 2 2006.257.17:14:08.97#ibcon#*before return 0, iclass 35, count 2 2006.257.17:14:08.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:08.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:08.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.17:14:08.97#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:08.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:09.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:09.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:09.09#ibcon#enter wrdev, iclass 35, count 0 2006.257.17:14:09.09#ibcon#first serial, iclass 35, count 0 2006.257.17:14:09.09#ibcon#enter sib2, iclass 35, count 0 2006.257.17:14:09.09#ibcon#flushed, iclass 35, count 0 2006.257.17:14:09.09#ibcon#about to write, iclass 35, count 0 2006.257.17:14:09.09#ibcon#wrote, iclass 35, count 0 2006.257.17:14:09.09#ibcon#about to read 3, iclass 35, count 0 2006.257.17:14:09.11#ibcon#read 3, iclass 35, count 0 2006.257.17:14:09.11#ibcon#about to read 4, iclass 35, count 0 2006.257.17:14:09.11#ibcon#read 4, iclass 35, count 0 2006.257.17:14:09.11#ibcon#about to read 5, iclass 35, count 0 2006.257.17:14:09.11#ibcon#read 5, iclass 35, count 0 2006.257.17:14:09.11#ibcon#about to read 6, iclass 35, count 0 2006.257.17:14:09.11#ibcon#read 6, iclass 35, count 0 2006.257.17:14:09.11#ibcon#end of sib2, iclass 35, count 0 2006.257.17:14:09.11#ibcon#*mode == 0, iclass 35, count 0 2006.257.17:14:09.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.17:14:09.11#ibcon#[25=USB\r\n] 2006.257.17:14:09.11#ibcon#*before write, iclass 35, count 0 2006.257.17:14:09.11#ibcon#enter sib2, iclass 35, count 0 2006.257.17:14:09.11#ibcon#flushed, iclass 35, count 0 2006.257.17:14:09.11#ibcon#about to write, iclass 35, count 0 2006.257.17:14:09.11#ibcon#wrote, iclass 35, count 0 2006.257.17:14:09.11#ibcon#about to read 3, iclass 35, count 0 2006.257.17:14:09.14#ibcon#read 3, iclass 35, count 0 2006.257.17:14:09.14#ibcon#about to read 4, iclass 35, count 0 2006.257.17:14:09.14#ibcon#read 4, iclass 35, count 0 2006.257.17:14:09.14#ibcon#about to read 5, iclass 35, count 0 2006.257.17:14:09.14#ibcon#read 5, iclass 35, count 0 2006.257.17:14:09.14#ibcon#about to read 6, iclass 35, count 0 2006.257.17:14:09.14#ibcon#read 6, iclass 35, count 0 2006.257.17:14:09.14#ibcon#end of sib2, iclass 35, count 0 2006.257.17:14:09.14#ibcon#*after write, iclass 35, count 0 2006.257.17:14:09.14#ibcon#*before return 0, iclass 35, count 0 2006.257.17:14:09.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:09.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:09.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.17:14:09.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.17:14:09.14$vck44/valo=3,564.99 2006.257.17:14:09.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.17:14:09.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.17:14:09.14#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:09.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:09.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:09.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:09.14#ibcon#enter wrdev, iclass 37, count 0 2006.257.17:14:09.14#ibcon#first serial, iclass 37, count 0 2006.257.17:14:09.14#ibcon#enter sib2, iclass 37, count 0 2006.257.17:14:09.14#ibcon#flushed, iclass 37, count 0 2006.257.17:14:09.14#ibcon#about to write, iclass 37, count 0 2006.257.17:14:09.14#ibcon#wrote, iclass 37, count 0 2006.257.17:14:09.14#ibcon#about to read 3, iclass 37, count 0 2006.257.17:14:09.16#ibcon#read 3, iclass 37, count 0 2006.257.17:14:09.16#ibcon#about to read 4, iclass 37, count 0 2006.257.17:14:09.16#ibcon#read 4, iclass 37, count 0 2006.257.17:14:09.16#ibcon#about to read 5, iclass 37, count 0 2006.257.17:14:09.16#ibcon#read 5, iclass 37, count 0 2006.257.17:14:09.16#ibcon#about to read 6, iclass 37, count 0 2006.257.17:14:09.16#ibcon#read 6, iclass 37, count 0 2006.257.17:14:09.16#ibcon#end of sib2, iclass 37, count 0 2006.257.17:14:09.16#ibcon#*mode == 0, iclass 37, count 0 2006.257.17:14:09.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.17:14:09.16#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:14:09.16#ibcon#*before write, iclass 37, count 0 2006.257.17:14:09.16#ibcon#enter sib2, iclass 37, count 0 2006.257.17:14:09.16#ibcon#flushed, iclass 37, count 0 2006.257.17:14:09.16#ibcon#about to write, iclass 37, count 0 2006.257.17:14:09.16#ibcon#wrote, iclass 37, count 0 2006.257.17:14:09.16#ibcon#about to read 3, iclass 37, count 0 2006.257.17:14:09.20#ibcon#read 3, iclass 37, count 0 2006.257.17:14:09.20#ibcon#about to read 4, iclass 37, count 0 2006.257.17:14:09.20#ibcon#read 4, iclass 37, count 0 2006.257.17:14:09.20#ibcon#about to read 5, iclass 37, count 0 2006.257.17:14:09.20#ibcon#read 5, iclass 37, count 0 2006.257.17:14:09.20#ibcon#about to read 6, iclass 37, count 0 2006.257.17:14:09.20#ibcon#read 6, iclass 37, count 0 2006.257.17:14:09.20#ibcon#end of sib2, iclass 37, count 0 2006.257.17:14:09.20#ibcon#*after write, iclass 37, count 0 2006.257.17:14:09.20#ibcon#*before return 0, iclass 37, count 0 2006.257.17:14:09.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:09.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:09.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.17:14:09.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.17:14:09.20$vck44/va=3,8 2006.257.17:14:09.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.17:14:09.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.17:14:09.20#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:09.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:09.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:09.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:09.26#ibcon#enter wrdev, iclass 39, count 2 2006.257.17:14:09.26#ibcon#first serial, iclass 39, count 2 2006.257.17:14:09.26#ibcon#enter sib2, iclass 39, count 2 2006.257.17:14:09.26#ibcon#flushed, iclass 39, count 2 2006.257.17:14:09.26#ibcon#about to write, iclass 39, count 2 2006.257.17:14:09.26#ibcon#wrote, iclass 39, count 2 2006.257.17:14:09.26#ibcon#about to read 3, iclass 39, count 2 2006.257.17:14:09.28#ibcon#read 3, iclass 39, count 2 2006.257.17:14:09.28#ibcon#about to read 4, iclass 39, count 2 2006.257.17:14:09.28#ibcon#read 4, iclass 39, count 2 2006.257.17:14:09.28#ibcon#about to read 5, iclass 39, count 2 2006.257.17:14:09.28#ibcon#read 5, iclass 39, count 2 2006.257.17:14:09.28#ibcon#about to read 6, iclass 39, count 2 2006.257.17:14:09.28#ibcon#read 6, iclass 39, count 2 2006.257.17:14:09.28#ibcon#end of sib2, iclass 39, count 2 2006.257.17:14:09.28#ibcon#*mode == 0, iclass 39, count 2 2006.257.17:14:09.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.17:14:09.28#ibcon#[25=AT03-08\r\n] 2006.257.17:14:09.28#ibcon#*before write, iclass 39, count 2 2006.257.17:14:09.28#ibcon#enter sib2, iclass 39, count 2 2006.257.17:14:09.28#ibcon#flushed, iclass 39, count 2 2006.257.17:14:09.28#ibcon#about to write, iclass 39, count 2 2006.257.17:14:09.28#ibcon#wrote, iclass 39, count 2 2006.257.17:14:09.28#ibcon#about to read 3, iclass 39, count 2 2006.257.17:14:09.31#ibcon#read 3, iclass 39, count 2 2006.257.17:14:09.31#ibcon#about to read 4, iclass 39, count 2 2006.257.17:14:09.31#ibcon#read 4, iclass 39, count 2 2006.257.17:14:09.31#ibcon#about to read 5, iclass 39, count 2 2006.257.17:14:09.31#ibcon#read 5, iclass 39, count 2 2006.257.17:14:09.31#ibcon#about to read 6, iclass 39, count 2 2006.257.17:14:09.31#ibcon#read 6, iclass 39, count 2 2006.257.17:14:09.31#ibcon#end of sib2, iclass 39, count 2 2006.257.17:14:09.31#ibcon#*after write, iclass 39, count 2 2006.257.17:14:09.31#ibcon#*before return 0, iclass 39, count 2 2006.257.17:14:09.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:09.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:09.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.17:14:09.31#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:09.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:09.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:09.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:09.43#ibcon#enter wrdev, iclass 39, count 0 2006.257.17:14:09.43#ibcon#first serial, iclass 39, count 0 2006.257.17:14:09.43#ibcon#enter sib2, iclass 39, count 0 2006.257.17:14:09.43#ibcon#flushed, iclass 39, count 0 2006.257.17:14:09.43#ibcon#about to write, iclass 39, count 0 2006.257.17:14:09.43#ibcon#wrote, iclass 39, count 0 2006.257.17:14:09.43#ibcon#about to read 3, iclass 39, count 0 2006.257.17:14:09.45#ibcon#read 3, iclass 39, count 0 2006.257.17:14:09.45#ibcon#about to read 4, iclass 39, count 0 2006.257.17:14:09.45#ibcon#read 4, iclass 39, count 0 2006.257.17:14:09.45#ibcon#about to read 5, iclass 39, count 0 2006.257.17:14:09.45#ibcon#read 5, iclass 39, count 0 2006.257.17:14:09.45#ibcon#about to read 6, iclass 39, count 0 2006.257.17:14:09.45#ibcon#read 6, iclass 39, count 0 2006.257.17:14:09.45#ibcon#end of sib2, iclass 39, count 0 2006.257.17:14:09.45#ibcon#*mode == 0, iclass 39, count 0 2006.257.17:14:09.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.17:14:09.45#ibcon#[25=USB\r\n] 2006.257.17:14:09.45#ibcon#*before write, iclass 39, count 0 2006.257.17:14:09.45#ibcon#enter sib2, iclass 39, count 0 2006.257.17:14:09.45#ibcon#flushed, iclass 39, count 0 2006.257.17:14:09.45#ibcon#about to write, iclass 39, count 0 2006.257.17:14:09.45#ibcon#wrote, iclass 39, count 0 2006.257.17:14:09.45#ibcon#about to read 3, iclass 39, count 0 2006.257.17:14:09.48#ibcon#read 3, iclass 39, count 0 2006.257.17:14:09.48#ibcon#about to read 4, iclass 39, count 0 2006.257.17:14:09.48#ibcon#read 4, iclass 39, count 0 2006.257.17:14:09.48#ibcon#about to read 5, iclass 39, count 0 2006.257.17:14:09.48#ibcon#read 5, iclass 39, count 0 2006.257.17:14:09.48#ibcon#about to read 6, iclass 39, count 0 2006.257.17:14:09.48#ibcon#read 6, iclass 39, count 0 2006.257.17:14:09.48#ibcon#end of sib2, iclass 39, count 0 2006.257.17:14:09.48#ibcon#*after write, iclass 39, count 0 2006.257.17:14:09.48#ibcon#*before return 0, iclass 39, count 0 2006.257.17:14:09.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:09.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:09.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.17:14:09.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.17:14:09.48$vck44/valo=4,624.99 2006.257.17:14:09.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.17:14:09.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.17:14:09.48#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:09.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:09.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:09.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:09.48#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:14:09.48#ibcon#first serial, iclass 3, count 0 2006.257.17:14:09.48#ibcon#enter sib2, iclass 3, count 0 2006.257.17:14:09.48#ibcon#flushed, iclass 3, count 0 2006.257.17:14:09.48#ibcon#about to write, iclass 3, count 0 2006.257.17:14:09.48#ibcon#wrote, iclass 3, count 0 2006.257.17:14:09.48#ibcon#about to read 3, iclass 3, count 0 2006.257.17:14:09.50#ibcon#read 3, iclass 3, count 0 2006.257.17:14:09.50#ibcon#about to read 4, iclass 3, count 0 2006.257.17:14:09.50#ibcon#read 4, iclass 3, count 0 2006.257.17:14:09.50#ibcon#about to read 5, iclass 3, count 0 2006.257.17:14:09.50#ibcon#read 5, iclass 3, count 0 2006.257.17:14:09.50#ibcon#about to read 6, iclass 3, count 0 2006.257.17:14:09.50#ibcon#read 6, iclass 3, count 0 2006.257.17:14:09.50#ibcon#end of sib2, iclass 3, count 0 2006.257.17:14:09.50#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:14:09.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:14:09.50#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:14:09.50#ibcon#*before write, iclass 3, count 0 2006.257.17:14:09.50#ibcon#enter sib2, iclass 3, count 0 2006.257.17:14:09.50#ibcon#flushed, iclass 3, count 0 2006.257.17:14:09.50#ibcon#about to write, iclass 3, count 0 2006.257.17:14:09.50#ibcon#wrote, iclass 3, count 0 2006.257.17:14:09.50#ibcon#about to read 3, iclass 3, count 0 2006.257.17:14:09.54#ibcon#read 3, iclass 3, count 0 2006.257.17:14:09.54#ibcon#about to read 4, iclass 3, count 0 2006.257.17:14:09.54#ibcon#read 4, iclass 3, count 0 2006.257.17:14:09.54#ibcon#about to read 5, iclass 3, count 0 2006.257.17:14:09.54#ibcon#read 5, iclass 3, count 0 2006.257.17:14:09.54#ibcon#about to read 6, iclass 3, count 0 2006.257.17:14:09.54#ibcon#read 6, iclass 3, count 0 2006.257.17:14:09.54#ibcon#end of sib2, iclass 3, count 0 2006.257.17:14:09.54#ibcon#*after write, iclass 3, count 0 2006.257.17:14:09.54#ibcon#*before return 0, iclass 3, count 0 2006.257.17:14:09.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:09.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:09.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:14:09.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:14:09.54$vck44/va=4,7 2006.257.17:14:09.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.17:14:09.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.17:14:09.54#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:09.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:09.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:09.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:09.60#ibcon#enter wrdev, iclass 5, count 2 2006.257.17:14:09.60#ibcon#first serial, iclass 5, count 2 2006.257.17:14:09.60#ibcon#enter sib2, iclass 5, count 2 2006.257.17:14:09.60#ibcon#flushed, iclass 5, count 2 2006.257.17:14:09.60#ibcon#about to write, iclass 5, count 2 2006.257.17:14:09.60#ibcon#wrote, iclass 5, count 2 2006.257.17:14:09.60#ibcon#about to read 3, iclass 5, count 2 2006.257.17:14:09.62#ibcon#read 3, iclass 5, count 2 2006.257.17:14:09.62#ibcon#about to read 4, iclass 5, count 2 2006.257.17:14:09.62#ibcon#read 4, iclass 5, count 2 2006.257.17:14:09.62#ibcon#about to read 5, iclass 5, count 2 2006.257.17:14:09.62#ibcon#read 5, iclass 5, count 2 2006.257.17:14:09.62#ibcon#about to read 6, iclass 5, count 2 2006.257.17:14:09.62#ibcon#read 6, iclass 5, count 2 2006.257.17:14:09.62#ibcon#end of sib2, iclass 5, count 2 2006.257.17:14:09.62#ibcon#*mode == 0, iclass 5, count 2 2006.257.17:14:09.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.17:14:09.62#ibcon#[25=AT04-07\r\n] 2006.257.17:14:09.62#ibcon#*before write, iclass 5, count 2 2006.257.17:14:09.62#ibcon#enter sib2, iclass 5, count 2 2006.257.17:14:09.62#ibcon#flushed, iclass 5, count 2 2006.257.17:14:09.62#ibcon#about to write, iclass 5, count 2 2006.257.17:14:09.62#ibcon#wrote, iclass 5, count 2 2006.257.17:14:09.62#ibcon#about to read 3, iclass 5, count 2 2006.257.17:14:09.65#ibcon#read 3, iclass 5, count 2 2006.257.17:14:09.65#ibcon#about to read 4, iclass 5, count 2 2006.257.17:14:09.65#ibcon#read 4, iclass 5, count 2 2006.257.17:14:09.65#ibcon#about to read 5, iclass 5, count 2 2006.257.17:14:09.65#ibcon#read 5, iclass 5, count 2 2006.257.17:14:09.65#ibcon#about to read 6, iclass 5, count 2 2006.257.17:14:09.65#ibcon#read 6, iclass 5, count 2 2006.257.17:14:09.65#ibcon#end of sib2, iclass 5, count 2 2006.257.17:14:09.65#ibcon#*after write, iclass 5, count 2 2006.257.17:14:09.65#ibcon#*before return 0, iclass 5, count 2 2006.257.17:14:09.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:09.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:09.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.17:14:09.65#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:09.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:09.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:09.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:09.77#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:14:09.77#ibcon#first serial, iclass 5, count 0 2006.257.17:14:09.77#ibcon#enter sib2, iclass 5, count 0 2006.257.17:14:09.77#ibcon#flushed, iclass 5, count 0 2006.257.17:14:09.77#ibcon#about to write, iclass 5, count 0 2006.257.17:14:09.77#ibcon#wrote, iclass 5, count 0 2006.257.17:14:09.77#ibcon#about to read 3, iclass 5, count 0 2006.257.17:14:09.79#ibcon#read 3, iclass 5, count 0 2006.257.17:14:09.79#ibcon#about to read 4, iclass 5, count 0 2006.257.17:14:09.79#ibcon#read 4, iclass 5, count 0 2006.257.17:14:09.79#ibcon#about to read 5, iclass 5, count 0 2006.257.17:14:09.79#ibcon#read 5, iclass 5, count 0 2006.257.17:14:09.79#ibcon#about to read 6, iclass 5, count 0 2006.257.17:14:09.79#ibcon#read 6, iclass 5, count 0 2006.257.17:14:09.79#ibcon#end of sib2, iclass 5, count 0 2006.257.17:14:09.79#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:14:09.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:14:09.79#ibcon#[25=USB\r\n] 2006.257.17:14:09.79#ibcon#*before write, iclass 5, count 0 2006.257.17:14:09.79#ibcon#enter sib2, iclass 5, count 0 2006.257.17:14:09.79#ibcon#flushed, iclass 5, count 0 2006.257.17:14:09.79#ibcon#about to write, iclass 5, count 0 2006.257.17:14:09.79#ibcon#wrote, iclass 5, count 0 2006.257.17:14:09.79#ibcon#about to read 3, iclass 5, count 0 2006.257.17:14:09.82#ibcon#read 3, iclass 5, count 0 2006.257.17:14:09.82#ibcon#about to read 4, iclass 5, count 0 2006.257.17:14:09.82#ibcon#read 4, iclass 5, count 0 2006.257.17:14:09.82#ibcon#about to read 5, iclass 5, count 0 2006.257.17:14:09.82#ibcon#read 5, iclass 5, count 0 2006.257.17:14:09.82#ibcon#about to read 6, iclass 5, count 0 2006.257.17:14:09.82#ibcon#read 6, iclass 5, count 0 2006.257.17:14:09.82#ibcon#end of sib2, iclass 5, count 0 2006.257.17:14:09.82#ibcon#*after write, iclass 5, count 0 2006.257.17:14:09.82#ibcon#*before return 0, iclass 5, count 0 2006.257.17:14:09.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:09.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:09.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:14:09.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:14:09.82$vck44/valo=5,734.99 2006.257.17:14:09.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.17:14:09.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.17:14:09.82#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:09.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:09.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:09.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:09.82#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:14:09.82#ibcon#first serial, iclass 7, count 0 2006.257.17:14:09.82#ibcon#enter sib2, iclass 7, count 0 2006.257.17:14:09.82#ibcon#flushed, iclass 7, count 0 2006.257.17:14:09.82#ibcon#about to write, iclass 7, count 0 2006.257.17:14:09.82#ibcon#wrote, iclass 7, count 0 2006.257.17:14:09.82#ibcon#about to read 3, iclass 7, count 0 2006.257.17:14:09.84#ibcon#read 3, iclass 7, count 0 2006.257.17:14:09.84#ibcon#about to read 4, iclass 7, count 0 2006.257.17:14:09.84#ibcon#read 4, iclass 7, count 0 2006.257.17:14:09.84#ibcon#about to read 5, iclass 7, count 0 2006.257.17:14:09.84#ibcon#read 5, iclass 7, count 0 2006.257.17:14:09.84#ibcon#about to read 6, iclass 7, count 0 2006.257.17:14:09.84#ibcon#read 6, iclass 7, count 0 2006.257.17:14:09.84#ibcon#end of sib2, iclass 7, count 0 2006.257.17:14:09.84#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:14:09.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:14:09.84#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:14:09.84#ibcon#*before write, iclass 7, count 0 2006.257.17:14:09.84#ibcon#enter sib2, iclass 7, count 0 2006.257.17:14:09.84#ibcon#flushed, iclass 7, count 0 2006.257.17:14:09.84#ibcon#about to write, iclass 7, count 0 2006.257.17:14:09.84#ibcon#wrote, iclass 7, count 0 2006.257.17:14:09.84#ibcon#about to read 3, iclass 7, count 0 2006.257.17:14:09.88#ibcon#read 3, iclass 7, count 0 2006.257.17:14:09.88#ibcon#about to read 4, iclass 7, count 0 2006.257.17:14:09.88#ibcon#read 4, iclass 7, count 0 2006.257.17:14:09.88#ibcon#about to read 5, iclass 7, count 0 2006.257.17:14:09.88#ibcon#read 5, iclass 7, count 0 2006.257.17:14:09.88#ibcon#about to read 6, iclass 7, count 0 2006.257.17:14:09.88#ibcon#read 6, iclass 7, count 0 2006.257.17:14:09.88#ibcon#end of sib2, iclass 7, count 0 2006.257.17:14:09.88#ibcon#*after write, iclass 7, count 0 2006.257.17:14:09.88#ibcon#*before return 0, iclass 7, count 0 2006.257.17:14:09.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:09.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:09.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:14:09.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:14:09.88$vck44/va=5,4 2006.257.17:14:09.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.17:14:09.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.17:14:09.88#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:09.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:09.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:09.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:09.94#ibcon#enter wrdev, iclass 11, count 2 2006.257.17:14:09.94#ibcon#first serial, iclass 11, count 2 2006.257.17:14:09.94#ibcon#enter sib2, iclass 11, count 2 2006.257.17:14:09.94#ibcon#flushed, iclass 11, count 2 2006.257.17:14:09.94#ibcon#about to write, iclass 11, count 2 2006.257.17:14:09.94#ibcon#wrote, iclass 11, count 2 2006.257.17:14:09.94#ibcon#about to read 3, iclass 11, count 2 2006.257.17:14:09.96#ibcon#read 3, iclass 11, count 2 2006.257.17:14:09.96#ibcon#about to read 4, iclass 11, count 2 2006.257.17:14:09.96#ibcon#read 4, iclass 11, count 2 2006.257.17:14:09.96#ibcon#about to read 5, iclass 11, count 2 2006.257.17:14:09.96#ibcon#read 5, iclass 11, count 2 2006.257.17:14:09.96#ibcon#about to read 6, iclass 11, count 2 2006.257.17:14:09.96#ibcon#read 6, iclass 11, count 2 2006.257.17:14:09.96#ibcon#end of sib2, iclass 11, count 2 2006.257.17:14:09.96#ibcon#*mode == 0, iclass 11, count 2 2006.257.17:14:09.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.17:14:09.96#ibcon#[25=AT05-04\r\n] 2006.257.17:14:09.96#ibcon#*before write, iclass 11, count 2 2006.257.17:14:09.96#ibcon#enter sib2, iclass 11, count 2 2006.257.17:14:09.96#ibcon#flushed, iclass 11, count 2 2006.257.17:14:09.96#ibcon#about to write, iclass 11, count 2 2006.257.17:14:09.96#ibcon#wrote, iclass 11, count 2 2006.257.17:14:09.96#ibcon#about to read 3, iclass 11, count 2 2006.257.17:14:09.99#ibcon#read 3, iclass 11, count 2 2006.257.17:14:09.99#ibcon#about to read 4, iclass 11, count 2 2006.257.17:14:09.99#ibcon#read 4, iclass 11, count 2 2006.257.17:14:09.99#ibcon#about to read 5, iclass 11, count 2 2006.257.17:14:09.99#ibcon#read 5, iclass 11, count 2 2006.257.17:14:09.99#ibcon#about to read 6, iclass 11, count 2 2006.257.17:14:09.99#ibcon#read 6, iclass 11, count 2 2006.257.17:14:09.99#ibcon#end of sib2, iclass 11, count 2 2006.257.17:14:09.99#ibcon#*after write, iclass 11, count 2 2006.257.17:14:09.99#ibcon#*before return 0, iclass 11, count 2 2006.257.17:14:09.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:09.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:09.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.17:14:09.99#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:09.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:10.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:10.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:10.11#ibcon#enter wrdev, iclass 11, count 0 2006.257.17:14:10.11#ibcon#first serial, iclass 11, count 0 2006.257.17:14:10.11#ibcon#enter sib2, iclass 11, count 0 2006.257.17:14:10.11#ibcon#flushed, iclass 11, count 0 2006.257.17:14:10.11#ibcon#about to write, iclass 11, count 0 2006.257.17:14:10.11#ibcon#wrote, iclass 11, count 0 2006.257.17:14:10.11#ibcon#about to read 3, iclass 11, count 0 2006.257.17:14:10.13#ibcon#read 3, iclass 11, count 0 2006.257.17:14:10.13#ibcon#about to read 4, iclass 11, count 0 2006.257.17:14:10.13#ibcon#read 4, iclass 11, count 0 2006.257.17:14:10.13#ibcon#about to read 5, iclass 11, count 0 2006.257.17:14:10.13#ibcon#read 5, iclass 11, count 0 2006.257.17:14:10.13#ibcon#about to read 6, iclass 11, count 0 2006.257.17:14:10.13#ibcon#read 6, iclass 11, count 0 2006.257.17:14:10.13#ibcon#end of sib2, iclass 11, count 0 2006.257.17:14:10.13#ibcon#*mode == 0, iclass 11, count 0 2006.257.17:14:10.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.17:14:10.13#ibcon#[25=USB\r\n] 2006.257.17:14:10.13#ibcon#*before write, iclass 11, count 0 2006.257.17:14:10.13#ibcon#enter sib2, iclass 11, count 0 2006.257.17:14:10.13#ibcon#flushed, iclass 11, count 0 2006.257.17:14:10.13#ibcon#about to write, iclass 11, count 0 2006.257.17:14:10.13#ibcon#wrote, iclass 11, count 0 2006.257.17:14:10.13#ibcon#about to read 3, iclass 11, count 0 2006.257.17:14:10.16#ibcon#read 3, iclass 11, count 0 2006.257.17:14:10.16#ibcon#about to read 4, iclass 11, count 0 2006.257.17:14:10.16#ibcon#read 4, iclass 11, count 0 2006.257.17:14:10.16#ibcon#about to read 5, iclass 11, count 0 2006.257.17:14:10.16#ibcon#read 5, iclass 11, count 0 2006.257.17:14:10.16#ibcon#about to read 6, iclass 11, count 0 2006.257.17:14:10.16#ibcon#read 6, iclass 11, count 0 2006.257.17:14:10.16#ibcon#end of sib2, iclass 11, count 0 2006.257.17:14:10.16#ibcon#*after write, iclass 11, count 0 2006.257.17:14:10.16#ibcon#*before return 0, iclass 11, count 0 2006.257.17:14:10.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:10.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:10.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.17:14:10.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.17:14:10.16$vck44/valo=6,814.99 2006.257.17:14:10.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.17:14:10.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.17:14:10.16#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:10.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:10.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:10.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:10.16#ibcon#enter wrdev, iclass 13, count 0 2006.257.17:14:10.16#ibcon#first serial, iclass 13, count 0 2006.257.17:14:10.16#ibcon#enter sib2, iclass 13, count 0 2006.257.17:14:10.16#ibcon#flushed, iclass 13, count 0 2006.257.17:14:10.16#ibcon#about to write, iclass 13, count 0 2006.257.17:14:10.16#ibcon#wrote, iclass 13, count 0 2006.257.17:14:10.16#ibcon#about to read 3, iclass 13, count 0 2006.257.17:14:10.18#ibcon#read 3, iclass 13, count 0 2006.257.17:14:10.18#ibcon#about to read 4, iclass 13, count 0 2006.257.17:14:10.18#ibcon#read 4, iclass 13, count 0 2006.257.17:14:10.18#ibcon#about to read 5, iclass 13, count 0 2006.257.17:14:10.18#ibcon#read 5, iclass 13, count 0 2006.257.17:14:10.18#ibcon#about to read 6, iclass 13, count 0 2006.257.17:14:10.18#ibcon#read 6, iclass 13, count 0 2006.257.17:14:10.18#ibcon#end of sib2, iclass 13, count 0 2006.257.17:14:10.18#ibcon#*mode == 0, iclass 13, count 0 2006.257.17:14:10.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.17:14:10.18#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:14:10.18#ibcon#*before write, iclass 13, count 0 2006.257.17:14:10.18#ibcon#enter sib2, iclass 13, count 0 2006.257.17:14:10.18#ibcon#flushed, iclass 13, count 0 2006.257.17:14:10.18#ibcon#about to write, iclass 13, count 0 2006.257.17:14:10.18#ibcon#wrote, iclass 13, count 0 2006.257.17:14:10.18#ibcon#about to read 3, iclass 13, count 0 2006.257.17:14:10.22#ibcon#read 3, iclass 13, count 0 2006.257.17:14:10.22#ibcon#about to read 4, iclass 13, count 0 2006.257.17:14:10.22#ibcon#read 4, iclass 13, count 0 2006.257.17:14:10.22#ibcon#about to read 5, iclass 13, count 0 2006.257.17:14:10.22#ibcon#read 5, iclass 13, count 0 2006.257.17:14:10.22#ibcon#about to read 6, iclass 13, count 0 2006.257.17:14:10.22#ibcon#read 6, iclass 13, count 0 2006.257.17:14:10.22#ibcon#end of sib2, iclass 13, count 0 2006.257.17:14:10.22#ibcon#*after write, iclass 13, count 0 2006.257.17:14:10.22#ibcon#*before return 0, iclass 13, count 0 2006.257.17:14:10.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:10.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:10.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.17:14:10.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.17:14:10.22$vck44/va=6,4 2006.257.17:14:10.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.17:14:10.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.17:14:10.22#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:10.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:10.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:10.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:10.28#ibcon#enter wrdev, iclass 15, count 2 2006.257.17:14:10.28#ibcon#first serial, iclass 15, count 2 2006.257.17:14:10.28#ibcon#enter sib2, iclass 15, count 2 2006.257.17:14:10.28#ibcon#flushed, iclass 15, count 2 2006.257.17:14:10.28#ibcon#about to write, iclass 15, count 2 2006.257.17:14:10.28#ibcon#wrote, iclass 15, count 2 2006.257.17:14:10.28#ibcon#about to read 3, iclass 15, count 2 2006.257.17:14:10.30#ibcon#read 3, iclass 15, count 2 2006.257.17:14:10.30#ibcon#about to read 4, iclass 15, count 2 2006.257.17:14:10.30#ibcon#read 4, iclass 15, count 2 2006.257.17:14:10.30#ibcon#about to read 5, iclass 15, count 2 2006.257.17:14:10.30#ibcon#read 5, iclass 15, count 2 2006.257.17:14:10.30#ibcon#about to read 6, iclass 15, count 2 2006.257.17:14:10.30#ibcon#read 6, iclass 15, count 2 2006.257.17:14:10.30#ibcon#end of sib2, iclass 15, count 2 2006.257.17:14:10.30#ibcon#*mode == 0, iclass 15, count 2 2006.257.17:14:10.30#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.17:14:10.30#ibcon#[25=AT06-04\r\n] 2006.257.17:14:10.30#ibcon#*before write, iclass 15, count 2 2006.257.17:14:10.30#ibcon#enter sib2, iclass 15, count 2 2006.257.17:14:10.30#ibcon#flushed, iclass 15, count 2 2006.257.17:14:10.30#ibcon#about to write, iclass 15, count 2 2006.257.17:14:10.30#ibcon#wrote, iclass 15, count 2 2006.257.17:14:10.30#ibcon#about to read 3, iclass 15, count 2 2006.257.17:14:10.33#ibcon#read 3, iclass 15, count 2 2006.257.17:14:10.33#ibcon#about to read 4, iclass 15, count 2 2006.257.17:14:10.33#ibcon#read 4, iclass 15, count 2 2006.257.17:14:10.33#ibcon#about to read 5, iclass 15, count 2 2006.257.17:14:10.33#ibcon#read 5, iclass 15, count 2 2006.257.17:14:10.33#ibcon#about to read 6, iclass 15, count 2 2006.257.17:14:10.33#ibcon#read 6, iclass 15, count 2 2006.257.17:14:10.33#ibcon#end of sib2, iclass 15, count 2 2006.257.17:14:10.33#ibcon#*after write, iclass 15, count 2 2006.257.17:14:10.33#ibcon#*before return 0, iclass 15, count 2 2006.257.17:14:10.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:10.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:10.33#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.17:14:10.33#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:10.33#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:10.45#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:10.45#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:10.45#ibcon#enter wrdev, iclass 15, count 0 2006.257.17:14:10.45#ibcon#first serial, iclass 15, count 0 2006.257.17:14:10.45#ibcon#enter sib2, iclass 15, count 0 2006.257.17:14:10.45#ibcon#flushed, iclass 15, count 0 2006.257.17:14:10.45#ibcon#about to write, iclass 15, count 0 2006.257.17:14:10.45#ibcon#wrote, iclass 15, count 0 2006.257.17:14:10.45#ibcon#about to read 3, iclass 15, count 0 2006.257.17:14:10.47#ibcon#read 3, iclass 15, count 0 2006.257.17:14:10.47#ibcon#about to read 4, iclass 15, count 0 2006.257.17:14:10.47#ibcon#read 4, iclass 15, count 0 2006.257.17:14:10.47#ibcon#about to read 5, iclass 15, count 0 2006.257.17:14:10.47#ibcon#read 5, iclass 15, count 0 2006.257.17:14:10.47#ibcon#about to read 6, iclass 15, count 0 2006.257.17:14:10.47#ibcon#read 6, iclass 15, count 0 2006.257.17:14:10.47#ibcon#end of sib2, iclass 15, count 0 2006.257.17:14:10.47#ibcon#*mode == 0, iclass 15, count 0 2006.257.17:14:10.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.17:14:10.47#ibcon#[25=USB\r\n] 2006.257.17:14:10.47#ibcon#*before write, iclass 15, count 0 2006.257.17:14:10.47#ibcon#enter sib2, iclass 15, count 0 2006.257.17:14:10.47#ibcon#flushed, iclass 15, count 0 2006.257.17:14:10.47#ibcon#about to write, iclass 15, count 0 2006.257.17:14:10.47#ibcon#wrote, iclass 15, count 0 2006.257.17:14:10.47#ibcon#about to read 3, iclass 15, count 0 2006.257.17:14:10.50#ibcon#read 3, iclass 15, count 0 2006.257.17:14:10.50#ibcon#about to read 4, iclass 15, count 0 2006.257.17:14:10.50#ibcon#read 4, iclass 15, count 0 2006.257.17:14:10.50#ibcon#about to read 5, iclass 15, count 0 2006.257.17:14:10.50#ibcon#read 5, iclass 15, count 0 2006.257.17:14:10.50#ibcon#about to read 6, iclass 15, count 0 2006.257.17:14:10.50#ibcon#read 6, iclass 15, count 0 2006.257.17:14:10.50#ibcon#end of sib2, iclass 15, count 0 2006.257.17:14:10.50#ibcon#*after write, iclass 15, count 0 2006.257.17:14:10.50#ibcon#*before return 0, iclass 15, count 0 2006.257.17:14:10.50#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:10.50#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:10.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.17:14:10.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.17:14:10.50$vck44/valo=7,864.99 2006.257.17:14:10.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.17:14:10.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.17:14:10.50#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:10.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:10.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:10.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:10.50#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:14:10.50#ibcon#first serial, iclass 17, count 0 2006.257.17:14:10.50#ibcon#enter sib2, iclass 17, count 0 2006.257.17:14:10.50#ibcon#flushed, iclass 17, count 0 2006.257.17:14:10.50#ibcon#about to write, iclass 17, count 0 2006.257.17:14:10.50#ibcon#wrote, iclass 17, count 0 2006.257.17:14:10.50#ibcon#about to read 3, iclass 17, count 0 2006.257.17:14:10.52#ibcon#read 3, iclass 17, count 0 2006.257.17:14:10.52#ibcon#about to read 4, iclass 17, count 0 2006.257.17:14:10.52#ibcon#read 4, iclass 17, count 0 2006.257.17:14:10.52#ibcon#about to read 5, iclass 17, count 0 2006.257.17:14:10.52#ibcon#read 5, iclass 17, count 0 2006.257.17:14:10.52#ibcon#about to read 6, iclass 17, count 0 2006.257.17:14:10.52#ibcon#read 6, iclass 17, count 0 2006.257.17:14:10.52#ibcon#end of sib2, iclass 17, count 0 2006.257.17:14:10.52#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:14:10.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:14:10.52#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:14:10.52#ibcon#*before write, iclass 17, count 0 2006.257.17:14:10.52#ibcon#enter sib2, iclass 17, count 0 2006.257.17:14:10.52#ibcon#flushed, iclass 17, count 0 2006.257.17:14:10.52#ibcon#about to write, iclass 17, count 0 2006.257.17:14:10.52#ibcon#wrote, iclass 17, count 0 2006.257.17:14:10.52#ibcon#about to read 3, iclass 17, count 0 2006.257.17:14:10.56#ibcon#read 3, iclass 17, count 0 2006.257.17:14:10.56#ibcon#about to read 4, iclass 17, count 0 2006.257.17:14:10.56#ibcon#read 4, iclass 17, count 0 2006.257.17:14:10.56#ibcon#about to read 5, iclass 17, count 0 2006.257.17:14:10.56#ibcon#read 5, iclass 17, count 0 2006.257.17:14:10.56#ibcon#about to read 6, iclass 17, count 0 2006.257.17:14:10.56#ibcon#read 6, iclass 17, count 0 2006.257.17:14:10.56#ibcon#end of sib2, iclass 17, count 0 2006.257.17:14:10.56#ibcon#*after write, iclass 17, count 0 2006.257.17:14:10.56#ibcon#*before return 0, iclass 17, count 0 2006.257.17:14:10.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:10.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:10.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:14:10.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:14:10.56$vck44/va=7,4 2006.257.17:14:10.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.17:14:10.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.17:14:10.56#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:10.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:10.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:10.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:10.62#ibcon#enter wrdev, iclass 19, count 2 2006.257.17:14:10.62#ibcon#first serial, iclass 19, count 2 2006.257.17:14:10.62#ibcon#enter sib2, iclass 19, count 2 2006.257.17:14:10.62#ibcon#flushed, iclass 19, count 2 2006.257.17:14:10.62#ibcon#about to write, iclass 19, count 2 2006.257.17:14:10.62#ibcon#wrote, iclass 19, count 2 2006.257.17:14:10.62#ibcon#about to read 3, iclass 19, count 2 2006.257.17:14:10.64#ibcon#read 3, iclass 19, count 2 2006.257.17:14:10.64#ibcon#about to read 4, iclass 19, count 2 2006.257.17:14:10.64#ibcon#read 4, iclass 19, count 2 2006.257.17:14:10.64#ibcon#about to read 5, iclass 19, count 2 2006.257.17:14:10.64#ibcon#read 5, iclass 19, count 2 2006.257.17:14:10.64#ibcon#about to read 6, iclass 19, count 2 2006.257.17:14:10.64#ibcon#read 6, iclass 19, count 2 2006.257.17:14:10.64#ibcon#end of sib2, iclass 19, count 2 2006.257.17:14:10.64#ibcon#*mode == 0, iclass 19, count 2 2006.257.17:14:10.64#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.17:14:10.64#ibcon#[25=AT07-04\r\n] 2006.257.17:14:10.64#ibcon#*before write, iclass 19, count 2 2006.257.17:14:10.64#ibcon#enter sib2, iclass 19, count 2 2006.257.17:14:10.64#ibcon#flushed, iclass 19, count 2 2006.257.17:14:10.64#ibcon#about to write, iclass 19, count 2 2006.257.17:14:10.64#ibcon#wrote, iclass 19, count 2 2006.257.17:14:10.64#ibcon#about to read 3, iclass 19, count 2 2006.257.17:14:10.67#ibcon#read 3, iclass 19, count 2 2006.257.17:14:10.67#ibcon#about to read 4, iclass 19, count 2 2006.257.17:14:10.67#ibcon#read 4, iclass 19, count 2 2006.257.17:14:10.67#ibcon#about to read 5, iclass 19, count 2 2006.257.17:14:10.67#ibcon#read 5, iclass 19, count 2 2006.257.17:14:10.67#ibcon#about to read 6, iclass 19, count 2 2006.257.17:14:10.67#ibcon#read 6, iclass 19, count 2 2006.257.17:14:10.67#ibcon#end of sib2, iclass 19, count 2 2006.257.17:14:10.67#ibcon#*after write, iclass 19, count 2 2006.257.17:14:10.67#ibcon#*before return 0, iclass 19, count 2 2006.257.17:14:10.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:10.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:10.67#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.17:14:10.67#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:10.67#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:10.79#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:10.79#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:10.79#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:14:10.79#ibcon#first serial, iclass 19, count 0 2006.257.17:14:10.79#ibcon#enter sib2, iclass 19, count 0 2006.257.17:14:10.79#ibcon#flushed, iclass 19, count 0 2006.257.17:14:10.79#ibcon#about to write, iclass 19, count 0 2006.257.17:14:10.79#ibcon#wrote, iclass 19, count 0 2006.257.17:14:10.79#ibcon#about to read 3, iclass 19, count 0 2006.257.17:14:10.81#ibcon#read 3, iclass 19, count 0 2006.257.17:14:10.81#ibcon#about to read 4, iclass 19, count 0 2006.257.17:14:10.81#ibcon#read 4, iclass 19, count 0 2006.257.17:14:10.81#ibcon#about to read 5, iclass 19, count 0 2006.257.17:14:10.81#ibcon#read 5, iclass 19, count 0 2006.257.17:14:10.81#ibcon#about to read 6, iclass 19, count 0 2006.257.17:14:10.81#ibcon#read 6, iclass 19, count 0 2006.257.17:14:10.81#ibcon#end of sib2, iclass 19, count 0 2006.257.17:14:10.81#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:14:10.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:14:10.81#ibcon#[25=USB\r\n] 2006.257.17:14:10.81#ibcon#*before write, iclass 19, count 0 2006.257.17:14:10.81#ibcon#enter sib2, iclass 19, count 0 2006.257.17:14:10.81#ibcon#flushed, iclass 19, count 0 2006.257.17:14:10.81#ibcon#about to write, iclass 19, count 0 2006.257.17:14:10.81#ibcon#wrote, iclass 19, count 0 2006.257.17:14:10.81#ibcon#about to read 3, iclass 19, count 0 2006.257.17:14:10.84#ibcon#read 3, iclass 19, count 0 2006.257.17:14:10.84#ibcon#about to read 4, iclass 19, count 0 2006.257.17:14:10.84#ibcon#read 4, iclass 19, count 0 2006.257.17:14:10.84#ibcon#about to read 5, iclass 19, count 0 2006.257.17:14:10.84#ibcon#read 5, iclass 19, count 0 2006.257.17:14:10.84#ibcon#about to read 6, iclass 19, count 0 2006.257.17:14:10.84#ibcon#read 6, iclass 19, count 0 2006.257.17:14:10.84#ibcon#end of sib2, iclass 19, count 0 2006.257.17:14:10.84#ibcon#*after write, iclass 19, count 0 2006.257.17:14:10.84#ibcon#*before return 0, iclass 19, count 0 2006.257.17:14:10.84#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:10.84#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:10.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:14:10.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:14:10.84$vck44/valo=8,884.99 2006.257.17:14:10.84#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.17:14:10.84#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.17:14:10.84#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:10.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:10.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:10.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:10.84#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:14:10.84#ibcon#first serial, iclass 21, count 0 2006.257.17:14:10.84#ibcon#enter sib2, iclass 21, count 0 2006.257.17:14:10.84#ibcon#flushed, iclass 21, count 0 2006.257.17:14:10.84#ibcon#about to write, iclass 21, count 0 2006.257.17:14:10.84#ibcon#wrote, iclass 21, count 0 2006.257.17:14:10.84#ibcon#about to read 3, iclass 21, count 0 2006.257.17:14:10.86#ibcon#read 3, iclass 21, count 0 2006.257.17:14:10.86#ibcon#about to read 4, iclass 21, count 0 2006.257.17:14:10.86#ibcon#read 4, iclass 21, count 0 2006.257.17:14:10.86#ibcon#about to read 5, iclass 21, count 0 2006.257.17:14:10.86#ibcon#read 5, iclass 21, count 0 2006.257.17:14:10.86#ibcon#about to read 6, iclass 21, count 0 2006.257.17:14:10.86#ibcon#read 6, iclass 21, count 0 2006.257.17:14:10.86#ibcon#end of sib2, iclass 21, count 0 2006.257.17:14:10.86#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:14:10.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:14:10.86#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:14:10.86#ibcon#*before write, iclass 21, count 0 2006.257.17:14:10.86#ibcon#enter sib2, iclass 21, count 0 2006.257.17:14:10.86#ibcon#flushed, iclass 21, count 0 2006.257.17:14:10.86#ibcon#about to write, iclass 21, count 0 2006.257.17:14:10.86#ibcon#wrote, iclass 21, count 0 2006.257.17:14:10.86#ibcon#about to read 3, iclass 21, count 0 2006.257.17:14:10.90#ibcon#read 3, iclass 21, count 0 2006.257.17:14:10.90#ibcon#about to read 4, iclass 21, count 0 2006.257.17:14:10.90#ibcon#read 4, iclass 21, count 0 2006.257.17:14:10.90#ibcon#about to read 5, iclass 21, count 0 2006.257.17:14:10.90#ibcon#read 5, iclass 21, count 0 2006.257.17:14:10.90#ibcon#about to read 6, iclass 21, count 0 2006.257.17:14:10.90#ibcon#read 6, iclass 21, count 0 2006.257.17:14:10.90#ibcon#end of sib2, iclass 21, count 0 2006.257.17:14:10.90#ibcon#*after write, iclass 21, count 0 2006.257.17:14:10.90#ibcon#*before return 0, iclass 21, count 0 2006.257.17:14:10.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:10.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:10.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:14:10.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:14:10.90$vck44/va=8,4 2006.257.17:14:10.90#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.17:14:10.90#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.17:14:10.90#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:10.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:14:10.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:14:10.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:14:10.96#ibcon#enter wrdev, iclass 23, count 2 2006.257.17:14:10.96#ibcon#first serial, iclass 23, count 2 2006.257.17:14:10.96#ibcon#enter sib2, iclass 23, count 2 2006.257.17:14:10.96#ibcon#flushed, iclass 23, count 2 2006.257.17:14:10.96#ibcon#about to write, iclass 23, count 2 2006.257.17:14:10.96#ibcon#wrote, iclass 23, count 2 2006.257.17:14:10.96#ibcon#about to read 3, iclass 23, count 2 2006.257.17:14:10.98#ibcon#read 3, iclass 23, count 2 2006.257.17:14:10.98#ibcon#about to read 4, iclass 23, count 2 2006.257.17:14:10.98#ibcon#read 4, iclass 23, count 2 2006.257.17:14:10.98#ibcon#about to read 5, iclass 23, count 2 2006.257.17:14:10.98#ibcon#read 5, iclass 23, count 2 2006.257.17:14:10.98#ibcon#about to read 6, iclass 23, count 2 2006.257.17:14:10.98#ibcon#read 6, iclass 23, count 2 2006.257.17:14:10.98#ibcon#end of sib2, iclass 23, count 2 2006.257.17:14:10.98#ibcon#*mode == 0, iclass 23, count 2 2006.257.17:14:10.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.17:14:10.98#ibcon#[25=AT08-04\r\n] 2006.257.17:14:10.98#ibcon#*before write, iclass 23, count 2 2006.257.17:14:10.98#ibcon#enter sib2, iclass 23, count 2 2006.257.17:14:10.98#ibcon#flushed, iclass 23, count 2 2006.257.17:14:10.98#ibcon#about to write, iclass 23, count 2 2006.257.17:14:10.98#ibcon#wrote, iclass 23, count 2 2006.257.17:14:10.98#ibcon#about to read 3, iclass 23, count 2 2006.257.17:14:11.01#ibcon#read 3, iclass 23, count 2 2006.257.17:14:11.01#ibcon#about to read 4, iclass 23, count 2 2006.257.17:14:11.01#ibcon#read 4, iclass 23, count 2 2006.257.17:14:11.01#ibcon#about to read 5, iclass 23, count 2 2006.257.17:14:11.01#ibcon#read 5, iclass 23, count 2 2006.257.17:14:11.01#ibcon#about to read 6, iclass 23, count 2 2006.257.17:14:11.01#ibcon#read 6, iclass 23, count 2 2006.257.17:14:11.01#ibcon#end of sib2, iclass 23, count 2 2006.257.17:14:11.01#ibcon#*after write, iclass 23, count 2 2006.257.17:14:11.01#ibcon#*before return 0, iclass 23, count 2 2006.257.17:14:11.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:14:11.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:14:11.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.17:14:11.01#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:11.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:14:11.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:14:11.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:14:11.13#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:14:11.13#ibcon#first serial, iclass 23, count 0 2006.257.17:14:11.13#ibcon#enter sib2, iclass 23, count 0 2006.257.17:14:11.13#ibcon#flushed, iclass 23, count 0 2006.257.17:14:11.13#ibcon#about to write, iclass 23, count 0 2006.257.17:14:11.13#ibcon#wrote, iclass 23, count 0 2006.257.17:14:11.13#ibcon#about to read 3, iclass 23, count 0 2006.257.17:14:11.15#ibcon#read 3, iclass 23, count 0 2006.257.17:14:11.15#ibcon#about to read 4, iclass 23, count 0 2006.257.17:14:11.15#ibcon#read 4, iclass 23, count 0 2006.257.17:14:11.15#ibcon#about to read 5, iclass 23, count 0 2006.257.17:14:11.15#ibcon#read 5, iclass 23, count 0 2006.257.17:14:11.15#ibcon#about to read 6, iclass 23, count 0 2006.257.17:14:11.15#ibcon#read 6, iclass 23, count 0 2006.257.17:14:11.15#ibcon#end of sib2, iclass 23, count 0 2006.257.17:14:11.15#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:14:11.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:14:11.15#ibcon#[25=USB\r\n] 2006.257.17:14:11.15#ibcon#*before write, iclass 23, count 0 2006.257.17:14:11.15#ibcon#enter sib2, iclass 23, count 0 2006.257.17:14:11.15#ibcon#flushed, iclass 23, count 0 2006.257.17:14:11.15#ibcon#about to write, iclass 23, count 0 2006.257.17:14:11.15#ibcon#wrote, iclass 23, count 0 2006.257.17:14:11.15#ibcon#about to read 3, iclass 23, count 0 2006.257.17:14:11.18#ibcon#read 3, iclass 23, count 0 2006.257.17:14:11.18#ibcon#about to read 4, iclass 23, count 0 2006.257.17:14:11.18#ibcon#read 4, iclass 23, count 0 2006.257.17:14:11.18#ibcon#about to read 5, iclass 23, count 0 2006.257.17:14:11.18#ibcon#read 5, iclass 23, count 0 2006.257.17:14:11.18#ibcon#about to read 6, iclass 23, count 0 2006.257.17:14:11.18#ibcon#read 6, iclass 23, count 0 2006.257.17:14:11.18#ibcon#end of sib2, iclass 23, count 0 2006.257.17:14:11.18#ibcon#*after write, iclass 23, count 0 2006.257.17:14:11.18#ibcon#*before return 0, iclass 23, count 0 2006.257.17:14:11.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:14:11.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:14:11.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:14:11.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:14:11.18$vck44/vblo=1,629.99 2006.257.17:14:11.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.17:14:11.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.17:14:11.18#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:11.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:14:11.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:14:11.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:14:11.18#ibcon#enter wrdev, iclass 25, count 0 2006.257.17:14:11.18#ibcon#first serial, iclass 25, count 0 2006.257.17:14:11.18#ibcon#enter sib2, iclass 25, count 0 2006.257.17:14:11.18#ibcon#flushed, iclass 25, count 0 2006.257.17:14:11.18#ibcon#about to write, iclass 25, count 0 2006.257.17:14:11.18#ibcon#wrote, iclass 25, count 0 2006.257.17:14:11.18#ibcon#about to read 3, iclass 25, count 0 2006.257.17:14:11.20#ibcon#read 3, iclass 25, count 0 2006.257.17:14:11.20#ibcon#about to read 4, iclass 25, count 0 2006.257.17:14:11.20#ibcon#read 4, iclass 25, count 0 2006.257.17:14:11.20#ibcon#about to read 5, iclass 25, count 0 2006.257.17:14:11.20#ibcon#read 5, iclass 25, count 0 2006.257.17:14:11.20#ibcon#about to read 6, iclass 25, count 0 2006.257.17:14:11.20#ibcon#read 6, iclass 25, count 0 2006.257.17:14:11.20#ibcon#end of sib2, iclass 25, count 0 2006.257.17:14:11.20#ibcon#*mode == 0, iclass 25, count 0 2006.257.17:14:11.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.17:14:11.20#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:14:11.20#ibcon#*before write, iclass 25, count 0 2006.257.17:14:11.20#ibcon#enter sib2, iclass 25, count 0 2006.257.17:14:11.20#ibcon#flushed, iclass 25, count 0 2006.257.17:14:11.20#ibcon#about to write, iclass 25, count 0 2006.257.17:14:11.20#ibcon#wrote, iclass 25, count 0 2006.257.17:14:11.20#ibcon#about to read 3, iclass 25, count 0 2006.257.17:14:11.24#ibcon#read 3, iclass 25, count 0 2006.257.17:14:11.24#ibcon#about to read 4, iclass 25, count 0 2006.257.17:14:11.24#ibcon#read 4, iclass 25, count 0 2006.257.17:14:11.24#ibcon#about to read 5, iclass 25, count 0 2006.257.17:14:11.24#ibcon#read 5, iclass 25, count 0 2006.257.17:14:11.24#ibcon#about to read 6, iclass 25, count 0 2006.257.17:14:11.24#ibcon#read 6, iclass 25, count 0 2006.257.17:14:11.24#ibcon#end of sib2, iclass 25, count 0 2006.257.17:14:11.24#ibcon#*after write, iclass 25, count 0 2006.257.17:14:11.24#ibcon#*before return 0, iclass 25, count 0 2006.257.17:14:11.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:14:11.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:14:11.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.17:14:11.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.17:14:11.24$vck44/vb=1,4 2006.257.17:14:11.24#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.17:14:11.24#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.17:14:11.24#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:11.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:14:11.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:14:11.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:14:11.24#ibcon#enter wrdev, iclass 27, count 2 2006.257.17:14:11.24#ibcon#first serial, iclass 27, count 2 2006.257.17:14:11.24#ibcon#enter sib2, iclass 27, count 2 2006.257.17:14:11.24#ibcon#flushed, iclass 27, count 2 2006.257.17:14:11.24#ibcon#about to write, iclass 27, count 2 2006.257.17:14:11.24#ibcon#wrote, iclass 27, count 2 2006.257.17:14:11.24#ibcon#about to read 3, iclass 27, count 2 2006.257.17:14:11.26#ibcon#read 3, iclass 27, count 2 2006.257.17:14:11.26#ibcon#about to read 4, iclass 27, count 2 2006.257.17:14:11.26#ibcon#read 4, iclass 27, count 2 2006.257.17:14:11.26#ibcon#about to read 5, iclass 27, count 2 2006.257.17:14:11.26#ibcon#read 5, iclass 27, count 2 2006.257.17:14:11.26#ibcon#about to read 6, iclass 27, count 2 2006.257.17:14:11.26#ibcon#read 6, iclass 27, count 2 2006.257.17:14:11.26#ibcon#end of sib2, iclass 27, count 2 2006.257.17:14:11.26#ibcon#*mode == 0, iclass 27, count 2 2006.257.17:14:11.26#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.17:14:11.26#ibcon#[27=AT01-04\r\n] 2006.257.17:14:11.26#ibcon#*before write, iclass 27, count 2 2006.257.17:14:11.26#ibcon#enter sib2, iclass 27, count 2 2006.257.17:14:11.26#ibcon#flushed, iclass 27, count 2 2006.257.17:14:11.26#ibcon#about to write, iclass 27, count 2 2006.257.17:14:11.26#ibcon#wrote, iclass 27, count 2 2006.257.17:14:11.26#ibcon#about to read 3, iclass 27, count 2 2006.257.17:14:11.29#ibcon#read 3, iclass 27, count 2 2006.257.17:14:11.29#ibcon#about to read 4, iclass 27, count 2 2006.257.17:14:11.29#ibcon#read 4, iclass 27, count 2 2006.257.17:14:11.29#ibcon#about to read 5, iclass 27, count 2 2006.257.17:14:11.29#ibcon#read 5, iclass 27, count 2 2006.257.17:14:11.29#ibcon#about to read 6, iclass 27, count 2 2006.257.17:14:11.29#ibcon#read 6, iclass 27, count 2 2006.257.17:14:11.29#ibcon#end of sib2, iclass 27, count 2 2006.257.17:14:11.29#ibcon#*after write, iclass 27, count 2 2006.257.17:14:11.29#ibcon#*before return 0, iclass 27, count 2 2006.257.17:14:11.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:14:11.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:14:11.29#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.17:14:11.29#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:11.29#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:14:11.41#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:14:11.41#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:14:11.41#ibcon#enter wrdev, iclass 27, count 0 2006.257.17:14:11.41#ibcon#first serial, iclass 27, count 0 2006.257.17:14:11.41#ibcon#enter sib2, iclass 27, count 0 2006.257.17:14:11.41#ibcon#flushed, iclass 27, count 0 2006.257.17:14:11.41#ibcon#about to write, iclass 27, count 0 2006.257.17:14:11.41#ibcon#wrote, iclass 27, count 0 2006.257.17:14:11.41#ibcon#about to read 3, iclass 27, count 0 2006.257.17:14:11.43#ibcon#read 3, iclass 27, count 0 2006.257.17:14:11.43#ibcon#about to read 4, iclass 27, count 0 2006.257.17:14:11.43#ibcon#read 4, iclass 27, count 0 2006.257.17:14:11.43#ibcon#about to read 5, iclass 27, count 0 2006.257.17:14:11.43#ibcon#read 5, iclass 27, count 0 2006.257.17:14:11.43#ibcon#about to read 6, iclass 27, count 0 2006.257.17:14:11.43#ibcon#read 6, iclass 27, count 0 2006.257.17:14:11.43#ibcon#end of sib2, iclass 27, count 0 2006.257.17:14:11.43#ibcon#*mode == 0, iclass 27, count 0 2006.257.17:14:11.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.17:14:11.43#ibcon#[27=USB\r\n] 2006.257.17:14:11.43#ibcon#*before write, iclass 27, count 0 2006.257.17:14:11.43#ibcon#enter sib2, iclass 27, count 0 2006.257.17:14:11.43#ibcon#flushed, iclass 27, count 0 2006.257.17:14:11.43#ibcon#about to write, iclass 27, count 0 2006.257.17:14:11.43#ibcon#wrote, iclass 27, count 0 2006.257.17:14:11.43#ibcon#about to read 3, iclass 27, count 0 2006.257.17:14:11.46#ibcon#read 3, iclass 27, count 0 2006.257.17:14:11.46#ibcon#about to read 4, iclass 27, count 0 2006.257.17:14:11.46#ibcon#read 4, iclass 27, count 0 2006.257.17:14:11.46#ibcon#about to read 5, iclass 27, count 0 2006.257.17:14:11.46#ibcon#read 5, iclass 27, count 0 2006.257.17:14:11.46#ibcon#about to read 6, iclass 27, count 0 2006.257.17:14:11.46#ibcon#read 6, iclass 27, count 0 2006.257.17:14:11.46#ibcon#end of sib2, iclass 27, count 0 2006.257.17:14:11.46#ibcon#*after write, iclass 27, count 0 2006.257.17:14:11.46#ibcon#*before return 0, iclass 27, count 0 2006.257.17:14:11.46#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:14:11.46#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:14:11.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.17:14:11.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.17:14:11.46$vck44/vblo=2,634.99 2006.257.17:14:11.46#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.17:14:11.46#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.17:14:11.46#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:11.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:11.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:11.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:11.46#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:14:11.46#ibcon#first serial, iclass 29, count 0 2006.257.17:14:11.46#ibcon#enter sib2, iclass 29, count 0 2006.257.17:14:11.46#ibcon#flushed, iclass 29, count 0 2006.257.17:14:11.46#ibcon#about to write, iclass 29, count 0 2006.257.17:14:11.46#ibcon#wrote, iclass 29, count 0 2006.257.17:14:11.46#ibcon#about to read 3, iclass 29, count 0 2006.257.17:14:11.48#ibcon#read 3, iclass 29, count 0 2006.257.17:14:11.48#ibcon#about to read 4, iclass 29, count 0 2006.257.17:14:11.48#ibcon#read 4, iclass 29, count 0 2006.257.17:14:11.48#ibcon#about to read 5, iclass 29, count 0 2006.257.17:14:11.48#ibcon#read 5, iclass 29, count 0 2006.257.17:14:11.48#ibcon#about to read 6, iclass 29, count 0 2006.257.17:14:11.48#ibcon#read 6, iclass 29, count 0 2006.257.17:14:11.48#ibcon#end of sib2, iclass 29, count 0 2006.257.17:14:11.48#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:14:11.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:14:11.48#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:14:11.48#ibcon#*before write, iclass 29, count 0 2006.257.17:14:11.48#ibcon#enter sib2, iclass 29, count 0 2006.257.17:14:11.48#ibcon#flushed, iclass 29, count 0 2006.257.17:14:11.48#ibcon#about to write, iclass 29, count 0 2006.257.17:14:11.48#ibcon#wrote, iclass 29, count 0 2006.257.17:14:11.48#ibcon#about to read 3, iclass 29, count 0 2006.257.17:14:11.52#ibcon#read 3, iclass 29, count 0 2006.257.17:14:11.52#ibcon#about to read 4, iclass 29, count 0 2006.257.17:14:11.52#ibcon#read 4, iclass 29, count 0 2006.257.17:14:11.52#ibcon#about to read 5, iclass 29, count 0 2006.257.17:14:11.52#ibcon#read 5, iclass 29, count 0 2006.257.17:14:11.52#ibcon#about to read 6, iclass 29, count 0 2006.257.17:14:11.52#ibcon#read 6, iclass 29, count 0 2006.257.17:14:11.52#ibcon#end of sib2, iclass 29, count 0 2006.257.17:14:11.52#ibcon#*after write, iclass 29, count 0 2006.257.17:14:11.52#ibcon#*before return 0, iclass 29, count 0 2006.257.17:14:11.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:11.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:14:11.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:14:11.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:14:11.52$vck44/vb=2,5 2006.257.17:14:11.52#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.17:14:11.52#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.17:14:11.52#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:11.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:11.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:11.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:11.58#ibcon#enter wrdev, iclass 31, count 2 2006.257.17:14:11.58#ibcon#first serial, iclass 31, count 2 2006.257.17:14:11.58#ibcon#enter sib2, iclass 31, count 2 2006.257.17:14:11.58#ibcon#flushed, iclass 31, count 2 2006.257.17:14:11.58#ibcon#about to write, iclass 31, count 2 2006.257.17:14:11.58#ibcon#wrote, iclass 31, count 2 2006.257.17:14:11.58#ibcon#about to read 3, iclass 31, count 2 2006.257.17:14:11.60#ibcon#read 3, iclass 31, count 2 2006.257.17:14:11.60#ibcon#about to read 4, iclass 31, count 2 2006.257.17:14:11.60#ibcon#read 4, iclass 31, count 2 2006.257.17:14:11.60#ibcon#about to read 5, iclass 31, count 2 2006.257.17:14:11.60#ibcon#read 5, iclass 31, count 2 2006.257.17:14:11.60#ibcon#about to read 6, iclass 31, count 2 2006.257.17:14:11.60#ibcon#read 6, iclass 31, count 2 2006.257.17:14:11.60#ibcon#end of sib2, iclass 31, count 2 2006.257.17:14:11.60#ibcon#*mode == 0, iclass 31, count 2 2006.257.17:14:11.60#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.17:14:11.60#ibcon#[27=AT02-05\r\n] 2006.257.17:14:11.60#ibcon#*before write, iclass 31, count 2 2006.257.17:14:11.60#ibcon#enter sib2, iclass 31, count 2 2006.257.17:14:11.60#ibcon#flushed, iclass 31, count 2 2006.257.17:14:11.60#ibcon#about to write, iclass 31, count 2 2006.257.17:14:11.60#ibcon#wrote, iclass 31, count 2 2006.257.17:14:11.60#ibcon#about to read 3, iclass 31, count 2 2006.257.17:14:11.63#ibcon#read 3, iclass 31, count 2 2006.257.17:14:11.63#ibcon#about to read 4, iclass 31, count 2 2006.257.17:14:11.63#ibcon#read 4, iclass 31, count 2 2006.257.17:14:11.63#ibcon#about to read 5, iclass 31, count 2 2006.257.17:14:11.63#ibcon#read 5, iclass 31, count 2 2006.257.17:14:11.63#ibcon#about to read 6, iclass 31, count 2 2006.257.17:14:11.63#ibcon#read 6, iclass 31, count 2 2006.257.17:14:11.63#ibcon#end of sib2, iclass 31, count 2 2006.257.17:14:11.63#ibcon#*after write, iclass 31, count 2 2006.257.17:14:11.63#ibcon#*before return 0, iclass 31, count 2 2006.257.17:14:11.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:11.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:14:11.63#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.17:14:11.63#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:11.63#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:11.75#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:11.75#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:11.75#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:14:11.75#ibcon#first serial, iclass 31, count 0 2006.257.17:14:11.75#ibcon#enter sib2, iclass 31, count 0 2006.257.17:14:11.75#ibcon#flushed, iclass 31, count 0 2006.257.17:14:11.75#ibcon#about to write, iclass 31, count 0 2006.257.17:14:11.75#ibcon#wrote, iclass 31, count 0 2006.257.17:14:11.75#ibcon#about to read 3, iclass 31, count 0 2006.257.17:14:11.77#ibcon#read 3, iclass 31, count 0 2006.257.17:14:11.77#ibcon#about to read 4, iclass 31, count 0 2006.257.17:14:11.77#ibcon#read 4, iclass 31, count 0 2006.257.17:14:11.77#ibcon#about to read 5, iclass 31, count 0 2006.257.17:14:11.77#ibcon#read 5, iclass 31, count 0 2006.257.17:14:11.77#ibcon#about to read 6, iclass 31, count 0 2006.257.17:14:11.77#ibcon#read 6, iclass 31, count 0 2006.257.17:14:11.77#ibcon#end of sib2, iclass 31, count 0 2006.257.17:14:11.77#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:14:11.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:14:11.77#ibcon#[27=USB\r\n] 2006.257.17:14:11.77#ibcon#*before write, iclass 31, count 0 2006.257.17:14:11.77#ibcon#enter sib2, iclass 31, count 0 2006.257.17:14:11.77#ibcon#flushed, iclass 31, count 0 2006.257.17:14:11.77#ibcon#about to write, iclass 31, count 0 2006.257.17:14:11.77#ibcon#wrote, iclass 31, count 0 2006.257.17:14:11.77#ibcon#about to read 3, iclass 31, count 0 2006.257.17:14:11.80#ibcon#read 3, iclass 31, count 0 2006.257.17:14:11.80#ibcon#about to read 4, iclass 31, count 0 2006.257.17:14:11.80#ibcon#read 4, iclass 31, count 0 2006.257.17:14:11.80#ibcon#about to read 5, iclass 31, count 0 2006.257.17:14:11.80#ibcon#read 5, iclass 31, count 0 2006.257.17:14:11.80#ibcon#about to read 6, iclass 31, count 0 2006.257.17:14:11.80#ibcon#read 6, iclass 31, count 0 2006.257.17:14:11.80#ibcon#end of sib2, iclass 31, count 0 2006.257.17:14:11.80#ibcon#*after write, iclass 31, count 0 2006.257.17:14:11.80#ibcon#*before return 0, iclass 31, count 0 2006.257.17:14:11.80#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:11.80#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:14:11.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:14:11.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:14:11.80$vck44/vblo=3,649.99 2006.257.17:14:11.80#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.17:14:11.80#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.17:14:11.80#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:11.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:11.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:11.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:11.80#ibcon#enter wrdev, iclass 33, count 0 2006.257.17:14:11.80#ibcon#first serial, iclass 33, count 0 2006.257.17:14:11.80#ibcon#enter sib2, iclass 33, count 0 2006.257.17:14:11.80#ibcon#flushed, iclass 33, count 0 2006.257.17:14:11.80#ibcon#about to write, iclass 33, count 0 2006.257.17:14:11.80#ibcon#wrote, iclass 33, count 0 2006.257.17:14:11.80#ibcon#about to read 3, iclass 33, count 0 2006.257.17:14:11.82#ibcon#read 3, iclass 33, count 0 2006.257.17:14:11.82#ibcon#about to read 4, iclass 33, count 0 2006.257.17:14:11.82#ibcon#read 4, iclass 33, count 0 2006.257.17:14:11.82#ibcon#about to read 5, iclass 33, count 0 2006.257.17:14:11.82#ibcon#read 5, iclass 33, count 0 2006.257.17:14:11.82#ibcon#about to read 6, iclass 33, count 0 2006.257.17:14:11.82#ibcon#read 6, iclass 33, count 0 2006.257.17:14:11.82#ibcon#end of sib2, iclass 33, count 0 2006.257.17:14:11.82#ibcon#*mode == 0, iclass 33, count 0 2006.257.17:14:11.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.17:14:11.82#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:14:11.82#ibcon#*before write, iclass 33, count 0 2006.257.17:14:11.82#ibcon#enter sib2, iclass 33, count 0 2006.257.17:14:11.82#ibcon#flushed, iclass 33, count 0 2006.257.17:14:11.82#ibcon#about to write, iclass 33, count 0 2006.257.17:14:11.82#ibcon#wrote, iclass 33, count 0 2006.257.17:14:11.82#ibcon#about to read 3, iclass 33, count 0 2006.257.17:14:11.86#ibcon#read 3, iclass 33, count 0 2006.257.17:14:11.86#ibcon#about to read 4, iclass 33, count 0 2006.257.17:14:11.86#ibcon#read 4, iclass 33, count 0 2006.257.17:14:11.86#ibcon#about to read 5, iclass 33, count 0 2006.257.17:14:11.86#ibcon#read 5, iclass 33, count 0 2006.257.17:14:11.86#ibcon#about to read 6, iclass 33, count 0 2006.257.17:14:11.86#ibcon#read 6, iclass 33, count 0 2006.257.17:14:11.86#ibcon#end of sib2, iclass 33, count 0 2006.257.17:14:11.86#ibcon#*after write, iclass 33, count 0 2006.257.17:14:11.86#ibcon#*before return 0, iclass 33, count 0 2006.257.17:14:11.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:11.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:14:11.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.17:14:11.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.17:14:11.86$vck44/vb=3,4 2006.257.17:14:11.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.17:14:11.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.17:14:11.86#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:11.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:11.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:11.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:11.92#ibcon#enter wrdev, iclass 35, count 2 2006.257.17:14:11.92#ibcon#first serial, iclass 35, count 2 2006.257.17:14:11.92#ibcon#enter sib2, iclass 35, count 2 2006.257.17:14:11.92#ibcon#flushed, iclass 35, count 2 2006.257.17:14:11.92#ibcon#about to write, iclass 35, count 2 2006.257.17:14:11.92#ibcon#wrote, iclass 35, count 2 2006.257.17:14:11.92#ibcon#about to read 3, iclass 35, count 2 2006.257.17:14:11.94#ibcon#read 3, iclass 35, count 2 2006.257.17:14:11.94#ibcon#about to read 4, iclass 35, count 2 2006.257.17:14:11.94#ibcon#read 4, iclass 35, count 2 2006.257.17:14:11.94#ibcon#about to read 5, iclass 35, count 2 2006.257.17:14:11.94#ibcon#read 5, iclass 35, count 2 2006.257.17:14:11.94#ibcon#about to read 6, iclass 35, count 2 2006.257.17:14:11.94#ibcon#read 6, iclass 35, count 2 2006.257.17:14:11.94#ibcon#end of sib2, iclass 35, count 2 2006.257.17:14:11.94#ibcon#*mode == 0, iclass 35, count 2 2006.257.17:14:11.94#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.17:14:11.94#ibcon#[27=AT03-04\r\n] 2006.257.17:14:11.94#ibcon#*before write, iclass 35, count 2 2006.257.17:14:11.94#ibcon#enter sib2, iclass 35, count 2 2006.257.17:14:11.94#ibcon#flushed, iclass 35, count 2 2006.257.17:14:11.94#ibcon#about to write, iclass 35, count 2 2006.257.17:14:11.94#ibcon#wrote, iclass 35, count 2 2006.257.17:14:11.94#ibcon#about to read 3, iclass 35, count 2 2006.257.17:14:11.97#ibcon#read 3, iclass 35, count 2 2006.257.17:14:11.97#ibcon#about to read 4, iclass 35, count 2 2006.257.17:14:11.97#ibcon#read 4, iclass 35, count 2 2006.257.17:14:11.97#ibcon#about to read 5, iclass 35, count 2 2006.257.17:14:11.97#ibcon#read 5, iclass 35, count 2 2006.257.17:14:11.97#ibcon#about to read 6, iclass 35, count 2 2006.257.17:14:11.97#ibcon#read 6, iclass 35, count 2 2006.257.17:14:11.97#ibcon#end of sib2, iclass 35, count 2 2006.257.17:14:11.97#ibcon#*after write, iclass 35, count 2 2006.257.17:14:11.97#ibcon#*before return 0, iclass 35, count 2 2006.257.17:14:11.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:11.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:14:11.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.17:14:11.97#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:11.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:12.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:12.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:12.09#ibcon#enter wrdev, iclass 35, count 0 2006.257.17:14:12.09#ibcon#first serial, iclass 35, count 0 2006.257.17:14:12.09#ibcon#enter sib2, iclass 35, count 0 2006.257.17:14:12.09#ibcon#flushed, iclass 35, count 0 2006.257.17:14:12.09#ibcon#about to write, iclass 35, count 0 2006.257.17:14:12.09#ibcon#wrote, iclass 35, count 0 2006.257.17:14:12.09#ibcon#about to read 3, iclass 35, count 0 2006.257.17:14:12.11#ibcon#read 3, iclass 35, count 0 2006.257.17:14:12.11#ibcon#about to read 4, iclass 35, count 0 2006.257.17:14:12.11#ibcon#read 4, iclass 35, count 0 2006.257.17:14:12.11#ibcon#about to read 5, iclass 35, count 0 2006.257.17:14:12.11#ibcon#read 5, iclass 35, count 0 2006.257.17:14:12.11#ibcon#about to read 6, iclass 35, count 0 2006.257.17:14:12.11#ibcon#read 6, iclass 35, count 0 2006.257.17:14:12.11#ibcon#end of sib2, iclass 35, count 0 2006.257.17:14:12.11#ibcon#*mode == 0, iclass 35, count 0 2006.257.17:14:12.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.17:14:12.11#ibcon#[27=USB\r\n] 2006.257.17:14:12.11#ibcon#*before write, iclass 35, count 0 2006.257.17:14:12.11#ibcon#enter sib2, iclass 35, count 0 2006.257.17:14:12.11#ibcon#flushed, iclass 35, count 0 2006.257.17:14:12.11#ibcon#about to write, iclass 35, count 0 2006.257.17:14:12.11#ibcon#wrote, iclass 35, count 0 2006.257.17:14:12.11#ibcon#about to read 3, iclass 35, count 0 2006.257.17:14:12.14#ibcon#read 3, iclass 35, count 0 2006.257.17:14:12.14#ibcon#about to read 4, iclass 35, count 0 2006.257.17:14:12.14#ibcon#read 4, iclass 35, count 0 2006.257.17:14:12.14#ibcon#about to read 5, iclass 35, count 0 2006.257.17:14:12.14#ibcon#read 5, iclass 35, count 0 2006.257.17:14:12.14#ibcon#about to read 6, iclass 35, count 0 2006.257.17:14:12.14#ibcon#read 6, iclass 35, count 0 2006.257.17:14:12.14#ibcon#end of sib2, iclass 35, count 0 2006.257.17:14:12.14#ibcon#*after write, iclass 35, count 0 2006.257.17:14:12.14#ibcon#*before return 0, iclass 35, count 0 2006.257.17:14:12.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:12.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:14:12.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.17:14:12.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.17:14:12.14$vck44/vblo=4,679.99 2006.257.17:14:12.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.17:14:12.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.17:14:12.14#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:12.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:12.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:12.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:12.14#ibcon#enter wrdev, iclass 37, count 0 2006.257.17:14:12.14#ibcon#first serial, iclass 37, count 0 2006.257.17:14:12.14#ibcon#enter sib2, iclass 37, count 0 2006.257.17:14:12.14#ibcon#flushed, iclass 37, count 0 2006.257.17:14:12.14#ibcon#about to write, iclass 37, count 0 2006.257.17:14:12.14#ibcon#wrote, iclass 37, count 0 2006.257.17:14:12.14#ibcon#about to read 3, iclass 37, count 0 2006.257.17:14:12.16#ibcon#read 3, iclass 37, count 0 2006.257.17:14:12.16#ibcon#about to read 4, iclass 37, count 0 2006.257.17:14:12.16#ibcon#read 4, iclass 37, count 0 2006.257.17:14:12.16#ibcon#about to read 5, iclass 37, count 0 2006.257.17:14:12.16#ibcon#read 5, iclass 37, count 0 2006.257.17:14:12.16#ibcon#about to read 6, iclass 37, count 0 2006.257.17:14:12.16#ibcon#read 6, iclass 37, count 0 2006.257.17:14:12.16#ibcon#end of sib2, iclass 37, count 0 2006.257.17:14:12.16#ibcon#*mode == 0, iclass 37, count 0 2006.257.17:14:12.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.17:14:12.16#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:14:12.16#ibcon#*before write, iclass 37, count 0 2006.257.17:14:12.16#ibcon#enter sib2, iclass 37, count 0 2006.257.17:14:12.16#ibcon#flushed, iclass 37, count 0 2006.257.17:14:12.16#ibcon#about to write, iclass 37, count 0 2006.257.17:14:12.16#ibcon#wrote, iclass 37, count 0 2006.257.17:14:12.16#ibcon#about to read 3, iclass 37, count 0 2006.257.17:14:12.20#ibcon#read 3, iclass 37, count 0 2006.257.17:14:12.20#ibcon#about to read 4, iclass 37, count 0 2006.257.17:14:12.20#ibcon#read 4, iclass 37, count 0 2006.257.17:14:12.20#ibcon#about to read 5, iclass 37, count 0 2006.257.17:14:12.20#ibcon#read 5, iclass 37, count 0 2006.257.17:14:12.20#ibcon#about to read 6, iclass 37, count 0 2006.257.17:14:12.20#ibcon#read 6, iclass 37, count 0 2006.257.17:14:12.20#ibcon#end of sib2, iclass 37, count 0 2006.257.17:14:12.20#ibcon#*after write, iclass 37, count 0 2006.257.17:14:12.20#ibcon#*before return 0, iclass 37, count 0 2006.257.17:14:12.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:12.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:14:12.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.17:14:12.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.17:14:12.20$vck44/vb=4,5 2006.257.17:14:12.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.17:14:12.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.17:14:12.20#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:12.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:12.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:12.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:12.26#ibcon#enter wrdev, iclass 39, count 2 2006.257.17:14:12.26#ibcon#first serial, iclass 39, count 2 2006.257.17:14:12.26#ibcon#enter sib2, iclass 39, count 2 2006.257.17:14:12.26#ibcon#flushed, iclass 39, count 2 2006.257.17:14:12.26#ibcon#about to write, iclass 39, count 2 2006.257.17:14:12.26#ibcon#wrote, iclass 39, count 2 2006.257.17:14:12.26#ibcon#about to read 3, iclass 39, count 2 2006.257.17:14:12.28#ibcon#read 3, iclass 39, count 2 2006.257.17:14:12.28#ibcon#about to read 4, iclass 39, count 2 2006.257.17:14:12.28#ibcon#read 4, iclass 39, count 2 2006.257.17:14:12.28#ibcon#about to read 5, iclass 39, count 2 2006.257.17:14:12.28#ibcon#read 5, iclass 39, count 2 2006.257.17:14:12.28#ibcon#about to read 6, iclass 39, count 2 2006.257.17:14:12.28#ibcon#read 6, iclass 39, count 2 2006.257.17:14:12.28#ibcon#end of sib2, iclass 39, count 2 2006.257.17:14:12.28#ibcon#*mode == 0, iclass 39, count 2 2006.257.17:14:12.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.17:14:12.28#ibcon#[27=AT04-05\r\n] 2006.257.17:14:12.28#ibcon#*before write, iclass 39, count 2 2006.257.17:14:12.28#ibcon#enter sib2, iclass 39, count 2 2006.257.17:14:12.28#ibcon#flushed, iclass 39, count 2 2006.257.17:14:12.28#ibcon#about to write, iclass 39, count 2 2006.257.17:14:12.28#ibcon#wrote, iclass 39, count 2 2006.257.17:14:12.28#ibcon#about to read 3, iclass 39, count 2 2006.257.17:14:12.31#ibcon#read 3, iclass 39, count 2 2006.257.17:14:12.31#ibcon#about to read 4, iclass 39, count 2 2006.257.17:14:12.31#ibcon#read 4, iclass 39, count 2 2006.257.17:14:12.31#ibcon#about to read 5, iclass 39, count 2 2006.257.17:14:12.31#ibcon#read 5, iclass 39, count 2 2006.257.17:14:12.31#ibcon#about to read 6, iclass 39, count 2 2006.257.17:14:12.31#ibcon#read 6, iclass 39, count 2 2006.257.17:14:12.31#ibcon#end of sib2, iclass 39, count 2 2006.257.17:14:12.31#ibcon#*after write, iclass 39, count 2 2006.257.17:14:12.31#ibcon#*before return 0, iclass 39, count 2 2006.257.17:14:12.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:12.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:14:12.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.17:14:12.31#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:12.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:12.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:12.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:12.43#ibcon#enter wrdev, iclass 39, count 0 2006.257.17:14:12.43#ibcon#first serial, iclass 39, count 0 2006.257.17:14:12.43#ibcon#enter sib2, iclass 39, count 0 2006.257.17:14:12.43#ibcon#flushed, iclass 39, count 0 2006.257.17:14:12.43#ibcon#about to write, iclass 39, count 0 2006.257.17:14:12.43#ibcon#wrote, iclass 39, count 0 2006.257.17:14:12.43#ibcon#about to read 3, iclass 39, count 0 2006.257.17:14:12.45#ibcon#read 3, iclass 39, count 0 2006.257.17:14:12.45#ibcon#about to read 4, iclass 39, count 0 2006.257.17:14:12.45#ibcon#read 4, iclass 39, count 0 2006.257.17:14:12.45#ibcon#about to read 5, iclass 39, count 0 2006.257.17:14:12.45#ibcon#read 5, iclass 39, count 0 2006.257.17:14:12.45#ibcon#about to read 6, iclass 39, count 0 2006.257.17:14:12.45#ibcon#read 6, iclass 39, count 0 2006.257.17:14:12.45#ibcon#end of sib2, iclass 39, count 0 2006.257.17:14:12.45#ibcon#*mode == 0, iclass 39, count 0 2006.257.17:14:12.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.17:14:12.45#ibcon#[27=USB\r\n] 2006.257.17:14:12.45#ibcon#*before write, iclass 39, count 0 2006.257.17:14:12.45#ibcon#enter sib2, iclass 39, count 0 2006.257.17:14:12.45#ibcon#flushed, iclass 39, count 0 2006.257.17:14:12.45#ibcon#about to write, iclass 39, count 0 2006.257.17:14:12.45#ibcon#wrote, iclass 39, count 0 2006.257.17:14:12.45#ibcon#about to read 3, iclass 39, count 0 2006.257.17:14:12.48#ibcon#read 3, iclass 39, count 0 2006.257.17:14:12.48#ibcon#about to read 4, iclass 39, count 0 2006.257.17:14:12.48#ibcon#read 4, iclass 39, count 0 2006.257.17:14:12.48#ibcon#about to read 5, iclass 39, count 0 2006.257.17:14:12.48#ibcon#read 5, iclass 39, count 0 2006.257.17:14:12.48#ibcon#about to read 6, iclass 39, count 0 2006.257.17:14:12.48#ibcon#read 6, iclass 39, count 0 2006.257.17:14:12.48#ibcon#end of sib2, iclass 39, count 0 2006.257.17:14:12.48#ibcon#*after write, iclass 39, count 0 2006.257.17:14:12.48#ibcon#*before return 0, iclass 39, count 0 2006.257.17:14:12.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:12.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:14:12.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.17:14:12.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.17:14:12.48$vck44/vblo=5,709.99 2006.257.17:14:12.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.17:14:12.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.17:14:12.48#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:12.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:12.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:12.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:12.48#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:14:12.48#ibcon#first serial, iclass 3, count 0 2006.257.17:14:12.48#ibcon#enter sib2, iclass 3, count 0 2006.257.17:14:12.48#ibcon#flushed, iclass 3, count 0 2006.257.17:14:12.48#ibcon#about to write, iclass 3, count 0 2006.257.17:14:12.48#ibcon#wrote, iclass 3, count 0 2006.257.17:14:12.48#ibcon#about to read 3, iclass 3, count 0 2006.257.17:14:12.50#ibcon#read 3, iclass 3, count 0 2006.257.17:14:12.50#ibcon#about to read 4, iclass 3, count 0 2006.257.17:14:12.50#ibcon#read 4, iclass 3, count 0 2006.257.17:14:12.50#ibcon#about to read 5, iclass 3, count 0 2006.257.17:14:12.50#ibcon#read 5, iclass 3, count 0 2006.257.17:14:12.50#ibcon#about to read 6, iclass 3, count 0 2006.257.17:14:12.50#ibcon#read 6, iclass 3, count 0 2006.257.17:14:12.50#ibcon#end of sib2, iclass 3, count 0 2006.257.17:14:12.50#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:14:12.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:14:12.50#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:14:12.50#ibcon#*before write, iclass 3, count 0 2006.257.17:14:12.50#ibcon#enter sib2, iclass 3, count 0 2006.257.17:14:12.50#ibcon#flushed, iclass 3, count 0 2006.257.17:14:12.50#ibcon#about to write, iclass 3, count 0 2006.257.17:14:12.50#ibcon#wrote, iclass 3, count 0 2006.257.17:14:12.50#ibcon#about to read 3, iclass 3, count 0 2006.257.17:14:12.54#ibcon#read 3, iclass 3, count 0 2006.257.17:14:12.54#ibcon#about to read 4, iclass 3, count 0 2006.257.17:14:12.54#ibcon#read 4, iclass 3, count 0 2006.257.17:14:12.54#ibcon#about to read 5, iclass 3, count 0 2006.257.17:14:12.54#ibcon#read 5, iclass 3, count 0 2006.257.17:14:12.54#ibcon#about to read 6, iclass 3, count 0 2006.257.17:14:12.54#ibcon#read 6, iclass 3, count 0 2006.257.17:14:12.54#ibcon#end of sib2, iclass 3, count 0 2006.257.17:14:12.54#ibcon#*after write, iclass 3, count 0 2006.257.17:14:12.54#ibcon#*before return 0, iclass 3, count 0 2006.257.17:14:12.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:12.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:14:12.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:14:12.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:14:12.54$vck44/vb=5,4 2006.257.17:14:12.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.17:14:12.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.17:14:12.54#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:12.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:12.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:12.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:12.60#ibcon#enter wrdev, iclass 5, count 2 2006.257.17:14:12.60#ibcon#first serial, iclass 5, count 2 2006.257.17:14:12.60#ibcon#enter sib2, iclass 5, count 2 2006.257.17:14:12.60#ibcon#flushed, iclass 5, count 2 2006.257.17:14:12.60#ibcon#about to write, iclass 5, count 2 2006.257.17:14:12.60#ibcon#wrote, iclass 5, count 2 2006.257.17:14:12.60#ibcon#about to read 3, iclass 5, count 2 2006.257.17:14:12.62#ibcon#read 3, iclass 5, count 2 2006.257.17:14:12.62#ibcon#about to read 4, iclass 5, count 2 2006.257.17:14:12.62#ibcon#read 4, iclass 5, count 2 2006.257.17:14:12.62#ibcon#about to read 5, iclass 5, count 2 2006.257.17:14:12.62#ibcon#read 5, iclass 5, count 2 2006.257.17:14:12.62#ibcon#about to read 6, iclass 5, count 2 2006.257.17:14:12.62#ibcon#read 6, iclass 5, count 2 2006.257.17:14:12.62#ibcon#end of sib2, iclass 5, count 2 2006.257.17:14:12.62#ibcon#*mode == 0, iclass 5, count 2 2006.257.17:14:12.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.17:14:12.62#ibcon#[27=AT05-04\r\n] 2006.257.17:14:12.62#ibcon#*before write, iclass 5, count 2 2006.257.17:14:12.62#ibcon#enter sib2, iclass 5, count 2 2006.257.17:14:12.62#ibcon#flushed, iclass 5, count 2 2006.257.17:14:12.62#ibcon#about to write, iclass 5, count 2 2006.257.17:14:12.62#ibcon#wrote, iclass 5, count 2 2006.257.17:14:12.62#ibcon#about to read 3, iclass 5, count 2 2006.257.17:14:12.65#ibcon#read 3, iclass 5, count 2 2006.257.17:14:12.65#ibcon#about to read 4, iclass 5, count 2 2006.257.17:14:12.65#ibcon#read 4, iclass 5, count 2 2006.257.17:14:12.65#ibcon#about to read 5, iclass 5, count 2 2006.257.17:14:12.65#ibcon#read 5, iclass 5, count 2 2006.257.17:14:12.65#ibcon#about to read 6, iclass 5, count 2 2006.257.17:14:12.65#ibcon#read 6, iclass 5, count 2 2006.257.17:14:12.65#ibcon#end of sib2, iclass 5, count 2 2006.257.17:14:12.65#ibcon#*after write, iclass 5, count 2 2006.257.17:14:12.65#ibcon#*before return 0, iclass 5, count 2 2006.257.17:14:12.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:12.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:14:12.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.17:14:12.65#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:12.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:12.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:12.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:12.77#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:14:12.77#ibcon#first serial, iclass 5, count 0 2006.257.17:14:12.77#ibcon#enter sib2, iclass 5, count 0 2006.257.17:14:12.77#ibcon#flushed, iclass 5, count 0 2006.257.17:14:12.77#ibcon#about to write, iclass 5, count 0 2006.257.17:14:12.77#ibcon#wrote, iclass 5, count 0 2006.257.17:14:12.77#ibcon#about to read 3, iclass 5, count 0 2006.257.17:14:12.79#ibcon#read 3, iclass 5, count 0 2006.257.17:14:12.79#ibcon#about to read 4, iclass 5, count 0 2006.257.17:14:12.79#ibcon#read 4, iclass 5, count 0 2006.257.17:14:12.79#ibcon#about to read 5, iclass 5, count 0 2006.257.17:14:12.79#ibcon#read 5, iclass 5, count 0 2006.257.17:14:12.79#ibcon#about to read 6, iclass 5, count 0 2006.257.17:14:12.79#ibcon#read 6, iclass 5, count 0 2006.257.17:14:12.79#ibcon#end of sib2, iclass 5, count 0 2006.257.17:14:12.79#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:14:12.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:14:12.79#ibcon#[27=USB\r\n] 2006.257.17:14:12.79#ibcon#*before write, iclass 5, count 0 2006.257.17:14:12.79#ibcon#enter sib2, iclass 5, count 0 2006.257.17:14:12.79#ibcon#flushed, iclass 5, count 0 2006.257.17:14:12.79#ibcon#about to write, iclass 5, count 0 2006.257.17:14:12.79#ibcon#wrote, iclass 5, count 0 2006.257.17:14:12.79#ibcon#about to read 3, iclass 5, count 0 2006.257.17:14:12.82#ibcon#read 3, iclass 5, count 0 2006.257.17:14:12.82#ibcon#about to read 4, iclass 5, count 0 2006.257.17:14:12.82#ibcon#read 4, iclass 5, count 0 2006.257.17:14:12.82#ibcon#about to read 5, iclass 5, count 0 2006.257.17:14:12.82#ibcon#read 5, iclass 5, count 0 2006.257.17:14:12.82#ibcon#about to read 6, iclass 5, count 0 2006.257.17:14:12.82#ibcon#read 6, iclass 5, count 0 2006.257.17:14:12.82#ibcon#end of sib2, iclass 5, count 0 2006.257.17:14:12.82#ibcon#*after write, iclass 5, count 0 2006.257.17:14:12.82#ibcon#*before return 0, iclass 5, count 0 2006.257.17:14:12.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:12.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:14:12.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:14:12.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:14:12.82$vck44/vblo=6,719.99 2006.257.17:14:12.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.17:14:12.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.17:14:12.82#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:12.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:12.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:12.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:12.82#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:14:12.82#ibcon#first serial, iclass 7, count 0 2006.257.17:14:12.82#ibcon#enter sib2, iclass 7, count 0 2006.257.17:14:12.82#ibcon#flushed, iclass 7, count 0 2006.257.17:14:12.82#ibcon#about to write, iclass 7, count 0 2006.257.17:14:12.82#ibcon#wrote, iclass 7, count 0 2006.257.17:14:12.82#ibcon#about to read 3, iclass 7, count 0 2006.257.17:14:12.84#ibcon#read 3, iclass 7, count 0 2006.257.17:14:12.84#ibcon#about to read 4, iclass 7, count 0 2006.257.17:14:12.84#ibcon#read 4, iclass 7, count 0 2006.257.17:14:12.84#ibcon#about to read 5, iclass 7, count 0 2006.257.17:14:12.84#ibcon#read 5, iclass 7, count 0 2006.257.17:14:12.84#ibcon#about to read 6, iclass 7, count 0 2006.257.17:14:12.84#ibcon#read 6, iclass 7, count 0 2006.257.17:14:12.84#ibcon#end of sib2, iclass 7, count 0 2006.257.17:14:12.84#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:14:12.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:14:12.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:14:12.84#ibcon#*before write, iclass 7, count 0 2006.257.17:14:12.84#ibcon#enter sib2, iclass 7, count 0 2006.257.17:14:12.84#ibcon#flushed, iclass 7, count 0 2006.257.17:14:12.84#ibcon#about to write, iclass 7, count 0 2006.257.17:14:12.84#ibcon#wrote, iclass 7, count 0 2006.257.17:14:12.84#ibcon#about to read 3, iclass 7, count 0 2006.257.17:14:12.88#ibcon#read 3, iclass 7, count 0 2006.257.17:14:12.88#ibcon#about to read 4, iclass 7, count 0 2006.257.17:14:12.88#ibcon#read 4, iclass 7, count 0 2006.257.17:14:12.88#ibcon#about to read 5, iclass 7, count 0 2006.257.17:14:12.88#ibcon#read 5, iclass 7, count 0 2006.257.17:14:12.88#ibcon#about to read 6, iclass 7, count 0 2006.257.17:14:12.88#ibcon#read 6, iclass 7, count 0 2006.257.17:14:12.88#ibcon#end of sib2, iclass 7, count 0 2006.257.17:14:12.88#ibcon#*after write, iclass 7, count 0 2006.257.17:14:12.88#ibcon#*before return 0, iclass 7, count 0 2006.257.17:14:12.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:12.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:14:12.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:14:12.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:14:12.88$vck44/vb=6,4 2006.257.17:14:12.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.17:14:12.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.17:14:12.88#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:12.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:12.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:12.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:12.94#ibcon#enter wrdev, iclass 11, count 2 2006.257.17:14:12.94#ibcon#first serial, iclass 11, count 2 2006.257.17:14:12.94#ibcon#enter sib2, iclass 11, count 2 2006.257.17:14:12.94#ibcon#flushed, iclass 11, count 2 2006.257.17:14:12.94#ibcon#about to write, iclass 11, count 2 2006.257.17:14:12.94#ibcon#wrote, iclass 11, count 2 2006.257.17:14:12.94#ibcon#about to read 3, iclass 11, count 2 2006.257.17:14:12.96#ibcon#read 3, iclass 11, count 2 2006.257.17:14:12.96#ibcon#about to read 4, iclass 11, count 2 2006.257.17:14:12.96#ibcon#read 4, iclass 11, count 2 2006.257.17:14:12.96#ibcon#about to read 5, iclass 11, count 2 2006.257.17:14:12.96#ibcon#read 5, iclass 11, count 2 2006.257.17:14:12.96#ibcon#about to read 6, iclass 11, count 2 2006.257.17:14:12.96#ibcon#read 6, iclass 11, count 2 2006.257.17:14:12.96#ibcon#end of sib2, iclass 11, count 2 2006.257.17:14:12.96#ibcon#*mode == 0, iclass 11, count 2 2006.257.17:14:12.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.17:14:12.96#ibcon#[27=AT06-04\r\n] 2006.257.17:14:12.96#ibcon#*before write, iclass 11, count 2 2006.257.17:14:12.96#ibcon#enter sib2, iclass 11, count 2 2006.257.17:14:12.96#ibcon#flushed, iclass 11, count 2 2006.257.17:14:12.96#ibcon#about to write, iclass 11, count 2 2006.257.17:14:12.96#ibcon#wrote, iclass 11, count 2 2006.257.17:14:12.96#ibcon#about to read 3, iclass 11, count 2 2006.257.17:14:12.99#ibcon#read 3, iclass 11, count 2 2006.257.17:14:12.99#ibcon#about to read 4, iclass 11, count 2 2006.257.17:14:12.99#ibcon#read 4, iclass 11, count 2 2006.257.17:14:12.99#ibcon#about to read 5, iclass 11, count 2 2006.257.17:14:12.99#ibcon#read 5, iclass 11, count 2 2006.257.17:14:12.99#ibcon#about to read 6, iclass 11, count 2 2006.257.17:14:12.99#ibcon#read 6, iclass 11, count 2 2006.257.17:14:12.99#ibcon#end of sib2, iclass 11, count 2 2006.257.17:14:12.99#ibcon#*after write, iclass 11, count 2 2006.257.17:14:12.99#ibcon#*before return 0, iclass 11, count 2 2006.257.17:14:12.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:12.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:14:12.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.17:14:12.99#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:12.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:13.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:13.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:13.11#ibcon#enter wrdev, iclass 11, count 0 2006.257.17:14:13.11#ibcon#first serial, iclass 11, count 0 2006.257.17:14:13.11#ibcon#enter sib2, iclass 11, count 0 2006.257.17:14:13.11#ibcon#flushed, iclass 11, count 0 2006.257.17:14:13.11#ibcon#about to write, iclass 11, count 0 2006.257.17:14:13.11#ibcon#wrote, iclass 11, count 0 2006.257.17:14:13.11#ibcon#about to read 3, iclass 11, count 0 2006.257.17:14:13.13#ibcon#read 3, iclass 11, count 0 2006.257.17:14:13.13#ibcon#about to read 4, iclass 11, count 0 2006.257.17:14:13.13#ibcon#read 4, iclass 11, count 0 2006.257.17:14:13.13#ibcon#about to read 5, iclass 11, count 0 2006.257.17:14:13.13#ibcon#read 5, iclass 11, count 0 2006.257.17:14:13.13#ibcon#about to read 6, iclass 11, count 0 2006.257.17:14:13.13#ibcon#read 6, iclass 11, count 0 2006.257.17:14:13.13#ibcon#end of sib2, iclass 11, count 0 2006.257.17:14:13.13#ibcon#*mode == 0, iclass 11, count 0 2006.257.17:14:13.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.17:14:13.13#ibcon#[27=USB\r\n] 2006.257.17:14:13.13#ibcon#*before write, iclass 11, count 0 2006.257.17:14:13.13#ibcon#enter sib2, iclass 11, count 0 2006.257.17:14:13.13#ibcon#flushed, iclass 11, count 0 2006.257.17:14:13.13#ibcon#about to write, iclass 11, count 0 2006.257.17:14:13.13#ibcon#wrote, iclass 11, count 0 2006.257.17:14:13.13#ibcon#about to read 3, iclass 11, count 0 2006.257.17:14:13.16#ibcon#read 3, iclass 11, count 0 2006.257.17:14:13.16#ibcon#about to read 4, iclass 11, count 0 2006.257.17:14:13.16#ibcon#read 4, iclass 11, count 0 2006.257.17:14:13.16#ibcon#about to read 5, iclass 11, count 0 2006.257.17:14:13.16#ibcon#read 5, iclass 11, count 0 2006.257.17:14:13.16#ibcon#about to read 6, iclass 11, count 0 2006.257.17:14:13.16#ibcon#read 6, iclass 11, count 0 2006.257.17:14:13.16#ibcon#end of sib2, iclass 11, count 0 2006.257.17:14:13.16#ibcon#*after write, iclass 11, count 0 2006.257.17:14:13.16#ibcon#*before return 0, iclass 11, count 0 2006.257.17:14:13.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:13.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:14:13.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.17:14:13.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.17:14:13.16$vck44/vblo=7,734.99 2006.257.17:14:13.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.17:14:13.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.17:14:13.16#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:13.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:13.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:13.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:13.16#ibcon#enter wrdev, iclass 13, count 0 2006.257.17:14:13.16#ibcon#first serial, iclass 13, count 0 2006.257.17:14:13.16#ibcon#enter sib2, iclass 13, count 0 2006.257.17:14:13.16#ibcon#flushed, iclass 13, count 0 2006.257.17:14:13.16#ibcon#about to write, iclass 13, count 0 2006.257.17:14:13.16#ibcon#wrote, iclass 13, count 0 2006.257.17:14:13.16#ibcon#about to read 3, iclass 13, count 0 2006.257.17:14:13.18#ibcon#read 3, iclass 13, count 0 2006.257.17:14:13.18#ibcon#about to read 4, iclass 13, count 0 2006.257.17:14:13.18#ibcon#read 4, iclass 13, count 0 2006.257.17:14:13.18#ibcon#about to read 5, iclass 13, count 0 2006.257.17:14:13.18#ibcon#read 5, iclass 13, count 0 2006.257.17:14:13.18#ibcon#about to read 6, iclass 13, count 0 2006.257.17:14:13.18#ibcon#read 6, iclass 13, count 0 2006.257.17:14:13.18#ibcon#end of sib2, iclass 13, count 0 2006.257.17:14:13.18#ibcon#*mode == 0, iclass 13, count 0 2006.257.17:14:13.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.17:14:13.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:14:13.18#ibcon#*before write, iclass 13, count 0 2006.257.17:14:13.18#ibcon#enter sib2, iclass 13, count 0 2006.257.17:14:13.18#ibcon#flushed, iclass 13, count 0 2006.257.17:14:13.18#ibcon#about to write, iclass 13, count 0 2006.257.17:14:13.18#ibcon#wrote, iclass 13, count 0 2006.257.17:14:13.18#ibcon#about to read 3, iclass 13, count 0 2006.257.17:14:13.22#ibcon#read 3, iclass 13, count 0 2006.257.17:14:13.22#ibcon#about to read 4, iclass 13, count 0 2006.257.17:14:13.22#ibcon#read 4, iclass 13, count 0 2006.257.17:14:13.22#ibcon#about to read 5, iclass 13, count 0 2006.257.17:14:13.22#ibcon#read 5, iclass 13, count 0 2006.257.17:14:13.22#ibcon#about to read 6, iclass 13, count 0 2006.257.17:14:13.22#ibcon#read 6, iclass 13, count 0 2006.257.17:14:13.22#ibcon#end of sib2, iclass 13, count 0 2006.257.17:14:13.22#ibcon#*after write, iclass 13, count 0 2006.257.17:14:13.22#ibcon#*before return 0, iclass 13, count 0 2006.257.17:14:13.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:13.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:14:13.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.17:14:13.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.17:14:13.22$vck44/vb=7,4 2006.257.17:14:13.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.17:14:13.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.17:14:13.22#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:13.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:13.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:13.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:13.28#ibcon#enter wrdev, iclass 15, count 2 2006.257.17:14:13.28#ibcon#first serial, iclass 15, count 2 2006.257.17:14:13.28#ibcon#enter sib2, iclass 15, count 2 2006.257.17:14:13.28#ibcon#flushed, iclass 15, count 2 2006.257.17:14:13.28#ibcon#about to write, iclass 15, count 2 2006.257.17:14:13.28#ibcon#wrote, iclass 15, count 2 2006.257.17:14:13.28#ibcon#about to read 3, iclass 15, count 2 2006.257.17:14:13.30#ibcon#read 3, iclass 15, count 2 2006.257.17:14:13.30#ibcon#about to read 4, iclass 15, count 2 2006.257.17:14:13.30#ibcon#read 4, iclass 15, count 2 2006.257.17:14:13.30#ibcon#about to read 5, iclass 15, count 2 2006.257.17:14:13.30#ibcon#read 5, iclass 15, count 2 2006.257.17:14:13.30#ibcon#about to read 6, iclass 15, count 2 2006.257.17:14:13.30#ibcon#read 6, iclass 15, count 2 2006.257.17:14:13.30#ibcon#end of sib2, iclass 15, count 2 2006.257.17:14:13.30#ibcon#*mode == 0, iclass 15, count 2 2006.257.17:14:13.30#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.17:14:13.30#ibcon#[27=AT07-04\r\n] 2006.257.17:14:13.30#ibcon#*before write, iclass 15, count 2 2006.257.17:14:13.30#ibcon#enter sib2, iclass 15, count 2 2006.257.17:14:13.30#ibcon#flushed, iclass 15, count 2 2006.257.17:14:13.30#ibcon#about to write, iclass 15, count 2 2006.257.17:14:13.30#ibcon#wrote, iclass 15, count 2 2006.257.17:14:13.30#ibcon#about to read 3, iclass 15, count 2 2006.257.17:14:13.33#ibcon#read 3, iclass 15, count 2 2006.257.17:14:13.33#ibcon#about to read 4, iclass 15, count 2 2006.257.17:14:13.33#ibcon#read 4, iclass 15, count 2 2006.257.17:14:13.33#ibcon#about to read 5, iclass 15, count 2 2006.257.17:14:13.33#ibcon#read 5, iclass 15, count 2 2006.257.17:14:13.33#ibcon#about to read 6, iclass 15, count 2 2006.257.17:14:13.33#ibcon#read 6, iclass 15, count 2 2006.257.17:14:13.33#ibcon#end of sib2, iclass 15, count 2 2006.257.17:14:13.33#ibcon#*after write, iclass 15, count 2 2006.257.17:14:13.33#ibcon#*before return 0, iclass 15, count 2 2006.257.17:14:13.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:13.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:14:13.33#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.17:14:13.33#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:13.33#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:13.45#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:13.45#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:13.45#ibcon#enter wrdev, iclass 15, count 0 2006.257.17:14:13.45#ibcon#first serial, iclass 15, count 0 2006.257.17:14:13.45#ibcon#enter sib2, iclass 15, count 0 2006.257.17:14:13.45#ibcon#flushed, iclass 15, count 0 2006.257.17:14:13.45#ibcon#about to write, iclass 15, count 0 2006.257.17:14:13.45#ibcon#wrote, iclass 15, count 0 2006.257.17:14:13.45#ibcon#about to read 3, iclass 15, count 0 2006.257.17:14:13.47#ibcon#read 3, iclass 15, count 0 2006.257.17:14:13.47#ibcon#about to read 4, iclass 15, count 0 2006.257.17:14:13.47#ibcon#read 4, iclass 15, count 0 2006.257.17:14:13.47#ibcon#about to read 5, iclass 15, count 0 2006.257.17:14:13.47#ibcon#read 5, iclass 15, count 0 2006.257.17:14:13.47#ibcon#about to read 6, iclass 15, count 0 2006.257.17:14:13.47#ibcon#read 6, iclass 15, count 0 2006.257.17:14:13.47#ibcon#end of sib2, iclass 15, count 0 2006.257.17:14:13.47#ibcon#*mode == 0, iclass 15, count 0 2006.257.17:14:13.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.17:14:13.47#ibcon#[27=USB\r\n] 2006.257.17:14:13.47#ibcon#*before write, iclass 15, count 0 2006.257.17:14:13.47#ibcon#enter sib2, iclass 15, count 0 2006.257.17:14:13.47#ibcon#flushed, iclass 15, count 0 2006.257.17:14:13.47#ibcon#about to write, iclass 15, count 0 2006.257.17:14:13.47#ibcon#wrote, iclass 15, count 0 2006.257.17:14:13.47#ibcon#about to read 3, iclass 15, count 0 2006.257.17:14:13.50#ibcon#read 3, iclass 15, count 0 2006.257.17:14:13.50#ibcon#about to read 4, iclass 15, count 0 2006.257.17:14:13.50#ibcon#read 4, iclass 15, count 0 2006.257.17:14:13.50#ibcon#about to read 5, iclass 15, count 0 2006.257.17:14:13.50#ibcon#read 5, iclass 15, count 0 2006.257.17:14:13.50#ibcon#about to read 6, iclass 15, count 0 2006.257.17:14:13.50#ibcon#read 6, iclass 15, count 0 2006.257.17:14:13.50#ibcon#end of sib2, iclass 15, count 0 2006.257.17:14:13.50#ibcon#*after write, iclass 15, count 0 2006.257.17:14:13.50#ibcon#*before return 0, iclass 15, count 0 2006.257.17:14:13.50#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:13.50#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:14:13.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.17:14:13.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.17:14:13.50$vck44/vblo=8,744.99 2006.257.17:14:13.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.17:14:13.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.17:14:13.50#ibcon#ireg 17 cls_cnt 0 2006.257.17:14:13.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:13.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:13.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:13.50#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:14:13.50#ibcon#first serial, iclass 17, count 0 2006.257.17:14:13.50#ibcon#enter sib2, iclass 17, count 0 2006.257.17:14:13.50#ibcon#flushed, iclass 17, count 0 2006.257.17:14:13.50#ibcon#about to write, iclass 17, count 0 2006.257.17:14:13.50#ibcon#wrote, iclass 17, count 0 2006.257.17:14:13.50#ibcon#about to read 3, iclass 17, count 0 2006.257.17:14:13.52#ibcon#read 3, iclass 17, count 0 2006.257.17:14:13.52#ibcon#about to read 4, iclass 17, count 0 2006.257.17:14:13.52#ibcon#read 4, iclass 17, count 0 2006.257.17:14:13.52#ibcon#about to read 5, iclass 17, count 0 2006.257.17:14:13.52#ibcon#read 5, iclass 17, count 0 2006.257.17:14:13.52#ibcon#about to read 6, iclass 17, count 0 2006.257.17:14:13.52#ibcon#read 6, iclass 17, count 0 2006.257.17:14:13.52#ibcon#end of sib2, iclass 17, count 0 2006.257.17:14:13.52#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:14:13.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:14:13.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:14:13.52#ibcon#*before write, iclass 17, count 0 2006.257.17:14:13.52#ibcon#enter sib2, iclass 17, count 0 2006.257.17:14:13.52#ibcon#flushed, iclass 17, count 0 2006.257.17:14:13.52#ibcon#about to write, iclass 17, count 0 2006.257.17:14:13.52#ibcon#wrote, iclass 17, count 0 2006.257.17:14:13.52#ibcon#about to read 3, iclass 17, count 0 2006.257.17:14:13.56#ibcon#read 3, iclass 17, count 0 2006.257.17:14:13.56#ibcon#about to read 4, iclass 17, count 0 2006.257.17:14:13.56#ibcon#read 4, iclass 17, count 0 2006.257.17:14:13.56#ibcon#about to read 5, iclass 17, count 0 2006.257.17:14:13.56#ibcon#read 5, iclass 17, count 0 2006.257.17:14:13.56#ibcon#about to read 6, iclass 17, count 0 2006.257.17:14:13.56#ibcon#read 6, iclass 17, count 0 2006.257.17:14:13.56#ibcon#end of sib2, iclass 17, count 0 2006.257.17:14:13.56#ibcon#*after write, iclass 17, count 0 2006.257.17:14:13.56#ibcon#*before return 0, iclass 17, count 0 2006.257.17:14:13.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:13.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:14:13.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:14:13.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:14:13.56$vck44/vb=8,4 2006.257.17:14:13.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.17:14:13.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.17:14:13.56#ibcon#ireg 11 cls_cnt 2 2006.257.17:14:13.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:13.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:13.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:13.62#ibcon#enter wrdev, iclass 19, count 2 2006.257.17:14:13.62#ibcon#first serial, iclass 19, count 2 2006.257.17:14:13.62#ibcon#enter sib2, iclass 19, count 2 2006.257.17:14:13.62#ibcon#flushed, iclass 19, count 2 2006.257.17:14:13.62#ibcon#about to write, iclass 19, count 2 2006.257.17:14:13.62#ibcon#wrote, iclass 19, count 2 2006.257.17:14:13.62#ibcon#about to read 3, iclass 19, count 2 2006.257.17:14:13.64#ibcon#read 3, iclass 19, count 2 2006.257.17:14:13.64#ibcon#about to read 4, iclass 19, count 2 2006.257.17:14:13.64#ibcon#read 4, iclass 19, count 2 2006.257.17:14:13.64#ibcon#about to read 5, iclass 19, count 2 2006.257.17:14:13.64#ibcon#read 5, iclass 19, count 2 2006.257.17:14:13.64#ibcon#about to read 6, iclass 19, count 2 2006.257.17:14:13.64#ibcon#read 6, iclass 19, count 2 2006.257.17:14:13.64#ibcon#end of sib2, iclass 19, count 2 2006.257.17:14:13.64#ibcon#*mode == 0, iclass 19, count 2 2006.257.17:14:13.64#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.17:14:13.64#ibcon#[27=AT08-04\r\n] 2006.257.17:14:13.64#ibcon#*before write, iclass 19, count 2 2006.257.17:14:13.64#ibcon#enter sib2, iclass 19, count 2 2006.257.17:14:13.64#ibcon#flushed, iclass 19, count 2 2006.257.17:14:13.64#ibcon#about to write, iclass 19, count 2 2006.257.17:14:13.64#ibcon#wrote, iclass 19, count 2 2006.257.17:14:13.64#ibcon#about to read 3, iclass 19, count 2 2006.257.17:14:13.67#ibcon#read 3, iclass 19, count 2 2006.257.17:14:13.67#ibcon#about to read 4, iclass 19, count 2 2006.257.17:14:13.67#ibcon#read 4, iclass 19, count 2 2006.257.17:14:13.67#ibcon#about to read 5, iclass 19, count 2 2006.257.17:14:13.67#ibcon#read 5, iclass 19, count 2 2006.257.17:14:13.67#ibcon#about to read 6, iclass 19, count 2 2006.257.17:14:13.67#ibcon#read 6, iclass 19, count 2 2006.257.17:14:13.67#ibcon#end of sib2, iclass 19, count 2 2006.257.17:14:13.67#ibcon#*after write, iclass 19, count 2 2006.257.17:14:13.67#ibcon#*before return 0, iclass 19, count 2 2006.257.17:14:13.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:13.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:14:13.67#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.17:14:13.67#ibcon#ireg 7 cls_cnt 0 2006.257.17:14:13.67#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:13.79#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:13.79#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:13.79#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:14:13.79#ibcon#first serial, iclass 19, count 0 2006.257.17:14:13.79#ibcon#enter sib2, iclass 19, count 0 2006.257.17:14:13.79#ibcon#flushed, iclass 19, count 0 2006.257.17:14:13.79#ibcon#about to write, iclass 19, count 0 2006.257.17:14:13.79#ibcon#wrote, iclass 19, count 0 2006.257.17:14:13.79#ibcon#about to read 3, iclass 19, count 0 2006.257.17:14:13.81#ibcon#read 3, iclass 19, count 0 2006.257.17:14:13.81#ibcon#about to read 4, iclass 19, count 0 2006.257.17:14:13.81#ibcon#read 4, iclass 19, count 0 2006.257.17:14:13.81#ibcon#about to read 5, iclass 19, count 0 2006.257.17:14:13.81#ibcon#read 5, iclass 19, count 0 2006.257.17:14:13.81#ibcon#about to read 6, iclass 19, count 0 2006.257.17:14:13.81#ibcon#read 6, iclass 19, count 0 2006.257.17:14:13.81#ibcon#end of sib2, iclass 19, count 0 2006.257.17:14:13.81#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:14:13.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:14:13.81#ibcon#[27=USB\r\n] 2006.257.17:14:13.81#ibcon#*before write, iclass 19, count 0 2006.257.17:14:13.81#ibcon#enter sib2, iclass 19, count 0 2006.257.17:14:13.81#ibcon#flushed, iclass 19, count 0 2006.257.17:14:13.81#ibcon#about to write, iclass 19, count 0 2006.257.17:14:13.81#ibcon#wrote, iclass 19, count 0 2006.257.17:14:13.81#ibcon#about to read 3, iclass 19, count 0 2006.257.17:14:13.84#ibcon#read 3, iclass 19, count 0 2006.257.17:14:13.84#ibcon#about to read 4, iclass 19, count 0 2006.257.17:14:13.84#ibcon#read 4, iclass 19, count 0 2006.257.17:14:13.84#ibcon#about to read 5, iclass 19, count 0 2006.257.17:14:13.84#ibcon#read 5, iclass 19, count 0 2006.257.17:14:13.84#ibcon#about to read 6, iclass 19, count 0 2006.257.17:14:13.84#ibcon#read 6, iclass 19, count 0 2006.257.17:14:13.84#ibcon#end of sib2, iclass 19, count 0 2006.257.17:14:13.84#ibcon#*after write, iclass 19, count 0 2006.257.17:14:13.84#ibcon#*before return 0, iclass 19, count 0 2006.257.17:14:13.84#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:13.84#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:14:13.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:14:13.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:14:13.84$vck44/vabw=wide 2006.257.17:14:13.84#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.17:14:13.84#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.17:14:13.84#ibcon#ireg 8 cls_cnt 0 2006.257.17:14:13.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:13.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:13.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:13.84#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:14:13.84#ibcon#first serial, iclass 21, count 0 2006.257.17:14:13.84#ibcon#enter sib2, iclass 21, count 0 2006.257.17:14:13.84#ibcon#flushed, iclass 21, count 0 2006.257.17:14:13.84#ibcon#about to write, iclass 21, count 0 2006.257.17:14:13.84#ibcon#wrote, iclass 21, count 0 2006.257.17:14:13.84#ibcon#about to read 3, iclass 21, count 0 2006.257.17:14:13.86#ibcon#read 3, iclass 21, count 0 2006.257.17:14:13.86#ibcon#about to read 4, iclass 21, count 0 2006.257.17:14:13.86#ibcon#read 4, iclass 21, count 0 2006.257.17:14:13.86#ibcon#about to read 5, iclass 21, count 0 2006.257.17:14:13.86#ibcon#read 5, iclass 21, count 0 2006.257.17:14:13.86#ibcon#about to read 6, iclass 21, count 0 2006.257.17:14:13.86#ibcon#read 6, iclass 21, count 0 2006.257.17:14:13.86#ibcon#end of sib2, iclass 21, count 0 2006.257.17:14:13.86#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:14:13.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:14:13.86#ibcon#[25=BW32\r\n] 2006.257.17:14:13.86#ibcon#*before write, iclass 21, count 0 2006.257.17:14:13.86#ibcon#enter sib2, iclass 21, count 0 2006.257.17:14:13.86#ibcon#flushed, iclass 21, count 0 2006.257.17:14:13.86#ibcon#about to write, iclass 21, count 0 2006.257.17:14:13.86#ibcon#wrote, iclass 21, count 0 2006.257.17:14:13.86#ibcon#about to read 3, iclass 21, count 0 2006.257.17:14:13.89#ibcon#read 3, iclass 21, count 0 2006.257.17:14:13.89#ibcon#about to read 4, iclass 21, count 0 2006.257.17:14:13.89#ibcon#read 4, iclass 21, count 0 2006.257.17:14:13.89#ibcon#about to read 5, iclass 21, count 0 2006.257.17:14:13.89#ibcon#read 5, iclass 21, count 0 2006.257.17:14:13.89#ibcon#about to read 6, iclass 21, count 0 2006.257.17:14:13.89#ibcon#read 6, iclass 21, count 0 2006.257.17:14:13.89#ibcon#end of sib2, iclass 21, count 0 2006.257.17:14:13.89#ibcon#*after write, iclass 21, count 0 2006.257.17:14:13.89#ibcon#*before return 0, iclass 21, count 0 2006.257.17:14:13.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:13.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:14:13.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:14:13.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:14:13.89$vck44/vbbw=wide 2006.257.17:14:13.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.17:14:13.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.17:14:13.89#ibcon#ireg 8 cls_cnt 0 2006.257.17:14:13.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:14:13.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:14:13.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:14:13.96#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:14:13.96#ibcon#first serial, iclass 23, count 0 2006.257.17:14:13.96#ibcon#enter sib2, iclass 23, count 0 2006.257.17:14:13.96#ibcon#flushed, iclass 23, count 0 2006.257.17:14:13.96#ibcon#about to write, iclass 23, count 0 2006.257.17:14:13.96#ibcon#wrote, iclass 23, count 0 2006.257.17:14:13.96#ibcon#about to read 3, iclass 23, count 0 2006.257.17:14:13.98#ibcon#read 3, iclass 23, count 0 2006.257.17:14:13.98#ibcon#about to read 4, iclass 23, count 0 2006.257.17:14:13.98#ibcon#read 4, iclass 23, count 0 2006.257.17:14:13.98#ibcon#about to read 5, iclass 23, count 0 2006.257.17:14:13.98#ibcon#read 5, iclass 23, count 0 2006.257.17:14:13.98#ibcon#about to read 6, iclass 23, count 0 2006.257.17:14:13.98#ibcon#read 6, iclass 23, count 0 2006.257.17:14:13.98#ibcon#end of sib2, iclass 23, count 0 2006.257.17:14:13.98#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:14:13.98#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:14:13.98#ibcon#[27=BW32\r\n] 2006.257.17:14:13.98#ibcon#*before write, iclass 23, count 0 2006.257.17:14:13.98#ibcon#enter sib2, iclass 23, count 0 2006.257.17:14:13.98#ibcon#flushed, iclass 23, count 0 2006.257.17:14:13.98#ibcon#about to write, iclass 23, count 0 2006.257.17:14:13.98#ibcon#wrote, iclass 23, count 0 2006.257.17:14:13.98#ibcon#about to read 3, iclass 23, count 0 2006.257.17:14:14.01#ibcon#read 3, iclass 23, count 0 2006.257.17:14:14.01#ibcon#about to read 4, iclass 23, count 0 2006.257.17:14:14.01#ibcon#read 4, iclass 23, count 0 2006.257.17:14:14.01#ibcon#about to read 5, iclass 23, count 0 2006.257.17:14:14.01#ibcon#read 5, iclass 23, count 0 2006.257.17:14:14.01#ibcon#about to read 6, iclass 23, count 0 2006.257.17:14:14.01#ibcon#read 6, iclass 23, count 0 2006.257.17:14:14.01#ibcon#end of sib2, iclass 23, count 0 2006.257.17:14:14.01#ibcon#*after write, iclass 23, count 0 2006.257.17:14:14.01#ibcon#*before return 0, iclass 23, count 0 2006.257.17:14:14.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:14:14.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:14:14.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:14:14.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:14:14.01$setupk4/ifdk4 2006.257.17:14:14.01$ifdk4/lo= 2006.257.17:14:14.01$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:14:14.01$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:14:14.01$ifdk4/patch= 2006.257.17:14:14.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:14:14.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:14:14.01$setupk4/!*+20s 2006.257.17:14:15.44#abcon#<5=/14 1.5 4.0 17.37 971014.3\r\n> 2006.257.17:14:15.46#abcon#{5=INTERFACE CLEAR} 2006.257.17:14:15.52#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:14:20.14#trakl#Source acquired 2006.257.17:14:22.14#flagr#flagr/antenna,acquired 2006.257.17:14:25.61#abcon#<5=/14 1.4 4.0 17.37 971014.3\r\n> 2006.257.17:14:25.63#abcon#{5=INTERFACE CLEAR} 2006.257.17:14:25.69#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:14:28.52$setupk4/"tpicd 2006.257.17:14:28.52$setupk4/echo=off 2006.257.17:14:28.52$setupk4/xlog=off 2006.257.17:14:28.52:!2006.257.17:16:15 2006.257.17:16:15.00:preob 2006.257.17:16:15.14/onsource/TRACKING 2006.257.17:16:15.14:!2006.257.17:16:25 2006.257.17:16:25.00:"tape 2006.257.17:16:25.00:"st=record 2006.257.17:16:25.00:data_valid=on 2006.257.17:16:25.00:midob 2006.257.17:16:25.14/onsource/TRACKING 2006.257.17:16:25.14/wx/17.37,1014.3,97 2006.257.17:16:25.19/cable/+6.4876E-03 2006.257.17:16:26.28/va/01,08,usb,yes,35,38 2006.257.17:16:26.28/va/02,07,usb,yes,38,39 2006.257.17:16:26.28/va/03,08,usb,yes,35,37 2006.257.17:16:26.28/va/04,07,usb,yes,40,42 2006.257.17:16:26.28/va/05,04,usb,yes,35,36 2006.257.17:16:26.28/va/06,04,usb,yes,39,39 2006.257.17:16:26.28/va/07,04,usb,yes,40,41 2006.257.17:16:26.28/va/08,04,usb,yes,34,41 2006.257.17:16:26.51/valo/01,524.99,yes,locked 2006.257.17:16:26.51/valo/02,534.99,yes,locked 2006.257.17:16:26.51/valo/03,564.99,yes,locked 2006.257.17:16:26.51/valo/04,624.99,yes,locked 2006.257.17:16:26.51/valo/05,734.99,yes,locked 2006.257.17:16:26.51/valo/06,814.99,yes,locked 2006.257.17:16:26.51/valo/07,864.99,yes,locked 2006.257.17:16:26.51/valo/08,884.99,yes,locked 2006.257.17:16:27.60/vb/01,04,usb,yes,34,32 2006.257.17:16:27.60/vb/02,05,usb,yes,32,32 2006.257.17:16:27.60/vb/03,04,usb,yes,33,37 2006.257.17:16:27.60/vb/04,05,usb,yes,34,32 2006.257.17:16:27.60/vb/05,04,usb,yes,30,33 2006.257.17:16:27.60/vb/06,04,usb,yes,35,31 2006.257.17:16:27.60/vb/07,04,usb,yes,35,34 2006.257.17:16:27.60/vb/08,04,usb,yes,32,35 2006.257.17:16:27.84/vblo/01,629.99,yes,locked 2006.257.17:16:27.84/vblo/02,634.99,yes,locked 2006.257.17:16:27.84/vblo/03,649.99,yes,locked 2006.257.17:16:27.84/vblo/04,679.99,yes,locked 2006.257.17:16:27.84/vblo/05,709.99,yes,locked 2006.257.17:16:27.84/vblo/06,719.99,yes,locked 2006.257.17:16:27.84/vblo/07,734.99,yes,locked 2006.257.17:16:27.84/vblo/08,744.99,yes,locked 2006.257.17:16:27.99/vabw/8 2006.257.17:16:28.14/vbbw/8 2006.257.17:16:28.23/xfe/off,on,15.0 2006.257.17:16:28.63/ifatt/23,28,28,28 2006.257.17:16:29.08/fmout-gps/S +4.52E-07 2006.257.17:16:29.12:!2006.257.17:17:05 2006.257.17:17:05.01:data_valid=off 2006.257.17:17:05.01:"et 2006.257.17:17:05.01:!+3s 2006.257.17:17:08.02:"tape 2006.257.17:17:08.02:postob 2006.257.17:17:08.20/cable/+6.4861E-03 2006.257.17:17:08.20/wx/17.37,1014.3,97 2006.257.17:17:09.07/fmout-gps/S +4.52E-07 2006.257.17:17:09.07:scan_name=257-1727,jd0609,110 2006.257.17:17:09.07:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.257.17:17:10.14#flagr#flagr/antenna,new-source 2006.257.17:17:10.14:checkk5 2006.257.17:17:10.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:17:10.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:17:11.15/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:17:11.49/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:17:11.83/chk_obsdata//k5ts1/T2571716??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.17:17:12.16/chk_obsdata//k5ts2/T2571716??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.17:17:12.49/chk_obsdata//k5ts3/T2571716??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.17:17:12.82/chk_obsdata//k5ts4/T2571716??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.17:17:13.48/k5log//k5ts1_log_newline 2006.257.17:17:14.15/k5log//k5ts2_log_newline 2006.257.17:17:14.80/k5log//k5ts3_log_newline 2006.257.17:17:15.45/k5log//k5ts4_log_newline 2006.257.17:17:15.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:17:15.48:setupk4=1 2006.257.17:17:15.48$setupk4/echo=on 2006.257.17:17:15.48$setupk4/pcalon 2006.257.17:17:15.48$pcalon/"no phase cal control is implemented here 2006.257.17:17:15.48$setupk4/"tpicd=stop 2006.257.17:17:15.48$setupk4/"rec=synch_on 2006.257.17:17:15.48$setupk4/"rec_mode=128 2006.257.17:17:15.48$setupk4/!* 2006.257.17:17:15.48$setupk4/recpk4 2006.257.17:17:15.48$recpk4/recpatch= 2006.257.17:17:15.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:17:15.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:17:15.49$setupk4/vck44 2006.257.17:17:15.49$vck44/valo=1,524.99 2006.257.17:17:15.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.17:17:15.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.17:17:15.49#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:15.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:15.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:15.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:15.49#ibcon#enter wrdev, iclass 28, count 0 2006.257.17:17:15.49#ibcon#first serial, iclass 28, count 0 2006.257.17:17:15.49#ibcon#enter sib2, iclass 28, count 0 2006.257.17:17:15.49#ibcon#flushed, iclass 28, count 0 2006.257.17:17:15.49#ibcon#about to write, iclass 28, count 0 2006.257.17:17:15.49#ibcon#wrote, iclass 28, count 0 2006.257.17:17:15.49#ibcon#about to read 3, iclass 28, count 0 2006.257.17:17:15.50#ibcon#read 3, iclass 28, count 0 2006.257.17:17:15.50#ibcon#about to read 4, iclass 28, count 0 2006.257.17:17:15.50#ibcon#read 4, iclass 28, count 0 2006.257.17:17:15.50#ibcon#about to read 5, iclass 28, count 0 2006.257.17:17:15.50#ibcon#read 5, iclass 28, count 0 2006.257.17:17:15.50#ibcon#about to read 6, iclass 28, count 0 2006.257.17:17:15.50#ibcon#read 6, iclass 28, count 0 2006.257.17:17:15.50#ibcon#end of sib2, iclass 28, count 0 2006.257.17:17:15.50#ibcon#*mode == 0, iclass 28, count 0 2006.257.17:17:15.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.17:17:15.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:17:15.50#ibcon#*before write, iclass 28, count 0 2006.257.17:17:15.50#ibcon#enter sib2, iclass 28, count 0 2006.257.17:17:15.50#ibcon#flushed, iclass 28, count 0 2006.257.17:17:15.50#ibcon#about to write, iclass 28, count 0 2006.257.17:17:15.50#ibcon#wrote, iclass 28, count 0 2006.257.17:17:15.50#ibcon#about to read 3, iclass 28, count 0 2006.257.17:17:15.55#ibcon#read 3, iclass 28, count 0 2006.257.17:17:15.55#ibcon#about to read 4, iclass 28, count 0 2006.257.17:17:15.55#ibcon#read 4, iclass 28, count 0 2006.257.17:17:15.55#ibcon#about to read 5, iclass 28, count 0 2006.257.17:17:15.55#ibcon#read 5, iclass 28, count 0 2006.257.17:17:15.55#ibcon#about to read 6, iclass 28, count 0 2006.257.17:17:15.55#ibcon#read 6, iclass 28, count 0 2006.257.17:17:15.55#ibcon#end of sib2, iclass 28, count 0 2006.257.17:17:15.55#ibcon#*after write, iclass 28, count 0 2006.257.17:17:15.55#ibcon#*before return 0, iclass 28, count 0 2006.257.17:17:15.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:15.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:15.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.17:17:15.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.17:17:15.55$vck44/va=1,8 2006.257.17:17:15.55#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.17:17:15.55#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.17:17:15.55#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:15.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:17:15.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:17:15.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:17:15.55#ibcon#enter wrdev, iclass 30, count 2 2006.257.17:17:15.55#ibcon#first serial, iclass 30, count 2 2006.257.17:17:15.55#ibcon#enter sib2, iclass 30, count 2 2006.257.17:17:15.55#ibcon#flushed, iclass 30, count 2 2006.257.17:17:15.55#ibcon#about to write, iclass 30, count 2 2006.257.17:17:15.55#ibcon#wrote, iclass 30, count 2 2006.257.17:17:15.55#ibcon#about to read 3, iclass 30, count 2 2006.257.17:17:15.57#ibcon#read 3, iclass 30, count 2 2006.257.17:17:15.57#ibcon#about to read 4, iclass 30, count 2 2006.257.17:17:15.57#ibcon#read 4, iclass 30, count 2 2006.257.17:17:15.57#ibcon#about to read 5, iclass 30, count 2 2006.257.17:17:15.57#ibcon#read 5, iclass 30, count 2 2006.257.17:17:15.57#ibcon#about to read 6, iclass 30, count 2 2006.257.17:17:15.57#ibcon#read 6, iclass 30, count 2 2006.257.17:17:15.57#ibcon#end of sib2, iclass 30, count 2 2006.257.17:17:15.57#ibcon#*mode == 0, iclass 30, count 2 2006.257.17:17:15.57#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.17:17:15.57#ibcon#[25=AT01-08\r\n] 2006.257.17:17:15.57#ibcon#*before write, iclass 30, count 2 2006.257.17:17:15.57#ibcon#enter sib2, iclass 30, count 2 2006.257.17:17:15.57#ibcon#flushed, iclass 30, count 2 2006.257.17:17:15.57#ibcon#about to write, iclass 30, count 2 2006.257.17:17:15.57#ibcon#wrote, iclass 30, count 2 2006.257.17:17:15.57#ibcon#about to read 3, iclass 30, count 2 2006.257.17:17:15.60#ibcon#read 3, iclass 30, count 2 2006.257.17:17:15.60#ibcon#about to read 4, iclass 30, count 2 2006.257.17:17:15.60#ibcon#read 4, iclass 30, count 2 2006.257.17:17:15.60#ibcon#about to read 5, iclass 30, count 2 2006.257.17:17:15.60#ibcon#read 5, iclass 30, count 2 2006.257.17:17:15.60#ibcon#about to read 6, iclass 30, count 2 2006.257.17:17:15.60#ibcon#read 6, iclass 30, count 2 2006.257.17:17:15.60#ibcon#end of sib2, iclass 30, count 2 2006.257.17:17:15.60#ibcon#*after write, iclass 30, count 2 2006.257.17:17:15.60#ibcon#*before return 0, iclass 30, count 2 2006.257.17:17:15.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:17:15.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:17:15.60#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.17:17:15.60#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:15.60#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:17:15.72#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:17:15.72#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:17:15.72#ibcon#enter wrdev, iclass 30, count 0 2006.257.17:17:15.72#ibcon#first serial, iclass 30, count 0 2006.257.17:17:15.72#ibcon#enter sib2, iclass 30, count 0 2006.257.17:17:15.72#ibcon#flushed, iclass 30, count 0 2006.257.17:17:15.72#ibcon#about to write, iclass 30, count 0 2006.257.17:17:15.72#ibcon#wrote, iclass 30, count 0 2006.257.17:17:15.72#ibcon#about to read 3, iclass 30, count 0 2006.257.17:17:15.74#ibcon#read 3, iclass 30, count 0 2006.257.17:17:15.74#ibcon#about to read 4, iclass 30, count 0 2006.257.17:17:15.74#ibcon#read 4, iclass 30, count 0 2006.257.17:17:15.74#ibcon#about to read 5, iclass 30, count 0 2006.257.17:17:15.74#ibcon#read 5, iclass 30, count 0 2006.257.17:17:15.74#ibcon#about to read 6, iclass 30, count 0 2006.257.17:17:15.74#ibcon#read 6, iclass 30, count 0 2006.257.17:17:15.74#ibcon#end of sib2, iclass 30, count 0 2006.257.17:17:15.74#ibcon#*mode == 0, iclass 30, count 0 2006.257.17:17:15.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.17:17:15.74#ibcon#[25=USB\r\n] 2006.257.17:17:15.74#ibcon#*before write, iclass 30, count 0 2006.257.17:17:15.74#ibcon#enter sib2, iclass 30, count 0 2006.257.17:17:15.74#ibcon#flushed, iclass 30, count 0 2006.257.17:17:15.74#ibcon#about to write, iclass 30, count 0 2006.257.17:17:15.74#ibcon#wrote, iclass 30, count 0 2006.257.17:17:15.74#ibcon#about to read 3, iclass 30, count 0 2006.257.17:17:15.77#ibcon#read 3, iclass 30, count 0 2006.257.17:17:15.77#ibcon#about to read 4, iclass 30, count 0 2006.257.17:17:15.77#ibcon#read 4, iclass 30, count 0 2006.257.17:17:15.77#ibcon#about to read 5, iclass 30, count 0 2006.257.17:17:15.77#ibcon#read 5, iclass 30, count 0 2006.257.17:17:15.77#ibcon#about to read 6, iclass 30, count 0 2006.257.17:17:15.77#ibcon#read 6, iclass 30, count 0 2006.257.17:17:15.77#ibcon#end of sib2, iclass 30, count 0 2006.257.17:17:15.77#ibcon#*after write, iclass 30, count 0 2006.257.17:17:15.77#ibcon#*before return 0, iclass 30, count 0 2006.257.17:17:15.77#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:17:15.77#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:17:15.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.17:17:15.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.17:17:15.77$vck44/valo=2,534.99 2006.257.17:17:15.77#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.17:17:15.77#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.17:17:15.77#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:15.77#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:17:15.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:17:15.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:17:15.77#ibcon#enter wrdev, iclass 32, count 0 2006.257.17:17:15.77#ibcon#first serial, iclass 32, count 0 2006.257.17:17:15.77#ibcon#enter sib2, iclass 32, count 0 2006.257.17:17:15.77#ibcon#flushed, iclass 32, count 0 2006.257.17:17:15.77#ibcon#about to write, iclass 32, count 0 2006.257.17:17:15.77#ibcon#wrote, iclass 32, count 0 2006.257.17:17:15.77#ibcon#about to read 3, iclass 32, count 0 2006.257.17:17:15.79#ibcon#read 3, iclass 32, count 0 2006.257.17:17:15.79#ibcon#about to read 4, iclass 32, count 0 2006.257.17:17:15.79#ibcon#read 4, iclass 32, count 0 2006.257.17:17:15.79#ibcon#about to read 5, iclass 32, count 0 2006.257.17:17:15.79#ibcon#read 5, iclass 32, count 0 2006.257.17:17:15.79#ibcon#about to read 6, iclass 32, count 0 2006.257.17:17:15.79#ibcon#read 6, iclass 32, count 0 2006.257.17:17:15.79#ibcon#end of sib2, iclass 32, count 0 2006.257.17:17:15.79#ibcon#*mode == 0, iclass 32, count 0 2006.257.17:17:15.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.17:17:15.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:17:15.79#ibcon#*before write, iclass 32, count 0 2006.257.17:17:15.79#ibcon#enter sib2, iclass 32, count 0 2006.257.17:17:15.79#ibcon#flushed, iclass 32, count 0 2006.257.17:17:15.79#ibcon#about to write, iclass 32, count 0 2006.257.17:17:15.79#ibcon#wrote, iclass 32, count 0 2006.257.17:17:15.79#ibcon#about to read 3, iclass 32, count 0 2006.257.17:17:15.83#ibcon#read 3, iclass 32, count 0 2006.257.17:17:15.83#ibcon#about to read 4, iclass 32, count 0 2006.257.17:17:15.83#ibcon#read 4, iclass 32, count 0 2006.257.17:17:15.83#ibcon#about to read 5, iclass 32, count 0 2006.257.17:17:15.83#ibcon#read 5, iclass 32, count 0 2006.257.17:17:15.83#ibcon#about to read 6, iclass 32, count 0 2006.257.17:17:15.83#ibcon#read 6, iclass 32, count 0 2006.257.17:17:15.83#ibcon#end of sib2, iclass 32, count 0 2006.257.17:17:15.83#ibcon#*after write, iclass 32, count 0 2006.257.17:17:15.83#ibcon#*before return 0, iclass 32, count 0 2006.257.17:17:15.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:17:15.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:17:15.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.17:17:15.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.17:17:15.83$vck44/va=2,7 2006.257.17:17:15.83#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.17:17:15.83#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.17:17:15.83#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:15.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:17:15.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:17:15.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:17:15.89#ibcon#enter wrdev, iclass 34, count 2 2006.257.17:17:15.89#ibcon#first serial, iclass 34, count 2 2006.257.17:17:15.89#ibcon#enter sib2, iclass 34, count 2 2006.257.17:17:15.89#ibcon#flushed, iclass 34, count 2 2006.257.17:17:15.89#ibcon#about to write, iclass 34, count 2 2006.257.17:17:15.89#ibcon#wrote, iclass 34, count 2 2006.257.17:17:15.89#ibcon#about to read 3, iclass 34, count 2 2006.257.17:17:15.91#ibcon#read 3, iclass 34, count 2 2006.257.17:17:15.91#ibcon#about to read 4, iclass 34, count 2 2006.257.17:17:15.91#ibcon#read 4, iclass 34, count 2 2006.257.17:17:15.91#ibcon#about to read 5, iclass 34, count 2 2006.257.17:17:15.91#ibcon#read 5, iclass 34, count 2 2006.257.17:17:15.91#ibcon#about to read 6, iclass 34, count 2 2006.257.17:17:15.91#ibcon#read 6, iclass 34, count 2 2006.257.17:17:15.91#ibcon#end of sib2, iclass 34, count 2 2006.257.17:17:15.91#ibcon#*mode == 0, iclass 34, count 2 2006.257.17:17:15.91#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.17:17:15.91#ibcon#[25=AT02-07\r\n] 2006.257.17:17:15.91#ibcon#*before write, iclass 34, count 2 2006.257.17:17:15.91#ibcon#enter sib2, iclass 34, count 2 2006.257.17:17:15.91#ibcon#flushed, iclass 34, count 2 2006.257.17:17:15.91#ibcon#about to write, iclass 34, count 2 2006.257.17:17:15.91#ibcon#wrote, iclass 34, count 2 2006.257.17:17:15.91#ibcon#about to read 3, iclass 34, count 2 2006.257.17:17:15.94#ibcon#read 3, iclass 34, count 2 2006.257.17:17:15.94#ibcon#about to read 4, iclass 34, count 2 2006.257.17:17:15.94#ibcon#read 4, iclass 34, count 2 2006.257.17:17:15.94#ibcon#about to read 5, iclass 34, count 2 2006.257.17:17:15.94#ibcon#read 5, iclass 34, count 2 2006.257.17:17:15.94#ibcon#about to read 6, iclass 34, count 2 2006.257.17:17:15.94#ibcon#read 6, iclass 34, count 2 2006.257.17:17:15.94#ibcon#end of sib2, iclass 34, count 2 2006.257.17:17:15.94#ibcon#*after write, iclass 34, count 2 2006.257.17:17:15.94#ibcon#*before return 0, iclass 34, count 2 2006.257.17:17:15.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:17:15.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:17:15.94#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.17:17:15.94#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:15.94#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:17:16.06#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:17:16.06#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:17:16.06#ibcon#enter wrdev, iclass 34, count 0 2006.257.17:17:16.06#ibcon#first serial, iclass 34, count 0 2006.257.17:17:16.06#ibcon#enter sib2, iclass 34, count 0 2006.257.17:17:16.06#ibcon#flushed, iclass 34, count 0 2006.257.17:17:16.06#ibcon#about to write, iclass 34, count 0 2006.257.17:17:16.06#ibcon#wrote, iclass 34, count 0 2006.257.17:17:16.06#ibcon#about to read 3, iclass 34, count 0 2006.257.17:17:16.08#ibcon#read 3, iclass 34, count 0 2006.257.17:17:16.08#ibcon#about to read 4, iclass 34, count 0 2006.257.17:17:16.08#ibcon#read 4, iclass 34, count 0 2006.257.17:17:16.08#ibcon#about to read 5, iclass 34, count 0 2006.257.17:17:16.08#ibcon#read 5, iclass 34, count 0 2006.257.17:17:16.08#ibcon#about to read 6, iclass 34, count 0 2006.257.17:17:16.08#ibcon#read 6, iclass 34, count 0 2006.257.17:17:16.08#ibcon#end of sib2, iclass 34, count 0 2006.257.17:17:16.08#ibcon#*mode == 0, iclass 34, count 0 2006.257.17:17:16.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.17:17:16.08#ibcon#[25=USB\r\n] 2006.257.17:17:16.08#ibcon#*before write, iclass 34, count 0 2006.257.17:17:16.08#ibcon#enter sib2, iclass 34, count 0 2006.257.17:17:16.08#ibcon#flushed, iclass 34, count 0 2006.257.17:17:16.08#ibcon#about to write, iclass 34, count 0 2006.257.17:17:16.08#ibcon#wrote, iclass 34, count 0 2006.257.17:17:16.08#ibcon#about to read 3, iclass 34, count 0 2006.257.17:17:16.11#ibcon#read 3, iclass 34, count 0 2006.257.17:17:16.11#ibcon#about to read 4, iclass 34, count 0 2006.257.17:17:16.11#ibcon#read 4, iclass 34, count 0 2006.257.17:17:16.11#ibcon#about to read 5, iclass 34, count 0 2006.257.17:17:16.11#ibcon#read 5, iclass 34, count 0 2006.257.17:17:16.11#ibcon#about to read 6, iclass 34, count 0 2006.257.17:17:16.11#ibcon#read 6, iclass 34, count 0 2006.257.17:17:16.11#ibcon#end of sib2, iclass 34, count 0 2006.257.17:17:16.11#ibcon#*after write, iclass 34, count 0 2006.257.17:17:16.11#ibcon#*before return 0, iclass 34, count 0 2006.257.17:17:16.11#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:17:16.11#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:17:16.11#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.17:17:16.11#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.17:17:16.11$vck44/valo=3,564.99 2006.257.17:17:16.11#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.17:17:16.11#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.17:17:16.11#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:16.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:16.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:16.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:16.11#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:17:16.11#ibcon#first serial, iclass 36, count 0 2006.257.17:17:16.11#ibcon#enter sib2, iclass 36, count 0 2006.257.17:17:16.11#ibcon#flushed, iclass 36, count 0 2006.257.17:17:16.11#ibcon#about to write, iclass 36, count 0 2006.257.17:17:16.11#ibcon#wrote, iclass 36, count 0 2006.257.17:17:16.11#ibcon#about to read 3, iclass 36, count 0 2006.257.17:17:16.13#ibcon#read 3, iclass 36, count 0 2006.257.17:17:16.13#ibcon#about to read 4, iclass 36, count 0 2006.257.17:17:16.13#ibcon#read 4, iclass 36, count 0 2006.257.17:17:16.13#ibcon#about to read 5, iclass 36, count 0 2006.257.17:17:16.13#ibcon#read 5, iclass 36, count 0 2006.257.17:17:16.13#ibcon#about to read 6, iclass 36, count 0 2006.257.17:17:16.13#ibcon#read 6, iclass 36, count 0 2006.257.17:17:16.13#ibcon#end of sib2, iclass 36, count 0 2006.257.17:17:16.13#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:17:16.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:17:16.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:17:16.13#ibcon#*before write, iclass 36, count 0 2006.257.17:17:16.13#ibcon#enter sib2, iclass 36, count 0 2006.257.17:17:16.13#ibcon#flushed, iclass 36, count 0 2006.257.17:17:16.13#ibcon#about to write, iclass 36, count 0 2006.257.17:17:16.13#ibcon#wrote, iclass 36, count 0 2006.257.17:17:16.13#ibcon#about to read 3, iclass 36, count 0 2006.257.17:17:16.17#ibcon#read 3, iclass 36, count 0 2006.257.17:17:16.17#ibcon#about to read 4, iclass 36, count 0 2006.257.17:17:16.17#ibcon#read 4, iclass 36, count 0 2006.257.17:17:16.17#ibcon#about to read 5, iclass 36, count 0 2006.257.17:17:16.17#ibcon#read 5, iclass 36, count 0 2006.257.17:17:16.17#ibcon#about to read 6, iclass 36, count 0 2006.257.17:17:16.17#ibcon#read 6, iclass 36, count 0 2006.257.17:17:16.17#ibcon#end of sib2, iclass 36, count 0 2006.257.17:17:16.17#ibcon#*after write, iclass 36, count 0 2006.257.17:17:16.17#ibcon#*before return 0, iclass 36, count 0 2006.257.17:17:16.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:16.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:16.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:17:16.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:17:16.17$vck44/va=3,8 2006.257.17:17:16.17#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.17:17:16.17#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.17:17:16.17#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:16.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:16.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:16.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:16.23#ibcon#enter wrdev, iclass 38, count 2 2006.257.17:17:16.23#ibcon#first serial, iclass 38, count 2 2006.257.17:17:16.23#ibcon#enter sib2, iclass 38, count 2 2006.257.17:17:16.23#ibcon#flushed, iclass 38, count 2 2006.257.17:17:16.23#ibcon#about to write, iclass 38, count 2 2006.257.17:17:16.23#ibcon#wrote, iclass 38, count 2 2006.257.17:17:16.23#ibcon#about to read 3, iclass 38, count 2 2006.257.17:17:16.25#ibcon#read 3, iclass 38, count 2 2006.257.17:17:16.25#ibcon#about to read 4, iclass 38, count 2 2006.257.17:17:16.25#ibcon#read 4, iclass 38, count 2 2006.257.17:17:16.25#ibcon#about to read 5, iclass 38, count 2 2006.257.17:17:16.25#ibcon#read 5, iclass 38, count 2 2006.257.17:17:16.25#ibcon#about to read 6, iclass 38, count 2 2006.257.17:17:16.25#ibcon#read 6, iclass 38, count 2 2006.257.17:17:16.25#ibcon#end of sib2, iclass 38, count 2 2006.257.17:17:16.25#ibcon#*mode == 0, iclass 38, count 2 2006.257.17:17:16.25#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.17:17:16.25#ibcon#[25=AT03-08\r\n] 2006.257.17:17:16.25#ibcon#*before write, iclass 38, count 2 2006.257.17:17:16.25#ibcon#enter sib2, iclass 38, count 2 2006.257.17:17:16.25#ibcon#flushed, iclass 38, count 2 2006.257.17:17:16.25#ibcon#about to write, iclass 38, count 2 2006.257.17:17:16.25#ibcon#wrote, iclass 38, count 2 2006.257.17:17:16.25#ibcon#about to read 3, iclass 38, count 2 2006.257.17:17:16.28#ibcon#read 3, iclass 38, count 2 2006.257.17:17:16.28#ibcon#about to read 4, iclass 38, count 2 2006.257.17:17:16.28#ibcon#read 4, iclass 38, count 2 2006.257.17:17:16.28#ibcon#about to read 5, iclass 38, count 2 2006.257.17:17:16.28#ibcon#read 5, iclass 38, count 2 2006.257.17:17:16.28#ibcon#about to read 6, iclass 38, count 2 2006.257.17:17:16.28#ibcon#read 6, iclass 38, count 2 2006.257.17:17:16.28#ibcon#end of sib2, iclass 38, count 2 2006.257.17:17:16.28#ibcon#*after write, iclass 38, count 2 2006.257.17:17:16.28#ibcon#*before return 0, iclass 38, count 2 2006.257.17:17:16.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:16.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:16.28#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.17:17:16.28#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:16.28#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:16.40#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:16.40#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:16.40#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:17:16.40#ibcon#first serial, iclass 38, count 0 2006.257.17:17:16.40#ibcon#enter sib2, iclass 38, count 0 2006.257.17:17:16.40#ibcon#flushed, iclass 38, count 0 2006.257.17:17:16.40#ibcon#about to write, iclass 38, count 0 2006.257.17:17:16.40#ibcon#wrote, iclass 38, count 0 2006.257.17:17:16.40#ibcon#about to read 3, iclass 38, count 0 2006.257.17:17:16.42#ibcon#read 3, iclass 38, count 0 2006.257.17:17:16.42#ibcon#about to read 4, iclass 38, count 0 2006.257.17:17:16.42#ibcon#read 4, iclass 38, count 0 2006.257.17:17:16.42#ibcon#about to read 5, iclass 38, count 0 2006.257.17:17:16.42#ibcon#read 5, iclass 38, count 0 2006.257.17:17:16.42#ibcon#about to read 6, iclass 38, count 0 2006.257.17:17:16.42#ibcon#read 6, iclass 38, count 0 2006.257.17:17:16.42#ibcon#end of sib2, iclass 38, count 0 2006.257.17:17:16.42#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:17:16.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:17:16.42#ibcon#[25=USB\r\n] 2006.257.17:17:16.42#ibcon#*before write, iclass 38, count 0 2006.257.17:17:16.42#ibcon#enter sib2, iclass 38, count 0 2006.257.17:17:16.42#ibcon#flushed, iclass 38, count 0 2006.257.17:17:16.42#ibcon#about to write, iclass 38, count 0 2006.257.17:17:16.42#ibcon#wrote, iclass 38, count 0 2006.257.17:17:16.42#ibcon#about to read 3, iclass 38, count 0 2006.257.17:17:16.45#ibcon#read 3, iclass 38, count 0 2006.257.17:17:16.45#ibcon#about to read 4, iclass 38, count 0 2006.257.17:17:16.45#ibcon#read 4, iclass 38, count 0 2006.257.17:17:16.45#ibcon#about to read 5, iclass 38, count 0 2006.257.17:17:16.45#ibcon#read 5, iclass 38, count 0 2006.257.17:17:16.45#ibcon#about to read 6, iclass 38, count 0 2006.257.17:17:16.45#ibcon#read 6, iclass 38, count 0 2006.257.17:17:16.45#ibcon#end of sib2, iclass 38, count 0 2006.257.17:17:16.45#ibcon#*after write, iclass 38, count 0 2006.257.17:17:16.45#ibcon#*before return 0, iclass 38, count 0 2006.257.17:17:16.45#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:16.45#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:16.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:17:16.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:17:16.45$vck44/valo=4,624.99 2006.257.17:17:16.45#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.17:17:16.45#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.17:17:16.45#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:16.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:16.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:16.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:16.45#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:17:16.45#ibcon#first serial, iclass 40, count 0 2006.257.17:17:16.45#ibcon#enter sib2, iclass 40, count 0 2006.257.17:17:16.45#ibcon#flushed, iclass 40, count 0 2006.257.17:17:16.45#ibcon#about to write, iclass 40, count 0 2006.257.17:17:16.45#ibcon#wrote, iclass 40, count 0 2006.257.17:17:16.45#ibcon#about to read 3, iclass 40, count 0 2006.257.17:17:16.47#ibcon#read 3, iclass 40, count 0 2006.257.17:17:16.47#ibcon#about to read 4, iclass 40, count 0 2006.257.17:17:16.47#ibcon#read 4, iclass 40, count 0 2006.257.17:17:16.47#ibcon#about to read 5, iclass 40, count 0 2006.257.17:17:16.47#ibcon#read 5, iclass 40, count 0 2006.257.17:17:16.47#ibcon#about to read 6, iclass 40, count 0 2006.257.17:17:16.47#ibcon#read 6, iclass 40, count 0 2006.257.17:17:16.47#ibcon#end of sib2, iclass 40, count 0 2006.257.17:17:16.47#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:17:16.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:17:16.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:17:16.47#ibcon#*before write, iclass 40, count 0 2006.257.17:17:16.47#ibcon#enter sib2, iclass 40, count 0 2006.257.17:17:16.47#ibcon#flushed, iclass 40, count 0 2006.257.17:17:16.47#ibcon#about to write, iclass 40, count 0 2006.257.17:17:16.47#ibcon#wrote, iclass 40, count 0 2006.257.17:17:16.47#ibcon#about to read 3, iclass 40, count 0 2006.257.17:17:16.51#ibcon#read 3, iclass 40, count 0 2006.257.17:17:16.51#ibcon#about to read 4, iclass 40, count 0 2006.257.17:17:16.51#ibcon#read 4, iclass 40, count 0 2006.257.17:17:16.51#ibcon#about to read 5, iclass 40, count 0 2006.257.17:17:16.51#ibcon#read 5, iclass 40, count 0 2006.257.17:17:16.51#ibcon#about to read 6, iclass 40, count 0 2006.257.17:17:16.51#ibcon#read 6, iclass 40, count 0 2006.257.17:17:16.51#ibcon#end of sib2, iclass 40, count 0 2006.257.17:17:16.51#ibcon#*after write, iclass 40, count 0 2006.257.17:17:16.51#ibcon#*before return 0, iclass 40, count 0 2006.257.17:17:16.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:16.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:16.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:17:16.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:17:16.51$vck44/va=4,7 2006.257.17:17:16.51#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.17:17:16.51#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.17:17:16.51#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:16.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:16.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:16.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:16.57#ibcon#enter wrdev, iclass 4, count 2 2006.257.17:17:16.57#ibcon#first serial, iclass 4, count 2 2006.257.17:17:16.57#ibcon#enter sib2, iclass 4, count 2 2006.257.17:17:16.57#ibcon#flushed, iclass 4, count 2 2006.257.17:17:16.57#ibcon#about to write, iclass 4, count 2 2006.257.17:17:16.57#ibcon#wrote, iclass 4, count 2 2006.257.17:17:16.57#ibcon#about to read 3, iclass 4, count 2 2006.257.17:17:16.59#ibcon#read 3, iclass 4, count 2 2006.257.17:17:16.59#ibcon#about to read 4, iclass 4, count 2 2006.257.17:17:16.59#ibcon#read 4, iclass 4, count 2 2006.257.17:17:16.59#ibcon#about to read 5, iclass 4, count 2 2006.257.17:17:16.59#ibcon#read 5, iclass 4, count 2 2006.257.17:17:16.59#ibcon#about to read 6, iclass 4, count 2 2006.257.17:17:16.59#ibcon#read 6, iclass 4, count 2 2006.257.17:17:16.59#ibcon#end of sib2, iclass 4, count 2 2006.257.17:17:16.59#ibcon#*mode == 0, iclass 4, count 2 2006.257.17:17:16.59#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.17:17:16.59#ibcon#[25=AT04-07\r\n] 2006.257.17:17:16.59#ibcon#*before write, iclass 4, count 2 2006.257.17:17:16.59#ibcon#enter sib2, iclass 4, count 2 2006.257.17:17:16.59#ibcon#flushed, iclass 4, count 2 2006.257.17:17:16.59#ibcon#about to write, iclass 4, count 2 2006.257.17:17:16.59#ibcon#wrote, iclass 4, count 2 2006.257.17:17:16.59#ibcon#about to read 3, iclass 4, count 2 2006.257.17:17:16.62#ibcon#read 3, iclass 4, count 2 2006.257.17:17:16.62#ibcon#about to read 4, iclass 4, count 2 2006.257.17:17:16.62#ibcon#read 4, iclass 4, count 2 2006.257.17:17:16.62#ibcon#about to read 5, iclass 4, count 2 2006.257.17:17:16.62#ibcon#read 5, iclass 4, count 2 2006.257.17:17:16.62#ibcon#about to read 6, iclass 4, count 2 2006.257.17:17:16.62#ibcon#read 6, iclass 4, count 2 2006.257.17:17:16.62#ibcon#end of sib2, iclass 4, count 2 2006.257.17:17:16.62#ibcon#*after write, iclass 4, count 2 2006.257.17:17:16.62#ibcon#*before return 0, iclass 4, count 2 2006.257.17:17:16.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:16.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:16.62#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.17:17:16.62#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:16.62#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:16.74#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:16.74#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:16.74#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:17:16.74#ibcon#first serial, iclass 4, count 0 2006.257.17:17:16.74#ibcon#enter sib2, iclass 4, count 0 2006.257.17:17:16.74#ibcon#flushed, iclass 4, count 0 2006.257.17:17:16.74#ibcon#about to write, iclass 4, count 0 2006.257.17:17:16.74#ibcon#wrote, iclass 4, count 0 2006.257.17:17:16.74#ibcon#about to read 3, iclass 4, count 0 2006.257.17:17:16.76#ibcon#read 3, iclass 4, count 0 2006.257.17:17:16.76#ibcon#about to read 4, iclass 4, count 0 2006.257.17:17:16.76#ibcon#read 4, iclass 4, count 0 2006.257.17:17:16.76#ibcon#about to read 5, iclass 4, count 0 2006.257.17:17:16.76#ibcon#read 5, iclass 4, count 0 2006.257.17:17:16.76#ibcon#about to read 6, iclass 4, count 0 2006.257.17:17:16.76#ibcon#read 6, iclass 4, count 0 2006.257.17:17:16.76#ibcon#end of sib2, iclass 4, count 0 2006.257.17:17:16.76#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:17:16.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:17:16.76#ibcon#[25=USB\r\n] 2006.257.17:17:16.76#ibcon#*before write, iclass 4, count 0 2006.257.17:17:16.76#ibcon#enter sib2, iclass 4, count 0 2006.257.17:17:16.76#ibcon#flushed, iclass 4, count 0 2006.257.17:17:16.76#ibcon#about to write, iclass 4, count 0 2006.257.17:17:16.76#ibcon#wrote, iclass 4, count 0 2006.257.17:17:16.76#ibcon#about to read 3, iclass 4, count 0 2006.257.17:17:16.79#ibcon#read 3, iclass 4, count 0 2006.257.17:17:16.79#ibcon#about to read 4, iclass 4, count 0 2006.257.17:17:16.79#ibcon#read 4, iclass 4, count 0 2006.257.17:17:16.79#ibcon#about to read 5, iclass 4, count 0 2006.257.17:17:16.79#ibcon#read 5, iclass 4, count 0 2006.257.17:17:16.79#ibcon#about to read 6, iclass 4, count 0 2006.257.17:17:16.79#ibcon#read 6, iclass 4, count 0 2006.257.17:17:16.79#ibcon#end of sib2, iclass 4, count 0 2006.257.17:17:16.79#ibcon#*after write, iclass 4, count 0 2006.257.17:17:16.79#ibcon#*before return 0, iclass 4, count 0 2006.257.17:17:16.79#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:16.79#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:16.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:17:16.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:17:16.79$vck44/valo=5,734.99 2006.257.17:17:16.79#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.17:17:16.79#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.17:17:16.79#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:16.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:16.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:16.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:16.79#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:17:16.79#ibcon#first serial, iclass 6, count 0 2006.257.17:17:16.79#ibcon#enter sib2, iclass 6, count 0 2006.257.17:17:16.79#ibcon#flushed, iclass 6, count 0 2006.257.17:17:16.79#ibcon#about to write, iclass 6, count 0 2006.257.17:17:16.79#ibcon#wrote, iclass 6, count 0 2006.257.17:17:16.79#ibcon#about to read 3, iclass 6, count 0 2006.257.17:17:16.81#ibcon#read 3, iclass 6, count 0 2006.257.17:17:16.81#ibcon#about to read 4, iclass 6, count 0 2006.257.17:17:16.81#ibcon#read 4, iclass 6, count 0 2006.257.17:17:16.81#ibcon#about to read 5, iclass 6, count 0 2006.257.17:17:16.81#ibcon#read 5, iclass 6, count 0 2006.257.17:17:16.81#ibcon#about to read 6, iclass 6, count 0 2006.257.17:17:16.81#ibcon#read 6, iclass 6, count 0 2006.257.17:17:16.81#ibcon#end of sib2, iclass 6, count 0 2006.257.17:17:16.81#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:17:16.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:17:16.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:17:16.81#ibcon#*before write, iclass 6, count 0 2006.257.17:17:16.81#ibcon#enter sib2, iclass 6, count 0 2006.257.17:17:16.81#ibcon#flushed, iclass 6, count 0 2006.257.17:17:16.81#ibcon#about to write, iclass 6, count 0 2006.257.17:17:16.81#ibcon#wrote, iclass 6, count 0 2006.257.17:17:16.81#ibcon#about to read 3, iclass 6, count 0 2006.257.17:17:16.85#ibcon#read 3, iclass 6, count 0 2006.257.17:17:16.85#ibcon#about to read 4, iclass 6, count 0 2006.257.17:17:16.85#ibcon#read 4, iclass 6, count 0 2006.257.17:17:16.85#ibcon#about to read 5, iclass 6, count 0 2006.257.17:17:16.85#ibcon#read 5, iclass 6, count 0 2006.257.17:17:16.85#ibcon#about to read 6, iclass 6, count 0 2006.257.17:17:16.85#ibcon#read 6, iclass 6, count 0 2006.257.17:17:16.85#ibcon#end of sib2, iclass 6, count 0 2006.257.17:17:16.85#ibcon#*after write, iclass 6, count 0 2006.257.17:17:16.85#ibcon#*before return 0, iclass 6, count 0 2006.257.17:17:16.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:16.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:16.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:17:16.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:17:16.85$vck44/va=5,4 2006.257.17:17:16.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.17:17:16.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.17:17:16.85#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:16.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:16.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:16.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:16.91#ibcon#enter wrdev, iclass 10, count 2 2006.257.17:17:16.91#ibcon#first serial, iclass 10, count 2 2006.257.17:17:16.91#ibcon#enter sib2, iclass 10, count 2 2006.257.17:17:16.91#ibcon#flushed, iclass 10, count 2 2006.257.17:17:16.91#ibcon#about to write, iclass 10, count 2 2006.257.17:17:16.91#ibcon#wrote, iclass 10, count 2 2006.257.17:17:16.91#ibcon#about to read 3, iclass 10, count 2 2006.257.17:17:16.93#ibcon#read 3, iclass 10, count 2 2006.257.17:17:16.93#ibcon#about to read 4, iclass 10, count 2 2006.257.17:17:16.93#ibcon#read 4, iclass 10, count 2 2006.257.17:17:16.93#ibcon#about to read 5, iclass 10, count 2 2006.257.17:17:16.93#ibcon#read 5, iclass 10, count 2 2006.257.17:17:16.93#ibcon#about to read 6, iclass 10, count 2 2006.257.17:17:16.93#ibcon#read 6, iclass 10, count 2 2006.257.17:17:16.93#ibcon#end of sib2, iclass 10, count 2 2006.257.17:17:16.93#ibcon#*mode == 0, iclass 10, count 2 2006.257.17:17:16.93#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.17:17:16.93#ibcon#[25=AT05-04\r\n] 2006.257.17:17:16.93#ibcon#*before write, iclass 10, count 2 2006.257.17:17:16.93#ibcon#enter sib2, iclass 10, count 2 2006.257.17:17:16.93#ibcon#flushed, iclass 10, count 2 2006.257.17:17:16.93#ibcon#about to write, iclass 10, count 2 2006.257.17:17:16.93#ibcon#wrote, iclass 10, count 2 2006.257.17:17:16.93#ibcon#about to read 3, iclass 10, count 2 2006.257.17:17:16.96#ibcon#read 3, iclass 10, count 2 2006.257.17:17:16.96#ibcon#about to read 4, iclass 10, count 2 2006.257.17:17:16.96#ibcon#read 4, iclass 10, count 2 2006.257.17:17:16.96#ibcon#about to read 5, iclass 10, count 2 2006.257.17:17:16.96#ibcon#read 5, iclass 10, count 2 2006.257.17:17:16.96#ibcon#about to read 6, iclass 10, count 2 2006.257.17:17:16.96#ibcon#read 6, iclass 10, count 2 2006.257.17:17:16.96#ibcon#end of sib2, iclass 10, count 2 2006.257.17:17:16.96#ibcon#*after write, iclass 10, count 2 2006.257.17:17:16.96#ibcon#*before return 0, iclass 10, count 2 2006.257.17:17:16.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:16.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:16.96#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.17:17:16.96#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:16.96#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:17.08#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:17.08#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:17.08#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:17:17.08#ibcon#first serial, iclass 10, count 0 2006.257.17:17:17.08#ibcon#enter sib2, iclass 10, count 0 2006.257.17:17:17.08#ibcon#flushed, iclass 10, count 0 2006.257.17:17:17.08#ibcon#about to write, iclass 10, count 0 2006.257.17:17:17.08#ibcon#wrote, iclass 10, count 0 2006.257.17:17:17.08#ibcon#about to read 3, iclass 10, count 0 2006.257.17:17:17.10#ibcon#read 3, iclass 10, count 0 2006.257.17:17:17.10#ibcon#about to read 4, iclass 10, count 0 2006.257.17:17:17.10#ibcon#read 4, iclass 10, count 0 2006.257.17:17:17.10#ibcon#about to read 5, iclass 10, count 0 2006.257.17:17:17.10#ibcon#read 5, iclass 10, count 0 2006.257.17:17:17.10#ibcon#about to read 6, iclass 10, count 0 2006.257.17:17:17.10#ibcon#read 6, iclass 10, count 0 2006.257.17:17:17.10#ibcon#end of sib2, iclass 10, count 0 2006.257.17:17:17.10#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:17:17.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:17:17.10#ibcon#[25=USB\r\n] 2006.257.17:17:17.10#ibcon#*before write, iclass 10, count 0 2006.257.17:17:17.10#ibcon#enter sib2, iclass 10, count 0 2006.257.17:17:17.10#ibcon#flushed, iclass 10, count 0 2006.257.17:17:17.10#ibcon#about to write, iclass 10, count 0 2006.257.17:17:17.10#ibcon#wrote, iclass 10, count 0 2006.257.17:17:17.10#ibcon#about to read 3, iclass 10, count 0 2006.257.17:17:17.13#ibcon#read 3, iclass 10, count 0 2006.257.17:17:17.13#ibcon#about to read 4, iclass 10, count 0 2006.257.17:17:17.13#ibcon#read 4, iclass 10, count 0 2006.257.17:17:17.13#ibcon#about to read 5, iclass 10, count 0 2006.257.17:17:17.13#ibcon#read 5, iclass 10, count 0 2006.257.17:17:17.13#ibcon#about to read 6, iclass 10, count 0 2006.257.17:17:17.13#ibcon#read 6, iclass 10, count 0 2006.257.17:17:17.13#ibcon#end of sib2, iclass 10, count 0 2006.257.17:17:17.13#ibcon#*after write, iclass 10, count 0 2006.257.17:17:17.13#ibcon#*before return 0, iclass 10, count 0 2006.257.17:17:17.13#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:17.13#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:17.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:17:17.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:17:17.13$vck44/valo=6,814.99 2006.257.17:17:17.13#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.17:17:17.13#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.17:17:17.13#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:17.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:17.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:17.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:17.13#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:17:17.13#ibcon#first serial, iclass 12, count 0 2006.257.17:17:17.13#ibcon#enter sib2, iclass 12, count 0 2006.257.17:17:17.13#ibcon#flushed, iclass 12, count 0 2006.257.17:17:17.13#ibcon#about to write, iclass 12, count 0 2006.257.17:17:17.13#ibcon#wrote, iclass 12, count 0 2006.257.17:17:17.13#ibcon#about to read 3, iclass 12, count 0 2006.257.17:17:17.15#ibcon#read 3, iclass 12, count 0 2006.257.17:17:17.15#ibcon#about to read 4, iclass 12, count 0 2006.257.17:17:17.15#ibcon#read 4, iclass 12, count 0 2006.257.17:17:17.15#ibcon#about to read 5, iclass 12, count 0 2006.257.17:17:17.15#ibcon#read 5, iclass 12, count 0 2006.257.17:17:17.15#ibcon#about to read 6, iclass 12, count 0 2006.257.17:17:17.15#ibcon#read 6, iclass 12, count 0 2006.257.17:17:17.15#ibcon#end of sib2, iclass 12, count 0 2006.257.17:17:17.15#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:17:17.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:17:17.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:17:17.15#ibcon#*before write, iclass 12, count 0 2006.257.17:17:17.15#ibcon#enter sib2, iclass 12, count 0 2006.257.17:17:17.15#ibcon#flushed, iclass 12, count 0 2006.257.17:17:17.15#ibcon#about to write, iclass 12, count 0 2006.257.17:17:17.15#ibcon#wrote, iclass 12, count 0 2006.257.17:17:17.15#ibcon#about to read 3, iclass 12, count 0 2006.257.17:17:17.19#ibcon#read 3, iclass 12, count 0 2006.257.17:17:17.19#ibcon#about to read 4, iclass 12, count 0 2006.257.17:17:17.19#ibcon#read 4, iclass 12, count 0 2006.257.17:17:17.19#ibcon#about to read 5, iclass 12, count 0 2006.257.17:17:17.19#ibcon#read 5, iclass 12, count 0 2006.257.17:17:17.19#ibcon#about to read 6, iclass 12, count 0 2006.257.17:17:17.19#ibcon#read 6, iclass 12, count 0 2006.257.17:17:17.19#ibcon#end of sib2, iclass 12, count 0 2006.257.17:17:17.19#ibcon#*after write, iclass 12, count 0 2006.257.17:17:17.19#ibcon#*before return 0, iclass 12, count 0 2006.257.17:17:17.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:17.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:17.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:17:17.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:17:17.19$vck44/va=6,4 2006.257.17:17:17.19#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.17:17:17.19#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.17:17:17.19#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:17.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:17.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:17.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:17.25#ibcon#enter wrdev, iclass 14, count 2 2006.257.17:17:17.25#ibcon#first serial, iclass 14, count 2 2006.257.17:17:17.25#ibcon#enter sib2, iclass 14, count 2 2006.257.17:17:17.25#ibcon#flushed, iclass 14, count 2 2006.257.17:17:17.25#ibcon#about to write, iclass 14, count 2 2006.257.17:17:17.25#ibcon#wrote, iclass 14, count 2 2006.257.17:17:17.25#ibcon#about to read 3, iclass 14, count 2 2006.257.17:17:17.27#ibcon#read 3, iclass 14, count 2 2006.257.17:17:17.27#ibcon#about to read 4, iclass 14, count 2 2006.257.17:17:17.27#ibcon#read 4, iclass 14, count 2 2006.257.17:17:17.27#ibcon#about to read 5, iclass 14, count 2 2006.257.17:17:17.27#ibcon#read 5, iclass 14, count 2 2006.257.17:17:17.27#ibcon#about to read 6, iclass 14, count 2 2006.257.17:17:17.27#ibcon#read 6, iclass 14, count 2 2006.257.17:17:17.27#ibcon#end of sib2, iclass 14, count 2 2006.257.17:17:17.27#ibcon#*mode == 0, iclass 14, count 2 2006.257.17:17:17.27#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.17:17:17.27#ibcon#[25=AT06-04\r\n] 2006.257.17:17:17.27#ibcon#*before write, iclass 14, count 2 2006.257.17:17:17.27#ibcon#enter sib2, iclass 14, count 2 2006.257.17:17:17.27#ibcon#flushed, iclass 14, count 2 2006.257.17:17:17.27#ibcon#about to write, iclass 14, count 2 2006.257.17:17:17.27#ibcon#wrote, iclass 14, count 2 2006.257.17:17:17.27#ibcon#about to read 3, iclass 14, count 2 2006.257.17:17:17.30#ibcon#read 3, iclass 14, count 2 2006.257.17:17:17.30#ibcon#about to read 4, iclass 14, count 2 2006.257.17:17:17.30#ibcon#read 4, iclass 14, count 2 2006.257.17:17:17.30#ibcon#about to read 5, iclass 14, count 2 2006.257.17:17:17.30#ibcon#read 5, iclass 14, count 2 2006.257.17:17:17.30#ibcon#about to read 6, iclass 14, count 2 2006.257.17:17:17.30#ibcon#read 6, iclass 14, count 2 2006.257.17:17:17.30#ibcon#end of sib2, iclass 14, count 2 2006.257.17:17:17.30#ibcon#*after write, iclass 14, count 2 2006.257.17:17:17.30#ibcon#*before return 0, iclass 14, count 2 2006.257.17:17:17.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:17.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:17.30#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.17:17:17.30#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:17.30#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:17.42#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:17.42#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:17.42#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:17:17.42#ibcon#first serial, iclass 14, count 0 2006.257.17:17:17.42#ibcon#enter sib2, iclass 14, count 0 2006.257.17:17:17.42#ibcon#flushed, iclass 14, count 0 2006.257.17:17:17.42#ibcon#about to write, iclass 14, count 0 2006.257.17:17:17.42#ibcon#wrote, iclass 14, count 0 2006.257.17:17:17.42#ibcon#about to read 3, iclass 14, count 0 2006.257.17:17:17.44#ibcon#read 3, iclass 14, count 0 2006.257.17:17:17.44#ibcon#about to read 4, iclass 14, count 0 2006.257.17:17:17.44#ibcon#read 4, iclass 14, count 0 2006.257.17:17:17.44#ibcon#about to read 5, iclass 14, count 0 2006.257.17:17:17.44#ibcon#read 5, iclass 14, count 0 2006.257.17:17:17.44#ibcon#about to read 6, iclass 14, count 0 2006.257.17:17:17.44#ibcon#read 6, iclass 14, count 0 2006.257.17:17:17.44#ibcon#end of sib2, iclass 14, count 0 2006.257.17:17:17.44#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:17:17.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:17:17.44#ibcon#[25=USB\r\n] 2006.257.17:17:17.44#ibcon#*before write, iclass 14, count 0 2006.257.17:17:17.44#ibcon#enter sib2, iclass 14, count 0 2006.257.17:17:17.44#ibcon#flushed, iclass 14, count 0 2006.257.17:17:17.44#ibcon#about to write, iclass 14, count 0 2006.257.17:17:17.44#ibcon#wrote, iclass 14, count 0 2006.257.17:17:17.44#ibcon#about to read 3, iclass 14, count 0 2006.257.17:17:17.47#ibcon#read 3, iclass 14, count 0 2006.257.17:17:17.47#ibcon#about to read 4, iclass 14, count 0 2006.257.17:17:17.47#ibcon#read 4, iclass 14, count 0 2006.257.17:17:17.47#ibcon#about to read 5, iclass 14, count 0 2006.257.17:17:17.47#ibcon#read 5, iclass 14, count 0 2006.257.17:17:17.47#ibcon#about to read 6, iclass 14, count 0 2006.257.17:17:17.47#ibcon#read 6, iclass 14, count 0 2006.257.17:17:17.47#ibcon#end of sib2, iclass 14, count 0 2006.257.17:17:17.47#ibcon#*after write, iclass 14, count 0 2006.257.17:17:17.47#ibcon#*before return 0, iclass 14, count 0 2006.257.17:17:17.47#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:17.47#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:17.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:17:17.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:17:17.47$vck44/valo=7,864.99 2006.257.17:17:17.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.17:17:17.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.17:17:17.47#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:17.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:17.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:17.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:17.47#ibcon#enter wrdev, iclass 16, count 0 2006.257.17:17:17.47#ibcon#first serial, iclass 16, count 0 2006.257.17:17:17.47#ibcon#enter sib2, iclass 16, count 0 2006.257.17:17:17.47#ibcon#flushed, iclass 16, count 0 2006.257.17:17:17.47#ibcon#about to write, iclass 16, count 0 2006.257.17:17:17.47#ibcon#wrote, iclass 16, count 0 2006.257.17:17:17.47#ibcon#about to read 3, iclass 16, count 0 2006.257.17:17:17.49#ibcon#read 3, iclass 16, count 0 2006.257.17:17:17.49#ibcon#about to read 4, iclass 16, count 0 2006.257.17:17:17.49#ibcon#read 4, iclass 16, count 0 2006.257.17:17:17.49#ibcon#about to read 5, iclass 16, count 0 2006.257.17:17:17.49#ibcon#read 5, iclass 16, count 0 2006.257.17:17:17.49#ibcon#about to read 6, iclass 16, count 0 2006.257.17:17:17.49#ibcon#read 6, iclass 16, count 0 2006.257.17:17:17.49#ibcon#end of sib2, iclass 16, count 0 2006.257.17:17:17.49#ibcon#*mode == 0, iclass 16, count 0 2006.257.17:17:17.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.17:17:17.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:17:17.49#ibcon#*before write, iclass 16, count 0 2006.257.17:17:17.49#ibcon#enter sib2, iclass 16, count 0 2006.257.17:17:17.49#ibcon#flushed, iclass 16, count 0 2006.257.17:17:17.49#ibcon#about to write, iclass 16, count 0 2006.257.17:17:17.49#ibcon#wrote, iclass 16, count 0 2006.257.17:17:17.49#ibcon#about to read 3, iclass 16, count 0 2006.257.17:17:17.53#ibcon#read 3, iclass 16, count 0 2006.257.17:17:17.53#ibcon#about to read 4, iclass 16, count 0 2006.257.17:17:17.53#ibcon#read 4, iclass 16, count 0 2006.257.17:17:17.53#ibcon#about to read 5, iclass 16, count 0 2006.257.17:17:17.53#ibcon#read 5, iclass 16, count 0 2006.257.17:17:17.53#ibcon#about to read 6, iclass 16, count 0 2006.257.17:17:17.53#ibcon#read 6, iclass 16, count 0 2006.257.17:17:17.53#ibcon#end of sib2, iclass 16, count 0 2006.257.17:17:17.53#ibcon#*after write, iclass 16, count 0 2006.257.17:17:17.53#ibcon#*before return 0, iclass 16, count 0 2006.257.17:17:17.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:17.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:17.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.17:17:17.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.17:17:17.53$vck44/va=7,4 2006.257.17:17:17.53#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.17:17:17.53#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.17:17:17.53#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:17.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:17.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:17.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:17.59#ibcon#enter wrdev, iclass 18, count 2 2006.257.17:17:17.59#ibcon#first serial, iclass 18, count 2 2006.257.17:17:17.59#ibcon#enter sib2, iclass 18, count 2 2006.257.17:17:17.59#ibcon#flushed, iclass 18, count 2 2006.257.17:17:17.59#ibcon#about to write, iclass 18, count 2 2006.257.17:17:17.59#ibcon#wrote, iclass 18, count 2 2006.257.17:17:17.59#ibcon#about to read 3, iclass 18, count 2 2006.257.17:17:17.61#ibcon#read 3, iclass 18, count 2 2006.257.17:17:17.61#ibcon#about to read 4, iclass 18, count 2 2006.257.17:17:17.61#ibcon#read 4, iclass 18, count 2 2006.257.17:17:17.61#ibcon#about to read 5, iclass 18, count 2 2006.257.17:17:17.61#ibcon#read 5, iclass 18, count 2 2006.257.17:17:17.61#ibcon#about to read 6, iclass 18, count 2 2006.257.17:17:17.61#ibcon#read 6, iclass 18, count 2 2006.257.17:17:17.61#ibcon#end of sib2, iclass 18, count 2 2006.257.17:17:17.61#ibcon#*mode == 0, iclass 18, count 2 2006.257.17:17:17.61#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.17:17:17.61#ibcon#[25=AT07-04\r\n] 2006.257.17:17:17.61#ibcon#*before write, iclass 18, count 2 2006.257.17:17:17.61#ibcon#enter sib2, iclass 18, count 2 2006.257.17:17:17.61#ibcon#flushed, iclass 18, count 2 2006.257.17:17:17.61#ibcon#about to write, iclass 18, count 2 2006.257.17:17:17.61#ibcon#wrote, iclass 18, count 2 2006.257.17:17:17.61#ibcon#about to read 3, iclass 18, count 2 2006.257.17:17:17.64#ibcon#read 3, iclass 18, count 2 2006.257.17:17:17.64#ibcon#about to read 4, iclass 18, count 2 2006.257.17:17:17.64#ibcon#read 4, iclass 18, count 2 2006.257.17:17:17.64#ibcon#about to read 5, iclass 18, count 2 2006.257.17:17:17.64#ibcon#read 5, iclass 18, count 2 2006.257.17:17:17.64#ibcon#about to read 6, iclass 18, count 2 2006.257.17:17:17.64#ibcon#read 6, iclass 18, count 2 2006.257.17:17:17.64#ibcon#end of sib2, iclass 18, count 2 2006.257.17:17:17.64#ibcon#*after write, iclass 18, count 2 2006.257.17:17:17.64#ibcon#*before return 0, iclass 18, count 2 2006.257.17:17:17.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:17.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:17.64#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.17:17:17.64#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:17.64#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:17.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:17.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:17.76#ibcon#enter wrdev, iclass 18, count 0 2006.257.17:17:17.76#ibcon#first serial, iclass 18, count 0 2006.257.17:17:17.76#ibcon#enter sib2, iclass 18, count 0 2006.257.17:17:17.76#ibcon#flushed, iclass 18, count 0 2006.257.17:17:17.76#ibcon#about to write, iclass 18, count 0 2006.257.17:17:17.76#ibcon#wrote, iclass 18, count 0 2006.257.17:17:17.76#ibcon#about to read 3, iclass 18, count 0 2006.257.17:17:17.78#ibcon#read 3, iclass 18, count 0 2006.257.17:17:17.78#ibcon#about to read 4, iclass 18, count 0 2006.257.17:17:17.78#ibcon#read 4, iclass 18, count 0 2006.257.17:17:17.78#ibcon#about to read 5, iclass 18, count 0 2006.257.17:17:17.78#ibcon#read 5, iclass 18, count 0 2006.257.17:17:17.78#ibcon#about to read 6, iclass 18, count 0 2006.257.17:17:17.78#ibcon#read 6, iclass 18, count 0 2006.257.17:17:17.78#ibcon#end of sib2, iclass 18, count 0 2006.257.17:17:17.78#ibcon#*mode == 0, iclass 18, count 0 2006.257.17:17:17.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.17:17:17.78#ibcon#[25=USB\r\n] 2006.257.17:17:17.78#ibcon#*before write, iclass 18, count 0 2006.257.17:17:17.78#ibcon#enter sib2, iclass 18, count 0 2006.257.17:17:17.78#ibcon#flushed, iclass 18, count 0 2006.257.17:17:17.78#ibcon#about to write, iclass 18, count 0 2006.257.17:17:17.78#ibcon#wrote, iclass 18, count 0 2006.257.17:17:17.78#ibcon#about to read 3, iclass 18, count 0 2006.257.17:17:17.81#ibcon#read 3, iclass 18, count 0 2006.257.17:17:17.81#ibcon#about to read 4, iclass 18, count 0 2006.257.17:17:17.81#ibcon#read 4, iclass 18, count 0 2006.257.17:17:17.81#ibcon#about to read 5, iclass 18, count 0 2006.257.17:17:17.81#ibcon#read 5, iclass 18, count 0 2006.257.17:17:17.81#ibcon#about to read 6, iclass 18, count 0 2006.257.17:17:17.81#ibcon#read 6, iclass 18, count 0 2006.257.17:17:17.81#ibcon#end of sib2, iclass 18, count 0 2006.257.17:17:17.81#ibcon#*after write, iclass 18, count 0 2006.257.17:17:17.81#ibcon#*before return 0, iclass 18, count 0 2006.257.17:17:17.81#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:17.81#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:17.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.17:17:17.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.17:17:17.81$vck44/valo=8,884.99 2006.257.17:17:17.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.17:17:17.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.17:17:17.81#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:17.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:17.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:17.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:17.81#ibcon#enter wrdev, iclass 20, count 0 2006.257.17:17:17.81#ibcon#first serial, iclass 20, count 0 2006.257.17:17:17.81#ibcon#enter sib2, iclass 20, count 0 2006.257.17:17:17.81#ibcon#flushed, iclass 20, count 0 2006.257.17:17:17.81#ibcon#about to write, iclass 20, count 0 2006.257.17:17:17.81#ibcon#wrote, iclass 20, count 0 2006.257.17:17:17.81#ibcon#about to read 3, iclass 20, count 0 2006.257.17:17:17.83#ibcon#read 3, iclass 20, count 0 2006.257.17:17:17.83#ibcon#about to read 4, iclass 20, count 0 2006.257.17:17:17.83#ibcon#read 4, iclass 20, count 0 2006.257.17:17:17.83#ibcon#about to read 5, iclass 20, count 0 2006.257.17:17:17.83#ibcon#read 5, iclass 20, count 0 2006.257.17:17:17.83#ibcon#about to read 6, iclass 20, count 0 2006.257.17:17:17.83#ibcon#read 6, iclass 20, count 0 2006.257.17:17:17.83#ibcon#end of sib2, iclass 20, count 0 2006.257.17:17:17.83#ibcon#*mode == 0, iclass 20, count 0 2006.257.17:17:17.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.17:17:17.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:17:17.83#ibcon#*before write, iclass 20, count 0 2006.257.17:17:17.83#ibcon#enter sib2, iclass 20, count 0 2006.257.17:17:17.83#ibcon#flushed, iclass 20, count 0 2006.257.17:17:17.83#ibcon#about to write, iclass 20, count 0 2006.257.17:17:17.83#ibcon#wrote, iclass 20, count 0 2006.257.17:17:17.83#ibcon#about to read 3, iclass 20, count 0 2006.257.17:17:17.87#ibcon#read 3, iclass 20, count 0 2006.257.17:17:17.87#ibcon#about to read 4, iclass 20, count 0 2006.257.17:17:17.87#ibcon#read 4, iclass 20, count 0 2006.257.17:17:17.87#ibcon#about to read 5, iclass 20, count 0 2006.257.17:17:17.87#ibcon#read 5, iclass 20, count 0 2006.257.17:17:17.87#ibcon#about to read 6, iclass 20, count 0 2006.257.17:17:17.87#ibcon#read 6, iclass 20, count 0 2006.257.17:17:17.87#ibcon#end of sib2, iclass 20, count 0 2006.257.17:17:17.87#ibcon#*after write, iclass 20, count 0 2006.257.17:17:17.87#ibcon#*before return 0, iclass 20, count 0 2006.257.17:17:17.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:17.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:17.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.17:17:17.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.17:17:17.87$vck44/va=8,4 2006.257.17:17:17.87#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.17:17:17.87#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.17:17:17.87#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:17.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:17.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:17.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:17.93#ibcon#enter wrdev, iclass 22, count 2 2006.257.17:17:17.93#ibcon#first serial, iclass 22, count 2 2006.257.17:17:17.93#ibcon#enter sib2, iclass 22, count 2 2006.257.17:17:17.93#ibcon#flushed, iclass 22, count 2 2006.257.17:17:17.93#ibcon#about to write, iclass 22, count 2 2006.257.17:17:17.93#ibcon#wrote, iclass 22, count 2 2006.257.17:17:17.93#ibcon#about to read 3, iclass 22, count 2 2006.257.17:17:17.95#ibcon#read 3, iclass 22, count 2 2006.257.17:17:17.95#ibcon#about to read 4, iclass 22, count 2 2006.257.17:17:17.95#ibcon#read 4, iclass 22, count 2 2006.257.17:17:17.95#ibcon#about to read 5, iclass 22, count 2 2006.257.17:17:17.95#ibcon#read 5, iclass 22, count 2 2006.257.17:17:17.95#ibcon#about to read 6, iclass 22, count 2 2006.257.17:17:17.95#ibcon#read 6, iclass 22, count 2 2006.257.17:17:17.95#ibcon#end of sib2, iclass 22, count 2 2006.257.17:17:17.95#ibcon#*mode == 0, iclass 22, count 2 2006.257.17:17:17.95#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.17:17:17.95#ibcon#[25=AT08-04\r\n] 2006.257.17:17:17.95#ibcon#*before write, iclass 22, count 2 2006.257.17:17:17.95#ibcon#enter sib2, iclass 22, count 2 2006.257.17:17:17.95#ibcon#flushed, iclass 22, count 2 2006.257.17:17:17.95#ibcon#about to write, iclass 22, count 2 2006.257.17:17:17.95#ibcon#wrote, iclass 22, count 2 2006.257.17:17:17.95#ibcon#about to read 3, iclass 22, count 2 2006.257.17:17:17.98#ibcon#read 3, iclass 22, count 2 2006.257.17:17:17.98#ibcon#about to read 4, iclass 22, count 2 2006.257.17:17:17.98#ibcon#read 4, iclass 22, count 2 2006.257.17:17:17.98#ibcon#about to read 5, iclass 22, count 2 2006.257.17:17:17.98#ibcon#read 5, iclass 22, count 2 2006.257.17:17:17.98#ibcon#about to read 6, iclass 22, count 2 2006.257.17:17:17.98#ibcon#read 6, iclass 22, count 2 2006.257.17:17:17.98#ibcon#end of sib2, iclass 22, count 2 2006.257.17:17:17.98#ibcon#*after write, iclass 22, count 2 2006.257.17:17:17.98#ibcon#*before return 0, iclass 22, count 2 2006.257.17:17:17.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:17.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:17.98#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.17:17:17.98#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:17.98#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:18.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:18.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:18.10#ibcon#enter wrdev, iclass 22, count 0 2006.257.17:17:18.10#ibcon#first serial, iclass 22, count 0 2006.257.17:17:18.10#ibcon#enter sib2, iclass 22, count 0 2006.257.17:17:18.10#ibcon#flushed, iclass 22, count 0 2006.257.17:17:18.10#ibcon#about to write, iclass 22, count 0 2006.257.17:17:18.10#ibcon#wrote, iclass 22, count 0 2006.257.17:17:18.10#ibcon#about to read 3, iclass 22, count 0 2006.257.17:17:18.12#ibcon#read 3, iclass 22, count 0 2006.257.17:17:18.12#ibcon#about to read 4, iclass 22, count 0 2006.257.17:17:18.12#ibcon#read 4, iclass 22, count 0 2006.257.17:17:18.12#ibcon#about to read 5, iclass 22, count 0 2006.257.17:17:18.12#ibcon#read 5, iclass 22, count 0 2006.257.17:17:18.12#ibcon#about to read 6, iclass 22, count 0 2006.257.17:17:18.12#ibcon#read 6, iclass 22, count 0 2006.257.17:17:18.12#ibcon#end of sib2, iclass 22, count 0 2006.257.17:17:18.12#ibcon#*mode == 0, iclass 22, count 0 2006.257.17:17:18.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.17:17:18.12#ibcon#[25=USB\r\n] 2006.257.17:17:18.12#ibcon#*before write, iclass 22, count 0 2006.257.17:17:18.12#ibcon#enter sib2, iclass 22, count 0 2006.257.17:17:18.12#ibcon#flushed, iclass 22, count 0 2006.257.17:17:18.12#ibcon#about to write, iclass 22, count 0 2006.257.17:17:18.12#ibcon#wrote, iclass 22, count 0 2006.257.17:17:18.12#ibcon#about to read 3, iclass 22, count 0 2006.257.17:17:18.15#ibcon#read 3, iclass 22, count 0 2006.257.17:17:18.15#ibcon#about to read 4, iclass 22, count 0 2006.257.17:17:18.15#ibcon#read 4, iclass 22, count 0 2006.257.17:17:18.15#ibcon#about to read 5, iclass 22, count 0 2006.257.17:17:18.15#ibcon#read 5, iclass 22, count 0 2006.257.17:17:18.15#ibcon#about to read 6, iclass 22, count 0 2006.257.17:17:18.15#ibcon#read 6, iclass 22, count 0 2006.257.17:17:18.15#ibcon#end of sib2, iclass 22, count 0 2006.257.17:17:18.15#ibcon#*after write, iclass 22, count 0 2006.257.17:17:18.15#ibcon#*before return 0, iclass 22, count 0 2006.257.17:17:18.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:18.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:18.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.17:17:18.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.17:17:18.15$vck44/vblo=1,629.99 2006.257.17:17:18.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.17:17:18.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.17:17:18.15#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:18.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:18.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:18.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:18.15#ibcon#enter wrdev, iclass 24, count 0 2006.257.17:17:18.15#ibcon#first serial, iclass 24, count 0 2006.257.17:17:18.15#ibcon#enter sib2, iclass 24, count 0 2006.257.17:17:18.15#ibcon#flushed, iclass 24, count 0 2006.257.17:17:18.15#ibcon#about to write, iclass 24, count 0 2006.257.17:17:18.15#ibcon#wrote, iclass 24, count 0 2006.257.17:17:18.15#ibcon#about to read 3, iclass 24, count 0 2006.257.17:17:18.17#ibcon#read 3, iclass 24, count 0 2006.257.17:17:18.17#ibcon#about to read 4, iclass 24, count 0 2006.257.17:17:18.17#ibcon#read 4, iclass 24, count 0 2006.257.17:17:18.17#ibcon#about to read 5, iclass 24, count 0 2006.257.17:17:18.17#ibcon#read 5, iclass 24, count 0 2006.257.17:17:18.17#ibcon#about to read 6, iclass 24, count 0 2006.257.17:17:18.17#ibcon#read 6, iclass 24, count 0 2006.257.17:17:18.17#ibcon#end of sib2, iclass 24, count 0 2006.257.17:17:18.17#ibcon#*mode == 0, iclass 24, count 0 2006.257.17:17:18.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.17:17:18.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:17:18.17#ibcon#*before write, iclass 24, count 0 2006.257.17:17:18.17#ibcon#enter sib2, iclass 24, count 0 2006.257.17:17:18.17#ibcon#flushed, iclass 24, count 0 2006.257.17:17:18.17#ibcon#about to write, iclass 24, count 0 2006.257.17:17:18.17#ibcon#wrote, iclass 24, count 0 2006.257.17:17:18.17#ibcon#about to read 3, iclass 24, count 0 2006.257.17:17:18.21#ibcon#read 3, iclass 24, count 0 2006.257.17:17:18.21#ibcon#about to read 4, iclass 24, count 0 2006.257.17:17:18.21#ibcon#read 4, iclass 24, count 0 2006.257.17:17:18.21#ibcon#about to read 5, iclass 24, count 0 2006.257.17:17:18.21#ibcon#read 5, iclass 24, count 0 2006.257.17:17:18.21#ibcon#about to read 6, iclass 24, count 0 2006.257.17:17:18.21#ibcon#read 6, iclass 24, count 0 2006.257.17:17:18.21#ibcon#end of sib2, iclass 24, count 0 2006.257.17:17:18.21#ibcon#*after write, iclass 24, count 0 2006.257.17:17:18.21#ibcon#*before return 0, iclass 24, count 0 2006.257.17:17:18.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:18.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:18.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.17:17:18.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.17:17:18.21$vck44/vb=1,4 2006.257.17:17:18.21#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.17:17:18.21#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.17:17:18.21#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:18.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:17:18.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:17:18.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:17:18.21#ibcon#enter wrdev, iclass 26, count 2 2006.257.17:17:18.21#ibcon#first serial, iclass 26, count 2 2006.257.17:17:18.21#ibcon#enter sib2, iclass 26, count 2 2006.257.17:17:18.21#ibcon#flushed, iclass 26, count 2 2006.257.17:17:18.21#ibcon#about to write, iclass 26, count 2 2006.257.17:17:18.21#ibcon#wrote, iclass 26, count 2 2006.257.17:17:18.21#ibcon#about to read 3, iclass 26, count 2 2006.257.17:17:18.23#ibcon#read 3, iclass 26, count 2 2006.257.17:17:18.23#ibcon#about to read 4, iclass 26, count 2 2006.257.17:17:18.23#ibcon#read 4, iclass 26, count 2 2006.257.17:17:18.23#ibcon#about to read 5, iclass 26, count 2 2006.257.17:17:18.23#ibcon#read 5, iclass 26, count 2 2006.257.17:17:18.23#ibcon#about to read 6, iclass 26, count 2 2006.257.17:17:18.23#ibcon#read 6, iclass 26, count 2 2006.257.17:17:18.23#ibcon#end of sib2, iclass 26, count 2 2006.257.17:17:18.23#ibcon#*mode == 0, iclass 26, count 2 2006.257.17:17:18.23#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.17:17:18.23#ibcon#[27=AT01-04\r\n] 2006.257.17:17:18.23#ibcon#*before write, iclass 26, count 2 2006.257.17:17:18.23#ibcon#enter sib2, iclass 26, count 2 2006.257.17:17:18.23#ibcon#flushed, iclass 26, count 2 2006.257.17:17:18.23#ibcon#about to write, iclass 26, count 2 2006.257.17:17:18.23#ibcon#wrote, iclass 26, count 2 2006.257.17:17:18.23#ibcon#about to read 3, iclass 26, count 2 2006.257.17:17:18.26#ibcon#read 3, iclass 26, count 2 2006.257.17:17:18.26#ibcon#about to read 4, iclass 26, count 2 2006.257.17:17:18.26#ibcon#read 4, iclass 26, count 2 2006.257.17:17:18.26#ibcon#about to read 5, iclass 26, count 2 2006.257.17:17:18.26#ibcon#read 5, iclass 26, count 2 2006.257.17:17:18.26#ibcon#about to read 6, iclass 26, count 2 2006.257.17:17:18.26#ibcon#read 6, iclass 26, count 2 2006.257.17:17:18.26#ibcon#end of sib2, iclass 26, count 2 2006.257.17:17:18.26#ibcon#*after write, iclass 26, count 2 2006.257.17:17:18.26#ibcon#*before return 0, iclass 26, count 2 2006.257.17:17:18.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:17:18.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:17:18.26#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.17:17:18.26#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:18.26#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:17:18.38#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:17:18.38#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:17:18.38#ibcon#enter wrdev, iclass 26, count 0 2006.257.17:17:18.38#ibcon#first serial, iclass 26, count 0 2006.257.17:17:18.38#ibcon#enter sib2, iclass 26, count 0 2006.257.17:17:18.38#ibcon#flushed, iclass 26, count 0 2006.257.17:17:18.38#ibcon#about to write, iclass 26, count 0 2006.257.17:17:18.38#ibcon#wrote, iclass 26, count 0 2006.257.17:17:18.38#ibcon#about to read 3, iclass 26, count 0 2006.257.17:17:18.40#ibcon#read 3, iclass 26, count 0 2006.257.17:17:18.40#ibcon#about to read 4, iclass 26, count 0 2006.257.17:17:18.40#ibcon#read 4, iclass 26, count 0 2006.257.17:17:18.40#ibcon#about to read 5, iclass 26, count 0 2006.257.17:17:18.40#ibcon#read 5, iclass 26, count 0 2006.257.17:17:18.40#ibcon#about to read 6, iclass 26, count 0 2006.257.17:17:18.40#ibcon#read 6, iclass 26, count 0 2006.257.17:17:18.40#ibcon#end of sib2, iclass 26, count 0 2006.257.17:17:18.40#ibcon#*mode == 0, iclass 26, count 0 2006.257.17:17:18.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.17:17:18.40#ibcon#[27=USB\r\n] 2006.257.17:17:18.40#ibcon#*before write, iclass 26, count 0 2006.257.17:17:18.40#ibcon#enter sib2, iclass 26, count 0 2006.257.17:17:18.40#ibcon#flushed, iclass 26, count 0 2006.257.17:17:18.40#ibcon#about to write, iclass 26, count 0 2006.257.17:17:18.40#ibcon#wrote, iclass 26, count 0 2006.257.17:17:18.40#ibcon#about to read 3, iclass 26, count 0 2006.257.17:17:18.43#ibcon#read 3, iclass 26, count 0 2006.257.17:17:18.43#ibcon#about to read 4, iclass 26, count 0 2006.257.17:17:18.43#ibcon#read 4, iclass 26, count 0 2006.257.17:17:18.43#ibcon#about to read 5, iclass 26, count 0 2006.257.17:17:18.43#ibcon#read 5, iclass 26, count 0 2006.257.17:17:18.43#ibcon#about to read 6, iclass 26, count 0 2006.257.17:17:18.43#ibcon#read 6, iclass 26, count 0 2006.257.17:17:18.43#ibcon#end of sib2, iclass 26, count 0 2006.257.17:17:18.43#ibcon#*after write, iclass 26, count 0 2006.257.17:17:18.43#ibcon#*before return 0, iclass 26, count 0 2006.257.17:17:18.43#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:17:18.43#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:17:18.43#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.17:17:18.43#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.17:17:18.43$vck44/vblo=2,634.99 2006.257.17:17:18.43#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.17:17:18.43#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.17:17:18.43#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:18.43#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:18.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:18.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:18.43#ibcon#enter wrdev, iclass 28, count 0 2006.257.17:17:18.43#ibcon#first serial, iclass 28, count 0 2006.257.17:17:18.43#ibcon#enter sib2, iclass 28, count 0 2006.257.17:17:18.43#ibcon#flushed, iclass 28, count 0 2006.257.17:17:18.43#ibcon#about to write, iclass 28, count 0 2006.257.17:17:18.43#ibcon#wrote, iclass 28, count 0 2006.257.17:17:18.43#ibcon#about to read 3, iclass 28, count 0 2006.257.17:17:18.45#ibcon#read 3, iclass 28, count 0 2006.257.17:17:18.45#ibcon#about to read 4, iclass 28, count 0 2006.257.17:17:18.45#ibcon#read 4, iclass 28, count 0 2006.257.17:17:18.45#ibcon#about to read 5, iclass 28, count 0 2006.257.17:17:18.45#ibcon#read 5, iclass 28, count 0 2006.257.17:17:18.45#ibcon#about to read 6, iclass 28, count 0 2006.257.17:17:18.45#ibcon#read 6, iclass 28, count 0 2006.257.17:17:18.45#ibcon#end of sib2, iclass 28, count 0 2006.257.17:17:18.45#ibcon#*mode == 0, iclass 28, count 0 2006.257.17:17:18.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.17:17:18.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:17:18.45#ibcon#*before write, iclass 28, count 0 2006.257.17:17:18.45#ibcon#enter sib2, iclass 28, count 0 2006.257.17:17:18.45#ibcon#flushed, iclass 28, count 0 2006.257.17:17:18.45#ibcon#about to write, iclass 28, count 0 2006.257.17:17:18.45#ibcon#wrote, iclass 28, count 0 2006.257.17:17:18.45#ibcon#about to read 3, iclass 28, count 0 2006.257.17:17:18.49#ibcon#read 3, iclass 28, count 0 2006.257.17:17:18.49#ibcon#about to read 4, iclass 28, count 0 2006.257.17:17:18.49#ibcon#read 4, iclass 28, count 0 2006.257.17:17:18.49#ibcon#about to read 5, iclass 28, count 0 2006.257.17:17:18.49#ibcon#read 5, iclass 28, count 0 2006.257.17:17:18.49#ibcon#about to read 6, iclass 28, count 0 2006.257.17:17:18.49#ibcon#read 6, iclass 28, count 0 2006.257.17:17:18.49#ibcon#end of sib2, iclass 28, count 0 2006.257.17:17:18.49#ibcon#*after write, iclass 28, count 0 2006.257.17:17:18.49#ibcon#*before return 0, iclass 28, count 0 2006.257.17:17:18.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:18.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:17:18.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.17:17:18.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.17:17:18.49$vck44/vb=2,5 2006.257.17:17:18.49#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.17:17:18.49#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.17:17:18.49#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:18.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:17:18.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:17:18.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:17:18.55#ibcon#enter wrdev, iclass 31, count 2 2006.257.17:17:18.55#ibcon#first serial, iclass 31, count 2 2006.257.17:17:18.55#ibcon#enter sib2, iclass 31, count 2 2006.257.17:17:18.55#ibcon#flushed, iclass 31, count 2 2006.257.17:17:18.55#ibcon#about to write, iclass 31, count 2 2006.257.17:17:18.55#ibcon#wrote, iclass 31, count 2 2006.257.17:17:18.55#ibcon#about to read 3, iclass 31, count 2 2006.257.17:17:18.57#ibcon#read 3, iclass 31, count 2 2006.257.17:17:18.57#ibcon#about to read 4, iclass 31, count 2 2006.257.17:17:18.57#ibcon#read 4, iclass 31, count 2 2006.257.17:17:18.57#ibcon#about to read 5, iclass 31, count 2 2006.257.17:17:18.57#ibcon#read 5, iclass 31, count 2 2006.257.17:17:18.57#ibcon#about to read 6, iclass 31, count 2 2006.257.17:17:18.57#ibcon#read 6, iclass 31, count 2 2006.257.17:17:18.57#ibcon#end of sib2, iclass 31, count 2 2006.257.17:17:18.57#ibcon#*mode == 0, iclass 31, count 2 2006.257.17:17:18.57#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.17:17:18.57#ibcon#[27=AT02-05\r\n] 2006.257.17:17:18.57#ibcon#*before write, iclass 31, count 2 2006.257.17:17:18.57#ibcon#enter sib2, iclass 31, count 2 2006.257.17:17:18.57#ibcon#flushed, iclass 31, count 2 2006.257.17:17:18.57#ibcon#about to write, iclass 31, count 2 2006.257.17:17:18.57#ibcon#wrote, iclass 31, count 2 2006.257.17:17:18.57#ibcon#about to read 3, iclass 31, count 2 2006.257.17:17:18.60#ibcon#read 3, iclass 31, count 2 2006.257.17:17:18.60#ibcon#about to read 4, iclass 31, count 2 2006.257.17:17:18.60#ibcon#read 4, iclass 31, count 2 2006.257.17:17:18.60#ibcon#about to read 5, iclass 31, count 2 2006.257.17:17:18.60#ibcon#read 5, iclass 31, count 2 2006.257.17:17:18.60#ibcon#about to read 6, iclass 31, count 2 2006.257.17:17:18.60#ibcon#read 6, iclass 31, count 2 2006.257.17:17:18.60#ibcon#end of sib2, iclass 31, count 2 2006.257.17:17:18.60#ibcon#*after write, iclass 31, count 2 2006.257.17:17:18.60#ibcon#*before return 0, iclass 31, count 2 2006.257.17:17:18.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:17:18.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:17:18.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.17:17:18.60#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:18.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:17:18.64#abcon#<5=/14 1.3 4.0 17.37 971014.3\r\n> 2006.257.17:17:18.66#abcon#{5=INTERFACE CLEAR} 2006.257.17:17:18.72#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:17:18.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:17:18.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:17:18.72#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:17:18.72#ibcon#first serial, iclass 31, count 0 2006.257.17:17:18.72#ibcon#enter sib2, iclass 31, count 0 2006.257.17:17:18.72#ibcon#flushed, iclass 31, count 0 2006.257.17:17:18.72#ibcon#about to write, iclass 31, count 0 2006.257.17:17:18.72#ibcon#wrote, iclass 31, count 0 2006.257.17:17:18.72#ibcon#about to read 3, iclass 31, count 0 2006.257.17:17:18.74#ibcon#read 3, iclass 31, count 0 2006.257.17:17:18.74#ibcon#about to read 4, iclass 31, count 0 2006.257.17:17:18.74#ibcon#read 4, iclass 31, count 0 2006.257.17:17:18.74#ibcon#about to read 5, iclass 31, count 0 2006.257.17:17:18.74#ibcon#read 5, iclass 31, count 0 2006.257.17:17:18.74#ibcon#about to read 6, iclass 31, count 0 2006.257.17:17:18.74#ibcon#read 6, iclass 31, count 0 2006.257.17:17:18.74#ibcon#end of sib2, iclass 31, count 0 2006.257.17:17:18.74#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:17:18.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:17:18.74#ibcon#[27=USB\r\n] 2006.257.17:17:18.74#ibcon#*before write, iclass 31, count 0 2006.257.17:17:18.74#ibcon#enter sib2, iclass 31, count 0 2006.257.17:17:18.74#ibcon#flushed, iclass 31, count 0 2006.257.17:17:18.74#ibcon#about to write, iclass 31, count 0 2006.257.17:17:18.74#ibcon#wrote, iclass 31, count 0 2006.257.17:17:18.74#ibcon#about to read 3, iclass 31, count 0 2006.257.17:17:18.77#ibcon#read 3, iclass 31, count 0 2006.257.17:17:18.77#ibcon#about to read 4, iclass 31, count 0 2006.257.17:17:18.77#ibcon#read 4, iclass 31, count 0 2006.257.17:17:18.77#ibcon#about to read 5, iclass 31, count 0 2006.257.17:17:18.77#ibcon#read 5, iclass 31, count 0 2006.257.17:17:18.77#ibcon#about to read 6, iclass 31, count 0 2006.257.17:17:18.77#ibcon#read 6, iclass 31, count 0 2006.257.17:17:18.77#ibcon#end of sib2, iclass 31, count 0 2006.257.17:17:18.77#ibcon#*after write, iclass 31, count 0 2006.257.17:17:18.77#ibcon#*before return 0, iclass 31, count 0 2006.257.17:17:18.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:17:18.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:17:18.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:17:18.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:17:18.77$vck44/vblo=3,649.99 2006.257.17:17:18.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.17:17:18.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.17:17:18.77#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:18.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:18.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:18.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:18.77#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:17:18.77#ibcon#first serial, iclass 36, count 0 2006.257.17:17:18.77#ibcon#enter sib2, iclass 36, count 0 2006.257.17:17:18.77#ibcon#flushed, iclass 36, count 0 2006.257.17:17:18.77#ibcon#about to write, iclass 36, count 0 2006.257.17:17:18.77#ibcon#wrote, iclass 36, count 0 2006.257.17:17:18.77#ibcon#about to read 3, iclass 36, count 0 2006.257.17:17:18.79#ibcon#read 3, iclass 36, count 0 2006.257.17:17:18.79#ibcon#about to read 4, iclass 36, count 0 2006.257.17:17:18.79#ibcon#read 4, iclass 36, count 0 2006.257.17:17:18.79#ibcon#about to read 5, iclass 36, count 0 2006.257.17:17:18.79#ibcon#read 5, iclass 36, count 0 2006.257.17:17:18.79#ibcon#about to read 6, iclass 36, count 0 2006.257.17:17:18.79#ibcon#read 6, iclass 36, count 0 2006.257.17:17:18.79#ibcon#end of sib2, iclass 36, count 0 2006.257.17:17:18.79#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:17:18.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:17:18.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:17:18.79#ibcon#*before write, iclass 36, count 0 2006.257.17:17:18.79#ibcon#enter sib2, iclass 36, count 0 2006.257.17:17:18.79#ibcon#flushed, iclass 36, count 0 2006.257.17:17:18.79#ibcon#about to write, iclass 36, count 0 2006.257.17:17:18.79#ibcon#wrote, iclass 36, count 0 2006.257.17:17:18.79#ibcon#about to read 3, iclass 36, count 0 2006.257.17:17:18.83#ibcon#read 3, iclass 36, count 0 2006.257.17:17:18.83#ibcon#about to read 4, iclass 36, count 0 2006.257.17:17:18.83#ibcon#read 4, iclass 36, count 0 2006.257.17:17:18.83#ibcon#about to read 5, iclass 36, count 0 2006.257.17:17:18.83#ibcon#read 5, iclass 36, count 0 2006.257.17:17:18.83#ibcon#about to read 6, iclass 36, count 0 2006.257.17:17:18.83#ibcon#read 6, iclass 36, count 0 2006.257.17:17:18.83#ibcon#end of sib2, iclass 36, count 0 2006.257.17:17:18.83#ibcon#*after write, iclass 36, count 0 2006.257.17:17:18.83#ibcon#*before return 0, iclass 36, count 0 2006.257.17:17:18.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:18.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:17:18.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:17:18.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:17:18.83$vck44/vb=3,4 2006.257.17:17:18.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.17:17:18.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.17:17:18.83#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:18.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:18.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:18.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:18.89#ibcon#enter wrdev, iclass 38, count 2 2006.257.17:17:18.89#ibcon#first serial, iclass 38, count 2 2006.257.17:17:18.89#ibcon#enter sib2, iclass 38, count 2 2006.257.17:17:18.89#ibcon#flushed, iclass 38, count 2 2006.257.17:17:18.89#ibcon#about to write, iclass 38, count 2 2006.257.17:17:18.89#ibcon#wrote, iclass 38, count 2 2006.257.17:17:18.89#ibcon#about to read 3, iclass 38, count 2 2006.257.17:17:18.91#ibcon#read 3, iclass 38, count 2 2006.257.17:17:18.91#ibcon#about to read 4, iclass 38, count 2 2006.257.17:17:18.91#ibcon#read 4, iclass 38, count 2 2006.257.17:17:18.91#ibcon#about to read 5, iclass 38, count 2 2006.257.17:17:18.91#ibcon#read 5, iclass 38, count 2 2006.257.17:17:18.91#ibcon#about to read 6, iclass 38, count 2 2006.257.17:17:18.91#ibcon#read 6, iclass 38, count 2 2006.257.17:17:18.91#ibcon#end of sib2, iclass 38, count 2 2006.257.17:17:18.91#ibcon#*mode == 0, iclass 38, count 2 2006.257.17:17:18.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.17:17:18.91#ibcon#[27=AT03-04\r\n] 2006.257.17:17:18.91#ibcon#*before write, iclass 38, count 2 2006.257.17:17:18.91#ibcon#enter sib2, iclass 38, count 2 2006.257.17:17:18.91#ibcon#flushed, iclass 38, count 2 2006.257.17:17:18.91#ibcon#about to write, iclass 38, count 2 2006.257.17:17:18.91#ibcon#wrote, iclass 38, count 2 2006.257.17:17:18.91#ibcon#about to read 3, iclass 38, count 2 2006.257.17:17:18.94#ibcon#read 3, iclass 38, count 2 2006.257.17:17:18.94#ibcon#about to read 4, iclass 38, count 2 2006.257.17:17:18.94#ibcon#read 4, iclass 38, count 2 2006.257.17:17:18.94#ibcon#about to read 5, iclass 38, count 2 2006.257.17:17:18.94#ibcon#read 5, iclass 38, count 2 2006.257.17:17:18.94#ibcon#about to read 6, iclass 38, count 2 2006.257.17:17:18.94#ibcon#read 6, iclass 38, count 2 2006.257.17:17:18.94#ibcon#end of sib2, iclass 38, count 2 2006.257.17:17:18.94#ibcon#*after write, iclass 38, count 2 2006.257.17:17:18.94#ibcon#*before return 0, iclass 38, count 2 2006.257.17:17:18.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:18.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:17:18.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.17:17:18.94#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:18.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:19.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:19.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:19.06#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:17:19.06#ibcon#first serial, iclass 38, count 0 2006.257.17:17:19.06#ibcon#enter sib2, iclass 38, count 0 2006.257.17:17:19.06#ibcon#flushed, iclass 38, count 0 2006.257.17:17:19.06#ibcon#about to write, iclass 38, count 0 2006.257.17:17:19.06#ibcon#wrote, iclass 38, count 0 2006.257.17:17:19.06#ibcon#about to read 3, iclass 38, count 0 2006.257.17:17:19.08#ibcon#read 3, iclass 38, count 0 2006.257.17:17:19.08#ibcon#about to read 4, iclass 38, count 0 2006.257.17:17:19.08#ibcon#read 4, iclass 38, count 0 2006.257.17:17:19.08#ibcon#about to read 5, iclass 38, count 0 2006.257.17:17:19.08#ibcon#read 5, iclass 38, count 0 2006.257.17:17:19.08#ibcon#about to read 6, iclass 38, count 0 2006.257.17:17:19.08#ibcon#read 6, iclass 38, count 0 2006.257.17:17:19.08#ibcon#end of sib2, iclass 38, count 0 2006.257.17:17:19.08#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:17:19.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:17:19.08#ibcon#[27=USB\r\n] 2006.257.17:17:19.08#ibcon#*before write, iclass 38, count 0 2006.257.17:17:19.08#ibcon#enter sib2, iclass 38, count 0 2006.257.17:17:19.08#ibcon#flushed, iclass 38, count 0 2006.257.17:17:19.08#ibcon#about to write, iclass 38, count 0 2006.257.17:17:19.08#ibcon#wrote, iclass 38, count 0 2006.257.17:17:19.08#ibcon#about to read 3, iclass 38, count 0 2006.257.17:17:19.11#ibcon#read 3, iclass 38, count 0 2006.257.17:17:19.11#ibcon#about to read 4, iclass 38, count 0 2006.257.17:17:19.11#ibcon#read 4, iclass 38, count 0 2006.257.17:17:19.11#ibcon#about to read 5, iclass 38, count 0 2006.257.17:17:19.11#ibcon#read 5, iclass 38, count 0 2006.257.17:17:19.11#ibcon#about to read 6, iclass 38, count 0 2006.257.17:17:19.11#ibcon#read 6, iclass 38, count 0 2006.257.17:17:19.11#ibcon#end of sib2, iclass 38, count 0 2006.257.17:17:19.11#ibcon#*after write, iclass 38, count 0 2006.257.17:17:19.11#ibcon#*before return 0, iclass 38, count 0 2006.257.17:17:19.11#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:19.11#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:17:19.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:17:19.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:17:19.11$vck44/vblo=4,679.99 2006.257.17:17:19.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.17:17:19.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.17:17:19.11#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:19.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:19.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:19.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:19.11#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:17:19.11#ibcon#first serial, iclass 40, count 0 2006.257.17:17:19.11#ibcon#enter sib2, iclass 40, count 0 2006.257.17:17:19.11#ibcon#flushed, iclass 40, count 0 2006.257.17:17:19.11#ibcon#about to write, iclass 40, count 0 2006.257.17:17:19.11#ibcon#wrote, iclass 40, count 0 2006.257.17:17:19.11#ibcon#about to read 3, iclass 40, count 0 2006.257.17:17:19.13#ibcon#read 3, iclass 40, count 0 2006.257.17:17:19.13#ibcon#about to read 4, iclass 40, count 0 2006.257.17:17:19.13#ibcon#read 4, iclass 40, count 0 2006.257.17:17:19.13#ibcon#about to read 5, iclass 40, count 0 2006.257.17:17:19.13#ibcon#read 5, iclass 40, count 0 2006.257.17:17:19.13#ibcon#about to read 6, iclass 40, count 0 2006.257.17:17:19.13#ibcon#read 6, iclass 40, count 0 2006.257.17:17:19.13#ibcon#end of sib2, iclass 40, count 0 2006.257.17:17:19.13#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:17:19.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:17:19.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:17:19.13#ibcon#*before write, iclass 40, count 0 2006.257.17:17:19.13#ibcon#enter sib2, iclass 40, count 0 2006.257.17:17:19.13#ibcon#flushed, iclass 40, count 0 2006.257.17:17:19.13#ibcon#about to write, iclass 40, count 0 2006.257.17:17:19.13#ibcon#wrote, iclass 40, count 0 2006.257.17:17:19.13#ibcon#about to read 3, iclass 40, count 0 2006.257.17:17:19.17#ibcon#read 3, iclass 40, count 0 2006.257.17:17:19.17#ibcon#about to read 4, iclass 40, count 0 2006.257.17:17:19.17#ibcon#read 4, iclass 40, count 0 2006.257.17:17:19.17#ibcon#about to read 5, iclass 40, count 0 2006.257.17:17:19.17#ibcon#read 5, iclass 40, count 0 2006.257.17:17:19.17#ibcon#about to read 6, iclass 40, count 0 2006.257.17:17:19.17#ibcon#read 6, iclass 40, count 0 2006.257.17:17:19.17#ibcon#end of sib2, iclass 40, count 0 2006.257.17:17:19.17#ibcon#*after write, iclass 40, count 0 2006.257.17:17:19.17#ibcon#*before return 0, iclass 40, count 0 2006.257.17:17:19.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:19.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:17:19.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:17:19.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:17:19.17$vck44/vb=4,5 2006.257.17:17:19.17#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.17:17:19.17#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.17:17:19.17#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:19.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:19.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:19.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:19.23#ibcon#enter wrdev, iclass 4, count 2 2006.257.17:17:19.23#ibcon#first serial, iclass 4, count 2 2006.257.17:17:19.23#ibcon#enter sib2, iclass 4, count 2 2006.257.17:17:19.23#ibcon#flushed, iclass 4, count 2 2006.257.17:17:19.23#ibcon#about to write, iclass 4, count 2 2006.257.17:17:19.23#ibcon#wrote, iclass 4, count 2 2006.257.17:17:19.23#ibcon#about to read 3, iclass 4, count 2 2006.257.17:17:19.25#ibcon#read 3, iclass 4, count 2 2006.257.17:17:19.25#ibcon#about to read 4, iclass 4, count 2 2006.257.17:17:19.25#ibcon#read 4, iclass 4, count 2 2006.257.17:17:19.25#ibcon#about to read 5, iclass 4, count 2 2006.257.17:17:19.25#ibcon#read 5, iclass 4, count 2 2006.257.17:17:19.25#ibcon#about to read 6, iclass 4, count 2 2006.257.17:17:19.25#ibcon#read 6, iclass 4, count 2 2006.257.17:17:19.25#ibcon#end of sib2, iclass 4, count 2 2006.257.17:17:19.25#ibcon#*mode == 0, iclass 4, count 2 2006.257.17:17:19.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.17:17:19.25#ibcon#[27=AT04-05\r\n] 2006.257.17:17:19.25#ibcon#*before write, iclass 4, count 2 2006.257.17:17:19.25#ibcon#enter sib2, iclass 4, count 2 2006.257.17:17:19.25#ibcon#flushed, iclass 4, count 2 2006.257.17:17:19.25#ibcon#about to write, iclass 4, count 2 2006.257.17:17:19.25#ibcon#wrote, iclass 4, count 2 2006.257.17:17:19.25#ibcon#about to read 3, iclass 4, count 2 2006.257.17:17:19.28#ibcon#read 3, iclass 4, count 2 2006.257.17:17:19.28#ibcon#about to read 4, iclass 4, count 2 2006.257.17:17:19.28#ibcon#read 4, iclass 4, count 2 2006.257.17:17:19.28#ibcon#about to read 5, iclass 4, count 2 2006.257.17:17:19.28#ibcon#read 5, iclass 4, count 2 2006.257.17:17:19.28#ibcon#about to read 6, iclass 4, count 2 2006.257.17:17:19.28#ibcon#read 6, iclass 4, count 2 2006.257.17:17:19.28#ibcon#end of sib2, iclass 4, count 2 2006.257.17:17:19.28#ibcon#*after write, iclass 4, count 2 2006.257.17:17:19.28#ibcon#*before return 0, iclass 4, count 2 2006.257.17:17:19.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:19.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:17:19.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.17:17:19.28#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:19.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:19.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:19.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:19.40#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:17:19.40#ibcon#first serial, iclass 4, count 0 2006.257.17:17:19.40#ibcon#enter sib2, iclass 4, count 0 2006.257.17:17:19.40#ibcon#flushed, iclass 4, count 0 2006.257.17:17:19.40#ibcon#about to write, iclass 4, count 0 2006.257.17:17:19.40#ibcon#wrote, iclass 4, count 0 2006.257.17:17:19.40#ibcon#about to read 3, iclass 4, count 0 2006.257.17:17:19.42#ibcon#read 3, iclass 4, count 0 2006.257.17:17:19.42#ibcon#about to read 4, iclass 4, count 0 2006.257.17:17:19.42#ibcon#read 4, iclass 4, count 0 2006.257.17:17:19.42#ibcon#about to read 5, iclass 4, count 0 2006.257.17:17:19.42#ibcon#read 5, iclass 4, count 0 2006.257.17:17:19.42#ibcon#about to read 6, iclass 4, count 0 2006.257.17:17:19.42#ibcon#read 6, iclass 4, count 0 2006.257.17:17:19.42#ibcon#end of sib2, iclass 4, count 0 2006.257.17:17:19.42#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:17:19.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:17:19.42#ibcon#[27=USB\r\n] 2006.257.17:17:19.42#ibcon#*before write, iclass 4, count 0 2006.257.17:17:19.42#ibcon#enter sib2, iclass 4, count 0 2006.257.17:17:19.42#ibcon#flushed, iclass 4, count 0 2006.257.17:17:19.42#ibcon#about to write, iclass 4, count 0 2006.257.17:17:19.42#ibcon#wrote, iclass 4, count 0 2006.257.17:17:19.42#ibcon#about to read 3, iclass 4, count 0 2006.257.17:17:19.45#ibcon#read 3, iclass 4, count 0 2006.257.17:17:19.45#ibcon#about to read 4, iclass 4, count 0 2006.257.17:17:19.45#ibcon#read 4, iclass 4, count 0 2006.257.17:17:19.45#ibcon#about to read 5, iclass 4, count 0 2006.257.17:17:19.45#ibcon#read 5, iclass 4, count 0 2006.257.17:17:19.45#ibcon#about to read 6, iclass 4, count 0 2006.257.17:17:19.45#ibcon#read 6, iclass 4, count 0 2006.257.17:17:19.45#ibcon#end of sib2, iclass 4, count 0 2006.257.17:17:19.45#ibcon#*after write, iclass 4, count 0 2006.257.17:17:19.45#ibcon#*before return 0, iclass 4, count 0 2006.257.17:17:19.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:19.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:17:19.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:17:19.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:17:19.45$vck44/vblo=5,709.99 2006.257.17:17:19.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.17:17:19.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.17:17:19.45#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:19.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:19.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:19.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:19.45#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:17:19.45#ibcon#first serial, iclass 6, count 0 2006.257.17:17:19.45#ibcon#enter sib2, iclass 6, count 0 2006.257.17:17:19.45#ibcon#flushed, iclass 6, count 0 2006.257.17:17:19.45#ibcon#about to write, iclass 6, count 0 2006.257.17:17:19.45#ibcon#wrote, iclass 6, count 0 2006.257.17:17:19.45#ibcon#about to read 3, iclass 6, count 0 2006.257.17:17:19.47#ibcon#read 3, iclass 6, count 0 2006.257.17:17:19.47#ibcon#about to read 4, iclass 6, count 0 2006.257.17:17:19.47#ibcon#read 4, iclass 6, count 0 2006.257.17:17:19.47#ibcon#about to read 5, iclass 6, count 0 2006.257.17:17:19.47#ibcon#read 5, iclass 6, count 0 2006.257.17:17:19.47#ibcon#about to read 6, iclass 6, count 0 2006.257.17:17:19.47#ibcon#read 6, iclass 6, count 0 2006.257.17:17:19.47#ibcon#end of sib2, iclass 6, count 0 2006.257.17:17:19.47#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:17:19.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:17:19.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:17:19.47#ibcon#*before write, iclass 6, count 0 2006.257.17:17:19.47#ibcon#enter sib2, iclass 6, count 0 2006.257.17:17:19.47#ibcon#flushed, iclass 6, count 0 2006.257.17:17:19.47#ibcon#about to write, iclass 6, count 0 2006.257.17:17:19.47#ibcon#wrote, iclass 6, count 0 2006.257.17:17:19.47#ibcon#about to read 3, iclass 6, count 0 2006.257.17:17:19.51#ibcon#read 3, iclass 6, count 0 2006.257.17:17:19.51#ibcon#about to read 4, iclass 6, count 0 2006.257.17:17:19.51#ibcon#read 4, iclass 6, count 0 2006.257.17:17:19.51#ibcon#about to read 5, iclass 6, count 0 2006.257.17:17:19.51#ibcon#read 5, iclass 6, count 0 2006.257.17:17:19.51#ibcon#about to read 6, iclass 6, count 0 2006.257.17:17:19.51#ibcon#read 6, iclass 6, count 0 2006.257.17:17:19.51#ibcon#end of sib2, iclass 6, count 0 2006.257.17:17:19.51#ibcon#*after write, iclass 6, count 0 2006.257.17:17:19.51#ibcon#*before return 0, iclass 6, count 0 2006.257.17:17:19.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:19.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:17:19.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:17:19.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:17:19.51$vck44/vb=5,4 2006.257.17:17:19.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.17:17:19.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.17:17:19.51#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:19.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:19.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:19.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:19.57#ibcon#enter wrdev, iclass 10, count 2 2006.257.17:17:19.57#ibcon#first serial, iclass 10, count 2 2006.257.17:17:19.57#ibcon#enter sib2, iclass 10, count 2 2006.257.17:17:19.57#ibcon#flushed, iclass 10, count 2 2006.257.17:17:19.57#ibcon#about to write, iclass 10, count 2 2006.257.17:17:19.57#ibcon#wrote, iclass 10, count 2 2006.257.17:17:19.57#ibcon#about to read 3, iclass 10, count 2 2006.257.17:17:19.59#ibcon#read 3, iclass 10, count 2 2006.257.17:17:19.59#ibcon#about to read 4, iclass 10, count 2 2006.257.17:17:19.59#ibcon#read 4, iclass 10, count 2 2006.257.17:17:19.59#ibcon#about to read 5, iclass 10, count 2 2006.257.17:17:19.59#ibcon#read 5, iclass 10, count 2 2006.257.17:17:19.59#ibcon#about to read 6, iclass 10, count 2 2006.257.17:17:19.59#ibcon#read 6, iclass 10, count 2 2006.257.17:17:19.59#ibcon#end of sib2, iclass 10, count 2 2006.257.17:17:19.59#ibcon#*mode == 0, iclass 10, count 2 2006.257.17:17:19.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.17:17:19.59#ibcon#[27=AT05-04\r\n] 2006.257.17:17:19.59#ibcon#*before write, iclass 10, count 2 2006.257.17:17:19.59#ibcon#enter sib2, iclass 10, count 2 2006.257.17:17:19.59#ibcon#flushed, iclass 10, count 2 2006.257.17:17:19.59#ibcon#about to write, iclass 10, count 2 2006.257.17:17:19.59#ibcon#wrote, iclass 10, count 2 2006.257.17:17:19.59#ibcon#about to read 3, iclass 10, count 2 2006.257.17:17:19.62#ibcon#read 3, iclass 10, count 2 2006.257.17:17:19.62#ibcon#about to read 4, iclass 10, count 2 2006.257.17:17:19.62#ibcon#read 4, iclass 10, count 2 2006.257.17:17:19.62#ibcon#about to read 5, iclass 10, count 2 2006.257.17:17:19.62#ibcon#read 5, iclass 10, count 2 2006.257.17:17:19.62#ibcon#about to read 6, iclass 10, count 2 2006.257.17:17:19.62#ibcon#read 6, iclass 10, count 2 2006.257.17:17:19.62#ibcon#end of sib2, iclass 10, count 2 2006.257.17:17:19.62#ibcon#*after write, iclass 10, count 2 2006.257.17:17:19.62#ibcon#*before return 0, iclass 10, count 2 2006.257.17:17:19.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:19.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:17:19.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.17:17:19.62#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:19.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:19.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:19.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:19.74#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:17:19.74#ibcon#first serial, iclass 10, count 0 2006.257.17:17:19.74#ibcon#enter sib2, iclass 10, count 0 2006.257.17:17:19.74#ibcon#flushed, iclass 10, count 0 2006.257.17:17:19.74#ibcon#about to write, iclass 10, count 0 2006.257.17:17:19.74#ibcon#wrote, iclass 10, count 0 2006.257.17:17:19.74#ibcon#about to read 3, iclass 10, count 0 2006.257.17:17:19.76#ibcon#read 3, iclass 10, count 0 2006.257.17:17:19.76#ibcon#about to read 4, iclass 10, count 0 2006.257.17:17:19.76#ibcon#read 4, iclass 10, count 0 2006.257.17:17:19.76#ibcon#about to read 5, iclass 10, count 0 2006.257.17:17:19.76#ibcon#read 5, iclass 10, count 0 2006.257.17:17:19.76#ibcon#about to read 6, iclass 10, count 0 2006.257.17:17:19.76#ibcon#read 6, iclass 10, count 0 2006.257.17:17:19.76#ibcon#end of sib2, iclass 10, count 0 2006.257.17:17:19.76#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:17:19.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:17:19.76#ibcon#[27=USB\r\n] 2006.257.17:17:19.76#ibcon#*before write, iclass 10, count 0 2006.257.17:17:19.76#ibcon#enter sib2, iclass 10, count 0 2006.257.17:17:19.76#ibcon#flushed, iclass 10, count 0 2006.257.17:17:19.76#ibcon#about to write, iclass 10, count 0 2006.257.17:17:19.76#ibcon#wrote, iclass 10, count 0 2006.257.17:17:19.76#ibcon#about to read 3, iclass 10, count 0 2006.257.17:17:19.79#ibcon#read 3, iclass 10, count 0 2006.257.17:17:19.79#ibcon#about to read 4, iclass 10, count 0 2006.257.17:17:19.79#ibcon#read 4, iclass 10, count 0 2006.257.17:17:19.79#ibcon#about to read 5, iclass 10, count 0 2006.257.17:17:19.79#ibcon#read 5, iclass 10, count 0 2006.257.17:17:19.79#ibcon#about to read 6, iclass 10, count 0 2006.257.17:17:19.79#ibcon#read 6, iclass 10, count 0 2006.257.17:17:19.79#ibcon#end of sib2, iclass 10, count 0 2006.257.17:17:19.79#ibcon#*after write, iclass 10, count 0 2006.257.17:17:19.79#ibcon#*before return 0, iclass 10, count 0 2006.257.17:17:19.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:19.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:17:19.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:17:19.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:17:19.79$vck44/vblo=6,719.99 2006.257.17:17:19.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.17:17:19.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.17:17:19.79#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:19.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:19.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:19.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:19.79#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:17:19.79#ibcon#first serial, iclass 12, count 0 2006.257.17:17:19.79#ibcon#enter sib2, iclass 12, count 0 2006.257.17:17:19.79#ibcon#flushed, iclass 12, count 0 2006.257.17:17:19.79#ibcon#about to write, iclass 12, count 0 2006.257.17:17:19.79#ibcon#wrote, iclass 12, count 0 2006.257.17:17:19.79#ibcon#about to read 3, iclass 12, count 0 2006.257.17:17:19.81#ibcon#read 3, iclass 12, count 0 2006.257.17:17:19.81#ibcon#about to read 4, iclass 12, count 0 2006.257.17:17:19.81#ibcon#read 4, iclass 12, count 0 2006.257.17:17:19.81#ibcon#about to read 5, iclass 12, count 0 2006.257.17:17:19.81#ibcon#read 5, iclass 12, count 0 2006.257.17:17:19.81#ibcon#about to read 6, iclass 12, count 0 2006.257.17:17:19.81#ibcon#read 6, iclass 12, count 0 2006.257.17:17:19.81#ibcon#end of sib2, iclass 12, count 0 2006.257.17:17:19.81#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:17:19.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:17:19.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:17:19.81#ibcon#*before write, iclass 12, count 0 2006.257.17:17:19.81#ibcon#enter sib2, iclass 12, count 0 2006.257.17:17:19.81#ibcon#flushed, iclass 12, count 0 2006.257.17:17:19.81#ibcon#about to write, iclass 12, count 0 2006.257.17:17:19.81#ibcon#wrote, iclass 12, count 0 2006.257.17:17:19.81#ibcon#about to read 3, iclass 12, count 0 2006.257.17:17:19.85#ibcon#read 3, iclass 12, count 0 2006.257.17:17:19.85#ibcon#about to read 4, iclass 12, count 0 2006.257.17:17:19.85#ibcon#read 4, iclass 12, count 0 2006.257.17:17:19.85#ibcon#about to read 5, iclass 12, count 0 2006.257.17:17:19.85#ibcon#read 5, iclass 12, count 0 2006.257.17:17:19.85#ibcon#about to read 6, iclass 12, count 0 2006.257.17:17:19.85#ibcon#read 6, iclass 12, count 0 2006.257.17:17:19.85#ibcon#end of sib2, iclass 12, count 0 2006.257.17:17:19.85#ibcon#*after write, iclass 12, count 0 2006.257.17:17:19.85#ibcon#*before return 0, iclass 12, count 0 2006.257.17:17:19.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:19.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:17:19.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:17:19.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:17:19.85$vck44/vb=6,4 2006.257.17:17:19.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.17:17:19.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.17:17:19.85#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:19.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:19.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:19.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:19.91#ibcon#enter wrdev, iclass 14, count 2 2006.257.17:17:19.91#ibcon#first serial, iclass 14, count 2 2006.257.17:17:19.91#ibcon#enter sib2, iclass 14, count 2 2006.257.17:17:19.91#ibcon#flushed, iclass 14, count 2 2006.257.17:17:19.91#ibcon#about to write, iclass 14, count 2 2006.257.17:17:19.91#ibcon#wrote, iclass 14, count 2 2006.257.17:17:19.91#ibcon#about to read 3, iclass 14, count 2 2006.257.17:17:19.93#ibcon#read 3, iclass 14, count 2 2006.257.17:17:19.93#ibcon#about to read 4, iclass 14, count 2 2006.257.17:17:19.93#ibcon#read 4, iclass 14, count 2 2006.257.17:17:19.93#ibcon#about to read 5, iclass 14, count 2 2006.257.17:17:19.93#ibcon#read 5, iclass 14, count 2 2006.257.17:17:19.93#ibcon#about to read 6, iclass 14, count 2 2006.257.17:17:19.93#ibcon#read 6, iclass 14, count 2 2006.257.17:17:19.93#ibcon#end of sib2, iclass 14, count 2 2006.257.17:17:19.93#ibcon#*mode == 0, iclass 14, count 2 2006.257.17:17:19.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.17:17:19.93#ibcon#[27=AT06-04\r\n] 2006.257.17:17:19.93#ibcon#*before write, iclass 14, count 2 2006.257.17:17:19.93#ibcon#enter sib2, iclass 14, count 2 2006.257.17:17:19.93#ibcon#flushed, iclass 14, count 2 2006.257.17:17:19.93#ibcon#about to write, iclass 14, count 2 2006.257.17:17:19.93#ibcon#wrote, iclass 14, count 2 2006.257.17:17:19.93#ibcon#about to read 3, iclass 14, count 2 2006.257.17:17:19.96#ibcon#read 3, iclass 14, count 2 2006.257.17:17:19.96#ibcon#about to read 4, iclass 14, count 2 2006.257.17:17:19.96#ibcon#read 4, iclass 14, count 2 2006.257.17:17:19.96#ibcon#about to read 5, iclass 14, count 2 2006.257.17:17:19.96#ibcon#read 5, iclass 14, count 2 2006.257.17:17:19.96#ibcon#about to read 6, iclass 14, count 2 2006.257.17:17:19.96#ibcon#read 6, iclass 14, count 2 2006.257.17:17:19.96#ibcon#end of sib2, iclass 14, count 2 2006.257.17:17:19.96#ibcon#*after write, iclass 14, count 2 2006.257.17:17:19.96#ibcon#*before return 0, iclass 14, count 2 2006.257.17:17:19.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:19.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:17:19.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.17:17:19.96#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:19.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:20.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:20.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:20.08#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:17:20.08#ibcon#first serial, iclass 14, count 0 2006.257.17:17:20.08#ibcon#enter sib2, iclass 14, count 0 2006.257.17:17:20.08#ibcon#flushed, iclass 14, count 0 2006.257.17:17:20.08#ibcon#about to write, iclass 14, count 0 2006.257.17:17:20.08#ibcon#wrote, iclass 14, count 0 2006.257.17:17:20.08#ibcon#about to read 3, iclass 14, count 0 2006.257.17:17:20.10#ibcon#read 3, iclass 14, count 0 2006.257.17:17:20.10#ibcon#about to read 4, iclass 14, count 0 2006.257.17:17:20.10#ibcon#read 4, iclass 14, count 0 2006.257.17:17:20.10#ibcon#about to read 5, iclass 14, count 0 2006.257.17:17:20.10#ibcon#read 5, iclass 14, count 0 2006.257.17:17:20.10#ibcon#about to read 6, iclass 14, count 0 2006.257.17:17:20.10#ibcon#read 6, iclass 14, count 0 2006.257.17:17:20.10#ibcon#end of sib2, iclass 14, count 0 2006.257.17:17:20.10#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:17:20.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:17:20.10#ibcon#[27=USB\r\n] 2006.257.17:17:20.10#ibcon#*before write, iclass 14, count 0 2006.257.17:17:20.10#ibcon#enter sib2, iclass 14, count 0 2006.257.17:17:20.10#ibcon#flushed, iclass 14, count 0 2006.257.17:17:20.10#ibcon#about to write, iclass 14, count 0 2006.257.17:17:20.10#ibcon#wrote, iclass 14, count 0 2006.257.17:17:20.10#ibcon#about to read 3, iclass 14, count 0 2006.257.17:17:20.13#ibcon#read 3, iclass 14, count 0 2006.257.17:17:20.13#ibcon#about to read 4, iclass 14, count 0 2006.257.17:17:20.13#ibcon#read 4, iclass 14, count 0 2006.257.17:17:20.13#ibcon#about to read 5, iclass 14, count 0 2006.257.17:17:20.13#ibcon#read 5, iclass 14, count 0 2006.257.17:17:20.13#ibcon#about to read 6, iclass 14, count 0 2006.257.17:17:20.13#ibcon#read 6, iclass 14, count 0 2006.257.17:17:20.13#ibcon#end of sib2, iclass 14, count 0 2006.257.17:17:20.13#ibcon#*after write, iclass 14, count 0 2006.257.17:17:20.13#ibcon#*before return 0, iclass 14, count 0 2006.257.17:17:20.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:20.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:17:20.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:17:20.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:17:20.13$vck44/vblo=7,734.99 2006.257.17:17:20.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.17:17:20.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.17:17:20.13#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:20.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:20.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:20.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:20.13#ibcon#enter wrdev, iclass 16, count 0 2006.257.17:17:20.13#ibcon#first serial, iclass 16, count 0 2006.257.17:17:20.13#ibcon#enter sib2, iclass 16, count 0 2006.257.17:17:20.13#ibcon#flushed, iclass 16, count 0 2006.257.17:17:20.13#ibcon#about to write, iclass 16, count 0 2006.257.17:17:20.13#ibcon#wrote, iclass 16, count 0 2006.257.17:17:20.13#ibcon#about to read 3, iclass 16, count 0 2006.257.17:17:20.15#ibcon#read 3, iclass 16, count 0 2006.257.17:17:20.15#ibcon#about to read 4, iclass 16, count 0 2006.257.17:17:20.15#ibcon#read 4, iclass 16, count 0 2006.257.17:17:20.15#ibcon#about to read 5, iclass 16, count 0 2006.257.17:17:20.15#ibcon#read 5, iclass 16, count 0 2006.257.17:17:20.15#ibcon#about to read 6, iclass 16, count 0 2006.257.17:17:20.15#ibcon#read 6, iclass 16, count 0 2006.257.17:17:20.15#ibcon#end of sib2, iclass 16, count 0 2006.257.17:17:20.15#ibcon#*mode == 0, iclass 16, count 0 2006.257.17:17:20.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.17:17:20.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:17:20.15#ibcon#*before write, iclass 16, count 0 2006.257.17:17:20.15#ibcon#enter sib2, iclass 16, count 0 2006.257.17:17:20.15#ibcon#flushed, iclass 16, count 0 2006.257.17:17:20.15#ibcon#about to write, iclass 16, count 0 2006.257.17:17:20.15#ibcon#wrote, iclass 16, count 0 2006.257.17:17:20.15#ibcon#about to read 3, iclass 16, count 0 2006.257.17:17:20.19#ibcon#read 3, iclass 16, count 0 2006.257.17:17:20.19#ibcon#about to read 4, iclass 16, count 0 2006.257.17:17:20.19#ibcon#read 4, iclass 16, count 0 2006.257.17:17:20.19#ibcon#about to read 5, iclass 16, count 0 2006.257.17:17:20.19#ibcon#read 5, iclass 16, count 0 2006.257.17:17:20.19#ibcon#about to read 6, iclass 16, count 0 2006.257.17:17:20.19#ibcon#read 6, iclass 16, count 0 2006.257.17:17:20.19#ibcon#end of sib2, iclass 16, count 0 2006.257.17:17:20.19#ibcon#*after write, iclass 16, count 0 2006.257.17:17:20.19#ibcon#*before return 0, iclass 16, count 0 2006.257.17:17:20.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:20.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:17:20.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.17:17:20.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.17:17:20.19$vck44/vb=7,4 2006.257.17:17:20.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.17:17:20.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.17:17:20.19#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:20.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:20.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:20.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:20.25#ibcon#enter wrdev, iclass 18, count 2 2006.257.17:17:20.25#ibcon#first serial, iclass 18, count 2 2006.257.17:17:20.25#ibcon#enter sib2, iclass 18, count 2 2006.257.17:17:20.25#ibcon#flushed, iclass 18, count 2 2006.257.17:17:20.25#ibcon#about to write, iclass 18, count 2 2006.257.17:17:20.25#ibcon#wrote, iclass 18, count 2 2006.257.17:17:20.25#ibcon#about to read 3, iclass 18, count 2 2006.257.17:17:20.27#ibcon#read 3, iclass 18, count 2 2006.257.17:17:20.27#ibcon#about to read 4, iclass 18, count 2 2006.257.17:17:20.27#ibcon#read 4, iclass 18, count 2 2006.257.17:17:20.27#ibcon#about to read 5, iclass 18, count 2 2006.257.17:17:20.27#ibcon#read 5, iclass 18, count 2 2006.257.17:17:20.27#ibcon#about to read 6, iclass 18, count 2 2006.257.17:17:20.27#ibcon#read 6, iclass 18, count 2 2006.257.17:17:20.27#ibcon#end of sib2, iclass 18, count 2 2006.257.17:17:20.27#ibcon#*mode == 0, iclass 18, count 2 2006.257.17:17:20.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.17:17:20.27#ibcon#[27=AT07-04\r\n] 2006.257.17:17:20.27#ibcon#*before write, iclass 18, count 2 2006.257.17:17:20.27#ibcon#enter sib2, iclass 18, count 2 2006.257.17:17:20.27#ibcon#flushed, iclass 18, count 2 2006.257.17:17:20.27#ibcon#about to write, iclass 18, count 2 2006.257.17:17:20.27#ibcon#wrote, iclass 18, count 2 2006.257.17:17:20.27#ibcon#about to read 3, iclass 18, count 2 2006.257.17:17:20.30#ibcon#read 3, iclass 18, count 2 2006.257.17:17:20.30#ibcon#about to read 4, iclass 18, count 2 2006.257.17:17:20.30#ibcon#read 4, iclass 18, count 2 2006.257.17:17:20.30#ibcon#about to read 5, iclass 18, count 2 2006.257.17:17:20.30#ibcon#read 5, iclass 18, count 2 2006.257.17:17:20.30#ibcon#about to read 6, iclass 18, count 2 2006.257.17:17:20.30#ibcon#read 6, iclass 18, count 2 2006.257.17:17:20.30#ibcon#end of sib2, iclass 18, count 2 2006.257.17:17:20.30#ibcon#*after write, iclass 18, count 2 2006.257.17:17:20.30#ibcon#*before return 0, iclass 18, count 2 2006.257.17:17:20.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:20.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:17:20.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.17:17:20.30#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:20.30#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:20.42#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:20.42#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:20.42#ibcon#enter wrdev, iclass 18, count 0 2006.257.17:17:20.42#ibcon#first serial, iclass 18, count 0 2006.257.17:17:20.42#ibcon#enter sib2, iclass 18, count 0 2006.257.17:17:20.42#ibcon#flushed, iclass 18, count 0 2006.257.17:17:20.42#ibcon#about to write, iclass 18, count 0 2006.257.17:17:20.42#ibcon#wrote, iclass 18, count 0 2006.257.17:17:20.42#ibcon#about to read 3, iclass 18, count 0 2006.257.17:17:20.44#ibcon#read 3, iclass 18, count 0 2006.257.17:17:20.44#ibcon#about to read 4, iclass 18, count 0 2006.257.17:17:20.44#ibcon#read 4, iclass 18, count 0 2006.257.17:17:20.44#ibcon#about to read 5, iclass 18, count 0 2006.257.17:17:20.44#ibcon#read 5, iclass 18, count 0 2006.257.17:17:20.44#ibcon#about to read 6, iclass 18, count 0 2006.257.17:17:20.44#ibcon#read 6, iclass 18, count 0 2006.257.17:17:20.44#ibcon#end of sib2, iclass 18, count 0 2006.257.17:17:20.44#ibcon#*mode == 0, iclass 18, count 0 2006.257.17:17:20.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.17:17:20.44#ibcon#[27=USB\r\n] 2006.257.17:17:20.44#ibcon#*before write, iclass 18, count 0 2006.257.17:17:20.44#ibcon#enter sib2, iclass 18, count 0 2006.257.17:17:20.44#ibcon#flushed, iclass 18, count 0 2006.257.17:17:20.44#ibcon#about to write, iclass 18, count 0 2006.257.17:17:20.44#ibcon#wrote, iclass 18, count 0 2006.257.17:17:20.44#ibcon#about to read 3, iclass 18, count 0 2006.257.17:17:20.47#ibcon#read 3, iclass 18, count 0 2006.257.17:17:20.47#ibcon#about to read 4, iclass 18, count 0 2006.257.17:17:20.47#ibcon#read 4, iclass 18, count 0 2006.257.17:17:20.47#ibcon#about to read 5, iclass 18, count 0 2006.257.17:17:20.47#ibcon#read 5, iclass 18, count 0 2006.257.17:17:20.47#ibcon#about to read 6, iclass 18, count 0 2006.257.17:17:20.47#ibcon#read 6, iclass 18, count 0 2006.257.17:17:20.47#ibcon#end of sib2, iclass 18, count 0 2006.257.17:17:20.47#ibcon#*after write, iclass 18, count 0 2006.257.17:17:20.47#ibcon#*before return 0, iclass 18, count 0 2006.257.17:17:20.47#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:20.47#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:17:20.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.17:17:20.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.17:17:20.47$vck44/vblo=8,744.99 2006.257.17:17:20.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.17:17:20.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.17:17:20.47#ibcon#ireg 17 cls_cnt 0 2006.257.17:17:20.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:20.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:20.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:20.47#ibcon#enter wrdev, iclass 20, count 0 2006.257.17:17:20.47#ibcon#first serial, iclass 20, count 0 2006.257.17:17:20.47#ibcon#enter sib2, iclass 20, count 0 2006.257.17:17:20.47#ibcon#flushed, iclass 20, count 0 2006.257.17:17:20.47#ibcon#about to write, iclass 20, count 0 2006.257.17:17:20.47#ibcon#wrote, iclass 20, count 0 2006.257.17:17:20.47#ibcon#about to read 3, iclass 20, count 0 2006.257.17:17:20.49#ibcon#read 3, iclass 20, count 0 2006.257.17:17:20.49#ibcon#about to read 4, iclass 20, count 0 2006.257.17:17:20.49#ibcon#read 4, iclass 20, count 0 2006.257.17:17:20.49#ibcon#about to read 5, iclass 20, count 0 2006.257.17:17:20.49#ibcon#read 5, iclass 20, count 0 2006.257.17:17:20.49#ibcon#about to read 6, iclass 20, count 0 2006.257.17:17:20.49#ibcon#read 6, iclass 20, count 0 2006.257.17:17:20.49#ibcon#end of sib2, iclass 20, count 0 2006.257.17:17:20.49#ibcon#*mode == 0, iclass 20, count 0 2006.257.17:17:20.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.17:17:20.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:17:20.49#ibcon#*before write, iclass 20, count 0 2006.257.17:17:20.49#ibcon#enter sib2, iclass 20, count 0 2006.257.17:17:20.49#ibcon#flushed, iclass 20, count 0 2006.257.17:17:20.49#ibcon#about to write, iclass 20, count 0 2006.257.17:17:20.49#ibcon#wrote, iclass 20, count 0 2006.257.17:17:20.49#ibcon#about to read 3, iclass 20, count 0 2006.257.17:17:20.53#ibcon#read 3, iclass 20, count 0 2006.257.17:17:20.53#ibcon#about to read 4, iclass 20, count 0 2006.257.17:17:20.53#ibcon#read 4, iclass 20, count 0 2006.257.17:17:20.53#ibcon#about to read 5, iclass 20, count 0 2006.257.17:17:20.53#ibcon#read 5, iclass 20, count 0 2006.257.17:17:20.53#ibcon#about to read 6, iclass 20, count 0 2006.257.17:17:20.53#ibcon#read 6, iclass 20, count 0 2006.257.17:17:20.53#ibcon#end of sib2, iclass 20, count 0 2006.257.17:17:20.53#ibcon#*after write, iclass 20, count 0 2006.257.17:17:20.53#ibcon#*before return 0, iclass 20, count 0 2006.257.17:17:20.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:20.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:17:20.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.17:17:20.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.17:17:20.53$vck44/vb=8,4 2006.257.17:17:20.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.17:17:20.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.17:17:20.53#ibcon#ireg 11 cls_cnt 2 2006.257.17:17:20.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:20.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:20.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:20.59#ibcon#enter wrdev, iclass 22, count 2 2006.257.17:17:20.59#ibcon#first serial, iclass 22, count 2 2006.257.17:17:20.59#ibcon#enter sib2, iclass 22, count 2 2006.257.17:17:20.59#ibcon#flushed, iclass 22, count 2 2006.257.17:17:20.59#ibcon#about to write, iclass 22, count 2 2006.257.17:17:20.59#ibcon#wrote, iclass 22, count 2 2006.257.17:17:20.59#ibcon#about to read 3, iclass 22, count 2 2006.257.17:17:20.61#ibcon#read 3, iclass 22, count 2 2006.257.17:17:20.61#ibcon#about to read 4, iclass 22, count 2 2006.257.17:17:20.61#ibcon#read 4, iclass 22, count 2 2006.257.17:17:20.61#ibcon#about to read 5, iclass 22, count 2 2006.257.17:17:20.61#ibcon#read 5, iclass 22, count 2 2006.257.17:17:20.61#ibcon#about to read 6, iclass 22, count 2 2006.257.17:17:20.61#ibcon#read 6, iclass 22, count 2 2006.257.17:17:20.61#ibcon#end of sib2, iclass 22, count 2 2006.257.17:17:20.61#ibcon#*mode == 0, iclass 22, count 2 2006.257.17:17:20.61#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.17:17:20.61#ibcon#[27=AT08-04\r\n] 2006.257.17:17:20.61#ibcon#*before write, iclass 22, count 2 2006.257.17:17:20.61#ibcon#enter sib2, iclass 22, count 2 2006.257.17:17:20.61#ibcon#flushed, iclass 22, count 2 2006.257.17:17:20.61#ibcon#about to write, iclass 22, count 2 2006.257.17:17:20.61#ibcon#wrote, iclass 22, count 2 2006.257.17:17:20.61#ibcon#about to read 3, iclass 22, count 2 2006.257.17:17:20.64#ibcon#read 3, iclass 22, count 2 2006.257.17:17:20.64#ibcon#about to read 4, iclass 22, count 2 2006.257.17:17:20.64#ibcon#read 4, iclass 22, count 2 2006.257.17:17:20.64#ibcon#about to read 5, iclass 22, count 2 2006.257.17:17:20.64#ibcon#read 5, iclass 22, count 2 2006.257.17:17:20.64#ibcon#about to read 6, iclass 22, count 2 2006.257.17:17:20.64#ibcon#read 6, iclass 22, count 2 2006.257.17:17:20.64#ibcon#end of sib2, iclass 22, count 2 2006.257.17:17:20.64#ibcon#*after write, iclass 22, count 2 2006.257.17:17:20.64#ibcon#*before return 0, iclass 22, count 2 2006.257.17:17:20.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:20.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:17:20.64#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.17:17:20.64#ibcon#ireg 7 cls_cnt 0 2006.257.17:17:20.64#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:20.76#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:20.76#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:20.76#ibcon#enter wrdev, iclass 22, count 0 2006.257.17:17:20.76#ibcon#first serial, iclass 22, count 0 2006.257.17:17:20.76#ibcon#enter sib2, iclass 22, count 0 2006.257.17:17:20.76#ibcon#flushed, iclass 22, count 0 2006.257.17:17:20.76#ibcon#about to write, iclass 22, count 0 2006.257.17:17:20.76#ibcon#wrote, iclass 22, count 0 2006.257.17:17:20.76#ibcon#about to read 3, iclass 22, count 0 2006.257.17:17:20.78#ibcon#read 3, iclass 22, count 0 2006.257.17:17:20.78#ibcon#about to read 4, iclass 22, count 0 2006.257.17:17:20.78#ibcon#read 4, iclass 22, count 0 2006.257.17:17:20.78#ibcon#about to read 5, iclass 22, count 0 2006.257.17:17:20.78#ibcon#read 5, iclass 22, count 0 2006.257.17:17:20.78#ibcon#about to read 6, iclass 22, count 0 2006.257.17:17:20.78#ibcon#read 6, iclass 22, count 0 2006.257.17:17:20.78#ibcon#end of sib2, iclass 22, count 0 2006.257.17:17:20.78#ibcon#*mode == 0, iclass 22, count 0 2006.257.17:17:20.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.17:17:20.78#ibcon#[27=USB\r\n] 2006.257.17:17:20.78#ibcon#*before write, iclass 22, count 0 2006.257.17:17:20.78#ibcon#enter sib2, iclass 22, count 0 2006.257.17:17:20.78#ibcon#flushed, iclass 22, count 0 2006.257.17:17:20.78#ibcon#about to write, iclass 22, count 0 2006.257.17:17:20.78#ibcon#wrote, iclass 22, count 0 2006.257.17:17:20.78#ibcon#about to read 3, iclass 22, count 0 2006.257.17:17:20.81#ibcon#read 3, iclass 22, count 0 2006.257.17:17:20.81#ibcon#about to read 4, iclass 22, count 0 2006.257.17:17:20.81#ibcon#read 4, iclass 22, count 0 2006.257.17:17:20.81#ibcon#about to read 5, iclass 22, count 0 2006.257.17:17:20.81#ibcon#read 5, iclass 22, count 0 2006.257.17:17:20.81#ibcon#about to read 6, iclass 22, count 0 2006.257.17:17:20.81#ibcon#read 6, iclass 22, count 0 2006.257.17:17:20.81#ibcon#end of sib2, iclass 22, count 0 2006.257.17:17:20.81#ibcon#*after write, iclass 22, count 0 2006.257.17:17:20.81#ibcon#*before return 0, iclass 22, count 0 2006.257.17:17:20.81#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:20.81#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:17:20.81#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.17:17:20.81#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.17:17:20.81$vck44/vabw=wide 2006.257.17:17:20.81#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.17:17:20.81#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.17:17:20.81#ibcon#ireg 8 cls_cnt 0 2006.257.17:17:20.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:20.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:20.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:20.81#ibcon#enter wrdev, iclass 24, count 0 2006.257.17:17:20.81#ibcon#first serial, iclass 24, count 0 2006.257.17:17:20.81#ibcon#enter sib2, iclass 24, count 0 2006.257.17:17:20.81#ibcon#flushed, iclass 24, count 0 2006.257.17:17:20.81#ibcon#about to write, iclass 24, count 0 2006.257.17:17:20.81#ibcon#wrote, iclass 24, count 0 2006.257.17:17:20.81#ibcon#about to read 3, iclass 24, count 0 2006.257.17:17:20.83#ibcon#read 3, iclass 24, count 0 2006.257.17:17:20.83#ibcon#about to read 4, iclass 24, count 0 2006.257.17:17:20.83#ibcon#read 4, iclass 24, count 0 2006.257.17:17:20.83#ibcon#about to read 5, iclass 24, count 0 2006.257.17:17:20.83#ibcon#read 5, iclass 24, count 0 2006.257.17:17:20.83#ibcon#about to read 6, iclass 24, count 0 2006.257.17:17:20.83#ibcon#read 6, iclass 24, count 0 2006.257.17:17:20.83#ibcon#end of sib2, iclass 24, count 0 2006.257.17:17:20.83#ibcon#*mode == 0, iclass 24, count 0 2006.257.17:17:20.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.17:17:20.83#ibcon#[25=BW32\r\n] 2006.257.17:17:20.83#ibcon#*before write, iclass 24, count 0 2006.257.17:17:20.83#ibcon#enter sib2, iclass 24, count 0 2006.257.17:17:20.83#ibcon#flushed, iclass 24, count 0 2006.257.17:17:20.83#ibcon#about to write, iclass 24, count 0 2006.257.17:17:20.83#ibcon#wrote, iclass 24, count 0 2006.257.17:17:20.83#ibcon#about to read 3, iclass 24, count 0 2006.257.17:17:20.86#ibcon#read 3, iclass 24, count 0 2006.257.17:17:20.86#ibcon#about to read 4, iclass 24, count 0 2006.257.17:17:20.86#ibcon#read 4, iclass 24, count 0 2006.257.17:17:20.86#ibcon#about to read 5, iclass 24, count 0 2006.257.17:17:20.86#ibcon#read 5, iclass 24, count 0 2006.257.17:17:20.86#ibcon#about to read 6, iclass 24, count 0 2006.257.17:17:20.86#ibcon#read 6, iclass 24, count 0 2006.257.17:17:20.86#ibcon#end of sib2, iclass 24, count 0 2006.257.17:17:20.86#ibcon#*after write, iclass 24, count 0 2006.257.17:17:20.86#ibcon#*before return 0, iclass 24, count 0 2006.257.17:17:20.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:20.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:17:20.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.17:17:20.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.17:17:20.86$vck44/vbbw=wide 2006.257.17:17:20.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.17:17:20.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.17:17:20.86#ibcon#ireg 8 cls_cnt 0 2006.257.17:17:20.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:17:20.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:17:20.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:17:20.93#ibcon#enter wrdev, iclass 26, count 0 2006.257.17:17:20.93#ibcon#first serial, iclass 26, count 0 2006.257.17:17:20.93#ibcon#enter sib2, iclass 26, count 0 2006.257.17:17:20.93#ibcon#flushed, iclass 26, count 0 2006.257.17:17:20.93#ibcon#about to write, iclass 26, count 0 2006.257.17:17:20.93#ibcon#wrote, iclass 26, count 0 2006.257.17:17:20.93#ibcon#about to read 3, iclass 26, count 0 2006.257.17:17:20.95#ibcon#read 3, iclass 26, count 0 2006.257.17:17:20.95#ibcon#about to read 4, iclass 26, count 0 2006.257.17:17:20.95#ibcon#read 4, iclass 26, count 0 2006.257.17:17:20.95#ibcon#about to read 5, iclass 26, count 0 2006.257.17:17:20.95#ibcon#read 5, iclass 26, count 0 2006.257.17:17:20.95#ibcon#about to read 6, iclass 26, count 0 2006.257.17:17:20.95#ibcon#read 6, iclass 26, count 0 2006.257.17:17:20.95#ibcon#end of sib2, iclass 26, count 0 2006.257.17:17:20.95#ibcon#*mode == 0, iclass 26, count 0 2006.257.17:17:20.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.17:17:20.95#ibcon#[27=BW32\r\n] 2006.257.17:17:20.95#ibcon#*before write, iclass 26, count 0 2006.257.17:17:20.95#ibcon#enter sib2, iclass 26, count 0 2006.257.17:17:20.95#ibcon#flushed, iclass 26, count 0 2006.257.17:17:20.95#ibcon#about to write, iclass 26, count 0 2006.257.17:17:20.95#ibcon#wrote, iclass 26, count 0 2006.257.17:17:20.95#ibcon#about to read 3, iclass 26, count 0 2006.257.17:17:20.98#ibcon#read 3, iclass 26, count 0 2006.257.17:17:20.98#ibcon#about to read 4, iclass 26, count 0 2006.257.17:17:20.98#ibcon#read 4, iclass 26, count 0 2006.257.17:17:20.98#ibcon#about to read 5, iclass 26, count 0 2006.257.17:17:20.98#ibcon#read 5, iclass 26, count 0 2006.257.17:17:20.98#ibcon#about to read 6, iclass 26, count 0 2006.257.17:17:20.98#ibcon#read 6, iclass 26, count 0 2006.257.17:17:20.98#ibcon#end of sib2, iclass 26, count 0 2006.257.17:17:20.98#ibcon#*after write, iclass 26, count 0 2006.257.17:17:20.98#ibcon#*before return 0, iclass 26, count 0 2006.257.17:17:20.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:17:20.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:17:20.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.17:17:20.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.17:17:20.98$setupk4/ifdk4 2006.257.17:17:20.98$ifdk4/lo= 2006.257.17:17:20.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:17:20.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:17:20.98$ifdk4/patch= 2006.257.17:17:20.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:17:20.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:17:20.98$setupk4/!*+20s 2006.257.17:17:28.81#abcon#<5=/14 1.3 4.0 17.38 971014.3\r\n> 2006.257.17:17:28.83#abcon#{5=INTERFACE CLEAR} 2006.257.17:17:28.89#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:17:35.49$setupk4/"tpicd 2006.257.17:17:35.49$setupk4/echo=off 2006.257.17:17:35.49$setupk4/xlog=off 2006.257.17:17:35.49:!2006.257.17:27:33 2006.257.17:18:05.14#trakl#Source acquired 2006.257.17:18:05.14#flagr#flagr/antenna,acquired 2006.257.17:27:33.02:preob 2006.257.17:27:34.14/onsource/TRACKING 2006.257.17:27:34.14:!2006.257.17:27:43 2006.257.17:27:43.01:"tape 2006.257.17:27:43.02:"st=record 2006.257.17:27:43.02:data_valid=on 2006.257.17:27:43.02:midob 2006.257.17:27:44.14/onsource/TRACKING 2006.257.17:27:44.14/wx/17.40,1014.3,97 2006.257.17:27:44.19/cable/+6.4823E-03 2006.257.17:27:45.28/va/01,08,usb,yes,30,33 2006.257.17:27:45.28/va/02,07,usb,yes,33,33 2006.257.17:27:45.28/va/03,08,usb,yes,29,31 2006.257.17:27:45.28/va/04,07,usb,yes,34,35 2006.257.17:27:45.28/va/05,04,usb,yes,30,31 2006.257.17:27:45.28/va/06,04,usb,yes,34,33 2006.257.17:27:45.28/va/07,04,usb,yes,35,35 2006.257.17:27:45.28/va/08,04,usb,yes,29,35 2006.257.17:27:45.51/valo/01,524.99,yes,locked 2006.257.17:27:45.51/valo/02,534.99,yes,locked 2006.257.17:27:45.51/valo/03,564.99,yes,locked 2006.257.17:27:45.51/valo/04,624.99,yes,locked 2006.257.17:27:45.51/valo/05,734.99,yes,locked 2006.257.17:27:45.51/valo/06,814.99,yes,locked 2006.257.17:27:45.51/valo/07,864.99,yes,locked 2006.257.17:27:45.51/valo/08,884.99,yes,locked 2006.257.17:27:46.60/vb/01,04,usb,yes,30,28 2006.257.17:27:46.60/vb/02,05,usb,yes,28,28 2006.257.17:27:46.60/vb/03,04,usb,yes,29,32 2006.257.17:27:46.60/vb/04,05,usb,yes,30,29 2006.257.17:27:46.60/vb/05,04,usb,yes,26,29 2006.257.17:27:46.60/vb/06,04,usb,yes,31,27 2006.257.17:27:46.60/vb/07,04,usb,yes,30,30 2006.257.17:27:46.60/vb/08,04,usb,yes,28,31 2006.257.17:27:46.83/vblo/01,629.99,yes,locked 2006.257.17:27:46.83/vblo/02,634.99,yes,locked 2006.257.17:27:46.83/vblo/03,649.99,yes,locked 2006.257.17:27:46.83/vblo/04,679.99,yes,locked 2006.257.17:27:46.83/vblo/05,709.99,yes,locked 2006.257.17:27:46.83/vblo/06,719.99,yes,locked 2006.257.17:27:46.83/vblo/07,734.99,yes,locked 2006.257.17:27:46.83/vblo/08,744.99,yes,locked 2006.257.17:27:46.98/vabw/8 2006.257.17:27:47.13/vbbw/8 2006.257.17:27:47.22/xfe/off,on,15.0 2006.257.17:27:47.59/ifatt/23,28,28,28 2006.257.17:27:48.07/fmout-gps/S +4.49E-07 2006.257.17:27:48.12:!2006.257.17:29:33 2006.257.17:29:33.01:data_valid=off 2006.257.17:29:33.02:"et 2006.257.17:29:33.02:!+3s 2006.257.17:29:36.03:"tape 2006.257.17:29:36.04:postob 2006.257.17:29:36.27/cable/+6.4831E-03 2006.257.17:29:36.28/wx/17.40,1014.2,97 2006.257.17:29:36.33/fmout-gps/S +4.51E-07 2006.257.17:29:36.34:scan_name=257-1732,jd0609,100 2006.257.17:29:36.34:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.257.17:29:38.14#flagr#flagr/antenna,new-source 2006.257.17:29:38.15:checkk5 2006.257.17:29:38.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:29:38.84/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:29:39.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:29:39.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:29:39.86/chk_obsdata//k5ts1/T2571727??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.17:29:40.20/chk_obsdata//k5ts2/T2571727??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.17:29:40.53/chk_obsdata//k5ts3/T2571727??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.17:29:40.87/chk_obsdata//k5ts4/T2571727??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.17:29:41.54/k5log//k5ts1_log_newline 2006.257.17:29:42.21/k5log//k5ts2_log_newline 2006.257.17:29:42.88/k5log//k5ts3_log_newline 2006.257.17:29:43.53/k5log//k5ts4_log_newline 2006.257.17:29:43.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:29:43.56:setupk4=1 2006.257.17:29:43.56$setupk4/echo=on 2006.257.17:29:43.56$setupk4/pcalon 2006.257.17:29:43.56$pcalon/"no phase cal control is implemented here 2006.257.17:29:43.56$setupk4/"tpicd=stop 2006.257.17:29:43.56$setupk4/"rec=synch_on 2006.257.17:29:43.56$setupk4/"rec_mode=128 2006.257.17:29:43.56$setupk4/!* 2006.257.17:29:43.56$setupk4/recpk4 2006.257.17:29:43.56$recpk4/recpatch= 2006.257.17:29:43.57$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:29:43.57$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:29:43.57$setupk4/vck44 2006.257.17:29:43.57$vck44/valo=1,524.99 2006.257.17:29:43.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.17:29:43.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.17:29:43.57#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:43.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:43.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:43.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:43.57#ibcon#enter wrdev, iclass 35, count 0 2006.257.17:29:43.57#ibcon#first serial, iclass 35, count 0 2006.257.17:29:43.57#ibcon#enter sib2, iclass 35, count 0 2006.257.17:29:43.57#ibcon#flushed, iclass 35, count 0 2006.257.17:29:43.57#ibcon#about to write, iclass 35, count 0 2006.257.17:29:43.57#ibcon#wrote, iclass 35, count 0 2006.257.17:29:43.57#ibcon#about to read 3, iclass 35, count 0 2006.257.17:29:43.58#ibcon#read 3, iclass 35, count 0 2006.257.17:29:43.58#ibcon#about to read 4, iclass 35, count 0 2006.257.17:29:43.58#ibcon#read 4, iclass 35, count 0 2006.257.17:29:43.58#ibcon#about to read 5, iclass 35, count 0 2006.257.17:29:43.58#ibcon#read 5, iclass 35, count 0 2006.257.17:29:43.58#ibcon#about to read 6, iclass 35, count 0 2006.257.17:29:43.58#ibcon#read 6, iclass 35, count 0 2006.257.17:29:43.58#ibcon#end of sib2, iclass 35, count 0 2006.257.17:29:43.58#ibcon#*mode == 0, iclass 35, count 0 2006.257.17:29:43.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.17:29:43.58#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:29:43.58#ibcon#*before write, iclass 35, count 0 2006.257.17:29:43.58#ibcon#enter sib2, iclass 35, count 0 2006.257.17:29:43.58#ibcon#flushed, iclass 35, count 0 2006.257.17:29:43.58#ibcon#about to write, iclass 35, count 0 2006.257.17:29:43.58#ibcon#wrote, iclass 35, count 0 2006.257.17:29:43.58#ibcon#about to read 3, iclass 35, count 0 2006.257.17:29:43.63#ibcon#read 3, iclass 35, count 0 2006.257.17:29:43.63#ibcon#about to read 4, iclass 35, count 0 2006.257.17:29:43.63#ibcon#read 4, iclass 35, count 0 2006.257.17:29:43.63#ibcon#about to read 5, iclass 35, count 0 2006.257.17:29:43.63#ibcon#read 5, iclass 35, count 0 2006.257.17:29:43.63#ibcon#about to read 6, iclass 35, count 0 2006.257.17:29:43.63#ibcon#read 6, iclass 35, count 0 2006.257.17:29:43.63#ibcon#end of sib2, iclass 35, count 0 2006.257.17:29:43.63#ibcon#*after write, iclass 35, count 0 2006.257.17:29:43.63#ibcon#*before return 0, iclass 35, count 0 2006.257.17:29:43.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:43.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:43.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.17:29:43.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.17:29:43.64$vck44/va=1,8 2006.257.17:29:43.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.17:29:43.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.17:29:43.64#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:43.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:43.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:43.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:43.64#ibcon#enter wrdev, iclass 37, count 2 2006.257.17:29:43.64#ibcon#first serial, iclass 37, count 2 2006.257.17:29:43.64#ibcon#enter sib2, iclass 37, count 2 2006.257.17:29:43.64#ibcon#flushed, iclass 37, count 2 2006.257.17:29:43.64#ibcon#about to write, iclass 37, count 2 2006.257.17:29:43.64#ibcon#wrote, iclass 37, count 2 2006.257.17:29:43.64#ibcon#about to read 3, iclass 37, count 2 2006.257.17:29:43.65#ibcon#read 3, iclass 37, count 2 2006.257.17:29:43.65#ibcon#about to read 4, iclass 37, count 2 2006.257.17:29:43.65#ibcon#read 4, iclass 37, count 2 2006.257.17:29:43.65#ibcon#about to read 5, iclass 37, count 2 2006.257.17:29:43.65#ibcon#read 5, iclass 37, count 2 2006.257.17:29:43.65#ibcon#about to read 6, iclass 37, count 2 2006.257.17:29:43.65#ibcon#read 6, iclass 37, count 2 2006.257.17:29:43.65#ibcon#end of sib2, iclass 37, count 2 2006.257.17:29:43.65#ibcon#*mode == 0, iclass 37, count 2 2006.257.17:29:43.65#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.17:29:43.65#ibcon#[25=AT01-08\r\n] 2006.257.17:29:43.65#ibcon#*before write, iclass 37, count 2 2006.257.17:29:43.65#ibcon#enter sib2, iclass 37, count 2 2006.257.17:29:43.65#ibcon#flushed, iclass 37, count 2 2006.257.17:29:43.65#ibcon#about to write, iclass 37, count 2 2006.257.17:29:43.65#ibcon#wrote, iclass 37, count 2 2006.257.17:29:43.65#ibcon#about to read 3, iclass 37, count 2 2006.257.17:29:43.68#ibcon#read 3, iclass 37, count 2 2006.257.17:29:43.68#ibcon#about to read 4, iclass 37, count 2 2006.257.17:29:43.68#ibcon#read 4, iclass 37, count 2 2006.257.17:29:43.68#ibcon#about to read 5, iclass 37, count 2 2006.257.17:29:43.68#ibcon#read 5, iclass 37, count 2 2006.257.17:29:43.68#ibcon#about to read 6, iclass 37, count 2 2006.257.17:29:43.68#ibcon#read 6, iclass 37, count 2 2006.257.17:29:43.68#ibcon#end of sib2, iclass 37, count 2 2006.257.17:29:43.68#ibcon#*after write, iclass 37, count 2 2006.257.17:29:43.68#ibcon#*before return 0, iclass 37, count 2 2006.257.17:29:43.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:43.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:43.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.17:29:43.68#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:43.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:43.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:43.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:43.80#ibcon#enter wrdev, iclass 37, count 0 2006.257.17:29:43.80#ibcon#first serial, iclass 37, count 0 2006.257.17:29:43.80#ibcon#enter sib2, iclass 37, count 0 2006.257.17:29:43.80#ibcon#flushed, iclass 37, count 0 2006.257.17:29:43.80#ibcon#about to write, iclass 37, count 0 2006.257.17:29:43.80#ibcon#wrote, iclass 37, count 0 2006.257.17:29:43.80#ibcon#about to read 3, iclass 37, count 0 2006.257.17:29:43.82#ibcon#read 3, iclass 37, count 0 2006.257.17:29:43.82#ibcon#about to read 4, iclass 37, count 0 2006.257.17:29:43.82#ibcon#read 4, iclass 37, count 0 2006.257.17:29:43.82#ibcon#about to read 5, iclass 37, count 0 2006.257.17:29:43.82#ibcon#read 5, iclass 37, count 0 2006.257.17:29:43.82#ibcon#about to read 6, iclass 37, count 0 2006.257.17:29:43.82#ibcon#read 6, iclass 37, count 0 2006.257.17:29:43.82#ibcon#end of sib2, iclass 37, count 0 2006.257.17:29:43.82#ibcon#*mode == 0, iclass 37, count 0 2006.257.17:29:43.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.17:29:43.82#ibcon#[25=USB\r\n] 2006.257.17:29:43.82#ibcon#*before write, iclass 37, count 0 2006.257.17:29:43.82#ibcon#enter sib2, iclass 37, count 0 2006.257.17:29:43.82#ibcon#flushed, iclass 37, count 0 2006.257.17:29:43.82#ibcon#about to write, iclass 37, count 0 2006.257.17:29:43.82#ibcon#wrote, iclass 37, count 0 2006.257.17:29:43.82#ibcon#about to read 3, iclass 37, count 0 2006.257.17:29:43.85#ibcon#read 3, iclass 37, count 0 2006.257.17:29:43.85#ibcon#about to read 4, iclass 37, count 0 2006.257.17:29:43.85#ibcon#read 4, iclass 37, count 0 2006.257.17:29:43.85#ibcon#about to read 5, iclass 37, count 0 2006.257.17:29:43.85#ibcon#read 5, iclass 37, count 0 2006.257.17:29:43.85#ibcon#about to read 6, iclass 37, count 0 2006.257.17:29:43.85#ibcon#read 6, iclass 37, count 0 2006.257.17:29:43.85#ibcon#end of sib2, iclass 37, count 0 2006.257.17:29:43.85#ibcon#*after write, iclass 37, count 0 2006.257.17:29:43.85#ibcon#*before return 0, iclass 37, count 0 2006.257.17:29:43.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:43.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:43.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.17:29:43.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.17:29:43.86$vck44/valo=2,534.99 2006.257.17:29:43.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.17:29:43.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.17:29:43.86#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:43.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:43.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:43.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:43.86#ibcon#enter wrdev, iclass 39, count 0 2006.257.17:29:43.86#ibcon#first serial, iclass 39, count 0 2006.257.17:29:43.86#ibcon#enter sib2, iclass 39, count 0 2006.257.17:29:43.86#ibcon#flushed, iclass 39, count 0 2006.257.17:29:43.86#ibcon#about to write, iclass 39, count 0 2006.257.17:29:43.86#ibcon#wrote, iclass 39, count 0 2006.257.17:29:43.86#ibcon#about to read 3, iclass 39, count 0 2006.257.17:29:43.87#ibcon#read 3, iclass 39, count 0 2006.257.17:29:43.87#ibcon#about to read 4, iclass 39, count 0 2006.257.17:29:43.87#ibcon#read 4, iclass 39, count 0 2006.257.17:29:43.87#ibcon#about to read 5, iclass 39, count 0 2006.257.17:29:43.87#ibcon#read 5, iclass 39, count 0 2006.257.17:29:43.87#ibcon#about to read 6, iclass 39, count 0 2006.257.17:29:43.87#ibcon#read 6, iclass 39, count 0 2006.257.17:29:43.87#ibcon#end of sib2, iclass 39, count 0 2006.257.17:29:43.87#ibcon#*mode == 0, iclass 39, count 0 2006.257.17:29:43.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.17:29:43.87#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:29:43.87#ibcon#*before write, iclass 39, count 0 2006.257.17:29:43.87#ibcon#enter sib2, iclass 39, count 0 2006.257.17:29:43.87#ibcon#flushed, iclass 39, count 0 2006.257.17:29:43.87#ibcon#about to write, iclass 39, count 0 2006.257.17:29:43.87#ibcon#wrote, iclass 39, count 0 2006.257.17:29:43.87#ibcon#about to read 3, iclass 39, count 0 2006.257.17:29:43.91#ibcon#read 3, iclass 39, count 0 2006.257.17:29:43.91#ibcon#about to read 4, iclass 39, count 0 2006.257.17:29:43.91#ibcon#read 4, iclass 39, count 0 2006.257.17:29:43.91#ibcon#about to read 5, iclass 39, count 0 2006.257.17:29:43.91#ibcon#read 5, iclass 39, count 0 2006.257.17:29:43.91#ibcon#about to read 6, iclass 39, count 0 2006.257.17:29:43.91#ibcon#read 6, iclass 39, count 0 2006.257.17:29:43.91#ibcon#end of sib2, iclass 39, count 0 2006.257.17:29:43.91#ibcon#*after write, iclass 39, count 0 2006.257.17:29:43.91#ibcon#*before return 0, iclass 39, count 0 2006.257.17:29:43.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:43.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:43.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.17:29:43.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.17:29:43.92$vck44/va=2,7 2006.257.17:29:43.92#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.17:29:43.92#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.17:29:43.92#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:43.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:43.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:43.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:43.96#ibcon#enter wrdev, iclass 3, count 2 2006.257.17:29:43.96#ibcon#first serial, iclass 3, count 2 2006.257.17:29:43.96#ibcon#enter sib2, iclass 3, count 2 2006.257.17:29:43.96#ibcon#flushed, iclass 3, count 2 2006.257.17:29:43.96#ibcon#about to write, iclass 3, count 2 2006.257.17:29:43.96#ibcon#wrote, iclass 3, count 2 2006.257.17:29:43.96#ibcon#about to read 3, iclass 3, count 2 2006.257.17:29:43.98#ibcon#read 3, iclass 3, count 2 2006.257.17:29:43.98#ibcon#about to read 4, iclass 3, count 2 2006.257.17:29:43.98#ibcon#read 4, iclass 3, count 2 2006.257.17:29:43.98#ibcon#about to read 5, iclass 3, count 2 2006.257.17:29:43.98#ibcon#read 5, iclass 3, count 2 2006.257.17:29:43.98#ibcon#about to read 6, iclass 3, count 2 2006.257.17:29:43.98#ibcon#read 6, iclass 3, count 2 2006.257.17:29:43.98#ibcon#end of sib2, iclass 3, count 2 2006.257.17:29:43.98#ibcon#*mode == 0, iclass 3, count 2 2006.257.17:29:43.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.17:29:43.98#ibcon#[25=AT02-07\r\n] 2006.257.17:29:43.98#ibcon#*before write, iclass 3, count 2 2006.257.17:29:43.98#ibcon#enter sib2, iclass 3, count 2 2006.257.17:29:43.98#ibcon#flushed, iclass 3, count 2 2006.257.17:29:43.98#ibcon#about to write, iclass 3, count 2 2006.257.17:29:43.98#ibcon#wrote, iclass 3, count 2 2006.257.17:29:43.98#ibcon#about to read 3, iclass 3, count 2 2006.257.17:29:44.01#ibcon#read 3, iclass 3, count 2 2006.257.17:29:44.01#ibcon#about to read 4, iclass 3, count 2 2006.257.17:29:44.01#ibcon#read 4, iclass 3, count 2 2006.257.17:29:44.01#ibcon#about to read 5, iclass 3, count 2 2006.257.17:29:44.01#ibcon#read 5, iclass 3, count 2 2006.257.17:29:44.01#ibcon#about to read 6, iclass 3, count 2 2006.257.17:29:44.01#ibcon#read 6, iclass 3, count 2 2006.257.17:29:44.01#ibcon#end of sib2, iclass 3, count 2 2006.257.17:29:44.01#ibcon#*after write, iclass 3, count 2 2006.257.17:29:44.01#ibcon#*before return 0, iclass 3, count 2 2006.257.17:29:44.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:44.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:44.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.17:29:44.01#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:44.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:44.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:44.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:44.13#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:29:44.13#ibcon#first serial, iclass 3, count 0 2006.257.17:29:44.13#ibcon#enter sib2, iclass 3, count 0 2006.257.17:29:44.13#ibcon#flushed, iclass 3, count 0 2006.257.17:29:44.13#ibcon#about to write, iclass 3, count 0 2006.257.17:29:44.13#ibcon#wrote, iclass 3, count 0 2006.257.17:29:44.13#ibcon#about to read 3, iclass 3, count 0 2006.257.17:29:44.15#ibcon#read 3, iclass 3, count 0 2006.257.17:29:44.15#ibcon#about to read 4, iclass 3, count 0 2006.257.17:29:44.15#ibcon#read 4, iclass 3, count 0 2006.257.17:29:44.15#ibcon#about to read 5, iclass 3, count 0 2006.257.17:29:44.15#ibcon#read 5, iclass 3, count 0 2006.257.17:29:44.15#ibcon#about to read 6, iclass 3, count 0 2006.257.17:29:44.15#ibcon#read 6, iclass 3, count 0 2006.257.17:29:44.15#ibcon#end of sib2, iclass 3, count 0 2006.257.17:29:44.15#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:29:44.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:29:44.15#ibcon#[25=USB\r\n] 2006.257.17:29:44.15#ibcon#*before write, iclass 3, count 0 2006.257.17:29:44.15#ibcon#enter sib2, iclass 3, count 0 2006.257.17:29:44.15#ibcon#flushed, iclass 3, count 0 2006.257.17:29:44.15#ibcon#about to write, iclass 3, count 0 2006.257.17:29:44.15#ibcon#wrote, iclass 3, count 0 2006.257.17:29:44.15#ibcon#about to read 3, iclass 3, count 0 2006.257.17:29:44.18#ibcon#read 3, iclass 3, count 0 2006.257.17:29:44.18#ibcon#about to read 4, iclass 3, count 0 2006.257.17:29:44.18#ibcon#read 4, iclass 3, count 0 2006.257.17:29:44.18#ibcon#about to read 5, iclass 3, count 0 2006.257.17:29:44.18#ibcon#read 5, iclass 3, count 0 2006.257.17:29:44.18#ibcon#about to read 6, iclass 3, count 0 2006.257.17:29:44.18#ibcon#read 6, iclass 3, count 0 2006.257.17:29:44.18#ibcon#end of sib2, iclass 3, count 0 2006.257.17:29:44.18#ibcon#*after write, iclass 3, count 0 2006.257.17:29:44.18#ibcon#*before return 0, iclass 3, count 0 2006.257.17:29:44.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:44.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:44.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:29:44.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:29:44.19$vck44/valo=3,564.99 2006.257.17:29:44.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.17:29:44.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.17:29:44.19#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:44.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:44.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:44.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:44.19#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:29:44.19#ibcon#first serial, iclass 5, count 0 2006.257.17:29:44.19#ibcon#enter sib2, iclass 5, count 0 2006.257.17:29:44.19#ibcon#flushed, iclass 5, count 0 2006.257.17:29:44.19#ibcon#about to write, iclass 5, count 0 2006.257.17:29:44.19#ibcon#wrote, iclass 5, count 0 2006.257.17:29:44.19#ibcon#about to read 3, iclass 5, count 0 2006.257.17:29:44.20#ibcon#read 3, iclass 5, count 0 2006.257.17:29:44.20#ibcon#about to read 4, iclass 5, count 0 2006.257.17:29:44.20#ibcon#read 4, iclass 5, count 0 2006.257.17:29:44.20#ibcon#about to read 5, iclass 5, count 0 2006.257.17:29:44.20#ibcon#read 5, iclass 5, count 0 2006.257.17:29:44.20#ibcon#about to read 6, iclass 5, count 0 2006.257.17:29:44.20#ibcon#read 6, iclass 5, count 0 2006.257.17:29:44.20#ibcon#end of sib2, iclass 5, count 0 2006.257.17:29:44.20#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:29:44.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:29:44.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:29:44.20#ibcon#*before write, iclass 5, count 0 2006.257.17:29:44.20#ibcon#enter sib2, iclass 5, count 0 2006.257.17:29:44.20#ibcon#flushed, iclass 5, count 0 2006.257.17:29:44.20#ibcon#about to write, iclass 5, count 0 2006.257.17:29:44.20#ibcon#wrote, iclass 5, count 0 2006.257.17:29:44.20#ibcon#about to read 3, iclass 5, count 0 2006.257.17:29:44.24#ibcon#read 3, iclass 5, count 0 2006.257.17:29:44.24#ibcon#about to read 4, iclass 5, count 0 2006.257.17:29:44.24#ibcon#read 4, iclass 5, count 0 2006.257.17:29:44.24#ibcon#about to read 5, iclass 5, count 0 2006.257.17:29:44.24#ibcon#read 5, iclass 5, count 0 2006.257.17:29:44.24#ibcon#about to read 6, iclass 5, count 0 2006.257.17:29:44.24#ibcon#read 6, iclass 5, count 0 2006.257.17:29:44.24#ibcon#end of sib2, iclass 5, count 0 2006.257.17:29:44.24#ibcon#*after write, iclass 5, count 0 2006.257.17:29:44.24#ibcon#*before return 0, iclass 5, count 0 2006.257.17:29:44.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:44.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:44.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:29:44.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:29:44.25$vck44/va=3,8 2006.257.17:29:44.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.17:29:44.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.17:29:44.25#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:44.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:44.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:44.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:44.29#ibcon#enter wrdev, iclass 7, count 2 2006.257.17:29:44.29#ibcon#first serial, iclass 7, count 2 2006.257.17:29:44.29#ibcon#enter sib2, iclass 7, count 2 2006.257.17:29:44.29#ibcon#flushed, iclass 7, count 2 2006.257.17:29:44.29#ibcon#about to write, iclass 7, count 2 2006.257.17:29:44.29#ibcon#wrote, iclass 7, count 2 2006.257.17:29:44.29#ibcon#about to read 3, iclass 7, count 2 2006.257.17:29:44.31#ibcon#read 3, iclass 7, count 2 2006.257.17:29:44.31#ibcon#about to read 4, iclass 7, count 2 2006.257.17:29:44.31#ibcon#read 4, iclass 7, count 2 2006.257.17:29:44.31#ibcon#about to read 5, iclass 7, count 2 2006.257.17:29:44.31#ibcon#read 5, iclass 7, count 2 2006.257.17:29:44.31#ibcon#about to read 6, iclass 7, count 2 2006.257.17:29:44.31#ibcon#read 6, iclass 7, count 2 2006.257.17:29:44.31#ibcon#end of sib2, iclass 7, count 2 2006.257.17:29:44.31#ibcon#*mode == 0, iclass 7, count 2 2006.257.17:29:44.31#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.17:29:44.31#ibcon#[25=AT03-08\r\n] 2006.257.17:29:44.31#ibcon#*before write, iclass 7, count 2 2006.257.17:29:44.31#ibcon#enter sib2, iclass 7, count 2 2006.257.17:29:44.31#ibcon#flushed, iclass 7, count 2 2006.257.17:29:44.31#ibcon#about to write, iclass 7, count 2 2006.257.17:29:44.31#ibcon#wrote, iclass 7, count 2 2006.257.17:29:44.31#ibcon#about to read 3, iclass 7, count 2 2006.257.17:29:44.34#ibcon#read 3, iclass 7, count 2 2006.257.17:29:44.34#ibcon#about to read 4, iclass 7, count 2 2006.257.17:29:44.34#ibcon#read 4, iclass 7, count 2 2006.257.17:29:44.34#ibcon#about to read 5, iclass 7, count 2 2006.257.17:29:44.34#ibcon#read 5, iclass 7, count 2 2006.257.17:29:44.34#ibcon#about to read 6, iclass 7, count 2 2006.257.17:29:44.34#ibcon#read 6, iclass 7, count 2 2006.257.17:29:44.34#ibcon#end of sib2, iclass 7, count 2 2006.257.17:29:44.34#ibcon#*after write, iclass 7, count 2 2006.257.17:29:44.34#ibcon#*before return 0, iclass 7, count 2 2006.257.17:29:44.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:44.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:44.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.17:29:44.34#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:44.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:44.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:44.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:44.46#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:29:44.46#ibcon#first serial, iclass 7, count 0 2006.257.17:29:44.46#ibcon#enter sib2, iclass 7, count 0 2006.257.17:29:44.46#ibcon#flushed, iclass 7, count 0 2006.257.17:29:44.46#ibcon#about to write, iclass 7, count 0 2006.257.17:29:44.46#ibcon#wrote, iclass 7, count 0 2006.257.17:29:44.46#ibcon#about to read 3, iclass 7, count 0 2006.257.17:29:44.48#ibcon#read 3, iclass 7, count 0 2006.257.17:29:44.48#ibcon#about to read 4, iclass 7, count 0 2006.257.17:29:44.48#ibcon#read 4, iclass 7, count 0 2006.257.17:29:44.48#ibcon#about to read 5, iclass 7, count 0 2006.257.17:29:44.48#ibcon#read 5, iclass 7, count 0 2006.257.17:29:44.48#ibcon#about to read 6, iclass 7, count 0 2006.257.17:29:44.48#ibcon#read 6, iclass 7, count 0 2006.257.17:29:44.48#ibcon#end of sib2, iclass 7, count 0 2006.257.17:29:44.48#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:29:44.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:29:44.48#ibcon#[25=USB\r\n] 2006.257.17:29:44.48#ibcon#*before write, iclass 7, count 0 2006.257.17:29:44.48#ibcon#enter sib2, iclass 7, count 0 2006.257.17:29:44.48#ibcon#flushed, iclass 7, count 0 2006.257.17:29:44.48#ibcon#about to write, iclass 7, count 0 2006.257.17:29:44.48#ibcon#wrote, iclass 7, count 0 2006.257.17:29:44.48#ibcon#about to read 3, iclass 7, count 0 2006.257.17:29:44.51#ibcon#read 3, iclass 7, count 0 2006.257.17:29:44.51#ibcon#about to read 4, iclass 7, count 0 2006.257.17:29:44.51#ibcon#read 4, iclass 7, count 0 2006.257.17:29:44.51#ibcon#about to read 5, iclass 7, count 0 2006.257.17:29:44.51#ibcon#read 5, iclass 7, count 0 2006.257.17:29:44.51#ibcon#about to read 6, iclass 7, count 0 2006.257.17:29:44.51#ibcon#read 6, iclass 7, count 0 2006.257.17:29:44.51#ibcon#end of sib2, iclass 7, count 0 2006.257.17:29:44.51#ibcon#*after write, iclass 7, count 0 2006.257.17:29:44.51#ibcon#*before return 0, iclass 7, count 0 2006.257.17:29:44.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:44.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:44.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:29:44.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:29:44.52$vck44/valo=4,624.99 2006.257.17:29:44.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.17:29:44.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.17:29:44.52#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:44.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:44.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:44.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:44.52#ibcon#enter wrdev, iclass 11, count 0 2006.257.17:29:44.52#ibcon#first serial, iclass 11, count 0 2006.257.17:29:44.52#ibcon#enter sib2, iclass 11, count 0 2006.257.17:29:44.52#ibcon#flushed, iclass 11, count 0 2006.257.17:29:44.52#ibcon#about to write, iclass 11, count 0 2006.257.17:29:44.52#ibcon#wrote, iclass 11, count 0 2006.257.17:29:44.52#ibcon#about to read 3, iclass 11, count 0 2006.257.17:29:44.53#ibcon#read 3, iclass 11, count 0 2006.257.17:29:44.53#ibcon#about to read 4, iclass 11, count 0 2006.257.17:29:44.53#ibcon#read 4, iclass 11, count 0 2006.257.17:29:44.53#ibcon#about to read 5, iclass 11, count 0 2006.257.17:29:44.53#ibcon#read 5, iclass 11, count 0 2006.257.17:29:44.53#ibcon#about to read 6, iclass 11, count 0 2006.257.17:29:44.53#ibcon#read 6, iclass 11, count 0 2006.257.17:29:44.53#ibcon#end of sib2, iclass 11, count 0 2006.257.17:29:44.53#ibcon#*mode == 0, iclass 11, count 0 2006.257.17:29:44.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.17:29:44.53#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:29:44.53#ibcon#*before write, iclass 11, count 0 2006.257.17:29:44.53#ibcon#enter sib2, iclass 11, count 0 2006.257.17:29:44.53#ibcon#flushed, iclass 11, count 0 2006.257.17:29:44.53#ibcon#about to write, iclass 11, count 0 2006.257.17:29:44.53#ibcon#wrote, iclass 11, count 0 2006.257.17:29:44.53#ibcon#about to read 3, iclass 11, count 0 2006.257.17:29:44.57#ibcon#read 3, iclass 11, count 0 2006.257.17:29:44.57#ibcon#about to read 4, iclass 11, count 0 2006.257.17:29:44.57#ibcon#read 4, iclass 11, count 0 2006.257.17:29:44.57#ibcon#about to read 5, iclass 11, count 0 2006.257.17:29:44.57#ibcon#read 5, iclass 11, count 0 2006.257.17:29:44.57#ibcon#about to read 6, iclass 11, count 0 2006.257.17:29:44.57#ibcon#read 6, iclass 11, count 0 2006.257.17:29:44.57#ibcon#end of sib2, iclass 11, count 0 2006.257.17:29:44.57#ibcon#*after write, iclass 11, count 0 2006.257.17:29:44.57#ibcon#*before return 0, iclass 11, count 0 2006.257.17:29:44.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:44.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:44.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.17:29:44.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.17:29:44.58$vck44/va=4,7 2006.257.17:29:44.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.17:29:44.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.17:29:44.58#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:44.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:44.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:44.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:44.62#ibcon#enter wrdev, iclass 13, count 2 2006.257.17:29:44.62#ibcon#first serial, iclass 13, count 2 2006.257.17:29:44.62#ibcon#enter sib2, iclass 13, count 2 2006.257.17:29:44.62#ibcon#flushed, iclass 13, count 2 2006.257.17:29:44.62#ibcon#about to write, iclass 13, count 2 2006.257.17:29:44.62#ibcon#wrote, iclass 13, count 2 2006.257.17:29:44.62#ibcon#about to read 3, iclass 13, count 2 2006.257.17:29:44.64#ibcon#read 3, iclass 13, count 2 2006.257.17:29:44.64#ibcon#about to read 4, iclass 13, count 2 2006.257.17:29:44.64#ibcon#read 4, iclass 13, count 2 2006.257.17:29:44.64#ibcon#about to read 5, iclass 13, count 2 2006.257.17:29:44.64#ibcon#read 5, iclass 13, count 2 2006.257.17:29:44.64#ibcon#about to read 6, iclass 13, count 2 2006.257.17:29:44.64#ibcon#read 6, iclass 13, count 2 2006.257.17:29:44.64#ibcon#end of sib2, iclass 13, count 2 2006.257.17:29:44.64#ibcon#*mode == 0, iclass 13, count 2 2006.257.17:29:44.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.17:29:44.64#ibcon#[25=AT04-07\r\n] 2006.257.17:29:44.64#ibcon#*before write, iclass 13, count 2 2006.257.17:29:44.64#ibcon#enter sib2, iclass 13, count 2 2006.257.17:29:44.64#ibcon#flushed, iclass 13, count 2 2006.257.17:29:44.64#ibcon#about to write, iclass 13, count 2 2006.257.17:29:44.64#ibcon#wrote, iclass 13, count 2 2006.257.17:29:44.64#ibcon#about to read 3, iclass 13, count 2 2006.257.17:29:44.67#ibcon#read 3, iclass 13, count 2 2006.257.17:29:44.67#ibcon#about to read 4, iclass 13, count 2 2006.257.17:29:44.67#ibcon#read 4, iclass 13, count 2 2006.257.17:29:44.67#ibcon#about to read 5, iclass 13, count 2 2006.257.17:29:44.67#ibcon#read 5, iclass 13, count 2 2006.257.17:29:44.67#ibcon#about to read 6, iclass 13, count 2 2006.257.17:29:44.67#ibcon#read 6, iclass 13, count 2 2006.257.17:29:44.67#ibcon#end of sib2, iclass 13, count 2 2006.257.17:29:44.67#ibcon#*after write, iclass 13, count 2 2006.257.17:29:44.67#ibcon#*before return 0, iclass 13, count 2 2006.257.17:29:44.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:44.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:44.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.17:29:44.67#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:44.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:44.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:44.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:44.79#ibcon#enter wrdev, iclass 13, count 0 2006.257.17:29:44.79#ibcon#first serial, iclass 13, count 0 2006.257.17:29:44.79#ibcon#enter sib2, iclass 13, count 0 2006.257.17:29:44.79#ibcon#flushed, iclass 13, count 0 2006.257.17:29:44.79#ibcon#about to write, iclass 13, count 0 2006.257.17:29:44.79#ibcon#wrote, iclass 13, count 0 2006.257.17:29:44.79#ibcon#about to read 3, iclass 13, count 0 2006.257.17:29:44.81#ibcon#read 3, iclass 13, count 0 2006.257.17:29:44.81#ibcon#about to read 4, iclass 13, count 0 2006.257.17:29:44.81#ibcon#read 4, iclass 13, count 0 2006.257.17:29:44.81#ibcon#about to read 5, iclass 13, count 0 2006.257.17:29:44.81#ibcon#read 5, iclass 13, count 0 2006.257.17:29:44.81#ibcon#about to read 6, iclass 13, count 0 2006.257.17:29:44.81#ibcon#read 6, iclass 13, count 0 2006.257.17:29:44.81#ibcon#end of sib2, iclass 13, count 0 2006.257.17:29:44.81#ibcon#*mode == 0, iclass 13, count 0 2006.257.17:29:44.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.17:29:44.81#ibcon#[25=USB\r\n] 2006.257.17:29:44.81#ibcon#*before write, iclass 13, count 0 2006.257.17:29:44.81#ibcon#enter sib2, iclass 13, count 0 2006.257.17:29:44.81#ibcon#flushed, iclass 13, count 0 2006.257.17:29:44.81#ibcon#about to write, iclass 13, count 0 2006.257.17:29:44.81#ibcon#wrote, iclass 13, count 0 2006.257.17:29:44.81#ibcon#about to read 3, iclass 13, count 0 2006.257.17:29:44.84#ibcon#read 3, iclass 13, count 0 2006.257.17:29:44.84#ibcon#about to read 4, iclass 13, count 0 2006.257.17:29:44.84#ibcon#read 4, iclass 13, count 0 2006.257.17:29:44.84#ibcon#about to read 5, iclass 13, count 0 2006.257.17:29:44.84#ibcon#read 5, iclass 13, count 0 2006.257.17:29:44.84#ibcon#about to read 6, iclass 13, count 0 2006.257.17:29:44.84#ibcon#read 6, iclass 13, count 0 2006.257.17:29:44.84#ibcon#end of sib2, iclass 13, count 0 2006.257.17:29:44.84#ibcon#*after write, iclass 13, count 0 2006.257.17:29:44.84#ibcon#*before return 0, iclass 13, count 0 2006.257.17:29:44.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:44.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:44.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.17:29:44.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.17:29:44.85$vck44/valo=5,734.99 2006.257.17:29:44.85#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.17:29:44.85#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.17:29:44.85#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:44.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:44.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:44.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:44.85#ibcon#enter wrdev, iclass 15, count 0 2006.257.17:29:44.85#ibcon#first serial, iclass 15, count 0 2006.257.17:29:44.85#ibcon#enter sib2, iclass 15, count 0 2006.257.17:29:44.85#ibcon#flushed, iclass 15, count 0 2006.257.17:29:44.85#ibcon#about to write, iclass 15, count 0 2006.257.17:29:44.85#ibcon#wrote, iclass 15, count 0 2006.257.17:29:44.85#ibcon#about to read 3, iclass 15, count 0 2006.257.17:29:44.86#ibcon#read 3, iclass 15, count 0 2006.257.17:29:44.86#ibcon#about to read 4, iclass 15, count 0 2006.257.17:29:44.86#ibcon#read 4, iclass 15, count 0 2006.257.17:29:44.86#ibcon#about to read 5, iclass 15, count 0 2006.257.17:29:44.86#ibcon#read 5, iclass 15, count 0 2006.257.17:29:44.86#ibcon#about to read 6, iclass 15, count 0 2006.257.17:29:44.86#ibcon#read 6, iclass 15, count 0 2006.257.17:29:44.86#ibcon#end of sib2, iclass 15, count 0 2006.257.17:29:44.86#ibcon#*mode == 0, iclass 15, count 0 2006.257.17:29:44.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.17:29:44.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:29:44.86#ibcon#*before write, iclass 15, count 0 2006.257.17:29:44.86#ibcon#enter sib2, iclass 15, count 0 2006.257.17:29:44.86#ibcon#flushed, iclass 15, count 0 2006.257.17:29:44.86#ibcon#about to write, iclass 15, count 0 2006.257.17:29:44.86#ibcon#wrote, iclass 15, count 0 2006.257.17:29:44.86#ibcon#about to read 3, iclass 15, count 0 2006.257.17:29:44.90#ibcon#read 3, iclass 15, count 0 2006.257.17:29:44.90#ibcon#about to read 4, iclass 15, count 0 2006.257.17:29:44.90#ibcon#read 4, iclass 15, count 0 2006.257.17:29:44.90#ibcon#about to read 5, iclass 15, count 0 2006.257.17:29:44.90#ibcon#read 5, iclass 15, count 0 2006.257.17:29:44.90#ibcon#about to read 6, iclass 15, count 0 2006.257.17:29:44.90#ibcon#read 6, iclass 15, count 0 2006.257.17:29:44.90#ibcon#end of sib2, iclass 15, count 0 2006.257.17:29:44.90#ibcon#*after write, iclass 15, count 0 2006.257.17:29:44.90#ibcon#*before return 0, iclass 15, count 0 2006.257.17:29:44.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:44.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:44.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.17:29:44.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.17:29:44.91$vck44/va=5,4 2006.257.17:29:44.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.17:29:44.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.17:29:44.91#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:44.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:44.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:44.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:44.95#ibcon#enter wrdev, iclass 17, count 2 2006.257.17:29:44.95#ibcon#first serial, iclass 17, count 2 2006.257.17:29:44.95#ibcon#enter sib2, iclass 17, count 2 2006.257.17:29:44.95#ibcon#flushed, iclass 17, count 2 2006.257.17:29:44.95#ibcon#about to write, iclass 17, count 2 2006.257.17:29:44.95#ibcon#wrote, iclass 17, count 2 2006.257.17:29:44.95#ibcon#about to read 3, iclass 17, count 2 2006.257.17:29:44.97#ibcon#read 3, iclass 17, count 2 2006.257.17:29:44.97#ibcon#about to read 4, iclass 17, count 2 2006.257.17:29:44.97#ibcon#read 4, iclass 17, count 2 2006.257.17:29:44.97#ibcon#about to read 5, iclass 17, count 2 2006.257.17:29:44.97#ibcon#read 5, iclass 17, count 2 2006.257.17:29:44.97#ibcon#about to read 6, iclass 17, count 2 2006.257.17:29:44.97#ibcon#read 6, iclass 17, count 2 2006.257.17:29:44.97#ibcon#end of sib2, iclass 17, count 2 2006.257.17:29:44.97#ibcon#*mode == 0, iclass 17, count 2 2006.257.17:29:44.97#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.17:29:44.97#ibcon#[25=AT05-04\r\n] 2006.257.17:29:44.97#ibcon#*before write, iclass 17, count 2 2006.257.17:29:44.97#ibcon#enter sib2, iclass 17, count 2 2006.257.17:29:44.97#ibcon#flushed, iclass 17, count 2 2006.257.17:29:44.97#ibcon#about to write, iclass 17, count 2 2006.257.17:29:44.97#ibcon#wrote, iclass 17, count 2 2006.257.17:29:44.97#ibcon#about to read 3, iclass 17, count 2 2006.257.17:29:45.00#ibcon#read 3, iclass 17, count 2 2006.257.17:29:45.00#ibcon#about to read 4, iclass 17, count 2 2006.257.17:29:45.00#ibcon#read 4, iclass 17, count 2 2006.257.17:29:45.00#ibcon#about to read 5, iclass 17, count 2 2006.257.17:29:45.00#ibcon#read 5, iclass 17, count 2 2006.257.17:29:45.00#ibcon#about to read 6, iclass 17, count 2 2006.257.17:29:45.00#ibcon#read 6, iclass 17, count 2 2006.257.17:29:45.00#ibcon#end of sib2, iclass 17, count 2 2006.257.17:29:45.00#ibcon#*after write, iclass 17, count 2 2006.257.17:29:45.00#ibcon#*before return 0, iclass 17, count 2 2006.257.17:29:45.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:45.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:45.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.17:29:45.00#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:45.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:45.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:45.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:45.12#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:29:45.12#ibcon#first serial, iclass 17, count 0 2006.257.17:29:45.12#ibcon#enter sib2, iclass 17, count 0 2006.257.17:29:45.12#ibcon#flushed, iclass 17, count 0 2006.257.17:29:45.12#ibcon#about to write, iclass 17, count 0 2006.257.17:29:45.12#ibcon#wrote, iclass 17, count 0 2006.257.17:29:45.12#ibcon#about to read 3, iclass 17, count 0 2006.257.17:29:45.14#ibcon#read 3, iclass 17, count 0 2006.257.17:29:45.14#ibcon#about to read 4, iclass 17, count 0 2006.257.17:29:45.14#ibcon#read 4, iclass 17, count 0 2006.257.17:29:45.14#ibcon#about to read 5, iclass 17, count 0 2006.257.17:29:45.14#ibcon#read 5, iclass 17, count 0 2006.257.17:29:45.14#ibcon#about to read 6, iclass 17, count 0 2006.257.17:29:45.14#ibcon#read 6, iclass 17, count 0 2006.257.17:29:45.14#ibcon#end of sib2, iclass 17, count 0 2006.257.17:29:45.14#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:29:45.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:29:45.14#ibcon#[25=USB\r\n] 2006.257.17:29:45.14#ibcon#*before write, iclass 17, count 0 2006.257.17:29:45.14#ibcon#enter sib2, iclass 17, count 0 2006.257.17:29:45.14#ibcon#flushed, iclass 17, count 0 2006.257.17:29:45.14#ibcon#about to write, iclass 17, count 0 2006.257.17:29:45.14#ibcon#wrote, iclass 17, count 0 2006.257.17:29:45.14#ibcon#about to read 3, iclass 17, count 0 2006.257.17:29:45.17#ibcon#read 3, iclass 17, count 0 2006.257.17:29:45.17#ibcon#about to read 4, iclass 17, count 0 2006.257.17:29:45.17#ibcon#read 4, iclass 17, count 0 2006.257.17:29:45.17#ibcon#about to read 5, iclass 17, count 0 2006.257.17:29:45.17#ibcon#read 5, iclass 17, count 0 2006.257.17:29:45.17#ibcon#about to read 6, iclass 17, count 0 2006.257.17:29:45.17#ibcon#read 6, iclass 17, count 0 2006.257.17:29:45.17#ibcon#end of sib2, iclass 17, count 0 2006.257.17:29:45.17#ibcon#*after write, iclass 17, count 0 2006.257.17:29:45.17#ibcon#*before return 0, iclass 17, count 0 2006.257.17:29:45.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:45.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:45.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:29:45.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:29:45.17$vck44/valo=6,814.99 2006.257.17:29:45.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.17:29:45.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.17:29:45.17#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:45.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:45.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:45.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:45.18#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:29:45.18#ibcon#first serial, iclass 19, count 0 2006.257.17:29:45.18#ibcon#enter sib2, iclass 19, count 0 2006.257.17:29:45.18#ibcon#flushed, iclass 19, count 0 2006.257.17:29:45.18#ibcon#about to write, iclass 19, count 0 2006.257.17:29:45.18#ibcon#wrote, iclass 19, count 0 2006.257.17:29:45.18#ibcon#about to read 3, iclass 19, count 0 2006.257.17:29:45.19#ibcon#read 3, iclass 19, count 0 2006.257.17:29:45.19#ibcon#about to read 4, iclass 19, count 0 2006.257.17:29:45.19#ibcon#read 4, iclass 19, count 0 2006.257.17:29:45.19#ibcon#about to read 5, iclass 19, count 0 2006.257.17:29:45.19#ibcon#read 5, iclass 19, count 0 2006.257.17:29:45.19#ibcon#about to read 6, iclass 19, count 0 2006.257.17:29:45.19#ibcon#read 6, iclass 19, count 0 2006.257.17:29:45.19#ibcon#end of sib2, iclass 19, count 0 2006.257.17:29:45.19#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:29:45.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:29:45.19#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:29:45.19#ibcon#*before write, iclass 19, count 0 2006.257.17:29:45.19#ibcon#enter sib2, iclass 19, count 0 2006.257.17:29:45.19#ibcon#flushed, iclass 19, count 0 2006.257.17:29:45.19#ibcon#about to write, iclass 19, count 0 2006.257.17:29:45.19#ibcon#wrote, iclass 19, count 0 2006.257.17:29:45.19#ibcon#about to read 3, iclass 19, count 0 2006.257.17:29:45.23#ibcon#read 3, iclass 19, count 0 2006.257.17:29:45.23#ibcon#about to read 4, iclass 19, count 0 2006.257.17:29:45.23#ibcon#read 4, iclass 19, count 0 2006.257.17:29:45.23#ibcon#about to read 5, iclass 19, count 0 2006.257.17:29:45.23#ibcon#read 5, iclass 19, count 0 2006.257.17:29:45.23#ibcon#about to read 6, iclass 19, count 0 2006.257.17:29:45.23#ibcon#read 6, iclass 19, count 0 2006.257.17:29:45.23#ibcon#end of sib2, iclass 19, count 0 2006.257.17:29:45.23#ibcon#*after write, iclass 19, count 0 2006.257.17:29:45.23#ibcon#*before return 0, iclass 19, count 0 2006.257.17:29:45.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:45.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:45.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:29:45.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:29:45.23$vck44/va=6,4 2006.257.17:29:45.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.17:29:45.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.17:29:45.23#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:45.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:45.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:45.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:45.29#ibcon#enter wrdev, iclass 21, count 2 2006.257.17:29:45.29#ibcon#first serial, iclass 21, count 2 2006.257.17:29:45.29#ibcon#enter sib2, iclass 21, count 2 2006.257.17:29:45.29#ibcon#flushed, iclass 21, count 2 2006.257.17:29:45.29#ibcon#about to write, iclass 21, count 2 2006.257.17:29:45.29#ibcon#wrote, iclass 21, count 2 2006.257.17:29:45.29#ibcon#about to read 3, iclass 21, count 2 2006.257.17:29:45.31#ibcon#read 3, iclass 21, count 2 2006.257.17:29:45.31#ibcon#about to read 4, iclass 21, count 2 2006.257.17:29:45.31#ibcon#read 4, iclass 21, count 2 2006.257.17:29:45.31#ibcon#about to read 5, iclass 21, count 2 2006.257.17:29:45.31#ibcon#read 5, iclass 21, count 2 2006.257.17:29:45.31#ibcon#about to read 6, iclass 21, count 2 2006.257.17:29:45.31#ibcon#read 6, iclass 21, count 2 2006.257.17:29:45.31#ibcon#end of sib2, iclass 21, count 2 2006.257.17:29:45.31#ibcon#*mode == 0, iclass 21, count 2 2006.257.17:29:45.31#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.17:29:45.31#ibcon#[25=AT06-04\r\n] 2006.257.17:29:45.31#ibcon#*before write, iclass 21, count 2 2006.257.17:29:45.31#ibcon#enter sib2, iclass 21, count 2 2006.257.17:29:45.31#ibcon#flushed, iclass 21, count 2 2006.257.17:29:45.31#ibcon#about to write, iclass 21, count 2 2006.257.17:29:45.31#ibcon#wrote, iclass 21, count 2 2006.257.17:29:45.31#ibcon#about to read 3, iclass 21, count 2 2006.257.17:29:45.34#ibcon#read 3, iclass 21, count 2 2006.257.17:29:45.34#ibcon#about to read 4, iclass 21, count 2 2006.257.17:29:45.34#ibcon#read 4, iclass 21, count 2 2006.257.17:29:45.34#ibcon#about to read 5, iclass 21, count 2 2006.257.17:29:45.34#ibcon#read 5, iclass 21, count 2 2006.257.17:29:45.34#ibcon#about to read 6, iclass 21, count 2 2006.257.17:29:45.34#ibcon#read 6, iclass 21, count 2 2006.257.17:29:45.34#ibcon#end of sib2, iclass 21, count 2 2006.257.17:29:45.34#ibcon#*after write, iclass 21, count 2 2006.257.17:29:45.34#ibcon#*before return 0, iclass 21, count 2 2006.257.17:29:45.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:45.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:45.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.17:29:45.34#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:45.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:45.46#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:45.46#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:45.46#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:29:45.46#ibcon#first serial, iclass 21, count 0 2006.257.17:29:45.46#ibcon#enter sib2, iclass 21, count 0 2006.257.17:29:45.46#ibcon#flushed, iclass 21, count 0 2006.257.17:29:45.46#ibcon#about to write, iclass 21, count 0 2006.257.17:29:45.46#ibcon#wrote, iclass 21, count 0 2006.257.17:29:45.46#ibcon#about to read 3, iclass 21, count 0 2006.257.17:29:45.48#ibcon#read 3, iclass 21, count 0 2006.257.17:29:45.48#ibcon#about to read 4, iclass 21, count 0 2006.257.17:29:45.48#ibcon#read 4, iclass 21, count 0 2006.257.17:29:45.48#ibcon#about to read 5, iclass 21, count 0 2006.257.17:29:45.48#ibcon#read 5, iclass 21, count 0 2006.257.17:29:45.48#ibcon#about to read 6, iclass 21, count 0 2006.257.17:29:45.48#ibcon#read 6, iclass 21, count 0 2006.257.17:29:45.48#ibcon#end of sib2, iclass 21, count 0 2006.257.17:29:45.48#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:29:45.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:29:45.48#ibcon#[25=USB\r\n] 2006.257.17:29:45.48#ibcon#*before write, iclass 21, count 0 2006.257.17:29:45.48#ibcon#enter sib2, iclass 21, count 0 2006.257.17:29:45.48#ibcon#flushed, iclass 21, count 0 2006.257.17:29:45.48#ibcon#about to write, iclass 21, count 0 2006.257.17:29:45.48#ibcon#wrote, iclass 21, count 0 2006.257.17:29:45.48#ibcon#about to read 3, iclass 21, count 0 2006.257.17:29:45.51#ibcon#read 3, iclass 21, count 0 2006.257.17:29:45.51#ibcon#about to read 4, iclass 21, count 0 2006.257.17:29:45.51#ibcon#read 4, iclass 21, count 0 2006.257.17:29:45.51#ibcon#about to read 5, iclass 21, count 0 2006.257.17:29:45.51#ibcon#read 5, iclass 21, count 0 2006.257.17:29:45.51#ibcon#about to read 6, iclass 21, count 0 2006.257.17:29:45.51#ibcon#read 6, iclass 21, count 0 2006.257.17:29:45.51#ibcon#end of sib2, iclass 21, count 0 2006.257.17:29:45.51#ibcon#*after write, iclass 21, count 0 2006.257.17:29:45.51#ibcon#*before return 0, iclass 21, count 0 2006.257.17:29:45.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:45.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:45.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:29:45.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:29:45.51$vck44/valo=7,864.99 2006.257.17:29:45.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.17:29:45.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.17:29:45.51#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:45.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:45.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:45.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:45.51#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:29:45.51#ibcon#first serial, iclass 23, count 0 2006.257.17:29:45.51#ibcon#enter sib2, iclass 23, count 0 2006.257.17:29:45.51#ibcon#flushed, iclass 23, count 0 2006.257.17:29:45.51#ibcon#about to write, iclass 23, count 0 2006.257.17:29:45.52#ibcon#wrote, iclass 23, count 0 2006.257.17:29:45.52#ibcon#about to read 3, iclass 23, count 0 2006.257.17:29:45.53#ibcon#read 3, iclass 23, count 0 2006.257.17:29:45.53#ibcon#about to read 4, iclass 23, count 0 2006.257.17:29:45.53#ibcon#read 4, iclass 23, count 0 2006.257.17:29:45.53#ibcon#about to read 5, iclass 23, count 0 2006.257.17:29:45.53#ibcon#read 5, iclass 23, count 0 2006.257.17:29:45.53#ibcon#about to read 6, iclass 23, count 0 2006.257.17:29:45.53#ibcon#read 6, iclass 23, count 0 2006.257.17:29:45.53#ibcon#end of sib2, iclass 23, count 0 2006.257.17:29:45.53#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:29:45.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:29:45.53#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:29:45.53#ibcon#*before write, iclass 23, count 0 2006.257.17:29:45.53#ibcon#enter sib2, iclass 23, count 0 2006.257.17:29:45.53#ibcon#flushed, iclass 23, count 0 2006.257.17:29:45.53#ibcon#about to write, iclass 23, count 0 2006.257.17:29:45.53#ibcon#wrote, iclass 23, count 0 2006.257.17:29:45.53#ibcon#about to read 3, iclass 23, count 0 2006.257.17:29:45.57#ibcon#read 3, iclass 23, count 0 2006.257.17:29:45.57#ibcon#about to read 4, iclass 23, count 0 2006.257.17:29:45.57#ibcon#read 4, iclass 23, count 0 2006.257.17:29:45.57#ibcon#about to read 5, iclass 23, count 0 2006.257.17:29:45.57#ibcon#read 5, iclass 23, count 0 2006.257.17:29:45.57#ibcon#about to read 6, iclass 23, count 0 2006.257.17:29:45.57#ibcon#read 6, iclass 23, count 0 2006.257.17:29:45.57#ibcon#end of sib2, iclass 23, count 0 2006.257.17:29:45.57#ibcon#*after write, iclass 23, count 0 2006.257.17:29:45.57#ibcon#*before return 0, iclass 23, count 0 2006.257.17:29:45.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:45.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:45.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:29:45.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:29:45.57$vck44/va=7,4 2006.257.17:29:45.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.17:29:45.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.17:29:45.57#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:45.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:45.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:45.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:45.63#ibcon#enter wrdev, iclass 25, count 2 2006.257.17:29:45.63#ibcon#first serial, iclass 25, count 2 2006.257.17:29:45.63#ibcon#enter sib2, iclass 25, count 2 2006.257.17:29:45.63#ibcon#flushed, iclass 25, count 2 2006.257.17:29:45.63#ibcon#about to write, iclass 25, count 2 2006.257.17:29:45.63#ibcon#wrote, iclass 25, count 2 2006.257.17:29:45.63#ibcon#about to read 3, iclass 25, count 2 2006.257.17:29:45.65#ibcon#read 3, iclass 25, count 2 2006.257.17:29:45.65#ibcon#about to read 4, iclass 25, count 2 2006.257.17:29:45.65#ibcon#read 4, iclass 25, count 2 2006.257.17:29:45.65#ibcon#about to read 5, iclass 25, count 2 2006.257.17:29:45.65#ibcon#read 5, iclass 25, count 2 2006.257.17:29:45.65#ibcon#about to read 6, iclass 25, count 2 2006.257.17:29:45.65#ibcon#read 6, iclass 25, count 2 2006.257.17:29:45.65#ibcon#end of sib2, iclass 25, count 2 2006.257.17:29:45.65#ibcon#*mode == 0, iclass 25, count 2 2006.257.17:29:45.65#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.17:29:45.65#ibcon#[25=AT07-04\r\n] 2006.257.17:29:45.65#ibcon#*before write, iclass 25, count 2 2006.257.17:29:45.65#ibcon#enter sib2, iclass 25, count 2 2006.257.17:29:45.65#ibcon#flushed, iclass 25, count 2 2006.257.17:29:45.65#ibcon#about to write, iclass 25, count 2 2006.257.17:29:45.65#ibcon#wrote, iclass 25, count 2 2006.257.17:29:45.65#ibcon#about to read 3, iclass 25, count 2 2006.257.17:29:45.68#ibcon#read 3, iclass 25, count 2 2006.257.17:29:45.68#ibcon#about to read 4, iclass 25, count 2 2006.257.17:29:45.68#ibcon#read 4, iclass 25, count 2 2006.257.17:29:45.68#ibcon#about to read 5, iclass 25, count 2 2006.257.17:29:45.68#ibcon#read 5, iclass 25, count 2 2006.257.17:29:45.68#ibcon#about to read 6, iclass 25, count 2 2006.257.17:29:45.68#ibcon#read 6, iclass 25, count 2 2006.257.17:29:45.68#ibcon#end of sib2, iclass 25, count 2 2006.257.17:29:45.68#ibcon#*after write, iclass 25, count 2 2006.257.17:29:45.68#ibcon#*before return 0, iclass 25, count 2 2006.257.17:29:45.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:45.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:45.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.17:29:45.68#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:45.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:45.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:45.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:45.80#ibcon#enter wrdev, iclass 25, count 0 2006.257.17:29:45.80#ibcon#first serial, iclass 25, count 0 2006.257.17:29:45.80#ibcon#enter sib2, iclass 25, count 0 2006.257.17:29:45.80#ibcon#flushed, iclass 25, count 0 2006.257.17:29:45.80#ibcon#about to write, iclass 25, count 0 2006.257.17:29:45.80#ibcon#wrote, iclass 25, count 0 2006.257.17:29:45.80#ibcon#about to read 3, iclass 25, count 0 2006.257.17:29:45.82#ibcon#read 3, iclass 25, count 0 2006.257.17:29:45.82#ibcon#about to read 4, iclass 25, count 0 2006.257.17:29:45.82#ibcon#read 4, iclass 25, count 0 2006.257.17:29:45.82#ibcon#about to read 5, iclass 25, count 0 2006.257.17:29:45.82#ibcon#read 5, iclass 25, count 0 2006.257.17:29:45.82#ibcon#about to read 6, iclass 25, count 0 2006.257.17:29:45.82#ibcon#read 6, iclass 25, count 0 2006.257.17:29:45.82#ibcon#end of sib2, iclass 25, count 0 2006.257.17:29:45.82#ibcon#*mode == 0, iclass 25, count 0 2006.257.17:29:45.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.17:29:45.82#ibcon#[25=USB\r\n] 2006.257.17:29:45.82#ibcon#*before write, iclass 25, count 0 2006.257.17:29:45.82#ibcon#enter sib2, iclass 25, count 0 2006.257.17:29:45.82#ibcon#flushed, iclass 25, count 0 2006.257.17:29:45.82#ibcon#about to write, iclass 25, count 0 2006.257.17:29:45.82#ibcon#wrote, iclass 25, count 0 2006.257.17:29:45.82#ibcon#about to read 3, iclass 25, count 0 2006.257.17:29:45.85#ibcon#read 3, iclass 25, count 0 2006.257.17:29:45.85#ibcon#about to read 4, iclass 25, count 0 2006.257.17:29:45.85#ibcon#read 4, iclass 25, count 0 2006.257.17:29:45.85#ibcon#about to read 5, iclass 25, count 0 2006.257.17:29:45.85#ibcon#read 5, iclass 25, count 0 2006.257.17:29:45.85#ibcon#about to read 6, iclass 25, count 0 2006.257.17:29:45.85#ibcon#read 6, iclass 25, count 0 2006.257.17:29:45.85#ibcon#end of sib2, iclass 25, count 0 2006.257.17:29:45.85#ibcon#*after write, iclass 25, count 0 2006.257.17:29:45.85#ibcon#*before return 0, iclass 25, count 0 2006.257.17:29:45.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:45.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:45.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.17:29:45.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.17:29:45.85$vck44/valo=8,884.99 2006.257.17:29:45.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.17:29:45.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.17:29:45.85#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:45.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:45.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:45.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:45.85#ibcon#enter wrdev, iclass 27, count 0 2006.257.17:29:45.85#ibcon#first serial, iclass 27, count 0 2006.257.17:29:45.85#ibcon#enter sib2, iclass 27, count 0 2006.257.17:29:45.85#ibcon#flushed, iclass 27, count 0 2006.257.17:29:45.85#ibcon#about to write, iclass 27, count 0 2006.257.17:29:45.86#ibcon#wrote, iclass 27, count 0 2006.257.17:29:45.86#ibcon#about to read 3, iclass 27, count 0 2006.257.17:29:45.87#ibcon#read 3, iclass 27, count 0 2006.257.17:29:45.87#ibcon#about to read 4, iclass 27, count 0 2006.257.17:29:45.87#ibcon#read 4, iclass 27, count 0 2006.257.17:29:45.87#ibcon#about to read 5, iclass 27, count 0 2006.257.17:29:45.87#ibcon#read 5, iclass 27, count 0 2006.257.17:29:45.87#ibcon#about to read 6, iclass 27, count 0 2006.257.17:29:45.87#ibcon#read 6, iclass 27, count 0 2006.257.17:29:45.87#ibcon#end of sib2, iclass 27, count 0 2006.257.17:29:45.87#ibcon#*mode == 0, iclass 27, count 0 2006.257.17:29:45.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.17:29:45.87#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:29:45.87#ibcon#*before write, iclass 27, count 0 2006.257.17:29:45.87#ibcon#enter sib2, iclass 27, count 0 2006.257.17:29:45.87#ibcon#flushed, iclass 27, count 0 2006.257.17:29:45.87#ibcon#about to write, iclass 27, count 0 2006.257.17:29:45.87#ibcon#wrote, iclass 27, count 0 2006.257.17:29:45.87#ibcon#about to read 3, iclass 27, count 0 2006.257.17:29:45.91#ibcon#read 3, iclass 27, count 0 2006.257.17:29:45.91#ibcon#about to read 4, iclass 27, count 0 2006.257.17:29:45.91#ibcon#read 4, iclass 27, count 0 2006.257.17:29:45.91#ibcon#about to read 5, iclass 27, count 0 2006.257.17:29:45.91#ibcon#read 5, iclass 27, count 0 2006.257.17:29:45.91#ibcon#about to read 6, iclass 27, count 0 2006.257.17:29:45.91#ibcon#read 6, iclass 27, count 0 2006.257.17:29:45.91#ibcon#end of sib2, iclass 27, count 0 2006.257.17:29:45.91#ibcon#*after write, iclass 27, count 0 2006.257.17:29:45.91#ibcon#*before return 0, iclass 27, count 0 2006.257.17:29:45.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:45.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:45.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.17:29:45.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.17:29:45.91$vck44/va=8,4 2006.257.17:29:45.91#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.17:29:45.91#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.17:29:45.91#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:45.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:29:45.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:29:45.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:29:45.97#ibcon#enter wrdev, iclass 29, count 2 2006.257.17:29:45.97#ibcon#first serial, iclass 29, count 2 2006.257.17:29:45.97#ibcon#enter sib2, iclass 29, count 2 2006.257.17:29:45.97#ibcon#flushed, iclass 29, count 2 2006.257.17:29:45.97#ibcon#about to write, iclass 29, count 2 2006.257.17:29:45.97#ibcon#wrote, iclass 29, count 2 2006.257.17:29:45.97#ibcon#about to read 3, iclass 29, count 2 2006.257.17:29:45.99#ibcon#read 3, iclass 29, count 2 2006.257.17:29:45.99#ibcon#about to read 4, iclass 29, count 2 2006.257.17:29:45.99#ibcon#read 4, iclass 29, count 2 2006.257.17:29:45.99#ibcon#about to read 5, iclass 29, count 2 2006.257.17:29:45.99#ibcon#read 5, iclass 29, count 2 2006.257.17:29:45.99#ibcon#about to read 6, iclass 29, count 2 2006.257.17:29:45.99#ibcon#read 6, iclass 29, count 2 2006.257.17:29:45.99#ibcon#end of sib2, iclass 29, count 2 2006.257.17:29:45.99#ibcon#*mode == 0, iclass 29, count 2 2006.257.17:29:45.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.17:29:45.99#ibcon#[25=AT08-04\r\n] 2006.257.17:29:45.99#ibcon#*before write, iclass 29, count 2 2006.257.17:29:45.99#ibcon#enter sib2, iclass 29, count 2 2006.257.17:29:45.99#ibcon#flushed, iclass 29, count 2 2006.257.17:29:45.99#ibcon#about to write, iclass 29, count 2 2006.257.17:29:45.99#ibcon#wrote, iclass 29, count 2 2006.257.17:29:45.99#ibcon#about to read 3, iclass 29, count 2 2006.257.17:29:46.02#ibcon#read 3, iclass 29, count 2 2006.257.17:29:46.02#ibcon#about to read 4, iclass 29, count 2 2006.257.17:29:46.02#ibcon#read 4, iclass 29, count 2 2006.257.17:29:46.02#ibcon#about to read 5, iclass 29, count 2 2006.257.17:29:46.02#ibcon#read 5, iclass 29, count 2 2006.257.17:29:46.02#ibcon#about to read 6, iclass 29, count 2 2006.257.17:29:46.02#ibcon#read 6, iclass 29, count 2 2006.257.17:29:46.02#ibcon#end of sib2, iclass 29, count 2 2006.257.17:29:46.02#ibcon#*after write, iclass 29, count 2 2006.257.17:29:46.02#ibcon#*before return 0, iclass 29, count 2 2006.257.17:29:46.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:29:46.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:29:46.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.17:29:46.02#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:46.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:29:46.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:29:46.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:29:46.14#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:29:46.14#ibcon#first serial, iclass 29, count 0 2006.257.17:29:46.14#ibcon#enter sib2, iclass 29, count 0 2006.257.17:29:46.14#ibcon#flushed, iclass 29, count 0 2006.257.17:29:46.14#ibcon#about to write, iclass 29, count 0 2006.257.17:29:46.14#ibcon#wrote, iclass 29, count 0 2006.257.17:29:46.15#ibcon#about to read 3, iclass 29, count 0 2006.257.17:29:46.16#ibcon#read 3, iclass 29, count 0 2006.257.17:29:46.16#ibcon#about to read 4, iclass 29, count 0 2006.257.17:29:46.16#ibcon#read 4, iclass 29, count 0 2006.257.17:29:46.16#ibcon#about to read 5, iclass 29, count 0 2006.257.17:29:46.16#ibcon#read 5, iclass 29, count 0 2006.257.17:29:46.16#ibcon#about to read 6, iclass 29, count 0 2006.257.17:29:46.16#ibcon#read 6, iclass 29, count 0 2006.257.17:29:46.16#ibcon#end of sib2, iclass 29, count 0 2006.257.17:29:46.16#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:29:46.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:29:46.16#ibcon#[25=USB\r\n] 2006.257.17:29:46.16#ibcon#*before write, iclass 29, count 0 2006.257.17:29:46.16#ibcon#enter sib2, iclass 29, count 0 2006.257.17:29:46.16#ibcon#flushed, iclass 29, count 0 2006.257.17:29:46.16#ibcon#about to write, iclass 29, count 0 2006.257.17:29:46.16#ibcon#wrote, iclass 29, count 0 2006.257.17:29:46.16#ibcon#about to read 3, iclass 29, count 0 2006.257.17:29:46.19#ibcon#read 3, iclass 29, count 0 2006.257.17:29:46.19#ibcon#about to read 4, iclass 29, count 0 2006.257.17:29:46.19#ibcon#read 4, iclass 29, count 0 2006.257.17:29:46.19#ibcon#about to read 5, iclass 29, count 0 2006.257.17:29:46.19#ibcon#read 5, iclass 29, count 0 2006.257.17:29:46.19#ibcon#about to read 6, iclass 29, count 0 2006.257.17:29:46.19#ibcon#read 6, iclass 29, count 0 2006.257.17:29:46.19#ibcon#end of sib2, iclass 29, count 0 2006.257.17:29:46.19#ibcon#*after write, iclass 29, count 0 2006.257.17:29:46.19#ibcon#*before return 0, iclass 29, count 0 2006.257.17:29:46.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:29:46.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:29:46.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:29:46.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:29:46.19$vck44/vblo=1,629.99 2006.257.17:29:46.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.17:29:46.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.17:29:46.19#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:46.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:29:46.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:29:46.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:29:46.19#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:29:46.19#ibcon#first serial, iclass 31, count 0 2006.257.17:29:46.19#ibcon#enter sib2, iclass 31, count 0 2006.257.17:29:46.19#ibcon#flushed, iclass 31, count 0 2006.257.17:29:46.19#ibcon#about to write, iclass 31, count 0 2006.257.17:29:46.20#ibcon#wrote, iclass 31, count 0 2006.257.17:29:46.20#ibcon#about to read 3, iclass 31, count 0 2006.257.17:29:46.21#ibcon#read 3, iclass 31, count 0 2006.257.17:29:46.21#ibcon#about to read 4, iclass 31, count 0 2006.257.17:29:46.21#ibcon#read 4, iclass 31, count 0 2006.257.17:29:46.21#ibcon#about to read 5, iclass 31, count 0 2006.257.17:29:46.21#ibcon#read 5, iclass 31, count 0 2006.257.17:29:46.21#ibcon#about to read 6, iclass 31, count 0 2006.257.17:29:46.21#ibcon#read 6, iclass 31, count 0 2006.257.17:29:46.21#ibcon#end of sib2, iclass 31, count 0 2006.257.17:29:46.21#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:29:46.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:29:46.21#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:29:46.21#ibcon#*before write, iclass 31, count 0 2006.257.17:29:46.21#ibcon#enter sib2, iclass 31, count 0 2006.257.17:29:46.21#ibcon#flushed, iclass 31, count 0 2006.257.17:29:46.21#ibcon#about to write, iclass 31, count 0 2006.257.17:29:46.21#ibcon#wrote, iclass 31, count 0 2006.257.17:29:46.21#ibcon#about to read 3, iclass 31, count 0 2006.257.17:29:46.25#ibcon#read 3, iclass 31, count 0 2006.257.17:29:46.25#ibcon#about to read 4, iclass 31, count 0 2006.257.17:29:46.25#ibcon#read 4, iclass 31, count 0 2006.257.17:29:46.25#ibcon#about to read 5, iclass 31, count 0 2006.257.17:29:46.25#ibcon#read 5, iclass 31, count 0 2006.257.17:29:46.25#ibcon#about to read 6, iclass 31, count 0 2006.257.17:29:46.25#ibcon#read 6, iclass 31, count 0 2006.257.17:29:46.25#ibcon#end of sib2, iclass 31, count 0 2006.257.17:29:46.25#ibcon#*after write, iclass 31, count 0 2006.257.17:29:46.25#ibcon#*before return 0, iclass 31, count 0 2006.257.17:29:46.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:29:46.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:29:46.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:29:46.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:29:46.25$vck44/vb=1,4 2006.257.17:29:46.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.17:29:46.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.17:29:46.25#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:46.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:29:46.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:29:46.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:29:46.25#ibcon#enter wrdev, iclass 33, count 2 2006.257.17:29:46.25#ibcon#first serial, iclass 33, count 2 2006.257.17:29:46.25#ibcon#enter sib2, iclass 33, count 2 2006.257.17:29:46.25#ibcon#flushed, iclass 33, count 2 2006.257.17:29:46.25#ibcon#about to write, iclass 33, count 2 2006.257.17:29:46.25#ibcon#wrote, iclass 33, count 2 2006.257.17:29:46.25#ibcon#about to read 3, iclass 33, count 2 2006.257.17:29:46.27#ibcon#read 3, iclass 33, count 2 2006.257.17:29:46.27#ibcon#about to read 4, iclass 33, count 2 2006.257.17:29:46.27#ibcon#read 4, iclass 33, count 2 2006.257.17:29:46.27#ibcon#about to read 5, iclass 33, count 2 2006.257.17:29:46.27#ibcon#read 5, iclass 33, count 2 2006.257.17:29:46.27#ibcon#about to read 6, iclass 33, count 2 2006.257.17:29:46.27#ibcon#read 6, iclass 33, count 2 2006.257.17:29:46.27#ibcon#end of sib2, iclass 33, count 2 2006.257.17:29:46.27#ibcon#*mode == 0, iclass 33, count 2 2006.257.17:29:46.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.17:29:46.27#ibcon#[27=AT01-04\r\n] 2006.257.17:29:46.27#ibcon#*before write, iclass 33, count 2 2006.257.17:29:46.27#ibcon#enter sib2, iclass 33, count 2 2006.257.17:29:46.27#ibcon#flushed, iclass 33, count 2 2006.257.17:29:46.27#ibcon#about to write, iclass 33, count 2 2006.257.17:29:46.27#ibcon#wrote, iclass 33, count 2 2006.257.17:29:46.27#ibcon#about to read 3, iclass 33, count 2 2006.257.17:29:46.30#ibcon#read 3, iclass 33, count 2 2006.257.17:29:46.30#ibcon#about to read 4, iclass 33, count 2 2006.257.17:29:46.30#ibcon#read 4, iclass 33, count 2 2006.257.17:29:46.30#ibcon#about to read 5, iclass 33, count 2 2006.257.17:29:46.30#ibcon#read 5, iclass 33, count 2 2006.257.17:29:46.30#ibcon#about to read 6, iclass 33, count 2 2006.257.17:29:46.30#ibcon#read 6, iclass 33, count 2 2006.257.17:29:46.30#ibcon#end of sib2, iclass 33, count 2 2006.257.17:29:46.30#ibcon#*after write, iclass 33, count 2 2006.257.17:29:46.30#ibcon#*before return 0, iclass 33, count 2 2006.257.17:29:46.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:29:46.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:29:46.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.17:29:46.30#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:46.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:29:46.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:29:46.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:29:46.42#ibcon#enter wrdev, iclass 33, count 0 2006.257.17:29:46.42#ibcon#first serial, iclass 33, count 0 2006.257.17:29:46.42#ibcon#enter sib2, iclass 33, count 0 2006.257.17:29:46.42#ibcon#flushed, iclass 33, count 0 2006.257.17:29:46.42#ibcon#about to write, iclass 33, count 0 2006.257.17:29:46.42#ibcon#wrote, iclass 33, count 0 2006.257.17:29:46.42#ibcon#about to read 3, iclass 33, count 0 2006.257.17:29:46.44#ibcon#read 3, iclass 33, count 0 2006.257.17:29:46.44#ibcon#about to read 4, iclass 33, count 0 2006.257.17:29:46.44#ibcon#read 4, iclass 33, count 0 2006.257.17:29:46.44#ibcon#about to read 5, iclass 33, count 0 2006.257.17:29:46.44#ibcon#read 5, iclass 33, count 0 2006.257.17:29:46.44#ibcon#about to read 6, iclass 33, count 0 2006.257.17:29:46.44#ibcon#read 6, iclass 33, count 0 2006.257.17:29:46.44#ibcon#end of sib2, iclass 33, count 0 2006.257.17:29:46.44#ibcon#*mode == 0, iclass 33, count 0 2006.257.17:29:46.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.17:29:46.44#ibcon#[27=USB\r\n] 2006.257.17:29:46.44#ibcon#*before write, iclass 33, count 0 2006.257.17:29:46.44#ibcon#enter sib2, iclass 33, count 0 2006.257.17:29:46.44#ibcon#flushed, iclass 33, count 0 2006.257.17:29:46.44#ibcon#about to write, iclass 33, count 0 2006.257.17:29:46.44#ibcon#wrote, iclass 33, count 0 2006.257.17:29:46.44#ibcon#about to read 3, iclass 33, count 0 2006.257.17:29:46.47#ibcon#read 3, iclass 33, count 0 2006.257.17:29:46.47#ibcon#about to read 4, iclass 33, count 0 2006.257.17:29:46.47#ibcon#read 4, iclass 33, count 0 2006.257.17:29:46.47#ibcon#about to read 5, iclass 33, count 0 2006.257.17:29:46.47#ibcon#read 5, iclass 33, count 0 2006.257.17:29:46.47#ibcon#about to read 6, iclass 33, count 0 2006.257.17:29:46.47#ibcon#read 6, iclass 33, count 0 2006.257.17:29:46.47#ibcon#end of sib2, iclass 33, count 0 2006.257.17:29:46.47#ibcon#*after write, iclass 33, count 0 2006.257.17:29:46.47#ibcon#*before return 0, iclass 33, count 0 2006.257.17:29:46.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:29:46.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:29:46.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.17:29:46.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.17:29:46.47$vck44/vblo=2,634.99 2006.257.17:29:46.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.17:29:46.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.17:29:46.47#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:46.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:46.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:46.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:46.47#ibcon#enter wrdev, iclass 35, count 0 2006.257.17:29:46.47#ibcon#first serial, iclass 35, count 0 2006.257.17:29:46.47#ibcon#enter sib2, iclass 35, count 0 2006.257.17:29:46.47#ibcon#flushed, iclass 35, count 0 2006.257.17:29:46.47#ibcon#about to write, iclass 35, count 0 2006.257.17:29:46.48#ibcon#wrote, iclass 35, count 0 2006.257.17:29:46.48#ibcon#about to read 3, iclass 35, count 0 2006.257.17:29:46.49#ibcon#read 3, iclass 35, count 0 2006.257.17:29:46.49#ibcon#about to read 4, iclass 35, count 0 2006.257.17:29:46.49#ibcon#read 4, iclass 35, count 0 2006.257.17:29:46.49#ibcon#about to read 5, iclass 35, count 0 2006.257.17:29:46.49#ibcon#read 5, iclass 35, count 0 2006.257.17:29:46.49#ibcon#about to read 6, iclass 35, count 0 2006.257.17:29:46.49#ibcon#read 6, iclass 35, count 0 2006.257.17:29:46.49#ibcon#end of sib2, iclass 35, count 0 2006.257.17:29:46.49#ibcon#*mode == 0, iclass 35, count 0 2006.257.17:29:46.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.17:29:46.49#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:29:46.49#ibcon#*before write, iclass 35, count 0 2006.257.17:29:46.49#ibcon#enter sib2, iclass 35, count 0 2006.257.17:29:46.49#ibcon#flushed, iclass 35, count 0 2006.257.17:29:46.49#ibcon#about to write, iclass 35, count 0 2006.257.17:29:46.49#ibcon#wrote, iclass 35, count 0 2006.257.17:29:46.49#ibcon#about to read 3, iclass 35, count 0 2006.257.17:29:46.53#ibcon#read 3, iclass 35, count 0 2006.257.17:29:46.53#ibcon#about to read 4, iclass 35, count 0 2006.257.17:29:46.53#ibcon#read 4, iclass 35, count 0 2006.257.17:29:46.53#ibcon#about to read 5, iclass 35, count 0 2006.257.17:29:46.53#ibcon#read 5, iclass 35, count 0 2006.257.17:29:46.53#ibcon#about to read 6, iclass 35, count 0 2006.257.17:29:46.53#ibcon#read 6, iclass 35, count 0 2006.257.17:29:46.53#ibcon#end of sib2, iclass 35, count 0 2006.257.17:29:46.53#ibcon#*after write, iclass 35, count 0 2006.257.17:29:46.53#ibcon#*before return 0, iclass 35, count 0 2006.257.17:29:46.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:46.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:29:46.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.17:29:46.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.17:29:46.53$vck44/vb=2,5 2006.257.17:29:46.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.17:29:46.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.17:29:46.53#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:46.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:46.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:46.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:46.59#ibcon#enter wrdev, iclass 37, count 2 2006.257.17:29:46.59#ibcon#first serial, iclass 37, count 2 2006.257.17:29:46.59#ibcon#enter sib2, iclass 37, count 2 2006.257.17:29:46.59#ibcon#flushed, iclass 37, count 2 2006.257.17:29:46.59#ibcon#about to write, iclass 37, count 2 2006.257.17:29:46.59#ibcon#wrote, iclass 37, count 2 2006.257.17:29:46.59#ibcon#about to read 3, iclass 37, count 2 2006.257.17:29:46.61#ibcon#read 3, iclass 37, count 2 2006.257.17:29:46.61#ibcon#about to read 4, iclass 37, count 2 2006.257.17:29:46.61#ibcon#read 4, iclass 37, count 2 2006.257.17:29:46.61#ibcon#about to read 5, iclass 37, count 2 2006.257.17:29:46.61#ibcon#read 5, iclass 37, count 2 2006.257.17:29:46.61#ibcon#about to read 6, iclass 37, count 2 2006.257.17:29:46.61#ibcon#read 6, iclass 37, count 2 2006.257.17:29:46.61#ibcon#end of sib2, iclass 37, count 2 2006.257.17:29:46.61#ibcon#*mode == 0, iclass 37, count 2 2006.257.17:29:46.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.17:29:46.61#ibcon#[27=AT02-05\r\n] 2006.257.17:29:46.61#ibcon#*before write, iclass 37, count 2 2006.257.17:29:46.61#ibcon#enter sib2, iclass 37, count 2 2006.257.17:29:46.61#ibcon#flushed, iclass 37, count 2 2006.257.17:29:46.61#ibcon#about to write, iclass 37, count 2 2006.257.17:29:46.61#ibcon#wrote, iclass 37, count 2 2006.257.17:29:46.61#ibcon#about to read 3, iclass 37, count 2 2006.257.17:29:46.64#ibcon#read 3, iclass 37, count 2 2006.257.17:29:46.64#ibcon#about to read 4, iclass 37, count 2 2006.257.17:29:46.64#ibcon#read 4, iclass 37, count 2 2006.257.17:29:46.64#ibcon#about to read 5, iclass 37, count 2 2006.257.17:29:46.64#ibcon#read 5, iclass 37, count 2 2006.257.17:29:46.64#ibcon#about to read 6, iclass 37, count 2 2006.257.17:29:46.64#ibcon#read 6, iclass 37, count 2 2006.257.17:29:46.64#ibcon#end of sib2, iclass 37, count 2 2006.257.17:29:46.64#ibcon#*after write, iclass 37, count 2 2006.257.17:29:46.64#ibcon#*before return 0, iclass 37, count 2 2006.257.17:29:46.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:46.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:29:46.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.17:29:46.64#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:46.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:46.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:46.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:46.76#ibcon#enter wrdev, iclass 37, count 0 2006.257.17:29:46.76#ibcon#first serial, iclass 37, count 0 2006.257.17:29:46.76#ibcon#enter sib2, iclass 37, count 0 2006.257.17:29:46.76#ibcon#flushed, iclass 37, count 0 2006.257.17:29:46.76#ibcon#about to write, iclass 37, count 0 2006.257.17:29:46.76#ibcon#wrote, iclass 37, count 0 2006.257.17:29:46.76#ibcon#about to read 3, iclass 37, count 0 2006.257.17:29:46.78#ibcon#read 3, iclass 37, count 0 2006.257.17:29:46.78#ibcon#about to read 4, iclass 37, count 0 2006.257.17:29:46.78#ibcon#read 4, iclass 37, count 0 2006.257.17:29:46.78#ibcon#about to read 5, iclass 37, count 0 2006.257.17:29:46.78#ibcon#read 5, iclass 37, count 0 2006.257.17:29:46.78#ibcon#about to read 6, iclass 37, count 0 2006.257.17:29:46.78#ibcon#read 6, iclass 37, count 0 2006.257.17:29:46.78#ibcon#end of sib2, iclass 37, count 0 2006.257.17:29:46.78#ibcon#*mode == 0, iclass 37, count 0 2006.257.17:29:46.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.17:29:46.78#ibcon#[27=USB\r\n] 2006.257.17:29:46.78#ibcon#*before write, iclass 37, count 0 2006.257.17:29:46.78#ibcon#enter sib2, iclass 37, count 0 2006.257.17:29:46.78#ibcon#flushed, iclass 37, count 0 2006.257.17:29:46.78#ibcon#about to write, iclass 37, count 0 2006.257.17:29:46.78#ibcon#wrote, iclass 37, count 0 2006.257.17:29:46.78#ibcon#about to read 3, iclass 37, count 0 2006.257.17:29:46.81#ibcon#read 3, iclass 37, count 0 2006.257.17:29:46.81#ibcon#about to read 4, iclass 37, count 0 2006.257.17:29:46.81#ibcon#read 4, iclass 37, count 0 2006.257.17:29:46.81#ibcon#about to read 5, iclass 37, count 0 2006.257.17:29:46.81#ibcon#read 5, iclass 37, count 0 2006.257.17:29:46.81#ibcon#about to read 6, iclass 37, count 0 2006.257.17:29:46.81#ibcon#read 6, iclass 37, count 0 2006.257.17:29:46.81#ibcon#end of sib2, iclass 37, count 0 2006.257.17:29:46.81#ibcon#*after write, iclass 37, count 0 2006.257.17:29:46.81#ibcon#*before return 0, iclass 37, count 0 2006.257.17:29:46.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:46.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:29:46.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.17:29:46.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.17:29:46.81$vck44/vblo=3,649.99 2006.257.17:29:46.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.17:29:46.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.17:29:46.81#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:46.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:46.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:46.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:46.81#ibcon#enter wrdev, iclass 39, count 0 2006.257.17:29:46.81#ibcon#first serial, iclass 39, count 0 2006.257.17:29:46.81#ibcon#enter sib2, iclass 39, count 0 2006.257.17:29:46.81#ibcon#flushed, iclass 39, count 0 2006.257.17:29:46.81#ibcon#about to write, iclass 39, count 0 2006.257.17:29:46.82#ibcon#wrote, iclass 39, count 0 2006.257.17:29:46.82#ibcon#about to read 3, iclass 39, count 0 2006.257.17:29:46.83#ibcon#read 3, iclass 39, count 0 2006.257.17:29:46.83#ibcon#about to read 4, iclass 39, count 0 2006.257.17:29:46.83#ibcon#read 4, iclass 39, count 0 2006.257.17:29:46.83#ibcon#about to read 5, iclass 39, count 0 2006.257.17:29:46.83#ibcon#read 5, iclass 39, count 0 2006.257.17:29:46.83#ibcon#about to read 6, iclass 39, count 0 2006.257.17:29:46.83#ibcon#read 6, iclass 39, count 0 2006.257.17:29:46.83#ibcon#end of sib2, iclass 39, count 0 2006.257.17:29:46.83#ibcon#*mode == 0, iclass 39, count 0 2006.257.17:29:46.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.17:29:46.83#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:29:46.83#ibcon#*before write, iclass 39, count 0 2006.257.17:29:46.83#ibcon#enter sib2, iclass 39, count 0 2006.257.17:29:46.83#ibcon#flushed, iclass 39, count 0 2006.257.17:29:46.83#ibcon#about to write, iclass 39, count 0 2006.257.17:29:46.83#ibcon#wrote, iclass 39, count 0 2006.257.17:29:46.83#ibcon#about to read 3, iclass 39, count 0 2006.257.17:29:46.87#ibcon#read 3, iclass 39, count 0 2006.257.17:29:46.87#ibcon#about to read 4, iclass 39, count 0 2006.257.17:29:46.87#ibcon#read 4, iclass 39, count 0 2006.257.17:29:46.87#ibcon#about to read 5, iclass 39, count 0 2006.257.17:29:46.87#ibcon#read 5, iclass 39, count 0 2006.257.17:29:46.87#ibcon#about to read 6, iclass 39, count 0 2006.257.17:29:46.87#ibcon#read 6, iclass 39, count 0 2006.257.17:29:46.87#ibcon#end of sib2, iclass 39, count 0 2006.257.17:29:46.87#ibcon#*after write, iclass 39, count 0 2006.257.17:29:46.87#ibcon#*before return 0, iclass 39, count 0 2006.257.17:29:46.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:46.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:29:46.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.17:29:46.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.17:29:46.87$vck44/vb=3,4 2006.257.17:29:46.87#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.17:29:46.87#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.17:29:46.87#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:46.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:46.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:46.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:46.93#ibcon#enter wrdev, iclass 3, count 2 2006.257.17:29:46.93#ibcon#first serial, iclass 3, count 2 2006.257.17:29:46.93#ibcon#enter sib2, iclass 3, count 2 2006.257.17:29:46.93#ibcon#flushed, iclass 3, count 2 2006.257.17:29:46.93#ibcon#about to write, iclass 3, count 2 2006.257.17:29:46.93#ibcon#wrote, iclass 3, count 2 2006.257.17:29:46.93#ibcon#about to read 3, iclass 3, count 2 2006.257.17:29:46.95#ibcon#read 3, iclass 3, count 2 2006.257.17:29:46.95#ibcon#about to read 4, iclass 3, count 2 2006.257.17:29:46.95#ibcon#read 4, iclass 3, count 2 2006.257.17:29:46.95#ibcon#about to read 5, iclass 3, count 2 2006.257.17:29:46.95#ibcon#read 5, iclass 3, count 2 2006.257.17:29:46.95#ibcon#about to read 6, iclass 3, count 2 2006.257.17:29:46.95#ibcon#read 6, iclass 3, count 2 2006.257.17:29:46.95#ibcon#end of sib2, iclass 3, count 2 2006.257.17:29:46.95#ibcon#*mode == 0, iclass 3, count 2 2006.257.17:29:46.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.17:29:46.95#ibcon#[27=AT03-04\r\n] 2006.257.17:29:46.95#ibcon#*before write, iclass 3, count 2 2006.257.17:29:46.95#ibcon#enter sib2, iclass 3, count 2 2006.257.17:29:46.95#ibcon#flushed, iclass 3, count 2 2006.257.17:29:46.95#ibcon#about to write, iclass 3, count 2 2006.257.17:29:46.95#ibcon#wrote, iclass 3, count 2 2006.257.17:29:46.95#ibcon#about to read 3, iclass 3, count 2 2006.257.17:29:46.98#ibcon#read 3, iclass 3, count 2 2006.257.17:29:46.98#ibcon#about to read 4, iclass 3, count 2 2006.257.17:29:46.98#ibcon#read 4, iclass 3, count 2 2006.257.17:29:46.98#ibcon#about to read 5, iclass 3, count 2 2006.257.17:29:46.98#ibcon#read 5, iclass 3, count 2 2006.257.17:29:46.98#ibcon#about to read 6, iclass 3, count 2 2006.257.17:29:46.98#ibcon#read 6, iclass 3, count 2 2006.257.17:29:46.98#ibcon#end of sib2, iclass 3, count 2 2006.257.17:29:46.98#ibcon#*after write, iclass 3, count 2 2006.257.17:29:46.98#ibcon#*before return 0, iclass 3, count 2 2006.257.17:29:46.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:46.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:29:46.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.17:29:46.98#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:46.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:47.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:47.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:47.10#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:29:47.10#ibcon#first serial, iclass 3, count 0 2006.257.17:29:47.10#ibcon#enter sib2, iclass 3, count 0 2006.257.17:29:47.10#ibcon#flushed, iclass 3, count 0 2006.257.17:29:47.10#ibcon#about to write, iclass 3, count 0 2006.257.17:29:47.10#ibcon#wrote, iclass 3, count 0 2006.257.17:29:47.10#ibcon#about to read 3, iclass 3, count 0 2006.257.17:29:47.12#ibcon#read 3, iclass 3, count 0 2006.257.17:29:47.12#ibcon#about to read 4, iclass 3, count 0 2006.257.17:29:47.12#ibcon#read 4, iclass 3, count 0 2006.257.17:29:47.12#ibcon#about to read 5, iclass 3, count 0 2006.257.17:29:47.12#ibcon#read 5, iclass 3, count 0 2006.257.17:29:47.12#ibcon#about to read 6, iclass 3, count 0 2006.257.17:29:47.12#ibcon#read 6, iclass 3, count 0 2006.257.17:29:47.12#ibcon#end of sib2, iclass 3, count 0 2006.257.17:29:47.12#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:29:47.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:29:47.12#ibcon#[27=USB\r\n] 2006.257.17:29:47.12#ibcon#*before write, iclass 3, count 0 2006.257.17:29:47.12#ibcon#enter sib2, iclass 3, count 0 2006.257.17:29:47.12#ibcon#flushed, iclass 3, count 0 2006.257.17:29:47.12#ibcon#about to write, iclass 3, count 0 2006.257.17:29:47.12#ibcon#wrote, iclass 3, count 0 2006.257.17:29:47.12#ibcon#about to read 3, iclass 3, count 0 2006.257.17:29:47.15#ibcon#read 3, iclass 3, count 0 2006.257.17:29:47.15#ibcon#about to read 4, iclass 3, count 0 2006.257.17:29:47.15#ibcon#read 4, iclass 3, count 0 2006.257.17:29:47.15#ibcon#about to read 5, iclass 3, count 0 2006.257.17:29:47.15#ibcon#read 5, iclass 3, count 0 2006.257.17:29:47.15#ibcon#about to read 6, iclass 3, count 0 2006.257.17:29:47.15#ibcon#read 6, iclass 3, count 0 2006.257.17:29:47.15#ibcon#end of sib2, iclass 3, count 0 2006.257.17:29:47.15#ibcon#*after write, iclass 3, count 0 2006.257.17:29:47.15#ibcon#*before return 0, iclass 3, count 0 2006.257.17:29:47.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:47.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:29:47.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:29:47.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:29:47.15$vck44/vblo=4,679.99 2006.257.17:29:47.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.17:29:47.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.17:29:47.15#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:47.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:47.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:47.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:47.15#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:29:47.15#ibcon#first serial, iclass 5, count 0 2006.257.17:29:47.15#ibcon#enter sib2, iclass 5, count 0 2006.257.17:29:47.15#ibcon#flushed, iclass 5, count 0 2006.257.17:29:47.15#ibcon#about to write, iclass 5, count 0 2006.257.17:29:47.15#ibcon#wrote, iclass 5, count 0 2006.257.17:29:47.15#ibcon#about to read 3, iclass 5, count 0 2006.257.17:29:47.17#ibcon#read 3, iclass 5, count 0 2006.257.17:29:47.17#ibcon#about to read 4, iclass 5, count 0 2006.257.17:29:47.17#ibcon#read 4, iclass 5, count 0 2006.257.17:29:47.17#ibcon#about to read 5, iclass 5, count 0 2006.257.17:29:47.17#ibcon#read 5, iclass 5, count 0 2006.257.17:29:47.17#ibcon#about to read 6, iclass 5, count 0 2006.257.17:29:47.17#ibcon#read 6, iclass 5, count 0 2006.257.17:29:47.17#ibcon#end of sib2, iclass 5, count 0 2006.257.17:29:47.17#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:29:47.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:29:47.17#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:29:47.17#ibcon#*before write, iclass 5, count 0 2006.257.17:29:47.17#ibcon#enter sib2, iclass 5, count 0 2006.257.17:29:47.17#ibcon#flushed, iclass 5, count 0 2006.257.17:29:47.17#ibcon#about to write, iclass 5, count 0 2006.257.17:29:47.17#ibcon#wrote, iclass 5, count 0 2006.257.17:29:47.17#ibcon#about to read 3, iclass 5, count 0 2006.257.17:29:47.21#ibcon#read 3, iclass 5, count 0 2006.257.17:29:47.21#ibcon#about to read 4, iclass 5, count 0 2006.257.17:29:47.21#ibcon#read 4, iclass 5, count 0 2006.257.17:29:47.21#ibcon#about to read 5, iclass 5, count 0 2006.257.17:29:47.21#ibcon#read 5, iclass 5, count 0 2006.257.17:29:47.21#ibcon#about to read 6, iclass 5, count 0 2006.257.17:29:47.21#ibcon#read 6, iclass 5, count 0 2006.257.17:29:47.21#ibcon#end of sib2, iclass 5, count 0 2006.257.17:29:47.21#ibcon#*after write, iclass 5, count 0 2006.257.17:29:47.21#ibcon#*before return 0, iclass 5, count 0 2006.257.17:29:47.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:47.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:29:47.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:29:47.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:29:47.21$vck44/vb=4,5 2006.257.17:29:47.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.17:29:47.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.17:29:47.21#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:47.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:47.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:47.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:47.27#ibcon#enter wrdev, iclass 7, count 2 2006.257.17:29:47.27#ibcon#first serial, iclass 7, count 2 2006.257.17:29:47.27#ibcon#enter sib2, iclass 7, count 2 2006.257.17:29:47.27#ibcon#flushed, iclass 7, count 2 2006.257.17:29:47.27#ibcon#about to write, iclass 7, count 2 2006.257.17:29:47.27#ibcon#wrote, iclass 7, count 2 2006.257.17:29:47.27#ibcon#about to read 3, iclass 7, count 2 2006.257.17:29:47.29#ibcon#read 3, iclass 7, count 2 2006.257.17:29:47.29#ibcon#about to read 4, iclass 7, count 2 2006.257.17:29:47.29#ibcon#read 4, iclass 7, count 2 2006.257.17:29:47.29#ibcon#about to read 5, iclass 7, count 2 2006.257.17:29:47.29#ibcon#read 5, iclass 7, count 2 2006.257.17:29:47.29#ibcon#about to read 6, iclass 7, count 2 2006.257.17:29:47.29#ibcon#read 6, iclass 7, count 2 2006.257.17:29:47.29#ibcon#end of sib2, iclass 7, count 2 2006.257.17:29:47.29#ibcon#*mode == 0, iclass 7, count 2 2006.257.17:29:47.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.17:29:47.29#ibcon#[27=AT04-05\r\n] 2006.257.17:29:47.29#ibcon#*before write, iclass 7, count 2 2006.257.17:29:47.29#ibcon#enter sib2, iclass 7, count 2 2006.257.17:29:47.29#ibcon#flushed, iclass 7, count 2 2006.257.17:29:47.29#ibcon#about to write, iclass 7, count 2 2006.257.17:29:47.29#ibcon#wrote, iclass 7, count 2 2006.257.17:29:47.29#ibcon#about to read 3, iclass 7, count 2 2006.257.17:29:47.32#ibcon#read 3, iclass 7, count 2 2006.257.17:29:47.32#ibcon#about to read 4, iclass 7, count 2 2006.257.17:29:47.32#ibcon#read 4, iclass 7, count 2 2006.257.17:29:47.32#ibcon#about to read 5, iclass 7, count 2 2006.257.17:29:47.32#ibcon#read 5, iclass 7, count 2 2006.257.17:29:47.32#ibcon#about to read 6, iclass 7, count 2 2006.257.17:29:47.32#ibcon#read 6, iclass 7, count 2 2006.257.17:29:47.32#ibcon#end of sib2, iclass 7, count 2 2006.257.17:29:47.32#ibcon#*after write, iclass 7, count 2 2006.257.17:29:47.32#ibcon#*before return 0, iclass 7, count 2 2006.257.17:29:47.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:47.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:29:47.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.17:29:47.32#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:47.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:47.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:47.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:47.44#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:29:47.44#ibcon#first serial, iclass 7, count 0 2006.257.17:29:47.44#ibcon#enter sib2, iclass 7, count 0 2006.257.17:29:47.44#ibcon#flushed, iclass 7, count 0 2006.257.17:29:47.44#ibcon#about to write, iclass 7, count 0 2006.257.17:29:47.44#ibcon#wrote, iclass 7, count 0 2006.257.17:29:47.44#ibcon#about to read 3, iclass 7, count 0 2006.257.17:29:47.46#ibcon#read 3, iclass 7, count 0 2006.257.17:29:47.46#ibcon#about to read 4, iclass 7, count 0 2006.257.17:29:47.46#ibcon#read 4, iclass 7, count 0 2006.257.17:29:47.46#ibcon#about to read 5, iclass 7, count 0 2006.257.17:29:47.46#ibcon#read 5, iclass 7, count 0 2006.257.17:29:47.46#ibcon#about to read 6, iclass 7, count 0 2006.257.17:29:47.46#ibcon#read 6, iclass 7, count 0 2006.257.17:29:47.46#ibcon#end of sib2, iclass 7, count 0 2006.257.17:29:47.46#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:29:47.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:29:47.46#ibcon#[27=USB\r\n] 2006.257.17:29:47.46#ibcon#*before write, iclass 7, count 0 2006.257.17:29:47.46#ibcon#enter sib2, iclass 7, count 0 2006.257.17:29:47.46#ibcon#flushed, iclass 7, count 0 2006.257.17:29:47.46#ibcon#about to write, iclass 7, count 0 2006.257.17:29:47.46#ibcon#wrote, iclass 7, count 0 2006.257.17:29:47.46#ibcon#about to read 3, iclass 7, count 0 2006.257.17:29:47.49#ibcon#read 3, iclass 7, count 0 2006.257.17:29:47.49#ibcon#about to read 4, iclass 7, count 0 2006.257.17:29:47.49#ibcon#read 4, iclass 7, count 0 2006.257.17:29:47.49#ibcon#about to read 5, iclass 7, count 0 2006.257.17:29:47.49#ibcon#read 5, iclass 7, count 0 2006.257.17:29:47.49#ibcon#about to read 6, iclass 7, count 0 2006.257.17:29:47.49#ibcon#read 6, iclass 7, count 0 2006.257.17:29:47.49#ibcon#end of sib2, iclass 7, count 0 2006.257.17:29:47.49#ibcon#*after write, iclass 7, count 0 2006.257.17:29:47.49#ibcon#*before return 0, iclass 7, count 0 2006.257.17:29:47.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:47.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:29:47.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:29:47.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:29:47.49$vck44/vblo=5,709.99 2006.257.17:29:47.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.17:29:47.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.17:29:47.49#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:47.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:47.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:47.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:47.49#ibcon#enter wrdev, iclass 11, count 0 2006.257.17:29:47.49#ibcon#first serial, iclass 11, count 0 2006.257.17:29:47.49#ibcon#enter sib2, iclass 11, count 0 2006.257.17:29:47.49#ibcon#flushed, iclass 11, count 0 2006.257.17:29:47.49#ibcon#about to write, iclass 11, count 0 2006.257.17:29:47.49#ibcon#wrote, iclass 11, count 0 2006.257.17:29:47.50#ibcon#about to read 3, iclass 11, count 0 2006.257.17:29:47.51#ibcon#read 3, iclass 11, count 0 2006.257.17:29:47.51#ibcon#about to read 4, iclass 11, count 0 2006.257.17:29:47.51#ibcon#read 4, iclass 11, count 0 2006.257.17:29:47.51#ibcon#about to read 5, iclass 11, count 0 2006.257.17:29:47.51#ibcon#read 5, iclass 11, count 0 2006.257.17:29:47.51#ibcon#about to read 6, iclass 11, count 0 2006.257.17:29:47.51#ibcon#read 6, iclass 11, count 0 2006.257.17:29:47.51#ibcon#end of sib2, iclass 11, count 0 2006.257.17:29:47.51#ibcon#*mode == 0, iclass 11, count 0 2006.257.17:29:47.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.17:29:47.51#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:29:47.51#ibcon#*before write, iclass 11, count 0 2006.257.17:29:47.51#ibcon#enter sib2, iclass 11, count 0 2006.257.17:29:47.51#ibcon#flushed, iclass 11, count 0 2006.257.17:29:47.51#ibcon#about to write, iclass 11, count 0 2006.257.17:29:47.51#ibcon#wrote, iclass 11, count 0 2006.257.17:29:47.51#ibcon#about to read 3, iclass 11, count 0 2006.257.17:29:47.55#ibcon#read 3, iclass 11, count 0 2006.257.17:29:47.55#ibcon#about to read 4, iclass 11, count 0 2006.257.17:29:47.55#ibcon#read 4, iclass 11, count 0 2006.257.17:29:47.55#ibcon#about to read 5, iclass 11, count 0 2006.257.17:29:47.55#ibcon#read 5, iclass 11, count 0 2006.257.17:29:47.55#ibcon#about to read 6, iclass 11, count 0 2006.257.17:29:47.55#ibcon#read 6, iclass 11, count 0 2006.257.17:29:47.55#ibcon#end of sib2, iclass 11, count 0 2006.257.17:29:47.55#ibcon#*after write, iclass 11, count 0 2006.257.17:29:47.55#ibcon#*before return 0, iclass 11, count 0 2006.257.17:29:47.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:47.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:29:47.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.17:29:47.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.17:29:47.55$vck44/vb=5,4 2006.257.17:29:47.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.17:29:47.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.17:29:47.55#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:47.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:47.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:47.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:47.61#ibcon#enter wrdev, iclass 13, count 2 2006.257.17:29:47.61#ibcon#first serial, iclass 13, count 2 2006.257.17:29:47.61#ibcon#enter sib2, iclass 13, count 2 2006.257.17:29:47.61#ibcon#flushed, iclass 13, count 2 2006.257.17:29:47.61#ibcon#about to write, iclass 13, count 2 2006.257.17:29:47.61#ibcon#wrote, iclass 13, count 2 2006.257.17:29:47.61#ibcon#about to read 3, iclass 13, count 2 2006.257.17:29:47.63#ibcon#read 3, iclass 13, count 2 2006.257.17:29:47.63#ibcon#about to read 4, iclass 13, count 2 2006.257.17:29:47.63#ibcon#read 4, iclass 13, count 2 2006.257.17:29:47.63#ibcon#about to read 5, iclass 13, count 2 2006.257.17:29:47.63#ibcon#read 5, iclass 13, count 2 2006.257.17:29:47.63#ibcon#about to read 6, iclass 13, count 2 2006.257.17:29:47.63#ibcon#read 6, iclass 13, count 2 2006.257.17:29:47.63#ibcon#end of sib2, iclass 13, count 2 2006.257.17:29:47.63#ibcon#*mode == 0, iclass 13, count 2 2006.257.17:29:47.63#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.17:29:47.63#ibcon#[27=AT05-04\r\n] 2006.257.17:29:47.63#ibcon#*before write, iclass 13, count 2 2006.257.17:29:47.63#ibcon#enter sib2, iclass 13, count 2 2006.257.17:29:47.63#ibcon#flushed, iclass 13, count 2 2006.257.17:29:47.63#ibcon#about to write, iclass 13, count 2 2006.257.17:29:47.63#ibcon#wrote, iclass 13, count 2 2006.257.17:29:47.63#ibcon#about to read 3, iclass 13, count 2 2006.257.17:29:47.66#ibcon#read 3, iclass 13, count 2 2006.257.17:29:47.66#ibcon#about to read 4, iclass 13, count 2 2006.257.17:29:47.66#ibcon#read 4, iclass 13, count 2 2006.257.17:29:47.66#ibcon#about to read 5, iclass 13, count 2 2006.257.17:29:47.66#ibcon#read 5, iclass 13, count 2 2006.257.17:29:47.66#ibcon#about to read 6, iclass 13, count 2 2006.257.17:29:47.66#ibcon#read 6, iclass 13, count 2 2006.257.17:29:47.66#ibcon#end of sib2, iclass 13, count 2 2006.257.17:29:47.66#ibcon#*after write, iclass 13, count 2 2006.257.17:29:47.66#ibcon#*before return 0, iclass 13, count 2 2006.257.17:29:47.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:47.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:29:47.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.17:29:47.66#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:47.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:47.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:47.78#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:47.78#ibcon#enter wrdev, iclass 13, count 0 2006.257.17:29:47.78#ibcon#first serial, iclass 13, count 0 2006.257.17:29:47.78#ibcon#enter sib2, iclass 13, count 0 2006.257.17:29:47.78#ibcon#flushed, iclass 13, count 0 2006.257.17:29:47.78#ibcon#about to write, iclass 13, count 0 2006.257.17:29:47.78#ibcon#wrote, iclass 13, count 0 2006.257.17:29:47.78#ibcon#about to read 3, iclass 13, count 0 2006.257.17:29:47.80#ibcon#read 3, iclass 13, count 0 2006.257.17:29:47.80#ibcon#about to read 4, iclass 13, count 0 2006.257.17:29:47.80#ibcon#read 4, iclass 13, count 0 2006.257.17:29:47.80#ibcon#about to read 5, iclass 13, count 0 2006.257.17:29:47.80#ibcon#read 5, iclass 13, count 0 2006.257.17:29:47.80#ibcon#about to read 6, iclass 13, count 0 2006.257.17:29:47.80#ibcon#read 6, iclass 13, count 0 2006.257.17:29:47.80#ibcon#end of sib2, iclass 13, count 0 2006.257.17:29:47.80#ibcon#*mode == 0, iclass 13, count 0 2006.257.17:29:47.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.17:29:47.80#ibcon#[27=USB\r\n] 2006.257.17:29:47.80#ibcon#*before write, iclass 13, count 0 2006.257.17:29:47.80#ibcon#enter sib2, iclass 13, count 0 2006.257.17:29:47.80#ibcon#flushed, iclass 13, count 0 2006.257.17:29:47.80#ibcon#about to write, iclass 13, count 0 2006.257.17:29:47.80#ibcon#wrote, iclass 13, count 0 2006.257.17:29:47.80#ibcon#about to read 3, iclass 13, count 0 2006.257.17:29:47.83#ibcon#read 3, iclass 13, count 0 2006.257.17:29:47.83#ibcon#about to read 4, iclass 13, count 0 2006.257.17:29:47.83#ibcon#read 4, iclass 13, count 0 2006.257.17:29:47.83#ibcon#about to read 5, iclass 13, count 0 2006.257.17:29:47.83#ibcon#read 5, iclass 13, count 0 2006.257.17:29:47.83#ibcon#about to read 6, iclass 13, count 0 2006.257.17:29:47.83#ibcon#read 6, iclass 13, count 0 2006.257.17:29:47.83#ibcon#end of sib2, iclass 13, count 0 2006.257.17:29:47.83#ibcon#*after write, iclass 13, count 0 2006.257.17:29:47.83#ibcon#*before return 0, iclass 13, count 0 2006.257.17:29:47.83#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:47.83#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:29:47.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.17:29:47.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.17:29:47.83$vck44/vblo=6,719.99 2006.257.17:29:47.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.17:29:47.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.17:29:47.83#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:47.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:47.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:47.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:47.83#ibcon#enter wrdev, iclass 15, count 0 2006.257.17:29:47.83#ibcon#first serial, iclass 15, count 0 2006.257.17:29:47.83#ibcon#enter sib2, iclass 15, count 0 2006.257.17:29:47.83#ibcon#flushed, iclass 15, count 0 2006.257.17:29:47.83#ibcon#about to write, iclass 15, count 0 2006.257.17:29:47.84#ibcon#wrote, iclass 15, count 0 2006.257.17:29:47.84#ibcon#about to read 3, iclass 15, count 0 2006.257.17:29:47.85#ibcon#read 3, iclass 15, count 0 2006.257.17:29:47.85#ibcon#about to read 4, iclass 15, count 0 2006.257.17:29:47.85#ibcon#read 4, iclass 15, count 0 2006.257.17:29:47.85#ibcon#about to read 5, iclass 15, count 0 2006.257.17:29:47.85#ibcon#read 5, iclass 15, count 0 2006.257.17:29:47.85#ibcon#about to read 6, iclass 15, count 0 2006.257.17:29:47.85#ibcon#read 6, iclass 15, count 0 2006.257.17:29:47.85#ibcon#end of sib2, iclass 15, count 0 2006.257.17:29:47.85#ibcon#*mode == 0, iclass 15, count 0 2006.257.17:29:47.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.17:29:47.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:29:47.85#ibcon#*before write, iclass 15, count 0 2006.257.17:29:47.85#ibcon#enter sib2, iclass 15, count 0 2006.257.17:29:47.85#ibcon#flushed, iclass 15, count 0 2006.257.17:29:47.85#ibcon#about to write, iclass 15, count 0 2006.257.17:29:47.85#ibcon#wrote, iclass 15, count 0 2006.257.17:29:47.85#ibcon#about to read 3, iclass 15, count 0 2006.257.17:29:47.89#ibcon#read 3, iclass 15, count 0 2006.257.17:29:47.89#ibcon#about to read 4, iclass 15, count 0 2006.257.17:29:47.89#ibcon#read 4, iclass 15, count 0 2006.257.17:29:47.89#ibcon#about to read 5, iclass 15, count 0 2006.257.17:29:47.89#ibcon#read 5, iclass 15, count 0 2006.257.17:29:47.89#ibcon#about to read 6, iclass 15, count 0 2006.257.17:29:47.89#ibcon#read 6, iclass 15, count 0 2006.257.17:29:47.89#ibcon#end of sib2, iclass 15, count 0 2006.257.17:29:47.89#ibcon#*after write, iclass 15, count 0 2006.257.17:29:47.89#ibcon#*before return 0, iclass 15, count 0 2006.257.17:29:47.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:47.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:29:47.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.17:29:47.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.17:29:47.89$vck44/vb=6,4 2006.257.17:29:47.89#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.17:29:47.89#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.17:29:47.89#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:47.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:47.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:47.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:47.95#ibcon#enter wrdev, iclass 17, count 2 2006.257.17:29:47.95#ibcon#first serial, iclass 17, count 2 2006.257.17:29:47.95#ibcon#enter sib2, iclass 17, count 2 2006.257.17:29:47.95#ibcon#flushed, iclass 17, count 2 2006.257.17:29:47.95#ibcon#about to write, iclass 17, count 2 2006.257.17:29:47.95#ibcon#wrote, iclass 17, count 2 2006.257.17:29:47.95#ibcon#about to read 3, iclass 17, count 2 2006.257.17:29:47.97#ibcon#read 3, iclass 17, count 2 2006.257.17:29:47.97#ibcon#about to read 4, iclass 17, count 2 2006.257.17:29:47.97#ibcon#read 4, iclass 17, count 2 2006.257.17:29:47.97#ibcon#about to read 5, iclass 17, count 2 2006.257.17:29:47.97#ibcon#read 5, iclass 17, count 2 2006.257.17:29:47.97#ibcon#about to read 6, iclass 17, count 2 2006.257.17:29:47.97#ibcon#read 6, iclass 17, count 2 2006.257.17:29:47.97#ibcon#end of sib2, iclass 17, count 2 2006.257.17:29:47.97#ibcon#*mode == 0, iclass 17, count 2 2006.257.17:29:47.97#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.17:29:47.97#ibcon#[27=AT06-04\r\n] 2006.257.17:29:47.97#ibcon#*before write, iclass 17, count 2 2006.257.17:29:47.97#ibcon#enter sib2, iclass 17, count 2 2006.257.17:29:47.97#ibcon#flushed, iclass 17, count 2 2006.257.17:29:47.97#ibcon#about to write, iclass 17, count 2 2006.257.17:29:47.97#ibcon#wrote, iclass 17, count 2 2006.257.17:29:47.97#ibcon#about to read 3, iclass 17, count 2 2006.257.17:29:48.00#ibcon#read 3, iclass 17, count 2 2006.257.17:29:48.00#ibcon#about to read 4, iclass 17, count 2 2006.257.17:29:48.00#ibcon#read 4, iclass 17, count 2 2006.257.17:29:48.00#ibcon#about to read 5, iclass 17, count 2 2006.257.17:29:48.00#ibcon#read 5, iclass 17, count 2 2006.257.17:29:48.00#ibcon#about to read 6, iclass 17, count 2 2006.257.17:29:48.00#ibcon#read 6, iclass 17, count 2 2006.257.17:29:48.00#ibcon#end of sib2, iclass 17, count 2 2006.257.17:29:48.00#ibcon#*after write, iclass 17, count 2 2006.257.17:29:48.00#ibcon#*before return 0, iclass 17, count 2 2006.257.17:29:48.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:48.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:29:48.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.17:29:48.00#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:48.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:48.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:48.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:48.12#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:29:48.12#ibcon#first serial, iclass 17, count 0 2006.257.17:29:48.12#ibcon#enter sib2, iclass 17, count 0 2006.257.17:29:48.12#ibcon#flushed, iclass 17, count 0 2006.257.17:29:48.12#ibcon#about to write, iclass 17, count 0 2006.257.17:29:48.12#ibcon#wrote, iclass 17, count 0 2006.257.17:29:48.12#ibcon#about to read 3, iclass 17, count 0 2006.257.17:29:48.14#ibcon#read 3, iclass 17, count 0 2006.257.17:29:48.14#ibcon#about to read 4, iclass 17, count 0 2006.257.17:29:48.14#ibcon#read 4, iclass 17, count 0 2006.257.17:29:48.14#ibcon#about to read 5, iclass 17, count 0 2006.257.17:29:48.14#ibcon#read 5, iclass 17, count 0 2006.257.17:29:48.14#ibcon#about to read 6, iclass 17, count 0 2006.257.17:29:48.14#ibcon#read 6, iclass 17, count 0 2006.257.17:29:48.14#ibcon#end of sib2, iclass 17, count 0 2006.257.17:29:48.14#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:29:48.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:29:48.14#ibcon#[27=USB\r\n] 2006.257.17:29:48.14#ibcon#*before write, iclass 17, count 0 2006.257.17:29:48.14#ibcon#enter sib2, iclass 17, count 0 2006.257.17:29:48.14#ibcon#flushed, iclass 17, count 0 2006.257.17:29:48.14#ibcon#about to write, iclass 17, count 0 2006.257.17:29:48.14#ibcon#wrote, iclass 17, count 0 2006.257.17:29:48.14#ibcon#about to read 3, iclass 17, count 0 2006.257.17:29:48.17#ibcon#read 3, iclass 17, count 0 2006.257.17:29:48.17#ibcon#about to read 4, iclass 17, count 0 2006.257.17:29:48.17#ibcon#read 4, iclass 17, count 0 2006.257.17:29:48.17#ibcon#about to read 5, iclass 17, count 0 2006.257.17:29:48.17#ibcon#read 5, iclass 17, count 0 2006.257.17:29:48.17#ibcon#about to read 6, iclass 17, count 0 2006.257.17:29:48.17#ibcon#read 6, iclass 17, count 0 2006.257.17:29:48.17#ibcon#end of sib2, iclass 17, count 0 2006.257.17:29:48.17#ibcon#*after write, iclass 17, count 0 2006.257.17:29:48.17#ibcon#*before return 0, iclass 17, count 0 2006.257.17:29:48.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:48.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:29:48.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:29:48.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:29:48.17$vck44/vblo=7,734.99 2006.257.17:29:48.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.17:29:48.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.17:29:48.17#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:48.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:48.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:48.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:48.17#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:29:48.17#ibcon#first serial, iclass 19, count 0 2006.257.17:29:48.17#ibcon#enter sib2, iclass 19, count 0 2006.257.17:29:48.17#ibcon#flushed, iclass 19, count 0 2006.257.17:29:48.17#ibcon#about to write, iclass 19, count 0 2006.257.17:29:48.17#ibcon#wrote, iclass 19, count 0 2006.257.17:29:48.18#ibcon#about to read 3, iclass 19, count 0 2006.257.17:29:48.19#ibcon#read 3, iclass 19, count 0 2006.257.17:29:48.19#ibcon#about to read 4, iclass 19, count 0 2006.257.17:29:48.19#ibcon#read 4, iclass 19, count 0 2006.257.17:29:48.19#ibcon#about to read 5, iclass 19, count 0 2006.257.17:29:48.19#ibcon#read 5, iclass 19, count 0 2006.257.17:29:48.19#ibcon#about to read 6, iclass 19, count 0 2006.257.17:29:48.19#ibcon#read 6, iclass 19, count 0 2006.257.17:29:48.19#ibcon#end of sib2, iclass 19, count 0 2006.257.17:29:48.19#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:29:48.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:29:48.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:29:48.19#ibcon#*before write, iclass 19, count 0 2006.257.17:29:48.19#ibcon#enter sib2, iclass 19, count 0 2006.257.17:29:48.19#ibcon#flushed, iclass 19, count 0 2006.257.17:29:48.19#ibcon#about to write, iclass 19, count 0 2006.257.17:29:48.19#ibcon#wrote, iclass 19, count 0 2006.257.17:29:48.19#ibcon#about to read 3, iclass 19, count 0 2006.257.17:29:48.23#ibcon#read 3, iclass 19, count 0 2006.257.17:29:48.23#ibcon#about to read 4, iclass 19, count 0 2006.257.17:29:48.23#ibcon#read 4, iclass 19, count 0 2006.257.17:29:48.23#ibcon#about to read 5, iclass 19, count 0 2006.257.17:29:48.23#ibcon#read 5, iclass 19, count 0 2006.257.17:29:48.23#ibcon#about to read 6, iclass 19, count 0 2006.257.17:29:48.23#ibcon#read 6, iclass 19, count 0 2006.257.17:29:48.23#ibcon#end of sib2, iclass 19, count 0 2006.257.17:29:48.23#ibcon#*after write, iclass 19, count 0 2006.257.17:29:48.23#ibcon#*before return 0, iclass 19, count 0 2006.257.17:29:48.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:48.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:29:48.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:29:48.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:29:48.23$vck44/vb=7,4 2006.257.17:29:48.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.17:29:48.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.17:29:48.23#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:48.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:48.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:48.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:48.29#ibcon#enter wrdev, iclass 21, count 2 2006.257.17:29:48.29#ibcon#first serial, iclass 21, count 2 2006.257.17:29:48.29#ibcon#enter sib2, iclass 21, count 2 2006.257.17:29:48.29#ibcon#flushed, iclass 21, count 2 2006.257.17:29:48.29#ibcon#about to write, iclass 21, count 2 2006.257.17:29:48.29#ibcon#wrote, iclass 21, count 2 2006.257.17:29:48.29#ibcon#about to read 3, iclass 21, count 2 2006.257.17:29:48.31#ibcon#read 3, iclass 21, count 2 2006.257.17:29:48.31#ibcon#about to read 4, iclass 21, count 2 2006.257.17:29:48.31#ibcon#read 4, iclass 21, count 2 2006.257.17:29:48.31#ibcon#about to read 5, iclass 21, count 2 2006.257.17:29:48.31#ibcon#read 5, iclass 21, count 2 2006.257.17:29:48.31#ibcon#about to read 6, iclass 21, count 2 2006.257.17:29:48.31#ibcon#read 6, iclass 21, count 2 2006.257.17:29:48.31#ibcon#end of sib2, iclass 21, count 2 2006.257.17:29:48.31#ibcon#*mode == 0, iclass 21, count 2 2006.257.17:29:48.31#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.17:29:48.31#ibcon#[27=AT07-04\r\n] 2006.257.17:29:48.31#ibcon#*before write, iclass 21, count 2 2006.257.17:29:48.31#ibcon#enter sib2, iclass 21, count 2 2006.257.17:29:48.31#ibcon#flushed, iclass 21, count 2 2006.257.17:29:48.31#ibcon#about to write, iclass 21, count 2 2006.257.17:29:48.31#ibcon#wrote, iclass 21, count 2 2006.257.17:29:48.31#ibcon#about to read 3, iclass 21, count 2 2006.257.17:29:48.34#ibcon#read 3, iclass 21, count 2 2006.257.17:29:48.34#ibcon#about to read 4, iclass 21, count 2 2006.257.17:29:48.34#ibcon#read 4, iclass 21, count 2 2006.257.17:29:48.34#ibcon#about to read 5, iclass 21, count 2 2006.257.17:29:48.34#ibcon#read 5, iclass 21, count 2 2006.257.17:29:48.34#ibcon#about to read 6, iclass 21, count 2 2006.257.17:29:48.34#ibcon#read 6, iclass 21, count 2 2006.257.17:29:48.34#ibcon#end of sib2, iclass 21, count 2 2006.257.17:29:48.34#ibcon#*after write, iclass 21, count 2 2006.257.17:29:48.34#ibcon#*before return 0, iclass 21, count 2 2006.257.17:29:48.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:48.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:29:48.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.17:29:48.34#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:48.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:48.46#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:48.46#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:48.46#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:29:48.46#ibcon#first serial, iclass 21, count 0 2006.257.17:29:48.46#ibcon#enter sib2, iclass 21, count 0 2006.257.17:29:48.46#ibcon#flushed, iclass 21, count 0 2006.257.17:29:48.46#ibcon#about to write, iclass 21, count 0 2006.257.17:29:48.46#ibcon#wrote, iclass 21, count 0 2006.257.17:29:48.46#ibcon#about to read 3, iclass 21, count 0 2006.257.17:29:48.48#ibcon#read 3, iclass 21, count 0 2006.257.17:29:48.48#ibcon#about to read 4, iclass 21, count 0 2006.257.17:29:48.48#ibcon#read 4, iclass 21, count 0 2006.257.17:29:48.48#ibcon#about to read 5, iclass 21, count 0 2006.257.17:29:48.48#ibcon#read 5, iclass 21, count 0 2006.257.17:29:48.48#ibcon#about to read 6, iclass 21, count 0 2006.257.17:29:48.48#ibcon#read 6, iclass 21, count 0 2006.257.17:29:48.48#ibcon#end of sib2, iclass 21, count 0 2006.257.17:29:48.48#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:29:48.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:29:48.48#ibcon#[27=USB\r\n] 2006.257.17:29:48.48#ibcon#*before write, iclass 21, count 0 2006.257.17:29:48.48#ibcon#enter sib2, iclass 21, count 0 2006.257.17:29:48.48#ibcon#flushed, iclass 21, count 0 2006.257.17:29:48.48#ibcon#about to write, iclass 21, count 0 2006.257.17:29:48.48#ibcon#wrote, iclass 21, count 0 2006.257.17:29:48.48#ibcon#about to read 3, iclass 21, count 0 2006.257.17:29:48.51#ibcon#read 3, iclass 21, count 0 2006.257.17:29:48.51#ibcon#about to read 4, iclass 21, count 0 2006.257.17:29:48.51#ibcon#read 4, iclass 21, count 0 2006.257.17:29:48.51#ibcon#about to read 5, iclass 21, count 0 2006.257.17:29:48.51#ibcon#read 5, iclass 21, count 0 2006.257.17:29:48.51#ibcon#about to read 6, iclass 21, count 0 2006.257.17:29:48.51#ibcon#read 6, iclass 21, count 0 2006.257.17:29:48.51#ibcon#end of sib2, iclass 21, count 0 2006.257.17:29:48.51#ibcon#*after write, iclass 21, count 0 2006.257.17:29:48.51#ibcon#*before return 0, iclass 21, count 0 2006.257.17:29:48.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:48.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:29:48.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:29:48.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:29:48.51$vck44/vblo=8,744.99 2006.257.17:29:48.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.17:29:48.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.17:29:48.51#ibcon#ireg 17 cls_cnt 0 2006.257.17:29:48.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:48.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:48.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:48.51#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:29:48.51#ibcon#first serial, iclass 23, count 0 2006.257.17:29:48.51#ibcon#enter sib2, iclass 23, count 0 2006.257.17:29:48.51#ibcon#flushed, iclass 23, count 0 2006.257.17:29:48.51#ibcon#about to write, iclass 23, count 0 2006.257.17:29:48.51#ibcon#wrote, iclass 23, count 0 2006.257.17:29:48.52#ibcon#about to read 3, iclass 23, count 0 2006.257.17:29:48.53#ibcon#read 3, iclass 23, count 0 2006.257.17:29:48.53#ibcon#about to read 4, iclass 23, count 0 2006.257.17:29:48.53#ibcon#read 4, iclass 23, count 0 2006.257.17:29:48.53#ibcon#about to read 5, iclass 23, count 0 2006.257.17:29:48.53#ibcon#read 5, iclass 23, count 0 2006.257.17:29:48.53#ibcon#about to read 6, iclass 23, count 0 2006.257.17:29:48.53#ibcon#read 6, iclass 23, count 0 2006.257.17:29:48.53#ibcon#end of sib2, iclass 23, count 0 2006.257.17:29:48.53#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:29:48.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:29:48.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:29:48.53#ibcon#*before write, iclass 23, count 0 2006.257.17:29:48.53#ibcon#enter sib2, iclass 23, count 0 2006.257.17:29:48.53#ibcon#flushed, iclass 23, count 0 2006.257.17:29:48.53#ibcon#about to write, iclass 23, count 0 2006.257.17:29:48.53#ibcon#wrote, iclass 23, count 0 2006.257.17:29:48.53#ibcon#about to read 3, iclass 23, count 0 2006.257.17:29:48.57#ibcon#read 3, iclass 23, count 0 2006.257.17:29:48.57#ibcon#about to read 4, iclass 23, count 0 2006.257.17:29:48.57#ibcon#read 4, iclass 23, count 0 2006.257.17:29:48.57#ibcon#about to read 5, iclass 23, count 0 2006.257.17:29:48.57#ibcon#read 5, iclass 23, count 0 2006.257.17:29:48.57#ibcon#about to read 6, iclass 23, count 0 2006.257.17:29:48.57#ibcon#read 6, iclass 23, count 0 2006.257.17:29:48.57#ibcon#end of sib2, iclass 23, count 0 2006.257.17:29:48.57#ibcon#*after write, iclass 23, count 0 2006.257.17:29:48.57#ibcon#*before return 0, iclass 23, count 0 2006.257.17:29:48.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:48.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:29:48.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:29:48.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:29:48.57$vck44/vb=8,4 2006.257.17:29:48.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.17:29:48.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.17:29:48.57#ibcon#ireg 11 cls_cnt 2 2006.257.17:29:48.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:48.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:48.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:48.63#ibcon#enter wrdev, iclass 25, count 2 2006.257.17:29:48.63#ibcon#first serial, iclass 25, count 2 2006.257.17:29:48.63#ibcon#enter sib2, iclass 25, count 2 2006.257.17:29:48.63#ibcon#flushed, iclass 25, count 2 2006.257.17:29:48.63#ibcon#about to write, iclass 25, count 2 2006.257.17:29:48.63#ibcon#wrote, iclass 25, count 2 2006.257.17:29:48.63#ibcon#about to read 3, iclass 25, count 2 2006.257.17:29:48.65#ibcon#read 3, iclass 25, count 2 2006.257.17:29:48.65#ibcon#about to read 4, iclass 25, count 2 2006.257.17:29:48.65#ibcon#read 4, iclass 25, count 2 2006.257.17:29:48.65#ibcon#about to read 5, iclass 25, count 2 2006.257.17:29:48.65#ibcon#read 5, iclass 25, count 2 2006.257.17:29:48.65#ibcon#about to read 6, iclass 25, count 2 2006.257.17:29:48.65#ibcon#read 6, iclass 25, count 2 2006.257.17:29:48.65#ibcon#end of sib2, iclass 25, count 2 2006.257.17:29:48.65#ibcon#*mode == 0, iclass 25, count 2 2006.257.17:29:48.65#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.17:29:48.65#ibcon#[27=AT08-04\r\n] 2006.257.17:29:48.65#ibcon#*before write, iclass 25, count 2 2006.257.17:29:48.65#ibcon#enter sib2, iclass 25, count 2 2006.257.17:29:48.65#ibcon#flushed, iclass 25, count 2 2006.257.17:29:48.65#ibcon#about to write, iclass 25, count 2 2006.257.17:29:48.65#ibcon#wrote, iclass 25, count 2 2006.257.17:29:48.65#ibcon#about to read 3, iclass 25, count 2 2006.257.17:29:48.68#ibcon#read 3, iclass 25, count 2 2006.257.17:29:48.68#ibcon#about to read 4, iclass 25, count 2 2006.257.17:29:48.68#ibcon#read 4, iclass 25, count 2 2006.257.17:29:48.68#ibcon#about to read 5, iclass 25, count 2 2006.257.17:29:48.68#ibcon#read 5, iclass 25, count 2 2006.257.17:29:48.68#ibcon#about to read 6, iclass 25, count 2 2006.257.17:29:48.68#ibcon#read 6, iclass 25, count 2 2006.257.17:29:48.68#ibcon#end of sib2, iclass 25, count 2 2006.257.17:29:48.68#ibcon#*after write, iclass 25, count 2 2006.257.17:29:48.68#ibcon#*before return 0, iclass 25, count 2 2006.257.17:29:48.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:48.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:29:48.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.17:29:48.68#ibcon#ireg 7 cls_cnt 0 2006.257.17:29:48.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:48.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:48.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:48.80#ibcon#enter wrdev, iclass 25, count 0 2006.257.17:29:48.80#ibcon#first serial, iclass 25, count 0 2006.257.17:29:48.80#ibcon#enter sib2, iclass 25, count 0 2006.257.17:29:48.80#ibcon#flushed, iclass 25, count 0 2006.257.17:29:48.80#ibcon#about to write, iclass 25, count 0 2006.257.17:29:48.80#ibcon#wrote, iclass 25, count 0 2006.257.17:29:48.80#ibcon#about to read 3, iclass 25, count 0 2006.257.17:29:48.82#ibcon#read 3, iclass 25, count 0 2006.257.17:29:48.82#ibcon#about to read 4, iclass 25, count 0 2006.257.17:29:48.82#ibcon#read 4, iclass 25, count 0 2006.257.17:29:48.82#ibcon#about to read 5, iclass 25, count 0 2006.257.17:29:48.82#ibcon#read 5, iclass 25, count 0 2006.257.17:29:48.82#ibcon#about to read 6, iclass 25, count 0 2006.257.17:29:48.82#ibcon#read 6, iclass 25, count 0 2006.257.17:29:48.82#ibcon#end of sib2, iclass 25, count 0 2006.257.17:29:48.82#ibcon#*mode == 0, iclass 25, count 0 2006.257.17:29:48.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.17:29:48.82#ibcon#[27=USB\r\n] 2006.257.17:29:48.82#ibcon#*before write, iclass 25, count 0 2006.257.17:29:48.82#ibcon#enter sib2, iclass 25, count 0 2006.257.17:29:48.82#ibcon#flushed, iclass 25, count 0 2006.257.17:29:48.82#ibcon#about to write, iclass 25, count 0 2006.257.17:29:48.82#ibcon#wrote, iclass 25, count 0 2006.257.17:29:48.82#ibcon#about to read 3, iclass 25, count 0 2006.257.17:29:48.85#ibcon#read 3, iclass 25, count 0 2006.257.17:29:48.85#ibcon#about to read 4, iclass 25, count 0 2006.257.17:29:48.85#ibcon#read 4, iclass 25, count 0 2006.257.17:29:48.85#ibcon#about to read 5, iclass 25, count 0 2006.257.17:29:48.85#ibcon#read 5, iclass 25, count 0 2006.257.17:29:48.85#ibcon#about to read 6, iclass 25, count 0 2006.257.17:29:48.85#ibcon#read 6, iclass 25, count 0 2006.257.17:29:48.85#ibcon#end of sib2, iclass 25, count 0 2006.257.17:29:48.85#ibcon#*after write, iclass 25, count 0 2006.257.17:29:48.85#ibcon#*before return 0, iclass 25, count 0 2006.257.17:29:48.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:48.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:29:48.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.17:29:48.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.17:29:48.85$vck44/vabw=wide 2006.257.17:29:48.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.17:29:48.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.17:29:48.85#ibcon#ireg 8 cls_cnt 0 2006.257.17:29:48.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:48.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:48.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:48.85#ibcon#enter wrdev, iclass 27, count 0 2006.257.17:29:48.85#ibcon#first serial, iclass 27, count 0 2006.257.17:29:48.85#ibcon#enter sib2, iclass 27, count 0 2006.257.17:29:48.85#ibcon#flushed, iclass 27, count 0 2006.257.17:29:48.85#ibcon#about to write, iclass 27, count 0 2006.257.17:29:48.85#ibcon#wrote, iclass 27, count 0 2006.257.17:29:48.85#ibcon#about to read 3, iclass 27, count 0 2006.257.17:29:48.87#ibcon#read 3, iclass 27, count 0 2006.257.17:29:48.87#ibcon#about to read 4, iclass 27, count 0 2006.257.17:29:48.87#ibcon#read 4, iclass 27, count 0 2006.257.17:29:48.87#ibcon#about to read 5, iclass 27, count 0 2006.257.17:29:48.87#ibcon#read 5, iclass 27, count 0 2006.257.17:29:48.87#ibcon#about to read 6, iclass 27, count 0 2006.257.17:29:48.87#ibcon#read 6, iclass 27, count 0 2006.257.17:29:48.87#ibcon#end of sib2, iclass 27, count 0 2006.257.17:29:48.87#ibcon#*mode == 0, iclass 27, count 0 2006.257.17:29:48.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.17:29:48.87#ibcon#[25=BW32\r\n] 2006.257.17:29:48.87#ibcon#*before write, iclass 27, count 0 2006.257.17:29:48.87#ibcon#enter sib2, iclass 27, count 0 2006.257.17:29:48.87#ibcon#flushed, iclass 27, count 0 2006.257.17:29:48.87#ibcon#about to write, iclass 27, count 0 2006.257.17:29:48.87#ibcon#wrote, iclass 27, count 0 2006.257.17:29:48.87#ibcon#about to read 3, iclass 27, count 0 2006.257.17:29:48.90#ibcon#read 3, iclass 27, count 0 2006.257.17:29:48.90#ibcon#about to read 4, iclass 27, count 0 2006.257.17:29:48.90#ibcon#read 4, iclass 27, count 0 2006.257.17:29:48.90#ibcon#about to read 5, iclass 27, count 0 2006.257.17:29:48.90#ibcon#read 5, iclass 27, count 0 2006.257.17:29:48.90#ibcon#about to read 6, iclass 27, count 0 2006.257.17:29:48.90#ibcon#read 6, iclass 27, count 0 2006.257.17:29:48.90#ibcon#end of sib2, iclass 27, count 0 2006.257.17:29:48.90#ibcon#*after write, iclass 27, count 0 2006.257.17:29:48.90#ibcon#*before return 0, iclass 27, count 0 2006.257.17:29:48.90#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:48.90#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:29:48.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.17:29:48.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.17:29:48.90$vck44/vbbw=wide 2006.257.17:29:48.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.17:29:48.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.17:29:48.90#ibcon#ireg 8 cls_cnt 0 2006.257.17:29:48.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:29:48.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:29:48.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:29:48.97#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:29:48.97#ibcon#first serial, iclass 29, count 0 2006.257.17:29:48.97#ibcon#enter sib2, iclass 29, count 0 2006.257.17:29:48.97#ibcon#flushed, iclass 29, count 0 2006.257.17:29:48.97#ibcon#about to write, iclass 29, count 0 2006.257.17:29:48.97#ibcon#wrote, iclass 29, count 0 2006.257.17:29:48.97#ibcon#about to read 3, iclass 29, count 0 2006.257.17:29:48.99#ibcon#read 3, iclass 29, count 0 2006.257.17:29:48.99#ibcon#about to read 4, iclass 29, count 0 2006.257.17:29:48.99#ibcon#read 4, iclass 29, count 0 2006.257.17:29:48.99#ibcon#about to read 5, iclass 29, count 0 2006.257.17:29:48.99#ibcon#read 5, iclass 29, count 0 2006.257.17:29:48.99#ibcon#about to read 6, iclass 29, count 0 2006.257.17:29:48.99#ibcon#read 6, iclass 29, count 0 2006.257.17:29:48.99#ibcon#end of sib2, iclass 29, count 0 2006.257.17:29:48.99#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:29:48.99#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:29:48.99#ibcon#[27=BW32\r\n] 2006.257.17:29:48.99#ibcon#*before write, iclass 29, count 0 2006.257.17:29:48.99#ibcon#enter sib2, iclass 29, count 0 2006.257.17:29:48.99#ibcon#flushed, iclass 29, count 0 2006.257.17:29:48.99#ibcon#about to write, iclass 29, count 0 2006.257.17:29:48.99#ibcon#wrote, iclass 29, count 0 2006.257.17:29:48.99#ibcon#about to read 3, iclass 29, count 0 2006.257.17:29:49.02#ibcon#read 3, iclass 29, count 0 2006.257.17:29:49.02#ibcon#about to read 4, iclass 29, count 0 2006.257.17:29:49.02#ibcon#read 4, iclass 29, count 0 2006.257.17:29:49.02#ibcon#about to read 5, iclass 29, count 0 2006.257.17:29:49.02#ibcon#read 5, iclass 29, count 0 2006.257.17:29:49.02#ibcon#about to read 6, iclass 29, count 0 2006.257.17:29:49.02#ibcon#read 6, iclass 29, count 0 2006.257.17:29:49.02#ibcon#end of sib2, iclass 29, count 0 2006.257.17:29:49.02#ibcon#*after write, iclass 29, count 0 2006.257.17:29:49.02#ibcon#*before return 0, iclass 29, count 0 2006.257.17:29:49.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:29:49.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:29:49.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:29:49.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:29:49.02$setupk4/ifdk4 2006.257.17:29:49.02$ifdk4/lo= 2006.257.17:29:49.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:29:49.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:29:49.03$ifdk4/patch= 2006.257.17:29:49.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:29:49.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:29:49.03$setupk4/!*+20s 2006.257.17:29:51.36#abcon#<5=/14 1.6 4.4 17.40 971014.2\r\n> 2006.257.17:29:51.38#abcon#{5=INTERFACE CLEAR} 2006.257.17:29:51.44#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:30:01.53#abcon#<5=/14 1.6 4.4 17.40 971014.2\r\n> 2006.257.17:30:01.55#abcon#{5=INTERFACE CLEAR} 2006.257.17:30:01.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:30:03.58$setupk4/"tpicd 2006.257.17:30:03.58$setupk4/echo=off 2006.257.17:30:03.58$setupk4/xlog=off 2006.257.17:30:03.58:!2006.257.17:32:21 2006.257.17:30:37.14#trakl#Source acquired 2006.257.17:30:39.14#flagr#flagr/antenna,acquired 2006.257.17:32:21.00:preob 2006.257.17:32:22.14/onsource/TRACKING 2006.257.17:32:22.14:!2006.257.17:32:31 2006.257.17:32:31.00:"tape 2006.257.17:32:31.00:"st=record 2006.257.17:32:31.00:data_valid=on 2006.257.17:32:31.00:midob 2006.257.17:32:31.14/onsource/TRACKING 2006.257.17:32:31.14/wx/17.40,1014.2,97 2006.257.17:32:31.28/cable/+6.4865E-03 2006.257.17:32:32.37/va/01,08,usb,yes,33,35 2006.257.17:32:32.37/va/02,07,usb,yes,35,36 2006.257.17:32:32.37/va/03,08,usb,yes,32,34 2006.257.17:32:32.37/va/04,07,usb,yes,36,38 2006.257.17:32:32.37/va/05,04,usb,yes,33,33 2006.257.17:32:32.37/va/06,04,usb,yes,36,36 2006.257.17:32:32.37/va/07,04,usb,yes,37,38 2006.257.17:32:32.37/va/08,04,usb,yes,31,38 2006.257.17:32:32.60/valo/01,524.99,yes,locked 2006.257.17:32:32.60/valo/02,534.99,yes,locked 2006.257.17:32:32.60/valo/03,564.99,yes,locked 2006.257.17:32:32.60/valo/04,624.99,yes,locked 2006.257.17:32:32.60/valo/05,734.99,yes,locked 2006.257.17:32:32.60/valo/06,814.99,yes,locked 2006.257.17:32:32.60/valo/07,864.99,yes,locked 2006.257.17:32:32.60/valo/08,884.99,yes,locked 2006.257.17:32:33.69/vb/01,04,usb,yes,29,27 2006.257.17:32:33.69/vb/02,05,usb,yes,27,27 2006.257.17:32:33.69/vb/03,04,usb,yes,28,31 2006.257.17:32:33.69/vb/04,05,usb,yes,28,27 2006.257.17:32:33.69/vb/05,04,usb,yes,25,27 2006.257.17:32:33.69/vb/06,04,usb,yes,30,26 2006.257.17:32:33.69/vb/07,04,usb,yes,29,29 2006.257.17:32:33.69/vb/08,04,usb,yes,27,30 2006.257.17:32:33.93/vblo/01,629.99,yes,locked 2006.257.17:32:33.93/vblo/02,634.99,yes,locked 2006.257.17:32:33.93/vblo/03,649.99,yes,locked 2006.257.17:32:33.93/vblo/04,679.99,yes,locked 2006.257.17:32:33.93/vblo/05,709.99,yes,locked 2006.257.17:32:33.93/vblo/06,719.99,yes,locked 2006.257.17:32:33.93/vblo/07,734.99,yes,locked 2006.257.17:32:33.93/vblo/08,744.99,yes,locked 2006.257.17:32:34.08/vabw/8 2006.257.17:32:34.23/vbbw/8 2006.257.17:32:34.32/xfe/off,on,15.0 2006.257.17:32:34.70/ifatt/23,28,28,28 2006.257.17:32:35.07/fmout-gps/S +4.49E-07 2006.257.17:32:35.11:!2006.257.17:34:11 2006.257.17:34:11.01:data_valid=off 2006.257.17:34:11.01:"et 2006.257.17:34:11.01:!+3s 2006.257.17:34:14.02:"tape 2006.257.17:34:14.02:postob 2006.257.17:34:14.24/cable/+6.4862E-03 2006.257.17:34:14.24/wx/17.40,1014.2,97 2006.257.17:34:14.30/fmout-gps/S +4.50E-07 2006.257.17:34:14.30:scan_name=257-1736,jd0609,170 2006.257.17:34:14.30:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.257.17:34:16.14#flagr#flagr/antenna,new-source 2006.257.17:34:16.14:checkk5 2006.257.17:34:16.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:34:16.84/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:34:17.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:34:17.57/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:34:17.90/chk_obsdata//k5ts1/T2571732??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.17:34:18.23/chk_obsdata//k5ts2/T2571732??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.17:34:18.57/chk_obsdata//k5ts3/T2571732??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.17:34:18.90/chk_obsdata//k5ts4/T2571732??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.17:34:19.57/k5log//k5ts1_log_newline 2006.257.17:34:20.23/k5log//k5ts2_log_newline 2006.257.17:34:20.88/k5log//k5ts3_log_newline 2006.257.17:34:21.54/k5log//k5ts4_log_newline 2006.257.17:34:21.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:34:21.56:setupk4=1 2006.257.17:34:21.56$setupk4/echo=on 2006.257.17:34:21.56$setupk4/pcalon 2006.257.17:34:21.56$pcalon/"no phase cal control is implemented here 2006.257.17:34:21.56$setupk4/"tpicd=stop 2006.257.17:34:21.56$setupk4/"rec=synch_on 2006.257.17:34:21.56$setupk4/"rec_mode=128 2006.257.17:34:21.56$setupk4/!* 2006.257.17:34:21.56$setupk4/recpk4 2006.257.17:34:21.56$recpk4/recpatch= 2006.257.17:34:21.56$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:34:21.56$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:34:21.56$setupk4/vck44 2006.257.17:34:21.56$vck44/valo=1,524.99 2006.257.17:34:21.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.17:34:21.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.17:34:21.56#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:21.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:21.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:21.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:21.56#ibcon#enter wrdev, iclass 34, count 0 2006.257.17:34:21.56#ibcon#first serial, iclass 34, count 0 2006.257.17:34:21.56#ibcon#enter sib2, iclass 34, count 0 2006.257.17:34:21.56#ibcon#flushed, iclass 34, count 0 2006.257.17:34:21.56#ibcon#about to write, iclass 34, count 0 2006.257.17:34:21.56#ibcon#wrote, iclass 34, count 0 2006.257.17:34:21.56#ibcon#about to read 3, iclass 34, count 0 2006.257.17:34:21.58#ibcon#read 3, iclass 34, count 0 2006.257.17:34:21.58#ibcon#about to read 4, iclass 34, count 0 2006.257.17:34:21.58#ibcon#read 4, iclass 34, count 0 2006.257.17:34:21.58#ibcon#about to read 5, iclass 34, count 0 2006.257.17:34:21.58#ibcon#read 5, iclass 34, count 0 2006.257.17:34:21.58#ibcon#about to read 6, iclass 34, count 0 2006.257.17:34:21.58#ibcon#read 6, iclass 34, count 0 2006.257.17:34:21.58#ibcon#end of sib2, iclass 34, count 0 2006.257.17:34:21.58#ibcon#*mode == 0, iclass 34, count 0 2006.257.17:34:21.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.17:34:21.58#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:34:21.58#ibcon#*before write, iclass 34, count 0 2006.257.17:34:21.58#ibcon#enter sib2, iclass 34, count 0 2006.257.17:34:21.58#ibcon#flushed, iclass 34, count 0 2006.257.17:34:21.58#ibcon#about to write, iclass 34, count 0 2006.257.17:34:21.58#ibcon#wrote, iclass 34, count 0 2006.257.17:34:21.58#ibcon#about to read 3, iclass 34, count 0 2006.257.17:34:21.63#ibcon#read 3, iclass 34, count 0 2006.257.17:34:21.63#ibcon#about to read 4, iclass 34, count 0 2006.257.17:34:21.63#ibcon#read 4, iclass 34, count 0 2006.257.17:34:21.63#ibcon#about to read 5, iclass 34, count 0 2006.257.17:34:21.63#ibcon#read 5, iclass 34, count 0 2006.257.17:34:21.63#ibcon#about to read 6, iclass 34, count 0 2006.257.17:34:21.63#ibcon#read 6, iclass 34, count 0 2006.257.17:34:21.63#ibcon#end of sib2, iclass 34, count 0 2006.257.17:34:21.63#ibcon#*after write, iclass 34, count 0 2006.257.17:34:21.63#ibcon#*before return 0, iclass 34, count 0 2006.257.17:34:21.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:21.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:21.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.17:34:21.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.17:34:21.63$vck44/va=1,8 2006.257.17:34:21.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.17:34:21.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.17:34:21.63#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:21.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:21.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:21.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:21.63#ibcon#enter wrdev, iclass 36, count 2 2006.257.17:34:21.63#ibcon#first serial, iclass 36, count 2 2006.257.17:34:21.63#ibcon#enter sib2, iclass 36, count 2 2006.257.17:34:21.63#ibcon#flushed, iclass 36, count 2 2006.257.17:34:21.63#ibcon#about to write, iclass 36, count 2 2006.257.17:34:21.63#ibcon#wrote, iclass 36, count 2 2006.257.17:34:21.63#ibcon#about to read 3, iclass 36, count 2 2006.257.17:34:21.65#ibcon#read 3, iclass 36, count 2 2006.257.17:34:21.65#ibcon#about to read 4, iclass 36, count 2 2006.257.17:34:21.65#ibcon#read 4, iclass 36, count 2 2006.257.17:34:21.65#ibcon#about to read 5, iclass 36, count 2 2006.257.17:34:21.65#ibcon#read 5, iclass 36, count 2 2006.257.17:34:21.65#ibcon#about to read 6, iclass 36, count 2 2006.257.17:34:21.65#ibcon#read 6, iclass 36, count 2 2006.257.17:34:21.65#ibcon#end of sib2, iclass 36, count 2 2006.257.17:34:21.65#ibcon#*mode == 0, iclass 36, count 2 2006.257.17:34:21.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.17:34:21.65#ibcon#[25=AT01-08\r\n] 2006.257.17:34:21.65#ibcon#*before write, iclass 36, count 2 2006.257.17:34:21.65#ibcon#enter sib2, iclass 36, count 2 2006.257.17:34:21.65#ibcon#flushed, iclass 36, count 2 2006.257.17:34:21.65#ibcon#about to write, iclass 36, count 2 2006.257.17:34:21.65#ibcon#wrote, iclass 36, count 2 2006.257.17:34:21.65#ibcon#about to read 3, iclass 36, count 2 2006.257.17:34:21.68#ibcon#read 3, iclass 36, count 2 2006.257.17:34:21.68#ibcon#about to read 4, iclass 36, count 2 2006.257.17:34:21.68#ibcon#read 4, iclass 36, count 2 2006.257.17:34:21.68#ibcon#about to read 5, iclass 36, count 2 2006.257.17:34:21.68#ibcon#read 5, iclass 36, count 2 2006.257.17:34:21.68#ibcon#about to read 6, iclass 36, count 2 2006.257.17:34:21.68#ibcon#read 6, iclass 36, count 2 2006.257.17:34:21.68#ibcon#end of sib2, iclass 36, count 2 2006.257.17:34:21.68#ibcon#*after write, iclass 36, count 2 2006.257.17:34:21.68#ibcon#*before return 0, iclass 36, count 2 2006.257.17:34:21.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:21.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:21.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.17:34:21.68#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:21.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:21.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:21.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:21.80#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:34:21.80#ibcon#first serial, iclass 36, count 0 2006.257.17:34:21.80#ibcon#enter sib2, iclass 36, count 0 2006.257.17:34:21.80#ibcon#flushed, iclass 36, count 0 2006.257.17:34:21.80#ibcon#about to write, iclass 36, count 0 2006.257.17:34:21.80#ibcon#wrote, iclass 36, count 0 2006.257.17:34:21.80#ibcon#about to read 3, iclass 36, count 0 2006.257.17:34:21.82#ibcon#read 3, iclass 36, count 0 2006.257.17:34:21.82#ibcon#about to read 4, iclass 36, count 0 2006.257.17:34:21.82#ibcon#read 4, iclass 36, count 0 2006.257.17:34:21.82#ibcon#about to read 5, iclass 36, count 0 2006.257.17:34:21.82#ibcon#read 5, iclass 36, count 0 2006.257.17:34:21.82#ibcon#about to read 6, iclass 36, count 0 2006.257.17:34:21.82#ibcon#read 6, iclass 36, count 0 2006.257.17:34:21.82#ibcon#end of sib2, iclass 36, count 0 2006.257.17:34:21.82#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:34:21.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:34:21.82#ibcon#[25=USB\r\n] 2006.257.17:34:21.82#ibcon#*before write, iclass 36, count 0 2006.257.17:34:21.82#ibcon#enter sib2, iclass 36, count 0 2006.257.17:34:21.82#ibcon#flushed, iclass 36, count 0 2006.257.17:34:21.82#ibcon#about to write, iclass 36, count 0 2006.257.17:34:21.82#ibcon#wrote, iclass 36, count 0 2006.257.17:34:21.82#ibcon#about to read 3, iclass 36, count 0 2006.257.17:34:21.85#ibcon#read 3, iclass 36, count 0 2006.257.17:34:21.85#ibcon#about to read 4, iclass 36, count 0 2006.257.17:34:21.85#ibcon#read 4, iclass 36, count 0 2006.257.17:34:21.85#ibcon#about to read 5, iclass 36, count 0 2006.257.17:34:21.85#ibcon#read 5, iclass 36, count 0 2006.257.17:34:21.85#ibcon#about to read 6, iclass 36, count 0 2006.257.17:34:21.85#ibcon#read 6, iclass 36, count 0 2006.257.17:34:21.85#ibcon#end of sib2, iclass 36, count 0 2006.257.17:34:21.85#ibcon#*after write, iclass 36, count 0 2006.257.17:34:21.85#ibcon#*before return 0, iclass 36, count 0 2006.257.17:34:21.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:21.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:21.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:34:21.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:34:21.85$vck44/valo=2,534.99 2006.257.17:34:21.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.17:34:21.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.17:34:21.85#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:21.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:21.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:21.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:21.85#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:34:21.85#ibcon#first serial, iclass 38, count 0 2006.257.17:34:21.85#ibcon#enter sib2, iclass 38, count 0 2006.257.17:34:21.85#ibcon#flushed, iclass 38, count 0 2006.257.17:34:21.85#ibcon#about to write, iclass 38, count 0 2006.257.17:34:21.85#ibcon#wrote, iclass 38, count 0 2006.257.17:34:21.85#ibcon#about to read 3, iclass 38, count 0 2006.257.17:34:21.87#ibcon#read 3, iclass 38, count 0 2006.257.17:34:21.87#ibcon#about to read 4, iclass 38, count 0 2006.257.17:34:21.87#ibcon#read 4, iclass 38, count 0 2006.257.17:34:21.87#ibcon#about to read 5, iclass 38, count 0 2006.257.17:34:21.87#ibcon#read 5, iclass 38, count 0 2006.257.17:34:21.87#ibcon#about to read 6, iclass 38, count 0 2006.257.17:34:21.87#ibcon#read 6, iclass 38, count 0 2006.257.17:34:21.87#ibcon#end of sib2, iclass 38, count 0 2006.257.17:34:21.87#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:34:21.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:34:21.87#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:34:21.87#ibcon#*before write, iclass 38, count 0 2006.257.17:34:21.87#ibcon#enter sib2, iclass 38, count 0 2006.257.17:34:21.87#ibcon#flushed, iclass 38, count 0 2006.257.17:34:21.87#ibcon#about to write, iclass 38, count 0 2006.257.17:34:21.87#ibcon#wrote, iclass 38, count 0 2006.257.17:34:21.87#ibcon#about to read 3, iclass 38, count 0 2006.257.17:34:21.91#ibcon#read 3, iclass 38, count 0 2006.257.17:34:21.91#ibcon#about to read 4, iclass 38, count 0 2006.257.17:34:21.91#ibcon#read 4, iclass 38, count 0 2006.257.17:34:21.91#ibcon#about to read 5, iclass 38, count 0 2006.257.17:34:21.91#ibcon#read 5, iclass 38, count 0 2006.257.17:34:21.91#ibcon#about to read 6, iclass 38, count 0 2006.257.17:34:21.91#ibcon#read 6, iclass 38, count 0 2006.257.17:34:21.91#ibcon#end of sib2, iclass 38, count 0 2006.257.17:34:21.91#ibcon#*after write, iclass 38, count 0 2006.257.17:34:21.91#ibcon#*before return 0, iclass 38, count 0 2006.257.17:34:21.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:21.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:21.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:34:21.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:34:21.91$vck44/va=2,7 2006.257.17:34:21.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.17:34:21.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.17:34:21.91#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:21.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:21.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:21.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:21.97#ibcon#enter wrdev, iclass 40, count 2 2006.257.17:34:21.97#ibcon#first serial, iclass 40, count 2 2006.257.17:34:21.97#ibcon#enter sib2, iclass 40, count 2 2006.257.17:34:21.97#ibcon#flushed, iclass 40, count 2 2006.257.17:34:21.97#ibcon#about to write, iclass 40, count 2 2006.257.17:34:21.97#ibcon#wrote, iclass 40, count 2 2006.257.17:34:21.97#ibcon#about to read 3, iclass 40, count 2 2006.257.17:34:21.99#ibcon#read 3, iclass 40, count 2 2006.257.17:34:21.99#ibcon#about to read 4, iclass 40, count 2 2006.257.17:34:21.99#ibcon#read 4, iclass 40, count 2 2006.257.17:34:21.99#ibcon#about to read 5, iclass 40, count 2 2006.257.17:34:21.99#ibcon#read 5, iclass 40, count 2 2006.257.17:34:21.99#ibcon#about to read 6, iclass 40, count 2 2006.257.17:34:21.99#ibcon#read 6, iclass 40, count 2 2006.257.17:34:21.99#ibcon#end of sib2, iclass 40, count 2 2006.257.17:34:21.99#ibcon#*mode == 0, iclass 40, count 2 2006.257.17:34:21.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.17:34:21.99#ibcon#[25=AT02-07\r\n] 2006.257.17:34:21.99#ibcon#*before write, iclass 40, count 2 2006.257.17:34:21.99#ibcon#enter sib2, iclass 40, count 2 2006.257.17:34:21.99#ibcon#flushed, iclass 40, count 2 2006.257.17:34:21.99#ibcon#about to write, iclass 40, count 2 2006.257.17:34:21.99#ibcon#wrote, iclass 40, count 2 2006.257.17:34:21.99#ibcon#about to read 3, iclass 40, count 2 2006.257.17:34:22.02#ibcon#read 3, iclass 40, count 2 2006.257.17:34:22.02#ibcon#about to read 4, iclass 40, count 2 2006.257.17:34:22.02#ibcon#read 4, iclass 40, count 2 2006.257.17:34:22.02#ibcon#about to read 5, iclass 40, count 2 2006.257.17:34:22.02#ibcon#read 5, iclass 40, count 2 2006.257.17:34:22.02#ibcon#about to read 6, iclass 40, count 2 2006.257.17:34:22.02#ibcon#read 6, iclass 40, count 2 2006.257.17:34:22.02#ibcon#end of sib2, iclass 40, count 2 2006.257.17:34:22.02#ibcon#*after write, iclass 40, count 2 2006.257.17:34:22.02#ibcon#*before return 0, iclass 40, count 2 2006.257.17:34:22.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:22.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:22.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.17:34:22.02#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:22.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:22.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:22.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:22.14#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:34:22.14#ibcon#first serial, iclass 40, count 0 2006.257.17:34:22.14#ibcon#enter sib2, iclass 40, count 0 2006.257.17:34:22.14#ibcon#flushed, iclass 40, count 0 2006.257.17:34:22.14#ibcon#about to write, iclass 40, count 0 2006.257.17:34:22.14#ibcon#wrote, iclass 40, count 0 2006.257.17:34:22.14#ibcon#about to read 3, iclass 40, count 0 2006.257.17:34:22.16#ibcon#read 3, iclass 40, count 0 2006.257.17:34:22.16#ibcon#about to read 4, iclass 40, count 0 2006.257.17:34:22.16#ibcon#read 4, iclass 40, count 0 2006.257.17:34:22.16#ibcon#about to read 5, iclass 40, count 0 2006.257.17:34:22.16#ibcon#read 5, iclass 40, count 0 2006.257.17:34:22.16#ibcon#about to read 6, iclass 40, count 0 2006.257.17:34:22.16#ibcon#read 6, iclass 40, count 0 2006.257.17:34:22.16#ibcon#end of sib2, iclass 40, count 0 2006.257.17:34:22.16#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:34:22.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:34:22.16#ibcon#[25=USB\r\n] 2006.257.17:34:22.16#ibcon#*before write, iclass 40, count 0 2006.257.17:34:22.16#ibcon#enter sib2, iclass 40, count 0 2006.257.17:34:22.16#ibcon#flushed, iclass 40, count 0 2006.257.17:34:22.16#ibcon#about to write, iclass 40, count 0 2006.257.17:34:22.16#ibcon#wrote, iclass 40, count 0 2006.257.17:34:22.16#ibcon#about to read 3, iclass 40, count 0 2006.257.17:34:22.19#ibcon#read 3, iclass 40, count 0 2006.257.17:34:22.19#ibcon#about to read 4, iclass 40, count 0 2006.257.17:34:22.19#ibcon#read 4, iclass 40, count 0 2006.257.17:34:22.19#ibcon#about to read 5, iclass 40, count 0 2006.257.17:34:22.19#ibcon#read 5, iclass 40, count 0 2006.257.17:34:22.19#ibcon#about to read 6, iclass 40, count 0 2006.257.17:34:22.19#ibcon#read 6, iclass 40, count 0 2006.257.17:34:22.19#ibcon#end of sib2, iclass 40, count 0 2006.257.17:34:22.19#ibcon#*after write, iclass 40, count 0 2006.257.17:34:22.19#ibcon#*before return 0, iclass 40, count 0 2006.257.17:34:22.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:22.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:22.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:34:22.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:34:22.19$vck44/valo=3,564.99 2006.257.17:34:22.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.17:34:22.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.17:34:22.19#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:22.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:22.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:22.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:22.19#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:34:22.19#ibcon#first serial, iclass 4, count 0 2006.257.17:34:22.19#ibcon#enter sib2, iclass 4, count 0 2006.257.17:34:22.19#ibcon#flushed, iclass 4, count 0 2006.257.17:34:22.19#ibcon#about to write, iclass 4, count 0 2006.257.17:34:22.19#ibcon#wrote, iclass 4, count 0 2006.257.17:34:22.19#ibcon#about to read 3, iclass 4, count 0 2006.257.17:34:22.21#ibcon#read 3, iclass 4, count 0 2006.257.17:34:22.21#ibcon#about to read 4, iclass 4, count 0 2006.257.17:34:22.21#ibcon#read 4, iclass 4, count 0 2006.257.17:34:22.21#ibcon#about to read 5, iclass 4, count 0 2006.257.17:34:22.21#ibcon#read 5, iclass 4, count 0 2006.257.17:34:22.21#ibcon#about to read 6, iclass 4, count 0 2006.257.17:34:22.21#ibcon#read 6, iclass 4, count 0 2006.257.17:34:22.21#ibcon#end of sib2, iclass 4, count 0 2006.257.17:34:22.21#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:34:22.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:34:22.21#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:34:22.21#ibcon#*before write, iclass 4, count 0 2006.257.17:34:22.21#ibcon#enter sib2, iclass 4, count 0 2006.257.17:34:22.21#ibcon#flushed, iclass 4, count 0 2006.257.17:34:22.21#ibcon#about to write, iclass 4, count 0 2006.257.17:34:22.21#ibcon#wrote, iclass 4, count 0 2006.257.17:34:22.21#ibcon#about to read 3, iclass 4, count 0 2006.257.17:34:22.25#ibcon#read 3, iclass 4, count 0 2006.257.17:34:22.25#ibcon#about to read 4, iclass 4, count 0 2006.257.17:34:22.25#ibcon#read 4, iclass 4, count 0 2006.257.17:34:22.25#ibcon#about to read 5, iclass 4, count 0 2006.257.17:34:22.25#ibcon#read 5, iclass 4, count 0 2006.257.17:34:22.25#ibcon#about to read 6, iclass 4, count 0 2006.257.17:34:22.25#ibcon#read 6, iclass 4, count 0 2006.257.17:34:22.25#ibcon#end of sib2, iclass 4, count 0 2006.257.17:34:22.25#ibcon#*after write, iclass 4, count 0 2006.257.17:34:22.25#ibcon#*before return 0, iclass 4, count 0 2006.257.17:34:22.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:22.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:22.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:34:22.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:34:22.25$vck44/va=3,8 2006.257.17:34:22.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.17:34:22.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.17:34:22.25#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:22.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:22.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:22.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:22.31#ibcon#enter wrdev, iclass 6, count 2 2006.257.17:34:22.31#ibcon#first serial, iclass 6, count 2 2006.257.17:34:22.31#ibcon#enter sib2, iclass 6, count 2 2006.257.17:34:22.31#ibcon#flushed, iclass 6, count 2 2006.257.17:34:22.31#ibcon#about to write, iclass 6, count 2 2006.257.17:34:22.31#ibcon#wrote, iclass 6, count 2 2006.257.17:34:22.31#ibcon#about to read 3, iclass 6, count 2 2006.257.17:34:22.33#ibcon#read 3, iclass 6, count 2 2006.257.17:34:22.33#ibcon#about to read 4, iclass 6, count 2 2006.257.17:34:22.33#ibcon#read 4, iclass 6, count 2 2006.257.17:34:22.33#ibcon#about to read 5, iclass 6, count 2 2006.257.17:34:22.33#ibcon#read 5, iclass 6, count 2 2006.257.17:34:22.33#ibcon#about to read 6, iclass 6, count 2 2006.257.17:34:22.33#ibcon#read 6, iclass 6, count 2 2006.257.17:34:22.33#ibcon#end of sib2, iclass 6, count 2 2006.257.17:34:22.33#ibcon#*mode == 0, iclass 6, count 2 2006.257.17:34:22.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.17:34:22.33#ibcon#[25=AT03-08\r\n] 2006.257.17:34:22.33#ibcon#*before write, iclass 6, count 2 2006.257.17:34:22.33#ibcon#enter sib2, iclass 6, count 2 2006.257.17:34:22.33#ibcon#flushed, iclass 6, count 2 2006.257.17:34:22.33#ibcon#about to write, iclass 6, count 2 2006.257.17:34:22.33#ibcon#wrote, iclass 6, count 2 2006.257.17:34:22.33#ibcon#about to read 3, iclass 6, count 2 2006.257.17:34:22.36#ibcon#read 3, iclass 6, count 2 2006.257.17:34:22.36#ibcon#about to read 4, iclass 6, count 2 2006.257.17:34:22.36#ibcon#read 4, iclass 6, count 2 2006.257.17:34:22.36#ibcon#about to read 5, iclass 6, count 2 2006.257.17:34:22.36#ibcon#read 5, iclass 6, count 2 2006.257.17:34:22.36#ibcon#about to read 6, iclass 6, count 2 2006.257.17:34:22.36#ibcon#read 6, iclass 6, count 2 2006.257.17:34:22.36#ibcon#end of sib2, iclass 6, count 2 2006.257.17:34:22.36#ibcon#*after write, iclass 6, count 2 2006.257.17:34:22.36#ibcon#*before return 0, iclass 6, count 2 2006.257.17:34:22.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:22.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:22.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.17:34:22.36#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:22.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:22.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:22.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:22.48#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:34:22.48#ibcon#first serial, iclass 6, count 0 2006.257.17:34:22.48#ibcon#enter sib2, iclass 6, count 0 2006.257.17:34:22.48#ibcon#flushed, iclass 6, count 0 2006.257.17:34:22.48#ibcon#about to write, iclass 6, count 0 2006.257.17:34:22.48#ibcon#wrote, iclass 6, count 0 2006.257.17:34:22.48#ibcon#about to read 3, iclass 6, count 0 2006.257.17:34:22.50#ibcon#read 3, iclass 6, count 0 2006.257.17:34:22.50#ibcon#about to read 4, iclass 6, count 0 2006.257.17:34:22.50#ibcon#read 4, iclass 6, count 0 2006.257.17:34:22.50#ibcon#about to read 5, iclass 6, count 0 2006.257.17:34:22.50#ibcon#read 5, iclass 6, count 0 2006.257.17:34:22.50#ibcon#about to read 6, iclass 6, count 0 2006.257.17:34:22.50#ibcon#read 6, iclass 6, count 0 2006.257.17:34:22.50#ibcon#end of sib2, iclass 6, count 0 2006.257.17:34:22.50#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:34:22.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:34:22.50#ibcon#[25=USB\r\n] 2006.257.17:34:22.50#ibcon#*before write, iclass 6, count 0 2006.257.17:34:22.50#ibcon#enter sib2, iclass 6, count 0 2006.257.17:34:22.50#ibcon#flushed, iclass 6, count 0 2006.257.17:34:22.50#ibcon#about to write, iclass 6, count 0 2006.257.17:34:22.50#ibcon#wrote, iclass 6, count 0 2006.257.17:34:22.50#ibcon#about to read 3, iclass 6, count 0 2006.257.17:34:22.53#ibcon#read 3, iclass 6, count 0 2006.257.17:34:22.53#ibcon#about to read 4, iclass 6, count 0 2006.257.17:34:22.53#ibcon#read 4, iclass 6, count 0 2006.257.17:34:22.53#ibcon#about to read 5, iclass 6, count 0 2006.257.17:34:22.53#ibcon#read 5, iclass 6, count 0 2006.257.17:34:22.53#ibcon#about to read 6, iclass 6, count 0 2006.257.17:34:22.53#ibcon#read 6, iclass 6, count 0 2006.257.17:34:22.53#ibcon#end of sib2, iclass 6, count 0 2006.257.17:34:22.53#ibcon#*after write, iclass 6, count 0 2006.257.17:34:22.53#ibcon#*before return 0, iclass 6, count 0 2006.257.17:34:22.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:22.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:22.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:34:22.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:34:22.53$vck44/valo=4,624.99 2006.257.17:34:22.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.17:34:22.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.17:34:22.53#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:22.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:22.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:22.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:22.53#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:34:22.53#ibcon#first serial, iclass 10, count 0 2006.257.17:34:22.53#ibcon#enter sib2, iclass 10, count 0 2006.257.17:34:22.53#ibcon#flushed, iclass 10, count 0 2006.257.17:34:22.53#ibcon#about to write, iclass 10, count 0 2006.257.17:34:22.53#ibcon#wrote, iclass 10, count 0 2006.257.17:34:22.53#ibcon#about to read 3, iclass 10, count 0 2006.257.17:34:22.55#ibcon#read 3, iclass 10, count 0 2006.257.17:34:22.55#ibcon#about to read 4, iclass 10, count 0 2006.257.17:34:22.55#ibcon#read 4, iclass 10, count 0 2006.257.17:34:22.55#ibcon#about to read 5, iclass 10, count 0 2006.257.17:34:22.55#ibcon#read 5, iclass 10, count 0 2006.257.17:34:22.55#ibcon#about to read 6, iclass 10, count 0 2006.257.17:34:22.55#ibcon#read 6, iclass 10, count 0 2006.257.17:34:22.55#ibcon#end of sib2, iclass 10, count 0 2006.257.17:34:22.55#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:34:22.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:34:22.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:34:22.55#ibcon#*before write, iclass 10, count 0 2006.257.17:34:22.55#ibcon#enter sib2, iclass 10, count 0 2006.257.17:34:22.55#ibcon#flushed, iclass 10, count 0 2006.257.17:34:22.55#ibcon#about to write, iclass 10, count 0 2006.257.17:34:22.55#ibcon#wrote, iclass 10, count 0 2006.257.17:34:22.55#ibcon#about to read 3, iclass 10, count 0 2006.257.17:34:22.59#ibcon#read 3, iclass 10, count 0 2006.257.17:34:22.59#ibcon#about to read 4, iclass 10, count 0 2006.257.17:34:22.59#ibcon#read 4, iclass 10, count 0 2006.257.17:34:22.59#ibcon#about to read 5, iclass 10, count 0 2006.257.17:34:22.59#ibcon#read 5, iclass 10, count 0 2006.257.17:34:22.59#ibcon#about to read 6, iclass 10, count 0 2006.257.17:34:22.59#ibcon#read 6, iclass 10, count 0 2006.257.17:34:22.59#ibcon#end of sib2, iclass 10, count 0 2006.257.17:34:22.59#ibcon#*after write, iclass 10, count 0 2006.257.17:34:22.59#ibcon#*before return 0, iclass 10, count 0 2006.257.17:34:22.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:22.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:22.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:34:22.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:34:22.59$vck44/va=4,7 2006.257.17:34:22.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.17:34:22.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.17:34:22.59#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:22.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:22.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:22.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:22.65#ibcon#enter wrdev, iclass 12, count 2 2006.257.17:34:22.65#ibcon#first serial, iclass 12, count 2 2006.257.17:34:22.65#ibcon#enter sib2, iclass 12, count 2 2006.257.17:34:22.65#ibcon#flushed, iclass 12, count 2 2006.257.17:34:22.65#ibcon#about to write, iclass 12, count 2 2006.257.17:34:22.65#ibcon#wrote, iclass 12, count 2 2006.257.17:34:22.65#ibcon#about to read 3, iclass 12, count 2 2006.257.17:34:22.67#ibcon#read 3, iclass 12, count 2 2006.257.17:34:22.67#ibcon#about to read 4, iclass 12, count 2 2006.257.17:34:22.67#ibcon#read 4, iclass 12, count 2 2006.257.17:34:22.67#ibcon#about to read 5, iclass 12, count 2 2006.257.17:34:22.67#ibcon#read 5, iclass 12, count 2 2006.257.17:34:22.67#ibcon#about to read 6, iclass 12, count 2 2006.257.17:34:22.67#ibcon#read 6, iclass 12, count 2 2006.257.17:34:22.67#ibcon#end of sib2, iclass 12, count 2 2006.257.17:34:22.67#ibcon#*mode == 0, iclass 12, count 2 2006.257.17:34:22.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.17:34:22.67#ibcon#[25=AT04-07\r\n] 2006.257.17:34:22.67#ibcon#*before write, iclass 12, count 2 2006.257.17:34:22.67#ibcon#enter sib2, iclass 12, count 2 2006.257.17:34:22.67#ibcon#flushed, iclass 12, count 2 2006.257.17:34:22.67#ibcon#about to write, iclass 12, count 2 2006.257.17:34:22.67#ibcon#wrote, iclass 12, count 2 2006.257.17:34:22.67#ibcon#about to read 3, iclass 12, count 2 2006.257.17:34:22.70#ibcon#read 3, iclass 12, count 2 2006.257.17:34:22.70#ibcon#about to read 4, iclass 12, count 2 2006.257.17:34:22.70#ibcon#read 4, iclass 12, count 2 2006.257.17:34:22.70#ibcon#about to read 5, iclass 12, count 2 2006.257.17:34:22.70#ibcon#read 5, iclass 12, count 2 2006.257.17:34:22.70#ibcon#about to read 6, iclass 12, count 2 2006.257.17:34:22.70#ibcon#read 6, iclass 12, count 2 2006.257.17:34:22.70#ibcon#end of sib2, iclass 12, count 2 2006.257.17:34:22.70#ibcon#*after write, iclass 12, count 2 2006.257.17:34:22.70#ibcon#*before return 0, iclass 12, count 2 2006.257.17:34:22.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:22.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:22.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.17:34:22.70#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:22.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:22.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:22.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:22.82#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:34:22.82#ibcon#first serial, iclass 12, count 0 2006.257.17:34:22.82#ibcon#enter sib2, iclass 12, count 0 2006.257.17:34:22.82#ibcon#flushed, iclass 12, count 0 2006.257.17:34:22.82#ibcon#about to write, iclass 12, count 0 2006.257.17:34:22.82#ibcon#wrote, iclass 12, count 0 2006.257.17:34:22.82#ibcon#about to read 3, iclass 12, count 0 2006.257.17:34:22.84#ibcon#read 3, iclass 12, count 0 2006.257.17:34:22.84#ibcon#about to read 4, iclass 12, count 0 2006.257.17:34:22.84#ibcon#read 4, iclass 12, count 0 2006.257.17:34:22.84#ibcon#about to read 5, iclass 12, count 0 2006.257.17:34:22.84#ibcon#read 5, iclass 12, count 0 2006.257.17:34:22.84#ibcon#about to read 6, iclass 12, count 0 2006.257.17:34:22.84#ibcon#read 6, iclass 12, count 0 2006.257.17:34:22.84#ibcon#end of sib2, iclass 12, count 0 2006.257.17:34:22.84#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:34:22.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:34:22.84#ibcon#[25=USB\r\n] 2006.257.17:34:22.84#ibcon#*before write, iclass 12, count 0 2006.257.17:34:22.84#ibcon#enter sib2, iclass 12, count 0 2006.257.17:34:22.84#ibcon#flushed, iclass 12, count 0 2006.257.17:34:22.84#ibcon#about to write, iclass 12, count 0 2006.257.17:34:22.84#ibcon#wrote, iclass 12, count 0 2006.257.17:34:22.84#ibcon#about to read 3, iclass 12, count 0 2006.257.17:34:22.87#ibcon#read 3, iclass 12, count 0 2006.257.17:34:22.87#ibcon#about to read 4, iclass 12, count 0 2006.257.17:34:22.87#ibcon#read 4, iclass 12, count 0 2006.257.17:34:22.87#ibcon#about to read 5, iclass 12, count 0 2006.257.17:34:22.87#ibcon#read 5, iclass 12, count 0 2006.257.17:34:22.87#ibcon#about to read 6, iclass 12, count 0 2006.257.17:34:22.87#ibcon#read 6, iclass 12, count 0 2006.257.17:34:22.87#ibcon#end of sib2, iclass 12, count 0 2006.257.17:34:22.87#ibcon#*after write, iclass 12, count 0 2006.257.17:34:22.87#ibcon#*before return 0, iclass 12, count 0 2006.257.17:34:22.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:22.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:22.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:34:22.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:34:22.87$vck44/valo=5,734.99 2006.257.17:34:22.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.17:34:22.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.17:34:22.87#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:22.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:22.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:22.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:22.87#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:34:22.87#ibcon#first serial, iclass 14, count 0 2006.257.17:34:22.87#ibcon#enter sib2, iclass 14, count 0 2006.257.17:34:22.87#ibcon#flushed, iclass 14, count 0 2006.257.17:34:22.87#ibcon#about to write, iclass 14, count 0 2006.257.17:34:22.87#ibcon#wrote, iclass 14, count 0 2006.257.17:34:22.87#ibcon#about to read 3, iclass 14, count 0 2006.257.17:34:22.89#ibcon#read 3, iclass 14, count 0 2006.257.17:34:22.89#ibcon#about to read 4, iclass 14, count 0 2006.257.17:34:22.89#ibcon#read 4, iclass 14, count 0 2006.257.17:34:22.89#ibcon#about to read 5, iclass 14, count 0 2006.257.17:34:22.89#ibcon#read 5, iclass 14, count 0 2006.257.17:34:22.89#ibcon#about to read 6, iclass 14, count 0 2006.257.17:34:22.89#ibcon#read 6, iclass 14, count 0 2006.257.17:34:22.89#ibcon#end of sib2, iclass 14, count 0 2006.257.17:34:22.89#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:34:22.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:34:22.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:34:22.89#ibcon#*before write, iclass 14, count 0 2006.257.17:34:22.89#ibcon#enter sib2, iclass 14, count 0 2006.257.17:34:22.89#ibcon#flushed, iclass 14, count 0 2006.257.17:34:22.89#ibcon#about to write, iclass 14, count 0 2006.257.17:34:22.89#ibcon#wrote, iclass 14, count 0 2006.257.17:34:22.89#ibcon#about to read 3, iclass 14, count 0 2006.257.17:34:22.93#ibcon#read 3, iclass 14, count 0 2006.257.17:34:22.93#ibcon#about to read 4, iclass 14, count 0 2006.257.17:34:22.93#ibcon#read 4, iclass 14, count 0 2006.257.17:34:22.93#ibcon#about to read 5, iclass 14, count 0 2006.257.17:34:22.93#ibcon#read 5, iclass 14, count 0 2006.257.17:34:22.93#ibcon#about to read 6, iclass 14, count 0 2006.257.17:34:22.93#ibcon#read 6, iclass 14, count 0 2006.257.17:34:22.93#ibcon#end of sib2, iclass 14, count 0 2006.257.17:34:22.93#ibcon#*after write, iclass 14, count 0 2006.257.17:34:22.93#ibcon#*before return 0, iclass 14, count 0 2006.257.17:34:22.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:22.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:22.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:34:22.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:34:22.93$vck44/va=5,4 2006.257.17:34:22.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.17:34:22.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.17:34:22.93#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:22.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:34:22.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:34:22.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:34:22.99#ibcon#enter wrdev, iclass 16, count 2 2006.257.17:34:22.99#ibcon#first serial, iclass 16, count 2 2006.257.17:34:22.99#ibcon#enter sib2, iclass 16, count 2 2006.257.17:34:22.99#ibcon#flushed, iclass 16, count 2 2006.257.17:34:22.99#ibcon#about to write, iclass 16, count 2 2006.257.17:34:22.99#ibcon#wrote, iclass 16, count 2 2006.257.17:34:22.99#ibcon#about to read 3, iclass 16, count 2 2006.257.17:34:23.01#ibcon#read 3, iclass 16, count 2 2006.257.17:34:23.01#ibcon#about to read 4, iclass 16, count 2 2006.257.17:34:23.01#ibcon#read 4, iclass 16, count 2 2006.257.17:34:23.01#ibcon#about to read 5, iclass 16, count 2 2006.257.17:34:23.01#ibcon#read 5, iclass 16, count 2 2006.257.17:34:23.01#ibcon#about to read 6, iclass 16, count 2 2006.257.17:34:23.01#ibcon#read 6, iclass 16, count 2 2006.257.17:34:23.01#ibcon#end of sib2, iclass 16, count 2 2006.257.17:34:23.01#ibcon#*mode == 0, iclass 16, count 2 2006.257.17:34:23.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.17:34:23.01#ibcon#[25=AT05-04\r\n] 2006.257.17:34:23.01#ibcon#*before write, iclass 16, count 2 2006.257.17:34:23.01#ibcon#enter sib2, iclass 16, count 2 2006.257.17:34:23.01#ibcon#flushed, iclass 16, count 2 2006.257.17:34:23.01#ibcon#about to write, iclass 16, count 2 2006.257.17:34:23.01#ibcon#wrote, iclass 16, count 2 2006.257.17:34:23.01#ibcon#about to read 3, iclass 16, count 2 2006.257.17:34:23.04#ibcon#read 3, iclass 16, count 2 2006.257.17:34:23.04#ibcon#about to read 4, iclass 16, count 2 2006.257.17:34:23.04#ibcon#read 4, iclass 16, count 2 2006.257.17:34:23.04#ibcon#about to read 5, iclass 16, count 2 2006.257.17:34:23.04#ibcon#read 5, iclass 16, count 2 2006.257.17:34:23.04#ibcon#about to read 6, iclass 16, count 2 2006.257.17:34:23.04#ibcon#read 6, iclass 16, count 2 2006.257.17:34:23.04#ibcon#end of sib2, iclass 16, count 2 2006.257.17:34:23.04#ibcon#*after write, iclass 16, count 2 2006.257.17:34:23.04#ibcon#*before return 0, iclass 16, count 2 2006.257.17:34:23.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:34:23.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:34:23.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.17:34:23.04#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:23.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:34:23.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:34:23.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:34:23.16#ibcon#enter wrdev, iclass 16, count 0 2006.257.17:34:23.16#ibcon#first serial, iclass 16, count 0 2006.257.17:34:23.16#ibcon#enter sib2, iclass 16, count 0 2006.257.17:34:23.16#ibcon#flushed, iclass 16, count 0 2006.257.17:34:23.16#ibcon#about to write, iclass 16, count 0 2006.257.17:34:23.16#ibcon#wrote, iclass 16, count 0 2006.257.17:34:23.16#ibcon#about to read 3, iclass 16, count 0 2006.257.17:34:23.18#ibcon#read 3, iclass 16, count 0 2006.257.17:34:23.18#ibcon#about to read 4, iclass 16, count 0 2006.257.17:34:23.18#ibcon#read 4, iclass 16, count 0 2006.257.17:34:23.18#ibcon#about to read 5, iclass 16, count 0 2006.257.17:34:23.18#ibcon#read 5, iclass 16, count 0 2006.257.17:34:23.18#ibcon#about to read 6, iclass 16, count 0 2006.257.17:34:23.18#ibcon#read 6, iclass 16, count 0 2006.257.17:34:23.18#ibcon#end of sib2, iclass 16, count 0 2006.257.17:34:23.18#ibcon#*mode == 0, iclass 16, count 0 2006.257.17:34:23.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.17:34:23.18#ibcon#[25=USB\r\n] 2006.257.17:34:23.18#ibcon#*before write, iclass 16, count 0 2006.257.17:34:23.18#ibcon#enter sib2, iclass 16, count 0 2006.257.17:34:23.18#ibcon#flushed, iclass 16, count 0 2006.257.17:34:23.18#ibcon#about to write, iclass 16, count 0 2006.257.17:34:23.18#ibcon#wrote, iclass 16, count 0 2006.257.17:34:23.18#ibcon#about to read 3, iclass 16, count 0 2006.257.17:34:23.21#ibcon#read 3, iclass 16, count 0 2006.257.17:34:23.21#ibcon#about to read 4, iclass 16, count 0 2006.257.17:34:23.21#ibcon#read 4, iclass 16, count 0 2006.257.17:34:23.21#ibcon#about to read 5, iclass 16, count 0 2006.257.17:34:23.21#ibcon#read 5, iclass 16, count 0 2006.257.17:34:23.21#ibcon#about to read 6, iclass 16, count 0 2006.257.17:34:23.21#ibcon#read 6, iclass 16, count 0 2006.257.17:34:23.21#ibcon#end of sib2, iclass 16, count 0 2006.257.17:34:23.21#ibcon#*after write, iclass 16, count 0 2006.257.17:34:23.21#ibcon#*before return 0, iclass 16, count 0 2006.257.17:34:23.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:34:23.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:34:23.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.17:34:23.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.17:34:23.21$vck44/valo=6,814.99 2006.257.17:34:23.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.17:34:23.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.17:34:23.21#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:23.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:34:23.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:34:23.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:34:23.21#ibcon#enter wrdev, iclass 18, count 0 2006.257.17:34:23.21#ibcon#first serial, iclass 18, count 0 2006.257.17:34:23.21#ibcon#enter sib2, iclass 18, count 0 2006.257.17:34:23.21#ibcon#flushed, iclass 18, count 0 2006.257.17:34:23.21#ibcon#about to write, iclass 18, count 0 2006.257.17:34:23.21#ibcon#wrote, iclass 18, count 0 2006.257.17:34:23.21#ibcon#about to read 3, iclass 18, count 0 2006.257.17:34:23.23#ibcon#read 3, iclass 18, count 0 2006.257.17:34:23.23#ibcon#about to read 4, iclass 18, count 0 2006.257.17:34:23.23#ibcon#read 4, iclass 18, count 0 2006.257.17:34:23.23#ibcon#about to read 5, iclass 18, count 0 2006.257.17:34:23.23#ibcon#read 5, iclass 18, count 0 2006.257.17:34:23.23#ibcon#about to read 6, iclass 18, count 0 2006.257.17:34:23.23#ibcon#read 6, iclass 18, count 0 2006.257.17:34:23.23#ibcon#end of sib2, iclass 18, count 0 2006.257.17:34:23.23#ibcon#*mode == 0, iclass 18, count 0 2006.257.17:34:23.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.17:34:23.23#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:34:23.23#ibcon#*before write, iclass 18, count 0 2006.257.17:34:23.23#ibcon#enter sib2, iclass 18, count 0 2006.257.17:34:23.23#ibcon#flushed, iclass 18, count 0 2006.257.17:34:23.23#ibcon#about to write, iclass 18, count 0 2006.257.17:34:23.23#ibcon#wrote, iclass 18, count 0 2006.257.17:34:23.23#ibcon#about to read 3, iclass 18, count 0 2006.257.17:34:23.27#ibcon#read 3, iclass 18, count 0 2006.257.17:34:23.27#ibcon#about to read 4, iclass 18, count 0 2006.257.17:34:23.27#ibcon#read 4, iclass 18, count 0 2006.257.17:34:23.27#ibcon#about to read 5, iclass 18, count 0 2006.257.17:34:23.27#ibcon#read 5, iclass 18, count 0 2006.257.17:34:23.27#ibcon#about to read 6, iclass 18, count 0 2006.257.17:34:23.27#ibcon#read 6, iclass 18, count 0 2006.257.17:34:23.27#ibcon#end of sib2, iclass 18, count 0 2006.257.17:34:23.27#ibcon#*after write, iclass 18, count 0 2006.257.17:34:23.27#ibcon#*before return 0, iclass 18, count 0 2006.257.17:34:23.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:34:23.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:34:23.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.17:34:23.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.17:34:23.27$vck44/va=6,4 2006.257.17:34:23.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.17:34:23.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.17:34:23.27#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:23.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:34:23.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:34:23.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:34:23.33#ibcon#enter wrdev, iclass 20, count 2 2006.257.17:34:23.33#ibcon#first serial, iclass 20, count 2 2006.257.17:34:23.33#ibcon#enter sib2, iclass 20, count 2 2006.257.17:34:23.33#ibcon#flushed, iclass 20, count 2 2006.257.17:34:23.33#ibcon#about to write, iclass 20, count 2 2006.257.17:34:23.33#ibcon#wrote, iclass 20, count 2 2006.257.17:34:23.33#ibcon#about to read 3, iclass 20, count 2 2006.257.17:34:23.35#ibcon#read 3, iclass 20, count 2 2006.257.17:34:23.35#ibcon#about to read 4, iclass 20, count 2 2006.257.17:34:23.35#ibcon#read 4, iclass 20, count 2 2006.257.17:34:23.35#ibcon#about to read 5, iclass 20, count 2 2006.257.17:34:23.35#ibcon#read 5, iclass 20, count 2 2006.257.17:34:23.35#ibcon#about to read 6, iclass 20, count 2 2006.257.17:34:23.35#ibcon#read 6, iclass 20, count 2 2006.257.17:34:23.35#ibcon#end of sib2, iclass 20, count 2 2006.257.17:34:23.35#ibcon#*mode == 0, iclass 20, count 2 2006.257.17:34:23.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.17:34:23.35#ibcon#[25=AT06-04\r\n] 2006.257.17:34:23.35#ibcon#*before write, iclass 20, count 2 2006.257.17:34:23.35#ibcon#enter sib2, iclass 20, count 2 2006.257.17:34:23.35#ibcon#flushed, iclass 20, count 2 2006.257.17:34:23.35#ibcon#about to write, iclass 20, count 2 2006.257.17:34:23.35#ibcon#wrote, iclass 20, count 2 2006.257.17:34:23.35#ibcon#about to read 3, iclass 20, count 2 2006.257.17:34:23.38#ibcon#read 3, iclass 20, count 2 2006.257.17:34:23.38#ibcon#about to read 4, iclass 20, count 2 2006.257.17:34:23.38#ibcon#read 4, iclass 20, count 2 2006.257.17:34:23.38#ibcon#about to read 5, iclass 20, count 2 2006.257.17:34:23.38#ibcon#read 5, iclass 20, count 2 2006.257.17:34:23.38#ibcon#about to read 6, iclass 20, count 2 2006.257.17:34:23.38#ibcon#read 6, iclass 20, count 2 2006.257.17:34:23.38#ibcon#end of sib2, iclass 20, count 2 2006.257.17:34:23.38#ibcon#*after write, iclass 20, count 2 2006.257.17:34:23.38#ibcon#*before return 0, iclass 20, count 2 2006.257.17:34:23.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:34:23.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:34:23.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.17:34:23.38#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:23.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:34:23.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:34:23.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:34:23.50#ibcon#enter wrdev, iclass 20, count 0 2006.257.17:34:23.50#ibcon#first serial, iclass 20, count 0 2006.257.17:34:23.50#ibcon#enter sib2, iclass 20, count 0 2006.257.17:34:23.50#ibcon#flushed, iclass 20, count 0 2006.257.17:34:23.50#ibcon#about to write, iclass 20, count 0 2006.257.17:34:23.50#ibcon#wrote, iclass 20, count 0 2006.257.17:34:23.50#ibcon#about to read 3, iclass 20, count 0 2006.257.17:34:23.52#ibcon#read 3, iclass 20, count 0 2006.257.17:34:23.52#ibcon#about to read 4, iclass 20, count 0 2006.257.17:34:23.52#ibcon#read 4, iclass 20, count 0 2006.257.17:34:23.52#ibcon#about to read 5, iclass 20, count 0 2006.257.17:34:23.52#ibcon#read 5, iclass 20, count 0 2006.257.17:34:23.52#ibcon#about to read 6, iclass 20, count 0 2006.257.17:34:23.52#ibcon#read 6, iclass 20, count 0 2006.257.17:34:23.52#ibcon#end of sib2, iclass 20, count 0 2006.257.17:34:23.52#ibcon#*mode == 0, iclass 20, count 0 2006.257.17:34:23.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.17:34:23.52#ibcon#[25=USB\r\n] 2006.257.17:34:23.52#ibcon#*before write, iclass 20, count 0 2006.257.17:34:23.52#ibcon#enter sib2, iclass 20, count 0 2006.257.17:34:23.52#ibcon#flushed, iclass 20, count 0 2006.257.17:34:23.52#ibcon#about to write, iclass 20, count 0 2006.257.17:34:23.52#ibcon#wrote, iclass 20, count 0 2006.257.17:34:23.52#ibcon#about to read 3, iclass 20, count 0 2006.257.17:34:23.55#ibcon#read 3, iclass 20, count 0 2006.257.17:34:23.55#ibcon#about to read 4, iclass 20, count 0 2006.257.17:34:23.55#ibcon#read 4, iclass 20, count 0 2006.257.17:34:23.55#ibcon#about to read 5, iclass 20, count 0 2006.257.17:34:23.55#ibcon#read 5, iclass 20, count 0 2006.257.17:34:23.55#ibcon#about to read 6, iclass 20, count 0 2006.257.17:34:23.55#ibcon#read 6, iclass 20, count 0 2006.257.17:34:23.55#ibcon#end of sib2, iclass 20, count 0 2006.257.17:34:23.55#ibcon#*after write, iclass 20, count 0 2006.257.17:34:23.55#ibcon#*before return 0, iclass 20, count 0 2006.257.17:34:23.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:34:23.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:34:23.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.17:34:23.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.17:34:23.55$vck44/valo=7,864.99 2006.257.17:34:23.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.17:34:23.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.17:34:23.55#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:23.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:23.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:23.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:23.55#ibcon#enter wrdev, iclass 22, count 0 2006.257.17:34:23.55#ibcon#first serial, iclass 22, count 0 2006.257.17:34:23.55#ibcon#enter sib2, iclass 22, count 0 2006.257.17:34:23.55#ibcon#flushed, iclass 22, count 0 2006.257.17:34:23.55#ibcon#about to write, iclass 22, count 0 2006.257.17:34:23.55#ibcon#wrote, iclass 22, count 0 2006.257.17:34:23.55#ibcon#about to read 3, iclass 22, count 0 2006.257.17:34:23.57#ibcon#read 3, iclass 22, count 0 2006.257.17:34:23.57#ibcon#about to read 4, iclass 22, count 0 2006.257.17:34:23.57#ibcon#read 4, iclass 22, count 0 2006.257.17:34:23.57#ibcon#about to read 5, iclass 22, count 0 2006.257.17:34:23.57#ibcon#read 5, iclass 22, count 0 2006.257.17:34:23.57#ibcon#about to read 6, iclass 22, count 0 2006.257.17:34:23.57#ibcon#read 6, iclass 22, count 0 2006.257.17:34:23.57#ibcon#end of sib2, iclass 22, count 0 2006.257.17:34:23.57#ibcon#*mode == 0, iclass 22, count 0 2006.257.17:34:23.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.17:34:23.57#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:34:23.57#ibcon#*before write, iclass 22, count 0 2006.257.17:34:23.57#ibcon#enter sib2, iclass 22, count 0 2006.257.17:34:23.57#ibcon#flushed, iclass 22, count 0 2006.257.17:34:23.57#ibcon#about to write, iclass 22, count 0 2006.257.17:34:23.57#ibcon#wrote, iclass 22, count 0 2006.257.17:34:23.57#ibcon#about to read 3, iclass 22, count 0 2006.257.17:34:23.61#ibcon#read 3, iclass 22, count 0 2006.257.17:34:23.61#ibcon#about to read 4, iclass 22, count 0 2006.257.17:34:23.61#ibcon#read 4, iclass 22, count 0 2006.257.17:34:23.61#ibcon#about to read 5, iclass 22, count 0 2006.257.17:34:23.61#ibcon#read 5, iclass 22, count 0 2006.257.17:34:23.61#ibcon#about to read 6, iclass 22, count 0 2006.257.17:34:23.61#ibcon#read 6, iclass 22, count 0 2006.257.17:34:23.61#ibcon#end of sib2, iclass 22, count 0 2006.257.17:34:23.61#ibcon#*after write, iclass 22, count 0 2006.257.17:34:23.61#ibcon#*before return 0, iclass 22, count 0 2006.257.17:34:23.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:23.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:23.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.17:34:23.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.17:34:23.61$vck44/va=7,4 2006.257.17:34:23.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.17:34:23.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.17:34:23.61#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:23.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:23.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:23.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:23.67#ibcon#enter wrdev, iclass 24, count 2 2006.257.17:34:23.67#ibcon#first serial, iclass 24, count 2 2006.257.17:34:23.67#ibcon#enter sib2, iclass 24, count 2 2006.257.17:34:23.67#ibcon#flushed, iclass 24, count 2 2006.257.17:34:23.67#ibcon#about to write, iclass 24, count 2 2006.257.17:34:23.67#ibcon#wrote, iclass 24, count 2 2006.257.17:34:23.67#ibcon#about to read 3, iclass 24, count 2 2006.257.17:34:23.69#ibcon#read 3, iclass 24, count 2 2006.257.17:34:23.69#ibcon#about to read 4, iclass 24, count 2 2006.257.17:34:23.69#ibcon#read 4, iclass 24, count 2 2006.257.17:34:23.69#ibcon#about to read 5, iclass 24, count 2 2006.257.17:34:23.69#ibcon#read 5, iclass 24, count 2 2006.257.17:34:23.69#ibcon#about to read 6, iclass 24, count 2 2006.257.17:34:23.69#ibcon#read 6, iclass 24, count 2 2006.257.17:34:23.69#ibcon#end of sib2, iclass 24, count 2 2006.257.17:34:23.69#ibcon#*mode == 0, iclass 24, count 2 2006.257.17:34:23.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.17:34:23.69#ibcon#[25=AT07-04\r\n] 2006.257.17:34:23.69#ibcon#*before write, iclass 24, count 2 2006.257.17:34:23.69#ibcon#enter sib2, iclass 24, count 2 2006.257.17:34:23.69#ibcon#flushed, iclass 24, count 2 2006.257.17:34:23.69#ibcon#about to write, iclass 24, count 2 2006.257.17:34:23.69#ibcon#wrote, iclass 24, count 2 2006.257.17:34:23.69#ibcon#about to read 3, iclass 24, count 2 2006.257.17:34:23.72#ibcon#read 3, iclass 24, count 2 2006.257.17:34:23.72#ibcon#about to read 4, iclass 24, count 2 2006.257.17:34:23.72#ibcon#read 4, iclass 24, count 2 2006.257.17:34:23.72#ibcon#about to read 5, iclass 24, count 2 2006.257.17:34:23.72#ibcon#read 5, iclass 24, count 2 2006.257.17:34:23.72#ibcon#about to read 6, iclass 24, count 2 2006.257.17:34:23.72#ibcon#read 6, iclass 24, count 2 2006.257.17:34:23.72#ibcon#end of sib2, iclass 24, count 2 2006.257.17:34:23.72#ibcon#*after write, iclass 24, count 2 2006.257.17:34:23.72#ibcon#*before return 0, iclass 24, count 2 2006.257.17:34:23.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:23.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:23.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.17:34:23.72#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:23.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:23.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:23.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:23.84#ibcon#enter wrdev, iclass 24, count 0 2006.257.17:34:23.84#ibcon#first serial, iclass 24, count 0 2006.257.17:34:23.84#ibcon#enter sib2, iclass 24, count 0 2006.257.17:34:23.84#ibcon#flushed, iclass 24, count 0 2006.257.17:34:23.84#ibcon#about to write, iclass 24, count 0 2006.257.17:34:23.84#ibcon#wrote, iclass 24, count 0 2006.257.17:34:23.84#ibcon#about to read 3, iclass 24, count 0 2006.257.17:34:23.86#ibcon#read 3, iclass 24, count 0 2006.257.17:34:23.86#ibcon#about to read 4, iclass 24, count 0 2006.257.17:34:23.86#ibcon#read 4, iclass 24, count 0 2006.257.17:34:23.86#ibcon#about to read 5, iclass 24, count 0 2006.257.17:34:23.86#ibcon#read 5, iclass 24, count 0 2006.257.17:34:23.86#ibcon#about to read 6, iclass 24, count 0 2006.257.17:34:23.86#ibcon#read 6, iclass 24, count 0 2006.257.17:34:23.86#ibcon#end of sib2, iclass 24, count 0 2006.257.17:34:23.86#ibcon#*mode == 0, iclass 24, count 0 2006.257.17:34:23.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.17:34:23.86#ibcon#[25=USB\r\n] 2006.257.17:34:23.86#ibcon#*before write, iclass 24, count 0 2006.257.17:34:23.86#ibcon#enter sib2, iclass 24, count 0 2006.257.17:34:23.86#ibcon#flushed, iclass 24, count 0 2006.257.17:34:23.86#ibcon#about to write, iclass 24, count 0 2006.257.17:34:23.86#ibcon#wrote, iclass 24, count 0 2006.257.17:34:23.86#ibcon#about to read 3, iclass 24, count 0 2006.257.17:34:23.89#ibcon#read 3, iclass 24, count 0 2006.257.17:34:23.89#ibcon#about to read 4, iclass 24, count 0 2006.257.17:34:23.89#ibcon#read 4, iclass 24, count 0 2006.257.17:34:23.89#ibcon#about to read 5, iclass 24, count 0 2006.257.17:34:23.89#ibcon#read 5, iclass 24, count 0 2006.257.17:34:23.89#ibcon#about to read 6, iclass 24, count 0 2006.257.17:34:23.89#ibcon#read 6, iclass 24, count 0 2006.257.17:34:23.89#ibcon#end of sib2, iclass 24, count 0 2006.257.17:34:23.89#ibcon#*after write, iclass 24, count 0 2006.257.17:34:23.89#ibcon#*before return 0, iclass 24, count 0 2006.257.17:34:23.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:23.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:23.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.17:34:23.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.17:34:23.89$vck44/valo=8,884.99 2006.257.17:34:23.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.17:34:23.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.17:34:23.89#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:23.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:23.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:23.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:23.89#ibcon#enter wrdev, iclass 26, count 0 2006.257.17:34:23.89#ibcon#first serial, iclass 26, count 0 2006.257.17:34:23.89#ibcon#enter sib2, iclass 26, count 0 2006.257.17:34:23.89#ibcon#flushed, iclass 26, count 0 2006.257.17:34:23.89#ibcon#about to write, iclass 26, count 0 2006.257.17:34:23.89#ibcon#wrote, iclass 26, count 0 2006.257.17:34:23.89#ibcon#about to read 3, iclass 26, count 0 2006.257.17:34:23.91#ibcon#read 3, iclass 26, count 0 2006.257.17:34:23.91#ibcon#about to read 4, iclass 26, count 0 2006.257.17:34:23.91#ibcon#read 4, iclass 26, count 0 2006.257.17:34:23.91#ibcon#about to read 5, iclass 26, count 0 2006.257.17:34:23.91#ibcon#read 5, iclass 26, count 0 2006.257.17:34:23.91#ibcon#about to read 6, iclass 26, count 0 2006.257.17:34:23.91#ibcon#read 6, iclass 26, count 0 2006.257.17:34:23.91#ibcon#end of sib2, iclass 26, count 0 2006.257.17:34:23.91#ibcon#*mode == 0, iclass 26, count 0 2006.257.17:34:23.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.17:34:23.91#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:34:23.91#ibcon#*before write, iclass 26, count 0 2006.257.17:34:23.91#ibcon#enter sib2, iclass 26, count 0 2006.257.17:34:23.91#ibcon#flushed, iclass 26, count 0 2006.257.17:34:23.91#ibcon#about to write, iclass 26, count 0 2006.257.17:34:23.91#ibcon#wrote, iclass 26, count 0 2006.257.17:34:23.91#ibcon#about to read 3, iclass 26, count 0 2006.257.17:34:23.95#ibcon#read 3, iclass 26, count 0 2006.257.17:34:23.95#ibcon#about to read 4, iclass 26, count 0 2006.257.17:34:23.95#ibcon#read 4, iclass 26, count 0 2006.257.17:34:23.95#ibcon#about to read 5, iclass 26, count 0 2006.257.17:34:23.95#ibcon#read 5, iclass 26, count 0 2006.257.17:34:23.95#ibcon#about to read 6, iclass 26, count 0 2006.257.17:34:23.95#ibcon#read 6, iclass 26, count 0 2006.257.17:34:23.95#ibcon#end of sib2, iclass 26, count 0 2006.257.17:34:23.95#ibcon#*after write, iclass 26, count 0 2006.257.17:34:23.95#ibcon#*before return 0, iclass 26, count 0 2006.257.17:34:23.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:23.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:23.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.17:34:23.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.17:34:23.95$vck44/va=8,4 2006.257.17:34:23.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.17:34:23.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.17:34:23.95#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:23.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:24.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:24.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:24.01#ibcon#enter wrdev, iclass 28, count 2 2006.257.17:34:24.01#ibcon#first serial, iclass 28, count 2 2006.257.17:34:24.01#ibcon#enter sib2, iclass 28, count 2 2006.257.17:34:24.01#ibcon#flushed, iclass 28, count 2 2006.257.17:34:24.01#ibcon#about to write, iclass 28, count 2 2006.257.17:34:24.01#ibcon#wrote, iclass 28, count 2 2006.257.17:34:24.01#ibcon#about to read 3, iclass 28, count 2 2006.257.17:34:24.03#ibcon#read 3, iclass 28, count 2 2006.257.17:34:24.03#ibcon#about to read 4, iclass 28, count 2 2006.257.17:34:24.03#ibcon#read 4, iclass 28, count 2 2006.257.17:34:24.03#ibcon#about to read 5, iclass 28, count 2 2006.257.17:34:24.03#ibcon#read 5, iclass 28, count 2 2006.257.17:34:24.03#ibcon#about to read 6, iclass 28, count 2 2006.257.17:34:24.03#ibcon#read 6, iclass 28, count 2 2006.257.17:34:24.03#ibcon#end of sib2, iclass 28, count 2 2006.257.17:34:24.03#ibcon#*mode == 0, iclass 28, count 2 2006.257.17:34:24.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.17:34:24.03#ibcon#[25=AT08-04\r\n] 2006.257.17:34:24.03#ibcon#*before write, iclass 28, count 2 2006.257.17:34:24.03#ibcon#enter sib2, iclass 28, count 2 2006.257.17:34:24.03#ibcon#flushed, iclass 28, count 2 2006.257.17:34:24.03#ibcon#about to write, iclass 28, count 2 2006.257.17:34:24.03#ibcon#wrote, iclass 28, count 2 2006.257.17:34:24.03#ibcon#about to read 3, iclass 28, count 2 2006.257.17:34:24.06#ibcon#read 3, iclass 28, count 2 2006.257.17:34:24.06#ibcon#about to read 4, iclass 28, count 2 2006.257.17:34:24.06#ibcon#read 4, iclass 28, count 2 2006.257.17:34:24.06#ibcon#about to read 5, iclass 28, count 2 2006.257.17:34:24.06#ibcon#read 5, iclass 28, count 2 2006.257.17:34:24.06#ibcon#about to read 6, iclass 28, count 2 2006.257.17:34:24.06#ibcon#read 6, iclass 28, count 2 2006.257.17:34:24.06#ibcon#end of sib2, iclass 28, count 2 2006.257.17:34:24.06#ibcon#*after write, iclass 28, count 2 2006.257.17:34:24.06#ibcon#*before return 0, iclass 28, count 2 2006.257.17:34:24.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:24.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:24.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.17:34:24.06#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:24.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:24.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:24.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:24.18#ibcon#enter wrdev, iclass 28, count 0 2006.257.17:34:24.18#ibcon#first serial, iclass 28, count 0 2006.257.17:34:24.18#ibcon#enter sib2, iclass 28, count 0 2006.257.17:34:24.18#ibcon#flushed, iclass 28, count 0 2006.257.17:34:24.18#ibcon#about to write, iclass 28, count 0 2006.257.17:34:24.18#ibcon#wrote, iclass 28, count 0 2006.257.17:34:24.18#ibcon#about to read 3, iclass 28, count 0 2006.257.17:34:24.20#ibcon#read 3, iclass 28, count 0 2006.257.17:34:24.20#ibcon#about to read 4, iclass 28, count 0 2006.257.17:34:24.20#ibcon#read 4, iclass 28, count 0 2006.257.17:34:24.20#ibcon#about to read 5, iclass 28, count 0 2006.257.17:34:24.20#ibcon#read 5, iclass 28, count 0 2006.257.17:34:24.20#ibcon#about to read 6, iclass 28, count 0 2006.257.17:34:24.20#ibcon#read 6, iclass 28, count 0 2006.257.17:34:24.20#ibcon#end of sib2, iclass 28, count 0 2006.257.17:34:24.20#ibcon#*mode == 0, iclass 28, count 0 2006.257.17:34:24.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.17:34:24.20#ibcon#[25=USB\r\n] 2006.257.17:34:24.20#ibcon#*before write, iclass 28, count 0 2006.257.17:34:24.20#ibcon#enter sib2, iclass 28, count 0 2006.257.17:34:24.20#ibcon#flushed, iclass 28, count 0 2006.257.17:34:24.20#ibcon#about to write, iclass 28, count 0 2006.257.17:34:24.20#ibcon#wrote, iclass 28, count 0 2006.257.17:34:24.20#ibcon#about to read 3, iclass 28, count 0 2006.257.17:34:24.23#ibcon#read 3, iclass 28, count 0 2006.257.17:34:24.23#ibcon#about to read 4, iclass 28, count 0 2006.257.17:34:24.23#ibcon#read 4, iclass 28, count 0 2006.257.17:34:24.23#ibcon#about to read 5, iclass 28, count 0 2006.257.17:34:24.23#ibcon#read 5, iclass 28, count 0 2006.257.17:34:24.23#ibcon#about to read 6, iclass 28, count 0 2006.257.17:34:24.23#ibcon#read 6, iclass 28, count 0 2006.257.17:34:24.23#ibcon#end of sib2, iclass 28, count 0 2006.257.17:34:24.23#ibcon#*after write, iclass 28, count 0 2006.257.17:34:24.23#ibcon#*before return 0, iclass 28, count 0 2006.257.17:34:24.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:24.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:24.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.17:34:24.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.17:34:24.23$vck44/vblo=1,629.99 2006.257.17:34:24.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.17:34:24.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.17:34:24.23#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:24.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:24.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:24.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:24.23#ibcon#enter wrdev, iclass 30, count 0 2006.257.17:34:24.23#ibcon#first serial, iclass 30, count 0 2006.257.17:34:24.23#ibcon#enter sib2, iclass 30, count 0 2006.257.17:34:24.23#ibcon#flushed, iclass 30, count 0 2006.257.17:34:24.23#ibcon#about to write, iclass 30, count 0 2006.257.17:34:24.23#ibcon#wrote, iclass 30, count 0 2006.257.17:34:24.23#ibcon#about to read 3, iclass 30, count 0 2006.257.17:34:24.25#ibcon#read 3, iclass 30, count 0 2006.257.17:34:24.25#ibcon#about to read 4, iclass 30, count 0 2006.257.17:34:24.25#ibcon#read 4, iclass 30, count 0 2006.257.17:34:24.25#ibcon#about to read 5, iclass 30, count 0 2006.257.17:34:24.25#ibcon#read 5, iclass 30, count 0 2006.257.17:34:24.25#ibcon#about to read 6, iclass 30, count 0 2006.257.17:34:24.25#ibcon#read 6, iclass 30, count 0 2006.257.17:34:24.25#ibcon#end of sib2, iclass 30, count 0 2006.257.17:34:24.25#ibcon#*mode == 0, iclass 30, count 0 2006.257.17:34:24.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.17:34:24.25#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:34:24.25#ibcon#*before write, iclass 30, count 0 2006.257.17:34:24.25#ibcon#enter sib2, iclass 30, count 0 2006.257.17:34:24.25#ibcon#flushed, iclass 30, count 0 2006.257.17:34:24.25#ibcon#about to write, iclass 30, count 0 2006.257.17:34:24.25#ibcon#wrote, iclass 30, count 0 2006.257.17:34:24.25#ibcon#about to read 3, iclass 30, count 0 2006.257.17:34:24.29#ibcon#read 3, iclass 30, count 0 2006.257.17:34:24.29#ibcon#about to read 4, iclass 30, count 0 2006.257.17:34:24.29#ibcon#read 4, iclass 30, count 0 2006.257.17:34:24.29#ibcon#about to read 5, iclass 30, count 0 2006.257.17:34:24.29#ibcon#read 5, iclass 30, count 0 2006.257.17:34:24.29#ibcon#about to read 6, iclass 30, count 0 2006.257.17:34:24.29#ibcon#read 6, iclass 30, count 0 2006.257.17:34:24.29#ibcon#end of sib2, iclass 30, count 0 2006.257.17:34:24.29#ibcon#*after write, iclass 30, count 0 2006.257.17:34:24.29#ibcon#*before return 0, iclass 30, count 0 2006.257.17:34:24.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:24.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:24.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.17:34:24.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.17:34:24.29$vck44/vb=1,4 2006.257.17:34:24.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.17:34:24.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.17:34:24.29#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:24.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:34:24.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:34:24.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:34:24.29#ibcon#enter wrdev, iclass 32, count 2 2006.257.17:34:24.29#ibcon#first serial, iclass 32, count 2 2006.257.17:34:24.29#ibcon#enter sib2, iclass 32, count 2 2006.257.17:34:24.29#ibcon#flushed, iclass 32, count 2 2006.257.17:34:24.29#ibcon#about to write, iclass 32, count 2 2006.257.17:34:24.29#ibcon#wrote, iclass 32, count 2 2006.257.17:34:24.29#ibcon#about to read 3, iclass 32, count 2 2006.257.17:34:24.31#ibcon#read 3, iclass 32, count 2 2006.257.17:34:24.31#ibcon#about to read 4, iclass 32, count 2 2006.257.17:34:24.31#ibcon#read 4, iclass 32, count 2 2006.257.17:34:24.31#ibcon#about to read 5, iclass 32, count 2 2006.257.17:34:24.31#ibcon#read 5, iclass 32, count 2 2006.257.17:34:24.31#ibcon#about to read 6, iclass 32, count 2 2006.257.17:34:24.31#ibcon#read 6, iclass 32, count 2 2006.257.17:34:24.31#ibcon#end of sib2, iclass 32, count 2 2006.257.17:34:24.31#ibcon#*mode == 0, iclass 32, count 2 2006.257.17:34:24.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.17:34:24.31#ibcon#[27=AT01-04\r\n] 2006.257.17:34:24.31#ibcon#*before write, iclass 32, count 2 2006.257.17:34:24.31#ibcon#enter sib2, iclass 32, count 2 2006.257.17:34:24.31#ibcon#flushed, iclass 32, count 2 2006.257.17:34:24.31#ibcon#about to write, iclass 32, count 2 2006.257.17:34:24.31#ibcon#wrote, iclass 32, count 2 2006.257.17:34:24.31#ibcon#about to read 3, iclass 32, count 2 2006.257.17:34:24.34#ibcon#read 3, iclass 32, count 2 2006.257.17:34:24.34#ibcon#about to read 4, iclass 32, count 2 2006.257.17:34:24.34#ibcon#read 4, iclass 32, count 2 2006.257.17:34:24.34#ibcon#about to read 5, iclass 32, count 2 2006.257.17:34:24.34#ibcon#read 5, iclass 32, count 2 2006.257.17:34:24.34#ibcon#about to read 6, iclass 32, count 2 2006.257.17:34:24.34#ibcon#read 6, iclass 32, count 2 2006.257.17:34:24.34#ibcon#end of sib2, iclass 32, count 2 2006.257.17:34:24.34#ibcon#*after write, iclass 32, count 2 2006.257.17:34:24.34#ibcon#*before return 0, iclass 32, count 2 2006.257.17:34:24.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:34:24.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:34:24.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.17:34:24.34#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:24.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:34:24.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:34:24.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:34:24.46#ibcon#enter wrdev, iclass 32, count 0 2006.257.17:34:24.46#ibcon#first serial, iclass 32, count 0 2006.257.17:34:24.46#ibcon#enter sib2, iclass 32, count 0 2006.257.17:34:24.46#ibcon#flushed, iclass 32, count 0 2006.257.17:34:24.46#ibcon#about to write, iclass 32, count 0 2006.257.17:34:24.46#ibcon#wrote, iclass 32, count 0 2006.257.17:34:24.46#ibcon#about to read 3, iclass 32, count 0 2006.257.17:34:24.48#ibcon#read 3, iclass 32, count 0 2006.257.17:34:24.48#ibcon#about to read 4, iclass 32, count 0 2006.257.17:34:24.48#ibcon#read 4, iclass 32, count 0 2006.257.17:34:24.48#ibcon#about to read 5, iclass 32, count 0 2006.257.17:34:24.48#ibcon#read 5, iclass 32, count 0 2006.257.17:34:24.48#ibcon#about to read 6, iclass 32, count 0 2006.257.17:34:24.48#ibcon#read 6, iclass 32, count 0 2006.257.17:34:24.48#ibcon#end of sib2, iclass 32, count 0 2006.257.17:34:24.48#ibcon#*mode == 0, iclass 32, count 0 2006.257.17:34:24.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.17:34:24.48#ibcon#[27=USB\r\n] 2006.257.17:34:24.48#ibcon#*before write, iclass 32, count 0 2006.257.17:34:24.48#ibcon#enter sib2, iclass 32, count 0 2006.257.17:34:24.48#ibcon#flushed, iclass 32, count 0 2006.257.17:34:24.48#ibcon#about to write, iclass 32, count 0 2006.257.17:34:24.48#ibcon#wrote, iclass 32, count 0 2006.257.17:34:24.48#ibcon#about to read 3, iclass 32, count 0 2006.257.17:34:24.51#ibcon#read 3, iclass 32, count 0 2006.257.17:34:24.51#ibcon#about to read 4, iclass 32, count 0 2006.257.17:34:24.51#ibcon#read 4, iclass 32, count 0 2006.257.17:34:24.51#ibcon#about to read 5, iclass 32, count 0 2006.257.17:34:24.51#ibcon#read 5, iclass 32, count 0 2006.257.17:34:24.51#ibcon#about to read 6, iclass 32, count 0 2006.257.17:34:24.51#ibcon#read 6, iclass 32, count 0 2006.257.17:34:24.51#ibcon#end of sib2, iclass 32, count 0 2006.257.17:34:24.51#ibcon#*after write, iclass 32, count 0 2006.257.17:34:24.51#ibcon#*before return 0, iclass 32, count 0 2006.257.17:34:24.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:34:24.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:34:24.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.17:34:24.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.17:34:24.51$vck44/vblo=2,634.99 2006.257.17:34:24.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.17:34:24.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.17:34:24.51#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:24.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:24.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:24.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:24.51#ibcon#enter wrdev, iclass 34, count 0 2006.257.17:34:24.51#ibcon#first serial, iclass 34, count 0 2006.257.17:34:24.51#ibcon#enter sib2, iclass 34, count 0 2006.257.17:34:24.51#ibcon#flushed, iclass 34, count 0 2006.257.17:34:24.51#ibcon#about to write, iclass 34, count 0 2006.257.17:34:24.51#ibcon#wrote, iclass 34, count 0 2006.257.17:34:24.51#ibcon#about to read 3, iclass 34, count 0 2006.257.17:34:24.53#ibcon#read 3, iclass 34, count 0 2006.257.17:34:24.53#ibcon#about to read 4, iclass 34, count 0 2006.257.17:34:24.53#ibcon#read 4, iclass 34, count 0 2006.257.17:34:24.53#ibcon#about to read 5, iclass 34, count 0 2006.257.17:34:24.53#ibcon#read 5, iclass 34, count 0 2006.257.17:34:24.53#ibcon#about to read 6, iclass 34, count 0 2006.257.17:34:24.53#ibcon#read 6, iclass 34, count 0 2006.257.17:34:24.53#ibcon#end of sib2, iclass 34, count 0 2006.257.17:34:24.53#ibcon#*mode == 0, iclass 34, count 0 2006.257.17:34:24.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.17:34:24.53#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:34:24.53#ibcon#*before write, iclass 34, count 0 2006.257.17:34:24.53#ibcon#enter sib2, iclass 34, count 0 2006.257.17:34:24.53#ibcon#flushed, iclass 34, count 0 2006.257.17:34:24.53#ibcon#about to write, iclass 34, count 0 2006.257.17:34:24.53#ibcon#wrote, iclass 34, count 0 2006.257.17:34:24.53#ibcon#about to read 3, iclass 34, count 0 2006.257.17:34:24.57#ibcon#read 3, iclass 34, count 0 2006.257.17:34:24.57#ibcon#about to read 4, iclass 34, count 0 2006.257.17:34:24.57#ibcon#read 4, iclass 34, count 0 2006.257.17:34:24.57#ibcon#about to read 5, iclass 34, count 0 2006.257.17:34:24.57#ibcon#read 5, iclass 34, count 0 2006.257.17:34:24.57#ibcon#about to read 6, iclass 34, count 0 2006.257.17:34:24.57#ibcon#read 6, iclass 34, count 0 2006.257.17:34:24.57#ibcon#end of sib2, iclass 34, count 0 2006.257.17:34:24.57#ibcon#*after write, iclass 34, count 0 2006.257.17:34:24.57#ibcon#*before return 0, iclass 34, count 0 2006.257.17:34:24.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:24.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:34:24.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.17:34:24.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.17:34:24.57$vck44/vb=2,5 2006.257.17:34:24.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.17:34:24.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.17:34:24.57#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:24.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:24.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:24.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:24.63#ibcon#enter wrdev, iclass 36, count 2 2006.257.17:34:24.63#ibcon#first serial, iclass 36, count 2 2006.257.17:34:24.63#ibcon#enter sib2, iclass 36, count 2 2006.257.17:34:24.63#ibcon#flushed, iclass 36, count 2 2006.257.17:34:24.63#ibcon#about to write, iclass 36, count 2 2006.257.17:34:24.63#ibcon#wrote, iclass 36, count 2 2006.257.17:34:24.63#ibcon#about to read 3, iclass 36, count 2 2006.257.17:34:24.65#ibcon#read 3, iclass 36, count 2 2006.257.17:34:24.65#ibcon#about to read 4, iclass 36, count 2 2006.257.17:34:24.65#ibcon#read 4, iclass 36, count 2 2006.257.17:34:24.65#ibcon#about to read 5, iclass 36, count 2 2006.257.17:34:24.65#ibcon#read 5, iclass 36, count 2 2006.257.17:34:24.65#ibcon#about to read 6, iclass 36, count 2 2006.257.17:34:24.65#ibcon#read 6, iclass 36, count 2 2006.257.17:34:24.65#ibcon#end of sib2, iclass 36, count 2 2006.257.17:34:24.65#ibcon#*mode == 0, iclass 36, count 2 2006.257.17:34:24.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.17:34:24.65#ibcon#[27=AT02-05\r\n] 2006.257.17:34:24.65#ibcon#*before write, iclass 36, count 2 2006.257.17:34:24.65#ibcon#enter sib2, iclass 36, count 2 2006.257.17:34:24.65#ibcon#flushed, iclass 36, count 2 2006.257.17:34:24.65#ibcon#about to write, iclass 36, count 2 2006.257.17:34:24.65#ibcon#wrote, iclass 36, count 2 2006.257.17:34:24.65#ibcon#about to read 3, iclass 36, count 2 2006.257.17:34:24.68#ibcon#read 3, iclass 36, count 2 2006.257.17:34:24.68#ibcon#about to read 4, iclass 36, count 2 2006.257.17:34:24.68#ibcon#read 4, iclass 36, count 2 2006.257.17:34:24.68#ibcon#about to read 5, iclass 36, count 2 2006.257.17:34:24.68#ibcon#read 5, iclass 36, count 2 2006.257.17:34:24.68#ibcon#about to read 6, iclass 36, count 2 2006.257.17:34:24.68#ibcon#read 6, iclass 36, count 2 2006.257.17:34:24.68#ibcon#end of sib2, iclass 36, count 2 2006.257.17:34:24.68#ibcon#*after write, iclass 36, count 2 2006.257.17:34:24.68#ibcon#*before return 0, iclass 36, count 2 2006.257.17:34:24.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:24.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:34:24.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.17:34:24.68#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:24.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:24.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:24.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:24.80#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:34:24.80#ibcon#first serial, iclass 36, count 0 2006.257.17:34:24.80#ibcon#enter sib2, iclass 36, count 0 2006.257.17:34:24.80#ibcon#flushed, iclass 36, count 0 2006.257.17:34:24.80#ibcon#about to write, iclass 36, count 0 2006.257.17:34:24.80#ibcon#wrote, iclass 36, count 0 2006.257.17:34:24.80#ibcon#about to read 3, iclass 36, count 0 2006.257.17:34:24.82#ibcon#read 3, iclass 36, count 0 2006.257.17:34:24.82#ibcon#about to read 4, iclass 36, count 0 2006.257.17:34:24.82#ibcon#read 4, iclass 36, count 0 2006.257.17:34:24.82#ibcon#about to read 5, iclass 36, count 0 2006.257.17:34:24.82#ibcon#read 5, iclass 36, count 0 2006.257.17:34:24.82#ibcon#about to read 6, iclass 36, count 0 2006.257.17:34:24.82#ibcon#read 6, iclass 36, count 0 2006.257.17:34:24.82#ibcon#end of sib2, iclass 36, count 0 2006.257.17:34:24.82#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:34:24.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:34:24.82#ibcon#[27=USB\r\n] 2006.257.17:34:24.82#ibcon#*before write, iclass 36, count 0 2006.257.17:34:24.82#ibcon#enter sib2, iclass 36, count 0 2006.257.17:34:24.82#ibcon#flushed, iclass 36, count 0 2006.257.17:34:24.82#ibcon#about to write, iclass 36, count 0 2006.257.17:34:24.82#ibcon#wrote, iclass 36, count 0 2006.257.17:34:24.82#ibcon#about to read 3, iclass 36, count 0 2006.257.17:34:24.85#ibcon#read 3, iclass 36, count 0 2006.257.17:34:24.85#ibcon#about to read 4, iclass 36, count 0 2006.257.17:34:24.85#ibcon#read 4, iclass 36, count 0 2006.257.17:34:24.85#ibcon#about to read 5, iclass 36, count 0 2006.257.17:34:24.85#ibcon#read 5, iclass 36, count 0 2006.257.17:34:24.85#ibcon#about to read 6, iclass 36, count 0 2006.257.17:34:24.85#ibcon#read 6, iclass 36, count 0 2006.257.17:34:24.85#ibcon#end of sib2, iclass 36, count 0 2006.257.17:34:24.85#ibcon#*after write, iclass 36, count 0 2006.257.17:34:24.85#ibcon#*before return 0, iclass 36, count 0 2006.257.17:34:24.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:24.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:34:24.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:34:24.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:34:24.85$vck44/vblo=3,649.99 2006.257.17:34:24.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.17:34:24.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.17:34:24.85#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:24.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:24.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:24.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:24.85#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:34:24.85#ibcon#first serial, iclass 38, count 0 2006.257.17:34:24.85#ibcon#enter sib2, iclass 38, count 0 2006.257.17:34:24.85#ibcon#flushed, iclass 38, count 0 2006.257.17:34:24.85#ibcon#about to write, iclass 38, count 0 2006.257.17:34:24.85#ibcon#wrote, iclass 38, count 0 2006.257.17:34:24.85#ibcon#about to read 3, iclass 38, count 0 2006.257.17:34:24.87#ibcon#read 3, iclass 38, count 0 2006.257.17:34:24.87#ibcon#about to read 4, iclass 38, count 0 2006.257.17:34:24.87#ibcon#read 4, iclass 38, count 0 2006.257.17:34:24.87#ibcon#about to read 5, iclass 38, count 0 2006.257.17:34:24.87#ibcon#read 5, iclass 38, count 0 2006.257.17:34:24.87#ibcon#about to read 6, iclass 38, count 0 2006.257.17:34:24.87#ibcon#read 6, iclass 38, count 0 2006.257.17:34:24.87#ibcon#end of sib2, iclass 38, count 0 2006.257.17:34:24.87#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:34:24.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:34:24.87#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:34:24.87#ibcon#*before write, iclass 38, count 0 2006.257.17:34:24.87#ibcon#enter sib2, iclass 38, count 0 2006.257.17:34:24.87#ibcon#flushed, iclass 38, count 0 2006.257.17:34:24.87#ibcon#about to write, iclass 38, count 0 2006.257.17:34:24.87#ibcon#wrote, iclass 38, count 0 2006.257.17:34:24.87#ibcon#about to read 3, iclass 38, count 0 2006.257.17:34:24.91#ibcon#read 3, iclass 38, count 0 2006.257.17:34:24.91#ibcon#about to read 4, iclass 38, count 0 2006.257.17:34:24.91#ibcon#read 4, iclass 38, count 0 2006.257.17:34:24.91#ibcon#about to read 5, iclass 38, count 0 2006.257.17:34:24.91#ibcon#read 5, iclass 38, count 0 2006.257.17:34:24.91#ibcon#about to read 6, iclass 38, count 0 2006.257.17:34:24.91#ibcon#read 6, iclass 38, count 0 2006.257.17:34:24.91#ibcon#end of sib2, iclass 38, count 0 2006.257.17:34:24.91#ibcon#*after write, iclass 38, count 0 2006.257.17:34:24.91#ibcon#*before return 0, iclass 38, count 0 2006.257.17:34:24.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:24.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:34:24.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:34:24.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:34:24.91$vck44/vb=3,4 2006.257.17:34:24.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.17:34:24.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.17:34:24.91#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:24.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:24.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:24.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:24.97#ibcon#enter wrdev, iclass 40, count 2 2006.257.17:34:24.97#ibcon#first serial, iclass 40, count 2 2006.257.17:34:24.97#ibcon#enter sib2, iclass 40, count 2 2006.257.17:34:24.97#ibcon#flushed, iclass 40, count 2 2006.257.17:34:24.97#ibcon#about to write, iclass 40, count 2 2006.257.17:34:24.97#ibcon#wrote, iclass 40, count 2 2006.257.17:34:24.97#ibcon#about to read 3, iclass 40, count 2 2006.257.17:34:24.99#ibcon#read 3, iclass 40, count 2 2006.257.17:34:24.99#ibcon#about to read 4, iclass 40, count 2 2006.257.17:34:24.99#ibcon#read 4, iclass 40, count 2 2006.257.17:34:24.99#ibcon#about to read 5, iclass 40, count 2 2006.257.17:34:24.99#ibcon#read 5, iclass 40, count 2 2006.257.17:34:24.99#ibcon#about to read 6, iclass 40, count 2 2006.257.17:34:24.99#ibcon#read 6, iclass 40, count 2 2006.257.17:34:24.99#ibcon#end of sib2, iclass 40, count 2 2006.257.17:34:24.99#ibcon#*mode == 0, iclass 40, count 2 2006.257.17:34:24.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.17:34:24.99#ibcon#[27=AT03-04\r\n] 2006.257.17:34:24.99#ibcon#*before write, iclass 40, count 2 2006.257.17:34:24.99#ibcon#enter sib2, iclass 40, count 2 2006.257.17:34:24.99#ibcon#flushed, iclass 40, count 2 2006.257.17:34:24.99#ibcon#about to write, iclass 40, count 2 2006.257.17:34:24.99#ibcon#wrote, iclass 40, count 2 2006.257.17:34:24.99#ibcon#about to read 3, iclass 40, count 2 2006.257.17:34:25.02#ibcon#read 3, iclass 40, count 2 2006.257.17:34:25.02#ibcon#about to read 4, iclass 40, count 2 2006.257.17:34:25.02#ibcon#read 4, iclass 40, count 2 2006.257.17:34:25.02#ibcon#about to read 5, iclass 40, count 2 2006.257.17:34:25.02#ibcon#read 5, iclass 40, count 2 2006.257.17:34:25.02#ibcon#about to read 6, iclass 40, count 2 2006.257.17:34:25.02#ibcon#read 6, iclass 40, count 2 2006.257.17:34:25.02#ibcon#end of sib2, iclass 40, count 2 2006.257.17:34:25.02#ibcon#*after write, iclass 40, count 2 2006.257.17:34:25.02#ibcon#*before return 0, iclass 40, count 2 2006.257.17:34:25.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:25.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:34:25.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.17:34:25.02#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:25.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:25.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:25.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:25.14#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:34:25.14#ibcon#first serial, iclass 40, count 0 2006.257.17:34:25.14#ibcon#enter sib2, iclass 40, count 0 2006.257.17:34:25.14#ibcon#flushed, iclass 40, count 0 2006.257.17:34:25.14#ibcon#about to write, iclass 40, count 0 2006.257.17:34:25.14#ibcon#wrote, iclass 40, count 0 2006.257.17:34:25.14#ibcon#about to read 3, iclass 40, count 0 2006.257.17:34:25.16#ibcon#read 3, iclass 40, count 0 2006.257.17:34:25.16#ibcon#about to read 4, iclass 40, count 0 2006.257.17:34:25.16#ibcon#read 4, iclass 40, count 0 2006.257.17:34:25.16#ibcon#about to read 5, iclass 40, count 0 2006.257.17:34:25.16#ibcon#read 5, iclass 40, count 0 2006.257.17:34:25.16#ibcon#about to read 6, iclass 40, count 0 2006.257.17:34:25.16#ibcon#read 6, iclass 40, count 0 2006.257.17:34:25.16#ibcon#end of sib2, iclass 40, count 0 2006.257.17:34:25.16#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:34:25.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:34:25.16#ibcon#[27=USB\r\n] 2006.257.17:34:25.16#ibcon#*before write, iclass 40, count 0 2006.257.17:34:25.16#ibcon#enter sib2, iclass 40, count 0 2006.257.17:34:25.16#ibcon#flushed, iclass 40, count 0 2006.257.17:34:25.16#ibcon#about to write, iclass 40, count 0 2006.257.17:34:25.16#ibcon#wrote, iclass 40, count 0 2006.257.17:34:25.16#ibcon#about to read 3, iclass 40, count 0 2006.257.17:34:25.19#ibcon#read 3, iclass 40, count 0 2006.257.17:34:25.19#ibcon#about to read 4, iclass 40, count 0 2006.257.17:34:25.19#ibcon#read 4, iclass 40, count 0 2006.257.17:34:25.19#ibcon#about to read 5, iclass 40, count 0 2006.257.17:34:25.19#ibcon#read 5, iclass 40, count 0 2006.257.17:34:25.19#ibcon#about to read 6, iclass 40, count 0 2006.257.17:34:25.19#ibcon#read 6, iclass 40, count 0 2006.257.17:34:25.19#ibcon#end of sib2, iclass 40, count 0 2006.257.17:34:25.19#ibcon#*after write, iclass 40, count 0 2006.257.17:34:25.19#ibcon#*before return 0, iclass 40, count 0 2006.257.17:34:25.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:25.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:34:25.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:34:25.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:34:25.19$vck44/vblo=4,679.99 2006.257.17:34:25.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.17:34:25.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.17:34:25.19#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:25.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:25.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:25.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:25.19#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:34:25.19#ibcon#first serial, iclass 4, count 0 2006.257.17:34:25.19#ibcon#enter sib2, iclass 4, count 0 2006.257.17:34:25.19#ibcon#flushed, iclass 4, count 0 2006.257.17:34:25.19#ibcon#about to write, iclass 4, count 0 2006.257.17:34:25.19#ibcon#wrote, iclass 4, count 0 2006.257.17:34:25.19#ibcon#about to read 3, iclass 4, count 0 2006.257.17:34:25.21#ibcon#read 3, iclass 4, count 0 2006.257.17:34:25.21#ibcon#about to read 4, iclass 4, count 0 2006.257.17:34:25.21#ibcon#read 4, iclass 4, count 0 2006.257.17:34:25.21#ibcon#about to read 5, iclass 4, count 0 2006.257.17:34:25.21#ibcon#read 5, iclass 4, count 0 2006.257.17:34:25.21#ibcon#about to read 6, iclass 4, count 0 2006.257.17:34:25.21#ibcon#read 6, iclass 4, count 0 2006.257.17:34:25.21#ibcon#end of sib2, iclass 4, count 0 2006.257.17:34:25.21#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:34:25.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:34:25.21#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:34:25.21#ibcon#*before write, iclass 4, count 0 2006.257.17:34:25.21#ibcon#enter sib2, iclass 4, count 0 2006.257.17:34:25.21#ibcon#flushed, iclass 4, count 0 2006.257.17:34:25.21#ibcon#about to write, iclass 4, count 0 2006.257.17:34:25.21#ibcon#wrote, iclass 4, count 0 2006.257.17:34:25.21#ibcon#about to read 3, iclass 4, count 0 2006.257.17:34:25.25#ibcon#read 3, iclass 4, count 0 2006.257.17:34:25.25#ibcon#about to read 4, iclass 4, count 0 2006.257.17:34:25.25#ibcon#read 4, iclass 4, count 0 2006.257.17:34:25.25#ibcon#about to read 5, iclass 4, count 0 2006.257.17:34:25.25#ibcon#read 5, iclass 4, count 0 2006.257.17:34:25.25#ibcon#about to read 6, iclass 4, count 0 2006.257.17:34:25.25#ibcon#read 6, iclass 4, count 0 2006.257.17:34:25.25#ibcon#end of sib2, iclass 4, count 0 2006.257.17:34:25.25#ibcon#*after write, iclass 4, count 0 2006.257.17:34:25.25#ibcon#*before return 0, iclass 4, count 0 2006.257.17:34:25.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:25.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:34:25.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:34:25.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:34:25.25$vck44/vb=4,5 2006.257.17:34:25.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.17:34:25.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.17:34:25.25#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:25.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:25.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:25.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:25.31#ibcon#enter wrdev, iclass 6, count 2 2006.257.17:34:25.31#ibcon#first serial, iclass 6, count 2 2006.257.17:34:25.31#ibcon#enter sib2, iclass 6, count 2 2006.257.17:34:25.31#ibcon#flushed, iclass 6, count 2 2006.257.17:34:25.31#ibcon#about to write, iclass 6, count 2 2006.257.17:34:25.31#ibcon#wrote, iclass 6, count 2 2006.257.17:34:25.31#ibcon#about to read 3, iclass 6, count 2 2006.257.17:34:25.33#ibcon#read 3, iclass 6, count 2 2006.257.17:34:25.33#ibcon#about to read 4, iclass 6, count 2 2006.257.17:34:25.33#ibcon#read 4, iclass 6, count 2 2006.257.17:34:25.33#ibcon#about to read 5, iclass 6, count 2 2006.257.17:34:25.33#ibcon#read 5, iclass 6, count 2 2006.257.17:34:25.33#ibcon#about to read 6, iclass 6, count 2 2006.257.17:34:25.33#ibcon#read 6, iclass 6, count 2 2006.257.17:34:25.33#ibcon#end of sib2, iclass 6, count 2 2006.257.17:34:25.33#ibcon#*mode == 0, iclass 6, count 2 2006.257.17:34:25.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.17:34:25.33#ibcon#[27=AT04-05\r\n] 2006.257.17:34:25.33#ibcon#*before write, iclass 6, count 2 2006.257.17:34:25.33#ibcon#enter sib2, iclass 6, count 2 2006.257.17:34:25.33#ibcon#flushed, iclass 6, count 2 2006.257.17:34:25.33#ibcon#about to write, iclass 6, count 2 2006.257.17:34:25.33#ibcon#wrote, iclass 6, count 2 2006.257.17:34:25.33#ibcon#about to read 3, iclass 6, count 2 2006.257.17:34:25.36#ibcon#read 3, iclass 6, count 2 2006.257.17:34:25.36#ibcon#about to read 4, iclass 6, count 2 2006.257.17:34:25.36#ibcon#read 4, iclass 6, count 2 2006.257.17:34:25.36#ibcon#about to read 5, iclass 6, count 2 2006.257.17:34:25.36#ibcon#read 5, iclass 6, count 2 2006.257.17:34:25.36#ibcon#about to read 6, iclass 6, count 2 2006.257.17:34:25.36#ibcon#read 6, iclass 6, count 2 2006.257.17:34:25.36#ibcon#end of sib2, iclass 6, count 2 2006.257.17:34:25.36#ibcon#*after write, iclass 6, count 2 2006.257.17:34:25.36#ibcon#*before return 0, iclass 6, count 2 2006.257.17:34:25.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:25.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:34:25.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.17:34:25.36#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:25.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:25.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:25.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:25.48#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:34:25.48#ibcon#first serial, iclass 6, count 0 2006.257.17:34:25.48#ibcon#enter sib2, iclass 6, count 0 2006.257.17:34:25.48#ibcon#flushed, iclass 6, count 0 2006.257.17:34:25.48#ibcon#about to write, iclass 6, count 0 2006.257.17:34:25.48#ibcon#wrote, iclass 6, count 0 2006.257.17:34:25.48#ibcon#about to read 3, iclass 6, count 0 2006.257.17:34:25.50#ibcon#read 3, iclass 6, count 0 2006.257.17:34:25.50#ibcon#about to read 4, iclass 6, count 0 2006.257.17:34:25.50#ibcon#read 4, iclass 6, count 0 2006.257.17:34:25.50#ibcon#about to read 5, iclass 6, count 0 2006.257.17:34:25.50#ibcon#read 5, iclass 6, count 0 2006.257.17:34:25.50#ibcon#about to read 6, iclass 6, count 0 2006.257.17:34:25.50#ibcon#read 6, iclass 6, count 0 2006.257.17:34:25.50#ibcon#end of sib2, iclass 6, count 0 2006.257.17:34:25.50#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:34:25.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:34:25.50#ibcon#[27=USB\r\n] 2006.257.17:34:25.50#ibcon#*before write, iclass 6, count 0 2006.257.17:34:25.50#ibcon#enter sib2, iclass 6, count 0 2006.257.17:34:25.50#ibcon#flushed, iclass 6, count 0 2006.257.17:34:25.50#ibcon#about to write, iclass 6, count 0 2006.257.17:34:25.50#ibcon#wrote, iclass 6, count 0 2006.257.17:34:25.50#ibcon#about to read 3, iclass 6, count 0 2006.257.17:34:25.53#ibcon#read 3, iclass 6, count 0 2006.257.17:34:25.53#ibcon#about to read 4, iclass 6, count 0 2006.257.17:34:25.53#ibcon#read 4, iclass 6, count 0 2006.257.17:34:25.53#ibcon#about to read 5, iclass 6, count 0 2006.257.17:34:25.53#ibcon#read 5, iclass 6, count 0 2006.257.17:34:25.53#ibcon#about to read 6, iclass 6, count 0 2006.257.17:34:25.53#ibcon#read 6, iclass 6, count 0 2006.257.17:34:25.53#ibcon#end of sib2, iclass 6, count 0 2006.257.17:34:25.53#ibcon#*after write, iclass 6, count 0 2006.257.17:34:25.53#ibcon#*before return 0, iclass 6, count 0 2006.257.17:34:25.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:25.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:34:25.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:34:25.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:34:25.53$vck44/vblo=5,709.99 2006.257.17:34:25.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.17:34:25.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.17:34:25.53#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:25.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:25.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:25.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:25.53#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:34:25.53#ibcon#first serial, iclass 10, count 0 2006.257.17:34:25.53#ibcon#enter sib2, iclass 10, count 0 2006.257.17:34:25.53#ibcon#flushed, iclass 10, count 0 2006.257.17:34:25.53#ibcon#about to write, iclass 10, count 0 2006.257.17:34:25.53#ibcon#wrote, iclass 10, count 0 2006.257.17:34:25.53#ibcon#about to read 3, iclass 10, count 0 2006.257.17:34:25.55#ibcon#read 3, iclass 10, count 0 2006.257.17:34:25.55#ibcon#about to read 4, iclass 10, count 0 2006.257.17:34:25.55#ibcon#read 4, iclass 10, count 0 2006.257.17:34:25.55#ibcon#about to read 5, iclass 10, count 0 2006.257.17:34:25.55#ibcon#read 5, iclass 10, count 0 2006.257.17:34:25.55#ibcon#about to read 6, iclass 10, count 0 2006.257.17:34:25.55#ibcon#read 6, iclass 10, count 0 2006.257.17:34:25.55#ibcon#end of sib2, iclass 10, count 0 2006.257.17:34:25.55#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:34:25.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:34:25.55#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:34:25.55#ibcon#*before write, iclass 10, count 0 2006.257.17:34:25.55#ibcon#enter sib2, iclass 10, count 0 2006.257.17:34:25.55#ibcon#flushed, iclass 10, count 0 2006.257.17:34:25.55#ibcon#about to write, iclass 10, count 0 2006.257.17:34:25.55#ibcon#wrote, iclass 10, count 0 2006.257.17:34:25.55#ibcon#about to read 3, iclass 10, count 0 2006.257.17:34:25.59#ibcon#read 3, iclass 10, count 0 2006.257.17:34:25.59#ibcon#about to read 4, iclass 10, count 0 2006.257.17:34:25.59#ibcon#read 4, iclass 10, count 0 2006.257.17:34:25.59#ibcon#about to read 5, iclass 10, count 0 2006.257.17:34:25.59#ibcon#read 5, iclass 10, count 0 2006.257.17:34:25.59#ibcon#about to read 6, iclass 10, count 0 2006.257.17:34:25.59#ibcon#read 6, iclass 10, count 0 2006.257.17:34:25.59#ibcon#end of sib2, iclass 10, count 0 2006.257.17:34:25.59#ibcon#*after write, iclass 10, count 0 2006.257.17:34:25.59#ibcon#*before return 0, iclass 10, count 0 2006.257.17:34:25.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:25.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:34:25.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:34:25.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:34:25.59$vck44/vb=5,4 2006.257.17:34:25.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.17:34:25.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.17:34:25.59#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:25.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:25.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:25.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:25.65#ibcon#enter wrdev, iclass 12, count 2 2006.257.17:34:25.65#ibcon#first serial, iclass 12, count 2 2006.257.17:34:25.65#ibcon#enter sib2, iclass 12, count 2 2006.257.17:34:25.65#ibcon#flushed, iclass 12, count 2 2006.257.17:34:25.65#ibcon#about to write, iclass 12, count 2 2006.257.17:34:25.65#ibcon#wrote, iclass 12, count 2 2006.257.17:34:25.65#ibcon#about to read 3, iclass 12, count 2 2006.257.17:34:25.67#ibcon#read 3, iclass 12, count 2 2006.257.17:34:25.67#ibcon#about to read 4, iclass 12, count 2 2006.257.17:34:25.67#ibcon#read 4, iclass 12, count 2 2006.257.17:34:25.67#ibcon#about to read 5, iclass 12, count 2 2006.257.17:34:25.67#ibcon#read 5, iclass 12, count 2 2006.257.17:34:25.67#ibcon#about to read 6, iclass 12, count 2 2006.257.17:34:25.67#ibcon#read 6, iclass 12, count 2 2006.257.17:34:25.67#ibcon#end of sib2, iclass 12, count 2 2006.257.17:34:25.67#ibcon#*mode == 0, iclass 12, count 2 2006.257.17:34:25.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.17:34:25.67#ibcon#[27=AT05-04\r\n] 2006.257.17:34:25.67#ibcon#*before write, iclass 12, count 2 2006.257.17:34:25.67#ibcon#enter sib2, iclass 12, count 2 2006.257.17:34:25.67#ibcon#flushed, iclass 12, count 2 2006.257.17:34:25.67#ibcon#about to write, iclass 12, count 2 2006.257.17:34:25.67#ibcon#wrote, iclass 12, count 2 2006.257.17:34:25.67#ibcon#about to read 3, iclass 12, count 2 2006.257.17:34:25.70#ibcon#read 3, iclass 12, count 2 2006.257.17:34:25.70#ibcon#about to read 4, iclass 12, count 2 2006.257.17:34:25.70#ibcon#read 4, iclass 12, count 2 2006.257.17:34:25.70#ibcon#about to read 5, iclass 12, count 2 2006.257.17:34:25.70#ibcon#read 5, iclass 12, count 2 2006.257.17:34:25.70#ibcon#about to read 6, iclass 12, count 2 2006.257.17:34:25.70#ibcon#read 6, iclass 12, count 2 2006.257.17:34:25.70#ibcon#end of sib2, iclass 12, count 2 2006.257.17:34:25.70#ibcon#*after write, iclass 12, count 2 2006.257.17:34:25.70#ibcon#*before return 0, iclass 12, count 2 2006.257.17:34:25.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:25.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:34:25.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.17:34:25.70#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:25.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:25.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:25.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:25.82#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:34:25.82#ibcon#first serial, iclass 12, count 0 2006.257.17:34:25.82#ibcon#enter sib2, iclass 12, count 0 2006.257.17:34:25.82#ibcon#flushed, iclass 12, count 0 2006.257.17:34:25.82#ibcon#about to write, iclass 12, count 0 2006.257.17:34:25.82#ibcon#wrote, iclass 12, count 0 2006.257.17:34:25.82#ibcon#about to read 3, iclass 12, count 0 2006.257.17:34:25.84#ibcon#read 3, iclass 12, count 0 2006.257.17:34:25.84#ibcon#about to read 4, iclass 12, count 0 2006.257.17:34:25.84#ibcon#read 4, iclass 12, count 0 2006.257.17:34:25.84#ibcon#about to read 5, iclass 12, count 0 2006.257.17:34:25.84#ibcon#read 5, iclass 12, count 0 2006.257.17:34:25.84#ibcon#about to read 6, iclass 12, count 0 2006.257.17:34:25.84#ibcon#read 6, iclass 12, count 0 2006.257.17:34:25.84#ibcon#end of sib2, iclass 12, count 0 2006.257.17:34:25.84#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:34:25.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:34:25.84#ibcon#[27=USB\r\n] 2006.257.17:34:25.84#ibcon#*before write, iclass 12, count 0 2006.257.17:34:25.84#ibcon#enter sib2, iclass 12, count 0 2006.257.17:34:25.84#ibcon#flushed, iclass 12, count 0 2006.257.17:34:25.84#ibcon#about to write, iclass 12, count 0 2006.257.17:34:25.84#ibcon#wrote, iclass 12, count 0 2006.257.17:34:25.84#ibcon#about to read 3, iclass 12, count 0 2006.257.17:34:25.87#ibcon#read 3, iclass 12, count 0 2006.257.17:34:25.87#ibcon#about to read 4, iclass 12, count 0 2006.257.17:34:25.87#ibcon#read 4, iclass 12, count 0 2006.257.17:34:25.87#ibcon#about to read 5, iclass 12, count 0 2006.257.17:34:25.87#ibcon#read 5, iclass 12, count 0 2006.257.17:34:25.87#ibcon#about to read 6, iclass 12, count 0 2006.257.17:34:25.87#ibcon#read 6, iclass 12, count 0 2006.257.17:34:25.87#ibcon#end of sib2, iclass 12, count 0 2006.257.17:34:25.87#ibcon#*after write, iclass 12, count 0 2006.257.17:34:25.87#ibcon#*before return 0, iclass 12, count 0 2006.257.17:34:25.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:25.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:34:25.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:34:25.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:34:25.87$vck44/vblo=6,719.99 2006.257.17:34:25.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.17:34:25.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.17:34:25.87#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:25.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:25.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:25.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:25.87#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:34:25.87#ibcon#first serial, iclass 14, count 0 2006.257.17:34:25.87#ibcon#enter sib2, iclass 14, count 0 2006.257.17:34:25.87#ibcon#flushed, iclass 14, count 0 2006.257.17:34:25.87#ibcon#about to write, iclass 14, count 0 2006.257.17:34:25.87#ibcon#wrote, iclass 14, count 0 2006.257.17:34:25.87#ibcon#about to read 3, iclass 14, count 0 2006.257.17:34:25.89#ibcon#read 3, iclass 14, count 0 2006.257.17:34:25.89#ibcon#about to read 4, iclass 14, count 0 2006.257.17:34:25.89#ibcon#read 4, iclass 14, count 0 2006.257.17:34:25.89#ibcon#about to read 5, iclass 14, count 0 2006.257.17:34:25.89#ibcon#read 5, iclass 14, count 0 2006.257.17:34:25.89#ibcon#about to read 6, iclass 14, count 0 2006.257.17:34:25.89#ibcon#read 6, iclass 14, count 0 2006.257.17:34:25.89#ibcon#end of sib2, iclass 14, count 0 2006.257.17:34:25.89#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:34:25.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:34:25.89#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:34:25.89#ibcon#*before write, iclass 14, count 0 2006.257.17:34:25.89#ibcon#enter sib2, iclass 14, count 0 2006.257.17:34:25.89#ibcon#flushed, iclass 14, count 0 2006.257.17:34:25.89#ibcon#about to write, iclass 14, count 0 2006.257.17:34:25.89#ibcon#wrote, iclass 14, count 0 2006.257.17:34:25.89#ibcon#about to read 3, iclass 14, count 0 2006.257.17:34:25.93#ibcon#read 3, iclass 14, count 0 2006.257.17:34:25.93#ibcon#about to read 4, iclass 14, count 0 2006.257.17:34:25.93#ibcon#read 4, iclass 14, count 0 2006.257.17:34:25.93#ibcon#about to read 5, iclass 14, count 0 2006.257.17:34:25.93#ibcon#read 5, iclass 14, count 0 2006.257.17:34:25.93#ibcon#about to read 6, iclass 14, count 0 2006.257.17:34:25.93#ibcon#read 6, iclass 14, count 0 2006.257.17:34:25.93#ibcon#end of sib2, iclass 14, count 0 2006.257.17:34:25.93#ibcon#*after write, iclass 14, count 0 2006.257.17:34:25.93#ibcon#*before return 0, iclass 14, count 0 2006.257.17:34:25.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:25.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:34:25.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:34:25.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:34:25.93$vck44/vb=6,4 2006.257.17:34:25.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.17:34:25.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.17:34:25.93#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:25.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:34:25.95#abcon#<5=/14 1.6 4.4 17.40 971014.2\r\n> 2006.257.17:34:25.97#abcon#{5=INTERFACE CLEAR} 2006.257.17:34:25.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:34:25.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:34:25.99#ibcon#enter wrdev, iclass 17, count 2 2006.257.17:34:25.99#ibcon#first serial, iclass 17, count 2 2006.257.17:34:25.99#ibcon#enter sib2, iclass 17, count 2 2006.257.17:34:25.99#ibcon#flushed, iclass 17, count 2 2006.257.17:34:25.99#ibcon#about to write, iclass 17, count 2 2006.257.17:34:25.99#ibcon#wrote, iclass 17, count 2 2006.257.17:34:25.99#ibcon#about to read 3, iclass 17, count 2 2006.257.17:34:26.01#ibcon#read 3, iclass 17, count 2 2006.257.17:34:26.01#ibcon#about to read 4, iclass 17, count 2 2006.257.17:34:26.01#ibcon#read 4, iclass 17, count 2 2006.257.17:34:26.01#ibcon#about to read 5, iclass 17, count 2 2006.257.17:34:26.01#ibcon#read 5, iclass 17, count 2 2006.257.17:34:26.01#ibcon#about to read 6, iclass 17, count 2 2006.257.17:34:26.01#ibcon#read 6, iclass 17, count 2 2006.257.17:34:26.01#ibcon#end of sib2, iclass 17, count 2 2006.257.17:34:26.01#ibcon#*mode == 0, iclass 17, count 2 2006.257.17:34:26.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.17:34:26.01#ibcon#[27=AT06-04\r\n] 2006.257.17:34:26.01#ibcon#*before write, iclass 17, count 2 2006.257.17:34:26.01#ibcon#enter sib2, iclass 17, count 2 2006.257.17:34:26.01#ibcon#flushed, iclass 17, count 2 2006.257.17:34:26.01#ibcon#about to write, iclass 17, count 2 2006.257.17:34:26.01#ibcon#wrote, iclass 17, count 2 2006.257.17:34:26.01#ibcon#about to read 3, iclass 17, count 2 2006.257.17:34:26.03#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:34:26.04#ibcon#read 3, iclass 17, count 2 2006.257.17:34:26.04#ibcon#about to read 4, iclass 17, count 2 2006.257.17:34:26.04#ibcon#read 4, iclass 17, count 2 2006.257.17:34:26.04#ibcon#about to read 5, iclass 17, count 2 2006.257.17:34:26.04#ibcon#read 5, iclass 17, count 2 2006.257.17:34:26.04#ibcon#about to read 6, iclass 17, count 2 2006.257.17:34:26.04#ibcon#read 6, iclass 17, count 2 2006.257.17:34:26.04#ibcon#end of sib2, iclass 17, count 2 2006.257.17:34:26.04#ibcon#*after write, iclass 17, count 2 2006.257.17:34:26.04#ibcon#*before return 0, iclass 17, count 2 2006.257.17:34:26.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:34:26.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:34:26.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.17:34:26.04#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:26.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:34:26.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:34:26.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:34:26.16#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:34:26.16#ibcon#first serial, iclass 17, count 0 2006.257.17:34:26.16#ibcon#enter sib2, iclass 17, count 0 2006.257.17:34:26.16#ibcon#flushed, iclass 17, count 0 2006.257.17:34:26.16#ibcon#about to write, iclass 17, count 0 2006.257.17:34:26.16#ibcon#wrote, iclass 17, count 0 2006.257.17:34:26.16#ibcon#about to read 3, iclass 17, count 0 2006.257.17:34:26.18#ibcon#read 3, iclass 17, count 0 2006.257.17:34:26.18#ibcon#about to read 4, iclass 17, count 0 2006.257.17:34:26.18#ibcon#read 4, iclass 17, count 0 2006.257.17:34:26.18#ibcon#about to read 5, iclass 17, count 0 2006.257.17:34:26.18#ibcon#read 5, iclass 17, count 0 2006.257.17:34:26.18#ibcon#about to read 6, iclass 17, count 0 2006.257.17:34:26.18#ibcon#read 6, iclass 17, count 0 2006.257.17:34:26.18#ibcon#end of sib2, iclass 17, count 0 2006.257.17:34:26.18#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:34:26.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:34:26.18#ibcon#[27=USB\r\n] 2006.257.17:34:26.18#ibcon#*before write, iclass 17, count 0 2006.257.17:34:26.18#ibcon#enter sib2, iclass 17, count 0 2006.257.17:34:26.18#ibcon#flushed, iclass 17, count 0 2006.257.17:34:26.18#ibcon#about to write, iclass 17, count 0 2006.257.17:34:26.18#ibcon#wrote, iclass 17, count 0 2006.257.17:34:26.18#ibcon#about to read 3, iclass 17, count 0 2006.257.17:34:26.21#ibcon#read 3, iclass 17, count 0 2006.257.17:34:26.21#ibcon#about to read 4, iclass 17, count 0 2006.257.17:34:26.21#ibcon#read 4, iclass 17, count 0 2006.257.17:34:26.21#ibcon#about to read 5, iclass 17, count 0 2006.257.17:34:26.21#ibcon#read 5, iclass 17, count 0 2006.257.17:34:26.21#ibcon#about to read 6, iclass 17, count 0 2006.257.17:34:26.21#ibcon#read 6, iclass 17, count 0 2006.257.17:34:26.21#ibcon#end of sib2, iclass 17, count 0 2006.257.17:34:26.21#ibcon#*after write, iclass 17, count 0 2006.257.17:34:26.21#ibcon#*before return 0, iclass 17, count 0 2006.257.17:34:26.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:34:26.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:34:26.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:34:26.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:34:26.21$vck44/vblo=7,734.99 2006.257.17:34:26.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.17:34:26.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.17:34:26.21#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:26.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:26.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:26.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:26.21#ibcon#enter wrdev, iclass 22, count 0 2006.257.17:34:26.21#ibcon#first serial, iclass 22, count 0 2006.257.17:34:26.21#ibcon#enter sib2, iclass 22, count 0 2006.257.17:34:26.21#ibcon#flushed, iclass 22, count 0 2006.257.17:34:26.21#ibcon#about to write, iclass 22, count 0 2006.257.17:34:26.21#ibcon#wrote, iclass 22, count 0 2006.257.17:34:26.21#ibcon#about to read 3, iclass 22, count 0 2006.257.17:34:26.23#ibcon#read 3, iclass 22, count 0 2006.257.17:34:26.23#ibcon#about to read 4, iclass 22, count 0 2006.257.17:34:26.23#ibcon#read 4, iclass 22, count 0 2006.257.17:34:26.23#ibcon#about to read 5, iclass 22, count 0 2006.257.17:34:26.23#ibcon#read 5, iclass 22, count 0 2006.257.17:34:26.23#ibcon#about to read 6, iclass 22, count 0 2006.257.17:34:26.23#ibcon#read 6, iclass 22, count 0 2006.257.17:34:26.23#ibcon#end of sib2, iclass 22, count 0 2006.257.17:34:26.23#ibcon#*mode == 0, iclass 22, count 0 2006.257.17:34:26.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.17:34:26.23#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:34:26.23#ibcon#*before write, iclass 22, count 0 2006.257.17:34:26.23#ibcon#enter sib2, iclass 22, count 0 2006.257.17:34:26.23#ibcon#flushed, iclass 22, count 0 2006.257.17:34:26.23#ibcon#about to write, iclass 22, count 0 2006.257.17:34:26.23#ibcon#wrote, iclass 22, count 0 2006.257.17:34:26.23#ibcon#about to read 3, iclass 22, count 0 2006.257.17:34:26.27#ibcon#read 3, iclass 22, count 0 2006.257.17:34:26.27#ibcon#about to read 4, iclass 22, count 0 2006.257.17:34:26.27#ibcon#read 4, iclass 22, count 0 2006.257.17:34:26.27#ibcon#about to read 5, iclass 22, count 0 2006.257.17:34:26.27#ibcon#read 5, iclass 22, count 0 2006.257.17:34:26.27#ibcon#about to read 6, iclass 22, count 0 2006.257.17:34:26.27#ibcon#read 6, iclass 22, count 0 2006.257.17:34:26.27#ibcon#end of sib2, iclass 22, count 0 2006.257.17:34:26.27#ibcon#*after write, iclass 22, count 0 2006.257.17:34:26.27#ibcon#*before return 0, iclass 22, count 0 2006.257.17:34:26.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:26.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:34:26.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.17:34:26.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.17:34:26.27$vck44/vb=7,4 2006.257.17:34:26.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.17:34:26.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.17:34:26.27#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:26.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:26.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:26.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:26.33#ibcon#enter wrdev, iclass 24, count 2 2006.257.17:34:26.33#ibcon#first serial, iclass 24, count 2 2006.257.17:34:26.33#ibcon#enter sib2, iclass 24, count 2 2006.257.17:34:26.33#ibcon#flushed, iclass 24, count 2 2006.257.17:34:26.33#ibcon#about to write, iclass 24, count 2 2006.257.17:34:26.33#ibcon#wrote, iclass 24, count 2 2006.257.17:34:26.33#ibcon#about to read 3, iclass 24, count 2 2006.257.17:34:26.35#ibcon#read 3, iclass 24, count 2 2006.257.17:34:26.35#ibcon#about to read 4, iclass 24, count 2 2006.257.17:34:26.35#ibcon#read 4, iclass 24, count 2 2006.257.17:34:26.35#ibcon#about to read 5, iclass 24, count 2 2006.257.17:34:26.35#ibcon#read 5, iclass 24, count 2 2006.257.17:34:26.35#ibcon#about to read 6, iclass 24, count 2 2006.257.17:34:26.35#ibcon#read 6, iclass 24, count 2 2006.257.17:34:26.35#ibcon#end of sib2, iclass 24, count 2 2006.257.17:34:26.35#ibcon#*mode == 0, iclass 24, count 2 2006.257.17:34:26.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.17:34:26.35#ibcon#[27=AT07-04\r\n] 2006.257.17:34:26.35#ibcon#*before write, iclass 24, count 2 2006.257.17:34:26.35#ibcon#enter sib2, iclass 24, count 2 2006.257.17:34:26.35#ibcon#flushed, iclass 24, count 2 2006.257.17:34:26.35#ibcon#about to write, iclass 24, count 2 2006.257.17:34:26.35#ibcon#wrote, iclass 24, count 2 2006.257.17:34:26.35#ibcon#about to read 3, iclass 24, count 2 2006.257.17:34:26.38#ibcon#read 3, iclass 24, count 2 2006.257.17:34:26.38#ibcon#about to read 4, iclass 24, count 2 2006.257.17:34:26.38#ibcon#read 4, iclass 24, count 2 2006.257.17:34:26.38#ibcon#about to read 5, iclass 24, count 2 2006.257.17:34:26.38#ibcon#read 5, iclass 24, count 2 2006.257.17:34:26.38#ibcon#about to read 6, iclass 24, count 2 2006.257.17:34:26.38#ibcon#read 6, iclass 24, count 2 2006.257.17:34:26.38#ibcon#end of sib2, iclass 24, count 2 2006.257.17:34:26.38#ibcon#*after write, iclass 24, count 2 2006.257.17:34:26.38#ibcon#*before return 0, iclass 24, count 2 2006.257.17:34:26.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:26.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:34:26.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.17:34:26.38#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:26.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:26.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:26.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:26.50#ibcon#enter wrdev, iclass 24, count 0 2006.257.17:34:26.50#ibcon#first serial, iclass 24, count 0 2006.257.17:34:26.50#ibcon#enter sib2, iclass 24, count 0 2006.257.17:34:26.50#ibcon#flushed, iclass 24, count 0 2006.257.17:34:26.50#ibcon#about to write, iclass 24, count 0 2006.257.17:34:26.50#ibcon#wrote, iclass 24, count 0 2006.257.17:34:26.50#ibcon#about to read 3, iclass 24, count 0 2006.257.17:34:26.52#ibcon#read 3, iclass 24, count 0 2006.257.17:34:26.52#ibcon#about to read 4, iclass 24, count 0 2006.257.17:34:26.52#ibcon#read 4, iclass 24, count 0 2006.257.17:34:26.52#ibcon#about to read 5, iclass 24, count 0 2006.257.17:34:26.52#ibcon#read 5, iclass 24, count 0 2006.257.17:34:26.52#ibcon#about to read 6, iclass 24, count 0 2006.257.17:34:26.52#ibcon#read 6, iclass 24, count 0 2006.257.17:34:26.52#ibcon#end of sib2, iclass 24, count 0 2006.257.17:34:26.52#ibcon#*mode == 0, iclass 24, count 0 2006.257.17:34:26.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.17:34:26.52#ibcon#[27=USB\r\n] 2006.257.17:34:26.52#ibcon#*before write, iclass 24, count 0 2006.257.17:34:26.52#ibcon#enter sib2, iclass 24, count 0 2006.257.17:34:26.52#ibcon#flushed, iclass 24, count 0 2006.257.17:34:26.52#ibcon#about to write, iclass 24, count 0 2006.257.17:34:26.52#ibcon#wrote, iclass 24, count 0 2006.257.17:34:26.52#ibcon#about to read 3, iclass 24, count 0 2006.257.17:34:26.55#ibcon#read 3, iclass 24, count 0 2006.257.17:34:26.55#ibcon#about to read 4, iclass 24, count 0 2006.257.17:34:26.55#ibcon#read 4, iclass 24, count 0 2006.257.17:34:26.55#ibcon#about to read 5, iclass 24, count 0 2006.257.17:34:26.55#ibcon#read 5, iclass 24, count 0 2006.257.17:34:26.55#ibcon#about to read 6, iclass 24, count 0 2006.257.17:34:26.55#ibcon#read 6, iclass 24, count 0 2006.257.17:34:26.55#ibcon#end of sib2, iclass 24, count 0 2006.257.17:34:26.55#ibcon#*after write, iclass 24, count 0 2006.257.17:34:26.55#ibcon#*before return 0, iclass 24, count 0 2006.257.17:34:26.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:26.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:34:26.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.17:34:26.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.17:34:26.55$vck44/vblo=8,744.99 2006.257.17:34:26.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.17:34:26.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.17:34:26.55#ibcon#ireg 17 cls_cnt 0 2006.257.17:34:26.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:26.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:26.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:26.55#ibcon#enter wrdev, iclass 26, count 0 2006.257.17:34:26.55#ibcon#first serial, iclass 26, count 0 2006.257.17:34:26.55#ibcon#enter sib2, iclass 26, count 0 2006.257.17:34:26.55#ibcon#flushed, iclass 26, count 0 2006.257.17:34:26.55#ibcon#about to write, iclass 26, count 0 2006.257.17:34:26.55#ibcon#wrote, iclass 26, count 0 2006.257.17:34:26.55#ibcon#about to read 3, iclass 26, count 0 2006.257.17:34:26.57#ibcon#read 3, iclass 26, count 0 2006.257.17:34:26.57#ibcon#about to read 4, iclass 26, count 0 2006.257.17:34:26.57#ibcon#read 4, iclass 26, count 0 2006.257.17:34:26.57#ibcon#about to read 5, iclass 26, count 0 2006.257.17:34:26.57#ibcon#read 5, iclass 26, count 0 2006.257.17:34:26.57#ibcon#about to read 6, iclass 26, count 0 2006.257.17:34:26.57#ibcon#read 6, iclass 26, count 0 2006.257.17:34:26.57#ibcon#end of sib2, iclass 26, count 0 2006.257.17:34:26.57#ibcon#*mode == 0, iclass 26, count 0 2006.257.17:34:26.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.17:34:26.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:34:26.57#ibcon#*before write, iclass 26, count 0 2006.257.17:34:26.57#ibcon#enter sib2, iclass 26, count 0 2006.257.17:34:26.57#ibcon#flushed, iclass 26, count 0 2006.257.17:34:26.57#ibcon#about to write, iclass 26, count 0 2006.257.17:34:26.57#ibcon#wrote, iclass 26, count 0 2006.257.17:34:26.57#ibcon#about to read 3, iclass 26, count 0 2006.257.17:34:26.61#ibcon#read 3, iclass 26, count 0 2006.257.17:34:26.61#ibcon#about to read 4, iclass 26, count 0 2006.257.17:34:26.61#ibcon#read 4, iclass 26, count 0 2006.257.17:34:26.61#ibcon#about to read 5, iclass 26, count 0 2006.257.17:34:26.61#ibcon#read 5, iclass 26, count 0 2006.257.17:34:26.61#ibcon#about to read 6, iclass 26, count 0 2006.257.17:34:26.61#ibcon#read 6, iclass 26, count 0 2006.257.17:34:26.61#ibcon#end of sib2, iclass 26, count 0 2006.257.17:34:26.61#ibcon#*after write, iclass 26, count 0 2006.257.17:34:26.61#ibcon#*before return 0, iclass 26, count 0 2006.257.17:34:26.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:26.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:34:26.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.17:34:26.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.17:34:26.61$vck44/vb=8,4 2006.257.17:34:26.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.17:34:26.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.17:34:26.61#ibcon#ireg 11 cls_cnt 2 2006.257.17:34:26.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:26.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:26.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:26.67#ibcon#enter wrdev, iclass 28, count 2 2006.257.17:34:26.67#ibcon#first serial, iclass 28, count 2 2006.257.17:34:26.67#ibcon#enter sib2, iclass 28, count 2 2006.257.17:34:26.67#ibcon#flushed, iclass 28, count 2 2006.257.17:34:26.67#ibcon#about to write, iclass 28, count 2 2006.257.17:34:26.67#ibcon#wrote, iclass 28, count 2 2006.257.17:34:26.67#ibcon#about to read 3, iclass 28, count 2 2006.257.17:34:26.69#ibcon#read 3, iclass 28, count 2 2006.257.17:34:26.69#ibcon#about to read 4, iclass 28, count 2 2006.257.17:34:26.69#ibcon#read 4, iclass 28, count 2 2006.257.17:34:26.69#ibcon#about to read 5, iclass 28, count 2 2006.257.17:34:26.69#ibcon#read 5, iclass 28, count 2 2006.257.17:34:26.69#ibcon#about to read 6, iclass 28, count 2 2006.257.17:34:26.69#ibcon#read 6, iclass 28, count 2 2006.257.17:34:26.69#ibcon#end of sib2, iclass 28, count 2 2006.257.17:34:26.69#ibcon#*mode == 0, iclass 28, count 2 2006.257.17:34:26.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.17:34:26.69#ibcon#[27=AT08-04\r\n] 2006.257.17:34:26.69#ibcon#*before write, iclass 28, count 2 2006.257.17:34:26.69#ibcon#enter sib2, iclass 28, count 2 2006.257.17:34:26.69#ibcon#flushed, iclass 28, count 2 2006.257.17:34:26.69#ibcon#about to write, iclass 28, count 2 2006.257.17:34:26.69#ibcon#wrote, iclass 28, count 2 2006.257.17:34:26.69#ibcon#about to read 3, iclass 28, count 2 2006.257.17:34:26.72#ibcon#read 3, iclass 28, count 2 2006.257.17:34:26.72#ibcon#about to read 4, iclass 28, count 2 2006.257.17:34:26.72#ibcon#read 4, iclass 28, count 2 2006.257.17:34:26.72#ibcon#about to read 5, iclass 28, count 2 2006.257.17:34:26.72#ibcon#read 5, iclass 28, count 2 2006.257.17:34:26.72#ibcon#about to read 6, iclass 28, count 2 2006.257.17:34:26.72#ibcon#read 6, iclass 28, count 2 2006.257.17:34:26.72#ibcon#end of sib2, iclass 28, count 2 2006.257.17:34:26.72#ibcon#*after write, iclass 28, count 2 2006.257.17:34:26.72#ibcon#*before return 0, iclass 28, count 2 2006.257.17:34:26.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:26.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:34:26.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.17:34:26.72#ibcon#ireg 7 cls_cnt 0 2006.257.17:34:26.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:26.84#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:26.84#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:26.84#ibcon#enter wrdev, iclass 28, count 0 2006.257.17:34:26.84#ibcon#first serial, iclass 28, count 0 2006.257.17:34:26.84#ibcon#enter sib2, iclass 28, count 0 2006.257.17:34:26.84#ibcon#flushed, iclass 28, count 0 2006.257.17:34:26.84#ibcon#about to write, iclass 28, count 0 2006.257.17:34:26.84#ibcon#wrote, iclass 28, count 0 2006.257.17:34:26.84#ibcon#about to read 3, iclass 28, count 0 2006.257.17:34:26.86#ibcon#read 3, iclass 28, count 0 2006.257.17:34:26.86#ibcon#about to read 4, iclass 28, count 0 2006.257.17:34:26.86#ibcon#read 4, iclass 28, count 0 2006.257.17:34:26.86#ibcon#about to read 5, iclass 28, count 0 2006.257.17:34:26.86#ibcon#read 5, iclass 28, count 0 2006.257.17:34:26.86#ibcon#about to read 6, iclass 28, count 0 2006.257.17:34:26.86#ibcon#read 6, iclass 28, count 0 2006.257.17:34:26.86#ibcon#end of sib2, iclass 28, count 0 2006.257.17:34:26.86#ibcon#*mode == 0, iclass 28, count 0 2006.257.17:34:26.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.17:34:26.86#ibcon#[27=USB\r\n] 2006.257.17:34:26.86#ibcon#*before write, iclass 28, count 0 2006.257.17:34:26.86#ibcon#enter sib2, iclass 28, count 0 2006.257.17:34:26.86#ibcon#flushed, iclass 28, count 0 2006.257.17:34:26.86#ibcon#about to write, iclass 28, count 0 2006.257.17:34:26.86#ibcon#wrote, iclass 28, count 0 2006.257.17:34:26.86#ibcon#about to read 3, iclass 28, count 0 2006.257.17:34:26.89#ibcon#read 3, iclass 28, count 0 2006.257.17:34:26.89#ibcon#about to read 4, iclass 28, count 0 2006.257.17:34:26.89#ibcon#read 4, iclass 28, count 0 2006.257.17:34:26.89#ibcon#about to read 5, iclass 28, count 0 2006.257.17:34:26.89#ibcon#read 5, iclass 28, count 0 2006.257.17:34:26.89#ibcon#about to read 6, iclass 28, count 0 2006.257.17:34:26.89#ibcon#read 6, iclass 28, count 0 2006.257.17:34:26.89#ibcon#end of sib2, iclass 28, count 0 2006.257.17:34:26.89#ibcon#*after write, iclass 28, count 0 2006.257.17:34:26.89#ibcon#*before return 0, iclass 28, count 0 2006.257.17:34:26.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:26.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:34:26.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.17:34:26.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.17:34:26.89$vck44/vabw=wide 2006.257.17:34:26.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.17:34:26.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.17:34:26.89#ibcon#ireg 8 cls_cnt 0 2006.257.17:34:26.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:26.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:26.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:26.89#ibcon#enter wrdev, iclass 30, count 0 2006.257.17:34:26.89#ibcon#first serial, iclass 30, count 0 2006.257.17:34:26.89#ibcon#enter sib2, iclass 30, count 0 2006.257.17:34:26.89#ibcon#flushed, iclass 30, count 0 2006.257.17:34:26.89#ibcon#about to write, iclass 30, count 0 2006.257.17:34:26.89#ibcon#wrote, iclass 30, count 0 2006.257.17:34:26.89#ibcon#about to read 3, iclass 30, count 0 2006.257.17:34:26.91#ibcon#read 3, iclass 30, count 0 2006.257.17:34:26.91#ibcon#about to read 4, iclass 30, count 0 2006.257.17:34:26.91#ibcon#read 4, iclass 30, count 0 2006.257.17:34:26.91#ibcon#about to read 5, iclass 30, count 0 2006.257.17:34:26.91#ibcon#read 5, iclass 30, count 0 2006.257.17:34:26.91#ibcon#about to read 6, iclass 30, count 0 2006.257.17:34:26.91#ibcon#read 6, iclass 30, count 0 2006.257.17:34:26.91#ibcon#end of sib2, iclass 30, count 0 2006.257.17:34:26.91#ibcon#*mode == 0, iclass 30, count 0 2006.257.17:34:26.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.17:34:26.91#ibcon#[25=BW32\r\n] 2006.257.17:34:26.91#ibcon#*before write, iclass 30, count 0 2006.257.17:34:26.91#ibcon#enter sib2, iclass 30, count 0 2006.257.17:34:26.91#ibcon#flushed, iclass 30, count 0 2006.257.17:34:26.91#ibcon#about to write, iclass 30, count 0 2006.257.17:34:26.91#ibcon#wrote, iclass 30, count 0 2006.257.17:34:26.91#ibcon#about to read 3, iclass 30, count 0 2006.257.17:34:26.94#ibcon#read 3, iclass 30, count 0 2006.257.17:34:26.94#ibcon#about to read 4, iclass 30, count 0 2006.257.17:34:26.94#ibcon#read 4, iclass 30, count 0 2006.257.17:34:26.94#ibcon#about to read 5, iclass 30, count 0 2006.257.17:34:26.94#ibcon#read 5, iclass 30, count 0 2006.257.17:34:26.94#ibcon#about to read 6, iclass 30, count 0 2006.257.17:34:26.94#ibcon#read 6, iclass 30, count 0 2006.257.17:34:26.94#ibcon#end of sib2, iclass 30, count 0 2006.257.17:34:26.94#ibcon#*after write, iclass 30, count 0 2006.257.17:34:26.94#ibcon#*before return 0, iclass 30, count 0 2006.257.17:34:26.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:26.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:34:26.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.17:34:26.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.17:34:26.94$vck44/vbbw=wide 2006.257.17:34:26.94#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.17:34:26.94#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.17:34:26.94#ibcon#ireg 8 cls_cnt 0 2006.257.17:34:26.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:34:27.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:34:27.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:34:27.01#ibcon#enter wrdev, iclass 32, count 0 2006.257.17:34:27.01#ibcon#first serial, iclass 32, count 0 2006.257.17:34:27.01#ibcon#enter sib2, iclass 32, count 0 2006.257.17:34:27.01#ibcon#flushed, iclass 32, count 0 2006.257.17:34:27.01#ibcon#about to write, iclass 32, count 0 2006.257.17:34:27.01#ibcon#wrote, iclass 32, count 0 2006.257.17:34:27.01#ibcon#about to read 3, iclass 32, count 0 2006.257.17:34:27.03#ibcon#read 3, iclass 32, count 0 2006.257.17:34:27.03#ibcon#about to read 4, iclass 32, count 0 2006.257.17:34:27.03#ibcon#read 4, iclass 32, count 0 2006.257.17:34:27.03#ibcon#about to read 5, iclass 32, count 0 2006.257.17:34:27.03#ibcon#read 5, iclass 32, count 0 2006.257.17:34:27.03#ibcon#about to read 6, iclass 32, count 0 2006.257.17:34:27.03#ibcon#read 6, iclass 32, count 0 2006.257.17:34:27.03#ibcon#end of sib2, iclass 32, count 0 2006.257.17:34:27.03#ibcon#*mode == 0, iclass 32, count 0 2006.257.17:34:27.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.17:34:27.03#ibcon#[27=BW32\r\n] 2006.257.17:34:27.03#ibcon#*before write, iclass 32, count 0 2006.257.17:34:27.03#ibcon#enter sib2, iclass 32, count 0 2006.257.17:34:27.03#ibcon#flushed, iclass 32, count 0 2006.257.17:34:27.03#ibcon#about to write, iclass 32, count 0 2006.257.17:34:27.03#ibcon#wrote, iclass 32, count 0 2006.257.17:34:27.03#ibcon#about to read 3, iclass 32, count 0 2006.257.17:34:27.06#ibcon#read 3, iclass 32, count 0 2006.257.17:34:27.06#ibcon#about to read 4, iclass 32, count 0 2006.257.17:34:27.06#ibcon#read 4, iclass 32, count 0 2006.257.17:34:27.06#ibcon#about to read 5, iclass 32, count 0 2006.257.17:34:27.06#ibcon#read 5, iclass 32, count 0 2006.257.17:34:27.06#ibcon#about to read 6, iclass 32, count 0 2006.257.17:34:27.06#ibcon#read 6, iclass 32, count 0 2006.257.17:34:27.06#ibcon#end of sib2, iclass 32, count 0 2006.257.17:34:27.06#ibcon#*after write, iclass 32, count 0 2006.257.17:34:27.06#ibcon#*before return 0, iclass 32, count 0 2006.257.17:34:27.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:34:27.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:34:27.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.17:34:27.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.17:34:27.06$setupk4/ifdk4 2006.257.17:34:27.06$ifdk4/lo= 2006.257.17:34:27.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:34:27.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:34:27.06$ifdk4/patch= 2006.257.17:34:27.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:34:27.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:34:27.06$setupk4/!*+20s 2006.257.17:34:34.14#trakl#Source acquired 2006.257.17:34:35.14#flagr#flagr/antenna,acquired 2006.257.17:34:36.12#abcon#<5=/14 1.6 4.4 17.40 971014.2\r\n> 2006.257.17:34:36.14#abcon#{5=INTERFACE CLEAR} 2006.257.17:34:36.20#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:34:41.57$setupk4/"tpicd 2006.257.17:34:41.57$setupk4/echo=off 2006.257.17:34:41.57$setupk4/xlog=off 2006.257.17:34:41.57:!2006.257.17:36:08 2006.257.17:36:08.00:preob 2006.257.17:36:09.13/onsource/TRACKING 2006.257.17:36:09.13:!2006.257.17:36:18 2006.257.17:36:18.00:"tape 2006.257.17:36:18.00:"st=record 2006.257.17:36:18.00:data_valid=on 2006.257.17:36:18.00:midob 2006.257.17:36:18.13/onsource/TRACKING 2006.257.17:36:18.13/wx/17.39,1014.2,97 2006.257.17:36:18.28/cable/+6.4861E-03 2006.257.17:36:19.37/va/01,08,usb,yes,30,33 2006.257.17:36:19.37/va/02,07,usb,yes,33,33 2006.257.17:36:19.37/va/03,08,usb,yes,29,31 2006.257.17:36:19.37/va/04,07,usb,yes,34,35 2006.257.17:36:19.37/va/05,04,usb,yes,30,31 2006.257.17:36:19.37/va/06,04,usb,yes,34,33 2006.257.17:36:19.37/va/07,04,usb,yes,35,35 2006.257.17:36:19.37/va/08,04,usb,yes,29,35 2006.257.17:36:19.60/valo/01,524.99,yes,locked 2006.257.17:36:19.60/valo/02,534.99,yes,locked 2006.257.17:36:19.60/valo/03,564.99,yes,locked 2006.257.17:36:19.60/valo/04,624.99,yes,locked 2006.257.17:36:19.60/valo/05,734.99,yes,locked 2006.257.17:36:19.60/valo/06,814.99,yes,locked 2006.257.17:36:19.60/valo/07,864.99,yes,locked 2006.257.17:36:19.60/valo/08,884.99,yes,locked 2006.257.17:36:20.69/vb/01,04,usb,yes,31,29 2006.257.17:36:20.69/vb/02,05,usb,yes,29,29 2006.257.17:36:20.69/vb/03,04,usb,yes,30,33 2006.257.17:36:20.69/vb/04,05,usb,yes,31,29 2006.257.17:36:20.69/vb/05,04,usb,yes,27,29 2006.257.17:36:20.69/vb/06,04,usb,yes,32,28 2006.257.17:36:20.69/vb/07,04,usb,yes,31,31 2006.257.17:36:20.69/vb/08,04,usb,yes,29,32 2006.257.17:36:20.93/vblo/01,629.99,yes,locked 2006.257.17:36:20.93/vblo/02,634.99,yes,locked 2006.257.17:36:20.93/vblo/03,649.99,yes,locked 2006.257.17:36:20.93/vblo/04,679.99,yes,locked 2006.257.17:36:20.93/vblo/05,709.99,yes,locked 2006.257.17:36:20.93/vblo/06,719.99,yes,locked 2006.257.17:36:20.93/vblo/07,734.99,yes,locked 2006.257.17:36:20.93/vblo/08,744.99,yes,locked 2006.257.17:36:21.08/vabw/8 2006.257.17:36:21.23/vbbw/8 2006.257.17:36:21.32/xfe/off,on,15.0 2006.257.17:36:21.71/ifatt/23,28,28,28 2006.257.17:36:22.07/fmout-gps/S +4.50E-07 2006.257.17:36:22.11:!2006.257.17:39:08 2006.257.17:39:08.01:data_valid=off 2006.257.17:39:08.01:"et 2006.257.17:39:08.01:!+3s 2006.257.17:39:11.02:"tape 2006.257.17:39:11.02:postob 2006.257.17:39:11.15/cable/+6.4849E-03 2006.257.17:39:11.15/wx/17.38,1014.2,97 2006.257.17:39:11.21/fmout-gps/S +4.52E-07 2006.257.17:39:11.21:scan_name=257-1745,jd0609,110 2006.257.17:39:11.21:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.257.17:39:12.14#flagr#flagr/antenna,new-source 2006.257.17:39:12.14:checkk5 2006.257.17:39:12.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:39:12.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:39:13.15/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:39:13.49/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:39:13.83/chk_obsdata//k5ts1/T2571736??a.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.17:39:14.15/chk_obsdata//k5ts2/T2571736??b.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.17:39:14.49/chk_obsdata//k5ts3/T2571736??c.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.17:39:14.82/chk_obsdata//k5ts4/T2571736??d.dat file size is correct (nominal:680MB, actual:680MB). 2006.257.17:39:15.47/k5log//k5ts1_log_newline 2006.257.17:39:16.13/k5log//k5ts2_log_newline 2006.257.17:39:16.79/k5log//k5ts3_log_newline 2006.257.17:39:17.45/k5log//k5ts4_log_newline 2006.257.17:39:17.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:39:17.47:setupk4=1 2006.257.17:39:17.47$setupk4/echo=on 2006.257.17:39:17.47$setupk4/pcalon 2006.257.17:39:17.47$pcalon/"no phase cal control is implemented here 2006.257.17:39:17.47$setupk4/"tpicd=stop 2006.257.17:39:17.47$setupk4/"rec=synch_on 2006.257.17:39:17.47$setupk4/"rec_mode=128 2006.257.17:39:17.47$setupk4/!* 2006.257.17:39:17.47$setupk4/recpk4 2006.257.17:39:17.47$recpk4/recpatch= 2006.257.17:39:17.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:39:17.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:39:17.48$setupk4/vck44 2006.257.17:39:17.48$vck44/valo=1,524.99 2006.257.17:39:17.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.17:39:17.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.17:39:17.48#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:17.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:17.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:17.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:17.48#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:39:17.48#ibcon#first serial, iclass 3, count 0 2006.257.17:39:17.48#ibcon#enter sib2, iclass 3, count 0 2006.257.17:39:17.48#ibcon#flushed, iclass 3, count 0 2006.257.17:39:17.48#ibcon#about to write, iclass 3, count 0 2006.257.17:39:17.48#ibcon#wrote, iclass 3, count 0 2006.257.17:39:17.48#ibcon#about to read 3, iclass 3, count 0 2006.257.17:39:17.49#ibcon#read 3, iclass 3, count 0 2006.257.17:39:17.49#ibcon#about to read 4, iclass 3, count 0 2006.257.17:39:17.49#ibcon#read 4, iclass 3, count 0 2006.257.17:39:17.49#ibcon#about to read 5, iclass 3, count 0 2006.257.17:39:17.49#ibcon#read 5, iclass 3, count 0 2006.257.17:39:17.49#ibcon#about to read 6, iclass 3, count 0 2006.257.17:39:17.49#ibcon#read 6, iclass 3, count 0 2006.257.17:39:17.49#ibcon#end of sib2, iclass 3, count 0 2006.257.17:39:17.49#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:39:17.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:39:17.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:39:17.49#ibcon#*before write, iclass 3, count 0 2006.257.17:39:17.49#ibcon#enter sib2, iclass 3, count 0 2006.257.17:39:17.49#ibcon#flushed, iclass 3, count 0 2006.257.17:39:17.49#ibcon#about to write, iclass 3, count 0 2006.257.17:39:17.49#ibcon#wrote, iclass 3, count 0 2006.257.17:39:17.49#ibcon#about to read 3, iclass 3, count 0 2006.257.17:39:17.54#ibcon#read 3, iclass 3, count 0 2006.257.17:39:17.54#ibcon#about to read 4, iclass 3, count 0 2006.257.17:39:17.54#ibcon#read 4, iclass 3, count 0 2006.257.17:39:17.54#ibcon#about to read 5, iclass 3, count 0 2006.257.17:39:17.54#ibcon#read 5, iclass 3, count 0 2006.257.17:39:17.54#ibcon#about to read 6, iclass 3, count 0 2006.257.17:39:17.54#ibcon#read 6, iclass 3, count 0 2006.257.17:39:17.54#ibcon#end of sib2, iclass 3, count 0 2006.257.17:39:17.54#ibcon#*after write, iclass 3, count 0 2006.257.17:39:17.54#ibcon#*before return 0, iclass 3, count 0 2006.257.17:39:17.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:17.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:17.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:39:17.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:39:17.54$vck44/va=1,8 2006.257.17:39:17.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.17:39:17.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.17:39:17.54#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:17.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:17.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:17.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:17.54#ibcon#enter wrdev, iclass 5, count 2 2006.257.17:39:17.54#ibcon#first serial, iclass 5, count 2 2006.257.17:39:17.54#ibcon#enter sib2, iclass 5, count 2 2006.257.17:39:17.54#ibcon#flushed, iclass 5, count 2 2006.257.17:39:17.54#ibcon#about to write, iclass 5, count 2 2006.257.17:39:17.54#ibcon#wrote, iclass 5, count 2 2006.257.17:39:17.54#ibcon#about to read 3, iclass 5, count 2 2006.257.17:39:17.56#ibcon#read 3, iclass 5, count 2 2006.257.17:39:17.56#ibcon#about to read 4, iclass 5, count 2 2006.257.17:39:17.56#ibcon#read 4, iclass 5, count 2 2006.257.17:39:17.56#ibcon#about to read 5, iclass 5, count 2 2006.257.17:39:17.56#ibcon#read 5, iclass 5, count 2 2006.257.17:39:17.56#ibcon#about to read 6, iclass 5, count 2 2006.257.17:39:17.56#ibcon#read 6, iclass 5, count 2 2006.257.17:39:17.56#ibcon#end of sib2, iclass 5, count 2 2006.257.17:39:17.56#ibcon#*mode == 0, iclass 5, count 2 2006.257.17:39:17.56#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.17:39:17.56#ibcon#[25=AT01-08\r\n] 2006.257.17:39:17.56#ibcon#*before write, iclass 5, count 2 2006.257.17:39:17.56#ibcon#enter sib2, iclass 5, count 2 2006.257.17:39:17.56#ibcon#flushed, iclass 5, count 2 2006.257.17:39:17.56#ibcon#about to write, iclass 5, count 2 2006.257.17:39:17.56#ibcon#wrote, iclass 5, count 2 2006.257.17:39:17.56#ibcon#about to read 3, iclass 5, count 2 2006.257.17:39:17.59#ibcon#read 3, iclass 5, count 2 2006.257.17:39:17.59#ibcon#about to read 4, iclass 5, count 2 2006.257.17:39:17.59#ibcon#read 4, iclass 5, count 2 2006.257.17:39:17.59#ibcon#about to read 5, iclass 5, count 2 2006.257.17:39:17.59#ibcon#read 5, iclass 5, count 2 2006.257.17:39:17.59#ibcon#about to read 6, iclass 5, count 2 2006.257.17:39:17.59#ibcon#read 6, iclass 5, count 2 2006.257.17:39:17.59#ibcon#end of sib2, iclass 5, count 2 2006.257.17:39:17.59#ibcon#*after write, iclass 5, count 2 2006.257.17:39:17.59#ibcon#*before return 0, iclass 5, count 2 2006.257.17:39:17.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:17.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:17.59#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.17:39:17.59#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:17.59#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:17.71#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:17.71#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:17.71#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:39:17.71#ibcon#first serial, iclass 5, count 0 2006.257.17:39:17.71#ibcon#enter sib2, iclass 5, count 0 2006.257.17:39:17.71#ibcon#flushed, iclass 5, count 0 2006.257.17:39:17.71#ibcon#about to write, iclass 5, count 0 2006.257.17:39:17.71#ibcon#wrote, iclass 5, count 0 2006.257.17:39:17.71#ibcon#about to read 3, iclass 5, count 0 2006.257.17:39:17.73#ibcon#read 3, iclass 5, count 0 2006.257.17:39:17.73#ibcon#about to read 4, iclass 5, count 0 2006.257.17:39:17.73#ibcon#read 4, iclass 5, count 0 2006.257.17:39:17.73#ibcon#about to read 5, iclass 5, count 0 2006.257.17:39:17.73#ibcon#read 5, iclass 5, count 0 2006.257.17:39:17.73#ibcon#about to read 6, iclass 5, count 0 2006.257.17:39:17.73#ibcon#read 6, iclass 5, count 0 2006.257.17:39:17.73#ibcon#end of sib2, iclass 5, count 0 2006.257.17:39:17.73#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:39:17.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:39:17.73#ibcon#[25=USB\r\n] 2006.257.17:39:17.73#ibcon#*before write, iclass 5, count 0 2006.257.17:39:17.73#ibcon#enter sib2, iclass 5, count 0 2006.257.17:39:17.73#ibcon#flushed, iclass 5, count 0 2006.257.17:39:17.73#ibcon#about to write, iclass 5, count 0 2006.257.17:39:17.73#ibcon#wrote, iclass 5, count 0 2006.257.17:39:17.73#ibcon#about to read 3, iclass 5, count 0 2006.257.17:39:17.76#ibcon#read 3, iclass 5, count 0 2006.257.17:39:17.76#ibcon#about to read 4, iclass 5, count 0 2006.257.17:39:17.76#ibcon#read 4, iclass 5, count 0 2006.257.17:39:17.76#ibcon#about to read 5, iclass 5, count 0 2006.257.17:39:17.76#ibcon#read 5, iclass 5, count 0 2006.257.17:39:17.76#ibcon#about to read 6, iclass 5, count 0 2006.257.17:39:17.76#ibcon#read 6, iclass 5, count 0 2006.257.17:39:17.76#ibcon#end of sib2, iclass 5, count 0 2006.257.17:39:17.76#ibcon#*after write, iclass 5, count 0 2006.257.17:39:17.76#ibcon#*before return 0, iclass 5, count 0 2006.257.17:39:17.76#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:17.76#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:17.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:39:17.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:39:17.76$vck44/valo=2,534.99 2006.257.17:39:17.76#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.17:39:17.76#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.17:39:17.76#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:17.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:17.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:17.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:17.76#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:39:17.76#ibcon#first serial, iclass 7, count 0 2006.257.17:39:17.76#ibcon#enter sib2, iclass 7, count 0 2006.257.17:39:17.76#ibcon#flushed, iclass 7, count 0 2006.257.17:39:17.76#ibcon#about to write, iclass 7, count 0 2006.257.17:39:17.76#ibcon#wrote, iclass 7, count 0 2006.257.17:39:17.76#ibcon#about to read 3, iclass 7, count 0 2006.257.17:39:17.78#ibcon#read 3, iclass 7, count 0 2006.257.17:39:17.78#ibcon#about to read 4, iclass 7, count 0 2006.257.17:39:17.78#ibcon#read 4, iclass 7, count 0 2006.257.17:39:17.78#ibcon#about to read 5, iclass 7, count 0 2006.257.17:39:17.78#ibcon#read 5, iclass 7, count 0 2006.257.17:39:17.78#ibcon#about to read 6, iclass 7, count 0 2006.257.17:39:17.78#ibcon#read 6, iclass 7, count 0 2006.257.17:39:17.78#ibcon#end of sib2, iclass 7, count 0 2006.257.17:39:17.78#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:39:17.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:39:17.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:39:17.78#ibcon#*before write, iclass 7, count 0 2006.257.17:39:17.78#ibcon#enter sib2, iclass 7, count 0 2006.257.17:39:17.78#ibcon#flushed, iclass 7, count 0 2006.257.17:39:17.78#ibcon#about to write, iclass 7, count 0 2006.257.17:39:17.78#ibcon#wrote, iclass 7, count 0 2006.257.17:39:17.78#ibcon#about to read 3, iclass 7, count 0 2006.257.17:39:17.82#ibcon#read 3, iclass 7, count 0 2006.257.17:39:17.82#ibcon#about to read 4, iclass 7, count 0 2006.257.17:39:17.82#ibcon#read 4, iclass 7, count 0 2006.257.17:39:17.82#ibcon#about to read 5, iclass 7, count 0 2006.257.17:39:17.82#ibcon#read 5, iclass 7, count 0 2006.257.17:39:17.82#ibcon#about to read 6, iclass 7, count 0 2006.257.17:39:17.82#ibcon#read 6, iclass 7, count 0 2006.257.17:39:17.82#ibcon#end of sib2, iclass 7, count 0 2006.257.17:39:17.82#ibcon#*after write, iclass 7, count 0 2006.257.17:39:17.82#ibcon#*before return 0, iclass 7, count 0 2006.257.17:39:17.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:17.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:17.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:39:17.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:39:17.82$vck44/va=2,7 2006.257.17:39:17.82#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.17:39:17.82#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.17:39:17.82#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:17.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:17.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:17.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:17.88#ibcon#enter wrdev, iclass 11, count 2 2006.257.17:39:17.88#ibcon#first serial, iclass 11, count 2 2006.257.17:39:17.88#ibcon#enter sib2, iclass 11, count 2 2006.257.17:39:17.88#ibcon#flushed, iclass 11, count 2 2006.257.17:39:17.88#ibcon#about to write, iclass 11, count 2 2006.257.17:39:17.88#ibcon#wrote, iclass 11, count 2 2006.257.17:39:17.88#ibcon#about to read 3, iclass 11, count 2 2006.257.17:39:17.90#ibcon#read 3, iclass 11, count 2 2006.257.17:39:17.90#ibcon#about to read 4, iclass 11, count 2 2006.257.17:39:17.90#ibcon#read 4, iclass 11, count 2 2006.257.17:39:17.90#ibcon#about to read 5, iclass 11, count 2 2006.257.17:39:17.90#ibcon#read 5, iclass 11, count 2 2006.257.17:39:17.90#ibcon#about to read 6, iclass 11, count 2 2006.257.17:39:17.90#ibcon#read 6, iclass 11, count 2 2006.257.17:39:17.90#ibcon#end of sib2, iclass 11, count 2 2006.257.17:39:17.90#ibcon#*mode == 0, iclass 11, count 2 2006.257.17:39:17.90#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.17:39:17.90#ibcon#[25=AT02-07\r\n] 2006.257.17:39:17.90#ibcon#*before write, iclass 11, count 2 2006.257.17:39:17.90#ibcon#enter sib2, iclass 11, count 2 2006.257.17:39:17.90#ibcon#flushed, iclass 11, count 2 2006.257.17:39:17.90#ibcon#about to write, iclass 11, count 2 2006.257.17:39:17.90#ibcon#wrote, iclass 11, count 2 2006.257.17:39:17.90#ibcon#about to read 3, iclass 11, count 2 2006.257.17:39:17.93#ibcon#read 3, iclass 11, count 2 2006.257.17:39:17.93#ibcon#about to read 4, iclass 11, count 2 2006.257.17:39:17.93#ibcon#read 4, iclass 11, count 2 2006.257.17:39:17.93#ibcon#about to read 5, iclass 11, count 2 2006.257.17:39:17.93#ibcon#read 5, iclass 11, count 2 2006.257.17:39:17.93#ibcon#about to read 6, iclass 11, count 2 2006.257.17:39:17.93#ibcon#read 6, iclass 11, count 2 2006.257.17:39:17.93#ibcon#end of sib2, iclass 11, count 2 2006.257.17:39:17.93#ibcon#*after write, iclass 11, count 2 2006.257.17:39:17.93#ibcon#*before return 0, iclass 11, count 2 2006.257.17:39:17.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:17.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:17.93#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.17:39:17.93#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:17.93#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:18.05#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:18.05#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:18.05#ibcon#enter wrdev, iclass 11, count 0 2006.257.17:39:18.05#ibcon#first serial, iclass 11, count 0 2006.257.17:39:18.05#ibcon#enter sib2, iclass 11, count 0 2006.257.17:39:18.05#ibcon#flushed, iclass 11, count 0 2006.257.17:39:18.05#ibcon#about to write, iclass 11, count 0 2006.257.17:39:18.05#ibcon#wrote, iclass 11, count 0 2006.257.17:39:18.05#ibcon#about to read 3, iclass 11, count 0 2006.257.17:39:18.07#ibcon#read 3, iclass 11, count 0 2006.257.17:39:18.07#ibcon#about to read 4, iclass 11, count 0 2006.257.17:39:18.07#ibcon#read 4, iclass 11, count 0 2006.257.17:39:18.07#ibcon#about to read 5, iclass 11, count 0 2006.257.17:39:18.07#ibcon#read 5, iclass 11, count 0 2006.257.17:39:18.07#ibcon#about to read 6, iclass 11, count 0 2006.257.17:39:18.07#ibcon#read 6, iclass 11, count 0 2006.257.17:39:18.07#ibcon#end of sib2, iclass 11, count 0 2006.257.17:39:18.07#ibcon#*mode == 0, iclass 11, count 0 2006.257.17:39:18.07#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.17:39:18.07#ibcon#[25=USB\r\n] 2006.257.17:39:18.07#ibcon#*before write, iclass 11, count 0 2006.257.17:39:18.07#ibcon#enter sib2, iclass 11, count 0 2006.257.17:39:18.07#ibcon#flushed, iclass 11, count 0 2006.257.17:39:18.07#ibcon#about to write, iclass 11, count 0 2006.257.17:39:18.07#ibcon#wrote, iclass 11, count 0 2006.257.17:39:18.07#ibcon#about to read 3, iclass 11, count 0 2006.257.17:39:18.10#ibcon#read 3, iclass 11, count 0 2006.257.17:39:18.10#ibcon#about to read 4, iclass 11, count 0 2006.257.17:39:18.10#ibcon#read 4, iclass 11, count 0 2006.257.17:39:18.10#ibcon#about to read 5, iclass 11, count 0 2006.257.17:39:18.10#ibcon#read 5, iclass 11, count 0 2006.257.17:39:18.10#ibcon#about to read 6, iclass 11, count 0 2006.257.17:39:18.10#ibcon#read 6, iclass 11, count 0 2006.257.17:39:18.10#ibcon#end of sib2, iclass 11, count 0 2006.257.17:39:18.10#ibcon#*after write, iclass 11, count 0 2006.257.17:39:18.10#ibcon#*before return 0, iclass 11, count 0 2006.257.17:39:18.10#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:18.10#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:18.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.17:39:18.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.17:39:18.10$vck44/valo=3,564.99 2006.257.17:39:18.10#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.17:39:18.10#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.17:39:18.10#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:18.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:39:18.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:39:18.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:39:18.10#ibcon#enter wrdev, iclass 13, count 0 2006.257.17:39:18.10#ibcon#first serial, iclass 13, count 0 2006.257.17:39:18.10#ibcon#enter sib2, iclass 13, count 0 2006.257.17:39:18.10#ibcon#flushed, iclass 13, count 0 2006.257.17:39:18.10#ibcon#about to write, iclass 13, count 0 2006.257.17:39:18.10#ibcon#wrote, iclass 13, count 0 2006.257.17:39:18.10#ibcon#about to read 3, iclass 13, count 0 2006.257.17:39:18.12#ibcon#read 3, iclass 13, count 0 2006.257.17:39:18.12#ibcon#about to read 4, iclass 13, count 0 2006.257.17:39:18.12#ibcon#read 4, iclass 13, count 0 2006.257.17:39:18.12#ibcon#about to read 5, iclass 13, count 0 2006.257.17:39:18.12#ibcon#read 5, iclass 13, count 0 2006.257.17:39:18.12#ibcon#about to read 6, iclass 13, count 0 2006.257.17:39:18.12#ibcon#read 6, iclass 13, count 0 2006.257.17:39:18.12#ibcon#end of sib2, iclass 13, count 0 2006.257.17:39:18.12#ibcon#*mode == 0, iclass 13, count 0 2006.257.17:39:18.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.17:39:18.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:39:18.12#ibcon#*before write, iclass 13, count 0 2006.257.17:39:18.12#ibcon#enter sib2, iclass 13, count 0 2006.257.17:39:18.12#ibcon#flushed, iclass 13, count 0 2006.257.17:39:18.12#ibcon#about to write, iclass 13, count 0 2006.257.17:39:18.12#ibcon#wrote, iclass 13, count 0 2006.257.17:39:18.12#ibcon#about to read 3, iclass 13, count 0 2006.257.17:39:18.16#ibcon#read 3, iclass 13, count 0 2006.257.17:39:18.16#ibcon#about to read 4, iclass 13, count 0 2006.257.17:39:18.16#ibcon#read 4, iclass 13, count 0 2006.257.17:39:18.16#ibcon#about to read 5, iclass 13, count 0 2006.257.17:39:18.16#ibcon#read 5, iclass 13, count 0 2006.257.17:39:18.16#ibcon#about to read 6, iclass 13, count 0 2006.257.17:39:18.16#ibcon#read 6, iclass 13, count 0 2006.257.17:39:18.16#ibcon#end of sib2, iclass 13, count 0 2006.257.17:39:18.16#ibcon#*after write, iclass 13, count 0 2006.257.17:39:18.16#ibcon#*before return 0, iclass 13, count 0 2006.257.17:39:18.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:39:18.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.17:39:18.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.17:39:18.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.17:39:18.16$vck44/va=3,8 2006.257.17:39:18.16#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.17:39:18.16#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.17:39:18.16#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:18.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:39:18.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:39:18.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:39:18.22#ibcon#enter wrdev, iclass 15, count 2 2006.257.17:39:18.22#ibcon#first serial, iclass 15, count 2 2006.257.17:39:18.22#ibcon#enter sib2, iclass 15, count 2 2006.257.17:39:18.22#ibcon#flushed, iclass 15, count 2 2006.257.17:39:18.22#ibcon#about to write, iclass 15, count 2 2006.257.17:39:18.22#ibcon#wrote, iclass 15, count 2 2006.257.17:39:18.22#ibcon#about to read 3, iclass 15, count 2 2006.257.17:39:18.24#ibcon#read 3, iclass 15, count 2 2006.257.17:39:18.24#ibcon#about to read 4, iclass 15, count 2 2006.257.17:39:18.24#ibcon#read 4, iclass 15, count 2 2006.257.17:39:18.24#ibcon#about to read 5, iclass 15, count 2 2006.257.17:39:18.24#ibcon#read 5, iclass 15, count 2 2006.257.17:39:18.24#ibcon#about to read 6, iclass 15, count 2 2006.257.17:39:18.24#ibcon#read 6, iclass 15, count 2 2006.257.17:39:18.24#ibcon#end of sib2, iclass 15, count 2 2006.257.17:39:18.24#ibcon#*mode == 0, iclass 15, count 2 2006.257.17:39:18.24#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.17:39:18.24#ibcon#[25=AT03-08\r\n] 2006.257.17:39:18.24#ibcon#*before write, iclass 15, count 2 2006.257.17:39:18.24#ibcon#enter sib2, iclass 15, count 2 2006.257.17:39:18.24#ibcon#flushed, iclass 15, count 2 2006.257.17:39:18.24#ibcon#about to write, iclass 15, count 2 2006.257.17:39:18.24#ibcon#wrote, iclass 15, count 2 2006.257.17:39:18.24#ibcon#about to read 3, iclass 15, count 2 2006.257.17:39:18.27#ibcon#read 3, iclass 15, count 2 2006.257.17:39:18.27#ibcon#about to read 4, iclass 15, count 2 2006.257.17:39:18.27#ibcon#read 4, iclass 15, count 2 2006.257.17:39:18.27#ibcon#about to read 5, iclass 15, count 2 2006.257.17:39:18.27#ibcon#read 5, iclass 15, count 2 2006.257.17:39:18.27#ibcon#about to read 6, iclass 15, count 2 2006.257.17:39:18.27#ibcon#read 6, iclass 15, count 2 2006.257.17:39:18.27#ibcon#end of sib2, iclass 15, count 2 2006.257.17:39:18.27#ibcon#*after write, iclass 15, count 2 2006.257.17:39:18.27#ibcon#*before return 0, iclass 15, count 2 2006.257.17:39:18.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:39:18.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.17:39:18.27#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.17:39:18.27#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:18.27#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:39:18.39#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:39:18.39#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:39:18.39#ibcon#enter wrdev, iclass 15, count 0 2006.257.17:39:18.39#ibcon#first serial, iclass 15, count 0 2006.257.17:39:18.39#ibcon#enter sib2, iclass 15, count 0 2006.257.17:39:18.39#ibcon#flushed, iclass 15, count 0 2006.257.17:39:18.39#ibcon#about to write, iclass 15, count 0 2006.257.17:39:18.39#ibcon#wrote, iclass 15, count 0 2006.257.17:39:18.39#ibcon#about to read 3, iclass 15, count 0 2006.257.17:39:18.41#ibcon#read 3, iclass 15, count 0 2006.257.17:39:18.41#ibcon#about to read 4, iclass 15, count 0 2006.257.17:39:18.41#ibcon#read 4, iclass 15, count 0 2006.257.17:39:18.41#ibcon#about to read 5, iclass 15, count 0 2006.257.17:39:18.41#ibcon#read 5, iclass 15, count 0 2006.257.17:39:18.41#ibcon#about to read 6, iclass 15, count 0 2006.257.17:39:18.41#ibcon#read 6, iclass 15, count 0 2006.257.17:39:18.41#ibcon#end of sib2, iclass 15, count 0 2006.257.17:39:18.41#ibcon#*mode == 0, iclass 15, count 0 2006.257.17:39:18.41#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.17:39:18.41#ibcon#[25=USB\r\n] 2006.257.17:39:18.41#ibcon#*before write, iclass 15, count 0 2006.257.17:39:18.41#ibcon#enter sib2, iclass 15, count 0 2006.257.17:39:18.41#ibcon#flushed, iclass 15, count 0 2006.257.17:39:18.41#ibcon#about to write, iclass 15, count 0 2006.257.17:39:18.41#ibcon#wrote, iclass 15, count 0 2006.257.17:39:18.41#ibcon#about to read 3, iclass 15, count 0 2006.257.17:39:18.44#ibcon#read 3, iclass 15, count 0 2006.257.17:39:18.44#ibcon#about to read 4, iclass 15, count 0 2006.257.17:39:18.44#ibcon#read 4, iclass 15, count 0 2006.257.17:39:18.44#ibcon#about to read 5, iclass 15, count 0 2006.257.17:39:18.44#ibcon#read 5, iclass 15, count 0 2006.257.17:39:18.44#ibcon#about to read 6, iclass 15, count 0 2006.257.17:39:18.44#ibcon#read 6, iclass 15, count 0 2006.257.17:39:18.44#ibcon#end of sib2, iclass 15, count 0 2006.257.17:39:18.44#ibcon#*after write, iclass 15, count 0 2006.257.17:39:18.44#ibcon#*before return 0, iclass 15, count 0 2006.257.17:39:18.44#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:39:18.44#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.17:39:18.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.17:39:18.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.17:39:18.44$vck44/valo=4,624.99 2006.257.17:39:18.44#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.17:39:18.44#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.17:39:18.44#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:18.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:18.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:18.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:18.44#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:39:18.44#ibcon#first serial, iclass 17, count 0 2006.257.17:39:18.44#ibcon#enter sib2, iclass 17, count 0 2006.257.17:39:18.44#ibcon#flushed, iclass 17, count 0 2006.257.17:39:18.44#ibcon#about to write, iclass 17, count 0 2006.257.17:39:18.44#ibcon#wrote, iclass 17, count 0 2006.257.17:39:18.44#ibcon#about to read 3, iclass 17, count 0 2006.257.17:39:18.46#ibcon#read 3, iclass 17, count 0 2006.257.17:39:18.46#ibcon#about to read 4, iclass 17, count 0 2006.257.17:39:18.46#ibcon#read 4, iclass 17, count 0 2006.257.17:39:18.46#ibcon#about to read 5, iclass 17, count 0 2006.257.17:39:18.46#ibcon#read 5, iclass 17, count 0 2006.257.17:39:18.46#ibcon#about to read 6, iclass 17, count 0 2006.257.17:39:18.46#ibcon#read 6, iclass 17, count 0 2006.257.17:39:18.46#ibcon#end of sib2, iclass 17, count 0 2006.257.17:39:18.46#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:39:18.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:39:18.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:39:18.46#ibcon#*before write, iclass 17, count 0 2006.257.17:39:18.46#ibcon#enter sib2, iclass 17, count 0 2006.257.17:39:18.46#ibcon#flushed, iclass 17, count 0 2006.257.17:39:18.46#ibcon#about to write, iclass 17, count 0 2006.257.17:39:18.46#ibcon#wrote, iclass 17, count 0 2006.257.17:39:18.46#ibcon#about to read 3, iclass 17, count 0 2006.257.17:39:18.50#ibcon#read 3, iclass 17, count 0 2006.257.17:39:18.50#ibcon#about to read 4, iclass 17, count 0 2006.257.17:39:18.50#ibcon#read 4, iclass 17, count 0 2006.257.17:39:18.50#ibcon#about to read 5, iclass 17, count 0 2006.257.17:39:18.50#ibcon#read 5, iclass 17, count 0 2006.257.17:39:18.50#ibcon#about to read 6, iclass 17, count 0 2006.257.17:39:18.50#ibcon#read 6, iclass 17, count 0 2006.257.17:39:18.50#ibcon#end of sib2, iclass 17, count 0 2006.257.17:39:18.50#ibcon#*after write, iclass 17, count 0 2006.257.17:39:18.50#ibcon#*before return 0, iclass 17, count 0 2006.257.17:39:18.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:18.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:18.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:39:18.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:39:18.50$vck44/va=4,7 2006.257.17:39:18.50#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.17:39:18.50#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.17:39:18.50#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:18.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:18.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:18.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:18.56#ibcon#enter wrdev, iclass 19, count 2 2006.257.17:39:18.56#ibcon#first serial, iclass 19, count 2 2006.257.17:39:18.56#ibcon#enter sib2, iclass 19, count 2 2006.257.17:39:18.56#ibcon#flushed, iclass 19, count 2 2006.257.17:39:18.56#ibcon#about to write, iclass 19, count 2 2006.257.17:39:18.56#ibcon#wrote, iclass 19, count 2 2006.257.17:39:18.56#ibcon#about to read 3, iclass 19, count 2 2006.257.17:39:18.58#ibcon#read 3, iclass 19, count 2 2006.257.17:39:18.58#ibcon#about to read 4, iclass 19, count 2 2006.257.17:39:18.58#ibcon#read 4, iclass 19, count 2 2006.257.17:39:18.58#ibcon#about to read 5, iclass 19, count 2 2006.257.17:39:18.58#ibcon#read 5, iclass 19, count 2 2006.257.17:39:18.58#ibcon#about to read 6, iclass 19, count 2 2006.257.17:39:18.58#ibcon#read 6, iclass 19, count 2 2006.257.17:39:18.58#ibcon#end of sib2, iclass 19, count 2 2006.257.17:39:18.58#ibcon#*mode == 0, iclass 19, count 2 2006.257.17:39:18.58#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.17:39:18.58#ibcon#[25=AT04-07\r\n] 2006.257.17:39:18.58#ibcon#*before write, iclass 19, count 2 2006.257.17:39:18.58#ibcon#enter sib2, iclass 19, count 2 2006.257.17:39:18.58#ibcon#flushed, iclass 19, count 2 2006.257.17:39:18.58#ibcon#about to write, iclass 19, count 2 2006.257.17:39:18.58#ibcon#wrote, iclass 19, count 2 2006.257.17:39:18.58#ibcon#about to read 3, iclass 19, count 2 2006.257.17:39:18.61#ibcon#read 3, iclass 19, count 2 2006.257.17:39:18.61#ibcon#about to read 4, iclass 19, count 2 2006.257.17:39:18.61#ibcon#read 4, iclass 19, count 2 2006.257.17:39:18.61#ibcon#about to read 5, iclass 19, count 2 2006.257.17:39:18.61#ibcon#read 5, iclass 19, count 2 2006.257.17:39:18.61#ibcon#about to read 6, iclass 19, count 2 2006.257.17:39:18.61#ibcon#read 6, iclass 19, count 2 2006.257.17:39:18.61#ibcon#end of sib2, iclass 19, count 2 2006.257.17:39:18.61#ibcon#*after write, iclass 19, count 2 2006.257.17:39:18.61#ibcon#*before return 0, iclass 19, count 2 2006.257.17:39:18.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:18.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:18.61#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.17:39:18.61#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:18.61#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:18.73#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:18.73#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:18.73#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:39:18.73#ibcon#first serial, iclass 19, count 0 2006.257.17:39:18.73#ibcon#enter sib2, iclass 19, count 0 2006.257.17:39:18.73#ibcon#flushed, iclass 19, count 0 2006.257.17:39:18.73#ibcon#about to write, iclass 19, count 0 2006.257.17:39:18.73#ibcon#wrote, iclass 19, count 0 2006.257.17:39:18.73#ibcon#about to read 3, iclass 19, count 0 2006.257.17:39:18.75#ibcon#read 3, iclass 19, count 0 2006.257.17:39:18.75#ibcon#about to read 4, iclass 19, count 0 2006.257.17:39:18.75#ibcon#read 4, iclass 19, count 0 2006.257.17:39:18.75#ibcon#about to read 5, iclass 19, count 0 2006.257.17:39:18.75#ibcon#read 5, iclass 19, count 0 2006.257.17:39:18.75#ibcon#about to read 6, iclass 19, count 0 2006.257.17:39:18.75#ibcon#read 6, iclass 19, count 0 2006.257.17:39:18.75#ibcon#end of sib2, iclass 19, count 0 2006.257.17:39:18.75#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:39:18.75#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:39:18.75#ibcon#[25=USB\r\n] 2006.257.17:39:18.75#ibcon#*before write, iclass 19, count 0 2006.257.17:39:18.75#ibcon#enter sib2, iclass 19, count 0 2006.257.17:39:18.75#ibcon#flushed, iclass 19, count 0 2006.257.17:39:18.75#ibcon#about to write, iclass 19, count 0 2006.257.17:39:18.75#ibcon#wrote, iclass 19, count 0 2006.257.17:39:18.75#ibcon#about to read 3, iclass 19, count 0 2006.257.17:39:18.78#ibcon#read 3, iclass 19, count 0 2006.257.17:39:18.78#ibcon#about to read 4, iclass 19, count 0 2006.257.17:39:18.78#ibcon#read 4, iclass 19, count 0 2006.257.17:39:18.78#ibcon#about to read 5, iclass 19, count 0 2006.257.17:39:18.78#ibcon#read 5, iclass 19, count 0 2006.257.17:39:18.78#ibcon#about to read 6, iclass 19, count 0 2006.257.17:39:18.78#ibcon#read 6, iclass 19, count 0 2006.257.17:39:18.78#ibcon#end of sib2, iclass 19, count 0 2006.257.17:39:18.78#ibcon#*after write, iclass 19, count 0 2006.257.17:39:18.78#ibcon#*before return 0, iclass 19, count 0 2006.257.17:39:18.78#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:18.78#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:18.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:39:18.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:39:18.78$vck44/valo=5,734.99 2006.257.17:39:18.78#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.17:39:18.78#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.17:39:18.78#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:18.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:18.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:18.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:18.78#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:39:18.78#ibcon#first serial, iclass 21, count 0 2006.257.17:39:18.78#ibcon#enter sib2, iclass 21, count 0 2006.257.17:39:18.78#ibcon#flushed, iclass 21, count 0 2006.257.17:39:18.78#ibcon#about to write, iclass 21, count 0 2006.257.17:39:18.78#ibcon#wrote, iclass 21, count 0 2006.257.17:39:18.78#ibcon#about to read 3, iclass 21, count 0 2006.257.17:39:18.80#ibcon#read 3, iclass 21, count 0 2006.257.17:39:18.80#ibcon#about to read 4, iclass 21, count 0 2006.257.17:39:18.80#ibcon#read 4, iclass 21, count 0 2006.257.17:39:18.80#ibcon#about to read 5, iclass 21, count 0 2006.257.17:39:18.80#ibcon#read 5, iclass 21, count 0 2006.257.17:39:18.80#ibcon#about to read 6, iclass 21, count 0 2006.257.17:39:18.80#ibcon#read 6, iclass 21, count 0 2006.257.17:39:18.80#ibcon#end of sib2, iclass 21, count 0 2006.257.17:39:18.80#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:39:18.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:39:18.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:39:18.80#ibcon#*before write, iclass 21, count 0 2006.257.17:39:18.80#ibcon#enter sib2, iclass 21, count 0 2006.257.17:39:18.80#ibcon#flushed, iclass 21, count 0 2006.257.17:39:18.80#ibcon#about to write, iclass 21, count 0 2006.257.17:39:18.80#ibcon#wrote, iclass 21, count 0 2006.257.17:39:18.80#ibcon#about to read 3, iclass 21, count 0 2006.257.17:39:18.84#ibcon#read 3, iclass 21, count 0 2006.257.17:39:18.84#ibcon#about to read 4, iclass 21, count 0 2006.257.17:39:18.84#ibcon#read 4, iclass 21, count 0 2006.257.17:39:18.84#ibcon#about to read 5, iclass 21, count 0 2006.257.17:39:18.84#ibcon#read 5, iclass 21, count 0 2006.257.17:39:18.84#ibcon#about to read 6, iclass 21, count 0 2006.257.17:39:18.84#ibcon#read 6, iclass 21, count 0 2006.257.17:39:18.84#ibcon#end of sib2, iclass 21, count 0 2006.257.17:39:18.84#ibcon#*after write, iclass 21, count 0 2006.257.17:39:18.84#ibcon#*before return 0, iclass 21, count 0 2006.257.17:39:18.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:18.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:18.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:39:18.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:39:18.84$vck44/va=5,4 2006.257.17:39:18.84#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.17:39:18.84#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.17:39:18.84#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:18.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:18.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:18.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:18.90#ibcon#enter wrdev, iclass 23, count 2 2006.257.17:39:18.90#ibcon#first serial, iclass 23, count 2 2006.257.17:39:18.90#ibcon#enter sib2, iclass 23, count 2 2006.257.17:39:18.90#ibcon#flushed, iclass 23, count 2 2006.257.17:39:18.90#ibcon#about to write, iclass 23, count 2 2006.257.17:39:18.90#ibcon#wrote, iclass 23, count 2 2006.257.17:39:18.90#ibcon#about to read 3, iclass 23, count 2 2006.257.17:39:18.92#ibcon#read 3, iclass 23, count 2 2006.257.17:39:18.92#ibcon#about to read 4, iclass 23, count 2 2006.257.17:39:18.92#ibcon#read 4, iclass 23, count 2 2006.257.17:39:18.92#ibcon#about to read 5, iclass 23, count 2 2006.257.17:39:18.92#ibcon#read 5, iclass 23, count 2 2006.257.17:39:18.92#ibcon#about to read 6, iclass 23, count 2 2006.257.17:39:18.92#ibcon#read 6, iclass 23, count 2 2006.257.17:39:18.92#ibcon#end of sib2, iclass 23, count 2 2006.257.17:39:18.92#ibcon#*mode == 0, iclass 23, count 2 2006.257.17:39:18.92#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.17:39:18.92#ibcon#[25=AT05-04\r\n] 2006.257.17:39:18.92#ibcon#*before write, iclass 23, count 2 2006.257.17:39:18.92#ibcon#enter sib2, iclass 23, count 2 2006.257.17:39:18.92#ibcon#flushed, iclass 23, count 2 2006.257.17:39:18.92#ibcon#about to write, iclass 23, count 2 2006.257.17:39:18.92#ibcon#wrote, iclass 23, count 2 2006.257.17:39:18.92#ibcon#about to read 3, iclass 23, count 2 2006.257.17:39:18.95#ibcon#read 3, iclass 23, count 2 2006.257.17:39:18.95#ibcon#about to read 4, iclass 23, count 2 2006.257.17:39:18.95#ibcon#read 4, iclass 23, count 2 2006.257.17:39:18.95#ibcon#about to read 5, iclass 23, count 2 2006.257.17:39:18.95#ibcon#read 5, iclass 23, count 2 2006.257.17:39:18.95#ibcon#about to read 6, iclass 23, count 2 2006.257.17:39:18.95#ibcon#read 6, iclass 23, count 2 2006.257.17:39:18.95#ibcon#end of sib2, iclass 23, count 2 2006.257.17:39:18.95#ibcon#*after write, iclass 23, count 2 2006.257.17:39:18.95#ibcon#*before return 0, iclass 23, count 2 2006.257.17:39:18.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:18.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:18.95#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.17:39:18.95#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:18.95#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:19.07#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:19.07#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:19.07#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:39:19.07#ibcon#first serial, iclass 23, count 0 2006.257.17:39:19.07#ibcon#enter sib2, iclass 23, count 0 2006.257.17:39:19.07#ibcon#flushed, iclass 23, count 0 2006.257.17:39:19.07#ibcon#about to write, iclass 23, count 0 2006.257.17:39:19.07#ibcon#wrote, iclass 23, count 0 2006.257.17:39:19.07#ibcon#about to read 3, iclass 23, count 0 2006.257.17:39:19.09#ibcon#read 3, iclass 23, count 0 2006.257.17:39:19.09#ibcon#about to read 4, iclass 23, count 0 2006.257.17:39:19.09#ibcon#read 4, iclass 23, count 0 2006.257.17:39:19.09#ibcon#about to read 5, iclass 23, count 0 2006.257.17:39:19.09#ibcon#read 5, iclass 23, count 0 2006.257.17:39:19.09#ibcon#about to read 6, iclass 23, count 0 2006.257.17:39:19.09#ibcon#read 6, iclass 23, count 0 2006.257.17:39:19.09#ibcon#end of sib2, iclass 23, count 0 2006.257.17:39:19.09#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:39:19.09#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:39:19.09#ibcon#[25=USB\r\n] 2006.257.17:39:19.09#ibcon#*before write, iclass 23, count 0 2006.257.17:39:19.09#ibcon#enter sib2, iclass 23, count 0 2006.257.17:39:19.09#ibcon#flushed, iclass 23, count 0 2006.257.17:39:19.09#ibcon#about to write, iclass 23, count 0 2006.257.17:39:19.09#ibcon#wrote, iclass 23, count 0 2006.257.17:39:19.09#ibcon#about to read 3, iclass 23, count 0 2006.257.17:39:19.12#ibcon#read 3, iclass 23, count 0 2006.257.17:39:19.12#ibcon#about to read 4, iclass 23, count 0 2006.257.17:39:19.12#ibcon#read 4, iclass 23, count 0 2006.257.17:39:19.12#ibcon#about to read 5, iclass 23, count 0 2006.257.17:39:19.12#ibcon#read 5, iclass 23, count 0 2006.257.17:39:19.12#ibcon#about to read 6, iclass 23, count 0 2006.257.17:39:19.12#ibcon#read 6, iclass 23, count 0 2006.257.17:39:19.12#ibcon#end of sib2, iclass 23, count 0 2006.257.17:39:19.12#ibcon#*after write, iclass 23, count 0 2006.257.17:39:19.12#ibcon#*before return 0, iclass 23, count 0 2006.257.17:39:19.12#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:19.12#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:19.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:39:19.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:39:19.12$vck44/valo=6,814.99 2006.257.17:39:19.12#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.17:39:19.12#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.17:39:19.12#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:19.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:19.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:19.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:19.12#ibcon#enter wrdev, iclass 25, count 0 2006.257.17:39:19.12#ibcon#first serial, iclass 25, count 0 2006.257.17:39:19.12#ibcon#enter sib2, iclass 25, count 0 2006.257.17:39:19.12#ibcon#flushed, iclass 25, count 0 2006.257.17:39:19.12#ibcon#about to write, iclass 25, count 0 2006.257.17:39:19.12#ibcon#wrote, iclass 25, count 0 2006.257.17:39:19.12#ibcon#about to read 3, iclass 25, count 0 2006.257.17:39:19.14#ibcon#read 3, iclass 25, count 0 2006.257.17:39:19.14#ibcon#about to read 4, iclass 25, count 0 2006.257.17:39:19.14#ibcon#read 4, iclass 25, count 0 2006.257.17:39:19.14#ibcon#about to read 5, iclass 25, count 0 2006.257.17:39:19.14#ibcon#read 5, iclass 25, count 0 2006.257.17:39:19.14#ibcon#about to read 6, iclass 25, count 0 2006.257.17:39:19.14#ibcon#read 6, iclass 25, count 0 2006.257.17:39:19.14#ibcon#end of sib2, iclass 25, count 0 2006.257.17:39:19.14#ibcon#*mode == 0, iclass 25, count 0 2006.257.17:39:19.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.17:39:19.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:39:19.14#ibcon#*before write, iclass 25, count 0 2006.257.17:39:19.14#ibcon#enter sib2, iclass 25, count 0 2006.257.17:39:19.14#ibcon#flushed, iclass 25, count 0 2006.257.17:39:19.14#ibcon#about to write, iclass 25, count 0 2006.257.17:39:19.14#ibcon#wrote, iclass 25, count 0 2006.257.17:39:19.14#ibcon#about to read 3, iclass 25, count 0 2006.257.17:39:19.18#ibcon#read 3, iclass 25, count 0 2006.257.17:39:19.18#ibcon#about to read 4, iclass 25, count 0 2006.257.17:39:19.18#ibcon#read 4, iclass 25, count 0 2006.257.17:39:19.18#ibcon#about to read 5, iclass 25, count 0 2006.257.17:39:19.18#ibcon#read 5, iclass 25, count 0 2006.257.17:39:19.18#ibcon#about to read 6, iclass 25, count 0 2006.257.17:39:19.18#ibcon#read 6, iclass 25, count 0 2006.257.17:39:19.18#ibcon#end of sib2, iclass 25, count 0 2006.257.17:39:19.18#ibcon#*after write, iclass 25, count 0 2006.257.17:39:19.18#ibcon#*before return 0, iclass 25, count 0 2006.257.17:39:19.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:19.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:19.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.17:39:19.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.17:39:19.18$vck44/va=6,4 2006.257.17:39:19.18#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.17:39:19.18#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.17:39:19.18#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:19.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:19.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:19.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:19.24#ibcon#enter wrdev, iclass 27, count 2 2006.257.17:39:19.24#ibcon#first serial, iclass 27, count 2 2006.257.17:39:19.24#ibcon#enter sib2, iclass 27, count 2 2006.257.17:39:19.24#ibcon#flushed, iclass 27, count 2 2006.257.17:39:19.24#ibcon#about to write, iclass 27, count 2 2006.257.17:39:19.24#ibcon#wrote, iclass 27, count 2 2006.257.17:39:19.24#ibcon#about to read 3, iclass 27, count 2 2006.257.17:39:19.26#ibcon#read 3, iclass 27, count 2 2006.257.17:39:19.26#ibcon#about to read 4, iclass 27, count 2 2006.257.17:39:19.26#ibcon#read 4, iclass 27, count 2 2006.257.17:39:19.26#ibcon#about to read 5, iclass 27, count 2 2006.257.17:39:19.26#ibcon#read 5, iclass 27, count 2 2006.257.17:39:19.26#ibcon#about to read 6, iclass 27, count 2 2006.257.17:39:19.26#ibcon#read 6, iclass 27, count 2 2006.257.17:39:19.26#ibcon#end of sib2, iclass 27, count 2 2006.257.17:39:19.26#ibcon#*mode == 0, iclass 27, count 2 2006.257.17:39:19.26#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.17:39:19.26#ibcon#[25=AT06-04\r\n] 2006.257.17:39:19.26#ibcon#*before write, iclass 27, count 2 2006.257.17:39:19.26#ibcon#enter sib2, iclass 27, count 2 2006.257.17:39:19.26#ibcon#flushed, iclass 27, count 2 2006.257.17:39:19.26#ibcon#about to write, iclass 27, count 2 2006.257.17:39:19.26#ibcon#wrote, iclass 27, count 2 2006.257.17:39:19.26#ibcon#about to read 3, iclass 27, count 2 2006.257.17:39:19.29#ibcon#read 3, iclass 27, count 2 2006.257.17:39:19.29#ibcon#about to read 4, iclass 27, count 2 2006.257.17:39:19.29#ibcon#read 4, iclass 27, count 2 2006.257.17:39:19.29#ibcon#about to read 5, iclass 27, count 2 2006.257.17:39:19.29#ibcon#read 5, iclass 27, count 2 2006.257.17:39:19.29#ibcon#about to read 6, iclass 27, count 2 2006.257.17:39:19.29#ibcon#read 6, iclass 27, count 2 2006.257.17:39:19.29#ibcon#end of sib2, iclass 27, count 2 2006.257.17:39:19.29#ibcon#*after write, iclass 27, count 2 2006.257.17:39:19.29#ibcon#*before return 0, iclass 27, count 2 2006.257.17:39:19.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:19.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:19.29#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.17:39:19.29#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:19.29#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:19.41#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:19.41#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:19.41#ibcon#enter wrdev, iclass 27, count 0 2006.257.17:39:19.41#ibcon#first serial, iclass 27, count 0 2006.257.17:39:19.41#ibcon#enter sib2, iclass 27, count 0 2006.257.17:39:19.41#ibcon#flushed, iclass 27, count 0 2006.257.17:39:19.41#ibcon#about to write, iclass 27, count 0 2006.257.17:39:19.41#ibcon#wrote, iclass 27, count 0 2006.257.17:39:19.41#ibcon#about to read 3, iclass 27, count 0 2006.257.17:39:19.43#ibcon#read 3, iclass 27, count 0 2006.257.17:39:19.43#ibcon#about to read 4, iclass 27, count 0 2006.257.17:39:19.43#ibcon#read 4, iclass 27, count 0 2006.257.17:39:19.43#ibcon#about to read 5, iclass 27, count 0 2006.257.17:39:19.43#ibcon#read 5, iclass 27, count 0 2006.257.17:39:19.43#ibcon#about to read 6, iclass 27, count 0 2006.257.17:39:19.43#ibcon#read 6, iclass 27, count 0 2006.257.17:39:19.43#ibcon#end of sib2, iclass 27, count 0 2006.257.17:39:19.43#ibcon#*mode == 0, iclass 27, count 0 2006.257.17:39:19.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.17:39:19.43#ibcon#[25=USB\r\n] 2006.257.17:39:19.43#ibcon#*before write, iclass 27, count 0 2006.257.17:39:19.43#ibcon#enter sib2, iclass 27, count 0 2006.257.17:39:19.43#ibcon#flushed, iclass 27, count 0 2006.257.17:39:19.43#ibcon#about to write, iclass 27, count 0 2006.257.17:39:19.43#ibcon#wrote, iclass 27, count 0 2006.257.17:39:19.43#ibcon#about to read 3, iclass 27, count 0 2006.257.17:39:19.46#ibcon#read 3, iclass 27, count 0 2006.257.17:39:19.46#ibcon#about to read 4, iclass 27, count 0 2006.257.17:39:19.46#ibcon#read 4, iclass 27, count 0 2006.257.17:39:19.46#ibcon#about to read 5, iclass 27, count 0 2006.257.17:39:19.46#ibcon#read 5, iclass 27, count 0 2006.257.17:39:19.46#ibcon#about to read 6, iclass 27, count 0 2006.257.17:39:19.46#ibcon#read 6, iclass 27, count 0 2006.257.17:39:19.46#ibcon#end of sib2, iclass 27, count 0 2006.257.17:39:19.46#ibcon#*after write, iclass 27, count 0 2006.257.17:39:19.46#ibcon#*before return 0, iclass 27, count 0 2006.257.17:39:19.46#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:19.46#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:19.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.17:39:19.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.17:39:19.46$vck44/valo=7,864.99 2006.257.17:39:19.46#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.17:39:19.46#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.17:39:19.46#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:19.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:19.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:19.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:19.46#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:39:19.46#ibcon#first serial, iclass 29, count 0 2006.257.17:39:19.46#ibcon#enter sib2, iclass 29, count 0 2006.257.17:39:19.46#ibcon#flushed, iclass 29, count 0 2006.257.17:39:19.46#ibcon#about to write, iclass 29, count 0 2006.257.17:39:19.46#ibcon#wrote, iclass 29, count 0 2006.257.17:39:19.46#ibcon#about to read 3, iclass 29, count 0 2006.257.17:39:19.48#ibcon#read 3, iclass 29, count 0 2006.257.17:39:19.48#ibcon#about to read 4, iclass 29, count 0 2006.257.17:39:19.48#ibcon#read 4, iclass 29, count 0 2006.257.17:39:19.48#ibcon#about to read 5, iclass 29, count 0 2006.257.17:39:19.48#ibcon#read 5, iclass 29, count 0 2006.257.17:39:19.48#ibcon#about to read 6, iclass 29, count 0 2006.257.17:39:19.48#ibcon#read 6, iclass 29, count 0 2006.257.17:39:19.48#ibcon#end of sib2, iclass 29, count 0 2006.257.17:39:19.48#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:39:19.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:39:19.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:39:19.48#ibcon#*before write, iclass 29, count 0 2006.257.17:39:19.48#ibcon#enter sib2, iclass 29, count 0 2006.257.17:39:19.48#ibcon#flushed, iclass 29, count 0 2006.257.17:39:19.48#ibcon#about to write, iclass 29, count 0 2006.257.17:39:19.48#ibcon#wrote, iclass 29, count 0 2006.257.17:39:19.48#ibcon#about to read 3, iclass 29, count 0 2006.257.17:39:19.52#ibcon#read 3, iclass 29, count 0 2006.257.17:39:19.52#ibcon#about to read 4, iclass 29, count 0 2006.257.17:39:19.52#ibcon#read 4, iclass 29, count 0 2006.257.17:39:19.52#ibcon#about to read 5, iclass 29, count 0 2006.257.17:39:19.52#ibcon#read 5, iclass 29, count 0 2006.257.17:39:19.52#ibcon#about to read 6, iclass 29, count 0 2006.257.17:39:19.52#ibcon#read 6, iclass 29, count 0 2006.257.17:39:19.52#ibcon#end of sib2, iclass 29, count 0 2006.257.17:39:19.52#ibcon#*after write, iclass 29, count 0 2006.257.17:39:19.52#ibcon#*before return 0, iclass 29, count 0 2006.257.17:39:19.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:19.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:19.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:39:19.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:39:19.52$vck44/va=7,4 2006.257.17:39:19.52#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.17:39:19.52#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.17:39:19.52#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:19.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:19.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:19.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:19.58#ibcon#enter wrdev, iclass 31, count 2 2006.257.17:39:19.58#ibcon#first serial, iclass 31, count 2 2006.257.17:39:19.58#ibcon#enter sib2, iclass 31, count 2 2006.257.17:39:19.58#ibcon#flushed, iclass 31, count 2 2006.257.17:39:19.58#ibcon#about to write, iclass 31, count 2 2006.257.17:39:19.58#ibcon#wrote, iclass 31, count 2 2006.257.17:39:19.58#ibcon#about to read 3, iclass 31, count 2 2006.257.17:39:19.60#ibcon#read 3, iclass 31, count 2 2006.257.17:39:19.60#ibcon#about to read 4, iclass 31, count 2 2006.257.17:39:19.60#ibcon#read 4, iclass 31, count 2 2006.257.17:39:19.60#ibcon#about to read 5, iclass 31, count 2 2006.257.17:39:19.60#ibcon#read 5, iclass 31, count 2 2006.257.17:39:19.60#ibcon#about to read 6, iclass 31, count 2 2006.257.17:39:19.60#ibcon#read 6, iclass 31, count 2 2006.257.17:39:19.60#ibcon#end of sib2, iclass 31, count 2 2006.257.17:39:19.60#ibcon#*mode == 0, iclass 31, count 2 2006.257.17:39:19.60#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.17:39:19.60#ibcon#[25=AT07-04\r\n] 2006.257.17:39:19.60#ibcon#*before write, iclass 31, count 2 2006.257.17:39:19.60#ibcon#enter sib2, iclass 31, count 2 2006.257.17:39:19.60#ibcon#flushed, iclass 31, count 2 2006.257.17:39:19.60#ibcon#about to write, iclass 31, count 2 2006.257.17:39:19.60#ibcon#wrote, iclass 31, count 2 2006.257.17:39:19.60#ibcon#about to read 3, iclass 31, count 2 2006.257.17:39:19.63#ibcon#read 3, iclass 31, count 2 2006.257.17:39:19.63#ibcon#about to read 4, iclass 31, count 2 2006.257.17:39:19.63#ibcon#read 4, iclass 31, count 2 2006.257.17:39:19.63#ibcon#about to read 5, iclass 31, count 2 2006.257.17:39:19.63#ibcon#read 5, iclass 31, count 2 2006.257.17:39:19.63#ibcon#about to read 6, iclass 31, count 2 2006.257.17:39:19.63#ibcon#read 6, iclass 31, count 2 2006.257.17:39:19.63#ibcon#end of sib2, iclass 31, count 2 2006.257.17:39:19.63#ibcon#*after write, iclass 31, count 2 2006.257.17:39:19.63#ibcon#*before return 0, iclass 31, count 2 2006.257.17:39:19.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:19.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:19.63#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.17:39:19.63#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:19.63#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:19.75#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:19.75#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:19.75#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:39:19.75#ibcon#first serial, iclass 31, count 0 2006.257.17:39:19.75#ibcon#enter sib2, iclass 31, count 0 2006.257.17:39:19.75#ibcon#flushed, iclass 31, count 0 2006.257.17:39:19.75#ibcon#about to write, iclass 31, count 0 2006.257.17:39:19.75#ibcon#wrote, iclass 31, count 0 2006.257.17:39:19.75#ibcon#about to read 3, iclass 31, count 0 2006.257.17:39:19.77#ibcon#read 3, iclass 31, count 0 2006.257.17:39:19.77#ibcon#about to read 4, iclass 31, count 0 2006.257.17:39:19.77#ibcon#read 4, iclass 31, count 0 2006.257.17:39:19.77#ibcon#about to read 5, iclass 31, count 0 2006.257.17:39:19.77#ibcon#read 5, iclass 31, count 0 2006.257.17:39:19.77#ibcon#about to read 6, iclass 31, count 0 2006.257.17:39:19.77#ibcon#read 6, iclass 31, count 0 2006.257.17:39:19.77#ibcon#end of sib2, iclass 31, count 0 2006.257.17:39:19.77#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:39:19.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:39:19.77#ibcon#[25=USB\r\n] 2006.257.17:39:19.77#ibcon#*before write, iclass 31, count 0 2006.257.17:39:19.77#ibcon#enter sib2, iclass 31, count 0 2006.257.17:39:19.77#ibcon#flushed, iclass 31, count 0 2006.257.17:39:19.77#ibcon#about to write, iclass 31, count 0 2006.257.17:39:19.77#ibcon#wrote, iclass 31, count 0 2006.257.17:39:19.77#ibcon#about to read 3, iclass 31, count 0 2006.257.17:39:19.80#ibcon#read 3, iclass 31, count 0 2006.257.17:39:19.80#ibcon#about to read 4, iclass 31, count 0 2006.257.17:39:19.80#ibcon#read 4, iclass 31, count 0 2006.257.17:39:19.80#ibcon#about to read 5, iclass 31, count 0 2006.257.17:39:19.80#ibcon#read 5, iclass 31, count 0 2006.257.17:39:19.80#ibcon#about to read 6, iclass 31, count 0 2006.257.17:39:19.80#ibcon#read 6, iclass 31, count 0 2006.257.17:39:19.80#ibcon#end of sib2, iclass 31, count 0 2006.257.17:39:19.80#ibcon#*after write, iclass 31, count 0 2006.257.17:39:19.80#ibcon#*before return 0, iclass 31, count 0 2006.257.17:39:19.80#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:19.80#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:19.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:39:19.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:39:19.80$vck44/valo=8,884.99 2006.257.17:39:19.80#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.17:39:19.80#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.17:39:19.80#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:19.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:19.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:19.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:19.80#ibcon#enter wrdev, iclass 33, count 0 2006.257.17:39:19.80#ibcon#first serial, iclass 33, count 0 2006.257.17:39:19.80#ibcon#enter sib2, iclass 33, count 0 2006.257.17:39:19.80#ibcon#flushed, iclass 33, count 0 2006.257.17:39:19.80#ibcon#about to write, iclass 33, count 0 2006.257.17:39:19.80#ibcon#wrote, iclass 33, count 0 2006.257.17:39:19.80#ibcon#about to read 3, iclass 33, count 0 2006.257.17:39:19.82#ibcon#read 3, iclass 33, count 0 2006.257.17:39:19.82#ibcon#about to read 4, iclass 33, count 0 2006.257.17:39:19.82#ibcon#read 4, iclass 33, count 0 2006.257.17:39:19.82#ibcon#about to read 5, iclass 33, count 0 2006.257.17:39:19.82#ibcon#read 5, iclass 33, count 0 2006.257.17:39:19.82#ibcon#about to read 6, iclass 33, count 0 2006.257.17:39:19.82#ibcon#read 6, iclass 33, count 0 2006.257.17:39:19.82#ibcon#end of sib2, iclass 33, count 0 2006.257.17:39:19.82#ibcon#*mode == 0, iclass 33, count 0 2006.257.17:39:19.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.17:39:19.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:39:19.82#ibcon#*before write, iclass 33, count 0 2006.257.17:39:19.82#ibcon#enter sib2, iclass 33, count 0 2006.257.17:39:19.82#ibcon#flushed, iclass 33, count 0 2006.257.17:39:19.82#ibcon#about to write, iclass 33, count 0 2006.257.17:39:19.82#ibcon#wrote, iclass 33, count 0 2006.257.17:39:19.82#ibcon#about to read 3, iclass 33, count 0 2006.257.17:39:19.86#ibcon#read 3, iclass 33, count 0 2006.257.17:39:19.86#ibcon#about to read 4, iclass 33, count 0 2006.257.17:39:19.86#ibcon#read 4, iclass 33, count 0 2006.257.17:39:19.86#ibcon#about to read 5, iclass 33, count 0 2006.257.17:39:19.86#ibcon#read 5, iclass 33, count 0 2006.257.17:39:19.86#ibcon#about to read 6, iclass 33, count 0 2006.257.17:39:19.86#ibcon#read 6, iclass 33, count 0 2006.257.17:39:19.86#ibcon#end of sib2, iclass 33, count 0 2006.257.17:39:19.86#ibcon#*after write, iclass 33, count 0 2006.257.17:39:19.86#ibcon#*before return 0, iclass 33, count 0 2006.257.17:39:19.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:19.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:19.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.17:39:19.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.17:39:19.86$vck44/va=8,4 2006.257.17:39:19.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.17:39:19.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.17:39:19.86#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:19.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:19.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:19.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:19.92#ibcon#enter wrdev, iclass 35, count 2 2006.257.17:39:19.92#ibcon#first serial, iclass 35, count 2 2006.257.17:39:19.92#ibcon#enter sib2, iclass 35, count 2 2006.257.17:39:19.92#ibcon#flushed, iclass 35, count 2 2006.257.17:39:19.92#ibcon#about to write, iclass 35, count 2 2006.257.17:39:19.92#ibcon#wrote, iclass 35, count 2 2006.257.17:39:19.92#ibcon#about to read 3, iclass 35, count 2 2006.257.17:39:19.94#ibcon#read 3, iclass 35, count 2 2006.257.17:39:19.94#ibcon#about to read 4, iclass 35, count 2 2006.257.17:39:19.94#ibcon#read 4, iclass 35, count 2 2006.257.17:39:19.94#ibcon#about to read 5, iclass 35, count 2 2006.257.17:39:19.94#ibcon#read 5, iclass 35, count 2 2006.257.17:39:19.94#ibcon#about to read 6, iclass 35, count 2 2006.257.17:39:19.94#ibcon#read 6, iclass 35, count 2 2006.257.17:39:19.94#ibcon#end of sib2, iclass 35, count 2 2006.257.17:39:19.94#ibcon#*mode == 0, iclass 35, count 2 2006.257.17:39:19.94#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.17:39:19.94#ibcon#[25=AT08-04\r\n] 2006.257.17:39:19.94#ibcon#*before write, iclass 35, count 2 2006.257.17:39:19.94#ibcon#enter sib2, iclass 35, count 2 2006.257.17:39:19.94#ibcon#flushed, iclass 35, count 2 2006.257.17:39:19.94#ibcon#about to write, iclass 35, count 2 2006.257.17:39:19.94#ibcon#wrote, iclass 35, count 2 2006.257.17:39:19.94#ibcon#about to read 3, iclass 35, count 2 2006.257.17:39:19.97#ibcon#read 3, iclass 35, count 2 2006.257.17:39:19.97#ibcon#about to read 4, iclass 35, count 2 2006.257.17:39:19.97#ibcon#read 4, iclass 35, count 2 2006.257.17:39:19.97#ibcon#about to read 5, iclass 35, count 2 2006.257.17:39:19.97#ibcon#read 5, iclass 35, count 2 2006.257.17:39:19.97#ibcon#about to read 6, iclass 35, count 2 2006.257.17:39:19.97#ibcon#read 6, iclass 35, count 2 2006.257.17:39:19.97#ibcon#end of sib2, iclass 35, count 2 2006.257.17:39:19.97#ibcon#*after write, iclass 35, count 2 2006.257.17:39:19.97#ibcon#*before return 0, iclass 35, count 2 2006.257.17:39:19.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:19.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:19.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.17:39:19.97#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:19.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:20.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:20.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:20.09#ibcon#enter wrdev, iclass 35, count 0 2006.257.17:39:20.09#ibcon#first serial, iclass 35, count 0 2006.257.17:39:20.09#ibcon#enter sib2, iclass 35, count 0 2006.257.17:39:20.09#ibcon#flushed, iclass 35, count 0 2006.257.17:39:20.09#ibcon#about to write, iclass 35, count 0 2006.257.17:39:20.09#ibcon#wrote, iclass 35, count 0 2006.257.17:39:20.09#ibcon#about to read 3, iclass 35, count 0 2006.257.17:39:20.11#ibcon#read 3, iclass 35, count 0 2006.257.17:39:20.11#ibcon#about to read 4, iclass 35, count 0 2006.257.17:39:20.11#ibcon#read 4, iclass 35, count 0 2006.257.17:39:20.11#ibcon#about to read 5, iclass 35, count 0 2006.257.17:39:20.11#ibcon#read 5, iclass 35, count 0 2006.257.17:39:20.11#ibcon#about to read 6, iclass 35, count 0 2006.257.17:39:20.11#ibcon#read 6, iclass 35, count 0 2006.257.17:39:20.11#ibcon#end of sib2, iclass 35, count 0 2006.257.17:39:20.11#ibcon#*mode == 0, iclass 35, count 0 2006.257.17:39:20.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.17:39:20.11#ibcon#[25=USB\r\n] 2006.257.17:39:20.11#ibcon#*before write, iclass 35, count 0 2006.257.17:39:20.11#ibcon#enter sib2, iclass 35, count 0 2006.257.17:39:20.11#ibcon#flushed, iclass 35, count 0 2006.257.17:39:20.11#ibcon#about to write, iclass 35, count 0 2006.257.17:39:20.11#ibcon#wrote, iclass 35, count 0 2006.257.17:39:20.11#ibcon#about to read 3, iclass 35, count 0 2006.257.17:39:20.14#ibcon#read 3, iclass 35, count 0 2006.257.17:39:20.14#ibcon#about to read 4, iclass 35, count 0 2006.257.17:39:20.14#ibcon#read 4, iclass 35, count 0 2006.257.17:39:20.14#ibcon#about to read 5, iclass 35, count 0 2006.257.17:39:20.14#ibcon#read 5, iclass 35, count 0 2006.257.17:39:20.14#ibcon#about to read 6, iclass 35, count 0 2006.257.17:39:20.14#ibcon#read 6, iclass 35, count 0 2006.257.17:39:20.14#ibcon#end of sib2, iclass 35, count 0 2006.257.17:39:20.14#ibcon#*after write, iclass 35, count 0 2006.257.17:39:20.14#ibcon#*before return 0, iclass 35, count 0 2006.257.17:39:20.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:20.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:20.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.17:39:20.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.17:39:20.14$vck44/vblo=1,629.99 2006.257.17:39:20.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.17:39:20.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.17:39:20.14#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:20.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:20.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:20.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:20.14#ibcon#enter wrdev, iclass 37, count 0 2006.257.17:39:20.14#ibcon#first serial, iclass 37, count 0 2006.257.17:39:20.14#ibcon#enter sib2, iclass 37, count 0 2006.257.17:39:20.14#ibcon#flushed, iclass 37, count 0 2006.257.17:39:20.14#ibcon#about to write, iclass 37, count 0 2006.257.17:39:20.14#ibcon#wrote, iclass 37, count 0 2006.257.17:39:20.14#ibcon#about to read 3, iclass 37, count 0 2006.257.17:39:20.16#ibcon#read 3, iclass 37, count 0 2006.257.17:39:20.16#ibcon#about to read 4, iclass 37, count 0 2006.257.17:39:20.16#ibcon#read 4, iclass 37, count 0 2006.257.17:39:20.16#ibcon#about to read 5, iclass 37, count 0 2006.257.17:39:20.16#ibcon#read 5, iclass 37, count 0 2006.257.17:39:20.16#ibcon#about to read 6, iclass 37, count 0 2006.257.17:39:20.16#ibcon#read 6, iclass 37, count 0 2006.257.17:39:20.16#ibcon#end of sib2, iclass 37, count 0 2006.257.17:39:20.16#ibcon#*mode == 0, iclass 37, count 0 2006.257.17:39:20.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.17:39:20.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:39:20.16#ibcon#*before write, iclass 37, count 0 2006.257.17:39:20.16#ibcon#enter sib2, iclass 37, count 0 2006.257.17:39:20.16#ibcon#flushed, iclass 37, count 0 2006.257.17:39:20.16#ibcon#about to write, iclass 37, count 0 2006.257.17:39:20.16#ibcon#wrote, iclass 37, count 0 2006.257.17:39:20.16#ibcon#about to read 3, iclass 37, count 0 2006.257.17:39:20.20#ibcon#read 3, iclass 37, count 0 2006.257.17:39:20.20#ibcon#about to read 4, iclass 37, count 0 2006.257.17:39:20.20#ibcon#read 4, iclass 37, count 0 2006.257.17:39:20.20#ibcon#about to read 5, iclass 37, count 0 2006.257.17:39:20.20#ibcon#read 5, iclass 37, count 0 2006.257.17:39:20.20#ibcon#about to read 6, iclass 37, count 0 2006.257.17:39:20.20#ibcon#read 6, iclass 37, count 0 2006.257.17:39:20.20#ibcon#end of sib2, iclass 37, count 0 2006.257.17:39:20.20#ibcon#*after write, iclass 37, count 0 2006.257.17:39:20.20#ibcon#*before return 0, iclass 37, count 0 2006.257.17:39:20.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:20.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:20.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.17:39:20.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.17:39:20.20$vck44/vb=1,4 2006.257.17:39:20.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.17:39:20.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.17:39:20.20#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:20.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:39:20.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:39:20.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:39:20.20#ibcon#enter wrdev, iclass 39, count 2 2006.257.17:39:20.20#ibcon#first serial, iclass 39, count 2 2006.257.17:39:20.20#ibcon#enter sib2, iclass 39, count 2 2006.257.17:39:20.20#ibcon#flushed, iclass 39, count 2 2006.257.17:39:20.20#ibcon#about to write, iclass 39, count 2 2006.257.17:39:20.20#ibcon#wrote, iclass 39, count 2 2006.257.17:39:20.20#ibcon#about to read 3, iclass 39, count 2 2006.257.17:39:20.22#ibcon#read 3, iclass 39, count 2 2006.257.17:39:20.22#ibcon#about to read 4, iclass 39, count 2 2006.257.17:39:20.22#ibcon#read 4, iclass 39, count 2 2006.257.17:39:20.22#ibcon#about to read 5, iclass 39, count 2 2006.257.17:39:20.22#ibcon#read 5, iclass 39, count 2 2006.257.17:39:20.22#ibcon#about to read 6, iclass 39, count 2 2006.257.17:39:20.22#ibcon#read 6, iclass 39, count 2 2006.257.17:39:20.22#ibcon#end of sib2, iclass 39, count 2 2006.257.17:39:20.22#ibcon#*mode == 0, iclass 39, count 2 2006.257.17:39:20.22#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.17:39:20.22#ibcon#[27=AT01-04\r\n] 2006.257.17:39:20.22#ibcon#*before write, iclass 39, count 2 2006.257.17:39:20.22#ibcon#enter sib2, iclass 39, count 2 2006.257.17:39:20.22#ibcon#flushed, iclass 39, count 2 2006.257.17:39:20.22#ibcon#about to write, iclass 39, count 2 2006.257.17:39:20.22#ibcon#wrote, iclass 39, count 2 2006.257.17:39:20.22#ibcon#about to read 3, iclass 39, count 2 2006.257.17:39:20.25#ibcon#read 3, iclass 39, count 2 2006.257.17:39:20.25#ibcon#about to read 4, iclass 39, count 2 2006.257.17:39:20.25#ibcon#read 4, iclass 39, count 2 2006.257.17:39:20.25#ibcon#about to read 5, iclass 39, count 2 2006.257.17:39:20.25#ibcon#read 5, iclass 39, count 2 2006.257.17:39:20.25#ibcon#about to read 6, iclass 39, count 2 2006.257.17:39:20.25#ibcon#read 6, iclass 39, count 2 2006.257.17:39:20.25#ibcon#end of sib2, iclass 39, count 2 2006.257.17:39:20.25#ibcon#*after write, iclass 39, count 2 2006.257.17:39:20.25#ibcon#*before return 0, iclass 39, count 2 2006.257.17:39:20.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:39:20.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.17:39:20.25#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.17:39:20.25#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:20.25#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:39:20.37#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:39:20.37#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:39:20.37#ibcon#enter wrdev, iclass 39, count 0 2006.257.17:39:20.37#ibcon#first serial, iclass 39, count 0 2006.257.17:39:20.37#ibcon#enter sib2, iclass 39, count 0 2006.257.17:39:20.37#ibcon#flushed, iclass 39, count 0 2006.257.17:39:20.37#ibcon#about to write, iclass 39, count 0 2006.257.17:39:20.37#ibcon#wrote, iclass 39, count 0 2006.257.17:39:20.37#ibcon#about to read 3, iclass 39, count 0 2006.257.17:39:20.39#ibcon#read 3, iclass 39, count 0 2006.257.17:39:20.39#ibcon#about to read 4, iclass 39, count 0 2006.257.17:39:20.39#ibcon#read 4, iclass 39, count 0 2006.257.17:39:20.39#ibcon#about to read 5, iclass 39, count 0 2006.257.17:39:20.39#ibcon#read 5, iclass 39, count 0 2006.257.17:39:20.39#ibcon#about to read 6, iclass 39, count 0 2006.257.17:39:20.39#ibcon#read 6, iclass 39, count 0 2006.257.17:39:20.39#ibcon#end of sib2, iclass 39, count 0 2006.257.17:39:20.39#ibcon#*mode == 0, iclass 39, count 0 2006.257.17:39:20.39#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.17:39:20.39#ibcon#[27=USB\r\n] 2006.257.17:39:20.39#ibcon#*before write, iclass 39, count 0 2006.257.17:39:20.39#ibcon#enter sib2, iclass 39, count 0 2006.257.17:39:20.39#ibcon#flushed, iclass 39, count 0 2006.257.17:39:20.39#ibcon#about to write, iclass 39, count 0 2006.257.17:39:20.39#ibcon#wrote, iclass 39, count 0 2006.257.17:39:20.39#ibcon#about to read 3, iclass 39, count 0 2006.257.17:39:20.42#ibcon#read 3, iclass 39, count 0 2006.257.17:39:20.42#ibcon#about to read 4, iclass 39, count 0 2006.257.17:39:20.42#ibcon#read 4, iclass 39, count 0 2006.257.17:39:20.42#ibcon#about to read 5, iclass 39, count 0 2006.257.17:39:20.42#ibcon#read 5, iclass 39, count 0 2006.257.17:39:20.42#ibcon#about to read 6, iclass 39, count 0 2006.257.17:39:20.42#ibcon#read 6, iclass 39, count 0 2006.257.17:39:20.42#ibcon#end of sib2, iclass 39, count 0 2006.257.17:39:20.42#ibcon#*after write, iclass 39, count 0 2006.257.17:39:20.42#ibcon#*before return 0, iclass 39, count 0 2006.257.17:39:20.42#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:39:20.42#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.17:39:20.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.17:39:20.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.17:39:20.42$vck44/vblo=2,634.99 2006.257.17:39:20.42#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.17:39:20.42#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.17:39:20.42#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:20.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:20.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:20.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:20.42#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:39:20.42#ibcon#first serial, iclass 3, count 0 2006.257.17:39:20.42#ibcon#enter sib2, iclass 3, count 0 2006.257.17:39:20.42#ibcon#flushed, iclass 3, count 0 2006.257.17:39:20.42#ibcon#about to write, iclass 3, count 0 2006.257.17:39:20.42#ibcon#wrote, iclass 3, count 0 2006.257.17:39:20.42#ibcon#about to read 3, iclass 3, count 0 2006.257.17:39:20.44#ibcon#read 3, iclass 3, count 0 2006.257.17:39:20.44#ibcon#about to read 4, iclass 3, count 0 2006.257.17:39:20.44#ibcon#read 4, iclass 3, count 0 2006.257.17:39:20.44#ibcon#about to read 5, iclass 3, count 0 2006.257.17:39:20.44#ibcon#read 5, iclass 3, count 0 2006.257.17:39:20.44#ibcon#about to read 6, iclass 3, count 0 2006.257.17:39:20.44#ibcon#read 6, iclass 3, count 0 2006.257.17:39:20.44#ibcon#end of sib2, iclass 3, count 0 2006.257.17:39:20.44#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:39:20.44#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:39:20.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:39:20.44#ibcon#*before write, iclass 3, count 0 2006.257.17:39:20.44#ibcon#enter sib2, iclass 3, count 0 2006.257.17:39:20.44#ibcon#flushed, iclass 3, count 0 2006.257.17:39:20.44#ibcon#about to write, iclass 3, count 0 2006.257.17:39:20.44#ibcon#wrote, iclass 3, count 0 2006.257.17:39:20.44#ibcon#about to read 3, iclass 3, count 0 2006.257.17:39:20.48#ibcon#read 3, iclass 3, count 0 2006.257.17:39:20.48#ibcon#about to read 4, iclass 3, count 0 2006.257.17:39:20.48#ibcon#read 4, iclass 3, count 0 2006.257.17:39:20.48#ibcon#about to read 5, iclass 3, count 0 2006.257.17:39:20.48#ibcon#read 5, iclass 3, count 0 2006.257.17:39:20.48#ibcon#about to read 6, iclass 3, count 0 2006.257.17:39:20.48#ibcon#read 6, iclass 3, count 0 2006.257.17:39:20.48#ibcon#end of sib2, iclass 3, count 0 2006.257.17:39:20.48#ibcon#*after write, iclass 3, count 0 2006.257.17:39:20.48#ibcon#*before return 0, iclass 3, count 0 2006.257.17:39:20.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:20.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.17:39:20.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:39:20.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:39:20.48$vck44/vb=2,5 2006.257.17:39:20.48#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.17:39:20.48#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.17:39:20.48#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:20.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:20.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:20.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:20.54#ibcon#enter wrdev, iclass 5, count 2 2006.257.17:39:20.54#ibcon#first serial, iclass 5, count 2 2006.257.17:39:20.54#ibcon#enter sib2, iclass 5, count 2 2006.257.17:39:20.54#ibcon#flushed, iclass 5, count 2 2006.257.17:39:20.54#ibcon#about to write, iclass 5, count 2 2006.257.17:39:20.54#ibcon#wrote, iclass 5, count 2 2006.257.17:39:20.54#ibcon#about to read 3, iclass 5, count 2 2006.257.17:39:20.56#ibcon#read 3, iclass 5, count 2 2006.257.17:39:20.56#ibcon#about to read 4, iclass 5, count 2 2006.257.17:39:20.56#ibcon#read 4, iclass 5, count 2 2006.257.17:39:20.56#ibcon#about to read 5, iclass 5, count 2 2006.257.17:39:20.56#ibcon#read 5, iclass 5, count 2 2006.257.17:39:20.56#ibcon#about to read 6, iclass 5, count 2 2006.257.17:39:20.56#ibcon#read 6, iclass 5, count 2 2006.257.17:39:20.56#ibcon#end of sib2, iclass 5, count 2 2006.257.17:39:20.56#ibcon#*mode == 0, iclass 5, count 2 2006.257.17:39:20.56#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.17:39:20.56#ibcon#[27=AT02-05\r\n] 2006.257.17:39:20.56#ibcon#*before write, iclass 5, count 2 2006.257.17:39:20.56#ibcon#enter sib2, iclass 5, count 2 2006.257.17:39:20.56#ibcon#flushed, iclass 5, count 2 2006.257.17:39:20.56#ibcon#about to write, iclass 5, count 2 2006.257.17:39:20.56#ibcon#wrote, iclass 5, count 2 2006.257.17:39:20.56#ibcon#about to read 3, iclass 5, count 2 2006.257.17:39:20.59#ibcon#read 3, iclass 5, count 2 2006.257.17:39:20.59#ibcon#about to read 4, iclass 5, count 2 2006.257.17:39:20.59#ibcon#read 4, iclass 5, count 2 2006.257.17:39:20.59#ibcon#about to read 5, iclass 5, count 2 2006.257.17:39:20.59#ibcon#read 5, iclass 5, count 2 2006.257.17:39:20.59#ibcon#about to read 6, iclass 5, count 2 2006.257.17:39:20.59#ibcon#read 6, iclass 5, count 2 2006.257.17:39:20.59#ibcon#end of sib2, iclass 5, count 2 2006.257.17:39:20.59#ibcon#*after write, iclass 5, count 2 2006.257.17:39:20.59#ibcon#*before return 0, iclass 5, count 2 2006.257.17:39:20.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:20.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.17:39:20.59#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.17:39:20.59#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:20.59#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:20.71#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:20.71#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:20.71#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:39:20.71#ibcon#first serial, iclass 5, count 0 2006.257.17:39:20.71#ibcon#enter sib2, iclass 5, count 0 2006.257.17:39:20.71#ibcon#flushed, iclass 5, count 0 2006.257.17:39:20.71#ibcon#about to write, iclass 5, count 0 2006.257.17:39:20.71#ibcon#wrote, iclass 5, count 0 2006.257.17:39:20.71#ibcon#about to read 3, iclass 5, count 0 2006.257.17:39:20.73#ibcon#read 3, iclass 5, count 0 2006.257.17:39:20.73#ibcon#about to read 4, iclass 5, count 0 2006.257.17:39:20.73#ibcon#read 4, iclass 5, count 0 2006.257.17:39:20.73#ibcon#about to read 5, iclass 5, count 0 2006.257.17:39:20.73#ibcon#read 5, iclass 5, count 0 2006.257.17:39:20.73#ibcon#about to read 6, iclass 5, count 0 2006.257.17:39:20.73#ibcon#read 6, iclass 5, count 0 2006.257.17:39:20.73#ibcon#end of sib2, iclass 5, count 0 2006.257.17:39:20.73#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:39:20.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:39:20.73#ibcon#[27=USB\r\n] 2006.257.17:39:20.73#ibcon#*before write, iclass 5, count 0 2006.257.17:39:20.73#ibcon#enter sib2, iclass 5, count 0 2006.257.17:39:20.73#ibcon#flushed, iclass 5, count 0 2006.257.17:39:20.73#ibcon#about to write, iclass 5, count 0 2006.257.17:39:20.73#ibcon#wrote, iclass 5, count 0 2006.257.17:39:20.73#ibcon#about to read 3, iclass 5, count 0 2006.257.17:39:20.76#ibcon#read 3, iclass 5, count 0 2006.257.17:39:20.76#ibcon#about to read 4, iclass 5, count 0 2006.257.17:39:20.76#ibcon#read 4, iclass 5, count 0 2006.257.17:39:20.76#ibcon#about to read 5, iclass 5, count 0 2006.257.17:39:20.76#ibcon#read 5, iclass 5, count 0 2006.257.17:39:20.76#ibcon#about to read 6, iclass 5, count 0 2006.257.17:39:20.76#ibcon#read 6, iclass 5, count 0 2006.257.17:39:20.76#ibcon#end of sib2, iclass 5, count 0 2006.257.17:39:20.76#ibcon#*after write, iclass 5, count 0 2006.257.17:39:20.76#ibcon#*before return 0, iclass 5, count 0 2006.257.17:39:20.76#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:20.76#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.17:39:20.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:39:20.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:39:20.76$vck44/vblo=3,649.99 2006.257.17:39:20.76#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.17:39:20.76#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.17:39:20.76#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:20.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:20.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:20.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:20.76#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:39:20.76#ibcon#first serial, iclass 7, count 0 2006.257.17:39:20.76#ibcon#enter sib2, iclass 7, count 0 2006.257.17:39:20.76#ibcon#flushed, iclass 7, count 0 2006.257.17:39:20.76#ibcon#about to write, iclass 7, count 0 2006.257.17:39:20.76#ibcon#wrote, iclass 7, count 0 2006.257.17:39:20.76#ibcon#about to read 3, iclass 7, count 0 2006.257.17:39:20.78#ibcon#read 3, iclass 7, count 0 2006.257.17:39:20.78#ibcon#about to read 4, iclass 7, count 0 2006.257.17:39:20.78#ibcon#read 4, iclass 7, count 0 2006.257.17:39:20.78#ibcon#about to read 5, iclass 7, count 0 2006.257.17:39:20.78#ibcon#read 5, iclass 7, count 0 2006.257.17:39:20.78#ibcon#about to read 6, iclass 7, count 0 2006.257.17:39:20.78#ibcon#read 6, iclass 7, count 0 2006.257.17:39:20.78#ibcon#end of sib2, iclass 7, count 0 2006.257.17:39:20.78#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:39:20.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:39:20.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:39:20.78#ibcon#*before write, iclass 7, count 0 2006.257.17:39:20.78#ibcon#enter sib2, iclass 7, count 0 2006.257.17:39:20.78#ibcon#flushed, iclass 7, count 0 2006.257.17:39:20.78#ibcon#about to write, iclass 7, count 0 2006.257.17:39:20.78#ibcon#wrote, iclass 7, count 0 2006.257.17:39:20.78#ibcon#about to read 3, iclass 7, count 0 2006.257.17:39:20.82#ibcon#read 3, iclass 7, count 0 2006.257.17:39:20.82#ibcon#about to read 4, iclass 7, count 0 2006.257.17:39:20.82#ibcon#read 4, iclass 7, count 0 2006.257.17:39:20.82#ibcon#about to read 5, iclass 7, count 0 2006.257.17:39:20.82#ibcon#read 5, iclass 7, count 0 2006.257.17:39:20.82#ibcon#about to read 6, iclass 7, count 0 2006.257.17:39:20.82#ibcon#read 6, iclass 7, count 0 2006.257.17:39:20.82#ibcon#end of sib2, iclass 7, count 0 2006.257.17:39:20.82#ibcon#*after write, iclass 7, count 0 2006.257.17:39:20.82#ibcon#*before return 0, iclass 7, count 0 2006.257.17:39:20.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:20.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:39:20.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:39:20.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:39:20.82$vck44/vb=3,4 2006.257.17:39:20.82#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.17:39:20.82#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.17:39:20.82#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:20.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:20.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:20.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:20.88#ibcon#enter wrdev, iclass 11, count 2 2006.257.17:39:20.88#ibcon#first serial, iclass 11, count 2 2006.257.17:39:20.88#ibcon#enter sib2, iclass 11, count 2 2006.257.17:39:20.88#ibcon#flushed, iclass 11, count 2 2006.257.17:39:20.88#ibcon#about to write, iclass 11, count 2 2006.257.17:39:20.88#ibcon#wrote, iclass 11, count 2 2006.257.17:39:20.88#ibcon#about to read 3, iclass 11, count 2 2006.257.17:39:20.90#ibcon#read 3, iclass 11, count 2 2006.257.17:39:20.90#ibcon#about to read 4, iclass 11, count 2 2006.257.17:39:20.90#ibcon#read 4, iclass 11, count 2 2006.257.17:39:20.90#ibcon#about to read 5, iclass 11, count 2 2006.257.17:39:20.90#ibcon#read 5, iclass 11, count 2 2006.257.17:39:20.90#ibcon#about to read 6, iclass 11, count 2 2006.257.17:39:20.90#ibcon#read 6, iclass 11, count 2 2006.257.17:39:20.90#ibcon#end of sib2, iclass 11, count 2 2006.257.17:39:20.90#ibcon#*mode == 0, iclass 11, count 2 2006.257.17:39:20.90#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.17:39:20.90#ibcon#[27=AT03-04\r\n] 2006.257.17:39:20.90#ibcon#*before write, iclass 11, count 2 2006.257.17:39:20.90#ibcon#enter sib2, iclass 11, count 2 2006.257.17:39:20.90#ibcon#flushed, iclass 11, count 2 2006.257.17:39:20.90#ibcon#about to write, iclass 11, count 2 2006.257.17:39:20.90#ibcon#wrote, iclass 11, count 2 2006.257.17:39:20.90#ibcon#about to read 3, iclass 11, count 2 2006.257.17:39:20.93#ibcon#read 3, iclass 11, count 2 2006.257.17:39:20.93#ibcon#about to read 4, iclass 11, count 2 2006.257.17:39:20.93#ibcon#read 4, iclass 11, count 2 2006.257.17:39:20.93#ibcon#about to read 5, iclass 11, count 2 2006.257.17:39:20.93#ibcon#read 5, iclass 11, count 2 2006.257.17:39:20.93#ibcon#about to read 6, iclass 11, count 2 2006.257.17:39:20.93#ibcon#read 6, iclass 11, count 2 2006.257.17:39:20.93#ibcon#end of sib2, iclass 11, count 2 2006.257.17:39:20.93#ibcon#*after write, iclass 11, count 2 2006.257.17:39:20.93#ibcon#*before return 0, iclass 11, count 2 2006.257.17:39:20.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:20.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.17:39:20.93#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.17:39:20.93#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:20.93#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:21.01#abcon#<5=/14 1.4 3.2 17.38 971014.2\r\n> 2006.257.17:39:21.03#abcon#{5=INTERFACE CLEAR} 2006.257.17:39:21.05#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:21.05#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:21.05#ibcon#enter wrdev, iclass 11, count 0 2006.257.17:39:21.05#ibcon#first serial, iclass 11, count 0 2006.257.17:39:21.05#ibcon#enter sib2, iclass 11, count 0 2006.257.17:39:21.05#ibcon#flushed, iclass 11, count 0 2006.257.17:39:21.05#ibcon#about to write, iclass 11, count 0 2006.257.17:39:21.05#ibcon#wrote, iclass 11, count 0 2006.257.17:39:21.05#ibcon#about to read 3, iclass 11, count 0 2006.257.17:39:21.07#ibcon#read 3, iclass 11, count 0 2006.257.17:39:21.07#ibcon#about to read 4, iclass 11, count 0 2006.257.17:39:21.07#ibcon#read 4, iclass 11, count 0 2006.257.17:39:21.07#ibcon#about to read 5, iclass 11, count 0 2006.257.17:39:21.07#ibcon#read 5, iclass 11, count 0 2006.257.17:39:21.07#ibcon#about to read 6, iclass 11, count 0 2006.257.17:39:21.07#ibcon#read 6, iclass 11, count 0 2006.257.17:39:21.07#ibcon#end of sib2, iclass 11, count 0 2006.257.17:39:21.07#ibcon#*mode == 0, iclass 11, count 0 2006.257.17:39:21.07#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.17:39:21.07#ibcon#[27=USB\r\n] 2006.257.17:39:21.07#ibcon#*before write, iclass 11, count 0 2006.257.17:39:21.07#ibcon#enter sib2, iclass 11, count 0 2006.257.17:39:21.07#ibcon#flushed, iclass 11, count 0 2006.257.17:39:21.07#ibcon#about to write, iclass 11, count 0 2006.257.17:39:21.07#ibcon#wrote, iclass 11, count 0 2006.257.17:39:21.07#ibcon#about to read 3, iclass 11, count 0 2006.257.17:39:21.09#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:39:21.10#ibcon#read 3, iclass 11, count 0 2006.257.17:39:21.10#ibcon#about to read 4, iclass 11, count 0 2006.257.17:39:21.10#ibcon#read 4, iclass 11, count 0 2006.257.17:39:21.10#ibcon#about to read 5, iclass 11, count 0 2006.257.17:39:21.10#ibcon#read 5, iclass 11, count 0 2006.257.17:39:21.10#ibcon#about to read 6, iclass 11, count 0 2006.257.17:39:21.10#ibcon#read 6, iclass 11, count 0 2006.257.17:39:21.10#ibcon#end of sib2, iclass 11, count 0 2006.257.17:39:21.10#ibcon#*after write, iclass 11, count 0 2006.257.17:39:21.10#ibcon#*before return 0, iclass 11, count 0 2006.257.17:39:21.10#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:21.10#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.17:39:21.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.17:39:21.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.17:39:21.10$vck44/vblo=4,679.99 2006.257.17:39:21.10#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.17:39:21.10#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.17:39:21.10#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:21.10#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:21.10#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:21.10#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:21.10#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:39:21.10#ibcon#first serial, iclass 17, count 0 2006.257.17:39:21.10#ibcon#enter sib2, iclass 17, count 0 2006.257.17:39:21.10#ibcon#flushed, iclass 17, count 0 2006.257.17:39:21.10#ibcon#about to write, iclass 17, count 0 2006.257.17:39:21.10#ibcon#wrote, iclass 17, count 0 2006.257.17:39:21.10#ibcon#about to read 3, iclass 17, count 0 2006.257.17:39:21.12#ibcon#read 3, iclass 17, count 0 2006.257.17:39:21.12#ibcon#about to read 4, iclass 17, count 0 2006.257.17:39:21.12#ibcon#read 4, iclass 17, count 0 2006.257.17:39:21.12#ibcon#about to read 5, iclass 17, count 0 2006.257.17:39:21.12#ibcon#read 5, iclass 17, count 0 2006.257.17:39:21.12#ibcon#about to read 6, iclass 17, count 0 2006.257.17:39:21.12#ibcon#read 6, iclass 17, count 0 2006.257.17:39:21.12#ibcon#end of sib2, iclass 17, count 0 2006.257.17:39:21.12#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:39:21.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:39:21.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:39:21.12#ibcon#*before write, iclass 17, count 0 2006.257.17:39:21.12#ibcon#enter sib2, iclass 17, count 0 2006.257.17:39:21.12#ibcon#flushed, iclass 17, count 0 2006.257.17:39:21.12#ibcon#about to write, iclass 17, count 0 2006.257.17:39:21.12#ibcon#wrote, iclass 17, count 0 2006.257.17:39:21.12#ibcon#about to read 3, iclass 17, count 0 2006.257.17:39:21.16#ibcon#read 3, iclass 17, count 0 2006.257.17:39:21.16#ibcon#about to read 4, iclass 17, count 0 2006.257.17:39:21.16#ibcon#read 4, iclass 17, count 0 2006.257.17:39:21.16#ibcon#about to read 5, iclass 17, count 0 2006.257.17:39:21.16#ibcon#read 5, iclass 17, count 0 2006.257.17:39:21.16#ibcon#about to read 6, iclass 17, count 0 2006.257.17:39:21.16#ibcon#read 6, iclass 17, count 0 2006.257.17:39:21.16#ibcon#end of sib2, iclass 17, count 0 2006.257.17:39:21.16#ibcon#*after write, iclass 17, count 0 2006.257.17:39:21.16#ibcon#*before return 0, iclass 17, count 0 2006.257.17:39:21.16#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:21.16#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.17:39:21.16#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:39:21.16#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:39:21.16$vck44/vb=4,5 2006.257.17:39:21.16#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.17:39:21.16#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.17:39:21.16#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:21.16#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:21.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:21.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:21.22#ibcon#enter wrdev, iclass 19, count 2 2006.257.17:39:21.22#ibcon#first serial, iclass 19, count 2 2006.257.17:39:21.22#ibcon#enter sib2, iclass 19, count 2 2006.257.17:39:21.22#ibcon#flushed, iclass 19, count 2 2006.257.17:39:21.22#ibcon#about to write, iclass 19, count 2 2006.257.17:39:21.22#ibcon#wrote, iclass 19, count 2 2006.257.17:39:21.22#ibcon#about to read 3, iclass 19, count 2 2006.257.17:39:21.24#ibcon#read 3, iclass 19, count 2 2006.257.17:39:21.24#ibcon#about to read 4, iclass 19, count 2 2006.257.17:39:21.24#ibcon#read 4, iclass 19, count 2 2006.257.17:39:21.24#ibcon#about to read 5, iclass 19, count 2 2006.257.17:39:21.24#ibcon#read 5, iclass 19, count 2 2006.257.17:39:21.24#ibcon#about to read 6, iclass 19, count 2 2006.257.17:39:21.24#ibcon#read 6, iclass 19, count 2 2006.257.17:39:21.24#ibcon#end of sib2, iclass 19, count 2 2006.257.17:39:21.24#ibcon#*mode == 0, iclass 19, count 2 2006.257.17:39:21.24#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.17:39:21.24#ibcon#[27=AT04-05\r\n] 2006.257.17:39:21.24#ibcon#*before write, iclass 19, count 2 2006.257.17:39:21.24#ibcon#enter sib2, iclass 19, count 2 2006.257.17:39:21.24#ibcon#flushed, iclass 19, count 2 2006.257.17:39:21.24#ibcon#about to write, iclass 19, count 2 2006.257.17:39:21.24#ibcon#wrote, iclass 19, count 2 2006.257.17:39:21.24#ibcon#about to read 3, iclass 19, count 2 2006.257.17:39:21.27#ibcon#read 3, iclass 19, count 2 2006.257.17:39:21.27#ibcon#about to read 4, iclass 19, count 2 2006.257.17:39:21.27#ibcon#read 4, iclass 19, count 2 2006.257.17:39:21.27#ibcon#about to read 5, iclass 19, count 2 2006.257.17:39:21.27#ibcon#read 5, iclass 19, count 2 2006.257.17:39:21.27#ibcon#about to read 6, iclass 19, count 2 2006.257.17:39:21.27#ibcon#read 6, iclass 19, count 2 2006.257.17:39:21.27#ibcon#end of sib2, iclass 19, count 2 2006.257.17:39:21.27#ibcon#*after write, iclass 19, count 2 2006.257.17:39:21.27#ibcon#*before return 0, iclass 19, count 2 2006.257.17:39:21.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:21.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.17:39:21.27#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.17:39:21.27#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:21.27#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:21.39#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:21.39#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:21.39#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:39:21.39#ibcon#first serial, iclass 19, count 0 2006.257.17:39:21.39#ibcon#enter sib2, iclass 19, count 0 2006.257.17:39:21.39#ibcon#flushed, iclass 19, count 0 2006.257.17:39:21.39#ibcon#about to write, iclass 19, count 0 2006.257.17:39:21.39#ibcon#wrote, iclass 19, count 0 2006.257.17:39:21.39#ibcon#about to read 3, iclass 19, count 0 2006.257.17:39:21.41#ibcon#read 3, iclass 19, count 0 2006.257.17:39:21.41#ibcon#about to read 4, iclass 19, count 0 2006.257.17:39:21.41#ibcon#read 4, iclass 19, count 0 2006.257.17:39:21.41#ibcon#about to read 5, iclass 19, count 0 2006.257.17:39:21.41#ibcon#read 5, iclass 19, count 0 2006.257.17:39:21.41#ibcon#about to read 6, iclass 19, count 0 2006.257.17:39:21.41#ibcon#read 6, iclass 19, count 0 2006.257.17:39:21.41#ibcon#end of sib2, iclass 19, count 0 2006.257.17:39:21.41#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:39:21.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:39:21.41#ibcon#[27=USB\r\n] 2006.257.17:39:21.41#ibcon#*before write, iclass 19, count 0 2006.257.17:39:21.41#ibcon#enter sib2, iclass 19, count 0 2006.257.17:39:21.41#ibcon#flushed, iclass 19, count 0 2006.257.17:39:21.41#ibcon#about to write, iclass 19, count 0 2006.257.17:39:21.41#ibcon#wrote, iclass 19, count 0 2006.257.17:39:21.41#ibcon#about to read 3, iclass 19, count 0 2006.257.17:39:21.44#ibcon#read 3, iclass 19, count 0 2006.257.17:39:21.44#ibcon#about to read 4, iclass 19, count 0 2006.257.17:39:21.44#ibcon#read 4, iclass 19, count 0 2006.257.17:39:21.44#ibcon#about to read 5, iclass 19, count 0 2006.257.17:39:21.44#ibcon#read 5, iclass 19, count 0 2006.257.17:39:21.44#ibcon#about to read 6, iclass 19, count 0 2006.257.17:39:21.44#ibcon#read 6, iclass 19, count 0 2006.257.17:39:21.44#ibcon#end of sib2, iclass 19, count 0 2006.257.17:39:21.44#ibcon#*after write, iclass 19, count 0 2006.257.17:39:21.44#ibcon#*before return 0, iclass 19, count 0 2006.257.17:39:21.44#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:21.44#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.17:39:21.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:39:21.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:39:21.44$vck44/vblo=5,709.99 2006.257.17:39:21.44#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.17:39:21.44#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.17:39:21.44#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:21.44#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:21.44#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:21.44#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:21.44#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:39:21.44#ibcon#first serial, iclass 21, count 0 2006.257.17:39:21.44#ibcon#enter sib2, iclass 21, count 0 2006.257.17:39:21.44#ibcon#flushed, iclass 21, count 0 2006.257.17:39:21.44#ibcon#about to write, iclass 21, count 0 2006.257.17:39:21.44#ibcon#wrote, iclass 21, count 0 2006.257.17:39:21.44#ibcon#about to read 3, iclass 21, count 0 2006.257.17:39:21.46#ibcon#read 3, iclass 21, count 0 2006.257.17:39:21.46#ibcon#about to read 4, iclass 21, count 0 2006.257.17:39:21.46#ibcon#read 4, iclass 21, count 0 2006.257.17:39:21.46#ibcon#about to read 5, iclass 21, count 0 2006.257.17:39:21.46#ibcon#read 5, iclass 21, count 0 2006.257.17:39:21.46#ibcon#about to read 6, iclass 21, count 0 2006.257.17:39:21.46#ibcon#read 6, iclass 21, count 0 2006.257.17:39:21.46#ibcon#end of sib2, iclass 21, count 0 2006.257.17:39:21.46#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:39:21.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:39:21.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:39:21.46#ibcon#*before write, iclass 21, count 0 2006.257.17:39:21.46#ibcon#enter sib2, iclass 21, count 0 2006.257.17:39:21.46#ibcon#flushed, iclass 21, count 0 2006.257.17:39:21.46#ibcon#about to write, iclass 21, count 0 2006.257.17:39:21.46#ibcon#wrote, iclass 21, count 0 2006.257.17:39:21.46#ibcon#about to read 3, iclass 21, count 0 2006.257.17:39:21.50#ibcon#read 3, iclass 21, count 0 2006.257.17:39:21.50#ibcon#about to read 4, iclass 21, count 0 2006.257.17:39:21.50#ibcon#read 4, iclass 21, count 0 2006.257.17:39:21.50#ibcon#about to read 5, iclass 21, count 0 2006.257.17:39:21.50#ibcon#read 5, iclass 21, count 0 2006.257.17:39:21.50#ibcon#about to read 6, iclass 21, count 0 2006.257.17:39:21.50#ibcon#read 6, iclass 21, count 0 2006.257.17:39:21.50#ibcon#end of sib2, iclass 21, count 0 2006.257.17:39:21.50#ibcon#*after write, iclass 21, count 0 2006.257.17:39:21.50#ibcon#*before return 0, iclass 21, count 0 2006.257.17:39:21.50#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:21.50#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.17:39:21.50#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:39:21.50#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:39:21.50$vck44/vb=5,4 2006.257.17:39:21.50#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.17:39:21.50#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.17:39:21.50#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:21.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:21.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:21.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:21.56#ibcon#enter wrdev, iclass 23, count 2 2006.257.17:39:21.56#ibcon#first serial, iclass 23, count 2 2006.257.17:39:21.56#ibcon#enter sib2, iclass 23, count 2 2006.257.17:39:21.56#ibcon#flushed, iclass 23, count 2 2006.257.17:39:21.56#ibcon#about to write, iclass 23, count 2 2006.257.17:39:21.56#ibcon#wrote, iclass 23, count 2 2006.257.17:39:21.56#ibcon#about to read 3, iclass 23, count 2 2006.257.17:39:21.58#ibcon#read 3, iclass 23, count 2 2006.257.17:39:21.58#ibcon#about to read 4, iclass 23, count 2 2006.257.17:39:21.58#ibcon#read 4, iclass 23, count 2 2006.257.17:39:21.58#ibcon#about to read 5, iclass 23, count 2 2006.257.17:39:21.58#ibcon#read 5, iclass 23, count 2 2006.257.17:39:21.58#ibcon#about to read 6, iclass 23, count 2 2006.257.17:39:21.58#ibcon#read 6, iclass 23, count 2 2006.257.17:39:21.58#ibcon#end of sib2, iclass 23, count 2 2006.257.17:39:21.58#ibcon#*mode == 0, iclass 23, count 2 2006.257.17:39:21.58#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.17:39:21.58#ibcon#[27=AT05-04\r\n] 2006.257.17:39:21.58#ibcon#*before write, iclass 23, count 2 2006.257.17:39:21.58#ibcon#enter sib2, iclass 23, count 2 2006.257.17:39:21.58#ibcon#flushed, iclass 23, count 2 2006.257.17:39:21.58#ibcon#about to write, iclass 23, count 2 2006.257.17:39:21.58#ibcon#wrote, iclass 23, count 2 2006.257.17:39:21.58#ibcon#about to read 3, iclass 23, count 2 2006.257.17:39:21.61#ibcon#read 3, iclass 23, count 2 2006.257.17:39:21.61#ibcon#about to read 4, iclass 23, count 2 2006.257.17:39:21.61#ibcon#read 4, iclass 23, count 2 2006.257.17:39:21.61#ibcon#about to read 5, iclass 23, count 2 2006.257.17:39:21.61#ibcon#read 5, iclass 23, count 2 2006.257.17:39:21.61#ibcon#about to read 6, iclass 23, count 2 2006.257.17:39:21.61#ibcon#read 6, iclass 23, count 2 2006.257.17:39:21.61#ibcon#end of sib2, iclass 23, count 2 2006.257.17:39:21.61#ibcon#*after write, iclass 23, count 2 2006.257.17:39:21.61#ibcon#*before return 0, iclass 23, count 2 2006.257.17:39:21.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:21.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.17:39:21.61#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.17:39:21.61#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:21.61#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:21.73#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:21.73#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:21.73#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:39:21.73#ibcon#first serial, iclass 23, count 0 2006.257.17:39:21.73#ibcon#enter sib2, iclass 23, count 0 2006.257.17:39:21.73#ibcon#flushed, iclass 23, count 0 2006.257.17:39:21.73#ibcon#about to write, iclass 23, count 0 2006.257.17:39:21.73#ibcon#wrote, iclass 23, count 0 2006.257.17:39:21.73#ibcon#about to read 3, iclass 23, count 0 2006.257.17:39:21.75#ibcon#read 3, iclass 23, count 0 2006.257.17:39:21.75#ibcon#about to read 4, iclass 23, count 0 2006.257.17:39:21.75#ibcon#read 4, iclass 23, count 0 2006.257.17:39:21.75#ibcon#about to read 5, iclass 23, count 0 2006.257.17:39:21.75#ibcon#read 5, iclass 23, count 0 2006.257.17:39:21.75#ibcon#about to read 6, iclass 23, count 0 2006.257.17:39:21.75#ibcon#read 6, iclass 23, count 0 2006.257.17:39:21.75#ibcon#end of sib2, iclass 23, count 0 2006.257.17:39:21.75#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:39:21.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:39:21.75#ibcon#[27=USB\r\n] 2006.257.17:39:21.75#ibcon#*before write, iclass 23, count 0 2006.257.17:39:21.75#ibcon#enter sib2, iclass 23, count 0 2006.257.17:39:21.75#ibcon#flushed, iclass 23, count 0 2006.257.17:39:21.75#ibcon#about to write, iclass 23, count 0 2006.257.17:39:21.75#ibcon#wrote, iclass 23, count 0 2006.257.17:39:21.75#ibcon#about to read 3, iclass 23, count 0 2006.257.17:39:21.78#ibcon#read 3, iclass 23, count 0 2006.257.17:39:21.78#ibcon#about to read 4, iclass 23, count 0 2006.257.17:39:21.78#ibcon#read 4, iclass 23, count 0 2006.257.17:39:21.78#ibcon#about to read 5, iclass 23, count 0 2006.257.17:39:21.78#ibcon#read 5, iclass 23, count 0 2006.257.17:39:21.78#ibcon#about to read 6, iclass 23, count 0 2006.257.17:39:21.78#ibcon#read 6, iclass 23, count 0 2006.257.17:39:21.78#ibcon#end of sib2, iclass 23, count 0 2006.257.17:39:21.78#ibcon#*after write, iclass 23, count 0 2006.257.17:39:21.78#ibcon#*before return 0, iclass 23, count 0 2006.257.17:39:21.78#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:21.78#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.17:39:21.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:39:21.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:39:21.78$vck44/vblo=6,719.99 2006.257.17:39:21.78#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.17:39:21.78#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.17:39:21.78#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:21.78#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:21.78#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:21.78#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:21.78#ibcon#enter wrdev, iclass 25, count 0 2006.257.17:39:21.78#ibcon#first serial, iclass 25, count 0 2006.257.17:39:21.78#ibcon#enter sib2, iclass 25, count 0 2006.257.17:39:21.78#ibcon#flushed, iclass 25, count 0 2006.257.17:39:21.78#ibcon#about to write, iclass 25, count 0 2006.257.17:39:21.78#ibcon#wrote, iclass 25, count 0 2006.257.17:39:21.78#ibcon#about to read 3, iclass 25, count 0 2006.257.17:39:21.80#ibcon#read 3, iclass 25, count 0 2006.257.17:39:21.80#ibcon#about to read 4, iclass 25, count 0 2006.257.17:39:21.80#ibcon#read 4, iclass 25, count 0 2006.257.17:39:21.80#ibcon#about to read 5, iclass 25, count 0 2006.257.17:39:21.80#ibcon#read 5, iclass 25, count 0 2006.257.17:39:21.80#ibcon#about to read 6, iclass 25, count 0 2006.257.17:39:21.80#ibcon#read 6, iclass 25, count 0 2006.257.17:39:21.80#ibcon#end of sib2, iclass 25, count 0 2006.257.17:39:21.80#ibcon#*mode == 0, iclass 25, count 0 2006.257.17:39:21.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.17:39:21.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:39:21.80#ibcon#*before write, iclass 25, count 0 2006.257.17:39:21.80#ibcon#enter sib2, iclass 25, count 0 2006.257.17:39:21.80#ibcon#flushed, iclass 25, count 0 2006.257.17:39:21.80#ibcon#about to write, iclass 25, count 0 2006.257.17:39:21.80#ibcon#wrote, iclass 25, count 0 2006.257.17:39:21.80#ibcon#about to read 3, iclass 25, count 0 2006.257.17:39:21.84#ibcon#read 3, iclass 25, count 0 2006.257.17:39:21.84#ibcon#about to read 4, iclass 25, count 0 2006.257.17:39:21.84#ibcon#read 4, iclass 25, count 0 2006.257.17:39:21.84#ibcon#about to read 5, iclass 25, count 0 2006.257.17:39:21.84#ibcon#read 5, iclass 25, count 0 2006.257.17:39:21.84#ibcon#about to read 6, iclass 25, count 0 2006.257.17:39:21.84#ibcon#read 6, iclass 25, count 0 2006.257.17:39:21.84#ibcon#end of sib2, iclass 25, count 0 2006.257.17:39:21.84#ibcon#*after write, iclass 25, count 0 2006.257.17:39:21.84#ibcon#*before return 0, iclass 25, count 0 2006.257.17:39:21.84#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:21.84#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.17:39:21.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.17:39:21.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.17:39:21.84$vck44/vb=6,4 2006.257.17:39:21.84#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.17:39:21.84#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.17:39:21.84#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:21.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:21.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:21.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:21.90#ibcon#enter wrdev, iclass 27, count 2 2006.257.17:39:21.90#ibcon#first serial, iclass 27, count 2 2006.257.17:39:21.90#ibcon#enter sib2, iclass 27, count 2 2006.257.17:39:21.90#ibcon#flushed, iclass 27, count 2 2006.257.17:39:21.90#ibcon#about to write, iclass 27, count 2 2006.257.17:39:21.90#ibcon#wrote, iclass 27, count 2 2006.257.17:39:21.90#ibcon#about to read 3, iclass 27, count 2 2006.257.17:39:21.92#ibcon#read 3, iclass 27, count 2 2006.257.17:39:21.92#ibcon#about to read 4, iclass 27, count 2 2006.257.17:39:21.92#ibcon#read 4, iclass 27, count 2 2006.257.17:39:21.92#ibcon#about to read 5, iclass 27, count 2 2006.257.17:39:21.92#ibcon#read 5, iclass 27, count 2 2006.257.17:39:21.92#ibcon#about to read 6, iclass 27, count 2 2006.257.17:39:21.92#ibcon#read 6, iclass 27, count 2 2006.257.17:39:21.92#ibcon#end of sib2, iclass 27, count 2 2006.257.17:39:21.92#ibcon#*mode == 0, iclass 27, count 2 2006.257.17:39:21.92#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.17:39:21.92#ibcon#[27=AT06-04\r\n] 2006.257.17:39:21.92#ibcon#*before write, iclass 27, count 2 2006.257.17:39:21.92#ibcon#enter sib2, iclass 27, count 2 2006.257.17:39:21.92#ibcon#flushed, iclass 27, count 2 2006.257.17:39:21.92#ibcon#about to write, iclass 27, count 2 2006.257.17:39:21.92#ibcon#wrote, iclass 27, count 2 2006.257.17:39:21.92#ibcon#about to read 3, iclass 27, count 2 2006.257.17:39:21.95#ibcon#read 3, iclass 27, count 2 2006.257.17:39:21.95#ibcon#about to read 4, iclass 27, count 2 2006.257.17:39:21.95#ibcon#read 4, iclass 27, count 2 2006.257.17:39:21.95#ibcon#about to read 5, iclass 27, count 2 2006.257.17:39:21.95#ibcon#read 5, iclass 27, count 2 2006.257.17:39:21.95#ibcon#about to read 6, iclass 27, count 2 2006.257.17:39:21.95#ibcon#read 6, iclass 27, count 2 2006.257.17:39:21.95#ibcon#end of sib2, iclass 27, count 2 2006.257.17:39:21.95#ibcon#*after write, iclass 27, count 2 2006.257.17:39:21.95#ibcon#*before return 0, iclass 27, count 2 2006.257.17:39:21.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:21.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.17:39:21.95#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.17:39:21.95#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:21.95#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:22.07#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:22.07#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:22.07#ibcon#enter wrdev, iclass 27, count 0 2006.257.17:39:22.07#ibcon#first serial, iclass 27, count 0 2006.257.17:39:22.07#ibcon#enter sib2, iclass 27, count 0 2006.257.17:39:22.07#ibcon#flushed, iclass 27, count 0 2006.257.17:39:22.07#ibcon#about to write, iclass 27, count 0 2006.257.17:39:22.07#ibcon#wrote, iclass 27, count 0 2006.257.17:39:22.07#ibcon#about to read 3, iclass 27, count 0 2006.257.17:39:22.09#ibcon#read 3, iclass 27, count 0 2006.257.17:39:22.09#ibcon#about to read 4, iclass 27, count 0 2006.257.17:39:22.09#ibcon#read 4, iclass 27, count 0 2006.257.17:39:22.09#ibcon#about to read 5, iclass 27, count 0 2006.257.17:39:22.09#ibcon#read 5, iclass 27, count 0 2006.257.17:39:22.09#ibcon#about to read 6, iclass 27, count 0 2006.257.17:39:22.09#ibcon#read 6, iclass 27, count 0 2006.257.17:39:22.09#ibcon#end of sib2, iclass 27, count 0 2006.257.17:39:22.09#ibcon#*mode == 0, iclass 27, count 0 2006.257.17:39:22.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.17:39:22.09#ibcon#[27=USB\r\n] 2006.257.17:39:22.09#ibcon#*before write, iclass 27, count 0 2006.257.17:39:22.09#ibcon#enter sib2, iclass 27, count 0 2006.257.17:39:22.09#ibcon#flushed, iclass 27, count 0 2006.257.17:39:22.09#ibcon#about to write, iclass 27, count 0 2006.257.17:39:22.09#ibcon#wrote, iclass 27, count 0 2006.257.17:39:22.09#ibcon#about to read 3, iclass 27, count 0 2006.257.17:39:22.12#ibcon#read 3, iclass 27, count 0 2006.257.17:39:22.12#ibcon#about to read 4, iclass 27, count 0 2006.257.17:39:22.12#ibcon#read 4, iclass 27, count 0 2006.257.17:39:22.12#ibcon#about to read 5, iclass 27, count 0 2006.257.17:39:22.12#ibcon#read 5, iclass 27, count 0 2006.257.17:39:22.12#ibcon#about to read 6, iclass 27, count 0 2006.257.17:39:22.12#ibcon#read 6, iclass 27, count 0 2006.257.17:39:22.12#ibcon#end of sib2, iclass 27, count 0 2006.257.17:39:22.12#ibcon#*after write, iclass 27, count 0 2006.257.17:39:22.12#ibcon#*before return 0, iclass 27, count 0 2006.257.17:39:22.12#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:22.12#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.17:39:22.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.17:39:22.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.17:39:22.12$vck44/vblo=7,734.99 2006.257.17:39:22.12#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.17:39:22.12#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.17:39:22.12#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:22.12#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:22.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:22.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:22.12#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:39:22.12#ibcon#first serial, iclass 29, count 0 2006.257.17:39:22.12#ibcon#enter sib2, iclass 29, count 0 2006.257.17:39:22.12#ibcon#flushed, iclass 29, count 0 2006.257.17:39:22.12#ibcon#about to write, iclass 29, count 0 2006.257.17:39:22.12#ibcon#wrote, iclass 29, count 0 2006.257.17:39:22.12#ibcon#about to read 3, iclass 29, count 0 2006.257.17:39:22.14#ibcon#read 3, iclass 29, count 0 2006.257.17:39:22.14#ibcon#about to read 4, iclass 29, count 0 2006.257.17:39:22.14#ibcon#read 4, iclass 29, count 0 2006.257.17:39:22.14#ibcon#about to read 5, iclass 29, count 0 2006.257.17:39:22.14#ibcon#read 5, iclass 29, count 0 2006.257.17:39:22.14#ibcon#about to read 6, iclass 29, count 0 2006.257.17:39:22.14#ibcon#read 6, iclass 29, count 0 2006.257.17:39:22.14#ibcon#end of sib2, iclass 29, count 0 2006.257.17:39:22.14#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:39:22.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:39:22.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:39:22.14#ibcon#*before write, iclass 29, count 0 2006.257.17:39:22.14#ibcon#enter sib2, iclass 29, count 0 2006.257.17:39:22.14#ibcon#flushed, iclass 29, count 0 2006.257.17:39:22.14#ibcon#about to write, iclass 29, count 0 2006.257.17:39:22.14#ibcon#wrote, iclass 29, count 0 2006.257.17:39:22.14#ibcon#about to read 3, iclass 29, count 0 2006.257.17:39:22.18#ibcon#read 3, iclass 29, count 0 2006.257.17:39:22.18#ibcon#about to read 4, iclass 29, count 0 2006.257.17:39:22.18#ibcon#read 4, iclass 29, count 0 2006.257.17:39:22.18#ibcon#about to read 5, iclass 29, count 0 2006.257.17:39:22.18#ibcon#read 5, iclass 29, count 0 2006.257.17:39:22.18#ibcon#about to read 6, iclass 29, count 0 2006.257.17:39:22.18#ibcon#read 6, iclass 29, count 0 2006.257.17:39:22.18#ibcon#end of sib2, iclass 29, count 0 2006.257.17:39:22.18#ibcon#*after write, iclass 29, count 0 2006.257.17:39:22.18#ibcon#*before return 0, iclass 29, count 0 2006.257.17:39:22.18#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:22.18#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.17:39:22.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:39:22.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:39:22.18$vck44/vb=7,4 2006.257.17:39:22.18#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.17:39:22.18#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.17:39:22.18#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:22.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:22.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:22.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:22.24#ibcon#enter wrdev, iclass 31, count 2 2006.257.17:39:22.24#ibcon#first serial, iclass 31, count 2 2006.257.17:39:22.24#ibcon#enter sib2, iclass 31, count 2 2006.257.17:39:22.24#ibcon#flushed, iclass 31, count 2 2006.257.17:39:22.24#ibcon#about to write, iclass 31, count 2 2006.257.17:39:22.24#ibcon#wrote, iclass 31, count 2 2006.257.17:39:22.24#ibcon#about to read 3, iclass 31, count 2 2006.257.17:39:22.26#ibcon#read 3, iclass 31, count 2 2006.257.17:39:22.26#ibcon#about to read 4, iclass 31, count 2 2006.257.17:39:22.26#ibcon#read 4, iclass 31, count 2 2006.257.17:39:22.26#ibcon#about to read 5, iclass 31, count 2 2006.257.17:39:22.26#ibcon#read 5, iclass 31, count 2 2006.257.17:39:22.26#ibcon#about to read 6, iclass 31, count 2 2006.257.17:39:22.26#ibcon#read 6, iclass 31, count 2 2006.257.17:39:22.26#ibcon#end of sib2, iclass 31, count 2 2006.257.17:39:22.26#ibcon#*mode == 0, iclass 31, count 2 2006.257.17:39:22.26#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.17:39:22.26#ibcon#[27=AT07-04\r\n] 2006.257.17:39:22.26#ibcon#*before write, iclass 31, count 2 2006.257.17:39:22.26#ibcon#enter sib2, iclass 31, count 2 2006.257.17:39:22.26#ibcon#flushed, iclass 31, count 2 2006.257.17:39:22.26#ibcon#about to write, iclass 31, count 2 2006.257.17:39:22.26#ibcon#wrote, iclass 31, count 2 2006.257.17:39:22.26#ibcon#about to read 3, iclass 31, count 2 2006.257.17:39:22.29#ibcon#read 3, iclass 31, count 2 2006.257.17:39:22.29#ibcon#about to read 4, iclass 31, count 2 2006.257.17:39:22.29#ibcon#read 4, iclass 31, count 2 2006.257.17:39:22.29#ibcon#about to read 5, iclass 31, count 2 2006.257.17:39:22.29#ibcon#read 5, iclass 31, count 2 2006.257.17:39:22.29#ibcon#about to read 6, iclass 31, count 2 2006.257.17:39:22.29#ibcon#read 6, iclass 31, count 2 2006.257.17:39:22.29#ibcon#end of sib2, iclass 31, count 2 2006.257.17:39:22.29#ibcon#*after write, iclass 31, count 2 2006.257.17:39:22.29#ibcon#*before return 0, iclass 31, count 2 2006.257.17:39:22.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:22.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.17:39:22.29#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.17:39:22.29#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:22.29#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:22.41#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:22.41#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:22.41#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:39:22.41#ibcon#first serial, iclass 31, count 0 2006.257.17:39:22.41#ibcon#enter sib2, iclass 31, count 0 2006.257.17:39:22.41#ibcon#flushed, iclass 31, count 0 2006.257.17:39:22.41#ibcon#about to write, iclass 31, count 0 2006.257.17:39:22.41#ibcon#wrote, iclass 31, count 0 2006.257.17:39:22.41#ibcon#about to read 3, iclass 31, count 0 2006.257.17:39:22.43#ibcon#read 3, iclass 31, count 0 2006.257.17:39:22.43#ibcon#about to read 4, iclass 31, count 0 2006.257.17:39:22.43#ibcon#read 4, iclass 31, count 0 2006.257.17:39:22.43#ibcon#about to read 5, iclass 31, count 0 2006.257.17:39:22.43#ibcon#read 5, iclass 31, count 0 2006.257.17:39:22.43#ibcon#about to read 6, iclass 31, count 0 2006.257.17:39:22.43#ibcon#read 6, iclass 31, count 0 2006.257.17:39:22.43#ibcon#end of sib2, iclass 31, count 0 2006.257.17:39:22.43#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:39:22.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:39:22.43#ibcon#[27=USB\r\n] 2006.257.17:39:22.43#ibcon#*before write, iclass 31, count 0 2006.257.17:39:22.43#ibcon#enter sib2, iclass 31, count 0 2006.257.17:39:22.43#ibcon#flushed, iclass 31, count 0 2006.257.17:39:22.43#ibcon#about to write, iclass 31, count 0 2006.257.17:39:22.43#ibcon#wrote, iclass 31, count 0 2006.257.17:39:22.43#ibcon#about to read 3, iclass 31, count 0 2006.257.17:39:22.46#ibcon#read 3, iclass 31, count 0 2006.257.17:39:22.46#ibcon#about to read 4, iclass 31, count 0 2006.257.17:39:22.46#ibcon#read 4, iclass 31, count 0 2006.257.17:39:22.46#ibcon#about to read 5, iclass 31, count 0 2006.257.17:39:22.46#ibcon#read 5, iclass 31, count 0 2006.257.17:39:22.46#ibcon#about to read 6, iclass 31, count 0 2006.257.17:39:22.46#ibcon#read 6, iclass 31, count 0 2006.257.17:39:22.46#ibcon#end of sib2, iclass 31, count 0 2006.257.17:39:22.46#ibcon#*after write, iclass 31, count 0 2006.257.17:39:22.46#ibcon#*before return 0, iclass 31, count 0 2006.257.17:39:22.46#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:22.46#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.17:39:22.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:39:22.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:39:22.46$vck44/vblo=8,744.99 2006.257.17:39:22.46#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.17:39:22.46#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.17:39:22.46#ibcon#ireg 17 cls_cnt 0 2006.257.17:39:22.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:22.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:22.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:22.46#ibcon#enter wrdev, iclass 33, count 0 2006.257.17:39:22.46#ibcon#first serial, iclass 33, count 0 2006.257.17:39:22.46#ibcon#enter sib2, iclass 33, count 0 2006.257.17:39:22.46#ibcon#flushed, iclass 33, count 0 2006.257.17:39:22.46#ibcon#about to write, iclass 33, count 0 2006.257.17:39:22.46#ibcon#wrote, iclass 33, count 0 2006.257.17:39:22.46#ibcon#about to read 3, iclass 33, count 0 2006.257.17:39:22.48#ibcon#read 3, iclass 33, count 0 2006.257.17:39:22.48#ibcon#about to read 4, iclass 33, count 0 2006.257.17:39:22.48#ibcon#read 4, iclass 33, count 0 2006.257.17:39:22.48#ibcon#about to read 5, iclass 33, count 0 2006.257.17:39:22.48#ibcon#read 5, iclass 33, count 0 2006.257.17:39:22.48#ibcon#about to read 6, iclass 33, count 0 2006.257.17:39:22.48#ibcon#read 6, iclass 33, count 0 2006.257.17:39:22.48#ibcon#end of sib2, iclass 33, count 0 2006.257.17:39:22.48#ibcon#*mode == 0, iclass 33, count 0 2006.257.17:39:22.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.17:39:22.48#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:39:22.48#ibcon#*before write, iclass 33, count 0 2006.257.17:39:22.48#ibcon#enter sib2, iclass 33, count 0 2006.257.17:39:22.48#ibcon#flushed, iclass 33, count 0 2006.257.17:39:22.48#ibcon#about to write, iclass 33, count 0 2006.257.17:39:22.48#ibcon#wrote, iclass 33, count 0 2006.257.17:39:22.48#ibcon#about to read 3, iclass 33, count 0 2006.257.17:39:22.52#ibcon#read 3, iclass 33, count 0 2006.257.17:39:22.52#ibcon#about to read 4, iclass 33, count 0 2006.257.17:39:22.52#ibcon#read 4, iclass 33, count 0 2006.257.17:39:22.52#ibcon#about to read 5, iclass 33, count 0 2006.257.17:39:22.52#ibcon#read 5, iclass 33, count 0 2006.257.17:39:22.52#ibcon#about to read 6, iclass 33, count 0 2006.257.17:39:22.52#ibcon#read 6, iclass 33, count 0 2006.257.17:39:22.52#ibcon#end of sib2, iclass 33, count 0 2006.257.17:39:22.52#ibcon#*after write, iclass 33, count 0 2006.257.17:39:22.52#ibcon#*before return 0, iclass 33, count 0 2006.257.17:39:22.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:22.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.17:39:22.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.17:39:22.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.17:39:22.52$vck44/vb=8,4 2006.257.17:39:22.52#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.17:39:22.52#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.17:39:22.52#ibcon#ireg 11 cls_cnt 2 2006.257.17:39:22.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:22.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:22.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:22.58#ibcon#enter wrdev, iclass 35, count 2 2006.257.17:39:22.58#ibcon#first serial, iclass 35, count 2 2006.257.17:39:22.58#ibcon#enter sib2, iclass 35, count 2 2006.257.17:39:22.58#ibcon#flushed, iclass 35, count 2 2006.257.17:39:22.58#ibcon#about to write, iclass 35, count 2 2006.257.17:39:22.58#ibcon#wrote, iclass 35, count 2 2006.257.17:39:22.58#ibcon#about to read 3, iclass 35, count 2 2006.257.17:39:22.60#ibcon#read 3, iclass 35, count 2 2006.257.17:39:22.60#ibcon#about to read 4, iclass 35, count 2 2006.257.17:39:22.60#ibcon#read 4, iclass 35, count 2 2006.257.17:39:22.60#ibcon#about to read 5, iclass 35, count 2 2006.257.17:39:22.60#ibcon#read 5, iclass 35, count 2 2006.257.17:39:22.60#ibcon#about to read 6, iclass 35, count 2 2006.257.17:39:22.60#ibcon#read 6, iclass 35, count 2 2006.257.17:39:22.60#ibcon#end of sib2, iclass 35, count 2 2006.257.17:39:22.60#ibcon#*mode == 0, iclass 35, count 2 2006.257.17:39:22.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.17:39:22.60#ibcon#[27=AT08-04\r\n] 2006.257.17:39:22.60#ibcon#*before write, iclass 35, count 2 2006.257.17:39:22.60#ibcon#enter sib2, iclass 35, count 2 2006.257.17:39:22.60#ibcon#flushed, iclass 35, count 2 2006.257.17:39:22.60#ibcon#about to write, iclass 35, count 2 2006.257.17:39:22.60#ibcon#wrote, iclass 35, count 2 2006.257.17:39:22.60#ibcon#about to read 3, iclass 35, count 2 2006.257.17:39:22.63#ibcon#read 3, iclass 35, count 2 2006.257.17:39:22.63#ibcon#about to read 4, iclass 35, count 2 2006.257.17:39:22.63#ibcon#read 4, iclass 35, count 2 2006.257.17:39:22.63#ibcon#about to read 5, iclass 35, count 2 2006.257.17:39:22.63#ibcon#read 5, iclass 35, count 2 2006.257.17:39:22.63#ibcon#about to read 6, iclass 35, count 2 2006.257.17:39:22.63#ibcon#read 6, iclass 35, count 2 2006.257.17:39:22.63#ibcon#end of sib2, iclass 35, count 2 2006.257.17:39:22.63#ibcon#*after write, iclass 35, count 2 2006.257.17:39:22.63#ibcon#*before return 0, iclass 35, count 2 2006.257.17:39:22.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:22.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.17:39:22.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.17:39:22.63#ibcon#ireg 7 cls_cnt 0 2006.257.17:39:22.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:22.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:22.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:22.75#ibcon#enter wrdev, iclass 35, count 0 2006.257.17:39:22.75#ibcon#first serial, iclass 35, count 0 2006.257.17:39:22.75#ibcon#enter sib2, iclass 35, count 0 2006.257.17:39:22.75#ibcon#flushed, iclass 35, count 0 2006.257.17:39:22.75#ibcon#about to write, iclass 35, count 0 2006.257.17:39:22.75#ibcon#wrote, iclass 35, count 0 2006.257.17:39:22.75#ibcon#about to read 3, iclass 35, count 0 2006.257.17:39:22.77#ibcon#read 3, iclass 35, count 0 2006.257.17:39:22.77#ibcon#about to read 4, iclass 35, count 0 2006.257.17:39:22.77#ibcon#read 4, iclass 35, count 0 2006.257.17:39:22.77#ibcon#about to read 5, iclass 35, count 0 2006.257.17:39:22.77#ibcon#read 5, iclass 35, count 0 2006.257.17:39:22.77#ibcon#about to read 6, iclass 35, count 0 2006.257.17:39:22.77#ibcon#read 6, iclass 35, count 0 2006.257.17:39:22.77#ibcon#end of sib2, iclass 35, count 0 2006.257.17:39:22.77#ibcon#*mode == 0, iclass 35, count 0 2006.257.17:39:22.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.17:39:22.77#ibcon#[27=USB\r\n] 2006.257.17:39:22.77#ibcon#*before write, iclass 35, count 0 2006.257.17:39:22.77#ibcon#enter sib2, iclass 35, count 0 2006.257.17:39:22.77#ibcon#flushed, iclass 35, count 0 2006.257.17:39:22.77#ibcon#about to write, iclass 35, count 0 2006.257.17:39:22.77#ibcon#wrote, iclass 35, count 0 2006.257.17:39:22.77#ibcon#about to read 3, iclass 35, count 0 2006.257.17:39:22.80#ibcon#read 3, iclass 35, count 0 2006.257.17:39:22.80#ibcon#about to read 4, iclass 35, count 0 2006.257.17:39:22.80#ibcon#read 4, iclass 35, count 0 2006.257.17:39:22.80#ibcon#about to read 5, iclass 35, count 0 2006.257.17:39:22.80#ibcon#read 5, iclass 35, count 0 2006.257.17:39:22.80#ibcon#about to read 6, iclass 35, count 0 2006.257.17:39:22.80#ibcon#read 6, iclass 35, count 0 2006.257.17:39:22.80#ibcon#end of sib2, iclass 35, count 0 2006.257.17:39:22.80#ibcon#*after write, iclass 35, count 0 2006.257.17:39:22.80#ibcon#*before return 0, iclass 35, count 0 2006.257.17:39:22.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:22.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.17:39:22.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.17:39:22.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.17:39:22.80$vck44/vabw=wide 2006.257.17:39:22.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.17:39:22.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.17:39:22.80#ibcon#ireg 8 cls_cnt 0 2006.257.17:39:22.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:22.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:22.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:22.80#ibcon#enter wrdev, iclass 37, count 0 2006.257.17:39:22.80#ibcon#first serial, iclass 37, count 0 2006.257.17:39:22.80#ibcon#enter sib2, iclass 37, count 0 2006.257.17:39:22.80#ibcon#flushed, iclass 37, count 0 2006.257.17:39:22.80#ibcon#about to write, iclass 37, count 0 2006.257.17:39:22.80#ibcon#wrote, iclass 37, count 0 2006.257.17:39:22.80#ibcon#about to read 3, iclass 37, count 0 2006.257.17:39:22.82#ibcon#read 3, iclass 37, count 0 2006.257.17:39:22.82#ibcon#about to read 4, iclass 37, count 0 2006.257.17:39:22.82#ibcon#read 4, iclass 37, count 0 2006.257.17:39:22.82#ibcon#about to read 5, iclass 37, count 0 2006.257.17:39:22.82#ibcon#read 5, iclass 37, count 0 2006.257.17:39:22.82#ibcon#about to read 6, iclass 37, count 0 2006.257.17:39:22.82#ibcon#read 6, iclass 37, count 0 2006.257.17:39:22.82#ibcon#end of sib2, iclass 37, count 0 2006.257.17:39:22.82#ibcon#*mode == 0, iclass 37, count 0 2006.257.17:39:22.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.17:39:22.82#ibcon#[25=BW32\r\n] 2006.257.17:39:22.82#ibcon#*before write, iclass 37, count 0 2006.257.17:39:22.82#ibcon#enter sib2, iclass 37, count 0 2006.257.17:39:22.82#ibcon#flushed, iclass 37, count 0 2006.257.17:39:22.82#ibcon#about to write, iclass 37, count 0 2006.257.17:39:22.82#ibcon#wrote, iclass 37, count 0 2006.257.17:39:22.82#ibcon#about to read 3, iclass 37, count 0 2006.257.17:39:22.85#ibcon#read 3, iclass 37, count 0 2006.257.17:39:22.85#ibcon#about to read 4, iclass 37, count 0 2006.257.17:39:22.85#ibcon#read 4, iclass 37, count 0 2006.257.17:39:22.85#ibcon#about to read 5, iclass 37, count 0 2006.257.17:39:22.85#ibcon#read 5, iclass 37, count 0 2006.257.17:39:22.85#ibcon#about to read 6, iclass 37, count 0 2006.257.17:39:22.85#ibcon#read 6, iclass 37, count 0 2006.257.17:39:22.85#ibcon#end of sib2, iclass 37, count 0 2006.257.17:39:22.85#ibcon#*after write, iclass 37, count 0 2006.257.17:39:22.85#ibcon#*before return 0, iclass 37, count 0 2006.257.17:39:22.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:22.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.17:39:22.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.17:39:22.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.17:39:22.85$vck44/vbbw=wide 2006.257.17:39:22.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.17:39:22.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.17:39:22.85#ibcon#ireg 8 cls_cnt 0 2006.257.17:39:22.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:39:22.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:39:22.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:39:22.92#ibcon#enter wrdev, iclass 39, count 0 2006.257.17:39:22.92#ibcon#first serial, iclass 39, count 0 2006.257.17:39:22.92#ibcon#enter sib2, iclass 39, count 0 2006.257.17:39:22.92#ibcon#flushed, iclass 39, count 0 2006.257.17:39:22.92#ibcon#about to write, iclass 39, count 0 2006.257.17:39:22.92#ibcon#wrote, iclass 39, count 0 2006.257.17:39:22.92#ibcon#about to read 3, iclass 39, count 0 2006.257.17:39:22.94#ibcon#read 3, iclass 39, count 0 2006.257.17:39:22.94#ibcon#about to read 4, iclass 39, count 0 2006.257.17:39:22.94#ibcon#read 4, iclass 39, count 0 2006.257.17:39:22.94#ibcon#about to read 5, iclass 39, count 0 2006.257.17:39:22.94#ibcon#read 5, iclass 39, count 0 2006.257.17:39:22.94#ibcon#about to read 6, iclass 39, count 0 2006.257.17:39:22.94#ibcon#read 6, iclass 39, count 0 2006.257.17:39:22.94#ibcon#end of sib2, iclass 39, count 0 2006.257.17:39:22.94#ibcon#*mode == 0, iclass 39, count 0 2006.257.17:39:22.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.17:39:22.94#ibcon#[27=BW32\r\n] 2006.257.17:39:22.94#ibcon#*before write, iclass 39, count 0 2006.257.17:39:22.94#ibcon#enter sib2, iclass 39, count 0 2006.257.17:39:22.94#ibcon#flushed, iclass 39, count 0 2006.257.17:39:22.94#ibcon#about to write, iclass 39, count 0 2006.257.17:39:22.94#ibcon#wrote, iclass 39, count 0 2006.257.17:39:22.94#ibcon#about to read 3, iclass 39, count 0 2006.257.17:39:22.97#ibcon#read 3, iclass 39, count 0 2006.257.17:39:22.97#ibcon#about to read 4, iclass 39, count 0 2006.257.17:39:22.97#ibcon#read 4, iclass 39, count 0 2006.257.17:39:22.97#ibcon#about to read 5, iclass 39, count 0 2006.257.17:39:22.97#ibcon#read 5, iclass 39, count 0 2006.257.17:39:22.97#ibcon#about to read 6, iclass 39, count 0 2006.257.17:39:22.97#ibcon#read 6, iclass 39, count 0 2006.257.17:39:22.97#ibcon#end of sib2, iclass 39, count 0 2006.257.17:39:22.97#ibcon#*after write, iclass 39, count 0 2006.257.17:39:22.97#ibcon#*before return 0, iclass 39, count 0 2006.257.17:39:22.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:39:22.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:39:22.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.17:39:22.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.17:39:22.97$setupk4/ifdk4 2006.257.17:39:22.97$ifdk4/lo= 2006.257.17:39:22.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:39:22.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:39:22.97$ifdk4/patch= 2006.257.17:39:22.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:39:22.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:39:22.97$setupk4/!*+20s 2006.257.17:39:31.18#abcon#<5=/14 1.4 3.2 17.38 971014.2\r\n> 2006.257.17:39:31.20#abcon#{5=INTERFACE CLEAR} 2006.257.17:39:31.26#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:39:36.14#trakl#Source acquired 2006.257.17:39:37.14#flagr#flagr/antenna,acquired 2006.257.17:39:37.48$setupk4/"tpicd 2006.257.17:39:37.48$setupk4/echo=off 2006.257.17:39:37.48$setupk4/xlog=off 2006.257.17:39:37.48:!2006.257.17:45:25 2006.257.17:45:25.00:preob 2006.257.17:45:26.13/onsource/TRACKING 2006.257.17:45:26.13:!2006.257.17:45:35 2006.257.17:45:35.00:"tape 2006.257.17:45:35.00:"st=record 2006.257.17:45:35.00:data_valid=on 2006.257.17:45:35.00:midob 2006.257.17:45:35.13/onsource/TRACKING 2006.257.17:45:35.13/wx/17.33,1014.2,97 2006.257.17:45:35.20/cable/+6.4847E-03 2006.257.17:45:36.29/va/01,08,usb,yes,30,32 2006.257.17:45:36.29/va/02,07,usb,yes,32,33 2006.257.17:45:36.29/va/03,08,usb,yes,29,31 2006.257.17:45:36.29/va/04,07,usb,yes,33,35 2006.257.17:45:36.29/va/05,04,usb,yes,30,30 2006.257.17:45:36.29/va/06,04,usb,yes,33,33 2006.257.17:45:36.29/va/07,04,usb,yes,34,34 2006.257.17:45:36.29/va/08,04,usb,yes,28,35 2006.257.17:45:36.52/valo/01,524.99,yes,locked 2006.257.17:45:36.52/valo/02,534.99,yes,locked 2006.257.17:45:36.52/valo/03,564.99,yes,locked 2006.257.17:45:36.52/valo/04,624.99,yes,locked 2006.257.17:45:36.52/valo/05,734.99,yes,locked 2006.257.17:45:36.52/valo/06,814.99,yes,locked 2006.257.17:45:36.52/valo/07,864.99,yes,locked 2006.257.17:45:36.52/valo/08,884.99,yes,locked 2006.257.17:45:37.61/vb/01,04,usb,yes,30,28 2006.257.17:45:37.61/vb/02,05,usb,yes,28,28 2006.257.17:45:37.61/vb/03,04,usb,yes,29,32 2006.257.17:45:37.61/vb/04,05,usb,yes,30,29 2006.257.17:45:37.61/vb/05,04,usb,yes,26,29 2006.257.17:45:37.61/vb/06,04,usb,yes,31,27 2006.257.17:45:37.61/vb/07,04,usb,yes,30,30 2006.257.17:45:37.61/vb/08,04,usb,yes,28,31 2006.257.17:45:37.84/vblo/01,629.99,yes,locked 2006.257.17:45:37.84/vblo/02,634.99,yes,locked 2006.257.17:45:37.84/vblo/03,649.99,yes,locked 2006.257.17:45:37.84/vblo/04,679.99,yes,locked 2006.257.17:45:37.84/vblo/05,709.99,yes,locked 2006.257.17:45:37.84/vblo/06,719.99,yes,locked 2006.257.17:45:37.84/vblo/07,734.99,yes,locked 2006.257.17:45:37.84/vblo/08,744.99,yes,locked 2006.257.17:45:37.99/vabw/8 2006.257.17:45:38.14/vbbw/8 2006.257.17:45:38.23/xfe/off,on,15.0 2006.257.17:45:38.62/ifatt/23,28,28,28 2006.257.17:45:39.07/fmout-gps/S +4.51E-07 2006.257.17:45:39.11:!2006.257.17:47:25 2006.257.17:47:25.01:data_valid=off 2006.257.17:47:25.01:"et 2006.257.17:47:25.01:!+3s 2006.257.17:47:28.02:"tape 2006.257.17:47:28.02:postob 2006.257.17:47:28.09/cable/+6.4838E-03 2006.257.17:47:28.09/wx/17.31,1014.2,97 2006.257.17:47:28.15/fmout-gps/S +4.49E-07 2006.257.17:47:28.15:scan_name=257-1750,jd0609,50 2006.257.17:47:28.15:source=0552+398,055530.81,394849.2,2000.0,cw 2006.257.17:47:29.14#flagr#flagr/antenna,new-source 2006.257.17:47:29.14:checkk5 2006.257.17:47:29.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:47:29.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:47:30.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:47:30.49/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:47:30.83/chk_obsdata//k5ts1/T2571745??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.17:47:31.16/chk_obsdata//k5ts2/T2571745??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.17:47:31.49/chk_obsdata//k5ts3/T2571745??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.17:47:31.82/chk_obsdata//k5ts4/T2571745??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.17:47:32.49/k5log//k5ts1_log_newline 2006.257.17:47:33.14/k5log//k5ts2_log_newline 2006.257.17:47:33.79/k5log//k5ts3_log_newline 2006.257.17:47:34.45/k5log//k5ts4_log_newline 2006.257.17:47:34.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:47:34.47:setupk4=1 2006.257.17:47:34.47$setupk4/echo=on 2006.257.17:47:34.47$setupk4/pcalon 2006.257.17:47:34.47$pcalon/"no phase cal control is implemented here 2006.257.17:47:34.47$setupk4/"tpicd=stop 2006.257.17:47:34.47$setupk4/"rec=synch_on 2006.257.17:47:34.47$setupk4/"rec_mode=128 2006.257.17:47:34.47$setupk4/!* 2006.257.17:47:34.47$setupk4/recpk4 2006.257.17:47:34.47$recpk4/recpatch= 2006.257.17:47:34.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:47:34.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:47:34.47$setupk4/vck44 2006.257.17:47:34.47$vck44/valo=1,524.99 2006.257.17:47:34.47#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.17:47:34.47#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.17:47:34.47#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:34.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:34.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:34.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:34.47#ibcon#enter wrdev, iclass 15, count 0 2006.257.17:47:34.47#ibcon#first serial, iclass 15, count 0 2006.257.17:47:34.47#ibcon#enter sib2, iclass 15, count 0 2006.257.17:47:34.47#ibcon#flushed, iclass 15, count 0 2006.257.17:47:34.47#ibcon#about to write, iclass 15, count 0 2006.257.17:47:34.47#ibcon#wrote, iclass 15, count 0 2006.257.17:47:34.47#ibcon#about to read 3, iclass 15, count 0 2006.257.17:47:34.49#ibcon#read 3, iclass 15, count 0 2006.257.17:47:34.49#ibcon#about to read 4, iclass 15, count 0 2006.257.17:47:34.49#ibcon#read 4, iclass 15, count 0 2006.257.17:47:34.49#ibcon#about to read 5, iclass 15, count 0 2006.257.17:47:34.49#ibcon#read 5, iclass 15, count 0 2006.257.17:47:34.49#ibcon#about to read 6, iclass 15, count 0 2006.257.17:47:34.49#ibcon#read 6, iclass 15, count 0 2006.257.17:47:34.49#ibcon#end of sib2, iclass 15, count 0 2006.257.17:47:34.49#ibcon#*mode == 0, iclass 15, count 0 2006.257.17:47:34.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.17:47:34.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:47:34.49#ibcon#*before write, iclass 15, count 0 2006.257.17:47:34.49#ibcon#enter sib2, iclass 15, count 0 2006.257.17:47:34.49#ibcon#flushed, iclass 15, count 0 2006.257.17:47:34.49#ibcon#about to write, iclass 15, count 0 2006.257.17:47:34.49#ibcon#wrote, iclass 15, count 0 2006.257.17:47:34.49#ibcon#about to read 3, iclass 15, count 0 2006.257.17:47:34.54#ibcon#read 3, iclass 15, count 0 2006.257.17:47:34.54#ibcon#about to read 4, iclass 15, count 0 2006.257.17:47:34.54#ibcon#read 4, iclass 15, count 0 2006.257.17:47:34.54#ibcon#about to read 5, iclass 15, count 0 2006.257.17:47:34.54#ibcon#read 5, iclass 15, count 0 2006.257.17:47:34.54#ibcon#about to read 6, iclass 15, count 0 2006.257.17:47:34.54#ibcon#read 6, iclass 15, count 0 2006.257.17:47:34.54#ibcon#end of sib2, iclass 15, count 0 2006.257.17:47:34.54#ibcon#*after write, iclass 15, count 0 2006.257.17:47:34.54#ibcon#*before return 0, iclass 15, count 0 2006.257.17:47:34.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:34.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:34.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.17:47:34.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.17:47:34.54$vck44/va=1,8 2006.257.17:47:34.54#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.17:47:34.54#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.17:47:34.54#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:34.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:34.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:34.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:34.54#ibcon#enter wrdev, iclass 17, count 2 2006.257.17:47:34.54#ibcon#first serial, iclass 17, count 2 2006.257.17:47:34.54#ibcon#enter sib2, iclass 17, count 2 2006.257.17:47:34.54#ibcon#flushed, iclass 17, count 2 2006.257.17:47:34.54#ibcon#about to write, iclass 17, count 2 2006.257.17:47:34.54#ibcon#wrote, iclass 17, count 2 2006.257.17:47:34.54#ibcon#about to read 3, iclass 17, count 2 2006.257.17:47:34.56#ibcon#read 3, iclass 17, count 2 2006.257.17:47:34.56#ibcon#about to read 4, iclass 17, count 2 2006.257.17:47:34.56#ibcon#read 4, iclass 17, count 2 2006.257.17:47:34.56#ibcon#about to read 5, iclass 17, count 2 2006.257.17:47:34.56#ibcon#read 5, iclass 17, count 2 2006.257.17:47:34.56#ibcon#about to read 6, iclass 17, count 2 2006.257.17:47:34.56#ibcon#read 6, iclass 17, count 2 2006.257.17:47:34.56#ibcon#end of sib2, iclass 17, count 2 2006.257.17:47:34.56#ibcon#*mode == 0, iclass 17, count 2 2006.257.17:47:34.56#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.17:47:34.56#ibcon#[25=AT01-08\r\n] 2006.257.17:47:34.56#ibcon#*before write, iclass 17, count 2 2006.257.17:47:34.56#ibcon#enter sib2, iclass 17, count 2 2006.257.17:47:34.56#ibcon#flushed, iclass 17, count 2 2006.257.17:47:34.56#ibcon#about to write, iclass 17, count 2 2006.257.17:47:34.56#ibcon#wrote, iclass 17, count 2 2006.257.17:47:34.56#ibcon#about to read 3, iclass 17, count 2 2006.257.17:47:34.59#ibcon#read 3, iclass 17, count 2 2006.257.17:47:34.59#ibcon#about to read 4, iclass 17, count 2 2006.257.17:47:34.59#ibcon#read 4, iclass 17, count 2 2006.257.17:47:34.59#ibcon#about to read 5, iclass 17, count 2 2006.257.17:47:34.59#ibcon#read 5, iclass 17, count 2 2006.257.17:47:34.59#ibcon#about to read 6, iclass 17, count 2 2006.257.17:47:34.59#ibcon#read 6, iclass 17, count 2 2006.257.17:47:34.59#ibcon#end of sib2, iclass 17, count 2 2006.257.17:47:34.59#ibcon#*after write, iclass 17, count 2 2006.257.17:47:34.59#ibcon#*before return 0, iclass 17, count 2 2006.257.17:47:34.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:34.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:34.59#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.17:47:34.59#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:34.59#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:34.71#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:34.71#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:34.71#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:47:34.71#ibcon#first serial, iclass 17, count 0 2006.257.17:47:34.71#ibcon#enter sib2, iclass 17, count 0 2006.257.17:47:34.71#ibcon#flushed, iclass 17, count 0 2006.257.17:47:34.71#ibcon#about to write, iclass 17, count 0 2006.257.17:47:34.71#ibcon#wrote, iclass 17, count 0 2006.257.17:47:34.71#ibcon#about to read 3, iclass 17, count 0 2006.257.17:47:34.73#ibcon#read 3, iclass 17, count 0 2006.257.17:47:34.73#ibcon#about to read 4, iclass 17, count 0 2006.257.17:47:34.73#ibcon#read 4, iclass 17, count 0 2006.257.17:47:34.73#ibcon#about to read 5, iclass 17, count 0 2006.257.17:47:34.73#ibcon#read 5, iclass 17, count 0 2006.257.17:47:34.73#ibcon#about to read 6, iclass 17, count 0 2006.257.17:47:34.73#ibcon#read 6, iclass 17, count 0 2006.257.17:47:34.73#ibcon#end of sib2, iclass 17, count 0 2006.257.17:47:34.73#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:47:34.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:47:34.73#ibcon#[25=USB\r\n] 2006.257.17:47:34.73#ibcon#*before write, iclass 17, count 0 2006.257.17:47:34.73#ibcon#enter sib2, iclass 17, count 0 2006.257.17:47:34.73#ibcon#flushed, iclass 17, count 0 2006.257.17:47:34.73#ibcon#about to write, iclass 17, count 0 2006.257.17:47:34.73#ibcon#wrote, iclass 17, count 0 2006.257.17:47:34.73#ibcon#about to read 3, iclass 17, count 0 2006.257.17:47:34.76#ibcon#read 3, iclass 17, count 0 2006.257.17:47:34.76#ibcon#about to read 4, iclass 17, count 0 2006.257.17:47:34.76#ibcon#read 4, iclass 17, count 0 2006.257.17:47:34.76#ibcon#about to read 5, iclass 17, count 0 2006.257.17:47:34.76#ibcon#read 5, iclass 17, count 0 2006.257.17:47:34.76#ibcon#about to read 6, iclass 17, count 0 2006.257.17:47:34.76#ibcon#read 6, iclass 17, count 0 2006.257.17:47:34.76#ibcon#end of sib2, iclass 17, count 0 2006.257.17:47:34.76#ibcon#*after write, iclass 17, count 0 2006.257.17:47:34.76#ibcon#*before return 0, iclass 17, count 0 2006.257.17:47:34.76#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:34.76#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:34.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:47:34.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:47:34.76$vck44/valo=2,534.99 2006.257.17:47:34.76#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.17:47:34.76#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.17:47:34.76#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:34.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:34.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:34.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:34.76#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:47:34.76#ibcon#first serial, iclass 19, count 0 2006.257.17:47:34.76#ibcon#enter sib2, iclass 19, count 0 2006.257.17:47:34.76#ibcon#flushed, iclass 19, count 0 2006.257.17:47:34.76#ibcon#about to write, iclass 19, count 0 2006.257.17:47:34.76#ibcon#wrote, iclass 19, count 0 2006.257.17:47:34.76#ibcon#about to read 3, iclass 19, count 0 2006.257.17:47:34.78#ibcon#read 3, iclass 19, count 0 2006.257.17:47:34.78#ibcon#about to read 4, iclass 19, count 0 2006.257.17:47:34.78#ibcon#read 4, iclass 19, count 0 2006.257.17:47:34.78#ibcon#about to read 5, iclass 19, count 0 2006.257.17:47:34.78#ibcon#read 5, iclass 19, count 0 2006.257.17:47:34.78#ibcon#about to read 6, iclass 19, count 0 2006.257.17:47:34.78#ibcon#read 6, iclass 19, count 0 2006.257.17:47:34.78#ibcon#end of sib2, iclass 19, count 0 2006.257.17:47:34.78#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:47:34.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:47:34.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:47:34.78#ibcon#*before write, iclass 19, count 0 2006.257.17:47:34.78#ibcon#enter sib2, iclass 19, count 0 2006.257.17:47:34.78#ibcon#flushed, iclass 19, count 0 2006.257.17:47:34.78#ibcon#about to write, iclass 19, count 0 2006.257.17:47:34.78#ibcon#wrote, iclass 19, count 0 2006.257.17:47:34.78#ibcon#about to read 3, iclass 19, count 0 2006.257.17:47:34.82#ibcon#read 3, iclass 19, count 0 2006.257.17:47:34.82#ibcon#about to read 4, iclass 19, count 0 2006.257.17:47:34.82#ibcon#read 4, iclass 19, count 0 2006.257.17:47:34.82#ibcon#about to read 5, iclass 19, count 0 2006.257.17:47:34.82#ibcon#read 5, iclass 19, count 0 2006.257.17:47:34.82#ibcon#about to read 6, iclass 19, count 0 2006.257.17:47:34.82#ibcon#read 6, iclass 19, count 0 2006.257.17:47:34.82#ibcon#end of sib2, iclass 19, count 0 2006.257.17:47:34.82#ibcon#*after write, iclass 19, count 0 2006.257.17:47:34.82#ibcon#*before return 0, iclass 19, count 0 2006.257.17:47:34.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:34.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:34.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:47:34.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:47:34.82$vck44/va=2,7 2006.257.17:47:34.82#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.17:47:34.82#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.17:47:34.82#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:34.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:34.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:34.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:34.88#ibcon#enter wrdev, iclass 21, count 2 2006.257.17:47:34.88#ibcon#first serial, iclass 21, count 2 2006.257.17:47:34.88#ibcon#enter sib2, iclass 21, count 2 2006.257.17:47:34.88#ibcon#flushed, iclass 21, count 2 2006.257.17:47:34.88#ibcon#about to write, iclass 21, count 2 2006.257.17:47:34.88#ibcon#wrote, iclass 21, count 2 2006.257.17:47:34.88#ibcon#about to read 3, iclass 21, count 2 2006.257.17:47:34.90#ibcon#read 3, iclass 21, count 2 2006.257.17:47:34.90#ibcon#about to read 4, iclass 21, count 2 2006.257.17:47:34.90#ibcon#read 4, iclass 21, count 2 2006.257.17:47:34.90#ibcon#about to read 5, iclass 21, count 2 2006.257.17:47:34.90#ibcon#read 5, iclass 21, count 2 2006.257.17:47:34.90#ibcon#about to read 6, iclass 21, count 2 2006.257.17:47:34.90#ibcon#read 6, iclass 21, count 2 2006.257.17:47:34.90#ibcon#end of sib2, iclass 21, count 2 2006.257.17:47:34.90#ibcon#*mode == 0, iclass 21, count 2 2006.257.17:47:34.90#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.17:47:34.90#ibcon#[25=AT02-07\r\n] 2006.257.17:47:34.90#ibcon#*before write, iclass 21, count 2 2006.257.17:47:34.90#ibcon#enter sib2, iclass 21, count 2 2006.257.17:47:34.90#ibcon#flushed, iclass 21, count 2 2006.257.17:47:34.90#ibcon#about to write, iclass 21, count 2 2006.257.17:47:34.90#ibcon#wrote, iclass 21, count 2 2006.257.17:47:34.90#ibcon#about to read 3, iclass 21, count 2 2006.257.17:47:34.93#ibcon#read 3, iclass 21, count 2 2006.257.17:47:34.93#ibcon#about to read 4, iclass 21, count 2 2006.257.17:47:34.93#ibcon#read 4, iclass 21, count 2 2006.257.17:47:34.93#ibcon#about to read 5, iclass 21, count 2 2006.257.17:47:34.93#ibcon#read 5, iclass 21, count 2 2006.257.17:47:34.93#ibcon#about to read 6, iclass 21, count 2 2006.257.17:47:34.93#ibcon#read 6, iclass 21, count 2 2006.257.17:47:34.93#ibcon#end of sib2, iclass 21, count 2 2006.257.17:47:34.93#ibcon#*after write, iclass 21, count 2 2006.257.17:47:34.93#ibcon#*before return 0, iclass 21, count 2 2006.257.17:47:34.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:34.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:34.93#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.17:47:34.93#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:34.93#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:35.05#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:35.05#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:35.05#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:47:35.05#ibcon#first serial, iclass 21, count 0 2006.257.17:47:35.05#ibcon#enter sib2, iclass 21, count 0 2006.257.17:47:35.05#ibcon#flushed, iclass 21, count 0 2006.257.17:47:35.05#ibcon#about to write, iclass 21, count 0 2006.257.17:47:35.05#ibcon#wrote, iclass 21, count 0 2006.257.17:47:35.05#ibcon#about to read 3, iclass 21, count 0 2006.257.17:47:35.07#ibcon#read 3, iclass 21, count 0 2006.257.17:47:35.07#ibcon#about to read 4, iclass 21, count 0 2006.257.17:47:35.07#ibcon#read 4, iclass 21, count 0 2006.257.17:47:35.07#ibcon#about to read 5, iclass 21, count 0 2006.257.17:47:35.07#ibcon#read 5, iclass 21, count 0 2006.257.17:47:35.07#ibcon#about to read 6, iclass 21, count 0 2006.257.17:47:35.07#ibcon#read 6, iclass 21, count 0 2006.257.17:47:35.07#ibcon#end of sib2, iclass 21, count 0 2006.257.17:47:35.07#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:47:35.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:47:35.07#ibcon#[25=USB\r\n] 2006.257.17:47:35.07#ibcon#*before write, iclass 21, count 0 2006.257.17:47:35.07#ibcon#enter sib2, iclass 21, count 0 2006.257.17:47:35.07#ibcon#flushed, iclass 21, count 0 2006.257.17:47:35.07#ibcon#about to write, iclass 21, count 0 2006.257.17:47:35.07#ibcon#wrote, iclass 21, count 0 2006.257.17:47:35.07#ibcon#about to read 3, iclass 21, count 0 2006.257.17:47:35.10#ibcon#read 3, iclass 21, count 0 2006.257.17:47:35.10#ibcon#about to read 4, iclass 21, count 0 2006.257.17:47:35.10#ibcon#read 4, iclass 21, count 0 2006.257.17:47:35.10#ibcon#about to read 5, iclass 21, count 0 2006.257.17:47:35.10#ibcon#read 5, iclass 21, count 0 2006.257.17:47:35.10#ibcon#about to read 6, iclass 21, count 0 2006.257.17:47:35.10#ibcon#read 6, iclass 21, count 0 2006.257.17:47:35.10#ibcon#end of sib2, iclass 21, count 0 2006.257.17:47:35.10#ibcon#*after write, iclass 21, count 0 2006.257.17:47:35.10#ibcon#*before return 0, iclass 21, count 0 2006.257.17:47:35.10#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:35.10#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:35.10#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:47:35.10#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:47:35.10$vck44/valo=3,564.99 2006.257.17:47:35.10#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.17:47:35.10#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.17:47:35.10#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:35.10#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:35.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:35.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:35.10#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:47:35.10#ibcon#first serial, iclass 23, count 0 2006.257.17:47:35.10#ibcon#enter sib2, iclass 23, count 0 2006.257.17:47:35.10#ibcon#flushed, iclass 23, count 0 2006.257.17:47:35.10#ibcon#about to write, iclass 23, count 0 2006.257.17:47:35.10#ibcon#wrote, iclass 23, count 0 2006.257.17:47:35.10#ibcon#about to read 3, iclass 23, count 0 2006.257.17:47:35.12#ibcon#read 3, iclass 23, count 0 2006.257.17:47:35.12#ibcon#about to read 4, iclass 23, count 0 2006.257.17:47:35.12#ibcon#read 4, iclass 23, count 0 2006.257.17:47:35.12#ibcon#about to read 5, iclass 23, count 0 2006.257.17:47:35.12#ibcon#read 5, iclass 23, count 0 2006.257.17:47:35.12#ibcon#about to read 6, iclass 23, count 0 2006.257.17:47:35.12#ibcon#read 6, iclass 23, count 0 2006.257.17:47:35.12#ibcon#end of sib2, iclass 23, count 0 2006.257.17:47:35.12#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:47:35.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:47:35.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:47:35.12#ibcon#*before write, iclass 23, count 0 2006.257.17:47:35.12#ibcon#enter sib2, iclass 23, count 0 2006.257.17:47:35.12#ibcon#flushed, iclass 23, count 0 2006.257.17:47:35.12#ibcon#about to write, iclass 23, count 0 2006.257.17:47:35.12#ibcon#wrote, iclass 23, count 0 2006.257.17:47:35.12#ibcon#about to read 3, iclass 23, count 0 2006.257.17:47:35.16#ibcon#read 3, iclass 23, count 0 2006.257.17:47:35.16#ibcon#about to read 4, iclass 23, count 0 2006.257.17:47:35.16#ibcon#read 4, iclass 23, count 0 2006.257.17:47:35.16#ibcon#about to read 5, iclass 23, count 0 2006.257.17:47:35.16#ibcon#read 5, iclass 23, count 0 2006.257.17:47:35.16#ibcon#about to read 6, iclass 23, count 0 2006.257.17:47:35.16#ibcon#read 6, iclass 23, count 0 2006.257.17:47:35.16#ibcon#end of sib2, iclass 23, count 0 2006.257.17:47:35.16#ibcon#*after write, iclass 23, count 0 2006.257.17:47:35.16#ibcon#*before return 0, iclass 23, count 0 2006.257.17:47:35.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:35.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:35.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:47:35.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:47:35.16$vck44/va=3,8 2006.257.17:47:35.16#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.17:47:35.16#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.17:47:35.16#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:35.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:35.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:35.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:35.22#ibcon#enter wrdev, iclass 25, count 2 2006.257.17:47:35.22#ibcon#first serial, iclass 25, count 2 2006.257.17:47:35.22#ibcon#enter sib2, iclass 25, count 2 2006.257.17:47:35.22#ibcon#flushed, iclass 25, count 2 2006.257.17:47:35.22#ibcon#about to write, iclass 25, count 2 2006.257.17:47:35.22#ibcon#wrote, iclass 25, count 2 2006.257.17:47:35.22#ibcon#about to read 3, iclass 25, count 2 2006.257.17:47:35.24#ibcon#read 3, iclass 25, count 2 2006.257.17:47:35.24#ibcon#about to read 4, iclass 25, count 2 2006.257.17:47:35.24#ibcon#read 4, iclass 25, count 2 2006.257.17:47:35.24#ibcon#about to read 5, iclass 25, count 2 2006.257.17:47:35.24#ibcon#read 5, iclass 25, count 2 2006.257.17:47:35.24#ibcon#about to read 6, iclass 25, count 2 2006.257.17:47:35.24#ibcon#read 6, iclass 25, count 2 2006.257.17:47:35.24#ibcon#end of sib2, iclass 25, count 2 2006.257.17:47:35.24#ibcon#*mode == 0, iclass 25, count 2 2006.257.17:47:35.24#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.17:47:35.24#ibcon#[25=AT03-08\r\n] 2006.257.17:47:35.24#ibcon#*before write, iclass 25, count 2 2006.257.17:47:35.24#ibcon#enter sib2, iclass 25, count 2 2006.257.17:47:35.24#ibcon#flushed, iclass 25, count 2 2006.257.17:47:35.24#ibcon#about to write, iclass 25, count 2 2006.257.17:47:35.24#ibcon#wrote, iclass 25, count 2 2006.257.17:47:35.24#ibcon#about to read 3, iclass 25, count 2 2006.257.17:47:35.27#ibcon#read 3, iclass 25, count 2 2006.257.17:47:35.27#ibcon#about to read 4, iclass 25, count 2 2006.257.17:47:35.27#ibcon#read 4, iclass 25, count 2 2006.257.17:47:35.27#ibcon#about to read 5, iclass 25, count 2 2006.257.17:47:35.27#ibcon#read 5, iclass 25, count 2 2006.257.17:47:35.27#ibcon#about to read 6, iclass 25, count 2 2006.257.17:47:35.27#ibcon#read 6, iclass 25, count 2 2006.257.17:47:35.27#ibcon#end of sib2, iclass 25, count 2 2006.257.17:47:35.27#ibcon#*after write, iclass 25, count 2 2006.257.17:47:35.27#ibcon#*before return 0, iclass 25, count 2 2006.257.17:47:35.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:35.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:35.27#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.17:47:35.27#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:35.27#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:35.39#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:35.39#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:35.39#ibcon#enter wrdev, iclass 25, count 0 2006.257.17:47:35.39#ibcon#first serial, iclass 25, count 0 2006.257.17:47:35.39#ibcon#enter sib2, iclass 25, count 0 2006.257.17:47:35.39#ibcon#flushed, iclass 25, count 0 2006.257.17:47:35.39#ibcon#about to write, iclass 25, count 0 2006.257.17:47:35.39#ibcon#wrote, iclass 25, count 0 2006.257.17:47:35.39#ibcon#about to read 3, iclass 25, count 0 2006.257.17:47:35.41#ibcon#read 3, iclass 25, count 0 2006.257.17:47:35.41#ibcon#about to read 4, iclass 25, count 0 2006.257.17:47:35.41#ibcon#read 4, iclass 25, count 0 2006.257.17:47:35.41#ibcon#about to read 5, iclass 25, count 0 2006.257.17:47:35.41#ibcon#read 5, iclass 25, count 0 2006.257.17:47:35.41#ibcon#about to read 6, iclass 25, count 0 2006.257.17:47:35.41#ibcon#read 6, iclass 25, count 0 2006.257.17:47:35.41#ibcon#end of sib2, iclass 25, count 0 2006.257.17:47:35.41#ibcon#*mode == 0, iclass 25, count 0 2006.257.17:47:35.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.17:47:35.41#ibcon#[25=USB\r\n] 2006.257.17:47:35.41#ibcon#*before write, iclass 25, count 0 2006.257.17:47:35.41#ibcon#enter sib2, iclass 25, count 0 2006.257.17:47:35.41#ibcon#flushed, iclass 25, count 0 2006.257.17:47:35.41#ibcon#about to write, iclass 25, count 0 2006.257.17:47:35.41#ibcon#wrote, iclass 25, count 0 2006.257.17:47:35.41#ibcon#about to read 3, iclass 25, count 0 2006.257.17:47:35.44#ibcon#read 3, iclass 25, count 0 2006.257.17:47:35.44#ibcon#about to read 4, iclass 25, count 0 2006.257.17:47:35.44#ibcon#read 4, iclass 25, count 0 2006.257.17:47:35.44#ibcon#about to read 5, iclass 25, count 0 2006.257.17:47:35.44#ibcon#read 5, iclass 25, count 0 2006.257.17:47:35.44#ibcon#about to read 6, iclass 25, count 0 2006.257.17:47:35.44#ibcon#read 6, iclass 25, count 0 2006.257.17:47:35.44#ibcon#end of sib2, iclass 25, count 0 2006.257.17:47:35.44#ibcon#*after write, iclass 25, count 0 2006.257.17:47:35.44#ibcon#*before return 0, iclass 25, count 0 2006.257.17:47:35.44#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:35.44#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:35.44#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.17:47:35.44#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.17:47:35.44$vck44/valo=4,624.99 2006.257.17:47:35.44#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.17:47:35.44#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.17:47:35.44#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:35.44#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:35.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:35.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:35.44#ibcon#enter wrdev, iclass 27, count 0 2006.257.17:47:35.44#ibcon#first serial, iclass 27, count 0 2006.257.17:47:35.44#ibcon#enter sib2, iclass 27, count 0 2006.257.17:47:35.44#ibcon#flushed, iclass 27, count 0 2006.257.17:47:35.44#ibcon#about to write, iclass 27, count 0 2006.257.17:47:35.44#ibcon#wrote, iclass 27, count 0 2006.257.17:47:35.44#ibcon#about to read 3, iclass 27, count 0 2006.257.17:47:35.46#ibcon#read 3, iclass 27, count 0 2006.257.17:47:35.46#ibcon#about to read 4, iclass 27, count 0 2006.257.17:47:35.46#ibcon#read 4, iclass 27, count 0 2006.257.17:47:35.46#ibcon#about to read 5, iclass 27, count 0 2006.257.17:47:35.46#ibcon#read 5, iclass 27, count 0 2006.257.17:47:35.46#ibcon#about to read 6, iclass 27, count 0 2006.257.17:47:35.46#ibcon#read 6, iclass 27, count 0 2006.257.17:47:35.46#ibcon#end of sib2, iclass 27, count 0 2006.257.17:47:35.46#ibcon#*mode == 0, iclass 27, count 0 2006.257.17:47:35.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.17:47:35.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:47:35.46#ibcon#*before write, iclass 27, count 0 2006.257.17:47:35.46#ibcon#enter sib2, iclass 27, count 0 2006.257.17:47:35.46#ibcon#flushed, iclass 27, count 0 2006.257.17:47:35.46#ibcon#about to write, iclass 27, count 0 2006.257.17:47:35.46#ibcon#wrote, iclass 27, count 0 2006.257.17:47:35.46#ibcon#about to read 3, iclass 27, count 0 2006.257.17:47:35.50#ibcon#read 3, iclass 27, count 0 2006.257.17:47:35.50#ibcon#about to read 4, iclass 27, count 0 2006.257.17:47:35.50#ibcon#read 4, iclass 27, count 0 2006.257.17:47:35.50#ibcon#about to read 5, iclass 27, count 0 2006.257.17:47:35.50#ibcon#read 5, iclass 27, count 0 2006.257.17:47:35.50#ibcon#about to read 6, iclass 27, count 0 2006.257.17:47:35.50#ibcon#read 6, iclass 27, count 0 2006.257.17:47:35.50#ibcon#end of sib2, iclass 27, count 0 2006.257.17:47:35.50#ibcon#*after write, iclass 27, count 0 2006.257.17:47:35.50#ibcon#*before return 0, iclass 27, count 0 2006.257.17:47:35.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:35.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:35.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.17:47:35.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.17:47:35.50$vck44/va=4,7 2006.257.17:47:35.50#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.17:47:35.50#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.17:47:35.50#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:35.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:35.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:35.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:35.56#ibcon#enter wrdev, iclass 29, count 2 2006.257.17:47:35.56#ibcon#first serial, iclass 29, count 2 2006.257.17:47:35.56#ibcon#enter sib2, iclass 29, count 2 2006.257.17:47:35.56#ibcon#flushed, iclass 29, count 2 2006.257.17:47:35.56#ibcon#about to write, iclass 29, count 2 2006.257.17:47:35.56#ibcon#wrote, iclass 29, count 2 2006.257.17:47:35.56#ibcon#about to read 3, iclass 29, count 2 2006.257.17:47:35.58#ibcon#read 3, iclass 29, count 2 2006.257.17:47:35.58#ibcon#about to read 4, iclass 29, count 2 2006.257.17:47:35.58#ibcon#read 4, iclass 29, count 2 2006.257.17:47:35.58#ibcon#about to read 5, iclass 29, count 2 2006.257.17:47:35.58#ibcon#read 5, iclass 29, count 2 2006.257.17:47:35.58#ibcon#about to read 6, iclass 29, count 2 2006.257.17:47:35.58#ibcon#read 6, iclass 29, count 2 2006.257.17:47:35.58#ibcon#end of sib2, iclass 29, count 2 2006.257.17:47:35.58#ibcon#*mode == 0, iclass 29, count 2 2006.257.17:47:35.58#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.17:47:35.58#ibcon#[25=AT04-07\r\n] 2006.257.17:47:35.58#ibcon#*before write, iclass 29, count 2 2006.257.17:47:35.58#ibcon#enter sib2, iclass 29, count 2 2006.257.17:47:35.58#ibcon#flushed, iclass 29, count 2 2006.257.17:47:35.58#ibcon#about to write, iclass 29, count 2 2006.257.17:47:35.58#ibcon#wrote, iclass 29, count 2 2006.257.17:47:35.58#ibcon#about to read 3, iclass 29, count 2 2006.257.17:47:35.61#ibcon#read 3, iclass 29, count 2 2006.257.17:47:35.61#ibcon#about to read 4, iclass 29, count 2 2006.257.17:47:35.61#ibcon#read 4, iclass 29, count 2 2006.257.17:47:35.61#ibcon#about to read 5, iclass 29, count 2 2006.257.17:47:35.61#ibcon#read 5, iclass 29, count 2 2006.257.17:47:35.61#ibcon#about to read 6, iclass 29, count 2 2006.257.17:47:35.61#ibcon#read 6, iclass 29, count 2 2006.257.17:47:35.61#ibcon#end of sib2, iclass 29, count 2 2006.257.17:47:35.61#ibcon#*after write, iclass 29, count 2 2006.257.17:47:35.61#ibcon#*before return 0, iclass 29, count 2 2006.257.17:47:35.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:35.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:35.61#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.17:47:35.61#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:35.61#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:35.73#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:35.73#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:35.73#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:47:35.73#ibcon#first serial, iclass 29, count 0 2006.257.17:47:35.73#ibcon#enter sib2, iclass 29, count 0 2006.257.17:47:35.73#ibcon#flushed, iclass 29, count 0 2006.257.17:47:35.73#ibcon#about to write, iclass 29, count 0 2006.257.17:47:35.73#ibcon#wrote, iclass 29, count 0 2006.257.17:47:35.73#ibcon#about to read 3, iclass 29, count 0 2006.257.17:47:35.75#ibcon#read 3, iclass 29, count 0 2006.257.17:47:35.75#ibcon#about to read 4, iclass 29, count 0 2006.257.17:47:35.75#ibcon#read 4, iclass 29, count 0 2006.257.17:47:35.75#ibcon#about to read 5, iclass 29, count 0 2006.257.17:47:35.75#ibcon#read 5, iclass 29, count 0 2006.257.17:47:35.75#ibcon#about to read 6, iclass 29, count 0 2006.257.17:47:35.75#ibcon#read 6, iclass 29, count 0 2006.257.17:47:35.75#ibcon#end of sib2, iclass 29, count 0 2006.257.17:47:35.75#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:47:35.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:47:35.75#ibcon#[25=USB\r\n] 2006.257.17:47:35.75#ibcon#*before write, iclass 29, count 0 2006.257.17:47:35.75#ibcon#enter sib2, iclass 29, count 0 2006.257.17:47:35.75#ibcon#flushed, iclass 29, count 0 2006.257.17:47:35.75#ibcon#about to write, iclass 29, count 0 2006.257.17:47:35.75#ibcon#wrote, iclass 29, count 0 2006.257.17:47:35.75#ibcon#about to read 3, iclass 29, count 0 2006.257.17:47:35.78#ibcon#read 3, iclass 29, count 0 2006.257.17:47:35.78#ibcon#about to read 4, iclass 29, count 0 2006.257.17:47:35.78#ibcon#read 4, iclass 29, count 0 2006.257.17:47:35.78#ibcon#about to read 5, iclass 29, count 0 2006.257.17:47:35.78#ibcon#read 5, iclass 29, count 0 2006.257.17:47:35.78#ibcon#about to read 6, iclass 29, count 0 2006.257.17:47:35.78#ibcon#read 6, iclass 29, count 0 2006.257.17:47:35.78#ibcon#end of sib2, iclass 29, count 0 2006.257.17:47:35.78#ibcon#*after write, iclass 29, count 0 2006.257.17:47:35.78#ibcon#*before return 0, iclass 29, count 0 2006.257.17:47:35.78#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:35.78#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:35.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:47:35.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:47:35.78$vck44/valo=5,734.99 2006.257.17:47:35.78#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.17:47:35.78#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.17:47:35.78#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:35.78#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:35.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:35.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:35.78#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:47:35.78#ibcon#first serial, iclass 31, count 0 2006.257.17:47:35.78#ibcon#enter sib2, iclass 31, count 0 2006.257.17:47:35.78#ibcon#flushed, iclass 31, count 0 2006.257.17:47:35.78#ibcon#about to write, iclass 31, count 0 2006.257.17:47:35.78#ibcon#wrote, iclass 31, count 0 2006.257.17:47:35.78#ibcon#about to read 3, iclass 31, count 0 2006.257.17:47:35.80#ibcon#read 3, iclass 31, count 0 2006.257.17:47:35.80#ibcon#about to read 4, iclass 31, count 0 2006.257.17:47:35.80#ibcon#read 4, iclass 31, count 0 2006.257.17:47:35.80#ibcon#about to read 5, iclass 31, count 0 2006.257.17:47:35.80#ibcon#read 5, iclass 31, count 0 2006.257.17:47:35.80#ibcon#about to read 6, iclass 31, count 0 2006.257.17:47:35.80#ibcon#read 6, iclass 31, count 0 2006.257.17:47:35.80#ibcon#end of sib2, iclass 31, count 0 2006.257.17:47:35.80#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:47:35.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:47:35.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:47:35.80#ibcon#*before write, iclass 31, count 0 2006.257.17:47:35.80#ibcon#enter sib2, iclass 31, count 0 2006.257.17:47:35.80#ibcon#flushed, iclass 31, count 0 2006.257.17:47:35.80#ibcon#about to write, iclass 31, count 0 2006.257.17:47:35.80#ibcon#wrote, iclass 31, count 0 2006.257.17:47:35.80#ibcon#about to read 3, iclass 31, count 0 2006.257.17:47:35.84#ibcon#read 3, iclass 31, count 0 2006.257.17:47:35.84#ibcon#about to read 4, iclass 31, count 0 2006.257.17:47:35.84#ibcon#read 4, iclass 31, count 0 2006.257.17:47:35.84#ibcon#about to read 5, iclass 31, count 0 2006.257.17:47:35.84#ibcon#read 5, iclass 31, count 0 2006.257.17:47:35.84#ibcon#about to read 6, iclass 31, count 0 2006.257.17:47:35.84#ibcon#read 6, iclass 31, count 0 2006.257.17:47:35.84#ibcon#end of sib2, iclass 31, count 0 2006.257.17:47:35.84#ibcon#*after write, iclass 31, count 0 2006.257.17:47:35.84#ibcon#*before return 0, iclass 31, count 0 2006.257.17:47:35.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:35.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:35.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:47:35.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:47:35.84$vck44/va=5,4 2006.257.17:47:35.84#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.17:47:35.84#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.17:47:35.84#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:35.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:35.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:35.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:35.90#ibcon#enter wrdev, iclass 33, count 2 2006.257.17:47:35.90#ibcon#first serial, iclass 33, count 2 2006.257.17:47:35.90#ibcon#enter sib2, iclass 33, count 2 2006.257.17:47:35.90#ibcon#flushed, iclass 33, count 2 2006.257.17:47:35.90#ibcon#about to write, iclass 33, count 2 2006.257.17:47:35.90#ibcon#wrote, iclass 33, count 2 2006.257.17:47:35.90#ibcon#about to read 3, iclass 33, count 2 2006.257.17:47:35.92#ibcon#read 3, iclass 33, count 2 2006.257.17:47:35.92#ibcon#about to read 4, iclass 33, count 2 2006.257.17:47:35.92#ibcon#read 4, iclass 33, count 2 2006.257.17:47:35.92#ibcon#about to read 5, iclass 33, count 2 2006.257.17:47:35.92#ibcon#read 5, iclass 33, count 2 2006.257.17:47:35.92#ibcon#about to read 6, iclass 33, count 2 2006.257.17:47:35.92#ibcon#read 6, iclass 33, count 2 2006.257.17:47:35.92#ibcon#end of sib2, iclass 33, count 2 2006.257.17:47:35.92#ibcon#*mode == 0, iclass 33, count 2 2006.257.17:47:35.92#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.17:47:35.92#ibcon#[25=AT05-04\r\n] 2006.257.17:47:35.92#ibcon#*before write, iclass 33, count 2 2006.257.17:47:35.92#ibcon#enter sib2, iclass 33, count 2 2006.257.17:47:35.92#ibcon#flushed, iclass 33, count 2 2006.257.17:47:35.92#ibcon#about to write, iclass 33, count 2 2006.257.17:47:35.92#ibcon#wrote, iclass 33, count 2 2006.257.17:47:35.92#ibcon#about to read 3, iclass 33, count 2 2006.257.17:47:35.95#ibcon#read 3, iclass 33, count 2 2006.257.17:47:35.95#ibcon#about to read 4, iclass 33, count 2 2006.257.17:47:35.95#ibcon#read 4, iclass 33, count 2 2006.257.17:47:35.95#ibcon#about to read 5, iclass 33, count 2 2006.257.17:47:35.95#ibcon#read 5, iclass 33, count 2 2006.257.17:47:35.95#ibcon#about to read 6, iclass 33, count 2 2006.257.17:47:35.95#ibcon#read 6, iclass 33, count 2 2006.257.17:47:35.95#ibcon#end of sib2, iclass 33, count 2 2006.257.17:47:35.95#ibcon#*after write, iclass 33, count 2 2006.257.17:47:35.95#ibcon#*before return 0, iclass 33, count 2 2006.257.17:47:35.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:35.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:35.95#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.17:47:35.95#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:35.95#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:36.07#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:36.07#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:36.07#ibcon#enter wrdev, iclass 33, count 0 2006.257.17:47:36.07#ibcon#first serial, iclass 33, count 0 2006.257.17:47:36.07#ibcon#enter sib2, iclass 33, count 0 2006.257.17:47:36.07#ibcon#flushed, iclass 33, count 0 2006.257.17:47:36.07#ibcon#about to write, iclass 33, count 0 2006.257.17:47:36.07#ibcon#wrote, iclass 33, count 0 2006.257.17:47:36.07#ibcon#about to read 3, iclass 33, count 0 2006.257.17:47:36.09#ibcon#read 3, iclass 33, count 0 2006.257.17:47:36.09#ibcon#about to read 4, iclass 33, count 0 2006.257.17:47:36.09#ibcon#read 4, iclass 33, count 0 2006.257.17:47:36.09#ibcon#about to read 5, iclass 33, count 0 2006.257.17:47:36.09#ibcon#read 5, iclass 33, count 0 2006.257.17:47:36.09#ibcon#about to read 6, iclass 33, count 0 2006.257.17:47:36.09#ibcon#read 6, iclass 33, count 0 2006.257.17:47:36.09#ibcon#end of sib2, iclass 33, count 0 2006.257.17:47:36.09#ibcon#*mode == 0, iclass 33, count 0 2006.257.17:47:36.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.17:47:36.09#ibcon#[25=USB\r\n] 2006.257.17:47:36.09#ibcon#*before write, iclass 33, count 0 2006.257.17:47:36.09#ibcon#enter sib2, iclass 33, count 0 2006.257.17:47:36.09#ibcon#flushed, iclass 33, count 0 2006.257.17:47:36.09#ibcon#about to write, iclass 33, count 0 2006.257.17:47:36.09#ibcon#wrote, iclass 33, count 0 2006.257.17:47:36.09#ibcon#about to read 3, iclass 33, count 0 2006.257.17:47:36.12#ibcon#read 3, iclass 33, count 0 2006.257.17:47:36.12#ibcon#about to read 4, iclass 33, count 0 2006.257.17:47:36.12#ibcon#read 4, iclass 33, count 0 2006.257.17:47:36.12#ibcon#about to read 5, iclass 33, count 0 2006.257.17:47:36.12#ibcon#read 5, iclass 33, count 0 2006.257.17:47:36.12#ibcon#about to read 6, iclass 33, count 0 2006.257.17:47:36.12#ibcon#read 6, iclass 33, count 0 2006.257.17:47:36.12#ibcon#end of sib2, iclass 33, count 0 2006.257.17:47:36.12#ibcon#*after write, iclass 33, count 0 2006.257.17:47:36.12#ibcon#*before return 0, iclass 33, count 0 2006.257.17:47:36.12#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:36.12#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:36.12#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.17:47:36.12#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.17:47:36.12$vck44/valo=6,814.99 2006.257.17:47:36.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.17:47:36.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.17:47:36.12#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:36.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:36.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:36.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:36.12#ibcon#enter wrdev, iclass 35, count 0 2006.257.17:47:36.12#ibcon#first serial, iclass 35, count 0 2006.257.17:47:36.12#ibcon#enter sib2, iclass 35, count 0 2006.257.17:47:36.12#ibcon#flushed, iclass 35, count 0 2006.257.17:47:36.12#ibcon#about to write, iclass 35, count 0 2006.257.17:47:36.12#ibcon#wrote, iclass 35, count 0 2006.257.17:47:36.12#ibcon#about to read 3, iclass 35, count 0 2006.257.17:47:36.14#ibcon#read 3, iclass 35, count 0 2006.257.17:47:36.14#ibcon#about to read 4, iclass 35, count 0 2006.257.17:47:36.14#ibcon#read 4, iclass 35, count 0 2006.257.17:47:36.14#ibcon#about to read 5, iclass 35, count 0 2006.257.17:47:36.14#ibcon#read 5, iclass 35, count 0 2006.257.17:47:36.14#ibcon#about to read 6, iclass 35, count 0 2006.257.17:47:36.14#ibcon#read 6, iclass 35, count 0 2006.257.17:47:36.14#ibcon#end of sib2, iclass 35, count 0 2006.257.17:47:36.14#ibcon#*mode == 0, iclass 35, count 0 2006.257.17:47:36.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.17:47:36.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:47:36.14#ibcon#*before write, iclass 35, count 0 2006.257.17:47:36.14#ibcon#enter sib2, iclass 35, count 0 2006.257.17:47:36.14#ibcon#flushed, iclass 35, count 0 2006.257.17:47:36.14#ibcon#about to write, iclass 35, count 0 2006.257.17:47:36.14#ibcon#wrote, iclass 35, count 0 2006.257.17:47:36.14#ibcon#about to read 3, iclass 35, count 0 2006.257.17:47:36.18#ibcon#read 3, iclass 35, count 0 2006.257.17:47:36.18#ibcon#about to read 4, iclass 35, count 0 2006.257.17:47:36.18#ibcon#read 4, iclass 35, count 0 2006.257.17:47:36.18#ibcon#about to read 5, iclass 35, count 0 2006.257.17:47:36.18#ibcon#read 5, iclass 35, count 0 2006.257.17:47:36.18#ibcon#about to read 6, iclass 35, count 0 2006.257.17:47:36.18#ibcon#read 6, iclass 35, count 0 2006.257.17:47:36.18#ibcon#end of sib2, iclass 35, count 0 2006.257.17:47:36.18#ibcon#*after write, iclass 35, count 0 2006.257.17:47:36.18#ibcon#*before return 0, iclass 35, count 0 2006.257.17:47:36.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:36.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:36.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.17:47:36.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.17:47:36.18$vck44/va=6,4 2006.257.17:47:36.18#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.17:47:36.18#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.17:47:36.18#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:36.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:36.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:36.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:36.24#ibcon#enter wrdev, iclass 37, count 2 2006.257.17:47:36.24#ibcon#first serial, iclass 37, count 2 2006.257.17:47:36.24#ibcon#enter sib2, iclass 37, count 2 2006.257.17:47:36.24#ibcon#flushed, iclass 37, count 2 2006.257.17:47:36.24#ibcon#about to write, iclass 37, count 2 2006.257.17:47:36.24#ibcon#wrote, iclass 37, count 2 2006.257.17:47:36.24#ibcon#about to read 3, iclass 37, count 2 2006.257.17:47:36.26#ibcon#read 3, iclass 37, count 2 2006.257.17:47:36.26#ibcon#about to read 4, iclass 37, count 2 2006.257.17:47:36.26#ibcon#read 4, iclass 37, count 2 2006.257.17:47:36.26#ibcon#about to read 5, iclass 37, count 2 2006.257.17:47:36.26#ibcon#read 5, iclass 37, count 2 2006.257.17:47:36.26#ibcon#about to read 6, iclass 37, count 2 2006.257.17:47:36.26#ibcon#read 6, iclass 37, count 2 2006.257.17:47:36.26#ibcon#end of sib2, iclass 37, count 2 2006.257.17:47:36.26#ibcon#*mode == 0, iclass 37, count 2 2006.257.17:47:36.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.17:47:36.26#ibcon#[25=AT06-04\r\n] 2006.257.17:47:36.26#ibcon#*before write, iclass 37, count 2 2006.257.17:47:36.26#ibcon#enter sib2, iclass 37, count 2 2006.257.17:47:36.26#ibcon#flushed, iclass 37, count 2 2006.257.17:47:36.26#ibcon#about to write, iclass 37, count 2 2006.257.17:47:36.26#ibcon#wrote, iclass 37, count 2 2006.257.17:47:36.26#ibcon#about to read 3, iclass 37, count 2 2006.257.17:47:36.29#ibcon#read 3, iclass 37, count 2 2006.257.17:47:36.29#ibcon#about to read 4, iclass 37, count 2 2006.257.17:47:36.29#ibcon#read 4, iclass 37, count 2 2006.257.17:47:36.29#ibcon#about to read 5, iclass 37, count 2 2006.257.17:47:36.29#ibcon#read 5, iclass 37, count 2 2006.257.17:47:36.29#ibcon#about to read 6, iclass 37, count 2 2006.257.17:47:36.29#ibcon#read 6, iclass 37, count 2 2006.257.17:47:36.29#ibcon#end of sib2, iclass 37, count 2 2006.257.17:47:36.29#ibcon#*after write, iclass 37, count 2 2006.257.17:47:36.29#ibcon#*before return 0, iclass 37, count 2 2006.257.17:47:36.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:36.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:36.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.17:47:36.29#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:36.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:36.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:36.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:36.41#ibcon#enter wrdev, iclass 37, count 0 2006.257.17:47:36.41#ibcon#first serial, iclass 37, count 0 2006.257.17:47:36.41#ibcon#enter sib2, iclass 37, count 0 2006.257.17:47:36.41#ibcon#flushed, iclass 37, count 0 2006.257.17:47:36.41#ibcon#about to write, iclass 37, count 0 2006.257.17:47:36.41#ibcon#wrote, iclass 37, count 0 2006.257.17:47:36.41#ibcon#about to read 3, iclass 37, count 0 2006.257.17:47:36.43#ibcon#read 3, iclass 37, count 0 2006.257.17:47:36.43#ibcon#about to read 4, iclass 37, count 0 2006.257.17:47:36.43#ibcon#read 4, iclass 37, count 0 2006.257.17:47:36.43#ibcon#about to read 5, iclass 37, count 0 2006.257.17:47:36.43#ibcon#read 5, iclass 37, count 0 2006.257.17:47:36.43#ibcon#about to read 6, iclass 37, count 0 2006.257.17:47:36.43#ibcon#read 6, iclass 37, count 0 2006.257.17:47:36.43#ibcon#end of sib2, iclass 37, count 0 2006.257.17:47:36.43#ibcon#*mode == 0, iclass 37, count 0 2006.257.17:47:36.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.17:47:36.43#ibcon#[25=USB\r\n] 2006.257.17:47:36.43#ibcon#*before write, iclass 37, count 0 2006.257.17:47:36.43#ibcon#enter sib2, iclass 37, count 0 2006.257.17:47:36.43#ibcon#flushed, iclass 37, count 0 2006.257.17:47:36.43#ibcon#about to write, iclass 37, count 0 2006.257.17:47:36.43#ibcon#wrote, iclass 37, count 0 2006.257.17:47:36.43#ibcon#about to read 3, iclass 37, count 0 2006.257.17:47:36.46#ibcon#read 3, iclass 37, count 0 2006.257.17:47:36.46#ibcon#about to read 4, iclass 37, count 0 2006.257.17:47:36.46#ibcon#read 4, iclass 37, count 0 2006.257.17:47:36.46#ibcon#about to read 5, iclass 37, count 0 2006.257.17:47:36.46#ibcon#read 5, iclass 37, count 0 2006.257.17:47:36.46#ibcon#about to read 6, iclass 37, count 0 2006.257.17:47:36.46#ibcon#read 6, iclass 37, count 0 2006.257.17:47:36.46#ibcon#end of sib2, iclass 37, count 0 2006.257.17:47:36.46#ibcon#*after write, iclass 37, count 0 2006.257.17:47:36.46#ibcon#*before return 0, iclass 37, count 0 2006.257.17:47:36.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:36.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:36.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.17:47:36.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.17:47:36.46$vck44/valo=7,864.99 2006.257.17:47:36.46#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.17:47:36.46#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.17:47:36.46#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:36.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:36.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:36.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:36.46#ibcon#enter wrdev, iclass 39, count 0 2006.257.17:47:36.46#ibcon#first serial, iclass 39, count 0 2006.257.17:47:36.46#ibcon#enter sib2, iclass 39, count 0 2006.257.17:47:36.46#ibcon#flushed, iclass 39, count 0 2006.257.17:47:36.46#ibcon#about to write, iclass 39, count 0 2006.257.17:47:36.46#ibcon#wrote, iclass 39, count 0 2006.257.17:47:36.46#ibcon#about to read 3, iclass 39, count 0 2006.257.17:47:36.48#ibcon#read 3, iclass 39, count 0 2006.257.17:47:36.48#ibcon#about to read 4, iclass 39, count 0 2006.257.17:47:36.48#ibcon#read 4, iclass 39, count 0 2006.257.17:47:36.48#ibcon#about to read 5, iclass 39, count 0 2006.257.17:47:36.48#ibcon#read 5, iclass 39, count 0 2006.257.17:47:36.48#ibcon#about to read 6, iclass 39, count 0 2006.257.17:47:36.48#ibcon#read 6, iclass 39, count 0 2006.257.17:47:36.48#ibcon#end of sib2, iclass 39, count 0 2006.257.17:47:36.48#ibcon#*mode == 0, iclass 39, count 0 2006.257.17:47:36.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.17:47:36.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:47:36.48#ibcon#*before write, iclass 39, count 0 2006.257.17:47:36.48#ibcon#enter sib2, iclass 39, count 0 2006.257.17:47:36.48#ibcon#flushed, iclass 39, count 0 2006.257.17:47:36.48#ibcon#about to write, iclass 39, count 0 2006.257.17:47:36.48#ibcon#wrote, iclass 39, count 0 2006.257.17:47:36.48#ibcon#about to read 3, iclass 39, count 0 2006.257.17:47:36.52#ibcon#read 3, iclass 39, count 0 2006.257.17:47:36.52#ibcon#about to read 4, iclass 39, count 0 2006.257.17:47:36.52#ibcon#read 4, iclass 39, count 0 2006.257.17:47:36.52#ibcon#about to read 5, iclass 39, count 0 2006.257.17:47:36.52#ibcon#read 5, iclass 39, count 0 2006.257.17:47:36.52#ibcon#about to read 6, iclass 39, count 0 2006.257.17:47:36.52#ibcon#read 6, iclass 39, count 0 2006.257.17:47:36.52#ibcon#end of sib2, iclass 39, count 0 2006.257.17:47:36.52#ibcon#*after write, iclass 39, count 0 2006.257.17:47:36.52#ibcon#*before return 0, iclass 39, count 0 2006.257.17:47:36.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:36.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:36.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.17:47:36.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.17:47:36.52$vck44/va=7,4 2006.257.17:47:36.52#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.17:47:36.52#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.17:47:36.52#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:36.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:36.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:36.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:36.58#ibcon#enter wrdev, iclass 3, count 2 2006.257.17:47:36.58#ibcon#first serial, iclass 3, count 2 2006.257.17:47:36.58#ibcon#enter sib2, iclass 3, count 2 2006.257.17:47:36.58#ibcon#flushed, iclass 3, count 2 2006.257.17:47:36.58#ibcon#about to write, iclass 3, count 2 2006.257.17:47:36.58#ibcon#wrote, iclass 3, count 2 2006.257.17:47:36.58#ibcon#about to read 3, iclass 3, count 2 2006.257.17:47:36.60#ibcon#read 3, iclass 3, count 2 2006.257.17:47:36.60#ibcon#about to read 4, iclass 3, count 2 2006.257.17:47:36.60#ibcon#read 4, iclass 3, count 2 2006.257.17:47:36.60#ibcon#about to read 5, iclass 3, count 2 2006.257.17:47:36.60#ibcon#read 5, iclass 3, count 2 2006.257.17:47:36.60#ibcon#about to read 6, iclass 3, count 2 2006.257.17:47:36.60#ibcon#read 6, iclass 3, count 2 2006.257.17:47:36.60#ibcon#end of sib2, iclass 3, count 2 2006.257.17:47:36.60#ibcon#*mode == 0, iclass 3, count 2 2006.257.17:47:36.60#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.17:47:36.60#ibcon#[25=AT07-04\r\n] 2006.257.17:47:36.60#ibcon#*before write, iclass 3, count 2 2006.257.17:47:36.60#ibcon#enter sib2, iclass 3, count 2 2006.257.17:47:36.60#ibcon#flushed, iclass 3, count 2 2006.257.17:47:36.60#ibcon#about to write, iclass 3, count 2 2006.257.17:47:36.60#ibcon#wrote, iclass 3, count 2 2006.257.17:47:36.60#ibcon#about to read 3, iclass 3, count 2 2006.257.17:47:36.63#ibcon#read 3, iclass 3, count 2 2006.257.17:47:36.63#ibcon#about to read 4, iclass 3, count 2 2006.257.17:47:36.63#ibcon#read 4, iclass 3, count 2 2006.257.17:47:36.63#ibcon#about to read 5, iclass 3, count 2 2006.257.17:47:36.63#ibcon#read 5, iclass 3, count 2 2006.257.17:47:36.63#ibcon#about to read 6, iclass 3, count 2 2006.257.17:47:36.63#ibcon#read 6, iclass 3, count 2 2006.257.17:47:36.63#ibcon#end of sib2, iclass 3, count 2 2006.257.17:47:36.63#ibcon#*after write, iclass 3, count 2 2006.257.17:47:36.63#ibcon#*before return 0, iclass 3, count 2 2006.257.17:47:36.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:36.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:36.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.17:47:36.63#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:36.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:36.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:36.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:36.75#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:47:36.75#ibcon#first serial, iclass 3, count 0 2006.257.17:47:36.75#ibcon#enter sib2, iclass 3, count 0 2006.257.17:47:36.75#ibcon#flushed, iclass 3, count 0 2006.257.17:47:36.75#ibcon#about to write, iclass 3, count 0 2006.257.17:47:36.75#ibcon#wrote, iclass 3, count 0 2006.257.17:47:36.75#ibcon#about to read 3, iclass 3, count 0 2006.257.17:47:36.77#ibcon#read 3, iclass 3, count 0 2006.257.17:47:36.77#ibcon#about to read 4, iclass 3, count 0 2006.257.17:47:36.77#ibcon#read 4, iclass 3, count 0 2006.257.17:47:36.77#ibcon#about to read 5, iclass 3, count 0 2006.257.17:47:36.77#ibcon#read 5, iclass 3, count 0 2006.257.17:47:36.77#ibcon#about to read 6, iclass 3, count 0 2006.257.17:47:36.77#ibcon#read 6, iclass 3, count 0 2006.257.17:47:36.77#ibcon#end of sib2, iclass 3, count 0 2006.257.17:47:36.77#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:47:36.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:47:36.77#ibcon#[25=USB\r\n] 2006.257.17:47:36.77#ibcon#*before write, iclass 3, count 0 2006.257.17:47:36.77#ibcon#enter sib2, iclass 3, count 0 2006.257.17:47:36.77#ibcon#flushed, iclass 3, count 0 2006.257.17:47:36.77#ibcon#about to write, iclass 3, count 0 2006.257.17:47:36.77#ibcon#wrote, iclass 3, count 0 2006.257.17:47:36.77#ibcon#about to read 3, iclass 3, count 0 2006.257.17:47:36.80#ibcon#read 3, iclass 3, count 0 2006.257.17:47:36.80#ibcon#about to read 4, iclass 3, count 0 2006.257.17:47:36.80#ibcon#read 4, iclass 3, count 0 2006.257.17:47:36.80#ibcon#about to read 5, iclass 3, count 0 2006.257.17:47:36.80#ibcon#read 5, iclass 3, count 0 2006.257.17:47:36.80#ibcon#about to read 6, iclass 3, count 0 2006.257.17:47:36.80#ibcon#read 6, iclass 3, count 0 2006.257.17:47:36.80#ibcon#end of sib2, iclass 3, count 0 2006.257.17:47:36.80#ibcon#*after write, iclass 3, count 0 2006.257.17:47:36.80#ibcon#*before return 0, iclass 3, count 0 2006.257.17:47:36.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:36.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:36.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:47:36.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:47:36.80$vck44/valo=8,884.99 2006.257.17:47:36.80#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.17:47:36.80#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.17:47:36.80#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:36.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:36.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:36.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:36.80#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:47:36.80#ibcon#first serial, iclass 5, count 0 2006.257.17:47:36.80#ibcon#enter sib2, iclass 5, count 0 2006.257.17:47:36.80#ibcon#flushed, iclass 5, count 0 2006.257.17:47:36.80#ibcon#about to write, iclass 5, count 0 2006.257.17:47:36.80#ibcon#wrote, iclass 5, count 0 2006.257.17:47:36.80#ibcon#about to read 3, iclass 5, count 0 2006.257.17:47:36.82#ibcon#read 3, iclass 5, count 0 2006.257.17:47:36.82#ibcon#about to read 4, iclass 5, count 0 2006.257.17:47:36.82#ibcon#read 4, iclass 5, count 0 2006.257.17:47:36.82#ibcon#about to read 5, iclass 5, count 0 2006.257.17:47:36.82#ibcon#read 5, iclass 5, count 0 2006.257.17:47:36.82#ibcon#about to read 6, iclass 5, count 0 2006.257.17:47:36.82#ibcon#read 6, iclass 5, count 0 2006.257.17:47:36.82#ibcon#end of sib2, iclass 5, count 0 2006.257.17:47:36.82#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:47:36.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:47:36.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:47:36.82#ibcon#*before write, iclass 5, count 0 2006.257.17:47:36.82#ibcon#enter sib2, iclass 5, count 0 2006.257.17:47:36.82#ibcon#flushed, iclass 5, count 0 2006.257.17:47:36.82#ibcon#about to write, iclass 5, count 0 2006.257.17:47:36.82#ibcon#wrote, iclass 5, count 0 2006.257.17:47:36.82#ibcon#about to read 3, iclass 5, count 0 2006.257.17:47:36.86#ibcon#read 3, iclass 5, count 0 2006.257.17:47:36.86#ibcon#about to read 4, iclass 5, count 0 2006.257.17:47:36.86#ibcon#read 4, iclass 5, count 0 2006.257.17:47:36.86#ibcon#about to read 5, iclass 5, count 0 2006.257.17:47:36.86#ibcon#read 5, iclass 5, count 0 2006.257.17:47:36.86#ibcon#about to read 6, iclass 5, count 0 2006.257.17:47:36.86#ibcon#read 6, iclass 5, count 0 2006.257.17:47:36.86#ibcon#end of sib2, iclass 5, count 0 2006.257.17:47:36.86#ibcon#*after write, iclass 5, count 0 2006.257.17:47:36.86#ibcon#*before return 0, iclass 5, count 0 2006.257.17:47:36.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:36.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:36.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:47:36.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:47:36.86$vck44/va=8,4 2006.257.17:47:36.86#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.17:47:36.86#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.17:47:36.86#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:36.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:47:36.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:47:36.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:47:36.92#ibcon#enter wrdev, iclass 7, count 2 2006.257.17:47:36.92#ibcon#first serial, iclass 7, count 2 2006.257.17:47:36.92#ibcon#enter sib2, iclass 7, count 2 2006.257.17:47:36.92#ibcon#flushed, iclass 7, count 2 2006.257.17:47:36.92#ibcon#about to write, iclass 7, count 2 2006.257.17:47:36.92#ibcon#wrote, iclass 7, count 2 2006.257.17:47:36.92#ibcon#about to read 3, iclass 7, count 2 2006.257.17:47:36.94#ibcon#read 3, iclass 7, count 2 2006.257.17:47:36.94#ibcon#about to read 4, iclass 7, count 2 2006.257.17:47:36.94#ibcon#read 4, iclass 7, count 2 2006.257.17:47:36.94#ibcon#about to read 5, iclass 7, count 2 2006.257.17:47:36.94#ibcon#read 5, iclass 7, count 2 2006.257.17:47:36.94#ibcon#about to read 6, iclass 7, count 2 2006.257.17:47:36.94#ibcon#read 6, iclass 7, count 2 2006.257.17:47:36.94#ibcon#end of sib2, iclass 7, count 2 2006.257.17:47:36.94#ibcon#*mode == 0, iclass 7, count 2 2006.257.17:47:36.94#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.17:47:36.94#ibcon#[25=AT08-04\r\n] 2006.257.17:47:36.94#ibcon#*before write, iclass 7, count 2 2006.257.17:47:36.94#ibcon#enter sib2, iclass 7, count 2 2006.257.17:47:36.94#ibcon#flushed, iclass 7, count 2 2006.257.17:47:36.94#ibcon#about to write, iclass 7, count 2 2006.257.17:47:36.94#ibcon#wrote, iclass 7, count 2 2006.257.17:47:36.94#ibcon#about to read 3, iclass 7, count 2 2006.257.17:47:36.97#ibcon#read 3, iclass 7, count 2 2006.257.17:47:36.97#ibcon#about to read 4, iclass 7, count 2 2006.257.17:47:36.97#ibcon#read 4, iclass 7, count 2 2006.257.17:47:36.97#ibcon#about to read 5, iclass 7, count 2 2006.257.17:47:36.97#ibcon#read 5, iclass 7, count 2 2006.257.17:47:36.97#ibcon#about to read 6, iclass 7, count 2 2006.257.17:47:36.97#ibcon#read 6, iclass 7, count 2 2006.257.17:47:36.97#ibcon#end of sib2, iclass 7, count 2 2006.257.17:47:36.97#ibcon#*after write, iclass 7, count 2 2006.257.17:47:36.97#ibcon#*before return 0, iclass 7, count 2 2006.257.17:47:36.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:47:36.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.17:47:36.97#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.17:47:36.97#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:36.97#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:47:37.09#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:47:37.09#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:47:37.09#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:47:37.09#ibcon#first serial, iclass 7, count 0 2006.257.17:47:37.09#ibcon#enter sib2, iclass 7, count 0 2006.257.17:47:37.09#ibcon#flushed, iclass 7, count 0 2006.257.17:47:37.09#ibcon#about to write, iclass 7, count 0 2006.257.17:47:37.09#ibcon#wrote, iclass 7, count 0 2006.257.17:47:37.09#ibcon#about to read 3, iclass 7, count 0 2006.257.17:47:37.11#ibcon#read 3, iclass 7, count 0 2006.257.17:47:37.11#ibcon#about to read 4, iclass 7, count 0 2006.257.17:47:37.11#ibcon#read 4, iclass 7, count 0 2006.257.17:47:37.11#ibcon#about to read 5, iclass 7, count 0 2006.257.17:47:37.11#ibcon#read 5, iclass 7, count 0 2006.257.17:47:37.11#ibcon#about to read 6, iclass 7, count 0 2006.257.17:47:37.11#ibcon#read 6, iclass 7, count 0 2006.257.17:47:37.11#ibcon#end of sib2, iclass 7, count 0 2006.257.17:47:37.11#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:47:37.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:47:37.11#ibcon#[25=USB\r\n] 2006.257.17:47:37.11#ibcon#*before write, iclass 7, count 0 2006.257.17:47:37.11#ibcon#enter sib2, iclass 7, count 0 2006.257.17:47:37.11#ibcon#flushed, iclass 7, count 0 2006.257.17:47:37.11#ibcon#about to write, iclass 7, count 0 2006.257.17:47:37.11#ibcon#wrote, iclass 7, count 0 2006.257.17:47:37.11#ibcon#about to read 3, iclass 7, count 0 2006.257.17:47:37.14#ibcon#read 3, iclass 7, count 0 2006.257.17:47:37.14#ibcon#about to read 4, iclass 7, count 0 2006.257.17:47:37.14#ibcon#read 4, iclass 7, count 0 2006.257.17:47:37.14#ibcon#about to read 5, iclass 7, count 0 2006.257.17:47:37.14#ibcon#read 5, iclass 7, count 0 2006.257.17:47:37.14#ibcon#about to read 6, iclass 7, count 0 2006.257.17:47:37.14#ibcon#read 6, iclass 7, count 0 2006.257.17:47:37.14#ibcon#end of sib2, iclass 7, count 0 2006.257.17:47:37.14#ibcon#*after write, iclass 7, count 0 2006.257.17:47:37.14#ibcon#*before return 0, iclass 7, count 0 2006.257.17:47:37.14#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:47:37.14#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.17:47:37.14#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:47:37.14#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:47:37.14$vck44/vblo=1,629.99 2006.257.17:47:37.14#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.17:47:37.14#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.17:47:37.14#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:37.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:47:37.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:47:37.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:47:37.14#ibcon#enter wrdev, iclass 11, count 0 2006.257.17:47:37.14#ibcon#first serial, iclass 11, count 0 2006.257.17:47:37.14#ibcon#enter sib2, iclass 11, count 0 2006.257.17:47:37.14#ibcon#flushed, iclass 11, count 0 2006.257.17:47:37.14#ibcon#about to write, iclass 11, count 0 2006.257.17:47:37.14#ibcon#wrote, iclass 11, count 0 2006.257.17:47:37.14#ibcon#about to read 3, iclass 11, count 0 2006.257.17:47:37.16#ibcon#read 3, iclass 11, count 0 2006.257.17:47:37.16#ibcon#about to read 4, iclass 11, count 0 2006.257.17:47:37.16#ibcon#read 4, iclass 11, count 0 2006.257.17:47:37.16#ibcon#about to read 5, iclass 11, count 0 2006.257.17:47:37.16#ibcon#read 5, iclass 11, count 0 2006.257.17:47:37.16#ibcon#about to read 6, iclass 11, count 0 2006.257.17:47:37.16#ibcon#read 6, iclass 11, count 0 2006.257.17:47:37.16#ibcon#end of sib2, iclass 11, count 0 2006.257.17:47:37.16#ibcon#*mode == 0, iclass 11, count 0 2006.257.17:47:37.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.17:47:37.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:47:37.16#ibcon#*before write, iclass 11, count 0 2006.257.17:47:37.16#ibcon#enter sib2, iclass 11, count 0 2006.257.17:47:37.16#ibcon#flushed, iclass 11, count 0 2006.257.17:47:37.16#ibcon#about to write, iclass 11, count 0 2006.257.17:47:37.16#ibcon#wrote, iclass 11, count 0 2006.257.17:47:37.16#ibcon#about to read 3, iclass 11, count 0 2006.257.17:47:37.20#ibcon#read 3, iclass 11, count 0 2006.257.17:47:37.20#ibcon#about to read 4, iclass 11, count 0 2006.257.17:47:37.20#ibcon#read 4, iclass 11, count 0 2006.257.17:47:37.20#ibcon#about to read 5, iclass 11, count 0 2006.257.17:47:37.20#ibcon#read 5, iclass 11, count 0 2006.257.17:47:37.20#ibcon#about to read 6, iclass 11, count 0 2006.257.17:47:37.20#ibcon#read 6, iclass 11, count 0 2006.257.17:47:37.20#ibcon#end of sib2, iclass 11, count 0 2006.257.17:47:37.20#ibcon#*after write, iclass 11, count 0 2006.257.17:47:37.20#ibcon#*before return 0, iclass 11, count 0 2006.257.17:47:37.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:47:37.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.17:47:37.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.17:47:37.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.17:47:37.20$vck44/vb=1,4 2006.257.17:47:37.20#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.17:47:37.20#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.17:47:37.20#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:37.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:47:37.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:47:37.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:47:37.20#ibcon#enter wrdev, iclass 13, count 2 2006.257.17:47:37.20#ibcon#first serial, iclass 13, count 2 2006.257.17:47:37.20#ibcon#enter sib2, iclass 13, count 2 2006.257.17:47:37.20#ibcon#flushed, iclass 13, count 2 2006.257.17:47:37.20#ibcon#about to write, iclass 13, count 2 2006.257.17:47:37.20#ibcon#wrote, iclass 13, count 2 2006.257.17:47:37.20#ibcon#about to read 3, iclass 13, count 2 2006.257.17:47:37.22#ibcon#read 3, iclass 13, count 2 2006.257.17:47:37.22#ibcon#about to read 4, iclass 13, count 2 2006.257.17:47:37.22#ibcon#read 4, iclass 13, count 2 2006.257.17:47:37.22#ibcon#about to read 5, iclass 13, count 2 2006.257.17:47:37.22#ibcon#read 5, iclass 13, count 2 2006.257.17:47:37.22#ibcon#about to read 6, iclass 13, count 2 2006.257.17:47:37.22#ibcon#read 6, iclass 13, count 2 2006.257.17:47:37.22#ibcon#end of sib2, iclass 13, count 2 2006.257.17:47:37.22#ibcon#*mode == 0, iclass 13, count 2 2006.257.17:47:37.22#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.17:47:37.22#ibcon#[27=AT01-04\r\n] 2006.257.17:47:37.22#ibcon#*before write, iclass 13, count 2 2006.257.17:47:37.22#ibcon#enter sib2, iclass 13, count 2 2006.257.17:47:37.22#ibcon#flushed, iclass 13, count 2 2006.257.17:47:37.22#ibcon#about to write, iclass 13, count 2 2006.257.17:47:37.22#ibcon#wrote, iclass 13, count 2 2006.257.17:47:37.22#ibcon#about to read 3, iclass 13, count 2 2006.257.17:47:37.25#ibcon#read 3, iclass 13, count 2 2006.257.17:47:37.25#ibcon#about to read 4, iclass 13, count 2 2006.257.17:47:37.25#ibcon#read 4, iclass 13, count 2 2006.257.17:47:37.25#ibcon#about to read 5, iclass 13, count 2 2006.257.17:47:37.25#ibcon#read 5, iclass 13, count 2 2006.257.17:47:37.25#ibcon#about to read 6, iclass 13, count 2 2006.257.17:47:37.25#ibcon#read 6, iclass 13, count 2 2006.257.17:47:37.25#ibcon#end of sib2, iclass 13, count 2 2006.257.17:47:37.25#ibcon#*after write, iclass 13, count 2 2006.257.17:47:37.25#ibcon#*before return 0, iclass 13, count 2 2006.257.17:47:37.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:47:37.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.17:47:37.25#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.17:47:37.25#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:37.25#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:47:37.37#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:47:37.37#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:47:37.37#ibcon#enter wrdev, iclass 13, count 0 2006.257.17:47:37.37#ibcon#first serial, iclass 13, count 0 2006.257.17:47:37.37#ibcon#enter sib2, iclass 13, count 0 2006.257.17:47:37.37#ibcon#flushed, iclass 13, count 0 2006.257.17:47:37.37#ibcon#about to write, iclass 13, count 0 2006.257.17:47:37.37#ibcon#wrote, iclass 13, count 0 2006.257.17:47:37.37#ibcon#about to read 3, iclass 13, count 0 2006.257.17:47:37.39#ibcon#read 3, iclass 13, count 0 2006.257.17:47:37.39#ibcon#about to read 4, iclass 13, count 0 2006.257.17:47:37.39#ibcon#read 4, iclass 13, count 0 2006.257.17:47:37.39#ibcon#about to read 5, iclass 13, count 0 2006.257.17:47:37.39#ibcon#read 5, iclass 13, count 0 2006.257.17:47:37.39#ibcon#about to read 6, iclass 13, count 0 2006.257.17:47:37.39#ibcon#read 6, iclass 13, count 0 2006.257.17:47:37.39#ibcon#end of sib2, iclass 13, count 0 2006.257.17:47:37.39#ibcon#*mode == 0, iclass 13, count 0 2006.257.17:47:37.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.17:47:37.39#ibcon#[27=USB\r\n] 2006.257.17:47:37.39#ibcon#*before write, iclass 13, count 0 2006.257.17:47:37.39#ibcon#enter sib2, iclass 13, count 0 2006.257.17:47:37.39#ibcon#flushed, iclass 13, count 0 2006.257.17:47:37.39#ibcon#about to write, iclass 13, count 0 2006.257.17:47:37.39#ibcon#wrote, iclass 13, count 0 2006.257.17:47:37.39#ibcon#about to read 3, iclass 13, count 0 2006.257.17:47:37.42#ibcon#read 3, iclass 13, count 0 2006.257.17:47:37.42#ibcon#about to read 4, iclass 13, count 0 2006.257.17:47:37.42#ibcon#read 4, iclass 13, count 0 2006.257.17:47:37.42#ibcon#about to read 5, iclass 13, count 0 2006.257.17:47:37.42#ibcon#read 5, iclass 13, count 0 2006.257.17:47:37.42#ibcon#about to read 6, iclass 13, count 0 2006.257.17:47:37.42#ibcon#read 6, iclass 13, count 0 2006.257.17:47:37.42#ibcon#end of sib2, iclass 13, count 0 2006.257.17:47:37.42#ibcon#*after write, iclass 13, count 0 2006.257.17:47:37.42#ibcon#*before return 0, iclass 13, count 0 2006.257.17:47:37.42#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:47:37.42#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.17:47:37.42#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.17:47:37.42#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.17:47:37.42$vck44/vblo=2,634.99 2006.257.17:47:37.42#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.17:47:37.42#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.17:47:37.42#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:37.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:37.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:37.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:37.42#ibcon#enter wrdev, iclass 15, count 0 2006.257.17:47:37.42#ibcon#first serial, iclass 15, count 0 2006.257.17:47:37.42#ibcon#enter sib2, iclass 15, count 0 2006.257.17:47:37.42#ibcon#flushed, iclass 15, count 0 2006.257.17:47:37.42#ibcon#about to write, iclass 15, count 0 2006.257.17:47:37.42#ibcon#wrote, iclass 15, count 0 2006.257.17:47:37.42#ibcon#about to read 3, iclass 15, count 0 2006.257.17:47:37.44#ibcon#read 3, iclass 15, count 0 2006.257.17:47:37.44#ibcon#about to read 4, iclass 15, count 0 2006.257.17:47:37.44#ibcon#read 4, iclass 15, count 0 2006.257.17:47:37.44#ibcon#about to read 5, iclass 15, count 0 2006.257.17:47:37.44#ibcon#read 5, iclass 15, count 0 2006.257.17:47:37.44#ibcon#about to read 6, iclass 15, count 0 2006.257.17:47:37.44#ibcon#read 6, iclass 15, count 0 2006.257.17:47:37.44#ibcon#end of sib2, iclass 15, count 0 2006.257.17:47:37.44#ibcon#*mode == 0, iclass 15, count 0 2006.257.17:47:37.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.17:47:37.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:47:37.44#ibcon#*before write, iclass 15, count 0 2006.257.17:47:37.44#ibcon#enter sib2, iclass 15, count 0 2006.257.17:47:37.44#ibcon#flushed, iclass 15, count 0 2006.257.17:47:37.44#ibcon#about to write, iclass 15, count 0 2006.257.17:47:37.44#ibcon#wrote, iclass 15, count 0 2006.257.17:47:37.44#ibcon#about to read 3, iclass 15, count 0 2006.257.17:47:37.48#ibcon#read 3, iclass 15, count 0 2006.257.17:47:37.48#ibcon#about to read 4, iclass 15, count 0 2006.257.17:47:37.48#ibcon#read 4, iclass 15, count 0 2006.257.17:47:37.48#ibcon#about to read 5, iclass 15, count 0 2006.257.17:47:37.48#ibcon#read 5, iclass 15, count 0 2006.257.17:47:37.48#ibcon#about to read 6, iclass 15, count 0 2006.257.17:47:37.48#ibcon#read 6, iclass 15, count 0 2006.257.17:47:37.48#ibcon#end of sib2, iclass 15, count 0 2006.257.17:47:37.48#ibcon#*after write, iclass 15, count 0 2006.257.17:47:37.48#ibcon#*before return 0, iclass 15, count 0 2006.257.17:47:37.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:37.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.17:47:37.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.17:47:37.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.17:47:37.48$vck44/vb=2,5 2006.257.17:47:37.48#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.17:47:37.48#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.17:47:37.48#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:37.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:37.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:37.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:37.54#ibcon#enter wrdev, iclass 17, count 2 2006.257.17:47:37.54#ibcon#first serial, iclass 17, count 2 2006.257.17:47:37.54#ibcon#enter sib2, iclass 17, count 2 2006.257.17:47:37.54#ibcon#flushed, iclass 17, count 2 2006.257.17:47:37.54#ibcon#about to write, iclass 17, count 2 2006.257.17:47:37.54#ibcon#wrote, iclass 17, count 2 2006.257.17:47:37.54#ibcon#about to read 3, iclass 17, count 2 2006.257.17:47:37.56#ibcon#read 3, iclass 17, count 2 2006.257.17:47:37.56#ibcon#about to read 4, iclass 17, count 2 2006.257.17:47:37.56#ibcon#read 4, iclass 17, count 2 2006.257.17:47:37.56#ibcon#about to read 5, iclass 17, count 2 2006.257.17:47:37.56#ibcon#read 5, iclass 17, count 2 2006.257.17:47:37.56#ibcon#about to read 6, iclass 17, count 2 2006.257.17:47:37.56#ibcon#read 6, iclass 17, count 2 2006.257.17:47:37.56#ibcon#end of sib2, iclass 17, count 2 2006.257.17:47:37.56#ibcon#*mode == 0, iclass 17, count 2 2006.257.17:47:37.56#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.17:47:37.56#ibcon#[27=AT02-05\r\n] 2006.257.17:47:37.56#ibcon#*before write, iclass 17, count 2 2006.257.17:47:37.56#ibcon#enter sib2, iclass 17, count 2 2006.257.17:47:37.56#ibcon#flushed, iclass 17, count 2 2006.257.17:47:37.56#ibcon#about to write, iclass 17, count 2 2006.257.17:47:37.56#ibcon#wrote, iclass 17, count 2 2006.257.17:47:37.56#ibcon#about to read 3, iclass 17, count 2 2006.257.17:47:37.59#ibcon#read 3, iclass 17, count 2 2006.257.17:47:37.59#ibcon#about to read 4, iclass 17, count 2 2006.257.17:47:37.59#ibcon#read 4, iclass 17, count 2 2006.257.17:47:37.59#ibcon#about to read 5, iclass 17, count 2 2006.257.17:47:37.59#ibcon#read 5, iclass 17, count 2 2006.257.17:47:37.59#ibcon#about to read 6, iclass 17, count 2 2006.257.17:47:37.59#ibcon#read 6, iclass 17, count 2 2006.257.17:47:37.59#ibcon#end of sib2, iclass 17, count 2 2006.257.17:47:37.59#ibcon#*after write, iclass 17, count 2 2006.257.17:47:37.59#ibcon#*before return 0, iclass 17, count 2 2006.257.17:47:37.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:37.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.17:47:37.59#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.17:47:37.59#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:37.59#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:37.71#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:37.71#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:37.71#ibcon#enter wrdev, iclass 17, count 0 2006.257.17:47:37.71#ibcon#first serial, iclass 17, count 0 2006.257.17:47:37.71#ibcon#enter sib2, iclass 17, count 0 2006.257.17:47:37.71#ibcon#flushed, iclass 17, count 0 2006.257.17:47:37.71#ibcon#about to write, iclass 17, count 0 2006.257.17:47:37.71#ibcon#wrote, iclass 17, count 0 2006.257.17:47:37.71#ibcon#about to read 3, iclass 17, count 0 2006.257.17:47:37.73#ibcon#read 3, iclass 17, count 0 2006.257.17:47:37.73#ibcon#about to read 4, iclass 17, count 0 2006.257.17:47:37.73#ibcon#read 4, iclass 17, count 0 2006.257.17:47:37.73#ibcon#about to read 5, iclass 17, count 0 2006.257.17:47:37.73#ibcon#read 5, iclass 17, count 0 2006.257.17:47:37.73#ibcon#about to read 6, iclass 17, count 0 2006.257.17:47:37.73#ibcon#read 6, iclass 17, count 0 2006.257.17:47:37.73#ibcon#end of sib2, iclass 17, count 0 2006.257.17:47:37.73#ibcon#*mode == 0, iclass 17, count 0 2006.257.17:47:37.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.17:47:37.73#ibcon#[27=USB\r\n] 2006.257.17:47:37.73#ibcon#*before write, iclass 17, count 0 2006.257.17:47:37.73#ibcon#enter sib2, iclass 17, count 0 2006.257.17:47:37.73#ibcon#flushed, iclass 17, count 0 2006.257.17:47:37.73#ibcon#about to write, iclass 17, count 0 2006.257.17:47:37.73#ibcon#wrote, iclass 17, count 0 2006.257.17:47:37.73#ibcon#about to read 3, iclass 17, count 0 2006.257.17:47:37.76#ibcon#read 3, iclass 17, count 0 2006.257.17:47:37.76#ibcon#about to read 4, iclass 17, count 0 2006.257.17:47:37.76#ibcon#read 4, iclass 17, count 0 2006.257.17:47:37.76#ibcon#about to read 5, iclass 17, count 0 2006.257.17:47:37.76#ibcon#read 5, iclass 17, count 0 2006.257.17:47:37.76#ibcon#about to read 6, iclass 17, count 0 2006.257.17:47:37.76#ibcon#read 6, iclass 17, count 0 2006.257.17:47:37.76#ibcon#end of sib2, iclass 17, count 0 2006.257.17:47:37.76#ibcon#*after write, iclass 17, count 0 2006.257.17:47:37.76#ibcon#*before return 0, iclass 17, count 0 2006.257.17:47:37.76#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:37.76#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.17:47:37.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.17:47:37.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.17:47:37.76$vck44/vblo=3,649.99 2006.257.17:47:37.76#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.17:47:37.76#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.17:47:37.76#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:37.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:37.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:37.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:37.76#ibcon#enter wrdev, iclass 19, count 0 2006.257.17:47:37.76#ibcon#first serial, iclass 19, count 0 2006.257.17:47:37.76#ibcon#enter sib2, iclass 19, count 0 2006.257.17:47:37.76#ibcon#flushed, iclass 19, count 0 2006.257.17:47:37.76#ibcon#about to write, iclass 19, count 0 2006.257.17:47:37.76#ibcon#wrote, iclass 19, count 0 2006.257.17:47:37.76#ibcon#about to read 3, iclass 19, count 0 2006.257.17:47:37.78#ibcon#read 3, iclass 19, count 0 2006.257.17:47:37.78#ibcon#about to read 4, iclass 19, count 0 2006.257.17:47:37.78#ibcon#read 4, iclass 19, count 0 2006.257.17:47:37.78#ibcon#about to read 5, iclass 19, count 0 2006.257.17:47:37.78#ibcon#read 5, iclass 19, count 0 2006.257.17:47:37.78#ibcon#about to read 6, iclass 19, count 0 2006.257.17:47:37.78#ibcon#read 6, iclass 19, count 0 2006.257.17:47:37.78#ibcon#end of sib2, iclass 19, count 0 2006.257.17:47:37.78#ibcon#*mode == 0, iclass 19, count 0 2006.257.17:47:37.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.17:47:37.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:47:37.78#ibcon#*before write, iclass 19, count 0 2006.257.17:47:37.78#ibcon#enter sib2, iclass 19, count 0 2006.257.17:47:37.78#ibcon#flushed, iclass 19, count 0 2006.257.17:47:37.78#ibcon#about to write, iclass 19, count 0 2006.257.17:47:37.78#ibcon#wrote, iclass 19, count 0 2006.257.17:47:37.78#ibcon#about to read 3, iclass 19, count 0 2006.257.17:47:37.82#ibcon#read 3, iclass 19, count 0 2006.257.17:47:37.82#ibcon#about to read 4, iclass 19, count 0 2006.257.17:47:37.82#ibcon#read 4, iclass 19, count 0 2006.257.17:47:37.82#ibcon#about to read 5, iclass 19, count 0 2006.257.17:47:37.82#ibcon#read 5, iclass 19, count 0 2006.257.17:47:37.82#ibcon#about to read 6, iclass 19, count 0 2006.257.17:47:37.82#ibcon#read 6, iclass 19, count 0 2006.257.17:47:37.82#ibcon#end of sib2, iclass 19, count 0 2006.257.17:47:37.82#ibcon#*after write, iclass 19, count 0 2006.257.17:47:37.82#ibcon#*before return 0, iclass 19, count 0 2006.257.17:47:37.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:37.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.17:47:37.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.17:47:37.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.17:47:37.82$vck44/vb=3,4 2006.257.17:47:37.82#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.17:47:37.82#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.17:47:37.82#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:37.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:37.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:37.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:37.88#ibcon#enter wrdev, iclass 21, count 2 2006.257.17:47:37.88#ibcon#first serial, iclass 21, count 2 2006.257.17:47:37.88#ibcon#enter sib2, iclass 21, count 2 2006.257.17:47:37.88#ibcon#flushed, iclass 21, count 2 2006.257.17:47:37.88#ibcon#about to write, iclass 21, count 2 2006.257.17:47:37.88#ibcon#wrote, iclass 21, count 2 2006.257.17:47:37.88#ibcon#about to read 3, iclass 21, count 2 2006.257.17:47:37.90#ibcon#read 3, iclass 21, count 2 2006.257.17:47:37.90#ibcon#about to read 4, iclass 21, count 2 2006.257.17:47:37.90#ibcon#read 4, iclass 21, count 2 2006.257.17:47:37.90#ibcon#about to read 5, iclass 21, count 2 2006.257.17:47:37.90#ibcon#read 5, iclass 21, count 2 2006.257.17:47:37.90#ibcon#about to read 6, iclass 21, count 2 2006.257.17:47:37.90#ibcon#read 6, iclass 21, count 2 2006.257.17:47:37.90#ibcon#end of sib2, iclass 21, count 2 2006.257.17:47:37.90#ibcon#*mode == 0, iclass 21, count 2 2006.257.17:47:37.90#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.17:47:37.90#ibcon#[27=AT03-04\r\n] 2006.257.17:47:37.90#ibcon#*before write, iclass 21, count 2 2006.257.17:47:37.90#ibcon#enter sib2, iclass 21, count 2 2006.257.17:47:37.90#ibcon#flushed, iclass 21, count 2 2006.257.17:47:37.90#ibcon#about to write, iclass 21, count 2 2006.257.17:47:37.90#ibcon#wrote, iclass 21, count 2 2006.257.17:47:37.90#ibcon#about to read 3, iclass 21, count 2 2006.257.17:47:37.93#ibcon#read 3, iclass 21, count 2 2006.257.17:47:37.93#ibcon#about to read 4, iclass 21, count 2 2006.257.17:47:37.93#ibcon#read 4, iclass 21, count 2 2006.257.17:47:37.93#ibcon#about to read 5, iclass 21, count 2 2006.257.17:47:37.93#ibcon#read 5, iclass 21, count 2 2006.257.17:47:37.93#ibcon#about to read 6, iclass 21, count 2 2006.257.17:47:37.93#ibcon#read 6, iclass 21, count 2 2006.257.17:47:37.93#ibcon#end of sib2, iclass 21, count 2 2006.257.17:47:37.93#ibcon#*after write, iclass 21, count 2 2006.257.17:47:37.93#ibcon#*before return 0, iclass 21, count 2 2006.257.17:47:37.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:37.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.17:47:37.93#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.17:47:37.93#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:37.93#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:38.05#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:38.05#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:38.05#ibcon#enter wrdev, iclass 21, count 0 2006.257.17:47:38.05#ibcon#first serial, iclass 21, count 0 2006.257.17:47:38.05#ibcon#enter sib2, iclass 21, count 0 2006.257.17:47:38.05#ibcon#flushed, iclass 21, count 0 2006.257.17:47:38.05#ibcon#about to write, iclass 21, count 0 2006.257.17:47:38.05#ibcon#wrote, iclass 21, count 0 2006.257.17:47:38.05#ibcon#about to read 3, iclass 21, count 0 2006.257.17:47:38.07#ibcon#read 3, iclass 21, count 0 2006.257.17:47:38.07#ibcon#about to read 4, iclass 21, count 0 2006.257.17:47:38.07#ibcon#read 4, iclass 21, count 0 2006.257.17:47:38.07#ibcon#about to read 5, iclass 21, count 0 2006.257.17:47:38.07#ibcon#read 5, iclass 21, count 0 2006.257.17:47:38.07#ibcon#about to read 6, iclass 21, count 0 2006.257.17:47:38.07#ibcon#read 6, iclass 21, count 0 2006.257.17:47:38.07#ibcon#end of sib2, iclass 21, count 0 2006.257.17:47:38.07#ibcon#*mode == 0, iclass 21, count 0 2006.257.17:47:38.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.17:47:38.07#ibcon#[27=USB\r\n] 2006.257.17:47:38.07#ibcon#*before write, iclass 21, count 0 2006.257.17:47:38.07#ibcon#enter sib2, iclass 21, count 0 2006.257.17:47:38.07#ibcon#flushed, iclass 21, count 0 2006.257.17:47:38.07#ibcon#about to write, iclass 21, count 0 2006.257.17:47:38.07#ibcon#wrote, iclass 21, count 0 2006.257.17:47:38.07#ibcon#about to read 3, iclass 21, count 0 2006.257.17:47:38.10#ibcon#read 3, iclass 21, count 0 2006.257.17:47:38.10#ibcon#about to read 4, iclass 21, count 0 2006.257.17:47:38.10#ibcon#read 4, iclass 21, count 0 2006.257.17:47:38.10#ibcon#about to read 5, iclass 21, count 0 2006.257.17:47:38.10#ibcon#read 5, iclass 21, count 0 2006.257.17:47:38.10#ibcon#about to read 6, iclass 21, count 0 2006.257.17:47:38.10#ibcon#read 6, iclass 21, count 0 2006.257.17:47:38.10#ibcon#end of sib2, iclass 21, count 0 2006.257.17:47:38.10#ibcon#*after write, iclass 21, count 0 2006.257.17:47:38.10#ibcon#*before return 0, iclass 21, count 0 2006.257.17:47:38.10#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:38.10#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.17:47:38.10#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.17:47:38.10#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.17:47:38.10$vck44/vblo=4,679.99 2006.257.17:47:38.10#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.17:47:38.10#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.17:47:38.10#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:38.10#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:38.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:38.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:38.10#ibcon#enter wrdev, iclass 23, count 0 2006.257.17:47:38.10#ibcon#first serial, iclass 23, count 0 2006.257.17:47:38.10#ibcon#enter sib2, iclass 23, count 0 2006.257.17:47:38.10#ibcon#flushed, iclass 23, count 0 2006.257.17:47:38.10#ibcon#about to write, iclass 23, count 0 2006.257.17:47:38.10#ibcon#wrote, iclass 23, count 0 2006.257.17:47:38.10#ibcon#about to read 3, iclass 23, count 0 2006.257.17:47:38.12#ibcon#read 3, iclass 23, count 0 2006.257.17:47:38.12#ibcon#about to read 4, iclass 23, count 0 2006.257.17:47:38.12#ibcon#read 4, iclass 23, count 0 2006.257.17:47:38.12#ibcon#about to read 5, iclass 23, count 0 2006.257.17:47:38.12#ibcon#read 5, iclass 23, count 0 2006.257.17:47:38.12#ibcon#about to read 6, iclass 23, count 0 2006.257.17:47:38.12#ibcon#read 6, iclass 23, count 0 2006.257.17:47:38.12#ibcon#end of sib2, iclass 23, count 0 2006.257.17:47:38.12#ibcon#*mode == 0, iclass 23, count 0 2006.257.17:47:38.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.17:47:38.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:47:38.12#ibcon#*before write, iclass 23, count 0 2006.257.17:47:38.12#ibcon#enter sib2, iclass 23, count 0 2006.257.17:47:38.12#ibcon#flushed, iclass 23, count 0 2006.257.17:47:38.12#ibcon#about to write, iclass 23, count 0 2006.257.17:47:38.12#ibcon#wrote, iclass 23, count 0 2006.257.17:47:38.12#ibcon#about to read 3, iclass 23, count 0 2006.257.17:47:38.16#ibcon#read 3, iclass 23, count 0 2006.257.17:47:38.16#ibcon#about to read 4, iclass 23, count 0 2006.257.17:47:38.16#ibcon#read 4, iclass 23, count 0 2006.257.17:47:38.16#ibcon#about to read 5, iclass 23, count 0 2006.257.17:47:38.16#ibcon#read 5, iclass 23, count 0 2006.257.17:47:38.16#ibcon#about to read 6, iclass 23, count 0 2006.257.17:47:38.16#ibcon#read 6, iclass 23, count 0 2006.257.17:47:38.16#ibcon#end of sib2, iclass 23, count 0 2006.257.17:47:38.16#ibcon#*after write, iclass 23, count 0 2006.257.17:47:38.16#ibcon#*before return 0, iclass 23, count 0 2006.257.17:47:38.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:38.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.17:47:38.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.17:47:38.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.17:47:38.16$vck44/vb=4,5 2006.257.17:47:38.16#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.17:47:38.16#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.17:47:38.16#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:38.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:38.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:38.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:38.22#ibcon#enter wrdev, iclass 25, count 2 2006.257.17:47:38.22#ibcon#first serial, iclass 25, count 2 2006.257.17:47:38.22#ibcon#enter sib2, iclass 25, count 2 2006.257.17:47:38.22#ibcon#flushed, iclass 25, count 2 2006.257.17:47:38.22#ibcon#about to write, iclass 25, count 2 2006.257.17:47:38.22#ibcon#wrote, iclass 25, count 2 2006.257.17:47:38.22#ibcon#about to read 3, iclass 25, count 2 2006.257.17:47:38.24#ibcon#read 3, iclass 25, count 2 2006.257.17:47:38.24#ibcon#about to read 4, iclass 25, count 2 2006.257.17:47:38.24#ibcon#read 4, iclass 25, count 2 2006.257.17:47:38.24#ibcon#about to read 5, iclass 25, count 2 2006.257.17:47:38.24#ibcon#read 5, iclass 25, count 2 2006.257.17:47:38.24#ibcon#about to read 6, iclass 25, count 2 2006.257.17:47:38.24#ibcon#read 6, iclass 25, count 2 2006.257.17:47:38.24#ibcon#end of sib2, iclass 25, count 2 2006.257.17:47:38.24#ibcon#*mode == 0, iclass 25, count 2 2006.257.17:47:38.24#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.17:47:38.24#ibcon#[27=AT04-05\r\n] 2006.257.17:47:38.24#ibcon#*before write, iclass 25, count 2 2006.257.17:47:38.24#ibcon#enter sib2, iclass 25, count 2 2006.257.17:47:38.24#ibcon#flushed, iclass 25, count 2 2006.257.17:47:38.24#ibcon#about to write, iclass 25, count 2 2006.257.17:47:38.24#ibcon#wrote, iclass 25, count 2 2006.257.17:47:38.24#ibcon#about to read 3, iclass 25, count 2 2006.257.17:47:38.27#ibcon#read 3, iclass 25, count 2 2006.257.17:47:38.27#ibcon#about to read 4, iclass 25, count 2 2006.257.17:47:38.27#ibcon#read 4, iclass 25, count 2 2006.257.17:47:38.27#ibcon#about to read 5, iclass 25, count 2 2006.257.17:47:38.27#ibcon#read 5, iclass 25, count 2 2006.257.17:47:38.27#ibcon#about to read 6, iclass 25, count 2 2006.257.17:47:38.27#ibcon#read 6, iclass 25, count 2 2006.257.17:47:38.27#ibcon#end of sib2, iclass 25, count 2 2006.257.17:47:38.27#ibcon#*after write, iclass 25, count 2 2006.257.17:47:38.27#ibcon#*before return 0, iclass 25, count 2 2006.257.17:47:38.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:38.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.17:47:38.27#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.17:47:38.27#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:38.27#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:38.39#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:38.39#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:38.39#ibcon#enter wrdev, iclass 25, count 0 2006.257.17:47:38.39#ibcon#first serial, iclass 25, count 0 2006.257.17:47:38.39#ibcon#enter sib2, iclass 25, count 0 2006.257.17:47:38.39#ibcon#flushed, iclass 25, count 0 2006.257.17:47:38.39#ibcon#about to write, iclass 25, count 0 2006.257.17:47:38.39#ibcon#wrote, iclass 25, count 0 2006.257.17:47:38.39#ibcon#about to read 3, iclass 25, count 0 2006.257.17:47:38.41#ibcon#read 3, iclass 25, count 0 2006.257.17:47:38.41#ibcon#about to read 4, iclass 25, count 0 2006.257.17:47:38.41#ibcon#read 4, iclass 25, count 0 2006.257.17:47:38.41#ibcon#about to read 5, iclass 25, count 0 2006.257.17:47:38.41#ibcon#read 5, iclass 25, count 0 2006.257.17:47:38.41#ibcon#about to read 6, iclass 25, count 0 2006.257.17:47:38.41#ibcon#read 6, iclass 25, count 0 2006.257.17:47:38.41#ibcon#end of sib2, iclass 25, count 0 2006.257.17:47:38.41#ibcon#*mode == 0, iclass 25, count 0 2006.257.17:47:38.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.17:47:38.41#ibcon#[27=USB\r\n] 2006.257.17:47:38.41#ibcon#*before write, iclass 25, count 0 2006.257.17:47:38.41#ibcon#enter sib2, iclass 25, count 0 2006.257.17:47:38.41#ibcon#flushed, iclass 25, count 0 2006.257.17:47:38.41#ibcon#about to write, iclass 25, count 0 2006.257.17:47:38.41#ibcon#wrote, iclass 25, count 0 2006.257.17:47:38.41#ibcon#about to read 3, iclass 25, count 0 2006.257.17:47:38.44#ibcon#read 3, iclass 25, count 0 2006.257.17:47:38.44#ibcon#about to read 4, iclass 25, count 0 2006.257.17:47:38.44#ibcon#read 4, iclass 25, count 0 2006.257.17:47:38.44#ibcon#about to read 5, iclass 25, count 0 2006.257.17:47:38.44#ibcon#read 5, iclass 25, count 0 2006.257.17:47:38.44#ibcon#about to read 6, iclass 25, count 0 2006.257.17:47:38.44#ibcon#read 6, iclass 25, count 0 2006.257.17:47:38.44#ibcon#end of sib2, iclass 25, count 0 2006.257.17:47:38.44#ibcon#*after write, iclass 25, count 0 2006.257.17:47:38.44#ibcon#*before return 0, iclass 25, count 0 2006.257.17:47:38.44#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:38.44#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.17:47:38.44#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.17:47:38.44#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.17:47:38.44$vck44/vblo=5,709.99 2006.257.17:47:38.44#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.17:47:38.44#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.17:47:38.44#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:38.44#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:38.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:38.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:38.44#ibcon#enter wrdev, iclass 27, count 0 2006.257.17:47:38.44#ibcon#first serial, iclass 27, count 0 2006.257.17:47:38.44#ibcon#enter sib2, iclass 27, count 0 2006.257.17:47:38.44#ibcon#flushed, iclass 27, count 0 2006.257.17:47:38.44#ibcon#about to write, iclass 27, count 0 2006.257.17:47:38.44#ibcon#wrote, iclass 27, count 0 2006.257.17:47:38.44#ibcon#about to read 3, iclass 27, count 0 2006.257.17:47:38.46#ibcon#read 3, iclass 27, count 0 2006.257.17:47:38.46#ibcon#about to read 4, iclass 27, count 0 2006.257.17:47:38.46#ibcon#read 4, iclass 27, count 0 2006.257.17:47:38.46#ibcon#about to read 5, iclass 27, count 0 2006.257.17:47:38.46#ibcon#read 5, iclass 27, count 0 2006.257.17:47:38.46#ibcon#about to read 6, iclass 27, count 0 2006.257.17:47:38.46#ibcon#read 6, iclass 27, count 0 2006.257.17:47:38.46#ibcon#end of sib2, iclass 27, count 0 2006.257.17:47:38.46#ibcon#*mode == 0, iclass 27, count 0 2006.257.17:47:38.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.17:47:38.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:47:38.46#ibcon#*before write, iclass 27, count 0 2006.257.17:47:38.46#ibcon#enter sib2, iclass 27, count 0 2006.257.17:47:38.46#ibcon#flushed, iclass 27, count 0 2006.257.17:47:38.46#ibcon#about to write, iclass 27, count 0 2006.257.17:47:38.46#ibcon#wrote, iclass 27, count 0 2006.257.17:47:38.46#ibcon#about to read 3, iclass 27, count 0 2006.257.17:47:38.50#ibcon#read 3, iclass 27, count 0 2006.257.17:47:38.50#ibcon#about to read 4, iclass 27, count 0 2006.257.17:47:38.50#ibcon#read 4, iclass 27, count 0 2006.257.17:47:38.50#ibcon#about to read 5, iclass 27, count 0 2006.257.17:47:38.50#ibcon#read 5, iclass 27, count 0 2006.257.17:47:38.50#ibcon#about to read 6, iclass 27, count 0 2006.257.17:47:38.50#ibcon#read 6, iclass 27, count 0 2006.257.17:47:38.50#ibcon#end of sib2, iclass 27, count 0 2006.257.17:47:38.50#ibcon#*after write, iclass 27, count 0 2006.257.17:47:38.50#ibcon#*before return 0, iclass 27, count 0 2006.257.17:47:38.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:38.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.17:47:38.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.17:47:38.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.17:47:38.50$vck44/vb=5,4 2006.257.17:47:38.50#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.17:47:38.50#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.17:47:38.50#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:38.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:38.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:38.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:38.56#ibcon#enter wrdev, iclass 29, count 2 2006.257.17:47:38.56#ibcon#first serial, iclass 29, count 2 2006.257.17:47:38.56#ibcon#enter sib2, iclass 29, count 2 2006.257.17:47:38.56#ibcon#flushed, iclass 29, count 2 2006.257.17:47:38.56#ibcon#about to write, iclass 29, count 2 2006.257.17:47:38.56#ibcon#wrote, iclass 29, count 2 2006.257.17:47:38.56#ibcon#about to read 3, iclass 29, count 2 2006.257.17:47:38.58#ibcon#read 3, iclass 29, count 2 2006.257.17:47:38.58#ibcon#about to read 4, iclass 29, count 2 2006.257.17:47:38.58#ibcon#read 4, iclass 29, count 2 2006.257.17:47:38.58#ibcon#about to read 5, iclass 29, count 2 2006.257.17:47:38.58#ibcon#read 5, iclass 29, count 2 2006.257.17:47:38.58#ibcon#about to read 6, iclass 29, count 2 2006.257.17:47:38.58#ibcon#read 6, iclass 29, count 2 2006.257.17:47:38.58#ibcon#end of sib2, iclass 29, count 2 2006.257.17:47:38.58#ibcon#*mode == 0, iclass 29, count 2 2006.257.17:47:38.58#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.17:47:38.58#ibcon#[27=AT05-04\r\n] 2006.257.17:47:38.58#ibcon#*before write, iclass 29, count 2 2006.257.17:47:38.58#ibcon#enter sib2, iclass 29, count 2 2006.257.17:47:38.58#ibcon#flushed, iclass 29, count 2 2006.257.17:47:38.58#ibcon#about to write, iclass 29, count 2 2006.257.17:47:38.58#ibcon#wrote, iclass 29, count 2 2006.257.17:47:38.58#ibcon#about to read 3, iclass 29, count 2 2006.257.17:47:38.61#ibcon#read 3, iclass 29, count 2 2006.257.17:47:38.61#ibcon#about to read 4, iclass 29, count 2 2006.257.17:47:38.61#ibcon#read 4, iclass 29, count 2 2006.257.17:47:38.61#ibcon#about to read 5, iclass 29, count 2 2006.257.17:47:38.61#ibcon#read 5, iclass 29, count 2 2006.257.17:47:38.61#ibcon#about to read 6, iclass 29, count 2 2006.257.17:47:38.61#ibcon#read 6, iclass 29, count 2 2006.257.17:47:38.61#ibcon#end of sib2, iclass 29, count 2 2006.257.17:47:38.61#ibcon#*after write, iclass 29, count 2 2006.257.17:47:38.61#ibcon#*before return 0, iclass 29, count 2 2006.257.17:47:38.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:38.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.17:47:38.61#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.17:47:38.61#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:38.61#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:38.73#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:38.73#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:38.73#ibcon#enter wrdev, iclass 29, count 0 2006.257.17:47:38.73#ibcon#first serial, iclass 29, count 0 2006.257.17:47:38.73#ibcon#enter sib2, iclass 29, count 0 2006.257.17:47:38.73#ibcon#flushed, iclass 29, count 0 2006.257.17:47:38.73#ibcon#about to write, iclass 29, count 0 2006.257.17:47:38.73#ibcon#wrote, iclass 29, count 0 2006.257.17:47:38.73#ibcon#about to read 3, iclass 29, count 0 2006.257.17:47:38.75#ibcon#read 3, iclass 29, count 0 2006.257.17:47:38.75#ibcon#about to read 4, iclass 29, count 0 2006.257.17:47:38.75#ibcon#read 4, iclass 29, count 0 2006.257.17:47:38.75#ibcon#about to read 5, iclass 29, count 0 2006.257.17:47:38.75#ibcon#read 5, iclass 29, count 0 2006.257.17:47:38.75#ibcon#about to read 6, iclass 29, count 0 2006.257.17:47:38.75#ibcon#read 6, iclass 29, count 0 2006.257.17:47:38.75#ibcon#end of sib2, iclass 29, count 0 2006.257.17:47:38.75#ibcon#*mode == 0, iclass 29, count 0 2006.257.17:47:38.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.17:47:38.75#ibcon#[27=USB\r\n] 2006.257.17:47:38.75#ibcon#*before write, iclass 29, count 0 2006.257.17:47:38.75#ibcon#enter sib2, iclass 29, count 0 2006.257.17:47:38.75#ibcon#flushed, iclass 29, count 0 2006.257.17:47:38.75#ibcon#about to write, iclass 29, count 0 2006.257.17:47:38.75#ibcon#wrote, iclass 29, count 0 2006.257.17:47:38.75#ibcon#about to read 3, iclass 29, count 0 2006.257.17:47:38.78#ibcon#read 3, iclass 29, count 0 2006.257.17:47:38.78#ibcon#about to read 4, iclass 29, count 0 2006.257.17:47:38.78#ibcon#read 4, iclass 29, count 0 2006.257.17:47:38.78#ibcon#about to read 5, iclass 29, count 0 2006.257.17:47:38.78#ibcon#read 5, iclass 29, count 0 2006.257.17:47:38.78#ibcon#about to read 6, iclass 29, count 0 2006.257.17:47:38.78#ibcon#read 6, iclass 29, count 0 2006.257.17:47:38.78#ibcon#end of sib2, iclass 29, count 0 2006.257.17:47:38.78#ibcon#*after write, iclass 29, count 0 2006.257.17:47:38.78#ibcon#*before return 0, iclass 29, count 0 2006.257.17:47:38.78#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:38.78#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.17:47:38.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.17:47:38.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.17:47:38.78$vck44/vblo=6,719.99 2006.257.17:47:38.78#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.17:47:38.78#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.17:47:38.78#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:38.78#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:38.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:38.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:38.78#ibcon#enter wrdev, iclass 31, count 0 2006.257.17:47:38.78#ibcon#first serial, iclass 31, count 0 2006.257.17:47:38.78#ibcon#enter sib2, iclass 31, count 0 2006.257.17:47:38.78#ibcon#flushed, iclass 31, count 0 2006.257.17:47:38.78#ibcon#about to write, iclass 31, count 0 2006.257.17:47:38.78#ibcon#wrote, iclass 31, count 0 2006.257.17:47:38.78#ibcon#about to read 3, iclass 31, count 0 2006.257.17:47:38.80#ibcon#read 3, iclass 31, count 0 2006.257.17:47:38.80#ibcon#about to read 4, iclass 31, count 0 2006.257.17:47:38.80#ibcon#read 4, iclass 31, count 0 2006.257.17:47:38.80#ibcon#about to read 5, iclass 31, count 0 2006.257.17:47:38.80#ibcon#read 5, iclass 31, count 0 2006.257.17:47:38.80#ibcon#about to read 6, iclass 31, count 0 2006.257.17:47:38.80#ibcon#read 6, iclass 31, count 0 2006.257.17:47:38.80#ibcon#end of sib2, iclass 31, count 0 2006.257.17:47:38.80#ibcon#*mode == 0, iclass 31, count 0 2006.257.17:47:38.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.17:47:38.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:47:38.80#ibcon#*before write, iclass 31, count 0 2006.257.17:47:38.80#ibcon#enter sib2, iclass 31, count 0 2006.257.17:47:38.80#ibcon#flushed, iclass 31, count 0 2006.257.17:47:38.80#ibcon#about to write, iclass 31, count 0 2006.257.17:47:38.80#ibcon#wrote, iclass 31, count 0 2006.257.17:47:38.80#ibcon#about to read 3, iclass 31, count 0 2006.257.17:47:38.84#ibcon#read 3, iclass 31, count 0 2006.257.17:47:38.84#ibcon#about to read 4, iclass 31, count 0 2006.257.17:47:38.84#ibcon#read 4, iclass 31, count 0 2006.257.17:47:38.84#ibcon#about to read 5, iclass 31, count 0 2006.257.17:47:38.84#ibcon#read 5, iclass 31, count 0 2006.257.17:47:38.84#ibcon#about to read 6, iclass 31, count 0 2006.257.17:47:38.84#ibcon#read 6, iclass 31, count 0 2006.257.17:47:38.84#ibcon#end of sib2, iclass 31, count 0 2006.257.17:47:38.84#ibcon#*after write, iclass 31, count 0 2006.257.17:47:38.84#ibcon#*before return 0, iclass 31, count 0 2006.257.17:47:38.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:38.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.17:47:38.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.17:47:38.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.17:47:38.84$vck44/vb=6,4 2006.257.17:47:38.84#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.17:47:38.84#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.17:47:38.84#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:38.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:38.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:38.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:38.90#ibcon#enter wrdev, iclass 33, count 2 2006.257.17:47:38.90#ibcon#first serial, iclass 33, count 2 2006.257.17:47:38.90#ibcon#enter sib2, iclass 33, count 2 2006.257.17:47:38.90#ibcon#flushed, iclass 33, count 2 2006.257.17:47:38.90#ibcon#about to write, iclass 33, count 2 2006.257.17:47:38.90#ibcon#wrote, iclass 33, count 2 2006.257.17:47:38.90#ibcon#about to read 3, iclass 33, count 2 2006.257.17:47:38.92#ibcon#read 3, iclass 33, count 2 2006.257.17:47:38.92#ibcon#about to read 4, iclass 33, count 2 2006.257.17:47:38.92#ibcon#read 4, iclass 33, count 2 2006.257.17:47:38.92#ibcon#about to read 5, iclass 33, count 2 2006.257.17:47:38.92#ibcon#read 5, iclass 33, count 2 2006.257.17:47:38.92#ibcon#about to read 6, iclass 33, count 2 2006.257.17:47:38.92#ibcon#read 6, iclass 33, count 2 2006.257.17:47:38.92#ibcon#end of sib2, iclass 33, count 2 2006.257.17:47:38.92#ibcon#*mode == 0, iclass 33, count 2 2006.257.17:47:38.92#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.17:47:38.92#ibcon#[27=AT06-04\r\n] 2006.257.17:47:38.92#ibcon#*before write, iclass 33, count 2 2006.257.17:47:38.92#ibcon#enter sib2, iclass 33, count 2 2006.257.17:47:38.92#ibcon#flushed, iclass 33, count 2 2006.257.17:47:38.92#ibcon#about to write, iclass 33, count 2 2006.257.17:47:38.92#ibcon#wrote, iclass 33, count 2 2006.257.17:47:38.92#ibcon#about to read 3, iclass 33, count 2 2006.257.17:47:38.95#ibcon#read 3, iclass 33, count 2 2006.257.17:47:38.95#ibcon#about to read 4, iclass 33, count 2 2006.257.17:47:38.95#ibcon#read 4, iclass 33, count 2 2006.257.17:47:38.95#ibcon#about to read 5, iclass 33, count 2 2006.257.17:47:38.95#ibcon#read 5, iclass 33, count 2 2006.257.17:47:38.95#ibcon#about to read 6, iclass 33, count 2 2006.257.17:47:38.95#ibcon#read 6, iclass 33, count 2 2006.257.17:47:38.95#ibcon#end of sib2, iclass 33, count 2 2006.257.17:47:38.95#ibcon#*after write, iclass 33, count 2 2006.257.17:47:38.95#ibcon#*before return 0, iclass 33, count 2 2006.257.17:47:38.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:38.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.17:47:38.95#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.17:47:38.95#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:38.95#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:39.07#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:39.07#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:39.07#ibcon#enter wrdev, iclass 33, count 0 2006.257.17:47:39.07#ibcon#first serial, iclass 33, count 0 2006.257.17:47:39.07#ibcon#enter sib2, iclass 33, count 0 2006.257.17:47:39.07#ibcon#flushed, iclass 33, count 0 2006.257.17:47:39.07#ibcon#about to write, iclass 33, count 0 2006.257.17:47:39.07#ibcon#wrote, iclass 33, count 0 2006.257.17:47:39.07#ibcon#about to read 3, iclass 33, count 0 2006.257.17:47:39.09#ibcon#read 3, iclass 33, count 0 2006.257.17:47:39.09#ibcon#about to read 4, iclass 33, count 0 2006.257.17:47:39.09#ibcon#read 4, iclass 33, count 0 2006.257.17:47:39.09#ibcon#about to read 5, iclass 33, count 0 2006.257.17:47:39.09#ibcon#read 5, iclass 33, count 0 2006.257.17:47:39.09#ibcon#about to read 6, iclass 33, count 0 2006.257.17:47:39.09#ibcon#read 6, iclass 33, count 0 2006.257.17:47:39.09#ibcon#end of sib2, iclass 33, count 0 2006.257.17:47:39.09#ibcon#*mode == 0, iclass 33, count 0 2006.257.17:47:39.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.17:47:39.09#ibcon#[27=USB\r\n] 2006.257.17:47:39.09#ibcon#*before write, iclass 33, count 0 2006.257.17:47:39.09#ibcon#enter sib2, iclass 33, count 0 2006.257.17:47:39.09#ibcon#flushed, iclass 33, count 0 2006.257.17:47:39.09#ibcon#about to write, iclass 33, count 0 2006.257.17:47:39.09#ibcon#wrote, iclass 33, count 0 2006.257.17:47:39.09#ibcon#about to read 3, iclass 33, count 0 2006.257.17:47:39.12#ibcon#read 3, iclass 33, count 0 2006.257.17:47:39.12#ibcon#about to read 4, iclass 33, count 0 2006.257.17:47:39.12#ibcon#read 4, iclass 33, count 0 2006.257.17:47:39.12#ibcon#about to read 5, iclass 33, count 0 2006.257.17:47:39.12#ibcon#read 5, iclass 33, count 0 2006.257.17:47:39.12#ibcon#about to read 6, iclass 33, count 0 2006.257.17:47:39.12#ibcon#read 6, iclass 33, count 0 2006.257.17:47:39.12#ibcon#end of sib2, iclass 33, count 0 2006.257.17:47:39.12#ibcon#*after write, iclass 33, count 0 2006.257.17:47:39.12#ibcon#*before return 0, iclass 33, count 0 2006.257.17:47:39.12#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:39.12#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.17:47:39.12#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.17:47:39.12#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.17:47:39.12$vck44/vblo=7,734.99 2006.257.17:47:39.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.17:47:39.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.17:47:39.12#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:39.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:39.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:39.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:39.12#ibcon#enter wrdev, iclass 35, count 0 2006.257.17:47:39.12#ibcon#first serial, iclass 35, count 0 2006.257.17:47:39.12#ibcon#enter sib2, iclass 35, count 0 2006.257.17:47:39.12#ibcon#flushed, iclass 35, count 0 2006.257.17:47:39.12#ibcon#about to write, iclass 35, count 0 2006.257.17:47:39.12#ibcon#wrote, iclass 35, count 0 2006.257.17:47:39.12#ibcon#about to read 3, iclass 35, count 0 2006.257.17:47:39.14#ibcon#read 3, iclass 35, count 0 2006.257.17:47:39.14#ibcon#about to read 4, iclass 35, count 0 2006.257.17:47:39.14#ibcon#read 4, iclass 35, count 0 2006.257.17:47:39.14#ibcon#about to read 5, iclass 35, count 0 2006.257.17:47:39.14#ibcon#read 5, iclass 35, count 0 2006.257.17:47:39.14#ibcon#about to read 6, iclass 35, count 0 2006.257.17:47:39.14#ibcon#read 6, iclass 35, count 0 2006.257.17:47:39.14#ibcon#end of sib2, iclass 35, count 0 2006.257.17:47:39.14#ibcon#*mode == 0, iclass 35, count 0 2006.257.17:47:39.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.17:47:39.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:47:39.14#ibcon#*before write, iclass 35, count 0 2006.257.17:47:39.14#ibcon#enter sib2, iclass 35, count 0 2006.257.17:47:39.14#ibcon#flushed, iclass 35, count 0 2006.257.17:47:39.14#ibcon#about to write, iclass 35, count 0 2006.257.17:47:39.14#ibcon#wrote, iclass 35, count 0 2006.257.17:47:39.14#ibcon#about to read 3, iclass 35, count 0 2006.257.17:47:39.18#ibcon#read 3, iclass 35, count 0 2006.257.17:47:39.18#ibcon#about to read 4, iclass 35, count 0 2006.257.17:47:39.18#ibcon#read 4, iclass 35, count 0 2006.257.17:47:39.18#ibcon#about to read 5, iclass 35, count 0 2006.257.17:47:39.18#ibcon#read 5, iclass 35, count 0 2006.257.17:47:39.18#ibcon#about to read 6, iclass 35, count 0 2006.257.17:47:39.18#ibcon#read 6, iclass 35, count 0 2006.257.17:47:39.18#ibcon#end of sib2, iclass 35, count 0 2006.257.17:47:39.18#ibcon#*after write, iclass 35, count 0 2006.257.17:47:39.18#ibcon#*before return 0, iclass 35, count 0 2006.257.17:47:39.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:39.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.17:47:39.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.17:47:39.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.17:47:39.18$vck44/vb=7,4 2006.257.17:47:39.18#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.17:47:39.18#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.17:47:39.18#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:39.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:39.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:39.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:39.24#ibcon#enter wrdev, iclass 37, count 2 2006.257.17:47:39.24#ibcon#first serial, iclass 37, count 2 2006.257.17:47:39.24#ibcon#enter sib2, iclass 37, count 2 2006.257.17:47:39.24#ibcon#flushed, iclass 37, count 2 2006.257.17:47:39.24#ibcon#about to write, iclass 37, count 2 2006.257.17:47:39.24#ibcon#wrote, iclass 37, count 2 2006.257.17:47:39.24#ibcon#about to read 3, iclass 37, count 2 2006.257.17:47:39.26#ibcon#read 3, iclass 37, count 2 2006.257.17:47:39.26#ibcon#about to read 4, iclass 37, count 2 2006.257.17:47:39.26#ibcon#read 4, iclass 37, count 2 2006.257.17:47:39.26#ibcon#about to read 5, iclass 37, count 2 2006.257.17:47:39.26#ibcon#read 5, iclass 37, count 2 2006.257.17:47:39.26#ibcon#about to read 6, iclass 37, count 2 2006.257.17:47:39.26#ibcon#read 6, iclass 37, count 2 2006.257.17:47:39.26#ibcon#end of sib2, iclass 37, count 2 2006.257.17:47:39.26#ibcon#*mode == 0, iclass 37, count 2 2006.257.17:47:39.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.17:47:39.26#ibcon#[27=AT07-04\r\n] 2006.257.17:47:39.26#ibcon#*before write, iclass 37, count 2 2006.257.17:47:39.26#ibcon#enter sib2, iclass 37, count 2 2006.257.17:47:39.26#ibcon#flushed, iclass 37, count 2 2006.257.17:47:39.26#ibcon#about to write, iclass 37, count 2 2006.257.17:47:39.26#ibcon#wrote, iclass 37, count 2 2006.257.17:47:39.26#ibcon#about to read 3, iclass 37, count 2 2006.257.17:47:39.29#ibcon#read 3, iclass 37, count 2 2006.257.17:47:39.29#ibcon#about to read 4, iclass 37, count 2 2006.257.17:47:39.29#ibcon#read 4, iclass 37, count 2 2006.257.17:47:39.29#ibcon#about to read 5, iclass 37, count 2 2006.257.17:47:39.29#ibcon#read 5, iclass 37, count 2 2006.257.17:47:39.29#ibcon#about to read 6, iclass 37, count 2 2006.257.17:47:39.29#ibcon#read 6, iclass 37, count 2 2006.257.17:47:39.29#ibcon#end of sib2, iclass 37, count 2 2006.257.17:47:39.29#ibcon#*after write, iclass 37, count 2 2006.257.17:47:39.29#ibcon#*before return 0, iclass 37, count 2 2006.257.17:47:39.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:39.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.17:47:39.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.17:47:39.29#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:39.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:39.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:39.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:39.41#ibcon#enter wrdev, iclass 37, count 0 2006.257.17:47:39.41#ibcon#first serial, iclass 37, count 0 2006.257.17:47:39.41#ibcon#enter sib2, iclass 37, count 0 2006.257.17:47:39.41#ibcon#flushed, iclass 37, count 0 2006.257.17:47:39.41#ibcon#about to write, iclass 37, count 0 2006.257.17:47:39.41#ibcon#wrote, iclass 37, count 0 2006.257.17:47:39.41#ibcon#about to read 3, iclass 37, count 0 2006.257.17:47:39.43#ibcon#read 3, iclass 37, count 0 2006.257.17:47:39.43#ibcon#about to read 4, iclass 37, count 0 2006.257.17:47:39.43#ibcon#read 4, iclass 37, count 0 2006.257.17:47:39.43#ibcon#about to read 5, iclass 37, count 0 2006.257.17:47:39.43#ibcon#read 5, iclass 37, count 0 2006.257.17:47:39.43#ibcon#about to read 6, iclass 37, count 0 2006.257.17:47:39.43#ibcon#read 6, iclass 37, count 0 2006.257.17:47:39.43#ibcon#end of sib2, iclass 37, count 0 2006.257.17:47:39.43#ibcon#*mode == 0, iclass 37, count 0 2006.257.17:47:39.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.17:47:39.43#ibcon#[27=USB\r\n] 2006.257.17:47:39.43#ibcon#*before write, iclass 37, count 0 2006.257.17:47:39.43#ibcon#enter sib2, iclass 37, count 0 2006.257.17:47:39.43#ibcon#flushed, iclass 37, count 0 2006.257.17:47:39.43#ibcon#about to write, iclass 37, count 0 2006.257.17:47:39.43#ibcon#wrote, iclass 37, count 0 2006.257.17:47:39.43#ibcon#about to read 3, iclass 37, count 0 2006.257.17:47:39.46#ibcon#read 3, iclass 37, count 0 2006.257.17:47:39.46#ibcon#about to read 4, iclass 37, count 0 2006.257.17:47:39.46#ibcon#read 4, iclass 37, count 0 2006.257.17:47:39.46#ibcon#about to read 5, iclass 37, count 0 2006.257.17:47:39.46#ibcon#read 5, iclass 37, count 0 2006.257.17:47:39.46#ibcon#about to read 6, iclass 37, count 0 2006.257.17:47:39.46#ibcon#read 6, iclass 37, count 0 2006.257.17:47:39.46#ibcon#end of sib2, iclass 37, count 0 2006.257.17:47:39.46#ibcon#*after write, iclass 37, count 0 2006.257.17:47:39.46#ibcon#*before return 0, iclass 37, count 0 2006.257.17:47:39.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:39.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.17:47:39.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.17:47:39.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.17:47:39.46$vck44/vblo=8,744.99 2006.257.17:47:39.46#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.17:47:39.46#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.17:47:39.46#ibcon#ireg 17 cls_cnt 0 2006.257.17:47:39.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:39.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:39.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:39.46#ibcon#enter wrdev, iclass 39, count 0 2006.257.17:47:39.46#ibcon#first serial, iclass 39, count 0 2006.257.17:47:39.46#ibcon#enter sib2, iclass 39, count 0 2006.257.17:47:39.46#ibcon#flushed, iclass 39, count 0 2006.257.17:47:39.46#ibcon#about to write, iclass 39, count 0 2006.257.17:47:39.46#ibcon#wrote, iclass 39, count 0 2006.257.17:47:39.46#ibcon#about to read 3, iclass 39, count 0 2006.257.17:47:39.48#ibcon#read 3, iclass 39, count 0 2006.257.17:47:39.48#ibcon#about to read 4, iclass 39, count 0 2006.257.17:47:39.48#ibcon#read 4, iclass 39, count 0 2006.257.17:47:39.48#ibcon#about to read 5, iclass 39, count 0 2006.257.17:47:39.48#ibcon#read 5, iclass 39, count 0 2006.257.17:47:39.48#ibcon#about to read 6, iclass 39, count 0 2006.257.17:47:39.48#ibcon#read 6, iclass 39, count 0 2006.257.17:47:39.48#ibcon#end of sib2, iclass 39, count 0 2006.257.17:47:39.48#ibcon#*mode == 0, iclass 39, count 0 2006.257.17:47:39.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.17:47:39.48#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:47:39.48#ibcon#*before write, iclass 39, count 0 2006.257.17:47:39.48#ibcon#enter sib2, iclass 39, count 0 2006.257.17:47:39.48#ibcon#flushed, iclass 39, count 0 2006.257.17:47:39.48#ibcon#about to write, iclass 39, count 0 2006.257.17:47:39.48#ibcon#wrote, iclass 39, count 0 2006.257.17:47:39.48#ibcon#about to read 3, iclass 39, count 0 2006.257.17:47:39.52#ibcon#read 3, iclass 39, count 0 2006.257.17:47:39.52#ibcon#about to read 4, iclass 39, count 0 2006.257.17:47:39.52#ibcon#read 4, iclass 39, count 0 2006.257.17:47:39.52#ibcon#about to read 5, iclass 39, count 0 2006.257.17:47:39.52#ibcon#read 5, iclass 39, count 0 2006.257.17:47:39.52#ibcon#about to read 6, iclass 39, count 0 2006.257.17:47:39.52#ibcon#read 6, iclass 39, count 0 2006.257.17:47:39.52#ibcon#end of sib2, iclass 39, count 0 2006.257.17:47:39.52#ibcon#*after write, iclass 39, count 0 2006.257.17:47:39.52#ibcon#*before return 0, iclass 39, count 0 2006.257.17:47:39.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:39.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.17:47:39.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.17:47:39.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.17:47:39.52$vck44/vb=8,4 2006.257.17:47:39.52#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.17:47:39.52#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.17:47:39.52#ibcon#ireg 11 cls_cnt 2 2006.257.17:47:39.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:39.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:39.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:39.58#ibcon#enter wrdev, iclass 3, count 2 2006.257.17:47:39.58#ibcon#first serial, iclass 3, count 2 2006.257.17:47:39.58#ibcon#enter sib2, iclass 3, count 2 2006.257.17:47:39.58#ibcon#flushed, iclass 3, count 2 2006.257.17:47:39.58#ibcon#about to write, iclass 3, count 2 2006.257.17:47:39.58#ibcon#wrote, iclass 3, count 2 2006.257.17:47:39.58#ibcon#about to read 3, iclass 3, count 2 2006.257.17:47:39.60#ibcon#read 3, iclass 3, count 2 2006.257.17:47:39.60#ibcon#about to read 4, iclass 3, count 2 2006.257.17:47:39.60#ibcon#read 4, iclass 3, count 2 2006.257.17:47:39.60#ibcon#about to read 5, iclass 3, count 2 2006.257.17:47:39.60#ibcon#read 5, iclass 3, count 2 2006.257.17:47:39.60#ibcon#about to read 6, iclass 3, count 2 2006.257.17:47:39.60#ibcon#read 6, iclass 3, count 2 2006.257.17:47:39.60#ibcon#end of sib2, iclass 3, count 2 2006.257.17:47:39.60#ibcon#*mode == 0, iclass 3, count 2 2006.257.17:47:39.60#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.17:47:39.60#ibcon#[27=AT08-04\r\n] 2006.257.17:47:39.60#ibcon#*before write, iclass 3, count 2 2006.257.17:47:39.60#ibcon#enter sib2, iclass 3, count 2 2006.257.17:47:39.60#ibcon#flushed, iclass 3, count 2 2006.257.17:47:39.60#ibcon#about to write, iclass 3, count 2 2006.257.17:47:39.60#ibcon#wrote, iclass 3, count 2 2006.257.17:47:39.60#ibcon#about to read 3, iclass 3, count 2 2006.257.17:47:39.63#ibcon#read 3, iclass 3, count 2 2006.257.17:47:39.63#ibcon#about to read 4, iclass 3, count 2 2006.257.17:47:39.63#ibcon#read 4, iclass 3, count 2 2006.257.17:47:39.63#ibcon#about to read 5, iclass 3, count 2 2006.257.17:47:39.63#ibcon#read 5, iclass 3, count 2 2006.257.17:47:39.63#ibcon#about to read 6, iclass 3, count 2 2006.257.17:47:39.63#ibcon#read 6, iclass 3, count 2 2006.257.17:47:39.63#ibcon#end of sib2, iclass 3, count 2 2006.257.17:47:39.63#ibcon#*after write, iclass 3, count 2 2006.257.17:47:39.63#ibcon#*before return 0, iclass 3, count 2 2006.257.17:47:39.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:39.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.17:47:39.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.17:47:39.63#ibcon#ireg 7 cls_cnt 0 2006.257.17:47:39.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:39.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:39.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:39.75#ibcon#enter wrdev, iclass 3, count 0 2006.257.17:47:39.75#ibcon#first serial, iclass 3, count 0 2006.257.17:47:39.75#ibcon#enter sib2, iclass 3, count 0 2006.257.17:47:39.75#ibcon#flushed, iclass 3, count 0 2006.257.17:47:39.75#ibcon#about to write, iclass 3, count 0 2006.257.17:47:39.75#ibcon#wrote, iclass 3, count 0 2006.257.17:47:39.75#ibcon#about to read 3, iclass 3, count 0 2006.257.17:47:39.77#ibcon#read 3, iclass 3, count 0 2006.257.17:47:39.77#ibcon#about to read 4, iclass 3, count 0 2006.257.17:47:39.77#ibcon#read 4, iclass 3, count 0 2006.257.17:47:39.77#ibcon#about to read 5, iclass 3, count 0 2006.257.17:47:39.77#ibcon#read 5, iclass 3, count 0 2006.257.17:47:39.77#ibcon#about to read 6, iclass 3, count 0 2006.257.17:47:39.77#ibcon#read 6, iclass 3, count 0 2006.257.17:47:39.77#ibcon#end of sib2, iclass 3, count 0 2006.257.17:47:39.77#ibcon#*mode == 0, iclass 3, count 0 2006.257.17:47:39.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.17:47:39.77#ibcon#[27=USB\r\n] 2006.257.17:47:39.77#ibcon#*before write, iclass 3, count 0 2006.257.17:47:39.77#ibcon#enter sib2, iclass 3, count 0 2006.257.17:47:39.77#ibcon#flushed, iclass 3, count 0 2006.257.17:47:39.77#ibcon#about to write, iclass 3, count 0 2006.257.17:47:39.77#ibcon#wrote, iclass 3, count 0 2006.257.17:47:39.77#ibcon#about to read 3, iclass 3, count 0 2006.257.17:47:39.80#ibcon#read 3, iclass 3, count 0 2006.257.17:47:39.80#ibcon#about to read 4, iclass 3, count 0 2006.257.17:47:39.80#ibcon#read 4, iclass 3, count 0 2006.257.17:47:39.80#ibcon#about to read 5, iclass 3, count 0 2006.257.17:47:39.80#ibcon#read 5, iclass 3, count 0 2006.257.17:47:39.80#ibcon#about to read 6, iclass 3, count 0 2006.257.17:47:39.80#ibcon#read 6, iclass 3, count 0 2006.257.17:47:39.80#ibcon#end of sib2, iclass 3, count 0 2006.257.17:47:39.80#ibcon#*after write, iclass 3, count 0 2006.257.17:47:39.80#ibcon#*before return 0, iclass 3, count 0 2006.257.17:47:39.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:39.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.17:47:39.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.17:47:39.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.17:47:39.80$vck44/vabw=wide 2006.257.17:47:39.80#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.17:47:39.80#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.17:47:39.80#ibcon#ireg 8 cls_cnt 0 2006.257.17:47:39.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:39.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:39.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:39.80#ibcon#enter wrdev, iclass 5, count 0 2006.257.17:47:39.80#ibcon#first serial, iclass 5, count 0 2006.257.17:47:39.80#ibcon#enter sib2, iclass 5, count 0 2006.257.17:47:39.80#ibcon#flushed, iclass 5, count 0 2006.257.17:47:39.80#ibcon#about to write, iclass 5, count 0 2006.257.17:47:39.80#ibcon#wrote, iclass 5, count 0 2006.257.17:47:39.80#ibcon#about to read 3, iclass 5, count 0 2006.257.17:47:39.82#ibcon#read 3, iclass 5, count 0 2006.257.17:47:39.82#ibcon#about to read 4, iclass 5, count 0 2006.257.17:47:39.82#ibcon#read 4, iclass 5, count 0 2006.257.17:47:39.82#ibcon#about to read 5, iclass 5, count 0 2006.257.17:47:39.82#ibcon#read 5, iclass 5, count 0 2006.257.17:47:39.82#ibcon#about to read 6, iclass 5, count 0 2006.257.17:47:39.82#ibcon#read 6, iclass 5, count 0 2006.257.17:47:39.82#ibcon#end of sib2, iclass 5, count 0 2006.257.17:47:39.82#ibcon#*mode == 0, iclass 5, count 0 2006.257.17:47:39.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.17:47:39.82#ibcon#[25=BW32\r\n] 2006.257.17:47:39.82#ibcon#*before write, iclass 5, count 0 2006.257.17:47:39.82#ibcon#enter sib2, iclass 5, count 0 2006.257.17:47:39.82#ibcon#flushed, iclass 5, count 0 2006.257.17:47:39.82#ibcon#about to write, iclass 5, count 0 2006.257.17:47:39.82#ibcon#wrote, iclass 5, count 0 2006.257.17:47:39.82#ibcon#about to read 3, iclass 5, count 0 2006.257.17:47:39.85#ibcon#read 3, iclass 5, count 0 2006.257.17:47:39.85#ibcon#about to read 4, iclass 5, count 0 2006.257.17:47:39.85#ibcon#read 4, iclass 5, count 0 2006.257.17:47:39.85#ibcon#about to read 5, iclass 5, count 0 2006.257.17:47:39.85#ibcon#read 5, iclass 5, count 0 2006.257.17:47:39.85#ibcon#about to read 6, iclass 5, count 0 2006.257.17:47:39.85#ibcon#read 6, iclass 5, count 0 2006.257.17:47:39.85#ibcon#end of sib2, iclass 5, count 0 2006.257.17:47:39.85#ibcon#*after write, iclass 5, count 0 2006.257.17:47:39.85#ibcon#*before return 0, iclass 5, count 0 2006.257.17:47:39.85#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:39.85#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.17:47:39.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.17:47:39.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.17:47:39.85$vck44/vbbw=wide 2006.257.17:47:39.85#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.17:47:39.85#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.17:47:39.85#ibcon#ireg 8 cls_cnt 0 2006.257.17:47:39.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:47:39.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:47:39.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:47:39.92#ibcon#enter wrdev, iclass 7, count 0 2006.257.17:47:39.92#ibcon#first serial, iclass 7, count 0 2006.257.17:47:39.92#ibcon#enter sib2, iclass 7, count 0 2006.257.17:47:39.92#ibcon#flushed, iclass 7, count 0 2006.257.17:47:39.92#ibcon#about to write, iclass 7, count 0 2006.257.17:47:39.92#ibcon#wrote, iclass 7, count 0 2006.257.17:47:39.92#ibcon#about to read 3, iclass 7, count 0 2006.257.17:47:39.94#ibcon#read 3, iclass 7, count 0 2006.257.17:47:39.94#ibcon#about to read 4, iclass 7, count 0 2006.257.17:47:39.94#ibcon#read 4, iclass 7, count 0 2006.257.17:47:39.94#ibcon#about to read 5, iclass 7, count 0 2006.257.17:47:39.94#ibcon#read 5, iclass 7, count 0 2006.257.17:47:39.94#ibcon#about to read 6, iclass 7, count 0 2006.257.17:47:39.94#ibcon#read 6, iclass 7, count 0 2006.257.17:47:39.94#ibcon#end of sib2, iclass 7, count 0 2006.257.17:47:39.94#ibcon#*mode == 0, iclass 7, count 0 2006.257.17:47:39.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.17:47:39.94#ibcon#[27=BW32\r\n] 2006.257.17:47:39.94#ibcon#*before write, iclass 7, count 0 2006.257.17:47:39.94#ibcon#enter sib2, iclass 7, count 0 2006.257.17:47:39.94#ibcon#flushed, iclass 7, count 0 2006.257.17:47:39.94#ibcon#about to write, iclass 7, count 0 2006.257.17:47:39.94#ibcon#wrote, iclass 7, count 0 2006.257.17:47:39.94#ibcon#about to read 3, iclass 7, count 0 2006.257.17:47:39.97#ibcon#read 3, iclass 7, count 0 2006.257.17:47:39.97#ibcon#about to read 4, iclass 7, count 0 2006.257.17:47:39.97#ibcon#read 4, iclass 7, count 0 2006.257.17:47:39.97#ibcon#about to read 5, iclass 7, count 0 2006.257.17:47:39.97#ibcon#read 5, iclass 7, count 0 2006.257.17:47:39.97#ibcon#about to read 6, iclass 7, count 0 2006.257.17:47:39.97#ibcon#read 6, iclass 7, count 0 2006.257.17:47:39.97#ibcon#end of sib2, iclass 7, count 0 2006.257.17:47:39.97#ibcon#*after write, iclass 7, count 0 2006.257.17:47:39.97#ibcon#*before return 0, iclass 7, count 0 2006.257.17:47:39.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:47:39.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.17:47:39.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.17:47:39.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.17:47:39.97$setupk4/ifdk4 2006.257.17:47:39.97$ifdk4/lo= 2006.257.17:47:39.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:47:39.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:47:39.97$ifdk4/patch= 2006.257.17:47:39.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:47:39.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:47:39.97$setupk4/!*+20s 2006.257.17:47:42.27#abcon#<5=/15 1.6 3.9 17.30 971014.2\r\n> 2006.257.17:47:42.29#abcon#{5=INTERFACE CLEAR} 2006.257.17:47:42.35#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:47:52.44#abcon#<5=/15 1.6 3.9 17.30 971014.2\r\n> 2006.257.17:47:52.46#abcon#{5=INTERFACE CLEAR} 2006.257.17:47:52.52#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:47:54.48$setupk4/"tpicd 2006.257.17:47:54.48$setupk4/echo=off 2006.257.17:47:54.48$setupk4/xlog=off 2006.257.17:47:54.48:!2006.257.17:49:59 2006.257.17:48:09.14#trakl#Source acquired 2006.257.17:48:09.14#flagr#flagr/antenna,acquired 2006.257.17:49:59.00:preob 2006.257.17:49:59.14/onsource/TRACKING 2006.257.17:49:59.14:!2006.257.17:50:09 2006.257.17:50:09.00:"tape 2006.257.17:50:09.00:"st=record 2006.257.17:50:09.00:data_valid=on 2006.257.17:50:09.00:midob 2006.257.17:50:09.14/onsource/TRACKING 2006.257.17:50:09.14/wx/17.28,1014.2,97 2006.257.17:50:09.36/cable/+6.4836E-03 2006.257.17:50:10.45/va/01,08,usb,yes,30,32 2006.257.17:50:10.45/va/02,07,usb,yes,32,33 2006.257.17:50:10.45/va/03,08,usb,yes,29,31 2006.257.17:50:10.45/va/04,07,usb,yes,33,35 2006.257.17:50:10.45/va/05,04,usb,yes,30,30 2006.257.17:50:10.45/va/06,04,usb,yes,33,33 2006.257.17:50:10.45/va/07,04,usb,yes,34,35 2006.257.17:50:10.45/va/08,04,usb,yes,29,35 2006.257.17:50:10.68/valo/01,524.99,yes,locked 2006.257.17:50:10.68/valo/02,534.99,yes,locked 2006.257.17:50:10.68/valo/03,564.99,yes,locked 2006.257.17:50:10.68/valo/04,624.99,yes,locked 2006.257.17:50:10.68/valo/05,734.99,yes,locked 2006.257.17:50:10.68/valo/06,814.99,yes,locked 2006.257.17:50:10.68/valo/07,864.99,yes,locked 2006.257.17:50:10.68/valo/08,884.99,yes,locked 2006.257.17:50:11.77/vb/01,04,usb,yes,30,28 2006.257.17:50:11.77/vb/02,05,usb,yes,29,29 2006.257.17:50:11.77/vb/03,04,usb,yes,30,33 2006.257.17:50:11.77/vb/04,05,usb,yes,30,29 2006.257.17:50:11.77/vb/05,04,usb,yes,26,29 2006.257.17:50:11.77/vb/06,04,usb,yes,31,27 2006.257.17:50:11.77/vb/07,04,usb,yes,31,30 2006.257.17:50:11.77/vb/08,04,usb,yes,28,31 2006.257.17:50:12.00/vblo/01,629.99,yes,locked 2006.257.17:50:12.00/vblo/02,634.99,yes,locked 2006.257.17:50:12.00/vblo/03,649.99,yes,locked 2006.257.17:50:12.00/vblo/04,679.99,yes,locked 2006.257.17:50:12.00/vblo/05,709.99,yes,locked 2006.257.17:50:12.00/vblo/06,719.99,yes,locked 2006.257.17:50:12.00/vblo/07,734.99,yes,locked 2006.257.17:50:12.00/vblo/08,744.99,yes,locked 2006.257.17:50:12.15/vabw/8 2006.257.17:50:12.30/vbbw/8 2006.257.17:50:12.39/xfe/off,on,15.0 2006.257.17:50:12.76/ifatt/23,28,28,28 2006.257.17:50:13.08/fmout-gps/S +4.50E-07 2006.257.17:50:13.12:!2006.257.17:50:59 2006.257.17:50:59.01:data_valid=off 2006.257.17:50:59.01:"et 2006.257.17:50:59.01:!+3s 2006.257.17:51:02.02:"tape 2006.257.17:51:02.02:postob 2006.257.17:51:02.24/cable/+6.4851E-03 2006.257.17:51:02.24/wx/17.27,1014.3,97 2006.257.17:51:03.07/fmout-gps/S +4.50E-07 2006.257.17:51:03.07:scan_name=257-1753,jd0609,40 2006.257.17:51:03.07:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.257.17:51:04.14#flagr#flagr/antenna,new-source 2006.257.17:51:04.14:checkk5 2006.257.17:51:04.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:51:04.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:51:05.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:51:05.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:51:05.84/chk_obsdata//k5ts1/T2571750??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.17:51:06.17/chk_obsdata//k5ts2/T2571750??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.17:51:06.50/chk_obsdata//k5ts3/T2571750??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.17:51:06.83/chk_obsdata//k5ts4/T2571750??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.17:51:07.49/k5log//k5ts1_log_newline 2006.257.17:51:08.14/k5log//k5ts2_log_newline 2006.257.17:51:08.79/k5log//k5ts3_log_newline 2006.257.17:51:09.45/k5log//k5ts4_log_newline 2006.257.17:51:09.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:51:09.47:setupk4=1 2006.257.17:51:09.47$setupk4/echo=on 2006.257.17:51:09.47$setupk4/pcalon 2006.257.17:51:09.47$pcalon/"no phase cal control is implemented here 2006.257.17:51:09.47$setupk4/"tpicd=stop 2006.257.17:51:09.47$setupk4/"rec=synch_on 2006.257.17:51:09.47$setupk4/"rec_mode=128 2006.257.17:51:09.47$setupk4/!* 2006.257.17:51:09.47$setupk4/recpk4 2006.257.17:51:09.47$recpk4/recpatch= 2006.257.17:51:09.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:51:09.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:51:09.48$setupk4/vck44 2006.257.17:51:09.48$vck44/valo=1,524.99 2006.257.17:51:09.48#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.17:51:09.48#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.17:51:09.48#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:09.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:09.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:09.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:09.48#ibcon#enter wrdev, iclass 26, count 0 2006.257.17:51:09.48#ibcon#first serial, iclass 26, count 0 2006.257.17:51:09.48#ibcon#enter sib2, iclass 26, count 0 2006.257.17:51:09.48#ibcon#flushed, iclass 26, count 0 2006.257.17:51:09.48#ibcon#about to write, iclass 26, count 0 2006.257.17:51:09.48#ibcon#wrote, iclass 26, count 0 2006.257.17:51:09.48#ibcon#about to read 3, iclass 26, count 0 2006.257.17:51:09.50#ibcon#read 3, iclass 26, count 0 2006.257.17:51:09.50#ibcon#about to read 4, iclass 26, count 0 2006.257.17:51:09.50#ibcon#read 4, iclass 26, count 0 2006.257.17:51:09.50#ibcon#about to read 5, iclass 26, count 0 2006.257.17:51:09.50#ibcon#read 5, iclass 26, count 0 2006.257.17:51:09.50#ibcon#about to read 6, iclass 26, count 0 2006.257.17:51:09.50#ibcon#read 6, iclass 26, count 0 2006.257.17:51:09.50#ibcon#end of sib2, iclass 26, count 0 2006.257.17:51:09.50#ibcon#*mode == 0, iclass 26, count 0 2006.257.17:51:09.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.17:51:09.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:51:09.50#ibcon#*before write, iclass 26, count 0 2006.257.17:51:09.50#ibcon#enter sib2, iclass 26, count 0 2006.257.17:51:09.50#ibcon#flushed, iclass 26, count 0 2006.257.17:51:09.50#ibcon#about to write, iclass 26, count 0 2006.257.17:51:09.50#ibcon#wrote, iclass 26, count 0 2006.257.17:51:09.50#ibcon#about to read 3, iclass 26, count 0 2006.257.17:51:09.55#ibcon#read 3, iclass 26, count 0 2006.257.17:51:09.55#ibcon#about to read 4, iclass 26, count 0 2006.257.17:51:09.55#ibcon#read 4, iclass 26, count 0 2006.257.17:51:09.55#ibcon#about to read 5, iclass 26, count 0 2006.257.17:51:09.55#ibcon#read 5, iclass 26, count 0 2006.257.17:51:09.55#ibcon#about to read 6, iclass 26, count 0 2006.257.17:51:09.55#ibcon#read 6, iclass 26, count 0 2006.257.17:51:09.55#ibcon#end of sib2, iclass 26, count 0 2006.257.17:51:09.55#ibcon#*after write, iclass 26, count 0 2006.257.17:51:09.55#ibcon#*before return 0, iclass 26, count 0 2006.257.17:51:09.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:09.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:09.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.17:51:09.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.17:51:09.55$vck44/va=1,8 2006.257.17:51:09.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.17:51:09.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.17:51:09.55#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:09.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:09.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:09.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:09.55#ibcon#enter wrdev, iclass 28, count 2 2006.257.17:51:09.55#ibcon#first serial, iclass 28, count 2 2006.257.17:51:09.55#ibcon#enter sib2, iclass 28, count 2 2006.257.17:51:09.55#ibcon#flushed, iclass 28, count 2 2006.257.17:51:09.55#ibcon#about to write, iclass 28, count 2 2006.257.17:51:09.55#ibcon#wrote, iclass 28, count 2 2006.257.17:51:09.55#ibcon#about to read 3, iclass 28, count 2 2006.257.17:51:09.57#ibcon#read 3, iclass 28, count 2 2006.257.17:51:09.57#ibcon#about to read 4, iclass 28, count 2 2006.257.17:51:09.57#ibcon#read 4, iclass 28, count 2 2006.257.17:51:09.57#ibcon#about to read 5, iclass 28, count 2 2006.257.17:51:09.57#ibcon#read 5, iclass 28, count 2 2006.257.17:51:09.57#ibcon#about to read 6, iclass 28, count 2 2006.257.17:51:09.57#ibcon#read 6, iclass 28, count 2 2006.257.17:51:09.57#ibcon#end of sib2, iclass 28, count 2 2006.257.17:51:09.57#ibcon#*mode == 0, iclass 28, count 2 2006.257.17:51:09.57#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.17:51:09.57#ibcon#[25=AT01-08\r\n] 2006.257.17:51:09.57#ibcon#*before write, iclass 28, count 2 2006.257.17:51:09.57#ibcon#enter sib2, iclass 28, count 2 2006.257.17:51:09.57#ibcon#flushed, iclass 28, count 2 2006.257.17:51:09.57#ibcon#about to write, iclass 28, count 2 2006.257.17:51:09.57#ibcon#wrote, iclass 28, count 2 2006.257.17:51:09.57#ibcon#about to read 3, iclass 28, count 2 2006.257.17:51:09.60#ibcon#read 3, iclass 28, count 2 2006.257.17:51:09.60#ibcon#about to read 4, iclass 28, count 2 2006.257.17:51:09.60#ibcon#read 4, iclass 28, count 2 2006.257.17:51:09.60#ibcon#about to read 5, iclass 28, count 2 2006.257.17:51:09.60#ibcon#read 5, iclass 28, count 2 2006.257.17:51:09.60#ibcon#about to read 6, iclass 28, count 2 2006.257.17:51:09.60#ibcon#read 6, iclass 28, count 2 2006.257.17:51:09.60#ibcon#end of sib2, iclass 28, count 2 2006.257.17:51:09.60#ibcon#*after write, iclass 28, count 2 2006.257.17:51:09.60#ibcon#*before return 0, iclass 28, count 2 2006.257.17:51:09.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:09.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:09.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.17:51:09.60#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:09.60#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:09.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:09.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:09.72#ibcon#enter wrdev, iclass 28, count 0 2006.257.17:51:09.72#ibcon#first serial, iclass 28, count 0 2006.257.17:51:09.72#ibcon#enter sib2, iclass 28, count 0 2006.257.17:51:09.72#ibcon#flushed, iclass 28, count 0 2006.257.17:51:09.72#ibcon#about to write, iclass 28, count 0 2006.257.17:51:09.72#ibcon#wrote, iclass 28, count 0 2006.257.17:51:09.72#ibcon#about to read 3, iclass 28, count 0 2006.257.17:51:09.74#ibcon#read 3, iclass 28, count 0 2006.257.17:51:09.74#ibcon#about to read 4, iclass 28, count 0 2006.257.17:51:09.74#ibcon#read 4, iclass 28, count 0 2006.257.17:51:09.74#ibcon#about to read 5, iclass 28, count 0 2006.257.17:51:09.74#ibcon#read 5, iclass 28, count 0 2006.257.17:51:09.74#ibcon#about to read 6, iclass 28, count 0 2006.257.17:51:09.74#ibcon#read 6, iclass 28, count 0 2006.257.17:51:09.74#ibcon#end of sib2, iclass 28, count 0 2006.257.17:51:09.74#ibcon#*mode == 0, iclass 28, count 0 2006.257.17:51:09.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.17:51:09.74#ibcon#[25=USB\r\n] 2006.257.17:51:09.74#ibcon#*before write, iclass 28, count 0 2006.257.17:51:09.74#ibcon#enter sib2, iclass 28, count 0 2006.257.17:51:09.74#ibcon#flushed, iclass 28, count 0 2006.257.17:51:09.74#ibcon#about to write, iclass 28, count 0 2006.257.17:51:09.74#ibcon#wrote, iclass 28, count 0 2006.257.17:51:09.74#ibcon#about to read 3, iclass 28, count 0 2006.257.17:51:09.77#ibcon#read 3, iclass 28, count 0 2006.257.17:51:09.77#ibcon#about to read 4, iclass 28, count 0 2006.257.17:51:09.77#ibcon#read 4, iclass 28, count 0 2006.257.17:51:09.77#ibcon#about to read 5, iclass 28, count 0 2006.257.17:51:09.77#ibcon#read 5, iclass 28, count 0 2006.257.17:51:09.77#ibcon#about to read 6, iclass 28, count 0 2006.257.17:51:09.77#ibcon#read 6, iclass 28, count 0 2006.257.17:51:09.77#ibcon#end of sib2, iclass 28, count 0 2006.257.17:51:09.77#ibcon#*after write, iclass 28, count 0 2006.257.17:51:09.77#ibcon#*before return 0, iclass 28, count 0 2006.257.17:51:09.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:09.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:09.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.17:51:09.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.17:51:09.77$vck44/valo=2,534.99 2006.257.17:51:09.77#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.17:51:09.77#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.17:51:09.77#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:09.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:09.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:09.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:09.77#ibcon#enter wrdev, iclass 30, count 0 2006.257.17:51:09.77#ibcon#first serial, iclass 30, count 0 2006.257.17:51:09.77#ibcon#enter sib2, iclass 30, count 0 2006.257.17:51:09.77#ibcon#flushed, iclass 30, count 0 2006.257.17:51:09.77#ibcon#about to write, iclass 30, count 0 2006.257.17:51:09.77#ibcon#wrote, iclass 30, count 0 2006.257.17:51:09.77#ibcon#about to read 3, iclass 30, count 0 2006.257.17:51:09.79#ibcon#read 3, iclass 30, count 0 2006.257.17:51:09.79#ibcon#about to read 4, iclass 30, count 0 2006.257.17:51:09.79#ibcon#read 4, iclass 30, count 0 2006.257.17:51:09.79#ibcon#about to read 5, iclass 30, count 0 2006.257.17:51:09.79#ibcon#read 5, iclass 30, count 0 2006.257.17:51:09.79#ibcon#about to read 6, iclass 30, count 0 2006.257.17:51:09.79#ibcon#read 6, iclass 30, count 0 2006.257.17:51:09.79#ibcon#end of sib2, iclass 30, count 0 2006.257.17:51:09.79#ibcon#*mode == 0, iclass 30, count 0 2006.257.17:51:09.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.17:51:09.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:51:09.79#ibcon#*before write, iclass 30, count 0 2006.257.17:51:09.79#ibcon#enter sib2, iclass 30, count 0 2006.257.17:51:09.79#ibcon#flushed, iclass 30, count 0 2006.257.17:51:09.79#ibcon#about to write, iclass 30, count 0 2006.257.17:51:09.79#ibcon#wrote, iclass 30, count 0 2006.257.17:51:09.79#ibcon#about to read 3, iclass 30, count 0 2006.257.17:51:09.83#ibcon#read 3, iclass 30, count 0 2006.257.17:51:09.83#ibcon#about to read 4, iclass 30, count 0 2006.257.17:51:09.83#ibcon#read 4, iclass 30, count 0 2006.257.17:51:09.83#ibcon#about to read 5, iclass 30, count 0 2006.257.17:51:09.83#ibcon#read 5, iclass 30, count 0 2006.257.17:51:09.83#ibcon#about to read 6, iclass 30, count 0 2006.257.17:51:09.83#ibcon#read 6, iclass 30, count 0 2006.257.17:51:09.83#ibcon#end of sib2, iclass 30, count 0 2006.257.17:51:09.83#ibcon#*after write, iclass 30, count 0 2006.257.17:51:09.83#ibcon#*before return 0, iclass 30, count 0 2006.257.17:51:09.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:09.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:09.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.17:51:09.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.17:51:09.83$vck44/va=2,7 2006.257.17:51:09.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.17:51:09.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.17:51:09.83#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:09.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:09.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:09.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:09.89#ibcon#enter wrdev, iclass 32, count 2 2006.257.17:51:09.89#ibcon#first serial, iclass 32, count 2 2006.257.17:51:09.89#ibcon#enter sib2, iclass 32, count 2 2006.257.17:51:09.89#ibcon#flushed, iclass 32, count 2 2006.257.17:51:09.89#ibcon#about to write, iclass 32, count 2 2006.257.17:51:09.89#ibcon#wrote, iclass 32, count 2 2006.257.17:51:09.89#ibcon#about to read 3, iclass 32, count 2 2006.257.17:51:09.91#ibcon#read 3, iclass 32, count 2 2006.257.17:51:09.91#ibcon#about to read 4, iclass 32, count 2 2006.257.17:51:09.91#ibcon#read 4, iclass 32, count 2 2006.257.17:51:09.91#ibcon#about to read 5, iclass 32, count 2 2006.257.17:51:09.91#ibcon#read 5, iclass 32, count 2 2006.257.17:51:09.91#ibcon#about to read 6, iclass 32, count 2 2006.257.17:51:09.91#ibcon#read 6, iclass 32, count 2 2006.257.17:51:09.91#ibcon#end of sib2, iclass 32, count 2 2006.257.17:51:09.91#ibcon#*mode == 0, iclass 32, count 2 2006.257.17:51:09.91#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.17:51:09.91#ibcon#[25=AT02-07\r\n] 2006.257.17:51:09.91#ibcon#*before write, iclass 32, count 2 2006.257.17:51:09.91#ibcon#enter sib2, iclass 32, count 2 2006.257.17:51:09.91#ibcon#flushed, iclass 32, count 2 2006.257.17:51:09.91#ibcon#about to write, iclass 32, count 2 2006.257.17:51:09.91#ibcon#wrote, iclass 32, count 2 2006.257.17:51:09.91#ibcon#about to read 3, iclass 32, count 2 2006.257.17:51:09.94#ibcon#read 3, iclass 32, count 2 2006.257.17:51:09.94#ibcon#about to read 4, iclass 32, count 2 2006.257.17:51:09.94#ibcon#read 4, iclass 32, count 2 2006.257.17:51:09.94#ibcon#about to read 5, iclass 32, count 2 2006.257.17:51:09.94#ibcon#read 5, iclass 32, count 2 2006.257.17:51:09.94#ibcon#about to read 6, iclass 32, count 2 2006.257.17:51:09.94#ibcon#read 6, iclass 32, count 2 2006.257.17:51:09.94#ibcon#end of sib2, iclass 32, count 2 2006.257.17:51:09.94#ibcon#*after write, iclass 32, count 2 2006.257.17:51:09.94#ibcon#*before return 0, iclass 32, count 2 2006.257.17:51:09.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:09.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:09.94#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.17:51:09.94#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:09.94#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:10.06#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:10.06#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:10.06#ibcon#enter wrdev, iclass 32, count 0 2006.257.17:51:10.06#ibcon#first serial, iclass 32, count 0 2006.257.17:51:10.06#ibcon#enter sib2, iclass 32, count 0 2006.257.17:51:10.06#ibcon#flushed, iclass 32, count 0 2006.257.17:51:10.06#ibcon#about to write, iclass 32, count 0 2006.257.17:51:10.06#ibcon#wrote, iclass 32, count 0 2006.257.17:51:10.06#ibcon#about to read 3, iclass 32, count 0 2006.257.17:51:10.08#ibcon#read 3, iclass 32, count 0 2006.257.17:51:10.08#ibcon#about to read 4, iclass 32, count 0 2006.257.17:51:10.08#ibcon#read 4, iclass 32, count 0 2006.257.17:51:10.08#ibcon#about to read 5, iclass 32, count 0 2006.257.17:51:10.08#ibcon#read 5, iclass 32, count 0 2006.257.17:51:10.08#ibcon#about to read 6, iclass 32, count 0 2006.257.17:51:10.08#ibcon#read 6, iclass 32, count 0 2006.257.17:51:10.08#ibcon#end of sib2, iclass 32, count 0 2006.257.17:51:10.08#ibcon#*mode == 0, iclass 32, count 0 2006.257.17:51:10.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.17:51:10.08#ibcon#[25=USB\r\n] 2006.257.17:51:10.08#ibcon#*before write, iclass 32, count 0 2006.257.17:51:10.08#ibcon#enter sib2, iclass 32, count 0 2006.257.17:51:10.08#ibcon#flushed, iclass 32, count 0 2006.257.17:51:10.08#ibcon#about to write, iclass 32, count 0 2006.257.17:51:10.08#ibcon#wrote, iclass 32, count 0 2006.257.17:51:10.08#ibcon#about to read 3, iclass 32, count 0 2006.257.17:51:10.11#ibcon#read 3, iclass 32, count 0 2006.257.17:51:10.11#ibcon#about to read 4, iclass 32, count 0 2006.257.17:51:10.11#ibcon#read 4, iclass 32, count 0 2006.257.17:51:10.11#ibcon#about to read 5, iclass 32, count 0 2006.257.17:51:10.11#ibcon#read 5, iclass 32, count 0 2006.257.17:51:10.11#ibcon#about to read 6, iclass 32, count 0 2006.257.17:51:10.11#ibcon#read 6, iclass 32, count 0 2006.257.17:51:10.11#ibcon#end of sib2, iclass 32, count 0 2006.257.17:51:10.11#ibcon#*after write, iclass 32, count 0 2006.257.17:51:10.11#ibcon#*before return 0, iclass 32, count 0 2006.257.17:51:10.11#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:10.11#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:10.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.17:51:10.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.17:51:10.11$vck44/valo=3,564.99 2006.257.17:51:10.11#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.17:51:10.11#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.17:51:10.11#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:10.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:10.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:10.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:10.11#ibcon#enter wrdev, iclass 34, count 0 2006.257.17:51:10.11#ibcon#first serial, iclass 34, count 0 2006.257.17:51:10.11#ibcon#enter sib2, iclass 34, count 0 2006.257.17:51:10.11#ibcon#flushed, iclass 34, count 0 2006.257.17:51:10.11#ibcon#about to write, iclass 34, count 0 2006.257.17:51:10.11#ibcon#wrote, iclass 34, count 0 2006.257.17:51:10.11#ibcon#about to read 3, iclass 34, count 0 2006.257.17:51:10.13#ibcon#read 3, iclass 34, count 0 2006.257.17:51:10.13#ibcon#about to read 4, iclass 34, count 0 2006.257.17:51:10.13#ibcon#read 4, iclass 34, count 0 2006.257.17:51:10.13#ibcon#about to read 5, iclass 34, count 0 2006.257.17:51:10.13#ibcon#read 5, iclass 34, count 0 2006.257.17:51:10.13#ibcon#about to read 6, iclass 34, count 0 2006.257.17:51:10.13#ibcon#read 6, iclass 34, count 0 2006.257.17:51:10.13#ibcon#end of sib2, iclass 34, count 0 2006.257.17:51:10.13#ibcon#*mode == 0, iclass 34, count 0 2006.257.17:51:10.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.17:51:10.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:51:10.13#ibcon#*before write, iclass 34, count 0 2006.257.17:51:10.13#ibcon#enter sib2, iclass 34, count 0 2006.257.17:51:10.13#ibcon#flushed, iclass 34, count 0 2006.257.17:51:10.13#ibcon#about to write, iclass 34, count 0 2006.257.17:51:10.13#ibcon#wrote, iclass 34, count 0 2006.257.17:51:10.13#ibcon#about to read 3, iclass 34, count 0 2006.257.17:51:10.17#ibcon#read 3, iclass 34, count 0 2006.257.17:51:10.17#ibcon#about to read 4, iclass 34, count 0 2006.257.17:51:10.17#ibcon#read 4, iclass 34, count 0 2006.257.17:51:10.17#ibcon#about to read 5, iclass 34, count 0 2006.257.17:51:10.17#ibcon#read 5, iclass 34, count 0 2006.257.17:51:10.17#ibcon#about to read 6, iclass 34, count 0 2006.257.17:51:10.17#ibcon#read 6, iclass 34, count 0 2006.257.17:51:10.17#ibcon#end of sib2, iclass 34, count 0 2006.257.17:51:10.17#ibcon#*after write, iclass 34, count 0 2006.257.17:51:10.17#ibcon#*before return 0, iclass 34, count 0 2006.257.17:51:10.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:10.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:10.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.17:51:10.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.17:51:10.17$vck44/va=3,8 2006.257.17:51:10.17#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.17:51:10.17#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.17:51:10.17#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:10.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:10.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:10.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:10.23#ibcon#enter wrdev, iclass 36, count 2 2006.257.17:51:10.23#ibcon#first serial, iclass 36, count 2 2006.257.17:51:10.23#ibcon#enter sib2, iclass 36, count 2 2006.257.17:51:10.23#ibcon#flushed, iclass 36, count 2 2006.257.17:51:10.23#ibcon#about to write, iclass 36, count 2 2006.257.17:51:10.23#ibcon#wrote, iclass 36, count 2 2006.257.17:51:10.23#ibcon#about to read 3, iclass 36, count 2 2006.257.17:51:10.25#ibcon#read 3, iclass 36, count 2 2006.257.17:51:10.25#ibcon#about to read 4, iclass 36, count 2 2006.257.17:51:10.25#ibcon#read 4, iclass 36, count 2 2006.257.17:51:10.25#ibcon#about to read 5, iclass 36, count 2 2006.257.17:51:10.25#ibcon#read 5, iclass 36, count 2 2006.257.17:51:10.25#ibcon#about to read 6, iclass 36, count 2 2006.257.17:51:10.25#ibcon#read 6, iclass 36, count 2 2006.257.17:51:10.25#ibcon#end of sib2, iclass 36, count 2 2006.257.17:51:10.25#ibcon#*mode == 0, iclass 36, count 2 2006.257.17:51:10.25#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.17:51:10.25#ibcon#[25=AT03-08\r\n] 2006.257.17:51:10.25#ibcon#*before write, iclass 36, count 2 2006.257.17:51:10.25#ibcon#enter sib2, iclass 36, count 2 2006.257.17:51:10.25#ibcon#flushed, iclass 36, count 2 2006.257.17:51:10.25#ibcon#about to write, iclass 36, count 2 2006.257.17:51:10.25#ibcon#wrote, iclass 36, count 2 2006.257.17:51:10.25#ibcon#about to read 3, iclass 36, count 2 2006.257.17:51:10.28#ibcon#read 3, iclass 36, count 2 2006.257.17:51:10.28#ibcon#about to read 4, iclass 36, count 2 2006.257.17:51:10.28#ibcon#read 4, iclass 36, count 2 2006.257.17:51:10.28#ibcon#about to read 5, iclass 36, count 2 2006.257.17:51:10.28#ibcon#read 5, iclass 36, count 2 2006.257.17:51:10.28#ibcon#about to read 6, iclass 36, count 2 2006.257.17:51:10.28#ibcon#read 6, iclass 36, count 2 2006.257.17:51:10.28#ibcon#end of sib2, iclass 36, count 2 2006.257.17:51:10.28#ibcon#*after write, iclass 36, count 2 2006.257.17:51:10.28#ibcon#*before return 0, iclass 36, count 2 2006.257.17:51:10.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:10.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:10.28#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.17:51:10.28#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:10.28#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:10.40#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:10.40#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:10.40#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:51:10.40#ibcon#first serial, iclass 36, count 0 2006.257.17:51:10.40#ibcon#enter sib2, iclass 36, count 0 2006.257.17:51:10.40#ibcon#flushed, iclass 36, count 0 2006.257.17:51:10.40#ibcon#about to write, iclass 36, count 0 2006.257.17:51:10.40#ibcon#wrote, iclass 36, count 0 2006.257.17:51:10.40#ibcon#about to read 3, iclass 36, count 0 2006.257.17:51:10.42#ibcon#read 3, iclass 36, count 0 2006.257.17:51:10.42#ibcon#about to read 4, iclass 36, count 0 2006.257.17:51:10.42#ibcon#read 4, iclass 36, count 0 2006.257.17:51:10.42#ibcon#about to read 5, iclass 36, count 0 2006.257.17:51:10.42#ibcon#read 5, iclass 36, count 0 2006.257.17:51:10.42#ibcon#about to read 6, iclass 36, count 0 2006.257.17:51:10.42#ibcon#read 6, iclass 36, count 0 2006.257.17:51:10.42#ibcon#end of sib2, iclass 36, count 0 2006.257.17:51:10.42#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:51:10.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:51:10.42#ibcon#[25=USB\r\n] 2006.257.17:51:10.42#ibcon#*before write, iclass 36, count 0 2006.257.17:51:10.42#ibcon#enter sib2, iclass 36, count 0 2006.257.17:51:10.42#ibcon#flushed, iclass 36, count 0 2006.257.17:51:10.42#ibcon#about to write, iclass 36, count 0 2006.257.17:51:10.42#ibcon#wrote, iclass 36, count 0 2006.257.17:51:10.42#ibcon#about to read 3, iclass 36, count 0 2006.257.17:51:10.45#ibcon#read 3, iclass 36, count 0 2006.257.17:51:10.45#ibcon#about to read 4, iclass 36, count 0 2006.257.17:51:10.45#ibcon#read 4, iclass 36, count 0 2006.257.17:51:10.45#ibcon#about to read 5, iclass 36, count 0 2006.257.17:51:10.45#ibcon#read 5, iclass 36, count 0 2006.257.17:51:10.45#ibcon#about to read 6, iclass 36, count 0 2006.257.17:51:10.45#ibcon#read 6, iclass 36, count 0 2006.257.17:51:10.45#ibcon#end of sib2, iclass 36, count 0 2006.257.17:51:10.45#ibcon#*after write, iclass 36, count 0 2006.257.17:51:10.45#ibcon#*before return 0, iclass 36, count 0 2006.257.17:51:10.45#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:10.45#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:10.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:51:10.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:51:10.45$vck44/valo=4,624.99 2006.257.17:51:10.45#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.17:51:10.45#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.17:51:10.45#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:10.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:10.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:10.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:10.45#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:51:10.45#ibcon#first serial, iclass 38, count 0 2006.257.17:51:10.45#ibcon#enter sib2, iclass 38, count 0 2006.257.17:51:10.45#ibcon#flushed, iclass 38, count 0 2006.257.17:51:10.45#ibcon#about to write, iclass 38, count 0 2006.257.17:51:10.45#ibcon#wrote, iclass 38, count 0 2006.257.17:51:10.45#ibcon#about to read 3, iclass 38, count 0 2006.257.17:51:10.47#ibcon#read 3, iclass 38, count 0 2006.257.17:51:10.47#ibcon#about to read 4, iclass 38, count 0 2006.257.17:51:10.47#ibcon#read 4, iclass 38, count 0 2006.257.17:51:10.47#ibcon#about to read 5, iclass 38, count 0 2006.257.17:51:10.47#ibcon#read 5, iclass 38, count 0 2006.257.17:51:10.47#ibcon#about to read 6, iclass 38, count 0 2006.257.17:51:10.47#ibcon#read 6, iclass 38, count 0 2006.257.17:51:10.47#ibcon#end of sib2, iclass 38, count 0 2006.257.17:51:10.47#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:51:10.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:51:10.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:51:10.47#ibcon#*before write, iclass 38, count 0 2006.257.17:51:10.47#ibcon#enter sib2, iclass 38, count 0 2006.257.17:51:10.47#ibcon#flushed, iclass 38, count 0 2006.257.17:51:10.47#ibcon#about to write, iclass 38, count 0 2006.257.17:51:10.47#ibcon#wrote, iclass 38, count 0 2006.257.17:51:10.47#ibcon#about to read 3, iclass 38, count 0 2006.257.17:51:10.51#ibcon#read 3, iclass 38, count 0 2006.257.17:51:10.51#ibcon#about to read 4, iclass 38, count 0 2006.257.17:51:10.51#ibcon#read 4, iclass 38, count 0 2006.257.17:51:10.51#ibcon#about to read 5, iclass 38, count 0 2006.257.17:51:10.51#ibcon#read 5, iclass 38, count 0 2006.257.17:51:10.51#ibcon#about to read 6, iclass 38, count 0 2006.257.17:51:10.51#ibcon#read 6, iclass 38, count 0 2006.257.17:51:10.51#ibcon#end of sib2, iclass 38, count 0 2006.257.17:51:10.51#ibcon#*after write, iclass 38, count 0 2006.257.17:51:10.51#ibcon#*before return 0, iclass 38, count 0 2006.257.17:51:10.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:10.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:10.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:51:10.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:51:10.51$vck44/va=4,7 2006.257.17:51:10.51#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.17:51:10.51#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.17:51:10.51#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:10.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:10.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:10.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:10.57#ibcon#enter wrdev, iclass 40, count 2 2006.257.17:51:10.57#ibcon#first serial, iclass 40, count 2 2006.257.17:51:10.57#ibcon#enter sib2, iclass 40, count 2 2006.257.17:51:10.57#ibcon#flushed, iclass 40, count 2 2006.257.17:51:10.57#ibcon#about to write, iclass 40, count 2 2006.257.17:51:10.57#ibcon#wrote, iclass 40, count 2 2006.257.17:51:10.57#ibcon#about to read 3, iclass 40, count 2 2006.257.17:51:10.59#ibcon#read 3, iclass 40, count 2 2006.257.17:51:10.59#ibcon#about to read 4, iclass 40, count 2 2006.257.17:51:10.59#ibcon#read 4, iclass 40, count 2 2006.257.17:51:10.59#ibcon#about to read 5, iclass 40, count 2 2006.257.17:51:10.59#ibcon#read 5, iclass 40, count 2 2006.257.17:51:10.59#ibcon#about to read 6, iclass 40, count 2 2006.257.17:51:10.59#ibcon#read 6, iclass 40, count 2 2006.257.17:51:10.59#ibcon#end of sib2, iclass 40, count 2 2006.257.17:51:10.59#ibcon#*mode == 0, iclass 40, count 2 2006.257.17:51:10.59#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.17:51:10.59#ibcon#[25=AT04-07\r\n] 2006.257.17:51:10.59#ibcon#*before write, iclass 40, count 2 2006.257.17:51:10.59#ibcon#enter sib2, iclass 40, count 2 2006.257.17:51:10.59#ibcon#flushed, iclass 40, count 2 2006.257.17:51:10.59#ibcon#about to write, iclass 40, count 2 2006.257.17:51:10.59#ibcon#wrote, iclass 40, count 2 2006.257.17:51:10.59#ibcon#about to read 3, iclass 40, count 2 2006.257.17:51:10.62#ibcon#read 3, iclass 40, count 2 2006.257.17:51:10.62#ibcon#about to read 4, iclass 40, count 2 2006.257.17:51:10.62#ibcon#read 4, iclass 40, count 2 2006.257.17:51:10.62#ibcon#about to read 5, iclass 40, count 2 2006.257.17:51:10.62#ibcon#read 5, iclass 40, count 2 2006.257.17:51:10.62#ibcon#about to read 6, iclass 40, count 2 2006.257.17:51:10.62#ibcon#read 6, iclass 40, count 2 2006.257.17:51:10.62#ibcon#end of sib2, iclass 40, count 2 2006.257.17:51:10.62#ibcon#*after write, iclass 40, count 2 2006.257.17:51:10.62#ibcon#*before return 0, iclass 40, count 2 2006.257.17:51:10.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:10.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:10.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.17:51:10.62#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:10.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:10.74#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:10.74#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:10.74#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:51:10.74#ibcon#first serial, iclass 40, count 0 2006.257.17:51:10.74#ibcon#enter sib2, iclass 40, count 0 2006.257.17:51:10.74#ibcon#flushed, iclass 40, count 0 2006.257.17:51:10.74#ibcon#about to write, iclass 40, count 0 2006.257.17:51:10.74#ibcon#wrote, iclass 40, count 0 2006.257.17:51:10.74#ibcon#about to read 3, iclass 40, count 0 2006.257.17:51:10.76#ibcon#read 3, iclass 40, count 0 2006.257.17:51:10.76#ibcon#about to read 4, iclass 40, count 0 2006.257.17:51:10.76#ibcon#read 4, iclass 40, count 0 2006.257.17:51:10.76#ibcon#about to read 5, iclass 40, count 0 2006.257.17:51:10.76#ibcon#read 5, iclass 40, count 0 2006.257.17:51:10.76#ibcon#about to read 6, iclass 40, count 0 2006.257.17:51:10.76#ibcon#read 6, iclass 40, count 0 2006.257.17:51:10.76#ibcon#end of sib2, iclass 40, count 0 2006.257.17:51:10.76#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:51:10.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:51:10.76#ibcon#[25=USB\r\n] 2006.257.17:51:10.76#ibcon#*before write, iclass 40, count 0 2006.257.17:51:10.76#ibcon#enter sib2, iclass 40, count 0 2006.257.17:51:10.76#ibcon#flushed, iclass 40, count 0 2006.257.17:51:10.76#ibcon#about to write, iclass 40, count 0 2006.257.17:51:10.76#ibcon#wrote, iclass 40, count 0 2006.257.17:51:10.76#ibcon#about to read 3, iclass 40, count 0 2006.257.17:51:10.79#ibcon#read 3, iclass 40, count 0 2006.257.17:51:10.79#ibcon#about to read 4, iclass 40, count 0 2006.257.17:51:10.79#ibcon#read 4, iclass 40, count 0 2006.257.17:51:10.79#ibcon#about to read 5, iclass 40, count 0 2006.257.17:51:10.79#ibcon#read 5, iclass 40, count 0 2006.257.17:51:10.79#ibcon#about to read 6, iclass 40, count 0 2006.257.17:51:10.79#ibcon#read 6, iclass 40, count 0 2006.257.17:51:10.79#ibcon#end of sib2, iclass 40, count 0 2006.257.17:51:10.79#ibcon#*after write, iclass 40, count 0 2006.257.17:51:10.79#ibcon#*before return 0, iclass 40, count 0 2006.257.17:51:10.79#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:10.79#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:10.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:51:10.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:51:10.79$vck44/valo=5,734.99 2006.257.17:51:10.79#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.17:51:10.79#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.17:51:10.79#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:10.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:10.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:10.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:10.79#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:51:10.79#ibcon#first serial, iclass 4, count 0 2006.257.17:51:10.79#ibcon#enter sib2, iclass 4, count 0 2006.257.17:51:10.79#ibcon#flushed, iclass 4, count 0 2006.257.17:51:10.79#ibcon#about to write, iclass 4, count 0 2006.257.17:51:10.79#ibcon#wrote, iclass 4, count 0 2006.257.17:51:10.79#ibcon#about to read 3, iclass 4, count 0 2006.257.17:51:10.81#ibcon#read 3, iclass 4, count 0 2006.257.17:51:10.81#ibcon#about to read 4, iclass 4, count 0 2006.257.17:51:10.81#ibcon#read 4, iclass 4, count 0 2006.257.17:51:10.81#ibcon#about to read 5, iclass 4, count 0 2006.257.17:51:10.81#ibcon#read 5, iclass 4, count 0 2006.257.17:51:10.81#ibcon#about to read 6, iclass 4, count 0 2006.257.17:51:10.81#ibcon#read 6, iclass 4, count 0 2006.257.17:51:10.81#ibcon#end of sib2, iclass 4, count 0 2006.257.17:51:10.81#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:51:10.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:51:10.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:51:10.81#ibcon#*before write, iclass 4, count 0 2006.257.17:51:10.81#ibcon#enter sib2, iclass 4, count 0 2006.257.17:51:10.81#ibcon#flushed, iclass 4, count 0 2006.257.17:51:10.81#ibcon#about to write, iclass 4, count 0 2006.257.17:51:10.81#ibcon#wrote, iclass 4, count 0 2006.257.17:51:10.81#ibcon#about to read 3, iclass 4, count 0 2006.257.17:51:10.85#ibcon#read 3, iclass 4, count 0 2006.257.17:51:10.85#ibcon#about to read 4, iclass 4, count 0 2006.257.17:51:10.85#ibcon#read 4, iclass 4, count 0 2006.257.17:51:10.85#ibcon#about to read 5, iclass 4, count 0 2006.257.17:51:10.85#ibcon#read 5, iclass 4, count 0 2006.257.17:51:10.85#ibcon#about to read 6, iclass 4, count 0 2006.257.17:51:10.85#ibcon#read 6, iclass 4, count 0 2006.257.17:51:10.85#ibcon#end of sib2, iclass 4, count 0 2006.257.17:51:10.85#ibcon#*after write, iclass 4, count 0 2006.257.17:51:10.85#ibcon#*before return 0, iclass 4, count 0 2006.257.17:51:10.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:10.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:10.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:51:10.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:51:10.85$vck44/va=5,4 2006.257.17:51:10.85#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.17:51:10.85#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.17:51:10.85#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:10.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:10.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:10.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:10.91#ibcon#enter wrdev, iclass 6, count 2 2006.257.17:51:10.91#ibcon#first serial, iclass 6, count 2 2006.257.17:51:10.91#ibcon#enter sib2, iclass 6, count 2 2006.257.17:51:10.91#ibcon#flushed, iclass 6, count 2 2006.257.17:51:10.91#ibcon#about to write, iclass 6, count 2 2006.257.17:51:10.91#ibcon#wrote, iclass 6, count 2 2006.257.17:51:10.91#ibcon#about to read 3, iclass 6, count 2 2006.257.17:51:10.93#ibcon#read 3, iclass 6, count 2 2006.257.17:51:10.93#ibcon#about to read 4, iclass 6, count 2 2006.257.17:51:10.93#ibcon#read 4, iclass 6, count 2 2006.257.17:51:10.93#ibcon#about to read 5, iclass 6, count 2 2006.257.17:51:10.93#ibcon#read 5, iclass 6, count 2 2006.257.17:51:10.93#ibcon#about to read 6, iclass 6, count 2 2006.257.17:51:10.93#ibcon#read 6, iclass 6, count 2 2006.257.17:51:10.93#ibcon#end of sib2, iclass 6, count 2 2006.257.17:51:10.93#ibcon#*mode == 0, iclass 6, count 2 2006.257.17:51:10.93#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.17:51:10.93#ibcon#[25=AT05-04\r\n] 2006.257.17:51:10.93#ibcon#*before write, iclass 6, count 2 2006.257.17:51:10.93#ibcon#enter sib2, iclass 6, count 2 2006.257.17:51:10.93#ibcon#flushed, iclass 6, count 2 2006.257.17:51:10.93#ibcon#about to write, iclass 6, count 2 2006.257.17:51:10.93#ibcon#wrote, iclass 6, count 2 2006.257.17:51:10.93#ibcon#about to read 3, iclass 6, count 2 2006.257.17:51:10.96#ibcon#read 3, iclass 6, count 2 2006.257.17:51:10.96#ibcon#about to read 4, iclass 6, count 2 2006.257.17:51:10.96#ibcon#read 4, iclass 6, count 2 2006.257.17:51:10.96#ibcon#about to read 5, iclass 6, count 2 2006.257.17:51:10.96#ibcon#read 5, iclass 6, count 2 2006.257.17:51:10.96#ibcon#about to read 6, iclass 6, count 2 2006.257.17:51:10.96#ibcon#read 6, iclass 6, count 2 2006.257.17:51:10.96#ibcon#end of sib2, iclass 6, count 2 2006.257.17:51:10.96#ibcon#*after write, iclass 6, count 2 2006.257.17:51:10.96#ibcon#*before return 0, iclass 6, count 2 2006.257.17:51:10.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:10.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:10.96#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.17:51:10.96#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:10.96#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:11.08#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:11.08#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:11.08#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:51:11.08#ibcon#first serial, iclass 6, count 0 2006.257.17:51:11.08#ibcon#enter sib2, iclass 6, count 0 2006.257.17:51:11.08#ibcon#flushed, iclass 6, count 0 2006.257.17:51:11.08#ibcon#about to write, iclass 6, count 0 2006.257.17:51:11.08#ibcon#wrote, iclass 6, count 0 2006.257.17:51:11.08#ibcon#about to read 3, iclass 6, count 0 2006.257.17:51:11.10#ibcon#read 3, iclass 6, count 0 2006.257.17:51:11.10#ibcon#about to read 4, iclass 6, count 0 2006.257.17:51:11.10#ibcon#read 4, iclass 6, count 0 2006.257.17:51:11.10#ibcon#about to read 5, iclass 6, count 0 2006.257.17:51:11.10#ibcon#read 5, iclass 6, count 0 2006.257.17:51:11.10#ibcon#about to read 6, iclass 6, count 0 2006.257.17:51:11.10#ibcon#read 6, iclass 6, count 0 2006.257.17:51:11.10#ibcon#end of sib2, iclass 6, count 0 2006.257.17:51:11.10#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:51:11.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:51:11.10#ibcon#[25=USB\r\n] 2006.257.17:51:11.10#ibcon#*before write, iclass 6, count 0 2006.257.17:51:11.10#ibcon#enter sib2, iclass 6, count 0 2006.257.17:51:11.10#ibcon#flushed, iclass 6, count 0 2006.257.17:51:11.10#ibcon#about to write, iclass 6, count 0 2006.257.17:51:11.10#ibcon#wrote, iclass 6, count 0 2006.257.17:51:11.10#ibcon#about to read 3, iclass 6, count 0 2006.257.17:51:11.13#ibcon#read 3, iclass 6, count 0 2006.257.17:51:11.13#ibcon#about to read 4, iclass 6, count 0 2006.257.17:51:11.13#ibcon#read 4, iclass 6, count 0 2006.257.17:51:11.13#ibcon#about to read 5, iclass 6, count 0 2006.257.17:51:11.13#ibcon#read 5, iclass 6, count 0 2006.257.17:51:11.13#ibcon#about to read 6, iclass 6, count 0 2006.257.17:51:11.13#ibcon#read 6, iclass 6, count 0 2006.257.17:51:11.13#ibcon#end of sib2, iclass 6, count 0 2006.257.17:51:11.13#ibcon#*after write, iclass 6, count 0 2006.257.17:51:11.13#ibcon#*before return 0, iclass 6, count 0 2006.257.17:51:11.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:11.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:11.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:51:11.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:51:11.13$vck44/valo=6,814.99 2006.257.17:51:11.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.17:51:11.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.17:51:11.13#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:11.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:11.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:11.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:11.13#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:51:11.13#ibcon#first serial, iclass 10, count 0 2006.257.17:51:11.13#ibcon#enter sib2, iclass 10, count 0 2006.257.17:51:11.13#ibcon#flushed, iclass 10, count 0 2006.257.17:51:11.13#ibcon#about to write, iclass 10, count 0 2006.257.17:51:11.13#ibcon#wrote, iclass 10, count 0 2006.257.17:51:11.13#ibcon#about to read 3, iclass 10, count 0 2006.257.17:51:11.15#ibcon#read 3, iclass 10, count 0 2006.257.17:51:11.15#ibcon#about to read 4, iclass 10, count 0 2006.257.17:51:11.15#ibcon#read 4, iclass 10, count 0 2006.257.17:51:11.15#ibcon#about to read 5, iclass 10, count 0 2006.257.17:51:11.15#ibcon#read 5, iclass 10, count 0 2006.257.17:51:11.15#ibcon#about to read 6, iclass 10, count 0 2006.257.17:51:11.15#ibcon#read 6, iclass 10, count 0 2006.257.17:51:11.15#ibcon#end of sib2, iclass 10, count 0 2006.257.17:51:11.15#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:51:11.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:51:11.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:51:11.15#ibcon#*before write, iclass 10, count 0 2006.257.17:51:11.15#ibcon#enter sib2, iclass 10, count 0 2006.257.17:51:11.15#ibcon#flushed, iclass 10, count 0 2006.257.17:51:11.15#ibcon#about to write, iclass 10, count 0 2006.257.17:51:11.15#ibcon#wrote, iclass 10, count 0 2006.257.17:51:11.15#ibcon#about to read 3, iclass 10, count 0 2006.257.17:51:11.19#ibcon#read 3, iclass 10, count 0 2006.257.17:51:11.19#ibcon#about to read 4, iclass 10, count 0 2006.257.17:51:11.19#ibcon#read 4, iclass 10, count 0 2006.257.17:51:11.19#ibcon#about to read 5, iclass 10, count 0 2006.257.17:51:11.19#ibcon#read 5, iclass 10, count 0 2006.257.17:51:11.19#ibcon#about to read 6, iclass 10, count 0 2006.257.17:51:11.19#ibcon#read 6, iclass 10, count 0 2006.257.17:51:11.19#ibcon#end of sib2, iclass 10, count 0 2006.257.17:51:11.19#ibcon#*after write, iclass 10, count 0 2006.257.17:51:11.19#ibcon#*before return 0, iclass 10, count 0 2006.257.17:51:11.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:11.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:11.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:51:11.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:51:11.19$vck44/va=6,4 2006.257.17:51:11.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.17:51:11.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.17:51:11.19#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:11.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:11.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:11.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:11.25#ibcon#enter wrdev, iclass 12, count 2 2006.257.17:51:11.25#ibcon#first serial, iclass 12, count 2 2006.257.17:51:11.25#ibcon#enter sib2, iclass 12, count 2 2006.257.17:51:11.25#ibcon#flushed, iclass 12, count 2 2006.257.17:51:11.25#ibcon#about to write, iclass 12, count 2 2006.257.17:51:11.25#ibcon#wrote, iclass 12, count 2 2006.257.17:51:11.25#ibcon#about to read 3, iclass 12, count 2 2006.257.17:51:11.27#ibcon#read 3, iclass 12, count 2 2006.257.17:51:11.27#ibcon#about to read 4, iclass 12, count 2 2006.257.17:51:11.27#ibcon#read 4, iclass 12, count 2 2006.257.17:51:11.27#ibcon#about to read 5, iclass 12, count 2 2006.257.17:51:11.27#ibcon#read 5, iclass 12, count 2 2006.257.17:51:11.27#ibcon#about to read 6, iclass 12, count 2 2006.257.17:51:11.27#ibcon#read 6, iclass 12, count 2 2006.257.17:51:11.27#ibcon#end of sib2, iclass 12, count 2 2006.257.17:51:11.27#ibcon#*mode == 0, iclass 12, count 2 2006.257.17:51:11.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.17:51:11.27#ibcon#[25=AT06-04\r\n] 2006.257.17:51:11.27#ibcon#*before write, iclass 12, count 2 2006.257.17:51:11.27#ibcon#enter sib2, iclass 12, count 2 2006.257.17:51:11.27#ibcon#flushed, iclass 12, count 2 2006.257.17:51:11.27#ibcon#about to write, iclass 12, count 2 2006.257.17:51:11.27#ibcon#wrote, iclass 12, count 2 2006.257.17:51:11.27#ibcon#about to read 3, iclass 12, count 2 2006.257.17:51:11.30#ibcon#read 3, iclass 12, count 2 2006.257.17:51:11.30#ibcon#about to read 4, iclass 12, count 2 2006.257.17:51:11.30#ibcon#read 4, iclass 12, count 2 2006.257.17:51:11.30#ibcon#about to read 5, iclass 12, count 2 2006.257.17:51:11.30#ibcon#read 5, iclass 12, count 2 2006.257.17:51:11.30#ibcon#about to read 6, iclass 12, count 2 2006.257.17:51:11.30#ibcon#read 6, iclass 12, count 2 2006.257.17:51:11.30#ibcon#end of sib2, iclass 12, count 2 2006.257.17:51:11.30#ibcon#*after write, iclass 12, count 2 2006.257.17:51:11.30#ibcon#*before return 0, iclass 12, count 2 2006.257.17:51:11.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:11.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:11.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.17:51:11.30#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:11.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:11.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:11.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:11.42#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:51:11.42#ibcon#first serial, iclass 12, count 0 2006.257.17:51:11.42#ibcon#enter sib2, iclass 12, count 0 2006.257.17:51:11.42#ibcon#flushed, iclass 12, count 0 2006.257.17:51:11.42#ibcon#about to write, iclass 12, count 0 2006.257.17:51:11.42#ibcon#wrote, iclass 12, count 0 2006.257.17:51:11.42#ibcon#about to read 3, iclass 12, count 0 2006.257.17:51:11.44#ibcon#read 3, iclass 12, count 0 2006.257.17:51:11.44#ibcon#about to read 4, iclass 12, count 0 2006.257.17:51:11.44#ibcon#read 4, iclass 12, count 0 2006.257.17:51:11.44#ibcon#about to read 5, iclass 12, count 0 2006.257.17:51:11.44#ibcon#read 5, iclass 12, count 0 2006.257.17:51:11.44#ibcon#about to read 6, iclass 12, count 0 2006.257.17:51:11.44#ibcon#read 6, iclass 12, count 0 2006.257.17:51:11.44#ibcon#end of sib2, iclass 12, count 0 2006.257.17:51:11.44#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:51:11.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:51:11.44#ibcon#[25=USB\r\n] 2006.257.17:51:11.44#ibcon#*before write, iclass 12, count 0 2006.257.17:51:11.44#ibcon#enter sib2, iclass 12, count 0 2006.257.17:51:11.44#ibcon#flushed, iclass 12, count 0 2006.257.17:51:11.44#ibcon#about to write, iclass 12, count 0 2006.257.17:51:11.44#ibcon#wrote, iclass 12, count 0 2006.257.17:51:11.44#ibcon#about to read 3, iclass 12, count 0 2006.257.17:51:11.47#ibcon#read 3, iclass 12, count 0 2006.257.17:51:11.47#ibcon#about to read 4, iclass 12, count 0 2006.257.17:51:11.47#ibcon#read 4, iclass 12, count 0 2006.257.17:51:11.47#ibcon#about to read 5, iclass 12, count 0 2006.257.17:51:11.47#ibcon#read 5, iclass 12, count 0 2006.257.17:51:11.47#ibcon#about to read 6, iclass 12, count 0 2006.257.17:51:11.47#ibcon#read 6, iclass 12, count 0 2006.257.17:51:11.47#ibcon#end of sib2, iclass 12, count 0 2006.257.17:51:11.47#ibcon#*after write, iclass 12, count 0 2006.257.17:51:11.47#ibcon#*before return 0, iclass 12, count 0 2006.257.17:51:11.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:11.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:11.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:51:11.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:51:11.47$vck44/valo=7,864.99 2006.257.17:51:11.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.17:51:11.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.17:51:11.47#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:11.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:11.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:11.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:11.47#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:51:11.47#ibcon#first serial, iclass 14, count 0 2006.257.17:51:11.47#ibcon#enter sib2, iclass 14, count 0 2006.257.17:51:11.47#ibcon#flushed, iclass 14, count 0 2006.257.17:51:11.47#ibcon#about to write, iclass 14, count 0 2006.257.17:51:11.47#ibcon#wrote, iclass 14, count 0 2006.257.17:51:11.47#ibcon#about to read 3, iclass 14, count 0 2006.257.17:51:11.49#ibcon#read 3, iclass 14, count 0 2006.257.17:51:11.49#ibcon#about to read 4, iclass 14, count 0 2006.257.17:51:11.49#ibcon#read 4, iclass 14, count 0 2006.257.17:51:11.49#ibcon#about to read 5, iclass 14, count 0 2006.257.17:51:11.49#ibcon#read 5, iclass 14, count 0 2006.257.17:51:11.49#ibcon#about to read 6, iclass 14, count 0 2006.257.17:51:11.49#ibcon#read 6, iclass 14, count 0 2006.257.17:51:11.49#ibcon#end of sib2, iclass 14, count 0 2006.257.17:51:11.49#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:51:11.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:51:11.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:51:11.49#ibcon#*before write, iclass 14, count 0 2006.257.17:51:11.49#ibcon#enter sib2, iclass 14, count 0 2006.257.17:51:11.49#ibcon#flushed, iclass 14, count 0 2006.257.17:51:11.49#ibcon#about to write, iclass 14, count 0 2006.257.17:51:11.49#ibcon#wrote, iclass 14, count 0 2006.257.17:51:11.49#ibcon#about to read 3, iclass 14, count 0 2006.257.17:51:11.53#ibcon#read 3, iclass 14, count 0 2006.257.17:51:11.53#ibcon#about to read 4, iclass 14, count 0 2006.257.17:51:11.53#ibcon#read 4, iclass 14, count 0 2006.257.17:51:11.53#ibcon#about to read 5, iclass 14, count 0 2006.257.17:51:11.53#ibcon#read 5, iclass 14, count 0 2006.257.17:51:11.53#ibcon#about to read 6, iclass 14, count 0 2006.257.17:51:11.53#ibcon#read 6, iclass 14, count 0 2006.257.17:51:11.53#ibcon#end of sib2, iclass 14, count 0 2006.257.17:51:11.53#ibcon#*after write, iclass 14, count 0 2006.257.17:51:11.53#ibcon#*before return 0, iclass 14, count 0 2006.257.17:51:11.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:11.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:11.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:51:11.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:51:11.53$vck44/va=7,4 2006.257.17:51:11.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.17:51:11.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.17:51:11.53#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:11.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:11.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:11.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:11.59#ibcon#enter wrdev, iclass 16, count 2 2006.257.17:51:11.59#ibcon#first serial, iclass 16, count 2 2006.257.17:51:11.59#ibcon#enter sib2, iclass 16, count 2 2006.257.17:51:11.59#ibcon#flushed, iclass 16, count 2 2006.257.17:51:11.59#ibcon#about to write, iclass 16, count 2 2006.257.17:51:11.59#ibcon#wrote, iclass 16, count 2 2006.257.17:51:11.59#ibcon#about to read 3, iclass 16, count 2 2006.257.17:51:11.61#ibcon#read 3, iclass 16, count 2 2006.257.17:51:11.61#ibcon#about to read 4, iclass 16, count 2 2006.257.17:51:11.61#ibcon#read 4, iclass 16, count 2 2006.257.17:51:11.61#ibcon#about to read 5, iclass 16, count 2 2006.257.17:51:11.61#ibcon#read 5, iclass 16, count 2 2006.257.17:51:11.61#ibcon#about to read 6, iclass 16, count 2 2006.257.17:51:11.61#ibcon#read 6, iclass 16, count 2 2006.257.17:51:11.61#ibcon#end of sib2, iclass 16, count 2 2006.257.17:51:11.61#ibcon#*mode == 0, iclass 16, count 2 2006.257.17:51:11.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.17:51:11.61#ibcon#[25=AT07-04\r\n] 2006.257.17:51:11.61#ibcon#*before write, iclass 16, count 2 2006.257.17:51:11.61#ibcon#enter sib2, iclass 16, count 2 2006.257.17:51:11.61#ibcon#flushed, iclass 16, count 2 2006.257.17:51:11.61#ibcon#about to write, iclass 16, count 2 2006.257.17:51:11.61#ibcon#wrote, iclass 16, count 2 2006.257.17:51:11.61#ibcon#about to read 3, iclass 16, count 2 2006.257.17:51:11.64#ibcon#read 3, iclass 16, count 2 2006.257.17:51:11.64#ibcon#about to read 4, iclass 16, count 2 2006.257.17:51:11.64#ibcon#read 4, iclass 16, count 2 2006.257.17:51:11.64#ibcon#about to read 5, iclass 16, count 2 2006.257.17:51:11.64#ibcon#read 5, iclass 16, count 2 2006.257.17:51:11.64#ibcon#about to read 6, iclass 16, count 2 2006.257.17:51:11.64#ibcon#read 6, iclass 16, count 2 2006.257.17:51:11.64#ibcon#end of sib2, iclass 16, count 2 2006.257.17:51:11.64#ibcon#*after write, iclass 16, count 2 2006.257.17:51:11.64#ibcon#*before return 0, iclass 16, count 2 2006.257.17:51:11.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:11.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:11.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.17:51:11.64#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:11.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:11.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:11.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:11.76#ibcon#enter wrdev, iclass 16, count 0 2006.257.17:51:11.76#ibcon#first serial, iclass 16, count 0 2006.257.17:51:11.76#ibcon#enter sib2, iclass 16, count 0 2006.257.17:51:11.76#ibcon#flushed, iclass 16, count 0 2006.257.17:51:11.76#ibcon#about to write, iclass 16, count 0 2006.257.17:51:11.76#ibcon#wrote, iclass 16, count 0 2006.257.17:51:11.76#ibcon#about to read 3, iclass 16, count 0 2006.257.17:51:11.78#ibcon#read 3, iclass 16, count 0 2006.257.17:51:11.78#ibcon#about to read 4, iclass 16, count 0 2006.257.17:51:11.78#ibcon#read 4, iclass 16, count 0 2006.257.17:51:11.78#ibcon#about to read 5, iclass 16, count 0 2006.257.17:51:11.78#ibcon#read 5, iclass 16, count 0 2006.257.17:51:11.78#ibcon#about to read 6, iclass 16, count 0 2006.257.17:51:11.78#ibcon#read 6, iclass 16, count 0 2006.257.17:51:11.78#ibcon#end of sib2, iclass 16, count 0 2006.257.17:51:11.78#ibcon#*mode == 0, iclass 16, count 0 2006.257.17:51:11.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.17:51:11.78#ibcon#[25=USB\r\n] 2006.257.17:51:11.78#ibcon#*before write, iclass 16, count 0 2006.257.17:51:11.78#ibcon#enter sib2, iclass 16, count 0 2006.257.17:51:11.78#ibcon#flushed, iclass 16, count 0 2006.257.17:51:11.78#ibcon#about to write, iclass 16, count 0 2006.257.17:51:11.78#ibcon#wrote, iclass 16, count 0 2006.257.17:51:11.78#ibcon#about to read 3, iclass 16, count 0 2006.257.17:51:11.81#ibcon#read 3, iclass 16, count 0 2006.257.17:51:11.81#ibcon#about to read 4, iclass 16, count 0 2006.257.17:51:11.81#ibcon#read 4, iclass 16, count 0 2006.257.17:51:11.81#ibcon#about to read 5, iclass 16, count 0 2006.257.17:51:11.81#ibcon#read 5, iclass 16, count 0 2006.257.17:51:11.81#ibcon#about to read 6, iclass 16, count 0 2006.257.17:51:11.81#ibcon#read 6, iclass 16, count 0 2006.257.17:51:11.81#ibcon#end of sib2, iclass 16, count 0 2006.257.17:51:11.81#ibcon#*after write, iclass 16, count 0 2006.257.17:51:11.81#ibcon#*before return 0, iclass 16, count 0 2006.257.17:51:11.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:11.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:11.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.17:51:11.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.17:51:11.81$vck44/valo=8,884.99 2006.257.17:51:11.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.17:51:11.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.17:51:11.81#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:11.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:11.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:11.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:11.81#ibcon#enter wrdev, iclass 18, count 0 2006.257.17:51:11.81#ibcon#first serial, iclass 18, count 0 2006.257.17:51:11.81#ibcon#enter sib2, iclass 18, count 0 2006.257.17:51:11.81#ibcon#flushed, iclass 18, count 0 2006.257.17:51:11.81#ibcon#about to write, iclass 18, count 0 2006.257.17:51:11.81#ibcon#wrote, iclass 18, count 0 2006.257.17:51:11.81#ibcon#about to read 3, iclass 18, count 0 2006.257.17:51:11.83#ibcon#read 3, iclass 18, count 0 2006.257.17:51:11.83#ibcon#about to read 4, iclass 18, count 0 2006.257.17:51:11.83#ibcon#read 4, iclass 18, count 0 2006.257.17:51:11.83#ibcon#about to read 5, iclass 18, count 0 2006.257.17:51:11.83#ibcon#read 5, iclass 18, count 0 2006.257.17:51:11.83#ibcon#about to read 6, iclass 18, count 0 2006.257.17:51:11.83#ibcon#read 6, iclass 18, count 0 2006.257.17:51:11.83#ibcon#end of sib2, iclass 18, count 0 2006.257.17:51:11.83#ibcon#*mode == 0, iclass 18, count 0 2006.257.17:51:11.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.17:51:11.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:51:11.83#ibcon#*before write, iclass 18, count 0 2006.257.17:51:11.83#ibcon#enter sib2, iclass 18, count 0 2006.257.17:51:11.83#ibcon#flushed, iclass 18, count 0 2006.257.17:51:11.83#ibcon#about to write, iclass 18, count 0 2006.257.17:51:11.83#ibcon#wrote, iclass 18, count 0 2006.257.17:51:11.83#ibcon#about to read 3, iclass 18, count 0 2006.257.17:51:11.87#ibcon#read 3, iclass 18, count 0 2006.257.17:51:11.87#ibcon#about to read 4, iclass 18, count 0 2006.257.17:51:11.87#ibcon#read 4, iclass 18, count 0 2006.257.17:51:11.87#ibcon#about to read 5, iclass 18, count 0 2006.257.17:51:11.87#ibcon#read 5, iclass 18, count 0 2006.257.17:51:11.87#ibcon#about to read 6, iclass 18, count 0 2006.257.17:51:11.87#ibcon#read 6, iclass 18, count 0 2006.257.17:51:11.87#ibcon#end of sib2, iclass 18, count 0 2006.257.17:51:11.87#ibcon#*after write, iclass 18, count 0 2006.257.17:51:11.87#ibcon#*before return 0, iclass 18, count 0 2006.257.17:51:11.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:11.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:11.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.17:51:11.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.17:51:11.87$vck44/va=8,4 2006.257.17:51:11.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.17:51:11.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.17:51:11.87#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:11.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:51:11.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:51:11.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:51:11.93#ibcon#enter wrdev, iclass 20, count 2 2006.257.17:51:11.93#ibcon#first serial, iclass 20, count 2 2006.257.17:51:11.93#ibcon#enter sib2, iclass 20, count 2 2006.257.17:51:11.93#ibcon#flushed, iclass 20, count 2 2006.257.17:51:11.93#ibcon#about to write, iclass 20, count 2 2006.257.17:51:11.93#ibcon#wrote, iclass 20, count 2 2006.257.17:51:11.93#ibcon#about to read 3, iclass 20, count 2 2006.257.17:51:11.95#ibcon#read 3, iclass 20, count 2 2006.257.17:51:11.95#ibcon#about to read 4, iclass 20, count 2 2006.257.17:51:11.95#ibcon#read 4, iclass 20, count 2 2006.257.17:51:11.95#ibcon#about to read 5, iclass 20, count 2 2006.257.17:51:11.95#ibcon#read 5, iclass 20, count 2 2006.257.17:51:11.95#ibcon#about to read 6, iclass 20, count 2 2006.257.17:51:11.95#ibcon#read 6, iclass 20, count 2 2006.257.17:51:11.95#ibcon#end of sib2, iclass 20, count 2 2006.257.17:51:11.95#ibcon#*mode == 0, iclass 20, count 2 2006.257.17:51:11.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.17:51:11.95#ibcon#[25=AT08-04\r\n] 2006.257.17:51:11.95#ibcon#*before write, iclass 20, count 2 2006.257.17:51:11.95#ibcon#enter sib2, iclass 20, count 2 2006.257.17:51:11.95#ibcon#flushed, iclass 20, count 2 2006.257.17:51:11.95#ibcon#about to write, iclass 20, count 2 2006.257.17:51:11.95#ibcon#wrote, iclass 20, count 2 2006.257.17:51:11.95#ibcon#about to read 3, iclass 20, count 2 2006.257.17:51:11.98#ibcon#read 3, iclass 20, count 2 2006.257.17:51:11.98#ibcon#about to read 4, iclass 20, count 2 2006.257.17:51:11.98#ibcon#read 4, iclass 20, count 2 2006.257.17:51:11.98#ibcon#about to read 5, iclass 20, count 2 2006.257.17:51:11.98#ibcon#read 5, iclass 20, count 2 2006.257.17:51:11.98#ibcon#about to read 6, iclass 20, count 2 2006.257.17:51:11.98#ibcon#read 6, iclass 20, count 2 2006.257.17:51:11.98#ibcon#end of sib2, iclass 20, count 2 2006.257.17:51:11.98#ibcon#*after write, iclass 20, count 2 2006.257.17:51:11.98#ibcon#*before return 0, iclass 20, count 2 2006.257.17:51:11.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:51:11.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.17:51:11.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.17:51:11.98#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:11.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:51:12.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:51:12.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:51:12.10#ibcon#enter wrdev, iclass 20, count 0 2006.257.17:51:12.10#ibcon#first serial, iclass 20, count 0 2006.257.17:51:12.10#ibcon#enter sib2, iclass 20, count 0 2006.257.17:51:12.10#ibcon#flushed, iclass 20, count 0 2006.257.17:51:12.10#ibcon#about to write, iclass 20, count 0 2006.257.17:51:12.10#ibcon#wrote, iclass 20, count 0 2006.257.17:51:12.10#ibcon#about to read 3, iclass 20, count 0 2006.257.17:51:12.12#ibcon#read 3, iclass 20, count 0 2006.257.17:51:12.12#ibcon#about to read 4, iclass 20, count 0 2006.257.17:51:12.12#ibcon#read 4, iclass 20, count 0 2006.257.17:51:12.12#ibcon#about to read 5, iclass 20, count 0 2006.257.17:51:12.12#ibcon#read 5, iclass 20, count 0 2006.257.17:51:12.12#ibcon#about to read 6, iclass 20, count 0 2006.257.17:51:12.12#ibcon#read 6, iclass 20, count 0 2006.257.17:51:12.12#ibcon#end of sib2, iclass 20, count 0 2006.257.17:51:12.12#ibcon#*mode == 0, iclass 20, count 0 2006.257.17:51:12.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.17:51:12.12#ibcon#[25=USB\r\n] 2006.257.17:51:12.12#ibcon#*before write, iclass 20, count 0 2006.257.17:51:12.12#ibcon#enter sib2, iclass 20, count 0 2006.257.17:51:12.12#ibcon#flushed, iclass 20, count 0 2006.257.17:51:12.12#ibcon#about to write, iclass 20, count 0 2006.257.17:51:12.12#ibcon#wrote, iclass 20, count 0 2006.257.17:51:12.12#ibcon#about to read 3, iclass 20, count 0 2006.257.17:51:12.15#ibcon#read 3, iclass 20, count 0 2006.257.17:51:12.15#ibcon#about to read 4, iclass 20, count 0 2006.257.17:51:12.15#ibcon#read 4, iclass 20, count 0 2006.257.17:51:12.15#ibcon#about to read 5, iclass 20, count 0 2006.257.17:51:12.15#ibcon#read 5, iclass 20, count 0 2006.257.17:51:12.15#ibcon#about to read 6, iclass 20, count 0 2006.257.17:51:12.15#ibcon#read 6, iclass 20, count 0 2006.257.17:51:12.15#ibcon#end of sib2, iclass 20, count 0 2006.257.17:51:12.15#ibcon#*after write, iclass 20, count 0 2006.257.17:51:12.15#ibcon#*before return 0, iclass 20, count 0 2006.257.17:51:12.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:51:12.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.17:51:12.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.17:51:12.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.17:51:12.15$vck44/vblo=1,629.99 2006.257.17:51:12.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.17:51:12.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.17:51:12.15#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:12.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:51:12.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:51:12.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:51:12.15#ibcon#enter wrdev, iclass 22, count 0 2006.257.17:51:12.15#ibcon#first serial, iclass 22, count 0 2006.257.17:51:12.15#ibcon#enter sib2, iclass 22, count 0 2006.257.17:51:12.15#ibcon#flushed, iclass 22, count 0 2006.257.17:51:12.15#ibcon#about to write, iclass 22, count 0 2006.257.17:51:12.15#ibcon#wrote, iclass 22, count 0 2006.257.17:51:12.15#ibcon#about to read 3, iclass 22, count 0 2006.257.17:51:12.17#ibcon#read 3, iclass 22, count 0 2006.257.17:51:12.17#ibcon#about to read 4, iclass 22, count 0 2006.257.17:51:12.17#ibcon#read 4, iclass 22, count 0 2006.257.17:51:12.17#ibcon#about to read 5, iclass 22, count 0 2006.257.17:51:12.17#ibcon#read 5, iclass 22, count 0 2006.257.17:51:12.17#ibcon#about to read 6, iclass 22, count 0 2006.257.17:51:12.17#ibcon#read 6, iclass 22, count 0 2006.257.17:51:12.17#ibcon#end of sib2, iclass 22, count 0 2006.257.17:51:12.17#ibcon#*mode == 0, iclass 22, count 0 2006.257.17:51:12.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.17:51:12.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:51:12.17#ibcon#*before write, iclass 22, count 0 2006.257.17:51:12.17#ibcon#enter sib2, iclass 22, count 0 2006.257.17:51:12.17#ibcon#flushed, iclass 22, count 0 2006.257.17:51:12.17#ibcon#about to write, iclass 22, count 0 2006.257.17:51:12.17#ibcon#wrote, iclass 22, count 0 2006.257.17:51:12.17#ibcon#about to read 3, iclass 22, count 0 2006.257.17:51:12.21#ibcon#read 3, iclass 22, count 0 2006.257.17:51:12.21#ibcon#about to read 4, iclass 22, count 0 2006.257.17:51:12.21#ibcon#read 4, iclass 22, count 0 2006.257.17:51:12.21#ibcon#about to read 5, iclass 22, count 0 2006.257.17:51:12.21#ibcon#read 5, iclass 22, count 0 2006.257.17:51:12.21#ibcon#about to read 6, iclass 22, count 0 2006.257.17:51:12.21#ibcon#read 6, iclass 22, count 0 2006.257.17:51:12.21#ibcon#end of sib2, iclass 22, count 0 2006.257.17:51:12.21#ibcon#*after write, iclass 22, count 0 2006.257.17:51:12.21#ibcon#*before return 0, iclass 22, count 0 2006.257.17:51:12.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:51:12.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.17:51:12.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.17:51:12.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.17:51:12.21$vck44/vb=1,4 2006.257.17:51:12.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.17:51:12.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.17:51:12.21#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:12.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:51:12.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:51:12.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:51:12.21#ibcon#enter wrdev, iclass 24, count 2 2006.257.17:51:12.21#ibcon#first serial, iclass 24, count 2 2006.257.17:51:12.21#ibcon#enter sib2, iclass 24, count 2 2006.257.17:51:12.21#ibcon#flushed, iclass 24, count 2 2006.257.17:51:12.21#ibcon#about to write, iclass 24, count 2 2006.257.17:51:12.21#ibcon#wrote, iclass 24, count 2 2006.257.17:51:12.21#ibcon#about to read 3, iclass 24, count 2 2006.257.17:51:12.23#ibcon#read 3, iclass 24, count 2 2006.257.17:51:12.23#ibcon#about to read 4, iclass 24, count 2 2006.257.17:51:12.23#ibcon#read 4, iclass 24, count 2 2006.257.17:51:12.23#ibcon#about to read 5, iclass 24, count 2 2006.257.17:51:12.23#ibcon#read 5, iclass 24, count 2 2006.257.17:51:12.23#ibcon#about to read 6, iclass 24, count 2 2006.257.17:51:12.23#ibcon#read 6, iclass 24, count 2 2006.257.17:51:12.23#ibcon#end of sib2, iclass 24, count 2 2006.257.17:51:12.23#ibcon#*mode == 0, iclass 24, count 2 2006.257.17:51:12.23#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.17:51:12.23#ibcon#[27=AT01-04\r\n] 2006.257.17:51:12.23#ibcon#*before write, iclass 24, count 2 2006.257.17:51:12.23#ibcon#enter sib2, iclass 24, count 2 2006.257.17:51:12.23#ibcon#flushed, iclass 24, count 2 2006.257.17:51:12.23#ibcon#about to write, iclass 24, count 2 2006.257.17:51:12.23#ibcon#wrote, iclass 24, count 2 2006.257.17:51:12.23#ibcon#about to read 3, iclass 24, count 2 2006.257.17:51:12.26#ibcon#read 3, iclass 24, count 2 2006.257.17:51:12.26#ibcon#about to read 4, iclass 24, count 2 2006.257.17:51:12.26#ibcon#read 4, iclass 24, count 2 2006.257.17:51:12.26#ibcon#about to read 5, iclass 24, count 2 2006.257.17:51:12.26#ibcon#read 5, iclass 24, count 2 2006.257.17:51:12.26#ibcon#about to read 6, iclass 24, count 2 2006.257.17:51:12.26#ibcon#read 6, iclass 24, count 2 2006.257.17:51:12.26#ibcon#end of sib2, iclass 24, count 2 2006.257.17:51:12.26#ibcon#*after write, iclass 24, count 2 2006.257.17:51:12.26#ibcon#*before return 0, iclass 24, count 2 2006.257.17:51:12.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:51:12.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.17:51:12.26#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.17:51:12.26#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:12.26#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:51:12.38#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:51:12.38#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:51:12.38#ibcon#enter wrdev, iclass 24, count 0 2006.257.17:51:12.38#ibcon#first serial, iclass 24, count 0 2006.257.17:51:12.38#ibcon#enter sib2, iclass 24, count 0 2006.257.17:51:12.38#ibcon#flushed, iclass 24, count 0 2006.257.17:51:12.38#ibcon#about to write, iclass 24, count 0 2006.257.17:51:12.38#ibcon#wrote, iclass 24, count 0 2006.257.17:51:12.38#ibcon#about to read 3, iclass 24, count 0 2006.257.17:51:12.40#ibcon#read 3, iclass 24, count 0 2006.257.17:51:12.40#ibcon#about to read 4, iclass 24, count 0 2006.257.17:51:12.40#ibcon#read 4, iclass 24, count 0 2006.257.17:51:12.40#ibcon#about to read 5, iclass 24, count 0 2006.257.17:51:12.40#ibcon#read 5, iclass 24, count 0 2006.257.17:51:12.40#ibcon#about to read 6, iclass 24, count 0 2006.257.17:51:12.40#ibcon#read 6, iclass 24, count 0 2006.257.17:51:12.40#ibcon#end of sib2, iclass 24, count 0 2006.257.17:51:12.40#ibcon#*mode == 0, iclass 24, count 0 2006.257.17:51:12.40#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.17:51:12.40#ibcon#[27=USB\r\n] 2006.257.17:51:12.40#ibcon#*before write, iclass 24, count 0 2006.257.17:51:12.40#ibcon#enter sib2, iclass 24, count 0 2006.257.17:51:12.40#ibcon#flushed, iclass 24, count 0 2006.257.17:51:12.40#ibcon#about to write, iclass 24, count 0 2006.257.17:51:12.40#ibcon#wrote, iclass 24, count 0 2006.257.17:51:12.40#ibcon#about to read 3, iclass 24, count 0 2006.257.17:51:12.43#ibcon#read 3, iclass 24, count 0 2006.257.17:51:12.43#ibcon#about to read 4, iclass 24, count 0 2006.257.17:51:12.43#ibcon#read 4, iclass 24, count 0 2006.257.17:51:12.43#ibcon#about to read 5, iclass 24, count 0 2006.257.17:51:12.43#ibcon#read 5, iclass 24, count 0 2006.257.17:51:12.43#ibcon#about to read 6, iclass 24, count 0 2006.257.17:51:12.43#ibcon#read 6, iclass 24, count 0 2006.257.17:51:12.43#ibcon#end of sib2, iclass 24, count 0 2006.257.17:51:12.43#ibcon#*after write, iclass 24, count 0 2006.257.17:51:12.43#ibcon#*before return 0, iclass 24, count 0 2006.257.17:51:12.43#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:51:12.43#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.17:51:12.43#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.17:51:12.43#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.17:51:12.43$vck44/vblo=2,634.99 2006.257.17:51:12.43#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.17:51:12.43#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.17:51:12.43#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:12.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:12.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:12.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:12.43#ibcon#enter wrdev, iclass 26, count 0 2006.257.17:51:12.43#ibcon#first serial, iclass 26, count 0 2006.257.17:51:12.43#ibcon#enter sib2, iclass 26, count 0 2006.257.17:51:12.43#ibcon#flushed, iclass 26, count 0 2006.257.17:51:12.43#ibcon#about to write, iclass 26, count 0 2006.257.17:51:12.43#ibcon#wrote, iclass 26, count 0 2006.257.17:51:12.43#ibcon#about to read 3, iclass 26, count 0 2006.257.17:51:12.45#ibcon#read 3, iclass 26, count 0 2006.257.17:51:12.45#ibcon#about to read 4, iclass 26, count 0 2006.257.17:51:12.45#ibcon#read 4, iclass 26, count 0 2006.257.17:51:12.45#ibcon#about to read 5, iclass 26, count 0 2006.257.17:51:12.45#ibcon#read 5, iclass 26, count 0 2006.257.17:51:12.45#ibcon#about to read 6, iclass 26, count 0 2006.257.17:51:12.45#ibcon#read 6, iclass 26, count 0 2006.257.17:51:12.45#ibcon#end of sib2, iclass 26, count 0 2006.257.17:51:12.45#ibcon#*mode == 0, iclass 26, count 0 2006.257.17:51:12.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.17:51:12.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:51:12.45#ibcon#*before write, iclass 26, count 0 2006.257.17:51:12.45#ibcon#enter sib2, iclass 26, count 0 2006.257.17:51:12.45#ibcon#flushed, iclass 26, count 0 2006.257.17:51:12.45#ibcon#about to write, iclass 26, count 0 2006.257.17:51:12.45#ibcon#wrote, iclass 26, count 0 2006.257.17:51:12.45#ibcon#about to read 3, iclass 26, count 0 2006.257.17:51:12.49#ibcon#read 3, iclass 26, count 0 2006.257.17:51:12.49#ibcon#about to read 4, iclass 26, count 0 2006.257.17:51:12.49#ibcon#read 4, iclass 26, count 0 2006.257.17:51:12.49#ibcon#about to read 5, iclass 26, count 0 2006.257.17:51:12.49#ibcon#read 5, iclass 26, count 0 2006.257.17:51:12.49#ibcon#about to read 6, iclass 26, count 0 2006.257.17:51:12.49#ibcon#read 6, iclass 26, count 0 2006.257.17:51:12.49#ibcon#end of sib2, iclass 26, count 0 2006.257.17:51:12.49#ibcon#*after write, iclass 26, count 0 2006.257.17:51:12.49#ibcon#*before return 0, iclass 26, count 0 2006.257.17:51:12.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:12.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.17:51:12.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.17:51:12.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.17:51:12.49$vck44/vb=2,5 2006.257.17:51:12.49#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.17:51:12.49#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.17:51:12.49#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:12.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:12.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:12.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:12.55#ibcon#enter wrdev, iclass 28, count 2 2006.257.17:51:12.55#ibcon#first serial, iclass 28, count 2 2006.257.17:51:12.55#ibcon#enter sib2, iclass 28, count 2 2006.257.17:51:12.55#ibcon#flushed, iclass 28, count 2 2006.257.17:51:12.55#ibcon#about to write, iclass 28, count 2 2006.257.17:51:12.55#ibcon#wrote, iclass 28, count 2 2006.257.17:51:12.55#ibcon#about to read 3, iclass 28, count 2 2006.257.17:51:12.57#ibcon#read 3, iclass 28, count 2 2006.257.17:51:12.57#ibcon#about to read 4, iclass 28, count 2 2006.257.17:51:12.57#ibcon#read 4, iclass 28, count 2 2006.257.17:51:12.57#ibcon#about to read 5, iclass 28, count 2 2006.257.17:51:12.57#ibcon#read 5, iclass 28, count 2 2006.257.17:51:12.57#ibcon#about to read 6, iclass 28, count 2 2006.257.17:51:12.57#ibcon#read 6, iclass 28, count 2 2006.257.17:51:12.57#ibcon#end of sib2, iclass 28, count 2 2006.257.17:51:12.57#ibcon#*mode == 0, iclass 28, count 2 2006.257.17:51:12.57#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.17:51:12.57#ibcon#[27=AT02-05\r\n] 2006.257.17:51:12.57#ibcon#*before write, iclass 28, count 2 2006.257.17:51:12.57#ibcon#enter sib2, iclass 28, count 2 2006.257.17:51:12.57#ibcon#flushed, iclass 28, count 2 2006.257.17:51:12.57#ibcon#about to write, iclass 28, count 2 2006.257.17:51:12.57#ibcon#wrote, iclass 28, count 2 2006.257.17:51:12.57#ibcon#about to read 3, iclass 28, count 2 2006.257.17:51:12.60#ibcon#read 3, iclass 28, count 2 2006.257.17:51:12.60#ibcon#about to read 4, iclass 28, count 2 2006.257.17:51:12.60#ibcon#read 4, iclass 28, count 2 2006.257.17:51:12.60#ibcon#about to read 5, iclass 28, count 2 2006.257.17:51:12.60#ibcon#read 5, iclass 28, count 2 2006.257.17:51:12.60#ibcon#about to read 6, iclass 28, count 2 2006.257.17:51:12.60#ibcon#read 6, iclass 28, count 2 2006.257.17:51:12.60#ibcon#end of sib2, iclass 28, count 2 2006.257.17:51:12.60#ibcon#*after write, iclass 28, count 2 2006.257.17:51:12.60#ibcon#*before return 0, iclass 28, count 2 2006.257.17:51:12.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:12.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.17:51:12.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.17:51:12.60#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:12.60#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:12.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:12.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:12.72#ibcon#enter wrdev, iclass 28, count 0 2006.257.17:51:12.72#ibcon#first serial, iclass 28, count 0 2006.257.17:51:12.72#ibcon#enter sib2, iclass 28, count 0 2006.257.17:51:12.72#ibcon#flushed, iclass 28, count 0 2006.257.17:51:12.72#ibcon#about to write, iclass 28, count 0 2006.257.17:51:12.72#ibcon#wrote, iclass 28, count 0 2006.257.17:51:12.72#ibcon#about to read 3, iclass 28, count 0 2006.257.17:51:12.74#ibcon#read 3, iclass 28, count 0 2006.257.17:51:12.74#ibcon#about to read 4, iclass 28, count 0 2006.257.17:51:12.74#ibcon#read 4, iclass 28, count 0 2006.257.17:51:12.74#ibcon#about to read 5, iclass 28, count 0 2006.257.17:51:12.74#ibcon#read 5, iclass 28, count 0 2006.257.17:51:12.74#ibcon#about to read 6, iclass 28, count 0 2006.257.17:51:12.74#ibcon#read 6, iclass 28, count 0 2006.257.17:51:12.74#ibcon#end of sib2, iclass 28, count 0 2006.257.17:51:12.74#ibcon#*mode == 0, iclass 28, count 0 2006.257.17:51:12.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.17:51:12.74#ibcon#[27=USB\r\n] 2006.257.17:51:12.74#ibcon#*before write, iclass 28, count 0 2006.257.17:51:12.74#ibcon#enter sib2, iclass 28, count 0 2006.257.17:51:12.74#ibcon#flushed, iclass 28, count 0 2006.257.17:51:12.74#ibcon#about to write, iclass 28, count 0 2006.257.17:51:12.74#ibcon#wrote, iclass 28, count 0 2006.257.17:51:12.74#ibcon#about to read 3, iclass 28, count 0 2006.257.17:51:12.77#ibcon#read 3, iclass 28, count 0 2006.257.17:51:12.77#ibcon#about to read 4, iclass 28, count 0 2006.257.17:51:12.77#ibcon#read 4, iclass 28, count 0 2006.257.17:51:12.77#ibcon#about to read 5, iclass 28, count 0 2006.257.17:51:12.77#ibcon#read 5, iclass 28, count 0 2006.257.17:51:12.77#ibcon#about to read 6, iclass 28, count 0 2006.257.17:51:12.77#ibcon#read 6, iclass 28, count 0 2006.257.17:51:12.77#ibcon#end of sib2, iclass 28, count 0 2006.257.17:51:12.77#ibcon#*after write, iclass 28, count 0 2006.257.17:51:12.77#ibcon#*before return 0, iclass 28, count 0 2006.257.17:51:12.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:12.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.17:51:12.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.17:51:12.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.17:51:12.77$vck44/vblo=3,649.99 2006.257.17:51:12.77#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.17:51:12.77#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.17:51:12.77#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:12.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:12.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:12.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:12.77#ibcon#enter wrdev, iclass 30, count 0 2006.257.17:51:12.77#ibcon#first serial, iclass 30, count 0 2006.257.17:51:12.77#ibcon#enter sib2, iclass 30, count 0 2006.257.17:51:12.77#ibcon#flushed, iclass 30, count 0 2006.257.17:51:12.77#ibcon#about to write, iclass 30, count 0 2006.257.17:51:12.77#ibcon#wrote, iclass 30, count 0 2006.257.17:51:12.77#ibcon#about to read 3, iclass 30, count 0 2006.257.17:51:12.79#ibcon#read 3, iclass 30, count 0 2006.257.17:51:12.79#ibcon#about to read 4, iclass 30, count 0 2006.257.17:51:12.79#ibcon#read 4, iclass 30, count 0 2006.257.17:51:12.79#ibcon#about to read 5, iclass 30, count 0 2006.257.17:51:12.79#ibcon#read 5, iclass 30, count 0 2006.257.17:51:12.79#ibcon#about to read 6, iclass 30, count 0 2006.257.17:51:12.79#ibcon#read 6, iclass 30, count 0 2006.257.17:51:12.79#ibcon#end of sib2, iclass 30, count 0 2006.257.17:51:12.79#ibcon#*mode == 0, iclass 30, count 0 2006.257.17:51:12.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.17:51:12.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:51:12.79#ibcon#*before write, iclass 30, count 0 2006.257.17:51:12.79#ibcon#enter sib2, iclass 30, count 0 2006.257.17:51:12.79#ibcon#flushed, iclass 30, count 0 2006.257.17:51:12.79#ibcon#about to write, iclass 30, count 0 2006.257.17:51:12.79#ibcon#wrote, iclass 30, count 0 2006.257.17:51:12.79#ibcon#about to read 3, iclass 30, count 0 2006.257.17:51:12.83#ibcon#read 3, iclass 30, count 0 2006.257.17:51:12.83#ibcon#about to read 4, iclass 30, count 0 2006.257.17:51:12.83#ibcon#read 4, iclass 30, count 0 2006.257.17:51:12.83#ibcon#about to read 5, iclass 30, count 0 2006.257.17:51:12.83#ibcon#read 5, iclass 30, count 0 2006.257.17:51:12.83#ibcon#about to read 6, iclass 30, count 0 2006.257.17:51:12.83#ibcon#read 6, iclass 30, count 0 2006.257.17:51:12.83#ibcon#end of sib2, iclass 30, count 0 2006.257.17:51:12.83#ibcon#*after write, iclass 30, count 0 2006.257.17:51:12.83#ibcon#*before return 0, iclass 30, count 0 2006.257.17:51:12.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:12.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.17:51:12.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.17:51:12.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.17:51:12.83$vck44/vb=3,4 2006.257.17:51:12.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.17:51:12.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.17:51:12.83#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:12.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:12.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:12.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:12.89#ibcon#enter wrdev, iclass 32, count 2 2006.257.17:51:12.89#ibcon#first serial, iclass 32, count 2 2006.257.17:51:12.89#ibcon#enter sib2, iclass 32, count 2 2006.257.17:51:12.89#ibcon#flushed, iclass 32, count 2 2006.257.17:51:12.89#ibcon#about to write, iclass 32, count 2 2006.257.17:51:12.89#ibcon#wrote, iclass 32, count 2 2006.257.17:51:12.89#ibcon#about to read 3, iclass 32, count 2 2006.257.17:51:12.91#ibcon#read 3, iclass 32, count 2 2006.257.17:51:12.91#ibcon#about to read 4, iclass 32, count 2 2006.257.17:51:12.91#ibcon#read 4, iclass 32, count 2 2006.257.17:51:12.91#ibcon#about to read 5, iclass 32, count 2 2006.257.17:51:12.91#ibcon#read 5, iclass 32, count 2 2006.257.17:51:12.91#ibcon#about to read 6, iclass 32, count 2 2006.257.17:51:12.91#ibcon#read 6, iclass 32, count 2 2006.257.17:51:12.91#ibcon#end of sib2, iclass 32, count 2 2006.257.17:51:12.91#ibcon#*mode == 0, iclass 32, count 2 2006.257.17:51:12.91#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.17:51:12.91#ibcon#[27=AT03-04\r\n] 2006.257.17:51:12.91#ibcon#*before write, iclass 32, count 2 2006.257.17:51:12.91#ibcon#enter sib2, iclass 32, count 2 2006.257.17:51:12.91#ibcon#flushed, iclass 32, count 2 2006.257.17:51:12.91#ibcon#about to write, iclass 32, count 2 2006.257.17:51:12.91#ibcon#wrote, iclass 32, count 2 2006.257.17:51:12.91#ibcon#about to read 3, iclass 32, count 2 2006.257.17:51:12.94#ibcon#read 3, iclass 32, count 2 2006.257.17:51:12.94#ibcon#about to read 4, iclass 32, count 2 2006.257.17:51:12.94#ibcon#read 4, iclass 32, count 2 2006.257.17:51:12.94#ibcon#about to read 5, iclass 32, count 2 2006.257.17:51:12.94#ibcon#read 5, iclass 32, count 2 2006.257.17:51:12.94#ibcon#about to read 6, iclass 32, count 2 2006.257.17:51:12.94#ibcon#read 6, iclass 32, count 2 2006.257.17:51:12.94#ibcon#end of sib2, iclass 32, count 2 2006.257.17:51:12.94#ibcon#*after write, iclass 32, count 2 2006.257.17:51:12.94#ibcon#*before return 0, iclass 32, count 2 2006.257.17:51:12.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:12.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.17:51:12.94#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.17:51:12.94#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:12.94#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:13.06#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:13.06#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:13.06#ibcon#enter wrdev, iclass 32, count 0 2006.257.17:51:13.06#ibcon#first serial, iclass 32, count 0 2006.257.17:51:13.06#ibcon#enter sib2, iclass 32, count 0 2006.257.17:51:13.06#ibcon#flushed, iclass 32, count 0 2006.257.17:51:13.06#ibcon#about to write, iclass 32, count 0 2006.257.17:51:13.06#ibcon#wrote, iclass 32, count 0 2006.257.17:51:13.06#ibcon#about to read 3, iclass 32, count 0 2006.257.17:51:13.08#ibcon#read 3, iclass 32, count 0 2006.257.17:51:13.08#ibcon#about to read 4, iclass 32, count 0 2006.257.17:51:13.08#ibcon#read 4, iclass 32, count 0 2006.257.17:51:13.08#ibcon#about to read 5, iclass 32, count 0 2006.257.17:51:13.08#ibcon#read 5, iclass 32, count 0 2006.257.17:51:13.08#ibcon#about to read 6, iclass 32, count 0 2006.257.17:51:13.08#ibcon#read 6, iclass 32, count 0 2006.257.17:51:13.08#ibcon#end of sib2, iclass 32, count 0 2006.257.17:51:13.08#ibcon#*mode == 0, iclass 32, count 0 2006.257.17:51:13.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.17:51:13.08#ibcon#[27=USB\r\n] 2006.257.17:51:13.08#ibcon#*before write, iclass 32, count 0 2006.257.17:51:13.08#ibcon#enter sib2, iclass 32, count 0 2006.257.17:51:13.08#ibcon#flushed, iclass 32, count 0 2006.257.17:51:13.08#ibcon#about to write, iclass 32, count 0 2006.257.17:51:13.08#ibcon#wrote, iclass 32, count 0 2006.257.17:51:13.08#ibcon#about to read 3, iclass 32, count 0 2006.257.17:51:13.11#ibcon#read 3, iclass 32, count 0 2006.257.17:51:13.11#ibcon#about to read 4, iclass 32, count 0 2006.257.17:51:13.11#ibcon#read 4, iclass 32, count 0 2006.257.17:51:13.11#ibcon#about to read 5, iclass 32, count 0 2006.257.17:51:13.11#ibcon#read 5, iclass 32, count 0 2006.257.17:51:13.11#ibcon#about to read 6, iclass 32, count 0 2006.257.17:51:13.11#ibcon#read 6, iclass 32, count 0 2006.257.17:51:13.11#ibcon#end of sib2, iclass 32, count 0 2006.257.17:51:13.11#ibcon#*after write, iclass 32, count 0 2006.257.17:51:13.11#ibcon#*before return 0, iclass 32, count 0 2006.257.17:51:13.11#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:13.11#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.17:51:13.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.17:51:13.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.17:51:13.11$vck44/vblo=4,679.99 2006.257.17:51:13.11#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.17:51:13.11#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.17:51:13.11#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:13.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:13.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:13.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:13.11#ibcon#enter wrdev, iclass 34, count 0 2006.257.17:51:13.11#ibcon#first serial, iclass 34, count 0 2006.257.17:51:13.11#ibcon#enter sib2, iclass 34, count 0 2006.257.17:51:13.11#ibcon#flushed, iclass 34, count 0 2006.257.17:51:13.11#ibcon#about to write, iclass 34, count 0 2006.257.17:51:13.11#ibcon#wrote, iclass 34, count 0 2006.257.17:51:13.11#ibcon#about to read 3, iclass 34, count 0 2006.257.17:51:13.13#ibcon#read 3, iclass 34, count 0 2006.257.17:51:13.13#ibcon#about to read 4, iclass 34, count 0 2006.257.17:51:13.13#ibcon#read 4, iclass 34, count 0 2006.257.17:51:13.13#ibcon#about to read 5, iclass 34, count 0 2006.257.17:51:13.13#ibcon#read 5, iclass 34, count 0 2006.257.17:51:13.13#ibcon#about to read 6, iclass 34, count 0 2006.257.17:51:13.13#ibcon#read 6, iclass 34, count 0 2006.257.17:51:13.13#ibcon#end of sib2, iclass 34, count 0 2006.257.17:51:13.13#ibcon#*mode == 0, iclass 34, count 0 2006.257.17:51:13.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.17:51:13.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:51:13.13#ibcon#*before write, iclass 34, count 0 2006.257.17:51:13.13#ibcon#enter sib2, iclass 34, count 0 2006.257.17:51:13.13#ibcon#flushed, iclass 34, count 0 2006.257.17:51:13.13#ibcon#about to write, iclass 34, count 0 2006.257.17:51:13.13#ibcon#wrote, iclass 34, count 0 2006.257.17:51:13.13#ibcon#about to read 3, iclass 34, count 0 2006.257.17:51:13.17#ibcon#read 3, iclass 34, count 0 2006.257.17:51:13.17#ibcon#about to read 4, iclass 34, count 0 2006.257.17:51:13.17#ibcon#read 4, iclass 34, count 0 2006.257.17:51:13.17#ibcon#about to read 5, iclass 34, count 0 2006.257.17:51:13.17#ibcon#read 5, iclass 34, count 0 2006.257.17:51:13.17#ibcon#about to read 6, iclass 34, count 0 2006.257.17:51:13.17#ibcon#read 6, iclass 34, count 0 2006.257.17:51:13.17#ibcon#end of sib2, iclass 34, count 0 2006.257.17:51:13.17#ibcon#*after write, iclass 34, count 0 2006.257.17:51:13.17#ibcon#*before return 0, iclass 34, count 0 2006.257.17:51:13.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:13.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.17:51:13.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.17:51:13.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.17:51:13.17$vck44/vb=4,5 2006.257.17:51:13.17#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.17:51:13.17#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.17:51:13.17#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:13.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:13.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:13.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:13.23#ibcon#enter wrdev, iclass 36, count 2 2006.257.17:51:13.23#ibcon#first serial, iclass 36, count 2 2006.257.17:51:13.23#ibcon#enter sib2, iclass 36, count 2 2006.257.17:51:13.23#ibcon#flushed, iclass 36, count 2 2006.257.17:51:13.23#ibcon#about to write, iclass 36, count 2 2006.257.17:51:13.23#ibcon#wrote, iclass 36, count 2 2006.257.17:51:13.23#ibcon#about to read 3, iclass 36, count 2 2006.257.17:51:13.25#ibcon#read 3, iclass 36, count 2 2006.257.17:51:13.25#ibcon#about to read 4, iclass 36, count 2 2006.257.17:51:13.25#ibcon#read 4, iclass 36, count 2 2006.257.17:51:13.25#ibcon#about to read 5, iclass 36, count 2 2006.257.17:51:13.25#ibcon#read 5, iclass 36, count 2 2006.257.17:51:13.25#ibcon#about to read 6, iclass 36, count 2 2006.257.17:51:13.25#ibcon#read 6, iclass 36, count 2 2006.257.17:51:13.25#ibcon#end of sib2, iclass 36, count 2 2006.257.17:51:13.25#ibcon#*mode == 0, iclass 36, count 2 2006.257.17:51:13.25#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.17:51:13.25#ibcon#[27=AT04-05\r\n] 2006.257.17:51:13.25#ibcon#*before write, iclass 36, count 2 2006.257.17:51:13.25#ibcon#enter sib2, iclass 36, count 2 2006.257.17:51:13.25#ibcon#flushed, iclass 36, count 2 2006.257.17:51:13.25#ibcon#about to write, iclass 36, count 2 2006.257.17:51:13.25#ibcon#wrote, iclass 36, count 2 2006.257.17:51:13.25#ibcon#about to read 3, iclass 36, count 2 2006.257.17:51:13.28#ibcon#read 3, iclass 36, count 2 2006.257.17:51:13.28#ibcon#about to read 4, iclass 36, count 2 2006.257.17:51:13.28#ibcon#read 4, iclass 36, count 2 2006.257.17:51:13.28#ibcon#about to read 5, iclass 36, count 2 2006.257.17:51:13.28#ibcon#read 5, iclass 36, count 2 2006.257.17:51:13.28#ibcon#about to read 6, iclass 36, count 2 2006.257.17:51:13.28#ibcon#read 6, iclass 36, count 2 2006.257.17:51:13.28#ibcon#end of sib2, iclass 36, count 2 2006.257.17:51:13.28#ibcon#*after write, iclass 36, count 2 2006.257.17:51:13.28#ibcon#*before return 0, iclass 36, count 2 2006.257.17:51:13.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:13.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.17:51:13.28#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.17:51:13.28#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:13.28#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:13.40#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:13.40#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:13.40#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:51:13.40#ibcon#first serial, iclass 36, count 0 2006.257.17:51:13.40#ibcon#enter sib2, iclass 36, count 0 2006.257.17:51:13.40#ibcon#flushed, iclass 36, count 0 2006.257.17:51:13.40#ibcon#about to write, iclass 36, count 0 2006.257.17:51:13.40#ibcon#wrote, iclass 36, count 0 2006.257.17:51:13.40#ibcon#about to read 3, iclass 36, count 0 2006.257.17:51:13.42#ibcon#read 3, iclass 36, count 0 2006.257.17:51:13.42#ibcon#about to read 4, iclass 36, count 0 2006.257.17:51:13.42#ibcon#read 4, iclass 36, count 0 2006.257.17:51:13.42#ibcon#about to read 5, iclass 36, count 0 2006.257.17:51:13.42#ibcon#read 5, iclass 36, count 0 2006.257.17:51:13.42#ibcon#about to read 6, iclass 36, count 0 2006.257.17:51:13.42#ibcon#read 6, iclass 36, count 0 2006.257.17:51:13.42#ibcon#end of sib2, iclass 36, count 0 2006.257.17:51:13.42#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:51:13.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:51:13.42#ibcon#[27=USB\r\n] 2006.257.17:51:13.42#ibcon#*before write, iclass 36, count 0 2006.257.17:51:13.42#ibcon#enter sib2, iclass 36, count 0 2006.257.17:51:13.42#ibcon#flushed, iclass 36, count 0 2006.257.17:51:13.42#ibcon#about to write, iclass 36, count 0 2006.257.17:51:13.42#ibcon#wrote, iclass 36, count 0 2006.257.17:51:13.42#ibcon#about to read 3, iclass 36, count 0 2006.257.17:51:13.45#ibcon#read 3, iclass 36, count 0 2006.257.17:51:13.45#ibcon#about to read 4, iclass 36, count 0 2006.257.17:51:13.45#ibcon#read 4, iclass 36, count 0 2006.257.17:51:13.45#ibcon#about to read 5, iclass 36, count 0 2006.257.17:51:13.45#ibcon#read 5, iclass 36, count 0 2006.257.17:51:13.45#ibcon#about to read 6, iclass 36, count 0 2006.257.17:51:13.45#ibcon#read 6, iclass 36, count 0 2006.257.17:51:13.45#ibcon#end of sib2, iclass 36, count 0 2006.257.17:51:13.45#ibcon#*after write, iclass 36, count 0 2006.257.17:51:13.45#ibcon#*before return 0, iclass 36, count 0 2006.257.17:51:13.45#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:13.45#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.17:51:13.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:51:13.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:51:13.45$vck44/vblo=5,709.99 2006.257.17:51:13.45#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.17:51:13.45#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.17:51:13.45#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:13.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:13.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:13.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:13.45#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:51:13.45#ibcon#first serial, iclass 38, count 0 2006.257.17:51:13.45#ibcon#enter sib2, iclass 38, count 0 2006.257.17:51:13.45#ibcon#flushed, iclass 38, count 0 2006.257.17:51:13.45#ibcon#about to write, iclass 38, count 0 2006.257.17:51:13.45#ibcon#wrote, iclass 38, count 0 2006.257.17:51:13.45#ibcon#about to read 3, iclass 38, count 0 2006.257.17:51:13.47#ibcon#read 3, iclass 38, count 0 2006.257.17:51:13.47#ibcon#about to read 4, iclass 38, count 0 2006.257.17:51:13.47#ibcon#read 4, iclass 38, count 0 2006.257.17:51:13.47#ibcon#about to read 5, iclass 38, count 0 2006.257.17:51:13.47#ibcon#read 5, iclass 38, count 0 2006.257.17:51:13.47#ibcon#about to read 6, iclass 38, count 0 2006.257.17:51:13.47#ibcon#read 6, iclass 38, count 0 2006.257.17:51:13.47#ibcon#end of sib2, iclass 38, count 0 2006.257.17:51:13.47#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:51:13.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:51:13.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:51:13.47#ibcon#*before write, iclass 38, count 0 2006.257.17:51:13.47#ibcon#enter sib2, iclass 38, count 0 2006.257.17:51:13.47#ibcon#flushed, iclass 38, count 0 2006.257.17:51:13.47#ibcon#about to write, iclass 38, count 0 2006.257.17:51:13.47#ibcon#wrote, iclass 38, count 0 2006.257.17:51:13.47#ibcon#about to read 3, iclass 38, count 0 2006.257.17:51:13.51#ibcon#read 3, iclass 38, count 0 2006.257.17:51:13.51#ibcon#about to read 4, iclass 38, count 0 2006.257.17:51:13.51#ibcon#read 4, iclass 38, count 0 2006.257.17:51:13.51#ibcon#about to read 5, iclass 38, count 0 2006.257.17:51:13.51#ibcon#read 5, iclass 38, count 0 2006.257.17:51:13.51#ibcon#about to read 6, iclass 38, count 0 2006.257.17:51:13.51#ibcon#read 6, iclass 38, count 0 2006.257.17:51:13.51#ibcon#end of sib2, iclass 38, count 0 2006.257.17:51:13.51#ibcon#*after write, iclass 38, count 0 2006.257.17:51:13.51#ibcon#*before return 0, iclass 38, count 0 2006.257.17:51:13.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:13.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.17:51:13.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:51:13.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:51:13.51$vck44/vb=5,4 2006.257.17:51:13.51#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.17:51:13.51#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.17:51:13.51#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:13.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:13.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:13.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:13.57#ibcon#enter wrdev, iclass 40, count 2 2006.257.17:51:13.57#ibcon#first serial, iclass 40, count 2 2006.257.17:51:13.57#ibcon#enter sib2, iclass 40, count 2 2006.257.17:51:13.57#ibcon#flushed, iclass 40, count 2 2006.257.17:51:13.57#ibcon#about to write, iclass 40, count 2 2006.257.17:51:13.57#ibcon#wrote, iclass 40, count 2 2006.257.17:51:13.57#ibcon#about to read 3, iclass 40, count 2 2006.257.17:51:13.59#ibcon#read 3, iclass 40, count 2 2006.257.17:51:13.59#ibcon#about to read 4, iclass 40, count 2 2006.257.17:51:13.59#ibcon#read 4, iclass 40, count 2 2006.257.17:51:13.59#ibcon#about to read 5, iclass 40, count 2 2006.257.17:51:13.59#ibcon#read 5, iclass 40, count 2 2006.257.17:51:13.59#ibcon#about to read 6, iclass 40, count 2 2006.257.17:51:13.59#ibcon#read 6, iclass 40, count 2 2006.257.17:51:13.59#ibcon#end of sib2, iclass 40, count 2 2006.257.17:51:13.59#ibcon#*mode == 0, iclass 40, count 2 2006.257.17:51:13.59#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.17:51:13.59#ibcon#[27=AT05-04\r\n] 2006.257.17:51:13.59#ibcon#*before write, iclass 40, count 2 2006.257.17:51:13.59#ibcon#enter sib2, iclass 40, count 2 2006.257.17:51:13.59#ibcon#flushed, iclass 40, count 2 2006.257.17:51:13.59#ibcon#about to write, iclass 40, count 2 2006.257.17:51:13.59#ibcon#wrote, iclass 40, count 2 2006.257.17:51:13.59#ibcon#about to read 3, iclass 40, count 2 2006.257.17:51:13.62#ibcon#read 3, iclass 40, count 2 2006.257.17:51:13.62#ibcon#about to read 4, iclass 40, count 2 2006.257.17:51:13.62#ibcon#read 4, iclass 40, count 2 2006.257.17:51:13.62#ibcon#about to read 5, iclass 40, count 2 2006.257.17:51:13.62#ibcon#read 5, iclass 40, count 2 2006.257.17:51:13.62#ibcon#about to read 6, iclass 40, count 2 2006.257.17:51:13.62#ibcon#read 6, iclass 40, count 2 2006.257.17:51:13.62#ibcon#end of sib2, iclass 40, count 2 2006.257.17:51:13.62#ibcon#*after write, iclass 40, count 2 2006.257.17:51:13.62#ibcon#*before return 0, iclass 40, count 2 2006.257.17:51:13.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:13.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.17:51:13.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.17:51:13.62#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:13.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:13.74#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:13.74#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:13.74#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:51:13.74#ibcon#first serial, iclass 40, count 0 2006.257.17:51:13.74#ibcon#enter sib2, iclass 40, count 0 2006.257.17:51:13.74#ibcon#flushed, iclass 40, count 0 2006.257.17:51:13.74#ibcon#about to write, iclass 40, count 0 2006.257.17:51:13.74#ibcon#wrote, iclass 40, count 0 2006.257.17:51:13.74#ibcon#about to read 3, iclass 40, count 0 2006.257.17:51:13.76#ibcon#read 3, iclass 40, count 0 2006.257.17:51:13.76#ibcon#about to read 4, iclass 40, count 0 2006.257.17:51:13.76#ibcon#read 4, iclass 40, count 0 2006.257.17:51:13.76#ibcon#about to read 5, iclass 40, count 0 2006.257.17:51:13.76#ibcon#read 5, iclass 40, count 0 2006.257.17:51:13.76#ibcon#about to read 6, iclass 40, count 0 2006.257.17:51:13.76#ibcon#read 6, iclass 40, count 0 2006.257.17:51:13.76#ibcon#end of sib2, iclass 40, count 0 2006.257.17:51:13.76#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:51:13.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:51:13.76#ibcon#[27=USB\r\n] 2006.257.17:51:13.76#ibcon#*before write, iclass 40, count 0 2006.257.17:51:13.76#ibcon#enter sib2, iclass 40, count 0 2006.257.17:51:13.76#ibcon#flushed, iclass 40, count 0 2006.257.17:51:13.76#ibcon#about to write, iclass 40, count 0 2006.257.17:51:13.76#ibcon#wrote, iclass 40, count 0 2006.257.17:51:13.76#ibcon#about to read 3, iclass 40, count 0 2006.257.17:51:13.79#ibcon#read 3, iclass 40, count 0 2006.257.17:51:13.79#ibcon#about to read 4, iclass 40, count 0 2006.257.17:51:13.79#ibcon#read 4, iclass 40, count 0 2006.257.17:51:13.79#ibcon#about to read 5, iclass 40, count 0 2006.257.17:51:13.79#ibcon#read 5, iclass 40, count 0 2006.257.17:51:13.79#ibcon#about to read 6, iclass 40, count 0 2006.257.17:51:13.79#ibcon#read 6, iclass 40, count 0 2006.257.17:51:13.79#ibcon#end of sib2, iclass 40, count 0 2006.257.17:51:13.79#ibcon#*after write, iclass 40, count 0 2006.257.17:51:13.79#ibcon#*before return 0, iclass 40, count 0 2006.257.17:51:13.79#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:13.79#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.17:51:13.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:51:13.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:51:13.79$vck44/vblo=6,719.99 2006.257.17:51:13.79#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.17:51:13.79#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.17:51:13.79#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:13.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:13.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:13.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:13.79#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:51:13.79#ibcon#first serial, iclass 4, count 0 2006.257.17:51:13.79#ibcon#enter sib2, iclass 4, count 0 2006.257.17:51:13.79#ibcon#flushed, iclass 4, count 0 2006.257.17:51:13.79#ibcon#about to write, iclass 4, count 0 2006.257.17:51:13.79#ibcon#wrote, iclass 4, count 0 2006.257.17:51:13.79#ibcon#about to read 3, iclass 4, count 0 2006.257.17:51:13.81#ibcon#read 3, iclass 4, count 0 2006.257.17:51:13.81#ibcon#about to read 4, iclass 4, count 0 2006.257.17:51:13.81#ibcon#read 4, iclass 4, count 0 2006.257.17:51:13.81#ibcon#about to read 5, iclass 4, count 0 2006.257.17:51:13.81#ibcon#read 5, iclass 4, count 0 2006.257.17:51:13.81#ibcon#about to read 6, iclass 4, count 0 2006.257.17:51:13.81#ibcon#read 6, iclass 4, count 0 2006.257.17:51:13.81#ibcon#end of sib2, iclass 4, count 0 2006.257.17:51:13.81#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:51:13.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:51:13.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:51:13.81#ibcon#*before write, iclass 4, count 0 2006.257.17:51:13.81#ibcon#enter sib2, iclass 4, count 0 2006.257.17:51:13.81#ibcon#flushed, iclass 4, count 0 2006.257.17:51:13.81#ibcon#about to write, iclass 4, count 0 2006.257.17:51:13.81#ibcon#wrote, iclass 4, count 0 2006.257.17:51:13.81#ibcon#about to read 3, iclass 4, count 0 2006.257.17:51:13.85#ibcon#read 3, iclass 4, count 0 2006.257.17:51:13.85#ibcon#about to read 4, iclass 4, count 0 2006.257.17:51:13.85#ibcon#read 4, iclass 4, count 0 2006.257.17:51:13.85#ibcon#about to read 5, iclass 4, count 0 2006.257.17:51:13.85#ibcon#read 5, iclass 4, count 0 2006.257.17:51:13.85#ibcon#about to read 6, iclass 4, count 0 2006.257.17:51:13.85#ibcon#read 6, iclass 4, count 0 2006.257.17:51:13.85#ibcon#end of sib2, iclass 4, count 0 2006.257.17:51:13.85#ibcon#*after write, iclass 4, count 0 2006.257.17:51:13.85#ibcon#*before return 0, iclass 4, count 0 2006.257.17:51:13.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:13.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.17:51:13.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:51:13.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:51:13.85$vck44/vb=6,4 2006.257.17:51:13.85#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.17:51:13.85#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.17:51:13.85#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:13.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:13.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:13.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:13.91#ibcon#enter wrdev, iclass 6, count 2 2006.257.17:51:13.91#ibcon#first serial, iclass 6, count 2 2006.257.17:51:13.91#ibcon#enter sib2, iclass 6, count 2 2006.257.17:51:13.91#ibcon#flushed, iclass 6, count 2 2006.257.17:51:13.91#ibcon#about to write, iclass 6, count 2 2006.257.17:51:13.91#ibcon#wrote, iclass 6, count 2 2006.257.17:51:13.91#ibcon#about to read 3, iclass 6, count 2 2006.257.17:51:13.93#ibcon#read 3, iclass 6, count 2 2006.257.17:51:13.93#ibcon#about to read 4, iclass 6, count 2 2006.257.17:51:13.93#ibcon#read 4, iclass 6, count 2 2006.257.17:51:13.93#ibcon#about to read 5, iclass 6, count 2 2006.257.17:51:13.93#ibcon#read 5, iclass 6, count 2 2006.257.17:51:13.93#ibcon#about to read 6, iclass 6, count 2 2006.257.17:51:13.93#ibcon#read 6, iclass 6, count 2 2006.257.17:51:13.93#ibcon#end of sib2, iclass 6, count 2 2006.257.17:51:13.93#ibcon#*mode == 0, iclass 6, count 2 2006.257.17:51:13.93#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.17:51:13.93#ibcon#[27=AT06-04\r\n] 2006.257.17:51:13.93#ibcon#*before write, iclass 6, count 2 2006.257.17:51:13.93#ibcon#enter sib2, iclass 6, count 2 2006.257.17:51:13.93#ibcon#flushed, iclass 6, count 2 2006.257.17:51:13.93#ibcon#about to write, iclass 6, count 2 2006.257.17:51:13.93#ibcon#wrote, iclass 6, count 2 2006.257.17:51:13.93#ibcon#about to read 3, iclass 6, count 2 2006.257.17:51:13.96#ibcon#read 3, iclass 6, count 2 2006.257.17:51:13.96#ibcon#about to read 4, iclass 6, count 2 2006.257.17:51:13.96#ibcon#read 4, iclass 6, count 2 2006.257.17:51:13.96#ibcon#about to read 5, iclass 6, count 2 2006.257.17:51:13.96#ibcon#read 5, iclass 6, count 2 2006.257.17:51:13.96#ibcon#about to read 6, iclass 6, count 2 2006.257.17:51:13.96#ibcon#read 6, iclass 6, count 2 2006.257.17:51:13.96#ibcon#end of sib2, iclass 6, count 2 2006.257.17:51:13.96#ibcon#*after write, iclass 6, count 2 2006.257.17:51:13.96#ibcon#*before return 0, iclass 6, count 2 2006.257.17:51:13.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:13.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.17:51:13.96#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.17:51:13.96#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:13.96#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:14.08#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:14.08#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:14.08#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:51:14.08#ibcon#first serial, iclass 6, count 0 2006.257.17:51:14.08#ibcon#enter sib2, iclass 6, count 0 2006.257.17:51:14.08#ibcon#flushed, iclass 6, count 0 2006.257.17:51:14.08#ibcon#about to write, iclass 6, count 0 2006.257.17:51:14.08#ibcon#wrote, iclass 6, count 0 2006.257.17:51:14.08#ibcon#about to read 3, iclass 6, count 0 2006.257.17:51:14.10#ibcon#read 3, iclass 6, count 0 2006.257.17:51:14.10#ibcon#about to read 4, iclass 6, count 0 2006.257.17:51:14.10#ibcon#read 4, iclass 6, count 0 2006.257.17:51:14.10#ibcon#about to read 5, iclass 6, count 0 2006.257.17:51:14.10#ibcon#read 5, iclass 6, count 0 2006.257.17:51:14.10#ibcon#about to read 6, iclass 6, count 0 2006.257.17:51:14.10#ibcon#read 6, iclass 6, count 0 2006.257.17:51:14.10#ibcon#end of sib2, iclass 6, count 0 2006.257.17:51:14.10#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:51:14.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:51:14.10#ibcon#[27=USB\r\n] 2006.257.17:51:14.10#ibcon#*before write, iclass 6, count 0 2006.257.17:51:14.10#ibcon#enter sib2, iclass 6, count 0 2006.257.17:51:14.10#ibcon#flushed, iclass 6, count 0 2006.257.17:51:14.10#ibcon#about to write, iclass 6, count 0 2006.257.17:51:14.10#ibcon#wrote, iclass 6, count 0 2006.257.17:51:14.10#ibcon#about to read 3, iclass 6, count 0 2006.257.17:51:14.13#ibcon#read 3, iclass 6, count 0 2006.257.17:51:14.13#ibcon#about to read 4, iclass 6, count 0 2006.257.17:51:14.13#ibcon#read 4, iclass 6, count 0 2006.257.17:51:14.13#ibcon#about to read 5, iclass 6, count 0 2006.257.17:51:14.13#ibcon#read 5, iclass 6, count 0 2006.257.17:51:14.13#ibcon#about to read 6, iclass 6, count 0 2006.257.17:51:14.13#ibcon#read 6, iclass 6, count 0 2006.257.17:51:14.13#ibcon#end of sib2, iclass 6, count 0 2006.257.17:51:14.13#ibcon#*after write, iclass 6, count 0 2006.257.17:51:14.13#ibcon#*before return 0, iclass 6, count 0 2006.257.17:51:14.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:14.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.17:51:14.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:51:14.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:51:14.13$vck44/vblo=7,734.99 2006.257.17:51:14.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.17:51:14.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.17:51:14.13#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:14.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:14.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:14.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:14.13#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:51:14.13#ibcon#first serial, iclass 10, count 0 2006.257.17:51:14.13#ibcon#enter sib2, iclass 10, count 0 2006.257.17:51:14.13#ibcon#flushed, iclass 10, count 0 2006.257.17:51:14.13#ibcon#about to write, iclass 10, count 0 2006.257.17:51:14.13#ibcon#wrote, iclass 10, count 0 2006.257.17:51:14.13#ibcon#about to read 3, iclass 10, count 0 2006.257.17:51:14.15#ibcon#read 3, iclass 10, count 0 2006.257.17:51:14.15#ibcon#about to read 4, iclass 10, count 0 2006.257.17:51:14.15#ibcon#read 4, iclass 10, count 0 2006.257.17:51:14.15#ibcon#about to read 5, iclass 10, count 0 2006.257.17:51:14.15#ibcon#read 5, iclass 10, count 0 2006.257.17:51:14.15#ibcon#about to read 6, iclass 10, count 0 2006.257.17:51:14.15#ibcon#read 6, iclass 10, count 0 2006.257.17:51:14.15#ibcon#end of sib2, iclass 10, count 0 2006.257.17:51:14.15#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:51:14.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:51:14.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:51:14.15#ibcon#*before write, iclass 10, count 0 2006.257.17:51:14.15#ibcon#enter sib2, iclass 10, count 0 2006.257.17:51:14.15#ibcon#flushed, iclass 10, count 0 2006.257.17:51:14.15#ibcon#about to write, iclass 10, count 0 2006.257.17:51:14.15#ibcon#wrote, iclass 10, count 0 2006.257.17:51:14.15#ibcon#about to read 3, iclass 10, count 0 2006.257.17:51:14.19#ibcon#read 3, iclass 10, count 0 2006.257.17:51:14.19#ibcon#about to read 4, iclass 10, count 0 2006.257.17:51:14.19#ibcon#read 4, iclass 10, count 0 2006.257.17:51:14.19#ibcon#about to read 5, iclass 10, count 0 2006.257.17:51:14.19#ibcon#read 5, iclass 10, count 0 2006.257.17:51:14.19#ibcon#about to read 6, iclass 10, count 0 2006.257.17:51:14.19#ibcon#read 6, iclass 10, count 0 2006.257.17:51:14.19#ibcon#end of sib2, iclass 10, count 0 2006.257.17:51:14.19#ibcon#*after write, iclass 10, count 0 2006.257.17:51:14.19#ibcon#*before return 0, iclass 10, count 0 2006.257.17:51:14.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:14.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.17:51:14.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:51:14.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:51:14.19$vck44/vb=7,4 2006.257.17:51:14.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.17:51:14.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.17:51:14.19#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:14.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:14.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:14.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:14.25#ibcon#enter wrdev, iclass 12, count 2 2006.257.17:51:14.25#ibcon#first serial, iclass 12, count 2 2006.257.17:51:14.25#ibcon#enter sib2, iclass 12, count 2 2006.257.17:51:14.25#ibcon#flushed, iclass 12, count 2 2006.257.17:51:14.25#ibcon#about to write, iclass 12, count 2 2006.257.17:51:14.25#ibcon#wrote, iclass 12, count 2 2006.257.17:51:14.25#ibcon#about to read 3, iclass 12, count 2 2006.257.17:51:14.27#ibcon#read 3, iclass 12, count 2 2006.257.17:51:14.27#ibcon#about to read 4, iclass 12, count 2 2006.257.17:51:14.27#ibcon#read 4, iclass 12, count 2 2006.257.17:51:14.27#ibcon#about to read 5, iclass 12, count 2 2006.257.17:51:14.27#ibcon#read 5, iclass 12, count 2 2006.257.17:51:14.27#ibcon#about to read 6, iclass 12, count 2 2006.257.17:51:14.27#ibcon#read 6, iclass 12, count 2 2006.257.17:51:14.27#ibcon#end of sib2, iclass 12, count 2 2006.257.17:51:14.27#ibcon#*mode == 0, iclass 12, count 2 2006.257.17:51:14.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.17:51:14.27#ibcon#[27=AT07-04\r\n] 2006.257.17:51:14.27#ibcon#*before write, iclass 12, count 2 2006.257.17:51:14.27#ibcon#enter sib2, iclass 12, count 2 2006.257.17:51:14.27#ibcon#flushed, iclass 12, count 2 2006.257.17:51:14.27#ibcon#about to write, iclass 12, count 2 2006.257.17:51:14.27#ibcon#wrote, iclass 12, count 2 2006.257.17:51:14.27#ibcon#about to read 3, iclass 12, count 2 2006.257.17:51:14.30#ibcon#read 3, iclass 12, count 2 2006.257.17:51:14.30#ibcon#about to read 4, iclass 12, count 2 2006.257.17:51:14.30#ibcon#read 4, iclass 12, count 2 2006.257.17:51:14.30#ibcon#about to read 5, iclass 12, count 2 2006.257.17:51:14.30#ibcon#read 5, iclass 12, count 2 2006.257.17:51:14.30#ibcon#about to read 6, iclass 12, count 2 2006.257.17:51:14.30#ibcon#read 6, iclass 12, count 2 2006.257.17:51:14.30#ibcon#end of sib2, iclass 12, count 2 2006.257.17:51:14.30#ibcon#*after write, iclass 12, count 2 2006.257.17:51:14.30#ibcon#*before return 0, iclass 12, count 2 2006.257.17:51:14.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:14.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.17:51:14.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.17:51:14.30#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:14.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:14.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:14.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:14.42#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:51:14.42#ibcon#first serial, iclass 12, count 0 2006.257.17:51:14.42#ibcon#enter sib2, iclass 12, count 0 2006.257.17:51:14.42#ibcon#flushed, iclass 12, count 0 2006.257.17:51:14.42#ibcon#about to write, iclass 12, count 0 2006.257.17:51:14.42#ibcon#wrote, iclass 12, count 0 2006.257.17:51:14.42#ibcon#about to read 3, iclass 12, count 0 2006.257.17:51:14.44#ibcon#read 3, iclass 12, count 0 2006.257.17:51:14.44#ibcon#about to read 4, iclass 12, count 0 2006.257.17:51:14.44#ibcon#read 4, iclass 12, count 0 2006.257.17:51:14.44#ibcon#about to read 5, iclass 12, count 0 2006.257.17:51:14.44#ibcon#read 5, iclass 12, count 0 2006.257.17:51:14.44#ibcon#about to read 6, iclass 12, count 0 2006.257.17:51:14.44#ibcon#read 6, iclass 12, count 0 2006.257.17:51:14.44#ibcon#end of sib2, iclass 12, count 0 2006.257.17:51:14.44#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:51:14.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:51:14.44#ibcon#[27=USB\r\n] 2006.257.17:51:14.44#ibcon#*before write, iclass 12, count 0 2006.257.17:51:14.44#ibcon#enter sib2, iclass 12, count 0 2006.257.17:51:14.44#ibcon#flushed, iclass 12, count 0 2006.257.17:51:14.44#ibcon#about to write, iclass 12, count 0 2006.257.17:51:14.44#ibcon#wrote, iclass 12, count 0 2006.257.17:51:14.44#ibcon#about to read 3, iclass 12, count 0 2006.257.17:51:14.47#ibcon#read 3, iclass 12, count 0 2006.257.17:51:14.47#ibcon#about to read 4, iclass 12, count 0 2006.257.17:51:14.47#ibcon#read 4, iclass 12, count 0 2006.257.17:51:14.47#ibcon#about to read 5, iclass 12, count 0 2006.257.17:51:14.47#ibcon#read 5, iclass 12, count 0 2006.257.17:51:14.47#ibcon#about to read 6, iclass 12, count 0 2006.257.17:51:14.47#ibcon#read 6, iclass 12, count 0 2006.257.17:51:14.47#ibcon#end of sib2, iclass 12, count 0 2006.257.17:51:14.47#ibcon#*after write, iclass 12, count 0 2006.257.17:51:14.47#ibcon#*before return 0, iclass 12, count 0 2006.257.17:51:14.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:14.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.17:51:14.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:51:14.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:51:14.47$vck44/vblo=8,744.99 2006.257.17:51:14.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.17:51:14.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.17:51:14.47#ibcon#ireg 17 cls_cnt 0 2006.257.17:51:14.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:14.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:14.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:14.47#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:51:14.47#ibcon#first serial, iclass 14, count 0 2006.257.17:51:14.47#ibcon#enter sib2, iclass 14, count 0 2006.257.17:51:14.47#ibcon#flushed, iclass 14, count 0 2006.257.17:51:14.47#ibcon#about to write, iclass 14, count 0 2006.257.17:51:14.47#ibcon#wrote, iclass 14, count 0 2006.257.17:51:14.47#ibcon#about to read 3, iclass 14, count 0 2006.257.17:51:14.49#ibcon#read 3, iclass 14, count 0 2006.257.17:51:14.49#ibcon#about to read 4, iclass 14, count 0 2006.257.17:51:14.49#ibcon#read 4, iclass 14, count 0 2006.257.17:51:14.49#ibcon#about to read 5, iclass 14, count 0 2006.257.17:51:14.49#ibcon#read 5, iclass 14, count 0 2006.257.17:51:14.49#ibcon#about to read 6, iclass 14, count 0 2006.257.17:51:14.49#ibcon#read 6, iclass 14, count 0 2006.257.17:51:14.49#ibcon#end of sib2, iclass 14, count 0 2006.257.17:51:14.49#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:51:14.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:51:14.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:51:14.49#ibcon#*before write, iclass 14, count 0 2006.257.17:51:14.49#ibcon#enter sib2, iclass 14, count 0 2006.257.17:51:14.49#ibcon#flushed, iclass 14, count 0 2006.257.17:51:14.49#ibcon#about to write, iclass 14, count 0 2006.257.17:51:14.49#ibcon#wrote, iclass 14, count 0 2006.257.17:51:14.49#ibcon#about to read 3, iclass 14, count 0 2006.257.17:51:14.53#ibcon#read 3, iclass 14, count 0 2006.257.17:51:14.53#ibcon#about to read 4, iclass 14, count 0 2006.257.17:51:14.53#ibcon#read 4, iclass 14, count 0 2006.257.17:51:14.53#ibcon#about to read 5, iclass 14, count 0 2006.257.17:51:14.53#ibcon#read 5, iclass 14, count 0 2006.257.17:51:14.53#ibcon#about to read 6, iclass 14, count 0 2006.257.17:51:14.53#ibcon#read 6, iclass 14, count 0 2006.257.17:51:14.53#ibcon#end of sib2, iclass 14, count 0 2006.257.17:51:14.53#ibcon#*after write, iclass 14, count 0 2006.257.17:51:14.53#ibcon#*before return 0, iclass 14, count 0 2006.257.17:51:14.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:14.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.17:51:14.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:51:14.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:51:14.53$vck44/vb=8,4 2006.257.17:51:14.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.17:51:14.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.17:51:14.53#ibcon#ireg 11 cls_cnt 2 2006.257.17:51:14.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:14.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:14.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:14.59#ibcon#enter wrdev, iclass 16, count 2 2006.257.17:51:14.59#ibcon#first serial, iclass 16, count 2 2006.257.17:51:14.59#ibcon#enter sib2, iclass 16, count 2 2006.257.17:51:14.59#ibcon#flushed, iclass 16, count 2 2006.257.17:51:14.59#ibcon#about to write, iclass 16, count 2 2006.257.17:51:14.59#ibcon#wrote, iclass 16, count 2 2006.257.17:51:14.59#ibcon#about to read 3, iclass 16, count 2 2006.257.17:51:14.61#ibcon#read 3, iclass 16, count 2 2006.257.17:51:14.61#ibcon#about to read 4, iclass 16, count 2 2006.257.17:51:14.61#ibcon#read 4, iclass 16, count 2 2006.257.17:51:14.61#ibcon#about to read 5, iclass 16, count 2 2006.257.17:51:14.61#ibcon#read 5, iclass 16, count 2 2006.257.17:51:14.61#ibcon#about to read 6, iclass 16, count 2 2006.257.17:51:14.61#ibcon#read 6, iclass 16, count 2 2006.257.17:51:14.61#ibcon#end of sib2, iclass 16, count 2 2006.257.17:51:14.61#ibcon#*mode == 0, iclass 16, count 2 2006.257.17:51:14.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.17:51:14.61#ibcon#[27=AT08-04\r\n] 2006.257.17:51:14.61#ibcon#*before write, iclass 16, count 2 2006.257.17:51:14.61#ibcon#enter sib2, iclass 16, count 2 2006.257.17:51:14.61#ibcon#flushed, iclass 16, count 2 2006.257.17:51:14.61#ibcon#about to write, iclass 16, count 2 2006.257.17:51:14.61#ibcon#wrote, iclass 16, count 2 2006.257.17:51:14.61#ibcon#about to read 3, iclass 16, count 2 2006.257.17:51:14.64#ibcon#read 3, iclass 16, count 2 2006.257.17:51:14.64#ibcon#about to read 4, iclass 16, count 2 2006.257.17:51:14.64#ibcon#read 4, iclass 16, count 2 2006.257.17:51:14.64#ibcon#about to read 5, iclass 16, count 2 2006.257.17:51:14.64#ibcon#read 5, iclass 16, count 2 2006.257.17:51:14.64#ibcon#about to read 6, iclass 16, count 2 2006.257.17:51:14.64#ibcon#read 6, iclass 16, count 2 2006.257.17:51:14.64#ibcon#end of sib2, iclass 16, count 2 2006.257.17:51:14.64#ibcon#*after write, iclass 16, count 2 2006.257.17:51:14.64#ibcon#*before return 0, iclass 16, count 2 2006.257.17:51:14.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:14.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.17:51:14.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.17:51:14.64#ibcon#ireg 7 cls_cnt 0 2006.257.17:51:14.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:14.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:14.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:14.76#ibcon#enter wrdev, iclass 16, count 0 2006.257.17:51:14.76#ibcon#first serial, iclass 16, count 0 2006.257.17:51:14.76#ibcon#enter sib2, iclass 16, count 0 2006.257.17:51:14.76#ibcon#flushed, iclass 16, count 0 2006.257.17:51:14.76#ibcon#about to write, iclass 16, count 0 2006.257.17:51:14.76#ibcon#wrote, iclass 16, count 0 2006.257.17:51:14.76#ibcon#about to read 3, iclass 16, count 0 2006.257.17:51:14.78#ibcon#read 3, iclass 16, count 0 2006.257.17:51:14.78#ibcon#about to read 4, iclass 16, count 0 2006.257.17:51:14.78#ibcon#read 4, iclass 16, count 0 2006.257.17:51:14.78#ibcon#about to read 5, iclass 16, count 0 2006.257.17:51:14.78#ibcon#read 5, iclass 16, count 0 2006.257.17:51:14.78#ibcon#about to read 6, iclass 16, count 0 2006.257.17:51:14.78#ibcon#read 6, iclass 16, count 0 2006.257.17:51:14.78#ibcon#end of sib2, iclass 16, count 0 2006.257.17:51:14.78#ibcon#*mode == 0, iclass 16, count 0 2006.257.17:51:14.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.17:51:14.78#ibcon#[27=USB\r\n] 2006.257.17:51:14.78#ibcon#*before write, iclass 16, count 0 2006.257.17:51:14.78#ibcon#enter sib2, iclass 16, count 0 2006.257.17:51:14.78#ibcon#flushed, iclass 16, count 0 2006.257.17:51:14.78#ibcon#about to write, iclass 16, count 0 2006.257.17:51:14.78#ibcon#wrote, iclass 16, count 0 2006.257.17:51:14.78#ibcon#about to read 3, iclass 16, count 0 2006.257.17:51:14.81#ibcon#read 3, iclass 16, count 0 2006.257.17:51:14.81#ibcon#about to read 4, iclass 16, count 0 2006.257.17:51:14.81#ibcon#read 4, iclass 16, count 0 2006.257.17:51:14.81#ibcon#about to read 5, iclass 16, count 0 2006.257.17:51:14.81#ibcon#read 5, iclass 16, count 0 2006.257.17:51:14.81#ibcon#about to read 6, iclass 16, count 0 2006.257.17:51:14.81#ibcon#read 6, iclass 16, count 0 2006.257.17:51:14.81#ibcon#end of sib2, iclass 16, count 0 2006.257.17:51:14.81#ibcon#*after write, iclass 16, count 0 2006.257.17:51:14.81#ibcon#*before return 0, iclass 16, count 0 2006.257.17:51:14.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:14.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.17:51:14.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.17:51:14.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.17:51:14.81$vck44/vabw=wide 2006.257.17:51:14.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.17:51:14.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.17:51:14.81#ibcon#ireg 8 cls_cnt 0 2006.257.17:51:14.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:14.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:14.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:14.81#ibcon#enter wrdev, iclass 18, count 0 2006.257.17:51:14.81#ibcon#first serial, iclass 18, count 0 2006.257.17:51:14.81#ibcon#enter sib2, iclass 18, count 0 2006.257.17:51:14.81#ibcon#flushed, iclass 18, count 0 2006.257.17:51:14.81#ibcon#about to write, iclass 18, count 0 2006.257.17:51:14.81#ibcon#wrote, iclass 18, count 0 2006.257.17:51:14.81#ibcon#about to read 3, iclass 18, count 0 2006.257.17:51:14.83#ibcon#read 3, iclass 18, count 0 2006.257.17:51:14.83#ibcon#about to read 4, iclass 18, count 0 2006.257.17:51:14.83#ibcon#read 4, iclass 18, count 0 2006.257.17:51:14.83#ibcon#about to read 5, iclass 18, count 0 2006.257.17:51:14.83#ibcon#read 5, iclass 18, count 0 2006.257.17:51:14.83#ibcon#about to read 6, iclass 18, count 0 2006.257.17:51:14.83#ibcon#read 6, iclass 18, count 0 2006.257.17:51:14.83#ibcon#end of sib2, iclass 18, count 0 2006.257.17:51:14.83#ibcon#*mode == 0, iclass 18, count 0 2006.257.17:51:14.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.17:51:14.83#ibcon#[25=BW32\r\n] 2006.257.17:51:14.83#ibcon#*before write, iclass 18, count 0 2006.257.17:51:14.83#ibcon#enter sib2, iclass 18, count 0 2006.257.17:51:14.83#ibcon#flushed, iclass 18, count 0 2006.257.17:51:14.83#ibcon#about to write, iclass 18, count 0 2006.257.17:51:14.83#ibcon#wrote, iclass 18, count 0 2006.257.17:51:14.83#ibcon#about to read 3, iclass 18, count 0 2006.257.17:51:14.86#ibcon#read 3, iclass 18, count 0 2006.257.17:51:14.86#ibcon#about to read 4, iclass 18, count 0 2006.257.17:51:14.86#ibcon#read 4, iclass 18, count 0 2006.257.17:51:14.86#ibcon#about to read 5, iclass 18, count 0 2006.257.17:51:14.86#ibcon#read 5, iclass 18, count 0 2006.257.17:51:14.86#ibcon#about to read 6, iclass 18, count 0 2006.257.17:51:14.86#ibcon#read 6, iclass 18, count 0 2006.257.17:51:14.86#ibcon#end of sib2, iclass 18, count 0 2006.257.17:51:14.86#ibcon#*after write, iclass 18, count 0 2006.257.17:51:14.86#ibcon#*before return 0, iclass 18, count 0 2006.257.17:51:14.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:14.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:51:14.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.17:51:14.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.17:51:14.86$vck44/vbbw=wide 2006.257.17:51:14.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.17:51:14.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.17:51:14.86#ibcon#ireg 8 cls_cnt 0 2006.257.17:51:14.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:51:14.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:51:14.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:51:14.93#ibcon#enter wrdev, iclass 20, count 0 2006.257.17:51:14.93#ibcon#first serial, iclass 20, count 0 2006.257.17:51:14.93#ibcon#enter sib2, iclass 20, count 0 2006.257.17:51:14.93#ibcon#flushed, iclass 20, count 0 2006.257.17:51:14.93#ibcon#about to write, iclass 20, count 0 2006.257.17:51:14.93#ibcon#wrote, iclass 20, count 0 2006.257.17:51:14.93#ibcon#about to read 3, iclass 20, count 0 2006.257.17:51:14.95#ibcon#read 3, iclass 20, count 0 2006.257.17:51:14.95#ibcon#about to read 4, iclass 20, count 0 2006.257.17:51:14.95#ibcon#read 4, iclass 20, count 0 2006.257.17:51:14.95#ibcon#about to read 5, iclass 20, count 0 2006.257.17:51:14.95#ibcon#read 5, iclass 20, count 0 2006.257.17:51:14.95#ibcon#about to read 6, iclass 20, count 0 2006.257.17:51:14.95#ibcon#read 6, iclass 20, count 0 2006.257.17:51:14.95#ibcon#end of sib2, iclass 20, count 0 2006.257.17:51:14.95#ibcon#*mode == 0, iclass 20, count 0 2006.257.17:51:14.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.17:51:14.95#ibcon#[27=BW32\r\n] 2006.257.17:51:14.95#ibcon#*before write, iclass 20, count 0 2006.257.17:51:14.95#ibcon#enter sib2, iclass 20, count 0 2006.257.17:51:14.95#ibcon#flushed, iclass 20, count 0 2006.257.17:51:14.95#ibcon#about to write, iclass 20, count 0 2006.257.17:51:14.95#ibcon#wrote, iclass 20, count 0 2006.257.17:51:14.95#ibcon#about to read 3, iclass 20, count 0 2006.257.17:51:14.98#ibcon#read 3, iclass 20, count 0 2006.257.17:51:14.98#ibcon#about to read 4, iclass 20, count 0 2006.257.17:51:14.98#ibcon#read 4, iclass 20, count 0 2006.257.17:51:14.98#ibcon#about to read 5, iclass 20, count 0 2006.257.17:51:14.98#ibcon#read 5, iclass 20, count 0 2006.257.17:51:14.98#ibcon#about to read 6, iclass 20, count 0 2006.257.17:51:14.98#ibcon#read 6, iclass 20, count 0 2006.257.17:51:14.98#ibcon#end of sib2, iclass 20, count 0 2006.257.17:51:14.98#ibcon#*after write, iclass 20, count 0 2006.257.17:51:14.98#ibcon#*before return 0, iclass 20, count 0 2006.257.17:51:14.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:51:14.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:51:14.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.17:51:14.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.17:51:14.98$setupk4/ifdk4 2006.257.17:51:14.98$ifdk4/lo= 2006.257.17:51:14.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:51:14.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:51:14.98$ifdk4/patch= 2006.257.17:51:14.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:51:14.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:51:14.98$setupk4/!*+20s 2006.257.17:51:15.85#abcon#<5=/14 1.5 3.9 17.27 971014.3\r\n> 2006.257.17:51:15.87#abcon#{5=INTERFACE CLEAR} 2006.257.17:51:15.93#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:51:26.02#abcon#<5=/14 1.5 3.9 17.26 971014.3\r\n> 2006.257.17:51:26.04#abcon#{5=INTERFACE CLEAR} 2006.257.17:51:26.10#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:51:29.48$setupk4/"tpicd 2006.257.17:51:29.48$setupk4/echo=off 2006.257.17:51:29.48$setupk4/xlog=off 2006.257.17:51:29.48:!2006.257.17:53:26 2006.257.17:51:31.14#trakl#Source acquired 2006.257.17:51:33.14#flagr#flagr/antenna,acquired 2006.257.17:53:26.00:preob 2006.257.17:53:26.13/onsource/TRACKING 2006.257.17:53:26.13:!2006.257.17:53:36 2006.257.17:53:36.00:"tape 2006.257.17:53:36.00:"st=record 2006.257.17:53:36.00:data_valid=on 2006.257.17:53:36.00:midob 2006.257.17:53:36.13/onsource/TRACKING 2006.257.17:53:36.13/wx/17.25,1014.3,98 2006.257.17:53:36.33/cable/+6.4843E-03 2006.257.17:53:37.42/va/01,08,usb,yes,36,38 2006.257.17:53:37.42/va/02,07,usb,yes,38,39 2006.257.17:53:37.42/va/03,08,usb,yes,35,37 2006.257.17:53:37.42/va/04,07,usb,yes,40,42 2006.257.17:53:37.42/va/05,04,usb,yes,35,36 2006.257.17:53:37.42/va/06,04,usb,yes,40,39 2006.257.17:53:37.42/va/07,04,usb,yes,40,41 2006.257.17:53:37.42/va/08,04,usb,yes,34,41 2006.257.17:53:37.65/valo/01,524.99,yes,locked 2006.257.17:53:37.65/valo/02,534.99,yes,locked 2006.257.17:53:37.65/valo/03,564.99,yes,locked 2006.257.17:53:37.65/valo/04,624.99,yes,locked 2006.257.17:53:37.65/valo/05,734.99,yes,locked 2006.257.17:53:37.65/valo/06,814.99,yes,locked 2006.257.17:53:37.65/valo/07,864.99,yes,locked 2006.257.17:53:37.65/valo/08,884.99,yes,locked 2006.257.17:53:38.74/vb/01,04,usb,yes,34,31 2006.257.17:53:38.74/vb/02,05,usb,yes,32,32 2006.257.17:53:38.74/vb/03,04,usb,yes,33,36 2006.257.17:53:38.74/vb/04,05,usb,yes,33,32 2006.257.17:53:38.74/vb/05,04,usb,yes,30,32 2006.257.17:53:38.74/vb/06,04,usb,yes,35,31 2006.257.17:53:38.74/vb/07,04,usb,yes,34,34 2006.257.17:53:38.74/vb/08,04,usb,yes,31,35 2006.257.17:53:38.97/vblo/01,629.99,yes,locked 2006.257.17:53:38.97/vblo/02,634.99,yes,locked 2006.257.17:53:38.97/vblo/03,649.99,yes,locked 2006.257.17:53:38.97/vblo/04,679.99,yes,locked 2006.257.17:53:38.97/vblo/05,709.99,yes,locked 2006.257.17:53:38.97/vblo/06,719.99,yes,locked 2006.257.17:53:38.97/vblo/07,734.99,yes,locked 2006.257.17:53:38.97/vblo/08,744.99,yes,locked 2006.257.17:53:39.12/vabw/8 2006.257.17:53:39.27/vbbw/8 2006.257.17:53:39.36/xfe/off,on,15.0 2006.257.17:53:39.74/ifatt/23,28,28,28 2006.257.17:53:40.07/fmout-gps/S +4.48E-07 2006.257.17:53:40.11:!2006.257.17:54:16 2006.257.17:54:16.00:data_valid=off 2006.257.17:54:16.00:"et 2006.257.17:54:16.00:!+3s 2006.257.17:54:19.02:"tape 2006.257.17:54:19.02:postob 2006.257.17:54:19.20/cable/+6.4872E-03 2006.257.17:54:19.20/wx/17.25,1014.3,98 2006.257.17:54:20.08/fmout-gps/S +4.49E-07 2006.257.17:54:20.08:scan_name=257-1755,jd0609,310 2006.257.17:54:20.08:source=nrao150,035929.75,505750.2,2000.0,cw 2006.257.17:54:21.13#flagr#flagr/antenna,new-source 2006.257.17:54:21.13:checkk5 2006.257.17:54:21.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.17:54:21.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.17:54:22.14/chk_autoobs//k5ts3/ autoobs is running! 2006.257.17:54:22.48/chk_autoobs//k5ts4/ autoobs is running! 2006.257.17:54:22.81/chk_obsdata//k5ts1/T2571753??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.17:54:23.14/chk_obsdata//k5ts2/T2571753??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.17:54:23.47/chk_obsdata//k5ts3/T2571753??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.17:54:23.81/chk_obsdata//k5ts4/T2571753??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.17:54:24.47/k5log//k5ts1_log_newline 2006.257.17:54:25.12/k5log//k5ts2_log_newline 2006.257.17:54:25.77/k5log//k5ts3_log_newline 2006.257.17:54:26.43/k5log//k5ts4_log_newline 2006.257.17:54:26.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.17:54:26.45:setupk4=1 2006.257.17:54:26.45$setupk4/echo=on 2006.257.17:54:26.45$setupk4/pcalon 2006.257.17:54:26.45$pcalon/"no phase cal control is implemented here 2006.257.17:54:26.45$setupk4/"tpicd=stop 2006.257.17:54:26.45$setupk4/"rec=synch_on 2006.257.17:54:26.45$setupk4/"rec_mode=128 2006.257.17:54:26.45$setupk4/!* 2006.257.17:54:26.45$setupk4/recpk4 2006.257.17:54:26.45$recpk4/recpatch= 2006.257.17:54:26.46$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.17:54:26.46$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.17:54:26.46$setupk4/vck44 2006.257.17:54:26.46$vck44/valo=1,524.99 2006.257.17:54:26.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.17:54:26.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.17:54:26.46#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:26.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:26.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:26.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:26.46#ibcon#enter wrdev, iclass 24, count 0 2006.257.17:54:26.46#ibcon#first serial, iclass 24, count 0 2006.257.17:54:26.46#ibcon#enter sib2, iclass 24, count 0 2006.257.17:54:26.46#ibcon#flushed, iclass 24, count 0 2006.257.17:54:26.46#ibcon#about to write, iclass 24, count 0 2006.257.17:54:26.46#ibcon#wrote, iclass 24, count 0 2006.257.17:54:26.46#ibcon#about to read 3, iclass 24, count 0 2006.257.17:54:26.48#ibcon#read 3, iclass 24, count 0 2006.257.17:54:26.48#ibcon#about to read 4, iclass 24, count 0 2006.257.17:54:26.48#ibcon#read 4, iclass 24, count 0 2006.257.17:54:26.48#ibcon#about to read 5, iclass 24, count 0 2006.257.17:54:26.48#ibcon#read 5, iclass 24, count 0 2006.257.17:54:26.48#ibcon#about to read 6, iclass 24, count 0 2006.257.17:54:26.48#ibcon#read 6, iclass 24, count 0 2006.257.17:54:26.48#ibcon#end of sib2, iclass 24, count 0 2006.257.17:54:26.48#ibcon#*mode == 0, iclass 24, count 0 2006.257.17:54:26.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.17:54:26.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.17:54:26.48#ibcon#*before write, iclass 24, count 0 2006.257.17:54:26.48#ibcon#enter sib2, iclass 24, count 0 2006.257.17:54:26.48#ibcon#flushed, iclass 24, count 0 2006.257.17:54:26.48#ibcon#about to write, iclass 24, count 0 2006.257.17:54:26.48#ibcon#wrote, iclass 24, count 0 2006.257.17:54:26.48#ibcon#about to read 3, iclass 24, count 0 2006.257.17:54:26.53#ibcon#read 3, iclass 24, count 0 2006.257.17:54:26.53#ibcon#about to read 4, iclass 24, count 0 2006.257.17:54:26.53#ibcon#read 4, iclass 24, count 0 2006.257.17:54:26.53#ibcon#about to read 5, iclass 24, count 0 2006.257.17:54:26.53#ibcon#read 5, iclass 24, count 0 2006.257.17:54:26.53#ibcon#about to read 6, iclass 24, count 0 2006.257.17:54:26.53#ibcon#read 6, iclass 24, count 0 2006.257.17:54:26.53#ibcon#end of sib2, iclass 24, count 0 2006.257.17:54:26.53#ibcon#*after write, iclass 24, count 0 2006.257.17:54:26.53#ibcon#*before return 0, iclass 24, count 0 2006.257.17:54:26.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:26.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:26.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.17:54:26.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.17:54:26.53$vck44/va=1,8 2006.257.17:54:26.53#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.17:54:26.53#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.17:54:26.53#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:26.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:26.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:26.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:26.53#ibcon#enter wrdev, iclass 26, count 2 2006.257.17:54:26.53#ibcon#first serial, iclass 26, count 2 2006.257.17:54:26.53#ibcon#enter sib2, iclass 26, count 2 2006.257.17:54:26.53#ibcon#flushed, iclass 26, count 2 2006.257.17:54:26.53#ibcon#about to write, iclass 26, count 2 2006.257.17:54:26.53#ibcon#wrote, iclass 26, count 2 2006.257.17:54:26.53#ibcon#about to read 3, iclass 26, count 2 2006.257.17:54:26.55#ibcon#read 3, iclass 26, count 2 2006.257.17:54:26.55#ibcon#about to read 4, iclass 26, count 2 2006.257.17:54:26.55#ibcon#read 4, iclass 26, count 2 2006.257.17:54:26.55#ibcon#about to read 5, iclass 26, count 2 2006.257.17:54:26.55#ibcon#read 5, iclass 26, count 2 2006.257.17:54:26.55#ibcon#about to read 6, iclass 26, count 2 2006.257.17:54:26.55#ibcon#read 6, iclass 26, count 2 2006.257.17:54:26.55#ibcon#end of sib2, iclass 26, count 2 2006.257.17:54:26.55#ibcon#*mode == 0, iclass 26, count 2 2006.257.17:54:26.55#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.17:54:26.55#ibcon#[25=AT01-08\r\n] 2006.257.17:54:26.55#ibcon#*before write, iclass 26, count 2 2006.257.17:54:26.55#ibcon#enter sib2, iclass 26, count 2 2006.257.17:54:26.55#ibcon#flushed, iclass 26, count 2 2006.257.17:54:26.55#ibcon#about to write, iclass 26, count 2 2006.257.17:54:26.55#ibcon#wrote, iclass 26, count 2 2006.257.17:54:26.55#ibcon#about to read 3, iclass 26, count 2 2006.257.17:54:26.58#ibcon#read 3, iclass 26, count 2 2006.257.17:54:26.58#ibcon#about to read 4, iclass 26, count 2 2006.257.17:54:26.58#ibcon#read 4, iclass 26, count 2 2006.257.17:54:26.58#ibcon#about to read 5, iclass 26, count 2 2006.257.17:54:26.58#ibcon#read 5, iclass 26, count 2 2006.257.17:54:26.58#ibcon#about to read 6, iclass 26, count 2 2006.257.17:54:26.58#ibcon#read 6, iclass 26, count 2 2006.257.17:54:26.58#ibcon#end of sib2, iclass 26, count 2 2006.257.17:54:26.58#ibcon#*after write, iclass 26, count 2 2006.257.17:54:26.58#ibcon#*before return 0, iclass 26, count 2 2006.257.17:54:26.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:26.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:26.58#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.17:54:26.58#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:26.58#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:26.70#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:26.70#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:26.70#ibcon#enter wrdev, iclass 26, count 0 2006.257.17:54:26.70#ibcon#first serial, iclass 26, count 0 2006.257.17:54:26.70#ibcon#enter sib2, iclass 26, count 0 2006.257.17:54:26.70#ibcon#flushed, iclass 26, count 0 2006.257.17:54:26.70#ibcon#about to write, iclass 26, count 0 2006.257.17:54:26.70#ibcon#wrote, iclass 26, count 0 2006.257.17:54:26.70#ibcon#about to read 3, iclass 26, count 0 2006.257.17:54:26.72#ibcon#read 3, iclass 26, count 0 2006.257.17:54:26.72#ibcon#about to read 4, iclass 26, count 0 2006.257.17:54:26.72#ibcon#read 4, iclass 26, count 0 2006.257.17:54:26.72#ibcon#about to read 5, iclass 26, count 0 2006.257.17:54:26.72#ibcon#read 5, iclass 26, count 0 2006.257.17:54:26.72#ibcon#about to read 6, iclass 26, count 0 2006.257.17:54:26.72#ibcon#read 6, iclass 26, count 0 2006.257.17:54:26.72#ibcon#end of sib2, iclass 26, count 0 2006.257.17:54:26.72#ibcon#*mode == 0, iclass 26, count 0 2006.257.17:54:26.72#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.17:54:26.72#ibcon#[25=USB\r\n] 2006.257.17:54:26.72#ibcon#*before write, iclass 26, count 0 2006.257.17:54:26.72#ibcon#enter sib2, iclass 26, count 0 2006.257.17:54:26.72#ibcon#flushed, iclass 26, count 0 2006.257.17:54:26.72#ibcon#about to write, iclass 26, count 0 2006.257.17:54:26.72#ibcon#wrote, iclass 26, count 0 2006.257.17:54:26.72#ibcon#about to read 3, iclass 26, count 0 2006.257.17:54:26.75#ibcon#read 3, iclass 26, count 0 2006.257.17:54:26.75#ibcon#about to read 4, iclass 26, count 0 2006.257.17:54:26.75#ibcon#read 4, iclass 26, count 0 2006.257.17:54:26.75#ibcon#about to read 5, iclass 26, count 0 2006.257.17:54:26.75#ibcon#read 5, iclass 26, count 0 2006.257.17:54:26.75#ibcon#about to read 6, iclass 26, count 0 2006.257.17:54:26.75#ibcon#read 6, iclass 26, count 0 2006.257.17:54:26.75#ibcon#end of sib2, iclass 26, count 0 2006.257.17:54:26.75#ibcon#*after write, iclass 26, count 0 2006.257.17:54:26.75#ibcon#*before return 0, iclass 26, count 0 2006.257.17:54:26.75#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:26.75#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:26.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.17:54:26.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.17:54:26.75$vck44/valo=2,534.99 2006.257.17:54:26.75#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.17:54:26.75#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.17:54:26.75#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:26.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:26.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:26.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:26.75#ibcon#enter wrdev, iclass 28, count 0 2006.257.17:54:26.75#ibcon#first serial, iclass 28, count 0 2006.257.17:54:26.75#ibcon#enter sib2, iclass 28, count 0 2006.257.17:54:26.75#ibcon#flushed, iclass 28, count 0 2006.257.17:54:26.75#ibcon#about to write, iclass 28, count 0 2006.257.17:54:26.75#ibcon#wrote, iclass 28, count 0 2006.257.17:54:26.75#ibcon#about to read 3, iclass 28, count 0 2006.257.17:54:26.77#ibcon#read 3, iclass 28, count 0 2006.257.17:54:26.77#ibcon#about to read 4, iclass 28, count 0 2006.257.17:54:26.77#ibcon#read 4, iclass 28, count 0 2006.257.17:54:26.77#ibcon#about to read 5, iclass 28, count 0 2006.257.17:54:26.77#ibcon#read 5, iclass 28, count 0 2006.257.17:54:26.77#ibcon#about to read 6, iclass 28, count 0 2006.257.17:54:26.77#ibcon#read 6, iclass 28, count 0 2006.257.17:54:26.77#ibcon#end of sib2, iclass 28, count 0 2006.257.17:54:26.77#ibcon#*mode == 0, iclass 28, count 0 2006.257.17:54:26.77#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.17:54:26.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.17:54:26.77#ibcon#*before write, iclass 28, count 0 2006.257.17:54:26.77#ibcon#enter sib2, iclass 28, count 0 2006.257.17:54:26.77#ibcon#flushed, iclass 28, count 0 2006.257.17:54:26.77#ibcon#about to write, iclass 28, count 0 2006.257.17:54:26.77#ibcon#wrote, iclass 28, count 0 2006.257.17:54:26.77#ibcon#about to read 3, iclass 28, count 0 2006.257.17:54:26.81#ibcon#read 3, iclass 28, count 0 2006.257.17:54:26.81#ibcon#about to read 4, iclass 28, count 0 2006.257.17:54:26.81#ibcon#read 4, iclass 28, count 0 2006.257.17:54:26.81#ibcon#about to read 5, iclass 28, count 0 2006.257.17:54:26.81#ibcon#read 5, iclass 28, count 0 2006.257.17:54:26.81#ibcon#about to read 6, iclass 28, count 0 2006.257.17:54:26.81#ibcon#read 6, iclass 28, count 0 2006.257.17:54:26.81#ibcon#end of sib2, iclass 28, count 0 2006.257.17:54:26.81#ibcon#*after write, iclass 28, count 0 2006.257.17:54:26.81#ibcon#*before return 0, iclass 28, count 0 2006.257.17:54:26.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:26.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:26.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.17:54:26.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.17:54:26.81$vck44/va=2,7 2006.257.17:54:26.81#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.17:54:26.81#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.17:54:26.81#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:26.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:26.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:26.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:26.87#ibcon#enter wrdev, iclass 30, count 2 2006.257.17:54:26.87#ibcon#first serial, iclass 30, count 2 2006.257.17:54:26.87#ibcon#enter sib2, iclass 30, count 2 2006.257.17:54:26.87#ibcon#flushed, iclass 30, count 2 2006.257.17:54:26.87#ibcon#about to write, iclass 30, count 2 2006.257.17:54:26.87#ibcon#wrote, iclass 30, count 2 2006.257.17:54:26.87#ibcon#about to read 3, iclass 30, count 2 2006.257.17:54:26.89#ibcon#read 3, iclass 30, count 2 2006.257.17:54:26.89#ibcon#about to read 4, iclass 30, count 2 2006.257.17:54:26.89#ibcon#read 4, iclass 30, count 2 2006.257.17:54:26.89#ibcon#about to read 5, iclass 30, count 2 2006.257.17:54:26.89#ibcon#read 5, iclass 30, count 2 2006.257.17:54:26.89#ibcon#about to read 6, iclass 30, count 2 2006.257.17:54:26.89#ibcon#read 6, iclass 30, count 2 2006.257.17:54:26.89#ibcon#end of sib2, iclass 30, count 2 2006.257.17:54:26.89#ibcon#*mode == 0, iclass 30, count 2 2006.257.17:54:26.89#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.17:54:26.89#ibcon#[25=AT02-07\r\n] 2006.257.17:54:26.89#ibcon#*before write, iclass 30, count 2 2006.257.17:54:26.89#ibcon#enter sib2, iclass 30, count 2 2006.257.17:54:26.89#ibcon#flushed, iclass 30, count 2 2006.257.17:54:26.89#ibcon#about to write, iclass 30, count 2 2006.257.17:54:26.89#ibcon#wrote, iclass 30, count 2 2006.257.17:54:26.89#ibcon#about to read 3, iclass 30, count 2 2006.257.17:54:26.92#ibcon#read 3, iclass 30, count 2 2006.257.17:54:26.92#ibcon#about to read 4, iclass 30, count 2 2006.257.17:54:26.92#ibcon#read 4, iclass 30, count 2 2006.257.17:54:26.92#ibcon#about to read 5, iclass 30, count 2 2006.257.17:54:26.92#ibcon#read 5, iclass 30, count 2 2006.257.17:54:26.92#ibcon#about to read 6, iclass 30, count 2 2006.257.17:54:26.92#ibcon#read 6, iclass 30, count 2 2006.257.17:54:26.92#ibcon#end of sib2, iclass 30, count 2 2006.257.17:54:26.92#ibcon#*after write, iclass 30, count 2 2006.257.17:54:26.92#ibcon#*before return 0, iclass 30, count 2 2006.257.17:54:26.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:26.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:26.92#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.17:54:26.92#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:26.92#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:27.04#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:27.04#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:27.04#ibcon#enter wrdev, iclass 30, count 0 2006.257.17:54:27.04#ibcon#first serial, iclass 30, count 0 2006.257.17:54:27.04#ibcon#enter sib2, iclass 30, count 0 2006.257.17:54:27.04#ibcon#flushed, iclass 30, count 0 2006.257.17:54:27.04#ibcon#about to write, iclass 30, count 0 2006.257.17:54:27.04#ibcon#wrote, iclass 30, count 0 2006.257.17:54:27.04#ibcon#about to read 3, iclass 30, count 0 2006.257.17:54:27.06#ibcon#read 3, iclass 30, count 0 2006.257.17:54:27.06#ibcon#about to read 4, iclass 30, count 0 2006.257.17:54:27.06#ibcon#read 4, iclass 30, count 0 2006.257.17:54:27.06#ibcon#about to read 5, iclass 30, count 0 2006.257.17:54:27.06#ibcon#read 5, iclass 30, count 0 2006.257.17:54:27.06#ibcon#about to read 6, iclass 30, count 0 2006.257.17:54:27.06#ibcon#read 6, iclass 30, count 0 2006.257.17:54:27.06#ibcon#end of sib2, iclass 30, count 0 2006.257.17:54:27.06#ibcon#*mode == 0, iclass 30, count 0 2006.257.17:54:27.06#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.17:54:27.06#ibcon#[25=USB\r\n] 2006.257.17:54:27.06#ibcon#*before write, iclass 30, count 0 2006.257.17:54:27.06#ibcon#enter sib2, iclass 30, count 0 2006.257.17:54:27.06#ibcon#flushed, iclass 30, count 0 2006.257.17:54:27.06#ibcon#about to write, iclass 30, count 0 2006.257.17:54:27.06#ibcon#wrote, iclass 30, count 0 2006.257.17:54:27.06#ibcon#about to read 3, iclass 30, count 0 2006.257.17:54:27.09#ibcon#read 3, iclass 30, count 0 2006.257.17:54:27.09#ibcon#about to read 4, iclass 30, count 0 2006.257.17:54:27.09#ibcon#read 4, iclass 30, count 0 2006.257.17:54:27.09#ibcon#about to read 5, iclass 30, count 0 2006.257.17:54:27.09#ibcon#read 5, iclass 30, count 0 2006.257.17:54:27.09#ibcon#about to read 6, iclass 30, count 0 2006.257.17:54:27.09#ibcon#read 6, iclass 30, count 0 2006.257.17:54:27.09#ibcon#end of sib2, iclass 30, count 0 2006.257.17:54:27.09#ibcon#*after write, iclass 30, count 0 2006.257.17:54:27.09#ibcon#*before return 0, iclass 30, count 0 2006.257.17:54:27.09#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:27.09#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:27.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.17:54:27.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.17:54:27.09$vck44/valo=3,564.99 2006.257.17:54:27.09#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.17:54:27.09#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.17:54:27.09#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:27.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:27.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:27.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:27.09#ibcon#enter wrdev, iclass 32, count 0 2006.257.17:54:27.09#ibcon#first serial, iclass 32, count 0 2006.257.17:54:27.09#ibcon#enter sib2, iclass 32, count 0 2006.257.17:54:27.09#ibcon#flushed, iclass 32, count 0 2006.257.17:54:27.09#ibcon#about to write, iclass 32, count 0 2006.257.17:54:27.09#ibcon#wrote, iclass 32, count 0 2006.257.17:54:27.09#ibcon#about to read 3, iclass 32, count 0 2006.257.17:54:27.11#ibcon#read 3, iclass 32, count 0 2006.257.17:54:27.11#ibcon#about to read 4, iclass 32, count 0 2006.257.17:54:27.11#ibcon#read 4, iclass 32, count 0 2006.257.17:54:27.11#ibcon#about to read 5, iclass 32, count 0 2006.257.17:54:27.11#ibcon#read 5, iclass 32, count 0 2006.257.17:54:27.11#ibcon#about to read 6, iclass 32, count 0 2006.257.17:54:27.11#ibcon#read 6, iclass 32, count 0 2006.257.17:54:27.11#ibcon#end of sib2, iclass 32, count 0 2006.257.17:54:27.11#ibcon#*mode == 0, iclass 32, count 0 2006.257.17:54:27.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.17:54:27.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.17:54:27.11#ibcon#*before write, iclass 32, count 0 2006.257.17:54:27.11#ibcon#enter sib2, iclass 32, count 0 2006.257.17:54:27.11#ibcon#flushed, iclass 32, count 0 2006.257.17:54:27.11#ibcon#about to write, iclass 32, count 0 2006.257.17:54:27.11#ibcon#wrote, iclass 32, count 0 2006.257.17:54:27.11#ibcon#about to read 3, iclass 32, count 0 2006.257.17:54:27.15#ibcon#read 3, iclass 32, count 0 2006.257.17:54:27.15#ibcon#about to read 4, iclass 32, count 0 2006.257.17:54:27.15#ibcon#read 4, iclass 32, count 0 2006.257.17:54:27.15#ibcon#about to read 5, iclass 32, count 0 2006.257.17:54:27.15#ibcon#read 5, iclass 32, count 0 2006.257.17:54:27.15#ibcon#about to read 6, iclass 32, count 0 2006.257.17:54:27.15#ibcon#read 6, iclass 32, count 0 2006.257.17:54:27.15#ibcon#end of sib2, iclass 32, count 0 2006.257.17:54:27.15#ibcon#*after write, iclass 32, count 0 2006.257.17:54:27.15#ibcon#*before return 0, iclass 32, count 0 2006.257.17:54:27.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:27.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:27.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.17:54:27.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.17:54:27.15$vck44/va=3,8 2006.257.17:54:27.15#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.17:54:27.15#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.17:54:27.15#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:27.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:27.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:27.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:27.21#ibcon#enter wrdev, iclass 34, count 2 2006.257.17:54:27.21#ibcon#first serial, iclass 34, count 2 2006.257.17:54:27.21#ibcon#enter sib2, iclass 34, count 2 2006.257.17:54:27.21#ibcon#flushed, iclass 34, count 2 2006.257.17:54:27.21#ibcon#about to write, iclass 34, count 2 2006.257.17:54:27.21#ibcon#wrote, iclass 34, count 2 2006.257.17:54:27.21#ibcon#about to read 3, iclass 34, count 2 2006.257.17:54:27.23#ibcon#read 3, iclass 34, count 2 2006.257.17:54:27.23#ibcon#about to read 4, iclass 34, count 2 2006.257.17:54:27.23#ibcon#read 4, iclass 34, count 2 2006.257.17:54:27.23#ibcon#about to read 5, iclass 34, count 2 2006.257.17:54:27.23#ibcon#read 5, iclass 34, count 2 2006.257.17:54:27.23#ibcon#about to read 6, iclass 34, count 2 2006.257.17:54:27.23#ibcon#read 6, iclass 34, count 2 2006.257.17:54:27.23#ibcon#end of sib2, iclass 34, count 2 2006.257.17:54:27.23#ibcon#*mode == 0, iclass 34, count 2 2006.257.17:54:27.23#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.17:54:27.23#ibcon#[25=AT03-08\r\n] 2006.257.17:54:27.23#ibcon#*before write, iclass 34, count 2 2006.257.17:54:27.23#ibcon#enter sib2, iclass 34, count 2 2006.257.17:54:27.23#ibcon#flushed, iclass 34, count 2 2006.257.17:54:27.23#ibcon#about to write, iclass 34, count 2 2006.257.17:54:27.23#ibcon#wrote, iclass 34, count 2 2006.257.17:54:27.23#ibcon#about to read 3, iclass 34, count 2 2006.257.17:54:27.26#ibcon#read 3, iclass 34, count 2 2006.257.17:54:27.26#ibcon#about to read 4, iclass 34, count 2 2006.257.17:54:27.26#ibcon#read 4, iclass 34, count 2 2006.257.17:54:27.26#ibcon#about to read 5, iclass 34, count 2 2006.257.17:54:27.26#ibcon#read 5, iclass 34, count 2 2006.257.17:54:27.26#ibcon#about to read 6, iclass 34, count 2 2006.257.17:54:27.26#ibcon#read 6, iclass 34, count 2 2006.257.17:54:27.26#ibcon#end of sib2, iclass 34, count 2 2006.257.17:54:27.26#ibcon#*after write, iclass 34, count 2 2006.257.17:54:27.26#ibcon#*before return 0, iclass 34, count 2 2006.257.17:54:27.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:27.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:27.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.17:54:27.26#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:27.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:27.38#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:27.38#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:27.38#ibcon#enter wrdev, iclass 34, count 0 2006.257.17:54:27.38#ibcon#first serial, iclass 34, count 0 2006.257.17:54:27.38#ibcon#enter sib2, iclass 34, count 0 2006.257.17:54:27.38#ibcon#flushed, iclass 34, count 0 2006.257.17:54:27.38#ibcon#about to write, iclass 34, count 0 2006.257.17:54:27.38#ibcon#wrote, iclass 34, count 0 2006.257.17:54:27.38#ibcon#about to read 3, iclass 34, count 0 2006.257.17:54:27.40#ibcon#read 3, iclass 34, count 0 2006.257.17:54:27.40#ibcon#about to read 4, iclass 34, count 0 2006.257.17:54:27.40#ibcon#read 4, iclass 34, count 0 2006.257.17:54:27.40#ibcon#about to read 5, iclass 34, count 0 2006.257.17:54:27.40#ibcon#read 5, iclass 34, count 0 2006.257.17:54:27.40#ibcon#about to read 6, iclass 34, count 0 2006.257.17:54:27.40#ibcon#read 6, iclass 34, count 0 2006.257.17:54:27.40#ibcon#end of sib2, iclass 34, count 0 2006.257.17:54:27.40#ibcon#*mode == 0, iclass 34, count 0 2006.257.17:54:27.40#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.17:54:27.40#ibcon#[25=USB\r\n] 2006.257.17:54:27.40#ibcon#*before write, iclass 34, count 0 2006.257.17:54:27.40#ibcon#enter sib2, iclass 34, count 0 2006.257.17:54:27.40#ibcon#flushed, iclass 34, count 0 2006.257.17:54:27.40#ibcon#about to write, iclass 34, count 0 2006.257.17:54:27.40#ibcon#wrote, iclass 34, count 0 2006.257.17:54:27.40#ibcon#about to read 3, iclass 34, count 0 2006.257.17:54:27.43#ibcon#read 3, iclass 34, count 0 2006.257.17:54:27.43#ibcon#about to read 4, iclass 34, count 0 2006.257.17:54:27.43#ibcon#read 4, iclass 34, count 0 2006.257.17:54:27.43#ibcon#about to read 5, iclass 34, count 0 2006.257.17:54:27.43#ibcon#read 5, iclass 34, count 0 2006.257.17:54:27.43#ibcon#about to read 6, iclass 34, count 0 2006.257.17:54:27.43#ibcon#read 6, iclass 34, count 0 2006.257.17:54:27.43#ibcon#end of sib2, iclass 34, count 0 2006.257.17:54:27.43#ibcon#*after write, iclass 34, count 0 2006.257.17:54:27.43#ibcon#*before return 0, iclass 34, count 0 2006.257.17:54:27.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:27.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:27.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.17:54:27.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.17:54:27.43$vck44/valo=4,624.99 2006.257.17:54:27.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.17:54:27.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.17:54:27.43#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:27.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:27.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:27.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:27.43#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:54:27.43#ibcon#first serial, iclass 36, count 0 2006.257.17:54:27.43#ibcon#enter sib2, iclass 36, count 0 2006.257.17:54:27.43#ibcon#flushed, iclass 36, count 0 2006.257.17:54:27.43#ibcon#about to write, iclass 36, count 0 2006.257.17:54:27.43#ibcon#wrote, iclass 36, count 0 2006.257.17:54:27.43#ibcon#about to read 3, iclass 36, count 0 2006.257.17:54:27.45#ibcon#read 3, iclass 36, count 0 2006.257.17:54:27.45#ibcon#about to read 4, iclass 36, count 0 2006.257.17:54:27.45#ibcon#read 4, iclass 36, count 0 2006.257.17:54:27.45#ibcon#about to read 5, iclass 36, count 0 2006.257.17:54:27.45#ibcon#read 5, iclass 36, count 0 2006.257.17:54:27.45#ibcon#about to read 6, iclass 36, count 0 2006.257.17:54:27.45#ibcon#read 6, iclass 36, count 0 2006.257.17:54:27.45#ibcon#end of sib2, iclass 36, count 0 2006.257.17:54:27.45#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:54:27.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:54:27.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.17:54:27.45#ibcon#*before write, iclass 36, count 0 2006.257.17:54:27.45#ibcon#enter sib2, iclass 36, count 0 2006.257.17:54:27.45#ibcon#flushed, iclass 36, count 0 2006.257.17:54:27.45#ibcon#about to write, iclass 36, count 0 2006.257.17:54:27.45#ibcon#wrote, iclass 36, count 0 2006.257.17:54:27.45#ibcon#about to read 3, iclass 36, count 0 2006.257.17:54:27.49#ibcon#read 3, iclass 36, count 0 2006.257.17:54:27.49#ibcon#about to read 4, iclass 36, count 0 2006.257.17:54:27.49#ibcon#read 4, iclass 36, count 0 2006.257.17:54:27.49#ibcon#about to read 5, iclass 36, count 0 2006.257.17:54:27.49#ibcon#read 5, iclass 36, count 0 2006.257.17:54:27.49#ibcon#about to read 6, iclass 36, count 0 2006.257.17:54:27.49#ibcon#read 6, iclass 36, count 0 2006.257.17:54:27.49#ibcon#end of sib2, iclass 36, count 0 2006.257.17:54:27.49#ibcon#*after write, iclass 36, count 0 2006.257.17:54:27.49#ibcon#*before return 0, iclass 36, count 0 2006.257.17:54:27.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:27.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:27.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:54:27.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:54:27.49$vck44/va=4,7 2006.257.17:54:27.49#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.17:54:27.49#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.17:54:27.49#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:27.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:27.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:27.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:27.55#ibcon#enter wrdev, iclass 38, count 2 2006.257.17:54:27.55#ibcon#first serial, iclass 38, count 2 2006.257.17:54:27.55#ibcon#enter sib2, iclass 38, count 2 2006.257.17:54:27.55#ibcon#flushed, iclass 38, count 2 2006.257.17:54:27.55#ibcon#about to write, iclass 38, count 2 2006.257.17:54:27.55#ibcon#wrote, iclass 38, count 2 2006.257.17:54:27.55#ibcon#about to read 3, iclass 38, count 2 2006.257.17:54:27.57#ibcon#read 3, iclass 38, count 2 2006.257.17:54:27.57#ibcon#about to read 4, iclass 38, count 2 2006.257.17:54:27.57#ibcon#read 4, iclass 38, count 2 2006.257.17:54:27.57#ibcon#about to read 5, iclass 38, count 2 2006.257.17:54:27.57#ibcon#read 5, iclass 38, count 2 2006.257.17:54:27.57#ibcon#about to read 6, iclass 38, count 2 2006.257.17:54:27.57#ibcon#read 6, iclass 38, count 2 2006.257.17:54:27.57#ibcon#end of sib2, iclass 38, count 2 2006.257.17:54:27.57#ibcon#*mode == 0, iclass 38, count 2 2006.257.17:54:27.57#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.17:54:27.57#ibcon#[25=AT04-07\r\n] 2006.257.17:54:27.57#ibcon#*before write, iclass 38, count 2 2006.257.17:54:27.57#ibcon#enter sib2, iclass 38, count 2 2006.257.17:54:27.57#ibcon#flushed, iclass 38, count 2 2006.257.17:54:27.57#ibcon#about to write, iclass 38, count 2 2006.257.17:54:27.57#ibcon#wrote, iclass 38, count 2 2006.257.17:54:27.57#ibcon#about to read 3, iclass 38, count 2 2006.257.17:54:27.60#ibcon#read 3, iclass 38, count 2 2006.257.17:54:27.60#ibcon#about to read 4, iclass 38, count 2 2006.257.17:54:27.60#ibcon#read 4, iclass 38, count 2 2006.257.17:54:27.60#ibcon#about to read 5, iclass 38, count 2 2006.257.17:54:27.60#ibcon#read 5, iclass 38, count 2 2006.257.17:54:27.60#ibcon#about to read 6, iclass 38, count 2 2006.257.17:54:27.60#ibcon#read 6, iclass 38, count 2 2006.257.17:54:27.60#ibcon#end of sib2, iclass 38, count 2 2006.257.17:54:27.60#ibcon#*after write, iclass 38, count 2 2006.257.17:54:27.60#ibcon#*before return 0, iclass 38, count 2 2006.257.17:54:27.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:27.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:27.60#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.17:54:27.60#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:27.60#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:27.72#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:27.72#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:27.72#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:54:27.72#ibcon#first serial, iclass 38, count 0 2006.257.17:54:27.72#ibcon#enter sib2, iclass 38, count 0 2006.257.17:54:27.72#ibcon#flushed, iclass 38, count 0 2006.257.17:54:27.72#ibcon#about to write, iclass 38, count 0 2006.257.17:54:27.72#ibcon#wrote, iclass 38, count 0 2006.257.17:54:27.72#ibcon#about to read 3, iclass 38, count 0 2006.257.17:54:27.74#ibcon#read 3, iclass 38, count 0 2006.257.17:54:27.74#ibcon#about to read 4, iclass 38, count 0 2006.257.17:54:27.74#ibcon#read 4, iclass 38, count 0 2006.257.17:54:27.74#ibcon#about to read 5, iclass 38, count 0 2006.257.17:54:27.74#ibcon#read 5, iclass 38, count 0 2006.257.17:54:27.74#ibcon#about to read 6, iclass 38, count 0 2006.257.17:54:27.74#ibcon#read 6, iclass 38, count 0 2006.257.17:54:27.74#ibcon#end of sib2, iclass 38, count 0 2006.257.17:54:27.74#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:54:27.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:54:27.74#ibcon#[25=USB\r\n] 2006.257.17:54:27.74#ibcon#*before write, iclass 38, count 0 2006.257.17:54:27.74#ibcon#enter sib2, iclass 38, count 0 2006.257.17:54:27.74#ibcon#flushed, iclass 38, count 0 2006.257.17:54:27.74#ibcon#about to write, iclass 38, count 0 2006.257.17:54:27.74#ibcon#wrote, iclass 38, count 0 2006.257.17:54:27.74#ibcon#about to read 3, iclass 38, count 0 2006.257.17:54:27.77#ibcon#read 3, iclass 38, count 0 2006.257.17:54:27.77#ibcon#about to read 4, iclass 38, count 0 2006.257.17:54:27.77#ibcon#read 4, iclass 38, count 0 2006.257.17:54:27.77#ibcon#about to read 5, iclass 38, count 0 2006.257.17:54:27.77#ibcon#read 5, iclass 38, count 0 2006.257.17:54:27.77#ibcon#about to read 6, iclass 38, count 0 2006.257.17:54:27.77#ibcon#read 6, iclass 38, count 0 2006.257.17:54:27.77#ibcon#end of sib2, iclass 38, count 0 2006.257.17:54:27.77#ibcon#*after write, iclass 38, count 0 2006.257.17:54:27.77#ibcon#*before return 0, iclass 38, count 0 2006.257.17:54:27.77#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:27.77#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:27.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:54:27.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:54:27.77$vck44/valo=5,734.99 2006.257.17:54:27.77#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.17:54:27.77#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.17:54:27.77#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:27.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:27.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:27.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:27.77#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:54:27.77#ibcon#first serial, iclass 40, count 0 2006.257.17:54:27.77#ibcon#enter sib2, iclass 40, count 0 2006.257.17:54:27.77#ibcon#flushed, iclass 40, count 0 2006.257.17:54:27.77#ibcon#about to write, iclass 40, count 0 2006.257.17:54:27.77#ibcon#wrote, iclass 40, count 0 2006.257.17:54:27.77#ibcon#about to read 3, iclass 40, count 0 2006.257.17:54:27.79#ibcon#read 3, iclass 40, count 0 2006.257.17:54:27.79#ibcon#about to read 4, iclass 40, count 0 2006.257.17:54:27.79#ibcon#read 4, iclass 40, count 0 2006.257.17:54:27.79#ibcon#about to read 5, iclass 40, count 0 2006.257.17:54:27.79#ibcon#read 5, iclass 40, count 0 2006.257.17:54:27.79#ibcon#about to read 6, iclass 40, count 0 2006.257.17:54:27.79#ibcon#read 6, iclass 40, count 0 2006.257.17:54:27.79#ibcon#end of sib2, iclass 40, count 0 2006.257.17:54:27.79#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:54:27.79#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:54:27.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.17:54:27.79#ibcon#*before write, iclass 40, count 0 2006.257.17:54:27.79#ibcon#enter sib2, iclass 40, count 0 2006.257.17:54:27.79#ibcon#flushed, iclass 40, count 0 2006.257.17:54:27.79#ibcon#about to write, iclass 40, count 0 2006.257.17:54:27.79#ibcon#wrote, iclass 40, count 0 2006.257.17:54:27.79#ibcon#about to read 3, iclass 40, count 0 2006.257.17:54:27.83#ibcon#read 3, iclass 40, count 0 2006.257.17:54:27.83#ibcon#about to read 4, iclass 40, count 0 2006.257.17:54:27.83#ibcon#read 4, iclass 40, count 0 2006.257.17:54:27.83#ibcon#about to read 5, iclass 40, count 0 2006.257.17:54:27.83#ibcon#read 5, iclass 40, count 0 2006.257.17:54:27.83#ibcon#about to read 6, iclass 40, count 0 2006.257.17:54:27.83#ibcon#read 6, iclass 40, count 0 2006.257.17:54:27.83#ibcon#end of sib2, iclass 40, count 0 2006.257.17:54:27.83#ibcon#*after write, iclass 40, count 0 2006.257.17:54:27.83#ibcon#*before return 0, iclass 40, count 0 2006.257.17:54:27.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:27.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:27.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:54:27.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:54:27.83$vck44/va=5,4 2006.257.17:54:27.83#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.17:54:27.83#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.17:54:27.83#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:27.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:27.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:27.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:27.89#ibcon#enter wrdev, iclass 4, count 2 2006.257.17:54:27.89#ibcon#first serial, iclass 4, count 2 2006.257.17:54:27.89#ibcon#enter sib2, iclass 4, count 2 2006.257.17:54:27.89#ibcon#flushed, iclass 4, count 2 2006.257.17:54:27.89#ibcon#about to write, iclass 4, count 2 2006.257.17:54:27.89#ibcon#wrote, iclass 4, count 2 2006.257.17:54:27.89#ibcon#about to read 3, iclass 4, count 2 2006.257.17:54:27.91#ibcon#read 3, iclass 4, count 2 2006.257.17:54:27.91#ibcon#about to read 4, iclass 4, count 2 2006.257.17:54:27.91#ibcon#read 4, iclass 4, count 2 2006.257.17:54:27.91#ibcon#about to read 5, iclass 4, count 2 2006.257.17:54:27.91#ibcon#read 5, iclass 4, count 2 2006.257.17:54:27.91#ibcon#about to read 6, iclass 4, count 2 2006.257.17:54:27.91#ibcon#read 6, iclass 4, count 2 2006.257.17:54:27.91#ibcon#end of sib2, iclass 4, count 2 2006.257.17:54:27.91#ibcon#*mode == 0, iclass 4, count 2 2006.257.17:54:27.91#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.17:54:27.91#ibcon#[25=AT05-04\r\n] 2006.257.17:54:27.91#ibcon#*before write, iclass 4, count 2 2006.257.17:54:27.91#ibcon#enter sib2, iclass 4, count 2 2006.257.17:54:27.91#ibcon#flushed, iclass 4, count 2 2006.257.17:54:27.91#ibcon#about to write, iclass 4, count 2 2006.257.17:54:27.91#ibcon#wrote, iclass 4, count 2 2006.257.17:54:27.91#ibcon#about to read 3, iclass 4, count 2 2006.257.17:54:27.94#ibcon#read 3, iclass 4, count 2 2006.257.17:54:27.94#ibcon#about to read 4, iclass 4, count 2 2006.257.17:54:27.94#ibcon#read 4, iclass 4, count 2 2006.257.17:54:27.94#ibcon#about to read 5, iclass 4, count 2 2006.257.17:54:27.94#ibcon#read 5, iclass 4, count 2 2006.257.17:54:27.94#ibcon#about to read 6, iclass 4, count 2 2006.257.17:54:27.94#ibcon#read 6, iclass 4, count 2 2006.257.17:54:27.94#ibcon#end of sib2, iclass 4, count 2 2006.257.17:54:27.94#ibcon#*after write, iclass 4, count 2 2006.257.17:54:27.94#ibcon#*before return 0, iclass 4, count 2 2006.257.17:54:27.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:27.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:27.94#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.17:54:27.94#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:27.94#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:28.06#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:28.06#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:28.06#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:54:28.06#ibcon#first serial, iclass 4, count 0 2006.257.17:54:28.06#ibcon#enter sib2, iclass 4, count 0 2006.257.17:54:28.06#ibcon#flushed, iclass 4, count 0 2006.257.17:54:28.06#ibcon#about to write, iclass 4, count 0 2006.257.17:54:28.06#ibcon#wrote, iclass 4, count 0 2006.257.17:54:28.06#ibcon#about to read 3, iclass 4, count 0 2006.257.17:54:28.08#ibcon#read 3, iclass 4, count 0 2006.257.17:54:28.08#ibcon#about to read 4, iclass 4, count 0 2006.257.17:54:28.08#ibcon#read 4, iclass 4, count 0 2006.257.17:54:28.08#ibcon#about to read 5, iclass 4, count 0 2006.257.17:54:28.08#ibcon#read 5, iclass 4, count 0 2006.257.17:54:28.08#ibcon#about to read 6, iclass 4, count 0 2006.257.17:54:28.08#ibcon#read 6, iclass 4, count 0 2006.257.17:54:28.08#ibcon#end of sib2, iclass 4, count 0 2006.257.17:54:28.08#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:54:28.08#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:54:28.08#ibcon#[25=USB\r\n] 2006.257.17:54:28.08#ibcon#*before write, iclass 4, count 0 2006.257.17:54:28.08#ibcon#enter sib2, iclass 4, count 0 2006.257.17:54:28.08#ibcon#flushed, iclass 4, count 0 2006.257.17:54:28.08#ibcon#about to write, iclass 4, count 0 2006.257.17:54:28.08#ibcon#wrote, iclass 4, count 0 2006.257.17:54:28.08#ibcon#about to read 3, iclass 4, count 0 2006.257.17:54:28.11#ibcon#read 3, iclass 4, count 0 2006.257.17:54:28.11#ibcon#about to read 4, iclass 4, count 0 2006.257.17:54:28.11#ibcon#read 4, iclass 4, count 0 2006.257.17:54:28.11#ibcon#about to read 5, iclass 4, count 0 2006.257.17:54:28.11#ibcon#read 5, iclass 4, count 0 2006.257.17:54:28.11#ibcon#about to read 6, iclass 4, count 0 2006.257.17:54:28.11#ibcon#read 6, iclass 4, count 0 2006.257.17:54:28.11#ibcon#end of sib2, iclass 4, count 0 2006.257.17:54:28.11#ibcon#*after write, iclass 4, count 0 2006.257.17:54:28.11#ibcon#*before return 0, iclass 4, count 0 2006.257.17:54:28.11#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:28.11#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:28.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:54:28.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:54:28.11$vck44/valo=6,814.99 2006.257.17:54:28.11#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.17:54:28.11#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.17:54:28.11#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:28.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:28.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:28.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:28.11#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:54:28.11#ibcon#first serial, iclass 6, count 0 2006.257.17:54:28.11#ibcon#enter sib2, iclass 6, count 0 2006.257.17:54:28.11#ibcon#flushed, iclass 6, count 0 2006.257.17:54:28.11#ibcon#about to write, iclass 6, count 0 2006.257.17:54:28.11#ibcon#wrote, iclass 6, count 0 2006.257.17:54:28.11#ibcon#about to read 3, iclass 6, count 0 2006.257.17:54:28.13#ibcon#read 3, iclass 6, count 0 2006.257.17:54:28.13#ibcon#about to read 4, iclass 6, count 0 2006.257.17:54:28.13#ibcon#read 4, iclass 6, count 0 2006.257.17:54:28.13#ibcon#about to read 5, iclass 6, count 0 2006.257.17:54:28.13#ibcon#read 5, iclass 6, count 0 2006.257.17:54:28.13#ibcon#about to read 6, iclass 6, count 0 2006.257.17:54:28.13#ibcon#read 6, iclass 6, count 0 2006.257.17:54:28.13#ibcon#end of sib2, iclass 6, count 0 2006.257.17:54:28.13#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:54:28.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:54:28.13#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.17:54:28.13#ibcon#*before write, iclass 6, count 0 2006.257.17:54:28.13#ibcon#enter sib2, iclass 6, count 0 2006.257.17:54:28.13#ibcon#flushed, iclass 6, count 0 2006.257.17:54:28.13#ibcon#about to write, iclass 6, count 0 2006.257.17:54:28.13#ibcon#wrote, iclass 6, count 0 2006.257.17:54:28.13#ibcon#about to read 3, iclass 6, count 0 2006.257.17:54:28.17#ibcon#read 3, iclass 6, count 0 2006.257.17:54:28.17#ibcon#about to read 4, iclass 6, count 0 2006.257.17:54:28.17#ibcon#read 4, iclass 6, count 0 2006.257.17:54:28.17#ibcon#about to read 5, iclass 6, count 0 2006.257.17:54:28.17#ibcon#read 5, iclass 6, count 0 2006.257.17:54:28.17#ibcon#about to read 6, iclass 6, count 0 2006.257.17:54:28.17#ibcon#read 6, iclass 6, count 0 2006.257.17:54:28.17#ibcon#end of sib2, iclass 6, count 0 2006.257.17:54:28.17#ibcon#*after write, iclass 6, count 0 2006.257.17:54:28.17#ibcon#*before return 0, iclass 6, count 0 2006.257.17:54:28.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:28.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:28.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:54:28.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:54:28.17$vck44/va=6,4 2006.257.17:54:28.17#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.17:54:28.17#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.17:54:28.17#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:28.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:28.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:28.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:28.23#ibcon#enter wrdev, iclass 10, count 2 2006.257.17:54:28.23#ibcon#first serial, iclass 10, count 2 2006.257.17:54:28.23#ibcon#enter sib2, iclass 10, count 2 2006.257.17:54:28.23#ibcon#flushed, iclass 10, count 2 2006.257.17:54:28.23#ibcon#about to write, iclass 10, count 2 2006.257.17:54:28.23#ibcon#wrote, iclass 10, count 2 2006.257.17:54:28.23#ibcon#about to read 3, iclass 10, count 2 2006.257.17:54:28.25#ibcon#read 3, iclass 10, count 2 2006.257.17:54:28.25#ibcon#about to read 4, iclass 10, count 2 2006.257.17:54:28.25#ibcon#read 4, iclass 10, count 2 2006.257.17:54:28.25#ibcon#about to read 5, iclass 10, count 2 2006.257.17:54:28.25#ibcon#read 5, iclass 10, count 2 2006.257.17:54:28.25#ibcon#about to read 6, iclass 10, count 2 2006.257.17:54:28.25#ibcon#read 6, iclass 10, count 2 2006.257.17:54:28.25#ibcon#end of sib2, iclass 10, count 2 2006.257.17:54:28.25#ibcon#*mode == 0, iclass 10, count 2 2006.257.17:54:28.25#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.17:54:28.25#ibcon#[25=AT06-04\r\n] 2006.257.17:54:28.25#ibcon#*before write, iclass 10, count 2 2006.257.17:54:28.25#ibcon#enter sib2, iclass 10, count 2 2006.257.17:54:28.25#ibcon#flushed, iclass 10, count 2 2006.257.17:54:28.25#ibcon#about to write, iclass 10, count 2 2006.257.17:54:28.25#ibcon#wrote, iclass 10, count 2 2006.257.17:54:28.25#ibcon#about to read 3, iclass 10, count 2 2006.257.17:54:28.28#ibcon#read 3, iclass 10, count 2 2006.257.17:54:28.28#ibcon#about to read 4, iclass 10, count 2 2006.257.17:54:28.28#ibcon#read 4, iclass 10, count 2 2006.257.17:54:28.28#ibcon#about to read 5, iclass 10, count 2 2006.257.17:54:28.28#ibcon#read 5, iclass 10, count 2 2006.257.17:54:28.28#ibcon#about to read 6, iclass 10, count 2 2006.257.17:54:28.28#ibcon#read 6, iclass 10, count 2 2006.257.17:54:28.28#ibcon#end of sib2, iclass 10, count 2 2006.257.17:54:28.28#ibcon#*after write, iclass 10, count 2 2006.257.17:54:28.28#ibcon#*before return 0, iclass 10, count 2 2006.257.17:54:28.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:28.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:28.28#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.17:54:28.28#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:28.28#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:28.40#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:28.40#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:28.40#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:54:28.40#ibcon#first serial, iclass 10, count 0 2006.257.17:54:28.40#ibcon#enter sib2, iclass 10, count 0 2006.257.17:54:28.40#ibcon#flushed, iclass 10, count 0 2006.257.17:54:28.40#ibcon#about to write, iclass 10, count 0 2006.257.17:54:28.40#ibcon#wrote, iclass 10, count 0 2006.257.17:54:28.40#ibcon#about to read 3, iclass 10, count 0 2006.257.17:54:28.42#ibcon#read 3, iclass 10, count 0 2006.257.17:54:28.42#ibcon#about to read 4, iclass 10, count 0 2006.257.17:54:28.42#ibcon#read 4, iclass 10, count 0 2006.257.17:54:28.42#ibcon#about to read 5, iclass 10, count 0 2006.257.17:54:28.42#ibcon#read 5, iclass 10, count 0 2006.257.17:54:28.42#ibcon#about to read 6, iclass 10, count 0 2006.257.17:54:28.42#ibcon#read 6, iclass 10, count 0 2006.257.17:54:28.42#ibcon#end of sib2, iclass 10, count 0 2006.257.17:54:28.42#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:54:28.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:54:28.42#ibcon#[25=USB\r\n] 2006.257.17:54:28.42#ibcon#*before write, iclass 10, count 0 2006.257.17:54:28.42#ibcon#enter sib2, iclass 10, count 0 2006.257.17:54:28.42#ibcon#flushed, iclass 10, count 0 2006.257.17:54:28.42#ibcon#about to write, iclass 10, count 0 2006.257.17:54:28.42#ibcon#wrote, iclass 10, count 0 2006.257.17:54:28.42#ibcon#about to read 3, iclass 10, count 0 2006.257.17:54:28.45#ibcon#read 3, iclass 10, count 0 2006.257.17:54:28.45#ibcon#about to read 4, iclass 10, count 0 2006.257.17:54:28.45#ibcon#read 4, iclass 10, count 0 2006.257.17:54:28.45#ibcon#about to read 5, iclass 10, count 0 2006.257.17:54:28.45#ibcon#read 5, iclass 10, count 0 2006.257.17:54:28.45#ibcon#about to read 6, iclass 10, count 0 2006.257.17:54:28.45#ibcon#read 6, iclass 10, count 0 2006.257.17:54:28.45#ibcon#end of sib2, iclass 10, count 0 2006.257.17:54:28.45#ibcon#*after write, iclass 10, count 0 2006.257.17:54:28.45#ibcon#*before return 0, iclass 10, count 0 2006.257.17:54:28.45#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:28.45#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:28.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:54:28.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:54:28.45$vck44/valo=7,864.99 2006.257.17:54:28.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.17:54:28.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.17:54:28.45#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:28.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:28.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:28.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:28.45#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:54:28.45#ibcon#first serial, iclass 12, count 0 2006.257.17:54:28.45#ibcon#enter sib2, iclass 12, count 0 2006.257.17:54:28.45#ibcon#flushed, iclass 12, count 0 2006.257.17:54:28.45#ibcon#about to write, iclass 12, count 0 2006.257.17:54:28.45#ibcon#wrote, iclass 12, count 0 2006.257.17:54:28.45#ibcon#about to read 3, iclass 12, count 0 2006.257.17:54:28.47#ibcon#read 3, iclass 12, count 0 2006.257.17:54:28.47#ibcon#about to read 4, iclass 12, count 0 2006.257.17:54:28.47#ibcon#read 4, iclass 12, count 0 2006.257.17:54:28.47#ibcon#about to read 5, iclass 12, count 0 2006.257.17:54:28.47#ibcon#read 5, iclass 12, count 0 2006.257.17:54:28.47#ibcon#about to read 6, iclass 12, count 0 2006.257.17:54:28.47#ibcon#read 6, iclass 12, count 0 2006.257.17:54:28.47#ibcon#end of sib2, iclass 12, count 0 2006.257.17:54:28.47#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:54:28.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:54:28.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.17:54:28.47#ibcon#*before write, iclass 12, count 0 2006.257.17:54:28.47#ibcon#enter sib2, iclass 12, count 0 2006.257.17:54:28.47#ibcon#flushed, iclass 12, count 0 2006.257.17:54:28.47#ibcon#about to write, iclass 12, count 0 2006.257.17:54:28.47#ibcon#wrote, iclass 12, count 0 2006.257.17:54:28.47#ibcon#about to read 3, iclass 12, count 0 2006.257.17:54:28.51#ibcon#read 3, iclass 12, count 0 2006.257.17:54:28.51#ibcon#about to read 4, iclass 12, count 0 2006.257.17:54:28.51#ibcon#read 4, iclass 12, count 0 2006.257.17:54:28.51#ibcon#about to read 5, iclass 12, count 0 2006.257.17:54:28.51#ibcon#read 5, iclass 12, count 0 2006.257.17:54:28.51#ibcon#about to read 6, iclass 12, count 0 2006.257.17:54:28.51#ibcon#read 6, iclass 12, count 0 2006.257.17:54:28.51#ibcon#end of sib2, iclass 12, count 0 2006.257.17:54:28.51#ibcon#*after write, iclass 12, count 0 2006.257.17:54:28.51#ibcon#*before return 0, iclass 12, count 0 2006.257.17:54:28.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:28.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:28.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:54:28.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:54:28.51$vck44/va=7,4 2006.257.17:54:28.51#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.17:54:28.51#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.17:54:28.51#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:28.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:28.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:28.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:28.57#ibcon#enter wrdev, iclass 14, count 2 2006.257.17:54:28.57#ibcon#first serial, iclass 14, count 2 2006.257.17:54:28.57#ibcon#enter sib2, iclass 14, count 2 2006.257.17:54:28.57#ibcon#flushed, iclass 14, count 2 2006.257.17:54:28.57#ibcon#about to write, iclass 14, count 2 2006.257.17:54:28.57#ibcon#wrote, iclass 14, count 2 2006.257.17:54:28.57#ibcon#about to read 3, iclass 14, count 2 2006.257.17:54:28.59#ibcon#read 3, iclass 14, count 2 2006.257.17:54:28.59#ibcon#about to read 4, iclass 14, count 2 2006.257.17:54:28.59#ibcon#read 4, iclass 14, count 2 2006.257.17:54:28.59#ibcon#about to read 5, iclass 14, count 2 2006.257.17:54:28.59#ibcon#read 5, iclass 14, count 2 2006.257.17:54:28.59#ibcon#about to read 6, iclass 14, count 2 2006.257.17:54:28.59#ibcon#read 6, iclass 14, count 2 2006.257.17:54:28.59#ibcon#end of sib2, iclass 14, count 2 2006.257.17:54:28.59#ibcon#*mode == 0, iclass 14, count 2 2006.257.17:54:28.59#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.17:54:28.59#ibcon#[25=AT07-04\r\n] 2006.257.17:54:28.59#ibcon#*before write, iclass 14, count 2 2006.257.17:54:28.59#ibcon#enter sib2, iclass 14, count 2 2006.257.17:54:28.59#ibcon#flushed, iclass 14, count 2 2006.257.17:54:28.59#ibcon#about to write, iclass 14, count 2 2006.257.17:54:28.59#ibcon#wrote, iclass 14, count 2 2006.257.17:54:28.59#ibcon#about to read 3, iclass 14, count 2 2006.257.17:54:28.62#ibcon#read 3, iclass 14, count 2 2006.257.17:54:28.62#ibcon#about to read 4, iclass 14, count 2 2006.257.17:54:28.62#ibcon#read 4, iclass 14, count 2 2006.257.17:54:28.62#ibcon#about to read 5, iclass 14, count 2 2006.257.17:54:28.62#ibcon#read 5, iclass 14, count 2 2006.257.17:54:28.62#ibcon#about to read 6, iclass 14, count 2 2006.257.17:54:28.62#ibcon#read 6, iclass 14, count 2 2006.257.17:54:28.62#ibcon#end of sib2, iclass 14, count 2 2006.257.17:54:28.62#ibcon#*after write, iclass 14, count 2 2006.257.17:54:28.62#ibcon#*before return 0, iclass 14, count 2 2006.257.17:54:28.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:28.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:28.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.17:54:28.62#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:28.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:28.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:28.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:28.74#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:54:28.74#ibcon#first serial, iclass 14, count 0 2006.257.17:54:28.74#ibcon#enter sib2, iclass 14, count 0 2006.257.17:54:28.74#ibcon#flushed, iclass 14, count 0 2006.257.17:54:28.74#ibcon#about to write, iclass 14, count 0 2006.257.17:54:28.74#ibcon#wrote, iclass 14, count 0 2006.257.17:54:28.74#ibcon#about to read 3, iclass 14, count 0 2006.257.17:54:28.76#ibcon#read 3, iclass 14, count 0 2006.257.17:54:28.76#ibcon#about to read 4, iclass 14, count 0 2006.257.17:54:28.76#ibcon#read 4, iclass 14, count 0 2006.257.17:54:28.76#ibcon#about to read 5, iclass 14, count 0 2006.257.17:54:28.76#ibcon#read 5, iclass 14, count 0 2006.257.17:54:28.76#ibcon#about to read 6, iclass 14, count 0 2006.257.17:54:28.76#ibcon#read 6, iclass 14, count 0 2006.257.17:54:28.76#ibcon#end of sib2, iclass 14, count 0 2006.257.17:54:28.76#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:54:28.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:54:28.76#ibcon#[25=USB\r\n] 2006.257.17:54:28.76#ibcon#*before write, iclass 14, count 0 2006.257.17:54:28.76#ibcon#enter sib2, iclass 14, count 0 2006.257.17:54:28.76#ibcon#flushed, iclass 14, count 0 2006.257.17:54:28.76#ibcon#about to write, iclass 14, count 0 2006.257.17:54:28.76#ibcon#wrote, iclass 14, count 0 2006.257.17:54:28.76#ibcon#about to read 3, iclass 14, count 0 2006.257.17:54:28.79#ibcon#read 3, iclass 14, count 0 2006.257.17:54:28.79#ibcon#about to read 4, iclass 14, count 0 2006.257.17:54:28.79#ibcon#read 4, iclass 14, count 0 2006.257.17:54:28.79#ibcon#about to read 5, iclass 14, count 0 2006.257.17:54:28.79#ibcon#read 5, iclass 14, count 0 2006.257.17:54:28.79#ibcon#about to read 6, iclass 14, count 0 2006.257.17:54:28.79#ibcon#read 6, iclass 14, count 0 2006.257.17:54:28.79#ibcon#end of sib2, iclass 14, count 0 2006.257.17:54:28.79#ibcon#*after write, iclass 14, count 0 2006.257.17:54:28.79#ibcon#*before return 0, iclass 14, count 0 2006.257.17:54:28.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:28.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:28.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:54:28.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:54:28.79$vck44/valo=8,884.99 2006.257.17:54:28.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.17:54:28.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.17:54:28.79#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:28.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:28.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:28.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:28.79#ibcon#enter wrdev, iclass 16, count 0 2006.257.17:54:28.79#ibcon#first serial, iclass 16, count 0 2006.257.17:54:28.79#ibcon#enter sib2, iclass 16, count 0 2006.257.17:54:28.79#ibcon#flushed, iclass 16, count 0 2006.257.17:54:28.79#ibcon#about to write, iclass 16, count 0 2006.257.17:54:28.79#ibcon#wrote, iclass 16, count 0 2006.257.17:54:28.79#ibcon#about to read 3, iclass 16, count 0 2006.257.17:54:28.81#ibcon#read 3, iclass 16, count 0 2006.257.17:54:28.81#ibcon#about to read 4, iclass 16, count 0 2006.257.17:54:28.81#ibcon#read 4, iclass 16, count 0 2006.257.17:54:28.81#ibcon#about to read 5, iclass 16, count 0 2006.257.17:54:28.81#ibcon#read 5, iclass 16, count 0 2006.257.17:54:28.81#ibcon#about to read 6, iclass 16, count 0 2006.257.17:54:28.81#ibcon#read 6, iclass 16, count 0 2006.257.17:54:28.81#ibcon#end of sib2, iclass 16, count 0 2006.257.17:54:28.81#ibcon#*mode == 0, iclass 16, count 0 2006.257.17:54:28.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.17:54:28.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.17:54:28.81#ibcon#*before write, iclass 16, count 0 2006.257.17:54:28.81#ibcon#enter sib2, iclass 16, count 0 2006.257.17:54:28.81#ibcon#flushed, iclass 16, count 0 2006.257.17:54:28.81#ibcon#about to write, iclass 16, count 0 2006.257.17:54:28.81#ibcon#wrote, iclass 16, count 0 2006.257.17:54:28.81#ibcon#about to read 3, iclass 16, count 0 2006.257.17:54:28.85#ibcon#read 3, iclass 16, count 0 2006.257.17:54:28.85#ibcon#about to read 4, iclass 16, count 0 2006.257.17:54:28.85#ibcon#read 4, iclass 16, count 0 2006.257.17:54:28.85#ibcon#about to read 5, iclass 16, count 0 2006.257.17:54:28.85#ibcon#read 5, iclass 16, count 0 2006.257.17:54:28.85#ibcon#about to read 6, iclass 16, count 0 2006.257.17:54:28.85#ibcon#read 6, iclass 16, count 0 2006.257.17:54:28.85#ibcon#end of sib2, iclass 16, count 0 2006.257.17:54:28.85#ibcon#*after write, iclass 16, count 0 2006.257.17:54:28.85#ibcon#*before return 0, iclass 16, count 0 2006.257.17:54:28.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:28.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:28.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.17:54:28.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.17:54:28.85$vck44/va=8,4 2006.257.17:54:28.85#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.17:54:28.85#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.17:54:28.85#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:28.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:54:28.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:54:28.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:54:28.91#ibcon#enter wrdev, iclass 18, count 2 2006.257.17:54:28.91#ibcon#first serial, iclass 18, count 2 2006.257.17:54:28.91#ibcon#enter sib2, iclass 18, count 2 2006.257.17:54:28.91#ibcon#flushed, iclass 18, count 2 2006.257.17:54:28.91#ibcon#about to write, iclass 18, count 2 2006.257.17:54:28.91#ibcon#wrote, iclass 18, count 2 2006.257.17:54:28.91#ibcon#about to read 3, iclass 18, count 2 2006.257.17:54:28.93#ibcon#read 3, iclass 18, count 2 2006.257.17:54:28.93#ibcon#about to read 4, iclass 18, count 2 2006.257.17:54:28.93#ibcon#read 4, iclass 18, count 2 2006.257.17:54:28.93#ibcon#about to read 5, iclass 18, count 2 2006.257.17:54:28.93#ibcon#read 5, iclass 18, count 2 2006.257.17:54:28.93#ibcon#about to read 6, iclass 18, count 2 2006.257.17:54:28.93#ibcon#read 6, iclass 18, count 2 2006.257.17:54:28.93#ibcon#end of sib2, iclass 18, count 2 2006.257.17:54:28.93#ibcon#*mode == 0, iclass 18, count 2 2006.257.17:54:28.93#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.17:54:28.93#ibcon#[25=AT08-04\r\n] 2006.257.17:54:28.93#ibcon#*before write, iclass 18, count 2 2006.257.17:54:28.93#ibcon#enter sib2, iclass 18, count 2 2006.257.17:54:28.93#ibcon#flushed, iclass 18, count 2 2006.257.17:54:28.93#ibcon#about to write, iclass 18, count 2 2006.257.17:54:28.93#ibcon#wrote, iclass 18, count 2 2006.257.17:54:28.93#ibcon#about to read 3, iclass 18, count 2 2006.257.17:54:28.96#ibcon#read 3, iclass 18, count 2 2006.257.17:54:28.96#ibcon#about to read 4, iclass 18, count 2 2006.257.17:54:28.96#ibcon#read 4, iclass 18, count 2 2006.257.17:54:28.96#ibcon#about to read 5, iclass 18, count 2 2006.257.17:54:28.96#ibcon#read 5, iclass 18, count 2 2006.257.17:54:28.96#ibcon#about to read 6, iclass 18, count 2 2006.257.17:54:28.96#ibcon#read 6, iclass 18, count 2 2006.257.17:54:28.96#ibcon#end of sib2, iclass 18, count 2 2006.257.17:54:28.96#ibcon#*after write, iclass 18, count 2 2006.257.17:54:28.96#ibcon#*before return 0, iclass 18, count 2 2006.257.17:54:28.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:54:28.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.17:54:28.96#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.17:54:28.96#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:28.96#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:54:29.08#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:54:29.08#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:54:29.08#ibcon#enter wrdev, iclass 18, count 0 2006.257.17:54:29.08#ibcon#first serial, iclass 18, count 0 2006.257.17:54:29.08#ibcon#enter sib2, iclass 18, count 0 2006.257.17:54:29.08#ibcon#flushed, iclass 18, count 0 2006.257.17:54:29.08#ibcon#about to write, iclass 18, count 0 2006.257.17:54:29.08#ibcon#wrote, iclass 18, count 0 2006.257.17:54:29.08#ibcon#about to read 3, iclass 18, count 0 2006.257.17:54:29.10#ibcon#read 3, iclass 18, count 0 2006.257.17:54:29.10#ibcon#about to read 4, iclass 18, count 0 2006.257.17:54:29.10#ibcon#read 4, iclass 18, count 0 2006.257.17:54:29.10#ibcon#about to read 5, iclass 18, count 0 2006.257.17:54:29.10#ibcon#read 5, iclass 18, count 0 2006.257.17:54:29.10#ibcon#about to read 6, iclass 18, count 0 2006.257.17:54:29.10#ibcon#read 6, iclass 18, count 0 2006.257.17:54:29.10#ibcon#end of sib2, iclass 18, count 0 2006.257.17:54:29.10#ibcon#*mode == 0, iclass 18, count 0 2006.257.17:54:29.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.17:54:29.10#ibcon#[25=USB\r\n] 2006.257.17:54:29.10#ibcon#*before write, iclass 18, count 0 2006.257.17:54:29.10#ibcon#enter sib2, iclass 18, count 0 2006.257.17:54:29.10#ibcon#flushed, iclass 18, count 0 2006.257.17:54:29.10#ibcon#about to write, iclass 18, count 0 2006.257.17:54:29.10#ibcon#wrote, iclass 18, count 0 2006.257.17:54:29.10#ibcon#about to read 3, iclass 18, count 0 2006.257.17:54:29.13#ibcon#read 3, iclass 18, count 0 2006.257.17:54:29.13#ibcon#about to read 4, iclass 18, count 0 2006.257.17:54:29.13#ibcon#read 4, iclass 18, count 0 2006.257.17:54:29.13#ibcon#about to read 5, iclass 18, count 0 2006.257.17:54:29.13#ibcon#read 5, iclass 18, count 0 2006.257.17:54:29.13#ibcon#about to read 6, iclass 18, count 0 2006.257.17:54:29.13#ibcon#read 6, iclass 18, count 0 2006.257.17:54:29.13#ibcon#end of sib2, iclass 18, count 0 2006.257.17:54:29.13#ibcon#*after write, iclass 18, count 0 2006.257.17:54:29.13#ibcon#*before return 0, iclass 18, count 0 2006.257.17:54:29.13#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:54:29.13#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.17:54:29.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.17:54:29.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.17:54:29.13$vck44/vblo=1,629.99 2006.257.17:54:29.13#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.17:54:29.13#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.17:54:29.13#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:29.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:54:29.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:54:29.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:54:29.13#ibcon#enter wrdev, iclass 20, count 0 2006.257.17:54:29.13#ibcon#first serial, iclass 20, count 0 2006.257.17:54:29.13#ibcon#enter sib2, iclass 20, count 0 2006.257.17:54:29.13#ibcon#flushed, iclass 20, count 0 2006.257.17:54:29.13#ibcon#about to write, iclass 20, count 0 2006.257.17:54:29.13#ibcon#wrote, iclass 20, count 0 2006.257.17:54:29.13#ibcon#about to read 3, iclass 20, count 0 2006.257.17:54:29.15#ibcon#read 3, iclass 20, count 0 2006.257.17:54:29.15#ibcon#about to read 4, iclass 20, count 0 2006.257.17:54:29.15#ibcon#read 4, iclass 20, count 0 2006.257.17:54:29.15#ibcon#about to read 5, iclass 20, count 0 2006.257.17:54:29.15#ibcon#read 5, iclass 20, count 0 2006.257.17:54:29.15#ibcon#about to read 6, iclass 20, count 0 2006.257.17:54:29.15#ibcon#read 6, iclass 20, count 0 2006.257.17:54:29.15#ibcon#end of sib2, iclass 20, count 0 2006.257.17:54:29.15#ibcon#*mode == 0, iclass 20, count 0 2006.257.17:54:29.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.17:54:29.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.17:54:29.15#ibcon#*before write, iclass 20, count 0 2006.257.17:54:29.15#ibcon#enter sib2, iclass 20, count 0 2006.257.17:54:29.15#ibcon#flushed, iclass 20, count 0 2006.257.17:54:29.15#ibcon#about to write, iclass 20, count 0 2006.257.17:54:29.15#ibcon#wrote, iclass 20, count 0 2006.257.17:54:29.15#ibcon#about to read 3, iclass 20, count 0 2006.257.17:54:29.19#ibcon#read 3, iclass 20, count 0 2006.257.17:54:29.19#ibcon#about to read 4, iclass 20, count 0 2006.257.17:54:29.19#ibcon#read 4, iclass 20, count 0 2006.257.17:54:29.19#ibcon#about to read 5, iclass 20, count 0 2006.257.17:54:29.19#ibcon#read 5, iclass 20, count 0 2006.257.17:54:29.19#ibcon#about to read 6, iclass 20, count 0 2006.257.17:54:29.19#ibcon#read 6, iclass 20, count 0 2006.257.17:54:29.19#ibcon#end of sib2, iclass 20, count 0 2006.257.17:54:29.19#ibcon#*after write, iclass 20, count 0 2006.257.17:54:29.19#ibcon#*before return 0, iclass 20, count 0 2006.257.17:54:29.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:54:29.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.17:54:29.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.17:54:29.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.17:54:29.19$vck44/vb=1,4 2006.257.17:54:29.19#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.17:54:29.19#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.17:54:29.19#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:29.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:54:29.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:54:29.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:54:29.19#ibcon#enter wrdev, iclass 22, count 2 2006.257.17:54:29.19#ibcon#first serial, iclass 22, count 2 2006.257.17:54:29.19#ibcon#enter sib2, iclass 22, count 2 2006.257.17:54:29.19#ibcon#flushed, iclass 22, count 2 2006.257.17:54:29.19#ibcon#about to write, iclass 22, count 2 2006.257.17:54:29.19#ibcon#wrote, iclass 22, count 2 2006.257.17:54:29.19#ibcon#about to read 3, iclass 22, count 2 2006.257.17:54:29.21#ibcon#read 3, iclass 22, count 2 2006.257.17:54:29.21#ibcon#about to read 4, iclass 22, count 2 2006.257.17:54:29.21#ibcon#read 4, iclass 22, count 2 2006.257.17:54:29.21#ibcon#about to read 5, iclass 22, count 2 2006.257.17:54:29.21#ibcon#read 5, iclass 22, count 2 2006.257.17:54:29.21#ibcon#about to read 6, iclass 22, count 2 2006.257.17:54:29.21#ibcon#read 6, iclass 22, count 2 2006.257.17:54:29.21#ibcon#end of sib2, iclass 22, count 2 2006.257.17:54:29.21#ibcon#*mode == 0, iclass 22, count 2 2006.257.17:54:29.21#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.17:54:29.21#ibcon#[27=AT01-04\r\n] 2006.257.17:54:29.21#ibcon#*before write, iclass 22, count 2 2006.257.17:54:29.21#ibcon#enter sib2, iclass 22, count 2 2006.257.17:54:29.21#ibcon#flushed, iclass 22, count 2 2006.257.17:54:29.21#ibcon#about to write, iclass 22, count 2 2006.257.17:54:29.21#ibcon#wrote, iclass 22, count 2 2006.257.17:54:29.21#ibcon#about to read 3, iclass 22, count 2 2006.257.17:54:29.24#ibcon#read 3, iclass 22, count 2 2006.257.17:54:29.24#ibcon#about to read 4, iclass 22, count 2 2006.257.17:54:29.24#ibcon#read 4, iclass 22, count 2 2006.257.17:54:29.24#ibcon#about to read 5, iclass 22, count 2 2006.257.17:54:29.24#ibcon#read 5, iclass 22, count 2 2006.257.17:54:29.24#ibcon#about to read 6, iclass 22, count 2 2006.257.17:54:29.24#ibcon#read 6, iclass 22, count 2 2006.257.17:54:29.24#ibcon#end of sib2, iclass 22, count 2 2006.257.17:54:29.24#ibcon#*after write, iclass 22, count 2 2006.257.17:54:29.24#ibcon#*before return 0, iclass 22, count 2 2006.257.17:54:29.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:54:29.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.17:54:29.24#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.17:54:29.24#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:29.24#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:54:29.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:54:29.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:54:29.36#ibcon#enter wrdev, iclass 22, count 0 2006.257.17:54:29.36#ibcon#first serial, iclass 22, count 0 2006.257.17:54:29.36#ibcon#enter sib2, iclass 22, count 0 2006.257.17:54:29.36#ibcon#flushed, iclass 22, count 0 2006.257.17:54:29.36#ibcon#about to write, iclass 22, count 0 2006.257.17:54:29.36#ibcon#wrote, iclass 22, count 0 2006.257.17:54:29.36#ibcon#about to read 3, iclass 22, count 0 2006.257.17:54:29.38#ibcon#read 3, iclass 22, count 0 2006.257.17:54:29.38#ibcon#about to read 4, iclass 22, count 0 2006.257.17:54:29.38#ibcon#read 4, iclass 22, count 0 2006.257.17:54:29.38#ibcon#about to read 5, iclass 22, count 0 2006.257.17:54:29.38#ibcon#read 5, iclass 22, count 0 2006.257.17:54:29.38#ibcon#about to read 6, iclass 22, count 0 2006.257.17:54:29.38#ibcon#read 6, iclass 22, count 0 2006.257.17:54:29.38#ibcon#end of sib2, iclass 22, count 0 2006.257.17:54:29.38#ibcon#*mode == 0, iclass 22, count 0 2006.257.17:54:29.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.17:54:29.38#ibcon#[27=USB\r\n] 2006.257.17:54:29.38#ibcon#*before write, iclass 22, count 0 2006.257.17:54:29.38#ibcon#enter sib2, iclass 22, count 0 2006.257.17:54:29.38#ibcon#flushed, iclass 22, count 0 2006.257.17:54:29.38#ibcon#about to write, iclass 22, count 0 2006.257.17:54:29.38#ibcon#wrote, iclass 22, count 0 2006.257.17:54:29.38#ibcon#about to read 3, iclass 22, count 0 2006.257.17:54:29.41#ibcon#read 3, iclass 22, count 0 2006.257.17:54:29.41#ibcon#about to read 4, iclass 22, count 0 2006.257.17:54:29.41#ibcon#read 4, iclass 22, count 0 2006.257.17:54:29.41#ibcon#about to read 5, iclass 22, count 0 2006.257.17:54:29.41#ibcon#read 5, iclass 22, count 0 2006.257.17:54:29.41#ibcon#about to read 6, iclass 22, count 0 2006.257.17:54:29.41#ibcon#read 6, iclass 22, count 0 2006.257.17:54:29.41#ibcon#end of sib2, iclass 22, count 0 2006.257.17:54:29.41#ibcon#*after write, iclass 22, count 0 2006.257.17:54:29.41#ibcon#*before return 0, iclass 22, count 0 2006.257.17:54:29.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:54:29.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.17:54:29.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.17:54:29.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.17:54:29.41$vck44/vblo=2,634.99 2006.257.17:54:29.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.17:54:29.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.17:54:29.41#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:29.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:29.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:29.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:29.41#ibcon#enter wrdev, iclass 24, count 0 2006.257.17:54:29.41#ibcon#first serial, iclass 24, count 0 2006.257.17:54:29.41#ibcon#enter sib2, iclass 24, count 0 2006.257.17:54:29.41#ibcon#flushed, iclass 24, count 0 2006.257.17:54:29.41#ibcon#about to write, iclass 24, count 0 2006.257.17:54:29.41#ibcon#wrote, iclass 24, count 0 2006.257.17:54:29.41#ibcon#about to read 3, iclass 24, count 0 2006.257.17:54:29.43#ibcon#read 3, iclass 24, count 0 2006.257.17:54:29.43#ibcon#about to read 4, iclass 24, count 0 2006.257.17:54:29.43#ibcon#read 4, iclass 24, count 0 2006.257.17:54:29.43#ibcon#about to read 5, iclass 24, count 0 2006.257.17:54:29.43#ibcon#read 5, iclass 24, count 0 2006.257.17:54:29.43#ibcon#about to read 6, iclass 24, count 0 2006.257.17:54:29.43#ibcon#read 6, iclass 24, count 0 2006.257.17:54:29.43#ibcon#end of sib2, iclass 24, count 0 2006.257.17:54:29.43#ibcon#*mode == 0, iclass 24, count 0 2006.257.17:54:29.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.17:54:29.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.17:54:29.43#ibcon#*before write, iclass 24, count 0 2006.257.17:54:29.43#ibcon#enter sib2, iclass 24, count 0 2006.257.17:54:29.43#ibcon#flushed, iclass 24, count 0 2006.257.17:54:29.43#ibcon#about to write, iclass 24, count 0 2006.257.17:54:29.43#ibcon#wrote, iclass 24, count 0 2006.257.17:54:29.43#ibcon#about to read 3, iclass 24, count 0 2006.257.17:54:29.47#ibcon#read 3, iclass 24, count 0 2006.257.17:54:29.47#ibcon#about to read 4, iclass 24, count 0 2006.257.17:54:29.47#ibcon#read 4, iclass 24, count 0 2006.257.17:54:29.47#ibcon#about to read 5, iclass 24, count 0 2006.257.17:54:29.47#ibcon#read 5, iclass 24, count 0 2006.257.17:54:29.47#ibcon#about to read 6, iclass 24, count 0 2006.257.17:54:29.47#ibcon#read 6, iclass 24, count 0 2006.257.17:54:29.47#ibcon#end of sib2, iclass 24, count 0 2006.257.17:54:29.47#ibcon#*after write, iclass 24, count 0 2006.257.17:54:29.47#ibcon#*before return 0, iclass 24, count 0 2006.257.17:54:29.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:29.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.17:54:29.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.17:54:29.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.17:54:29.47$vck44/vb=2,5 2006.257.17:54:29.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.17:54:29.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.17:54:29.47#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:29.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:29.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:29.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:29.53#ibcon#enter wrdev, iclass 26, count 2 2006.257.17:54:29.53#ibcon#first serial, iclass 26, count 2 2006.257.17:54:29.53#ibcon#enter sib2, iclass 26, count 2 2006.257.17:54:29.53#ibcon#flushed, iclass 26, count 2 2006.257.17:54:29.53#ibcon#about to write, iclass 26, count 2 2006.257.17:54:29.53#ibcon#wrote, iclass 26, count 2 2006.257.17:54:29.53#ibcon#about to read 3, iclass 26, count 2 2006.257.17:54:29.55#ibcon#read 3, iclass 26, count 2 2006.257.17:54:29.55#ibcon#about to read 4, iclass 26, count 2 2006.257.17:54:29.55#ibcon#read 4, iclass 26, count 2 2006.257.17:54:29.55#ibcon#about to read 5, iclass 26, count 2 2006.257.17:54:29.55#ibcon#read 5, iclass 26, count 2 2006.257.17:54:29.55#ibcon#about to read 6, iclass 26, count 2 2006.257.17:54:29.55#ibcon#read 6, iclass 26, count 2 2006.257.17:54:29.55#ibcon#end of sib2, iclass 26, count 2 2006.257.17:54:29.55#ibcon#*mode == 0, iclass 26, count 2 2006.257.17:54:29.55#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.17:54:29.55#ibcon#[27=AT02-05\r\n] 2006.257.17:54:29.55#ibcon#*before write, iclass 26, count 2 2006.257.17:54:29.55#ibcon#enter sib2, iclass 26, count 2 2006.257.17:54:29.55#ibcon#flushed, iclass 26, count 2 2006.257.17:54:29.55#ibcon#about to write, iclass 26, count 2 2006.257.17:54:29.55#ibcon#wrote, iclass 26, count 2 2006.257.17:54:29.55#ibcon#about to read 3, iclass 26, count 2 2006.257.17:54:29.58#ibcon#read 3, iclass 26, count 2 2006.257.17:54:29.58#ibcon#about to read 4, iclass 26, count 2 2006.257.17:54:29.58#ibcon#read 4, iclass 26, count 2 2006.257.17:54:29.58#ibcon#about to read 5, iclass 26, count 2 2006.257.17:54:29.58#ibcon#read 5, iclass 26, count 2 2006.257.17:54:29.58#ibcon#about to read 6, iclass 26, count 2 2006.257.17:54:29.58#ibcon#read 6, iclass 26, count 2 2006.257.17:54:29.58#ibcon#end of sib2, iclass 26, count 2 2006.257.17:54:29.58#ibcon#*after write, iclass 26, count 2 2006.257.17:54:29.58#ibcon#*before return 0, iclass 26, count 2 2006.257.17:54:29.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:29.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.17:54:29.58#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.17:54:29.58#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:29.58#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:29.70#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:29.70#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:29.70#ibcon#enter wrdev, iclass 26, count 0 2006.257.17:54:29.70#ibcon#first serial, iclass 26, count 0 2006.257.17:54:29.70#ibcon#enter sib2, iclass 26, count 0 2006.257.17:54:29.70#ibcon#flushed, iclass 26, count 0 2006.257.17:54:29.70#ibcon#about to write, iclass 26, count 0 2006.257.17:54:29.70#ibcon#wrote, iclass 26, count 0 2006.257.17:54:29.70#ibcon#about to read 3, iclass 26, count 0 2006.257.17:54:29.72#ibcon#read 3, iclass 26, count 0 2006.257.17:54:29.72#ibcon#about to read 4, iclass 26, count 0 2006.257.17:54:29.72#ibcon#read 4, iclass 26, count 0 2006.257.17:54:29.72#ibcon#about to read 5, iclass 26, count 0 2006.257.17:54:29.72#ibcon#read 5, iclass 26, count 0 2006.257.17:54:29.72#ibcon#about to read 6, iclass 26, count 0 2006.257.17:54:29.72#ibcon#read 6, iclass 26, count 0 2006.257.17:54:29.72#ibcon#end of sib2, iclass 26, count 0 2006.257.17:54:29.72#ibcon#*mode == 0, iclass 26, count 0 2006.257.17:54:29.72#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.17:54:29.72#ibcon#[27=USB\r\n] 2006.257.17:54:29.72#ibcon#*before write, iclass 26, count 0 2006.257.17:54:29.72#ibcon#enter sib2, iclass 26, count 0 2006.257.17:54:29.72#ibcon#flushed, iclass 26, count 0 2006.257.17:54:29.72#ibcon#about to write, iclass 26, count 0 2006.257.17:54:29.72#ibcon#wrote, iclass 26, count 0 2006.257.17:54:29.72#ibcon#about to read 3, iclass 26, count 0 2006.257.17:54:29.75#ibcon#read 3, iclass 26, count 0 2006.257.17:54:29.75#ibcon#about to read 4, iclass 26, count 0 2006.257.17:54:29.75#ibcon#read 4, iclass 26, count 0 2006.257.17:54:29.75#ibcon#about to read 5, iclass 26, count 0 2006.257.17:54:29.75#ibcon#read 5, iclass 26, count 0 2006.257.17:54:29.75#ibcon#about to read 6, iclass 26, count 0 2006.257.17:54:29.75#ibcon#read 6, iclass 26, count 0 2006.257.17:54:29.75#ibcon#end of sib2, iclass 26, count 0 2006.257.17:54:29.75#ibcon#*after write, iclass 26, count 0 2006.257.17:54:29.75#ibcon#*before return 0, iclass 26, count 0 2006.257.17:54:29.75#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:29.75#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.17:54:29.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.17:54:29.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.17:54:29.75$vck44/vblo=3,649.99 2006.257.17:54:29.75#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.17:54:29.75#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.17:54:29.75#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:29.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:29.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:29.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:29.75#ibcon#enter wrdev, iclass 28, count 0 2006.257.17:54:29.75#ibcon#first serial, iclass 28, count 0 2006.257.17:54:29.75#ibcon#enter sib2, iclass 28, count 0 2006.257.17:54:29.75#ibcon#flushed, iclass 28, count 0 2006.257.17:54:29.75#ibcon#about to write, iclass 28, count 0 2006.257.17:54:29.75#ibcon#wrote, iclass 28, count 0 2006.257.17:54:29.75#ibcon#about to read 3, iclass 28, count 0 2006.257.17:54:29.77#ibcon#read 3, iclass 28, count 0 2006.257.17:54:29.77#ibcon#about to read 4, iclass 28, count 0 2006.257.17:54:29.77#ibcon#read 4, iclass 28, count 0 2006.257.17:54:29.77#ibcon#about to read 5, iclass 28, count 0 2006.257.17:54:29.77#ibcon#read 5, iclass 28, count 0 2006.257.17:54:29.77#ibcon#about to read 6, iclass 28, count 0 2006.257.17:54:29.77#ibcon#read 6, iclass 28, count 0 2006.257.17:54:29.77#ibcon#end of sib2, iclass 28, count 0 2006.257.17:54:29.77#ibcon#*mode == 0, iclass 28, count 0 2006.257.17:54:29.77#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.17:54:29.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.17:54:29.77#ibcon#*before write, iclass 28, count 0 2006.257.17:54:29.77#ibcon#enter sib2, iclass 28, count 0 2006.257.17:54:29.77#ibcon#flushed, iclass 28, count 0 2006.257.17:54:29.77#ibcon#about to write, iclass 28, count 0 2006.257.17:54:29.77#ibcon#wrote, iclass 28, count 0 2006.257.17:54:29.77#ibcon#about to read 3, iclass 28, count 0 2006.257.17:54:29.81#ibcon#read 3, iclass 28, count 0 2006.257.17:54:29.81#ibcon#about to read 4, iclass 28, count 0 2006.257.17:54:29.81#ibcon#read 4, iclass 28, count 0 2006.257.17:54:29.81#ibcon#about to read 5, iclass 28, count 0 2006.257.17:54:29.81#ibcon#read 5, iclass 28, count 0 2006.257.17:54:29.81#ibcon#about to read 6, iclass 28, count 0 2006.257.17:54:29.81#ibcon#read 6, iclass 28, count 0 2006.257.17:54:29.81#ibcon#end of sib2, iclass 28, count 0 2006.257.17:54:29.81#ibcon#*after write, iclass 28, count 0 2006.257.17:54:29.81#ibcon#*before return 0, iclass 28, count 0 2006.257.17:54:29.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:29.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.17:54:29.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.17:54:29.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.17:54:29.81$vck44/vb=3,4 2006.257.17:54:29.81#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.17:54:29.81#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.17:54:29.81#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:29.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:29.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:29.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:29.87#ibcon#enter wrdev, iclass 30, count 2 2006.257.17:54:29.87#ibcon#first serial, iclass 30, count 2 2006.257.17:54:29.87#ibcon#enter sib2, iclass 30, count 2 2006.257.17:54:29.87#ibcon#flushed, iclass 30, count 2 2006.257.17:54:29.87#ibcon#about to write, iclass 30, count 2 2006.257.17:54:29.87#ibcon#wrote, iclass 30, count 2 2006.257.17:54:29.87#ibcon#about to read 3, iclass 30, count 2 2006.257.17:54:29.89#ibcon#read 3, iclass 30, count 2 2006.257.17:54:29.89#ibcon#about to read 4, iclass 30, count 2 2006.257.17:54:29.89#ibcon#read 4, iclass 30, count 2 2006.257.17:54:29.89#ibcon#about to read 5, iclass 30, count 2 2006.257.17:54:29.89#ibcon#read 5, iclass 30, count 2 2006.257.17:54:29.89#ibcon#about to read 6, iclass 30, count 2 2006.257.17:54:29.89#ibcon#read 6, iclass 30, count 2 2006.257.17:54:29.89#ibcon#end of sib2, iclass 30, count 2 2006.257.17:54:29.89#ibcon#*mode == 0, iclass 30, count 2 2006.257.17:54:29.89#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.17:54:29.89#ibcon#[27=AT03-04\r\n] 2006.257.17:54:29.89#ibcon#*before write, iclass 30, count 2 2006.257.17:54:29.89#ibcon#enter sib2, iclass 30, count 2 2006.257.17:54:29.89#ibcon#flushed, iclass 30, count 2 2006.257.17:54:29.89#ibcon#about to write, iclass 30, count 2 2006.257.17:54:29.89#ibcon#wrote, iclass 30, count 2 2006.257.17:54:29.89#ibcon#about to read 3, iclass 30, count 2 2006.257.17:54:29.92#ibcon#read 3, iclass 30, count 2 2006.257.17:54:29.92#ibcon#about to read 4, iclass 30, count 2 2006.257.17:54:29.92#ibcon#read 4, iclass 30, count 2 2006.257.17:54:29.92#ibcon#about to read 5, iclass 30, count 2 2006.257.17:54:29.92#ibcon#read 5, iclass 30, count 2 2006.257.17:54:29.92#ibcon#about to read 6, iclass 30, count 2 2006.257.17:54:29.92#ibcon#read 6, iclass 30, count 2 2006.257.17:54:29.92#ibcon#end of sib2, iclass 30, count 2 2006.257.17:54:29.92#ibcon#*after write, iclass 30, count 2 2006.257.17:54:29.92#ibcon#*before return 0, iclass 30, count 2 2006.257.17:54:29.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:29.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.17:54:29.92#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.17:54:29.92#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:29.92#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:30.04#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:30.04#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:30.04#ibcon#enter wrdev, iclass 30, count 0 2006.257.17:54:30.04#ibcon#first serial, iclass 30, count 0 2006.257.17:54:30.04#ibcon#enter sib2, iclass 30, count 0 2006.257.17:54:30.04#ibcon#flushed, iclass 30, count 0 2006.257.17:54:30.04#ibcon#about to write, iclass 30, count 0 2006.257.17:54:30.04#ibcon#wrote, iclass 30, count 0 2006.257.17:54:30.04#ibcon#about to read 3, iclass 30, count 0 2006.257.17:54:30.06#ibcon#read 3, iclass 30, count 0 2006.257.17:54:30.06#ibcon#about to read 4, iclass 30, count 0 2006.257.17:54:30.06#ibcon#read 4, iclass 30, count 0 2006.257.17:54:30.06#ibcon#about to read 5, iclass 30, count 0 2006.257.17:54:30.06#ibcon#read 5, iclass 30, count 0 2006.257.17:54:30.06#ibcon#about to read 6, iclass 30, count 0 2006.257.17:54:30.06#ibcon#read 6, iclass 30, count 0 2006.257.17:54:30.06#ibcon#end of sib2, iclass 30, count 0 2006.257.17:54:30.06#ibcon#*mode == 0, iclass 30, count 0 2006.257.17:54:30.06#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.17:54:30.06#ibcon#[27=USB\r\n] 2006.257.17:54:30.06#ibcon#*before write, iclass 30, count 0 2006.257.17:54:30.06#ibcon#enter sib2, iclass 30, count 0 2006.257.17:54:30.06#ibcon#flushed, iclass 30, count 0 2006.257.17:54:30.06#ibcon#about to write, iclass 30, count 0 2006.257.17:54:30.06#ibcon#wrote, iclass 30, count 0 2006.257.17:54:30.06#ibcon#about to read 3, iclass 30, count 0 2006.257.17:54:30.09#ibcon#read 3, iclass 30, count 0 2006.257.17:54:30.09#ibcon#about to read 4, iclass 30, count 0 2006.257.17:54:30.09#ibcon#read 4, iclass 30, count 0 2006.257.17:54:30.09#ibcon#about to read 5, iclass 30, count 0 2006.257.17:54:30.09#ibcon#read 5, iclass 30, count 0 2006.257.17:54:30.09#ibcon#about to read 6, iclass 30, count 0 2006.257.17:54:30.09#ibcon#read 6, iclass 30, count 0 2006.257.17:54:30.09#ibcon#end of sib2, iclass 30, count 0 2006.257.17:54:30.09#ibcon#*after write, iclass 30, count 0 2006.257.17:54:30.09#ibcon#*before return 0, iclass 30, count 0 2006.257.17:54:30.09#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:30.09#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.17:54:30.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.17:54:30.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.17:54:30.09$vck44/vblo=4,679.99 2006.257.17:54:30.09#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.17:54:30.09#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.17:54:30.09#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:30.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:30.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:30.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:30.09#ibcon#enter wrdev, iclass 32, count 0 2006.257.17:54:30.09#ibcon#first serial, iclass 32, count 0 2006.257.17:54:30.09#ibcon#enter sib2, iclass 32, count 0 2006.257.17:54:30.09#ibcon#flushed, iclass 32, count 0 2006.257.17:54:30.09#ibcon#about to write, iclass 32, count 0 2006.257.17:54:30.09#ibcon#wrote, iclass 32, count 0 2006.257.17:54:30.09#ibcon#about to read 3, iclass 32, count 0 2006.257.17:54:30.11#ibcon#read 3, iclass 32, count 0 2006.257.17:54:30.11#ibcon#about to read 4, iclass 32, count 0 2006.257.17:54:30.11#ibcon#read 4, iclass 32, count 0 2006.257.17:54:30.11#ibcon#about to read 5, iclass 32, count 0 2006.257.17:54:30.11#ibcon#read 5, iclass 32, count 0 2006.257.17:54:30.11#ibcon#about to read 6, iclass 32, count 0 2006.257.17:54:30.11#ibcon#read 6, iclass 32, count 0 2006.257.17:54:30.11#ibcon#end of sib2, iclass 32, count 0 2006.257.17:54:30.11#ibcon#*mode == 0, iclass 32, count 0 2006.257.17:54:30.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.17:54:30.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.17:54:30.11#ibcon#*before write, iclass 32, count 0 2006.257.17:54:30.11#ibcon#enter sib2, iclass 32, count 0 2006.257.17:54:30.11#ibcon#flushed, iclass 32, count 0 2006.257.17:54:30.11#ibcon#about to write, iclass 32, count 0 2006.257.17:54:30.11#ibcon#wrote, iclass 32, count 0 2006.257.17:54:30.11#ibcon#about to read 3, iclass 32, count 0 2006.257.17:54:30.15#ibcon#read 3, iclass 32, count 0 2006.257.17:54:30.15#ibcon#about to read 4, iclass 32, count 0 2006.257.17:54:30.15#ibcon#read 4, iclass 32, count 0 2006.257.17:54:30.15#ibcon#about to read 5, iclass 32, count 0 2006.257.17:54:30.15#ibcon#read 5, iclass 32, count 0 2006.257.17:54:30.15#ibcon#about to read 6, iclass 32, count 0 2006.257.17:54:30.15#ibcon#read 6, iclass 32, count 0 2006.257.17:54:30.15#ibcon#end of sib2, iclass 32, count 0 2006.257.17:54:30.15#ibcon#*after write, iclass 32, count 0 2006.257.17:54:30.15#ibcon#*before return 0, iclass 32, count 0 2006.257.17:54:30.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:30.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.17:54:30.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.17:54:30.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.17:54:30.15$vck44/vb=4,5 2006.257.17:54:30.15#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.17:54:30.15#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.17:54:30.15#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:30.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:30.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:30.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:30.21#ibcon#enter wrdev, iclass 34, count 2 2006.257.17:54:30.21#ibcon#first serial, iclass 34, count 2 2006.257.17:54:30.21#ibcon#enter sib2, iclass 34, count 2 2006.257.17:54:30.21#ibcon#flushed, iclass 34, count 2 2006.257.17:54:30.21#ibcon#about to write, iclass 34, count 2 2006.257.17:54:30.21#ibcon#wrote, iclass 34, count 2 2006.257.17:54:30.21#ibcon#about to read 3, iclass 34, count 2 2006.257.17:54:30.23#ibcon#read 3, iclass 34, count 2 2006.257.17:54:30.23#ibcon#about to read 4, iclass 34, count 2 2006.257.17:54:30.23#ibcon#read 4, iclass 34, count 2 2006.257.17:54:30.23#ibcon#about to read 5, iclass 34, count 2 2006.257.17:54:30.23#ibcon#read 5, iclass 34, count 2 2006.257.17:54:30.23#ibcon#about to read 6, iclass 34, count 2 2006.257.17:54:30.23#ibcon#read 6, iclass 34, count 2 2006.257.17:54:30.23#ibcon#end of sib2, iclass 34, count 2 2006.257.17:54:30.23#ibcon#*mode == 0, iclass 34, count 2 2006.257.17:54:30.23#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.17:54:30.23#ibcon#[27=AT04-05\r\n] 2006.257.17:54:30.23#ibcon#*before write, iclass 34, count 2 2006.257.17:54:30.23#ibcon#enter sib2, iclass 34, count 2 2006.257.17:54:30.23#ibcon#flushed, iclass 34, count 2 2006.257.17:54:30.23#ibcon#about to write, iclass 34, count 2 2006.257.17:54:30.23#ibcon#wrote, iclass 34, count 2 2006.257.17:54:30.23#ibcon#about to read 3, iclass 34, count 2 2006.257.17:54:30.26#ibcon#read 3, iclass 34, count 2 2006.257.17:54:30.26#ibcon#about to read 4, iclass 34, count 2 2006.257.17:54:30.26#ibcon#read 4, iclass 34, count 2 2006.257.17:54:30.26#ibcon#about to read 5, iclass 34, count 2 2006.257.17:54:30.26#ibcon#read 5, iclass 34, count 2 2006.257.17:54:30.26#ibcon#about to read 6, iclass 34, count 2 2006.257.17:54:30.26#ibcon#read 6, iclass 34, count 2 2006.257.17:54:30.26#ibcon#end of sib2, iclass 34, count 2 2006.257.17:54:30.26#ibcon#*after write, iclass 34, count 2 2006.257.17:54:30.26#ibcon#*before return 0, iclass 34, count 2 2006.257.17:54:30.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:30.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.17:54:30.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.17:54:30.26#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:30.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:30.38#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:30.38#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:30.38#ibcon#enter wrdev, iclass 34, count 0 2006.257.17:54:30.38#ibcon#first serial, iclass 34, count 0 2006.257.17:54:30.38#ibcon#enter sib2, iclass 34, count 0 2006.257.17:54:30.38#ibcon#flushed, iclass 34, count 0 2006.257.17:54:30.38#ibcon#about to write, iclass 34, count 0 2006.257.17:54:30.38#ibcon#wrote, iclass 34, count 0 2006.257.17:54:30.38#ibcon#about to read 3, iclass 34, count 0 2006.257.17:54:30.40#ibcon#read 3, iclass 34, count 0 2006.257.17:54:30.40#ibcon#about to read 4, iclass 34, count 0 2006.257.17:54:30.40#ibcon#read 4, iclass 34, count 0 2006.257.17:54:30.40#ibcon#about to read 5, iclass 34, count 0 2006.257.17:54:30.40#ibcon#read 5, iclass 34, count 0 2006.257.17:54:30.40#ibcon#about to read 6, iclass 34, count 0 2006.257.17:54:30.40#ibcon#read 6, iclass 34, count 0 2006.257.17:54:30.40#ibcon#end of sib2, iclass 34, count 0 2006.257.17:54:30.40#ibcon#*mode == 0, iclass 34, count 0 2006.257.17:54:30.40#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.17:54:30.40#ibcon#[27=USB\r\n] 2006.257.17:54:30.40#ibcon#*before write, iclass 34, count 0 2006.257.17:54:30.40#ibcon#enter sib2, iclass 34, count 0 2006.257.17:54:30.40#ibcon#flushed, iclass 34, count 0 2006.257.17:54:30.40#ibcon#about to write, iclass 34, count 0 2006.257.17:54:30.40#ibcon#wrote, iclass 34, count 0 2006.257.17:54:30.40#ibcon#about to read 3, iclass 34, count 0 2006.257.17:54:30.43#ibcon#read 3, iclass 34, count 0 2006.257.17:54:30.43#ibcon#about to read 4, iclass 34, count 0 2006.257.17:54:30.43#ibcon#read 4, iclass 34, count 0 2006.257.17:54:30.43#ibcon#about to read 5, iclass 34, count 0 2006.257.17:54:30.43#ibcon#read 5, iclass 34, count 0 2006.257.17:54:30.43#ibcon#about to read 6, iclass 34, count 0 2006.257.17:54:30.43#ibcon#read 6, iclass 34, count 0 2006.257.17:54:30.43#ibcon#end of sib2, iclass 34, count 0 2006.257.17:54:30.43#ibcon#*after write, iclass 34, count 0 2006.257.17:54:30.43#ibcon#*before return 0, iclass 34, count 0 2006.257.17:54:30.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:30.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.17:54:30.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.17:54:30.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.17:54:30.43$vck44/vblo=5,709.99 2006.257.17:54:30.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.17:54:30.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.17:54:30.43#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:30.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:30.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:30.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:30.43#ibcon#enter wrdev, iclass 36, count 0 2006.257.17:54:30.43#ibcon#first serial, iclass 36, count 0 2006.257.17:54:30.43#ibcon#enter sib2, iclass 36, count 0 2006.257.17:54:30.43#ibcon#flushed, iclass 36, count 0 2006.257.17:54:30.43#ibcon#about to write, iclass 36, count 0 2006.257.17:54:30.43#ibcon#wrote, iclass 36, count 0 2006.257.17:54:30.43#ibcon#about to read 3, iclass 36, count 0 2006.257.17:54:30.45#ibcon#read 3, iclass 36, count 0 2006.257.17:54:30.45#ibcon#about to read 4, iclass 36, count 0 2006.257.17:54:30.45#ibcon#read 4, iclass 36, count 0 2006.257.17:54:30.45#ibcon#about to read 5, iclass 36, count 0 2006.257.17:54:30.45#ibcon#read 5, iclass 36, count 0 2006.257.17:54:30.45#ibcon#about to read 6, iclass 36, count 0 2006.257.17:54:30.45#ibcon#read 6, iclass 36, count 0 2006.257.17:54:30.45#ibcon#end of sib2, iclass 36, count 0 2006.257.17:54:30.45#ibcon#*mode == 0, iclass 36, count 0 2006.257.17:54:30.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.17:54:30.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.17:54:30.45#ibcon#*before write, iclass 36, count 0 2006.257.17:54:30.45#ibcon#enter sib2, iclass 36, count 0 2006.257.17:54:30.45#ibcon#flushed, iclass 36, count 0 2006.257.17:54:30.45#ibcon#about to write, iclass 36, count 0 2006.257.17:54:30.45#ibcon#wrote, iclass 36, count 0 2006.257.17:54:30.45#ibcon#about to read 3, iclass 36, count 0 2006.257.17:54:30.49#ibcon#read 3, iclass 36, count 0 2006.257.17:54:30.49#ibcon#about to read 4, iclass 36, count 0 2006.257.17:54:30.49#ibcon#read 4, iclass 36, count 0 2006.257.17:54:30.49#ibcon#about to read 5, iclass 36, count 0 2006.257.17:54:30.49#ibcon#read 5, iclass 36, count 0 2006.257.17:54:30.49#ibcon#about to read 6, iclass 36, count 0 2006.257.17:54:30.49#ibcon#read 6, iclass 36, count 0 2006.257.17:54:30.49#ibcon#end of sib2, iclass 36, count 0 2006.257.17:54:30.49#ibcon#*after write, iclass 36, count 0 2006.257.17:54:30.49#ibcon#*before return 0, iclass 36, count 0 2006.257.17:54:30.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:30.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.17:54:30.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.17:54:30.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.17:54:30.49$vck44/vb=5,4 2006.257.17:54:30.49#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.17:54:30.49#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.17:54:30.49#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:30.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:30.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:30.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:30.55#ibcon#enter wrdev, iclass 38, count 2 2006.257.17:54:30.55#ibcon#first serial, iclass 38, count 2 2006.257.17:54:30.55#ibcon#enter sib2, iclass 38, count 2 2006.257.17:54:30.55#ibcon#flushed, iclass 38, count 2 2006.257.17:54:30.55#ibcon#about to write, iclass 38, count 2 2006.257.17:54:30.55#ibcon#wrote, iclass 38, count 2 2006.257.17:54:30.55#ibcon#about to read 3, iclass 38, count 2 2006.257.17:54:30.57#ibcon#read 3, iclass 38, count 2 2006.257.17:54:30.57#ibcon#about to read 4, iclass 38, count 2 2006.257.17:54:30.57#ibcon#read 4, iclass 38, count 2 2006.257.17:54:30.57#ibcon#about to read 5, iclass 38, count 2 2006.257.17:54:30.57#ibcon#read 5, iclass 38, count 2 2006.257.17:54:30.57#ibcon#about to read 6, iclass 38, count 2 2006.257.17:54:30.57#ibcon#read 6, iclass 38, count 2 2006.257.17:54:30.57#ibcon#end of sib2, iclass 38, count 2 2006.257.17:54:30.57#ibcon#*mode == 0, iclass 38, count 2 2006.257.17:54:30.57#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.17:54:30.57#ibcon#[27=AT05-04\r\n] 2006.257.17:54:30.57#ibcon#*before write, iclass 38, count 2 2006.257.17:54:30.57#ibcon#enter sib2, iclass 38, count 2 2006.257.17:54:30.57#ibcon#flushed, iclass 38, count 2 2006.257.17:54:30.57#ibcon#about to write, iclass 38, count 2 2006.257.17:54:30.57#ibcon#wrote, iclass 38, count 2 2006.257.17:54:30.57#ibcon#about to read 3, iclass 38, count 2 2006.257.17:54:30.60#ibcon#read 3, iclass 38, count 2 2006.257.17:54:30.60#ibcon#about to read 4, iclass 38, count 2 2006.257.17:54:30.60#ibcon#read 4, iclass 38, count 2 2006.257.17:54:30.60#ibcon#about to read 5, iclass 38, count 2 2006.257.17:54:30.60#ibcon#read 5, iclass 38, count 2 2006.257.17:54:30.60#ibcon#about to read 6, iclass 38, count 2 2006.257.17:54:30.60#ibcon#read 6, iclass 38, count 2 2006.257.17:54:30.60#ibcon#end of sib2, iclass 38, count 2 2006.257.17:54:30.60#ibcon#*after write, iclass 38, count 2 2006.257.17:54:30.60#ibcon#*before return 0, iclass 38, count 2 2006.257.17:54:30.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:30.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.17:54:30.60#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.17:54:30.60#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:30.60#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:30.72#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:30.72#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:30.72#ibcon#enter wrdev, iclass 38, count 0 2006.257.17:54:30.72#ibcon#first serial, iclass 38, count 0 2006.257.17:54:30.72#ibcon#enter sib2, iclass 38, count 0 2006.257.17:54:30.72#ibcon#flushed, iclass 38, count 0 2006.257.17:54:30.72#ibcon#about to write, iclass 38, count 0 2006.257.17:54:30.72#ibcon#wrote, iclass 38, count 0 2006.257.17:54:30.72#ibcon#about to read 3, iclass 38, count 0 2006.257.17:54:30.74#ibcon#read 3, iclass 38, count 0 2006.257.17:54:30.74#ibcon#about to read 4, iclass 38, count 0 2006.257.17:54:30.74#ibcon#read 4, iclass 38, count 0 2006.257.17:54:30.74#ibcon#about to read 5, iclass 38, count 0 2006.257.17:54:30.74#ibcon#read 5, iclass 38, count 0 2006.257.17:54:30.74#ibcon#about to read 6, iclass 38, count 0 2006.257.17:54:30.74#ibcon#read 6, iclass 38, count 0 2006.257.17:54:30.74#ibcon#end of sib2, iclass 38, count 0 2006.257.17:54:30.74#ibcon#*mode == 0, iclass 38, count 0 2006.257.17:54:30.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.17:54:30.74#ibcon#[27=USB\r\n] 2006.257.17:54:30.74#ibcon#*before write, iclass 38, count 0 2006.257.17:54:30.74#ibcon#enter sib2, iclass 38, count 0 2006.257.17:54:30.74#ibcon#flushed, iclass 38, count 0 2006.257.17:54:30.74#ibcon#about to write, iclass 38, count 0 2006.257.17:54:30.74#ibcon#wrote, iclass 38, count 0 2006.257.17:54:30.74#ibcon#about to read 3, iclass 38, count 0 2006.257.17:54:30.77#ibcon#read 3, iclass 38, count 0 2006.257.17:54:30.77#ibcon#about to read 4, iclass 38, count 0 2006.257.17:54:30.77#ibcon#read 4, iclass 38, count 0 2006.257.17:54:30.77#ibcon#about to read 5, iclass 38, count 0 2006.257.17:54:30.77#ibcon#read 5, iclass 38, count 0 2006.257.17:54:30.77#ibcon#about to read 6, iclass 38, count 0 2006.257.17:54:30.77#ibcon#read 6, iclass 38, count 0 2006.257.17:54:30.77#ibcon#end of sib2, iclass 38, count 0 2006.257.17:54:30.77#ibcon#*after write, iclass 38, count 0 2006.257.17:54:30.77#ibcon#*before return 0, iclass 38, count 0 2006.257.17:54:30.77#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:30.77#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.17:54:30.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.17:54:30.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.17:54:30.77$vck44/vblo=6,719.99 2006.257.17:54:30.77#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.17:54:30.77#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.17:54:30.77#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:30.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:30.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:30.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:30.77#ibcon#enter wrdev, iclass 40, count 0 2006.257.17:54:30.77#ibcon#first serial, iclass 40, count 0 2006.257.17:54:30.77#ibcon#enter sib2, iclass 40, count 0 2006.257.17:54:30.77#ibcon#flushed, iclass 40, count 0 2006.257.17:54:30.77#ibcon#about to write, iclass 40, count 0 2006.257.17:54:30.77#ibcon#wrote, iclass 40, count 0 2006.257.17:54:30.77#ibcon#about to read 3, iclass 40, count 0 2006.257.17:54:30.79#ibcon#read 3, iclass 40, count 0 2006.257.17:54:30.79#ibcon#about to read 4, iclass 40, count 0 2006.257.17:54:30.79#ibcon#read 4, iclass 40, count 0 2006.257.17:54:30.79#ibcon#about to read 5, iclass 40, count 0 2006.257.17:54:30.79#ibcon#read 5, iclass 40, count 0 2006.257.17:54:30.79#ibcon#about to read 6, iclass 40, count 0 2006.257.17:54:30.79#ibcon#read 6, iclass 40, count 0 2006.257.17:54:30.79#ibcon#end of sib2, iclass 40, count 0 2006.257.17:54:30.79#ibcon#*mode == 0, iclass 40, count 0 2006.257.17:54:30.79#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.17:54:30.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.17:54:30.79#ibcon#*before write, iclass 40, count 0 2006.257.17:54:30.79#ibcon#enter sib2, iclass 40, count 0 2006.257.17:54:30.79#ibcon#flushed, iclass 40, count 0 2006.257.17:54:30.79#ibcon#about to write, iclass 40, count 0 2006.257.17:54:30.79#ibcon#wrote, iclass 40, count 0 2006.257.17:54:30.79#ibcon#about to read 3, iclass 40, count 0 2006.257.17:54:30.83#ibcon#read 3, iclass 40, count 0 2006.257.17:54:30.83#ibcon#about to read 4, iclass 40, count 0 2006.257.17:54:30.83#ibcon#read 4, iclass 40, count 0 2006.257.17:54:30.83#ibcon#about to read 5, iclass 40, count 0 2006.257.17:54:30.83#ibcon#read 5, iclass 40, count 0 2006.257.17:54:30.83#ibcon#about to read 6, iclass 40, count 0 2006.257.17:54:30.83#ibcon#read 6, iclass 40, count 0 2006.257.17:54:30.83#ibcon#end of sib2, iclass 40, count 0 2006.257.17:54:30.83#ibcon#*after write, iclass 40, count 0 2006.257.17:54:30.83#ibcon#*before return 0, iclass 40, count 0 2006.257.17:54:30.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:30.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.17:54:30.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.17:54:30.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.17:54:30.83$vck44/vb=6,4 2006.257.17:54:30.83#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.17:54:30.83#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.17:54:30.83#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:30.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:30.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:30.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:30.89#ibcon#enter wrdev, iclass 4, count 2 2006.257.17:54:30.89#ibcon#first serial, iclass 4, count 2 2006.257.17:54:30.89#ibcon#enter sib2, iclass 4, count 2 2006.257.17:54:30.89#ibcon#flushed, iclass 4, count 2 2006.257.17:54:30.89#ibcon#about to write, iclass 4, count 2 2006.257.17:54:30.89#ibcon#wrote, iclass 4, count 2 2006.257.17:54:30.89#ibcon#about to read 3, iclass 4, count 2 2006.257.17:54:30.91#ibcon#read 3, iclass 4, count 2 2006.257.17:54:30.91#ibcon#about to read 4, iclass 4, count 2 2006.257.17:54:30.91#ibcon#read 4, iclass 4, count 2 2006.257.17:54:30.91#ibcon#about to read 5, iclass 4, count 2 2006.257.17:54:30.91#ibcon#read 5, iclass 4, count 2 2006.257.17:54:30.91#ibcon#about to read 6, iclass 4, count 2 2006.257.17:54:30.91#ibcon#read 6, iclass 4, count 2 2006.257.17:54:30.91#ibcon#end of sib2, iclass 4, count 2 2006.257.17:54:30.91#ibcon#*mode == 0, iclass 4, count 2 2006.257.17:54:30.91#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.17:54:30.91#ibcon#[27=AT06-04\r\n] 2006.257.17:54:30.91#ibcon#*before write, iclass 4, count 2 2006.257.17:54:30.91#ibcon#enter sib2, iclass 4, count 2 2006.257.17:54:30.91#ibcon#flushed, iclass 4, count 2 2006.257.17:54:30.91#ibcon#about to write, iclass 4, count 2 2006.257.17:54:30.91#ibcon#wrote, iclass 4, count 2 2006.257.17:54:30.91#ibcon#about to read 3, iclass 4, count 2 2006.257.17:54:30.94#ibcon#read 3, iclass 4, count 2 2006.257.17:54:30.94#ibcon#about to read 4, iclass 4, count 2 2006.257.17:54:30.94#ibcon#read 4, iclass 4, count 2 2006.257.17:54:30.94#ibcon#about to read 5, iclass 4, count 2 2006.257.17:54:30.94#ibcon#read 5, iclass 4, count 2 2006.257.17:54:30.94#ibcon#about to read 6, iclass 4, count 2 2006.257.17:54:30.94#ibcon#read 6, iclass 4, count 2 2006.257.17:54:30.94#ibcon#end of sib2, iclass 4, count 2 2006.257.17:54:30.94#ibcon#*after write, iclass 4, count 2 2006.257.17:54:30.94#ibcon#*before return 0, iclass 4, count 2 2006.257.17:54:30.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:30.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.17:54:30.94#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.17:54:30.94#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:30.94#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:31.06#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:31.06#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:31.06#ibcon#enter wrdev, iclass 4, count 0 2006.257.17:54:31.06#ibcon#first serial, iclass 4, count 0 2006.257.17:54:31.06#ibcon#enter sib2, iclass 4, count 0 2006.257.17:54:31.06#ibcon#flushed, iclass 4, count 0 2006.257.17:54:31.06#ibcon#about to write, iclass 4, count 0 2006.257.17:54:31.06#ibcon#wrote, iclass 4, count 0 2006.257.17:54:31.06#ibcon#about to read 3, iclass 4, count 0 2006.257.17:54:31.08#ibcon#read 3, iclass 4, count 0 2006.257.17:54:31.08#ibcon#about to read 4, iclass 4, count 0 2006.257.17:54:31.08#ibcon#read 4, iclass 4, count 0 2006.257.17:54:31.08#ibcon#about to read 5, iclass 4, count 0 2006.257.17:54:31.08#ibcon#read 5, iclass 4, count 0 2006.257.17:54:31.08#ibcon#about to read 6, iclass 4, count 0 2006.257.17:54:31.08#ibcon#read 6, iclass 4, count 0 2006.257.17:54:31.08#ibcon#end of sib2, iclass 4, count 0 2006.257.17:54:31.08#ibcon#*mode == 0, iclass 4, count 0 2006.257.17:54:31.08#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.17:54:31.08#ibcon#[27=USB\r\n] 2006.257.17:54:31.08#ibcon#*before write, iclass 4, count 0 2006.257.17:54:31.08#ibcon#enter sib2, iclass 4, count 0 2006.257.17:54:31.08#ibcon#flushed, iclass 4, count 0 2006.257.17:54:31.08#ibcon#about to write, iclass 4, count 0 2006.257.17:54:31.08#ibcon#wrote, iclass 4, count 0 2006.257.17:54:31.08#ibcon#about to read 3, iclass 4, count 0 2006.257.17:54:31.11#ibcon#read 3, iclass 4, count 0 2006.257.17:54:31.11#ibcon#about to read 4, iclass 4, count 0 2006.257.17:54:31.11#ibcon#read 4, iclass 4, count 0 2006.257.17:54:31.11#ibcon#about to read 5, iclass 4, count 0 2006.257.17:54:31.11#ibcon#read 5, iclass 4, count 0 2006.257.17:54:31.11#ibcon#about to read 6, iclass 4, count 0 2006.257.17:54:31.11#ibcon#read 6, iclass 4, count 0 2006.257.17:54:31.11#ibcon#end of sib2, iclass 4, count 0 2006.257.17:54:31.11#ibcon#*after write, iclass 4, count 0 2006.257.17:54:31.11#ibcon#*before return 0, iclass 4, count 0 2006.257.17:54:31.11#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:31.11#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.17:54:31.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.17:54:31.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.17:54:31.11$vck44/vblo=7,734.99 2006.257.17:54:31.11#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.17:54:31.11#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.17:54:31.11#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:31.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:31.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:31.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:31.11#ibcon#enter wrdev, iclass 6, count 0 2006.257.17:54:31.11#ibcon#first serial, iclass 6, count 0 2006.257.17:54:31.11#ibcon#enter sib2, iclass 6, count 0 2006.257.17:54:31.11#ibcon#flushed, iclass 6, count 0 2006.257.17:54:31.11#ibcon#about to write, iclass 6, count 0 2006.257.17:54:31.11#ibcon#wrote, iclass 6, count 0 2006.257.17:54:31.11#ibcon#about to read 3, iclass 6, count 0 2006.257.17:54:31.13#ibcon#read 3, iclass 6, count 0 2006.257.17:54:31.13#ibcon#about to read 4, iclass 6, count 0 2006.257.17:54:31.13#ibcon#read 4, iclass 6, count 0 2006.257.17:54:31.13#ibcon#about to read 5, iclass 6, count 0 2006.257.17:54:31.13#ibcon#read 5, iclass 6, count 0 2006.257.17:54:31.13#ibcon#about to read 6, iclass 6, count 0 2006.257.17:54:31.13#ibcon#read 6, iclass 6, count 0 2006.257.17:54:31.13#ibcon#end of sib2, iclass 6, count 0 2006.257.17:54:31.13#ibcon#*mode == 0, iclass 6, count 0 2006.257.17:54:31.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.17:54:31.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.17:54:31.13#ibcon#*before write, iclass 6, count 0 2006.257.17:54:31.13#ibcon#enter sib2, iclass 6, count 0 2006.257.17:54:31.13#ibcon#flushed, iclass 6, count 0 2006.257.17:54:31.13#ibcon#about to write, iclass 6, count 0 2006.257.17:54:31.13#ibcon#wrote, iclass 6, count 0 2006.257.17:54:31.13#ibcon#about to read 3, iclass 6, count 0 2006.257.17:54:31.17#ibcon#read 3, iclass 6, count 0 2006.257.17:54:31.17#ibcon#about to read 4, iclass 6, count 0 2006.257.17:54:31.17#ibcon#read 4, iclass 6, count 0 2006.257.17:54:31.17#ibcon#about to read 5, iclass 6, count 0 2006.257.17:54:31.17#ibcon#read 5, iclass 6, count 0 2006.257.17:54:31.17#ibcon#about to read 6, iclass 6, count 0 2006.257.17:54:31.17#ibcon#read 6, iclass 6, count 0 2006.257.17:54:31.17#ibcon#end of sib2, iclass 6, count 0 2006.257.17:54:31.17#ibcon#*after write, iclass 6, count 0 2006.257.17:54:31.17#ibcon#*before return 0, iclass 6, count 0 2006.257.17:54:31.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:31.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.17:54:31.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.17:54:31.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.17:54:31.17$vck44/vb=7,4 2006.257.17:54:31.17#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.17:54:31.17#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.17:54:31.17#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:31.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:31.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:31.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:31.23#ibcon#enter wrdev, iclass 10, count 2 2006.257.17:54:31.23#ibcon#first serial, iclass 10, count 2 2006.257.17:54:31.23#ibcon#enter sib2, iclass 10, count 2 2006.257.17:54:31.23#ibcon#flushed, iclass 10, count 2 2006.257.17:54:31.23#ibcon#about to write, iclass 10, count 2 2006.257.17:54:31.23#ibcon#wrote, iclass 10, count 2 2006.257.17:54:31.23#ibcon#about to read 3, iclass 10, count 2 2006.257.17:54:31.25#ibcon#read 3, iclass 10, count 2 2006.257.17:54:31.25#ibcon#about to read 4, iclass 10, count 2 2006.257.17:54:31.25#ibcon#read 4, iclass 10, count 2 2006.257.17:54:31.25#ibcon#about to read 5, iclass 10, count 2 2006.257.17:54:31.25#ibcon#read 5, iclass 10, count 2 2006.257.17:54:31.25#ibcon#about to read 6, iclass 10, count 2 2006.257.17:54:31.25#ibcon#read 6, iclass 10, count 2 2006.257.17:54:31.25#ibcon#end of sib2, iclass 10, count 2 2006.257.17:54:31.25#ibcon#*mode == 0, iclass 10, count 2 2006.257.17:54:31.25#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.17:54:31.25#ibcon#[27=AT07-04\r\n] 2006.257.17:54:31.25#ibcon#*before write, iclass 10, count 2 2006.257.17:54:31.25#ibcon#enter sib2, iclass 10, count 2 2006.257.17:54:31.25#ibcon#flushed, iclass 10, count 2 2006.257.17:54:31.25#ibcon#about to write, iclass 10, count 2 2006.257.17:54:31.25#ibcon#wrote, iclass 10, count 2 2006.257.17:54:31.25#ibcon#about to read 3, iclass 10, count 2 2006.257.17:54:31.28#ibcon#read 3, iclass 10, count 2 2006.257.17:54:31.28#ibcon#about to read 4, iclass 10, count 2 2006.257.17:54:31.28#ibcon#read 4, iclass 10, count 2 2006.257.17:54:31.28#ibcon#about to read 5, iclass 10, count 2 2006.257.17:54:31.28#ibcon#read 5, iclass 10, count 2 2006.257.17:54:31.28#ibcon#about to read 6, iclass 10, count 2 2006.257.17:54:31.28#ibcon#read 6, iclass 10, count 2 2006.257.17:54:31.28#ibcon#end of sib2, iclass 10, count 2 2006.257.17:54:31.28#ibcon#*after write, iclass 10, count 2 2006.257.17:54:31.28#ibcon#*before return 0, iclass 10, count 2 2006.257.17:54:31.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:31.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.17:54:31.28#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.17:54:31.28#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:31.28#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:31.40#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:31.40#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:31.40#ibcon#enter wrdev, iclass 10, count 0 2006.257.17:54:31.40#ibcon#first serial, iclass 10, count 0 2006.257.17:54:31.40#ibcon#enter sib2, iclass 10, count 0 2006.257.17:54:31.40#ibcon#flushed, iclass 10, count 0 2006.257.17:54:31.40#ibcon#about to write, iclass 10, count 0 2006.257.17:54:31.40#ibcon#wrote, iclass 10, count 0 2006.257.17:54:31.40#ibcon#about to read 3, iclass 10, count 0 2006.257.17:54:31.42#ibcon#read 3, iclass 10, count 0 2006.257.17:54:31.42#ibcon#about to read 4, iclass 10, count 0 2006.257.17:54:31.42#ibcon#read 4, iclass 10, count 0 2006.257.17:54:31.42#ibcon#about to read 5, iclass 10, count 0 2006.257.17:54:31.42#ibcon#read 5, iclass 10, count 0 2006.257.17:54:31.42#ibcon#about to read 6, iclass 10, count 0 2006.257.17:54:31.42#ibcon#read 6, iclass 10, count 0 2006.257.17:54:31.42#ibcon#end of sib2, iclass 10, count 0 2006.257.17:54:31.42#ibcon#*mode == 0, iclass 10, count 0 2006.257.17:54:31.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.17:54:31.42#ibcon#[27=USB\r\n] 2006.257.17:54:31.42#ibcon#*before write, iclass 10, count 0 2006.257.17:54:31.42#ibcon#enter sib2, iclass 10, count 0 2006.257.17:54:31.42#ibcon#flushed, iclass 10, count 0 2006.257.17:54:31.42#ibcon#about to write, iclass 10, count 0 2006.257.17:54:31.42#ibcon#wrote, iclass 10, count 0 2006.257.17:54:31.42#ibcon#about to read 3, iclass 10, count 0 2006.257.17:54:31.45#ibcon#read 3, iclass 10, count 0 2006.257.17:54:31.45#ibcon#about to read 4, iclass 10, count 0 2006.257.17:54:31.45#ibcon#read 4, iclass 10, count 0 2006.257.17:54:31.45#ibcon#about to read 5, iclass 10, count 0 2006.257.17:54:31.45#ibcon#read 5, iclass 10, count 0 2006.257.17:54:31.45#ibcon#about to read 6, iclass 10, count 0 2006.257.17:54:31.45#ibcon#read 6, iclass 10, count 0 2006.257.17:54:31.45#ibcon#end of sib2, iclass 10, count 0 2006.257.17:54:31.45#ibcon#*after write, iclass 10, count 0 2006.257.17:54:31.45#ibcon#*before return 0, iclass 10, count 0 2006.257.17:54:31.45#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:31.45#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.17:54:31.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.17:54:31.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.17:54:31.45$vck44/vblo=8,744.99 2006.257.17:54:31.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.17:54:31.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.17:54:31.45#ibcon#ireg 17 cls_cnt 0 2006.257.17:54:31.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:31.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:31.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:31.45#ibcon#enter wrdev, iclass 12, count 0 2006.257.17:54:31.45#ibcon#first serial, iclass 12, count 0 2006.257.17:54:31.45#ibcon#enter sib2, iclass 12, count 0 2006.257.17:54:31.45#ibcon#flushed, iclass 12, count 0 2006.257.17:54:31.45#ibcon#about to write, iclass 12, count 0 2006.257.17:54:31.45#ibcon#wrote, iclass 12, count 0 2006.257.17:54:31.45#ibcon#about to read 3, iclass 12, count 0 2006.257.17:54:31.47#ibcon#read 3, iclass 12, count 0 2006.257.17:54:31.47#ibcon#about to read 4, iclass 12, count 0 2006.257.17:54:31.47#ibcon#read 4, iclass 12, count 0 2006.257.17:54:31.47#ibcon#about to read 5, iclass 12, count 0 2006.257.17:54:31.47#ibcon#read 5, iclass 12, count 0 2006.257.17:54:31.47#ibcon#about to read 6, iclass 12, count 0 2006.257.17:54:31.47#ibcon#read 6, iclass 12, count 0 2006.257.17:54:31.47#ibcon#end of sib2, iclass 12, count 0 2006.257.17:54:31.47#ibcon#*mode == 0, iclass 12, count 0 2006.257.17:54:31.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.17:54:31.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.17:54:31.47#ibcon#*before write, iclass 12, count 0 2006.257.17:54:31.47#ibcon#enter sib2, iclass 12, count 0 2006.257.17:54:31.47#ibcon#flushed, iclass 12, count 0 2006.257.17:54:31.47#ibcon#about to write, iclass 12, count 0 2006.257.17:54:31.47#ibcon#wrote, iclass 12, count 0 2006.257.17:54:31.47#ibcon#about to read 3, iclass 12, count 0 2006.257.17:54:31.51#ibcon#read 3, iclass 12, count 0 2006.257.17:54:31.51#ibcon#about to read 4, iclass 12, count 0 2006.257.17:54:31.51#ibcon#read 4, iclass 12, count 0 2006.257.17:54:31.51#ibcon#about to read 5, iclass 12, count 0 2006.257.17:54:31.51#ibcon#read 5, iclass 12, count 0 2006.257.17:54:31.51#ibcon#about to read 6, iclass 12, count 0 2006.257.17:54:31.51#ibcon#read 6, iclass 12, count 0 2006.257.17:54:31.51#ibcon#end of sib2, iclass 12, count 0 2006.257.17:54:31.51#ibcon#*after write, iclass 12, count 0 2006.257.17:54:31.51#ibcon#*before return 0, iclass 12, count 0 2006.257.17:54:31.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:31.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.17:54:31.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.17:54:31.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.17:54:31.51$vck44/vb=8,4 2006.257.17:54:31.51#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.17:54:31.51#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.17:54:31.51#ibcon#ireg 11 cls_cnt 2 2006.257.17:54:31.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:31.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:31.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:31.57#ibcon#enter wrdev, iclass 14, count 2 2006.257.17:54:31.57#ibcon#first serial, iclass 14, count 2 2006.257.17:54:31.57#ibcon#enter sib2, iclass 14, count 2 2006.257.17:54:31.57#ibcon#flushed, iclass 14, count 2 2006.257.17:54:31.57#ibcon#about to write, iclass 14, count 2 2006.257.17:54:31.57#ibcon#wrote, iclass 14, count 2 2006.257.17:54:31.57#ibcon#about to read 3, iclass 14, count 2 2006.257.17:54:31.59#ibcon#read 3, iclass 14, count 2 2006.257.17:54:31.59#ibcon#about to read 4, iclass 14, count 2 2006.257.17:54:31.59#ibcon#read 4, iclass 14, count 2 2006.257.17:54:31.59#ibcon#about to read 5, iclass 14, count 2 2006.257.17:54:31.59#ibcon#read 5, iclass 14, count 2 2006.257.17:54:31.59#ibcon#about to read 6, iclass 14, count 2 2006.257.17:54:31.59#ibcon#read 6, iclass 14, count 2 2006.257.17:54:31.59#ibcon#end of sib2, iclass 14, count 2 2006.257.17:54:31.59#ibcon#*mode == 0, iclass 14, count 2 2006.257.17:54:31.59#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.17:54:31.59#ibcon#[27=AT08-04\r\n] 2006.257.17:54:31.59#ibcon#*before write, iclass 14, count 2 2006.257.17:54:31.59#ibcon#enter sib2, iclass 14, count 2 2006.257.17:54:31.59#ibcon#flushed, iclass 14, count 2 2006.257.17:54:31.59#ibcon#about to write, iclass 14, count 2 2006.257.17:54:31.59#ibcon#wrote, iclass 14, count 2 2006.257.17:54:31.59#ibcon#about to read 3, iclass 14, count 2 2006.257.17:54:31.62#ibcon#read 3, iclass 14, count 2 2006.257.17:54:31.62#ibcon#about to read 4, iclass 14, count 2 2006.257.17:54:31.62#ibcon#read 4, iclass 14, count 2 2006.257.17:54:31.62#ibcon#about to read 5, iclass 14, count 2 2006.257.17:54:31.62#ibcon#read 5, iclass 14, count 2 2006.257.17:54:31.62#ibcon#about to read 6, iclass 14, count 2 2006.257.17:54:31.62#ibcon#read 6, iclass 14, count 2 2006.257.17:54:31.62#ibcon#end of sib2, iclass 14, count 2 2006.257.17:54:31.62#ibcon#*after write, iclass 14, count 2 2006.257.17:54:31.62#ibcon#*before return 0, iclass 14, count 2 2006.257.17:54:31.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:31.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.17:54:31.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.17:54:31.62#ibcon#ireg 7 cls_cnt 0 2006.257.17:54:31.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:31.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:31.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:31.74#ibcon#enter wrdev, iclass 14, count 0 2006.257.17:54:31.74#ibcon#first serial, iclass 14, count 0 2006.257.17:54:31.74#ibcon#enter sib2, iclass 14, count 0 2006.257.17:54:31.74#ibcon#flushed, iclass 14, count 0 2006.257.17:54:31.74#ibcon#about to write, iclass 14, count 0 2006.257.17:54:31.74#ibcon#wrote, iclass 14, count 0 2006.257.17:54:31.74#ibcon#about to read 3, iclass 14, count 0 2006.257.17:54:31.76#ibcon#read 3, iclass 14, count 0 2006.257.17:54:31.76#ibcon#about to read 4, iclass 14, count 0 2006.257.17:54:31.76#ibcon#read 4, iclass 14, count 0 2006.257.17:54:31.76#ibcon#about to read 5, iclass 14, count 0 2006.257.17:54:31.76#ibcon#read 5, iclass 14, count 0 2006.257.17:54:31.76#ibcon#about to read 6, iclass 14, count 0 2006.257.17:54:31.76#ibcon#read 6, iclass 14, count 0 2006.257.17:54:31.76#ibcon#end of sib2, iclass 14, count 0 2006.257.17:54:31.76#ibcon#*mode == 0, iclass 14, count 0 2006.257.17:54:31.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.17:54:31.76#ibcon#[27=USB\r\n] 2006.257.17:54:31.76#ibcon#*before write, iclass 14, count 0 2006.257.17:54:31.76#ibcon#enter sib2, iclass 14, count 0 2006.257.17:54:31.76#ibcon#flushed, iclass 14, count 0 2006.257.17:54:31.76#ibcon#about to write, iclass 14, count 0 2006.257.17:54:31.76#ibcon#wrote, iclass 14, count 0 2006.257.17:54:31.76#ibcon#about to read 3, iclass 14, count 0 2006.257.17:54:31.79#ibcon#read 3, iclass 14, count 0 2006.257.17:54:31.79#ibcon#about to read 4, iclass 14, count 0 2006.257.17:54:31.79#ibcon#read 4, iclass 14, count 0 2006.257.17:54:31.79#ibcon#about to read 5, iclass 14, count 0 2006.257.17:54:31.79#ibcon#read 5, iclass 14, count 0 2006.257.17:54:31.79#ibcon#about to read 6, iclass 14, count 0 2006.257.17:54:31.79#ibcon#read 6, iclass 14, count 0 2006.257.17:54:31.79#ibcon#end of sib2, iclass 14, count 0 2006.257.17:54:31.79#ibcon#*after write, iclass 14, count 0 2006.257.17:54:31.79#ibcon#*before return 0, iclass 14, count 0 2006.257.17:54:31.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:31.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.17:54:31.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.17:54:31.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.17:54:31.79$vck44/vabw=wide 2006.257.17:54:31.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.17:54:31.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.17:54:31.79#ibcon#ireg 8 cls_cnt 0 2006.257.17:54:31.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:31.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:31.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:31.79#ibcon#enter wrdev, iclass 16, count 0 2006.257.17:54:31.79#ibcon#first serial, iclass 16, count 0 2006.257.17:54:31.79#ibcon#enter sib2, iclass 16, count 0 2006.257.17:54:31.79#ibcon#flushed, iclass 16, count 0 2006.257.17:54:31.79#ibcon#about to write, iclass 16, count 0 2006.257.17:54:31.79#ibcon#wrote, iclass 16, count 0 2006.257.17:54:31.79#ibcon#about to read 3, iclass 16, count 0 2006.257.17:54:31.81#ibcon#read 3, iclass 16, count 0 2006.257.17:54:31.81#ibcon#about to read 4, iclass 16, count 0 2006.257.17:54:31.81#ibcon#read 4, iclass 16, count 0 2006.257.17:54:31.81#ibcon#about to read 5, iclass 16, count 0 2006.257.17:54:31.81#ibcon#read 5, iclass 16, count 0 2006.257.17:54:31.81#ibcon#about to read 6, iclass 16, count 0 2006.257.17:54:31.81#ibcon#read 6, iclass 16, count 0 2006.257.17:54:31.81#ibcon#end of sib2, iclass 16, count 0 2006.257.17:54:31.81#ibcon#*mode == 0, iclass 16, count 0 2006.257.17:54:31.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.17:54:31.81#ibcon#[25=BW32\r\n] 2006.257.17:54:31.81#ibcon#*before write, iclass 16, count 0 2006.257.17:54:31.81#ibcon#enter sib2, iclass 16, count 0 2006.257.17:54:31.81#ibcon#flushed, iclass 16, count 0 2006.257.17:54:31.81#ibcon#about to write, iclass 16, count 0 2006.257.17:54:31.81#ibcon#wrote, iclass 16, count 0 2006.257.17:54:31.81#ibcon#about to read 3, iclass 16, count 0 2006.257.17:54:31.84#ibcon#read 3, iclass 16, count 0 2006.257.17:54:31.84#ibcon#about to read 4, iclass 16, count 0 2006.257.17:54:31.84#ibcon#read 4, iclass 16, count 0 2006.257.17:54:31.84#ibcon#about to read 5, iclass 16, count 0 2006.257.17:54:31.84#ibcon#read 5, iclass 16, count 0 2006.257.17:54:31.84#ibcon#about to read 6, iclass 16, count 0 2006.257.17:54:31.84#ibcon#read 6, iclass 16, count 0 2006.257.17:54:31.84#ibcon#end of sib2, iclass 16, count 0 2006.257.17:54:31.84#ibcon#*after write, iclass 16, count 0 2006.257.17:54:31.84#ibcon#*before return 0, iclass 16, count 0 2006.257.17:54:31.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:31.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.17:54:31.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.17:54:31.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.17:54:31.84$vck44/vbbw=wide 2006.257.17:54:31.84#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.17:54:31.84#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.17:54:31.84#ibcon#ireg 8 cls_cnt 0 2006.257.17:54:31.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:54:31.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:54:31.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:54:31.91#ibcon#enter wrdev, iclass 18, count 0 2006.257.17:54:31.91#ibcon#first serial, iclass 18, count 0 2006.257.17:54:31.91#ibcon#enter sib2, iclass 18, count 0 2006.257.17:54:31.91#ibcon#flushed, iclass 18, count 0 2006.257.17:54:31.91#ibcon#about to write, iclass 18, count 0 2006.257.17:54:31.91#ibcon#wrote, iclass 18, count 0 2006.257.17:54:31.91#ibcon#about to read 3, iclass 18, count 0 2006.257.17:54:31.92#abcon#<5=/14 1.3 3.5 17.24 981014.3\r\n> 2006.257.17:54:31.93#ibcon#read 3, iclass 18, count 0 2006.257.17:54:31.93#ibcon#about to read 4, iclass 18, count 0 2006.257.17:54:31.93#ibcon#read 4, iclass 18, count 0 2006.257.17:54:31.93#ibcon#about to read 5, iclass 18, count 0 2006.257.17:54:31.93#ibcon#read 5, iclass 18, count 0 2006.257.17:54:31.93#ibcon#about to read 6, iclass 18, count 0 2006.257.17:54:31.93#ibcon#read 6, iclass 18, count 0 2006.257.17:54:31.93#ibcon#end of sib2, iclass 18, count 0 2006.257.17:54:31.93#ibcon#*mode == 0, iclass 18, count 0 2006.257.17:54:31.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.17:54:31.93#ibcon#[27=BW32\r\n] 2006.257.17:54:31.93#ibcon#*before write, iclass 18, count 0 2006.257.17:54:31.93#ibcon#enter sib2, iclass 18, count 0 2006.257.17:54:31.93#ibcon#flushed, iclass 18, count 0 2006.257.17:54:31.93#ibcon#about to write, iclass 18, count 0 2006.257.17:54:31.93#ibcon#wrote, iclass 18, count 0 2006.257.17:54:31.93#ibcon#about to read 3, iclass 18, count 0 2006.257.17:54:31.94#abcon#{5=INTERFACE CLEAR} 2006.257.17:54:31.96#ibcon#read 3, iclass 18, count 0 2006.257.17:54:31.96#ibcon#about to read 4, iclass 18, count 0 2006.257.17:54:31.96#ibcon#read 4, iclass 18, count 0 2006.257.17:54:31.96#ibcon#about to read 5, iclass 18, count 0 2006.257.17:54:31.96#ibcon#read 5, iclass 18, count 0 2006.257.17:54:31.96#ibcon#about to read 6, iclass 18, count 0 2006.257.17:54:31.96#ibcon#read 6, iclass 18, count 0 2006.257.17:54:31.96#ibcon#end of sib2, iclass 18, count 0 2006.257.17:54:31.96#ibcon#*after write, iclass 18, count 0 2006.257.17:54:31.96#ibcon#*before return 0, iclass 18, count 0 2006.257.17:54:31.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:54:31.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.17:54:31.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.17:54:31.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.17:54:31.96$setupk4/ifdk4 2006.257.17:54:31.96$ifdk4/lo= 2006.257.17:54:31.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.17:54:31.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.17:54:31.96$ifdk4/patch= 2006.257.17:54:31.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.17:54:31.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.17:54:31.96$setupk4/!*+20s 2006.257.17:54:32.00#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:54:42.09#abcon#<5=/14 1.3 3.5 17.24 981014.3\r\n> 2006.257.17:54:42.11#abcon#{5=INTERFACE CLEAR} 2006.257.17:54:42.17#abcon#[5=S1D000X0/0*\r\n] 2006.257.17:54:46.46$setupk4/"tpicd 2006.257.17:54:46.46$setupk4/echo=off 2006.257.17:54:46.46$setupk4/xlog=off 2006.257.17:54:46.46:!2006.257.17:55:12 2006.257.17:54:54.14#trakl#Source acquired 2006.257.17:54:55.14#flagr#flagr/antenna,acquired 2006.257.17:55:12.00:preob 2006.257.17:55:12.14/onsource/TRACKING 2006.257.17:55:12.14:!2006.257.17:55:22 2006.257.17:55:22.00:"tape 2006.257.17:55:22.00:"st=record 2006.257.17:55:22.00:data_valid=on 2006.257.17:55:22.00:midob 2006.257.17:55:22.14/onsource/TRACKING 2006.257.17:55:22.14/wx/17.24,1014.3,98 2006.257.17:55:22.23/cable/+6.4818E-03 2006.257.17:55:23.32/va/01,08,usb,yes,30,32 2006.257.17:55:23.32/va/02,07,usb,yes,32,33 2006.257.17:55:23.32/va/03,08,usb,yes,29,31 2006.257.17:55:23.32/va/04,07,usb,yes,33,35 2006.257.17:55:23.32/va/05,04,usb,yes,30,30 2006.257.17:55:23.32/va/06,04,usb,yes,33,33 2006.257.17:55:23.32/va/07,04,usb,yes,34,34 2006.257.17:55:23.32/va/08,04,usb,yes,28,35 2006.257.17:55:23.55/valo/01,524.99,yes,locked 2006.257.17:55:23.55/valo/02,534.99,yes,locked 2006.257.17:55:23.55/valo/03,564.99,yes,locked 2006.257.17:55:23.55/valo/04,624.99,yes,locked 2006.257.17:55:23.55/valo/05,734.99,yes,locked 2006.257.17:55:23.55/valo/06,814.99,yes,locked 2006.257.17:55:23.55/valo/07,864.99,yes,locked 2006.257.17:55:23.55/valo/08,884.99,yes,locked 2006.257.17:55:24.64/vb/01,04,usb,yes,30,28 2006.257.17:55:24.64/vb/02,05,usb,yes,29,28 2006.257.17:55:24.64/vb/03,04,usb,yes,29,32 2006.257.17:55:24.64/vb/04,05,usb,yes,30,29 2006.257.17:55:24.64/vb/05,04,usb,yes,26,29 2006.257.17:55:24.64/vb/06,04,usb,yes,31,27 2006.257.17:55:24.64/vb/07,04,usb,yes,30,30 2006.257.17:55:24.64/vb/08,04,usb,yes,28,31 2006.257.17:55:24.88/vblo/01,629.99,yes,locked 2006.257.17:55:24.88/vblo/02,634.99,yes,locked 2006.257.17:55:24.88/vblo/03,649.99,yes,locked 2006.257.17:55:24.88/vblo/04,679.99,yes,locked 2006.257.17:55:24.88/vblo/05,709.99,yes,locked 2006.257.17:55:24.88/vblo/06,719.99,yes,locked 2006.257.17:55:24.88/vblo/07,734.99,yes,locked 2006.257.17:55:24.88/vblo/08,744.99,yes,locked 2006.257.17:55:25.03/vabw/8 2006.257.17:55:25.18/vbbw/8 2006.257.17:55:25.34/xfe/off,on,15.0 2006.257.17:55:25.73/ifatt/23,28,28,28 2006.257.17:55:26.07/fmout-gps/S +4.50E-07 2006.257.17:55:26.11:!2006.257.18:00:32 2006.257.18:00:32.00:data_valid=off 2006.257.18:00:32.00:"et 2006.257.18:00:32.00:!+3s 2006.257.18:00:35.01:"tape 2006.257.18:00:35.01:postob 2006.257.18:00:35.11/cable/+6.4850E-03 2006.257.18:00:35.11/wx/17.20,1014.3,98 2006.257.18:00:36.08/fmout-gps/S +4.50E-07 2006.257.18:00:36.08:scan_name=257-1801,jd0609,500 2006.257.18:00:36.08:source=0804+499,080839.67,495036.5,2000.0,cw 2006.257.18:00:37.14#flagr#flagr/antenna,new-source 2006.257.18:00:37.14:checkk5 2006.257.18:00:37.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:00:37.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:00:38.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:00:38.54/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:00:38.87/chk_obsdata//k5ts1/T2571755??a.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.257.18:00:39.21/chk_obsdata//k5ts2/T2571755??b.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.257.18:00:39.54/chk_obsdata//k5ts3/T2571755??c.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.257.18:00:39.87/chk_obsdata//k5ts4/T2571755??d.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.257.18:00:40.54/k5log//k5ts1_log_newline 2006.257.18:00:41.23/k5log//k5ts2_log_newline 2006.257.18:00:41.89/k5log//k5ts3_log_newline 2006.257.18:00:42.56/k5log//k5ts4_log_newline 2006.257.18:00:42.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:00:42.58:setupk4=1 2006.257.18:00:42.58$setupk4/echo=on 2006.257.18:00:42.58$setupk4/pcalon 2006.257.18:00:42.58$pcalon/"no phase cal control is implemented here 2006.257.18:00:42.58$setupk4/"tpicd=stop 2006.257.18:00:42.58$setupk4/"rec=synch_on 2006.257.18:00:42.58$setupk4/"rec_mode=128 2006.257.18:00:42.58$setupk4/!* 2006.257.18:00:42.58$setupk4/recpk4 2006.257.18:00:42.58$recpk4/recpatch= 2006.257.18:00:42.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:00:42.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:00:42.59$setupk4/vck44 2006.257.18:00:42.59$vck44/valo=1,524.99 2006.257.18:00:42.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.18:00:42.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.18:00:42.59#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:42.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:42.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:42.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:42.59#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:00:42.59#ibcon#first serial, iclass 27, count 0 2006.257.18:00:42.59#ibcon#enter sib2, iclass 27, count 0 2006.257.18:00:42.59#ibcon#flushed, iclass 27, count 0 2006.257.18:00:42.59#ibcon#about to write, iclass 27, count 0 2006.257.18:00:42.59#ibcon#wrote, iclass 27, count 0 2006.257.18:00:42.59#ibcon#about to read 3, iclass 27, count 0 2006.257.18:00:42.61#ibcon#read 3, iclass 27, count 0 2006.257.18:00:42.61#ibcon#about to read 4, iclass 27, count 0 2006.257.18:00:42.61#ibcon#read 4, iclass 27, count 0 2006.257.18:00:42.61#ibcon#about to read 5, iclass 27, count 0 2006.257.18:00:42.61#ibcon#read 5, iclass 27, count 0 2006.257.18:00:42.61#ibcon#about to read 6, iclass 27, count 0 2006.257.18:00:42.61#ibcon#read 6, iclass 27, count 0 2006.257.18:00:42.61#ibcon#end of sib2, iclass 27, count 0 2006.257.18:00:42.61#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:00:42.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:00:42.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:00:42.61#ibcon#*before write, iclass 27, count 0 2006.257.18:00:42.61#ibcon#enter sib2, iclass 27, count 0 2006.257.18:00:42.61#ibcon#flushed, iclass 27, count 0 2006.257.18:00:42.61#ibcon#about to write, iclass 27, count 0 2006.257.18:00:42.61#ibcon#wrote, iclass 27, count 0 2006.257.18:00:42.61#ibcon#about to read 3, iclass 27, count 0 2006.257.18:00:42.66#ibcon#read 3, iclass 27, count 0 2006.257.18:00:42.66#ibcon#about to read 4, iclass 27, count 0 2006.257.18:00:42.66#ibcon#read 4, iclass 27, count 0 2006.257.18:00:42.66#ibcon#about to read 5, iclass 27, count 0 2006.257.18:00:42.66#ibcon#read 5, iclass 27, count 0 2006.257.18:00:42.66#ibcon#about to read 6, iclass 27, count 0 2006.257.18:00:42.66#ibcon#read 6, iclass 27, count 0 2006.257.18:00:42.66#ibcon#end of sib2, iclass 27, count 0 2006.257.18:00:42.66#ibcon#*after write, iclass 27, count 0 2006.257.18:00:42.66#ibcon#*before return 0, iclass 27, count 0 2006.257.18:00:42.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:42.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:42.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:00:42.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:00:42.66$vck44/va=1,8 2006.257.18:00:42.66#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.18:00:42.66#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.18:00:42.66#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:42.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:42.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:42.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:42.66#ibcon#enter wrdev, iclass 29, count 2 2006.257.18:00:42.66#ibcon#first serial, iclass 29, count 2 2006.257.18:00:42.66#ibcon#enter sib2, iclass 29, count 2 2006.257.18:00:42.66#ibcon#flushed, iclass 29, count 2 2006.257.18:00:42.66#ibcon#about to write, iclass 29, count 2 2006.257.18:00:42.66#ibcon#wrote, iclass 29, count 2 2006.257.18:00:42.66#ibcon#about to read 3, iclass 29, count 2 2006.257.18:00:42.68#ibcon#read 3, iclass 29, count 2 2006.257.18:00:42.68#ibcon#about to read 4, iclass 29, count 2 2006.257.18:00:42.68#ibcon#read 4, iclass 29, count 2 2006.257.18:00:42.68#ibcon#about to read 5, iclass 29, count 2 2006.257.18:00:42.68#ibcon#read 5, iclass 29, count 2 2006.257.18:00:42.68#ibcon#about to read 6, iclass 29, count 2 2006.257.18:00:42.68#ibcon#read 6, iclass 29, count 2 2006.257.18:00:42.68#ibcon#end of sib2, iclass 29, count 2 2006.257.18:00:42.68#ibcon#*mode == 0, iclass 29, count 2 2006.257.18:00:42.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.18:00:42.68#ibcon#[25=AT01-08\r\n] 2006.257.18:00:42.68#ibcon#*before write, iclass 29, count 2 2006.257.18:00:42.68#ibcon#enter sib2, iclass 29, count 2 2006.257.18:00:42.68#ibcon#flushed, iclass 29, count 2 2006.257.18:00:42.68#ibcon#about to write, iclass 29, count 2 2006.257.18:00:42.68#ibcon#wrote, iclass 29, count 2 2006.257.18:00:42.68#ibcon#about to read 3, iclass 29, count 2 2006.257.18:00:42.71#ibcon#read 3, iclass 29, count 2 2006.257.18:00:42.71#ibcon#about to read 4, iclass 29, count 2 2006.257.18:00:42.71#ibcon#read 4, iclass 29, count 2 2006.257.18:00:42.71#ibcon#about to read 5, iclass 29, count 2 2006.257.18:00:42.71#ibcon#read 5, iclass 29, count 2 2006.257.18:00:42.71#ibcon#about to read 6, iclass 29, count 2 2006.257.18:00:42.71#ibcon#read 6, iclass 29, count 2 2006.257.18:00:42.71#ibcon#end of sib2, iclass 29, count 2 2006.257.18:00:42.71#ibcon#*after write, iclass 29, count 2 2006.257.18:00:42.71#ibcon#*before return 0, iclass 29, count 2 2006.257.18:00:42.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:42.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:42.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.18:00:42.71#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:42.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:42.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:42.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:42.83#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:00:42.83#ibcon#first serial, iclass 29, count 0 2006.257.18:00:42.83#ibcon#enter sib2, iclass 29, count 0 2006.257.18:00:42.83#ibcon#flushed, iclass 29, count 0 2006.257.18:00:42.83#ibcon#about to write, iclass 29, count 0 2006.257.18:00:42.83#ibcon#wrote, iclass 29, count 0 2006.257.18:00:42.83#ibcon#about to read 3, iclass 29, count 0 2006.257.18:00:42.85#ibcon#read 3, iclass 29, count 0 2006.257.18:00:42.85#ibcon#about to read 4, iclass 29, count 0 2006.257.18:00:42.85#ibcon#read 4, iclass 29, count 0 2006.257.18:00:42.85#ibcon#about to read 5, iclass 29, count 0 2006.257.18:00:42.85#ibcon#read 5, iclass 29, count 0 2006.257.18:00:42.85#ibcon#about to read 6, iclass 29, count 0 2006.257.18:00:42.85#ibcon#read 6, iclass 29, count 0 2006.257.18:00:42.85#ibcon#end of sib2, iclass 29, count 0 2006.257.18:00:42.85#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:00:42.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:00:42.85#ibcon#[25=USB\r\n] 2006.257.18:00:42.85#ibcon#*before write, iclass 29, count 0 2006.257.18:00:42.85#ibcon#enter sib2, iclass 29, count 0 2006.257.18:00:42.85#ibcon#flushed, iclass 29, count 0 2006.257.18:00:42.85#ibcon#about to write, iclass 29, count 0 2006.257.18:00:42.85#ibcon#wrote, iclass 29, count 0 2006.257.18:00:42.85#ibcon#about to read 3, iclass 29, count 0 2006.257.18:00:42.88#ibcon#read 3, iclass 29, count 0 2006.257.18:00:42.88#ibcon#about to read 4, iclass 29, count 0 2006.257.18:00:42.88#ibcon#read 4, iclass 29, count 0 2006.257.18:00:42.88#ibcon#about to read 5, iclass 29, count 0 2006.257.18:00:42.88#ibcon#read 5, iclass 29, count 0 2006.257.18:00:42.88#ibcon#about to read 6, iclass 29, count 0 2006.257.18:00:42.88#ibcon#read 6, iclass 29, count 0 2006.257.18:00:42.88#ibcon#end of sib2, iclass 29, count 0 2006.257.18:00:42.88#ibcon#*after write, iclass 29, count 0 2006.257.18:00:42.88#ibcon#*before return 0, iclass 29, count 0 2006.257.18:00:42.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:42.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:42.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:00:42.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:00:42.88$vck44/valo=2,534.99 2006.257.18:00:42.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.18:00:42.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.18:00:42.88#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:42.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:42.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:42.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:42.88#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:00:42.88#ibcon#first serial, iclass 31, count 0 2006.257.18:00:42.88#ibcon#enter sib2, iclass 31, count 0 2006.257.18:00:42.88#ibcon#flushed, iclass 31, count 0 2006.257.18:00:42.88#ibcon#about to write, iclass 31, count 0 2006.257.18:00:42.88#ibcon#wrote, iclass 31, count 0 2006.257.18:00:42.88#ibcon#about to read 3, iclass 31, count 0 2006.257.18:00:42.90#ibcon#read 3, iclass 31, count 0 2006.257.18:00:42.90#ibcon#about to read 4, iclass 31, count 0 2006.257.18:00:42.90#ibcon#read 4, iclass 31, count 0 2006.257.18:00:42.90#ibcon#about to read 5, iclass 31, count 0 2006.257.18:00:42.90#ibcon#read 5, iclass 31, count 0 2006.257.18:00:42.90#ibcon#about to read 6, iclass 31, count 0 2006.257.18:00:42.90#ibcon#read 6, iclass 31, count 0 2006.257.18:00:42.90#ibcon#end of sib2, iclass 31, count 0 2006.257.18:00:42.90#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:00:42.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:00:42.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:00:42.90#ibcon#*before write, iclass 31, count 0 2006.257.18:00:42.90#ibcon#enter sib2, iclass 31, count 0 2006.257.18:00:42.90#ibcon#flushed, iclass 31, count 0 2006.257.18:00:42.90#ibcon#about to write, iclass 31, count 0 2006.257.18:00:42.90#ibcon#wrote, iclass 31, count 0 2006.257.18:00:42.90#ibcon#about to read 3, iclass 31, count 0 2006.257.18:00:42.94#ibcon#read 3, iclass 31, count 0 2006.257.18:00:42.94#ibcon#about to read 4, iclass 31, count 0 2006.257.18:00:42.94#ibcon#read 4, iclass 31, count 0 2006.257.18:00:42.94#ibcon#about to read 5, iclass 31, count 0 2006.257.18:00:42.94#ibcon#read 5, iclass 31, count 0 2006.257.18:00:42.94#ibcon#about to read 6, iclass 31, count 0 2006.257.18:00:42.94#ibcon#read 6, iclass 31, count 0 2006.257.18:00:42.94#ibcon#end of sib2, iclass 31, count 0 2006.257.18:00:42.94#ibcon#*after write, iclass 31, count 0 2006.257.18:00:42.94#ibcon#*before return 0, iclass 31, count 0 2006.257.18:00:42.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:42.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:42.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:00:42.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:00:42.94$vck44/va=2,7 2006.257.18:00:42.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.18:00:42.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.18:00:42.94#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:42.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:43.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:43.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:43.00#ibcon#enter wrdev, iclass 33, count 2 2006.257.18:00:43.00#ibcon#first serial, iclass 33, count 2 2006.257.18:00:43.00#ibcon#enter sib2, iclass 33, count 2 2006.257.18:00:43.00#ibcon#flushed, iclass 33, count 2 2006.257.18:00:43.00#ibcon#about to write, iclass 33, count 2 2006.257.18:00:43.00#ibcon#wrote, iclass 33, count 2 2006.257.18:00:43.00#ibcon#about to read 3, iclass 33, count 2 2006.257.18:00:43.02#ibcon#read 3, iclass 33, count 2 2006.257.18:00:43.02#ibcon#about to read 4, iclass 33, count 2 2006.257.18:00:43.02#ibcon#read 4, iclass 33, count 2 2006.257.18:00:43.02#ibcon#about to read 5, iclass 33, count 2 2006.257.18:00:43.02#ibcon#read 5, iclass 33, count 2 2006.257.18:00:43.02#ibcon#about to read 6, iclass 33, count 2 2006.257.18:00:43.02#ibcon#read 6, iclass 33, count 2 2006.257.18:00:43.02#ibcon#end of sib2, iclass 33, count 2 2006.257.18:00:43.02#ibcon#*mode == 0, iclass 33, count 2 2006.257.18:00:43.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.18:00:43.02#ibcon#[25=AT02-07\r\n] 2006.257.18:00:43.02#ibcon#*before write, iclass 33, count 2 2006.257.18:00:43.02#ibcon#enter sib2, iclass 33, count 2 2006.257.18:00:43.02#ibcon#flushed, iclass 33, count 2 2006.257.18:00:43.02#ibcon#about to write, iclass 33, count 2 2006.257.18:00:43.02#ibcon#wrote, iclass 33, count 2 2006.257.18:00:43.02#ibcon#about to read 3, iclass 33, count 2 2006.257.18:00:43.05#ibcon#read 3, iclass 33, count 2 2006.257.18:00:43.05#ibcon#about to read 4, iclass 33, count 2 2006.257.18:00:43.05#ibcon#read 4, iclass 33, count 2 2006.257.18:00:43.05#ibcon#about to read 5, iclass 33, count 2 2006.257.18:00:43.05#ibcon#read 5, iclass 33, count 2 2006.257.18:00:43.05#ibcon#about to read 6, iclass 33, count 2 2006.257.18:00:43.05#ibcon#read 6, iclass 33, count 2 2006.257.18:00:43.05#ibcon#end of sib2, iclass 33, count 2 2006.257.18:00:43.05#ibcon#*after write, iclass 33, count 2 2006.257.18:00:43.05#ibcon#*before return 0, iclass 33, count 2 2006.257.18:00:43.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:43.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:43.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.18:00:43.05#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:43.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:43.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:43.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:43.17#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:00:43.17#ibcon#first serial, iclass 33, count 0 2006.257.18:00:43.17#ibcon#enter sib2, iclass 33, count 0 2006.257.18:00:43.17#ibcon#flushed, iclass 33, count 0 2006.257.18:00:43.17#ibcon#about to write, iclass 33, count 0 2006.257.18:00:43.17#ibcon#wrote, iclass 33, count 0 2006.257.18:00:43.17#ibcon#about to read 3, iclass 33, count 0 2006.257.18:00:43.19#ibcon#read 3, iclass 33, count 0 2006.257.18:00:43.19#ibcon#about to read 4, iclass 33, count 0 2006.257.18:00:43.19#ibcon#read 4, iclass 33, count 0 2006.257.18:00:43.19#ibcon#about to read 5, iclass 33, count 0 2006.257.18:00:43.19#ibcon#read 5, iclass 33, count 0 2006.257.18:00:43.19#ibcon#about to read 6, iclass 33, count 0 2006.257.18:00:43.19#ibcon#read 6, iclass 33, count 0 2006.257.18:00:43.19#ibcon#end of sib2, iclass 33, count 0 2006.257.18:00:43.19#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:00:43.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:00:43.19#ibcon#[25=USB\r\n] 2006.257.18:00:43.19#ibcon#*before write, iclass 33, count 0 2006.257.18:00:43.19#ibcon#enter sib2, iclass 33, count 0 2006.257.18:00:43.19#ibcon#flushed, iclass 33, count 0 2006.257.18:00:43.19#ibcon#about to write, iclass 33, count 0 2006.257.18:00:43.19#ibcon#wrote, iclass 33, count 0 2006.257.18:00:43.19#ibcon#about to read 3, iclass 33, count 0 2006.257.18:00:43.22#ibcon#read 3, iclass 33, count 0 2006.257.18:00:43.22#ibcon#about to read 4, iclass 33, count 0 2006.257.18:00:43.22#ibcon#read 4, iclass 33, count 0 2006.257.18:00:43.22#ibcon#about to read 5, iclass 33, count 0 2006.257.18:00:43.22#ibcon#read 5, iclass 33, count 0 2006.257.18:00:43.22#ibcon#about to read 6, iclass 33, count 0 2006.257.18:00:43.22#ibcon#read 6, iclass 33, count 0 2006.257.18:00:43.22#ibcon#end of sib2, iclass 33, count 0 2006.257.18:00:43.22#ibcon#*after write, iclass 33, count 0 2006.257.18:00:43.22#ibcon#*before return 0, iclass 33, count 0 2006.257.18:00:43.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:43.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:43.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:00:43.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:00:43.22$vck44/valo=3,564.99 2006.257.18:00:43.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.18:00:43.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.18:00:43.22#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:43.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:43.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:43.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:43.22#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:00:43.22#ibcon#first serial, iclass 35, count 0 2006.257.18:00:43.22#ibcon#enter sib2, iclass 35, count 0 2006.257.18:00:43.22#ibcon#flushed, iclass 35, count 0 2006.257.18:00:43.22#ibcon#about to write, iclass 35, count 0 2006.257.18:00:43.22#ibcon#wrote, iclass 35, count 0 2006.257.18:00:43.22#ibcon#about to read 3, iclass 35, count 0 2006.257.18:00:43.24#ibcon#read 3, iclass 35, count 0 2006.257.18:00:43.24#ibcon#about to read 4, iclass 35, count 0 2006.257.18:00:43.24#ibcon#read 4, iclass 35, count 0 2006.257.18:00:43.24#ibcon#about to read 5, iclass 35, count 0 2006.257.18:00:43.24#ibcon#read 5, iclass 35, count 0 2006.257.18:00:43.24#ibcon#about to read 6, iclass 35, count 0 2006.257.18:00:43.24#ibcon#read 6, iclass 35, count 0 2006.257.18:00:43.24#ibcon#end of sib2, iclass 35, count 0 2006.257.18:00:43.24#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:00:43.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:00:43.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:00:43.24#ibcon#*before write, iclass 35, count 0 2006.257.18:00:43.24#ibcon#enter sib2, iclass 35, count 0 2006.257.18:00:43.24#ibcon#flushed, iclass 35, count 0 2006.257.18:00:43.24#ibcon#about to write, iclass 35, count 0 2006.257.18:00:43.24#ibcon#wrote, iclass 35, count 0 2006.257.18:00:43.24#ibcon#about to read 3, iclass 35, count 0 2006.257.18:00:43.28#ibcon#read 3, iclass 35, count 0 2006.257.18:00:43.28#ibcon#about to read 4, iclass 35, count 0 2006.257.18:00:43.28#ibcon#read 4, iclass 35, count 0 2006.257.18:00:43.28#ibcon#about to read 5, iclass 35, count 0 2006.257.18:00:43.28#ibcon#read 5, iclass 35, count 0 2006.257.18:00:43.28#ibcon#about to read 6, iclass 35, count 0 2006.257.18:00:43.28#ibcon#read 6, iclass 35, count 0 2006.257.18:00:43.28#ibcon#end of sib2, iclass 35, count 0 2006.257.18:00:43.28#ibcon#*after write, iclass 35, count 0 2006.257.18:00:43.28#ibcon#*before return 0, iclass 35, count 0 2006.257.18:00:43.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:43.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:43.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:00:43.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:00:43.28$vck44/va=3,8 2006.257.18:00:43.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.18:00:43.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.18:00:43.28#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:43.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:43.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:43.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:43.34#ibcon#enter wrdev, iclass 37, count 2 2006.257.18:00:43.34#ibcon#first serial, iclass 37, count 2 2006.257.18:00:43.34#ibcon#enter sib2, iclass 37, count 2 2006.257.18:00:43.34#ibcon#flushed, iclass 37, count 2 2006.257.18:00:43.34#ibcon#about to write, iclass 37, count 2 2006.257.18:00:43.34#ibcon#wrote, iclass 37, count 2 2006.257.18:00:43.34#ibcon#about to read 3, iclass 37, count 2 2006.257.18:00:43.36#ibcon#read 3, iclass 37, count 2 2006.257.18:00:43.36#ibcon#about to read 4, iclass 37, count 2 2006.257.18:00:43.36#ibcon#read 4, iclass 37, count 2 2006.257.18:00:43.36#ibcon#about to read 5, iclass 37, count 2 2006.257.18:00:43.36#ibcon#read 5, iclass 37, count 2 2006.257.18:00:43.36#ibcon#about to read 6, iclass 37, count 2 2006.257.18:00:43.36#ibcon#read 6, iclass 37, count 2 2006.257.18:00:43.36#ibcon#end of sib2, iclass 37, count 2 2006.257.18:00:43.36#ibcon#*mode == 0, iclass 37, count 2 2006.257.18:00:43.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.18:00:43.36#ibcon#[25=AT03-08\r\n] 2006.257.18:00:43.36#ibcon#*before write, iclass 37, count 2 2006.257.18:00:43.36#ibcon#enter sib2, iclass 37, count 2 2006.257.18:00:43.36#ibcon#flushed, iclass 37, count 2 2006.257.18:00:43.36#ibcon#about to write, iclass 37, count 2 2006.257.18:00:43.36#ibcon#wrote, iclass 37, count 2 2006.257.18:00:43.36#ibcon#about to read 3, iclass 37, count 2 2006.257.18:00:43.39#ibcon#read 3, iclass 37, count 2 2006.257.18:00:43.39#ibcon#about to read 4, iclass 37, count 2 2006.257.18:00:43.39#ibcon#read 4, iclass 37, count 2 2006.257.18:00:43.39#ibcon#about to read 5, iclass 37, count 2 2006.257.18:00:43.39#ibcon#read 5, iclass 37, count 2 2006.257.18:00:43.39#ibcon#about to read 6, iclass 37, count 2 2006.257.18:00:43.39#ibcon#read 6, iclass 37, count 2 2006.257.18:00:43.39#ibcon#end of sib2, iclass 37, count 2 2006.257.18:00:43.39#ibcon#*after write, iclass 37, count 2 2006.257.18:00:43.39#ibcon#*before return 0, iclass 37, count 2 2006.257.18:00:43.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:43.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:43.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.18:00:43.39#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:43.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:43.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:43.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:43.51#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:00:43.51#ibcon#first serial, iclass 37, count 0 2006.257.18:00:43.51#ibcon#enter sib2, iclass 37, count 0 2006.257.18:00:43.51#ibcon#flushed, iclass 37, count 0 2006.257.18:00:43.51#ibcon#about to write, iclass 37, count 0 2006.257.18:00:43.51#ibcon#wrote, iclass 37, count 0 2006.257.18:00:43.51#ibcon#about to read 3, iclass 37, count 0 2006.257.18:00:43.53#ibcon#read 3, iclass 37, count 0 2006.257.18:00:43.53#ibcon#about to read 4, iclass 37, count 0 2006.257.18:00:43.53#ibcon#read 4, iclass 37, count 0 2006.257.18:00:43.53#ibcon#about to read 5, iclass 37, count 0 2006.257.18:00:43.53#ibcon#read 5, iclass 37, count 0 2006.257.18:00:43.53#ibcon#about to read 6, iclass 37, count 0 2006.257.18:00:43.53#ibcon#read 6, iclass 37, count 0 2006.257.18:00:43.53#ibcon#end of sib2, iclass 37, count 0 2006.257.18:00:43.53#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:00:43.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:00:43.53#ibcon#[25=USB\r\n] 2006.257.18:00:43.53#ibcon#*before write, iclass 37, count 0 2006.257.18:00:43.53#ibcon#enter sib2, iclass 37, count 0 2006.257.18:00:43.53#ibcon#flushed, iclass 37, count 0 2006.257.18:00:43.53#ibcon#about to write, iclass 37, count 0 2006.257.18:00:43.53#ibcon#wrote, iclass 37, count 0 2006.257.18:00:43.53#ibcon#about to read 3, iclass 37, count 0 2006.257.18:00:43.56#ibcon#read 3, iclass 37, count 0 2006.257.18:00:43.56#ibcon#about to read 4, iclass 37, count 0 2006.257.18:00:43.56#ibcon#read 4, iclass 37, count 0 2006.257.18:00:43.56#ibcon#about to read 5, iclass 37, count 0 2006.257.18:00:43.56#ibcon#read 5, iclass 37, count 0 2006.257.18:00:43.56#ibcon#about to read 6, iclass 37, count 0 2006.257.18:00:43.56#ibcon#read 6, iclass 37, count 0 2006.257.18:00:43.56#ibcon#end of sib2, iclass 37, count 0 2006.257.18:00:43.56#ibcon#*after write, iclass 37, count 0 2006.257.18:00:43.56#ibcon#*before return 0, iclass 37, count 0 2006.257.18:00:43.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:43.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:43.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:00:43.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:00:43.56$vck44/valo=4,624.99 2006.257.18:00:43.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.18:00:43.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.18:00:43.56#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:43.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:43.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:43.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:43.56#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:00:43.56#ibcon#first serial, iclass 39, count 0 2006.257.18:00:43.56#ibcon#enter sib2, iclass 39, count 0 2006.257.18:00:43.56#ibcon#flushed, iclass 39, count 0 2006.257.18:00:43.56#ibcon#about to write, iclass 39, count 0 2006.257.18:00:43.56#ibcon#wrote, iclass 39, count 0 2006.257.18:00:43.56#ibcon#about to read 3, iclass 39, count 0 2006.257.18:00:43.58#ibcon#read 3, iclass 39, count 0 2006.257.18:00:43.58#ibcon#about to read 4, iclass 39, count 0 2006.257.18:00:43.58#ibcon#read 4, iclass 39, count 0 2006.257.18:00:43.58#ibcon#about to read 5, iclass 39, count 0 2006.257.18:00:43.58#ibcon#read 5, iclass 39, count 0 2006.257.18:00:43.58#ibcon#about to read 6, iclass 39, count 0 2006.257.18:00:43.58#ibcon#read 6, iclass 39, count 0 2006.257.18:00:43.58#ibcon#end of sib2, iclass 39, count 0 2006.257.18:00:43.58#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:00:43.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:00:43.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:00:43.58#ibcon#*before write, iclass 39, count 0 2006.257.18:00:43.58#ibcon#enter sib2, iclass 39, count 0 2006.257.18:00:43.58#ibcon#flushed, iclass 39, count 0 2006.257.18:00:43.58#ibcon#about to write, iclass 39, count 0 2006.257.18:00:43.58#ibcon#wrote, iclass 39, count 0 2006.257.18:00:43.58#ibcon#about to read 3, iclass 39, count 0 2006.257.18:00:43.62#ibcon#read 3, iclass 39, count 0 2006.257.18:00:43.62#ibcon#about to read 4, iclass 39, count 0 2006.257.18:00:43.62#ibcon#read 4, iclass 39, count 0 2006.257.18:00:43.62#ibcon#about to read 5, iclass 39, count 0 2006.257.18:00:43.62#ibcon#read 5, iclass 39, count 0 2006.257.18:00:43.62#ibcon#about to read 6, iclass 39, count 0 2006.257.18:00:43.62#ibcon#read 6, iclass 39, count 0 2006.257.18:00:43.62#ibcon#end of sib2, iclass 39, count 0 2006.257.18:00:43.62#ibcon#*after write, iclass 39, count 0 2006.257.18:00:43.62#ibcon#*before return 0, iclass 39, count 0 2006.257.18:00:43.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:43.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:43.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:00:43.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:00:43.62$vck44/va=4,7 2006.257.18:00:43.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.18:00:43.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.18:00:43.62#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:43.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:43.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:43.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:43.68#ibcon#enter wrdev, iclass 3, count 2 2006.257.18:00:43.68#ibcon#first serial, iclass 3, count 2 2006.257.18:00:43.68#ibcon#enter sib2, iclass 3, count 2 2006.257.18:00:43.68#ibcon#flushed, iclass 3, count 2 2006.257.18:00:43.68#ibcon#about to write, iclass 3, count 2 2006.257.18:00:43.68#ibcon#wrote, iclass 3, count 2 2006.257.18:00:43.68#ibcon#about to read 3, iclass 3, count 2 2006.257.18:00:43.70#ibcon#read 3, iclass 3, count 2 2006.257.18:00:43.70#ibcon#about to read 4, iclass 3, count 2 2006.257.18:00:43.70#ibcon#read 4, iclass 3, count 2 2006.257.18:00:43.70#ibcon#about to read 5, iclass 3, count 2 2006.257.18:00:43.70#ibcon#read 5, iclass 3, count 2 2006.257.18:00:43.70#ibcon#about to read 6, iclass 3, count 2 2006.257.18:00:43.70#ibcon#read 6, iclass 3, count 2 2006.257.18:00:43.70#ibcon#end of sib2, iclass 3, count 2 2006.257.18:00:43.70#ibcon#*mode == 0, iclass 3, count 2 2006.257.18:00:43.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.18:00:43.70#ibcon#[25=AT04-07\r\n] 2006.257.18:00:43.70#ibcon#*before write, iclass 3, count 2 2006.257.18:00:43.70#ibcon#enter sib2, iclass 3, count 2 2006.257.18:00:43.70#ibcon#flushed, iclass 3, count 2 2006.257.18:00:43.70#ibcon#about to write, iclass 3, count 2 2006.257.18:00:43.70#ibcon#wrote, iclass 3, count 2 2006.257.18:00:43.70#ibcon#about to read 3, iclass 3, count 2 2006.257.18:00:43.73#ibcon#read 3, iclass 3, count 2 2006.257.18:00:43.73#ibcon#about to read 4, iclass 3, count 2 2006.257.18:00:43.73#ibcon#read 4, iclass 3, count 2 2006.257.18:00:43.73#ibcon#about to read 5, iclass 3, count 2 2006.257.18:00:43.73#ibcon#read 5, iclass 3, count 2 2006.257.18:00:43.73#ibcon#about to read 6, iclass 3, count 2 2006.257.18:00:43.73#ibcon#read 6, iclass 3, count 2 2006.257.18:00:43.73#ibcon#end of sib2, iclass 3, count 2 2006.257.18:00:43.73#ibcon#*after write, iclass 3, count 2 2006.257.18:00:43.73#ibcon#*before return 0, iclass 3, count 2 2006.257.18:00:43.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:43.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:43.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.18:00:43.73#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:43.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:43.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:43.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:43.85#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:00:43.85#ibcon#first serial, iclass 3, count 0 2006.257.18:00:43.85#ibcon#enter sib2, iclass 3, count 0 2006.257.18:00:43.85#ibcon#flushed, iclass 3, count 0 2006.257.18:00:43.85#ibcon#about to write, iclass 3, count 0 2006.257.18:00:43.85#ibcon#wrote, iclass 3, count 0 2006.257.18:00:43.85#ibcon#about to read 3, iclass 3, count 0 2006.257.18:00:43.87#ibcon#read 3, iclass 3, count 0 2006.257.18:00:43.87#ibcon#about to read 4, iclass 3, count 0 2006.257.18:00:43.87#ibcon#read 4, iclass 3, count 0 2006.257.18:00:43.87#ibcon#about to read 5, iclass 3, count 0 2006.257.18:00:43.87#ibcon#read 5, iclass 3, count 0 2006.257.18:00:43.87#ibcon#about to read 6, iclass 3, count 0 2006.257.18:00:43.87#ibcon#read 6, iclass 3, count 0 2006.257.18:00:43.87#ibcon#end of sib2, iclass 3, count 0 2006.257.18:00:43.87#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:00:43.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:00:43.87#ibcon#[25=USB\r\n] 2006.257.18:00:43.87#ibcon#*before write, iclass 3, count 0 2006.257.18:00:43.87#ibcon#enter sib2, iclass 3, count 0 2006.257.18:00:43.87#ibcon#flushed, iclass 3, count 0 2006.257.18:00:43.87#ibcon#about to write, iclass 3, count 0 2006.257.18:00:43.87#ibcon#wrote, iclass 3, count 0 2006.257.18:00:43.87#ibcon#about to read 3, iclass 3, count 0 2006.257.18:00:43.90#ibcon#read 3, iclass 3, count 0 2006.257.18:00:43.90#ibcon#about to read 4, iclass 3, count 0 2006.257.18:00:43.90#ibcon#read 4, iclass 3, count 0 2006.257.18:00:43.90#ibcon#about to read 5, iclass 3, count 0 2006.257.18:00:43.90#ibcon#read 5, iclass 3, count 0 2006.257.18:00:43.90#ibcon#about to read 6, iclass 3, count 0 2006.257.18:00:43.90#ibcon#read 6, iclass 3, count 0 2006.257.18:00:43.90#ibcon#end of sib2, iclass 3, count 0 2006.257.18:00:43.90#ibcon#*after write, iclass 3, count 0 2006.257.18:00:43.90#ibcon#*before return 0, iclass 3, count 0 2006.257.18:00:43.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:43.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:43.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:00:43.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:00:43.90$vck44/valo=5,734.99 2006.257.18:00:43.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.18:00:43.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.18:00:43.90#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:43.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:43.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:43.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:43.90#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:00:43.90#ibcon#first serial, iclass 5, count 0 2006.257.18:00:43.90#ibcon#enter sib2, iclass 5, count 0 2006.257.18:00:43.90#ibcon#flushed, iclass 5, count 0 2006.257.18:00:43.90#ibcon#about to write, iclass 5, count 0 2006.257.18:00:43.90#ibcon#wrote, iclass 5, count 0 2006.257.18:00:43.90#ibcon#about to read 3, iclass 5, count 0 2006.257.18:00:43.92#ibcon#read 3, iclass 5, count 0 2006.257.18:00:43.92#ibcon#about to read 4, iclass 5, count 0 2006.257.18:00:43.92#ibcon#read 4, iclass 5, count 0 2006.257.18:00:43.92#ibcon#about to read 5, iclass 5, count 0 2006.257.18:00:43.92#ibcon#read 5, iclass 5, count 0 2006.257.18:00:43.92#ibcon#about to read 6, iclass 5, count 0 2006.257.18:00:43.92#ibcon#read 6, iclass 5, count 0 2006.257.18:00:43.92#ibcon#end of sib2, iclass 5, count 0 2006.257.18:00:43.92#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:00:43.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:00:43.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:00:43.92#ibcon#*before write, iclass 5, count 0 2006.257.18:00:43.92#ibcon#enter sib2, iclass 5, count 0 2006.257.18:00:43.92#ibcon#flushed, iclass 5, count 0 2006.257.18:00:43.92#ibcon#about to write, iclass 5, count 0 2006.257.18:00:43.92#ibcon#wrote, iclass 5, count 0 2006.257.18:00:43.92#ibcon#about to read 3, iclass 5, count 0 2006.257.18:00:43.96#ibcon#read 3, iclass 5, count 0 2006.257.18:00:43.96#ibcon#about to read 4, iclass 5, count 0 2006.257.18:00:43.96#ibcon#read 4, iclass 5, count 0 2006.257.18:00:43.96#ibcon#about to read 5, iclass 5, count 0 2006.257.18:00:43.96#ibcon#read 5, iclass 5, count 0 2006.257.18:00:43.96#ibcon#about to read 6, iclass 5, count 0 2006.257.18:00:43.96#ibcon#read 6, iclass 5, count 0 2006.257.18:00:43.96#ibcon#end of sib2, iclass 5, count 0 2006.257.18:00:43.96#ibcon#*after write, iclass 5, count 0 2006.257.18:00:43.96#ibcon#*before return 0, iclass 5, count 0 2006.257.18:00:43.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:43.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:43.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:00:43.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:00:43.96$vck44/va=5,4 2006.257.18:00:43.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.18:00:43.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.18:00:43.96#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:43.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:44.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:44.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:44.02#ibcon#enter wrdev, iclass 7, count 2 2006.257.18:00:44.02#ibcon#first serial, iclass 7, count 2 2006.257.18:00:44.02#ibcon#enter sib2, iclass 7, count 2 2006.257.18:00:44.02#ibcon#flushed, iclass 7, count 2 2006.257.18:00:44.02#ibcon#about to write, iclass 7, count 2 2006.257.18:00:44.02#ibcon#wrote, iclass 7, count 2 2006.257.18:00:44.02#ibcon#about to read 3, iclass 7, count 2 2006.257.18:00:44.04#ibcon#read 3, iclass 7, count 2 2006.257.18:00:44.04#ibcon#about to read 4, iclass 7, count 2 2006.257.18:00:44.04#ibcon#read 4, iclass 7, count 2 2006.257.18:00:44.04#ibcon#about to read 5, iclass 7, count 2 2006.257.18:00:44.04#ibcon#read 5, iclass 7, count 2 2006.257.18:00:44.04#ibcon#about to read 6, iclass 7, count 2 2006.257.18:00:44.04#ibcon#read 6, iclass 7, count 2 2006.257.18:00:44.04#ibcon#end of sib2, iclass 7, count 2 2006.257.18:00:44.04#ibcon#*mode == 0, iclass 7, count 2 2006.257.18:00:44.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.18:00:44.04#ibcon#[25=AT05-04\r\n] 2006.257.18:00:44.04#ibcon#*before write, iclass 7, count 2 2006.257.18:00:44.04#ibcon#enter sib2, iclass 7, count 2 2006.257.18:00:44.04#ibcon#flushed, iclass 7, count 2 2006.257.18:00:44.04#ibcon#about to write, iclass 7, count 2 2006.257.18:00:44.04#ibcon#wrote, iclass 7, count 2 2006.257.18:00:44.04#ibcon#about to read 3, iclass 7, count 2 2006.257.18:00:44.07#ibcon#read 3, iclass 7, count 2 2006.257.18:00:44.07#ibcon#about to read 4, iclass 7, count 2 2006.257.18:00:44.07#ibcon#read 4, iclass 7, count 2 2006.257.18:00:44.07#ibcon#about to read 5, iclass 7, count 2 2006.257.18:00:44.07#ibcon#read 5, iclass 7, count 2 2006.257.18:00:44.07#ibcon#about to read 6, iclass 7, count 2 2006.257.18:00:44.07#ibcon#read 6, iclass 7, count 2 2006.257.18:00:44.07#ibcon#end of sib2, iclass 7, count 2 2006.257.18:00:44.07#ibcon#*after write, iclass 7, count 2 2006.257.18:00:44.07#ibcon#*before return 0, iclass 7, count 2 2006.257.18:00:44.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:44.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:44.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.18:00:44.07#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:44.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:44.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:44.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:44.19#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:00:44.19#ibcon#first serial, iclass 7, count 0 2006.257.18:00:44.19#ibcon#enter sib2, iclass 7, count 0 2006.257.18:00:44.19#ibcon#flushed, iclass 7, count 0 2006.257.18:00:44.19#ibcon#about to write, iclass 7, count 0 2006.257.18:00:44.19#ibcon#wrote, iclass 7, count 0 2006.257.18:00:44.19#ibcon#about to read 3, iclass 7, count 0 2006.257.18:00:44.21#ibcon#read 3, iclass 7, count 0 2006.257.18:00:44.21#ibcon#about to read 4, iclass 7, count 0 2006.257.18:00:44.21#ibcon#read 4, iclass 7, count 0 2006.257.18:00:44.21#ibcon#about to read 5, iclass 7, count 0 2006.257.18:00:44.21#ibcon#read 5, iclass 7, count 0 2006.257.18:00:44.21#ibcon#about to read 6, iclass 7, count 0 2006.257.18:00:44.21#ibcon#read 6, iclass 7, count 0 2006.257.18:00:44.21#ibcon#end of sib2, iclass 7, count 0 2006.257.18:00:44.21#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:00:44.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:00:44.21#ibcon#[25=USB\r\n] 2006.257.18:00:44.21#ibcon#*before write, iclass 7, count 0 2006.257.18:00:44.21#ibcon#enter sib2, iclass 7, count 0 2006.257.18:00:44.21#ibcon#flushed, iclass 7, count 0 2006.257.18:00:44.21#ibcon#about to write, iclass 7, count 0 2006.257.18:00:44.21#ibcon#wrote, iclass 7, count 0 2006.257.18:00:44.21#ibcon#about to read 3, iclass 7, count 0 2006.257.18:00:44.24#ibcon#read 3, iclass 7, count 0 2006.257.18:00:44.24#ibcon#about to read 4, iclass 7, count 0 2006.257.18:00:44.24#ibcon#read 4, iclass 7, count 0 2006.257.18:00:44.24#ibcon#about to read 5, iclass 7, count 0 2006.257.18:00:44.24#ibcon#read 5, iclass 7, count 0 2006.257.18:00:44.24#ibcon#about to read 6, iclass 7, count 0 2006.257.18:00:44.24#ibcon#read 6, iclass 7, count 0 2006.257.18:00:44.24#ibcon#end of sib2, iclass 7, count 0 2006.257.18:00:44.24#ibcon#*after write, iclass 7, count 0 2006.257.18:00:44.24#ibcon#*before return 0, iclass 7, count 0 2006.257.18:00:44.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:44.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:44.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:00:44.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:00:44.24$vck44/valo=6,814.99 2006.257.18:00:44.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.18:00:44.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.18:00:44.24#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:44.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:44.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:44.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:44.24#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:00:44.24#ibcon#first serial, iclass 11, count 0 2006.257.18:00:44.24#ibcon#enter sib2, iclass 11, count 0 2006.257.18:00:44.24#ibcon#flushed, iclass 11, count 0 2006.257.18:00:44.24#ibcon#about to write, iclass 11, count 0 2006.257.18:00:44.24#ibcon#wrote, iclass 11, count 0 2006.257.18:00:44.24#ibcon#about to read 3, iclass 11, count 0 2006.257.18:00:44.26#ibcon#read 3, iclass 11, count 0 2006.257.18:00:44.26#ibcon#about to read 4, iclass 11, count 0 2006.257.18:00:44.26#ibcon#read 4, iclass 11, count 0 2006.257.18:00:44.26#ibcon#about to read 5, iclass 11, count 0 2006.257.18:00:44.26#ibcon#read 5, iclass 11, count 0 2006.257.18:00:44.26#ibcon#about to read 6, iclass 11, count 0 2006.257.18:00:44.26#ibcon#read 6, iclass 11, count 0 2006.257.18:00:44.26#ibcon#end of sib2, iclass 11, count 0 2006.257.18:00:44.26#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:00:44.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:00:44.26#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:00:44.26#ibcon#*before write, iclass 11, count 0 2006.257.18:00:44.26#ibcon#enter sib2, iclass 11, count 0 2006.257.18:00:44.26#ibcon#flushed, iclass 11, count 0 2006.257.18:00:44.26#ibcon#about to write, iclass 11, count 0 2006.257.18:00:44.26#ibcon#wrote, iclass 11, count 0 2006.257.18:00:44.26#ibcon#about to read 3, iclass 11, count 0 2006.257.18:00:44.30#ibcon#read 3, iclass 11, count 0 2006.257.18:00:44.30#ibcon#about to read 4, iclass 11, count 0 2006.257.18:00:44.30#ibcon#read 4, iclass 11, count 0 2006.257.18:00:44.30#ibcon#about to read 5, iclass 11, count 0 2006.257.18:00:44.30#ibcon#read 5, iclass 11, count 0 2006.257.18:00:44.30#ibcon#about to read 6, iclass 11, count 0 2006.257.18:00:44.30#ibcon#read 6, iclass 11, count 0 2006.257.18:00:44.30#ibcon#end of sib2, iclass 11, count 0 2006.257.18:00:44.30#ibcon#*after write, iclass 11, count 0 2006.257.18:00:44.30#ibcon#*before return 0, iclass 11, count 0 2006.257.18:00:44.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:44.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:44.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:00:44.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:00:44.30$vck44/va=6,4 2006.257.18:00:44.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.18:00:44.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.18:00:44.30#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:44.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:44.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:44.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:44.36#ibcon#enter wrdev, iclass 13, count 2 2006.257.18:00:44.36#ibcon#first serial, iclass 13, count 2 2006.257.18:00:44.36#ibcon#enter sib2, iclass 13, count 2 2006.257.18:00:44.36#ibcon#flushed, iclass 13, count 2 2006.257.18:00:44.36#ibcon#about to write, iclass 13, count 2 2006.257.18:00:44.36#ibcon#wrote, iclass 13, count 2 2006.257.18:00:44.36#ibcon#about to read 3, iclass 13, count 2 2006.257.18:00:44.38#ibcon#read 3, iclass 13, count 2 2006.257.18:00:44.38#ibcon#about to read 4, iclass 13, count 2 2006.257.18:00:44.38#ibcon#read 4, iclass 13, count 2 2006.257.18:00:44.38#ibcon#about to read 5, iclass 13, count 2 2006.257.18:00:44.38#ibcon#read 5, iclass 13, count 2 2006.257.18:00:44.38#ibcon#about to read 6, iclass 13, count 2 2006.257.18:00:44.38#ibcon#read 6, iclass 13, count 2 2006.257.18:00:44.38#ibcon#end of sib2, iclass 13, count 2 2006.257.18:00:44.38#ibcon#*mode == 0, iclass 13, count 2 2006.257.18:00:44.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.18:00:44.38#ibcon#[25=AT06-04\r\n] 2006.257.18:00:44.38#ibcon#*before write, iclass 13, count 2 2006.257.18:00:44.38#ibcon#enter sib2, iclass 13, count 2 2006.257.18:00:44.38#ibcon#flushed, iclass 13, count 2 2006.257.18:00:44.38#ibcon#about to write, iclass 13, count 2 2006.257.18:00:44.38#ibcon#wrote, iclass 13, count 2 2006.257.18:00:44.38#ibcon#about to read 3, iclass 13, count 2 2006.257.18:00:44.41#ibcon#read 3, iclass 13, count 2 2006.257.18:00:44.41#ibcon#about to read 4, iclass 13, count 2 2006.257.18:00:44.41#ibcon#read 4, iclass 13, count 2 2006.257.18:00:44.41#ibcon#about to read 5, iclass 13, count 2 2006.257.18:00:44.41#ibcon#read 5, iclass 13, count 2 2006.257.18:00:44.41#ibcon#about to read 6, iclass 13, count 2 2006.257.18:00:44.41#ibcon#read 6, iclass 13, count 2 2006.257.18:00:44.41#ibcon#end of sib2, iclass 13, count 2 2006.257.18:00:44.41#ibcon#*after write, iclass 13, count 2 2006.257.18:00:44.41#ibcon#*before return 0, iclass 13, count 2 2006.257.18:00:44.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:44.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:44.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.18:00:44.41#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:44.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:44.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:44.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:44.53#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:00:44.53#ibcon#first serial, iclass 13, count 0 2006.257.18:00:44.53#ibcon#enter sib2, iclass 13, count 0 2006.257.18:00:44.53#ibcon#flushed, iclass 13, count 0 2006.257.18:00:44.53#ibcon#about to write, iclass 13, count 0 2006.257.18:00:44.53#ibcon#wrote, iclass 13, count 0 2006.257.18:00:44.53#ibcon#about to read 3, iclass 13, count 0 2006.257.18:00:44.55#ibcon#read 3, iclass 13, count 0 2006.257.18:00:44.55#ibcon#about to read 4, iclass 13, count 0 2006.257.18:00:44.55#ibcon#read 4, iclass 13, count 0 2006.257.18:00:44.55#ibcon#about to read 5, iclass 13, count 0 2006.257.18:00:44.55#ibcon#read 5, iclass 13, count 0 2006.257.18:00:44.55#ibcon#about to read 6, iclass 13, count 0 2006.257.18:00:44.55#ibcon#read 6, iclass 13, count 0 2006.257.18:00:44.55#ibcon#end of sib2, iclass 13, count 0 2006.257.18:00:44.55#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:00:44.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:00:44.55#ibcon#[25=USB\r\n] 2006.257.18:00:44.55#ibcon#*before write, iclass 13, count 0 2006.257.18:00:44.55#ibcon#enter sib2, iclass 13, count 0 2006.257.18:00:44.55#ibcon#flushed, iclass 13, count 0 2006.257.18:00:44.55#ibcon#about to write, iclass 13, count 0 2006.257.18:00:44.55#ibcon#wrote, iclass 13, count 0 2006.257.18:00:44.55#ibcon#about to read 3, iclass 13, count 0 2006.257.18:00:44.58#ibcon#read 3, iclass 13, count 0 2006.257.18:00:44.58#ibcon#about to read 4, iclass 13, count 0 2006.257.18:00:44.58#ibcon#read 4, iclass 13, count 0 2006.257.18:00:44.58#ibcon#about to read 5, iclass 13, count 0 2006.257.18:00:44.58#ibcon#read 5, iclass 13, count 0 2006.257.18:00:44.58#ibcon#about to read 6, iclass 13, count 0 2006.257.18:00:44.58#ibcon#read 6, iclass 13, count 0 2006.257.18:00:44.58#ibcon#end of sib2, iclass 13, count 0 2006.257.18:00:44.58#ibcon#*after write, iclass 13, count 0 2006.257.18:00:44.58#ibcon#*before return 0, iclass 13, count 0 2006.257.18:00:44.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:44.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:44.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:00:44.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:00:44.58$vck44/valo=7,864.99 2006.257.18:00:44.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.18:00:44.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.18:00:44.58#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:44.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:44.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:44.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:44.58#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:00:44.58#ibcon#first serial, iclass 15, count 0 2006.257.18:00:44.58#ibcon#enter sib2, iclass 15, count 0 2006.257.18:00:44.58#ibcon#flushed, iclass 15, count 0 2006.257.18:00:44.58#ibcon#about to write, iclass 15, count 0 2006.257.18:00:44.58#ibcon#wrote, iclass 15, count 0 2006.257.18:00:44.58#ibcon#about to read 3, iclass 15, count 0 2006.257.18:00:44.60#ibcon#read 3, iclass 15, count 0 2006.257.18:00:44.60#ibcon#about to read 4, iclass 15, count 0 2006.257.18:00:44.60#ibcon#read 4, iclass 15, count 0 2006.257.18:00:44.60#ibcon#about to read 5, iclass 15, count 0 2006.257.18:00:44.60#ibcon#read 5, iclass 15, count 0 2006.257.18:00:44.60#ibcon#about to read 6, iclass 15, count 0 2006.257.18:00:44.60#ibcon#read 6, iclass 15, count 0 2006.257.18:00:44.60#ibcon#end of sib2, iclass 15, count 0 2006.257.18:00:44.60#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:00:44.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:00:44.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:00:44.60#ibcon#*before write, iclass 15, count 0 2006.257.18:00:44.60#ibcon#enter sib2, iclass 15, count 0 2006.257.18:00:44.60#ibcon#flushed, iclass 15, count 0 2006.257.18:00:44.60#ibcon#about to write, iclass 15, count 0 2006.257.18:00:44.60#ibcon#wrote, iclass 15, count 0 2006.257.18:00:44.60#ibcon#about to read 3, iclass 15, count 0 2006.257.18:00:44.64#ibcon#read 3, iclass 15, count 0 2006.257.18:00:44.64#ibcon#about to read 4, iclass 15, count 0 2006.257.18:00:44.64#ibcon#read 4, iclass 15, count 0 2006.257.18:00:44.64#ibcon#about to read 5, iclass 15, count 0 2006.257.18:00:44.64#ibcon#read 5, iclass 15, count 0 2006.257.18:00:44.64#ibcon#about to read 6, iclass 15, count 0 2006.257.18:00:44.64#ibcon#read 6, iclass 15, count 0 2006.257.18:00:44.64#ibcon#end of sib2, iclass 15, count 0 2006.257.18:00:44.64#ibcon#*after write, iclass 15, count 0 2006.257.18:00:44.64#ibcon#*before return 0, iclass 15, count 0 2006.257.18:00:44.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:44.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:44.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:00:44.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:00:44.64$vck44/va=7,4 2006.257.18:00:44.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.18:00:44.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.18:00:44.64#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:44.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:44.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:44.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:44.70#ibcon#enter wrdev, iclass 17, count 2 2006.257.18:00:44.70#ibcon#first serial, iclass 17, count 2 2006.257.18:00:44.70#ibcon#enter sib2, iclass 17, count 2 2006.257.18:00:44.70#ibcon#flushed, iclass 17, count 2 2006.257.18:00:44.70#ibcon#about to write, iclass 17, count 2 2006.257.18:00:44.70#ibcon#wrote, iclass 17, count 2 2006.257.18:00:44.70#ibcon#about to read 3, iclass 17, count 2 2006.257.18:00:44.72#ibcon#read 3, iclass 17, count 2 2006.257.18:00:44.72#ibcon#about to read 4, iclass 17, count 2 2006.257.18:00:44.72#ibcon#read 4, iclass 17, count 2 2006.257.18:00:44.72#ibcon#about to read 5, iclass 17, count 2 2006.257.18:00:44.72#ibcon#read 5, iclass 17, count 2 2006.257.18:00:44.72#ibcon#about to read 6, iclass 17, count 2 2006.257.18:00:44.72#ibcon#read 6, iclass 17, count 2 2006.257.18:00:44.72#ibcon#end of sib2, iclass 17, count 2 2006.257.18:00:44.72#ibcon#*mode == 0, iclass 17, count 2 2006.257.18:00:44.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.18:00:44.72#ibcon#[25=AT07-04\r\n] 2006.257.18:00:44.72#ibcon#*before write, iclass 17, count 2 2006.257.18:00:44.72#ibcon#enter sib2, iclass 17, count 2 2006.257.18:00:44.72#ibcon#flushed, iclass 17, count 2 2006.257.18:00:44.72#ibcon#about to write, iclass 17, count 2 2006.257.18:00:44.72#ibcon#wrote, iclass 17, count 2 2006.257.18:00:44.72#ibcon#about to read 3, iclass 17, count 2 2006.257.18:00:44.75#ibcon#read 3, iclass 17, count 2 2006.257.18:00:44.75#ibcon#about to read 4, iclass 17, count 2 2006.257.18:00:44.75#ibcon#read 4, iclass 17, count 2 2006.257.18:00:44.75#ibcon#about to read 5, iclass 17, count 2 2006.257.18:00:44.75#ibcon#read 5, iclass 17, count 2 2006.257.18:00:44.75#ibcon#about to read 6, iclass 17, count 2 2006.257.18:00:44.75#ibcon#read 6, iclass 17, count 2 2006.257.18:00:44.75#ibcon#end of sib2, iclass 17, count 2 2006.257.18:00:44.75#ibcon#*after write, iclass 17, count 2 2006.257.18:00:44.75#ibcon#*before return 0, iclass 17, count 2 2006.257.18:00:44.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:44.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:44.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.18:00:44.75#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:44.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:44.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:44.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:44.87#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:00:44.87#ibcon#first serial, iclass 17, count 0 2006.257.18:00:44.87#ibcon#enter sib2, iclass 17, count 0 2006.257.18:00:44.87#ibcon#flushed, iclass 17, count 0 2006.257.18:00:44.87#ibcon#about to write, iclass 17, count 0 2006.257.18:00:44.87#ibcon#wrote, iclass 17, count 0 2006.257.18:00:44.87#ibcon#about to read 3, iclass 17, count 0 2006.257.18:00:44.89#ibcon#read 3, iclass 17, count 0 2006.257.18:00:44.89#ibcon#about to read 4, iclass 17, count 0 2006.257.18:00:44.89#ibcon#read 4, iclass 17, count 0 2006.257.18:00:44.89#ibcon#about to read 5, iclass 17, count 0 2006.257.18:00:44.89#ibcon#read 5, iclass 17, count 0 2006.257.18:00:44.89#ibcon#about to read 6, iclass 17, count 0 2006.257.18:00:44.89#ibcon#read 6, iclass 17, count 0 2006.257.18:00:44.89#ibcon#end of sib2, iclass 17, count 0 2006.257.18:00:44.89#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:00:44.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:00:44.89#ibcon#[25=USB\r\n] 2006.257.18:00:44.89#ibcon#*before write, iclass 17, count 0 2006.257.18:00:44.89#ibcon#enter sib2, iclass 17, count 0 2006.257.18:00:44.89#ibcon#flushed, iclass 17, count 0 2006.257.18:00:44.89#ibcon#about to write, iclass 17, count 0 2006.257.18:00:44.89#ibcon#wrote, iclass 17, count 0 2006.257.18:00:44.89#ibcon#about to read 3, iclass 17, count 0 2006.257.18:00:44.92#ibcon#read 3, iclass 17, count 0 2006.257.18:00:44.92#ibcon#about to read 4, iclass 17, count 0 2006.257.18:00:44.92#ibcon#read 4, iclass 17, count 0 2006.257.18:00:44.92#ibcon#about to read 5, iclass 17, count 0 2006.257.18:00:44.92#ibcon#read 5, iclass 17, count 0 2006.257.18:00:44.92#ibcon#about to read 6, iclass 17, count 0 2006.257.18:00:44.92#ibcon#read 6, iclass 17, count 0 2006.257.18:00:44.92#ibcon#end of sib2, iclass 17, count 0 2006.257.18:00:44.92#ibcon#*after write, iclass 17, count 0 2006.257.18:00:44.92#ibcon#*before return 0, iclass 17, count 0 2006.257.18:00:44.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:44.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:44.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:00:44.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:00:44.92$vck44/valo=8,884.99 2006.257.18:00:44.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.18:00:44.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.18:00:44.92#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:44.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:44.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:44.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:44.92#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:00:44.92#ibcon#first serial, iclass 19, count 0 2006.257.18:00:44.92#ibcon#enter sib2, iclass 19, count 0 2006.257.18:00:44.92#ibcon#flushed, iclass 19, count 0 2006.257.18:00:44.92#ibcon#about to write, iclass 19, count 0 2006.257.18:00:44.92#ibcon#wrote, iclass 19, count 0 2006.257.18:00:44.92#ibcon#about to read 3, iclass 19, count 0 2006.257.18:00:44.94#ibcon#read 3, iclass 19, count 0 2006.257.18:00:44.94#ibcon#about to read 4, iclass 19, count 0 2006.257.18:00:44.94#ibcon#read 4, iclass 19, count 0 2006.257.18:00:44.94#ibcon#about to read 5, iclass 19, count 0 2006.257.18:00:44.94#ibcon#read 5, iclass 19, count 0 2006.257.18:00:44.94#ibcon#about to read 6, iclass 19, count 0 2006.257.18:00:44.94#ibcon#read 6, iclass 19, count 0 2006.257.18:00:44.94#ibcon#end of sib2, iclass 19, count 0 2006.257.18:00:44.94#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:00:44.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:00:44.94#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:00:44.94#ibcon#*before write, iclass 19, count 0 2006.257.18:00:44.94#ibcon#enter sib2, iclass 19, count 0 2006.257.18:00:44.94#ibcon#flushed, iclass 19, count 0 2006.257.18:00:44.94#ibcon#about to write, iclass 19, count 0 2006.257.18:00:44.94#ibcon#wrote, iclass 19, count 0 2006.257.18:00:44.94#ibcon#about to read 3, iclass 19, count 0 2006.257.18:00:44.98#ibcon#read 3, iclass 19, count 0 2006.257.18:00:44.98#ibcon#about to read 4, iclass 19, count 0 2006.257.18:00:44.98#ibcon#read 4, iclass 19, count 0 2006.257.18:00:44.98#ibcon#about to read 5, iclass 19, count 0 2006.257.18:00:44.98#ibcon#read 5, iclass 19, count 0 2006.257.18:00:44.98#ibcon#about to read 6, iclass 19, count 0 2006.257.18:00:44.98#ibcon#read 6, iclass 19, count 0 2006.257.18:00:44.98#ibcon#end of sib2, iclass 19, count 0 2006.257.18:00:44.98#ibcon#*after write, iclass 19, count 0 2006.257.18:00:44.98#ibcon#*before return 0, iclass 19, count 0 2006.257.18:00:44.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:44.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:44.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:00:44.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:00:44.98$vck44/va=8,4 2006.257.18:00:44.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.18:00:44.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.18:00:44.98#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:44.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:00:45.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:00:45.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:00:45.04#ibcon#enter wrdev, iclass 21, count 2 2006.257.18:00:45.04#ibcon#first serial, iclass 21, count 2 2006.257.18:00:45.04#ibcon#enter sib2, iclass 21, count 2 2006.257.18:00:45.04#ibcon#flushed, iclass 21, count 2 2006.257.18:00:45.04#ibcon#about to write, iclass 21, count 2 2006.257.18:00:45.04#ibcon#wrote, iclass 21, count 2 2006.257.18:00:45.04#ibcon#about to read 3, iclass 21, count 2 2006.257.18:00:45.06#ibcon#read 3, iclass 21, count 2 2006.257.18:00:45.06#ibcon#about to read 4, iclass 21, count 2 2006.257.18:00:45.06#ibcon#read 4, iclass 21, count 2 2006.257.18:00:45.06#ibcon#about to read 5, iclass 21, count 2 2006.257.18:00:45.06#ibcon#read 5, iclass 21, count 2 2006.257.18:00:45.06#ibcon#about to read 6, iclass 21, count 2 2006.257.18:00:45.06#ibcon#read 6, iclass 21, count 2 2006.257.18:00:45.06#ibcon#end of sib2, iclass 21, count 2 2006.257.18:00:45.06#ibcon#*mode == 0, iclass 21, count 2 2006.257.18:00:45.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.18:00:45.06#ibcon#[25=AT08-04\r\n] 2006.257.18:00:45.06#ibcon#*before write, iclass 21, count 2 2006.257.18:00:45.06#ibcon#enter sib2, iclass 21, count 2 2006.257.18:00:45.06#ibcon#flushed, iclass 21, count 2 2006.257.18:00:45.06#ibcon#about to write, iclass 21, count 2 2006.257.18:00:45.06#ibcon#wrote, iclass 21, count 2 2006.257.18:00:45.06#ibcon#about to read 3, iclass 21, count 2 2006.257.18:00:45.09#ibcon#read 3, iclass 21, count 2 2006.257.18:00:45.09#ibcon#about to read 4, iclass 21, count 2 2006.257.18:00:45.09#ibcon#read 4, iclass 21, count 2 2006.257.18:00:45.09#ibcon#about to read 5, iclass 21, count 2 2006.257.18:00:45.09#ibcon#read 5, iclass 21, count 2 2006.257.18:00:45.09#ibcon#about to read 6, iclass 21, count 2 2006.257.18:00:45.09#ibcon#read 6, iclass 21, count 2 2006.257.18:00:45.09#ibcon#end of sib2, iclass 21, count 2 2006.257.18:00:45.09#ibcon#*after write, iclass 21, count 2 2006.257.18:00:45.09#ibcon#*before return 0, iclass 21, count 2 2006.257.18:00:45.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:00:45.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:00:45.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.18:00:45.09#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:45.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:00:45.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:00:45.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:00:45.21#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:00:45.21#ibcon#first serial, iclass 21, count 0 2006.257.18:00:45.21#ibcon#enter sib2, iclass 21, count 0 2006.257.18:00:45.21#ibcon#flushed, iclass 21, count 0 2006.257.18:00:45.21#ibcon#about to write, iclass 21, count 0 2006.257.18:00:45.21#ibcon#wrote, iclass 21, count 0 2006.257.18:00:45.21#ibcon#about to read 3, iclass 21, count 0 2006.257.18:00:45.23#ibcon#read 3, iclass 21, count 0 2006.257.18:00:45.23#ibcon#about to read 4, iclass 21, count 0 2006.257.18:00:45.23#ibcon#read 4, iclass 21, count 0 2006.257.18:00:45.23#ibcon#about to read 5, iclass 21, count 0 2006.257.18:00:45.23#ibcon#read 5, iclass 21, count 0 2006.257.18:00:45.23#ibcon#about to read 6, iclass 21, count 0 2006.257.18:00:45.23#ibcon#read 6, iclass 21, count 0 2006.257.18:00:45.23#ibcon#end of sib2, iclass 21, count 0 2006.257.18:00:45.23#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:00:45.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:00:45.23#ibcon#[25=USB\r\n] 2006.257.18:00:45.23#ibcon#*before write, iclass 21, count 0 2006.257.18:00:45.23#ibcon#enter sib2, iclass 21, count 0 2006.257.18:00:45.23#ibcon#flushed, iclass 21, count 0 2006.257.18:00:45.23#ibcon#about to write, iclass 21, count 0 2006.257.18:00:45.23#ibcon#wrote, iclass 21, count 0 2006.257.18:00:45.23#ibcon#about to read 3, iclass 21, count 0 2006.257.18:00:45.26#ibcon#read 3, iclass 21, count 0 2006.257.18:00:45.26#ibcon#about to read 4, iclass 21, count 0 2006.257.18:00:45.26#ibcon#read 4, iclass 21, count 0 2006.257.18:00:45.26#ibcon#about to read 5, iclass 21, count 0 2006.257.18:00:45.26#ibcon#read 5, iclass 21, count 0 2006.257.18:00:45.26#ibcon#about to read 6, iclass 21, count 0 2006.257.18:00:45.26#ibcon#read 6, iclass 21, count 0 2006.257.18:00:45.26#ibcon#end of sib2, iclass 21, count 0 2006.257.18:00:45.26#ibcon#*after write, iclass 21, count 0 2006.257.18:00:45.26#ibcon#*before return 0, iclass 21, count 0 2006.257.18:00:45.26#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:00:45.26#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:00:45.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:00:45.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:00:45.26$vck44/vblo=1,629.99 2006.257.18:00:45.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.18:00:45.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.18:00:45.26#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:45.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:00:45.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:00:45.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:00:45.26#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:00:45.26#ibcon#first serial, iclass 23, count 0 2006.257.18:00:45.26#ibcon#enter sib2, iclass 23, count 0 2006.257.18:00:45.26#ibcon#flushed, iclass 23, count 0 2006.257.18:00:45.26#ibcon#about to write, iclass 23, count 0 2006.257.18:00:45.26#ibcon#wrote, iclass 23, count 0 2006.257.18:00:45.26#ibcon#about to read 3, iclass 23, count 0 2006.257.18:00:45.28#ibcon#read 3, iclass 23, count 0 2006.257.18:00:45.28#ibcon#about to read 4, iclass 23, count 0 2006.257.18:00:45.28#ibcon#read 4, iclass 23, count 0 2006.257.18:00:45.28#ibcon#about to read 5, iclass 23, count 0 2006.257.18:00:45.28#ibcon#read 5, iclass 23, count 0 2006.257.18:00:45.28#ibcon#about to read 6, iclass 23, count 0 2006.257.18:00:45.28#ibcon#read 6, iclass 23, count 0 2006.257.18:00:45.28#ibcon#end of sib2, iclass 23, count 0 2006.257.18:00:45.28#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:00:45.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:00:45.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:00:45.28#ibcon#*before write, iclass 23, count 0 2006.257.18:00:45.28#ibcon#enter sib2, iclass 23, count 0 2006.257.18:00:45.28#ibcon#flushed, iclass 23, count 0 2006.257.18:00:45.28#ibcon#about to write, iclass 23, count 0 2006.257.18:00:45.28#ibcon#wrote, iclass 23, count 0 2006.257.18:00:45.28#ibcon#about to read 3, iclass 23, count 0 2006.257.18:00:45.32#ibcon#read 3, iclass 23, count 0 2006.257.18:00:45.32#ibcon#about to read 4, iclass 23, count 0 2006.257.18:00:45.32#ibcon#read 4, iclass 23, count 0 2006.257.18:00:45.32#ibcon#about to read 5, iclass 23, count 0 2006.257.18:00:45.32#ibcon#read 5, iclass 23, count 0 2006.257.18:00:45.32#ibcon#about to read 6, iclass 23, count 0 2006.257.18:00:45.32#ibcon#read 6, iclass 23, count 0 2006.257.18:00:45.32#ibcon#end of sib2, iclass 23, count 0 2006.257.18:00:45.32#ibcon#*after write, iclass 23, count 0 2006.257.18:00:45.32#ibcon#*before return 0, iclass 23, count 0 2006.257.18:00:45.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:00:45.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:00:45.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:00:45.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:00:45.32$vck44/vb=1,4 2006.257.18:00:45.32#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.18:00:45.32#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.18:00:45.32#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:45.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:00:45.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:00:45.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:00:45.32#ibcon#enter wrdev, iclass 25, count 2 2006.257.18:00:45.32#ibcon#first serial, iclass 25, count 2 2006.257.18:00:45.32#ibcon#enter sib2, iclass 25, count 2 2006.257.18:00:45.32#ibcon#flushed, iclass 25, count 2 2006.257.18:00:45.32#ibcon#about to write, iclass 25, count 2 2006.257.18:00:45.32#ibcon#wrote, iclass 25, count 2 2006.257.18:00:45.32#ibcon#about to read 3, iclass 25, count 2 2006.257.18:00:45.34#ibcon#read 3, iclass 25, count 2 2006.257.18:00:45.34#ibcon#about to read 4, iclass 25, count 2 2006.257.18:00:45.34#ibcon#read 4, iclass 25, count 2 2006.257.18:00:45.34#ibcon#about to read 5, iclass 25, count 2 2006.257.18:00:45.34#ibcon#read 5, iclass 25, count 2 2006.257.18:00:45.34#ibcon#about to read 6, iclass 25, count 2 2006.257.18:00:45.34#ibcon#read 6, iclass 25, count 2 2006.257.18:00:45.34#ibcon#end of sib2, iclass 25, count 2 2006.257.18:00:45.34#ibcon#*mode == 0, iclass 25, count 2 2006.257.18:00:45.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.18:00:45.34#ibcon#[27=AT01-04\r\n] 2006.257.18:00:45.34#ibcon#*before write, iclass 25, count 2 2006.257.18:00:45.34#ibcon#enter sib2, iclass 25, count 2 2006.257.18:00:45.34#ibcon#flushed, iclass 25, count 2 2006.257.18:00:45.34#ibcon#about to write, iclass 25, count 2 2006.257.18:00:45.34#ibcon#wrote, iclass 25, count 2 2006.257.18:00:45.34#ibcon#about to read 3, iclass 25, count 2 2006.257.18:00:45.37#ibcon#read 3, iclass 25, count 2 2006.257.18:00:45.37#ibcon#about to read 4, iclass 25, count 2 2006.257.18:00:45.37#ibcon#read 4, iclass 25, count 2 2006.257.18:00:45.37#ibcon#about to read 5, iclass 25, count 2 2006.257.18:00:45.37#ibcon#read 5, iclass 25, count 2 2006.257.18:00:45.37#ibcon#about to read 6, iclass 25, count 2 2006.257.18:00:45.37#ibcon#read 6, iclass 25, count 2 2006.257.18:00:45.37#ibcon#end of sib2, iclass 25, count 2 2006.257.18:00:45.37#ibcon#*after write, iclass 25, count 2 2006.257.18:00:45.37#ibcon#*before return 0, iclass 25, count 2 2006.257.18:00:45.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:00:45.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:00:45.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.18:00:45.37#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:45.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:00:45.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:00:45.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:00:45.49#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:00:45.49#ibcon#first serial, iclass 25, count 0 2006.257.18:00:45.49#ibcon#enter sib2, iclass 25, count 0 2006.257.18:00:45.49#ibcon#flushed, iclass 25, count 0 2006.257.18:00:45.49#ibcon#about to write, iclass 25, count 0 2006.257.18:00:45.49#ibcon#wrote, iclass 25, count 0 2006.257.18:00:45.49#ibcon#about to read 3, iclass 25, count 0 2006.257.18:00:45.51#ibcon#read 3, iclass 25, count 0 2006.257.18:00:45.51#ibcon#about to read 4, iclass 25, count 0 2006.257.18:00:45.51#ibcon#read 4, iclass 25, count 0 2006.257.18:00:45.51#ibcon#about to read 5, iclass 25, count 0 2006.257.18:00:45.51#ibcon#read 5, iclass 25, count 0 2006.257.18:00:45.51#ibcon#about to read 6, iclass 25, count 0 2006.257.18:00:45.51#ibcon#read 6, iclass 25, count 0 2006.257.18:00:45.51#ibcon#end of sib2, iclass 25, count 0 2006.257.18:00:45.51#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:00:45.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:00:45.51#ibcon#[27=USB\r\n] 2006.257.18:00:45.51#ibcon#*before write, iclass 25, count 0 2006.257.18:00:45.51#ibcon#enter sib2, iclass 25, count 0 2006.257.18:00:45.51#ibcon#flushed, iclass 25, count 0 2006.257.18:00:45.51#ibcon#about to write, iclass 25, count 0 2006.257.18:00:45.51#ibcon#wrote, iclass 25, count 0 2006.257.18:00:45.51#ibcon#about to read 3, iclass 25, count 0 2006.257.18:00:45.54#ibcon#read 3, iclass 25, count 0 2006.257.18:00:45.54#ibcon#about to read 4, iclass 25, count 0 2006.257.18:00:45.54#ibcon#read 4, iclass 25, count 0 2006.257.18:00:45.54#ibcon#about to read 5, iclass 25, count 0 2006.257.18:00:45.54#ibcon#read 5, iclass 25, count 0 2006.257.18:00:45.54#ibcon#about to read 6, iclass 25, count 0 2006.257.18:00:45.54#ibcon#read 6, iclass 25, count 0 2006.257.18:00:45.54#ibcon#end of sib2, iclass 25, count 0 2006.257.18:00:45.54#ibcon#*after write, iclass 25, count 0 2006.257.18:00:45.54#ibcon#*before return 0, iclass 25, count 0 2006.257.18:00:45.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:00:45.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:00:45.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:00:45.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:00:45.54$vck44/vblo=2,634.99 2006.257.18:00:45.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.18:00:45.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.18:00:45.54#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:45.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:45.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:45.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:45.54#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:00:45.54#ibcon#first serial, iclass 27, count 0 2006.257.18:00:45.54#ibcon#enter sib2, iclass 27, count 0 2006.257.18:00:45.54#ibcon#flushed, iclass 27, count 0 2006.257.18:00:45.54#ibcon#about to write, iclass 27, count 0 2006.257.18:00:45.54#ibcon#wrote, iclass 27, count 0 2006.257.18:00:45.54#ibcon#about to read 3, iclass 27, count 0 2006.257.18:00:45.56#ibcon#read 3, iclass 27, count 0 2006.257.18:00:45.56#ibcon#about to read 4, iclass 27, count 0 2006.257.18:00:45.56#ibcon#read 4, iclass 27, count 0 2006.257.18:00:45.56#ibcon#about to read 5, iclass 27, count 0 2006.257.18:00:45.56#ibcon#read 5, iclass 27, count 0 2006.257.18:00:45.56#ibcon#about to read 6, iclass 27, count 0 2006.257.18:00:45.56#ibcon#read 6, iclass 27, count 0 2006.257.18:00:45.56#ibcon#end of sib2, iclass 27, count 0 2006.257.18:00:45.56#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:00:45.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:00:45.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:00:45.56#ibcon#*before write, iclass 27, count 0 2006.257.18:00:45.56#ibcon#enter sib2, iclass 27, count 0 2006.257.18:00:45.56#ibcon#flushed, iclass 27, count 0 2006.257.18:00:45.56#ibcon#about to write, iclass 27, count 0 2006.257.18:00:45.56#ibcon#wrote, iclass 27, count 0 2006.257.18:00:45.56#ibcon#about to read 3, iclass 27, count 0 2006.257.18:00:45.60#ibcon#read 3, iclass 27, count 0 2006.257.18:00:45.60#ibcon#about to read 4, iclass 27, count 0 2006.257.18:00:45.60#ibcon#read 4, iclass 27, count 0 2006.257.18:00:45.60#ibcon#about to read 5, iclass 27, count 0 2006.257.18:00:45.60#ibcon#read 5, iclass 27, count 0 2006.257.18:00:45.60#ibcon#about to read 6, iclass 27, count 0 2006.257.18:00:45.60#ibcon#read 6, iclass 27, count 0 2006.257.18:00:45.60#ibcon#end of sib2, iclass 27, count 0 2006.257.18:00:45.60#ibcon#*after write, iclass 27, count 0 2006.257.18:00:45.60#ibcon#*before return 0, iclass 27, count 0 2006.257.18:00:45.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:45.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:00:45.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:00:45.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:00:45.60$vck44/vb=2,5 2006.257.18:00:45.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.18:00:45.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.18:00:45.60#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:45.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:45.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:45.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:45.66#ibcon#enter wrdev, iclass 29, count 2 2006.257.18:00:45.66#ibcon#first serial, iclass 29, count 2 2006.257.18:00:45.66#ibcon#enter sib2, iclass 29, count 2 2006.257.18:00:45.66#ibcon#flushed, iclass 29, count 2 2006.257.18:00:45.66#ibcon#about to write, iclass 29, count 2 2006.257.18:00:45.66#ibcon#wrote, iclass 29, count 2 2006.257.18:00:45.66#ibcon#about to read 3, iclass 29, count 2 2006.257.18:00:45.68#ibcon#read 3, iclass 29, count 2 2006.257.18:00:45.68#ibcon#about to read 4, iclass 29, count 2 2006.257.18:00:45.68#ibcon#read 4, iclass 29, count 2 2006.257.18:00:45.68#ibcon#about to read 5, iclass 29, count 2 2006.257.18:00:45.68#ibcon#read 5, iclass 29, count 2 2006.257.18:00:45.68#ibcon#about to read 6, iclass 29, count 2 2006.257.18:00:45.68#ibcon#read 6, iclass 29, count 2 2006.257.18:00:45.68#ibcon#end of sib2, iclass 29, count 2 2006.257.18:00:45.68#ibcon#*mode == 0, iclass 29, count 2 2006.257.18:00:45.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.18:00:45.68#ibcon#[27=AT02-05\r\n] 2006.257.18:00:45.68#ibcon#*before write, iclass 29, count 2 2006.257.18:00:45.68#ibcon#enter sib2, iclass 29, count 2 2006.257.18:00:45.68#ibcon#flushed, iclass 29, count 2 2006.257.18:00:45.68#ibcon#about to write, iclass 29, count 2 2006.257.18:00:45.68#ibcon#wrote, iclass 29, count 2 2006.257.18:00:45.68#ibcon#about to read 3, iclass 29, count 2 2006.257.18:00:45.71#ibcon#read 3, iclass 29, count 2 2006.257.18:00:45.71#ibcon#about to read 4, iclass 29, count 2 2006.257.18:00:45.71#ibcon#read 4, iclass 29, count 2 2006.257.18:00:45.71#ibcon#about to read 5, iclass 29, count 2 2006.257.18:00:45.71#ibcon#read 5, iclass 29, count 2 2006.257.18:00:45.71#ibcon#about to read 6, iclass 29, count 2 2006.257.18:00:45.71#ibcon#read 6, iclass 29, count 2 2006.257.18:00:45.71#ibcon#end of sib2, iclass 29, count 2 2006.257.18:00:45.71#ibcon#*after write, iclass 29, count 2 2006.257.18:00:45.71#ibcon#*before return 0, iclass 29, count 2 2006.257.18:00:45.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:45.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:00:45.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.18:00:45.71#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:45.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:45.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:45.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:45.83#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:00:45.83#ibcon#first serial, iclass 29, count 0 2006.257.18:00:45.83#ibcon#enter sib2, iclass 29, count 0 2006.257.18:00:45.83#ibcon#flushed, iclass 29, count 0 2006.257.18:00:45.83#ibcon#about to write, iclass 29, count 0 2006.257.18:00:45.83#ibcon#wrote, iclass 29, count 0 2006.257.18:00:45.83#ibcon#about to read 3, iclass 29, count 0 2006.257.18:00:45.85#ibcon#read 3, iclass 29, count 0 2006.257.18:00:45.85#ibcon#about to read 4, iclass 29, count 0 2006.257.18:00:45.85#ibcon#read 4, iclass 29, count 0 2006.257.18:00:45.85#ibcon#about to read 5, iclass 29, count 0 2006.257.18:00:45.85#ibcon#read 5, iclass 29, count 0 2006.257.18:00:45.85#ibcon#about to read 6, iclass 29, count 0 2006.257.18:00:45.85#ibcon#read 6, iclass 29, count 0 2006.257.18:00:45.85#ibcon#end of sib2, iclass 29, count 0 2006.257.18:00:45.85#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:00:45.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:00:45.85#ibcon#[27=USB\r\n] 2006.257.18:00:45.85#ibcon#*before write, iclass 29, count 0 2006.257.18:00:45.85#ibcon#enter sib2, iclass 29, count 0 2006.257.18:00:45.85#ibcon#flushed, iclass 29, count 0 2006.257.18:00:45.85#ibcon#about to write, iclass 29, count 0 2006.257.18:00:45.85#ibcon#wrote, iclass 29, count 0 2006.257.18:00:45.85#ibcon#about to read 3, iclass 29, count 0 2006.257.18:00:45.88#ibcon#read 3, iclass 29, count 0 2006.257.18:00:45.88#ibcon#about to read 4, iclass 29, count 0 2006.257.18:00:45.88#ibcon#read 4, iclass 29, count 0 2006.257.18:00:45.88#ibcon#about to read 5, iclass 29, count 0 2006.257.18:00:45.88#ibcon#read 5, iclass 29, count 0 2006.257.18:00:45.88#ibcon#about to read 6, iclass 29, count 0 2006.257.18:00:45.88#ibcon#read 6, iclass 29, count 0 2006.257.18:00:45.88#ibcon#end of sib2, iclass 29, count 0 2006.257.18:00:45.88#ibcon#*after write, iclass 29, count 0 2006.257.18:00:45.88#ibcon#*before return 0, iclass 29, count 0 2006.257.18:00:45.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:45.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:00:45.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:00:45.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:00:45.88$vck44/vblo=3,649.99 2006.257.18:00:45.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.18:00:45.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.18:00:45.88#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:45.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:45.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:45.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:45.88#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:00:45.88#ibcon#first serial, iclass 31, count 0 2006.257.18:00:45.88#ibcon#enter sib2, iclass 31, count 0 2006.257.18:00:45.88#ibcon#flushed, iclass 31, count 0 2006.257.18:00:45.88#ibcon#about to write, iclass 31, count 0 2006.257.18:00:45.88#ibcon#wrote, iclass 31, count 0 2006.257.18:00:45.88#ibcon#about to read 3, iclass 31, count 0 2006.257.18:00:45.90#ibcon#read 3, iclass 31, count 0 2006.257.18:00:45.90#ibcon#about to read 4, iclass 31, count 0 2006.257.18:00:45.90#ibcon#read 4, iclass 31, count 0 2006.257.18:00:45.90#ibcon#about to read 5, iclass 31, count 0 2006.257.18:00:45.90#ibcon#read 5, iclass 31, count 0 2006.257.18:00:45.90#ibcon#about to read 6, iclass 31, count 0 2006.257.18:00:45.90#ibcon#read 6, iclass 31, count 0 2006.257.18:00:45.90#ibcon#end of sib2, iclass 31, count 0 2006.257.18:00:45.90#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:00:45.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:00:45.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:00:45.90#ibcon#*before write, iclass 31, count 0 2006.257.18:00:45.90#ibcon#enter sib2, iclass 31, count 0 2006.257.18:00:45.90#ibcon#flushed, iclass 31, count 0 2006.257.18:00:45.90#ibcon#about to write, iclass 31, count 0 2006.257.18:00:45.90#ibcon#wrote, iclass 31, count 0 2006.257.18:00:45.90#ibcon#about to read 3, iclass 31, count 0 2006.257.18:00:45.94#ibcon#read 3, iclass 31, count 0 2006.257.18:00:45.94#ibcon#about to read 4, iclass 31, count 0 2006.257.18:00:45.94#ibcon#read 4, iclass 31, count 0 2006.257.18:00:45.94#ibcon#about to read 5, iclass 31, count 0 2006.257.18:00:45.94#ibcon#read 5, iclass 31, count 0 2006.257.18:00:45.94#ibcon#about to read 6, iclass 31, count 0 2006.257.18:00:45.94#ibcon#read 6, iclass 31, count 0 2006.257.18:00:45.94#ibcon#end of sib2, iclass 31, count 0 2006.257.18:00:45.94#ibcon#*after write, iclass 31, count 0 2006.257.18:00:45.94#ibcon#*before return 0, iclass 31, count 0 2006.257.18:00:45.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:45.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:00:45.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:00:45.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:00:45.94$vck44/vb=3,4 2006.257.18:00:45.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.18:00:45.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.18:00:45.94#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:45.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:46.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:46.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:46.00#ibcon#enter wrdev, iclass 33, count 2 2006.257.18:00:46.00#ibcon#first serial, iclass 33, count 2 2006.257.18:00:46.00#ibcon#enter sib2, iclass 33, count 2 2006.257.18:00:46.00#ibcon#flushed, iclass 33, count 2 2006.257.18:00:46.00#ibcon#about to write, iclass 33, count 2 2006.257.18:00:46.00#ibcon#wrote, iclass 33, count 2 2006.257.18:00:46.00#ibcon#about to read 3, iclass 33, count 2 2006.257.18:00:46.02#ibcon#read 3, iclass 33, count 2 2006.257.18:00:46.02#ibcon#about to read 4, iclass 33, count 2 2006.257.18:00:46.02#ibcon#read 4, iclass 33, count 2 2006.257.18:00:46.02#ibcon#about to read 5, iclass 33, count 2 2006.257.18:00:46.02#ibcon#read 5, iclass 33, count 2 2006.257.18:00:46.02#ibcon#about to read 6, iclass 33, count 2 2006.257.18:00:46.02#ibcon#read 6, iclass 33, count 2 2006.257.18:00:46.02#ibcon#end of sib2, iclass 33, count 2 2006.257.18:00:46.02#ibcon#*mode == 0, iclass 33, count 2 2006.257.18:00:46.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.18:00:46.02#ibcon#[27=AT03-04\r\n] 2006.257.18:00:46.02#ibcon#*before write, iclass 33, count 2 2006.257.18:00:46.02#ibcon#enter sib2, iclass 33, count 2 2006.257.18:00:46.02#ibcon#flushed, iclass 33, count 2 2006.257.18:00:46.02#ibcon#about to write, iclass 33, count 2 2006.257.18:00:46.02#ibcon#wrote, iclass 33, count 2 2006.257.18:00:46.02#ibcon#about to read 3, iclass 33, count 2 2006.257.18:00:46.05#ibcon#read 3, iclass 33, count 2 2006.257.18:00:46.05#ibcon#about to read 4, iclass 33, count 2 2006.257.18:00:46.05#ibcon#read 4, iclass 33, count 2 2006.257.18:00:46.05#ibcon#about to read 5, iclass 33, count 2 2006.257.18:00:46.05#ibcon#read 5, iclass 33, count 2 2006.257.18:00:46.05#ibcon#about to read 6, iclass 33, count 2 2006.257.18:00:46.05#ibcon#read 6, iclass 33, count 2 2006.257.18:00:46.05#ibcon#end of sib2, iclass 33, count 2 2006.257.18:00:46.05#ibcon#*after write, iclass 33, count 2 2006.257.18:00:46.05#ibcon#*before return 0, iclass 33, count 2 2006.257.18:00:46.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:46.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:00:46.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.18:00:46.05#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:46.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:46.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:46.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:46.17#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:00:46.17#ibcon#first serial, iclass 33, count 0 2006.257.18:00:46.17#ibcon#enter sib2, iclass 33, count 0 2006.257.18:00:46.17#ibcon#flushed, iclass 33, count 0 2006.257.18:00:46.17#ibcon#about to write, iclass 33, count 0 2006.257.18:00:46.17#ibcon#wrote, iclass 33, count 0 2006.257.18:00:46.17#ibcon#about to read 3, iclass 33, count 0 2006.257.18:00:46.19#ibcon#read 3, iclass 33, count 0 2006.257.18:00:46.19#ibcon#about to read 4, iclass 33, count 0 2006.257.18:00:46.19#ibcon#read 4, iclass 33, count 0 2006.257.18:00:46.19#ibcon#about to read 5, iclass 33, count 0 2006.257.18:00:46.19#ibcon#read 5, iclass 33, count 0 2006.257.18:00:46.19#ibcon#about to read 6, iclass 33, count 0 2006.257.18:00:46.19#ibcon#read 6, iclass 33, count 0 2006.257.18:00:46.19#ibcon#end of sib2, iclass 33, count 0 2006.257.18:00:46.19#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:00:46.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:00:46.19#ibcon#[27=USB\r\n] 2006.257.18:00:46.19#ibcon#*before write, iclass 33, count 0 2006.257.18:00:46.19#ibcon#enter sib2, iclass 33, count 0 2006.257.18:00:46.19#ibcon#flushed, iclass 33, count 0 2006.257.18:00:46.19#ibcon#about to write, iclass 33, count 0 2006.257.18:00:46.19#ibcon#wrote, iclass 33, count 0 2006.257.18:00:46.19#ibcon#about to read 3, iclass 33, count 0 2006.257.18:00:46.22#ibcon#read 3, iclass 33, count 0 2006.257.18:00:46.22#ibcon#about to read 4, iclass 33, count 0 2006.257.18:00:46.22#ibcon#read 4, iclass 33, count 0 2006.257.18:00:46.22#ibcon#about to read 5, iclass 33, count 0 2006.257.18:00:46.22#ibcon#read 5, iclass 33, count 0 2006.257.18:00:46.22#ibcon#about to read 6, iclass 33, count 0 2006.257.18:00:46.22#ibcon#read 6, iclass 33, count 0 2006.257.18:00:46.22#ibcon#end of sib2, iclass 33, count 0 2006.257.18:00:46.22#ibcon#*after write, iclass 33, count 0 2006.257.18:00:46.22#ibcon#*before return 0, iclass 33, count 0 2006.257.18:00:46.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:46.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:00:46.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:00:46.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:00:46.22$vck44/vblo=4,679.99 2006.257.18:00:46.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.18:00:46.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.18:00:46.22#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:46.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:46.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:46.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:46.22#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:00:46.22#ibcon#first serial, iclass 35, count 0 2006.257.18:00:46.22#ibcon#enter sib2, iclass 35, count 0 2006.257.18:00:46.22#ibcon#flushed, iclass 35, count 0 2006.257.18:00:46.22#ibcon#about to write, iclass 35, count 0 2006.257.18:00:46.22#ibcon#wrote, iclass 35, count 0 2006.257.18:00:46.22#ibcon#about to read 3, iclass 35, count 0 2006.257.18:00:46.24#ibcon#read 3, iclass 35, count 0 2006.257.18:00:46.24#ibcon#about to read 4, iclass 35, count 0 2006.257.18:00:46.24#ibcon#read 4, iclass 35, count 0 2006.257.18:00:46.24#ibcon#about to read 5, iclass 35, count 0 2006.257.18:00:46.24#ibcon#read 5, iclass 35, count 0 2006.257.18:00:46.24#ibcon#about to read 6, iclass 35, count 0 2006.257.18:00:46.24#ibcon#read 6, iclass 35, count 0 2006.257.18:00:46.24#ibcon#end of sib2, iclass 35, count 0 2006.257.18:00:46.24#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:00:46.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:00:46.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:00:46.24#ibcon#*before write, iclass 35, count 0 2006.257.18:00:46.24#ibcon#enter sib2, iclass 35, count 0 2006.257.18:00:46.24#ibcon#flushed, iclass 35, count 0 2006.257.18:00:46.24#ibcon#about to write, iclass 35, count 0 2006.257.18:00:46.24#ibcon#wrote, iclass 35, count 0 2006.257.18:00:46.24#ibcon#about to read 3, iclass 35, count 0 2006.257.18:00:46.28#ibcon#read 3, iclass 35, count 0 2006.257.18:00:46.28#ibcon#about to read 4, iclass 35, count 0 2006.257.18:00:46.28#ibcon#read 4, iclass 35, count 0 2006.257.18:00:46.28#ibcon#about to read 5, iclass 35, count 0 2006.257.18:00:46.28#ibcon#read 5, iclass 35, count 0 2006.257.18:00:46.28#ibcon#about to read 6, iclass 35, count 0 2006.257.18:00:46.28#ibcon#read 6, iclass 35, count 0 2006.257.18:00:46.28#ibcon#end of sib2, iclass 35, count 0 2006.257.18:00:46.28#ibcon#*after write, iclass 35, count 0 2006.257.18:00:46.28#ibcon#*before return 0, iclass 35, count 0 2006.257.18:00:46.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:46.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:00:46.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:00:46.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:00:46.28$vck44/vb=4,5 2006.257.18:00:46.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.18:00:46.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.18:00:46.28#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:46.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:46.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:46.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:46.34#ibcon#enter wrdev, iclass 37, count 2 2006.257.18:00:46.34#ibcon#first serial, iclass 37, count 2 2006.257.18:00:46.34#ibcon#enter sib2, iclass 37, count 2 2006.257.18:00:46.34#ibcon#flushed, iclass 37, count 2 2006.257.18:00:46.34#ibcon#about to write, iclass 37, count 2 2006.257.18:00:46.34#ibcon#wrote, iclass 37, count 2 2006.257.18:00:46.34#ibcon#about to read 3, iclass 37, count 2 2006.257.18:00:46.36#ibcon#read 3, iclass 37, count 2 2006.257.18:00:46.36#ibcon#about to read 4, iclass 37, count 2 2006.257.18:00:46.36#ibcon#read 4, iclass 37, count 2 2006.257.18:00:46.36#ibcon#about to read 5, iclass 37, count 2 2006.257.18:00:46.36#ibcon#read 5, iclass 37, count 2 2006.257.18:00:46.36#ibcon#about to read 6, iclass 37, count 2 2006.257.18:00:46.36#ibcon#read 6, iclass 37, count 2 2006.257.18:00:46.36#ibcon#end of sib2, iclass 37, count 2 2006.257.18:00:46.36#ibcon#*mode == 0, iclass 37, count 2 2006.257.18:00:46.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.18:00:46.36#ibcon#[27=AT04-05\r\n] 2006.257.18:00:46.36#ibcon#*before write, iclass 37, count 2 2006.257.18:00:46.36#ibcon#enter sib2, iclass 37, count 2 2006.257.18:00:46.36#ibcon#flushed, iclass 37, count 2 2006.257.18:00:46.36#ibcon#about to write, iclass 37, count 2 2006.257.18:00:46.36#ibcon#wrote, iclass 37, count 2 2006.257.18:00:46.36#ibcon#about to read 3, iclass 37, count 2 2006.257.18:00:46.39#ibcon#read 3, iclass 37, count 2 2006.257.18:00:46.39#ibcon#about to read 4, iclass 37, count 2 2006.257.18:00:46.39#ibcon#read 4, iclass 37, count 2 2006.257.18:00:46.39#ibcon#about to read 5, iclass 37, count 2 2006.257.18:00:46.39#ibcon#read 5, iclass 37, count 2 2006.257.18:00:46.39#ibcon#about to read 6, iclass 37, count 2 2006.257.18:00:46.39#ibcon#read 6, iclass 37, count 2 2006.257.18:00:46.39#ibcon#end of sib2, iclass 37, count 2 2006.257.18:00:46.39#ibcon#*after write, iclass 37, count 2 2006.257.18:00:46.39#ibcon#*before return 0, iclass 37, count 2 2006.257.18:00:46.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:46.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:00:46.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.18:00:46.39#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:46.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:46.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:46.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:46.51#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:00:46.51#ibcon#first serial, iclass 37, count 0 2006.257.18:00:46.51#ibcon#enter sib2, iclass 37, count 0 2006.257.18:00:46.51#ibcon#flushed, iclass 37, count 0 2006.257.18:00:46.51#ibcon#about to write, iclass 37, count 0 2006.257.18:00:46.51#ibcon#wrote, iclass 37, count 0 2006.257.18:00:46.51#ibcon#about to read 3, iclass 37, count 0 2006.257.18:00:46.53#ibcon#read 3, iclass 37, count 0 2006.257.18:00:46.53#ibcon#about to read 4, iclass 37, count 0 2006.257.18:00:46.53#ibcon#read 4, iclass 37, count 0 2006.257.18:00:46.53#ibcon#about to read 5, iclass 37, count 0 2006.257.18:00:46.53#ibcon#read 5, iclass 37, count 0 2006.257.18:00:46.53#ibcon#about to read 6, iclass 37, count 0 2006.257.18:00:46.53#ibcon#read 6, iclass 37, count 0 2006.257.18:00:46.53#ibcon#end of sib2, iclass 37, count 0 2006.257.18:00:46.53#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:00:46.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:00:46.53#ibcon#[27=USB\r\n] 2006.257.18:00:46.53#ibcon#*before write, iclass 37, count 0 2006.257.18:00:46.53#ibcon#enter sib2, iclass 37, count 0 2006.257.18:00:46.53#ibcon#flushed, iclass 37, count 0 2006.257.18:00:46.53#ibcon#about to write, iclass 37, count 0 2006.257.18:00:46.53#ibcon#wrote, iclass 37, count 0 2006.257.18:00:46.53#ibcon#about to read 3, iclass 37, count 0 2006.257.18:00:46.56#ibcon#read 3, iclass 37, count 0 2006.257.18:00:46.56#ibcon#about to read 4, iclass 37, count 0 2006.257.18:00:46.56#ibcon#read 4, iclass 37, count 0 2006.257.18:00:46.56#ibcon#about to read 5, iclass 37, count 0 2006.257.18:00:46.56#ibcon#read 5, iclass 37, count 0 2006.257.18:00:46.56#ibcon#about to read 6, iclass 37, count 0 2006.257.18:00:46.56#ibcon#read 6, iclass 37, count 0 2006.257.18:00:46.56#ibcon#end of sib2, iclass 37, count 0 2006.257.18:00:46.56#ibcon#*after write, iclass 37, count 0 2006.257.18:00:46.56#ibcon#*before return 0, iclass 37, count 0 2006.257.18:00:46.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:46.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:00:46.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:00:46.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:00:46.56$vck44/vblo=5,709.99 2006.257.18:00:46.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.18:00:46.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.18:00:46.56#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:46.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:46.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:46.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:46.56#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:00:46.56#ibcon#first serial, iclass 39, count 0 2006.257.18:00:46.56#ibcon#enter sib2, iclass 39, count 0 2006.257.18:00:46.56#ibcon#flushed, iclass 39, count 0 2006.257.18:00:46.56#ibcon#about to write, iclass 39, count 0 2006.257.18:00:46.56#ibcon#wrote, iclass 39, count 0 2006.257.18:00:46.56#ibcon#about to read 3, iclass 39, count 0 2006.257.18:00:46.58#ibcon#read 3, iclass 39, count 0 2006.257.18:00:46.58#ibcon#about to read 4, iclass 39, count 0 2006.257.18:00:46.58#ibcon#read 4, iclass 39, count 0 2006.257.18:00:46.58#ibcon#about to read 5, iclass 39, count 0 2006.257.18:00:46.58#ibcon#read 5, iclass 39, count 0 2006.257.18:00:46.58#ibcon#about to read 6, iclass 39, count 0 2006.257.18:00:46.58#ibcon#read 6, iclass 39, count 0 2006.257.18:00:46.58#ibcon#end of sib2, iclass 39, count 0 2006.257.18:00:46.58#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:00:46.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:00:46.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:00:46.58#ibcon#*before write, iclass 39, count 0 2006.257.18:00:46.58#ibcon#enter sib2, iclass 39, count 0 2006.257.18:00:46.58#ibcon#flushed, iclass 39, count 0 2006.257.18:00:46.58#ibcon#about to write, iclass 39, count 0 2006.257.18:00:46.58#ibcon#wrote, iclass 39, count 0 2006.257.18:00:46.58#ibcon#about to read 3, iclass 39, count 0 2006.257.18:00:46.62#ibcon#read 3, iclass 39, count 0 2006.257.18:00:46.62#ibcon#about to read 4, iclass 39, count 0 2006.257.18:00:46.62#ibcon#read 4, iclass 39, count 0 2006.257.18:00:46.62#ibcon#about to read 5, iclass 39, count 0 2006.257.18:00:46.62#ibcon#read 5, iclass 39, count 0 2006.257.18:00:46.62#ibcon#about to read 6, iclass 39, count 0 2006.257.18:00:46.62#ibcon#read 6, iclass 39, count 0 2006.257.18:00:46.62#ibcon#end of sib2, iclass 39, count 0 2006.257.18:00:46.62#ibcon#*after write, iclass 39, count 0 2006.257.18:00:46.62#ibcon#*before return 0, iclass 39, count 0 2006.257.18:00:46.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:46.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:00:46.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:00:46.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:00:46.62$vck44/vb=5,4 2006.257.18:00:46.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.18:00:46.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.18:00:46.62#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:46.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:46.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:46.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:46.68#ibcon#enter wrdev, iclass 3, count 2 2006.257.18:00:46.68#ibcon#first serial, iclass 3, count 2 2006.257.18:00:46.68#ibcon#enter sib2, iclass 3, count 2 2006.257.18:00:46.68#ibcon#flushed, iclass 3, count 2 2006.257.18:00:46.68#ibcon#about to write, iclass 3, count 2 2006.257.18:00:46.68#ibcon#wrote, iclass 3, count 2 2006.257.18:00:46.68#ibcon#about to read 3, iclass 3, count 2 2006.257.18:00:46.70#ibcon#read 3, iclass 3, count 2 2006.257.18:00:46.70#ibcon#about to read 4, iclass 3, count 2 2006.257.18:00:46.70#ibcon#read 4, iclass 3, count 2 2006.257.18:00:46.70#ibcon#about to read 5, iclass 3, count 2 2006.257.18:00:46.70#ibcon#read 5, iclass 3, count 2 2006.257.18:00:46.70#ibcon#about to read 6, iclass 3, count 2 2006.257.18:00:46.70#ibcon#read 6, iclass 3, count 2 2006.257.18:00:46.70#ibcon#end of sib2, iclass 3, count 2 2006.257.18:00:46.70#ibcon#*mode == 0, iclass 3, count 2 2006.257.18:00:46.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.18:00:46.70#ibcon#[27=AT05-04\r\n] 2006.257.18:00:46.70#ibcon#*before write, iclass 3, count 2 2006.257.18:00:46.70#ibcon#enter sib2, iclass 3, count 2 2006.257.18:00:46.70#ibcon#flushed, iclass 3, count 2 2006.257.18:00:46.70#ibcon#about to write, iclass 3, count 2 2006.257.18:00:46.70#ibcon#wrote, iclass 3, count 2 2006.257.18:00:46.70#ibcon#about to read 3, iclass 3, count 2 2006.257.18:00:46.73#ibcon#read 3, iclass 3, count 2 2006.257.18:00:46.73#ibcon#about to read 4, iclass 3, count 2 2006.257.18:00:46.73#ibcon#read 4, iclass 3, count 2 2006.257.18:00:46.73#ibcon#about to read 5, iclass 3, count 2 2006.257.18:00:46.73#ibcon#read 5, iclass 3, count 2 2006.257.18:00:46.73#ibcon#about to read 6, iclass 3, count 2 2006.257.18:00:46.73#ibcon#read 6, iclass 3, count 2 2006.257.18:00:46.73#ibcon#end of sib2, iclass 3, count 2 2006.257.18:00:46.73#ibcon#*after write, iclass 3, count 2 2006.257.18:00:46.73#ibcon#*before return 0, iclass 3, count 2 2006.257.18:00:46.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:46.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:00:46.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.18:00:46.73#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:46.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:46.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:46.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:46.85#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:00:46.85#ibcon#first serial, iclass 3, count 0 2006.257.18:00:46.85#ibcon#enter sib2, iclass 3, count 0 2006.257.18:00:46.85#ibcon#flushed, iclass 3, count 0 2006.257.18:00:46.85#ibcon#about to write, iclass 3, count 0 2006.257.18:00:46.85#ibcon#wrote, iclass 3, count 0 2006.257.18:00:46.85#ibcon#about to read 3, iclass 3, count 0 2006.257.18:00:46.87#ibcon#read 3, iclass 3, count 0 2006.257.18:00:46.87#ibcon#about to read 4, iclass 3, count 0 2006.257.18:00:46.87#ibcon#read 4, iclass 3, count 0 2006.257.18:00:46.87#ibcon#about to read 5, iclass 3, count 0 2006.257.18:00:46.87#ibcon#read 5, iclass 3, count 0 2006.257.18:00:46.87#ibcon#about to read 6, iclass 3, count 0 2006.257.18:00:46.87#ibcon#read 6, iclass 3, count 0 2006.257.18:00:46.87#ibcon#end of sib2, iclass 3, count 0 2006.257.18:00:46.87#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:00:46.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:00:46.87#ibcon#[27=USB\r\n] 2006.257.18:00:46.87#ibcon#*before write, iclass 3, count 0 2006.257.18:00:46.87#ibcon#enter sib2, iclass 3, count 0 2006.257.18:00:46.87#ibcon#flushed, iclass 3, count 0 2006.257.18:00:46.87#ibcon#about to write, iclass 3, count 0 2006.257.18:00:46.87#ibcon#wrote, iclass 3, count 0 2006.257.18:00:46.87#ibcon#about to read 3, iclass 3, count 0 2006.257.18:00:46.90#ibcon#read 3, iclass 3, count 0 2006.257.18:00:46.90#ibcon#about to read 4, iclass 3, count 0 2006.257.18:00:46.90#ibcon#read 4, iclass 3, count 0 2006.257.18:00:46.90#ibcon#about to read 5, iclass 3, count 0 2006.257.18:00:46.90#ibcon#read 5, iclass 3, count 0 2006.257.18:00:46.90#ibcon#about to read 6, iclass 3, count 0 2006.257.18:00:46.90#ibcon#read 6, iclass 3, count 0 2006.257.18:00:46.90#ibcon#end of sib2, iclass 3, count 0 2006.257.18:00:46.90#ibcon#*after write, iclass 3, count 0 2006.257.18:00:46.90#ibcon#*before return 0, iclass 3, count 0 2006.257.18:00:46.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:46.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:00:46.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:00:46.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:00:46.90$vck44/vblo=6,719.99 2006.257.18:00:46.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.18:00:46.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.18:00:46.90#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:46.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:46.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:46.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:46.90#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:00:46.90#ibcon#first serial, iclass 5, count 0 2006.257.18:00:46.90#ibcon#enter sib2, iclass 5, count 0 2006.257.18:00:46.90#ibcon#flushed, iclass 5, count 0 2006.257.18:00:46.90#ibcon#about to write, iclass 5, count 0 2006.257.18:00:46.90#ibcon#wrote, iclass 5, count 0 2006.257.18:00:46.90#ibcon#about to read 3, iclass 5, count 0 2006.257.18:00:46.92#ibcon#read 3, iclass 5, count 0 2006.257.18:00:46.92#ibcon#about to read 4, iclass 5, count 0 2006.257.18:00:46.92#ibcon#read 4, iclass 5, count 0 2006.257.18:00:46.92#ibcon#about to read 5, iclass 5, count 0 2006.257.18:00:46.92#ibcon#read 5, iclass 5, count 0 2006.257.18:00:46.92#ibcon#about to read 6, iclass 5, count 0 2006.257.18:00:46.92#ibcon#read 6, iclass 5, count 0 2006.257.18:00:46.92#ibcon#end of sib2, iclass 5, count 0 2006.257.18:00:46.92#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:00:46.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:00:46.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:00:46.92#ibcon#*before write, iclass 5, count 0 2006.257.18:00:46.92#ibcon#enter sib2, iclass 5, count 0 2006.257.18:00:46.92#ibcon#flushed, iclass 5, count 0 2006.257.18:00:46.92#ibcon#about to write, iclass 5, count 0 2006.257.18:00:46.92#ibcon#wrote, iclass 5, count 0 2006.257.18:00:46.92#ibcon#about to read 3, iclass 5, count 0 2006.257.18:00:46.96#ibcon#read 3, iclass 5, count 0 2006.257.18:00:46.96#ibcon#about to read 4, iclass 5, count 0 2006.257.18:00:46.96#ibcon#read 4, iclass 5, count 0 2006.257.18:00:46.96#ibcon#about to read 5, iclass 5, count 0 2006.257.18:00:46.96#ibcon#read 5, iclass 5, count 0 2006.257.18:00:46.96#ibcon#about to read 6, iclass 5, count 0 2006.257.18:00:46.96#ibcon#read 6, iclass 5, count 0 2006.257.18:00:46.96#ibcon#end of sib2, iclass 5, count 0 2006.257.18:00:46.96#ibcon#*after write, iclass 5, count 0 2006.257.18:00:46.96#ibcon#*before return 0, iclass 5, count 0 2006.257.18:00:46.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:46.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:00:46.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:00:46.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:00:46.96$vck44/vb=6,4 2006.257.18:00:46.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.18:00:46.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.18:00:46.96#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:46.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:47.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:47.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:47.02#ibcon#enter wrdev, iclass 7, count 2 2006.257.18:00:47.02#ibcon#first serial, iclass 7, count 2 2006.257.18:00:47.02#ibcon#enter sib2, iclass 7, count 2 2006.257.18:00:47.02#ibcon#flushed, iclass 7, count 2 2006.257.18:00:47.02#ibcon#about to write, iclass 7, count 2 2006.257.18:00:47.02#ibcon#wrote, iclass 7, count 2 2006.257.18:00:47.02#ibcon#about to read 3, iclass 7, count 2 2006.257.18:00:47.04#ibcon#read 3, iclass 7, count 2 2006.257.18:00:47.04#ibcon#about to read 4, iclass 7, count 2 2006.257.18:00:47.04#ibcon#read 4, iclass 7, count 2 2006.257.18:00:47.04#ibcon#about to read 5, iclass 7, count 2 2006.257.18:00:47.04#ibcon#read 5, iclass 7, count 2 2006.257.18:00:47.04#ibcon#about to read 6, iclass 7, count 2 2006.257.18:00:47.04#ibcon#read 6, iclass 7, count 2 2006.257.18:00:47.04#ibcon#end of sib2, iclass 7, count 2 2006.257.18:00:47.04#ibcon#*mode == 0, iclass 7, count 2 2006.257.18:00:47.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.18:00:47.04#ibcon#[27=AT06-04\r\n] 2006.257.18:00:47.04#ibcon#*before write, iclass 7, count 2 2006.257.18:00:47.04#ibcon#enter sib2, iclass 7, count 2 2006.257.18:00:47.04#ibcon#flushed, iclass 7, count 2 2006.257.18:00:47.04#ibcon#about to write, iclass 7, count 2 2006.257.18:00:47.04#ibcon#wrote, iclass 7, count 2 2006.257.18:00:47.04#ibcon#about to read 3, iclass 7, count 2 2006.257.18:00:47.07#ibcon#read 3, iclass 7, count 2 2006.257.18:00:47.07#ibcon#about to read 4, iclass 7, count 2 2006.257.18:00:47.07#ibcon#read 4, iclass 7, count 2 2006.257.18:00:47.07#ibcon#about to read 5, iclass 7, count 2 2006.257.18:00:47.07#ibcon#read 5, iclass 7, count 2 2006.257.18:00:47.07#ibcon#about to read 6, iclass 7, count 2 2006.257.18:00:47.07#ibcon#read 6, iclass 7, count 2 2006.257.18:00:47.07#ibcon#end of sib2, iclass 7, count 2 2006.257.18:00:47.07#ibcon#*after write, iclass 7, count 2 2006.257.18:00:47.07#ibcon#*before return 0, iclass 7, count 2 2006.257.18:00:47.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:47.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:00:47.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.18:00:47.07#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:47.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:47.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:47.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:47.19#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:00:47.19#ibcon#first serial, iclass 7, count 0 2006.257.18:00:47.19#ibcon#enter sib2, iclass 7, count 0 2006.257.18:00:47.19#ibcon#flushed, iclass 7, count 0 2006.257.18:00:47.19#ibcon#about to write, iclass 7, count 0 2006.257.18:00:47.19#ibcon#wrote, iclass 7, count 0 2006.257.18:00:47.19#ibcon#about to read 3, iclass 7, count 0 2006.257.18:00:47.21#ibcon#read 3, iclass 7, count 0 2006.257.18:00:47.21#ibcon#about to read 4, iclass 7, count 0 2006.257.18:00:47.21#ibcon#read 4, iclass 7, count 0 2006.257.18:00:47.21#ibcon#about to read 5, iclass 7, count 0 2006.257.18:00:47.21#ibcon#read 5, iclass 7, count 0 2006.257.18:00:47.21#ibcon#about to read 6, iclass 7, count 0 2006.257.18:00:47.21#ibcon#read 6, iclass 7, count 0 2006.257.18:00:47.21#ibcon#end of sib2, iclass 7, count 0 2006.257.18:00:47.21#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:00:47.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:00:47.21#ibcon#[27=USB\r\n] 2006.257.18:00:47.21#ibcon#*before write, iclass 7, count 0 2006.257.18:00:47.21#ibcon#enter sib2, iclass 7, count 0 2006.257.18:00:47.21#ibcon#flushed, iclass 7, count 0 2006.257.18:00:47.21#ibcon#about to write, iclass 7, count 0 2006.257.18:00:47.21#ibcon#wrote, iclass 7, count 0 2006.257.18:00:47.21#ibcon#about to read 3, iclass 7, count 0 2006.257.18:00:47.24#ibcon#read 3, iclass 7, count 0 2006.257.18:00:47.24#ibcon#about to read 4, iclass 7, count 0 2006.257.18:00:47.24#ibcon#read 4, iclass 7, count 0 2006.257.18:00:47.24#ibcon#about to read 5, iclass 7, count 0 2006.257.18:00:47.24#ibcon#read 5, iclass 7, count 0 2006.257.18:00:47.24#ibcon#about to read 6, iclass 7, count 0 2006.257.18:00:47.24#ibcon#read 6, iclass 7, count 0 2006.257.18:00:47.24#ibcon#end of sib2, iclass 7, count 0 2006.257.18:00:47.24#ibcon#*after write, iclass 7, count 0 2006.257.18:00:47.24#ibcon#*before return 0, iclass 7, count 0 2006.257.18:00:47.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:47.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:00:47.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:00:47.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:00:47.24$vck44/vblo=7,734.99 2006.257.18:00:47.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.18:00:47.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.18:00:47.24#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:47.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:47.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:47.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:47.24#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:00:47.24#ibcon#first serial, iclass 11, count 0 2006.257.18:00:47.24#ibcon#enter sib2, iclass 11, count 0 2006.257.18:00:47.24#ibcon#flushed, iclass 11, count 0 2006.257.18:00:47.24#ibcon#about to write, iclass 11, count 0 2006.257.18:00:47.24#ibcon#wrote, iclass 11, count 0 2006.257.18:00:47.24#ibcon#about to read 3, iclass 11, count 0 2006.257.18:00:47.26#ibcon#read 3, iclass 11, count 0 2006.257.18:00:47.26#ibcon#about to read 4, iclass 11, count 0 2006.257.18:00:47.26#ibcon#read 4, iclass 11, count 0 2006.257.18:00:47.26#ibcon#about to read 5, iclass 11, count 0 2006.257.18:00:47.26#ibcon#read 5, iclass 11, count 0 2006.257.18:00:47.26#ibcon#about to read 6, iclass 11, count 0 2006.257.18:00:47.26#ibcon#read 6, iclass 11, count 0 2006.257.18:00:47.26#ibcon#end of sib2, iclass 11, count 0 2006.257.18:00:47.26#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:00:47.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:00:47.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:00:47.26#ibcon#*before write, iclass 11, count 0 2006.257.18:00:47.26#ibcon#enter sib2, iclass 11, count 0 2006.257.18:00:47.26#ibcon#flushed, iclass 11, count 0 2006.257.18:00:47.26#ibcon#about to write, iclass 11, count 0 2006.257.18:00:47.26#ibcon#wrote, iclass 11, count 0 2006.257.18:00:47.26#ibcon#about to read 3, iclass 11, count 0 2006.257.18:00:47.30#ibcon#read 3, iclass 11, count 0 2006.257.18:00:47.30#ibcon#about to read 4, iclass 11, count 0 2006.257.18:00:47.30#ibcon#read 4, iclass 11, count 0 2006.257.18:00:47.30#ibcon#about to read 5, iclass 11, count 0 2006.257.18:00:47.30#ibcon#read 5, iclass 11, count 0 2006.257.18:00:47.30#ibcon#about to read 6, iclass 11, count 0 2006.257.18:00:47.30#ibcon#read 6, iclass 11, count 0 2006.257.18:00:47.30#ibcon#end of sib2, iclass 11, count 0 2006.257.18:00:47.30#ibcon#*after write, iclass 11, count 0 2006.257.18:00:47.30#ibcon#*before return 0, iclass 11, count 0 2006.257.18:00:47.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:47.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:00:47.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:00:47.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:00:47.30$vck44/vb=7,4 2006.257.18:00:47.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.18:00:47.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.18:00:47.30#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:47.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:47.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:47.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:47.36#ibcon#enter wrdev, iclass 13, count 2 2006.257.18:00:47.36#ibcon#first serial, iclass 13, count 2 2006.257.18:00:47.36#ibcon#enter sib2, iclass 13, count 2 2006.257.18:00:47.36#ibcon#flushed, iclass 13, count 2 2006.257.18:00:47.36#ibcon#about to write, iclass 13, count 2 2006.257.18:00:47.36#ibcon#wrote, iclass 13, count 2 2006.257.18:00:47.36#ibcon#about to read 3, iclass 13, count 2 2006.257.18:00:47.38#ibcon#read 3, iclass 13, count 2 2006.257.18:00:47.38#ibcon#about to read 4, iclass 13, count 2 2006.257.18:00:47.38#ibcon#read 4, iclass 13, count 2 2006.257.18:00:47.38#ibcon#about to read 5, iclass 13, count 2 2006.257.18:00:47.38#ibcon#read 5, iclass 13, count 2 2006.257.18:00:47.38#ibcon#about to read 6, iclass 13, count 2 2006.257.18:00:47.38#ibcon#read 6, iclass 13, count 2 2006.257.18:00:47.38#ibcon#end of sib2, iclass 13, count 2 2006.257.18:00:47.38#ibcon#*mode == 0, iclass 13, count 2 2006.257.18:00:47.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.18:00:47.38#ibcon#[27=AT07-04\r\n] 2006.257.18:00:47.38#ibcon#*before write, iclass 13, count 2 2006.257.18:00:47.38#ibcon#enter sib2, iclass 13, count 2 2006.257.18:00:47.38#ibcon#flushed, iclass 13, count 2 2006.257.18:00:47.38#ibcon#about to write, iclass 13, count 2 2006.257.18:00:47.38#ibcon#wrote, iclass 13, count 2 2006.257.18:00:47.38#ibcon#about to read 3, iclass 13, count 2 2006.257.18:00:47.41#ibcon#read 3, iclass 13, count 2 2006.257.18:00:47.41#ibcon#about to read 4, iclass 13, count 2 2006.257.18:00:47.41#ibcon#read 4, iclass 13, count 2 2006.257.18:00:47.41#ibcon#about to read 5, iclass 13, count 2 2006.257.18:00:47.41#ibcon#read 5, iclass 13, count 2 2006.257.18:00:47.41#ibcon#about to read 6, iclass 13, count 2 2006.257.18:00:47.41#ibcon#read 6, iclass 13, count 2 2006.257.18:00:47.41#ibcon#end of sib2, iclass 13, count 2 2006.257.18:00:47.41#ibcon#*after write, iclass 13, count 2 2006.257.18:00:47.41#ibcon#*before return 0, iclass 13, count 2 2006.257.18:00:47.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:47.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:00:47.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.18:00:47.41#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:47.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:47.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:47.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:47.53#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:00:47.53#ibcon#first serial, iclass 13, count 0 2006.257.18:00:47.53#ibcon#enter sib2, iclass 13, count 0 2006.257.18:00:47.53#ibcon#flushed, iclass 13, count 0 2006.257.18:00:47.53#ibcon#about to write, iclass 13, count 0 2006.257.18:00:47.53#ibcon#wrote, iclass 13, count 0 2006.257.18:00:47.53#ibcon#about to read 3, iclass 13, count 0 2006.257.18:00:47.55#ibcon#read 3, iclass 13, count 0 2006.257.18:00:47.55#ibcon#about to read 4, iclass 13, count 0 2006.257.18:00:47.55#ibcon#read 4, iclass 13, count 0 2006.257.18:00:47.55#ibcon#about to read 5, iclass 13, count 0 2006.257.18:00:47.55#ibcon#read 5, iclass 13, count 0 2006.257.18:00:47.55#ibcon#about to read 6, iclass 13, count 0 2006.257.18:00:47.55#ibcon#read 6, iclass 13, count 0 2006.257.18:00:47.55#ibcon#end of sib2, iclass 13, count 0 2006.257.18:00:47.55#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:00:47.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:00:47.55#ibcon#[27=USB\r\n] 2006.257.18:00:47.55#ibcon#*before write, iclass 13, count 0 2006.257.18:00:47.55#ibcon#enter sib2, iclass 13, count 0 2006.257.18:00:47.55#ibcon#flushed, iclass 13, count 0 2006.257.18:00:47.55#ibcon#about to write, iclass 13, count 0 2006.257.18:00:47.55#ibcon#wrote, iclass 13, count 0 2006.257.18:00:47.55#ibcon#about to read 3, iclass 13, count 0 2006.257.18:00:47.58#ibcon#read 3, iclass 13, count 0 2006.257.18:00:47.58#ibcon#about to read 4, iclass 13, count 0 2006.257.18:00:47.58#ibcon#read 4, iclass 13, count 0 2006.257.18:00:47.58#ibcon#about to read 5, iclass 13, count 0 2006.257.18:00:47.58#ibcon#read 5, iclass 13, count 0 2006.257.18:00:47.58#ibcon#about to read 6, iclass 13, count 0 2006.257.18:00:47.58#ibcon#read 6, iclass 13, count 0 2006.257.18:00:47.58#ibcon#end of sib2, iclass 13, count 0 2006.257.18:00:47.58#ibcon#*after write, iclass 13, count 0 2006.257.18:00:47.58#ibcon#*before return 0, iclass 13, count 0 2006.257.18:00:47.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:47.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:00:47.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:00:47.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:00:47.58$vck44/vblo=8,744.99 2006.257.18:00:47.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.18:00:47.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.18:00:47.58#ibcon#ireg 17 cls_cnt 0 2006.257.18:00:47.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:47.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:47.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:47.58#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:00:47.58#ibcon#first serial, iclass 15, count 0 2006.257.18:00:47.58#ibcon#enter sib2, iclass 15, count 0 2006.257.18:00:47.58#ibcon#flushed, iclass 15, count 0 2006.257.18:00:47.58#ibcon#about to write, iclass 15, count 0 2006.257.18:00:47.58#ibcon#wrote, iclass 15, count 0 2006.257.18:00:47.58#ibcon#about to read 3, iclass 15, count 0 2006.257.18:00:47.60#ibcon#read 3, iclass 15, count 0 2006.257.18:00:47.60#ibcon#about to read 4, iclass 15, count 0 2006.257.18:00:47.60#ibcon#read 4, iclass 15, count 0 2006.257.18:00:47.60#ibcon#about to read 5, iclass 15, count 0 2006.257.18:00:47.60#ibcon#read 5, iclass 15, count 0 2006.257.18:00:47.60#ibcon#about to read 6, iclass 15, count 0 2006.257.18:00:47.60#ibcon#read 6, iclass 15, count 0 2006.257.18:00:47.60#ibcon#end of sib2, iclass 15, count 0 2006.257.18:00:47.60#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:00:47.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:00:47.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:00:47.60#ibcon#*before write, iclass 15, count 0 2006.257.18:00:47.60#ibcon#enter sib2, iclass 15, count 0 2006.257.18:00:47.60#ibcon#flushed, iclass 15, count 0 2006.257.18:00:47.60#ibcon#about to write, iclass 15, count 0 2006.257.18:00:47.60#ibcon#wrote, iclass 15, count 0 2006.257.18:00:47.60#ibcon#about to read 3, iclass 15, count 0 2006.257.18:00:47.64#ibcon#read 3, iclass 15, count 0 2006.257.18:00:47.64#ibcon#about to read 4, iclass 15, count 0 2006.257.18:00:47.64#ibcon#read 4, iclass 15, count 0 2006.257.18:00:47.64#ibcon#about to read 5, iclass 15, count 0 2006.257.18:00:47.64#ibcon#read 5, iclass 15, count 0 2006.257.18:00:47.64#ibcon#about to read 6, iclass 15, count 0 2006.257.18:00:47.64#ibcon#read 6, iclass 15, count 0 2006.257.18:00:47.64#ibcon#end of sib2, iclass 15, count 0 2006.257.18:00:47.64#ibcon#*after write, iclass 15, count 0 2006.257.18:00:47.64#ibcon#*before return 0, iclass 15, count 0 2006.257.18:00:47.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:47.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:00:47.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:00:47.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:00:47.64$vck44/vb=8,4 2006.257.18:00:47.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.18:00:47.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.18:00:47.64#ibcon#ireg 11 cls_cnt 2 2006.257.18:00:47.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:47.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:47.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:47.70#ibcon#enter wrdev, iclass 17, count 2 2006.257.18:00:47.70#ibcon#first serial, iclass 17, count 2 2006.257.18:00:47.70#ibcon#enter sib2, iclass 17, count 2 2006.257.18:00:47.70#ibcon#flushed, iclass 17, count 2 2006.257.18:00:47.70#ibcon#about to write, iclass 17, count 2 2006.257.18:00:47.70#ibcon#wrote, iclass 17, count 2 2006.257.18:00:47.70#ibcon#about to read 3, iclass 17, count 2 2006.257.18:00:47.72#ibcon#read 3, iclass 17, count 2 2006.257.18:00:47.72#ibcon#about to read 4, iclass 17, count 2 2006.257.18:00:47.72#ibcon#read 4, iclass 17, count 2 2006.257.18:00:47.72#ibcon#about to read 5, iclass 17, count 2 2006.257.18:00:47.72#ibcon#read 5, iclass 17, count 2 2006.257.18:00:47.72#ibcon#about to read 6, iclass 17, count 2 2006.257.18:00:47.72#ibcon#read 6, iclass 17, count 2 2006.257.18:00:47.72#ibcon#end of sib2, iclass 17, count 2 2006.257.18:00:47.72#ibcon#*mode == 0, iclass 17, count 2 2006.257.18:00:47.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.18:00:47.72#ibcon#[27=AT08-04\r\n] 2006.257.18:00:47.72#ibcon#*before write, iclass 17, count 2 2006.257.18:00:47.72#ibcon#enter sib2, iclass 17, count 2 2006.257.18:00:47.72#ibcon#flushed, iclass 17, count 2 2006.257.18:00:47.72#ibcon#about to write, iclass 17, count 2 2006.257.18:00:47.72#ibcon#wrote, iclass 17, count 2 2006.257.18:00:47.72#ibcon#about to read 3, iclass 17, count 2 2006.257.18:00:47.75#ibcon#read 3, iclass 17, count 2 2006.257.18:00:47.75#ibcon#about to read 4, iclass 17, count 2 2006.257.18:00:47.75#ibcon#read 4, iclass 17, count 2 2006.257.18:00:47.75#ibcon#about to read 5, iclass 17, count 2 2006.257.18:00:47.75#ibcon#read 5, iclass 17, count 2 2006.257.18:00:47.75#ibcon#about to read 6, iclass 17, count 2 2006.257.18:00:47.75#ibcon#read 6, iclass 17, count 2 2006.257.18:00:47.75#ibcon#end of sib2, iclass 17, count 2 2006.257.18:00:47.75#ibcon#*after write, iclass 17, count 2 2006.257.18:00:47.75#ibcon#*before return 0, iclass 17, count 2 2006.257.18:00:47.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:47.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:00:47.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.18:00:47.75#ibcon#ireg 7 cls_cnt 0 2006.257.18:00:47.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:47.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:47.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:47.87#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:00:47.87#ibcon#first serial, iclass 17, count 0 2006.257.18:00:47.87#ibcon#enter sib2, iclass 17, count 0 2006.257.18:00:47.87#ibcon#flushed, iclass 17, count 0 2006.257.18:00:47.87#ibcon#about to write, iclass 17, count 0 2006.257.18:00:47.87#ibcon#wrote, iclass 17, count 0 2006.257.18:00:47.87#ibcon#about to read 3, iclass 17, count 0 2006.257.18:00:47.89#ibcon#read 3, iclass 17, count 0 2006.257.18:00:47.89#ibcon#about to read 4, iclass 17, count 0 2006.257.18:00:47.89#ibcon#read 4, iclass 17, count 0 2006.257.18:00:47.89#ibcon#about to read 5, iclass 17, count 0 2006.257.18:00:47.89#ibcon#read 5, iclass 17, count 0 2006.257.18:00:47.89#ibcon#about to read 6, iclass 17, count 0 2006.257.18:00:47.89#ibcon#read 6, iclass 17, count 0 2006.257.18:00:47.89#ibcon#end of sib2, iclass 17, count 0 2006.257.18:00:47.89#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:00:47.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:00:47.89#ibcon#[27=USB\r\n] 2006.257.18:00:47.89#ibcon#*before write, iclass 17, count 0 2006.257.18:00:47.89#ibcon#enter sib2, iclass 17, count 0 2006.257.18:00:47.89#ibcon#flushed, iclass 17, count 0 2006.257.18:00:47.89#ibcon#about to write, iclass 17, count 0 2006.257.18:00:47.89#ibcon#wrote, iclass 17, count 0 2006.257.18:00:47.89#ibcon#about to read 3, iclass 17, count 0 2006.257.18:00:47.92#ibcon#read 3, iclass 17, count 0 2006.257.18:00:47.92#ibcon#about to read 4, iclass 17, count 0 2006.257.18:00:47.92#ibcon#read 4, iclass 17, count 0 2006.257.18:00:47.92#ibcon#about to read 5, iclass 17, count 0 2006.257.18:00:47.92#ibcon#read 5, iclass 17, count 0 2006.257.18:00:47.92#ibcon#about to read 6, iclass 17, count 0 2006.257.18:00:47.92#ibcon#read 6, iclass 17, count 0 2006.257.18:00:47.92#ibcon#end of sib2, iclass 17, count 0 2006.257.18:00:47.92#ibcon#*after write, iclass 17, count 0 2006.257.18:00:47.92#ibcon#*before return 0, iclass 17, count 0 2006.257.18:00:47.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:47.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:00:47.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:00:47.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:00:47.92$vck44/vabw=wide 2006.257.18:00:47.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.18:00:47.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.18:00:47.92#ibcon#ireg 8 cls_cnt 0 2006.257.18:00:47.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:47.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:47.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:47.92#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:00:47.92#ibcon#first serial, iclass 19, count 0 2006.257.18:00:47.92#ibcon#enter sib2, iclass 19, count 0 2006.257.18:00:47.92#ibcon#flushed, iclass 19, count 0 2006.257.18:00:47.92#ibcon#about to write, iclass 19, count 0 2006.257.18:00:47.92#ibcon#wrote, iclass 19, count 0 2006.257.18:00:47.92#ibcon#about to read 3, iclass 19, count 0 2006.257.18:00:47.94#ibcon#read 3, iclass 19, count 0 2006.257.18:00:47.94#ibcon#about to read 4, iclass 19, count 0 2006.257.18:00:47.94#ibcon#read 4, iclass 19, count 0 2006.257.18:00:47.94#ibcon#about to read 5, iclass 19, count 0 2006.257.18:00:47.94#ibcon#read 5, iclass 19, count 0 2006.257.18:00:47.94#ibcon#about to read 6, iclass 19, count 0 2006.257.18:00:47.94#ibcon#read 6, iclass 19, count 0 2006.257.18:00:47.94#ibcon#end of sib2, iclass 19, count 0 2006.257.18:00:47.94#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:00:47.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:00:47.94#ibcon#[25=BW32\r\n] 2006.257.18:00:47.94#ibcon#*before write, iclass 19, count 0 2006.257.18:00:47.94#ibcon#enter sib2, iclass 19, count 0 2006.257.18:00:47.94#ibcon#flushed, iclass 19, count 0 2006.257.18:00:47.94#ibcon#about to write, iclass 19, count 0 2006.257.18:00:47.94#ibcon#wrote, iclass 19, count 0 2006.257.18:00:47.94#ibcon#about to read 3, iclass 19, count 0 2006.257.18:00:47.97#ibcon#read 3, iclass 19, count 0 2006.257.18:00:47.97#ibcon#about to read 4, iclass 19, count 0 2006.257.18:00:47.97#ibcon#read 4, iclass 19, count 0 2006.257.18:00:47.97#ibcon#about to read 5, iclass 19, count 0 2006.257.18:00:47.97#ibcon#read 5, iclass 19, count 0 2006.257.18:00:47.97#ibcon#about to read 6, iclass 19, count 0 2006.257.18:00:47.97#ibcon#read 6, iclass 19, count 0 2006.257.18:00:47.97#ibcon#end of sib2, iclass 19, count 0 2006.257.18:00:47.97#ibcon#*after write, iclass 19, count 0 2006.257.18:00:47.97#ibcon#*before return 0, iclass 19, count 0 2006.257.18:00:47.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:47.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:00:47.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:00:47.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:00:47.97$vck44/vbbw=wide 2006.257.18:00:47.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.18:00:47.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.18:00:47.97#ibcon#ireg 8 cls_cnt 0 2006.257.18:00:47.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:00:48.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:00:48.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:00:48.04#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:00:48.04#ibcon#first serial, iclass 21, count 0 2006.257.18:00:48.04#ibcon#enter sib2, iclass 21, count 0 2006.257.18:00:48.04#ibcon#flushed, iclass 21, count 0 2006.257.18:00:48.04#ibcon#about to write, iclass 21, count 0 2006.257.18:00:48.04#ibcon#wrote, iclass 21, count 0 2006.257.18:00:48.04#ibcon#about to read 3, iclass 21, count 0 2006.257.18:00:48.06#ibcon#read 3, iclass 21, count 0 2006.257.18:00:48.06#ibcon#about to read 4, iclass 21, count 0 2006.257.18:00:48.06#ibcon#read 4, iclass 21, count 0 2006.257.18:00:48.06#ibcon#about to read 5, iclass 21, count 0 2006.257.18:00:48.06#ibcon#read 5, iclass 21, count 0 2006.257.18:00:48.06#ibcon#about to read 6, iclass 21, count 0 2006.257.18:00:48.06#ibcon#read 6, iclass 21, count 0 2006.257.18:00:48.06#ibcon#end of sib2, iclass 21, count 0 2006.257.18:00:48.06#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:00:48.06#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:00:48.06#ibcon#[27=BW32\r\n] 2006.257.18:00:48.06#ibcon#*before write, iclass 21, count 0 2006.257.18:00:48.06#ibcon#enter sib2, iclass 21, count 0 2006.257.18:00:48.06#ibcon#flushed, iclass 21, count 0 2006.257.18:00:48.06#ibcon#about to write, iclass 21, count 0 2006.257.18:00:48.06#ibcon#wrote, iclass 21, count 0 2006.257.18:00:48.06#ibcon#about to read 3, iclass 21, count 0 2006.257.18:00:48.09#ibcon#read 3, iclass 21, count 0 2006.257.18:00:48.09#ibcon#about to read 4, iclass 21, count 0 2006.257.18:00:48.09#ibcon#read 4, iclass 21, count 0 2006.257.18:00:48.09#ibcon#about to read 5, iclass 21, count 0 2006.257.18:00:48.09#ibcon#read 5, iclass 21, count 0 2006.257.18:00:48.09#ibcon#about to read 6, iclass 21, count 0 2006.257.18:00:48.09#ibcon#read 6, iclass 21, count 0 2006.257.18:00:48.09#ibcon#end of sib2, iclass 21, count 0 2006.257.18:00:48.09#ibcon#*after write, iclass 21, count 0 2006.257.18:00:48.09#ibcon#*before return 0, iclass 21, count 0 2006.257.18:00:48.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:00:48.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:00:48.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:00:48.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:00:48.09$setupk4/ifdk4 2006.257.18:00:48.09$ifdk4/lo= 2006.257.18:00:48.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:00:48.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:00:48.09$ifdk4/patch= 2006.257.18:00:48.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:00:48.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:00:48.09$setupk4/!*+20s 2006.257.18:00:48.21#abcon#<5=/14 1.3 3.2 17.20 981014.3\r\n> 2006.257.18:00:48.23#abcon#{5=INTERFACE CLEAR} 2006.257.18:00:48.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:00:58.38#abcon#<5=/14 1.3 3.2 17.20 981014.2\r\n> 2006.257.18:00:58.40#abcon#{5=INTERFACE CLEAR} 2006.257.18:00:58.46#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:01:01.13#trakl#Source acquired 2006.257.18:01:02.14#flagr#flagr/antenna,acquired 2006.257.18:01:02.59$setupk4/"tpicd 2006.257.18:01:02.59$setupk4/echo=off 2006.257.18:01:02.59$setupk4/xlog=off 2006.257.18:01:02.59:!2006.257.18:01:27 2006.257.18:01:27.00:preob 2006.257.18:01:27.13/onsource/TRACKING 2006.257.18:01:27.13:!2006.257.18:01:37 2006.257.18:01:37.00:"tape 2006.257.18:01:37.00:"st=record 2006.257.18:01:37.00:data_valid=on 2006.257.18:01:37.00:midob 2006.257.18:01:38.13/onsource/TRACKING 2006.257.18:01:38.13/wx/17.20,1014.3,98 2006.257.18:01:38.29/cable/+6.4844E-03 2006.257.18:01:39.38/va/01,08,usb,yes,30,32 2006.257.18:01:39.38/va/02,07,usb,yes,33,33 2006.257.18:01:39.38/va/03,08,usb,yes,29,31 2006.257.18:01:39.38/va/04,07,usb,yes,34,35 2006.257.18:01:39.38/va/05,04,usb,yes,30,30 2006.257.18:01:39.38/va/06,04,usb,yes,34,33 2006.257.18:01:39.38/va/07,04,usb,yes,35,35 2006.257.18:01:39.38/va/08,04,usb,yes,29,35 2006.257.18:01:39.61/valo/01,524.99,yes,locked 2006.257.18:01:39.61/valo/02,534.99,yes,locked 2006.257.18:01:39.61/valo/03,564.99,yes,locked 2006.257.18:01:39.61/valo/04,624.99,yes,locked 2006.257.18:01:39.61/valo/05,734.99,yes,locked 2006.257.18:01:39.61/valo/06,814.99,yes,locked 2006.257.18:01:39.61/valo/07,864.99,yes,locked 2006.257.18:01:39.61/valo/08,884.99,yes,locked 2006.257.18:01:40.70/vb/01,04,usb,yes,30,28 2006.257.18:01:40.70/vb/02,05,usb,yes,29,29 2006.257.18:01:40.70/vb/03,04,usb,yes,30,33 2006.257.18:01:40.70/vb/04,05,usb,yes,30,29 2006.257.18:01:40.70/vb/05,04,usb,yes,26,29 2006.257.18:01:40.70/vb/06,04,usb,yes,31,27 2006.257.18:01:40.70/vb/07,04,usb,yes,31,31 2006.257.18:01:40.70/vb/08,04,usb,yes,28,32 2006.257.18:01:40.93/vblo/01,629.99,yes,locked 2006.257.18:01:40.93/vblo/02,634.99,yes,locked 2006.257.18:01:40.93/vblo/03,649.99,yes,locked 2006.257.18:01:40.93/vblo/04,679.99,yes,locked 2006.257.18:01:40.93/vblo/05,709.99,yes,locked 2006.257.18:01:40.93/vblo/06,719.99,yes,locked 2006.257.18:01:40.93/vblo/07,734.99,yes,locked 2006.257.18:01:40.93/vblo/08,744.99,yes,locked 2006.257.18:01:41.08/vabw/8 2006.257.18:01:41.23/vbbw/8 2006.257.18:01:41.32/xfe/off,on,15.0 2006.257.18:01:41.69/ifatt/23,28,28,28 2006.257.18:01:42.08/fmout-gps/S +4.50E-07 2006.257.18:01:42.11:!2006.257.18:09:57 2006.257.18:09:57.00:data_valid=off 2006.257.18:09:57.00:"et 2006.257.18:09:57.00:!+3s 2006.257.18:10:00.01:"tape 2006.257.18:10:00.01:postob 2006.257.18:10:00.23/cable/+6.4831E-03 2006.257.18:10:00.23/wx/17.21,1014.3,98 2006.257.18:10:01.07/fmout-gps/S +4.53E-07 2006.257.18:10:01.07:scan_name=257-1815,jd0609,100 2006.257.18:10:01.07:source=0528+134,053056.42,133155.1,2000.0,cw 2006.257.18:10:02.13#flagr#flagr/antenna,new-source 2006.257.18:10:02.13:checkk5 2006.257.18:10:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:10:02.86/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:10:03.21/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:10:03.56/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:10:03.89/chk_obsdata//k5ts1/T2571801??a.dat file size is correct (nominal:2000MB, actual:2000MB). 2006.257.18:10:04.23/chk_obsdata//k5ts2/T2571801??b.dat file size is correct (nominal:2000MB, actual:2000MB). 2006.257.18:10:04.56/chk_obsdata//k5ts3/T2571801??c.dat file size is correct (nominal:2000MB, actual:2000MB). 2006.257.18:10:04.89/chk_obsdata//k5ts4/T2571801??d.dat file size is correct (nominal:2000MB, actual:2000MB). 2006.257.18:10:05.55/k5log//k5ts1_log_newline 2006.257.18:10:06.22/k5log//k5ts2_log_newline 2006.257.18:10:06.88/k5log//k5ts3_log_newline 2006.257.18:10:07.53/k5log//k5ts4_log_newline 2006.257.18:10:07.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:10:07.56:setupk4=1 2006.257.18:10:07.56$setupk4/echo=on 2006.257.18:10:07.56$setupk4/pcalon 2006.257.18:10:07.56$pcalon/"no phase cal control is implemented here 2006.257.18:10:07.56$setupk4/"tpicd=stop 2006.257.18:10:07.56$setupk4/"rec=synch_on 2006.257.18:10:07.56$setupk4/"rec_mode=128 2006.257.18:10:07.56$setupk4/!* 2006.257.18:10:07.56$setupk4/recpk4 2006.257.18:10:07.56$recpk4/recpatch= 2006.257.18:10:07.57$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:10:07.57$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:10:07.57$setupk4/vck44 2006.257.18:10:07.57$vck44/valo=1,524.99 2006.257.18:10:07.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.18:10:07.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.18:10:07.57#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:07.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:07.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:07.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:07.57#ibcon#enter wrdev, iclass 30, count 0 2006.257.18:10:07.57#ibcon#first serial, iclass 30, count 0 2006.257.18:10:07.57#ibcon#enter sib2, iclass 30, count 0 2006.257.18:10:07.57#ibcon#flushed, iclass 30, count 0 2006.257.18:10:07.57#ibcon#about to write, iclass 30, count 0 2006.257.18:10:07.57#ibcon#wrote, iclass 30, count 0 2006.257.18:10:07.57#ibcon#about to read 3, iclass 30, count 0 2006.257.18:10:07.58#ibcon#read 3, iclass 30, count 0 2006.257.18:10:07.58#ibcon#about to read 4, iclass 30, count 0 2006.257.18:10:07.58#ibcon#read 4, iclass 30, count 0 2006.257.18:10:07.58#ibcon#about to read 5, iclass 30, count 0 2006.257.18:10:07.58#ibcon#read 5, iclass 30, count 0 2006.257.18:10:07.58#ibcon#about to read 6, iclass 30, count 0 2006.257.18:10:07.58#ibcon#read 6, iclass 30, count 0 2006.257.18:10:07.58#ibcon#end of sib2, iclass 30, count 0 2006.257.18:10:07.58#ibcon#*mode == 0, iclass 30, count 0 2006.257.18:10:07.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.18:10:07.58#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:10:07.58#ibcon#*before write, iclass 30, count 0 2006.257.18:10:07.58#ibcon#enter sib2, iclass 30, count 0 2006.257.18:10:07.58#ibcon#flushed, iclass 30, count 0 2006.257.18:10:07.58#ibcon#about to write, iclass 30, count 0 2006.257.18:10:07.58#ibcon#wrote, iclass 30, count 0 2006.257.18:10:07.58#ibcon#about to read 3, iclass 30, count 0 2006.257.18:10:07.63#abcon#<5=/14 1.5 3.4 17.21 981014.4\r\n> 2006.257.18:10:07.63#ibcon#read 3, iclass 30, count 0 2006.257.18:10:07.63#ibcon#about to read 4, iclass 30, count 0 2006.257.18:10:07.63#ibcon#read 4, iclass 30, count 0 2006.257.18:10:07.63#ibcon#about to read 5, iclass 30, count 0 2006.257.18:10:07.63#ibcon#read 5, iclass 30, count 0 2006.257.18:10:07.63#ibcon#about to read 6, iclass 30, count 0 2006.257.18:10:07.63#ibcon#read 6, iclass 30, count 0 2006.257.18:10:07.63#ibcon#end of sib2, iclass 30, count 0 2006.257.18:10:07.63#ibcon#*after write, iclass 30, count 0 2006.257.18:10:07.63#ibcon#*before return 0, iclass 30, count 0 2006.257.18:10:07.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:07.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:07.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.18:10:07.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.18:10:07.63$vck44/va=1,8 2006.257.18:10:07.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.18:10:07.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.18:10:07.63#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:07.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:10:07.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:10:07.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:10:07.63#ibcon#enter wrdev, iclass 35, count 2 2006.257.18:10:07.63#ibcon#first serial, iclass 35, count 2 2006.257.18:10:07.63#ibcon#enter sib2, iclass 35, count 2 2006.257.18:10:07.63#ibcon#flushed, iclass 35, count 2 2006.257.18:10:07.63#ibcon#about to write, iclass 35, count 2 2006.257.18:10:07.63#ibcon#wrote, iclass 35, count 2 2006.257.18:10:07.63#ibcon#about to read 3, iclass 35, count 2 2006.257.18:10:07.65#abcon#{5=INTERFACE CLEAR} 2006.257.18:10:07.65#ibcon#read 3, iclass 35, count 2 2006.257.18:10:07.65#ibcon#about to read 4, iclass 35, count 2 2006.257.18:10:07.65#ibcon#read 4, iclass 35, count 2 2006.257.18:10:07.65#ibcon#about to read 5, iclass 35, count 2 2006.257.18:10:07.65#ibcon#read 5, iclass 35, count 2 2006.257.18:10:07.65#ibcon#about to read 6, iclass 35, count 2 2006.257.18:10:07.65#ibcon#read 6, iclass 35, count 2 2006.257.18:10:07.65#ibcon#end of sib2, iclass 35, count 2 2006.257.18:10:07.65#ibcon#*mode == 0, iclass 35, count 2 2006.257.18:10:07.65#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.18:10:07.65#ibcon#[25=AT01-08\r\n] 2006.257.18:10:07.65#ibcon#*before write, iclass 35, count 2 2006.257.18:10:07.65#ibcon#enter sib2, iclass 35, count 2 2006.257.18:10:07.65#ibcon#flushed, iclass 35, count 2 2006.257.18:10:07.65#ibcon#about to write, iclass 35, count 2 2006.257.18:10:07.65#ibcon#wrote, iclass 35, count 2 2006.257.18:10:07.65#ibcon#about to read 3, iclass 35, count 2 2006.257.18:10:07.68#ibcon#read 3, iclass 35, count 2 2006.257.18:10:07.68#ibcon#about to read 4, iclass 35, count 2 2006.257.18:10:07.68#ibcon#read 4, iclass 35, count 2 2006.257.18:10:07.68#ibcon#about to read 5, iclass 35, count 2 2006.257.18:10:07.68#ibcon#read 5, iclass 35, count 2 2006.257.18:10:07.68#ibcon#about to read 6, iclass 35, count 2 2006.257.18:10:07.68#ibcon#read 6, iclass 35, count 2 2006.257.18:10:07.68#ibcon#end of sib2, iclass 35, count 2 2006.257.18:10:07.68#ibcon#*after write, iclass 35, count 2 2006.257.18:10:07.68#ibcon#*before return 0, iclass 35, count 2 2006.257.18:10:07.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:10:07.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:10:07.68#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.18:10:07.68#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:07.68#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:10:07.71#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:10:07.80#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:10:07.80#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:10:07.80#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:10:07.80#ibcon#first serial, iclass 35, count 0 2006.257.18:10:07.80#ibcon#enter sib2, iclass 35, count 0 2006.257.18:10:07.80#ibcon#flushed, iclass 35, count 0 2006.257.18:10:07.80#ibcon#about to write, iclass 35, count 0 2006.257.18:10:07.80#ibcon#wrote, iclass 35, count 0 2006.257.18:10:07.80#ibcon#about to read 3, iclass 35, count 0 2006.257.18:10:07.82#ibcon#read 3, iclass 35, count 0 2006.257.18:10:07.82#ibcon#about to read 4, iclass 35, count 0 2006.257.18:10:07.82#ibcon#read 4, iclass 35, count 0 2006.257.18:10:07.82#ibcon#about to read 5, iclass 35, count 0 2006.257.18:10:07.82#ibcon#read 5, iclass 35, count 0 2006.257.18:10:07.82#ibcon#about to read 6, iclass 35, count 0 2006.257.18:10:07.82#ibcon#read 6, iclass 35, count 0 2006.257.18:10:07.82#ibcon#end of sib2, iclass 35, count 0 2006.257.18:10:07.82#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:10:07.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:10:07.82#ibcon#[25=USB\r\n] 2006.257.18:10:07.82#ibcon#*before write, iclass 35, count 0 2006.257.18:10:07.82#ibcon#enter sib2, iclass 35, count 0 2006.257.18:10:07.82#ibcon#flushed, iclass 35, count 0 2006.257.18:10:07.82#ibcon#about to write, iclass 35, count 0 2006.257.18:10:07.82#ibcon#wrote, iclass 35, count 0 2006.257.18:10:07.82#ibcon#about to read 3, iclass 35, count 0 2006.257.18:10:07.85#ibcon#read 3, iclass 35, count 0 2006.257.18:10:07.85#ibcon#about to read 4, iclass 35, count 0 2006.257.18:10:07.85#ibcon#read 4, iclass 35, count 0 2006.257.18:10:07.85#ibcon#about to read 5, iclass 35, count 0 2006.257.18:10:07.85#ibcon#read 5, iclass 35, count 0 2006.257.18:10:07.85#ibcon#about to read 6, iclass 35, count 0 2006.257.18:10:07.85#ibcon#read 6, iclass 35, count 0 2006.257.18:10:07.85#ibcon#end of sib2, iclass 35, count 0 2006.257.18:10:07.85#ibcon#*after write, iclass 35, count 0 2006.257.18:10:07.85#ibcon#*before return 0, iclass 35, count 0 2006.257.18:10:07.85#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:10:07.85#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:10:07.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:10:07.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:10:07.85$vck44/valo=2,534.99 2006.257.18:10:07.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.18:10:07.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.18:10:07.85#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:07.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:07.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:07.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:07.85#ibcon#enter wrdev, iclass 38, count 0 2006.257.18:10:07.85#ibcon#first serial, iclass 38, count 0 2006.257.18:10:07.85#ibcon#enter sib2, iclass 38, count 0 2006.257.18:10:07.85#ibcon#flushed, iclass 38, count 0 2006.257.18:10:07.85#ibcon#about to write, iclass 38, count 0 2006.257.18:10:07.85#ibcon#wrote, iclass 38, count 0 2006.257.18:10:07.85#ibcon#about to read 3, iclass 38, count 0 2006.257.18:10:07.87#ibcon#read 3, iclass 38, count 0 2006.257.18:10:07.87#ibcon#about to read 4, iclass 38, count 0 2006.257.18:10:07.87#ibcon#read 4, iclass 38, count 0 2006.257.18:10:07.87#ibcon#about to read 5, iclass 38, count 0 2006.257.18:10:07.87#ibcon#read 5, iclass 38, count 0 2006.257.18:10:07.87#ibcon#about to read 6, iclass 38, count 0 2006.257.18:10:07.87#ibcon#read 6, iclass 38, count 0 2006.257.18:10:07.87#ibcon#end of sib2, iclass 38, count 0 2006.257.18:10:07.87#ibcon#*mode == 0, iclass 38, count 0 2006.257.18:10:07.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.18:10:07.87#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:10:07.87#ibcon#*before write, iclass 38, count 0 2006.257.18:10:07.87#ibcon#enter sib2, iclass 38, count 0 2006.257.18:10:07.87#ibcon#flushed, iclass 38, count 0 2006.257.18:10:07.87#ibcon#about to write, iclass 38, count 0 2006.257.18:10:07.87#ibcon#wrote, iclass 38, count 0 2006.257.18:10:07.87#ibcon#about to read 3, iclass 38, count 0 2006.257.18:10:07.91#ibcon#read 3, iclass 38, count 0 2006.257.18:10:07.91#ibcon#about to read 4, iclass 38, count 0 2006.257.18:10:07.91#ibcon#read 4, iclass 38, count 0 2006.257.18:10:07.91#ibcon#about to read 5, iclass 38, count 0 2006.257.18:10:07.91#ibcon#read 5, iclass 38, count 0 2006.257.18:10:07.91#ibcon#about to read 6, iclass 38, count 0 2006.257.18:10:07.91#ibcon#read 6, iclass 38, count 0 2006.257.18:10:07.91#ibcon#end of sib2, iclass 38, count 0 2006.257.18:10:07.91#ibcon#*after write, iclass 38, count 0 2006.257.18:10:07.91#ibcon#*before return 0, iclass 38, count 0 2006.257.18:10:07.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:07.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:07.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.18:10:07.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.18:10:07.91$vck44/va=2,7 2006.257.18:10:07.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.18:10:07.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.18:10:07.91#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:07.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:07.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:07.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:07.97#ibcon#enter wrdev, iclass 40, count 2 2006.257.18:10:07.97#ibcon#first serial, iclass 40, count 2 2006.257.18:10:07.97#ibcon#enter sib2, iclass 40, count 2 2006.257.18:10:07.97#ibcon#flushed, iclass 40, count 2 2006.257.18:10:07.97#ibcon#about to write, iclass 40, count 2 2006.257.18:10:07.97#ibcon#wrote, iclass 40, count 2 2006.257.18:10:07.97#ibcon#about to read 3, iclass 40, count 2 2006.257.18:10:07.99#ibcon#read 3, iclass 40, count 2 2006.257.18:10:07.99#ibcon#about to read 4, iclass 40, count 2 2006.257.18:10:07.99#ibcon#read 4, iclass 40, count 2 2006.257.18:10:07.99#ibcon#about to read 5, iclass 40, count 2 2006.257.18:10:07.99#ibcon#read 5, iclass 40, count 2 2006.257.18:10:07.99#ibcon#about to read 6, iclass 40, count 2 2006.257.18:10:07.99#ibcon#read 6, iclass 40, count 2 2006.257.18:10:07.99#ibcon#end of sib2, iclass 40, count 2 2006.257.18:10:07.99#ibcon#*mode == 0, iclass 40, count 2 2006.257.18:10:07.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.18:10:07.99#ibcon#[25=AT02-07\r\n] 2006.257.18:10:07.99#ibcon#*before write, iclass 40, count 2 2006.257.18:10:07.99#ibcon#enter sib2, iclass 40, count 2 2006.257.18:10:07.99#ibcon#flushed, iclass 40, count 2 2006.257.18:10:07.99#ibcon#about to write, iclass 40, count 2 2006.257.18:10:07.99#ibcon#wrote, iclass 40, count 2 2006.257.18:10:07.99#ibcon#about to read 3, iclass 40, count 2 2006.257.18:10:08.02#ibcon#read 3, iclass 40, count 2 2006.257.18:10:08.02#ibcon#about to read 4, iclass 40, count 2 2006.257.18:10:08.02#ibcon#read 4, iclass 40, count 2 2006.257.18:10:08.02#ibcon#about to read 5, iclass 40, count 2 2006.257.18:10:08.02#ibcon#read 5, iclass 40, count 2 2006.257.18:10:08.02#ibcon#about to read 6, iclass 40, count 2 2006.257.18:10:08.02#ibcon#read 6, iclass 40, count 2 2006.257.18:10:08.02#ibcon#end of sib2, iclass 40, count 2 2006.257.18:10:08.02#ibcon#*after write, iclass 40, count 2 2006.257.18:10:08.02#ibcon#*before return 0, iclass 40, count 2 2006.257.18:10:08.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:08.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:08.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.18:10:08.02#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:08.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:08.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:08.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:08.14#ibcon#enter wrdev, iclass 40, count 0 2006.257.18:10:08.14#ibcon#first serial, iclass 40, count 0 2006.257.18:10:08.14#ibcon#enter sib2, iclass 40, count 0 2006.257.18:10:08.14#ibcon#flushed, iclass 40, count 0 2006.257.18:10:08.14#ibcon#about to write, iclass 40, count 0 2006.257.18:10:08.14#ibcon#wrote, iclass 40, count 0 2006.257.18:10:08.14#ibcon#about to read 3, iclass 40, count 0 2006.257.18:10:08.16#ibcon#read 3, iclass 40, count 0 2006.257.18:10:08.16#ibcon#about to read 4, iclass 40, count 0 2006.257.18:10:08.16#ibcon#read 4, iclass 40, count 0 2006.257.18:10:08.16#ibcon#about to read 5, iclass 40, count 0 2006.257.18:10:08.16#ibcon#read 5, iclass 40, count 0 2006.257.18:10:08.16#ibcon#about to read 6, iclass 40, count 0 2006.257.18:10:08.16#ibcon#read 6, iclass 40, count 0 2006.257.18:10:08.16#ibcon#end of sib2, iclass 40, count 0 2006.257.18:10:08.16#ibcon#*mode == 0, iclass 40, count 0 2006.257.18:10:08.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.18:10:08.16#ibcon#[25=USB\r\n] 2006.257.18:10:08.16#ibcon#*before write, iclass 40, count 0 2006.257.18:10:08.16#ibcon#enter sib2, iclass 40, count 0 2006.257.18:10:08.16#ibcon#flushed, iclass 40, count 0 2006.257.18:10:08.16#ibcon#about to write, iclass 40, count 0 2006.257.18:10:08.16#ibcon#wrote, iclass 40, count 0 2006.257.18:10:08.16#ibcon#about to read 3, iclass 40, count 0 2006.257.18:10:08.19#ibcon#read 3, iclass 40, count 0 2006.257.18:10:08.19#ibcon#about to read 4, iclass 40, count 0 2006.257.18:10:08.19#ibcon#read 4, iclass 40, count 0 2006.257.18:10:08.19#ibcon#about to read 5, iclass 40, count 0 2006.257.18:10:08.19#ibcon#read 5, iclass 40, count 0 2006.257.18:10:08.19#ibcon#about to read 6, iclass 40, count 0 2006.257.18:10:08.19#ibcon#read 6, iclass 40, count 0 2006.257.18:10:08.19#ibcon#end of sib2, iclass 40, count 0 2006.257.18:10:08.19#ibcon#*after write, iclass 40, count 0 2006.257.18:10:08.19#ibcon#*before return 0, iclass 40, count 0 2006.257.18:10:08.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:08.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:08.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.18:10:08.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.18:10:08.19$vck44/valo=3,564.99 2006.257.18:10:08.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.18:10:08.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.18:10:08.19#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:08.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:08.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:08.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:08.19#ibcon#enter wrdev, iclass 4, count 0 2006.257.18:10:08.19#ibcon#first serial, iclass 4, count 0 2006.257.18:10:08.19#ibcon#enter sib2, iclass 4, count 0 2006.257.18:10:08.19#ibcon#flushed, iclass 4, count 0 2006.257.18:10:08.19#ibcon#about to write, iclass 4, count 0 2006.257.18:10:08.19#ibcon#wrote, iclass 4, count 0 2006.257.18:10:08.19#ibcon#about to read 3, iclass 4, count 0 2006.257.18:10:08.21#ibcon#read 3, iclass 4, count 0 2006.257.18:10:08.21#ibcon#about to read 4, iclass 4, count 0 2006.257.18:10:08.21#ibcon#read 4, iclass 4, count 0 2006.257.18:10:08.21#ibcon#about to read 5, iclass 4, count 0 2006.257.18:10:08.21#ibcon#read 5, iclass 4, count 0 2006.257.18:10:08.21#ibcon#about to read 6, iclass 4, count 0 2006.257.18:10:08.21#ibcon#read 6, iclass 4, count 0 2006.257.18:10:08.21#ibcon#end of sib2, iclass 4, count 0 2006.257.18:10:08.21#ibcon#*mode == 0, iclass 4, count 0 2006.257.18:10:08.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.18:10:08.21#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:10:08.21#ibcon#*before write, iclass 4, count 0 2006.257.18:10:08.21#ibcon#enter sib2, iclass 4, count 0 2006.257.18:10:08.21#ibcon#flushed, iclass 4, count 0 2006.257.18:10:08.21#ibcon#about to write, iclass 4, count 0 2006.257.18:10:08.21#ibcon#wrote, iclass 4, count 0 2006.257.18:10:08.21#ibcon#about to read 3, iclass 4, count 0 2006.257.18:10:08.25#ibcon#read 3, iclass 4, count 0 2006.257.18:10:08.25#ibcon#about to read 4, iclass 4, count 0 2006.257.18:10:08.25#ibcon#read 4, iclass 4, count 0 2006.257.18:10:08.25#ibcon#about to read 5, iclass 4, count 0 2006.257.18:10:08.25#ibcon#read 5, iclass 4, count 0 2006.257.18:10:08.25#ibcon#about to read 6, iclass 4, count 0 2006.257.18:10:08.25#ibcon#read 6, iclass 4, count 0 2006.257.18:10:08.25#ibcon#end of sib2, iclass 4, count 0 2006.257.18:10:08.25#ibcon#*after write, iclass 4, count 0 2006.257.18:10:08.25#ibcon#*before return 0, iclass 4, count 0 2006.257.18:10:08.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:08.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:08.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.18:10:08.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.18:10:08.25$vck44/va=3,8 2006.257.18:10:08.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.18:10:08.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.18:10:08.25#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:08.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:08.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:08.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:08.31#ibcon#enter wrdev, iclass 6, count 2 2006.257.18:10:08.31#ibcon#first serial, iclass 6, count 2 2006.257.18:10:08.31#ibcon#enter sib2, iclass 6, count 2 2006.257.18:10:08.31#ibcon#flushed, iclass 6, count 2 2006.257.18:10:08.31#ibcon#about to write, iclass 6, count 2 2006.257.18:10:08.31#ibcon#wrote, iclass 6, count 2 2006.257.18:10:08.31#ibcon#about to read 3, iclass 6, count 2 2006.257.18:10:08.33#ibcon#read 3, iclass 6, count 2 2006.257.18:10:08.33#ibcon#about to read 4, iclass 6, count 2 2006.257.18:10:08.33#ibcon#read 4, iclass 6, count 2 2006.257.18:10:08.33#ibcon#about to read 5, iclass 6, count 2 2006.257.18:10:08.33#ibcon#read 5, iclass 6, count 2 2006.257.18:10:08.33#ibcon#about to read 6, iclass 6, count 2 2006.257.18:10:08.33#ibcon#read 6, iclass 6, count 2 2006.257.18:10:08.33#ibcon#end of sib2, iclass 6, count 2 2006.257.18:10:08.33#ibcon#*mode == 0, iclass 6, count 2 2006.257.18:10:08.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.18:10:08.33#ibcon#[25=AT03-08\r\n] 2006.257.18:10:08.33#ibcon#*before write, iclass 6, count 2 2006.257.18:10:08.33#ibcon#enter sib2, iclass 6, count 2 2006.257.18:10:08.33#ibcon#flushed, iclass 6, count 2 2006.257.18:10:08.33#ibcon#about to write, iclass 6, count 2 2006.257.18:10:08.33#ibcon#wrote, iclass 6, count 2 2006.257.18:10:08.33#ibcon#about to read 3, iclass 6, count 2 2006.257.18:10:08.36#ibcon#read 3, iclass 6, count 2 2006.257.18:10:08.36#ibcon#about to read 4, iclass 6, count 2 2006.257.18:10:08.36#ibcon#read 4, iclass 6, count 2 2006.257.18:10:08.36#ibcon#about to read 5, iclass 6, count 2 2006.257.18:10:08.36#ibcon#read 5, iclass 6, count 2 2006.257.18:10:08.36#ibcon#about to read 6, iclass 6, count 2 2006.257.18:10:08.36#ibcon#read 6, iclass 6, count 2 2006.257.18:10:08.36#ibcon#end of sib2, iclass 6, count 2 2006.257.18:10:08.36#ibcon#*after write, iclass 6, count 2 2006.257.18:10:08.36#ibcon#*before return 0, iclass 6, count 2 2006.257.18:10:08.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:08.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:08.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.18:10:08.36#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:08.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:08.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:08.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:08.48#ibcon#enter wrdev, iclass 6, count 0 2006.257.18:10:08.48#ibcon#first serial, iclass 6, count 0 2006.257.18:10:08.48#ibcon#enter sib2, iclass 6, count 0 2006.257.18:10:08.48#ibcon#flushed, iclass 6, count 0 2006.257.18:10:08.48#ibcon#about to write, iclass 6, count 0 2006.257.18:10:08.48#ibcon#wrote, iclass 6, count 0 2006.257.18:10:08.48#ibcon#about to read 3, iclass 6, count 0 2006.257.18:10:08.50#ibcon#read 3, iclass 6, count 0 2006.257.18:10:08.50#ibcon#about to read 4, iclass 6, count 0 2006.257.18:10:08.50#ibcon#read 4, iclass 6, count 0 2006.257.18:10:08.50#ibcon#about to read 5, iclass 6, count 0 2006.257.18:10:08.50#ibcon#read 5, iclass 6, count 0 2006.257.18:10:08.50#ibcon#about to read 6, iclass 6, count 0 2006.257.18:10:08.50#ibcon#read 6, iclass 6, count 0 2006.257.18:10:08.50#ibcon#end of sib2, iclass 6, count 0 2006.257.18:10:08.50#ibcon#*mode == 0, iclass 6, count 0 2006.257.18:10:08.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.18:10:08.50#ibcon#[25=USB\r\n] 2006.257.18:10:08.50#ibcon#*before write, iclass 6, count 0 2006.257.18:10:08.50#ibcon#enter sib2, iclass 6, count 0 2006.257.18:10:08.50#ibcon#flushed, iclass 6, count 0 2006.257.18:10:08.50#ibcon#about to write, iclass 6, count 0 2006.257.18:10:08.50#ibcon#wrote, iclass 6, count 0 2006.257.18:10:08.50#ibcon#about to read 3, iclass 6, count 0 2006.257.18:10:08.53#ibcon#read 3, iclass 6, count 0 2006.257.18:10:08.53#ibcon#about to read 4, iclass 6, count 0 2006.257.18:10:08.53#ibcon#read 4, iclass 6, count 0 2006.257.18:10:08.53#ibcon#about to read 5, iclass 6, count 0 2006.257.18:10:08.53#ibcon#read 5, iclass 6, count 0 2006.257.18:10:08.53#ibcon#about to read 6, iclass 6, count 0 2006.257.18:10:08.53#ibcon#read 6, iclass 6, count 0 2006.257.18:10:08.53#ibcon#end of sib2, iclass 6, count 0 2006.257.18:10:08.53#ibcon#*after write, iclass 6, count 0 2006.257.18:10:08.53#ibcon#*before return 0, iclass 6, count 0 2006.257.18:10:08.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:08.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:08.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.18:10:08.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.18:10:08.53$vck44/valo=4,624.99 2006.257.18:10:08.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.18:10:08.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.18:10:08.53#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:08.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:08.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:08.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:08.53#ibcon#enter wrdev, iclass 10, count 0 2006.257.18:10:08.53#ibcon#first serial, iclass 10, count 0 2006.257.18:10:08.53#ibcon#enter sib2, iclass 10, count 0 2006.257.18:10:08.53#ibcon#flushed, iclass 10, count 0 2006.257.18:10:08.53#ibcon#about to write, iclass 10, count 0 2006.257.18:10:08.53#ibcon#wrote, iclass 10, count 0 2006.257.18:10:08.53#ibcon#about to read 3, iclass 10, count 0 2006.257.18:10:08.55#ibcon#read 3, iclass 10, count 0 2006.257.18:10:08.55#ibcon#about to read 4, iclass 10, count 0 2006.257.18:10:08.55#ibcon#read 4, iclass 10, count 0 2006.257.18:10:08.55#ibcon#about to read 5, iclass 10, count 0 2006.257.18:10:08.55#ibcon#read 5, iclass 10, count 0 2006.257.18:10:08.55#ibcon#about to read 6, iclass 10, count 0 2006.257.18:10:08.55#ibcon#read 6, iclass 10, count 0 2006.257.18:10:08.55#ibcon#end of sib2, iclass 10, count 0 2006.257.18:10:08.55#ibcon#*mode == 0, iclass 10, count 0 2006.257.18:10:08.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.18:10:08.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:10:08.55#ibcon#*before write, iclass 10, count 0 2006.257.18:10:08.55#ibcon#enter sib2, iclass 10, count 0 2006.257.18:10:08.55#ibcon#flushed, iclass 10, count 0 2006.257.18:10:08.55#ibcon#about to write, iclass 10, count 0 2006.257.18:10:08.55#ibcon#wrote, iclass 10, count 0 2006.257.18:10:08.55#ibcon#about to read 3, iclass 10, count 0 2006.257.18:10:08.59#ibcon#read 3, iclass 10, count 0 2006.257.18:10:08.59#ibcon#about to read 4, iclass 10, count 0 2006.257.18:10:08.59#ibcon#read 4, iclass 10, count 0 2006.257.18:10:08.59#ibcon#about to read 5, iclass 10, count 0 2006.257.18:10:08.59#ibcon#read 5, iclass 10, count 0 2006.257.18:10:08.59#ibcon#about to read 6, iclass 10, count 0 2006.257.18:10:08.59#ibcon#read 6, iclass 10, count 0 2006.257.18:10:08.59#ibcon#end of sib2, iclass 10, count 0 2006.257.18:10:08.59#ibcon#*after write, iclass 10, count 0 2006.257.18:10:08.59#ibcon#*before return 0, iclass 10, count 0 2006.257.18:10:08.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:08.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:08.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.18:10:08.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.18:10:08.59$vck44/va=4,7 2006.257.18:10:08.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.18:10:08.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.18:10:08.59#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:08.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:08.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:08.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:08.65#ibcon#enter wrdev, iclass 12, count 2 2006.257.18:10:08.65#ibcon#first serial, iclass 12, count 2 2006.257.18:10:08.65#ibcon#enter sib2, iclass 12, count 2 2006.257.18:10:08.65#ibcon#flushed, iclass 12, count 2 2006.257.18:10:08.65#ibcon#about to write, iclass 12, count 2 2006.257.18:10:08.65#ibcon#wrote, iclass 12, count 2 2006.257.18:10:08.65#ibcon#about to read 3, iclass 12, count 2 2006.257.18:10:08.67#ibcon#read 3, iclass 12, count 2 2006.257.18:10:08.67#ibcon#about to read 4, iclass 12, count 2 2006.257.18:10:08.67#ibcon#read 4, iclass 12, count 2 2006.257.18:10:08.67#ibcon#about to read 5, iclass 12, count 2 2006.257.18:10:08.67#ibcon#read 5, iclass 12, count 2 2006.257.18:10:08.67#ibcon#about to read 6, iclass 12, count 2 2006.257.18:10:08.67#ibcon#read 6, iclass 12, count 2 2006.257.18:10:08.67#ibcon#end of sib2, iclass 12, count 2 2006.257.18:10:08.67#ibcon#*mode == 0, iclass 12, count 2 2006.257.18:10:08.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.18:10:08.67#ibcon#[25=AT04-07\r\n] 2006.257.18:10:08.67#ibcon#*before write, iclass 12, count 2 2006.257.18:10:08.67#ibcon#enter sib2, iclass 12, count 2 2006.257.18:10:08.67#ibcon#flushed, iclass 12, count 2 2006.257.18:10:08.67#ibcon#about to write, iclass 12, count 2 2006.257.18:10:08.67#ibcon#wrote, iclass 12, count 2 2006.257.18:10:08.67#ibcon#about to read 3, iclass 12, count 2 2006.257.18:10:08.70#ibcon#read 3, iclass 12, count 2 2006.257.18:10:08.70#ibcon#about to read 4, iclass 12, count 2 2006.257.18:10:08.70#ibcon#read 4, iclass 12, count 2 2006.257.18:10:08.70#ibcon#about to read 5, iclass 12, count 2 2006.257.18:10:08.70#ibcon#read 5, iclass 12, count 2 2006.257.18:10:08.70#ibcon#about to read 6, iclass 12, count 2 2006.257.18:10:08.70#ibcon#read 6, iclass 12, count 2 2006.257.18:10:08.70#ibcon#end of sib2, iclass 12, count 2 2006.257.18:10:08.70#ibcon#*after write, iclass 12, count 2 2006.257.18:10:08.70#ibcon#*before return 0, iclass 12, count 2 2006.257.18:10:08.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:08.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:08.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.18:10:08.70#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:08.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:08.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:08.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:08.82#ibcon#enter wrdev, iclass 12, count 0 2006.257.18:10:08.82#ibcon#first serial, iclass 12, count 0 2006.257.18:10:08.82#ibcon#enter sib2, iclass 12, count 0 2006.257.18:10:08.82#ibcon#flushed, iclass 12, count 0 2006.257.18:10:08.82#ibcon#about to write, iclass 12, count 0 2006.257.18:10:08.82#ibcon#wrote, iclass 12, count 0 2006.257.18:10:08.82#ibcon#about to read 3, iclass 12, count 0 2006.257.18:10:08.84#ibcon#read 3, iclass 12, count 0 2006.257.18:10:08.84#ibcon#about to read 4, iclass 12, count 0 2006.257.18:10:08.84#ibcon#read 4, iclass 12, count 0 2006.257.18:10:08.84#ibcon#about to read 5, iclass 12, count 0 2006.257.18:10:08.84#ibcon#read 5, iclass 12, count 0 2006.257.18:10:08.84#ibcon#about to read 6, iclass 12, count 0 2006.257.18:10:08.84#ibcon#read 6, iclass 12, count 0 2006.257.18:10:08.84#ibcon#end of sib2, iclass 12, count 0 2006.257.18:10:08.84#ibcon#*mode == 0, iclass 12, count 0 2006.257.18:10:08.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.18:10:08.84#ibcon#[25=USB\r\n] 2006.257.18:10:08.84#ibcon#*before write, iclass 12, count 0 2006.257.18:10:08.84#ibcon#enter sib2, iclass 12, count 0 2006.257.18:10:08.84#ibcon#flushed, iclass 12, count 0 2006.257.18:10:08.84#ibcon#about to write, iclass 12, count 0 2006.257.18:10:08.84#ibcon#wrote, iclass 12, count 0 2006.257.18:10:08.84#ibcon#about to read 3, iclass 12, count 0 2006.257.18:10:08.87#ibcon#read 3, iclass 12, count 0 2006.257.18:10:08.87#ibcon#about to read 4, iclass 12, count 0 2006.257.18:10:08.87#ibcon#read 4, iclass 12, count 0 2006.257.18:10:08.87#ibcon#about to read 5, iclass 12, count 0 2006.257.18:10:08.87#ibcon#read 5, iclass 12, count 0 2006.257.18:10:08.87#ibcon#about to read 6, iclass 12, count 0 2006.257.18:10:08.87#ibcon#read 6, iclass 12, count 0 2006.257.18:10:08.87#ibcon#end of sib2, iclass 12, count 0 2006.257.18:10:08.87#ibcon#*after write, iclass 12, count 0 2006.257.18:10:08.87#ibcon#*before return 0, iclass 12, count 0 2006.257.18:10:08.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:08.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:08.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.18:10:08.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.18:10:08.87$vck44/valo=5,734.99 2006.257.18:10:08.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.18:10:08.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.18:10:08.87#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:08.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:08.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:08.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:08.87#ibcon#enter wrdev, iclass 14, count 0 2006.257.18:10:08.87#ibcon#first serial, iclass 14, count 0 2006.257.18:10:08.87#ibcon#enter sib2, iclass 14, count 0 2006.257.18:10:08.87#ibcon#flushed, iclass 14, count 0 2006.257.18:10:08.87#ibcon#about to write, iclass 14, count 0 2006.257.18:10:08.87#ibcon#wrote, iclass 14, count 0 2006.257.18:10:08.87#ibcon#about to read 3, iclass 14, count 0 2006.257.18:10:08.89#ibcon#read 3, iclass 14, count 0 2006.257.18:10:08.89#ibcon#about to read 4, iclass 14, count 0 2006.257.18:10:08.89#ibcon#read 4, iclass 14, count 0 2006.257.18:10:08.89#ibcon#about to read 5, iclass 14, count 0 2006.257.18:10:08.89#ibcon#read 5, iclass 14, count 0 2006.257.18:10:08.89#ibcon#about to read 6, iclass 14, count 0 2006.257.18:10:08.89#ibcon#read 6, iclass 14, count 0 2006.257.18:10:08.89#ibcon#end of sib2, iclass 14, count 0 2006.257.18:10:08.89#ibcon#*mode == 0, iclass 14, count 0 2006.257.18:10:08.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.18:10:08.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:10:08.89#ibcon#*before write, iclass 14, count 0 2006.257.18:10:08.89#ibcon#enter sib2, iclass 14, count 0 2006.257.18:10:08.89#ibcon#flushed, iclass 14, count 0 2006.257.18:10:08.89#ibcon#about to write, iclass 14, count 0 2006.257.18:10:08.89#ibcon#wrote, iclass 14, count 0 2006.257.18:10:08.89#ibcon#about to read 3, iclass 14, count 0 2006.257.18:10:08.93#ibcon#read 3, iclass 14, count 0 2006.257.18:10:08.93#ibcon#about to read 4, iclass 14, count 0 2006.257.18:10:08.93#ibcon#read 4, iclass 14, count 0 2006.257.18:10:08.93#ibcon#about to read 5, iclass 14, count 0 2006.257.18:10:08.93#ibcon#read 5, iclass 14, count 0 2006.257.18:10:08.93#ibcon#about to read 6, iclass 14, count 0 2006.257.18:10:08.93#ibcon#read 6, iclass 14, count 0 2006.257.18:10:08.93#ibcon#end of sib2, iclass 14, count 0 2006.257.18:10:08.93#ibcon#*after write, iclass 14, count 0 2006.257.18:10:08.93#ibcon#*before return 0, iclass 14, count 0 2006.257.18:10:08.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:08.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:08.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.18:10:08.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.18:10:08.93$vck44/va=5,4 2006.257.18:10:08.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.18:10:08.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.18:10:08.93#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:08.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:08.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:08.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:08.99#ibcon#enter wrdev, iclass 16, count 2 2006.257.18:10:08.99#ibcon#first serial, iclass 16, count 2 2006.257.18:10:08.99#ibcon#enter sib2, iclass 16, count 2 2006.257.18:10:08.99#ibcon#flushed, iclass 16, count 2 2006.257.18:10:08.99#ibcon#about to write, iclass 16, count 2 2006.257.18:10:08.99#ibcon#wrote, iclass 16, count 2 2006.257.18:10:08.99#ibcon#about to read 3, iclass 16, count 2 2006.257.18:10:09.01#ibcon#read 3, iclass 16, count 2 2006.257.18:10:09.01#ibcon#about to read 4, iclass 16, count 2 2006.257.18:10:09.01#ibcon#read 4, iclass 16, count 2 2006.257.18:10:09.01#ibcon#about to read 5, iclass 16, count 2 2006.257.18:10:09.01#ibcon#read 5, iclass 16, count 2 2006.257.18:10:09.01#ibcon#about to read 6, iclass 16, count 2 2006.257.18:10:09.01#ibcon#read 6, iclass 16, count 2 2006.257.18:10:09.01#ibcon#end of sib2, iclass 16, count 2 2006.257.18:10:09.01#ibcon#*mode == 0, iclass 16, count 2 2006.257.18:10:09.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.18:10:09.01#ibcon#[25=AT05-04\r\n] 2006.257.18:10:09.01#ibcon#*before write, iclass 16, count 2 2006.257.18:10:09.01#ibcon#enter sib2, iclass 16, count 2 2006.257.18:10:09.01#ibcon#flushed, iclass 16, count 2 2006.257.18:10:09.01#ibcon#about to write, iclass 16, count 2 2006.257.18:10:09.01#ibcon#wrote, iclass 16, count 2 2006.257.18:10:09.01#ibcon#about to read 3, iclass 16, count 2 2006.257.18:10:09.04#ibcon#read 3, iclass 16, count 2 2006.257.18:10:09.04#ibcon#about to read 4, iclass 16, count 2 2006.257.18:10:09.04#ibcon#read 4, iclass 16, count 2 2006.257.18:10:09.04#ibcon#about to read 5, iclass 16, count 2 2006.257.18:10:09.04#ibcon#read 5, iclass 16, count 2 2006.257.18:10:09.04#ibcon#about to read 6, iclass 16, count 2 2006.257.18:10:09.04#ibcon#read 6, iclass 16, count 2 2006.257.18:10:09.04#ibcon#end of sib2, iclass 16, count 2 2006.257.18:10:09.04#ibcon#*after write, iclass 16, count 2 2006.257.18:10:09.04#ibcon#*before return 0, iclass 16, count 2 2006.257.18:10:09.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:09.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:09.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.18:10:09.04#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:09.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:09.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:09.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:09.16#ibcon#enter wrdev, iclass 16, count 0 2006.257.18:10:09.16#ibcon#first serial, iclass 16, count 0 2006.257.18:10:09.16#ibcon#enter sib2, iclass 16, count 0 2006.257.18:10:09.16#ibcon#flushed, iclass 16, count 0 2006.257.18:10:09.16#ibcon#about to write, iclass 16, count 0 2006.257.18:10:09.16#ibcon#wrote, iclass 16, count 0 2006.257.18:10:09.16#ibcon#about to read 3, iclass 16, count 0 2006.257.18:10:09.18#ibcon#read 3, iclass 16, count 0 2006.257.18:10:09.18#ibcon#about to read 4, iclass 16, count 0 2006.257.18:10:09.18#ibcon#read 4, iclass 16, count 0 2006.257.18:10:09.18#ibcon#about to read 5, iclass 16, count 0 2006.257.18:10:09.18#ibcon#read 5, iclass 16, count 0 2006.257.18:10:09.18#ibcon#about to read 6, iclass 16, count 0 2006.257.18:10:09.18#ibcon#read 6, iclass 16, count 0 2006.257.18:10:09.18#ibcon#end of sib2, iclass 16, count 0 2006.257.18:10:09.18#ibcon#*mode == 0, iclass 16, count 0 2006.257.18:10:09.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.18:10:09.18#ibcon#[25=USB\r\n] 2006.257.18:10:09.18#ibcon#*before write, iclass 16, count 0 2006.257.18:10:09.18#ibcon#enter sib2, iclass 16, count 0 2006.257.18:10:09.18#ibcon#flushed, iclass 16, count 0 2006.257.18:10:09.18#ibcon#about to write, iclass 16, count 0 2006.257.18:10:09.18#ibcon#wrote, iclass 16, count 0 2006.257.18:10:09.18#ibcon#about to read 3, iclass 16, count 0 2006.257.18:10:09.21#ibcon#read 3, iclass 16, count 0 2006.257.18:10:09.21#ibcon#about to read 4, iclass 16, count 0 2006.257.18:10:09.21#ibcon#read 4, iclass 16, count 0 2006.257.18:10:09.21#ibcon#about to read 5, iclass 16, count 0 2006.257.18:10:09.21#ibcon#read 5, iclass 16, count 0 2006.257.18:10:09.21#ibcon#about to read 6, iclass 16, count 0 2006.257.18:10:09.21#ibcon#read 6, iclass 16, count 0 2006.257.18:10:09.21#ibcon#end of sib2, iclass 16, count 0 2006.257.18:10:09.21#ibcon#*after write, iclass 16, count 0 2006.257.18:10:09.21#ibcon#*before return 0, iclass 16, count 0 2006.257.18:10:09.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:09.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:09.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.18:10:09.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.18:10:09.21$vck44/valo=6,814.99 2006.257.18:10:09.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.18:10:09.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.18:10:09.21#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:09.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:09.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:09.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:09.21#ibcon#enter wrdev, iclass 18, count 0 2006.257.18:10:09.21#ibcon#first serial, iclass 18, count 0 2006.257.18:10:09.21#ibcon#enter sib2, iclass 18, count 0 2006.257.18:10:09.21#ibcon#flushed, iclass 18, count 0 2006.257.18:10:09.21#ibcon#about to write, iclass 18, count 0 2006.257.18:10:09.21#ibcon#wrote, iclass 18, count 0 2006.257.18:10:09.21#ibcon#about to read 3, iclass 18, count 0 2006.257.18:10:09.23#ibcon#read 3, iclass 18, count 0 2006.257.18:10:09.23#ibcon#about to read 4, iclass 18, count 0 2006.257.18:10:09.23#ibcon#read 4, iclass 18, count 0 2006.257.18:10:09.23#ibcon#about to read 5, iclass 18, count 0 2006.257.18:10:09.23#ibcon#read 5, iclass 18, count 0 2006.257.18:10:09.23#ibcon#about to read 6, iclass 18, count 0 2006.257.18:10:09.23#ibcon#read 6, iclass 18, count 0 2006.257.18:10:09.23#ibcon#end of sib2, iclass 18, count 0 2006.257.18:10:09.23#ibcon#*mode == 0, iclass 18, count 0 2006.257.18:10:09.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.18:10:09.23#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:10:09.23#ibcon#*before write, iclass 18, count 0 2006.257.18:10:09.23#ibcon#enter sib2, iclass 18, count 0 2006.257.18:10:09.23#ibcon#flushed, iclass 18, count 0 2006.257.18:10:09.23#ibcon#about to write, iclass 18, count 0 2006.257.18:10:09.23#ibcon#wrote, iclass 18, count 0 2006.257.18:10:09.23#ibcon#about to read 3, iclass 18, count 0 2006.257.18:10:09.27#ibcon#read 3, iclass 18, count 0 2006.257.18:10:09.27#ibcon#about to read 4, iclass 18, count 0 2006.257.18:10:09.27#ibcon#read 4, iclass 18, count 0 2006.257.18:10:09.27#ibcon#about to read 5, iclass 18, count 0 2006.257.18:10:09.27#ibcon#read 5, iclass 18, count 0 2006.257.18:10:09.27#ibcon#about to read 6, iclass 18, count 0 2006.257.18:10:09.27#ibcon#read 6, iclass 18, count 0 2006.257.18:10:09.27#ibcon#end of sib2, iclass 18, count 0 2006.257.18:10:09.27#ibcon#*after write, iclass 18, count 0 2006.257.18:10:09.27#ibcon#*before return 0, iclass 18, count 0 2006.257.18:10:09.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:09.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:09.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.18:10:09.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.18:10:09.27$vck44/va=6,4 2006.257.18:10:09.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.18:10:09.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.18:10:09.27#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:09.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:09.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:09.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:09.33#ibcon#enter wrdev, iclass 20, count 2 2006.257.18:10:09.33#ibcon#first serial, iclass 20, count 2 2006.257.18:10:09.33#ibcon#enter sib2, iclass 20, count 2 2006.257.18:10:09.33#ibcon#flushed, iclass 20, count 2 2006.257.18:10:09.33#ibcon#about to write, iclass 20, count 2 2006.257.18:10:09.33#ibcon#wrote, iclass 20, count 2 2006.257.18:10:09.33#ibcon#about to read 3, iclass 20, count 2 2006.257.18:10:09.35#ibcon#read 3, iclass 20, count 2 2006.257.18:10:09.35#ibcon#about to read 4, iclass 20, count 2 2006.257.18:10:09.35#ibcon#read 4, iclass 20, count 2 2006.257.18:10:09.35#ibcon#about to read 5, iclass 20, count 2 2006.257.18:10:09.35#ibcon#read 5, iclass 20, count 2 2006.257.18:10:09.35#ibcon#about to read 6, iclass 20, count 2 2006.257.18:10:09.35#ibcon#read 6, iclass 20, count 2 2006.257.18:10:09.35#ibcon#end of sib2, iclass 20, count 2 2006.257.18:10:09.35#ibcon#*mode == 0, iclass 20, count 2 2006.257.18:10:09.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.18:10:09.35#ibcon#[25=AT06-04\r\n] 2006.257.18:10:09.35#ibcon#*before write, iclass 20, count 2 2006.257.18:10:09.35#ibcon#enter sib2, iclass 20, count 2 2006.257.18:10:09.35#ibcon#flushed, iclass 20, count 2 2006.257.18:10:09.35#ibcon#about to write, iclass 20, count 2 2006.257.18:10:09.35#ibcon#wrote, iclass 20, count 2 2006.257.18:10:09.35#ibcon#about to read 3, iclass 20, count 2 2006.257.18:10:09.38#ibcon#read 3, iclass 20, count 2 2006.257.18:10:09.38#ibcon#about to read 4, iclass 20, count 2 2006.257.18:10:09.38#ibcon#read 4, iclass 20, count 2 2006.257.18:10:09.38#ibcon#about to read 5, iclass 20, count 2 2006.257.18:10:09.38#ibcon#read 5, iclass 20, count 2 2006.257.18:10:09.38#ibcon#about to read 6, iclass 20, count 2 2006.257.18:10:09.38#ibcon#read 6, iclass 20, count 2 2006.257.18:10:09.38#ibcon#end of sib2, iclass 20, count 2 2006.257.18:10:09.38#ibcon#*after write, iclass 20, count 2 2006.257.18:10:09.38#ibcon#*before return 0, iclass 20, count 2 2006.257.18:10:09.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:09.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:09.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.18:10:09.38#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:09.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:09.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:09.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:09.50#ibcon#enter wrdev, iclass 20, count 0 2006.257.18:10:09.50#ibcon#first serial, iclass 20, count 0 2006.257.18:10:09.50#ibcon#enter sib2, iclass 20, count 0 2006.257.18:10:09.50#ibcon#flushed, iclass 20, count 0 2006.257.18:10:09.50#ibcon#about to write, iclass 20, count 0 2006.257.18:10:09.50#ibcon#wrote, iclass 20, count 0 2006.257.18:10:09.50#ibcon#about to read 3, iclass 20, count 0 2006.257.18:10:09.52#ibcon#read 3, iclass 20, count 0 2006.257.18:10:09.52#ibcon#about to read 4, iclass 20, count 0 2006.257.18:10:09.52#ibcon#read 4, iclass 20, count 0 2006.257.18:10:09.52#ibcon#about to read 5, iclass 20, count 0 2006.257.18:10:09.52#ibcon#read 5, iclass 20, count 0 2006.257.18:10:09.52#ibcon#about to read 6, iclass 20, count 0 2006.257.18:10:09.52#ibcon#read 6, iclass 20, count 0 2006.257.18:10:09.52#ibcon#end of sib2, iclass 20, count 0 2006.257.18:10:09.52#ibcon#*mode == 0, iclass 20, count 0 2006.257.18:10:09.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.18:10:09.52#ibcon#[25=USB\r\n] 2006.257.18:10:09.52#ibcon#*before write, iclass 20, count 0 2006.257.18:10:09.52#ibcon#enter sib2, iclass 20, count 0 2006.257.18:10:09.52#ibcon#flushed, iclass 20, count 0 2006.257.18:10:09.52#ibcon#about to write, iclass 20, count 0 2006.257.18:10:09.52#ibcon#wrote, iclass 20, count 0 2006.257.18:10:09.52#ibcon#about to read 3, iclass 20, count 0 2006.257.18:10:09.55#ibcon#read 3, iclass 20, count 0 2006.257.18:10:09.55#ibcon#about to read 4, iclass 20, count 0 2006.257.18:10:09.55#ibcon#read 4, iclass 20, count 0 2006.257.18:10:09.55#ibcon#about to read 5, iclass 20, count 0 2006.257.18:10:09.55#ibcon#read 5, iclass 20, count 0 2006.257.18:10:09.55#ibcon#about to read 6, iclass 20, count 0 2006.257.18:10:09.55#ibcon#read 6, iclass 20, count 0 2006.257.18:10:09.55#ibcon#end of sib2, iclass 20, count 0 2006.257.18:10:09.55#ibcon#*after write, iclass 20, count 0 2006.257.18:10:09.55#ibcon#*before return 0, iclass 20, count 0 2006.257.18:10:09.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:09.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:09.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.18:10:09.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.18:10:09.55$vck44/valo=7,864.99 2006.257.18:10:09.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.18:10:09.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.18:10:09.55#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:09.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:09.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:09.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:09.55#ibcon#enter wrdev, iclass 22, count 0 2006.257.18:10:09.55#ibcon#first serial, iclass 22, count 0 2006.257.18:10:09.55#ibcon#enter sib2, iclass 22, count 0 2006.257.18:10:09.55#ibcon#flushed, iclass 22, count 0 2006.257.18:10:09.55#ibcon#about to write, iclass 22, count 0 2006.257.18:10:09.55#ibcon#wrote, iclass 22, count 0 2006.257.18:10:09.55#ibcon#about to read 3, iclass 22, count 0 2006.257.18:10:09.57#ibcon#read 3, iclass 22, count 0 2006.257.18:10:09.57#ibcon#about to read 4, iclass 22, count 0 2006.257.18:10:09.57#ibcon#read 4, iclass 22, count 0 2006.257.18:10:09.57#ibcon#about to read 5, iclass 22, count 0 2006.257.18:10:09.57#ibcon#read 5, iclass 22, count 0 2006.257.18:10:09.57#ibcon#about to read 6, iclass 22, count 0 2006.257.18:10:09.57#ibcon#read 6, iclass 22, count 0 2006.257.18:10:09.57#ibcon#end of sib2, iclass 22, count 0 2006.257.18:10:09.57#ibcon#*mode == 0, iclass 22, count 0 2006.257.18:10:09.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.18:10:09.57#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:10:09.57#ibcon#*before write, iclass 22, count 0 2006.257.18:10:09.57#ibcon#enter sib2, iclass 22, count 0 2006.257.18:10:09.57#ibcon#flushed, iclass 22, count 0 2006.257.18:10:09.57#ibcon#about to write, iclass 22, count 0 2006.257.18:10:09.57#ibcon#wrote, iclass 22, count 0 2006.257.18:10:09.57#ibcon#about to read 3, iclass 22, count 0 2006.257.18:10:09.61#ibcon#read 3, iclass 22, count 0 2006.257.18:10:09.61#ibcon#about to read 4, iclass 22, count 0 2006.257.18:10:09.61#ibcon#read 4, iclass 22, count 0 2006.257.18:10:09.61#ibcon#about to read 5, iclass 22, count 0 2006.257.18:10:09.61#ibcon#read 5, iclass 22, count 0 2006.257.18:10:09.61#ibcon#about to read 6, iclass 22, count 0 2006.257.18:10:09.61#ibcon#read 6, iclass 22, count 0 2006.257.18:10:09.61#ibcon#end of sib2, iclass 22, count 0 2006.257.18:10:09.61#ibcon#*after write, iclass 22, count 0 2006.257.18:10:09.61#ibcon#*before return 0, iclass 22, count 0 2006.257.18:10:09.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:09.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:09.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.18:10:09.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.18:10:09.61$vck44/va=7,4 2006.257.18:10:09.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.18:10:09.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.18:10:09.61#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:09.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:09.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:09.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:09.67#ibcon#enter wrdev, iclass 24, count 2 2006.257.18:10:09.67#ibcon#first serial, iclass 24, count 2 2006.257.18:10:09.67#ibcon#enter sib2, iclass 24, count 2 2006.257.18:10:09.67#ibcon#flushed, iclass 24, count 2 2006.257.18:10:09.67#ibcon#about to write, iclass 24, count 2 2006.257.18:10:09.67#ibcon#wrote, iclass 24, count 2 2006.257.18:10:09.67#ibcon#about to read 3, iclass 24, count 2 2006.257.18:10:09.69#ibcon#read 3, iclass 24, count 2 2006.257.18:10:09.69#ibcon#about to read 4, iclass 24, count 2 2006.257.18:10:09.69#ibcon#read 4, iclass 24, count 2 2006.257.18:10:09.69#ibcon#about to read 5, iclass 24, count 2 2006.257.18:10:09.69#ibcon#read 5, iclass 24, count 2 2006.257.18:10:09.69#ibcon#about to read 6, iclass 24, count 2 2006.257.18:10:09.69#ibcon#read 6, iclass 24, count 2 2006.257.18:10:09.69#ibcon#end of sib2, iclass 24, count 2 2006.257.18:10:09.69#ibcon#*mode == 0, iclass 24, count 2 2006.257.18:10:09.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.18:10:09.69#ibcon#[25=AT07-04\r\n] 2006.257.18:10:09.69#ibcon#*before write, iclass 24, count 2 2006.257.18:10:09.69#ibcon#enter sib2, iclass 24, count 2 2006.257.18:10:09.69#ibcon#flushed, iclass 24, count 2 2006.257.18:10:09.69#ibcon#about to write, iclass 24, count 2 2006.257.18:10:09.69#ibcon#wrote, iclass 24, count 2 2006.257.18:10:09.69#ibcon#about to read 3, iclass 24, count 2 2006.257.18:10:09.72#ibcon#read 3, iclass 24, count 2 2006.257.18:10:09.72#ibcon#about to read 4, iclass 24, count 2 2006.257.18:10:09.72#ibcon#read 4, iclass 24, count 2 2006.257.18:10:09.72#ibcon#about to read 5, iclass 24, count 2 2006.257.18:10:09.72#ibcon#read 5, iclass 24, count 2 2006.257.18:10:09.72#ibcon#about to read 6, iclass 24, count 2 2006.257.18:10:09.72#ibcon#read 6, iclass 24, count 2 2006.257.18:10:09.72#ibcon#end of sib2, iclass 24, count 2 2006.257.18:10:09.72#ibcon#*after write, iclass 24, count 2 2006.257.18:10:09.72#ibcon#*before return 0, iclass 24, count 2 2006.257.18:10:09.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:09.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:09.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.18:10:09.72#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:09.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:09.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:09.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:09.84#ibcon#enter wrdev, iclass 24, count 0 2006.257.18:10:09.84#ibcon#first serial, iclass 24, count 0 2006.257.18:10:09.84#ibcon#enter sib2, iclass 24, count 0 2006.257.18:10:09.84#ibcon#flushed, iclass 24, count 0 2006.257.18:10:09.84#ibcon#about to write, iclass 24, count 0 2006.257.18:10:09.84#ibcon#wrote, iclass 24, count 0 2006.257.18:10:09.84#ibcon#about to read 3, iclass 24, count 0 2006.257.18:10:09.86#ibcon#read 3, iclass 24, count 0 2006.257.18:10:09.86#ibcon#about to read 4, iclass 24, count 0 2006.257.18:10:09.86#ibcon#read 4, iclass 24, count 0 2006.257.18:10:09.86#ibcon#about to read 5, iclass 24, count 0 2006.257.18:10:09.86#ibcon#read 5, iclass 24, count 0 2006.257.18:10:09.86#ibcon#about to read 6, iclass 24, count 0 2006.257.18:10:09.86#ibcon#read 6, iclass 24, count 0 2006.257.18:10:09.86#ibcon#end of sib2, iclass 24, count 0 2006.257.18:10:09.86#ibcon#*mode == 0, iclass 24, count 0 2006.257.18:10:09.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.18:10:09.86#ibcon#[25=USB\r\n] 2006.257.18:10:09.86#ibcon#*before write, iclass 24, count 0 2006.257.18:10:09.86#ibcon#enter sib2, iclass 24, count 0 2006.257.18:10:09.86#ibcon#flushed, iclass 24, count 0 2006.257.18:10:09.86#ibcon#about to write, iclass 24, count 0 2006.257.18:10:09.86#ibcon#wrote, iclass 24, count 0 2006.257.18:10:09.86#ibcon#about to read 3, iclass 24, count 0 2006.257.18:10:09.89#ibcon#read 3, iclass 24, count 0 2006.257.18:10:09.89#ibcon#about to read 4, iclass 24, count 0 2006.257.18:10:09.89#ibcon#read 4, iclass 24, count 0 2006.257.18:10:09.89#ibcon#about to read 5, iclass 24, count 0 2006.257.18:10:09.89#ibcon#read 5, iclass 24, count 0 2006.257.18:10:09.89#ibcon#about to read 6, iclass 24, count 0 2006.257.18:10:09.89#ibcon#read 6, iclass 24, count 0 2006.257.18:10:09.89#ibcon#end of sib2, iclass 24, count 0 2006.257.18:10:09.89#ibcon#*after write, iclass 24, count 0 2006.257.18:10:09.89#ibcon#*before return 0, iclass 24, count 0 2006.257.18:10:09.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:09.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:09.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.18:10:09.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.18:10:09.89$vck44/valo=8,884.99 2006.257.18:10:09.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.18:10:09.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.18:10:09.89#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:09.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:09.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:09.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:09.89#ibcon#enter wrdev, iclass 26, count 0 2006.257.18:10:09.89#ibcon#first serial, iclass 26, count 0 2006.257.18:10:09.89#ibcon#enter sib2, iclass 26, count 0 2006.257.18:10:09.89#ibcon#flushed, iclass 26, count 0 2006.257.18:10:09.89#ibcon#about to write, iclass 26, count 0 2006.257.18:10:09.89#ibcon#wrote, iclass 26, count 0 2006.257.18:10:09.89#ibcon#about to read 3, iclass 26, count 0 2006.257.18:10:09.91#ibcon#read 3, iclass 26, count 0 2006.257.18:10:09.91#ibcon#about to read 4, iclass 26, count 0 2006.257.18:10:09.91#ibcon#read 4, iclass 26, count 0 2006.257.18:10:09.91#ibcon#about to read 5, iclass 26, count 0 2006.257.18:10:09.91#ibcon#read 5, iclass 26, count 0 2006.257.18:10:09.91#ibcon#about to read 6, iclass 26, count 0 2006.257.18:10:09.91#ibcon#read 6, iclass 26, count 0 2006.257.18:10:09.91#ibcon#end of sib2, iclass 26, count 0 2006.257.18:10:09.91#ibcon#*mode == 0, iclass 26, count 0 2006.257.18:10:09.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.18:10:09.91#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:10:09.91#ibcon#*before write, iclass 26, count 0 2006.257.18:10:09.91#ibcon#enter sib2, iclass 26, count 0 2006.257.18:10:09.91#ibcon#flushed, iclass 26, count 0 2006.257.18:10:09.91#ibcon#about to write, iclass 26, count 0 2006.257.18:10:09.91#ibcon#wrote, iclass 26, count 0 2006.257.18:10:09.91#ibcon#about to read 3, iclass 26, count 0 2006.257.18:10:09.95#ibcon#read 3, iclass 26, count 0 2006.257.18:10:09.95#ibcon#about to read 4, iclass 26, count 0 2006.257.18:10:09.95#ibcon#read 4, iclass 26, count 0 2006.257.18:10:09.95#ibcon#about to read 5, iclass 26, count 0 2006.257.18:10:09.95#ibcon#read 5, iclass 26, count 0 2006.257.18:10:09.95#ibcon#about to read 6, iclass 26, count 0 2006.257.18:10:09.95#ibcon#read 6, iclass 26, count 0 2006.257.18:10:09.95#ibcon#end of sib2, iclass 26, count 0 2006.257.18:10:09.95#ibcon#*after write, iclass 26, count 0 2006.257.18:10:09.95#ibcon#*before return 0, iclass 26, count 0 2006.257.18:10:09.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:09.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:09.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.18:10:09.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.18:10:09.95$vck44/va=8,4 2006.257.18:10:09.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.18:10:09.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.18:10:09.95#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:09.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:10:10.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:10:10.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:10:10.01#ibcon#enter wrdev, iclass 28, count 2 2006.257.18:10:10.01#ibcon#first serial, iclass 28, count 2 2006.257.18:10:10.01#ibcon#enter sib2, iclass 28, count 2 2006.257.18:10:10.01#ibcon#flushed, iclass 28, count 2 2006.257.18:10:10.01#ibcon#about to write, iclass 28, count 2 2006.257.18:10:10.01#ibcon#wrote, iclass 28, count 2 2006.257.18:10:10.01#ibcon#about to read 3, iclass 28, count 2 2006.257.18:10:10.03#ibcon#read 3, iclass 28, count 2 2006.257.18:10:10.03#ibcon#about to read 4, iclass 28, count 2 2006.257.18:10:10.03#ibcon#read 4, iclass 28, count 2 2006.257.18:10:10.03#ibcon#about to read 5, iclass 28, count 2 2006.257.18:10:10.03#ibcon#read 5, iclass 28, count 2 2006.257.18:10:10.03#ibcon#about to read 6, iclass 28, count 2 2006.257.18:10:10.03#ibcon#read 6, iclass 28, count 2 2006.257.18:10:10.03#ibcon#end of sib2, iclass 28, count 2 2006.257.18:10:10.03#ibcon#*mode == 0, iclass 28, count 2 2006.257.18:10:10.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.18:10:10.03#ibcon#[25=AT08-04\r\n] 2006.257.18:10:10.03#ibcon#*before write, iclass 28, count 2 2006.257.18:10:10.03#ibcon#enter sib2, iclass 28, count 2 2006.257.18:10:10.03#ibcon#flushed, iclass 28, count 2 2006.257.18:10:10.03#ibcon#about to write, iclass 28, count 2 2006.257.18:10:10.03#ibcon#wrote, iclass 28, count 2 2006.257.18:10:10.03#ibcon#about to read 3, iclass 28, count 2 2006.257.18:10:10.06#ibcon#read 3, iclass 28, count 2 2006.257.18:10:10.06#ibcon#about to read 4, iclass 28, count 2 2006.257.18:10:10.06#ibcon#read 4, iclass 28, count 2 2006.257.18:10:10.06#ibcon#about to read 5, iclass 28, count 2 2006.257.18:10:10.06#ibcon#read 5, iclass 28, count 2 2006.257.18:10:10.06#ibcon#about to read 6, iclass 28, count 2 2006.257.18:10:10.06#ibcon#read 6, iclass 28, count 2 2006.257.18:10:10.06#ibcon#end of sib2, iclass 28, count 2 2006.257.18:10:10.06#ibcon#*after write, iclass 28, count 2 2006.257.18:10:10.06#ibcon#*before return 0, iclass 28, count 2 2006.257.18:10:10.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:10:10.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:10:10.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.18:10:10.06#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:10.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:10:10.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:10:10.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:10:10.18#ibcon#enter wrdev, iclass 28, count 0 2006.257.18:10:10.18#ibcon#first serial, iclass 28, count 0 2006.257.18:10:10.18#ibcon#enter sib2, iclass 28, count 0 2006.257.18:10:10.18#ibcon#flushed, iclass 28, count 0 2006.257.18:10:10.18#ibcon#about to write, iclass 28, count 0 2006.257.18:10:10.18#ibcon#wrote, iclass 28, count 0 2006.257.18:10:10.18#ibcon#about to read 3, iclass 28, count 0 2006.257.18:10:10.20#ibcon#read 3, iclass 28, count 0 2006.257.18:10:10.20#ibcon#about to read 4, iclass 28, count 0 2006.257.18:10:10.20#ibcon#read 4, iclass 28, count 0 2006.257.18:10:10.20#ibcon#about to read 5, iclass 28, count 0 2006.257.18:10:10.20#ibcon#read 5, iclass 28, count 0 2006.257.18:10:10.20#ibcon#about to read 6, iclass 28, count 0 2006.257.18:10:10.20#ibcon#read 6, iclass 28, count 0 2006.257.18:10:10.20#ibcon#end of sib2, iclass 28, count 0 2006.257.18:10:10.20#ibcon#*mode == 0, iclass 28, count 0 2006.257.18:10:10.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.18:10:10.20#ibcon#[25=USB\r\n] 2006.257.18:10:10.20#ibcon#*before write, iclass 28, count 0 2006.257.18:10:10.20#ibcon#enter sib2, iclass 28, count 0 2006.257.18:10:10.20#ibcon#flushed, iclass 28, count 0 2006.257.18:10:10.20#ibcon#about to write, iclass 28, count 0 2006.257.18:10:10.20#ibcon#wrote, iclass 28, count 0 2006.257.18:10:10.20#ibcon#about to read 3, iclass 28, count 0 2006.257.18:10:10.23#ibcon#read 3, iclass 28, count 0 2006.257.18:10:10.23#ibcon#about to read 4, iclass 28, count 0 2006.257.18:10:10.23#ibcon#read 4, iclass 28, count 0 2006.257.18:10:10.23#ibcon#about to read 5, iclass 28, count 0 2006.257.18:10:10.23#ibcon#read 5, iclass 28, count 0 2006.257.18:10:10.23#ibcon#about to read 6, iclass 28, count 0 2006.257.18:10:10.23#ibcon#read 6, iclass 28, count 0 2006.257.18:10:10.23#ibcon#end of sib2, iclass 28, count 0 2006.257.18:10:10.23#ibcon#*after write, iclass 28, count 0 2006.257.18:10:10.23#ibcon#*before return 0, iclass 28, count 0 2006.257.18:10:10.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:10:10.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:10:10.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.18:10:10.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.18:10:10.23$vck44/vblo=1,629.99 2006.257.18:10:10.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.18:10:10.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.18:10:10.23#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:10.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:10.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:10.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:10.23#ibcon#enter wrdev, iclass 30, count 0 2006.257.18:10:10.23#ibcon#first serial, iclass 30, count 0 2006.257.18:10:10.23#ibcon#enter sib2, iclass 30, count 0 2006.257.18:10:10.23#ibcon#flushed, iclass 30, count 0 2006.257.18:10:10.23#ibcon#about to write, iclass 30, count 0 2006.257.18:10:10.23#ibcon#wrote, iclass 30, count 0 2006.257.18:10:10.23#ibcon#about to read 3, iclass 30, count 0 2006.257.18:10:10.25#ibcon#read 3, iclass 30, count 0 2006.257.18:10:10.25#ibcon#about to read 4, iclass 30, count 0 2006.257.18:10:10.25#ibcon#read 4, iclass 30, count 0 2006.257.18:10:10.25#ibcon#about to read 5, iclass 30, count 0 2006.257.18:10:10.25#ibcon#read 5, iclass 30, count 0 2006.257.18:10:10.25#ibcon#about to read 6, iclass 30, count 0 2006.257.18:10:10.25#ibcon#read 6, iclass 30, count 0 2006.257.18:10:10.25#ibcon#end of sib2, iclass 30, count 0 2006.257.18:10:10.25#ibcon#*mode == 0, iclass 30, count 0 2006.257.18:10:10.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.18:10:10.25#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:10:10.25#ibcon#*before write, iclass 30, count 0 2006.257.18:10:10.25#ibcon#enter sib2, iclass 30, count 0 2006.257.18:10:10.25#ibcon#flushed, iclass 30, count 0 2006.257.18:10:10.25#ibcon#about to write, iclass 30, count 0 2006.257.18:10:10.25#ibcon#wrote, iclass 30, count 0 2006.257.18:10:10.25#ibcon#about to read 3, iclass 30, count 0 2006.257.18:10:10.29#ibcon#read 3, iclass 30, count 0 2006.257.18:10:10.29#ibcon#about to read 4, iclass 30, count 0 2006.257.18:10:10.29#ibcon#read 4, iclass 30, count 0 2006.257.18:10:10.29#ibcon#about to read 5, iclass 30, count 0 2006.257.18:10:10.29#ibcon#read 5, iclass 30, count 0 2006.257.18:10:10.29#ibcon#about to read 6, iclass 30, count 0 2006.257.18:10:10.29#ibcon#read 6, iclass 30, count 0 2006.257.18:10:10.29#ibcon#end of sib2, iclass 30, count 0 2006.257.18:10:10.29#ibcon#*after write, iclass 30, count 0 2006.257.18:10:10.29#ibcon#*before return 0, iclass 30, count 0 2006.257.18:10:10.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:10.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:10:10.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.18:10:10.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.18:10:10.29$vck44/vb=1,4 2006.257.18:10:10.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.18:10:10.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.18:10:10.29#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:10.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:10:10.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:10:10.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:10:10.29#ibcon#enter wrdev, iclass 32, count 2 2006.257.18:10:10.29#ibcon#first serial, iclass 32, count 2 2006.257.18:10:10.29#ibcon#enter sib2, iclass 32, count 2 2006.257.18:10:10.29#ibcon#flushed, iclass 32, count 2 2006.257.18:10:10.29#ibcon#about to write, iclass 32, count 2 2006.257.18:10:10.29#ibcon#wrote, iclass 32, count 2 2006.257.18:10:10.29#ibcon#about to read 3, iclass 32, count 2 2006.257.18:10:10.31#ibcon#read 3, iclass 32, count 2 2006.257.18:10:10.31#ibcon#about to read 4, iclass 32, count 2 2006.257.18:10:10.31#ibcon#read 4, iclass 32, count 2 2006.257.18:10:10.31#ibcon#about to read 5, iclass 32, count 2 2006.257.18:10:10.31#ibcon#read 5, iclass 32, count 2 2006.257.18:10:10.31#ibcon#about to read 6, iclass 32, count 2 2006.257.18:10:10.31#ibcon#read 6, iclass 32, count 2 2006.257.18:10:10.31#ibcon#end of sib2, iclass 32, count 2 2006.257.18:10:10.31#ibcon#*mode == 0, iclass 32, count 2 2006.257.18:10:10.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.18:10:10.31#ibcon#[27=AT01-04\r\n] 2006.257.18:10:10.31#ibcon#*before write, iclass 32, count 2 2006.257.18:10:10.31#ibcon#enter sib2, iclass 32, count 2 2006.257.18:10:10.31#ibcon#flushed, iclass 32, count 2 2006.257.18:10:10.31#ibcon#about to write, iclass 32, count 2 2006.257.18:10:10.31#ibcon#wrote, iclass 32, count 2 2006.257.18:10:10.31#ibcon#about to read 3, iclass 32, count 2 2006.257.18:10:10.34#ibcon#read 3, iclass 32, count 2 2006.257.18:10:10.34#ibcon#about to read 4, iclass 32, count 2 2006.257.18:10:10.34#ibcon#read 4, iclass 32, count 2 2006.257.18:10:10.34#ibcon#about to read 5, iclass 32, count 2 2006.257.18:10:10.34#ibcon#read 5, iclass 32, count 2 2006.257.18:10:10.34#ibcon#about to read 6, iclass 32, count 2 2006.257.18:10:10.34#ibcon#read 6, iclass 32, count 2 2006.257.18:10:10.34#ibcon#end of sib2, iclass 32, count 2 2006.257.18:10:10.34#ibcon#*after write, iclass 32, count 2 2006.257.18:10:10.34#ibcon#*before return 0, iclass 32, count 2 2006.257.18:10:10.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:10:10.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:10:10.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.18:10:10.34#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:10.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:10:10.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:10:10.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:10:10.46#ibcon#enter wrdev, iclass 32, count 0 2006.257.18:10:10.46#ibcon#first serial, iclass 32, count 0 2006.257.18:10:10.46#ibcon#enter sib2, iclass 32, count 0 2006.257.18:10:10.46#ibcon#flushed, iclass 32, count 0 2006.257.18:10:10.46#ibcon#about to write, iclass 32, count 0 2006.257.18:10:10.46#ibcon#wrote, iclass 32, count 0 2006.257.18:10:10.46#ibcon#about to read 3, iclass 32, count 0 2006.257.18:10:10.48#ibcon#read 3, iclass 32, count 0 2006.257.18:10:10.48#ibcon#about to read 4, iclass 32, count 0 2006.257.18:10:10.48#ibcon#read 4, iclass 32, count 0 2006.257.18:10:10.48#ibcon#about to read 5, iclass 32, count 0 2006.257.18:10:10.48#ibcon#read 5, iclass 32, count 0 2006.257.18:10:10.48#ibcon#about to read 6, iclass 32, count 0 2006.257.18:10:10.48#ibcon#read 6, iclass 32, count 0 2006.257.18:10:10.48#ibcon#end of sib2, iclass 32, count 0 2006.257.18:10:10.48#ibcon#*mode == 0, iclass 32, count 0 2006.257.18:10:10.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.18:10:10.48#ibcon#[27=USB\r\n] 2006.257.18:10:10.48#ibcon#*before write, iclass 32, count 0 2006.257.18:10:10.48#ibcon#enter sib2, iclass 32, count 0 2006.257.18:10:10.48#ibcon#flushed, iclass 32, count 0 2006.257.18:10:10.48#ibcon#about to write, iclass 32, count 0 2006.257.18:10:10.48#ibcon#wrote, iclass 32, count 0 2006.257.18:10:10.48#ibcon#about to read 3, iclass 32, count 0 2006.257.18:10:10.51#ibcon#read 3, iclass 32, count 0 2006.257.18:10:10.51#ibcon#about to read 4, iclass 32, count 0 2006.257.18:10:10.51#ibcon#read 4, iclass 32, count 0 2006.257.18:10:10.51#ibcon#about to read 5, iclass 32, count 0 2006.257.18:10:10.51#ibcon#read 5, iclass 32, count 0 2006.257.18:10:10.51#ibcon#about to read 6, iclass 32, count 0 2006.257.18:10:10.51#ibcon#read 6, iclass 32, count 0 2006.257.18:10:10.51#ibcon#end of sib2, iclass 32, count 0 2006.257.18:10:10.51#ibcon#*after write, iclass 32, count 0 2006.257.18:10:10.51#ibcon#*before return 0, iclass 32, count 0 2006.257.18:10:10.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:10:10.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:10:10.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.18:10:10.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.18:10:10.51$vck44/vblo=2,634.99 2006.257.18:10:10.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.18:10:10.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.18:10:10.51#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:10.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:10:10.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:10:10.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:10:10.51#ibcon#enter wrdev, iclass 34, count 0 2006.257.18:10:10.51#ibcon#first serial, iclass 34, count 0 2006.257.18:10:10.51#ibcon#enter sib2, iclass 34, count 0 2006.257.18:10:10.51#ibcon#flushed, iclass 34, count 0 2006.257.18:10:10.51#ibcon#about to write, iclass 34, count 0 2006.257.18:10:10.51#ibcon#wrote, iclass 34, count 0 2006.257.18:10:10.51#ibcon#about to read 3, iclass 34, count 0 2006.257.18:10:10.53#ibcon#read 3, iclass 34, count 0 2006.257.18:10:10.53#ibcon#about to read 4, iclass 34, count 0 2006.257.18:10:10.53#ibcon#read 4, iclass 34, count 0 2006.257.18:10:10.53#ibcon#about to read 5, iclass 34, count 0 2006.257.18:10:10.53#ibcon#read 5, iclass 34, count 0 2006.257.18:10:10.53#ibcon#about to read 6, iclass 34, count 0 2006.257.18:10:10.53#ibcon#read 6, iclass 34, count 0 2006.257.18:10:10.53#ibcon#end of sib2, iclass 34, count 0 2006.257.18:10:10.53#ibcon#*mode == 0, iclass 34, count 0 2006.257.18:10:10.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.18:10:10.53#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:10:10.53#ibcon#*before write, iclass 34, count 0 2006.257.18:10:10.53#ibcon#enter sib2, iclass 34, count 0 2006.257.18:10:10.53#ibcon#flushed, iclass 34, count 0 2006.257.18:10:10.53#ibcon#about to write, iclass 34, count 0 2006.257.18:10:10.53#ibcon#wrote, iclass 34, count 0 2006.257.18:10:10.53#ibcon#about to read 3, iclass 34, count 0 2006.257.18:10:10.57#ibcon#read 3, iclass 34, count 0 2006.257.18:10:10.57#ibcon#about to read 4, iclass 34, count 0 2006.257.18:10:10.57#ibcon#read 4, iclass 34, count 0 2006.257.18:10:10.57#ibcon#about to read 5, iclass 34, count 0 2006.257.18:10:10.57#ibcon#read 5, iclass 34, count 0 2006.257.18:10:10.57#ibcon#about to read 6, iclass 34, count 0 2006.257.18:10:10.57#ibcon#read 6, iclass 34, count 0 2006.257.18:10:10.57#ibcon#end of sib2, iclass 34, count 0 2006.257.18:10:10.57#ibcon#*after write, iclass 34, count 0 2006.257.18:10:10.57#ibcon#*before return 0, iclass 34, count 0 2006.257.18:10:10.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:10:10.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:10:10.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.18:10:10.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.18:10:10.57$vck44/vb=2,5 2006.257.18:10:10.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.18:10:10.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.18:10:10.57#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:10.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:10:10.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:10:10.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:10:10.63#ibcon#enter wrdev, iclass 36, count 2 2006.257.18:10:10.63#ibcon#first serial, iclass 36, count 2 2006.257.18:10:10.63#ibcon#enter sib2, iclass 36, count 2 2006.257.18:10:10.63#ibcon#flushed, iclass 36, count 2 2006.257.18:10:10.63#ibcon#about to write, iclass 36, count 2 2006.257.18:10:10.63#ibcon#wrote, iclass 36, count 2 2006.257.18:10:10.63#ibcon#about to read 3, iclass 36, count 2 2006.257.18:10:10.65#ibcon#read 3, iclass 36, count 2 2006.257.18:10:10.65#ibcon#about to read 4, iclass 36, count 2 2006.257.18:10:10.65#ibcon#read 4, iclass 36, count 2 2006.257.18:10:10.65#ibcon#about to read 5, iclass 36, count 2 2006.257.18:10:10.65#ibcon#read 5, iclass 36, count 2 2006.257.18:10:10.65#ibcon#about to read 6, iclass 36, count 2 2006.257.18:10:10.65#ibcon#read 6, iclass 36, count 2 2006.257.18:10:10.65#ibcon#end of sib2, iclass 36, count 2 2006.257.18:10:10.65#ibcon#*mode == 0, iclass 36, count 2 2006.257.18:10:10.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.18:10:10.65#ibcon#[27=AT02-05\r\n] 2006.257.18:10:10.65#ibcon#*before write, iclass 36, count 2 2006.257.18:10:10.65#ibcon#enter sib2, iclass 36, count 2 2006.257.18:10:10.65#ibcon#flushed, iclass 36, count 2 2006.257.18:10:10.65#ibcon#about to write, iclass 36, count 2 2006.257.18:10:10.65#ibcon#wrote, iclass 36, count 2 2006.257.18:10:10.65#ibcon#about to read 3, iclass 36, count 2 2006.257.18:10:10.68#ibcon#read 3, iclass 36, count 2 2006.257.18:10:10.68#ibcon#about to read 4, iclass 36, count 2 2006.257.18:10:10.68#ibcon#read 4, iclass 36, count 2 2006.257.18:10:10.68#ibcon#about to read 5, iclass 36, count 2 2006.257.18:10:10.68#ibcon#read 5, iclass 36, count 2 2006.257.18:10:10.68#ibcon#about to read 6, iclass 36, count 2 2006.257.18:10:10.68#ibcon#read 6, iclass 36, count 2 2006.257.18:10:10.68#ibcon#end of sib2, iclass 36, count 2 2006.257.18:10:10.68#ibcon#*after write, iclass 36, count 2 2006.257.18:10:10.68#ibcon#*before return 0, iclass 36, count 2 2006.257.18:10:10.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:10:10.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:10:10.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.18:10:10.68#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:10.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:10:10.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:10:10.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:10:10.80#ibcon#enter wrdev, iclass 36, count 0 2006.257.18:10:10.80#ibcon#first serial, iclass 36, count 0 2006.257.18:10:10.80#ibcon#enter sib2, iclass 36, count 0 2006.257.18:10:10.80#ibcon#flushed, iclass 36, count 0 2006.257.18:10:10.80#ibcon#about to write, iclass 36, count 0 2006.257.18:10:10.80#ibcon#wrote, iclass 36, count 0 2006.257.18:10:10.80#ibcon#about to read 3, iclass 36, count 0 2006.257.18:10:10.82#ibcon#read 3, iclass 36, count 0 2006.257.18:10:10.82#ibcon#about to read 4, iclass 36, count 0 2006.257.18:10:10.82#ibcon#read 4, iclass 36, count 0 2006.257.18:10:10.82#ibcon#about to read 5, iclass 36, count 0 2006.257.18:10:10.82#ibcon#read 5, iclass 36, count 0 2006.257.18:10:10.82#ibcon#about to read 6, iclass 36, count 0 2006.257.18:10:10.82#ibcon#read 6, iclass 36, count 0 2006.257.18:10:10.82#ibcon#end of sib2, iclass 36, count 0 2006.257.18:10:10.82#ibcon#*mode == 0, iclass 36, count 0 2006.257.18:10:10.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.18:10:10.82#ibcon#[27=USB\r\n] 2006.257.18:10:10.82#ibcon#*before write, iclass 36, count 0 2006.257.18:10:10.82#ibcon#enter sib2, iclass 36, count 0 2006.257.18:10:10.82#ibcon#flushed, iclass 36, count 0 2006.257.18:10:10.82#ibcon#about to write, iclass 36, count 0 2006.257.18:10:10.82#ibcon#wrote, iclass 36, count 0 2006.257.18:10:10.82#ibcon#about to read 3, iclass 36, count 0 2006.257.18:10:10.85#ibcon#read 3, iclass 36, count 0 2006.257.18:10:10.85#ibcon#about to read 4, iclass 36, count 0 2006.257.18:10:10.85#ibcon#read 4, iclass 36, count 0 2006.257.18:10:10.85#ibcon#about to read 5, iclass 36, count 0 2006.257.18:10:10.85#ibcon#read 5, iclass 36, count 0 2006.257.18:10:10.85#ibcon#about to read 6, iclass 36, count 0 2006.257.18:10:10.85#ibcon#read 6, iclass 36, count 0 2006.257.18:10:10.85#ibcon#end of sib2, iclass 36, count 0 2006.257.18:10:10.85#ibcon#*after write, iclass 36, count 0 2006.257.18:10:10.85#ibcon#*before return 0, iclass 36, count 0 2006.257.18:10:10.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:10:10.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:10:10.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.18:10:10.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.18:10:10.85$vck44/vblo=3,649.99 2006.257.18:10:10.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.18:10:10.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.18:10:10.85#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:10.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:10.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:10.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:10.85#ibcon#enter wrdev, iclass 38, count 0 2006.257.18:10:10.85#ibcon#first serial, iclass 38, count 0 2006.257.18:10:10.85#ibcon#enter sib2, iclass 38, count 0 2006.257.18:10:10.85#ibcon#flushed, iclass 38, count 0 2006.257.18:10:10.85#ibcon#about to write, iclass 38, count 0 2006.257.18:10:10.85#ibcon#wrote, iclass 38, count 0 2006.257.18:10:10.85#ibcon#about to read 3, iclass 38, count 0 2006.257.18:10:10.87#ibcon#read 3, iclass 38, count 0 2006.257.18:10:10.87#ibcon#about to read 4, iclass 38, count 0 2006.257.18:10:10.87#ibcon#read 4, iclass 38, count 0 2006.257.18:10:10.87#ibcon#about to read 5, iclass 38, count 0 2006.257.18:10:10.87#ibcon#read 5, iclass 38, count 0 2006.257.18:10:10.87#ibcon#about to read 6, iclass 38, count 0 2006.257.18:10:10.87#ibcon#read 6, iclass 38, count 0 2006.257.18:10:10.87#ibcon#end of sib2, iclass 38, count 0 2006.257.18:10:10.87#ibcon#*mode == 0, iclass 38, count 0 2006.257.18:10:10.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.18:10:10.87#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:10:10.87#ibcon#*before write, iclass 38, count 0 2006.257.18:10:10.87#ibcon#enter sib2, iclass 38, count 0 2006.257.18:10:10.87#ibcon#flushed, iclass 38, count 0 2006.257.18:10:10.87#ibcon#about to write, iclass 38, count 0 2006.257.18:10:10.87#ibcon#wrote, iclass 38, count 0 2006.257.18:10:10.87#ibcon#about to read 3, iclass 38, count 0 2006.257.18:10:10.91#ibcon#read 3, iclass 38, count 0 2006.257.18:10:10.91#ibcon#about to read 4, iclass 38, count 0 2006.257.18:10:10.91#ibcon#read 4, iclass 38, count 0 2006.257.18:10:10.91#ibcon#about to read 5, iclass 38, count 0 2006.257.18:10:10.91#ibcon#read 5, iclass 38, count 0 2006.257.18:10:10.91#ibcon#about to read 6, iclass 38, count 0 2006.257.18:10:10.91#ibcon#read 6, iclass 38, count 0 2006.257.18:10:10.91#ibcon#end of sib2, iclass 38, count 0 2006.257.18:10:10.91#ibcon#*after write, iclass 38, count 0 2006.257.18:10:10.91#ibcon#*before return 0, iclass 38, count 0 2006.257.18:10:10.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:10.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:10:10.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.18:10:10.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.18:10:10.91$vck44/vb=3,4 2006.257.18:10:10.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.18:10:10.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.18:10:10.91#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:10.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:10.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:10.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:10.97#ibcon#enter wrdev, iclass 40, count 2 2006.257.18:10:10.97#ibcon#first serial, iclass 40, count 2 2006.257.18:10:10.97#ibcon#enter sib2, iclass 40, count 2 2006.257.18:10:10.97#ibcon#flushed, iclass 40, count 2 2006.257.18:10:10.97#ibcon#about to write, iclass 40, count 2 2006.257.18:10:10.97#ibcon#wrote, iclass 40, count 2 2006.257.18:10:10.97#ibcon#about to read 3, iclass 40, count 2 2006.257.18:10:10.99#ibcon#read 3, iclass 40, count 2 2006.257.18:10:10.99#ibcon#about to read 4, iclass 40, count 2 2006.257.18:10:10.99#ibcon#read 4, iclass 40, count 2 2006.257.18:10:10.99#ibcon#about to read 5, iclass 40, count 2 2006.257.18:10:10.99#ibcon#read 5, iclass 40, count 2 2006.257.18:10:10.99#ibcon#about to read 6, iclass 40, count 2 2006.257.18:10:10.99#ibcon#read 6, iclass 40, count 2 2006.257.18:10:10.99#ibcon#end of sib2, iclass 40, count 2 2006.257.18:10:10.99#ibcon#*mode == 0, iclass 40, count 2 2006.257.18:10:10.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.18:10:10.99#ibcon#[27=AT03-04\r\n] 2006.257.18:10:10.99#ibcon#*before write, iclass 40, count 2 2006.257.18:10:10.99#ibcon#enter sib2, iclass 40, count 2 2006.257.18:10:10.99#ibcon#flushed, iclass 40, count 2 2006.257.18:10:10.99#ibcon#about to write, iclass 40, count 2 2006.257.18:10:10.99#ibcon#wrote, iclass 40, count 2 2006.257.18:10:10.99#ibcon#about to read 3, iclass 40, count 2 2006.257.18:10:11.02#ibcon#read 3, iclass 40, count 2 2006.257.18:10:11.02#ibcon#about to read 4, iclass 40, count 2 2006.257.18:10:11.02#ibcon#read 4, iclass 40, count 2 2006.257.18:10:11.02#ibcon#about to read 5, iclass 40, count 2 2006.257.18:10:11.02#ibcon#read 5, iclass 40, count 2 2006.257.18:10:11.02#ibcon#about to read 6, iclass 40, count 2 2006.257.18:10:11.02#ibcon#read 6, iclass 40, count 2 2006.257.18:10:11.02#ibcon#end of sib2, iclass 40, count 2 2006.257.18:10:11.02#ibcon#*after write, iclass 40, count 2 2006.257.18:10:11.02#ibcon#*before return 0, iclass 40, count 2 2006.257.18:10:11.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:11.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:10:11.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.18:10:11.02#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:11.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:11.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:11.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:11.14#ibcon#enter wrdev, iclass 40, count 0 2006.257.18:10:11.14#ibcon#first serial, iclass 40, count 0 2006.257.18:10:11.14#ibcon#enter sib2, iclass 40, count 0 2006.257.18:10:11.14#ibcon#flushed, iclass 40, count 0 2006.257.18:10:11.14#ibcon#about to write, iclass 40, count 0 2006.257.18:10:11.14#ibcon#wrote, iclass 40, count 0 2006.257.18:10:11.14#ibcon#about to read 3, iclass 40, count 0 2006.257.18:10:11.16#ibcon#read 3, iclass 40, count 0 2006.257.18:10:11.16#ibcon#about to read 4, iclass 40, count 0 2006.257.18:10:11.16#ibcon#read 4, iclass 40, count 0 2006.257.18:10:11.16#ibcon#about to read 5, iclass 40, count 0 2006.257.18:10:11.16#ibcon#read 5, iclass 40, count 0 2006.257.18:10:11.16#ibcon#about to read 6, iclass 40, count 0 2006.257.18:10:11.16#ibcon#read 6, iclass 40, count 0 2006.257.18:10:11.16#ibcon#end of sib2, iclass 40, count 0 2006.257.18:10:11.16#ibcon#*mode == 0, iclass 40, count 0 2006.257.18:10:11.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.18:10:11.16#ibcon#[27=USB\r\n] 2006.257.18:10:11.16#ibcon#*before write, iclass 40, count 0 2006.257.18:10:11.16#ibcon#enter sib2, iclass 40, count 0 2006.257.18:10:11.16#ibcon#flushed, iclass 40, count 0 2006.257.18:10:11.16#ibcon#about to write, iclass 40, count 0 2006.257.18:10:11.16#ibcon#wrote, iclass 40, count 0 2006.257.18:10:11.16#ibcon#about to read 3, iclass 40, count 0 2006.257.18:10:11.19#ibcon#read 3, iclass 40, count 0 2006.257.18:10:11.19#ibcon#about to read 4, iclass 40, count 0 2006.257.18:10:11.19#ibcon#read 4, iclass 40, count 0 2006.257.18:10:11.19#ibcon#about to read 5, iclass 40, count 0 2006.257.18:10:11.19#ibcon#read 5, iclass 40, count 0 2006.257.18:10:11.19#ibcon#about to read 6, iclass 40, count 0 2006.257.18:10:11.19#ibcon#read 6, iclass 40, count 0 2006.257.18:10:11.19#ibcon#end of sib2, iclass 40, count 0 2006.257.18:10:11.19#ibcon#*after write, iclass 40, count 0 2006.257.18:10:11.19#ibcon#*before return 0, iclass 40, count 0 2006.257.18:10:11.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:11.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:10:11.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.18:10:11.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.18:10:11.19$vck44/vblo=4,679.99 2006.257.18:10:11.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.18:10:11.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.18:10:11.19#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:11.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:11.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:11.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:11.19#ibcon#enter wrdev, iclass 4, count 0 2006.257.18:10:11.19#ibcon#first serial, iclass 4, count 0 2006.257.18:10:11.19#ibcon#enter sib2, iclass 4, count 0 2006.257.18:10:11.19#ibcon#flushed, iclass 4, count 0 2006.257.18:10:11.19#ibcon#about to write, iclass 4, count 0 2006.257.18:10:11.19#ibcon#wrote, iclass 4, count 0 2006.257.18:10:11.19#ibcon#about to read 3, iclass 4, count 0 2006.257.18:10:11.21#ibcon#read 3, iclass 4, count 0 2006.257.18:10:11.21#ibcon#about to read 4, iclass 4, count 0 2006.257.18:10:11.21#ibcon#read 4, iclass 4, count 0 2006.257.18:10:11.21#ibcon#about to read 5, iclass 4, count 0 2006.257.18:10:11.21#ibcon#read 5, iclass 4, count 0 2006.257.18:10:11.21#ibcon#about to read 6, iclass 4, count 0 2006.257.18:10:11.21#ibcon#read 6, iclass 4, count 0 2006.257.18:10:11.21#ibcon#end of sib2, iclass 4, count 0 2006.257.18:10:11.21#ibcon#*mode == 0, iclass 4, count 0 2006.257.18:10:11.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.18:10:11.21#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:10:11.21#ibcon#*before write, iclass 4, count 0 2006.257.18:10:11.21#ibcon#enter sib2, iclass 4, count 0 2006.257.18:10:11.21#ibcon#flushed, iclass 4, count 0 2006.257.18:10:11.21#ibcon#about to write, iclass 4, count 0 2006.257.18:10:11.21#ibcon#wrote, iclass 4, count 0 2006.257.18:10:11.21#ibcon#about to read 3, iclass 4, count 0 2006.257.18:10:11.25#ibcon#read 3, iclass 4, count 0 2006.257.18:10:11.25#ibcon#about to read 4, iclass 4, count 0 2006.257.18:10:11.25#ibcon#read 4, iclass 4, count 0 2006.257.18:10:11.25#ibcon#about to read 5, iclass 4, count 0 2006.257.18:10:11.25#ibcon#read 5, iclass 4, count 0 2006.257.18:10:11.25#ibcon#about to read 6, iclass 4, count 0 2006.257.18:10:11.25#ibcon#read 6, iclass 4, count 0 2006.257.18:10:11.25#ibcon#end of sib2, iclass 4, count 0 2006.257.18:10:11.25#ibcon#*after write, iclass 4, count 0 2006.257.18:10:11.25#ibcon#*before return 0, iclass 4, count 0 2006.257.18:10:11.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:11.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:10:11.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.18:10:11.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.18:10:11.25$vck44/vb=4,5 2006.257.18:10:11.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.18:10:11.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.18:10:11.25#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:11.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:11.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:11.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:11.31#ibcon#enter wrdev, iclass 6, count 2 2006.257.18:10:11.31#ibcon#first serial, iclass 6, count 2 2006.257.18:10:11.31#ibcon#enter sib2, iclass 6, count 2 2006.257.18:10:11.31#ibcon#flushed, iclass 6, count 2 2006.257.18:10:11.31#ibcon#about to write, iclass 6, count 2 2006.257.18:10:11.31#ibcon#wrote, iclass 6, count 2 2006.257.18:10:11.31#ibcon#about to read 3, iclass 6, count 2 2006.257.18:10:11.33#ibcon#read 3, iclass 6, count 2 2006.257.18:10:11.33#ibcon#about to read 4, iclass 6, count 2 2006.257.18:10:11.33#ibcon#read 4, iclass 6, count 2 2006.257.18:10:11.33#ibcon#about to read 5, iclass 6, count 2 2006.257.18:10:11.33#ibcon#read 5, iclass 6, count 2 2006.257.18:10:11.33#ibcon#about to read 6, iclass 6, count 2 2006.257.18:10:11.33#ibcon#read 6, iclass 6, count 2 2006.257.18:10:11.33#ibcon#end of sib2, iclass 6, count 2 2006.257.18:10:11.33#ibcon#*mode == 0, iclass 6, count 2 2006.257.18:10:11.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.18:10:11.33#ibcon#[27=AT04-05\r\n] 2006.257.18:10:11.33#ibcon#*before write, iclass 6, count 2 2006.257.18:10:11.33#ibcon#enter sib2, iclass 6, count 2 2006.257.18:10:11.33#ibcon#flushed, iclass 6, count 2 2006.257.18:10:11.33#ibcon#about to write, iclass 6, count 2 2006.257.18:10:11.33#ibcon#wrote, iclass 6, count 2 2006.257.18:10:11.33#ibcon#about to read 3, iclass 6, count 2 2006.257.18:10:11.36#ibcon#read 3, iclass 6, count 2 2006.257.18:10:11.36#ibcon#about to read 4, iclass 6, count 2 2006.257.18:10:11.36#ibcon#read 4, iclass 6, count 2 2006.257.18:10:11.36#ibcon#about to read 5, iclass 6, count 2 2006.257.18:10:11.36#ibcon#read 5, iclass 6, count 2 2006.257.18:10:11.36#ibcon#about to read 6, iclass 6, count 2 2006.257.18:10:11.36#ibcon#read 6, iclass 6, count 2 2006.257.18:10:11.36#ibcon#end of sib2, iclass 6, count 2 2006.257.18:10:11.36#ibcon#*after write, iclass 6, count 2 2006.257.18:10:11.36#ibcon#*before return 0, iclass 6, count 2 2006.257.18:10:11.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:11.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:10:11.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.18:10:11.36#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:11.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:11.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:11.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:11.48#ibcon#enter wrdev, iclass 6, count 0 2006.257.18:10:11.48#ibcon#first serial, iclass 6, count 0 2006.257.18:10:11.48#ibcon#enter sib2, iclass 6, count 0 2006.257.18:10:11.48#ibcon#flushed, iclass 6, count 0 2006.257.18:10:11.48#ibcon#about to write, iclass 6, count 0 2006.257.18:10:11.48#ibcon#wrote, iclass 6, count 0 2006.257.18:10:11.48#ibcon#about to read 3, iclass 6, count 0 2006.257.18:10:11.50#ibcon#read 3, iclass 6, count 0 2006.257.18:10:11.50#ibcon#about to read 4, iclass 6, count 0 2006.257.18:10:11.50#ibcon#read 4, iclass 6, count 0 2006.257.18:10:11.50#ibcon#about to read 5, iclass 6, count 0 2006.257.18:10:11.50#ibcon#read 5, iclass 6, count 0 2006.257.18:10:11.50#ibcon#about to read 6, iclass 6, count 0 2006.257.18:10:11.50#ibcon#read 6, iclass 6, count 0 2006.257.18:10:11.50#ibcon#end of sib2, iclass 6, count 0 2006.257.18:10:11.50#ibcon#*mode == 0, iclass 6, count 0 2006.257.18:10:11.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.18:10:11.50#ibcon#[27=USB\r\n] 2006.257.18:10:11.50#ibcon#*before write, iclass 6, count 0 2006.257.18:10:11.50#ibcon#enter sib2, iclass 6, count 0 2006.257.18:10:11.50#ibcon#flushed, iclass 6, count 0 2006.257.18:10:11.50#ibcon#about to write, iclass 6, count 0 2006.257.18:10:11.50#ibcon#wrote, iclass 6, count 0 2006.257.18:10:11.50#ibcon#about to read 3, iclass 6, count 0 2006.257.18:10:11.53#ibcon#read 3, iclass 6, count 0 2006.257.18:10:11.53#ibcon#about to read 4, iclass 6, count 0 2006.257.18:10:11.53#ibcon#read 4, iclass 6, count 0 2006.257.18:10:11.53#ibcon#about to read 5, iclass 6, count 0 2006.257.18:10:11.53#ibcon#read 5, iclass 6, count 0 2006.257.18:10:11.53#ibcon#about to read 6, iclass 6, count 0 2006.257.18:10:11.53#ibcon#read 6, iclass 6, count 0 2006.257.18:10:11.53#ibcon#end of sib2, iclass 6, count 0 2006.257.18:10:11.53#ibcon#*after write, iclass 6, count 0 2006.257.18:10:11.53#ibcon#*before return 0, iclass 6, count 0 2006.257.18:10:11.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:11.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:10:11.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.18:10:11.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.18:10:11.53$vck44/vblo=5,709.99 2006.257.18:10:11.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.18:10:11.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.18:10:11.53#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:11.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:11.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:11.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:11.53#ibcon#enter wrdev, iclass 10, count 0 2006.257.18:10:11.53#ibcon#first serial, iclass 10, count 0 2006.257.18:10:11.53#ibcon#enter sib2, iclass 10, count 0 2006.257.18:10:11.53#ibcon#flushed, iclass 10, count 0 2006.257.18:10:11.53#ibcon#about to write, iclass 10, count 0 2006.257.18:10:11.53#ibcon#wrote, iclass 10, count 0 2006.257.18:10:11.53#ibcon#about to read 3, iclass 10, count 0 2006.257.18:10:11.55#ibcon#read 3, iclass 10, count 0 2006.257.18:10:11.55#ibcon#about to read 4, iclass 10, count 0 2006.257.18:10:11.55#ibcon#read 4, iclass 10, count 0 2006.257.18:10:11.55#ibcon#about to read 5, iclass 10, count 0 2006.257.18:10:11.55#ibcon#read 5, iclass 10, count 0 2006.257.18:10:11.55#ibcon#about to read 6, iclass 10, count 0 2006.257.18:10:11.55#ibcon#read 6, iclass 10, count 0 2006.257.18:10:11.55#ibcon#end of sib2, iclass 10, count 0 2006.257.18:10:11.55#ibcon#*mode == 0, iclass 10, count 0 2006.257.18:10:11.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.18:10:11.55#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:10:11.55#ibcon#*before write, iclass 10, count 0 2006.257.18:10:11.55#ibcon#enter sib2, iclass 10, count 0 2006.257.18:10:11.55#ibcon#flushed, iclass 10, count 0 2006.257.18:10:11.55#ibcon#about to write, iclass 10, count 0 2006.257.18:10:11.55#ibcon#wrote, iclass 10, count 0 2006.257.18:10:11.55#ibcon#about to read 3, iclass 10, count 0 2006.257.18:10:11.59#ibcon#read 3, iclass 10, count 0 2006.257.18:10:11.59#ibcon#about to read 4, iclass 10, count 0 2006.257.18:10:11.59#ibcon#read 4, iclass 10, count 0 2006.257.18:10:11.59#ibcon#about to read 5, iclass 10, count 0 2006.257.18:10:11.59#ibcon#read 5, iclass 10, count 0 2006.257.18:10:11.59#ibcon#about to read 6, iclass 10, count 0 2006.257.18:10:11.59#ibcon#read 6, iclass 10, count 0 2006.257.18:10:11.59#ibcon#end of sib2, iclass 10, count 0 2006.257.18:10:11.59#ibcon#*after write, iclass 10, count 0 2006.257.18:10:11.59#ibcon#*before return 0, iclass 10, count 0 2006.257.18:10:11.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:11.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:10:11.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.18:10:11.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.18:10:11.59$vck44/vb=5,4 2006.257.18:10:11.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.18:10:11.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.18:10:11.59#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:11.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:11.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:11.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:11.65#ibcon#enter wrdev, iclass 12, count 2 2006.257.18:10:11.65#ibcon#first serial, iclass 12, count 2 2006.257.18:10:11.65#ibcon#enter sib2, iclass 12, count 2 2006.257.18:10:11.65#ibcon#flushed, iclass 12, count 2 2006.257.18:10:11.65#ibcon#about to write, iclass 12, count 2 2006.257.18:10:11.65#ibcon#wrote, iclass 12, count 2 2006.257.18:10:11.65#ibcon#about to read 3, iclass 12, count 2 2006.257.18:10:11.67#ibcon#read 3, iclass 12, count 2 2006.257.18:10:11.67#ibcon#about to read 4, iclass 12, count 2 2006.257.18:10:11.67#ibcon#read 4, iclass 12, count 2 2006.257.18:10:11.67#ibcon#about to read 5, iclass 12, count 2 2006.257.18:10:11.67#ibcon#read 5, iclass 12, count 2 2006.257.18:10:11.67#ibcon#about to read 6, iclass 12, count 2 2006.257.18:10:11.67#ibcon#read 6, iclass 12, count 2 2006.257.18:10:11.67#ibcon#end of sib2, iclass 12, count 2 2006.257.18:10:11.67#ibcon#*mode == 0, iclass 12, count 2 2006.257.18:10:11.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.18:10:11.67#ibcon#[27=AT05-04\r\n] 2006.257.18:10:11.67#ibcon#*before write, iclass 12, count 2 2006.257.18:10:11.67#ibcon#enter sib2, iclass 12, count 2 2006.257.18:10:11.67#ibcon#flushed, iclass 12, count 2 2006.257.18:10:11.67#ibcon#about to write, iclass 12, count 2 2006.257.18:10:11.67#ibcon#wrote, iclass 12, count 2 2006.257.18:10:11.67#ibcon#about to read 3, iclass 12, count 2 2006.257.18:10:11.70#ibcon#read 3, iclass 12, count 2 2006.257.18:10:11.70#ibcon#about to read 4, iclass 12, count 2 2006.257.18:10:11.70#ibcon#read 4, iclass 12, count 2 2006.257.18:10:11.70#ibcon#about to read 5, iclass 12, count 2 2006.257.18:10:11.70#ibcon#read 5, iclass 12, count 2 2006.257.18:10:11.70#ibcon#about to read 6, iclass 12, count 2 2006.257.18:10:11.70#ibcon#read 6, iclass 12, count 2 2006.257.18:10:11.70#ibcon#end of sib2, iclass 12, count 2 2006.257.18:10:11.70#ibcon#*after write, iclass 12, count 2 2006.257.18:10:11.70#ibcon#*before return 0, iclass 12, count 2 2006.257.18:10:11.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:11.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:10:11.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.18:10:11.70#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:11.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:11.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:11.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:11.82#ibcon#enter wrdev, iclass 12, count 0 2006.257.18:10:11.82#ibcon#first serial, iclass 12, count 0 2006.257.18:10:11.82#ibcon#enter sib2, iclass 12, count 0 2006.257.18:10:11.82#ibcon#flushed, iclass 12, count 0 2006.257.18:10:11.82#ibcon#about to write, iclass 12, count 0 2006.257.18:10:11.82#ibcon#wrote, iclass 12, count 0 2006.257.18:10:11.82#ibcon#about to read 3, iclass 12, count 0 2006.257.18:10:11.84#ibcon#read 3, iclass 12, count 0 2006.257.18:10:11.84#ibcon#about to read 4, iclass 12, count 0 2006.257.18:10:11.84#ibcon#read 4, iclass 12, count 0 2006.257.18:10:11.84#ibcon#about to read 5, iclass 12, count 0 2006.257.18:10:11.84#ibcon#read 5, iclass 12, count 0 2006.257.18:10:11.84#ibcon#about to read 6, iclass 12, count 0 2006.257.18:10:11.84#ibcon#read 6, iclass 12, count 0 2006.257.18:10:11.84#ibcon#end of sib2, iclass 12, count 0 2006.257.18:10:11.84#ibcon#*mode == 0, iclass 12, count 0 2006.257.18:10:11.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.18:10:11.84#ibcon#[27=USB\r\n] 2006.257.18:10:11.84#ibcon#*before write, iclass 12, count 0 2006.257.18:10:11.84#ibcon#enter sib2, iclass 12, count 0 2006.257.18:10:11.84#ibcon#flushed, iclass 12, count 0 2006.257.18:10:11.84#ibcon#about to write, iclass 12, count 0 2006.257.18:10:11.84#ibcon#wrote, iclass 12, count 0 2006.257.18:10:11.84#ibcon#about to read 3, iclass 12, count 0 2006.257.18:10:11.87#ibcon#read 3, iclass 12, count 0 2006.257.18:10:11.87#ibcon#about to read 4, iclass 12, count 0 2006.257.18:10:11.87#ibcon#read 4, iclass 12, count 0 2006.257.18:10:11.87#ibcon#about to read 5, iclass 12, count 0 2006.257.18:10:11.87#ibcon#read 5, iclass 12, count 0 2006.257.18:10:11.87#ibcon#about to read 6, iclass 12, count 0 2006.257.18:10:11.87#ibcon#read 6, iclass 12, count 0 2006.257.18:10:11.87#ibcon#end of sib2, iclass 12, count 0 2006.257.18:10:11.87#ibcon#*after write, iclass 12, count 0 2006.257.18:10:11.87#ibcon#*before return 0, iclass 12, count 0 2006.257.18:10:11.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:11.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:10:11.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.18:10:11.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.18:10:11.87$vck44/vblo=6,719.99 2006.257.18:10:11.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.18:10:11.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.18:10:11.87#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:11.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:11.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:11.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:11.87#ibcon#enter wrdev, iclass 14, count 0 2006.257.18:10:11.87#ibcon#first serial, iclass 14, count 0 2006.257.18:10:11.87#ibcon#enter sib2, iclass 14, count 0 2006.257.18:10:11.87#ibcon#flushed, iclass 14, count 0 2006.257.18:10:11.87#ibcon#about to write, iclass 14, count 0 2006.257.18:10:11.87#ibcon#wrote, iclass 14, count 0 2006.257.18:10:11.87#ibcon#about to read 3, iclass 14, count 0 2006.257.18:10:11.89#ibcon#read 3, iclass 14, count 0 2006.257.18:10:11.89#ibcon#about to read 4, iclass 14, count 0 2006.257.18:10:11.89#ibcon#read 4, iclass 14, count 0 2006.257.18:10:11.89#ibcon#about to read 5, iclass 14, count 0 2006.257.18:10:11.89#ibcon#read 5, iclass 14, count 0 2006.257.18:10:11.89#ibcon#about to read 6, iclass 14, count 0 2006.257.18:10:11.89#ibcon#read 6, iclass 14, count 0 2006.257.18:10:11.89#ibcon#end of sib2, iclass 14, count 0 2006.257.18:10:11.89#ibcon#*mode == 0, iclass 14, count 0 2006.257.18:10:11.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.18:10:11.89#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:10:11.89#ibcon#*before write, iclass 14, count 0 2006.257.18:10:11.89#ibcon#enter sib2, iclass 14, count 0 2006.257.18:10:11.89#ibcon#flushed, iclass 14, count 0 2006.257.18:10:11.89#ibcon#about to write, iclass 14, count 0 2006.257.18:10:11.89#ibcon#wrote, iclass 14, count 0 2006.257.18:10:11.89#ibcon#about to read 3, iclass 14, count 0 2006.257.18:10:11.93#ibcon#read 3, iclass 14, count 0 2006.257.18:10:11.93#ibcon#about to read 4, iclass 14, count 0 2006.257.18:10:11.93#ibcon#read 4, iclass 14, count 0 2006.257.18:10:11.93#ibcon#about to read 5, iclass 14, count 0 2006.257.18:10:11.93#ibcon#read 5, iclass 14, count 0 2006.257.18:10:11.93#ibcon#about to read 6, iclass 14, count 0 2006.257.18:10:11.93#ibcon#read 6, iclass 14, count 0 2006.257.18:10:11.93#ibcon#end of sib2, iclass 14, count 0 2006.257.18:10:11.93#ibcon#*after write, iclass 14, count 0 2006.257.18:10:11.93#ibcon#*before return 0, iclass 14, count 0 2006.257.18:10:11.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:11.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:10:11.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.18:10:11.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.18:10:11.93$vck44/vb=6,4 2006.257.18:10:11.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.18:10:11.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.18:10:11.93#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:11.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:11.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:11.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:11.99#ibcon#enter wrdev, iclass 16, count 2 2006.257.18:10:11.99#ibcon#first serial, iclass 16, count 2 2006.257.18:10:11.99#ibcon#enter sib2, iclass 16, count 2 2006.257.18:10:11.99#ibcon#flushed, iclass 16, count 2 2006.257.18:10:11.99#ibcon#about to write, iclass 16, count 2 2006.257.18:10:11.99#ibcon#wrote, iclass 16, count 2 2006.257.18:10:11.99#ibcon#about to read 3, iclass 16, count 2 2006.257.18:10:12.01#ibcon#read 3, iclass 16, count 2 2006.257.18:10:12.01#ibcon#about to read 4, iclass 16, count 2 2006.257.18:10:12.01#ibcon#read 4, iclass 16, count 2 2006.257.18:10:12.01#ibcon#about to read 5, iclass 16, count 2 2006.257.18:10:12.01#ibcon#read 5, iclass 16, count 2 2006.257.18:10:12.01#ibcon#about to read 6, iclass 16, count 2 2006.257.18:10:12.01#ibcon#read 6, iclass 16, count 2 2006.257.18:10:12.01#ibcon#end of sib2, iclass 16, count 2 2006.257.18:10:12.01#ibcon#*mode == 0, iclass 16, count 2 2006.257.18:10:12.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.18:10:12.01#ibcon#[27=AT06-04\r\n] 2006.257.18:10:12.01#ibcon#*before write, iclass 16, count 2 2006.257.18:10:12.01#ibcon#enter sib2, iclass 16, count 2 2006.257.18:10:12.01#ibcon#flushed, iclass 16, count 2 2006.257.18:10:12.01#ibcon#about to write, iclass 16, count 2 2006.257.18:10:12.01#ibcon#wrote, iclass 16, count 2 2006.257.18:10:12.01#ibcon#about to read 3, iclass 16, count 2 2006.257.18:10:12.04#ibcon#read 3, iclass 16, count 2 2006.257.18:10:12.04#ibcon#about to read 4, iclass 16, count 2 2006.257.18:10:12.04#ibcon#read 4, iclass 16, count 2 2006.257.18:10:12.04#ibcon#about to read 5, iclass 16, count 2 2006.257.18:10:12.04#ibcon#read 5, iclass 16, count 2 2006.257.18:10:12.04#ibcon#about to read 6, iclass 16, count 2 2006.257.18:10:12.04#ibcon#read 6, iclass 16, count 2 2006.257.18:10:12.04#ibcon#end of sib2, iclass 16, count 2 2006.257.18:10:12.04#ibcon#*after write, iclass 16, count 2 2006.257.18:10:12.04#ibcon#*before return 0, iclass 16, count 2 2006.257.18:10:12.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:12.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:10:12.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.18:10:12.04#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:12.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:12.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:12.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:12.16#ibcon#enter wrdev, iclass 16, count 0 2006.257.18:10:12.16#ibcon#first serial, iclass 16, count 0 2006.257.18:10:12.16#ibcon#enter sib2, iclass 16, count 0 2006.257.18:10:12.16#ibcon#flushed, iclass 16, count 0 2006.257.18:10:12.16#ibcon#about to write, iclass 16, count 0 2006.257.18:10:12.16#ibcon#wrote, iclass 16, count 0 2006.257.18:10:12.16#ibcon#about to read 3, iclass 16, count 0 2006.257.18:10:12.18#ibcon#read 3, iclass 16, count 0 2006.257.18:10:12.18#ibcon#about to read 4, iclass 16, count 0 2006.257.18:10:12.18#ibcon#read 4, iclass 16, count 0 2006.257.18:10:12.18#ibcon#about to read 5, iclass 16, count 0 2006.257.18:10:12.18#ibcon#read 5, iclass 16, count 0 2006.257.18:10:12.18#ibcon#about to read 6, iclass 16, count 0 2006.257.18:10:12.18#ibcon#read 6, iclass 16, count 0 2006.257.18:10:12.18#ibcon#end of sib2, iclass 16, count 0 2006.257.18:10:12.18#ibcon#*mode == 0, iclass 16, count 0 2006.257.18:10:12.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.18:10:12.18#ibcon#[27=USB\r\n] 2006.257.18:10:12.18#ibcon#*before write, iclass 16, count 0 2006.257.18:10:12.18#ibcon#enter sib2, iclass 16, count 0 2006.257.18:10:12.18#ibcon#flushed, iclass 16, count 0 2006.257.18:10:12.18#ibcon#about to write, iclass 16, count 0 2006.257.18:10:12.18#ibcon#wrote, iclass 16, count 0 2006.257.18:10:12.18#ibcon#about to read 3, iclass 16, count 0 2006.257.18:10:12.21#ibcon#read 3, iclass 16, count 0 2006.257.18:10:12.21#ibcon#about to read 4, iclass 16, count 0 2006.257.18:10:12.21#ibcon#read 4, iclass 16, count 0 2006.257.18:10:12.21#ibcon#about to read 5, iclass 16, count 0 2006.257.18:10:12.21#ibcon#read 5, iclass 16, count 0 2006.257.18:10:12.21#ibcon#about to read 6, iclass 16, count 0 2006.257.18:10:12.21#ibcon#read 6, iclass 16, count 0 2006.257.18:10:12.21#ibcon#end of sib2, iclass 16, count 0 2006.257.18:10:12.21#ibcon#*after write, iclass 16, count 0 2006.257.18:10:12.21#ibcon#*before return 0, iclass 16, count 0 2006.257.18:10:12.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:12.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:10:12.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.18:10:12.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.18:10:12.21$vck44/vblo=7,734.99 2006.257.18:10:12.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.18:10:12.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.18:10:12.21#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:12.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:12.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:12.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:12.21#ibcon#enter wrdev, iclass 18, count 0 2006.257.18:10:12.21#ibcon#first serial, iclass 18, count 0 2006.257.18:10:12.21#ibcon#enter sib2, iclass 18, count 0 2006.257.18:10:12.21#ibcon#flushed, iclass 18, count 0 2006.257.18:10:12.21#ibcon#about to write, iclass 18, count 0 2006.257.18:10:12.21#ibcon#wrote, iclass 18, count 0 2006.257.18:10:12.21#ibcon#about to read 3, iclass 18, count 0 2006.257.18:10:12.23#ibcon#read 3, iclass 18, count 0 2006.257.18:10:12.23#ibcon#about to read 4, iclass 18, count 0 2006.257.18:10:12.23#ibcon#read 4, iclass 18, count 0 2006.257.18:10:12.23#ibcon#about to read 5, iclass 18, count 0 2006.257.18:10:12.23#ibcon#read 5, iclass 18, count 0 2006.257.18:10:12.23#ibcon#about to read 6, iclass 18, count 0 2006.257.18:10:12.23#ibcon#read 6, iclass 18, count 0 2006.257.18:10:12.23#ibcon#end of sib2, iclass 18, count 0 2006.257.18:10:12.23#ibcon#*mode == 0, iclass 18, count 0 2006.257.18:10:12.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.18:10:12.23#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:10:12.23#ibcon#*before write, iclass 18, count 0 2006.257.18:10:12.23#ibcon#enter sib2, iclass 18, count 0 2006.257.18:10:12.23#ibcon#flushed, iclass 18, count 0 2006.257.18:10:12.23#ibcon#about to write, iclass 18, count 0 2006.257.18:10:12.23#ibcon#wrote, iclass 18, count 0 2006.257.18:10:12.23#ibcon#about to read 3, iclass 18, count 0 2006.257.18:10:12.27#ibcon#read 3, iclass 18, count 0 2006.257.18:10:12.27#ibcon#about to read 4, iclass 18, count 0 2006.257.18:10:12.27#ibcon#read 4, iclass 18, count 0 2006.257.18:10:12.27#ibcon#about to read 5, iclass 18, count 0 2006.257.18:10:12.27#ibcon#read 5, iclass 18, count 0 2006.257.18:10:12.27#ibcon#about to read 6, iclass 18, count 0 2006.257.18:10:12.27#ibcon#read 6, iclass 18, count 0 2006.257.18:10:12.27#ibcon#end of sib2, iclass 18, count 0 2006.257.18:10:12.27#ibcon#*after write, iclass 18, count 0 2006.257.18:10:12.27#ibcon#*before return 0, iclass 18, count 0 2006.257.18:10:12.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:12.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:10:12.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.18:10:12.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.18:10:12.27$vck44/vb=7,4 2006.257.18:10:12.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.18:10:12.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.18:10:12.27#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:12.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:12.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:12.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:12.33#ibcon#enter wrdev, iclass 20, count 2 2006.257.18:10:12.33#ibcon#first serial, iclass 20, count 2 2006.257.18:10:12.33#ibcon#enter sib2, iclass 20, count 2 2006.257.18:10:12.33#ibcon#flushed, iclass 20, count 2 2006.257.18:10:12.33#ibcon#about to write, iclass 20, count 2 2006.257.18:10:12.33#ibcon#wrote, iclass 20, count 2 2006.257.18:10:12.33#ibcon#about to read 3, iclass 20, count 2 2006.257.18:10:12.35#ibcon#read 3, iclass 20, count 2 2006.257.18:10:12.35#ibcon#about to read 4, iclass 20, count 2 2006.257.18:10:12.35#ibcon#read 4, iclass 20, count 2 2006.257.18:10:12.35#ibcon#about to read 5, iclass 20, count 2 2006.257.18:10:12.35#ibcon#read 5, iclass 20, count 2 2006.257.18:10:12.35#ibcon#about to read 6, iclass 20, count 2 2006.257.18:10:12.35#ibcon#read 6, iclass 20, count 2 2006.257.18:10:12.35#ibcon#end of sib2, iclass 20, count 2 2006.257.18:10:12.35#ibcon#*mode == 0, iclass 20, count 2 2006.257.18:10:12.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.18:10:12.35#ibcon#[27=AT07-04\r\n] 2006.257.18:10:12.35#ibcon#*before write, iclass 20, count 2 2006.257.18:10:12.35#ibcon#enter sib2, iclass 20, count 2 2006.257.18:10:12.35#ibcon#flushed, iclass 20, count 2 2006.257.18:10:12.35#ibcon#about to write, iclass 20, count 2 2006.257.18:10:12.35#ibcon#wrote, iclass 20, count 2 2006.257.18:10:12.35#ibcon#about to read 3, iclass 20, count 2 2006.257.18:10:12.38#ibcon#read 3, iclass 20, count 2 2006.257.18:10:12.38#ibcon#about to read 4, iclass 20, count 2 2006.257.18:10:12.38#ibcon#read 4, iclass 20, count 2 2006.257.18:10:12.38#ibcon#about to read 5, iclass 20, count 2 2006.257.18:10:12.38#ibcon#read 5, iclass 20, count 2 2006.257.18:10:12.38#ibcon#about to read 6, iclass 20, count 2 2006.257.18:10:12.38#ibcon#read 6, iclass 20, count 2 2006.257.18:10:12.38#ibcon#end of sib2, iclass 20, count 2 2006.257.18:10:12.38#ibcon#*after write, iclass 20, count 2 2006.257.18:10:12.38#ibcon#*before return 0, iclass 20, count 2 2006.257.18:10:12.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:12.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:10:12.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.18:10:12.38#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:12.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:12.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:12.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:12.50#ibcon#enter wrdev, iclass 20, count 0 2006.257.18:10:12.50#ibcon#first serial, iclass 20, count 0 2006.257.18:10:12.50#ibcon#enter sib2, iclass 20, count 0 2006.257.18:10:12.50#ibcon#flushed, iclass 20, count 0 2006.257.18:10:12.50#ibcon#about to write, iclass 20, count 0 2006.257.18:10:12.50#ibcon#wrote, iclass 20, count 0 2006.257.18:10:12.50#ibcon#about to read 3, iclass 20, count 0 2006.257.18:10:12.52#ibcon#read 3, iclass 20, count 0 2006.257.18:10:12.52#ibcon#about to read 4, iclass 20, count 0 2006.257.18:10:12.52#ibcon#read 4, iclass 20, count 0 2006.257.18:10:12.52#ibcon#about to read 5, iclass 20, count 0 2006.257.18:10:12.52#ibcon#read 5, iclass 20, count 0 2006.257.18:10:12.52#ibcon#about to read 6, iclass 20, count 0 2006.257.18:10:12.52#ibcon#read 6, iclass 20, count 0 2006.257.18:10:12.52#ibcon#end of sib2, iclass 20, count 0 2006.257.18:10:12.52#ibcon#*mode == 0, iclass 20, count 0 2006.257.18:10:12.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.18:10:12.52#ibcon#[27=USB\r\n] 2006.257.18:10:12.52#ibcon#*before write, iclass 20, count 0 2006.257.18:10:12.52#ibcon#enter sib2, iclass 20, count 0 2006.257.18:10:12.52#ibcon#flushed, iclass 20, count 0 2006.257.18:10:12.52#ibcon#about to write, iclass 20, count 0 2006.257.18:10:12.52#ibcon#wrote, iclass 20, count 0 2006.257.18:10:12.52#ibcon#about to read 3, iclass 20, count 0 2006.257.18:10:12.55#ibcon#read 3, iclass 20, count 0 2006.257.18:10:12.55#ibcon#about to read 4, iclass 20, count 0 2006.257.18:10:12.55#ibcon#read 4, iclass 20, count 0 2006.257.18:10:12.55#ibcon#about to read 5, iclass 20, count 0 2006.257.18:10:12.55#ibcon#read 5, iclass 20, count 0 2006.257.18:10:12.55#ibcon#about to read 6, iclass 20, count 0 2006.257.18:10:12.55#ibcon#read 6, iclass 20, count 0 2006.257.18:10:12.55#ibcon#end of sib2, iclass 20, count 0 2006.257.18:10:12.55#ibcon#*after write, iclass 20, count 0 2006.257.18:10:12.55#ibcon#*before return 0, iclass 20, count 0 2006.257.18:10:12.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:12.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:10:12.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.18:10:12.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.18:10:12.55$vck44/vblo=8,744.99 2006.257.18:10:12.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.18:10:12.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.18:10:12.55#ibcon#ireg 17 cls_cnt 0 2006.257.18:10:12.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:12.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:12.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:12.55#ibcon#enter wrdev, iclass 22, count 0 2006.257.18:10:12.55#ibcon#first serial, iclass 22, count 0 2006.257.18:10:12.55#ibcon#enter sib2, iclass 22, count 0 2006.257.18:10:12.55#ibcon#flushed, iclass 22, count 0 2006.257.18:10:12.55#ibcon#about to write, iclass 22, count 0 2006.257.18:10:12.55#ibcon#wrote, iclass 22, count 0 2006.257.18:10:12.55#ibcon#about to read 3, iclass 22, count 0 2006.257.18:10:12.57#ibcon#read 3, iclass 22, count 0 2006.257.18:10:12.57#ibcon#about to read 4, iclass 22, count 0 2006.257.18:10:12.57#ibcon#read 4, iclass 22, count 0 2006.257.18:10:12.57#ibcon#about to read 5, iclass 22, count 0 2006.257.18:10:12.57#ibcon#read 5, iclass 22, count 0 2006.257.18:10:12.57#ibcon#about to read 6, iclass 22, count 0 2006.257.18:10:12.57#ibcon#read 6, iclass 22, count 0 2006.257.18:10:12.57#ibcon#end of sib2, iclass 22, count 0 2006.257.18:10:12.57#ibcon#*mode == 0, iclass 22, count 0 2006.257.18:10:12.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.18:10:12.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:10:12.57#ibcon#*before write, iclass 22, count 0 2006.257.18:10:12.57#ibcon#enter sib2, iclass 22, count 0 2006.257.18:10:12.57#ibcon#flushed, iclass 22, count 0 2006.257.18:10:12.57#ibcon#about to write, iclass 22, count 0 2006.257.18:10:12.57#ibcon#wrote, iclass 22, count 0 2006.257.18:10:12.57#ibcon#about to read 3, iclass 22, count 0 2006.257.18:10:12.61#ibcon#read 3, iclass 22, count 0 2006.257.18:10:12.61#ibcon#about to read 4, iclass 22, count 0 2006.257.18:10:12.61#ibcon#read 4, iclass 22, count 0 2006.257.18:10:12.61#ibcon#about to read 5, iclass 22, count 0 2006.257.18:10:12.61#ibcon#read 5, iclass 22, count 0 2006.257.18:10:12.61#ibcon#about to read 6, iclass 22, count 0 2006.257.18:10:12.61#ibcon#read 6, iclass 22, count 0 2006.257.18:10:12.61#ibcon#end of sib2, iclass 22, count 0 2006.257.18:10:12.61#ibcon#*after write, iclass 22, count 0 2006.257.18:10:12.61#ibcon#*before return 0, iclass 22, count 0 2006.257.18:10:12.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:12.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:10:12.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.18:10:12.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.18:10:12.61$vck44/vb=8,4 2006.257.18:10:12.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.18:10:12.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.18:10:12.61#ibcon#ireg 11 cls_cnt 2 2006.257.18:10:12.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:12.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:12.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:12.67#ibcon#enter wrdev, iclass 24, count 2 2006.257.18:10:12.67#ibcon#first serial, iclass 24, count 2 2006.257.18:10:12.67#ibcon#enter sib2, iclass 24, count 2 2006.257.18:10:12.67#ibcon#flushed, iclass 24, count 2 2006.257.18:10:12.67#ibcon#about to write, iclass 24, count 2 2006.257.18:10:12.67#ibcon#wrote, iclass 24, count 2 2006.257.18:10:12.67#ibcon#about to read 3, iclass 24, count 2 2006.257.18:10:12.69#ibcon#read 3, iclass 24, count 2 2006.257.18:10:12.69#ibcon#about to read 4, iclass 24, count 2 2006.257.18:10:12.69#ibcon#read 4, iclass 24, count 2 2006.257.18:10:12.69#ibcon#about to read 5, iclass 24, count 2 2006.257.18:10:12.69#ibcon#read 5, iclass 24, count 2 2006.257.18:10:12.69#ibcon#about to read 6, iclass 24, count 2 2006.257.18:10:12.69#ibcon#read 6, iclass 24, count 2 2006.257.18:10:12.69#ibcon#end of sib2, iclass 24, count 2 2006.257.18:10:12.69#ibcon#*mode == 0, iclass 24, count 2 2006.257.18:10:12.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.18:10:12.69#ibcon#[27=AT08-04\r\n] 2006.257.18:10:12.69#ibcon#*before write, iclass 24, count 2 2006.257.18:10:12.69#ibcon#enter sib2, iclass 24, count 2 2006.257.18:10:12.69#ibcon#flushed, iclass 24, count 2 2006.257.18:10:12.69#ibcon#about to write, iclass 24, count 2 2006.257.18:10:12.69#ibcon#wrote, iclass 24, count 2 2006.257.18:10:12.69#ibcon#about to read 3, iclass 24, count 2 2006.257.18:10:12.72#ibcon#read 3, iclass 24, count 2 2006.257.18:10:12.72#ibcon#about to read 4, iclass 24, count 2 2006.257.18:10:12.72#ibcon#read 4, iclass 24, count 2 2006.257.18:10:12.72#ibcon#about to read 5, iclass 24, count 2 2006.257.18:10:12.72#ibcon#read 5, iclass 24, count 2 2006.257.18:10:12.72#ibcon#about to read 6, iclass 24, count 2 2006.257.18:10:12.72#ibcon#read 6, iclass 24, count 2 2006.257.18:10:12.72#ibcon#end of sib2, iclass 24, count 2 2006.257.18:10:12.72#ibcon#*after write, iclass 24, count 2 2006.257.18:10:12.72#ibcon#*before return 0, iclass 24, count 2 2006.257.18:10:12.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:12.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:10:12.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.18:10:12.72#ibcon#ireg 7 cls_cnt 0 2006.257.18:10:12.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:12.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:12.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:12.84#ibcon#enter wrdev, iclass 24, count 0 2006.257.18:10:12.84#ibcon#first serial, iclass 24, count 0 2006.257.18:10:12.84#ibcon#enter sib2, iclass 24, count 0 2006.257.18:10:12.84#ibcon#flushed, iclass 24, count 0 2006.257.18:10:12.84#ibcon#about to write, iclass 24, count 0 2006.257.18:10:12.84#ibcon#wrote, iclass 24, count 0 2006.257.18:10:12.84#ibcon#about to read 3, iclass 24, count 0 2006.257.18:10:12.86#ibcon#read 3, iclass 24, count 0 2006.257.18:10:12.86#ibcon#about to read 4, iclass 24, count 0 2006.257.18:10:12.86#ibcon#read 4, iclass 24, count 0 2006.257.18:10:12.86#ibcon#about to read 5, iclass 24, count 0 2006.257.18:10:12.86#ibcon#read 5, iclass 24, count 0 2006.257.18:10:12.86#ibcon#about to read 6, iclass 24, count 0 2006.257.18:10:12.86#ibcon#read 6, iclass 24, count 0 2006.257.18:10:12.86#ibcon#end of sib2, iclass 24, count 0 2006.257.18:10:12.86#ibcon#*mode == 0, iclass 24, count 0 2006.257.18:10:12.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.18:10:12.86#ibcon#[27=USB\r\n] 2006.257.18:10:12.86#ibcon#*before write, iclass 24, count 0 2006.257.18:10:12.86#ibcon#enter sib2, iclass 24, count 0 2006.257.18:10:12.86#ibcon#flushed, iclass 24, count 0 2006.257.18:10:12.86#ibcon#about to write, iclass 24, count 0 2006.257.18:10:12.86#ibcon#wrote, iclass 24, count 0 2006.257.18:10:12.86#ibcon#about to read 3, iclass 24, count 0 2006.257.18:10:12.89#ibcon#read 3, iclass 24, count 0 2006.257.18:10:12.89#ibcon#about to read 4, iclass 24, count 0 2006.257.18:10:12.89#ibcon#read 4, iclass 24, count 0 2006.257.18:10:12.89#ibcon#about to read 5, iclass 24, count 0 2006.257.18:10:12.89#ibcon#read 5, iclass 24, count 0 2006.257.18:10:12.89#ibcon#about to read 6, iclass 24, count 0 2006.257.18:10:12.89#ibcon#read 6, iclass 24, count 0 2006.257.18:10:12.89#ibcon#end of sib2, iclass 24, count 0 2006.257.18:10:12.89#ibcon#*after write, iclass 24, count 0 2006.257.18:10:12.89#ibcon#*before return 0, iclass 24, count 0 2006.257.18:10:12.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:12.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:10:12.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.18:10:12.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.18:10:12.89$vck44/vabw=wide 2006.257.18:10:12.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.18:10:12.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.18:10:12.89#ibcon#ireg 8 cls_cnt 0 2006.257.18:10:12.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:12.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:12.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:12.89#ibcon#enter wrdev, iclass 26, count 0 2006.257.18:10:12.89#ibcon#first serial, iclass 26, count 0 2006.257.18:10:12.89#ibcon#enter sib2, iclass 26, count 0 2006.257.18:10:12.89#ibcon#flushed, iclass 26, count 0 2006.257.18:10:12.89#ibcon#about to write, iclass 26, count 0 2006.257.18:10:12.89#ibcon#wrote, iclass 26, count 0 2006.257.18:10:12.89#ibcon#about to read 3, iclass 26, count 0 2006.257.18:10:12.91#ibcon#read 3, iclass 26, count 0 2006.257.18:10:12.91#ibcon#about to read 4, iclass 26, count 0 2006.257.18:10:12.91#ibcon#read 4, iclass 26, count 0 2006.257.18:10:12.91#ibcon#about to read 5, iclass 26, count 0 2006.257.18:10:12.91#ibcon#read 5, iclass 26, count 0 2006.257.18:10:12.91#ibcon#about to read 6, iclass 26, count 0 2006.257.18:10:12.91#ibcon#read 6, iclass 26, count 0 2006.257.18:10:12.91#ibcon#end of sib2, iclass 26, count 0 2006.257.18:10:12.91#ibcon#*mode == 0, iclass 26, count 0 2006.257.18:10:12.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.18:10:12.91#ibcon#[25=BW32\r\n] 2006.257.18:10:12.91#ibcon#*before write, iclass 26, count 0 2006.257.18:10:12.91#ibcon#enter sib2, iclass 26, count 0 2006.257.18:10:12.91#ibcon#flushed, iclass 26, count 0 2006.257.18:10:12.91#ibcon#about to write, iclass 26, count 0 2006.257.18:10:12.91#ibcon#wrote, iclass 26, count 0 2006.257.18:10:12.91#ibcon#about to read 3, iclass 26, count 0 2006.257.18:10:12.94#ibcon#read 3, iclass 26, count 0 2006.257.18:10:12.94#ibcon#about to read 4, iclass 26, count 0 2006.257.18:10:12.94#ibcon#read 4, iclass 26, count 0 2006.257.18:10:12.94#ibcon#about to read 5, iclass 26, count 0 2006.257.18:10:12.94#ibcon#read 5, iclass 26, count 0 2006.257.18:10:12.94#ibcon#about to read 6, iclass 26, count 0 2006.257.18:10:12.94#ibcon#read 6, iclass 26, count 0 2006.257.18:10:12.94#ibcon#end of sib2, iclass 26, count 0 2006.257.18:10:12.94#ibcon#*after write, iclass 26, count 0 2006.257.18:10:12.94#ibcon#*before return 0, iclass 26, count 0 2006.257.18:10:12.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:12.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:10:12.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.18:10:12.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.18:10:12.94$vck44/vbbw=wide 2006.257.18:10:12.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.18:10:12.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.18:10:12.94#ibcon#ireg 8 cls_cnt 0 2006.257.18:10:12.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:10:13.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:10:13.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:10:13.01#ibcon#enter wrdev, iclass 28, count 0 2006.257.18:10:13.01#ibcon#first serial, iclass 28, count 0 2006.257.18:10:13.01#ibcon#enter sib2, iclass 28, count 0 2006.257.18:10:13.01#ibcon#flushed, iclass 28, count 0 2006.257.18:10:13.01#ibcon#about to write, iclass 28, count 0 2006.257.18:10:13.01#ibcon#wrote, iclass 28, count 0 2006.257.18:10:13.01#ibcon#about to read 3, iclass 28, count 0 2006.257.18:10:13.03#ibcon#read 3, iclass 28, count 0 2006.257.18:10:13.03#ibcon#about to read 4, iclass 28, count 0 2006.257.18:10:13.03#ibcon#read 4, iclass 28, count 0 2006.257.18:10:13.03#ibcon#about to read 5, iclass 28, count 0 2006.257.18:10:13.03#ibcon#read 5, iclass 28, count 0 2006.257.18:10:13.03#ibcon#about to read 6, iclass 28, count 0 2006.257.18:10:13.03#ibcon#read 6, iclass 28, count 0 2006.257.18:10:13.03#ibcon#end of sib2, iclass 28, count 0 2006.257.18:10:13.03#ibcon#*mode == 0, iclass 28, count 0 2006.257.18:10:13.03#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.18:10:13.03#ibcon#[27=BW32\r\n] 2006.257.18:10:13.03#ibcon#*before write, iclass 28, count 0 2006.257.18:10:13.03#ibcon#enter sib2, iclass 28, count 0 2006.257.18:10:13.03#ibcon#flushed, iclass 28, count 0 2006.257.18:10:13.03#ibcon#about to write, iclass 28, count 0 2006.257.18:10:13.03#ibcon#wrote, iclass 28, count 0 2006.257.18:10:13.03#ibcon#about to read 3, iclass 28, count 0 2006.257.18:10:13.06#ibcon#read 3, iclass 28, count 0 2006.257.18:10:13.06#ibcon#about to read 4, iclass 28, count 0 2006.257.18:10:13.06#ibcon#read 4, iclass 28, count 0 2006.257.18:10:13.06#ibcon#about to read 5, iclass 28, count 0 2006.257.18:10:13.06#ibcon#read 5, iclass 28, count 0 2006.257.18:10:13.06#ibcon#about to read 6, iclass 28, count 0 2006.257.18:10:13.06#ibcon#read 6, iclass 28, count 0 2006.257.18:10:13.06#ibcon#end of sib2, iclass 28, count 0 2006.257.18:10:13.06#ibcon#*after write, iclass 28, count 0 2006.257.18:10:13.06#ibcon#*before return 0, iclass 28, count 0 2006.257.18:10:13.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:10:13.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:10:13.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.18:10:13.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.18:10:13.06$setupk4/ifdk4 2006.257.18:10:13.06$ifdk4/lo= 2006.257.18:10:13.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:10:13.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:10:13.06$ifdk4/patch= 2006.257.18:10:13.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:10:13.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:10:13.06$setupk4/!*+20s 2006.257.18:10:17.80#abcon#<5=/14 1.5 3.4 17.21 981014.4\r\n> 2006.257.18:10:17.82#abcon#{5=INTERFACE CLEAR} 2006.257.18:10:17.88#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:10:27.57$setupk4/"tpicd 2006.257.18:10:27.57$setupk4/echo=off 2006.257.18:10:27.57$setupk4/xlog=off 2006.257.18:10:27.57:!2006.257.18:15:18 2006.257.18:10:32.13#trakl#Source acquired 2006.257.18:10:34.13#flagr#flagr/antenna,acquired 2006.257.18:15:18.00:preob 2006.257.18:15:18.14/onsource/TRACKING 2006.257.18:15:18.14:!2006.257.18:15:28 2006.257.18:15:28.00:"tape 2006.257.18:15:28.00:"st=record 2006.257.18:15:28.00:data_valid=on 2006.257.18:15:28.00:midob 2006.257.18:15:28.14/onsource/TRACKING 2006.257.18:15:28.14/wx/17.24,1014.4,98 2006.257.18:15:28.28/cable/+6.4842E-03 2006.257.18:15:29.37/va/01,08,usb,yes,32,34 2006.257.18:15:29.37/va/02,07,usb,yes,34,35 2006.257.18:15:29.37/va/03,08,usb,yes,30,33 2006.257.18:15:29.37/va/04,07,usb,yes,35,37 2006.257.18:15:29.37/va/05,04,usb,yes,31,32 2006.257.18:15:29.37/va/06,04,usb,yes,35,34 2006.257.18:15:29.37/va/07,04,usb,yes,35,36 2006.257.18:15:29.37/va/08,04,usb,yes,30,36 2006.257.18:15:29.60/valo/01,524.99,yes,locked 2006.257.18:15:29.60/valo/02,534.99,yes,locked 2006.257.18:15:29.60/valo/03,564.99,yes,locked 2006.257.18:15:29.60/valo/04,624.99,yes,locked 2006.257.18:15:29.60/valo/05,734.99,yes,locked 2006.257.18:15:29.60/valo/06,814.99,yes,locked 2006.257.18:15:29.60/valo/07,864.99,yes,locked 2006.257.18:15:29.60/valo/08,884.99,yes,locked 2006.257.18:15:30.69/vb/01,04,usb,yes,30,28 2006.257.18:15:30.69/vb/02,05,usb,yes,28,28 2006.257.18:15:30.69/vb/03,04,usb,yes,29,32 2006.257.18:15:30.69/vb/04,05,usb,yes,29,28 2006.257.18:15:30.69/vb/05,04,usb,yes,26,29 2006.257.18:15:30.69/vb/06,04,usb,yes,31,27 2006.257.18:15:30.69/vb/07,04,usb,yes,30,30 2006.257.18:15:30.69/vb/08,04,usb,yes,28,31 2006.257.18:15:30.92/vblo/01,629.99,yes,locked 2006.257.18:15:30.92/vblo/02,634.99,yes,locked 2006.257.18:15:30.92/vblo/03,649.99,yes,locked 2006.257.18:15:30.92/vblo/04,679.99,yes,locked 2006.257.18:15:30.92/vblo/05,709.99,yes,locked 2006.257.18:15:30.92/vblo/06,719.99,yes,locked 2006.257.18:15:30.92/vblo/07,734.99,yes,locked 2006.257.18:15:30.92/vblo/08,744.99,yes,locked 2006.257.18:15:31.07/vabw/8 2006.257.18:15:31.22/vbbw/8 2006.257.18:15:31.31/xfe/off,on,15.0 2006.257.18:15:31.69/ifatt/23,28,28,28 2006.257.18:15:32.07/fmout-gps/S +4.52E-07 2006.257.18:15:32.11:!2006.257.18:17:08 2006.257.18:17:08.01:data_valid=off 2006.257.18:17:08.01:"et 2006.257.18:17:08.01:!+3s 2006.257.18:17:11.02:"tape 2006.257.18:17:11.02:postob 2006.257.18:17:11.15/cable/+6.4837E-03 2006.257.18:17:11.15/wx/17.25,1014.3,98 2006.257.18:17:11.21/fmout-gps/S +4.53E-07 2006.257.18:17:11.21:scan_name=257-1819,jd0609,40 2006.257.18:17:11.21:source=2121+053,212344.52,053522.1,2000.0,cw 2006.257.18:17:13.14#flagr#flagr/antenna,new-source 2006.257.18:17:13.14:checkk5 2006.257.18:17:13.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:17:13.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:17:14.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:17:14.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:17:14.84/chk_obsdata//k5ts1/T2571815??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.18:17:15.17/chk_obsdata//k5ts2/T2571815??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.18:17:15.50/chk_obsdata//k5ts3/T2571815??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.18:17:15.83/chk_obsdata//k5ts4/T2571815??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.18:17:16.48/k5log//k5ts1_log_newline 2006.257.18:17:17.15/k5log//k5ts2_log_newline 2006.257.18:17:17.81/k5log//k5ts3_log_newline 2006.257.18:17:18.46/k5log//k5ts4_log_newline 2006.257.18:17:18.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:17:18.49:setupk4=1 2006.257.18:17:18.49$setupk4/echo=on 2006.257.18:17:18.49$setupk4/pcalon 2006.257.18:17:18.49$pcalon/"no phase cal control is implemented here 2006.257.18:17:18.49$setupk4/"tpicd=stop 2006.257.18:17:18.49$setupk4/"rec=synch_on 2006.257.18:17:18.49$setupk4/"rec_mode=128 2006.257.18:17:18.49$setupk4/!* 2006.257.18:17:18.49$setupk4/recpk4 2006.257.18:17:18.49$recpk4/recpatch= 2006.257.18:17:18.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:17:18.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:17:18.49$setupk4/vck44 2006.257.18:17:18.49$vck44/valo=1,524.99 2006.257.18:17:18.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.18:17:18.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.18:17:18.49#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:18.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:18.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:18.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:18.49#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:17:18.49#ibcon#first serial, iclass 21, count 0 2006.257.18:17:18.49#ibcon#enter sib2, iclass 21, count 0 2006.257.18:17:18.49#ibcon#flushed, iclass 21, count 0 2006.257.18:17:18.49#ibcon#about to write, iclass 21, count 0 2006.257.18:17:18.49#ibcon#wrote, iclass 21, count 0 2006.257.18:17:18.49#ibcon#about to read 3, iclass 21, count 0 2006.257.18:17:18.51#ibcon#read 3, iclass 21, count 0 2006.257.18:17:18.51#ibcon#about to read 4, iclass 21, count 0 2006.257.18:17:18.51#ibcon#read 4, iclass 21, count 0 2006.257.18:17:18.51#ibcon#about to read 5, iclass 21, count 0 2006.257.18:17:18.51#ibcon#read 5, iclass 21, count 0 2006.257.18:17:18.51#ibcon#about to read 6, iclass 21, count 0 2006.257.18:17:18.51#ibcon#read 6, iclass 21, count 0 2006.257.18:17:18.51#ibcon#end of sib2, iclass 21, count 0 2006.257.18:17:18.51#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:17:18.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:17:18.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:17:18.51#ibcon#*before write, iclass 21, count 0 2006.257.18:17:18.51#ibcon#enter sib2, iclass 21, count 0 2006.257.18:17:18.51#ibcon#flushed, iclass 21, count 0 2006.257.18:17:18.51#ibcon#about to write, iclass 21, count 0 2006.257.18:17:18.51#ibcon#wrote, iclass 21, count 0 2006.257.18:17:18.51#ibcon#about to read 3, iclass 21, count 0 2006.257.18:17:18.56#ibcon#read 3, iclass 21, count 0 2006.257.18:17:18.56#ibcon#about to read 4, iclass 21, count 0 2006.257.18:17:18.56#ibcon#read 4, iclass 21, count 0 2006.257.18:17:18.56#ibcon#about to read 5, iclass 21, count 0 2006.257.18:17:18.56#ibcon#read 5, iclass 21, count 0 2006.257.18:17:18.56#ibcon#about to read 6, iclass 21, count 0 2006.257.18:17:18.56#ibcon#read 6, iclass 21, count 0 2006.257.18:17:18.56#ibcon#end of sib2, iclass 21, count 0 2006.257.18:17:18.56#ibcon#*after write, iclass 21, count 0 2006.257.18:17:18.56#ibcon#*before return 0, iclass 21, count 0 2006.257.18:17:18.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:18.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:18.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:17:18.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:17:18.56$vck44/va=1,8 2006.257.18:17:18.56#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.18:17:18.56#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.18:17:18.56#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:18.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:18.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:18.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:18.56#ibcon#enter wrdev, iclass 23, count 2 2006.257.18:17:18.56#ibcon#first serial, iclass 23, count 2 2006.257.18:17:18.56#ibcon#enter sib2, iclass 23, count 2 2006.257.18:17:18.56#ibcon#flushed, iclass 23, count 2 2006.257.18:17:18.56#ibcon#about to write, iclass 23, count 2 2006.257.18:17:18.56#ibcon#wrote, iclass 23, count 2 2006.257.18:17:18.56#ibcon#about to read 3, iclass 23, count 2 2006.257.18:17:18.58#ibcon#read 3, iclass 23, count 2 2006.257.18:17:18.58#ibcon#about to read 4, iclass 23, count 2 2006.257.18:17:18.58#ibcon#read 4, iclass 23, count 2 2006.257.18:17:18.58#ibcon#about to read 5, iclass 23, count 2 2006.257.18:17:18.58#ibcon#read 5, iclass 23, count 2 2006.257.18:17:18.58#ibcon#about to read 6, iclass 23, count 2 2006.257.18:17:18.58#ibcon#read 6, iclass 23, count 2 2006.257.18:17:18.58#ibcon#end of sib2, iclass 23, count 2 2006.257.18:17:18.58#ibcon#*mode == 0, iclass 23, count 2 2006.257.18:17:18.58#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.18:17:18.58#ibcon#[25=AT01-08\r\n] 2006.257.18:17:18.58#ibcon#*before write, iclass 23, count 2 2006.257.18:17:18.58#ibcon#enter sib2, iclass 23, count 2 2006.257.18:17:18.58#ibcon#flushed, iclass 23, count 2 2006.257.18:17:18.58#ibcon#about to write, iclass 23, count 2 2006.257.18:17:18.58#ibcon#wrote, iclass 23, count 2 2006.257.18:17:18.58#ibcon#about to read 3, iclass 23, count 2 2006.257.18:17:18.61#ibcon#read 3, iclass 23, count 2 2006.257.18:17:18.61#ibcon#about to read 4, iclass 23, count 2 2006.257.18:17:18.61#ibcon#read 4, iclass 23, count 2 2006.257.18:17:18.61#ibcon#about to read 5, iclass 23, count 2 2006.257.18:17:18.61#ibcon#read 5, iclass 23, count 2 2006.257.18:17:18.61#ibcon#about to read 6, iclass 23, count 2 2006.257.18:17:18.61#ibcon#read 6, iclass 23, count 2 2006.257.18:17:18.61#ibcon#end of sib2, iclass 23, count 2 2006.257.18:17:18.61#ibcon#*after write, iclass 23, count 2 2006.257.18:17:18.61#ibcon#*before return 0, iclass 23, count 2 2006.257.18:17:18.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:18.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:18.61#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.18:17:18.61#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:18.61#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:18.73#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:18.73#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:18.73#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:17:18.73#ibcon#first serial, iclass 23, count 0 2006.257.18:17:18.73#ibcon#enter sib2, iclass 23, count 0 2006.257.18:17:18.73#ibcon#flushed, iclass 23, count 0 2006.257.18:17:18.73#ibcon#about to write, iclass 23, count 0 2006.257.18:17:18.73#ibcon#wrote, iclass 23, count 0 2006.257.18:17:18.73#ibcon#about to read 3, iclass 23, count 0 2006.257.18:17:18.75#ibcon#read 3, iclass 23, count 0 2006.257.18:17:18.75#ibcon#about to read 4, iclass 23, count 0 2006.257.18:17:18.75#ibcon#read 4, iclass 23, count 0 2006.257.18:17:18.75#ibcon#about to read 5, iclass 23, count 0 2006.257.18:17:18.75#ibcon#read 5, iclass 23, count 0 2006.257.18:17:18.75#ibcon#about to read 6, iclass 23, count 0 2006.257.18:17:18.75#ibcon#read 6, iclass 23, count 0 2006.257.18:17:18.75#ibcon#end of sib2, iclass 23, count 0 2006.257.18:17:18.75#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:17:18.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:17:18.75#ibcon#[25=USB\r\n] 2006.257.18:17:18.75#ibcon#*before write, iclass 23, count 0 2006.257.18:17:18.75#ibcon#enter sib2, iclass 23, count 0 2006.257.18:17:18.75#ibcon#flushed, iclass 23, count 0 2006.257.18:17:18.75#ibcon#about to write, iclass 23, count 0 2006.257.18:17:18.75#ibcon#wrote, iclass 23, count 0 2006.257.18:17:18.75#ibcon#about to read 3, iclass 23, count 0 2006.257.18:17:18.78#ibcon#read 3, iclass 23, count 0 2006.257.18:17:18.78#ibcon#about to read 4, iclass 23, count 0 2006.257.18:17:18.78#ibcon#read 4, iclass 23, count 0 2006.257.18:17:18.78#ibcon#about to read 5, iclass 23, count 0 2006.257.18:17:18.78#ibcon#read 5, iclass 23, count 0 2006.257.18:17:18.78#ibcon#about to read 6, iclass 23, count 0 2006.257.18:17:18.78#ibcon#read 6, iclass 23, count 0 2006.257.18:17:18.78#ibcon#end of sib2, iclass 23, count 0 2006.257.18:17:18.78#ibcon#*after write, iclass 23, count 0 2006.257.18:17:18.78#ibcon#*before return 0, iclass 23, count 0 2006.257.18:17:18.78#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:18.78#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:18.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:17:18.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:17:18.78$vck44/valo=2,534.99 2006.257.18:17:18.78#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.18:17:18.78#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.18:17:18.78#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:18.78#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:18.78#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:18.78#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:18.78#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:17:18.78#ibcon#first serial, iclass 25, count 0 2006.257.18:17:18.78#ibcon#enter sib2, iclass 25, count 0 2006.257.18:17:18.78#ibcon#flushed, iclass 25, count 0 2006.257.18:17:18.78#ibcon#about to write, iclass 25, count 0 2006.257.18:17:18.78#ibcon#wrote, iclass 25, count 0 2006.257.18:17:18.78#ibcon#about to read 3, iclass 25, count 0 2006.257.18:17:18.80#ibcon#read 3, iclass 25, count 0 2006.257.18:17:18.80#ibcon#about to read 4, iclass 25, count 0 2006.257.18:17:18.80#ibcon#read 4, iclass 25, count 0 2006.257.18:17:18.80#ibcon#about to read 5, iclass 25, count 0 2006.257.18:17:18.80#ibcon#read 5, iclass 25, count 0 2006.257.18:17:18.80#ibcon#about to read 6, iclass 25, count 0 2006.257.18:17:18.80#ibcon#read 6, iclass 25, count 0 2006.257.18:17:18.80#ibcon#end of sib2, iclass 25, count 0 2006.257.18:17:18.80#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:17:18.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:17:18.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:17:18.80#ibcon#*before write, iclass 25, count 0 2006.257.18:17:18.80#ibcon#enter sib2, iclass 25, count 0 2006.257.18:17:18.80#ibcon#flushed, iclass 25, count 0 2006.257.18:17:18.80#ibcon#about to write, iclass 25, count 0 2006.257.18:17:18.80#ibcon#wrote, iclass 25, count 0 2006.257.18:17:18.80#ibcon#about to read 3, iclass 25, count 0 2006.257.18:17:18.84#ibcon#read 3, iclass 25, count 0 2006.257.18:17:18.84#ibcon#about to read 4, iclass 25, count 0 2006.257.18:17:18.84#ibcon#read 4, iclass 25, count 0 2006.257.18:17:18.84#ibcon#about to read 5, iclass 25, count 0 2006.257.18:17:18.84#ibcon#read 5, iclass 25, count 0 2006.257.18:17:18.84#ibcon#about to read 6, iclass 25, count 0 2006.257.18:17:18.84#ibcon#read 6, iclass 25, count 0 2006.257.18:17:18.84#ibcon#end of sib2, iclass 25, count 0 2006.257.18:17:18.84#ibcon#*after write, iclass 25, count 0 2006.257.18:17:18.84#ibcon#*before return 0, iclass 25, count 0 2006.257.18:17:18.84#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:18.84#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:18.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:17:18.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:17:18.84$vck44/va=2,7 2006.257.18:17:18.84#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.18:17:18.84#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.18:17:18.84#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:18.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:18.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:18.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:18.90#ibcon#enter wrdev, iclass 27, count 2 2006.257.18:17:18.90#ibcon#first serial, iclass 27, count 2 2006.257.18:17:18.90#ibcon#enter sib2, iclass 27, count 2 2006.257.18:17:18.90#ibcon#flushed, iclass 27, count 2 2006.257.18:17:18.90#ibcon#about to write, iclass 27, count 2 2006.257.18:17:18.90#ibcon#wrote, iclass 27, count 2 2006.257.18:17:18.90#ibcon#about to read 3, iclass 27, count 2 2006.257.18:17:18.92#ibcon#read 3, iclass 27, count 2 2006.257.18:17:18.92#ibcon#about to read 4, iclass 27, count 2 2006.257.18:17:18.92#ibcon#read 4, iclass 27, count 2 2006.257.18:17:18.92#ibcon#about to read 5, iclass 27, count 2 2006.257.18:17:18.92#ibcon#read 5, iclass 27, count 2 2006.257.18:17:18.92#ibcon#about to read 6, iclass 27, count 2 2006.257.18:17:18.92#ibcon#read 6, iclass 27, count 2 2006.257.18:17:18.92#ibcon#end of sib2, iclass 27, count 2 2006.257.18:17:18.92#ibcon#*mode == 0, iclass 27, count 2 2006.257.18:17:18.92#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.18:17:18.92#ibcon#[25=AT02-07\r\n] 2006.257.18:17:18.92#ibcon#*before write, iclass 27, count 2 2006.257.18:17:18.92#ibcon#enter sib2, iclass 27, count 2 2006.257.18:17:18.92#ibcon#flushed, iclass 27, count 2 2006.257.18:17:18.92#ibcon#about to write, iclass 27, count 2 2006.257.18:17:18.92#ibcon#wrote, iclass 27, count 2 2006.257.18:17:18.92#ibcon#about to read 3, iclass 27, count 2 2006.257.18:17:18.95#ibcon#read 3, iclass 27, count 2 2006.257.18:17:18.95#ibcon#about to read 4, iclass 27, count 2 2006.257.18:17:18.95#ibcon#read 4, iclass 27, count 2 2006.257.18:17:18.95#ibcon#about to read 5, iclass 27, count 2 2006.257.18:17:18.95#ibcon#read 5, iclass 27, count 2 2006.257.18:17:18.95#ibcon#about to read 6, iclass 27, count 2 2006.257.18:17:18.95#ibcon#read 6, iclass 27, count 2 2006.257.18:17:18.95#ibcon#end of sib2, iclass 27, count 2 2006.257.18:17:18.95#ibcon#*after write, iclass 27, count 2 2006.257.18:17:18.95#ibcon#*before return 0, iclass 27, count 2 2006.257.18:17:18.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:18.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:18.95#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.18:17:18.95#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:18.95#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:19.07#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:19.07#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:19.07#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:17:19.07#ibcon#first serial, iclass 27, count 0 2006.257.18:17:19.07#ibcon#enter sib2, iclass 27, count 0 2006.257.18:17:19.07#ibcon#flushed, iclass 27, count 0 2006.257.18:17:19.07#ibcon#about to write, iclass 27, count 0 2006.257.18:17:19.07#ibcon#wrote, iclass 27, count 0 2006.257.18:17:19.07#ibcon#about to read 3, iclass 27, count 0 2006.257.18:17:19.09#ibcon#read 3, iclass 27, count 0 2006.257.18:17:19.09#ibcon#about to read 4, iclass 27, count 0 2006.257.18:17:19.09#ibcon#read 4, iclass 27, count 0 2006.257.18:17:19.09#ibcon#about to read 5, iclass 27, count 0 2006.257.18:17:19.09#ibcon#read 5, iclass 27, count 0 2006.257.18:17:19.09#ibcon#about to read 6, iclass 27, count 0 2006.257.18:17:19.09#ibcon#read 6, iclass 27, count 0 2006.257.18:17:19.09#ibcon#end of sib2, iclass 27, count 0 2006.257.18:17:19.09#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:17:19.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:17:19.09#ibcon#[25=USB\r\n] 2006.257.18:17:19.09#ibcon#*before write, iclass 27, count 0 2006.257.18:17:19.09#ibcon#enter sib2, iclass 27, count 0 2006.257.18:17:19.09#ibcon#flushed, iclass 27, count 0 2006.257.18:17:19.09#ibcon#about to write, iclass 27, count 0 2006.257.18:17:19.09#ibcon#wrote, iclass 27, count 0 2006.257.18:17:19.09#ibcon#about to read 3, iclass 27, count 0 2006.257.18:17:19.12#ibcon#read 3, iclass 27, count 0 2006.257.18:17:19.12#ibcon#about to read 4, iclass 27, count 0 2006.257.18:17:19.12#ibcon#read 4, iclass 27, count 0 2006.257.18:17:19.12#ibcon#about to read 5, iclass 27, count 0 2006.257.18:17:19.12#ibcon#read 5, iclass 27, count 0 2006.257.18:17:19.12#ibcon#about to read 6, iclass 27, count 0 2006.257.18:17:19.12#ibcon#read 6, iclass 27, count 0 2006.257.18:17:19.12#ibcon#end of sib2, iclass 27, count 0 2006.257.18:17:19.12#ibcon#*after write, iclass 27, count 0 2006.257.18:17:19.12#ibcon#*before return 0, iclass 27, count 0 2006.257.18:17:19.12#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:19.12#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:19.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:17:19.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:17:19.12$vck44/valo=3,564.99 2006.257.18:17:19.12#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.18:17:19.12#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.18:17:19.12#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:19.12#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:19.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:19.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:19.12#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:17:19.12#ibcon#first serial, iclass 29, count 0 2006.257.18:17:19.12#ibcon#enter sib2, iclass 29, count 0 2006.257.18:17:19.12#ibcon#flushed, iclass 29, count 0 2006.257.18:17:19.12#ibcon#about to write, iclass 29, count 0 2006.257.18:17:19.12#ibcon#wrote, iclass 29, count 0 2006.257.18:17:19.12#ibcon#about to read 3, iclass 29, count 0 2006.257.18:17:19.14#ibcon#read 3, iclass 29, count 0 2006.257.18:17:19.14#ibcon#about to read 4, iclass 29, count 0 2006.257.18:17:19.14#ibcon#read 4, iclass 29, count 0 2006.257.18:17:19.14#ibcon#about to read 5, iclass 29, count 0 2006.257.18:17:19.14#ibcon#read 5, iclass 29, count 0 2006.257.18:17:19.14#ibcon#about to read 6, iclass 29, count 0 2006.257.18:17:19.14#ibcon#read 6, iclass 29, count 0 2006.257.18:17:19.14#ibcon#end of sib2, iclass 29, count 0 2006.257.18:17:19.14#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:17:19.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:17:19.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:17:19.14#ibcon#*before write, iclass 29, count 0 2006.257.18:17:19.14#ibcon#enter sib2, iclass 29, count 0 2006.257.18:17:19.14#ibcon#flushed, iclass 29, count 0 2006.257.18:17:19.14#ibcon#about to write, iclass 29, count 0 2006.257.18:17:19.14#ibcon#wrote, iclass 29, count 0 2006.257.18:17:19.14#ibcon#about to read 3, iclass 29, count 0 2006.257.18:17:19.18#ibcon#read 3, iclass 29, count 0 2006.257.18:17:19.18#ibcon#about to read 4, iclass 29, count 0 2006.257.18:17:19.18#ibcon#read 4, iclass 29, count 0 2006.257.18:17:19.18#ibcon#about to read 5, iclass 29, count 0 2006.257.18:17:19.18#ibcon#read 5, iclass 29, count 0 2006.257.18:17:19.18#ibcon#about to read 6, iclass 29, count 0 2006.257.18:17:19.18#ibcon#read 6, iclass 29, count 0 2006.257.18:17:19.18#ibcon#end of sib2, iclass 29, count 0 2006.257.18:17:19.18#ibcon#*after write, iclass 29, count 0 2006.257.18:17:19.18#ibcon#*before return 0, iclass 29, count 0 2006.257.18:17:19.18#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:19.18#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:19.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:17:19.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:17:19.18$vck44/va=3,8 2006.257.18:17:19.18#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.18:17:19.18#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.18:17:19.18#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:19.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:19.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:19.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:19.24#ibcon#enter wrdev, iclass 31, count 2 2006.257.18:17:19.24#ibcon#first serial, iclass 31, count 2 2006.257.18:17:19.24#ibcon#enter sib2, iclass 31, count 2 2006.257.18:17:19.24#ibcon#flushed, iclass 31, count 2 2006.257.18:17:19.24#ibcon#about to write, iclass 31, count 2 2006.257.18:17:19.24#ibcon#wrote, iclass 31, count 2 2006.257.18:17:19.24#ibcon#about to read 3, iclass 31, count 2 2006.257.18:17:19.26#ibcon#read 3, iclass 31, count 2 2006.257.18:17:19.26#ibcon#about to read 4, iclass 31, count 2 2006.257.18:17:19.26#ibcon#read 4, iclass 31, count 2 2006.257.18:17:19.26#ibcon#about to read 5, iclass 31, count 2 2006.257.18:17:19.26#ibcon#read 5, iclass 31, count 2 2006.257.18:17:19.26#ibcon#about to read 6, iclass 31, count 2 2006.257.18:17:19.26#ibcon#read 6, iclass 31, count 2 2006.257.18:17:19.26#ibcon#end of sib2, iclass 31, count 2 2006.257.18:17:19.26#ibcon#*mode == 0, iclass 31, count 2 2006.257.18:17:19.26#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.18:17:19.26#ibcon#[25=AT03-08\r\n] 2006.257.18:17:19.26#ibcon#*before write, iclass 31, count 2 2006.257.18:17:19.26#ibcon#enter sib2, iclass 31, count 2 2006.257.18:17:19.26#ibcon#flushed, iclass 31, count 2 2006.257.18:17:19.26#ibcon#about to write, iclass 31, count 2 2006.257.18:17:19.26#ibcon#wrote, iclass 31, count 2 2006.257.18:17:19.26#ibcon#about to read 3, iclass 31, count 2 2006.257.18:17:19.29#ibcon#read 3, iclass 31, count 2 2006.257.18:17:19.29#ibcon#about to read 4, iclass 31, count 2 2006.257.18:17:19.29#ibcon#read 4, iclass 31, count 2 2006.257.18:17:19.29#ibcon#about to read 5, iclass 31, count 2 2006.257.18:17:19.29#ibcon#read 5, iclass 31, count 2 2006.257.18:17:19.29#ibcon#about to read 6, iclass 31, count 2 2006.257.18:17:19.29#ibcon#read 6, iclass 31, count 2 2006.257.18:17:19.29#ibcon#end of sib2, iclass 31, count 2 2006.257.18:17:19.29#ibcon#*after write, iclass 31, count 2 2006.257.18:17:19.29#ibcon#*before return 0, iclass 31, count 2 2006.257.18:17:19.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:19.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:19.29#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.18:17:19.29#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:19.29#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:19.41#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:19.41#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:19.41#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:17:19.41#ibcon#first serial, iclass 31, count 0 2006.257.18:17:19.41#ibcon#enter sib2, iclass 31, count 0 2006.257.18:17:19.41#ibcon#flushed, iclass 31, count 0 2006.257.18:17:19.41#ibcon#about to write, iclass 31, count 0 2006.257.18:17:19.41#ibcon#wrote, iclass 31, count 0 2006.257.18:17:19.41#ibcon#about to read 3, iclass 31, count 0 2006.257.18:17:19.43#ibcon#read 3, iclass 31, count 0 2006.257.18:17:19.43#ibcon#about to read 4, iclass 31, count 0 2006.257.18:17:19.43#ibcon#read 4, iclass 31, count 0 2006.257.18:17:19.43#ibcon#about to read 5, iclass 31, count 0 2006.257.18:17:19.43#ibcon#read 5, iclass 31, count 0 2006.257.18:17:19.43#ibcon#about to read 6, iclass 31, count 0 2006.257.18:17:19.43#ibcon#read 6, iclass 31, count 0 2006.257.18:17:19.43#ibcon#end of sib2, iclass 31, count 0 2006.257.18:17:19.43#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:17:19.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:17:19.43#ibcon#[25=USB\r\n] 2006.257.18:17:19.43#ibcon#*before write, iclass 31, count 0 2006.257.18:17:19.43#ibcon#enter sib2, iclass 31, count 0 2006.257.18:17:19.43#ibcon#flushed, iclass 31, count 0 2006.257.18:17:19.43#ibcon#about to write, iclass 31, count 0 2006.257.18:17:19.43#ibcon#wrote, iclass 31, count 0 2006.257.18:17:19.43#ibcon#about to read 3, iclass 31, count 0 2006.257.18:17:19.46#ibcon#read 3, iclass 31, count 0 2006.257.18:17:19.46#ibcon#about to read 4, iclass 31, count 0 2006.257.18:17:19.46#ibcon#read 4, iclass 31, count 0 2006.257.18:17:19.46#ibcon#about to read 5, iclass 31, count 0 2006.257.18:17:19.46#ibcon#read 5, iclass 31, count 0 2006.257.18:17:19.46#ibcon#about to read 6, iclass 31, count 0 2006.257.18:17:19.46#ibcon#read 6, iclass 31, count 0 2006.257.18:17:19.46#ibcon#end of sib2, iclass 31, count 0 2006.257.18:17:19.46#ibcon#*after write, iclass 31, count 0 2006.257.18:17:19.46#ibcon#*before return 0, iclass 31, count 0 2006.257.18:17:19.46#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:19.46#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:19.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:17:19.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:17:19.46$vck44/valo=4,624.99 2006.257.18:17:19.46#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.18:17:19.46#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.18:17:19.46#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:19.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:19.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:19.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:19.46#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:17:19.46#ibcon#first serial, iclass 33, count 0 2006.257.18:17:19.46#ibcon#enter sib2, iclass 33, count 0 2006.257.18:17:19.46#ibcon#flushed, iclass 33, count 0 2006.257.18:17:19.46#ibcon#about to write, iclass 33, count 0 2006.257.18:17:19.46#ibcon#wrote, iclass 33, count 0 2006.257.18:17:19.46#ibcon#about to read 3, iclass 33, count 0 2006.257.18:17:19.48#ibcon#read 3, iclass 33, count 0 2006.257.18:17:19.48#ibcon#about to read 4, iclass 33, count 0 2006.257.18:17:19.48#ibcon#read 4, iclass 33, count 0 2006.257.18:17:19.48#ibcon#about to read 5, iclass 33, count 0 2006.257.18:17:19.48#ibcon#read 5, iclass 33, count 0 2006.257.18:17:19.48#ibcon#about to read 6, iclass 33, count 0 2006.257.18:17:19.48#ibcon#read 6, iclass 33, count 0 2006.257.18:17:19.48#ibcon#end of sib2, iclass 33, count 0 2006.257.18:17:19.48#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:17:19.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:17:19.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:17:19.48#ibcon#*before write, iclass 33, count 0 2006.257.18:17:19.48#ibcon#enter sib2, iclass 33, count 0 2006.257.18:17:19.48#ibcon#flushed, iclass 33, count 0 2006.257.18:17:19.48#ibcon#about to write, iclass 33, count 0 2006.257.18:17:19.48#ibcon#wrote, iclass 33, count 0 2006.257.18:17:19.48#ibcon#about to read 3, iclass 33, count 0 2006.257.18:17:19.52#ibcon#read 3, iclass 33, count 0 2006.257.18:17:19.52#ibcon#about to read 4, iclass 33, count 0 2006.257.18:17:19.52#ibcon#read 4, iclass 33, count 0 2006.257.18:17:19.52#ibcon#about to read 5, iclass 33, count 0 2006.257.18:17:19.52#ibcon#read 5, iclass 33, count 0 2006.257.18:17:19.52#ibcon#about to read 6, iclass 33, count 0 2006.257.18:17:19.52#ibcon#read 6, iclass 33, count 0 2006.257.18:17:19.52#ibcon#end of sib2, iclass 33, count 0 2006.257.18:17:19.52#ibcon#*after write, iclass 33, count 0 2006.257.18:17:19.52#ibcon#*before return 0, iclass 33, count 0 2006.257.18:17:19.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:19.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:19.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:17:19.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:17:19.52$vck44/va=4,7 2006.257.18:17:19.52#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.18:17:19.52#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.18:17:19.52#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:19.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:19.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:19.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:19.58#ibcon#enter wrdev, iclass 35, count 2 2006.257.18:17:19.58#ibcon#first serial, iclass 35, count 2 2006.257.18:17:19.58#ibcon#enter sib2, iclass 35, count 2 2006.257.18:17:19.58#ibcon#flushed, iclass 35, count 2 2006.257.18:17:19.58#ibcon#about to write, iclass 35, count 2 2006.257.18:17:19.58#ibcon#wrote, iclass 35, count 2 2006.257.18:17:19.58#ibcon#about to read 3, iclass 35, count 2 2006.257.18:17:19.60#ibcon#read 3, iclass 35, count 2 2006.257.18:17:19.60#ibcon#about to read 4, iclass 35, count 2 2006.257.18:17:19.60#ibcon#read 4, iclass 35, count 2 2006.257.18:17:19.60#ibcon#about to read 5, iclass 35, count 2 2006.257.18:17:19.60#ibcon#read 5, iclass 35, count 2 2006.257.18:17:19.60#ibcon#about to read 6, iclass 35, count 2 2006.257.18:17:19.60#ibcon#read 6, iclass 35, count 2 2006.257.18:17:19.60#ibcon#end of sib2, iclass 35, count 2 2006.257.18:17:19.60#ibcon#*mode == 0, iclass 35, count 2 2006.257.18:17:19.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.18:17:19.60#ibcon#[25=AT04-07\r\n] 2006.257.18:17:19.60#ibcon#*before write, iclass 35, count 2 2006.257.18:17:19.60#ibcon#enter sib2, iclass 35, count 2 2006.257.18:17:19.60#ibcon#flushed, iclass 35, count 2 2006.257.18:17:19.60#ibcon#about to write, iclass 35, count 2 2006.257.18:17:19.60#ibcon#wrote, iclass 35, count 2 2006.257.18:17:19.60#ibcon#about to read 3, iclass 35, count 2 2006.257.18:17:19.63#ibcon#read 3, iclass 35, count 2 2006.257.18:17:19.63#ibcon#about to read 4, iclass 35, count 2 2006.257.18:17:19.63#ibcon#read 4, iclass 35, count 2 2006.257.18:17:19.63#ibcon#about to read 5, iclass 35, count 2 2006.257.18:17:19.63#ibcon#read 5, iclass 35, count 2 2006.257.18:17:19.63#ibcon#about to read 6, iclass 35, count 2 2006.257.18:17:19.63#ibcon#read 6, iclass 35, count 2 2006.257.18:17:19.63#ibcon#end of sib2, iclass 35, count 2 2006.257.18:17:19.63#ibcon#*after write, iclass 35, count 2 2006.257.18:17:19.63#ibcon#*before return 0, iclass 35, count 2 2006.257.18:17:19.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:19.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:19.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.18:17:19.63#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:19.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:19.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:19.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:19.75#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:17:19.75#ibcon#first serial, iclass 35, count 0 2006.257.18:17:19.75#ibcon#enter sib2, iclass 35, count 0 2006.257.18:17:19.75#ibcon#flushed, iclass 35, count 0 2006.257.18:17:19.75#ibcon#about to write, iclass 35, count 0 2006.257.18:17:19.75#ibcon#wrote, iclass 35, count 0 2006.257.18:17:19.75#ibcon#about to read 3, iclass 35, count 0 2006.257.18:17:19.77#ibcon#read 3, iclass 35, count 0 2006.257.18:17:19.77#ibcon#about to read 4, iclass 35, count 0 2006.257.18:17:19.77#ibcon#read 4, iclass 35, count 0 2006.257.18:17:19.77#ibcon#about to read 5, iclass 35, count 0 2006.257.18:17:19.77#ibcon#read 5, iclass 35, count 0 2006.257.18:17:19.77#ibcon#about to read 6, iclass 35, count 0 2006.257.18:17:19.77#ibcon#read 6, iclass 35, count 0 2006.257.18:17:19.77#ibcon#end of sib2, iclass 35, count 0 2006.257.18:17:19.77#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:17:19.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:17:19.77#ibcon#[25=USB\r\n] 2006.257.18:17:19.77#ibcon#*before write, iclass 35, count 0 2006.257.18:17:19.77#ibcon#enter sib2, iclass 35, count 0 2006.257.18:17:19.77#ibcon#flushed, iclass 35, count 0 2006.257.18:17:19.77#ibcon#about to write, iclass 35, count 0 2006.257.18:17:19.77#ibcon#wrote, iclass 35, count 0 2006.257.18:17:19.77#ibcon#about to read 3, iclass 35, count 0 2006.257.18:17:19.80#ibcon#read 3, iclass 35, count 0 2006.257.18:17:19.80#ibcon#about to read 4, iclass 35, count 0 2006.257.18:17:19.80#ibcon#read 4, iclass 35, count 0 2006.257.18:17:19.80#ibcon#about to read 5, iclass 35, count 0 2006.257.18:17:19.80#ibcon#read 5, iclass 35, count 0 2006.257.18:17:19.80#ibcon#about to read 6, iclass 35, count 0 2006.257.18:17:19.80#ibcon#read 6, iclass 35, count 0 2006.257.18:17:19.80#ibcon#end of sib2, iclass 35, count 0 2006.257.18:17:19.80#ibcon#*after write, iclass 35, count 0 2006.257.18:17:19.80#ibcon#*before return 0, iclass 35, count 0 2006.257.18:17:19.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:19.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:19.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:17:19.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:17:19.80$vck44/valo=5,734.99 2006.257.18:17:19.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.18:17:19.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.18:17:19.80#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:19.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:19.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:19.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:19.80#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:17:19.80#ibcon#first serial, iclass 37, count 0 2006.257.18:17:19.80#ibcon#enter sib2, iclass 37, count 0 2006.257.18:17:19.80#ibcon#flushed, iclass 37, count 0 2006.257.18:17:19.80#ibcon#about to write, iclass 37, count 0 2006.257.18:17:19.80#ibcon#wrote, iclass 37, count 0 2006.257.18:17:19.80#ibcon#about to read 3, iclass 37, count 0 2006.257.18:17:19.82#ibcon#read 3, iclass 37, count 0 2006.257.18:17:19.82#ibcon#about to read 4, iclass 37, count 0 2006.257.18:17:19.82#ibcon#read 4, iclass 37, count 0 2006.257.18:17:19.82#ibcon#about to read 5, iclass 37, count 0 2006.257.18:17:19.82#ibcon#read 5, iclass 37, count 0 2006.257.18:17:19.82#ibcon#about to read 6, iclass 37, count 0 2006.257.18:17:19.82#ibcon#read 6, iclass 37, count 0 2006.257.18:17:19.82#ibcon#end of sib2, iclass 37, count 0 2006.257.18:17:19.82#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:17:19.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:17:19.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:17:19.82#ibcon#*before write, iclass 37, count 0 2006.257.18:17:19.82#ibcon#enter sib2, iclass 37, count 0 2006.257.18:17:19.82#ibcon#flushed, iclass 37, count 0 2006.257.18:17:19.82#ibcon#about to write, iclass 37, count 0 2006.257.18:17:19.82#ibcon#wrote, iclass 37, count 0 2006.257.18:17:19.82#ibcon#about to read 3, iclass 37, count 0 2006.257.18:17:19.86#ibcon#read 3, iclass 37, count 0 2006.257.18:17:19.86#ibcon#about to read 4, iclass 37, count 0 2006.257.18:17:19.86#ibcon#read 4, iclass 37, count 0 2006.257.18:17:19.86#ibcon#about to read 5, iclass 37, count 0 2006.257.18:17:19.86#ibcon#read 5, iclass 37, count 0 2006.257.18:17:19.86#ibcon#about to read 6, iclass 37, count 0 2006.257.18:17:19.86#ibcon#read 6, iclass 37, count 0 2006.257.18:17:19.86#ibcon#end of sib2, iclass 37, count 0 2006.257.18:17:19.86#ibcon#*after write, iclass 37, count 0 2006.257.18:17:19.86#ibcon#*before return 0, iclass 37, count 0 2006.257.18:17:19.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:19.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:19.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:17:19.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:17:19.86$vck44/va=5,4 2006.257.18:17:19.86#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.18:17:19.86#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.18:17:19.86#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:19.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:19.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:19.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:19.92#ibcon#enter wrdev, iclass 39, count 2 2006.257.18:17:19.92#ibcon#first serial, iclass 39, count 2 2006.257.18:17:19.92#ibcon#enter sib2, iclass 39, count 2 2006.257.18:17:19.92#ibcon#flushed, iclass 39, count 2 2006.257.18:17:19.92#ibcon#about to write, iclass 39, count 2 2006.257.18:17:19.92#ibcon#wrote, iclass 39, count 2 2006.257.18:17:19.92#ibcon#about to read 3, iclass 39, count 2 2006.257.18:17:19.94#ibcon#read 3, iclass 39, count 2 2006.257.18:17:19.94#ibcon#about to read 4, iclass 39, count 2 2006.257.18:17:19.94#ibcon#read 4, iclass 39, count 2 2006.257.18:17:19.94#ibcon#about to read 5, iclass 39, count 2 2006.257.18:17:19.94#ibcon#read 5, iclass 39, count 2 2006.257.18:17:19.94#ibcon#about to read 6, iclass 39, count 2 2006.257.18:17:19.94#ibcon#read 6, iclass 39, count 2 2006.257.18:17:19.94#ibcon#end of sib2, iclass 39, count 2 2006.257.18:17:19.94#ibcon#*mode == 0, iclass 39, count 2 2006.257.18:17:19.94#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.18:17:19.94#ibcon#[25=AT05-04\r\n] 2006.257.18:17:19.94#ibcon#*before write, iclass 39, count 2 2006.257.18:17:19.94#ibcon#enter sib2, iclass 39, count 2 2006.257.18:17:19.94#ibcon#flushed, iclass 39, count 2 2006.257.18:17:19.94#ibcon#about to write, iclass 39, count 2 2006.257.18:17:19.94#ibcon#wrote, iclass 39, count 2 2006.257.18:17:19.94#ibcon#about to read 3, iclass 39, count 2 2006.257.18:17:19.97#ibcon#read 3, iclass 39, count 2 2006.257.18:17:19.97#ibcon#about to read 4, iclass 39, count 2 2006.257.18:17:19.97#ibcon#read 4, iclass 39, count 2 2006.257.18:17:19.97#ibcon#about to read 5, iclass 39, count 2 2006.257.18:17:19.97#ibcon#read 5, iclass 39, count 2 2006.257.18:17:19.97#ibcon#about to read 6, iclass 39, count 2 2006.257.18:17:19.97#ibcon#read 6, iclass 39, count 2 2006.257.18:17:19.97#ibcon#end of sib2, iclass 39, count 2 2006.257.18:17:19.97#ibcon#*after write, iclass 39, count 2 2006.257.18:17:19.97#ibcon#*before return 0, iclass 39, count 2 2006.257.18:17:19.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:19.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:19.97#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.18:17:19.97#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:19.97#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:20.09#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:20.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:20.09#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:17:20.09#ibcon#first serial, iclass 39, count 0 2006.257.18:17:20.09#ibcon#enter sib2, iclass 39, count 0 2006.257.18:17:20.09#ibcon#flushed, iclass 39, count 0 2006.257.18:17:20.09#ibcon#about to write, iclass 39, count 0 2006.257.18:17:20.09#ibcon#wrote, iclass 39, count 0 2006.257.18:17:20.09#ibcon#about to read 3, iclass 39, count 0 2006.257.18:17:20.11#ibcon#read 3, iclass 39, count 0 2006.257.18:17:20.11#ibcon#about to read 4, iclass 39, count 0 2006.257.18:17:20.11#ibcon#read 4, iclass 39, count 0 2006.257.18:17:20.11#ibcon#about to read 5, iclass 39, count 0 2006.257.18:17:20.11#ibcon#read 5, iclass 39, count 0 2006.257.18:17:20.11#ibcon#about to read 6, iclass 39, count 0 2006.257.18:17:20.11#ibcon#read 6, iclass 39, count 0 2006.257.18:17:20.11#ibcon#end of sib2, iclass 39, count 0 2006.257.18:17:20.11#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:17:20.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:17:20.11#ibcon#[25=USB\r\n] 2006.257.18:17:20.11#ibcon#*before write, iclass 39, count 0 2006.257.18:17:20.11#ibcon#enter sib2, iclass 39, count 0 2006.257.18:17:20.11#ibcon#flushed, iclass 39, count 0 2006.257.18:17:20.11#ibcon#about to write, iclass 39, count 0 2006.257.18:17:20.11#ibcon#wrote, iclass 39, count 0 2006.257.18:17:20.11#ibcon#about to read 3, iclass 39, count 0 2006.257.18:17:20.14#ibcon#read 3, iclass 39, count 0 2006.257.18:17:20.14#ibcon#about to read 4, iclass 39, count 0 2006.257.18:17:20.14#ibcon#read 4, iclass 39, count 0 2006.257.18:17:20.14#ibcon#about to read 5, iclass 39, count 0 2006.257.18:17:20.14#ibcon#read 5, iclass 39, count 0 2006.257.18:17:20.14#ibcon#about to read 6, iclass 39, count 0 2006.257.18:17:20.14#ibcon#read 6, iclass 39, count 0 2006.257.18:17:20.14#ibcon#end of sib2, iclass 39, count 0 2006.257.18:17:20.14#ibcon#*after write, iclass 39, count 0 2006.257.18:17:20.14#ibcon#*before return 0, iclass 39, count 0 2006.257.18:17:20.14#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:20.14#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:20.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:17:20.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:17:20.14$vck44/valo=6,814.99 2006.257.18:17:20.14#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.18:17:20.14#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.18:17:20.14#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:20.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:20.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:20.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:20.14#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:17:20.14#ibcon#first serial, iclass 3, count 0 2006.257.18:17:20.14#ibcon#enter sib2, iclass 3, count 0 2006.257.18:17:20.14#ibcon#flushed, iclass 3, count 0 2006.257.18:17:20.14#ibcon#about to write, iclass 3, count 0 2006.257.18:17:20.14#ibcon#wrote, iclass 3, count 0 2006.257.18:17:20.14#ibcon#about to read 3, iclass 3, count 0 2006.257.18:17:20.16#ibcon#read 3, iclass 3, count 0 2006.257.18:17:20.16#ibcon#about to read 4, iclass 3, count 0 2006.257.18:17:20.16#ibcon#read 4, iclass 3, count 0 2006.257.18:17:20.16#ibcon#about to read 5, iclass 3, count 0 2006.257.18:17:20.16#ibcon#read 5, iclass 3, count 0 2006.257.18:17:20.16#ibcon#about to read 6, iclass 3, count 0 2006.257.18:17:20.16#ibcon#read 6, iclass 3, count 0 2006.257.18:17:20.16#ibcon#end of sib2, iclass 3, count 0 2006.257.18:17:20.16#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:17:20.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:17:20.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:17:20.16#ibcon#*before write, iclass 3, count 0 2006.257.18:17:20.16#ibcon#enter sib2, iclass 3, count 0 2006.257.18:17:20.16#ibcon#flushed, iclass 3, count 0 2006.257.18:17:20.16#ibcon#about to write, iclass 3, count 0 2006.257.18:17:20.16#ibcon#wrote, iclass 3, count 0 2006.257.18:17:20.16#ibcon#about to read 3, iclass 3, count 0 2006.257.18:17:20.20#ibcon#read 3, iclass 3, count 0 2006.257.18:17:20.20#ibcon#about to read 4, iclass 3, count 0 2006.257.18:17:20.20#ibcon#read 4, iclass 3, count 0 2006.257.18:17:20.20#ibcon#about to read 5, iclass 3, count 0 2006.257.18:17:20.20#ibcon#read 5, iclass 3, count 0 2006.257.18:17:20.20#ibcon#about to read 6, iclass 3, count 0 2006.257.18:17:20.20#ibcon#read 6, iclass 3, count 0 2006.257.18:17:20.20#ibcon#end of sib2, iclass 3, count 0 2006.257.18:17:20.20#ibcon#*after write, iclass 3, count 0 2006.257.18:17:20.20#ibcon#*before return 0, iclass 3, count 0 2006.257.18:17:20.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:20.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:20.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:17:20.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:17:20.20$vck44/va=6,4 2006.257.18:17:20.20#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.18:17:20.20#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.18:17:20.20#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:20.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:20.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:20.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:20.26#ibcon#enter wrdev, iclass 5, count 2 2006.257.18:17:20.26#ibcon#first serial, iclass 5, count 2 2006.257.18:17:20.26#ibcon#enter sib2, iclass 5, count 2 2006.257.18:17:20.26#ibcon#flushed, iclass 5, count 2 2006.257.18:17:20.26#ibcon#about to write, iclass 5, count 2 2006.257.18:17:20.26#ibcon#wrote, iclass 5, count 2 2006.257.18:17:20.26#ibcon#about to read 3, iclass 5, count 2 2006.257.18:17:20.28#ibcon#read 3, iclass 5, count 2 2006.257.18:17:20.28#ibcon#about to read 4, iclass 5, count 2 2006.257.18:17:20.28#ibcon#read 4, iclass 5, count 2 2006.257.18:17:20.28#ibcon#about to read 5, iclass 5, count 2 2006.257.18:17:20.28#ibcon#read 5, iclass 5, count 2 2006.257.18:17:20.28#ibcon#about to read 6, iclass 5, count 2 2006.257.18:17:20.28#ibcon#read 6, iclass 5, count 2 2006.257.18:17:20.28#ibcon#end of sib2, iclass 5, count 2 2006.257.18:17:20.28#ibcon#*mode == 0, iclass 5, count 2 2006.257.18:17:20.28#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.18:17:20.28#ibcon#[25=AT06-04\r\n] 2006.257.18:17:20.28#ibcon#*before write, iclass 5, count 2 2006.257.18:17:20.28#ibcon#enter sib2, iclass 5, count 2 2006.257.18:17:20.28#ibcon#flushed, iclass 5, count 2 2006.257.18:17:20.28#ibcon#about to write, iclass 5, count 2 2006.257.18:17:20.28#ibcon#wrote, iclass 5, count 2 2006.257.18:17:20.28#ibcon#about to read 3, iclass 5, count 2 2006.257.18:17:20.31#ibcon#read 3, iclass 5, count 2 2006.257.18:17:20.31#ibcon#about to read 4, iclass 5, count 2 2006.257.18:17:20.31#ibcon#read 4, iclass 5, count 2 2006.257.18:17:20.31#ibcon#about to read 5, iclass 5, count 2 2006.257.18:17:20.31#ibcon#read 5, iclass 5, count 2 2006.257.18:17:20.31#ibcon#about to read 6, iclass 5, count 2 2006.257.18:17:20.31#ibcon#read 6, iclass 5, count 2 2006.257.18:17:20.31#ibcon#end of sib2, iclass 5, count 2 2006.257.18:17:20.31#ibcon#*after write, iclass 5, count 2 2006.257.18:17:20.31#ibcon#*before return 0, iclass 5, count 2 2006.257.18:17:20.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:20.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:20.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.18:17:20.31#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:20.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:20.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:20.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:20.43#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:17:20.43#ibcon#first serial, iclass 5, count 0 2006.257.18:17:20.43#ibcon#enter sib2, iclass 5, count 0 2006.257.18:17:20.43#ibcon#flushed, iclass 5, count 0 2006.257.18:17:20.43#ibcon#about to write, iclass 5, count 0 2006.257.18:17:20.43#ibcon#wrote, iclass 5, count 0 2006.257.18:17:20.43#ibcon#about to read 3, iclass 5, count 0 2006.257.18:17:20.45#ibcon#read 3, iclass 5, count 0 2006.257.18:17:20.45#ibcon#about to read 4, iclass 5, count 0 2006.257.18:17:20.45#ibcon#read 4, iclass 5, count 0 2006.257.18:17:20.45#ibcon#about to read 5, iclass 5, count 0 2006.257.18:17:20.45#ibcon#read 5, iclass 5, count 0 2006.257.18:17:20.45#ibcon#about to read 6, iclass 5, count 0 2006.257.18:17:20.45#ibcon#read 6, iclass 5, count 0 2006.257.18:17:20.45#ibcon#end of sib2, iclass 5, count 0 2006.257.18:17:20.45#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:17:20.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:17:20.45#ibcon#[25=USB\r\n] 2006.257.18:17:20.45#ibcon#*before write, iclass 5, count 0 2006.257.18:17:20.45#ibcon#enter sib2, iclass 5, count 0 2006.257.18:17:20.45#ibcon#flushed, iclass 5, count 0 2006.257.18:17:20.45#ibcon#about to write, iclass 5, count 0 2006.257.18:17:20.45#ibcon#wrote, iclass 5, count 0 2006.257.18:17:20.45#ibcon#about to read 3, iclass 5, count 0 2006.257.18:17:20.48#ibcon#read 3, iclass 5, count 0 2006.257.18:17:20.48#ibcon#about to read 4, iclass 5, count 0 2006.257.18:17:20.48#ibcon#read 4, iclass 5, count 0 2006.257.18:17:20.48#ibcon#about to read 5, iclass 5, count 0 2006.257.18:17:20.48#ibcon#read 5, iclass 5, count 0 2006.257.18:17:20.48#ibcon#about to read 6, iclass 5, count 0 2006.257.18:17:20.48#ibcon#read 6, iclass 5, count 0 2006.257.18:17:20.48#ibcon#end of sib2, iclass 5, count 0 2006.257.18:17:20.48#ibcon#*after write, iclass 5, count 0 2006.257.18:17:20.48#ibcon#*before return 0, iclass 5, count 0 2006.257.18:17:20.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:20.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:20.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:17:20.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:17:20.48$vck44/valo=7,864.99 2006.257.18:17:20.48#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.18:17:20.48#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.18:17:20.48#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:20.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:20.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:20.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:20.48#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:17:20.48#ibcon#first serial, iclass 7, count 0 2006.257.18:17:20.48#ibcon#enter sib2, iclass 7, count 0 2006.257.18:17:20.48#ibcon#flushed, iclass 7, count 0 2006.257.18:17:20.48#ibcon#about to write, iclass 7, count 0 2006.257.18:17:20.48#ibcon#wrote, iclass 7, count 0 2006.257.18:17:20.48#ibcon#about to read 3, iclass 7, count 0 2006.257.18:17:20.50#ibcon#read 3, iclass 7, count 0 2006.257.18:17:20.50#ibcon#about to read 4, iclass 7, count 0 2006.257.18:17:20.50#ibcon#read 4, iclass 7, count 0 2006.257.18:17:20.50#ibcon#about to read 5, iclass 7, count 0 2006.257.18:17:20.50#ibcon#read 5, iclass 7, count 0 2006.257.18:17:20.50#ibcon#about to read 6, iclass 7, count 0 2006.257.18:17:20.50#ibcon#read 6, iclass 7, count 0 2006.257.18:17:20.50#ibcon#end of sib2, iclass 7, count 0 2006.257.18:17:20.50#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:17:20.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:17:20.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:17:20.50#ibcon#*before write, iclass 7, count 0 2006.257.18:17:20.50#ibcon#enter sib2, iclass 7, count 0 2006.257.18:17:20.50#ibcon#flushed, iclass 7, count 0 2006.257.18:17:20.50#ibcon#about to write, iclass 7, count 0 2006.257.18:17:20.50#ibcon#wrote, iclass 7, count 0 2006.257.18:17:20.50#ibcon#about to read 3, iclass 7, count 0 2006.257.18:17:20.54#ibcon#read 3, iclass 7, count 0 2006.257.18:17:20.54#ibcon#about to read 4, iclass 7, count 0 2006.257.18:17:20.54#ibcon#read 4, iclass 7, count 0 2006.257.18:17:20.54#ibcon#about to read 5, iclass 7, count 0 2006.257.18:17:20.54#ibcon#read 5, iclass 7, count 0 2006.257.18:17:20.54#ibcon#about to read 6, iclass 7, count 0 2006.257.18:17:20.54#ibcon#read 6, iclass 7, count 0 2006.257.18:17:20.54#ibcon#end of sib2, iclass 7, count 0 2006.257.18:17:20.54#ibcon#*after write, iclass 7, count 0 2006.257.18:17:20.54#ibcon#*before return 0, iclass 7, count 0 2006.257.18:17:20.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:20.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:20.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:17:20.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:17:20.54$vck44/va=7,4 2006.257.18:17:20.54#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.18:17:20.54#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.18:17:20.54#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:20.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:20.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:20.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:20.60#ibcon#enter wrdev, iclass 11, count 2 2006.257.18:17:20.60#ibcon#first serial, iclass 11, count 2 2006.257.18:17:20.60#ibcon#enter sib2, iclass 11, count 2 2006.257.18:17:20.60#ibcon#flushed, iclass 11, count 2 2006.257.18:17:20.60#ibcon#about to write, iclass 11, count 2 2006.257.18:17:20.60#ibcon#wrote, iclass 11, count 2 2006.257.18:17:20.60#ibcon#about to read 3, iclass 11, count 2 2006.257.18:17:20.62#ibcon#read 3, iclass 11, count 2 2006.257.18:17:20.62#ibcon#about to read 4, iclass 11, count 2 2006.257.18:17:20.62#ibcon#read 4, iclass 11, count 2 2006.257.18:17:20.62#ibcon#about to read 5, iclass 11, count 2 2006.257.18:17:20.62#ibcon#read 5, iclass 11, count 2 2006.257.18:17:20.62#ibcon#about to read 6, iclass 11, count 2 2006.257.18:17:20.62#ibcon#read 6, iclass 11, count 2 2006.257.18:17:20.62#ibcon#end of sib2, iclass 11, count 2 2006.257.18:17:20.62#ibcon#*mode == 0, iclass 11, count 2 2006.257.18:17:20.62#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.18:17:20.62#ibcon#[25=AT07-04\r\n] 2006.257.18:17:20.62#ibcon#*before write, iclass 11, count 2 2006.257.18:17:20.62#ibcon#enter sib2, iclass 11, count 2 2006.257.18:17:20.62#ibcon#flushed, iclass 11, count 2 2006.257.18:17:20.62#ibcon#about to write, iclass 11, count 2 2006.257.18:17:20.62#ibcon#wrote, iclass 11, count 2 2006.257.18:17:20.62#ibcon#about to read 3, iclass 11, count 2 2006.257.18:17:20.65#ibcon#read 3, iclass 11, count 2 2006.257.18:17:20.65#ibcon#about to read 4, iclass 11, count 2 2006.257.18:17:20.65#ibcon#read 4, iclass 11, count 2 2006.257.18:17:20.65#ibcon#about to read 5, iclass 11, count 2 2006.257.18:17:20.65#ibcon#read 5, iclass 11, count 2 2006.257.18:17:20.65#ibcon#about to read 6, iclass 11, count 2 2006.257.18:17:20.65#ibcon#read 6, iclass 11, count 2 2006.257.18:17:20.65#ibcon#end of sib2, iclass 11, count 2 2006.257.18:17:20.65#ibcon#*after write, iclass 11, count 2 2006.257.18:17:20.65#ibcon#*before return 0, iclass 11, count 2 2006.257.18:17:20.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:20.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:20.65#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.18:17:20.65#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:20.65#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:20.77#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:20.77#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:20.77#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:17:20.77#ibcon#first serial, iclass 11, count 0 2006.257.18:17:20.77#ibcon#enter sib2, iclass 11, count 0 2006.257.18:17:20.77#ibcon#flushed, iclass 11, count 0 2006.257.18:17:20.77#ibcon#about to write, iclass 11, count 0 2006.257.18:17:20.77#ibcon#wrote, iclass 11, count 0 2006.257.18:17:20.77#ibcon#about to read 3, iclass 11, count 0 2006.257.18:17:20.79#ibcon#read 3, iclass 11, count 0 2006.257.18:17:20.79#ibcon#about to read 4, iclass 11, count 0 2006.257.18:17:20.79#ibcon#read 4, iclass 11, count 0 2006.257.18:17:20.79#ibcon#about to read 5, iclass 11, count 0 2006.257.18:17:20.79#ibcon#read 5, iclass 11, count 0 2006.257.18:17:20.79#ibcon#about to read 6, iclass 11, count 0 2006.257.18:17:20.79#ibcon#read 6, iclass 11, count 0 2006.257.18:17:20.79#ibcon#end of sib2, iclass 11, count 0 2006.257.18:17:20.79#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:17:20.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:17:20.79#ibcon#[25=USB\r\n] 2006.257.18:17:20.79#ibcon#*before write, iclass 11, count 0 2006.257.18:17:20.79#ibcon#enter sib2, iclass 11, count 0 2006.257.18:17:20.79#ibcon#flushed, iclass 11, count 0 2006.257.18:17:20.79#ibcon#about to write, iclass 11, count 0 2006.257.18:17:20.79#ibcon#wrote, iclass 11, count 0 2006.257.18:17:20.79#ibcon#about to read 3, iclass 11, count 0 2006.257.18:17:20.82#ibcon#read 3, iclass 11, count 0 2006.257.18:17:20.82#ibcon#about to read 4, iclass 11, count 0 2006.257.18:17:20.82#ibcon#read 4, iclass 11, count 0 2006.257.18:17:20.82#ibcon#about to read 5, iclass 11, count 0 2006.257.18:17:20.82#ibcon#read 5, iclass 11, count 0 2006.257.18:17:20.82#ibcon#about to read 6, iclass 11, count 0 2006.257.18:17:20.82#ibcon#read 6, iclass 11, count 0 2006.257.18:17:20.82#ibcon#end of sib2, iclass 11, count 0 2006.257.18:17:20.82#ibcon#*after write, iclass 11, count 0 2006.257.18:17:20.82#ibcon#*before return 0, iclass 11, count 0 2006.257.18:17:20.82#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:20.82#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:20.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:17:20.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:17:20.82$vck44/valo=8,884.99 2006.257.18:17:20.82#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.18:17:20.82#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.18:17:20.82#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:20.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:20.82#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:20.82#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:20.82#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:17:20.82#ibcon#first serial, iclass 13, count 0 2006.257.18:17:20.82#ibcon#enter sib2, iclass 13, count 0 2006.257.18:17:20.82#ibcon#flushed, iclass 13, count 0 2006.257.18:17:20.82#ibcon#about to write, iclass 13, count 0 2006.257.18:17:20.82#ibcon#wrote, iclass 13, count 0 2006.257.18:17:20.82#ibcon#about to read 3, iclass 13, count 0 2006.257.18:17:20.84#ibcon#read 3, iclass 13, count 0 2006.257.18:17:20.84#ibcon#about to read 4, iclass 13, count 0 2006.257.18:17:20.84#ibcon#read 4, iclass 13, count 0 2006.257.18:17:20.84#ibcon#about to read 5, iclass 13, count 0 2006.257.18:17:20.84#ibcon#read 5, iclass 13, count 0 2006.257.18:17:20.84#ibcon#about to read 6, iclass 13, count 0 2006.257.18:17:20.84#ibcon#read 6, iclass 13, count 0 2006.257.18:17:20.84#ibcon#end of sib2, iclass 13, count 0 2006.257.18:17:20.84#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:17:20.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:17:20.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:17:20.84#ibcon#*before write, iclass 13, count 0 2006.257.18:17:20.84#ibcon#enter sib2, iclass 13, count 0 2006.257.18:17:20.84#ibcon#flushed, iclass 13, count 0 2006.257.18:17:20.84#ibcon#about to write, iclass 13, count 0 2006.257.18:17:20.84#ibcon#wrote, iclass 13, count 0 2006.257.18:17:20.84#ibcon#about to read 3, iclass 13, count 0 2006.257.18:17:20.88#ibcon#read 3, iclass 13, count 0 2006.257.18:17:20.88#ibcon#about to read 4, iclass 13, count 0 2006.257.18:17:20.88#ibcon#read 4, iclass 13, count 0 2006.257.18:17:20.88#ibcon#about to read 5, iclass 13, count 0 2006.257.18:17:20.88#ibcon#read 5, iclass 13, count 0 2006.257.18:17:20.88#ibcon#about to read 6, iclass 13, count 0 2006.257.18:17:20.88#ibcon#read 6, iclass 13, count 0 2006.257.18:17:20.88#ibcon#end of sib2, iclass 13, count 0 2006.257.18:17:20.88#ibcon#*after write, iclass 13, count 0 2006.257.18:17:20.88#ibcon#*before return 0, iclass 13, count 0 2006.257.18:17:20.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:20.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:20.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:17:20.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:17:20.88$vck44/va=8,4 2006.257.18:17:20.88#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.18:17:20.88#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.18:17:20.88#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:20.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:17:20.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:17:20.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:17:20.94#ibcon#enter wrdev, iclass 15, count 2 2006.257.18:17:20.94#ibcon#first serial, iclass 15, count 2 2006.257.18:17:20.94#ibcon#enter sib2, iclass 15, count 2 2006.257.18:17:20.94#ibcon#flushed, iclass 15, count 2 2006.257.18:17:20.94#ibcon#about to write, iclass 15, count 2 2006.257.18:17:20.94#ibcon#wrote, iclass 15, count 2 2006.257.18:17:20.94#ibcon#about to read 3, iclass 15, count 2 2006.257.18:17:20.96#ibcon#read 3, iclass 15, count 2 2006.257.18:17:20.96#ibcon#about to read 4, iclass 15, count 2 2006.257.18:17:20.96#ibcon#read 4, iclass 15, count 2 2006.257.18:17:20.96#ibcon#about to read 5, iclass 15, count 2 2006.257.18:17:20.96#ibcon#read 5, iclass 15, count 2 2006.257.18:17:20.96#ibcon#about to read 6, iclass 15, count 2 2006.257.18:17:20.96#ibcon#read 6, iclass 15, count 2 2006.257.18:17:20.96#ibcon#end of sib2, iclass 15, count 2 2006.257.18:17:20.96#ibcon#*mode == 0, iclass 15, count 2 2006.257.18:17:20.96#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.18:17:20.96#ibcon#[25=AT08-04\r\n] 2006.257.18:17:20.96#ibcon#*before write, iclass 15, count 2 2006.257.18:17:20.96#ibcon#enter sib2, iclass 15, count 2 2006.257.18:17:20.96#ibcon#flushed, iclass 15, count 2 2006.257.18:17:20.96#ibcon#about to write, iclass 15, count 2 2006.257.18:17:20.96#ibcon#wrote, iclass 15, count 2 2006.257.18:17:20.96#ibcon#about to read 3, iclass 15, count 2 2006.257.18:17:20.99#ibcon#read 3, iclass 15, count 2 2006.257.18:17:20.99#ibcon#about to read 4, iclass 15, count 2 2006.257.18:17:20.99#ibcon#read 4, iclass 15, count 2 2006.257.18:17:20.99#ibcon#about to read 5, iclass 15, count 2 2006.257.18:17:20.99#ibcon#read 5, iclass 15, count 2 2006.257.18:17:20.99#ibcon#about to read 6, iclass 15, count 2 2006.257.18:17:20.99#ibcon#read 6, iclass 15, count 2 2006.257.18:17:20.99#ibcon#end of sib2, iclass 15, count 2 2006.257.18:17:20.99#ibcon#*after write, iclass 15, count 2 2006.257.18:17:20.99#ibcon#*before return 0, iclass 15, count 2 2006.257.18:17:20.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:17:20.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:17:20.99#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.18:17:20.99#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:20.99#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:17:21.11#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:17:21.11#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:17:21.11#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:17:21.11#ibcon#first serial, iclass 15, count 0 2006.257.18:17:21.11#ibcon#enter sib2, iclass 15, count 0 2006.257.18:17:21.11#ibcon#flushed, iclass 15, count 0 2006.257.18:17:21.11#ibcon#about to write, iclass 15, count 0 2006.257.18:17:21.11#ibcon#wrote, iclass 15, count 0 2006.257.18:17:21.11#ibcon#about to read 3, iclass 15, count 0 2006.257.18:17:21.13#ibcon#read 3, iclass 15, count 0 2006.257.18:17:21.13#ibcon#about to read 4, iclass 15, count 0 2006.257.18:17:21.13#ibcon#read 4, iclass 15, count 0 2006.257.18:17:21.13#ibcon#about to read 5, iclass 15, count 0 2006.257.18:17:21.13#ibcon#read 5, iclass 15, count 0 2006.257.18:17:21.13#ibcon#about to read 6, iclass 15, count 0 2006.257.18:17:21.13#ibcon#read 6, iclass 15, count 0 2006.257.18:17:21.13#ibcon#end of sib2, iclass 15, count 0 2006.257.18:17:21.13#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:17:21.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:17:21.13#ibcon#[25=USB\r\n] 2006.257.18:17:21.13#ibcon#*before write, iclass 15, count 0 2006.257.18:17:21.13#ibcon#enter sib2, iclass 15, count 0 2006.257.18:17:21.13#ibcon#flushed, iclass 15, count 0 2006.257.18:17:21.13#ibcon#about to write, iclass 15, count 0 2006.257.18:17:21.13#ibcon#wrote, iclass 15, count 0 2006.257.18:17:21.13#ibcon#about to read 3, iclass 15, count 0 2006.257.18:17:21.16#ibcon#read 3, iclass 15, count 0 2006.257.18:17:21.16#ibcon#about to read 4, iclass 15, count 0 2006.257.18:17:21.16#ibcon#read 4, iclass 15, count 0 2006.257.18:17:21.16#ibcon#about to read 5, iclass 15, count 0 2006.257.18:17:21.16#ibcon#read 5, iclass 15, count 0 2006.257.18:17:21.16#ibcon#about to read 6, iclass 15, count 0 2006.257.18:17:21.16#ibcon#read 6, iclass 15, count 0 2006.257.18:17:21.16#ibcon#end of sib2, iclass 15, count 0 2006.257.18:17:21.16#ibcon#*after write, iclass 15, count 0 2006.257.18:17:21.16#ibcon#*before return 0, iclass 15, count 0 2006.257.18:17:21.16#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:17:21.16#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:17:21.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:17:21.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:17:21.16$vck44/vblo=1,629.99 2006.257.18:17:21.16#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.18:17:21.16#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.18:17:21.16#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:21.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:17:21.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:17:21.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:17:21.16#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:17:21.16#ibcon#first serial, iclass 17, count 0 2006.257.18:17:21.16#ibcon#enter sib2, iclass 17, count 0 2006.257.18:17:21.16#ibcon#flushed, iclass 17, count 0 2006.257.18:17:21.16#ibcon#about to write, iclass 17, count 0 2006.257.18:17:21.16#ibcon#wrote, iclass 17, count 0 2006.257.18:17:21.16#ibcon#about to read 3, iclass 17, count 0 2006.257.18:17:21.18#ibcon#read 3, iclass 17, count 0 2006.257.18:17:21.18#ibcon#about to read 4, iclass 17, count 0 2006.257.18:17:21.18#ibcon#read 4, iclass 17, count 0 2006.257.18:17:21.18#ibcon#about to read 5, iclass 17, count 0 2006.257.18:17:21.18#ibcon#read 5, iclass 17, count 0 2006.257.18:17:21.18#ibcon#about to read 6, iclass 17, count 0 2006.257.18:17:21.18#ibcon#read 6, iclass 17, count 0 2006.257.18:17:21.18#ibcon#end of sib2, iclass 17, count 0 2006.257.18:17:21.18#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:17:21.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:17:21.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:17:21.18#ibcon#*before write, iclass 17, count 0 2006.257.18:17:21.18#ibcon#enter sib2, iclass 17, count 0 2006.257.18:17:21.18#ibcon#flushed, iclass 17, count 0 2006.257.18:17:21.18#ibcon#about to write, iclass 17, count 0 2006.257.18:17:21.18#ibcon#wrote, iclass 17, count 0 2006.257.18:17:21.18#ibcon#about to read 3, iclass 17, count 0 2006.257.18:17:21.22#ibcon#read 3, iclass 17, count 0 2006.257.18:17:21.22#ibcon#about to read 4, iclass 17, count 0 2006.257.18:17:21.22#ibcon#read 4, iclass 17, count 0 2006.257.18:17:21.22#ibcon#about to read 5, iclass 17, count 0 2006.257.18:17:21.22#ibcon#read 5, iclass 17, count 0 2006.257.18:17:21.22#ibcon#about to read 6, iclass 17, count 0 2006.257.18:17:21.22#ibcon#read 6, iclass 17, count 0 2006.257.18:17:21.22#ibcon#end of sib2, iclass 17, count 0 2006.257.18:17:21.22#ibcon#*after write, iclass 17, count 0 2006.257.18:17:21.22#ibcon#*before return 0, iclass 17, count 0 2006.257.18:17:21.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:17:21.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:17:21.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:17:21.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:17:21.22$vck44/vb=1,4 2006.257.18:17:21.22#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.18:17:21.22#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.18:17:21.22#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:21.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:17:21.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:17:21.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:17:21.22#ibcon#enter wrdev, iclass 19, count 2 2006.257.18:17:21.22#ibcon#first serial, iclass 19, count 2 2006.257.18:17:21.22#ibcon#enter sib2, iclass 19, count 2 2006.257.18:17:21.22#ibcon#flushed, iclass 19, count 2 2006.257.18:17:21.22#ibcon#about to write, iclass 19, count 2 2006.257.18:17:21.22#ibcon#wrote, iclass 19, count 2 2006.257.18:17:21.22#ibcon#about to read 3, iclass 19, count 2 2006.257.18:17:21.24#ibcon#read 3, iclass 19, count 2 2006.257.18:17:21.24#ibcon#about to read 4, iclass 19, count 2 2006.257.18:17:21.24#ibcon#read 4, iclass 19, count 2 2006.257.18:17:21.24#ibcon#about to read 5, iclass 19, count 2 2006.257.18:17:21.24#ibcon#read 5, iclass 19, count 2 2006.257.18:17:21.24#ibcon#about to read 6, iclass 19, count 2 2006.257.18:17:21.24#ibcon#read 6, iclass 19, count 2 2006.257.18:17:21.24#ibcon#end of sib2, iclass 19, count 2 2006.257.18:17:21.24#ibcon#*mode == 0, iclass 19, count 2 2006.257.18:17:21.24#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.18:17:21.24#ibcon#[27=AT01-04\r\n] 2006.257.18:17:21.24#ibcon#*before write, iclass 19, count 2 2006.257.18:17:21.24#ibcon#enter sib2, iclass 19, count 2 2006.257.18:17:21.24#ibcon#flushed, iclass 19, count 2 2006.257.18:17:21.24#ibcon#about to write, iclass 19, count 2 2006.257.18:17:21.24#ibcon#wrote, iclass 19, count 2 2006.257.18:17:21.24#ibcon#about to read 3, iclass 19, count 2 2006.257.18:17:21.27#ibcon#read 3, iclass 19, count 2 2006.257.18:17:21.27#ibcon#about to read 4, iclass 19, count 2 2006.257.18:17:21.27#ibcon#read 4, iclass 19, count 2 2006.257.18:17:21.27#ibcon#about to read 5, iclass 19, count 2 2006.257.18:17:21.27#ibcon#read 5, iclass 19, count 2 2006.257.18:17:21.27#ibcon#about to read 6, iclass 19, count 2 2006.257.18:17:21.27#ibcon#read 6, iclass 19, count 2 2006.257.18:17:21.27#ibcon#end of sib2, iclass 19, count 2 2006.257.18:17:21.27#ibcon#*after write, iclass 19, count 2 2006.257.18:17:21.27#ibcon#*before return 0, iclass 19, count 2 2006.257.18:17:21.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:17:21.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:17:21.27#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.18:17:21.27#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:21.27#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:17:21.39#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:17:21.39#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:17:21.39#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:17:21.39#ibcon#first serial, iclass 19, count 0 2006.257.18:17:21.39#ibcon#enter sib2, iclass 19, count 0 2006.257.18:17:21.39#ibcon#flushed, iclass 19, count 0 2006.257.18:17:21.39#ibcon#about to write, iclass 19, count 0 2006.257.18:17:21.39#ibcon#wrote, iclass 19, count 0 2006.257.18:17:21.39#ibcon#about to read 3, iclass 19, count 0 2006.257.18:17:21.41#ibcon#read 3, iclass 19, count 0 2006.257.18:17:21.41#ibcon#about to read 4, iclass 19, count 0 2006.257.18:17:21.41#ibcon#read 4, iclass 19, count 0 2006.257.18:17:21.41#ibcon#about to read 5, iclass 19, count 0 2006.257.18:17:21.41#ibcon#read 5, iclass 19, count 0 2006.257.18:17:21.41#ibcon#about to read 6, iclass 19, count 0 2006.257.18:17:21.41#ibcon#read 6, iclass 19, count 0 2006.257.18:17:21.41#ibcon#end of sib2, iclass 19, count 0 2006.257.18:17:21.41#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:17:21.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:17:21.41#ibcon#[27=USB\r\n] 2006.257.18:17:21.41#ibcon#*before write, iclass 19, count 0 2006.257.18:17:21.41#ibcon#enter sib2, iclass 19, count 0 2006.257.18:17:21.41#ibcon#flushed, iclass 19, count 0 2006.257.18:17:21.41#ibcon#about to write, iclass 19, count 0 2006.257.18:17:21.41#ibcon#wrote, iclass 19, count 0 2006.257.18:17:21.41#ibcon#about to read 3, iclass 19, count 0 2006.257.18:17:21.44#ibcon#read 3, iclass 19, count 0 2006.257.18:17:21.44#ibcon#about to read 4, iclass 19, count 0 2006.257.18:17:21.44#ibcon#read 4, iclass 19, count 0 2006.257.18:17:21.44#ibcon#about to read 5, iclass 19, count 0 2006.257.18:17:21.44#ibcon#read 5, iclass 19, count 0 2006.257.18:17:21.44#ibcon#about to read 6, iclass 19, count 0 2006.257.18:17:21.44#ibcon#read 6, iclass 19, count 0 2006.257.18:17:21.44#ibcon#end of sib2, iclass 19, count 0 2006.257.18:17:21.44#ibcon#*after write, iclass 19, count 0 2006.257.18:17:21.44#ibcon#*before return 0, iclass 19, count 0 2006.257.18:17:21.44#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:17:21.44#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:17:21.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:17:21.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:17:21.44$vck44/vblo=2,634.99 2006.257.18:17:21.44#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.18:17:21.44#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.18:17:21.44#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:21.44#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:21.44#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:21.44#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:21.44#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:17:21.44#ibcon#first serial, iclass 21, count 0 2006.257.18:17:21.44#ibcon#enter sib2, iclass 21, count 0 2006.257.18:17:21.44#ibcon#flushed, iclass 21, count 0 2006.257.18:17:21.44#ibcon#about to write, iclass 21, count 0 2006.257.18:17:21.44#ibcon#wrote, iclass 21, count 0 2006.257.18:17:21.44#ibcon#about to read 3, iclass 21, count 0 2006.257.18:17:21.46#ibcon#read 3, iclass 21, count 0 2006.257.18:17:21.46#ibcon#about to read 4, iclass 21, count 0 2006.257.18:17:21.46#ibcon#read 4, iclass 21, count 0 2006.257.18:17:21.46#ibcon#about to read 5, iclass 21, count 0 2006.257.18:17:21.46#ibcon#read 5, iclass 21, count 0 2006.257.18:17:21.46#ibcon#about to read 6, iclass 21, count 0 2006.257.18:17:21.46#ibcon#read 6, iclass 21, count 0 2006.257.18:17:21.46#ibcon#end of sib2, iclass 21, count 0 2006.257.18:17:21.46#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:17:21.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:17:21.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:17:21.46#ibcon#*before write, iclass 21, count 0 2006.257.18:17:21.46#ibcon#enter sib2, iclass 21, count 0 2006.257.18:17:21.46#ibcon#flushed, iclass 21, count 0 2006.257.18:17:21.46#ibcon#about to write, iclass 21, count 0 2006.257.18:17:21.46#ibcon#wrote, iclass 21, count 0 2006.257.18:17:21.46#ibcon#about to read 3, iclass 21, count 0 2006.257.18:17:21.50#ibcon#read 3, iclass 21, count 0 2006.257.18:17:21.50#ibcon#about to read 4, iclass 21, count 0 2006.257.18:17:21.50#ibcon#read 4, iclass 21, count 0 2006.257.18:17:21.50#ibcon#about to read 5, iclass 21, count 0 2006.257.18:17:21.50#ibcon#read 5, iclass 21, count 0 2006.257.18:17:21.50#ibcon#about to read 6, iclass 21, count 0 2006.257.18:17:21.50#ibcon#read 6, iclass 21, count 0 2006.257.18:17:21.50#ibcon#end of sib2, iclass 21, count 0 2006.257.18:17:21.50#ibcon#*after write, iclass 21, count 0 2006.257.18:17:21.50#ibcon#*before return 0, iclass 21, count 0 2006.257.18:17:21.50#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:21.50#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:17:21.50#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:17:21.50#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:17:21.50$vck44/vb=2,5 2006.257.18:17:21.50#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.18:17:21.50#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.18:17:21.50#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:21.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:21.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:21.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:21.56#ibcon#enter wrdev, iclass 23, count 2 2006.257.18:17:21.56#ibcon#first serial, iclass 23, count 2 2006.257.18:17:21.56#ibcon#enter sib2, iclass 23, count 2 2006.257.18:17:21.56#ibcon#flushed, iclass 23, count 2 2006.257.18:17:21.56#ibcon#about to write, iclass 23, count 2 2006.257.18:17:21.56#ibcon#wrote, iclass 23, count 2 2006.257.18:17:21.56#ibcon#about to read 3, iclass 23, count 2 2006.257.18:17:21.58#ibcon#read 3, iclass 23, count 2 2006.257.18:17:21.58#ibcon#about to read 4, iclass 23, count 2 2006.257.18:17:21.58#ibcon#read 4, iclass 23, count 2 2006.257.18:17:21.58#ibcon#about to read 5, iclass 23, count 2 2006.257.18:17:21.58#ibcon#read 5, iclass 23, count 2 2006.257.18:17:21.58#ibcon#about to read 6, iclass 23, count 2 2006.257.18:17:21.58#ibcon#read 6, iclass 23, count 2 2006.257.18:17:21.58#ibcon#end of sib2, iclass 23, count 2 2006.257.18:17:21.58#ibcon#*mode == 0, iclass 23, count 2 2006.257.18:17:21.58#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.18:17:21.58#ibcon#[27=AT02-05\r\n] 2006.257.18:17:21.58#ibcon#*before write, iclass 23, count 2 2006.257.18:17:21.58#ibcon#enter sib2, iclass 23, count 2 2006.257.18:17:21.58#ibcon#flushed, iclass 23, count 2 2006.257.18:17:21.58#ibcon#about to write, iclass 23, count 2 2006.257.18:17:21.58#ibcon#wrote, iclass 23, count 2 2006.257.18:17:21.58#ibcon#about to read 3, iclass 23, count 2 2006.257.18:17:21.61#ibcon#read 3, iclass 23, count 2 2006.257.18:17:21.61#ibcon#about to read 4, iclass 23, count 2 2006.257.18:17:21.61#ibcon#read 4, iclass 23, count 2 2006.257.18:17:21.61#ibcon#about to read 5, iclass 23, count 2 2006.257.18:17:21.61#ibcon#read 5, iclass 23, count 2 2006.257.18:17:21.61#ibcon#about to read 6, iclass 23, count 2 2006.257.18:17:21.61#ibcon#read 6, iclass 23, count 2 2006.257.18:17:21.61#ibcon#end of sib2, iclass 23, count 2 2006.257.18:17:21.61#ibcon#*after write, iclass 23, count 2 2006.257.18:17:21.61#ibcon#*before return 0, iclass 23, count 2 2006.257.18:17:21.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:21.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:17:21.61#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.18:17:21.61#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:21.61#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:21.73#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:21.73#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:21.73#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:17:21.73#ibcon#first serial, iclass 23, count 0 2006.257.18:17:21.73#ibcon#enter sib2, iclass 23, count 0 2006.257.18:17:21.73#ibcon#flushed, iclass 23, count 0 2006.257.18:17:21.73#ibcon#about to write, iclass 23, count 0 2006.257.18:17:21.73#ibcon#wrote, iclass 23, count 0 2006.257.18:17:21.73#ibcon#about to read 3, iclass 23, count 0 2006.257.18:17:21.75#ibcon#read 3, iclass 23, count 0 2006.257.18:17:21.75#ibcon#about to read 4, iclass 23, count 0 2006.257.18:17:21.75#ibcon#read 4, iclass 23, count 0 2006.257.18:17:21.75#ibcon#about to read 5, iclass 23, count 0 2006.257.18:17:21.75#ibcon#read 5, iclass 23, count 0 2006.257.18:17:21.75#ibcon#about to read 6, iclass 23, count 0 2006.257.18:17:21.75#ibcon#read 6, iclass 23, count 0 2006.257.18:17:21.75#ibcon#end of sib2, iclass 23, count 0 2006.257.18:17:21.75#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:17:21.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:17:21.75#ibcon#[27=USB\r\n] 2006.257.18:17:21.75#ibcon#*before write, iclass 23, count 0 2006.257.18:17:21.75#ibcon#enter sib2, iclass 23, count 0 2006.257.18:17:21.75#ibcon#flushed, iclass 23, count 0 2006.257.18:17:21.75#ibcon#about to write, iclass 23, count 0 2006.257.18:17:21.75#ibcon#wrote, iclass 23, count 0 2006.257.18:17:21.75#ibcon#about to read 3, iclass 23, count 0 2006.257.18:17:21.78#ibcon#read 3, iclass 23, count 0 2006.257.18:17:21.78#ibcon#about to read 4, iclass 23, count 0 2006.257.18:17:21.78#ibcon#read 4, iclass 23, count 0 2006.257.18:17:21.78#ibcon#about to read 5, iclass 23, count 0 2006.257.18:17:21.78#ibcon#read 5, iclass 23, count 0 2006.257.18:17:21.78#ibcon#about to read 6, iclass 23, count 0 2006.257.18:17:21.78#ibcon#read 6, iclass 23, count 0 2006.257.18:17:21.78#ibcon#end of sib2, iclass 23, count 0 2006.257.18:17:21.78#ibcon#*after write, iclass 23, count 0 2006.257.18:17:21.78#ibcon#*before return 0, iclass 23, count 0 2006.257.18:17:21.78#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:21.78#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:17:21.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:17:21.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:17:21.78$vck44/vblo=3,649.99 2006.257.18:17:21.78#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.18:17:21.78#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.18:17:21.78#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:21.78#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:21.78#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:21.78#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:21.78#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:17:21.78#ibcon#first serial, iclass 25, count 0 2006.257.18:17:21.78#ibcon#enter sib2, iclass 25, count 0 2006.257.18:17:21.78#ibcon#flushed, iclass 25, count 0 2006.257.18:17:21.78#ibcon#about to write, iclass 25, count 0 2006.257.18:17:21.78#ibcon#wrote, iclass 25, count 0 2006.257.18:17:21.78#ibcon#about to read 3, iclass 25, count 0 2006.257.18:17:21.80#ibcon#read 3, iclass 25, count 0 2006.257.18:17:21.80#ibcon#about to read 4, iclass 25, count 0 2006.257.18:17:21.80#ibcon#read 4, iclass 25, count 0 2006.257.18:17:21.80#ibcon#about to read 5, iclass 25, count 0 2006.257.18:17:21.80#ibcon#read 5, iclass 25, count 0 2006.257.18:17:21.80#ibcon#about to read 6, iclass 25, count 0 2006.257.18:17:21.80#ibcon#read 6, iclass 25, count 0 2006.257.18:17:21.80#ibcon#end of sib2, iclass 25, count 0 2006.257.18:17:21.80#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:17:21.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:17:21.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:17:21.80#ibcon#*before write, iclass 25, count 0 2006.257.18:17:21.80#ibcon#enter sib2, iclass 25, count 0 2006.257.18:17:21.80#ibcon#flushed, iclass 25, count 0 2006.257.18:17:21.80#ibcon#about to write, iclass 25, count 0 2006.257.18:17:21.80#ibcon#wrote, iclass 25, count 0 2006.257.18:17:21.80#ibcon#about to read 3, iclass 25, count 0 2006.257.18:17:21.84#ibcon#read 3, iclass 25, count 0 2006.257.18:17:21.84#ibcon#about to read 4, iclass 25, count 0 2006.257.18:17:21.84#ibcon#read 4, iclass 25, count 0 2006.257.18:17:21.84#ibcon#about to read 5, iclass 25, count 0 2006.257.18:17:21.84#ibcon#read 5, iclass 25, count 0 2006.257.18:17:21.84#ibcon#about to read 6, iclass 25, count 0 2006.257.18:17:21.84#ibcon#read 6, iclass 25, count 0 2006.257.18:17:21.84#ibcon#end of sib2, iclass 25, count 0 2006.257.18:17:21.84#ibcon#*after write, iclass 25, count 0 2006.257.18:17:21.84#ibcon#*before return 0, iclass 25, count 0 2006.257.18:17:21.84#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:21.84#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:17:21.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:17:21.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:17:21.84$vck44/vb=3,4 2006.257.18:17:21.84#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.18:17:21.84#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.18:17:21.84#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:21.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:21.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:21.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:21.90#ibcon#enter wrdev, iclass 27, count 2 2006.257.18:17:21.90#ibcon#first serial, iclass 27, count 2 2006.257.18:17:21.90#ibcon#enter sib2, iclass 27, count 2 2006.257.18:17:21.90#ibcon#flushed, iclass 27, count 2 2006.257.18:17:21.90#ibcon#about to write, iclass 27, count 2 2006.257.18:17:21.90#ibcon#wrote, iclass 27, count 2 2006.257.18:17:21.90#ibcon#about to read 3, iclass 27, count 2 2006.257.18:17:21.92#ibcon#read 3, iclass 27, count 2 2006.257.18:17:21.92#ibcon#about to read 4, iclass 27, count 2 2006.257.18:17:21.92#ibcon#read 4, iclass 27, count 2 2006.257.18:17:21.92#ibcon#about to read 5, iclass 27, count 2 2006.257.18:17:21.92#ibcon#read 5, iclass 27, count 2 2006.257.18:17:21.92#ibcon#about to read 6, iclass 27, count 2 2006.257.18:17:21.92#ibcon#read 6, iclass 27, count 2 2006.257.18:17:21.92#ibcon#end of sib2, iclass 27, count 2 2006.257.18:17:21.92#ibcon#*mode == 0, iclass 27, count 2 2006.257.18:17:21.92#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.18:17:21.92#ibcon#[27=AT03-04\r\n] 2006.257.18:17:21.92#ibcon#*before write, iclass 27, count 2 2006.257.18:17:21.92#ibcon#enter sib2, iclass 27, count 2 2006.257.18:17:21.92#ibcon#flushed, iclass 27, count 2 2006.257.18:17:21.92#ibcon#about to write, iclass 27, count 2 2006.257.18:17:21.92#ibcon#wrote, iclass 27, count 2 2006.257.18:17:21.92#ibcon#about to read 3, iclass 27, count 2 2006.257.18:17:21.95#ibcon#read 3, iclass 27, count 2 2006.257.18:17:21.95#ibcon#about to read 4, iclass 27, count 2 2006.257.18:17:21.95#ibcon#read 4, iclass 27, count 2 2006.257.18:17:21.95#ibcon#about to read 5, iclass 27, count 2 2006.257.18:17:21.95#ibcon#read 5, iclass 27, count 2 2006.257.18:17:21.95#ibcon#about to read 6, iclass 27, count 2 2006.257.18:17:21.95#ibcon#read 6, iclass 27, count 2 2006.257.18:17:21.95#ibcon#end of sib2, iclass 27, count 2 2006.257.18:17:21.95#ibcon#*after write, iclass 27, count 2 2006.257.18:17:21.95#ibcon#*before return 0, iclass 27, count 2 2006.257.18:17:21.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:21.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:17:21.95#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.18:17:21.95#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:21.95#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:22.07#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:22.07#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:22.07#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:17:22.07#ibcon#first serial, iclass 27, count 0 2006.257.18:17:22.07#ibcon#enter sib2, iclass 27, count 0 2006.257.18:17:22.07#ibcon#flushed, iclass 27, count 0 2006.257.18:17:22.07#ibcon#about to write, iclass 27, count 0 2006.257.18:17:22.07#ibcon#wrote, iclass 27, count 0 2006.257.18:17:22.07#ibcon#about to read 3, iclass 27, count 0 2006.257.18:17:22.09#ibcon#read 3, iclass 27, count 0 2006.257.18:17:22.09#ibcon#about to read 4, iclass 27, count 0 2006.257.18:17:22.09#ibcon#read 4, iclass 27, count 0 2006.257.18:17:22.09#ibcon#about to read 5, iclass 27, count 0 2006.257.18:17:22.09#ibcon#read 5, iclass 27, count 0 2006.257.18:17:22.09#ibcon#about to read 6, iclass 27, count 0 2006.257.18:17:22.09#ibcon#read 6, iclass 27, count 0 2006.257.18:17:22.09#ibcon#end of sib2, iclass 27, count 0 2006.257.18:17:22.09#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:17:22.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:17:22.09#ibcon#[27=USB\r\n] 2006.257.18:17:22.09#ibcon#*before write, iclass 27, count 0 2006.257.18:17:22.09#ibcon#enter sib2, iclass 27, count 0 2006.257.18:17:22.09#ibcon#flushed, iclass 27, count 0 2006.257.18:17:22.09#ibcon#about to write, iclass 27, count 0 2006.257.18:17:22.09#ibcon#wrote, iclass 27, count 0 2006.257.18:17:22.09#ibcon#about to read 3, iclass 27, count 0 2006.257.18:17:22.12#ibcon#read 3, iclass 27, count 0 2006.257.18:17:22.12#ibcon#about to read 4, iclass 27, count 0 2006.257.18:17:22.12#ibcon#read 4, iclass 27, count 0 2006.257.18:17:22.12#ibcon#about to read 5, iclass 27, count 0 2006.257.18:17:22.12#ibcon#read 5, iclass 27, count 0 2006.257.18:17:22.12#ibcon#about to read 6, iclass 27, count 0 2006.257.18:17:22.12#ibcon#read 6, iclass 27, count 0 2006.257.18:17:22.12#ibcon#end of sib2, iclass 27, count 0 2006.257.18:17:22.12#ibcon#*after write, iclass 27, count 0 2006.257.18:17:22.12#ibcon#*before return 0, iclass 27, count 0 2006.257.18:17:22.12#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:22.12#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:17:22.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:17:22.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:17:22.12$vck44/vblo=4,679.99 2006.257.18:17:22.12#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.18:17:22.12#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.18:17:22.12#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:22.12#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:22.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:22.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:22.12#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:17:22.12#ibcon#first serial, iclass 29, count 0 2006.257.18:17:22.12#ibcon#enter sib2, iclass 29, count 0 2006.257.18:17:22.12#ibcon#flushed, iclass 29, count 0 2006.257.18:17:22.12#ibcon#about to write, iclass 29, count 0 2006.257.18:17:22.12#ibcon#wrote, iclass 29, count 0 2006.257.18:17:22.12#ibcon#about to read 3, iclass 29, count 0 2006.257.18:17:22.14#ibcon#read 3, iclass 29, count 0 2006.257.18:17:22.14#ibcon#about to read 4, iclass 29, count 0 2006.257.18:17:22.14#ibcon#read 4, iclass 29, count 0 2006.257.18:17:22.14#ibcon#about to read 5, iclass 29, count 0 2006.257.18:17:22.14#ibcon#read 5, iclass 29, count 0 2006.257.18:17:22.14#ibcon#about to read 6, iclass 29, count 0 2006.257.18:17:22.14#ibcon#read 6, iclass 29, count 0 2006.257.18:17:22.14#ibcon#end of sib2, iclass 29, count 0 2006.257.18:17:22.14#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:17:22.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:17:22.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:17:22.14#ibcon#*before write, iclass 29, count 0 2006.257.18:17:22.14#ibcon#enter sib2, iclass 29, count 0 2006.257.18:17:22.14#ibcon#flushed, iclass 29, count 0 2006.257.18:17:22.14#ibcon#about to write, iclass 29, count 0 2006.257.18:17:22.14#ibcon#wrote, iclass 29, count 0 2006.257.18:17:22.14#ibcon#about to read 3, iclass 29, count 0 2006.257.18:17:22.18#ibcon#read 3, iclass 29, count 0 2006.257.18:17:22.18#ibcon#about to read 4, iclass 29, count 0 2006.257.18:17:22.18#ibcon#read 4, iclass 29, count 0 2006.257.18:17:22.18#ibcon#about to read 5, iclass 29, count 0 2006.257.18:17:22.18#ibcon#read 5, iclass 29, count 0 2006.257.18:17:22.18#ibcon#about to read 6, iclass 29, count 0 2006.257.18:17:22.18#ibcon#read 6, iclass 29, count 0 2006.257.18:17:22.18#ibcon#end of sib2, iclass 29, count 0 2006.257.18:17:22.18#ibcon#*after write, iclass 29, count 0 2006.257.18:17:22.18#ibcon#*before return 0, iclass 29, count 0 2006.257.18:17:22.18#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:22.18#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:17:22.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:17:22.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:17:22.18$vck44/vb=4,5 2006.257.18:17:22.18#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.18:17:22.18#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.18:17:22.18#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:22.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:22.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:22.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:22.24#ibcon#enter wrdev, iclass 31, count 2 2006.257.18:17:22.24#ibcon#first serial, iclass 31, count 2 2006.257.18:17:22.24#ibcon#enter sib2, iclass 31, count 2 2006.257.18:17:22.24#ibcon#flushed, iclass 31, count 2 2006.257.18:17:22.24#ibcon#about to write, iclass 31, count 2 2006.257.18:17:22.24#ibcon#wrote, iclass 31, count 2 2006.257.18:17:22.24#ibcon#about to read 3, iclass 31, count 2 2006.257.18:17:22.26#ibcon#read 3, iclass 31, count 2 2006.257.18:17:22.26#ibcon#about to read 4, iclass 31, count 2 2006.257.18:17:22.26#ibcon#read 4, iclass 31, count 2 2006.257.18:17:22.26#ibcon#about to read 5, iclass 31, count 2 2006.257.18:17:22.26#ibcon#read 5, iclass 31, count 2 2006.257.18:17:22.26#ibcon#about to read 6, iclass 31, count 2 2006.257.18:17:22.26#ibcon#read 6, iclass 31, count 2 2006.257.18:17:22.26#ibcon#end of sib2, iclass 31, count 2 2006.257.18:17:22.26#ibcon#*mode == 0, iclass 31, count 2 2006.257.18:17:22.26#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.18:17:22.26#ibcon#[27=AT04-05\r\n] 2006.257.18:17:22.26#ibcon#*before write, iclass 31, count 2 2006.257.18:17:22.26#ibcon#enter sib2, iclass 31, count 2 2006.257.18:17:22.26#ibcon#flushed, iclass 31, count 2 2006.257.18:17:22.26#ibcon#about to write, iclass 31, count 2 2006.257.18:17:22.26#ibcon#wrote, iclass 31, count 2 2006.257.18:17:22.26#ibcon#about to read 3, iclass 31, count 2 2006.257.18:17:22.29#ibcon#read 3, iclass 31, count 2 2006.257.18:17:22.29#ibcon#about to read 4, iclass 31, count 2 2006.257.18:17:22.29#ibcon#read 4, iclass 31, count 2 2006.257.18:17:22.29#ibcon#about to read 5, iclass 31, count 2 2006.257.18:17:22.29#ibcon#read 5, iclass 31, count 2 2006.257.18:17:22.29#ibcon#about to read 6, iclass 31, count 2 2006.257.18:17:22.29#ibcon#read 6, iclass 31, count 2 2006.257.18:17:22.29#ibcon#end of sib2, iclass 31, count 2 2006.257.18:17:22.29#ibcon#*after write, iclass 31, count 2 2006.257.18:17:22.29#ibcon#*before return 0, iclass 31, count 2 2006.257.18:17:22.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:22.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:17:22.29#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.18:17:22.29#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:22.29#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:22.41#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:22.41#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:22.41#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:17:22.41#ibcon#first serial, iclass 31, count 0 2006.257.18:17:22.41#ibcon#enter sib2, iclass 31, count 0 2006.257.18:17:22.41#ibcon#flushed, iclass 31, count 0 2006.257.18:17:22.41#ibcon#about to write, iclass 31, count 0 2006.257.18:17:22.41#ibcon#wrote, iclass 31, count 0 2006.257.18:17:22.41#ibcon#about to read 3, iclass 31, count 0 2006.257.18:17:22.43#ibcon#read 3, iclass 31, count 0 2006.257.18:17:22.43#ibcon#about to read 4, iclass 31, count 0 2006.257.18:17:22.43#ibcon#read 4, iclass 31, count 0 2006.257.18:17:22.43#ibcon#about to read 5, iclass 31, count 0 2006.257.18:17:22.43#ibcon#read 5, iclass 31, count 0 2006.257.18:17:22.43#ibcon#about to read 6, iclass 31, count 0 2006.257.18:17:22.43#ibcon#read 6, iclass 31, count 0 2006.257.18:17:22.43#ibcon#end of sib2, iclass 31, count 0 2006.257.18:17:22.43#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:17:22.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:17:22.43#ibcon#[27=USB\r\n] 2006.257.18:17:22.43#ibcon#*before write, iclass 31, count 0 2006.257.18:17:22.43#ibcon#enter sib2, iclass 31, count 0 2006.257.18:17:22.43#ibcon#flushed, iclass 31, count 0 2006.257.18:17:22.43#ibcon#about to write, iclass 31, count 0 2006.257.18:17:22.43#ibcon#wrote, iclass 31, count 0 2006.257.18:17:22.43#ibcon#about to read 3, iclass 31, count 0 2006.257.18:17:22.46#ibcon#read 3, iclass 31, count 0 2006.257.18:17:22.46#ibcon#about to read 4, iclass 31, count 0 2006.257.18:17:22.46#ibcon#read 4, iclass 31, count 0 2006.257.18:17:22.46#ibcon#about to read 5, iclass 31, count 0 2006.257.18:17:22.46#ibcon#read 5, iclass 31, count 0 2006.257.18:17:22.46#ibcon#about to read 6, iclass 31, count 0 2006.257.18:17:22.46#ibcon#read 6, iclass 31, count 0 2006.257.18:17:22.46#ibcon#end of sib2, iclass 31, count 0 2006.257.18:17:22.46#ibcon#*after write, iclass 31, count 0 2006.257.18:17:22.46#ibcon#*before return 0, iclass 31, count 0 2006.257.18:17:22.46#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:22.46#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:17:22.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:17:22.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:17:22.46$vck44/vblo=5,709.99 2006.257.18:17:22.46#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.18:17:22.46#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.18:17:22.46#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:22.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:22.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:22.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:22.46#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:17:22.46#ibcon#first serial, iclass 33, count 0 2006.257.18:17:22.46#ibcon#enter sib2, iclass 33, count 0 2006.257.18:17:22.46#ibcon#flushed, iclass 33, count 0 2006.257.18:17:22.46#ibcon#about to write, iclass 33, count 0 2006.257.18:17:22.46#ibcon#wrote, iclass 33, count 0 2006.257.18:17:22.46#ibcon#about to read 3, iclass 33, count 0 2006.257.18:17:22.48#ibcon#read 3, iclass 33, count 0 2006.257.18:17:22.48#ibcon#about to read 4, iclass 33, count 0 2006.257.18:17:22.48#ibcon#read 4, iclass 33, count 0 2006.257.18:17:22.48#ibcon#about to read 5, iclass 33, count 0 2006.257.18:17:22.48#ibcon#read 5, iclass 33, count 0 2006.257.18:17:22.48#ibcon#about to read 6, iclass 33, count 0 2006.257.18:17:22.48#ibcon#read 6, iclass 33, count 0 2006.257.18:17:22.48#ibcon#end of sib2, iclass 33, count 0 2006.257.18:17:22.48#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:17:22.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:17:22.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:17:22.48#ibcon#*before write, iclass 33, count 0 2006.257.18:17:22.48#ibcon#enter sib2, iclass 33, count 0 2006.257.18:17:22.48#ibcon#flushed, iclass 33, count 0 2006.257.18:17:22.48#ibcon#about to write, iclass 33, count 0 2006.257.18:17:22.48#ibcon#wrote, iclass 33, count 0 2006.257.18:17:22.48#ibcon#about to read 3, iclass 33, count 0 2006.257.18:17:22.52#ibcon#read 3, iclass 33, count 0 2006.257.18:17:22.52#ibcon#about to read 4, iclass 33, count 0 2006.257.18:17:22.52#ibcon#read 4, iclass 33, count 0 2006.257.18:17:22.52#ibcon#about to read 5, iclass 33, count 0 2006.257.18:17:22.52#ibcon#read 5, iclass 33, count 0 2006.257.18:17:22.52#ibcon#about to read 6, iclass 33, count 0 2006.257.18:17:22.52#ibcon#read 6, iclass 33, count 0 2006.257.18:17:22.52#ibcon#end of sib2, iclass 33, count 0 2006.257.18:17:22.52#ibcon#*after write, iclass 33, count 0 2006.257.18:17:22.52#ibcon#*before return 0, iclass 33, count 0 2006.257.18:17:22.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:22.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:17:22.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:17:22.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:17:22.52$vck44/vb=5,4 2006.257.18:17:22.52#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.18:17:22.52#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.18:17:22.52#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:22.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:22.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:22.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:22.58#ibcon#enter wrdev, iclass 35, count 2 2006.257.18:17:22.58#ibcon#first serial, iclass 35, count 2 2006.257.18:17:22.58#ibcon#enter sib2, iclass 35, count 2 2006.257.18:17:22.58#ibcon#flushed, iclass 35, count 2 2006.257.18:17:22.58#ibcon#about to write, iclass 35, count 2 2006.257.18:17:22.58#ibcon#wrote, iclass 35, count 2 2006.257.18:17:22.58#ibcon#about to read 3, iclass 35, count 2 2006.257.18:17:22.60#ibcon#read 3, iclass 35, count 2 2006.257.18:17:22.60#ibcon#about to read 4, iclass 35, count 2 2006.257.18:17:22.60#ibcon#read 4, iclass 35, count 2 2006.257.18:17:22.60#ibcon#about to read 5, iclass 35, count 2 2006.257.18:17:22.60#ibcon#read 5, iclass 35, count 2 2006.257.18:17:22.60#ibcon#about to read 6, iclass 35, count 2 2006.257.18:17:22.60#ibcon#read 6, iclass 35, count 2 2006.257.18:17:22.60#ibcon#end of sib2, iclass 35, count 2 2006.257.18:17:22.60#ibcon#*mode == 0, iclass 35, count 2 2006.257.18:17:22.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.18:17:22.60#ibcon#[27=AT05-04\r\n] 2006.257.18:17:22.60#ibcon#*before write, iclass 35, count 2 2006.257.18:17:22.60#ibcon#enter sib2, iclass 35, count 2 2006.257.18:17:22.60#ibcon#flushed, iclass 35, count 2 2006.257.18:17:22.60#ibcon#about to write, iclass 35, count 2 2006.257.18:17:22.60#ibcon#wrote, iclass 35, count 2 2006.257.18:17:22.60#ibcon#about to read 3, iclass 35, count 2 2006.257.18:17:22.63#ibcon#read 3, iclass 35, count 2 2006.257.18:17:22.63#ibcon#about to read 4, iclass 35, count 2 2006.257.18:17:22.63#ibcon#read 4, iclass 35, count 2 2006.257.18:17:22.63#ibcon#about to read 5, iclass 35, count 2 2006.257.18:17:22.63#ibcon#read 5, iclass 35, count 2 2006.257.18:17:22.63#ibcon#about to read 6, iclass 35, count 2 2006.257.18:17:22.63#ibcon#read 6, iclass 35, count 2 2006.257.18:17:22.63#ibcon#end of sib2, iclass 35, count 2 2006.257.18:17:22.63#ibcon#*after write, iclass 35, count 2 2006.257.18:17:22.63#ibcon#*before return 0, iclass 35, count 2 2006.257.18:17:22.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:22.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:17:22.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.18:17:22.63#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:22.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:22.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:22.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:22.75#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:17:22.75#ibcon#first serial, iclass 35, count 0 2006.257.18:17:22.75#ibcon#enter sib2, iclass 35, count 0 2006.257.18:17:22.75#ibcon#flushed, iclass 35, count 0 2006.257.18:17:22.75#ibcon#about to write, iclass 35, count 0 2006.257.18:17:22.75#ibcon#wrote, iclass 35, count 0 2006.257.18:17:22.75#ibcon#about to read 3, iclass 35, count 0 2006.257.18:17:22.77#ibcon#read 3, iclass 35, count 0 2006.257.18:17:22.77#ibcon#about to read 4, iclass 35, count 0 2006.257.18:17:22.77#ibcon#read 4, iclass 35, count 0 2006.257.18:17:22.77#ibcon#about to read 5, iclass 35, count 0 2006.257.18:17:22.77#ibcon#read 5, iclass 35, count 0 2006.257.18:17:22.77#ibcon#about to read 6, iclass 35, count 0 2006.257.18:17:22.77#ibcon#read 6, iclass 35, count 0 2006.257.18:17:22.77#ibcon#end of sib2, iclass 35, count 0 2006.257.18:17:22.77#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:17:22.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:17:22.77#ibcon#[27=USB\r\n] 2006.257.18:17:22.77#ibcon#*before write, iclass 35, count 0 2006.257.18:17:22.77#ibcon#enter sib2, iclass 35, count 0 2006.257.18:17:22.77#ibcon#flushed, iclass 35, count 0 2006.257.18:17:22.77#ibcon#about to write, iclass 35, count 0 2006.257.18:17:22.77#ibcon#wrote, iclass 35, count 0 2006.257.18:17:22.77#ibcon#about to read 3, iclass 35, count 0 2006.257.18:17:22.80#ibcon#read 3, iclass 35, count 0 2006.257.18:17:22.80#ibcon#about to read 4, iclass 35, count 0 2006.257.18:17:22.80#ibcon#read 4, iclass 35, count 0 2006.257.18:17:22.80#ibcon#about to read 5, iclass 35, count 0 2006.257.18:17:22.80#ibcon#read 5, iclass 35, count 0 2006.257.18:17:22.80#ibcon#about to read 6, iclass 35, count 0 2006.257.18:17:22.80#ibcon#read 6, iclass 35, count 0 2006.257.18:17:22.80#ibcon#end of sib2, iclass 35, count 0 2006.257.18:17:22.80#ibcon#*after write, iclass 35, count 0 2006.257.18:17:22.80#ibcon#*before return 0, iclass 35, count 0 2006.257.18:17:22.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:22.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:17:22.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:17:22.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:17:22.80$vck44/vblo=6,719.99 2006.257.18:17:22.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.18:17:22.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.18:17:22.80#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:22.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:22.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:22.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:22.80#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:17:22.80#ibcon#first serial, iclass 37, count 0 2006.257.18:17:22.80#ibcon#enter sib2, iclass 37, count 0 2006.257.18:17:22.80#ibcon#flushed, iclass 37, count 0 2006.257.18:17:22.80#ibcon#about to write, iclass 37, count 0 2006.257.18:17:22.80#ibcon#wrote, iclass 37, count 0 2006.257.18:17:22.80#ibcon#about to read 3, iclass 37, count 0 2006.257.18:17:22.82#ibcon#read 3, iclass 37, count 0 2006.257.18:17:22.82#ibcon#about to read 4, iclass 37, count 0 2006.257.18:17:22.82#ibcon#read 4, iclass 37, count 0 2006.257.18:17:22.82#ibcon#about to read 5, iclass 37, count 0 2006.257.18:17:22.82#ibcon#read 5, iclass 37, count 0 2006.257.18:17:22.82#ibcon#about to read 6, iclass 37, count 0 2006.257.18:17:22.82#ibcon#read 6, iclass 37, count 0 2006.257.18:17:22.82#ibcon#end of sib2, iclass 37, count 0 2006.257.18:17:22.82#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:17:22.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:17:22.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:17:22.82#ibcon#*before write, iclass 37, count 0 2006.257.18:17:22.82#ibcon#enter sib2, iclass 37, count 0 2006.257.18:17:22.82#ibcon#flushed, iclass 37, count 0 2006.257.18:17:22.82#ibcon#about to write, iclass 37, count 0 2006.257.18:17:22.82#ibcon#wrote, iclass 37, count 0 2006.257.18:17:22.82#ibcon#about to read 3, iclass 37, count 0 2006.257.18:17:22.86#ibcon#read 3, iclass 37, count 0 2006.257.18:17:22.86#ibcon#about to read 4, iclass 37, count 0 2006.257.18:17:22.86#ibcon#read 4, iclass 37, count 0 2006.257.18:17:22.86#ibcon#about to read 5, iclass 37, count 0 2006.257.18:17:22.86#ibcon#read 5, iclass 37, count 0 2006.257.18:17:22.86#ibcon#about to read 6, iclass 37, count 0 2006.257.18:17:22.86#ibcon#read 6, iclass 37, count 0 2006.257.18:17:22.86#ibcon#end of sib2, iclass 37, count 0 2006.257.18:17:22.86#ibcon#*after write, iclass 37, count 0 2006.257.18:17:22.86#ibcon#*before return 0, iclass 37, count 0 2006.257.18:17:22.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:22.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:17:22.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:17:22.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:17:22.86$vck44/vb=6,4 2006.257.18:17:22.86#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.18:17:22.86#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.18:17:22.86#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:22.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:22.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:22.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:22.92#ibcon#enter wrdev, iclass 39, count 2 2006.257.18:17:22.92#ibcon#first serial, iclass 39, count 2 2006.257.18:17:22.92#ibcon#enter sib2, iclass 39, count 2 2006.257.18:17:22.92#ibcon#flushed, iclass 39, count 2 2006.257.18:17:22.92#ibcon#about to write, iclass 39, count 2 2006.257.18:17:22.92#ibcon#wrote, iclass 39, count 2 2006.257.18:17:22.92#ibcon#about to read 3, iclass 39, count 2 2006.257.18:17:22.94#ibcon#read 3, iclass 39, count 2 2006.257.18:17:22.94#ibcon#about to read 4, iclass 39, count 2 2006.257.18:17:22.94#ibcon#read 4, iclass 39, count 2 2006.257.18:17:22.94#ibcon#about to read 5, iclass 39, count 2 2006.257.18:17:22.94#ibcon#read 5, iclass 39, count 2 2006.257.18:17:22.94#ibcon#about to read 6, iclass 39, count 2 2006.257.18:17:22.94#ibcon#read 6, iclass 39, count 2 2006.257.18:17:22.94#ibcon#end of sib2, iclass 39, count 2 2006.257.18:17:22.94#ibcon#*mode == 0, iclass 39, count 2 2006.257.18:17:22.94#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.18:17:22.94#ibcon#[27=AT06-04\r\n] 2006.257.18:17:22.94#ibcon#*before write, iclass 39, count 2 2006.257.18:17:22.94#ibcon#enter sib2, iclass 39, count 2 2006.257.18:17:22.94#ibcon#flushed, iclass 39, count 2 2006.257.18:17:22.94#ibcon#about to write, iclass 39, count 2 2006.257.18:17:22.94#ibcon#wrote, iclass 39, count 2 2006.257.18:17:22.94#ibcon#about to read 3, iclass 39, count 2 2006.257.18:17:22.97#ibcon#read 3, iclass 39, count 2 2006.257.18:17:22.97#ibcon#about to read 4, iclass 39, count 2 2006.257.18:17:22.97#ibcon#read 4, iclass 39, count 2 2006.257.18:17:22.97#ibcon#about to read 5, iclass 39, count 2 2006.257.18:17:22.97#ibcon#read 5, iclass 39, count 2 2006.257.18:17:22.97#ibcon#about to read 6, iclass 39, count 2 2006.257.18:17:22.97#ibcon#read 6, iclass 39, count 2 2006.257.18:17:22.97#ibcon#end of sib2, iclass 39, count 2 2006.257.18:17:22.97#ibcon#*after write, iclass 39, count 2 2006.257.18:17:22.97#ibcon#*before return 0, iclass 39, count 2 2006.257.18:17:22.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:22.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:17:22.97#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.18:17:22.97#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:22.97#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:23.09#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:23.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:23.09#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:17:23.09#ibcon#first serial, iclass 39, count 0 2006.257.18:17:23.09#ibcon#enter sib2, iclass 39, count 0 2006.257.18:17:23.09#ibcon#flushed, iclass 39, count 0 2006.257.18:17:23.09#ibcon#about to write, iclass 39, count 0 2006.257.18:17:23.09#ibcon#wrote, iclass 39, count 0 2006.257.18:17:23.09#ibcon#about to read 3, iclass 39, count 0 2006.257.18:17:23.11#ibcon#read 3, iclass 39, count 0 2006.257.18:17:23.11#ibcon#about to read 4, iclass 39, count 0 2006.257.18:17:23.11#ibcon#read 4, iclass 39, count 0 2006.257.18:17:23.11#ibcon#about to read 5, iclass 39, count 0 2006.257.18:17:23.11#ibcon#read 5, iclass 39, count 0 2006.257.18:17:23.11#ibcon#about to read 6, iclass 39, count 0 2006.257.18:17:23.11#ibcon#read 6, iclass 39, count 0 2006.257.18:17:23.11#ibcon#end of sib2, iclass 39, count 0 2006.257.18:17:23.11#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:17:23.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:17:23.11#ibcon#[27=USB\r\n] 2006.257.18:17:23.11#ibcon#*before write, iclass 39, count 0 2006.257.18:17:23.11#ibcon#enter sib2, iclass 39, count 0 2006.257.18:17:23.11#ibcon#flushed, iclass 39, count 0 2006.257.18:17:23.11#ibcon#about to write, iclass 39, count 0 2006.257.18:17:23.11#ibcon#wrote, iclass 39, count 0 2006.257.18:17:23.11#ibcon#about to read 3, iclass 39, count 0 2006.257.18:17:23.14#ibcon#read 3, iclass 39, count 0 2006.257.18:17:23.14#ibcon#about to read 4, iclass 39, count 0 2006.257.18:17:23.14#ibcon#read 4, iclass 39, count 0 2006.257.18:17:23.14#ibcon#about to read 5, iclass 39, count 0 2006.257.18:17:23.14#ibcon#read 5, iclass 39, count 0 2006.257.18:17:23.14#ibcon#about to read 6, iclass 39, count 0 2006.257.18:17:23.14#ibcon#read 6, iclass 39, count 0 2006.257.18:17:23.14#ibcon#end of sib2, iclass 39, count 0 2006.257.18:17:23.14#ibcon#*after write, iclass 39, count 0 2006.257.18:17:23.14#ibcon#*before return 0, iclass 39, count 0 2006.257.18:17:23.14#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:23.14#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:17:23.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:17:23.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:17:23.14$vck44/vblo=7,734.99 2006.257.18:17:23.14#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.18:17:23.14#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.18:17:23.14#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:23.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:23.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:23.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:23.14#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:17:23.14#ibcon#first serial, iclass 3, count 0 2006.257.18:17:23.14#ibcon#enter sib2, iclass 3, count 0 2006.257.18:17:23.14#ibcon#flushed, iclass 3, count 0 2006.257.18:17:23.14#ibcon#about to write, iclass 3, count 0 2006.257.18:17:23.14#ibcon#wrote, iclass 3, count 0 2006.257.18:17:23.14#ibcon#about to read 3, iclass 3, count 0 2006.257.18:17:23.16#ibcon#read 3, iclass 3, count 0 2006.257.18:17:23.16#ibcon#about to read 4, iclass 3, count 0 2006.257.18:17:23.16#ibcon#read 4, iclass 3, count 0 2006.257.18:17:23.16#ibcon#about to read 5, iclass 3, count 0 2006.257.18:17:23.16#ibcon#read 5, iclass 3, count 0 2006.257.18:17:23.16#ibcon#about to read 6, iclass 3, count 0 2006.257.18:17:23.16#ibcon#read 6, iclass 3, count 0 2006.257.18:17:23.16#ibcon#end of sib2, iclass 3, count 0 2006.257.18:17:23.16#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:17:23.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:17:23.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:17:23.16#ibcon#*before write, iclass 3, count 0 2006.257.18:17:23.16#ibcon#enter sib2, iclass 3, count 0 2006.257.18:17:23.16#ibcon#flushed, iclass 3, count 0 2006.257.18:17:23.16#ibcon#about to write, iclass 3, count 0 2006.257.18:17:23.16#ibcon#wrote, iclass 3, count 0 2006.257.18:17:23.16#ibcon#about to read 3, iclass 3, count 0 2006.257.18:17:23.20#ibcon#read 3, iclass 3, count 0 2006.257.18:17:23.20#ibcon#about to read 4, iclass 3, count 0 2006.257.18:17:23.20#ibcon#read 4, iclass 3, count 0 2006.257.18:17:23.20#ibcon#about to read 5, iclass 3, count 0 2006.257.18:17:23.20#ibcon#read 5, iclass 3, count 0 2006.257.18:17:23.20#ibcon#about to read 6, iclass 3, count 0 2006.257.18:17:23.20#ibcon#read 6, iclass 3, count 0 2006.257.18:17:23.20#ibcon#end of sib2, iclass 3, count 0 2006.257.18:17:23.20#ibcon#*after write, iclass 3, count 0 2006.257.18:17:23.20#ibcon#*before return 0, iclass 3, count 0 2006.257.18:17:23.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:23.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:17:23.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:17:23.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:17:23.20$vck44/vb=7,4 2006.257.18:17:23.20#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.18:17:23.20#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.18:17:23.20#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:23.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:23.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:23.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:23.26#ibcon#enter wrdev, iclass 5, count 2 2006.257.18:17:23.26#ibcon#first serial, iclass 5, count 2 2006.257.18:17:23.26#ibcon#enter sib2, iclass 5, count 2 2006.257.18:17:23.26#ibcon#flushed, iclass 5, count 2 2006.257.18:17:23.26#ibcon#about to write, iclass 5, count 2 2006.257.18:17:23.26#ibcon#wrote, iclass 5, count 2 2006.257.18:17:23.26#ibcon#about to read 3, iclass 5, count 2 2006.257.18:17:23.28#ibcon#read 3, iclass 5, count 2 2006.257.18:17:23.28#ibcon#about to read 4, iclass 5, count 2 2006.257.18:17:23.28#ibcon#read 4, iclass 5, count 2 2006.257.18:17:23.28#ibcon#about to read 5, iclass 5, count 2 2006.257.18:17:23.28#ibcon#read 5, iclass 5, count 2 2006.257.18:17:23.28#ibcon#about to read 6, iclass 5, count 2 2006.257.18:17:23.28#ibcon#read 6, iclass 5, count 2 2006.257.18:17:23.28#ibcon#end of sib2, iclass 5, count 2 2006.257.18:17:23.28#ibcon#*mode == 0, iclass 5, count 2 2006.257.18:17:23.28#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.18:17:23.28#ibcon#[27=AT07-04\r\n] 2006.257.18:17:23.28#ibcon#*before write, iclass 5, count 2 2006.257.18:17:23.28#ibcon#enter sib2, iclass 5, count 2 2006.257.18:17:23.28#ibcon#flushed, iclass 5, count 2 2006.257.18:17:23.28#ibcon#about to write, iclass 5, count 2 2006.257.18:17:23.28#ibcon#wrote, iclass 5, count 2 2006.257.18:17:23.28#ibcon#about to read 3, iclass 5, count 2 2006.257.18:17:23.31#ibcon#read 3, iclass 5, count 2 2006.257.18:17:23.31#ibcon#about to read 4, iclass 5, count 2 2006.257.18:17:23.31#ibcon#read 4, iclass 5, count 2 2006.257.18:17:23.31#ibcon#about to read 5, iclass 5, count 2 2006.257.18:17:23.31#ibcon#read 5, iclass 5, count 2 2006.257.18:17:23.31#ibcon#about to read 6, iclass 5, count 2 2006.257.18:17:23.31#ibcon#read 6, iclass 5, count 2 2006.257.18:17:23.31#ibcon#end of sib2, iclass 5, count 2 2006.257.18:17:23.31#ibcon#*after write, iclass 5, count 2 2006.257.18:17:23.31#ibcon#*before return 0, iclass 5, count 2 2006.257.18:17:23.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:23.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:17:23.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.18:17:23.31#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:23.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:23.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:23.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:23.43#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:17:23.43#ibcon#first serial, iclass 5, count 0 2006.257.18:17:23.43#ibcon#enter sib2, iclass 5, count 0 2006.257.18:17:23.43#ibcon#flushed, iclass 5, count 0 2006.257.18:17:23.43#ibcon#about to write, iclass 5, count 0 2006.257.18:17:23.43#ibcon#wrote, iclass 5, count 0 2006.257.18:17:23.43#ibcon#about to read 3, iclass 5, count 0 2006.257.18:17:23.45#ibcon#read 3, iclass 5, count 0 2006.257.18:17:23.45#ibcon#about to read 4, iclass 5, count 0 2006.257.18:17:23.45#ibcon#read 4, iclass 5, count 0 2006.257.18:17:23.45#ibcon#about to read 5, iclass 5, count 0 2006.257.18:17:23.45#ibcon#read 5, iclass 5, count 0 2006.257.18:17:23.45#ibcon#about to read 6, iclass 5, count 0 2006.257.18:17:23.45#ibcon#read 6, iclass 5, count 0 2006.257.18:17:23.45#ibcon#end of sib2, iclass 5, count 0 2006.257.18:17:23.45#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:17:23.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:17:23.45#ibcon#[27=USB\r\n] 2006.257.18:17:23.45#ibcon#*before write, iclass 5, count 0 2006.257.18:17:23.45#ibcon#enter sib2, iclass 5, count 0 2006.257.18:17:23.45#ibcon#flushed, iclass 5, count 0 2006.257.18:17:23.45#ibcon#about to write, iclass 5, count 0 2006.257.18:17:23.45#ibcon#wrote, iclass 5, count 0 2006.257.18:17:23.45#ibcon#about to read 3, iclass 5, count 0 2006.257.18:17:23.48#ibcon#read 3, iclass 5, count 0 2006.257.18:17:23.48#ibcon#about to read 4, iclass 5, count 0 2006.257.18:17:23.48#ibcon#read 4, iclass 5, count 0 2006.257.18:17:23.48#ibcon#about to read 5, iclass 5, count 0 2006.257.18:17:23.48#ibcon#read 5, iclass 5, count 0 2006.257.18:17:23.48#ibcon#about to read 6, iclass 5, count 0 2006.257.18:17:23.48#ibcon#read 6, iclass 5, count 0 2006.257.18:17:23.48#ibcon#end of sib2, iclass 5, count 0 2006.257.18:17:23.48#ibcon#*after write, iclass 5, count 0 2006.257.18:17:23.48#ibcon#*before return 0, iclass 5, count 0 2006.257.18:17:23.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:23.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:17:23.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:17:23.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:17:23.48$vck44/vblo=8,744.99 2006.257.18:17:23.48#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.18:17:23.48#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.18:17:23.48#ibcon#ireg 17 cls_cnt 0 2006.257.18:17:23.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:23.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:23.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:23.48#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:17:23.48#ibcon#first serial, iclass 7, count 0 2006.257.18:17:23.48#ibcon#enter sib2, iclass 7, count 0 2006.257.18:17:23.48#ibcon#flushed, iclass 7, count 0 2006.257.18:17:23.48#ibcon#about to write, iclass 7, count 0 2006.257.18:17:23.48#ibcon#wrote, iclass 7, count 0 2006.257.18:17:23.48#ibcon#about to read 3, iclass 7, count 0 2006.257.18:17:23.50#ibcon#read 3, iclass 7, count 0 2006.257.18:17:23.50#ibcon#about to read 4, iclass 7, count 0 2006.257.18:17:23.50#ibcon#read 4, iclass 7, count 0 2006.257.18:17:23.50#ibcon#about to read 5, iclass 7, count 0 2006.257.18:17:23.50#ibcon#read 5, iclass 7, count 0 2006.257.18:17:23.50#ibcon#about to read 6, iclass 7, count 0 2006.257.18:17:23.50#ibcon#read 6, iclass 7, count 0 2006.257.18:17:23.50#ibcon#end of sib2, iclass 7, count 0 2006.257.18:17:23.50#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:17:23.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:17:23.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:17:23.50#ibcon#*before write, iclass 7, count 0 2006.257.18:17:23.50#ibcon#enter sib2, iclass 7, count 0 2006.257.18:17:23.50#ibcon#flushed, iclass 7, count 0 2006.257.18:17:23.50#ibcon#about to write, iclass 7, count 0 2006.257.18:17:23.50#ibcon#wrote, iclass 7, count 0 2006.257.18:17:23.50#ibcon#about to read 3, iclass 7, count 0 2006.257.18:17:23.54#ibcon#read 3, iclass 7, count 0 2006.257.18:17:23.54#ibcon#about to read 4, iclass 7, count 0 2006.257.18:17:23.54#ibcon#read 4, iclass 7, count 0 2006.257.18:17:23.54#ibcon#about to read 5, iclass 7, count 0 2006.257.18:17:23.54#ibcon#read 5, iclass 7, count 0 2006.257.18:17:23.54#ibcon#about to read 6, iclass 7, count 0 2006.257.18:17:23.54#ibcon#read 6, iclass 7, count 0 2006.257.18:17:23.54#ibcon#end of sib2, iclass 7, count 0 2006.257.18:17:23.54#ibcon#*after write, iclass 7, count 0 2006.257.18:17:23.54#ibcon#*before return 0, iclass 7, count 0 2006.257.18:17:23.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:23.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:17:23.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:17:23.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:17:23.54$vck44/vb=8,4 2006.257.18:17:23.54#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.18:17:23.54#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.18:17:23.54#ibcon#ireg 11 cls_cnt 2 2006.257.18:17:23.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:23.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:23.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:23.60#ibcon#enter wrdev, iclass 11, count 2 2006.257.18:17:23.60#ibcon#first serial, iclass 11, count 2 2006.257.18:17:23.60#ibcon#enter sib2, iclass 11, count 2 2006.257.18:17:23.60#ibcon#flushed, iclass 11, count 2 2006.257.18:17:23.60#ibcon#about to write, iclass 11, count 2 2006.257.18:17:23.60#ibcon#wrote, iclass 11, count 2 2006.257.18:17:23.60#ibcon#about to read 3, iclass 11, count 2 2006.257.18:17:23.62#ibcon#read 3, iclass 11, count 2 2006.257.18:17:23.62#ibcon#about to read 4, iclass 11, count 2 2006.257.18:17:23.62#ibcon#read 4, iclass 11, count 2 2006.257.18:17:23.62#ibcon#about to read 5, iclass 11, count 2 2006.257.18:17:23.62#ibcon#read 5, iclass 11, count 2 2006.257.18:17:23.62#ibcon#about to read 6, iclass 11, count 2 2006.257.18:17:23.62#ibcon#read 6, iclass 11, count 2 2006.257.18:17:23.62#ibcon#end of sib2, iclass 11, count 2 2006.257.18:17:23.62#ibcon#*mode == 0, iclass 11, count 2 2006.257.18:17:23.62#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.18:17:23.62#ibcon#[27=AT08-04\r\n] 2006.257.18:17:23.62#ibcon#*before write, iclass 11, count 2 2006.257.18:17:23.62#ibcon#enter sib2, iclass 11, count 2 2006.257.18:17:23.62#ibcon#flushed, iclass 11, count 2 2006.257.18:17:23.62#ibcon#about to write, iclass 11, count 2 2006.257.18:17:23.62#ibcon#wrote, iclass 11, count 2 2006.257.18:17:23.62#ibcon#about to read 3, iclass 11, count 2 2006.257.18:17:23.65#ibcon#read 3, iclass 11, count 2 2006.257.18:17:23.65#ibcon#about to read 4, iclass 11, count 2 2006.257.18:17:23.65#ibcon#read 4, iclass 11, count 2 2006.257.18:17:23.65#ibcon#about to read 5, iclass 11, count 2 2006.257.18:17:23.65#ibcon#read 5, iclass 11, count 2 2006.257.18:17:23.65#ibcon#about to read 6, iclass 11, count 2 2006.257.18:17:23.65#ibcon#read 6, iclass 11, count 2 2006.257.18:17:23.65#ibcon#end of sib2, iclass 11, count 2 2006.257.18:17:23.65#ibcon#*after write, iclass 11, count 2 2006.257.18:17:23.65#ibcon#*before return 0, iclass 11, count 2 2006.257.18:17:23.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:23.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:17:23.65#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.18:17:23.65#ibcon#ireg 7 cls_cnt 0 2006.257.18:17:23.65#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:23.77#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:23.77#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:23.77#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:17:23.77#ibcon#first serial, iclass 11, count 0 2006.257.18:17:23.77#ibcon#enter sib2, iclass 11, count 0 2006.257.18:17:23.77#ibcon#flushed, iclass 11, count 0 2006.257.18:17:23.77#ibcon#about to write, iclass 11, count 0 2006.257.18:17:23.77#ibcon#wrote, iclass 11, count 0 2006.257.18:17:23.77#ibcon#about to read 3, iclass 11, count 0 2006.257.18:17:23.79#ibcon#read 3, iclass 11, count 0 2006.257.18:17:23.79#ibcon#about to read 4, iclass 11, count 0 2006.257.18:17:23.79#ibcon#read 4, iclass 11, count 0 2006.257.18:17:23.79#ibcon#about to read 5, iclass 11, count 0 2006.257.18:17:23.79#ibcon#read 5, iclass 11, count 0 2006.257.18:17:23.79#ibcon#about to read 6, iclass 11, count 0 2006.257.18:17:23.79#ibcon#read 6, iclass 11, count 0 2006.257.18:17:23.79#ibcon#end of sib2, iclass 11, count 0 2006.257.18:17:23.79#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:17:23.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:17:23.79#ibcon#[27=USB\r\n] 2006.257.18:17:23.79#ibcon#*before write, iclass 11, count 0 2006.257.18:17:23.79#ibcon#enter sib2, iclass 11, count 0 2006.257.18:17:23.79#ibcon#flushed, iclass 11, count 0 2006.257.18:17:23.79#ibcon#about to write, iclass 11, count 0 2006.257.18:17:23.79#ibcon#wrote, iclass 11, count 0 2006.257.18:17:23.79#ibcon#about to read 3, iclass 11, count 0 2006.257.18:17:23.82#ibcon#read 3, iclass 11, count 0 2006.257.18:17:23.82#ibcon#about to read 4, iclass 11, count 0 2006.257.18:17:23.82#ibcon#read 4, iclass 11, count 0 2006.257.18:17:23.82#ibcon#about to read 5, iclass 11, count 0 2006.257.18:17:23.82#ibcon#read 5, iclass 11, count 0 2006.257.18:17:23.82#ibcon#about to read 6, iclass 11, count 0 2006.257.18:17:23.82#ibcon#read 6, iclass 11, count 0 2006.257.18:17:23.82#ibcon#end of sib2, iclass 11, count 0 2006.257.18:17:23.82#ibcon#*after write, iclass 11, count 0 2006.257.18:17:23.82#ibcon#*before return 0, iclass 11, count 0 2006.257.18:17:23.82#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:23.82#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:17:23.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:17:23.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:17:23.82$vck44/vabw=wide 2006.257.18:17:23.82#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.18:17:23.82#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.18:17:23.82#ibcon#ireg 8 cls_cnt 0 2006.257.18:17:23.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:23.82#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:23.82#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:23.82#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:17:23.82#ibcon#first serial, iclass 13, count 0 2006.257.18:17:23.82#ibcon#enter sib2, iclass 13, count 0 2006.257.18:17:23.82#ibcon#flushed, iclass 13, count 0 2006.257.18:17:23.82#ibcon#about to write, iclass 13, count 0 2006.257.18:17:23.82#ibcon#wrote, iclass 13, count 0 2006.257.18:17:23.82#ibcon#about to read 3, iclass 13, count 0 2006.257.18:17:23.84#ibcon#read 3, iclass 13, count 0 2006.257.18:17:23.84#ibcon#about to read 4, iclass 13, count 0 2006.257.18:17:23.84#ibcon#read 4, iclass 13, count 0 2006.257.18:17:23.84#ibcon#about to read 5, iclass 13, count 0 2006.257.18:17:23.84#ibcon#read 5, iclass 13, count 0 2006.257.18:17:23.84#ibcon#about to read 6, iclass 13, count 0 2006.257.18:17:23.84#ibcon#read 6, iclass 13, count 0 2006.257.18:17:23.84#ibcon#end of sib2, iclass 13, count 0 2006.257.18:17:23.84#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:17:23.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:17:23.84#ibcon#[25=BW32\r\n] 2006.257.18:17:23.84#ibcon#*before write, iclass 13, count 0 2006.257.18:17:23.84#ibcon#enter sib2, iclass 13, count 0 2006.257.18:17:23.84#ibcon#flushed, iclass 13, count 0 2006.257.18:17:23.84#ibcon#about to write, iclass 13, count 0 2006.257.18:17:23.84#ibcon#wrote, iclass 13, count 0 2006.257.18:17:23.84#ibcon#about to read 3, iclass 13, count 0 2006.257.18:17:23.87#ibcon#read 3, iclass 13, count 0 2006.257.18:17:23.87#ibcon#about to read 4, iclass 13, count 0 2006.257.18:17:23.87#ibcon#read 4, iclass 13, count 0 2006.257.18:17:23.87#ibcon#about to read 5, iclass 13, count 0 2006.257.18:17:23.87#ibcon#read 5, iclass 13, count 0 2006.257.18:17:23.87#ibcon#about to read 6, iclass 13, count 0 2006.257.18:17:23.87#ibcon#read 6, iclass 13, count 0 2006.257.18:17:23.87#ibcon#end of sib2, iclass 13, count 0 2006.257.18:17:23.87#ibcon#*after write, iclass 13, count 0 2006.257.18:17:23.87#ibcon#*before return 0, iclass 13, count 0 2006.257.18:17:23.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:23.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:17:23.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:17:23.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:17:23.87$vck44/vbbw=wide 2006.257.18:17:23.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.18:17:23.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.18:17:23.87#ibcon#ireg 8 cls_cnt 0 2006.257.18:17:23.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:17:23.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:17:23.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:17:23.94#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:17:23.94#ibcon#first serial, iclass 15, count 0 2006.257.18:17:23.94#ibcon#enter sib2, iclass 15, count 0 2006.257.18:17:23.94#ibcon#flushed, iclass 15, count 0 2006.257.18:17:23.94#ibcon#about to write, iclass 15, count 0 2006.257.18:17:23.94#ibcon#wrote, iclass 15, count 0 2006.257.18:17:23.94#ibcon#about to read 3, iclass 15, count 0 2006.257.18:17:23.96#ibcon#read 3, iclass 15, count 0 2006.257.18:17:23.96#ibcon#about to read 4, iclass 15, count 0 2006.257.18:17:23.96#ibcon#read 4, iclass 15, count 0 2006.257.18:17:23.96#ibcon#about to read 5, iclass 15, count 0 2006.257.18:17:23.96#ibcon#read 5, iclass 15, count 0 2006.257.18:17:23.96#ibcon#about to read 6, iclass 15, count 0 2006.257.18:17:23.96#ibcon#read 6, iclass 15, count 0 2006.257.18:17:23.96#ibcon#end of sib2, iclass 15, count 0 2006.257.18:17:23.96#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:17:23.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:17:23.96#ibcon#[27=BW32\r\n] 2006.257.18:17:23.96#ibcon#*before write, iclass 15, count 0 2006.257.18:17:23.96#ibcon#enter sib2, iclass 15, count 0 2006.257.18:17:23.96#ibcon#flushed, iclass 15, count 0 2006.257.18:17:23.96#ibcon#about to write, iclass 15, count 0 2006.257.18:17:23.96#ibcon#wrote, iclass 15, count 0 2006.257.18:17:23.96#ibcon#about to read 3, iclass 15, count 0 2006.257.18:17:23.99#ibcon#read 3, iclass 15, count 0 2006.257.18:17:23.99#ibcon#about to read 4, iclass 15, count 0 2006.257.18:17:23.99#ibcon#read 4, iclass 15, count 0 2006.257.18:17:23.99#ibcon#about to read 5, iclass 15, count 0 2006.257.18:17:23.99#ibcon#read 5, iclass 15, count 0 2006.257.18:17:23.99#ibcon#about to read 6, iclass 15, count 0 2006.257.18:17:23.99#ibcon#read 6, iclass 15, count 0 2006.257.18:17:23.99#ibcon#end of sib2, iclass 15, count 0 2006.257.18:17:23.99#ibcon#*after write, iclass 15, count 0 2006.257.18:17:23.99#ibcon#*before return 0, iclass 15, count 0 2006.257.18:17:23.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:17:23.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:17:23.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:17:23.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:17:23.99$setupk4/ifdk4 2006.257.18:17:23.99$ifdk4/lo= 2006.257.18:17:23.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:17:23.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:17:23.99$ifdk4/patch= 2006.257.18:17:23.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:17:23.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:17:23.99$setupk4/!*+20s 2006.257.18:17:25.08#abcon#<5=/14 1.3 3.1 17.25 981014.4\r\n> 2006.257.18:17:25.10#abcon#{5=INTERFACE CLEAR} 2006.257.18:17:25.16#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:17:35.25#abcon#<5=/14 1.3 3.0 17.25 981014.4\r\n> 2006.257.18:17:35.27#abcon#{5=INTERFACE CLEAR} 2006.257.18:17:35.33#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:17:38.50$setupk4/"tpicd 2006.257.18:17:38.50$setupk4/echo=off 2006.257.18:17:38.50$setupk4/xlog=off 2006.257.18:17:38.50:!2006.257.18:19:29 2006.257.18:18:11.13#trakl#Source acquired 2006.257.18:18:11.13#flagr#flagr/antenna,acquired 2006.257.18:19:29.00:preob 2006.257.18:19:30.13/onsource/TRACKING 2006.257.18:19:30.13:!2006.257.18:19:39 2006.257.18:19:39.00:"tape 2006.257.18:19:39.00:"st=record 2006.257.18:19:39.00:data_valid=on 2006.257.18:19:39.00:midob 2006.257.18:19:39.13/onsource/TRACKING 2006.257.18:19:39.13/wx/17.27,1014.4,97 2006.257.18:19:39.23/cable/+6.4848E-03 2006.257.18:19:40.32/va/01,08,usb,yes,40,42 2006.257.18:19:40.32/va/02,07,usb,yes,43,43 2006.257.18:19:40.32/va/03,08,usb,yes,39,41 2006.257.18:19:40.32/va/04,07,usb,yes,44,46 2006.257.18:19:40.32/va/05,04,usb,yes,40,40 2006.257.18:19:40.32/va/06,04,usb,yes,44,43 2006.257.18:19:40.32/va/07,04,usb,yes,45,45 2006.257.18:19:40.32/va/08,04,usb,yes,38,46 2006.257.18:19:40.55/valo/01,524.99,yes,locked 2006.257.18:19:40.55/valo/02,534.99,yes,locked 2006.257.18:19:40.55/valo/03,564.99,yes,locked 2006.257.18:19:40.55/valo/04,624.99,yes,locked 2006.257.18:19:40.55/valo/05,734.99,yes,locked 2006.257.18:19:40.55/valo/06,814.99,yes,locked 2006.257.18:19:40.55/valo/07,864.99,yes,locked 2006.257.18:19:40.55/valo/08,884.99,yes,locked 2006.257.18:19:41.64/vb/01,04,usb,yes,32,30 2006.257.18:19:41.64/vb/02,05,usb,yes,31,30 2006.257.18:19:41.64/vb/03,04,usb,yes,32,35 2006.257.18:19:41.64/vb/04,05,usb,yes,32,31 2006.257.18:19:41.64/vb/05,04,usb,yes,28,31 2006.257.18:19:41.64/vb/06,04,usb,yes,33,29 2006.257.18:19:41.64/vb/07,04,usb,yes,33,33 2006.257.18:19:41.64/vb/08,04,usb,yes,30,34 2006.257.18:19:41.88/vblo/01,629.99,yes,locked 2006.257.18:19:41.88/vblo/02,634.99,yes,locked 2006.257.18:19:41.88/vblo/03,649.99,yes,locked 2006.257.18:19:41.88/vblo/04,679.99,yes,locked 2006.257.18:19:41.88/vblo/05,709.99,yes,locked 2006.257.18:19:41.88/vblo/06,719.99,yes,locked 2006.257.18:19:41.88/vblo/07,734.99,yes,locked 2006.257.18:19:41.88/vblo/08,744.99,yes,locked 2006.257.18:19:42.03/vabw/8 2006.257.18:19:42.18/vbbw/8 2006.257.18:19:42.27/xfe/off,on,15.0 2006.257.18:19:42.65/ifatt/23,28,28,28 2006.257.18:19:43.07/fmout-gps/S +4.53E-07 2006.257.18:19:43.11:!2006.257.18:20:19 2006.257.18:20:19.01:data_valid=off 2006.257.18:20:19.01:"et 2006.257.18:20:19.01:!+3s 2006.257.18:20:22.02:"tape 2006.257.18:20:22.02:postob 2006.257.18:20:22.11/cable/+6.4868E-03 2006.257.18:20:22.11/wx/17.27,1014.4,97 2006.257.18:20:22.17/fmout-gps/S +4.53E-07 2006.257.18:20:22.17:scan_name=257-1821,jd0609,130 2006.257.18:20:22.17:source=2136+141,213901.31,142336.0,2000.0,cw 2006.257.18:20:24.14#flagr#flagr/antenna,new-source 2006.257.18:20:24.14:checkk5 2006.257.18:20:24.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:20:24.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:20:25.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:20:25.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:20:25.83/chk_obsdata//k5ts1/T2571819??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.18:20:26.16/chk_obsdata//k5ts2/T2571819??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.18:20:26.51/chk_obsdata//k5ts3/T2571819??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.18:20:26.85/chk_obsdata//k5ts4/T2571819??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.18:20:27.51/k5log//k5ts1_log_newline 2006.257.18:20:28.18/k5log//k5ts2_log_newline 2006.257.18:20:28.83/k5log//k5ts3_log_newline 2006.257.18:20:29.48/k5log//k5ts4_log_newline 2006.257.18:20:29.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:20:29.51:setupk4=1 2006.257.18:20:29.51$setupk4/echo=on 2006.257.18:20:29.51$setupk4/pcalon 2006.257.18:20:29.51$pcalon/"no phase cal control is implemented here 2006.257.18:20:29.51$setupk4/"tpicd=stop 2006.257.18:20:29.51$setupk4/"rec=synch_on 2006.257.18:20:29.51$setupk4/"rec_mode=128 2006.257.18:20:29.51$setupk4/!* 2006.257.18:20:29.51$setupk4/recpk4 2006.257.18:20:29.51$recpk4/recpatch= 2006.257.18:20:29.51$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:20:29.51$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:20:29.51$setupk4/vck44 2006.257.18:20:29.51$vck44/valo=1,524.99 2006.257.18:20:29.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.18:20:29.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.18:20:29.51#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:29.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:29.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:29.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:29.51#ibcon#enter wrdev, iclass 24, count 0 2006.257.18:20:29.51#ibcon#first serial, iclass 24, count 0 2006.257.18:20:29.51#ibcon#enter sib2, iclass 24, count 0 2006.257.18:20:29.51#ibcon#flushed, iclass 24, count 0 2006.257.18:20:29.51#ibcon#about to write, iclass 24, count 0 2006.257.18:20:29.51#ibcon#wrote, iclass 24, count 0 2006.257.18:20:29.51#ibcon#about to read 3, iclass 24, count 0 2006.257.18:20:29.53#ibcon#read 3, iclass 24, count 0 2006.257.18:20:29.53#ibcon#about to read 4, iclass 24, count 0 2006.257.18:20:29.53#ibcon#read 4, iclass 24, count 0 2006.257.18:20:29.53#ibcon#about to read 5, iclass 24, count 0 2006.257.18:20:29.53#ibcon#read 5, iclass 24, count 0 2006.257.18:20:29.53#ibcon#about to read 6, iclass 24, count 0 2006.257.18:20:29.53#ibcon#read 6, iclass 24, count 0 2006.257.18:20:29.53#ibcon#end of sib2, iclass 24, count 0 2006.257.18:20:29.53#ibcon#*mode == 0, iclass 24, count 0 2006.257.18:20:29.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.18:20:29.53#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:20:29.53#ibcon#*before write, iclass 24, count 0 2006.257.18:20:29.53#ibcon#enter sib2, iclass 24, count 0 2006.257.18:20:29.53#ibcon#flushed, iclass 24, count 0 2006.257.18:20:29.53#ibcon#about to write, iclass 24, count 0 2006.257.18:20:29.53#ibcon#wrote, iclass 24, count 0 2006.257.18:20:29.53#ibcon#about to read 3, iclass 24, count 0 2006.257.18:20:29.58#ibcon#read 3, iclass 24, count 0 2006.257.18:20:29.58#ibcon#about to read 4, iclass 24, count 0 2006.257.18:20:29.58#ibcon#read 4, iclass 24, count 0 2006.257.18:20:29.58#ibcon#about to read 5, iclass 24, count 0 2006.257.18:20:29.58#ibcon#read 5, iclass 24, count 0 2006.257.18:20:29.58#ibcon#about to read 6, iclass 24, count 0 2006.257.18:20:29.58#ibcon#read 6, iclass 24, count 0 2006.257.18:20:29.58#ibcon#end of sib2, iclass 24, count 0 2006.257.18:20:29.58#ibcon#*after write, iclass 24, count 0 2006.257.18:20:29.58#ibcon#*before return 0, iclass 24, count 0 2006.257.18:20:29.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:29.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:29.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.18:20:29.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.18:20:29.58$vck44/va=1,8 2006.257.18:20:29.58#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.18:20:29.58#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.18:20:29.58#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:29.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:29.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:29.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:29.58#ibcon#enter wrdev, iclass 26, count 2 2006.257.18:20:29.58#ibcon#first serial, iclass 26, count 2 2006.257.18:20:29.58#ibcon#enter sib2, iclass 26, count 2 2006.257.18:20:29.58#ibcon#flushed, iclass 26, count 2 2006.257.18:20:29.58#ibcon#about to write, iclass 26, count 2 2006.257.18:20:29.58#ibcon#wrote, iclass 26, count 2 2006.257.18:20:29.58#ibcon#about to read 3, iclass 26, count 2 2006.257.18:20:29.60#ibcon#read 3, iclass 26, count 2 2006.257.18:20:29.60#ibcon#about to read 4, iclass 26, count 2 2006.257.18:20:29.60#ibcon#read 4, iclass 26, count 2 2006.257.18:20:29.60#ibcon#about to read 5, iclass 26, count 2 2006.257.18:20:29.60#ibcon#read 5, iclass 26, count 2 2006.257.18:20:29.60#ibcon#about to read 6, iclass 26, count 2 2006.257.18:20:29.60#ibcon#read 6, iclass 26, count 2 2006.257.18:20:29.60#ibcon#end of sib2, iclass 26, count 2 2006.257.18:20:29.60#ibcon#*mode == 0, iclass 26, count 2 2006.257.18:20:29.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.18:20:29.60#ibcon#[25=AT01-08\r\n] 2006.257.18:20:29.60#ibcon#*before write, iclass 26, count 2 2006.257.18:20:29.60#ibcon#enter sib2, iclass 26, count 2 2006.257.18:20:29.60#ibcon#flushed, iclass 26, count 2 2006.257.18:20:29.60#ibcon#about to write, iclass 26, count 2 2006.257.18:20:29.60#ibcon#wrote, iclass 26, count 2 2006.257.18:20:29.60#ibcon#about to read 3, iclass 26, count 2 2006.257.18:20:29.63#ibcon#read 3, iclass 26, count 2 2006.257.18:20:29.63#ibcon#about to read 4, iclass 26, count 2 2006.257.18:20:29.63#ibcon#read 4, iclass 26, count 2 2006.257.18:20:29.63#ibcon#about to read 5, iclass 26, count 2 2006.257.18:20:29.63#ibcon#read 5, iclass 26, count 2 2006.257.18:20:29.63#ibcon#about to read 6, iclass 26, count 2 2006.257.18:20:29.63#ibcon#read 6, iclass 26, count 2 2006.257.18:20:29.63#ibcon#end of sib2, iclass 26, count 2 2006.257.18:20:29.63#ibcon#*after write, iclass 26, count 2 2006.257.18:20:29.63#ibcon#*before return 0, iclass 26, count 2 2006.257.18:20:29.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:29.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:29.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.18:20:29.63#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:29.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:29.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:29.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:29.75#ibcon#enter wrdev, iclass 26, count 0 2006.257.18:20:29.75#ibcon#first serial, iclass 26, count 0 2006.257.18:20:29.75#ibcon#enter sib2, iclass 26, count 0 2006.257.18:20:29.75#ibcon#flushed, iclass 26, count 0 2006.257.18:20:29.75#ibcon#about to write, iclass 26, count 0 2006.257.18:20:29.75#ibcon#wrote, iclass 26, count 0 2006.257.18:20:29.75#ibcon#about to read 3, iclass 26, count 0 2006.257.18:20:29.77#ibcon#read 3, iclass 26, count 0 2006.257.18:20:29.77#ibcon#about to read 4, iclass 26, count 0 2006.257.18:20:29.77#ibcon#read 4, iclass 26, count 0 2006.257.18:20:29.77#ibcon#about to read 5, iclass 26, count 0 2006.257.18:20:29.77#ibcon#read 5, iclass 26, count 0 2006.257.18:20:29.77#ibcon#about to read 6, iclass 26, count 0 2006.257.18:20:29.77#ibcon#read 6, iclass 26, count 0 2006.257.18:20:29.77#ibcon#end of sib2, iclass 26, count 0 2006.257.18:20:29.77#ibcon#*mode == 0, iclass 26, count 0 2006.257.18:20:29.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.18:20:29.77#ibcon#[25=USB\r\n] 2006.257.18:20:29.77#ibcon#*before write, iclass 26, count 0 2006.257.18:20:29.77#ibcon#enter sib2, iclass 26, count 0 2006.257.18:20:29.77#ibcon#flushed, iclass 26, count 0 2006.257.18:20:29.77#ibcon#about to write, iclass 26, count 0 2006.257.18:20:29.77#ibcon#wrote, iclass 26, count 0 2006.257.18:20:29.77#ibcon#about to read 3, iclass 26, count 0 2006.257.18:20:29.80#ibcon#read 3, iclass 26, count 0 2006.257.18:20:29.80#ibcon#about to read 4, iclass 26, count 0 2006.257.18:20:29.80#ibcon#read 4, iclass 26, count 0 2006.257.18:20:29.80#ibcon#about to read 5, iclass 26, count 0 2006.257.18:20:29.80#ibcon#read 5, iclass 26, count 0 2006.257.18:20:29.80#ibcon#about to read 6, iclass 26, count 0 2006.257.18:20:29.80#ibcon#read 6, iclass 26, count 0 2006.257.18:20:29.80#ibcon#end of sib2, iclass 26, count 0 2006.257.18:20:29.80#ibcon#*after write, iclass 26, count 0 2006.257.18:20:29.80#ibcon#*before return 0, iclass 26, count 0 2006.257.18:20:29.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:29.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:29.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.18:20:29.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.18:20:29.80$vck44/valo=2,534.99 2006.257.18:20:29.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.18:20:29.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.18:20:29.80#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:29.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:29.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:29.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:29.80#ibcon#enter wrdev, iclass 28, count 0 2006.257.18:20:29.80#ibcon#first serial, iclass 28, count 0 2006.257.18:20:29.80#ibcon#enter sib2, iclass 28, count 0 2006.257.18:20:29.80#ibcon#flushed, iclass 28, count 0 2006.257.18:20:29.80#ibcon#about to write, iclass 28, count 0 2006.257.18:20:29.80#ibcon#wrote, iclass 28, count 0 2006.257.18:20:29.80#ibcon#about to read 3, iclass 28, count 0 2006.257.18:20:29.82#ibcon#read 3, iclass 28, count 0 2006.257.18:20:29.82#ibcon#about to read 4, iclass 28, count 0 2006.257.18:20:29.82#ibcon#read 4, iclass 28, count 0 2006.257.18:20:29.82#ibcon#about to read 5, iclass 28, count 0 2006.257.18:20:29.82#ibcon#read 5, iclass 28, count 0 2006.257.18:20:29.82#ibcon#about to read 6, iclass 28, count 0 2006.257.18:20:29.82#ibcon#read 6, iclass 28, count 0 2006.257.18:20:29.82#ibcon#end of sib2, iclass 28, count 0 2006.257.18:20:29.82#ibcon#*mode == 0, iclass 28, count 0 2006.257.18:20:29.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.18:20:29.82#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:20:29.82#ibcon#*before write, iclass 28, count 0 2006.257.18:20:29.82#ibcon#enter sib2, iclass 28, count 0 2006.257.18:20:29.82#ibcon#flushed, iclass 28, count 0 2006.257.18:20:29.82#ibcon#about to write, iclass 28, count 0 2006.257.18:20:29.82#ibcon#wrote, iclass 28, count 0 2006.257.18:20:29.82#ibcon#about to read 3, iclass 28, count 0 2006.257.18:20:29.86#ibcon#read 3, iclass 28, count 0 2006.257.18:20:29.86#ibcon#about to read 4, iclass 28, count 0 2006.257.18:20:29.86#ibcon#read 4, iclass 28, count 0 2006.257.18:20:29.86#ibcon#about to read 5, iclass 28, count 0 2006.257.18:20:29.86#ibcon#read 5, iclass 28, count 0 2006.257.18:20:29.86#ibcon#about to read 6, iclass 28, count 0 2006.257.18:20:29.86#ibcon#read 6, iclass 28, count 0 2006.257.18:20:29.86#ibcon#end of sib2, iclass 28, count 0 2006.257.18:20:29.86#ibcon#*after write, iclass 28, count 0 2006.257.18:20:29.86#ibcon#*before return 0, iclass 28, count 0 2006.257.18:20:29.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:29.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:29.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.18:20:29.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.18:20:29.86$vck44/va=2,7 2006.257.18:20:29.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.18:20:29.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.18:20:29.86#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:29.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:29.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:29.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:29.92#ibcon#enter wrdev, iclass 30, count 2 2006.257.18:20:29.92#ibcon#first serial, iclass 30, count 2 2006.257.18:20:29.92#ibcon#enter sib2, iclass 30, count 2 2006.257.18:20:29.92#ibcon#flushed, iclass 30, count 2 2006.257.18:20:29.92#ibcon#about to write, iclass 30, count 2 2006.257.18:20:29.92#ibcon#wrote, iclass 30, count 2 2006.257.18:20:29.92#ibcon#about to read 3, iclass 30, count 2 2006.257.18:20:29.94#ibcon#read 3, iclass 30, count 2 2006.257.18:20:29.94#ibcon#about to read 4, iclass 30, count 2 2006.257.18:20:29.94#ibcon#read 4, iclass 30, count 2 2006.257.18:20:29.94#ibcon#about to read 5, iclass 30, count 2 2006.257.18:20:29.94#ibcon#read 5, iclass 30, count 2 2006.257.18:20:29.94#ibcon#about to read 6, iclass 30, count 2 2006.257.18:20:29.94#ibcon#read 6, iclass 30, count 2 2006.257.18:20:29.94#ibcon#end of sib2, iclass 30, count 2 2006.257.18:20:29.94#ibcon#*mode == 0, iclass 30, count 2 2006.257.18:20:29.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.18:20:29.94#ibcon#[25=AT02-07\r\n] 2006.257.18:20:29.94#ibcon#*before write, iclass 30, count 2 2006.257.18:20:29.94#ibcon#enter sib2, iclass 30, count 2 2006.257.18:20:29.94#ibcon#flushed, iclass 30, count 2 2006.257.18:20:29.94#ibcon#about to write, iclass 30, count 2 2006.257.18:20:29.94#ibcon#wrote, iclass 30, count 2 2006.257.18:20:29.94#ibcon#about to read 3, iclass 30, count 2 2006.257.18:20:29.97#ibcon#read 3, iclass 30, count 2 2006.257.18:20:29.97#ibcon#about to read 4, iclass 30, count 2 2006.257.18:20:29.97#ibcon#read 4, iclass 30, count 2 2006.257.18:20:29.97#ibcon#about to read 5, iclass 30, count 2 2006.257.18:20:29.97#ibcon#read 5, iclass 30, count 2 2006.257.18:20:29.97#ibcon#about to read 6, iclass 30, count 2 2006.257.18:20:29.97#ibcon#read 6, iclass 30, count 2 2006.257.18:20:29.97#ibcon#end of sib2, iclass 30, count 2 2006.257.18:20:29.97#ibcon#*after write, iclass 30, count 2 2006.257.18:20:29.97#ibcon#*before return 0, iclass 30, count 2 2006.257.18:20:29.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:29.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:29.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.18:20:29.97#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:29.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:30.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:30.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:30.09#ibcon#enter wrdev, iclass 30, count 0 2006.257.18:20:30.09#ibcon#first serial, iclass 30, count 0 2006.257.18:20:30.09#ibcon#enter sib2, iclass 30, count 0 2006.257.18:20:30.09#ibcon#flushed, iclass 30, count 0 2006.257.18:20:30.09#ibcon#about to write, iclass 30, count 0 2006.257.18:20:30.09#ibcon#wrote, iclass 30, count 0 2006.257.18:20:30.09#ibcon#about to read 3, iclass 30, count 0 2006.257.18:20:30.11#ibcon#read 3, iclass 30, count 0 2006.257.18:20:30.11#ibcon#about to read 4, iclass 30, count 0 2006.257.18:20:30.11#ibcon#read 4, iclass 30, count 0 2006.257.18:20:30.11#ibcon#about to read 5, iclass 30, count 0 2006.257.18:20:30.11#ibcon#read 5, iclass 30, count 0 2006.257.18:20:30.11#ibcon#about to read 6, iclass 30, count 0 2006.257.18:20:30.11#ibcon#read 6, iclass 30, count 0 2006.257.18:20:30.11#ibcon#end of sib2, iclass 30, count 0 2006.257.18:20:30.11#ibcon#*mode == 0, iclass 30, count 0 2006.257.18:20:30.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.18:20:30.11#ibcon#[25=USB\r\n] 2006.257.18:20:30.11#ibcon#*before write, iclass 30, count 0 2006.257.18:20:30.11#ibcon#enter sib2, iclass 30, count 0 2006.257.18:20:30.11#ibcon#flushed, iclass 30, count 0 2006.257.18:20:30.11#ibcon#about to write, iclass 30, count 0 2006.257.18:20:30.11#ibcon#wrote, iclass 30, count 0 2006.257.18:20:30.11#ibcon#about to read 3, iclass 30, count 0 2006.257.18:20:30.14#ibcon#read 3, iclass 30, count 0 2006.257.18:20:30.14#ibcon#about to read 4, iclass 30, count 0 2006.257.18:20:30.14#ibcon#read 4, iclass 30, count 0 2006.257.18:20:30.14#ibcon#about to read 5, iclass 30, count 0 2006.257.18:20:30.14#ibcon#read 5, iclass 30, count 0 2006.257.18:20:30.14#ibcon#about to read 6, iclass 30, count 0 2006.257.18:20:30.14#ibcon#read 6, iclass 30, count 0 2006.257.18:20:30.14#ibcon#end of sib2, iclass 30, count 0 2006.257.18:20:30.14#ibcon#*after write, iclass 30, count 0 2006.257.18:20:30.14#ibcon#*before return 0, iclass 30, count 0 2006.257.18:20:30.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:30.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:30.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.18:20:30.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.18:20:30.14$vck44/valo=3,564.99 2006.257.18:20:30.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.18:20:30.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.18:20:30.14#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:30.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:30.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:30.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:30.14#ibcon#enter wrdev, iclass 32, count 0 2006.257.18:20:30.14#ibcon#first serial, iclass 32, count 0 2006.257.18:20:30.14#ibcon#enter sib2, iclass 32, count 0 2006.257.18:20:30.14#ibcon#flushed, iclass 32, count 0 2006.257.18:20:30.14#ibcon#about to write, iclass 32, count 0 2006.257.18:20:30.14#ibcon#wrote, iclass 32, count 0 2006.257.18:20:30.14#ibcon#about to read 3, iclass 32, count 0 2006.257.18:20:30.16#ibcon#read 3, iclass 32, count 0 2006.257.18:20:30.16#ibcon#about to read 4, iclass 32, count 0 2006.257.18:20:30.16#ibcon#read 4, iclass 32, count 0 2006.257.18:20:30.16#ibcon#about to read 5, iclass 32, count 0 2006.257.18:20:30.16#ibcon#read 5, iclass 32, count 0 2006.257.18:20:30.16#ibcon#about to read 6, iclass 32, count 0 2006.257.18:20:30.16#ibcon#read 6, iclass 32, count 0 2006.257.18:20:30.16#ibcon#end of sib2, iclass 32, count 0 2006.257.18:20:30.16#ibcon#*mode == 0, iclass 32, count 0 2006.257.18:20:30.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.18:20:30.16#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:20:30.16#ibcon#*before write, iclass 32, count 0 2006.257.18:20:30.16#ibcon#enter sib2, iclass 32, count 0 2006.257.18:20:30.16#ibcon#flushed, iclass 32, count 0 2006.257.18:20:30.16#ibcon#about to write, iclass 32, count 0 2006.257.18:20:30.16#ibcon#wrote, iclass 32, count 0 2006.257.18:20:30.16#ibcon#about to read 3, iclass 32, count 0 2006.257.18:20:30.20#ibcon#read 3, iclass 32, count 0 2006.257.18:20:30.20#ibcon#about to read 4, iclass 32, count 0 2006.257.18:20:30.20#ibcon#read 4, iclass 32, count 0 2006.257.18:20:30.20#ibcon#about to read 5, iclass 32, count 0 2006.257.18:20:30.20#ibcon#read 5, iclass 32, count 0 2006.257.18:20:30.20#ibcon#about to read 6, iclass 32, count 0 2006.257.18:20:30.20#ibcon#read 6, iclass 32, count 0 2006.257.18:20:30.20#ibcon#end of sib2, iclass 32, count 0 2006.257.18:20:30.20#ibcon#*after write, iclass 32, count 0 2006.257.18:20:30.20#ibcon#*before return 0, iclass 32, count 0 2006.257.18:20:30.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:30.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:30.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.18:20:30.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.18:20:30.20$vck44/va=3,8 2006.257.18:20:30.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.18:20:30.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.18:20:30.20#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:30.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:30.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:30.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:30.26#ibcon#enter wrdev, iclass 34, count 2 2006.257.18:20:30.26#ibcon#first serial, iclass 34, count 2 2006.257.18:20:30.26#ibcon#enter sib2, iclass 34, count 2 2006.257.18:20:30.26#ibcon#flushed, iclass 34, count 2 2006.257.18:20:30.26#ibcon#about to write, iclass 34, count 2 2006.257.18:20:30.26#ibcon#wrote, iclass 34, count 2 2006.257.18:20:30.26#ibcon#about to read 3, iclass 34, count 2 2006.257.18:20:30.28#ibcon#read 3, iclass 34, count 2 2006.257.18:20:30.28#ibcon#about to read 4, iclass 34, count 2 2006.257.18:20:30.28#ibcon#read 4, iclass 34, count 2 2006.257.18:20:30.28#ibcon#about to read 5, iclass 34, count 2 2006.257.18:20:30.28#ibcon#read 5, iclass 34, count 2 2006.257.18:20:30.28#ibcon#about to read 6, iclass 34, count 2 2006.257.18:20:30.28#ibcon#read 6, iclass 34, count 2 2006.257.18:20:30.28#ibcon#end of sib2, iclass 34, count 2 2006.257.18:20:30.28#ibcon#*mode == 0, iclass 34, count 2 2006.257.18:20:30.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.18:20:30.28#ibcon#[25=AT03-08\r\n] 2006.257.18:20:30.28#ibcon#*before write, iclass 34, count 2 2006.257.18:20:30.28#ibcon#enter sib2, iclass 34, count 2 2006.257.18:20:30.28#ibcon#flushed, iclass 34, count 2 2006.257.18:20:30.28#ibcon#about to write, iclass 34, count 2 2006.257.18:20:30.28#ibcon#wrote, iclass 34, count 2 2006.257.18:20:30.28#ibcon#about to read 3, iclass 34, count 2 2006.257.18:20:30.31#ibcon#read 3, iclass 34, count 2 2006.257.18:20:30.31#ibcon#about to read 4, iclass 34, count 2 2006.257.18:20:30.31#ibcon#read 4, iclass 34, count 2 2006.257.18:20:30.31#ibcon#about to read 5, iclass 34, count 2 2006.257.18:20:30.31#ibcon#read 5, iclass 34, count 2 2006.257.18:20:30.31#ibcon#about to read 6, iclass 34, count 2 2006.257.18:20:30.31#ibcon#read 6, iclass 34, count 2 2006.257.18:20:30.31#ibcon#end of sib2, iclass 34, count 2 2006.257.18:20:30.31#ibcon#*after write, iclass 34, count 2 2006.257.18:20:30.31#ibcon#*before return 0, iclass 34, count 2 2006.257.18:20:30.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:30.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:30.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.18:20:30.31#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:30.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:30.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:30.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:30.43#ibcon#enter wrdev, iclass 34, count 0 2006.257.18:20:30.43#ibcon#first serial, iclass 34, count 0 2006.257.18:20:30.43#ibcon#enter sib2, iclass 34, count 0 2006.257.18:20:30.43#ibcon#flushed, iclass 34, count 0 2006.257.18:20:30.43#ibcon#about to write, iclass 34, count 0 2006.257.18:20:30.43#ibcon#wrote, iclass 34, count 0 2006.257.18:20:30.43#ibcon#about to read 3, iclass 34, count 0 2006.257.18:20:30.45#ibcon#read 3, iclass 34, count 0 2006.257.18:20:30.45#ibcon#about to read 4, iclass 34, count 0 2006.257.18:20:30.45#ibcon#read 4, iclass 34, count 0 2006.257.18:20:30.45#ibcon#about to read 5, iclass 34, count 0 2006.257.18:20:30.45#ibcon#read 5, iclass 34, count 0 2006.257.18:20:30.45#ibcon#about to read 6, iclass 34, count 0 2006.257.18:20:30.45#ibcon#read 6, iclass 34, count 0 2006.257.18:20:30.45#ibcon#end of sib2, iclass 34, count 0 2006.257.18:20:30.45#ibcon#*mode == 0, iclass 34, count 0 2006.257.18:20:30.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.18:20:30.45#ibcon#[25=USB\r\n] 2006.257.18:20:30.45#ibcon#*before write, iclass 34, count 0 2006.257.18:20:30.45#ibcon#enter sib2, iclass 34, count 0 2006.257.18:20:30.45#ibcon#flushed, iclass 34, count 0 2006.257.18:20:30.45#ibcon#about to write, iclass 34, count 0 2006.257.18:20:30.45#ibcon#wrote, iclass 34, count 0 2006.257.18:20:30.45#ibcon#about to read 3, iclass 34, count 0 2006.257.18:20:30.48#ibcon#read 3, iclass 34, count 0 2006.257.18:20:30.48#ibcon#about to read 4, iclass 34, count 0 2006.257.18:20:30.48#ibcon#read 4, iclass 34, count 0 2006.257.18:20:30.48#ibcon#about to read 5, iclass 34, count 0 2006.257.18:20:30.48#ibcon#read 5, iclass 34, count 0 2006.257.18:20:30.48#ibcon#about to read 6, iclass 34, count 0 2006.257.18:20:30.48#ibcon#read 6, iclass 34, count 0 2006.257.18:20:30.48#ibcon#end of sib2, iclass 34, count 0 2006.257.18:20:30.48#ibcon#*after write, iclass 34, count 0 2006.257.18:20:30.48#ibcon#*before return 0, iclass 34, count 0 2006.257.18:20:30.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:30.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:30.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.18:20:30.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.18:20:30.48$vck44/valo=4,624.99 2006.257.18:20:30.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.18:20:30.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.18:20:30.48#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:30.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:30.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:30.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:30.48#ibcon#enter wrdev, iclass 36, count 0 2006.257.18:20:30.48#ibcon#first serial, iclass 36, count 0 2006.257.18:20:30.48#ibcon#enter sib2, iclass 36, count 0 2006.257.18:20:30.48#ibcon#flushed, iclass 36, count 0 2006.257.18:20:30.48#ibcon#about to write, iclass 36, count 0 2006.257.18:20:30.48#ibcon#wrote, iclass 36, count 0 2006.257.18:20:30.48#ibcon#about to read 3, iclass 36, count 0 2006.257.18:20:30.50#ibcon#read 3, iclass 36, count 0 2006.257.18:20:30.50#ibcon#about to read 4, iclass 36, count 0 2006.257.18:20:30.50#ibcon#read 4, iclass 36, count 0 2006.257.18:20:30.50#ibcon#about to read 5, iclass 36, count 0 2006.257.18:20:30.50#ibcon#read 5, iclass 36, count 0 2006.257.18:20:30.50#ibcon#about to read 6, iclass 36, count 0 2006.257.18:20:30.50#ibcon#read 6, iclass 36, count 0 2006.257.18:20:30.50#ibcon#end of sib2, iclass 36, count 0 2006.257.18:20:30.50#ibcon#*mode == 0, iclass 36, count 0 2006.257.18:20:30.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.18:20:30.50#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:20:30.50#ibcon#*before write, iclass 36, count 0 2006.257.18:20:30.50#ibcon#enter sib2, iclass 36, count 0 2006.257.18:20:30.50#ibcon#flushed, iclass 36, count 0 2006.257.18:20:30.50#ibcon#about to write, iclass 36, count 0 2006.257.18:20:30.50#ibcon#wrote, iclass 36, count 0 2006.257.18:20:30.50#ibcon#about to read 3, iclass 36, count 0 2006.257.18:20:30.54#ibcon#read 3, iclass 36, count 0 2006.257.18:20:30.54#ibcon#about to read 4, iclass 36, count 0 2006.257.18:20:30.54#ibcon#read 4, iclass 36, count 0 2006.257.18:20:30.54#ibcon#about to read 5, iclass 36, count 0 2006.257.18:20:30.54#ibcon#read 5, iclass 36, count 0 2006.257.18:20:30.54#ibcon#about to read 6, iclass 36, count 0 2006.257.18:20:30.54#ibcon#read 6, iclass 36, count 0 2006.257.18:20:30.54#ibcon#end of sib2, iclass 36, count 0 2006.257.18:20:30.54#ibcon#*after write, iclass 36, count 0 2006.257.18:20:30.54#ibcon#*before return 0, iclass 36, count 0 2006.257.18:20:30.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:30.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:30.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.18:20:30.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.18:20:30.54$vck44/va=4,7 2006.257.18:20:30.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.18:20:30.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.18:20:30.54#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:30.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:30.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:30.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:30.60#ibcon#enter wrdev, iclass 38, count 2 2006.257.18:20:30.60#ibcon#first serial, iclass 38, count 2 2006.257.18:20:30.60#ibcon#enter sib2, iclass 38, count 2 2006.257.18:20:30.60#ibcon#flushed, iclass 38, count 2 2006.257.18:20:30.60#ibcon#about to write, iclass 38, count 2 2006.257.18:20:30.60#ibcon#wrote, iclass 38, count 2 2006.257.18:20:30.60#ibcon#about to read 3, iclass 38, count 2 2006.257.18:20:30.62#ibcon#read 3, iclass 38, count 2 2006.257.18:20:30.62#ibcon#about to read 4, iclass 38, count 2 2006.257.18:20:30.62#ibcon#read 4, iclass 38, count 2 2006.257.18:20:30.62#ibcon#about to read 5, iclass 38, count 2 2006.257.18:20:30.62#ibcon#read 5, iclass 38, count 2 2006.257.18:20:30.62#ibcon#about to read 6, iclass 38, count 2 2006.257.18:20:30.62#ibcon#read 6, iclass 38, count 2 2006.257.18:20:30.62#ibcon#end of sib2, iclass 38, count 2 2006.257.18:20:30.62#ibcon#*mode == 0, iclass 38, count 2 2006.257.18:20:30.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.18:20:30.62#ibcon#[25=AT04-07\r\n] 2006.257.18:20:30.62#ibcon#*before write, iclass 38, count 2 2006.257.18:20:30.62#ibcon#enter sib2, iclass 38, count 2 2006.257.18:20:30.62#ibcon#flushed, iclass 38, count 2 2006.257.18:20:30.62#ibcon#about to write, iclass 38, count 2 2006.257.18:20:30.62#ibcon#wrote, iclass 38, count 2 2006.257.18:20:30.62#ibcon#about to read 3, iclass 38, count 2 2006.257.18:20:30.65#ibcon#read 3, iclass 38, count 2 2006.257.18:20:30.65#ibcon#about to read 4, iclass 38, count 2 2006.257.18:20:30.65#ibcon#read 4, iclass 38, count 2 2006.257.18:20:30.65#ibcon#about to read 5, iclass 38, count 2 2006.257.18:20:30.65#ibcon#read 5, iclass 38, count 2 2006.257.18:20:30.65#ibcon#about to read 6, iclass 38, count 2 2006.257.18:20:30.65#ibcon#read 6, iclass 38, count 2 2006.257.18:20:30.65#ibcon#end of sib2, iclass 38, count 2 2006.257.18:20:30.65#ibcon#*after write, iclass 38, count 2 2006.257.18:20:30.65#ibcon#*before return 0, iclass 38, count 2 2006.257.18:20:30.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:30.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:30.65#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.18:20:30.65#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:30.65#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:30.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:30.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:30.77#ibcon#enter wrdev, iclass 38, count 0 2006.257.18:20:30.77#ibcon#first serial, iclass 38, count 0 2006.257.18:20:30.77#ibcon#enter sib2, iclass 38, count 0 2006.257.18:20:30.77#ibcon#flushed, iclass 38, count 0 2006.257.18:20:30.77#ibcon#about to write, iclass 38, count 0 2006.257.18:20:30.77#ibcon#wrote, iclass 38, count 0 2006.257.18:20:30.77#ibcon#about to read 3, iclass 38, count 0 2006.257.18:20:30.79#ibcon#read 3, iclass 38, count 0 2006.257.18:20:30.79#ibcon#about to read 4, iclass 38, count 0 2006.257.18:20:30.79#ibcon#read 4, iclass 38, count 0 2006.257.18:20:30.79#ibcon#about to read 5, iclass 38, count 0 2006.257.18:20:30.79#ibcon#read 5, iclass 38, count 0 2006.257.18:20:30.79#ibcon#about to read 6, iclass 38, count 0 2006.257.18:20:30.79#ibcon#read 6, iclass 38, count 0 2006.257.18:20:30.79#ibcon#end of sib2, iclass 38, count 0 2006.257.18:20:30.79#ibcon#*mode == 0, iclass 38, count 0 2006.257.18:20:30.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.18:20:30.79#ibcon#[25=USB\r\n] 2006.257.18:20:30.79#ibcon#*before write, iclass 38, count 0 2006.257.18:20:30.79#ibcon#enter sib2, iclass 38, count 0 2006.257.18:20:30.79#ibcon#flushed, iclass 38, count 0 2006.257.18:20:30.79#ibcon#about to write, iclass 38, count 0 2006.257.18:20:30.79#ibcon#wrote, iclass 38, count 0 2006.257.18:20:30.79#ibcon#about to read 3, iclass 38, count 0 2006.257.18:20:30.82#ibcon#read 3, iclass 38, count 0 2006.257.18:20:30.82#ibcon#about to read 4, iclass 38, count 0 2006.257.18:20:30.82#ibcon#read 4, iclass 38, count 0 2006.257.18:20:30.82#ibcon#about to read 5, iclass 38, count 0 2006.257.18:20:30.82#ibcon#read 5, iclass 38, count 0 2006.257.18:20:30.82#ibcon#about to read 6, iclass 38, count 0 2006.257.18:20:30.82#ibcon#read 6, iclass 38, count 0 2006.257.18:20:30.82#ibcon#end of sib2, iclass 38, count 0 2006.257.18:20:30.82#ibcon#*after write, iclass 38, count 0 2006.257.18:20:30.82#ibcon#*before return 0, iclass 38, count 0 2006.257.18:20:30.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:30.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:30.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.18:20:30.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.18:20:30.82$vck44/valo=5,734.99 2006.257.18:20:30.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.18:20:30.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.18:20:30.82#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:30.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:30.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:30.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:30.82#ibcon#enter wrdev, iclass 40, count 0 2006.257.18:20:30.82#ibcon#first serial, iclass 40, count 0 2006.257.18:20:30.82#ibcon#enter sib2, iclass 40, count 0 2006.257.18:20:30.82#ibcon#flushed, iclass 40, count 0 2006.257.18:20:30.82#ibcon#about to write, iclass 40, count 0 2006.257.18:20:30.82#ibcon#wrote, iclass 40, count 0 2006.257.18:20:30.82#ibcon#about to read 3, iclass 40, count 0 2006.257.18:20:30.84#ibcon#read 3, iclass 40, count 0 2006.257.18:20:30.84#ibcon#about to read 4, iclass 40, count 0 2006.257.18:20:30.84#ibcon#read 4, iclass 40, count 0 2006.257.18:20:30.84#ibcon#about to read 5, iclass 40, count 0 2006.257.18:20:30.84#ibcon#read 5, iclass 40, count 0 2006.257.18:20:30.84#ibcon#about to read 6, iclass 40, count 0 2006.257.18:20:30.84#ibcon#read 6, iclass 40, count 0 2006.257.18:20:30.84#ibcon#end of sib2, iclass 40, count 0 2006.257.18:20:30.84#ibcon#*mode == 0, iclass 40, count 0 2006.257.18:20:30.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.18:20:30.84#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:20:30.84#ibcon#*before write, iclass 40, count 0 2006.257.18:20:30.84#ibcon#enter sib2, iclass 40, count 0 2006.257.18:20:30.84#ibcon#flushed, iclass 40, count 0 2006.257.18:20:30.84#ibcon#about to write, iclass 40, count 0 2006.257.18:20:30.84#ibcon#wrote, iclass 40, count 0 2006.257.18:20:30.84#ibcon#about to read 3, iclass 40, count 0 2006.257.18:20:30.88#ibcon#read 3, iclass 40, count 0 2006.257.18:20:30.88#ibcon#about to read 4, iclass 40, count 0 2006.257.18:20:30.88#ibcon#read 4, iclass 40, count 0 2006.257.18:20:30.88#ibcon#about to read 5, iclass 40, count 0 2006.257.18:20:30.88#ibcon#read 5, iclass 40, count 0 2006.257.18:20:30.88#ibcon#about to read 6, iclass 40, count 0 2006.257.18:20:30.88#ibcon#read 6, iclass 40, count 0 2006.257.18:20:30.88#ibcon#end of sib2, iclass 40, count 0 2006.257.18:20:30.88#ibcon#*after write, iclass 40, count 0 2006.257.18:20:30.88#ibcon#*before return 0, iclass 40, count 0 2006.257.18:20:30.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:30.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:30.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.18:20:30.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.18:20:30.88$vck44/va=5,4 2006.257.18:20:30.88#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.18:20:30.88#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.18:20:30.88#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:30.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:30.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:30.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:30.94#ibcon#enter wrdev, iclass 4, count 2 2006.257.18:20:30.94#ibcon#first serial, iclass 4, count 2 2006.257.18:20:30.94#ibcon#enter sib2, iclass 4, count 2 2006.257.18:20:30.94#ibcon#flushed, iclass 4, count 2 2006.257.18:20:30.94#ibcon#about to write, iclass 4, count 2 2006.257.18:20:30.94#ibcon#wrote, iclass 4, count 2 2006.257.18:20:30.94#ibcon#about to read 3, iclass 4, count 2 2006.257.18:20:30.96#ibcon#read 3, iclass 4, count 2 2006.257.18:20:30.96#ibcon#about to read 4, iclass 4, count 2 2006.257.18:20:30.96#ibcon#read 4, iclass 4, count 2 2006.257.18:20:30.96#ibcon#about to read 5, iclass 4, count 2 2006.257.18:20:30.96#ibcon#read 5, iclass 4, count 2 2006.257.18:20:30.96#ibcon#about to read 6, iclass 4, count 2 2006.257.18:20:30.96#ibcon#read 6, iclass 4, count 2 2006.257.18:20:30.96#ibcon#end of sib2, iclass 4, count 2 2006.257.18:20:30.96#ibcon#*mode == 0, iclass 4, count 2 2006.257.18:20:30.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.18:20:30.96#ibcon#[25=AT05-04\r\n] 2006.257.18:20:30.96#ibcon#*before write, iclass 4, count 2 2006.257.18:20:30.96#ibcon#enter sib2, iclass 4, count 2 2006.257.18:20:30.96#ibcon#flushed, iclass 4, count 2 2006.257.18:20:30.96#ibcon#about to write, iclass 4, count 2 2006.257.18:20:30.96#ibcon#wrote, iclass 4, count 2 2006.257.18:20:30.96#ibcon#about to read 3, iclass 4, count 2 2006.257.18:20:30.99#ibcon#read 3, iclass 4, count 2 2006.257.18:20:30.99#ibcon#about to read 4, iclass 4, count 2 2006.257.18:20:30.99#ibcon#read 4, iclass 4, count 2 2006.257.18:20:30.99#ibcon#about to read 5, iclass 4, count 2 2006.257.18:20:30.99#ibcon#read 5, iclass 4, count 2 2006.257.18:20:30.99#ibcon#about to read 6, iclass 4, count 2 2006.257.18:20:30.99#ibcon#read 6, iclass 4, count 2 2006.257.18:20:30.99#ibcon#end of sib2, iclass 4, count 2 2006.257.18:20:30.99#ibcon#*after write, iclass 4, count 2 2006.257.18:20:30.99#ibcon#*before return 0, iclass 4, count 2 2006.257.18:20:30.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:30.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:30.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.18:20:30.99#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:30.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:31.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:31.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:31.11#ibcon#enter wrdev, iclass 4, count 0 2006.257.18:20:31.11#ibcon#first serial, iclass 4, count 0 2006.257.18:20:31.11#ibcon#enter sib2, iclass 4, count 0 2006.257.18:20:31.11#ibcon#flushed, iclass 4, count 0 2006.257.18:20:31.11#ibcon#about to write, iclass 4, count 0 2006.257.18:20:31.11#ibcon#wrote, iclass 4, count 0 2006.257.18:20:31.11#ibcon#about to read 3, iclass 4, count 0 2006.257.18:20:31.13#ibcon#read 3, iclass 4, count 0 2006.257.18:20:31.13#ibcon#about to read 4, iclass 4, count 0 2006.257.18:20:31.13#ibcon#read 4, iclass 4, count 0 2006.257.18:20:31.13#ibcon#about to read 5, iclass 4, count 0 2006.257.18:20:31.13#ibcon#read 5, iclass 4, count 0 2006.257.18:20:31.13#ibcon#about to read 6, iclass 4, count 0 2006.257.18:20:31.13#ibcon#read 6, iclass 4, count 0 2006.257.18:20:31.13#ibcon#end of sib2, iclass 4, count 0 2006.257.18:20:31.13#ibcon#*mode == 0, iclass 4, count 0 2006.257.18:20:31.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.18:20:31.13#ibcon#[25=USB\r\n] 2006.257.18:20:31.13#ibcon#*before write, iclass 4, count 0 2006.257.18:20:31.13#ibcon#enter sib2, iclass 4, count 0 2006.257.18:20:31.13#ibcon#flushed, iclass 4, count 0 2006.257.18:20:31.13#ibcon#about to write, iclass 4, count 0 2006.257.18:20:31.13#ibcon#wrote, iclass 4, count 0 2006.257.18:20:31.13#ibcon#about to read 3, iclass 4, count 0 2006.257.18:20:31.16#ibcon#read 3, iclass 4, count 0 2006.257.18:20:31.16#ibcon#about to read 4, iclass 4, count 0 2006.257.18:20:31.16#ibcon#read 4, iclass 4, count 0 2006.257.18:20:31.16#ibcon#about to read 5, iclass 4, count 0 2006.257.18:20:31.16#ibcon#read 5, iclass 4, count 0 2006.257.18:20:31.16#ibcon#about to read 6, iclass 4, count 0 2006.257.18:20:31.16#ibcon#read 6, iclass 4, count 0 2006.257.18:20:31.16#ibcon#end of sib2, iclass 4, count 0 2006.257.18:20:31.16#ibcon#*after write, iclass 4, count 0 2006.257.18:20:31.16#ibcon#*before return 0, iclass 4, count 0 2006.257.18:20:31.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:31.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:31.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.18:20:31.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.18:20:31.16$vck44/valo=6,814.99 2006.257.18:20:31.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.18:20:31.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.18:20:31.16#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:31.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:31.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:31.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:31.16#ibcon#enter wrdev, iclass 6, count 0 2006.257.18:20:31.16#ibcon#first serial, iclass 6, count 0 2006.257.18:20:31.16#ibcon#enter sib2, iclass 6, count 0 2006.257.18:20:31.16#ibcon#flushed, iclass 6, count 0 2006.257.18:20:31.16#ibcon#about to write, iclass 6, count 0 2006.257.18:20:31.16#ibcon#wrote, iclass 6, count 0 2006.257.18:20:31.16#ibcon#about to read 3, iclass 6, count 0 2006.257.18:20:31.18#ibcon#read 3, iclass 6, count 0 2006.257.18:20:31.18#ibcon#about to read 4, iclass 6, count 0 2006.257.18:20:31.18#ibcon#read 4, iclass 6, count 0 2006.257.18:20:31.18#ibcon#about to read 5, iclass 6, count 0 2006.257.18:20:31.18#ibcon#read 5, iclass 6, count 0 2006.257.18:20:31.18#ibcon#about to read 6, iclass 6, count 0 2006.257.18:20:31.18#ibcon#read 6, iclass 6, count 0 2006.257.18:20:31.18#ibcon#end of sib2, iclass 6, count 0 2006.257.18:20:31.18#ibcon#*mode == 0, iclass 6, count 0 2006.257.18:20:31.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.18:20:31.18#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:20:31.18#ibcon#*before write, iclass 6, count 0 2006.257.18:20:31.18#ibcon#enter sib2, iclass 6, count 0 2006.257.18:20:31.18#ibcon#flushed, iclass 6, count 0 2006.257.18:20:31.18#ibcon#about to write, iclass 6, count 0 2006.257.18:20:31.18#ibcon#wrote, iclass 6, count 0 2006.257.18:20:31.18#ibcon#about to read 3, iclass 6, count 0 2006.257.18:20:31.22#ibcon#read 3, iclass 6, count 0 2006.257.18:20:31.22#ibcon#about to read 4, iclass 6, count 0 2006.257.18:20:31.22#ibcon#read 4, iclass 6, count 0 2006.257.18:20:31.22#ibcon#about to read 5, iclass 6, count 0 2006.257.18:20:31.22#ibcon#read 5, iclass 6, count 0 2006.257.18:20:31.22#ibcon#about to read 6, iclass 6, count 0 2006.257.18:20:31.22#ibcon#read 6, iclass 6, count 0 2006.257.18:20:31.22#ibcon#end of sib2, iclass 6, count 0 2006.257.18:20:31.22#ibcon#*after write, iclass 6, count 0 2006.257.18:20:31.22#ibcon#*before return 0, iclass 6, count 0 2006.257.18:20:31.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:31.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:31.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.18:20:31.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.18:20:31.22$vck44/va=6,4 2006.257.18:20:31.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.18:20:31.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.18:20:31.22#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:31.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:31.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:31.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:31.28#ibcon#enter wrdev, iclass 10, count 2 2006.257.18:20:31.28#ibcon#first serial, iclass 10, count 2 2006.257.18:20:31.28#ibcon#enter sib2, iclass 10, count 2 2006.257.18:20:31.28#ibcon#flushed, iclass 10, count 2 2006.257.18:20:31.28#ibcon#about to write, iclass 10, count 2 2006.257.18:20:31.28#ibcon#wrote, iclass 10, count 2 2006.257.18:20:31.28#ibcon#about to read 3, iclass 10, count 2 2006.257.18:20:31.30#ibcon#read 3, iclass 10, count 2 2006.257.18:20:31.30#ibcon#about to read 4, iclass 10, count 2 2006.257.18:20:31.30#ibcon#read 4, iclass 10, count 2 2006.257.18:20:31.30#ibcon#about to read 5, iclass 10, count 2 2006.257.18:20:31.30#ibcon#read 5, iclass 10, count 2 2006.257.18:20:31.30#ibcon#about to read 6, iclass 10, count 2 2006.257.18:20:31.30#ibcon#read 6, iclass 10, count 2 2006.257.18:20:31.30#ibcon#end of sib2, iclass 10, count 2 2006.257.18:20:31.30#ibcon#*mode == 0, iclass 10, count 2 2006.257.18:20:31.30#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.18:20:31.30#ibcon#[25=AT06-04\r\n] 2006.257.18:20:31.30#ibcon#*before write, iclass 10, count 2 2006.257.18:20:31.30#ibcon#enter sib2, iclass 10, count 2 2006.257.18:20:31.30#ibcon#flushed, iclass 10, count 2 2006.257.18:20:31.30#ibcon#about to write, iclass 10, count 2 2006.257.18:20:31.30#ibcon#wrote, iclass 10, count 2 2006.257.18:20:31.30#ibcon#about to read 3, iclass 10, count 2 2006.257.18:20:31.33#ibcon#read 3, iclass 10, count 2 2006.257.18:20:31.33#ibcon#about to read 4, iclass 10, count 2 2006.257.18:20:31.33#ibcon#read 4, iclass 10, count 2 2006.257.18:20:31.33#ibcon#about to read 5, iclass 10, count 2 2006.257.18:20:31.33#ibcon#read 5, iclass 10, count 2 2006.257.18:20:31.33#ibcon#about to read 6, iclass 10, count 2 2006.257.18:20:31.33#ibcon#read 6, iclass 10, count 2 2006.257.18:20:31.33#ibcon#end of sib2, iclass 10, count 2 2006.257.18:20:31.33#ibcon#*after write, iclass 10, count 2 2006.257.18:20:31.33#ibcon#*before return 0, iclass 10, count 2 2006.257.18:20:31.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:31.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:31.33#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.18:20:31.33#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:31.33#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:31.45#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:31.45#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:31.45#ibcon#enter wrdev, iclass 10, count 0 2006.257.18:20:31.45#ibcon#first serial, iclass 10, count 0 2006.257.18:20:31.45#ibcon#enter sib2, iclass 10, count 0 2006.257.18:20:31.45#ibcon#flushed, iclass 10, count 0 2006.257.18:20:31.45#ibcon#about to write, iclass 10, count 0 2006.257.18:20:31.45#ibcon#wrote, iclass 10, count 0 2006.257.18:20:31.45#ibcon#about to read 3, iclass 10, count 0 2006.257.18:20:31.47#ibcon#read 3, iclass 10, count 0 2006.257.18:20:31.47#ibcon#about to read 4, iclass 10, count 0 2006.257.18:20:31.47#ibcon#read 4, iclass 10, count 0 2006.257.18:20:31.47#ibcon#about to read 5, iclass 10, count 0 2006.257.18:20:31.47#ibcon#read 5, iclass 10, count 0 2006.257.18:20:31.47#ibcon#about to read 6, iclass 10, count 0 2006.257.18:20:31.47#ibcon#read 6, iclass 10, count 0 2006.257.18:20:31.47#ibcon#end of sib2, iclass 10, count 0 2006.257.18:20:31.47#ibcon#*mode == 0, iclass 10, count 0 2006.257.18:20:31.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.18:20:31.47#ibcon#[25=USB\r\n] 2006.257.18:20:31.47#ibcon#*before write, iclass 10, count 0 2006.257.18:20:31.47#ibcon#enter sib2, iclass 10, count 0 2006.257.18:20:31.47#ibcon#flushed, iclass 10, count 0 2006.257.18:20:31.47#ibcon#about to write, iclass 10, count 0 2006.257.18:20:31.47#ibcon#wrote, iclass 10, count 0 2006.257.18:20:31.47#ibcon#about to read 3, iclass 10, count 0 2006.257.18:20:31.50#ibcon#read 3, iclass 10, count 0 2006.257.18:20:31.50#ibcon#about to read 4, iclass 10, count 0 2006.257.18:20:31.50#ibcon#read 4, iclass 10, count 0 2006.257.18:20:31.50#ibcon#about to read 5, iclass 10, count 0 2006.257.18:20:31.50#ibcon#read 5, iclass 10, count 0 2006.257.18:20:31.50#ibcon#about to read 6, iclass 10, count 0 2006.257.18:20:31.50#ibcon#read 6, iclass 10, count 0 2006.257.18:20:31.50#ibcon#end of sib2, iclass 10, count 0 2006.257.18:20:31.50#ibcon#*after write, iclass 10, count 0 2006.257.18:20:31.50#ibcon#*before return 0, iclass 10, count 0 2006.257.18:20:31.50#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:31.50#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:31.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.18:20:31.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.18:20:31.50$vck44/valo=7,864.99 2006.257.18:20:31.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.18:20:31.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.18:20:31.50#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:31.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:31.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:31.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:31.50#ibcon#enter wrdev, iclass 12, count 0 2006.257.18:20:31.50#ibcon#first serial, iclass 12, count 0 2006.257.18:20:31.50#ibcon#enter sib2, iclass 12, count 0 2006.257.18:20:31.50#ibcon#flushed, iclass 12, count 0 2006.257.18:20:31.50#ibcon#about to write, iclass 12, count 0 2006.257.18:20:31.50#ibcon#wrote, iclass 12, count 0 2006.257.18:20:31.50#ibcon#about to read 3, iclass 12, count 0 2006.257.18:20:31.52#ibcon#read 3, iclass 12, count 0 2006.257.18:20:31.52#ibcon#about to read 4, iclass 12, count 0 2006.257.18:20:31.52#ibcon#read 4, iclass 12, count 0 2006.257.18:20:31.52#ibcon#about to read 5, iclass 12, count 0 2006.257.18:20:31.52#ibcon#read 5, iclass 12, count 0 2006.257.18:20:31.52#ibcon#about to read 6, iclass 12, count 0 2006.257.18:20:31.52#ibcon#read 6, iclass 12, count 0 2006.257.18:20:31.52#ibcon#end of sib2, iclass 12, count 0 2006.257.18:20:31.52#ibcon#*mode == 0, iclass 12, count 0 2006.257.18:20:31.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.18:20:31.52#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:20:31.52#ibcon#*before write, iclass 12, count 0 2006.257.18:20:31.52#ibcon#enter sib2, iclass 12, count 0 2006.257.18:20:31.52#ibcon#flushed, iclass 12, count 0 2006.257.18:20:31.52#ibcon#about to write, iclass 12, count 0 2006.257.18:20:31.52#ibcon#wrote, iclass 12, count 0 2006.257.18:20:31.52#ibcon#about to read 3, iclass 12, count 0 2006.257.18:20:31.56#ibcon#read 3, iclass 12, count 0 2006.257.18:20:31.56#ibcon#about to read 4, iclass 12, count 0 2006.257.18:20:31.56#ibcon#read 4, iclass 12, count 0 2006.257.18:20:31.56#ibcon#about to read 5, iclass 12, count 0 2006.257.18:20:31.56#ibcon#read 5, iclass 12, count 0 2006.257.18:20:31.56#ibcon#about to read 6, iclass 12, count 0 2006.257.18:20:31.56#ibcon#read 6, iclass 12, count 0 2006.257.18:20:31.56#ibcon#end of sib2, iclass 12, count 0 2006.257.18:20:31.56#ibcon#*after write, iclass 12, count 0 2006.257.18:20:31.56#ibcon#*before return 0, iclass 12, count 0 2006.257.18:20:31.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:31.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:31.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.18:20:31.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.18:20:31.56$vck44/va=7,4 2006.257.18:20:31.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.18:20:31.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.18:20:31.56#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:31.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:31.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:31.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:31.62#ibcon#enter wrdev, iclass 14, count 2 2006.257.18:20:31.62#ibcon#first serial, iclass 14, count 2 2006.257.18:20:31.62#ibcon#enter sib2, iclass 14, count 2 2006.257.18:20:31.62#ibcon#flushed, iclass 14, count 2 2006.257.18:20:31.62#ibcon#about to write, iclass 14, count 2 2006.257.18:20:31.62#ibcon#wrote, iclass 14, count 2 2006.257.18:20:31.62#ibcon#about to read 3, iclass 14, count 2 2006.257.18:20:31.64#ibcon#read 3, iclass 14, count 2 2006.257.18:20:31.64#ibcon#about to read 4, iclass 14, count 2 2006.257.18:20:31.64#ibcon#read 4, iclass 14, count 2 2006.257.18:20:31.64#ibcon#about to read 5, iclass 14, count 2 2006.257.18:20:31.64#ibcon#read 5, iclass 14, count 2 2006.257.18:20:31.64#ibcon#about to read 6, iclass 14, count 2 2006.257.18:20:31.64#ibcon#read 6, iclass 14, count 2 2006.257.18:20:31.64#ibcon#end of sib2, iclass 14, count 2 2006.257.18:20:31.64#ibcon#*mode == 0, iclass 14, count 2 2006.257.18:20:31.64#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.18:20:31.64#ibcon#[25=AT07-04\r\n] 2006.257.18:20:31.64#ibcon#*before write, iclass 14, count 2 2006.257.18:20:31.64#ibcon#enter sib2, iclass 14, count 2 2006.257.18:20:31.64#ibcon#flushed, iclass 14, count 2 2006.257.18:20:31.64#ibcon#about to write, iclass 14, count 2 2006.257.18:20:31.64#ibcon#wrote, iclass 14, count 2 2006.257.18:20:31.64#ibcon#about to read 3, iclass 14, count 2 2006.257.18:20:31.67#ibcon#read 3, iclass 14, count 2 2006.257.18:20:31.67#ibcon#about to read 4, iclass 14, count 2 2006.257.18:20:31.67#ibcon#read 4, iclass 14, count 2 2006.257.18:20:31.67#ibcon#about to read 5, iclass 14, count 2 2006.257.18:20:31.67#ibcon#read 5, iclass 14, count 2 2006.257.18:20:31.67#ibcon#about to read 6, iclass 14, count 2 2006.257.18:20:31.67#ibcon#read 6, iclass 14, count 2 2006.257.18:20:31.67#ibcon#end of sib2, iclass 14, count 2 2006.257.18:20:31.67#ibcon#*after write, iclass 14, count 2 2006.257.18:20:31.67#ibcon#*before return 0, iclass 14, count 2 2006.257.18:20:31.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:31.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:31.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.18:20:31.67#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:31.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:31.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:31.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:31.79#ibcon#enter wrdev, iclass 14, count 0 2006.257.18:20:31.79#ibcon#first serial, iclass 14, count 0 2006.257.18:20:31.79#ibcon#enter sib2, iclass 14, count 0 2006.257.18:20:31.79#ibcon#flushed, iclass 14, count 0 2006.257.18:20:31.79#ibcon#about to write, iclass 14, count 0 2006.257.18:20:31.79#ibcon#wrote, iclass 14, count 0 2006.257.18:20:31.79#ibcon#about to read 3, iclass 14, count 0 2006.257.18:20:31.81#ibcon#read 3, iclass 14, count 0 2006.257.18:20:31.81#ibcon#about to read 4, iclass 14, count 0 2006.257.18:20:31.81#ibcon#read 4, iclass 14, count 0 2006.257.18:20:31.81#ibcon#about to read 5, iclass 14, count 0 2006.257.18:20:31.81#ibcon#read 5, iclass 14, count 0 2006.257.18:20:31.81#ibcon#about to read 6, iclass 14, count 0 2006.257.18:20:31.81#ibcon#read 6, iclass 14, count 0 2006.257.18:20:31.81#ibcon#end of sib2, iclass 14, count 0 2006.257.18:20:31.81#ibcon#*mode == 0, iclass 14, count 0 2006.257.18:20:31.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.18:20:31.81#ibcon#[25=USB\r\n] 2006.257.18:20:31.81#ibcon#*before write, iclass 14, count 0 2006.257.18:20:31.81#ibcon#enter sib2, iclass 14, count 0 2006.257.18:20:31.81#ibcon#flushed, iclass 14, count 0 2006.257.18:20:31.81#ibcon#about to write, iclass 14, count 0 2006.257.18:20:31.81#ibcon#wrote, iclass 14, count 0 2006.257.18:20:31.81#ibcon#about to read 3, iclass 14, count 0 2006.257.18:20:31.84#ibcon#read 3, iclass 14, count 0 2006.257.18:20:31.84#ibcon#about to read 4, iclass 14, count 0 2006.257.18:20:31.84#ibcon#read 4, iclass 14, count 0 2006.257.18:20:31.84#ibcon#about to read 5, iclass 14, count 0 2006.257.18:20:31.84#ibcon#read 5, iclass 14, count 0 2006.257.18:20:31.84#ibcon#about to read 6, iclass 14, count 0 2006.257.18:20:31.84#ibcon#read 6, iclass 14, count 0 2006.257.18:20:31.84#ibcon#end of sib2, iclass 14, count 0 2006.257.18:20:31.84#ibcon#*after write, iclass 14, count 0 2006.257.18:20:31.84#ibcon#*before return 0, iclass 14, count 0 2006.257.18:20:31.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:31.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:31.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.18:20:31.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.18:20:31.84$vck44/valo=8,884.99 2006.257.18:20:31.84#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.18:20:31.84#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.18:20:31.84#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:31.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:31.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:31.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:31.84#ibcon#enter wrdev, iclass 16, count 0 2006.257.18:20:31.84#ibcon#first serial, iclass 16, count 0 2006.257.18:20:31.84#ibcon#enter sib2, iclass 16, count 0 2006.257.18:20:31.84#ibcon#flushed, iclass 16, count 0 2006.257.18:20:31.84#ibcon#about to write, iclass 16, count 0 2006.257.18:20:31.84#ibcon#wrote, iclass 16, count 0 2006.257.18:20:31.84#ibcon#about to read 3, iclass 16, count 0 2006.257.18:20:31.86#ibcon#read 3, iclass 16, count 0 2006.257.18:20:31.86#ibcon#about to read 4, iclass 16, count 0 2006.257.18:20:31.86#ibcon#read 4, iclass 16, count 0 2006.257.18:20:31.86#ibcon#about to read 5, iclass 16, count 0 2006.257.18:20:31.86#ibcon#read 5, iclass 16, count 0 2006.257.18:20:31.86#ibcon#about to read 6, iclass 16, count 0 2006.257.18:20:31.86#ibcon#read 6, iclass 16, count 0 2006.257.18:20:31.86#ibcon#end of sib2, iclass 16, count 0 2006.257.18:20:31.86#ibcon#*mode == 0, iclass 16, count 0 2006.257.18:20:31.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.18:20:31.86#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:20:31.86#ibcon#*before write, iclass 16, count 0 2006.257.18:20:31.86#ibcon#enter sib2, iclass 16, count 0 2006.257.18:20:31.86#ibcon#flushed, iclass 16, count 0 2006.257.18:20:31.86#ibcon#about to write, iclass 16, count 0 2006.257.18:20:31.86#ibcon#wrote, iclass 16, count 0 2006.257.18:20:31.86#ibcon#about to read 3, iclass 16, count 0 2006.257.18:20:31.90#ibcon#read 3, iclass 16, count 0 2006.257.18:20:31.90#ibcon#about to read 4, iclass 16, count 0 2006.257.18:20:31.90#ibcon#read 4, iclass 16, count 0 2006.257.18:20:31.90#ibcon#about to read 5, iclass 16, count 0 2006.257.18:20:31.90#ibcon#read 5, iclass 16, count 0 2006.257.18:20:31.90#ibcon#about to read 6, iclass 16, count 0 2006.257.18:20:31.90#ibcon#read 6, iclass 16, count 0 2006.257.18:20:31.90#ibcon#end of sib2, iclass 16, count 0 2006.257.18:20:31.90#ibcon#*after write, iclass 16, count 0 2006.257.18:20:31.90#ibcon#*before return 0, iclass 16, count 0 2006.257.18:20:31.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:31.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:31.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.18:20:31.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.18:20:31.90$vck44/va=8,4 2006.257.18:20:31.90#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.18:20:31.90#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.18:20:31.90#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:31.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:20:31.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:20:31.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:20:31.96#ibcon#enter wrdev, iclass 18, count 2 2006.257.18:20:31.96#ibcon#first serial, iclass 18, count 2 2006.257.18:20:31.96#ibcon#enter sib2, iclass 18, count 2 2006.257.18:20:31.96#ibcon#flushed, iclass 18, count 2 2006.257.18:20:31.96#ibcon#about to write, iclass 18, count 2 2006.257.18:20:31.96#ibcon#wrote, iclass 18, count 2 2006.257.18:20:31.96#ibcon#about to read 3, iclass 18, count 2 2006.257.18:20:31.98#ibcon#read 3, iclass 18, count 2 2006.257.18:20:31.98#ibcon#about to read 4, iclass 18, count 2 2006.257.18:20:31.98#ibcon#read 4, iclass 18, count 2 2006.257.18:20:31.98#ibcon#about to read 5, iclass 18, count 2 2006.257.18:20:31.98#ibcon#read 5, iclass 18, count 2 2006.257.18:20:31.98#ibcon#about to read 6, iclass 18, count 2 2006.257.18:20:31.98#ibcon#read 6, iclass 18, count 2 2006.257.18:20:31.98#ibcon#end of sib2, iclass 18, count 2 2006.257.18:20:31.98#ibcon#*mode == 0, iclass 18, count 2 2006.257.18:20:31.98#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.18:20:31.98#ibcon#[25=AT08-04\r\n] 2006.257.18:20:31.98#ibcon#*before write, iclass 18, count 2 2006.257.18:20:31.98#ibcon#enter sib2, iclass 18, count 2 2006.257.18:20:31.98#ibcon#flushed, iclass 18, count 2 2006.257.18:20:31.98#ibcon#about to write, iclass 18, count 2 2006.257.18:20:31.98#ibcon#wrote, iclass 18, count 2 2006.257.18:20:31.98#ibcon#about to read 3, iclass 18, count 2 2006.257.18:20:32.01#ibcon#read 3, iclass 18, count 2 2006.257.18:20:32.01#ibcon#about to read 4, iclass 18, count 2 2006.257.18:20:32.01#ibcon#read 4, iclass 18, count 2 2006.257.18:20:32.01#ibcon#about to read 5, iclass 18, count 2 2006.257.18:20:32.01#ibcon#read 5, iclass 18, count 2 2006.257.18:20:32.01#ibcon#about to read 6, iclass 18, count 2 2006.257.18:20:32.01#ibcon#read 6, iclass 18, count 2 2006.257.18:20:32.01#ibcon#end of sib2, iclass 18, count 2 2006.257.18:20:32.01#ibcon#*after write, iclass 18, count 2 2006.257.18:20:32.01#ibcon#*before return 0, iclass 18, count 2 2006.257.18:20:32.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:20:32.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:20:32.01#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.18:20:32.01#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:32.01#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:20:32.13#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:20:32.13#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:20:32.13#ibcon#enter wrdev, iclass 18, count 0 2006.257.18:20:32.13#ibcon#first serial, iclass 18, count 0 2006.257.18:20:32.13#ibcon#enter sib2, iclass 18, count 0 2006.257.18:20:32.13#ibcon#flushed, iclass 18, count 0 2006.257.18:20:32.13#ibcon#about to write, iclass 18, count 0 2006.257.18:20:32.13#ibcon#wrote, iclass 18, count 0 2006.257.18:20:32.13#ibcon#about to read 3, iclass 18, count 0 2006.257.18:20:32.15#ibcon#read 3, iclass 18, count 0 2006.257.18:20:32.15#ibcon#about to read 4, iclass 18, count 0 2006.257.18:20:32.15#ibcon#read 4, iclass 18, count 0 2006.257.18:20:32.15#ibcon#about to read 5, iclass 18, count 0 2006.257.18:20:32.15#ibcon#read 5, iclass 18, count 0 2006.257.18:20:32.15#ibcon#about to read 6, iclass 18, count 0 2006.257.18:20:32.15#ibcon#read 6, iclass 18, count 0 2006.257.18:20:32.15#ibcon#end of sib2, iclass 18, count 0 2006.257.18:20:32.15#ibcon#*mode == 0, iclass 18, count 0 2006.257.18:20:32.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.18:20:32.15#ibcon#[25=USB\r\n] 2006.257.18:20:32.15#ibcon#*before write, iclass 18, count 0 2006.257.18:20:32.15#ibcon#enter sib2, iclass 18, count 0 2006.257.18:20:32.15#ibcon#flushed, iclass 18, count 0 2006.257.18:20:32.15#ibcon#about to write, iclass 18, count 0 2006.257.18:20:32.15#ibcon#wrote, iclass 18, count 0 2006.257.18:20:32.15#ibcon#about to read 3, iclass 18, count 0 2006.257.18:20:32.18#ibcon#read 3, iclass 18, count 0 2006.257.18:20:32.18#ibcon#about to read 4, iclass 18, count 0 2006.257.18:20:32.18#ibcon#read 4, iclass 18, count 0 2006.257.18:20:32.18#ibcon#about to read 5, iclass 18, count 0 2006.257.18:20:32.18#ibcon#read 5, iclass 18, count 0 2006.257.18:20:32.18#ibcon#about to read 6, iclass 18, count 0 2006.257.18:20:32.18#ibcon#read 6, iclass 18, count 0 2006.257.18:20:32.18#ibcon#end of sib2, iclass 18, count 0 2006.257.18:20:32.18#ibcon#*after write, iclass 18, count 0 2006.257.18:20:32.18#ibcon#*before return 0, iclass 18, count 0 2006.257.18:20:32.18#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:20:32.18#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:20:32.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.18:20:32.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.18:20:32.18$vck44/vblo=1,629.99 2006.257.18:20:32.18#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.18:20:32.18#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.18:20:32.18#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:32.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:20:32.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:20:32.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:20:32.18#ibcon#enter wrdev, iclass 20, count 0 2006.257.18:20:32.18#ibcon#first serial, iclass 20, count 0 2006.257.18:20:32.18#ibcon#enter sib2, iclass 20, count 0 2006.257.18:20:32.18#ibcon#flushed, iclass 20, count 0 2006.257.18:20:32.18#ibcon#about to write, iclass 20, count 0 2006.257.18:20:32.18#ibcon#wrote, iclass 20, count 0 2006.257.18:20:32.18#ibcon#about to read 3, iclass 20, count 0 2006.257.18:20:32.20#ibcon#read 3, iclass 20, count 0 2006.257.18:20:32.20#ibcon#about to read 4, iclass 20, count 0 2006.257.18:20:32.20#ibcon#read 4, iclass 20, count 0 2006.257.18:20:32.20#ibcon#about to read 5, iclass 20, count 0 2006.257.18:20:32.20#ibcon#read 5, iclass 20, count 0 2006.257.18:20:32.20#ibcon#about to read 6, iclass 20, count 0 2006.257.18:20:32.20#ibcon#read 6, iclass 20, count 0 2006.257.18:20:32.20#ibcon#end of sib2, iclass 20, count 0 2006.257.18:20:32.20#ibcon#*mode == 0, iclass 20, count 0 2006.257.18:20:32.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.18:20:32.20#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:20:32.20#ibcon#*before write, iclass 20, count 0 2006.257.18:20:32.20#ibcon#enter sib2, iclass 20, count 0 2006.257.18:20:32.20#ibcon#flushed, iclass 20, count 0 2006.257.18:20:32.20#ibcon#about to write, iclass 20, count 0 2006.257.18:20:32.20#ibcon#wrote, iclass 20, count 0 2006.257.18:20:32.20#ibcon#about to read 3, iclass 20, count 0 2006.257.18:20:32.24#ibcon#read 3, iclass 20, count 0 2006.257.18:20:32.24#ibcon#about to read 4, iclass 20, count 0 2006.257.18:20:32.24#ibcon#read 4, iclass 20, count 0 2006.257.18:20:32.24#ibcon#about to read 5, iclass 20, count 0 2006.257.18:20:32.24#ibcon#read 5, iclass 20, count 0 2006.257.18:20:32.24#ibcon#about to read 6, iclass 20, count 0 2006.257.18:20:32.24#ibcon#read 6, iclass 20, count 0 2006.257.18:20:32.24#ibcon#end of sib2, iclass 20, count 0 2006.257.18:20:32.24#ibcon#*after write, iclass 20, count 0 2006.257.18:20:32.24#ibcon#*before return 0, iclass 20, count 0 2006.257.18:20:32.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:20:32.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:20:32.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.18:20:32.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.18:20:32.24$vck44/vb=1,4 2006.257.18:20:32.24#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.18:20:32.24#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.18:20:32.24#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:32.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:20:32.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:20:32.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:20:32.24#ibcon#enter wrdev, iclass 22, count 2 2006.257.18:20:32.24#ibcon#first serial, iclass 22, count 2 2006.257.18:20:32.24#ibcon#enter sib2, iclass 22, count 2 2006.257.18:20:32.24#ibcon#flushed, iclass 22, count 2 2006.257.18:20:32.24#ibcon#about to write, iclass 22, count 2 2006.257.18:20:32.24#ibcon#wrote, iclass 22, count 2 2006.257.18:20:32.24#ibcon#about to read 3, iclass 22, count 2 2006.257.18:20:32.26#ibcon#read 3, iclass 22, count 2 2006.257.18:20:32.26#ibcon#about to read 4, iclass 22, count 2 2006.257.18:20:32.26#ibcon#read 4, iclass 22, count 2 2006.257.18:20:32.26#ibcon#about to read 5, iclass 22, count 2 2006.257.18:20:32.26#ibcon#read 5, iclass 22, count 2 2006.257.18:20:32.26#ibcon#about to read 6, iclass 22, count 2 2006.257.18:20:32.26#ibcon#read 6, iclass 22, count 2 2006.257.18:20:32.26#ibcon#end of sib2, iclass 22, count 2 2006.257.18:20:32.26#ibcon#*mode == 0, iclass 22, count 2 2006.257.18:20:32.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.18:20:32.26#ibcon#[27=AT01-04\r\n] 2006.257.18:20:32.26#ibcon#*before write, iclass 22, count 2 2006.257.18:20:32.26#ibcon#enter sib2, iclass 22, count 2 2006.257.18:20:32.26#ibcon#flushed, iclass 22, count 2 2006.257.18:20:32.26#ibcon#about to write, iclass 22, count 2 2006.257.18:20:32.26#ibcon#wrote, iclass 22, count 2 2006.257.18:20:32.26#ibcon#about to read 3, iclass 22, count 2 2006.257.18:20:32.29#ibcon#read 3, iclass 22, count 2 2006.257.18:20:32.29#ibcon#about to read 4, iclass 22, count 2 2006.257.18:20:32.29#ibcon#read 4, iclass 22, count 2 2006.257.18:20:32.29#ibcon#about to read 5, iclass 22, count 2 2006.257.18:20:32.29#ibcon#read 5, iclass 22, count 2 2006.257.18:20:32.29#ibcon#about to read 6, iclass 22, count 2 2006.257.18:20:32.29#ibcon#read 6, iclass 22, count 2 2006.257.18:20:32.29#ibcon#end of sib2, iclass 22, count 2 2006.257.18:20:32.29#ibcon#*after write, iclass 22, count 2 2006.257.18:20:32.29#ibcon#*before return 0, iclass 22, count 2 2006.257.18:20:32.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:20:32.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:20:32.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.18:20:32.29#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:32.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:20:32.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:20:32.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:20:32.41#ibcon#enter wrdev, iclass 22, count 0 2006.257.18:20:32.41#ibcon#first serial, iclass 22, count 0 2006.257.18:20:32.41#ibcon#enter sib2, iclass 22, count 0 2006.257.18:20:32.41#ibcon#flushed, iclass 22, count 0 2006.257.18:20:32.41#ibcon#about to write, iclass 22, count 0 2006.257.18:20:32.41#ibcon#wrote, iclass 22, count 0 2006.257.18:20:32.41#ibcon#about to read 3, iclass 22, count 0 2006.257.18:20:32.43#ibcon#read 3, iclass 22, count 0 2006.257.18:20:32.43#ibcon#about to read 4, iclass 22, count 0 2006.257.18:20:32.43#ibcon#read 4, iclass 22, count 0 2006.257.18:20:32.43#ibcon#about to read 5, iclass 22, count 0 2006.257.18:20:32.43#ibcon#read 5, iclass 22, count 0 2006.257.18:20:32.43#ibcon#about to read 6, iclass 22, count 0 2006.257.18:20:32.43#ibcon#read 6, iclass 22, count 0 2006.257.18:20:32.43#ibcon#end of sib2, iclass 22, count 0 2006.257.18:20:32.43#ibcon#*mode == 0, iclass 22, count 0 2006.257.18:20:32.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.18:20:32.43#ibcon#[27=USB\r\n] 2006.257.18:20:32.43#ibcon#*before write, iclass 22, count 0 2006.257.18:20:32.43#ibcon#enter sib2, iclass 22, count 0 2006.257.18:20:32.43#ibcon#flushed, iclass 22, count 0 2006.257.18:20:32.43#ibcon#about to write, iclass 22, count 0 2006.257.18:20:32.43#ibcon#wrote, iclass 22, count 0 2006.257.18:20:32.43#ibcon#about to read 3, iclass 22, count 0 2006.257.18:20:32.46#ibcon#read 3, iclass 22, count 0 2006.257.18:20:32.46#ibcon#about to read 4, iclass 22, count 0 2006.257.18:20:32.46#ibcon#read 4, iclass 22, count 0 2006.257.18:20:32.46#ibcon#about to read 5, iclass 22, count 0 2006.257.18:20:32.46#ibcon#read 5, iclass 22, count 0 2006.257.18:20:32.46#ibcon#about to read 6, iclass 22, count 0 2006.257.18:20:32.46#ibcon#read 6, iclass 22, count 0 2006.257.18:20:32.46#ibcon#end of sib2, iclass 22, count 0 2006.257.18:20:32.46#ibcon#*after write, iclass 22, count 0 2006.257.18:20:32.46#ibcon#*before return 0, iclass 22, count 0 2006.257.18:20:32.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:20:32.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:20:32.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.18:20:32.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.18:20:32.46$vck44/vblo=2,634.99 2006.257.18:20:32.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.18:20:32.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.18:20:32.46#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:32.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:32.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:32.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:32.46#ibcon#enter wrdev, iclass 24, count 0 2006.257.18:20:32.46#ibcon#first serial, iclass 24, count 0 2006.257.18:20:32.46#ibcon#enter sib2, iclass 24, count 0 2006.257.18:20:32.46#ibcon#flushed, iclass 24, count 0 2006.257.18:20:32.46#ibcon#about to write, iclass 24, count 0 2006.257.18:20:32.46#ibcon#wrote, iclass 24, count 0 2006.257.18:20:32.46#ibcon#about to read 3, iclass 24, count 0 2006.257.18:20:32.48#ibcon#read 3, iclass 24, count 0 2006.257.18:20:32.48#ibcon#about to read 4, iclass 24, count 0 2006.257.18:20:32.48#ibcon#read 4, iclass 24, count 0 2006.257.18:20:32.48#ibcon#about to read 5, iclass 24, count 0 2006.257.18:20:32.48#ibcon#read 5, iclass 24, count 0 2006.257.18:20:32.48#ibcon#about to read 6, iclass 24, count 0 2006.257.18:20:32.48#ibcon#read 6, iclass 24, count 0 2006.257.18:20:32.48#ibcon#end of sib2, iclass 24, count 0 2006.257.18:20:32.48#ibcon#*mode == 0, iclass 24, count 0 2006.257.18:20:32.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.18:20:32.48#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:20:32.48#ibcon#*before write, iclass 24, count 0 2006.257.18:20:32.48#ibcon#enter sib2, iclass 24, count 0 2006.257.18:20:32.48#ibcon#flushed, iclass 24, count 0 2006.257.18:20:32.48#ibcon#about to write, iclass 24, count 0 2006.257.18:20:32.48#ibcon#wrote, iclass 24, count 0 2006.257.18:20:32.48#ibcon#about to read 3, iclass 24, count 0 2006.257.18:20:32.52#ibcon#read 3, iclass 24, count 0 2006.257.18:20:32.52#ibcon#about to read 4, iclass 24, count 0 2006.257.18:20:32.52#ibcon#read 4, iclass 24, count 0 2006.257.18:20:32.52#ibcon#about to read 5, iclass 24, count 0 2006.257.18:20:32.52#ibcon#read 5, iclass 24, count 0 2006.257.18:20:32.52#ibcon#about to read 6, iclass 24, count 0 2006.257.18:20:32.52#ibcon#read 6, iclass 24, count 0 2006.257.18:20:32.52#ibcon#end of sib2, iclass 24, count 0 2006.257.18:20:32.52#ibcon#*after write, iclass 24, count 0 2006.257.18:20:32.52#ibcon#*before return 0, iclass 24, count 0 2006.257.18:20:32.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:32.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:20:32.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.18:20:32.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.18:20:32.52$vck44/vb=2,5 2006.257.18:20:32.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.18:20:32.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.18:20:32.52#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:32.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:32.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:32.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:32.58#ibcon#enter wrdev, iclass 26, count 2 2006.257.18:20:32.58#ibcon#first serial, iclass 26, count 2 2006.257.18:20:32.58#ibcon#enter sib2, iclass 26, count 2 2006.257.18:20:32.58#ibcon#flushed, iclass 26, count 2 2006.257.18:20:32.58#ibcon#about to write, iclass 26, count 2 2006.257.18:20:32.58#ibcon#wrote, iclass 26, count 2 2006.257.18:20:32.58#ibcon#about to read 3, iclass 26, count 2 2006.257.18:20:32.60#ibcon#read 3, iclass 26, count 2 2006.257.18:20:32.60#ibcon#about to read 4, iclass 26, count 2 2006.257.18:20:32.60#ibcon#read 4, iclass 26, count 2 2006.257.18:20:32.60#ibcon#about to read 5, iclass 26, count 2 2006.257.18:20:32.60#ibcon#read 5, iclass 26, count 2 2006.257.18:20:32.60#ibcon#about to read 6, iclass 26, count 2 2006.257.18:20:32.60#ibcon#read 6, iclass 26, count 2 2006.257.18:20:32.60#ibcon#end of sib2, iclass 26, count 2 2006.257.18:20:32.60#ibcon#*mode == 0, iclass 26, count 2 2006.257.18:20:32.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.18:20:32.60#ibcon#[27=AT02-05\r\n] 2006.257.18:20:32.60#ibcon#*before write, iclass 26, count 2 2006.257.18:20:32.60#ibcon#enter sib2, iclass 26, count 2 2006.257.18:20:32.60#ibcon#flushed, iclass 26, count 2 2006.257.18:20:32.60#ibcon#about to write, iclass 26, count 2 2006.257.18:20:32.60#ibcon#wrote, iclass 26, count 2 2006.257.18:20:32.60#ibcon#about to read 3, iclass 26, count 2 2006.257.18:20:32.63#ibcon#read 3, iclass 26, count 2 2006.257.18:20:32.63#ibcon#about to read 4, iclass 26, count 2 2006.257.18:20:32.63#ibcon#read 4, iclass 26, count 2 2006.257.18:20:32.63#ibcon#about to read 5, iclass 26, count 2 2006.257.18:20:32.63#ibcon#read 5, iclass 26, count 2 2006.257.18:20:32.63#ibcon#about to read 6, iclass 26, count 2 2006.257.18:20:32.63#ibcon#read 6, iclass 26, count 2 2006.257.18:20:32.63#ibcon#end of sib2, iclass 26, count 2 2006.257.18:20:32.63#ibcon#*after write, iclass 26, count 2 2006.257.18:20:32.63#ibcon#*before return 0, iclass 26, count 2 2006.257.18:20:32.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:32.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:20:32.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.18:20:32.63#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:32.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:32.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:32.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:32.75#ibcon#enter wrdev, iclass 26, count 0 2006.257.18:20:32.75#ibcon#first serial, iclass 26, count 0 2006.257.18:20:32.75#ibcon#enter sib2, iclass 26, count 0 2006.257.18:20:32.75#ibcon#flushed, iclass 26, count 0 2006.257.18:20:32.75#ibcon#about to write, iclass 26, count 0 2006.257.18:20:32.75#ibcon#wrote, iclass 26, count 0 2006.257.18:20:32.75#ibcon#about to read 3, iclass 26, count 0 2006.257.18:20:32.77#ibcon#read 3, iclass 26, count 0 2006.257.18:20:32.77#ibcon#about to read 4, iclass 26, count 0 2006.257.18:20:32.77#ibcon#read 4, iclass 26, count 0 2006.257.18:20:32.77#ibcon#about to read 5, iclass 26, count 0 2006.257.18:20:32.77#ibcon#read 5, iclass 26, count 0 2006.257.18:20:32.77#ibcon#about to read 6, iclass 26, count 0 2006.257.18:20:32.77#ibcon#read 6, iclass 26, count 0 2006.257.18:20:32.77#ibcon#end of sib2, iclass 26, count 0 2006.257.18:20:32.77#ibcon#*mode == 0, iclass 26, count 0 2006.257.18:20:32.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.18:20:32.77#ibcon#[27=USB\r\n] 2006.257.18:20:32.77#ibcon#*before write, iclass 26, count 0 2006.257.18:20:32.77#ibcon#enter sib2, iclass 26, count 0 2006.257.18:20:32.77#ibcon#flushed, iclass 26, count 0 2006.257.18:20:32.77#ibcon#about to write, iclass 26, count 0 2006.257.18:20:32.77#ibcon#wrote, iclass 26, count 0 2006.257.18:20:32.77#ibcon#about to read 3, iclass 26, count 0 2006.257.18:20:32.80#ibcon#read 3, iclass 26, count 0 2006.257.18:20:32.80#ibcon#about to read 4, iclass 26, count 0 2006.257.18:20:32.80#ibcon#read 4, iclass 26, count 0 2006.257.18:20:32.80#ibcon#about to read 5, iclass 26, count 0 2006.257.18:20:32.80#ibcon#read 5, iclass 26, count 0 2006.257.18:20:32.80#ibcon#about to read 6, iclass 26, count 0 2006.257.18:20:32.80#ibcon#read 6, iclass 26, count 0 2006.257.18:20:32.80#ibcon#end of sib2, iclass 26, count 0 2006.257.18:20:32.80#ibcon#*after write, iclass 26, count 0 2006.257.18:20:32.80#ibcon#*before return 0, iclass 26, count 0 2006.257.18:20:32.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:32.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:20:32.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.18:20:32.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.18:20:32.80$vck44/vblo=3,649.99 2006.257.18:20:32.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.18:20:32.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.18:20:32.80#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:32.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:32.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:32.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:32.80#ibcon#enter wrdev, iclass 28, count 0 2006.257.18:20:32.80#ibcon#first serial, iclass 28, count 0 2006.257.18:20:32.80#ibcon#enter sib2, iclass 28, count 0 2006.257.18:20:32.80#ibcon#flushed, iclass 28, count 0 2006.257.18:20:32.80#ibcon#about to write, iclass 28, count 0 2006.257.18:20:32.80#ibcon#wrote, iclass 28, count 0 2006.257.18:20:32.80#ibcon#about to read 3, iclass 28, count 0 2006.257.18:20:32.82#ibcon#read 3, iclass 28, count 0 2006.257.18:20:32.82#ibcon#about to read 4, iclass 28, count 0 2006.257.18:20:32.82#ibcon#read 4, iclass 28, count 0 2006.257.18:20:32.82#ibcon#about to read 5, iclass 28, count 0 2006.257.18:20:32.82#ibcon#read 5, iclass 28, count 0 2006.257.18:20:32.82#ibcon#about to read 6, iclass 28, count 0 2006.257.18:20:32.82#ibcon#read 6, iclass 28, count 0 2006.257.18:20:32.82#ibcon#end of sib2, iclass 28, count 0 2006.257.18:20:32.82#ibcon#*mode == 0, iclass 28, count 0 2006.257.18:20:32.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.18:20:32.82#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:20:32.82#ibcon#*before write, iclass 28, count 0 2006.257.18:20:32.82#ibcon#enter sib2, iclass 28, count 0 2006.257.18:20:32.82#ibcon#flushed, iclass 28, count 0 2006.257.18:20:32.82#ibcon#about to write, iclass 28, count 0 2006.257.18:20:32.82#ibcon#wrote, iclass 28, count 0 2006.257.18:20:32.82#ibcon#about to read 3, iclass 28, count 0 2006.257.18:20:32.86#ibcon#read 3, iclass 28, count 0 2006.257.18:20:32.86#ibcon#about to read 4, iclass 28, count 0 2006.257.18:20:32.86#ibcon#read 4, iclass 28, count 0 2006.257.18:20:32.86#ibcon#about to read 5, iclass 28, count 0 2006.257.18:20:32.86#ibcon#read 5, iclass 28, count 0 2006.257.18:20:32.86#ibcon#about to read 6, iclass 28, count 0 2006.257.18:20:32.86#ibcon#read 6, iclass 28, count 0 2006.257.18:20:32.86#ibcon#end of sib2, iclass 28, count 0 2006.257.18:20:32.86#ibcon#*after write, iclass 28, count 0 2006.257.18:20:32.86#ibcon#*before return 0, iclass 28, count 0 2006.257.18:20:32.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:32.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:20:32.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.18:20:32.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.18:20:32.86$vck44/vb=3,4 2006.257.18:20:32.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.18:20:32.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.18:20:32.86#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:32.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:32.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:32.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:32.92#ibcon#enter wrdev, iclass 30, count 2 2006.257.18:20:32.92#ibcon#first serial, iclass 30, count 2 2006.257.18:20:32.92#ibcon#enter sib2, iclass 30, count 2 2006.257.18:20:32.92#ibcon#flushed, iclass 30, count 2 2006.257.18:20:32.92#ibcon#about to write, iclass 30, count 2 2006.257.18:20:32.92#ibcon#wrote, iclass 30, count 2 2006.257.18:20:32.92#ibcon#about to read 3, iclass 30, count 2 2006.257.18:20:32.94#ibcon#read 3, iclass 30, count 2 2006.257.18:20:32.94#ibcon#about to read 4, iclass 30, count 2 2006.257.18:20:32.94#ibcon#read 4, iclass 30, count 2 2006.257.18:20:32.94#ibcon#about to read 5, iclass 30, count 2 2006.257.18:20:32.94#ibcon#read 5, iclass 30, count 2 2006.257.18:20:32.94#ibcon#about to read 6, iclass 30, count 2 2006.257.18:20:32.94#ibcon#read 6, iclass 30, count 2 2006.257.18:20:32.94#ibcon#end of sib2, iclass 30, count 2 2006.257.18:20:32.94#ibcon#*mode == 0, iclass 30, count 2 2006.257.18:20:32.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.18:20:32.94#ibcon#[27=AT03-04\r\n] 2006.257.18:20:32.94#ibcon#*before write, iclass 30, count 2 2006.257.18:20:32.94#ibcon#enter sib2, iclass 30, count 2 2006.257.18:20:32.94#ibcon#flushed, iclass 30, count 2 2006.257.18:20:32.94#ibcon#about to write, iclass 30, count 2 2006.257.18:20:32.94#ibcon#wrote, iclass 30, count 2 2006.257.18:20:32.94#ibcon#about to read 3, iclass 30, count 2 2006.257.18:20:32.97#ibcon#read 3, iclass 30, count 2 2006.257.18:20:32.97#ibcon#about to read 4, iclass 30, count 2 2006.257.18:20:32.97#ibcon#read 4, iclass 30, count 2 2006.257.18:20:32.97#ibcon#about to read 5, iclass 30, count 2 2006.257.18:20:32.97#ibcon#read 5, iclass 30, count 2 2006.257.18:20:32.97#ibcon#about to read 6, iclass 30, count 2 2006.257.18:20:32.97#ibcon#read 6, iclass 30, count 2 2006.257.18:20:32.97#ibcon#end of sib2, iclass 30, count 2 2006.257.18:20:32.97#ibcon#*after write, iclass 30, count 2 2006.257.18:20:32.97#ibcon#*before return 0, iclass 30, count 2 2006.257.18:20:32.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:32.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:20:32.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.18:20:32.97#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:32.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:33.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:33.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:33.09#ibcon#enter wrdev, iclass 30, count 0 2006.257.18:20:33.09#ibcon#first serial, iclass 30, count 0 2006.257.18:20:33.09#ibcon#enter sib2, iclass 30, count 0 2006.257.18:20:33.09#ibcon#flushed, iclass 30, count 0 2006.257.18:20:33.09#ibcon#about to write, iclass 30, count 0 2006.257.18:20:33.09#ibcon#wrote, iclass 30, count 0 2006.257.18:20:33.09#ibcon#about to read 3, iclass 30, count 0 2006.257.18:20:33.11#ibcon#read 3, iclass 30, count 0 2006.257.18:20:33.11#ibcon#about to read 4, iclass 30, count 0 2006.257.18:20:33.11#ibcon#read 4, iclass 30, count 0 2006.257.18:20:33.11#ibcon#about to read 5, iclass 30, count 0 2006.257.18:20:33.11#ibcon#read 5, iclass 30, count 0 2006.257.18:20:33.11#ibcon#about to read 6, iclass 30, count 0 2006.257.18:20:33.11#ibcon#read 6, iclass 30, count 0 2006.257.18:20:33.11#ibcon#end of sib2, iclass 30, count 0 2006.257.18:20:33.11#ibcon#*mode == 0, iclass 30, count 0 2006.257.18:20:33.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.18:20:33.11#ibcon#[27=USB\r\n] 2006.257.18:20:33.11#ibcon#*before write, iclass 30, count 0 2006.257.18:20:33.11#ibcon#enter sib2, iclass 30, count 0 2006.257.18:20:33.11#ibcon#flushed, iclass 30, count 0 2006.257.18:20:33.11#ibcon#about to write, iclass 30, count 0 2006.257.18:20:33.11#ibcon#wrote, iclass 30, count 0 2006.257.18:20:33.11#ibcon#about to read 3, iclass 30, count 0 2006.257.18:20:33.14#ibcon#read 3, iclass 30, count 0 2006.257.18:20:33.14#ibcon#about to read 4, iclass 30, count 0 2006.257.18:20:33.14#ibcon#read 4, iclass 30, count 0 2006.257.18:20:33.14#ibcon#about to read 5, iclass 30, count 0 2006.257.18:20:33.14#ibcon#read 5, iclass 30, count 0 2006.257.18:20:33.14#ibcon#about to read 6, iclass 30, count 0 2006.257.18:20:33.14#ibcon#read 6, iclass 30, count 0 2006.257.18:20:33.14#ibcon#end of sib2, iclass 30, count 0 2006.257.18:20:33.14#ibcon#*after write, iclass 30, count 0 2006.257.18:20:33.14#ibcon#*before return 0, iclass 30, count 0 2006.257.18:20:33.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:33.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:20:33.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.18:20:33.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.18:20:33.14$vck44/vblo=4,679.99 2006.257.18:20:33.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.18:20:33.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.18:20:33.14#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:33.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:33.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:33.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:33.14#ibcon#enter wrdev, iclass 32, count 0 2006.257.18:20:33.14#ibcon#first serial, iclass 32, count 0 2006.257.18:20:33.14#ibcon#enter sib2, iclass 32, count 0 2006.257.18:20:33.14#ibcon#flushed, iclass 32, count 0 2006.257.18:20:33.14#ibcon#about to write, iclass 32, count 0 2006.257.18:20:33.14#ibcon#wrote, iclass 32, count 0 2006.257.18:20:33.14#ibcon#about to read 3, iclass 32, count 0 2006.257.18:20:33.16#ibcon#read 3, iclass 32, count 0 2006.257.18:20:33.16#ibcon#about to read 4, iclass 32, count 0 2006.257.18:20:33.16#ibcon#read 4, iclass 32, count 0 2006.257.18:20:33.16#ibcon#about to read 5, iclass 32, count 0 2006.257.18:20:33.16#ibcon#read 5, iclass 32, count 0 2006.257.18:20:33.16#ibcon#about to read 6, iclass 32, count 0 2006.257.18:20:33.16#ibcon#read 6, iclass 32, count 0 2006.257.18:20:33.16#ibcon#end of sib2, iclass 32, count 0 2006.257.18:20:33.16#ibcon#*mode == 0, iclass 32, count 0 2006.257.18:20:33.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.18:20:33.16#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:20:33.16#ibcon#*before write, iclass 32, count 0 2006.257.18:20:33.16#ibcon#enter sib2, iclass 32, count 0 2006.257.18:20:33.16#ibcon#flushed, iclass 32, count 0 2006.257.18:20:33.16#ibcon#about to write, iclass 32, count 0 2006.257.18:20:33.16#ibcon#wrote, iclass 32, count 0 2006.257.18:20:33.16#ibcon#about to read 3, iclass 32, count 0 2006.257.18:20:33.20#ibcon#read 3, iclass 32, count 0 2006.257.18:20:33.20#ibcon#about to read 4, iclass 32, count 0 2006.257.18:20:33.20#ibcon#read 4, iclass 32, count 0 2006.257.18:20:33.20#ibcon#about to read 5, iclass 32, count 0 2006.257.18:20:33.20#ibcon#read 5, iclass 32, count 0 2006.257.18:20:33.20#ibcon#about to read 6, iclass 32, count 0 2006.257.18:20:33.20#ibcon#read 6, iclass 32, count 0 2006.257.18:20:33.20#ibcon#end of sib2, iclass 32, count 0 2006.257.18:20:33.20#ibcon#*after write, iclass 32, count 0 2006.257.18:20:33.20#ibcon#*before return 0, iclass 32, count 0 2006.257.18:20:33.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:33.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:20:33.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.18:20:33.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.18:20:33.20$vck44/vb=4,5 2006.257.18:20:33.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.18:20:33.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.18:20:33.20#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:33.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:33.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:33.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:33.26#ibcon#enter wrdev, iclass 34, count 2 2006.257.18:20:33.26#ibcon#first serial, iclass 34, count 2 2006.257.18:20:33.26#ibcon#enter sib2, iclass 34, count 2 2006.257.18:20:33.26#ibcon#flushed, iclass 34, count 2 2006.257.18:20:33.26#ibcon#about to write, iclass 34, count 2 2006.257.18:20:33.26#ibcon#wrote, iclass 34, count 2 2006.257.18:20:33.26#ibcon#about to read 3, iclass 34, count 2 2006.257.18:20:33.28#ibcon#read 3, iclass 34, count 2 2006.257.18:20:33.28#ibcon#about to read 4, iclass 34, count 2 2006.257.18:20:33.28#ibcon#read 4, iclass 34, count 2 2006.257.18:20:33.28#ibcon#about to read 5, iclass 34, count 2 2006.257.18:20:33.28#ibcon#read 5, iclass 34, count 2 2006.257.18:20:33.28#ibcon#about to read 6, iclass 34, count 2 2006.257.18:20:33.28#ibcon#read 6, iclass 34, count 2 2006.257.18:20:33.28#ibcon#end of sib2, iclass 34, count 2 2006.257.18:20:33.28#ibcon#*mode == 0, iclass 34, count 2 2006.257.18:20:33.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.18:20:33.28#ibcon#[27=AT04-05\r\n] 2006.257.18:20:33.28#ibcon#*before write, iclass 34, count 2 2006.257.18:20:33.28#ibcon#enter sib2, iclass 34, count 2 2006.257.18:20:33.28#ibcon#flushed, iclass 34, count 2 2006.257.18:20:33.28#ibcon#about to write, iclass 34, count 2 2006.257.18:20:33.28#ibcon#wrote, iclass 34, count 2 2006.257.18:20:33.28#ibcon#about to read 3, iclass 34, count 2 2006.257.18:20:33.31#ibcon#read 3, iclass 34, count 2 2006.257.18:20:33.31#ibcon#about to read 4, iclass 34, count 2 2006.257.18:20:33.31#ibcon#read 4, iclass 34, count 2 2006.257.18:20:33.31#ibcon#about to read 5, iclass 34, count 2 2006.257.18:20:33.31#ibcon#read 5, iclass 34, count 2 2006.257.18:20:33.31#ibcon#about to read 6, iclass 34, count 2 2006.257.18:20:33.31#ibcon#read 6, iclass 34, count 2 2006.257.18:20:33.31#ibcon#end of sib2, iclass 34, count 2 2006.257.18:20:33.31#ibcon#*after write, iclass 34, count 2 2006.257.18:20:33.31#ibcon#*before return 0, iclass 34, count 2 2006.257.18:20:33.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:33.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:20:33.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.18:20:33.31#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:33.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:33.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:33.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:33.43#ibcon#enter wrdev, iclass 34, count 0 2006.257.18:20:33.43#ibcon#first serial, iclass 34, count 0 2006.257.18:20:33.43#ibcon#enter sib2, iclass 34, count 0 2006.257.18:20:33.43#ibcon#flushed, iclass 34, count 0 2006.257.18:20:33.43#ibcon#about to write, iclass 34, count 0 2006.257.18:20:33.43#ibcon#wrote, iclass 34, count 0 2006.257.18:20:33.43#ibcon#about to read 3, iclass 34, count 0 2006.257.18:20:33.45#ibcon#read 3, iclass 34, count 0 2006.257.18:20:33.45#ibcon#about to read 4, iclass 34, count 0 2006.257.18:20:33.45#ibcon#read 4, iclass 34, count 0 2006.257.18:20:33.45#ibcon#about to read 5, iclass 34, count 0 2006.257.18:20:33.45#ibcon#read 5, iclass 34, count 0 2006.257.18:20:33.45#ibcon#about to read 6, iclass 34, count 0 2006.257.18:20:33.45#ibcon#read 6, iclass 34, count 0 2006.257.18:20:33.45#ibcon#end of sib2, iclass 34, count 0 2006.257.18:20:33.45#ibcon#*mode == 0, iclass 34, count 0 2006.257.18:20:33.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.18:20:33.45#ibcon#[27=USB\r\n] 2006.257.18:20:33.45#ibcon#*before write, iclass 34, count 0 2006.257.18:20:33.45#ibcon#enter sib2, iclass 34, count 0 2006.257.18:20:33.45#ibcon#flushed, iclass 34, count 0 2006.257.18:20:33.45#ibcon#about to write, iclass 34, count 0 2006.257.18:20:33.45#ibcon#wrote, iclass 34, count 0 2006.257.18:20:33.45#ibcon#about to read 3, iclass 34, count 0 2006.257.18:20:33.48#ibcon#read 3, iclass 34, count 0 2006.257.18:20:33.48#ibcon#about to read 4, iclass 34, count 0 2006.257.18:20:33.48#ibcon#read 4, iclass 34, count 0 2006.257.18:20:33.48#ibcon#about to read 5, iclass 34, count 0 2006.257.18:20:33.48#ibcon#read 5, iclass 34, count 0 2006.257.18:20:33.48#ibcon#about to read 6, iclass 34, count 0 2006.257.18:20:33.48#ibcon#read 6, iclass 34, count 0 2006.257.18:20:33.48#ibcon#end of sib2, iclass 34, count 0 2006.257.18:20:33.48#ibcon#*after write, iclass 34, count 0 2006.257.18:20:33.48#ibcon#*before return 0, iclass 34, count 0 2006.257.18:20:33.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:33.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:20:33.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.18:20:33.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.18:20:33.48$vck44/vblo=5,709.99 2006.257.18:20:33.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.18:20:33.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.18:20:33.48#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:33.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:33.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:33.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:33.48#ibcon#enter wrdev, iclass 36, count 0 2006.257.18:20:33.48#ibcon#first serial, iclass 36, count 0 2006.257.18:20:33.48#ibcon#enter sib2, iclass 36, count 0 2006.257.18:20:33.48#ibcon#flushed, iclass 36, count 0 2006.257.18:20:33.48#ibcon#about to write, iclass 36, count 0 2006.257.18:20:33.48#ibcon#wrote, iclass 36, count 0 2006.257.18:20:33.48#ibcon#about to read 3, iclass 36, count 0 2006.257.18:20:33.50#ibcon#read 3, iclass 36, count 0 2006.257.18:20:33.50#ibcon#about to read 4, iclass 36, count 0 2006.257.18:20:33.50#ibcon#read 4, iclass 36, count 0 2006.257.18:20:33.50#ibcon#about to read 5, iclass 36, count 0 2006.257.18:20:33.50#ibcon#read 5, iclass 36, count 0 2006.257.18:20:33.50#ibcon#about to read 6, iclass 36, count 0 2006.257.18:20:33.50#ibcon#read 6, iclass 36, count 0 2006.257.18:20:33.50#ibcon#end of sib2, iclass 36, count 0 2006.257.18:20:33.50#ibcon#*mode == 0, iclass 36, count 0 2006.257.18:20:33.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.18:20:33.50#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:20:33.50#ibcon#*before write, iclass 36, count 0 2006.257.18:20:33.50#ibcon#enter sib2, iclass 36, count 0 2006.257.18:20:33.50#ibcon#flushed, iclass 36, count 0 2006.257.18:20:33.50#ibcon#about to write, iclass 36, count 0 2006.257.18:20:33.50#ibcon#wrote, iclass 36, count 0 2006.257.18:20:33.50#ibcon#about to read 3, iclass 36, count 0 2006.257.18:20:33.54#ibcon#read 3, iclass 36, count 0 2006.257.18:20:33.54#ibcon#about to read 4, iclass 36, count 0 2006.257.18:20:33.54#ibcon#read 4, iclass 36, count 0 2006.257.18:20:33.54#ibcon#about to read 5, iclass 36, count 0 2006.257.18:20:33.54#ibcon#read 5, iclass 36, count 0 2006.257.18:20:33.54#ibcon#about to read 6, iclass 36, count 0 2006.257.18:20:33.54#ibcon#read 6, iclass 36, count 0 2006.257.18:20:33.54#ibcon#end of sib2, iclass 36, count 0 2006.257.18:20:33.54#ibcon#*after write, iclass 36, count 0 2006.257.18:20:33.54#ibcon#*before return 0, iclass 36, count 0 2006.257.18:20:33.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:33.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:20:33.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.18:20:33.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.18:20:33.54$vck44/vb=5,4 2006.257.18:20:33.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.18:20:33.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.18:20:33.54#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:33.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:33.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:33.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:33.60#ibcon#enter wrdev, iclass 38, count 2 2006.257.18:20:33.60#ibcon#first serial, iclass 38, count 2 2006.257.18:20:33.60#ibcon#enter sib2, iclass 38, count 2 2006.257.18:20:33.60#ibcon#flushed, iclass 38, count 2 2006.257.18:20:33.60#ibcon#about to write, iclass 38, count 2 2006.257.18:20:33.60#ibcon#wrote, iclass 38, count 2 2006.257.18:20:33.60#ibcon#about to read 3, iclass 38, count 2 2006.257.18:20:33.62#ibcon#read 3, iclass 38, count 2 2006.257.18:20:33.62#ibcon#about to read 4, iclass 38, count 2 2006.257.18:20:33.62#ibcon#read 4, iclass 38, count 2 2006.257.18:20:33.62#ibcon#about to read 5, iclass 38, count 2 2006.257.18:20:33.62#ibcon#read 5, iclass 38, count 2 2006.257.18:20:33.62#ibcon#about to read 6, iclass 38, count 2 2006.257.18:20:33.62#ibcon#read 6, iclass 38, count 2 2006.257.18:20:33.62#ibcon#end of sib2, iclass 38, count 2 2006.257.18:20:33.62#ibcon#*mode == 0, iclass 38, count 2 2006.257.18:20:33.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.18:20:33.62#ibcon#[27=AT05-04\r\n] 2006.257.18:20:33.62#ibcon#*before write, iclass 38, count 2 2006.257.18:20:33.62#ibcon#enter sib2, iclass 38, count 2 2006.257.18:20:33.62#ibcon#flushed, iclass 38, count 2 2006.257.18:20:33.62#ibcon#about to write, iclass 38, count 2 2006.257.18:20:33.62#ibcon#wrote, iclass 38, count 2 2006.257.18:20:33.62#ibcon#about to read 3, iclass 38, count 2 2006.257.18:20:33.65#ibcon#read 3, iclass 38, count 2 2006.257.18:20:33.65#ibcon#about to read 4, iclass 38, count 2 2006.257.18:20:33.65#ibcon#read 4, iclass 38, count 2 2006.257.18:20:33.65#ibcon#about to read 5, iclass 38, count 2 2006.257.18:20:33.65#ibcon#read 5, iclass 38, count 2 2006.257.18:20:33.65#ibcon#about to read 6, iclass 38, count 2 2006.257.18:20:33.65#ibcon#read 6, iclass 38, count 2 2006.257.18:20:33.65#ibcon#end of sib2, iclass 38, count 2 2006.257.18:20:33.65#ibcon#*after write, iclass 38, count 2 2006.257.18:20:33.65#ibcon#*before return 0, iclass 38, count 2 2006.257.18:20:33.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:33.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:20:33.65#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.18:20:33.65#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:33.65#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:33.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:33.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:33.77#ibcon#enter wrdev, iclass 38, count 0 2006.257.18:20:33.77#ibcon#first serial, iclass 38, count 0 2006.257.18:20:33.77#ibcon#enter sib2, iclass 38, count 0 2006.257.18:20:33.77#ibcon#flushed, iclass 38, count 0 2006.257.18:20:33.77#ibcon#about to write, iclass 38, count 0 2006.257.18:20:33.77#ibcon#wrote, iclass 38, count 0 2006.257.18:20:33.77#ibcon#about to read 3, iclass 38, count 0 2006.257.18:20:33.79#ibcon#read 3, iclass 38, count 0 2006.257.18:20:33.79#ibcon#about to read 4, iclass 38, count 0 2006.257.18:20:33.79#ibcon#read 4, iclass 38, count 0 2006.257.18:20:33.79#ibcon#about to read 5, iclass 38, count 0 2006.257.18:20:33.79#ibcon#read 5, iclass 38, count 0 2006.257.18:20:33.79#ibcon#about to read 6, iclass 38, count 0 2006.257.18:20:33.79#ibcon#read 6, iclass 38, count 0 2006.257.18:20:33.79#ibcon#end of sib2, iclass 38, count 0 2006.257.18:20:33.79#ibcon#*mode == 0, iclass 38, count 0 2006.257.18:20:33.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.18:20:33.79#ibcon#[27=USB\r\n] 2006.257.18:20:33.79#ibcon#*before write, iclass 38, count 0 2006.257.18:20:33.79#ibcon#enter sib2, iclass 38, count 0 2006.257.18:20:33.79#ibcon#flushed, iclass 38, count 0 2006.257.18:20:33.79#ibcon#about to write, iclass 38, count 0 2006.257.18:20:33.79#ibcon#wrote, iclass 38, count 0 2006.257.18:20:33.79#ibcon#about to read 3, iclass 38, count 0 2006.257.18:20:33.82#ibcon#read 3, iclass 38, count 0 2006.257.18:20:33.82#ibcon#about to read 4, iclass 38, count 0 2006.257.18:20:33.82#ibcon#read 4, iclass 38, count 0 2006.257.18:20:33.82#ibcon#about to read 5, iclass 38, count 0 2006.257.18:20:33.82#ibcon#read 5, iclass 38, count 0 2006.257.18:20:33.82#ibcon#about to read 6, iclass 38, count 0 2006.257.18:20:33.82#ibcon#read 6, iclass 38, count 0 2006.257.18:20:33.82#ibcon#end of sib2, iclass 38, count 0 2006.257.18:20:33.82#ibcon#*after write, iclass 38, count 0 2006.257.18:20:33.82#ibcon#*before return 0, iclass 38, count 0 2006.257.18:20:33.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:33.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:20:33.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.18:20:33.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.18:20:33.82$vck44/vblo=6,719.99 2006.257.18:20:33.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.18:20:33.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.18:20:33.82#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:33.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:33.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:33.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:33.82#ibcon#enter wrdev, iclass 40, count 0 2006.257.18:20:33.82#ibcon#first serial, iclass 40, count 0 2006.257.18:20:33.82#ibcon#enter sib2, iclass 40, count 0 2006.257.18:20:33.82#ibcon#flushed, iclass 40, count 0 2006.257.18:20:33.82#ibcon#about to write, iclass 40, count 0 2006.257.18:20:33.82#ibcon#wrote, iclass 40, count 0 2006.257.18:20:33.82#ibcon#about to read 3, iclass 40, count 0 2006.257.18:20:33.84#ibcon#read 3, iclass 40, count 0 2006.257.18:20:33.84#ibcon#about to read 4, iclass 40, count 0 2006.257.18:20:33.84#ibcon#read 4, iclass 40, count 0 2006.257.18:20:33.84#ibcon#about to read 5, iclass 40, count 0 2006.257.18:20:33.84#ibcon#read 5, iclass 40, count 0 2006.257.18:20:33.84#ibcon#about to read 6, iclass 40, count 0 2006.257.18:20:33.84#ibcon#read 6, iclass 40, count 0 2006.257.18:20:33.84#ibcon#end of sib2, iclass 40, count 0 2006.257.18:20:33.84#ibcon#*mode == 0, iclass 40, count 0 2006.257.18:20:33.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.18:20:33.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:20:33.84#ibcon#*before write, iclass 40, count 0 2006.257.18:20:33.84#ibcon#enter sib2, iclass 40, count 0 2006.257.18:20:33.84#ibcon#flushed, iclass 40, count 0 2006.257.18:20:33.84#ibcon#about to write, iclass 40, count 0 2006.257.18:20:33.84#ibcon#wrote, iclass 40, count 0 2006.257.18:20:33.84#ibcon#about to read 3, iclass 40, count 0 2006.257.18:20:33.88#ibcon#read 3, iclass 40, count 0 2006.257.18:20:33.88#ibcon#about to read 4, iclass 40, count 0 2006.257.18:20:33.88#ibcon#read 4, iclass 40, count 0 2006.257.18:20:33.88#ibcon#about to read 5, iclass 40, count 0 2006.257.18:20:33.88#ibcon#read 5, iclass 40, count 0 2006.257.18:20:33.88#ibcon#about to read 6, iclass 40, count 0 2006.257.18:20:33.88#ibcon#read 6, iclass 40, count 0 2006.257.18:20:33.88#ibcon#end of sib2, iclass 40, count 0 2006.257.18:20:33.88#ibcon#*after write, iclass 40, count 0 2006.257.18:20:33.88#ibcon#*before return 0, iclass 40, count 0 2006.257.18:20:33.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:33.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:20:33.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.18:20:33.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.18:20:33.88$vck44/vb=6,4 2006.257.18:20:33.88#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.18:20:33.88#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.18:20:33.88#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:33.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:33.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:33.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:33.94#ibcon#enter wrdev, iclass 4, count 2 2006.257.18:20:33.94#ibcon#first serial, iclass 4, count 2 2006.257.18:20:33.94#ibcon#enter sib2, iclass 4, count 2 2006.257.18:20:33.94#ibcon#flushed, iclass 4, count 2 2006.257.18:20:33.94#ibcon#about to write, iclass 4, count 2 2006.257.18:20:33.94#ibcon#wrote, iclass 4, count 2 2006.257.18:20:33.94#ibcon#about to read 3, iclass 4, count 2 2006.257.18:20:33.96#ibcon#read 3, iclass 4, count 2 2006.257.18:20:33.96#ibcon#about to read 4, iclass 4, count 2 2006.257.18:20:33.96#ibcon#read 4, iclass 4, count 2 2006.257.18:20:33.96#ibcon#about to read 5, iclass 4, count 2 2006.257.18:20:33.96#ibcon#read 5, iclass 4, count 2 2006.257.18:20:33.96#ibcon#about to read 6, iclass 4, count 2 2006.257.18:20:33.96#ibcon#read 6, iclass 4, count 2 2006.257.18:20:33.96#ibcon#end of sib2, iclass 4, count 2 2006.257.18:20:33.96#ibcon#*mode == 0, iclass 4, count 2 2006.257.18:20:33.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.18:20:33.96#ibcon#[27=AT06-04\r\n] 2006.257.18:20:33.96#ibcon#*before write, iclass 4, count 2 2006.257.18:20:33.96#ibcon#enter sib2, iclass 4, count 2 2006.257.18:20:33.96#ibcon#flushed, iclass 4, count 2 2006.257.18:20:33.96#ibcon#about to write, iclass 4, count 2 2006.257.18:20:33.96#ibcon#wrote, iclass 4, count 2 2006.257.18:20:33.96#ibcon#about to read 3, iclass 4, count 2 2006.257.18:20:33.99#ibcon#read 3, iclass 4, count 2 2006.257.18:20:33.99#ibcon#about to read 4, iclass 4, count 2 2006.257.18:20:33.99#ibcon#read 4, iclass 4, count 2 2006.257.18:20:33.99#ibcon#about to read 5, iclass 4, count 2 2006.257.18:20:33.99#ibcon#read 5, iclass 4, count 2 2006.257.18:20:33.99#ibcon#about to read 6, iclass 4, count 2 2006.257.18:20:33.99#ibcon#read 6, iclass 4, count 2 2006.257.18:20:33.99#ibcon#end of sib2, iclass 4, count 2 2006.257.18:20:33.99#ibcon#*after write, iclass 4, count 2 2006.257.18:20:33.99#ibcon#*before return 0, iclass 4, count 2 2006.257.18:20:33.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:33.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:20:33.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.18:20:33.99#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:33.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:34.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:34.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:34.11#ibcon#enter wrdev, iclass 4, count 0 2006.257.18:20:34.11#ibcon#first serial, iclass 4, count 0 2006.257.18:20:34.11#ibcon#enter sib2, iclass 4, count 0 2006.257.18:20:34.11#ibcon#flushed, iclass 4, count 0 2006.257.18:20:34.11#ibcon#about to write, iclass 4, count 0 2006.257.18:20:34.11#ibcon#wrote, iclass 4, count 0 2006.257.18:20:34.11#ibcon#about to read 3, iclass 4, count 0 2006.257.18:20:34.13#ibcon#read 3, iclass 4, count 0 2006.257.18:20:34.13#ibcon#about to read 4, iclass 4, count 0 2006.257.18:20:34.13#ibcon#read 4, iclass 4, count 0 2006.257.18:20:34.13#ibcon#about to read 5, iclass 4, count 0 2006.257.18:20:34.13#ibcon#read 5, iclass 4, count 0 2006.257.18:20:34.13#ibcon#about to read 6, iclass 4, count 0 2006.257.18:20:34.13#ibcon#read 6, iclass 4, count 0 2006.257.18:20:34.13#ibcon#end of sib2, iclass 4, count 0 2006.257.18:20:34.13#ibcon#*mode == 0, iclass 4, count 0 2006.257.18:20:34.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.18:20:34.13#ibcon#[27=USB\r\n] 2006.257.18:20:34.13#ibcon#*before write, iclass 4, count 0 2006.257.18:20:34.13#ibcon#enter sib2, iclass 4, count 0 2006.257.18:20:34.13#ibcon#flushed, iclass 4, count 0 2006.257.18:20:34.13#ibcon#about to write, iclass 4, count 0 2006.257.18:20:34.13#ibcon#wrote, iclass 4, count 0 2006.257.18:20:34.13#ibcon#about to read 3, iclass 4, count 0 2006.257.18:20:34.16#ibcon#read 3, iclass 4, count 0 2006.257.18:20:34.16#ibcon#about to read 4, iclass 4, count 0 2006.257.18:20:34.16#ibcon#read 4, iclass 4, count 0 2006.257.18:20:34.16#ibcon#about to read 5, iclass 4, count 0 2006.257.18:20:34.16#ibcon#read 5, iclass 4, count 0 2006.257.18:20:34.16#ibcon#about to read 6, iclass 4, count 0 2006.257.18:20:34.16#ibcon#read 6, iclass 4, count 0 2006.257.18:20:34.16#ibcon#end of sib2, iclass 4, count 0 2006.257.18:20:34.16#ibcon#*after write, iclass 4, count 0 2006.257.18:20:34.16#ibcon#*before return 0, iclass 4, count 0 2006.257.18:20:34.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:34.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:20:34.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.18:20:34.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.18:20:34.16$vck44/vblo=7,734.99 2006.257.18:20:34.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.18:20:34.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.18:20:34.16#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:34.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:34.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:34.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:34.16#ibcon#enter wrdev, iclass 6, count 0 2006.257.18:20:34.16#ibcon#first serial, iclass 6, count 0 2006.257.18:20:34.16#ibcon#enter sib2, iclass 6, count 0 2006.257.18:20:34.16#ibcon#flushed, iclass 6, count 0 2006.257.18:20:34.16#ibcon#about to write, iclass 6, count 0 2006.257.18:20:34.16#ibcon#wrote, iclass 6, count 0 2006.257.18:20:34.16#ibcon#about to read 3, iclass 6, count 0 2006.257.18:20:34.18#ibcon#read 3, iclass 6, count 0 2006.257.18:20:34.18#ibcon#about to read 4, iclass 6, count 0 2006.257.18:20:34.18#ibcon#read 4, iclass 6, count 0 2006.257.18:20:34.18#ibcon#about to read 5, iclass 6, count 0 2006.257.18:20:34.18#ibcon#read 5, iclass 6, count 0 2006.257.18:20:34.18#ibcon#about to read 6, iclass 6, count 0 2006.257.18:20:34.18#ibcon#read 6, iclass 6, count 0 2006.257.18:20:34.18#ibcon#end of sib2, iclass 6, count 0 2006.257.18:20:34.18#ibcon#*mode == 0, iclass 6, count 0 2006.257.18:20:34.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.18:20:34.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:20:34.18#ibcon#*before write, iclass 6, count 0 2006.257.18:20:34.18#ibcon#enter sib2, iclass 6, count 0 2006.257.18:20:34.18#ibcon#flushed, iclass 6, count 0 2006.257.18:20:34.18#ibcon#about to write, iclass 6, count 0 2006.257.18:20:34.18#ibcon#wrote, iclass 6, count 0 2006.257.18:20:34.18#ibcon#about to read 3, iclass 6, count 0 2006.257.18:20:34.22#ibcon#read 3, iclass 6, count 0 2006.257.18:20:34.22#ibcon#about to read 4, iclass 6, count 0 2006.257.18:20:34.22#ibcon#read 4, iclass 6, count 0 2006.257.18:20:34.22#ibcon#about to read 5, iclass 6, count 0 2006.257.18:20:34.22#ibcon#read 5, iclass 6, count 0 2006.257.18:20:34.22#ibcon#about to read 6, iclass 6, count 0 2006.257.18:20:34.22#ibcon#read 6, iclass 6, count 0 2006.257.18:20:34.22#ibcon#end of sib2, iclass 6, count 0 2006.257.18:20:34.22#ibcon#*after write, iclass 6, count 0 2006.257.18:20:34.22#ibcon#*before return 0, iclass 6, count 0 2006.257.18:20:34.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:34.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:20:34.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.18:20:34.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.18:20:34.22$vck44/vb=7,4 2006.257.18:20:34.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.18:20:34.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.18:20:34.22#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:34.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:34.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:34.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:34.28#ibcon#enter wrdev, iclass 10, count 2 2006.257.18:20:34.28#ibcon#first serial, iclass 10, count 2 2006.257.18:20:34.28#ibcon#enter sib2, iclass 10, count 2 2006.257.18:20:34.28#ibcon#flushed, iclass 10, count 2 2006.257.18:20:34.28#ibcon#about to write, iclass 10, count 2 2006.257.18:20:34.28#ibcon#wrote, iclass 10, count 2 2006.257.18:20:34.28#ibcon#about to read 3, iclass 10, count 2 2006.257.18:20:34.30#ibcon#read 3, iclass 10, count 2 2006.257.18:20:34.30#ibcon#about to read 4, iclass 10, count 2 2006.257.18:20:34.30#ibcon#read 4, iclass 10, count 2 2006.257.18:20:34.30#ibcon#about to read 5, iclass 10, count 2 2006.257.18:20:34.30#ibcon#read 5, iclass 10, count 2 2006.257.18:20:34.30#ibcon#about to read 6, iclass 10, count 2 2006.257.18:20:34.30#ibcon#read 6, iclass 10, count 2 2006.257.18:20:34.30#ibcon#end of sib2, iclass 10, count 2 2006.257.18:20:34.30#ibcon#*mode == 0, iclass 10, count 2 2006.257.18:20:34.30#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.18:20:34.30#ibcon#[27=AT07-04\r\n] 2006.257.18:20:34.30#ibcon#*before write, iclass 10, count 2 2006.257.18:20:34.30#ibcon#enter sib2, iclass 10, count 2 2006.257.18:20:34.30#ibcon#flushed, iclass 10, count 2 2006.257.18:20:34.30#ibcon#about to write, iclass 10, count 2 2006.257.18:20:34.30#ibcon#wrote, iclass 10, count 2 2006.257.18:20:34.30#ibcon#about to read 3, iclass 10, count 2 2006.257.18:20:34.33#ibcon#read 3, iclass 10, count 2 2006.257.18:20:34.33#ibcon#about to read 4, iclass 10, count 2 2006.257.18:20:34.33#ibcon#read 4, iclass 10, count 2 2006.257.18:20:34.33#ibcon#about to read 5, iclass 10, count 2 2006.257.18:20:34.33#ibcon#read 5, iclass 10, count 2 2006.257.18:20:34.33#ibcon#about to read 6, iclass 10, count 2 2006.257.18:20:34.33#ibcon#read 6, iclass 10, count 2 2006.257.18:20:34.33#ibcon#end of sib2, iclass 10, count 2 2006.257.18:20:34.33#ibcon#*after write, iclass 10, count 2 2006.257.18:20:34.33#ibcon#*before return 0, iclass 10, count 2 2006.257.18:20:34.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:34.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:20:34.33#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.18:20:34.33#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:34.33#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:34.45#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:34.45#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:34.45#ibcon#enter wrdev, iclass 10, count 0 2006.257.18:20:34.45#ibcon#first serial, iclass 10, count 0 2006.257.18:20:34.45#ibcon#enter sib2, iclass 10, count 0 2006.257.18:20:34.45#ibcon#flushed, iclass 10, count 0 2006.257.18:20:34.45#ibcon#about to write, iclass 10, count 0 2006.257.18:20:34.45#ibcon#wrote, iclass 10, count 0 2006.257.18:20:34.45#ibcon#about to read 3, iclass 10, count 0 2006.257.18:20:34.47#ibcon#read 3, iclass 10, count 0 2006.257.18:20:34.47#ibcon#about to read 4, iclass 10, count 0 2006.257.18:20:34.47#ibcon#read 4, iclass 10, count 0 2006.257.18:20:34.47#ibcon#about to read 5, iclass 10, count 0 2006.257.18:20:34.47#ibcon#read 5, iclass 10, count 0 2006.257.18:20:34.47#ibcon#about to read 6, iclass 10, count 0 2006.257.18:20:34.47#ibcon#read 6, iclass 10, count 0 2006.257.18:20:34.47#ibcon#end of sib2, iclass 10, count 0 2006.257.18:20:34.47#ibcon#*mode == 0, iclass 10, count 0 2006.257.18:20:34.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.18:20:34.47#ibcon#[27=USB\r\n] 2006.257.18:20:34.47#ibcon#*before write, iclass 10, count 0 2006.257.18:20:34.47#ibcon#enter sib2, iclass 10, count 0 2006.257.18:20:34.47#ibcon#flushed, iclass 10, count 0 2006.257.18:20:34.47#ibcon#about to write, iclass 10, count 0 2006.257.18:20:34.47#ibcon#wrote, iclass 10, count 0 2006.257.18:20:34.47#ibcon#about to read 3, iclass 10, count 0 2006.257.18:20:34.50#ibcon#read 3, iclass 10, count 0 2006.257.18:20:34.50#ibcon#about to read 4, iclass 10, count 0 2006.257.18:20:34.50#ibcon#read 4, iclass 10, count 0 2006.257.18:20:34.50#ibcon#about to read 5, iclass 10, count 0 2006.257.18:20:34.50#ibcon#read 5, iclass 10, count 0 2006.257.18:20:34.50#ibcon#about to read 6, iclass 10, count 0 2006.257.18:20:34.50#ibcon#read 6, iclass 10, count 0 2006.257.18:20:34.50#ibcon#end of sib2, iclass 10, count 0 2006.257.18:20:34.50#ibcon#*after write, iclass 10, count 0 2006.257.18:20:34.50#ibcon#*before return 0, iclass 10, count 0 2006.257.18:20:34.50#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:34.50#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:20:34.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.18:20:34.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.18:20:34.50$vck44/vblo=8,744.99 2006.257.18:20:34.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.18:20:34.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.18:20:34.50#ibcon#ireg 17 cls_cnt 0 2006.257.18:20:34.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:34.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:34.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:34.50#ibcon#enter wrdev, iclass 12, count 0 2006.257.18:20:34.50#ibcon#first serial, iclass 12, count 0 2006.257.18:20:34.50#ibcon#enter sib2, iclass 12, count 0 2006.257.18:20:34.50#ibcon#flushed, iclass 12, count 0 2006.257.18:20:34.50#ibcon#about to write, iclass 12, count 0 2006.257.18:20:34.50#ibcon#wrote, iclass 12, count 0 2006.257.18:20:34.50#ibcon#about to read 3, iclass 12, count 0 2006.257.18:20:34.52#ibcon#read 3, iclass 12, count 0 2006.257.18:20:34.52#ibcon#about to read 4, iclass 12, count 0 2006.257.18:20:34.52#ibcon#read 4, iclass 12, count 0 2006.257.18:20:34.52#ibcon#about to read 5, iclass 12, count 0 2006.257.18:20:34.52#ibcon#read 5, iclass 12, count 0 2006.257.18:20:34.52#ibcon#about to read 6, iclass 12, count 0 2006.257.18:20:34.52#ibcon#read 6, iclass 12, count 0 2006.257.18:20:34.52#ibcon#end of sib2, iclass 12, count 0 2006.257.18:20:34.52#ibcon#*mode == 0, iclass 12, count 0 2006.257.18:20:34.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.18:20:34.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:20:34.52#ibcon#*before write, iclass 12, count 0 2006.257.18:20:34.52#ibcon#enter sib2, iclass 12, count 0 2006.257.18:20:34.52#ibcon#flushed, iclass 12, count 0 2006.257.18:20:34.52#ibcon#about to write, iclass 12, count 0 2006.257.18:20:34.52#ibcon#wrote, iclass 12, count 0 2006.257.18:20:34.52#ibcon#about to read 3, iclass 12, count 0 2006.257.18:20:34.56#ibcon#read 3, iclass 12, count 0 2006.257.18:20:34.56#ibcon#about to read 4, iclass 12, count 0 2006.257.18:20:34.56#ibcon#read 4, iclass 12, count 0 2006.257.18:20:34.56#ibcon#about to read 5, iclass 12, count 0 2006.257.18:20:34.56#ibcon#read 5, iclass 12, count 0 2006.257.18:20:34.56#ibcon#about to read 6, iclass 12, count 0 2006.257.18:20:34.56#ibcon#read 6, iclass 12, count 0 2006.257.18:20:34.56#ibcon#end of sib2, iclass 12, count 0 2006.257.18:20:34.56#ibcon#*after write, iclass 12, count 0 2006.257.18:20:34.56#ibcon#*before return 0, iclass 12, count 0 2006.257.18:20:34.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:34.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:20:34.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.18:20:34.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.18:20:34.56$vck44/vb=8,4 2006.257.18:20:34.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.18:20:34.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.18:20:34.56#ibcon#ireg 11 cls_cnt 2 2006.257.18:20:34.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:34.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:34.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:34.62#ibcon#enter wrdev, iclass 14, count 2 2006.257.18:20:34.62#ibcon#first serial, iclass 14, count 2 2006.257.18:20:34.62#ibcon#enter sib2, iclass 14, count 2 2006.257.18:20:34.62#ibcon#flushed, iclass 14, count 2 2006.257.18:20:34.62#ibcon#about to write, iclass 14, count 2 2006.257.18:20:34.62#ibcon#wrote, iclass 14, count 2 2006.257.18:20:34.62#ibcon#about to read 3, iclass 14, count 2 2006.257.18:20:34.64#ibcon#read 3, iclass 14, count 2 2006.257.18:20:34.64#ibcon#about to read 4, iclass 14, count 2 2006.257.18:20:34.64#ibcon#read 4, iclass 14, count 2 2006.257.18:20:34.64#ibcon#about to read 5, iclass 14, count 2 2006.257.18:20:34.64#ibcon#read 5, iclass 14, count 2 2006.257.18:20:34.64#ibcon#about to read 6, iclass 14, count 2 2006.257.18:20:34.64#ibcon#read 6, iclass 14, count 2 2006.257.18:20:34.64#ibcon#end of sib2, iclass 14, count 2 2006.257.18:20:34.64#ibcon#*mode == 0, iclass 14, count 2 2006.257.18:20:34.64#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.18:20:34.64#ibcon#[27=AT08-04\r\n] 2006.257.18:20:34.64#ibcon#*before write, iclass 14, count 2 2006.257.18:20:34.64#ibcon#enter sib2, iclass 14, count 2 2006.257.18:20:34.64#ibcon#flushed, iclass 14, count 2 2006.257.18:20:34.64#ibcon#about to write, iclass 14, count 2 2006.257.18:20:34.64#ibcon#wrote, iclass 14, count 2 2006.257.18:20:34.64#ibcon#about to read 3, iclass 14, count 2 2006.257.18:20:34.67#ibcon#read 3, iclass 14, count 2 2006.257.18:20:34.67#ibcon#about to read 4, iclass 14, count 2 2006.257.18:20:34.67#ibcon#read 4, iclass 14, count 2 2006.257.18:20:34.67#ibcon#about to read 5, iclass 14, count 2 2006.257.18:20:34.67#ibcon#read 5, iclass 14, count 2 2006.257.18:20:34.67#ibcon#about to read 6, iclass 14, count 2 2006.257.18:20:34.67#ibcon#read 6, iclass 14, count 2 2006.257.18:20:34.67#ibcon#end of sib2, iclass 14, count 2 2006.257.18:20:34.67#ibcon#*after write, iclass 14, count 2 2006.257.18:20:34.67#ibcon#*before return 0, iclass 14, count 2 2006.257.18:20:34.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:34.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:20:34.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.18:20:34.67#ibcon#ireg 7 cls_cnt 0 2006.257.18:20:34.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:34.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:34.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:34.79#ibcon#enter wrdev, iclass 14, count 0 2006.257.18:20:34.79#ibcon#first serial, iclass 14, count 0 2006.257.18:20:34.79#ibcon#enter sib2, iclass 14, count 0 2006.257.18:20:34.79#ibcon#flushed, iclass 14, count 0 2006.257.18:20:34.79#ibcon#about to write, iclass 14, count 0 2006.257.18:20:34.79#ibcon#wrote, iclass 14, count 0 2006.257.18:20:34.79#ibcon#about to read 3, iclass 14, count 0 2006.257.18:20:34.81#ibcon#read 3, iclass 14, count 0 2006.257.18:20:34.81#ibcon#about to read 4, iclass 14, count 0 2006.257.18:20:34.81#ibcon#read 4, iclass 14, count 0 2006.257.18:20:34.81#ibcon#about to read 5, iclass 14, count 0 2006.257.18:20:34.81#ibcon#read 5, iclass 14, count 0 2006.257.18:20:34.81#ibcon#about to read 6, iclass 14, count 0 2006.257.18:20:34.81#ibcon#read 6, iclass 14, count 0 2006.257.18:20:34.81#ibcon#end of sib2, iclass 14, count 0 2006.257.18:20:34.81#ibcon#*mode == 0, iclass 14, count 0 2006.257.18:20:34.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.18:20:34.81#ibcon#[27=USB\r\n] 2006.257.18:20:34.81#ibcon#*before write, iclass 14, count 0 2006.257.18:20:34.81#ibcon#enter sib2, iclass 14, count 0 2006.257.18:20:34.81#ibcon#flushed, iclass 14, count 0 2006.257.18:20:34.81#ibcon#about to write, iclass 14, count 0 2006.257.18:20:34.81#ibcon#wrote, iclass 14, count 0 2006.257.18:20:34.81#ibcon#about to read 3, iclass 14, count 0 2006.257.18:20:34.84#ibcon#read 3, iclass 14, count 0 2006.257.18:20:34.84#ibcon#about to read 4, iclass 14, count 0 2006.257.18:20:34.84#ibcon#read 4, iclass 14, count 0 2006.257.18:20:34.84#ibcon#about to read 5, iclass 14, count 0 2006.257.18:20:34.84#ibcon#read 5, iclass 14, count 0 2006.257.18:20:34.84#ibcon#about to read 6, iclass 14, count 0 2006.257.18:20:34.84#ibcon#read 6, iclass 14, count 0 2006.257.18:20:34.84#ibcon#end of sib2, iclass 14, count 0 2006.257.18:20:34.84#ibcon#*after write, iclass 14, count 0 2006.257.18:20:34.84#ibcon#*before return 0, iclass 14, count 0 2006.257.18:20:34.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:34.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:20:34.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.18:20:34.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.18:20:34.84$vck44/vabw=wide 2006.257.18:20:34.84#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.18:20:34.84#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.18:20:34.84#ibcon#ireg 8 cls_cnt 0 2006.257.18:20:34.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:34.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:34.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:34.84#ibcon#enter wrdev, iclass 16, count 0 2006.257.18:20:34.84#ibcon#first serial, iclass 16, count 0 2006.257.18:20:34.84#ibcon#enter sib2, iclass 16, count 0 2006.257.18:20:34.84#ibcon#flushed, iclass 16, count 0 2006.257.18:20:34.84#ibcon#about to write, iclass 16, count 0 2006.257.18:20:34.84#ibcon#wrote, iclass 16, count 0 2006.257.18:20:34.84#ibcon#about to read 3, iclass 16, count 0 2006.257.18:20:34.86#ibcon#read 3, iclass 16, count 0 2006.257.18:20:34.86#ibcon#about to read 4, iclass 16, count 0 2006.257.18:20:34.86#ibcon#read 4, iclass 16, count 0 2006.257.18:20:34.86#ibcon#about to read 5, iclass 16, count 0 2006.257.18:20:34.86#ibcon#read 5, iclass 16, count 0 2006.257.18:20:34.86#ibcon#about to read 6, iclass 16, count 0 2006.257.18:20:34.86#ibcon#read 6, iclass 16, count 0 2006.257.18:20:34.86#ibcon#end of sib2, iclass 16, count 0 2006.257.18:20:34.86#ibcon#*mode == 0, iclass 16, count 0 2006.257.18:20:34.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.18:20:34.86#ibcon#[25=BW32\r\n] 2006.257.18:20:34.86#ibcon#*before write, iclass 16, count 0 2006.257.18:20:34.86#ibcon#enter sib2, iclass 16, count 0 2006.257.18:20:34.86#ibcon#flushed, iclass 16, count 0 2006.257.18:20:34.86#ibcon#about to write, iclass 16, count 0 2006.257.18:20:34.86#ibcon#wrote, iclass 16, count 0 2006.257.18:20:34.86#ibcon#about to read 3, iclass 16, count 0 2006.257.18:20:34.89#ibcon#read 3, iclass 16, count 0 2006.257.18:20:34.89#ibcon#about to read 4, iclass 16, count 0 2006.257.18:20:34.89#ibcon#read 4, iclass 16, count 0 2006.257.18:20:34.89#ibcon#about to read 5, iclass 16, count 0 2006.257.18:20:34.89#ibcon#read 5, iclass 16, count 0 2006.257.18:20:34.89#ibcon#about to read 6, iclass 16, count 0 2006.257.18:20:34.89#ibcon#read 6, iclass 16, count 0 2006.257.18:20:34.89#ibcon#end of sib2, iclass 16, count 0 2006.257.18:20:34.89#ibcon#*after write, iclass 16, count 0 2006.257.18:20:34.89#ibcon#*before return 0, iclass 16, count 0 2006.257.18:20:34.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:34.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:20:34.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.18:20:34.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.18:20:34.89$vck44/vbbw=wide 2006.257.18:20:34.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.18:20:34.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.18:20:34.89#ibcon#ireg 8 cls_cnt 0 2006.257.18:20:34.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:20:34.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:20:34.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:20:34.96#ibcon#enter wrdev, iclass 18, count 0 2006.257.18:20:34.96#ibcon#first serial, iclass 18, count 0 2006.257.18:20:34.96#ibcon#enter sib2, iclass 18, count 0 2006.257.18:20:34.96#ibcon#flushed, iclass 18, count 0 2006.257.18:20:34.96#ibcon#about to write, iclass 18, count 0 2006.257.18:20:34.96#ibcon#wrote, iclass 18, count 0 2006.257.18:20:34.96#ibcon#about to read 3, iclass 18, count 0 2006.257.18:20:34.98#ibcon#read 3, iclass 18, count 0 2006.257.18:20:34.98#ibcon#about to read 4, iclass 18, count 0 2006.257.18:20:34.98#ibcon#read 4, iclass 18, count 0 2006.257.18:20:34.98#ibcon#about to read 5, iclass 18, count 0 2006.257.18:20:34.98#ibcon#read 5, iclass 18, count 0 2006.257.18:20:34.98#ibcon#about to read 6, iclass 18, count 0 2006.257.18:20:34.98#ibcon#read 6, iclass 18, count 0 2006.257.18:20:34.98#ibcon#end of sib2, iclass 18, count 0 2006.257.18:20:34.98#ibcon#*mode == 0, iclass 18, count 0 2006.257.18:20:34.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.18:20:34.98#ibcon#[27=BW32\r\n] 2006.257.18:20:34.98#ibcon#*before write, iclass 18, count 0 2006.257.18:20:34.98#ibcon#enter sib2, iclass 18, count 0 2006.257.18:20:34.98#ibcon#flushed, iclass 18, count 0 2006.257.18:20:34.98#ibcon#about to write, iclass 18, count 0 2006.257.18:20:34.98#ibcon#wrote, iclass 18, count 0 2006.257.18:20:34.98#ibcon#about to read 3, iclass 18, count 0 2006.257.18:20:35.01#ibcon#read 3, iclass 18, count 0 2006.257.18:20:35.01#ibcon#about to read 4, iclass 18, count 0 2006.257.18:20:35.01#ibcon#read 4, iclass 18, count 0 2006.257.18:20:35.01#ibcon#about to read 5, iclass 18, count 0 2006.257.18:20:35.01#ibcon#read 5, iclass 18, count 0 2006.257.18:20:35.01#ibcon#about to read 6, iclass 18, count 0 2006.257.18:20:35.01#ibcon#read 6, iclass 18, count 0 2006.257.18:20:35.01#ibcon#end of sib2, iclass 18, count 0 2006.257.18:20:35.01#ibcon#*after write, iclass 18, count 0 2006.257.18:20:35.01#ibcon#*before return 0, iclass 18, count 0 2006.257.18:20:35.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:20:35.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:20:35.01#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.18:20:35.01#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.18:20:35.01$setupk4/ifdk4 2006.257.18:20:35.01$ifdk4/lo= 2006.257.18:20:35.01$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:20:35.01$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:20:35.01$ifdk4/patch= 2006.257.18:20:35.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:20:35.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:20:35.01$setupk4/!*+20s 2006.257.18:20:37.14#trakl#Source acquired 2006.257.18:20:37.14#flagr#flagr/antenna,acquired 2006.257.18:20:38.31#abcon#<5=/14 1.3 3.0 17.28 971014.3\r\n> 2006.257.18:20:38.33#abcon#{5=INTERFACE CLEAR} 2006.257.18:20:38.39#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:20:48.62#abcon#<5=/14 1.4 3.0 17.28 971014.3\r\n> 2006.257.18:20:48.64#abcon#{5=INTERFACE CLEAR} 2006.257.18:20:48.70#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:20:49.52$setupk4/"tpicd 2006.257.18:20:49.52$setupk4/echo=off 2006.257.18:20:49.52$setupk4/xlog=off 2006.257.18:20:49.52:!2006.257.18:20:56 2006.257.18:20:56.00:preob 2006.257.18:20:56.14/onsource/TRACKING 2006.257.18:20:56.14:!2006.257.18:21:06 2006.257.18:21:06.00:"tape 2006.257.18:21:06.00:"st=record 2006.257.18:21:06.00:data_valid=on 2006.257.18:21:06.00:midob 2006.257.18:21:07.14/onsource/TRACKING 2006.257.18:21:07.14/wx/17.28,1014.3,97 2006.257.18:21:07.32/cable/+6.4871E-03 2006.257.18:21:08.41/va/01,08,usb,yes,35,37 2006.257.18:21:08.41/va/02,07,usb,yes,37,38 2006.257.18:21:08.41/va/03,08,usb,yes,34,36 2006.257.18:21:08.41/va/04,07,usb,yes,38,40 2006.257.18:21:08.41/va/05,04,usb,yes,34,35 2006.257.18:21:08.41/va/06,04,usb,yes,38,38 2006.257.18:21:08.41/va/07,04,usb,yes,39,39 2006.257.18:21:08.41/va/08,04,usb,yes,33,40 2006.257.18:21:08.64/valo/01,524.99,yes,locked 2006.257.18:21:08.64/valo/02,534.99,yes,locked 2006.257.18:21:08.64/valo/03,564.99,yes,locked 2006.257.18:21:08.64/valo/04,624.99,yes,locked 2006.257.18:21:08.64/valo/05,734.99,yes,locked 2006.257.18:21:08.64/valo/06,814.99,yes,locked 2006.257.18:21:08.64/valo/07,864.99,yes,locked 2006.257.18:21:08.64/valo/08,884.99,yes,locked 2006.257.18:21:09.73/vb/01,04,usb,yes,32,29 2006.257.18:21:09.73/vb/02,05,usb,yes,30,30 2006.257.18:21:09.73/vb/03,04,usb,yes,31,34 2006.257.18:21:09.73/vb/04,05,usb,yes,31,30 2006.257.18:21:09.73/vb/05,04,usb,yes,27,30 2006.257.18:21:09.73/vb/06,04,usb,yes,32,28 2006.257.18:21:09.73/vb/07,04,usb,yes,32,32 2006.257.18:21:09.73/vb/08,04,usb,yes,29,33 2006.257.18:21:09.97/vblo/01,629.99,yes,locked 2006.257.18:21:09.97/vblo/02,634.99,yes,locked 2006.257.18:21:09.97/vblo/03,649.99,yes,locked 2006.257.18:21:09.97/vblo/04,679.99,yes,locked 2006.257.18:21:09.97/vblo/05,709.99,yes,locked 2006.257.18:21:09.97/vblo/06,719.99,yes,locked 2006.257.18:21:09.97/vblo/07,734.99,yes,locked 2006.257.18:21:09.97/vblo/08,744.99,yes,locked 2006.257.18:21:10.12/vabw/8 2006.257.18:21:10.27/vbbw/8 2006.257.18:21:10.36/xfe/off,on,15.0 2006.257.18:21:10.73/ifatt/23,28,28,28 2006.257.18:21:11.07/fmout-gps/S +4.53E-07 2006.257.18:21:11.11:!2006.257.18:23:16 2006.257.18:23:16.01:data_valid=off 2006.257.18:23:16.01:"et 2006.257.18:23:16.01:!+3s 2006.257.18:23:19.02:"tape 2006.257.18:23:19.02:postob 2006.257.18:23:19.19/cable/+6.4851E-03 2006.257.18:23:19.19/wx/17.29,1014.3,97 2006.257.18:23:19.25/fmout-gps/S +4.55E-07 2006.257.18:23:19.25:scan_name=257-1829,jd0609,190 2006.257.18:23:19.25:source=2201+315,220314.98,314538.3,2000.0,cw 2006.257.18:23:21.14#flagr#flagr/antenna,new-source 2006.257.18:23:21.14:checkk5 2006.257.18:23:21.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:23:21.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:23:22.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:23:22.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:23:22.83/chk_obsdata//k5ts1/T2571821??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.18:23:23.17/chk_obsdata//k5ts2/T2571821??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.18:23:23.50/chk_obsdata//k5ts3/T2571821??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.18:23:23.85/chk_obsdata//k5ts4/T2571821??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.18:23:24.50/k5log//k5ts1_log_newline 2006.257.18:23:25.15/k5log//k5ts2_log_newline 2006.257.18:23:25.80/k5log//k5ts3_log_newline 2006.257.18:23:26.45/k5log//k5ts4_log_newline 2006.257.18:23:26.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:23:26.47:setupk4=1 2006.257.18:23:26.48$setupk4/echo=on 2006.257.18:23:26.48$setupk4/pcalon 2006.257.18:23:26.48$pcalon/"no phase cal control is implemented here 2006.257.18:23:26.48$setupk4/"tpicd=stop 2006.257.18:23:26.48$setupk4/"rec=synch_on 2006.257.18:23:26.48$setupk4/"rec_mode=128 2006.257.18:23:26.48$setupk4/!* 2006.257.18:23:26.48$setupk4/recpk4 2006.257.18:23:26.48$recpk4/recpatch= 2006.257.18:23:26.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:23:26.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:23:26.48$setupk4/vck44 2006.257.18:23:26.48$vck44/valo=1,524.99 2006.257.18:23:26.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.18:23:26.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.18:23:26.48#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:26.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:26.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:26.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:26.48#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:23:26.48#ibcon#first serial, iclass 19, count 0 2006.257.18:23:26.48#ibcon#enter sib2, iclass 19, count 0 2006.257.18:23:26.48#ibcon#flushed, iclass 19, count 0 2006.257.18:23:26.48#ibcon#about to write, iclass 19, count 0 2006.257.18:23:26.48#ibcon#wrote, iclass 19, count 0 2006.257.18:23:26.48#ibcon#about to read 3, iclass 19, count 0 2006.257.18:23:26.50#ibcon#read 3, iclass 19, count 0 2006.257.18:23:26.50#ibcon#about to read 4, iclass 19, count 0 2006.257.18:23:26.50#ibcon#read 4, iclass 19, count 0 2006.257.18:23:26.50#ibcon#about to read 5, iclass 19, count 0 2006.257.18:23:26.50#ibcon#read 5, iclass 19, count 0 2006.257.18:23:26.50#ibcon#about to read 6, iclass 19, count 0 2006.257.18:23:26.50#ibcon#read 6, iclass 19, count 0 2006.257.18:23:26.50#ibcon#end of sib2, iclass 19, count 0 2006.257.18:23:26.50#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:23:26.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:23:26.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:23:26.50#ibcon#*before write, iclass 19, count 0 2006.257.18:23:26.50#ibcon#enter sib2, iclass 19, count 0 2006.257.18:23:26.50#ibcon#flushed, iclass 19, count 0 2006.257.18:23:26.50#ibcon#about to write, iclass 19, count 0 2006.257.18:23:26.50#ibcon#wrote, iclass 19, count 0 2006.257.18:23:26.50#ibcon#about to read 3, iclass 19, count 0 2006.257.18:23:26.55#ibcon#read 3, iclass 19, count 0 2006.257.18:23:26.55#ibcon#about to read 4, iclass 19, count 0 2006.257.18:23:26.55#ibcon#read 4, iclass 19, count 0 2006.257.18:23:26.55#ibcon#about to read 5, iclass 19, count 0 2006.257.18:23:26.55#ibcon#read 5, iclass 19, count 0 2006.257.18:23:26.55#ibcon#about to read 6, iclass 19, count 0 2006.257.18:23:26.55#ibcon#read 6, iclass 19, count 0 2006.257.18:23:26.55#ibcon#end of sib2, iclass 19, count 0 2006.257.18:23:26.55#ibcon#*after write, iclass 19, count 0 2006.257.18:23:26.55#ibcon#*before return 0, iclass 19, count 0 2006.257.18:23:26.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:26.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:26.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:23:26.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:23:26.55$vck44/va=1,8 2006.257.18:23:26.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.18:23:26.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.18:23:26.55#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:26.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:26.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:26.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:26.55#ibcon#enter wrdev, iclass 21, count 2 2006.257.18:23:26.55#ibcon#first serial, iclass 21, count 2 2006.257.18:23:26.55#ibcon#enter sib2, iclass 21, count 2 2006.257.18:23:26.55#ibcon#flushed, iclass 21, count 2 2006.257.18:23:26.55#ibcon#about to write, iclass 21, count 2 2006.257.18:23:26.55#ibcon#wrote, iclass 21, count 2 2006.257.18:23:26.55#ibcon#about to read 3, iclass 21, count 2 2006.257.18:23:26.57#ibcon#read 3, iclass 21, count 2 2006.257.18:23:26.57#ibcon#about to read 4, iclass 21, count 2 2006.257.18:23:26.57#ibcon#read 4, iclass 21, count 2 2006.257.18:23:26.57#ibcon#about to read 5, iclass 21, count 2 2006.257.18:23:26.57#ibcon#read 5, iclass 21, count 2 2006.257.18:23:26.57#ibcon#about to read 6, iclass 21, count 2 2006.257.18:23:26.57#ibcon#read 6, iclass 21, count 2 2006.257.18:23:26.57#ibcon#end of sib2, iclass 21, count 2 2006.257.18:23:26.57#ibcon#*mode == 0, iclass 21, count 2 2006.257.18:23:26.57#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.18:23:26.57#ibcon#[25=AT01-08\r\n] 2006.257.18:23:26.57#ibcon#*before write, iclass 21, count 2 2006.257.18:23:26.57#ibcon#enter sib2, iclass 21, count 2 2006.257.18:23:26.57#ibcon#flushed, iclass 21, count 2 2006.257.18:23:26.57#ibcon#about to write, iclass 21, count 2 2006.257.18:23:26.57#ibcon#wrote, iclass 21, count 2 2006.257.18:23:26.57#ibcon#about to read 3, iclass 21, count 2 2006.257.18:23:26.60#ibcon#read 3, iclass 21, count 2 2006.257.18:23:26.60#ibcon#about to read 4, iclass 21, count 2 2006.257.18:23:26.60#ibcon#read 4, iclass 21, count 2 2006.257.18:23:26.60#ibcon#about to read 5, iclass 21, count 2 2006.257.18:23:26.60#ibcon#read 5, iclass 21, count 2 2006.257.18:23:26.60#ibcon#about to read 6, iclass 21, count 2 2006.257.18:23:26.60#ibcon#read 6, iclass 21, count 2 2006.257.18:23:26.60#ibcon#end of sib2, iclass 21, count 2 2006.257.18:23:26.60#ibcon#*after write, iclass 21, count 2 2006.257.18:23:26.60#ibcon#*before return 0, iclass 21, count 2 2006.257.18:23:26.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:26.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:26.60#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.18:23:26.60#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:26.60#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:26.72#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:26.72#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:26.72#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:23:26.72#ibcon#first serial, iclass 21, count 0 2006.257.18:23:26.72#ibcon#enter sib2, iclass 21, count 0 2006.257.18:23:26.72#ibcon#flushed, iclass 21, count 0 2006.257.18:23:26.72#ibcon#about to write, iclass 21, count 0 2006.257.18:23:26.72#ibcon#wrote, iclass 21, count 0 2006.257.18:23:26.72#ibcon#about to read 3, iclass 21, count 0 2006.257.18:23:26.74#ibcon#read 3, iclass 21, count 0 2006.257.18:23:26.74#ibcon#about to read 4, iclass 21, count 0 2006.257.18:23:26.74#ibcon#read 4, iclass 21, count 0 2006.257.18:23:26.74#ibcon#about to read 5, iclass 21, count 0 2006.257.18:23:26.74#ibcon#read 5, iclass 21, count 0 2006.257.18:23:26.74#ibcon#about to read 6, iclass 21, count 0 2006.257.18:23:26.74#ibcon#read 6, iclass 21, count 0 2006.257.18:23:26.74#ibcon#end of sib2, iclass 21, count 0 2006.257.18:23:26.74#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:23:26.74#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:23:26.74#ibcon#[25=USB\r\n] 2006.257.18:23:26.74#ibcon#*before write, iclass 21, count 0 2006.257.18:23:26.74#ibcon#enter sib2, iclass 21, count 0 2006.257.18:23:26.74#ibcon#flushed, iclass 21, count 0 2006.257.18:23:26.74#ibcon#about to write, iclass 21, count 0 2006.257.18:23:26.74#ibcon#wrote, iclass 21, count 0 2006.257.18:23:26.74#ibcon#about to read 3, iclass 21, count 0 2006.257.18:23:26.77#ibcon#read 3, iclass 21, count 0 2006.257.18:23:26.77#ibcon#about to read 4, iclass 21, count 0 2006.257.18:23:26.77#ibcon#read 4, iclass 21, count 0 2006.257.18:23:26.77#ibcon#about to read 5, iclass 21, count 0 2006.257.18:23:26.77#ibcon#read 5, iclass 21, count 0 2006.257.18:23:26.77#ibcon#about to read 6, iclass 21, count 0 2006.257.18:23:26.77#ibcon#read 6, iclass 21, count 0 2006.257.18:23:26.77#ibcon#end of sib2, iclass 21, count 0 2006.257.18:23:26.77#ibcon#*after write, iclass 21, count 0 2006.257.18:23:26.77#ibcon#*before return 0, iclass 21, count 0 2006.257.18:23:26.77#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:26.77#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:26.77#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:23:26.77#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:23:26.77$vck44/valo=2,534.99 2006.257.18:23:26.77#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.18:23:26.77#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.18:23:26.77#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:26.77#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:26.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:26.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:26.77#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:23:26.77#ibcon#first serial, iclass 23, count 0 2006.257.18:23:26.77#ibcon#enter sib2, iclass 23, count 0 2006.257.18:23:26.77#ibcon#flushed, iclass 23, count 0 2006.257.18:23:26.77#ibcon#about to write, iclass 23, count 0 2006.257.18:23:26.77#ibcon#wrote, iclass 23, count 0 2006.257.18:23:26.77#ibcon#about to read 3, iclass 23, count 0 2006.257.18:23:26.79#ibcon#read 3, iclass 23, count 0 2006.257.18:23:26.79#ibcon#about to read 4, iclass 23, count 0 2006.257.18:23:26.79#ibcon#read 4, iclass 23, count 0 2006.257.18:23:26.79#ibcon#about to read 5, iclass 23, count 0 2006.257.18:23:26.79#ibcon#read 5, iclass 23, count 0 2006.257.18:23:26.79#ibcon#about to read 6, iclass 23, count 0 2006.257.18:23:26.79#ibcon#read 6, iclass 23, count 0 2006.257.18:23:26.79#ibcon#end of sib2, iclass 23, count 0 2006.257.18:23:26.79#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:23:26.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:23:26.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:23:26.79#ibcon#*before write, iclass 23, count 0 2006.257.18:23:26.79#ibcon#enter sib2, iclass 23, count 0 2006.257.18:23:26.79#ibcon#flushed, iclass 23, count 0 2006.257.18:23:26.79#ibcon#about to write, iclass 23, count 0 2006.257.18:23:26.79#ibcon#wrote, iclass 23, count 0 2006.257.18:23:26.79#ibcon#about to read 3, iclass 23, count 0 2006.257.18:23:26.83#ibcon#read 3, iclass 23, count 0 2006.257.18:23:26.83#ibcon#about to read 4, iclass 23, count 0 2006.257.18:23:26.83#ibcon#read 4, iclass 23, count 0 2006.257.18:23:26.83#ibcon#about to read 5, iclass 23, count 0 2006.257.18:23:26.83#ibcon#read 5, iclass 23, count 0 2006.257.18:23:26.83#ibcon#about to read 6, iclass 23, count 0 2006.257.18:23:26.83#ibcon#read 6, iclass 23, count 0 2006.257.18:23:26.83#ibcon#end of sib2, iclass 23, count 0 2006.257.18:23:26.83#ibcon#*after write, iclass 23, count 0 2006.257.18:23:26.83#ibcon#*before return 0, iclass 23, count 0 2006.257.18:23:26.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:26.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:26.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:23:26.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:23:26.83$vck44/va=2,7 2006.257.18:23:26.83#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.18:23:26.83#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.18:23:26.83#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:26.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:26.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:26.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:26.89#ibcon#enter wrdev, iclass 25, count 2 2006.257.18:23:26.89#ibcon#first serial, iclass 25, count 2 2006.257.18:23:26.89#ibcon#enter sib2, iclass 25, count 2 2006.257.18:23:26.89#ibcon#flushed, iclass 25, count 2 2006.257.18:23:26.89#ibcon#about to write, iclass 25, count 2 2006.257.18:23:26.89#ibcon#wrote, iclass 25, count 2 2006.257.18:23:26.89#ibcon#about to read 3, iclass 25, count 2 2006.257.18:23:26.91#ibcon#read 3, iclass 25, count 2 2006.257.18:23:26.91#ibcon#about to read 4, iclass 25, count 2 2006.257.18:23:26.91#ibcon#read 4, iclass 25, count 2 2006.257.18:23:26.91#ibcon#about to read 5, iclass 25, count 2 2006.257.18:23:26.91#ibcon#read 5, iclass 25, count 2 2006.257.18:23:26.91#ibcon#about to read 6, iclass 25, count 2 2006.257.18:23:26.91#ibcon#read 6, iclass 25, count 2 2006.257.18:23:26.91#ibcon#end of sib2, iclass 25, count 2 2006.257.18:23:26.91#ibcon#*mode == 0, iclass 25, count 2 2006.257.18:23:26.91#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.18:23:26.91#ibcon#[25=AT02-07\r\n] 2006.257.18:23:26.91#ibcon#*before write, iclass 25, count 2 2006.257.18:23:26.91#ibcon#enter sib2, iclass 25, count 2 2006.257.18:23:26.91#ibcon#flushed, iclass 25, count 2 2006.257.18:23:26.91#ibcon#about to write, iclass 25, count 2 2006.257.18:23:26.91#ibcon#wrote, iclass 25, count 2 2006.257.18:23:26.91#ibcon#about to read 3, iclass 25, count 2 2006.257.18:23:26.94#ibcon#read 3, iclass 25, count 2 2006.257.18:23:26.94#ibcon#about to read 4, iclass 25, count 2 2006.257.18:23:26.94#ibcon#read 4, iclass 25, count 2 2006.257.18:23:26.94#ibcon#about to read 5, iclass 25, count 2 2006.257.18:23:26.94#ibcon#read 5, iclass 25, count 2 2006.257.18:23:26.94#ibcon#about to read 6, iclass 25, count 2 2006.257.18:23:26.94#ibcon#read 6, iclass 25, count 2 2006.257.18:23:26.94#ibcon#end of sib2, iclass 25, count 2 2006.257.18:23:26.94#ibcon#*after write, iclass 25, count 2 2006.257.18:23:26.94#ibcon#*before return 0, iclass 25, count 2 2006.257.18:23:26.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:26.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:26.94#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.18:23:26.94#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:26.94#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:27.06#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:27.06#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:27.06#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:23:27.06#ibcon#first serial, iclass 25, count 0 2006.257.18:23:27.06#ibcon#enter sib2, iclass 25, count 0 2006.257.18:23:27.06#ibcon#flushed, iclass 25, count 0 2006.257.18:23:27.06#ibcon#about to write, iclass 25, count 0 2006.257.18:23:27.06#ibcon#wrote, iclass 25, count 0 2006.257.18:23:27.06#ibcon#about to read 3, iclass 25, count 0 2006.257.18:23:27.08#ibcon#read 3, iclass 25, count 0 2006.257.18:23:27.08#ibcon#about to read 4, iclass 25, count 0 2006.257.18:23:27.08#ibcon#read 4, iclass 25, count 0 2006.257.18:23:27.08#ibcon#about to read 5, iclass 25, count 0 2006.257.18:23:27.08#ibcon#read 5, iclass 25, count 0 2006.257.18:23:27.08#ibcon#about to read 6, iclass 25, count 0 2006.257.18:23:27.08#ibcon#read 6, iclass 25, count 0 2006.257.18:23:27.08#ibcon#end of sib2, iclass 25, count 0 2006.257.18:23:27.08#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:23:27.08#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:23:27.08#ibcon#[25=USB\r\n] 2006.257.18:23:27.08#ibcon#*before write, iclass 25, count 0 2006.257.18:23:27.08#ibcon#enter sib2, iclass 25, count 0 2006.257.18:23:27.08#ibcon#flushed, iclass 25, count 0 2006.257.18:23:27.08#ibcon#about to write, iclass 25, count 0 2006.257.18:23:27.08#ibcon#wrote, iclass 25, count 0 2006.257.18:23:27.08#ibcon#about to read 3, iclass 25, count 0 2006.257.18:23:27.11#ibcon#read 3, iclass 25, count 0 2006.257.18:23:27.11#ibcon#about to read 4, iclass 25, count 0 2006.257.18:23:27.11#ibcon#read 4, iclass 25, count 0 2006.257.18:23:27.11#ibcon#about to read 5, iclass 25, count 0 2006.257.18:23:27.11#ibcon#read 5, iclass 25, count 0 2006.257.18:23:27.11#ibcon#about to read 6, iclass 25, count 0 2006.257.18:23:27.11#ibcon#read 6, iclass 25, count 0 2006.257.18:23:27.11#ibcon#end of sib2, iclass 25, count 0 2006.257.18:23:27.11#ibcon#*after write, iclass 25, count 0 2006.257.18:23:27.11#ibcon#*before return 0, iclass 25, count 0 2006.257.18:23:27.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:27.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:27.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:23:27.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:23:27.11$vck44/valo=3,564.99 2006.257.18:23:27.11#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.18:23:27.11#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.18:23:27.11#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:27.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:27.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:27.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:27.11#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:23:27.11#ibcon#first serial, iclass 27, count 0 2006.257.18:23:27.11#ibcon#enter sib2, iclass 27, count 0 2006.257.18:23:27.11#ibcon#flushed, iclass 27, count 0 2006.257.18:23:27.11#ibcon#about to write, iclass 27, count 0 2006.257.18:23:27.11#ibcon#wrote, iclass 27, count 0 2006.257.18:23:27.11#ibcon#about to read 3, iclass 27, count 0 2006.257.18:23:27.13#ibcon#read 3, iclass 27, count 0 2006.257.18:23:27.13#ibcon#about to read 4, iclass 27, count 0 2006.257.18:23:27.13#ibcon#read 4, iclass 27, count 0 2006.257.18:23:27.13#ibcon#about to read 5, iclass 27, count 0 2006.257.18:23:27.13#ibcon#read 5, iclass 27, count 0 2006.257.18:23:27.13#ibcon#about to read 6, iclass 27, count 0 2006.257.18:23:27.13#ibcon#read 6, iclass 27, count 0 2006.257.18:23:27.13#ibcon#end of sib2, iclass 27, count 0 2006.257.18:23:27.13#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:23:27.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:23:27.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:23:27.13#ibcon#*before write, iclass 27, count 0 2006.257.18:23:27.13#ibcon#enter sib2, iclass 27, count 0 2006.257.18:23:27.13#ibcon#flushed, iclass 27, count 0 2006.257.18:23:27.13#ibcon#about to write, iclass 27, count 0 2006.257.18:23:27.13#ibcon#wrote, iclass 27, count 0 2006.257.18:23:27.13#ibcon#about to read 3, iclass 27, count 0 2006.257.18:23:27.17#ibcon#read 3, iclass 27, count 0 2006.257.18:23:27.17#ibcon#about to read 4, iclass 27, count 0 2006.257.18:23:27.17#ibcon#read 4, iclass 27, count 0 2006.257.18:23:27.17#ibcon#about to read 5, iclass 27, count 0 2006.257.18:23:27.17#ibcon#read 5, iclass 27, count 0 2006.257.18:23:27.17#ibcon#about to read 6, iclass 27, count 0 2006.257.18:23:27.17#ibcon#read 6, iclass 27, count 0 2006.257.18:23:27.17#ibcon#end of sib2, iclass 27, count 0 2006.257.18:23:27.17#ibcon#*after write, iclass 27, count 0 2006.257.18:23:27.17#ibcon#*before return 0, iclass 27, count 0 2006.257.18:23:27.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:27.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:27.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:23:27.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:23:27.17$vck44/va=3,8 2006.257.18:23:27.17#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.18:23:27.17#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.18:23:27.17#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:27.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:27.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:27.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:27.23#ibcon#enter wrdev, iclass 29, count 2 2006.257.18:23:27.23#ibcon#first serial, iclass 29, count 2 2006.257.18:23:27.23#ibcon#enter sib2, iclass 29, count 2 2006.257.18:23:27.23#ibcon#flushed, iclass 29, count 2 2006.257.18:23:27.23#ibcon#about to write, iclass 29, count 2 2006.257.18:23:27.23#ibcon#wrote, iclass 29, count 2 2006.257.18:23:27.23#ibcon#about to read 3, iclass 29, count 2 2006.257.18:23:27.25#ibcon#read 3, iclass 29, count 2 2006.257.18:23:27.25#ibcon#about to read 4, iclass 29, count 2 2006.257.18:23:27.25#ibcon#read 4, iclass 29, count 2 2006.257.18:23:27.25#ibcon#about to read 5, iclass 29, count 2 2006.257.18:23:27.25#ibcon#read 5, iclass 29, count 2 2006.257.18:23:27.25#ibcon#about to read 6, iclass 29, count 2 2006.257.18:23:27.25#ibcon#read 6, iclass 29, count 2 2006.257.18:23:27.25#ibcon#end of sib2, iclass 29, count 2 2006.257.18:23:27.25#ibcon#*mode == 0, iclass 29, count 2 2006.257.18:23:27.25#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.18:23:27.25#ibcon#[25=AT03-08\r\n] 2006.257.18:23:27.25#ibcon#*before write, iclass 29, count 2 2006.257.18:23:27.25#ibcon#enter sib2, iclass 29, count 2 2006.257.18:23:27.25#ibcon#flushed, iclass 29, count 2 2006.257.18:23:27.25#ibcon#about to write, iclass 29, count 2 2006.257.18:23:27.25#ibcon#wrote, iclass 29, count 2 2006.257.18:23:27.25#ibcon#about to read 3, iclass 29, count 2 2006.257.18:23:27.28#ibcon#read 3, iclass 29, count 2 2006.257.18:23:27.28#ibcon#about to read 4, iclass 29, count 2 2006.257.18:23:27.28#ibcon#read 4, iclass 29, count 2 2006.257.18:23:27.28#ibcon#about to read 5, iclass 29, count 2 2006.257.18:23:27.28#ibcon#read 5, iclass 29, count 2 2006.257.18:23:27.28#ibcon#about to read 6, iclass 29, count 2 2006.257.18:23:27.28#ibcon#read 6, iclass 29, count 2 2006.257.18:23:27.28#ibcon#end of sib2, iclass 29, count 2 2006.257.18:23:27.28#ibcon#*after write, iclass 29, count 2 2006.257.18:23:27.28#ibcon#*before return 0, iclass 29, count 2 2006.257.18:23:27.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:27.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:27.28#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.18:23:27.28#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:27.28#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:27.40#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:27.40#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:27.40#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:23:27.40#ibcon#first serial, iclass 29, count 0 2006.257.18:23:27.40#ibcon#enter sib2, iclass 29, count 0 2006.257.18:23:27.40#ibcon#flushed, iclass 29, count 0 2006.257.18:23:27.40#ibcon#about to write, iclass 29, count 0 2006.257.18:23:27.40#ibcon#wrote, iclass 29, count 0 2006.257.18:23:27.40#ibcon#about to read 3, iclass 29, count 0 2006.257.18:23:27.42#ibcon#read 3, iclass 29, count 0 2006.257.18:23:27.42#ibcon#about to read 4, iclass 29, count 0 2006.257.18:23:27.42#ibcon#read 4, iclass 29, count 0 2006.257.18:23:27.42#ibcon#about to read 5, iclass 29, count 0 2006.257.18:23:27.42#ibcon#read 5, iclass 29, count 0 2006.257.18:23:27.42#ibcon#about to read 6, iclass 29, count 0 2006.257.18:23:27.42#ibcon#read 6, iclass 29, count 0 2006.257.18:23:27.42#ibcon#end of sib2, iclass 29, count 0 2006.257.18:23:27.42#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:23:27.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:23:27.42#ibcon#[25=USB\r\n] 2006.257.18:23:27.42#ibcon#*before write, iclass 29, count 0 2006.257.18:23:27.42#ibcon#enter sib2, iclass 29, count 0 2006.257.18:23:27.42#ibcon#flushed, iclass 29, count 0 2006.257.18:23:27.42#ibcon#about to write, iclass 29, count 0 2006.257.18:23:27.42#ibcon#wrote, iclass 29, count 0 2006.257.18:23:27.42#ibcon#about to read 3, iclass 29, count 0 2006.257.18:23:27.45#ibcon#read 3, iclass 29, count 0 2006.257.18:23:27.45#ibcon#about to read 4, iclass 29, count 0 2006.257.18:23:27.45#ibcon#read 4, iclass 29, count 0 2006.257.18:23:27.45#ibcon#about to read 5, iclass 29, count 0 2006.257.18:23:27.45#ibcon#read 5, iclass 29, count 0 2006.257.18:23:27.45#ibcon#about to read 6, iclass 29, count 0 2006.257.18:23:27.45#ibcon#read 6, iclass 29, count 0 2006.257.18:23:27.45#ibcon#end of sib2, iclass 29, count 0 2006.257.18:23:27.45#ibcon#*after write, iclass 29, count 0 2006.257.18:23:27.45#ibcon#*before return 0, iclass 29, count 0 2006.257.18:23:27.45#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:27.45#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:27.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:23:27.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:23:27.45$vck44/valo=4,624.99 2006.257.18:23:27.45#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.18:23:27.45#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.18:23:27.45#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:27.45#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:27.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:27.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:27.45#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:23:27.45#ibcon#first serial, iclass 31, count 0 2006.257.18:23:27.45#ibcon#enter sib2, iclass 31, count 0 2006.257.18:23:27.45#ibcon#flushed, iclass 31, count 0 2006.257.18:23:27.45#ibcon#about to write, iclass 31, count 0 2006.257.18:23:27.45#ibcon#wrote, iclass 31, count 0 2006.257.18:23:27.45#ibcon#about to read 3, iclass 31, count 0 2006.257.18:23:27.47#ibcon#read 3, iclass 31, count 0 2006.257.18:23:27.47#ibcon#about to read 4, iclass 31, count 0 2006.257.18:23:27.47#ibcon#read 4, iclass 31, count 0 2006.257.18:23:27.47#ibcon#about to read 5, iclass 31, count 0 2006.257.18:23:27.47#ibcon#read 5, iclass 31, count 0 2006.257.18:23:27.47#ibcon#about to read 6, iclass 31, count 0 2006.257.18:23:27.47#ibcon#read 6, iclass 31, count 0 2006.257.18:23:27.47#ibcon#end of sib2, iclass 31, count 0 2006.257.18:23:27.47#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:23:27.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:23:27.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:23:27.47#ibcon#*before write, iclass 31, count 0 2006.257.18:23:27.47#ibcon#enter sib2, iclass 31, count 0 2006.257.18:23:27.47#ibcon#flushed, iclass 31, count 0 2006.257.18:23:27.47#ibcon#about to write, iclass 31, count 0 2006.257.18:23:27.47#ibcon#wrote, iclass 31, count 0 2006.257.18:23:27.47#ibcon#about to read 3, iclass 31, count 0 2006.257.18:23:27.51#ibcon#read 3, iclass 31, count 0 2006.257.18:23:27.51#ibcon#about to read 4, iclass 31, count 0 2006.257.18:23:27.51#ibcon#read 4, iclass 31, count 0 2006.257.18:23:27.51#ibcon#about to read 5, iclass 31, count 0 2006.257.18:23:27.51#ibcon#read 5, iclass 31, count 0 2006.257.18:23:27.51#ibcon#about to read 6, iclass 31, count 0 2006.257.18:23:27.51#ibcon#read 6, iclass 31, count 0 2006.257.18:23:27.51#ibcon#end of sib2, iclass 31, count 0 2006.257.18:23:27.51#ibcon#*after write, iclass 31, count 0 2006.257.18:23:27.51#ibcon#*before return 0, iclass 31, count 0 2006.257.18:23:27.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:27.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:27.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:23:27.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:23:27.51$vck44/va=4,7 2006.257.18:23:27.51#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.18:23:27.51#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.18:23:27.51#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:27.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:27.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:27.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:27.57#ibcon#enter wrdev, iclass 33, count 2 2006.257.18:23:27.57#ibcon#first serial, iclass 33, count 2 2006.257.18:23:27.57#ibcon#enter sib2, iclass 33, count 2 2006.257.18:23:27.57#ibcon#flushed, iclass 33, count 2 2006.257.18:23:27.57#ibcon#about to write, iclass 33, count 2 2006.257.18:23:27.57#ibcon#wrote, iclass 33, count 2 2006.257.18:23:27.57#ibcon#about to read 3, iclass 33, count 2 2006.257.18:23:27.59#ibcon#read 3, iclass 33, count 2 2006.257.18:23:27.59#ibcon#about to read 4, iclass 33, count 2 2006.257.18:23:27.59#ibcon#read 4, iclass 33, count 2 2006.257.18:23:27.59#ibcon#about to read 5, iclass 33, count 2 2006.257.18:23:27.59#ibcon#read 5, iclass 33, count 2 2006.257.18:23:27.59#ibcon#about to read 6, iclass 33, count 2 2006.257.18:23:27.59#ibcon#read 6, iclass 33, count 2 2006.257.18:23:27.59#ibcon#end of sib2, iclass 33, count 2 2006.257.18:23:27.59#ibcon#*mode == 0, iclass 33, count 2 2006.257.18:23:27.59#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.18:23:27.59#ibcon#[25=AT04-07\r\n] 2006.257.18:23:27.59#ibcon#*before write, iclass 33, count 2 2006.257.18:23:27.59#ibcon#enter sib2, iclass 33, count 2 2006.257.18:23:27.59#ibcon#flushed, iclass 33, count 2 2006.257.18:23:27.59#ibcon#about to write, iclass 33, count 2 2006.257.18:23:27.59#ibcon#wrote, iclass 33, count 2 2006.257.18:23:27.59#ibcon#about to read 3, iclass 33, count 2 2006.257.18:23:27.62#ibcon#read 3, iclass 33, count 2 2006.257.18:23:27.62#ibcon#about to read 4, iclass 33, count 2 2006.257.18:23:27.62#ibcon#read 4, iclass 33, count 2 2006.257.18:23:27.62#ibcon#about to read 5, iclass 33, count 2 2006.257.18:23:27.62#ibcon#read 5, iclass 33, count 2 2006.257.18:23:27.62#ibcon#about to read 6, iclass 33, count 2 2006.257.18:23:27.62#ibcon#read 6, iclass 33, count 2 2006.257.18:23:27.62#ibcon#end of sib2, iclass 33, count 2 2006.257.18:23:27.62#ibcon#*after write, iclass 33, count 2 2006.257.18:23:27.62#ibcon#*before return 0, iclass 33, count 2 2006.257.18:23:27.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:27.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:27.62#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.18:23:27.62#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:27.62#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:27.74#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:27.74#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:27.74#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:23:27.74#ibcon#first serial, iclass 33, count 0 2006.257.18:23:27.74#ibcon#enter sib2, iclass 33, count 0 2006.257.18:23:27.74#ibcon#flushed, iclass 33, count 0 2006.257.18:23:27.74#ibcon#about to write, iclass 33, count 0 2006.257.18:23:27.74#ibcon#wrote, iclass 33, count 0 2006.257.18:23:27.74#ibcon#about to read 3, iclass 33, count 0 2006.257.18:23:27.76#ibcon#read 3, iclass 33, count 0 2006.257.18:23:27.76#ibcon#about to read 4, iclass 33, count 0 2006.257.18:23:27.76#ibcon#read 4, iclass 33, count 0 2006.257.18:23:27.76#ibcon#about to read 5, iclass 33, count 0 2006.257.18:23:27.76#ibcon#read 5, iclass 33, count 0 2006.257.18:23:27.76#ibcon#about to read 6, iclass 33, count 0 2006.257.18:23:27.76#ibcon#read 6, iclass 33, count 0 2006.257.18:23:27.76#ibcon#end of sib2, iclass 33, count 0 2006.257.18:23:27.76#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:23:27.76#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:23:27.76#ibcon#[25=USB\r\n] 2006.257.18:23:27.76#ibcon#*before write, iclass 33, count 0 2006.257.18:23:27.76#ibcon#enter sib2, iclass 33, count 0 2006.257.18:23:27.76#ibcon#flushed, iclass 33, count 0 2006.257.18:23:27.76#ibcon#about to write, iclass 33, count 0 2006.257.18:23:27.76#ibcon#wrote, iclass 33, count 0 2006.257.18:23:27.76#ibcon#about to read 3, iclass 33, count 0 2006.257.18:23:27.79#ibcon#read 3, iclass 33, count 0 2006.257.18:23:27.79#ibcon#about to read 4, iclass 33, count 0 2006.257.18:23:27.79#ibcon#read 4, iclass 33, count 0 2006.257.18:23:27.79#ibcon#about to read 5, iclass 33, count 0 2006.257.18:23:27.79#ibcon#read 5, iclass 33, count 0 2006.257.18:23:27.79#ibcon#about to read 6, iclass 33, count 0 2006.257.18:23:27.79#ibcon#read 6, iclass 33, count 0 2006.257.18:23:27.79#ibcon#end of sib2, iclass 33, count 0 2006.257.18:23:27.79#ibcon#*after write, iclass 33, count 0 2006.257.18:23:27.79#ibcon#*before return 0, iclass 33, count 0 2006.257.18:23:27.79#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:27.79#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:27.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:23:27.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:23:27.79$vck44/valo=5,734.99 2006.257.18:23:27.79#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.18:23:27.79#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.18:23:27.79#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:27.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:27.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:27.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:27.79#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:23:27.79#ibcon#first serial, iclass 35, count 0 2006.257.18:23:27.79#ibcon#enter sib2, iclass 35, count 0 2006.257.18:23:27.79#ibcon#flushed, iclass 35, count 0 2006.257.18:23:27.79#ibcon#about to write, iclass 35, count 0 2006.257.18:23:27.79#ibcon#wrote, iclass 35, count 0 2006.257.18:23:27.79#ibcon#about to read 3, iclass 35, count 0 2006.257.18:23:27.81#ibcon#read 3, iclass 35, count 0 2006.257.18:23:27.81#ibcon#about to read 4, iclass 35, count 0 2006.257.18:23:27.81#ibcon#read 4, iclass 35, count 0 2006.257.18:23:27.81#ibcon#about to read 5, iclass 35, count 0 2006.257.18:23:27.81#ibcon#read 5, iclass 35, count 0 2006.257.18:23:27.81#ibcon#about to read 6, iclass 35, count 0 2006.257.18:23:27.81#ibcon#read 6, iclass 35, count 0 2006.257.18:23:27.81#ibcon#end of sib2, iclass 35, count 0 2006.257.18:23:27.81#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:23:27.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:23:27.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:23:27.81#ibcon#*before write, iclass 35, count 0 2006.257.18:23:27.81#ibcon#enter sib2, iclass 35, count 0 2006.257.18:23:27.81#ibcon#flushed, iclass 35, count 0 2006.257.18:23:27.81#ibcon#about to write, iclass 35, count 0 2006.257.18:23:27.81#ibcon#wrote, iclass 35, count 0 2006.257.18:23:27.81#ibcon#about to read 3, iclass 35, count 0 2006.257.18:23:27.85#ibcon#read 3, iclass 35, count 0 2006.257.18:23:27.85#ibcon#about to read 4, iclass 35, count 0 2006.257.18:23:27.85#ibcon#read 4, iclass 35, count 0 2006.257.18:23:27.85#ibcon#about to read 5, iclass 35, count 0 2006.257.18:23:27.85#ibcon#read 5, iclass 35, count 0 2006.257.18:23:27.85#ibcon#about to read 6, iclass 35, count 0 2006.257.18:23:27.85#ibcon#read 6, iclass 35, count 0 2006.257.18:23:27.85#ibcon#end of sib2, iclass 35, count 0 2006.257.18:23:27.85#ibcon#*after write, iclass 35, count 0 2006.257.18:23:27.85#ibcon#*before return 0, iclass 35, count 0 2006.257.18:23:27.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:27.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:27.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:23:27.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:23:27.85$vck44/va=5,4 2006.257.18:23:27.85#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.18:23:27.85#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.18:23:27.85#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:27.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:27.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:27.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:27.91#ibcon#enter wrdev, iclass 37, count 2 2006.257.18:23:27.91#ibcon#first serial, iclass 37, count 2 2006.257.18:23:27.91#ibcon#enter sib2, iclass 37, count 2 2006.257.18:23:27.91#ibcon#flushed, iclass 37, count 2 2006.257.18:23:27.91#ibcon#about to write, iclass 37, count 2 2006.257.18:23:27.91#ibcon#wrote, iclass 37, count 2 2006.257.18:23:27.91#ibcon#about to read 3, iclass 37, count 2 2006.257.18:23:27.93#ibcon#read 3, iclass 37, count 2 2006.257.18:23:27.93#ibcon#about to read 4, iclass 37, count 2 2006.257.18:23:27.93#ibcon#read 4, iclass 37, count 2 2006.257.18:23:27.93#ibcon#about to read 5, iclass 37, count 2 2006.257.18:23:27.93#ibcon#read 5, iclass 37, count 2 2006.257.18:23:27.93#ibcon#about to read 6, iclass 37, count 2 2006.257.18:23:27.93#ibcon#read 6, iclass 37, count 2 2006.257.18:23:27.93#ibcon#end of sib2, iclass 37, count 2 2006.257.18:23:27.93#ibcon#*mode == 0, iclass 37, count 2 2006.257.18:23:27.93#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.18:23:27.93#ibcon#[25=AT05-04\r\n] 2006.257.18:23:27.93#ibcon#*before write, iclass 37, count 2 2006.257.18:23:27.93#ibcon#enter sib2, iclass 37, count 2 2006.257.18:23:27.93#ibcon#flushed, iclass 37, count 2 2006.257.18:23:27.93#ibcon#about to write, iclass 37, count 2 2006.257.18:23:27.93#ibcon#wrote, iclass 37, count 2 2006.257.18:23:27.93#ibcon#about to read 3, iclass 37, count 2 2006.257.18:23:27.96#ibcon#read 3, iclass 37, count 2 2006.257.18:23:27.96#ibcon#about to read 4, iclass 37, count 2 2006.257.18:23:27.96#ibcon#read 4, iclass 37, count 2 2006.257.18:23:27.96#ibcon#about to read 5, iclass 37, count 2 2006.257.18:23:27.96#ibcon#read 5, iclass 37, count 2 2006.257.18:23:27.96#ibcon#about to read 6, iclass 37, count 2 2006.257.18:23:27.96#ibcon#read 6, iclass 37, count 2 2006.257.18:23:27.96#ibcon#end of sib2, iclass 37, count 2 2006.257.18:23:27.96#ibcon#*after write, iclass 37, count 2 2006.257.18:23:27.96#ibcon#*before return 0, iclass 37, count 2 2006.257.18:23:27.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:27.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:27.96#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.18:23:27.96#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:27.96#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:28.08#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:28.08#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:28.08#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:23:28.08#ibcon#first serial, iclass 37, count 0 2006.257.18:23:28.08#ibcon#enter sib2, iclass 37, count 0 2006.257.18:23:28.08#ibcon#flushed, iclass 37, count 0 2006.257.18:23:28.08#ibcon#about to write, iclass 37, count 0 2006.257.18:23:28.08#ibcon#wrote, iclass 37, count 0 2006.257.18:23:28.08#ibcon#about to read 3, iclass 37, count 0 2006.257.18:23:28.10#ibcon#read 3, iclass 37, count 0 2006.257.18:23:28.10#ibcon#about to read 4, iclass 37, count 0 2006.257.18:23:28.10#ibcon#read 4, iclass 37, count 0 2006.257.18:23:28.10#ibcon#about to read 5, iclass 37, count 0 2006.257.18:23:28.10#ibcon#read 5, iclass 37, count 0 2006.257.18:23:28.10#ibcon#about to read 6, iclass 37, count 0 2006.257.18:23:28.10#ibcon#read 6, iclass 37, count 0 2006.257.18:23:28.10#ibcon#end of sib2, iclass 37, count 0 2006.257.18:23:28.10#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:23:28.10#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:23:28.10#ibcon#[25=USB\r\n] 2006.257.18:23:28.10#ibcon#*before write, iclass 37, count 0 2006.257.18:23:28.10#ibcon#enter sib2, iclass 37, count 0 2006.257.18:23:28.10#ibcon#flushed, iclass 37, count 0 2006.257.18:23:28.10#ibcon#about to write, iclass 37, count 0 2006.257.18:23:28.10#ibcon#wrote, iclass 37, count 0 2006.257.18:23:28.10#ibcon#about to read 3, iclass 37, count 0 2006.257.18:23:28.13#ibcon#read 3, iclass 37, count 0 2006.257.18:23:28.13#ibcon#about to read 4, iclass 37, count 0 2006.257.18:23:28.13#ibcon#read 4, iclass 37, count 0 2006.257.18:23:28.13#ibcon#about to read 5, iclass 37, count 0 2006.257.18:23:28.13#ibcon#read 5, iclass 37, count 0 2006.257.18:23:28.13#ibcon#about to read 6, iclass 37, count 0 2006.257.18:23:28.13#ibcon#read 6, iclass 37, count 0 2006.257.18:23:28.13#ibcon#end of sib2, iclass 37, count 0 2006.257.18:23:28.13#ibcon#*after write, iclass 37, count 0 2006.257.18:23:28.13#ibcon#*before return 0, iclass 37, count 0 2006.257.18:23:28.13#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:28.13#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:28.13#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:23:28.13#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:23:28.13$vck44/valo=6,814.99 2006.257.18:23:28.13#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.18:23:28.13#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.18:23:28.13#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:28.13#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:28.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:28.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:28.13#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:23:28.13#ibcon#first serial, iclass 39, count 0 2006.257.18:23:28.13#ibcon#enter sib2, iclass 39, count 0 2006.257.18:23:28.13#ibcon#flushed, iclass 39, count 0 2006.257.18:23:28.13#ibcon#about to write, iclass 39, count 0 2006.257.18:23:28.13#ibcon#wrote, iclass 39, count 0 2006.257.18:23:28.13#ibcon#about to read 3, iclass 39, count 0 2006.257.18:23:28.15#ibcon#read 3, iclass 39, count 0 2006.257.18:23:28.15#ibcon#about to read 4, iclass 39, count 0 2006.257.18:23:28.15#ibcon#read 4, iclass 39, count 0 2006.257.18:23:28.15#ibcon#about to read 5, iclass 39, count 0 2006.257.18:23:28.15#ibcon#read 5, iclass 39, count 0 2006.257.18:23:28.15#ibcon#about to read 6, iclass 39, count 0 2006.257.18:23:28.15#ibcon#read 6, iclass 39, count 0 2006.257.18:23:28.15#ibcon#end of sib2, iclass 39, count 0 2006.257.18:23:28.15#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:23:28.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:23:28.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:23:28.15#ibcon#*before write, iclass 39, count 0 2006.257.18:23:28.15#ibcon#enter sib2, iclass 39, count 0 2006.257.18:23:28.15#ibcon#flushed, iclass 39, count 0 2006.257.18:23:28.15#ibcon#about to write, iclass 39, count 0 2006.257.18:23:28.15#ibcon#wrote, iclass 39, count 0 2006.257.18:23:28.15#ibcon#about to read 3, iclass 39, count 0 2006.257.18:23:28.19#ibcon#read 3, iclass 39, count 0 2006.257.18:23:28.19#ibcon#about to read 4, iclass 39, count 0 2006.257.18:23:28.19#ibcon#read 4, iclass 39, count 0 2006.257.18:23:28.19#ibcon#about to read 5, iclass 39, count 0 2006.257.18:23:28.19#ibcon#read 5, iclass 39, count 0 2006.257.18:23:28.19#ibcon#about to read 6, iclass 39, count 0 2006.257.18:23:28.19#ibcon#read 6, iclass 39, count 0 2006.257.18:23:28.19#ibcon#end of sib2, iclass 39, count 0 2006.257.18:23:28.19#ibcon#*after write, iclass 39, count 0 2006.257.18:23:28.19#ibcon#*before return 0, iclass 39, count 0 2006.257.18:23:28.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:28.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:28.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:23:28.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:23:28.19$vck44/va=6,4 2006.257.18:23:28.19#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.18:23:28.19#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.18:23:28.19#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:28.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:28.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:28.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:28.25#ibcon#enter wrdev, iclass 3, count 2 2006.257.18:23:28.25#ibcon#first serial, iclass 3, count 2 2006.257.18:23:28.25#ibcon#enter sib2, iclass 3, count 2 2006.257.18:23:28.25#ibcon#flushed, iclass 3, count 2 2006.257.18:23:28.25#ibcon#about to write, iclass 3, count 2 2006.257.18:23:28.25#ibcon#wrote, iclass 3, count 2 2006.257.18:23:28.25#ibcon#about to read 3, iclass 3, count 2 2006.257.18:23:28.27#ibcon#read 3, iclass 3, count 2 2006.257.18:23:28.27#ibcon#about to read 4, iclass 3, count 2 2006.257.18:23:28.27#ibcon#read 4, iclass 3, count 2 2006.257.18:23:28.27#ibcon#about to read 5, iclass 3, count 2 2006.257.18:23:28.27#ibcon#read 5, iclass 3, count 2 2006.257.18:23:28.27#ibcon#about to read 6, iclass 3, count 2 2006.257.18:23:28.27#ibcon#read 6, iclass 3, count 2 2006.257.18:23:28.27#ibcon#end of sib2, iclass 3, count 2 2006.257.18:23:28.27#ibcon#*mode == 0, iclass 3, count 2 2006.257.18:23:28.27#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.18:23:28.27#ibcon#[25=AT06-04\r\n] 2006.257.18:23:28.27#ibcon#*before write, iclass 3, count 2 2006.257.18:23:28.27#ibcon#enter sib2, iclass 3, count 2 2006.257.18:23:28.27#ibcon#flushed, iclass 3, count 2 2006.257.18:23:28.27#ibcon#about to write, iclass 3, count 2 2006.257.18:23:28.27#ibcon#wrote, iclass 3, count 2 2006.257.18:23:28.27#ibcon#about to read 3, iclass 3, count 2 2006.257.18:23:28.30#ibcon#read 3, iclass 3, count 2 2006.257.18:23:28.30#ibcon#about to read 4, iclass 3, count 2 2006.257.18:23:28.30#ibcon#read 4, iclass 3, count 2 2006.257.18:23:28.30#ibcon#about to read 5, iclass 3, count 2 2006.257.18:23:28.30#ibcon#read 5, iclass 3, count 2 2006.257.18:23:28.30#ibcon#about to read 6, iclass 3, count 2 2006.257.18:23:28.30#ibcon#read 6, iclass 3, count 2 2006.257.18:23:28.30#ibcon#end of sib2, iclass 3, count 2 2006.257.18:23:28.30#ibcon#*after write, iclass 3, count 2 2006.257.18:23:28.30#ibcon#*before return 0, iclass 3, count 2 2006.257.18:23:28.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:28.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:28.30#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.18:23:28.30#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:28.30#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:28.42#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:28.42#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:28.42#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:23:28.42#ibcon#first serial, iclass 3, count 0 2006.257.18:23:28.42#ibcon#enter sib2, iclass 3, count 0 2006.257.18:23:28.42#ibcon#flushed, iclass 3, count 0 2006.257.18:23:28.42#ibcon#about to write, iclass 3, count 0 2006.257.18:23:28.42#ibcon#wrote, iclass 3, count 0 2006.257.18:23:28.42#ibcon#about to read 3, iclass 3, count 0 2006.257.18:23:28.44#ibcon#read 3, iclass 3, count 0 2006.257.18:23:28.44#ibcon#about to read 4, iclass 3, count 0 2006.257.18:23:28.44#ibcon#read 4, iclass 3, count 0 2006.257.18:23:28.44#ibcon#about to read 5, iclass 3, count 0 2006.257.18:23:28.44#ibcon#read 5, iclass 3, count 0 2006.257.18:23:28.44#ibcon#about to read 6, iclass 3, count 0 2006.257.18:23:28.44#ibcon#read 6, iclass 3, count 0 2006.257.18:23:28.44#ibcon#end of sib2, iclass 3, count 0 2006.257.18:23:28.44#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:23:28.44#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:23:28.44#ibcon#[25=USB\r\n] 2006.257.18:23:28.44#ibcon#*before write, iclass 3, count 0 2006.257.18:23:28.44#ibcon#enter sib2, iclass 3, count 0 2006.257.18:23:28.44#ibcon#flushed, iclass 3, count 0 2006.257.18:23:28.44#ibcon#about to write, iclass 3, count 0 2006.257.18:23:28.44#ibcon#wrote, iclass 3, count 0 2006.257.18:23:28.44#ibcon#about to read 3, iclass 3, count 0 2006.257.18:23:28.47#ibcon#read 3, iclass 3, count 0 2006.257.18:23:28.47#ibcon#about to read 4, iclass 3, count 0 2006.257.18:23:28.47#ibcon#read 4, iclass 3, count 0 2006.257.18:23:28.47#ibcon#about to read 5, iclass 3, count 0 2006.257.18:23:28.47#ibcon#read 5, iclass 3, count 0 2006.257.18:23:28.47#ibcon#about to read 6, iclass 3, count 0 2006.257.18:23:28.47#ibcon#read 6, iclass 3, count 0 2006.257.18:23:28.47#ibcon#end of sib2, iclass 3, count 0 2006.257.18:23:28.47#ibcon#*after write, iclass 3, count 0 2006.257.18:23:28.47#ibcon#*before return 0, iclass 3, count 0 2006.257.18:23:28.47#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:28.47#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:28.47#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:23:28.47#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:23:28.47$vck44/valo=7,864.99 2006.257.18:23:28.47#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.18:23:28.47#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.18:23:28.47#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:28.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:23:28.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:23:28.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:23:28.47#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:23:28.47#ibcon#first serial, iclass 5, count 0 2006.257.18:23:28.47#ibcon#enter sib2, iclass 5, count 0 2006.257.18:23:28.47#ibcon#flushed, iclass 5, count 0 2006.257.18:23:28.47#ibcon#about to write, iclass 5, count 0 2006.257.18:23:28.47#ibcon#wrote, iclass 5, count 0 2006.257.18:23:28.47#ibcon#about to read 3, iclass 5, count 0 2006.257.18:23:28.49#ibcon#read 3, iclass 5, count 0 2006.257.18:23:28.49#ibcon#about to read 4, iclass 5, count 0 2006.257.18:23:28.49#ibcon#read 4, iclass 5, count 0 2006.257.18:23:28.49#ibcon#about to read 5, iclass 5, count 0 2006.257.18:23:28.49#ibcon#read 5, iclass 5, count 0 2006.257.18:23:28.49#ibcon#about to read 6, iclass 5, count 0 2006.257.18:23:28.49#ibcon#read 6, iclass 5, count 0 2006.257.18:23:28.49#ibcon#end of sib2, iclass 5, count 0 2006.257.18:23:28.49#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:23:28.49#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:23:28.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:23:28.49#ibcon#*before write, iclass 5, count 0 2006.257.18:23:28.49#ibcon#enter sib2, iclass 5, count 0 2006.257.18:23:28.49#ibcon#flushed, iclass 5, count 0 2006.257.18:23:28.49#ibcon#about to write, iclass 5, count 0 2006.257.18:23:28.49#ibcon#wrote, iclass 5, count 0 2006.257.18:23:28.49#ibcon#about to read 3, iclass 5, count 0 2006.257.18:23:28.53#ibcon#read 3, iclass 5, count 0 2006.257.18:23:28.53#ibcon#about to read 4, iclass 5, count 0 2006.257.18:23:28.53#ibcon#read 4, iclass 5, count 0 2006.257.18:23:28.53#ibcon#about to read 5, iclass 5, count 0 2006.257.18:23:28.53#ibcon#read 5, iclass 5, count 0 2006.257.18:23:28.53#ibcon#about to read 6, iclass 5, count 0 2006.257.18:23:28.53#ibcon#read 6, iclass 5, count 0 2006.257.18:23:28.53#ibcon#end of sib2, iclass 5, count 0 2006.257.18:23:28.53#ibcon#*after write, iclass 5, count 0 2006.257.18:23:28.53#ibcon#*before return 0, iclass 5, count 0 2006.257.18:23:28.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:23:28.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:23:28.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:23:28.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:23:28.53$vck44/va=7,4 2006.257.18:23:28.53#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.18:23:28.53#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.18:23:28.53#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:28.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:23:28.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:23:28.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:23:28.59#ibcon#enter wrdev, iclass 7, count 2 2006.257.18:23:28.59#ibcon#first serial, iclass 7, count 2 2006.257.18:23:28.59#ibcon#enter sib2, iclass 7, count 2 2006.257.18:23:28.59#ibcon#flushed, iclass 7, count 2 2006.257.18:23:28.59#ibcon#about to write, iclass 7, count 2 2006.257.18:23:28.59#ibcon#wrote, iclass 7, count 2 2006.257.18:23:28.59#ibcon#about to read 3, iclass 7, count 2 2006.257.18:23:28.61#ibcon#read 3, iclass 7, count 2 2006.257.18:23:28.61#ibcon#about to read 4, iclass 7, count 2 2006.257.18:23:28.61#ibcon#read 4, iclass 7, count 2 2006.257.18:23:28.61#ibcon#about to read 5, iclass 7, count 2 2006.257.18:23:28.61#ibcon#read 5, iclass 7, count 2 2006.257.18:23:28.61#ibcon#about to read 6, iclass 7, count 2 2006.257.18:23:28.61#ibcon#read 6, iclass 7, count 2 2006.257.18:23:28.61#ibcon#end of sib2, iclass 7, count 2 2006.257.18:23:28.61#ibcon#*mode == 0, iclass 7, count 2 2006.257.18:23:28.61#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.18:23:28.61#ibcon#[25=AT07-04\r\n] 2006.257.18:23:28.61#ibcon#*before write, iclass 7, count 2 2006.257.18:23:28.61#ibcon#enter sib2, iclass 7, count 2 2006.257.18:23:28.61#ibcon#flushed, iclass 7, count 2 2006.257.18:23:28.61#ibcon#about to write, iclass 7, count 2 2006.257.18:23:28.61#ibcon#wrote, iclass 7, count 2 2006.257.18:23:28.61#ibcon#about to read 3, iclass 7, count 2 2006.257.18:23:28.64#ibcon#read 3, iclass 7, count 2 2006.257.18:23:28.64#ibcon#about to read 4, iclass 7, count 2 2006.257.18:23:28.64#ibcon#read 4, iclass 7, count 2 2006.257.18:23:28.64#ibcon#about to read 5, iclass 7, count 2 2006.257.18:23:28.64#ibcon#read 5, iclass 7, count 2 2006.257.18:23:28.64#ibcon#about to read 6, iclass 7, count 2 2006.257.18:23:28.64#ibcon#read 6, iclass 7, count 2 2006.257.18:23:28.64#ibcon#end of sib2, iclass 7, count 2 2006.257.18:23:28.64#ibcon#*after write, iclass 7, count 2 2006.257.18:23:28.64#ibcon#*before return 0, iclass 7, count 2 2006.257.18:23:28.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:23:28.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:23:28.64#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.18:23:28.64#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:28.64#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:23:28.76#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:23:28.76#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:23:28.76#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:23:28.76#ibcon#first serial, iclass 7, count 0 2006.257.18:23:28.76#ibcon#enter sib2, iclass 7, count 0 2006.257.18:23:28.76#ibcon#flushed, iclass 7, count 0 2006.257.18:23:28.76#ibcon#about to write, iclass 7, count 0 2006.257.18:23:28.76#ibcon#wrote, iclass 7, count 0 2006.257.18:23:28.76#ibcon#about to read 3, iclass 7, count 0 2006.257.18:23:28.78#ibcon#read 3, iclass 7, count 0 2006.257.18:23:28.78#ibcon#about to read 4, iclass 7, count 0 2006.257.18:23:28.78#ibcon#read 4, iclass 7, count 0 2006.257.18:23:28.78#ibcon#about to read 5, iclass 7, count 0 2006.257.18:23:28.78#ibcon#read 5, iclass 7, count 0 2006.257.18:23:28.78#ibcon#about to read 6, iclass 7, count 0 2006.257.18:23:28.78#ibcon#read 6, iclass 7, count 0 2006.257.18:23:28.78#ibcon#end of sib2, iclass 7, count 0 2006.257.18:23:28.78#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:23:28.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:23:28.78#ibcon#[25=USB\r\n] 2006.257.18:23:28.78#ibcon#*before write, iclass 7, count 0 2006.257.18:23:28.78#ibcon#enter sib2, iclass 7, count 0 2006.257.18:23:28.78#ibcon#flushed, iclass 7, count 0 2006.257.18:23:28.78#ibcon#about to write, iclass 7, count 0 2006.257.18:23:28.78#ibcon#wrote, iclass 7, count 0 2006.257.18:23:28.78#ibcon#about to read 3, iclass 7, count 0 2006.257.18:23:28.81#ibcon#read 3, iclass 7, count 0 2006.257.18:23:28.81#ibcon#about to read 4, iclass 7, count 0 2006.257.18:23:28.81#ibcon#read 4, iclass 7, count 0 2006.257.18:23:28.81#ibcon#about to read 5, iclass 7, count 0 2006.257.18:23:28.81#ibcon#read 5, iclass 7, count 0 2006.257.18:23:28.81#ibcon#about to read 6, iclass 7, count 0 2006.257.18:23:28.81#ibcon#read 6, iclass 7, count 0 2006.257.18:23:28.81#ibcon#end of sib2, iclass 7, count 0 2006.257.18:23:28.81#ibcon#*after write, iclass 7, count 0 2006.257.18:23:28.81#ibcon#*before return 0, iclass 7, count 0 2006.257.18:23:28.81#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:23:28.81#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:23:28.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:23:28.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:23:28.81$vck44/valo=8,884.99 2006.257.18:23:28.81#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.18:23:28.81#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.18:23:28.81#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:28.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:23:28.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:23:28.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:23:28.81#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:23:28.81#ibcon#first serial, iclass 11, count 0 2006.257.18:23:28.81#ibcon#enter sib2, iclass 11, count 0 2006.257.18:23:28.81#ibcon#flushed, iclass 11, count 0 2006.257.18:23:28.81#ibcon#about to write, iclass 11, count 0 2006.257.18:23:28.81#ibcon#wrote, iclass 11, count 0 2006.257.18:23:28.81#ibcon#about to read 3, iclass 11, count 0 2006.257.18:23:28.83#ibcon#read 3, iclass 11, count 0 2006.257.18:23:28.83#ibcon#about to read 4, iclass 11, count 0 2006.257.18:23:28.83#ibcon#read 4, iclass 11, count 0 2006.257.18:23:28.83#ibcon#about to read 5, iclass 11, count 0 2006.257.18:23:28.83#ibcon#read 5, iclass 11, count 0 2006.257.18:23:28.83#ibcon#about to read 6, iclass 11, count 0 2006.257.18:23:28.83#ibcon#read 6, iclass 11, count 0 2006.257.18:23:28.83#ibcon#end of sib2, iclass 11, count 0 2006.257.18:23:28.83#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:23:28.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:23:28.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:23:28.83#ibcon#*before write, iclass 11, count 0 2006.257.18:23:28.83#ibcon#enter sib2, iclass 11, count 0 2006.257.18:23:28.83#ibcon#flushed, iclass 11, count 0 2006.257.18:23:28.83#ibcon#about to write, iclass 11, count 0 2006.257.18:23:28.83#ibcon#wrote, iclass 11, count 0 2006.257.18:23:28.83#ibcon#about to read 3, iclass 11, count 0 2006.257.18:23:28.87#ibcon#read 3, iclass 11, count 0 2006.257.18:23:28.87#ibcon#about to read 4, iclass 11, count 0 2006.257.18:23:28.87#ibcon#read 4, iclass 11, count 0 2006.257.18:23:28.87#ibcon#about to read 5, iclass 11, count 0 2006.257.18:23:28.87#ibcon#read 5, iclass 11, count 0 2006.257.18:23:28.87#ibcon#about to read 6, iclass 11, count 0 2006.257.18:23:28.87#ibcon#read 6, iclass 11, count 0 2006.257.18:23:28.87#ibcon#end of sib2, iclass 11, count 0 2006.257.18:23:28.87#ibcon#*after write, iclass 11, count 0 2006.257.18:23:28.87#ibcon#*before return 0, iclass 11, count 0 2006.257.18:23:28.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:23:28.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:23:28.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:23:28.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:23:28.87$vck44/va=8,4 2006.257.18:23:28.87#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.18:23:28.87#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.18:23:28.87#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:28.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:28.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:28.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:28.93#ibcon#enter wrdev, iclass 13, count 2 2006.257.18:23:28.93#ibcon#first serial, iclass 13, count 2 2006.257.18:23:28.93#ibcon#enter sib2, iclass 13, count 2 2006.257.18:23:28.93#ibcon#flushed, iclass 13, count 2 2006.257.18:23:28.93#ibcon#about to write, iclass 13, count 2 2006.257.18:23:28.93#ibcon#wrote, iclass 13, count 2 2006.257.18:23:28.93#ibcon#about to read 3, iclass 13, count 2 2006.257.18:23:28.95#ibcon#read 3, iclass 13, count 2 2006.257.18:23:28.95#ibcon#about to read 4, iclass 13, count 2 2006.257.18:23:28.95#ibcon#read 4, iclass 13, count 2 2006.257.18:23:28.95#ibcon#about to read 5, iclass 13, count 2 2006.257.18:23:28.95#ibcon#read 5, iclass 13, count 2 2006.257.18:23:28.95#ibcon#about to read 6, iclass 13, count 2 2006.257.18:23:28.95#ibcon#read 6, iclass 13, count 2 2006.257.18:23:28.95#ibcon#end of sib2, iclass 13, count 2 2006.257.18:23:28.95#ibcon#*mode == 0, iclass 13, count 2 2006.257.18:23:28.95#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.18:23:28.95#ibcon#[25=AT08-04\r\n] 2006.257.18:23:28.95#ibcon#*before write, iclass 13, count 2 2006.257.18:23:28.95#ibcon#enter sib2, iclass 13, count 2 2006.257.18:23:28.95#ibcon#flushed, iclass 13, count 2 2006.257.18:23:28.95#ibcon#about to write, iclass 13, count 2 2006.257.18:23:28.95#ibcon#wrote, iclass 13, count 2 2006.257.18:23:28.95#ibcon#about to read 3, iclass 13, count 2 2006.257.18:23:28.98#ibcon#read 3, iclass 13, count 2 2006.257.18:23:28.98#ibcon#about to read 4, iclass 13, count 2 2006.257.18:23:28.98#ibcon#read 4, iclass 13, count 2 2006.257.18:23:28.98#ibcon#about to read 5, iclass 13, count 2 2006.257.18:23:28.98#ibcon#read 5, iclass 13, count 2 2006.257.18:23:28.98#ibcon#about to read 6, iclass 13, count 2 2006.257.18:23:28.98#ibcon#read 6, iclass 13, count 2 2006.257.18:23:28.98#ibcon#end of sib2, iclass 13, count 2 2006.257.18:23:28.98#ibcon#*after write, iclass 13, count 2 2006.257.18:23:28.98#ibcon#*before return 0, iclass 13, count 2 2006.257.18:23:28.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:28.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:28.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.18:23:28.98#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:28.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:29.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:29.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:29.10#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:23:29.10#ibcon#first serial, iclass 13, count 0 2006.257.18:23:29.10#ibcon#enter sib2, iclass 13, count 0 2006.257.18:23:29.10#ibcon#flushed, iclass 13, count 0 2006.257.18:23:29.10#ibcon#about to write, iclass 13, count 0 2006.257.18:23:29.10#ibcon#wrote, iclass 13, count 0 2006.257.18:23:29.10#ibcon#about to read 3, iclass 13, count 0 2006.257.18:23:29.12#ibcon#read 3, iclass 13, count 0 2006.257.18:23:29.12#ibcon#about to read 4, iclass 13, count 0 2006.257.18:23:29.12#ibcon#read 4, iclass 13, count 0 2006.257.18:23:29.12#ibcon#about to read 5, iclass 13, count 0 2006.257.18:23:29.12#ibcon#read 5, iclass 13, count 0 2006.257.18:23:29.12#ibcon#about to read 6, iclass 13, count 0 2006.257.18:23:29.12#ibcon#read 6, iclass 13, count 0 2006.257.18:23:29.12#ibcon#end of sib2, iclass 13, count 0 2006.257.18:23:29.12#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:23:29.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:23:29.12#ibcon#[25=USB\r\n] 2006.257.18:23:29.12#ibcon#*before write, iclass 13, count 0 2006.257.18:23:29.12#ibcon#enter sib2, iclass 13, count 0 2006.257.18:23:29.12#ibcon#flushed, iclass 13, count 0 2006.257.18:23:29.12#ibcon#about to write, iclass 13, count 0 2006.257.18:23:29.12#ibcon#wrote, iclass 13, count 0 2006.257.18:23:29.12#ibcon#about to read 3, iclass 13, count 0 2006.257.18:23:29.15#ibcon#read 3, iclass 13, count 0 2006.257.18:23:29.15#ibcon#about to read 4, iclass 13, count 0 2006.257.18:23:29.15#ibcon#read 4, iclass 13, count 0 2006.257.18:23:29.15#ibcon#about to read 5, iclass 13, count 0 2006.257.18:23:29.15#ibcon#read 5, iclass 13, count 0 2006.257.18:23:29.15#ibcon#about to read 6, iclass 13, count 0 2006.257.18:23:29.15#ibcon#read 6, iclass 13, count 0 2006.257.18:23:29.15#ibcon#end of sib2, iclass 13, count 0 2006.257.18:23:29.15#ibcon#*after write, iclass 13, count 0 2006.257.18:23:29.15#ibcon#*before return 0, iclass 13, count 0 2006.257.18:23:29.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:29.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:29.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:23:29.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:23:29.15$vck44/vblo=1,629.99 2006.257.18:23:29.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.18:23:29.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.18:23:29.15#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:29.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:29.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:29.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:29.15#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:23:29.15#ibcon#first serial, iclass 15, count 0 2006.257.18:23:29.15#ibcon#enter sib2, iclass 15, count 0 2006.257.18:23:29.15#ibcon#flushed, iclass 15, count 0 2006.257.18:23:29.15#ibcon#about to write, iclass 15, count 0 2006.257.18:23:29.15#ibcon#wrote, iclass 15, count 0 2006.257.18:23:29.15#ibcon#about to read 3, iclass 15, count 0 2006.257.18:23:29.17#ibcon#read 3, iclass 15, count 0 2006.257.18:23:29.17#ibcon#about to read 4, iclass 15, count 0 2006.257.18:23:29.17#ibcon#read 4, iclass 15, count 0 2006.257.18:23:29.17#ibcon#about to read 5, iclass 15, count 0 2006.257.18:23:29.17#ibcon#read 5, iclass 15, count 0 2006.257.18:23:29.17#ibcon#about to read 6, iclass 15, count 0 2006.257.18:23:29.17#ibcon#read 6, iclass 15, count 0 2006.257.18:23:29.17#ibcon#end of sib2, iclass 15, count 0 2006.257.18:23:29.17#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:23:29.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:23:29.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:23:29.17#ibcon#*before write, iclass 15, count 0 2006.257.18:23:29.17#ibcon#enter sib2, iclass 15, count 0 2006.257.18:23:29.17#ibcon#flushed, iclass 15, count 0 2006.257.18:23:29.17#ibcon#about to write, iclass 15, count 0 2006.257.18:23:29.17#ibcon#wrote, iclass 15, count 0 2006.257.18:23:29.17#ibcon#about to read 3, iclass 15, count 0 2006.257.18:23:29.21#ibcon#read 3, iclass 15, count 0 2006.257.18:23:29.21#ibcon#about to read 4, iclass 15, count 0 2006.257.18:23:29.21#ibcon#read 4, iclass 15, count 0 2006.257.18:23:29.21#ibcon#about to read 5, iclass 15, count 0 2006.257.18:23:29.21#ibcon#read 5, iclass 15, count 0 2006.257.18:23:29.21#ibcon#about to read 6, iclass 15, count 0 2006.257.18:23:29.21#ibcon#read 6, iclass 15, count 0 2006.257.18:23:29.21#ibcon#end of sib2, iclass 15, count 0 2006.257.18:23:29.21#ibcon#*after write, iclass 15, count 0 2006.257.18:23:29.21#ibcon#*before return 0, iclass 15, count 0 2006.257.18:23:29.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:29.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:29.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:23:29.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:23:29.21$vck44/vb=1,4 2006.257.18:23:29.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.18:23:29.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.18:23:29.21#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:29.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:23:29.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:23:29.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:23:29.21#ibcon#enter wrdev, iclass 17, count 2 2006.257.18:23:29.21#ibcon#first serial, iclass 17, count 2 2006.257.18:23:29.21#ibcon#enter sib2, iclass 17, count 2 2006.257.18:23:29.21#ibcon#flushed, iclass 17, count 2 2006.257.18:23:29.21#ibcon#about to write, iclass 17, count 2 2006.257.18:23:29.21#ibcon#wrote, iclass 17, count 2 2006.257.18:23:29.21#ibcon#about to read 3, iclass 17, count 2 2006.257.18:23:29.23#ibcon#read 3, iclass 17, count 2 2006.257.18:23:29.23#ibcon#about to read 4, iclass 17, count 2 2006.257.18:23:29.23#ibcon#read 4, iclass 17, count 2 2006.257.18:23:29.23#ibcon#about to read 5, iclass 17, count 2 2006.257.18:23:29.23#ibcon#read 5, iclass 17, count 2 2006.257.18:23:29.23#ibcon#about to read 6, iclass 17, count 2 2006.257.18:23:29.23#ibcon#read 6, iclass 17, count 2 2006.257.18:23:29.23#ibcon#end of sib2, iclass 17, count 2 2006.257.18:23:29.23#ibcon#*mode == 0, iclass 17, count 2 2006.257.18:23:29.23#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.18:23:29.23#ibcon#[27=AT01-04\r\n] 2006.257.18:23:29.23#ibcon#*before write, iclass 17, count 2 2006.257.18:23:29.23#ibcon#enter sib2, iclass 17, count 2 2006.257.18:23:29.23#ibcon#flushed, iclass 17, count 2 2006.257.18:23:29.23#ibcon#about to write, iclass 17, count 2 2006.257.18:23:29.23#ibcon#wrote, iclass 17, count 2 2006.257.18:23:29.23#ibcon#about to read 3, iclass 17, count 2 2006.257.18:23:29.26#ibcon#read 3, iclass 17, count 2 2006.257.18:23:29.26#ibcon#about to read 4, iclass 17, count 2 2006.257.18:23:29.26#ibcon#read 4, iclass 17, count 2 2006.257.18:23:29.26#ibcon#about to read 5, iclass 17, count 2 2006.257.18:23:29.26#ibcon#read 5, iclass 17, count 2 2006.257.18:23:29.26#ibcon#about to read 6, iclass 17, count 2 2006.257.18:23:29.26#ibcon#read 6, iclass 17, count 2 2006.257.18:23:29.26#ibcon#end of sib2, iclass 17, count 2 2006.257.18:23:29.26#ibcon#*after write, iclass 17, count 2 2006.257.18:23:29.26#ibcon#*before return 0, iclass 17, count 2 2006.257.18:23:29.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:23:29.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:23:29.26#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.18:23:29.26#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:29.26#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:23:29.38#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:23:29.38#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:23:29.38#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:23:29.38#ibcon#first serial, iclass 17, count 0 2006.257.18:23:29.38#ibcon#enter sib2, iclass 17, count 0 2006.257.18:23:29.38#ibcon#flushed, iclass 17, count 0 2006.257.18:23:29.38#ibcon#about to write, iclass 17, count 0 2006.257.18:23:29.38#ibcon#wrote, iclass 17, count 0 2006.257.18:23:29.38#ibcon#about to read 3, iclass 17, count 0 2006.257.18:23:29.40#ibcon#read 3, iclass 17, count 0 2006.257.18:23:29.40#ibcon#about to read 4, iclass 17, count 0 2006.257.18:23:29.40#ibcon#read 4, iclass 17, count 0 2006.257.18:23:29.40#ibcon#about to read 5, iclass 17, count 0 2006.257.18:23:29.40#ibcon#read 5, iclass 17, count 0 2006.257.18:23:29.40#ibcon#about to read 6, iclass 17, count 0 2006.257.18:23:29.40#ibcon#read 6, iclass 17, count 0 2006.257.18:23:29.40#ibcon#end of sib2, iclass 17, count 0 2006.257.18:23:29.40#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:23:29.40#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:23:29.40#ibcon#[27=USB\r\n] 2006.257.18:23:29.40#ibcon#*before write, iclass 17, count 0 2006.257.18:23:29.40#ibcon#enter sib2, iclass 17, count 0 2006.257.18:23:29.40#ibcon#flushed, iclass 17, count 0 2006.257.18:23:29.40#ibcon#about to write, iclass 17, count 0 2006.257.18:23:29.40#ibcon#wrote, iclass 17, count 0 2006.257.18:23:29.40#ibcon#about to read 3, iclass 17, count 0 2006.257.18:23:29.43#ibcon#read 3, iclass 17, count 0 2006.257.18:23:29.43#ibcon#about to read 4, iclass 17, count 0 2006.257.18:23:29.43#ibcon#read 4, iclass 17, count 0 2006.257.18:23:29.43#ibcon#about to read 5, iclass 17, count 0 2006.257.18:23:29.43#ibcon#read 5, iclass 17, count 0 2006.257.18:23:29.43#ibcon#about to read 6, iclass 17, count 0 2006.257.18:23:29.43#ibcon#read 6, iclass 17, count 0 2006.257.18:23:29.43#ibcon#end of sib2, iclass 17, count 0 2006.257.18:23:29.43#ibcon#*after write, iclass 17, count 0 2006.257.18:23:29.43#ibcon#*before return 0, iclass 17, count 0 2006.257.18:23:29.43#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:23:29.43#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:23:29.43#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:23:29.43#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:23:29.43$vck44/vblo=2,634.99 2006.257.18:23:29.43#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.18:23:29.43#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.18:23:29.43#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:29.43#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:29.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:29.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:29.43#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:23:29.43#ibcon#first serial, iclass 19, count 0 2006.257.18:23:29.43#ibcon#enter sib2, iclass 19, count 0 2006.257.18:23:29.43#ibcon#flushed, iclass 19, count 0 2006.257.18:23:29.43#ibcon#about to write, iclass 19, count 0 2006.257.18:23:29.43#ibcon#wrote, iclass 19, count 0 2006.257.18:23:29.43#ibcon#about to read 3, iclass 19, count 0 2006.257.18:23:29.45#ibcon#read 3, iclass 19, count 0 2006.257.18:23:29.45#ibcon#about to read 4, iclass 19, count 0 2006.257.18:23:29.45#ibcon#read 4, iclass 19, count 0 2006.257.18:23:29.45#ibcon#about to read 5, iclass 19, count 0 2006.257.18:23:29.45#ibcon#read 5, iclass 19, count 0 2006.257.18:23:29.45#ibcon#about to read 6, iclass 19, count 0 2006.257.18:23:29.45#ibcon#read 6, iclass 19, count 0 2006.257.18:23:29.45#ibcon#end of sib2, iclass 19, count 0 2006.257.18:23:29.45#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:23:29.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:23:29.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:23:29.45#ibcon#*before write, iclass 19, count 0 2006.257.18:23:29.45#ibcon#enter sib2, iclass 19, count 0 2006.257.18:23:29.45#ibcon#flushed, iclass 19, count 0 2006.257.18:23:29.45#ibcon#about to write, iclass 19, count 0 2006.257.18:23:29.45#ibcon#wrote, iclass 19, count 0 2006.257.18:23:29.45#ibcon#about to read 3, iclass 19, count 0 2006.257.18:23:29.49#ibcon#read 3, iclass 19, count 0 2006.257.18:23:29.49#ibcon#about to read 4, iclass 19, count 0 2006.257.18:23:29.49#ibcon#read 4, iclass 19, count 0 2006.257.18:23:29.49#ibcon#about to read 5, iclass 19, count 0 2006.257.18:23:29.49#ibcon#read 5, iclass 19, count 0 2006.257.18:23:29.49#ibcon#about to read 6, iclass 19, count 0 2006.257.18:23:29.49#ibcon#read 6, iclass 19, count 0 2006.257.18:23:29.49#ibcon#end of sib2, iclass 19, count 0 2006.257.18:23:29.49#ibcon#*after write, iclass 19, count 0 2006.257.18:23:29.49#ibcon#*before return 0, iclass 19, count 0 2006.257.18:23:29.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:29.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:23:29.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:23:29.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:23:29.49$vck44/vb=2,5 2006.257.18:23:29.49#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.18:23:29.49#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.18:23:29.49#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:29.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:29.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:29.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:29.55#ibcon#enter wrdev, iclass 21, count 2 2006.257.18:23:29.55#ibcon#first serial, iclass 21, count 2 2006.257.18:23:29.55#ibcon#enter sib2, iclass 21, count 2 2006.257.18:23:29.55#ibcon#flushed, iclass 21, count 2 2006.257.18:23:29.55#ibcon#about to write, iclass 21, count 2 2006.257.18:23:29.55#ibcon#wrote, iclass 21, count 2 2006.257.18:23:29.55#ibcon#about to read 3, iclass 21, count 2 2006.257.18:23:29.57#ibcon#read 3, iclass 21, count 2 2006.257.18:23:29.57#ibcon#about to read 4, iclass 21, count 2 2006.257.18:23:29.57#ibcon#read 4, iclass 21, count 2 2006.257.18:23:29.57#ibcon#about to read 5, iclass 21, count 2 2006.257.18:23:29.57#ibcon#read 5, iclass 21, count 2 2006.257.18:23:29.57#ibcon#about to read 6, iclass 21, count 2 2006.257.18:23:29.57#ibcon#read 6, iclass 21, count 2 2006.257.18:23:29.57#ibcon#end of sib2, iclass 21, count 2 2006.257.18:23:29.57#ibcon#*mode == 0, iclass 21, count 2 2006.257.18:23:29.57#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.18:23:29.57#ibcon#[27=AT02-05\r\n] 2006.257.18:23:29.57#ibcon#*before write, iclass 21, count 2 2006.257.18:23:29.57#ibcon#enter sib2, iclass 21, count 2 2006.257.18:23:29.57#ibcon#flushed, iclass 21, count 2 2006.257.18:23:29.57#ibcon#about to write, iclass 21, count 2 2006.257.18:23:29.57#ibcon#wrote, iclass 21, count 2 2006.257.18:23:29.57#ibcon#about to read 3, iclass 21, count 2 2006.257.18:23:29.60#ibcon#read 3, iclass 21, count 2 2006.257.18:23:29.60#ibcon#about to read 4, iclass 21, count 2 2006.257.18:23:29.60#ibcon#read 4, iclass 21, count 2 2006.257.18:23:29.60#ibcon#about to read 5, iclass 21, count 2 2006.257.18:23:29.60#ibcon#read 5, iclass 21, count 2 2006.257.18:23:29.60#ibcon#about to read 6, iclass 21, count 2 2006.257.18:23:29.60#ibcon#read 6, iclass 21, count 2 2006.257.18:23:29.60#ibcon#end of sib2, iclass 21, count 2 2006.257.18:23:29.60#ibcon#*after write, iclass 21, count 2 2006.257.18:23:29.60#ibcon#*before return 0, iclass 21, count 2 2006.257.18:23:29.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:29.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:23:29.60#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.18:23:29.60#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:29.60#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:29.72#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:29.72#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:29.72#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:23:29.72#ibcon#first serial, iclass 21, count 0 2006.257.18:23:29.72#ibcon#enter sib2, iclass 21, count 0 2006.257.18:23:29.72#ibcon#flushed, iclass 21, count 0 2006.257.18:23:29.72#ibcon#about to write, iclass 21, count 0 2006.257.18:23:29.72#ibcon#wrote, iclass 21, count 0 2006.257.18:23:29.72#ibcon#about to read 3, iclass 21, count 0 2006.257.18:23:29.74#ibcon#read 3, iclass 21, count 0 2006.257.18:23:29.74#ibcon#about to read 4, iclass 21, count 0 2006.257.18:23:29.74#ibcon#read 4, iclass 21, count 0 2006.257.18:23:29.74#ibcon#about to read 5, iclass 21, count 0 2006.257.18:23:29.74#ibcon#read 5, iclass 21, count 0 2006.257.18:23:29.74#ibcon#about to read 6, iclass 21, count 0 2006.257.18:23:29.74#ibcon#read 6, iclass 21, count 0 2006.257.18:23:29.74#ibcon#end of sib2, iclass 21, count 0 2006.257.18:23:29.74#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:23:29.74#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:23:29.74#ibcon#[27=USB\r\n] 2006.257.18:23:29.74#ibcon#*before write, iclass 21, count 0 2006.257.18:23:29.74#ibcon#enter sib2, iclass 21, count 0 2006.257.18:23:29.74#ibcon#flushed, iclass 21, count 0 2006.257.18:23:29.74#ibcon#about to write, iclass 21, count 0 2006.257.18:23:29.74#ibcon#wrote, iclass 21, count 0 2006.257.18:23:29.74#ibcon#about to read 3, iclass 21, count 0 2006.257.18:23:29.77#ibcon#read 3, iclass 21, count 0 2006.257.18:23:29.77#ibcon#about to read 4, iclass 21, count 0 2006.257.18:23:29.77#ibcon#read 4, iclass 21, count 0 2006.257.18:23:29.77#ibcon#about to read 5, iclass 21, count 0 2006.257.18:23:29.77#ibcon#read 5, iclass 21, count 0 2006.257.18:23:29.77#ibcon#about to read 6, iclass 21, count 0 2006.257.18:23:29.77#ibcon#read 6, iclass 21, count 0 2006.257.18:23:29.77#ibcon#end of sib2, iclass 21, count 0 2006.257.18:23:29.77#ibcon#*after write, iclass 21, count 0 2006.257.18:23:29.77#ibcon#*before return 0, iclass 21, count 0 2006.257.18:23:29.77#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:29.77#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:23:29.77#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:23:29.77#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:23:29.77$vck44/vblo=3,649.99 2006.257.18:23:29.77#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.18:23:29.77#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.18:23:29.77#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:29.77#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:29.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:29.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:29.77#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:23:29.77#ibcon#first serial, iclass 23, count 0 2006.257.18:23:29.77#ibcon#enter sib2, iclass 23, count 0 2006.257.18:23:29.77#ibcon#flushed, iclass 23, count 0 2006.257.18:23:29.77#ibcon#about to write, iclass 23, count 0 2006.257.18:23:29.77#ibcon#wrote, iclass 23, count 0 2006.257.18:23:29.77#ibcon#about to read 3, iclass 23, count 0 2006.257.18:23:29.79#ibcon#read 3, iclass 23, count 0 2006.257.18:23:29.79#ibcon#about to read 4, iclass 23, count 0 2006.257.18:23:29.79#ibcon#read 4, iclass 23, count 0 2006.257.18:23:29.79#ibcon#about to read 5, iclass 23, count 0 2006.257.18:23:29.79#ibcon#read 5, iclass 23, count 0 2006.257.18:23:29.79#ibcon#about to read 6, iclass 23, count 0 2006.257.18:23:29.79#ibcon#read 6, iclass 23, count 0 2006.257.18:23:29.79#ibcon#end of sib2, iclass 23, count 0 2006.257.18:23:29.79#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:23:29.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:23:29.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:23:29.79#ibcon#*before write, iclass 23, count 0 2006.257.18:23:29.79#ibcon#enter sib2, iclass 23, count 0 2006.257.18:23:29.79#ibcon#flushed, iclass 23, count 0 2006.257.18:23:29.79#ibcon#about to write, iclass 23, count 0 2006.257.18:23:29.79#ibcon#wrote, iclass 23, count 0 2006.257.18:23:29.79#ibcon#about to read 3, iclass 23, count 0 2006.257.18:23:29.83#ibcon#read 3, iclass 23, count 0 2006.257.18:23:29.83#ibcon#about to read 4, iclass 23, count 0 2006.257.18:23:29.83#ibcon#read 4, iclass 23, count 0 2006.257.18:23:29.83#ibcon#about to read 5, iclass 23, count 0 2006.257.18:23:29.83#ibcon#read 5, iclass 23, count 0 2006.257.18:23:29.83#ibcon#about to read 6, iclass 23, count 0 2006.257.18:23:29.83#ibcon#read 6, iclass 23, count 0 2006.257.18:23:29.83#ibcon#end of sib2, iclass 23, count 0 2006.257.18:23:29.83#ibcon#*after write, iclass 23, count 0 2006.257.18:23:29.83#ibcon#*before return 0, iclass 23, count 0 2006.257.18:23:29.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:29.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:23:29.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:23:29.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:23:29.83$vck44/vb=3,4 2006.257.18:23:29.83#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.18:23:29.83#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.18:23:29.83#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:29.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:29.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:29.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:29.89#ibcon#enter wrdev, iclass 25, count 2 2006.257.18:23:29.89#ibcon#first serial, iclass 25, count 2 2006.257.18:23:29.89#ibcon#enter sib2, iclass 25, count 2 2006.257.18:23:29.89#ibcon#flushed, iclass 25, count 2 2006.257.18:23:29.89#ibcon#about to write, iclass 25, count 2 2006.257.18:23:29.89#ibcon#wrote, iclass 25, count 2 2006.257.18:23:29.89#ibcon#about to read 3, iclass 25, count 2 2006.257.18:23:29.91#ibcon#read 3, iclass 25, count 2 2006.257.18:23:29.91#ibcon#about to read 4, iclass 25, count 2 2006.257.18:23:29.91#ibcon#read 4, iclass 25, count 2 2006.257.18:23:29.91#ibcon#about to read 5, iclass 25, count 2 2006.257.18:23:29.91#ibcon#read 5, iclass 25, count 2 2006.257.18:23:29.91#ibcon#about to read 6, iclass 25, count 2 2006.257.18:23:29.91#ibcon#read 6, iclass 25, count 2 2006.257.18:23:29.91#ibcon#end of sib2, iclass 25, count 2 2006.257.18:23:29.91#ibcon#*mode == 0, iclass 25, count 2 2006.257.18:23:29.91#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.18:23:29.91#ibcon#[27=AT03-04\r\n] 2006.257.18:23:29.91#ibcon#*before write, iclass 25, count 2 2006.257.18:23:29.91#ibcon#enter sib2, iclass 25, count 2 2006.257.18:23:29.91#ibcon#flushed, iclass 25, count 2 2006.257.18:23:29.91#ibcon#about to write, iclass 25, count 2 2006.257.18:23:29.91#ibcon#wrote, iclass 25, count 2 2006.257.18:23:29.91#ibcon#about to read 3, iclass 25, count 2 2006.257.18:23:29.94#ibcon#read 3, iclass 25, count 2 2006.257.18:23:29.94#ibcon#about to read 4, iclass 25, count 2 2006.257.18:23:29.94#ibcon#read 4, iclass 25, count 2 2006.257.18:23:29.94#ibcon#about to read 5, iclass 25, count 2 2006.257.18:23:29.94#ibcon#read 5, iclass 25, count 2 2006.257.18:23:29.94#ibcon#about to read 6, iclass 25, count 2 2006.257.18:23:29.94#ibcon#read 6, iclass 25, count 2 2006.257.18:23:29.94#ibcon#end of sib2, iclass 25, count 2 2006.257.18:23:29.94#ibcon#*after write, iclass 25, count 2 2006.257.18:23:29.94#ibcon#*before return 0, iclass 25, count 2 2006.257.18:23:29.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:29.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:23:29.94#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.18:23:29.94#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:29.94#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:30.06#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:30.06#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:30.06#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:23:30.06#ibcon#first serial, iclass 25, count 0 2006.257.18:23:30.06#ibcon#enter sib2, iclass 25, count 0 2006.257.18:23:30.06#ibcon#flushed, iclass 25, count 0 2006.257.18:23:30.06#ibcon#about to write, iclass 25, count 0 2006.257.18:23:30.06#ibcon#wrote, iclass 25, count 0 2006.257.18:23:30.06#ibcon#about to read 3, iclass 25, count 0 2006.257.18:23:30.08#ibcon#read 3, iclass 25, count 0 2006.257.18:23:30.08#ibcon#about to read 4, iclass 25, count 0 2006.257.18:23:30.08#ibcon#read 4, iclass 25, count 0 2006.257.18:23:30.08#ibcon#about to read 5, iclass 25, count 0 2006.257.18:23:30.08#ibcon#read 5, iclass 25, count 0 2006.257.18:23:30.08#ibcon#about to read 6, iclass 25, count 0 2006.257.18:23:30.08#ibcon#read 6, iclass 25, count 0 2006.257.18:23:30.08#ibcon#end of sib2, iclass 25, count 0 2006.257.18:23:30.08#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:23:30.08#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:23:30.08#ibcon#[27=USB\r\n] 2006.257.18:23:30.08#ibcon#*before write, iclass 25, count 0 2006.257.18:23:30.08#ibcon#enter sib2, iclass 25, count 0 2006.257.18:23:30.08#ibcon#flushed, iclass 25, count 0 2006.257.18:23:30.08#ibcon#about to write, iclass 25, count 0 2006.257.18:23:30.08#ibcon#wrote, iclass 25, count 0 2006.257.18:23:30.08#ibcon#about to read 3, iclass 25, count 0 2006.257.18:23:30.11#ibcon#read 3, iclass 25, count 0 2006.257.18:23:30.11#ibcon#about to read 4, iclass 25, count 0 2006.257.18:23:30.11#ibcon#read 4, iclass 25, count 0 2006.257.18:23:30.11#ibcon#about to read 5, iclass 25, count 0 2006.257.18:23:30.11#ibcon#read 5, iclass 25, count 0 2006.257.18:23:30.11#ibcon#about to read 6, iclass 25, count 0 2006.257.18:23:30.11#ibcon#read 6, iclass 25, count 0 2006.257.18:23:30.11#ibcon#end of sib2, iclass 25, count 0 2006.257.18:23:30.11#ibcon#*after write, iclass 25, count 0 2006.257.18:23:30.11#ibcon#*before return 0, iclass 25, count 0 2006.257.18:23:30.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:30.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:23:30.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:23:30.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:23:30.11$vck44/vblo=4,679.99 2006.257.18:23:30.11#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.18:23:30.11#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.18:23:30.11#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:30.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:30.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:30.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:30.11#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:23:30.11#ibcon#first serial, iclass 27, count 0 2006.257.18:23:30.11#ibcon#enter sib2, iclass 27, count 0 2006.257.18:23:30.11#ibcon#flushed, iclass 27, count 0 2006.257.18:23:30.11#ibcon#about to write, iclass 27, count 0 2006.257.18:23:30.11#ibcon#wrote, iclass 27, count 0 2006.257.18:23:30.11#ibcon#about to read 3, iclass 27, count 0 2006.257.18:23:30.13#ibcon#read 3, iclass 27, count 0 2006.257.18:23:30.13#ibcon#about to read 4, iclass 27, count 0 2006.257.18:23:30.13#ibcon#read 4, iclass 27, count 0 2006.257.18:23:30.13#ibcon#about to read 5, iclass 27, count 0 2006.257.18:23:30.13#ibcon#read 5, iclass 27, count 0 2006.257.18:23:30.13#ibcon#about to read 6, iclass 27, count 0 2006.257.18:23:30.13#ibcon#read 6, iclass 27, count 0 2006.257.18:23:30.13#ibcon#end of sib2, iclass 27, count 0 2006.257.18:23:30.13#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:23:30.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:23:30.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:23:30.13#ibcon#*before write, iclass 27, count 0 2006.257.18:23:30.13#ibcon#enter sib2, iclass 27, count 0 2006.257.18:23:30.13#ibcon#flushed, iclass 27, count 0 2006.257.18:23:30.13#ibcon#about to write, iclass 27, count 0 2006.257.18:23:30.13#ibcon#wrote, iclass 27, count 0 2006.257.18:23:30.13#ibcon#about to read 3, iclass 27, count 0 2006.257.18:23:30.17#ibcon#read 3, iclass 27, count 0 2006.257.18:23:30.17#ibcon#about to read 4, iclass 27, count 0 2006.257.18:23:30.17#ibcon#read 4, iclass 27, count 0 2006.257.18:23:30.17#ibcon#about to read 5, iclass 27, count 0 2006.257.18:23:30.17#ibcon#read 5, iclass 27, count 0 2006.257.18:23:30.17#ibcon#about to read 6, iclass 27, count 0 2006.257.18:23:30.17#ibcon#read 6, iclass 27, count 0 2006.257.18:23:30.17#ibcon#end of sib2, iclass 27, count 0 2006.257.18:23:30.17#ibcon#*after write, iclass 27, count 0 2006.257.18:23:30.17#ibcon#*before return 0, iclass 27, count 0 2006.257.18:23:30.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:30.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:23:30.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:23:30.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:23:30.17$vck44/vb=4,5 2006.257.18:23:30.17#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.18:23:30.17#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.18:23:30.17#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:30.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:30.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:30.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:30.23#ibcon#enter wrdev, iclass 29, count 2 2006.257.18:23:30.23#ibcon#first serial, iclass 29, count 2 2006.257.18:23:30.23#ibcon#enter sib2, iclass 29, count 2 2006.257.18:23:30.23#ibcon#flushed, iclass 29, count 2 2006.257.18:23:30.23#ibcon#about to write, iclass 29, count 2 2006.257.18:23:30.23#ibcon#wrote, iclass 29, count 2 2006.257.18:23:30.23#ibcon#about to read 3, iclass 29, count 2 2006.257.18:23:30.25#ibcon#read 3, iclass 29, count 2 2006.257.18:23:30.25#ibcon#about to read 4, iclass 29, count 2 2006.257.18:23:30.25#ibcon#read 4, iclass 29, count 2 2006.257.18:23:30.25#ibcon#about to read 5, iclass 29, count 2 2006.257.18:23:30.25#ibcon#read 5, iclass 29, count 2 2006.257.18:23:30.25#ibcon#about to read 6, iclass 29, count 2 2006.257.18:23:30.25#ibcon#read 6, iclass 29, count 2 2006.257.18:23:30.25#ibcon#end of sib2, iclass 29, count 2 2006.257.18:23:30.25#ibcon#*mode == 0, iclass 29, count 2 2006.257.18:23:30.25#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.18:23:30.25#ibcon#[27=AT04-05\r\n] 2006.257.18:23:30.25#ibcon#*before write, iclass 29, count 2 2006.257.18:23:30.25#ibcon#enter sib2, iclass 29, count 2 2006.257.18:23:30.25#ibcon#flushed, iclass 29, count 2 2006.257.18:23:30.25#ibcon#about to write, iclass 29, count 2 2006.257.18:23:30.25#ibcon#wrote, iclass 29, count 2 2006.257.18:23:30.25#ibcon#about to read 3, iclass 29, count 2 2006.257.18:23:30.28#ibcon#read 3, iclass 29, count 2 2006.257.18:23:30.28#ibcon#about to read 4, iclass 29, count 2 2006.257.18:23:30.28#ibcon#read 4, iclass 29, count 2 2006.257.18:23:30.28#ibcon#about to read 5, iclass 29, count 2 2006.257.18:23:30.28#ibcon#read 5, iclass 29, count 2 2006.257.18:23:30.28#ibcon#about to read 6, iclass 29, count 2 2006.257.18:23:30.28#ibcon#read 6, iclass 29, count 2 2006.257.18:23:30.28#ibcon#end of sib2, iclass 29, count 2 2006.257.18:23:30.28#ibcon#*after write, iclass 29, count 2 2006.257.18:23:30.28#ibcon#*before return 0, iclass 29, count 2 2006.257.18:23:30.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:30.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:23:30.28#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.18:23:30.28#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:30.28#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:30.40#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:30.40#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:30.40#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:23:30.40#ibcon#first serial, iclass 29, count 0 2006.257.18:23:30.40#ibcon#enter sib2, iclass 29, count 0 2006.257.18:23:30.40#ibcon#flushed, iclass 29, count 0 2006.257.18:23:30.40#ibcon#about to write, iclass 29, count 0 2006.257.18:23:30.40#ibcon#wrote, iclass 29, count 0 2006.257.18:23:30.40#ibcon#about to read 3, iclass 29, count 0 2006.257.18:23:30.42#ibcon#read 3, iclass 29, count 0 2006.257.18:23:30.42#ibcon#about to read 4, iclass 29, count 0 2006.257.18:23:30.42#ibcon#read 4, iclass 29, count 0 2006.257.18:23:30.42#ibcon#about to read 5, iclass 29, count 0 2006.257.18:23:30.42#ibcon#read 5, iclass 29, count 0 2006.257.18:23:30.42#ibcon#about to read 6, iclass 29, count 0 2006.257.18:23:30.42#ibcon#read 6, iclass 29, count 0 2006.257.18:23:30.42#ibcon#end of sib2, iclass 29, count 0 2006.257.18:23:30.42#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:23:30.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:23:30.42#ibcon#[27=USB\r\n] 2006.257.18:23:30.42#ibcon#*before write, iclass 29, count 0 2006.257.18:23:30.42#ibcon#enter sib2, iclass 29, count 0 2006.257.18:23:30.42#ibcon#flushed, iclass 29, count 0 2006.257.18:23:30.42#ibcon#about to write, iclass 29, count 0 2006.257.18:23:30.42#ibcon#wrote, iclass 29, count 0 2006.257.18:23:30.42#ibcon#about to read 3, iclass 29, count 0 2006.257.18:23:30.45#ibcon#read 3, iclass 29, count 0 2006.257.18:23:30.45#ibcon#about to read 4, iclass 29, count 0 2006.257.18:23:30.45#ibcon#read 4, iclass 29, count 0 2006.257.18:23:30.45#ibcon#about to read 5, iclass 29, count 0 2006.257.18:23:30.45#ibcon#read 5, iclass 29, count 0 2006.257.18:23:30.45#ibcon#about to read 6, iclass 29, count 0 2006.257.18:23:30.45#ibcon#read 6, iclass 29, count 0 2006.257.18:23:30.45#ibcon#end of sib2, iclass 29, count 0 2006.257.18:23:30.45#ibcon#*after write, iclass 29, count 0 2006.257.18:23:30.45#ibcon#*before return 0, iclass 29, count 0 2006.257.18:23:30.45#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:30.45#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:23:30.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:23:30.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:23:30.45$vck44/vblo=5,709.99 2006.257.18:23:30.45#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.18:23:30.45#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.18:23:30.45#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:30.45#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:30.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:30.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:30.45#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:23:30.45#ibcon#first serial, iclass 31, count 0 2006.257.18:23:30.45#ibcon#enter sib2, iclass 31, count 0 2006.257.18:23:30.45#ibcon#flushed, iclass 31, count 0 2006.257.18:23:30.45#ibcon#about to write, iclass 31, count 0 2006.257.18:23:30.45#ibcon#wrote, iclass 31, count 0 2006.257.18:23:30.45#ibcon#about to read 3, iclass 31, count 0 2006.257.18:23:30.47#ibcon#read 3, iclass 31, count 0 2006.257.18:23:30.47#ibcon#about to read 4, iclass 31, count 0 2006.257.18:23:30.47#ibcon#read 4, iclass 31, count 0 2006.257.18:23:30.47#ibcon#about to read 5, iclass 31, count 0 2006.257.18:23:30.47#ibcon#read 5, iclass 31, count 0 2006.257.18:23:30.47#ibcon#about to read 6, iclass 31, count 0 2006.257.18:23:30.47#ibcon#read 6, iclass 31, count 0 2006.257.18:23:30.47#ibcon#end of sib2, iclass 31, count 0 2006.257.18:23:30.47#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:23:30.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:23:30.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:23:30.47#ibcon#*before write, iclass 31, count 0 2006.257.18:23:30.47#ibcon#enter sib2, iclass 31, count 0 2006.257.18:23:30.47#ibcon#flushed, iclass 31, count 0 2006.257.18:23:30.47#ibcon#about to write, iclass 31, count 0 2006.257.18:23:30.47#ibcon#wrote, iclass 31, count 0 2006.257.18:23:30.47#ibcon#about to read 3, iclass 31, count 0 2006.257.18:23:30.51#ibcon#read 3, iclass 31, count 0 2006.257.18:23:30.51#ibcon#about to read 4, iclass 31, count 0 2006.257.18:23:30.51#ibcon#read 4, iclass 31, count 0 2006.257.18:23:30.51#ibcon#about to read 5, iclass 31, count 0 2006.257.18:23:30.51#ibcon#read 5, iclass 31, count 0 2006.257.18:23:30.51#ibcon#about to read 6, iclass 31, count 0 2006.257.18:23:30.51#ibcon#read 6, iclass 31, count 0 2006.257.18:23:30.51#ibcon#end of sib2, iclass 31, count 0 2006.257.18:23:30.51#ibcon#*after write, iclass 31, count 0 2006.257.18:23:30.51#ibcon#*before return 0, iclass 31, count 0 2006.257.18:23:30.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:30.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:23:30.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:23:30.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:23:30.51$vck44/vb=5,4 2006.257.18:23:30.51#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.18:23:30.51#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.18:23:30.51#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:30.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:30.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:30.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:30.57#ibcon#enter wrdev, iclass 33, count 2 2006.257.18:23:30.57#ibcon#first serial, iclass 33, count 2 2006.257.18:23:30.57#ibcon#enter sib2, iclass 33, count 2 2006.257.18:23:30.57#ibcon#flushed, iclass 33, count 2 2006.257.18:23:30.57#ibcon#about to write, iclass 33, count 2 2006.257.18:23:30.57#ibcon#wrote, iclass 33, count 2 2006.257.18:23:30.57#ibcon#about to read 3, iclass 33, count 2 2006.257.18:23:30.59#ibcon#read 3, iclass 33, count 2 2006.257.18:23:30.59#ibcon#about to read 4, iclass 33, count 2 2006.257.18:23:30.59#ibcon#read 4, iclass 33, count 2 2006.257.18:23:30.59#ibcon#about to read 5, iclass 33, count 2 2006.257.18:23:30.59#ibcon#read 5, iclass 33, count 2 2006.257.18:23:30.59#ibcon#about to read 6, iclass 33, count 2 2006.257.18:23:30.59#ibcon#read 6, iclass 33, count 2 2006.257.18:23:30.59#ibcon#end of sib2, iclass 33, count 2 2006.257.18:23:30.59#ibcon#*mode == 0, iclass 33, count 2 2006.257.18:23:30.59#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.18:23:30.59#ibcon#[27=AT05-04\r\n] 2006.257.18:23:30.59#ibcon#*before write, iclass 33, count 2 2006.257.18:23:30.59#ibcon#enter sib2, iclass 33, count 2 2006.257.18:23:30.59#ibcon#flushed, iclass 33, count 2 2006.257.18:23:30.59#ibcon#about to write, iclass 33, count 2 2006.257.18:23:30.59#ibcon#wrote, iclass 33, count 2 2006.257.18:23:30.59#ibcon#about to read 3, iclass 33, count 2 2006.257.18:23:30.62#ibcon#read 3, iclass 33, count 2 2006.257.18:23:30.62#ibcon#about to read 4, iclass 33, count 2 2006.257.18:23:30.62#ibcon#read 4, iclass 33, count 2 2006.257.18:23:30.62#ibcon#about to read 5, iclass 33, count 2 2006.257.18:23:30.62#ibcon#read 5, iclass 33, count 2 2006.257.18:23:30.62#ibcon#about to read 6, iclass 33, count 2 2006.257.18:23:30.62#ibcon#read 6, iclass 33, count 2 2006.257.18:23:30.62#ibcon#end of sib2, iclass 33, count 2 2006.257.18:23:30.62#ibcon#*after write, iclass 33, count 2 2006.257.18:23:30.62#ibcon#*before return 0, iclass 33, count 2 2006.257.18:23:30.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:30.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:23:30.62#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.18:23:30.62#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:30.62#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:30.74#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:30.74#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:30.74#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:23:30.74#ibcon#first serial, iclass 33, count 0 2006.257.18:23:30.74#ibcon#enter sib2, iclass 33, count 0 2006.257.18:23:30.74#ibcon#flushed, iclass 33, count 0 2006.257.18:23:30.74#ibcon#about to write, iclass 33, count 0 2006.257.18:23:30.74#ibcon#wrote, iclass 33, count 0 2006.257.18:23:30.74#ibcon#about to read 3, iclass 33, count 0 2006.257.18:23:30.76#ibcon#read 3, iclass 33, count 0 2006.257.18:23:30.76#ibcon#about to read 4, iclass 33, count 0 2006.257.18:23:30.76#ibcon#read 4, iclass 33, count 0 2006.257.18:23:30.76#ibcon#about to read 5, iclass 33, count 0 2006.257.18:23:30.76#ibcon#read 5, iclass 33, count 0 2006.257.18:23:30.76#ibcon#about to read 6, iclass 33, count 0 2006.257.18:23:30.76#ibcon#read 6, iclass 33, count 0 2006.257.18:23:30.76#ibcon#end of sib2, iclass 33, count 0 2006.257.18:23:30.76#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:23:30.76#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:23:30.76#ibcon#[27=USB\r\n] 2006.257.18:23:30.76#ibcon#*before write, iclass 33, count 0 2006.257.18:23:30.76#ibcon#enter sib2, iclass 33, count 0 2006.257.18:23:30.76#ibcon#flushed, iclass 33, count 0 2006.257.18:23:30.76#ibcon#about to write, iclass 33, count 0 2006.257.18:23:30.76#ibcon#wrote, iclass 33, count 0 2006.257.18:23:30.76#ibcon#about to read 3, iclass 33, count 0 2006.257.18:23:30.79#ibcon#read 3, iclass 33, count 0 2006.257.18:23:30.79#ibcon#about to read 4, iclass 33, count 0 2006.257.18:23:30.79#ibcon#read 4, iclass 33, count 0 2006.257.18:23:30.79#ibcon#about to read 5, iclass 33, count 0 2006.257.18:23:30.79#ibcon#read 5, iclass 33, count 0 2006.257.18:23:30.79#ibcon#about to read 6, iclass 33, count 0 2006.257.18:23:30.79#ibcon#read 6, iclass 33, count 0 2006.257.18:23:30.79#ibcon#end of sib2, iclass 33, count 0 2006.257.18:23:30.79#ibcon#*after write, iclass 33, count 0 2006.257.18:23:30.79#ibcon#*before return 0, iclass 33, count 0 2006.257.18:23:30.79#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:30.79#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:23:30.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:23:30.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:23:30.79$vck44/vblo=6,719.99 2006.257.18:23:30.79#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.18:23:30.79#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.18:23:30.79#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:30.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:30.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:30.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:30.79#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:23:30.79#ibcon#first serial, iclass 35, count 0 2006.257.18:23:30.79#ibcon#enter sib2, iclass 35, count 0 2006.257.18:23:30.79#ibcon#flushed, iclass 35, count 0 2006.257.18:23:30.79#ibcon#about to write, iclass 35, count 0 2006.257.18:23:30.79#ibcon#wrote, iclass 35, count 0 2006.257.18:23:30.79#ibcon#about to read 3, iclass 35, count 0 2006.257.18:23:30.81#ibcon#read 3, iclass 35, count 0 2006.257.18:23:30.81#ibcon#about to read 4, iclass 35, count 0 2006.257.18:23:30.81#ibcon#read 4, iclass 35, count 0 2006.257.18:23:30.81#ibcon#about to read 5, iclass 35, count 0 2006.257.18:23:30.81#ibcon#read 5, iclass 35, count 0 2006.257.18:23:30.81#ibcon#about to read 6, iclass 35, count 0 2006.257.18:23:30.81#ibcon#read 6, iclass 35, count 0 2006.257.18:23:30.81#ibcon#end of sib2, iclass 35, count 0 2006.257.18:23:30.81#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:23:30.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:23:30.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:23:30.81#ibcon#*before write, iclass 35, count 0 2006.257.18:23:30.81#ibcon#enter sib2, iclass 35, count 0 2006.257.18:23:30.81#ibcon#flushed, iclass 35, count 0 2006.257.18:23:30.81#ibcon#about to write, iclass 35, count 0 2006.257.18:23:30.81#ibcon#wrote, iclass 35, count 0 2006.257.18:23:30.81#ibcon#about to read 3, iclass 35, count 0 2006.257.18:23:30.85#ibcon#read 3, iclass 35, count 0 2006.257.18:23:30.85#ibcon#about to read 4, iclass 35, count 0 2006.257.18:23:30.85#ibcon#read 4, iclass 35, count 0 2006.257.18:23:30.85#ibcon#about to read 5, iclass 35, count 0 2006.257.18:23:30.85#ibcon#read 5, iclass 35, count 0 2006.257.18:23:30.85#ibcon#about to read 6, iclass 35, count 0 2006.257.18:23:30.85#ibcon#read 6, iclass 35, count 0 2006.257.18:23:30.85#ibcon#end of sib2, iclass 35, count 0 2006.257.18:23:30.85#ibcon#*after write, iclass 35, count 0 2006.257.18:23:30.85#ibcon#*before return 0, iclass 35, count 0 2006.257.18:23:30.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:30.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:23:30.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:23:30.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:23:30.85$vck44/vb=6,4 2006.257.18:23:30.85#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.18:23:30.85#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.18:23:30.85#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:30.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:30.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:30.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:30.91#ibcon#enter wrdev, iclass 37, count 2 2006.257.18:23:30.91#ibcon#first serial, iclass 37, count 2 2006.257.18:23:30.91#ibcon#enter sib2, iclass 37, count 2 2006.257.18:23:30.91#ibcon#flushed, iclass 37, count 2 2006.257.18:23:30.91#ibcon#about to write, iclass 37, count 2 2006.257.18:23:30.91#ibcon#wrote, iclass 37, count 2 2006.257.18:23:30.91#ibcon#about to read 3, iclass 37, count 2 2006.257.18:23:30.93#ibcon#read 3, iclass 37, count 2 2006.257.18:23:30.93#ibcon#about to read 4, iclass 37, count 2 2006.257.18:23:30.93#ibcon#read 4, iclass 37, count 2 2006.257.18:23:30.93#ibcon#about to read 5, iclass 37, count 2 2006.257.18:23:30.93#ibcon#read 5, iclass 37, count 2 2006.257.18:23:30.93#ibcon#about to read 6, iclass 37, count 2 2006.257.18:23:30.93#ibcon#read 6, iclass 37, count 2 2006.257.18:23:30.93#ibcon#end of sib2, iclass 37, count 2 2006.257.18:23:30.93#ibcon#*mode == 0, iclass 37, count 2 2006.257.18:23:30.93#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.18:23:30.93#ibcon#[27=AT06-04\r\n] 2006.257.18:23:30.93#ibcon#*before write, iclass 37, count 2 2006.257.18:23:30.93#ibcon#enter sib2, iclass 37, count 2 2006.257.18:23:30.93#ibcon#flushed, iclass 37, count 2 2006.257.18:23:30.93#ibcon#about to write, iclass 37, count 2 2006.257.18:23:30.93#ibcon#wrote, iclass 37, count 2 2006.257.18:23:30.93#ibcon#about to read 3, iclass 37, count 2 2006.257.18:23:30.96#ibcon#read 3, iclass 37, count 2 2006.257.18:23:30.96#ibcon#about to read 4, iclass 37, count 2 2006.257.18:23:30.96#ibcon#read 4, iclass 37, count 2 2006.257.18:23:30.96#ibcon#about to read 5, iclass 37, count 2 2006.257.18:23:30.96#ibcon#read 5, iclass 37, count 2 2006.257.18:23:30.96#ibcon#about to read 6, iclass 37, count 2 2006.257.18:23:30.96#ibcon#read 6, iclass 37, count 2 2006.257.18:23:30.96#ibcon#end of sib2, iclass 37, count 2 2006.257.18:23:30.96#ibcon#*after write, iclass 37, count 2 2006.257.18:23:30.96#ibcon#*before return 0, iclass 37, count 2 2006.257.18:23:30.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:30.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:23:30.96#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.18:23:30.96#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:30.96#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:31.08#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:31.08#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:31.08#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:23:31.08#ibcon#first serial, iclass 37, count 0 2006.257.18:23:31.08#ibcon#enter sib2, iclass 37, count 0 2006.257.18:23:31.08#ibcon#flushed, iclass 37, count 0 2006.257.18:23:31.08#ibcon#about to write, iclass 37, count 0 2006.257.18:23:31.08#ibcon#wrote, iclass 37, count 0 2006.257.18:23:31.08#ibcon#about to read 3, iclass 37, count 0 2006.257.18:23:31.10#ibcon#read 3, iclass 37, count 0 2006.257.18:23:31.10#ibcon#about to read 4, iclass 37, count 0 2006.257.18:23:31.10#ibcon#read 4, iclass 37, count 0 2006.257.18:23:31.10#ibcon#about to read 5, iclass 37, count 0 2006.257.18:23:31.10#ibcon#read 5, iclass 37, count 0 2006.257.18:23:31.10#ibcon#about to read 6, iclass 37, count 0 2006.257.18:23:31.10#ibcon#read 6, iclass 37, count 0 2006.257.18:23:31.10#ibcon#end of sib2, iclass 37, count 0 2006.257.18:23:31.10#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:23:31.10#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:23:31.10#ibcon#[27=USB\r\n] 2006.257.18:23:31.10#ibcon#*before write, iclass 37, count 0 2006.257.18:23:31.10#ibcon#enter sib2, iclass 37, count 0 2006.257.18:23:31.10#ibcon#flushed, iclass 37, count 0 2006.257.18:23:31.10#ibcon#about to write, iclass 37, count 0 2006.257.18:23:31.10#ibcon#wrote, iclass 37, count 0 2006.257.18:23:31.10#ibcon#about to read 3, iclass 37, count 0 2006.257.18:23:31.13#ibcon#read 3, iclass 37, count 0 2006.257.18:23:31.13#ibcon#about to read 4, iclass 37, count 0 2006.257.18:23:31.13#ibcon#read 4, iclass 37, count 0 2006.257.18:23:31.13#ibcon#about to read 5, iclass 37, count 0 2006.257.18:23:31.13#ibcon#read 5, iclass 37, count 0 2006.257.18:23:31.13#ibcon#about to read 6, iclass 37, count 0 2006.257.18:23:31.13#ibcon#read 6, iclass 37, count 0 2006.257.18:23:31.13#ibcon#end of sib2, iclass 37, count 0 2006.257.18:23:31.13#ibcon#*after write, iclass 37, count 0 2006.257.18:23:31.13#ibcon#*before return 0, iclass 37, count 0 2006.257.18:23:31.13#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:31.13#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:23:31.13#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:23:31.13#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:23:31.13$vck44/vblo=7,734.99 2006.257.18:23:31.13#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.18:23:31.13#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.18:23:31.13#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:31.13#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:31.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:31.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:31.13#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:23:31.13#ibcon#first serial, iclass 39, count 0 2006.257.18:23:31.13#ibcon#enter sib2, iclass 39, count 0 2006.257.18:23:31.13#ibcon#flushed, iclass 39, count 0 2006.257.18:23:31.13#ibcon#about to write, iclass 39, count 0 2006.257.18:23:31.13#ibcon#wrote, iclass 39, count 0 2006.257.18:23:31.13#ibcon#about to read 3, iclass 39, count 0 2006.257.18:23:31.15#ibcon#read 3, iclass 39, count 0 2006.257.18:23:31.15#ibcon#about to read 4, iclass 39, count 0 2006.257.18:23:31.15#ibcon#read 4, iclass 39, count 0 2006.257.18:23:31.15#ibcon#about to read 5, iclass 39, count 0 2006.257.18:23:31.15#ibcon#read 5, iclass 39, count 0 2006.257.18:23:31.15#ibcon#about to read 6, iclass 39, count 0 2006.257.18:23:31.15#ibcon#read 6, iclass 39, count 0 2006.257.18:23:31.15#ibcon#end of sib2, iclass 39, count 0 2006.257.18:23:31.15#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:23:31.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:23:31.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:23:31.15#ibcon#*before write, iclass 39, count 0 2006.257.18:23:31.15#ibcon#enter sib2, iclass 39, count 0 2006.257.18:23:31.15#ibcon#flushed, iclass 39, count 0 2006.257.18:23:31.15#ibcon#about to write, iclass 39, count 0 2006.257.18:23:31.15#ibcon#wrote, iclass 39, count 0 2006.257.18:23:31.15#ibcon#about to read 3, iclass 39, count 0 2006.257.18:23:31.19#ibcon#read 3, iclass 39, count 0 2006.257.18:23:31.19#ibcon#about to read 4, iclass 39, count 0 2006.257.18:23:31.19#ibcon#read 4, iclass 39, count 0 2006.257.18:23:31.19#ibcon#about to read 5, iclass 39, count 0 2006.257.18:23:31.19#ibcon#read 5, iclass 39, count 0 2006.257.18:23:31.19#ibcon#about to read 6, iclass 39, count 0 2006.257.18:23:31.19#ibcon#read 6, iclass 39, count 0 2006.257.18:23:31.19#ibcon#end of sib2, iclass 39, count 0 2006.257.18:23:31.19#ibcon#*after write, iclass 39, count 0 2006.257.18:23:31.19#ibcon#*before return 0, iclass 39, count 0 2006.257.18:23:31.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:31.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:23:31.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:23:31.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:23:31.19$vck44/vb=7,4 2006.257.18:23:31.19#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.18:23:31.19#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.18:23:31.19#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:31.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:31.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:31.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:31.25#ibcon#enter wrdev, iclass 3, count 2 2006.257.18:23:31.25#ibcon#first serial, iclass 3, count 2 2006.257.18:23:31.25#ibcon#enter sib2, iclass 3, count 2 2006.257.18:23:31.25#ibcon#flushed, iclass 3, count 2 2006.257.18:23:31.25#ibcon#about to write, iclass 3, count 2 2006.257.18:23:31.25#ibcon#wrote, iclass 3, count 2 2006.257.18:23:31.25#ibcon#about to read 3, iclass 3, count 2 2006.257.18:23:31.27#ibcon#read 3, iclass 3, count 2 2006.257.18:23:31.27#ibcon#about to read 4, iclass 3, count 2 2006.257.18:23:31.27#ibcon#read 4, iclass 3, count 2 2006.257.18:23:31.27#ibcon#about to read 5, iclass 3, count 2 2006.257.18:23:31.27#ibcon#read 5, iclass 3, count 2 2006.257.18:23:31.27#ibcon#about to read 6, iclass 3, count 2 2006.257.18:23:31.27#ibcon#read 6, iclass 3, count 2 2006.257.18:23:31.27#ibcon#end of sib2, iclass 3, count 2 2006.257.18:23:31.27#ibcon#*mode == 0, iclass 3, count 2 2006.257.18:23:31.27#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.18:23:31.27#ibcon#[27=AT07-04\r\n] 2006.257.18:23:31.27#ibcon#*before write, iclass 3, count 2 2006.257.18:23:31.27#ibcon#enter sib2, iclass 3, count 2 2006.257.18:23:31.27#ibcon#flushed, iclass 3, count 2 2006.257.18:23:31.27#ibcon#about to write, iclass 3, count 2 2006.257.18:23:31.27#ibcon#wrote, iclass 3, count 2 2006.257.18:23:31.27#ibcon#about to read 3, iclass 3, count 2 2006.257.18:23:31.30#ibcon#read 3, iclass 3, count 2 2006.257.18:23:31.30#ibcon#about to read 4, iclass 3, count 2 2006.257.18:23:31.30#ibcon#read 4, iclass 3, count 2 2006.257.18:23:31.30#ibcon#about to read 5, iclass 3, count 2 2006.257.18:23:31.30#ibcon#read 5, iclass 3, count 2 2006.257.18:23:31.30#ibcon#about to read 6, iclass 3, count 2 2006.257.18:23:31.30#ibcon#read 6, iclass 3, count 2 2006.257.18:23:31.30#ibcon#end of sib2, iclass 3, count 2 2006.257.18:23:31.30#ibcon#*after write, iclass 3, count 2 2006.257.18:23:31.30#ibcon#*before return 0, iclass 3, count 2 2006.257.18:23:31.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:31.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:23:31.30#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.18:23:31.30#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:31.30#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:31.42#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:31.42#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:31.42#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:23:31.42#ibcon#first serial, iclass 3, count 0 2006.257.18:23:31.42#ibcon#enter sib2, iclass 3, count 0 2006.257.18:23:31.42#ibcon#flushed, iclass 3, count 0 2006.257.18:23:31.42#ibcon#about to write, iclass 3, count 0 2006.257.18:23:31.42#ibcon#wrote, iclass 3, count 0 2006.257.18:23:31.42#ibcon#about to read 3, iclass 3, count 0 2006.257.18:23:31.43#abcon#<5=/14 1.3 3.0 17.29 971014.3\r\n> 2006.257.18:23:31.44#ibcon#read 3, iclass 3, count 0 2006.257.18:23:31.44#ibcon#about to read 4, iclass 3, count 0 2006.257.18:23:31.44#ibcon#read 4, iclass 3, count 0 2006.257.18:23:31.44#ibcon#about to read 5, iclass 3, count 0 2006.257.18:23:31.44#ibcon#read 5, iclass 3, count 0 2006.257.18:23:31.44#ibcon#about to read 6, iclass 3, count 0 2006.257.18:23:31.44#ibcon#read 6, iclass 3, count 0 2006.257.18:23:31.44#ibcon#end of sib2, iclass 3, count 0 2006.257.18:23:31.44#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:23:31.44#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:23:31.44#ibcon#[27=USB\r\n] 2006.257.18:23:31.44#ibcon#*before write, iclass 3, count 0 2006.257.18:23:31.44#ibcon#enter sib2, iclass 3, count 0 2006.257.18:23:31.44#ibcon#flushed, iclass 3, count 0 2006.257.18:23:31.44#ibcon#about to write, iclass 3, count 0 2006.257.18:23:31.44#ibcon#wrote, iclass 3, count 0 2006.257.18:23:31.44#ibcon#about to read 3, iclass 3, count 0 2006.257.18:23:31.45#abcon#{5=INTERFACE CLEAR} 2006.257.18:23:31.47#ibcon#read 3, iclass 3, count 0 2006.257.18:23:31.47#ibcon#about to read 4, iclass 3, count 0 2006.257.18:23:31.47#ibcon#read 4, iclass 3, count 0 2006.257.18:23:31.47#ibcon#about to read 5, iclass 3, count 0 2006.257.18:23:31.47#ibcon#read 5, iclass 3, count 0 2006.257.18:23:31.47#ibcon#about to read 6, iclass 3, count 0 2006.257.18:23:31.47#ibcon#read 6, iclass 3, count 0 2006.257.18:23:31.47#ibcon#end of sib2, iclass 3, count 0 2006.257.18:23:31.47#ibcon#*after write, iclass 3, count 0 2006.257.18:23:31.47#ibcon#*before return 0, iclass 3, count 0 2006.257.18:23:31.47#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:31.47#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:23:31.47#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:23:31.47#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:23:31.47$vck44/vblo=8,744.99 2006.257.18:23:31.47#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.18:23:31.47#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.18:23:31.47#ibcon#ireg 17 cls_cnt 0 2006.257.18:23:31.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:23:31.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:23:31.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:23:31.47#ibcon#enter wrdev, iclass 10, count 0 2006.257.18:23:31.47#ibcon#first serial, iclass 10, count 0 2006.257.18:23:31.47#ibcon#enter sib2, iclass 10, count 0 2006.257.18:23:31.47#ibcon#flushed, iclass 10, count 0 2006.257.18:23:31.47#ibcon#about to write, iclass 10, count 0 2006.257.18:23:31.47#ibcon#wrote, iclass 10, count 0 2006.257.18:23:31.47#ibcon#about to read 3, iclass 10, count 0 2006.257.18:23:31.49#ibcon#read 3, iclass 10, count 0 2006.257.18:23:31.49#ibcon#about to read 4, iclass 10, count 0 2006.257.18:23:31.49#ibcon#read 4, iclass 10, count 0 2006.257.18:23:31.49#ibcon#about to read 5, iclass 10, count 0 2006.257.18:23:31.49#ibcon#read 5, iclass 10, count 0 2006.257.18:23:31.49#ibcon#about to read 6, iclass 10, count 0 2006.257.18:23:31.49#ibcon#read 6, iclass 10, count 0 2006.257.18:23:31.49#ibcon#end of sib2, iclass 10, count 0 2006.257.18:23:31.49#ibcon#*mode == 0, iclass 10, count 0 2006.257.18:23:31.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.18:23:31.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:23:31.49#ibcon#*before write, iclass 10, count 0 2006.257.18:23:31.49#ibcon#enter sib2, iclass 10, count 0 2006.257.18:23:31.49#ibcon#flushed, iclass 10, count 0 2006.257.18:23:31.49#ibcon#about to write, iclass 10, count 0 2006.257.18:23:31.49#ibcon#wrote, iclass 10, count 0 2006.257.18:23:31.49#ibcon#about to read 3, iclass 10, count 0 2006.257.18:23:31.51#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:23:31.53#ibcon#read 3, iclass 10, count 0 2006.257.18:23:31.53#ibcon#about to read 4, iclass 10, count 0 2006.257.18:23:31.53#ibcon#read 4, iclass 10, count 0 2006.257.18:23:31.53#ibcon#about to read 5, iclass 10, count 0 2006.257.18:23:31.53#ibcon#read 5, iclass 10, count 0 2006.257.18:23:31.53#ibcon#about to read 6, iclass 10, count 0 2006.257.18:23:31.53#ibcon#read 6, iclass 10, count 0 2006.257.18:23:31.53#ibcon#end of sib2, iclass 10, count 0 2006.257.18:23:31.53#ibcon#*after write, iclass 10, count 0 2006.257.18:23:31.53#ibcon#*before return 0, iclass 10, count 0 2006.257.18:23:31.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:23:31.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:23:31.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.18:23:31.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.18:23:31.53$vck44/vb=8,4 2006.257.18:23:31.53#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.18:23:31.53#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.18:23:31.53#ibcon#ireg 11 cls_cnt 2 2006.257.18:23:31.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:31.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:31.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:31.59#ibcon#enter wrdev, iclass 13, count 2 2006.257.18:23:31.59#ibcon#first serial, iclass 13, count 2 2006.257.18:23:31.59#ibcon#enter sib2, iclass 13, count 2 2006.257.18:23:31.59#ibcon#flushed, iclass 13, count 2 2006.257.18:23:31.59#ibcon#about to write, iclass 13, count 2 2006.257.18:23:31.59#ibcon#wrote, iclass 13, count 2 2006.257.18:23:31.59#ibcon#about to read 3, iclass 13, count 2 2006.257.18:23:31.61#ibcon#read 3, iclass 13, count 2 2006.257.18:23:31.61#ibcon#about to read 4, iclass 13, count 2 2006.257.18:23:31.61#ibcon#read 4, iclass 13, count 2 2006.257.18:23:31.61#ibcon#about to read 5, iclass 13, count 2 2006.257.18:23:31.61#ibcon#read 5, iclass 13, count 2 2006.257.18:23:31.61#ibcon#about to read 6, iclass 13, count 2 2006.257.18:23:31.61#ibcon#read 6, iclass 13, count 2 2006.257.18:23:31.61#ibcon#end of sib2, iclass 13, count 2 2006.257.18:23:31.61#ibcon#*mode == 0, iclass 13, count 2 2006.257.18:23:31.61#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.18:23:31.61#ibcon#[27=AT08-04\r\n] 2006.257.18:23:31.61#ibcon#*before write, iclass 13, count 2 2006.257.18:23:31.61#ibcon#enter sib2, iclass 13, count 2 2006.257.18:23:31.61#ibcon#flushed, iclass 13, count 2 2006.257.18:23:31.61#ibcon#about to write, iclass 13, count 2 2006.257.18:23:31.61#ibcon#wrote, iclass 13, count 2 2006.257.18:23:31.61#ibcon#about to read 3, iclass 13, count 2 2006.257.18:23:31.64#ibcon#read 3, iclass 13, count 2 2006.257.18:23:31.64#ibcon#about to read 4, iclass 13, count 2 2006.257.18:23:31.64#ibcon#read 4, iclass 13, count 2 2006.257.18:23:31.64#ibcon#about to read 5, iclass 13, count 2 2006.257.18:23:31.64#ibcon#read 5, iclass 13, count 2 2006.257.18:23:31.64#ibcon#about to read 6, iclass 13, count 2 2006.257.18:23:31.64#ibcon#read 6, iclass 13, count 2 2006.257.18:23:31.64#ibcon#end of sib2, iclass 13, count 2 2006.257.18:23:31.64#ibcon#*after write, iclass 13, count 2 2006.257.18:23:31.64#ibcon#*before return 0, iclass 13, count 2 2006.257.18:23:31.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:31.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:23:31.64#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.18:23:31.64#ibcon#ireg 7 cls_cnt 0 2006.257.18:23:31.64#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:31.76#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:31.76#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:31.76#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:23:31.76#ibcon#first serial, iclass 13, count 0 2006.257.18:23:31.76#ibcon#enter sib2, iclass 13, count 0 2006.257.18:23:31.76#ibcon#flushed, iclass 13, count 0 2006.257.18:23:31.76#ibcon#about to write, iclass 13, count 0 2006.257.18:23:31.76#ibcon#wrote, iclass 13, count 0 2006.257.18:23:31.76#ibcon#about to read 3, iclass 13, count 0 2006.257.18:23:31.78#ibcon#read 3, iclass 13, count 0 2006.257.18:23:31.78#ibcon#about to read 4, iclass 13, count 0 2006.257.18:23:31.78#ibcon#read 4, iclass 13, count 0 2006.257.18:23:31.78#ibcon#about to read 5, iclass 13, count 0 2006.257.18:23:31.78#ibcon#read 5, iclass 13, count 0 2006.257.18:23:31.78#ibcon#about to read 6, iclass 13, count 0 2006.257.18:23:31.78#ibcon#read 6, iclass 13, count 0 2006.257.18:23:31.78#ibcon#end of sib2, iclass 13, count 0 2006.257.18:23:31.78#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:23:31.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:23:31.78#ibcon#[27=USB\r\n] 2006.257.18:23:31.78#ibcon#*before write, iclass 13, count 0 2006.257.18:23:31.78#ibcon#enter sib2, iclass 13, count 0 2006.257.18:23:31.78#ibcon#flushed, iclass 13, count 0 2006.257.18:23:31.78#ibcon#about to write, iclass 13, count 0 2006.257.18:23:31.78#ibcon#wrote, iclass 13, count 0 2006.257.18:23:31.78#ibcon#about to read 3, iclass 13, count 0 2006.257.18:23:31.81#ibcon#read 3, iclass 13, count 0 2006.257.18:23:31.81#ibcon#about to read 4, iclass 13, count 0 2006.257.18:23:31.81#ibcon#read 4, iclass 13, count 0 2006.257.18:23:31.81#ibcon#about to read 5, iclass 13, count 0 2006.257.18:23:31.81#ibcon#read 5, iclass 13, count 0 2006.257.18:23:31.81#ibcon#about to read 6, iclass 13, count 0 2006.257.18:23:31.81#ibcon#read 6, iclass 13, count 0 2006.257.18:23:31.81#ibcon#end of sib2, iclass 13, count 0 2006.257.18:23:31.81#ibcon#*after write, iclass 13, count 0 2006.257.18:23:31.81#ibcon#*before return 0, iclass 13, count 0 2006.257.18:23:31.81#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:31.81#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:23:31.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:23:31.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:23:31.81$vck44/vabw=wide 2006.257.18:23:31.81#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.18:23:31.81#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.18:23:31.81#ibcon#ireg 8 cls_cnt 0 2006.257.18:23:31.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:31.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:31.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:31.81#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:23:31.81#ibcon#first serial, iclass 15, count 0 2006.257.18:23:31.81#ibcon#enter sib2, iclass 15, count 0 2006.257.18:23:31.81#ibcon#flushed, iclass 15, count 0 2006.257.18:23:31.81#ibcon#about to write, iclass 15, count 0 2006.257.18:23:31.81#ibcon#wrote, iclass 15, count 0 2006.257.18:23:31.81#ibcon#about to read 3, iclass 15, count 0 2006.257.18:23:31.83#ibcon#read 3, iclass 15, count 0 2006.257.18:23:31.83#ibcon#about to read 4, iclass 15, count 0 2006.257.18:23:31.83#ibcon#read 4, iclass 15, count 0 2006.257.18:23:31.83#ibcon#about to read 5, iclass 15, count 0 2006.257.18:23:31.83#ibcon#read 5, iclass 15, count 0 2006.257.18:23:31.83#ibcon#about to read 6, iclass 15, count 0 2006.257.18:23:31.83#ibcon#read 6, iclass 15, count 0 2006.257.18:23:31.83#ibcon#end of sib2, iclass 15, count 0 2006.257.18:23:31.83#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:23:31.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:23:31.83#ibcon#[25=BW32\r\n] 2006.257.18:23:31.83#ibcon#*before write, iclass 15, count 0 2006.257.18:23:31.83#ibcon#enter sib2, iclass 15, count 0 2006.257.18:23:31.83#ibcon#flushed, iclass 15, count 0 2006.257.18:23:31.83#ibcon#about to write, iclass 15, count 0 2006.257.18:23:31.83#ibcon#wrote, iclass 15, count 0 2006.257.18:23:31.83#ibcon#about to read 3, iclass 15, count 0 2006.257.18:23:31.86#ibcon#read 3, iclass 15, count 0 2006.257.18:23:31.86#ibcon#about to read 4, iclass 15, count 0 2006.257.18:23:31.86#ibcon#read 4, iclass 15, count 0 2006.257.18:23:31.86#ibcon#about to read 5, iclass 15, count 0 2006.257.18:23:31.86#ibcon#read 5, iclass 15, count 0 2006.257.18:23:31.86#ibcon#about to read 6, iclass 15, count 0 2006.257.18:23:31.86#ibcon#read 6, iclass 15, count 0 2006.257.18:23:31.86#ibcon#end of sib2, iclass 15, count 0 2006.257.18:23:31.86#ibcon#*after write, iclass 15, count 0 2006.257.18:23:31.86#ibcon#*before return 0, iclass 15, count 0 2006.257.18:23:31.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:31.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:23:31.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:23:31.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:23:31.86$vck44/vbbw=wide 2006.257.18:23:31.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.18:23:31.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.18:23:31.86#ibcon#ireg 8 cls_cnt 0 2006.257.18:23:31.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:23:31.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:23:31.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:23:31.93#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:23:31.93#ibcon#first serial, iclass 17, count 0 2006.257.18:23:31.93#ibcon#enter sib2, iclass 17, count 0 2006.257.18:23:31.93#ibcon#flushed, iclass 17, count 0 2006.257.18:23:31.93#ibcon#about to write, iclass 17, count 0 2006.257.18:23:31.93#ibcon#wrote, iclass 17, count 0 2006.257.18:23:31.93#ibcon#about to read 3, iclass 17, count 0 2006.257.18:23:31.95#ibcon#read 3, iclass 17, count 0 2006.257.18:23:31.95#ibcon#about to read 4, iclass 17, count 0 2006.257.18:23:31.95#ibcon#read 4, iclass 17, count 0 2006.257.18:23:31.95#ibcon#about to read 5, iclass 17, count 0 2006.257.18:23:31.95#ibcon#read 5, iclass 17, count 0 2006.257.18:23:31.95#ibcon#about to read 6, iclass 17, count 0 2006.257.18:23:31.95#ibcon#read 6, iclass 17, count 0 2006.257.18:23:31.95#ibcon#end of sib2, iclass 17, count 0 2006.257.18:23:31.95#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:23:31.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:23:31.95#ibcon#[27=BW32\r\n] 2006.257.18:23:31.95#ibcon#*before write, iclass 17, count 0 2006.257.18:23:31.95#ibcon#enter sib2, iclass 17, count 0 2006.257.18:23:31.95#ibcon#flushed, iclass 17, count 0 2006.257.18:23:31.95#ibcon#about to write, iclass 17, count 0 2006.257.18:23:31.95#ibcon#wrote, iclass 17, count 0 2006.257.18:23:31.95#ibcon#about to read 3, iclass 17, count 0 2006.257.18:23:31.98#ibcon#read 3, iclass 17, count 0 2006.257.18:23:31.98#ibcon#about to read 4, iclass 17, count 0 2006.257.18:23:31.98#ibcon#read 4, iclass 17, count 0 2006.257.18:23:31.98#ibcon#about to read 5, iclass 17, count 0 2006.257.18:23:31.98#ibcon#read 5, iclass 17, count 0 2006.257.18:23:31.98#ibcon#about to read 6, iclass 17, count 0 2006.257.18:23:31.98#ibcon#read 6, iclass 17, count 0 2006.257.18:23:31.98#ibcon#end of sib2, iclass 17, count 0 2006.257.18:23:31.98#ibcon#*after write, iclass 17, count 0 2006.257.18:23:31.98#ibcon#*before return 0, iclass 17, count 0 2006.257.18:23:31.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:23:31.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:23:31.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:23:31.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:23:31.98$setupk4/ifdk4 2006.257.18:23:31.98$ifdk4/lo= 2006.257.18:23:31.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:23:31.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:23:31.98$ifdk4/patch= 2006.257.18:23:31.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:23:31.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:23:31.98$setupk4/!*+20s 2006.257.18:23:36.14#trakl#Source acquired 2006.257.18:23:37.14#flagr#flagr/antenna,acquired 2006.257.18:23:41.60#abcon#<5=/14 1.3 3.0 17.29 971014.3\r\n> 2006.257.18:23:41.62#abcon#{5=INTERFACE CLEAR} 2006.257.18:23:41.68#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:23:46.49$setupk4/"tpicd 2006.257.18:23:46.49$setupk4/echo=off 2006.257.18:23:46.49$setupk4/xlog=off 2006.257.18:23:46.49:!2006.257.18:29:43 2006.257.18:29:43.00:preob 2006.257.18:29:44.14/onsource/TRACKING 2006.257.18:29:44.14:!2006.257.18:29:53 2006.257.18:29:53.00:"tape 2006.257.18:29:53.00:"st=record 2006.257.18:29:53.00:data_valid=on 2006.257.18:29:53.00:midob 2006.257.18:29:53.14/onsource/TRACKING 2006.257.18:29:53.14/wx/17.29,1014.3,97 2006.257.18:29:53.35/cable/+6.4850E-03 2006.257.18:29:54.44/va/01,08,usb,yes,33,35 2006.257.18:29:54.44/va/02,07,usb,yes,35,36 2006.257.18:29:54.44/va/03,08,usb,yes,32,34 2006.257.18:29:54.44/va/04,07,usb,yes,36,38 2006.257.18:29:54.44/va/05,04,usb,yes,33,33 2006.257.18:29:54.44/va/06,04,usb,yes,36,36 2006.257.18:29:54.44/va/07,04,usb,yes,37,37 2006.257.18:29:54.44/va/08,04,usb,yes,31,38 2006.257.18:29:54.67/valo/01,524.99,yes,locked 2006.257.18:29:54.67/valo/02,534.99,yes,locked 2006.257.18:29:54.67/valo/03,564.99,yes,locked 2006.257.18:29:54.67/valo/04,624.99,yes,locked 2006.257.18:29:54.67/valo/05,734.99,yes,locked 2006.257.18:29:54.67/valo/06,814.99,yes,locked 2006.257.18:29:54.67/valo/07,864.99,yes,locked 2006.257.18:29:54.67/valo/08,884.99,yes,locked 2006.257.18:29:55.76/vb/01,04,usb,yes,31,29 2006.257.18:29:55.76/vb/02,05,usb,yes,29,29 2006.257.18:29:55.76/vb/03,04,usb,yes,30,33 2006.257.18:29:55.76/vb/04,05,usb,yes,31,30 2006.257.18:29:55.76/vb/05,04,usb,yes,27,30 2006.257.18:29:55.76/vb/06,04,usb,yes,32,28 2006.257.18:29:55.76/vb/07,04,usb,yes,31,31 2006.257.18:29:55.76/vb/08,04,usb,yes,29,32 2006.257.18:29:55.99/vblo/01,629.99,yes,locked 2006.257.18:29:55.99/vblo/02,634.99,yes,locked 2006.257.18:29:55.99/vblo/03,649.99,yes,locked 2006.257.18:29:55.99/vblo/04,679.99,yes,locked 2006.257.18:29:55.99/vblo/05,709.99,yes,locked 2006.257.18:29:55.99/vblo/06,719.99,yes,locked 2006.257.18:29:55.99/vblo/07,734.99,yes,locked 2006.257.18:29:55.99/vblo/08,744.99,yes,locked 2006.257.18:29:56.14/vabw/8 2006.257.18:29:56.29/vbbw/8 2006.257.18:29:56.38/xfe/off,on,15.0 2006.257.18:29:56.75/ifatt/23,28,28,28 2006.257.18:29:57.07/fmout-gps/S +4.54E-07 2006.257.18:29:57.11:!2006.257.18:33:03 2006.257.18:33:03.01:data_valid=off 2006.257.18:33:03.01:"et 2006.257.18:33:03.01:!+3s 2006.257.18:33:06.02:"tape 2006.257.18:33:06.02:postob 2006.257.18:33:06.08/cable/+6.4856E-03 2006.257.18:33:06.08/wx/17.29,1014.3,97 2006.257.18:33:07.08/fmout-gps/S +4.53E-07 2006.257.18:33:07.08:scan_name=257-1840,jd0609,70 2006.257.18:33:07.08:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.257.18:33:08.14#flagr#flagr/antenna,new-source 2006.257.18:33:08.14:checkk5 2006.257.18:33:08.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:33:08.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:33:09.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:33:09.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:33:09.84/chk_obsdata//k5ts1/T2571829??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.257.18:33:10.18/chk_obsdata//k5ts2/T2571829??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.257.18:33:10.51/chk_obsdata//k5ts3/T2571829??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.257.18:33:10.85/chk_obsdata//k5ts4/T2571829??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.257.18:33:11.51/k5log//k5ts1_log_newline 2006.257.18:33:12.17/k5log//k5ts2_log_newline 2006.257.18:33:12.87/k5log//k5ts3_log_newline 2006.257.18:33:13.53/k5log//k5ts4_log_newline 2006.257.18:33:13.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:33:13.55:setupk4=1 2006.257.18:33:13.55$setupk4/echo=on 2006.257.18:33:13.55$setupk4/pcalon 2006.257.18:33:13.55$pcalon/"no phase cal control is implemented here 2006.257.18:33:13.55$setupk4/"tpicd=stop 2006.257.18:33:13.55$setupk4/"rec=synch_on 2006.257.18:33:13.55$setupk4/"rec_mode=128 2006.257.18:33:13.55$setupk4/!* 2006.257.18:33:13.55$setupk4/recpk4 2006.257.18:33:13.55$recpk4/recpatch= 2006.257.18:33:13.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:33:13.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:33:13.55$setupk4/vck44 2006.257.18:33:13.55$vck44/valo=1,524.99 2006.257.18:33:13.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.18:33:13.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.18:33:13.55#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:13.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:13.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:13.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:13.55#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:33:13.55#ibcon#first serial, iclass 25, count 0 2006.257.18:33:13.55#ibcon#enter sib2, iclass 25, count 0 2006.257.18:33:13.55#ibcon#flushed, iclass 25, count 0 2006.257.18:33:13.55#ibcon#about to write, iclass 25, count 0 2006.257.18:33:13.55#ibcon#wrote, iclass 25, count 0 2006.257.18:33:13.55#ibcon#about to read 3, iclass 25, count 0 2006.257.18:33:13.57#ibcon#read 3, iclass 25, count 0 2006.257.18:33:13.57#ibcon#about to read 4, iclass 25, count 0 2006.257.18:33:13.57#ibcon#read 4, iclass 25, count 0 2006.257.18:33:13.57#ibcon#about to read 5, iclass 25, count 0 2006.257.18:33:13.57#ibcon#read 5, iclass 25, count 0 2006.257.18:33:13.57#ibcon#about to read 6, iclass 25, count 0 2006.257.18:33:13.57#ibcon#read 6, iclass 25, count 0 2006.257.18:33:13.57#ibcon#end of sib2, iclass 25, count 0 2006.257.18:33:13.57#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:33:13.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:33:13.57#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:33:13.57#ibcon#*before write, iclass 25, count 0 2006.257.18:33:13.57#ibcon#enter sib2, iclass 25, count 0 2006.257.18:33:13.57#ibcon#flushed, iclass 25, count 0 2006.257.18:33:13.57#ibcon#about to write, iclass 25, count 0 2006.257.18:33:13.57#ibcon#wrote, iclass 25, count 0 2006.257.18:33:13.57#ibcon#about to read 3, iclass 25, count 0 2006.257.18:33:13.62#ibcon#read 3, iclass 25, count 0 2006.257.18:33:13.62#ibcon#about to read 4, iclass 25, count 0 2006.257.18:33:13.62#ibcon#read 4, iclass 25, count 0 2006.257.18:33:13.62#ibcon#about to read 5, iclass 25, count 0 2006.257.18:33:13.62#ibcon#read 5, iclass 25, count 0 2006.257.18:33:13.62#ibcon#about to read 6, iclass 25, count 0 2006.257.18:33:13.62#ibcon#read 6, iclass 25, count 0 2006.257.18:33:13.62#ibcon#end of sib2, iclass 25, count 0 2006.257.18:33:13.62#ibcon#*after write, iclass 25, count 0 2006.257.18:33:13.62#ibcon#*before return 0, iclass 25, count 0 2006.257.18:33:13.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:13.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:13.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:33:13.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:33:13.62$vck44/va=1,8 2006.257.18:33:13.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.18:33:13.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.18:33:13.62#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:13.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:13.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:13.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:13.62#ibcon#enter wrdev, iclass 27, count 2 2006.257.18:33:13.62#ibcon#first serial, iclass 27, count 2 2006.257.18:33:13.62#ibcon#enter sib2, iclass 27, count 2 2006.257.18:33:13.62#ibcon#flushed, iclass 27, count 2 2006.257.18:33:13.62#ibcon#about to write, iclass 27, count 2 2006.257.18:33:13.62#ibcon#wrote, iclass 27, count 2 2006.257.18:33:13.62#ibcon#about to read 3, iclass 27, count 2 2006.257.18:33:13.64#ibcon#read 3, iclass 27, count 2 2006.257.18:33:13.64#ibcon#about to read 4, iclass 27, count 2 2006.257.18:33:13.64#ibcon#read 4, iclass 27, count 2 2006.257.18:33:13.64#ibcon#about to read 5, iclass 27, count 2 2006.257.18:33:13.64#ibcon#read 5, iclass 27, count 2 2006.257.18:33:13.64#ibcon#about to read 6, iclass 27, count 2 2006.257.18:33:13.64#ibcon#read 6, iclass 27, count 2 2006.257.18:33:13.64#ibcon#end of sib2, iclass 27, count 2 2006.257.18:33:13.64#ibcon#*mode == 0, iclass 27, count 2 2006.257.18:33:13.64#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.18:33:13.64#ibcon#[25=AT01-08\r\n] 2006.257.18:33:13.64#ibcon#*before write, iclass 27, count 2 2006.257.18:33:13.64#ibcon#enter sib2, iclass 27, count 2 2006.257.18:33:13.64#ibcon#flushed, iclass 27, count 2 2006.257.18:33:13.64#ibcon#about to write, iclass 27, count 2 2006.257.18:33:13.64#ibcon#wrote, iclass 27, count 2 2006.257.18:33:13.64#ibcon#about to read 3, iclass 27, count 2 2006.257.18:33:13.67#ibcon#read 3, iclass 27, count 2 2006.257.18:33:13.67#ibcon#about to read 4, iclass 27, count 2 2006.257.18:33:13.67#ibcon#read 4, iclass 27, count 2 2006.257.18:33:13.67#ibcon#about to read 5, iclass 27, count 2 2006.257.18:33:13.67#ibcon#read 5, iclass 27, count 2 2006.257.18:33:13.67#ibcon#about to read 6, iclass 27, count 2 2006.257.18:33:13.67#ibcon#read 6, iclass 27, count 2 2006.257.18:33:13.67#ibcon#end of sib2, iclass 27, count 2 2006.257.18:33:13.67#ibcon#*after write, iclass 27, count 2 2006.257.18:33:13.67#ibcon#*before return 0, iclass 27, count 2 2006.257.18:33:13.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:13.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:13.67#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.18:33:13.67#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:13.67#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:13.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:13.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:13.79#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:33:13.79#ibcon#first serial, iclass 27, count 0 2006.257.18:33:13.79#ibcon#enter sib2, iclass 27, count 0 2006.257.18:33:13.79#ibcon#flushed, iclass 27, count 0 2006.257.18:33:13.79#ibcon#about to write, iclass 27, count 0 2006.257.18:33:13.79#ibcon#wrote, iclass 27, count 0 2006.257.18:33:13.79#ibcon#about to read 3, iclass 27, count 0 2006.257.18:33:13.81#ibcon#read 3, iclass 27, count 0 2006.257.18:33:13.81#ibcon#about to read 4, iclass 27, count 0 2006.257.18:33:13.81#ibcon#read 4, iclass 27, count 0 2006.257.18:33:13.81#ibcon#about to read 5, iclass 27, count 0 2006.257.18:33:13.81#ibcon#read 5, iclass 27, count 0 2006.257.18:33:13.81#ibcon#about to read 6, iclass 27, count 0 2006.257.18:33:13.81#ibcon#read 6, iclass 27, count 0 2006.257.18:33:13.81#ibcon#end of sib2, iclass 27, count 0 2006.257.18:33:13.81#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:33:13.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:33:13.81#ibcon#[25=USB\r\n] 2006.257.18:33:13.81#ibcon#*before write, iclass 27, count 0 2006.257.18:33:13.81#ibcon#enter sib2, iclass 27, count 0 2006.257.18:33:13.81#ibcon#flushed, iclass 27, count 0 2006.257.18:33:13.81#ibcon#about to write, iclass 27, count 0 2006.257.18:33:13.81#ibcon#wrote, iclass 27, count 0 2006.257.18:33:13.81#ibcon#about to read 3, iclass 27, count 0 2006.257.18:33:13.84#ibcon#read 3, iclass 27, count 0 2006.257.18:33:13.84#ibcon#about to read 4, iclass 27, count 0 2006.257.18:33:13.84#ibcon#read 4, iclass 27, count 0 2006.257.18:33:13.84#ibcon#about to read 5, iclass 27, count 0 2006.257.18:33:13.84#ibcon#read 5, iclass 27, count 0 2006.257.18:33:13.84#ibcon#about to read 6, iclass 27, count 0 2006.257.18:33:13.84#ibcon#read 6, iclass 27, count 0 2006.257.18:33:13.84#ibcon#end of sib2, iclass 27, count 0 2006.257.18:33:13.84#ibcon#*after write, iclass 27, count 0 2006.257.18:33:13.84#ibcon#*before return 0, iclass 27, count 0 2006.257.18:33:13.84#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:13.84#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:13.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:33:13.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:33:13.84$vck44/valo=2,534.99 2006.257.18:33:13.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.18:33:13.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.18:33:13.84#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:13.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:13.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:13.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:13.84#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:33:13.84#ibcon#first serial, iclass 29, count 0 2006.257.18:33:13.84#ibcon#enter sib2, iclass 29, count 0 2006.257.18:33:13.84#ibcon#flushed, iclass 29, count 0 2006.257.18:33:13.84#ibcon#about to write, iclass 29, count 0 2006.257.18:33:13.84#ibcon#wrote, iclass 29, count 0 2006.257.18:33:13.84#ibcon#about to read 3, iclass 29, count 0 2006.257.18:33:13.86#ibcon#read 3, iclass 29, count 0 2006.257.18:33:13.86#ibcon#about to read 4, iclass 29, count 0 2006.257.18:33:13.86#ibcon#read 4, iclass 29, count 0 2006.257.18:33:13.86#ibcon#about to read 5, iclass 29, count 0 2006.257.18:33:13.86#ibcon#read 5, iclass 29, count 0 2006.257.18:33:13.86#ibcon#about to read 6, iclass 29, count 0 2006.257.18:33:13.86#ibcon#read 6, iclass 29, count 0 2006.257.18:33:13.86#ibcon#end of sib2, iclass 29, count 0 2006.257.18:33:13.86#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:33:13.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:33:13.86#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:33:13.86#ibcon#*before write, iclass 29, count 0 2006.257.18:33:13.86#ibcon#enter sib2, iclass 29, count 0 2006.257.18:33:13.86#ibcon#flushed, iclass 29, count 0 2006.257.18:33:13.86#ibcon#about to write, iclass 29, count 0 2006.257.18:33:13.86#ibcon#wrote, iclass 29, count 0 2006.257.18:33:13.86#ibcon#about to read 3, iclass 29, count 0 2006.257.18:33:13.90#ibcon#read 3, iclass 29, count 0 2006.257.18:33:13.90#ibcon#about to read 4, iclass 29, count 0 2006.257.18:33:13.90#ibcon#read 4, iclass 29, count 0 2006.257.18:33:13.90#ibcon#about to read 5, iclass 29, count 0 2006.257.18:33:13.90#ibcon#read 5, iclass 29, count 0 2006.257.18:33:13.90#ibcon#about to read 6, iclass 29, count 0 2006.257.18:33:13.90#ibcon#read 6, iclass 29, count 0 2006.257.18:33:13.90#ibcon#end of sib2, iclass 29, count 0 2006.257.18:33:13.90#ibcon#*after write, iclass 29, count 0 2006.257.18:33:13.90#ibcon#*before return 0, iclass 29, count 0 2006.257.18:33:13.90#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:13.90#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:13.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:33:13.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:33:13.90$vck44/va=2,7 2006.257.18:33:13.90#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.18:33:13.90#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.18:33:13.90#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:13.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:13.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:13.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:13.96#ibcon#enter wrdev, iclass 31, count 2 2006.257.18:33:13.96#ibcon#first serial, iclass 31, count 2 2006.257.18:33:13.96#ibcon#enter sib2, iclass 31, count 2 2006.257.18:33:13.96#ibcon#flushed, iclass 31, count 2 2006.257.18:33:13.96#ibcon#about to write, iclass 31, count 2 2006.257.18:33:13.96#ibcon#wrote, iclass 31, count 2 2006.257.18:33:13.96#ibcon#about to read 3, iclass 31, count 2 2006.257.18:33:13.98#ibcon#read 3, iclass 31, count 2 2006.257.18:33:13.98#ibcon#about to read 4, iclass 31, count 2 2006.257.18:33:13.98#ibcon#read 4, iclass 31, count 2 2006.257.18:33:13.98#ibcon#about to read 5, iclass 31, count 2 2006.257.18:33:13.98#ibcon#read 5, iclass 31, count 2 2006.257.18:33:13.98#ibcon#about to read 6, iclass 31, count 2 2006.257.18:33:13.98#ibcon#read 6, iclass 31, count 2 2006.257.18:33:13.98#ibcon#end of sib2, iclass 31, count 2 2006.257.18:33:13.98#ibcon#*mode == 0, iclass 31, count 2 2006.257.18:33:13.98#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.18:33:13.98#ibcon#[25=AT02-07\r\n] 2006.257.18:33:13.98#ibcon#*before write, iclass 31, count 2 2006.257.18:33:13.98#ibcon#enter sib2, iclass 31, count 2 2006.257.18:33:13.98#ibcon#flushed, iclass 31, count 2 2006.257.18:33:13.98#ibcon#about to write, iclass 31, count 2 2006.257.18:33:13.98#ibcon#wrote, iclass 31, count 2 2006.257.18:33:13.98#ibcon#about to read 3, iclass 31, count 2 2006.257.18:33:14.01#ibcon#read 3, iclass 31, count 2 2006.257.18:33:14.01#ibcon#about to read 4, iclass 31, count 2 2006.257.18:33:14.01#ibcon#read 4, iclass 31, count 2 2006.257.18:33:14.01#ibcon#about to read 5, iclass 31, count 2 2006.257.18:33:14.01#ibcon#read 5, iclass 31, count 2 2006.257.18:33:14.01#ibcon#about to read 6, iclass 31, count 2 2006.257.18:33:14.01#ibcon#read 6, iclass 31, count 2 2006.257.18:33:14.01#ibcon#end of sib2, iclass 31, count 2 2006.257.18:33:14.01#ibcon#*after write, iclass 31, count 2 2006.257.18:33:14.01#ibcon#*before return 0, iclass 31, count 2 2006.257.18:33:14.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:14.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:14.01#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.18:33:14.01#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:14.01#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:14.04#abcon#<5=/15 0.9 2.0 17.29 971014.3\r\n> 2006.257.18:33:14.06#abcon#{5=INTERFACE CLEAR} 2006.257.18:33:14.12#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:33:14.13#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:14.13#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:14.13#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:33:14.13#ibcon#first serial, iclass 31, count 0 2006.257.18:33:14.13#ibcon#enter sib2, iclass 31, count 0 2006.257.18:33:14.13#ibcon#flushed, iclass 31, count 0 2006.257.18:33:14.13#ibcon#about to write, iclass 31, count 0 2006.257.18:33:14.13#ibcon#wrote, iclass 31, count 0 2006.257.18:33:14.13#ibcon#about to read 3, iclass 31, count 0 2006.257.18:33:14.15#ibcon#read 3, iclass 31, count 0 2006.257.18:33:14.15#ibcon#about to read 4, iclass 31, count 0 2006.257.18:33:14.15#ibcon#read 4, iclass 31, count 0 2006.257.18:33:14.15#ibcon#about to read 5, iclass 31, count 0 2006.257.18:33:14.15#ibcon#read 5, iclass 31, count 0 2006.257.18:33:14.15#ibcon#about to read 6, iclass 31, count 0 2006.257.18:33:14.15#ibcon#read 6, iclass 31, count 0 2006.257.18:33:14.15#ibcon#end of sib2, iclass 31, count 0 2006.257.18:33:14.15#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:33:14.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:33:14.15#ibcon#[25=USB\r\n] 2006.257.18:33:14.15#ibcon#*before write, iclass 31, count 0 2006.257.18:33:14.15#ibcon#enter sib2, iclass 31, count 0 2006.257.18:33:14.15#ibcon#flushed, iclass 31, count 0 2006.257.18:33:14.15#ibcon#about to write, iclass 31, count 0 2006.257.18:33:14.15#ibcon#wrote, iclass 31, count 0 2006.257.18:33:14.15#ibcon#about to read 3, iclass 31, count 0 2006.257.18:33:14.18#ibcon#read 3, iclass 31, count 0 2006.257.18:33:14.18#ibcon#about to read 4, iclass 31, count 0 2006.257.18:33:14.18#ibcon#read 4, iclass 31, count 0 2006.257.18:33:14.18#ibcon#about to read 5, iclass 31, count 0 2006.257.18:33:14.18#ibcon#read 5, iclass 31, count 0 2006.257.18:33:14.18#ibcon#about to read 6, iclass 31, count 0 2006.257.18:33:14.18#ibcon#read 6, iclass 31, count 0 2006.257.18:33:14.18#ibcon#end of sib2, iclass 31, count 0 2006.257.18:33:14.18#ibcon#*after write, iclass 31, count 0 2006.257.18:33:14.18#ibcon#*before return 0, iclass 31, count 0 2006.257.18:33:14.18#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:14.18#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:14.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:33:14.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:33:14.18$vck44/valo=3,564.99 2006.257.18:33:14.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.18:33:14.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.18:33:14.18#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:14.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:14.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:14.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:14.18#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:33:14.18#ibcon#first serial, iclass 37, count 0 2006.257.18:33:14.18#ibcon#enter sib2, iclass 37, count 0 2006.257.18:33:14.18#ibcon#flushed, iclass 37, count 0 2006.257.18:33:14.18#ibcon#about to write, iclass 37, count 0 2006.257.18:33:14.18#ibcon#wrote, iclass 37, count 0 2006.257.18:33:14.18#ibcon#about to read 3, iclass 37, count 0 2006.257.18:33:14.20#ibcon#read 3, iclass 37, count 0 2006.257.18:33:14.20#ibcon#about to read 4, iclass 37, count 0 2006.257.18:33:14.20#ibcon#read 4, iclass 37, count 0 2006.257.18:33:14.20#ibcon#about to read 5, iclass 37, count 0 2006.257.18:33:14.20#ibcon#read 5, iclass 37, count 0 2006.257.18:33:14.20#ibcon#about to read 6, iclass 37, count 0 2006.257.18:33:14.20#ibcon#read 6, iclass 37, count 0 2006.257.18:33:14.20#ibcon#end of sib2, iclass 37, count 0 2006.257.18:33:14.20#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:33:14.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:33:14.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:33:14.20#ibcon#*before write, iclass 37, count 0 2006.257.18:33:14.20#ibcon#enter sib2, iclass 37, count 0 2006.257.18:33:14.20#ibcon#flushed, iclass 37, count 0 2006.257.18:33:14.20#ibcon#about to write, iclass 37, count 0 2006.257.18:33:14.20#ibcon#wrote, iclass 37, count 0 2006.257.18:33:14.20#ibcon#about to read 3, iclass 37, count 0 2006.257.18:33:14.24#ibcon#read 3, iclass 37, count 0 2006.257.18:33:14.24#ibcon#about to read 4, iclass 37, count 0 2006.257.18:33:14.24#ibcon#read 4, iclass 37, count 0 2006.257.18:33:14.24#ibcon#about to read 5, iclass 37, count 0 2006.257.18:33:14.24#ibcon#read 5, iclass 37, count 0 2006.257.18:33:14.24#ibcon#about to read 6, iclass 37, count 0 2006.257.18:33:14.24#ibcon#read 6, iclass 37, count 0 2006.257.18:33:14.24#ibcon#end of sib2, iclass 37, count 0 2006.257.18:33:14.24#ibcon#*after write, iclass 37, count 0 2006.257.18:33:14.24#ibcon#*before return 0, iclass 37, count 0 2006.257.18:33:14.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:14.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:14.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:33:14.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:33:14.24$vck44/va=3,8 2006.257.18:33:14.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.18:33:14.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.18:33:14.24#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:14.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:14.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:14.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:14.30#ibcon#enter wrdev, iclass 39, count 2 2006.257.18:33:14.30#ibcon#first serial, iclass 39, count 2 2006.257.18:33:14.30#ibcon#enter sib2, iclass 39, count 2 2006.257.18:33:14.30#ibcon#flushed, iclass 39, count 2 2006.257.18:33:14.30#ibcon#about to write, iclass 39, count 2 2006.257.18:33:14.30#ibcon#wrote, iclass 39, count 2 2006.257.18:33:14.30#ibcon#about to read 3, iclass 39, count 2 2006.257.18:33:14.32#ibcon#read 3, iclass 39, count 2 2006.257.18:33:14.32#ibcon#about to read 4, iclass 39, count 2 2006.257.18:33:14.32#ibcon#read 4, iclass 39, count 2 2006.257.18:33:14.32#ibcon#about to read 5, iclass 39, count 2 2006.257.18:33:14.32#ibcon#read 5, iclass 39, count 2 2006.257.18:33:14.32#ibcon#about to read 6, iclass 39, count 2 2006.257.18:33:14.32#ibcon#read 6, iclass 39, count 2 2006.257.18:33:14.32#ibcon#end of sib2, iclass 39, count 2 2006.257.18:33:14.32#ibcon#*mode == 0, iclass 39, count 2 2006.257.18:33:14.32#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.18:33:14.32#ibcon#[25=AT03-08\r\n] 2006.257.18:33:14.32#ibcon#*before write, iclass 39, count 2 2006.257.18:33:14.32#ibcon#enter sib2, iclass 39, count 2 2006.257.18:33:14.32#ibcon#flushed, iclass 39, count 2 2006.257.18:33:14.32#ibcon#about to write, iclass 39, count 2 2006.257.18:33:14.32#ibcon#wrote, iclass 39, count 2 2006.257.18:33:14.32#ibcon#about to read 3, iclass 39, count 2 2006.257.18:33:14.35#ibcon#read 3, iclass 39, count 2 2006.257.18:33:14.35#ibcon#about to read 4, iclass 39, count 2 2006.257.18:33:14.35#ibcon#read 4, iclass 39, count 2 2006.257.18:33:14.35#ibcon#about to read 5, iclass 39, count 2 2006.257.18:33:14.35#ibcon#read 5, iclass 39, count 2 2006.257.18:33:14.35#ibcon#about to read 6, iclass 39, count 2 2006.257.18:33:14.35#ibcon#read 6, iclass 39, count 2 2006.257.18:33:14.35#ibcon#end of sib2, iclass 39, count 2 2006.257.18:33:14.35#ibcon#*after write, iclass 39, count 2 2006.257.18:33:14.35#ibcon#*before return 0, iclass 39, count 2 2006.257.18:33:14.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:14.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:14.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.18:33:14.35#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:14.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:14.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:14.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:14.47#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:33:14.47#ibcon#first serial, iclass 39, count 0 2006.257.18:33:14.47#ibcon#enter sib2, iclass 39, count 0 2006.257.18:33:14.47#ibcon#flushed, iclass 39, count 0 2006.257.18:33:14.47#ibcon#about to write, iclass 39, count 0 2006.257.18:33:14.47#ibcon#wrote, iclass 39, count 0 2006.257.18:33:14.47#ibcon#about to read 3, iclass 39, count 0 2006.257.18:33:14.49#ibcon#read 3, iclass 39, count 0 2006.257.18:33:14.49#ibcon#about to read 4, iclass 39, count 0 2006.257.18:33:14.49#ibcon#read 4, iclass 39, count 0 2006.257.18:33:14.49#ibcon#about to read 5, iclass 39, count 0 2006.257.18:33:14.49#ibcon#read 5, iclass 39, count 0 2006.257.18:33:14.49#ibcon#about to read 6, iclass 39, count 0 2006.257.18:33:14.49#ibcon#read 6, iclass 39, count 0 2006.257.18:33:14.49#ibcon#end of sib2, iclass 39, count 0 2006.257.18:33:14.49#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:33:14.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:33:14.49#ibcon#[25=USB\r\n] 2006.257.18:33:14.49#ibcon#*before write, iclass 39, count 0 2006.257.18:33:14.49#ibcon#enter sib2, iclass 39, count 0 2006.257.18:33:14.49#ibcon#flushed, iclass 39, count 0 2006.257.18:33:14.49#ibcon#about to write, iclass 39, count 0 2006.257.18:33:14.49#ibcon#wrote, iclass 39, count 0 2006.257.18:33:14.49#ibcon#about to read 3, iclass 39, count 0 2006.257.18:33:14.52#ibcon#read 3, iclass 39, count 0 2006.257.18:33:14.52#ibcon#about to read 4, iclass 39, count 0 2006.257.18:33:14.52#ibcon#read 4, iclass 39, count 0 2006.257.18:33:14.52#ibcon#about to read 5, iclass 39, count 0 2006.257.18:33:14.52#ibcon#read 5, iclass 39, count 0 2006.257.18:33:14.52#ibcon#about to read 6, iclass 39, count 0 2006.257.18:33:14.52#ibcon#read 6, iclass 39, count 0 2006.257.18:33:14.52#ibcon#end of sib2, iclass 39, count 0 2006.257.18:33:14.52#ibcon#*after write, iclass 39, count 0 2006.257.18:33:14.52#ibcon#*before return 0, iclass 39, count 0 2006.257.18:33:14.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:14.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:14.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:33:14.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:33:14.52$vck44/valo=4,624.99 2006.257.18:33:14.52#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.18:33:14.52#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.18:33:14.52#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:14.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:14.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:14.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:14.52#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:33:14.52#ibcon#first serial, iclass 3, count 0 2006.257.18:33:14.52#ibcon#enter sib2, iclass 3, count 0 2006.257.18:33:14.52#ibcon#flushed, iclass 3, count 0 2006.257.18:33:14.52#ibcon#about to write, iclass 3, count 0 2006.257.18:33:14.52#ibcon#wrote, iclass 3, count 0 2006.257.18:33:14.52#ibcon#about to read 3, iclass 3, count 0 2006.257.18:33:14.54#ibcon#read 3, iclass 3, count 0 2006.257.18:33:14.54#ibcon#about to read 4, iclass 3, count 0 2006.257.18:33:14.54#ibcon#read 4, iclass 3, count 0 2006.257.18:33:14.54#ibcon#about to read 5, iclass 3, count 0 2006.257.18:33:14.54#ibcon#read 5, iclass 3, count 0 2006.257.18:33:14.54#ibcon#about to read 6, iclass 3, count 0 2006.257.18:33:14.54#ibcon#read 6, iclass 3, count 0 2006.257.18:33:14.54#ibcon#end of sib2, iclass 3, count 0 2006.257.18:33:14.54#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:33:14.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:33:14.54#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:33:14.54#ibcon#*before write, iclass 3, count 0 2006.257.18:33:14.54#ibcon#enter sib2, iclass 3, count 0 2006.257.18:33:14.54#ibcon#flushed, iclass 3, count 0 2006.257.18:33:14.54#ibcon#about to write, iclass 3, count 0 2006.257.18:33:14.54#ibcon#wrote, iclass 3, count 0 2006.257.18:33:14.54#ibcon#about to read 3, iclass 3, count 0 2006.257.18:33:14.58#ibcon#read 3, iclass 3, count 0 2006.257.18:33:14.58#ibcon#about to read 4, iclass 3, count 0 2006.257.18:33:14.58#ibcon#read 4, iclass 3, count 0 2006.257.18:33:14.58#ibcon#about to read 5, iclass 3, count 0 2006.257.18:33:14.58#ibcon#read 5, iclass 3, count 0 2006.257.18:33:14.58#ibcon#about to read 6, iclass 3, count 0 2006.257.18:33:14.58#ibcon#read 6, iclass 3, count 0 2006.257.18:33:14.58#ibcon#end of sib2, iclass 3, count 0 2006.257.18:33:14.58#ibcon#*after write, iclass 3, count 0 2006.257.18:33:14.58#ibcon#*before return 0, iclass 3, count 0 2006.257.18:33:14.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:14.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:14.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:33:14.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:33:14.58$vck44/va=4,7 2006.257.18:33:14.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.18:33:14.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.18:33:14.58#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:14.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:14.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:14.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:14.64#ibcon#enter wrdev, iclass 5, count 2 2006.257.18:33:14.64#ibcon#first serial, iclass 5, count 2 2006.257.18:33:14.64#ibcon#enter sib2, iclass 5, count 2 2006.257.18:33:14.64#ibcon#flushed, iclass 5, count 2 2006.257.18:33:14.64#ibcon#about to write, iclass 5, count 2 2006.257.18:33:14.64#ibcon#wrote, iclass 5, count 2 2006.257.18:33:14.64#ibcon#about to read 3, iclass 5, count 2 2006.257.18:33:14.66#ibcon#read 3, iclass 5, count 2 2006.257.18:33:14.66#ibcon#about to read 4, iclass 5, count 2 2006.257.18:33:14.66#ibcon#read 4, iclass 5, count 2 2006.257.18:33:14.66#ibcon#about to read 5, iclass 5, count 2 2006.257.18:33:14.66#ibcon#read 5, iclass 5, count 2 2006.257.18:33:14.66#ibcon#about to read 6, iclass 5, count 2 2006.257.18:33:14.66#ibcon#read 6, iclass 5, count 2 2006.257.18:33:14.66#ibcon#end of sib2, iclass 5, count 2 2006.257.18:33:14.66#ibcon#*mode == 0, iclass 5, count 2 2006.257.18:33:14.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.18:33:14.66#ibcon#[25=AT04-07\r\n] 2006.257.18:33:14.66#ibcon#*before write, iclass 5, count 2 2006.257.18:33:14.66#ibcon#enter sib2, iclass 5, count 2 2006.257.18:33:14.66#ibcon#flushed, iclass 5, count 2 2006.257.18:33:14.66#ibcon#about to write, iclass 5, count 2 2006.257.18:33:14.66#ibcon#wrote, iclass 5, count 2 2006.257.18:33:14.66#ibcon#about to read 3, iclass 5, count 2 2006.257.18:33:14.69#ibcon#read 3, iclass 5, count 2 2006.257.18:33:14.69#ibcon#about to read 4, iclass 5, count 2 2006.257.18:33:14.69#ibcon#read 4, iclass 5, count 2 2006.257.18:33:14.69#ibcon#about to read 5, iclass 5, count 2 2006.257.18:33:14.69#ibcon#read 5, iclass 5, count 2 2006.257.18:33:14.69#ibcon#about to read 6, iclass 5, count 2 2006.257.18:33:14.69#ibcon#read 6, iclass 5, count 2 2006.257.18:33:14.69#ibcon#end of sib2, iclass 5, count 2 2006.257.18:33:14.69#ibcon#*after write, iclass 5, count 2 2006.257.18:33:14.69#ibcon#*before return 0, iclass 5, count 2 2006.257.18:33:14.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:14.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:14.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.18:33:14.69#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:14.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:14.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:14.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:14.81#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:33:14.81#ibcon#first serial, iclass 5, count 0 2006.257.18:33:14.81#ibcon#enter sib2, iclass 5, count 0 2006.257.18:33:14.81#ibcon#flushed, iclass 5, count 0 2006.257.18:33:14.81#ibcon#about to write, iclass 5, count 0 2006.257.18:33:14.81#ibcon#wrote, iclass 5, count 0 2006.257.18:33:14.81#ibcon#about to read 3, iclass 5, count 0 2006.257.18:33:14.83#ibcon#read 3, iclass 5, count 0 2006.257.18:33:14.83#ibcon#about to read 4, iclass 5, count 0 2006.257.18:33:14.83#ibcon#read 4, iclass 5, count 0 2006.257.18:33:14.83#ibcon#about to read 5, iclass 5, count 0 2006.257.18:33:14.83#ibcon#read 5, iclass 5, count 0 2006.257.18:33:14.83#ibcon#about to read 6, iclass 5, count 0 2006.257.18:33:14.83#ibcon#read 6, iclass 5, count 0 2006.257.18:33:14.83#ibcon#end of sib2, iclass 5, count 0 2006.257.18:33:14.83#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:33:14.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:33:14.83#ibcon#[25=USB\r\n] 2006.257.18:33:14.83#ibcon#*before write, iclass 5, count 0 2006.257.18:33:14.83#ibcon#enter sib2, iclass 5, count 0 2006.257.18:33:14.83#ibcon#flushed, iclass 5, count 0 2006.257.18:33:14.83#ibcon#about to write, iclass 5, count 0 2006.257.18:33:14.83#ibcon#wrote, iclass 5, count 0 2006.257.18:33:14.83#ibcon#about to read 3, iclass 5, count 0 2006.257.18:33:14.86#ibcon#read 3, iclass 5, count 0 2006.257.18:33:14.86#ibcon#about to read 4, iclass 5, count 0 2006.257.18:33:14.86#ibcon#read 4, iclass 5, count 0 2006.257.18:33:14.86#ibcon#about to read 5, iclass 5, count 0 2006.257.18:33:14.86#ibcon#read 5, iclass 5, count 0 2006.257.18:33:14.86#ibcon#about to read 6, iclass 5, count 0 2006.257.18:33:14.86#ibcon#read 6, iclass 5, count 0 2006.257.18:33:14.86#ibcon#end of sib2, iclass 5, count 0 2006.257.18:33:14.86#ibcon#*after write, iclass 5, count 0 2006.257.18:33:14.86#ibcon#*before return 0, iclass 5, count 0 2006.257.18:33:14.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:14.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:14.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:33:14.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:33:14.86$vck44/valo=5,734.99 2006.257.18:33:14.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.18:33:14.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.18:33:14.86#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:14.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:14.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:14.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:14.86#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:33:14.86#ibcon#first serial, iclass 7, count 0 2006.257.18:33:14.86#ibcon#enter sib2, iclass 7, count 0 2006.257.18:33:14.86#ibcon#flushed, iclass 7, count 0 2006.257.18:33:14.86#ibcon#about to write, iclass 7, count 0 2006.257.18:33:14.86#ibcon#wrote, iclass 7, count 0 2006.257.18:33:14.86#ibcon#about to read 3, iclass 7, count 0 2006.257.18:33:14.88#ibcon#read 3, iclass 7, count 0 2006.257.18:33:14.88#ibcon#about to read 4, iclass 7, count 0 2006.257.18:33:14.88#ibcon#read 4, iclass 7, count 0 2006.257.18:33:14.88#ibcon#about to read 5, iclass 7, count 0 2006.257.18:33:14.88#ibcon#read 5, iclass 7, count 0 2006.257.18:33:14.88#ibcon#about to read 6, iclass 7, count 0 2006.257.18:33:14.88#ibcon#read 6, iclass 7, count 0 2006.257.18:33:14.88#ibcon#end of sib2, iclass 7, count 0 2006.257.18:33:14.88#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:33:14.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:33:14.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:33:14.88#ibcon#*before write, iclass 7, count 0 2006.257.18:33:14.88#ibcon#enter sib2, iclass 7, count 0 2006.257.18:33:14.88#ibcon#flushed, iclass 7, count 0 2006.257.18:33:14.88#ibcon#about to write, iclass 7, count 0 2006.257.18:33:14.88#ibcon#wrote, iclass 7, count 0 2006.257.18:33:14.88#ibcon#about to read 3, iclass 7, count 0 2006.257.18:33:14.92#ibcon#read 3, iclass 7, count 0 2006.257.18:33:14.92#ibcon#about to read 4, iclass 7, count 0 2006.257.18:33:14.92#ibcon#read 4, iclass 7, count 0 2006.257.18:33:14.92#ibcon#about to read 5, iclass 7, count 0 2006.257.18:33:14.92#ibcon#read 5, iclass 7, count 0 2006.257.18:33:14.92#ibcon#about to read 6, iclass 7, count 0 2006.257.18:33:14.92#ibcon#read 6, iclass 7, count 0 2006.257.18:33:14.92#ibcon#end of sib2, iclass 7, count 0 2006.257.18:33:14.92#ibcon#*after write, iclass 7, count 0 2006.257.18:33:14.92#ibcon#*before return 0, iclass 7, count 0 2006.257.18:33:14.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:14.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:14.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:33:14.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:33:14.92$vck44/va=5,4 2006.257.18:33:14.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.18:33:14.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.18:33:14.92#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:14.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:14.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:14.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:14.98#ibcon#enter wrdev, iclass 11, count 2 2006.257.18:33:14.98#ibcon#first serial, iclass 11, count 2 2006.257.18:33:14.98#ibcon#enter sib2, iclass 11, count 2 2006.257.18:33:14.98#ibcon#flushed, iclass 11, count 2 2006.257.18:33:14.98#ibcon#about to write, iclass 11, count 2 2006.257.18:33:14.98#ibcon#wrote, iclass 11, count 2 2006.257.18:33:14.98#ibcon#about to read 3, iclass 11, count 2 2006.257.18:33:15.00#ibcon#read 3, iclass 11, count 2 2006.257.18:33:15.00#ibcon#about to read 4, iclass 11, count 2 2006.257.18:33:15.00#ibcon#read 4, iclass 11, count 2 2006.257.18:33:15.00#ibcon#about to read 5, iclass 11, count 2 2006.257.18:33:15.00#ibcon#read 5, iclass 11, count 2 2006.257.18:33:15.00#ibcon#about to read 6, iclass 11, count 2 2006.257.18:33:15.00#ibcon#read 6, iclass 11, count 2 2006.257.18:33:15.00#ibcon#end of sib2, iclass 11, count 2 2006.257.18:33:15.00#ibcon#*mode == 0, iclass 11, count 2 2006.257.18:33:15.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.18:33:15.00#ibcon#[25=AT05-04\r\n] 2006.257.18:33:15.00#ibcon#*before write, iclass 11, count 2 2006.257.18:33:15.00#ibcon#enter sib2, iclass 11, count 2 2006.257.18:33:15.00#ibcon#flushed, iclass 11, count 2 2006.257.18:33:15.00#ibcon#about to write, iclass 11, count 2 2006.257.18:33:15.00#ibcon#wrote, iclass 11, count 2 2006.257.18:33:15.00#ibcon#about to read 3, iclass 11, count 2 2006.257.18:33:15.03#ibcon#read 3, iclass 11, count 2 2006.257.18:33:15.03#ibcon#about to read 4, iclass 11, count 2 2006.257.18:33:15.03#ibcon#read 4, iclass 11, count 2 2006.257.18:33:15.03#ibcon#about to read 5, iclass 11, count 2 2006.257.18:33:15.03#ibcon#read 5, iclass 11, count 2 2006.257.18:33:15.03#ibcon#about to read 6, iclass 11, count 2 2006.257.18:33:15.03#ibcon#read 6, iclass 11, count 2 2006.257.18:33:15.03#ibcon#end of sib2, iclass 11, count 2 2006.257.18:33:15.03#ibcon#*after write, iclass 11, count 2 2006.257.18:33:15.03#ibcon#*before return 0, iclass 11, count 2 2006.257.18:33:15.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:15.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:15.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.18:33:15.03#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:15.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:15.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:15.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:15.15#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:33:15.15#ibcon#first serial, iclass 11, count 0 2006.257.18:33:15.15#ibcon#enter sib2, iclass 11, count 0 2006.257.18:33:15.15#ibcon#flushed, iclass 11, count 0 2006.257.18:33:15.15#ibcon#about to write, iclass 11, count 0 2006.257.18:33:15.15#ibcon#wrote, iclass 11, count 0 2006.257.18:33:15.15#ibcon#about to read 3, iclass 11, count 0 2006.257.18:33:15.17#ibcon#read 3, iclass 11, count 0 2006.257.18:33:15.17#ibcon#about to read 4, iclass 11, count 0 2006.257.18:33:15.17#ibcon#read 4, iclass 11, count 0 2006.257.18:33:15.17#ibcon#about to read 5, iclass 11, count 0 2006.257.18:33:15.17#ibcon#read 5, iclass 11, count 0 2006.257.18:33:15.17#ibcon#about to read 6, iclass 11, count 0 2006.257.18:33:15.17#ibcon#read 6, iclass 11, count 0 2006.257.18:33:15.17#ibcon#end of sib2, iclass 11, count 0 2006.257.18:33:15.17#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:33:15.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:33:15.17#ibcon#[25=USB\r\n] 2006.257.18:33:15.17#ibcon#*before write, iclass 11, count 0 2006.257.18:33:15.17#ibcon#enter sib2, iclass 11, count 0 2006.257.18:33:15.17#ibcon#flushed, iclass 11, count 0 2006.257.18:33:15.17#ibcon#about to write, iclass 11, count 0 2006.257.18:33:15.17#ibcon#wrote, iclass 11, count 0 2006.257.18:33:15.17#ibcon#about to read 3, iclass 11, count 0 2006.257.18:33:15.20#ibcon#read 3, iclass 11, count 0 2006.257.18:33:15.20#ibcon#about to read 4, iclass 11, count 0 2006.257.18:33:15.20#ibcon#read 4, iclass 11, count 0 2006.257.18:33:15.20#ibcon#about to read 5, iclass 11, count 0 2006.257.18:33:15.20#ibcon#read 5, iclass 11, count 0 2006.257.18:33:15.20#ibcon#about to read 6, iclass 11, count 0 2006.257.18:33:15.20#ibcon#read 6, iclass 11, count 0 2006.257.18:33:15.20#ibcon#end of sib2, iclass 11, count 0 2006.257.18:33:15.20#ibcon#*after write, iclass 11, count 0 2006.257.18:33:15.20#ibcon#*before return 0, iclass 11, count 0 2006.257.18:33:15.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:15.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:15.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:33:15.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:33:15.20$vck44/valo=6,814.99 2006.257.18:33:15.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.18:33:15.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.18:33:15.20#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:15.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:15.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:15.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:15.20#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:33:15.20#ibcon#first serial, iclass 13, count 0 2006.257.18:33:15.20#ibcon#enter sib2, iclass 13, count 0 2006.257.18:33:15.20#ibcon#flushed, iclass 13, count 0 2006.257.18:33:15.20#ibcon#about to write, iclass 13, count 0 2006.257.18:33:15.20#ibcon#wrote, iclass 13, count 0 2006.257.18:33:15.20#ibcon#about to read 3, iclass 13, count 0 2006.257.18:33:15.22#ibcon#read 3, iclass 13, count 0 2006.257.18:33:15.22#ibcon#about to read 4, iclass 13, count 0 2006.257.18:33:15.22#ibcon#read 4, iclass 13, count 0 2006.257.18:33:15.22#ibcon#about to read 5, iclass 13, count 0 2006.257.18:33:15.22#ibcon#read 5, iclass 13, count 0 2006.257.18:33:15.22#ibcon#about to read 6, iclass 13, count 0 2006.257.18:33:15.22#ibcon#read 6, iclass 13, count 0 2006.257.18:33:15.22#ibcon#end of sib2, iclass 13, count 0 2006.257.18:33:15.22#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:33:15.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:33:15.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:33:15.22#ibcon#*before write, iclass 13, count 0 2006.257.18:33:15.22#ibcon#enter sib2, iclass 13, count 0 2006.257.18:33:15.22#ibcon#flushed, iclass 13, count 0 2006.257.18:33:15.22#ibcon#about to write, iclass 13, count 0 2006.257.18:33:15.22#ibcon#wrote, iclass 13, count 0 2006.257.18:33:15.22#ibcon#about to read 3, iclass 13, count 0 2006.257.18:33:15.26#ibcon#read 3, iclass 13, count 0 2006.257.18:33:15.26#ibcon#about to read 4, iclass 13, count 0 2006.257.18:33:15.26#ibcon#read 4, iclass 13, count 0 2006.257.18:33:15.26#ibcon#about to read 5, iclass 13, count 0 2006.257.18:33:15.26#ibcon#read 5, iclass 13, count 0 2006.257.18:33:15.26#ibcon#about to read 6, iclass 13, count 0 2006.257.18:33:15.26#ibcon#read 6, iclass 13, count 0 2006.257.18:33:15.26#ibcon#end of sib2, iclass 13, count 0 2006.257.18:33:15.26#ibcon#*after write, iclass 13, count 0 2006.257.18:33:15.26#ibcon#*before return 0, iclass 13, count 0 2006.257.18:33:15.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:15.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:15.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:33:15.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:33:15.26$vck44/va=6,4 2006.257.18:33:15.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.18:33:15.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.18:33:15.26#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:15.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:15.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:15.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:15.32#ibcon#enter wrdev, iclass 15, count 2 2006.257.18:33:15.32#ibcon#first serial, iclass 15, count 2 2006.257.18:33:15.32#ibcon#enter sib2, iclass 15, count 2 2006.257.18:33:15.32#ibcon#flushed, iclass 15, count 2 2006.257.18:33:15.32#ibcon#about to write, iclass 15, count 2 2006.257.18:33:15.32#ibcon#wrote, iclass 15, count 2 2006.257.18:33:15.32#ibcon#about to read 3, iclass 15, count 2 2006.257.18:33:15.34#ibcon#read 3, iclass 15, count 2 2006.257.18:33:15.34#ibcon#about to read 4, iclass 15, count 2 2006.257.18:33:15.34#ibcon#read 4, iclass 15, count 2 2006.257.18:33:15.34#ibcon#about to read 5, iclass 15, count 2 2006.257.18:33:15.34#ibcon#read 5, iclass 15, count 2 2006.257.18:33:15.34#ibcon#about to read 6, iclass 15, count 2 2006.257.18:33:15.34#ibcon#read 6, iclass 15, count 2 2006.257.18:33:15.34#ibcon#end of sib2, iclass 15, count 2 2006.257.18:33:15.34#ibcon#*mode == 0, iclass 15, count 2 2006.257.18:33:15.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.18:33:15.34#ibcon#[25=AT06-04\r\n] 2006.257.18:33:15.34#ibcon#*before write, iclass 15, count 2 2006.257.18:33:15.34#ibcon#enter sib2, iclass 15, count 2 2006.257.18:33:15.34#ibcon#flushed, iclass 15, count 2 2006.257.18:33:15.34#ibcon#about to write, iclass 15, count 2 2006.257.18:33:15.34#ibcon#wrote, iclass 15, count 2 2006.257.18:33:15.34#ibcon#about to read 3, iclass 15, count 2 2006.257.18:33:15.37#ibcon#read 3, iclass 15, count 2 2006.257.18:33:15.37#ibcon#about to read 4, iclass 15, count 2 2006.257.18:33:15.37#ibcon#read 4, iclass 15, count 2 2006.257.18:33:15.37#ibcon#about to read 5, iclass 15, count 2 2006.257.18:33:15.37#ibcon#read 5, iclass 15, count 2 2006.257.18:33:15.37#ibcon#about to read 6, iclass 15, count 2 2006.257.18:33:15.37#ibcon#read 6, iclass 15, count 2 2006.257.18:33:15.37#ibcon#end of sib2, iclass 15, count 2 2006.257.18:33:15.37#ibcon#*after write, iclass 15, count 2 2006.257.18:33:15.37#ibcon#*before return 0, iclass 15, count 2 2006.257.18:33:15.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:15.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:15.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.18:33:15.37#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:15.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:15.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:15.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:15.49#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:33:15.49#ibcon#first serial, iclass 15, count 0 2006.257.18:33:15.49#ibcon#enter sib2, iclass 15, count 0 2006.257.18:33:15.49#ibcon#flushed, iclass 15, count 0 2006.257.18:33:15.49#ibcon#about to write, iclass 15, count 0 2006.257.18:33:15.49#ibcon#wrote, iclass 15, count 0 2006.257.18:33:15.49#ibcon#about to read 3, iclass 15, count 0 2006.257.18:33:15.51#ibcon#read 3, iclass 15, count 0 2006.257.18:33:15.51#ibcon#about to read 4, iclass 15, count 0 2006.257.18:33:15.51#ibcon#read 4, iclass 15, count 0 2006.257.18:33:15.51#ibcon#about to read 5, iclass 15, count 0 2006.257.18:33:15.51#ibcon#read 5, iclass 15, count 0 2006.257.18:33:15.51#ibcon#about to read 6, iclass 15, count 0 2006.257.18:33:15.51#ibcon#read 6, iclass 15, count 0 2006.257.18:33:15.51#ibcon#end of sib2, iclass 15, count 0 2006.257.18:33:15.51#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:33:15.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:33:15.51#ibcon#[25=USB\r\n] 2006.257.18:33:15.51#ibcon#*before write, iclass 15, count 0 2006.257.18:33:15.51#ibcon#enter sib2, iclass 15, count 0 2006.257.18:33:15.51#ibcon#flushed, iclass 15, count 0 2006.257.18:33:15.51#ibcon#about to write, iclass 15, count 0 2006.257.18:33:15.51#ibcon#wrote, iclass 15, count 0 2006.257.18:33:15.51#ibcon#about to read 3, iclass 15, count 0 2006.257.18:33:15.54#ibcon#read 3, iclass 15, count 0 2006.257.18:33:15.54#ibcon#about to read 4, iclass 15, count 0 2006.257.18:33:15.54#ibcon#read 4, iclass 15, count 0 2006.257.18:33:15.54#ibcon#about to read 5, iclass 15, count 0 2006.257.18:33:15.54#ibcon#read 5, iclass 15, count 0 2006.257.18:33:15.54#ibcon#about to read 6, iclass 15, count 0 2006.257.18:33:15.54#ibcon#read 6, iclass 15, count 0 2006.257.18:33:15.54#ibcon#end of sib2, iclass 15, count 0 2006.257.18:33:15.54#ibcon#*after write, iclass 15, count 0 2006.257.18:33:15.54#ibcon#*before return 0, iclass 15, count 0 2006.257.18:33:15.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:15.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:15.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:33:15.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:33:15.54$vck44/valo=7,864.99 2006.257.18:33:15.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.18:33:15.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.18:33:15.54#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:15.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:15.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:15.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:15.54#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:33:15.54#ibcon#first serial, iclass 17, count 0 2006.257.18:33:15.54#ibcon#enter sib2, iclass 17, count 0 2006.257.18:33:15.54#ibcon#flushed, iclass 17, count 0 2006.257.18:33:15.54#ibcon#about to write, iclass 17, count 0 2006.257.18:33:15.54#ibcon#wrote, iclass 17, count 0 2006.257.18:33:15.54#ibcon#about to read 3, iclass 17, count 0 2006.257.18:33:15.56#ibcon#read 3, iclass 17, count 0 2006.257.18:33:15.56#ibcon#about to read 4, iclass 17, count 0 2006.257.18:33:15.56#ibcon#read 4, iclass 17, count 0 2006.257.18:33:15.56#ibcon#about to read 5, iclass 17, count 0 2006.257.18:33:15.56#ibcon#read 5, iclass 17, count 0 2006.257.18:33:15.56#ibcon#about to read 6, iclass 17, count 0 2006.257.18:33:15.56#ibcon#read 6, iclass 17, count 0 2006.257.18:33:15.56#ibcon#end of sib2, iclass 17, count 0 2006.257.18:33:15.56#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:33:15.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:33:15.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:33:15.56#ibcon#*before write, iclass 17, count 0 2006.257.18:33:15.56#ibcon#enter sib2, iclass 17, count 0 2006.257.18:33:15.56#ibcon#flushed, iclass 17, count 0 2006.257.18:33:15.56#ibcon#about to write, iclass 17, count 0 2006.257.18:33:15.56#ibcon#wrote, iclass 17, count 0 2006.257.18:33:15.56#ibcon#about to read 3, iclass 17, count 0 2006.257.18:33:15.60#ibcon#read 3, iclass 17, count 0 2006.257.18:33:15.60#ibcon#about to read 4, iclass 17, count 0 2006.257.18:33:15.60#ibcon#read 4, iclass 17, count 0 2006.257.18:33:15.60#ibcon#about to read 5, iclass 17, count 0 2006.257.18:33:15.60#ibcon#read 5, iclass 17, count 0 2006.257.18:33:15.60#ibcon#about to read 6, iclass 17, count 0 2006.257.18:33:15.60#ibcon#read 6, iclass 17, count 0 2006.257.18:33:15.60#ibcon#end of sib2, iclass 17, count 0 2006.257.18:33:15.60#ibcon#*after write, iclass 17, count 0 2006.257.18:33:15.60#ibcon#*before return 0, iclass 17, count 0 2006.257.18:33:15.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:15.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:15.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:33:15.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:33:15.60$vck44/va=7,4 2006.257.18:33:15.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.18:33:15.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.18:33:15.60#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:15.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:15.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:15.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:15.66#ibcon#enter wrdev, iclass 19, count 2 2006.257.18:33:15.66#ibcon#first serial, iclass 19, count 2 2006.257.18:33:15.66#ibcon#enter sib2, iclass 19, count 2 2006.257.18:33:15.66#ibcon#flushed, iclass 19, count 2 2006.257.18:33:15.66#ibcon#about to write, iclass 19, count 2 2006.257.18:33:15.66#ibcon#wrote, iclass 19, count 2 2006.257.18:33:15.66#ibcon#about to read 3, iclass 19, count 2 2006.257.18:33:15.68#ibcon#read 3, iclass 19, count 2 2006.257.18:33:15.68#ibcon#about to read 4, iclass 19, count 2 2006.257.18:33:15.68#ibcon#read 4, iclass 19, count 2 2006.257.18:33:15.68#ibcon#about to read 5, iclass 19, count 2 2006.257.18:33:15.68#ibcon#read 5, iclass 19, count 2 2006.257.18:33:15.68#ibcon#about to read 6, iclass 19, count 2 2006.257.18:33:15.68#ibcon#read 6, iclass 19, count 2 2006.257.18:33:15.68#ibcon#end of sib2, iclass 19, count 2 2006.257.18:33:15.68#ibcon#*mode == 0, iclass 19, count 2 2006.257.18:33:15.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.18:33:15.68#ibcon#[25=AT07-04\r\n] 2006.257.18:33:15.68#ibcon#*before write, iclass 19, count 2 2006.257.18:33:15.68#ibcon#enter sib2, iclass 19, count 2 2006.257.18:33:15.68#ibcon#flushed, iclass 19, count 2 2006.257.18:33:15.68#ibcon#about to write, iclass 19, count 2 2006.257.18:33:15.68#ibcon#wrote, iclass 19, count 2 2006.257.18:33:15.68#ibcon#about to read 3, iclass 19, count 2 2006.257.18:33:15.71#ibcon#read 3, iclass 19, count 2 2006.257.18:33:15.71#ibcon#about to read 4, iclass 19, count 2 2006.257.18:33:15.71#ibcon#read 4, iclass 19, count 2 2006.257.18:33:15.71#ibcon#about to read 5, iclass 19, count 2 2006.257.18:33:15.71#ibcon#read 5, iclass 19, count 2 2006.257.18:33:15.71#ibcon#about to read 6, iclass 19, count 2 2006.257.18:33:15.71#ibcon#read 6, iclass 19, count 2 2006.257.18:33:15.71#ibcon#end of sib2, iclass 19, count 2 2006.257.18:33:15.71#ibcon#*after write, iclass 19, count 2 2006.257.18:33:15.71#ibcon#*before return 0, iclass 19, count 2 2006.257.18:33:15.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:15.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:15.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.18:33:15.71#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:15.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:15.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:15.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:15.83#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:33:15.83#ibcon#first serial, iclass 19, count 0 2006.257.18:33:15.83#ibcon#enter sib2, iclass 19, count 0 2006.257.18:33:15.83#ibcon#flushed, iclass 19, count 0 2006.257.18:33:15.83#ibcon#about to write, iclass 19, count 0 2006.257.18:33:15.83#ibcon#wrote, iclass 19, count 0 2006.257.18:33:15.83#ibcon#about to read 3, iclass 19, count 0 2006.257.18:33:15.85#ibcon#read 3, iclass 19, count 0 2006.257.18:33:15.85#ibcon#about to read 4, iclass 19, count 0 2006.257.18:33:15.85#ibcon#read 4, iclass 19, count 0 2006.257.18:33:15.85#ibcon#about to read 5, iclass 19, count 0 2006.257.18:33:15.85#ibcon#read 5, iclass 19, count 0 2006.257.18:33:15.85#ibcon#about to read 6, iclass 19, count 0 2006.257.18:33:15.85#ibcon#read 6, iclass 19, count 0 2006.257.18:33:15.85#ibcon#end of sib2, iclass 19, count 0 2006.257.18:33:15.85#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:33:15.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:33:15.85#ibcon#[25=USB\r\n] 2006.257.18:33:15.85#ibcon#*before write, iclass 19, count 0 2006.257.18:33:15.85#ibcon#enter sib2, iclass 19, count 0 2006.257.18:33:15.85#ibcon#flushed, iclass 19, count 0 2006.257.18:33:15.85#ibcon#about to write, iclass 19, count 0 2006.257.18:33:15.85#ibcon#wrote, iclass 19, count 0 2006.257.18:33:15.85#ibcon#about to read 3, iclass 19, count 0 2006.257.18:33:15.88#ibcon#read 3, iclass 19, count 0 2006.257.18:33:15.88#ibcon#about to read 4, iclass 19, count 0 2006.257.18:33:15.88#ibcon#read 4, iclass 19, count 0 2006.257.18:33:15.88#ibcon#about to read 5, iclass 19, count 0 2006.257.18:33:15.88#ibcon#read 5, iclass 19, count 0 2006.257.18:33:15.88#ibcon#about to read 6, iclass 19, count 0 2006.257.18:33:15.88#ibcon#read 6, iclass 19, count 0 2006.257.18:33:15.88#ibcon#end of sib2, iclass 19, count 0 2006.257.18:33:15.88#ibcon#*after write, iclass 19, count 0 2006.257.18:33:15.88#ibcon#*before return 0, iclass 19, count 0 2006.257.18:33:15.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:15.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:15.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:33:15.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:33:15.88$vck44/valo=8,884.99 2006.257.18:33:15.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.18:33:15.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.18:33:15.88#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:15.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:15.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:15.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:15.88#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:33:15.88#ibcon#first serial, iclass 21, count 0 2006.257.18:33:15.88#ibcon#enter sib2, iclass 21, count 0 2006.257.18:33:15.88#ibcon#flushed, iclass 21, count 0 2006.257.18:33:15.88#ibcon#about to write, iclass 21, count 0 2006.257.18:33:15.88#ibcon#wrote, iclass 21, count 0 2006.257.18:33:15.88#ibcon#about to read 3, iclass 21, count 0 2006.257.18:33:15.90#ibcon#read 3, iclass 21, count 0 2006.257.18:33:15.90#ibcon#about to read 4, iclass 21, count 0 2006.257.18:33:15.90#ibcon#read 4, iclass 21, count 0 2006.257.18:33:15.90#ibcon#about to read 5, iclass 21, count 0 2006.257.18:33:15.90#ibcon#read 5, iclass 21, count 0 2006.257.18:33:15.90#ibcon#about to read 6, iclass 21, count 0 2006.257.18:33:15.90#ibcon#read 6, iclass 21, count 0 2006.257.18:33:15.90#ibcon#end of sib2, iclass 21, count 0 2006.257.18:33:15.90#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:33:15.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:33:15.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:33:15.90#ibcon#*before write, iclass 21, count 0 2006.257.18:33:15.90#ibcon#enter sib2, iclass 21, count 0 2006.257.18:33:15.90#ibcon#flushed, iclass 21, count 0 2006.257.18:33:15.90#ibcon#about to write, iclass 21, count 0 2006.257.18:33:15.90#ibcon#wrote, iclass 21, count 0 2006.257.18:33:15.90#ibcon#about to read 3, iclass 21, count 0 2006.257.18:33:15.94#ibcon#read 3, iclass 21, count 0 2006.257.18:33:15.94#ibcon#about to read 4, iclass 21, count 0 2006.257.18:33:15.94#ibcon#read 4, iclass 21, count 0 2006.257.18:33:15.94#ibcon#about to read 5, iclass 21, count 0 2006.257.18:33:15.94#ibcon#read 5, iclass 21, count 0 2006.257.18:33:15.94#ibcon#about to read 6, iclass 21, count 0 2006.257.18:33:15.94#ibcon#read 6, iclass 21, count 0 2006.257.18:33:15.94#ibcon#end of sib2, iclass 21, count 0 2006.257.18:33:15.94#ibcon#*after write, iclass 21, count 0 2006.257.18:33:15.94#ibcon#*before return 0, iclass 21, count 0 2006.257.18:33:15.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:15.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:15.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:33:15.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:33:15.94$vck44/va=8,4 2006.257.18:33:15.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.18:33:15.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.18:33:15.94#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:15.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:33:16.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:33:16.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:33:16.00#ibcon#enter wrdev, iclass 23, count 2 2006.257.18:33:16.00#ibcon#first serial, iclass 23, count 2 2006.257.18:33:16.00#ibcon#enter sib2, iclass 23, count 2 2006.257.18:33:16.00#ibcon#flushed, iclass 23, count 2 2006.257.18:33:16.00#ibcon#about to write, iclass 23, count 2 2006.257.18:33:16.00#ibcon#wrote, iclass 23, count 2 2006.257.18:33:16.00#ibcon#about to read 3, iclass 23, count 2 2006.257.18:33:16.02#ibcon#read 3, iclass 23, count 2 2006.257.18:33:16.02#ibcon#about to read 4, iclass 23, count 2 2006.257.18:33:16.02#ibcon#read 4, iclass 23, count 2 2006.257.18:33:16.02#ibcon#about to read 5, iclass 23, count 2 2006.257.18:33:16.02#ibcon#read 5, iclass 23, count 2 2006.257.18:33:16.02#ibcon#about to read 6, iclass 23, count 2 2006.257.18:33:16.02#ibcon#read 6, iclass 23, count 2 2006.257.18:33:16.02#ibcon#end of sib2, iclass 23, count 2 2006.257.18:33:16.02#ibcon#*mode == 0, iclass 23, count 2 2006.257.18:33:16.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.18:33:16.02#ibcon#[25=AT08-04\r\n] 2006.257.18:33:16.02#ibcon#*before write, iclass 23, count 2 2006.257.18:33:16.02#ibcon#enter sib2, iclass 23, count 2 2006.257.18:33:16.02#ibcon#flushed, iclass 23, count 2 2006.257.18:33:16.02#ibcon#about to write, iclass 23, count 2 2006.257.18:33:16.02#ibcon#wrote, iclass 23, count 2 2006.257.18:33:16.02#ibcon#about to read 3, iclass 23, count 2 2006.257.18:33:16.05#ibcon#read 3, iclass 23, count 2 2006.257.18:33:16.05#ibcon#about to read 4, iclass 23, count 2 2006.257.18:33:16.05#ibcon#read 4, iclass 23, count 2 2006.257.18:33:16.05#ibcon#about to read 5, iclass 23, count 2 2006.257.18:33:16.05#ibcon#read 5, iclass 23, count 2 2006.257.18:33:16.05#ibcon#about to read 6, iclass 23, count 2 2006.257.18:33:16.05#ibcon#read 6, iclass 23, count 2 2006.257.18:33:16.05#ibcon#end of sib2, iclass 23, count 2 2006.257.18:33:16.05#ibcon#*after write, iclass 23, count 2 2006.257.18:33:16.05#ibcon#*before return 0, iclass 23, count 2 2006.257.18:33:16.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:33:16.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:33:16.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.18:33:16.05#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:16.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:33:16.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:33:16.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:33:16.17#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:33:16.17#ibcon#first serial, iclass 23, count 0 2006.257.18:33:16.17#ibcon#enter sib2, iclass 23, count 0 2006.257.18:33:16.17#ibcon#flushed, iclass 23, count 0 2006.257.18:33:16.17#ibcon#about to write, iclass 23, count 0 2006.257.18:33:16.17#ibcon#wrote, iclass 23, count 0 2006.257.18:33:16.17#ibcon#about to read 3, iclass 23, count 0 2006.257.18:33:16.19#ibcon#read 3, iclass 23, count 0 2006.257.18:33:16.19#ibcon#about to read 4, iclass 23, count 0 2006.257.18:33:16.19#ibcon#read 4, iclass 23, count 0 2006.257.18:33:16.19#ibcon#about to read 5, iclass 23, count 0 2006.257.18:33:16.19#ibcon#read 5, iclass 23, count 0 2006.257.18:33:16.19#ibcon#about to read 6, iclass 23, count 0 2006.257.18:33:16.19#ibcon#read 6, iclass 23, count 0 2006.257.18:33:16.19#ibcon#end of sib2, iclass 23, count 0 2006.257.18:33:16.19#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:33:16.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:33:16.19#ibcon#[25=USB\r\n] 2006.257.18:33:16.19#ibcon#*before write, iclass 23, count 0 2006.257.18:33:16.19#ibcon#enter sib2, iclass 23, count 0 2006.257.18:33:16.19#ibcon#flushed, iclass 23, count 0 2006.257.18:33:16.19#ibcon#about to write, iclass 23, count 0 2006.257.18:33:16.19#ibcon#wrote, iclass 23, count 0 2006.257.18:33:16.19#ibcon#about to read 3, iclass 23, count 0 2006.257.18:33:16.22#ibcon#read 3, iclass 23, count 0 2006.257.18:33:16.22#ibcon#about to read 4, iclass 23, count 0 2006.257.18:33:16.22#ibcon#read 4, iclass 23, count 0 2006.257.18:33:16.22#ibcon#about to read 5, iclass 23, count 0 2006.257.18:33:16.22#ibcon#read 5, iclass 23, count 0 2006.257.18:33:16.22#ibcon#about to read 6, iclass 23, count 0 2006.257.18:33:16.22#ibcon#read 6, iclass 23, count 0 2006.257.18:33:16.22#ibcon#end of sib2, iclass 23, count 0 2006.257.18:33:16.22#ibcon#*after write, iclass 23, count 0 2006.257.18:33:16.22#ibcon#*before return 0, iclass 23, count 0 2006.257.18:33:16.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:33:16.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:33:16.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:33:16.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:33:16.22$vck44/vblo=1,629.99 2006.257.18:33:16.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.18:33:16.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.18:33:16.22#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:16.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:16.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:16.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:16.22#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:33:16.22#ibcon#first serial, iclass 25, count 0 2006.257.18:33:16.22#ibcon#enter sib2, iclass 25, count 0 2006.257.18:33:16.22#ibcon#flushed, iclass 25, count 0 2006.257.18:33:16.22#ibcon#about to write, iclass 25, count 0 2006.257.18:33:16.22#ibcon#wrote, iclass 25, count 0 2006.257.18:33:16.22#ibcon#about to read 3, iclass 25, count 0 2006.257.18:33:16.24#ibcon#read 3, iclass 25, count 0 2006.257.18:33:16.24#ibcon#about to read 4, iclass 25, count 0 2006.257.18:33:16.24#ibcon#read 4, iclass 25, count 0 2006.257.18:33:16.24#ibcon#about to read 5, iclass 25, count 0 2006.257.18:33:16.24#ibcon#read 5, iclass 25, count 0 2006.257.18:33:16.24#ibcon#about to read 6, iclass 25, count 0 2006.257.18:33:16.24#ibcon#read 6, iclass 25, count 0 2006.257.18:33:16.24#ibcon#end of sib2, iclass 25, count 0 2006.257.18:33:16.24#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:33:16.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:33:16.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:33:16.24#ibcon#*before write, iclass 25, count 0 2006.257.18:33:16.24#ibcon#enter sib2, iclass 25, count 0 2006.257.18:33:16.24#ibcon#flushed, iclass 25, count 0 2006.257.18:33:16.24#ibcon#about to write, iclass 25, count 0 2006.257.18:33:16.24#ibcon#wrote, iclass 25, count 0 2006.257.18:33:16.24#ibcon#about to read 3, iclass 25, count 0 2006.257.18:33:16.28#ibcon#read 3, iclass 25, count 0 2006.257.18:33:16.28#ibcon#about to read 4, iclass 25, count 0 2006.257.18:33:16.28#ibcon#read 4, iclass 25, count 0 2006.257.18:33:16.28#ibcon#about to read 5, iclass 25, count 0 2006.257.18:33:16.28#ibcon#read 5, iclass 25, count 0 2006.257.18:33:16.28#ibcon#about to read 6, iclass 25, count 0 2006.257.18:33:16.28#ibcon#read 6, iclass 25, count 0 2006.257.18:33:16.28#ibcon#end of sib2, iclass 25, count 0 2006.257.18:33:16.28#ibcon#*after write, iclass 25, count 0 2006.257.18:33:16.28#ibcon#*before return 0, iclass 25, count 0 2006.257.18:33:16.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:16.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:33:16.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:33:16.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:33:16.28$vck44/vb=1,4 2006.257.18:33:16.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.18:33:16.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.18:33:16.28#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:16.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:16.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:16.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:16.28#ibcon#enter wrdev, iclass 27, count 2 2006.257.18:33:16.28#ibcon#first serial, iclass 27, count 2 2006.257.18:33:16.28#ibcon#enter sib2, iclass 27, count 2 2006.257.18:33:16.28#ibcon#flushed, iclass 27, count 2 2006.257.18:33:16.28#ibcon#about to write, iclass 27, count 2 2006.257.18:33:16.28#ibcon#wrote, iclass 27, count 2 2006.257.18:33:16.28#ibcon#about to read 3, iclass 27, count 2 2006.257.18:33:16.30#ibcon#read 3, iclass 27, count 2 2006.257.18:33:16.30#ibcon#about to read 4, iclass 27, count 2 2006.257.18:33:16.30#ibcon#read 4, iclass 27, count 2 2006.257.18:33:16.30#ibcon#about to read 5, iclass 27, count 2 2006.257.18:33:16.30#ibcon#read 5, iclass 27, count 2 2006.257.18:33:16.30#ibcon#about to read 6, iclass 27, count 2 2006.257.18:33:16.30#ibcon#read 6, iclass 27, count 2 2006.257.18:33:16.30#ibcon#end of sib2, iclass 27, count 2 2006.257.18:33:16.30#ibcon#*mode == 0, iclass 27, count 2 2006.257.18:33:16.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.18:33:16.30#ibcon#[27=AT01-04\r\n] 2006.257.18:33:16.30#ibcon#*before write, iclass 27, count 2 2006.257.18:33:16.30#ibcon#enter sib2, iclass 27, count 2 2006.257.18:33:16.30#ibcon#flushed, iclass 27, count 2 2006.257.18:33:16.30#ibcon#about to write, iclass 27, count 2 2006.257.18:33:16.30#ibcon#wrote, iclass 27, count 2 2006.257.18:33:16.30#ibcon#about to read 3, iclass 27, count 2 2006.257.18:33:16.33#ibcon#read 3, iclass 27, count 2 2006.257.18:33:16.33#ibcon#about to read 4, iclass 27, count 2 2006.257.18:33:16.33#ibcon#read 4, iclass 27, count 2 2006.257.18:33:16.33#ibcon#about to read 5, iclass 27, count 2 2006.257.18:33:16.33#ibcon#read 5, iclass 27, count 2 2006.257.18:33:16.33#ibcon#about to read 6, iclass 27, count 2 2006.257.18:33:16.33#ibcon#read 6, iclass 27, count 2 2006.257.18:33:16.33#ibcon#end of sib2, iclass 27, count 2 2006.257.18:33:16.33#ibcon#*after write, iclass 27, count 2 2006.257.18:33:16.33#ibcon#*before return 0, iclass 27, count 2 2006.257.18:33:16.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:16.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:33:16.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.18:33:16.33#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:16.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:16.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:16.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:16.45#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:33:16.45#ibcon#first serial, iclass 27, count 0 2006.257.18:33:16.45#ibcon#enter sib2, iclass 27, count 0 2006.257.18:33:16.45#ibcon#flushed, iclass 27, count 0 2006.257.18:33:16.45#ibcon#about to write, iclass 27, count 0 2006.257.18:33:16.45#ibcon#wrote, iclass 27, count 0 2006.257.18:33:16.45#ibcon#about to read 3, iclass 27, count 0 2006.257.18:33:16.47#ibcon#read 3, iclass 27, count 0 2006.257.18:33:16.47#ibcon#about to read 4, iclass 27, count 0 2006.257.18:33:16.47#ibcon#read 4, iclass 27, count 0 2006.257.18:33:16.47#ibcon#about to read 5, iclass 27, count 0 2006.257.18:33:16.47#ibcon#read 5, iclass 27, count 0 2006.257.18:33:16.47#ibcon#about to read 6, iclass 27, count 0 2006.257.18:33:16.47#ibcon#read 6, iclass 27, count 0 2006.257.18:33:16.47#ibcon#end of sib2, iclass 27, count 0 2006.257.18:33:16.47#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:33:16.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:33:16.47#ibcon#[27=USB\r\n] 2006.257.18:33:16.47#ibcon#*before write, iclass 27, count 0 2006.257.18:33:16.47#ibcon#enter sib2, iclass 27, count 0 2006.257.18:33:16.47#ibcon#flushed, iclass 27, count 0 2006.257.18:33:16.47#ibcon#about to write, iclass 27, count 0 2006.257.18:33:16.47#ibcon#wrote, iclass 27, count 0 2006.257.18:33:16.47#ibcon#about to read 3, iclass 27, count 0 2006.257.18:33:16.50#ibcon#read 3, iclass 27, count 0 2006.257.18:33:16.50#ibcon#about to read 4, iclass 27, count 0 2006.257.18:33:16.50#ibcon#read 4, iclass 27, count 0 2006.257.18:33:16.50#ibcon#about to read 5, iclass 27, count 0 2006.257.18:33:16.50#ibcon#read 5, iclass 27, count 0 2006.257.18:33:16.50#ibcon#about to read 6, iclass 27, count 0 2006.257.18:33:16.50#ibcon#read 6, iclass 27, count 0 2006.257.18:33:16.50#ibcon#end of sib2, iclass 27, count 0 2006.257.18:33:16.50#ibcon#*after write, iclass 27, count 0 2006.257.18:33:16.50#ibcon#*before return 0, iclass 27, count 0 2006.257.18:33:16.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:16.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:33:16.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:33:16.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:33:16.50$vck44/vblo=2,634.99 2006.257.18:33:16.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.18:33:16.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.18:33:16.50#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:16.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:16.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:16.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:16.50#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:33:16.50#ibcon#first serial, iclass 29, count 0 2006.257.18:33:16.50#ibcon#enter sib2, iclass 29, count 0 2006.257.18:33:16.50#ibcon#flushed, iclass 29, count 0 2006.257.18:33:16.50#ibcon#about to write, iclass 29, count 0 2006.257.18:33:16.50#ibcon#wrote, iclass 29, count 0 2006.257.18:33:16.50#ibcon#about to read 3, iclass 29, count 0 2006.257.18:33:16.52#ibcon#read 3, iclass 29, count 0 2006.257.18:33:16.52#ibcon#about to read 4, iclass 29, count 0 2006.257.18:33:16.52#ibcon#read 4, iclass 29, count 0 2006.257.18:33:16.52#ibcon#about to read 5, iclass 29, count 0 2006.257.18:33:16.52#ibcon#read 5, iclass 29, count 0 2006.257.18:33:16.52#ibcon#about to read 6, iclass 29, count 0 2006.257.18:33:16.52#ibcon#read 6, iclass 29, count 0 2006.257.18:33:16.52#ibcon#end of sib2, iclass 29, count 0 2006.257.18:33:16.52#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:33:16.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:33:16.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:33:16.52#ibcon#*before write, iclass 29, count 0 2006.257.18:33:16.52#ibcon#enter sib2, iclass 29, count 0 2006.257.18:33:16.52#ibcon#flushed, iclass 29, count 0 2006.257.18:33:16.52#ibcon#about to write, iclass 29, count 0 2006.257.18:33:16.52#ibcon#wrote, iclass 29, count 0 2006.257.18:33:16.52#ibcon#about to read 3, iclass 29, count 0 2006.257.18:33:16.56#ibcon#read 3, iclass 29, count 0 2006.257.18:33:16.56#ibcon#about to read 4, iclass 29, count 0 2006.257.18:33:16.56#ibcon#read 4, iclass 29, count 0 2006.257.18:33:16.56#ibcon#about to read 5, iclass 29, count 0 2006.257.18:33:16.56#ibcon#read 5, iclass 29, count 0 2006.257.18:33:16.56#ibcon#about to read 6, iclass 29, count 0 2006.257.18:33:16.56#ibcon#read 6, iclass 29, count 0 2006.257.18:33:16.56#ibcon#end of sib2, iclass 29, count 0 2006.257.18:33:16.56#ibcon#*after write, iclass 29, count 0 2006.257.18:33:16.56#ibcon#*before return 0, iclass 29, count 0 2006.257.18:33:16.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:16.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:33:16.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:33:16.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:33:16.56$vck44/vb=2,5 2006.257.18:33:16.56#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.18:33:16.56#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.18:33:16.56#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:16.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:16.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:16.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:16.62#ibcon#enter wrdev, iclass 31, count 2 2006.257.18:33:16.62#ibcon#first serial, iclass 31, count 2 2006.257.18:33:16.62#ibcon#enter sib2, iclass 31, count 2 2006.257.18:33:16.62#ibcon#flushed, iclass 31, count 2 2006.257.18:33:16.62#ibcon#about to write, iclass 31, count 2 2006.257.18:33:16.62#ibcon#wrote, iclass 31, count 2 2006.257.18:33:16.62#ibcon#about to read 3, iclass 31, count 2 2006.257.18:33:16.64#ibcon#read 3, iclass 31, count 2 2006.257.18:33:16.64#ibcon#about to read 4, iclass 31, count 2 2006.257.18:33:16.64#ibcon#read 4, iclass 31, count 2 2006.257.18:33:16.64#ibcon#about to read 5, iclass 31, count 2 2006.257.18:33:16.64#ibcon#read 5, iclass 31, count 2 2006.257.18:33:16.64#ibcon#about to read 6, iclass 31, count 2 2006.257.18:33:16.64#ibcon#read 6, iclass 31, count 2 2006.257.18:33:16.64#ibcon#end of sib2, iclass 31, count 2 2006.257.18:33:16.64#ibcon#*mode == 0, iclass 31, count 2 2006.257.18:33:16.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.18:33:16.64#ibcon#[27=AT02-05\r\n] 2006.257.18:33:16.64#ibcon#*before write, iclass 31, count 2 2006.257.18:33:16.64#ibcon#enter sib2, iclass 31, count 2 2006.257.18:33:16.64#ibcon#flushed, iclass 31, count 2 2006.257.18:33:16.64#ibcon#about to write, iclass 31, count 2 2006.257.18:33:16.64#ibcon#wrote, iclass 31, count 2 2006.257.18:33:16.64#ibcon#about to read 3, iclass 31, count 2 2006.257.18:33:16.67#ibcon#read 3, iclass 31, count 2 2006.257.18:33:16.67#ibcon#about to read 4, iclass 31, count 2 2006.257.18:33:16.67#ibcon#read 4, iclass 31, count 2 2006.257.18:33:16.67#ibcon#about to read 5, iclass 31, count 2 2006.257.18:33:16.67#ibcon#read 5, iclass 31, count 2 2006.257.18:33:16.67#ibcon#about to read 6, iclass 31, count 2 2006.257.18:33:16.67#ibcon#read 6, iclass 31, count 2 2006.257.18:33:16.67#ibcon#end of sib2, iclass 31, count 2 2006.257.18:33:16.67#ibcon#*after write, iclass 31, count 2 2006.257.18:33:16.67#ibcon#*before return 0, iclass 31, count 2 2006.257.18:33:16.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:16.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:33:16.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.18:33:16.67#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:16.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:16.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:16.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:16.79#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:33:16.79#ibcon#first serial, iclass 31, count 0 2006.257.18:33:16.79#ibcon#enter sib2, iclass 31, count 0 2006.257.18:33:16.79#ibcon#flushed, iclass 31, count 0 2006.257.18:33:16.79#ibcon#about to write, iclass 31, count 0 2006.257.18:33:16.79#ibcon#wrote, iclass 31, count 0 2006.257.18:33:16.79#ibcon#about to read 3, iclass 31, count 0 2006.257.18:33:16.81#ibcon#read 3, iclass 31, count 0 2006.257.18:33:16.81#ibcon#about to read 4, iclass 31, count 0 2006.257.18:33:16.81#ibcon#read 4, iclass 31, count 0 2006.257.18:33:16.81#ibcon#about to read 5, iclass 31, count 0 2006.257.18:33:16.81#ibcon#read 5, iclass 31, count 0 2006.257.18:33:16.81#ibcon#about to read 6, iclass 31, count 0 2006.257.18:33:16.81#ibcon#read 6, iclass 31, count 0 2006.257.18:33:16.81#ibcon#end of sib2, iclass 31, count 0 2006.257.18:33:16.81#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:33:16.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:33:16.81#ibcon#[27=USB\r\n] 2006.257.18:33:16.81#ibcon#*before write, iclass 31, count 0 2006.257.18:33:16.81#ibcon#enter sib2, iclass 31, count 0 2006.257.18:33:16.81#ibcon#flushed, iclass 31, count 0 2006.257.18:33:16.81#ibcon#about to write, iclass 31, count 0 2006.257.18:33:16.81#ibcon#wrote, iclass 31, count 0 2006.257.18:33:16.81#ibcon#about to read 3, iclass 31, count 0 2006.257.18:33:16.84#ibcon#read 3, iclass 31, count 0 2006.257.18:33:16.84#ibcon#about to read 4, iclass 31, count 0 2006.257.18:33:16.84#ibcon#read 4, iclass 31, count 0 2006.257.18:33:16.84#ibcon#about to read 5, iclass 31, count 0 2006.257.18:33:16.84#ibcon#read 5, iclass 31, count 0 2006.257.18:33:16.84#ibcon#about to read 6, iclass 31, count 0 2006.257.18:33:16.84#ibcon#read 6, iclass 31, count 0 2006.257.18:33:16.84#ibcon#end of sib2, iclass 31, count 0 2006.257.18:33:16.84#ibcon#*after write, iclass 31, count 0 2006.257.18:33:16.84#ibcon#*before return 0, iclass 31, count 0 2006.257.18:33:16.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:16.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:33:16.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:33:16.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:33:16.84$vck44/vblo=3,649.99 2006.257.18:33:16.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.18:33:16.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.18:33:16.84#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:16.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:33:16.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:33:16.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:33:16.84#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:33:16.84#ibcon#first serial, iclass 33, count 0 2006.257.18:33:16.84#ibcon#enter sib2, iclass 33, count 0 2006.257.18:33:16.84#ibcon#flushed, iclass 33, count 0 2006.257.18:33:16.84#ibcon#about to write, iclass 33, count 0 2006.257.18:33:16.84#ibcon#wrote, iclass 33, count 0 2006.257.18:33:16.84#ibcon#about to read 3, iclass 33, count 0 2006.257.18:33:16.86#ibcon#read 3, iclass 33, count 0 2006.257.18:33:16.86#ibcon#about to read 4, iclass 33, count 0 2006.257.18:33:16.86#ibcon#read 4, iclass 33, count 0 2006.257.18:33:16.86#ibcon#about to read 5, iclass 33, count 0 2006.257.18:33:16.86#ibcon#read 5, iclass 33, count 0 2006.257.18:33:16.86#ibcon#about to read 6, iclass 33, count 0 2006.257.18:33:16.86#ibcon#read 6, iclass 33, count 0 2006.257.18:33:16.86#ibcon#end of sib2, iclass 33, count 0 2006.257.18:33:16.86#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:33:16.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:33:16.86#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:33:16.86#ibcon#*before write, iclass 33, count 0 2006.257.18:33:16.86#ibcon#enter sib2, iclass 33, count 0 2006.257.18:33:16.86#ibcon#flushed, iclass 33, count 0 2006.257.18:33:16.86#ibcon#about to write, iclass 33, count 0 2006.257.18:33:16.86#ibcon#wrote, iclass 33, count 0 2006.257.18:33:16.86#ibcon#about to read 3, iclass 33, count 0 2006.257.18:33:16.90#ibcon#read 3, iclass 33, count 0 2006.257.18:33:16.90#ibcon#about to read 4, iclass 33, count 0 2006.257.18:33:16.90#ibcon#read 4, iclass 33, count 0 2006.257.18:33:16.90#ibcon#about to read 5, iclass 33, count 0 2006.257.18:33:16.90#ibcon#read 5, iclass 33, count 0 2006.257.18:33:16.90#ibcon#about to read 6, iclass 33, count 0 2006.257.18:33:16.90#ibcon#read 6, iclass 33, count 0 2006.257.18:33:16.90#ibcon#end of sib2, iclass 33, count 0 2006.257.18:33:16.90#ibcon#*after write, iclass 33, count 0 2006.257.18:33:16.90#ibcon#*before return 0, iclass 33, count 0 2006.257.18:33:16.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:33:16.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:33:16.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:33:16.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:33:16.90$vck44/vb=3,4 2006.257.18:33:16.90#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.18:33:16.90#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.18:33:16.90#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:16.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:33:16.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:33:16.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:33:16.96#ibcon#enter wrdev, iclass 35, count 2 2006.257.18:33:16.96#ibcon#first serial, iclass 35, count 2 2006.257.18:33:16.96#ibcon#enter sib2, iclass 35, count 2 2006.257.18:33:16.96#ibcon#flushed, iclass 35, count 2 2006.257.18:33:16.96#ibcon#about to write, iclass 35, count 2 2006.257.18:33:16.96#ibcon#wrote, iclass 35, count 2 2006.257.18:33:16.96#ibcon#about to read 3, iclass 35, count 2 2006.257.18:33:16.98#ibcon#read 3, iclass 35, count 2 2006.257.18:33:16.98#ibcon#about to read 4, iclass 35, count 2 2006.257.18:33:16.98#ibcon#read 4, iclass 35, count 2 2006.257.18:33:16.98#ibcon#about to read 5, iclass 35, count 2 2006.257.18:33:16.98#ibcon#read 5, iclass 35, count 2 2006.257.18:33:16.98#ibcon#about to read 6, iclass 35, count 2 2006.257.18:33:16.98#ibcon#read 6, iclass 35, count 2 2006.257.18:33:16.98#ibcon#end of sib2, iclass 35, count 2 2006.257.18:33:16.98#ibcon#*mode == 0, iclass 35, count 2 2006.257.18:33:16.98#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.18:33:16.98#ibcon#[27=AT03-04\r\n] 2006.257.18:33:16.98#ibcon#*before write, iclass 35, count 2 2006.257.18:33:16.98#ibcon#enter sib2, iclass 35, count 2 2006.257.18:33:16.98#ibcon#flushed, iclass 35, count 2 2006.257.18:33:16.98#ibcon#about to write, iclass 35, count 2 2006.257.18:33:16.98#ibcon#wrote, iclass 35, count 2 2006.257.18:33:16.98#ibcon#about to read 3, iclass 35, count 2 2006.257.18:33:17.01#ibcon#read 3, iclass 35, count 2 2006.257.18:33:17.01#ibcon#about to read 4, iclass 35, count 2 2006.257.18:33:17.01#ibcon#read 4, iclass 35, count 2 2006.257.18:33:17.01#ibcon#about to read 5, iclass 35, count 2 2006.257.18:33:17.01#ibcon#read 5, iclass 35, count 2 2006.257.18:33:17.01#ibcon#about to read 6, iclass 35, count 2 2006.257.18:33:17.01#ibcon#read 6, iclass 35, count 2 2006.257.18:33:17.01#ibcon#end of sib2, iclass 35, count 2 2006.257.18:33:17.01#ibcon#*after write, iclass 35, count 2 2006.257.18:33:17.01#ibcon#*before return 0, iclass 35, count 2 2006.257.18:33:17.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:33:17.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:33:17.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.18:33:17.01#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:17.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:33:17.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:33:17.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:33:17.13#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:33:17.13#ibcon#first serial, iclass 35, count 0 2006.257.18:33:17.13#ibcon#enter sib2, iclass 35, count 0 2006.257.18:33:17.13#ibcon#flushed, iclass 35, count 0 2006.257.18:33:17.13#ibcon#about to write, iclass 35, count 0 2006.257.18:33:17.13#ibcon#wrote, iclass 35, count 0 2006.257.18:33:17.13#ibcon#about to read 3, iclass 35, count 0 2006.257.18:33:17.15#ibcon#read 3, iclass 35, count 0 2006.257.18:33:17.15#ibcon#about to read 4, iclass 35, count 0 2006.257.18:33:17.15#ibcon#read 4, iclass 35, count 0 2006.257.18:33:17.15#ibcon#about to read 5, iclass 35, count 0 2006.257.18:33:17.15#ibcon#read 5, iclass 35, count 0 2006.257.18:33:17.15#ibcon#about to read 6, iclass 35, count 0 2006.257.18:33:17.15#ibcon#read 6, iclass 35, count 0 2006.257.18:33:17.15#ibcon#end of sib2, iclass 35, count 0 2006.257.18:33:17.15#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:33:17.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:33:17.15#ibcon#[27=USB\r\n] 2006.257.18:33:17.15#ibcon#*before write, iclass 35, count 0 2006.257.18:33:17.15#ibcon#enter sib2, iclass 35, count 0 2006.257.18:33:17.15#ibcon#flushed, iclass 35, count 0 2006.257.18:33:17.15#ibcon#about to write, iclass 35, count 0 2006.257.18:33:17.15#ibcon#wrote, iclass 35, count 0 2006.257.18:33:17.15#ibcon#about to read 3, iclass 35, count 0 2006.257.18:33:17.18#ibcon#read 3, iclass 35, count 0 2006.257.18:33:17.18#ibcon#about to read 4, iclass 35, count 0 2006.257.18:33:17.18#ibcon#read 4, iclass 35, count 0 2006.257.18:33:17.18#ibcon#about to read 5, iclass 35, count 0 2006.257.18:33:17.18#ibcon#read 5, iclass 35, count 0 2006.257.18:33:17.18#ibcon#about to read 6, iclass 35, count 0 2006.257.18:33:17.18#ibcon#read 6, iclass 35, count 0 2006.257.18:33:17.18#ibcon#end of sib2, iclass 35, count 0 2006.257.18:33:17.18#ibcon#*after write, iclass 35, count 0 2006.257.18:33:17.18#ibcon#*before return 0, iclass 35, count 0 2006.257.18:33:17.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:33:17.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:33:17.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:33:17.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:33:17.18$vck44/vblo=4,679.99 2006.257.18:33:17.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.18:33:17.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.18:33:17.18#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:17.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:17.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:17.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:17.18#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:33:17.18#ibcon#first serial, iclass 37, count 0 2006.257.18:33:17.18#ibcon#enter sib2, iclass 37, count 0 2006.257.18:33:17.18#ibcon#flushed, iclass 37, count 0 2006.257.18:33:17.18#ibcon#about to write, iclass 37, count 0 2006.257.18:33:17.18#ibcon#wrote, iclass 37, count 0 2006.257.18:33:17.18#ibcon#about to read 3, iclass 37, count 0 2006.257.18:33:17.20#ibcon#read 3, iclass 37, count 0 2006.257.18:33:17.20#ibcon#about to read 4, iclass 37, count 0 2006.257.18:33:17.20#ibcon#read 4, iclass 37, count 0 2006.257.18:33:17.20#ibcon#about to read 5, iclass 37, count 0 2006.257.18:33:17.20#ibcon#read 5, iclass 37, count 0 2006.257.18:33:17.20#ibcon#about to read 6, iclass 37, count 0 2006.257.18:33:17.20#ibcon#read 6, iclass 37, count 0 2006.257.18:33:17.20#ibcon#end of sib2, iclass 37, count 0 2006.257.18:33:17.20#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:33:17.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:33:17.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:33:17.20#ibcon#*before write, iclass 37, count 0 2006.257.18:33:17.20#ibcon#enter sib2, iclass 37, count 0 2006.257.18:33:17.20#ibcon#flushed, iclass 37, count 0 2006.257.18:33:17.20#ibcon#about to write, iclass 37, count 0 2006.257.18:33:17.20#ibcon#wrote, iclass 37, count 0 2006.257.18:33:17.20#ibcon#about to read 3, iclass 37, count 0 2006.257.18:33:17.24#ibcon#read 3, iclass 37, count 0 2006.257.18:33:17.24#ibcon#about to read 4, iclass 37, count 0 2006.257.18:33:17.24#ibcon#read 4, iclass 37, count 0 2006.257.18:33:17.24#ibcon#about to read 5, iclass 37, count 0 2006.257.18:33:17.24#ibcon#read 5, iclass 37, count 0 2006.257.18:33:17.24#ibcon#about to read 6, iclass 37, count 0 2006.257.18:33:17.24#ibcon#read 6, iclass 37, count 0 2006.257.18:33:17.24#ibcon#end of sib2, iclass 37, count 0 2006.257.18:33:17.24#ibcon#*after write, iclass 37, count 0 2006.257.18:33:17.24#ibcon#*before return 0, iclass 37, count 0 2006.257.18:33:17.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:17.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:33:17.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:33:17.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:33:17.24$vck44/vb=4,5 2006.257.18:33:17.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.18:33:17.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.18:33:17.24#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:17.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:17.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:17.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:17.30#ibcon#enter wrdev, iclass 39, count 2 2006.257.18:33:17.30#ibcon#first serial, iclass 39, count 2 2006.257.18:33:17.30#ibcon#enter sib2, iclass 39, count 2 2006.257.18:33:17.30#ibcon#flushed, iclass 39, count 2 2006.257.18:33:17.30#ibcon#about to write, iclass 39, count 2 2006.257.18:33:17.30#ibcon#wrote, iclass 39, count 2 2006.257.18:33:17.30#ibcon#about to read 3, iclass 39, count 2 2006.257.18:33:17.32#ibcon#read 3, iclass 39, count 2 2006.257.18:33:17.32#ibcon#about to read 4, iclass 39, count 2 2006.257.18:33:17.32#ibcon#read 4, iclass 39, count 2 2006.257.18:33:17.32#ibcon#about to read 5, iclass 39, count 2 2006.257.18:33:17.32#ibcon#read 5, iclass 39, count 2 2006.257.18:33:17.32#ibcon#about to read 6, iclass 39, count 2 2006.257.18:33:17.32#ibcon#read 6, iclass 39, count 2 2006.257.18:33:17.32#ibcon#end of sib2, iclass 39, count 2 2006.257.18:33:17.32#ibcon#*mode == 0, iclass 39, count 2 2006.257.18:33:17.32#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.18:33:17.32#ibcon#[27=AT04-05\r\n] 2006.257.18:33:17.32#ibcon#*before write, iclass 39, count 2 2006.257.18:33:17.32#ibcon#enter sib2, iclass 39, count 2 2006.257.18:33:17.32#ibcon#flushed, iclass 39, count 2 2006.257.18:33:17.32#ibcon#about to write, iclass 39, count 2 2006.257.18:33:17.32#ibcon#wrote, iclass 39, count 2 2006.257.18:33:17.32#ibcon#about to read 3, iclass 39, count 2 2006.257.18:33:17.35#ibcon#read 3, iclass 39, count 2 2006.257.18:33:17.35#ibcon#about to read 4, iclass 39, count 2 2006.257.18:33:17.35#ibcon#read 4, iclass 39, count 2 2006.257.18:33:17.35#ibcon#about to read 5, iclass 39, count 2 2006.257.18:33:17.35#ibcon#read 5, iclass 39, count 2 2006.257.18:33:17.35#ibcon#about to read 6, iclass 39, count 2 2006.257.18:33:17.35#ibcon#read 6, iclass 39, count 2 2006.257.18:33:17.35#ibcon#end of sib2, iclass 39, count 2 2006.257.18:33:17.35#ibcon#*after write, iclass 39, count 2 2006.257.18:33:17.35#ibcon#*before return 0, iclass 39, count 2 2006.257.18:33:17.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:17.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:33:17.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.18:33:17.35#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:17.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:17.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:17.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:17.47#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:33:17.47#ibcon#first serial, iclass 39, count 0 2006.257.18:33:17.47#ibcon#enter sib2, iclass 39, count 0 2006.257.18:33:17.47#ibcon#flushed, iclass 39, count 0 2006.257.18:33:17.47#ibcon#about to write, iclass 39, count 0 2006.257.18:33:17.47#ibcon#wrote, iclass 39, count 0 2006.257.18:33:17.47#ibcon#about to read 3, iclass 39, count 0 2006.257.18:33:17.49#ibcon#read 3, iclass 39, count 0 2006.257.18:33:17.49#ibcon#about to read 4, iclass 39, count 0 2006.257.18:33:17.49#ibcon#read 4, iclass 39, count 0 2006.257.18:33:17.49#ibcon#about to read 5, iclass 39, count 0 2006.257.18:33:17.49#ibcon#read 5, iclass 39, count 0 2006.257.18:33:17.49#ibcon#about to read 6, iclass 39, count 0 2006.257.18:33:17.49#ibcon#read 6, iclass 39, count 0 2006.257.18:33:17.49#ibcon#end of sib2, iclass 39, count 0 2006.257.18:33:17.49#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:33:17.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:33:17.49#ibcon#[27=USB\r\n] 2006.257.18:33:17.49#ibcon#*before write, iclass 39, count 0 2006.257.18:33:17.49#ibcon#enter sib2, iclass 39, count 0 2006.257.18:33:17.49#ibcon#flushed, iclass 39, count 0 2006.257.18:33:17.49#ibcon#about to write, iclass 39, count 0 2006.257.18:33:17.49#ibcon#wrote, iclass 39, count 0 2006.257.18:33:17.49#ibcon#about to read 3, iclass 39, count 0 2006.257.18:33:17.52#ibcon#read 3, iclass 39, count 0 2006.257.18:33:17.52#ibcon#about to read 4, iclass 39, count 0 2006.257.18:33:17.52#ibcon#read 4, iclass 39, count 0 2006.257.18:33:17.52#ibcon#about to read 5, iclass 39, count 0 2006.257.18:33:17.52#ibcon#read 5, iclass 39, count 0 2006.257.18:33:17.52#ibcon#about to read 6, iclass 39, count 0 2006.257.18:33:17.52#ibcon#read 6, iclass 39, count 0 2006.257.18:33:17.52#ibcon#end of sib2, iclass 39, count 0 2006.257.18:33:17.52#ibcon#*after write, iclass 39, count 0 2006.257.18:33:17.52#ibcon#*before return 0, iclass 39, count 0 2006.257.18:33:17.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:17.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:33:17.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:33:17.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:33:17.52$vck44/vblo=5,709.99 2006.257.18:33:17.52#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.18:33:17.52#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.18:33:17.52#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:17.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:17.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:17.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:17.52#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:33:17.52#ibcon#first serial, iclass 3, count 0 2006.257.18:33:17.52#ibcon#enter sib2, iclass 3, count 0 2006.257.18:33:17.52#ibcon#flushed, iclass 3, count 0 2006.257.18:33:17.52#ibcon#about to write, iclass 3, count 0 2006.257.18:33:17.52#ibcon#wrote, iclass 3, count 0 2006.257.18:33:17.52#ibcon#about to read 3, iclass 3, count 0 2006.257.18:33:17.54#ibcon#read 3, iclass 3, count 0 2006.257.18:33:17.54#ibcon#about to read 4, iclass 3, count 0 2006.257.18:33:17.54#ibcon#read 4, iclass 3, count 0 2006.257.18:33:17.54#ibcon#about to read 5, iclass 3, count 0 2006.257.18:33:17.54#ibcon#read 5, iclass 3, count 0 2006.257.18:33:17.54#ibcon#about to read 6, iclass 3, count 0 2006.257.18:33:17.54#ibcon#read 6, iclass 3, count 0 2006.257.18:33:17.54#ibcon#end of sib2, iclass 3, count 0 2006.257.18:33:17.54#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:33:17.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:33:17.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:33:17.54#ibcon#*before write, iclass 3, count 0 2006.257.18:33:17.54#ibcon#enter sib2, iclass 3, count 0 2006.257.18:33:17.54#ibcon#flushed, iclass 3, count 0 2006.257.18:33:17.54#ibcon#about to write, iclass 3, count 0 2006.257.18:33:17.54#ibcon#wrote, iclass 3, count 0 2006.257.18:33:17.54#ibcon#about to read 3, iclass 3, count 0 2006.257.18:33:17.58#ibcon#read 3, iclass 3, count 0 2006.257.18:33:17.58#ibcon#about to read 4, iclass 3, count 0 2006.257.18:33:17.58#ibcon#read 4, iclass 3, count 0 2006.257.18:33:17.58#ibcon#about to read 5, iclass 3, count 0 2006.257.18:33:17.58#ibcon#read 5, iclass 3, count 0 2006.257.18:33:17.58#ibcon#about to read 6, iclass 3, count 0 2006.257.18:33:17.58#ibcon#read 6, iclass 3, count 0 2006.257.18:33:17.58#ibcon#end of sib2, iclass 3, count 0 2006.257.18:33:17.58#ibcon#*after write, iclass 3, count 0 2006.257.18:33:17.58#ibcon#*before return 0, iclass 3, count 0 2006.257.18:33:17.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:17.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:33:17.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:33:17.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:33:17.58$vck44/vb=5,4 2006.257.18:33:17.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.18:33:17.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.18:33:17.58#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:17.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:17.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:17.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:17.64#ibcon#enter wrdev, iclass 5, count 2 2006.257.18:33:17.64#ibcon#first serial, iclass 5, count 2 2006.257.18:33:17.64#ibcon#enter sib2, iclass 5, count 2 2006.257.18:33:17.64#ibcon#flushed, iclass 5, count 2 2006.257.18:33:17.64#ibcon#about to write, iclass 5, count 2 2006.257.18:33:17.64#ibcon#wrote, iclass 5, count 2 2006.257.18:33:17.64#ibcon#about to read 3, iclass 5, count 2 2006.257.18:33:17.66#ibcon#read 3, iclass 5, count 2 2006.257.18:33:17.66#ibcon#about to read 4, iclass 5, count 2 2006.257.18:33:17.66#ibcon#read 4, iclass 5, count 2 2006.257.18:33:17.66#ibcon#about to read 5, iclass 5, count 2 2006.257.18:33:17.66#ibcon#read 5, iclass 5, count 2 2006.257.18:33:17.66#ibcon#about to read 6, iclass 5, count 2 2006.257.18:33:17.66#ibcon#read 6, iclass 5, count 2 2006.257.18:33:17.66#ibcon#end of sib2, iclass 5, count 2 2006.257.18:33:17.66#ibcon#*mode == 0, iclass 5, count 2 2006.257.18:33:17.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.18:33:17.66#ibcon#[27=AT05-04\r\n] 2006.257.18:33:17.66#ibcon#*before write, iclass 5, count 2 2006.257.18:33:17.66#ibcon#enter sib2, iclass 5, count 2 2006.257.18:33:17.66#ibcon#flushed, iclass 5, count 2 2006.257.18:33:17.66#ibcon#about to write, iclass 5, count 2 2006.257.18:33:17.66#ibcon#wrote, iclass 5, count 2 2006.257.18:33:17.66#ibcon#about to read 3, iclass 5, count 2 2006.257.18:33:17.69#ibcon#read 3, iclass 5, count 2 2006.257.18:33:17.69#ibcon#about to read 4, iclass 5, count 2 2006.257.18:33:17.69#ibcon#read 4, iclass 5, count 2 2006.257.18:33:17.69#ibcon#about to read 5, iclass 5, count 2 2006.257.18:33:17.69#ibcon#read 5, iclass 5, count 2 2006.257.18:33:17.69#ibcon#about to read 6, iclass 5, count 2 2006.257.18:33:17.69#ibcon#read 6, iclass 5, count 2 2006.257.18:33:17.69#ibcon#end of sib2, iclass 5, count 2 2006.257.18:33:17.69#ibcon#*after write, iclass 5, count 2 2006.257.18:33:17.69#ibcon#*before return 0, iclass 5, count 2 2006.257.18:33:17.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:17.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:33:17.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.18:33:17.69#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:17.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:17.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:17.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:17.81#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:33:17.81#ibcon#first serial, iclass 5, count 0 2006.257.18:33:17.81#ibcon#enter sib2, iclass 5, count 0 2006.257.18:33:17.81#ibcon#flushed, iclass 5, count 0 2006.257.18:33:17.81#ibcon#about to write, iclass 5, count 0 2006.257.18:33:17.81#ibcon#wrote, iclass 5, count 0 2006.257.18:33:17.81#ibcon#about to read 3, iclass 5, count 0 2006.257.18:33:17.83#ibcon#read 3, iclass 5, count 0 2006.257.18:33:17.83#ibcon#about to read 4, iclass 5, count 0 2006.257.18:33:17.83#ibcon#read 4, iclass 5, count 0 2006.257.18:33:17.83#ibcon#about to read 5, iclass 5, count 0 2006.257.18:33:17.83#ibcon#read 5, iclass 5, count 0 2006.257.18:33:17.83#ibcon#about to read 6, iclass 5, count 0 2006.257.18:33:17.83#ibcon#read 6, iclass 5, count 0 2006.257.18:33:17.83#ibcon#end of sib2, iclass 5, count 0 2006.257.18:33:17.83#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:33:17.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:33:17.83#ibcon#[27=USB\r\n] 2006.257.18:33:17.83#ibcon#*before write, iclass 5, count 0 2006.257.18:33:17.83#ibcon#enter sib2, iclass 5, count 0 2006.257.18:33:17.83#ibcon#flushed, iclass 5, count 0 2006.257.18:33:17.83#ibcon#about to write, iclass 5, count 0 2006.257.18:33:17.83#ibcon#wrote, iclass 5, count 0 2006.257.18:33:17.83#ibcon#about to read 3, iclass 5, count 0 2006.257.18:33:17.86#ibcon#read 3, iclass 5, count 0 2006.257.18:33:17.86#ibcon#about to read 4, iclass 5, count 0 2006.257.18:33:17.86#ibcon#read 4, iclass 5, count 0 2006.257.18:33:17.86#ibcon#about to read 5, iclass 5, count 0 2006.257.18:33:17.86#ibcon#read 5, iclass 5, count 0 2006.257.18:33:17.86#ibcon#about to read 6, iclass 5, count 0 2006.257.18:33:17.86#ibcon#read 6, iclass 5, count 0 2006.257.18:33:17.86#ibcon#end of sib2, iclass 5, count 0 2006.257.18:33:17.86#ibcon#*after write, iclass 5, count 0 2006.257.18:33:17.86#ibcon#*before return 0, iclass 5, count 0 2006.257.18:33:17.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:17.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:33:17.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:33:17.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:33:17.86$vck44/vblo=6,719.99 2006.257.18:33:17.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.18:33:17.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.18:33:17.86#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:17.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:17.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:17.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:17.86#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:33:17.86#ibcon#first serial, iclass 7, count 0 2006.257.18:33:17.86#ibcon#enter sib2, iclass 7, count 0 2006.257.18:33:17.86#ibcon#flushed, iclass 7, count 0 2006.257.18:33:17.86#ibcon#about to write, iclass 7, count 0 2006.257.18:33:17.86#ibcon#wrote, iclass 7, count 0 2006.257.18:33:17.86#ibcon#about to read 3, iclass 7, count 0 2006.257.18:33:17.88#ibcon#read 3, iclass 7, count 0 2006.257.18:33:17.88#ibcon#about to read 4, iclass 7, count 0 2006.257.18:33:17.88#ibcon#read 4, iclass 7, count 0 2006.257.18:33:17.88#ibcon#about to read 5, iclass 7, count 0 2006.257.18:33:17.88#ibcon#read 5, iclass 7, count 0 2006.257.18:33:17.88#ibcon#about to read 6, iclass 7, count 0 2006.257.18:33:17.88#ibcon#read 6, iclass 7, count 0 2006.257.18:33:17.88#ibcon#end of sib2, iclass 7, count 0 2006.257.18:33:17.88#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:33:17.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:33:17.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:33:17.88#ibcon#*before write, iclass 7, count 0 2006.257.18:33:17.88#ibcon#enter sib2, iclass 7, count 0 2006.257.18:33:17.88#ibcon#flushed, iclass 7, count 0 2006.257.18:33:17.88#ibcon#about to write, iclass 7, count 0 2006.257.18:33:17.88#ibcon#wrote, iclass 7, count 0 2006.257.18:33:17.88#ibcon#about to read 3, iclass 7, count 0 2006.257.18:33:17.92#ibcon#read 3, iclass 7, count 0 2006.257.18:33:17.92#ibcon#about to read 4, iclass 7, count 0 2006.257.18:33:17.92#ibcon#read 4, iclass 7, count 0 2006.257.18:33:17.92#ibcon#about to read 5, iclass 7, count 0 2006.257.18:33:17.92#ibcon#read 5, iclass 7, count 0 2006.257.18:33:17.92#ibcon#about to read 6, iclass 7, count 0 2006.257.18:33:17.92#ibcon#read 6, iclass 7, count 0 2006.257.18:33:17.92#ibcon#end of sib2, iclass 7, count 0 2006.257.18:33:17.92#ibcon#*after write, iclass 7, count 0 2006.257.18:33:17.92#ibcon#*before return 0, iclass 7, count 0 2006.257.18:33:17.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:17.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:33:17.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:33:17.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:33:17.92$vck44/vb=6,4 2006.257.18:33:17.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.18:33:17.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.18:33:17.92#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:17.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:17.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:17.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:17.98#ibcon#enter wrdev, iclass 11, count 2 2006.257.18:33:17.98#ibcon#first serial, iclass 11, count 2 2006.257.18:33:17.98#ibcon#enter sib2, iclass 11, count 2 2006.257.18:33:17.98#ibcon#flushed, iclass 11, count 2 2006.257.18:33:17.98#ibcon#about to write, iclass 11, count 2 2006.257.18:33:17.98#ibcon#wrote, iclass 11, count 2 2006.257.18:33:17.98#ibcon#about to read 3, iclass 11, count 2 2006.257.18:33:18.00#ibcon#read 3, iclass 11, count 2 2006.257.18:33:18.00#ibcon#about to read 4, iclass 11, count 2 2006.257.18:33:18.00#ibcon#read 4, iclass 11, count 2 2006.257.18:33:18.00#ibcon#about to read 5, iclass 11, count 2 2006.257.18:33:18.00#ibcon#read 5, iclass 11, count 2 2006.257.18:33:18.00#ibcon#about to read 6, iclass 11, count 2 2006.257.18:33:18.00#ibcon#read 6, iclass 11, count 2 2006.257.18:33:18.00#ibcon#end of sib2, iclass 11, count 2 2006.257.18:33:18.00#ibcon#*mode == 0, iclass 11, count 2 2006.257.18:33:18.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.18:33:18.00#ibcon#[27=AT06-04\r\n] 2006.257.18:33:18.00#ibcon#*before write, iclass 11, count 2 2006.257.18:33:18.00#ibcon#enter sib2, iclass 11, count 2 2006.257.18:33:18.00#ibcon#flushed, iclass 11, count 2 2006.257.18:33:18.00#ibcon#about to write, iclass 11, count 2 2006.257.18:33:18.00#ibcon#wrote, iclass 11, count 2 2006.257.18:33:18.00#ibcon#about to read 3, iclass 11, count 2 2006.257.18:33:18.03#ibcon#read 3, iclass 11, count 2 2006.257.18:33:18.03#ibcon#about to read 4, iclass 11, count 2 2006.257.18:33:18.03#ibcon#read 4, iclass 11, count 2 2006.257.18:33:18.03#ibcon#about to read 5, iclass 11, count 2 2006.257.18:33:18.03#ibcon#read 5, iclass 11, count 2 2006.257.18:33:18.03#ibcon#about to read 6, iclass 11, count 2 2006.257.18:33:18.03#ibcon#read 6, iclass 11, count 2 2006.257.18:33:18.03#ibcon#end of sib2, iclass 11, count 2 2006.257.18:33:18.03#ibcon#*after write, iclass 11, count 2 2006.257.18:33:18.03#ibcon#*before return 0, iclass 11, count 2 2006.257.18:33:18.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:18.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:33:18.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.18:33:18.03#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:18.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:18.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:18.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:18.15#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:33:18.15#ibcon#first serial, iclass 11, count 0 2006.257.18:33:18.15#ibcon#enter sib2, iclass 11, count 0 2006.257.18:33:18.15#ibcon#flushed, iclass 11, count 0 2006.257.18:33:18.15#ibcon#about to write, iclass 11, count 0 2006.257.18:33:18.15#ibcon#wrote, iclass 11, count 0 2006.257.18:33:18.15#ibcon#about to read 3, iclass 11, count 0 2006.257.18:33:18.17#ibcon#read 3, iclass 11, count 0 2006.257.18:33:18.17#ibcon#about to read 4, iclass 11, count 0 2006.257.18:33:18.17#ibcon#read 4, iclass 11, count 0 2006.257.18:33:18.17#ibcon#about to read 5, iclass 11, count 0 2006.257.18:33:18.17#ibcon#read 5, iclass 11, count 0 2006.257.18:33:18.17#ibcon#about to read 6, iclass 11, count 0 2006.257.18:33:18.17#ibcon#read 6, iclass 11, count 0 2006.257.18:33:18.17#ibcon#end of sib2, iclass 11, count 0 2006.257.18:33:18.17#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:33:18.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:33:18.17#ibcon#[27=USB\r\n] 2006.257.18:33:18.17#ibcon#*before write, iclass 11, count 0 2006.257.18:33:18.17#ibcon#enter sib2, iclass 11, count 0 2006.257.18:33:18.17#ibcon#flushed, iclass 11, count 0 2006.257.18:33:18.17#ibcon#about to write, iclass 11, count 0 2006.257.18:33:18.17#ibcon#wrote, iclass 11, count 0 2006.257.18:33:18.17#ibcon#about to read 3, iclass 11, count 0 2006.257.18:33:18.20#ibcon#read 3, iclass 11, count 0 2006.257.18:33:18.20#ibcon#about to read 4, iclass 11, count 0 2006.257.18:33:18.20#ibcon#read 4, iclass 11, count 0 2006.257.18:33:18.20#ibcon#about to read 5, iclass 11, count 0 2006.257.18:33:18.20#ibcon#read 5, iclass 11, count 0 2006.257.18:33:18.20#ibcon#about to read 6, iclass 11, count 0 2006.257.18:33:18.20#ibcon#read 6, iclass 11, count 0 2006.257.18:33:18.20#ibcon#end of sib2, iclass 11, count 0 2006.257.18:33:18.20#ibcon#*after write, iclass 11, count 0 2006.257.18:33:18.20#ibcon#*before return 0, iclass 11, count 0 2006.257.18:33:18.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:18.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:33:18.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:33:18.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:33:18.20$vck44/vblo=7,734.99 2006.257.18:33:18.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.18:33:18.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.18:33:18.20#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:18.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:18.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:18.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:18.20#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:33:18.20#ibcon#first serial, iclass 13, count 0 2006.257.18:33:18.20#ibcon#enter sib2, iclass 13, count 0 2006.257.18:33:18.20#ibcon#flushed, iclass 13, count 0 2006.257.18:33:18.20#ibcon#about to write, iclass 13, count 0 2006.257.18:33:18.20#ibcon#wrote, iclass 13, count 0 2006.257.18:33:18.20#ibcon#about to read 3, iclass 13, count 0 2006.257.18:33:18.22#ibcon#read 3, iclass 13, count 0 2006.257.18:33:18.22#ibcon#about to read 4, iclass 13, count 0 2006.257.18:33:18.22#ibcon#read 4, iclass 13, count 0 2006.257.18:33:18.22#ibcon#about to read 5, iclass 13, count 0 2006.257.18:33:18.22#ibcon#read 5, iclass 13, count 0 2006.257.18:33:18.22#ibcon#about to read 6, iclass 13, count 0 2006.257.18:33:18.22#ibcon#read 6, iclass 13, count 0 2006.257.18:33:18.22#ibcon#end of sib2, iclass 13, count 0 2006.257.18:33:18.22#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:33:18.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:33:18.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:33:18.22#ibcon#*before write, iclass 13, count 0 2006.257.18:33:18.22#ibcon#enter sib2, iclass 13, count 0 2006.257.18:33:18.22#ibcon#flushed, iclass 13, count 0 2006.257.18:33:18.22#ibcon#about to write, iclass 13, count 0 2006.257.18:33:18.22#ibcon#wrote, iclass 13, count 0 2006.257.18:33:18.22#ibcon#about to read 3, iclass 13, count 0 2006.257.18:33:18.26#ibcon#read 3, iclass 13, count 0 2006.257.18:33:18.26#ibcon#about to read 4, iclass 13, count 0 2006.257.18:33:18.26#ibcon#read 4, iclass 13, count 0 2006.257.18:33:18.26#ibcon#about to read 5, iclass 13, count 0 2006.257.18:33:18.26#ibcon#read 5, iclass 13, count 0 2006.257.18:33:18.26#ibcon#about to read 6, iclass 13, count 0 2006.257.18:33:18.26#ibcon#read 6, iclass 13, count 0 2006.257.18:33:18.26#ibcon#end of sib2, iclass 13, count 0 2006.257.18:33:18.26#ibcon#*after write, iclass 13, count 0 2006.257.18:33:18.26#ibcon#*before return 0, iclass 13, count 0 2006.257.18:33:18.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:18.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:33:18.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:33:18.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:33:18.26$vck44/vb=7,4 2006.257.18:33:18.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.18:33:18.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.18:33:18.26#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:18.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:18.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:18.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:18.32#ibcon#enter wrdev, iclass 15, count 2 2006.257.18:33:18.32#ibcon#first serial, iclass 15, count 2 2006.257.18:33:18.32#ibcon#enter sib2, iclass 15, count 2 2006.257.18:33:18.32#ibcon#flushed, iclass 15, count 2 2006.257.18:33:18.32#ibcon#about to write, iclass 15, count 2 2006.257.18:33:18.32#ibcon#wrote, iclass 15, count 2 2006.257.18:33:18.32#ibcon#about to read 3, iclass 15, count 2 2006.257.18:33:18.34#ibcon#read 3, iclass 15, count 2 2006.257.18:33:18.34#ibcon#about to read 4, iclass 15, count 2 2006.257.18:33:18.34#ibcon#read 4, iclass 15, count 2 2006.257.18:33:18.34#ibcon#about to read 5, iclass 15, count 2 2006.257.18:33:18.34#ibcon#read 5, iclass 15, count 2 2006.257.18:33:18.34#ibcon#about to read 6, iclass 15, count 2 2006.257.18:33:18.34#ibcon#read 6, iclass 15, count 2 2006.257.18:33:18.34#ibcon#end of sib2, iclass 15, count 2 2006.257.18:33:18.34#ibcon#*mode == 0, iclass 15, count 2 2006.257.18:33:18.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.18:33:18.34#ibcon#[27=AT07-04\r\n] 2006.257.18:33:18.34#ibcon#*before write, iclass 15, count 2 2006.257.18:33:18.34#ibcon#enter sib2, iclass 15, count 2 2006.257.18:33:18.34#ibcon#flushed, iclass 15, count 2 2006.257.18:33:18.34#ibcon#about to write, iclass 15, count 2 2006.257.18:33:18.34#ibcon#wrote, iclass 15, count 2 2006.257.18:33:18.34#ibcon#about to read 3, iclass 15, count 2 2006.257.18:33:18.37#ibcon#read 3, iclass 15, count 2 2006.257.18:33:18.37#ibcon#about to read 4, iclass 15, count 2 2006.257.18:33:18.37#ibcon#read 4, iclass 15, count 2 2006.257.18:33:18.37#ibcon#about to read 5, iclass 15, count 2 2006.257.18:33:18.37#ibcon#read 5, iclass 15, count 2 2006.257.18:33:18.37#ibcon#about to read 6, iclass 15, count 2 2006.257.18:33:18.37#ibcon#read 6, iclass 15, count 2 2006.257.18:33:18.37#ibcon#end of sib2, iclass 15, count 2 2006.257.18:33:18.37#ibcon#*after write, iclass 15, count 2 2006.257.18:33:18.37#ibcon#*before return 0, iclass 15, count 2 2006.257.18:33:18.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:18.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:33:18.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.18:33:18.37#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:18.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:18.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:18.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:18.49#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:33:18.49#ibcon#first serial, iclass 15, count 0 2006.257.18:33:18.49#ibcon#enter sib2, iclass 15, count 0 2006.257.18:33:18.49#ibcon#flushed, iclass 15, count 0 2006.257.18:33:18.49#ibcon#about to write, iclass 15, count 0 2006.257.18:33:18.49#ibcon#wrote, iclass 15, count 0 2006.257.18:33:18.49#ibcon#about to read 3, iclass 15, count 0 2006.257.18:33:18.51#ibcon#read 3, iclass 15, count 0 2006.257.18:33:18.51#ibcon#about to read 4, iclass 15, count 0 2006.257.18:33:18.51#ibcon#read 4, iclass 15, count 0 2006.257.18:33:18.51#ibcon#about to read 5, iclass 15, count 0 2006.257.18:33:18.51#ibcon#read 5, iclass 15, count 0 2006.257.18:33:18.51#ibcon#about to read 6, iclass 15, count 0 2006.257.18:33:18.51#ibcon#read 6, iclass 15, count 0 2006.257.18:33:18.51#ibcon#end of sib2, iclass 15, count 0 2006.257.18:33:18.51#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:33:18.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:33:18.51#ibcon#[27=USB\r\n] 2006.257.18:33:18.51#ibcon#*before write, iclass 15, count 0 2006.257.18:33:18.51#ibcon#enter sib2, iclass 15, count 0 2006.257.18:33:18.51#ibcon#flushed, iclass 15, count 0 2006.257.18:33:18.51#ibcon#about to write, iclass 15, count 0 2006.257.18:33:18.51#ibcon#wrote, iclass 15, count 0 2006.257.18:33:18.51#ibcon#about to read 3, iclass 15, count 0 2006.257.18:33:18.54#ibcon#read 3, iclass 15, count 0 2006.257.18:33:18.54#ibcon#about to read 4, iclass 15, count 0 2006.257.18:33:18.54#ibcon#read 4, iclass 15, count 0 2006.257.18:33:18.54#ibcon#about to read 5, iclass 15, count 0 2006.257.18:33:18.54#ibcon#read 5, iclass 15, count 0 2006.257.18:33:18.54#ibcon#about to read 6, iclass 15, count 0 2006.257.18:33:18.54#ibcon#read 6, iclass 15, count 0 2006.257.18:33:18.54#ibcon#end of sib2, iclass 15, count 0 2006.257.18:33:18.54#ibcon#*after write, iclass 15, count 0 2006.257.18:33:18.54#ibcon#*before return 0, iclass 15, count 0 2006.257.18:33:18.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:18.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:33:18.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:33:18.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:33:18.54$vck44/vblo=8,744.99 2006.257.18:33:18.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.18:33:18.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.18:33:18.54#ibcon#ireg 17 cls_cnt 0 2006.257.18:33:18.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:18.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:18.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:18.54#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:33:18.54#ibcon#first serial, iclass 17, count 0 2006.257.18:33:18.54#ibcon#enter sib2, iclass 17, count 0 2006.257.18:33:18.54#ibcon#flushed, iclass 17, count 0 2006.257.18:33:18.54#ibcon#about to write, iclass 17, count 0 2006.257.18:33:18.54#ibcon#wrote, iclass 17, count 0 2006.257.18:33:18.54#ibcon#about to read 3, iclass 17, count 0 2006.257.18:33:18.56#ibcon#read 3, iclass 17, count 0 2006.257.18:33:18.56#ibcon#about to read 4, iclass 17, count 0 2006.257.18:33:18.56#ibcon#read 4, iclass 17, count 0 2006.257.18:33:18.56#ibcon#about to read 5, iclass 17, count 0 2006.257.18:33:18.56#ibcon#read 5, iclass 17, count 0 2006.257.18:33:18.56#ibcon#about to read 6, iclass 17, count 0 2006.257.18:33:18.56#ibcon#read 6, iclass 17, count 0 2006.257.18:33:18.56#ibcon#end of sib2, iclass 17, count 0 2006.257.18:33:18.56#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:33:18.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:33:18.56#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:33:18.56#ibcon#*before write, iclass 17, count 0 2006.257.18:33:18.56#ibcon#enter sib2, iclass 17, count 0 2006.257.18:33:18.56#ibcon#flushed, iclass 17, count 0 2006.257.18:33:18.56#ibcon#about to write, iclass 17, count 0 2006.257.18:33:18.56#ibcon#wrote, iclass 17, count 0 2006.257.18:33:18.56#ibcon#about to read 3, iclass 17, count 0 2006.257.18:33:18.60#ibcon#read 3, iclass 17, count 0 2006.257.18:33:18.60#ibcon#about to read 4, iclass 17, count 0 2006.257.18:33:18.60#ibcon#read 4, iclass 17, count 0 2006.257.18:33:18.60#ibcon#about to read 5, iclass 17, count 0 2006.257.18:33:18.60#ibcon#read 5, iclass 17, count 0 2006.257.18:33:18.60#ibcon#about to read 6, iclass 17, count 0 2006.257.18:33:18.60#ibcon#read 6, iclass 17, count 0 2006.257.18:33:18.60#ibcon#end of sib2, iclass 17, count 0 2006.257.18:33:18.60#ibcon#*after write, iclass 17, count 0 2006.257.18:33:18.60#ibcon#*before return 0, iclass 17, count 0 2006.257.18:33:18.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:18.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:33:18.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:33:18.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:33:18.60$vck44/vb=8,4 2006.257.18:33:18.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.18:33:18.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.18:33:18.60#ibcon#ireg 11 cls_cnt 2 2006.257.18:33:18.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:18.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:18.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:18.66#ibcon#enter wrdev, iclass 19, count 2 2006.257.18:33:18.66#ibcon#first serial, iclass 19, count 2 2006.257.18:33:18.66#ibcon#enter sib2, iclass 19, count 2 2006.257.18:33:18.66#ibcon#flushed, iclass 19, count 2 2006.257.18:33:18.66#ibcon#about to write, iclass 19, count 2 2006.257.18:33:18.66#ibcon#wrote, iclass 19, count 2 2006.257.18:33:18.66#ibcon#about to read 3, iclass 19, count 2 2006.257.18:33:18.68#ibcon#read 3, iclass 19, count 2 2006.257.18:33:18.68#ibcon#about to read 4, iclass 19, count 2 2006.257.18:33:18.68#ibcon#read 4, iclass 19, count 2 2006.257.18:33:18.68#ibcon#about to read 5, iclass 19, count 2 2006.257.18:33:18.68#ibcon#read 5, iclass 19, count 2 2006.257.18:33:18.68#ibcon#about to read 6, iclass 19, count 2 2006.257.18:33:18.68#ibcon#read 6, iclass 19, count 2 2006.257.18:33:18.68#ibcon#end of sib2, iclass 19, count 2 2006.257.18:33:18.68#ibcon#*mode == 0, iclass 19, count 2 2006.257.18:33:18.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.18:33:18.68#ibcon#[27=AT08-04\r\n] 2006.257.18:33:18.68#ibcon#*before write, iclass 19, count 2 2006.257.18:33:18.68#ibcon#enter sib2, iclass 19, count 2 2006.257.18:33:18.68#ibcon#flushed, iclass 19, count 2 2006.257.18:33:18.68#ibcon#about to write, iclass 19, count 2 2006.257.18:33:18.68#ibcon#wrote, iclass 19, count 2 2006.257.18:33:18.68#ibcon#about to read 3, iclass 19, count 2 2006.257.18:33:18.71#ibcon#read 3, iclass 19, count 2 2006.257.18:33:18.71#ibcon#about to read 4, iclass 19, count 2 2006.257.18:33:18.71#ibcon#read 4, iclass 19, count 2 2006.257.18:33:18.71#ibcon#about to read 5, iclass 19, count 2 2006.257.18:33:18.71#ibcon#read 5, iclass 19, count 2 2006.257.18:33:18.71#ibcon#about to read 6, iclass 19, count 2 2006.257.18:33:18.71#ibcon#read 6, iclass 19, count 2 2006.257.18:33:18.71#ibcon#end of sib2, iclass 19, count 2 2006.257.18:33:18.71#ibcon#*after write, iclass 19, count 2 2006.257.18:33:18.71#ibcon#*before return 0, iclass 19, count 2 2006.257.18:33:18.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:18.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:33:18.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.18:33:18.71#ibcon#ireg 7 cls_cnt 0 2006.257.18:33:18.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:18.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:18.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:18.83#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:33:18.83#ibcon#first serial, iclass 19, count 0 2006.257.18:33:18.83#ibcon#enter sib2, iclass 19, count 0 2006.257.18:33:18.83#ibcon#flushed, iclass 19, count 0 2006.257.18:33:18.83#ibcon#about to write, iclass 19, count 0 2006.257.18:33:18.83#ibcon#wrote, iclass 19, count 0 2006.257.18:33:18.83#ibcon#about to read 3, iclass 19, count 0 2006.257.18:33:18.85#ibcon#read 3, iclass 19, count 0 2006.257.18:33:18.85#ibcon#about to read 4, iclass 19, count 0 2006.257.18:33:18.85#ibcon#read 4, iclass 19, count 0 2006.257.18:33:18.85#ibcon#about to read 5, iclass 19, count 0 2006.257.18:33:18.85#ibcon#read 5, iclass 19, count 0 2006.257.18:33:18.85#ibcon#about to read 6, iclass 19, count 0 2006.257.18:33:18.85#ibcon#read 6, iclass 19, count 0 2006.257.18:33:18.85#ibcon#end of sib2, iclass 19, count 0 2006.257.18:33:18.85#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:33:18.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:33:18.85#ibcon#[27=USB\r\n] 2006.257.18:33:18.85#ibcon#*before write, iclass 19, count 0 2006.257.18:33:18.85#ibcon#enter sib2, iclass 19, count 0 2006.257.18:33:18.85#ibcon#flushed, iclass 19, count 0 2006.257.18:33:18.85#ibcon#about to write, iclass 19, count 0 2006.257.18:33:18.85#ibcon#wrote, iclass 19, count 0 2006.257.18:33:18.85#ibcon#about to read 3, iclass 19, count 0 2006.257.18:33:18.88#ibcon#read 3, iclass 19, count 0 2006.257.18:33:18.88#ibcon#about to read 4, iclass 19, count 0 2006.257.18:33:18.88#ibcon#read 4, iclass 19, count 0 2006.257.18:33:18.88#ibcon#about to read 5, iclass 19, count 0 2006.257.18:33:18.88#ibcon#read 5, iclass 19, count 0 2006.257.18:33:18.88#ibcon#about to read 6, iclass 19, count 0 2006.257.18:33:18.88#ibcon#read 6, iclass 19, count 0 2006.257.18:33:18.88#ibcon#end of sib2, iclass 19, count 0 2006.257.18:33:18.88#ibcon#*after write, iclass 19, count 0 2006.257.18:33:18.88#ibcon#*before return 0, iclass 19, count 0 2006.257.18:33:18.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:18.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:33:18.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:33:18.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:33:18.88$vck44/vabw=wide 2006.257.18:33:18.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.18:33:18.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.18:33:18.88#ibcon#ireg 8 cls_cnt 0 2006.257.18:33:18.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:18.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:18.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:18.88#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:33:18.88#ibcon#first serial, iclass 21, count 0 2006.257.18:33:18.88#ibcon#enter sib2, iclass 21, count 0 2006.257.18:33:18.88#ibcon#flushed, iclass 21, count 0 2006.257.18:33:18.88#ibcon#about to write, iclass 21, count 0 2006.257.18:33:18.88#ibcon#wrote, iclass 21, count 0 2006.257.18:33:18.88#ibcon#about to read 3, iclass 21, count 0 2006.257.18:33:18.90#ibcon#read 3, iclass 21, count 0 2006.257.18:33:18.90#ibcon#about to read 4, iclass 21, count 0 2006.257.18:33:18.90#ibcon#read 4, iclass 21, count 0 2006.257.18:33:18.90#ibcon#about to read 5, iclass 21, count 0 2006.257.18:33:18.90#ibcon#read 5, iclass 21, count 0 2006.257.18:33:18.90#ibcon#about to read 6, iclass 21, count 0 2006.257.18:33:18.90#ibcon#read 6, iclass 21, count 0 2006.257.18:33:18.90#ibcon#end of sib2, iclass 21, count 0 2006.257.18:33:18.90#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:33:18.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:33:18.90#ibcon#[25=BW32\r\n] 2006.257.18:33:18.90#ibcon#*before write, iclass 21, count 0 2006.257.18:33:18.90#ibcon#enter sib2, iclass 21, count 0 2006.257.18:33:18.90#ibcon#flushed, iclass 21, count 0 2006.257.18:33:18.90#ibcon#about to write, iclass 21, count 0 2006.257.18:33:18.90#ibcon#wrote, iclass 21, count 0 2006.257.18:33:18.90#ibcon#about to read 3, iclass 21, count 0 2006.257.18:33:18.93#ibcon#read 3, iclass 21, count 0 2006.257.18:33:18.93#ibcon#about to read 4, iclass 21, count 0 2006.257.18:33:18.93#ibcon#read 4, iclass 21, count 0 2006.257.18:33:18.93#ibcon#about to read 5, iclass 21, count 0 2006.257.18:33:18.93#ibcon#read 5, iclass 21, count 0 2006.257.18:33:18.93#ibcon#about to read 6, iclass 21, count 0 2006.257.18:33:18.93#ibcon#read 6, iclass 21, count 0 2006.257.18:33:18.93#ibcon#end of sib2, iclass 21, count 0 2006.257.18:33:18.93#ibcon#*after write, iclass 21, count 0 2006.257.18:33:18.93#ibcon#*before return 0, iclass 21, count 0 2006.257.18:33:18.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:18.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:33:18.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:33:18.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:33:18.93$vck44/vbbw=wide 2006.257.18:33:18.93#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.18:33:18.93#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.18:33:18.93#ibcon#ireg 8 cls_cnt 0 2006.257.18:33:18.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:33:19.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:33:19.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:33:19.00#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:33:19.00#ibcon#first serial, iclass 23, count 0 2006.257.18:33:19.00#ibcon#enter sib2, iclass 23, count 0 2006.257.18:33:19.00#ibcon#flushed, iclass 23, count 0 2006.257.18:33:19.00#ibcon#about to write, iclass 23, count 0 2006.257.18:33:19.00#ibcon#wrote, iclass 23, count 0 2006.257.18:33:19.00#ibcon#about to read 3, iclass 23, count 0 2006.257.18:33:19.02#ibcon#read 3, iclass 23, count 0 2006.257.18:33:19.02#ibcon#about to read 4, iclass 23, count 0 2006.257.18:33:19.02#ibcon#read 4, iclass 23, count 0 2006.257.18:33:19.02#ibcon#about to read 5, iclass 23, count 0 2006.257.18:33:19.02#ibcon#read 5, iclass 23, count 0 2006.257.18:33:19.02#ibcon#about to read 6, iclass 23, count 0 2006.257.18:33:19.02#ibcon#read 6, iclass 23, count 0 2006.257.18:33:19.02#ibcon#end of sib2, iclass 23, count 0 2006.257.18:33:19.02#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:33:19.02#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:33:19.02#ibcon#[27=BW32\r\n] 2006.257.18:33:19.02#ibcon#*before write, iclass 23, count 0 2006.257.18:33:19.02#ibcon#enter sib2, iclass 23, count 0 2006.257.18:33:19.02#ibcon#flushed, iclass 23, count 0 2006.257.18:33:19.02#ibcon#about to write, iclass 23, count 0 2006.257.18:33:19.02#ibcon#wrote, iclass 23, count 0 2006.257.18:33:19.02#ibcon#about to read 3, iclass 23, count 0 2006.257.18:33:19.05#ibcon#read 3, iclass 23, count 0 2006.257.18:33:19.05#ibcon#about to read 4, iclass 23, count 0 2006.257.18:33:19.05#ibcon#read 4, iclass 23, count 0 2006.257.18:33:19.05#ibcon#about to read 5, iclass 23, count 0 2006.257.18:33:19.05#ibcon#read 5, iclass 23, count 0 2006.257.18:33:19.05#ibcon#about to read 6, iclass 23, count 0 2006.257.18:33:19.05#ibcon#read 6, iclass 23, count 0 2006.257.18:33:19.05#ibcon#end of sib2, iclass 23, count 0 2006.257.18:33:19.05#ibcon#*after write, iclass 23, count 0 2006.257.18:33:19.05#ibcon#*before return 0, iclass 23, count 0 2006.257.18:33:19.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:33:19.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:33:19.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:33:19.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:33:19.05$setupk4/ifdk4 2006.257.18:33:19.05$ifdk4/lo= 2006.257.18:33:19.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:33:19.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:33:19.05$ifdk4/patch= 2006.257.18:33:19.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:33:19.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:33:19.05$setupk4/!*+20s 2006.257.18:33:24.21#abcon#<5=/15 1.0 2.0 17.29 971014.3\r\n> 2006.257.18:33:24.23#abcon#{5=INTERFACE CLEAR} 2006.257.18:33:24.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:33:33.56$setupk4/"tpicd 2006.257.18:33:33.56$setupk4/echo=off 2006.257.18:33:33.56$setupk4/xlog=off 2006.257.18:33:33.56:!2006.257.18:40:49 2006.257.18:34:11.14#trakl#Source acquired 2006.257.18:34:12.14#flagr#flagr/antenna,acquired 2006.257.18:40:49.02:preob 2006.257.18:40:50.15/onsource/TRACKING 2006.257.18:40:50.15:!2006.257.18:40:59 2006.257.18:40:59.01:"tape 2006.257.18:40:59.02:"st=record 2006.257.18:40:59.02:data_valid=on 2006.257.18:40:59.02:midob 2006.257.18:41:00.14/onsource/TRACKING 2006.257.18:41:00.15/wx/17.28,1014.2,97 2006.257.18:41:00.22/cable/+6.4845E-03 2006.257.18:41:01.31/va/01,08,usb,yes,34,36 2006.257.18:41:01.31/va/02,07,usb,yes,37,37 2006.257.18:41:01.31/va/03,08,usb,yes,33,35 2006.257.18:41:01.31/va/04,07,usb,yes,38,40 2006.257.18:41:01.31/va/05,04,usb,yes,34,34 2006.257.18:41:01.31/va/06,04,usb,yes,37,37 2006.257.18:41:01.31/va/07,04,usb,yes,38,39 2006.257.18:41:01.31/va/08,04,usb,yes,32,39 2006.257.18:41:01.54/valo/01,524.99,yes,locked 2006.257.18:41:01.54/valo/02,534.99,yes,locked 2006.257.18:41:01.54/valo/03,564.99,yes,locked 2006.257.18:41:01.54/valo/04,624.99,yes,locked 2006.257.18:41:01.54/valo/05,734.99,yes,locked 2006.257.18:41:01.54/valo/06,814.99,yes,locked 2006.257.18:41:01.54/valo/07,864.99,yes,locked 2006.257.18:41:01.54/valo/08,884.99,yes,locked 2006.257.18:41:02.63/vb/01,04,usb,yes,32,29 2006.257.18:41:02.63/vb/02,05,usb,yes,30,30 2006.257.18:41:02.63/vb/03,04,usb,yes,31,34 2006.257.18:41:02.63/vb/04,05,usb,yes,31,30 2006.257.18:41:02.63/vb/05,04,usb,yes,27,30 2006.257.18:41:02.63/vb/06,04,usb,yes,32,28 2006.257.18:41:02.63/vb/07,04,usb,yes,32,32 2006.257.18:41:02.63/vb/08,04,usb,yes,29,33 2006.257.18:41:02.87/vblo/01,629.99,yes,locked 2006.257.18:41:02.87/vblo/02,634.99,yes,locked 2006.257.18:41:02.87/vblo/03,649.99,yes,locked 2006.257.18:41:02.87/vblo/04,679.99,yes,locked 2006.257.18:41:02.87/vblo/05,709.99,yes,locked 2006.257.18:41:02.87/vblo/06,719.99,yes,locked 2006.257.18:41:02.87/vblo/07,734.99,yes,locked 2006.257.18:41:02.87/vblo/08,744.99,yes,locked 2006.257.18:41:03.02/vabw/8 2006.257.18:41:03.17/vbbw/8 2006.257.18:41:03.26/xfe/off,on,15.0 2006.257.18:41:03.63/ifatt/23,28,28,28 2006.257.18:41:04.07/fmout-gps/S +4.53E-07 2006.257.18:41:04.12:!2006.257.18:42:09 2006.257.18:42:09.01:data_valid=off 2006.257.18:42:09.02:"et 2006.257.18:42:09.02:!+3s 2006.257.18:42:12.03:"tape 2006.257.18:42:12.04:postob 2006.257.18:42:12.23/cable/+6.4848E-03 2006.257.18:42:12.24/wx/17.27,1014.2,97 2006.257.18:42:12.29/fmout-gps/S +4.51E-07 2006.257.18:42:12.30:scan_name=257-1845,jd0609,50 2006.257.18:42:12.30:source=0552+398,055530.81,394849.2,2000.0,cw 2006.257.18:42:13.14#flagr#flagr/antenna,new-source 2006.257.18:42:13.15:checkk5 2006.257.18:42:13.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:42:13.84/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:42:14.19/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:42:14.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:42:14.86/chk_obsdata//k5ts1/T2571840??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.18:42:15.20/chk_obsdata//k5ts2/T2571840??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.18:42:15.53/chk_obsdata//k5ts3/T2571840??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.18:42:15.87/chk_obsdata//k5ts4/T2571840??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.257.18:42:16.52/k5log//k5ts1_log_newline 2006.257.18:42:17.19/k5log//k5ts2_log_newline 2006.257.18:42:17.84/k5log//k5ts3_log_newline 2006.257.18:42:18.50/k5log//k5ts4_log_newline 2006.257.18:42:18.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:42:18.52:setupk4=1 2006.257.18:42:18.52$setupk4/echo=on 2006.257.18:42:18.52$setupk4/pcalon 2006.257.18:42:18.52$pcalon/"no phase cal control is implemented here 2006.257.18:42:18.52$setupk4/"tpicd=stop 2006.257.18:42:18.52$setupk4/"rec=synch_on 2006.257.18:42:18.52$setupk4/"rec_mode=128 2006.257.18:42:18.52$setupk4/!* 2006.257.18:42:18.52$setupk4/recpk4 2006.257.18:42:18.52$recpk4/recpatch= 2006.257.18:42:18.52$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:42:18.52$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:42:18.52$setupk4/vck44 2006.257.18:42:18.53$vck44/valo=1,524.99 2006.257.18:42:18.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.18:42:18.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.18:42:18.53#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:18.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:18.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:18.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:18.53#ibcon#enter wrdev, iclass 24, count 0 2006.257.18:42:18.53#ibcon#first serial, iclass 24, count 0 2006.257.18:42:18.53#ibcon#enter sib2, iclass 24, count 0 2006.257.18:42:18.53#ibcon#flushed, iclass 24, count 0 2006.257.18:42:18.53#ibcon#about to write, iclass 24, count 0 2006.257.18:42:18.53#ibcon#wrote, iclass 24, count 0 2006.257.18:42:18.53#ibcon#about to read 3, iclass 24, count 0 2006.257.18:42:18.54#ibcon#read 3, iclass 24, count 0 2006.257.18:42:18.54#ibcon#about to read 4, iclass 24, count 0 2006.257.18:42:18.54#ibcon#read 4, iclass 24, count 0 2006.257.18:42:18.54#ibcon#about to read 5, iclass 24, count 0 2006.257.18:42:18.54#ibcon#read 5, iclass 24, count 0 2006.257.18:42:18.54#ibcon#about to read 6, iclass 24, count 0 2006.257.18:42:18.54#ibcon#read 6, iclass 24, count 0 2006.257.18:42:18.54#ibcon#end of sib2, iclass 24, count 0 2006.257.18:42:18.54#ibcon#*mode == 0, iclass 24, count 0 2006.257.18:42:18.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.18:42:18.54#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:42:18.54#ibcon#*before write, iclass 24, count 0 2006.257.18:42:18.54#ibcon#enter sib2, iclass 24, count 0 2006.257.18:42:18.54#ibcon#flushed, iclass 24, count 0 2006.257.18:42:18.54#ibcon#about to write, iclass 24, count 0 2006.257.18:42:18.54#ibcon#wrote, iclass 24, count 0 2006.257.18:42:18.54#ibcon#about to read 3, iclass 24, count 0 2006.257.18:42:18.59#ibcon#read 3, iclass 24, count 0 2006.257.18:42:18.59#ibcon#about to read 4, iclass 24, count 0 2006.257.18:42:18.59#ibcon#read 4, iclass 24, count 0 2006.257.18:42:18.59#ibcon#about to read 5, iclass 24, count 0 2006.257.18:42:18.59#ibcon#read 5, iclass 24, count 0 2006.257.18:42:18.59#ibcon#about to read 6, iclass 24, count 0 2006.257.18:42:18.59#ibcon#read 6, iclass 24, count 0 2006.257.18:42:18.59#ibcon#end of sib2, iclass 24, count 0 2006.257.18:42:18.59#ibcon#*after write, iclass 24, count 0 2006.257.18:42:18.59#ibcon#*before return 0, iclass 24, count 0 2006.257.18:42:18.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:18.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:18.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.18:42:18.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.18:42:18.59$vck44/va=1,8 2006.257.18:42:18.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.18:42:18.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.18:42:18.59#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:18.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:18.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:18.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:18.59#ibcon#enter wrdev, iclass 26, count 2 2006.257.18:42:18.59#ibcon#first serial, iclass 26, count 2 2006.257.18:42:18.59#ibcon#enter sib2, iclass 26, count 2 2006.257.18:42:18.59#ibcon#flushed, iclass 26, count 2 2006.257.18:42:18.59#ibcon#about to write, iclass 26, count 2 2006.257.18:42:18.59#ibcon#wrote, iclass 26, count 2 2006.257.18:42:18.59#ibcon#about to read 3, iclass 26, count 2 2006.257.18:42:18.61#ibcon#read 3, iclass 26, count 2 2006.257.18:42:18.61#ibcon#about to read 4, iclass 26, count 2 2006.257.18:42:18.61#ibcon#read 4, iclass 26, count 2 2006.257.18:42:18.61#ibcon#about to read 5, iclass 26, count 2 2006.257.18:42:18.61#ibcon#read 5, iclass 26, count 2 2006.257.18:42:18.61#ibcon#about to read 6, iclass 26, count 2 2006.257.18:42:18.61#ibcon#read 6, iclass 26, count 2 2006.257.18:42:18.61#ibcon#end of sib2, iclass 26, count 2 2006.257.18:42:18.61#ibcon#*mode == 0, iclass 26, count 2 2006.257.18:42:18.61#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.18:42:18.61#ibcon#[25=AT01-08\r\n] 2006.257.18:42:18.61#ibcon#*before write, iclass 26, count 2 2006.257.18:42:18.61#ibcon#enter sib2, iclass 26, count 2 2006.257.18:42:18.61#ibcon#flushed, iclass 26, count 2 2006.257.18:42:18.61#ibcon#about to write, iclass 26, count 2 2006.257.18:42:18.61#ibcon#wrote, iclass 26, count 2 2006.257.18:42:18.61#ibcon#about to read 3, iclass 26, count 2 2006.257.18:42:18.64#ibcon#read 3, iclass 26, count 2 2006.257.18:42:18.64#ibcon#about to read 4, iclass 26, count 2 2006.257.18:42:18.64#ibcon#read 4, iclass 26, count 2 2006.257.18:42:18.64#ibcon#about to read 5, iclass 26, count 2 2006.257.18:42:18.64#ibcon#read 5, iclass 26, count 2 2006.257.18:42:18.64#ibcon#about to read 6, iclass 26, count 2 2006.257.18:42:18.64#ibcon#read 6, iclass 26, count 2 2006.257.18:42:18.64#ibcon#end of sib2, iclass 26, count 2 2006.257.18:42:18.64#ibcon#*after write, iclass 26, count 2 2006.257.18:42:18.64#ibcon#*before return 0, iclass 26, count 2 2006.257.18:42:18.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:18.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:18.64#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.18:42:18.64#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:18.64#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:18.76#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:18.76#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:18.76#ibcon#enter wrdev, iclass 26, count 0 2006.257.18:42:18.76#ibcon#first serial, iclass 26, count 0 2006.257.18:42:18.76#ibcon#enter sib2, iclass 26, count 0 2006.257.18:42:18.76#ibcon#flushed, iclass 26, count 0 2006.257.18:42:18.76#ibcon#about to write, iclass 26, count 0 2006.257.18:42:18.76#ibcon#wrote, iclass 26, count 0 2006.257.18:42:18.76#ibcon#about to read 3, iclass 26, count 0 2006.257.18:42:18.78#ibcon#read 3, iclass 26, count 0 2006.257.18:42:18.78#ibcon#about to read 4, iclass 26, count 0 2006.257.18:42:18.78#ibcon#read 4, iclass 26, count 0 2006.257.18:42:18.78#ibcon#about to read 5, iclass 26, count 0 2006.257.18:42:18.78#ibcon#read 5, iclass 26, count 0 2006.257.18:42:18.78#ibcon#about to read 6, iclass 26, count 0 2006.257.18:42:18.78#ibcon#read 6, iclass 26, count 0 2006.257.18:42:18.78#ibcon#end of sib2, iclass 26, count 0 2006.257.18:42:18.78#ibcon#*mode == 0, iclass 26, count 0 2006.257.18:42:18.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.18:42:18.78#ibcon#[25=USB\r\n] 2006.257.18:42:18.78#ibcon#*before write, iclass 26, count 0 2006.257.18:42:18.78#ibcon#enter sib2, iclass 26, count 0 2006.257.18:42:18.78#ibcon#flushed, iclass 26, count 0 2006.257.18:42:18.78#ibcon#about to write, iclass 26, count 0 2006.257.18:42:18.78#ibcon#wrote, iclass 26, count 0 2006.257.18:42:18.78#ibcon#about to read 3, iclass 26, count 0 2006.257.18:42:18.81#ibcon#read 3, iclass 26, count 0 2006.257.18:42:18.81#ibcon#about to read 4, iclass 26, count 0 2006.257.18:42:18.81#ibcon#read 4, iclass 26, count 0 2006.257.18:42:18.81#ibcon#about to read 5, iclass 26, count 0 2006.257.18:42:18.81#ibcon#read 5, iclass 26, count 0 2006.257.18:42:18.81#ibcon#about to read 6, iclass 26, count 0 2006.257.18:42:18.81#ibcon#read 6, iclass 26, count 0 2006.257.18:42:18.81#ibcon#end of sib2, iclass 26, count 0 2006.257.18:42:18.81#ibcon#*after write, iclass 26, count 0 2006.257.18:42:18.81#ibcon#*before return 0, iclass 26, count 0 2006.257.18:42:18.81#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:18.81#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:18.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.18:42:18.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.18:42:18.81$vck44/valo=2,534.99 2006.257.18:42:18.81#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.18:42:18.81#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.18:42:18.81#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:18.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:18.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:18.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:18.81#ibcon#enter wrdev, iclass 28, count 0 2006.257.18:42:18.81#ibcon#first serial, iclass 28, count 0 2006.257.18:42:18.81#ibcon#enter sib2, iclass 28, count 0 2006.257.18:42:18.81#ibcon#flushed, iclass 28, count 0 2006.257.18:42:18.81#ibcon#about to write, iclass 28, count 0 2006.257.18:42:18.81#ibcon#wrote, iclass 28, count 0 2006.257.18:42:18.81#ibcon#about to read 3, iclass 28, count 0 2006.257.18:42:18.83#ibcon#read 3, iclass 28, count 0 2006.257.18:42:18.83#ibcon#about to read 4, iclass 28, count 0 2006.257.18:42:18.83#ibcon#read 4, iclass 28, count 0 2006.257.18:42:18.83#ibcon#about to read 5, iclass 28, count 0 2006.257.18:42:18.83#ibcon#read 5, iclass 28, count 0 2006.257.18:42:18.83#ibcon#about to read 6, iclass 28, count 0 2006.257.18:42:18.83#ibcon#read 6, iclass 28, count 0 2006.257.18:42:18.83#ibcon#end of sib2, iclass 28, count 0 2006.257.18:42:18.83#ibcon#*mode == 0, iclass 28, count 0 2006.257.18:42:18.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.18:42:18.83#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:42:18.83#ibcon#*before write, iclass 28, count 0 2006.257.18:42:18.83#ibcon#enter sib2, iclass 28, count 0 2006.257.18:42:18.83#ibcon#flushed, iclass 28, count 0 2006.257.18:42:18.83#ibcon#about to write, iclass 28, count 0 2006.257.18:42:18.83#ibcon#wrote, iclass 28, count 0 2006.257.18:42:18.83#ibcon#about to read 3, iclass 28, count 0 2006.257.18:42:18.87#ibcon#read 3, iclass 28, count 0 2006.257.18:42:18.87#ibcon#about to read 4, iclass 28, count 0 2006.257.18:42:18.87#ibcon#read 4, iclass 28, count 0 2006.257.18:42:18.87#ibcon#about to read 5, iclass 28, count 0 2006.257.18:42:18.87#ibcon#read 5, iclass 28, count 0 2006.257.18:42:18.87#ibcon#about to read 6, iclass 28, count 0 2006.257.18:42:18.87#ibcon#read 6, iclass 28, count 0 2006.257.18:42:18.87#ibcon#end of sib2, iclass 28, count 0 2006.257.18:42:18.87#ibcon#*after write, iclass 28, count 0 2006.257.18:42:18.87#ibcon#*before return 0, iclass 28, count 0 2006.257.18:42:18.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:18.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:18.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.18:42:18.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.18:42:18.87$vck44/va=2,7 2006.257.18:42:18.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.18:42:18.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.18:42:18.87#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:18.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:18.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:18.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:18.93#ibcon#enter wrdev, iclass 30, count 2 2006.257.18:42:18.93#ibcon#first serial, iclass 30, count 2 2006.257.18:42:18.93#ibcon#enter sib2, iclass 30, count 2 2006.257.18:42:18.93#ibcon#flushed, iclass 30, count 2 2006.257.18:42:18.93#ibcon#about to write, iclass 30, count 2 2006.257.18:42:18.93#ibcon#wrote, iclass 30, count 2 2006.257.18:42:18.93#ibcon#about to read 3, iclass 30, count 2 2006.257.18:42:18.95#ibcon#read 3, iclass 30, count 2 2006.257.18:42:18.95#ibcon#about to read 4, iclass 30, count 2 2006.257.18:42:18.95#ibcon#read 4, iclass 30, count 2 2006.257.18:42:18.95#ibcon#about to read 5, iclass 30, count 2 2006.257.18:42:18.95#ibcon#read 5, iclass 30, count 2 2006.257.18:42:18.95#ibcon#about to read 6, iclass 30, count 2 2006.257.18:42:18.95#ibcon#read 6, iclass 30, count 2 2006.257.18:42:18.95#ibcon#end of sib2, iclass 30, count 2 2006.257.18:42:18.95#ibcon#*mode == 0, iclass 30, count 2 2006.257.18:42:18.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.18:42:18.95#ibcon#[25=AT02-07\r\n] 2006.257.18:42:18.95#ibcon#*before write, iclass 30, count 2 2006.257.18:42:18.95#ibcon#enter sib2, iclass 30, count 2 2006.257.18:42:18.95#ibcon#flushed, iclass 30, count 2 2006.257.18:42:18.95#ibcon#about to write, iclass 30, count 2 2006.257.18:42:18.95#ibcon#wrote, iclass 30, count 2 2006.257.18:42:18.95#ibcon#about to read 3, iclass 30, count 2 2006.257.18:42:18.98#ibcon#read 3, iclass 30, count 2 2006.257.18:42:18.98#ibcon#about to read 4, iclass 30, count 2 2006.257.18:42:18.98#ibcon#read 4, iclass 30, count 2 2006.257.18:42:18.98#ibcon#about to read 5, iclass 30, count 2 2006.257.18:42:18.98#ibcon#read 5, iclass 30, count 2 2006.257.18:42:18.98#ibcon#about to read 6, iclass 30, count 2 2006.257.18:42:18.98#ibcon#read 6, iclass 30, count 2 2006.257.18:42:18.98#ibcon#end of sib2, iclass 30, count 2 2006.257.18:42:18.98#ibcon#*after write, iclass 30, count 2 2006.257.18:42:18.98#ibcon#*before return 0, iclass 30, count 2 2006.257.18:42:18.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:18.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:18.98#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.18:42:18.98#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:18.98#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:19.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:19.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:19.10#ibcon#enter wrdev, iclass 30, count 0 2006.257.18:42:19.10#ibcon#first serial, iclass 30, count 0 2006.257.18:42:19.10#ibcon#enter sib2, iclass 30, count 0 2006.257.18:42:19.10#ibcon#flushed, iclass 30, count 0 2006.257.18:42:19.10#ibcon#about to write, iclass 30, count 0 2006.257.18:42:19.10#ibcon#wrote, iclass 30, count 0 2006.257.18:42:19.10#ibcon#about to read 3, iclass 30, count 0 2006.257.18:42:19.12#ibcon#read 3, iclass 30, count 0 2006.257.18:42:19.12#ibcon#about to read 4, iclass 30, count 0 2006.257.18:42:19.12#ibcon#read 4, iclass 30, count 0 2006.257.18:42:19.12#ibcon#about to read 5, iclass 30, count 0 2006.257.18:42:19.12#ibcon#read 5, iclass 30, count 0 2006.257.18:42:19.12#ibcon#about to read 6, iclass 30, count 0 2006.257.18:42:19.12#ibcon#read 6, iclass 30, count 0 2006.257.18:42:19.12#ibcon#end of sib2, iclass 30, count 0 2006.257.18:42:19.12#ibcon#*mode == 0, iclass 30, count 0 2006.257.18:42:19.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.18:42:19.12#ibcon#[25=USB\r\n] 2006.257.18:42:19.12#ibcon#*before write, iclass 30, count 0 2006.257.18:42:19.12#ibcon#enter sib2, iclass 30, count 0 2006.257.18:42:19.12#ibcon#flushed, iclass 30, count 0 2006.257.18:42:19.12#ibcon#about to write, iclass 30, count 0 2006.257.18:42:19.12#ibcon#wrote, iclass 30, count 0 2006.257.18:42:19.12#ibcon#about to read 3, iclass 30, count 0 2006.257.18:42:19.15#ibcon#read 3, iclass 30, count 0 2006.257.18:42:19.15#ibcon#about to read 4, iclass 30, count 0 2006.257.18:42:19.15#ibcon#read 4, iclass 30, count 0 2006.257.18:42:19.15#ibcon#about to read 5, iclass 30, count 0 2006.257.18:42:19.15#ibcon#read 5, iclass 30, count 0 2006.257.18:42:19.15#ibcon#about to read 6, iclass 30, count 0 2006.257.18:42:19.15#ibcon#read 6, iclass 30, count 0 2006.257.18:42:19.15#ibcon#end of sib2, iclass 30, count 0 2006.257.18:42:19.15#ibcon#*after write, iclass 30, count 0 2006.257.18:42:19.15#ibcon#*before return 0, iclass 30, count 0 2006.257.18:42:19.15#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:19.15#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:19.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.18:42:19.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.18:42:19.15$vck44/valo=3,564.99 2006.257.18:42:19.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.18:42:19.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.18:42:19.15#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:19.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:19.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:19.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:19.15#ibcon#enter wrdev, iclass 32, count 0 2006.257.18:42:19.15#ibcon#first serial, iclass 32, count 0 2006.257.18:42:19.15#ibcon#enter sib2, iclass 32, count 0 2006.257.18:42:19.15#ibcon#flushed, iclass 32, count 0 2006.257.18:42:19.15#ibcon#about to write, iclass 32, count 0 2006.257.18:42:19.15#ibcon#wrote, iclass 32, count 0 2006.257.18:42:19.15#ibcon#about to read 3, iclass 32, count 0 2006.257.18:42:19.17#ibcon#read 3, iclass 32, count 0 2006.257.18:42:19.17#ibcon#about to read 4, iclass 32, count 0 2006.257.18:42:19.17#ibcon#read 4, iclass 32, count 0 2006.257.18:42:19.17#ibcon#about to read 5, iclass 32, count 0 2006.257.18:42:19.17#ibcon#read 5, iclass 32, count 0 2006.257.18:42:19.17#ibcon#about to read 6, iclass 32, count 0 2006.257.18:42:19.17#ibcon#read 6, iclass 32, count 0 2006.257.18:42:19.17#ibcon#end of sib2, iclass 32, count 0 2006.257.18:42:19.17#ibcon#*mode == 0, iclass 32, count 0 2006.257.18:42:19.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.18:42:19.17#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:42:19.17#ibcon#*before write, iclass 32, count 0 2006.257.18:42:19.17#ibcon#enter sib2, iclass 32, count 0 2006.257.18:42:19.17#ibcon#flushed, iclass 32, count 0 2006.257.18:42:19.17#ibcon#about to write, iclass 32, count 0 2006.257.18:42:19.17#ibcon#wrote, iclass 32, count 0 2006.257.18:42:19.17#ibcon#about to read 3, iclass 32, count 0 2006.257.18:42:19.21#ibcon#read 3, iclass 32, count 0 2006.257.18:42:19.21#ibcon#about to read 4, iclass 32, count 0 2006.257.18:42:19.21#ibcon#read 4, iclass 32, count 0 2006.257.18:42:19.21#ibcon#about to read 5, iclass 32, count 0 2006.257.18:42:19.21#ibcon#read 5, iclass 32, count 0 2006.257.18:42:19.21#ibcon#about to read 6, iclass 32, count 0 2006.257.18:42:19.21#ibcon#read 6, iclass 32, count 0 2006.257.18:42:19.21#ibcon#end of sib2, iclass 32, count 0 2006.257.18:42:19.21#ibcon#*after write, iclass 32, count 0 2006.257.18:42:19.21#ibcon#*before return 0, iclass 32, count 0 2006.257.18:42:19.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:19.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:19.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.18:42:19.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.18:42:19.21$vck44/va=3,8 2006.257.18:42:19.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.18:42:19.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.18:42:19.21#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:19.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:19.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:19.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:19.27#ibcon#enter wrdev, iclass 34, count 2 2006.257.18:42:19.27#ibcon#first serial, iclass 34, count 2 2006.257.18:42:19.27#ibcon#enter sib2, iclass 34, count 2 2006.257.18:42:19.27#ibcon#flushed, iclass 34, count 2 2006.257.18:42:19.27#ibcon#about to write, iclass 34, count 2 2006.257.18:42:19.27#ibcon#wrote, iclass 34, count 2 2006.257.18:42:19.27#ibcon#about to read 3, iclass 34, count 2 2006.257.18:42:19.29#ibcon#read 3, iclass 34, count 2 2006.257.18:42:19.29#ibcon#about to read 4, iclass 34, count 2 2006.257.18:42:19.29#ibcon#read 4, iclass 34, count 2 2006.257.18:42:19.29#ibcon#about to read 5, iclass 34, count 2 2006.257.18:42:19.29#ibcon#read 5, iclass 34, count 2 2006.257.18:42:19.29#ibcon#about to read 6, iclass 34, count 2 2006.257.18:42:19.29#ibcon#read 6, iclass 34, count 2 2006.257.18:42:19.29#ibcon#end of sib2, iclass 34, count 2 2006.257.18:42:19.29#ibcon#*mode == 0, iclass 34, count 2 2006.257.18:42:19.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.18:42:19.29#ibcon#[25=AT03-08\r\n] 2006.257.18:42:19.29#ibcon#*before write, iclass 34, count 2 2006.257.18:42:19.29#ibcon#enter sib2, iclass 34, count 2 2006.257.18:42:19.29#ibcon#flushed, iclass 34, count 2 2006.257.18:42:19.29#ibcon#about to write, iclass 34, count 2 2006.257.18:42:19.29#ibcon#wrote, iclass 34, count 2 2006.257.18:42:19.29#ibcon#about to read 3, iclass 34, count 2 2006.257.18:42:19.32#ibcon#read 3, iclass 34, count 2 2006.257.18:42:19.32#ibcon#about to read 4, iclass 34, count 2 2006.257.18:42:19.32#ibcon#read 4, iclass 34, count 2 2006.257.18:42:19.32#ibcon#about to read 5, iclass 34, count 2 2006.257.18:42:19.32#ibcon#read 5, iclass 34, count 2 2006.257.18:42:19.32#ibcon#about to read 6, iclass 34, count 2 2006.257.18:42:19.32#ibcon#read 6, iclass 34, count 2 2006.257.18:42:19.32#ibcon#end of sib2, iclass 34, count 2 2006.257.18:42:19.32#ibcon#*after write, iclass 34, count 2 2006.257.18:42:19.32#ibcon#*before return 0, iclass 34, count 2 2006.257.18:42:19.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:19.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:19.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.18:42:19.32#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:19.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:19.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:19.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:19.44#ibcon#enter wrdev, iclass 34, count 0 2006.257.18:42:19.44#ibcon#first serial, iclass 34, count 0 2006.257.18:42:19.44#ibcon#enter sib2, iclass 34, count 0 2006.257.18:42:19.44#ibcon#flushed, iclass 34, count 0 2006.257.18:42:19.44#ibcon#about to write, iclass 34, count 0 2006.257.18:42:19.44#ibcon#wrote, iclass 34, count 0 2006.257.18:42:19.44#ibcon#about to read 3, iclass 34, count 0 2006.257.18:42:19.46#ibcon#read 3, iclass 34, count 0 2006.257.18:42:19.46#ibcon#about to read 4, iclass 34, count 0 2006.257.18:42:19.46#ibcon#read 4, iclass 34, count 0 2006.257.18:42:19.46#ibcon#about to read 5, iclass 34, count 0 2006.257.18:42:19.46#ibcon#read 5, iclass 34, count 0 2006.257.18:42:19.46#ibcon#about to read 6, iclass 34, count 0 2006.257.18:42:19.46#ibcon#read 6, iclass 34, count 0 2006.257.18:42:19.46#ibcon#end of sib2, iclass 34, count 0 2006.257.18:42:19.46#ibcon#*mode == 0, iclass 34, count 0 2006.257.18:42:19.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.18:42:19.46#ibcon#[25=USB\r\n] 2006.257.18:42:19.46#ibcon#*before write, iclass 34, count 0 2006.257.18:42:19.46#ibcon#enter sib2, iclass 34, count 0 2006.257.18:42:19.46#ibcon#flushed, iclass 34, count 0 2006.257.18:42:19.46#ibcon#about to write, iclass 34, count 0 2006.257.18:42:19.46#ibcon#wrote, iclass 34, count 0 2006.257.18:42:19.46#ibcon#about to read 3, iclass 34, count 0 2006.257.18:42:19.49#ibcon#read 3, iclass 34, count 0 2006.257.18:42:19.49#ibcon#about to read 4, iclass 34, count 0 2006.257.18:42:19.49#ibcon#read 4, iclass 34, count 0 2006.257.18:42:19.49#ibcon#about to read 5, iclass 34, count 0 2006.257.18:42:19.49#ibcon#read 5, iclass 34, count 0 2006.257.18:42:19.49#ibcon#about to read 6, iclass 34, count 0 2006.257.18:42:19.49#ibcon#read 6, iclass 34, count 0 2006.257.18:42:19.49#ibcon#end of sib2, iclass 34, count 0 2006.257.18:42:19.49#ibcon#*after write, iclass 34, count 0 2006.257.18:42:19.49#ibcon#*before return 0, iclass 34, count 0 2006.257.18:42:19.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:19.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:19.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.18:42:19.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.18:42:19.49$vck44/valo=4,624.99 2006.257.18:42:19.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.18:42:19.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.18:42:19.49#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:19.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:19.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:19.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:19.49#ibcon#enter wrdev, iclass 36, count 0 2006.257.18:42:19.49#ibcon#first serial, iclass 36, count 0 2006.257.18:42:19.49#ibcon#enter sib2, iclass 36, count 0 2006.257.18:42:19.49#ibcon#flushed, iclass 36, count 0 2006.257.18:42:19.49#ibcon#about to write, iclass 36, count 0 2006.257.18:42:19.49#ibcon#wrote, iclass 36, count 0 2006.257.18:42:19.49#ibcon#about to read 3, iclass 36, count 0 2006.257.18:42:19.51#ibcon#read 3, iclass 36, count 0 2006.257.18:42:19.51#ibcon#about to read 4, iclass 36, count 0 2006.257.18:42:19.51#ibcon#read 4, iclass 36, count 0 2006.257.18:42:19.51#ibcon#about to read 5, iclass 36, count 0 2006.257.18:42:19.51#ibcon#read 5, iclass 36, count 0 2006.257.18:42:19.51#ibcon#about to read 6, iclass 36, count 0 2006.257.18:42:19.51#ibcon#read 6, iclass 36, count 0 2006.257.18:42:19.51#ibcon#end of sib2, iclass 36, count 0 2006.257.18:42:19.51#ibcon#*mode == 0, iclass 36, count 0 2006.257.18:42:19.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.18:42:19.51#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:42:19.51#ibcon#*before write, iclass 36, count 0 2006.257.18:42:19.51#ibcon#enter sib2, iclass 36, count 0 2006.257.18:42:19.51#ibcon#flushed, iclass 36, count 0 2006.257.18:42:19.51#ibcon#about to write, iclass 36, count 0 2006.257.18:42:19.51#ibcon#wrote, iclass 36, count 0 2006.257.18:42:19.51#ibcon#about to read 3, iclass 36, count 0 2006.257.18:42:19.55#ibcon#read 3, iclass 36, count 0 2006.257.18:42:19.55#ibcon#about to read 4, iclass 36, count 0 2006.257.18:42:19.55#ibcon#read 4, iclass 36, count 0 2006.257.18:42:19.55#ibcon#about to read 5, iclass 36, count 0 2006.257.18:42:19.55#ibcon#read 5, iclass 36, count 0 2006.257.18:42:19.55#ibcon#about to read 6, iclass 36, count 0 2006.257.18:42:19.55#ibcon#read 6, iclass 36, count 0 2006.257.18:42:19.55#ibcon#end of sib2, iclass 36, count 0 2006.257.18:42:19.55#ibcon#*after write, iclass 36, count 0 2006.257.18:42:19.55#ibcon#*before return 0, iclass 36, count 0 2006.257.18:42:19.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:19.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:19.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.18:42:19.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.18:42:19.55$vck44/va=4,7 2006.257.18:42:19.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.18:42:19.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.18:42:19.55#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:19.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:19.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:19.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:19.61#ibcon#enter wrdev, iclass 38, count 2 2006.257.18:42:19.61#ibcon#first serial, iclass 38, count 2 2006.257.18:42:19.61#ibcon#enter sib2, iclass 38, count 2 2006.257.18:42:19.61#ibcon#flushed, iclass 38, count 2 2006.257.18:42:19.61#ibcon#about to write, iclass 38, count 2 2006.257.18:42:19.61#ibcon#wrote, iclass 38, count 2 2006.257.18:42:19.61#ibcon#about to read 3, iclass 38, count 2 2006.257.18:42:19.63#ibcon#read 3, iclass 38, count 2 2006.257.18:42:19.63#ibcon#about to read 4, iclass 38, count 2 2006.257.18:42:19.63#ibcon#read 4, iclass 38, count 2 2006.257.18:42:19.63#ibcon#about to read 5, iclass 38, count 2 2006.257.18:42:19.63#ibcon#read 5, iclass 38, count 2 2006.257.18:42:19.63#ibcon#about to read 6, iclass 38, count 2 2006.257.18:42:19.63#ibcon#read 6, iclass 38, count 2 2006.257.18:42:19.63#ibcon#end of sib2, iclass 38, count 2 2006.257.18:42:19.63#ibcon#*mode == 0, iclass 38, count 2 2006.257.18:42:19.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.18:42:19.63#ibcon#[25=AT04-07\r\n] 2006.257.18:42:19.63#ibcon#*before write, iclass 38, count 2 2006.257.18:42:19.63#ibcon#enter sib2, iclass 38, count 2 2006.257.18:42:19.63#ibcon#flushed, iclass 38, count 2 2006.257.18:42:19.63#ibcon#about to write, iclass 38, count 2 2006.257.18:42:19.63#ibcon#wrote, iclass 38, count 2 2006.257.18:42:19.63#ibcon#about to read 3, iclass 38, count 2 2006.257.18:42:19.66#ibcon#read 3, iclass 38, count 2 2006.257.18:42:19.66#ibcon#about to read 4, iclass 38, count 2 2006.257.18:42:19.66#ibcon#read 4, iclass 38, count 2 2006.257.18:42:19.66#ibcon#about to read 5, iclass 38, count 2 2006.257.18:42:19.66#ibcon#read 5, iclass 38, count 2 2006.257.18:42:19.66#ibcon#about to read 6, iclass 38, count 2 2006.257.18:42:19.66#ibcon#read 6, iclass 38, count 2 2006.257.18:42:19.66#ibcon#end of sib2, iclass 38, count 2 2006.257.18:42:19.66#ibcon#*after write, iclass 38, count 2 2006.257.18:42:19.66#ibcon#*before return 0, iclass 38, count 2 2006.257.18:42:19.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:19.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:19.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.18:42:19.66#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:19.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:19.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:19.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:19.78#ibcon#enter wrdev, iclass 38, count 0 2006.257.18:42:19.78#ibcon#first serial, iclass 38, count 0 2006.257.18:42:19.78#ibcon#enter sib2, iclass 38, count 0 2006.257.18:42:19.78#ibcon#flushed, iclass 38, count 0 2006.257.18:42:19.78#ibcon#about to write, iclass 38, count 0 2006.257.18:42:19.78#ibcon#wrote, iclass 38, count 0 2006.257.18:42:19.78#ibcon#about to read 3, iclass 38, count 0 2006.257.18:42:19.80#ibcon#read 3, iclass 38, count 0 2006.257.18:42:19.80#ibcon#about to read 4, iclass 38, count 0 2006.257.18:42:19.80#ibcon#read 4, iclass 38, count 0 2006.257.18:42:19.80#ibcon#about to read 5, iclass 38, count 0 2006.257.18:42:19.80#ibcon#read 5, iclass 38, count 0 2006.257.18:42:19.80#ibcon#about to read 6, iclass 38, count 0 2006.257.18:42:19.80#ibcon#read 6, iclass 38, count 0 2006.257.18:42:19.80#ibcon#end of sib2, iclass 38, count 0 2006.257.18:42:19.80#ibcon#*mode == 0, iclass 38, count 0 2006.257.18:42:19.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.18:42:19.80#ibcon#[25=USB\r\n] 2006.257.18:42:19.80#ibcon#*before write, iclass 38, count 0 2006.257.18:42:19.80#ibcon#enter sib2, iclass 38, count 0 2006.257.18:42:19.80#ibcon#flushed, iclass 38, count 0 2006.257.18:42:19.80#ibcon#about to write, iclass 38, count 0 2006.257.18:42:19.80#ibcon#wrote, iclass 38, count 0 2006.257.18:42:19.80#ibcon#about to read 3, iclass 38, count 0 2006.257.18:42:19.83#ibcon#read 3, iclass 38, count 0 2006.257.18:42:19.83#ibcon#about to read 4, iclass 38, count 0 2006.257.18:42:19.83#ibcon#read 4, iclass 38, count 0 2006.257.18:42:19.83#ibcon#about to read 5, iclass 38, count 0 2006.257.18:42:19.83#ibcon#read 5, iclass 38, count 0 2006.257.18:42:19.83#ibcon#about to read 6, iclass 38, count 0 2006.257.18:42:19.83#ibcon#read 6, iclass 38, count 0 2006.257.18:42:19.83#ibcon#end of sib2, iclass 38, count 0 2006.257.18:42:19.83#ibcon#*after write, iclass 38, count 0 2006.257.18:42:19.83#ibcon#*before return 0, iclass 38, count 0 2006.257.18:42:19.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:19.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:19.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.18:42:19.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.18:42:19.83$vck44/valo=5,734.99 2006.257.18:42:19.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.18:42:19.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.18:42:19.83#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:19.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:19.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:19.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:19.83#ibcon#enter wrdev, iclass 40, count 0 2006.257.18:42:19.83#ibcon#first serial, iclass 40, count 0 2006.257.18:42:19.83#ibcon#enter sib2, iclass 40, count 0 2006.257.18:42:19.83#ibcon#flushed, iclass 40, count 0 2006.257.18:42:19.83#ibcon#about to write, iclass 40, count 0 2006.257.18:42:19.83#ibcon#wrote, iclass 40, count 0 2006.257.18:42:19.83#ibcon#about to read 3, iclass 40, count 0 2006.257.18:42:19.85#ibcon#read 3, iclass 40, count 0 2006.257.18:42:19.85#ibcon#about to read 4, iclass 40, count 0 2006.257.18:42:19.85#ibcon#read 4, iclass 40, count 0 2006.257.18:42:19.85#ibcon#about to read 5, iclass 40, count 0 2006.257.18:42:19.85#ibcon#read 5, iclass 40, count 0 2006.257.18:42:19.85#ibcon#about to read 6, iclass 40, count 0 2006.257.18:42:19.85#ibcon#read 6, iclass 40, count 0 2006.257.18:42:19.85#ibcon#end of sib2, iclass 40, count 0 2006.257.18:42:19.85#ibcon#*mode == 0, iclass 40, count 0 2006.257.18:42:19.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.18:42:19.85#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:42:19.85#ibcon#*before write, iclass 40, count 0 2006.257.18:42:19.85#ibcon#enter sib2, iclass 40, count 0 2006.257.18:42:19.85#ibcon#flushed, iclass 40, count 0 2006.257.18:42:19.85#ibcon#about to write, iclass 40, count 0 2006.257.18:42:19.85#ibcon#wrote, iclass 40, count 0 2006.257.18:42:19.85#ibcon#about to read 3, iclass 40, count 0 2006.257.18:42:19.89#ibcon#read 3, iclass 40, count 0 2006.257.18:42:19.89#ibcon#about to read 4, iclass 40, count 0 2006.257.18:42:19.89#ibcon#read 4, iclass 40, count 0 2006.257.18:42:19.89#ibcon#about to read 5, iclass 40, count 0 2006.257.18:42:19.89#ibcon#read 5, iclass 40, count 0 2006.257.18:42:19.89#ibcon#about to read 6, iclass 40, count 0 2006.257.18:42:19.89#ibcon#read 6, iclass 40, count 0 2006.257.18:42:19.89#ibcon#end of sib2, iclass 40, count 0 2006.257.18:42:19.89#ibcon#*after write, iclass 40, count 0 2006.257.18:42:19.89#ibcon#*before return 0, iclass 40, count 0 2006.257.18:42:19.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:19.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:19.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.18:42:19.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.18:42:19.89$vck44/va=5,4 2006.257.18:42:19.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.18:42:19.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.18:42:19.89#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:19.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:19.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:19.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:19.95#ibcon#enter wrdev, iclass 4, count 2 2006.257.18:42:19.95#ibcon#first serial, iclass 4, count 2 2006.257.18:42:19.95#ibcon#enter sib2, iclass 4, count 2 2006.257.18:42:19.95#ibcon#flushed, iclass 4, count 2 2006.257.18:42:19.95#ibcon#about to write, iclass 4, count 2 2006.257.18:42:19.95#ibcon#wrote, iclass 4, count 2 2006.257.18:42:19.95#ibcon#about to read 3, iclass 4, count 2 2006.257.18:42:19.97#ibcon#read 3, iclass 4, count 2 2006.257.18:42:19.97#ibcon#about to read 4, iclass 4, count 2 2006.257.18:42:19.97#ibcon#read 4, iclass 4, count 2 2006.257.18:42:19.97#ibcon#about to read 5, iclass 4, count 2 2006.257.18:42:19.97#ibcon#read 5, iclass 4, count 2 2006.257.18:42:19.97#ibcon#about to read 6, iclass 4, count 2 2006.257.18:42:19.97#ibcon#read 6, iclass 4, count 2 2006.257.18:42:19.97#ibcon#end of sib2, iclass 4, count 2 2006.257.18:42:19.97#ibcon#*mode == 0, iclass 4, count 2 2006.257.18:42:19.97#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.18:42:19.97#ibcon#[25=AT05-04\r\n] 2006.257.18:42:19.97#ibcon#*before write, iclass 4, count 2 2006.257.18:42:19.97#ibcon#enter sib2, iclass 4, count 2 2006.257.18:42:19.97#ibcon#flushed, iclass 4, count 2 2006.257.18:42:19.97#ibcon#about to write, iclass 4, count 2 2006.257.18:42:19.97#ibcon#wrote, iclass 4, count 2 2006.257.18:42:19.97#ibcon#about to read 3, iclass 4, count 2 2006.257.18:42:20.00#ibcon#read 3, iclass 4, count 2 2006.257.18:42:20.00#ibcon#about to read 4, iclass 4, count 2 2006.257.18:42:20.00#ibcon#read 4, iclass 4, count 2 2006.257.18:42:20.00#ibcon#about to read 5, iclass 4, count 2 2006.257.18:42:20.00#ibcon#read 5, iclass 4, count 2 2006.257.18:42:20.00#ibcon#about to read 6, iclass 4, count 2 2006.257.18:42:20.00#ibcon#read 6, iclass 4, count 2 2006.257.18:42:20.00#ibcon#end of sib2, iclass 4, count 2 2006.257.18:42:20.00#ibcon#*after write, iclass 4, count 2 2006.257.18:42:20.00#ibcon#*before return 0, iclass 4, count 2 2006.257.18:42:20.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:20.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:20.00#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.18:42:20.00#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:20.00#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:20.12#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:20.12#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:20.12#ibcon#enter wrdev, iclass 4, count 0 2006.257.18:42:20.12#ibcon#first serial, iclass 4, count 0 2006.257.18:42:20.12#ibcon#enter sib2, iclass 4, count 0 2006.257.18:42:20.12#ibcon#flushed, iclass 4, count 0 2006.257.18:42:20.12#ibcon#about to write, iclass 4, count 0 2006.257.18:42:20.12#ibcon#wrote, iclass 4, count 0 2006.257.18:42:20.12#ibcon#about to read 3, iclass 4, count 0 2006.257.18:42:20.14#ibcon#read 3, iclass 4, count 0 2006.257.18:42:20.14#ibcon#about to read 4, iclass 4, count 0 2006.257.18:42:20.14#ibcon#read 4, iclass 4, count 0 2006.257.18:42:20.14#ibcon#about to read 5, iclass 4, count 0 2006.257.18:42:20.14#ibcon#read 5, iclass 4, count 0 2006.257.18:42:20.14#ibcon#about to read 6, iclass 4, count 0 2006.257.18:42:20.14#ibcon#read 6, iclass 4, count 0 2006.257.18:42:20.14#ibcon#end of sib2, iclass 4, count 0 2006.257.18:42:20.14#ibcon#*mode == 0, iclass 4, count 0 2006.257.18:42:20.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.18:42:20.14#ibcon#[25=USB\r\n] 2006.257.18:42:20.14#ibcon#*before write, iclass 4, count 0 2006.257.18:42:20.14#ibcon#enter sib2, iclass 4, count 0 2006.257.18:42:20.14#ibcon#flushed, iclass 4, count 0 2006.257.18:42:20.14#ibcon#about to write, iclass 4, count 0 2006.257.18:42:20.14#ibcon#wrote, iclass 4, count 0 2006.257.18:42:20.14#ibcon#about to read 3, iclass 4, count 0 2006.257.18:42:20.17#ibcon#read 3, iclass 4, count 0 2006.257.18:42:20.17#ibcon#about to read 4, iclass 4, count 0 2006.257.18:42:20.17#ibcon#read 4, iclass 4, count 0 2006.257.18:42:20.17#ibcon#about to read 5, iclass 4, count 0 2006.257.18:42:20.17#ibcon#read 5, iclass 4, count 0 2006.257.18:42:20.17#ibcon#about to read 6, iclass 4, count 0 2006.257.18:42:20.17#ibcon#read 6, iclass 4, count 0 2006.257.18:42:20.17#ibcon#end of sib2, iclass 4, count 0 2006.257.18:42:20.17#ibcon#*after write, iclass 4, count 0 2006.257.18:42:20.17#ibcon#*before return 0, iclass 4, count 0 2006.257.18:42:20.17#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:20.17#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:20.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.18:42:20.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.18:42:20.17$vck44/valo=6,814.99 2006.257.18:42:20.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.18:42:20.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.18:42:20.17#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:20.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:20.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:20.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:20.17#ibcon#enter wrdev, iclass 6, count 0 2006.257.18:42:20.17#ibcon#first serial, iclass 6, count 0 2006.257.18:42:20.17#ibcon#enter sib2, iclass 6, count 0 2006.257.18:42:20.17#ibcon#flushed, iclass 6, count 0 2006.257.18:42:20.17#ibcon#about to write, iclass 6, count 0 2006.257.18:42:20.17#ibcon#wrote, iclass 6, count 0 2006.257.18:42:20.17#ibcon#about to read 3, iclass 6, count 0 2006.257.18:42:20.19#ibcon#read 3, iclass 6, count 0 2006.257.18:42:20.19#ibcon#about to read 4, iclass 6, count 0 2006.257.18:42:20.19#ibcon#read 4, iclass 6, count 0 2006.257.18:42:20.19#ibcon#about to read 5, iclass 6, count 0 2006.257.18:42:20.19#ibcon#read 5, iclass 6, count 0 2006.257.18:42:20.19#ibcon#about to read 6, iclass 6, count 0 2006.257.18:42:20.19#ibcon#read 6, iclass 6, count 0 2006.257.18:42:20.19#ibcon#end of sib2, iclass 6, count 0 2006.257.18:42:20.19#ibcon#*mode == 0, iclass 6, count 0 2006.257.18:42:20.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.18:42:20.19#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:42:20.19#ibcon#*before write, iclass 6, count 0 2006.257.18:42:20.19#ibcon#enter sib2, iclass 6, count 0 2006.257.18:42:20.19#ibcon#flushed, iclass 6, count 0 2006.257.18:42:20.19#ibcon#about to write, iclass 6, count 0 2006.257.18:42:20.19#ibcon#wrote, iclass 6, count 0 2006.257.18:42:20.19#ibcon#about to read 3, iclass 6, count 0 2006.257.18:42:20.23#ibcon#read 3, iclass 6, count 0 2006.257.18:42:20.23#ibcon#about to read 4, iclass 6, count 0 2006.257.18:42:20.23#ibcon#read 4, iclass 6, count 0 2006.257.18:42:20.23#ibcon#about to read 5, iclass 6, count 0 2006.257.18:42:20.23#ibcon#read 5, iclass 6, count 0 2006.257.18:42:20.23#ibcon#about to read 6, iclass 6, count 0 2006.257.18:42:20.23#ibcon#read 6, iclass 6, count 0 2006.257.18:42:20.23#ibcon#end of sib2, iclass 6, count 0 2006.257.18:42:20.23#ibcon#*after write, iclass 6, count 0 2006.257.18:42:20.23#ibcon#*before return 0, iclass 6, count 0 2006.257.18:42:20.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:20.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:20.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.18:42:20.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.18:42:20.23$vck44/va=6,4 2006.257.18:42:20.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.18:42:20.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.18:42:20.23#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:20.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:20.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:20.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:20.29#ibcon#enter wrdev, iclass 10, count 2 2006.257.18:42:20.29#ibcon#first serial, iclass 10, count 2 2006.257.18:42:20.29#ibcon#enter sib2, iclass 10, count 2 2006.257.18:42:20.29#ibcon#flushed, iclass 10, count 2 2006.257.18:42:20.29#ibcon#about to write, iclass 10, count 2 2006.257.18:42:20.29#ibcon#wrote, iclass 10, count 2 2006.257.18:42:20.29#ibcon#about to read 3, iclass 10, count 2 2006.257.18:42:20.31#ibcon#read 3, iclass 10, count 2 2006.257.18:42:20.31#ibcon#about to read 4, iclass 10, count 2 2006.257.18:42:20.31#ibcon#read 4, iclass 10, count 2 2006.257.18:42:20.31#ibcon#about to read 5, iclass 10, count 2 2006.257.18:42:20.31#ibcon#read 5, iclass 10, count 2 2006.257.18:42:20.31#ibcon#about to read 6, iclass 10, count 2 2006.257.18:42:20.31#ibcon#read 6, iclass 10, count 2 2006.257.18:42:20.31#ibcon#end of sib2, iclass 10, count 2 2006.257.18:42:20.31#ibcon#*mode == 0, iclass 10, count 2 2006.257.18:42:20.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.18:42:20.31#ibcon#[25=AT06-04\r\n] 2006.257.18:42:20.31#ibcon#*before write, iclass 10, count 2 2006.257.18:42:20.31#ibcon#enter sib2, iclass 10, count 2 2006.257.18:42:20.31#ibcon#flushed, iclass 10, count 2 2006.257.18:42:20.31#ibcon#about to write, iclass 10, count 2 2006.257.18:42:20.31#ibcon#wrote, iclass 10, count 2 2006.257.18:42:20.31#ibcon#about to read 3, iclass 10, count 2 2006.257.18:42:20.34#ibcon#read 3, iclass 10, count 2 2006.257.18:42:20.34#ibcon#about to read 4, iclass 10, count 2 2006.257.18:42:20.34#ibcon#read 4, iclass 10, count 2 2006.257.18:42:20.34#ibcon#about to read 5, iclass 10, count 2 2006.257.18:42:20.34#ibcon#read 5, iclass 10, count 2 2006.257.18:42:20.34#ibcon#about to read 6, iclass 10, count 2 2006.257.18:42:20.34#ibcon#read 6, iclass 10, count 2 2006.257.18:42:20.34#ibcon#end of sib2, iclass 10, count 2 2006.257.18:42:20.34#ibcon#*after write, iclass 10, count 2 2006.257.18:42:20.34#ibcon#*before return 0, iclass 10, count 2 2006.257.18:42:20.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:20.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:20.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.18:42:20.34#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:20.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:20.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:20.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:20.46#ibcon#enter wrdev, iclass 10, count 0 2006.257.18:42:20.46#ibcon#first serial, iclass 10, count 0 2006.257.18:42:20.46#ibcon#enter sib2, iclass 10, count 0 2006.257.18:42:20.46#ibcon#flushed, iclass 10, count 0 2006.257.18:42:20.46#ibcon#about to write, iclass 10, count 0 2006.257.18:42:20.46#ibcon#wrote, iclass 10, count 0 2006.257.18:42:20.46#ibcon#about to read 3, iclass 10, count 0 2006.257.18:42:20.48#ibcon#read 3, iclass 10, count 0 2006.257.18:42:20.48#ibcon#about to read 4, iclass 10, count 0 2006.257.18:42:20.48#ibcon#read 4, iclass 10, count 0 2006.257.18:42:20.48#ibcon#about to read 5, iclass 10, count 0 2006.257.18:42:20.48#ibcon#read 5, iclass 10, count 0 2006.257.18:42:20.48#ibcon#about to read 6, iclass 10, count 0 2006.257.18:42:20.48#ibcon#read 6, iclass 10, count 0 2006.257.18:42:20.48#ibcon#end of sib2, iclass 10, count 0 2006.257.18:42:20.48#ibcon#*mode == 0, iclass 10, count 0 2006.257.18:42:20.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.18:42:20.48#ibcon#[25=USB\r\n] 2006.257.18:42:20.48#ibcon#*before write, iclass 10, count 0 2006.257.18:42:20.48#ibcon#enter sib2, iclass 10, count 0 2006.257.18:42:20.48#ibcon#flushed, iclass 10, count 0 2006.257.18:42:20.48#ibcon#about to write, iclass 10, count 0 2006.257.18:42:20.48#ibcon#wrote, iclass 10, count 0 2006.257.18:42:20.48#ibcon#about to read 3, iclass 10, count 0 2006.257.18:42:20.51#ibcon#read 3, iclass 10, count 0 2006.257.18:42:20.51#ibcon#about to read 4, iclass 10, count 0 2006.257.18:42:20.51#ibcon#read 4, iclass 10, count 0 2006.257.18:42:20.51#ibcon#about to read 5, iclass 10, count 0 2006.257.18:42:20.51#ibcon#read 5, iclass 10, count 0 2006.257.18:42:20.51#ibcon#about to read 6, iclass 10, count 0 2006.257.18:42:20.51#ibcon#read 6, iclass 10, count 0 2006.257.18:42:20.51#ibcon#end of sib2, iclass 10, count 0 2006.257.18:42:20.51#ibcon#*after write, iclass 10, count 0 2006.257.18:42:20.51#ibcon#*before return 0, iclass 10, count 0 2006.257.18:42:20.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:20.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:20.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.18:42:20.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.18:42:20.51$vck44/valo=7,864.99 2006.257.18:42:20.51#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.18:42:20.51#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.18:42:20.51#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:20.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:42:20.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:42:20.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:42:20.51#ibcon#enter wrdev, iclass 12, count 0 2006.257.18:42:20.51#ibcon#first serial, iclass 12, count 0 2006.257.18:42:20.51#ibcon#enter sib2, iclass 12, count 0 2006.257.18:42:20.51#ibcon#flushed, iclass 12, count 0 2006.257.18:42:20.51#ibcon#about to write, iclass 12, count 0 2006.257.18:42:20.51#ibcon#wrote, iclass 12, count 0 2006.257.18:42:20.51#ibcon#about to read 3, iclass 12, count 0 2006.257.18:42:20.53#ibcon#read 3, iclass 12, count 0 2006.257.18:42:20.53#ibcon#about to read 4, iclass 12, count 0 2006.257.18:42:20.53#ibcon#read 4, iclass 12, count 0 2006.257.18:42:20.53#ibcon#about to read 5, iclass 12, count 0 2006.257.18:42:20.53#ibcon#read 5, iclass 12, count 0 2006.257.18:42:20.53#ibcon#about to read 6, iclass 12, count 0 2006.257.18:42:20.53#ibcon#read 6, iclass 12, count 0 2006.257.18:42:20.53#ibcon#end of sib2, iclass 12, count 0 2006.257.18:42:20.53#ibcon#*mode == 0, iclass 12, count 0 2006.257.18:42:20.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.18:42:20.53#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:42:20.53#ibcon#*before write, iclass 12, count 0 2006.257.18:42:20.53#ibcon#enter sib2, iclass 12, count 0 2006.257.18:42:20.53#ibcon#flushed, iclass 12, count 0 2006.257.18:42:20.53#ibcon#about to write, iclass 12, count 0 2006.257.18:42:20.53#ibcon#wrote, iclass 12, count 0 2006.257.18:42:20.53#ibcon#about to read 3, iclass 12, count 0 2006.257.18:42:20.57#ibcon#read 3, iclass 12, count 0 2006.257.18:42:20.57#ibcon#about to read 4, iclass 12, count 0 2006.257.18:42:20.57#ibcon#read 4, iclass 12, count 0 2006.257.18:42:20.57#ibcon#about to read 5, iclass 12, count 0 2006.257.18:42:20.57#ibcon#read 5, iclass 12, count 0 2006.257.18:42:20.57#ibcon#about to read 6, iclass 12, count 0 2006.257.18:42:20.57#ibcon#read 6, iclass 12, count 0 2006.257.18:42:20.57#ibcon#end of sib2, iclass 12, count 0 2006.257.18:42:20.57#ibcon#*after write, iclass 12, count 0 2006.257.18:42:20.57#ibcon#*before return 0, iclass 12, count 0 2006.257.18:42:20.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:42:20.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:42:20.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.18:42:20.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.18:42:20.57$vck44/va=7,4 2006.257.18:42:20.57#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.18:42:20.57#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.18:42:20.57#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:20.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:42:20.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:42:20.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:42:20.63#ibcon#enter wrdev, iclass 14, count 2 2006.257.18:42:20.63#ibcon#first serial, iclass 14, count 2 2006.257.18:42:20.63#ibcon#enter sib2, iclass 14, count 2 2006.257.18:42:20.63#ibcon#flushed, iclass 14, count 2 2006.257.18:42:20.63#ibcon#about to write, iclass 14, count 2 2006.257.18:42:20.63#ibcon#wrote, iclass 14, count 2 2006.257.18:42:20.63#ibcon#about to read 3, iclass 14, count 2 2006.257.18:42:20.65#ibcon#read 3, iclass 14, count 2 2006.257.18:42:20.65#ibcon#about to read 4, iclass 14, count 2 2006.257.18:42:20.65#ibcon#read 4, iclass 14, count 2 2006.257.18:42:20.65#ibcon#about to read 5, iclass 14, count 2 2006.257.18:42:20.65#ibcon#read 5, iclass 14, count 2 2006.257.18:42:20.65#ibcon#about to read 6, iclass 14, count 2 2006.257.18:42:20.65#ibcon#read 6, iclass 14, count 2 2006.257.18:42:20.65#ibcon#end of sib2, iclass 14, count 2 2006.257.18:42:20.65#ibcon#*mode == 0, iclass 14, count 2 2006.257.18:42:20.65#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.18:42:20.65#ibcon#[25=AT07-04\r\n] 2006.257.18:42:20.65#ibcon#*before write, iclass 14, count 2 2006.257.18:42:20.65#ibcon#enter sib2, iclass 14, count 2 2006.257.18:42:20.65#ibcon#flushed, iclass 14, count 2 2006.257.18:42:20.65#ibcon#about to write, iclass 14, count 2 2006.257.18:42:20.65#ibcon#wrote, iclass 14, count 2 2006.257.18:42:20.65#ibcon#about to read 3, iclass 14, count 2 2006.257.18:42:20.68#ibcon#read 3, iclass 14, count 2 2006.257.18:42:20.68#ibcon#about to read 4, iclass 14, count 2 2006.257.18:42:20.68#ibcon#read 4, iclass 14, count 2 2006.257.18:42:20.68#ibcon#about to read 5, iclass 14, count 2 2006.257.18:42:20.68#ibcon#read 5, iclass 14, count 2 2006.257.18:42:20.68#ibcon#about to read 6, iclass 14, count 2 2006.257.18:42:20.68#ibcon#read 6, iclass 14, count 2 2006.257.18:42:20.68#ibcon#end of sib2, iclass 14, count 2 2006.257.18:42:20.68#ibcon#*after write, iclass 14, count 2 2006.257.18:42:20.68#ibcon#*before return 0, iclass 14, count 2 2006.257.18:42:20.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:42:20.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.18:42:20.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.18:42:20.68#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:20.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:42:20.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:42:20.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:42:20.80#ibcon#enter wrdev, iclass 14, count 0 2006.257.18:42:20.80#ibcon#first serial, iclass 14, count 0 2006.257.18:42:20.80#ibcon#enter sib2, iclass 14, count 0 2006.257.18:42:20.80#ibcon#flushed, iclass 14, count 0 2006.257.18:42:20.80#ibcon#about to write, iclass 14, count 0 2006.257.18:42:20.80#ibcon#wrote, iclass 14, count 0 2006.257.18:42:20.80#ibcon#about to read 3, iclass 14, count 0 2006.257.18:42:20.82#ibcon#read 3, iclass 14, count 0 2006.257.18:42:20.82#ibcon#about to read 4, iclass 14, count 0 2006.257.18:42:20.82#ibcon#read 4, iclass 14, count 0 2006.257.18:42:20.82#ibcon#about to read 5, iclass 14, count 0 2006.257.18:42:20.82#ibcon#read 5, iclass 14, count 0 2006.257.18:42:20.82#ibcon#about to read 6, iclass 14, count 0 2006.257.18:42:20.82#ibcon#read 6, iclass 14, count 0 2006.257.18:42:20.82#ibcon#end of sib2, iclass 14, count 0 2006.257.18:42:20.82#ibcon#*mode == 0, iclass 14, count 0 2006.257.18:42:20.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.18:42:20.82#ibcon#[25=USB\r\n] 2006.257.18:42:20.82#ibcon#*before write, iclass 14, count 0 2006.257.18:42:20.82#ibcon#enter sib2, iclass 14, count 0 2006.257.18:42:20.82#ibcon#flushed, iclass 14, count 0 2006.257.18:42:20.82#ibcon#about to write, iclass 14, count 0 2006.257.18:42:20.82#ibcon#wrote, iclass 14, count 0 2006.257.18:42:20.82#ibcon#about to read 3, iclass 14, count 0 2006.257.18:42:20.85#ibcon#read 3, iclass 14, count 0 2006.257.18:42:20.85#ibcon#about to read 4, iclass 14, count 0 2006.257.18:42:20.85#ibcon#read 4, iclass 14, count 0 2006.257.18:42:20.85#ibcon#about to read 5, iclass 14, count 0 2006.257.18:42:20.85#ibcon#read 5, iclass 14, count 0 2006.257.18:42:20.85#ibcon#about to read 6, iclass 14, count 0 2006.257.18:42:20.85#ibcon#read 6, iclass 14, count 0 2006.257.18:42:20.85#ibcon#end of sib2, iclass 14, count 0 2006.257.18:42:20.85#ibcon#*after write, iclass 14, count 0 2006.257.18:42:20.85#ibcon#*before return 0, iclass 14, count 0 2006.257.18:42:20.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:42:20.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.18:42:20.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.18:42:20.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.18:42:20.85$vck44/valo=8,884.99 2006.257.18:42:20.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.18:42:20.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.18:42:20.85#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:20.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:42:20.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:42:20.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:42:20.85#ibcon#enter wrdev, iclass 16, count 0 2006.257.18:42:20.85#ibcon#first serial, iclass 16, count 0 2006.257.18:42:20.85#ibcon#enter sib2, iclass 16, count 0 2006.257.18:42:20.85#ibcon#flushed, iclass 16, count 0 2006.257.18:42:20.85#ibcon#about to write, iclass 16, count 0 2006.257.18:42:20.85#ibcon#wrote, iclass 16, count 0 2006.257.18:42:20.85#ibcon#about to read 3, iclass 16, count 0 2006.257.18:42:20.87#ibcon#read 3, iclass 16, count 0 2006.257.18:42:20.87#ibcon#about to read 4, iclass 16, count 0 2006.257.18:42:20.87#ibcon#read 4, iclass 16, count 0 2006.257.18:42:20.87#ibcon#about to read 5, iclass 16, count 0 2006.257.18:42:20.87#ibcon#read 5, iclass 16, count 0 2006.257.18:42:20.87#ibcon#about to read 6, iclass 16, count 0 2006.257.18:42:20.87#ibcon#read 6, iclass 16, count 0 2006.257.18:42:20.87#ibcon#end of sib2, iclass 16, count 0 2006.257.18:42:20.87#ibcon#*mode == 0, iclass 16, count 0 2006.257.18:42:20.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.18:42:20.87#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:42:20.87#ibcon#*before write, iclass 16, count 0 2006.257.18:42:20.87#ibcon#enter sib2, iclass 16, count 0 2006.257.18:42:20.87#ibcon#flushed, iclass 16, count 0 2006.257.18:42:20.87#ibcon#about to write, iclass 16, count 0 2006.257.18:42:20.87#ibcon#wrote, iclass 16, count 0 2006.257.18:42:20.87#ibcon#about to read 3, iclass 16, count 0 2006.257.18:42:20.91#ibcon#read 3, iclass 16, count 0 2006.257.18:42:20.91#ibcon#about to read 4, iclass 16, count 0 2006.257.18:42:20.91#ibcon#read 4, iclass 16, count 0 2006.257.18:42:20.91#ibcon#about to read 5, iclass 16, count 0 2006.257.18:42:20.91#ibcon#read 5, iclass 16, count 0 2006.257.18:42:20.91#ibcon#about to read 6, iclass 16, count 0 2006.257.18:42:20.91#ibcon#read 6, iclass 16, count 0 2006.257.18:42:20.91#ibcon#end of sib2, iclass 16, count 0 2006.257.18:42:20.91#ibcon#*after write, iclass 16, count 0 2006.257.18:42:20.91#ibcon#*before return 0, iclass 16, count 0 2006.257.18:42:20.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:42:20.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.18:42:20.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.18:42:20.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.18:42:20.91$vck44/va=8,4 2006.257.18:42:20.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.18:42:20.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.18:42:20.91#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:20.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:20.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:20.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:20.97#ibcon#enter wrdev, iclass 18, count 2 2006.257.18:42:20.97#ibcon#first serial, iclass 18, count 2 2006.257.18:42:20.97#ibcon#enter sib2, iclass 18, count 2 2006.257.18:42:20.97#ibcon#flushed, iclass 18, count 2 2006.257.18:42:20.97#ibcon#about to write, iclass 18, count 2 2006.257.18:42:20.97#ibcon#wrote, iclass 18, count 2 2006.257.18:42:20.97#ibcon#about to read 3, iclass 18, count 2 2006.257.18:42:20.99#ibcon#read 3, iclass 18, count 2 2006.257.18:42:20.99#ibcon#about to read 4, iclass 18, count 2 2006.257.18:42:20.99#ibcon#read 4, iclass 18, count 2 2006.257.18:42:20.99#ibcon#about to read 5, iclass 18, count 2 2006.257.18:42:20.99#ibcon#read 5, iclass 18, count 2 2006.257.18:42:20.99#ibcon#about to read 6, iclass 18, count 2 2006.257.18:42:20.99#ibcon#read 6, iclass 18, count 2 2006.257.18:42:20.99#ibcon#end of sib2, iclass 18, count 2 2006.257.18:42:20.99#ibcon#*mode == 0, iclass 18, count 2 2006.257.18:42:20.99#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.18:42:20.99#ibcon#[25=AT08-04\r\n] 2006.257.18:42:20.99#ibcon#*before write, iclass 18, count 2 2006.257.18:42:20.99#ibcon#enter sib2, iclass 18, count 2 2006.257.18:42:20.99#ibcon#flushed, iclass 18, count 2 2006.257.18:42:20.99#ibcon#about to write, iclass 18, count 2 2006.257.18:42:20.99#ibcon#wrote, iclass 18, count 2 2006.257.18:42:20.99#ibcon#about to read 3, iclass 18, count 2 2006.257.18:42:21.02#ibcon#read 3, iclass 18, count 2 2006.257.18:42:21.02#ibcon#about to read 4, iclass 18, count 2 2006.257.18:42:21.02#ibcon#read 4, iclass 18, count 2 2006.257.18:42:21.02#ibcon#about to read 5, iclass 18, count 2 2006.257.18:42:21.02#ibcon#read 5, iclass 18, count 2 2006.257.18:42:21.02#ibcon#about to read 6, iclass 18, count 2 2006.257.18:42:21.02#ibcon#read 6, iclass 18, count 2 2006.257.18:42:21.02#ibcon#end of sib2, iclass 18, count 2 2006.257.18:42:21.02#ibcon#*after write, iclass 18, count 2 2006.257.18:42:21.02#ibcon#*before return 0, iclass 18, count 2 2006.257.18:42:21.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:21.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:21.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.18:42:21.02#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:21.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:21.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:21.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:21.14#ibcon#enter wrdev, iclass 18, count 0 2006.257.18:42:21.14#ibcon#first serial, iclass 18, count 0 2006.257.18:42:21.14#ibcon#enter sib2, iclass 18, count 0 2006.257.18:42:21.14#ibcon#flushed, iclass 18, count 0 2006.257.18:42:21.14#ibcon#about to write, iclass 18, count 0 2006.257.18:42:21.14#ibcon#wrote, iclass 18, count 0 2006.257.18:42:21.14#ibcon#about to read 3, iclass 18, count 0 2006.257.18:42:21.16#ibcon#read 3, iclass 18, count 0 2006.257.18:42:21.16#ibcon#about to read 4, iclass 18, count 0 2006.257.18:42:21.16#ibcon#read 4, iclass 18, count 0 2006.257.18:42:21.16#ibcon#about to read 5, iclass 18, count 0 2006.257.18:42:21.16#ibcon#read 5, iclass 18, count 0 2006.257.18:42:21.16#ibcon#about to read 6, iclass 18, count 0 2006.257.18:42:21.16#ibcon#read 6, iclass 18, count 0 2006.257.18:42:21.16#ibcon#end of sib2, iclass 18, count 0 2006.257.18:42:21.16#ibcon#*mode == 0, iclass 18, count 0 2006.257.18:42:21.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.18:42:21.16#ibcon#[25=USB\r\n] 2006.257.18:42:21.16#ibcon#*before write, iclass 18, count 0 2006.257.18:42:21.16#ibcon#enter sib2, iclass 18, count 0 2006.257.18:42:21.16#ibcon#flushed, iclass 18, count 0 2006.257.18:42:21.16#ibcon#about to write, iclass 18, count 0 2006.257.18:42:21.16#ibcon#wrote, iclass 18, count 0 2006.257.18:42:21.16#ibcon#about to read 3, iclass 18, count 0 2006.257.18:42:21.19#ibcon#read 3, iclass 18, count 0 2006.257.18:42:21.19#ibcon#about to read 4, iclass 18, count 0 2006.257.18:42:21.19#ibcon#read 4, iclass 18, count 0 2006.257.18:42:21.19#ibcon#about to read 5, iclass 18, count 0 2006.257.18:42:21.19#ibcon#read 5, iclass 18, count 0 2006.257.18:42:21.19#ibcon#about to read 6, iclass 18, count 0 2006.257.18:42:21.19#ibcon#read 6, iclass 18, count 0 2006.257.18:42:21.19#ibcon#end of sib2, iclass 18, count 0 2006.257.18:42:21.19#ibcon#*after write, iclass 18, count 0 2006.257.18:42:21.19#ibcon#*before return 0, iclass 18, count 0 2006.257.18:42:21.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:21.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:21.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.18:42:21.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.18:42:21.19$vck44/vblo=1,629.99 2006.257.18:42:21.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.18:42:21.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.18:42:21.19#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:21.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:21.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:21.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:21.19#ibcon#enter wrdev, iclass 20, count 0 2006.257.18:42:21.19#ibcon#first serial, iclass 20, count 0 2006.257.18:42:21.19#ibcon#enter sib2, iclass 20, count 0 2006.257.18:42:21.19#ibcon#flushed, iclass 20, count 0 2006.257.18:42:21.19#ibcon#about to write, iclass 20, count 0 2006.257.18:42:21.19#ibcon#wrote, iclass 20, count 0 2006.257.18:42:21.19#ibcon#about to read 3, iclass 20, count 0 2006.257.18:42:21.21#ibcon#read 3, iclass 20, count 0 2006.257.18:42:21.21#ibcon#about to read 4, iclass 20, count 0 2006.257.18:42:21.21#ibcon#read 4, iclass 20, count 0 2006.257.18:42:21.21#ibcon#about to read 5, iclass 20, count 0 2006.257.18:42:21.21#ibcon#read 5, iclass 20, count 0 2006.257.18:42:21.21#ibcon#about to read 6, iclass 20, count 0 2006.257.18:42:21.21#ibcon#read 6, iclass 20, count 0 2006.257.18:42:21.21#ibcon#end of sib2, iclass 20, count 0 2006.257.18:42:21.21#ibcon#*mode == 0, iclass 20, count 0 2006.257.18:42:21.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.18:42:21.21#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:42:21.21#ibcon#*before write, iclass 20, count 0 2006.257.18:42:21.21#ibcon#enter sib2, iclass 20, count 0 2006.257.18:42:21.21#ibcon#flushed, iclass 20, count 0 2006.257.18:42:21.21#ibcon#about to write, iclass 20, count 0 2006.257.18:42:21.21#ibcon#wrote, iclass 20, count 0 2006.257.18:42:21.21#ibcon#about to read 3, iclass 20, count 0 2006.257.18:42:21.25#ibcon#read 3, iclass 20, count 0 2006.257.18:42:21.25#ibcon#about to read 4, iclass 20, count 0 2006.257.18:42:21.25#ibcon#read 4, iclass 20, count 0 2006.257.18:42:21.25#ibcon#about to read 5, iclass 20, count 0 2006.257.18:42:21.25#ibcon#read 5, iclass 20, count 0 2006.257.18:42:21.25#ibcon#about to read 6, iclass 20, count 0 2006.257.18:42:21.25#ibcon#read 6, iclass 20, count 0 2006.257.18:42:21.25#ibcon#end of sib2, iclass 20, count 0 2006.257.18:42:21.25#ibcon#*after write, iclass 20, count 0 2006.257.18:42:21.25#ibcon#*before return 0, iclass 20, count 0 2006.257.18:42:21.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:21.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:21.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.18:42:21.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.18:42:21.25$vck44/vb=1,4 2006.257.18:42:21.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.18:42:21.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.18:42:21.25#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:21.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:42:21.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:42:21.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:42:21.25#ibcon#enter wrdev, iclass 22, count 2 2006.257.18:42:21.25#ibcon#first serial, iclass 22, count 2 2006.257.18:42:21.25#ibcon#enter sib2, iclass 22, count 2 2006.257.18:42:21.25#ibcon#flushed, iclass 22, count 2 2006.257.18:42:21.25#ibcon#about to write, iclass 22, count 2 2006.257.18:42:21.25#ibcon#wrote, iclass 22, count 2 2006.257.18:42:21.25#ibcon#about to read 3, iclass 22, count 2 2006.257.18:42:21.27#ibcon#read 3, iclass 22, count 2 2006.257.18:42:21.27#ibcon#about to read 4, iclass 22, count 2 2006.257.18:42:21.27#ibcon#read 4, iclass 22, count 2 2006.257.18:42:21.27#ibcon#about to read 5, iclass 22, count 2 2006.257.18:42:21.27#ibcon#read 5, iclass 22, count 2 2006.257.18:42:21.27#ibcon#about to read 6, iclass 22, count 2 2006.257.18:42:21.27#ibcon#read 6, iclass 22, count 2 2006.257.18:42:21.27#ibcon#end of sib2, iclass 22, count 2 2006.257.18:42:21.27#ibcon#*mode == 0, iclass 22, count 2 2006.257.18:42:21.27#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.18:42:21.27#ibcon#[27=AT01-04\r\n] 2006.257.18:42:21.27#ibcon#*before write, iclass 22, count 2 2006.257.18:42:21.27#ibcon#enter sib2, iclass 22, count 2 2006.257.18:42:21.27#ibcon#flushed, iclass 22, count 2 2006.257.18:42:21.27#ibcon#about to write, iclass 22, count 2 2006.257.18:42:21.27#ibcon#wrote, iclass 22, count 2 2006.257.18:42:21.27#ibcon#about to read 3, iclass 22, count 2 2006.257.18:42:21.30#ibcon#read 3, iclass 22, count 2 2006.257.18:42:21.30#ibcon#about to read 4, iclass 22, count 2 2006.257.18:42:21.30#ibcon#read 4, iclass 22, count 2 2006.257.18:42:21.30#ibcon#about to read 5, iclass 22, count 2 2006.257.18:42:21.30#ibcon#read 5, iclass 22, count 2 2006.257.18:42:21.30#ibcon#about to read 6, iclass 22, count 2 2006.257.18:42:21.30#ibcon#read 6, iclass 22, count 2 2006.257.18:42:21.30#ibcon#end of sib2, iclass 22, count 2 2006.257.18:42:21.30#ibcon#*after write, iclass 22, count 2 2006.257.18:42:21.30#ibcon#*before return 0, iclass 22, count 2 2006.257.18:42:21.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:42:21.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.18:42:21.30#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.18:42:21.30#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:21.30#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:42:21.42#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:42:21.42#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:42:21.42#ibcon#enter wrdev, iclass 22, count 0 2006.257.18:42:21.42#ibcon#first serial, iclass 22, count 0 2006.257.18:42:21.42#ibcon#enter sib2, iclass 22, count 0 2006.257.18:42:21.42#ibcon#flushed, iclass 22, count 0 2006.257.18:42:21.42#ibcon#about to write, iclass 22, count 0 2006.257.18:42:21.42#ibcon#wrote, iclass 22, count 0 2006.257.18:42:21.42#ibcon#about to read 3, iclass 22, count 0 2006.257.18:42:21.44#ibcon#read 3, iclass 22, count 0 2006.257.18:42:21.44#ibcon#about to read 4, iclass 22, count 0 2006.257.18:42:21.44#ibcon#read 4, iclass 22, count 0 2006.257.18:42:21.44#ibcon#about to read 5, iclass 22, count 0 2006.257.18:42:21.44#ibcon#read 5, iclass 22, count 0 2006.257.18:42:21.44#ibcon#about to read 6, iclass 22, count 0 2006.257.18:42:21.44#ibcon#read 6, iclass 22, count 0 2006.257.18:42:21.44#ibcon#end of sib2, iclass 22, count 0 2006.257.18:42:21.44#ibcon#*mode == 0, iclass 22, count 0 2006.257.18:42:21.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.18:42:21.44#ibcon#[27=USB\r\n] 2006.257.18:42:21.44#ibcon#*before write, iclass 22, count 0 2006.257.18:42:21.44#ibcon#enter sib2, iclass 22, count 0 2006.257.18:42:21.44#ibcon#flushed, iclass 22, count 0 2006.257.18:42:21.44#ibcon#about to write, iclass 22, count 0 2006.257.18:42:21.44#ibcon#wrote, iclass 22, count 0 2006.257.18:42:21.44#ibcon#about to read 3, iclass 22, count 0 2006.257.18:42:21.47#ibcon#read 3, iclass 22, count 0 2006.257.18:42:21.47#ibcon#about to read 4, iclass 22, count 0 2006.257.18:42:21.47#ibcon#read 4, iclass 22, count 0 2006.257.18:42:21.47#ibcon#about to read 5, iclass 22, count 0 2006.257.18:42:21.47#ibcon#read 5, iclass 22, count 0 2006.257.18:42:21.47#ibcon#about to read 6, iclass 22, count 0 2006.257.18:42:21.47#ibcon#read 6, iclass 22, count 0 2006.257.18:42:21.47#ibcon#end of sib2, iclass 22, count 0 2006.257.18:42:21.47#ibcon#*after write, iclass 22, count 0 2006.257.18:42:21.47#ibcon#*before return 0, iclass 22, count 0 2006.257.18:42:21.47#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:42:21.47#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.18:42:21.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.18:42:21.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.18:42:21.47$vck44/vblo=2,634.99 2006.257.18:42:21.47#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.18:42:21.47#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.18:42:21.47#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:21.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:21.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:21.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:21.47#ibcon#enter wrdev, iclass 24, count 0 2006.257.18:42:21.47#ibcon#first serial, iclass 24, count 0 2006.257.18:42:21.47#ibcon#enter sib2, iclass 24, count 0 2006.257.18:42:21.47#ibcon#flushed, iclass 24, count 0 2006.257.18:42:21.47#ibcon#about to write, iclass 24, count 0 2006.257.18:42:21.47#ibcon#wrote, iclass 24, count 0 2006.257.18:42:21.47#ibcon#about to read 3, iclass 24, count 0 2006.257.18:42:21.49#ibcon#read 3, iclass 24, count 0 2006.257.18:42:21.49#ibcon#about to read 4, iclass 24, count 0 2006.257.18:42:21.49#ibcon#read 4, iclass 24, count 0 2006.257.18:42:21.49#ibcon#about to read 5, iclass 24, count 0 2006.257.18:42:21.49#ibcon#read 5, iclass 24, count 0 2006.257.18:42:21.49#ibcon#about to read 6, iclass 24, count 0 2006.257.18:42:21.49#ibcon#read 6, iclass 24, count 0 2006.257.18:42:21.49#ibcon#end of sib2, iclass 24, count 0 2006.257.18:42:21.49#ibcon#*mode == 0, iclass 24, count 0 2006.257.18:42:21.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.18:42:21.49#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:42:21.49#ibcon#*before write, iclass 24, count 0 2006.257.18:42:21.49#ibcon#enter sib2, iclass 24, count 0 2006.257.18:42:21.49#ibcon#flushed, iclass 24, count 0 2006.257.18:42:21.49#ibcon#about to write, iclass 24, count 0 2006.257.18:42:21.49#ibcon#wrote, iclass 24, count 0 2006.257.18:42:21.49#ibcon#about to read 3, iclass 24, count 0 2006.257.18:42:21.53#ibcon#read 3, iclass 24, count 0 2006.257.18:42:21.53#ibcon#about to read 4, iclass 24, count 0 2006.257.18:42:21.53#ibcon#read 4, iclass 24, count 0 2006.257.18:42:21.53#ibcon#about to read 5, iclass 24, count 0 2006.257.18:42:21.53#ibcon#read 5, iclass 24, count 0 2006.257.18:42:21.53#ibcon#about to read 6, iclass 24, count 0 2006.257.18:42:21.53#ibcon#read 6, iclass 24, count 0 2006.257.18:42:21.53#ibcon#end of sib2, iclass 24, count 0 2006.257.18:42:21.53#ibcon#*after write, iclass 24, count 0 2006.257.18:42:21.53#ibcon#*before return 0, iclass 24, count 0 2006.257.18:42:21.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:21.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.18:42:21.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.18:42:21.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.18:42:21.53$vck44/vb=2,5 2006.257.18:42:21.53#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.18:42:21.53#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.18:42:21.53#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:21.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:21.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:21.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:21.59#ibcon#enter wrdev, iclass 26, count 2 2006.257.18:42:21.59#ibcon#first serial, iclass 26, count 2 2006.257.18:42:21.59#ibcon#enter sib2, iclass 26, count 2 2006.257.18:42:21.59#ibcon#flushed, iclass 26, count 2 2006.257.18:42:21.59#ibcon#about to write, iclass 26, count 2 2006.257.18:42:21.59#ibcon#wrote, iclass 26, count 2 2006.257.18:42:21.59#ibcon#about to read 3, iclass 26, count 2 2006.257.18:42:21.61#ibcon#read 3, iclass 26, count 2 2006.257.18:42:21.61#ibcon#about to read 4, iclass 26, count 2 2006.257.18:42:21.61#ibcon#read 4, iclass 26, count 2 2006.257.18:42:21.61#ibcon#about to read 5, iclass 26, count 2 2006.257.18:42:21.61#ibcon#read 5, iclass 26, count 2 2006.257.18:42:21.61#ibcon#about to read 6, iclass 26, count 2 2006.257.18:42:21.61#ibcon#read 6, iclass 26, count 2 2006.257.18:42:21.61#ibcon#end of sib2, iclass 26, count 2 2006.257.18:42:21.61#ibcon#*mode == 0, iclass 26, count 2 2006.257.18:42:21.61#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.18:42:21.61#ibcon#[27=AT02-05\r\n] 2006.257.18:42:21.61#ibcon#*before write, iclass 26, count 2 2006.257.18:42:21.61#ibcon#enter sib2, iclass 26, count 2 2006.257.18:42:21.61#ibcon#flushed, iclass 26, count 2 2006.257.18:42:21.61#ibcon#about to write, iclass 26, count 2 2006.257.18:42:21.61#ibcon#wrote, iclass 26, count 2 2006.257.18:42:21.61#ibcon#about to read 3, iclass 26, count 2 2006.257.18:42:21.64#ibcon#read 3, iclass 26, count 2 2006.257.18:42:21.64#ibcon#about to read 4, iclass 26, count 2 2006.257.18:42:21.64#ibcon#read 4, iclass 26, count 2 2006.257.18:42:21.64#ibcon#about to read 5, iclass 26, count 2 2006.257.18:42:21.64#ibcon#read 5, iclass 26, count 2 2006.257.18:42:21.64#ibcon#about to read 6, iclass 26, count 2 2006.257.18:42:21.64#ibcon#read 6, iclass 26, count 2 2006.257.18:42:21.64#ibcon#end of sib2, iclass 26, count 2 2006.257.18:42:21.64#ibcon#*after write, iclass 26, count 2 2006.257.18:42:21.64#ibcon#*before return 0, iclass 26, count 2 2006.257.18:42:21.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:21.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.18:42:21.64#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.18:42:21.64#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:21.64#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:21.76#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:21.76#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:21.76#ibcon#enter wrdev, iclass 26, count 0 2006.257.18:42:21.76#ibcon#first serial, iclass 26, count 0 2006.257.18:42:21.76#ibcon#enter sib2, iclass 26, count 0 2006.257.18:42:21.76#ibcon#flushed, iclass 26, count 0 2006.257.18:42:21.76#ibcon#about to write, iclass 26, count 0 2006.257.18:42:21.76#ibcon#wrote, iclass 26, count 0 2006.257.18:42:21.76#ibcon#about to read 3, iclass 26, count 0 2006.257.18:42:21.78#ibcon#read 3, iclass 26, count 0 2006.257.18:42:21.78#ibcon#about to read 4, iclass 26, count 0 2006.257.18:42:21.78#ibcon#read 4, iclass 26, count 0 2006.257.18:42:21.78#ibcon#about to read 5, iclass 26, count 0 2006.257.18:42:21.78#ibcon#read 5, iclass 26, count 0 2006.257.18:42:21.78#ibcon#about to read 6, iclass 26, count 0 2006.257.18:42:21.78#ibcon#read 6, iclass 26, count 0 2006.257.18:42:21.78#ibcon#end of sib2, iclass 26, count 0 2006.257.18:42:21.78#ibcon#*mode == 0, iclass 26, count 0 2006.257.18:42:21.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.18:42:21.78#ibcon#[27=USB\r\n] 2006.257.18:42:21.78#ibcon#*before write, iclass 26, count 0 2006.257.18:42:21.78#ibcon#enter sib2, iclass 26, count 0 2006.257.18:42:21.78#ibcon#flushed, iclass 26, count 0 2006.257.18:42:21.78#ibcon#about to write, iclass 26, count 0 2006.257.18:42:21.78#ibcon#wrote, iclass 26, count 0 2006.257.18:42:21.78#ibcon#about to read 3, iclass 26, count 0 2006.257.18:42:21.81#ibcon#read 3, iclass 26, count 0 2006.257.18:42:21.81#ibcon#about to read 4, iclass 26, count 0 2006.257.18:42:21.81#ibcon#read 4, iclass 26, count 0 2006.257.18:42:21.81#ibcon#about to read 5, iclass 26, count 0 2006.257.18:42:21.81#ibcon#read 5, iclass 26, count 0 2006.257.18:42:21.81#ibcon#about to read 6, iclass 26, count 0 2006.257.18:42:21.81#ibcon#read 6, iclass 26, count 0 2006.257.18:42:21.81#ibcon#end of sib2, iclass 26, count 0 2006.257.18:42:21.81#ibcon#*after write, iclass 26, count 0 2006.257.18:42:21.81#ibcon#*before return 0, iclass 26, count 0 2006.257.18:42:21.81#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:21.81#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.18:42:21.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.18:42:21.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.18:42:21.81$vck44/vblo=3,649.99 2006.257.18:42:21.81#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.18:42:21.81#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.18:42:21.81#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:21.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:21.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:21.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:21.81#ibcon#enter wrdev, iclass 28, count 0 2006.257.18:42:21.81#ibcon#first serial, iclass 28, count 0 2006.257.18:42:21.81#ibcon#enter sib2, iclass 28, count 0 2006.257.18:42:21.81#ibcon#flushed, iclass 28, count 0 2006.257.18:42:21.81#ibcon#about to write, iclass 28, count 0 2006.257.18:42:21.81#ibcon#wrote, iclass 28, count 0 2006.257.18:42:21.81#ibcon#about to read 3, iclass 28, count 0 2006.257.18:42:21.83#ibcon#read 3, iclass 28, count 0 2006.257.18:42:21.83#ibcon#about to read 4, iclass 28, count 0 2006.257.18:42:21.83#ibcon#read 4, iclass 28, count 0 2006.257.18:42:21.83#ibcon#about to read 5, iclass 28, count 0 2006.257.18:42:21.83#ibcon#read 5, iclass 28, count 0 2006.257.18:42:21.83#ibcon#about to read 6, iclass 28, count 0 2006.257.18:42:21.83#ibcon#read 6, iclass 28, count 0 2006.257.18:42:21.83#ibcon#end of sib2, iclass 28, count 0 2006.257.18:42:21.83#ibcon#*mode == 0, iclass 28, count 0 2006.257.18:42:21.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.18:42:21.83#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:42:21.83#ibcon#*before write, iclass 28, count 0 2006.257.18:42:21.83#ibcon#enter sib2, iclass 28, count 0 2006.257.18:42:21.83#ibcon#flushed, iclass 28, count 0 2006.257.18:42:21.83#ibcon#about to write, iclass 28, count 0 2006.257.18:42:21.83#ibcon#wrote, iclass 28, count 0 2006.257.18:42:21.83#ibcon#about to read 3, iclass 28, count 0 2006.257.18:42:21.87#ibcon#read 3, iclass 28, count 0 2006.257.18:42:21.87#ibcon#about to read 4, iclass 28, count 0 2006.257.18:42:21.87#ibcon#read 4, iclass 28, count 0 2006.257.18:42:21.87#ibcon#about to read 5, iclass 28, count 0 2006.257.18:42:21.87#ibcon#read 5, iclass 28, count 0 2006.257.18:42:21.87#ibcon#about to read 6, iclass 28, count 0 2006.257.18:42:21.87#ibcon#read 6, iclass 28, count 0 2006.257.18:42:21.87#ibcon#end of sib2, iclass 28, count 0 2006.257.18:42:21.87#ibcon#*after write, iclass 28, count 0 2006.257.18:42:21.87#ibcon#*before return 0, iclass 28, count 0 2006.257.18:42:21.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:21.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.18:42:21.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.18:42:21.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.18:42:21.87$vck44/vb=3,4 2006.257.18:42:21.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.18:42:21.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.18:42:21.87#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:21.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:21.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:21.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:21.93#ibcon#enter wrdev, iclass 30, count 2 2006.257.18:42:21.93#ibcon#first serial, iclass 30, count 2 2006.257.18:42:21.93#ibcon#enter sib2, iclass 30, count 2 2006.257.18:42:21.93#ibcon#flushed, iclass 30, count 2 2006.257.18:42:21.93#ibcon#about to write, iclass 30, count 2 2006.257.18:42:21.93#ibcon#wrote, iclass 30, count 2 2006.257.18:42:21.93#ibcon#about to read 3, iclass 30, count 2 2006.257.18:42:21.95#ibcon#read 3, iclass 30, count 2 2006.257.18:42:21.95#ibcon#about to read 4, iclass 30, count 2 2006.257.18:42:21.95#ibcon#read 4, iclass 30, count 2 2006.257.18:42:21.95#ibcon#about to read 5, iclass 30, count 2 2006.257.18:42:21.95#ibcon#read 5, iclass 30, count 2 2006.257.18:42:21.95#ibcon#about to read 6, iclass 30, count 2 2006.257.18:42:21.95#ibcon#read 6, iclass 30, count 2 2006.257.18:42:21.95#ibcon#end of sib2, iclass 30, count 2 2006.257.18:42:21.95#ibcon#*mode == 0, iclass 30, count 2 2006.257.18:42:21.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.18:42:21.95#ibcon#[27=AT03-04\r\n] 2006.257.18:42:21.95#ibcon#*before write, iclass 30, count 2 2006.257.18:42:21.95#ibcon#enter sib2, iclass 30, count 2 2006.257.18:42:21.95#ibcon#flushed, iclass 30, count 2 2006.257.18:42:21.95#ibcon#about to write, iclass 30, count 2 2006.257.18:42:21.95#ibcon#wrote, iclass 30, count 2 2006.257.18:42:21.95#ibcon#about to read 3, iclass 30, count 2 2006.257.18:42:21.98#ibcon#read 3, iclass 30, count 2 2006.257.18:42:21.98#ibcon#about to read 4, iclass 30, count 2 2006.257.18:42:21.98#ibcon#read 4, iclass 30, count 2 2006.257.18:42:21.98#ibcon#about to read 5, iclass 30, count 2 2006.257.18:42:21.98#ibcon#read 5, iclass 30, count 2 2006.257.18:42:21.98#ibcon#about to read 6, iclass 30, count 2 2006.257.18:42:21.98#ibcon#read 6, iclass 30, count 2 2006.257.18:42:21.98#ibcon#end of sib2, iclass 30, count 2 2006.257.18:42:21.98#ibcon#*after write, iclass 30, count 2 2006.257.18:42:21.98#ibcon#*before return 0, iclass 30, count 2 2006.257.18:42:21.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:21.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.18:42:21.98#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.18:42:21.98#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:21.98#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:22.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:22.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:22.10#ibcon#enter wrdev, iclass 30, count 0 2006.257.18:42:22.10#ibcon#first serial, iclass 30, count 0 2006.257.18:42:22.10#ibcon#enter sib2, iclass 30, count 0 2006.257.18:42:22.10#ibcon#flushed, iclass 30, count 0 2006.257.18:42:22.10#ibcon#about to write, iclass 30, count 0 2006.257.18:42:22.10#ibcon#wrote, iclass 30, count 0 2006.257.18:42:22.10#ibcon#about to read 3, iclass 30, count 0 2006.257.18:42:22.12#ibcon#read 3, iclass 30, count 0 2006.257.18:42:22.12#ibcon#about to read 4, iclass 30, count 0 2006.257.18:42:22.12#ibcon#read 4, iclass 30, count 0 2006.257.18:42:22.12#ibcon#about to read 5, iclass 30, count 0 2006.257.18:42:22.12#ibcon#read 5, iclass 30, count 0 2006.257.18:42:22.12#ibcon#about to read 6, iclass 30, count 0 2006.257.18:42:22.12#ibcon#read 6, iclass 30, count 0 2006.257.18:42:22.12#ibcon#end of sib2, iclass 30, count 0 2006.257.18:42:22.12#ibcon#*mode == 0, iclass 30, count 0 2006.257.18:42:22.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.18:42:22.12#ibcon#[27=USB\r\n] 2006.257.18:42:22.12#ibcon#*before write, iclass 30, count 0 2006.257.18:42:22.12#ibcon#enter sib2, iclass 30, count 0 2006.257.18:42:22.12#ibcon#flushed, iclass 30, count 0 2006.257.18:42:22.12#ibcon#about to write, iclass 30, count 0 2006.257.18:42:22.12#ibcon#wrote, iclass 30, count 0 2006.257.18:42:22.12#ibcon#about to read 3, iclass 30, count 0 2006.257.18:42:22.15#ibcon#read 3, iclass 30, count 0 2006.257.18:42:22.15#ibcon#about to read 4, iclass 30, count 0 2006.257.18:42:22.15#ibcon#read 4, iclass 30, count 0 2006.257.18:42:22.15#ibcon#about to read 5, iclass 30, count 0 2006.257.18:42:22.15#ibcon#read 5, iclass 30, count 0 2006.257.18:42:22.15#ibcon#about to read 6, iclass 30, count 0 2006.257.18:42:22.15#ibcon#read 6, iclass 30, count 0 2006.257.18:42:22.15#ibcon#end of sib2, iclass 30, count 0 2006.257.18:42:22.15#ibcon#*after write, iclass 30, count 0 2006.257.18:42:22.15#ibcon#*before return 0, iclass 30, count 0 2006.257.18:42:22.15#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:22.15#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.18:42:22.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.18:42:22.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.18:42:22.15$vck44/vblo=4,679.99 2006.257.18:42:22.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.18:42:22.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.18:42:22.15#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:22.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:22.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:22.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:22.15#ibcon#enter wrdev, iclass 32, count 0 2006.257.18:42:22.15#ibcon#first serial, iclass 32, count 0 2006.257.18:42:22.15#ibcon#enter sib2, iclass 32, count 0 2006.257.18:42:22.15#ibcon#flushed, iclass 32, count 0 2006.257.18:42:22.15#ibcon#about to write, iclass 32, count 0 2006.257.18:42:22.15#ibcon#wrote, iclass 32, count 0 2006.257.18:42:22.15#ibcon#about to read 3, iclass 32, count 0 2006.257.18:42:22.17#ibcon#read 3, iclass 32, count 0 2006.257.18:42:22.17#ibcon#about to read 4, iclass 32, count 0 2006.257.18:42:22.17#ibcon#read 4, iclass 32, count 0 2006.257.18:42:22.17#ibcon#about to read 5, iclass 32, count 0 2006.257.18:42:22.17#ibcon#read 5, iclass 32, count 0 2006.257.18:42:22.17#ibcon#about to read 6, iclass 32, count 0 2006.257.18:42:22.17#ibcon#read 6, iclass 32, count 0 2006.257.18:42:22.17#ibcon#end of sib2, iclass 32, count 0 2006.257.18:42:22.17#ibcon#*mode == 0, iclass 32, count 0 2006.257.18:42:22.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.18:42:22.17#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:42:22.17#ibcon#*before write, iclass 32, count 0 2006.257.18:42:22.17#ibcon#enter sib2, iclass 32, count 0 2006.257.18:42:22.17#ibcon#flushed, iclass 32, count 0 2006.257.18:42:22.17#ibcon#about to write, iclass 32, count 0 2006.257.18:42:22.17#ibcon#wrote, iclass 32, count 0 2006.257.18:42:22.17#ibcon#about to read 3, iclass 32, count 0 2006.257.18:42:22.21#ibcon#read 3, iclass 32, count 0 2006.257.18:42:22.21#ibcon#about to read 4, iclass 32, count 0 2006.257.18:42:22.21#ibcon#read 4, iclass 32, count 0 2006.257.18:42:22.21#ibcon#about to read 5, iclass 32, count 0 2006.257.18:42:22.21#ibcon#read 5, iclass 32, count 0 2006.257.18:42:22.21#ibcon#about to read 6, iclass 32, count 0 2006.257.18:42:22.21#ibcon#read 6, iclass 32, count 0 2006.257.18:42:22.21#ibcon#end of sib2, iclass 32, count 0 2006.257.18:42:22.21#ibcon#*after write, iclass 32, count 0 2006.257.18:42:22.21#ibcon#*before return 0, iclass 32, count 0 2006.257.18:42:22.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:22.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.18:42:22.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.18:42:22.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.18:42:22.21$vck44/vb=4,5 2006.257.18:42:22.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.18:42:22.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.18:42:22.21#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:22.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:22.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:22.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:22.27#ibcon#enter wrdev, iclass 34, count 2 2006.257.18:42:22.27#ibcon#first serial, iclass 34, count 2 2006.257.18:42:22.27#ibcon#enter sib2, iclass 34, count 2 2006.257.18:42:22.27#ibcon#flushed, iclass 34, count 2 2006.257.18:42:22.27#ibcon#about to write, iclass 34, count 2 2006.257.18:42:22.27#ibcon#wrote, iclass 34, count 2 2006.257.18:42:22.27#ibcon#about to read 3, iclass 34, count 2 2006.257.18:42:22.29#ibcon#read 3, iclass 34, count 2 2006.257.18:42:22.29#ibcon#about to read 4, iclass 34, count 2 2006.257.18:42:22.29#ibcon#read 4, iclass 34, count 2 2006.257.18:42:22.29#ibcon#about to read 5, iclass 34, count 2 2006.257.18:42:22.29#ibcon#read 5, iclass 34, count 2 2006.257.18:42:22.29#ibcon#about to read 6, iclass 34, count 2 2006.257.18:42:22.29#ibcon#read 6, iclass 34, count 2 2006.257.18:42:22.29#ibcon#end of sib2, iclass 34, count 2 2006.257.18:42:22.29#ibcon#*mode == 0, iclass 34, count 2 2006.257.18:42:22.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.18:42:22.29#ibcon#[27=AT04-05\r\n] 2006.257.18:42:22.29#ibcon#*before write, iclass 34, count 2 2006.257.18:42:22.29#ibcon#enter sib2, iclass 34, count 2 2006.257.18:42:22.29#ibcon#flushed, iclass 34, count 2 2006.257.18:42:22.29#ibcon#about to write, iclass 34, count 2 2006.257.18:42:22.29#ibcon#wrote, iclass 34, count 2 2006.257.18:42:22.29#ibcon#about to read 3, iclass 34, count 2 2006.257.18:42:22.32#ibcon#read 3, iclass 34, count 2 2006.257.18:42:22.32#ibcon#about to read 4, iclass 34, count 2 2006.257.18:42:22.32#ibcon#read 4, iclass 34, count 2 2006.257.18:42:22.32#ibcon#about to read 5, iclass 34, count 2 2006.257.18:42:22.32#ibcon#read 5, iclass 34, count 2 2006.257.18:42:22.32#ibcon#about to read 6, iclass 34, count 2 2006.257.18:42:22.32#ibcon#read 6, iclass 34, count 2 2006.257.18:42:22.32#ibcon#end of sib2, iclass 34, count 2 2006.257.18:42:22.32#ibcon#*after write, iclass 34, count 2 2006.257.18:42:22.32#ibcon#*before return 0, iclass 34, count 2 2006.257.18:42:22.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:22.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.18:42:22.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.18:42:22.32#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:22.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:22.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:22.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:22.44#ibcon#enter wrdev, iclass 34, count 0 2006.257.18:42:22.44#ibcon#first serial, iclass 34, count 0 2006.257.18:42:22.44#ibcon#enter sib2, iclass 34, count 0 2006.257.18:42:22.44#ibcon#flushed, iclass 34, count 0 2006.257.18:42:22.44#ibcon#about to write, iclass 34, count 0 2006.257.18:42:22.44#ibcon#wrote, iclass 34, count 0 2006.257.18:42:22.44#ibcon#about to read 3, iclass 34, count 0 2006.257.18:42:22.46#ibcon#read 3, iclass 34, count 0 2006.257.18:42:22.46#ibcon#about to read 4, iclass 34, count 0 2006.257.18:42:22.46#ibcon#read 4, iclass 34, count 0 2006.257.18:42:22.46#ibcon#about to read 5, iclass 34, count 0 2006.257.18:42:22.46#ibcon#read 5, iclass 34, count 0 2006.257.18:42:22.46#ibcon#about to read 6, iclass 34, count 0 2006.257.18:42:22.46#ibcon#read 6, iclass 34, count 0 2006.257.18:42:22.46#ibcon#end of sib2, iclass 34, count 0 2006.257.18:42:22.46#ibcon#*mode == 0, iclass 34, count 0 2006.257.18:42:22.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.18:42:22.46#ibcon#[27=USB\r\n] 2006.257.18:42:22.46#ibcon#*before write, iclass 34, count 0 2006.257.18:42:22.46#ibcon#enter sib2, iclass 34, count 0 2006.257.18:42:22.46#ibcon#flushed, iclass 34, count 0 2006.257.18:42:22.46#ibcon#about to write, iclass 34, count 0 2006.257.18:42:22.46#ibcon#wrote, iclass 34, count 0 2006.257.18:42:22.46#ibcon#about to read 3, iclass 34, count 0 2006.257.18:42:22.49#ibcon#read 3, iclass 34, count 0 2006.257.18:42:22.49#ibcon#about to read 4, iclass 34, count 0 2006.257.18:42:22.49#ibcon#read 4, iclass 34, count 0 2006.257.18:42:22.49#ibcon#about to read 5, iclass 34, count 0 2006.257.18:42:22.49#ibcon#read 5, iclass 34, count 0 2006.257.18:42:22.49#ibcon#about to read 6, iclass 34, count 0 2006.257.18:42:22.49#ibcon#read 6, iclass 34, count 0 2006.257.18:42:22.49#ibcon#end of sib2, iclass 34, count 0 2006.257.18:42:22.49#ibcon#*after write, iclass 34, count 0 2006.257.18:42:22.49#ibcon#*before return 0, iclass 34, count 0 2006.257.18:42:22.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:22.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.18:42:22.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.18:42:22.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.18:42:22.49$vck44/vblo=5,709.99 2006.257.18:42:22.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.18:42:22.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.18:42:22.49#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:22.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:22.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:22.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:22.49#ibcon#enter wrdev, iclass 36, count 0 2006.257.18:42:22.49#ibcon#first serial, iclass 36, count 0 2006.257.18:42:22.49#ibcon#enter sib2, iclass 36, count 0 2006.257.18:42:22.49#ibcon#flushed, iclass 36, count 0 2006.257.18:42:22.49#ibcon#about to write, iclass 36, count 0 2006.257.18:42:22.49#ibcon#wrote, iclass 36, count 0 2006.257.18:42:22.49#ibcon#about to read 3, iclass 36, count 0 2006.257.18:42:22.51#ibcon#read 3, iclass 36, count 0 2006.257.18:42:22.51#ibcon#about to read 4, iclass 36, count 0 2006.257.18:42:22.51#ibcon#read 4, iclass 36, count 0 2006.257.18:42:22.51#ibcon#about to read 5, iclass 36, count 0 2006.257.18:42:22.51#ibcon#read 5, iclass 36, count 0 2006.257.18:42:22.51#ibcon#about to read 6, iclass 36, count 0 2006.257.18:42:22.51#ibcon#read 6, iclass 36, count 0 2006.257.18:42:22.51#ibcon#end of sib2, iclass 36, count 0 2006.257.18:42:22.51#ibcon#*mode == 0, iclass 36, count 0 2006.257.18:42:22.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.18:42:22.51#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:42:22.51#ibcon#*before write, iclass 36, count 0 2006.257.18:42:22.51#ibcon#enter sib2, iclass 36, count 0 2006.257.18:42:22.51#ibcon#flushed, iclass 36, count 0 2006.257.18:42:22.51#ibcon#about to write, iclass 36, count 0 2006.257.18:42:22.51#ibcon#wrote, iclass 36, count 0 2006.257.18:42:22.51#ibcon#about to read 3, iclass 36, count 0 2006.257.18:42:22.55#ibcon#read 3, iclass 36, count 0 2006.257.18:42:22.55#ibcon#about to read 4, iclass 36, count 0 2006.257.18:42:22.55#ibcon#read 4, iclass 36, count 0 2006.257.18:42:22.55#ibcon#about to read 5, iclass 36, count 0 2006.257.18:42:22.55#ibcon#read 5, iclass 36, count 0 2006.257.18:42:22.55#ibcon#about to read 6, iclass 36, count 0 2006.257.18:42:22.55#ibcon#read 6, iclass 36, count 0 2006.257.18:42:22.55#ibcon#end of sib2, iclass 36, count 0 2006.257.18:42:22.55#ibcon#*after write, iclass 36, count 0 2006.257.18:42:22.55#ibcon#*before return 0, iclass 36, count 0 2006.257.18:42:22.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:22.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.18:42:22.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.18:42:22.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.18:42:22.55$vck44/vb=5,4 2006.257.18:42:22.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.18:42:22.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.18:42:22.55#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:22.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:22.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:22.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:22.61#ibcon#enter wrdev, iclass 38, count 2 2006.257.18:42:22.61#ibcon#first serial, iclass 38, count 2 2006.257.18:42:22.61#ibcon#enter sib2, iclass 38, count 2 2006.257.18:42:22.61#ibcon#flushed, iclass 38, count 2 2006.257.18:42:22.61#ibcon#about to write, iclass 38, count 2 2006.257.18:42:22.61#ibcon#wrote, iclass 38, count 2 2006.257.18:42:22.61#ibcon#about to read 3, iclass 38, count 2 2006.257.18:42:22.63#ibcon#read 3, iclass 38, count 2 2006.257.18:42:22.63#ibcon#about to read 4, iclass 38, count 2 2006.257.18:42:22.63#ibcon#read 4, iclass 38, count 2 2006.257.18:42:22.63#ibcon#about to read 5, iclass 38, count 2 2006.257.18:42:22.63#ibcon#read 5, iclass 38, count 2 2006.257.18:42:22.63#ibcon#about to read 6, iclass 38, count 2 2006.257.18:42:22.63#ibcon#read 6, iclass 38, count 2 2006.257.18:42:22.63#ibcon#end of sib2, iclass 38, count 2 2006.257.18:42:22.63#ibcon#*mode == 0, iclass 38, count 2 2006.257.18:42:22.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.18:42:22.63#ibcon#[27=AT05-04\r\n] 2006.257.18:42:22.63#ibcon#*before write, iclass 38, count 2 2006.257.18:42:22.63#ibcon#enter sib2, iclass 38, count 2 2006.257.18:42:22.63#ibcon#flushed, iclass 38, count 2 2006.257.18:42:22.63#ibcon#about to write, iclass 38, count 2 2006.257.18:42:22.63#ibcon#wrote, iclass 38, count 2 2006.257.18:42:22.63#ibcon#about to read 3, iclass 38, count 2 2006.257.18:42:22.66#ibcon#read 3, iclass 38, count 2 2006.257.18:42:22.66#ibcon#about to read 4, iclass 38, count 2 2006.257.18:42:22.66#ibcon#read 4, iclass 38, count 2 2006.257.18:42:22.66#ibcon#about to read 5, iclass 38, count 2 2006.257.18:42:22.66#ibcon#read 5, iclass 38, count 2 2006.257.18:42:22.66#ibcon#about to read 6, iclass 38, count 2 2006.257.18:42:22.66#ibcon#read 6, iclass 38, count 2 2006.257.18:42:22.66#ibcon#end of sib2, iclass 38, count 2 2006.257.18:42:22.66#ibcon#*after write, iclass 38, count 2 2006.257.18:42:22.66#ibcon#*before return 0, iclass 38, count 2 2006.257.18:42:22.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:22.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.18:42:22.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.18:42:22.66#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:22.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:22.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:22.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:22.78#ibcon#enter wrdev, iclass 38, count 0 2006.257.18:42:22.78#ibcon#first serial, iclass 38, count 0 2006.257.18:42:22.78#ibcon#enter sib2, iclass 38, count 0 2006.257.18:42:22.78#ibcon#flushed, iclass 38, count 0 2006.257.18:42:22.78#ibcon#about to write, iclass 38, count 0 2006.257.18:42:22.78#ibcon#wrote, iclass 38, count 0 2006.257.18:42:22.78#ibcon#about to read 3, iclass 38, count 0 2006.257.18:42:22.80#ibcon#read 3, iclass 38, count 0 2006.257.18:42:22.80#ibcon#about to read 4, iclass 38, count 0 2006.257.18:42:22.80#ibcon#read 4, iclass 38, count 0 2006.257.18:42:22.80#ibcon#about to read 5, iclass 38, count 0 2006.257.18:42:22.80#ibcon#read 5, iclass 38, count 0 2006.257.18:42:22.80#ibcon#about to read 6, iclass 38, count 0 2006.257.18:42:22.80#ibcon#read 6, iclass 38, count 0 2006.257.18:42:22.80#ibcon#end of sib2, iclass 38, count 0 2006.257.18:42:22.80#ibcon#*mode == 0, iclass 38, count 0 2006.257.18:42:22.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.18:42:22.80#ibcon#[27=USB\r\n] 2006.257.18:42:22.80#ibcon#*before write, iclass 38, count 0 2006.257.18:42:22.80#ibcon#enter sib2, iclass 38, count 0 2006.257.18:42:22.80#ibcon#flushed, iclass 38, count 0 2006.257.18:42:22.80#ibcon#about to write, iclass 38, count 0 2006.257.18:42:22.80#ibcon#wrote, iclass 38, count 0 2006.257.18:42:22.80#ibcon#about to read 3, iclass 38, count 0 2006.257.18:42:22.83#ibcon#read 3, iclass 38, count 0 2006.257.18:42:22.83#ibcon#about to read 4, iclass 38, count 0 2006.257.18:42:22.83#ibcon#read 4, iclass 38, count 0 2006.257.18:42:22.83#ibcon#about to read 5, iclass 38, count 0 2006.257.18:42:22.83#ibcon#read 5, iclass 38, count 0 2006.257.18:42:22.83#ibcon#about to read 6, iclass 38, count 0 2006.257.18:42:22.83#ibcon#read 6, iclass 38, count 0 2006.257.18:42:22.83#ibcon#end of sib2, iclass 38, count 0 2006.257.18:42:22.83#ibcon#*after write, iclass 38, count 0 2006.257.18:42:22.83#ibcon#*before return 0, iclass 38, count 0 2006.257.18:42:22.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:22.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.18:42:22.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.18:42:22.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.18:42:22.83$vck44/vblo=6,719.99 2006.257.18:42:22.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.18:42:22.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.18:42:22.83#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:22.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:22.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:22.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:22.83#ibcon#enter wrdev, iclass 40, count 0 2006.257.18:42:22.83#ibcon#first serial, iclass 40, count 0 2006.257.18:42:22.83#ibcon#enter sib2, iclass 40, count 0 2006.257.18:42:22.83#ibcon#flushed, iclass 40, count 0 2006.257.18:42:22.83#ibcon#about to write, iclass 40, count 0 2006.257.18:42:22.83#ibcon#wrote, iclass 40, count 0 2006.257.18:42:22.83#ibcon#about to read 3, iclass 40, count 0 2006.257.18:42:22.85#ibcon#read 3, iclass 40, count 0 2006.257.18:42:22.85#ibcon#about to read 4, iclass 40, count 0 2006.257.18:42:22.85#ibcon#read 4, iclass 40, count 0 2006.257.18:42:22.85#ibcon#about to read 5, iclass 40, count 0 2006.257.18:42:22.85#ibcon#read 5, iclass 40, count 0 2006.257.18:42:22.85#ibcon#about to read 6, iclass 40, count 0 2006.257.18:42:22.85#ibcon#read 6, iclass 40, count 0 2006.257.18:42:22.85#ibcon#end of sib2, iclass 40, count 0 2006.257.18:42:22.85#ibcon#*mode == 0, iclass 40, count 0 2006.257.18:42:22.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.18:42:22.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:42:22.85#ibcon#*before write, iclass 40, count 0 2006.257.18:42:22.85#ibcon#enter sib2, iclass 40, count 0 2006.257.18:42:22.85#ibcon#flushed, iclass 40, count 0 2006.257.18:42:22.85#ibcon#about to write, iclass 40, count 0 2006.257.18:42:22.85#ibcon#wrote, iclass 40, count 0 2006.257.18:42:22.85#ibcon#about to read 3, iclass 40, count 0 2006.257.18:42:22.89#ibcon#read 3, iclass 40, count 0 2006.257.18:42:22.89#ibcon#about to read 4, iclass 40, count 0 2006.257.18:42:22.89#ibcon#read 4, iclass 40, count 0 2006.257.18:42:22.89#ibcon#about to read 5, iclass 40, count 0 2006.257.18:42:22.89#ibcon#read 5, iclass 40, count 0 2006.257.18:42:22.89#ibcon#about to read 6, iclass 40, count 0 2006.257.18:42:22.89#ibcon#read 6, iclass 40, count 0 2006.257.18:42:22.89#ibcon#end of sib2, iclass 40, count 0 2006.257.18:42:22.89#ibcon#*after write, iclass 40, count 0 2006.257.18:42:22.89#ibcon#*before return 0, iclass 40, count 0 2006.257.18:42:22.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:22.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.18:42:22.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.18:42:22.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.18:42:22.89$vck44/vb=6,4 2006.257.18:42:22.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.18:42:22.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.18:42:22.89#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:22.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:22.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:22.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:22.95#ibcon#enter wrdev, iclass 4, count 2 2006.257.18:42:22.95#ibcon#first serial, iclass 4, count 2 2006.257.18:42:22.95#ibcon#enter sib2, iclass 4, count 2 2006.257.18:42:22.95#ibcon#flushed, iclass 4, count 2 2006.257.18:42:22.95#ibcon#about to write, iclass 4, count 2 2006.257.18:42:22.95#ibcon#wrote, iclass 4, count 2 2006.257.18:42:22.95#ibcon#about to read 3, iclass 4, count 2 2006.257.18:42:22.97#ibcon#read 3, iclass 4, count 2 2006.257.18:42:22.97#ibcon#about to read 4, iclass 4, count 2 2006.257.18:42:22.97#ibcon#read 4, iclass 4, count 2 2006.257.18:42:22.97#ibcon#about to read 5, iclass 4, count 2 2006.257.18:42:22.97#ibcon#read 5, iclass 4, count 2 2006.257.18:42:22.97#ibcon#about to read 6, iclass 4, count 2 2006.257.18:42:22.97#ibcon#read 6, iclass 4, count 2 2006.257.18:42:22.97#ibcon#end of sib2, iclass 4, count 2 2006.257.18:42:22.97#ibcon#*mode == 0, iclass 4, count 2 2006.257.18:42:22.97#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.18:42:22.97#ibcon#[27=AT06-04\r\n] 2006.257.18:42:22.97#ibcon#*before write, iclass 4, count 2 2006.257.18:42:22.97#ibcon#enter sib2, iclass 4, count 2 2006.257.18:42:22.97#ibcon#flushed, iclass 4, count 2 2006.257.18:42:22.97#ibcon#about to write, iclass 4, count 2 2006.257.18:42:22.97#ibcon#wrote, iclass 4, count 2 2006.257.18:42:22.97#ibcon#about to read 3, iclass 4, count 2 2006.257.18:42:23.00#ibcon#read 3, iclass 4, count 2 2006.257.18:42:23.00#ibcon#about to read 4, iclass 4, count 2 2006.257.18:42:23.00#ibcon#read 4, iclass 4, count 2 2006.257.18:42:23.00#ibcon#about to read 5, iclass 4, count 2 2006.257.18:42:23.00#ibcon#read 5, iclass 4, count 2 2006.257.18:42:23.00#ibcon#about to read 6, iclass 4, count 2 2006.257.18:42:23.00#ibcon#read 6, iclass 4, count 2 2006.257.18:42:23.00#ibcon#end of sib2, iclass 4, count 2 2006.257.18:42:23.00#ibcon#*after write, iclass 4, count 2 2006.257.18:42:23.00#ibcon#*before return 0, iclass 4, count 2 2006.257.18:42:23.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:23.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.18:42:23.00#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.18:42:23.00#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:23.00#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:23.12#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:23.12#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:23.12#ibcon#enter wrdev, iclass 4, count 0 2006.257.18:42:23.12#ibcon#first serial, iclass 4, count 0 2006.257.18:42:23.12#ibcon#enter sib2, iclass 4, count 0 2006.257.18:42:23.12#ibcon#flushed, iclass 4, count 0 2006.257.18:42:23.12#ibcon#about to write, iclass 4, count 0 2006.257.18:42:23.12#ibcon#wrote, iclass 4, count 0 2006.257.18:42:23.12#ibcon#about to read 3, iclass 4, count 0 2006.257.18:42:23.14#ibcon#read 3, iclass 4, count 0 2006.257.18:42:23.14#ibcon#about to read 4, iclass 4, count 0 2006.257.18:42:23.14#ibcon#read 4, iclass 4, count 0 2006.257.18:42:23.14#ibcon#about to read 5, iclass 4, count 0 2006.257.18:42:23.14#ibcon#read 5, iclass 4, count 0 2006.257.18:42:23.14#ibcon#about to read 6, iclass 4, count 0 2006.257.18:42:23.14#ibcon#read 6, iclass 4, count 0 2006.257.18:42:23.14#ibcon#end of sib2, iclass 4, count 0 2006.257.18:42:23.14#ibcon#*mode == 0, iclass 4, count 0 2006.257.18:42:23.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.18:42:23.14#ibcon#[27=USB\r\n] 2006.257.18:42:23.14#ibcon#*before write, iclass 4, count 0 2006.257.18:42:23.14#ibcon#enter sib2, iclass 4, count 0 2006.257.18:42:23.14#ibcon#flushed, iclass 4, count 0 2006.257.18:42:23.14#ibcon#about to write, iclass 4, count 0 2006.257.18:42:23.14#ibcon#wrote, iclass 4, count 0 2006.257.18:42:23.14#ibcon#about to read 3, iclass 4, count 0 2006.257.18:42:23.17#ibcon#read 3, iclass 4, count 0 2006.257.18:42:23.17#ibcon#about to read 4, iclass 4, count 0 2006.257.18:42:23.17#ibcon#read 4, iclass 4, count 0 2006.257.18:42:23.17#ibcon#about to read 5, iclass 4, count 0 2006.257.18:42:23.17#ibcon#read 5, iclass 4, count 0 2006.257.18:42:23.17#ibcon#about to read 6, iclass 4, count 0 2006.257.18:42:23.17#ibcon#read 6, iclass 4, count 0 2006.257.18:42:23.17#ibcon#end of sib2, iclass 4, count 0 2006.257.18:42:23.17#ibcon#*after write, iclass 4, count 0 2006.257.18:42:23.17#ibcon#*before return 0, iclass 4, count 0 2006.257.18:42:23.17#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:23.17#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.18:42:23.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.18:42:23.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.18:42:23.17$vck44/vblo=7,734.99 2006.257.18:42:23.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.18:42:23.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.18:42:23.17#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:23.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:23.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:23.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:23.17#ibcon#enter wrdev, iclass 6, count 0 2006.257.18:42:23.17#ibcon#first serial, iclass 6, count 0 2006.257.18:42:23.17#ibcon#enter sib2, iclass 6, count 0 2006.257.18:42:23.17#ibcon#flushed, iclass 6, count 0 2006.257.18:42:23.17#ibcon#about to write, iclass 6, count 0 2006.257.18:42:23.17#ibcon#wrote, iclass 6, count 0 2006.257.18:42:23.17#ibcon#about to read 3, iclass 6, count 0 2006.257.18:42:23.19#ibcon#read 3, iclass 6, count 0 2006.257.18:42:23.19#ibcon#about to read 4, iclass 6, count 0 2006.257.18:42:23.19#ibcon#read 4, iclass 6, count 0 2006.257.18:42:23.19#ibcon#about to read 5, iclass 6, count 0 2006.257.18:42:23.19#ibcon#read 5, iclass 6, count 0 2006.257.18:42:23.19#ibcon#about to read 6, iclass 6, count 0 2006.257.18:42:23.19#ibcon#read 6, iclass 6, count 0 2006.257.18:42:23.19#ibcon#end of sib2, iclass 6, count 0 2006.257.18:42:23.19#ibcon#*mode == 0, iclass 6, count 0 2006.257.18:42:23.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.18:42:23.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:42:23.19#ibcon#*before write, iclass 6, count 0 2006.257.18:42:23.19#ibcon#enter sib2, iclass 6, count 0 2006.257.18:42:23.19#ibcon#flushed, iclass 6, count 0 2006.257.18:42:23.19#ibcon#about to write, iclass 6, count 0 2006.257.18:42:23.19#ibcon#wrote, iclass 6, count 0 2006.257.18:42:23.19#ibcon#about to read 3, iclass 6, count 0 2006.257.18:42:23.23#ibcon#read 3, iclass 6, count 0 2006.257.18:42:23.23#ibcon#about to read 4, iclass 6, count 0 2006.257.18:42:23.23#ibcon#read 4, iclass 6, count 0 2006.257.18:42:23.23#ibcon#about to read 5, iclass 6, count 0 2006.257.18:42:23.23#ibcon#read 5, iclass 6, count 0 2006.257.18:42:23.23#ibcon#about to read 6, iclass 6, count 0 2006.257.18:42:23.23#ibcon#read 6, iclass 6, count 0 2006.257.18:42:23.23#ibcon#end of sib2, iclass 6, count 0 2006.257.18:42:23.23#ibcon#*after write, iclass 6, count 0 2006.257.18:42:23.23#ibcon#*before return 0, iclass 6, count 0 2006.257.18:42:23.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:23.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.18:42:23.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.18:42:23.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.18:42:23.23$vck44/vb=7,4 2006.257.18:42:23.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.18:42:23.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.18:42:23.23#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:23.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:23.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:23.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:23.29#ibcon#enter wrdev, iclass 10, count 2 2006.257.18:42:23.29#ibcon#first serial, iclass 10, count 2 2006.257.18:42:23.29#ibcon#enter sib2, iclass 10, count 2 2006.257.18:42:23.29#ibcon#flushed, iclass 10, count 2 2006.257.18:42:23.29#ibcon#about to write, iclass 10, count 2 2006.257.18:42:23.29#ibcon#wrote, iclass 10, count 2 2006.257.18:42:23.29#ibcon#about to read 3, iclass 10, count 2 2006.257.18:42:23.31#ibcon#read 3, iclass 10, count 2 2006.257.18:42:23.31#ibcon#about to read 4, iclass 10, count 2 2006.257.18:42:23.31#ibcon#read 4, iclass 10, count 2 2006.257.18:42:23.31#ibcon#about to read 5, iclass 10, count 2 2006.257.18:42:23.31#ibcon#read 5, iclass 10, count 2 2006.257.18:42:23.31#ibcon#about to read 6, iclass 10, count 2 2006.257.18:42:23.31#ibcon#read 6, iclass 10, count 2 2006.257.18:42:23.31#ibcon#end of sib2, iclass 10, count 2 2006.257.18:42:23.31#ibcon#*mode == 0, iclass 10, count 2 2006.257.18:42:23.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.18:42:23.31#ibcon#[27=AT07-04\r\n] 2006.257.18:42:23.31#ibcon#*before write, iclass 10, count 2 2006.257.18:42:23.31#ibcon#enter sib2, iclass 10, count 2 2006.257.18:42:23.31#ibcon#flushed, iclass 10, count 2 2006.257.18:42:23.31#ibcon#about to write, iclass 10, count 2 2006.257.18:42:23.31#ibcon#wrote, iclass 10, count 2 2006.257.18:42:23.31#ibcon#about to read 3, iclass 10, count 2 2006.257.18:42:23.34#ibcon#read 3, iclass 10, count 2 2006.257.18:42:23.34#ibcon#about to read 4, iclass 10, count 2 2006.257.18:42:23.34#ibcon#read 4, iclass 10, count 2 2006.257.18:42:23.34#ibcon#about to read 5, iclass 10, count 2 2006.257.18:42:23.34#ibcon#read 5, iclass 10, count 2 2006.257.18:42:23.34#ibcon#about to read 6, iclass 10, count 2 2006.257.18:42:23.34#ibcon#read 6, iclass 10, count 2 2006.257.18:42:23.34#ibcon#end of sib2, iclass 10, count 2 2006.257.18:42:23.34#ibcon#*after write, iclass 10, count 2 2006.257.18:42:23.34#ibcon#*before return 0, iclass 10, count 2 2006.257.18:42:23.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:23.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.18:42:23.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.18:42:23.34#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:23.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:23.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:23.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:23.46#ibcon#enter wrdev, iclass 10, count 0 2006.257.18:42:23.46#ibcon#first serial, iclass 10, count 0 2006.257.18:42:23.46#ibcon#enter sib2, iclass 10, count 0 2006.257.18:42:23.46#ibcon#flushed, iclass 10, count 0 2006.257.18:42:23.46#ibcon#about to write, iclass 10, count 0 2006.257.18:42:23.46#ibcon#wrote, iclass 10, count 0 2006.257.18:42:23.46#ibcon#about to read 3, iclass 10, count 0 2006.257.18:42:23.48#ibcon#read 3, iclass 10, count 0 2006.257.18:42:23.48#ibcon#about to read 4, iclass 10, count 0 2006.257.18:42:23.48#ibcon#read 4, iclass 10, count 0 2006.257.18:42:23.48#ibcon#about to read 5, iclass 10, count 0 2006.257.18:42:23.48#ibcon#read 5, iclass 10, count 0 2006.257.18:42:23.48#ibcon#about to read 6, iclass 10, count 0 2006.257.18:42:23.48#ibcon#read 6, iclass 10, count 0 2006.257.18:42:23.48#ibcon#end of sib2, iclass 10, count 0 2006.257.18:42:23.48#ibcon#*mode == 0, iclass 10, count 0 2006.257.18:42:23.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.18:42:23.48#ibcon#[27=USB\r\n] 2006.257.18:42:23.48#ibcon#*before write, iclass 10, count 0 2006.257.18:42:23.48#ibcon#enter sib2, iclass 10, count 0 2006.257.18:42:23.48#ibcon#flushed, iclass 10, count 0 2006.257.18:42:23.48#ibcon#about to write, iclass 10, count 0 2006.257.18:42:23.48#ibcon#wrote, iclass 10, count 0 2006.257.18:42:23.48#ibcon#about to read 3, iclass 10, count 0 2006.257.18:42:23.48#abcon#<5=/14 1.0 2.4 17.27 971014.2\r\n> 2006.257.18:42:23.50#abcon#{5=INTERFACE CLEAR} 2006.257.18:42:23.51#ibcon#read 3, iclass 10, count 0 2006.257.18:42:23.51#ibcon#about to read 4, iclass 10, count 0 2006.257.18:42:23.51#ibcon#read 4, iclass 10, count 0 2006.257.18:42:23.51#ibcon#about to read 5, iclass 10, count 0 2006.257.18:42:23.51#ibcon#read 5, iclass 10, count 0 2006.257.18:42:23.51#ibcon#about to read 6, iclass 10, count 0 2006.257.18:42:23.51#ibcon#read 6, iclass 10, count 0 2006.257.18:42:23.51#ibcon#end of sib2, iclass 10, count 0 2006.257.18:42:23.51#ibcon#*after write, iclass 10, count 0 2006.257.18:42:23.51#ibcon#*before return 0, iclass 10, count 0 2006.257.18:42:23.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:23.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.18:42:23.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.18:42:23.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.18:42:23.51$vck44/vblo=8,744.99 2006.257.18:42:23.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.18:42:23.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.18:42:23.51#ibcon#ireg 17 cls_cnt 0 2006.257.18:42:23.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:42:23.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:42:23.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:42:23.51#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:42:23.51#ibcon#first serial, iclass 15, count 0 2006.257.18:42:23.51#ibcon#enter sib2, iclass 15, count 0 2006.257.18:42:23.51#ibcon#flushed, iclass 15, count 0 2006.257.18:42:23.51#ibcon#about to write, iclass 15, count 0 2006.257.18:42:23.51#ibcon#wrote, iclass 15, count 0 2006.257.18:42:23.51#ibcon#about to read 3, iclass 15, count 0 2006.257.18:42:23.53#ibcon#read 3, iclass 15, count 0 2006.257.18:42:23.53#ibcon#about to read 4, iclass 15, count 0 2006.257.18:42:23.53#ibcon#read 4, iclass 15, count 0 2006.257.18:42:23.53#ibcon#about to read 5, iclass 15, count 0 2006.257.18:42:23.53#ibcon#read 5, iclass 15, count 0 2006.257.18:42:23.53#ibcon#about to read 6, iclass 15, count 0 2006.257.18:42:23.53#ibcon#read 6, iclass 15, count 0 2006.257.18:42:23.53#ibcon#end of sib2, iclass 15, count 0 2006.257.18:42:23.53#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:42:23.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:42:23.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:42:23.53#ibcon#*before write, iclass 15, count 0 2006.257.18:42:23.53#ibcon#enter sib2, iclass 15, count 0 2006.257.18:42:23.53#ibcon#flushed, iclass 15, count 0 2006.257.18:42:23.53#ibcon#about to write, iclass 15, count 0 2006.257.18:42:23.53#ibcon#wrote, iclass 15, count 0 2006.257.18:42:23.53#ibcon#about to read 3, iclass 15, count 0 2006.257.18:42:23.56#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:42:23.57#ibcon#read 3, iclass 15, count 0 2006.257.18:42:23.57#ibcon#about to read 4, iclass 15, count 0 2006.257.18:42:23.57#ibcon#read 4, iclass 15, count 0 2006.257.18:42:23.57#ibcon#about to read 5, iclass 15, count 0 2006.257.18:42:23.57#ibcon#read 5, iclass 15, count 0 2006.257.18:42:23.57#ibcon#about to read 6, iclass 15, count 0 2006.257.18:42:23.57#ibcon#read 6, iclass 15, count 0 2006.257.18:42:23.57#ibcon#end of sib2, iclass 15, count 0 2006.257.18:42:23.57#ibcon#*after write, iclass 15, count 0 2006.257.18:42:23.57#ibcon#*before return 0, iclass 15, count 0 2006.257.18:42:23.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:42:23.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:42:23.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:42:23.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:42:23.57$vck44/vb=8,4 2006.257.18:42:23.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.18:42:23.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.18:42:23.57#ibcon#ireg 11 cls_cnt 2 2006.257.18:42:23.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:23.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:23.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:23.63#ibcon#enter wrdev, iclass 18, count 2 2006.257.18:42:23.63#ibcon#first serial, iclass 18, count 2 2006.257.18:42:23.63#ibcon#enter sib2, iclass 18, count 2 2006.257.18:42:23.63#ibcon#flushed, iclass 18, count 2 2006.257.18:42:23.63#ibcon#about to write, iclass 18, count 2 2006.257.18:42:23.63#ibcon#wrote, iclass 18, count 2 2006.257.18:42:23.63#ibcon#about to read 3, iclass 18, count 2 2006.257.18:42:23.65#ibcon#read 3, iclass 18, count 2 2006.257.18:42:23.65#ibcon#about to read 4, iclass 18, count 2 2006.257.18:42:23.65#ibcon#read 4, iclass 18, count 2 2006.257.18:42:23.65#ibcon#about to read 5, iclass 18, count 2 2006.257.18:42:23.65#ibcon#read 5, iclass 18, count 2 2006.257.18:42:23.65#ibcon#about to read 6, iclass 18, count 2 2006.257.18:42:23.65#ibcon#read 6, iclass 18, count 2 2006.257.18:42:23.65#ibcon#end of sib2, iclass 18, count 2 2006.257.18:42:23.65#ibcon#*mode == 0, iclass 18, count 2 2006.257.18:42:23.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.18:42:23.65#ibcon#[27=AT08-04\r\n] 2006.257.18:42:23.65#ibcon#*before write, iclass 18, count 2 2006.257.18:42:23.65#ibcon#enter sib2, iclass 18, count 2 2006.257.18:42:23.65#ibcon#flushed, iclass 18, count 2 2006.257.18:42:23.65#ibcon#about to write, iclass 18, count 2 2006.257.18:42:23.65#ibcon#wrote, iclass 18, count 2 2006.257.18:42:23.65#ibcon#about to read 3, iclass 18, count 2 2006.257.18:42:23.68#ibcon#read 3, iclass 18, count 2 2006.257.18:42:23.68#ibcon#about to read 4, iclass 18, count 2 2006.257.18:42:23.68#ibcon#read 4, iclass 18, count 2 2006.257.18:42:23.68#ibcon#about to read 5, iclass 18, count 2 2006.257.18:42:23.68#ibcon#read 5, iclass 18, count 2 2006.257.18:42:23.68#ibcon#about to read 6, iclass 18, count 2 2006.257.18:42:23.68#ibcon#read 6, iclass 18, count 2 2006.257.18:42:23.68#ibcon#end of sib2, iclass 18, count 2 2006.257.18:42:23.68#ibcon#*after write, iclass 18, count 2 2006.257.18:42:23.68#ibcon#*before return 0, iclass 18, count 2 2006.257.18:42:23.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:23.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.18:42:23.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.18:42:23.68#ibcon#ireg 7 cls_cnt 0 2006.257.18:42:23.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:23.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:23.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:23.80#ibcon#enter wrdev, iclass 18, count 0 2006.257.18:42:23.80#ibcon#first serial, iclass 18, count 0 2006.257.18:42:23.80#ibcon#enter sib2, iclass 18, count 0 2006.257.18:42:23.80#ibcon#flushed, iclass 18, count 0 2006.257.18:42:23.80#ibcon#about to write, iclass 18, count 0 2006.257.18:42:23.80#ibcon#wrote, iclass 18, count 0 2006.257.18:42:23.80#ibcon#about to read 3, iclass 18, count 0 2006.257.18:42:23.82#ibcon#read 3, iclass 18, count 0 2006.257.18:42:23.82#ibcon#about to read 4, iclass 18, count 0 2006.257.18:42:23.82#ibcon#read 4, iclass 18, count 0 2006.257.18:42:23.82#ibcon#about to read 5, iclass 18, count 0 2006.257.18:42:23.82#ibcon#read 5, iclass 18, count 0 2006.257.18:42:23.82#ibcon#about to read 6, iclass 18, count 0 2006.257.18:42:23.82#ibcon#read 6, iclass 18, count 0 2006.257.18:42:23.82#ibcon#end of sib2, iclass 18, count 0 2006.257.18:42:23.82#ibcon#*mode == 0, iclass 18, count 0 2006.257.18:42:23.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.18:42:23.82#ibcon#[27=USB\r\n] 2006.257.18:42:23.82#ibcon#*before write, iclass 18, count 0 2006.257.18:42:23.82#ibcon#enter sib2, iclass 18, count 0 2006.257.18:42:23.82#ibcon#flushed, iclass 18, count 0 2006.257.18:42:23.82#ibcon#about to write, iclass 18, count 0 2006.257.18:42:23.82#ibcon#wrote, iclass 18, count 0 2006.257.18:42:23.82#ibcon#about to read 3, iclass 18, count 0 2006.257.18:42:23.85#ibcon#read 3, iclass 18, count 0 2006.257.18:42:23.85#ibcon#about to read 4, iclass 18, count 0 2006.257.18:42:23.85#ibcon#read 4, iclass 18, count 0 2006.257.18:42:23.85#ibcon#about to read 5, iclass 18, count 0 2006.257.18:42:23.85#ibcon#read 5, iclass 18, count 0 2006.257.18:42:23.85#ibcon#about to read 6, iclass 18, count 0 2006.257.18:42:23.85#ibcon#read 6, iclass 18, count 0 2006.257.18:42:23.85#ibcon#end of sib2, iclass 18, count 0 2006.257.18:42:23.85#ibcon#*after write, iclass 18, count 0 2006.257.18:42:23.85#ibcon#*before return 0, iclass 18, count 0 2006.257.18:42:23.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:23.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.18:42:23.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.18:42:23.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.18:42:23.85$vck44/vabw=wide 2006.257.18:42:23.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.18:42:23.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.18:42:23.85#ibcon#ireg 8 cls_cnt 0 2006.257.18:42:23.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:23.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:23.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:23.85#ibcon#enter wrdev, iclass 20, count 0 2006.257.18:42:23.85#ibcon#first serial, iclass 20, count 0 2006.257.18:42:23.85#ibcon#enter sib2, iclass 20, count 0 2006.257.18:42:23.85#ibcon#flushed, iclass 20, count 0 2006.257.18:42:23.85#ibcon#about to write, iclass 20, count 0 2006.257.18:42:23.85#ibcon#wrote, iclass 20, count 0 2006.257.18:42:23.85#ibcon#about to read 3, iclass 20, count 0 2006.257.18:42:23.87#ibcon#read 3, iclass 20, count 0 2006.257.18:42:23.87#ibcon#about to read 4, iclass 20, count 0 2006.257.18:42:23.87#ibcon#read 4, iclass 20, count 0 2006.257.18:42:23.87#ibcon#about to read 5, iclass 20, count 0 2006.257.18:42:23.87#ibcon#read 5, iclass 20, count 0 2006.257.18:42:23.87#ibcon#about to read 6, iclass 20, count 0 2006.257.18:42:23.87#ibcon#read 6, iclass 20, count 0 2006.257.18:42:23.87#ibcon#end of sib2, iclass 20, count 0 2006.257.18:42:23.87#ibcon#*mode == 0, iclass 20, count 0 2006.257.18:42:23.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.18:42:23.87#ibcon#[25=BW32\r\n] 2006.257.18:42:23.87#ibcon#*before write, iclass 20, count 0 2006.257.18:42:23.87#ibcon#enter sib2, iclass 20, count 0 2006.257.18:42:23.87#ibcon#flushed, iclass 20, count 0 2006.257.18:42:23.87#ibcon#about to write, iclass 20, count 0 2006.257.18:42:23.87#ibcon#wrote, iclass 20, count 0 2006.257.18:42:23.87#ibcon#about to read 3, iclass 20, count 0 2006.257.18:42:23.90#ibcon#read 3, iclass 20, count 0 2006.257.18:42:23.90#ibcon#about to read 4, iclass 20, count 0 2006.257.18:42:23.90#ibcon#read 4, iclass 20, count 0 2006.257.18:42:23.90#ibcon#about to read 5, iclass 20, count 0 2006.257.18:42:23.90#ibcon#read 5, iclass 20, count 0 2006.257.18:42:23.90#ibcon#about to read 6, iclass 20, count 0 2006.257.18:42:23.90#ibcon#read 6, iclass 20, count 0 2006.257.18:42:23.90#ibcon#end of sib2, iclass 20, count 0 2006.257.18:42:23.90#ibcon#*after write, iclass 20, count 0 2006.257.18:42:23.90#ibcon#*before return 0, iclass 20, count 0 2006.257.18:42:23.90#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:23.90#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.18:42:23.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.18:42:23.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.18:42:23.90$vck44/vbbw=wide 2006.257.18:42:23.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.18:42:23.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.18:42:23.90#ibcon#ireg 8 cls_cnt 0 2006.257.18:42:23.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:42:23.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:42:23.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:42:23.97#ibcon#enter wrdev, iclass 22, count 0 2006.257.18:42:23.97#ibcon#first serial, iclass 22, count 0 2006.257.18:42:23.97#ibcon#enter sib2, iclass 22, count 0 2006.257.18:42:23.97#ibcon#flushed, iclass 22, count 0 2006.257.18:42:23.97#ibcon#about to write, iclass 22, count 0 2006.257.18:42:23.97#ibcon#wrote, iclass 22, count 0 2006.257.18:42:23.97#ibcon#about to read 3, iclass 22, count 0 2006.257.18:42:23.99#ibcon#read 3, iclass 22, count 0 2006.257.18:42:23.99#ibcon#about to read 4, iclass 22, count 0 2006.257.18:42:23.99#ibcon#read 4, iclass 22, count 0 2006.257.18:42:23.99#ibcon#about to read 5, iclass 22, count 0 2006.257.18:42:23.99#ibcon#read 5, iclass 22, count 0 2006.257.18:42:23.99#ibcon#about to read 6, iclass 22, count 0 2006.257.18:42:23.99#ibcon#read 6, iclass 22, count 0 2006.257.18:42:23.99#ibcon#end of sib2, iclass 22, count 0 2006.257.18:42:23.99#ibcon#*mode == 0, iclass 22, count 0 2006.257.18:42:23.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.18:42:23.99#ibcon#[27=BW32\r\n] 2006.257.18:42:23.99#ibcon#*before write, iclass 22, count 0 2006.257.18:42:23.99#ibcon#enter sib2, iclass 22, count 0 2006.257.18:42:23.99#ibcon#flushed, iclass 22, count 0 2006.257.18:42:23.99#ibcon#about to write, iclass 22, count 0 2006.257.18:42:23.99#ibcon#wrote, iclass 22, count 0 2006.257.18:42:23.99#ibcon#about to read 3, iclass 22, count 0 2006.257.18:42:24.02#ibcon#read 3, iclass 22, count 0 2006.257.18:42:24.02#ibcon#about to read 4, iclass 22, count 0 2006.257.18:42:24.02#ibcon#read 4, iclass 22, count 0 2006.257.18:42:24.02#ibcon#about to read 5, iclass 22, count 0 2006.257.18:42:24.02#ibcon#read 5, iclass 22, count 0 2006.257.18:42:24.02#ibcon#about to read 6, iclass 22, count 0 2006.257.18:42:24.02#ibcon#read 6, iclass 22, count 0 2006.257.18:42:24.02#ibcon#end of sib2, iclass 22, count 0 2006.257.18:42:24.02#ibcon#*after write, iclass 22, count 0 2006.257.18:42:24.02#ibcon#*before return 0, iclass 22, count 0 2006.257.18:42:24.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:42:24.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:42:24.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.18:42:24.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.18:42:24.02$setupk4/ifdk4 2006.257.18:42:24.02$ifdk4/lo= 2006.257.18:42:24.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:42:24.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:42:24.03$ifdk4/patch= 2006.257.18:42:24.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:42:24.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:42:24.03$setupk4/!*+20s 2006.257.18:42:33.65#abcon#<5=/14 1.0 2.4 17.27 971014.2\r\n> 2006.257.18:42:33.67#abcon#{5=INTERFACE CLEAR} 2006.257.18:42:33.73#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:42:38.14#trakl#Source acquired 2006.257.18:42:38.54$setupk4/"tpicd 2006.257.18:42:38.54$setupk4/echo=off 2006.257.18:42:38.54$setupk4/xlog=off 2006.257.18:42:38.54:!2006.257.18:45:16 2006.257.18:42:39.14#flagr#flagr/antenna,acquired 2006.257.18:45:16.00:preob 2006.257.18:45:16.13/onsource/TRACKING 2006.257.18:45:16.13:!2006.257.18:45:26 2006.257.18:45:26.00:"tape 2006.257.18:45:26.00:"st=record 2006.257.18:45:26.00:data_valid=on 2006.257.18:45:26.00:midob 2006.257.18:45:27.13/onsource/TRACKING 2006.257.18:45:27.13/wx/17.29,1014.2,97 2006.257.18:45:27.27/cable/+6.4851E-03 2006.257.18:45:28.36/va/01,08,usb,yes,32,34 2006.257.18:45:28.36/va/02,07,usb,yes,35,35 2006.257.18:45:28.36/va/03,08,usb,yes,31,33 2006.257.18:45:28.36/va/04,07,usb,yes,35,37 2006.257.18:45:28.36/va/05,04,usb,yes,32,32 2006.257.18:45:28.36/va/06,04,usb,yes,35,35 2006.257.18:45:28.36/va/07,04,usb,yes,36,36 2006.257.18:45:28.36/va/08,04,usb,yes,30,37 2006.257.18:45:28.59/valo/01,524.99,yes,locked 2006.257.18:45:28.59/valo/02,534.99,yes,locked 2006.257.18:45:28.59/valo/03,564.99,yes,locked 2006.257.18:45:28.59/valo/04,624.99,yes,locked 2006.257.18:45:28.59/valo/05,734.99,yes,locked 2006.257.18:45:28.59/valo/06,814.99,yes,locked 2006.257.18:45:28.59/valo/07,864.99,yes,locked 2006.257.18:45:28.59/valo/08,884.99,yes,locked 2006.257.18:45:29.68/vb/01,04,usb,yes,30,28 2006.257.18:45:29.68/vb/02,05,usb,yes,29,28 2006.257.18:45:29.68/vb/03,04,usb,yes,29,32 2006.257.18:45:29.68/vb/04,05,usb,yes,30,29 2006.257.18:45:29.68/vb/05,04,usb,yes,26,29 2006.257.18:45:29.68/vb/06,04,usb,yes,31,27 2006.257.18:45:29.68/vb/07,04,usb,yes,30,30 2006.257.18:45:29.68/vb/08,04,usb,yes,28,31 2006.257.18:45:29.92/vblo/01,629.99,yes,locked 2006.257.18:45:29.92/vblo/02,634.99,yes,locked 2006.257.18:45:29.92/vblo/03,649.99,yes,locked 2006.257.18:45:29.92/vblo/04,679.99,yes,locked 2006.257.18:45:29.92/vblo/05,709.99,yes,locked 2006.257.18:45:29.92/vblo/06,719.99,yes,locked 2006.257.18:45:29.92/vblo/07,734.99,yes,locked 2006.257.18:45:29.92/vblo/08,744.99,yes,locked 2006.257.18:45:30.07/vabw/8 2006.257.18:45:30.22/vbbw/8 2006.257.18:45:30.31/xfe/off,on,14.7 2006.257.18:45:30.68/ifatt/23,28,28,28 2006.257.18:45:31.07/fmout-gps/S +4.51E-07 2006.257.18:45:31.11:!2006.257.18:46:16 2006.257.18:46:16.01:data_valid=off 2006.257.18:46:16.01:"et 2006.257.18:46:16.01:!+3s 2006.257.18:46:19.02:"tape 2006.257.18:46:19.02:postob 2006.257.18:46:19.15/cable/+6.4865E-03 2006.257.18:46:19.15/wx/17.29,1014.2,97 2006.257.18:46:19.21/fmout-gps/S +4.51E-07 2006.257.18:46:19.21:scan_name=257-1848,jd0609,220 2006.257.18:46:19.21:source=1044+719,104827.62,714335.9,2000.0,cw 2006.257.18:46:20.14#flagr#flagr/antenna,new-source 2006.257.18:46:20.14:checkk5 2006.257.18:46:20.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:46:20.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:46:21.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:46:21.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:46:21.85/chk_obsdata//k5ts1/T2571845??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.18:46:22.18/chk_obsdata//k5ts2/T2571845??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.18:46:22.52/chk_obsdata//k5ts3/T2571845??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.18:46:22.85/chk_obsdata//k5ts4/T2571845??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.18:46:23.52/k5log//k5ts1_log_newline 2006.257.18:46:24.18/k5log//k5ts2_log_newline 2006.257.18:46:24.85/k5log//k5ts3_log_newline 2006.257.18:46:25.50/k5log//k5ts4_log_newline 2006.257.18:46:25.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:46:25.52:setupk4=1 2006.257.18:46:25.52$setupk4/echo=on 2006.257.18:46:25.52$setupk4/pcalon 2006.257.18:46:25.52$pcalon/"no phase cal control is implemented here 2006.257.18:46:25.52$setupk4/"tpicd=stop 2006.257.18:46:25.52$setupk4/"rec=synch_on 2006.257.18:46:25.52$setupk4/"rec_mode=128 2006.257.18:46:25.52$setupk4/!* 2006.257.18:46:25.52$setupk4/recpk4 2006.257.18:46:25.52$recpk4/recpatch= 2006.257.18:46:25.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:46:25.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:46:25.53$setupk4/vck44 2006.257.18:46:25.53$vck44/valo=1,524.99 2006.257.18:46:25.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.18:46:25.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.18:46:25.53#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:25.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:25.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:25.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:25.53#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:46:25.53#ibcon#first serial, iclass 11, count 0 2006.257.18:46:25.53#ibcon#enter sib2, iclass 11, count 0 2006.257.18:46:25.53#ibcon#flushed, iclass 11, count 0 2006.257.18:46:25.53#ibcon#about to write, iclass 11, count 0 2006.257.18:46:25.53#ibcon#wrote, iclass 11, count 0 2006.257.18:46:25.53#ibcon#about to read 3, iclass 11, count 0 2006.257.18:46:25.54#ibcon#read 3, iclass 11, count 0 2006.257.18:46:25.54#ibcon#about to read 4, iclass 11, count 0 2006.257.18:46:25.54#ibcon#read 4, iclass 11, count 0 2006.257.18:46:25.54#ibcon#about to read 5, iclass 11, count 0 2006.257.18:46:25.54#ibcon#read 5, iclass 11, count 0 2006.257.18:46:25.54#ibcon#about to read 6, iclass 11, count 0 2006.257.18:46:25.54#ibcon#read 6, iclass 11, count 0 2006.257.18:46:25.54#ibcon#end of sib2, iclass 11, count 0 2006.257.18:46:25.54#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:46:25.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:46:25.54#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:46:25.54#ibcon#*before write, iclass 11, count 0 2006.257.18:46:25.54#ibcon#enter sib2, iclass 11, count 0 2006.257.18:46:25.54#ibcon#flushed, iclass 11, count 0 2006.257.18:46:25.54#ibcon#about to write, iclass 11, count 0 2006.257.18:46:25.54#ibcon#wrote, iclass 11, count 0 2006.257.18:46:25.54#ibcon#about to read 3, iclass 11, count 0 2006.257.18:46:25.59#ibcon#read 3, iclass 11, count 0 2006.257.18:46:25.59#ibcon#about to read 4, iclass 11, count 0 2006.257.18:46:25.59#ibcon#read 4, iclass 11, count 0 2006.257.18:46:25.59#ibcon#about to read 5, iclass 11, count 0 2006.257.18:46:25.59#ibcon#read 5, iclass 11, count 0 2006.257.18:46:25.59#ibcon#about to read 6, iclass 11, count 0 2006.257.18:46:25.59#ibcon#read 6, iclass 11, count 0 2006.257.18:46:25.59#ibcon#end of sib2, iclass 11, count 0 2006.257.18:46:25.59#ibcon#*after write, iclass 11, count 0 2006.257.18:46:25.59#ibcon#*before return 0, iclass 11, count 0 2006.257.18:46:25.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:25.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:25.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:46:25.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:46:25.59$vck44/va=1,8 2006.257.18:46:25.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.18:46:25.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.18:46:25.59#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:25.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:25.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:25.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:25.59#ibcon#enter wrdev, iclass 13, count 2 2006.257.18:46:25.59#ibcon#first serial, iclass 13, count 2 2006.257.18:46:25.59#ibcon#enter sib2, iclass 13, count 2 2006.257.18:46:25.59#ibcon#flushed, iclass 13, count 2 2006.257.18:46:25.59#ibcon#about to write, iclass 13, count 2 2006.257.18:46:25.59#ibcon#wrote, iclass 13, count 2 2006.257.18:46:25.59#ibcon#about to read 3, iclass 13, count 2 2006.257.18:46:25.61#ibcon#read 3, iclass 13, count 2 2006.257.18:46:25.61#ibcon#about to read 4, iclass 13, count 2 2006.257.18:46:25.61#ibcon#read 4, iclass 13, count 2 2006.257.18:46:25.61#ibcon#about to read 5, iclass 13, count 2 2006.257.18:46:25.61#ibcon#read 5, iclass 13, count 2 2006.257.18:46:25.61#ibcon#about to read 6, iclass 13, count 2 2006.257.18:46:25.61#ibcon#read 6, iclass 13, count 2 2006.257.18:46:25.61#ibcon#end of sib2, iclass 13, count 2 2006.257.18:46:25.61#ibcon#*mode == 0, iclass 13, count 2 2006.257.18:46:25.61#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.18:46:25.61#ibcon#[25=AT01-08\r\n] 2006.257.18:46:25.61#ibcon#*before write, iclass 13, count 2 2006.257.18:46:25.61#ibcon#enter sib2, iclass 13, count 2 2006.257.18:46:25.61#ibcon#flushed, iclass 13, count 2 2006.257.18:46:25.61#ibcon#about to write, iclass 13, count 2 2006.257.18:46:25.61#ibcon#wrote, iclass 13, count 2 2006.257.18:46:25.61#ibcon#about to read 3, iclass 13, count 2 2006.257.18:46:25.64#ibcon#read 3, iclass 13, count 2 2006.257.18:46:25.64#ibcon#about to read 4, iclass 13, count 2 2006.257.18:46:25.64#ibcon#read 4, iclass 13, count 2 2006.257.18:46:25.64#ibcon#about to read 5, iclass 13, count 2 2006.257.18:46:25.64#ibcon#read 5, iclass 13, count 2 2006.257.18:46:25.64#ibcon#about to read 6, iclass 13, count 2 2006.257.18:46:25.64#ibcon#read 6, iclass 13, count 2 2006.257.18:46:25.64#ibcon#end of sib2, iclass 13, count 2 2006.257.18:46:25.64#ibcon#*after write, iclass 13, count 2 2006.257.18:46:25.64#ibcon#*before return 0, iclass 13, count 2 2006.257.18:46:25.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:25.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:25.64#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.18:46:25.64#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:25.64#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:25.76#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:25.76#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:25.76#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:46:25.76#ibcon#first serial, iclass 13, count 0 2006.257.18:46:25.76#ibcon#enter sib2, iclass 13, count 0 2006.257.18:46:25.76#ibcon#flushed, iclass 13, count 0 2006.257.18:46:25.76#ibcon#about to write, iclass 13, count 0 2006.257.18:46:25.76#ibcon#wrote, iclass 13, count 0 2006.257.18:46:25.76#ibcon#about to read 3, iclass 13, count 0 2006.257.18:46:25.78#ibcon#read 3, iclass 13, count 0 2006.257.18:46:25.78#ibcon#about to read 4, iclass 13, count 0 2006.257.18:46:25.78#ibcon#read 4, iclass 13, count 0 2006.257.18:46:25.78#ibcon#about to read 5, iclass 13, count 0 2006.257.18:46:25.78#ibcon#read 5, iclass 13, count 0 2006.257.18:46:25.78#ibcon#about to read 6, iclass 13, count 0 2006.257.18:46:25.78#ibcon#read 6, iclass 13, count 0 2006.257.18:46:25.78#ibcon#end of sib2, iclass 13, count 0 2006.257.18:46:25.78#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:46:25.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:46:25.78#ibcon#[25=USB\r\n] 2006.257.18:46:25.78#ibcon#*before write, iclass 13, count 0 2006.257.18:46:25.78#ibcon#enter sib2, iclass 13, count 0 2006.257.18:46:25.78#ibcon#flushed, iclass 13, count 0 2006.257.18:46:25.78#ibcon#about to write, iclass 13, count 0 2006.257.18:46:25.78#ibcon#wrote, iclass 13, count 0 2006.257.18:46:25.78#ibcon#about to read 3, iclass 13, count 0 2006.257.18:46:25.81#ibcon#read 3, iclass 13, count 0 2006.257.18:46:25.81#ibcon#about to read 4, iclass 13, count 0 2006.257.18:46:25.81#ibcon#read 4, iclass 13, count 0 2006.257.18:46:25.81#ibcon#about to read 5, iclass 13, count 0 2006.257.18:46:25.81#ibcon#read 5, iclass 13, count 0 2006.257.18:46:25.81#ibcon#about to read 6, iclass 13, count 0 2006.257.18:46:25.81#ibcon#read 6, iclass 13, count 0 2006.257.18:46:25.81#ibcon#end of sib2, iclass 13, count 0 2006.257.18:46:25.81#ibcon#*after write, iclass 13, count 0 2006.257.18:46:25.81#ibcon#*before return 0, iclass 13, count 0 2006.257.18:46:25.81#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:25.81#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:25.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:46:25.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:46:25.81$vck44/valo=2,534.99 2006.257.18:46:25.81#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.18:46:25.81#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.18:46:25.81#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:25.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:25.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:25.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:25.81#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:46:25.81#ibcon#first serial, iclass 15, count 0 2006.257.18:46:25.81#ibcon#enter sib2, iclass 15, count 0 2006.257.18:46:25.81#ibcon#flushed, iclass 15, count 0 2006.257.18:46:25.81#ibcon#about to write, iclass 15, count 0 2006.257.18:46:25.81#ibcon#wrote, iclass 15, count 0 2006.257.18:46:25.81#ibcon#about to read 3, iclass 15, count 0 2006.257.18:46:25.83#ibcon#read 3, iclass 15, count 0 2006.257.18:46:25.83#ibcon#about to read 4, iclass 15, count 0 2006.257.18:46:25.83#ibcon#read 4, iclass 15, count 0 2006.257.18:46:25.83#ibcon#about to read 5, iclass 15, count 0 2006.257.18:46:25.83#ibcon#read 5, iclass 15, count 0 2006.257.18:46:25.83#ibcon#about to read 6, iclass 15, count 0 2006.257.18:46:25.83#ibcon#read 6, iclass 15, count 0 2006.257.18:46:25.83#ibcon#end of sib2, iclass 15, count 0 2006.257.18:46:25.83#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:46:25.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:46:25.83#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:46:25.83#ibcon#*before write, iclass 15, count 0 2006.257.18:46:25.83#ibcon#enter sib2, iclass 15, count 0 2006.257.18:46:25.83#ibcon#flushed, iclass 15, count 0 2006.257.18:46:25.83#ibcon#about to write, iclass 15, count 0 2006.257.18:46:25.83#ibcon#wrote, iclass 15, count 0 2006.257.18:46:25.83#ibcon#about to read 3, iclass 15, count 0 2006.257.18:46:25.87#ibcon#read 3, iclass 15, count 0 2006.257.18:46:25.87#ibcon#about to read 4, iclass 15, count 0 2006.257.18:46:25.87#ibcon#read 4, iclass 15, count 0 2006.257.18:46:25.87#ibcon#about to read 5, iclass 15, count 0 2006.257.18:46:25.87#ibcon#read 5, iclass 15, count 0 2006.257.18:46:25.87#ibcon#about to read 6, iclass 15, count 0 2006.257.18:46:25.87#ibcon#read 6, iclass 15, count 0 2006.257.18:46:25.87#ibcon#end of sib2, iclass 15, count 0 2006.257.18:46:25.87#ibcon#*after write, iclass 15, count 0 2006.257.18:46:25.87#ibcon#*before return 0, iclass 15, count 0 2006.257.18:46:25.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:25.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:25.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:46:25.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:46:25.87$vck44/va=2,7 2006.257.18:46:25.87#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.18:46:25.87#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.18:46:25.87#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:25.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:25.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:25.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:25.93#ibcon#enter wrdev, iclass 17, count 2 2006.257.18:46:25.93#ibcon#first serial, iclass 17, count 2 2006.257.18:46:25.93#ibcon#enter sib2, iclass 17, count 2 2006.257.18:46:25.93#ibcon#flushed, iclass 17, count 2 2006.257.18:46:25.93#ibcon#about to write, iclass 17, count 2 2006.257.18:46:25.93#ibcon#wrote, iclass 17, count 2 2006.257.18:46:25.93#ibcon#about to read 3, iclass 17, count 2 2006.257.18:46:25.95#ibcon#read 3, iclass 17, count 2 2006.257.18:46:25.95#ibcon#about to read 4, iclass 17, count 2 2006.257.18:46:25.95#ibcon#read 4, iclass 17, count 2 2006.257.18:46:25.95#ibcon#about to read 5, iclass 17, count 2 2006.257.18:46:25.95#ibcon#read 5, iclass 17, count 2 2006.257.18:46:25.95#ibcon#about to read 6, iclass 17, count 2 2006.257.18:46:25.95#ibcon#read 6, iclass 17, count 2 2006.257.18:46:25.95#ibcon#end of sib2, iclass 17, count 2 2006.257.18:46:25.95#ibcon#*mode == 0, iclass 17, count 2 2006.257.18:46:25.95#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.18:46:25.95#ibcon#[25=AT02-07\r\n] 2006.257.18:46:25.95#ibcon#*before write, iclass 17, count 2 2006.257.18:46:25.95#ibcon#enter sib2, iclass 17, count 2 2006.257.18:46:25.95#ibcon#flushed, iclass 17, count 2 2006.257.18:46:25.95#ibcon#about to write, iclass 17, count 2 2006.257.18:46:25.95#ibcon#wrote, iclass 17, count 2 2006.257.18:46:25.95#ibcon#about to read 3, iclass 17, count 2 2006.257.18:46:25.98#ibcon#read 3, iclass 17, count 2 2006.257.18:46:25.98#ibcon#about to read 4, iclass 17, count 2 2006.257.18:46:25.98#ibcon#read 4, iclass 17, count 2 2006.257.18:46:25.98#ibcon#about to read 5, iclass 17, count 2 2006.257.18:46:25.98#ibcon#read 5, iclass 17, count 2 2006.257.18:46:25.98#ibcon#about to read 6, iclass 17, count 2 2006.257.18:46:25.98#ibcon#read 6, iclass 17, count 2 2006.257.18:46:25.98#ibcon#end of sib2, iclass 17, count 2 2006.257.18:46:25.98#ibcon#*after write, iclass 17, count 2 2006.257.18:46:25.98#ibcon#*before return 0, iclass 17, count 2 2006.257.18:46:25.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:25.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:25.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.18:46:25.98#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:25.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:26.10#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:26.10#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:26.10#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:46:26.10#ibcon#first serial, iclass 17, count 0 2006.257.18:46:26.10#ibcon#enter sib2, iclass 17, count 0 2006.257.18:46:26.10#ibcon#flushed, iclass 17, count 0 2006.257.18:46:26.10#ibcon#about to write, iclass 17, count 0 2006.257.18:46:26.10#ibcon#wrote, iclass 17, count 0 2006.257.18:46:26.10#ibcon#about to read 3, iclass 17, count 0 2006.257.18:46:26.12#ibcon#read 3, iclass 17, count 0 2006.257.18:46:26.12#ibcon#about to read 4, iclass 17, count 0 2006.257.18:46:26.12#ibcon#read 4, iclass 17, count 0 2006.257.18:46:26.12#ibcon#about to read 5, iclass 17, count 0 2006.257.18:46:26.12#ibcon#read 5, iclass 17, count 0 2006.257.18:46:26.12#ibcon#about to read 6, iclass 17, count 0 2006.257.18:46:26.12#ibcon#read 6, iclass 17, count 0 2006.257.18:46:26.12#ibcon#end of sib2, iclass 17, count 0 2006.257.18:46:26.12#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:46:26.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:46:26.12#ibcon#[25=USB\r\n] 2006.257.18:46:26.12#ibcon#*before write, iclass 17, count 0 2006.257.18:46:26.12#ibcon#enter sib2, iclass 17, count 0 2006.257.18:46:26.12#ibcon#flushed, iclass 17, count 0 2006.257.18:46:26.12#ibcon#about to write, iclass 17, count 0 2006.257.18:46:26.12#ibcon#wrote, iclass 17, count 0 2006.257.18:46:26.12#ibcon#about to read 3, iclass 17, count 0 2006.257.18:46:26.15#ibcon#read 3, iclass 17, count 0 2006.257.18:46:26.15#ibcon#about to read 4, iclass 17, count 0 2006.257.18:46:26.15#ibcon#read 4, iclass 17, count 0 2006.257.18:46:26.15#ibcon#about to read 5, iclass 17, count 0 2006.257.18:46:26.15#ibcon#read 5, iclass 17, count 0 2006.257.18:46:26.15#ibcon#about to read 6, iclass 17, count 0 2006.257.18:46:26.15#ibcon#read 6, iclass 17, count 0 2006.257.18:46:26.15#ibcon#end of sib2, iclass 17, count 0 2006.257.18:46:26.15#ibcon#*after write, iclass 17, count 0 2006.257.18:46:26.15#ibcon#*before return 0, iclass 17, count 0 2006.257.18:46:26.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:26.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:26.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:46:26.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:46:26.15$vck44/valo=3,564.99 2006.257.18:46:26.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.18:46:26.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.18:46:26.15#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:26.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:26.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:26.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:26.15#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:46:26.15#ibcon#first serial, iclass 19, count 0 2006.257.18:46:26.15#ibcon#enter sib2, iclass 19, count 0 2006.257.18:46:26.15#ibcon#flushed, iclass 19, count 0 2006.257.18:46:26.15#ibcon#about to write, iclass 19, count 0 2006.257.18:46:26.15#ibcon#wrote, iclass 19, count 0 2006.257.18:46:26.15#ibcon#about to read 3, iclass 19, count 0 2006.257.18:46:26.17#ibcon#read 3, iclass 19, count 0 2006.257.18:46:26.17#ibcon#about to read 4, iclass 19, count 0 2006.257.18:46:26.17#ibcon#read 4, iclass 19, count 0 2006.257.18:46:26.17#ibcon#about to read 5, iclass 19, count 0 2006.257.18:46:26.17#ibcon#read 5, iclass 19, count 0 2006.257.18:46:26.17#ibcon#about to read 6, iclass 19, count 0 2006.257.18:46:26.17#ibcon#read 6, iclass 19, count 0 2006.257.18:46:26.17#ibcon#end of sib2, iclass 19, count 0 2006.257.18:46:26.17#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:46:26.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:46:26.17#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:46:26.17#ibcon#*before write, iclass 19, count 0 2006.257.18:46:26.17#ibcon#enter sib2, iclass 19, count 0 2006.257.18:46:26.17#ibcon#flushed, iclass 19, count 0 2006.257.18:46:26.17#ibcon#about to write, iclass 19, count 0 2006.257.18:46:26.17#ibcon#wrote, iclass 19, count 0 2006.257.18:46:26.17#ibcon#about to read 3, iclass 19, count 0 2006.257.18:46:26.21#ibcon#read 3, iclass 19, count 0 2006.257.18:46:26.21#ibcon#about to read 4, iclass 19, count 0 2006.257.18:46:26.21#ibcon#read 4, iclass 19, count 0 2006.257.18:46:26.21#ibcon#about to read 5, iclass 19, count 0 2006.257.18:46:26.21#ibcon#read 5, iclass 19, count 0 2006.257.18:46:26.21#ibcon#about to read 6, iclass 19, count 0 2006.257.18:46:26.21#ibcon#read 6, iclass 19, count 0 2006.257.18:46:26.21#ibcon#end of sib2, iclass 19, count 0 2006.257.18:46:26.21#ibcon#*after write, iclass 19, count 0 2006.257.18:46:26.21#ibcon#*before return 0, iclass 19, count 0 2006.257.18:46:26.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:26.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:26.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:46:26.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:46:26.21$vck44/va=3,8 2006.257.18:46:26.21#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.18:46:26.21#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.18:46:26.21#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:26.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:26.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:26.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:26.27#ibcon#enter wrdev, iclass 21, count 2 2006.257.18:46:26.27#ibcon#first serial, iclass 21, count 2 2006.257.18:46:26.27#ibcon#enter sib2, iclass 21, count 2 2006.257.18:46:26.27#ibcon#flushed, iclass 21, count 2 2006.257.18:46:26.27#ibcon#about to write, iclass 21, count 2 2006.257.18:46:26.27#ibcon#wrote, iclass 21, count 2 2006.257.18:46:26.27#ibcon#about to read 3, iclass 21, count 2 2006.257.18:46:26.29#ibcon#read 3, iclass 21, count 2 2006.257.18:46:26.29#ibcon#about to read 4, iclass 21, count 2 2006.257.18:46:26.29#ibcon#read 4, iclass 21, count 2 2006.257.18:46:26.29#ibcon#about to read 5, iclass 21, count 2 2006.257.18:46:26.29#ibcon#read 5, iclass 21, count 2 2006.257.18:46:26.29#ibcon#about to read 6, iclass 21, count 2 2006.257.18:46:26.29#ibcon#read 6, iclass 21, count 2 2006.257.18:46:26.29#ibcon#end of sib2, iclass 21, count 2 2006.257.18:46:26.29#ibcon#*mode == 0, iclass 21, count 2 2006.257.18:46:26.29#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.18:46:26.29#ibcon#[25=AT03-08\r\n] 2006.257.18:46:26.29#ibcon#*before write, iclass 21, count 2 2006.257.18:46:26.29#ibcon#enter sib2, iclass 21, count 2 2006.257.18:46:26.29#ibcon#flushed, iclass 21, count 2 2006.257.18:46:26.29#ibcon#about to write, iclass 21, count 2 2006.257.18:46:26.29#ibcon#wrote, iclass 21, count 2 2006.257.18:46:26.29#ibcon#about to read 3, iclass 21, count 2 2006.257.18:46:26.32#ibcon#read 3, iclass 21, count 2 2006.257.18:46:26.32#ibcon#about to read 4, iclass 21, count 2 2006.257.18:46:26.32#ibcon#read 4, iclass 21, count 2 2006.257.18:46:26.32#ibcon#about to read 5, iclass 21, count 2 2006.257.18:46:26.32#ibcon#read 5, iclass 21, count 2 2006.257.18:46:26.32#ibcon#about to read 6, iclass 21, count 2 2006.257.18:46:26.32#ibcon#read 6, iclass 21, count 2 2006.257.18:46:26.32#ibcon#end of sib2, iclass 21, count 2 2006.257.18:46:26.32#ibcon#*after write, iclass 21, count 2 2006.257.18:46:26.32#ibcon#*before return 0, iclass 21, count 2 2006.257.18:46:26.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:26.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:26.32#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.18:46:26.32#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:26.32#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:26.44#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:26.44#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:26.44#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:46:26.44#ibcon#first serial, iclass 21, count 0 2006.257.18:46:26.44#ibcon#enter sib2, iclass 21, count 0 2006.257.18:46:26.44#ibcon#flushed, iclass 21, count 0 2006.257.18:46:26.44#ibcon#about to write, iclass 21, count 0 2006.257.18:46:26.44#ibcon#wrote, iclass 21, count 0 2006.257.18:46:26.44#ibcon#about to read 3, iclass 21, count 0 2006.257.18:46:26.46#ibcon#read 3, iclass 21, count 0 2006.257.18:46:26.46#ibcon#about to read 4, iclass 21, count 0 2006.257.18:46:26.46#ibcon#read 4, iclass 21, count 0 2006.257.18:46:26.46#ibcon#about to read 5, iclass 21, count 0 2006.257.18:46:26.46#ibcon#read 5, iclass 21, count 0 2006.257.18:46:26.46#ibcon#about to read 6, iclass 21, count 0 2006.257.18:46:26.46#ibcon#read 6, iclass 21, count 0 2006.257.18:46:26.46#ibcon#end of sib2, iclass 21, count 0 2006.257.18:46:26.46#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:46:26.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:46:26.46#ibcon#[25=USB\r\n] 2006.257.18:46:26.46#ibcon#*before write, iclass 21, count 0 2006.257.18:46:26.46#ibcon#enter sib2, iclass 21, count 0 2006.257.18:46:26.46#ibcon#flushed, iclass 21, count 0 2006.257.18:46:26.46#ibcon#about to write, iclass 21, count 0 2006.257.18:46:26.46#ibcon#wrote, iclass 21, count 0 2006.257.18:46:26.46#ibcon#about to read 3, iclass 21, count 0 2006.257.18:46:26.49#ibcon#read 3, iclass 21, count 0 2006.257.18:46:26.49#ibcon#about to read 4, iclass 21, count 0 2006.257.18:46:26.49#ibcon#read 4, iclass 21, count 0 2006.257.18:46:26.49#ibcon#about to read 5, iclass 21, count 0 2006.257.18:46:26.49#ibcon#read 5, iclass 21, count 0 2006.257.18:46:26.49#ibcon#about to read 6, iclass 21, count 0 2006.257.18:46:26.49#ibcon#read 6, iclass 21, count 0 2006.257.18:46:26.49#ibcon#end of sib2, iclass 21, count 0 2006.257.18:46:26.49#ibcon#*after write, iclass 21, count 0 2006.257.18:46:26.49#ibcon#*before return 0, iclass 21, count 0 2006.257.18:46:26.49#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:26.49#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:26.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:46:26.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:46:26.49$vck44/valo=4,624.99 2006.257.18:46:26.49#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.18:46:26.49#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.18:46:26.49#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:26.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:26.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:26.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:26.49#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:46:26.49#ibcon#first serial, iclass 23, count 0 2006.257.18:46:26.49#ibcon#enter sib2, iclass 23, count 0 2006.257.18:46:26.49#ibcon#flushed, iclass 23, count 0 2006.257.18:46:26.49#ibcon#about to write, iclass 23, count 0 2006.257.18:46:26.49#ibcon#wrote, iclass 23, count 0 2006.257.18:46:26.49#ibcon#about to read 3, iclass 23, count 0 2006.257.18:46:26.51#ibcon#read 3, iclass 23, count 0 2006.257.18:46:26.51#ibcon#about to read 4, iclass 23, count 0 2006.257.18:46:26.51#ibcon#read 4, iclass 23, count 0 2006.257.18:46:26.51#ibcon#about to read 5, iclass 23, count 0 2006.257.18:46:26.51#ibcon#read 5, iclass 23, count 0 2006.257.18:46:26.51#ibcon#about to read 6, iclass 23, count 0 2006.257.18:46:26.51#ibcon#read 6, iclass 23, count 0 2006.257.18:46:26.51#ibcon#end of sib2, iclass 23, count 0 2006.257.18:46:26.51#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:46:26.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:46:26.51#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:46:26.51#ibcon#*before write, iclass 23, count 0 2006.257.18:46:26.51#ibcon#enter sib2, iclass 23, count 0 2006.257.18:46:26.51#ibcon#flushed, iclass 23, count 0 2006.257.18:46:26.51#ibcon#about to write, iclass 23, count 0 2006.257.18:46:26.51#ibcon#wrote, iclass 23, count 0 2006.257.18:46:26.51#ibcon#about to read 3, iclass 23, count 0 2006.257.18:46:26.55#ibcon#read 3, iclass 23, count 0 2006.257.18:46:26.55#ibcon#about to read 4, iclass 23, count 0 2006.257.18:46:26.55#ibcon#read 4, iclass 23, count 0 2006.257.18:46:26.55#ibcon#about to read 5, iclass 23, count 0 2006.257.18:46:26.55#ibcon#read 5, iclass 23, count 0 2006.257.18:46:26.55#ibcon#about to read 6, iclass 23, count 0 2006.257.18:46:26.55#ibcon#read 6, iclass 23, count 0 2006.257.18:46:26.55#ibcon#end of sib2, iclass 23, count 0 2006.257.18:46:26.55#ibcon#*after write, iclass 23, count 0 2006.257.18:46:26.55#ibcon#*before return 0, iclass 23, count 0 2006.257.18:46:26.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:26.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:26.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:46:26.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:46:26.55$vck44/va=4,7 2006.257.18:46:26.55#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.18:46:26.55#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.18:46:26.55#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:26.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:26.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:26.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:26.61#ibcon#enter wrdev, iclass 25, count 2 2006.257.18:46:26.61#ibcon#first serial, iclass 25, count 2 2006.257.18:46:26.61#ibcon#enter sib2, iclass 25, count 2 2006.257.18:46:26.61#ibcon#flushed, iclass 25, count 2 2006.257.18:46:26.61#ibcon#about to write, iclass 25, count 2 2006.257.18:46:26.61#ibcon#wrote, iclass 25, count 2 2006.257.18:46:26.61#ibcon#about to read 3, iclass 25, count 2 2006.257.18:46:26.63#ibcon#read 3, iclass 25, count 2 2006.257.18:46:26.63#ibcon#about to read 4, iclass 25, count 2 2006.257.18:46:26.63#ibcon#read 4, iclass 25, count 2 2006.257.18:46:26.63#ibcon#about to read 5, iclass 25, count 2 2006.257.18:46:26.63#ibcon#read 5, iclass 25, count 2 2006.257.18:46:26.63#ibcon#about to read 6, iclass 25, count 2 2006.257.18:46:26.63#ibcon#read 6, iclass 25, count 2 2006.257.18:46:26.63#ibcon#end of sib2, iclass 25, count 2 2006.257.18:46:26.63#ibcon#*mode == 0, iclass 25, count 2 2006.257.18:46:26.63#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.18:46:26.63#ibcon#[25=AT04-07\r\n] 2006.257.18:46:26.63#ibcon#*before write, iclass 25, count 2 2006.257.18:46:26.63#ibcon#enter sib2, iclass 25, count 2 2006.257.18:46:26.63#ibcon#flushed, iclass 25, count 2 2006.257.18:46:26.63#ibcon#about to write, iclass 25, count 2 2006.257.18:46:26.63#ibcon#wrote, iclass 25, count 2 2006.257.18:46:26.63#ibcon#about to read 3, iclass 25, count 2 2006.257.18:46:26.66#ibcon#read 3, iclass 25, count 2 2006.257.18:46:26.66#ibcon#about to read 4, iclass 25, count 2 2006.257.18:46:26.66#ibcon#read 4, iclass 25, count 2 2006.257.18:46:26.66#ibcon#about to read 5, iclass 25, count 2 2006.257.18:46:26.66#ibcon#read 5, iclass 25, count 2 2006.257.18:46:26.66#ibcon#about to read 6, iclass 25, count 2 2006.257.18:46:26.66#ibcon#read 6, iclass 25, count 2 2006.257.18:46:26.66#ibcon#end of sib2, iclass 25, count 2 2006.257.18:46:26.66#ibcon#*after write, iclass 25, count 2 2006.257.18:46:26.66#ibcon#*before return 0, iclass 25, count 2 2006.257.18:46:26.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:26.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:26.66#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.18:46:26.66#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:26.66#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:26.78#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:26.78#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:26.78#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:46:26.78#ibcon#first serial, iclass 25, count 0 2006.257.18:46:26.78#ibcon#enter sib2, iclass 25, count 0 2006.257.18:46:26.78#ibcon#flushed, iclass 25, count 0 2006.257.18:46:26.78#ibcon#about to write, iclass 25, count 0 2006.257.18:46:26.78#ibcon#wrote, iclass 25, count 0 2006.257.18:46:26.78#ibcon#about to read 3, iclass 25, count 0 2006.257.18:46:26.80#ibcon#read 3, iclass 25, count 0 2006.257.18:46:26.80#ibcon#about to read 4, iclass 25, count 0 2006.257.18:46:26.80#ibcon#read 4, iclass 25, count 0 2006.257.18:46:26.80#ibcon#about to read 5, iclass 25, count 0 2006.257.18:46:26.80#ibcon#read 5, iclass 25, count 0 2006.257.18:46:26.80#ibcon#about to read 6, iclass 25, count 0 2006.257.18:46:26.80#ibcon#read 6, iclass 25, count 0 2006.257.18:46:26.80#ibcon#end of sib2, iclass 25, count 0 2006.257.18:46:26.80#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:46:26.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:46:26.80#ibcon#[25=USB\r\n] 2006.257.18:46:26.80#ibcon#*before write, iclass 25, count 0 2006.257.18:46:26.80#ibcon#enter sib2, iclass 25, count 0 2006.257.18:46:26.80#ibcon#flushed, iclass 25, count 0 2006.257.18:46:26.80#ibcon#about to write, iclass 25, count 0 2006.257.18:46:26.80#ibcon#wrote, iclass 25, count 0 2006.257.18:46:26.80#ibcon#about to read 3, iclass 25, count 0 2006.257.18:46:26.83#ibcon#read 3, iclass 25, count 0 2006.257.18:46:26.83#ibcon#about to read 4, iclass 25, count 0 2006.257.18:46:26.83#ibcon#read 4, iclass 25, count 0 2006.257.18:46:26.83#ibcon#about to read 5, iclass 25, count 0 2006.257.18:46:26.83#ibcon#read 5, iclass 25, count 0 2006.257.18:46:26.83#ibcon#about to read 6, iclass 25, count 0 2006.257.18:46:26.83#ibcon#read 6, iclass 25, count 0 2006.257.18:46:26.83#ibcon#end of sib2, iclass 25, count 0 2006.257.18:46:26.83#ibcon#*after write, iclass 25, count 0 2006.257.18:46:26.83#ibcon#*before return 0, iclass 25, count 0 2006.257.18:46:26.83#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:26.83#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:26.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:46:26.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:46:26.83$vck44/valo=5,734.99 2006.257.18:46:26.83#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.18:46:26.83#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.18:46:26.83#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:26.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:26.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:26.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:26.83#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:46:26.83#ibcon#first serial, iclass 27, count 0 2006.257.18:46:26.83#ibcon#enter sib2, iclass 27, count 0 2006.257.18:46:26.83#ibcon#flushed, iclass 27, count 0 2006.257.18:46:26.83#ibcon#about to write, iclass 27, count 0 2006.257.18:46:26.83#ibcon#wrote, iclass 27, count 0 2006.257.18:46:26.83#ibcon#about to read 3, iclass 27, count 0 2006.257.18:46:26.85#ibcon#read 3, iclass 27, count 0 2006.257.18:46:26.85#ibcon#about to read 4, iclass 27, count 0 2006.257.18:46:26.85#ibcon#read 4, iclass 27, count 0 2006.257.18:46:26.85#ibcon#about to read 5, iclass 27, count 0 2006.257.18:46:26.85#ibcon#read 5, iclass 27, count 0 2006.257.18:46:26.85#ibcon#about to read 6, iclass 27, count 0 2006.257.18:46:26.85#ibcon#read 6, iclass 27, count 0 2006.257.18:46:26.85#ibcon#end of sib2, iclass 27, count 0 2006.257.18:46:26.85#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:46:26.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:46:26.85#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:46:26.85#ibcon#*before write, iclass 27, count 0 2006.257.18:46:26.85#ibcon#enter sib2, iclass 27, count 0 2006.257.18:46:26.85#ibcon#flushed, iclass 27, count 0 2006.257.18:46:26.85#ibcon#about to write, iclass 27, count 0 2006.257.18:46:26.85#ibcon#wrote, iclass 27, count 0 2006.257.18:46:26.85#ibcon#about to read 3, iclass 27, count 0 2006.257.18:46:26.89#ibcon#read 3, iclass 27, count 0 2006.257.18:46:26.89#ibcon#about to read 4, iclass 27, count 0 2006.257.18:46:26.89#ibcon#read 4, iclass 27, count 0 2006.257.18:46:26.89#ibcon#about to read 5, iclass 27, count 0 2006.257.18:46:26.89#ibcon#read 5, iclass 27, count 0 2006.257.18:46:26.89#ibcon#about to read 6, iclass 27, count 0 2006.257.18:46:26.89#ibcon#read 6, iclass 27, count 0 2006.257.18:46:26.89#ibcon#end of sib2, iclass 27, count 0 2006.257.18:46:26.89#ibcon#*after write, iclass 27, count 0 2006.257.18:46:26.89#ibcon#*before return 0, iclass 27, count 0 2006.257.18:46:26.89#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:26.89#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:26.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:46:26.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:46:26.89$vck44/va=5,4 2006.257.18:46:26.89#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.18:46:26.89#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.18:46:26.89#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:26.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:26.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:26.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:26.95#ibcon#enter wrdev, iclass 29, count 2 2006.257.18:46:26.95#ibcon#first serial, iclass 29, count 2 2006.257.18:46:26.95#ibcon#enter sib2, iclass 29, count 2 2006.257.18:46:26.95#ibcon#flushed, iclass 29, count 2 2006.257.18:46:26.95#ibcon#about to write, iclass 29, count 2 2006.257.18:46:26.95#ibcon#wrote, iclass 29, count 2 2006.257.18:46:26.95#ibcon#about to read 3, iclass 29, count 2 2006.257.18:46:26.97#ibcon#read 3, iclass 29, count 2 2006.257.18:46:26.97#ibcon#about to read 4, iclass 29, count 2 2006.257.18:46:26.97#ibcon#read 4, iclass 29, count 2 2006.257.18:46:26.97#ibcon#about to read 5, iclass 29, count 2 2006.257.18:46:26.97#ibcon#read 5, iclass 29, count 2 2006.257.18:46:26.97#ibcon#about to read 6, iclass 29, count 2 2006.257.18:46:26.97#ibcon#read 6, iclass 29, count 2 2006.257.18:46:26.97#ibcon#end of sib2, iclass 29, count 2 2006.257.18:46:26.97#ibcon#*mode == 0, iclass 29, count 2 2006.257.18:46:26.97#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.18:46:26.97#ibcon#[25=AT05-04\r\n] 2006.257.18:46:26.97#ibcon#*before write, iclass 29, count 2 2006.257.18:46:26.97#ibcon#enter sib2, iclass 29, count 2 2006.257.18:46:26.97#ibcon#flushed, iclass 29, count 2 2006.257.18:46:26.97#ibcon#about to write, iclass 29, count 2 2006.257.18:46:26.97#ibcon#wrote, iclass 29, count 2 2006.257.18:46:26.97#ibcon#about to read 3, iclass 29, count 2 2006.257.18:46:27.00#ibcon#read 3, iclass 29, count 2 2006.257.18:46:27.00#ibcon#about to read 4, iclass 29, count 2 2006.257.18:46:27.00#ibcon#read 4, iclass 29, count 2 2006.257.18:46:27.00#ibcon#about to read 5, iclass 29, count 2 2006.257.18:46:27.00#ibcon#read 5, iclass 29, count 2 2006.257.18:46:27.00#ibcon#about to read 6, iclass 29, count 2 2006.257.18:46:27.00#ibcon#read 6, iclass 29, count 2 2006.257.18:46:27.00#ibcon#end of sib2, iclass 29, count 2 2006.257.18:46:27.00#ibcon#*after write, iclass 29, count 2 2006.257.18:46:27.00#ibcon#*before return 0, iclass 29, count 2 2006.257.18:46:27.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:27.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:27.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.18:46:27.00#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:27.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:27.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:27.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:27.12#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:46:27.12#ibcon#first serial, iclass 29, count 0 2006.257.18:46:27.12#ibcon#enter sib2, iclass 29, count 0 2006.257.18:46:27.12#ibcon#flushed, iclass 29, count 0 2006.257.18:46:27.12#ibcon#about to write, iclass 29, count 0 2006.257.18:46:27.12#ibcon#wrote, iclass 29, count 0 2006.257.18:46:27.12#ibcon#about to read 3, iclass 29, count 0 2006.257.18:46:27.14#ibcon#read 3, iclass 29, count 0 2006.257.18:46:27.14#ibcon#about to read 4, iclass 29, count 0 2006.257.18:46:27.14#ibcon#read 4, iclass 29, count 0 2006.257.18:46:27.14#ibcon#about to read 5, iclass 29, count 0 2006.257.18:46:27.14#ibcon#read 5, iclass 29, count 0 2006.257.18:46:27.14#ibcon#about to read 6, iclass 29, count 0 2006.257.18:46:27.14#ibcon#read 6, iclass 29, count 0 2006.257.18:46:27.14#ibcon#end of sib2, iclass 29, count 0 2006.257.18:46:27.14#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:46:27.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:46:27.14#ibcon#[25=USB\r\n] 2006.257.18:46:27.14#ibcon#*before write, iclass 29, count 0 2006.257.18:46:27.14#ibcon#enter sib2, iclass 29, count 0 2006.257.18:46:27.14#ibcon#flushed, iclass 29, count 0 2006.257.18:46:27.14#ibcon#about to write, iclass 29, count 0 2006.257.18:46:27.14#ibcon#wrote, iclass 29, count 0 2006.257.18:46:27.14#ibcon#about to read 3, iclass 29, count 0 2006.257.18:46:27.17#ibcon#read 3, iclass 29, count 0 2006.257.18:46:27.17#ibcon#about to read 4, iclass 29, count 0 2006.257.18:46:27.17#ibcon#read 4, iclass 29, count 0 2006.257.18:46:27.17#ibcon#about to read 5, iclass 29, count 0 2006.257.18:46:27.17#ibcon#read 5, iclass 29, count 0 2006.257.18:46:27.17#ibcon#about to read 6, iclass 29, count 0 2006.257.18:46:27.17#ibcon#read 6, iclass 29, count 0 2006.257.18:46:27.17#ibcon#end of sib2, iclass 29, count 0 2006.257.18:46:27.17#ibcon#*after write, iclass 29, count 0 2006.257.18:46:27.17#ibcon#*before return 0, iclass 29, count 0 2006.257.18:46:27.17#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:27.17#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:27.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:46:27.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:46:27.17$vck44/valo=6,814.99 2006.257.18:46:27.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.18:46:27.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.18:46:27.17#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:27.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:27.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:27.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:27.17#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:46:27.17#ibcon#first serial, iclass 31, count 0 2006.257.18:46:27.17#ibcon#enter sib2, iclass 31, count 0 2006.257.18:46:27.17#ibcon#flushed, iclass 31, count 0 2006.257.18:46:27.17#ibcon#about to write, iclass 31, count 0 2006.257.18:46:27.17#ibcon#wrote, iclass 31, count 0 2006.257.18:46:27.17#ibcon#about to read 3, iclass 31, count 0 2006.257.18:46:27.19#ibcon#read 3, iclass 31, count 0 2006.257.18:46:27.19#ibcon#about to read 4, iclass 31, count 0 2006.257.18:46:27.19#ibcon#read 4, iclass 31, count 0 2006.257.18:46:27.19#ibcon#about to read 5, iclass 31, count 0 2006.257.18:46:27.19#ibcon#read 5, iclass 31, count 0 2006.257.18:46:27.19#ibcon#about to read 6, iclass 31, count 0 2006.257.18:46:27.19#ibcon#read 6, iclass 31, count 0 2006.257.18:46:27.19#ibcon#end of sib2, iclass 31, count 0 2006.257.18:46:27.19#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:46:27.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:46:27.19#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:46:27.19#ibcon#*before write, iclass 31, count 0 2006.257.18:46:27.19#ibcon#enter sib2, iclass 31, count 0 2006.257.18:46:27.19#ibcon#flushed, iclass 31, count 0 2006.257.18:46:27.19#ibcon#about to write, iclass 31, count 0 2006.257.18:46:27.19#ibcon#wrote, iclass 31, count 0 2006.257.18:46:27.19#ibcon#about to read 3, iclass 31, count 0 2006.257.18:46:27.23#ibcon#read 3, iclass 31, count 0 2006.257.18:46:27.23#ibcon#about to read 4, iclass 31, count 0 2006.257.18:46:27.23#ibcon#read 4, iclass 31, count 0 2006.257.18:46:27.23#ibcon#about to read 5, iclass 31, count 0 2006.257.18:46:27.23#ibcon#read 5, iclass 31, count 0 2006.257.18:46:27.23#ibcon#about to read 6, iclass 31, count 0 2006.257.18:46:27.23#ibcon#read 6, iclass 31, count 0 2006.257.18:46:27.23#ibcon#end of sib2, iclass 31, count 0 2006.257.18:46:27.23#ibcon#*after write, iclass 31, count 0 2006.257.18:46:27.23#ibcon#*before return 0, iclass 31, count 0 2006.257.18:46:27.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:27.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:27.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:46:27.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:46:27.23$vck44/va=6,4 2006.257.18:46:27.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.18:46:27.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.18:46:27.23#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:27.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:27.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:27.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:27.29#ibcon#enter wrdev, iclass 33, count 2 2006.257.18:46:27.29#ibcon#first serial, iclass 33, count 2 2006.257.18:46:27.29#ibcon#enter sib2, iclass 33, count 2 2006.257.18:46:27.29#ibcon#flushed, iclass 33, count 2 2006.257.18:46:27.29#ibcon#about to write, iclass 33, count 2 2006.257.18:46:27.29#ibcon#wrote, iclass 33, count 2 2006.257.18:46:27.29#ibcon#about to read 3, iclass 33, count 2 2006.257.18:46:27.31#ibcon#read 3, iclass 33, count 2 2006.257.18:46:27.31#ibcon#about to read 4, iclass 33, count 2 2006.257.18:46:27.31#ibcon#read 4, iclass 33, count 2 2006.257.18:46:27.31#ibcon#about to read 5, iclass 33, count 2 2006.257.18:46:27.31#ibcon#read 5, iclass 33, count 2 2006.257.18:46:27.31#ibcon#about to read 6, iclass 33, count 2 2006.257.18:46:27.31#ibcon#read 6, iclass 33, count 2 2006.257.18:46:27.31#ibcon#end of sib2, iclass 33, count 2 2006.257.18:46:27.31#ibcon#*mode == 0, iclass 33, count 2 2006.257.18:46:27.31#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.18:46:27.31#ibcon#[25=AT06-04\r\n] 2006.257.18:46:27.31#ibcon#*before write, iclass 33, count 2 2006.257.18:46:27.31#ibcon#enter sib2, iclass 33, count 2 2006.257.18:46:27.31#ibcon#flushed, iclass 33, count 2 2006.257.18:46:27.31#ibcon#about to write, iclass 33, count 2 2006.257.18:46:27.31#ibcon#wrote, iclass 33, count 2 2006.257.18:46:27.31#ibcon#about to read 3, iclass 33, count 2 2006.257.18:46:27.34#ibcon#read 3, iclass 33, count 2 2006.257.18:46:27.34#ibcon#about to read 4, iclass 33, count 2 2006.257.18:46:27.34#ibcon#read 4, iclass 33, count 2 2006.257.18:46:27.34#ibcon#about to read 5, iclass 33, count 2 2006.257.18:46:27.34#ibcon#read 5, iclass 33, count 2 2006.257.18:46:27.34#ibcon#about to read 6, iclass 33, count 2 2006.257.18:46:27.34#ibcon#read 6, iclass 33, count 2 2006.257.18:46:27.34#ibcon#end of sib2, iclass 33, count 2 2006.257.18:46:27.34#ibcon#*after write, iclass 33, count 2 2006.257.18:46:27.34#ibcon#*before return 0, iclass 33, count 2 2006.257.18:46:27.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:27.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:27.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.18:46:27.34#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:27.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:27.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:27.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:27.46#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:46:27.46#ibcon#first serial, iclass 33, count 0 2006.257.18:46:27.46#ibcon#enter sib2, iclass 33, count 0 2006.257.18:46:27.46#ibcon#flushed, iclass 33, count 0 2006.257.18:46:27.46#ibcon#about to write, iclass 33, count 0 2006.257.18:46:27.46#ibcon#wrote, iclass 33, count 0 2006.257.18:46:27.46#ibcon#about to read 3, iclass 33, count 0 2006.257.18:46:27.48#ibcon#read 3, iclass 33, count 0 2006.257.18:46:27.48#ibcon#about to read 4, iclass 33, count 0 2006.257.18:46:27.48#ibcon#read 4, iclass 33, count 0 2006.257.18:46:27.48#ibcon#about to read 5, iclass 33, count 0 2006.257.18:46:27.48#ibcon#read 5, iclass 33, count 0 2006.257.18:46:27.48#ibcon#about to read 6, iclass 33, count 0 2006.257.18:46:27.48#ibcon#read 6, iclass 33, count 0 2006.257.18:46:27.48#ibcon#end of sib2, iclass 33, count 0 2006.257.18:46:27.48#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:46:27.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:46:27.48#ibcon#[25=USB\r\n] 2006.257.18:46:27.48#ibcon#*before write, iclass 33, count 0 2006.257.18:46:27.48#ibcon#enter sib2, iclass 33, count 0 2006.257.18:46:27.48#ibcon#flushed, iclass 33, count 0 2006.257.18:46:27.48#ibcon#about to write, iclass 33, count 0 2006.257.18:46:27.48#ibcon#wrote, iclass 33, count 0 2006.257.18:46:27.48#ibcon#about to read 3, iclass 33, count 0 2006.257.18:46:27.51#ibcon#read 3, iclass 33, count 0 2006.257.18:46:27.51#ibcon#about to read 4, iclass 33, count 0 2006.257.18:46:27.51#ibcon#read 4, iclass 33, count 0 2006.257.18:46:27.51#ibcon#about to read 5, iclass 33, count 0 2006.257.18:46:27.51#ibcon#read 5, iclass 33, count 0 2006.257.18:46:27.51#ibcon#about to read 6, iclass 33, count 0 2006.257.18:46:27.51#ibcon#read 6, iclass 33, count 0 2006.257.18:46:27.51#ibcon#end of sib2, iclass 33, count 0 2006.257.18:46:27.51#ibcon#*after write, iclass 33, count 0 2006.257.18:46:27.51#ibcon#*before return 0, iclass 33, count 0 2006.257.18:46:27.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:27.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:27.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:46:27.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:46:27.51$vck44/valo=7,864.99 2006.257.18:46:27.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.18:46:27.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.18:46:27.51#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:27.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:27.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:27.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:27.51#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:46:27.51#ibcon#first serial, iclass 35, count 0 2006.257.18:46:27.51#ibcon#enter sib2, iclass 35, count 0 2006.257.18:46:27.51#ibcon#flushed, iclass 35, count 0 2006.257.18:46:27.51#ibcon#about to write, iclass 35, count 0 2006.257.18:46:27.51#ibcon#wrote, iclass 35, count 0 2006.257.18:46:27.51#ibcon#about to read 3, iclass 35, count 0 2006.257.18:46:27.53#ibcon#read 3, iclass 35, count 0 2006.257.18:46:27.53#ibcon#about to read 4, iclass 35, count 0 2006.257.18:46:27.53#ibcon#read 4, iclass 35, count 0 2006.257.18:46:27.53#ibcon#about to read 5, iclass 35, count 0 2006.257.18:46:27.53#ibcon#read 5, iclass 35, count 0 2006.257.18:46:27.53#ibcon#about to read 6, iclass 35, count 0 2006.257.18:46:27.53#ibcon#read 6, iclass 35, count 0 2006.257.18:46:27.53#ibcon#end of sib2, iclass 35, count 0 2006.257.18:46:27.53#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:46:27.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:46:27.53#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:46:27.53#ibcon#*before write, iclass 35, count 0 2006.257.18:46:27.53#ibcon#enter sib2, iclass 35, count 0 2006.257.18:46:27.53#ibcon#flushed, iclass 35, count 0 2006.257.18:46:27.53#ibcon#about to write, iclass 35, count 0 2006.257.18:46:27.53#ibcon#wrote, iclass 35, count 0 2006.257.18:46:27.53#ibcon#about to read 3, iclass 35, count 0 2006.257.18:46:27.56#abcon#<5=/15 1.1 2.4 17.29 971014.2\r\n> 2006.257.18:46:27.57#ibcon#read 3, iclass 35, count 0 2006.257.18:46:27.57#ibcon#about to read 4, iclass 35, count 0 2006.257.18:46:27.57#ibcon#read 4, iclass 35, count 0 2006.257.18:46:27.57#ibcon#about to read 5, iclass 35, count 0 2006.257.18:46:27.57#ibcon#read 5, iclass 35, count 0 2006.257.18:46:27.57#ibcon#about to read 6, iclass 35, count 0 2006.257.18:46:27.57#ibcon#read 6, iclass 35, count 0 2006.257.18:46:27.57#ibcon#end of sib2, iclass 35, count 0 2006.257.18:46:27.57#ibcon#*after write, iclass 35, count 0 2006.257.18:46:27.57#ibcon#*before return 0, iclass 35, count 0 2006.257.18:46:27.57#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:27.57#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:27.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:46:27.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:46:27.57$vck44/va=7,4 2006.257.18:46:27.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.18:46:27.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.18:46:27.57#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:27.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:46:27.58#abcon#{5=INTERFACE CLEAR} 2006.257.18:46:27.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:46:27.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:46:27.63#ibcon#enter wrdev, iclass 40, count 2 2006.257.18:46:27.63#ibcon#first serial, iclass 40, count 2 2006.257.18:46:27.63#ibcon#enter sib2, iclass 40, count 2 2006.257.18:46:27.63#ibcon#flushed, iclass 40, count 2 2006.257.18:46:27.63#ibcon#about to write, iclass 40, count 2 2006.257.18:46:27.63#ibcon#wrote, iclass 40, count 2 2006.257.18:46:27.63#ibcon#about to read 3, iclass 40, count 2 2006.257.18:46:27.64#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:46:27.65#ibcon#read 3, iclass 40, count 2 2006.257.18:46:27.65#ibcon#about to read 4, iclass 40, count 2 2006.257.18:46:27.65#ibcon#read 4, iclass 40, count 2 2006.257.18:46:27.65#ibcon#about to read 5, iclass 40, count 2 2006.257.18:46:27.65#ibcon#read 5, iclass 40, count 2 2006.257.18:46:27.65#ibcon#about to read 6, iclass 40, count 2 2006.257.18:46:27.65#ibcon#read 6, iclass 40, count 2 2006.257.18:46:27.65#ibcon#end of sib2, iclass 40, count 2 2006.257.18:46:27.65#ibcon#*mode == 0, iclass 40, count 2 2006.257.18:46:27.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.18:46:27.65#ibcon#[25=AT07-04\r\n] 2006.257.18:46:27.65#ibcon#*before write, iclass 40, count 2 2006.257.18:46:27.65#ibcon#enter sib2, iclass 40, count 2 2006.257.18:46:27.65#ibcon#flushed, iclass 40, count 2 2006.257.18:46:27.65#ibcon#about to write, iclass 40, count 2 2006.257.18:46:27.65#ibcon#wrote, iclass 40, count 2 2006.257.18:46:27.65#ibcon#about to read 3, iclass 40, count 2 2006.257.18:46:27.68#ibcon#read 3, iclass 40, count 2 2006.257.18:46:27.68#ibcon#about to read 4, iclass 40, count 2 2006.257.18:46:27.68#ibcon#read 4, iclass 40, count 2 2006.257.18:46:27.68#ibcon#about to read 5, iclass 40, count 2 2006.257.18:46:27.68#ibcon#read 5, iclass 40, count 2 2006.257.18:46:27.68#ibcon#about to read 6, iclass 40, count 2 2006.257.18:46:27.68#ibcon#read 6, iclass 40, count 2 2006.257.18:46:27.68#ibcon#end of sib2, iclass 40, count 2 2006.257.18:46:27.68#ibcon#*after write, iclass 40, count 2 2006.257.18:46:27.68#ibcon#*before return 0, iclass 40, count 2 2006.257.18:46:27.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:46:27.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:46:27.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.18:46:27.68#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:27.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:46:27.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:46:27.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:46:27.80#ibcon#enter wrdev, iclass 40, count 0 2006.257.18:46:27.80#ibcon#first serial, iclass 40, count 0 2006.257.18:46:27.80#ibcon#enter sib2, iclass 40, count 0 2006.257.18:46:27.80#ibcon#flushed, iclass 40, count 0 2006.257.18:46:27.80#ibcon#about to write, iclass 40, count 0 2006.257.18:46:27.80#ibcon#wrote, iclass 40, count 0 2006.257.18:46:27.80#ibcon#about to read 3, iclass 40, count 0 2006.257.18:46:27.82#ibcon#read 3, iclass 40, count 0 2006.257.18:46:27.82#ibcon#about to read 4, iclass 40, count 0 2006.257.18:46:27.82#ibcon#read 4, iclass 40, count 0 2006.257.18:46:27.82#ibcon#about to read 5, iclass 40, count 0 2006.257.18:46:27.82#ibcon#read 5, iclass 40, count 0 2006.257.18:46:27.82#ibcon#about to read 6, iclass 40, count 0 2006.257.18:46:27.82#ibcon#read 6, iclass 40, count 0 2006.257.18:46:27.82#ibcon#end of sib2, iclass 40, count 0 2006.257.18:46:27.82#ibcon#*mode == 0, iclass 40, count 0 2006.257.18:46:27.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.18:46:27.82#ibcon#[25=USB\r\n] 2006.257.18:46:27.82#ibcon#*before write, iclass 40, count 0 2006.257.18:46:27.82#ibcon#enter sib2, iclass 40, count 0 2006.257.18:46:27.82#ibcon#flushed, iclass 40, count 0 2006.257.18:46:27.82#ibcon#about to write, iclass 40, count 0 2006.257.18:46:27.82#ibcon#wrote, iclass 40, count 0 2006.257.18:46:27.82#ibcon#about to read 3, iclass 40, count 0 2006.257.18:46:27.85#ibcon#read 3, iclass 40, count 0 2006.257.18:46:27.85#ibcon#about to read 4, iclass 40, count 0 2006.257.18:46:27.85#ibcon#read 4, iclass 40, count 0 2006.257.18:46:27.85#ibcon#about to read 5, iclass 40, count 0 2006.257.18:46:27.85#ibcon#read 5, iclass 40, count 0 2006.257.18:46:27.85#ibcon#about to read 6, iclass 40, count 0 2006.257.18:46:27.85#ibcon#read 6, iclass 40, count 0 2006.257.18:46:27.85#ibcon#end of sib2, iclass 40, count 0 2006.257.18:46:27.85#ibcon#*after write, iclass 40, count 0 2006.257.18:46:27.85#ibcon#*before return 0, iclass 40, count 0 2006.257.18:46:27.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:46:27.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:46:27.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.18:46:27.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.18:46:27.85$vck44/valo=8,884.99 2006.257.18:46:27.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.18:46:27.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.18:46:27.85#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:27.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:27.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:27.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:27.85#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:46:27.85#ibcon#first serial, iclass 5, count 0 2006.257.18:46:27.85#ibcon#enter sib2, iclass 5, count 0 2006.257.18:46:27.85#ibcon#flushed, iclass 5, count 0 2006.257.18:46:27.85#ibcon#about to write, iclass 5, count 0 2006.257.18:46:27.85#ibcon#wrote, iclass 5, count 0 2006.257.18:46:27.85#ibcon#about to read 3, iclass 5, count 0 2006.257.18:46:27.87#ibcon#read 3, iclass 5, count 0 2006.257.18:46:27.87#ibcon#about to read 4, iclass 5, count 0 2006.257.18:46:27.87#ibcon#read 4, iclass 5, count 0 2006.257.18:46:27.87#ibcon#about to read 5, iclass 5, count 0 2006.257.18:46:27.87#ibcon#read 5, iclass 5, count 0 2006.257.18:46:27.87#ibcon#about to read 6, iclass 5, count 0 2006.257.18:46:27.87#ibcon#read 6, iclass 5, count 0 2006.257.18:46:27.87#ibcon#end of sib2, iclass 5, count 0 2006.257.18:46:27.87#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:46:27.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:46:27.87#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:46:27.87#ibcon#*before write, iclass 5, count 0 2006.257.18:46:27.87#ibcon#enter sib2, iclass 5, count 0 2006.257.18:46:27.87#ibcon#flushed, iclass 5, count 0 2006.257.18:46:27.87#ibcon#about to write, iclass 5, count 0 2006.257.18:46:27.87#ibcon#wrote, iclass 5, count 0 2006.257.18:46:27.87#ibcon#about to read 3, iclass 5, count 0 2006.257.18:46:27.91#ibcon#read 3, iclass 5, count 0 2006.257.18:46:27.91#ibcon#about to read 4, iclass 5, count 0 2006.257.18:46:27.91#ibcon#read 4, iclass 5, count 0 2006.257.18:46:27.91#ibcon#about to read 5, iclass 5, count 0 2006.257.18:46:27.91#ibcon#read 5, iclass 5, count 0 2006.257.18:46:27.91#ibcon#about to read 6, iclass 5, count 0 2006.257.18:46:27.91#ibcon#read 6, iclass 5, count 0 2006.257.18:46:27.91#ibcon#end of sib2, iclass 5, count 0 2006.257.18:46:27.91#ibcon#*after write, iclass 5, count 0 2006.257.18:46:27.91#ibcon#*before return 0, iclass 5, count 0 2006.257.18:46:27.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:27.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:27.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:46:27.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:46:27.91$vck44/va=8,4 2006.257.18:46:27.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.18:46:27.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.18:46:27.91#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:27.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:46:27.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:46:27.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:46:27.97#ibcon#enter wrdev, iclass 7, count 2 2006.257.18:46:27.97#ibcon#first serial, iclass 7, count 2 2006.257.18:46:27.97#ibcon#enter sib2, iclass 7, count 2 2006.257.18:46:27.97#ibcon#flushed, iclass 7, count 2 2006.257.18:46:27.97#ibcon#about to write, iclass 7, count 2 2006.257.18:46:27.97#ibcon#wrote, iclass 7, count 2 2006.257.18:46:27.97#ibcon#about to read 3, iclass 7, count 2 2006.257.18:46:27.99#ibcon#read 3, iclass 7, count 2 2006.257.18:46:27.99#ibcon#about to read 4, iclass 7, count 2 2006.257.18:46:27.99#ibcon#read 4, iclass 7, count 2 2006.257.18:46:27.99#ibcon#about to read 5, iclass 7, count 2 2006.257.18:46:27.99#ibcon#read 5, iclass 7, count 2 2006.257.18:46:27.99#ibcon#about to read 6, iclass 7, count 2 2006.257.18:46:27.99#ibcon#read 6, iclass 7, count 2 2006.257.18:46:27.99#ibcon#end of sib2, iclass 7, count 2 2006.257.18:46:27.99#ibcon#*mode == 0, iclass 7, count 2 2006.257.18:46:27.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.18:46:27.99#ibcon#[25=AT08-04\r\n] 2006.257.18:46:27.99#ibcon#*before write, iclass 7, count 2 2006.257.18:46:27.99#ibcon#enter sib2, iclass 7, count 2 2006.257.18:46:27.99#ibcon#flushed, iclass 7, count 2 2006.257.18:46:27.99#ibcon#about to write, iclass 7, count 2 2006.257.18:46:27.99#ibcon#wrote, iclass 7, count 2 2006.257.18:46:27.99#ibcon#about to read 3, iclass 7, count 2 2006.257.18:46:28.02#ibcon#read 3, iclass 7, count 2 2006.257.18:46:28.02#ibcon#about to read 4, iclass 7, count 2 2006.257.18:46:28.02#ibcon#read 4, iclass 7, count 2 2006.257.18:46:28.02#ibcon#about to read 5, iclass 7, count 2 2006.257.18:46:28.02#ibcon#read 5, iclass 7, count 2 2006.257.18:46:28.02#ibcon#about to read 6, iclass 7, count 2 2006.257.18:46:28.02#ibcon#read 6, iclass 7, count 2 2006.257.18:46:28.02#ibcon#end of sib2, iclass 7, count 2 2006.257.18:46:28.02#ibcon#*after write, iclass 7, count 2 2006.257.18:46:28.02#ibcon#*before return 0, iclass 7, count 2 2006.257.18:46:28.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:46:28.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.18:46:28.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.18:46:28.02#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:28.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:46:28.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:46:28.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:46:28.14#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:46:28.14#ibcon#first serial, iclass 7, count 0 2006.257.18:46:28.14#ibcon#enter sib2, iclass 7, count 0 2006.257.18:46:28.14#ibcon#flushed, iclass 7, count 0 2006.257.18:46:28.14#ibcon#about to write, iclass 7, count 0 2006.257.18:46:28.14#ibcon#wrote, iclass 7, count 0 2006.257.18:46:28.14#ibcon#about to read 3, iclass 7, count 0 2006.257.18:46:28.16#ibcon#read 3, iclass 7, count 0 2006.257.18:46:28.16#ibcon#about to read 4, iclass 7, count 0 2006.257.18:46:28.16#ibcon#read 4, iclass 7, count 0 2006.257.18:46:28.16#ibcon#about to read 5, iclass 7, count 0 2006.257.18:46:28.16#ibcon#read 5, iclass 7, count 0 2006.257.18:46:28.16#ibcon#about to read 6, iclass 7, count 0 2006.257.18:46:28.16#ibcon#read 6, iclass 7, count 0 2006.257.18:46:28.16#ibcon#end of sib2, iclass 7, count 0 2006.257.18:46:28.16#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:46:28.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:46:28.16#ibcon#[25=USB\r\n] 2006.257.18:46:28.16#ibcon#*before write, iclass 7, count 0 2006.257.18:46:28.16#ibcon#enter sib2, iclass 7, count 0 2006.257.18:46:28.16#ibcon#flushed, iclass 7, count 0 2006.257.18:46:28.16#ibcon#about to write, iclass 7, count 0 2006.257.18:46:28.16#ibcon#wrote, iclass 7, count 0 2006.257.18:46:28.16#ibcon#about to read 3, iclass 7, count 0 2006.257.18:46:28.19#ibcon#read 3, iclass 7, count 0 2006.257.18:46:28.19#ibcon#about to read 4, iclass 7, count 0 2006.257.18:46:28.19#ibcon#read 4, iclass 7, count 0 2006.257.18:46:28.19#ibcon#about to read 5, iclass 7, count 0 2006.257.18:46:28.19#ibcon#read 5, iclass 7, count 0 2006.257.18:46:28.19#ibcon#about to read 6, iclass 7, count 0 2006.257.18:46:28.19#ibcon#read 6, iclass 7, count 0 2006.257.18:46:28.19#ibcon#end of sib2, iclass 7, count 0 2006.257.18:46:28.19#ibcon#*after write, iclass 7, count 0 2006.257.18:46:28.19#ibcon#*before return 0, iclass 7, count 0 2006.257.18:46:28.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:46:28.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.18:46:28.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:46:28.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:46:28.19$vck44/vblo=1,629.99 2006.257.18:46:28.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.18:46:28.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.18:46:28.19#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:28.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:28.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:28.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:28.19#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:46:28.19#ibcon#first serial, iclass 11, count 0 2006.257.18:46:28.19#ibcon#enter sib2, iclass 11, count 0 2006.257.18:46:28.19#ibcon#flushed, iclass 11, count 0 2006.257.18:46:28.19#ibcon#about to write, iclass 11, count 0 2006.257.18:46:28.19#ibcon#wrote, iclass 11, count 0 2006.257.18:46:28.19#ibcon#about to read 3, iclass 11, count 0 2006.257.18:46:28.21#ibcon#read 3, iclass 11, count 0 2006.257.18:46:28.21#ibcon#about to read 4, iclass 11, count 0 2006.257.18:46:28.21#ibcon#read 4, iclass 11, count 0 2006.257.18:46:28.21#ibcon#about to read 5, iclass 11, count 0 2006.257.18:46:28.21#ibcon#read 5, iclass 11, count 0 2006.257.18:46:28.21#ibcon#about to read 6, iclass 11, count 0 2006.257.18:46:28.21#ibcon#read 6, iclass 11, count 0 2006.257.18:46:28.21#ibcon#end of sib2, iclass 11, count 0 2006.257.18:46:28.21#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:46:28.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:46:28.21#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:46:28.21#ibcon#*before write, iclass 11, count 0 2006.257.18:46:28.21#ibcon#enter sib2, iclass 11, count 0 2006.257.18:46:28.21#ibcon#flushed, iclass 11, count 0 2006.257.18:46:28.21#ibcon#about to write, iclass 11, count 0 2006.257.18:46:28.21#ibcon#wrote, iclass 11, count 0 2006.257.18:46:28.21#ibcon#about to read 3, iclass 11, count 0 2006.257.18:46:28.25#ibcon#read 3, iclass 11, count 0 2006.257.18:46:28.25#ibcon#about to read 4, iclass 11, count 0 2006.257.18:46:28.25#ibcon#read 4, iclass 11, count 0 2006.257.18:46:28.25#ibcon#about to read 5, iclass 11, count 0 2006.257.18:46:28.25#ibcon#read 5, iclass 11, count 0 2006.257.18:46:28.25#ibcon#about to read 6, iclass 11, count 0 2006.257.18:46:28.25#ibcon#read 6, iclass 11, count 0 2006.257.18:46:28.25#ibcon#end of sib2, iclass 11, count 0 2006.257.18:46:28.25#ibcon#*after write, iclass 11, count 0 2006.257.18:46:28.25#ibcon#*before return 0, iclass 11, count 0 2006.257.18:46:28.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:28.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.18:46:28.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:46:28.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:46:28.25$vck44/vb=1,4 2006.257.18:46:28.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.18:46:28.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.18:46:28.25#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:28.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:28.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:28.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:28.25#ibcon#enter wrdev, iclass 13, count 2 2006.257.18:46:28.25#ibcon#first serial, iclass 13, count 2 2006.257.18:46:28.25#ibcon#enter sib2, iclass 13, count 2 2006.257.18:46:28.25#ibcon#flushed, iclass 13, count 2 2006.257.18:46:28.25#ibcon#about to write, iclass 13, count 2 2006.257.18:46:28.25#ibcon#wrote, iclass 13, count 2 2006.257.18:46:28.25#ibcon#about to read 3, iclass 13, count 2 2006.257.18:46:28.27#ibcon#read 3, iclass 13, count 2 2006.257.18:46:28.27#ibcon#about to read 4, iclass 13, count 2 2006.257.18:46:28.27#ibcon#read 4, iclass 13, count 2 2006.257.18:46:28.27#ibcon#about to read 5, iclass 13, count 2 2006.257.18:46:28.27#ibcon#read 5, iclass 13, count 2 2006.257.18:46:28.27#ibcon#about to read 6, iclass 13, count 2 2006.257.18:46:28.27#ibcon#read 6, iclass 13, count 2 2006.257.18:46:28.27#ibcon#end of sib2, iclass 13, count 2 2006.257.18:46:28.27#ibcon#*mode == 0, iclass 13, count 2 2006.257.18:46:28.27#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.18:46:28.27#ibcon#[27=AT01-04\r\n] 2006.257.18:46:28.27#ibcon#*before write, iclass 13, count 2 2006.257.18:46:28.27#ibcon#enter sib2, iclass 13, count 2 2006.257.18:46:28.27#ibcon#flushed, iclass 13, count 2 2006.257.18:46:28.27#ibcon#about to write, iclass 13, count 2 2006.257.18:46:28.27#ibcon#wrote, iclass 13, count 2 2006.257.18:46:28.27#ibcon#about to read 3, iclass 13, count 2 2006.257.18:46:28.30#ibcon#read 3, iclass 13, count 2 2006.257.18:46:28.30#ibcon#about to read 4, iclass 13, count 2 2006.257.18:46:28.30#ibcon#read 4, iclass 13, count 2 2006.257.18:46:28.30#ibcon#about to read 5, iclass 13, count 2 2006.257.18:46:28.30#ibcon#read 5, iclass 13, count 2 2006.257.18:46:28.30#ibcon#about to read 6, iclass 13, count 2 2006.257.18:46:28.30#ibcon#read 6, iclass 13, count 2 2006.257.18:46:28.30#ibcon#end of sib2, iclass 13, count 2 2006.257.18:46:28.30#ibcon#*after write, iclass 13, count 2 2006.257.18:46:28.30#ibcon#*before return 0, iclass 13, count 2 2006.257.18:46:28.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:28.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.18:46:28.30#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.18:46:28.30#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:28.30#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:28.42#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:28.42#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:28.42#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:46:28.42#ibcon#first serial, iclass 13, count 0 2006.257.18:46:28.42#ibcon#enter sib2, iclass 13, count 0 2006.257.18:46:28.42#ibcon#flushed, iclass 13, count 0 2006.257.18:46:28.42#ibcon#about to write, iclass 13, count 0 2006.257.18:46:28.42#ibcon#wrote, iclass 13, count 0 2006.257.18:46:28.42#ibcon#about to read 3, iclass 13, count 0 2006.257.18:46:28.44#ibcon#read 3, iclass 13, count 0 2006.257.18:46:28.44#ibcon#about to read 4, iclass 13, count 0 2006.257.18:46:28.44#ibcon#read 4, iclass 13, count 0 2006.257.18:46:28.44#ibcon#about to read 5, iclass 13, count 0 2006.257.18:46:28.44#ibcon#read 5, iclass 13, count 0 2006.257.18:46:28.44#ibcon#about to read 6, iclass 13, count 0 2006.257.18:46:28.44#ibcon#read 6, iclass 13, count 0 2006.257.18:46:28.44#ibcon#end of sib2, iclass 13, count 0 2006.257.18:46:28.44#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:46:28.44#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:46:28.44#ibcon#[27=USB\r\n] 2006.257.18:46:28.44#ibcon#*before write, iclass 13, count 0 2006.257.18:46:28.44#ibcon#enter sib2, iclass 13, count 0 2006.257.18:46:28.44#ibcon#flushed, iclass 13, count 0 2006.257.18:46:28.44#ibcon#about to write, iclass 13, count 0 2006.257.18:46:28.44#ibcon#wrote, iclass 13, count 0 2006.257.18:46:28.44#ibcon#about to read 3, iclass 13, count 0 2006.257.18:46:28.47#ibcon#read 3, iclass 13, count 0 2006.257.18:46:28.47#ibcon#about to read 4, iclass 13, count 0 2006.257.18:46:28.47#ibcon#read 4, iclass 13, count 0 2006.257.18:46:28.47#ibcon#about to read 5, iclass 13, count 0 2006.257.18:46:28.47#ibcon#read 5, iclass 13, count 0 2006.257.18:46:28.47#ibcon#about to read 6, iclass 13, count 0 2006.257.18:46:28.47#ibcon#read 6, iclass 13, count 0 2006.257.18:46:28.47#ibcon#end of sib2, iclass 13, count 0 2006.257.18:46:28.47#ibcon#*after write, iclass 13, count 0 2006.257.18:46:28.47#ibcon#*before return 0, iclass 13, count 0 2006.257.18:46:28.47#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:28.47#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.18:46:28.47#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:46:28.47#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:46:28.47$vck44/vblo=2,634.99 2006.257.18:46:28.47#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.18:46:28.47#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.18:46:28.47#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:28.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:28.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:28.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:28.47#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:46:28.47#ibcon#first serial, iclass 15, count 0 2006.257.18:46:28.47#ibcon#enter sib2, iclass 15, count 0 2006.257.18:46:28.47#ibcon#flushed, iclass 15, count 0 2006.257.18:46:28.47#ibcon#about to write, iclass 15, count 0 2006.257.18:46:28.47#ibcon#wrote, iclass 15, count 0 2006.257.18:46:28.47#ibcon#about to read 3, iclass 15, count 0 2006.257.18:46:28.49#ibcon#read 3, iclass 15, count 0 2006.257.18:46:28.49#ibcon#about to read 4, iclass 15, count 0 2006.257.18:46:28.49#ibcon#read 4, iclass 15, count 0 2006.257.18:46:28.49#ibcon#about to read 5, iclass 15, count 0 2006.257.18:46:28.49#ibcon#read 5, iclass 15, count 0 2006.257.18:46:28.49#ibcon#about to read 6, iclass 15, count 0 2006.257.18:46:28.49#ibcon#read 6, iclass 15, count 0 2006.257.18:46:28.49#ibcon#end of sib2, iclass 15, count 0 2006.257.18:46:28.49#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:46:28.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:46:28.49#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:46:28.49#ibcon#*before write, iclass 15, count 0 2006.257.18:46:28.49#ibcon#enter sib2, iclass 15, count 0 2006.257.18:46:28.49#ibcon#flushed, iclass 15, count 0 2006.257.18:46:28.49#ibcon#about to write, iclass 15, count 0 2006.257.18:46:28.49#ibcon#wrote, iclass 15, count 0 2006.257.18:46:28.49#ibcon#about to read 3, iclass 15, count 0 2006.257.18:46:28.53#ibcon#read 3, iclass 15, count 0 2006.257.18:46:28.53#ibcon#about to read 4, iclass 15, count 0 2006.257.18:46:28.53#ibcon#read 4, iclass 15, count 0 2006.257.18:46:28.53#ibcon#about to read 5, iclass 15, count 0 2006.257.18:46:28.53#ibcon#read 5, iclass 15, count 0 2006.257.18:46:28.53#ibcon#about to read 6, iclass 15, count 0 2006.257.18:46:28.53#ibcon#read 6, iclass 15, count 0 2006.257.18:46:28.53#ibcon#end of sib2, iclass 15, count 0 2006.257.18:46:28.53#ibcon#*after write, iclass 15, count 0 2006.257.18:46:28.53#ibcon#*before return 0, iclass 15, count 0 2006.257.18:46:28.53#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:28.53#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.18:46:28.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:46:28.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:46:28.53$vck44/vb=2,5 2006.257.18:46:28.53#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.18:46:28.53#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.18:46:28.53#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:28.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:28.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:28.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:28.59#ibcon#enter wrdev, iclass 17, count 2 2006.257.18:46:28.59#ibcon#first serial, iclass 17, count 2 2006.257.18:46:28.59#ibcon#enter sib2, iclass 17, count 2 2006.257.18:46:28.59#ibcon#flushed, iclass 17, count 2 2006.257.18:46:28.59#ibcon#about to write, iclass 17, count 2 2006.257.18:46:28.59#ibcon#wrote, iclass 17, count 2 2006.257.18:46:28.59#ibcon#about to read 3, iclass 17, count 2 2006.257.18:46:28.61#ibcon#read 3, iclass 17, count 2 2006.257.18:46:28.61#ibcon#about to read 4, iclass 17, count 2 2006.257.18:46:28.61#ibcon#read 4, iclass 17, count 2 2006.257.18:46:28.61#ibcon#about to read 5, iclass 17, count 2 2006.257.18:46:28.61#ibcon#read 5, iclass 17, count 2 2006.257.18:46:28.61#ibcon#about to read 6, iclass 17, count 2 2006.257.18:46:28.61#ibcon#read 6, iclass 17, count 2 2006.257.18:46:28.61#ibcon#end of sib2, iclass 17, count 2 2006.257.18:46:28.61#ibcon#*mode == 0, iclass 17, count 2 2006.257.18:46:28.61#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.18:46:28.61#ibcon#[27=AT02-05\r\n] 2006.257.18:46:28.61#ibcon#*before write, iclass 17, count 2 2006.257.18:46:28.61#ibcon#enter sib2, iclass 17, count 2 2006.257.18:46:28.61#ibcon#flushed, iclass 17, count 2 2006.257.18:46:28.61#ibcon#about to write, iclass 17, count 2 2006.257.18:46:28.61#ibcon#wrote, iclass 17, count 2 2006.257.18:46:28.61#ibcon#about to read 3, iclass 17, count 2 2006.257.18:46:28.64#ibcon#read 3, iclass 17, count 2 2006.257.18:46:28.64#ibcon#about to read 4, iclass 17, count 2 2006.257.18:46:28.64#ibcon#read 4, iclass 17, count 2 2006.257.18:46:28.64#ibcon#about to read 5, iclass 17, count 2 2006.257.18:46:28.64#ibcon#read 5, iclass 17, count 2 2006.257.18:46:28.64#ibcon#about to read 6, iclass 17, count 2 2006.257.18:46:28.64#ibcon#read 6, iclass 17, count 2 2006.257.18:46:28.64#ibcon#end of sib2, iclass 17, count 2 2006.257.18:46:28.64#ibcon#*after write, iclass 17, count 2 2006.257.18:46:28.64#ibcon#*before return 0, iclass 17, count 2 2006.257.18:46:28.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:28.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.18:46:28.64#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.18:46:28.64#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:28.64#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:28.76#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:28.76#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:28.76#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:46:28.76#ibcon#first serial, iclass 17, count 0 2006.257.18:46:28.76#ibcon#enter sib2, iclass 17, count 0 2006.257.18:46:28.76#ibcon#flushed, iclass 17, count 0 2006.257.18:46:28.76#ibcon#about to write, iclass 17, count 0 2006.257.18:46:28.76#ibcon#wrote, iclass 17, count 0 2006.257.18:46:28.76#ibcon#about to read 3, iclass 17, count 0 2006.257.18:46:28.78#ibcon#read 3, iclass 17, count 0 2006.257.18:46:28.78#ibcon#about to read 4, iclass 17, count 0 2006.257.18:46:28.78#ibcon#read 4, iclass 17, count 0 2006.257.18:46:28.78#ibcon#about to read 5, iclass 17, count 0 2006.257.18:46:28.78#ibcon#read 5, iclass 17, count 0 2006.257.18:46:28.78#ibcon#about to read 6, iclass 17, count 0 2006.257.18:46:28.78#ibcon#read 6, iclass 17, count 0 2006.257.18:46:28.78#ibcon#end of sib2, iclass 17, count 0 2006.257.18:46:28.78#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:46:28.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:46:28.78#ibcon#[27=USB\r\n] 2006.257.18:46:28.78#ibcon#*before write, iclass 17, count 0 2006.257.18:46:28.78#ibcon#enter sib2, iclass 17, count 0 2006.257.18:46:28.78#ibcon#flushed, iclass 17, count 0 2006.257.18:46:28.78#ibcon#about to write, iclass 17, count 0 2006.257.18:46:28.78#ibcon#wrote, iclass 17, count 0 2006.257.18:46:28.78#ibcon#about to read 3, iclass 17, count 0 2006.257.18:46:28.81#ibcon#read 3, iclass 17, count 0 2006.257.18:46:28.81#ibcon#about to read 4, iclass 17, count 0 2006.257.18:46:28.81#ibcon#read 4, iclass 17, count 0 2006.257.18:46:28.81#ibcon#about to read 5, iclass 17, count 0 2006.257.18:46:28.81#ibcon#read 5, iclass 17, count 0 2006.257.18:46:28.81#ibcon#about to read 6, iclass 17, count 0 2006.257.18:46:28.81#ibcon#read 6, iclass 17, count 0 2006.257.18:46:28.81#ibcon#end of sib2, iclass 17, count 0 2006.257.18:46:28.81#ibcon#*after write, iclass 17, count 0 2006.257.18:46:28.81#ibcon#*before return 0, iclass 17, count 0 2006.257.18:46:28.81#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:28.81#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.18:46:28.81#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:46:28.81#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:46:28.81$vck44/vblo=3,649.99 2006.257.18:46:28.81#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.18:46:28.81#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.18:46:28.81#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:28.81#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:28.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:28.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:28.81#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:46:28.81#ibcon#first serial, iclass 19, count 0 2006.257.18:46:28.81#ibcon#enter sib2, iclass 19, count 0 2006.257.18:46:28.81#ibcon#flushed, iclass 19, count 0 2006.257.18:46:28.81#ibcon#about to write, iclass 19, count 0 2006.257.18:46:28.81#ibcon#wrote, iclass 19, count 0 2006.257.18:46:28.81#ibcon#about to read 3, iclass 19, count 0 2006.257.18:46:28.83#ibcon#read 3, iclass 19, count 0 2006.257.18:46:28.83#ibcon#about to read 4, iclass 19, count 0 2006.257.18:46:28.83#ibcon#read 4, iclass 19, count 0 2006.257.18:46:28.83#ibcon#about to read 5, iclass 19, count 0 2006.257.18:46:28.83#ibcon#read 5, iclass 19, count 0 2006.257.18:46:28.83#ibcon#about to read 6, iclass 19, count 0 2006.257.18:46:28.83#ibcon#read 6, iclass 19, count 0 2006.257.18:46:28.83#ibcon#end of sib2, iclass 19, count 0 2006.257.18:46:28.83#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:46:28.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:46:28.83#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:46:28.83#ibcon#*before write, iclass 19, count 0 2006.257.18:46:28.83#ibcon#enter sib2, iclass 19, count 0 2006.257.18:46:28.83#ibcon#flushed, iclass 19, count 0 2006.257.18:46:28.83#ibcon#about to write, iclass 19, count 0 2006.257.18:46:28.83#ibcon#wrote, iclass 19, count 0 2006.257.18:46:28.83#ibcon#about to read 3, iclass 19, count 0 2006.257.18:46:28.87#ibcon#read 3, iclass 19, count 0 2006.257.18:46:28.87#ibcon#about to read 4, iclass 19, count 0 2006.257.18:46:28.87#ibcon#read 4, iclass 19, count 0 2006.257.18:46:28.87#ibcon#about to read 5, iclass 19, count 0 2006.257.18:46:28.87#ibcon#read 5, iclass 19, count 0 2006.257.18:46:28.87#ibcon#about to read 6, iclass 19, count 0 2006.257.18:46:28.87#ibcon#read 6, iclass 19, count 0 2006.257.18:46:28.87#ibcon#end of sib2, iclass 19, count 0 2006.257.18:46:28.87#ibcon#*after write, iclass 19, count 0 2006.257.18:46:28.87#ibcon#*before return 0, iclass 19, count 0 2006.257.18:46:28.87#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:28.87#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.18:46:28.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:46:28.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:46:28.87$vck44/vb=3,4 2006.257.18:46:28.87#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.18:46:28.87#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.18:46:28.87#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:28.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:28.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:28.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:28.93#ibcon#enter wrdev, iclass 21, count 2 2006.257.18:46:28.93#ibcon#first serial, iclass 21, count 2 2006.257.18:46:28.93#ibcon#enter sib2, iclass 21, count 2 2006.257.18:46:28.93#ibcon#flushed, iclass 21, count 2 2006.257.18:46:28.93#ibcon#about to write, iclass 21, count 2 2006.257.18:46:28.93#ibcon#wrote, iclass 21, count 2 2006.257.18:46:28.93#ibcon#about to read 3, iclass 21, count 2 2006.257.18:46:28.95#ibcon#read 3, iclass 21, count 2 2006.257.18:46:28.95#ibcon#about to read 4, iclass 21, count 2 2006.257.18:46:28.95#ibcon#read 4, iclass 21, count 2 2006.257.18:46:28.95#ibcon#about to read 5, iclass 21, count 2 2006.257.18:46:28.95#ibcon#read 5, iclass 21, count 2 2006.257.18:46:28.95#ibcon#about to read 6, iclass 21, count 2 2006.257.18:46:28.95#ibcon#read 6, iclass 21, count 2 2006.257.18:46:28.95#ibcon#end of sib2, iclass 21, count 2 2006.257.18:46:28.95#ibcon#*mode == 0, iclass 21, count 2 2006.257.18:46:28.95#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.18:46:28.95#ibcon#[27=AT03-04\r\n] 2006.257.18:46:28.95#ibcon#*before write, iclass 21, count 2 2006.257.18:46:28.95#ibcon#enter sib2, iclass 21, count 2 2006.257.18:46:28.95#ibcon#flushed, iclass 21, count 2 2006.257.18:46:28.95#ibcon#about to write, iclass 21, count 2 2006.257.18:46:28.95#ibcon#wrote, iclass 21, count 2 2006.257.18:46:28.95#ibcon#about to read 3, iclass 21, count 2 2006.257.18:46:28.98#ibcon#read 3, iclass 21, count 2 2006.257.18:46:28.98#ibcon#about to read 4, iclass 21, count 2 2006.257.18:46:28.98#ibcon#read 4, iclass 21, count 2 2006.257.18:46:28.98#ibcon#about to read 5, iclass 21, count 2 2006.257.18:46:28.98#ibcon#read 5, iclass 21, count 2 2006.257.18:46:28.98#ibcon#about to read 6, iclass 21, count 2 2006.257.18:46:28.98#ibcon#read 6, iclass 21, count 2 2006.257.18:46:28.98#ibcon#end of sib2, iclass 21, count 2 2006.257.18:46:28.98#ibcon#*after write, iclass 21, count 2 2006.257.18:46:28.98#ibcon#*before return 0, iclass 21, count 2 2006.257.18:46:28.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:28.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.18:46:28.98#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.18:46:28.98#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:28.98#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:29.10#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:29.10#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:29.10#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:46:29.10#ibcon#first serial, iclass 21, count 0 2006.257.18:46:29.10#ibcon#enter sib2, iclass 21, count 0 2006.257.18:46:29.10#ibcon#flushed, iclass 21, count 0 2006.257.18:46:29.10#ibcon#about to write, iclass 21, count 0 2006.257.18:46:29.10#ibcon#wrote, iclass 21, count 0 2006.257.18:46:29.10#ibcon#about to read 3, iclass 21, count 0 2006.257.18:46:29.12#ibcon#read 3, iclass 21, count 0 2006.257.18:46:29.12#ibcon#about to read 4, iclass 21, count 0 2006.257.18:46:29.12#ibcon#read 4, iclass 21, count 0 2006.257.18:46:29.12#ibcon#about to read 5, iclass 21, count 0 2006.257.18:46:29.12#ibcon#read 5, iclass 21, count 0 2006.257.18:46:29.12#ibcon#about to read 6, iclass 21, count 0 2006.257.18:46:29.12#ibcon#read 6, iclass 21, count 0 2006.257.18:46:29.12#ibcon#end of sib2, iclass 21, count 0 2006.257.18:46:29.12#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:46:29.12#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:46:29.12#ibcon#[27=USB\r\n] 2006.257.18:46:29.12#ibcon#*before write, iclass 21, count 0 2006.257.18:46:29.12#ibcon#enter sib2, iclass 21, count 0 2006.257.18:46:29.12#ibcon#flushed, iclass 21, count 0 2006.257.18:46:29.12#ibcon#about to write, iclass 21, count 0 2006.257.18:46:29.12#ibcon#wrote, iclass 21, count 0 2006.257.18:46:29.12#ibcon#about to read 3, iclass 21, count 0 2006.257.18:46:29.15#ibcon#read 3, iclass 21, count 0 2006.257.18:46:29.15#ibcon#about to read 4, iclass 21, count 0 2006.257.18:46:29.15#ibcon#read 4, iclass 21, count 0 2006.257.18:46:29.15#ibcon#about to read 5, iclass 21, count 0 2006.257.18:46:29.15#ibcon#read 5, iclass 21, count 0 2006.257.18:46:29.15#ibcon#about to read 6, iclass 21, count 0 2006.257.18:46:29.15#ibcon#read 6, iclass 21, count 0 2006.257.18:46:29.15#ibcon#end of sib2, iclass 21, count 0 2006.257.18:46:29.15#ibcon#*after write, iclass 21, count 0 2006.257.18:46:29.15#ibcon#*before return 0, iclass 21, count 0 2006.257.18:46:29.15#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:29.15#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.18:46:29.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:46:29.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:46:29.15$vck44/vblo=4,679.99 2006.257.18:46:29.15#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.18:46:29.15#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.18:46:29.15#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:29.15#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:29.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:29.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:29.15#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:46:29.15#ibcon#first serial, iclass 23, count 0 2006.257.18:46:29.15#ibcon#enter sib2, iclass 23, count 0 2006.257.18:46:29.15#ibcon#flushed, iclass 23, count 0 2006.257.18:46:29.15#ibcon#about to write, iclass 23, count 0 2006.257.18:46:29.15#ibcon#wrote, iclass 23, count 0 2006.257.18:46:29.15#ibcon#about to read 3, iclass 23, count 0 2006.257.18:46:29.17#ibcon#read 3, iclass 23, count 0 2006.257.18:46:29.17#ibcon#about to read 4, iclass 23, count 0 2006.257.18:46:29.17#ibcon#read 4, iclass 23, count 0 2006.257.18:46:29.17#ibcon#about to read 5, iclass 23, count 0 2006.257.18:46:29.17#ibcon#read 5, iclass 23, count 0 2006.257.18:46:29.17#ibcon#about to read 6, iclass 23, count 0 2006.257.18:46:29.17#ibcon#read 6, iclass 23, count 0 2006.257.18:46:29.17#ibcon#end of sib2, iclass 23, count 0 2006.257.18:46:29.17#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:46:29.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:46:29.17#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:46:29.17#ibcon#*before write, iclass 23, count 0 2006.257.18:46:29.17#ibcon#enter sib2, iclass 23, count 0 2006.257.18:46:29.17#ibcon#flushed, iclass 23, count 0 2006.257.18:46:29.17#ibcon#about to write, iclass 23, count 0 2006.257.18:46:29.17#ibcon#wrote, iclass 23, count 0 2006.257.18:46:29.17#ibcon#about to read 3, iclass 23, count 0 2006.257.18:46:29.21#ibcon#read 3, iclass 23, count 0 2006.257.18:46:29.21#ibcon#about to read 4, iclass 23, count 0 2006.257.18:46:29.21#ibcon#read 4, iclass 23, count 0 2006.257.18:46:29.21#ibcon#about to read 5, iclass 23, count 0 2006.257.18:46:29.21#ibcon#read 5, iclass 23, count 0 2006.257.18:46:29.21#ibcon#about to read 6, iclass 23, count 0 2006.257.18:46:29.21#ibcon#read 6, iclass 23, count 0 2006.257.18:46:29.21#ibcon#end of sib2, iclass 23, count 0 2006.257.18:46:29.21#ibcon#*after write, iclass 23, count 0 2006.257.18:46:29.21#ibcon#*before return 0, iclass 23, count 0 2006.257.18:46:29.21#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:29.21#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.18:46:29.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:46:29.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:46:29.21$vck44/vb=4,5 2006.257.18:46:29.21#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.18:46:29.21#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.18:46:29.21#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:29.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:29.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:29.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:29.27#ibcon#enter wrdev, iclass 25, count 2 2006.257.18:46:29.27#ibcon#first serial, iclass 25, count 2 2006.257.18:46:29.27#ibcon#enter sib2, iclass 25, count 2 2006.257.18:46:29.27#ibcon#flushed, iclass 25, count 2 2006.257.18:46:29.27#ibcon#about to write, iclass 25, count 2 2006.257.18:46:29.27#ibcon#wrote, iclass 25, count 2 2006.257.18:46:29.27#ibcon#about to read 3, iclass 25, count 2 2006.257.18:46:29.29#ibcon#read 3, iclass 25, count 2 2006.257.18:46:29.29#ibcon#about to read 4, iclass 25, count 2 2006.257.18:46:29.29#ibcon#read 4, iclass 25, count 2 2006.257.18:46:29.29#ibcon#about to read 5, iclass 25, count 2 2006.257.18:46:29.29#ibcon#read 5, iclass 25, count 2 2006.257.18:46:29.29#ibcon#about to read 6, iclass 25, count 2 2006.257.18:46:29.29#ibcon#read 6, iclass 25, count 2 2006.257.18:46:29.29#ibcon#end of sib2, iclass 25, count 2 2006.257.18:46:29.29#ibcon#*mode == 0, iclass 25, count 2 2006.257.18:46:29.29#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.18:46:29.29#ibcon#[27=AT04-05\r\n] 2006.257.18:46:29.29#ibcon#*before write, iclass 25, count 2 2006.257.18:46:29.29#ibcon#enter sib2, iclass 25, count 2 2006.257.18:46:29.29#ibcon#flushed, iclass 25, count 2 2006.257.18:46:29.29#ibcon#about to write, iclass 25, count 2 2006.257.18:46:29.29#ibcon#wrote, iclass 25, count 2 2006.257.18:46:29.29#ibcon#about to read 3, iclass 25, count 2 2006.257.18:46:29.32#ibcon#read 3, iclass 25, count 2 2006.257.18:46:29.32#ibcon#about to read 4, iclass 25, count 2 2006.257.18:46:29.32#ibcon#read 4, iclass 25, count 2 2006.257.18:46:29.32#ibcon#about to read 5, iclass 25, count 2 2006.257.18:46:29.32#ibcon#read 5, iclass 25, count 2 2006.257.18:46:29.32#ibcon#about to read 6, iclass 25, count 2 2006.257.18:46:29.32#ibcon#read 6, iclass 25, count 2 2006.257.18:46:29.32#ibcon#end of sib2, iclass 25, count 2 2006.257.18:46:29.32#ibcon#*after write, iclass 25, count 2 2006.257.18:46:29.32#ibcon#*before return 0, iclass 25, count 2 2006.257.18:46:29.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:29.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.18:46:29.32#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.18:46:29.32#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:29.32#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:29.44#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:29.44#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:29.44#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:46:29.44#ibcon#first serial, iclass 25, count 0 2006.257.18:46:29.44#ibcon#enter sib2, iclass 25, count 0 2006.257.18:46:29.44#ibcon#flushed, iclass 25, count 0 2006.257.18:46:29.44#ibcon#about to write, iclass 25, count 0 2006.257.18:46:29.44#ibcon#wrote, iclass 25, count 0 2006.257.18:46:29.44#ibcon#about to read 3, iclass 25, count 0 2006.257.18:46:29.46#ibcon#read 3, iclass 25, count 0 2006.257.18:46:29.46#ibcon#about to read 4, iclass 25, count 0 2006.257.18:46:29.46#ibcon#read 4, iclass 25, count 0 2006.257.18:46:29.46#ibcon#about to read 5, iclass 25, count 0 2006.257.18:46:29.46#ibcon#read 5, iclass 25, count 0 2006.257.18:46:29.46#ibcon#about to read 6, iclass 25, count 0 2006.257.18:46:29.46#ibcon#read 6, iclass 25, count 0 2006.257.18:46:29.46#ibcon#end of sib2, iclass 25, count 0 2006.257.18:46:29.46#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:46:29.46#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:46:29.46#ibcon#[27=USB\r\n] 2006.257.18:46:29.46#ibcon#*before write, iclass 25, count 0 2006.257.18:46:29.46#ibcon#enter sib2, iclass 25, count 0 2006.257.18:46:29.46#ibcon#flushed, iclass 25, count 0 2006.257.18:46:29.46#ibcon#about to write, iclass 25, count 0 2006.257.18:46:29.46#ibcon#wrote, iclass 25, count 0 2006.257.18:46:29.46#ibcon#about to read 3, iclass 25, count 0 2006.257.18:46:29.49#ibcon#read 3, iclass 25, count 0 2006.257.18:46:29.49#ibcon#about to read 4, iclass 25, count 0 2006.257.18:46:29.49#ibcon#read 4, iclass 25, count 0 2006.257.18:46:29.49#ibcon#about to read 5, iclass 25, count 0 2006.257.18:46:29.49#ibcon#read 5, iclass 25, count 0 2006.257.18:46:29.49#ibcon#about to read 6, iclass 25, count 0 2006.257.18:46:29.49#ibcon#read 6, iclass 25, count 0 2006.257.18:46:29.49#ibcon#end of sib2, iclass 25, count 0 2006.257.18:46:29.49#ibcon#*after write, iclass 25, count 0 2006.257.18:46:29.49#ibcon#*before return 0, iclass 25, count 0 2006.257.18:46:29.49#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:29.49#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.18:46:29.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:46:29.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:46:29.49$vck44/vblo=5,709.99 2006.257.18:46:29.49#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.18:46:29.49#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.18:46:29.49#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:29.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:29.49#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:29.49#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:29.49#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:46:29.49#ibcon#first serial, iclass 27, count 0 2006.257.18:46:29.49#ibcon#enter sib2, iclass 27, count 0 2006.257.18:46:29.49#ibcon#flushed, iclass 27, count 0 2006.257.18:46:29.49#ibcon#about to write, iclass 27, count 0 2006.257.18:46:29.49#ibcon#wrote, iclass 27, count 0 2006.257.18:46:29.49#ibcon#about to read 3, iclass 27, count 0 2006.257.18:46:29.51#ibcon#read 3, iclass 27, count 0 2006.257.18:46:29.51#ibcon#about to read 4, iclass 27, count 0 2006.257.18:46:29.51#ibcon#read 4, iclass 27, count 0 2006.257.18:46:29.51#ibcon#about to read 5, iclass 27, count 0 2006.257.18:46:29.51#ibcon#read 5, iclass 27, count 0 2006.257.18:46:29.51#ibcon#about to read 6, iclass 27, count 0 2006.257.18:46:29.51#ibcon#read 6, iclass 27, count 0 2006.257.18:46:29.51#ibcon#end of sib2, iclass 27, count 0 2006.257.18:46:29.51#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:46:29.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:46:29.51#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:46:29.51#ibcon#*before write, iclass 27, count 0 2006.257.18:46:29.51#ibcon#enter sib2, iclass 27, count 0 2006.257.18:46:29.51#ibcon#flushed, iclass 27, count 0 2006.257.18:46:29.51#ibcon#about to write, iclass 27, count 0 2006.257.18:46:29.51#ibcon#wrote, iclass 27, count 0 2006.257.18:46:29.51#ibcon#about to read 3, iclass 27, count 0 2006.257.18:46:29.55#ibcon#read 3, iclass 27, count 0 2006.257.18:46:29.55#ibcon#about to read 4, iclass 27, count 0 2006.257.18:46:29.55#ibcon#read 4, iclass 27, count 0 2006.257.18:46:29.55#ibcon#about to read 5, iclass 27, count 0 2006.257.18:46:29.55#ibcon#read 5, iclass 27, count 0 2006.257.18:46:29.55#ibcon#about to read 6, iclass 27, count 0 2006.257.18:46:29.55#ibcon#read 6, iclass 27, count 0 2006.257.18:46:29.55#ibcon#end of sib2, iclass 27, count 0 2006.257.18:46:29.55#ibcon#*after write, iclass 27, count 0 2006.257.18:46:29.55#ibcon#*before return 0, iclass 27, count 0 2006.257.18:46:29.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:29.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.18:46:29.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:46:29.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:46:29.55$vck44/vb=5,4 2006.257.18:46:29.55#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.18:46:29.55#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.18:46:29.55#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:29.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:29.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:29.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:29.61#ibcon#enter wrdev, iclass 29, count 2 2006.257.18:46:29.61#ibcon#first serial, iclass 29, count 2 2006.257.18:46:29.61#ibcon#enter sib2, iclass 29, count 2 2006.257.18:46:29.61#ibcon#flushed, iclass 29, count 2 2006.257.18:46:29.61#ibcon#about to write, iclass 29, count 2 2006.257.18:46:29.61#ibcon#wrote, iclass 29, count 2 2006.257.18:46:29.61#ibcon#about to read 3, iclass 29, count 2 2006.257.18:46:29.63#ibcon#read 3, iclass 29, count 2 2006.257.18:46:29.63#ibcon#about to read 4, iclass 29, count 2 2006.257.18:46:29.63#ibcon#read 4, iclass 29, count 2 2006.257.18:46:29.63#ibcon#about to read 5, iclass 29, count 2 2006.257.18:46:29.63#ibcon#read 5, iclass 29, count 2 2006.257.18:46:29.63#ibcon#about to read 6, iclass 29, count 2 2006.257.18:46:29.63#ibcon#read 6, iclass 29, count 2 2006.257.18:46:29.63#ibcon#end of sib2, iclass 29, count 2 2006.257.18:46:29.63#ibcon#*mode == 0, iclass 29, count 2 2006.257.18:46:29.63#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.18:46:29.63#ibcon#[27=AT05-04\r\n] 2006.257.18:46:29.63#ibcon#*before write, iclass 29, count 2 2006.257.18:46:29.63#ibcon#enter sib2, iclass 29, count 2 2006.257.18:46:29.63#ibcon#flushed, iclass 29, count 2 2006.257.18:46:29.63#ibcon#about to write, iclass 29, count 2 2006.257.18:46:29.63#ibcon#wrote, iclass 29, count 2 2006.257.18:46:29.63#ibcon#about to read 3, iclass 29, count 2 2006.257.18:46:29.66#ibcon#read 3, iclass 29, count 2 2006.257.18:46:29.66#ibcon#about to read 4, iclass 29, count 2 2006.257.18:46:29.66#ibcon#read 4, iclass 29, count 2 2006.257.18:46:29.66#ibcon#about to read 5, iclass 29, count 2 2006.257.18:46:29.66#ibcon#read 5, iclass 29, count 2 2006.257.18:46:29.66#ibcon#about to read 6, iclass 29, count 2 2006.257.18:46:29.66#ibcon#read 6, iclass 29, count 2 2006.257.18:46:29.66#ibcon#end of sib2, iclass 29, count 2 2006.257.18:46:29.66#ibcon#*after write, iclass 29, count 2 2006.257.18:46:29.66#ibcon#*before return 0, iclass 29, count 2 2006.257.18:46:29.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:29.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.18:46:29.66#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.18:46:29.66#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:29.66#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:29.78#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:29.78#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:29.78#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:46:29.78#ibcon#first serial, iclass 29, count 0 2006.257.18:46:29.78#ibcon#enter sib2, iclass 29, count 0 2006.257.18:46:29.78#ibcon#flushed, iclass 29, count 0 2006.257.18:46:29.78#ibcon#about to write, iclass 29, count 0 2006.257.18:46:29.78#ibcon#wrote, iclass 29, count 0 2006.257.18:46:29.78#ibcon#about to read 3, iclass 29, count 0 2006.257.18:46:29.80#ibcon#read 3, iclass 29, count 0 2006.257.18:46:29.80#ibcon#about to read 4, iclass 29, count 0 2006.257.18:46:29.80#ibcon#read 4, iclass 29, count 0 2006.257.18:46:29.80#ibcon#about to read 5, iclass 29, count 0 2006.257.18:46:29.80#ibcon#read 5, iclass 29, count 0 2006.257.18:46:29.80#ibcon#about to read 6, iclass 29, count 0 2006.257.18:46:29.80#ibcon#read 6, iclass 29, count 0 2006.257.18:46:29.80#ibcon#end of sib2, iclass 29, count 0 2006.257.18:46:29.80#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:46:29.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:46:29.80#ibcon#[27=USB\r\n] 2006.257.18:46:29.80#ibcon#*before write, iclass 29, count 0 2006.257.18:46:29.80#ibcon#enter sib2, iclass 29, count 0 2006.257.18:46:29.80#ibcon#flushed, iclass 29, count 0 2006.257.18:46:29.80#ibcon#about to write, iclass 29, count 0 2006.257.18:46:29.80#ibcon#wrote, iclass 29, count 0 2006.257.18:46:29.80#ibcon#about to read 3, iclass 29, count 0 2006.257.18:46:29.83#ibcon#read 3, iclass 29, count 0 2006.257.18:46:29.83#ibcon#about to read 4, iclass 29, count 0 2006.257.18:46:29.83#ibcon#read 4, iclass 29, count 0 2006.257.18:46:29.83#ibcon#about to read 5, iclass 29, count 0 2006.257.18:46:29.83#ibcon#read 5, iclass 29, count 0 2006.257.18:46:29.83#ibcon#about to read 6, iclass 29, count 0 2006.257.18:46:29.83#ibcon#read 6, iclass 29, count 0 2006.257.18:46:29.83#ibcon#end of sib2, iclass 29, count 0 2006.257.18:46:29.83#ibcon#*after write, iclass 29, count 0 2006.257.18:46:29.83#ibcon#*before return 0, iclass 29, count 0 2006.257.18:46:29.83#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:29.83#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.18:46:29.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:46:29.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:46:29.83$vck44/vblo=6,719.99 2006.257.18:46:29.83#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.18:46:29.83#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.18:46:29.83#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:29.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:29.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:29.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:29.83#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:46:29.83#ibcon#first serial, iclass 31, count 0 2006.257.18:46:29.83#ibcon#enter sib2, iclass 31, count 0 2006.257.18:46:29.83#ibcon#flushed, iclass 31, count 0 2006.257.18:46:29.83#ibcon#about to write, iclass 31, count 0 2006.257.18:46:29.83#ibcon#wrote, iclass 31, count 0 2006.257.18:46:29.83#ibcon#about to read 3, iclass 31, count 0 2006.257.18:46:29.85#ibcon#read 3, iclass 31, count 0 2006.257.18:46:29.85#ibcon#about to read 4, iclass 31, count 0 2006.257.18:46:29.85#ibcon#read 4, iclass 31, count 0 2006.257.18:46:29.85#ibcon#about to read 5, iclass 31, count 0 2006.257.18:46:29.85#ibcon#read 5, iclass 31, count 0 2006.257.18:46:29.85#ibcon#about to read 6, iclass 31, count 0 2006.257.18:46:29.85#ibcon#read 6, iclass 31, count 0 2006.257.18:46:29.85#ibcon#end of sib2, iclass 31, count 0 2006.257.18:46:29.85#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:46:29.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:46:29.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:46:29.85#ibcon#*before write, iclass 31, count 0 2006.257.18:46:29.85#ibcon#enter sib2, iclass 31, count 0 2006.257.18:46:29.85#ibcon#flushed, iclass 31, count 0 2006.257.18:46:29.85#ibcon#about to write, iclass 31, count 0 2006.257.18:46:29.85#ibcon#wrote, iclass 31, count 0 2006.257.18:46:29.85#ibcon#about to read 3, iclass 31, count 0 2006.257.18:46:29.89#ibcon#read 3, iclass 31, count 0 2006.257.18:46:29.89#ibcon#about to read 4, iclass 31, count 0 2006.257.18:46:29.89#ibcon#read 4, iclass 31, count 0 2006.257.18:46:29.89#ibcon#about to read 5, iclass 31, count 0 2006.257.18:46:29.89#ibcon#read 5, iclass 31, count 0 2006.257.18:46:29.89#ibcon#about to read 6, iclass 31, count 0 2006.257.18:46:29.89#ibcon#read 6, iclass 31, count 0 2006.257.18:46:29.89#ibcon#end of sib2, iclass 31, count 0 2006.257.18:46:29.89#ibcon#*after write, iclass 31, count 0 2006.257.18:46:29.89#ibcon#*before return 0, iclass 31, count 0 2006.257.18:46:29.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:29.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:46:29.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:46:29.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:46:29.89$vck44/vb=6,4 2006.257.18:46:29.89#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.18:46:29.89#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.18:46:29.89#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:29.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:29.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:29.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:29.95#ibcon#enter wrdev, iclass 33, count 2 2006.257.18:46:29.95#ibcon#first serial, iclass 33, count 2 2006.257.18:46:29.95#ibcon#enter sib2, iclass 33, count 2 2006.257.18:46:29.95#ibcon#flushed, iclass 33, count 2 2006.257.18:46:29.95#ibcon#about to write, iclass 33, count 2 2006.257.18:46:29.95#ibcon#wrote, iclass 33, count 2 2006.257.18:46:29.95#ibcon#about to read 3, iclass 33, count 2 2006.257.18:46:29.97#ibcon#read 3, iclass 33, count 2 2006.257.18:46:29.97#ibcon#about to read 4, iclass 33, count 2 2006.257.18:46:29.97#ibcon#read 4, iclass 33, count 2 2006.257.18:46:29.97#ibcon#about to read 5, iclass 33, count 2 2006.257.18:46:29.97#ibcon#read 5, iclass 33, count 2 2006.257.18:46:29.97#ibcon#about to read 6, iclass 33, count 2 2006.257.18:46:29.97#ibcon#read 6, iclass 33, count 2 2006.257.18:46:29.97#ibcon#end of sib2, iclass 33, count 2 2006.257.18:46:29.97#ibcon#*mode == 0, iclass 33, count 2 2006.257.18:46:29.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.18:46:29.97#ibcon#[27=AT06-04\r\n] 2006.257.18:46:29.97#ibcon#*before write, iclass 33, count 2 2006.257.18:46:29.97#ibcon#enter sib2, iclass 33, count 2 2006.257.18:46:29.97#ibcon#flushed, iclass 33, count 2 2006.257.18:46:29.97#ibcon#about to write, iclass 33, count 2 2006.257.18:46:29.97#ibcon#wrote, iclass 33, count 2 2006.257.18:46:29.97#ibcon#about to read 3, iclass 33, count 2 2006.257.18:46:30.00#ibcon#read 3, iclass 33, count 2 2006.257.18:46:30.00#ibcon#about to read 4, iclass 33, count 2 2006.257.18:46:30.00#ibcon#read 4, iclass 33, count 2 2006.257.18:46:30.00#ibcon#about to read 5, iclass 33, count 2 2006.257.18:46:30.00#ibcon#read 5, iclass 33, count 2 2006.257.18:46:30.00#ibcon#about to read 6, iclass 33, count 2 2006.257.18:46:30.00#ibcon#read 6, iclass 33, count 2 2006.257.18:46:30.00#ibcon#end of sib2, iclass 33, count 2 2006.257.18:46:30.00#ibcon#*after write, iclass 33, count 2 2006.257.18:46:30.00#ibcon#*before return 0, iclass 33, count 2 2006.257.18:46:30.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:30.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.18:46:30.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.18:46:30.00#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:30.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:30.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:30.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:30.12#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:46:30.12#ibcon#first serial, iclass 33, count 0 2006.257.18:46:30.12#ibcon#enter sib2, iclass 33, count 0 2006.257.18:46:30.12#ibcon#flushed, iclass 33, count 0 2006.257.18:46:30.12#ibcon#about to write, iclass 33, count 0 2006.257.18:46:30.12#ibcon#wrote, iclass 33, count 0 2006.257.18:46:30.12#ibcon#about to read 3, iclass 33, count 0 2006.257.18:46:30.14#ibcon#read 3, iclass 33, count 0 2006.257.18:46:30.14#ibcon#about to read 4, iclass 33, count 0 2006.257.18:46:30.14#ibcon#read 4, iclass 33, count 0 2006.257.18:46:30.14#ibcon#about to read 5, iclass 33, count 0 2006.257.18:46:30.14#ibcon#read 5, iclass 33, count 0 2006.257.18:46:30.14#ibcon#about to read 6, iclass 33, count 0 2006.257.18:46:30.14#ibcon#read 6, iclass 33, count 0 2006.257.18:46:30.14#ibcon#end of sib2, iclass 33, count 0 2006.257.18:46:30.14#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:46:30.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:46:30.14#ibcon#[27=USB\r\n] 2006.257.18:46:30.14#ibcon#*before write, iclass 33, count 0 2006.257.18:46:30.14#ibcon#enter sib2, iclass 33, count 0 2006.257.18:46:30.14#ibcon#flushed, iclass 33, count 0 2006.257.18:46:30.14#ibcon#about to write, iclass 33, count 0 2006.257.18:46:30.14#ibcon#wrote, iclass 33, count 0 2006.257.18:46:30.14#ibcon#about to read 3, iclass 33, count 0 2006.257.18:46:30.17#ibcon#read 3, iclass 33, count 0 2006.257.18:46:30.17#ibcon#about to read 4, iclass 33, count 0 2006.257.18:46:30.17#ibcon#read 4, iclass 33, count 0 2006.257.18:46:30.17#ibcon#about to read 5, iclass 33, count 0 2006.257.18:46:30.17#ibcon#read 5, iclass 33, count 0 2006.257.18:46:30.17#ibcon#about to read 6, iclass 33, count 0 2006.257.18:46:30.17#ibcon#read 6, iclass 33, count 0 2006.257.18:46:30.17#ibcon#end of sib2, iclass 33, count 0 2006.257.18:46:30.17#ibcon#*after write, iclass 33, count 0 2006.257.18:46:30.17#ibcon#*before return 0, iclass 33, count 0 2006.257.18:46:30.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:30.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.18:46:30.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:46:30.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:46:30.17$vck44/vblo=7,734.99 2006.257.18:46:30.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.18:46:30.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.18:46:30.17#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:30.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:30.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:30.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:30.17#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:46:30.17#ibcon#first serial, iclass 35, count 0 2006.257.18:46:30.17#ibcon#enter sib2, iclass 35, count 0 2006.257.18:46:30.17#ibcon#flushed, iclass 35, count 0 2006.257.18:46:30.17#ibcon#about to write, iclass 35, count 0 2006.257.18:46:30.17#ibcon#wrote, iclass 35, count 0 2006.257.18:46:30.17#ibcon#about to read 3, iclass 35, count 0 2006.257.18:46:30.19#ibcon#read 3, iclass 35, count 0 2006.257.18:46:30.19#ibcon#about to read 4, iclass 35, count 0 2006.257.18:46:30.19#ibcon#read 4, iclass 35, count 0 2006.257.18:46:30.19#ibcon#about to read 5, iclass 35, count 0 2006.257.18:46:30.19#ibcon#read 5, iclass 35, count 0 2006.257.18:46:30.19#ibcon#about to read 6, iclass 35, count 0 2006.257.18:46:30.19#ibcon#read 6, iclass 35, count 0 2006.257.18:46:30.19#ibcon#end of sib2, iclass 35, count 0 2006.257.18:46:30.19#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:46:30.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:46:30.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:46:30.19#ibcon#*before write, iclass 35, count 0 2006.257.18:46:30.19#ibcon#enter sib2, iclass 35, count 0 2006.257.18:46:30.19#ibcon#flushed, iclass 35, count 0 2006.257.18:46:30.19#ibcon#about to write, iclass 35, count 0 2006.257.18:46:30.19#ibcon#wrote, iclass 35, count 0 2006.257.18:46:30.19#ibcon#about to read 3, iclass 35, count 0 2006.257.18:46:30.23#ibcon#read 3, iclass 35, count 0 2006.257.18:46:30.23#ibcon#about to read 4, iclass 35, count 0 2006.257.18:46:30.23#ibcon#read 4, iclass 35, count 0 2006.257.18:46:30.23#ibcon#about to read 5, iclass 35, count 0 2006.257.18:46:30.23#ibcon#read 5, iclass 35, count 0 2006.257.18:46:30.23#ibcon#about to read 6, iclass 35, count 0 2006.257.18:46:30.23#ibcon#read 6, iclass 35, count 0 2006.257.18:46:30.23#ibcon#end of sib2, iclass 35, count 0 2006.257.18:46:30.23#ibcon#*after write, iclass 35, count 0 2006.257.18:46:30.23#ibcon#*before return 0, iclass 35, count 0 2006.257.18:46:30.23#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:30.23#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.18:46:30.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:46:30.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:46:30.23$vck44/vb=7,4 2006.257.18:46:30.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.18:46:30.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.18:46:30.23#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:30.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:46:30.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:46:30.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:46:30.29#ibcon#enter wrdev, iclass 37, count 2 2006.257.18:46:30.29#ibcon#first serial, iclass 37, count 2 2006.257.18:46:30.29#ibcon#enter sib2, iclass 37, count 2 2006.257.18:46:30.29#ibcon#flushed, iclass 37, count 2 2006.257.18:46:30.29#ibcon#about to write, iclass 37, count 2 2006.257.18:46:30.29#ibcon#wrote, iclass 37, count 2 2006.257.18:46:30.29#ibcon#about to read 3, iclass 37, count 2 2006.257.18:46:30.31#ibcon#read 3, iclass 37, count 2 2006.257.18:46:30.31#ibcon#about to read 4, iclass 37, count 2 2006.257.18:46:30.31#ibcon#read 4, iclass 37, count 2 2006.257.18:46:30.31#ibcon#about to read 5, iclass 37, count 2 2006.257.18:46:30.31#ibcon#read 5, iclass 37, count 2 2006.257.18:46:30.31#ibcon#about to read 6, iclass 37, count 2 2006.257.18:46:30.31#ibcon#read 6, iclass 37, count 2 2006.257.18:46:30.31#ibcon#end of sib2, iclass 37, count 2 2006.257.18:46:30.31#ibcon#*mode == 0, iclass 37, count 2 2006.257.18:46:30.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.18:46:30.31#ibcon#[27=AT07-04\r\n] 2006.257.18:46:30.31#ibcon#*before write, iclass 37, count 2 2006.257.18:46:30.31#ibcon#enter sib2, iclass 37, count 2 2006.257.18:46:30.31#ibcon#flushed, iclass 37, count 2 2006.257.18:46:30.31#ibcon#about to write, iclass 37, count 2 2006.257.18:46:30.31#ibcon#wrote, iclass 37, count 2 2006.257.18:46:30.31#ibcon#about to read 3, iclass 37, count 2 2006.257.18:46:30.34#ibcon#read 3, iclass 37, count 2 2006.257.18:46:30.34#ibcon#about to read 4, iclass 37, count 2 2006.257.18:46:30.34#ibcon#read 4, iclass 37, count 2 2006.257.18:46:30.34#ibcon#about to read 5, iclass 37, count 2 2006.257.18:46:30.34#ibcon#read 5, iclass 37, count 2 2006.257.18:46:30.34#ibcon#about to read 6, iclass 37, count 2 2006.257.18:46:30.34#ibcon#read 6, iclass 37, count 2 2006.257.18:46:30.34#ibcon#end of sib2, iclass 37, count 2 2006.257.18:46:30.34#ibcon#*after write, iclass 37, count 2 2006.257.18:46:30.34#ibcon#*before return 0, iclass 37, count 2 2006.257.18:46:30.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:46:30.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.18:46:30.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.18:46:30.34#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:30.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:46:30.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:46:30.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:46:30.46#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:46:30.46#ibcon#first serial, iclass 37, count 0 2006.257.18:46:30.46#ibcon#enter sib2, iclass 37, count 0 2006.257.18:46:30.46#ibcon#flushed, iclass 37, count 0 2006.257.18:46:30.46#ibcon#about to write, iclass 37, count 0 2006.257.18:46:30.46#ibcon#wrote, iclass 37, count 0 2006.257.18:46:30.46#ibcon#about to read 3, iclass 37, count 0 2006.257.18:46:30.48#ibcon#read 3, iclass 37, count 0 2006.257.18:46:30.48#ibcon#about to read 4, iclass 37, count 0 2006.257.18:46:30.48#ibcon#read 4, iclass 37, count 0 2006.257.18:46:30.48#ibcon#about to read 5, iclass 37, count 0 2006.257.18:46:30.48#ibcon#read 5, iclass 37, count 0 2006.257.18:46:30.48#ibcon#about to read 6, iclass 37, count 0 2006.257.18:46:30.48#ibcon#read 6, iclass 37, count 0 2006.257.18:46:30.48#ibcon#end of sib2, iclass 37, count 0 2006.257.18:46:30.48#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:46:30.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:46:30.48#ibcon#[27=USB\r\n] 2006.257.18:46:30.48#ibcon#*before write, iclass 37, count 0 2006.257.18:46:30.48#ibcon#enter sib2, iclass 37, count 0 2006.257.18:46:30.48#ibcon#flushed, iclass 37, count 0 2006.257.18:46:30.48#ibcon#about to write, iclass 37, count 0 2006.257.18:46:30.48#ibcon#wrote, iclass 37, count 0 2006.257.18:46:30.48#ibcon#about to read 3, iclass 37, count 0 2006.257.18:46:30.51#ibcon#read 3, iclass 37, count 0 2006.257.18:46:30.51#ibcon#about to read 4, iclass 37, count 0 2006.257.18:46:30.51#ibcon#read 4, iclass 37, count 0 2006.257.18:46:30.51#ibcon#about to read 5, iclass 37, count 0 2006.257.18:46:30.51#ibcon#read 5, iclass 37, count 0 2006.257.18:46:30.51#ibcon#about to read 6, iclass 37, count 0 2006.257.18:46:30.51#ibcon#read 6, iclass 37, count 0 2006.257.18:46:30.51#ibcon#end of sib2, iclass 37, count 0 2006.257.18:46:30.51#ibcon#*after write, iclass 37, count 0 2006.257.18:46:30.51#ibcon#*before return 0, iclass 37, count 0 2006.257.18:46:30.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:46:30.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.18:46:30.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:46:30.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:46:30.51$vck44/vblo=8,744.99 2006.257.18:46:30.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.18:46:30.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.18:46:30.51#ibcon#ireg 17 cls_cnt 0 2006.257.18:46:30.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:46:30.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:46:30.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:46:30.51#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:46:30.51#ibcon#first serial, iclass 39, count 0 2006.257.18:46:30.51#ibcon#enter sib2, iclass 39, count 0 2006.257.18:46:30.51#ibcon#flushed, iclass 39, count 0 2006.257.18:46:30.51#ibcon#about to write, iclass 39, count 0 2006.257.18:46:30.51#ibcon#wrote, iclass 39, count 0 2006.257.18:46:30.51#ibcon#about to read 3, iclass 39, count 0 2006.257.18:46:30.53#ibcon#read 3, iclass 39, count 0 2006.257.18:46:30.53#ibcon#about to read 4, iclass 39, count 0 2006.257.18:46:30.53#ibcon#read 4, iclass 39, count 0 2006.257.18:46:30.53#ibcon#about to read 5, iclass 39, count 0 2006.257.18:46:30.53#ibcon#read 5, iclass 39, count 0 2006.257.18:46:30.53#ibcon#about to read 6, iclass 39, count 0 2006.257.18:46:30.53#ibcon#read 6, iclass 39, count 0 2006.257.18:46:30.53#ibcon#end of sib2, iclass 39, count 0 2006.257.18:46:30.53#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:46:30.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:46:30.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:46:30.53#ibcon#*before write, iclass 39, count 0 2006.257.18:46:30.53#ibcon#enter sib2, iclass 39, count 0 2006.257.18:46:30.53#ibcon#flushed, iclass 39, count 0 2006.257.18:46:30.53#ibcon#about to write, iclass 39, count 0 2006.257.18:46:30.53#ibcon#wrote, iclass 39, count 0 2006.257.18:46:30.53#ibcon#about to read 3, iclass 39, count 0 2006.257.18:46:30.57#ibcon#read 3, iclass 39, count 0 2006.257.18:46:30.57#ibcon#about to read 4, iclass 39, count 0 2006.257.18:46:30.57#ibcon#read 4, iclass 39, count 0 2006.257.18:46:30.57#ibcon#about to read 5, iclass 39, count 0 2006.257.18:46:30.57#ibcon#read 5, iclass 39, count 0 2006.257.18:46:30.57#ibcon#about to read 6, iclass 39, count 0 2006.257.18:46:30.57#ibcon#read 6, iclass 39, count 0 2006.257.18:46:30.57#ibcon#end of sib2, iclass 39, count 0 2006.257.18:46:30.57#ibcon#*after write, iclass 39, count 0 2006.257.18:46:30.57#ibcon#*before return 0, iclass 39, count 0 2006.257.18:46:30.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:46:30.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.18:46:30.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:46:30.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:46:30.57$vck44/vb=8,4 2006.257.18:46:30.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.18:46:30.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.18:46:30.57#ibcon#ireg 11 cls_cnt 2 2006.257.18:46:30.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:46:30.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:46:30.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:46:30.63#ibcon#enter wrdev, iclass 3, count 2 2006.257.18:46:30.63#ibcon#first serial, iclass 3, count 2 2006.257.18:46:30.63#ibcon#enter sib2, iclass 3, count 2 2006.257.18:46:30.63#ibcon#flushed, iclass 3, count 2 2006.257.18:46:30.63#ibcon#about to write, iclass 3, count 2 2006.257.18:46:30.63#ibcon#wrote, iclass 3, count 2 2006.257.18:46:30.63#ibcon#about to read 3, iclass 3, count 2 2006.257.18:46:30.65#ibcon#read 3, iclass 3, count 2 2006.257.18:46:30.65#ibcon#about to read 4, iclass 3, count 2 2006.257.18:46:30.65#ibcon#read 4, iclass 3, count 2 2006.257.18:46:30.65#ibcon#about to read 5, iclass 3, count 2 2006.257.18:46:30.65#ibcon#read 5, iclass 3, count 2 2006.257.18:46:30.65#ibcon#about to read 6, iclass 3, count 2 2006.257.18:46:30.65#ibcon#read 6, iclass 3, count 2 2006.257.18:46:30.65#ibcon#end of sib2, iclass 3, count 2 2006.257.18:46:30.65#ibcon#*mode == 0, iclass 3, count 2 2006.257.18:46:30.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.18:46:30.65#ibcon#[27=AT08-04\r\n] 2006.257.18:46:30.65#ibcon#*before write, iclass 3, count 2 2006.257.18:46:30.65#ibcon#enter sib2, iclass 3, count 2 2006.257.18:46:30.65#ibcon#flushed, iclass 3, count 2 2006.257.18:46:30.65#ibcon#about to write, iclass 3, count 2 2006.257.18:46:30.65#ibcon#wrote, iclass 3, count 2 2006.257.18:46:30.65#ibcon#about to read 3, iclass 3, count 2 2006.257.18:46:30.68#ibcon#read 3, iclass 3, count 2 2006.257.18:46:30.68#ibcon#about to read 4, iclass 3, count 2 2006.257.18:46:30.68#ibcon#read 4, iclass 3, count 2 2006.257.18:46:30.68#ibcon#about to read 5, iclass 3, count 2 2006.257.18:46:30.68#ibcon#read 5, iclass 3, count 2 2006.257.18:46:30.68#ibcon#about to read 6, iclass 3, count 2 2006.257.18:46:30.68#ibcon#read 6, iclass 3, count 2 2006.257.18:46:30.68#ibcon#end of sib2, iclass 3, count 2 2006.257.18:46:30.68#ibcon#*after write, iclass 3, count 2 2006.257.18:46:30.68#ibcon#*before return 0, iclass 3, count 2 2006.257.18:46:30.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:46:30.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.18:46:30.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.18:46:30.68#ibcon#ireg 7 cls_cnt 0 2006.257.18:46:30.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:46:30.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:46:30.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:46:30.80#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:46:30.80#ibcon#first serial, iclass 3, count 0 2006.257.18:46:30.80#ibcon#enter sib2, iclass 3, count 0 2006.257.18:46:30.80#ibcon#flushed, iclass 3, count 0 2006.257.18:46:30.80#ibcon#about to write, iclass 3, count 0 2006.257.18:46:30.80#ibcon#wrote, iclass 3, count 0 2006.257.18:46:30.80#ibcon#about to read 3, iclass 3, count 0 2006.257.18:46:30.82#ibcon#read 3, iclass 3, count 0 2006.257.18:46:30.82#ibcon#about to read 4, iclass 3, count 0 2006.257.18:46:30.82#ibcon#read 4, iclass 3, count 0 2006.257.18:46:30.82#ibcon#about to read 5, iclass 3, count 0 2006.257.18:46:30.82#ibcon#read 5, iclass 3, count 0 2006.257.18:46:30.82#ibcon#about to read 6, iclass 3, count 0 2006.257.18:46:30.82#ibcon#read 6, iclass 3, count 0 2006.257.18:46:30.82#ibcon#end of sib2, iclass 3, count 0 2006.257.18:46:30.82#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:46:30.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:46:30.82#ibcon#[27=USB\r\n] 2006.257.18:46:30.82#ibcon#*before write, iclass 3, count 0 2006.257.18:46:30.82#ibcon#enter sib2, iclass 3, count 0 2006.257.18:46:30.82#ibcon#flushed, iclass 3, count 0 2006.257.18:46:30.82#ibcon#about to write, iclass 3, count 0 2006.257.18:46:30.82#ibcon#wrote, iclass 3, count 0 2006.257.18:46:30.82#ibcon#about to read 3, iclass 3, count 0 2006.257.18:46:30.85#ibcon#read 3, iclass 3, count 0 2006.257.18:46:30.85#ibcon#about to read 4, iclass 3, count 0 2006.257.18:46:30.85#ibcon#read 4, iclass 3, count 0 2006.257.18:46:30.85#ibcon#about to read 5, iclass 3, count 0 2006.257.18:46:30.85#ibcon#read 5, iclass 3, count 0 2006.257.18:46:30.85#ibcon#about to read 6, iclass 3, count 0 2006.257.18:46:30.85#ibcon#read 6, iclass 3, count 0 2006.257.18:46:30.85#ibcon#end of sib2, iclass 3, count 0 2006.257.18:46:30.85#ibcon#*after write, iclass 3, count 0 2006.257.18:46:30.85#ibcon#*before return 0, iclass 3, count 0 2006.257.18:46:30.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:46:30.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.18:46:30.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:46:30.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:46:30.85$vck44/vabw=wide 2006.257.18:46:30.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.18:46:30.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.18:46:30.85#ibcon#ireg 8 cls_cnt 0 2006.257.18:46:30.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:30.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:30.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:30.85#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:46:30.85#ibcon#first serial, iclass 5, count 0 2006.257.18:46:30.85#ibcon#enter sib2, iclass 5, count 0 2006.257.18:46:30.85#ibcon#flushed, iclass 5, count 0 2006.257.18:46:30.85#ibcon#about to write, iclass 5, count 0 2006.257.18:46:30.85#ibcon#wrote, iclass 5, count 0 2006.257.18:46:30.85#ibcon#about to read 3, iclass 5, count 0 2006.257.18:46:30.87#ibcon#read 3, iclass 5, count 0 2006.257.18:46:30.87#ibcon#about to read 4, iclass 5, count 0 2006.257.18:46:30.87#ibcon#read 4, iclass 5, count 0 2006.257.18:46:30.87#ibcon#about to read 5, iclass 5, count 0 2006.257.18:46:30.87#ibcon#read 5, iclass 5, count 0 2006.257.18:46:30.87#ibcon#about to read 6, iclass 5, count 0 2006.257.18:46:30.87#ibcon#read 6, iclass 5, count 0 2006.257.18:46:30.87#ibcon#end of sib2, iclass 5, count 0 2006.257.18:46:30.87#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:46:30.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:46:30.87#ibcon#[25=BW32\r\n] 2006.257.18:46:30.87#ibcon#*before write, iclass 5, count 0 2006.257.18:46:30.87#ibcon#enter sib2, iclass 5, count 0 2006.257.18:46:30.87#ibcon#flushed, iclass 5, count 0 2006.257.18:46:30.87#ibcon#about to write, iclass 5, count 0 2006.257.18:46:30.87#ibcon#wrote, iclass 5, count 0 2006.257.18:46:30.87#ibcon#about to read 3, iclass 5, count 0 2006.257.18:46:30.90#ibcon#read 3, iclass 5, count 0 2006.257.18:46:30.90#ibcon#about to read 4, iclass 5, count 0 2006.257.18:46:30.90#ibcon#read 4, iclass 5, count 0 2006.257.18:46:30.90#ibcon#about to read 5, iclass 5, count 0 2006.257.18:46:30.90#ibcon#read 5, iclass 5, count 0 2006.257.18:46:30.90#ibcon#about to read 6, iclass 5, count 0 2006.257.18:46:30.90#ibcon#read 6, iclass 5, count 0 2006.257.18:46:30.90#ibcon#end of sib2, iclass 5, count 0 2006.257.18:46:30.90#ibcon#*after write, iclass 5, count 0 2006.257.18:46:30.90#ibcon#*before return 0, iclass 5, count 0 2006.257.18:46:30.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:30.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.18:46:30.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:46:30.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:46:30.90$vck44/vbbw=wide 2006.257.18:46:30.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.18:46:30.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.18:46:30.90#ibcon#ireg 8 cls_cnt 0 2006.257.18:46:30.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:46:30.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:46:30.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:46:30.97#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:46:30.97#ibcon#first serial, iclass 7, count 0 2006.257.18:46:30.97#ibcon#enter sib2, iclass 7, count 0 2006.257.18:46:30.97#ibcon#flushed, iclass 7, count 0 2006.257.18:46:30.97#ibcon#about to write, iclass 7, count 0 2006.257.18:46:30.97#ibcon#wrote, iclass 7, count 0 2006.257.18:46:30.97#ibcon#about to read 3, iclass 7, count 0 2006.257.18:46:30.99#ibcon#read 3, iclass 7, count 0 2006.257.18:46:30.99#ibcon#about to read 4, iclass 7, count 0 2006.257.18:46:30.99#ibcon#read 4, iclass 7, count 0 2006.257.18:46:30.99#ibcon#about to read 5, iclass 7, count 0 2006.257.18:46:30.99#ibcon#read 5, iclass 7, count 0 2006.257.18:46:30.99#ibcon#about to read 6, iclass 7, count 0 2006.257.18:46:30.99#ibcon#read 6, iclass 7, count 0 2006.257.18:46:30.99#ibcon#end of sib2, iclass 7, count 0 2006.257.18:46:30.99#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:46:30.99#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:46:30.99#ibcon#[27=BW32\r\n] 2006.257.18:46:30.99#ibcon#*before write, iclass 7, count 0 2006.257.18:46:30.99#ibcon#enter sib2, iclass 7, count 0 2006.257.18:46:30.99#ibcon#flushed, iclass 7, count 0 2006.257.18:46:30.99#ibcon#about to write, iclass 7, count 0 2006.257.18:46:30.99#ibcon#wrote, iclass 7, count 0 2006.257.18:46:30.99#ibcon#about to read 3, iclass 7, count 0 2006.257.18:46:31.02#ibcon#read 3, iclass 7, count 0 2006.257.18:46:31.02#ibcon#about to read 4, iclass 7, count 0 2006.257.18:46:31.02#ibcon#read 4, iclass 7, count 0 2006.257.18:46:31.02#ibcon#about to read 5, iclass 7, count 0 2006.257.18:46:31.02#ibcon#read 5, iclass 7, count 0 2006.257.18:46:31.02#ibcon#about to read 6, iclass 7, count 0 2006.257.18:46:31.02#ibcon#read 6, iclass 7, count 0 2006.257.18:46:31.02#ibcon#end of sib2, iclass 7, count 0 2006.257.18:46:31.02#ibcon#*after write, iclass 7, count 0 2006.257.18:46:31.02#ibcon#*before return 0, iclass 7, count 0 2006.257.18:46:31.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:46:31.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:46:31.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:46:31.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:46:31.02$setupk4/ifdk4 2006.257.18:46:31.02$ifdk4/lo= 2006.257.18:46:31.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:46:31.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:46:31.02$ifdk4/patch= 2006.257.18:46:31.02$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:46:31.02$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:46:31.02$setupk4/!*+20s 2006.257.18:46:37.73#abcon#<5=/15 1.1 2.4 17.29 971014.2\r\n> 2006.257.18:46:37.75#abcon#{5=INTERFACE CLEAR} 2006.257.18:46:37.81#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:46:45.53$setupk4/"tpicd 2006.257.18:46:45.53$setupk4/echo=off 2006.257.18:46:45.53$setupk4/xlog=off 2006.257.18:46:45.53:!2006.257.18:48:43 2006.257.18:46:46.14#trakl#Source acquired 2006.257.18:46:48.14#flagr#flagr/antenna,acquired 2006.257.18:48:43.00:preob 2006.257.18:48:43.14/onsource/TRACKING 2006.257.18:48:43.14:!2006.257.18:48:53 2006.257.18:48:53.00:"tape 2006.257.18:48:53.00:"st=record 2006.257.18:48:53.00:data_valid=on 2006.257.18:48:53.00:midob 2006.257.18:48:54.14/onsource/TRACKING 2006.257.18:48:54.14/wx/17.30,1014.3,97 2006.257.18:48:54.28/cable/+6.4846E-03 2006.257.18:48:55.37/va/01,08,usb,yes,33,35 2006.257.18:48:55.37/va/02,07,usb,yes,35,36 2006.257.18:48:55.37/va/03,08,usb,yes,32,34 2006.257.18:48:55.37/va/04,07,usb,yes,36,38 2006.257.18:48:55.37/va/05,04,usb,yes,33,33 2006.257.18:48:55.37/va/06,04,usb,yes,36,36 2006.257.18:48:55.37/va/07,04,usb,yes,37,37 2006.257.18:48:55.37/va/08,04,usb,yes,31,38 2006.257.18:48:55.60/valo/01,524.99,yes,locked 2006.257.18:48:55.60/valo/02,534.99,yes,locked 2006.257.18:48:55.60/valo/03,564.99,yes,locked 2006.257.18:48:55.60/valo/04,624.99,yes,locked 2006.257.18:48:55.60/valo/05,734.99,yes,locked 2006.257.18:48:55.60/valo/06,814.99,yes,locked 2006.257.18:48:55.60/valo/07,864.99,yes,locked 2006.257.18:48:55.60/valo/08,884.99,yes,locked 2006.257.18:48:56.69/vb/01,04,usb,yes,31,29 2006.257.18:48:56.69/vb/02,05,usb,yes,29,29 2006.257.18:48:56.69/vb/03,04,usb,yes,30,33 2006.257.18:48:56.69/vb/04,05,usb,yes,31,29 2006.257.18:48:56.69/vb/05,04,usb,yes,27,29 2006.257.18:48:56.69/vb/06,04,usb,yes,32,28 2006.257.18:48:56.69/vb/07,04,usb,yes,31,31 2006.257.18:48:56.69/vb/08,04,usb,yes,29,32 2006.257.18:48:56.93/vblo/01,629.99,yes,locked 2006.257.18:48:56.93/vblo/02,634.99,yes,locked 2006.257.18:48:56.93/vblo/03,649.99,yes,locked 2006.257.18:48:56.93/vblo/04,679.99,yes,locked 2006.257.18:48:56.93/vblo/05,709.99,yes,locked 2006.257.18:48:56.93/vblo/06,719.99,yes,locked 2006.257.18:48:56.93/vblo/07,734.99,yes,locked 2006.257.18:48:56.93/vblo/08,744.99,yes,locked 2006.257.18:48:57.08/vabw/8 2006.257.18:48:57.23/vbbw/8 2006.257.18:48:57.32/xfe/off,on,15.0 2006.257.18:48:57.69/ifatt/23,28,28,28 2006.257.18:48:58.07/fmout-gps/S +4.53E-07 2006.257.18:48:58.11:!2006.257.18:52:33 2006.257.18:52:33.01:data_valid=off 2006.257.18:52:33.01:"et 2006.257.18:52:33.01:!+3s 2006.257.18:52:36.02:"tape 2006.257.18:52:36.02:postob 2006.257.18:52:36.11/cable/+6.4845E-03 2006.257.18:52:36.11/wx/17.33,1014.3,97 2006.257.18:52:36.17/fmout-gps/S +4.54E-07 2006.257.18:52:36.17:scan_name=257-1856,jd0609,100 2006.257.18:52:36.17:source=0528+134,053056.42,133155.1,2000.0,cw 2006.257.18:52:38.13#flagr#flagr/antenna,new-source 2006.257.18:52:38.13:checkk5 2006.257.18:52:38.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:52:38.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:52:39.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:52:39.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:52:39.84/chk_obsdata//k5ts1/T2571848??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.18:52:40.16/chk_obsdata//k5ts2/T2571848??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.18:52:40.50/chk_obsdata//k5ts3/T2571848??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.18:52:40.83/chk_obsdata//k5ts4/T2571848??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.257.18:52:41.49/k5log//k5ts1_log_newline 2006.257.18:52:42.14/k5log//k5ts2_log_newline 2006.257.18:52:42.80/k5log//k5ts3_log_newline 2006.257.18:52:43.46/k5log//k5ts4_log_newline 2006.257.18:52:43.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:52:43.48:setupk4=1 2006.257.18:52:43.48$setupk4/echo=on 2006.257.18:52:43.48$setupk4/pcalon 2006.257.18:52:43.48$pcalon/"no phase cal control is implemented here 2006.257.18:52:43.48$setupk4/"tpicd=stop 2006.257.18:52:43.48$setupk4/"rec=synch_on 2006.257.18:52:43.48$setupk4/"rec_mode=128 2006.257.18:52:43.48$setupk4/!* 2006.257.18:52:43.48$setupk4/recpk4 2006.257.18:52:43.48$recpk4/recpatch= 2006.257.18:52:43.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:52:43.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:52:43.49$setupk4/vck44 2006.257.18:52:43.49$vck44/valo=1,524.99 2006.257.18:52:43.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.18:52:43.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.18:52:43.49#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:43.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:43.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:43.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:43.49#ibcon#enter wrdev, iclass 14, count 0 2006.257.18:52:43.49#ibcon#first serial, iclass 14, count 0 2006.257.18:52:43.49#ibcon#enter sib2, iclass 14, count 0 2006.257.18:52:43.49#ibcon#flushed, iclass 14, count 0 2006.257.18:52:43.49#ibcon#about to write, iclass 14, count 0 2006.257.18:52:43.49#ibcon#wrote, iclass 14, count 0 2006.257.18:52:43.49#ibcon#about to read 3, iclass 14, count 0 2006.257.18:52:43.51#ibcon#read 3, iclass 14, count 0 2006.257.18:52:43.51#ibcon#about to read 4, iclass 14, count 0 2006.257.18:52:43.51#ibcon#read 4, iclass 14, count 0 2006.257.18:52:43.51#ibcon#about to read 5, iclass 14, count 0 2006.257.18:52:43.51#ibcon#read 5, iclass 14, count 0 2006.257.18:52:43.51#ibcon#about to read 6, iclass 14, count 0 2006.257.18:52:43.51#ibcon#read 6, iclass 14, count 0 2006.257.18:52:43.51#ibcon#end of sib2, iclass 14, count 0 2006.257.18:52:43.51#ibcon#*mode == 0, iclass 14, count 0 2006.257.18:52:43.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.18:52:43.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:52:43.51#ibcon#*before write, iclass 14, count 0 2006.257.18:52:43.51#ibcon#enter sib2, iclass 14, count 0 2006.257.18:52:43.51#ibcon#flushed, iclass 14, count 0 2006.257.18:52:43.51#ibcon#about to write, iclass 14, count 0 2006.257.18:52:43.51#ibcon#wrote, iclass 14, count 0 2006.257.18:52:43.51#ibcon#about to read 3, iclass 14, count 0 2006.257.18:52:43.56#ibcon#read 3, iclass 14, count 0 2006.257.18:52:43.56#ibcon#about to read 4, iclass 14, count 0 2006.257.18:52:43.56#ibcon#read 4, iclass 14, count 0 2006.257.18:52:43.56#ibcon#about to read 5, iclass 14, count 0 2006.257.18:52:43.56#ibcon#read 5, iclass 14, count 0 2006.257.18:52:43.56#ibcon#about to read 6, iclass 14, count 0 2006.257.18:52:43.56#ibcon#read 6, iclass 14, count 0 2006.257.18:52:43.56#ibcon#end of sib2, iclass 14, count 0 2006.257.18:52:43.56#ibcon#*after write, iclass 14, count 0 2006.257.18:52:43.56#ibcon#*before return 0, iclass 14, count 0 2006.257.18:52:43.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:43.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:43.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.18:52:43.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.18:52:43.56$vck44/va=1,8 2006.257.18:52:43.56#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.18:52:43.56#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.18:52:43.56#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:43.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:43.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:43.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:43.56#ibcon#enter wrdev, iclass 16, count 2 2006.257.18:52:43.56#ibcon#first serial, iclass 16, count 2 2006.257.18:52:43.56#ibcon#enter sib2, iclass 16, count 2 2006.257.18:52:43.56#ibcon#flushed, iclass 16, count 2 2006.257.18:52:43.56#ibcon#about to write, iclass 16, count 2 2006.257.18:52:43.56#ibcon#wrote, iclass 16, count 2 2006.257.18:52:43.56#ibcon#about to read 3, iclass 16, count 2 2006.257.18:52:43.58#ibcon#read 3, iclass 16, count 2 2006.257.18:52:43.58#ibcon#about to read 4, iclass 16, count 2 2006.257.18:52:43.58#ibcon#read 4, iclass 16, count 2 2006.257.18:52:43.58#ibcon#about to read 5, iclass 16, count 2 2006.257.18:52:43.58#ibcon#read 5, iclass 16, count 2 2006.257.18:52:43.58#ibcon#about to read 6, iclass 16, count 2 2006.257.18:52:43.58#ibcon#read 6, iclass 16, count 2 2006.257.18:52:43.58#ibcon#end of sib2, iclass 16, count 2 2006.257.18:52:43.58#ibcon#*mode == 0, iclass 16, count 2 2006.257.18:52:43.58#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.18:52:43.58#ibcon#[25=AT01-08\r\n] 2006.257.18:52:43.58#ibcon#*before write, iclass 16, count 2 2006.257.18:52:43.58#ibcon#enter sib2, iclass 16, count 2 2006.257.18:52:43.58#ibcon#flushed, iclass 16, count 2 2006.257.18:52:43.58#ibcon#about to write, iclass 16, count 2 2006.257.18:52:43.58#ibcon#wrote, iclass 16, count 2 2006.257.18:52:43.58#ibcon#about to read 3, iclass 16, count 2 2006.257.18:52:43.61#ibcon#read 3, iclass 16, count 2 2006.257.18:52:43.61#ibcon#about to read 4, iclass 16, count 2 2006.257.18:52:43.61#ibcon#read 4, iclass 16, count 2 2006.257.18:52:43.61#ibcon#about to read 5, iclass 16, count 2 2006.257.18:52:43.61#ibcon#read 5, iclass 16, count 2 2006.257.18:52:43.61#ibcon#about to read 6, iclass 16, count 2 2006.257.18:52:43.61#ibcon#read 6, iclass 16, count 2 2006.257.18:52:43.61#ibcon#end of sib2, iclass 16, count 2 2006.257.18:52:43.61#ibcon#*after write, iclass 16, count 2 2006.257.18:52:43.61#ibcon#*before return 0, iclass 16, count 2 2006.257.18:52:43.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:43.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:43.61#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.18:52:43.61#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:43.61#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:43.73#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:43.73#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:43.73#ibcon#enter wrdev, iclass 16, count 0 2006.257.18:52:43.73#ibcon#first serial, iclass 16, count 0 2006.257.18:52:43.73#ibcon#enter sib2, iclass 16, count 0 2006.257.18:52:43.73#ibcon#flushed, iclass 16, count 0 2006.257.18:52:43.73#ibcon#about to write, iclass 16, count 0 2006.257.18:52:43.73#ibcon#wrote, iclass 16, count 0 2006.257.18:52:43.73#ibcon#about to read 3, iclass 16, count 0 2006.257.18:52:43.75#ibcon#read 3, iclass 16, count 0 2006.257.18:52:43.75#ibcon#about to read 4, iclass 16, count 0 2006.257.18:52:43.75#ibcon#read 4, iclass 16, count 0 2006.257.18:52:43.75#ibcon#about to read 5, iclass 16, count 0 2006.257.18:52:43.75#ibcon#read 5, iclass 16, count 0 2006.257.18:52:43.75#ibcon#about to read 6, iclass 16, count 0 2006.257.18:52:43.75#ibcon#read 6, iclass 16, count 0 2006.257.18:52:43.75#ibcon#end of sib2, iclass 16, count 0 2006.257.18:52:43.75#ibcon#*mode == 0, iclass 16, count 0 2006.257.18:52:43.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.18:52:43.75#ibcon#[25=USB\r\n] 2006.257.18:52:43.75#ibcon#*before write, iclass 16, count 0 2006.257.18:52:43.75#ibcon#enter sib2, iclass 16, count 0 2006.257.18:52:43.75#ibcon#flushed, iclass 16, count 0 2006.257.18:52:43.75#ibcon#about to write, iclass 16, count 0 2006.257.18:52:43.75#ibcon#wrote, iclass 16, count 0 2006.257.18:52:43.75#ibcon#about to read 3, iclass 16, count 0 2006.257.18:52:43.78#ibcon#read 3, iclass 16, count 0 2006.257.18:52:43.78#ibcon#about to read 4, iclass 16, count 0 2006.257.18:52:43.78#ibcon#read 4, iclass 16, count 0 2006.257.18:52:43.78#ibcon#about to read 5, iclass 16, count 0 2006.257.18:52:43.78#ibcon#read 5, iclass 16, count 0 2006.257.18:52:43.78#ibcon#about to read 6, iclass 16, count 0 2006.257.18:52:43.78#ibcon#read 6, iclass 16, count 0 2006.257.18:52:43.78#ibcon#end of sib2, iclass 16, count 0 2006.257.18:52:43.78#ibcon#*after write, iclass 16, count 0 2006.257.18:52:43.78#ibcon#*before return 0, iclass 16, count 0 2006.257.18:52:43.78#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:43.78#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:43.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.18:52:43.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.18:52:43.78$vck44/valo=2,534.99 2006.257.18:52:43.78#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.18:52:43.78#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.18:52:43.78#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:43.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:43.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:43.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:43.78#ibcon#enter wrdev, iclass 18, count 0 2006.257.18:52:43.78#ibcon#first serial, iclass 18, count 0 2006.257.18:52:43.78#ibcon#enter sib2, iclass 18, count 0 2006.257.18:52:43.78#ibcon#flushed, iclass 18, count 0 2006.257.18:52:43.78#ibcon#about to write, iclass 18, count 0 2006.257.18:52:43.78#ibcon#wrote, iclass 18, count 0 2006.257.18:52:43.78#ibcon#about to read 3, iclass 18, count 0 2006.257.18:52:43.80#ibcon#read 3, iclass 18, count 0 2006.257.18:52:43.80#ibcon#about to read 4, iclass 18, count 0 2006.257.18:52:43.80#ibcon#read 4, iclass 18, count 0 2006.257.18:52:43.80#ibcon#about to read 5, iclass 18, count 0 2006.257.18:52:43.80#ibcon#read 5, iclass 18, count 0 2006.257.18:52:43.80#ibcon#about to read 6, iclass 18, count 0 2006.257.18:52:43.80#ibcon#read 6, iclass 18, count 0 2006.257.18:52:43.80#ibcon#end of sib2, iclass 18, count 0 2006.257.18:52:43.80#ibcon#*mode == 0, iclass 18, count 0 2006.257.18:52:43.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.18:52:43.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:52:43.80#ibcon#*before write, iclass 18, count 0 2006.257.18:52:43.80#ibcon#enter sib2, iclass 18, count 0 2006.257.18:52:43.80#ibcon#flushed, iclass 18, count 0 2006.257.18:52:43.80#ibcon#about to write, iclass 18, count 0 2006.257.18:52:43.80#ibcon#wrote, iclass 18, count 0 2006.257.18:52:43.80#ibcon#about to read 3, iclass 18, count 0 2006.257.18:52:43.84#ibcon#read 3, iclass 18, count 0 2006.257.18:52:43.84#ibcon#about to read 4, iclass 18, count 0 2006.257.18:52:43.84#ibcon#read 4, iclass 18, count 0 2006.257.18:52:43.84#ibcon#about to read 5, iclass 18, count 0 2006.257.18:52:43.84#ibcon#read 5, iclass 18, count 0 2006.257.18:52:43.84#ibcon#about to read 6, iclass 18, count 0 2006.257.18:52:43.84#ibcon#read 6, iclass 18, count 0 2006.257.18:52:43.84#ibcon#end of sib2, iclass 18, count 0 2006.257.18:52:43.84#ibcon#*after write, iclass 18, count 0 2006.257.18:52:43.84#ibcon#*before return 0, iclass 18, count 0 2006.257.18:52:43.84#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:43.84#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:43.84#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.18:52:43.84#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.18:52:43.84$vck44/va=2,7 2006.257.18:52:43.84#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.18:52:43.84#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.18:52:43.84#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:43.84#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:43.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:43.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:43.90#ibcon#enter wrdev, iclass 20, count 2 2006.257.18:52:43.90#ibcon#first serial, iclass 20, count 2 2006.257.18:52:43.90#ibcon#enter sib2, iclass 20, count 2 2006.257.18:52:43.90#ibcon#flushed, iclass 20, count 2 2006.257.18:52:43.90#ibcon#about to write, iclass 20, count 2 2006.257.18:52:43.90#ibcon#wrote, iclass 20, count 2 2006.257.18:52:43.90#ibcon#about to read 3, iclass 20, count 2 2006.257.18:52:43.92#ibcon#read 3, iclass 20, count 2 2006.257.18:52:43.92#ibcon#about to read 4, iclass 20, count 2 2006.257.18:52:43.92#ibcon#read 4, iclass 20, count 2 2006.257.18:52:43.92#ibcon#about to read 5, iclass 20, count 2 2006.257.18:52:43.92#ibcon#read 5, iclass 20, count 2 2006.257.18:52:43.92#ibcon#about to read 6, iclass 20, count 2 2006.257.18:52:43.92#ibcon#read 6, iclass 20, count 2 2006.257.18:52:43.92#ibcon#end of sib2, iclass 20, count 2 2006.257.18:52:43.92#ibcon#*mode == 0, iclass 20, count 2 2006.257.18:52:43.92#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.18:52:43.92#ibcon#[25=AT02-07\r\n] 2006.257.18:52:43.92#ibcon#*before write, iclass 20, count 2 2006.257.18:52:43.92#ibcon#enter sib2, iclass 20, count 2 2006.257.18:52:43.92#ibcon#flushed, iclass 20, count 2 2006.257.18:52:43.92#ibcon#about to write, iclass 20, count 2 2006.257.18:52:43.92#ibcon#wrote, iclass 20, count 2 2006.257.18:52:43.92#ibcon#about to read 3, iclass 20, count 2 2006.257.18:52:43.95#ibcon#read 3, iclass 20, count 2 2006.257.18:52:43.95#ibcon#about to read 4, iclass 20, count 2 2006.257.18:52:43.95#ibcon#read 4, iclass 20, count 2 2006.257.18:52:43.95#ibcon#about to read 5, iclass 20, count 2 2006.257.18:52:43.95#ibcon#read 5, iclass 20, count 2 2006.257.18:52:43.95#ibcon#about to read 6, iclass 20, count 2 2006.257.18:52:43.95#ibcon#read 6, iclass 20, count 2 2006.257.18:52:43.95#ibcon#end of sib2, iclass 20, count 2 2006.257.18:52:43.95#ibcon#*after write, iclass 20, count 2 2006.257.18:52:43.95#ibcon#*before return 0, iclass 20, count 2 2006.257.18:52:43.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:43.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:43.95#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.18:52:43.95#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:43.95#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:44.06#abcon#<5=/14 1.5 3.7 17.33 971014.3\r\n> 2006.257.18:52:44.07#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:44.07#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:44.07#ibcon#enter wrdev, iclass 20, count 0 2006.257.18:52:44.07#ibcon#first serial, iclass 20, count 0 2006.257.18:52:44.07#ibcon#enter sib2, iclass 20, count 0 2006.257.18:52:44.07#ibcon#flushed, iclass 20, count 0 2006.257.18:52:44.07#ibcon#about to write, iclass 20, count 0 2006.257.18:52:44.07#ibcon#wrote, iclass 20, count 0 2006.257.18:52:44.07#ibcon#about to read 3, iclass 20, count 0 2006.257.18:52:44.08#abcon#{5=INTERFACE CLEAR} 2006.257.18:52:44.09#ibcon#read 3, iclass 20, count 0 2006.257.18:52:44.09#ibcon#about to read 4, iclass 20, count 0 2006.257.18:52:44.09#ibcon#read 4, iclass 20, count 0 2006.257.18:52:44.09#ibcon#about to read 5, iclass 20, count 0 2006.257.18:52:44.09#ibcon#read 5, iclass 20, count 0 2006.257.18:52:44.09#ibcon#about to read 6, iclass 20, count 0 2006.257.18:52:44.09#ibcon#read 6, iclass 20, count 0 2006.257.18:52:44.09#ibcon#end of sib2, iclass 20, count 0 2006.257.18:52:44.09#ibcon#*mode == 0, iclass 20, count 0 2006.257.18:52:44.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.18:52:44.09#ibcon#[25=USB\r\n] 2006.257.18:52:44.09#ibcon#*before write, iclass 20, count 0 2006.257.18:52:44.09#ibcon#enter sib2, iclass 20, count 0 2006.257.18:52:44.09#ibcon#flushed, iclass 20, count 0 2006.257.18:52:44.09#ibcon#about to write, iclass 20, count 0 2006.257.18:52:44.09#ibcon#wrote, iclass 20, count 0 2006.257.18:52:44.09#ibcon#about to read 3, iclass 20, count 0 2006.257.18:52:44.12#ibcon#read 3, iclass 20, count 0 2006.257.18:52:44.12#ibcon#about to read 4, iclass 20, count 0 2006.257.18:52:44.12#ibcon#read 4, iclass 20, count 0 2006.257.18:52:44.12#ibcon#about to read 5, iclass 20, count 0 2006.257.18:52:44.12#ibcon#read 5, iclass 20, count 0 2006.257.18:52:44.12#ibcon#about to read 6, iclass 20, count 0 2006.257.18:52:44.12#ibcon#read 6, iclass 20, count 0 2006.257.18:52:44.12#ibcon#end of sib2, iclass 20, count 0 2006.257.18:52:44.12#ibcon#*after write, iclass 20, count 0 2006.257.18:52:44.12#ibcon#*before return 0, iclass 20, count 0 2006.257.18:52:44.12#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:44.12#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:44.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.18:52:44.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.18:52:44.12$vck44/valo=3,564.99 2006.257.18:52:44.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.18:52:44.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.18:52:44.12#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:44.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:44.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:44.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:44.12#ibcon#enter wrdev, iclass 26, count 0 2006.257.18:52:44.12#ibcon#first serial, iclass 26, count 0 2006.257.18:52:44.12#ibcon#enter sib2, iclass 26, count 0 2006.257.18:52:44.12#ibcon#flushed, iclass 26, count 0 2006.257.18:52:44.12#ibcon#about to write, iclass 26, count 0 2006.257.18:52:44.12#ibcon#wrote, iclass 26, count 0 2006.257.18:52:44.12#ibcon#about to read 3, iclass 26, count 0 2006.257.18:52:44.14#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:52:44.14#ibcon#read 3, iclass 26, count 0 2006.257.18:52:44.14#ibcon#about to read 4, iclass 26, count 0 2006.257.18:52:44.14#ibcon#read 4, iclass 26, count 0 2006.257.18:52:44.14#ibcon#about to read 5, iclass 26, count 0 2006.257.18:52:44.14#ibcon#read 5, iclass 26, count 0 2006.257.18:52:44.14#ibcon#about to read 6, iclass 26, count 0 2006.257.18:52:44.14#ibcon#read 6, iclass 26, count 0 2006.257.18:52:44.14#ibcon#end of sib2, iclass 26, count 0 2006.257.18:52:44.14#ibcon#*mode == 0, iclass 26, count 0 2006.257.18:52:44.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.18:52:44.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:52:44.14#ibcon#*before write, iclass 26, count 0 2006.257.18:52:44.14#ibcon#enter sib2, iclass 26, count 0 2006.257.18:52:44.14#ibcon#flushed, iclass 26, count 0 2006.257.18:52:44.14#ibcon#about to write, iclass 26, count 0 2006.257.18:52:44.14#ibcon#wrote, iclass 26, count 0 2006.257.18:52:44.14#ibcon#about to read 3, iclass 26, count 0 2006.257.18:52:44.18#ibcon#read 3, iclass 26, count 0 2006.257.18:52:44.18#ibcon#about to read 4, iclass 26, count 0 2006.257.18:52:44.18#ibcon#read 4, iclass 26, count 0 2006.257.18:52:44.18#ibcon#about to read 5, iclass 26, count 0 2006.257.18:52:44.18#ibcon#read 5, iclass 26, count 0 2006.257.18:52:44.18#ibcon#about to read 6, iclass 26, count 0 2006.257.18:52:44.18#ibcon#read 6, iclass 26, count 0 2006.257.18:52:44.18#ibcon#end of sib2, iclass 26, count 0 2006.257.18:52:44.18#ibcon#*after write, iclass 26, count 0 2006.257.18:52:44.18#ibcon#*before return 0, iclass 26, count 0 2006.257.18:52:44.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:44.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:44.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.18:52:44.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.18:52:44.18$vck44/va=3,8 2006.257.18:52:44.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.18:52:44.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.18:52:44.18#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:44.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:44.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:44.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:44.24#ibcon#enter wrdev, iclass 28, count 2 2006.257.18:52:44.24#ibcon#first serial, iclass 28, count 2 2006.257.18:52:44.24#ibcon#enter sib2, iclass 28, count 2 2006.257.18:52:44.24#ibcon#flushed, iclass 28, count 2 2006.257.18:52:44.24#ibcon#about to write, iclass 28, count 2 2006.257.18:52:44.24#ibcon#wrote, iclass 28, count 2 2006.257.18:52:44.24#ibcon#about to read 3, iclass 28, count 2 2006.257.18:52:44.26#ibcon#read 3, iclass 28, count 2 2006.257.18:52:44.26#ibcon#about to read 4, iclass 28, count 2 2006.257.18:52:44.26#ibcon#read 4, iclass 28, count 2 2006.257.18:52:44.26#ibcon#about to read 5, iclass 28, count 2 2006.257.18:52:44.26#ibcon#read 5, iclass 28, count 2 2006.257.18:52:44.26#ibcon#about to read 6, iclass 28, count 2 2006.257.18:52:44.26#ibcon#read 6, iclass 28, count 2 2006.257.18:52:44.26#ibcon#end of sib2, iclass 28, count 2 2006.257.18:52:44.26#ibcon#*mode == 0, iclass 28, count 2 2006.257.18:52:44.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.18:52:44.26#ibcon#[25=AT03-08\r\n] 2006.257.18:52:44.26#ibcon#*before write, iclass 28, count 2 2006.257.18:52:44.26#ibcon#enter sib2, iclass 28, count 2 2006.257.18:52:44.26#ibcon#flushed, iclass 28, count 2 2006.257.18:52:44.26#ibcon#about to write, iclass 28, count 2 2006.257.18:52:44.26#ibcon#wrote, iclass 28, count 2 2006.257.18:52:44.26#ibcon#about to read 3, iclass 28, count 2 2006.257.18:52:44.29#ibcon#read 3, iclass 28, count 2 2006.257.18:52:44.29#ibcon#about to read 4, iclass 28, count 2 2006.257.18:52:44.29#ibcon#read 4, iclass 28, count 2 2006.257.18:52:44.29#ibcon#about to read 5, iclass 28, count 2 2006.257.18:52:44.29#ibcon#read 5, iclass 28, count 2 2006.257.18:52:44.29#ibcon#about to read 6, iclass 28, count 2 2006.257.18:52:44.29#ibcon#read 6, iclass 28, count 2 2006.257.18:52:44.29#ibcon#end of sib2, iclass 28, count 2 2006.257.18:52:44.29#ibcon#*after write, iclass 28, count 2 2006.257.18:52:44.29#ibcon#*before return 0, iclass 28, count 2 2006.257.18:52:44.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:44.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:44.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.18:52:44.29#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:44.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:44.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:44.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:44.41#ibcon#enter wrdev, iclass 28, count 0 2006.257.18:52:44.41#ibcon#first serial, iclass 28, count 0 2006.257.18:52:44.41#ibcon#enter sib2, iclass 28, count 0 2006.257.18:52:44.41#ibcon#flushed, iclass 28, count 0 2006.257.18:52:44.41#ibcon#about to write, iclass 28, count 0 2006.257.18:52:44.41#ibcon#wrote, iclass 28, count 0 2006.257.18:52:44.41#ibcon#about to read 3, iclass 28, count 0 2006.257.18:52:44.43#ibcon#read 3, iclass 28, count 0 2006.257.18:52:44.43#ibcon#about to read 4, iclass 28, count 0 2006.257.18:52:44.43#ibcon#read 4, iclass 28, count 0 2006.257.18:52:44.43#ibcon#about to read 5, iclass 28, count 0 2006.257.18:52:44.43#ibcon#read 5, iclass 28, count 0 2006.257.18:52:44.43#ibcon#about to read 6, iclass 28, count 0 2006.257.18:52:44.43#ibcon#read 6, iclass 28, count 0 2006.257.18:52:44.43#ibcon#end of sib2, iclass 28, count 0 2006.257.18:52:44.43#ibcon#*mode == 0, iclass 28, count 0 2006.257.18:52:44.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.18:52:44.43#ibcon#[25=USB\r\n] 2006.257.18:52:44.43#ibcon#*before write, iclass 28, count 0 2006.257.18:52:44.43#ibcon#enter sib2, iclass 28, count 0 2006.257.18:52:44.43#ibcon#flushed, iclass 28, count 0 2006.257.18:52:44.43#ibcon#about to write, iclass 28, count 0 2006.257.18:52:44.43#ibcon#wrote, iclass 28, count 0 2006.257.18:52:44.43#ibcon#about to read 3, iclass 28, count 0 2006.257.18:52:44.46#ibcon#read 3, iclass 28, count 0 2006.257.18:52:44.46#ibcon#about to read 4, iclass 28, count 0 2006.257.18:52:44.46#ibcon#read 4, iclass 28, count 0 2006.257.18:52:44.46#ibcon#about to read 5, iclass 28, count 0 2006.257.18:52:44.46#ibcon#read 5, iclass 28, count 0 2006.257.18:52:44.46#ibcon#about to read 6, iclass 28, count 0 2006.257.18:52:44.46#ibcon#read 6, iclass 28, count 0 2006.257.18:52:44.46#ibcon#end of sib2, iclass 28, count 0 2006.257.18:52:44.46#ibcon#*after write, iclass 28, count 0 2006.257.18:52:44.46#ibcon#*before return 0, iclass 28, count 0 2006.257.18:52:44.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:44.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:44.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.18:52:44.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.18:52:44.46$vck44/valo=4,624.99 2006.257.18:52:44.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.18:52:44.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.18:52:44.46#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:44.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:44.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:44.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:44.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.18:52:44.46#ibcon#first serial, iclass 30, count 0 2006.257.18:52:44.46#ibcon#enter sib2, iclass 30, count 0 2006.257.18:52:44.46#ibcon#flushed, iclass 30, count 0 2006.257.18:52:44.46#ibcon#about to write, iclass 30, count 0 2006.257.18:52:44.46#ibcon#wrote, iclass 30, count 0 2006.257.18:52:44.46#ibcon#about to read 3, iclass 30, count 0 2006.257.18:52:44.48#ibcon#read 3, iclass 30, count 0 2006.257.18:52:44.48#ibcon#about to read 4, iclass 30, count 0 2006.257.18:52:44.48#ibcon#read 4, iclass 30, count 0 2006.257.18:52:44.48#ibcon#about to read 5, iclass 30, count 0 2006.257.18:52:44.48#ibcon#read 5, iclass 30, count 0 2006.257.18:52:44.48#ibcon#about to read 6, iclass 30, count 0 2006.257.18:52:44.48#ibcon#read 6, iclass 30, count 0 2006.257.18:52:44.48#ibcon#end of sib2, iclass 30, count 0 2006.257.18:52:44.48#ibcon#*mode == 0, iclass 30, count 0 2006.257.18:52:44.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.18:52:44.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:52:44.48#ibcon#*before write, iclass 30, count 0 2006.257.18:52:44.48#ibcon#enter sib2, iclass 30, count 0 2006.257.18:52:44.48#ibcon#flushed, iclass 30, count 0 2006.257.18:52:44.48#ibcon#about to write, iclass 30, count 0 2006.257.18:52:44.48#ibcon#wrote, iclass 30, count 0 2006.257.18:52:44.48#ibcon#about to read 3, iclass 30, count 0 2006.257.18:52:44.52#ibcon#read 3, iclass 30, count 0 2006.257.18:52:44.52#ibcon#about to read 4, iclass 30, count 0 2006.257.18:52:44.52#ibcon#read 4, iclass 30, count 0 2006.257.18:52:44.52#ibcon#about to read 5, iclass 30, count 0 2006.257.18:52:44.52#ibcon#read 5, iclass 30, count 0 2006.257.18:52:44.52#ibcon#about to read 6, iclass 30, count 0 2006.257.18:52:44.52#ibcon#read 6, iclass 30, count 0 2006.257.18:52:44.52#ibcon#end of sib2, iclass 30, count 0 2006.257.18:52:44.52#ibcon#*after write, iclass 30, count 0 2006.257.18:52:44.52#ibcon#*before return 0, iclass 30, count 0 2006.257.18:52:44.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:44.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:44.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.18:52:44.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.18:52:44.52$vck44/va=4,7 2006.257.18:52:44.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.18:52:44.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.18:52:44.52#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:44.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:44.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:44.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:44.58#ibcon#enter wrdev, iclass 32, count 2 2006.257.18:52:44.58#ibcon#first serial, iclass 32, count 2 2006.257.18:52:44.58#ibcon#enter sib2, iclass 32, count 2 2006.257.18:52:44.58#ibcon#flushed, iclass 32, count 2 2006.257.18:52:44.58#ibcon#about to write, iclass 32, count 2 2006.257.18:52:44.58#ibcon#wrote, iclass 32, count 2 2006.257.18:52:44.58#ibcon#about to read 3, iclass 32, count 2 2006.257.18:52:44.60#ibcon#read 3, iclass 32, count 2 2006.257.18:52:44.60#ibcon#about to read 4, iclass 32, count 2 2006.257.18:52:44.60#ibcon#read 4, iclass 32, count 2 2006.257.18:52:44.60#ibcon#about to read 5, iclass 32, count 2 2006.257.18:52:44.60#ibcon#read 5, iclass 32, count 2 2006.257.18:52:44.60#ibcon#about to read 6, iclass 32, count 2 2006.257.18:52:44.60#ibcon#read 6, iclass 32, count 2 2006.257.18:52:44.60#ibcon#end of sib2, iclass 32, count 2 2006.257.18:52:44.60#ibcon#*mode == 0, iclass 32, count 2 2006.257.18:52:44.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.18:52:44.60#ibcon#[25=AT04-07\r\n] 2006.257.18:52:44.60#ibcon#*before write, iclass 32, count 2 2006.257.18:52:44.60#ibcon#enter sib2, iclass 32, count 2 2006.257.18:52:44.60#ibcon#flushed, iclass 32, count 2 2006.257.18:52:44.60#ibcon#about to write, iclass 32, count 2 2006.257.18:52:44.60#ibcon#wrote, iclass 32, count 2 2006.257.18:52:44.60#ibcon#about to read 3, iclass 32, count 2 2006.257.18:52:44.63#ibcon#read 3, iclass 32, count 2 2006.257.18:52:44.63#ibcon#about to read 4, iclass 32, count 2 2006.257.18:52:44.63#ibcon#read 4, iclass 32, count 2 2006.257.18:52:44.63#ibcon#about to read 5, iclass 32, count 2 2006.257.18:52:44.63#ibcon#read 5, iclass 32, count 2 2006.257.18:52:44.63#ibcon#about to read 6, iclass 32, count 2 2006.257.18:52:44.63#ibcon#read 6, iclass 32, count 2 2006.257.18:52:44.63#ibcon#end of sib2, iclass 32, count 2 2006.257.18:52:44.63#ibcon#*after write, iclass 32, count 2 2006.257.18:52:44.63#ibcon#*before return 0, iclass 32, count 2 2006.257.18:52:44.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:44.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:44.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.18:52:44.63#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:44.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:44.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:44.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:44.75#ibcon#enter wrdev, iclass 32, count 0 2006.257.18:52:44.75#ibcon#first serial, iclass 32, count 0 2006.257.18:52:44.75#ibcon#enter sib2, iclass 32, count 0 2006.257.18:52:44.75#ibcon#flushed, iclass 32, count 0 2006.257.18:52:44.75#ibcon#about to write, iclass 32, count 0 2006.257.18:52:44.75#ibcon#wrote, iclass 32, count 0 2006.257.18:52:44.75#ibcon#about to read 3, iclass 32, count 0 2006.257.18:52:44.77#ibcon#read 3, iclass 32, count 0 2006.257.18:52:44.77#ibcon#about to read 4, iclass 32, count 0 2006.257.18:52:44.77#ibcon#read 4, iclass 32, count 0 2006.257.18:52:44.77#ibcon#about to read 5, iclass 32, count 0 2006.257.18:52:44.77#ibcon#read 5, iclass 32, count 0 2006.257.18:52:44.77#ibcon#about to read 6, iclass 32, count 0 2006.257.18:52:44.77#ibcon#read 6, iclass 32, count 0 2006.257.18:52:44.77#ibcon#end of sib2, iclass 32, count 0 2006.257.18:52:44.77#ibcon#*mode == 0, iclass 32, count 0 2006.257.18:52:44.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.18:52:44.77#ibcon#[25=USB\r\n] 2006.257.18:52:44.77#ibcon#*before write, iclass 32, count 0 2006.257.18:52:44.77#ibcon#enter sib2, iclass 32, count 0 2006.257.18:52:44.77#ibcon#flushed, iclass 32, count 0 2006.257.18:52:44.77#ibcon#about to write, iclass 32, count 0 2006.257.18:52:44.77#ibcon#wrote, iclass 32, count 0 2006.257.18:52:44.77#ibcon#about to read 3, iclass 32, count 0 2006.257.18:52:44.80#ibcon#read 3, iclass 32, count 0 2006.257.18:52:44.80#ibcon#about to read 4, iclass 32, count 0 2006.257.18:52:44.80#ibcon#read 4, iclass 32, count 0 2006.257.18:52:44.80#ibcon#about to read 5, iclass 32, count 0 2006.257.18:52:44.80#ibcon#read 5, iclass 32, count 0 2006.257.18:52:44.80#ibcon#about to read 6, iclass 32, count 0 2006.257.18:52:44.80#ibcon#read 6, iclass 32, count 0 2006.257.18:52:44.80#ibcon#end of sib2, iclass 32, count 0 2006.257.18:52:44.80#ibcon#*after write, iclass 32, count 0 2006.257.18:52:44.80#ibcon#*before return 0, iclass 32, count 0 2006.257.18:52:44.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:44.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:44.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.18:52:44.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.18:52:44.80$vck44/valo=5,734.99 2006.257.18:52:44.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.18:52:44.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.18:52:44.80#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:44.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:44.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:44.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:44.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.18:52:44.80#ibcon#first serial, iclass 34, count 0 2006.257.18:52:44.80#ibcon#enter sib2, iclass 34, count 0 2006.257.18:52:44.80#ibcon#flushed, iclass 34, count 0 2006.257.18:52:44.80#ibcon#about to write, iclass 34, count 0 2006.257.18:52:44.80#ibcon#wrote, iclass 34, count 0 2006.257.18:52:44.80#ibcon#about to read 3, iclass 34, count 0 2006.257.18:52:44.82#ibcon#read 3, iclass 34, count 0 2006.257.18:52:44.82#ibcon#about to read 4, iclass 34, count 0 2006.257.18:52:44.82#ibcon#read 4, iclass 34, count 0 2006.257.18:52:44.82#ibcon#about to read 5, iclass 34, count 0 2006.257.18:52:44.82#ibcon#read 5, iclass 34, count 0 2006.257.18:52:44.82#ibcon#about to read 6, iclass 34, count 0 2006.257.18:52:44.82#ibcon#read 6, iclass 34, count 0 2006.257.18:52:44.82#ibcon#end of sib2, iclass 34, count 0 2006.257.18:52:44.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.18:52:44.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.18:52:44.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:52:44.82#ibcon#*before write, iclass 34, count 0 2006.257.18:52:44.82#ibcon#enter sib2, iclass 34, count 0 2006.257.18:52:44.82#ibcon#flushed, iclass 34, count 0 2006.257.18:52:44.82#ibcon#about to write, iclass 34, count 0 2006.257.18:52:44.82#ibcon#wrote, iclass 34, count 0 2006.257.18:52:44.82#ibcon#about to read 3, iclass 34, count 0 2006.257.18:52:44.86#ibcon#read 3, iclass 34, count 0 2006.257.18:52:44.86#ibcon#about to read 4, iclass 34, count 0 2006.257.18:52:44.86#ibcon#read 4, iclass 34, count 0 2006.257.18:52:44.86#ibcon#about to read 5, iclass 34, count 0 2006.257.18:52:44.86#ibcon#read 5, iclass 34, count 0 2006.257.18:52:44.86#ibcon#about to read 6, iclass 34, count 0 2006.257.18:52:44.86#ibcon#read 6, iclass 34, count 0 2006.257.18:52:44.86#ibcon#end of sib2, iclass 34, count 0 2006.257.18:52:44.86#ibcon#*after write, iclass 34, count 0 2006.257.18:52:44.86#ibcon#*before return 0, iclass 34, count 0 2006.257.18:52:44.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:44.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:44.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.18:52:44.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.18:52:44.86$vck44/va=5,4 2006.257.18:52:44.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.18:52:44.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.18:52:44.86#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:44.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:44.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:44.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:44.92#ibcon#enter wrdev, iclass 36, count 2 2006.257.18:52:44.92#ibcon#first serial, iclass 36, count 2 2006.257.18:52:44.92#ibcon#enter sib2, iclass 36, count 2 2006.257.18:52:44.92#ibcon#flushed, iclass 36, count 2 2006.257.18:52:44.92#ibcon#about to write, iclass 36, count 2 2006.257.18:52:44.92#ibcon#wrote, iclass 36, count 2 2006.257.18:52:44.92#ibcon#about to read 3, iclass 36, count 2 2006.257.18:52:44.94#ibcon#read 3, iclass 36, count 2 2006.257.18:52:44.94#ibcon#about to read 4, iclass 36, count 2 2006.257.18:52:44.94#ibcon#read 4, iclass 36, count 2 2006.257.18:52:44.94#ibcon#about to read 5, iclass 36, count 2 2006.257.18:52:44.94#ibcon#read 5, iclass 36, count 2 2006.257.18:52:44.94#ibcon#about to read 6, iclass 36, count 2 2006.257.18:52:44.94#ibcon#read 6, iclass 36, count 2 2006.257.18:52:44.94#ibcon#end of sib2, iclass 36, count 2 2006.257.18:52:44.94#ibcon#*mode == 0, iclass 36, count 2 2006.257.18:52:44.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.18:52:44.94#ibcon#[25=AT05-04\r\n] 2006.257.18:52:44.94#ibcon#*before write, iclass 36, count 2 2006.257.18:52:44.94#ibcon#enter sib2, iclass 36, count 2 2006.257.18:52:44.94#ibcon#flushed, iclass 36, count 2 2006.257.18:52:44.94#ibcon#about to write, iclass 36, count 2 2006.257.18:52:44.94#ibcon#wrote, iclass 36, count 2 2006.257.18:52:44.94#ibcon#about to read 3, iclass 36, count 2 2006.257.18:52:44.97#ibcon#read 3, iclass 36, count 2 2006.257.18:52:44.97#ibcon#about to read 4, iclass 36, count 2 2006.257.18:52:44.97#ibcon#read 4, iclass 36, count 2 2006.257.18:52:44.97#ibcon#about to read 5, iclass 36, count 2 2006.257.18:52:44.97#ibcon#read 5, iclass 36, count 2 2006.257.18:52:44.97#ibcon#about to read 6, iclass 36, count 2 2006.257.18:52:44.97#ibcon#read 6, iclass 36, count 2 2006.257.18:52:44.97#ibcon#end of sib2, iclass 36, count 2 2006.257.18:52:44.97#ibcon#*after write, iclass 36, count 2 2006.257.18:52:44.97#ibcon#*before return 0, iclass 36, count 2 2006.257.18:52:44.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:44.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:44.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.18:52:44.97#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:44.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:45.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:45.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:45.09#ibcon#enter wrdev, iclass 36, count 0 2006.257.18:52:45.09#ibcon#first serial, iclass 36, count 0 2006.257.18:52:45.09#ibcon#enter sib2, iclass 36, count 0 2006.257.18:52:45.09#ibcon#flushed, iclass 36, count 0 2006.257.18:52:45.09#ibcon#about to write, iclass 36, count 0 2006.257.18:52:45.09#ibcon#wrote, iclass 36, count 0 2006.257.18:52:45.09#ibcon#about to read 3, iclass 36, count 0 2006.257.18:52:45.11#ibcon#read 3, iclass 36, count 0 2006.257.18:52:45.11#ibcon#about to read 4, iclass 36, count 0 2006.257.18:52:45.11#ibcon#read 4, iclass 36, count 0 2006.257.18:52:45.11#ibcon#about to read 5, iclass 36, count 0 2006.257.18:52:45.11#ibcon#read 5, iclass 36, count 0 2006.257.18:52:45.11#ibcon#about to read 6, iclass 36, count 0 2006.257.18:52:45.11#ibcon#read 6, iclass 36, count 0 2006.257.18:52:45.11#ibcon#end of sib2, iclass 36, count 0 2006.257.18:52:45.11#ibcon#*mode == 0, iclass 36, count 0 2006.257.18:52:45.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.18:52:45.11#ibcon#[25=USB\r\n] 2006.257.18:52:45.11#ibcon#*before write, iclass 36, count 0 2006.257.18:52:45.11#ibcon#enter sib2, iclass 36, count 0 2006.257.18:52:45.11#ibcon#flushed, iclass 36, count 0 2006.257.18:52:45.11#ibcon#about to write, iclass 36, count 0 2006.257.18:52:45.11#ibcon#wrote, iclass 36, count 0 2006.257.18:52:45.11#ibcon#about to read 3, iclass 36, count 0 2006.257.18:52:45.14#ibcon#read 3, iclass 36, count 0 2006.257.18:52:45.14#ibcon#about to read 4, iclass 36, count 0 2006.257.18:52:45.14#ibcon#read 4, iclass 36, count 0 2006.257.18:52:45.14#ibcon#about to read 5, iclass 36, count 0 2006.257.18:52:45.14#ibcon#read 5, iclass 36, count 0 2006.257.18:52:45.14#ibcon#about to read 6, iclass 36, count 0 2006.257.18:52:45.14#ibcon#read 6, iclass 36, count 0 2006.257.18:52:45.14#ibcon#end of sib2, iclass 36, count 0 2006.257.18:52:45.14#ibcon#*after write, iclass 36, count 0 2006.257.18:52:45.14#ibcon#*before return 0, iclass 36, count 0 2006.257.18:52:45.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:45.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:45.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.18:52:45.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.18:52:45.14$vck44/valo=6,814.99 2006.257.18:52:45.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.18:52:45.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.18:52:45.14#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:45.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:45.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:45.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:45.14#ibcon#enter wrdev, iclass 38, count 0 2006.257.18:52:45.14#ibcon#first serial, iclass 38, count 0 2006.257.18:52:45.14#ibcon#enter sib2, iclass 38, count 0 2006.257.18:52:45.14#ibcon#flushed, iclass 38, count 0 2006.257.18:52:45.14#ibcon#about to write, iclass 38, count 0 2006.257.18:52:45.14#ibcon#wrote, iclass 38, count 0 2006.257.18:52:45.14#ibcon#about to read 3, iclass 38, count 0 2006.257.18:52:45.16#ibcon#read 3, iclass 38, count 0 2006.257.18:52:45.16#ibcon#about to read 4, iclass 38, count 0 2006.257.18:52:45.16#ibcon#read 4, iclass 38, count 0 2006.257.18:52:45.16#ibcon#about to read 5, iclass 38, count 0 2006.257.18:52:45.16#ibcon#read 5, iclass 38, count 0 2006.257.18:52:45.16#ibcon#about to read 6, iclass 38, count 0 2006.257.18:52:45.16#ibcon#read 6, iclass 38, count 0 2006.257.18:52:45.16#ibcon#end of sib2, iclass 38, count 0 2006.257.18:52:45.16#ibcon#*mode == 0, iclass 38, count 0 2006.257.18:52:45.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.18:52:45.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:52:45.16#ibcon#*before write, iclass 38, count 0 2006.257.18:52:45.16#ibcon#enter sib2, iclass 38, count 0 2006.257.18:52:45.16#ibcon#flushed, iclass 38, count 0 2006.257.18:52:45.16#ibcon#about to write, iclass 38, count 0 2006.257.18:52:45.16#ibcon#wrote, iclass 38, count 0 2006.257.18:52:45.16#ibcon#about to read 3, iclass 38, count 0 2006.257.18:52:45.20#ibcon#read 3, iclass 38, count 0 2006.257.18:52:45.20#ibcon#about to read 4, iclass 38, count 0 2006.257.18:52:45.20#ibcon#read 4, iclass 38, count 0 2006.257.18:52:45.20#ibcon#about to read 5, iclass 38, count 0 2006.257.18:52:45.20#ibcon#read 5, iclass 38, count 0 2006.257.18:52:45.20#ibcon#about to read 6, iclass 38, count 0 2006.257.18:52:45.20#ibcon#read 6, iclass 38, count 0 2006.257.18:52:45.20#ibcon#end of sib2, iclass 38, count 0 2006.257.18:52:45.20#ibcon#*after write, iclass 38, count 0 2006.257.18:52:45.20#ibcon#*before return 0, iclass 38, count 0 2006.257.18:52:45.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:45.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:45.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.18:52:45.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.18:52:45.20$vck44/va=6,4 2006.257.18:52:45.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.18:52:45.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.18:52:45.20#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:45.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:45.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:45.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:45.26#ibcon#enter wrdev, iclass 40, count 2 2006.257.18:52:45.26#ibcon#first serial, iclass 40, count 2 2006.257.18:52:45.26#ibcon#enter sib2, iclass 40, count 2 2006.257.18:52:45.26#ibcon#flushed, iclass 40, count 2 2006.257.18:52:45.26#ibcon#about to write, iclass 40, count 2 2006.257.18:52:45.26#ibcon#wrote, iclass 40, count 2 2006.257.18:52:45.26#ibcon#about to read 3, iclass 40, count 2 2006.257.18:52:45.28#ibcon#read 3, iclass 40, count 2 2006.257.18:52:45.28#ibcon#about to read 4, iclass 40, count 2 2006.257.18:52:45.28#ibcon#read 4, iclass 40, count 2 2006.257.18:52:45.28#ibcon#about to read 5, iclass 40, count 2 2006.257.18:52:45.28#ibcon#read 5, iclass 40, count 2 2006.257.18:52:45.28#ibcon#about to read 6, iclass 40, count 2 2006.257.18:52:45.28#ibcon#read 6, iclass 40, count 2 2006.257.18:52:45.28#ibcon#end of sib2, iclass 40, count 2 2006.257.18:52:45.28#ibcon#*mode == 0, iclass 40, count 2 2006.257.18:52:45.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.18:52:45.28#ibcon#[25=AT06-04\r\n] 2006.257.18:52:45.28#ibcon#*before write, iclass 40, count 2 2006.257.18:52:45.28#ibcon#enter sib2, iclass 40, count 2 2006.257.18:52:45.28#ibcon#flushed, iclass 40, count 2 2006.257.18:52:45.28#ibcon#about to write, iclass 40, count 2 2006.257.18:52:45.28#ibcon#wrote, iclass 40, count 2 2006.257.18:52:45.28#ibcon#about to read 3, iclass 40, count 2 2006.257.18:52:45.31#ibcon#read 3, iclass 40, count 2 2006.257.18:52:45.31#ibcon#about to read 4, iclass 40, count 2 2006.257.18:52:45.31#ibcon#read 4, iclass 40, count 2 2006.257.18:52:45.31#ibcon#about to read 5, iclass 40, count 2 2006.257.18:52:45.31#ibcon#read 5, iclass 40, count 2 2006.257.18:52:45.31#ibcon#about to read 6, iclass 40, count 2 2006.257.18:52:45.31#ibcon#read 6, iclass 40, count 2 2006.257.18:52:45.31#ibcon#end of sib2, iclass 40, count 2 2006.257.18:52:45.31#ibcon#*after write, iclass 40, count 2 2006.257.18:52:45.31#ibcon#*before return 0, iclass 40, count 2 2006.257.18:52:45.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:45.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:45.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.18:52:45.31#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:45.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:45.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:45.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:45.43#ibcon#enter wrdev, iclass 40, count 0 2006.257.18:52:45.43#ibcon#first serial, iclass 40, count 0 2006.257.18:52:45.43#ibcon#enter sib2, iclass 40, count 0 2006.257.18:52:45.43#ibcon#flushed, iclass 40, count 0 2006.257.18:52:45.43#ibcon#about to write, iclass 40, count 0 2006.257.18:52:45.43#ibcon#wrote, iclass 40, count 0 2006.257.18:52:45.43#ibcon#about to read 3, iclass 40, count 0 2006.257.18:52:45.45#ibcon#read 3, iclass 40, count 0 2006.257.18:52:45.45#ibcon#about to read 4, iclass 40, count 0 2006.257.18:52:45.45#ibcon#read 4, iclass 40, count 0 2006.257.18:52:45.45#ibcon#about to read 5, iclass 40, count 0 2006.257.18:52:45.45#ibcon#read 5, iclass 40, count 0 2006.257.18:52:45.45#ibcon#about to read 6, iclass 40, count 0 2006.257.18:52:45.45#ibcon#read 6, iclass 40, count 0 2006.257.18:52:45.45#ibcon#end of sib2, iclass 40, count 0 2006.257.18:52:45.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.18:52:45.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.18:52:45.45#ibcon#[25=USB\r\n] 2006.257.18:52:45.45#ibcon#*before write, iclass 40, count 0 2006.257.18:52:45.45#ibcon#enter sib2, iclass 40, count 0 2006.257.18:52:45.45#ibcon#flushed, iclass 40, count 0 2006.257.18:52:45.45#ibcon#about to write, iclass 40, count 0 2006.257.18:52:45.45#ibcon#wrote, iclass 40, count 0 2006.257.18:52:45.45#ibcon#about to read 3, iclass 40, count 0 2006.257.18:52:45.48#ibcon#read 3, iclass 40, count 0 2006.257.18:52:45.48#ibcon#about to read 4, iclass 40, count 0 2006.257.18:52:45.48#ibcon#read 4, iclass 40, count 0 2006.257.18:52:45.48#ibcon#about to read 5, iclass 40, count 0 2006.257.18:52:45.48#ibcon#read 5, iclass 40, count 0 2006.257.18:52:45.48#ibcon#about to read 6, iclass 40, count 0 2006.257.18:52:45.48#ibcon#read 6, iclass 40, count 0 2006.257.18:52:45.48#ibcon#end of sib2, iclass 40, count 0 2006.257.18:52:45.48#ibcon#*after write, iclass 40, count 0 2006.257.18:52:45.48#ibcon#*before return 0, iclass 40, count 0 2006.257.18:52:45.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:45.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:45.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.18:52:45.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.18:52:45.48$vck44/valo=7,864.99 2006.257.18:52:45.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.18:52:45.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.18:52:45.48#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:45.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:45.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:45.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:45.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.18:52:45.48#ibcon#first serial, iclass 4, count 0 2006.257.18:52:45.48#ibcon#enter sib2, iclass 4, count 0 2006.257.18:52:45.48#ibcon#flushed, iclass 4, count 0 2006.257.18:52:45.48#ibcon#about to write, iclass 4, count 0 2006.257.18:52:45.48#ibcon#wrote, iclass 4, count 0 2006.257.18:52:45.48#ibcon#about to read 3, iclass 4, count 0 2006.257.18:52:45.50#ibcon#read 3, iclass 4, count 0 2006.257.18:52:45.50#ibcon#about to read 4, iclass 4, count 0 2006.257.18:52:45.50#ibcon#read 4, iclass 4, count 0 2006.257.18:52:45.50#ibcon#about to read 5, iclass 4, count 0 2006.257.18:52:45.50#ibcon#read 5, iclass 4, count 0 2006.257.18:52:45.50#ibcon#about to read 6, iclass 4, count 0 2006.257.18:52:45.50#ibcon#read 6, iclass 4, count 0 2006.257.18:52:45.50#ibcon#end of sib2, iclass 4, count 0 2006.257.18:52:45.50#ibcon#*mode == 0, iclass 4, count 0 2006.257.18:52:45.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.18:52:45.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:52:45.50#ibcon#*before write, iclass 4, count 0 2006.257.18:52:45.50#ibcon#enter sib2, iclass 4, count 0 2006.257.18:52:45.50#ibcon#flushed, iclass 4, count 0 2006.257.18:52:45.50#ibcon#about to write, iclass 4, count 0 2006.257.18:52:45.50#ibcon#wrote, iclass 4, count 0 2006.257.18:52:45.50#ibcon#about to read 3, iclass 4, count 0 2006.257.18:52:45.54#ibcon#read 3, iclass 4, count 0 2006.257.18:52:45.54#ibcon#about to read 4, iclass 4, count 0 2006.257.18:52:45.54#ibcon#read 4, iclass 4, count 0 2006.257.18:52:45.54#ibcon#about to read 5, iclass 4, count 0 2006.257.18:52:45.54#ibcon#read 5, iclass 4, count 0 2006.257.18:52:45.54#ibcon#about to read 6, iclass 4, count 0 2006.257.18:52:45.54#ibcon#read 6, iclass 4, count 0 2006.257.18:52:45.54#ibcon#end of sib2, iclass 4, count 0 2006.257.18:52:45.54#ibcon#*after write, iclass 4, count 0 2006.257.18:52:45.54#ibcon#*before return 0, iclass 4, count 0 2006.257.18:52:45.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:45.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:45.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.18:52:45.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.18:52:45.54$vck44/va=7,4 2006.257.18:52:45.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.18:52:45.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.18:52:45.54#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:45.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:45.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:45.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:45.60#ibcon#enter wrdev, iclass 6, count 2 2006.257.18:52:45.60#ibcon#first serial, iclass 6, count 2 2006.257.18:52:45.60#ibcon#enter sib2, iclass 6, count 2 2006.257.18:52:45.60#ibcon#flushed, iclass 6, count 2 2006.257.18:52:45.60#ibcon#about to write, iclass 6, count 2 2006.257.18:52:45.60#ibcon#wrote, iclass 6, count 2 2006.257.18:52:45.60#ibcon#about to read 3, iclass 6, count 2 2006.257.18:52:45.62#ibcon#read 3, iclass 6, count 2 2006.257.18:52:45.62#ibcon#about to read 4, iclass 6, count 2 2006.257.18:52:45.62#ibcon#read 4, iclass 6, count 2 2006.257.18:52:45.62#ibcon#about to read 5, iclass 6, count 2 2006.257.18:52:45.62#ibcon#read 5, iclass 6, count 2 2006.257.18:52:45.62#ibcon#about to read 6, iclass 6, count 2 2006.257.18:52:45.62#ibcon#read 6, iclass 6, count 2 2006.257.18:52:45.62#ibcon#end of sib2, iclass 6, count 2 2006.257.18:52:45.62#ibcon#*mode == 0, iclass 6, count 2 2006.257.18:52:45.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.18:52:45.62#ibcon#[25=AT07-04\r\n] 2006.257.18:52:45.62#ibcon#*before write, iclass 6, count 2 2006.257.18:52:45.62#ibcon#enter sib2, iclass 6, count 2 2006.257.18:52:45.62#ibcon#flushed, iclass 6, count 2 2006.257.18:52:45.62#ibcon#about to write, iclass 6, count 2 2006.257.18:52:45.62#ibcon#wrote, iclass 6, count 2 2006.257.18:52:45.62#ibcon#about to read 3, iclass 6, count 2 2006.257.18:52:45.65#ibcon#read 3, iclass 6, count 2 2006.257.18:52:45.65#ibcon#about to read 4, iclass 6, count 2 2006.257.18:52:45.65#ibcon#read 4, iclass 6, count 2 2006.257.18:52:45.65#ibcon#about to read 5, iclass 6, count 2 2006.257.18:52:45.65#ibcon#read 5, iclass 6, count 2 2006.257.18:52:45.65#ibcon#about to read 6, iclass 6, count 2 2006.257.18:52:45.65#ibcon#read 6, iclass 6, count 2 2006.257.18:52:45.65#ibcon#end of sib2, iclass 6, count 2 2006.257.18:52:45.65#ibcon#*after write, iclass 6, count 2 2006.257.18:52:45.65#ibcon#*before return 0, iclass 6, count 2 2006.257.18:52:45.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:45.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:45.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.18:52:45.65#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:45.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:45.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:45.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:45.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.18:52:45.77#ibcon#first serial, iclass 6, count 0 2006.257.18:52:45.77#ibcon#enter sib2, iclass 6, count 0 2006.257.18:52:45.77#ibcon#flushed, iclass 6, count 0 2006.257.18:52:45.77#ibcon#about to write, iclass 6, count 0 2006.257.18:52:45.77#ibcon#wrote, iclass 6, count 0 2006.257.18:52:45.77#ibcon#about to read 3, iclass 6, count 0 2006.257.18:52:45.79#ibcon#read 3, iclass 6, count 0 2006.257.18:52:45.79#ibcon#about to read 4, iclass 6, count 0 2006.257.18:52:45.79#ibcon#read 4, iclass 6, count 0 2006.257.18:52:45.79#ibcon#about to read 5, iclass 6, count 0 2006.257.18:52:45.79#ibcon#read 5, iclass 6, count 0 2006.257.18:52:45.79#ibcon#about to read 6, iclass 6, count 0 2006.257.18:52:45.79#ibcon#read 6, iclass 6, count 0 2006.257.18:52:45.79#ibcon#end of sib2, iclass 6, count 0 2006.257.18:52:45.79#ibcon#*mode == 0, iclass 6, count 0 2006.257.18:52:45.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.18:52:45.79#ibcon#[25=USB\r\n] 2006.257.18:52:45.79#ibcon#*before write, iclass 6, count 0 2006.257.18:52:45.79#ibcon#enter sib2, iclass 6, count 0 2006.257.18:52:45.79#ibcon#flushed, iclass 6, count 0 2006.257.18:52:45.79#ibcon#about to write, iclass 6, count 0 2006.257.18:52:45.79#ibcon#wrote, iclass 6, count 0 2006.257.18:52:45.79#ibcon#about to read 3, iclass 6, count 0 2006.257.18:52:45.82#ibcon#read 3, iclass 6, count 0 2006.257.18:52:45.82#ibcon#about to read 4, iclass 6, count 0 2006.257.18:52:45.82#ibcon#read 4, iclass 6, count 0 2006.257.18:52:45.82#ibcon#about to read 5, iclass 6, count 0 2006.257.18:52:45.82#ibcon#read 5, iclass 6, count 0 2006.257.18:52:45.82#ibcon#about to read 6, iclass 6, count 0 2006.257.18:52:45.82#ibcon#read 6, iclass 6, count 0 2006.257.18:52:45.82#ibcon#end of sib2, iclass 6, count 0 2006.257.18:52:45.82#ibcon#*after write, iclass 6, count 0 2006.257.18:52:45.82#ibcon#*before return 0, iclass 6, count 0 2006.257.18:52:45.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:45.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:45.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.18:52:45.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.18:52:45.82$vck44/valo=8,884.99 2006.257.18:52:45.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.18:52:45.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.18:52:45.82#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:45.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:45.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:45.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:45.82#ibcon#enter wrdev, iclass 10, count 0 2006.257.18:52:45.82#ibcon#first serial, iclass 10, count 0 2006.257.18:52:45.82#ibcon#enter sib2, iclass 10, count 0 2006.257.18:52:45.82#ibcon#flushed, iclass 10, count 0 2006.257.18:52:45.82#ibcon#about to write, iclass 10, count 0 2006.257.18:52:45.82#ibcon#wrote, iclass 10, count 0 2006.257.18:52:45.82#ibcon#about to read 3, iclass 10, count 0 2006.257.18:52:45.84#ibcon#read 3, iclass 10, count 0 2006.257.18:52:45.84#ibcon#about to read 4, iclass 10, count 0 2006.257.18:52:45.84#ibcon#read 4, iclass 10, count 0 2006.257.18:52:45.84#ibcon#about to read 5, iclass 10, count 0 2006.257.18:52:45.84#ibcon#read 5, iclass 10, count 0 2006.257.18:52:45.84#ibcon#about to read 6, iclass 10, count 0 2006.257.18:52:45.84#ibcon#read 6, iclass 10, count 0 2006.257.18:52:45.84#ibcon#end of sib2, iclass 10, count 0 2006.257.18:52:45.84#ibcon#*mode == 0, iclass 10, count 0 2006.257.18:52:45.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.18:52:45.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:52:45.84#ibcon#*before write, iclass 10, count 0 2006.257.18:52:45.84#ibcon#enter sib2, iclass 10, count 0 2006.257.18:52:45.84#ibcon#flushed, iclass 10, count 0 2006.257.18:52:45.84#ibcon#about to write, iclass 10, count 0 2006.257.18:52:45.84#ibcon#wrote, iclass 10, count 0 2006.257.18:52:45.84#ibcon#about to read 3, iclass 10, count 0 2006.257.18:52:45.88#ibcon#read 3, iclass 10, count 0 2006.257.18:52:45.88#ibcon#about to read 4, iclass 10, count 0 2006.257.18:52:45.88#ibcon#read 4, iclass 10, count 0 2006.257.18:52:45.88#ibcon#about to read 5, iclass 10, count 0 2006.257.18:52:45.88#ibcon#read 5, iclass 10, count 0 2006.257.18:52:45.88#ibcon#about to read 6, iclass 10, count 0 2006.257.18:52:45.88#ibcon#read 6, iclass 10, count 0 2006.257.18:52:45.88#ibcon#end of sib2, iclass 10, count 0 2006.257.18:52:45.88#ibcon#*after write, iclass 10, count 0 2006.257.18:52:45.88#ibcon#*before return 0, iclass 10, count 0 2006.257.18:52:45.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:45.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:45.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.18:52:45.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.18:52:45.88$vck44/va=8,4 2006.257.18:52:45.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.18:52:45.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.18:52:45.88#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:45.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:52:45.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:52:45.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:52:45.94#ibcon#enter wrdev, iclass 12, count 2 2006.257.18:52:45.94#ibcon#first serial, iclass 12, count 2 2006.257.18:52:45.94#ibcon#enter sib2, iclass 12, count 2 2006.257.18:52:45.94#ibcon#flushed, iclass 12, count 2 2006.257.18:52:45.94#ibcon#about to write, iclass 12, count 2 2006.257.18:52:45.94#ibcon#wrote, iclass 12, count 2 2006.257.18:52:45.94#ibcon#about to read 3, iclass 12, count 2 2006.257.18:52:45.96#ibcon#read 3, iclass 12, count 2 2006.257.18:52:45.96#ibcon#about to read 4, iclass 12, count 2 2006.257.18:52:45.96#ibcon#read 4, iclass 12, count 2 2006.257.18:52:45.96#ibcon#about to read 5, iclass 12, count 2 2006.257.18:52:45.96#ibcon#read 5, iclass 12, count 2 2006.257.18:52:45.96#ibcon#about to read 6, iclass 12, count 2 2006.257.18:52:45.96#ibcon#read 6, iclass 12, count 2 2006.257.18:52:45.96#ibcon#end of sib2, iclass 12, count 2 2006.257.18:52:45.96#ibcon#*mode == 0, iclass 12, count 2 2006.257.18:52:45.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.18:52:45.96#ibcon#[25=AT08-04\r\n] 2006.257.18:52:45.96#ibcon#*before write, iclass 12, count 2 2006.257.18:52:45.96#ibcon#enter sib2, iclass 12, count 2 2006.257.18:52:45.96#ibcon#flushed, iclass 12, count 2 2006.257.18:52:45.96#ibcon#about to write, iclass 12, count 2 2006.257.18:52:45.96#ibcon#wrote, iclass 12, count 2 2006.257.18:52:45.96#ibcon#about to read 3, iclass 12, count 2 2006.257.18:52:45.99#ibcon#read 3, iclass 12, count 2 2006.257.18:52:45.99#ibcon#about to read 4, iclass 12, count 2 2006.257.18:52:45.99#ibcon#read 4, iclass 12, count 2 2006.257.18:52:45.99#ibcon#about to read 5, iclass 12, count 2 2006.257.18:52:45.99#ibcon#read 5, iclass 12, count 2 2006.257.18:52:45.99#ibcon#about to read 6, iclass 12, count 2 2006.257.18:52:45.99#ibcon#read 6, iclass 12, count 2 2006.257.18:52:45.99#ibcon#end of sib2, iclass 12, count 2 2006.257.18:52:45.99#ibcon#*after write, iclass 12, count 2 2006.257.18:52:45.99#ibcon#*before return 0, iclass 12, count 2 2006.257.18:52:45.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:52:45.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.18:52:45.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.18:52:45.99#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:45.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:52:46.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:52:46.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:52:46.11#ibcon#enter wrdev, iclass 12, count 0 2006.257.18:52:46.11#ibcon#first serial, iclass 12, count 0 2006.257.18:52:46.11#ibcon#enter sib2, iclass 12, count 0 2006.257.18:52:46.11#ibcon#flushed, iclass 12, count 0 2006.257.18:52:46.11#ibcon#about to write, iclass 12, count 0 2006.257.18:52:46.11#ibcon#wrote, iclass 12, count 0 2006.257.18:52:46.11#ibcon#about to read 3, iclass 12, count 0 2006.257.18:52:46.13#ibcon#read 3, iclass 12, count 0 2006.257.18:52:46.13#ibcon#about to read 4, iclass 12, count 0 2006.257.18:52:46.13#ibcon#read 4, iclass 12, count 0 2006.257.18:52:46.13#ibcon#about to read 5, iclass 12, count 0 2006.257.18:52:46.13#ibcon#read 5, iclass 12, count 0 2006.257.18:52:46.13#ibcon#about to read 6, iclass 12, count 0 2006.257.18:52:46.13#ibcon#read 6, iclass 12, count 0 2006.257.18:52:46.13#ibcon#end of sib2, iclass 12, count 0 2006.257.18:52:46.13#ibcon#*mode == 0, iclass 12, count 0 2006.257.18:52:46.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.18:52:46.13#ibcon#[25=USB\r\n] 2006.257.18:52:46.13#ibcon#*before write, iclass 12, count 0 2006.257.18:52:46.13#ibcon#enter sib2, iclass 12, count 0 2006.257.18:52:46.13#ibcon#flushed, iclass 12, count 0 2006.257.18:52:46.13#ibcon#about to write, iclass 12, count 0 2006.257.18:52:46.13#ibcon#wrote, iclass 12, count 0 2006.257.18:52:46.13#ibcon#about to read 3, iclass 12, count 0 2006.257.18:52:46.16#ibcon#read 3, iclass 12, count 0 2006.257.18:52:46.16#ibcon#about to read 4, iclass 12, count 0 2006.257.18:52:46.16#ibcon#read 4, iclass 12, count 0 2006.257.18:52:46.16#ibcon#about to read 5, iclass 12, count 0 2006.257.18:52:46.16#ibcon#read 5, iclass 12, count 0 2006.257.18:52:46.16#ibcon#about to read 6, iclass 12, count 0 2006.257.18:52:46.16#ibcon#read 6, iclass 12, count 0 2006.257.18:52:46.16#ibcon#end of sib2, iclass 12, count 0 2006.257.18:52:46.16#ibcon#*after write, iclass 12, count 0 2006.257.18:52:46.16#ibcon#*before return 0, iclass 12, count 0 2006.257.18:52:46.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:52:46.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.18:52:46.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.18:52:46.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.18:52:46.16$vck44/vblo=1,629.99 2006.257.18:52:46.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.18:52:46.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.18:52:46.16#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:46.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:46.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:46.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:46.16#ibcon#enter wrdev, iclass 14, count 0 2006.257.18:52:46.16#ibcon#first serial, iclass 14, count 0 2006.257.18:52:46.16#ibcon#enter sib2, iclass 14, count 0 2006.257.18:52:46.16#ibcon#flushed, iclass 14, count 0 2006.257.18:52:46.16#ibcon#about to write, iclass 14, count 0 2006.257.18:52:46.16#ibcon#wrote, iclass 14, count 0 2006.257.18:52:46.16#ibcon#about to read 3, iclass 14, count 0 2006.257.18:52:46.18#ibcon#read 3, iclass 14, count 0 2006.257.18:52:46.18#ibcon#about to read 4, iclass 14, count 0 2006.257.18:52:46.18#ibcon#read 4, iclass 14, count 0 2006.257.18:52:46.18#ibcon#about to read 5, iclass 14, count 0 2006.257.18:52:46.18#ibcon#read 5, iclass 14, count 0 2006.257.18:52:46.18#ibcon#about to read 6, iclass 14, count 0 2006.257.18:52:46.18#ibcon#read 6, iclass 14, count 0 2006.257.18:52:46.18#ibcon#end of sib2, iclass 14, count 0 2006.257.18:52:46.18#ibcon#*mode == 0, iclass 14, count 0 2006.257.18:52:46.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.18:52:46.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:52:46.18#ibcon#*before write, iclass 14, count 0 2006.257.18:52:46.18#ibcon#enter sib2, iclass 14, count 0 2006.257.18:52:46.18#ibcon#flushed, iclass 14, count 0 2006.257.18:52:46.18#ibcon#about to write, iclass 14, count 0 2006.257.18:52:46.18#ibcon#wrote, iclass 14, count 0 2006.257.18:52:46.18#ibcon#about to read 3, iclass 14, count 0 2006.257.18:52:46.22#ibcon#read 3, iclass 14, count 0 2006.257.18:52:46.22#ibcon#about to read 4, iclass 14, count 0 2006.257.18:52:46.22#ibcon#read 4, iclass 14, count 0 2006.257.18:52:46.22#ibcon#about to read 5, iclass 14, count 0 2006.257.18:52:46.22#ibcon#read 5, iclass 14, count 0 2006.257.18:52:46.22#ibcon#about to read 6, iclass 14, count 0 2006.257.18:52:46.22#ibcon#read 6, iclass 14, count 0 2006.257.18:52:46.22#ibcon#end of sib2, iclass 14, count 0 2006.257.18:52:46.22#ibcon#*after write, iclass 14, count 0 2006.257.18:52:46.22#ibcon#*before return 0, iclass 14, count 0 2006.257.18:52:46.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:46.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.18:52:46.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.18:52:46.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.18:52:46.22$vck44/vb=1,4 2006.257.18:52:46.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.18:52:46.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.18:52:46.22#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:46.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:46.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:46.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:46.22#ibcon#enter wrdev, iclass 16, count 2 2006.257.18:52:46.22#ibcon#first serial, iclass 16, count 2 2006.257.18:52:46.22#ibcon#enter sib2, iclass 16, count 2 2006.257.18:52:46.22#ibcon#flushed, iclass 16, count 2 2006.257.18:52:46.22#ibcon#about to write, iclass 16, count 2 2006.257.18:52:46.22#ibcon#wrote, iclass 16, count 2 2006.257.18:52:46.22#ibcon#about to read 3, iclass 16, count 2 2006.257.18:52:46.24#ibcon#read 3, iclass 16, count 2 2006.257.18:52:46.24#ibcon#about to read 4, iclass 16, count 2 2006.257.18:52:46.24#ibcon#read 4, iclass 16, count 2 2006.257.18:52:46.24#ibcon#about to read 5, iclass 16, count 2 2006.257.18:52:46.24#ibcon#read 5, iclass 16, count 2 2006.257.18:52:46.24#ibcon#about to read 6, iclass 16, count 2 2006.257.18:52:46.24#ibcon#read 6, iclass 16, count 2 2006.257.18:52:46.24#ibcon#end of sib2, iclass 16, count 2 2006.257.18:52:46.24#ibcon#*mode == 0, iclass 16, count 2 2006.257.18:52:46.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.18:52:46.24#ibcon#[27=AT01-04\r\n] 2006.257.18:52:46.24#ibcon#*before write, iclass 16, count 2 2006.257.18:52:46.24#ibcon#enter sib2, iclass 16, count 2 2006.257.18:52:46.24#ibcon#flushed, iclass 16, count 2 2006.257.18:52:46.24#ibcon#about to write, iclass 16, count 2 2006.257.18:52:46.24#ibcon#wrote, iclass 16, count 2 2006.257.18:52:46.24#ibcon#about to read 3, iclass 16, count 2 2006.257.18:52:46.27#ibcon#read 3, iclass 16, count 2 2006.257.18:52:46.27#ibcon#about to read 4, iclass 16, count 2 2006.257.18:52:46.27#ibcon#read 4, iclass 16, count 2 2006.257.18:52:46.27#ibcon#about to read 5, iclass 16, count 2 2006.257.18:52:46.27#ibcon#read 5, iclass 16, count 2 2006.257.18:52:46.27#ibcon#about to read 6, iclass 16, count 2 2006.257.18:52:46.27#ibcon#read 6, iclass 16, count 2 2006.257.18:52:46.27#ibcon#end of sib2, iclass 16, count 2 2006.257.18:52:46.27#ibcon#*after write, iclass 16, count 2 2006.257.18:52:46.27#ibcon#*before return 0, iclass 16, count 2 2006.257.18:52:46.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:46.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.18:52:46.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.18:52:46.27#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:46.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:46.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:46.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:46.39#ibcon#enter wrdev, iclass 16, count 0 2006.257.18:52:46.39#ibcon#first serial, iclass 16, count 0 2006.257.18:52:46.39#ibcon#enter sib2, iclass 16, count 0 2006.257.18:52:46.39#ibcon#flushed, iclass 16, count 0 2006.257.18:52:46.39#ibcon#about to write, iclass 16, count 0 2006.257.18:52:46.39#ibcon#wrote, iclass 16, count 0 2006.257.18:52:46.39#ibcon#about to read 3, iclass 16, count 0 2006.257.18:52:46.41#ibcon#read 3, iclass 16, count 0 2006.257.18:52:46.41#ibcon#about to read 4, iclass 16, count 0 2006.257.18:52:46.41#ibcon#read 4, iclass 16, count 0 2006.257.18:52:46.41#ibcon#about to read 5, iclass 16, count 0 2006.257.18:52:46.41#ibcon#read 5, iclass 16, count 0 2006.257.18:52:46.41#ibcon#about to read 6, iclass 16, count 0 2006.257.18:52:46.41#ibcon#read 6, iclass 16, count 0 2006.257.18:52:46.41#ibcon#end of sib2, iclass 16, count 0 2006.257.18:52:46.41#ibcon#*mode == 0, iclass 16, count 0 2006.257.18:52:46.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.18:52:46.41#ibcon#[27=USB\r\n] 2006.257.18:52:46.41#ibcon#*before write, iclass 16, count 0 2006.257.18:52:46.41#ibcon#enter sib2, iclass 16, count 0 2006.257.18:52:46.41#ibcon#flushed, iclass 16, count 0 2006.257.18:52:46.41#ibcon#about to write, iclass 16, count 0 2006.257.18:52:46.41#ibcon#wrote, iclass 16, count 0 2006.257.18:52:46.41#ibcon#about to read 3, iclass 16, count 0 2006.257.18:52:46.44#ibcon#read 3, iclass 16, count 0 2006.257.18:52:46.44#ibcon#about to read 4, iclass 16, count 0 2006.257.18:52:46.44#ibcon#read 4, iclass 16, count 0 2006.257.18:52:46.44#ibcon#about to read 5, iclass 16, count 0 2006.257.18:52:46.44#ibcon#read 5, iclass 16, count 0 2006.257.18:52:46.44#ibcon#about to read 6, iclass 16, count 0 2006.257.18:52:46.44#ibcon#read 6, iclass 16, count 0 2006.257.18:52:46.44#ibcon#end of sib2, iclass 16, count 0 2006.257.18:52:46.44#ibcon#*after write, iclass 16, count 0 2006.257.18:52:46.44#ibcon#*before return 0, iclass 16, count 0 2006.257.18:52:46.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:46.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.18:52:46.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.18:52:46.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.18:52:46.44$vck44/vblo=2,634.99 2006.257.18:52:46.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.18:52:46.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.18:52:46.44#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:46.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:46.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:46.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:46.44#ibcon#enter wrdev, iclass 18, count 0 2006.257.18:52:46.44#ibcon#first serial, iclass 18, count 0 2006.257.18:52:46.44#ibcon#enter sib2, iclass 18, count 0 2006.257.18:52:46.44#ibcon#flushed, iclass 18, count 0 2006.257.18:52:46.44#ibcon#about to write, iclass 18, count 0 2006.257.18:52:46.44#ibcon#wrote, iclass 18, count 0 2006.257.18:52:46.44#ibcon#about to read 3, iclass 18, count 0 2006.257.18:52:46.46#ibcon#read 3, iclass 18, count 0 2006.257.18:52:46.46#ibcon#about to read 4, iclass 18, count 0 2006.257.18:52:46.46#ibcon#read 4, iclass 18, count 0 2006.257.18:52:46.46#ibcon#about to read 5, iclass 18, count 0 2006.257.18:52:46.46#ibcon#read 5, iclass 18, count 0 2006.257.18:52:46.46#ibcon#about to read 6, iclass 18, count 0 2006.257.18:52:46.46#ibcon#read 6, iclass 18, count 0 2006.257.18:52:46.46#ibcon#end of sib2, iclass 18, count 0 2006.257.18:52:46.46#ibcon#*mode == 0, iclass 18, count 0 2006.257.18:52:46.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.18:52:46.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:52:46.46#ibcon#*before write, iclass 18, count 0 2006.257.18:52:46.46#ibcon#enter sib2, iclass 18, count 0 2006.257.18:52:46.46#ibcon#flushed, iclass 18, count 0 2006.257.18:52:46.46#ibcon#about to write, iclass 18, count 0 2006.257.18:52:46.46#ibcon#wrote, iclass 18, count 0 2006.257.18:52:46.46#ibcon#about to read 3, iclass 18, count 0 2006.257.18:52:46.50#ibcon#read 3, iclass 18, count 0 2006.257.18:52:46.50#ibcon#about to read 4, iclass 18, count 0 2006.257.18:52:46.50#ibcon#read 4, iclass 18, count 0 2006.257.18:52:46.50#ibcon#about to read 5, iclass 18, count 0 2006.257.18:52:46.50#ibcon#read 5, iclass 18, count 0 2006.257.18:52:46.50#ibcon#about to read 6, iclass 18, count 0 2006.257.18:52:46.50#ibcon#read 6, iclass 18, count 0 2006.257.18:52:46.50#ibcon#end of sib2, iclass 18, count 0 2006.257.18:52:46.50#ibcon#*after write, iclass 18, count 0 2006.257.18:52:46.50#ibcon#*before return 0, iclass 18, count 0 2006.257.18:52:46.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:46.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.18:52:46.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.18:52:46.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.18:52:46.50$vck44/vb=2,5 2006.257.18:52:46.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.18:52:46.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.18:52:46.50#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:46.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:46.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:46.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:46.56#ibcon#enter wrdev, iclass 20, count 2 2006.257.18:52:46.56#ibcon#first serial, iclass 20, count 2 2006.257.18:52:46.56#ibcon#enter sib2, iclass 20, count 2 2006.257.18:52:46.56#ibcon#flushed, iclass 20, count 2 2006.257.18:52:46.56#ibcon#about to write, iclass 20, count 2 2006.257.18:52:46.56#ibcon#wrote, iclass 20, count 2 2006.257.18:52:46.56#ibcon#about to read 3, iclass 20, count 2 2006.257.18:52:46.58#ibcon#read 3, iclass 20, count 2 2006.257.18:52:46.58#ibcon#about to read 4, iclass 20, count 2 2006.257.18:52:46.58#ibcon#read 4, iclass 20, count 2 2006.257.18:52:46.58#ibcon#about to read 5, iclass 20, count 2 2006.257.18:52:46.58#ibcon#read 5, iclass 20, count 2 2006.257.18:52:46.58#ibcon#about to read 6, iclass 20, count 2 2006.257.18:52:46.58#ibcon#read 6, iclass 20, count 2 2006.257.18:52:46.58#ibcon#end of sib2, iclass 20, count 2 2006.257.18:52:46.58#ibcon#*mode == 0, iclass 20, count 2 2006.257.18:52:46.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.18:52:46.58#ibcon#[27=AT02-05\r\n] 2006.257.18:52:46.58#ibcon#*before write, iclass 20, count 2 2006.257.18:52:46.58#ibcon#enter sib2, iclass 20, count 2 2006.257.18:52:46.58#ibcon#flushed, iclass 20, count 2 2006.257.18:52:46.58#ibcon#about to write, iclass 20, count 2 2006.257.18:52:46.58#ibcon#wrote, iclass 20, count 2 2006.257.18:52:46.58#ibcon#about to read 3, iclass 20, count 2 2006.257.18:52:46.61#ibcon#read 3, iclass 20, count 2 2006.257.18:52:46.61#ibcon#about to read 4, iclass 20, count 2 2006.257.18:52:46.61#ibcon#read 4, iclass 20, count 2 2006.257.18:52:46.61#ibcon#about to read 5, iclass 20, count 2 2006.257.18:52:46.61#ibcon#read 5, iclass 20, count 2 2006.257.18:52:46.61#ibcon#about to read 6, iclass 20, count 2 2006.257.18:52:46.61#ibcon#read 6, iclass 20, count 2 2006.257.18:52:46.61#ibcon#end of sib2, iclass 20, count 2 2006.257.18:52:46.61#ibcon#*after write, iclass 20, count 2 2006.257.18:52:46.61#ibcon#*before return 0, iclass 20, count 2 2006.257.18:52:46.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:46.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.18:52:46.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.18:52:46.61#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:46.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:46.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:46.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:46.73#ibcon#enter wrdev, iclass 20, count 0 2006.257.18:52:46.73#ibcon#first serial, iclass 20, count 0 2006.257.18:52:46.73#ibcon#enter sib2, iclass 20, count 0 2006.257.18:52:46.73#ibcon#flushed, iclass 20, count 0 2006.257.18:52:46.73#ibcon#about to write, iclass 20, count 0 2006.257.18:52:46.73#ibcon#wrote, iclass 20, count 0 2006.257.18:52:46.73#ibcon#about to read 3, iclass 20, count 0 2006.257.18:52:46.75#ibcon#read 3, iclass 20, count 0 2006.257.18:52:46.75#ibcon#about to read 4, iclass 20, count 0 2006.257.18:52:46.75#ibcon#read 4, iclass 20, count 0 2006.257.18:52:46.75#ibcon#about to read 5, iclass 20, count 0 2006.257.18:52:46.75#ibcon#read 5, iclass 20, count 0 2006.257.18:52:46.75#ibcon#about to read 6, iclass 20, count 0 2006.257.18:52:46.75#ibcon#read 6, iclass 20, count 0 2006.257.18:52:46.75#ibcon#end of sib2, iclass 20, count 0 2006.257.18:52:46.75#ibcon#*mode == 0, iclass 20, count 0 2006.257.18:52:46.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.18:52:46.75#ibcon#[27=USB\r\n] 2006.257.18:52:46.75#ibcon#*before write, iclass 20, count 0 2006.257.18:52:46.75#ibcon#enter sib2, iclass 20, count 0 2006.257.18:52:46.75#ibcon#flushed, iclass 20, count 0 2006.257.18:52:46.75#ibcon#about to write, iclass 20, count 0 2006.257.18:52:46.75#ibcon#wrote, iclass 20, count 0 2006.257.18:52:46.75#ibcon#about to read 3, iclass 20, count 0 2006.257.18:52:46.78#ibcon#read 3, iclass 20, count 0 2006.257.18:52:46.78#ibcon#about to read 4, iclass 20, count 0 2006.257.18:52:46.78#ibcon#read 4, iclass 20, count 0 2006.257.18:52:46.78#ibcon#about to read 5, iclass 20, count 0 2006.257.18:52:46.78#ibcon#read 5, iclass 20, count 0 2006.257.18:52:46.78#ibcon#about to read 6, iclass 20, count 0 2006.257.18:52:46.78#ibcon#read 6, iclass 20, count 0 2006.257.18:52:46.78#ibcon#end of sib2, iclass 20, count 0 2006.257.18:52:46.78#ibcon#*after write, iclass 20, count 0 2006.257.18:52:46.78#ibcon#*before return 0, iclass 20, count 0 2006.257.18:52:46.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:46.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.18:52:46.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.18:52:46.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.18:52:46.78$vck44/vblo=3,649.99 2006.257.18:52:46.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.18:52:46.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.18:52:46.78#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:46.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:52:46.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:52:46.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:52:46.78#ibcon#enter wrdev, iclass 22, count 0 2006.257.18:52:46.78#ibcon#first serial, iclass 22, count 0 2006.257.18:52:46.78#ibcon#enter sib2, iclass 22, count 0 2006.257.18:52:46.78#ibcon#flushed, iclass 22, count 0 2006.257.18:52:46.78#ibcon#about to write, iclass 22, count 0 2006.257.18:52:46.78#ibcon#wrote, iclass 22, count 0 2006.257.18:52:46.78#ibcon#about to read 3, iclass 22, count 0 2006.257.18:52:46.80#ibcon#read 3, iclass 22, count 0 2006.257.18:52:46.80#ibcon#about to read 4, iclass 22, count 0 2006.257.18:52:46.80#ibcon#read 4, iclass 22, count 0 2006.257.18:52:46.80#ibcon#about to read 5, iclass 22, count 0 2006.257.18:52:46.80#ibcon#read 5, iclass 22, count 0 2006.257.18:52:46.80#ibcon#about to read 6, iclass 22, count 0 2006.257.18:52:46.80#ibcon#read 6, iclass 22, count 0 2006.257.18:52:46.80#ibcon#end of sib2, iclass 22, count 0 2006.257.18:52:46.80#ibcon#*mode == 0, iclass 22, count 0 2006.257.18:52:46.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.18:52:46.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:52:46.80#ibcon#*before write, iclass 22, count 0 2006.257.18:52:46.80#ibcon#enter sib2, iclass 22, count 0 2006.257.18:52:46.80#ibcon#flushed, iclass 22, count 0 2006.257.18:52:46.80#ibcon#about to write, iclass 22, count 0 2006.257.18:52:46.80#ibcon#wrote, iclass 22, count 0 2006.257.18:52:46.80#ibcon#about to read 3, iclass 22, count 0 2006.257.18:52:46.84#ibcon#read 3, iclass 22, count 0 2006.257.18:52:46.84#ibcon#about to read 4, iclass 22, count 0 2006.257.18:52:46.84#ibcon#read 4, iclass 22, count 0 2006.257.18:52:46.84#ibcon#about to read 5, iclass 22, count 0 2006.257.18:52:46.84#ibcon#read 5, iclass 22, count 0 2006.257.18:52:46.84#ibcon#about to read 6, iclass 22, count 0 2006.257.18:52:46.84#ibcon#read 6, iclass 22, count 0 2006.257.18:52:46.84#ibcon#end of sib2, iclass 22, count 0 2006.257.18:52:46.84#ibcon#*after write, iclass 22, count 0 2006.257.18:52:46.84#ibcon#*before return 0, iclass 22, count 0 2006.257.18:52:46.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:52:46.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.18:52:46.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.18:52:46.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.18:52:46.84$vck44/vb=3,4 2006.257.18:52:46.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.18:52:46.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.18:52:46.84#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:46.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:52:46.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:52:46.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:52:46.90#ibcon#enter wrdev, iclass 24, count 2 2006.257.18:52:46.90#ibcon#first serial, iclass 24, count 2 2006.257.18:52:46.90#ibcon#enter sib2, iclass 24, count 2 2006.257.18:52:46.90#ibcon#flushed, iclass 24, count 2 2006.257.18:52:46.90#ibcon#about to write, iclass 24, count 2 2006.257.18:52:46.90#ibcon#wrote, iclass 24, count 2 2006.257.18:52:46.90#ibcon#about to read 3, iclass 24, count 2 2006.257.18:52:46.92#ibcon#read 3, iclass 24, count 2 2006.257.18:52:46.92#ibcon#about to read 4, iclass 24, count 2 2006.257.18:52:46.92#ibcon#read 4, iclass 24, count 2 2006.257.18:52:46.92#ibcon#about to read 5, iclass 24, count 2 2006.257.18:52:46.92#ibcon#read 5, iclass 24, count 2 2006.257.18:52:46.92#ibcon#about to read 6, iclass 24, count 2 2006.257.18:52:46.92#ibcon#read 6, iclass 24, count 2 2006.257.18:52:46.92#ibcon#end of sib2, iclass 24, count 2 2006.257.18:52:46.92#ibcon#*mode == 0, iclass 24, count 2 2006.257.18:52:46.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.18:52:46.92#ibcon#[27=AT03-04\r\n] 2006.257.18:52:46.92#ibcon#*before write, iclass 24, count 2 2006.257.18:52:46.92#ibcon#enter sib2, iclass 24, count 2 2006.257.18:52:46.92#ibcon#flushed, iclass 24, count 2 2006.257.18:52:46.92#ibcon#about to write, iclass 24, count 2 2006.257.18:52:46.92#ibcon#wrote, iclass 24, count 2 2006.257.18:52:46.92#ibcon#about to read 3, iclass 24, count 2 2006.257.18:52:46.95#ibcon#read 3, iclass 24, count 2 2006.257.18:52:46.95#ibcon#about to read 4, iclass 24, count 2 2006.257.18:52:46.95#ibcon#read 4, iclass 24, count 2 2006.257.18:52:46.95#ibcon#about to read 5, iclass 24, count 2 2006.257.18:52:46.95#ibcon#read 5, iclass 24, count 2 2006.257.18:52:46.95#ibcon#about to read 6, iclass 24, count 2 2006.257.18:52:46.95#ibcon#read 6, iclass 24, count 2 2006.257.18:52:46.95#ibcon#end of sib2, iclass 24, count 2 2006.257.18:52:46.95#ibcon#*after write, iclass 24, count 2 2006.257.18:52:46.95#ibcon#*before return 0, iclass 24, count 2 2006.257.18:52:46.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:52:46.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.18:52:46.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.18:52:46.95#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:46.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:52:47.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:52:47.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:52:47.07#ibcon#enter wrdev, iclass 24, count 0 2006.257.18:52:47.07#ibcon#first serial, iclass 24, count 0 2006.257.18:52:47.07#ibcon#enter sib2, iclass 24, count 0 2006.257.18:52:47.07#ibcon#flushed, iclass 24, count 0 2006.257.18:52:47.07#ibcon#about to write, iclass 24, count 0 2006.257.18:52:47.07#ibcon#wrote, iclass 24, count 0 2006.257.18:52:47.07#ibcon#about to read 3, iclass 24, count 0 2006.257.18:52:47.09#ibcon#read 3, iclass 24, count 0 2006.257.18:52:47.09#ibcon#about to read 4, iclass 24, count 0 2006.257.18:52:47.09#ibcon#read 4, iclass 24, count 0 2006.257.18:52:47.09#ibcon#about to read 5, iclass 24, count 0 2006.257.18:52:47.09#ibcon#read 5, iclass 24, count 0 2006.257.18:52:47.09#ibcon#about to read 6, iclass 24, count 0 2006.257.18:52:47.09#ibcon#read 6, iclass 24, count 0 2006.257.18:52:47.09#ibcon#end of sib2, iclass 24, count 0 2006.257.18:52:47.09#ibcon#*mode == 0, iclass 24, count 0 2006.257.18:52:47.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.18:52:47.09#ibcon#[27=USB\r\n] 2006.257.18:52:47.09#ibcon#*before write, iclass 24, count 0 2006.257.18:52:47.09#ibcon#enter sib2, iclass 24, count 0 2006.257.18:52:47.09#ibcon#flushed, iclass 24, count 0 2006.257.18:52:47.09#ibcon#about to write, iclass 24, count 0 2006.257.18:52:47.09#ibcon#wrote, iclass 24, count 0 2006.257.18:52:47.09#ibcon#about to read 3, iclass 24, count 0 2006.257.18:52:47.12#ibcon#read 3, iclass 24, count 0 2006.257.18:52:47.12#ibcon#about to read 4, iclass 24, count 0 2006.257.18:52:47.12#ibcon#read 4, iclass 24, count 0 2006.257.18:52:47.12#ibcon#about to read 5, iclass 24, count 0 2006.257.18:52:47.12#ibcon#read 5, iclass 24, count 0 2006.257.18:52:47.12#ibcon#about to read 6, iclass 24, count 0 2006.257.18:52:47.12#ibcon#read 6, iclass 24, count 0 2006.257.18:52:47.12#ibcon#end of sib2, iclass 24, count 0 2006.257.18:52:47.12#ibcon#*after write, iclass 24, count 0 2006.257.18:52:47.12#ibcon#*before return 0, iclass 24, count 0 2006.257.18:52:47.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:52:47.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.18:52:47.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.18:52:47.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.18:52:47.12$vck44/vblo=4,679.99 2006.257.18:52:47.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.18:52:47.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.18:52:47.12#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:47.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:47.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:47.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:47.12#ibcon#enter wrdev, iclass 26, count 0 2006.257.18:52:47.12#ibcon#first serial, iclass 26, count 0 2006.257.18:52:47.12#ibcon#enter sib2, iclass 26, count 0 2006.257.18:52:47.12#ibcon#flushed, iclass 26, count 0 2006.257.18:52:47.12#ibcon#about to write, iclass 26, count 0 2006.257.18:52:47.12#ibcon#wrote, iclass 26, count 0 2006.257.18:52:47.12#ibcon#about to read 3, iclass 26, count 0 2006.257.18:52:47.14#ibcon#read 3, iclass 26, count 0 2006.257.18:52:47.14#ibcon#about to read 4, iclass 26, count 0 2006.257.18:52:47.14#ibcon#read 4, iclass 26, count 0 2006.257.18:52:47.14#ibcon#about to read 5, iclass 26, count 0 2006.257.18:52:47.14#ibcon#read 5, iclass 26, count 0 2006.257.18:52:47.14#ibcon#about to read 6, iclass 26, count 0 2006.257.18:52:47.14#ibcon#read 6, iclass 26, count 0 2006.257.18:52:47.14#ibcon#end of sib2, iclass 26, count 0 2006.257.18:52:47.14#ibcon#*mode == 0, iclass 26, count 0 2006.257.18:52:47.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.18:52:47.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:52:47.14#ibcon#*before write, iclass 26, count 0 2006.257.18:52:47.14#ibcon#enter sib2, iclass 26, count 0 2006.257.18:52:47.14#ibcon#flushed, iclass 26, count 0 2006.257.18:52:47.14#ibcon#about to write, iclass 26, count 0 2006.257.18:52:47.14#ibcon#wrote, iclass 26, count 0 2006.257.18:52:47.14#ibcon#about to read 3, iclass 26, count 0 2006.257.18:52:47.18#ibcon#read 3, iclass 26, count 0 2006.257.18:52:47.18#ibcon#about to read 4, iclass 26, count 0 2006.257.18:52:47.18#ibcon#read 4, iclass 26, count 0 2006.257.18:52:47.18#ibcon#about to read 5, iclass 26, count 0 2006.257.18:52:47.18#ibcon#read 5, iclass 26, count 0 2006.257.18:52:47.18#ibcon#about to read 6, iclass 26, count 0 2006.257.18:52:47.18#ibcon#read 6, iclass 26, count 0 2006.257.18:52:47.18#ibcon#end of sib2, iclass 26, count 0 2006.257.18:52:47.18#ibcon#*after write, iclass 26, count 0 2006.257.18:52:47.18#ibcon#*before return 0, iclass 26, count 0 2006.257.18:52:47.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:47.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.18:52:47.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.18:52:47.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.18:52:47.18$vck44/vb=4,5 2006.257.18:52:47.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.18:52:47.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.18:52:47.18#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:47.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:47.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:47.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:47.24#ibcon#enter wrdev, iclass 28, count 2 2006.257.18:52:47.24#ibcon#first serial, iclass 28, count 2 2006.257.18:52:47.24#ibcon#enter sib2, iclass 28, count 2 2006.257.18:52:47.24#ibcon#flushed, iclass 28, count 2 2006.257.18:52:47.24#ibcon#about to write, iclass 28, count 2 2006.257.18:52:47.24#ibcon#wrote, iclass 28, count 2 2006.257.18:52:47.24#ibcon#about to read 3, iclass 28, count 2 2006.257.18:52:47.26#ibcon#read 3, iclass 28, count 2 2006.257.18:52:47.26#ibcon#about to read 4, iclass 28, count 2 2006.257.18:52:47.26#ibcon#read 4, iclass 28, count 2 2006.257.18:52:47.26#ibcon#about to read 5, iclass 28, count 2 2006.257.18:52:47.26#ibcon#read 5, iclass 28, count 2 2006.257.18:52:47.26#ibcon#about to read 6, iclass 28, count 2 2006.257.18:52:47.26#ibcon#read 6, iclass 28, count 2 2006.257.18:52:47.26#ibcon#end of sib2, iclass 28, count 2 2006.257.18:52:47.26#ibcon#*mode == 0, iclass 28, count 2 2006.257.18:52:47.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.18:52:47.26#ibcon#[27=AT04-05\r\n] 2006.257.18:52:47.26#ibcon#*before write, iclass 28, count 2 2006.257.18:52:47.26#ibcon#enter sib2, iclass 28, count 2 2006.257.18:52:47.26#ibcon#flushed, iclass 28, count 2 2006.257.18:52:47.26#ibcon#about to write, iclass 28, count 2 2006.257.18:52:47.26#ibcon#wrote, iclass 28, count 2 2006.257.18:52:47.26#ibcon#about to read 3, iclass 28, count 2 2006.257.18:52:47.29#ibcon#read 3, iclass 28, count 2 2006.257.18:52:47.29#ibcon#about to read 4, iclass 28, count 2 2006.257.18:52:47.29#ibcon#read 4, iclass 28, count 2 2006.257.18:52:47.29#ibcon#about to read 5, iclass 28, count 2 2006.257.18:52:47.29#ibcon#read 5, iclass 28, count 2 2006.257.18:52:47.29#ibcon#about to read 6, iclass 28, count 2 2006.257.18:52:47.29#ibcon#read 6, iclass 28, count 2 2006.257.18:52:47.29#ibcon#end of sib2, iclass 28, count 2 2006.257.18:52:47.29#ibcon#*after write, iclass 28, count 2 2006.257.18:52:47.29#ibcon#*before return 0, iclass 28, count 2 2006.257.18:52:47.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:47.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.18:52:47.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.18:52:47.29#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:47.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:47.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:47.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:47.41#ibcon#enter wrdev, iclass 28, count 0 2006.257.18:52:47.41#ibcon#first serial, iclass 28, count 0 2006.257.18:52:47.41#ibcon#enter sib2, iclass 28, count 0 2006.257.18:52:47.41#ibcon#flushed, iclass 28, count 0 2006.257.18:52:47.41#ibcon#about to write, iclass 28, count 0 2006.257.18:52:47.41#ibcon#wrote, iclass 28, count 0 2006.257.18:52:47.41#ibcon#about to read 3, iclass 28, count 0 2006.257.18:52:47.43#ibcon#read 3, iclass 28, count 0 2006.257.18:52:47.43#ibcon#about to read 4, iclass 28, count 0 2006.257.18:52:47.43#ibcon#read 4, iclass 28, count 0 2006.257.18:52:47.43#ibcon#about to read 5, iclass 28, count 0 2006.257.18:52:47.43#ibcon#read 5, iclass 28, count 0 2006.257.18:52:47.43#ibcon#about to read 6, iclass 28, count 0 2006.257.18:52:47.43#ibcon#read 6, iclass 28, count 0 2006.257.18:52:47.43#ibcon#end of sib2, iclass 28, count 0 2006.257.18:52:47.43#ibcon#*mode == 0, iclass 28, count 0 2006.257.18:52:47.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.18:52:47.43#ibcon#[27=USB\r\n] 2006.257.18:52:47.43#ibcon#*before write, iclass 28, count 0 2006.257.18:52:47.43#ibcon#enter sib2, iclass 28, count 0 2006.257.18:52:47.43#ibcon#flushed, iclass 28, count 0 2006.257.18:52:47.43#ibcon#about to write, iclass 28, count 0 2006.257.18:52:47.43#ibcon#wrote, iclass 28, count 0 2006.257.18:52:47.43#ibcon#about to read 3, iclass 28, count 0 2006.257.18:52:47.46#ibcon#read 3, iclass 28, count 0 2006.257.18:52:47.46#ibcon#about to read 4, iclass 28, count 0 2006.257.18:52:47.46#ibcon#read 4, iclass 28, count 0 2006.257.18:52:47.46#ibcon#about to read 5, iclass 28, count 0 2006.257.18:52:47.46#ibcon#read 5, iclass 28, count 0 2006.257.18:52:47.46#ibcon#about to read 6, iclass 28, count 0 2006.257.18:52:47.46#ibcon#read 6, iclass 28, count 0 2006.257.18:52:47.46#ibcon#end of sib2, iclass 28, count 0 2006.257.18:52:47.46#ibcon#*after write, iclass 28, count 0 2006.257.18:52:47.46#ibcon#*before return 0, iclass 28, count 0 2006.257.18:52:47.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:47.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.18:52:47.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.18:52:47.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.18:52:47.46$vck44/vblo=5,709.99 2006.257.18:52:47.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.18:52:47.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.18:52:47.46#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:47.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:47.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:47.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:47.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.18:52:47.46#ibcon#first serial, iclass 30, count 0 2006.257.18:52:47.46#ibcon#enter sib2, iclass 30, count 0 2006.257.18:52:47.46#ibcon#flushed, iclass 30, count 0 2006.257.18:52:47.46#ibcon#about to write, iclass 30, count 0 2006.257.18:52:47.46#ibcon#wrote, iclass 30, count 0 2006.257.18:52:47.46#ibcon#about to read 3, iclass 30, count 0 2006.257.18:52:47.48#ibcon#read 3, iclass 30, count 0 2006.257.18:52:47.48#ibcon#about to read 4, iclass 30, count 0 2006.257.18:52:47.48#ibcon#read 4, iclass 30, count 0 2006.257.18:52:47.48#ibcon#about to read 5, iclass 30, count 0 2006.257.18:52:47.48#ibcon#read 5, iclass 30, count 0 2006.257.18:52:47.48#ibcon#about to read 6, iclass 30, count 0 2006.257.18:52:47.48#ibcon#read 6, iclass 30, count 0 2006.257.18:52:47.48#ibcon#end of sib2, iclass 30, count 0 2006.257.18:52:47.48#ibcon#*mode == 0, iclass 30, count 0 2006.257.18:52:47.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.18:52:47.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:52:47.48#ibcon#*before write, iclass 30, count 0 2006.257.18:52:47.48#ibcon#enter sib2, iclass 30, count 0 2006.257.18:52:47.48#ibcon#flushed, iclass 30, count 0 2006.257.18:52:47.48#ibcon#about to write, iclass 30, count 0 2006.257.18:52:47.48#ibcon#wrote, iclass 30, count 0 2006.257.18:52:47.48#ibcon#about to read 3, iclass 30, count 0 2006.257.18:52:47.52#ibcon#read 3, iclass 30, count 0 2006.257.18:52:47.52#ibcon#about to read 4, iclass 30, count 0 2006.257.18:52:47.52#ibcon#read 4, iclass 30, count 0 2006.257.18:52:47.52#ibcon#about to read 5, iclass 30, count 0 2006.257.18:52:47.52#ibcon#read 5, iclass 30, count 0 2006.257.18:52:47.52#ibcon#about to read 6, iclass 30, count 0 2006.257.18:52:47.52#ibcon#read 6, iclass 30, count 0 2006.257.18:52:47.52#ibcon#end of sib2, iclass 30, count 0 2006.257.18:52:47.52#ibcon#*after write, iclass 30, count 0 2006.257.18:52:47.52#ibcon#*before return 0, iclass 30, count 0 2006.257.18:52:47.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:47.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.18:52:47.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.18:52:47.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.18:52:47.52$vck44/vb=5,4 2006.257.18:52:47.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.18:52:47.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.18:52:47.52#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:47.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:47.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:47.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:47.58#ibcon#enter wrdev, iclass 32, count 2 2006.257.18:52:47.58#ibcon#first serial, iclass 32, count 2 2006.257.18:52:47.58#ibcon#enter sib2, iclass 32, count 2 2006.257.18:52:47.58#ibcon#flushed, iclass 32, count 2 2006.257.18:52:47.58#ibcon#about to write, iclass 32, count 2 2006.257.18:52:47.58#ibcon#wrote, iclass 32, count 2 2006.257.18:52:47.58#ibcon#about to read 3, iclass 32, count 2 2006.257.18:52:47.60#ibcon#read 3, iclass 32, count 2 2006.257.18:52:47.60#ibcon#about to read 4, iclass 32, count 2 2006.257.18:52:47.60#ibcon#read 4, iclass 32, count 2 2006.257.18:52:47.60#ibcon#about to read 5, iclass 32, count 2 2006.257.18:52:47.60#ibcon#read 5, iclass 32, count 2 2006.257.18:52:47.60#ibcon#about to read 6, iclass 32, count 2 2006.257.18:52:47.60#ibcon#read 6, iclass 32, count 2 2006.257.18:52:47.60#ibcon#end of sib2, iclass 32, count 2 2006.257.18:52:47.60#ibcon#*mode == 0, iclass 32, count 2 2006.257.18:52:47.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.18:52:47.60#ibcon#[27=AT05-04\r\n] 2006.257.18:52:47.60#ibcon#*before write, iclass 32, count 2 2006.257.18:52:47.60#ibcon#enter sib2, iclass 32, count 2 2006.257.18:52:47.60#ibcon#flushed, iclass 32, count 2 2006.257.18:52:47.60#ibcon#about to write, iclass 32, count 2 2006.257.18:52:47.60#ibcon#wrote, iclass 32, count 2 2006.257.18:52:47.60#ibcon#about to read 3, iclass 32, count 2 2006.257.18:52:47.63#ibcon#read 3, iclass 32, count 2 2006.257.18:52:47.63#ibcon#about to read 4, iclass 32, count 2 2006.257.18:52:47.63#ibcon#read 4, iclass 32, count 2 2006.257.18:52:47.63#ibcon#about to read 5, iclass 32, count 2 2006.257.18:52:47.63#ibcon#read 5, iclass 32, count 2 2006.257.18:52:47.63#ibcon#about to read 6, iclass 32, count 2 2006.257.18:52:47.63#ibcon#read 6, iclass 32, count 2 2006.257.18:52:47.63#ibcon#end of sib2, iclass 32, count 2 2006.257.18:52:47.63#ibcon#*after write, iclass 32, count 2 2006.257.18:52:47.63#ibcon#*before return 0, iclass 32, count 2 2006.257.18:52:47.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:47.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.18:52:47.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.18:52:47.63#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:47.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:47.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:47.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:47.75#ibcon#enter wrdev, iclass 32, count 0 2006.257.18:52:47.75#ibcon#first serial, iclass 32, count 0 2006.257.18:52:47.75#ibcon#enter sib2, iclass 32, count 0 2006.257.18:52:47.75#ibcon#flushed, iclass 32, count 0 2006.257.18:52:47.75#ibcon#about to write, iclass 32, count 0 2006.257.18:52:47.75#ibcon#wrote, iclass 32, count 0 2006.257.18:52:47.75#ibcon#about to read 3, iclass 32, count 0 2006.257.18:52:47.77#ibcon#read 3, iclass 32, count 0 2006.257.18:52:47.77#ibcon#about to read 4, iclass 32, count 0 2006.257.18:52:47.77#ibcon#read 4, iclass 32, count 0 2006.257.18:52:47.77#ibcon#about to read 5, iclass 32, count 0 2006.257.18:52:47.77#ibcon#read 5, iclass 32, count 0 2006.257.18:52:47.77#ibcon#about to read 6, iclass 32, count 0 2006.257.18:52:47.77#ibcon#read 6, iclass 32, count 0 2006.257.18:52:47.77#ibcon#end of sib2, iclass 32, count 0 2006.257.18:52:47.77#ibcon#*mode == 0, iclass 32, count 0 2006.257.18:52:47.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.18:52:47.77#ibcon#[27=USB\r\n] 2006.257.18:52:47.77#ibcon#*before write, iclass 32, count 0 2006.257.18:52:47.77#ibcon#enter sib2, iclass 32, count 0 2006.257.18:52:47.77#ibcon#flushed, iclass 32, count 0 2006.257.18:52:47.77#ibcon#about to write, iclass 32, count 0 2006.257.18:52:47.77#ibcon#wrote, iclass 32, count 0 2006.257.18:52:47.77#ibcon#about to read 3, iclass 32, count 0 2006.257.18:52:47.80#ibcon#read 3, iclass 32, count 0 2006.257.18:52:47.80#ibcon#about to read 4, iclass 32, count 0 2006.257.18:52:47.80#ibcon#read 4, iclass 32, count 0 2006.257.18:52:47.80#ibcon#about to read 5, iclass 32, count 0 2006.257.18:52:47.80#ibcon#read 5, iclass 32, count 0 2006.257.18:52:47.80#ibcon#about to read 6, iclass 32, count 0 2006.257.18:52:47.80#ibcon#read 6, iclass 32, count 0 2006.257.18:52:47.80#ibcon#end of sib2, iclass 32, count 0 2006.257.18:52:47.80#ibcon#*after write, iclass 32, count 0 2006.257.18:52:47.80#ibcon#*before return 0, iclass 32, count 0 2006.257.18:52:47.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:47.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.18:52:47.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.18:52:47.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.18:52:47.80$vck44/vblo=6,719.99 2006.257.18:52:47.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.18:52:47.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.18:52:47.80#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:47.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:47.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:47.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:47.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.18:52:47.80#ibcon#first serial, iclass 34, count 0 2006.257.18:52:47.80#ibcon#enter sib2, iclass 34, count 0 2006.257.18:52:47.80#ibcon#flushed, iclass 34, count 0 2006.257.18:52:47.80#ibcon#about to write, iclass 34, count 0 2006.257.18:52:47.80#ibcon#wrote, iclass 34, count 0 2006.257.18:52:47.80#ibcon#about to read 3, iclass 34, count 0 2006.257.18:52:47.82#ibcon#read 3, iclass 34, count 0 2006.257.18:52:47.82#ibcon#about to read 4, iclass 34, count 0 2006.257.18:52:47.82#ibcon#read 4, iclass 34, count 0 2006.257.18:52:47.82#ibcon#about to read 5, iclass 34, count 0 2006.257.18:52:47.82#ibcon#read 5, iclass 34, count 0 2006.257.18:52:47.82#ibcon#about to read 6, iclass 34, count 0 2006.257.18:52:47.82#ibcon#read 6, iclass 34, count 0 2006.257.18:52:47.82#ibcon#end of sib2, iclass 34, count 0 2006.257.18:52:47.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.18:52:47.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.18:52:47.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:52:47.82#ibcon#*before write, iclass 34, count 0 2006.257.18:52:47.82#ibcon#enter sib2, iclass 34, count 0 2006.257.18:52:47.82#ibcon#flushed, iclass 34, count 0 2006.257.18:52:47.82#ibcon#about to write, iclass 34, count 0 2006.257.18:52:47.82#ibcon#wrote, iclass 34, count 0 2006.257.18:52:47.82#ibcon#about to read 3, iclass 34, count 0 2006.257.18:52:47.86#ibcon#read 3, iclass 34, count 0 2006.257.18:52:47.86#ibcon#about to read 4, iclass 34, count 0 2006.257.18:52:47.86#ibcon#read 4, iclass 34, count 0 2006.257.18:52:47.86#ibcon#about to read 5, iclass 34, count 0 2006.257.18:52:47.86#ibcon#read 5, iclass 34, count 0 2006.257.18:52:47.86#ibcon#about to read 6, iclass 34, count 0 2006.257.18:52:47.86#ibcon#read 6, iclass 34, count 0 2006.257.18:52:47.86#ibcon#end of sib2, iclass 34, count 0 2006.257.18:52:47.86#ibcon#*after write, iclass 34, count 0 2006.257.18:52:47.86#ibcon#*before return 0, iclass 34, count 0 2006.257.18:52:47.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:47.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.18:52:47.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.18:52:47.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.18:52:47.86$vck44/vb=6,4 2006.257.18:52:47.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.18:52:47.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.18:52:47.86#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:47.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:47.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:47.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:47.92#ibcon#enter wrdev, iclass 36, count 2 2006.257.18:52:47.92#ibcon#first serial, iclass 36, count 2 2006.257.18:52:47.92#ibcon#enter sib2, iclass 36, count 2 2006.257.18:52:47.92#ibcon#flushed, iclass 36, count 2 2006.257.18:52:47.92#ibcon#about to write, iclass 36, count 2 2006.257.18:52:47.92#ibcon#wrote, iclass 36, count 2 2006.257.18:52:47.92#ibcon#about to read 3, iclass 36, count 2 2006.257.18:52:47.94#ibcon#read 3, iclass 36, count 2 2006.257.18:52:47.94#ibcon#about to read 4, iclass 36, count 2 2006.257.18:52:47.94#ibcon#read 4, iclass 36, count 2 2006.257.18:52:47.94#ibcon#about to read 5, iclass 36, count 2 2006.257.18:52:47.94#ibcon#read 5, iclass 36, count 2 2006.257.18:52:47.94#ibcon#about to read 6, iclass 36, count 2 2006.257.18:52:47.94#ibcon#read 6, iclass 36, count 2 2006.257.18:52:47.94#ibcon#end of sib2, iclass 36, count 2 2006.257.18:52:47.94#ibcon#*mode == 0, iclass 36, count 2 2006.257.18:52:47.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.18:52:47.94#ibcon#[27=AT06-04\r\n] 2006.257.18:52:47.94#ibcon#*before write, iclass 36, count 2 2006.257.18:52:47.94#ibcon#enter sib2, iclass 36, count 2 2006.257.18:52:47.94#ibcon#flushed, iclass 36, count 2 2006.257.18:52:47.94#ibcon#about to write, iclass 36, count 2 2006.257.18:52:47.94#ibcon#wrote, iclass 36, count 2 2006.257.18:52:47.94#ibcon#about to read 3, iclass 36, count 2 2006.257.18:52:47.97#ibcon#read 3, iclass 36, count 2 2006.257.18:52:47.97#ibcon#about to read 4, iclass 36, count 2 2006.257.18:52:47.97#ibcon#read 4, iclass 36, count 2 2006.257.18:52:47.97#ibcon#about to read 5, iclass 36, count 2 2006.257.18:52:47.97#ibcon#read 5, iclass 36, count 2 2006.257.18:52:47.97#ibcon#about to read 6, iclass 36, count 2 2006.257.18:52:47.97#ibcon#read 6, iclass 36, count 2 2006.257.18:52:47.97#ibcon#end of sib2, iclass 36, count 2 2006.257.18:52:47.97#ibcon#*after write, iclass 36, count 2 2006.257.18:52:47.97#ibcon#*before return 0, iclass 36, count 2 2006.257.18:52:47.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:47.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.18:52:47.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.18:52:47.97#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:47.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:48.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:48.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:48.09#ibcon#enter wrdev, iclass 36, count 0 2006.257.18:52:48.09#ibcon#first serial, iclass 36, count 0 2006.257.18:52:48.09#ibcon#enter sib2, iclass 36, count 0 2006.257.18:52:48.09#ibcon#flushed, iclass 36, count 0 2006.257.18:52:48.09#ibcon#about to write, iclass 36, count 0 2006.257.18:52:48.09#ibcon#wrote, iclass 36, count 0 2006.257.18:52:48.09#ibcon#about to read 3, iclass 36, count 0 2006.257.18:52:48.11#ibcon#read 3, iclass 36, count 0 2006.257.18:52:48.11#ibcon#about to read 4, iclass 36, count 0 2006.257.18:52:48.11#ibcon#read 4, iclass 36, count 0 2006.257.18:52:48.11#ibcon#about to read 5, iclass 36, count 0 2006.257.18:52:48.11#ibcon#read 5, iclass 36, count 0 2006.257.18:52:48.11#ibcon#about to read 6, iclass 36, count 0 2006.257.18:52:48.11#ibcon#read 6, iclass 36, count 0 2006.257.18:52:48.11#ibcon#end of sib2, iclass 36, count 0 2006.257.18:52:48.11#ibcon#*mode == 0, iclass 36, count 0 2006.257.18:52:48.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.18:52:48.11#ibcon#[27=USB\r\n] 2006.257.18:52:48.11#ibcon#*before write, iclass 36, count 0 2006.257.18:52:48.11#ibcon#enter sib2, iclass 36, count 0 2006.257.18:52:48.11#ibcon#flushed, iclass 36, count 0 2006.257.18:52:48.11#ibcon#about to write, iclass 36, count 0 2006.257.18:52:48.11#ibcon#wrote, iclass 36, count 0 2006.257.18:52:48.11#ibcon#about to read 3, iclass 36, count 0 2006.257.18:52:48.14#ibcon#read 3, iclass 36, count 0 2006.257.18:52:48.14#ibcon#about to read 4, iclass 36, count 0 2006.257.18:52:48.14#ibcon#read 4, iclass 36, count 0 2006.257.18:52:48.14#ibcon#about to read 5, iclass 36, count 0 2006.257.18:52:48.14#ibcon#read 5, iclass 36, count 0 2006.257.18:52:48.14#ibcon#about to read 6, iclass 36, count 0 2006.257.18:52:48.14#ibcon#read 6, iclass 36, count 0 2006.257.18:52:48.14#ibcon#end of sib2, iclass 36, count 0 2006.257.18:52:48.14#ibcon#*after write, iclass 36, count 0 2006.257.18:52:48.14#ibcon#*before return 0, iclass 36, count 0 2006.257.18:52:48.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:48.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.18:52:48.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.18:52:48.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.18:52:48.14$vck44/vblo=7,734.99 2006.257.18:52:48.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.18:52:48.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.18:52:48.14#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:48.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:48.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:48.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:48.14#ibcon#enter wrdev, iclass 38, count 0 2006.257.18:52:48.14#ibcon#first serial, iclass 38, count 0 2006.257.18:52:48.14#ibcon#enter sib2, iclass 38, count 0 2006.257.18:52:48.14#ibcon#flushed, iclass 38, count 0 2006.257.18:52:48.14#ibcon#about to write, iclass 38, count 0 2006.257.18:52:48.14#ibcon#wrote, iclass 38, count 0 2006.257.18:52:48.14#ibcon#about to read 3, iclass 38, count 0 2006.257.18:52:48.16#ibcon#read 3, iclass 38, count 0 2006.257.18:52:48.16#ibcon#about to read 4, iclass 38, count 0 2006.257.18:52:48.16#ibcon#read 4, iclass 38, count 0 2006.257.18:52:48.16#ibcon#about to read 5, iclass 38, count 0 2006.257.18:52:48.16#ibcon#read 5, iclass 38, count 0 2006.257.18:52:48.16#ibcon#about to read 6, iclass 38, count 0 2006.257.18:52:48.16#ibcon#read 6, iclass 38, count 0 2006.257.18:52:48.16#ibcon#end of sib2, iclass 38, count 0 2006.257.18:52:48.16#ibcon#*mode == 0, iclass 38, count 0 2006.257.18:52:48.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.18:52:48.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:52:48.16#ibcon#*before write, iclass 38, count 0 2006.257.18:52:48.16#ibcon#enter sib2, iclass 38, count 0 2006.257.18:52:48.16#ibcon#flushed, iclass 38, count 0 2006.257.18:52:48.16#ibcon#about to write, iclass 38, count 0 2006.257.18:52:48.16#ibcon#wrote, iclass 38, count 0 2006.257.18:52:48.16#ibcon#about to read 3, iclass 38, count 0 2006.257.18:52:48.20#ibcon#read 3, iclass 38, count 0 2006.257.18:52:48.20#ibcon#about to read 4, iclass 38, count 0 2006.257.18:52:48.20#ibcon#read 4, iclass 38, count 0 2006.257.18:52:48.20#ibcon#about to read 5, iclass 38, count 0 2006.257.18:52:48.20#ibcon#read 5, iclass 38, count 0 2006.257.18:52:48.20#ibcon#about to read 6, iclass 38, count 0 2006.257.18:52:48.20#ibcon#read 6, iclass 38, count 0 2006.257.18:52:48.20#ibcon#end of sib2, iclass 38, count 0 2006.257.18:52:48.20#ibcon#*after write, iclass 38, count 0 2006.257.18:52:48.20#ibcon#*before return 0, iclass 38, count 0 2006.257.18:52:48.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:48.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.18:52:48.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.18:52:48.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.18:52:48.20$vck44/vb=7,4 2006.257.18:52:48.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.18:52:48.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.18:52:48.20#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:48.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:48.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:48.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:48.26#ibcon#enter wrdev, iclass 40, count 2 2006.257.18:52:48.26#ibcon#first serial, iclass 40, count 2 2006.257.18:52:48.26#ibcon#enter sib2, iclass 40, count 2 2006.257.18:52:48.26#ibcon#flushed, iclass 40, count 2 2006.257.18:52:48.26#ibcon#about to write, iclass 40, count 2 2006.257.18:52:48.26#ibcon#wrote, iclass 40, count 2 2006.257.18:52:48.26#ibcon#about to read 3, iclass 40, count 2 2006.257.18:52:48.28#ibcon#read 3, iclass 40, count 2 2006.257.18:52:48.28#ibcon#about to read 4, iclass 40, count 2 2006.257.18:52:48.28#ibcon#read 4, iclass 40, count 2 2006.257.18:52:48.28#ibcon#about to read 5, iclass 40, count 2 2006.257.18:52:48.28#ibcon#read 5, iclass 40, count 2 2006.257.18:52:48.28#ibcon#about to read 6, iclass 40, count 2 2006.257.18:52:48.28#ibcon#read 6, iclass 40, count 2 2006.257.18:52:48.28#ibcon#end of sib2, iclass 40, count 2 2006.257.18:52:48.28#ibcon#*mode == 0, iclass 40, count 2 2006.257.18:52:48.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.18:52:48.28#ibcon#[27=AT07-04\r\n] 2006.257.18:52:48.28#ibcon#*before write, iclass 40, count 2 2006.257.18:52:48.28#ibcon#enter sib2, iclass 40, count 2 2006.257.18:52:48.28#ibcon#flushed, iclass 40, count 2 2006.257.18:52:48.28#ibcon#about to write, iclass 40, count 2 2006.257.18:52:48.28#ibcon#wrote, iclass 40, count 2 2006.257.18:52:48.28#ibcon#about to read 3, iclass 40, count 2 2006.257.18:52:48.31#ibcon#read 3, iclass 40, count 2 2006.257.18:52:48.31#ibcon#about to read 4, iclass 40, count 2 2006.257.18:52:48.31#ibcon#read 4, iclass 40, count 2 2006.257.18:52:48.31#ibcon#about to read 5, iclass 40, count 2 2006.257.18:52:48.31#ibcon#read 5, iclass 40, count 2 2006.257.18:52:48.31#ibcon#about to read 6, iclass 40, count 2 2006.257.18:52:48.31#ibcon#read 6, iclass 40, count 2 2006.257.18:52:48.31#ibcon#end of sib2, iclass 40, count 2 2006.257.18:52:48.31#ibcon#*after write, iclass 40, count 2 2006.257.18:52:48.31#ibcon#*before return 0, iclass 40, count 2 2006.257.18:52:48.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:48.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.18:52:48.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.18:52:48.31#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:48.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:48.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:48.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:48.43#ibcon#enter wrdev, iclass 40, count 0 2006.257.18:52:48.43#ibcon#first serial, iclass 40, count 0 2006.257.18:52:48.43#ibcon#enter sib2, iclass 40, count 0 2006.257.18:52:48.43#ibcon#flushed, iclass 40, count 0 2006.257.18:52:48.43#ibcon#about to write, iclass 40, count 0 2006.257.18:52:48.43#ibcon#wrote, iclass 40, count 0 2006.257.18:52:48.43#ibcon#about to read 3, iclass 40, count 0 2006.257.18:52:48.45#ibcon#read 3, iclass 40, count 0 2006.257.18:52:48.45#ibcon#about to read 4, iclass 40, count 0 2006.257.18:52:48.45#ibcon#read 4, iclass 40, count 0 2006.257.18:52:48.45#ibcon#about to read 5, iclass 40, count 0 2006.257.18:52:48.45#ibcon#read 5, iclass 40, count 0 2006.257.18:52:48.45#ibcon#about to read 6, iclass 40, count 0 2006.257.18:52:48.45#ibcon#read 6, iclass 40, count 0 2006.257.18:52:48.45#ibcon#end of sib2, iclass 40, count 0 2006.257.18:52:48.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.18:52:48.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.18:52:48.45#ibcon#[27=USB\r\n] 2006.257.18:52:48.45#ibcon#*before write, iclass 40, count 0 2006.257.18:52:48.45#ibcon#enter sib2, iclass 40, count 0 2006.257.18:52:48.45#ibcon#flushed, iclass 40, count 0 2006.257.18:52:48.45#ibcon#about to write, iclass 40, count 0 2006.257.18:52:48.45#ibcon#wrote, iclass 40, count 0 2006.257.18:52:48.45#ibcon#about to read 3, iclass 40, count 0 2006.257.18:52:48.48#ibcon#read 3, iclass 40, count 0 2006.257.18:52:48.48#ibcon#about to read 4, iclass 40, count 0 2006.257.18:52:48.48#ibcon#read 4, iclass 40, count 0 2006.257.18:52:48.48#ibcon#about to read 5, iclass 40, count 0 2006.257.18:52:48.48#ibcon#read 5, iclass 40, count 0 2006.257.18:52:48.48#ibcon#about to read 6, iclass 40, count 0 2006.257.18:52:48.48#ibcon#read 6, iclass 40, count 0 2006.257.18:52:48.48#ibcon#end of sib2, iclass 40, count 0 2006.257.18:52:48.48#ibcon#*after write, iclass 40, count 0 2006.257.18:52:48.48#ibcon#*before return 0, iclass 40, count 0 2006.257.18:52:48.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:48.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.18:52:48.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.18:52:48.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.18:52:48.48$vck44/vblo=8,744.99 2006.257.18:52:48.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.18:52:48.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.18:52:48.48#ibcon#ireg 17 cls_cnt 0 2006.257.18:52:48.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:48.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:48.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:48.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.18:52:48.48#ibcon#first serial, iclass 4, count 0 2006.257.18:52:48.48#ibcon#enter sib2, iclass 4, count 0 2006.257.18:52:48.48#ibcon#flushed, iclass 4, count 0 2006.257.18:52:48.48#ibcon#about to write, iclass 4, count 0 2006.257.18:52:48.48#ibcon#wrote, iclass 4, count 0 2006.257.18:52:48.48#ibcon#about to read 3, iclass 4, count 0 2006.257.18:52:48.50#ibcon#read 3, iclass 4, count 0 2006.257.18:52:48.50#ibcon#about to read 4, iclass 4, count 0 2006.257.18:52:48.50#ibcon#read 4, iclass 4, count 0 2006.257.18:52:48.50#ibcon#about to read 5, iclass 4, count 0 2006.257.18:52:48.50#ibcon#read 5, iclass 4, count 0 2006.257.18:52:48.50#ibcon#about to read 6, iclass 4, count 0 2006.257.18:52:48.50#ibcon#read 6, iclass 4, count 0 2006.257.18:52:48.50#ibcon#end of sib2, iclass 4, count 0 2006.257.18:52:48.50#ibcon#*mode == 0, iclass 4, count 0 2006.257.18:52:48.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.18:52:48.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:52:48.50#ibcon#*before write, iclass 4, count 0 2006.257.18:52:48.50#ibcon#enter sib2, iclass 4, count 0 2006.257.18:52:48.50#ibcon#flushed, iclass 4, count 0 2006.257.18:52:48.50#ibcon#about to write, iclass 4, count 0 2006.257.18:52:48.50#ibcon#wrote, iclass 4, count 0 2006.257.18:52:48.50#ibcon#about to read 3, iclass 4, count 0 2006.257.18:52:48.54#ibcon#read 3, iclass 4, count 0 2006.257.18:52:48.54#ibcon#about to read 4, iclass 4, count 0 2006.257.18:52:48.54#ibcon#read 4, iclass 4, count 0 2006.257.18:52:48.54#ibcon#about to read 5, iclass 4, count 0 2006.257.18:52:48.54#ibcon#read 5, iclass 4, count 0 2006.257.18:52:48.54#ibcon#about to read 6, iclass 4, count 0 2006.257.18:52:48.54#ibcon#read 6, iclass 4, count 0 2006.257.18:52:48.54#ibcon#end of sib2, iclass 4, count 0 2006.257.18:52:48.54#ibcon#*after write, iclass 4, count 0 2006.257.18:52:48.54#ibcon#*before return 0, iclass 4, count 0 2006.257.18:52:48.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:48.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.18:52:48.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.18:52:48.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.18:52:48.54$vck44/vb=8,4 2006.257.18:52:48.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.18:52:48.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.18:52:48.54#ibcon#ireg 11 cls_cnt 2 2006.257.18:52:48.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:48.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:48.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:48.60#ibcon#enter wrdev, iclass 6, count 2 2006.257.18:52:48.60#ibcon#first serial, iclass 6, count 2 2006.257.18:52:48.60#ibcon#enter sib2, iclass 6, count 2 2006.257.18:52:48.60#ibcon#flushed, iclass 6, count 2 2006.257.18:52:48.60#ibcon#about to write, iclass 6, count 2 2006.257.18:52:48.60#ibcon#wrote, iclass 6, count 2 2006.257.18:52:48.60#ibcon#about to read 3, iclass 6, count 2 2006.257.18:52:48.62#ibcon#read 3, iclass 6, count 2 2006.257.18:52:48.62#ibcon#about to read 4, iclass 6, count 2 2006.257.18:52:48.62#ibcon#read 4, iclass 6, count 2 2006.257.18:52:48.62#ibcon#about to read 5, iclass 6, count 2 2006.257.18:52:48.62#ibcon#read 5, iclass 6, count 2 2006.257.18:52:48.62#ibcon#about to read 6, iclass 6, count 2 2006.257.18:52:48.62#ibcon#read 6, iclass 6, count 2 2006.257.18:52:48.62#ibcon#end of sib2, iclass 6, count 2 2006.257.18:52:48.62#ibcon#*mode == 0, iclass 6, count 2 2006.257.18:52:48.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.18:52:48.62#ibcon#[27=AT08-04\r\n] 2006.257.18:52:48.62#ibcon#*before write, iclass 6, count 2 2006.257.18:52:48.62#ibcon#enter sib2, iclass 6, count 2 2006.257.18:52:48.62#ibcon#flushed, iclass 6, count 2 2006.257.18:52:48.62#ibcon#about to write, iclass 6, count 2 2006.257.18:52:48.62#ibcon#wrote, iclass 6, count 2 2006.257.18:52:48.62#ibcon#about to read 3, iclass 6, count 2 2006.257.18:52:48.65#ibcon#read 3, iclass 6, count 2 2006.257.18:52:48.65#ibcon#about to read 4, iclass 6, count 2 2006.257.18:52:48.65#ibcon#read 4, iclass 6, count 2 2006.257.18:52:48.65#ibcon#about to read 5, iclass 6, count 2 2006.257.18:52:48.65#ibcon#read 5, iclass 6, count 2 2006.257.18:52:48.65#ibcon#about to read 6, iclass 6, count 2 2006.257.18:52:48.65#ibcon#read 6, iclass 6, count 2 2006.257.18:52:48.65#ibcon#end of sib2, iclass 6, count 2 2006.257.18:52:48.65#ibcon#*after write, iclass 6, count 2 2006.257.18:52:48.65#ibcon#*before return 0, iclass 6, count 2 2006.257.18:52:48.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:48.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.18:52:48.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.18:52:48.65#ibcon#ireg 7 cls_cnt 0 2006.257.18:52:48.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:48.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:48.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:48.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.18:52:48.77#ibcon#first serial, iclass 6, count 0 2006.257.18:52:48.77#ibcon#enter sib2, iclass 6, count 0 2006.257.18:52:48.77#ibcon#flushed, iclass 6, count 0 2006.257.18:52:48.77#ibcon#about to write, iclass 6, count 0 2006.257.18:52:48.77#ibcon#wrote, iclass 6, count 0 2006.257.18:52:48.77#ibcon#about to read 3, iclass 6, count 0 2006.257.18:52:48.79#ibcon#read 3, iclass 6, count 0 2006.257.18:52:48.79#ibcon#about to read 4, iclass 6, count 0 2006.257.18:52:48.79#ibcon#read 4, iclass 6, count 0 2006.257.18:52:48.79#ibcon#about to read 5, iclass 6, count 0 2006.257.18:52:48.79#ibcon#read 5, iclass 6, count 0 2006.257.18:52:48.79#ibcon#about to read 6, iclass 6, count 0 2006.257.18:52:48.79#ibcon#read 6, iclass 6, count 0 2006.257.18:52:48.79#ibcon#end of sib2, iclass 6, count 0 2006.257.18:52:48.79#ibcon#*mode == 0, iclass 6, count 0 2006.257.18:52:48.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.18:52:48.79#ibcon#[27=USB\r\n] 2006.257.18:52:48.79#ibcon#*before write, iclass 6, count 0 2006.257.18:52:48.79#ibcon#enter sib2, iclass 6, count 0 2006.257.18:52:48.79#ibcon#flushed, iclass 6, count 0 2006.257.18:52:48.79#ibcon#about to write, iclass 6, count 0 2006.257.18:52:48.79#ibcon#wrote, iclass 6, count 0 2006.257.18:52:48.79#ibcon#about to read 3, iclass 6, count 0 2006.257.18:52:48.82#ibcon#read 3, iclass 6, count 0 2006.257.18:52:48.82#ibcon#about to read 4, iclass 6, count 0 2006.257.18:52:48.82#ibcon#read 4, iclass 6, count 0 2006.257.18:52:48.82#ibcon#about to read 5, iclass 6, count 0 2006.257.18:52:48.82#ibcon#read 5, iclass 6, count 0 2006.257.18:52:48.82#ibcon#about to read 6, iclass 6, count 0 2006.257.18:52:48.82#ibcon#read 6, iclass 6, count 0 2006.257.18:52:48.82#ibcon#end of sib2, iclass 6, count 0 2006.257.18:52:48.82#ibcon#*after write, iclass 6, count 0 2006.257.18:52:48.82#ibcon#*before return 0, iclass 6, count 0 2006.257.18:52:48.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:48.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.18:52:48.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.18:52:48.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.18:52:48.82$vck44/vabw=wide 2006.257.18:52:48.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.18:52:48.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.18:52:48.82#ibcon#ireg 8 cls_cnt 0 2006.257.18:52:48.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:48.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:48.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:48.82#ibcon#enter wrdev, iclass 10, count 0 2006.257.18:52:48.82#ibcon#first serial, iclass 10, count 0 2006.257.18:52:48.82#ibcon#enter sib2, iclass 10, count 0 2006.257.18:52:48.82#ibcon#flushed, iclass 10, count 0 2006.257.18:52:48.82#ibcon#about to write, iclass 10, count 0 2006.257.18:52:48.82#ibcon#wrote, iclass 10, count 0 2006.257.18:52:48.82#ibcon#about to read 3, iclass 10, count 0 2006.257.18:52:48.84#ibcon#read 3, iclass 10, count 0 2006.257.18:52:48.84#ibcon#about to read 4, iclass 10, count 0 2006.257.18:52:48.84#ibcon#read 4, iclass 10, count 0 2006.257.18:52:48.84#ibcon#about to read 5, iclass 10, count 0 2006.257.18:52:48.84#ibcon#read 5, iclass 10, count 0 2006.257.18:52:48.84#ibcon#about to read 6, iclass 10, count 0 2006.257.18:52:48.84#ibcon#read 6, iclass 10, count 0 2006.257.18:52:48.84#ibcon#end of sib2, iclass 10, count 0 2006.257.18:52:48.84#ibcon#*mode == 0, iclass 10, count 0 2006.257.18:52:48.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.18:52:48.84#ibcon#[25=BW32\r\n] 2006.257.18:52:48.84#ibcon#*before write, iclass 10, count 0 2006.257.18:52:48.84#ibcon#enter sib2, iclass 10, count 0 2006.257.18:52:48.84#ibcon#flushed, iclass 10, count 0 2006.257.18:52:48.84#ibcon#about to write, iclass 10, count 0 2006.257.18:52:48.84#ibcon#wrote, iclass 10, count 0 2006.257.18:52:48.84#ibcon#about to read 3, iclass 10, count 0 2006.257.18:52:48.87#ibcon#read 3, iclass 10, count 0 2006.257.18:52:48.87#ibcon#about to read 4, iclass 10, count 0 2006.257.18:52:48.87#ibcon#read 4, iclass 10, count 0 2006.257.18:52:48.87#ibcon#about to read 5, iclass 10, count 0 2006.257.18:52:48.87#ibcon#read 5, iclass 10, count 0 2006.257.18:52:48.87#ibcon#about to read 6, iclass 10, count 0 2006.257.18:52:48.87#ibcon#read 6, iclass 10, count 0 2006.257.18:52:48.87#ibcon#end of sib2, iclass 10, count 0 2006.257.18:52:48.87#ibcon#*after write, iclass 10, count 0 2006.257.18:52:48.87#ibcon#*before return 0, iclass 10, count 0 2006.257.18:52:48.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:48.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.18:52:48.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.18:52:48.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.18:52:48.87$vck44/vbbw=wide 2006.257.18:52:48.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.18:52:48.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.18:52:48.87#ibcon#ireg 8 cls_cnt 0 2006.257.18:52:48.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:52:48.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:52:48.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:52:48.94#ibcon#enter wrdev, iclass 12, count 0 2006.257.18:52:48.94#ibcon#first serial, iclass 12, count 0 2006.257.18:52:48.94#ibcon#enter sib2, iclass 12, count 0 2006.257.18:52:48.94#ibcon#flushed, iclass 12, count 0 2006.257.18:52:48.94#ibcon#about to write, iclass 12, count 0 2006.257.18:52:48.94#ibcon#wrote, iclass 12, count 0 2006.257.18:52:48.94#ibcon#about to read 3, iclass 12, count 0 2006.257.18:52:48.96#ibcon#read 3, iclass 12, count 0 2006.257.18:52:48.96#ibcon#about to read 4, iclass 12, count 0 2006.257.18:52:48.96#ibcon#read 4, iclass 12, count 0 2006.257.18:52:48.96#ibcon#about to read 5, iclass 12, count 0 2006.257.18:52:48.96#ibcon#read 5, iclass 12, count 0 2006.257.18:52:48.96#ibcon#about to read 6, iclass 12, count 0 2006.257.18:52:48.96#ibcon#read 6, iclass 12, count 0 2006.257.18:52:48.96#ibcon#end of sib2, iclass 12, count 0 2006.257.18:52:48.96#ibcon#*mode == 0, iclass 12, count 0 2006.257.18:52:48.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.18:52:48.96#ibcon#[27=BW32\r\n] 2006.257.18:52:48.96#ibcon#*before write, iclass 12, count 0 2006.257.18:52:48.96#ibcon#enter sib2, iclass 12, count 0 2006.257.18:52:48.96#ibcon#flushed, iclass 12, count 0 2006.257.18:52:48.96#ibcon#about to write, iclass 12, count 0 2006.257.18:52:48.96#ibcon#wrote, iclass 12, count 0 2006.257.18:52:48.96#ibcon#about to read 3, iclass 12, count 0 2006.257.18:52:48.99#ibcon#read 3, iclass 12, count 0 2006.257.18:52:48.99#ibcon#about to read 4, iclass 12, count 0 2006.257.18:52:48.99#ibcon#read 4, iclass 12, count 0 2006.257.18:52:48.99#ibcon#about to read 5, iclass 12, count 0 2006.257.18:52:48.99#ibcon#read 5, iclass 12, count 0 2006.257.18:52:48.99#ibcon#about to read 6, iclass 12, count 0 2006.257.18:52:48.99#ibcon#read 6, iclass 12, count 0 2006.257.18:52:48.99#ibcon#end of sib2, iclass 12, count 0 2006.257.18:52:48.99#ibcon#*after write, iclass 12, count 0 2006.257.18:52:48.99#ibcon#*before return 0, iclass 12, count 0 2006.257.18:52:48.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:52:48.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.18:52:48.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.18:52:48.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.18:52:48.99$setupk4/ifdk4 2006.257.18:52:48.99$ifdk4/lo= 2006.257.18:52:48.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:52:48.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:52:48.99$ifdk4/patch= 2006.257.18:52:48.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:52:48.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:52:48.99$setupk4/!*+20s 2006.257.18:52:54.23#abcon#<5=/14 1.5 3.7 17.33 971014.3\r\n> 2006.257.18:52:54.25#abcon#{5=INTERFACE CLEAR} 2006.257.18:52:54.31#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:53:03.49$setupk4/"tpicd 2006.257.18:53:03.49$setupk4/echo=off 2006.257.18:53:03.49$setupk4/xlog=off 2006.257.18:53:03.49:!2006.257.18:56:12 2006.257.18:53:21.13#trakl#Source acquired 2006.257.18:53:21.13#flagr#flagr/antenna,acquired 2006.257.18:56:12.00:preob 2006.257.18:56:13.14/onsource/TRACKING 2006.257.18:56:13.14:!2006.257.18:56:22 2006.257.18:56:22.00:"tape 2006.257.18:56:22.00:"st=record 2006.257.18:56:22.00:data_valid=on 2006.257.18:56:22.00:midob 2006.257.18:56:22.14/onsource/TRACKING 2006.257.18:56:22.14/wx/17.36,1014.3,96 2006.257.18:56:22.20/cable/+6.4861E-03 2006.257.18:56:23.29/va/01,08,usb,yes,32,34 2006.257.18:56:23.29/va/02,07,usb,yes,35,35 2006.257.18:56:23.29/va/03,08,usb,yes,31,33 2006.257.18:56:23.29/va/04,07,usb,yes,36,37 2006.257.18:56:23.29/va/05,04,usb,yes,32,32 2006.257.18:56:23.29/va/06,04,usb,yes,35,35 2006.257.18:56:23.29/va/07,04,usb,yes,36,36 2006.257.18:56:23.29/va/08,04,usb,yes,30,37 2006.257.18:56:23.52/valo/01,524.99,yes,locked 2006.257.18:56:23.52/valo/02,534.99,yes,locked 2006.257.18:56:23.52/valo/03,564.99,yes,locked 2006.257.18:56:23.52/valo/04,624.99,yes,locked 2006.257.18:56:23.52/valo/05,734.99,yes,locked 2006.257.18:56:23.52/valo/06,814.99,yes,locked 2006.257.18:56:23.52/valo/07,864.99,yes,locked 2006.257.18:56:23.52/valo/08,884.99,yes,locked 2006.257.18:56:24.61/vb/01,04,usb,yes,30,28 2006.257.18:56:24.61/vb/02,05,usb,yes,28,28 2006.257.18:56:24.61/vb/03,04,usb,yes,29,32 2006.257.18:56:24.61/vb/04,05,usb,yes,30,29 2006.257.18:56:24.61/vb/05,04,usb,yes,26,29 2006.257.18:56:24.61/vb/06,04,usb,yes,31,27 2006.257.18:56:24.61/vb/07,04,usb,yes,30,30 2006.257.18:56:24.61/vb/08,04,usb,yes,28,31 2006.257.18:56:24.85/vblo/01,629.99,yes,locked 2006.257.18:56:24.85/vblo/02,634.99,yes,locked 2006.257.18:56:24.85/vblo/03,649.99,yes,locked 2006.257.18:56:24.85/vblo/04,679.99,yes,locked 2006.257.18:56:24.85/vblo/05,709.99,yes,locked 2006.257.18:56:24.85/vblo/06,719.99,yes,locked 2006.257.18:56:24.85/vblo/07,734.99,yes,locked 2006.257.18:56:24.85/vblo/08,744.99,yes,locked 2006.257.18:56:25.00/vabw/8 2006.257.18:56:25.15/vbbw/8 2006.257.18:56:25.30/xfe/off,on,15.0 2006.257.18:56:25.67/ifatt/23,28,28,28 2006.257.18:56:26.07/fmout-gps/S +4.53E-07 2006.257.18:56:26.11:!2006.257.18:58:02 2006.257.18:58:02.00:data_valid=off 2006.257.18:58:02.00:"et 2006.257.18:58:02.01:!+3s 2006.257.18:58:05.02:"tape 2006.257.18:58:05.02:postob 2006.257.18:58:05.16/cable/+6.4855E-03 2006.257.18:58:05.16/wx/17.37,1014.3,96 2006.257.18:58:05.22/fmout-gps/S +4.52E-07 2006.257.18:58:05.22:scan_name=257-1859,jd0609,50 2006.257.18:58:05.23:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.257.18:58:07.14#flagr#flagr/antenna,new-source 2006.257.18:58:07.14:checkk5 2006.257.18:58:07.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.18:58:07.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.18:58:08.26/chk_autoobs//k5ts3/ autoobs is running! 2006.257.18:58:08.59/chk_autoobs//k5ts4/ autoobs is running! 2006.257.18:58:08.92/chk_obsdata//k5ts1/T2571856??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.18:58:09.26/chk_obsdata//k5ts2/T2571856??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.18:58:09.58/chk_obsdata//k5ts3/T2571856??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.18:58:09.92/chk_obsdata//k5ts4/T2571856??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.18:58:10.58/k5log//k5ts1_log_newline 2006.257.18:58:11.24/k5log//k5ts2_log_newline 2006.257.18:58:11.89/k5log//k5ts3_log_newline 2006.257.18:58:12.56/k5log//k5ts4_log_newline 2006.257.18:58:12.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.18:58:12.58:setupk4=1 2006.257.18:58:12.58$setupk4/echo=on 2006.257.18:58:12.58$setupk4/pcalon 2006.257.18:58:12.58$pcalon/"no phase cal control is implemented here 2006.257.18:58:12.58$setupk4/"tpicd=stop 2006.257.18:58:12.58$setupk4/"rec=synch_on 2006.257.18:58:12.58$setupk4/"rec_mode=128 2006.257.18:58:12.58$setupk4/!* 2006.257.18:58:12.58$setupk4/recpk4 2006.257.18:58:12.58$recpk4/recpatch= 2006.257.18:58:12.58$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.18:58:12.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.18:58:12.58$setupk4/vck44 2006.257.18:58:12.58$vck44/valo=1,524.99 2006.257.18:58:12.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.18:58:12.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.18:58:12.58#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:12.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:12.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:12.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:12.58#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:58:12.58#ibcon#first serial, iclass 37, count 0 2006.257.18:58:12.58#ibcon#enter sib2, iclass 37, count 0 2006.257.18:58:12.58#ibcon#flushed, iclass 37, count 0 2006.257.18:58:12.58#ibcon#about to write, iclass 37, count 0 2006.257.18:58:12.58#ibcon#wrote, iclass 37, count 0 2006.257.18:58:12.58#ibcon#about to read 3, iclass 37, count 0 2006.257.18:58:12.60#ibcon#read 3, iclass 37, count 0 2006.257.18:58:12.60#ibcon#about to read 4, iclass 37, count 0 2006.257.18:58:12.60#ibcon#read 4, iclass 37, count 0 2006.257.18:58:12.60#ibcon#about to read 5, iclass 37, count 0 2006.257.18:58:12.60#ibcon#read 5, iclass 37, count 0 2006.257.18:58:12.60#ibcon#about to read 6, iclass 37, count 0 2006.257.18:58:12.60#ibcon#read 6, iclass 37, count 0 2006.257.18:58:12.60#ibcon#end of sib2, iclass 37, count 0 2006.257.18:58:12.60#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:58:12.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:58:12.60#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.18:58:12.60#ibcon#*before write, iclass 37, count 0 2006.257.18:58:12.60#ibcon#enter sib2, iclass 37, count 0 2006.257.18:58:12.60#ibcon#flushed, iclass 37, count 0 2006.257.18:58:12.60#ibcon#about to write, iclass 37, count 0 2006.257.18:58:12.60#ibcon#wrote, iclass 37, count 0 2006.257.18:58:12.60#ibcon#about to read 3, iclass 37, count 0 2006.257.18:58:12.65#ibcon#read 3, iclass 37, count 0 2006.257.18:58:12.65#ibcon#about to read 4, iclass 37, count 0 2006.257.18:58:12.65#ibcon#read 4, iclass 37, count 0 2006.257.18:58:12.65#ibcon#about to read 5, iclass 37, count 0 2006.257.18:58:12.65#ibcon#read 5, iclass 37, count 0 2006.257.18:58:12.65#ibcon#about to read 6, iclass 37, count 0 2006.257.18:58:12.65#ibcon#read 6, iclass 37, count 0 2006.257.18:58:12.65#ibcon#end of sib2, iclass 37, count 0 2006.257.18:58:12.65#ibcon#*after write, iclass 37, count 0 2006.257.18:58:12.65#ibcon#*before return 0, iclass 37, count 0 2006.257.18:58:12.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:12.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:12.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:58:12.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:58:12.65$vck44/va=1,8 2006.257.18:58:12.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.18:58:12.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.18:58:12.65#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:12.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:12.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:12.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:12.65#ibcon#enter wrdev, iclass 39, count 2 2006.257.18:58:12.65#ibcon#first serial, iclass 39, count 2 2006.257.18:58:12.65#ibcon#enter sib2, iclass 39, count 2 2006.257.18:58:12.65#ibcon#flushed, iclass 39, count 2 2006.257.18:58:12.65#ibcon#about to write, iclass 39, count 2 2006.257.18:58:12.65#ibcon#wrote, iclass 39, count 2 2006.257.18:58:12.65#ibcon#about to read 3, iclass 39, count 2 2006.257.18:58:12.67#ibcon#read 3, iclass 39, count 2 2006.257.18:58:12.67#ibcon#about to read 4, iclass 39, count 2 2006.257.18:58:12.67#ibcon#read 4, iclass 39, count 2 2006.257.18:58:12.67#ibcon#about to read 5, iclass 39, count 2 2006.257.18:58:12.67#ibcon#read 5, iclass 39, count 2 2006.257.18:58:12.67#ibcon#about to read 6, iclass 39, count 2 2006.257.18:58:12.67#ibcon#read 6, iclass 39, count 2 2006.257.18:58:12.67#ibcon#end of sib2, iclass 39, count 2 2006.257.18:58:12.67#ibcon#*mode == 0, iclass 39, count 2 2006.257.18:58:12.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.18:58:12.67#ibcon#[25=AT01-08\r\n] 2006.257.18:58:12.67#ibcon#*before write, iclass 39, count 2 2006.257.18:58:12.67#ibcon#enter sib2, iclass 39, count 2 2006.257.18:58:12.67#ibcon#flushed, iclass 39, count 2 2006.257.18:58:12.67#ibcon#about to write, iclass 39, count 2 2006.257.18:58:12.67#ibcon#wrote, iclass 39, count 2 2006.257.18:58:12.67#ibcon#about to read 3, iclass 39, count 2 2006.257.18:58:12.70#ibcon#read 3, iclass 39, count 2 2006.257.18:58:12.70#ibcon#about to read 4, iclass 39, count 2 2006.257.18:58:12.70#ibcon#read 4, iclass 39, count 2 2006.257.18:58:12.70#ibcon#about to read 5, iclass 39, count 2 2006.257.18:58:12.70#ibcon#read 5, iclass 39, count 2 2006.257.18:58:12.70#ibcon#about to read 6, iclass 39, count 2 2006.257.18:58:12.70#ibcon#read 6, iclass 39, count 2 2006.257.18:58:12.70#ibcon#end of sib2, iclass 39, count 2 2006.257.18:58:12.70#ibcon#*after write, iclass 39, count 2 2006.257.18:58:12.70#ibcon#*before return 0, iclass 39, count 2 2006.257.18:58:12.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:12.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:12.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.18:58:12.70#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:12.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:12.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:12.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:12.82#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:58:12.82#ibcon#first serial, iclass 39, count 0 2006.257.18:58:12.82#ibcon#enter sib2, iclass 39, count 0 2006.257.18:58:12.82#ibcon#flushed, iclass 39, count 0 2006.257.18:58:12.82#ibcon#about to write, iclass 39, count 0 2006.257.18:58:12.82#ibcon#wrote, iclass 39, count 0 2006.257.18:58:12.82#ibcon#about to read 3, iclass 39, count 0 2006.257.18:58:12.84#ibcon#read 3, iclass 39, count 0 2006.257.18:58:12.84#ibcon#about to read 4, iclass 39, count 0 2006.257.18:58:12.84#ibcon#read 4, iclass 39, count 0 2006.257.18:58:12.84#ibcon#about to read 5, iclass 39, count 0 2006.257.18:58:12.84#ibcon#read 5, iclass 39, count 0 2006.257.18:58:12.84#ibcon#about to read 6, iclass 39, count 0 2006.257.18:58:12.84#ibcon#read 6, iclass 39, count 0 2006.257.18:58:12.84#ibcon#end of sib2, iclass 39, count 0 2006.257.18:58:12.84#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:58:12.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:58:12.84#ibcon#[25=USB\r\n] 2006.257.18:58:12.84#ibcon#*before write, iclass 39, count 0 2006.257.18:58:12.84#ibcon#enter sib2, iclass 39, count 0 2006.257.18:58:12.84#ibcon#flushed, iclass 39, count 0 2006.257.18:58:12.84#ibcon#about to write, iclass 39, count 0 2006.257.18:58:12.84#ibcon#wrote, iclass 39, count 0 2006.257.18:58:12.84#ibcon#about to read 3, iclass 39, count 0 2006.257.18:58:12.87#ibcon#read 3, iclass 39, count 0 2006.257.18:58:12.87#ibcon#about to read 4, iclass 39, count 0 2006.257.18:58:12.87#ibcon#read 4, iclass 39, count 0 2006.257.18:58:12.87#ibcon#about to read 5, iclass 39, count 0 2006.257.18:58:12.87#ibcon#read 5, iclass 39, count 0 2006.257.18:58:12.87#ibcon#about to read 6, iclass 39, count 0 2006.257.18:58:12.87#ibcon#read 6, iclass 39, count 0 2006.257.18:58:12.87#ibcon#end of sib2, iclass 39, count 0 2006.257.18:58:12.87#ibcon#*after write, iclass 39, count 0 2006.257.18:58:12.87#ibcon#*before return 0, iclass 39, count 0 2006.257.18:58:12.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:12.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:12.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:58:12.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:58:12.87$vck44/valo=2,534.99 2006.257.18:58:12.87#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.18:58:12.87#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.18:58:12.87#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:12.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:12.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:12.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:12.87#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:58:12.87#ibcon#first serial, iclass 3, count 0 2006.257.18:58:12.87#ibcon#enter sib2, iclass 3, count 0 2006.257.18:58:12.87#ibcon#flushed, iclass 3, count 0 2006.257.18:58:12.87#ibcon#about to write, iclass 3, count 0 2006.257.18:58:12.87#ibcon#wrote, iclass 3, count 0 2006.257.18:58:12.87#ibcon#about to read 3, iclass 3, count 0 2006.257.18:58:12.89#ibcon#read 3, iclass 3, count 0 2006.257.18:58:12.89#ibcon#about to read 4, iclass 3, count 0 2006.257.18:58:12.89#ibcon#read 4, iclass 3, count 0 2006.257.18:58:12.89#ibcon#about to read 5, iclass 3, count 0 2006.257.18:58:12.89#ibcon#read 5, iclass 3, count 0 2006.257.18:58:12.89#ibcon#about to read 6, iclass 3, count 0 2006.257.18:58:12.89#ibcon#read 6, iclass 3, count 0 2006.257.18:58:12.89#ibcon#end of sib2, iclass 3, count 0 2006.257.18:58:12.89#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:58:12.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:58:12.89#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.18:58:12.89#ibcon#*before write, iclass 3, count 0 2006.257.18:58:12.89#ibcon#enter sib2, iclass 3, count 0 2006.257.18:58:12.89#ibcon#flushed, iclass 3, count 0 2006.257.18:58:12.89#ibcon#about to write, iclass 3, count 0 2006.257.18:58:12.89#ibcon#wrote, iclass 3, count 0 2006.257.18:58:12.89#ibcon#about to read 3, iclass 3, count 0 2006.257.18:58:12.93#ibcon#read 3, iclass 3, count 0 2006.257.18:58:12.93#ibcon#about to read 4, iclass 3, count 0 2006.257.18:58:12.93#ibcon#read 4, iclass 3, count 0 2006.257.18:58:12.93#ibcon#about to read 5, iclass 3, count 0 2006.257.18:58:12.93#ibcon#read 5, iclass 3, count 0 2006.257.18:58:12.93#ibcon#about to read 6, iclass 3, count 0 2006.257.18:58:12.93#ibcon#read 6, iclass 3, count 0 2006.257.18:58:12.93#ibcon#end of sib2, iclass 3, count 0 2006.257.18:58:12.93#ibcon#*after write, iclass 3, count 0 2006.257.18:58:12.93#ibcon#*before return 0, iclass 3, count 0 2006.257.18:58:12.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:12.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:12.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:58:12.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:58:12.93$vck44/va=2,7 2006.257.18:58:12.93#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.18:58:12.93#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.18:58:12.93#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:12.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:12.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:12.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:12.99#ibcon#enter wrdev, iclass 5, count 2 2006.257.18:58:12.99#ibcon#first serial, iclass 5, count 2 2006.257.18:58:12.99#ibcon#enter sib2, iclass 5, count 2 2006.257.18:58:12.99#ibcon#flushed, iclass 5, count 2 2006.257.18:58:12.99#ibcon#about to write, iclass 5, count 2 2006.257.18:58:12.99#ibcon#wrote, iclass 5, count 2 2006.257.18:58:12.99#ibcon#about to read 3, iclass 5, count 2 2006.257.18:58:13.01#ibcon#read 3, iclass 5, count 2 2006.257.18:58:13.01#ibcon#about to read 4, iclass 5, count 2 2006.257.18:58:13.01#ibcon#read 4, iclass 5, count 2 2006.257.18:58:13.01#ibcon#about to read 5, iclass 5, count 2 2006.257.18:58:13.01#ibcon#read 5, iclass 5, count 2 2006.257.18:58:13.01#ibcon#about to read 6, iclass 5, count 2 2006.257.18:58:13.01#ibcon#read 6, iclass 5, count 2 2006.257.18:58:13.01#ibcon#end of sib2, iclass 5, count 2 2006.257.18:58:13.01#ibcon#*mode == 0, iclass 5, count 2 2006.257.18:58:13.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.18:58:13.01#ibcon#[25=AT02-07\r\n] 2006.257.18:58:13.01#ibcon#*before write, iclass 5, count 2 2006.257.18:58:13.01#ibcon#enter sib2, iclass 5, count 2 2006.257.18:58:13.01#ibcon#flushed, iclass 5, count 2 2006.257.18:58:13.01#ibcon#about to write, iclass 5, count 2 2006.257.18:58:13.01#ibcon#wrote, iclass 5, count 2 2006.257.18:58:13.01#ibcon#about to read 3, iclass 5, count 2 2006.257.18:58:13.04#ibcon#read 3, iclass 5, count 2 2006.257.18:58:13.04#ibcon#about to read 4, iclass 5, count 2 2006.257.18:58:13.04#ibcon#read 4, iclass 5, count 2 2006.257.18:58:13.04#ibcon#about to read 5, iclass 5, count 2 2006.257.18:58:13.04#ibcon#read 5, iclass 5, count 2 2006.257.18:58:13.04#ibcon#about to read 6, iclass 5, count 2 2006.257.18:58:13.04#ibcon#read 6, iclass 5, count 2 2006.257.18:58:13.04#ibcon#end of sib2, iclass 5, count 2 2006.257.18:58:13.04#ibcon#*after write, iclass 5, count 2 2006.257.18:58:13.04#ibcon#*before return 0, iclass 5, count 2 2006.257.18:58:13.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:13.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:13.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.18:58:13.04#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:13.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:13.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:13.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:13.16#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:58:13.16#ibcon#first serial, iclass 5, count 0 2006.257.18:58:13.16#ibcon#enter sib2, iclass 5, count 0 2006.257.18:58:13.16#ibcon#flushed, iclass 5, count 0 2006.257.18:58:13.16#ibcon#about to write, iclass 5, count 0 2006.257.18:58:13.16#ibcon#wrote, iclass 5, count 0 2006.257.18:58:13.16#ibcon#about to read 3, iclass 5, count 0 2006.257.18:58:13.18#ibcon#read 3, iclass 5, count 0 2006.257.18:58:13.18#ibcon#about to read 4, iclass 5, count 0 2006.257.18:58:13.18#ibcon#read 4, iclass 5, count 0 2006.257.18:58:13.18#ibcon#about to read 5, iclass 5, count 0 2006.257.18:58:13.18#ibcon#read 5, iclass 5, count 0 2006.257.18:58:13.18#ibcon#about to read 6, iclass 5, count 0 2006.257.18:58:13.18#ibcon#read 6, iclass 5, count 0 2006.257.18:58:13.18#ibcon#end of sib2, iclass 5, count 0 2006.257.18:58:13.18#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:58:13.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:58:13.18#ibcon#[25=USB\r\n] 2006.257.18:58:13.18#ibcon#*before write, iclass 5, count 0 2006.257.18:58:13.18#ibcon#enter sib2, iclass 5, count 0 2006.257.18:58:13.18#ibcon#flushed, iclass 5, count 0 2006.257.18:58:13.18#ibcon#about to write, iclass 5, count 0 2006.257.18:58:13.18#ibcon#wrote, iclass 5, count 0 2006.257.18:58:13.18#ibcon#about to read 3, iclass 5, count 0 2006.257.18:58:13.21#ibcon#read 3, iclass 5, count 0 2006.257.18:58:13.21#ibcon#about to read 4, iclass 5, count 0 2006.257.18:58:13.21#ibcon#read 4, iclass 5, count 0 2006.257.18:58:13.21#ibcon#about to read 5, iclass 5, count 0 2006.257.18:58:13.21#ibcon#read 5, iclass 5, count 0 2006.257.18:58:13.21#ibcon#about to read 6, iclass 5, count 0 2006.257.18:58:13.21#ibcon#read 6, iclass 5, count 0 2006.257.18:58:13.21#ibcon#end of sib2, iclass 5, count 0 2006.257.18:58:13.21#ibcon#*after write, iclass 5, count 0 2006.257.18:58:13.21#ibcon#*before return 0, iclass 5, count 0 2006.257.18:58:13.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:13.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:13.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:58:13.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:58:13.21$vck44/valo=3,564.99 2006.257.18:58:13.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.18:58:13.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.18:58:13.21#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:13.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:13.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:13.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:13.21#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:58:13.21#ibcon#first serial, iclass 7, count 0 2006.257.18:58:13.21#ibcon#enter sib2, iclass 7, count 0 2006.257.18:58:13.21#ibcon#flushed, iclass 7, count 0 2006.257.18:58:13.21#ibcon#about to write, iclass 7, count 0 2006.257.18:58:13.21#ibcon#wrote, iclass 7, count 0 2006.257.18:58:13.21#ibcon#about to read 3, iclass 7, count 0 2006.257.18:58:13.24#ibcon#read 3, iclass 7, count 0 2006.257.18:58:13.24#ibcon#about to read 4, iclass 7, count 0 2006.257.18:58:13.24#ibcon#read 4, iclass 7, count 0 2006.257.18:58:13.24#ibcon#about to read 5, iclass 7, count 0 2006.257.18:58:13.24#ibcon#read 5, iclass 7, count 0 2006.257.18:58:13.24#ibcon#about to read 6, iclass 7, count 0 2006.257.18:58:13.24#ibcon#read 6, iclass 7, count 0 2006.257.18:58:13.24#ibcon#end of sib2, iclass 7, count 0 2006.257.18:58:13.24#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:58:13.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:58:13.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.18:58:13.24#ibcon#*before write, iclass 7, count 0 2006.257.18:58:13.24#ibcon#enter sib2, iclass 7, count 0 2006.257.18:58:13.24#ibcon#flushed, iclass 7, count 0 2006.257.18:58:13.24#ibcon#about to write, iclass 7, count 0 2006.257.18:58:13.24#ibcon#wrote, iclass 7, count 0 2006.257.18:58:13.24#ibcon#about to read 3, iclass 7, count 0 2006.257.18:58:13.29#ibcon#read 3, iclass 7, count 0 2006.257.18:58:13.29#ibcon#about to read 4, iclass 7, count 0 2006.257.18:58:13.29#ibcon#read 4, iclass 7, count 0 2006.257.18:58:13.29#ibcon#about to read 5, iclass 7, count 0 2006.257.18:58:13.29#ibcon#read 5, iclass 7, count 0 2006.257.18:58:13.29#ibcon#about to read 6, iclass 7, count 0 2006.257.18:58:13.29#ibcon#read 6, iclass 7, count 0 2006.257.18:58:13.29#ibcon#end of sib2, iclass 7, count 0 2006.257.18:58:13.29#ibcon#*after write, iclass 7, count 0 2006.257.18:58:13.29#ibcon#*before return 0, iclass 7, count 0 2006.257.18:58:13.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:13.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:13.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:58:13.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:58:13.29$vck44/va=3,8 2006.257.18:58:13.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.18:58:13.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.18:58:13.29#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:13.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:13.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:13.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:13.33#ibcon#enter wrdev, iclass 11, count 2 2006.257.18:58:13.33#ibcon#first serial, iclass 11, count 2 2006.257.18:58:13.33#ibcon#enter sib2, iclass 11, count 2 2006.257.18:58:13.33#ibcon#flushed, iclass 11, count 2 2006.257.18:58:13.33#ibcon#about to write, iclass 11, count 2 2006.257.18:58:13.33#ibcon#wrote, iclass 11, count 2 2006.257.18:58:13.33#ibcon#about to read 3, iclass 11, count 2 2006.257.18:58:13.35#ibcon#read 3, iclass 11, count 2 2006.257.18:58:13.35#ibcon#about to read 4, iclass 11, count 2 2006.257.18:58:13.35#ibcon#read 4, iclass 11, count 2 2006.257.18:58:13.35#ibcon#about to read 5, iclass 11, count 2 2006.257.18:58:13.35#ibcon#read 5, iclass 11, count 2 2006.257.18:58:13.35#ibcon#about to read 6, iclass 11, count 2 2006.257.18:58:13.35#ibcon#read 6, iclass 11, count 2 2006.257.18:58:13.35#ibcon#end of sib2, iclass 11, count 2 2006.257.18:58:13.35#ibcon#*mode == 0, iclass 11, count 2 2006.257.18:58:13.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.18:58:13.35#ibcon#[25=AT03-08\r\n] 2006.257.18:58:13.35#ibcon#*before write, iclass 11, count 2 2006.257.18:58:13.35#ibcon#enter sib2, iclass 11, count 2 2006.257.18:58:13.35#ibcon#flushed, iclass 11, count 2 2006.257.18:58:13.35#ibcon#about to write, iclass 11, count 2 2006.257.18:58:13.35#ibcon#wrote, iclass 11, count 2 2006.257.18:58:13.35#ibcon#about to read 3, iclass 11, count 2 2006.257.18:58:13.38#ibcon#read 3, iclass 11, count 2 2006.257.18:58:13.38#ibcon#about to read 4, iclass 11, count 2 2006.257.18:58:13.38#ibcon#read 4, iclass 11, count 2 2006.257.18:58:13.38#ibcon#about to read 5, iclass 11, count 2 2006.257.18:58:13.38#ibcon#read 5, iclass 11, count 2 2006.257.18:58:13.38#ibcon#about to read 6, iclass 11, count 2 2006.257.18:58:13.38#ibcon#read 6, iclass 11, count 2 2006.257.18:58:13.38#ibcon#end of sib2, iclass 11, count 2 2006.257.18:58:13.38#ibcon#*after write, iclass 11, count 2 2006.257.18:58:13.38#ibcon#*before return 0, iclass 11, count 2 2006.257.18:58:13.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:13.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:13.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.18:58:13.38#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:13.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:13.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:13.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:13.50#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:58:13.50#ibcon#first serial, iclass 11, count 0 2006.257.18:58:13.50#ibcon#enter sib2, iclass 11, count 0 2006.257.18:58:13.50#ibcon#flushed, iclass 11, count 0 2006.257.18:58:13.50#ibcon#about to write, iclass 11, count 0 2006.257.18:58:13.50#ibcon#wrote, iclass 11, count 0 2006.257.18:58:13.50#ibcon#about to read 3, iclass 11, count 0 2006.257.18:58:13.52#ibcon#read 3, iclass 11, count 0 2006.257.18:58:13.52#ibcon#about to read 4, iclass 11, count 0 2006.257.18:58:13.52#ibcon#read 4, iclass 11, count 0 2006.257.18:58:13.52#ibcon#about to read 5, iclass 11, count 0 2006.257.18:58:13.52#ibcon#read 5, iclass 11, count 0 2006.257.18:58:13.52#ibcon#about to read 6, iclass 11, count 0 2006.257.18:58:13.52#ibcon#read 6, iclass 11, count 0 2006.257.18:58:13.52#ibcon#end of sib2, iclass 11, count 0 2006.257.18:58:13.52#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:58:13.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:58:13.52#ibcon#[25=USB\r\n] 2006.257.18:58:13.52#ibcon#*before write, iclass 11, count 0 2006.257.18:58:13.52#ibcon#enter sib2, iclass 11, count 0 2006.257.18:58:13.52#ibcon#flushed, iclass 11, count 0 2006.257.18:58:13.52#ibcon#about to write, iclass 11, count 0 2006.257.18:58:13.52#ibcon#wrote, iclass 11, count 0 2006.257.18:58:13.52#ibcon#about to read 3, iclass 11, count 0 2006.257.18:58:13.55#ibcon#read 3, iclass 11, count 0 2006.257.18:58:13.55#ibcon#about to read 4, iclass 11, count 0 2006.257.18:58:13.55#ibcon#read 4, iclass 11, count 0 2006.257.18:58:13.55#ibcon#about to read 5, iclass 11, count 0 2006.257.18:58:13.55#ibcon#read 5, iclass 11, count 0 2006.257.18:58:13.55#ibcon#about to read 6, iclass 11, count 0 2006.257.18:58:13.55#ibcon#read 6, iclass 11, count 0 2006.257.18:58:13.55#ibcon#end of sib2, iclass 11, count 0 2006.257.18:58:13.55#ibcon#*after write, iclass 11, count 0 2006.257.18:58:13.55#ibcon#*before return 0, iclass 11, count 0 2006.257.18:58:13.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:13.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:13.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:58:13.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:58:13.55$vck44/valo=4,624.99 2006.257.18:58:13.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.18:58:13.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.18:58:13.55#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:13.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:13.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:13.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:13.55#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:58:13.55#ibcon#first serial, iclass 13, count 0 2006.257.18:58:13.55#ibcon#enter sib2, iclass 13, count 0 2006.257.18:58:13.55#ibcon#flushed, iclass 13, count 0 2006.257.18:58:13.55#ibcon#about to write, iclass 13, count 0 2006.257.18:58:13.55#ibcon#wrote, iclass 13, count 0 2006.257.18:58:13.55#ibcon#about to read 3, iclass 13, count 0 2006.257.18:58:13.57#ibcon#read 3, iclass 13, count 0 2006.257.18:58:13.57#ibcon#about to read 4, iclass 13, count 0 2006.257.18:58:13.57#ibcon#read 4, iclass 13, count 0 2006.257.18:58:13.57#ibcon#about to read 5, iclass 13, count 0 2006.257.18:58:13.57#ibcon#read 5, iclass 13, count 0 2006.257.18:58:13.57#ibcon#about to read 6, iclass 13, count 0 2006.257.18:58:13.57#ibcon#read 6, iclass 13, count 0 2006.257.18:58:13.57#ibcon#end of sib2, iclass 13, count 0 2006.257.18:58:13.57#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:58:13.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:58:13.57#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.18:58:13.57#ibcon#*before write, iclass 13, count 0 2006.257.18:58:13.57#ibcon#enter sib2, iclass 13, count 0 2006.257.18:58:13.57#ibcon#flushed, iclass 13, count 0 2006.257.18:58:13.57#ibcon#about to write, iclass 13, count 0 2006.257.18:58:13.57#ibcon#wrote, iclass 13, count 0 2006.257.18:58:13.57#ibcon#about to read 3, iclass 13, count 0 2006.257.18:58:13.61#ibcon#read 3, iclass 13, count 0 2006.257.18:58:13.61#ibcon#about to read 4, iclass 13, count 0 2006.257.18:58:13.61#ibcon#read 4, iclass 13, count 0 2006.257.18:58:13.61#ibcon#about to read 5, iclass 13, count 0 2006.257.18:58:13.61#ibcon#read 5, iclass 13, count 0 2006.257.18:58:13.61#ibcon#about to read 6, iclass 13, count 0 2006.257.18:58:13.61#ibcon#read 6, iclass 13, count 0 2006.257.18:58:13.61#ibcon#end of sib2, iclass 13, count 0 2006.257.18:58:13.61#ibcon#*after write, iclass 13, count 0 2006.257.18:58:13.61#ibcon#*before return 0, iclass 13, count 0 2006.257.18:58:13.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:13.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:13.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:58:13.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:58:13.61$vck44/va=4,7 2006.257.18:58:13.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.18:58:13.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.18:58:13.61#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:13.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:13.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:13.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:13.67#ibcon#enter wrdev, iclass 15, count 2 2006.257.18:58:13.67#ibcon#first serial, iclass 15, count 2 2006.257.18:58:13.67#ibcon#enter sib2, iclass 15, count 2 2006.257.18:58:13.67#ibcon#flushed, iclass 15, count 2 2006.257.18:58:13.67#ibcon#about to write, iclass 15, count 2 2006.257.18:58:13.67#ibcon#wrote, iclass 15, count 2 2006.257.18:58:13.67#ibcon#about to read 3, iclass 15, count 2 2006.257.18:58:13.69#ibcon#read 3, iclass 15, count 2 2006.257.18:58:13.69#ibcon#about to read 4, iclass 15, count 2 2006.257.18:58:13.69#ibcon#read 4, iclass 15, count 2 2006.257.18:58:13.69#ibcon#about to read 5, iclass 15, count 2 2006.257.18:58:13.69#ibcon#read 5, iclass 15, count 2 2006.257.18:58:13.69#ibcon#about to read 6, iclass 15, count 2 2006.257.18:58:13.69#ibcon#read 6, iclass 15, count 2 2006.257.18:58:13.69#ibcon#end of sib2, iclass 15, count 2 2006.257.18:58:13.69#ibcon#*mode == 0, iclass 15, count 2 2006.257.18:58:13.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.18:58:13.69#ibcon#[25=AT04-07\r\n] 2006.257.18:58:13.69#ibcon#*before write, iclass 15, count 2 2006.257.18:58:13.69#ibcon#enter sib2, iclass 15, count 2 2006.257.18:58:13.69#ibcon#flushed, iclass 15, count 2 2006.257.18:58:13.69#ibcon#about to write, iclass 15, count 2 2006.257.18:58:13.69#ibcon#wrote, iclass 15, count 2 2006.257.18:58:13.69#ibcon#about to read 3, iclass 15, count 2 2006.257.18:58:13.72#ibcon#read 3, iclass 15, count 2 2006.257.18:58:13.72#ibcon#about to read 4, iclass 15, count 2 2006.257.18:58:13.72#ibcon#read 4, iclass 15, count 2 2006.257.18:58:13.72#ibcon#about to read 5, iclass 15, count 2 2006.257.18:58:13.72#ibcon#read 5, iclass 15, count 2 2006.257.18:58:13.72#ibcon#about to read 6, iclass 15, count 2 2006.257.18:58:13.72#ibcon#read 6, iclass 15, count 2 2006.257.18:58:13.72#ibcon#end of sib2, iclass 15, count 2 2006.257.18:58:13.72#ibcon#*after write, iclass 15, count 2 2006.257.18:58:13.72#ibcon#*before return 0, iclass 15, count 2 2006.257.18:58:13.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:13.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:13.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.18:58:13.72#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:13.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:13.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:13.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:13.84#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:58:13.84#ibcon#first serial, iclass 15, count 0 2006.257.18:58:13.84#ibcon#enter sib2, iclass 15, count 0 2006.257.18:58:13.84#ibcon#flushed, iclass 15, count 0 2006.257.18:58:13.84#ibcon#about to write, iclass 15, count 0 2006.257.18:58:13.84#ibcon#wrote, iclass 15, count 0 2006.257.18:58:13.84#ibcon#about to read 3, iclass 15, count 0 2006.257.18:58:13.86#ibcon#read 3, iclass 15, count 0 2006.257.18:58:13.86#ibcon#about to read 4, iclass 15, count 0 2006.257.18:58:13.86#ibcon#read 4, iclass 15, count 0 2006.257.18:58:13.86#ibcon#about to read 5, iclass 15, count 0 2006.257.18:58:13.86#ibcon#read 5, iclass 15, count 0 2006.257.18:58:13.86#ibcon#about to read 6, iclass 15, count 0 2006.257.18:58:13.86#ibcon#read 6, iclass 15, count 0 2006.257.18:58:13.86#ibcon#end of sib2, iclass 15, count 0 2006.257.18:58:13.86#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:58:13.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:58:13.86#ibcon#[25=USB\r\n] 2006.257.18:58:13.86#ibcon#*before write, iclass 15, count 0 2006.257.18:58:13.86#ibcon#enter sib2, iclass 15, count 0 2006.257.18:58:13.86#ibcon#flushed, iclass 15, count 0 2006.257.18:58:13.86#ibcon#about to write, iclass 15, count 0 2006.257.18:58:13.86#ibcon#wrote, iclass 15, count 0 2006.257.18:58:13.86#ibcon#about to read 3, iclass 15, count 0 2006.257.18:58:13.89#ibcon#read 3, iclass 15, count 0 2006.257.18:58:13.89#ibcon#about to read 4, iclass 15, count 0 2006.257.18:58:13.89#ibcon#read 4, iclass 15, count 0 2006.257.18:58:13.89#ibcon#about to read 5, iclass 15, count 0 2006.257.18:58:13.89#ibcon#read 5, iclass 15, count 0 2006.257.18:58:13.89#ibcon#about to read 6, iclass 15, count 0 2006.257.18:58:13.89#ibcon#read 6, iclass 15, count 0 2006.257.18:58:13.89#ibcon#end of sib2, iclass 15, count 0 2006.257.18:58:13.89#ibcon#*after write, iclass 15, count 0 2006.257.18:58:13.89#ibcon#*before return 0, iclass 15, count 0 2006.257.18:58:13.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:13.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:13.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:58:13.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:58:13.89$vck44/valo=5,734.99 2006.257.18:58:13.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.18:58:13.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.18:58:13.89#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:13.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:13.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:13.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:13.89#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:58:13.89#ibcon#first serial, iclass 17, count 0 2006.257.18:58:13.89#ibcon#enter sib2, iclass 17, count 0 2006.257.18:58:13.89#ibcon#flushed, iclass 17, count 0 2006.257.18:58:13.89#ibcon#about to write, iclass 17, count 0 2006.257.18:58:13.89#ibcon#wrote, iclass 17, count 0 2006.257.18:58:13.89#ibcon#about to read 3, iclass 17, count 0 2006.257.18:58:13.91#ibcon#read 3, iclass 17, count 0 2006.257.18:58:13.91#ibcon#about to read 4, iclass 17, count 0 2006.257.18:58:13.91#ibcon#read 4, iclass 17, count 0 2006.257.18:58:13.91#ibcon#about to read 5, iclass 17, count 0 2006.257.18:58:13.91#ibcon#read 5, iclass 17, count 0 2006.257.18:58:13.91#ibcon#about to read 6, iclass 17, count 0 2006.257.18:58:13.91#ibcon#read 6, iclass 17, count 0 2006.257.18:58:13.91#ibcon#end of sib2, iclass 17, count 0 2006.257.18:58:13.91#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:58:13.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:58:13.91#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.18:58:13.91#ibcon#*before write, iclass 17, count 0 2006.257.18:58:13.91#ibcon#enter sib2, iclass 17, count 0 2006.257.18:58:13.91#ibcon#flushed, iclass 17, count 0 2006.257.18:58:13.91#ibcon#about to write, iclass 17, count 0 2006.257.18:58:13.91#ibcon#wrote, iclass 17, count 0 2006.257.18:58:13.91#ibcon#about to read 3, iclass 17, count 0 2006.257.18:58:13.95#ibcon#read 3, iclass 17, count 0 2006.257.18:58:13.95#ibcon#about to read 4, iclass 17, count 0 2006.257.18:58:13.95#ibcon#read 4, iclass 17, count 0 2006.257.18:58:13.95#ibcon#about to read 5, iclass 17, count 0 2006.257.18:58:13.95#ibcon#read 5, iclass 17, count 0 2006.257.18:58:13.95#ibcon#about to read 6, iclass 17, count 0 2006.257.18:58:13.95#ibcon#read 6, iclass 17, count 0 2006.257.18:58:13.95#ibcon#end of sib2, iclass 17, count 0 2006.257.18:58:13.95#ibcon#*after write, iclass 17, count 0 2006.257.18:58:13.95#ibcon#*before return 0, iclass 17, count 0 2006.257.18:58:13.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:13.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:13.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:58:13.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:58:13.95$vck44/va=5,4 2006.257.18:58:13.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.18:58:13.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.18:58:13.95#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:13.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:14.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:14.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:14.01#ibcon#enter wrdev, iclass 19, count 2 2006.257.18:58:14.01#ibcon#first serial, iclass 19, count 2 2006.257.18:58:14.01#ibcon#enter sib2, iclass 19, count 2 2006.257.18:58:14.01#ibcon#flushed, iclass 19, count 2 2006.257.18:58:14.01#ibcon#about to write, iclass 19, count 2 2006.257.18:58:14.01#ibcon#wrote, iclass 19, count 2 2006.257.18:58:14.01#ibcon#about to read 3, iclass 19, count 2 2006.257.18:58:14.03#ibcon#read 3, iclass 19, count 2 2006.257.18:58:14.03#ibcon#about to read 4, iclass 19, count 2 2006.257.18:58:14.03#ibcon#read 4, iclass 19, count 2 2006.257.18:58:14.03#ibcon#about to read 5, iclass 19, count 2 2006.257.18:58:14.03#ibcon#read 5, iclass 19, count 2 2006.257.18:58:14.03#ibcon#about to read 6, iclass 19, count 2 2006.257.18:58:14.03#ibcon#read 6, iclass 19, count 2 2006.257.18:58:14.03#ibcon#end of sib2, iclass 19, count 2 2006.257.18:58:14.03#ibcon#*mode == 0, iclass 19, count 2 2006.257.18:58:14.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.18:58:14.03#ibcon#[25=AT05-04\r\n] 2006.257.18:58:14.03#ibcon#*before write, iclass 19, count 2 2006.257.18:58:14.03#ibcon#enter sib2, iclass 19, count 2 2006.257.18:58:14.03#ibcon#flushed, iclass 19, count 2 2006.257.18:58:14.03#ibcon#about to write, iclass 19, count 2 2006.257.18:58:14.03#ibcon#wrote, iclass 19, count 2 2006.257.18:58:14.03#ibcon#about to read 3, iclass 19, count 2 2006.257.18:58:14.06#ibcon#read 3, iclass 19, count 2 2006.257.18:58:14.06#ibcon#about to read 4, iclass 19, count 2 2006.257.18:58:14.06#ibcon#read 4, iclass 19, count 2 2006.257.18:58:14.06#ibcon#about to read 5, iclass 19, count 2 2006.257.18:58:14.06#ibcon#read 5, iclass 19, count 2 2006.257.18:58:14.06#ibcon#about to read 6, iclass 19, count 2 2006.257.18:58:14.06#ibcon#read 6, iclass 19, count 2 2006.257.18:58:14.06#ibcon#end of sib2, iclass 19, count 2 2006.257.18:58:14.06#ibcon#*after write, iclass 19, count 2 2006.257.18:58:14.06#ibcon#*before return 0, iclass 19, count 2 2006.257.18:58:14.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:14.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:14.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.18:58:14.06#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:14.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:14.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:14.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:14.18#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:58:14.18#ibcon#first serial, iclass 19, count 0 2006.257.18:58:14.18#ibcon#enter sib2, iclass 19, count 0 2006.257.18:58:14.18#ibcon#flushed, iclass 19, count 0 2006.257.18:58:14.18#ibcon#about to write, iclass 19, count 0 2006.257.18:58:14.18#ibcon#wrote, iclass 19, count 0 2006.257.18:58:14.18#ibcon#about to read 3, iclass 19, count 0 2006.257.18:58:14.20#ibcon#read 3, iclass 19, count 0 2006.257.18:58:14.20#ibcon#about to read 4, iclass 19, count 0 2006.257.18:58:14.20#ibcon#read 4, iclass 19, count 0 2006.257.18:58:14.20#ibcon#about to read 5, iclass 19, count 0 2006.257.18:58:14.20#ibcon#read 5, iclass 19, count 0 2006.257.18:58:14.20#ibcon#about to read 6, iclass 19, count 0 2006.257.18:58:14.20#ibcon#read 6, iclass 19, count 0 2006.257.18:58:14.20#ibcon#end of sib2, iclass 19, count 0 2006.257.18:58:14.20#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:58:14.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:58:14.20#ibcon#[25=USB\r\n] 2006.257.18:58:14.20#ibcon#*before write, iclass 19, count 0 2006.257.18:58:14.20#ibcon#enter sib2, iclass 19, count 0 2006.257.18:58:14.20#ibcon#flushed, iclass 19, count 0 2006.257.18:58:14.20#ibcon#about to write, iclass 19, count 0 2006.257.18:58:14.20#ibcon#wrote, iclass 19, count 0 2006.257.18:58:14.20#ibcon#about to read 3, iclass 19, count 0 2006.257.18:58:14.23#ibcon#read 3, iclass 19, count 0 2006.257.18:58:14.23#ibcon#about to read 4, iclass 19, count 0 2006.257.18:58:14.23#ibcon#read 4, iclass 19, count 0 2006.257.18:58:14.23#ibcon#about to read 5, iclass 19, count 0 2006.257.18:58:14.23#ibcon#read 5, iclass 19, count 0 2006.257.18:58:14.23#ibcon#about to read 6, iclass 19, count 0 2006.257.18:58:14.23#ibcon#read 6, iclass 19, count 0 2006.257.18:58:14.23#ibcon#end of sib2, iclass 19, count 0 2006.257.18:58:14.23#ibcon#*after write, iclass 19, count 0 2006.257.18:58:14.23#ibcon#*before return 0, iclass 19, count 0 2006.257.18:58:14.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:14.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:14.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:58:14.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:58:14.23$vck44/valo=6,814.99 2006.257.18:58:14.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.18:58:14.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.18:58:14.23#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:14.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:14.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:14.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:14.23#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:58:14.23#ibcon#first serial, iclass 21, count 0 2006.257.18:58:14.23#ibcon#enter sib2, iclass 21, count 0 2006.257.18:58:14.23#ibcon#flushed, iclass 21, count 0 2006.257.18:58:14.23#ibcon#about to write, iclass 21, count 0 2006.257.18:58:14.23#ibcon#wrote, iclass 21, count 0 2006.257.18:58:14.23#ibcon#about to read 3, iclass 21, count 0 2006.257.18:58:14.25#ibcon#read 3, iclass 21, count 0 2006.257.18:58:14.25#ibcon#about to read 4, iclass 21, count 0 2006.257.18:58:14.25#ibcon#read 4, iclass 21, count 0 2006.257.18:58:14.25#ibcon#about to read 5, iclass 21, count 0 2006.257.18:58:14.25#ibcon#read 5, iclass 21, count 0 2006.257.18:58:14.25#ibcon#about to read 6, iclass 21, count 0 2006.257.18:58:14.25#ibcon#read 6, iclass 21, count 0 2006.257.18:58:14.25#ibcon#end of sib2, iclass 21, count 0 2006.257.18:58:14.25#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:58:14.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:58:14.25#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.18:58:14.25#ibcon#*before write, iclass 21, count 0 2006.257.18:58:14.25#ibcon#enter sib2, iclass 21, count 0 2006.257.18:58:14.25#ibcon#flushed, iclass 21, count 0 2006.257.18:58:14.25#ibcon#about to write, iclass 21, count 0 2006.257.18:58:14.25#ibcon#wrote, iclass 21, count 0 2006.257.18:58:14.25#ibcon#about to read 3, iclass 21, count 0 2006.257.18:58:14.29#ibcon#read 3, iclass 21, count 0 2006.257.18:58:14.29#ibcon#about to read 4, iclass 21, count 0 2006.257.18:58:14.29#ibcon#read 4, iclass 21, count 0 2006.257.18:58:14.29#ibcon#about to read 5, iclass 21, count 0 2006.257.18:58:14.29#ibcon#read 5, iclass 21, count 0 2006.257.18:58:14.29#ibcon#about to read 6, iclass 21, count 0 2006.257.18:58:14.29#ibcon#read 6, iclass 21, count 0 2006.257.18:58:14.29#ibcon#end of sib2, iclass 21, count 0 2006.257.18:58:14.29#ibcon#*after write, iclass 21, count 0 2006.257.18:58:14.29#ibcon#*before return 0, iclass 21, count 0 2006.257.18:58:14.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:14.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:14.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:58:14.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:58:14.29$vck44/va=6,4 2006.257.18:58:14.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.18:58:14.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.18:58:14.29#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:14.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:14.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:14.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:14.35#ibcon#enter wrdev, iclass 23, count 2 2006.257.18:58:14.35#ibcon#first serial, iclass 23, count 2 2006.257.18:58:14.35#ibcon#enter sib2, iclass 23, count 2 2006.257.18:58:14.35#ibcon#flushed, iclass 23, count 2 2006.257.18:58:14.35#ibcon#about to write, iclass 23, count 2 2006.257.18:58:14.35#ibcon#wrote, iclass 23, count 2 2006.257.18:58:14.35#ibcon#about to read 3, iclass 23, count 2 2006.257.18:58:14.37#ibcon#read 3, iclass 23, count 2 2006.257.18:58:14.37#ibcon#about to read 4, iclass 23, count 2 2006.257.18:58:14.37#ibcon#read 4, iclass 23, count 2 2006.257.18:58:14.37#ibcon#about to read 5, iclass 23, count 2 2006.257.18:58:14.37#ibcon#read 5, iclass 23, count 2 2006.257.18:58:14.37#ibcon#about to read 6, iclass 23, count 2 2006.257.18:58:14.37#ibcon#read 6, iclass 23, count 2 2006.257.18:58:14.37#ibcon#end of sib2, iclass 23, count 2 2006.257.18:58:14.37#ibcon#*mode == 0, iclass 23, count 2 2006.257.18:58:14.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.18:58:14.37#ibcon#[25=AT06-04\r\n] 2006.257.18:58:14.37#ibcon#*before write, iclass 23, count 2 2006.257.18:58:14.37#ibcon#enter sib2, iclass 23, count 2 2006.257.18:58:14.37#ibcon#flushed, iclass 23, count 2 2006.257.18:58:14.37#ibcon#about to write, iclass 23, count 2 2006.257.18:58:14.37#ibcon#wrote, iclass 23, count 2 2006.257.18:58:14.37#ibcon#about to read 3, iclass 23, count 2 2006.257.18:58:14.40#ibcon#read 3, iclass 23, count 2 2006.257.18:58:14.40#ibcon#about to read 4, iclass 23, count 2 2006.257.18:58:14.40#ibcon#read 4, iclass 23, count 2 2006.257.18:58:14.40#ibcon#about to read 5, iclass 23, count 2 2006.257.18:58:14.40#ibcon#read 5, iclass 23, count 2 2006.257.18:58:14.40#ibcon#about to read 6, iclass 23, count 2 2006.257.18:58:14.40#ibcon#read 6, iclass 23, count 2 2006.257.18:58:14.40#ibcon#end of sib2, iclass 23, count 2 2006.257.18:58:14.40#ibcon#*after write, iclass 23, count 2 2006.257.18:58:14.40#ibcon#*before return 0, iclass 23, count 2 2006.257.18:58:14.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:14.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:14.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.18:58:14.40#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:14.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:14.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:14.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:14.52#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:58:14.52#ibcon#first serial, iclass 23, count 0 2006.257.18:58:14.52#ibcon#enter sib2, iclass 23, count 0 2006.257.18:58:14.52#ibcon#flushed, iclass 23, count 0 2006.257.18:58:14.52#ibcon#about to write, iclass 23, count 0 2006.257.18:58:14.52#ibcon#wrote, iclass 23, count 0 2006.257.18:58:14.52#ibcon#about to read 3, iclass 23, count 0 2006.257.18:58:14.54#ibcon#read 3, iclass 23, count 0 2006.257.18:58:14.54#ibcon#about to read 4, iclass 23, count 0 2006.257.18:58:14.54#ibcon#read 4, iclass 23, count 0 2006.257.18:58:14.54#ibcon#about to read 5, iclass 23, count 0 2006.257.18:58:14.54#ibcon#read 5, iclass 23, count 0 2006.257.18:58:14.54#ibcon#about to read 6, iclass 23, count 0 2006.257.18:58:14.54#ibcon#read 6, iclass 23, count 0 2006.257.18:58:14.54#ibcon#end of sib2, iclass 23, count 0 2006.257.18:58:14.54#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:58:14.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:58:14.54#ibcon#[25=USB\r\n] 2006.257.18:58:14.54#ibcon#*before write, iclass 23, count 0 2006.257.18:58:14.54#ibcon#enter sib2, iclass 23, count 0 2006.257.18:58:14.54#ibcon#flushed, iclass 23, count 0 2006.257.18:58:14.54#ibcon#about to write, iclass 23, count 0 2006.257.18:58:14.54#ibcon#wrote, iclass 23, count 0 2006.257.18:58:14.54#ibcon#about to read 3, iclass 23, count 0 2006.257.18:58:14.57#ibcon#read 3, iclass 23, count 0 2006.257.18:58:14.57#ibcon#about to read 4, iclass 23, count 0 2006.257.18:58:14.57#ibcon#read 4, iclass 23, count 0 2006.257.18:58:14.57#ibcon#about to read 5, iclass 23, count 0 2006.257.18:58:14.57#ibcon#read 5, iclass 23, count 0 2006.257.18:58:14.57#ibcon#about to read 6, iclass 23, count 0 2006.257.18:58:14.57#ibcon#read 6, iclass 23, count 0 2006.257.18:58:14.57#ibcon#end of sib2, iclass 23, count 0 2006.257.18:58:14.57#ibcon#*after write, iclass 23, count 0 2006.257.18:58:14.57#ibcon#*before return 0, iclass 23, count 0 2006.257.18:58:14.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:14.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:14.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:58:14.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:58:14.57$vck44/valo=7,864.99 2006.257.18:58:14.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.18:58:14.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.18:58:14.57#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:14.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:14.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:14.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:14.57#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:58:14.57#ibcon#first serial, iclass 25, count 0 2006.257.18:58:14.57#ibcon#enter sib2, iclass 25, count 0 2006.257.18:58:14.57#ibcon#flushed, iclass 25, count 0 2006.257.18:58:14.57#ibcon#about to write, iclass 25, count 0 2006.257.18:58:14.57#ibcon#wrote, iclass 25, count 0 2006.257.18:58:14.57#ibcon#about to read 3, iclass 25, count 0 2006.257.18:58:14.59#ibcon#read 3, iclass 25, count 0 2006.257.18:58:14.59#ibcon#about to read 4, iclass 25, count 0 2006.257.18:58:14.59#ibcon#read 4, iclass 25, count 0 2006.257.18:58:14.59#ibcon#about to read 5, iclass 25, count 0 2006.257.18:58:14.59#ibcon#read 5, iclass 25, count 0 2006.257.18:58:14.59#ibcon#about to read 6, iclass 25, count 0 2006.257.18:58:14.59#ibcon#read 6, iclass 25, count 0 2006.257.18:58:14.59#ibcon#end of sib2, iclass 25, count 0 2006.257.18:58:14.59#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:58:14.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:58:14.59#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.18:58:14.59#ibcon#*before write, iclass 25, count 0 2006.257.18:58:14.59#ibcon#enter sib2, iclass 25, count 0 2006.257.18:58:14.59#ibcon#flushed, iclass 25, count 0 2006.257.18:58:14.59#ibcon#about to write, iclass 25, count 0 2006.257.18:58:14.59#ibcon#wrote, iclass 25, count 0 2006.257.18:58:14.59#ibcon#about to read 3, iclass 25, count 0 2006.257.18:58:14.63#ibcon#read 3, iclass 25, count 0 2006.257.18:58:14.63#ibcon#about to read 4, iclass 25, count 0 2006.257.18:58:14.63#ibcon#read 4, iclass 25, count 0 2006.257.18:58:14.63#ibcon#about to read 5, iclass 25, count 0 2006.257.18:58:14.63#ibcon#read 5, iclass 25, count 0 2006.257.18:58:14.63#ibcon#about to read 6, iclass 25, count 0 2006.257.18:58:14.63#ibcon#read 6, iclass 25, count 0 2006.257.18:58:14.63#ibcon#end of sib2, iclass 25, count 0 2006.257.18:58:14.63#ibcon#*after write, iclass 25, count 0 2006.257.18:58:14.63#ibcon#*before return 0, iclass 25, count 0 2006.257.18:58:14.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:14.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:14.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:58:14.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:58:14.63$vck44/va=7,4 2006.257.18:58:14.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.18:58:14.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.18:58:14.63#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:14.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:14.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:14.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:14.69#ibcon#enter wrdev, iclass 27, count 2 2006.257.18:58:14.69#ibcon#first serial, iclass 27, count 2 2006.257.18:58:14.69#ibcon#enter sib2, iclass 27, count 2 2006.257.18:58:14.69#ibcon#flushed, iclass 27, count 2 2006.257.18:58:14.69#ibcon#about to write, iclass 27, count 2 2006.257.18:58:14.69#ibcon#wrote, iclass 27, count 2 2006.257.18:58:14.69#ibcon#about to read 3, iclass 27, count 2 2006.257.18:58:14.71#ibcon#read 3, iclass 27, count 2 2006.257.18:58:14.71#ibcon#about to read 4, iclass 27, count 2 2006.257.18:58:14.71#ibcon#read 4, iclass 27, count 2 2006.257.18:58:14.71#ibcon#about to read 5, iclass 27, count 2 2006.257.18:58:14.71#ibcon#read 5, iclass 27, count 2 2006.257.18:58:14.71#ibcon#about to read 6, iclass 27, count 2 2006.257.18:58:14.71#ibcon#read 6, iclass 27, count 2 2006.257.18:58:14.71#ibcon#end of sib2, iclass 27, count 2 2006.257.18:58:14.71#ibcon#*mode == 0, iclass 27, count 2 2006.257.18:58:14.71#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.18:58:14.71#ibcon#[25=AT07-04\r\n] 2006.257.18:58:14.71#ibcon#*before write, iclass 27, count 2 2006.257.18:58:14.71#ibcon#enter sib2, iclass 27, count 2 2006.257.18:58:14.71#ibcon#flushed, iclass 27, count 2 2006.257.18:58:14.71#ibcon#about to write, iclass 27, count 2 2006.257.18:58:14.71#ibcon#wrote, iclass 27, count 2 2006.257.18:58:14.71#ibcon#about to read 3, iclass 27, count 2 2006.257.18:58:14.74#ibcon#read 3, iclass 27, count 2 2006.257.18:58:14.74#ibcon#about to read 4, iclass 27, count 2 2006.257.18:58:14.74#ibcon#read 4, iclass 27, count 2 2006.257.18:58:14.74#ibcon#about to read 5, iclass 27, count 2 2006.257.18:58:14.74#ibcon#read 5, iclass 27, count 2 2006.257.18:58:14.74#ibcon#about to read 6, iclass 27, count 2 2006.257.18:58:14.74#ibcon#read 6, iclass 27, count 2 2006.257.18:58:14.74#ibcon#end of sib2, iclass 27, count 2 2006.257.18:58:14.74#ibcon#*after write, iclass 27, count 2 2006.257.18:58:14.74#ibcon#*before return 0, iclass 27, count 2 2006.257.18:58:14.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:14.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:14.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.18:58:14.74#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:14.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:14.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:14.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:14.86#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:58:14.86#ibcon#first serial, iclass 27, count 0 2006.257.18:58:14.86#ibcon#enter sib2, iclass 27, count 0 2006.257.18:58:14.86#ibcon#flushed, iclass 27, count 0 2006.257.18:58:14.86#ibcon#about to write, iclass 27, count 0 2006.257.18:58:14.86#ibcon#wrote, iclass 27, count 0 2006.257.18:58:14.86#ibcon#about to read 3, iclass 27, count 0 2006.257.18:58:14.88#ibcon#read 3, iclass 27, count 0 2006.257.18:58:14.88#ibcon#about to read 4, iclass 27, count 0 2006.257.18:58:14.88#ibcon#read 4, iclass 27, count 0 2006.257.18:58:14.88#ibcon#about to read 5, iclass 27, count 0 2006.257.18:58:14.88#ibcon#read 5, iclass 27, count 0 2006.257.18:58:14.88#ibcon#about to read 6, iclass 27, count 0 2006.257.18:58:14.88#ibcon#read 6, iclass 27, count 0 2006.257.18:58:14.88#ibcon#end of sib2, iclass 27, count 0 2006.257.18:58:14.88#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:58:14.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:58:14.88#ibcon#[25=USB\r\n] 2006.257.18:58:14.88#ibcon#*before write, iclass 27, count 0 2006.257.18:58:14.88#ibcon#enter sib2, iclass 27, count 0 2006.257.18:58:14.88#ibcon#flushed, iclass 27, count 0 2006.257.18:58:14.88#ibcon#about to write, iclass 27, count 0 2006.257.18:58:14.88#ibcon#wrote, iclass 27, count 0 2006.257.18:58:14.88#ibcon#about to read 3, iclass 27, count 0 2006.257.18:58:14.91#ibcon#read 3, iclass 27, count 0 2006.257.18:58:14.91#ibcon#about to read 4, iclass 27, count 0 2006.257.18:58:14.91#ibcon#read 4, iclass 27, count 0 2006.257.18:58:14.91#ibcon#about to read 5, iclass 27, count 0 2006.257.18:58:14.91#ibcon#read 5, iclass 27, count 0 2006.257.18:58:14.91#ibcon#about to read 6, iclass 27, count 0 2006.257.18:58:14.91#ibcon#read 6, iclass 27, count 0 2006.257.18:58:14.91#ibcon#end of sib2, iclass 27, count 0 2006.257.18:58:14.91#ibcon#*after write, iclass 27, count 0 2006.257.18:58:14.91#ibcon#*before return 0, iclass 27, count 0 2006.257.18:58:14.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:14.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:14.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:58:14.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:58:14.91$vck44/valo=8,884.99 2006.257.18:58:14.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.18:58:14.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.18:58:14.91#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:14.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:14.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:14.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:14.91#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:58:14.91#ibcon#first serial, iclass 29, count 0 2006.257.18:58:14.91#ibcon#enter sib2, iclass 29, count 0 2006.257.18:58:14.91#ibcon#flushed, iclass 29, count 0 2006.257.18:58:14.91#ibcon#about to write, iclass 29, count 0 2006.257.18:58:14.91#ibcon#wrote, iclass 29, count 0 2006.257.18:58:14.91#ibcon#about to read 3, iclass 29, count 0 2006.257.18:58:14.93#ibcon#read 3, iclass 29, count 0 2006.257.18:58:14.93#ibcon#about to read 4, iclass 29, count 0 2006.257.18:58:14.93#ibcon#read 4, iclass 29, count 0 2006.257.18:58:14.93#ibcon#about to read 5, iclass 29, count 0 2006.257.18:58:14.93#ibcon#read 5, iclass 29, count 0 2006.257.18:58:14.93#ibcon#about to read 6, iclass 29, count 0 2006.257.18:58:14.93#ibcon#read 6, iclass 29, count 0 2006.257.18:58:14.93#ibcon#end of sib2, iclass 29, count 0 2006.257.18:58:14.93#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:58:14.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:58:14.93#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.18:58:14.93#ibcon#*before write, iclass 29, count 0 2006.257.18:58:14.93#ibcon#enter sib2, iclass 29, count 0 2006.257.18:58:14.93#ibcon#flushed, iclass 29, count 0 2006.257.18:58:14.93#ibcon#about to write, iclass 29, count 0 2006.257.18:58:14.93#ibcon#wrote, iclass 29, count 0 2006.257.18:58:14.93#ibcon#about to read 3, iclass 29, count 0 2006.257.18:58:14.97#ibcon#read 3, iclass 29, count 0 2006.257.18:58:14.97#ibcon#about to read 4, iclass 29, count 0 2006.257.18:58:14.97#ibcon#read 4, iclass 29, count 0 2006.257.18:58:14.97#ibcon#about to read 5, iclass 29, count 0 2006.257.18:58:14.97#ibcon#read 5, iclass 29, count 0 2006.257.18:58:14.97#ibcon#about to read 6, iclass 29, count 0 2006.257.18:58:14.97#ibcon#read 6, iclass 29, count 0 2006.257.18:58:14.97#ibcon#end of sib2, iclass 29, count 0 2006.257.18:58:14.97#ibcon#*after write, iclass 29, count 0 2006.257.18:58:14.97#ibcon#*before return 0, iclass 29, count 0 2006.257.18:58:14.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:14.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:14.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:58:14.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:58:14.97$vck44/va=8,4 2006.257.18:58:14.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.18:58:14.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.18:58:14.97#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:14.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:58:15.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:58:15.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:58:15.03#ibcon#enter wrdev, iclass 31, count 2 2006.257.18:58:15.03#ibcon#first serial, iclass 31, count 2 2006.257.18:58:15.03#ibcon#enter sib2, iclass 31, count 2 2006.257.18:58:15.03#ibcon#flushed, iclass 31, count 2 2006.257.18:58:15.03#ibcon#about to write, iclass 31, count 2 2006.257.18:58:15.03#ibcon#wrote, iclass 31, count 2 2006.257.18:58:15.03#ibcon#about to read 3, iclass 31, count 2 2006.257.18:58:15.05#ibcon#read 3, iclass 31, count 2 2006.257.18:58:15.05#ibcon#about to read 4, iclass 31, count 2 2006.257.18:58:15.05#ibcon#read 4, iclass 31, count 2 2006.257.18:58:15.05#ibcon#about to read 5, iclass 31, count 2 2006.257.18:58:15.05#ibcon#read 5, iclass 31, count 2 2006.257.18:58:15.05#ibcon#about to read 6, iclass 31, count 2 2006.257.18:58:15.05#ibcon#read 6, iclass 31, count 2 2006.257.18:58:15.05#ibcon#end of sib2, iclass 31, count 2 2006.257.18:58:15.05#ibcon#*mode == 0, iclass 31, count 2 2006.257.18:58:15.05#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.18:58:15.05#ibcon#[25=AT08-04\r\n] 2006.257.18:58:15.05#ibcon#*before write, iclass 31, count 2 2006.257.18:58:15.05#ibcon#enter sib2, iclass 31, count 2 2006.257.18:58:15.05#ibcon#flushed, iclass 31, count 2 2006.257.18:58:15.05#ibcon#about to write, iclass 31, count 2 2006.257.18:58:15.05#ibcon#wrote, iclass 31, count 2 2006.257.18:58:15.05#ibcon#about to read 3, iclass 31, count 2 2006.257.18:58:15.08#ibcon#read 3, iclass 31, count 2 2006.257.18:58:15.08#ibcon#about to read 4, iclass 31, count 2 2006.257.18:58:15.08#ibcon#read 4, iclass 31, count 2 2006.257.18:58:15.08#ibcon#about to read 5, iclass 31, count 2 2006.257.18:58:15.08#ibcon#read 5, iclass 31, count 2 2006.257.18:58:15.08#ibcon#about to read 6, iclass 31, count 2 2006.257.18:58:15.08#ibcon#read 6, iclass 31, count 2 2006.257.18:58:15.08#ibcon#end of sib2, iclass 31, count 2 2006.257.18:58:15.08#ibcon#*after write, iclass 31, count 2 2006.257.18:58:15.08#ibcon#*before return 0, iclass 31, count 2 2006.257.18:58:15.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:58:15.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.18:58:15.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.18:58:15.08#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:15.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:58:15.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:58:15.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:58:15.20#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:58:15.20#ibcon#first serial, iclass 31, count 0 2006.257.18:58:15.20#ibcon#enter sib2, iclass 31, count 0 2006.257.18:58:15.20#ibcon#flushed, iclass 31, count 0 2006.257.18:58:15.20#ibcon#about to write, iclass 31, count 0 2006.257.18:58:15.20#ibcon#wrote, iclass 31, count 0 2006.257.18:58:15.20#ibcon#about to read 3, iclass 31, count 0 2006.257.18:58:15.22#ibcon#read 3, iclass 31, count 0 2006.257.18:58:15.22#ibcon#about to read 4, iclass 31, count 0 2006.257.18:58:15.22#ibcon#read 4, iclass 31, count 0 2006.257.18:58:15.22#ibcon#about to read 5, iclass 31, count 0 2006.257.18:58:15.22#ibcon#read 5, iclass 31, count 0 2006.257.18:58:15.22#ibcon#about to read 6, iclass 31, count 0 2006.257.18:58:15.22#ibcon#read 6, iclass 31, count 0 2006.257.18:58:15.22#ibcon#end of sib2, iclass 31, count 0 2006.257.18:58:15.22#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:58:15.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:58:15.22#ibcon#[25=USB\r\n] 2006.257.18:58:15.22#ibcon#*before write, iclass 31, count 0 2006.257.18:58:15.22#ibcon#enter sib2, iclass 31, count 0 2006.257.18:58:15.22#ibcon#flushed, iclass 31, count 0 2006.257.18:58:15.22#ibcon#about to write, iclass 31, count 0 2006.257.18:58:15.22#ibcon#wrote, iclass 31, count 0 2006.257.18:58:15.22#ibcon#about to read 3, iclass 31, count 0 2006.257.18:58:15.25#ibcon#read 3, iclass 31, count 0 2006.257.18:58:15.25#ibcon#about to read 4, iclass 31, count 0 2006.257.18:58:15.25#ibcon#read 4, iclass 31, count 0 2006.257.18:58:15.25#ibcon#about to read 5, iclass 31, count 0 2006.257.18:58:15.25#ibcon#read 5, iclass 31, count 0 2006.257.18:58:15.25#ibcon#about to read 6, iclass 31, count 0 2006.257.18:58:15.25#ibcon#read 6, iclass 31, count 0 2006.257.18:58:15.25#ibcon#end of sib2, iclass 31, count 0 2006.257.18:58:15.25#ibcon#*after write, iclass 31, count 0 2006.257.18:58:15.25#ibcon#*before return 0, iclass 31, count 0 2006.257.18:58:15.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:58:15.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.18:58:15.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:58:15.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:58:15.25$vck44/vblo=1,629.99 2006.257.18:58:15.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.18:58:15.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.18:58:15.25#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:15.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:58:15.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:58:15.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:58:15.25#ibcon#enter wrdev, iclass 33, count 0 2006.257.18:58:15.25#ibcon#first serial, iclass 33, count 0 2006.257.18:58:15.25#ibcon#enter sib2, iclass 33, count 0 2006.257.18:58:15.25#ibcon#flushed, iclass 33, count 0 2006.257.18:58:15.25#ibcon#about to write, iclass 33, count 0 2006.257.18:58:15.25#ibcon#wrote, iclass 33, count 0 2006.257.18:58:15.25#ibcon#about to read 3, iclass 33, count 0 2006.257.18:58:15.27#ibcon#read 3, iclass 33, count 0 2006.257.18:58:15.27#ibcon#about to read 4, iclass 33, count 0 2006.257.18:58:15.27#ibcon#read 4, iclass 33, count 0 2006.257.18:58:15.27#ibcon#about to read 5, iclass 33, count 0 2006.257.18:58:15.27#ibcon#read 5, iclass 33, count 0 2006.257.18:58:15.27#ibcon#about to read 6, iclass 33, count 0 2006.257.18:58:15.27#ibcon#read 6, iclass 33, count 0 2006.257.18:58:15.27#ibcon#end of sib2, iclass 33, count 0 2006.257.18:58:15.27#ibcon#*mode == 0, iclass 33, count 0 2006.257.18:58:15.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.18:58:15.27#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.18:58:15.27#ibcon#*before write, iclass 33, count 0 2006.257.18:58:15.27#ibcon#enter sib2, iclass 33, count 0 2006.257.18:58:15.27#ibcon#flushed, iclass 33, count 0 2006.257.18:58:15.27#ibcon#about to write, iclass 33, count 0 2006.257.18:58:15.27#ibcon#wrote, iclass 33, count 0 2006.257.18:58:15.27#ibcon#about to read 3, iclass 33, count 0 2006.257.18:58:15.31#ibcon#read 3, iclass 33, count 0 2006.257.18:58:15.31#ibcon#about to read 4, iclass 33, count 0 2006.257.18:58:15.31#ibcon#read 4, iclass 33, count 0 2006.257.18:58:15.31#ibcon#about to read 5, iclass 33, count 0 2006.257.18:58:15.31#ibcon#read 5, iclass 33, count 0 2006.257.18:58:15.31#ibcon#about to read 6, iclass 33, count 0 2006.257.18:58:15.31#ibcon#read 6, iclass 33, count 0 2006.257.18:58:15.31#ibcon#end of sib2, iclass 33, count 0 2006.257.18:58:15.31#ibcon#*after write, iclass 33, count 0 2006.257.18:58:15.31#ibcon#*before return 0, iclass 33, count 0 2006.257.18:58:15.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:58:15.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.18:58:15.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.18:58:15.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.18:58:15.31$vck44/vb=1,4 2006.257.18:58:15.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.18:58:15.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.18:58:15.31#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:15.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:58:15.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:58:15.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:58:15.31#ibcon#enter wrdev, iclass 35, count 2 2006.257.18:58:15.31#ibcon#first serial, iclass 35, count 2 2006.257.18:58:15.31#ibcon#enter sib2, iclass 35, count 2 2006.257.18:58:15.31#ibcon#flushed, iclass 35, count 2 2006.257.18:58:15.31#ibcon#about to write, iclass 35, count 2 2006.257.18:58:15.31#ibcon#wrote, iclass 35, count 2 2006.257.18:58:15.31#ibcon#about to read 3, iclass 35, count 2 2006.257.18:58:15.33#ibcon#read 3, iclass 35, count 2 2006.257.18:58:15.33#ibcon#about to read 4, iclass 35, count 2 2006.257.18:58:15.33#ibcon#read 4, iclass 35, count 2 2006.257.18:58:15.33#ibcon#about to read 5, iclass 35, count 2 2006.257.18:58:15.33#ibcon#read 5, iclass 35, count 2 2006.257.18:58:15.33#ibcon#about to read 6, iclass 35, count 2 2006.257.18:58:15.33#ibcon#read 6, iclass 35, count 2 2006.257.18:58:15.33#ibcon#end of sib2, iclass 35, count 2 2006.257.18:58:15.33#ibcon#*mode == 0, iclass 35, count 2 2006.257.18:58:15.33#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.18:58:15.33#ibcon#[27=AT01-04\r\n] 2006.257.18:58:15.33#ibcon#*before write, iclass 35, count 2 2006.257.18:58:15.33#ibcon#enter sib2, iclass 35, count 2 2006.257.18:58:15.33#ibcon#flushed, iclass 35, count 2 2006.257.18:58:15.33#ibcon#about to write, iclass 35, count 2 2006.257.18:58:15.33#ibcon#wrote, iclass 35, count 2 2006.257.18:58:15.33#ibcon#about to read 3, iclass 35, count 2 2006.257.18:58:15.36#ibcon#read 3, iclass 35, count 2 2006.257.18:58:15.36#ibcon#about to read 4, iclass 35, count 2 2006.257.18:58:15.36#ibcon#read 4, iclass 35, count 2 2006.257.18:58:15.36#ibcon#about to read 5, iclass 35, count 2 2006.257.18:58:15.36#ibcon#read 5, iclass 35, count 2 2006.257.18:58:15.36#ibcon#about to read 6, iclass 35, count 2 2006.257.18:58:15.36#ibcon#read 6, iclass 35, count 2 2006.257.18:58:15.36#ibcon#end of sib2, iclass 35, count 2 2006.257.18:58:15.36#ibcon#*after write, iclass 35, count 2 2006.257.18:58:15.36#ibcon#*before return 0, iclass 35, count 2 2006.257.18:58:15.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:58:15.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.18:58:15.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.18:58:15.36#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:15.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:58:15.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:58:15.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:58:15.48#ibcon#enter wrdev, iclass 35, count 0 2006.257.18:58:15.48#ibcon#first serial, iclass 35, count 0 2006.257.18:58:15.48#ibcon#enter sib2, iclass 35, count 0 2006.257.18:58:15.48#ibcon#flushed, iclass 35, count 0 2006.257.18:58:15.48#ibcon#about to write, iclass 35, count 0 2006.257.18:58:15.48#ibcon#wrote, iclass 35, count 0 2006.257.18:58:15.48#ibcon#about to read 3, iclass 35, count 0 2006.257.18:58:15.50#ibcon#read 3, iclass 35, count 0 2006.257.18:58:15.50#ibcon#about to read 4, iclass 35, count 0 2006.257.18:58:15.50#ibcon#read 4, iclass 35, count 0 2006.257.18:58:15.50#ibcon#about to read 5, iclass 35, count 0 2006.257.18:58:15.50#ibcon#read 5, iclass 35, count 0 2006.257.18:58:15.50#ibcon#about to read 6, iclass 35, count 0 2006.257.18:58:15.50#ibcon#read 6, iclass 35, count 0 2006.257.18:58:15.50#ibcon#end of sib2, iclass 35, count 0 2006.257.18:58:15.50#ibcon#*mode == 0, iclass 35, count 0 2006.257.18:58:15.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.18:58:15.50#ibcon#[27=USB\r\n] 2006.257.18:58:15.50#ibcon#*before write, iclass 35, count 0 2006.257.18:58:15.50#ibcon#enter sib2, iclass 35, count 0 2006.257.18:58:15.50#ibcon#flushed, iclass 35, count 0 2006.257.18:58:15.50#ibcon#about to write, iclass 35, count 0 2006.257.18:58:15.50#ibcon#wrote, iclass 35, count 0 2006.257.18:58:15.50#ibcon#about to read 3, iclass 35, count 0 2006.257.18:58:15.53#ibcon#read 3, iclass 35, count 0 2006.257.18:58:15.53#ibcon#about to read 4, iclass 35, count 0 2006.257.18:58:15.53#ibcon#read 4, iclass 35, count 0 2006.257.18:58:15.53#ibcon#about to read 5, iclass 35, count 0 2006.257.18:58:15.53#ibcon#read 5, iclass 35, count 0 2006.257.18:58:15.53#ibcon#about to read 6, iclass 35, count 0 2006.257.18:58:15.53#ibcon#read 6, iclass 35, count 0 2006.257.18:58:15.53#ibcon#end of sib2, iclass 35, count 0 2006.257.18:58:15.53#ibcon#*after write, iclass 35, count 0 2006.257.18:58:15.53#ibcon#*before return 0, iclass 35, count 0 2006.257.18:58:15.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:58:15.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.18:58:15.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.18:58:15.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.18:58:15.53$vck44/vblo=2,634.99 2006.257.18:58:15.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.18:58:15.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.18:58:15.53#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:15.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:15.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:15.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:15.53#ibcon#enter wrdev, iclass 37, count 0 2006.257.18:58:15.53#ibcon#first serial, iclass 37, count 0 2006.257.18:58:15.53#ibcon#enter sib2, iclass 37, count 0 2006.257.18:58:15.53#ibcon#flushed, iclass 37, count 0 2006.257.18:58:15.53#ibcon#about to write, iclass 37, count 0 2006.257.18:58:15.53#ibcon#wrote, iclass 37, count 0 2006.257.18:58:15.53#ibcon#about to read 3, iclass 37, count 0 2006.257.18:58:15.55#ibcon#read 3, iclass 37, count 0 2006.257.18:58:15.55#ibcon#about to read 4, iclass 37, count 0 2006.257.18:58:15.55#ibcon#read 4, iclass 37, count 0 2006.257.18:58:15.55#ibcon#about to read 5, iclass 37, count 0 2006.257.18:58:15.55#ibcon#read 5, iclass 37, count 0 2006.257.18:58:15.55#ibcon#about to read 6, iclass 37, count 0 2006.257.18:58:15.55#ibcon#read 6, iclass 37, count 0 2006.257.18:58:15.55#ibcon#end of sib2, iclass 37, count 0 2006.257.18:58:15.55#ibcon#*mode == 0, iclass 37, count 0 2006.257.18:58:15.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.18:58:15.55#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.18:58:15.55#ibcon#*before write, iclass 37, count 0 2006.257.18:58:15.55#ibcon#enter sib2, iclass 37, count 0 2006.257.18:58:15.55#ibcon#flushed, iclass 37, count 0 2006.257.18:58:15.55#ibcon#about to write, iclass 37, count 0 2006.257.18:58:15.55#ibcon#wrote, iclass 37, count 0 2006.257.18:58:15.55#ibcon#about to read 3, iclass 37, count 0 2006.257.18:58:15.59#ibcon#read 3, iclass 37, count 0 2006.257.18:58:15.59#ibcon#about to read 4, iclass 37, count 0 2006.257.18:58:15.59#ibcon#read 4, iclass 37, count 0 2006.257.18:58:15.59#ibcon#about to read 5, iclass 37, count 0 2006.257.18:58:15.59#ibcon#read 5, iclass 37, count 0 2006.257.18:58:15.59#ibcon#about to read 6, iclass 37, count 0 2006.257.18:58:15.59#ibcon#read 6, iclass 37, count 0 2006.257.18:58:15.59#ibcon#end of sib2, iclass 37, count 0 2006.257.18:58:15.59#ibcon#*after write, iclass 37, count 0 2006.257.18:58:15.59#ibcon#*before return 0, iclass 37, count 0 2006.257.18:58:15.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:15.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.18:58:15.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.18:58:15.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.18:58:15.59$vck44/vb=2,5 2006.257.18:58:15.59#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.18:58:15.59#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.18:58:15.59#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:15.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:15.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:15.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:15.65#ibcon#enter wrdev, iclass 39, count 2 2006.257.18:58:15.65#ibcon#first serial, iclass 39, count 2 2006.257.18:58:15.65#ibcon#enter sib2, iclass 39, count 2 2006.257.18:58:15.65#ibcon#flushed, iclass 39, count 2 2006.257.18:58:15.65#ibcon#about to write, iclass 39, count 2 2006.257.18:58:15.65#ibcon#wrote, iclass 39, count 2 2006.257.18:58:15.65#ibcon#about to read 3, iclass 39, count 2 2006.257.18:58:15.67#ibcon#read 3, iclass 39, count 2 2006.257.18:58:15.67#ibcon#about to read 4, iclass 39, count 2 2006.257.18:58:15.67#ibcon#read 4, iclass 39, count 2 2006.257.18:58:15.67#ibcon#about to read 5, iclass 39, count 2 2006.257.18:58:15.67#ibcon#read 5, iclass 39, count 2 2006.257.18:58:15.67#ibcon#about to read 6, iclass 39, count 2 2006.257.18:58:15.67#ibcon#read 6, iclass 39, count 2 2006.257.18:58:15.67#ibcon#end of sib2, iclass 39, count 2 2006.257.18:58:15.67#ibcon#*mode == 0, iclass 39, count 2 2006.257.18:58:15.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.18:58:15.67#ibcon#[27=AT02-05\r\n] 2006.257.18:58:15.67#ibcon#*before write, iclass 39, count 2 2006.257.18:58:15.67#ibcon#enter sib2, iclass 39, count 2 2006.257.18:58:15.67#ibcon#flushed, iclass 39, count 2 2006.257.18:58:15.67#ibcon#about to write, iclass 39, count 2 2006.257.18:58:15.67#ibcon#wrote, iclass 39, count 2 2006.257.18:58:15.67#ibcon#about to read 3, iclass 39, count 2 2006.257.18:58:15.70#ibcon#read 3, iclass 39, count 2 2006.257.18:58:15.70#ibcon#about to read 4, iclass 39, count 2 2006.257.18:58:15.70#ibcon#read 4, iclass 39, count 2 2006.257.18:58:15.70#ibcon#about to read 5, iclass 39, count 2 2006.257.18:58:15.70#ibcon#read 5, iclass 39, count 2 2006.257.18:58:15.70#ibcon#about to read 6, iclass 39, count 2 2006.257.18:58:15.70#ibcon#read 6, iclass 39, count 2 2006.257.18:58:15.70#ibcon#end of sib2, iclass 39, count 2 2006.257.18:58:15.70#ibcon#*after write, iclass 39, count 2 2006.257.18:58:15.70#ibcon#*before return 0, iclass 39, count 2 2006.257.18:58:15.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:15.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.18:58:15.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.18:58:15.70#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:15.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:15.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:15.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:15.82#ibcon#enter wrdev, iclass 39, count 0 2006.257.18:58:15.82#ibcon#first serial, iclass 39, count 0 2006.257.18:58:15.82#ibcon#enter sib2, iclass 39, count 0 2006.257.18:58:15.82#ibcon#flushed, iclass 39, count 0 2006.257.18:58:15.82#ibcon#about to write, iclass 39, count 0 2006.257.18:58:15.82#ibcon#wrote, iclass 39, count 0 2006.257.18:58:15.82#ibcon#about to read 3, iclass 39, count 0 2006.257.18:58:15.84#ibcon#read 3, iclass 39, count 0 2006.257.18:58:15.84#ibcon#about to read 4, iclass 39, count 0 2006.257.18:58:15.84#ibcon#read 4, iclass 39, count 0 2006.257.18:58:15.84#ibcon#about to read 5, iclass 39, count 0 2006.257.18:58:15.84#ibcon#read 5, iclass 39, count 0 2006.257.18:58:15.84#ibcon#about to read 6, iclass 39, count 0 2006.257.18:58:15.84#ibcon#read 6, iclass 39, count 0 2006.257.18:58:15.84#ibcon#end of sib2, iclass 39, count 0 2006.257.18:58:15.84#ibcon#*mode == 0, iclass 39, count 0 2006.257.18:58:15.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.18:58:15.84#ibcon#[27=USB\r\n] 2006.257.18:58:15.84#ibcon#*before write, iclass 39, count 0 2006.257.18:58:15.84#ibcon#enter sib2, iclass 39, count 0 2006.257.18:58:15.84#ibcon#flushed, iclass 39, count 0 2006.257.18:58:15.84#ibcon#about to write, iclass 39, count 0 2006.257.18:58:15.84#ibcon#wrote, iclass 39, count 0 2006.257.18:58:15.84#ibcon#about to read 3, iclass 39, count 0 2006.257.18:58:15.87#ibcon#read 3, iclass 39, count 0 2006.257.18:58:15.87#ibcon#about to read 4, iclass 39, count 0 2006.257.18:58:15.87#ibcon#read 4, iclass 39, count 0 2006.257.18:58:15.87#ibcon#about to read 5, iclass 39, count 0 2006.257.18:58:15.87#ibcon#read 5, iclass 39, count 0 2006.257.18:58:15.87#ibcon#about to read 6, iclass 39, count 0 2006.257.18:58:15.87#ibcon#read 6, iclass 39, count 0 2006.257.18:58:15.87#ibcon#end of sib2, iclass 39, count 0 2006.257.18:58:15.87#ibcon#*after write, iclass 39, count 0 2006.257.18:58:15.87#ibcon#*before return 0, iclass 39, count 0 2006.257.18:58:15.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:15.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.18:58:15.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.18:58:15.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.18:58:15.87$vck44/vblo=3,649.99 2006.257.18:58:15.87#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.18:58:15.87#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.18:58:15.87#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:15.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:15.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:15.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:15.87#ibcon#enter wrdev, iclass 3, count 0 2006.257.18:58:15.87#ibcon#first serial, iclass 3, count 0 2006.257.18:58:15.87#ibcon#enter sib2, iclass 3, count 0 2006.257.18:58:15.87#ibcon#flushed, iclass 3, count 0 2006.257.18:58:15.87#ibcon#about to write, iclass 3, count 0 2006.257.18:58:15.87#ibcon#wrote, iclass 3, count 0 2006.257.18:58:15.87#ibcon#about to read 3, iclass 3, count 0 2006.257.18:58:15.89#ibcon#read 3, iclass 3, count 0 2006.257.18:58:15.89#ibcon#about to read 4, iclass 3, count 0 2006.257.18:58:15.89#ibcon#read 4, iclass 3, count 0 2006.257.18:58:15.89#ibcon#about to read 5, iclass 3, count 0 2006.257.18:58:15.89#ibcon#read 5, iclass 3, count 0 2006.257.18:58:15.89#ibcon#about to read 6, iclass 3, count 0 2006.257.18:58:15.89#ibcon#read 6, iclass 3, count 0 2006.257.18:58:15.89#ibcon#end of sib2, iclass 3, count 0 2006.257.18:58:15.89#ibcon#*mode == 0, iclass 3, count 0 2006.257.18:58:15.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.18:58:15.89#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.18:58:15.89#ibcon#*before write, iclass 3, count 0 2006.257.18:58:15.89#ibcon#enter sib2, iclass 3, count 0 2006.257.18:58:15.89#ibcon#flushed, iclass 3, count 0 2006.257.18:58:15.89#ibcon#about to write, iclass 3, count 0 2006.257.18:58:15.89#ibcon#wrote, iclass 3, count 0 2006.257.18:58:15.89#ibcon#about to read 3, iclass 3, count 0 2006.257.18:58:15.93#ibcon#read 3, iclass 3, count 0 2006.257.18:58:15.93#ibcon#about to read 4, iclass 3, count 0 2006.257.18:58:15.93#ibcon#read 4, iclass 3, count 0 2006.257.18:58:15.93#ibcon#about to read 5, iclass 3, count 0 2006.257.18:58:15.93#ibcon#read 5, iclass 3, count 0 2006.257.18:58:15.93#ibcon#about to read 6, iclass 3, count 0 2006.257.18:58:15.93#ibcon#read 6, iclass 3, count 0 2006.257.18:58:15.93#ibcon#end of sib2, iclass 3, count 0 2006.257.18:58:15.93#ibcon#*after write, iclass 3, count 0 2006.257.18:58:15.93#ibcon#*before return 0, iclass 3, count 0 2006.257.18:58:15.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:15.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.18:58:15.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.18:58:15.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.18:58:15.93$vck44/vb=3,4 2006.257.18:58:15.93#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.18:58:15.93#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.18:58:15.93#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:15.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:15.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:15.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:15.99#ibcon#enter wrdev, iclass 5, count 2 2006.257.18:58:15.99#ibcon#first serial, iclass 5, count 2 2006.257.18:58:15.99#ibcon#enter sib2, iclass 5, count 2 2006.257.18:58:15.99#ibcon#flushed, iclass 5, count 2 2006.257.18:58:15.99#ibcon#about to write, iclass 5, count 2 2006.257.18:58:15.99#ibcon#wrote, iclass 5, count 2 2006.257.18:58:15.99#ibcon#about to read 3, iclass 5, count 2 2006.257.18:58:16.01#ibcon#read 3, iclass 5, count 2 2006.257.18:58:16.01#ibcon#about to read 4, iclass 5, count 2 2006.257.18:58:16.01#ibcon#read 4, iclass 5, count 2 2006.257.18:58:16.01#ibcon#about to read 5, iclass 5, count 2 2006.257.18:58:16.01#ibcon#read 5, iclass 5, count 2 2006.257.18:58:16.01#ibcon#about to read 6, iclass 5, count 2 2006.257.18:58:16.01#ibcon#read 6, iclass 5, count 2 2006.257.18:58:16.01#ibcon#end of sib2, iclass 5, count 2 2006.257.18:58:16.01#ibcon#*mode == 0, iclass 5, count 2 2006.257.18:58:16.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.18:58:16.01#ibcon#[27=AT03-04\r\n] 2006.257.18:58:16.01#ibcon#*before write, iclass 5, count 2 2006.257.18:58:16.01#ibcon#enter sib2, iclass 5, count 2 2006.257.18:58:16.01#ibcon#flushed, iclass 5, count 2 2006.257.18:58:16.01#ibcon#about to write, iclass 5, count 2 2006.257.18:58:16.01#ibcon#wrote, iclass 5, count 2 2006.257.18:58:16.01#ibcon#about to read 3, iclass 5, count 2 2006.257.18:58:16.04#ibcon#read 3, iclass 5, count 2 2006.257.18:58:16.04#ibcon#about to read 4, iclass 5, count 2 2006.257.18:58:16.04#ibcon#read 4, iclass 5, count 2 2006.257.18:58:16.04#ibcon#about to read 5, iclass 5, count 2 2006.257.18:58:16.04#ibcon#read 5, iclass 5, count 2 2006.257.18:58:16.04#ibcon#about to read 6, iclass 5, count 2 2006.257.18:58:16.04#ibcon#read 6, iclass 5, count 2 2006.257.18:58:16.04#ibcon#end of sib2, iclass 5, count 2 2006.257.18:58:16.04#ibcon#*after write, iclass 5, count 2 2006.257.18:58:16.04#ibcon#*before return 0, iclass 5, count 2 2006.257.18:58:16.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:16.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.18:58:16.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.18:58:16.04#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:16.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:16.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:16.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:16.16#ibcon#enter wrdev, iclass 5, count 0 2006.257.18:58:16.16#ibcon#first serial, iclass 5, count 0 2006.257.18:58:16.16#ibcon#enter sib2, iclass 5, count 0 2006.257.18:58:16.16#ibcon#flushed, iclass 5, count 0 2006.257.18:58:16.16#ibcon#about to write, iclass 5, count 0 2006.257.18:58:16.16#ibcon#wrote, iclass 5, count 0 2006.257.18:58:16.16#ibcon#about to read 3, iclass 5, count 0 2006.257.18:58:16.18#ibcon#read 3, iclass 5, count 0 2006.257.18:58:16.18#ibcon#about to read 4, iclass 5, count 0 2006.257.18:58:16.18#ibcon#read 4, iclass 5, count 0 2006.257.18:58:16.18#ibcon#about to read 5, iclass 5, count 0 2006.257.18:58:16.18#ibcon#read 5, iclass 5, count 0 2006.257.18:58:16.18#ibcon#about to read 6, iclass 5, count 0 2006.257.18:58:16.18#ibcon#read 6, iclass 5, count 0 2006.257.18:58:16.18#ibcon#end of sib2, iclass 5, count 0 2006.257.18:58:16.18#ibcon#*mode == 0, iclass 5, count 0 2006.257.18:58:16.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.18:58:16.18#ibcon#[27=USB\r\n] 2006.257.18:58:16.18#ibcon#*before write, iclass 5, count 0 2006.257.18:58:16.18#ibcon#enter sib2, iclass 5, count 0 2006.257.18:58:16.18#ibcon#flushed, iclass 5, count 0 2006.257.18:58:16.18#ibcon#about to write, iclass 5, count 0 2006.257.18:58:16.18#ibcon#wrote, iclass 5, count 0 2006.257.18:58:16.18#ibcon#about to read 3, iclass 5, count 0 2006.257.18:58:16.21#ibcon#read 3, iclass 5, count 0 2006.257.18:58:16.21#ibcon#about to read 4, iclass 5, count 0 2006.257.18:58:16.21#ibcon#read 4, iclass 5, count 0 2006.257.18:58:16.21#ibcon#about to read 5, iclass 5, count 0 2006.257.18:58:16.21#ibcon#read 5, iclass 5, count 0 2006.257.18:58:16.21#ibcon#about to read 6, iclass 5, count 0 2006.257.18:58:16.21#ibcon#read 6, iclass 5, count 0 2006.257.18:58:16.21#ibcon#end of sib2, iclass 5, count 0 2006.257.18:58:16.21#ibcon#*after write, iclass 5, count 0 2006.257.18:58:16.21#ibcon#*before return 0, iclass 5, count 0 2006.257.18:58:16.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:16.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.18:58:16.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.18:58:16.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.18:58:16.21$vck44/vblo=4,679.99 2006.257.18:58:16.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.18:58:16.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.18:58:16.21#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:16.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:16.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:16.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:16.21#ibcon#enter wrdev, iclass 7, count 0 2006.257.18:58:16.21#ibcon#first serial, iclass 7, count 0 2006.257.18:58:16.21#ibcon#enter sib2, iclass 7, count 0 2006.257.18:58:16.21#ibcon#flushed, iclass 7, count 0 2006.257.18:58:16.21#ibcon#about to write, iclass 7, count 0 2006.257.18:58:16.21#ibcon#wrote, iclass 7, count 0 2006.257.18:58:16.21#ibcon#about to read 3, iclass 7, count 0 2006.257.18:58:16.23#ibcon#read 3, iclass 7, count 0 2006.257.18:58:16.23#ibcon#about to read 4, iclass 7, count 0 2006.257.18:58:16.23#ibcon#read 4, iclass 7, count 0 2006.257.18:58:16.23#ibcon#about to read 5, iclass 7, count 0 2006.257.18:58:16.23#ibcon#read 5, iclass 7, count 0 2006.257.18:58:16.23#ibcon#about to read 6, iclass 7, count 0 2006.257.18:58:16.23#ibcon#read 6, iclass 7, count 0 2006.257.18:58:16.23#ibcon#end of sib2, iclass 7, count 0 2006.257.18:58:16.23#ibcon#*mode == 0, iclass 7, count 0 2006.257.18:58:16.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.18:58:16.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.18:58:16.23#ibcon#*before write, iclass 7, count 0 2006.257.18:58:16.23#ibcon#enter sib2, iclass 7, count 0 2006.257.18:58:16.23#ibcon#flushed, iclass 7, count 0 2006.257.18:58:16.23#ibcon#about to write, iclass 7, count 0 2006.257.18:58:16.23#ibcon#wrote, iclass 7, count 0 2006.257.18:58:16.23#ibcon#about to read 3, iclass 7, count 0 2006.257.18:58:16.27#ibcon#read 3, iclass 7, count 0 2006.257.18:58:16.27#ibcon#about to read 4, iclass 7, count 0 2006.257.18:58:16.27#ibcon#read 4, iclass 7, count 0 2006.257.18:58:16.27#ibcon#about to read 5, iclass 7, count 0 2006.257.18:58:16.27#ibcon#read 5, iclass 7, count 0 2006.257.18:58:16.27#ibcon#about to read 6, iclass 7, count 0 2006.257.18:58:16.27#ibcon#read 6, iclass 7, count 0 2006.257.18:58:16.27#ibcon#end of sib2, iclass 7, count 0 2006.257.18:58:16.27#ibcon#*after write, iclass 7, count 0 2006.257.18:58:16.27#ibcon#*before return 0, iclass 7, count 0 2006.257.18:58:16.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:16.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.18:58:16.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.18:58:16.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.18:58:16.27$vck44/vb=4,5 2006.257.18:58:16.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.18:58:16.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.18:58:16.27#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:16.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:16.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:16.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:16.33#ibcon#enter wrdev, iclass 11, count 2 2006.257.18:58:16.33#ibcon#first serial, iclass 11, count 2 2006.257.18:58:16.33#ibcon#enter sib2, iclass 11, count 2 2006.257.18:58:16.33#ibcon#flushed, iclass 11, count 2 2006.257.18:58:16.33#ibcon#about to write, iclass 11, count 2 2006.257.18:58:16.33#ibcon#wrote, iclass 11, count 2 2006.257.18:58:16.33#ibcon#about to read 3, iclass 11, count 2 2006.257.18:58:16.35#ibcon#read 3, iclass 11, count 2 2006.257.18:58:16.35#ibcon#about to read 4, iclass 11, count 2 2006.257.18:58:16.35#ibcon#read 4, iclass 11, count 2 2006.257.18:58:16.35#ibcon#about to read 5, iclass 11, count 2 2006.257.18:58:16.35#ibcon#read 5, iclass 11, count 2 2006.257.18:58:16.35#ibcon#about to read 6, iclass 11, count 2 2006.257.18:58:16.35#ibcon#read 6, iclass 11, count 2 2006.257.18:58:16.35#ibcon#end of sib2, iclass 11, count 2 2006.257.18:58:16.35#ibcon#*mode == 0, iclass 11, count 2 2006.257.18:58:16.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.18:58:16.35#ibcon#[27=AT04-05\r\n] 2006.257.18:58:16.35#ibcon#*before write, iclass 11, count 2 2006.257.18:58:16.35#ibcon#enter sib2, iclass 11, count 2 2006.257.18:58:16.35#ibcon#flushed, iclass 11, count 2 2006.257.18:58:16.35#ibcon#about to write, iclass 11, count 2 2006.257.18:58:16.35#ibcon#wrote, iclass 11, count 2 2006.257.18:58:16.35#ibcon#about to read 3, iclass 11, count 2 2006.257.18:58:16.38#ibcon#read 3, iclass 11, count 2 2006.257.18:58:16.38#ibcon#about to read 4, iclass 11, count 2 2006.257.18:58:16.38#ibcon#read 4, iclass 11, count 2 2006.257.18:58:16.38#ibcon#about to read 5, iclass 11, count 2 2006.257.18:58:16.38#ibcon#read 5, iclass 11, count 2 2006.257.18:58:16.38#ibcon#about to read 6, iclass 11, count 2 2006.257.18:58:16.38#ibcon#read 6, iclass 11, count 2 2006.257.18:58:16.38#ibcon#end of sib2, iclass 11, count 2 2006.257.18:58:16.38#ibcon#*after write, iclass 11, count 2 2006.257.18:58:16.38#ibcon#*before return 0, iclass 11, count 2 2006.257.18:58:16.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:16.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.18:58:16.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.18:58:16.38#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:16.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:16.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:16.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:16.50#ibcon#enter wrdev, iclass 11, count 0 2006.257.18:58:16.50#ibcon#first serial, iclass 11, count 0 2006.257.18:58:16.50#ibcon#enter sib2, iclass 11, count 0 2006.257.18:58:16.50#ibcon#flushed, iclass 11, count 0 2006.257.18:58:16.50#ibcon#about to write, iclass 11, count 0 2006.257.18:58:16.50#ibcon#wrote, iclass 11, count 0 2006.257.18:58:16.50#ibcon#about to read 3, iclass 11, count 0 2006.257.18:58:16.52#ibcon#read 3, iclass 11, count 0 2006.257.18:58:16.52#ibcon#about to read 4, iclass 11, count 0 2006.257.18:58:16.52#ibcon#read 4, iclass 11, count 0 2006.257.18:58:16.52#ibcon#about to read 5, iclass 11, count 0 2006.257.18:58:16.52#ibcon#read 5, iclass 11, count 0 2006.257.18:58:16.52#ibcon#about to read 6, iclass 11, count 0 2006.257.18:58:16.52#ibcon#read 6, iclass 11, count 0 2006.257.18:58:16.52#ibcon#end of sib2, iclass 11, count 0 2006.257.18:58:16.52#ibcon#*mode == 0, iclass 11, count 0 2006.257.18:58:16.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.18:58:16.52#ibcon#[27=USB\r\n] 2006.257.18:58:16.52#ibcon#*before write, iclass 11, count 0 2006.257.18:58:16.52#ibcon#enter sib2, iclass 11, count 0 2006.257.18:58:16.52#ibcon#flushed, iclass 11, count 0 2006.257.18:58:16.52#ibcon#about to write, iclass 11, count 0 2006.257.18:58:16.52#ibcon#wrote, iclass 11, count 0 2006.257.18:58:16.52#ibcon#about to read 3, iclass 11, count 0 2006.257.18:58:16.55#ibcon#read 3, iclass 11, count 0 2006.257.18:58:16.55#ibcon#about to read 4, iclass 11, count 0 2006.257.18:58:16.55#ibcon#read 4, iclass 11, count 0 2006.257.18:58:16.55#ibcon#about to read 5, iclass 11, count 0 2006.257.18:58:16.55#ibcon#read 5, iclass 11, count 0 2006.257.18:58:16.55#ibcon#about to read 6, iclass 11, count 0 2006.257.18:58:16.55#ibcon#read 6, iclass 11, count 0 2006.257.18:58:16.55#ibcon#end of sib2, iclass 11, count 0 2006.257.18:58:16.55#ibcon#*after write, iclass 11, count 0 2006.257.18:58:16.55#ibcon#*before return 0, iclass 11, count 0 2006.257.18:58:16.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:16.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.18:58:16.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.18:58:16.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.18:58:16.55$vck44/vblo=5,709.99 2006.257.18:58:16.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.18:58:16.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.18:58:16.55#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:16.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:16.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:16.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:16.55#ibcon#enter wrdev, iclass 13, count 0 2006.257.18:58:16.55#ibcon#first serial, iclass 13, count 0 2006.257.18:58:16.55#ibcon#enter sib2, iclass 13, count 0 2006.257.18:58:16.55#ibcon#flushed, iclass 13, count 0 2006.257.18:58:16.55#ibcon#about to write, iclass 13, count 0 2006.257.18:58:16.55#ibcon#wrote, iclass 13, count 0 2006.257.18:58:16.55#ibcon#about to read 3, iclass 13, count 0 2006.257.18:58:16.57#ibcon#read 3, iclass 13, count 0 2006.257.18:58:16.57#ibcon#about to read 4, iclass 13, count 0 2006.257.18:58:16.57#ibcon#read 4, iclass 13, count 0 2006.257.18:58:16.57#ibcon#about to read 5, iclass 13, count 0 2006.257.18:58:16.57#ibcon#read 5, iclass 13, count 0 2006.257.18:58:16.57#ibcon#about to read 6, iclass 13, count 0 2006.257.18:58:16.57#ibcon#read 6, iclass 13, count 0 2006.257.18:58:16.57#ibcon#end of sib2, iclass 13, count 0 2006.257.18:58:16.57#ibcon#*mode == 0, iclass 13, count 0 2006.257.18:58:16.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.18:58:16.57#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.18:58:16.57#ibcon#*before write, iclass 13, count 0 2006.257.18:58:16.57#ibcon#enter sib2, iclass 13, count 0 2006.257.18:58:16.57#ibcon#flushed, iclass 13, count 0 2006.257.18:58:16.57#ibcon#about to write, iclass 13, count 0 2006.257.18:58:16.57#ibcon#wrote, iclass 13, count 0 2006.257.18:58:16.57#ibcon#about to read 3, iclass 13, count 0 2006.257.18:58:16.61#ibcon#read 3, iclass 13, count 0 2006.257.18:58:16.61#ibcon#about to read 4, iclass 13, count 0 2006.257.18:58:16.61#ibcon#read 4, iclass 13, count 0 2006.257.18:58:16.61#ibcon#about to read 5, iclass 13, count 0 2006.257.18:58:16.61#ibcon#read 5, iclass 13, count 0 2006.257.18:58:16.61#ibcon#about to read 6, iclass 13, count 0 2006.257.18:58:16.61#ibcon#read 6, iclass 13, count 0 2006.257.18:58:16.61#ibcon#end of sib2, iclass 13, count 0 2006.257.18:58:16.61#ibcon#*after write, iclass 13, count 0 2006.257.18:58:16.61#ibcon#*before return 0, iclass 13, count 0 2006.257.18:58:16.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:16.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.18:58:16.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.18:58:16.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.18:58:16.61$vck44/vb=5,4 2006.257.18:58:16.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.18:58:16.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.18:58:16.61#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:16.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:16.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:16.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:16.67#ibcon#enter wrdev, iclass 15, count 2 2006.257.18:58:16.67#ibcon#first serial, iclass 15, count 2 2006.257.18:58:16.67#ibcon#enter sib2, iclass 15, count 2 2006.257.18:58:16.67#ibcon#flushed, iclass 15, count 2 2006.257.18:58:16.67#ibcon#about to write, iclass 15, count 2 2006.257.18:58:16.67#ibcon#wrote, iclass 15, count 2 2006.257.18:58:16.67#ibcon#about to read 3, iclass 15, count 2 2006.257.18:58:16.69#ibcon#read 3, iclass 15, count 2 2006.257.18:58:16.69#ibcon#about to read 4, iclass 15, count 2 2006.257.18:58:16.69#ibcon#read 4, iclass 15, count 2 2006.257.18:58:16.69#ibcon#about to read 5, iclass 15, count 2 2006.257.18:58:16.69#ibcon#read 5, iclass 15, count 2 2006.257.18:58:16.69#ibcon#about to read 6, iclass 15, count 2 2006.257.18:58:16.69#ibcon#read 6, iclass 15, count 2 2006.257.18:58:16.69#ibcon#end of sib2, iclass 15, count 2 2006.257.18:58:16.69#ibcon#*mode == 0, iclass 15, count 2 2006.257.18:58:16.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.18:58:16.69#ibcon#[27=AT05-04\r\n] 2006.257.18:58:16.69#ibcon#*before write, iclass 15, count 2 2006.257.18:58:16.69#ibcon#enter sib2, iclass 15, count 2 2006.257.18:58:16.69#ibcon#flushed, iclass 15, count 2 2006.257.18:58:16.69#ibcon#about to write, iclass 15, count 2 2006.257.18:58:16.69#ibcon#wrote, iclass 15, count 2 2006.257.18:58:16.69#ibcon#about to read 3, iclass 15, count 2 2006.257.18:58:16.72#ibcon#read 3, iclass 15, count 2 2006.257.18:58:16.72#ibcon#about to read 4, iclass 15, count 2 2006.257.18:58:16.72#ibcon#read 4, iclass 15, count 2 2006.257.18:58:16.72#ibcon#about to read 5, iclass 15, count 2 2006.257.18:58:16.72#ibcon#read 5, iclass 15, count 2 2006.257.18:58:16.72#ibcon#about to read 6, iclass 15, count 2 2006.257.18:58:16.72#ibcon#read 6, iclass 15, count 2 2006.257.18:58:16.72#ibcon#end of sib2, iclass 15, count 2 2006.257.18:58:16.72#ibcon#*after write, iclass 15, count 2 2006.257.18:58:16.72#ibcon#*before return 0, iclass 15, count 2 2006.257.18:58:16.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:16.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.18:58:16.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.18:58:16.72#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:16.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:16.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:16.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:16.84#ibcon#enter wrdev, iclass 15, count 0 2006.257.18:58:16.84#ibcon#first serial, iclass 15, count 0 2006.257.18:58:16.84#ibcon#enter sib2, iclass 15, count 0 2006.257.18:58:16.84#ibcon#flushed, iclass 15, count 0 2006.257.18:58:16.84#ibcon#about to write, iclass 15, count 0 2006.257.18:58:16.84#ibcon#wrote, iclass 15, count 0 2006.257.18:58:16.84#ibcon#about to read 3, iclass 15, count 0 2006.257.18:58:16.86#ibcon#read 3, iclass 15, count 0 2006.257.18:58:16.86#ibcon#about to read 4, iclass 15, count 0 2006.257.18:58:16.86#ibcon#read 4, iclass 15, count 0 2006.257.18:58:16.86#ibcon#about to read 5, iclass 15, count 0 2006.257.18:58:16.86#ibcon#read 5, iclass 15, count 0 2006.257.18:58:16.86#ibcon#about to read 6, iclass 15, count 0 2006.257.18:58:16.86#ibcon#read 6, iclass 15, count 0 2006.257.18:58:16.86#ibcon#end of sib2, iclass 15, count 0 2006.257.18:58:16.86#ibcon#*mode == 0, iclass 15, count 0 2006.257.18:58:16.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.18:58:16.86#ibcon#[27=USB\r\n] 2006.257.18:58:16.86#ibcon#*before write, iclass 15, count 0 2006.257.18:58:16.86#ibcon#enter sib2, iclass 15, count 0 2006.257.18:58:16.86#ibcon#flushed, iclass 15, count 0 2006.257.18:58:16.86#ibcon#about to write, iclass 15, count 0 2006.257.18:58:16.86#ibcon#wrote, iclass 15, count 0 2006.257.18:58:16.86#ibcon#about to read 3, iclass 15, count 0 2006.257.18:58:16.89#ibcon#read 3, iclass 15, count 0 2006.257.18:58:16.89#ibcon#about to read 4, iclass 15, count 0 2006.257.18:58:16.89#ibcon#read 4, iclass 15, count 0 2006.257.18:58:16.89#ibcon#about to read 5, iclass 15, count 0 2006.257.18:58:16.89#ibcon#read 5, iclass 15, count 0 2006.257.18:58:16.89#ibcon#about to read 6, iclass 15, count 0 2006.257.18:58:16.89#ibcon#read 6, iclass 15, count 0 2006.257.18:58:16.89#ibcon#end of sib2, iclass 15, count 0 2006.257.18:58:16.89#ibcon#*after write, iclass 15, count 0 2006.257.18:58:16.89#ibcon#*before return 0, iclass 15, count 0 2006.257.18:58:16.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:16.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.18:58:16.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.18:58:16.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.18:58:16.89$vck44/vblo=6,719.99 2006.257.18:58:16.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.18:58:16.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.18:58:16.89#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:16.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:16.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:16.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:16.89#ibcon#enter wrdev, iclass 17, count 0 2006.257.18:58:16.89#ibcon#first serial, iclass 17, count 0 2006.257.18:58:16.89#ibcon#enter sib2, iclass 17, count 0 2006.257.18:58:16.89#ibcon#flushed, iclass 17, count 0 2006.257.18:58:16.89#ibcon#about to write, iclass 17, count 0 2006.257.18:58:16.89#ibcon#wrote, iclass 17, count 0 2006.257.18:58:16.89#ibcon#about to read 3, iclass 17, count 0 2006.257.18:58:16.91#ibcon#read 3, iclass 17, count 0 2006.257.18:58:16.91#ibcon#about to read 4, iclass 17, count 0 2006.257.18:58:16.91#ibcon#read 4, iclass 17, count 0 2006.257.18:58:16.91#ibcon#about to read 5, iclass 17, count 0 2006.257.18:58:16.91#ibcon#read 5, iclass 17, count 0 2006.257.18:58:16.91#ibcon#about to read 6, iclass 17, count 0 2006.257.18:58:16.91#ibcon#read 6, iclass 17, count 0 2006.257.18:58:16.91#ibcon#end of sib2, iclass 17, count 0 2006.257.18:58:16.91#ibcon#*mode == 0, iclass 17, count 0 2006.257.18:58:16.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.18:58:16.91#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.18:58:16.91#ibcon#*before write, iclass 17, count 0 2006.257.18:58:16.91#ibcon#enter sib2, iclass 17, count 0 2006.257.18:58:16.91#ibcon#flushed, iclass 17, count 0 2006.257.18:58:16.91#ibcon#about to write, iclass 17, count 0 2006.257.18:58:16.91#ibcon#wrote, iclass 17, count 0 2006.257.18:58:16.91#ibcon#about to read 3, iclass 17, count 0 2006.257.18:58:16.95#ibcon#read 3, iclass 17, count 0 2006.257.18:58:16.95#ibcon#about to read 4, iclass 17, count 0 2006.257.18:58:16.95#ibcon#read 4, iclass 17, count 0 2006.257.18:58:16.95#ibcon#about to read 5, iclass 17, count 0 2006.257.18:58:16.95#ibcon#read 5, iclass 17, count 0 2006.257.18:58:16.95#ibcon#about to read 6, iclass 17, count 0 2006.257.18:58:16.95#ibcon#read 6, iclass 17, count 0 2006.257.18:58:16.95#ibcon#end of sib2, iclass 17, count 0 2006.257.18:58:16.95#ibcon#*after write, iclass 17, count 0 2006.257.18:58:16.95#ibcon#*before return 0, iclass 17, count 0 2006.257.18:58:16.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:16.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.18:58:16.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.18:58:16.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.18:58:16.95$vck44/vb=6,4 2006.257.18:58:16.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.18:58:16.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.18:58:16.95#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:16.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:17.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:17.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:17.01#ibcon#enter wrdev, iclass 19, count 2 2006.257.18:58:17.01#ibcon#first serial, iclass 19, count 2 2006.257.18:58:17.01#ibcon#enter sib2, iclass 19, count 2 2006.257.18:58:17.01#ibcon#flushed, iclass 19, count 2 2006.257.18:58:17.01#ibcon#about to write, iclass 19, count 2 2006.257.18:58:17.01#ibcon#wrote, iclass 19, count 2 2006.257.18:58:17.01#ibcon#about to read 3, iclass 19, count 2 2006.257.18:58:17.03#ibcon#read 3, iclass 19, count 2 2006.257.18:58:17.03#ibcon#about to read 4, iclass 19, count 2 2006.257.18:58:17.03#ibcon#read 4, iclass 19, count 2 2006.257.18:58:17.03#ibcon#about to read 5, iclass 19, count 2 2006.257.18:58:17.03#ibcon#read 5, iclass 19, count 2 2006.257.18:58:17.03#ibcon#about to read 6, iclass 19, count 2 2006.257.18:58:17.03#ibcon#read 6, iclass 19, count 2 2006.257.18:58:17.03#ibcon#end of sib2, iclass 19, count 2 2006.257.18:58:17.03#ibcon#*mode == 0, iclass 19, count 2 2006.257.18:58:17.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.18:58:17.03#ibcon#[27=AT06-04\r\n] 2006.257.18:58:17.03#ibcon#*before write, iclass 19, count 2 2006.257.18:58:17.03#ibcon#enter sib2, iclass 19, count 2 2006.257.18:58:17.03#ibcon#flushed, iclass 19, count 2 2006.257.18:58:17.03#ibcon#about to write, iclass 19, count 2 2006.257.18:58:17.03#ibcon#wrote, iclass 19, count 2 2006.257.18:58:17.03#ibcon#about to read 3, iclass 19, count 2 2006.257.18:58:17.06#ibcon#read 3, iclass 19, count 2 2006.257.18:58:17.06#ibcon#about to read 4, iclass 19, count 2 2006.257.18:58:17.06#ibcon#read 4, iclass 19, count 2 2006.257.18:58:17.06#ibcon#about to read 5, iclass 19, count 2 2006.257.18:58:17.06#ibcon#read 5, iclass 19, count 2 2006.257.18:58:17.06#ibcon#about to read 6, iclass 19, count 2 2006.257.18:58:17.06#ibcon#read 6, iclass 19, count 2 2006.257.18:58:17.06#ibcon#end of sib2, iclass 19, count 2 2006.257.18:58:17.06#ibcon#*after write, iclass 19, count 2 2006.257.18:58:17.06#ibcon#*before return 0, iclass 19, count 2 2006.257.18:58:17.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:17.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.18:58:17.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.18:58:17.06#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:17.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:17.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:17.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:17.18#ibcon#enter wrdev, iclass 19, count 0 2006.257.18:58:17.18#ibcon#first serial, iclass 19, count 0 2006.257.18:58:17.18#ibcon#enter sib2, iclass 19, count 0 2006.257.18:58:17.18#ibcon#flushed, iclass 19, count 0 2006.257.18:58:17.18#ibcon#about to write, iclass 19, count 0 2006.257.18:58:17.18#ibcon#wrote, iclass 19, count 0 2006.257.18:58:17.18#ibcon#about to read 3, iclass 19, count 0 2006.257.18:58:17.20#ibcon#read 3, iclass 19, count 0 2006.257.18:58:17.20#ibcon#about to read 4, iclass 19, count 0 2006.257.18:58:17.20#ibcon#read 4, iclass 19, count 0 2006.257.18:58:17.20#ibcon#about to read 5, iclass 19, count 0 2006.257.18:58:17.20#ibcon#read 5, iclass 19, count 0 2006.257.18:58:17.20#ibcon#about to read 6, iclass 19, count 0 2006.257.18:58:17.20#ibcon#read 6, iclass 19, count 0 2006.257.18:58:17.20#ibcon#end of sib2, iclass 19, count 0 2006.257.18:58:17.20#ibcon#*mode == 0, iclass 19, count 0 2006.257.18:58:17.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.18:58:17.20#ibcon#[27=USB\r\n] 2006.257.18:58:17.20#ibcon#*before write, iclass 19, count 0 2006.257.18:58:17.20#ibcon#enter sib2, iclass 19, count 0 2006.257.18:58:17.20#ibcon#flushed, iclass 19, count 0 2006.257.18:58:17.20#ibcon#about to write, iclass 19, count 0 2006.257.18:58:17.20#ibcon#wrote, iclass 19, count 0 2006.257.18:58:17.20#ibcon#about to read 3, iclass 19, count 0 2006.257.18:58:17.23#ibcon#read 3, iclass 19, count 0 2006.257.18:58:17.23#ibcon#about to read 4, iclass 19, count 0 2006.257.18:58:17.23#ibcon#read 4, iclass 19, count 0 2006.257.18:58:17.23#ibcon#about to read 5, iclass 19, count 0 2006.257.18:58:17.23#ibcon#read 5, iclass 19, count 0 2006.257.18:58:17.23#ibcon#about to read 6, iclass 19, count 0 2006.257.18:58:17.23#ibcon#read 6, iclass 19, count 0 2006.257.18:58:17.23#ibcon#end of sib2, iclass 19, count 0 2006.257.18:58:17.23#ibcon#*after write, iclass 19, count 0 2006.257.18:58:17.23#ibcon#*before return 0, iclass 19, count 0 2006.257.18:58:17.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:17.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.18:58:17.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.18:58:17.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.18:58:17.23$vck44/vblo=7,734.99 2006.257.18:58:17.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.18:58:17.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.18:58:17.23#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:17.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:17.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:17.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:17.23#ibcon#enter wrdev, iclass 21, count 0 2006.257.18:58:17.23#ibcon#first serial, iclass 21, count 0 2006.257.18:58:17.23#ibcon#enter sib2, iclass 21, count 0 2006.257.18:58:17.23#ibcon#flushed, iclass 21, count 0 2006.257.18:58:17.23#ibcon#about to write, iclass 21, count 0 2006.257.18:58:17.23#ibcon#wrote, iclass 21, count 0 2006.257.18:58:17.23#ibcon#about to read 3, iclass 21, count 0 2006.257.18:58:17.25#ibcon#read 3, iclass 21, count 0 2006.257.18:58:17.25#ibcon#about to read 4, iclass 21, count 0 2006.257.18:58:17.25#ibcon#read 4, iclass 21, count 0 2006.257.18:58:17.25#ibcon#about to read 5, iclass 21, count 0 2006.257.18:58:17.25#ibcon#read 5, iclass 21, count 0 2006.257.18:58:17.25#ibcon#about to read 6, iclass 21, count 0 2006.257.18:58:17.25#ibcon#read 6, iclass 21, count 0 2006.257.18:58:17.25#ibcon#end of sib2, iclass 21, count 0 2006.257.18:58:17.25#ibcon#*mode == 0, iclass 21, count 0 2006.257.18:58:17.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.18:58:17.25#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.18:58:17.25#ibcon#*before write, iclass 21, count 0 2006.257.18:58:17.25#ibcon#enter sib2, iclass 21, count 0 2006.257.18:58:17.25#ibcon#flushed, iclass 21, count 0 2006.257.18:58:17.25#ibcon#about to write, iclass 21, count 0 2006.257.18:58:17.25#ibcon#wrote, iclass 21, count 0 2006.257.18:58:17.25#ibcon#about to read 3, iclass 21, count 0 2006.257.18:58:17.29#ibcon#read 3, iclass 21, count 0 2006.257.18:58:17.29#ibcon#about to read 4, iclass 21, count 0 2006.257.18:58:17.29#ibcon#read 4, iclass 21, count 0 2006.257.18:58:17.29#ibcon#about to read 5, iclass 21, count 0 2006.257.18:58:17.29#ibcon#read 5, iclass 21, count 0 2006.257.18:58:17.29#ibcon#about to read 6, iclass 21, count 0 2006.257.18:58:17.29#ibcon#read 6, iclass 21, count 0 2006.257.18:58:17.29#ibcon#end of sib2, iclass 21, count 0 2006.257.18:58:17.29#ibcon#*after write, iclass 21, count 0 2006.257.18:58:17.29#ibcon#*before return 0, iclass 21, count 0 2006.257.18:58:17.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:17.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.18:58:17.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.18:58:17.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.18:58:17.29$vck44/vb=7,4 2006.257.18:58:17.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.18:58:17.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.18:58:17.29#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:17.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:17.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:17.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:17.35#ibcon#enter wrdev, iclass 23, count 2 2006.257.18:58:17.35#ibcon#first serial, iclass 23, count 2 2006.257.18:58:17.35#ibcon#enter sib2, iclass 23, count 2 2006.257.18:58:17.35#ibcon#flushed, iclass 23, count 2 2006.257.18:58:17.35#ibcon#about to write, iclass 23, count 2 2006.257.18:58:17.35#ibcon#wrote, iclass 23, count 2 2006.257.18:58:17.35#ibcon#about to read 3, iclass 23, count 2 2006.257.18:58:17.37#ibcon#read 3, iclass 23, count 2 2006.257.18:58:17.37#ibcon#about to read 4, iclass 23, count 2 2006.257.18:58:17.37#ibcon#read 4, iclass 23, count 2 2006.257.18:58:17.37#ibcon#about to read 5, iclass 23, count 2 2006.257.18:58:17.37#ibcon#read 5, iclass 23, count 2 2006.257.18:58:17.37#ibcon#about to read 6, iclass 23, count 2 2006.257.18:58:17.37#ibcon#read 6, iclass 23, count 2 2006.257.18:58:17.37#ibcon#end of sib2, iclass 23, count 2 2006.257.18:58:17.37#ibcon#*mode == 0, iclass 23, count 2 2006.257.18:58:17.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.18:58:17.37#ibcon#[27=AT07-04\r\n] 2006.257.18:58:17.37#ibcon#*before write, iclass 23, count 2 2006.257.18:58:17.37#ibcon#enter sib2, iclass 23, count 2 2006.257.18:58:17.37#ibcon#flushed, iclass 23, count 2 2006.257.18:58:17.37#ibcon#about to write, iclass 23, count 2 2006.257.18:58:17.37#ibcon#wrote, iclass 23, count 2 2006.257.18:58:17.37#ibcon#about to read 3, iclass 23, count 2 2006.257.18:58:17.40#ibcon#read 3, iclass 23, count 2 2006.257.18:58:17.40#ibcon#about to read 4, iclass 23, count 2 2006.257.18:58:17.40#ibcon#read 4, iclass 23, count 2 2006.257.18:58:17.40#ibcon#about to read 5, iclass 23, count 2 2006.257.18:58:17.40#ibcon#read 5, iclass 23, count 2 2006.257.18:58:17.40#ibcon#about to read 6, iclass 23, count 2 2006.257.18:58:17.40#ibcon#read 6, iclass 23, count 2 2006.257.18:58:17.40#ibcon#end of sib2, iclass 23, count 2 2006.257.18:58:17.40#ibcon#*after write, iclass 23, count 2 2006.257.18:58:17.40#ibcon#*before return 0, iclass 23, count 2 2006.257.18:58:17.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:17.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.18:58:17.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.18:58:17.40#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:17.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:17.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:17.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:17.52#ibcon#enter wrdev, iclass 23, count 0 2006.257.18:58:17.52#ibcon#first serial, iclass 23, count 0 2006.257.18:58:17.52#ibcon#enter sib2, iclass 23, count 0 2006.257.18:58:17.52#ibcon#flushed, iclass 23, count 0 2006.257.18:58:17.52#ibcon#about to write, iclass 23, count 0 2006.257.18:58:17.52#ibcon#wrote, iclass 23, count 0 2006.257.18:58:17.52#ibcon#about to read 3, iclass 23, count 0 2006.257.18:58:17.54#ibcon#read 3, iclass 23, count 0 2006.257.18:58:17.54#ibcon#about to read 4, iclass 23, count 0 2006.257.18:58:17.54#ibcon#read 4, iclass 23, count 0 2006.257.18:58:17.54#ibcon#about to read 5, iclass 23, count 0 2006.257.18:58:17.54#ibcon#read 5, iclass 23, count 0 2006.257.18:58:17.54#ibcon#about to read 6, iclass 23, count 0 2006.257.18:58:17.54#ibcon#read 6, iclass 23, count 0 2006.257.18:58:17.54#ibcon#end of sib2, iclass 23, count 0 2006.257.18:58:17.54#ibcon#*mode == 0, iclass 23, count 0 2006.257.18:58:17.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.18:58:17.54#ibcon#[27=USB\r\n] 2006.257.18:58:17.54#ibcon#*before write, iclass 23, count 0 2006.257.18:58:17.54#ibcon#enter sib2, iclass 23, count 0 2006.257.18:58:17.54#ibcon#flushed, iclass 23, count 0 2006.257.18:58:17.54#ibcon#about to write, iclass 23, count 0 2006.257.18:58:17.54#ibcon#wrote, iclass 23, count 0 2006.257.18:58:17.54#ibcon#about to read 3, iclass 23, count 0 2006.257.18:58:17.57#ibcon#read 3, iclass 23, count 0 2006.257.18:58:17.57#ibcon#about to read 4, iclass 23, count 0 2006.257.18:58:17.57#ibcon#read 4, iclass 23, count 0 2006.257.18:58:17.57#ibcon#about to read 5, iclass 23, count 0 2006.257.18:58:17.57#ibcon#read 5, iclass 23, count 0 2006.257.18:58:17.57#ibcon#about to read 6, iclass 23, count 0 2006.257.18:58:17.57#ibcon#read 6, iclass 23, count 0 2006.257.18:58:17.57#ibcon#end of sib2, iclass 23, count 0 2006.257.18:58:17.57#ibcon#*after write, iclass 23, count 0 2006.257.18:58:17.57#ibcon#*before return 0, iclass 23, count 0 2006.257.18:58:17.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:17.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.18:58:17.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.18:58:17.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.18:58:17.57$vck44/vblo=8,744.99 2006.257.18:58:17.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.18:58:17.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.18:58:17.57#ibcon#ireg 17 cls_cnt 0 2006.257.18:58:17.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:17.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:17.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:17.57#ibcon#enter wrdev, iclass 25, count 0 2006.257.18:58:17.57#ibcon#first serial, iclass 25, count 0 2006.257.18:58:17.57#ibcon#enter sib2, iclass 25, count 0 2006.257.18:58:17.57#ibcon#flushed, iclass 25, count 0 2006.257.18:58:17.57#ibcon#about to write, iclass 25, count 0 2006.257.18:58:17.57#ibcon#wrote, iclass 25, count 0 2006.257.18:58:17.57#ibcon#about to read 3, iclass 25, count 0 2006.257.18:58:17.59#ibcon#read 3, iclass 25, count 0 2006.257.18:58:17.59#ibcon#about to read 4, iclass 25, count 0 2006.257.18:58:17.59#ibcon#read 4, iclass 25, count 0 2006.257.18:58:17.59#ibcon#about to read 5, iclass 25, count 0 2006.257.18:58:17.59#ibcon#read 5, iclass 25, count 0 2006.257.18:58:17.59#ibcon#about to read 6, iclass 25, count 0 2006.257.18:58:17.59#ibcon#read 6, iclass 25, count 0 2006.257.18:58:17.59#ibcon#end of sib2, iclass 25, count 0 2006.257.18:58:17.59#ibcon#*mode == 0, iclass 25, count 0 2006.257.18:58:17.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.18:58:17.59#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.18:58:17.59#ibcon#*before write, iclass 25, count 0 2006.257.18:58:17.59#ibcon#enter sib2, iclass 25, count 0 2006.257.18:58:17.59#ibcon#flushed, iclass 25, count 0 2006.257.18:58:17.59#ibcon#about to write, iclass 25, count 0 2006.257.18:58:17.59#ibcon#wrote, iclass 25, count 0 2006.257.18:58:17.59#ibcon#about to read 3, iclass 25, count 0 2006.257.18:58:17.63#ibcon#read 3, iclass 25, count 0 2006.257.18:58:17.63#ibcon#about to read 4, iclass 25, count 0 2006.257.18:58:17.63#ibcon#read 4, iclass 25, count 0 2006.257.18:58:17.63#ibcon#about to read 5, iclass 25, count 0 2006.257.18:58:17.63#ibcon#read 5, iclass 25, count 0 2006.257.18:58:17.63#ibcon#about to read 6, iclass 25, count 0 2006.257.18:58:17.63#ibcon#read 6, iclass 25, count 0 2006.257.18:58:17.63#ibcon#end of sib2, iclass 25, count 0 2006.257.18:58:17.63#ibcon#*after write, iclass 25, count 0 2006.257.18:58:17.63#ibcon#*before return 0, iclass 25, count 0 2006.257.18:58:17.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:17.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.18:58:17.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.18:58:17.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.18:58:17.63$vck44/vb=8,4 2006.257.18:58:17.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.18:58:17.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.18:58:17.63#ibcon#ireg 11 cls_cnt 2 2006.257.18:58:17.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:17.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:17.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:17.69#ibcon#enter wrdev, iclass 27, count 2 2006.257.18:58:17.69#ibcon#first serial, iclass 27, count 2 2006.257.18:58:17.69#ibcon#enter sib2, iclass 27, count 2 2006.257.18:58:17.69#ibcon#flushed, iclass 27, count 2 2006.257.18:58:17.69#ibcon#about to write, iclass 27, count 2 2006.257.18:58:17.69#ibcon#wrote, iclass 27, count 2 2006.257.18:58:17.69#ibcon#about to read 3, iclass 27, count 2 2006.257.18:58:17.71#ibcon#read 3, iclass 27, count 2 2006.257.18:58:17.71#ibcon#about to read 4, iclass 27, count 2 2006.257.18:58:17.71#ibcon#read 4, iclass 27, count 2 2006.257.18:58:17.71#ibcon#about to read 5, iclass 27, count 2 2006.257.18:58:17.71#ibcon#read 5, iclass 27, count 2 2006.257.18:58:17.71#ibcon#about to read 6, iclass 27, count 2 2006.257.18:58:17.71#ibcon#read 6, iclass 27, count 2 2006.257.18:58:17.71#ibcon#end of sib2, iclass 27, count 2 2006.257.18:58:17.71#ibcon#*mode == 0, iclass 27, count 2 2006.257.18:58:17.71#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.18:58:17.71#ibcon#[27=AT08-04\r\n] 2006.257.18:58:17.71#ibcon#*before write, iclass 27, count 2 2006.257.18:58:17.71#ibcon#enter sib2, iclass 27, count 2 2006.257.18:58:17.71#ibcon#flushed, iclass 27, count 2 2006.257.18:58:17.71#ibcon#about to write, iclass 27, count 2 2006.257.18:58:17.71#ibcon#wrote, iclass 27, count 2 2006.257.18:58:17.71#ibcon#about to read 3, iclass 27, count 2 2006.257.18:58:17.74#ibcon#read 3, iclass 27, count 2 2006.257.18:58:17.74#ibcon#about to read 4, iclass 27, count 2 2006.257.18:58:17.74#ibcon#read 4, iclass 27, count 2 2006.257.18:58:17.74#ibcon#about to read 5, iclass 27, count 2 2006.257.18:58:17.74#ibcon#read 5, iclass 27, count 2 2006.257.18:58:17.74#ibcon#about to read 6, iclass 27, count 2 2006.257.18:58:17.74#ibcon#read 6, iclass 27, count 2 2006.257.18:58:17.74#ibcon#end of sib2, iclass 27, count 2 2006.257.18:58:17.74#ibcon#*after write, iclass 27, count 2 2006.257.18:58:17.74#ibcon#*before return 0, iclass 27, count 2 2006.257.18:58:17.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:17.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.18:58:17.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.18:58:17.74#ibcon#ireg 7 cls_cnt 0 2006.257.18:58:17.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:17.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:17.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:17.86#ibcon#enter wrdev, iclass 27, count 0 2006.257.18:58:17.86#ibcon#first serial, iclass 27, count 0 2006.257.18:58:17.86#ibcon#enter sib2, iclass 27, count 0 2006.257.18:58:17.86#ibcon#flushed, iclass 27, count 0 2006.257.18:58:17.86#ibcon#about to write, iclass 27, count 0 2006.257.18:58:17.86#ibcon#wrote, iclass 27, count 0 2006.257.18:58:17.86#ibcon#about to read 3, iclass 27, count 0 2006.257.18:58:17.88#ibcon#read 3, iclass 27, count 0 2006.257.18:58:17.88#ibcon#about to read 4, iclass 27, count 0 2006.257.18:58:17.88#ibcon#read 4, iclass 27, count 0 2006.257.18:58:17.88#ibcon#about to read 5, iclass 27, count 0 2006.257.18:58:17.88#ibcon#read 5, iclass 27, count 0 2006.257.18:58:17.88#ibcon#about to read 6, iclass 27, count 0 2006.257.18:58:17.88#ibcon#read 6, iclass 27, count 0 2006.257.18:58:17.88#ibcon#end of sib2, iclass 27, count 0 2006.257.18:58:17.88#ibcon#*mode == 0, iclass 27, count 0 2006.257.18:58:17.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.18:58:17.88#ibcon#[27=USB\r\n] 2006.257.18:58:17.88#ibcon#*before write, iclass 27, count 0 2006.257.18:58:17.88#ibcon#enter sib2, iclass 27, count 0 2006.257.18:58:17.88#ibcon#flushed, iclass 27, count 0 2006.257.18:58:17.88#ibcon#about to write, iclass 27, count 0 2006.257.18:58:17.88#ibcon#wrote, iclass 27, count 0 2006.257.18:58:17.88#ibcon#about to read 3, iclass 27, count 0 2006.257.18:58:17.91#ibcon#read 3, iclass 27, count 0 2006.257.18:58:17.91#ibcon#about to read 4, iclass 27, count 0 2006.257.18:58:17.91#ibcon#read 4, iclass 27, count 0 2006.257.18:58:17.91#ibcon#about to read 5, iclass 27, count 0 2006.257.18:58:17.91#ibcon#read 5, iclass 27, count 0 2006.257.18:58:17.91#ibcon#about to read 6, iclass 27, count 0 2006.257.18:58:17.91#ibcon#read 6, iclass 27, count 0 2006.257.18:58:17.91#ibcon#end of sib2, iclass 27, count 0 2006.257.18:58:17.91#ibcon#*after write, iclass 27, count 0 2006.257.18:58:17.91#ibcon#*before return 0, iclass 27, count 0 2006.257.18:58:17.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:17.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.18:58:17.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.18:58:17.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.18:58:17.91$vck44/vabw=wide 2006.257.18:58:17.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.18:58:17.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.18:58:17.91#ibcon#ireg 8 cls_cnt 0 2006.257.18:58:17.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:17.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:17.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:17.91#ibcon#enter wrdev, iclass 29, count 0 2006.257.18:58:17.91#ibcon#first serial, iclass 29, count 0 2006.257.18:58:17.91#ibcon#enter sib2, iclass 29, count 0 2006.257.18:58:17.91#ibcon#flushed, iclass 29, count 0 2006.257.18:58:17.91#ibcon#about to write, iclass 29, count 0 2006.257.18:58:17.91#ibcon#wrote, iclass 29, count 0 2006.257.18:58:17.91#ibcon#about to read 3, iclass 29, count 0 2006.257.18:58:17.93#ibcon#read 3, iclass 29, count 0 2006.257.18:58:17.93#ibcon#about to read 4, iclass 29, count 0 2006.257.18:58:17.93#ibcon#read 4, iclass 29, count 0 2006.257.18:58:17.93#ibcon#about to read 5, iclass 29, count 0 2006.257.18:58:17.93#ibcon#read 5, iclass 29, count 0 2006.257.18:58:17.93#ibcon#about to read 6, iclass 29, count 0 2006.257.18:58:17.93#ibcon#read 6, iclass 29, count 0 2006.257.18:58:17.93#ibcon#end of sib2, iclass 29, count 0 2006.257.18:58:17.93#ibcon#*mode == 0, iclass 29, count 0 2006.257.18:58:17.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.18:58:17.93#ibcon#[25=BW32\r\n] 2006.257.18:58:17.93#ibcon#*before write, iclass 29, count 0 2006.257.18:58:17.93#ibcon#enter sib2, iclass 29, count 0 2006.257.18:58:17.93#ibcon#flushed, iclass 29, count 0 2006.257.18:58:17.93#ibcon#about to write, iclass 29, count 0 2006.257.18:58:17.93#ibcon#wrote, iclass 29, count 0 2006.257.18:58:17.93#ibcon#about to read 3, iclass 29, count 0 2006.257.18:58:17.96#ibcon#read 3, iclass 29, count 0 2006.257.18:58:17.96#ibcon#about to read 4, iclass 29, count 0 2006.257.18:58:17.96#ibcon#read 4, iclass 29, count 0 2006.257.18:58:17.96#ibcon#about to read 5, iclass 29, count 0 2006.257.18:58:17.96#ibcon#read 5, iclass 29, count 0 2006.257.18:58:17.96#ibcon#about to read 6, iclass 29, count 0 2006.257.18:58:17.96#ibcon#read 6, iclass 29, count 0 2006.257.18:58:17.96#ibcon#end of sib2, iclass 29, count 0 2006.257.18:58:17.96#ibcon#*after write, iclass 29, count 0 2006.257.18:58:17.96#ibcon#*before return 0, iclass 29, count 0 2006.257.18:58:17.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:17.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.18:58:17.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.18:58:17.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.18:58:17.96$vck44/vbbw=wide 2006.257.18:58:17.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.18:58:17.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.18:58:17.96#ibcon#ireg 8 cls_cnt 0 2006.257.18:58:17.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:58:18.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:58:18.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:58:18.03#ibcon#enter wrdev, iclass 31, count 0 2006.257.18:58:18.03#ibcon#first serial, iclass 31, count 0 2006.257.18:58:18.03#ibcon#enter sib2, iclass 31, count 0 2006.257.18:58:18.03#ibcon#flushed, iclass 31, count 0 2006.257.18:58:18.03#ibcon#about to write, iclass 31, count 0 2006.257.18:58:18.03#ibcon#wrote, iclass 31, count 0 2006.257.18:58:18.03#ibcon#about to read 3, iclass 31, count 0 2006.257.18:58:18.05#ibcon#read 3, iclass 31, count 0 2006.257.18:58:18.05#ibcon#about to read 4, iclass 31, count 0 2006.257.18:58:18.05#ibcon#read 4, iclass 31, count 0 2006.257.18:58:18.05#ibcon#about to read 5, iclass 31, count 0 2006.257.18:58:18.05#ibcon#read 5, iclass 31, count 0 2006.257.18:58:18.05#ibcon#about to read 6, iclass 31, count 0 2006.257.18:58:18.05#ibcon#read 6, iclass 31, count 0 2006.257.18:58:18.05#ibcon#end of sib2, iclass 31, count 0 2006.257.18:58:18.05#ibcon#*mode == 0, iclass 31, count 0 2006.257.18:58:18.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.18:58:18.05#ibcon#[27=BW32\r\n] 2006.257.18:58:18.05#ibcon#*before write, iclass 31, count 0 2006.257.18:58:18.05#ibcon#enter sib2, iclass 31, count 0 2006.257.18:58:18.05#ibcon#flushed, iclass 31, count 0 2006.257.18:58:18.05#ibcon#about to write, iclass 31, count 0 2006.257.18:58:18.05#ibcon#wrote, iclass 31, count 0 2006.257.18:58:18.05#ibcon#about to read 3, iclass 31, count 0 2006.257.18:58:18.08#ibcon#read 3, iclass 31, count 0 2006.257.18:58:18.08#ibcon#about to read 4, iclass 31, count 0 2006.257.18:58:18.08#ibcon#read 4, iclass 31, count 0 2006.257.18:58:18.08#ibcon#about to read 5, iclass 31, count 0 2006.257.18:58:18.08#ibcon#read 5, iclass 31, count 0 2006.257.18:58:18.08#ibcon#about to read 6, iclass 31, count 0 2006.257.18:58:18.08#ibcon#read 6, iclass 31, count 0 2006.257.18:58:18.08#ibcon#end of sib2, iclass 31, count 0 2006.257.18:58:18.08#ibcon#*after write, iclass 31, count 0 2006.257.18:58:18.08#ibcon#*before return 0, iclass 31, count 0 2006.257.18:58:18.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:58:18.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.18:58:18.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.18:58:18.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.18:58:18.08$setupk4/ifdk4 2006.257.18:58:18.08$ifdk4/lo= 2006.257.18:58:18.08$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.18:58:18.08$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.18:58:18.08$ifdk4/patch= 2006.257.18:58:18.08$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.18:58:18.08$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.18:58:18.08$setupk4/!*+20s 2006.257.18:58:19.81#abcon#<5=/14 1.5 3.7 17.37 961014.3\r\n> 2006.257.18:58:19.83#abcon#{5=INTERFACE CLEAR} 2006.257.18:58:19.89#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:58:29.98#abcon#<5=/14 1.5 3.7 17.37 961014.3\r\n> 2006.257.18:58:30.00#abcon#{5=INTERFACE CLEAR} 2006.257.18:58:30.06#abcon#[5=S1D000X0/0*\r\n] 2006.257.18:58:32.59$setupk4/"tpicd 2006.257.18:58:32.59$setupk4/echo=off 2006.257.18:58:32.59$setupk4/xlog=off 2006.257.18:58:32.59:!2006.257.18:59:49 2006.257.18:58:36.14#trakl#Source acquired 2006.257.18:58:38.14#flagr#flagr/antenna,acquired 2006.257.18:59:49.00:preob 2006.257.18:59:49.14/onsource/TRACKING 2006.257.18:59:49.14:!2006.257.18:59:59 2006.257.18:59:59.00:"tape 2006.257.18:59:59.00:"st=record 2006.257.18:59:59.00:data_valid=on 2006.257.18:59:59.00:midob 2006.257.18:59:59.14/onsource/TRACKING 2006.257.18:59:59.14/wx/17.38,1014.3,96 2006.257.18:59:59.31/cable/+6.4856E-03 2006.257.19:00:00.40/va/01,08,usb,yes,40,43 2006.257.19:00:00.40/va/02,07,usb,yes,43,44 2006.257.19:00:00.40/va/03,08,usb,yes,39,41 2006.257.19:00:00.40/va/04,07,usb,yes,44,46 2006.257.19:00:00.40/va/05,04,usb,yes,40,40 2006.257.19:00:00.40/va/06,04,usb,yes,44,44 2006.257.19:00:00.40/va/07,04,usb,yes,45,45 2006.257.19:00:00.40/va/08,04,usb,yes,38,46 2006.257.19:00:00.63/valo/01,524.99,yes,locked 2006.257.19:00:00.63/valo/02,534.99,yes,locked 2006.257.19:00:00.63/valo/03,564.99,yes,locked 2006.257.19:00:00.63/valo/04,624.99,yes,locked 2006.257.19:00:00.63/valo/05,734.99,yes,locked 2006.257.19:00:00.63/valo/06,814.99,yes,locked 2006.257.19:00:00.63/valo/07,864.99,yes,locked 2006.257.19:00:00.63/valo/08,884.99,yes,locked 2006.257.19:00:01.72/vb/01,04,usb,yes,35,33 2006.257.19:00:01.72/vb/02,05,usb,yes,33,33 2006.257.19:00:01.72/vb/03,04,usb,yes,34,38 2006.257.19:00:01.72/vb/04,05,usb,yes,35,34 2006.257.19:00:01.72/vb/05,04,usb,yes,31,34 2006.257.19:00:01.72/vb/06,04,usb,yes,36,32 2006.257.19:00:01.72/vb/07,04,usb,yes,36,36 2006.257.19:00:01.72/vb/08,04,usb,yes,33,37 2006.257.19:00:01.95/vblo/01,629.99,yes,locked 2006.257.19:00:01.95/vblo/02,634.99,yes,locked 2006.257.19:00:01.95/vblo/03,649.99,yes,locked 2006.257.19:00:01.95/vblo/04,679.99,yes,locked 2006.257.19:00:01.95/vblo/05,709.99,yes,locked 2006.257.19:00:01.95/vblo/06,719.99,yes,locked 2006.257.19:00:01.95/vblo/07,734.99,yes,locked 2006.257.19:00:01.95/vblo/08,744.99,yes,locked 2006.257.19:00:02.10/vabw/8 2006.257.19:00:02.25/vbbw/8 2006.257.19:00:02.34/xfe/off,on,15.0 2006.257.19:00:02.73/ifatt/23,28,28,28 2006.257.19:00:03.07/fmout-gps/S +4.52E-07 2006.257.19:00:03.11:!2006.257.19:00:49 2006.257.19:00:49.01:data_valid=off 2006.257.19:00:49.01:"et 2006.257.19:00:49.01:!+3s 2006.257.19:00:52.02:"tape 2006.257.19:00:52.02:postob 2006.257.19:00:52.16/cable/+6.4846E-03 2006.257.19:00:52.16/wx/17.38,1014.3,96 2006.257.19:00:53.07/fmout-gps/S +4.51E-07 2006.257.19:00:53.07:scan_name=257-1910,jd0609,460 2006.257.19:00:53.07:source=0804+499,080839.67,495036.5,2000.0,cw 2006.257.19:00:54.13#flagr#flagr/antenna,new-source 2006.257.19:00:54.13:checkk5 2006.257.19:00:54.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.19:00:54.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.19:00:55.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.19:00:55.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.19:00:55.83/chk_obsdata//k5ts1/T2571859??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.19:00:56.17/chk_obsdata//k5ts2/T2571859??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.19:00:56.50/chk_obsdata//k5ts3/T2571859??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.19:00:56.83/chk_obsdata//k5ts4/T2571859??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.19:00:57.49/k5log//k5ts1_log_newline 2006.257.19:00:58.16/k5log//k5ts2_log_newline 2006.257.19:00:58.81/k5log//k5ts3_log_newline 2006.257.19:00:59.46/k5log//k5ts4_log_newline 2006.257.19:00:59.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.19:00:59.48:setupk4=1 2006.257.19:00:59.48$setupk4/echo=on 2006.257.19:00:59.48$setupk4/pcalon 2006.257.19:00:59.48$pcalon/"no phase cal control is implemented here 2006.257.19:00:59.48$setupk4/"tpicd=stop 2006.257.19:00:59.48$setupk4/"rec=synch_on 2006.257.19:00:59.48$setupk4/"rec_mode=128 2006.257.19:00:59.48$setupk4/!* 2006.257.19:00:59.48$setupk4/recpk4 2006.257.19:00:59.48$recpk4/recpatch= 2006.257.19:00:59.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.19:00:59.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.19:00:59.49$setupk4/vck44 2006.257.19:00:59.49$vck44/valo=1,524.99 2006.257.19:00:59.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.19:00:59.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.19:00:59.49#ibcon#ireg 17 cls_cnt 0 2006.257.19:00:59.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:00:59.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:00:59.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:00:59.49#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:00:59.49#ibcon#first serial, iclass 28, count 0 2006.257.19:00:59.49#ibcon#enter sib2, iclass 28, count 0 2006.257.19:00:59.49#ibcon#flushed, iclass 28, count 0 2006.257.19:00:59.49#ibcon#about to write, iclass 28, count 0 2006.257.19:00:59.49#ibcon#wrote, iclass 28, count 0 2006.257.19:00:59.49#ibcon#about to read 3, iclass 28, count 0 2006.257.19:00:59.51#ibcon#read 3, iclass 28, count 0 2006.257.19:00:59.51#ibcon#about to read 4, iclass 28, count 0 2006.257.19:00:59.51#ibcon#read 4, iclass 28, count 0 2006.257.19:00:59.51#ibcon#about to read 5, iclass 28, count 0 2006.257.19:00:59.51#ibcon#read 5, iclass 28, count 0 2006.257.19:00:59.51#ibcon#about to read 6, iclass 28, count 0 2006.257.19:00:59.51#ibcon#read 6, iclass 28, count 0 2006.257.19:00:59.51#ibcon#end of sib2, iclass 28, count 0 2006.257.19:00:59.51#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:00:59.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:00:59.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.19:00:59.51#ibcon#*before write, iclass 28, count 0 2006.257.19:00:59.51#ibcon#enter sib2, iclass 28, count 0 2006.257.19:00:59.51#ibcon#flushed, iclass 28, count 0 2006.257.19:00:59.51#ibcon#about to write, iclass 28, count 0 2006.257.19:00:59.51#ibcon#wrote, iclass 28, count 0 2006.257.19:00:59.51#ibcon#about to read 3, iclass 28, count 0 2006.257.19:00:59.56#ibcon#read 3, iclass 28, count 0 2006.257.19:00:59.56#ibcon#about to read 4, iclass 28, count 0 2006.257.19:00:59.56#ibcon#read 4, iclass 28, count 0 2006.257.19:00:59.56#ibcon#about to read 5, iclass 28, count 0 2006.257.19:00:59.56#ibcon#read 5, iclass 28, count 0 2006.257.19:00:59.56#ibcon#about to read 6, iclass 28, count 0 2006.257.19:00:59.56#ibcon#read 6, iclass 28, count 0 2006.257.19:00:59.56#ibcon#end of sib2, iclass 28, count 0 2006.257.19:00:59.56#ibcon#*after write, iclass 28, count 0 2006.257.19:00:59.56#ibcon#*before return 0, iclass 28, count 0 2006.257.19:00:59.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:00:59.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:00:59.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:00:59.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:00:59.56$vck44/va=1,8 2006.257.19:00:59.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.19:00:59.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.19:00:59.56#ibcon#ireg 11 cls_cnt 2 2006.257.19:00:59.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:00:59.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:00:59.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:00:59.56#ibcon#enter wrdev, iclass 30, count 2 2006.257.19:00:59.56#ibcon#first serial, iclass 30, count 2 2006.257.19:00:59.56#ibcon#enter sib2, iclass 30, count 2 2006.257.19:00:59.56#ibcon#flushed, iclass 30, count 2 2006.257.19:00:59.56#ibcon#about to write, iclass 30, count 2 2006.257.19:00:59.56#ibcon#wrote, iclass 30, count 2 2006.257.19:00:59.56#ibcon#about to read 3, iclass 30, count 2 2006.257.19:00:59.58#ibcon#read 3, iclass 30, count 2 2006.257.19:00:59.58#ibcon#about to read 4, iclass 30, count 2 2006.257.19:00:59.58#ibcon#read 4, iclass 30, count 2 2006.257.19:00:59.58#ibcon#about to read 5, iclass 30, count 2 2006.257.19:00:59.58#ibcon#read 5, iclass 30, count 2 2006.257.19:00:59.58#ibcon#about to read 6, iclass 30, count 2 2006.257.19:00:59.58#ibcon#read 6, iclass 30, count 2 2006.257.19:00:59.58#ibcon#end of sib2, iclass 30, count 2 2006.257.19:00:59.58#ibcon#*mode == 0, iclass 30, count 2 2006.257.19:00:59.58#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.19:00:59.58#ibcon#[25=AT01-08\r\n] 2006.257.19:00:59.58#ibcon#*before write, iclass 30, count 2 2006.257.19:00:59.58#ibcon#enter sib2, iclass 30, count 2 2006.257.19:00:59.58#ibcon#flushed, iclass 30, count 2 2006.257.19:00:59.58#ibcon#about to write, iclass 30, count 2 2006.257.19:00:59.58#ibcon#wrote, iclass 30, count 2 2006.257.19:00:59.58#ibcon#about to read 3, iclass 30, count 2 2006.257.19:00:59.61#ibcon#read 3, iclass 30, count 2 2006.257.19:00:59.61#ibcon#about to read 4, iclass 30, count 2 2006.257.19:00:59.61#ibcon#read 4, iclass 30, count 2 2006.257.19:00:59.61#ibcon#about to read 5, iclass 30, count 2 2006.257.19:00:59.61#ibcon#read 5, iclass 30, count 2 2006.257.19:00:59.61#ibcon#about to read 6, iclass 30, count 2 2006.257.19:00:59.61#ibcon#read 6, iclass 30, count 2 2006.257.19:00:59.61#ibcon#end of sib2, iclass 30, count 2 2006.257.19:00:59.61#ibcon#*after write, iclass 30, count 2 2006.257.19:00:59.61#ibcon#*before return 0, iclass 30, count 2 2006.257.19:00:59.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:00:59.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:00:59.61#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.19:00:59.61#ibcon#ireg 7 cls_cnt 0 2006.257.19:00:59.61#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:00:59.73#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:00:59.73#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:00:59.73#ibcon#enter wrdev, iclass 30, count 0 2006.257.19:00:59.73#ibcon#first serial, iclass 30, count 0 2006.257.19:00:59.73#ibcon#enter sib2, iclass 30, count 0 2006.257.19:00:59.73#ibcon#flushed, iclass 30, count 0 2006.257.19:00:59.73#ibcon#about to write, iclass 30, count 0 2006.257.19:00:59.73#ibcon#wrote, iclass 30, count 0 2006.257.19:00:59.73#ibcon#about to read 3, iclass 30, count 0 2006.257.19:00:59.75#ibcon#read 3, iclass 30, count 0 2006.257.19:00:59.75#ibcon#about to read 4, iclass 30, count 0 2006.257.19:00:59.75#ibcon#read 4, iclass 30, count 0 2006.257.19:00:59.75#ibcon#about to read 5, iclass 30, count 0 2006.257.19:00:59.75#ibcon#read 5, iclass 30, count 0 2006.257.19:00:59.75#ibcon#about to read 6, iclass 30, count 0 2006.257.19:00:59.75#ibcon#read 6, iclass 30, count 0 2006.257.19:00:59.75#ibcon#end of sib2, iclass 30, count 0 2006.257.19:00:59.75#ibcon#*mode == 0, iclass 30, count 0 2006.257.19:00:59.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.19:00:59.75#ibcon#[25=USB\r\n] 2006.257.19:00:59.75#ibcon#*before write, iclass 30, count 0 2006.257.19:00:59.75#ibcon#enter sib2, iclass 30, count 0 2006.257.19:00:59.75#ibcon#flushed, iclass 30, count 0 2006.257.19:00:59.75#ibcon#about to write, iclass 30, count 0 2006.257.19:00:59.75#ibcon#wrote, iclass 30, count 0 2006.257.19:00:59.75#ibcon#about to read 3, iclass 30, count 0 2006.257.19:00:59.78#ibcon#read 3, iclass 30, count 0 2006.257.19:00:59.78#ibcon#about to read 4, iclass 30, count 0 2006.257.19:00:59.78#ibcon#read 4, iclass 30, count 0 2006.257.19:00:59.78#ibcon#about to read 5, iclass 30, count 0 2006.257.19:00:59.78#ibcon#read 5, iclass 30, count 0 2006.257.19:00:59.78#ibcon#about to read 6, iclass 30, count 0 2006.257.19:00:59.78#ibcon#read 6, iclass 30, count 0 2006.257.19:00:59.78#ibcon#end of sib2, iclass 30, count 0 2006.257.19:00:59.78#ibcon#*after write, iclass 30, count 0 2006.257.19:00:59.78#ibcon#*before return 0, iclass 30, count 0 2006.257.19:00:59.78#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:00:59.78#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:00:59.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.19:00:59.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.19:00:59.78$vck44/valo=2,534.99 2006.257.19:00:59.78#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.19:00:59.78#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.19:00:59.78#ibcon#ireg 17 cls_cnt 0 2006.257.19:00:59.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:00:59.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:00:59.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:00:59.78#ibcon#enter wrdev, iclass 32, count 0 2006.257.19:00:59.78#ibcon#first serial, iclass 32, count 0 2006.257.19:00:59.78#ibcon#enter sib2, iclass 32, count 0 2006.257.19:00:59.78#ibcon#flushed, iclass 32, count 0 2006.257.19:00:59.78#ibcon#about to write, iclass 32, count 0 2006.257.19:00:59.78#ibcon#wrote, iclass 32, count 0 2006.257.19:00:59.78#ibcon#about to read 3, iclass 32, count 0 2006.257.19:00:59.80#ibcon#read 3, iclass 32, count 0 2006.257.19:00:59.80#ibcon#about to read 4, iclass 32, count 0 2006.257.19:00:59.80#ibcon#read 4, iclass 32, count 0 2006.257.19:00:59.80#ibcon#about to read 5, iclass 32, count 0 2006.257.19:00:59.80#ibcon#read 5, iclass 32, count 0 2006.257.19:00:59.80#ibcon#about to read 6, iclass 32, count 0 2006.257.19:00:59.80#ibcon#read 6, iclass 32, count 0 2006.257.19:00:59.80#ibcon#end of sib2, iclass 32, count 0 2006.257.19:00:59.80#ibcon#*mode == 0, iclass 32, count 0 2006.257.19:00:59.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.19:00:59.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.19:00:59.80#ibcon#*before write, iclass 32, count 0 2006.257.19:00:59.80#ibcon#enter sib2, iclass 32, count 0 2006.257.19:00:59.80#ibcon#flushed, iclass 32, count 0 2006.257.19:00:59.80#ibcon#about to write, iclass 32, count 0 2006.257.19:00:59.80#ibcon#wrote, iclass 32, count 0 2006.257.19:00:59.80#ibcon#about to read 3, iclass 32, count 0 2006.257.19:00:59.84#ibcon#read 3, iclass 32, count 0 2006.257.19:00:59.84#ibcon#about to read 4, iclass 32, count 0 2006.257.19:00:59.84#ibcon#read 4, iclass 32, count 0 2006.257.19:00:59.84#ibcon#about to read 5, iclass 32, count 0 2006.257.19:00:59.84#ibcon#read 5, iclass 32, count 0 2006.257.19:00:59.84#ibcon#about to read 6, iclass 32, count 0 2006.257.19:00:59.84#ibcon#read 6, iclass 32, count 0 2006.257.19:00:59.84#ibcon#end of sib2, iclass 32, count 0 2006.257.19:00:59.84#ibcon#*after write, iclass 32, count 0 2006.257.19:00:59.84#ibcon#*before return 0, iclass 32, count 0 2006.257.19:00:59.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:00:59.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:00:59.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.19:00:59.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.19:00:59.84$vck44/va=2,7 2006.257.19:00:59.84#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.19:00:59.84#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.19:00:59.84#ibcon#ireg 11 cls_cnt 2 2006.257.19:00:59.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:00:59.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:00:59.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:00:59.90#ibcon#enter wrdev, iclass 34, count 2 2006.257.19:00:59.90#ibcon#first serial, iclass 34, count 2 2006.257.19:00:59.90#ibcon#enter sib2, iclass 34, count 2 2006.257.19:00:59.90#ibcon#flushed, iclass 34, count 2 2006.257.19:00:59.90#ibcon#about to write, iclass 34, count 2 2006.257.19:00:59.90#ibcon#wrote, iclass 34, count 2 2006.257.19:00:59.90#ibcon#about to read 3, iclass 34, count 2 2006.257.19:00:59.92#ibcon#read 3, iclass 34, count 2 2006.257.19:00:59.92#ibcon#about to read 4, iclass 34, count 2 2006.257.19:00:59.92#ibcon#read 4, iclass 34, count 2 2006.257.19:00:59.92#ibcon#about to read 5, iclass 34, count 2 2006.257.19:00:59.92#ibcon#read 5, iclass 34, count 2 2006.257.19:00:59.92#ibcon#about to read 6, iclass 34, count 2 2006.257.19:00:59.92#ibcon#read 6, iclass 34, count 2 2006.257.19:00:59.92#ibcon#end of sib2, iclass 34, count 2 2006.257.19:00:59.92#ibcon#*mode == 0, iclass 34, count 2 2006.257.19:00:59.92#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.19:00:59.92#ibcon#[25=AT02-07\r\n] 2006.257.19:00:59.92#ibcon#*before write, iclass 34, count 2 2006.257.19:00:59.92#ibcon#enter sib2, iclass 34, count 2 2006.257.19:00:59.92#ibcon#flushed, iclass 34, count 2 2006.257.19:00:59.92#ibcon#about to write, iclass 34, count 2 2006.257.19:00:59.92#ibcon#wrote, iclass 34, count 2 2006.257.19:00:59.92#ibcon#about to read 3, iclass 34, count 2 2006.257.19:00:59.95#ibcon#read 3, iclass 34, count 2 2006.257.19:00:59.95#ibcon#about to read 4, iclass 34, count 2 2006.257.19:00:59.95#ibcon#read 4, iclass 34, count 2 2006.257.19:00:59.95#ibcon#about to read 5, iclass 34, count 2 2006.257.19:00:59.95#ibcon#read 5, iclass 34, count 2 2006.257.19:00:59.95#ibcon#about to read 6, iclass 34, count 2 2006.257.19:00:59.95#ibcon#read 6, iclass 34, count 2 2006.257.19:00:59.95#ibcon#end of sib2, iclass 34, count 2 2006.257.19:00:59.95#ibcon#*after write, iclass 34, count 2 2006.257.19:00:59.95#ibcon#*before return 0, iclass 34, count 2 2006.257.19:00:59.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:00:59.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:00:59.95#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.19:00:59.95#ibcon#ireg 7 cls_cnt 0 2006.257.19:00:59.95#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:01:00.07#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:01:00.07#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:01:00.07#ibcon#enter wrdev, iclass 34, count 0 2006.257.19:01:00.07#ibcon#first serial, iclass 34, count 0 2006.257.19:01:00.07#ibcon#enter sib2, iclass 34, count 0 2006.257.19:01:00.07#ibcon#flushed, iclass 34, count 0 2006.257.19:01:00.07#ibcon#about to write, iclass 34, count 0 2006.257.19:01:00.07#ibcon#wrote, iclass 34, count 0 2006.257.19:01:00.07#ibcon#about to read 3, iclass 34, count 0 2006.257.19:01:00.09#ibcon#read 3, iclass 34, count 0 2006.257.19:01:00.09#ibcon#about to read 4, iclass 34, count 0 2006.257.19:01:00.09#ibcon#read 4, iclass 34, count 0 2006.257.19:01:00.09#ibcon#about to read 5, iclass 34, count 0 2006.257.19:01:00.09#ibcon#read 5, iclass 34, count 0 2006.257.19:01:00.09#ibcon#about to read 6, iclass 34, count 0 2006.257.19:01:00.09#ibcon#read 6, iclass 34, count 0 2006.257.19:01:00.09#ibcon#end of sib2, iclass 34, count 0 2006.257.19:01:00.09#ibcon#*mode == 0, iclass 34, count 0 2006.257.19:01:00.09#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.19:01:00.09#ibcon#[25=USB\r\n] 2006.257.19:01:00.09#ibcon#*before write, iclass 34, count 0 2006.257.19:01:00.09#ibcon#enter sib2, iclass 34, count 0 2006.257.19:01:00.09#ibcon#flushed, iclass 34, count 0 2006.257.19:01:00.09#ibcon#about to write, iclass 34, count 0 2006.257.19:01:00.09#ibcon#wrote, iclass 34, count 0 2006.257.19:01:00.09#ibcon#about to read 3, iclass 34, count 0 2006.257.19:01:00.12#ibcon#read 3, iclass 34, count 0 2006.257.19:01:00.12#ibcon#about to read 4, iclass 34, count 0 2006.257.19:01:00.12#ibcon#read 4, iclass 34, count 0 2006.257.19:01:00.12#ibcon#about to read 5, iclass 34, count 0 2006.257.19:01:00.12#ibcon#read 5, iclass 34, count 0 2006.257.19:01:00.12#ibcon#about to read 6, iclass 34, count 0 2006.257.19:01:00.12#ibcon#read 6, iclass 34, count 0 2006.257.19:01:00.12#ibcon#end of sib2, iclass 34, count 0 2006.257.19:01:00.12#ibcon#*after write, iclass 34, count 0 2006.257.19:01:00.12#ibcon#*before return 0, iclass 34, count 0 2006.257.19:01:00.12#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:01:00.12#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:01:00.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.19:01:00.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.19:01:00.12$vck44/valo=3,564.99 2006.257.19:01:00.12#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.19:01:00.12#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.19:01:00.12#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:00.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:00.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:00.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:00.12#ibcon#enter wrdev, iclass 36, count 0 2006.257.19:01:00.12#ibcon#first serial, iclass 36, count 0 2006.257.19:01:00.12#ibcon#enter sib2, iclass 36, count 0 2006.257.19:01:00.12#ibcon#flushed, iclass 36, count 0 2006.257.19:01:00.12#ibcon#about to write, iclass 36, count 0 2006.257.19:01:00.12#ibcon#wrote, iclass 36, count 0 2006.257.19:01:00.12#ibcon#about to read 3, iclass 36, count 0 2006.257.19:01:00.14#ibcon#read 3, iclass 36, count 0 2006.257.19:01:00.14#ibcon#about to read 4, iclass 36, count 0 2006.257.19:01:00.14#ibcon#read 4, iclass 36, count 0 2006.257.19:01:00.14#ibcon#about to read 5, iclass 36, count 0 2006.257.19:01:00.14#ibcon#read 5, iclass 36, count 0 2006.257.19:01:00.14#ibcon#about to read 6, iclass 36, count 0 2006.257.19:01:00.14#ibcon#read 6, iclass 36, count 0 2006.257.19:01:00.14#ibcon#end of sib2, iclass 36, count 0 2006.257.19:01:00.14#ibcon#*mode == 0, iclass 36, count 0 2006.257.19:01:00.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.19:01:00.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.19:01:00.14#ibcon#*before write, iclass 36, count 0 2006.257.19:01:00.14#ibcon#enter sib2, iclass 36, count 0 2006.257.19:01:00.14#ibcon#flushed, iclass 36, count 0 2006.257.19:01:00.14#ibcon#about to write, iclass 36, count 0 2006.257.19:01:00.14#ibcon#wrote, iclass 36, count 0 2006.257.19:01:00.14#ibcon#about to read 3, iclass 36, count 0 2006.257.19:01:00.18#ibcon#read 3, iclass 36, count 0 2006.257.19:01:00.18#ibcon#about to read 4, iclass 36, count 0 2006.257.19:01:00.18#ibcon#read 4, iclass 36, count 0 2006.257.19:01:00.18#ibcon#about to read 5, iclass 36, count 0 2006.257.19:01:00.18#ibcon#read 5, iclass 36, count 0 2006.257.19:01:00.18#ibcon#about to read 6, iclass 36, count 0 2006.257.19:01:00.18#ibcon#read 6, iclass 36, count 0 2006.257.19:01:00.18#ibcon#end of sib2, iclass 36, count 0 2006.257.19:01:00.18#ibcon#*after write, iclass 36, count 0 2006.257.19:01:00.18#ibcon#*before return 0, iclass 36, count 0 2006.257.19:01:00.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:00.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:00.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.19:01:00.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.19:01:00.18$vck44/va=3,8 2006.257.19:01:00.18#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.19:01:00.18#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.19:01:00.18#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:00.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:00.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:00.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:00.24#ibcon#enter wrdev, iclass 38, count 2 2006.257.19:01:00.24#ibcon#first serial, iclass 38, count 2 2006.257.19:01:00.24#ibcon#enter sib2, iclass 38, count 2 2006.257.19:01:00.24#ibcon#flushed, iclass 38, count 2 2006.257.19:01:00.24#ibcon#about to write, iclass 38, count 2 2006.257.19:01:00.24#ibcon#wrote, iclass 38, count 2 2006.257.19:01:00.24#ibcon#about to read 3, iclass 38, count 2 2006.257.19:01:00.26#ibcon#read 3, iclass 38, count 2 2006.257.19:01:00.26#ibcon#about to read 4, iclass 38, count 2 2006.257.19:01:00.26#ibcon#read 4, iclass 38, count 2 2006.257.19:01:00.26#ibcon#about to read 5, iclass 38, count 2 2006.257.19:01:00.26#ibcon#read 5, iclass 38, count 2 2006.257.19:01:00.26#ibcon#about to read 6, iclass 38, count 2 2006.257.19:01:00.26#ibcon#read 6, iclass 38, count 2 2006.257.19:01:00.26#ibcon#end of sib2, iclass 38, count 2 2006.257.19:01:00.26#ibcon#*mode == 0, iclass 38, count 2 2006.257.19:01:00.26#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.19:01:00.26#ibcon#[25=AT03-08\r\n] 2006.257.19:01:00.26#ibcon#*before write, iclass 38, count 2 2006.257.19:01:00.26#ibcon#enter sib2, iclass 38, count 2 2006.257.19:01:00.26#ibcon#flushed, iclass 38, count 2 2006.257.19:01:00.26#ibcon#about to write, iclass 38, count 2 2006.257.19:01:00.26#ibcon#wrote, iclass 38, count 2 2006.257.19:01:00.26#ibcon#about to read 3, iclass 38, count 2 2006.257.19:01:00.29#ibcon#read 3, iclass 38, count 2 2006.257.19:01:00.29#ibcon#about to read 4, iclass 38, count 2 2006.257.19:01:00.29#ibcon#read 4, iclass 38, count 2 2006.257.19:01:00.29#ibcon#about to read 5, iclass 38, count 2 2006.257.19:01:00.29#ibcon#read 5, iclass 38, count 2 2006.257.19:01:00.29#ibcon#about to read 6, iclass 38, count 2 2006.257.19:01:00.29#ibcon#read 6, iclass 38, count 2 2006.257.19:01:00.29#ibcon#end of sib2, iclass 38, count 2 2006.257.19:01:00.29#ibcon#*after write, iclass 38, count 2 2006.257.19:01:00.29#ibcon#*before return 0, iclass 38, count 2 2006.257.19:01:00.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:00.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:00.29#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.19:01:00.29#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:00.29#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:00.41#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:00.41#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:00.41#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:01:00.41#ibcon#first serial, iclass 38, count 0 2006.257.19:01:00.41#ibcon#enter sib2, iclass 38, count 0 2006.257.19:01:00.41#ibcon#flushed, iclass 38, count 0 2006.257.19:01:00.41#ibcon#about to write, iclass 38, count 0 2006.257.19:01:00.41#ibcon#wrote, iclass 38, count 0 2006.257.19:01:00.41#ibcon#about to read 3, iclass 38, count 0 2006.257.19:01:00.43#ibcon#read 3, iclass 38, count 0 2006.257.19:01:00.43#ibcon#about to read 4, iclass 38, count 0 2006.257.19:01:00.43#ibcon#read 4, iclass 38, count 0 2006.257.19:01:00.43#ibcon#about to read 5, iclass 38, count 0 2006.257.19:01:00.43#ibcon#read 5, iclass 38, count 0 2006.257.19:01:00.43#ibcon#about to read 6, iclass 38, count 0 2006.257.19:01:00.43#ibcon#read 6, iclass 38, count 0 2006.257.19:01:00.43#ibcon#end of sib2, iclass 38, count 0 2006.257.19:01:00.43#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:01:00.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:01:00.43#ibcon#[25=USB\r\n] 2006.257.19:01:00.43#ibcon#*before write, iclass 38, count 0 2006.257.19:01:00.43#ibcon#enter sib2, iclass 38, count 0 2006.257.19:01:00.43#ibcon#flushed, iclass 38, count 0 2006.257.19:01:00.43#ibcon#about to write, iclass 38, count 0 2006.257.19:01:00.43#ibcon#wrote, iclass 38, count 0 2006.257.19:01:00.43#ibcon#about to read 3, iclass 38, count 0 2006.257.19:01:00.46#ibcon#read 3, iclass 38, count 0 2006.257.19:01:00.46#ibcon#about to read 4, iclass 38, count 0 2006.257.19:01:00.46#ibcon#read 4, iclass 38, count 0 2006.257.19:01:00.46#ibcon#about to read 5, iclass 38, count 0 2006.257.19:01:00.46#ibcon#read 5, iclass 38, count 0 2006.257.19:01:00.46#ibcon#about to read 6, iclass 38, count 0 2006.257.19:01:00.46#ibcon#read 6, iclass 38, count 0 2006.257.19:01:00.46#ibcon#end of sib2, iclass 38, count 0 2006.257.19:01:00.46#ibcon#*after write, iclass 38, count 0 2006.257.19:01:00.46#ibcon#*before return 0, iclass 38, count 0 2006.257.19:01:00.46#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:00.46#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:00.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:01:00.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:01:00.46$vck44/valo=4,624.99 2006.257.19:01:00.46#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.19:01:00.46#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.19:01:00.46#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:00.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:00.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:00.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:00.46#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:01:00.46#ibcon#first serial, iclass 40, count 0 2006.257.19:01:00.46#ibcon#enter sib2, iclass 40, count 0 2006.257.19:01:00.46#ibcon#flushed, iclass 40, count 0 2006.257.19:01:00.46#ibcon#about to write, iclass 40, count 0 2006.257.19:01:00.46#ibcon#wrote, iclass 40, count 0 2006.257.19:01:00.46#ibcon#about to read 3, iclass 40, count 0 2006.257.19:01:00.48#ibcon#read 3, iclass 40, count 0 2006.257.19:01:00.48#ibcon#about to read 4, iclass 40, count 0 2006.257.19:01:00.48#ibcon#read 4, iclass 40, count 0 2006.257.19:01:00.48#ibcon#about to read 5, iclass 40, count 0 2006.257.19:01:00.48#ibcon#read 5, iclass 40, count 0 2006.257.19:01:00.48#ibcon#about to read 6, iclass 40, count 0 2006.257.19:01:00.48#ibcon#read 6, iclass 40, count 0 2006.257.19:01:00.48#ibcon#end of sib2, iclass 40, count 0 2006.257.19:01:00.48#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:01:00.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:01:00.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.19:01:00.48#ibcon#*before write, iclass 40, count 0 2006.257.19:01:00.48#ibcon#enter sib2, iclass 40, count 0 2006.257.19:01:00.48#ibcon#flushed, iclass 40, count 0 2006.257.19:01:00.48#ibcon#about to write, iclass 40, count 0 2006.257.19:01:00.48#ibcon#wrote, iclass 40, count 0 2006.257.19:01:00.48#ibcon#about to read 3, iclass 40, count 0 2006.257.19:01:00.52#ibcon#read 3, iclass 40, count 0 2006.257.19:01:00.52#ibcon#about to read 4, iclass 40, count 0 2006.257.19:01:00.52#ibcon#read 4, iclass 40, count 0 2006.257.19:01:00.52#ibcon#about to read 5, iclass 40, count 0 2006.257.19:01:00.52#ibcon#read 5, iclass 40, count 0 2006.257.19:01:00.52#ibcon#about to read 6, iclass 40, count 0 2006.257.19:01:00.52#ibcon#read 6, iclass 40, count 0 2006.257.19:01:00.52#ibcon#end of sib2, iclass 40, count 0 2006.257.19:01:00.52#ibcon#*after write, iclass 40, count 0 2006.257.19:01:00.52#ibcon#*before return 0, iclass 40, count 0 2006.257.19:01:00.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:00.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:00.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:01:00.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:01:00.52$vck44/va=4,7 2006.257.19:01:00.52#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.19:01:00.52#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.19:01:00.52#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:00.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:00.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:00.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:00.58#ibcon#enter wrdev, iclass 4, count 2 2006.257.19:01:00.58#ibcon#first serial, iclass 4, count 2 2006.257.19:01:00.58#ibcon#enter sib2, iclass 4, count 2 2006.257.19:01:00.58#ibcon#flushed, iclass 4, count 2 2006.257.19:01:00.58#ibcon#about to write, iclass 4, count 2 2006.257.19:01:00.58#ibcon#wrote, iclass 4, count 2 2006.257.19:01:00.58#ibcon#about to read 3, iclass 4, count 2 2006.257.19:01:00.60#ibcon#read 3, iclass 4, count 2 2006.257.19:01:00.60#ibcon#about to read 4, iclass 4, count 2 2006.257.19:01:00.60#ibcon#read 4, iclass 4, count 2 2006.257.19:01:00.60#ibcon#about to read 5, iclass 4, count 2 2006.257.19:01:00.60#ibcon#read 5, iclass 4, count 2 2006.257.19:01:00.60#ibcon#about to read 6, iclass 4, count 2 2006.257.19:01:00.60#ibcon#read 6, iclass 4, count 2 2006.257.19:01:00.60#ibcon#end of sib2, iclass 4, count 2 2006.257.19:01:00.60#ibcon#*mode == 0, iclass 4, count 2 2006.257.19:01:00.60#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.19:01:00.60#ibcon#[25=AT04-07\r\n] 2006.257.19:01:00.60#ibcon#*before write, iclass 4, count 2 2006.257.19:01:00.60#ibcon#enter sib2, iclass 4, count 2 2006.257.19:01:00.60#ibcon#flushed, iclass 4, count 2 2006.257.19:01:00.60#ibcon#about to write, iclass 4, count 2 2006.257.19:01:00.60#ibcon#wrote, iclass 4, count 2 2006.257.19:01:00.60#ibcon#about to read 3, iclass 4, count 2 2006.257.19:01:00.63#ibcon#read 3, iclass 4, count 2 2006.257.19:01:00.63#ibcon#about to read 4, iclass 4, count 2 2006.257.19:01:00.63#ibcon#read 4, iclass 4, count 2 2006.257.19:01:00.63#ibcon#about to read 5, iclass 4, count 2 2006.257.19:01:00.63#ibcon#read 5, iclass 4, count 2 2006.257.19:01:00.63#ibcon#about to read 6, iclass 4, count 2 2006.257.19:01:00.63#ibcon#read 6, iclass 4, count 2 2006.257.19:01:00.63#ibcon#end of sib2, iclass 4, count 2 2006.257.19:01:00.63#ibcon#*after write, iclass 4, count 2 2006.257.19:01:00.63#ibcon#*before return 0, iclass 4, count 2 2006.257.19:01:00.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:00.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:00.63#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.19:01:00.63#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:00.63#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:00.75#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:00.75#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:00.75#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:01:00.75#ibcon#first serial, iclass 4, count 0 2006.257.19:01:00.75#ibcon#enter sib2, iclass 4, count 0 2006.257.19:01:00.75#ibcon#flushed, iclass 4, count 0 2006.257.19:01:00.75#ibcon#about to write, iclass 4, count 0 2006.257.19:01:00.75#ibcon#wrote, iclass 4, count 0 2006.257.19:01:00.75#ibcon#about to read 3, iclass 4, count 0 2006.257.19:01:00.77#ibcon#read 3, iclass 4, count 0 2006.257.19:01:00.77#ibcon#about to read 4, iclass 4, count 0 2006.257.19:01:00.77#ibcon#read 4, iclass 4, count 0 2006.257.19:01:00.77#ibcon#about to read 5, iclass 4, count 0 2006.257.19:01:00.77#ibcon#read 5, iclass 4, count 0 2006.257.19:01:00.77#ibcon#about to read 6, iclass 4, count 0 2006.257.19:01:00.77#ibcon#read 6, iclass 4, count 0 2006.257.19:01:00.77#ibcon#end of sib2, iclass 4, count 0 2006.257.19:01:00.77#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:01:00.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:01:00.77#ibcon#[25=USB\r\n] 2006.257.19:01:00.77#ibcon#*before write, iclass 4, count 0 2006.257.19:01:00.77#ibcon#enter sib2, iclass 4, count 0 2006.257.19:01:00.77#ibcon#flushed, iclass 4, count 0 2006.257.19:01:00.77#ibcon#about to write, iclass 4, count 0 2006.257.19:01:00.77#ibcon#wrote, iclass 4, count 0 2006.257.19:01:00.77#ibcon#about to read 3, iclass 4, count 0 2006.257.19:01:00.80#ibcon#read 3, iclass 4, count 0 2006.257.19:01:00.80#ibcon#about to read 4, iclass 4, count 0 2006.257.19:01:00.80#ibcon#read 4, iclass 4, count 0 2006.257.19:01:00.80#ibcon#about to read 5, iclass 4, count 0 2006.257.19:01:00.80#ibcon#read 5, iclass 4, count 0 2006.257.19:01:00.80#ibcon#about to read 6, iclass 4, count 0 2006.257.19:01:00.80#ibcon#read 6, iclass 4, count 0 2006.257.19:01:00.80#ibcon#end of sib2, iclass 4, count 0 2006.257.19:01:00.80#ibcon#*after write, iclass 4, count 0 2006.257.19:01:00.80#ibcon#*before return 0, iclass 4, count 0 2006.257.19:01:00.80#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:00.80#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:00.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:01:00.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:01:00.80$vck44/valo=5,734.99 2006.257.19:01:00.80#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.19:01:00.80#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.19:01:00.80#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:00.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:00.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:00.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:00.80#ibcon#enter wrdev, iclass 6, count 0 2006.257.19:01:00.80#ibcon#first serial, iclass 6, count 0 2006.257.19:01:00.80#ibcon#enter sib2, iclass 6, count 0 2006.257.19:01:00.80#ibcon#flushed, iclass 6, count 0 2006.257.19:01:00.80#ibcon#about to write, iclass 6, count 0 2006.257.19:01:00.80#ibcon#wrote, iclass 6, count 0 2006.257.19:01:00.80#ibcon#about to read 3, iclass 6, count 0 2006.257.19:01:00.82#ibcon#read 3, iclass 6, count 0 2006.257.19:01:00.82#ibcon#about to read 4, iclass 6, count 0 2006.257.19:01:00.82#ibcon#read 4, iclass 6, count 0 2006.257.19:01:00.82#ibcon#about to read 5, iclass 6, count 0 2006.257.19:01:00.82#ibcon#read 5, iclass 6, count 0 2006.257.19:01:00.82#ibcon#about to read 6, iclass 6, count 0 2006.257.19:01:00.82#ibcon#read 6, iclass 6, count 0 2006.257.19:01:00.82#ibcon#end of sib2, iclass 6, count 0 2006.257.19:01:00.82#ibcon#*mode == 0, iclass 6, count 0 2006.257.19:01:00.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.19:01:00.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.19:01:00.82#ibcon#*before write, iclass 6, count 0 2006.257.19:01:00.82#ibcon#enter sib2, iclass 6, count 0 2006.257.19:01:00.82#ibcon#flushed, iclass 6, count 0 2006.257.19:01:00.82#ibcon#about to write, iclass 6, count 0 2006.257.19:01:00.82#ibcon#wrote, iclass 6, count 0 2006.257.19:01:00.82#ibcon#about to read 3, iclass 6, count 0 2006.257.19:01:00.86#ibcon#read 3, iclass 6, count 0 2006.257.19:01:00.86#ibcon#about to read 4, iclass 6, count 0 2006.257.19:01:00.86#ibcon#read 4, iclass 6, count 0 2006.257.19:01:00.86#ibcon#about to read 5, iclass 6, count 0 2006.257.19:01:00.86#ibcon#read 5, iclass 6, count 0 2006.257.19:01:00.86#ibcon#about to read 6, iclass 6, count 0 2006.257.19:01:00.86#ibcon#read 6, iclass 6, count 0 2006.257.19:01:00.86#ibcon#end of sib2, iclass 6, count 0 2006.257.19:01:00.86#ibcon#*after write, iclass 6, count 0 2006.257.19:01:00.86#ibcon#*before return 0, iclass 6, count 0 2006.257.19:01:00.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:00.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:00.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.19:01:00.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.19:01:00.86$vck44/va=5,4 2006.257.19:01:00.86#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.19:01:00.86#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.19:01:00.86#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:00.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:00.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:00.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:00.92#ibcon#enter wrdev, iclass 10, count 2 2006.257.19:01:00.92#ibcon#first serial, iclass 10, count 2 2006.257.19:01:00.92#ibcon#enter sib2, iclass 10, count 2 2006.257.19:01:00.92#ibcon#flushed, iclass 10, count 2 2006.257.19:01:00.92#ibcon#about to write, iclass 10, count 2 2006.257.19:01:00.92#ibcon#wrote, iclass 10, count 2 2006.257.19:01:00.92#ibcon#about to read 3, iclass 10, count 2 2006.257.19:01:00.94#ibcon#read 3, iclass 10, count 2 2006.257.19:01:00.94#ibcon#about to read 4, iclass 10, count 2 2006.257.19:01:00.94#ibcon#read 4, iclass 10, count 2 2006.257.19:01:00.94#ibcon#about to read 5, iclass 10, count 2 2006.257.19:01:00.94#ibcon#read 5, iclass 10, count 2 2006.257.19:01:00.94#ibcon#about to read 6, iclass 10, count 2 2006.257.19:01:00.94#ibcon#read 6, iclass 10, count 2 2006.257.19:01:00.94#ibcon#end of sib2, iclass 10, count 2 2006.257.19:01:00.94#ibcon#*mode == 0, iclass 10, count 2 2006.257.19:01:00.94#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.19:01:00.94#ibcon#[25=AT05-04\r\n] 2006.257.19:01:00.94#ibcon#*before write, iclass 10, count 2 2006.257.19:01:00.94#ibcon#enter sib2, iclass 10, count 2 2006.257.19:01:00.94#ibcon#flushed, iclass 10, count 2 2006.257.19:01:00.94#ibcon#about to write, iclass 10, count 2 2006.257.19:01:00.94#ibcon#wrote, iclass 10, count 2 2006.257.19:01:00.94#ibcon#about to read 3, iclass 10, count 2 2006.257.19:01:00.97#ibcon#read 3, iclass 10, count 2 2006.257.19:01:00.97#ibcon#about to read 4, iclass 10, count 2 2006.257.19:01:00.97#ibcon#read 4, iclass 10, count 2 2006.257.19:01:00.97#ibcon#about to read 5, iclass 10, count 2 2006.257.19:01:00.97#ibcon#read 5, iclass 10, count 2 2006.257.19:01:00.97#ibcon#about to read 6, iclass 10, count 2 2006.257.19:01:00.97#ibcon#read 6, iclass 10, count 2 2006.257.19:01:00.97#ibcon#end of sib2, iclass 10, count 2 2006.257.19:01:00.97#ibcon#*after write, iclass 10, count 2 2006.257.19:01:00.97#ibcon#*before return 0, iclass 10, count 2 2006.257.19:01:00.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:00.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:00.97#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.19:01:00.97#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:00.97#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:01.09#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:01.09#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:01.09#ibcon#enter wrdev, iclass 10, count 0 2006.257.19:01:01.09#ibcon#first serial, iclass 10, count 0 2006.257.19:01:01.09#ibcon#enter sib2, iclass 10, count 0 2006.257.19:01:01.09#ibcon#flushed, iclass 10, count 0 2006.257.19:01:01.09#ibcon#about to write, iclass 10, count 0 2006.257.19:01:01.09#ibcon#wrote, iclass 10, count 0 2006.257.19:01:01.09#ibcon#about to read 3, iclass 10, count 0 2006.257.19:01:01.11#ibcon#read 3, iclass 10, count 0 2006.257.19:01:01.11#ibcon#about to read 4, iclass 10, count 0 2006.257.19:01:01.11#ibcon#read 4, iclass 10, count 0 2006.257.19:01:01.11#ibcon#about to read 5, iclass 10, count 0 2006.257.19:01:01.11#ibcon#read 5, iclass 10, count 0 2006.257.19:01:01.11#ibcon#about to read 6, iclass 10, count 0 2006.257.19:01:01.11#ibcon#read 6, iclass 10, count 0 2006.257.19:01:01.11#ibcon#end of sib2, iclass 10, count 0 2006.257.19:01:01.11#ibcon#*mode == 0, iclass 10, count 0 2006.257.19:01:01.11#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.19:01:01.11#ibcon#[25=USB\r\n] 2006.257.19:01:01.11#ibcon#*before write, iclass 10, count 0 2006.257.19:01:01.11#ibcon#enter sib2, iclass 10, count 0 2006.257.19:01:01.11#ibcon#flushed, iclass 10, count 0 2006.257.19:01:01.11#ibcon#about to write, iclass 10, count 0 2006.257.19:01:01.11#ibcon#wrote, iclass 10, count 0 2006.257.19:01:01.11#ibcon#about to read 3, iclass 10, count 0 2006.257.19:01:01.14#ibcon#read 3, iclass 10, count 0 2006.257.19:01:01.14#ibcon#about to read 4, iclass 10, count 0 2006.257.19:01:01.14#ibcon#read 4, iclass 10, count 0 2006.257.19:01:01.14#ibcon#about to read 5, iclass 10, count 0 2006.257.19:01:01.14#ibcon#read 5, iclass 10, count 0 2006.257.19:01:01.14#ibcon#about to read 6, iclass 10, count 0 2006.257.19:01:01.14#ibcon#read 6, iclass 10, count 0 2006.257.19:01:01.14#ibcon#end of sib2, iclass 10, count 0 2006.257.19:01:01.14#ibcon#*after write, iclass 10, count 0 2006.257.19:01:01.14#ibcon#*before return 0, iclass 10, count 0 2006.257.19:01:01.14#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:01.14#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:01.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.19:01:01.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.19:01:01.14$vck44/valo=6,814.99 2006.257.19:01:01.14#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.19:01:01.14#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.19:01:01.14#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:01.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:01.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:01.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:01.14#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:01:01.14#ibcon#first serial, iclass 12, count 0 2006.257.19:01:01.14#ibcon#enter sib2, iclass 12, count 0 2006.257.19:01:01.14#ibcon#flushed, iclass 12, count 0 2006.257.19:01:01.14#ibcon#about to write, iclass 12, count 0 2006.257.19:01:01.14#ibcon#wrote, iclass 12, count 0 2006.257.19:01:01.14#ibcon#about to read 3, iclass 12, count 0 2006.257.19:01:01.16#ibcon#read 3, iclass 12, count 0 2006.257.19:01:01.16#ibcon#about to read 4, iclass 12, count 0 2006.257.19:01:01.16#ibcon#read 4, iclass 12, count 0 2006.257.19:01:01.16#ibcon#about to read 5, iclass 12, count 0 2006.257.19:01:01.16#ibcon#read 5, iclass 12, count 0 2006.257.19:01:01.16#ibcon#about to read 6, iclass 12, count 0 2006.257.19:01:01.16#ibcon#read 6, iclass 12, count 0 2006.257.19:01:01.16#ibcon#end of sib2, iclass 12, count 0 2006.257.19:01:01.16#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:01:01.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:01:01.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.19:01:01.16#ibcon#*before write, iclass 12, count 0 2006.257.19:01:01.16#ibcon#enter sib2, iclass 12, count 0 2006.257.19:01:01.16#ibcon#flushed, iclass 12, count 0 2006.257.19:01:01.16#ibcon#about to write, iclass 12, count 0 2006.257.19:01:01.16#ibcon#wrote, iclass 12, count 0 2006.257.19:01:01.16#ibcon#about to read 3, iclass 12, count 0 2006.257.19:01:01.20#ibcon#read 3, iclass 12, count 0 2006.257.19:01:01.20#ibcon#about to read 4, iclass 12, count 0 2006.257.19:01:01.20#ibcon#read 4, iclass 12, count 0 2006.257.19:01:01.20#ibcon#about to read 5, iclass 12, count 0 2006.257.19:01:01.20#ibcon#read 5, iclass 12, count 0 2006.257.19:01:01.20#ibcon#about to read 6, iclass 12, count 0 2006.257.19:01:01.20#ibcon#read 6, iclass 12, count 0 2006.257.19:01:01.20#ibcon#end of sib2, iclass 12, count 0 2006.257.19:01:01.20#ibcon#*after write, iclass 12, count 0 2006.257.19:01:01.20#ibcon#*before return 0, iclass 12, count 0 2006.257.19:01:01.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:01.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:01.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:01:01.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:01:01.20$vck44/va=6,4 2006.257.19:01:01.20#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.19:01:01.20#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.19:01:01.20#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:01.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:01.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:01.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:01.26#ibcon#enter wrdev, iclass 14, count 2 2006.257.19:01:01.26#ibcon#first serial, iclass 14, count 2 2006.257.19:01:01.26#ibcon#enter sib2, iclass 14, count 2 2006.257.19:01:01.26#ibcon#flushed, iclass 14, count 2 2006.257.19:01:01.26#ibcon#about to write, iclass 14, count 2 2006.257.19:01:01.26#ibcon#wrote, iclass 14, count 2 2006.257.19:01:01.26#ibcon#about to read 3, iclass 14, count 2 2006.257.19:01:01.28#ibcon#read 3, iclass 14, count 2 2006.257.19:01:01.28#ibcon#about to read 4, iclass 14, count 2 2006.257.19:01:01.28#ibcon#read 4, iclass 14, count 2 2006.257.19:01:01.28#ibcon#about to read 5, iclass 14, count 2 2006.257.19:01:01.28#ibcon#read 5, iclass 14, count 2 2006.257.19:01:01.28#ibcon#about to read 6, iclass 14, count 2 2006.257.19:01:01.28#ibcon#read 6, iclass 14, count 2 2006.257.19:01:01.28#ibcon#end of sib2, iclass 14, count 2 2006.257.19:01:01.28#ibcon#*mode == 0, iclass 14, count 2 2006.257.19:01:01.28#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.19:01:01.28#ibcon#[25=AT06-04\r\n] 2006.257.19:01:01.28#ibcon#*before write, iclass 14, count 2 2006.257.19:01:01.28#ibcon#enter sib2, iclass 14, count 2 2006.257.19:01:01.28#ibcon#flushed, iclass 14, count 2 2006.257.19:01:01.28#ibcon#about to write, iclass 14, count 2 2006.257.19:01:01.28#ibcon#wrote, iclass 14, count 2 2006.257.19:01:01.28#ibcon#about to read 3, iclass 14, count 2 2006.257.19:01:01.31#ibcon#read 3, iclass 14, count 2 2006.257.19:01:01.31#ibcon#about to read 4, iclass 14, count 2 2006.257.19:01:01.31#ibcon#read 4, iclass 14, count 2 2006.257.19:01:01.31#ibcon#about to read 5, iclass 14, count 2 2006.257.19:01:01.31#ibcon#read 5, iclass 14, count 2 2006.257.19:01:01.31#ibcon#about to read 6, iclass 14, count 2 2006.257.19:01:01.31#ibcon#read 6, iclass 14, count 2 2006.257.19:01:01.31#ibcon#end of sib2, iclass 14, count 2 2006.257.19:01:01.31#ibcon#*after write, iclass 14, count 2 2006.257.19:01:01.31#ibcon#*before return 0, iclass 14, count 2 2006.257.19:01:01.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:01.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:01.31#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.19:01:01.31#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:01.31#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:01.43#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:01.43#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:01.43#ibcon#enter wrdev, iclass 14, count 0 2006.257.19:01:01.43#ibcon#first serial, iclass 14, count 0 2006.257.19:01:01.43#ibcon#enter sib2, iclass 14, count 0 2006.257.19:01:01.43#ibcon#flushed, iclass 14, count 0 2006.257.19:01:01.43#ibcon#about to write, iclass 14, count 0 2006.257.19:01:01.43#ibcon#wrote, iclass 14, count 0 2006.257.19:01:01.43#ibcon#about to read 3, iclass 14, count 0 2006.257.19:01:01.45#ibcon#read 3, iclass 14, count 0 2006.257.19:01:01.45#ibcon#about to read 4, iclass 14, count 0 2006.257.19:01:01.45#ibcon#read 4, iclass 14, count 0 2006.257.19:01:01.45#ibcon#about to read 5, iclass 14, count 0 2006.257.19:01:01.45#ibcon#read 5, iclass 14, count 0 2006.257.19:01:01.45#ibcon#about to read 6, iclass 14, count 0 2006.257.19:01:01.45#ibcon#read 6, iclass 14, count 0 2006.257.19:01:01.45#ibcon#end of sib2, iclass 14, count 0 2006.257.19:01:01.45#ibcon#*mode == 0, iclass 14, count 0 2006.257.19:01:01.45#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.19:01:01.45#ibcon#[25=USB\r\n] 2006.257.19:01:01.45#ibcon#*before write, iclass 14, count 0 2006.257.19:01:01.45#ibcon#enter sib2, iclass 14, count 0 2006.257.19:01:01.45#ibcon#flushed, iclass 14, count 0 2006.257.19:01:01.45#ibcon#about to write, iclass 14, count 0 2006.257.19:01:01.45#ibcon#wrote, iclass 14, count 0 2006.257.19:01:01.45#ibcon#about to read 3, iclass 14, count 0 2006.257.19:01:01.48#ibcon#read 3, iclass 14, count 0 2006.257.19:01:01.48#ibcon#about to read 4, iclass 14, count 0 2006.257.19:01:01.48#ibcon#read 4, iclass 14, count 0 2006.257.19:01:01.48#ibcon#about to read 5, iclass 14, count 0 2006.257.19:01:01.48#ibcon#read 5, iclass 14, count 0 2006.257.19:01:01.48#ibcon#about to read 6, iclass 14, count 0 2006.257.19:01:01.48#ibcon#read 6, iclass 14, count 0 2006.257.19:01:01.48#ibcon#end of sib2, iclass 14, count 0 2006.257.19:01:01.48#ibcon#*after write, iclass 14, count 0 2006.257.19:01:01.48#ibcon#*before return 0, iclass 14, count 0 2006.257.19:01:01.48#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:01.48#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:01.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.19:01:01.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.19:01:01.48$vck44/valo=7,864.99 2006.257.19:01:01.48#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.19:01:01.48#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.19:01:01.48#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:01.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:01.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:01.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:01.48#ibcon#enter wrdev, iclass 16, count 0 2006.257.19:01:01.48#ibcon#first serial, iclass 16, count 0 2006.257.19:01:01.48#ibcon#enter sib2, iclass 16, count 0 2006.257.19:01:01.48#ibcon#flushed, iclass 16, count 0 2006.257.19:01:01.48#ibcon#about to write, iclass 16, count 0 2006.257.19:01:01.48#ibcon#wrote, iclass 16, count 0 2006.257.19:01:01.48#ibcon#about to read 3, iclass 16, count 0 2006.257.19:01:01.50#ibcon#read 3, iclass 16, count 0 2006.257.19:01:01.50#ibcon#about to read 4, iclass 16, count 0 2006.257.19:01:01.50#ibcon#read 4, iclass 16, count 0 2006.257.19:01:01.50#ibcon#about to read 5, iclass 16, count 0 2006.257.19:01:01.50#ibcon#read 5, iclass 16, count 0 2006.257.19:01:01.50#ibcon#about to read 6, iclass 16, count 0 2006.257.19:01:01.50#ibcon#read 6, iclass 16, count 0 2006.257.19:01:01.50#ibcon#end of sib2, iclass 16, count 0 2006.257.19:01:01.50#ibcon#*mode == 0, iclass 16, count 0 2006.257.19:01:01.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.19:01:01.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.19:01:01.50#ibcon#*before write, iclass 16, count 0 2006.257.19:01:01.50#ibcon#enter sib2, iclass 16, count 0 2006.257.19:01:01.50#ibcon#flushed, iclass 16, count 0 2006.257.19:01:01.50#ibcon#about to write, iclass 16, count 0 2006.257.19:01:01.50#ibcon#wrote, iclass 16, count 0 2006.257.19:01:01.50#ibcon#about to read 3, iclass 16, count 0 2006.257.19:01:01.54#ibcon#read 3, iclass 16, count 0 2006.257.19:01:01.54#ibcon#about to read 4, iclass 16, count 0 2006.257.19:01:01.54#ibcon#read 4, iclass 16, count 0 2006.257.19:01:01.54#ibcon#about to read 5, iclass 16, count 0 2006.257.19:01:01.54#ibcon#read 5, iclass 16, count 0 2006.257.19:01:01.54#ibcon#about to read 6, iclass 16, count 0 2006.257.19:01:01.54#ibcon#read 6, iclass 16, count 0 2006.257.19:01:01.54#ibcon#end of sib2, iclass 16, count 0 2006.257.19:01:01.54#ibcon#*after write, iclass 16, count 0 2006.257.19:01:01.54#ibcon#*before return 0, iclass 16, count 0 2006.257.19:01:01.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:01.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:01.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.19:01:01.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.19:01:01.54$vck44/va=7,4 2006.257.19:01:01.54#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.19:01:01.54#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.19:01:01.54#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:01.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:01.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:01.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:01.60#ibcon#enter wrdev, iclass 18, count 2 2006.257.19:01:01.60#ibcon#first serial, iclass 18, count 2 2006.257.19:01:01.60#ibcon#enter sib2, iclass 18, count 2 2006.257.19:01:01.60#ibcon#flushed, iclass 18, count 2 2006.257.19:01:01.60#ibcon#about to write, iclass 18, count 2 2006.257.19:01:01.60#ibcon#wrote, iclass 18, count 2 2006.257.19:01:01.60#ibcon#about to read 3, iclass 18, count 2 2006.257.19:01:01.62#ibcon#read 3, iclass 18, count 2 2006.257.19:01:01.62#ibcon#about to read 4, iclass 18, count 2 2006.257.19:01:01.62#ibcon#read 4, iclass 18, count 2 2006.257.19:01:01.62#ibcon#about to read 5, iclass 18, count 2 2006.257.19:01:01.62#ibcon#read 5, iclass 18, count 2 2006.257.19:01:01.62#ibcon#about to read 6, iclass 18, count 2 2006.257.19:01:01.62#ibcon#read 6, iclass 18, count 2 2006.257.19:01:01.62#ibcon#end of sib2, iclass 18, count 2 2006.257.19:01:01.62#ibcon#*mode == 0, iclass 18, count 2 2006.257.19:01:01.62#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.19:01:01.62#ibcon#[25=AT07-04\r\n] 2006.257.19:01:01.62#ibcon#*before write, iclass 18, count 2 2006.257.19:01:01.62#ibcon#enter sib2, iclass 18, count 2 2006.257.19:01:01.62#ibcon#flushed, iclass 18, count 2 2006.257.19:01:01.62#ibcon#about to write, iclass 18, count 2 2006.257.19:01:01.62#ibcon#wrote, iclass 18, count 2 2006.257.19:01:01.62#ibcon#about to read 3, iclass 18, count 2 2006.257.19:01:01.65#ibcon#read 3, iclass 18, count 2 2006.257.19:01:01.65#ibcon#about to read 4, iclass 18, count 2 2006.257.19:01:01.65#ibcon#read 4, iclass 18, count 2 2006.257.19:01:01.65#ibcon#about to read 5, iclass 18, count 2 2006.257.19:01:01.65#ibcon#read 5, iclass 18, count 2 2006.257.19:01:01.65#ibcon#about to read 6, iclass 18, count 2 2006.257.19:01:01.65#ibcon#read 6, iclass 18, count 2 2006.257.19:01:01.65#ibcon#end of sib2, iclass 18, count 2 2006.257.19:01:01.65#ibcon#*after write, iclass 18, count 2 2006.257.19:01:01.65#ibcon#*before return 0, iclass 18, count 2 2006.257.19:01:01.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:01.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:01.65#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.19:01:01.65#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:01.65#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:01.77#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:01.77#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:01.77#ibcon#enter wrdev, iclass 18, count 0 2006.257.19:01:01.77#ibcon#first serial, iclass 18, count 0 2006.257.19:01:01.77#ibcon#enter sib2, iclass 18, count 0 2006.257.19:01:01.77#ibcon#flushed, iclass 18, count 0 2006.257.19:01:01.77#ibcon#about to write, iclass 18, count 0 2006.257.19:01:01.77#ibcon#wrote, iclass 18, count 0 2006.257.19:01:01.77#ibcon#about to read 3, iclass 18, count 0 2006.257.19:01:01.79#ibcon#read 3, iclass 18, count 0 2006.257.19:01:01.79#ibcon#about to read 4, iclass 18, count 0 2006.257.19:01:01.79#ibcon#read 4, iclass 18, count 0 2006.257.19:01:01.79#ibcon#about to read 5, iclass 18, count 0 2006.257.19:01:01.79#ibcon#read 5, iclass 18, count 0 2006.257.19:01:01.79#ibcon#about to read 6, iclass 18, count 0 2006.257.19:01:01.79#ibcon#read 6, iclass 18, count 0 2006.257.19:01:01.79#ibcon#end of sib2, iclass 18, count 0 2006.257.19:01:01.79#ibcon#*mode == 0, iclass 18, count 0 2006.257.19:01:01.79#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.19:01:01.79#ibcon#[25=USB\r\n] 2006.257.19:01:01.79#ibcon#*before write, iclass 18, count 0 2006.257.19:01:01.79#ibcon#enter sib2, iclass 18, count 0 2006.257.19:01:01.79#ibcon#flushed, iclass 18, count 0 2006.257.19:01:01.79#ibcon#about to write, iclass 18, count 0 2006.257.19:01:01.79#ibcon#wrote, iclass 18, count 0 2006.257.19:01:01.79#ibcon#about to read 3, iclass 18, count 0 2006.257.19:01:01.82#ibcon#read 3, iclass 18, count 0 2006.257.19:01:01.82#ibcon#about to read 4, iclass 18, count 0 2006.257.19:01:01.82#ibcon#read 4, iclass 18, count 0 2006.257.19:01:01.82#ibcon#about to read 5, iclass 18, count 0 2006.257.19:01:01.82#ibcon#read 5, iclass 18, count 0 2006.257.19:01:01.82#ibcon#about to read 6, iclass 18, count 0 2006.257.19:01:01.82#ibcon#read 6, iclass 18, count 0 2006.257.19:01:01.82#ibcon#end of sib2, iclass 18, count 0 2006.257.19:01:01.82#ibcon#*after write, iclass 18, count 0 2006.257.19:01:01.82#ibcon#*before return 0, iclass 18, count 0 2006.257.19:01:01.82#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:01.82#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:01.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.19:01:01.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.19:01:01.82$vck44/valo=8,884.99 2006.257.19:01:01.82#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.19:01:01.82#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.19:01:01.82#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:01.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:01.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:01.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:01.82#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:01:01.82#ibcon#first serial, iclass 20, count 0 2006.257.19:01:01.82#ibcon#enter sib2, iclass 20, count 0 2006.257.19:01:01.82#ibcon#flushed, iclass 20, count 0 2006.257.19:01:01.82#ibcon#about to write, iclass 20, count 0 2006.257.19:01:01.82#ibcon#wrote, iclass 20, count 0 2006.257.19:01:01.82#ibcon#about to read 3, iclass 20, count 0 2006.257.19:01:01.84#ibcon#read 3, iclass 20, count 0 2006.257.19:01:01.84#ibcon#about to read 4, iclass 20, count 0 2006.257.19:01:01.84#ibcon#read 4, iclass 20, count 0 2006.257.19:01:01.84#ibcon#about to read 5, iclass 20, count 0 2006.257.19:01:01.84#ibcon#read 5, iclass 20, count 0 2006.257.19:01:01.84#ibcon#about to read 6, iclass 20, count 0 2006.257.19:01:01.84#ibcon#read 6, iclass 20, count 0 2006.257.19:01:01.84#ibcon#end of sib2, iclass 20, count 0 2006.257.19:01:01.84#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:01:01.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:01:01.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.19:01:01.84#ibcon#*before write, iclass 20, count 0 2006.257.19:01:01.84#ibcon#enter sib2, iclass 20, count 0 2006.257.19:01:01.84#ibcon#flushed, iclass 20, count 0 2006.257.19:01:01.84#ibcon#about to write, iclass 20, count 0 2006.257.19:01:01.84#ibcon#wrote, iclass 20, count 0 2006.257.19:01:01.84#ibcon#about to read 3, iclass 20, count 0 2006.257.19:01:01.88#ibcon#read 3, iclass 20, count 0 2006.257.19:01:01.88#ibcon#about to read 4, iclass 20, count 0 2006.257.19:01:01.88#ibcon#read 4, iclass 20, count 0 2006.257.19:01:01.88#ibcon#about to read 5, iclass 20, count 0 2006.257.19:01:01.88#ibcon#read 5, iclass 20, count 0 2006.257.19:01:01.88#ibcon#about to read 6, iclass 20, count 0 2006.257.19:01:01.88#ibcon#read 6, iclass 20, count 0 2006.257.19:01:01.88#ibcon#end of sib2, iclass 20, count 0 2006.257.19:01:01.88#ibcon#*after write, iclass 20, count 0 2006.257.19:01:01.88#ibcon#*before return 0, iclass 20, count 0 2006.257.19:01:01.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:01.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:01.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:01:01.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:01:01.88$vck44/va=8,4 2006.257.19:01:01.88#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.19:01:01.88#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.19:01:01.88#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:01.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:01.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:01.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:01.94#ibcon#enter wrdev, iclass 22, count 2 2006.257.19:01:01.94#ibcon#first serial, iclass 22, count 2 2006.257.19:01:01.94#ibcon#enter sib2, iclass 22, count 2 2006.257.19:01:01.94#ibcon#flushed, iclass 22, count 2 2006.257.19:01:01.94#ibcon#about to write, iclass 22, count 2 2006.257.19:01:01.94#ibcon#wrote, iclass 22, count 2 2006.257.19:01:01.94#ibcon#about to read 3, iclass 22, count 2 2006.257.19:01:01.96#ibcon#read 3, iclass 22, count 2 2006.257.19:01:01.96#ibcon#about to read 4, iclass 22, count 2 2006.257.19:01:01.96#ibcon#read 4, iclass 22, count 2 2006.257.19:01:01.96#ibcon#about to read 5, iclass 22, count 2 2006.257.19:01:01.96#ibcon#read 5, iclass 22, count 2 2006.257.19:01:01.96#ibcon#about to read 6, iclass 22, count 2 2006.257.19:01:01.96#ibcon#read 6, iclass 22, count 2 2006.257.19:01:01.96#ibcon#end of sib2, iclass 22, count 2 2006.257.19:01:01.96#ibcon#*mode == 0, iclass 22, count 2 2006.257.19:01:01.96#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.19:01:01.96#ibcon#[25=AT08-04\r\n] 2006.257.19:01:01.96#ibcon#*before write, iclass 22, count 2 2006.257.19:01:01.96#ibcon#enter sib2, iclass 22, count 2 2006.257.19:01:01.96#ibcon#flushed, iclass 22, count 2 2006.257.19:01:01.96#ibcon#about to write, iclass 22, count 2 2006.257.19:01:01.96#ibcon#wrote, iclass 22, count 2 2006.257.19:01:01.96#ibcon#about to read 3, iclass 22, count 2 2006.257.19:01:01.99#ibcon#read 3, iclass 22, count 2 2006.257.19:01:01.99#ibcon#about to read 4, iclass 22, count 2 2006.257.19:01:01.99#ibcon#read 4, iclass 22, count 2 2006.257.19:01:01.99#ibcon#about to read 5, iclass 22, count 2 2006.257.19:01:01.99#ibcon#read 5, iclass 22, count 2 2006.257.19:01:01.99#ibcon#about to read 6, iclass 22, count 2 2006.257.19:01:01.99#ibcon#read 6, iclass 22, count 2 2006.257.19:01:01.99#ibcon#end of sib2, iclass 22, count 2 2006.257.19:01:01.99#ibcon#*after write, iclass 22, count 2 2006.257.19:01:01.99#ibcon#*before return 0, iclass 22, count 2 2006.257.19:01:01.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:01.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:01.99#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.19:01:01.99#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:01.99#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:02.11#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:02.11#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:02.11#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:01:02.11#ibcon#first serial, iclass 22, count 0 2006.257.19:01:02.11#ibcon#enter sib2, iclass 22, count 0 2006.257.19:01:02.11#ibcon#flushed, iclass 22, count 0 2006.257.19:01:02.11#ibcon#about to write, iclass 22, count 0 2006.257.19:01:02.11#ibcon#wrote, iclass 22, count 0 2006.257.19:01:02.11#ibcon#about to read 3, iclass 22, count 0 2006.257.19:01:02.13#ibcon#read 3, iclass 22, count 0 2006.257.19:01:02.13#ibcon#about to read 4, iclass 22, count 0 2006.257.19:01:02.13#ibcon#read 4, iclass 22, count 0 2006.257.19:01:02.13#ibcon#about to read 5, iclass 22, count 0 2006.257.19:01:02.13#ibcon#read 5, iclass 22, count 0 2006.257.19:01:02.13#ibcon#about to read 6, iclass 22, count 0 2006.257.19:01:02.13#ibcon#read 6, iclass 22, count 0 2006.257.19:01:02.13#ibcon#end of sib2, iclass 22, count 0 2006.257.19:01:02.13#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:01:02.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:01:02.13#ibcon#[25=USB\r\n] 2006.257.19:01:02.13#ibcon#*before write, iclass 22, count 0 2006.257.19:01:02.13#ibcon#enter sib2, iclass 22, count 0 2006.257.19:01:02.13#ibcon#flushed, iclass 22, count 0 2006.257.19:01:02.13#ibcon#about to write, iclass 22, count 0 2006.257.19:01:02.13#ibcon#wrote, iclass 22, count 0 2006.257.19:01:02.13#ibcon#about to read 3, iclass 22, count 0 2006.257.19:01:02.16#ibcon#read 3, iclass 22, count 0 2006.257.19:01:02.16#ibcon#about to read 4, iclass 22, count 0 2006.257.19:01:02.16#ibcon#read 4, iclass 22, count 0 2006.257.19:01:02.16#ibcon#about to read 5, iclass 22, count 0 2006.257.19:01:02.16#ibcon#read 5, iclass 22, count 0 2006.257.19:01:02.16#ibcon#about to read 6, iclass 22, count 0 2006.257.19:01:02.16#ibcon#read 6, iclass 22, count 0 2006.257.19:01:02.16#ibcon#end of sib2, iclass 22, count 0 2006.257.19:01:02.16#ibcon#*after write, iclass 22, count 0 2006.257.19:01:02.16#ibcon#*before return 0, iclass 22, count 0 2006.257.19:01:02.16#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:02.16#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:02.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:01:02.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:01:02.16$vck44/vblo=1,629.99 2006.257.19:01:02.16#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.19:01:02.16#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.19:01:02.16#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:02.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:02.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:02.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:02.16#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:01:02.16#ibcon#first serial, iclass 24, count 0 2006.257.19:01:02.16#ibcon#enter sib2, iclass 24, count 0 2006.257.19:01:02.16#ibcon#flushed, iclass 24, count 0 2006.257.19:01:02.16#ibcon#about to write, iclass 24, count 0 2006.257.19:01:02.16#ibcon#wrote, iclass 24, count 0 2006.257.19:01:02.16#ibcon#about to read 3, iclass 24, count 0 2006.257.19:01:02.18#ibcon#read 3, iclass 24, count 0 2006.257.19:01:02.18#ibcon#about to read 4, iclass 24, count 0 2006.257.19:01:02.18#ibcon#read 4, iclass 24, count 0 2006.257.19:01:02.18#ibcon#about to read 5, iclass 24, count 0 2006.257.19:01:02.18#ibcon#read 5, iclass 24, count 0 2006.257.19:01:02.18#ibcon#about to read 6, iclass 24, count 0 2006.257.19:01:02.18#ibcon#read 6, iclass 24, count 0 2006.257.19:01:02.18#ibcon#end of sib2, iclass 24, count 0 2006.257.19:01:02.18#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:01:02.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:01:02.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.19:01:02.18#ibcon#*before write, iclass 24, count 0 2006.257.19:01:02.18#ibcon#enter sib2, iclass 24, count 0 2006.257.19:01:02.18#ibcon#flushed, iclass 24, count 0 2006.257.19:01:02.18#ibcon#about to write, iclass 24, count 0 2006.257.19:01:02.18#ibcon#wrote, iclass 24, count 0 2006.257.19:01:02.18#ibcon#about to read 3, iclass 24, count 0 2006.257.19:01:02.22#ibcon#read 3, iclass 24, count 0 2006.257.19:01:02.22#ibcon#about to read 4, iclass 24, count 0 2006.257.19:01:02.22#ibcon#read 4, iclass 24, count 0 2006.257.19:01:02.22#ibcon#about to read 5, iclass 24, count 0 2006.257.19:01:02.22#ibcon#read 5, iclass 24, count 0 2006.257.19:01:02.22#ibcon#about to read 6, iclass 24, count 0 2006.257.19:01:02.22#ibcon#read 6, iclass 24, count 0 2006.257.19:01:02.22#ibcon#end of sib2, iclass 24, count 0 2006.257.19:01:02.22#ibcon#*after write, iclass 24, count 0 2006.257.19:01:02.22#ibcon#*before return 0, iclass 24, count 0 2006.257.19:01:02.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:02.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:02.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:01:02.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:01:02.22$vck44/vb=1,4 2006.257.19:01:02.22#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.19:01:02.22#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.19:01:02.22#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:02.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:01:02.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:01:02.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:01:02.22#ibcon#enter wrdev, iclass 26, count 2 2006.257.19:01:02.22#ibcon#first serial, iclass 26, count 2 2006.257.19:01:02.22#ibcon#enter sib2, iclass 26, count 2 2006.257.19:01:02.22#ibcon#flushed, iclass 26, count 2 2006.257.19:01:02.22#ibcon#about to write, iclass 26, count 2 2006.257.19:01:02.22#ibcon#wrote, iclass 26, count 2 2006.257.19:01:02.22#ibcon#about to read 3, iclass 26, count 2 2006.257.19:01:02.24#ibcon#read 3, iclass 26, count 2 2006.257.19:01:02.24#ibcon#about to read 4, iclass 26, count 2 2006.257.19:01:02.24#ibcon#read 4, iclass 26, count 2 2006.257.19:01:02.24#ibcon#about to read 5, iclass 26, count 2 2006.257.19:01:02.24#ibcon#read 5, iclass 26, count 2 2006.257.19:01:02.24#ibcon#about to read 6, iclass 26, count 2 2006.257.19:01:02.24#ibcon#read 6, iclass 26, count 2 2006.257.19:01:02.24#ibcon#end of sib2, iclass 26, count 2 2006.257.19:01:02.24#ibcon#*mode == 0, iclass 26, count 2 2006.257.19:01:02.24#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.19:01:02.24#ibcon#[27=AT01-04\r\n] 2006.257.19:01:02.24#ibcon#*before write, iclass 26, count 2 2006.257.19:01:02.24#ibcon#enter sib2, iclass 26, count 2 2006.257.19:01:02.24#ibcon#flushed, iclass 26, count 2 2006.257.19:01:02.24#ibcon#about to write, iclass 26, count 2 2006.257.19:01:02.24#ibcon#wrote, iclass 26, count 2 2006.257.19:01:02.24#ibcon#about to read 3, iclass 26, count 2 2006.257.19:01:02.27#ibcon#read 3, iclass 26, count 2 2006.257.19:01:02.27#ibcon#about to read 4, iclass 26, count 2 2006.257.19:01:02.27#ibcon#read 4, iclass 26, count 2 2006.257.19:01:02.27#ibcon#about to read 5, iclass 26, count 2 2006.257.19:01:02.27#ibcon#read 5, iclass 26, count 2 2006.257.19:01:02.27#ibcon#about to read 6, iclass 26, count 2 2006.257.19:01:02.27#ibcon#read 6, iclass 26, count 2 2006.257.19:01:02.27#ibcon#end of sib2, iclass 26, count 2 2006.257.19:01:02.27#ibcon#*after write, iclass 26, count 2 2006.257.19:01:02.27#ibcon#*before return 0, iclass 26, count 2 2006.257.19:01:02.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:01:02.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:01:02.27#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.19:01:02.27#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:02.27#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:01:02.39#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:01:02.39#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:01:02.39#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:01:02.39#ibcon#first serial, iclass 26, count 0 2006.257.19:01:02.39#ibcon#enter sib2, iclass 26, count 0 2006.257.19:01:02.39#ibcon#flushed, iclass 26, count 0 2006.257.19:01:02.39#ibcon#about to write, iclass 26, count 0 2006.257.19:01:02.39#ibcon#wrote, iclass 26, count 0 2006.257.19:01:02.39#ibcon#about to read 3, iclass 26, count 0 2006.257.19:01:02.41#ibcon#read 3, iclass 26, count 0 2006.257.19:01:02.41#ibcon#about to read 4, iclass 26, count 0 2006.257.19:01:02.41#ibcon#read 4, iclass 26, count 0 2006.257.19:01:02.41#ibcon#about to read 5, iclass 26, count 0 2006.257.19:01:02.41#ibcon#read 5, iclass 26, count 0 2006.257.19:01:02.41#ibcon#about to read 6, iclass 26, count 0 2006.257.19:01:02.41#ibcon#read 6, iclass 26, count 0 2006.257.19:01:02.41#ibcon#end of sib2, iclass 26, count 0 2006.257.19:01:02.41#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:01:02.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:01:02.41#ibcon#[27=USB\r\n] 2006.257.19:01:02.41#ibcon#*before write, iclass 26, count 0 2006.257.19:01:02.41#ibcon#enter sib2, iclass 26, count 0 2006.257.19:01:02.41#ibcon#flushed, iclass 26, count 0 2006.257.19:01:02.41#ibcon#about to write, iclass 26, count 0 2006.257.19:01:02.41#ibcon#wrote, iclass 26, count 0 2006.257.19:01:02.41#ibcon#about to read 3, iclass 26, count 0 2006.257.19:01:02.44#ibcon#read 3, iclass 26, count 0 2006.257.19:01:02.44#ibcon#about to read 4, iclass 26, count 0 2006.257.19:01:02.44#ibcon#read 4, iclass 26, count 0 2006.257.19:01:02.44#ibcon#about to read 5, iclass 26, count 0 2006.257.19:01:02.44#ibcon#read 5, iclass 26, count 0 2006.257.19:01:02.44#ibcon#about to read 6, iclass 26, count 0 2006.257.19:01:02.44#ibcon#read 6, iclass 26, count 0 2006.257.19:01:02.44#ibcon#end of sib2, iclass 26, count 0 2006.257.19:01:02.44#ibcon#*after write, iclass 26, count 0 2006.257.19:01:02.44#ibcon#*before return 0, iclass 26, count 0 2006.257.19:01:02.44#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:01:02.44#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:01:02.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:01:02.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:01:02.44$vck44/vblo=2,634.99 2006.257.19:01:02.44#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.19:01:02.44#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.19:01:02.44#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:02.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:01:02.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:01:02.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:01:02.44#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:01:02.44#ibcon#first serial, iclass 28, count 0 2006.257.19:01:02.44#ibcon#enter sib2, iclass 28, count 0 2006.257.19:01:02.44#ibcon#flushed, iclass 28, count 0 2006.257.19:01:02.44#ibcon#about to write, iclass 28, count 0 2006.257.19:01:02.44#ibcon#wrote, iclass 28, count 0 2006.257.19:01:02.44#ibcon#about to read 3, iclass 28, count 0 2006.257.19:01:02.46#ibcon#read 3, iclass 28, count 0 2006.257.19:01:02.46#ibcon#about to read 4, iclass 28, count 0 2006.257.19:01:02.46#ibcon#read 4, iclass 28, count 0 2006.257.19:01:02.46#ibcon#about to read 5, iclass 28, count 0 2006.257.19:01:02.46#ibcon#read 5, iclass 28, count 0 2006.257.19:01:02.46#ibcon#about to read 6, iclass 28, count 0 2006.257.19:01:02.46#ibcon#read 6, iclass 28, count 0 2006.257.19:01:02.46#ibcon#end of sib2, iclass 28, count 0 2006.257.19:01:02.46#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:01:02.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:01:02.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.19:01:02.46#ibcon#*before write, iclass 28, count 0 2006.257.19:01:02.46#ibcon#enter sib2, iclass 28, count 0 2006.257.19:01:02.46#ibcon#flushed, iclass 28, count 0 2006.257.19:01:02.46#ibcon#about to write, iclass 28, count 0 2006.257.19:01:02.46#ibcon#wrote, iclass 28, count 0 2006.257.19:01:02.46#ibcon#about to read 3, iclass 28, count 0 2006.257.19:01:02.50#ibcon#read 3, iclass 28, count 0 2006.257.19:01:02.50#ibcon#about to read 4, iclass 28, count 0 2006.257.19:01:02.50#ibcon#read 4, iclass 28, count 0 2006.257.19:01:02.50#ibcon#about to read 5, iclass 28, count 0 2006.257.19:01:02.50#ibcon#read 5, iclass 28, count 0 2006.257.19:01:02.50#ibcon#about to read 6, iclass 28, count 0 2006.257.19:01:02.50#ibcon#read 6, iclass 28, count 0 2006.257.19:01:02.50#ibcon#end of sib2, iclass 28, count 0 2006.257.19:01:02.50#ibcon#*after write, iclass 28, count 0 2006.257.19:01:02.50#ibcon#*before return 0, iclass 28, count 0 2006.257.19:01:02.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:01:02.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:01:02.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:01:02.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:01:02.50$vck44/vb=2,5 2006.257.19:01:02.50#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.19:01:02.50#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.19:01:02.50#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:02.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:01:02.53#abcon#<5=/14 1.4 3.4 17.39 961014.3\r\n> 2006.257.19:01:02.55#abcon#{5=INTERFACE CLEAR} 2006.257.19:01:02.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:01:02.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:01:02.56#ibcon#enter wrdev, iclass 31, count 2 2006.257.19:01:02.56#ibcon#first serial, iclass 31, count 2 2006.257.19:01:02.56#ibcon#enter sib2, iclass 31, count 2 2006.257.19:01:02.56#ibcon#flushed, iclass 31, count 2 2006.257.19:01:02.56#ibcon#about to write, iclass 31, count 2 2006.257.19:01:02.56#ibcon#wrote, iclass 31, count 2 2006.257.19:01:02.56#ibcon#about to read 3, iclass 31, count 2 2006.257.19:01:02.58#ibcon#read 3, iclass 31, count 2 2006.257.19:01:02.58#ibcon#about to read 4, iclass 31, count 2 2006.257.19:01:02.58#ibcon#read 4, iclass 31, count 2 2006.257.19:01:02.58#ibcon#about to read 5, iclass 31, count 2 2006.257.19:01:02.58#ibcon#read 5, iclass 31, count 2 2006.257.19:01:02.58#ibcon#about to read 6, iclass 31, count 2 2006.257.19:01:02.58#ibcon#read 6, iclass 31, count 2 2006.257.19:01:02.58#ibcon#end of sib2, iclass 31, count 2 2006.257.19:01:02.58#ibcon#*mode == 0, iclass 31, count 2 2006.257.19:01:02.58#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.19:01:02.58#ibcon#[27=AT02-05\r\n] 2006.257.19:01:02.58#ibcon#*before write, iclass 31, count 2 2006.257.19:01:02.58#ibcon#enter sib2, iclass 31, count 2 2006.257.19:01:02.58#ibcon#flushed, iclass 31, count 2 2006.257.19:01:02.58#ibcon#about to write, iclass 31, count 2 2006.257.19:01:02.58#ibcon#wrote, iclass 31, count 2 2006.257.19:01:02.58#ibcon#about to read 3, iclass 31, count 2 2006.257.19:01:02.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:01:02.61#ibcon#read 3, iclass 31, count 2 2006.257.19:01:02.61#ibcon#about to read 4, iclass 31, count 2 2006.257.19:01:02.61#ibcon#read 4, iclass 31, count 2 2006.257.19:01:02.61#ibcon#about to read 5, iclass 31, count 2 2006.257.19:01:02.61#ibcon#read 5, iclass 31, count 2 2006.257.19:01:02.61#ibcon#about to read 6, iclass 31, count 2 2006.257.19:01:02.61#ibcon#read 6, iclass 31, count 2 2006.257.19:01:02.61#ibcon#end of sib2, iclass 31, count 2 2006.257.19:01:02.61#ibcon#*after write, iclass 31, count 2 2006.257.19:01:02.61#ibcon#*before return 0, iclass 31, count 2 2006.257.19:01:02.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:01:02.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:01:02.61#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.19:01:02.61#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:02.61#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:01:02.73#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:01:02.73#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:01:02.73#ibcon#enter wrdev, iclass 31, count 0 2006.257.19:01:02.73#ibcon#first serial, iclass 31, count 0 2006.257.19:01:02.73#ibcon#enter sib2, iclass 31, count 0 2006.257.19:01:02.73#ibcon#flushed, iclass 31, count 0 2006.257.19:01:02.73#ibcon#about to write, iclass 31, count 0 2006.257.19:01:02.73#ibcon#wrote, iclass 31, count 0 2006.257.19:01:02.73#ibcon#about to read 3, iclass 31, count 0 2006.257.19:01:02.75#ibcon#read 3, iclass 31, count 0 2006.257.19:01:02.75#ibcon#about to read 4, iclass 31, count 0 2006.257.19:01:02.75#ibcon#read 4, iclass 31, count 0 2006.257.19:01:02.75#ibcon#about to read 5, iclass 31, count 0 2006.257.19:01:02.75#ibcon#read 5, iclass 31, count 0 2006.257.19:01:02.75#ibcon#about to read 6, iclass 31, count 0 2006.257.19:01:02.75#ibcon#read 6, iclass 31, count 0 2006.257.19:01:02.75#ibcon#end of sib2, iclass 31, count 0 2006.257.19:01:02.75#ibcon#*mode == 0, iclass 31, count 0 2006.257.19:01:02.75#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.19:01:02.75#ibcon#[27=USB\r\n] 2006.257.19:01:02.75#ibcon#*before write, iclass 31, count 0 2006.257.19:01:02.75#ibcon#enter sib2, iclass 31, count 0 2006.257.19:01:02.75#ibcon#flushed, iclass 31, count 0 2006.257.19:01:02.75#ibcon#about to write, iclass 31, count 0 2006.257.19:01:02.75#ibcon#wrote, iclass 31, count 0 2006.257.19:01:02.75#ibcon#about to read 3, iclass 31, count 0 2006.257.19:01:02.78#ibcon#read 3, iclass 31, count 0 2006.257.19:01:02.78#ibcon#about to read 4, iclass 31, count 0 2006.257.19:01:02.78#ibcon#read 4, iclass 31, count 0 2006.257.19:01:02.78#ibcon#about to read 5, iclass 31, count 0 2006.257.19:01:02.78#ibcon#read 5, iclass 31, count 0 2006.257.19:01:02.78#ibcon#about to read 6, iclass 31, count 0 2006.257.19:01:02.78#ibcon#read 6, iclass 31, count 0 2006.257.19:01:02.78#ibcon#end of sib2, iclass 31, count 0 2006.257.19:01:02.78#ibcon#*after write, iclass 31, count 0 2006.257.19:01:02.78#ibcon#*before return 0, iclass 31, count 0 2006.257.19:01:02.78#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:01:02.78#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:01:02.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.19:01:02.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.19:01:02.78$vck44/vblo=3,649.99 2006.257.19:01:02.78#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.19:01:02.78#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.19:01:02.78#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:02.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:02.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:02.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:02.78#ibcon#enter wrdev, iclass 36, count 0 2006.257.19:01:02.78#ibcon#first serial, iclass 36, count 0 2006.257.19:01:02.78#ibcon#enter sib2, iclass 36, count 0 2006.257.19:01:02.78#ibcon#flushed, iclass 36, count 0 2006.257.19:01:02.78#ibcon#about to write, iclass 36, count 0 2006.257.19:01:02.78#ibcon#wrote, iclass 36, count 0 2006.257.19:01:02.78#ibcon#about to read 3, iclass 36, count 0 2006.257.19:01:02.80#ibcon#read 3, iclass 36, count 0 2006.257.19:01:02.80#ibcon#about to read 4, iclass 36, count 0 2006.257.19:01:02.80#ibcon#read 4, iclass 36, count 0 2006.257.19:01:02.80#ibcon#about to read 5, iclass 36, count 0 2006.257.19:01:02.80#ibcon#read 5, iclass 36, count 0 2006.257.19:01:02.80#ibcon#about to read 6, iclass 36, count 0 2006.257.19:01:02.80#ibcon#read 6, iclass 36, count 0 2006.257.19:01:02.80#ibcon#end of sib2, iclass 36, count 0 2006.257.19:01:02.80#ibcon#*mode == 0, iclass 36, count 0 2006.257.19:01:02.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.19:01:02.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.19:01:02.80#ibcon#*before write, iclass 36, count 0 2006.257.19:01:02.80#ibcon#enter sib2, iclass 36, count 0 2006.257.19:01:02.80#ibcon#flushed, iclass 36, count 0 2006.257.19:01:02.80#ibcon#about to write, iclass 36, count 0 2006.257.19:01:02.80#ibcon#wrote, iclass 36, count 0 2006.257.19:01:02.80#ibcon#about to read 3, iclass 36, count 0 2006.257.19:01:02.84#ibcon#read 3, iclass 36, count 0 2006.257.19:01:02.84#ibcon#about to read 4, iclass 36, count 0 2006.257.19:01:02.84#ibcon#read 4, iclass 36, count 0 2006.257.19:01:02.84#ibcon#about to read 5, iclass 36, count 0 2006.257.19:01:02.84#ibcon#read 5, iclass 36, count 0 2006.257.19:01:02.84#ibcon#about to read 6, iclass 36, count 0 2006.257.19:01:02.84#ibcon#read 6, iclass 36, count 0 2006.257.19:01:02.84#ibcon#end of sib2, iclass 36, count 0 2006.257.19:01:02.84#ibcon#*after write, iclass 36, count 0 2006.257.19:01:02.84#ibcon#*before return 0, iclass 36, count 0 2006.257.19:01:02.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:02.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:01:02.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.19:01:02.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.19:01:02.84$vck44/vb=3,4 2006.257.19:01:02.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.19:01:02.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.19:01:02.84#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:02.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:02.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:02.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:02.90#ibcon#enter wrdev, iclass 38, count 2 2006.257.19:01:02.90#ibcon#first serial, iclass 38, count 2 2006.257.19:01:02.90#ibcon#enter sib2, iclass 38, count 2 2006.257.19:01:02.90#ibcon#flushed, iclass 38, count 2 2006.257.19:01:02.90#ibcon#about to write, iclass 38, count 2 2006.257.19:01:02.90#ibcon#wrote, iclass 38, count 2 2006.257.19:01:02.90#ibcon#about to read 3, iclass 38, count 2 2006.257.19:01:02.92#ibcon#read 3, iclass 38, count 2 2006.257.19:01:02.92#ibcon#about to read 4, iclass 38, count 2 2006.257.19:01:02.92#ibcon#read 4, iclass 38, count 2 2006.257.19:01:02.92#ibcon#about to read 5, iclass 38, count 2 2006.257.19:01:02.92#ibcon#read 5, iclass 38, count 2 2006.257.19:01:02.92#ibcon#about to read 6, iclass 38, count 2 2006.257.19:01:02.92#ibcon#read 6, iclass 38, count 2 2006.257.19:01:02.92#ibcon#end of sib2, iclass 38, count 2 2006.257.19:01:02.92#ibcon#*mode == 0, iclass 38, count 2 2006.257.19:01:02.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.19:01:02.92#ibcon#[27=AT03-04\r\n] 2006.257.19:01:02.92#ibcon#*before write, iclass 38, count 2 2006.257.19:01:02.92#ibcon#enter sib2, iclass 38, count 2 2006.257.19:01:02.92#ibcon#flushed, iclass 38, count 2 2006.257.19:01:02.92#ibcon#about to write, iclass 38, count 2 2006.257.19:01:02.92#ibcon#wrote, iclass 38, count 2 2006.257.19:01:02.92#ibcon#about to read 3, iclass 38, count 2 2006.257.19:01:02.95#ibcon#read 3, iclass 38, count 2 2006.257.19:01:02.95#ibcon#about to read 4, iclass 38, count 2 2006.257.19:01:02.95#ibcon#read 4, iclass 38, count 2 2006.257.19:01:02.95#ibcon#about to read 5, iclass 38, count 2 2006.257.19:01:02.95#ibcon#read 5, iclass 38, count 2 2006.257.19:01:02.95#ibcon#about to read 6, iclass 38, count 2 2006.257.19:01:02.95#ibcon#read 6, iclass 38, count 2 2006.257.19:01:02.95#ibcon#end of sib2, iclass 38, count 2 2006.257.19:01:02.95#ibcon#*after write, iclass 38, count 2 2006.257.19:01:02.95#ibcon#*before return 0, iclass 38, count 2 2006.257.19:01:02.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:02.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:01:02.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.19:01:02.95#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:02.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:03.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:03.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:03.07#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:01:03.07#ibcon#first serial, iclass 38, count 0 2006.257.19:01:03.07#ibcon#enter sib2, iclass 38, count 0 2006.257.19:01:03.07#ibcon#flushed, iclass 38, count 0 2006.257.19:01:03.07#ibcon#about to write, iclass 38, count 0 2006.257.19:01:03.07#ibcon#wrote, iclass 38, count 0 2006.257.19:01:03.07#ibcon#about to read 3, iclass 38, count 0 2006.257.19:01:03.09#ibcon#read 3, iclass 38, count 0 2006.257.19:01:03.09#ibcon#about to read 4, iclass 38, count 0 2006.257.19:01:03.09#ibcon#read 4, iclass 38, count 0 2006.257.19:01:03.09#ibcon#about to read 5, iclass 38, count 0 2006.257.19:01:03.09#ibcon#read 5, iclass 38, count 0 2006.257.19:01:03.09#ibcon#about to read 6, iclass 38, count 0 2006.257.19:01:03.09#ibcon#read 6, iclass 38, count 0 2006.257.19:01:03.09#ibcon#end of sib2, iclass 38, count 0 2006.257.19:01:03.09#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:01:03.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:01:03.09#ibcon#[27=USB\r\n] 2006.257.19:01:03.09#ibcon#*before write, iclass 38, count 0 2006.257.19:01:03.09#ibcon#enter sib2, iclass 38, count 0 2006.257.19:01:03.09#ibcon#flushed, iclass 38, count 0 2006.257.19:01:03.09#ibcon#about to write, iclass 38, count 0 2006.257.19:01:03.09#ibcon#wrote, iclass 38, count 0 2006.257.19:01:03.09#ibcon#about to read 3, iclass 38, count 0 2006.257.19:01:03.12#ibcon#read 3, iclass 38, count 0 2006.257.19:01:03.12#ibcon#about to read 4, iclass 38, count 0 2006.257.19:01:03.12#ibcon#read 4, iclass 38, count 0 2006.257.19:01:03.12#ibcon#about to read 5, iclass 38, count 0 2006.257.19:01:03.12#ibcon#read 5, iclass 38, count 0 2006.257.19:01:03.12#ibcon#about to read 6, iclass 38, count 0 2006.257.19:01:03.12#ibcon#read 6, iclass 38, count 0 2006.257.19:01:03.12#ibcon#end of sib2, iclass 38, count 0 2006.257.19:01:03.12#ibcon#*after write, iclass 38, count 0 2006.257.19:01:03.12#ibcon#*before return 0, iclass 38, count 0 2006.257.19:01:03.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:03.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:01:03.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:01:03.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:01:03.12$vck44/vblo=4,679.99 2006.257.19:01:03.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.19:01:03.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.19:01:03.12#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:03.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:03.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:03.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:03.12#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:01:03.12#ibcon#first serial, iclass 40, count 0 2006.257.19:01:03.12#ibcon#enter sib2, iclass 40, count 0 2006.257.19:01:03.12#ibcon#flushed, iclass 40, count 0 2006.257.19:01:03.12#ibcon#about to write, iclass 40, count 0 2006.257.19:01:03.12#ibcon#wrote, iclass 40, count 0 2006.257.19:01:03.12#ibcon#about to read 3, iclass 40, count 0 2006.257.19:01:03.14#ibcon#read 3, iclass 40, count 0 2006.257.19:01:03.14#ibcon#about to read 4, iclass 40, count 0 2006.257.19:01:03.14#ibcon#read 4, iclass 40, count 0 2006.257.19:01:03.14#ibcon#about to read 5, iclass 40, count 0 2006.257.19:01:03.14#ibcon#read 5, iclass 40, count 0 2006.257.19:01:03.14#ibcon#about to read 6, iclass 40, count 0 2006.257.19:01:03.14#ibcon#read 6, iclass 40, count 0 2006.257.19:01:03.14#ibcon#end of sib2, iclass 40, count 0 2006.257.19:01:03.14#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:01:03.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:01:03.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.19:01:03.14#ibcon#*before write, iclass 40, count 0 2006.257.19:01:03.14#ibcon#enter sib2, iclass 40, count 0 2006.257.19:01:03.14#ibcon#flushed, iclass 40, count 0 2006.257.19:01:03.14#ibcon#about to write, iclass 40, count 0 2006.257.19:01:03.14#ibcon#wrote, iclass 40, count 0 2006.257.19:01:03.14#ibcon#about to read 3, iclass 40, count 0 2006.257.19:01:03.18#ibcon#read 3, iclass 40, count 0 2006.257.19:01:03.18#ibcon#about to read 4, iclass 40, count 0 2006.257.19:01:03.18#ibcon#read 4, iclass 40, count 0 2006.257.19:01:03.18#ibcon#about to read 5, iclass 40, count 0 2006.257.19:01:03.18#ibcon#read 5, iclass 40, count 0 2006.257.19:01:03.18#ibcon#about to read 6, iclass 40, count 0 2006.257.19:01:03.18#ibcon#read 6, iclass 40, count 0 2006.257.19:01:03.18#ibcon#end of sib2, iclass 40, count 0 2006.257.19:01:03.18#ibcon#*after write, iclass 40, count 0 2006.257.19:01:03.18#ibcon#*before return 0, iclass 40, count 0 2006.257.19:01:03.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:03.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:01:03.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:01:03.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:01:03.18$vck44/vb=4,5 2006.257.19:01:03.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.19:01:03.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.19:01:03.18#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:03.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:03.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:03.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:03.24#ibcon#enter wrdev, iclass 4, count 2 2006.257.19:01:03.24#ibcon#first serial, iclass 4, count 2 2006.257.19:01:03.24#ibcon#enter sib2, iclass 4, count 2 2006.257.19:01:03.24#ibcon#flushed, iclass 4, count 2 2006.257.19:01:03.24#ibcon#about to write, iclass 4, count 2 2006.257.19:01:03.24#ibcon#wrote, iclass 4, count 2 2006.257.19:01:03.24#ibcon#about to read 3, iclass 4, count 2 2006.257.19:01:03.26#ibcon#read 3, iclass 4, count 2 2006.257.19:01:03.26#ibcon#about to read 4, iclass 4, count 2 2006.257.19:01:03.26#ibcon#read 4, iclass 4, count 2 2006.257.19:01:03.26#ibcon#about to read 5, iclass 4, count 2 2006.257.19:01:03.26#ibcon#read 5, iclass 4, count 2 2006.257.19:01:03.26#ibcon#about to read 6, iclass 4, count 2 2006.257.19:01:03.26#ibcon#read 6, iclass 4, count 2 2006.257.19:01:03.26#ibcon#end of sib2, iclass 4, count 2 2006.257.19:01:03.26#ibcon#*mode == 0, iclass 4, count 2 2006.257.19:01:03.26#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.19:01:03.26#ibcon#[27=AT04-05\r\n] 2006.257.19:01:03.26#ibcon#*before write, iclass 4, count 2 2006.257.19:01:03.26#ibcon#enter sib2, iclass 4, count 2 2006.257.19:01:03.26#ibcon#flushed, iclass 4, count 2 2006.257.19:01:03.26#ibcon#about to write, iclass 4, count 2 2006.257.19:01:03.26#ibcon#wrote, iclass 4, count 2 2006.257.19:01:03.26#ibcon#about to read 3, iclass 4, count 2 2006.257.19:01:03.29#ibcon#read 3, iclass 4, count 2 2006.257.19:01:03.29#ibcon#about to read 4, iclass 4, count 2 2006.257.19:01:03.29#ibcon#read 4, iclass 4, count 2 2006.257.19:01:03.29#ibcon#about to read 5, iclass 4, count 2 2006.257.19:01:03.29#ibcon#read 5, iclass 4, count 2 2006.257.19:01:03.29#ibcon#about to read 6, iclass 4, count 2 2006.257.19:01:03.29#ibcon#read 6, iclass 4, count 2 2006.257.19:01:03.29#ibcon#end of sib2, iclass 4, count 2 2006.257.19:01:03.29#ibcon#*after write, iclass 4, count 2 2006.257.19:01:03.29#ibcon#*before return 0, iclass 4, count 2 2006.257.19:01:03.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:03.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:01:03.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.19:01:03.29#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:03.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:03.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:03.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:03.41#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:01:03.41#ibcon#first serial, iclass 4, count 0 2006.257.19:01:03.41#ibcon#enter sib2, iclass 4, count 0 2006.257.19:01:03.41#ibcon#flushed, iclass 4, count 0 2006.257.19:01:03.41#ibcon#about to write, iclass 4, count 0 2006.257.19:01:03.41#ibcon#wrote, iclass 4, count 0 2006.257.19:01:03.41#ibcon#about to read 3, iclass 4, count 0 2006.257.19:01:03.43#ibcon#read 3, iclass 4, count 0 2006.257.19:01:03.43#ibcon#about to read 4, iclass 4, count 0 2006.257.19:01:03.43#ibcon#read 4, iclass 4, count 0 2006.257.19:01:03.43#ibcon#about to read 5, iclass 4, count 0 2006.257.19:01:03.43#ibcon#read 5, iclass 4, count 0 2006.257.19:01:03.43#ibcon#about to read 6, iclass 4, count 0 2006.257.19:01:03.43#ibcon#read 6, iclass 4, count 0 2006.257.19:01:03.43#ibcon#end of sib2, iclass 4, count 0 2006.257.19:01:03.43#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:01:03.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:01:03.43#ibcon#[27=USB\r\n] 2006.257.19:01:03.43#ibcon#*before write, iclass 4, count 0 2006.257.19:01:03.43#ibcon#enter sib2, iclass 4, count 0 2006.257.19:01:03.43#ibcon#flushed, iclass 4, count 0 2006.257.19:01:03.43#ibcon#about to write, iclass 4, count 0 2006.257.19:01:03.43#ibcon#wrote, iclass 4, count 0 2006.257.19:01:03.43#ibcon#about to read 3, iclass 4, count 0 2006.257.19:01:03.46#ibcon#read 3, iclass 4, count 0 2006.257.19:01:03.46#ibcon#about to read 4, iclass 4, count 0 2006.257.19:01:03.46#ibcon#read 4, iclass 4, count 0 2006.257.19:01:03.46#ibcon#about to read 5, iclass 4, count 0 2006.257.19:01:03.46#ibcon#read 5, iclass 4, count 0 2006.257.19:01:03.46#ibcon#about to read 6, iclass 4, count 0 2006.257.19:01:03.46#ibcon#read 6, iclass 4, count 0 2006.257.19:01:03.46#ibcon#end of sib2, iclass 4, count 0 2006.257.19:01:03.46#ibcon#*after write, iclass 4, count 0 2006.257.19:01:03.46#ibcon#*before return 0, iclass 4, count 0 2006.257.19:01:03.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:03.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:01:03.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:01:03.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:01:03.46$vck44/vblo=5,709.99 2006.257.19:01:03.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.19:01:03.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.19:01:03.46#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:03.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:03.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:03.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:03.46#ibcon#enter wrdev, iclass 6, count 0 2006.257.19:01:03.46#ibcon#first serial, iclass 6, count 0 2006.257.19:01:03.46#ibcon#enter sib2, iclass 6, count 0 2006.257.19:01:03.46#ibcon#flushed, iclass 6, count 0 2006.257.19:01:03.46#ibcon#about to write, iclass 6, count 0 2006.257.19:01:03.46#ibcon#wrote, iclass 6, count 0 2006.257.19:01:03.46#ibcon#about to read 3, iclass 6, count 0 2006.257.19:01:03.48#ibcon#read 3, iclass 6, count 0 2006.257.19:01:03.48#ibcon#about to read 4, iclass 6, count 0 2006.257.19:01:03.48#ibcon#read 4, iclass 6, count 0 2006.257.19:01:03.48#ibcon#about to read 5, iclass 6, count 0 2006.257.19:01:03.48#ibcon#read 5, iclass 6, count 0 2006.257.19:01:03.48#ibcon#about to read 6, iclass 6, count 0 2006.257.19:01:03.48#ibcon#read 6, iclass 6, count 0 2006.257.19:01:03.48#ibcon#end of sib2, iclass 6, count 0 2006.257.19:01:03.48#ibcon#*mode == 0, iclass 6, count 0 2006.257.19:01:03.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.19:01:03.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.19:01:03.48#ibcon#*before write, iclass 6, count 0 2006.257.19:01:03.48#ibcon#enter sib2, iclass 6, count 0 2006.257.19:01:03.48#ibcon#flushed, iclass 6, count 0 2006.257.19:01:03.48#ibcon#about to write, iclass 6, count 0 2006.257.19:01:03.48#ibcon#wrote, iclass 6, count 0 2006.257.19:01:03.48#ibcon#about to read 3, iclass 6, count 0 2006.257.19:01:03.52#ibcon#read 3, iclass 6, count 0 2006.257.19:01:03.52#ibcon#about to read 4, iclass 6, count 0 2006.257.19:01:03.52#ibcon#read 4, iclass 6, count 0 2006.257.19:01:03.52#ibcon#about to read 5, iclass 6, count 0 2006.257.19:01:03.52#ibcon#read 5, iclass 6, count 0 2006.257.19:01:03.52#ibcon#about to read 6, iclass 6, count 0 2006.257.19:01:03.52#ibcon#read 6, iclass 6, count 0 2006.257.19:01:03.52#ibcon#end of sib2, iclass 6, count 0 2006.257.19:01:03.52#ibcon#*after write, iclass 6, count 0 2006.257.19:01:03.52#ibcon#*before return 0, iclass 6, count 0 2006.257.19:01:03.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:03.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:01:03.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.19:01:03.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.19:01:03.52$vck44/vb=5,4 2006.257.19:01:03.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.19:01:03.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.19:01:03.52#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:03.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:03.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:03.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:03.58#ibcon#enter wrdev, iclass 10, count 2 2006.257.19:01:03.58#ibcon#first serial, iclass 10, count 2 2006.257.19:01:03.58#ibcon#enter sib2, iclass 10, count 2 2006.257.19:01:03.58#ibcon#flushed, iclass 10, count 2 2006.257.19:01:03.58#ibcon#about to write, iclass 10, count 2 2006.257.19:01:03.58#ibcon#wrote, iclass 10, count 2 2006.257.19:01:03.58#ibcon#about to read 3, iclass 10, count 2 2006.257.19:01:03.60#ibcon#read 3, iclass 10, count 2 2006.257.19:01:03.60#ibcon#about to read 4, iclass 10, count 2 2006.257.19:01:03.60#ibcon#read 4, iclass 10, count 2 2006.257.19:01:03.60#ibcon#about to read 5, iclass 10, count 2 2006.257.19:01:03.60#ibcon#read 5, iclass 10, count 2 2006.257.19:01:03.60#ibcon#about to read 6, iclass 10, count 2 2006.257.19:01:03.60#ibcon#read 6, iclass 10, count 2 2006.257.19:01:03.60#ibcon#end of sib2, iclass 10, count 2 2006.257.19:01:03.60#ibcon#*mode == 0, iclass 10, count 2 2006.257.19:01:03.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.19:01:03.60#ibcon#[27=AT05-04\r\n] 2006.257.19:01:03.60#ibcon#*before write, iclass 10, count 2 2006.257.19:01:03.60#ibcon#enter sib2, iclass 10, count 2 2006.257.19:01:03.60#ibcon#flushed, iclass 10, count 2 2006.257.19:01:03.60#ibcon#about to write, iclass 10, count 2 2006.257.19:01:03.60#ibcon#wrote, iclass 10, count 2 2006.257.19:01:03.60#ibcon#about to read 3, iclass 10, count 2 2006.257.19:01:03.63#ibcon#read 3, iclass 10, count 2 2006.257.19:01:03.63#ibcon#about to read 4, iclass 10, count 2 2006.257.19:01:03.63#ibcon#read 4, iclass 10, count 2 2006.257.19:01:03.63#ibcon#about to read 5, iclass 10, count 2 2006.257.19:01:03.63#ibcon#read 5, iclass 10, count 2 2006.257.19:01:03.63#ibcon#about to read 6, iclass 10, count 2 2006.257.19:01:03.63#ibcon#read 6, iclass 10, count 2 2006.257.19:01:03.63#ibcon#end of sib2, iclass 10, count 2 2006.257.19:01:03.63#ibcon#*after write, iclass 10, count 2 2006.257.19:01:03.63#ibcon#*before return 0, iclass 10, count 2 2006.257.19:01:03.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:03.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:01:03.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.19:01:03.63#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:03.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:03.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:03.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:03.75#ibcon#enter wrdev, iclass 10, count 0 2006.257.19:01:03.75#ibcon#first serial, iclass 10, count 0 2006.257.19:01:03.75#ibcon#enter sib2, iclass 10, count 0 2006.257.19:01:03.75#ibcon#flushed, iclass 10, count 0 2006.257.19:01:03.75#ibcon#about to write, iclass 10, count 0 2006.257.19:01:03.75#ibcon#wrote, iclass 10, count 0 2006.257.19:01:03.75#ibcon#about to read 3, iclass 10, count 0 2006.257.19:01:03.77#ibcon#read 3, iclass 10, count 0 2006.257.19:01:03.77#ibcon#about to read 4, iclass 10, count 0 2006.257.19:01:03.77#ibcon#read 4, iclass 10, count 0 2006.257.19:01:03.77#ibcon#about to read 5, iclass 10, count 0 2006.257.19:01:03.77#ibcon#read 5, iclass 10, count 0 2006.257.19:01:03.77#ibcon#about to read 6, iclass 10, count 0 2006.257.19:01:03.77#ibcon#read 6, iclass 10, count 0 2006.257.19:01:03.77#ibcon#end of sib2, iclass 10, count 0 2006.257.19:01:03.77#ibcon#*mode == 0, iclass 10, count 0 2006.257.19:01:03.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.19:01:03.77#ibcon#[27=USB\r\n] 2006.257.19:01:03.77#ibcon#*before write, iclass 10, count 0 2006.257.19:01:03.77#ibcon#enter sib2, iclass 10, count 0 2006.257.19:01:03.77#ibcon#flushed, iclass 10, count 0 2006.257.19:01:03.77#ibcon#about to write, iclass 10, count 0 2006.257.19:01:03.77#ibcon#wrote, iclass 10, count 0 2006.257.19:01:03.77#ibcon#about to read 3, iclass 10, count 0 2006.257.19:01:03.80#ibcon#read 3, iclass 10, count 0 2006.257.19:01:03.80#ibcon#about to read 4, iclass 10, count 0 2006.257.19:01:03.80#ibcon#read 4, iclass 10, count 0 2006.257.19:01:03.80#ibcon#about to read 5, iclass 10, count 0 2006.257.19:01:03.80#ibcon#read 5, iclass 10, count 0 2006.257.19:01:03.80#ibcon#about to read 6, iclass 10, count 0 2006.257.19:01:03.80#ibcon#read 6, iclass 10, count 0 2006.257.19:01:03.80#ibcon#end of sib2, iclass 10, count 0 2006.257.19:01:03.80#ibcon#*after write, iclass 10, count 0 2006.257.19:01:03.80#ibcon#*before return 0, iclass 10, count 0 2006.257.19:01:03.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:03.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:01:03.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.19:01:03.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.19:01:03.80$vck44/vblo=6,719.99 2006.257.19:01:03.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.19:01:03.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.19:01:03.80#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:03.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:03.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:03.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:03.80#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:01:03.80#ibcon#first serial, iclass 12, count 0 2006.257.19:01:03.80#ibcon#enter sib2, iclass 12, count 0 2006.257.19:01:03.80#ibcon#flushed, iclass 12, count 0 2006.257.19:01:03.80#ibcon#about to write, iclass 12, count 0 2006.257.19:01:03.80#ibcon#wrote, iclass 12, count 0 2006.257.19:01:03.80#ibcon#about to read 3, iclass 12, count 0 2006.257.19:01:03.82#ibcon#read 3, iclass 12, count 0 2006.257.19:01:03.82#ibcon#about to read 4, iclass 12, count 0 2006.257.19:01:03.82#ibcon#read 4, iclass 12, count 0 2006.257.19:01:03.82#ibcon#about to read 5, iclass 12, count 0 2006.257.19:01:03.82#ibcon#read 5, iclass 12, count 0 2006.257.19:01:03.82#ibcon#about to read 6, iclass 12, count 0 2006.257.19:01:03.82#ibcon#read 6, iclass 12, count 0 2006.257.19:01:03.82#ibcon#end of sib2, iclass 12, count 0 2006.257.19:01:03.82#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:01:03.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:01:03.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.19:01:03.82#ibcon#*before write, iclass 12, count 0 2006.257.19:01:03.82#ibcon#enter sib2, iclass 12, count 0 2006.257.19:01:03.82#ibcon#flushed, iclass 12, count 0 2006.257.19:01:03.82#ibcon#about to write, iclass 12, count 0 2006.257.19:01:03.82#ibcon#wrote, iclass 12, count 0 2006.257.19:01:03.82#ibcon#about to read 3, iclass 12, count 0 2006.257.19:01:03.86#ibcon#read 3, iclass 12, count 0 2006.257.19:01:03.86#ibcon#about to read 4, iclass 12, count 0 2006.257.19:01:03.86#ibcon#read 4, iclass 12, count 0 2006.257.19:01:03.86#ibcon#about to read 5, iclass 12, count 0 2006.257.19:01:03.86#ibcon#read 5, iclass 12, count 0 2006.257.19:01:03.86#ibcon#about to read 6, iclass 12, count 0 2006.257.19:01:03.86#ibcon#read 6, iclass 12, count 0 2006.257.19:01:03.86#ibcon#end of sib2, iclass 12, count 0 2006.257.19:01:03.86#ibcon#*after write, iclass 12, count 0 2006.257.19:01:03.86#ibcon#*before return 0, iclass 12, count 0 2006.257.19:01:03.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:03.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:01:03.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:01:03.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:01:03.86$vck44/vb=6,4 2006.257.19:01:03.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.19:01:03.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.19:01:03.86#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:03.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:03.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:03.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:03.92#ibcon#enter wrdev, iclass 14, count 2 2006.257.19:01:03.92#ibcon#first serial, iclass 14, count 2 2006.257.19:01:03.92#ibcon#enter sib2, iclass 14, count 2 2006.257.19:01:03.92#ibcon#flushed, iclass 14, count 2 2006.257.19:01:03.92#ibcon#about to write, iclass 14, count 2 2006.257.19:01:03.92#ibcon#wrote, iclass 14, count 2 2006.257.19:01:03.92#ibcon#about to read 3, iclass 14, count 2 2006.257.19:01:03.94#ibcon#read 3, iclass 14, count 2 2006.257.19:01:03.94#ibcon#about to read 4, iclass 14, count 2 2006.257.19:01:03.94#ibcon#read 4, iclass 14, count 2 2006.257.19:01:03.94#ibcon#about to read 5, iclass 14, count 2 2006.257.19:01:03.94#ibcon#read 5, iclass 14, count 2 2006.257.19:01:03.94#ibcon#about to read 6, iclass 14, count 2 2006.257.19:01:03.94#ibcon#read 6, iclass 14, count 2 2006.257.19:01:03.94#ibcon#end of sib2, iclass 14, count 2 2006.257.19:01:03.94#ibcon#*mode == 0, iclass 14, count 2 2006.257.19:01:03.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.19:01:03.94#ibcon#[27=AT06-04\r\n] 2006.257.19:01:03.94#ibcon#*before write, iclass 14, count 2 2006.257.19:01:03.94#ibcon#enter sib2, iclass 14, count 2 2006.257.19:01:03.94#ibcon#flushed, iclass 14, count 2 2006.257.19:01:03.94#ibcon#about to write, iclass 14, count 2 2006.257.19:01:03.94#ibcon#wrote, iclass 14, count 2 2006.257.19:01:03.94#ibcon#about to read 3, iclass 14, count 2 2006.257.19:01:03.97#ibcon#read 3, iclass 14, count 2 2006.257.19:01:03.97#ibcon#about to read 4, iclass 14, count 2 2006.257.19:01:03.97#ibcon#read 4, iclass 14, count 2 2006.257.19:01:03.97#ibcon#about to read 5, iclass 14, count 2 2006.257.19:01:03.97#ibcon#read 5, iclass 14, count 2 2006.257.19:01:03.97#ibcon#about to read 6, iclass 14, count 2 2006.257.19:01:03.97#ibcon#read 6, iclass 14, count 2 2006.257.19:01:03.97#ibcon#end of sib2, iclass 14, count 2 2006.257.19:01:03.97#ibcon#*after write, iclass 14, count 2 2006.257.19:01:03.97#ibcon#*before return 0, iclass 14, count 2 2006.257.19:01:03.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:03.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:01:03.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.19:01:03.97#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:03.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:04.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:04.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:04.09#ibcon#enter wrdev, iclass 14, count 0 2006.257.19:01:04.09#ibcon#first serial, iclass 14, count 0 2006.257.19:01:04.09#ibcon#enter sib2, iclass 14, count 0 2006.257.19:01:04.09#ibcon#flushed, iclass 14, count 0 2006.257.19:01:04.09#ibcon#about to write, iclass 14, count 0 2006.257.19:01:04.09#ibcon#wrote, iclass 14, count 0 2006.257.19:01:04.09#ibcon#about to read 3, iclass 14, count 0 2006.257.19:01:04.11#ibcon#read 3, iclass 14, count 0 2006.257.19:01:04.11#ibcon#about to read 4, iclass 14, count 0 2006.257.19:01:04.11#ibcon#read 4, iclass 14, count 0 2006.257.19:01:04.11#ibcon#about to read 5, iclass 14, count 0 2006.257.19:01:04.11#ibcon#read 5, iclass 14, count 0 2006.257.19:01:04.11#ibcon#about to read 6, iclass 14, count 0 2006.257.19:01:04.11#ibcon#read 6, iclass 14, count 0 2006.257.19:01:04.11#ibcon#end of sib2, iclass 14, count 0 2006.257.19:01:04.11#ibcon#*mode == 0, iclass 14, count 0 2006.257.19:01:04.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.19:01:04.11#ibcon#[27=USB\r\n] 2006.257.19:01:04.11#ibcon#*before write, iclass 14, count 0 2006.257.19:01:04.11#ibcon#enter sib2, iclass 14, count 0 2006.257.19:01:04.11#ibcon#flushed, iclass 14, count 0 2006.257.19:01:04.11#ibcon#about to write, iclass 14, count 0 2006.257.19:01:04.11#ibcon#wrote, iclass 14, count 0 2006.257.19:01:04.11#ibcon#about to read 3, iclass 14, count 0 2006.257.19:01:04.14#ibcon#read 3, iclass 14, count 0 2006.257.19:01:04.14#ibcon#about to read 4, iclass 14, count 0 2006.257.19:01:04.14#ibcon#read 4, iclass 14, count 0 2006.257.19:01:04.14#ibcon#about to read 5, iclass 14, count 0 2006.257.19:01:04.14#ibcon#read 5, iclass 14, count 0 2006.257.19:01:04.14#ibcon#about to read 6, iclass 14, count 0 2006.257.19:01:04.14#ibcon#read 6, iclass 14, count 0 2006.257.19:01:04.14#ibcon#end of sib2, iclass 14, count 0 2006.257.19:01:04.14#ibcon#*after write, iclass 14, count 0 2006.257.19:01:04.14#ibcon#*before return 0, iclass 14, count 0 2006.257.19:01:04.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:04.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:01:04.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.19:01:04.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.19:01:04.14$vck44/vblo=7,734.99 2006.257.19:01:04.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.19:01:04.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.19:01:04.14#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:04.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:04.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:04.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:04.14#ibcon#enter wrdev, iclass 16, count 0 2006.257.19:01:04.14#ibcon#first serial, iclass 16, count 0 2006.257.19:01:04.14#ibcon#enter sib2, iclass 16, count 0 2006.257.19:01:04.14#ibcon#flushed, iclass 16, count 0 2006.257.19:01:04.14#ibcon#about to write, iclass 16, count 0 2006.257.19:01:04.14#ibcon#wrote, iclass 16, count 0 2006.257.19:01:04.14#ibcon#about to read 3, iclass 16, count 0 2006.257.19:01:04.16#ibcon#read 3, iclass 16, count 0 2006.257.19:01:04.16#ibcon#about to read 4, iclass 16, count 0 2006.257.19:01:04.16#ibcon#read 4, iclass 16, count 0 2006.257.19:01:04.16#ibcon#about to read 5, iclass 16, count 0 2006.257.19:01:04.16#ibcon#read 5, iclass 16, count 0 2006.257.19:01:04.16#ibcon#about to read 6, iclass 16, count 0 2006.257.19:01:04.16#ibcon#read 6, iclass 16, count 0 2006.257.19:01:04.16#ibcon#end of sib2, iclass 16, count 0 2006.257.19:01:04.16#ibcon#*mode == 0, iclass 16, count 0 2006.257.19:01:04.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.19:01:04.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.19:01:04.16#ibcon#*before write, iclass 16, count 0 2006.257.19:01:04.16#ibcon#enter sib2, iclass 16, count 0 2006.257.19:01:04.16#ibcon#flushed, iclass 16, count 0 2006.257.19:01:04.16#ibcon#about to write, iclass 16, count 0 2006.257.19:01:04.16#ibcon#wrote, iclass 16, count 0 2006.257.19:01:04.16#ibcon#about to read 3, iclass 16, count 0 2006.257.19:01:04.20#ibcon#read 3, iclass 16, count 0 2006.257.19:01:04.20#ibcon#about to read 4, iclass 16, count 0 2006.257.19:01:04.20#ibcon#read 4, iclass 16, count 0 2006.257.19:01:04.20#ibcon#about to read 5, iclass 16, count 0 2006.257.19:01:04.20#ibcon#read 5, iclass 16, count 0 2006.257.19:01:04.20#ibcon#about to read 6, iclass 16, count 0 2006.257.19:01:04.20#ibcon#read 6, iclass 16, count 0 2006.257.19:01:04.20#ibcon#end of sib2, iclass 16, count 0 2006.257.19:01:04.20#ibcon#*after write, iclass 16, count 0 2006.257.19:01:04.20#ibcon#*before return 0, iclass 16, count 0 2006.257.19:01:04.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:04.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:01:04.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.19:01:04.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.19:01:04.20$vck44/vb=7,4 2006.257.19:01:04.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.19:01:04.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.19:01:04.20#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:04.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:04.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:04.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:04.26#ibcon#enter wrdev, iclass 18, count 2 2006.257.19:01:04.26#ibcon#first serial, iclass 18, count 2 2006.257.19:01:04.26#ibcon#enter sib2, iclass 18, count 2 2006.257.19:01:04.26#ibcon#flushed, iclass 18, count 2 2006.257.19:01:04.26#ibcon#about to write, iclass 18, count 2 2006.257.19:01:04.26#ibcon#wrote, iclass 18, count 2 2006.257.19:01:04.26#ibcon#about to read 3, iclass 18, count 2 2006.257.19:01:04.28#ibcon#read 3, iclass 18, count 2 2006.257.19:01:04.28#ibcon#about to read 4, iclass 18, count 2 2006.257.19:01:04.28#ibcon#read 4, iclass 18, count 2 2006.257.19:01:04.28#ibcon#about to read 5, iclass 18, count 2 2006.257.19:01:04.28#ibcon#read 5, iclass 18, count 2 2006.257.19:01:04.28#ibcon#about to read 6, iclass 18, count 2 2006.257.19:01:04.28#ibcon#read 6, iclass 18, count 2 2006.257.19:01:04.28#ibcon#end of sib2, iclass 18, count 2 2006.257.19:01:04.28#ibcon#*mode == 0, iclass 18, count 2 2006.257.19:01:04.28#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.19:01:04.28#ibcon#[27=AT07-04\r\n] 2006.257.19:01:04.28#ibcon#*before write, iclass 18, count 2 2006.257.19:01:04.28#ibcon#enter sib2, iclass 18, count 2 2006.257.19:01:04.28#ibcon#flushed, iclass 18, count 2 2006.257.19:01:04.28#ibcon#about to write, iclass 18, count 2 2006.257.19:01:04.28#ibcon#wrote, iclass 18, count 2 2006.257.19:01:04.28#ibcon#about to read 3, iclass 18, count 2 2006.257.19:01:04.31#ibcon#read 3, iclass 18, count 2 2006.257.19:01:04.31#ibcon#about to read 4, iclass 18, count 2 2006.257.19:01:04.31#ibcon#read 4, iclass 18, count 2 2006.257.19:01:04.31#ibcon#about to read 5, iclass 18, count 2 2006.257.19:01:04.31#ibcon#read 5, iclass 18, count 2 2006.257.19:01:04.31#ibcon#about to read 6, iclass 18, count 2 2006.257.19:01:04.31#ibcon#read 6, iclass 18, count 2 2006.257.19:01:04.31#ibcon#end of sib2, iclass 18, count 2 2006.257.19:01:04.31#ibcon#*after write, iclass 18, count 2 2006.257.19:01:04.31#ibcon#*before return 0, iclass 18, count 2 2006.257.19:01:04.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:04.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:01:04.31#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.19:01:04.31#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:04.31#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:04.43#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:04.43#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:04.43#ibcon#enter wrdev, iclass 18, count 0 2006.257.19:01:04.43#ibcon#first serial, iclass 18, count 0 2006.257.19:01:04.43#ibcon#enter sib2, iclass 18, count 0 2006.257.19:01:04.43#ibcon#flushed, iclass 18, count 0 2006.257.19:01:04.43#ibcon#about to write, iclass 18, count 0 2006.257.19:01:04.43#ibcon#wrote, iclass 18, count 0 2006.257.19:01:04.43#ibcon#about to read 3, iclass 18, count 0 2006.257.19:01:04.45#ibcon#read 3, iclass 18, count 0 2006.257.19:01:04.45#ibcon#about to read 4, iclass 18, count 0 2006.257.19:01:04.45#ibcon#read 4, iclass 18, count 0 2006.257.19:01:04.45#ibcon#about to read 5, iclass 18, count 0 2006.257.19:01:04.45#ibcon#read 5, iclass 18, count 0 2006.257.19:01:04.45#ibcon#about to read 6, iclass 18, count 0 2006.257.19:01:04.45#ibcon#read 6, iclass 18, count 0 2006.257.19:01:04.45#ibcon#end of sib2, iclass 18, count 0 2006.257.19:01:04.45#ibcon#*mode == 0, iclass 18, count 0 2006.257.19:01:04.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.19:01:04.45#ibcon#[27=USB\r\n] 2006.257.19:01:04.45#ibcon#*before write, iclass 18, count 0 2006.257.19:01:04.45#ibcon#enter sib2, iclass 18, count 0 2006.257.19:01:04.45#ibcon#flushed, iclass 18, count 0 2006.257.19:01:04.45#ibcon#about to write, iclass 18, count 0 2006.257.19:01:04.45#ibcon#wrote, iclass 18, count 0 2006.257.19:01:04.45#ibcon#about to read 3, iclass 18, count 0 2006.257.19:01:04.48#ibcon#read 3, iclass 18, count 0 2006.257.19:01:04.48#ibcon#about to read 4, iclass 18, count 0 2006.257.19:01:04.48#ibcon#read 4, iclass 18, count 0 2006.257.19:01:04.48#ibcon#about to read 5, iclass 18, count 0 2006.257.19:01:04.48#ibcon#read 5, iclass 18, count 0 2006.257.19:01:04.48#ibcon#about to read 6, iclass 18, count 0 2006.257.19:01:04.48#ibcon#read 6, iclass 18, count 0 2006.257.19:01:04.48#ibcon#end of sib2, iclass 18, count 0 2006.257.19:01:04.48#ibcon#*after write, iclass 18, count 0 2006.257.19:01:04.48#ibcon#*before return 0, iclass 18, count 0 2006.257.19:01:04.48#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:04.48#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:01:04.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.19:01:04.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.19:01:04.48$vck44/vblo=8,744.99 2006.257.19:01:04.48#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.19:01:04.48#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.19:01:04.48#ibcon#ireg 17 cls_cnt 0 2006.257.19:01:04.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:04.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:04.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:04.48#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:01:04.48#ibcon#first serial, iclass 20, count 0 2006.257.19:01:04.48#ibcon#enter sib2, iclass 20, count 0 2006.257.19:01:04.48#ibcon#flushed, iclass 20, count 0 2006.257.19:01:04.48#ibcon#about to write, iclass 20, count 0 2006.257.19:01:04.48#ibcon#wrote, iclass 20, count 0 2006.257.19:01:04.48#ibcon#about to read 3, iclass 20, count 0 2006.257.19:01:04.50#ibcon#read 3, iclass 20, count 0 2006.257.19:01:04.50#ibcon#about to read 4, iclass 20, count 0 2006.257.19:01:04.50#ibcon#read 4, iclass 20, count 0 2006.257.19:01:04.50#ibcon#about to read 5, iclass 20, count 0 2006.257.19:01:04.50#ibcon#read 5, iclass 20, count 0 2006.257.19:01:04.50#ibcon#about to read 6, iclass 20, count 0 2006.257.19:01:04.50#ibcon#read 6, iclass 20, count 0 2006.257.19:01:04.50#ibcon#end of sib2, iclass 20, count 0 2006.257.19:01:04.50#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:01:04.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:01:04.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.19:01:04.50#ibcon#*before write, iclass 20, count 0 2006.257.19:01:04.50#ibcon#enter sib2, iclass 20, count 0 2006.257.19:01:04.50#ibcon#flushed, iclass 20, count 0 2006.257.19:01:04.50#ibcon#about to write, iclass 20, count 0 2006.257.19:01:04.50#ibcon#wrote, iclass 20, count 0 2006.257.19:01:04.50#ibcon#about to read 3, iclass 20, count 0 2006.257.19:01:04.54#ibcon#read 3, iclass 20, count 0 2006.257.19:01:04.54#ibcon#about to read 4, iclass 20, count 0 2006.257.19:01:04.54#ibcon#read 4, iclass 20, count 0 2006.257.19:01:04.54#ibcon#about to read 5, iclass 20, count 0 2006.257.19:01:04.54#ibcon#read 5, iclass 20, count 0 2006.257.19:01:04.54#ibcon#about to read 6, iclass 20, count 0 2006.257.19:01:04.54#ibcon#read 6, iclass 20, count 0 2006.257.19:01:04.54#ibcon#end of sib2, iclass 20, count 0 2006.257.19:01:04.54#ibcon#*after write, iclass 20, count 0 2006.257.19:01:04.54#ibcon#*before return 0, iclass 20, count 0 2006.257.19:01:04.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:04.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:01:04.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:01:04.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:01:04.54$vck44/vb=8,4 2006.257.19:01:04.54#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.19:01:04.54#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.19:01:04.54#ibcon#ireg 11 cls_cnt 2 2006.257.19:01:04.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:04.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:04.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:04.60#ibcon#enter wrdev, iclass 22, count 2 2006.257.19:01:04.60#ibcon#first serial, iclass 22, count 2 2006.257.19:01:04.60#ibcon#enter sib2, iclass 22, count 2 2006.257.19:01:04.60#ibcon#flushed, iclass 22, count 2 2006.257.19:01:04.60#ibcon#about to write, iclass 22, count 2 2006.257.19:01:04.60#ibcon#wrote, iclass 22, count 2 2006.257.19:01:04.60#ibcon#about to read 3, iclass 22, count 2 2006.257.19:01:04.62#ibcon#read 3, iclass 22, count 2 2006.257.19:01:04.62#ibcon#about to read 4, iclass 22, count 2 2006.257.19:01:04.62#ibcon#read 4, iclass 22, count 2 2006.257.19:01:04.62#ibcon#about to read 5, iclass 22, count 2 2006.257.19:01:04.62#ibcon#read 5, iclass 22, count 2 2006.257.19:01:04.62#ibcon#about to read 6, iclass 22, count 2 2006.257.19:01:04.62#ibcon#read 6, iclass 22, count 2 2006.257.19:01:04.62#ibcon#end of sib2, iclass 22, count 2 2006.257.19:01:04.62#ibcon#*mode == 0, iclass 22, count 2 2006.257.19:01:04.62#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.19:01:04.62#ibcon#[27=AT08-04\r\n] 2006.257.19:01:04.62#ibcon#*before write, iclass 22, count 2 2006.257.19:01:04.62#ibcon#enter sib2, iclass 22, count 2 2006.257.19:01:04.62#ibcon#flushed, iclass 22, count 2 2006.257.19:01:04.62#ibcon#about to write, iclass 22, count 2 2006.257.19:01:04.62#ibcon#wrote, iclass 22, count 2 2006.257.19:01:04.62#ibcon#about to read 3, iclass 22, count 2 2006.257.19:01:04.65#ibcon#read 3, iclass 22, count 2 2006.257.19:01:04.65#ibcon#about to read 4, iclass 22, count 2 2006.257.19:01:04.65#ibcon#read 4, iclass 22, count 2 2006.257.19:01:04.65#ibcon#about to read 5, iclass 22, count 2 2006.257.19:01:04.65#ibcon#read 5, iclass 22, count 2 2006.257.19:01:04.65#ibcon#about to read 6, iclass 22, count 2 2006.257.19:01:04.65#ibcon#read 6, iclass 22, count 2 2006.257.19:01:04.65#ibcon#end of sib2, iclass 22, count 2 2006.257.19:01:04.65#ibcon#*after write, iclass 22, count 2 2006.257.19:01:04.65#ibcon#*before return 0, iclass 22, count 2 2006.257.19:01:04.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:04.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:01:04.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.19:01:04.65#ibcon#ireg 7 cls_cnt 0 2006.257.19:01:04.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:04.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:04.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:04.77#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:01:04.77#ibcon#first serial, iclass 22, count 0 2006.257.19:01:04.77#ibcon#enter sib2, iclass 22, count 0 2006.257.19:01:04.77#ibcon#flushed, iclass 22, count 0 2006.257.19:01:04.77#ibcon#about to write, iclass 22, count 0 2006.257.19:01:04.77#ibcon#wrote, iclass 22, count 0 2006.257.19:01:04.77#ibcon#about to read 3, iclass 22, count 0 2006.257.19:01:04.79#ibcon#read 3, iclass 22, count 0 2006.257.19:01:04.79#ibcon#about to read 4, iclass 22, count 0 2006.257.19:01:04.79#ibcon#read 4, iclass 22, count 0 2006.257.19:01:04.79#ibcon#about to read 5, iclass 22, count 0 2006.257.19:01:04.79#ibcon#read 5, iclass 22, count 0 2006.257.19:01:04.79#ibcon#about to read 6, iclass 22, count 0 2006.257.19:01:04.79#ibcon#read 6, iclass 22, count 0 2006.257.19:01:04.79#ibcon#end of sib2, iclass 22, count 0 2006.257.19:01:04.79#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:01:04.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:01:04.79#ibcon#[27=USB\r\n] 2006.257.19:01:04.79#ibcon#*before write, iclass 22, count 0 2006.257.19:01:04.79#ibcon#enter sib2, iclass 22, count 0 2006.257.19:01:04.79#ibcon#flushed, iclass 22, count 0 2006.257.19:01:04.79#ibcon#about to write, iclass 22, count 0 2006.257.19:01:04.79#ibcon#wrote, iclass 22, count 0 2006.257.19:01:04.79#ibcon#about to read 3, iclass 22, count 0 2006.257.19:01:04.82#ibcon#read 3, iclass 22, count 0 2006.257.19:01:04.82#ibcon#about to read 4, iclass 22, count 0 2006.257.19:01:04.82#ibcon#read 4, iclass 22, count 0 2006.257.19:01:04.82#ibcon#about to read 5, iclass 22, count 0 2006.257.19:01:04.82#ibcon#read 5, iclass 22, count 0 2006.257.19:01:04.82#ibcon#about to read 6, iclass 22, count 0 2006.257.19:01:04.82#ibcon#read 6, iclass 22, count 0 2006.257.19:01:04.82#ibcon#end of sib2, iclass 22, count 0 2006.257.19:01:04.82#ibcon#*after write, iclass 22, count 0 2006.257.19:01:04.82#ibcon#*before return 0, iclass 22, count 0 2006.257.19:01:04.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:04.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:01:04.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:01:04.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:01:04.82$vck44/vabw=wide 2006.257.19:01:04.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.19:01:04.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.19:01:04.82#ibcon#ireg 8 cls_cnt 0 2006.257.19:01:04.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:04.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:04.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:04.82#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:01:04.82#ibcon#first serial, iclass 24, count 0 2006.257.19:01:04.82#ibcon#enter sib2, iclass 24, count 0 2006.257.19:01:04.82#ibcon#flushed, iclass 24, count 0 2006.257.19:01:04.82#ibcon#about to write, iclass 24, count 0 2006.257.19:01:04.82#ibcon#wrote, iclass 24, count 0 2006.257.19:01:04.82#ibcon#about to read 3, iclass 24, count 0 2006.257.19:01:04.84#ibcon#read 3, iclass 24, count 0 2006.257.19:01:04.84#ibcon#about to read 4, iclass 24, count 0 2006.257.19:01:04.84#ibcon#read 4, iclass 24, count 0 2006.257.19:01:04.84#ibcon#about to read 5, iclass 24, count 0 2006.257.19:01:04.84#ibcon#read 5, iclass 24, count 0 2006.257.19:01:04.84#ibcon#about to read 6, iclass 24, count 0 2006.257.19:01:04.84#ibcon#read 6, iclass 24, count 0 2006.257.19:01:04.84#ibcon#end of sib2, iclass 24, count 0 2006.257.19:01:04.84#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:01:04.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:01:04.84#ibcon#[25=BW32\r\n] 2006.257.19:01:04.84#ibcon#*before write, iclass 24, count 0 2006.257.19:01:04.84#ibcon#enter sib2, iclass 24, count 0 2006.257.19:01:04.84#ibcon#flushed, iclass 24, count 0 2006.257.19:01:04.84#ibcon#about to write, iclass 24, count 0 2006.257.19:01:04.84#ibcon#wrote, iclass 24, count 0 2006.257.19:01:04.84#ibcon#about to read 3, iclass 24, count 0 2006.257.19:01:04.87#ibcon#read 3, iclass 24, count 0 2006.257.19:01:04.87#ibcon#about to read 4, iclass 24, count 0 2006.257.19:01:04.87#ibcon#read 4, iclass 24, count 0 2006.257.19:01:04.87#ibcon#about to read 5, iclass 24, count 0 2006.257.19:01:04.87#ibcon#read 5, iclass 24, count 0 2006.257.19:01:04.87#ibcon#about to read 6, iclass 24, count 0 2006.257.19:01:04.87#ibcon#read 6, iclass 24, count 0 2006.257.19:01:04.87#ibcon#end of sib2, iclass 24, count 0 2006.257.19:01:04.87#ibcon#*after write, iclass 24, count 0 2006.257.19:01:04.87#ibcon#*before return 0, iclass 24, count 0 2006.257.19:01:04.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:04.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:01:04.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:01:04.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:01:04.87$vck44/vbbw=wide 2006.257.19:01:04.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.19:01:04.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.19:01:04.87#ibcon#ireg 8 cls_cnt 0 2006.257.19:01:04.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:01:04.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:01:04.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:01:04.94#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:01:04.94#ibcon#first serial, iclass 26, count 0 2006.257.19:01:04.94#ibcon#enter sib2, iclass 26, count 0 2006.257.19:01:04.94#ibcon#flushed, iclass 26, count 0 2006.257.19:01:04.94#ibcon#about to write, iclass 26, count 0 2006.257.19:01:04.94#ibcon#wrote, iclass 26, count 0 2006.257.19:01:04.94#ibcon#about to read 3, iclass 26, count 0 2006.257.19:01:04.96#ibcon#read 3, iclass 26, count 0 2006.257.19:01:04.96#ibcon#about to read 4, iclass 26, count 0 2006.257.19:01:04.96#ibcon#read 4, iclass 26, count 0 2006.257.19:01:04.96#ibcon#about to read 5, iclass 26, count 0 2006.257.19:01:04.96#ibcon#read 5, iclass 26, count 0 2006.257.19:01:04.96#ibcon#about to read 6, iclass 26, count 0 2006.257.19:01:04.96#ibcon#read 6, iclass 26, count 0 2006.257.19:01:04.96#ibcon#end of sib2, iclass 26, count 0 2006.257.19:01:04.96#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:01:04.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:01:04.96#ibcon#[27=BW32\r\n] 2006.257.19:01:04.96#ibcon#*before write, iclass 26, count 0 2006.257.19:01:04.96#ibcon#enter sib2, iclass 26, count 0 2006.257.19:01:04.96#ibcon#flushed, iclass 26, count 0 2006.257.19:01:04.96#ibcon#about to write, iclass 26, count 0 2006.257.19:01:04.96#ibcon#wrote, iclass 26, count 0 2006.257.19:01:04.96#ibcon#about to read 3, iclass 26, count 0 2006.257.19:01:04.99#ibcon#read 3, iclass 26, count 0 2006.257.19:01:04.99#ibcon#about to read 4, iclass 26, count 0 2006.257.19:01:04.99#ibcon#read 4, iclass 26, count 0 2006.257.19:01:04.99#ibcon#about to read 5, iclass 26, count 0 2006.257.19:01:04.99#ibcon#read 5, iclass 26, count 0 2006.257.19:01:04.99#ibcon#about to read 6, iclass 26, count 0 2006.257.19:01:04.99#ibcon#read 6, iclass 26, count 0 2006.257.19:01:04.99#ibcon#end of sib2, iclass 26, count 0 2006.257.19:01:04.99#ibcon#*after write, iclass 26, count 0 2006.257.19:01:04.99#ibcon#*before return 0, iclass 26, count 0 2006.257.19:01:04.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:01:04.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:01:04.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:01:04.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:01:04.99$setupk4/ifdk4 2006.257.19:01:04.99$ifdk4/lo= 2006.257.19:01:04.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.19:01:04.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.19:01:04.99$ifdk4/patch= 2006.257.19:01:04.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.19:01:04.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.19:01:04.99$setupk4/!*+20s 2006.257.19:01:12.70#abcon#<5=/14 1.4 3.4 17.39 961014.3\r\n> 2006.257.19:01:12.72#abcon#{5=INTERFACE CLEAR} 2006.257.19:01:12.78#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:01:19.49$setupk4/"tpicd 2006.257.19:01:19.49$setupk4/echo=off 2006.257.19:01:19.49$setupk4/xlog=off 2006.257.19:01:19.49:!2006.257.19:10:25 2006.257.19:01:37.13#trakl#Source acquired 2006.257.19:01:38.13#flagr#flagr/antenna,acquired 2006.257.19:10:25.00:preob 2006.257.19:10:25.13/onsource/TRACKING 2006.257.19:10:25.13:!2006.257.19:10:35 2006.257.19:10:35.00:"tape 2006.257.19:10:35.00:"st=record 2006.257.19:10:35.00:data_valid=on 2006.257.19:10:35.00:midob 2006.257.19:10:35.13/onsource/TRACKING 2006.257.19:10:35.13/wx/17.44,1014.3,96 2006.257.19:10:35.20/cable/+6.4858E-03 2006.257.19:10:36.29/va/01,08,usb,yes,32,34 2006.257.19:10:36.29/va/02,07,usb,yes,35,35 2006.257.19:10:36.29/va/03,08,usb,yes,31,33 2006.257.19:10:36.29/va/04,07,usb,yes,36,37 2006.257.19:10:36.29/va/05,04,usb,yes,32,32 2006.257.19:10:36.29/va/06,04,usb,yes,35,35 2006.257.19:10:36.29/va/07,04,usb,yes,36,36 2006.257.19:10:36.29/va/08,04,usb,yes,30,37 2006.257.19:10:36.52/valo/01,524.99,yes,locked 2006.257.19:10:36.52/valo/02,534.99,yes,locked 2006.257.19:10:36.52/valo/03,564.99,yes,locked 2006.257.19:10:36.52/valo/04,624.99,yes,locked 2006.257.19:10:36.52/valo/05,734.99,yes,locked 2006.257.19:10:36.52/valo/06,814.99,yes,locked 2006.257.19:10:36.52/valo/07,864.99,yes,locked 2006.257.19:10:36.52/valo/08,884.99,yes,locked 2006.257.19:10:37.61/vb/01,04,usb,yes,30,28 2006.257.19:10:37.61/vb/02,05,usb,yes,28,28 2006.257.19:10:37.61/vb/03,04,usb,yes,29,32 2006.257.19:10:37.61/vb/04,05,usb,yes,30,29 2006.257.19:10:37.61/vb/05,04,usb,yes,26,29 2006.257.19:10:37.61/vb/06,04,usb,yes,31,27 2006.257.19:10:37.61/vb/07,04,usb,yes,30,30 2006.257.19:10:37.61/vb/08,04,usb,yes,28,31 2006.257.19:10:37.85/vblo/01,629.99,yes,locked 2006.257.19:10:37.85/vblo/02,634.99,yes,locked 2006.257.19:10:37.85/vblo/03,649.99,yes,locked 2006.257.19:10:37.85/vblo/04,679.99,yes,locked 2006.257.19:10:37.85/vblo/05,709.99,yes,locked 2006.257.19:10:37.85/vblo/06,719.99,yes,locked 2006.257.19:10:37.85/vblo/07,734.99,yes,locked 2006.257.19:10:37.85/vblo/08,744.99,yes,locked 2006.257.19:10:38.00/vabw/8 2006.257.19:10:38.15/vbbw/8 2006.257.19:10:38.24/xfe/off,on,14.7 2006.257.19:10:38.62/ifatt/23,28,28,28 2006.257.19:10:39.07/fmout-gps/S +4.57E-07 2006.257.19:10:39.11:!2006.257.19:18:15 2006.257.19:18:15.00:data_valid=off 2006.257.19:18:15.01:"et 2006.257.19:18:15.01:!+3s 2006.257.19:18:18.02:"tape 2006.257.19:18:18.03:postob 2006.257.19:18:18.15/cable/+6.4842E-03 2006.257.19:18:18.16/wx/17.46,1014.3,96 2006.257.19:18:18.21/fmout-gps/S +4.56E-07 2006.257.19:18:18.22:scan_name=257-1924,jd0609,210 2006.257.19:18:18.22:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.257.19:18:20.13#flagr#flagr/antenna,new-source 2006.257.19:18:20.14:checkk5 2006.257.19:18:20.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.19:18:20.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.19:18:21.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.19:18:21.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.19:18:21.86/chk_obsdata//k5ts1/T2571910??a.dat file size is correct (nominal:1840MB, actual:1836MB). 2006.257.19:18:22.19/chk_obsdata//k5ts2/T2571910??b.dat file size is correct (nominal:1840MB, actual:1836MB). 2006.257.19:18:22.53/chk_obsdata//k5ts3/T2571910??c.dat file size is correct (nominal:1840MB, actual:1836MB). 2006.257.19:18:22.87/chk_obsdata//k5ts4/T2571910??d.dat file size is correct (nominal:1840MB, actual:1836MB). 2006.257.19:18:23.52/k5log//k5ts1_log_newline 2006.257.19:18:24.19/k5log//k5ts2_log_newline 2006.257.19:18:24.86/k5log//k5ts3_log_newline 2006.257.19:18:25.52/k5log//k5ts4_log_newline 2006.257.19:18:25.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.19:18:25.55:setupk4=1 2006.257.19:18:25.55$setupk4/echo=on 2006.257.19:18:25.55$setupk4/pcalon 2006.257.19:18:25.55$pcalon/"no phase cal control is implemented here 2006.257.19:18:25.55$setupk4/"tpicd=stop 2006.257.19:18:25.55$setupk4/"rec=synch_on 2006.257.19:18:25.55$setupk4/"rec_mode=128 2006.257.19:18:25.55$setupk4/!* 2006.257.19:18:25.55$setupk4/recpk4 2006.257.19:18:25.55$recpk4/recpatch= 2006.257.19:18:25.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.19:18:25.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.19:18:25.55$setupk4/vck44 2006.257.19:18:25.55$vck44/valo=1,524.99 2006.257.19:18:25.55#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.19:18:25.55#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.19:18:25.55#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:25.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:25.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:25.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:25.55#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:18:25.55#ibcon#first serial, iclass 38, count 0 2006.257.19:18:25.55#ibcon#enter sib2, iclass 38, count 0 2006.257.19:18:25.55#ibcon#flushed, iclass 38, count 0 2006.257.19:18:25.55#ibcon#about to write, iclass 38, count 0 2006.257.19:18:25.55#ibcon#wrote, iclass 38, count 0 2006.257.19:18:25.55#ibcon#about to read 3, iclass 38, count 0 2006.257.19:18:25.56#ibcon#read 3, iclass 38, count 0 2006.257.19:18:25.56#ibcon#about to read 4, iclass 38, count 0 2006.257.19:18:25.56#ibcon#read 4, iclass 38, count 0 2006.257.19:18:25.56#ibcon#about to read 5, iclass 38, count 0 2006.257.19:18:25.56#ibcon#read 5, iclass 38, count 0 2006.257.19:18:25.56#ibcon#about to read 6, iclass 38, count 0 2006.257.19:18:25.56#ibcon#read 6, iclass 38, count 0 2006.257.19:18:25.56#ibcon#end of sib2, iclass 38, count 0 2006.257.19:18:25.56#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:18:25.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:18:25.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.19:18:25.56#ibcon#*before write, iclass 38, count 0 2006.257.19:18:25.56#ibcon#enter sib2, iclass 38, count 0 2006.257.19:18:25.56#ibcon#flushed, iclass 38, count 0 2006.257.19:18:25.56#ibcon#about to write, iclass 38, count 0 2006.257.19:18:25.56#ibcon#wrote, iclass 38, count 0 2006.257.19:18:25.56#ibcon#about to read 3, iclass 38, count 0 2006.257.19:18:25.61#ibcon#read 3, iclass 38, count 0 2006.257.19:18:25.61#ibcon#about to read 4, iclass 38, count 0 2006.257.19:18:25.61#ibcon#read 4, iclass 38, count 0 2006.257.19:18:25.61#ibcon#about to read 5, iclass 38, count 0 2006.257.19:18:25.61#ibcon#read 5, iclass 38, count 0 2006.257.19:18:25.61#ibcon#about to read 6, iclass 38, count 0 2006.257.19:18:25.61#ibcon#read 6, iclass 38, count 0 2006.257.19:18:25.61#ibcon#end of sib2, iclass 38, count 0 2006.257.19:18:25.61#ibcon#*after write, iclass 38, count 0 2006.257.19:18:25.61#ibcon#*before return 0, iclass 38, count 0 2006.257.19:18:25.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:25.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:25.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:18:25.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:18:25.61$vck44/va=1,8 2006.257.19:18:25.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.19:18:25.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.19:18:25.61#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:25.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:25.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:25.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:25.61#ibcon#enter wrdev, iclass 40, count 2 2006.257.19:18:25.61#ibcon#first serial, iclass 40, count 2 2006.257.19:18:25.61#ibcon#enter sib2, iclass 40, count 2 2006.257.19:18:25.61#ibcon#flushed, iclass 40, count 2 2006.257.19:18:25.61#ibcon#about to write, iclass 40, count 2 2006.257.19:18:25.61#ibcon#wrote, iclass 40, count 2 2006.257.19:18:25.61#ibcon#about to read 3, iclass 40, count 2 2006.257.19:18:25.63#ibcon#read 3, iclass 40, count 2 2006.257.19:18:25.63#ibcon#about to read 4, iclass 40, count 2 2006.257.19:18:25.63#ibcon#read 4, iclass 40, count 2 2006.257.19:18:25.63#ibcon#about to read 5, iclass 40, count 2 2006.257.19:18:25.63#ibcon#read 5, iclass 40, count 2 2006.257.19:18:25.63#ibcon#about to read 6, iclass 40, count 2 2006.257.19:18:25.63#ibcon#read 6, iclass 40, count 2 2006.257.19:18:25.63#ibcon#end of sib2, iclass 40, count 2 2006.257.19:18:25.63#ibcon#*mode == 0, iclass 40, count 2 2006.257.19:18:25.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.19:18:25.63#ibcon#[25=AT01-08\r\n] 2006.257.19:18:25.63#ibcon#*before write, iclass 40, count 2 2006.257.19:18:25.63#ibcon#enter sib2, iclass 40, count 2 2006.257.19:18:25.63#ibcon#flushed, iclass 40, count 2 2006.257.19:18:25.63#ibcon#about to write, iclass 40, count 2 2006.257.19:18:25.63#ibcon#wrote, iclass 40, count 2 2006.257.19:18:25.63#ibcon#about to read 3, iclass 40, count 2 2006.257.19:18:25.66#ibcon#read 3, iclass 40, count 2 2006.257.19:18:25.66#ibcon#about to read 4, iclass 40, count 2 2006.257.19:18:25.66#ibcon#read 4, iclass 40, count 2 2006.257.19:18:25.66#ibcon#about to read 5, iclass 40, count 2 2006.257.19:18:25.66#ibcon#read 5, iclass 40, count 2 2006.257.19:18:25.66#ibcon#about to read 6, iclass 40, count 2 2006.257.19:18:25.66#ibcon#read 6, iclass 40, count 2 2006.257.19:18:25.66#ibcon#end of sib2, iclass 40, count 2 2006.257.19:18:25.66#ibcon#*after write, iclass 40, count 2 2006.257.19:18:25.66#ibcon#*before return 0, iclass 40, count 2 2006.257.19:18:25.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:25.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:25.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.19:18:25.66#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:25.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:25.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:25.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:25.78#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:18:25.78#ibcon#first serial, iclass 40, count 0 2006.257.19:18:25.78#ibcon#enter sib2, iclass 40, count 0 2006.257.19:18:25.78#ibcon#flushed, iclass 40, count 0 2006.257.19:18:25.78#ibcon#about to write, iclass 40, count 0 2006.257.19:18:25.78#ibcon#wrote, iclass 40, count 0 2006.257.19:18:25.78#ibcon#about to read 3, iclass 40, count 0 2006.257.19:18:25.80#ibcon#read 3, iclass 40, count 0 2006.257.19:18:25.80#ibcon#about to read 4, iclass 40, count 0 2006.257.19:18:25.80#ibcon#read 4, iclass 40, count 0 2006.257.19:18:25.80#ibcon#about to read 5, iclass 40, count 0 2006.257.19:18:25.80#ibcon#read 5, iclass 40, count 0 2006.257.19:18:25.80#ibcon#about to read 6, iclass 40, count 0 2006.257.19:18:25.80#ibcon#read 6, iclass 40, count 0 2006.257.19:18:25.80#ibcon#end of sib2, iclass 40, count 0 2006.257.19:18:25.80#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:18:25.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:18:25.80#ibcon#[25=USB\r\n] 2006.257.19:18:25.80#ibcon#*before write, iclass 40, count 0 2006.257.19:18:25.80#ibcon#enter sib2, iclass 40, count 0 2006.257.19:18:25.80#ibcon#flushed, iclass 40, count 0 2006.257.19:18:25.80#ibcon#about to write, iclass 40, count 0 2006.257.19:18:25.80#ibcon#wrote, iclass 40, count 0 2006.257.19:18:25.80#ibcon#about to read 3, iclass 40, count 0 2006.257.19:18:25.83#ibcon#read 3, iclass 40, count 0 2006.257.19:18:25.83#ibcon#about to read 4, iclass 40, count 0 2006.257.19:18:25.83#ibcon#read 4, iclass 40, count 0 2006.257.19:18:25.83#ibcon#about to read 5, iclass 40, count 0 2006.257.19:18:25.83#ibcon#read 5, iclass 40, count 0 2006.257.19:18:25.83#ibcon#about to read 6, iclass 40, count 0 2006.257.19:18:25.83#ibcon#read 6, iclass 40, count 0 2006.257.19:18:25.83#ibcon#end of sib2, iclass 40, count 0 2006.257.19:18:25.83#ibcon#*after write, iclass 40, count 0 2006.257.19:18:25.83#ibcon#*before return 0, iclass 40, count 0 2006.257.19:18:25.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:25.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:25.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:18:25.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:18:25.83$vck44/valo=2,534.99 2006.257.19:18:25.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.19:18:25.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.19:18:25.83#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:25.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:25.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:25.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:25.83#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:18:25.83#ibcon#first serial, iclass 4, count 0 2006.257.19:18:25.83#ibcon#enter sib2, iclass 4, count 0 2006.257.19:18:25.83#ibcon#flushed, iclass 4, count 0 2006.257.19:18:25.83#ibcon#about to write, iclass 4, count 0 2006.257.19:18:25.83#ibcon#wrote, iclass 4, count 0 2006.257.19:18:25.83#ibcon#about to read 3, iclass 4, count 0 2006.257.19:18:25.85#ibcon#read 3, iclass 4, count 0 2006.257.19:18:25.85#ibcon#about to read 4, iclass 4, count 0 2006.257.19:18:25.85#ibcon#read 4, iclass 4, count 0 2006.257.19:18:25.85#ibcon#about to read 5, iclass 4, count 0 2006.257.19:18:25.85#ibcon#read 5, iclass 4, count 0 2006.257.19:18:25.85#ibcon#about to read 6, iclass 4, count 0 2006.257.19:18:25.85#ibcon#read 6, iclass 4, count 0 2006.257.19:18:25.85#ibcon#end of sib2, iclass 4, count 0 2006.257.19:18:25.85#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:18:25.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:18:25.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.19:18:25.85#ibcon#*before write, iclass 4, count 0 2006.257.19:18:25.85#ibcon#enter sib2, iclass 4, count 0 2006.257.19:18:25.85#ibcon#flushed, iclass 4, count 0 2006.257.19:18:25.85#ibcon#about to write, iclass 4, count 0 2006.257.19:18:25.85#ibcon#wrote, iclass 4, count 0 2006.257.19:18:25.85#ibcon#about to read 3, iclass 4, count 0 2006.257.19:18:25.89#ibcon#read 3, iclass 4, count 0 2006.257.19:18:25.89#ibcon#about to read 4, iclass 4, count 0 2006.257.19:18:25.89#ibcon#read 4, iclass 4, count 0 2006.257.19:18:25.89#ibcon#about to read 5, iclass 4, count 0 2006.257.19:18:25.89#ibcon#read 5, iclass 4, count 0 2006.257.19:18:25.89#ibcon#about to read 6, iclass 4, count 0 2006.257.19:18:25.89#ibcon#read 6, iclass 4, count 0 2006.257.19:18:25.89#ibcon#end of sib2, iclass 4, count 0 2006.257.19:18:25.89#ibcon#*after write, iclass 4, count 0 2006.257.19:18:25.89#ibcon#*before return 0, iclass 4, count 0 2006.257.19:18:25.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:25.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:25.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:18:25.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:18:25.89$vck44/va=2,7 2006.257.19:18:25.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.19:18:25.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.19:18:25.89#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:25.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:25.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:25.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:25.95#ibcon#enter wrdev, iclass 6, count 2 2006.257.19:18:25.95#ibcon#first serial, iclass 6, count 2 2006.257.19:18:25.95#ibcon#enter sib2, iclass 6, count 2 2006.257.19:18:25.95#ibcon#flushed, iclass 6, count 2 2006.257.19:18:25.95#ibcon#about to write, iclass 6, count 2 2006.257.19:18:25.95#ibcon#wrote, iclass 6, count 2 2006.257.19:18:25.95#ibcon#about to read 3, iclass 6, count 2 2006.257.19:18:25.97#ibcon#read 3, iclass 6, count 2 2006.257.19:18:25.97#ibcon#about to read 4, iclass 6, count 2 2006.257.19:18:25.97#ibcon#read 4, iclass 6, count 2 2006.257.19:18:25.97#ibcon#about to read 5, iclass 6, count 2 2006.257.19:18:25.97#ibcon#read 5, iclass 6, count 2 2006.257.19:18:25.97#ibcon#about to read 6, iclass 6, count 2 2006.257.19:18:25.97#ibcon#read 6, iclass 6, count 2 2006.257.19:18:25.97#ibcon#end of sib2, iclass 6, count 2 2006.257.19:18:25.97#ibcon#*mode == 0, iclass 6, count 2 2006.257.19:18:25.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.19:18:25.97#ibcon#[25=AT02-07\r\n] 2006.257.19:18:25.97#ibcon#*before write, iclass 6, count 2 2006.257.19:18:25.97#ibcon#enter sib2, iclass 6, count 2 2006.257.19:18:25.97#ibcon#flushed, iclass 6, count 2 2006.257.19:18:25.97#ibcon#about to write, iclass 6, count 2 2006.257.19:18:25.97#ibcon#wrote, iclass 6, count 2 2006.257.19:18:25.97#ibcon#about to read 3, iclass 6, count 2 2006.257.19:18:26.00#ibcon#read 3, iclass 6, count 2 2006.257.19:18:26.00#ibcon#about to read 4, iclass 6, count 2 2006.257.19:18:26.00#ibcon#read 4, iclass 6, count 2 2006.257.19:18:26.00#ibcon#about to read 5, iclass 6, count 2 2006.257.19:18:26.00#ibcon#read 5, iclass 6, count 2 2006.257.19:18:26.00#ibcon#about to read 6, iclass 6, count 2 2006.257.19:18:26.00#ibcon#read 6, iclass 6, count 2 2006.257.19:18:26.00#ibcon#end of sib2, iclass 6, count 2 2006.257.19:18:26.00#ibcon#*after write, iclass 6, count 2 2006.257.19:18:26.00#ibcon#*before return 0, iclass 6, count 2 2006.257.19:18:26.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:26.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:26.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.19:18:26.00#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:26.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:26.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:26.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:26.12#ibcon#enter wrdev, iclass 6, count 0 2006.257.19:18:26.12#ibcon#first serial, iclass 6, count 0 2006.257.19:18:26.12#ibcon#enter sib2, iclass 6, count 0 2006.257.19:18:26.12#ibcon#flushed, iclass 6, count 0 2006.257.19:18:26.12#ibcon#about to write, iclass 6, count 0 2006.257.19:18:26.12#ibcon#wrote, iclass 6, count 0 2006.257.19:18:26.12#ibcon#about to read 3, iclass 6, count 0 2006.257.19:18:26.14#ibcon#read 3, iclass 6, count 0 2006.257.19:18:26.14#ibcon#about to read 4, iclass 6, count 0 2006.257.19:18:26.14#ibcon#read 4, iclass 6, count 0 2006.257.19:18:26.14#ibcon#about to read 5, iclass 6, count 0 2006.257.19:18:26.14#ibcon#read 5, iclass 6, count 0 2006.257.19:18:26.14#ibcon#about to read 6, iclass 6, count 0 2006.257.19:18:26.14#ibcon#read 6, iclass 6, count 0 2006.257.19:18:26.14#ibcon#end of sib2, iclass 6, count 0 2006.257.19:18:26.14#ibcon#*mode == 0, iclass 6, count 0 2006.257.19:18:26.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.19:18:26.14#ibcon#[25=USB\r\n] 2006.257.19:18:26.14#ibcon#*before write, iclass 6, count 0 2006.257.19:18:26.14#ibcon#enter sib2, iclass 6, count 0 2006.257.19:18:26.14#ibcon#flushed, iclass 6, count 0 2006.257.19:18:26.14#ibcon#about to write, iclass 6, count 0 2006.257.19:18:26.14#ibcon#wrote, iclass 6, count 0 2006.257.19:18:26.14#ibcon#about to read 3, iclass 6, count 0 2006.257.19:18:26.17#ibcon#read 3, iclass 6, count 0 2006.257.19:18:26.17#ibcon#about to read 4, iclass 6, count 0 2006.257.19:18:26.17#ibcon#read 4, iclass 6, count 0 2006.257.19:18:26.17#ibcon#about to read 5, iclass 6, count 0 2006.257.19:18:26.17#ibcon#read 5, iclass 6, count 0 2006.257.19:18:26.17#ibcon#about to read 6, iclass 6, count 0 2006.257.19:18:26.17#ibcon#read 6, iclass 6, count 0 2006.257.19:18:26.17#ibcon#end of sib2, iclass 6, count 0 2006.257.19:18:26.17#ibcon#*after write, iclass 6, count 0 2006.257.19:18:26.17#ibcon#*before return 0, iclass 6, count 0 2006.257.19:18:26.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:26.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:26.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.19:18:26.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.19:18:26.17$vck44/valo=3,564.99 2006.257.19:18:26.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.19:18:26.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.19:18:26.17#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:26.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:26.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:26.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:26.17#ibcon#enter wrdev, iclass 10, count 0 2006.257.19:18:26.17#ibcon#first serial, iclass 10, count 0 2006.257.19:18:26.17#ibcon#enter sib2, iclass 10, count 0 2006.257.19:18:26.17#ibcon#flushed, iclass 10, count 0 2006.257.19:18:26.17#ibcon#about to write, iclass 10, count 0 2006.257.19:18:26.17#ibcon#wrote, iclass 10, count 0 2006.257.19:18:26.17#ibcon#about to read 3, iclass 10, count 0 2006.257.19:18:26.19#ibcon#read 3, iclass 10, count 0 2006.257.19:18:26.19#ibcon#about to read 4, iclass 10, count 0 2006.257.19:18:26.19#ibcon#read 4, iclass 10, count 0 2006.257.19:18:26.19#ibcon#about to read 5, iclass 10, count 0 2006.257.19:18:26.19#ibcon#read 5, iclass 10, count 0 2006.257.19:18:26.19#ibcon#about to read 6, iclass 10, count 0 2006.257.19:18:26.19#ibcon#read 6, iclass 10, count 0 2006.257.19:18:26.19#ibcon#end of sib2, iclass 10, count 0 2006.257.19:18:26.19#ibcon#*mode == 0, iclass 10, count 0 2006.257.19:18:26.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.19:18:26.19#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.19:18:26.19#ibcon#*before write, iclass 10, count 0 2006.257.19:18:26.19#ibcon#enter sib2, iclass 10, count 0 2006.257.19:18:26.19#ibcon#flushed, iclass 10, count 0 2006.257.19:18:26.19#ibcon#about to write, iclass 10, count 0 2006.257.19:18:26.19#ibcon#wrote, iclass 10, count 0 2006.257.19:18:26.19#ibcon#about to read 3, iclass 10, count 0 2006.257.19:18:26.23#ibcon#read 3, iclass 10, count 0 2006.257.19:18:26.23#ibcon#about to read 4, iclass 10, count 0 2006.257.19:18:26.23#ibcon#read 4, iclass 10, count 0 2006.257.19:18:26.23#ibcon#about to read 5, iclass 10, count 0 2006.257.19:18:26.23#ibcon#read 5, iclass 10, count 0 2006.257.19:18:26.23#ibcon#about to read 6, iclass 10, count 0 2006.257.19:18:26.23#ibcon#read 6, iclass 10, count 0 2006.257.19:18:26.23#ibcon#end of sib2, iclass 10, count 0 2006.257.19:18:26.23#ibcon#*after write, iclass 10, count 0 2006.257.19:18:26.23#ibcon#*before return 0, iclass 10, count 0 2006.257.19:18:26.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:26.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:26.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.19:18:26.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.19:18:26.23$vck44/va=3,8 2006.257.19:18:26.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.19:18:26.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.19:18:26.23#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:26.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:26.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:26.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:26.29#ibcon#enter wrdev, iclass 12, count 2 2006.257.19:18:26.29#ibcon#first serial, iclass 12, count 2 2006.257.19:18:26.29#ibcon#enter sib2, iclass 12, count 2 2006.257.19:18:26.29#ibcon#flushed, iclass 12, count 2 2006.257.19:18:26.29#ibcon#about to write, iclass 12, count 2 2006.257.19:18:26.29#ibcon#wrote, iclass 12, count 2 2006.257.19:18:26.29#ibcon#about to read 3, iclass 12, count 2 2006.257.19:18:26.31#ibcon#read 3, iclass 12, count 2 2006.257.19:18:26.31#ibcon#about to read 4, iclass 12, count 2 2006.257.19:18:26.31#ibcon#read 4, iclass 12, count 2 2006.257.19:18:26.31#ibcon#about to read 5, iclass 12, count 2 2006.257.19:18:26.31#ibcon#read 5, iclass 12, count 2 2006.257.19:18:26.31#ibcon#about to read 6, iclass 12, count 2 2006.257.19:18:26.31#ibcon#read 6, iclass 12, count 2 2006.257.19:18:26.31#ibcon#end of sib2, iclass 12, count 2 2006.257.19:18:26.31#ibcon#*mode == 0, iclass 12, count 2 2006.257.19:18:26.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.19:18:26.31#ibcon#[25=AT03-08\r\n] 2006.257.19:18:26.31#ibcon#*before write, iclass 12, count 2 2006.257.19:18:26.31#ibcon#enter sib2, iclass 12, count 2 2006.257.19:18:26.31#ibcon#flushed, iclass 12, count 2 2006.257.19:18:26.31#ibcon#about to write, iclass 12, count 2 2006.257.19:18:26.31#ibcon#wrote, iclass 12, count 2 2006.257.19:18:26.31#ibcon#about to read 3, iclass 12, count 2 2006.257.19:18:26.34#ibcon#read 3, iclass 12, count 2 2006.257.19:18:26.34#ibcon#about to read 4, iclass 12, count 2 2006.257.19:18:26.34#ibcon#read 4, iclass 12, count 2 2006.257.19:18:26.34#ibcon#about to read 5, iclass 12, count 2 2006.257.19:18:26.34#ibcon#read 5, iclass 12, count 2 2006.257.19:18:26.34#ibcon#about to read 6, iclass 12, count 2 2006.257.19:18:26.34#ibcon#read 6, iclass 12, count 2 2006.257.19:18:26.34#ibcon#end of sib2, iclass 12, count 2 2006.257.19:18:26.34#ibcon#*after write, iclass 12, count 2 2006.257.19:18:26.34#ibcon#*before return 0, iclass 12, count 2 2006.257.19:18:26.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:26.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:26.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.19:18:26.34#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:26.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:26.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:26.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:26.46#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:18:26.46#ibcon#first serial, iclass 12, count 0 2006.257.19:18:26.46#ibcon#enter sib2, iclass 12, count 0 2006.257.19:18:26.46#ibcon#flushed, iclass 12, count 0 2006.257.19:18:26.46#ibcon#about to write, iclass 12, count 0 2006.257.19:18:26.46#ibcon#wrote, iclass 12, count 0 2006.257.19:18:26.46#ibcon#about to read 3, iclass 12, count 0 2006.257.19:18:26.48#ibcon#read 3, iclass 12, count 0 2006.257.19:18:26.48#ibcon#about to read 4, iclass 12, count 0 2006.257.19:18:26.48#ibcon#read 4, iclass 12, count 0 2006.257.19:18:26.48#ibcon#about to read 5, iclass 12, count 0 2006.257.19:18:26.48#ibcon#read 5, iclass 12, count 0 2006.257.19:18:26.48#ibcon#about to read 6, iclass 12, count 0 2006.257.19:18:26.48#ibcon#read 6, iclass 12, count 0 2006.257.19:18:26.48#ibcon#end of sib2, iclass 12, count 0 2006.257.19:18:26.48#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:18:26.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:18:26.48#ibcon#[25=USB\r\n] 2006.257.19:18:26.48#ibcon#*before write, iclass 12, count 0 2006.257.19:18:26.48#ibcon#enter sib2, iclass 12, count 0 2006.257.19:18:26.48#ibcon#flushed, iclass 12, count 0 2006.257.19:18:26.48#ibcon#about to write, iclass 12, count 0 2006.257.19:18:26.48#ibcon#wrote, iclass 12, count 0 2006.257.19:18:26.48#ibcon#about to read 3, iclass 12, count 0 2006.257.19:18:26.51#ibcon#read 3, iclass 12, count 0 2006.257.19:18:26.51#ibcon#about to read 4, iclass 12, count 0 2006.257.19:18:26.51#ibcon#read 4, iclass 12, count 0 2006.257.19:18:26.51#ibcon#about to read 5, iclass 12, count 0 2006.257.19:18:26.51#ibcon#read 5, iclass 12, count 0 2006.257.19:18:26.51#ibcon#about to read 6, iclass 12, count 0 2006.257.19:18:26.51#ibcon#read 6, iclass 12, count 0 2006.257.19:18:26.51#ibcon#end of sib2, iclass 12, count 0 2006.257.19:18:26.51#ibcon#*after write, iclass 12, count 0 2006.257.19:18:26.51#ibcon#*before return 0, iclass 12, count 0 2006.257.19:18:26.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:26.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:26.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:18:26.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:18:26.51$vck44/valo=4,624.99 2006.257.19:18:26.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.19:18:26.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.19:18:26.51#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:26.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:26.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:26.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:26.51#ibcon#enter wrdev, iclass 14, count 0 2006.257.19:18:26.51#ibcon#first serial, iclass 14, count 0 2006.257.19:18:26.51#ibcon#enter sib2, iclass 14, count 0 2006.257.19:18:26.51#ibcon#flushed, iclass 14, count 0 2006.257.19:18:26.51#ibcon#about to write, iclass 14, count 0 2006.257.19:18:26.51#ibcon#wrote, iclass 14, count 0 2006.257.19:18:26.51#ibcon#about to read 3, iclass 14, count 0 2006.257.19:18:26.53#ibcon#read 3, iclass 14, count 0 2006.257.19:18:26.53#ibcon#about to read 4, iclass 14, count 0 2006.257.19:18:26.53#ibcon#read 4, iclass 14, count 0 2006.257.19:18:26.53#ibcon#about to read 5, iclass 14, count 0 2006.257.19:18:26.53#ibcon#read 5, iclass 14, count 0 2006.257.19:18:26.53#ibcon#about to read 6, iclass 14, count 0 2006.257.19:18:26.53#ibcon#read 6, iclass 14, count 0 2006.257.19:18:26.53#ibcon#end of sib2, iclass 14, count 0 2006.257.19:18:26.53#ibcon#*mode == 0, iclass 14, count 0 2006.257.19:18:26.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.19:18:26.53#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.19:18:26.53#ibcon#*before write, iclass 14, count 0 2006.257.19:18:26.53#ibcon#enter sib2, iclass 14, count 0 2006.257.19:18:26.53#ibcon#flushed, iclass 14, count 0 2006.257.19:18:26.53#ibcon#about to write, iclass 14, count 0 2006.257.19:18:26.53#ibcon#wrote, iclass 14, count 0 2006.257.19:18:26.53#ibcon#about to read 3, iclass 14, count 0 2006.257.19:18:26.57#ibcon#read 3, iclass 14, count 0 2006.257.19:18:26.57#ibcon#about to read 4, iclass 14, count 0 2006.257.19:18:26.57#ibcon#read 4, iclass 14, count 0 2006.257.19:18:26.57#ibcon#about to read 5, iclass 14, count 0 2006.257.19:18:26.57#ibcon#read 5, iclass 14, count 0 2006.257.19:18:26.57#ibcon#about to read 6, iclass 14, count 0 2006.257.19:18:26.57#ibcon#read 6, iclass 14, count 0 2006.257.19:18:26.57#ibcon#end of sib2, iclass 14, count 0 2006.257.19:18:26.57#ibcon#*after write, iclass 14, count 0 2006.257.19:18:26.57#ibcon#*before return 0, iclass 14, count 0 2006.257.19:18:26.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:26.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:26.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.19:18:26.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.19:18:26.57$vck44/va=4,7 2006.257.19:18:26.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.19:18:26.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.19:18:26.57#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:26.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:26.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:26.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:26.63#ibcon#enter wrdev, iclass 16, count 2 2006.257.19:18:26.63#ibcon#first serial, iclass 16, count 2 2006.257.19:18:26.63#ibcon#enter sib2, iclass 16, count 2 2006.257.19:18:26.63#ibcon#flushed, iclass 16, count 2 2006.257.19:18:26.63#ibcon#about to write, iclass 16, count 2 2006.257.19:18:26.63#ibcon#wrote, iclass 16, count 2 2006.257.19:18:26.63#ibcon#about to read 3, iclass 16, count 2 2006.257.19:18:26.65#ibcon#read 3, iclass 16, count 2 2006.257.19:18:26.65#ibcon#about to read 4, iclass 16, count 2 2006.257.19:18:26.65#ibcon#read 4, iclass 16, count 2 2006.257.19:18:26.65#ibcon#about to read 5, iclass 16, count 2 2006.257.19:18:26.65#ibcon#read 5, iclass 16, count 2 2006.257.19:18:26.65#ibcon#about to read 6, iclass 16, count 2 2006.257.19:18:26.65#ibcon#read 6, iclass 16, count 2 2006.257.19:18:26.65#ibcon#end of sib2, iclass 16, count 2 2006.257.19:18:26.65#ibcon#*mode == 0, iclass 16, count 2 2006.257.19:18:26.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.19:18:26.65#ibcon#[25=AT04-07\r\n] 2006.257.19:18:26.65#ibcon#*before write, iclass 16, count 2 2006.257.19:18:26.65#ibcon#enter sib2, iclass 16, count 2 2006.257.19:18:26.65#ibcon#flushed, iclass 16, count 2 2006.257.19:18:26.65#ibcon#about to write, iclass 16, count 2 2006.257.19:18:26.65#ibcon#wrote, iclass 16, count 2 2006.257.19:18:26.65#ibcon#about to read 3, iclass 16, count 2 2006.257.19:18:26.68#ibcon#read 3, iclass 16, count 2 2006.257.19:18:26.68#ibcon#about to read 4, iclass 16, count 2 2006.257.19:18:26.68#ibcon#read 4, iclass 16, count 2 2006.257.19:18:26.68#ibcon#about to read 5, iclass 16, count 2 2006.257.19:18:26.68#ibcon#read 5, iclass 16, count 2 2006.257.19:18:26.68#ibcon#about to read 6, iclass 16, count 2 2006.257.19:18:26.68#ibcon#read 6, iclass 16, count 2 2006.257.19:18:26.68#ibcon#end of sib2, iclass 16, count 2 2006.257.19:18:26.68#ibcon#*after write, iclass 16, count 2 2006.257.19:18:26.68#ibcon#*before return 0, iclass 16, count 2 2006.257.19:18:26.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:26.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:26.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.19:18:26.68#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:26.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:26.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:26.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:26.80#ibcon#enter wrdev, iclass 16, count 0 2006.257.19:18:26.80#ibcon#first serial, iclass 16, count 0 2006.257.19:18:26.80#ibcon#enter sib2, iclass 16, count 0 2006.257.19:18:26.80#ibcon#flushed, iclass 16, count 0 2006.257.19:18:26.80#ibcon#about to write, iclass 16, count 0 2006.257.19:18:26.80#ibcon#wrote, iclass 16, count 0 2006.257.19:18:26.80#ibcon#about to read 3, iclass 16, count 0 2006.257.19:18:26.82#ibcon#read 3, iclass 16, count 0 2006.257.19:18:26.82#ibcon#about to read 4, iclass 16, count 0 2006.257.19:18:26.82#ibcon#read 4, iclass 16, count 0 2006.257.19:18:26.82#ibcon#about to read 5, iclass 16, count 0 2006.257.19:18:26.82#ibcon#read 5, iclass 16, count 0 2006.257.19:18:26.82#ibcon#about to read 6, iclass 16, count 0 2006.257.19:18:26.82#ibcon#read 6, iclass 16, count 0 2006.257.19:18:26.82#ibcon#end of sib2, iclass 16, count 0 2006.257.19:18:26.82#ibcon#*mode == 0, iclass 16, count 0 2006.257.19:18:26.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.19:18:26.82#ibcon#[25=USB\r\n] 2006.257.19:18:26.82#ibcon#*before write, iclass 16, count 0 2006.257.19:18:26.82#ibcon#enter sib2, iclass 16, count 0 2006.257.19:18:26.82#ibcon#flushed, iclass 16, count 0 2006.257.19:18:26.82#ibcon#about to write, iclass 16, count 0 2006.257.19:18:26.82#ibcon#wrote, iclass 16, count 0 2006.257.19:18:26.82#ibcon#about to read 3, iclass 16, count 0 2006.257.19:18:26.85#ibcon#read 3, iclass 16, count 0 2006.257.19:18:26.85#ibcon#about to read 4, iclass 16, count 0 2006.257.19:18:26.85#ibcon#read 4, iclass 16, count 0 2006.257.19:18:26.85#ibcon#about to read 5, iclass 16, count 0 2006.257.19:18:26.85#ibcon#read 5, iclass 16, count 0 2006.257.19:18:26.85#ibcon#about to read 6, iclass 16, count 0 2006.257.19:18:26.85#ibcon#read 6, iclass 16, count 0 2006.257.19:18:26.85#ibcon#end of sib2, iclass 16, count 0 2006.257.19:18:26.85#ibcon#*after write, iclass 16, count 0 2006.257.19:18:26.85#ibcon#*before return 0, iclass 16, count 0 2006.257.19:18:26.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:26.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:26.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.19:18:26.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.19:18:26.85$vck44/valo=5,734.99 2006.257.19:18:26.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.19:18:26.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.19:18:26.85#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:26.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:26.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:26.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:26.85#ibcon#enter wrdev, iclass 18, count 0 2006.257.19:18:26.85#ibcon#first serial, iclass 18, count 0 2006.257.19:18:26.85#ibcon#enter sib2, iclass 18, count 0 2006.257.19:18:26.85#ibcon#flushed, iclass 18, count 0 2006.257.19:18:26.85#ibcon#about to write, iclass 18, count 0 2006.257.19:18:26.85#ibcon#wrote, iclass 18, count 0 2006.257.19:18:26.85#ibcon#about to read 3, iclass 18, count 0 2006.257.19:18:26.87#ibcon#read 3, iclass 18, count 0 2006.257.19:18:26.87#ibcon#about to read 4, iclass 18, count 0 2006.257.19:18:26.87#ibcon#read 4, iclass 18, count 0 2006.257.19:18:26.87#ibcon#about to read 5, iclass 18, count 0 2006.257.19:18:26.87#ibcon#read 5, iclass 18, count 0 2006.257.19:18:26.87#ibcon#about to read 6, iclass 18, count 0 2006.257.19:18:26.87#ibcon#read 6, iclass 18, count 0 2006.257.19:18:26.87#ibcon#end of sib2, iclass 18, count 0 2006.257.19:18:26.87#ibcon#*mode == 0, iclass 18, count 0 2006.257.19:18:26.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.19:18:26.87#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.19:18:26.87#ibcon#*before write, iclass 18, count 0 2006.257.19:18:26.87#ibcon#enter sib2, iclass 18, count 0 2006.257.19:18:26.87#ibcon#flushed, iclass 18, count 0 2006.257.19:18:26.87#ibcon#about to write, iclass 18, count 0 2006.257.19:18:26.87#ibcon#wrote, iclass 18, count 0 2006.257.19:18:26.87#ibcon#about to read 3, iclass 18, count 0 2006.257.19:18:26.91#ibcon#read 3, iclass 18, count 0 2006.257.19:18:26.91#ibcon#about to read 4, iclass 18, count 0 2006.257.19:18:26.91#ibcon#read 4, iclass 18, count 0 2006.257.19:18:26.91#ibcon#about to read 5, iclass 18, count 0 2006.257.19:18:26.91#ibcon#read 5, iclass 18, count 0 2006.257.19:18:26.91#ibcon#about to read 6, iclass 18, count 0 2006.257.19:18:26.91#ibcon#read 6, iclass 18, count 0 2006.257.19:18:26.91#ibcon#end of sib2, iclass 18, count 0 2006.257.19:18:26.91#ibcon#*after write, iclass 18, count 0 2006.257.19:18:26.91#ibcon#*before return 0, iclass 18, count 0 2006.257.19:18:26.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:26.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:26.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.19:18:26.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.19:18:26.91$vck44/va=5,4 2006.257.19:18:26.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.19:18:26.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.19:18:26.91#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:26.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:26.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:26.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:26.97#ibcon#enter wrdev, iclass 20, count 2 2006.257.19:18:26.97#ibcon#first serial, iclass 20, count 2 2006.257.19:18:26.97#ibcon#enter sib2, iclass 20, count 2 2006.257.19:18:26.97#ibcon#flushed, iclass 20, count 2 2006.257.19:18:26.97#ibcon#about to write, iclass 20, count 2 2006.257.19:18:26.97#ibcon#wrote, iclass 20, count 2 2006.257.19:18:26.97#ibcon#about to read 3, iclass 20, count 2 2006.257.19:18:26.99#ibcon#read 3, iclass 20, count 2 2006.257.19:18:26.99#ibcon#about to read 4, iclass 20, count 2 2006.257.19:18:26.99#ibcon#read 4, iclass 20, count 2 2006.257.19:18:26.99#ibcon#about to read 5, iclass 20, count 2 2006.257.19:18:26.99#ibcon#read 5, iclass 20, count 2 2006.257.19:18:26.99#ibcon#about to read 6, iclass 20, count 2 2006.257.19:18:26.99#ibcon#read 6, iclass 20, count 2 2006.257.19:18:26.99#ibcon#end of sib2, iclass 20, count 2 2006.257.19:18:26.99#ibcon#*mode == 0, iclass 20, count 2 2006.257.19:18:26.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.19:18:26.99#ibcon#[25=AT05-04\r\n] 2006.257.19:18:26.99#ibcon#*before write, iclass 20, count 2 2006.257.19:18:26.99#ibcon#enter sib2, iclass 20, count 2 2006.257.19:18:26.99#ibcon#flushed, iclass 20, count 2 2006.257.19:18:26.99#ibcon#about to write, iclass 20, count 2 2006.257.19:18:26.99#ibcon#wrote, iclass 20, count 2 2006.257.19:18:26.99#ibcon#about to read 3, iclass 20, count 2 2006.257.19:18:27.02#ibcon#read 3, iclass 20, count 2 2006.257.19:18:27.02#ibcon#about to read 4, iclass 20, count 2 2006.257.19:18:27.02#ibcon#read 4, iclass 20, count 2 2006.257.19:18:27.02#ibcon#about to read 5, iclass 20, count 2 2006.257.19:18:27.02#ibcon#read 5, iclass 20, count 2 2006.257.19:18:27.02#ibcon#about to read 6, iclass 20, count 2 2006.257.19:18:27.02#ibcon#read 6, iclass 20, count 2 2006.257.19:18:27.02#ibcon#end of sib2, iclass 20, count 2 2006.257.19:18:27.02#ibcon#*after write, iclass 20, count 2 2006.257.19:18:27.02#ibcon#*before return 0, iclass 20, count 2 2006.257.19:18:27.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:27.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:27.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.19:18:27.02#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:27.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:27.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:27.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:27.14#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:18:27.14#ibcon#first serial, iclass 20, count 0 2006.257.19:18:27.14#ibcon#enter sib2, iclass 20, count 0 2006.257.19:18:27.14#ibcon#flushed, iclass 20, count 0 2006.257.19:18:27.14#ibcon#about to write, iclass 20, count 0 2006.257.19:18:27.14#ibcon#wrote, iclass 20, count 0 2006.257.19:18:27.14#ibcon#about to read 3, iclass 20, count 0 2006.257.19:18:27.16#ibcon#read 3, iclass 20, count 0 2006.257.19:18:27.16#ibcon#about to read 4, iclass 20, count 0 2006.257.19:18:27.16#ibcon#read 4, iclass 20, count 0 2006.257.19:18:27.16#ibcon#about to read 5, iclass 20, count 0 2006.257.19:18:27.16#ibcon#read 5, iclass 20, count 0 2006.257.19:18:27.16#ibcon#about to read 6, iclass 20, count 0 2006.257.19:18:27.16#ibcon#read 6, iclass 20, count 0 2006.257.19:18:27.16#ibcon#end of sib2, iclass 20, count 0 2006.257.19:18:27.16#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:18:27.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:18:27.16#ibcon#[25=USB\r\n] 2006.257.19:18:27.16#ibcon#*before write, iclass 20, count 0 2006.257.19:18:27.16#ibcon#enter sib2, iclass 20, count 0 2006.257.19:18:27.16#ibcon#flushed, iclass 20, count 0 2006.257.19:18:27.16#ibcon#about to write, iclass 20, count 0 2006.257.19:18:27.16#ibcon#wrote, iclass 20, count 0 2006.257.19:18:27.16#ibcon#about to read 3, iclass 20, count 0 2006.257.19:18:27.19#ibcon#read 3, iclass 20, count 0 2006.257.19:18:27.19#ibcon#about to read 4, iclass 20, count 0 2006.257.19:18:27.19#ibcon#read 4, iclass 20, count 0 2006.257.19:18:27.19#ibcon#about to read 5, iclass 20, count 0 2006.257.19:18:27.19#ibcon#read 5, iclass 20, count 0 2006.257.19:18:27.19#ibcon#about to read 6, iclass 20, count 0 2006.257.19:18:27.19#ibcon#read 6, iclass 20, count 0 2006.257.19:18:27.19#ibcon#end of sib2, iclass 20, count 0 2006.257.19:18:27.19#ibcon#*after write, iclass 20, count 0 2006.257.19:18:27.19#ibcon#*before return 0, iclass 20, count 0 2006.257.19:18:27.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:27.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:27.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:18:27.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:18:27.19$vck44/valo=6,814.99 2006.257.19:18:27.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.19:18:27.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.19:18:27.19#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:27.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:27.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:27.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:27.19#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:18:27.19#ibcon#first serial, iclass 22, count 0 2006.257.19:18:27.19#ibcon#enter sib2, iclass 22, count 0 2006.257.19:18:27.19#ibcon#flushed, iclass 22, count 0 2006.257.19:18:27.19#ibcon#about to write, iclass 22, count 0 2006.257.19:18:27.19#ibcon#wrote, iclass 22, count 0 2006.257.19:18:27.19#ibcon#about to read 3, iclass 22, count 0 2006.257.19:18:27.21#ibcon#read 3, iclass 22, count 0 2006.257.19:18:27.21#ibcon#about to read 4, iclass 22, count 0 2006.257.19:18:27.21#ibcon#read 4, iclass 22, count 0 2006.257.19:18:27.21#ibcon#about to read 5, iclass 22, count 0 2006.257.19:18:27.21#ibcon#read 5, iclass 22, count 0 2006.257.19:18:27.21#ibcon#about to read 6, iclass 22, count 0 2006.257.19:18:27.21#ibcon#read 6, iclass 22, count 0 2006.257.19:18:27.21#ibcon#end of sib2, iclass 22, count 0 2006.257.19:18:27.21#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:18:27.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:18:27.21#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.19:18:27.21#ibcon#*before write, iclass 22, count 0 2006.257.19:18:27.21#ibcon#enter sib2, iclass 22, count 0 2006.257.19:18:27.21#ibcon#flushed, iclass 22, count 0 2006.257.19:18:27.21#ibcon#about to write, iclass 22, count 0 2006.257.19:18:27.21#ibcon#wrote, iclass 22, count 0 2006.257.19:18:27.21#ibcon#about to read 3, iclass 22, count 0 2006.257.19:18:27.25#ibcon#read 3, iclass 22, count 0 2006.257.19:18:27.25#ibcon#about to read 4, iclass 22, count 0 2006.257.19:18:27.25#ibcon#read 4, iclass 22, count 0 2006.257.19:18:27.25#ibcon#about to read 5, iclass 22, count 0 2006.257.19:18:27.25#ibcon#read 5, iclass 22, count 0 2006.257.19:18:27.25#ibcon#about to read 6, iclass 22, count 0 2006.257.19:18:27.25#ibcon#read 6, iclass 22, count 0 2006.257.19:18:27.25#ibcon#end of sib2, iclass 22, count 0 2006.257.19:18:27.25#ibcon#*after write, iclass 22, count 0 2006.257.19:18:27.25#ibcon#*before return 0, iclass 22, count 0 2006.257.19:18:27.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:27.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:27.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:18:27.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:18:27.25$vck44/va=6,4 2006.257.19:18:27.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.19:18:27.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.19:18:27.25#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:27.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:27.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:27.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:27.31#ibcon#enter wrdev, iclass 24, count 2 2006.257.19:18:27.31#ibcon#first serial, iclass 24, count 2 2006.257.19:18:27.31#ibcon#enter sib2, iclass 24, count 2 2006.257.19:18:27.31#ibcon#flushed, iclass 24, count 2 2006.257.19:18:27.31#ibcon#about to write, iclass 24, count 2 2006.257.19:18:27.31#ibcon#wrote, iclass 24, count 2 2006.257.19:18:27.31#ibcon#about to read 3, iclass 24, count 2 2006.257.19:18:27.33#ibcon#read 3, iclass 24, count 2 2006.257.19:18:27.33#ibcon#about to read 4, iclass 24, count 2 2006.257.19:18:27.33#ibcon#read 4, iclass 24, count 2 2006.257.19:18:27.33#ibcon#about to read 5, iclass 24, count 2 2006.257.19:18:27.33#ibcon#read 5, iclass 24, count 2 2006.257.19:18:27.33#ibcon#about to read 6, iclass 24, count 2 2006.257.19:18:27.33#ibcon#read 6, iclass 24, count 2 2006.257.19:18:27.33#ibcon#end of sib2, iclass 24, count 2 2006.257.19:18:27.33#ibcon#*mode == 0, iclass 24, count 2 2006.257.19:18:27.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.19:18:27.33#ibcon#[25=AT06-04\r\n] 2006.257.19:18:27.33#ibcon#*before write, iclass 24, count 2 2006.257.19:18:27.33#ibcon#enter sib2, iclass 24, count 2 2006.257.19:18:27.33#ibcon#flushed, iclass 24, count 2 2006.257.19:18:27.33#ibcon#about to write, iclass 24, count 2 2006.257.19:18:27.33#ibcon#wrote, iclass 24, count 2 2006.257.19:18:27.33#ibcon#about to read 3, iclass 24, count 2 2006.257.19:18:27.36#ibcon#read 3, iclass 24, count 2 2006.257.19:18:27.36#ibcon#about to read 4, iclass 24, count 2 2006.257.19:18:27.36#ibcon#read 4, iclass 24, count 2 2006.257.19:18:27.36#ibcon#about to read 5, iclass 24, count 2 2006.257.19:18:27.36#ibcon#read 5, iclass 24, count 2 2006.257.19:18:27.36#ibcon#about to read 6, iclass 24, count 2 2006.257.19:18:27.36#ibcon#read 6, iclass 24, count 2 2006.257.19:18:27.36#ibcon#end of sib2, iclass 24, count 2 2006.257.19:18:27.36#ibcon#*after write, iclass 24, count 2 2006.257.19:18:27.36#ibcon#*before return 0, iclass 24, count 2 2006.257.19:18:27.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:27.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:27.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.19:18:27.36#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:27.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:27.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:27.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:27.48#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:18:27.48#ibcon#first serial, iclass 24, count 0 2006.257.19:18:27.48#ibcon#enter sib2, iclass 24, count 0 2006.257.19:18:27.48#ibcon#flushed, iclass 24, count 0 2006.257.19:18:27.48#ibcon#about to write, iclass 24, count 0 2006.257.19:18:27.48#ibcon#wrote, iclass 24, count 0 2006.257.19:18:27.48#ibcon#about to read 3, iclass 24, count 0 2006.257.19:18:27.50#ibcon#read 3, iclass 24, count 0 2006.257.19:18:27.50#ibcon#about to read 4, iclass 24, count 0 2006.257.19:18:27.50#ibcon#read 4, iclass 24, count 0 2006.257.19:18:27.50#ibcon#about to read 5, iclass 24, count 0 2006.257.19:18:27.50#ibcon#read 5, iclass 24, count 0 2006.257.19:18:27.50#ibcon#about to read 6, iclass 24, count 0 2006.257.19:18:27.50#ibcon#read 6, iclass 24, count 0 2006.257.19:18:27.50#ibcon#end of sib2, iclass 24, count 0 2006.257.19:18:27.50#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:18:27.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:18:27.50#ibcon#[25=USB\r\n] 2006.257.19:18:27.50#ibcon#*before write, iclass 24, count 0 2006.257.19:18:27.50#ibcon#enter sib2, iclass 24, count 0 2006.257.19:18:27.50#ibcon#flushed, iclass 24, count 0 2006.257.19:18:27.50#ibcon#about to write, iclass 24, count 0 2006.257.19:18:27.50#ibcon#wrote, iclass 24, count 0 2006.257.19:18:27.50#ibcon#about to read 3, iclass 24, count 0 2006.257.19:18:27.53#ibcon#read 3, iclass 24, count 0 2006.257.19:18:27.53#ibcon#about to read 4, iclass 24, count 0 2006.257.19:18:27.53#ibcon#read 4, iclass 24, count 0 2006.257.19:18:27.53#ibcon#about to read 5, iclass 24, count 0 2006.257.19:18:27.53#ibcon#read 5, iclass 24, count 0 2006.257.19:18:27.53#ibcon#about to read 6, iclass 24, count 0 2006.257.19:18:27.53#ibcon#read 6, iclass 24, count 0 2006.257.19:18:27.53#ibcon#end of sib2, iclass 24, count 0 2006.257.19:18:27.53#ibcon#*after write, iclass 24, count 0 2006.257.19:18:27.53#ibcon#*before return 0, iclass 24, count 0 2006.257.19:18:27.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:27.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:27.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:18:27.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:18:27.53$vck44/valo=7,864.99 2006.257.19:18:27.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.19:18:27.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.19:18:27.53#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:27.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:27.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:27.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:27.53#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:18:27.53#ibcon#first serial, iclass 26, count 0 2006.257.19:18:27.53#ibcon#enter sib2, iclass 26, count 0 2006.257.19:18:27.53#ibcon#flushed, iclass 26, count 0 2006.257.19:18:27.53#ibcon#about to write, iclass 26, count 0 2006.257.19:18:27.53#ibcon#wrote, iclass 26, count 0 2006.257.19:18:27.53#ibcon#about to read 3, iclass 26, count 0 2006.257.19:18:27.55#ibcon#read 3, iclass 26, count 0 2006.257.19:18:27.55#ibcon#about to read 4, iclass 26, count 0 2006.257.19:18:27.55#ibcon#read 4, iclass 26, count 0 2006.257.19:18:27.55#ibcon#about to read 5, iclass 26, count 0 2006.257.19:18:27.55#ibcon#read 5, iclass 26, count 0 2006.257.19:18:27.55#ibcon#about to read 6, iclass 26, count 0 2006.257.19:18:27.55#ibcon#read 6, iclass 26, count 0 2006.257.19:18:27.55#ibcon#end of sib2, iclass 26, count 0 2006.257.19:18:27.55#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:18:27.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:18:27.55#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.19:18:27.55#ibcon#*before write, iclass 26, count 0 2006.257.19:18:27.55#ibcon#enter sib2, iclass 26, count 0 2006.257.19:18:27.55#ibcon#flushed, iclass 26, count 0 2006.257.19:18:27.55#ibcon#about to write, iclass 26, count 0 2006.257.19:18:27.55#ibcon#wrote, iclass 26, count 0 2006.257.19:18:27.55#ibcon#about to read 3, iclass 26, count 0 2006.257.19:18:27.59#ibcon#read 3, iclass 26, count 0 2006.257.19:18:27.59#ibcon#about to read 4, iclass 26, count 0 2006.257.19:18:27.59#ibcon#read 4, iclass 26, count 0 2006.257.19:18:27.59#ibcon#about to read 5, iclass 26, count 0 2006.257.19:18:27.59#ibcon#read 5, iclass 26, count 0 2006.257.19:18:27.59#ibcon#about to read 6, iclass 26, count 0 2006.257.19:18:27.59#ibcon#read 6, iclass 26, count 0 2006.257.19:18:27.59#ibcon#end of sib2, iclass 26, count 0 2006.257.19:18:27.59#ibcon#*after write, iclass 26, count 0 2006.257.19:18:27.59#ibcon#*before return 0, iclass 26, count 0 2006.257.19:18:27.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:27.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:27.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:18:27.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:18:27.59$vck44/va=7,4 2006.257.19:18:27.59#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.19:18:27.59#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.19:18:27.59#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:27.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:27.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:27.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:27.65#ibcon#enter wrdev, iclass 28, count 2 2006.257.19:18:27.65#ibcon#first serial, iclass 28, count 2 2006.257.19:18:27.65#ibcon#enter sib2, iclass 28, count 2 2006.257.19:18:27.65#ibcon#flushed, iclass 28, count 2 2006.257.19:18:27.65#ibcon#about to write, iclass 28, count 2 2006.257.19:18:27.65#ibcon#wrote, iclass 28, count 2 2006.257.19:18:27.65#ibcon#about to read 3, iclass 28, count 2 2006.257.19:18:27.67#ibcon#read 3, iclass 28, count 2 2006.257.19:18:27.67#ibcon#about to read 4, iclass 28, count 2 2006.257.19:18:27.67#ibcon#read 4, iclass 28, count 2 2006.257.19:18:27.67#ibcon#about to read 5, iclass 28, count 2 2006.257.19:18:27.67#ibcon#read 5, iclass 28, count 2 2006.257.19:18:27.67#ibcon#about to read 6, iclass 28, count 2 2006.257.19:18:27.67#ibcon#read 6, iclass 28, count 2 2006.257.19:18:27.67#ibcon#end of sib2, iclass 28, count 2 2006.257.19:18:27.67#ibcon#*mode == 0, iclass 28, count 2 2006.257.19:18:27.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.19:18:27.67#ibcon#[25=AT07-04\r\n] 2006.257.19:18:27.67#ibcon#*before write, iclass 28, count 2 2006.257.19:18:27.67#ibcon#enter sib2, iclass 28, count 2 2006.257.19:18:27.67#ibcon#flushed, iclass 28, count 2 2006.257.19:18:27.67#ibcon#about to write, iclass 28, count 2 2006.257.19:18:27.67#ibcon#wrote, iclass 28, count 2 2006.257.19:18:27.67#ibcon#about to read 3, iclass 28, count 2 2006.257.19:18:27.70#ibcon#read 3, iclass 28, count 2 2006.257.19:18:27.70#ibcon#about to read 4, iclass 28, count 2 2006.257.19:18:27.70#ibcon#read 4, iclass 28, count 2 2006.257.19:18:27.70#ibcon#about to read 5, iclass 28, count 2 2006.257.19:18:27.70#ibcon#read 5, iclass 28, count 2 2006.257.19:18:27.70#ibcon#about to read 6, iclass 28, count 2 2006.257.19:18:27.70#ibcon#read 6, iclass 28, count 2 2006.257.19:18:27.70#ibcon#end of sib2, iclass 28, count 2 2006.257.19:18:27.70#ibcon#*after write, iclass 28, count 2 2006.257.19:18:27.70#ibcon#*before return 0, iclass 28, count 2 2006.257.19:18:27.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:27.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:27.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.19:18:27.70#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:27.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:27.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:27.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:27.82#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:18:27.82#ibcon#first serial, iclass 28, count 0 2006.257.19:18:27.82#ibcon#enter sib2, iclass 28, count 0 2006.257.19:18:27.82#ibcon#flushed, iclass 28, count 0 2006.257.19:18:27.82#ibcon#about to write, iclass 28, count 0 2006.257.19:18:27.82#ibcon#wrote, iclass 28, count 0 2006.257.19:18:27.82#ibcon#about to read 3, iclass 28, count 0 2006.257.19:18:27.84#ibcon#read 3, iclass 28, count 0 2006.257.19:18:27.84#ibcon#about to read 4, iclass 28, count 0 2006.257.19:18:27.84#ibcon#read 4, iclass 28, count 0 2006.257.19:18:27.84#ibcon#about to read 5, iclass 28, count 0 2006.257.19:18:27.84#ibcon#read 5, iclass 28, count 0 2006.257.19:18:27.84#ibcon#about to read 6, iclass 28, count 0 2006.257.19:18:27.84#ibcon#read 6, iclass 28, count 0 2006.257.19:18:27.84#ibcon#end of sib2, iclass 28, count 0 2006.257.19:18:27.84#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:18:27.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:18:27.84#ibcon#[25=USB\r\n] 2006.257.19:18:27.84#ibcon#*before write, iclass 28, count 0 2006.257.19:18:27.84#ibcon#enter sib2, iclass 28, count 0 2006.257.19:18:27.84#ibcon#flushed, iclass 28, count 0 2006.257.19:18:27.84#ibcon#about to write, iclass 28, count 0 2006.257.19:18:27.84#ibcon#wrote, iclass 28, count 0 2006.257.19:18:27.84#ibcon#about to read 3, iclass 28, count 0 2006.257.19:18:27.87#ibcon#read 3, iclass 28, count 0 2006.257.19:18:27.87#ibcon#about to read 4, iclass 28, count 0 2006.257.19:18:27.87#ibcon#read 4, iclass 28, count 0 2006.257.19:18:27.87#ibcon#about to read 5, iclass 28, count 0 2006.257.19:18:27.87#ibcon#read 5, iclass 28, count 0 2006.257.19:18:27.87#ibcon#about to read 6, iclass 28, count 0 2006.257.19:18:27.87#ibcon#read 6, iclass 28, count 0 2006.257.19:18:27.87#ibcon#end of sib2, iclass 28, count 0 2006.257.19:18:27.87#ibcon#*after write, iclass 28, count 0 2006.257.19:18:27.87#ibcon#*before return 0, iclass 28, count 0 2006.257.19:18:27.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:27.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:27.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:18:27.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:18:27.87$vck44/valo=8,884.99 2006.257.19:18:27.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.19:18:27.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.19:18:27.87#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:27.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:27.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:27.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:27.87#ibcon#enter wrdev, iclass 30, count 0 2006.257.19:18:27.87#ibcon#first serial, iclass 30, count 0 2006.257.19:18:27.87#ibcon#enter sib2, iclass 30, count 0 2006.257.19:18:27.87#ibcon#flushed, iclass 30, count 0 2006.257.19:18:27.87#ibcon#about to write, iclass 30, count 0 2006.257.19:18:27.87#ibcon#wrote, iclass 30, count 0 2006.257.19:18:27.87#ibcon#about to read 3, iclass 30, count 0 2006.257.19:18:27.89#ibcon#read 3, iclass 30, count 0 2006.257.19:18:27.89#ibcon#about to read 4, iclass 30, count 0 2006.257.19:18:27.89#ibcon#read 4, iclass 30, count 0 2006.257.19:18:27.89#ibcon#about to read 5, iclass 30, count 0 2006.257.19:18:27.89#ibcon#read 5, iclass 30, count 0 2006.257.19:18:27.89#ibcon#about to read 6, iclass 30, count 0 2006.257.19:18:27.89#ibcon#read 6, iclass 30, count 0 2006.257.19:18:27.89#ibcon#end of sib2, iclass 30, count 0 2006.257.19:18:27.89#ibcon#*mode == 0, iclass 30, count 0 2006.257.19:18:27.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.19:18:27.89#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.19:18:27.89#ibcon#*before write, iclass 30, count 0 2006.257.19:18:27.89#ibcon#enter sib2, iclass 30, count 0 2006.257.19:18:27.89#ibcon#flushed, iclass 30, count 0 2006.257.19:18:27.89#ibcon#about to write, iclass 30, count 0 2006.257.19:18:27.89#ibcon#wrote, iclass 30, count 0 2006.257.19:18:27.89#ibcon#about to read 3, iclass 30, count 0 2006.257.19:18:27.93#ibcon#read 3, iclass 30, count 0 2006.257.19:18:27.93#ibcon#about to read 4, iclass 30, count 0 2006.257.19:18:27.93#ibcon#read 4, iclass 30, count 0 2006.257.19:18:27.93#ibcon#about to read 5, iclass 30, count 0 2006.257.19:18:27.93#ibcon#read 5, iclass 30, count 0 2006.257.19:18:27.93#ibcon#about to read 6, iclass 30, count 0 2006.257.19:18:27.93#ibcon#read 6, iclass 30, count 0 2006.257.19:18:27.93#ibcon#end of sib2, iclass 30, count 0 2006.257.19:18:27.93#ibcon#*after write, iclass 30, count 0 2006.257.19:18:27.93#ibcon#*before return 0, iclass 30, count 0 2006.257.19:18:27.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:27.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:27.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.19:18:27.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.19:18:27.93$vck44/va=8,4 2006.257.19:18:27.93#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.19:18:27.93#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.19:18:27.93#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:27.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:18:27.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:18:27.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:18:27.99#ibcon#enter wrdev, iclass 32, count 2 2006.257.19:18:27.99#ibcon#first serial, iclass 32, count 2 2006.257.19:18:27.99#ibcon#enter sib2, iclass 32, count 2 2006.257.19:18:27.99#ibcon#flushed, iclass 32, count 2 2006.257.19:18:27.99#ibcon#about to write, iclass 32, count 2 2006.257.19:18:27.99#ibcon#wrote, iclass 32, count 2 2006.257.19:18:27.99#ibcon#about to read 3, iclass 32, count 2 2006.257.19:18:28.01#ibcon#read 3, iclass 32, count 2 2006.257.19:18:28.01#ibcon#about to read 4, iclass 32, count 2 2006.257.19:18:28.01#ibcon#read 4, iclass 32, count 2 2006.257.19:18:28.01#ibcon#about to read 5, iclass 32, count 2 2006.257.19:18:28.01#ibcon#read 5, iclass 32, count 2 2006.257.19:18:28.01#ibcon#about to read 6, iclass 32, count 2 2006.257.19:18:28.01#ibcon#read 6, iclass 32, count 2 2006.257.19:18:28.01#ibcon#end of sib2, iclass 32, count 2 2006.257.19:18:28.01#ibcon#*mode == 0, iclass 32, count 2 2006.257.19:18:28.01#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.19:18:28.01#ibcon#[25=AT08-04\r\n] 2006.257.19:18:28.01#ibcon#*before write, iclass 32, count 2 2006.257.19:18:28.01#ibcon#enter sib2, iclass 32, count 2 2006.257.19:18:28.01#ibcon#flushed, iclass 32, count 2 2006.257.19:18:28.01#ibcon#about to write, iclass 32, count 2 2006.257.19:18:28.01#ibcon#wrote, iclass 32, count 2 2006.257.19:18:28.01#ibcon#about to read 3, iclass 32, count 2 2006.257.19:18:28.04#ibcon#read 3, iclass 32, count 2 2006.257.19:18:28.04#ibcon#about to read 4, iclass 32, count 2 2006.257.19:18:28.04#ibcon#read 4, iclass 32, count 2 2006.257.19:18:28.04#ibcon#about to read 5, iclass 32, count 2 2006.257.19:18:28.04#ibcon#read 5, iclass 32, count 2 2006.257.19:18:28.04#ibcon#about to read 6, iclass 32, count 2 2006.257.19:18:28.04#ibcon#read 6, iclass 32, count 2 2006.257.19:18:28.04#ibcon#end of sib2, iclass 32, count 2 2006.257.19:18:28.04#ibcon#*after write, iclass 32, count 2 2006.257.19:18:28.04#ibcon#*before return 0, iclass 32, count 2 2006.257.19:18:28.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:18:28.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:18:28.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.19:18:28.04#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:28.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:18:28.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:18:28.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:18:28.16#ibcon#enter wrdev, iclass 32, count 0 2006.257.19:18:28.16#ibcon#first serial, iclass 32, count 0 2006.257.19:18:28.16#ibcon#enter sib2, iclass 32, count 0 2006.257.19:18:28.16#ibcon#flushed, iclass 32, count 0 2006.257.19:18:28.16#ibcon#about to write, iclass 32, count 0 2006.257.19:18:28.16#ibcon#wrote, iclass 32, count 0 2006.257.19:18:28.16#ibcon#about to read 3, iclass 32, count 0 2006.257.19:18:28.18#ibcon#read 3, iclass 32, count 0 2006.257.19:18:28.18#ibcon#about to read 4, iclass 32, count 0 2006.257.19:18:28.18#ibcon#read 4, iclass 32, count 0 2006.257.19:18:28.18#ibcon#about to read 5, iclass 32, count 0 2006.257.19:18:28.18#ibcon#read 5, iclass 32, count 0 2006.257.19:18:28.18#ibcon#about to read 6, iclass 32, count 0 2006.257.19:18:28.18#ibcon#read 6, iclass 32, count 0 2006.257.19:18:28.18#ibcon#end of sib2, iclass 32, count 0 2006.257.19:18:28.18#ibcon#*mode == 0, iclass 32, count 0 2006.257.19:18:28.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.19:18:28.18#ibcon#[25=USB\r\n] 2006.257.19:18:28.18#ibcon#*before write, iclass 32, count 0 2006.257.19:18:28.18#ibcon#enter sib2, iclass 32, count 0 2006.257.19:18:28.18#ibcon#flushed, iclass 32, count 0 2006.257.19:18:28.18#ibcon#about to write, iclass 32, count 0 2006.257.19:18:28.18#ibcon#wrote, iclass 32, count 0 2006.257.19:18:28.18#ibcon#about to read 3, iclass 32, count 0 2006.257.19:18:28.21#ibcon#read 3, iclass 32, count 0 2006.257.19:18:28.21#ibcon#about to read 4, iclass 32, count 0 2006.257.19:18:28.21#ibcon#read 4, iclass 32, count 0 2006.257.19:18:28.21#ibcon#about to read 5, iclass 32, count 0 2006.257.19:18:28.21#ibcon#read 5, iclass 32, count 0 2006.257.19:18:28.21#ibcon#about to read 6, iclass 32, count 0 2006.257.19:18:28.21#ibcon#read 6, iclass 32, count 0 2006.257.19:18:28.21#ibcon#end of sib2, iclass 32, count 0 2006.257.19:18:28.21#ibcon#*after write, iclass 32, count 0 2006.257.19:18:28.21#ibcon#*before return 0, iclass 32, count 0 2006.257.19:18:28.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:18:28.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:18:28.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.19:18:28.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.19:18:28.21$vck44/vblo=1,629.99 2006.257.19:18:28.21#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.19:18:28.21#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.19:18:28.21#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:28.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:18:28.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:18:28.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:18:28.21#ibcon#enter wrdev, iclass 34, count 0 2006.257.19:18:28.21#ibcon#first serial, iclass 34, count 0 2006.257.19:18:28.21#ibcon#enter sib2, iclass 34, count 0 2006.257.19:18:28.21#ibcon#flushed, iclass 34, count 0 2006.257.19:18:28.21#ibcon#about to write, iclass 34, count 0 2006.257.19:18:28.21#ibcon#wrote, iclass 34, count 0 2006.257.19:18:28.21#ibcon#about to read 3, iclass 34, count 0 2006.257.19:18:28.23#ibcon#read 3, iclass 34, count 0 2006.257.19:18:28.23#ibcon#about to read 4, iclass 34, count 0 2006.257.19:18:28.23#ibcon#read 4, iclass 34, count 0 2006.257.19:18:28.23#ibcon#about to read 5, iclass 34, count 0 2006.257.19:18:28.23#ibcon#read 5, iclass 34, count 0 2006.257.19:18:28.23#ibcon#about to read 6, iclass 34, count 0 2006.257.19:18:28.23#ibcon#read 6, iclass 34, count 0 2006.257.19:18:28.23#ibcon#end of sib2, iclass 34, count 0 2006.257.19:18:28.23#ibcon#*mode == 0, iclass 34, count 0 2006.257.19:18:28.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.19:18:28.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.19:18:28.23#ibcon#*before write, iclass 34, count 0 2006.257.19:18:28.23#ibcon#enter sib2, iclass 34, count 0 2006.257.19:18:28.23#ibcon#flushed, iclass 34, count 0 2006.257.19:18:28.23#ibcon#about to write, iclass 34, count 0 2006.257.19:18:28.23#ibcon#wrote, iclass 34, count 0 2006.257.19:18:28.23#ibcon#about to read 3, iclass 34, count 0 2006.257.19:18:28.27#ibcon#read 3, iclass 34, count 0 2006.257.19:18:28.27#ibcon#about to read 4, iclass 34, count 0 2006.257.19:18:28.27#ibcon#read 4, iclass 34, count 0 2006.257.19:18:28.27#ibcon#about to read 5, iclass 34, count 0 2006.257.19:18:28.27#ibcon#read 5, iclass 34, count 0 2006.257.19:18:28.27#ibcon#about to read 6, iclass 34, count 0 2006.257.19:18:28.27#ibcon#read 6, iclass 34, count 0 2006.257.19:18:28.27#ibcon#end of sib2, iclass 34, count 0 2006.257.19:18:28.27#ibcon#*after write, iclass 34, count 0 2006.257.19:18:28.27#ibcon#*before return 0, iclass 34, count 0 2006.257.19:18:28.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:18:28.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:18:28.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.19:18:28.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.19:18:28.27$vck44/vb=1,4 2006.257.19:18:28.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.19:18:28.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.19:18:28.27#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:28.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:18:28.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:18:28.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:18:28.27#ibcon#enter wrdev, iclass 36, count 2 2006.257.19:18:28.27#ibcon#first serial, iclass 36, count 2 2006.257.19:18:28.27#ibcon#enter sib2, iclass 36, count 2 2006.257.19:18:28.27#ibcon#flushed, iclass 36, count 2 2006.257.19:18:28.27#ibcon#about to write, iclass 36, count 2 2006.257.19:18:28.27#ibcon#wrote, iclass 36, count 2 2006.257.19:18:28.27#ibcon#about to read 3, iclass 36, count 2 2006.257.19:18:28.29#ibcon#read 3, iclass 36, count 2 2006.257.19:18:28.29#ibcon#about to read 4, iclass 36, count 2 2006.257.19:18:28.29#ibcon#read 4, iclass 36, count 2 2006.257.19:18:28.29#ibcon#about to read 5, iclass 36, count 2 2006.257.19:18:28.29#ibcon#read 5, iclass 36, count 2 2006.257.19:18:28.29#ibcon#about to read 6, iclass 36, count 2 2006.257.19:18:28.29#ibcon#read 6, iclass 36, count 2 2006.257.19:18:28.29#ibcon#end of sib2, iclass 36, count 2 2006.257.19:18:28.29#ibcon#*mode == 0, iclass 36, count 2 2006.257.19:18:28.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.19:18:28.29#ibcon#[27=AT01-04\r\n] 2006.257.19:18:28.29#ibcon#*before write, iclass 36, count 2 2006.257.19:18:28.29#ibcon#enter sib2, iclass 36, count 2 2006.257.19:18:28.29#ibcon#flushed, iclass 36, count 2 2006.257.19:18:28.29#ibcon#about to write, iclass 36, count 2 2006.257.19:18:28.29#ibcon#wrote, iclass 36, count 2 2006.257.19:18:28.29#ibcon#about to read 3, iclass 36, count 2 2006.257.19:18:28.32#ibcon#read 3, iclass 36, count 2 2006.257.19:18:28.32#ibcon#about to read 4, iclass 36, count 2 2006.257.19:18:28.32#ibcon#read 4, iclass 36, count 2 2006.257.19:18:28.32#ibcon#about to read 5, iclass 36, count 2 2006.257.19:18:28.32#ibcon#read 5, iclass 36, count 2 2006.257.19:18:28.32#ibcon#about to read 6, iclass 36, count 2 2006.257.19:18:28.32#ibcon#read 6, iclass 36, count 2 2006.257.19:18:28.32#ibcon#end of sib2, iclass 36, count 2 2006.257.19:18:28.32#ibcon#*after write, iclass 36, count 2 2006.257.19:18:28.32#ibcon#*before return 0, iclass 36, count 2 2006.257.19:18:28.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:18:28.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:18:28.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.19:18:28.32#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:28.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:18:28.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:18:28.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:18:28.44#ibcon#enter wrdev, iclass 36, count 0 2006.257.19:18:28.44#ibcon#first serial, iclass 36, count 0 2006.257.19:18:28.44#ibcon#enter sib2, iclass 36, count 0 2006.257.19:18:28.44#ibcon#flushed, iclass 36, count 0 2006.257.19:18:28.44#ibcon#about to write, iclass 36, count 0 2006.257.19:18:28.44#ibcon#wrote, iclass 36, count 0 2006.257.19:18:28.44#ibcon#about to read 3, iclass 36, count 0 2006.257.19:18:28.46#ibcon#read 3, iclass 36, count 0 2006.257.19:18:28.46#ibcon#about to read 4, iclass 36, count 0 2006.257.19:18:28.46#ibcon#read 4, iclass 36, count 0 2006.257.19:18:28.46#ibcon#about to read 5, iclass 36, count 0 2006.257.19:18:28.46#ibcon#read 5, iclass 36, count 0 2006.257.19:18:28.46#ibcon#about to read 6, iclass 36, count 0 2006.257.19:18:28.46#ibcon#read 6, iclass 36, count 0 2006.257.19:18:28.46#ibcon#end of sib2, iclass 36, count 0 2006.257.19:18:28.46#ibcon#*mode == 0, iclass 36, count 0 2006.257.19:18:28.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.19:18:28.46#ibcon#[27=USB\r\n] 2006.257.19:18:28.46#ibcon#*before write, iclass 36, count 0 2006.257.19:18:28.46#ibcon#enter sib2, iclass 36, count 0 2006.257.19:18:28.46#ibcon#flushed, iclass 36, count 0 2006.257.19:18:28.46#ibcon#about to write, iclass 36, count 0 2006.257.19:18:28.46#ibcon#wrote, iclass 36, count 0 2006.257.19:18:28.46#ibcon#about to read 3, iclass 36, count 0 2006.257.19:18:28.49#ibcon#read 3, iclass 36, count 0 2006.257.19:18:28.49#ibcon#about to read 4, iclass 36, count 0 2006.257.19:18:28.49#ibcon#read 4, iclass 36, count 0 2006.257.19:18:28.49#ibcon#about to read 5, iclass 36, count 0 2006.257.19:18:28.49#ibcon#read 5, iclass 36, count 0 2006.257.19:18:28.49#ibcon#about to read 6, iclass 36, count 0 2006.257.19:18:28.49#ibcon#read 6, iclass 36, count 0 2006.257.19:18:28.49#ibcon#end of sib2, iclass 36, count 0 2006.257.19:18:28.49#ibcon#*after write, iclass 36, count 0 2006.257.19:18:28.49#ibcon#*before return 0, iclass 36, count 0 2006.257.19:18:28.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:18:28.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:18:28.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.19:18:28.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.19:18:28.49$vck44/vblo=2,634.99 2006.257.19:18:28.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.19:18:28.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.19:18:28.49#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:28.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:28.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:28.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:28.49#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:18:28.49#ibcon#first serial, iclass 38, count 0 2006.257.19:18:28.49#ibcon#enter sib2, iclass 38, count 0 2006.257.19:18:28.49#ibcon#flushed, iclass 38, count 0 2006.257.19:18:28.49#ibcon#about to write, iclass 38, count 0 2006.257.19:18:28.49#ibcon#wrote, iclass 38, count 0 2006.257.19:18:28.49#ibcon#about to read 3, iclass 38, count 0 2006.257.19:18:28.51#ibcon#read 3, iclass 38, count 0 2006.257.19:18:28.51#ibcon#about to read 4, iclass 38, count 0 2006.257.19:18:28.51#ibcon#read 4, iclass 38, count 0 2006.257.19:18:28.51#ibcon#about to read 5, iclass 38, count 0 2006.257.19:18:28.51#ibcon#read 5, iclass 38, count 0 2006.257.19:18:28.51#ibcon#about to read 6, iclass 38, count 0 2006.257.19:18:28.51#ibcon#read 6, iclass 38, count 0 2006.257.19:18:28.51#ibcon#end of sib2, iclass 38, count 0 2006.257.19:18:28.51#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:18:28.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:18:28.51#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.19:18:28.51#ibcon#*before write, iclass 38, count 0 2006.257.19:18:28.51#ibcon#enter sib2, iclass 38, count 0 2006.257.19:18:28.51#ibcon#flushed, iclass 38, count 0 2006.257.19:18:28.51#ibcon#about to write, iclass 38, count 0 2006.257.19:18:28.51#ibcon#wrote, iclass 38, count 0 2006.257.19:18:28.51#ibcon#about to read 3, iclass 38, count 0 2006.257.19:18:28.55#ibcon#read 3, iclass 38, count 0 2006.257.19:18:28.55#ibcon#about to read 4, iclass 38, count 0 2006.257.19:18:28.55#ibcon#read 4, iclass 38, count 0 2006.257.19:18:28.55#ibcon#about to read 5, iclass 38, count 0 2006.257.19:18:28.55#ibcon#read 5, iclass 38, count 0 2006.257.19:18:28.55#ibcon#about to read 6, iclass 38, count 0 2006.257.19:18:28.55#ibcon#read 6, iclass 38, count 0 2006.257.19:18:28.55#ibcon#end of sib2, iclass 38, count 0 2006.257.19:18:28.55#ibcon#*after write, iclass 38, count 0 2006.257.19:18:28.55#ibcon#*before return 0, iclass 38, count 0 2006.257.19:18:28.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:28.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:18:28.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:18:28.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:18:28.55$vck44/vb=2,5 2006.257.19:18:28.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.19:18:28.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.19:18:28.55#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:28.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:28.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:28.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:28.61#ibcon#enter wrdev, iclass 40, count 2 2006.257.19:18:28.61#ibcon#first serial, iclass 40, count 2 2006.257.19:18:28.61#ibcon#enter sib2, iclass 40, count 2 2006.257.19:18:28.61#ibcon#flushed, iclass 40, count 2 2006.257.19:18:28.61#ibcon#about to write, iclass 40, count 2 2006.257.19:18:28.61#ibcon#wrote, iclass 40, count 2 2006.257.19:18:28.61#ibcon#about to read 3, iclass 40, count 2 2006.257.19:18:28.63#ibcon#read 3, iclass 40, count 2 2006.257.19:18:28.63#ibcon#about to read 4, iclass 40, count 2 2006.257.19:18:28.63#ibcon#read 4, iclass 40, count 2 2006.257.19:18:28.63#ibcon#about to read 5, iclass 40, count 2 2006.257.19:18:28.63#ibcon#read 5, iclass 40, count 2 2006.257.19:18:28.63#ibcon#about to read 6, iclass 40, count 2 2006.257.19:18:28.63#ibcon#read 6, iclass 40, count 2 2006.257.19:18:28.63#ibcon#end of sib2, iclass 40, count 2 2006.257.19:18:28.63#ibcon#*mode == 0, iclass 40, count 2 2006.257.19:18:28.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.19:18:28.63#ibcon#[27=AT02-05\r\n] 2006.257.19:18:28.63#ibcon#*before write, iclass 40, count 2 2006.257.19:18:28.63#ibcon#enter sib2, iclass 40, count 2 2006.257.19:18:28.63#ibcon#flushed, iclass 40, count 2 2006.257.19:18:28.63#ibcon#about to write, iclass 40, count 2 2006.257.19:18:28.63#ibcon#wrote, iclass 40, count 2 2006.257.19:18:28.63#ibcon#about to read 3, iclass 40, count 2 2006.257.19:18:28.66#ibcon#read 3, iclass 40, count 2 2006.257.19:18:28.66#ibcon#about to read 4, iclass 40, count 2 2006.257.19:18:28.66#ibcon#read 4, iclass 40, count 2 2006.257.19:18:28.66#ibcon#about to read 5, iclass 40, count 2 2006.257.19:18:28.66#ibcon#read 5, iclass 40, count 2 2006.257.19:18:28.66#ibcon#about to read 6, iclass 40, count 2 2006.257.19:18:28.66#ibcon#read 6, iclass 40, count 2 2006.257.19:18:28.66#ibcon#end of sib2, iclass 40, count 2 2006.257.19:18:28.66#ibcon#*after write, iclass 40, count 2 2006.257.19:18:28.66#ibcon#*before return 0, iclass 40, count 2 2006.257.19:18:28.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:28.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:18:28.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.19:18:28.66#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:28.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:28.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:28.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:28.78#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:18:28.78#ibcon#first serial, iclass 40, count 0 2006.257.19:18:28.78#ibcon#enter sib2, iclass 40, count 0 2006.257.19:18:28.78#ibcon#flushed, iclass 40, count 0 2006.257.19:18:28.78#ibcon#about to write, iclass 40, count 0 2006.257.19:18:28.78#ibcon#wrote, iclass 40, count 0 2006.257.19:18:28.78#ibcon#about to read 3, iclass 40, count 0 2006.257.19:18:28.80#ibcon#read 3, iclass 40, count 0 2006.257.19:18:28.80#ibcon#about to read 4, iclass 40, count 0 2006.257.19:18:28.80#ibcon#read 4, iclass 40, count 0 2006.257.19:18:28.80#ibcon#about to read 5, iclass 40, count 0 2006.257.19:18:28.80#ibcon#read 5, iclass 40, count 0 2006.257.19:18:28.80#ibcon#about to read 6, iclass 40, count 0 2006.257.19:18:28.80#ibcon#read 6, iclass 40, count 0 2006.257.19:18:28.80#ibcon#end of sib2, iclass 40, count 0 2006.257.19:18:28.80#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:18:28.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:18:28.80#ibcon#[27=USB\r\n] 2006.257.19:18:28.80#ibcon#*before write, iclass 40, count 0 2006.257.19:18:28.80#ibcon#enter sib2, iclass 40, count 0 2006.257.19:18:28.80#ibcon#flushed, iclass 40, count 0 2006.257.19:18:28.80#ibcon#about to write, iclass 40, count 0 2006.257.19:18:28.80#ibcon#wrote, iclass 40, count 0 2006.257.19:18:28.80#ibcon#about to read 3, iclass 40, count 0 2006.257.19:18:28.83#ibcon#read 3, iclass 40, count 0 2006.257.19:18:28.83#ibcon#about to read 4, iclass 40, count 0 2006.257.19:18:28.83#ibcon#read 4, iclass 40, count 0 2006.257.19:18:28.83#ibcon#about to read 5, iclass 40, count 0 2006.257.19:18:28.83#ibcon#read 5, iclass 40, count 0 2006.257.19:18:28.83#ibcon#about to read 6, iclass 40, count 0 2006.257.19:18:28.83#ibcon#read 6, iclass 40, count 0 2006.257.19:18:28.83#ibcon#end of sib2, iclass 40, count 0 2006.257.19:18:28.83#ibcon#*after write, iclass 40, count 0 2006.257.19:18:28.83#ibcon#*before return 0, iclass 40, count 0 2006.257.19:18:28.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:28.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:18:28.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:18:28.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:18:28.83$vck44/vblo=3,649.99 2006.257.19:18:28.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.19:18:28.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.19:18:28.83#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:28.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:28.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:28.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:28.83#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:18:28.83#ibcon#first serial, iclass 4, count 0 2006.257.19:18:28.83#ibcon#enter sib2, iclass 4, count 0 2006.257.19:18:28.83#ibcon#flushed, iclass 4, count 0 2006.257.19:18:28.83#ibcon#about to write, iclass 4, count 0 2006.257.19:18:28.83#ibcon#wrote, iclass 4, count 0 2006.257.19:18:28.83#ibcon#about to read 3, iclass 4, count 0 2006.257.19:18:28.85#ibcon#read 3, iclass 4, count 0 2006.257.19:18:28.85#ibcon#about to read 4, iclass 4, count 0 2006.257.19:18:28.85#ibcon#read 4, iclass 4, count 0 2006.257.19:18:28.85#ibcon#about to read 5, iclass 4, count 0 2006.257.19:18:28.85#ibcon#read 5, iclass 4, count 0 2006.257.19:18:28.85#ibcon#about to read 6, iclass 4, count 0 2006.257.19:18:28.85#ibcon#read 6, iclass 4, count 0 2006.257.19:18:28.85#ibcon#end of sib2, iclass 4, count 0 2006.257.19:18:28.85#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:18:28.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:18:28.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.19:18:28.85#ibcon#*before write, iclass 4, count 0 2006.257.19:18:28.85#ibcon#enter sib2, iclass 4, count 0 2006.257.19:18:28.85#ibcon#flushed, iclass 4, count 0 2006.257.19:18:28.85#ibcon#about to write, iclass 4, count 0 2006.257.19:18:28.85#ibcon#wrote, iclass 4, count 0 2006.257.19:18:28.85#ibcon#about to read 3, iclass 4, count 0 2006.257.19:18:28.89#ibcon#read 3, iclass 4, count 0 2006.257.19:18:28.89#ibcon#about to read 4, iclass 4, count 0 2006.257.19:18:28.89#ibcon#read 4, iclass 4, count 0 2006.257.19:18:28.89#ibcon#about to read 5, iclass 4, count 0 2006.257.19:18:28.89#ibcon#read 5, iclass 4, count 0 2006.257.19:18:28.89#ibcon#about to read 6, iclass 4, count 0 2006.257.19:18:28.89#ibcon#read 6, iclass 4, count 0 2006.257.19:18:28.89#ibcon#end of sib2, iclass 4, count 0 2006.257.19:18:28.89#ibcon#*after write, iclass 4, count 0 2006.257.19:18:28.89#ibcon#*before return 0, iclass 4, count 0 2006.257.19:18:28.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:28.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:18:28.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:18:28.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:18:28.89$vck44/vb=3,4 2006.257.19:18:28.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.19:18:28.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.19:18:28.89#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:28.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:28.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:28.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:28.95#ibcon#enter wrdev, iclass 6, count 2 2006.257.19:18:28.95#ibcon#first serial, iclass 6, count 2 2006.257.19:18:28.95#ibcon#enter sib2, iclass 6, count 2 2006.257.19:18:28.95#ibcon#flushed, iclass 6, count 2 2006.257.19:18:28.95#ibcon#about to write, iclass 6, count 2 2006.257.19:18:28.95#ibcon#wrote, iclass 6, count 2 2006.257.19:18:28.95#ibcon#about to read 3, iclass 6, count 2 2006.257.19:18:28.97#ibcon#read 3, iclass 6, count 2 2006.257.19:18:28.97#ibcon#about to read 4, iclass 6, count 2 2006.257.19:18:28.97#ibcon#read 4, iclass 6, count 2 2006.257.19:18:28.97#ibcon#about to read 5, iclass 6, count 2 2006.257.19:18:28.97#ibcon#read 5, iclass 6, count 2 2006.257.19:18:28.97#ibcon#about to read 6, iclass 6, count 2 2006.257.19:18:28.97#ibcon#read 6, iclass 6, count 2 2006.257.19:18:28.97#ibcon#end of sib2, iclass 6, count 2 2006.257.19:18:28.97#ibcon#*mode == 0, iclass 6, count 2 2006.257.19:18:28.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.19:18:28.97#ibcon#[27=AT03-04\r\n] 2006.257.19:18:28.97#ibcon#*before write, iclass 6, count 2 2006.257.19:18:28.97#ibcon#enter sib2, iclass 6, count 2 2006.257.19:18:28.97#ibcon#flushed, iclass 6, count 2 2006.257.19:18:28.97#ibcon#about to write, iclass 6, count 2 2006.257.19:18:28.97#ibcon#wrote, iclass 6, count 2 2006.257.19:18:28.97#ibcon#about to read 3, iclass 6, count 2 2006.257.19:18:29.00#ibcon#read 3, iclass 6, count 2 2006.257.19:18:29.00#ibcon#about to read 4, iclass 6, count 2 2006.257.19:18:29.00#ibcon#read 4, iclass 6, count 2 2006.257.19:18:29.00#ibcon#about to read 5, iclass 6, count 2 2006.257.19:18:29.00#ibcon#read 5, iclass 6, count 2 2006.257.19:18:29.00#ibcon#about to read 6, iclass 6, count 2 2006.257.19:18:29.00#ibcon#read 6, iclass 6, count 2 2006.257.19:18:29.00#ibcon#end of sib2, iclass 6, count 2 2006.257.19:18:29.00#ibcon#*after write, iclass 6, count 2 2006.257.19:18:29.00#ibcon#*before return 0, iclass 6, count 2 2006.257.19:18:29.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:29.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:18:29.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.19:18:29.00#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:29.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:29.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:29.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:29.12#ibcon#enter wrdev, iclass 6, count 0 2006.257.19:18:29.12#ibcon#first serial, iclass 6, count 0 2006.257.19:18:29.12#ibcon#enter sib2, iclass 6, count 0 2006.257.19:18:29.12#ibcon#flushed, iclass 6, count 0 2006.257.19:18:29.12#ibcon#about to write, iclass 6, count 0 2006.257.19:18:29.12#ibcon#wrote, iclass 6, count 0 2006.257.19:18:29.12#ibcon#about to read 3, iclass 6, count 0 2006.257.19:18:29.14#ibcon#read 3, iclass 6, count 0 2006.257.19:18:29.14#ibcon#about to read 4, iclass 6, count 0 2006.257.19:18:29.14#ibcon#read 4, iclass 6, count 0 2006.257.19:18:29.14#ibcon#about to read 5, iclass 6, count 0 2006.257.19:18:29.14#ibcon#read 5, iclass 6, count 0 2006.257.19:18:29.14#ibcon#about to read 6, iclass 6, count 0 2006.257.19:18:29.14#ibcon#read 6, iclass 6, count 0 2006.257.19:18:29.14#ibcon#end of sib2, iclass 6, count 0 2006.257.19:18:29.14#ibcon#*mode == 0, iclass 6, count 0 2006.257.19:18:29.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.19:18:29.14#ibcon#[27=USB\r\n] 2006.257.19:18:29.14#ibcon#*before write, iclass 6, count 0 2006.257.19:18:29.14#ibcon#enter sib2, iclass 6, count 0 2006.257.19:18:29.14#ibcon#flushed, iclass 6, count 0 2006.257.19:18:29.14#ibcon#about to write, iclass 6, count 0 2006.257.19:18:29.14#ibcon#wrote, iclass 6, count 0 2006.257.19:18:29.14#ibcon#about to read 3, iclass 6, count 0 2006.257.19:18:29.17#ibcon#read 3, iclass 6, count 0 2006.257.19:18:29.17#ibcon#about to read 4, iclass 6, count 0 2006.257.19:18:29.17#ibcon#read 4, iclass 6, count 0 2006.257.19:18:29.17#ibcon#about to read 5, iclass 6, count 0 2006.257.19:18:29.17#ibcon#read 5, iclass 6, count 0 2006.257.19:18:29.17#ibcon#about to read 6, iclass 6, count 0 2006.257.19:18:29.17#ibcon#read 6, iclass 6, count 0 2006.257.19:18:29.17#ibcon#end of sib2, iclass 6, count 0 2006.257.19:18:29.17#ibcon#*after write, iclass 6, count 0 2006.257.19:18:29.17#ibcon#*before return 0, iclass 6, count 0 2006.257.19:18:29.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:29.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:18:29.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.19:18:29.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.19:18:29.17$vck44/vblo=4,679.99 2006.257.19:18:29.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.19:18:29.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.19:18:29.17#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:29.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:29.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:29.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:29.17#ibcon#enter wrdev, iclass 10, count 0 2006.257.19:18:29.17#ibcon#first serial, iclass 10, count 0 2006.257.19:18:29.17#ibcon#enter sib2, iclass 10, count 0 2006.257.19:18:29.17#ibcon#flushed, iclass 10, count 0 2006.257.19:18:29.17#ibcon#about to write, iclass 10, count 0 2006.257.19:18:29.17#ibcon#wrote, iclass 10, count 0 2006.257.19:18:29.17#ibcon#about to read 3, iclass 10, count 0 2006.257.19:18:29.19#ibcon#read 3, iclass 10, count 0 2006.257.19:18:29.19#ibcon#about to read 4, iclass 10, count 0 2006.257.19:18:29.19#ibcon#read 4, iclass 10, count 0 2006.257.19:18:29.19#ibcon#about to read 5, iclass 10, count 0 2006.257.19:18:29.19#ibcon#read 5, iclass 10, count 0 2006.257.19:18:29.19#ibcon#about to read 6, iclass 10, count 0 2006.257.19:18:29.19#ibcon#read 6, iclass 10, count 0 2006.257.19:18:29.19#ibcon#end of sib2, iclass 10, count 0 2006.257.19:18:29.19#ibcon#*mode == 0, iclass 10, count 0 2006.257.19:18:29.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.19:18:29.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.19:18:29.19#ibcon#*before write, iclass 10, count 0 2006.257.19:18:29.19#ibcon#enter sib2, iclass 10, count 0 2006.257.19:18:29.19#ibcon#flushed, iclass 10, count 0 2006.257.19:18:29.19#ibcon#about to write, iclass 10, count 0 2006.257.19:18:29.19#ibcon#wrote, iclass 10, count 0 2006.257.19:18:29.19#ibcon#about to read 3, iclass 10, count 0 2006.257.19:18:29.23#ibcon#read 3, iclass 10, count 0 2006.257.19:18:29.23#ibcon#about to read 4, iclass 10, count 0 2006.257.19:18:29.23#ibcon#read 4, iclass 10, count 0 2006.257.19:18:29.23#ibcon#about to read 5, iclass 10, count 0 2006.257.19:18:29.23#ibcon#read 5, iclass 10, count 0 2006.257.19:18:29.23#ibcon#about to read 6, iclass 10, count 0 2006.257.19:18:29.23#ibcon#read 6, iclass 10, count 0 2006.257.19:18:29.23#ibcon#end of sib2, iclass 10, count 0 2006.257.19:18:29.23#ibcon#*after write, iclass 10, count 0 2006.257.19:18:29.23#ibcon#*before return 0, iclass 10, count 0 2006.257.19:18:29.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:29.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:18:29.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.19:18:29.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.19:18:29.23$vck44/vb=4,5 2006.257.19:18:29.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.19:18:29.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.19:18:29.23#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:29.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:29.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:29.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:29.29#ibcon#enter wrdev, iclass 12, count 2 2006.257.19:18:29.29#ibcon#first serial, iclass 12, count 2 2006.257.19:18:29.29#ibcon#enter sib2, iclass 12, count 2 2006.257.19:18:29.29#ibcon#flushed, iclass 12, count 2 2006.257.19:18:29.29#ibcon#about to write, iclass 12, count 2 2006.257.19:18:29.29#ibcon#wrote, iclass 12, count 2 2006.257.19:18:29.29#ibcon#about to read 3, iclass 12, count 2 2006.257.19:18:29.31#ibcon#read 3, iclass 12, count 2 2006.257.19:18:29.31#ibcon#about to read 4, iclass 12, count 2 2006.257.19:18:29.31#ibcon#read 4, iclass 12, count 2 2006.257.19:18:29.31#ibcon#about to read 5, iclass 12, count 2 2006.257.19:18:29.31#ibcon#read 5, iclass 12, count 2 2006.257.19:18:29.31#ibcon#about to read 6, iclass 12, count 2 2006.257.19:18:29.31#ibcon#read 6, iclass 12, count 2 2006.257.19:18:29.31#ibcon#end of sib2, iclass 12, count 2 2006.257.19:18:29.31#ibcon#*mode == 0, iclass 12, count 2 2006.257.19:18:29.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.19:18:29.31#ibcon#[27=AT04-05\r\n] 2006.257.19:18:29.31#ibcon#*before write, iclass 12, count 2 2006.257.19:18:29.31#ibcon#enter sib2, iclass 12, count 2 2006.257.19:18:29.31#ibcon#flushed, iclass 12, count 2 2006.257.19:18:29.31#ibcon#about to write, iclass 12, count 2 2006.257.19:18:29.31#ibcon#wrote, iclass 12, count 2 2006.257.19:18:29.31#ibcon#about to read 3, iclass 12, count 2 2006.257.19:18:29.34#ibcon#read 3, iclass 12, count 2 2006.257.19:18:29.34#ibcon#about to read 4, iclass 12, count 2 2006.257.19:18:29.34#ibcon#read 4, iclass 12, count 2 2006.257.19:18:29.34#ibcon#about to read 5, iclass 12, count 2 2006.257.19:18:29.34#ibcon#read 5, iclass 12, count 2 2006.257.19:18:29.34#ibcon#about to read 6, iclass 12, count 2 2006.257.19:18:29.34#ibcon#read 6, iclass 12, count 2 2006.257.19:18:29.34#ibcon#end of sib2, iclass 12, count 2 2006.257.19:18:29.34#ibcon#*after write, iclass 12, count 2 2006.257.19:18:29.34#ibcon#*before return 0, iclass 12, count 2 2006.257.19:18:29.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:29.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:18:29.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.19:18:29.34#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:29.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:29.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:29.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:29.46#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:18:29.46#ibcon#first serial, iclass 12, count 0 2006.257.19:18:29.46#ibcon#enter sib2, iclass 12, count 0 2006.257.19:18:29.46#ibcon#flushed, iclass 12, count 0 2006.257.19:18:29.46#ibcon#about to write, iclass 12, count 0 2006.257.19:18:29.46#ibcon#wrote, iclass 12, count 0 2006.257.19:18:29.46#ibcon#about to read 3, iclass 12, count 0 2006.257.19:18:29.48#ibcon#read 3, iclass 12, count 0 2006.257.19:18:29.48#ibcon#about to read 4, iclass 12, count 0 2006.257.19:18:29.48#ibcon#read 4, iclass 12, count 0 2006.257.19:18:29.48#ibcon#about to read 5, iclass 12, count 0 2006.257.19:18:29.48#ibcon#read 5, iclass 12, count 0 2006.257.19:18:29.48#ibcon#about to read 6, iclass 12, count 0 2006.257.19:18:29.48#ibcon#read 6, iclass 12, count 0 2006.257.19:18:29.48#ibcon#end of sib2, iclass 12, count 0 2006.257.19:18:29.48#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:18:29.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:18:29.48#ibcon#[27=USB\r\n] 2006.257.19:18:29.48#ibcon#*before write, iclass 12, count 0 2006.257.19:18:29.48#ibcon#enter sib2, iclass 12, count 0 2006.257.19:18:29.48#ibcon#flushed, iclass 12, count 0 2006.257.19:18:29.48#ibcon#about to write, iclass 12, count 0 2006.257.19:18:29.48#ibcon#wrote, iclass 12, count 0 2006.257.19:18:29.48#ibcon#about to read 3, iclass 12, count 0 2006.257.19:18:29.51#ibcon#read 3, iclass 12, count 0 2006.257.19:18:29.51#ibcon#about to read 4, iclass 12, count 0 2006.257.19:18:29.51#ibcon#read 4, iclass 12, count 0 2006.257.19:18:29.51#ibcon#about to read 5, iclass 12, count 0 2006.257.19:18:29.51#ibcon#read 5, iclass 12, count 0 2006.257.19:18:29.51#ibcon#about to read 6, iclass 12, count 0 2006.257.19:18:29.51#ibcon#read 6, iclass 12, count 0 2006.257.19:18:29.51#ibcon#end of sib2, iclass 12, count 0 2006.257.19:18:29.51#ibcon#*after write, iclass 12, count 0 2006.257.19:18:29.51#ibcon#*before return 0, iclass 12, count 0 2006.257.19:18:29.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:29.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:18:29.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:18:29.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:18:29.51$vck44/vblo=5,709.99 2006.257.19:18:29.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.19:18:29.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.19:18:29.51#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:29.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:29.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:29.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:29.51#ibcon#enter wrdev, iclass 14, count 0 2006.257.19:18:29.51#ibcon#first serial, iclass 14, count 0 2006.257.19:18:29.51#ibcon#enter sib2, iclass 14, count 0 2006.257.19:18:29.51#ibcon#flushed, iclass 14, count 0 2006.257.19:18:29.51#ibcon#about to write, iclass 14, count 0 2006.257.19:18:29.51#ibcon#wrote, iclass 14, count 0 2006.257.19:18:29.51#ibcon#about to read 3, iclass 14, count 0 2006.257.19:18:29.53#ibcon#read 3, iclass 14, count 0 2006.257.19:18:29.53#ibcon#about to read 4, iclass 14, count 0 2006.257.19:18:29.53#ibcon#read 4, iclass 14, count 0 2006.257.19:18:29.53#ibcon#about to read 5, iclass 14, count 0 2006.257.19:18:29.53#ibcon#read 5, iclass 14, count 0 2006.257.19:18:29.53#ibcon#about to read 6, iclass 14, count 0 2006.257.19:18:29.53#ibcon#read 6, iclass 14, count 0 2006.257.19:18:29.53#ibcon#end of sib2, iclass 14, count 0 2006.257.19:18:29.53#ibcon#*mode == 0, iclass 14, count 0 2006.257.19:18:29.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.19:18:29.53#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.19:18:29.53#ibcon#*before write, iclass 14, count 0 2006.257.19:18:29.53#ibcon#enter sib2, iclass 14, count 0 2006.257.19:18:29.53#ibcon#flushed, iclass 14, count 0 2006.257.19:18:29.53#ibcon#about to write, iclass 14, count 0 2006.257.19:18:29.53#ibcon#wrote, iclass 14, count 0 2006.257.19:18:29.53#ibcon#about to read 3, iclass 14, count 0 2006.257.19:18:29.57#ibcon#read 3, iclass 14, count 0 2006.257.19:18:29.57#ibcon#about to read 4, iclass 14, count 0 2006.257.19:18:29.57#ibcon#read 4, iclass 14, count 0 2006.257.19:18:29.57#ibcon#about to read 5, iclass 14, count 0 2006.257.19:18:29.57#ibcon#read 5, iclass 14, count 0 2006.257.19:18:29.57#ibcon#about to read 6, iclass 14, count 0 2006.257.19:18:29.57#ibcon#read 6, iclass 14, count 0 2006.257.19:18:29.57#ibcon#end of sib2, iclass 14, count 0 2006.257.19:18:29.57#ibcon#*after write, iclass 14, count 0 2006.257.19:18:29.57#ibcon#*before return 0, iclass 14, count 0 2006.257.19:18:29.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:29.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:18:29.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.19:18:29.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.19:18:29.57$vck44/vb=5,4 2006.257.19:18:29.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.19:18:29.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.19:18:29.57#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:29.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:29.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:29.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:29.63#ibcon#enter wrdev, iclass 16, count 2 2006.257.19:18:29.63#ibcon#first serial, iclass 16, count 2 2006.257.19:18:29.63#ibcon#enter sib2, iclass 16, count 2 2006.257.19:18:29.63#ibcon#flushed, iclass 16, count 2 2006.257.19:18:29.63#ibcon#about to write, iclass 16, count 2 2006.257.19:18:29.63#ibcon#wrote, iclass 16, count 2 2006.257.19:18:29.63#ibcon#about to read 3, iclass 16, count 2 2006.257.19:18:29.65#ibcon#read 3, iclass 16, count 2 2006.257.19:18:29.65#ibcon#about to read 4, iclass 16, count 2 2006.257.19:18:29.65#ibcon#read 4, iclass 16, count 2 2006.257.19:18:29.65#ibcon#about to read 5, iclass 16, count 2 2006.257.19:18:29.65#ibcon#read 5, iclass 16, count 2 2006.257.19:18:29.65#ibcon#about to read 6, iclass 16, count 2 2006.257.19:18:29.65#ibcon#read 6, iclass 16, count 2 2006.257.19:18:29.65#ibcon#end of sib2, iclass 16, count 2 2006.257.19:18:29.65#ibcon#*mode == 0, iclass 16, count 2 2006.257.19:18:29.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.19:18:29.65#ibcon#[27=AT05-04\r\n] 2006.257.19:18:29.65#ibcon#*before write, iclass 16, count 2 2006.257.19:18:29.65#ibcon#enter sib2, iclass 16, count 2 2006.257.19:18:29.65#ibcon#flushed, iclass 16, count 2 2006.257.19:18:29.65#ibcon#about to write, iclass 16, count 2 2006.257.19:18:29.65#ibcon#wrote, iclass 16, count 2 2006.257.19:18:29.65#ibcon#about to read 3, iclass 16, count 2 2006.257.19:18:29.68#ibcon#read 3, iclass 16, count 2 2006.257.19:18:29.68#ibcon#about to read 4, iclass 16, count 2 2006.257.19:18:29.68#ibcon#read 4, iclass 16, count 2 2006.257.19:18:29.68#ibcon#about to read 5, iclass 16, count 2 2006.257.19:18:29.68#ibcon#read 5, iclass 16, count 2 2006.257.19:18:29.68#ibcon#about to read 6, iclass 16, count 2 2006.257.19:18:29.68#ibcon#read 6, iclass 16, count 2 2006.257.19:18:29.68#ibcon#end of sib2, iclass 16, count 2 2006.257.19:18:29.68#ibcon#*after write, iclass 16, count 2 2006.257.19:18:29.68#ibcon#*before return 0, iclass 16, count 2 2006.257.19:18:29.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:29.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:18:29.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.19:18:29.68#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:29.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:29.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:29.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:29.80#ibcon#enter wrdev, iclass 16, count 0 2006.257.19:18:29.80#ibcon#first serial, iclass 16, count 0 2006.257.19:18:29.80#ibcon#enter sib2, iclass 16, count 0 2006.257.19:18:29.80#ibcon#flushed, iclass 16, count 0 2006.257.19:18:29.80#ibcon#about to write, iclass 16, count 0 2006.257.19:18:29.80#ibcon#wrote, iclass 16, count 0 2006.257.19:18:29.80#ibcon#about to read 3, iclass 16, count 0 2006.257.19:18:29.82#ibcon#read 3, iclass 16, count 0 2006.257.19:18:29.82#ibcon#about to read 4, iclass 16, count 0 2006.257.19:18:29.82#ibcon#read 4, iclass 16, count 0 2006.257.19:18:29.82#ibcon#about to read 5, iclass 16, count 0 2006.257.19:18:29.82#ibcon#read 5, iclass 16, count 0 2006.257.19:18:29.82#ibcon#about to read 6, iclass 16, count 0 2006.257.19:18:29.82#ibcon#read 6, iclass 16, count 0 2006.257.19:18:29.82#ibcon#end of sib2, iclass 16, count 0 2006.257.19:18:29.82#ibcon#*mode == 0, iclass 16, count 0 2006.257.19:18:29.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.19:18:29.82#ibcon#[27=USB\r\n] 2006.257.19:18:29.82#ibcon#*before write, iclass 16, count 0 2006.257.19:18:29.82#ibcon#enter sib2, iclass 16, count 0 2006.257.19:18:29.82#ibcon#flushed, iclass 16, count 0 2006.257.19:18:29.82#ibcon#about to write, iclass 16, count 0 2006.257.19:18:29.82#ibcon#wrote, iclass 16, count 0 2006.257.19:18:29.82#ibcon#about to read 3, iclass 16, count 0 2006.257.19:18:29.85#ibcon#read 3, iclass 16, count 0 2006.257.19:18:29.85#ibcon#about to read 4, iclass 16, count 0 2006.257.19:18:29.85#ibcon#read 4, iclass 16, count 0 2006.257.19:18:29.85#ibcon#about to read 5, iclass 16, count 0 2006.257.19:18:29.85#ibcon#read 5, iclass 16, count 0 2006.257.19:18:29.85#ibcon#about to read 6, iclass 16, count 0 2006.257.19:18:29.85#ibcon#read 6, iclass 16, count 0 2006.257.19:18:29.85#ibcon#end of sib2, iclass 16, count 0 2006.257.19:18:29.85#ibcon#*after write, iclass 16, count 0 2006.257.19:18:29.85#ibcon#*before return 0, iclass 16, count 0 2006.257.19:18:29.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:29.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:18:29.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.19:18:29.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.19:18:29.85$vck44/vblo=6,719.99 2006.257.19:18:29.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.19:18:29.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.19:18:29.85#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:29.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:29.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:29.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:29.85#ibcon#enter wrdev, iclass 18, count 0 2006.257.19:18:29.85#ibcon#first serial, iclass 18, count 0 2006.257.19:18:29.85#ibcon#enter sib2, iclass 18, count 0 2006.257.19:18:29.85#ibcon#flushed, iclass 18, count 0 2006.257.19:18:29.85#ibcon#about to write, iclass 18, count 0 2006.257.19:18:29.85#ibcon#wrote, iclass 18, count 0 2006.257.19:18:29.85#ibcon#about to read 3, iclass 18, count 0 2006.257.19:18:29.87#ibcon#read 3, iclass 18, count 0 2006.257.19:18:29.87#ibcon#about to read 4, iclass 18, count 0 2006.257.19:18:29.87#ibcon#read 4, iclass 18, count 0 2006.257.19:18:29.87#ibcon#about to read 5, iclass 18, count 0 2006.257.19:18:29.87#ibcon#read 5, iclass 18, count 0 2006.257.19:18:29.87#ibcon#about to read 6, iclass 18, count 0 2006.257.19:18:29.87#ibcon#read 6, iclass 18, count 0 2006.257.19:18:29.87#ibcon#end of sib2, iclass 18, count 0 2006.257.19:18:29.87#ibcon#*mode == 0, iclass 18, count 0 2006.257.19:18:29.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.19:18:29.87#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.19:18:29.87#ibcon#*before write, iclass 18, count 0 2006.257.19:18:29.87#ibcon#enter sib2, iclass 18, count 0 2006.257.19:18:29.87#ibcon#flushed, iclass 18, count 0 2006.257.19:18:29.87#ibcon#about to write, iclass 18, count 0 2006.257.19:18:29.87#ibcon#wrote, iclass 18, count 0 2006.257.19:18:29.87#ibcon#about to read 3, iclass 18, count 0 2006.257.19:18:29.91#ibcon#read 3, iclass 18, count 0 2006.257.19:18:29.91#ibcon#about to read 4, iclass 18, count 0 2006.257.19:18:29.91#ibcon#read 4, iclass 18, count 0 2006.257.19:18:29.91#ibcon#about to read 5, iclass 18, count 0 2006.257.19:18:29.91#ibcon#read 5, iclass 18, count 0 2006.257.19:18:29.91#ibcon#about to read 6, iclass 18, count 0 2006.257.19:18:29.91#ibcon#read 6, iclass 18, count 0 2006.257.19:18:29.91#ibcon#end of sib2, iclass 18, count 0 2006.257.19:18:29.91#ibcon#*after write, iclass 18, count 0 2006.257.19:18:29.91#ibcon#*before return 0, iclass 18, count 0 2006.257.19:18:29.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:29.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:18:29.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.19:18:29.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.19:18:29.91$vck44/vb=6,4 2006.257.19:18:29.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.19:18:29.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.19:18:29.91#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:29.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:29.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:29.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:29.97#ibcon#enter wrdev, iclass 20, count 2 2006.257.19:18:29.97#ibcon#first serial, iclass 20, count 2 2006.257.19:18:29.97#ibcon#enter sib2, iclass 20, count 2 2006.257.19:18:29.97#ibcon#flushed, iclass 20, count 2 2006.257.19:18:29.97#ibcon#about to write, iclass 20, count 2 2006.257.19:18:29.97#ibcon#wrote, iclass 20, count 2 2006.257.19:18:29.97#ibcon#about to read 3, iclass 20, count 2 2006.257.19:18:29.99#ibcon#read 3, iclass 20, count 2 2006.257.19:18:29.99#ibcon#about to read 4, iclass 20, count 2 2006.257.19:18:29.99#ibcon#read 4, iclass 20, count 2 2006.257.19:18:29.99#ibcon#about to read 5, iclass 20, count 2 2006.257.19:18:29.99#ibcon#read 5, iclass 20, count 2 2006.257.19:18:29.99#ibcon#about to read 6, iclass 20, count 2 2006.257.19:18:29.99#ibcon#read 6, iclass 20, count 2 2006.257.19:18:29.99#ibcon#end of sib2, iclass 20, count 2 2006.257.19:18:29.99#ibcon#*mode == 0, iclass 20, count 2 2006.257.19:18:29.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.19:18:29.99#ibcon#[27=AT06-04\r\n] 2006.257.19:18:29.99#ibcon#*before write, iclass 20, count 2 2006.257.19:18:29.99#ibcon#enter sib2, iclass 20, count 2 2006.257.19:18:29.99#ibcon#flushed, iclass 20, count 2 2006.257.19:18:29.99#ibcon#about to write, iclass 20, count 2 2006.257.19:18:29.99#ibcon#wrote, iclass 20, count 2 2006.257.19:18:29.99#ibcon#about to read 3, iclass 20, count 2 2006.257.19:18:30.02#ibcon#read 3, iclass 20, count 2 2006.257.19:18:30.02#ibcon#about to read 4, iclass 20, count 2 2006.257.19:18:30.02#ibcon#read 4, iclass 20, count 2 2006.257.19:18:30.02#ibcon#about to read 5, iclass 20, count 2 2006.257.19:18:30.02#ibcon#read 5, iclass 20, count 2 2006.257.19:18:30.02#ibcon#about to read 6, iclass 20, count 2 2006.257.19:18:30.02#ibcon#read 6, iclass 20, count 2 2006.257.19:18:30.02#ibcon#end of sib2, iclass 20, count 2 2006.257.19:18:30.02#ibcon#*after write, iclass 20, count 2 2006.257.19:18:30.02#ibcon#*before return 0, iclass 20, count 2 2006.257.19:18:30.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:30.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:18:30.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.19:18:30.02#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:30.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:30.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:30.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:30.14#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:18:30.14#ibcon#first serial, iclass 20, count 0 2006.257.19:18:30.14#ibcon#enter sib2, iclass 20, count 0 2006.257.19:18:30.14#ibcon#flushed, iclass 20, count 0 2006.257.19:18:30.14#ibcon#about to write, iclass 20, count 0 2006.257.19:18:30.14#ibcon#wrote, iclass 20, count 0 2006.257.19:18:30.14#ibcon#about to read 3, iclass 20, count 0 2006.257.19:18:30.16#ibcon#read 3, iclass 20, count 0 2006.257.19:18:30.16#ibcon#about to read 4, iclass 20, count 0 2006.257.19:18:30.16#ibcon#read 4, iclass 20, count 0 2006.257.19:18:30.16#ibcon#about to read 5, iclass 20, count 0 2006.257.19:18:30.16#ibcon#read 5, iclass 20, count 0 2006.257.19:18:30.16#ibcon#about to read 6, iclass 20, count 0 2006.257.19:18:30.16#ibcon#read 6, iclass 20, count 0 2006.257.19:18:30.16#ibcon#end of sib2, iclass 20, count 0 2006.257.19:18:30.16#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:18:30.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:18:30.16#ibcon#[27=USB\r\n] 2006.257.19:18:30.16#ibcon#*before write, iclass 20, count 0 2006.257.19:18:30.16#ibcon#enter sib2, iclass 20, count 0 2006.257.19:18:30.16#ibcon#flushed, iclass 20, count 0 2006.257.19:18:30.16#ibcon#about to write, iclass 20, count 0 2006.257.19:18:30.16#ibcon#wrote, iclass 20, count 0 2006.257.19:18:30.16#ibcon#about to read 3, iclass 20, count 0 2006.257.19:18:30.19#ibcon#read 3, iclass 20, count 0 2006.257.19:18:30.19#ibcon#about to read 4, iclass 20, count 0 2006.257.19:18:30.19#ibcon#read 4, iclass 20, count 0 2006.257.19:18:30.19#ibcon#about to read 5, iclass 20, count 0 2006.257.19:18:30.19#ibcon#read 5, iclass 20, count 0 2006.257.19:18:30.19#ibcon#about to read 6, iclass 20, count 0 2006.257.19:18:30.19#ibcon#read 6, iclass 20, count 0 2006.257.19:18:30.19#ibcon#end of sib2, iclass 20, count 0 2006.257.19:18:30.19#ibcon#*after write, iclass 20, count 0 2006.257.19:18:30.19#ibcon#*before return 0, iclass 20, count 0 2006.257.19:18:30.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:30.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:18:30.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:18:30.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:18:30.19$vck44/vblo=7,734.99 2006.257.19:18:30.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.19:18:30.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.19:18:30.19#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:30.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:30.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:30.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:30.19#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:18:30.19#ibcon#first serial, iclass 22, count 0 2006.257.19:18:30.19#ibcon#enter sib2, iclass 22, count 0 2006.257.19:18:30.19#ibcon#flushed, iclass 22, count 0 2006.257.19:18:30.19#ibcon#about to write, iclass 22, count 0 2006.257.19:18:30.19#ibcon#wrote, iclass 22, count 0 2006.257.19:18:30.19#ibcon#about to read 3, iclass 22, count 0 2006.257.19:18:30.21#ibcon#read 3, iclass 22, count 0 2006.257.19:18:30.21#ibcon#about to read 4, iclass 22, count 0 2006.257.19:18:30.21#ibcon#read 4, iclass 22, count 0 2006.257.19:18:30.21#ibcon#about to read 5, iclass 22, count 0 2006.257.19:18:30.21#ibcon#read 5, iclass 22, count 0 2006.257.19:18:30.21#ibcon#about to read 6, iclass 22, count 0 2006.257.19:18:30.21#ibcon#read 6, iclass 22, count 0 2006.257.19:18:30.21#ibcon#end of sib2, iclass 22, count 0 2006.257.19:18:30.21#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:18:30.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:18:30.21#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.19:18:30.21#ibcon#*before write, iclass 22, count 0 2006.257.19:18:30.21#ibcon#enter sib2, iclass 22, count 0 2006.257.19:18:30.21#ibcon#flushed, iclass 22, count 0 2006.257.19:18:30.21#ibcon#about to write, iclass 22, count 0 2006.257.19:18:30.21#ibcon#wrote, iclass 22, count 0 2006.257.19:18:30.21#ibcon#about to read 3, iclass 22, count 0 2006.257.19:18:30.25#ibcon#read 3, iclass 22, count 0 2006.257.19:18:30.25#ibcon#about to read 4, iclass 22, count 0 2006.257.19:18:30.25#ibcon#read 4, iclass 22, count 0 2006.257.19:18:30.25#ibcon#about to read 5, iclass 22, count 0 2006.257.19:18:30.25#ibcon#read 5, iclass 22, count 0 2006.257.19:18:30.25#ibcon#about to read 6, iclass 22, count 0 2006.257.19:18:30.25#ibcon#read 6, iclass 22, count 0 2006.257.19:18:30.25#ibcon#end of sib2, iclass 22, count 0 2006.257.19:18:30.25#ibcon#*after write, iclass 22, count 0 2006.257.19:18:30.25#ibcon#*before return 0, iclass 22, count 0 2006.257.19:18:30.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:30.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:18:30.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:18:30.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:18:30.25$vck44/vb=7,4 2006.257.19:18:30.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.19:18:30.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.19:18:30.25#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:30.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:30.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:30.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:30.31#ibcon#enter wrdev, iclass 24, count 2 2006.257.19:18:30.31#ibcon#first serial, iclass 24, count 2 2006.257.19:18:30.31#ibcon#enter sib2, iclass 24, count 2 2006.257.19:18:30.31#ibcon#flushed, iclass 24, count 2 2006.257.19:18:30.31#ibcon#about to write, iclass 24, count 2 2006.257.19:18:30.31#ibcon#wrote, iclass 24, count 2 2006.257.19:18:30.31#ibcon#about to read 3, iclass 24, count 2 2006.257.19:18:30.33#ibcon#read 3, iclass 24, count 2 2006.257.19:18:30.33#ibcon#about to read 4, iclass 24, count 2 2006.257.19:18:30.33#ibcon#read 4, iclass 24, count 2 2006.257.19:18:30.33#ibcon#about to read 5, iclass 24, count 2 2006.257.19:18:30.33#ibcon#read 5, iclass 24, count 2 2006.257.19:18:30.33#ibcon#about to read 6, iclass 24, count 2 2006.257.19:18:30.33#ibcon#read 6, iclass 24, count 2 2006.257.19:18:30.33#ibcon#end of sib2, iclass 24, count 2 2006.257.19:18:30.33#ibcon#*mode == 0, iclass 24, count 2 2006.257.19:18:30.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.19:18:30.33#ibcon#[27=AT07-04\r\n] 2006.257.19:18:30.33#ibcon#*before write, iclass 24, count 2 2006.257.19:18:30.33#ibcon#enter sib2, iclass 24, count 2 2006.257.19:18:30.33#ibcon#flushed, iclass 24, count 2 2006.257.19:18:30.33#ibcon#about to write, iclass 24, count 2 2006.257.19:18:30.33#ibcon#wrote, iclass 24, count 2 2006.257.19:18:30.33#ibcon#about to read 3, iclass 24, count 2 2006.257.19:18:30.36#ibcon#read 3, iclass 24, count 2 2006.257.19:18:30.36#ibcon#about to read 4, iclass 24, count 2 2006.257.19:18:30.36#ibcon#read 4, iclass 24, count 2 2006.257.19:18:30.36#ibcon#about to read 5, iclass 24, count 2 2006.257.19:18:30.36#ibcon#read 5, iclass 24, count 2 2006.257.19:18:30.36#ibcon#about to read 6, iclass 24, count 2 2006.257.19:18:30.36#ibcon#read 6, iclass 24, count 2 2006.257.19:18:30.36#ibcon#end of sib2, iclass 24, count 2 2006.257.19:18:30.36#ibcon#*after write, iclass 24, count 2 2006.257.19:18:30.36#ibcon#*before return 0, iclass 24, count 2 2006.257.19:18:30.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:30.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:18:30.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.19:18:30.36#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:30.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:30.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:30.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:30.48#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:18:30.48#ibcon#first serial, iclass 24, count 0 2006.257.19:18:30.48#ibcon#enter sib2, iclass 24, count 0 2006.257.19:18:30.48#ibcon#flushed, iclass 24, count 0 2006.257.19:18:30.48#ibcon#about to write, iclass 24, count 0 2006.257.19:18:30.48#ibcon#wrote, iclass 24, count 0 2006.257.19:18:30.48#ibcon#about to read 3, iclass 24, count 0 2006.257.19:18:30.50#ibcon#read 3, iclass 24, count 0 2006.257.19:18:30.50#ibcon#about to read 4, iclass 24, count 0 2006.257.19:18:30.50#ibcon#read 4, iclass 24, count 0 2006.257.19:18:30.50#ibcon#about to read 5, iclass 24, count 0 2006.257.19:18:30.50#ibcon#read 5, iclass 24, count 0 2006.257.19:18:30.50#ibcon#about to read 6, iclass 24, count 0 2006.257.19:18:30.50#ibcon#read 6, iclass 24, count 0 2006.257.19:18:30.50#ibcon#end of sib2, iclass 24, count 0 2006.257.19:18:30.50#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:18:30.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:18:30.50#ibcon#[27=USB\r\n] 2006.257.19:18:30.50#ibcon#*before write, iclass 24, count 0 2006.257.19:18:30.50#ibcon#enter sib2, iclass 24, count 0 2006.257.19:18:30.50#ibcon#flushed, iclass 24, count 0 2006.257.19:18:30.50#ibcon#about to write, iclass 24, count 0 2006.257.19:18:30.50#ibcon#wrote, iclass 24, count 0 2006.257.19:18:30.50#ibcon#about to read 3, iclass 24, count 0 2006.257.19:18:30.53#ibcon#read 3, iclass 24, count 0 2006.257.19:18:30.53#ibcon#about to read 4, iclass 24, count 0 2006.257.19:18:30.53#ibcon#read 4, iclass 24, count 0 2006.257.19:18:30.53#ibcon#about to read 5, iclass 24, count 0 2006.257.19:18:30.53#ibcon#read 5, iclass 24, count 0 2006.257.19:18:30.53#ibcon#about to read 6, iclass 24, count 0 2006.257.19:18:30.53#ibcon#read 6, iclass 24, count 0 2006.257.19:18:30.53#ibcon#end of sib2, iclass 24, count 0 2006.257.19:18:30.53#ibcon#*after write, iclass 24, count 0 2006.257.19:18:30.53#ibcon#*before return 0, iclass 24, count 0 2006.257.19:18:30.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:30.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:18:30.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:18:30.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:18:30.53$vck44/vblo=8,744.99 2006.257.19:18:30.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.19:18:30.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.19:18:30.53#ibcon#ireg 17 cls_cnt 0 2006.257.19:18:30.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:30.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:30.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:30.53#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:18:30.53#ibcon#first serial, iclass 26, count 0 2006.257.19:18:30.53#ibcon#enter sib2, iclass 26, count 0 2006.257.19:18:30.53#ibcon#flushed, iclass 26, count 0 2006.257.19:18:30.53#ibcon#about to write, iclass 26, count 0 2006.257.19:18:30.53#ibcon#wrote, iclass 26, count 0 2006.257.19:18:30.53#ibcon#about to read 3, iclass 26, count 0 2006.257.19:18:30.55#ibcon#read 3, iclass 26, count 0 2006.257.19:18:30.55#ibcon#about to read 4, iclass 26, count 0 2006.257.19:18:30.55#ibcon#read 4, iclass 26, count 0 2006.257.19:18:30.55#ibcon#about to read 5, iclass 26, count 0 2006.257.19:18:30.55#ibcon#read 5, iclass 26, count 0 2006.257.19:18:30.55#ibcon#about to read 6, iclass 26, count 0 2006.257.19:18:30.55#ibcon#read 6, iclass 26, count 0 2006.257.19:18:30.55#ibcon#end of sib2, iclass 26, count 0 2006.257.19:18:30.55#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:18:30.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:18:30.55#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.19:18:30.55#ibcon#*before write, iclass 26, count 0 2006.257.19:18:30.55#ibcon#enter sib2, iclass 26, count 0 2006.257.19:18:30.55#ibcon#flushed, iclass 26, count 0 2006.257.19:18:30.55#ibcon#about to write, iclass 26, count 0 2006.257.19:18:30.55#ibcon#wrote, iclass 26, count 0 2006.257.19:18:30.55#ibcon#about to read 3, iclass 26, count 0 2006.257.19:18:30.59#ibcon#read 3, iclass 26, count 0 2006.257.19:18:30.59#ibcon#about to read 4, iclass 26, count 0 2006.257.19:18:30.59#ibcon#read 4, iclass 26, count 0 2006.257.19:18:30.59#ibcon#about to read 5, iclass 26, count 0 2006.257.19:18:30.59#ibcon#read 5, iclass 26, count 0 2006.257.19:18:30.59#ibcon#about to read 6, iclass 26, count 0 2006.257.19:18:30.59#ibcon#read 6, iclass 26, count 0 2006.257.19:18:30.59#ibcon#end of sib2, iclass 26, count 0 2006.257.19:18:30.59#ibcon#*after write, iclass 26, count 0 2006.257.19:18:30.59#ibcon#*before return 0, iclass 26, count 0 2006.257.19:18:30.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:30.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:18:30.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:18:30.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:18:30.59$vck44/vb=8,4 2006.257.19:18:30.59#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.19:18:30.59#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.19:18:30.59#ibcon#ireg 11 cls_cnt 2 2006.257.19:18:30.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:30.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:30.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:30.65#ibcon#enter wrdev, iclass 28, count 2 2006.257.19:18:30.65#ibcon#first serial, iclass 28, count 2 2006.257.19:18:30.65#ibcon#enter sib2, iclass 28, count 2 2006.257.19:18:30.65#ibcon#flushed, iclass 28, count 2 2006.257.19:18:30.65#ibcon#about to write, iclass 28, count 2 2006.257.19:18:30.65#ibcon#wrote, iclass 28, count 2 2006.257.19:18:30.65#ibcon#about to read 3, iclass 28, count 2 2006.257.19:18:30.67#ibcon#read 3, iclass 28, count 2 2006.257.19:18:30.67#ibcon#about to read 4, iclass 28, count 2 2006.257.19:18:30.67#ibcon#read 4, iclass 28, count 2 2006.257.19:18:30.67#ibcon#about to read 5, iclass 28, count 2 2006.257.19:18:30.67#ibcon#read 5, iclass 28, count 2 2006.257.19:18:30.67#ibcon#about to read 6, iclass 28, count 2 2006.257.19:18:30.67#ibcon#read 6, iclass 28, count 2 2006.257.19:18:30.67#ibcon#end of sib2, iclass 28, count 2 2006.257.19:18:30.67#ibcon#*mode == 0, iclass 28, count 2 2006.257.19:18:30.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.19:18:30.67#ibcon#[27=AT08-04\r\n] 2006.257.19:18:30.67#ibcon#*before write, iclass 28, count 2 2006.257.19:18:30.67#ibcon#enter sib2, iclass 28, count 2 2006.257.19:18:30.67#ibcon#flushed, iclass 28, count 2 2006.257.19:18:30.67#ibcon#about to write, iclass 28, count 2 2006.257.19:18:30.67#ibcon#wrote, iclass 28, count 2 2006.257.19:18:30.67#ibcon#about to read 3, iclass 28, count 2 2006.257.19:18:30.70#ibcon#read 3, iclass 28, count 2 2006.257.19:18:30.70#ibcon#about to read 4, iclass 28, count 2 2006.257.19:18:30.70#ibcon#read 4, iclass 28, count 2 2006.257.19:18:30.70#ibcon#about to read 5, iclass 28, count 2 2006.257.19:18:30.70#ibcon#read 5, iclass 28, count 2 2006.257.19:18:30.70#ibcon#about to read 6, iclass 28, count 2 2006.257.19:18:30.70#ibcon#read 6, iclass 28, count 2 2006.257.19:18:30.70#ibcon#end of sib2, iclass 28, count 2 2006.257.19:18:30.70#ibcon#*after write, iclass 28, count 2 2006.257.19:18:30.70#ibcon#*before return 0, iclass 28, count 2 2006.257.19:18:30.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:30.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:18:30.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.19:18:30.70#ibcon#ireg 7 cls_cnt 0 2006.257.19:18:30.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:30.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:30.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:30.82#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:18:30.82#ibcon#first serial, iclass 28, count 0 2006.257.19:18:30.82#ibcon#enter sib2, iclass 28, count 0 2006.257.19:18:30.82#ibcon#flushed, iclass 28, count 0 2006.257.19:18:30.82#ibcon#about to write, iclass 28, count 0 2006.257.19:18:30.82#ibcon#wrote, iclass 28, count 0 2006.257.19:18:30.82#ibcon#about to read 3, iclass 28, count 0 2006.257.19:18:30.84#ibcon#read 3, iclass 28, count 0 2006.257.19:18:30.84#ibcon#about to read 4, iclass 28, count 0 2006.257.19:18:30.84#ibcon#read 4, iclass 28, count 0 2006.257.19:18:30.84#ibcon#about to read 5, iclass 28, count 0 2006.257.19:18:30.84#ibcon#read 5, iclass 28, count 0 2006.257.19:18:30.84#ibcon#about to read 6, iclass 28, count 0 2006.257.19:18:30.84#ibcon#read 6, iclass 28, count 0 2006.257.19:18:30.84#ibcon#end of sib2, iclass 28, count 0 2006.257.19:18:30.84#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:18:30.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:18:30.84#ibcon#[27=USB\r\n] 2006.257.19:18:30.84#ibcon#*before write, iclass 28, count 0 2006.257.19:18:30.84#ibcon#enter sib2, iclass 28, count 0 2006.257.19:18:30.84#ibcon#flushed, iclass 28, count 0 2006.257.19:18:30.84#ibcon#about to write, iclass 28, count 0 2006.257.19:18:30.84#ibcon#wrote, iclass 28, count 0 2006.257.19:18:30.84#ibcon#about to read 3, iclass 28, count 0 2006.257.19:18:30.87#ibcon#read 3, iclass 28, count 0 2006.257.19:18:30.87#ibcon#about to read 4, iclass 28, count 0 2006.257.19:18:30.87#ibcon#read 4, iclass 28, count 0 2006.257.19:18:30.87#ibcon#about to read 5, iclass 28, count 0 2006.257.19:18:30.87#ibcon#read 5, iclass 28, count 0 2006.257.19:18:30.87#ibcon#about to read 6, iclass 28, count 0 2006.257.19:18:30.87#ibcon#read 6, iclass 28, count 0 2006.257.19:18:30.87#ibcon#end of sib2, iclass 28, count 0 2006.257.19:18:30.87#ibcon#*after write, iclass 28, count 0 2006.257.19:18:30.87#ibcon#*before return 0, iclass 28, count 0 2006.257.19:18:30.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:30.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:18:30.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:18:30.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:18:30.87$vck44/vabw=wide 2006.257.19:18:30.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.19:18:30.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.19:18:30.87#ibcon#ireg 8 cls_cnt 0 2006.257.19:18:30.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:30.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:30.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:30.87#ibcon#enter wrdev, iclass 30, count 0 2006.257.19:18:30.87#ibcon#first serial, iclass 30, count 0 2006.257.19:18:30.87#ibcon#enter sib2, iclass 30, count 0 2006.257.19:18:30.87#ibcon#flushed, iclass 30, count 0 2006.257.19:18:30.87#ibcon#about to write, iclass 30, count 0 2006.257.19:18:30.87#ibcon#wrote, iclass 30, count 0 2006.257.19:18:30.87#ibcon#about to read 3, iclass 30, count 0 2006.257.19:18:30.89#ibcon#read 3, iclass 30, count 0 2006.257.19:18:30.89#ibcon#about to read 4, iclass 30, count 0 2006.257.19:18:30.89#ibcon#read 4, iclass 30, count 0 2006.257.19:18:30.89#ibcon#about to read 5, iclass 30, count 0 2006.257.19:18:30.89#ibcon#read 5, iclass 30, count 0 2006.257.19:18:30.89#ibcon#about to read 6, iclass 30, count 0 2006.257.19:18:30.89#ibcon#read 6, iclass 30, count 0 2006.257.19:18:30.89#ibcon#end of sib2, iclass 30, count 0 2006.257.19:18:30.89#ibcon#*mode == 0, iclass 30, count 0 2006.257.19:18:30.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.19:18:30.89#ibcon#[25=BW32\r\n] 2006.257.19:18:30.89#ibcon#*before write, iclass 30, count 0 2006.257.19:18:30.89#ibcon#enter sib2, iclass 30, count 0 2006.257.19:18:30.89#ibcon#flushed, iclass 30, count 0 2006.257.19:18:30.89#ibcon#about to write, iclass 30, count 0 2006.257.19:18:30.89#ibcon#wrote, iclass 30, count 0 2006.257.19:18:30.89#ibcon#about to read 3, iclass 30, count 0 2006.257.19:18:30.92#ibcon#read 3, iclass 30, count 0 2006.257.19:18:30.92#ibcon#about to read 4, iclass 30, count 0 2006.257.19:18:30.92#ibcon#read 4, iclass 30, count 0 2006.257.19:18:30.92#ibcon#about to read 5, iclass 30, count 0 2006.257.19:18:30.92#ibcon#read 5, iclass 30, count 0 2006.257.19:18:30.92#ibcon#about to read 6, iclass 30, count 0 2006.257.19:18:30.92#ibcon#read 6, iclass 30, count 0 2006.257.19:18:30.92#ibcon#end of sib2, iclass 30, count 0 2006.257.19:18:30.92#ibcon#*after write, iclass 30, count 0 2006.257.19:18:30.92#ibcon#*before return 0, iclass 30, count 0 2006.257.19:18:30.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:30.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:18:30.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.19:18:30.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.19:18:30.92$vck44/vbbw=wide 2006.257.19:18:30.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.19:18:30.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.19:18:30.92#ibcon#ireg 8 cls_cnt 0 2006.257.19:18:30.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:18:30.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:18:30.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:18:30.99#ibcon#enter wrdev, iclass 32, count 0 2006.257.19:18:30.99#ibcon#first serial, iclass 32, count 0 2006.257.19:18:30.99#ibcon#enter sib2, iclass 32, count 0 2006.257.19:18:30.99#ibcon#flushed, iclass 32, count 0 2006.257.19:18:30.99#ibcon#about to write, iclass 32, count 0 2006.257.19:18:30.99#ibcon#wrote, iclass 32, count 0 2006.257.19:18:30.99#ibcon#about to read 3, iclass 32, count 0 2006.257.19:18:31.01#ibcon#read 3, iclass 32, count 0 2006.257.19:18:31.01#ibcon#about to read 4, iclass 32, count 0 2006.257.19:18:31.01#ibcon#read 4, iclass 32, count 0 2006.257.19:18:31.01#ibcon#about to read 5, iclass 32, count 0 2006.257.19:18:31.01#ibcon#read 5, iclass 32, count 0 2006.257.19:18:31.01#ibcon#about to read 6, iclass 32, count 0 2006.257.19:18:31.01#ibcon#read 6, iclass 32, count 0 2006.257.19:18:31.01#ibcon#end of sib2, iclass 32, count 0 2006.257.19:18:31.01#ibcon#*mode == 0, iclass 32, count 0 2006.257.19:18:31.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.19:18:31.01#ibcon#[27=BW32\r\n] 2006.257.19:18:31.01#ibcon#*before write, iclass 32, count 0 2006.257.19:18:31.01#ibcon#enter sib2, iclass 32, count 0 2006.257.19:18:31.01#ibcon#flushed, iclass 32, count 0 2006.257.19:18:31.01#ibcon#about to write, iclass 32, count 0 2006.257.19:18:31.01#ibcon#wrote, iclass 32, count 0 2006.257.19:18:31.01#ibcon#about to read 3, iclass 32, count 0 2006.257.19:18:31.04#ibcon#read 3, iclass 32, count 0 2006.257.19:18:31.04#ibcon#about to read 4, iclass 32, count 0 2006.257.19:18:31.04#ibcon#read 4, iclass 32, count 0 2006.257.19:18:31.04#ibcon#about to read 5, iclass 32, count 0 2006.257.19:18:31.04#ibcon#read 5, iclass 32, count 0 2006.257.19:18:31.04#ibcon#about to read 6, iclass 32, count 0 2006.257.19:18:31.04#ibcon#read 6, iclass 32, count 0 2006.257.19:18:31.04#ibcon#end of sib2, iclass 32, count 0 2006.257.19:18:31.04#ibcon#*after write, iclass 32, count 0 2006.257.19:18:31.04#ibcon#*before return 0, iclass 32, count 0 2006.257.19:18:31.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:18:31.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:18:31.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.19:18:31.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.19:18:31.04$setupk4/ifdk4 2006.257.19:18:31.04$ifdk4/lo= 2006.257.19:18:31.04$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.19:18:31.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.19:18:31.05$ifdk4/patch= 2006.257.19:18:31.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.19:18:31.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.19:18:31.05$setupk4/!*+20s 2006.257.19:18:33.21#abcon#<5=/14 1.0 2.8 17.47 961014.3\r\n> 2006.257.19:18:33.23#abcon#{5=INTERFACE CLEAR} 2006.257.19:18:33.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:18:43.38#abcon#<5=/14 1.0 2.8 17.47 961014.3\r\n> 2006.257.19:18:43.40#abcon#{5=INTERFACE CLEAR} 2006.257.19:18:43.46#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:18:45.57$setupk4/"tpicd 2006.257.19:18:45.57$setupk4/echo=off 2006.257.19:18:45.57$setupk4/xlog=off 2006.257.19:18:45.57:!2006.257.19:24:16 2006.257.19:18:49.13#trakl#Source acquired 2006.257.19:18:51.13#flagr#flagr/antenna,acquired 2006.257.19:24:16.00:preob 2006.257.19:24:16.14/onsource/TRACKING 2006.257.19:24:16.14:!2006.257.19:24:26 2006.257.19:24:26.00:"tape 2006.257.19:24:26.00:"st=record 2006.257.19:24:26.00:data_valid=on 2006.257.19:24:26.00:midob 2006.257.19:24:27.14/onsource/TRACKING 2006.257.19:24:27.14/wx/17.50,1014.3,96 2006.257.19:24:27.24/cable/+6.4851E-03 2006.257.19:24:28.33/va/01,08,usb,yes,32,35 2006.257.19:24:28.33/va/02,07,usb,yes,35,35 2006.257.19:24:28.33/va/03,08,usb,yes,31,33 2006.257.19:24:28.33/va/04,07,usb,yes,36,38 2006.257.19:24:28.33/va/05,04,usb,yes,32,33 2006.257.19:24:28.33/va/06,04,usb,yes,36,35 2006.257.19:24:28.33/va/07,04,usb,yes,37,37 2006.257.19:24:28.33/va/08,04,usb,yes,31,37 2006.257.19:24:28.56/valo/01,524.99,yes,locked 2006.257.19:24:28.56/valo/02,534.99,yes,locked 2006.257.19:24:28.56/valo/03,564.99,yes,locked 2006.257.19:24:28.56/valo/04,624.99,yes,locked 2006.257.19:24:28.56/valo/05,734.99,yes,locked 2006.257.19:24:28.56/valo/06,814.99,yes,locked 2006.257.19:24:28.56/valo/07,864.99,yes,locked 2006.257.19:24:28.56/valo/08,884.99,yes,locked 2006.257.19:24:29.65/vb/01,04,usb,yes,30,28 2006.257.19:24:29.65/vb/02,05,usb,yes,29,28 2006.257.19:24:29.65/vb/03,04,usb,yes,29,32 2006.257.19:24:29.65/vb/04,05,usb,yes,30,29 2006.257.19:24:29.65/vb/05,04,usb,yes,26,29 2006.257.19:24:29.65/vb/06,04,usb,yes,31,27 2006.257.19:24:29.65/vb/07,04,usb,yes,30,30 2006.257.19:24:29.65/vb/08,04,usb,yes,28,31 2006.257.19:24:29.89/vblo/01,629.99,yes,locked 2006.257.19:24:29.89/vblo/02,634.99,yes,locked 2006.257.19:24:29.89/vblo/03,649.99,yes,locked 2006.257.19:24:29.89/vblo/04,679.99,yes,locked 2006.257.19:24:29.89/vblo/05,709.99,yes,locked 2006.257.19:24:29.89/vblo/06,719.99,yes,locked 2006.257.19:24:29.89/vblo/07,734.99,yes,locked 2006.257.19:24:29.89/vblo/08,744.99,yes,locked 2006.257.19:24:30.04/vabw/8 2006.257.19:24:30.19/vbbw/8 2006.257.19:24:30.37/xfe/off,on,15.0 2006.257.19:24:30.75/ifatt/23,28,28,28 2006.257.19:24:31.07/fmout-gps/S +4.54E-07 2006.257.19:24:31.11:!2006.257.19:27:56 2006.257.19:27:56.01:data_valid=off 2006.257.19:27:56.02:"et 2006.257.19:27:56.02:!+3s 2006.257.19:27:59.03:"tape 2006.257.19:27:59.03:postob 2006.257.19:27:59.20/cable/+6.4861E-03 2006.257.19:27:59.20/wx/17.51,1014.4,96 2006.257.19:27:59.26/fmout-gps/S +4.52E-07 2006.257.19:27:59.26:scan_name=257-1938,jd0609,110 2006.257.19:27:59.26:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.257.19:28:00.13#flagr#flagr/antenna,new-source 2006.257.19:28:00.14:checkk5 2006.257.19:28:00.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.19:28:00.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.19:28:01.15/chk_autoobs//k5ts3/ autoobs is running! 2006.257.19:28:01.49/chk_autoobs//k5ts4/ autoobs is running! 2006.257.19:28:01.83/chk_obsdata//k5ts1/T2571924??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.19:28:02.16/chk_obsdata//k5ts2/T2571924??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.19:28:02.49/chk_obsdata//k5ts3/T2571924??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.19:28:02.83/chk_obsdata//k5ts4/T2571924??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.19:28:03.48/k5log//k5ts1_log_newline 2006.257.19:28:04.13/k5log//k5ts2_log_newline 2006.257.19:28:04.78/k5log//k5ts3_log_newline 2006.257.19:28:05.44/k5log//k5ts4_log_newline 2006.257.19:28:05.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.19:28:05.47:setupk4=1 2006.257.19:28:05.47$setupk4/echo=on 2006.257.19:28:05.47$setupk4/pcalon 2006.257.19:28:05.47$pcalon/"no phase cal control is implemented here 2006.257.19:28:05.47$setupk4/"tpicd=stop 2006.257.19:28:05.47$setupk4/"rec=synch_on 2006.257.19:28:05.47$setupk4/"rec_mode=128 2006.257.19:28:05.47$setupk4/!* 2006.257.19:28:05.47$setupk4/recpk4 2006.257.19:28:05.47$recpk4/recpatch= 2006.257.19:28:05.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.19:28:05.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.19:28:05.47$setupk4/vck44 2006.257.19:28:05.47$vck44/valo=1,524.99 2006.257.19:28:05.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.19:28:05.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.19:28:05.47#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:05.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:05.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:05.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:05.47#ibcon#enter wrdev, iclass 13, count 0 2006.257.19:28:05.47#ibcon#first serial, iclass 13, count 0 2006.257.19:28:05.47#ibcon#enter sib2, iclass 13, count 0 2006.257.19:28:05.47#ibcon#flushed, iclass 13, count 0 2006.257.19:28:05.47#ibcon#about to write, iclass 13, count 0 2006.257.19:28:05.47#ibcon#wrote, iclass 13, count 0 2006.257.19:28:05.47#ibcon#about to read 3, iclass 13, count 0 2006.257.19:28:05.49#ibcon#read 3, iclass 13, count 0 2006.257.19:28:05.49#ibcon#about to read 4, iclass 13, count 0 2006.257.19:28:05.49#ibcon#read 4, iclass 13, count 0 2006.257.19:28:05.49#ibcon#about to read 5, iclass 13, count 0 2006.257.19:28:05.49#ibcon#read 5, iclass 13, count 0 2006.257.19:28:05.49#ibcon#about to read 6, iclass 13, count 0 2006.257.19:28:05.49#ibcon#read 6, iclass 13, count 0 2006.257.19:28:05.49#ibcon#end of sib2, iclass 13, count 0 2006.257.19:28:05.49#ibcon#*mode == 0, iclass 13, count 0 2006.257.19:28:05.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.19:28:05.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.19:28:05.49#ibcon#*before write, iclass 13, count 0 2006.257.19:28:05.49#ibcon#enter sib2, iclass 13, count 0 2006.257.19:28:05.49#ibcon#flushed, iclass 13, count 0 2006.257.19:28:05.49#ibcon#about to write, iclass 13, count 0 2006.257.19:28:05.49#ibcon#wrote, iclass 13, count 0 2006.257.19:28:05.49#ibcon#about to read 3, iclass 13, count 0 2006.257.19:28:05.54#ibcon#read 3, iclass 13, count 0 2006.257.19:28:05.54#ibcon#about to read 4, iclass 13, count 0 2006.257.19:28:05.54#ibcon#read 4, iclass 13, count 0 2006.257.19:28:05.54#ibcon#about to read 5, iclass 13, count 0 2006.257.19:28:05.54#ibcon#read 5, iclass 13, count 0 2006.257.19:28:05.54#ibcon#about to read 6, iclass 13, count 0 2006.257.19:28:05.54#ibcon#read 6, iclass 13, count 0 2006.257.19:28:05.54#ibcon#end of sib2, iclass 13, count 0 2006.257.19:28:05.54#ibcon#*after write, iclass 13, count 0 2006.257.19:28:05.54#ibcon#*before return 0, iclass 13, count 0 2006.257.19:28:05.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:05.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:05.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.19:28:05.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.19:28:05.54$vck44/va=1,8 2006.257.19:28:05.54#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.19:28:05.54#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.19:28:05.54#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:05.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:05.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:05.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:05.54#ibcon#enter wrdev, iclass 15, count 2 2006.257.19:28:05.54#ibcon#first serial, iclass 15, count 2 2006.257.19:28:05.54#ibcon#enter sib2, iclass 15, count 2 2006.257.19:28:05.54#ibcon#flushed, iclass 15, count 2 2006.257.19:28:05.54#ibcon#about to write, iclass 15, count 2 2006.257.19:28:05.54#ibcon#wrote, iclass 15, count 2 2006.257.19:28:05.54#ibcon#about to read 3, iclass 15, count 2 2006.257.19:28:05.56#ibcon#read 3, iclass 15, count 2 2006.257.19:28:05.56#ibcon#about to read 4, iclass 15, count 2 2006.257.19:28:05.56#ibcon#read 4, iclass 15, count 2 2006.257.19:28:05.56#ibcon#about to read 5, iclass 15, count 2 2006.257.19:28:05.56#ibcon#read 5, iclass 15, count 2 2006.257.19:28:05.56#ibcon#about to read 6, iclass 15, count 2 2006.257.19:28:05.56#ibcon#read 6, iclass 15, count 2 2006.257.19:28:05.56#ibcon#end of sib2, iclass 15, count 2 2006.257.19:28:05.56#ibcon#*mode == 0, iclass 15, count 2 2006.257.19:28:05.56#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.19:28:05.56#ibcon#[25=AT01-08\r\n] 2006.257.19:28:05.56#ibcon#*before write, iclass 15, count 2 2006.257.19:28:05.56#ibcon#enter sib2, iclass 15, count 2 2006.257.19:28:05.56#ibcon#flushed, iclass 15, count 2 2006.257.19:28:05.56#ibcon#about to write, iclass 15, count 2 2006.257.19:28:05.56#ibcon#wrote, iclass 15, count 2 2006.257.19:28:05.56#ibcon#about to read 3, iclass 15, count 2 2006.257.19:28:05.59#ibcon#read 3, iclass 15, count 2 2006.257.19:28:05.59#ibcon#about to read 4, iclass 15, count 2 2006.257.19:28:05.59#ibcon#read 4, iclass 15, count 2 2006.257.19:28:05.59#ibcon#about to read 5, iclass 15, count 2 2006.257.19:28:05.59#ibcon#read 5, iclass 15, count 2 2006.257.19:28:05.59#ibcon#about to read 6, iclass 15, count 2 2006.257.19:28:05.59#ibcon#read 6, iclass 15, count 2 2006.257.19:28:05.59#ibcon#end of sib2, iclass 15, count 2 2006.257.19:28:05.59#ibcon#*after write, iclass 15, count 2 2006.257.19:28:05.59#ibcon#*before return 0, iclass 15, count 2 2006.257.19:28:05.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:05.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:05.59#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.19:28:05.59#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:05.59#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:05.71#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:05.71#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:05.71#ibcon#enter wrdev, iclass 15, count 0 2006.257.19:28:05.71#ibcon#first serial, iclass 15, count 0 2006.257.19:28:05.71#ibcon#enter sib2, iclass 15, count 0 2006.257.19:28:05.71#ibcon#flushed, iclass 15, count 0 2006.257.19:28:05.71#ibcon#about to write, iclass 15, count 0 2006.257.19:28:05.71#ibcon#wrote, iclass 15, count 0 2006.257.19:28:05.71#ibcon#about to read 3, iclass 15, count 0 2006.257.19:28:05.73#ibcon#read 3, iclass 15, count 0 2006.257.19:28:05.73#ibcon#about to read 4, iclass 15, count 0 2006.257.19:28:05.73#ibcon#read 4, iclass 15, count 0 2006.257.19:28:05.73#ibcon#about to read 5, iclass 15, count 0 2006.257.19:28:05.73#ibcon#read 5, iclass 15, count 0 2006.257.19:28:05.73#ibcon#about to read 6, iclass 15, count 0 2006.257.19:28:05.73#ibcon#read 6, iclass 15, count 0 2006.257.19:28:05.73#ibcon#end of sib2, iclass 15, count 0 2006.257.19:28:05.73#ibcon#*mode == 0, iclass 15, count 0 2006.257.19:28:05.73#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.19:28:05.73#ibcon#[25=USB\r\n] 2006.257.19:28:05.73#ibcon#*before write, iclass 15, count 0 2006.257.19:28:05.73#ibcon#enter sib2, iclass 15, count 0 2006.257.19:28:05.73#ibcon#flushed, iclass 15, count 0 2006.257.19:28:05.73#ibcon#about to write, iclass 15, count 0 2006.257.19:28:05.73#ibcon#wrote, iclass 15, count 0 2006.257.19:28:05.73#ibcon#about to read 3, iclass 15, count 0 2006.257.19:28:05.76#ibcon#read 3, iclass 15, count 0 2006.257.19:28:05.76#ibcon#about to read 4, iclass 15, count 0 2006.257.19:28:05.76#ibcon#read 4, iclass 15, count 0 2006.257.19:28:05.76#ibcon#about to read 5, iclass 15, count 0 2006.257.19:28:05.76#ibcon#read 5, iclass 15, count 0 2006.257.19:28:05.76#ibcon#about to read 6, iclass 15, count 0 2006.257.19:28:05.76#ibcon#read 6, iclass 15, count 0 2006.257.19:28:05.76#ibcon#end of sib2, iclass 15, count 0 2006.257.19:28:05.76#ibcon#*after write, iclass 15, count 0 2006.257.19:28:05.76#ibcon#*before return 0, iclass 15, count 0 2006.257.19:28:05.76#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:05.76#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:05.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.19:28:05.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.19:28:05.76$vck44/valo=2,534.99 2006.257.19:28:05.76#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.19:28:05.76#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.19:28:05.76#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:05.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:05.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:05.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:05.76#ibcon#enter wrdev, iclass 17, count 0 2006.257.19:28:05.76#ibcon#first serial, iclass 17, count 0 2006.257.19:28:05.76#ibcon#enter sib2, iclass 17, count 0 2006.257.19:28:05.76#ibcon#flushed, iclass 17, count 0 2006.257.19:28:05.76#ibcon#about to write, iclass 17, count 0 2006.257.19:28:05.76#ibcon#wrote, iclass 17, count 0 2006.257.19:28:05.76#ibcon#about to read 3, iclass 17, count 0 2006.257.19:28:05.78#ibcon#read 3, iclass 17, count 0 2006.257.19:28:05.78#ibcon#about to read 4, iclass 17, count 0 2006.257.19:28:05.78#ibcon#read 4, iclass 17, count 0 2006.257.19:28:05.78#ibcon#about to read 5, iclass 17, count 0 2006.257.19:28:05.78#ibcon#read 5, iclass 17, count 0 2006.257.19:28:05.78#ibcon#about to read 6, iclass 17, count 0 2006.257.19:28:05.78#ibcon#read 6, iclass 17, count 0 2006.257.19:28:05.78#ibcon#end of sib2, iclass 17, count 0 2006.257.19:28:05.78#ibcon#*mode == 0, iclass 17, count 0 2006.257.19:28:05.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.19:28:05.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.19:28:05.78#ibcon#*before write, iclass 17, count 0 2006.257.19:28:05.78#ibcon#enter sib2, iclass 17, count 0 2006.257.19:28:05.78#ibcon#flushed, iclass 17, count 0 2006.257.19:28:05.78#ibcon#about to write, iclass 17, count 0 2006.257.19:28:05.78#ibcon#wrote, iclass 17, count 0 2006.257.19:28:05.78#ibcon#about to read 3, iclass 17, count 0 2006.257.19:28:05.82#ibcon#read 3, iclass 17, count 0 2006.257.19:28:05.82#ibcon#about to read 4, iclass 17, count 0 2006.257.19:28:05.82#ibcon#read 4, iclass 17, count 0 2006.257.19:28:05.82#ibcon#about to read 5, iclass 17, count 0 2006.257.19:28:05.82#ibcon#read 5, iclass 17, count 0 2006.257.19:28:05.82#ibcon#about to read 6, iclass 17, count 0 2006.257.19:28:05.82#ibcon#read 6, iclass 17, count 0 2006.257.19:28:05.82#ibcon#end of sib2, iclass 17, count 0 2006.257.19:28:05.82#ibcon#*after write, iclass 17, count 0 2006.257.19:28:05.82#ibcon#*before return 0, iclass 17, count 0 2006.257.19:28:05.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:05.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:05.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.19:28:05.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.19:28:05.82$vck44/va=2,7 2006.257.19:28:05.82#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.19:28:05.82#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.19:28:05.82#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:05.82#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:05.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:05.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:05.88#ibcon#enter wrdev, iclass 19, count 2 2006.257.19:28:05.88#ibcon#first serial, iclass 19, count 2 2006.257.19:28:05.88#ibcon#enter sib2, iclass 19, count 2 2006.257.19:28:05.88#ibcon#flushed, iclass 19, count 2 2006.257.19:28:05.88#ibcon#about to write, iclass 19, count 2 2006.257.19:28:05.88#ibcon#wrote, iclass 19, count 2 2006.257.19:28:05.88#ibcon#about to read 3, iclass 19, count 2 2006.257.19:28:05.90#ibcon#read 3, iclass 19, count 2 2006.257.19:28:05.90#ibcon#about to read 4, iclass 19, count 2 2006.257.19:28:05.90#ibcon#read 4, iclass 19, count 2 2006.257.19:28:05.90#ibcon#about to read 5, iclass 19, count 2 2006.257.19:28:05.90#ibcon#read 5, iclass 19, count 2 2006.257.19:28:05.90#ibcon#about to read 6, iclass 19, count 2 2006.257.19:28:05.90#ibcon#read 6, iclass 19, count 2 2006.257.19:28:05.90#ibcon#end of sib2, iclass 19, count 2 2006.257.19:28:05.90#ibcon#*mode == 0, iclass 19, count 2 2006.257.19:28:05.90#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.19:28:05.90#ibcon#[25=AT02-07\r\n] 2006.257.19:28:05.90#ibcon#*before write, iclass 19, count 2 2006.257.19:28:05.90#ibcon#enter sib2, iclass 19, count 2 2006.257.19:28:05.90#ibcon#flushed, iclass 19, count 2 2006.257.19:28:05.90#ibcon#about to write, iclass 19, count 2 2006.257.19:28:05.90#ibcon#wrote, iclass 19, count 2 2006.257.19:28:05.90#ibcon#about to read 3, iclass 19, count 2 2006.257.19:28:05.93#ibcon#read 3, iclass 19, count 2 2006.257.19:28:05.93#ibcon#about to read 4, iclass 19, count 2 2006.257.19:28:05.93#ibcon#read 4, iclass 19, count 2 2006.257.19:28:05.93#ibcon#about to read 5, iclass 19, count 2 2006.257.19:28:05.93#ibcon#read 5, iclass 19, count 2 2006.257.19:28:05.93#ibcon#about to read 6, iclass 19, count 2 2006.257.19:28:05.93#ibcon#read 6, iclass 19, count 2 2006.257.19:28:05.93#ibcon#end of sib2, iclass 19, count 2 2006.257.19:28:05.93#ibcon#*after write, iclass 19, count 2 2006.257.19:28:05.93#ibcon#*before return 0, iclass 19, count 2 2006.257.19:28:05.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:05.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:05.93#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.19:28:05.93#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:05.93#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:06.05#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:06.05#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:06.05#ibcon#enter wrdev, iclass 19, count 0 2006.257.19:28:06.05#ibcon#first serial, iclass 19, count 0 2006.257.19:28:06.05#ibcon#enter sib2, iclass 19, count 0 2006.257.19:28:06.05#ibcon#flushed, iclass 19, count 0 2006.257.19:28:06.05#ibcon#about to write, iclass 19, count 0 2006.257.19:28:06.05#ibcon#wrote, iclass 19, count 0 2006.257.19:28:06.05#ibcon#about to read 3, iclass 19, count 0 2006.257.19:28:06.07#ibcon#read 3, iclass 19, count 0 2006.257.19:28:06.07#ibcon#about to read 4, iclass 19, count 0 2006.257.19:28:06.07#ibcon#read 4, iclass 19, count 0 2006.257.19:28:06.07#ibcon#about to read 5, iclass 19, count 0 2006.257.19:28:06.07#ibcon#read 5, iclass 19, count 0 2006.257.19:28:06.07#ibcon#about to read 6, iclass 19, count 0 2006.257.19:28:06.07#ibcon#read 6, iclass 19, count 0 2006.257.19:28:06.07#ibcon#end of sib2, iclass 19, count 0 2006.257.19:28:06.07#ibcon#*mode == 0, iclass 19, count 0 2006.257.19:28:06.07#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.19:28:06.07#ibcon#[25=USB\r\n] 2006.257.19:28:06.07#ibcon#*before write, iclass 19, count 0 2006.257.19:28:06.07#ibcon#enter sib2, iclass 19, count 0 2006.257.19:28:06.07#ibcon#flushed, iclass 19, count 0 2006.257.19:28:06.07#ibcon#about to write, iclass 19, count 0 2006.257.19:28:06.07#ibcon#wrote, iclass 19, count 0 2006.257.19:28:06.07#ibcon#about to read 3, iclass 19, count 0 2006.257.19:28:06.10#ibcon#read 3, iclass 19, count 0 2006.257.19:28:06.10#ibcon#about to read 4, iclass 19, count 0 2006.257.19:28:06.10#ibcon#read 4, iclass 19, count 0 2006.257.19:28:06.10#ibcon#about to read 5, iclass 19, count 0 2006.257.19:28:06.10#ibcon#read 5, iclass 19, count 0 2006.257.19:28:06.10#ibcon#about to read 6, iclass 19, count 0 2006.257.19:28:06.10#ibcon#read 6, iclass 19, count 0 2006.257.19:28:06.10#ibcon#end of sib2, iclass 19, count 0 2006.257.19:28:06.10#ibcon#*after write, iclass 19, count 0 2006.257.19:28:06.10#ibcon#*before return 0, iclass 19, count 0 2006.257.19:28:06.10#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:06.10#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:06.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.19:28:06.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.19:28:06.10$vck44/valo=3,564.99 2006.257.19:28:06.10#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.19:28:06.10#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.19:28:06.10#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:06.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:06.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:06.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:06.10#ibcon#enter wrdev, iclass 21, count 0 2006.257.19:28:06.10#ibcon#first serial, iclass 21, count 0 2006.257.19:28:06.10#ibcon#enter sib2, iclass 21, count 0 2006.257.19:28:06.10#ibcon#flushed, iclass 21, count 0 2006.257.19:28:06.10#ibcon#about to write, iclass 21, count 0 2006.257.19:28:06.10#ibcon#wrote, iclass 21, count 0 2006.257.19:28:06.10#ibcon#about to read 3, iclass 21, count 0 2006.257.19:28:06.12#ibcon#read 3, iclass 21, count 0 2006.257.19:28:06.12#ibcon#about to read 4, iclass 21, count 0 2006.257.19:28:06.12#ibcon#read 4, iclass 21, count 0 2006.257.19:28:06.12#ibcon#about to read 5, iclass 21, count 0 2006.257.19:28:06.12#ibcon#read 5, iclass 21, count 0 2006.257.19:28:06.12#ibcon#about to read 6, iclass 21, count 0 2006.257.19:28:06.12#ibcon#read 6, iclass 21, count 0 2006.257.19:28:06.12#ibcon#end of sib2, iclass 21, count 0 2006.257.19:28:06.12#ibcon#*mode == 0, iclass 21, count 0 2006.257.19:28:06.12#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.19:28:06.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.19:28:06.12#ibcon#*before write, iclass 21, count 0 2006.257.19:28:06.12#ibcon#enter sib2, iclass 21, count 0 2006.257.19:28:06.12#ibcon#flushed, iclass 21, count 0 2006.257.19:28:06.12#ibcon#about to write, iclass 21, count 0 2006.257.19:28:06.12#ibcon#wrote, iclass 21, count 0 2006.257.19:28:06.12#ibcon#about to read 3, iclass 21, count 0 2006.257.19:28:06.16#ibcon#read 3, iclass 21, count 0 2006.257.19:28:06.16#ibcon#about to read 4, iclass 21, count 0 2006.257.19:28:06.16#ibcon#read 4, iclass 21, count 0 2006.257.19:28:06.16#ibcon#about to read 5, iclass 21, count 0 2006.257.19:28:06.16#ibcon#read 5, iclass 21, count 0 2006.257.19:28:06.16#ibcon#about to read 6, iclass 21, count 0 2006.257.19:28:06.16#ibcon#read 6, iclass 21, count 0 2006.257.19:28:06.16#ibcon#end of sib2, iclass 21, count 0 2006.257.19:28:06.16#ibcon#*after write, iclass 21, count 0 2006.257.19:28:06.16#ibcon#*before return 0, iclass 21, count 0 2006.257.19:28:06.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:06.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:06.16#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.19:28:06.16#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.19:28:06.16$vck44/va=3,8 2006.257.19:28:06.16#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.19:28:06.16#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.19:28:06.16#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:06.16#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:06.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:06.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:06.22#ibcon#enter wrdev, iclass 23, count 2 2006.257.19:28:06.22#ibcon#first serial, iclass 23, count 2 2006.257.19:28:06.22#ibcon#enter sib2, iclass 23, count 2 2006.257.19:28:06.22#ibcon#flushed, iclass 23, count 2 2006.257.19:28:06.22#ibcon#about to write, iclass 23, count 2 2006.257.19:28:06.22#ibcon#wrote, iclass 23, count 2 2006.257.19:28:06.22#ibcon#about to read 3, iclass 23, count 2 2006.257.19:28:06.24#ibcon#read 3, iclass 23, count 2 2006.257.19:28:06.24#ibcon#about to read 4, iclass 23, count 2 2006.257.19:28:06.24#ibcon#read 4, iclass 23, count 2 2006.257.19:28:06.24#ibcon#about to read 5, iclass 23, count 2 2006.257.19:28:06.24#ibcon#read 5, iclass 23, count 2 2006.257.19:28:06.24#ibcon#about to read 6, iclass 23, count 2 2006.257.19:28:06.24#ibcon#read 6, iclass 23, count 2 2006.257.19:28:06.24#ibcon#end of sib2, iclass 23, count 2 2006.257.19:28:06.24#ibcon#*mode == 0, iclass 23, count 2 2006.257.19:28:06.24#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.19:28:06.24#ibcon#[25=AT03-08\r\n] 2006.257.19:28:06.24#ibcon#*before write, iclass 23, count 2 2006.257.19:28:06.24#ibcon#enter sib2, iclass 23, count 2 2006.257.19:28:06.24#ibcon#flushed, iclass 23, count 2 2006.257.19:28:06.24#ibcon#about to write, iclass 23, count 2 2006.257.19:28:06.24#ibcon#wrote, iclass 23, count 2 2006.257.19:28:06.24#ibcon#about to read 3, iclass 23, count 2 2006.257.19:28:06.27#ibcon#read 3, iclass 23, count 2 2006.257.19:28:06.27#ibcon#about to read 4, iclass 23, count 2 2006.257.19:28:06.27#ibcon#read 4, iclass 23, count 2 2006.257.19:28:06.27#ibcon#about to read 5, iclass 23, count 2 2006.257.19:28:06.27#ibcon#read 5, iclass 23, count 2 2006.257.19:28:06.27#ibcon#about to read 6, iclass 23, count 2 2006.257.19:28:06.27#ibcon#read 6, iclass 23, count 2 2006.257.19:28:06.27#ibcon#end of sib2, iclass 23, count 2 2006.257.19:28:06.27#ibcon#*after write, iclass 23, count 2 2006.257.19:28:06.27#ibcon#*before return 0, iclass 23, count 2 2006.257.19:28:06.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:06.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:06.27#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.19:28:06.27#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:06.27#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:06.39#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:06.39#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:06.39#ibcon#enter wrdev, iclass 23, count 0 2006.257.19:28:06.39#ibcon#first serial, iclass 23, count 0 2006.257.19:28:06.39#ibcon#enter sib2, iclass 23, count 0 2006.257.19:28:06.39#ibcon#flushed, iclass 23, count 0 2006.257.19:28:06.39#ibcon#about to write, iclass 23, count 0 2006.257.19:28:06.39#ibcon#wrote, iclass 23, count 0 2006.257.19:28:06.39#ibcon#about to read 3, iclass 23, count 0 2006.257.19:28:06.41#ibcon#read 3, iclass 23, count 0 2006.257.19:28:06.41#ibcon#about to read 4, iclass 23, count 0 2006.257.19:28:06.41#ibcon#read 4, iclass 23, count 0 2006.257.19:28:06.41#ibcon#about to read 5, iclass 23, count 0 2006.257.19:28:06.41#ibcon#read 5, iclass 23, count 0 2006.257.19:28:06.41#ibcon#about to read 6, iclass 23, count 0 2006.257.19:28:06.41#ibcon#read 6, iclass 23, count 0 2006.257.19:28:06.41#ibcon#end of sib2, iclass 23, count 0 2006.257.19:28:06.41#ibcon#*mode == 0, iclass 23, count 0 2006.257.19:28:06.41#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.19:28:06.41#ibcon#[25=USB\r\n] 2006.257.19:28:06.41#ibcon#*before write, iclass 23, count 0 2006.257.19:28:06.41#ibcon#enter sib2, iclass 23, count 0 2006.257.19:28:06.41#ibcon#flushed, iclass 23, count 0 2006.257.19:28:06.41#ibcon#about to write, iclass 23, count 0 2006.257.19:28:06.41#ibcon#wrote, iclass 23, count 0 2006.257.19:28:06.41#ibcon#about to read 3, iclass 23, count 0 2006.257.19:28:06.44#ibcon#read 3, iclass 23, count 0 2006.257.19:28:06.44#ibcon#about to read 4, iclass 23, count 0 2006.257.19:28:06.44#ibcon#read 4, iclass 23, count 0 2006.257.19:28:06.44#ibcon#about to read 5, iclass 23, count 0 2006.257.19:28:06.44#ibcon#read 5, iclass 23, count 0 2006.257.19:28:06.44#ibcon#about to read 6, iclass 23, count 0 2006.257.19:28:06.44#ibcon#read 6, iclass 23, count 0 2006.257.19:28:06.44#ibcon#end of sib2, iclass 23, count 0 2006.257.19:28:06.44#ibcon#*after write, iclass 23, count 0 2006.257.19:28:06.44#ibcon#*before return 0, iclass 23, count 0 2006.257.19:28:06.44#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:06.44#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:06.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.19:28:06.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.19:28:06.44$vck44/valo=4,624.99 2006.257.19:28:06.44#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.19:28:06.44#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.19:28:06.44#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:06.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:06.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:06.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:06.44#ibcon#enter wrdev, iclass 25, count 0 2006.257.19:28:06.44#ibcon#first serial, iclass 25, count 0 2006.257.19:28:06.44#ibcon#enter sib2, iclass 25, count 0 2006.257.19:28:06.44#ibcon#flushed, iclass 25, count 0 2006.257.19:28:06.44#ibcon#about to write, iclass 25, count 0 2006.257.19:28:06.44#ibcon#wrote, iclass 25, count 0 2006.257.19:28:06.44#ibcon#about to read 3, iclass 25, count 0 2006.257.19:28:06.46#ibcon#read 3, iclass 25, count 0 2006.257.19:28:06.46#ibcon#about to read 4, iclass 25, count 0 2006.257.19:28:06.46#ibcon#read 4, iclass 25, count 0 2006.257.19:28:06.46#ibcon#about to read 5, iclass 25, count 0 2006.257.19:28:06.46#ibcon#read 5, iclass 25, count 0 2006.257.19:28:06.46#ibcon#about to read 6, iclass 25, count 0 2006.257.19:28:06.46#ibcon#read 6, iclass 25, count 0 2006.257.19:28:06.46#ibcon#end of sib2, iclass 25, count 0 2006.257.19:28:06.46#ibcon#*mode == 0, iclass 25, count 0 2006.257.19:28:06.46#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.19:28:06.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.19:28:06.46#ibcon#*before write, iclass 25, count 0 2006.257.19:28:06.46#ibcon#enter sib2, iclass 25, count 0 2006.257.19:28:06.46#ibcon#flushed, iclass 25, count 0 2006.257.19:28:06.46#ibcon#about to write, iclass 25, count 0 2006.257.19:28:06.46#ibcon#wrote, iclass 25, count 0 2006.257.19:28:06.46#ibcon#about to read 3, iclass 25, count 0 2006.257.19:28:06.50#ibcon#read 3, iclass 25, count 0 2006.257.19:28:06.50#ibcon#about to read 4, iclass 25, count 0 2006.257.19:28:06.50#ibcon#read 4, iclass 25, count 0 2006.257.19:28:06.50#ibcon#about to read 5, iclass 25, count 0 2006.257.19:28:06.50#ibcon#read 5, iclass 25, count 0 2006.257.19:28:06.50#ibcon#about to read 6, iclass 25, count 0 2006.257.19:28:06.50#ibcon#read 6, iclass 25, count 0 2006.257.19:28:06.50#ibcon#end of sib2, iclass 25, count 0 2006.257.19:28:06.50#ibcon#*after write, iclass 25, count 0 2006.257.19:28:06.50#ibcon#*before return 0, iclass 25, count 0 2006.257.19:28:06.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:06.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:06.50#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.19:28:06.50#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.19:28:06.50$vck44/va=4,7 2006.257.19:28:06.50#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.19:28:06.50#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.19:28:06.50#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:06.50#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:06.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:06.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:06.56#ibcon#enter wrdev, iclass 27, count 2 2006.257.19:28:06.56#ibcon#first serial, iclass 27, count 2 2006.257.19:28:06.56#ibcon#enter sib2, iclass 27, count 2 2006.257.19:28:06.56#ibcon#flushed, iclass 27, count 2 2006.257.19:28:06.56#ibcon#about to write, iclass 27, count 2 2006.257.19:28:06.56#ibcon#wrote, iclass 27, count 2 2006.257.19:28:06.56#ibcon#about to read 3, iclass 27, count 2 2006.257.19:28:06.58#ibcon#read 3, iclass 27, count 2 2006.257.19:28:06.58#ibcon#about to read 4, iclass 27, count 2 2006.257.19:28:06.58#ibcon#read 4, iclass 27, count 2 2006.257.19:28:06.58#ibcon#about to read 5, iclass 27, count 2 2006.257.19:28:06.58#ibcon#read 5, iclass 27, count 2 2006.257.19:28:06.58#ibcon#about to read 6, iclass 27, count 2 2006.257.19:28:06.58#ibcon#read 6, iclass 27, count 2 2006.257.19:28:06.58#ibcon#end of sib2, iclass 27, count 2 2006.257.19:28:06.58#ibcon#*mode == 0, iclass 27, count 2 2006.257.19:28:06.58#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.19:28:06.58#ibcon#[25=AT04-07\r\n] 2006.257.19:28:06.58#ibcon#*before write, iclass 27, count 2 2006.257.19:28:06.58#ibcon#enter sib2, iclass 27, count 2 2006.257.19:28:06.58#ibcon#flushed, iclass 27, count 2 2006.257.19:28:06.58#ibcon#about to write, iclass 27, count 2 2006.257.19:28:06.58#ibcon#wrote, iclass 27, count 2 2006.257.19:28:06.58#ibcon#about to read 3, iclass 27, count 2 2006.257.19:28:06.61#ibcon#read 3, iclass 27, count 2 2006.257.19:28:06.61#ibcon#about to read 4, iclass 27, count 2 2006.257.19:28:06.61#ibcon#read 4, iclass 27, count 2 2006.257.19:28:06.61#ibcon#about to read 5, iclass 27, count 2 2006.257.19:28:06.61#ibcon#read 5, iclass 27, count 2 2006.257.19:28:06.61#ibcon#about to read 6, iclass 27, count 2 2006.257.19:28:06.61#ibcon#read 6, iclass 27, count 2 2006.257.19:28:06.61#ibcon#end of sib2, iclass 27, count 2 2006.257.19:28:06.61#ibcon#*after write, iclass 27, count 2 2006.257.19:28:06.61#ibcon#*before return 0, iclass 27, count 2 2006.257.19:28:06.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:06.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:06.61#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.19:28:06.61#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:06.61#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:06.73#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:06.73#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:06.73#ibcon#enter wrdev, iclass 27, count 0 2006.257.19:28:06.73#ibcon#first serial, iclass 27, count 0 2006.257.19:28:06.73#ibcon#enter sib2, iclass 27, count 0 2006.257.19:28:06.73#ibcon#flushed, iclass 27, count 0 2006.257.19:28:06.73#ibcon#about to write, iclass 27, count 0 2006.257.19:28:06.73#ibcon#wrote, iclass 27, count 0 2006.257.19:28:06.73#ibcon#about to read 3, iclass 27, count 0 2006.257.19:28:06.75#ibcon#read 3, iclass 27, count 0 2006.257.19:28:06.75#ibcon#about to read 4, iclass 27, count 0 2006.257.19:28:06.75#ibcon#read 4, iclass 27, count 0 2006.257.19:28:06.75#ibcon#about to read 5, iclass 27, count 0 2006.257.19:28:06.75#ibcon#read 5, iclass 27, count 0 2006.257.19:28:06.75#ibcon#about to read 6, iclass 27, count 0 2006.257.19:28:06.75#ibcon#read 6, iclass 27, count 0 2006.257.19:28:06.75#ibcon#end of sib2, iclass 27, count 0 2006.257.19:28:06.75#ibcon#*mode == 0, iclass 27, count 0 2006.257.19:28:06.75#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.19:28:06.75#ibcon#[25=USB\r\n] 2006.257.19:28:06.75#ibcon#*before write, iclass 27, count 0 2006.257.19:28:06.75#ibcon#enter sib2, iclass 27, count 0 2006.257.19:28:06.75#ibcon#flushed, iclass 27, count 0 2006.257.19:28:06.75#ibcon#about to write, iclass 27, count 0 2006.257.19:28:06.75#ibcon#wrote, iclass 27, count 0 2006.257.19:28:06.75#ibcon#about to read 3, iclass 27, count 0 2006.257.19:28:06.78#ibcon#read 3, iclass 27, count 0 2006.257.19:28:06.78#ibcon#about to read 4, iclass 27, count 0 2006.257.19:28:06.78#ibcon#read 4, iclass 27, count 0 2006.257.19:28:06.78#ibcon#about to read 5, iclass 27, count 0 2006.257.19:28:06.78#ibcon#read 5, iclass 27, count 0 2006.257.19:28:06.78#ibcon#about to read 6, iclass 27, count 0 2006.257.19:28:06.78#ibcon#read 6, iclass 27, count 0 2006.257.19:28:06.78#ibcon#end of sib2, iclass 27, count 0 2006.257.19:28:06.78#ibcon#*after write, iclass 27, count 0 2006.257.19:28:06.78#ibcon#*before return 0, iclass 27, count 0 2006.257.19:28:06.78#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:06.78#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:06.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.19:28:06.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.19:28:06.78$vck44/valo=5,734.99 2006.257.19:28:06.78#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.19:28:06.78#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.19:28:06.78#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:06.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:06.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:06.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:06.78#ibcon#enter wrdev, iclass 29, count 0 2006.257.19:28:06.78#ibcon#first serial, iclass 29, count 0 2006.257.19:28:06.78#ibcon#enter sib2, iclass 29, count 0 2006.257.19:28:06.78#ibcon#flushed, iclass 29, count 0 2006.257.19:28:06.78#ibcon#about to write, iclass 29, count 0 2006.257.19:28:06.78#ibcon#wrote, iclass 29, count 0 2006.257.19:28:06.78#ibcon#about to read 3, iclass 29, count 0 2006.257.19:28:06.80#ibcon#read 3, iclass 29, count 0 2006.257.19:28:06.80#ibcon#about to read 4, iclass 29, count 0 2006.257.19:28:06.80#ibcon#read 4, iclass 29, count 0 2006.257.19:28:06.80#ibcon#about to read 5, iclass 29, count 0 2006.257.19:28:06.80#ibcon#read 5, iclass 29, count 0 2006.257.19:28:06.80#ibcon#about to read 6, iclass 29, count 0 2006.257.19:28:06.80#ibcon#read 6, iclass 29, count 0 2006.257.19:28:06.80#ibcon#end of sib2, iclass 29, count 0 2006.257.19:28:06.80#ibcon#*mode == 0, iclass 29, count 0 2006.257.19:28:06.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.19:28:06.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.19:28:06.80#ibcon#*before write, iclass 29, count 0 2006.257.19:28:06.80#ibcon#enter sib2, iclass 29, count 0 2006.257.19:28:06.80#ibcon#flushed, iclass 29, count 0 2006.257.19:28:06.80#ibcon#about to write, iclass 29, count 0 2006.257.19:28:06.80#ibcon#wrote, iclass 29, count 0 2006.257.19:28:06.80#ibcon#about to read 3, iclass 29, count 0 2006.257.19:28:06.84#ibcon#read 3, iclass 29, count 0 2006.257.19:28:06.84#ibcon#about to read 4, iclass 29, count 0 2006.257.19:28:06.84#ibcon#read 4, iclass 29, count 0 2006.257.19:28:06.84#ibcon#about to read 5, iclass 29, count 0 2006.257.19:28:06.84#ibcon#read 5, iclass 29, count 0 2006.257.19:28:06.84#ibcon#about to read 6, iclass 29, count 0 2006.257.19:28:06.84#ibcon#read 6, iclass 29, count 0 2006.257.19:28:06.84#ibcon#end of sib2, iclass 29, count 0 2006.257.19:28:06.84#ibcon#*after write, iclass 29, count 0 2006.257.19:28:06.84#ibcon#*before return 0, iclass 29, count 0 2006.257.19:28:06.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:06.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:06.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.19:28:06.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.19:28:06.84$vck44/va=5,4 2006.257.19:28:06.84#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.19:28:06.84#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.19:28:06.84#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:06.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:06.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:06.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:06.90#ibcon#enter wrdev, iclass 31, count 2 2006.257.19:28:06.90#ibcon#first serial, iclass 31, count 2 2006.257.19:28:06.90#ibcon#enter sib2, iclass 31, count 2 2006.257.19:28:06.90#ibcon#flushed, iclass 31, count 2 2006.257.19:28:06.90#ibcon#about to write, iclass 31, count 2 2006.257.19:28:06.90#ibcon#wrote, iclass 31, count 2 2006.257.19:28:06.90#ibcon#about to read 3, iclass 31, count 2 2006.257.19:28:06.92#ibcon#read 3, iclass 31, count 2 2006.257.19:28:06.92#ibcon#about to read 4, iclass 31, count 2 2006.257.19:28:06.92#ibcon#read 4, iclass 31, count 2 2006.257.19:28:06.92#ibcon#about to read 5, iclass 31, count 2 2006.257.19:28:06.92#ibcon#read 5, iclass 31, count 2 2006.257.19:28:06.92#ibcon#about to read 6, iclass 31, count 2 2006.257.19:28:06.92#ibcon#read 6, iclass 31, count 2 2006.257.19:28:06.92#ibcon#end of sib2, iclass 31, count 2 2006.257.19:28:06.92#ibcon#*mode == 0, iclass 31, count 2 2006.257.19:28:06.92#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.19:28:06.92#ibcon#[25=AT05-04\r\n] 2006.257.19:28:06.92#ibcon#*before write, iclass 31, count 2 2006.257.19:28:06.92#ibcon#enter sib2, iclass 31, count 2 2006.257.19:28:06.92#ibcon#flushed, iclass 31, count 2 2006.257.19:28:06.92#ibcon#about to write, iclass 31, count 2 2006.257.19:28:06.92#ibcon#wrote, iclass 31, count 2 2006.257.19:28:06.92#ibcon#about to read 3, iclass 31, count 2 2006.257.19:28:06.95#ibcon#read 3, iclass 31, count 2 2006.257.19:28:06.95#ibcon#about to read 4, iclass 31, count 2 2006.257.19:28:06.95#ibcon#read 4, iclass 31, count 2 2006.257.19:28:06.95#ibcon#about to read 5, iclass 31, count 2 2006.257.19:28:06.95#ibcon#read 5, iclass 31, count 2 2006.257.19:28:06.95#ibcon#about to read 6, iclass 31, count 2 2006.257.19:28:06.95#ibcon#read 6, iclass 31, count 2 2006.257.19:28:06.95#ibcon#end of sib2, iclass 31, count 2 2006.257.19:28:06.95#ibcon#*after write, iclass 31, count 2 2006.257.19:28:06.95#ibcon#*before return 0, iclass 31, count 2 2006.257.19:28:06.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:06.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:06.95#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.19:28:06.95#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:06.95#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:07.07#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:07.07#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:07.07#ibcon#enter wrdev, iclass 31, count 0 2006.257.19:28:07.07#ibcon#first serial, iclass 31, count 0 2006.257.19:28:07.07#ibcon#enter sib2, iclass 31, count 0 2006.257.19:28:07.07#ibcon#flushed, iclass 31, count 0 2006.257.19:28:07.07#ibcon#about to write, iclass 31, count 0 2006.257.19:28:07.07#ibcon#wrote, iclass 31, count 0 2006.257.19:28:07.07#ibcon#about to read 3, iclass 31, count 0 2006.257.19:28:07.09#ibcon#read 3, iclass 31, count 0 2006.257.19:28:07.09#ibcon#about to read 4, iclass 31, count 0 2006.257.19:28:07.09#ibcon#read 4, iclass 31, count 0 2006.257.19:28:07.09#ibcon#about to read 5, iclass 31, count 0 2006.257.19:28:07.09#ibcon#read 5, iclass 31, count 0 2006.257.19:28:07.09#ibcon#about to read 6, iclass 31, count 0 2006.257.19:28:07.09#ibcon#read 6, iclass 31, count 0 2006.257.19:28:07.09#ibcon#end of sib2, iclass 31, count 0 2006.257.19:28:07.09#ibcon#*mode == 0, iclass 31, count 0 2006.257.19:28:07.09#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.19:28:07.09#ibcon#[25=USB\r\n] 2006.257.19:28:07.09#ibcon#*before write, iclass 31, count 0 2006.257.19:28:07.09#ibcon#enter sib2, iclass 31, count 0 2006.257.19:28:07.09#ibcon#flushed, iclass 31, count 0 2006.257.19:28:07.09#ibcon#about to write, iclass 31, count 0 2006.257.19:28:07.09#ibcon#wrote, iclass 31, count 0 2006.257.19:28:07.09#ibcon#about to read 3, iclass 31, count 0 2006.257.19:28:07.12#ibcon#read 3, iclass 31, count 0 2006.257.19:28:07.12#ibcon#about to read 4, iclass 31, count 0 2006.257.19:28:07.12#ibcon#read 4, iclass 31, count 0 2006.257.19:28:07.12#ibcon#about to read 5, iclass 31, count 0 2006.257.19:28:07.12#ibcon#read 5, iclass 31, count 0 2006.257.19:28:07.12#ibcon#about to read 6, iclass 31, count 0 2006.257.19:28:07.12#ibcon#read 6, iclass 31, count 0 2006.257.19:28:07.12#ibcon#end of sib2, iclass 31, count 0 2006.257.19:28:07.12#ibcon#*after write, iclass 31, count 0 2006.257.19:28:07.12#ibcon#*before return 0, iclass 31, count 0 2006.257.19:28:07.12#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:07.12#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:07.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.19:28:07.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.19:28:07.12$vck44/valo=6,814.99 2006.257.19:28:07.12#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.19:28:07.12#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.19:28:07.12#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:07.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:07.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:07.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:07.12#ibcon#enter wrdev, iclass 33, count 0 2006.257.19:28:07.12#ibcon#first serial, iclass 33, count 0 2006.257.19:28:07.12#ibcon#enter sib2, iclass 33, count 0 2006.257.19:28:07.12#ibcon#flushed, iclass 33, count 0 2006.257.19:28:07.12#ibcon#about to write, iclass 33, count 0 2006.257.19:28:07.12#ibcon#wrote, iclass 33, count 0 2006.257.19:28:07.12#ibcon#about to read 3, iclass 33, count 0 2006.257.19:28:07.14#ibcon#read 3, iclass 33, count 0 2006.257.19:28:07.14#ibcon#about to read 4, iclass 33, count 0 2006.257.19:28:07.14#ibcon#read 4, iclass 33, count 0 2006.257.19:28:07.14#ibcon#about to read 5, iclass 33, count 0 2006.257.19:28:07.14#ibcon#read 5, iclass 33, count 0 2006.257.19:28:07.14#ibcon#about to read 6, iclass 33, count 0 2006.257.19:28:07.14#ibcon#read 6, iclass 33, count 0 2006.257.19:28:07.14#ibcon#end of sib2, iclass 33, count 0 2006.257.19:28:07.14#ibcon#*mode == 0, iclass 33, count 0 2006.257.19:28:07.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.19:28:07.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.19:28:07.14#ibcon#*before write, iclass 33, count 0 2006.257.19:28:07.14#ibcon#enter sib2, iclass 33, count 0 2006.257.19:28:07.14#ibcon#flushed, iclass 33, count 0 2006.257.19:28:07.14#ibcon#about to write, iclass 33, count 0 2006.257.19:28:07.14#ibcon#wrote, iclass 33, count 0 2006.257.19:28:07.14#ibcon#about to read 3, iclass 33, count 0 2006.257.19:28:07.18#ibcon#read 3, iclass 33, count 0 2006.257.19:28:07.18#ibcon#about to read 4, iclass 33, count 0 2006.257.19:28:07.18#ibcon#read 4, iclass 33, count 0 2006.257.19:28:07.18#ibcon#about to read 5, iclass 33, count 0 2006.257.19:28:07.18#ibcon#read 5, iclass 33, count 0 2006.257.19:28:07.18#ibcon#about to read 6, iclass 33, count 0 2006.257.19:28:07.18#ibcon#read 6, iclass 33, count 0 2006.257.19:28:07.18#ibcon#end of sib2, iclass 33, count 0 2006.257.19:28:07.18#ibcon#*after write, iclass 33, count 0 2006.257.19:28:07.18#ibcon#*before return 0, iclass 33, count 0 2006.257.19:28:07.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:07.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:07.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.19:28:07.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.19:28:07.18$vck44/va=6,4 2006.257.19:28:07.18#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.19:28:07.18#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.19:28:07.18#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:07.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:07.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:07.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:07.24#ibcon#enter wrdev, iclass 35, count 2 2006.257.19:28:07.24#ibcon#first serial, iclass 35, count 2 2006.257.19:28:07.24#ibcon#enter sib2, iclass 35, count 2 2006.257.19:28:07.24#ibcon#flushed, iclass 35, count 2 2006.257.19:28:07.24#ibcon#about to write, iclass 35, count 2 2006.257.19:28:07.24#ibcon#wrote, iclass 35, count 2 2006.257.19:28:07.24#ibcon#about to read 3, iclass 35, count 2 2006.257.19:28:07.26#ibcon#read 3, iclass 35, count 2 2006.257.19:28:07.26#ibcon#about to read 4, iclass 35, count 2 2006.257.19:28:07.26#ibcon#read 4, iclass 35, count 2 2006.257.19:28:07.26#ibcon#about to read 5, iclass 35, count 2 2006.257.19:28:07.26#ibcon#read 5, iclass 35, count 2 2006.257.19:28:07.26#ibcon#about to read 6, iclass 35, count 2 2006.257.19:28:07.26#ibcon#read 6, iclass 35, count 2 2006.257.19:28:07.26#ibcon#end of sib2, iclass 35, count 2 2006.257.19:28:07.26#ibcon#*mode == 0, iclass 35, count 2 2006.257.19:28:07.26#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.19:28:07.26#ibcon#[25=AT06-04\r\n] 2006.257.19:28:07.26#ibcon#*before write, iclass 35, count 2 2006.257.19:28:07.26#ibcon#enter sib2, iclass 35, count 2 2006.257.19:28:07.26#ibcon#flushed, iclass 35, count 2 2006.257.19:28:07.26#ibcon#about to write, iclass 35, count 2 2006.257.19:28:07.26#ibcon#wrote, iclass 35, count 2 2006.257.19:28:07.26#ibcon#about to read 3, iclass 35, count 2 2006.257.19:28:07.29#ibcon#read 3, iclass 35, count 2 2006.257.19:28:07.29#ibcon#about to read 4, iclass 35, count 2 2006.257.19:28:07.29#ibcon#read 4, iclass 35, count 2 2006.257.19:28:07.29#ibcon#about to read 5, iclass 35, count 2 2006.257.19:28:07.29#ibcon#read 5, iclass 35, count 2 2006.257.19:28:07.29#ibcon#about to read 6, iclass 35, count 2 2006.257.19:28:07.29#ibcon#read 6, iclass 35, count 2 2006.257.19:28:07.29#ibcon#end of sib2, iclass 35, count 2 2006.257.19:28:07.29#ibcon#*after write, iclass 35, count 2 2006.257.19:28:07.29#ibcon#*before return 0, iclass 35, count 2 2006.257.19:28:07.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:07.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:07.29#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.19:28:07.29#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:07.29#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:07.41#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:07.41#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:07.41#ibcon#enter wrdev, iclass 35, count 0 2006.257.19:28:07.41#ibcon#first serial, iclass 35, count 0 2006.257.19:28:07.41#ibcon#enter sib2, iclass 35, count 0 2006.257.19:28:07.41#ibcon#flushed, iclass 35, count 0 2006.257.19:28:07.41#ibcon#about to write, iclass 35, count 0 2006.257.19:28:07.41#ibcon#wrote, iclass 35, count 0 2006.257.19:28:07.41#ibcon#about to read 3, iclass 35, count 0 2006.257.19:28:07.43#ibcon#read 3, iclass 35, count 0 2006.257.19:28:07.43#ibcon#about to read 4, iclass 35, count 0 2006.257.19:28:07.43#ibcon#read 4, iclass 35, count 0 2006.257.19:28:07.43#ibcon#about to read 5, iclass 35, count 0 2006.257.19:28:07.43#ibcon#read 5, iclass 35, count 0 2006.257.19:28:07.43#ibcon#about to read 6, iclass 35, count 0 2006.257.19:28:07.43#ibcon#read 6, iclass 35, count 0 2006.257.19:28:07.43#ibcon#end of sib2, iclass 35, count 0 2006.257.19:28:07.43#ibcon#*mode == 0, iclass 35, count 0 2006.257.19:28:07.43#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.19:28:07.43#ibcon#[25=USB\r\n] 2006.257.19:28:07.43#ibcon#*before write, iclass 35, count 0 2006.257.19:28:07.43#ibcon#enter sib2, iclass 35, count 0 2006.257.19:28:07.43#ibcon#flushed, iclass 35, count 0 2006.257.19:28:07.43#ibcon#about to write, iclass 35, count 0 2006.257.19:28:07.43#ibcon#wrote, iclass 35, count 0 2006.257.19:28:07.43#ibcon#about to read 3, iclass 35, count 0 2006.257.19:28:07.46#ibcon#read 3, iclass 35, count 0 2006.257.19:28:07.46#ibcon#about to read 4, iclass 35, count 0 2006.257.19:28:07.46#ibcon#read 4, iclass 35, count 0 2006.257.19:28:07.46#ibcon#about to read 5, iclass 35, count 0 2006.257.19:28:07.46#ibcon#read 5, iclass 35, count 0 2006.257.19:28:07.46#ibcon#about to read 6, iclass 35, count 0 2006.257.19:28:07.46#ibcon#read 6, iclass 35, count 0 2006.257.19:28:07.46#ibcon#end of sib2, iclass 35, count 0 2006.257.19:28:07.46#ibcon#*after write, iclass 35, count 0 2006.257.19:28:07.46#ibcon#*before return 0, iclass 35, count 0 2006.257.19:28:07.46#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:07.46#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:07.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.19:28:07.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.19:28:07.46$vck44/valo=7,864.99 2006.257.19:28:07.46#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.19:28:07.46#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.19:28:07.46#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:07.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:07.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:07.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:07.46#ibcon#enter wrdev, iclass 37, count 0 2006.257.19:28:07.46#ibcon#first serial, iclass 37, count 0 2006.257.19:28:07.46#ibcon#enter sib2, iclass 37, count 0 2006.257.19:28:07.46#ibcon#flushed, iclass 37, count 0 2006.257.19:28:07.46#ibcon#about to write, iclass 37, count 0 2006.257.19:28:07.46#ibcon#wrote, iclass 37, count 0 2006.257.19:28:07.46#ibcon#about to read 3, iclass 37, count 0 2006.257.19:28:07.48#ibcon#read 3, iclass 37, count 0 2006.257.19:28:07.48#ibcon#about to read 4, iclass 37, count 0 2006.257.19:28:07.48#ibcon#read 4, iclass 37, count 0 2006.257.19:28:07.48#ibcon#about to read 5, iclass 37, count 0 2006.257.19:28:07.48#ibcon#read 5, iclass 37, count 0 2006.257.19:28:07.48#ibcon#about to read 6, iclass 37, count 0 2006.257.19:28:07.48#ibcon#read 6, iclass 37, count 0 2006.257.19:28:07.48#ibcon#end of sib2, iclass 37, count 0 2006.257.19:28:07.48#ibcon#*mode == 0, iclass 37, count 0 2006.257.19:28:07.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.19:28:07.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.19:28:07.48#ibcon#*before write, iclass 37, count 0 2006.257.19:28:07.48#ibcon#enter sib2, iclass 37, count 0 2006.257.19:28:07.48#ibcon#flushed, iclass 37, count 0 2006.257.19:28:07.48#ibcon#about to write, iclass 37, count 0 2006.257.19:28:07.48#ibcon#wrote, iclass 37, count 0 2006.257.19:28:07.48#ibcon#about to read 3, iclass 37, count 0 2006.257.19:28:07.52#ibcon#read 3, iclass 37, count 0 2006.257.19:28:07.52#ibcon#about to read 4, iclass 37, count 0 2006.257.19:28:07.52#ibcon#read 4, iclass 37, count 0 2006.257.19:28:07.52#ibcon#about to read 5, iclass 37, count 0 2006.257.19:28:07.52#ibcon#read 5, iclass 37, count 0 2006.257.19:28:07.52#ibcon#about to read 6, iclass 37, count 0 2006.257.19:28:07.52#ibcon#read 6, iclass 37, count 0 2006.257.19:28:07.52#ibcon#end of sib2, iclass 37, count 0 2006.257.19:28:07.52#ibcon#*after write, iclass 37, count 0 2006.257.19:28:07.52#ibcon#*before return 0, iclass 37, count 0 2006.257.19:28:07.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:07.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:07.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.19:28:07.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.19:28:07.52$vck44/va=7,4 2006.257.19:28:07.52#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.19:28:07.52#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.19:28:07.52#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:07.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:07.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:07.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:07.58#ibcon#enter wrdev, iclass 39, count 2 2006.257.19:28:07.58#ibcon#first serial, iclass 39, count 2 2006.257.19:28:07.58#ibcon#enter sib2, iclass 39, count 2 2006.257.19:28:07.58#ibcon#flushed, iclass 39, count 2 2006.257.19:28:07.58#ibcon#about to write, iclass 39, count 2 2006.257.19:28:07.58#ibcon#wrote, iclass 39, count 2 2006.257.19:28:07.58#ibcon#about to read 3, iclass 39, count 2 2006.257.19:28:07.60#ibcon#read 3, iclass 39, count 2 2006.257.19:28:07.60#ibcon#about to read 4, iclass 39, count 2 2006.257.19:28:07.60#ibcon#read 4, iclass 39, count 2 2006.257.19:28:07.60#ibcon#about to read 5, iclass 39, count 2 2006.257.19:28:07.60#ibcon#read 5, iclass 39, count 2 2006.257.19:28:07.60#ibcon#about to read 6, iclass 39, count 2 2006.257.19:28:07.60#ibcon#read 6, iclass 39, count 2 2006.257.19:28:07.60#ibcon#end of sib2, iclass 39, count 2 2006.257.19:28:07.60#ibcon#*mode == 0, iclass 39, count 2 2006.257.19:28:07.60#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.19:28:07.60#ibcon#[25=AT07-04\r\n] 2006.257.19:28:07.60#ibcon#*before write, iclass 39, count 2 2006.257.19:28:07.60#ibcon#enter sib2, iclass 39, count 2 2006.257.19:28:07.60#ibcon#flushed, iclass 39, count 2 2006.257.19:28:07.60#ibcon#about to write, iclass 39, count 2 2006.257.19:28:07.60#ibcon#wrote, iclass 39, count 2 2006.257.19:28:07.60#ibcon#about to read 3, iclass 39, count 2 2006.257.19:28:07.63#ibcon#read 3, iclass 39, count 2 2006.257.19:28:07.63#ibcon#about to read 4, iclass 39, count 2 2006.257.19:28:07.63#ibcon#read 4, iclass 39, count 2 2006.257.19:28:07.63#ibcon#about to read 5, iclass 39, count 2 2006.257.19:28:07.63#ibcon#read 5, iclass 39, count 2 2006.257.19:28:07.63#ibcon#about to read 6, iclass 39, count 2 2006.257.19:28:07.63#ibcon#read 6, iclass 39, count 2 2006.257.19:28:07.63#ibcon#end of sib2, iclass 39, count 2 2006.257.19:28:07.63#ibcon#*after write, iclass 39, count 2 2006.257.19:28:07.63#ibcon#*before return 0, iclass 39, count 2 2006.257.19:28:07.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:07.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:07.63#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.19:28:07.63#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:07.63#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:07.75#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:07.75#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:07.75#ibcon#enter wrdev, iclass 39, count 0 2006.257.19:28:07.75#ibcon#first serial, iclass 39, count 0 2006.257.19:28:07.75#ibcon#enter sib2, iclass 39, count 0 2006.257.19:28:07.75#ibcon#flushed, iclass 39, count 0 2006.257.19:28:07.75#ibcon#about to write, iclass 39, count 0 2006.257.19:28:07.75#ibcon#wrote, iclass 39, count 0 2006.257.19:28:07.75#ibcon#about to read 3, iclass 39, count 0 2006.257.19:28:07.77#ibcon#read 3, iclass 39, count 0 2006.257.19:28:07.77#ibcon#about to read 4, iclass 39, count 0 2006.257.19:28:07.77#ibcon#read 4, iclass 39, count 0 2006.257.19:28:07.77#ibcon#about to read 5, iclass 39, count 0 2006.257.19:28:07.77#ibcon#read 5, iclass 39, count 0 2006.257.19:28:07.77#ibcon#about to read 6, iclass 39, count 0 2006.257.19:28:07.77#ibcon#read 6, iclass 39, count 0 2006.257.19:28:07.77#ibcon#end of sib2, iclass 39, count 0 2006.257.19:28:07.77#ibcon#*mode == 0, iclass 39, count 0 2006.257.19:28:07.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.19:28:07.77#ibcon#[25=USB\r\n] 2006.257.19:28:07.77#ibcon#*before write, iclass 39, count 0 2006.257.19:28:07.77#ibcon#enter sib2, iclass 39, count 0 2006.257.19:28:07.77#ibcon#flushed, iclass 39, count 0 2006.257.19:28:07.77#ibcon#about to write, iclass 39, count 0 2006.257.19:28:07.77#ibcon#wrote, iclass 39, count 0 2006.257.19:28:07.77#ibcon#about to read 3, iclass 39, count 0 2006.257.19:28:07.80#ibcon#read 3, iclass 39, count 0 2006.257.19:28:07.80#ibcon#about to read 4, iclass 39, count 0 2006.257.19:28:07.80#ibcon#read 4, iclass 39, count 0 2006.257.19:28:07.80#ibcon#about to read 5, iclass 39, count 0 2006.257.19:28:07.80#ibcon#read 5, iclass 39, count 0 2006.257.19:28:07.80#ibcon#about to read 6, iclass 39, count 0 2006.257.19:28:07.80#ibcon#read 6, iclass 39, count 0 2006.257.19:28:07.80#ibcon#end of sib2, iclass 39, count 0 2006.257.19:28:07.80#ibcon#*after write, iclass 39, count 0 2006.257.19:28:07.80#ibcon#*before return 0, iclass 39, count 0 2006.257.19:28:07.80#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:07.80#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:07.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.19:28:07.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.19:28:07.80$vck44/valo=8,884.99 2006.257.19:28:07.80#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.19:28:07.80#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.19:28:07.80#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:07.80#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:07.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:07.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:07.80#ibcon#enter wrdev, iclass 3, count 0 2006.257.19:28:07.80#ibcon#first serial, iclass 3, count 0 2006.257.19:28:07.80#ibcon#enter sib2, iclass 3, count 0 2006.257.19:28:07.80#ibcon#flushed, iclass 3, count 0 2006.257.19:28:07.80#ibcon#about to write, iclass 3, count 0 2006.257.19:28:07.80#ibcon#wrote, iclass 3, count 0 2006.257.19:28:07.80#ibcon#about to read 3, iclass 3, count 0 2006.257.19:28:07.82#ibcon#read 3, iclass 3, count 0 2006.257.19:28:07.82#ibcon#about to read 4, iclass 3, count 0 2006.257.19:28:07.82#ibcon#read 4, iclass 3, count 0 2006.257.19:28:07.82#ibcon#about to read 5, iclass 3, count 0 2006.257.19:28:07.82#ibcon#read 5, iclass 3, count 0 2006.257.19:28:07.82#ibcon#about to read 6, iclass 3, count 0 2006.257.19:28:07.82#ibcon#read 6, iclass 3, count 0 2006.257.19:28:07.82#ibcon#end of sib2, iclass 3, count 0 2006.257.19:28:07.82#ibcon#*mode == 0, iclass 3, count 0 2006.257.19:28:07.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.19:28:07.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.19:28:07.82#ibcon#*before write, iclass 3, count 0 2006.257.19:28:07.82#ibcon#enter sib2, iclass 3, count 0 2006.257.19:28:07.82#ibcon#flushed, iclass 3, count 0 2006.257.19:28:07.82#ibcon#about to write, iclass 3, count 0 2006.257.19:28:07.82#ibcon#wrote, iclass 3, count 0 2006.257.19:28:07.82#ibcon#about to read 3, iclass 3, count 0 2006.257.19:28:07.86#ibcon#read 3, iclass 3, count 0 2006.257.19:28:07.86#ibcon#about to read 4, iclass 3, count 0 2006.257.19:28:07.86#ibcon#read 4, iclass 3, count 0 2006.257.19:28:07.86#ibcon#about to read 5, iclass 3, count 0 2006.257.19:28:07.86#ibcon#read 5, iclass 3, count 0 2006.257.19:28:07.86#ibcon#about to read 6, iclass 3, count 0 2006.257.19:28:07.86#ibcon#read 6, iclass 3, count 0 2006.257.19:28:07.86#ibcon#end of sib2, iclass 3, count 0 2006.257.19:28:07.86#ibcon#*after write, iclass 3, count 0 2006.257.19:28:07.86#ibcon#*before return 0, iclass 3, count 0 2006.257.19:28:07.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:07.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:07.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.19:28:07.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.19:28:07.86$vck44/va=8,4 2006.257.19:28:07.86#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.19:28:07.86#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.19:28:07.86#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:07.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:28:07.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:28:07.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:28:07.92#ibcon#enter wrdev, iclass 5, count 2 2006.257.19:28:07.92#ibcon#first serial, iclass 5, count 2 2006.257.19:28:07.92#ibcon#enter sib2, iclass 5, count 2 2006.257.19:28:07.92#ibcon#flushed, iclass 5, count 2 2006.257.19:28:07.92#ibcon#about to write, iclass 5, count 2 2006.257.19:28:07.92#ibcon#wrote, iclass 5, count 2 2006.257.19:28:07.92#ibcon#about to read 3, iclass 5, count 2 2006.257.19:28:07.94#ibcon#read 3, iclass 5, count 2 2006.257.19:28:07.94#ibcon#about to read 4, iclass 5, count 2 2006.257.19:28:07.94#ibcon#read 4, iclass 5, count 2 2006.257.19:28:07.94#ibcon#about to read 5, iclass 5, count 2 2006.257.19:28:07.94#ibcon#read 5, iclass 5, count 2 2006.257.19:28:07.94#ibcon#about to read 6, iclass 5, count 2 2006.257.19:28:07.94#ibcon#read 6, iclass 5, count 2 2006.257.19:28:07.94#ibcon#end of sib2, iclass 5, count 2 2006.257.19:28:07.94#ibcon#*mode == 0, iclass 5, count 2 2006.257.19:28:07.94#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.19:28:07.94#ibcon#[25=AT08-04\r\n] 2006.257.19:28:07.94#ibcon#*before write, iclass 5, count 2 2006.257.19:28:07.94#ibcon#enter sib2, iclass 5, count 2 2006.257.19:28:07.94#ibcon#flushed, iclass 5, count 2 2006.257.19:28:07.94#ibcon#about to write, iclass 5, count 2 2006.257.19:28:07.94#ibcon#wrote, iclass 5, count 2 2006.257.19:28:07.94#ibcon#about to read 3, iclass 5, count 2 2006.257.19:28:07.97#ibcon#read 3, iclass 5, count 2 2006.257.19:28:07.97#ibcon#about to read 4, iclass 5, count 2 2006.257.19:28:07.97#ibcon#read 4, iclass 5, count 2 2006.257.19:28:07.97#ibcon#about to read 5, iclass 5, count 2 2006.257.19:28:07.97#ibcon#read 5, iclass 5, count 2 2006.257.19:28:07.97#ibcon#about to read 6, iclass 5, count 2 2006.257.19:28:07.97#ibcon#read 6, iclass 5, count 2 2006.257.19:28:07.97#ibcon#end of sib2, iclass 5, count 2 2006.257.19:28:07.97#ibcon#*after write, iclass 5, count 2 2006.257.19:28:07.97#ibcon#*before return 0, iclass 5, count 2 2006.257.19:28:07.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:28:07.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:28:07.97#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.19:28:07.97#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:07.97#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:28:08.09#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:28:08.09#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:28:08.09#ibcon#enter wrdev, iclass 5, count 0 2006.257.19:28:08.09#ibcon#first serial, iclass 5, count 0 2006.257.19:28:08.09#ibcon#enter sib2, iclass 5, count 0 2006.257.19:28:08.09#ibcon#flushed, iclass 5, count 0 2006.257.19:28:08.09#ibcon#about to write, iclass 5, count 0 2006.257.19:28:08.09#ibcon#wrote, iclass 5, count 0 2006.257.19:28:08.09#ibcon#about to read 3, iclass 5, count 0 2006.257.19:28:08.11#ibcon#read 3, iclass 5, count 0 2006.257.19:28:08.11#ibcon#about to read 4, iclass 5, count 0 2006.257.19:28:08.11#ibcon#read 4, iclass 5, count 0 2006.257.19:28:08.11#ibcon#about to read 5, iclass 5, count 0 2006.257.19:28:08.11#ibcon#read 5, iclass 5, count 0 2006.257.19:28:08.11#ibcon#about to read 6, iclass 5, count 0 2006.257.19:28:08.11#ibcon#read 6, iclass 5, count 0 2006.257.19:28:08.11#ibcon#end of sib2, iclass 5, count 0 2006.257.19:28:08.11#ibcon#*mode == 0, iclass 5, count 0 2006.257.19:28:08.11#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.19:28:08.11#ibcon#[25=USB\r\n] 2006.257.19:28:08.11#ibcon#*before write, iclass 5, count 0 2006.257.19:28:08.11#ibcon#enter sib2, iclass 5, count 0 2006.257.19:28:08.11#ibcon#flushed, iclass 5, count 0 2006.257.19:28:08.11#ibcon#about to write, iclass 5, count 0 2006.257.19:28:08.11#ibcon#wrote, iclass 5, count 0 2006.257.19:28:08.11#ibcon#about to read 3, iclass 5, count 0 2006.257.19:28:08.14#ibcon#read 3, iclass 5, count 0 2006.257.19:28:08.14#ibcon#about to read 4, iclass 5, count 0 2006.257.19:28:08.14#ibcon#read 4, iclass 5, count 0 2006.257.19:28:08.14#ibcon#about to read 5, iclass 5, count 0 2006.257.19:28:08.14#ibcon#read 5, iclass 5, count 0 2006.257.19:28:08.14#ibcon#about to read 6, iclass 5, count 0 2006.257.19:28:08.14#ibcon#read 6, iclass 5, count 0 2006.257.19:28:08.14#ibcon#end of sib2, iclass 5, count 0 2006.257.19:28:08.14#ibcon#*after write, iclass 5, count 0 2006.257.19:28:08.14#ibcon#*before return 0, iclass 5, count 0 2006.257.19:28:08.14#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:28:08.14#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:28:08.14#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.19:28:08.14#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.19:28:08.14$vck44/vblo=1,629.99 2006.257.19:28:08.14#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.19:28:08.14#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.19:28:08.14#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:08.14#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:28:08.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:28:08.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:28:08.14#ibcon#enter wrdev, iclass 7, count 0 2006.257.19:28:08.14#ibcon#first serial, iclass 7, count 0 2006.257.19:28:08.14#ibcon#enter sib2, iclass 7, count 0 2006.257.19:28:08.14#ibcon#flushed, iclass 7, count 0 2006.257.19:28:08.14#ibcon#about to write, iclass 7, count 0 2006.257.19:28:08.14#ibcon#wrote, iclass 7, count 0 2006.257.19:28:08.14#ibcon#about to read 3, iclass 7, count 0 2006.257.19:28:08.16#ibcon#read 3, iclass 7, count 0 2006.257.19:28:08.16#ibcon#about to read 4, iclass 7, count 0 2006.257.19:28:08.16#ibcon#read 4, iclass 7, count 0 2006.257.19:28:08.16#ibcon#about to read 5, iclass 7, count 0 2006.257.19:28:08.16#ibcon#read 5, iclass 7, count 0 2006.257.19:28:08.16#ibcon#about to read 6, iclass 7, count 0 2006.257.19:28:08.16#ibcon#read 6, iclass 7, count 0 2006.257.19:28:08.16#ibcon#end of sib2, iclass 7, count 0 2006.257.19:28:08.16#ibcon#*mode == 0, iclass 7, count 0 2006.257.19:28:08.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.19:28:08.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.19:28:08.16#ibcon#*before write, iclass 7, count 0 2006.257.19:28:08.16#ibcon#enter sib2, iclass 7, count 0 2006.257.19:28:08.16#ibcon#flushed, iclass 7, count 0 2006.257.19:28:08.16#ibcon#about to write, iclass 7, count 0 2006.257.19:28:08.16#ibcon#wrote, iclass 7, count 0 2006.257.19:28:08.16#ibcon#about to read 3, iclass 7, count 0 2006.257.19:28:08.20#ibcon#read 3, iclass 7, count 0 2006.257.19:28:08.20#ibcon#about to read 4, iclass 7, count 0 2006.257.19:28:08.20#ibcon#read 4, iclass 7, count 0 2006.257.19:28:08.20#ibcon#about to read 5, iclass 7, count 0 2006.257.19:28:08.20#ibcon#read 5, iclass 7, count 0 2006.257.19:28:08.20#ibcon#about to read 6, iclass 7, count 0 2006.257.19:28:08.20#ibcon#read 6, iclass 7, count 0 2006.257.19:28:08.20#ibcon#end of sib2, iclass 7, count 0 2006.257.19:28:08.20#ibcon#*after write, iclass 7, count 0 2006.257.19:28:08.20#ibcon#*before return 0, iclass 7, count 0 2006.257.19:28:08.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:28:08.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:28:08.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.19:28:08.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.19:28:08.20$vck44/vb=1,4 2006.257.19:28:08.20#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.19:28:08.20#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.19:28:08.20#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:08.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:28:08.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:28:08.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:28:08.20#ibcon#enter wrdev, iclass 11, count 2 2006.257.19:28:08.20#ibcon#first serial, iclass 11, count 2 2006.257.19:28:08.20#ibcon#enter sib2, iclass 11, count 2 2006.257.19:28:08.20#ibcon#flushed, iclass 11, count 2 2006.257.19:28:08.20#ibcon#about to write, iclass 11, count 2 2006.257.19:28:08.20#ibcon#wrote, iclass 11, count 2 2006.257.19:28:08.20#ibcon#about to read 3, iclass 11, count 2 2006.257.19:28:08.22#ibcon#read 3, iclass 11, count 2 2006.257.19:28:08.22#ibcon#about to read 4, iclass 11, count 2 2006.257.19:28:08.22#ibcon#read 4, iclass 11, count 2 2006.257.19:28:08.22#ibcon#about to read 5, iclass 11, count 2 2006.257.19:28:08.22#ibcon#read 5, iclass 11, count 2 2006.257.19:28:08.22#ibcon#about to read 6, iclass 11, count 2 2006.257.19:28:08.22#ibcon#read 6, iclass 11, count 2 2006.257.19:28:08.22#ibcon#end of sib2, iclass 11, count 2 2006.257.19:28:08.22#ibcon#*mode == 0, iclass 11, count 2 2006.257.19:28:08.22#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.19:28:08.22#ibcon#[27=AT01-04\r\n] 2006.257.19:28:08.22#ibcon#*before write, iclass 11, count 2 2006.257.19:28:08.22#ibcon#enter sib2, iclass 11, count 2 2006.257.19:28:08.22#ibcon#flushed, iclass 11, count 2 2006.257.19:28:08.22#ibcon#about to write, iclass 11, count 2 2006.257.19:28:08.22#ibcon#wrote, iclass 11, count 2 2006.257.19:28:08.22#ibcon#about to read 3, iclass 11, count 2 2006.257.19:28:08.25#ibcon#read 3, iclass 11, count 2 2006.257.19:28:08.25#ibcon#about to read 4, iclass 11, count 2 2006.257.19:28:08.25#ibcon#read 4, iclass 11, count 2 2006.257.19:28:08.25#ibcon#about to read 5, iclass 11, count 2 2006.257.19:28:08.25#ibcon#read 5, iclass 11, count 2 2006.257.19:28:08.25#ibcon#about to read 6, iclass 11, count 2 2006.257.19:28:08.25#ibcon#read 6, iclass 11, count 2 2006.257.19:28:08.25#ibcon#end of sib2, iclass 11, count 2 2006.257.19:28:08.25#ibcon#*after write, iclass 11, count 2 2006.257.19:28:08.25#ibcon#*before return 0, iclass 11, count 2 2006.257.19:28:08.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:28:08.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:28:08.25#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.19:28:08.25#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:08.25#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:28:08.37#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:28:08.37#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:28:08.37#ibcon#enter wrdev, iclass 11, count 0 2006.257.19:28:08.37#ibcon#first serial, iclass 11, count 0 2006.257.19:28:08.37#ibcon#enter sib2, iclass 11, count 0 2006.257.19:28:08.37#ibcon#flushed, iclass 11, count 0 2006.257.19:28:08.37#ibcon#about to write, iclass 11, count 0 2006.257.19:28:08.37#ibcon#wrote, iclass 11, count 0 2006.257.19:28:08.37#ibcon#about to read 3, iclass 11, count 0 2006.257.19:28:08.39#ibcon#read 3, iclass 11, count 0 2006.257.19:28:08.39#ibcon#about to read 4, iclass 11, count 0 2006.257.19:28:08.39#ibcon#read 4, iclass 11, count 0 2006.257.19:28:08.39#ibcon#about to read 5, iclass 11, count 0 2006.257.19:28:08.39#ibcon#read 5, iclass 11, count 0 2006.257.19:28:08.39#ibcon#about to read 6, iclass 11, count 0 2006.257.19:28:08.39#ibcon#read 6, iclass 11, count 0 2006.257.19:28:08.39#ibcon#end of sib2, iclass 11, count 0 2006.257.19:28:08.39#ibcon#*mode == 0, iclass 11, count 0 2006.257.19:28:08.39#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.19:28:08.39#ibcon#[27=USB\r\n] 2006.257.19:28:08.39#ibcon#*before write, iclass 11, count 0 2006.257.19:28:08.39#ibcon#enter sib2, iclass 11, count 0 2006.257.19:28:08.39#ibcon#flushed, iclass 11, count 0 2006.257.19:28:08.39#ibcon#about to write, iclass 11, count 0 2006.257.19:28:08.39#ibcon#wrote, iclass 11, count 0 2006.257.19:28:08.39#ibcon#about to read 3, iclass 11, count 0 2006.257.19:28:08.42#ibcon#read 3, iclass 11, count 0 2006.257.19:28:08.42#ibcon#about to read 4, iclass 11, count 0 2006.257.19:28:08.42#ibcon#read 4, iclass 11, count 0 2006.257.19:28:08.42#ibcon#about to read 5, iclass 11, count 0 2006.257.19:28:08.42#ibcon#read 5, iclass 11, count 0 2006.257.19:28:08.42#ibcon#about to read 6, iclass 11, count 0 2006.257.19:28:08.42#ibcon#read 6, iclass 11, count 0 2006.257.19:28:08.42#ibcon#end of sib2, iclass 11, count 0 2006.257.19:28:08.42#ibcon#*after write, iclass 11, count 0 2006.257.19:28:08.42#ibcon#*before return 0, iclass 11, count 0 2006.257.19:28:08.42#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:28:08.42#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:28:08.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.19:28:08.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.19:28:08.42$vck44/vblo=2,634.99 2006.257.19:28:08.42#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.19:28:08.42#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.19:28:08.42#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:08.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:08.42#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:08.42#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:08.42#ibcon#enter wrdev, iclass 13, count 0 2006.257.19:28:08.42#ibcon#first serial, iclass 13, count 0 2006.257.19:28:08.42#ibcon#enter sib2, iclass 13, count 0 2006.257.19:28:08.42#ibcon#flushed, iclass 13, count 0 2006.257.19:28:08.42#ibcon#about to write, iclass 13, count 0 2006.257.19:28:08.42#ibcon#wrote, iclass 13, count 0 2006.257.19:28:08.42#ibcon#about to read 3, iclass 13, count 0 2006.257.19:28:08.44#ibcon#read 3, iclass 13, count 0 2006.257.19:28:08.44#ibcon#about to read 4, iclass 13, count 0 2006.257.19:28:08.44#ibcon#read 4, iclass 13, count 0 2006.257.19:28:08.44#ibcon#about to read 5, iclass 13, count 0 2006.257.19:28:08.44#ibcon#read 5, iclass 13, count 0 2006.257.19:28:08.44#ibcon#about to read 6, iclass 13, count 0 2006.257.19:28:08.44#ibcon#read 6, iclass 13, count 0 2006.257.19:28:08.44#ibcon#end of sib2, iclass 13, count 0 2006.257.19:28:08.44#ibcon#*mode == 0, iclass 13, count 0 2006.257.19:28:08.44#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.19:28:08.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.19:28:08.44#ibcon#*before write, iclass 13, count 0 2006.257.19:28:08.44#ibcon#enter sib2, iclass 13, count 0 2006.257.19:28:08.44#ibcon#flushed, iclass 13, count 0 2006.257.19:28:08.44#ibcon#about to write, iclass 13, count 0 2006.257.19:28:08.44#ibcon#wrote, iclass 13, count 0 2006.257.19:28:08.44#ibcon#about to read 3, iclass 13, count 0 2006.257.19:28:08.48#ibcon#read 3, iclass 13, count 0 2006.257.19:28:08.48#ibcon#about to read 4, iclass 13, count 0 2006.257.19:28:08.48#ibcon#read 4, iclass 13, count 0 2006.257.19:28:08.48#ibcon#about to read 5, iclass 13, count 0 2006.257.19:28:08.48#ibcon#read 5, iclass 13, count 0 2006.257.19:28:08.48#ibcon#about to read 6, iclass 13, count 0 2006.257.19:28:08.48#ibcon#read 6, iclass 13, count 0 2006.257.19:28:08.48#ibcon#end of sib2, iclass 13, count 0 2006.257.19:28:08.48#ibcon#*after write, iclass 13, count 0 2006.257.19:28:08.48#ibcon#*before return 0, iclass 13, count 0 2006.257.19:28:08.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:08.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:28:08.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.19:28:08.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.19:28:08.48$vck44/vb=2,5 2006.257.19:28:08.48#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.19:28:08.48#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.19:28:08.48#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:08.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:08.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:08.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:08.54#ibcon#enter wrdev, iclass 15, count 2 2006.257.19:28:08.54#ibcon#first serial, iclass 15, count 2 2006.257.19:28:08.54#ibcon#enter sib2, iclass 15, count 2 2006.257.19:28:08.54#ibcon#flushed, iclass 15, count 2 2006.257.19:28:08.54#ibcon#about to write, iclass 15, count 2 2006.257.19:28:08.54#ibcon#wrote, iclass 15, count 2 2006.257.19:28:08.54#ibcon#about to read 3, iclass 15, count 2 2006.257.19:28:08.56#ibcon#read 3, iclass 15, count 2 2006.257.19:28:08.56#ibcon#about to read 4, iclass 15, count 2 2006.257.19:28:08.56#ibcon#read 4, iclass 15, count 2 2006.257.19:28:08.56#ibcon#about to read 5, iclass 15, count 2 2006.257.19:28:08.56#ibcon#read 5, iclass 15, count 2 2006.257.19:28:08.56#ibcon#about to read 6, iclass 15, count 2 2006.257.19:28:08.56#ibcon#read 6, iclass 15, count 2 2006.257.19:28:08.56#ibcon#end of sib2, iclass 15, count 2 2006.257.19:28:08.56#ibcon#*mode == 0, iclass 15, count 2 2006.257.19:28:08.56#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.19:28:08.56#ibcon#[27=AT02-05\r\n] 2006.257.19:28:08.56#ibcon#*before write, iclass 15, count 2 2006.257.19:28:08.56#ibcon#enter sib2, iclass 15, count 2 2006.257.19:28:08.56#ibcon#flushed, iclass 15, count 2 2006.257.19:28:08.56#ibcon#about to write, iclass 15, count 2 2006.257.19:28:08.56#ibcon#wrote, iclass 15, count 2 2006.257.19:28:08.56#ibcon#about to read 3, iclass 15, count 2 2006.257.19:28:08.59#ibcon#read 3, iclass 15, count 2 2006.257.19:28:08.59#ibcon#about to read 4, iclass 15, count 2 2006.257.19:28:08.59#ibcon#read 4, iclass 15, count 2 2006.257.19:28:08.59#ibcon#about to read 5, iclass 15, count 2 2006.257.19:28:08.59#ibcon#read 5, iclass 15, count 2 2006.257.19:28:08.59#ibcon#about to read 6, iclass 15, count 2 2006.257.19:28:08.59#ibcon#read 6, iclass 15, count 2 2006.257.19:28:08.59#ibcon#end of sib2, iclass 15, count 2 2006.257.19:28:08.59#ibcon#*after write, iclass 15, count 2 2006.257.19:28:08.59#ibcon#*before return 0, iclass 15, count 2 2006.257.19:28:08.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:08.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:28:08.59#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.19:28:08.59#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:08.59#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:08.71#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:08.71#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:08.71#ibcon#enter wrdev, iclass 15, count 0 2006.257.19:28:08.71#ibcon#first serial, iclass 15, count 0 2006.257.19:28:08.71#ibcon#enter sib2, iclass 15, count 0 2006.257.19:28:08.71#ibcon#flushed, iclass 15, count 0 2006.257.19:28:08.71#ibcon#about to write, iclass 15, count 0 2006.257.19:28:08.71#ibcon#wrote, iclass 15, count 0 2006.257.19:28:08.71#ibcon#about to read 3, iclass 15, count 0 2006.257.19:28:08.73#ibcon#read 3, iclass 15, count 0 2006.257.19:28:08.73#ibcon#about to read 4, iclass 15, count 0 2006.257.19:28:08.73#ibcon#read 4, iclass 15, count 0 2006.257.19:28:08.73#ibcon#about to read 5, iclass 15, count 0 2006.257.19:28:08.73#ibcon#read 5, iclass 15, count 0 2006.257.19:28:08.73#ibcon#about to read 6, iclass 15, count 0 2006.257.19:28:08.73#ibcon#read 6, iclass 15, count 0 2006.257.19:28:08.73#ibcon#end of sib2, iclass 15, count 0 2006.257.19:28:08.73#ibcon#*mode == 0, iclass 15, count 0 2006.257.19:28:08.73#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.19:28:08.73#ibcon#[27=USB\r\n] 2006.257.19:28:08.73#ibcon#*before write, iclass 15, count 0 2006.257.19:28:08.73#ibcon#enter sib2, iclass 15, count 0 2006.257.19:28:08.73#ibcon#flushed, iclass 15, count 0 2006.257.19:28:08.73#ibcon#about to write, iclass 15, count 0 2006.257.19:28:08.73#ibcon#wrote, iclass 15, count 0 2006.257.19:28:08.73#ibcon#about to read 3, iclass 15, count 0 2006.257.19:28:08.76#ibcon#read 3, iclass 15, count 0 2006.257.19:28:08.76#ibcon#about to read 4, iclass 15, count 0 2006.257.19:28:08.76#ibcon#read 4, iclass 15, count 0 2006.257.19:28:08.76#ibcon#about to read 5, iclass 15, count 0 2006.257.19:28:08.76#ibcon#read 5, iclass 15, count 0 2006.257.19:28:08.76#ibcon#about to read 6, iclass 15, count 0 2006.257.19:28:08.76#ibcon#read 6, iclass 15, count 0 2006.257.19:28:08.76#ibcon#end of sib2, iclass 15, count 0 2006.257.19:28:08.76#ibcon#*after write, iclass 15, count 0 2006.257.19:28:08.76#ibcon#*before return 0, iclass 15, count 0 2006.257.19:28:08.76#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:08.76#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:28:08.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.19:28:08.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.19:28:08.76$vck44/vblo=3,649.99 2006.257.19:28:08.76#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.19:28:08.76#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.19:28:08.76#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:08.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:08.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:08.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:08.76#ibcon#enter wrdev, iclass 17, count 0 2006.257.19:28:08.76#ibcon#first serial, iclass 17, count 0 2006.257.19:28:08.76#ibcon#enter sib2, iclass 17, count 0 2006.257.19:28:08.76#ibcon#flushed, iclass 17, count 0 2006.257.19:28:08.76#ibcon#about to write, iclass 17, count 0 2006.257.19:28:08.76#ibcon#wrote, iclass 17, count 0 2006.257.19:28:08.76#ibcon#about to read 3, iclass 17, count 0 2006.257.19:28:08.78#ibcon#read 3, iclass 17, count 0 2006.257.19:28:08.78#ibcon#about to read 4, iclass 17, count 0 2006.257.19:28:08.78#ibcon#read 4, iclass 17, count 0 2006.257.19:28:08.78#ibcon#about to read 5, iclass 17, count 0 2006.257.19:28:08.78#ibcon#read 5, iclass 17, count 0 2006.257.19:28:08.78#ibcon#about to read 6, iclass 17, count 0 2006.257.19:28:08.78#ibcon#read 6, iclass 17, count 0 2006.257.19:28:08.78#ibcon#end of sib2, iclass 17, count 0 2006.257.19:28:08.78#ibcon#*mode == 0, iclass 17, count 0 2006.257.19:28:08.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.19:28:08.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.19:28:08.78#ibcon#*before write, iclass 17, count 0 2006.257.19:28:08.78#ibcon#enter sib2, iclass 17, count 0 2006.257.19:28:08.78#ibcon#flushed, iclass 17, count 0 2006.257.19:28:08.78#ibcon#about to write, iclass 17, count 0 2006.257.19:28:08.78#ibcon#wrote, iclass 17, count 0 2006.257.19:28:08.78#ibcon#about to read 3, iclass 17, count 0 2006.257.19:28:08.82#ibcon#read 3, iclass 17, count 0 2006.257.19:28:08.82#ibcon#about to read 4, iclass 17, count 0 2006.257.19:28:08.82#ibcon#read 4, iclass 17, count 0 2006.257.19:28:08.82#ibcon#about to read 5, iclass 17, count 0 2006.257.19:28:08.82#ibcon#read 5, iclass 17, count 0 2006.257.19:28:08.82#ibcon#about to read 6, iclass 17, count 0 2006.257.19:28:08.82#ibcon#read 6, iclass 17, count 0 2006.257.19:28:08.82#ibcon#end of sib2, iclass 17, count 0 2006.257.19:28:08.82#ibcon#*after write, iclass 17, count 0 2006.257.19:28:08.82#ibcon#*before return 0, iclass 17, count 0 2006.257.19:28:08.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:08.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:28:08.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.19:28:08.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.19:28:08.82$vck44/vb=3,4 2006.257.19:28:08.82#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.19:28:08.82#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.19:28:08.82#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:08.82#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:08.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:08.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:08.88#ibcon#enter wrdev, iclass 19, count 2 2006.257.19:28:08.88#ibcon#first serial, iclass 19, count 2 2006.257.19:28:08.88#ibcon#enter sib2, iclass 19, count 2 2006.257.19:28:08.88#ibcon#flushed, iclass 19, count 2 2006.257.19:28:08.88#ibcon#about to write, iclass 19, count 2 2006.257.19:28:08.88#ibcon#wrote, iclass 19, count 2 2006.257.19:28:08.88#ibcon#about to read 3, iclass 19, count 2 2006.257.19:28:08.90#ibcon#read 3, iclass 19, count 2 2006.257.19:28:08.90#ibcon#about to read 4, iclass 19, count 2 2006.257.19:28:08.90#ibcon#read 4, iclass 19, count 2 2006.257.19:28:08.90#ibcon#about to read 5, iclass 19, count 2 2006.257.19:28:08.90#ibcon#read 5, iclass 19, count 2 2006.257.19:28:08.90#ibcon#about to read 6, iclass 19, count 2 2006.257.19:28:08.90#ibcon#read 6, iclass 19, count 2 2006.257.19:28:08.90#ibcon#end of sib2, iclass 19, count 2 2006.257.19:28:08.90#ibcon#*mode == 0, iclass 19, count 2 2006.257.19:28:08.90#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.19:28:08.90#ibcon#[27=AT03-04\r\n] 2006.257.19:28:08.90#ibcon#*before write, iclass 19, count 2 2006.257.19:28:08.90#ibcon#enter sib2, iclass 19, count 2 2006.257.19:28:08.90#ibcon#flushed, iclass 19, count 2 2006.257.19:28:08.90#ibcon#about to write, iclass 19, count 2 2006.257.19:28:08.90#ibcon#wrote, iclass 19, count 2 2006.257.19:28:08.90#ibcon#about to read 3, iclass 19, count 2 2006.257.19:28:08.93#ibcon#read 3, iclass 19, count 2 2006.257.19:28:08.93#ibcon#about to read 4, iclass 19, count 2 2006.257.19:28:08.93#ibcon#read 4, iclass 19, count 2 2006.257.19:28:08.93#ibcon#about to read 5, iclass 19, count 2 2006.257.19:28:08.93#ibcon#read 5, iclass 19, count 2 2006.257.19:28:08.93#ibcon#about to read 6, iclass 19, count 2 2006.257.19:28:08.93#ibcon#read 6, iclass 19, count 2 2006.257.19:28:08.93#ibcon#end of sib2, iclass 19, count 2 2006.257.19:28:08.93#ibcon#*after write, iclass 19, count 2 2006.257.19:28:08.93#ibcon#*before return 0, iclass 19, count 2 2006.257.19:28:08.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:08.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:28:08.93#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.19:28:08.93#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:08.93#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:09.05#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:09.05#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:09.05#ibcon#enter wrdev, iclass 19, count 0 2006.257.19:28:09.05#ibcon#first serial, iclass 19, count 0 2006.257.19:28:09.05#ibcon#enter sib2, iclass 19, count 0 2006.257.19:28:09.05#ibcon#flushed, iclass 19, count 0 2006.257.19:28:09.05#ibcon#about to write, iclass 19, count 0 2006.257.19:28:09.05#ibcon#wrote, iclass 19, count 0 2006.257.19:28:09.05#ibcon#about to read 3, iclass 19, count 0 2006.257.19:28:09.07#ibcon#read 3, iclass 19, count 0 2006.257.19:28:09.07#ibcon#about to read 4, iclass 19, count 0 2006.257.19:28:09.07#ibcon#read 4, iclass 19, count 0 2006.257.19:28:09.07#ibcon#about to read 5, iclass 19, count 0 2006.257.19:28:09.07#ibcon#read 5, iclass 19, count 0 2006.257.19:28:09.07#ibcon#about to read 6, iclass 19, count 0 2006.257.19:28:09.07#ibcon#read 6, iclass 19, count 0 2006.257.19:28:09.07#ibcon#end of sib2, iclass 19, count 0 2006.257.19:28:09.07#ibcon#*mode == 0, iclass 19, count 0 2006.257.19:28:09.07#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.19:28:09.07#ibcon#[27=USB\r\n] 2006.257.19:28:09.07#ibcon#*before write, iclass 19, count 0 2006.257.19:28:09.07#ibcon#enter sib2, iclass 19, count 0 2006.257.19:28:09.07#ibcon#flushed, iclass 19, count 0 2006.257.19:28:09.07#ibcon#about to write, iclass 19, count 0 2006.257.19:28:09.07#ibcon#wrote, iclass 19, count 0 2006.257.19:28:09.07#ibcon#about to read 3, iclass 19, count 0 2006.257.19:28:09.10#ibcon#read 3, iclass 19, count 0 2006.257.19:28:09.10#ibcon#about to read 4, iclass 19, count 0 2006.257.19:28:09.10#ibcon#read 4, iclass 19, count 0 2006.257.19:28:09.10#ibcon#about to read 5, iclass 19, count 0 2006.257.19:28:09.10#ibcon#read 5, iclass 19, count 0 2006.257.19:28:09.10#ibcon#about to read 6, iclass 19, count 0 2006.257.19:28:09.10#ibcon#read 6, iclass 19, count 0 2006.257.19:28:09.10#ibcon#end of sib2, iclass 19, count 0 2006.257.19:28:09.10#ibcon#*after write, iclass 19, count 0 2006.257.19:28:09.10#ibcon#*before return 0, iclass 19, count 0 2006.257.19:28:09.10#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:09.10#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:28:09.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.19:28:09.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.19:28:09.10$vck44/vblo=4,679.99 2006.257.19:28:09.10#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.19:28:09.10#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.19:28:09.10#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:09.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:09.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:09.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:09.10#ibcon#enter wrdev, iclass 21, count 0 2006.257.19:28:09.10#ibcon#first serial, iclass 21, count 0 2006.257.19:28:09.10#ibcon#enter sib2, iclass 21, count 0 2006.257.19:28:09.10#ibcon#flushed, iclass 21, count 0 2006.257.19:28:09.10#ibcon#about to write, iclass 21, count 0 2006.257.19:28:09.10#ibcon#wrote, iclass 21, count 0 2006.257.19:28:09.10#ibcon#about to read 3, iclass 21, count 0 2006.257.19:28:09.12#ibcon#read 3, iclass 21, count 0 2006.257.19:28:09.12#ibcon#about to read 4, iclass 21, count 0 2006.257.19:28:09.12#ibcon#read 4, iclass 21, count 0 2006.257.19:28:09.12#ibcon#about to read 5, iclass 21, count 0 2006.257.19:28:09.12#ibcon#read 5, iclass 21, count 0 2006.257.19:28:09.12#ibcon#about to read 6, iclass 21, count 0 2006.257.19:28:09.12#ibcon#read 6, iclass 21, count 0 2006.257.19:28:09.12#ibcon#end of sib2, iclass 21, count 0 2006.257.19:28:09.12#ibcon#*mode == 0, iclass 21, count 0 2006.257.19:28:09.12#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.19:28:09.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.19:28:09.12#ibcon#*before write, iclass 21, count 0 2006.257.19:28:09.12#ibcon#enter sib2, iclass 21, count 0 2006.257.19:28:09.12#ibcon#flushed, iclass 21, count 0 2006.257.19:28:09.12#ibcon#about to write, iclass 21, count 0 2006.257.19:28:09.12#ibcon#wrote, iclass 21, count 0 2006.257.19:28:09.12#ibcon#about to read 3, iclass 21, count 0 2006.257.19:28:09.16#ibcon#read 3, iclass 21, count 0 2006.257.19:28:09.16#ibcon#about to read 4, iclass 21, count 0 2006.257.19:28:09.16#ibcon#read 4, iclass 21, count 0 2006.257.19:28:09.16#ibcon#about to read 5, iclass 21, count 0 2006.257.19:28:09.16#ibcon#read 5, iclass 21, count 0 2006.257.19:28:09.16#ibcon#about to read 6, iclass 21, count 0 2006.257.19:28:09.16#ibcon#read 6, iclass 21, count 0 2006.257.19:28:09.16#ibcon#end of sib2, iclass 21, count 0 2006.257.19:28:09.16#ibcon#*after write, iclass 21, count 0 2006.257.19:28:09.16#ibcon#*before return 0, iclass 21, count 0 2006.257.19:28:09.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:09.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:28:09.16#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.19:28:09.16#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.19:28:09.16$vck44/vb=4,5 2006.257.19:28:09.16#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.19:28:09.16#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.19:28:09.16#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:09.16#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:09.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:09.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:09.22#ibcon#enter wrdev, iclass 23, count 2 2006.257.19:28:09.22#ibcon#first serial, iclass 23, count 2 2006.257.19:28:09.22#ibcon#enter sib2, iclass 23, count 2 2006.257.19:28:09.22#ibcon#flushed, iclass 23, count 2 2006.257.19:28:09.22#ibcon#about to write, iclass 23, count 2 2006.257.19:28:09.22#ibcon#wrote, iclass 23, count 2 2006.257.19:28:09.22#ibcon#about to read 3, iclass 23, count 2 2006.257.19:28:09.24#ibcon#read 3, iclass 23, count 2 2006.257.19:28:09.24#ibcon#about to read 4, iclass 23, count 2 2006.257.19:28:09.24#ibcon#read 4, iclass 23, count 2 2006.257.19:28:09.24#ibcon#about to read 5, iclass 23, count 2 2006.257.19:28:09.24#ibcon#read 5, iclass 23, count 2 2006.257.19:28:09.24#ibcon#about to read 6, iclass 23, count 2 2006.257.19:28:09.24#ibcon#read 6, iclass 23, count 2 2006.257.19:28:09.24#ibcon#end of sib2, iclass 23, count 2 2006.257.19:28:09.24#ibcon#*mode == 0, iclass 23, count 2 2006.257.19:28:09.24#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.19:28:09.24#ibcon#[27=AT04-05\r\n] 2006.257.19:28:09.24#ibcon#*before write, iclass 23, count 2 2006.257.19:28:09.24#ibcon#enter sib2, iclass 23, count 2 2006.257.19:28:09.24#ibcon#flushed, iclass 23, count 2 2006.257.19:28:09.24#ibcon#about to write, iclass 23, count 2 2006.257.19:28:09.24#ibcon#wrote, iclass 23, count 2 2006.257.19:28:09.24#ibcon#about to read 3, iclass 23, count 2 2006.257.19:28:09.27#ibcon#read 3, iclass 23, count 2 2006.257.19:28:09.27#ibcon#about to read 4, iclass 23, count 2 2006.257.19:28:09.27#ibcon#read 4, iclass 23, count 2 2006.257.19:28:09.27#ibcon#about to read 5, iclass 23, count 2 2006.257.19:28:09.27#ibcon#read 5, iclass 23, count 2 2006.257.19:28:09.27#ibcon#about to read 6, iclass 23, count 2 2006.257.19:28:09.27#ibcon#read 6, iclass 23, count 2 2006.257.19:28:09.27#ibcon#end of sib2, iclass 23, count 2 2006.257.19:28:09.27#ibcon#*after write, iclass 23, count 2 2006.257.19:28:09.27#ibcon#*before return 0, iclass 23, count 2 2006.257.19:28:09.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:09.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:28:09.27#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.19:28:09.27#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:09.27#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:09.39#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:09.39#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:09.39#ibcon#enter wrdev, iclass 23, count 0 2006.257.19:28:09.39#ibcon#first serial, iclass 23, count 0 2006.257.19:28:09.39#ibcon#enter sib2, iclass 23, count 0 2006.257.19:28:09.39#ibcon#flushed, iclass 23, count 0 2006.257.19:28:09.39#ibcon#about to write, iclass 23, count 0 2006.257.19:28:09.39#ibcon#wrote, iclass 23, count 0 2006.257.19:28:09.39#ibcon#about to read 3, iclass 23, count 0 2006.257.19:28:09.41#ibcon#read 3, iclass 23, count 0 2006.257.19:28:09.41#ibcon#about to read 4, iclass 23, count 0 2006.257.19:28:09.41#ibcon#read 4, iclass 23, count 0 2006.257.19:28:09.41#ibcon#about to read 5, iclass 23, count 0 2006.257.19:28:09.41#ibcon#read 5, iclass 23, count 0 2006.257.19:28:09.41#ibcon#about to read 6, iclass 23, count 0 2006.257.19:28:09.41#ibcon#read 6, iclass 23, count 0 2006.257.19:28:09.41#ibcon#end of sib2, iclass 23, count 0 2006.257.19:28:09.41#ibcon#*mode == 0, iclass 23, count 0 2006.257.19:28:09.41#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.19:28:09.41#ibcon#[27=USB\r\n] 2006.257.19:28:09.41#ibcon#*before write, iclass 23, count 0 2006.257.19:28:09.41#ibcon#enter sib2, iclass 23, count 0 2006.257.19:28:09.41#ibcon#flushed, iclass 23, count 0 2006.257.19:28:09.41#ibcon#about to write, iclass 23, count 0 2006.257.19:28:09.41#ibcon#wrote, iclass 23, count 0 2006.257.19:28:09.41#ibcon#about to read 3, iclass 23, count 0 2006.257.19:28:09.44#ibcon#read 3, iclass 23, count 0 2006.257.19:28:09.44#ibcon#about to read 4, iclass 23, count 0 2006.257.19:28:09.44#ibcon#read 4, iclass 23, count 0 2006.257.19:28:09.44#ibcon#about to read 5, iclass 23, count 0 2006.257.19:28:09.44#ibcon#read 5, iclass 23, count 0 2006.257.19:28:09.44#ibcon#about to read 6, iclass 23, count 0 2006.257.19:28:09.44#ibcon#read 6, iclass 23, count 0 2006.257.19:28:09.44#ibcon#end of sib2, iclass 23, count 0 2006.257.19:28:09.44#ibcon#*after write, iclass 23, count 0 2006.257.19:28:09.44#ibcon#*before return 0, iclass 23, count 0 2006.257.19:28:09.44#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:09.44#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:28:09.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.19:28:09.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.19:28:09.44$vck44/vblo=5,709.99 2006.257.19:28:09.44#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.19:28:09.44#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.19:28:09.44#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:09.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:09.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:09.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:09.44#ibcon#enter wrdev, iclass 25, count 0 2006.257.19:28:09.44#ibcon#first serial, iclass 25, count 0 2006.257.19:28:09.44#ibcon#enter sib2, iclass 25, count 0 2006.257.19:28:09.44#ibcon#flushed, iclass 25, count 0 2006.257.19:28:09.44#ibcon#about to write, iclass 25, count 0 2006.257.19:28:09.44#ibcon#wrote, iclass 25, count 0 2006.257.19:28:09.44#ibcon#about to read 3, iclass 25, count 0 2006.257.19:28:09.46#ibcon#read 3, iclass 25, count 0 2006.257.19:28:09.46#ibcon#about to read 4, iclass 25, count 0 2006.257.19:28:09.46#ibcon#read 4, iclass 25, count 0 2006.257.19:28:09.46#ibcon#about to read 5, iclass 25, count 0 2006.257.19:28:09.46#ibcon#read 5, iclass 25, count 0 2006.257.19:28:09.46#ibcon#about to read 6, iclass 25, count 0 2006.257.19:28:09.46#ibcon#read 6, iclass 25, count 0 2006.257.19:28:09.46#ibcon#end of sib2, iclass 25, count 0 2006.257.19:28:09.46#ibcon#*mode == 0, iclass 25, count 0 2006.257.19:28:09.46#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.19:28:09.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.19:28:09.46#ibcon#*before write, iclass 25, count 0 2006.257.19:28:09.46#ibcon#enter sib2, iclass 25, count 0 2006.257.19:28:09.46#ibcon#flushed, iclass 25, count 0 2006.257.19:28:09.46#ibcon#about to write, iclass 25, count 0 2006.257.19:28:09.46#ibcon#wrote, iclass 25, count 0 2006.257.19:28:09.46#ibcon#about to read 3, iclass 25, count 0 2006.257.19:28:09.50#ibcon#read 3, iclass 25, count 0 2006.257.19:28:09.50#ibcon#about to read 4, iclass 25, count 0 2006.257.19:28:09.50#ibcon#read 4, iclass 25, count 0 2006.257.19:28:09.50#ibcon#about to read 5, iclass 25, count 0 2006.257.19:28:09.50#ibcon#read 5, iclass 25, count 0 2006.257.19:28:09.50#ibcon#about to read 6, iclass 25, count 0 2006.257.19:28:09.50#ibcon#read 6, iclass 25, count 0 2006.257.19:28:09.50#ibcon#end of sib2, iclass 25, count 0 2006.257.19:28:09.50#ibcon#*after write, iclass 25, count 0 2006.257.19:28:09.50#ibcon#*before return 0, iclass 25, count 0 2006.257.19:28:09.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:09.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:28:09.50#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.19:28:09.50#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.19:28:09.50$vck44/vb=5,4 2006.257.19:28:09.50#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.19:28:09.50#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.19:28:09.50#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:09.50#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:09.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:09.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:09.56#ibcon#enter wrdev, iclass 27, count 2 2006.257.19:28:09.56#ibcon#first serial, iclass 27, count 2 2006.257.19:28:09.56#ibcon#enter sib2, iclass 27, count 2 2006.257.19:28:09.56#ibcon#flushed, iclass 27, count 2 2006.257.19:28:09.56#ibcon#about to write, iclass 27, count 2 2006.257.19:28:09.56#ibcon#wrote, iclass 27, count 2 2006.257.19:28:09.56#ibcon#about to read 3, iclass 27, count 2 2006.257.19:28:09.58#ibcon#read 3, iclass 27, count 2 2006.257.19:28:09.58#ibcon#about to read 4, iclass 27, count 2 2006.257.19:28:09.58#ibcon#read 4, iclass 27, count 2 2006.257.19:28:09.58#ibcon#about to read 5, iclass 27, count 2 2006.257.19:28:09.58#ibcon#read 5, iclass 27, count 2 2006.257.19:28:09.58#ibcon#about to read 6, iclass 27, count 2 2006.257.19:28:09.58#ibcon#read 6, iclass 27, count 2 2006.257.19:28:09.58#ibcon#end of sib2, iclass 27, count 2 2006.257.19:28:09.58#ibcon#*mode == 0, iclass 27, count 2 2006.257.19:28:09.58#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.19:28:09.58#ibcon#[27=AT05-04\r\n] 2006.257.19:28:09.58#ibcon#*before write, iclass 27, count 2 2006.257.19:28:09.58#ibcon#enter sib2, iclass 27, count 2 2006.257.19:28:09.58#ibcon#flushed, iclass 27, count 2 2006.257.19:28:09.58#ibcon#about to write, iclass 27, count 2 2006.257.19:28:09.58#ibcon#wrote, iclass 27, count 2 2006.257.19:28:09.58#ibcon#about to read 3, iclass 27, count 2 2006.257.19:28:09.61#ibcon#read 3, iclass 27, count 2 2006.257.19:28:09.61#ibcon#about to read 4, iclass 27, count 2 2006.257.19:28:09.61#ibcon#read 4, iclass 27, count 2 2006.257.19:28:09.61#ibcon#about to read 5, iclass 27, count 2 2006.257.19:28:09.61#ibcon#read 5, iclass 27, count 2 2006.257.19:28:09.61#ibcon#about to read 6, iclass 27, count 2 2006.257.19:28:09.61#ibcon#read 6, iclass 27, count 2 2006.257.19:28:09.61#ibcon#end of sib2, iclass 27, count 2 2006.257.19:28:09.61#ibcon#*after write, iclass 27, count 2 2006.257.19:28:09.61#ibcon#*before return 0, iclass 27, count 2 2006.257.19:28:09.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:09.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:28:09.61#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.19:28:09.61#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:09.61#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:09.73#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:09.73#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:09.73#ibcon#enter wrdev, iclass 27, count 0 2006.257.19:28:09.73#ibcon#first serial, iclass 27, count 0 2006.257.19:28:09.73#ibcon#enter sib2, iclass 27, count 0 2006.257.19:28:09.73#ibcon#flushed, iclass 27, count 0 2006.257.19:28:09.73#ibcon#about to write, iclass 27, count 0 2006.257.19:28:09.73#ibcon#wrote, iclass 27, count 0 2006.257.19:28:09.73#ibcon#about to read 3, iclass 27, count 0 2006.257.19:28:09.75#ibcon#read 3, iclass 27, count 0 2006.257.19:28:09.75#ibcon#about to read 4, iclass 27, count 0 2006.257.19:28:09.75#ibcon#read 4, iclass 27, count 0 2006.257.19:28:09.75#ibcon#about to read 5, iclass 27, count 0 2006.257.19:28:09.75#ibcon#read 5, iclass 27, count 0 2006.257.19:28:09.75#ibcon#about to read 6, iclass 27, count 0 2006.257.19:28:09.75#ibcon#read 6, iclass 27, count 0 2006.257.19:28:09.75#ibcon#end of sib2, iclass 27, count 0 2006.257.19:28:09.75#ibcon#*mode == 0, iclass 27, count 0 2006.257.19:28:09.75#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.19:28:09.75#ibcon#[27=USB\r\n] 2006.257.19:28:09.75#ibcon#*before write, iclass 27, count 0 2006.257.19:28:09.75#ibcon#enter sib2, iclass 27, count 0 2006.257.19:28:09.75#ibcon#flushed, iclass 27, count 0 2006.257.19:28:09.75#ibcon#about to write, iclass 27, count 0 2006.257.19:28:09.75#ibcon#wrote, iclass 27, count 0 2006.257.19:28:09.75#ibcon#about to read 3, iclass 27, count 0 2006.257.19:28:09.78#ibcon#read 3, iclass 27, count 0 2006.257.19:28:09.78#ibcon#about to read 4, iclass 27, count 0 2006.257.19:28:09.78#ibcon#read 4, iclass 27, count 0 2006.257.19:28:09.78#ibcon#about to read 5, iclass 27, count 0 2006.257.19:28:09.78#ibcon#read 5, iclass 27, count 0 2006.257.19:28:09.78#ibcon#about to read 6, iclass 27, count 0 2006.257.19:28:09.78#ibcon#read 6, iclass 27, count 0 2006.257.19:28:09.78#ibcon#end of sib2, iclass 27, count 0 2006.257.19:28:09.78#ibcon#*after write, iclass 27, count 0 2006.257.19:28:09.78#ibcon#*before return 0, iclass 27, count 0 2006.257.19:28:09.78#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:09.78#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:28:09.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.19:28:09.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.19:28:09.78$vck44/vblo=6,719.99 2006.257.19:28:09.78#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.19:28:09.78#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.19:28:09.78#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:09.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:09.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:09.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:09.78#ibcon#enter wrdev, iclass 29, count 0 2006.257.19:28:09.78#ibcon#first serial, iclass 29, count 0 2006.257.19:28:09.78#ibcon#enter sib2, iclass 29, count 0 2006.257.19:28:09.78#ibcon#flushed, iclass 29, count 0 2006.257.19:28:09.78#ibcon#about to write, iclass 29, count 0 2006.257.19:28:09.78#ibcon#wrote, iclass 29, count 0 2006.257.19:28:09.78#ibcon#about to read 3, iclass 29, count 0 2006.257.19:28:09.80#ibcon#read 3, iclass 29, count 0 2006.257.19:28:09.80#ibcon#about to read 4, iclass 29, count 0 2006.257.19:28:09.80#ibcon#read 4, iclass 29, count 0 2006.257.19:28:09.80#ibcon#about to read 5, iclass 29, count 0 2006.257.19:28:09.80#ibcon#read 5, iclass 29, count 0 2006.257.19:28:09.80#ibcon#about to read 6, iclass 29, count 0 2006.257.19:28:09.80#ibcon#read 6, iclass 29, count 0 2006.257.19:28:09.80#ibcon#end of sib2, iclass 29, count 0 2006.257.19:28:09.80#ibcon#*mode == 0, iclass 29, count 0 2006.257.19:28:09.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.19:28:09.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.19:28:09.80#ibcon#*before write, iclass 29, count 0 2006.257.19:28:09.80#ibcon#enter sib2, iclass 29, count 0 2006.257.19:28:09.80#ibcon#flushed, iclass 29, count 0 2006.257.19:28:09.80#ibcon#about to write, iclass 29, count 0 2006.257.19:28:09.80#ibcon#wrote, iclass 29, count 0 2006.257.19:28:09.80#ibcon#about to read 3, iclass 29, count 0 2006.257.19:28:09.84#ibcon#read 3, iclass 29, count 0 2006.257.19:28:09.84#ibcon#about to read 4, iclass 29, count 0 2006.257.19:28:09.84#ibcon#read 4, iclass 29, count 0 2006.257.19:28:09.84#ibcon#about to read 5, iclass 29, count 0 2006.257.19:28:09.84#ibcon#read 5, iclass 29, count 0 2006.257.19:28:09.84#ibcon#about to read 6, iclass 29, count 0 2006.257.19:28:09.84#ibcon#read 6, iclass 29, count 0 2006.257.19:28:09.84#ibcon#end of sib2, iclass 29, count 0 2006.257.19:28:09.84#ibcon#*after write, iclass 29, count 0 2006.257.19:28:09.84#ibcon#*before return 0, iclass 29, count 0 2006.257.19:28:09.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:09.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:28:09.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.19:28:09.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.19:28:09.84$vck44/vb=6,4 2006.257.19:28:09.84#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.19:28:09.84#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.19:28:09.84#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:09.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:09.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:09.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:09.90#ibcon#enter wrdev, iclass 31, count 2 2006.257.19:28:09.90#ibcon#first serial, iclass 31, count 2 2006.257.19:28:09.90#ibcon#enter sib2, iclass 31, count 2 2006.257.19:28:09.90#ibcon#flushed, iclass 31, count 2 2006.257.19:28:09.90#ibcon#about to write, iclass 31, count 2 2006.257.19:28:09.90#ibcon#wrote, iclass 31, count 2 2006.257.19:28:09.90#ibcon#about to read 3, iclass 31, count 2 2006.257.19:28:09.92#ibcon#read 3, iclass 31, count 2 2006.257.19:28:09.92#ibcon#about to read 4, iclass 31, count 2 2006.257.19:28:09.92#ibcon#read 4, iclass 31, count 2 2006.257.19:28:09.92#ibcon#about to read 5, iclass 31, count 2 2006.257.19:28:09.92#ibcon#read 5, iclass 31, count 2 2006.257.19:28:09.92#ibcon#about to read 6, iclass 31, count 2 2006.257.19:28:09.92#ibcon#read 6, iclass 31, count 2 2006.257.19:28:09.92#ibcon#end of sib2, iclass 31, count 2 2006.257.19:28:09.92#ibcon#*mode == 0, iclass 31, count 2 2006.257.19:28:09.92#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.19:28:09.92#ibcon#[27=AT06-04\r\n] 2006.257.19:28:09.92#ibcon#*before write, iclass 31, count 2 2006.257.19:28:09.92#ibcon#enter sib2, iclass 31, count 2 2006.257.19:28:09.92#ibcon#flushed, iclass 31, count 2 2006.257.19:28:09.92#ibcon#about to write, iclass 31, count 2 2006.257.19:28:09.92#ibcon#wrote, iclass 31, count 2 2006.257.19:28:09.92#ibcon#about to read 3, iclass 31, count 2 2006.257.19:28:09.95#ibcon#read 3, iclass 31, count 2 2006.257.19:28:09.95#ibcon#about to read 4, iclass 31, count 2 2006.257.19:28:09.95#ibcon#read 4, iclass 31, count 2 2006.257.19:28:09.95#ibcon#about to read 5, iclass 31, count 2 2006.257.19:28:09.95#ibcon#read 5, iclass 31, count 2 2006.257.19:28:09.95#ibcon#about to read 6, iclass 31, count 2 2006.257.19:28:09.95#ibcon#read 6, iclass 31, count 2 2006.257.19:28:09.95#ibcon#end of sib2, iclass 31, count 2 2006.257.19:28:09.95#ibcon#*after write, iclass 31, count 2 2006.257.19:28:09.95#ibcon#*before return 0, iclass 31, count 2 2006.257.19:28:09.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:09.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:28:09.95#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.19:28:09.95#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:09.95#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:10.07#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:10.07#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:10.07#ibcon#enter wrdev, iclass 31, count 0 2006.257.19:28:10.07#ibcon#first serial, iclass 31, count 0 2006.257.19:28:10.07#ibcon#enter sib2, iclass 31, count 0 2006.257.19:28:10.07#ibcon#flushed, iclass 31, count 0 2006.257.19:28:10.07#ibcon#about to write, iclass 31, count 0 2006.257.19:28:10.07#ibcon#wrote, iclass 31, count 0 2006.257.19:28:10.07#ibcon#about to read 3, iclass 31, count 0 2006.257.19:28:10.09#ibcon#read 3, iclass 31, count 0 2006.257.19:28:10.09#ibcon#about to read 4, iclass 31, count 0 2006.257.19:28:10.09#ibcon#read 4, iclass 31, count 0 2006.257.19:28:10.09#ibcon#about to read 5, iclass 31, count 0 2006.257.19:28:10.09#ibcon#read 5, iclass 31, count 0 2006.257.19:28:10.09#ibcon#about to read 6, iclass 31, count 0 2006.257.19:28:10.09#ibcon#read 6, iclass 31, count 0 2006.257.19:28:10.09#ibcon#end of sib2, iclass 31, count 0 2006.257.19:28:10.09#ibcon#*mode == 0, iclass 31, count 0 2006.257.19:28:10.09#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.19:28:10.09#ibcon#[27=USB\r\n] 2006.257.19:28:10.09#ibcon#*before write, iclass 31, count 0 2006.257.19:28:10.09#ibcon#enter sib2, iclass 31, count 0 2006.257.19:28:10.09#ibcon#flushed, iclass 31, count 0 2006.257.19:28:10.09#ibcon#about to write, iclass 31, count 0 2006.257.19:28:10.09#ibcon#wrote, iclass 31, count 0 2006.257.19:28:10.09#ibcon#about to read 3, iclass 31, count 0 2006.257.19:28:10.12#ibcon#read 3, iclass 31, count 0 2006.257.19:28:10.12#ibcon#about to read 4, iclass 31, count 0 2006.257.19:28:10.12#ibcon#read 4, iclass 31, count 0 2006.257.19:28:10.12#ibcon#about to read 5, iclass 31, count 0 2006.257.19:28:10.12#ibcon#read 5, iclass 31, count 0 2006.257.19:28:10.12#ibcon#about to read 6, iclass 31, count 0 2006.257.19:28:10.12#ibcon#read 6, iclass 31, count 0 2006.257.19:28:10.12#ibcon#end of sib2, iclass 31, count 0 2006.257.19:28:10.12#ibcon#*after write, iclass 31, count 0 2006.257.19:28:10.12#ibcon#*before return 0, iclass 31, count 0 2006.257.19:28:10.12#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:10.12#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:28:10.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.19:28:10.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.19:28:10.12$vck44/vblo=7,734.99 2006.257.19:28:10.12#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.19:28:10.12#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.19:28:10.12#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:10.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:10.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:10.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:10.12#ibcon#enter wrdev, iclass 33, count 0 2006.257.19:28:10.12#ibcon#first serial, iclass 33, count 0 2006.257.19:28:10.12#ibcon#enter sib2, iclass 33, count 0 2006.257.19:28:10.12#ibcon#flushed, iclass 33, count 0 2006.257.19:28:10.12#ibcon#about to write, iclass 33, count 0 2006.257.19:28:10.12#ibcon#wrote, iclass 33, count 0 2006.257.19:28:10.12#ibcon#about to read 3, iclass 33, count 0 2006.257.19:28:10.14#ibcon#read 3, iclass 33, count 0 2006.257.19:28:10.14#ibcon#about to read 4, iclass 33, count 0 2006.257.19:28:10.14#ibcon#read 4, iclass 33, count 0 2006.257.19:28:10.14#ibcon#about to read 5, iclass 33, count 0 2006.257.19:28:10.14#ibcon#read 5, iclass 33, count 0 2006.257.19:28:10.14#ibcon#about to read 6, iclass 33, count 0 2006.257.19:28:10.14#ibcon#read 6, iclass 33, count 0 2006.257.19:28:10.14#ibcon#end of sib2, iclass 33, count 0 2006.257.19:28:10.14#ibcon#*mode == 0, iclass 33, count 0 2006.257.19:28:10.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.19:28:10.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.19:28:10.14#ibcon#*before write, iclass 33, count 0 2006.257.19:28:10.14#ibcon#enter sib2, iclass 33, count 0 2006.257.19:28:10.14#ibcon#flushed, iclass 33, count 0 2006.257.19:28:10.14#ibcon#about to write, iclass 33, count 0 2006.257.19:28:10.14#ibcon#wrote, iclass 33, count 0 2006.257.19:28:10.14#ibcon#about to read 3, iclass 33, count 0 2006.257.19:28:10.18#ibcon#read 3, iclass 33, count 0 2006.257.19:28:10.18#ibcon#about to read 4, iclass 33, count 0 2006.257.19:28:10.18#ibcon#read 4, iclass 33, count 0 2006.257.19:28:10.18#ibcon#about to read 5, iclass 33, count 0 2006.257.19:28:10.18#ibcon#read 5, iclass 33, count 0 2006.257.19:28:10.18#ibcon#about to read 6, iclass 33, count 0 2006.257.19:28:10.18#ibcon#read 6, iclass 33, count 0 2006.257.19:28:10.18#ibcon#end of sib2, iclass 33, count 0 2006.257.19:28:10.18#ibcon#*after write, iclass 33, count 0 2006.257.19:28:10.18#ibcon#*before return 0, iclass 33, count 0 2006.257.19:28:10.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:10.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:28:10.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.19:28:10.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.19:28:10.18$vck44/vb=7,4 2006.257.19:28:10.18#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.19:28:10.18#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.19:28:10.18#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:10.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:10.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:10.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:10.24#ibcon#enter wrdev, iclass 35, count 2 2006.257.19:28:10.24#ibcon#first serial, iclass 35, count 2 2006.257.19:28:10.24#ibcon#enter sib2, iclass 35, count 2 2006.257.19:28:10.24#ibcon#flushed, iclass 35, count 2 2006.257.19:28:10.24#ibcon#about to write, iclass 35, count 2 2006.257.19:28:10.24#ibcon#wrote, iclass 35, count 2 2006.257.19:28:10.24#ibcon#about to read 3, iclass 35, count 2 2006.257.19:28:10.26#ibcon#read 3, iclass 35, count 2 2006.257.19:28:10.26#ibcon#about to read 4, iclass 35, count 2 2006.257.19:28:10.26#ibcon#read 4, iclass 35, count 2 2006.257.19:28:10.26#ibcon#about to read 5, iclass 35, count 2 2006.257.19:28:10.26#ibcon#read 5, iclass 35, count 2 2006.257.19:28:10.26#ibcon#about to read 6, iclass 35, count 2 2006.257.19:28:10.26#ibcon#read 6, iclass 35, count 2 2006.257.19:28:10.26#ibcon#end of sib2, iclass 35, count 2 2006.257.19:28:10.26#ibcon#*mode == 0, iclass 35, count 2 2006.257.19:28:10.26#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.19:28:10.26#ibcon#[27=AT07-04\r\n] 2006.257.19:28:10.26#ibcon#*before write, iclass 35, count 2 2006.257.19:28:10.26#ibcon#enter sib2, iclass 35, count 2 2006.257.19:28:10.26#ibcon#flushed, iclass 35, count 2 2006.257.19:28:10.26#ibcon#about to write, iclass 35, count 2 2006.257.19:28:10.26#ibcon#wrote, iclass 35, count 2 2006.257.19:28:10.26#ibcon#about to read 3, iclass 35, count 2 2006.257.19:28:10.29#ibcon#read 3, iclass 35, count 2 2006.257.19:28:10.29#ibcon#about to read 4, iclass 35, count 2 2006.257.19:28:10.29#ibcon#read 4, iclass 35, count 2 2006.257.19:28:10.29#ibcon#about to read 5, iclass 35, count 2 2006.257.19:28:10.29#ibcon#read 5, iclass 35, count 2 2006.257.19:28:10.29#ibcon#about to read 6, iclass 35, count 2 2006.257.19:28:10.29#ibcon#read 6, iclass 35, count 2 2006.257.19:28:10.29#ibcon#end of sib2, iclass 35, count 2 2006.257.19:28:10.29#ibcon#*after write, iclass 35, count 2 2006.257.19:28:10.29#ibcon#*before return 0, iclass 35, count 2 2006.257.19:28:10.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:10.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:28:10.29#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.19:28:10.29#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:10.29#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:10.41#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:10.41#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:10.41#ibcon#enter wrdev, iclass 35, count 0 2006.257.19:28:10.41#ibcon#first serial, iclass 35, count 0 2006.257.19:28:10.41#ibcon#enter sib2, iclass 35, count 0 2006.257.19:28:10.41#ibcon#flushed, iclass 35, count 0 2006.257.19:28:10.41#ibcon#about to write, iclass 35, count 0 2006.257.19:28:10.41#ibcon#wrote, iclass 35, count 0 2006.257.19:28:10.41#ibcon#about to read 3, iclass 35, count 0 2006.257.19:28:10.43#ibcon#read 3, iclass 35, count 0 2006.257.19:28:10.43#ibcon#about to read 4, iclass 35, count 0 2006.257.19:28:10.43#ibcon#read 4, iclass 35, count 0 2006.257.19:28:10.43#ibcon#about to read 5, iclass 35, count 0 2006.257.19:28:10.43#ibcon#read 5, iclass 35, count 0 2006.257.19:28:10.43#ibcon#about to read 6, iclass 35, count 0 2006.257.19:28:10.43#ibcon#read 6, iclass 35, count 0 2006.257.19:28:10.43#ibcon#end of sib2, iclass 35, count 0 2006.257.19:28:10.43#ibcon#*mode == 0, iclass 35, count 0 2006.257.19:28:10.43#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.19:28:10.43#ibcon#[27=USB\r\n] 2006.257.19:28:10.43#ibcon#*before write, iclass 35, count 0 2006.257.19:28:10.43#ibcon#enter sib2, iclass 35, count 0 2006.257.19:28:10.43#ibcon#flushed, iclass 35, count 0 2006.257.19:28:10.43#ibcon#about to write, iclass 35, count 0 2006.257.19:28:10.43#ibcon#wrote, iclass 35, count 0 2006.257.19:28:10.43#ibcon#about to read 3, iclass 35, count 0 2006.257.19:28:10.46#ibcon#read 3, iclass 35, count 0 2006.257.19:28:10.46#ibcon#about to read 4, iclass 35, count 0 2006.257.19:28:10.46#ibcon#read 4, iclass 35, count 0 2006.257.19:28:10.46#ibcon#about to read 5, iclass 35, count 0 2006.257.19:28:10.46#ibcon#read 5, iclass 35, count 0 2006.257.19:28:10.46#ibcon#about to read 6, iclass 35, count 0 2006.257.19:28:10.46#ibcon#read 6, iclass 35, count 0 2006.257.19:28:10.46#ibcon#end of sib2, iclass 35, count 0 2006.257.19:28:10.46#ibcon#*after write, iclass 35, count 0 2006.257.19:28:10.46#ibcon#*before return 0, iclass 35, count 0 2006.257.19:28:10.46#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:10.46#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:28:10.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.19:28:10.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.19:28:10.46$vck44/vblo=8,744.99 2006.257.19:28:10.46#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.19:28:10.46#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.19:28:10.46#ibcon#ireg 17 cls_cnt 0 2006.257.19:28:10.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:10.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:10.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:10.46#ibcon#enter wrdev, iclass 37, count 0 2006.257.19:28:10.46#ibcon#first serial, iclass 37, count 0 2006.257.19:28:10.46#ibcon#enter sib2, iclass 37, count 0 2006.257.19:28:10.46#ibcon#flushed, iclass 37, count 0 2006.257.19:28:10.46#ibcon#about to write, iclass 37, count 0 2006.257.19:28:10.46#ibcon#wrote, iclass 37, count 0 2006.257.19:28:10.46#ibcon#about to read 3, iclass 37, count 0 2006.257.19:28:10.48#ibcon#read 3, iclass 37, count 0 2006.257.19:28:10.48#ibcon#about to read 4, iclass 37, count 0 2006.257.19:28:10.48#ibcon#read 4, iclass 37, count 0 2006.257.19:28:10.48#ibcon#about to read 5, iclass 37, count 0 2006.257.19:28:10.48#ibcon#read 5, iclass 37, count 0 2006.257.19:28:10.48#ibcon#about to read 6, iclass 37, count 0 2006.257.19:28:10.48#ibcon#read 6, iclass 37, count 0 2006.257.19:28:10.48#ibcon#end of sib2, iclass 37, count 0 2006.257.19:28:10.48#ibcon#*mode == 0, iclass 37, count 0 2006.257.19:28:10.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.19:28:10.48#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.19:28:10.48#ibcon#*before write, iclass 37, count 0 2006.257.19:28:10.48#ibcon#enter sib2, iclass 37, count 0 2006.257.19:28:10.48#ibcon#flushed, iclass 37, count 0 2006.257.19:28:10.48#ibcon#about to write, iclass 37, count 0 2006.257.19:28:10.48#ibcon#wrote, iclass 37, count 0 2006.257.19:28:10.48#ibcon#about to read 3, iclass 37, count 0 2006.257.19:28:10.52#ibcon#read 3, iclass 37, count 0 2006.257.19:28:10.52#ibcon#about to read 4, iclass 37, count 0 2006.257.19:28:10.52#ibcon#read 4, iclass 37, count 0 2006.257.19:28:10.52#ibcon#about to read 5, iclass 37, count 0 2006.257.19:28:10.52#ibcon#read 5, iclass 37, count 0 2006.257.19:28:10.52#ibcon#about to read 6, iclass 37, count 0 2006.257.19:28:10.52#ibcon#read 6, iclass 37, count 0 2006.257.19:28:10.52#ibcon#end of sib2, iclass 37, count 0 2006.257.19:28:10.52#ibcon#*after write, iclass 37, count 0 2006.257.19:28:10.52#ibcon#*before return 0, iclass 37, count 0 2006.257.19:28:10.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:10.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:28:10.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.19:28:10.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.19:28:10.52$vck44/vb=8,4 2006.257.19:28:10.52#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.19:28:10.52#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.19:28:10.52#ibcon#ireg 11 cls_cnt 2 2006.257.19:28:10.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:10.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:10.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:10.58#ibcon#enter wrdev, iclass 39, count 2 2006.257.19:28:10.58#ibcon#first serial, iclass 39, count 2 2006.257.19:28:10.58#ibcon#enter sib2, iclass 39, count 2 2006.257.19:28:10.58#ibcon#flushed, iclass 39, count 2 2006.257.19:28:10.58#ibcon#about to write, iclass 39, count 2 2006.257.19:28:10.58#ibcon#wrote, iclass 39, count 2 2006.257.19:28:10.58#ibcon#about to read 3, iclass 39, count 2 2006.257.19:28:10.60#ibcon#read 3, iclass 39, count 2 2006.257.19:28:10.60#ibcon#about to read 4, iclass 39, count 2 2006.257.19:28:10.60#ibcon#read 4, iclass 39, count 2 2006.257.19:28:10.60#ibcon#about to read 5, iclass 39, count 2 2006.257.19:28:10.60#ibcon#read 5, iclass 39, count 2 2006.257.19:28:10.60#ibcon#about to read 6, iclass 39, count 2 2006.257.19:28:10.60#ibcon#read 6, iclass 39, count 2 2006.257.19:28:10.60#ibcon#end of sib2, iclass 39, count 2 2006.257.19:28:10.60#ibcon#*mode == 0, iclass 39, count 2 2006.257.19:28:10.60#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.19:28:10.60#ibcon#[27=AT08-04\r\n] 2006.257.19:28:10.60#ibcon#*before write, iclass 39, count 2 2006.257.19:28:10.60#ibcon#enter sib2, iclass 39, count 2 2006.257.19:28:10.60#ibcon#flushed, iclass 39, count 2 2006.257.19:28:10.60#ibcon#about to write, iclass 39, count 2 2006.257.19:28:10.60#ibcon#wrote, iclass 39, count 2 2006.257.19:28:10.60#ibcon#about to read 3, iclass 39, count 2 2006.257.19:28:10.63#ibcon#read 3, iclass 39, count 2 2006.257.19:28:10.63#ibcon#about to read 4, iclass 39, count 2 2006.257.19:28:10.63#ibcon#read 4, iclass 39, count 2 2006.257.19:28:10.63#ibcon#about to read 5, iclass 39, count 2 2006.257.19:28:10.63#ibcon#read 5, iclass 39, count 2 2006.257.19:28:10.63#ibcon#about to read 6, iclass 39, count 2 2006.257.19:28:10.63#ibcon#read 6, iclass 39, count 2 2006.257.19:28:10.63#ibcon#end of sib2, iclass 39, count 2 2006.257.19:28:10.63#ibcon#*after write, iclass 39, count 2 2006.257.19:28:10.63#ibcon#*before return 0, iclass 39, count 2 2006.257.19:28:10.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:10.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:28:10.63#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.19:28:10.63#ibcon#ireg 7 cls_cnt 0 2006.257.19:28:10.63#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:10.75#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:10.75#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:10.75#ibcon#enter wrdev, iclass 39, count 0 2006.257.19:28:10.75#ibcon#first serial, iclass 39, count 0 2006.257.19:28:10.75#ibcon#enter sib2, iclass 39, count 0 2006.257.19:28:10.75#ibcon#flushed, iclass 39, count 0 2006.257.19:28:10.75#ibcon#about to write, iclass 39, count 0 2006.257.19:28:10.75#ibcon#wrote, iclass 39, count 0 2006.257.19:28:10.75#ibcon#about to read 3, iclass 39, count 0 2006.257.19:28:10.77#ibcon#read 3, iclass 39, count 0 2006.257.19:28:10.77#ibcon#about to read 4, iclass 39, count 0 2006.257.19:28:10.77#ibcon#read 4, iclass 39, count 0 2006.257.19:28:10.77#ibcon#about to read 5, iclass 39, count 0 2006.257.19:28:10.77#ibcon#read 5, iclass 39, count 0 2006.257.19:28:10.77#ibcon#about to read 6, iclass 39, count 0 2006.257.19:28:10.77#ibcon#read 6, iclass 39, count 0 2006.257.19:28:10.77#ibcon#end of sib2, iclass 39, count 0 2006.257.19:28:10.77#ibcon#*mode == 0, iclass 39, count 0 2006.257.19:28:10.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.19:28:10.77#ibcon#[27=USB\r\n] 2006.257.19:28:10.77#ibcon#*before write, iclass 39, count 0 2006.257.19:28:10.77#ibcon#enter sib2, iclass 39, count 0 2006.257.19:28:10.77#ibcon#flushed, iclass 39, count 0 2006.257.19:28:10.77#ibcon#about to write, iclass 39, count 0 2006.257.19:28:10.77#ibcon#wrote, iclass 39, count 0 2006.257.19:28:10.77#ibcon#about to read 3, iclass 39, count 0 2006.257.19:28:10.80#ibcon#read 3, iclass 39, count 0 2006.257.19:28:10.80#ibcon#about to read 4, iclass 39, count 0 2006.257.19:28:10.80#ibcon#read 4, iclass 39, count 0 2006.257.19:28:10.80#ibcon#about to read 5, iclass 39, count 0 2006.257.19:28:10.80#ibcon#read 5, iclass 39, count 0 2006.257.19:28:10.80#ibcon#about to read 6, iclass 39, count 0 2006.257.19:28:10.80#ibcon#read 6, iclass 39, count 0 2006.257.19:28:10.80#ibcon#end of sib2, iclass 39, count 0 2006.257.19:28:10.80#ibcon#*after write, iclass 39, count 0 2006.257.19:28:10.80#ibcon#*before return 0, iclass 39, count 0 2006.257.19:28:10.80#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:10.80#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:28:10.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.19:28:10.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.19:28:10.80$vck44/vabw=wide 2006.257.19:28:10.80#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.19:28:10.80#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.19:28:10.80#ibcon#ireg 8 cls_cnt 0 2006.257.19:28:10.80#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:10.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:10.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:10.80#ibcon#enter wrdev, iclass 3, count 0 2006.257.19:28:10.80#ibcon#first serial, iclass 3, count 0 2006.257.19:28:10.80#ibcon#enter sib2, iclass 3, count 0 2006.257.19:28:10.80#ibcon#flushed, iclass 3, count 0 2006.257.19:28:10.80#ibcon#about to write, iclass 3, count 0 2006.257.19:28:10.80#ibcon#wrote, iclass 3, count 0 2006.257.19:28:10.80#ibcon#about to read 3, iclass 3, count 0 2006.257.19:28:10.82#ibcon#read 3, iclass 3, count 0 2006.257.19:28:10.82#ibcon#about to read 4, iclass 3, count 0 2006.257.19:28:10.82#ibcon#read 4, iclass 3, count 0 2006.257.19:28:10.82#ibcon#about to read 5, iclass 3, count 0 2006.257.19:28:10.82#ibcon#read 5, iclass 3, count 0 2006.257.19:28:10.82#ibcon#about to read 6, iclass 3, count 0 2006.257.19:28:10.82#ibcon#read 6, iclass 3, count 0 2006.257.19:28:10.82#ibcon#end of sib2, iclass 3, count 0 2006.257.19:28:10.82#ibcon#*mode == 0, iclass 3, count 0 2006.257.19:28:10.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.19:28:10.82#ibcon#[25=BW32\r\n] 2006.257.19:28:10.82#ibcon#*before write, iclass 3, count 0 2006.257.19:28:10.82#ibcon#enter sib2, iclass 3, count 0 2006.257.19:28:10.82#ibcon#flushed, iclass 3, count 0 2006.257.19:28:10.82#ibcon#about to write, iclass 3, count 0 2006.257.19:28:10.82#ibcon#wrote, iclass 3, count 0 2006.257.19:28:10.82#ibcon#about to read 3, iclass 3, count 0 2006.257.19:28:10.85#ibcon#read 3, iclass 3, count 0 2006.257.19:28:10.85#ibcon#about to read 4, iclass 3, count 0 2006.257.19:28:10.85#ibcon#read 4, iclass 3, count 0 2006.257.19:28:10.85#ibcon#about to read 5, iclass 3, count 0 2006.257.19:28:10.85#ibcon#read 5, iclass 3, count 0 2006.257.19:28:10.85#ibcon#about to read 6, iclass 3, count 0 2006.257.19:28:10.85#ibcon#read 6, iclass 3, count 0 2006.257.19:28:10.85#ibcon#end of sib2, iclass 3, count 0 2006.257.19:28:10.85#ibcon#*after write, iclass 3, count 0 2006.257.19:28:10.85#ibcon#*before return 0, iclass 3, count 0 2006.257.19:28:10.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:10.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:28:10.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.19:28:10.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.19:28:10.85$vck44/vbbw=wide 2006.257.19:28:10.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.19:28:10.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.19:28:10.85#ibcon#ireg 8 cls_cnt 0 2006.257.19:28:10.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:28:10.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:28:10.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:28:10.92#ibcon#enter wrdev, iclass 5, count 0 2006.257.19:28:10.92#ibcon#first serial, iclass 5, count 0 2006.257.19:28:10.92#ibcon#enter sib2, iclass 5, count 0 2006.257.19:28:10.92#ibcon#flushed, iclass 5, count 0 2006.257.19:28:10.92#ibcon#about to write, iclass 5, count 0 2006.257.19:28:10.92#ibcon#wrote, iclass 5, count 0 2006.257.19:28:10.92#ibcon#about to read 3, iclass 5, count 0 2006.257.19:28:10.94#ibcon#read 3, iclass 5, count 0 2006.257.19:28:10.94#ibcon#about to read 4, iclass 5, count 0 2006.257.19:28:10.94#ibcon#read 4, iclass 5, count 0 2006.257.19:28:10.94#ibcon#about to read 5, iclass 5, count 0 2006.257.19:28:10.94#ibcon#read 5, iclass 5, count 0 2006.257.19:28:10.94#ibcon#about to read 6, iclass 5, count 0 2006.257.19:28:10.94#ibcon#read 6, iclass 5, count 0 2006.257.19:28:10.94#ibcon#end of sib2, iclass 5, count 0 2006.257.19:28:10.94#ibcon#*mode == 0, iclass 5, count 0 2006.257.19:28:10.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.19:28:10.94#ibcon#[27=BW32\r\n] 2006.257.19:28:10.94#ibcon#*before write, iclass 5, count 0 2006.257.19:28:10.94#ibcon#enter sib2, iclass 5, count 0 2006.257.19:28:10.94#ibcon#flushed, iclass 5, count 0 2006.257.19:28:10.94#ibcon#about to write, iclass 5, count 0 2006.257.19:28:10.94#ibcon#wrote, iclass 5, count 0 2006.257.19:28:10.94#ibcon#about to read 3, iclass 5, count 0 2006.257.19:28:10.97#ibcon#read 3, iclass 5, count 0 2006.257.19:28:10.97#ibcon#about to read 4, iclass 5, count 0 2006.257.19:28:10.97#ibcon#read 4, iclass 5, count 0 2006.257.19:28:10.97#ibcon#about to read 5, iclass 5, count 0 2006.257.19:28:10.97#ibcon#read 5, iclass 5, count 0 2006.257.19:28:10.97#ibcon#about to read 6, iclass 5, count 0 2006.257.19:28:10.97#ibcon#read 6, iclass 5, count 0 2006.257.19:28:10.97#ibcon#end of sib2, iclass 5, count 0 2006.257.19:28:10.97#ibcon#*after write, iclass 5, count 0 2006.257.19:28:10.97#ibcon#*before return 0, iclass 5, count 0 2006.257.19:28:10.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:28:10.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:28:10.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.19:28:10.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.19:28:10.97$setupk4/ifdk4 2006.257.19:28:10.97$ifdk4/lo= 2006.257.19:28:10.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.19:28:10.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.19:28:10.97$ifdk4/patch= 2006.257.19:28:10.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.19:28:10.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.19:28:10.97$setupk4/!*+20s 2006.257.19:28:13.21#abcon#<5=/14 1.5 3.6 17.51 961014.4\r\n> 2006.257.19:28:13.23#abcon#{5=INTERFACE CLEAR} 2006.257.19:28:13.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:28:19.14#trakl#Source acquired 2006.257.19:28:20.14#flagr#flagr/antenna,acquired 2006.257.19:28:23.38#abcon#<5=/14 1.6 3.6 17.51 961014.4\r\n> 2006.257.19:28:23.40#abcon#{5=INTERFACE CLEAR} 2006.257.19:28:23.46#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:28:25.48$setupk4/"tpicd 2006.257.19:28:25.48$setupk4/echo=off 2006.257.19:28:25.48$setupk4/xlog=off 2006.257.19:28:25.48:!2006.257.19:38:07 2006.257.19:38:07.00:preob 2006.257.19:38:07.14/onsource/TRACKING 2006.257.19:38:07.14:!2006.257.19:38:17 2006.257.19:38:17.00:"tape 2006.257.19:38:17.00:"st=record 2006.257.19:38:17.00:data_valid=on 2006.257.19:38:17.00:midob 2006.257.19:38:17.14/onsource/TRACKING 2006.257.19:38:17.14/wx/17.53,1014.5,96 2006.257.19:38:17.23/cable/+6.4861E-03 2006.257.19:38:18.32/va/01,08,usb,yes,32,34 2006.257.19:38:18.32/va/02,07,usb,yes,35,35 2006.257.19:38:18.32/va/03,08,usb,yes,31,33 2006.257.19:38:18.32/va/04,07,usb,yes,36,37 2006.257.19:38:18.32/va/05,04,usb,yes,32,32 2006.257.19:38:18.32/va/06,04,usb,yes,35,35 2006.257.19:38:18.32/va/07,04,usb,yes,36,36 2006.257.19:38:18.32/va/08,04,usb,yes,30,37 2006.257.19:38:18.55/valo/01,524.99,yes,locked 2006.257.19:38:18.55/valo/02,534.99,yes,locked 2006.257.19:38:18.55/valo/03,564.99,yes,locked 2006.257.19:38:18.55/valo/04,624.99,yes,locked 2006.257.19:38:18.55/valo/05,734.99,yes,locked 2006.257.19:38:18.55/valo/06,814.99,yes,locked 2006.257.19:38:18.55/valo/07,864.99,yes,locked 2006.257.19:38:18.55/valo/08,884.99,yes,locked 2006.257.19:38:19.64/vb/01,04,usb,yes,30,28 2006.257.19:38:19.64/vb/02,05,usb,yes,29,29 2006.257.19:38:19.64/vb/03,04,usb,yes,30,33 2006.257.19:38:19.64/vb/04,05,usb,yes,30,29 2006.257.19:38:19.64/vb/05,04,usb,yes,26,29 2006.257.19:38:19.64/vb/06,04,usb,yes,31,27 2006.257.19:38:19.64/vb/07,04,usb,yes,31,30 2006.257.19:38:19.64/vb/08,04,usb,yes,28,31 2006.257.19:38:19.88/vblo/01,629.99,yes,locked 2006.257.19:38:19.88/vblo/02,634.99,yes,locked 2006.257.19:38:19.88/vblo/03,649.99,yes,locked 2006.257.19:38:19.88/vblo/04,679.99,yes,locked 2006.257.19:38:19.88/vblo/05,709.99,yes,locked 2006.257.19:38:19.88/vblo/06,719.99,yes,locked 2006.257.19:38:19.88/vblo/07,734.99,yes,locked 2006.257.19:38:19.88/vblo/08,744.99,yes,locked 2006.257.19:38:20.03/vabw/8 2006.257.19:38:20.18/vbbw/8 2006.257.19:38:20.27/xfe/off,on,15.0 2006.257.19:38:20.64/ifatt/23,28,28,28 2006.257.19:38:21.07/fmout-gps/S +4.53E-07 2006.257.19:38:21.11:!2006.257.19:40:07 2006.257.19:40:07.00:data_valid=off 2006.257.19:40:07.00:"et 2006.257.19:40:07.00:!+3s 2006.257.19:40:10.03:"tape 2006.257.19:40:10.03:postob 2006.257.19:40:10.24/cable/+6.4868E-03 2006.257.19:40:10.24/wx/17.52,1014.5,96 2006.257.19:40:10.30/fmout-gps/S +4.53E-07 2006.257.19:40:10.30:scan_name=257-1942,jd0609,230 2006.257.19:40:10.30:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.257.19:40:11.14#flagr#flagr/antenna,new-source 2006.257.19:40:11.14:checkk5 2006.257.19:40:11.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.19:40:11.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.19:40:12.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.19:40:12.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.19:40:12.86/chk_obsdata//k5ts1/T2571938??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.19:40:13.19/chk_obsdata//k5ts2/T2571938??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.19:40:13.53/chk_obsdata//k5ts3/T2571938??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.19:40:13.86/chk_obsdata//k5ts4/T2571938??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.19:40:14.53/k5log//k5ts1_log_newline 2006.257.19:40:15.19/k5log//k5ts2_log_newline 2006.257.19:40:15.85/k5log//k5ts3_log_newline 2006.257.19:40:16.51/k5log//k5ts4_log_newline 2006.257.19:40:16.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.19:40:16.53:setupk4=1 2006.257.19:40:16.53$setupk4/echo=on 2006.257.19:40:16.53$setupk4/pcalon 2006.257.19:40:16.53$pcalon/"no phase cal control is implemented here 2006.257.19:40:16.53$setupk4/"tpicd=stop 2006.257.19:40:16.53$setupk4/"rec=synch_on 2006.257.19:40:16.53$setupk4/"rec_mode=128 2006.257.19:40:16.53$setupk4/!* 2006.257.19:40:16.53$setupk4/recpk4 2006.257.19:40:16.53$recpk4/recpatch= 2006.257.19:40:16.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.19:40:16.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.19:40:16.53$setupk4/vck44 2006.257.19:40:16.53$vck44/valo=1,524.99 2006.257.19:40:16.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.19:40:16.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.19:40:16.53#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:16.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:16.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:16.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:16.53#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:40:16.53#ibcon#first serial, iclass 12, count 0 2006.257.19:40:16.53#ibcon#enter sib2, iclass 12, count 0 2006.257.19:40:16.53#ibcon#flushed, iclass 12, count 0 2006.257.19:40:16.53#ibcon#about to write, iclass 12, count 0 2006.257.19:40:16.53#ibcon#wrote, iclass 12, count 0 2006.257.19:40:16.53#ibcon#about to read 3, iclass 12, count 0 2006.257.19:40:16.55#ibcon#read 3, iclass 12, count 0 2006.257.19:40:16.55#ibcon#about to read 4, iclass 12, count 0 2006.257.19:40:16.55#ibcon#read 4, iclass 12, count 0 2006.257.19:40:16.55#ibcon#about to read 5, iclass 12, count 0 2006.257.19:40:16.55#ibcon#read 5, iclass 12, count 0 2006.257.19:40:16.55#ibcon#about to read 6, iclass 12, count 0 2006.257.19:40:16.55#ibcon#read 6, iclass 12, count 0 2006.257.19:40:16.55#ibcon#end of sib2, iclass 12, count 0 2006.257.19:40:16.55#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:40:16.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:40:16.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.19:40:16.55#ibcon#*before write, iclass 12, count 0 2006.257.19:40:16.55#ibcon#enter sib2, iclass 12, count 0 2006.257.19:40:16.55#ibcon#flushed, iclass 12, count 0 2006.257.19:40:16.55#ibcon#about to write, iclass 12, count 0 2006.257.19:40:16.55#ibcon#wrote, iclass 12, count 0 2006.257.19:40:16.55#ibcon#about to read 3, iclass 12, count 0 2006.257.19:40:16.60#ibcon#read 3, iclass 12, count 0 2006.257.19:40:16.60#ibcon#about to read 4, iclass 12, count 0 2006.257.19:40:16.60#ibcon#read 4, iclass 12, count 0 2006.257.19:40:16.60#ibcon#about to read 5, iclass 12, count 0 2006.257.19:40:16.60#ibcon#read 5, iclass 12, count 0 2006.257.19:40:16.60#ibcon#about to read 6, iclass 12, count 0 2006.257.19:40:16.60#ibcon#read 6, iclass 12, count 0 2006.257.19:40:16.60#ibcon#end of sib2, iclass 12, count 0 2006.257.19:40:16.60#ibcon#*after write, iclass 12, count 0 2006.257.19:40:16.60#ibcon#*before return 0, iclass 12, count 0 2006.257.19:40:16.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:16.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:16.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:40:16.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:40:16.60$vck44/va=1,8 2006.257.19:40:16.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.19:40:16.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.19:40:16.60#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:16.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:16.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:16.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:16.60#ibcon#enter wrdev, iclass 14, count 2 2006.257.19:40:16.60#ibcon#first serial, iclass 14, count 2 2006.257.19:40:16.60#ibcon#enter sib2, iclass 14, count 2 2006.257.19:40:16.60#ibcon#flushed, iclass 14, count 2 2006.257.19:40:16.60#ibcon#about to write, iclass 14, count 2 2006.257.19:40:16.60#ibcon#wrote, iclass 14, count 2 2006.257.19:40:16.60#ibcon#about to read 3, iclass 14, count 2 2006.257.19:40:16.62#ibcon#read 3, iclass 14, count 2 2006.257.19:40:16.62#ibcon#about to read 4, iclass 14, count 2 2006.257.19:40:16.62#ibcon#read 4, iclass 14, count 2 2006.257.19:40:16.62#ibcon#about to read 5, iclass 14, count 2 2006.257.19:40:16.62#ibcon#read 5, iclass 14, count 2 2006.257.19:40:16.62#ibcon#about to read 6, iclass 14, count 2 2006.257.19:40:16.62#ibcon#read 6, iclass 14, count 2 2006.257.19:40:16.62#ibcon#end of sib2, iclass 14, count 2 2006.257.19:40:16.62#ibcon#*mode == 0, iclass 14, count 2 2006.257.19:40:16.62#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.19:40:16.62#ibcon#[25=AT01-08\r\n] 2006.257.19:40:16.62#ibcon#*before write, iclass 14, count 2 2006.257.19:40:16.62#ibcon#enter sib2, iclass 14, count 2 2006.257.19:40:16.62#ibcon#flushed, iclass 14, count 2 2006.257.19:40:16.62#ibcon#about to write, iclass 14, count 2 2006.257.19:40:16.62#ibcon#wrote, iclass 14, count 2 2006.257.19:40:16.62#ibcon#about to read 3, iclass 14, count 2 2006.257.19:40:16.65#ibcon#read 3, iclass 14, count 2 2006.257.19:40:16.65#ibcon#about to read 4, iclass 14, count 2 2006.257.19:40:16.65#ibcon#read 4, iclass 14, count 2 2006.257.19:40:16.65#ibcon#about to read 5, iclass 14, count 2 2006.257.19:40:16.65#ibcon#read 5, iclass 14, count 2 2006.257.19:40:16.65#ibcon#about to read 6, iclass 14, count 2 2006.257.19:40:16.65#ibcon#read 6, iclass 14, count 2 2006.257.19:40:16.65#ibcon#end of sib2, iclass 14, count 2 2006.257.19:40:16.65#ibcon#*after write, iclass 14, count 2 2006.257.19:40:16.65#ibcon#*before return 0, iclass 14, count 2 2006.257.19:40:16.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:16.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:16.65#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.19:40:16.65#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:16.65#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:16.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:16.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:16.77#ibcon#enter wrdev, iclass 14, count 0 2006.257.19:40:16.77#ibcon#first serial, iclass 14, count 0 2006.257.19:40:16.77#ibcon#enter sib2, iclass 14, count 0 2006.257.19:40:16.77#ibcon#flushed, iclass 14, count 0 2006.257.19:40:16.77#ibcon#about to write, iclass 14, count 0 2006.257.19:40:16.77#ibcon#wrote, iclass 14, count 0 2006.257.19:40:16.77#ibcon#about to read 3, iclass 14, count 0 2006.257.19:40:16.79#ibcon#read 3, iclass 14, count 0 2006.257.19:40:16.79#ibcon#about to read 4, iclass 14, count 0 2006.257.19:40:16.79#ibcon#read 4, iclass 14, count 0 2006.257.19:40:16.79#ibcon#about to read 5, iclass 14, count 0 2006.257.19:40:16.79#ibcon#read 5, iclass 14, count 0 2006.257.19:40:16.79#ibcon#about to read 6, iclass 14, count 0 2006.257.19:40:16.79#ibcon#read 6, iclass 14, count 0 2006.257.19:40:16.79#ibcon#end of sib2, iclass 14, count 0 2006.257.19:40:16.79#ibcon#*mode == 0, iclass 14, count 0 2006.257.19:40:16.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.19:40:16.79#ibcon#[25=USB\r\n] 2006.257.19:40:16.79#ibcon#*before write, iclass 14, count 0 2006.257.19:40:16.79#ibcon#enter sib2, iclass 14, count 0 2006.257.19:40:16.79#ibcon#flushed, iclass 14, count 0 2006.257.19:40:16.79#ibcon#about to write, iclass 14, count 0 2006.257.19:40:16.79#ibcon#wrote, iclass 14, count 0 2006.257.19:40:16.79#ibcon#about to read 3, iclass 14, count 0 2006.257.19:40:16.82#ibcon#read 3, iclass 14, count 0 2006.257.19:40:16.82#ibcon#about to read 4, iclass 14, count 0 2006.257.19:40:16.82#ibcon#read 4, iclass 14, count 0 2006.257.19:40:16.82#ibcon#about to read 5, iclass 14, count 0 2006.257.19:40:16.82#ibcon#read 5, iclass 14, count 0 2006.257.19:40:16.82#ibcon#about to read 6, iclass 14, count 0 2006.257.19:40:16.82#ibcon#read 6, iclass 14, count 0 2006.257.19:40:16.82#ibcon#end of sib2, iclass 14, count 0 2006.257.19:40:16.82#ibcon#*after write, iclass 14, count 0 2006.257.19:40:16.82#ibcon#*before return 0, iclass 14, count 0 2006.257.19:40:16.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:16.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:16.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.19:40:16.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.19:40:16.82$vck44/valo=2,534.99 2006.257.19:40:16.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.19:40:16.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.19:40:16.82#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:16.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:16.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:16.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:16.82#ibcon#enter wrdev, iclass 16, count 0 2006.257.19:40:16.82#ibcon#first serial, iclass 16, count 0 2006.257.19:40:16.82#ibcon#enter sib2, iclass 16, count 0 2006.257.19:40:16.82#ibcon#flushed, iclass 16, count 0 2006.257.19:40:16.82#ibcon#about to write, iclass 16, count 0 2006.257.19:40:16.82#ibcon#wrote, iclass 16, count 0 2006.257.19:40:16.82#ibcon#about to read 3, iclass 16, count 0 2006.257.19:40:16.84#ibcon#read 3, iclass 16, count 0 2006.257.19:40:16.84#ibcon#about to read 4, iclass 16, count 0 2006.257.19:40:16.84#ibcon#read 4, iclass 16, count 0 2006.257.19:40:16.84#ibcon#about to read 5, iclass 16, count 0 2006.257.19:40:16.84#ibcon#read 5, iclass 16, count 0 2006.257.19:40:16.84#ibcon#about to read 6, iclass 16, count 0 2006.257.19:40:16.84#ibcon#read 6, iclass 16, count 0 2006.257.19:40:16.84#ibcon#end of sib2, iclass 16, count 0 2006.257.19:40:16.84#ibcon#*mode == 0, iclass 16, count 0 2006.257.19:40:16.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.19:40:16.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.19:40:16.84#ibcon#*before write, iclass 16, count 0 2006.257.19:40:16.84#ibcon#enter sib2, iclass 16, count 0 2006.257.19:40:16.84#ibcon#flushed, iclass 16, count 0 2006.257.19:40:16.84#ibcon#about to write, iclass 16, count 0 2006.257.19:40:16.84#ibcon#wrote, iclass 16, count 0 2006.257.19:40:16.84#ibcon#about to read 3, iclass 16, count 0 2006.257.19:40:16.88#ibcon#read 3, iclass 16, count 0 2006.257.19:40:16.88#ibcon#about to read 4, iclass 16, count 0 2006.257.19:40:16.88#ibcon#read 4, iclass 16, count 0 2006.257.19:40:16.88#ibcon#about to read 5, iclass 16, count 0 2006.257.19:40:16.88#ibcon#read 5, iclass 16, count 0 2006.257.19:40:16.88#ibcon#about to read 6, iclass 16, count 0 2006.257.19:40:16.88#ibcon#read 6, iclass 16, count 0 2006.257.19:40:16.88#ibcon#end of sib2, iclass 16, count 0 2006.257.19:40:16.88#ibcon#*after write, iclass 16, count 0 2006.257.19:40:16.88#ibcon#*before return 0, iclass 16, count 0 2006.257.19:40:16.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:16.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:16.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.19:40:16.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.19:40:16.88$vck44/va=2,7 2006.257.19:40:16.88#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.19:40:16.88#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.19:40:16.88#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:16.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:16.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:16.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:16.94#ibcon#enter wrdev, iclass 18, count 2 2006.257.19:40:16.94#ibcon#first serial, iclass 18, count 2 2006.257.19:40:16.94#ibcon#enter sib2, iclass 18, count 2 2006.257.19:40:16.94#ibcon#flushed, iclass 18, count 2 2006.257.19:40:16.94#ibcon#about to write, iclass 18, count 2 2006.257.19:40:16.94#ibcon#wrote, iclass 18, count 2 2006.257.19:40:16.94#ibcon#about to read 3, iclass 18, count 2 2006.257.19:40:16.96#ibcon#read 3, iclass 18, count 2 2006.257.19:40:16.96#ibcon#about to read 4, iclass 18, count 2 2006.257.19:40:16.96#ibcon#read 4, iclass 18, count 2 2006.257.19:40:16.96#ibcon#about to read 5, iclass 18, count 2 2006.257.19:40:16.96#ibcon#read 5, iclass 18, count 2 2006.257.19:40:16.96#ibcon#about to read 6, iclass 18, count 2 2006.257.19:40:16.96#ibcon#read 6, iclass 18, count 2 2006.257.19:40:16.96#ibcon#end of sib2, iclass 18, count 2 2006.257.19:40:16.96#ibcon#*mode == 0, iclass 18, count 2 2006.257.19:40:16.96#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.19:40:16.96#ibcon#[25=AT02-07\r\n] 2006.257.19:40:16.96#ibcon#*before write, iclass 18, count 2 2006.257.19:40:16.96#ibcon#enter sib2, iclass 18, count 2 2006.257.19:40:16.96#ibcon#flushed, iclass 18, count 2 2006.257.19:40:16.96#ibcon#about to write, iclass 18, count 2 2006.257.19:40:16.96#ibcon#wrote, iclass 18, count 2 2006.257.19:40:16.96#ibcon#about to read 3, iclass 18, count 2 2006.257.19:40:16.99#ibcon#read 3, iclass 18, count 2 2006.257.19:40:16.99#ibcon#about to read 4, iclass 18, count 2 2006.257.19:40:16.99#ibcon#read 4, iclass 18, count 2 2006.257.19:40:16.99#ibcon#about to read 5, iclass 18, count 2 2006.257.19:40:16.99#ibcon#read 5, iclass 18, count 2 2006.257.19:40:16.99#ibcon#about to read 6, iclass 18, count 2 2006.257.19:40:16.99#ibcon#read 6, iclass 18, count 2 2006.257.19:40:16.99#ibcon#end of sib2, iclass 18, count 2 2006.257.19:40:16.99#ibcon#*after write, iclass 18, count 2 2006.257.19:40:16.99#ibcon#*before return 0, iclass 18, count 2 2006.257.19:40:16.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:16.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:16.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.19:40:16.99#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:16.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:17.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:17.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:17.11#ibcon#enter wrdev, iclass 18, count 0 2006.257.19:40:17.11#ibcon#first serial, iclass 18, count 0 2006.257.19:40:17.11#ibcon#enter sib2, iclass 18, count 0 2006.257.19:40:17.11#ibcon#flushed, iclass 18, count 0 2006.257.19:40:17.11#ibcon#about to write, iclass 18, count 0 2006.257.19:40:17.11#ibcon#wrote, iclass 18, count 0 2006.257.19:40:17.11#ibcon#about to read 3, iclass 18, count 0 2006.257.19:40:17.13#ibcon#read 3, iclass 18, count 0 2006.257.19:40:17.13#ibcon#about to read 4, iclass 18, count 0 2006.257.19:40:17.13#ibcon#read 4, iclass 18, count 0 2006.257.19:40:17.13#ibcon#about to read 5, iclass 18, count 0 2006.257.19:40:17.13#ibcon#read 5, iclass 18, count 0 2006.257.19:40:17.13#ibcon#about to read 6, iclass 18, count 0 2006.257.19:40:17.13#ibcon#read 6, iclass 18, count 0 2006.257.19:40:17.13#ibcon#end of sib2, iclass 18, count 0 2006.257.19:40:17.13#ibcon#*mode == 0, iclass 18, count 0 2006.257.19:40:17.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.19:40:17.13#ibcon#[25=USB\r\n] 2006.257.19:40:17.13#ibcon#*before write, iclass 18, count 0 2006.257.19:40:17.13#ibcon#enter sib2, iclass 18, count 0 2006.257.19:40:17.13#ibcon#flushed, iclass 18, count 0 2006.257.19:40:17.13#ibcon#about to write, iclass 18, count 0 2006.257.19:40:17.13#ibcon#wrote, iclass 18, count 0 2006.257.19:40:17.13#ibcon#about to read 3, iclass 18, count 0 2006.257.19:40:17.16#ibcon#read 3, iclass 18, count 0 2006.257.19:40:17.16#ibcon#about to read 4, iclass 18, count 0 2006.257.19:40:17.16#ibcon#read 4, iclass 18, count 0 2006.257.19:40:17.16#ibcon#about to read 5, iclass 18, count 0 2006.257.19:40:17.16#ibcon#read 5, iclass 18, count 0 2006.257.19:40:17.16#ibcon#about to read 6, iclass 18, count 0 2006.257.19:40:17.16#ibcon#read 6, iclass 18, count 0 2006.257.19:40:17.16#ibcon#end of sib2, iclass 18, count 0 2006.257.19:40:17.16#ibcon#*after write, iclass 18, count 0 2006.257.19:40:17.16#ibcon#*before return 0, iclass 18, count 0 2006.257.19:40:17.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:17.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:17.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.19:40:17.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.19:40:17.16$vck44/valo=3,564.99 2006.257.19:40:17.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.19:40:17.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.19:40:17.16#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:17.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:17.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:17.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:17.16#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:40:17.16#ibcon#first serial, iclass 20, count 0 2006.257.19:40:17.16#ibcon#enter sib2, iclass 20, count 0 2006.257.19:40:17.16#ibcon#flushed, iclass 20, count 0 2006.257.19:40:17.16#ibcon#about to write, iclass 20, count 0 2006.257.19:40:17.16#ibcon#wrote, iclass 20, count 0 2006.257.19:40:17.16#ibcon#about to read 3, iclass 20, count 0 2006.257.19:40:17.18#ibcon#read 3, iclass 20, count 0 2006.257.19:40:17.18#ibcon#about to read 4, iclass 20, count 0 2006.257.19:40:17.18#ibcon#read 4, iclass 20, count 0 2006.257.19:40:17.18#ibcon#about to read 5, iclass 20, count 0 2006.257.19:40:17.18#ibcon#read 5, iclass 20, count 0 2006.257.19:40:17.18#ibcon#about to read 6, iclass 20, count 0 2006.257.19:40:17.18#ibcon#read 6, iclass 20, count 0 2006.257.19:40:17.18#ibcon#end of sib2, iclass 20, count 0 2006.257.19:40:17.18#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:40:17.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:40:17.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.19:40:17.18#ibcon#*before write, iclass 20, count 0 2006.257.19:40:17.18#ibcon#enter sib2, iclass 20, count 0 2006.257.19:40:17.18#ibcon#flushed, iclass 20, count 0 2006.257.19:40:17.18#ibcon#about to write, iclass 20, count 0 2006.257.19:40:17.18#ibcon#wrote, iclass 20, count 0 2006.257.19:40:17.18#ibcon#about to read 3, iclass 20, count 0 2006.257.19:40:17.22#ibcon#read 3, iclass 20, count 0 2006.257.19:40:17.22#ibcon#about to read 4, iclass 20, count 0 2006.257.19:40:17.22#ibcon#read 4, iclass 20, count 0 2006.257.19:40:17.22#ibcon#about to read 5, iclass 20, count 0 2006.257.19:40:17.22#ibcon#read 5, iclass 20, count 0 2006.257.19:40:17.22#ibcon#about to read 6, iclass 20, count 0 2006.257.19:40:17.22#ibcon#read 6, iclass 20, count 0 2006.257.19:40:17.22#ibcon#end of sib2, iclass 20, count 0 2006.257.19:40:17.22#ibcon#*after write, iclass 20, count 0 2006.257.19:40:17.22#ibcon#*before return 0, iclass 20, count 0 2006.257.19:40:17.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:17.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:17.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:40:17.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:40:17.22$vck44/va=3,8 2006.257.19:40:17.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.19:40:17.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.19:40:17.22#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:17.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:17.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:17.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:17.28#ibcon#enter wrdev, iclass 22, count 2 2006.257.19:40:17.28#ibcon#first serial, iclass 22, count 2 2006.257.19:40:17.28#ibcon#enter sib2, iclass 22, count 2 2006.257.19:40:17.28#ibcon#flushed, iclass 22, count 2 2006.257.19:40:17.28#ibcon#about to write, iclass 22, count 2 2006.257.19:40:17.28#ibcon#wrote, iclass 22, count 2 2006.257.19:40:17.28#ibcon#about to read 3, iclass 22, count 2 2006.257.19:40:17.30#ibcon#read 3, iclass 22, count 2 2006.257.19:40:17.30#ibcon#about to read 4, iclass 22, count 2 2006.257.19:40:17.30#ibcon#read 4, iclass 22, count 2 2006.257.19:40:17.30#ibcon#about to read 5, iclass 22, count 2 2006.257.19:40:17.30#ibcon#read 5, iclass 22, count 2 2006.257.19:40:17.30#ibcon#about to read 6, iclass 22, count 2 2006.257.19:40:17.30#ibcon#read 6, iclass 22, count 2 2006.257.19:40:17.30#ibcon#end of sib2, iclass 22, count 2 2006.257.19:40:17.30#ibcon#*mode == 0, iclass 22, count 2 2006.257.19:40:17.30#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.19:40:17.30#ibcon#[25=AT03-08\r\n] 2006.257.19:40:17.30#ibcon#*before write, iclass 22, count 2 2006.257.19:40:17.30#ibcon#enter sib2, iclass 22, count 2 2006.257.19:40:17.30#ibcon#flushed, iclass 22, count 2 2006.257.19:40:17.30#ibcon#about to write, iclass 22, count 2 2006.257.19:40:17.30#ibcon#wrote, iclass 22, count 2 2006.257.19:40:17.30#ibcon#about to read 3, iclass 22, count 2 2006.257.19:40:17.33#ibcon#read 3, iclass 22, count 2 2006.257.19:40:17.33#ibcon#about to read 4, iclass 22, count 2 2006.257.19:40:17.33#ibcon#read 4, iclass 22, count 2 2006.257.19:40:17.33#ibcon#about to read 5, iclass 22, count 2 2006.257.19:40:17.33#ibcon#read 5, iclass 22, count 2 2006.257.19:40:17.33#ibcon#about to read 6, iclass 22, count 2 2006.257.19:40:17.33#ibcon#read 6, iclass 22, count 2 2006.257.19:40:17.33#ibcon#end of sib2, iclass 22, count 2 2006.257.19:40:17.33#ibcon#*after write, iclass 22, count 2 2006.257.19:40:17.33#ibcon#*before return 0, iclass 22, count 2 2006.257.19:40:17.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:17.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:17.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.19:40:17.33#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:17.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:17.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:17.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:17.45#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:40:17.45#ibcon#first serial, iclass 22, count 0 2006.257.19:40:17.45#ibcon#enter sib2, iclass 22, count 0 2006.257.19:40:17.45#ibcon#flushed, iclass 22, count 0 2006.257.19:40:17.45#ibcon#about to write, iclass 22, count 0 2006.257.19:40:17.45#ibcon#wrote, iclass 22, count 0 2006.257.19:40:17.45#ibcon#about to read 3, iclass 22, count 0 2006.257.19:40:17.47#ibcon#read 3, iclass 22, count 0 2006.257.19:40:17.47#ibcon#about to read 4, iclass 22, count 0 2006.257.19:40:17.47#ibcon#read 4, iclass 22, count 0 2006.257.19:40:17.47#ibcon#about to read 5, iclass 22, count 0 2006.257.19:40:17.47#ibcon#read 5, iclass 22, count 0 2006.257.19:40:17.47#ibcon#about to read 6, iclass 22, count 0 2006.257.19:40:17.47#ibcon#read 6, iclass 22, count 0 2006.257.19:40:17.47#ibcon#end of sib2, iclass 22, count 0 2006.257.19:40:17.47#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:40:17.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:40:17.47#ibcon#[25=USB\r\n] 2006.257.19:40:17.47#ibcon#*before write, iclass 22, count 0 2006.257.19:40:17.47#ibcon#enter sib2, iclass 22, count 0 2006.257.19:40:17.47#ibcon#flushed, iclass 22, count 0 2006.257.19:40:17.47#ibcon#about to write, iclass 22, count 0 2006.257.19:40:17.47#ibcon#wrote, iclass 22, count 0 2006.257.19:40:17.47#ibcon#about to read 3, iclass 22, count 0 2006.257.19:40:17.50#ibcon#read 3, iclass 22, count 0 2006.257.19:40:17.50#ibcon#about to read 4, iclass 22, count 0 2006.257.19:40:17.50#ibcon#read 4, iclass 22, count 0 2006.257.19:40:17.50#ibcon#about to read 5, iclass 22, count 0 2006.257.19:40:17.50#ibcon#read 5, iclass 22, count 0 2006.257.19:40:17.50#ibcon#about to read 6, iclass 22, count 0 2006.257.19:40:17.50#ibcon#read 6, iclass 22, count 0 2006.257.19:40:17.50#ibcon#end of sib2, iclass 22, count 0 2006.257.19:40:17.50#ibcon#*after write, iclass 22, count 0 2006.257.19:40:17.50#ibcon#*before return 0, iclass 22, count 0 2006.257.19:40:17.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:17.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:17.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:40:17.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:40:17.50$vck44/valo=4,624.99 2006.257.19:40:17.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.19:40:17.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.19:40:17.50#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:17.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:17.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:17.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:17.50#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:40:17.50#ibcon#first serial, iclass 24, count 0 2006.257.19:40:17.50#ibcon#enter sib2, iclass 24, count 0 2006.257.19:40:17.50#ibcon#flushed, iclass 24, count 0 2006.257.19:40:17.50#ibcon#about to write, iclass 24, count 0 2006.257.19:40:17.50#ibcon#wrote, iclass 24, count 0 2006.257.19:40:17.50#ibcon#about to read 3, iclass 24, count 0 2006.257.19:40:17.52#ibcon#read 3, iclass 24, count 0 2006.257.19:40:17.52#ibcon#about to read 4, iclass 24, count 0 2006.257.19:40:17.52#ibcon#read 4, iclass 24, count 0 2006.257.19:40:17.52#ibcon#about to read 5, iclass 24, count 0 2006.257.19:40:17.52#ibcon#read 5, iclass 24, count 0 2006.257.19:40:17.52#ibcon#about to read 6, iclass 24, count 0 2006.257.19:40:17.52#ibcon#read 6, iclass 24, count 0 2006.257.19:40:17.52#ibcon#end of sib2, iclass 24, count 0 2006.257.19:40:17.52#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:40:17.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:40:17.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.19:40:17.52#ibcon#*before write, iclass 24, count 0 2006.257.19:40:17.52#ibcon#enter sib2, iclass 24, count 0 2006.257.19:40:17.52#ibcon#flushed, iclass 24, count 0 2006.257.19:40:17.52#ibcon#about to write, iclass 24, count 0 2006.257.19:40:17.52#ibcon#wrote, iclass 24, count 0 2006.257.19:40:17.52#ibcon#about to read 3, iclass 24, count 0 2006.257.19:40:17.56#ibcon#read 3, iclass 24, count 0 2006.257.19:40:17.56#ibcon#about to read 4, iclass 24, count 0 2006.257.19:40:17.56#ibcon#read 4, iclass 24, count 0 2006.257.19:40:17.56#ibcon#about to read 5, iclass 24, count 0 2006.257.19:40:17.56#ibcon#read 5, iclass 24, count 0 2006.257.19:40:17.56#ibcon#about to read 6, iclass 24, count 0 2006.257.19:40:17.56#ibcon#read 6, iclass 24, count 0 2006.257.19:40:17.56#ibcon#end of sib2, iclass 24, count 0 2006.257.19:40:17.56#ibcon#*after write, iclass 24, count 0 2006.257.19:40:17.56#ibcon#*before return 0, iclass 24, count 0 2006.257.19:40:17.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:17.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:17.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:40:17.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:40:17.56$vck44/va=4,7 2006.257.19:40:17.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.19:40:17.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.19:40:17.56#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:17.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:17.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:17.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:17.62#ibcon#enter wrdev, iclass 26, count 2 2006.257.19:40:17.62#ibcon#first serial, iclass 26, count 2 2006.257.19:40:17.62#ibcon#enter sib2, iclass 26, count 2 2006.257.19:40:17.62#ibcon#flushed, iclass 26, count 2 2006.257.19:40:17.62#ibcon#about to write, iclass 26, count 2 2006.257.19:40:17.62#ibcon#wrote, iclass 26, count 2 2006.257.19:40:17.62#ibcon#about to read 3, iclass 26, count 2 2006.257.19:40:17.64#ibcon#read 3, iclass 26, count 2 2006.257.19:40:17.64#ibcon#about to read 4, iclass 26, count 2 2006.257.19:40:17.64#ibcon#read 4, iclass 26, count 2 2006.257.19:40:17.64#ibcon#about to read 5, iclass 26, count 2 2006.257.19:40:17.64#ibcon#read 5, iclass 26, count 2 2006.257.19:40:17.64#ibcon#about to read 6, iclass 26, count 2 2006.257.19:40:17.64#ibcon#read 6, iclass 26, count 2 2006.257.19:40:17.64#ibcon#end of sib2, iclass 26, count 2 2006.257.19:40:17.64#ibcon#*mode == 0, iclass 26, count 2 2006.257.19:40:17.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.19:40:17.64#ibcon#[25=AT04-07\r\n] 2006.257.19:40:17.64#ibcon#*before write, iclass 26, count 2 2006.257.19:40:17.64#ibcon#enter sib2, iclass 26, count 2 2006.257.19:40:17.64#ibcon#flushed, iclass 26, count 2 2006.257.19:40:17.64#ibcon#about to write, iclass 26, count 2 2006.257.19:40:17.64#ibcon#wrote, iclass 26, count 2 2006.257.19:40:17.64#ibcon#about to read 3, iclass 26, count 2 2006.257.19:40:17.67#ibcon#read 3, iclass 26, count 2 2006.257.19:40:17.67#ibcon#about to read 4, iclass 26, count 2 2006.257.19:40:17.67#ibcon#read 4, iclass 26, count 2 2006.257.19:40:17.67#ibcon#about to read 5, iclass 26, count 2 2006.257.19:40:17.67#ibcon#read 5, iclass 26, count 2 2006.257.19:40:17.67#ibcon#about to read 6, iclass 26, count 2 2006.257.19:40:17.67#ibcon#read 6, iclass 26, count 2 2006.257.19:40:17.67#ibcon#end of sib2, iclass 26, count 2 2006.257.19:40:17.67#ibcon#*after write, iclass 26, count 2 2006.257.19:40:17.67#ibcon#*before return 0, iclass 26, count 2 2006.257.19:40:17.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:17.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:17.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.19:40:17.67#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:17.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:17.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:17.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:17.79#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:40:17.79#ibcon#first serial, iclass 26, count 0 2006.257.19:40:17.79#ibcon#enter sib2, iclass 26, count 0 2006.257.19:40:17.79#ibcon#flushed, iclass 26, count 0 2006.257.19:40:17.79#ibcon#about to write, iclass 26, count 0 2006.257.19:40:17.79#ibcon#wrote, iclass 26, count 0 2006.257.19:40:17.79#ibcon#about to read 3, iclass 26, count 0 2006.257.19:40:17.81#ibcon#read 3, iclass 26, count 0 2006.257.19:40:17.81#ibcon#about to read 4, iclass 26, count 0 2006.257.19:40:17.81#ibcon#read 4, iclass 26, count 0 2006.257.19:40:17.81#ibcon#about to read 5, iclass 26, count 0 2006.257.19:40:17.81#ibcon#read 5, iclass 26, count 0 2006.257.19:40:17.81#ibcon#about to read 6, iclass 26, count 0 2006.257.19:40:17.81#ibcon#read 6, iclass 26, count 0 2006.257.19:40:17.81#ibcon#end of sib2, iclass 26, count 0 2006.257.19:40:17.81#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:40:17.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:40:17.81#ibcon#[25=USB\r\n] 2006.257.19:40:17.81#ibcon#*before write, iclass 26, count 0 2006.257.19:40:17.81#ibcon#enter sib2, iclass 26, count 0 2006.257.19:40:17.81#ibcon#flushed, iclass 26, count 0 2006.257.19:40:17.81#ibcon#about to write, iclass 26, count 0 2006.257.19:40:17.81#ibcon#wrote, iclass 26, count 0 2006.257.19:40:17.81#ibcon#about to read 3, iclass 26, count 0 2006.257.19:40:17.84#ibcon#read 3, iclass 26, count 0 2006.257.19:40:17.84#ibcon#about to read 4, iclass 26, count 0 2006.257.19:40:17.84#ibcon#read 4, iclass 26, count 0 2006.257.19:40:17.84#ibcon#about to read 5, iclass 26, count 0 2006.257.19:40:17.84#ibcon#read 5, iclass 26, count 0 2006.257.19:40:17.84#ibcon#about to read 6, iclass 26, count 0 2006.257.19:40:17.84#ibcon#read 6, iclass 26, count 0 2006.257.19:40:17.84#ibcon#end of sib2, iclass 26, count 0 2006.257.19:40:17.84#ibcon#*after write, iclass 26, count 0 2006.257.19:40:17.84#ibcon#*before return 0, iclass 26, count 0 2006.257.19:40:17.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:17.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:17.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:40:17.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:40:17.84$vck44/valo=5,734.99 2006.257.19:40:17.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.19:40:17.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.19:40:17.84#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:17.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:17.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:17.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:17.84#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:40:17.84#ibcon#first serial, iclass 28, count 0 2006.257.19:40:17.84#ibcon#enter sib2, iclass 28, count 0 2006.257.19:40:17.84#ibcon#flushed, iclass 28, count 0 2006.257.19:40:17.84#ibcon#about to write, iclass 28, count 0 2006.257.19:40:17.84#ibcon#wrote, iclass 28, count 0 2006.257.19:40:17.84#ibcon#about to read 3, iclass 28, count 0 2006.257.19:40:17.86#ibcon#read 3, iclass 28, count 0 2006.257.19:40:17.86#ibcon#about to read 4, iclass 28, count 0 2006.257.19:40:17.86#ibcon#read 4, iclass 28, count 0 2006.257.19:40:17.86#ibcon#about to read 5, iclass 28, count 0 2006.257.19:40:17.86#ibcon#read 5, iclass 28, count 0 2006.257.19:40:17.86#ibcon#about to read 6, iclass 28, count 0 2006.257.19:40:17.86#ibcon#read 6, iclass 28, count 0 2006.257.19:40:17.86#ibcon#end of sib2, iclass 28, count 0 2006.257.19:40:17.86#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:40:17.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:40:17.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.19:40:17.86#ibcon#*before write, iclass 28, count 0 2006.257.19:40:17.86#ibcon#enter sib2, iclass 28, count 0 2006.257.19:40:17.86#ibcon#flushed, iclass 28, count 0 2006.257.19:40:17.86#ibcon#about to write, iclass 28, count 0 2006.257.19:40:17.86#ibcon#wrote, iclass 28, count 0 2006.257.19:40:17.86#ibcon#about to read 3, iclass 28, count 0 2006.257.19:40:17.90#ibcon#read 3, iclass 28, count 0 2006.257.19:40:17.90#ibcon#about to read 4, iclass 28, count 0 2006.257.19:40:17.90#ibcon#read 4, iclass 28, count 0 2006.257.19:40:17.90#ibcon#about to read 5, iclass 28, count 0 2006.257.19:40:17.90#ibcon#read 5, iclass 28, count 0 2006.257.19:40:17.90#ibcon#about to read 6, iclass 28, count 0 2006.257.19:40:17.90#ibcon#read 6, iclass 28, count 0 2006.257.19:40:17.90#ibcon#end of sib2, iclass 28, count 0 2006.257.19:40:17.90#ibcon#*after write, iclass 28, count 0 2006.257.19:40:17.90#ibcon#*before return 0, iclass 28, count 0 2006.257.19:40:17.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:17.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:17.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:40:17.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:40:17.90$vck44/va=5,4 2006.257.19:40:17.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.19:40:17.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.19:40:17.90#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:17.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:17.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:17.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:17.96#ibcon#enter wrdev, iclass 30, count 2 2006.257.19:40:17.96#ibcon#first serial, iclass 30, count 2 2006.257.19:40:17.96#ibcon#enter sib2, iclass 30, count 2 2006.257.19:40:17.96#ibcon#flushed, iclass 30, count 2 2006.257.19:40:17.96#ibcon#about to write, iclass 30, count 2 2006.257.19:40:17.96#ibcon#wrote, iclass 30, count 2 2006.257.19:40:17.96#ibcon#about to read 3, iclass 30, count 2 2006.257.19:40:17.98#ibcon#read 3, iclass 30, count 2 2006.257.19:40:17.98#ibcon#about to read 4, iclass 30, count 2 2006.257.19:40:17.98#ibcon#read 4, iclass 30, count 2 2006.257.19:40:17.98#ibcon#about to read 5, iclass 30, count 2 2006.257.19:40:17.98#ibcon#read 5, iclass 30, count 2 2006.257.19:40:17.98#ibcon#about to read 6, iclass 30, count 2 2006.257.19:40:17.98#ibcon#read 6, iclass 30, count 2 2006.257.19:40:17.98#ibcon#end of sib2, iclass 30, count 2 2006.257.19:40:17.98#ibcon#*mode == 0, iclass 30, count 2 2006.257.19:40:17.98#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.19:40:17.98#ibcon#[25=AT05-04\r\n] 2006.257.19:40:17.98#ibcon#*before write, iclass 30, count 2 2006.257.19:40:17.98#ibcon#enter sib2, iclass 30, count 2 2006.257.19:40:17.98#ibcon#flushed, iclass 30, count 2 2006.257.19:40:17.98#ibcon#about to write, iclass 30, count 2 2006.257.19:40:17.98#ibcon#wrote, iclass 30, count 2 2006.257.19:40:17.98#ibcon#about to read 3, iclass 30, count 2 2006.257.19:40:18.01#ibcon#read 3, iclass 30, count 2 2006.257.19:40:18.01#ibcon#about to read 4, iclass 30, count 2 2006.257.19:40:18.01#ibcon#read 4, iclass 30, count 2 2006.257.19:40:18.01#ibcon#about to read 5, iclass 30, count 2 2006.257.19:40:18.01#ibcon#read 5, iclass 30, count 2 2006.257.19:40:18.01#ibcon#about to read 6, iclass 30, count 2 2006.257.19:40:18.01#ibcon#read 6, iclass 30, count 2 2006.257.19:40:18.01#ibcon#end of sib2, iclass 30, count 2 2006.257.19:40:18.01#ibcon#*after write, iclass 30, count 2 2006.257.19:40:18.01#ibcon#*before return 0, iclass 30, count 2 2006.257.19:40:18.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:18.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:18.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.19:40:18.01#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:18.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:18.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:18.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:18.13#ibcon#enter wrdev, iclass 30, count 0 2006.257.19:40:18.13#ibcon#first serial, iclass 30, count 0 2006.257.19:40:18.13#ibcon#enter sib2, iclass 30, count 0 2006.257.19:40:18.13#ibcon#flushed, iclass 30, count 0 2006.257.19:40:18.13#ibcon#about to write, iclass 30, count 0 2006.257.19:40:18.13#ibcon#wrote, iclass 30, count 0 2006.257.19:40:18.13#ibcon#about to read 3, iclass 30, count 0 2006.257.19:40:18.15#ibcon#read 3, iclass 30, count 0 2006.257.19:40:18.15#ibcon#about to read 4, iclass 30, count 0 2006.257.19:40:18.15#ibcon#read 4, iclass 30, count 0 2006.257.19:40:18.15#ibcon#about to read 5, iclass 30, count 0 2006.257.19:40:18.15#ibcon#read 5, iclass 30, count 0 2006.257.19:40:18.15#ibcon#about to read 6, iclass 30, count 0 2006.257.19:40:18.15#ibcon#read 6, iclass 30, count 0 2006.257.19:40:18.15#ibcon#end of sib2, iclass 30, count 0 2006.257.19:40:18.15#ibcon#*mode == 0, iclass 30, count 0 2006.257.19:40:18.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.19:40:18.15#ibcon#[25=USB\r\n] 2006.257.19:40:18.15#ibcon#*before write, iclass 30, count 0 2006.257.19:40:18.15#ibcon#enter sib2, iclass 30, count 0 2006.257.19:40:18.15#ibcon#flushed, iclass 30, count 0 2006.257.19:40:18.15#ibcon#about to write, iclass 30, count 0 2006.257.19:40:18.15#ibcon#wrote, iclass 30, count 0 2006.257.19:40:18.15#ibcon#about to read 3, iclass 30, count 0 2006.257.19:40:18.18#ibcon#read 3, iclass 30, count 0 2006.257.19:40:18.18#ibcon#about to read 4, iclass 30, count 0 2006.257.19:40:18.18#ibcon#read 4, iclass 30, count 0 2006.257.19:40:18.18#ibcon#about to read 5, iclass 30, count 0 2006.257.19:40:18.18#ibcon#read 5, iclass 30, count 0 2006.257.19:40:18.18#ibcon#about to read 6, iclass 30, count 0 2006.257.19:40:18.18#ibcon#read 6, iclass 30, count 0 2006.257.19:40:18.18#ibcon#end of sib2, iclass 30, count 0 2006.257.19:40:18.18#ibcon#*after write, iclass 30, count 0 2006.257.19:40:18.18#ibcon#*before return 0, iclass 30, count 0 2006.257.19:40:18.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:18.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:18.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.19:40:18.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.19:40:18.18$vck44/valo=6,814.99 2006.257.19:40:18.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.19:40:18.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.19:40:18.18#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:18.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:18.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:18.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:18.18#ibcon#enter wrdev, iclass 32, count 0 2006.257.19:40:18.18#ibcon#first serial, iclass 32, count 0 2006.257.19:40:18.18#ibcon#enter sib2, iclass 32, count 0 2006.257.19:40:18.18#ibcon#flushed, iclass 32, count 0 2006.257.19:40:18.18#ibcon#about to write, iclass 32, count 0 2006.257.19:40:18.18#ibcon#wrote, iclass 32, count 0 2006.257.19:40:18.18#ibcon#about to read 3, iclass 32, count 0 2006.257.19:40:18.20#ibcon#read 3, iclass 32, count 0 2006.257.19:40:18.20#ibcon#about to read 4, iclass 32, count 0 2006.257.19:40:18.20#ibcon#read 4, iclass 32, count 0 2006.257.19:40:18.20#ibcon#about to read 5, iclass 32, count 0 2006.257.19:40:18.20#ibcon#read 5, iclass 32, count 0 2006.257.19:40:18.20#ibcon#about to read 6, iclass 32, count 0 2006.257.19:40:18.20#ibcon#read 6, iclass 32, count 0 2006.257.19:40:18.20#ibcon#end of sib2, iclass 32, count 0 2006.257.19:40:18.20#ibcon#*mode == 0, iclass 32, count 0 2006.257.19:40:18.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.19:40:18.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.19:40:18.20#ibcon#*before write, iclass 32, count 0 2006.257.19:40:18.20#ibcon#enter sib2, iclass 32, count 0 2006.257.19:40:18.20#ibcon#flushed, iclass 32, count 0 2006.257.19:40:18.20#ibcon#about to write, iclass 32, count 0 2006.257.19:40:18.20#ibcon#wrote, iclass 32, count 0 2006.257.19:40:18.20#ibcon#about to read 3, iclass 32, count 0 2006.257.19:40:18.24#ibcon#read 3, iclass 32, count 0 2006.257.19:40:18.24#ibcon#about to read 4, iclass 32, count 0 2006.257.19:40:18.24#ibcon#read 4, iclass 32, count 0 2006.257.19:40:18.24#ibcon#about to read 5, iclass 32, count 0 2006.257.19:40:18.24#ibcon#read 5, iclass 32, count 0 2006.257.19:40:18.24#ibcon#about to read 6, iclass 32, count 0 2006.257.19:40:18.24#ibcon#read 6, iclass 32, count 0 2006.257.19:40:18.24#ibcon#end of sib2, iclass 32, count 0 2006.257.19:40:18.24#ibcon#*after write, iclass 32, count 0 2006.257.19:40:18.24#ibcon#*before return 0, iclass 32, count 0 2006.257.19:40:18.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:18.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:18.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.19:40:18.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.19:40:18.24$vck44/va=6,4 2006.257.19:40:18.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.19:40:18.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.19:40:18.24#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:18.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:18.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:18.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:18.30#ibcon#enter wrdev, iclass 34, count 2 2006.257.19:40:18.30#ibcon#first serial, iclass 34, count 2 2006.257.19:40:18.30#ibcon#enter sib2, iclass 34, count 2 2006.257.19:40:18.30#ibcon#flushed, iclass 34, count 2 2006.257.19:40:18.30#ibcon#about to write, iclass 34, count 2 2006.257.19:40:18.30#ibcon#wrote, iclass 34, count 2 2006.257.19:40:18.30#ibcon#about to read 3, iclass 34, count 2 2006.257.19:40:18.32#ibcon#read 3, iclass 34, count 2 2006.257.19:40:18.32#ibcon#about to read 4, iclass 34, count 2 2006.257.19:40:18.32#ibcon#read 4, iclass 34, count 2 2006.257.19:40:18.32#ibcon#about to read 5, iclass 34, count 2 2006.257.19:40:18.32#ibcon#read 5, iclass 34, count 2 2006.257.19:40:18.32#ibcon#about to read 6, iclass 34, count 2 2006.257.19:40:18.32#ibcon#read 6, iclass 34, count 2 2006.257.19:40:18.32#ibcon#end of sib2, iclass 34, count 2 2006.257.19:40:18.32#ibcon#*mode == 0, iclass 34, count 2 2006.257.19:40:18.32#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.19:40:18.32#ibcon#[25=AT06-04\r\n] 2006.257.19:40:18.32#ibcon#*before write, iclass 34, count 2 2006.257.19:40:18.32#ibcon#enter sib2, iclass 34, count 2 2006.257.19:40:18.32#ibcon#flushed, iclass 34, count 2 2006.257.19:40:18.32#ibcon#about to write, iclass 34, count 2 2006.257.19:40:18.32#ibcon#wrote, iclass 34, count 2 2006.257.19:40:18.32#ibcon#about to read 3, iclass 34, count 2 2006.257.19:40:18.35#ibcon#read 3, iclass 34, count 2 2006.257.19:40:18.35#ibcon#about to read 4, iclass 34, count 2 2006.257.19:40:18.35#ibcon#read 4, iclass 34, count 2 2006.257.19:40:18.35#ibcon#about to read 5, iclass 34, count 2 2006.257.19:40:18.35#ibcon#read 5, iclass 34, count 2 2006.257.19:40:18.35#ibcon#about to read 6, iclass 34, count 2 2006.257.19:40:18.35#ibcon#read 6, iclass 34, count 2 2006.257.19:40:18.35#ibcon#end of sib2, iclass 34, count 2 2006.257.19:40:18.35#ibcon#*after write, iclass 34, count 2 2006.257.19:40:18.35#ibcon#*before return 0, iclass 34, count 2 2006.257.19:40:18.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:18.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:18.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.19:40:18.35#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:18.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:18.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:18.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:18.47#ibcon#enter wrdev, iclass 34, count 0 2006.257.19:40:18.47#ibcon#first serial, iclass 34, count 0 2006.257.19:40:18.47#ibcon#enter sib2, iclass 34, count 0 2006.257.19:40:18.47#ibcon#flushed, iclass 34, count 0 2006.257.19:40:18.47#ibcon#about to write, iclass 34, count 0 2006.257.19:40:18.47#ibcon#wrote, iclass 34, count 0 2006.257.19:40:18.47#ibcon#about to read 3, iclass 34, count 0 2006.257.19:40:18.49#ibcon#read 3, iclass 34, count 0 2006.257.19:40:18.49#ibcon#about to read 4, iclass 34, count 0 2006.257.19:40:18.49#ibcon#read 4, iclass 34, count 0 2006.257.19:40:18.49#ibcon#about to read 5, iclass 34, count 0 2006.257.19:40:18.49#ibcon#read 5, iclass 34, count 0 2006.257.19:40:18.49#ibcon#about to read 6, iclass 34, count 0 2006.257.19:40:18.49#ibcon#read 6, iclass 34, count 0 2006.257.19:40:18.49#ibcon#end of sib2, iclass 34, count 0 2006.257.19:40:18.49#ibcon#*mode == 0, iclass 34, count 0 2006.257.19:40:18.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.19:40:18.49#ibcon#[25=USB\r\n] 2006.257.19:40:18.49#ibcon#*before write, iclass 34, count 0 2006.257.19:40:18.49#ibcon#enter sib2, iclass 34, count 0 2006.257.19:40:18.49#ibcon#flushed, iclass 34, count 0 2006.257.19:40:18.49#ibcon#about to write, iclass 34, count 0 2006.257.19:40:18.49#ibcon#wrote, iclass 34, count 0 2006.257.19:40:18.49#ibcon#about to read 3, iclass 34, count 0 2006.257.19:40:18.52#ibcon#read 3, iclass 34, count 0 2006.257.19:40:18.52#ibcon#about to read 4, iclass 34, count 0 2006.257.19:40:18.52#ibcon#read 4, iclass 34, count 0 2006.257.19:40:18.52#ibcon#about to read 5, iclass 34, count 0 2006.257.19:40:18.52#ibcon#read 5, iclass 34, count 0 2006.257.19:40:18.52#ibcon#about to read 6, iclass 34, count 0 2006.257.19:40:18.52#ibcon#read 6, iclass 34, count 0 2006.257.19:40:18.52#ibcon#end of sib2, iclass 34, count 0 2006.257.19:40:18.52#ibcon#*after write, iclass 34, count 0 2006.257.19:40:18.52#ibcon#*before return 0, iclass 34, count 0 2006.257.19:40:18.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:18.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:18.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.19:40:18.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.19:40:18.52$vck44/valo=7,864.99 2006.257.19:40:18.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.19:40:18.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.19:40:18.52#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:18.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:18.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:18.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:18.52#ibcon#enter wrdev, iclass 36, count 0 2006.257.19:40:18.52#ibcon#first serial, iclass 36, count 0 2006.257.19:40:18.52#ibcon#enter sib2, iclass 36, count 0 2006.257.19:40:18.52#ibcon#flushed, iclass 36, count 0 2006.257.19:40:18.52#ibcon#about to write, iclass 36, count 0 2006.257.19:40:18.52#ibcon#wrote, iclass 36, count 0 2006.257.19:40:18.52#ibcon#about to read 3, iclass 36, count 0 2006.257.19:40:18.54#ibcon#read 3, iclass 36, count 0 2006.257.19:40:18.54#ibcon#about to read 4, iclass 36, count 0 2006.257.19:40:18.54#ibcon#read 4, iclass 36, count 0 2006.257.19:40:18.54#ibcon#about to read 5, iclass 36, count 0 2006.257.19:40:18.54#ibcon#read 5, iclass 36, count 0 2006.257.19:40:18.54#ibcon#about to read 6, iclass 36, count 0 2006.257.19:40:18.54#ibcon#read 6, iclass 36, count 0 2006.257.19:40:18.54#ibcon#end of sib2, iclass 36, count 0 2006.257.19:40:18.54#ibcon#*mode == 0, iclass 36, count 0 2006.257.19:40:18.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.19:40:18.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.19:40:18.54#ibcon#*before write, iclass 36, count 0 2006.257.19:40:18.54#ibcon#enter sib2, iclass 36, count 0 2006.257.19:40:18.54#ibcon#flushed, iclass 36, count 0 2006.257.19:40:18.54#ibcon#about to write, iclass 36, count 0 2006.257.19:40:18.54#ibcon#wrote, iclass 36, count 0 2006.257.19:40:18.54#ibcon#about to read 3, iclass 36, count 0 2006.257.19:40:18.58#ibcon#read 3, iclass 36, count 0 2006.257.19:40:18.58#ibcon#about to read 4, iclass 36, count 0 2006.257.19:40:18.58#ibcon#read 4, iclass 36, count 0 2006.257.19:40:18.58#ibcon#about to read 5, iclass 36, count 0 2006.257.19:40:18.58#ibcon#read 5, iclass 36, count 0 2006.257.19:40:18.58#ibcon#about to read 6, iclass 36, count 0 2006.257.19:40:18.58#ibcon#read 6, iclass 36, count 0 2006.257.19:40:18.58#ibcon#end of sib2, iclass 36, count 0 2006.257.19:40:18.58#ibcon#*after write, iclass 36, count 0 2006.257.19:40:18.58#ibcon#*before return 0, iclass 36, count 0 2006.257.19:40:18.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:18.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:18.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.19:40:18.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.19:40:18.58$vck44/va=7,4 2006.257.19:40:18.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.19:40:18.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.19:40:18.58#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:18.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:18.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:18.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:18.64#ibcon#enter wrdev, iclass 38, count 2 2006.257.19:40:18.64#ibcon#first serial, iclass 38, count 2 2006.257.19:40:18.64#ibcon#enter sib2, iclass 38, count 2 2006.257.19:40:18.64#ibcon#flushed, iclass 38, count 2 2006.257.19:40:18.64#ibcon#about to write, iclass 38, count 2 2006.257.19:40:18.64#ibcon#wrote, iclass 38, count 2 2006.257.19:40:18.64#ibcon#about to read 3, iclass 38, count 2 2006.257.19:40:18.66#ibcon#read 3, iclass 38, count 2 2006.257.19:40:18.66#ibcon#about to read 4, iclass 38, count 2 2006.257.19:40:18.66#ibcon#read 4, iclass 38, count 2 2006.257.19:40:18.66#ibcon#about to read 5, iclass 38, count 2 2006.257.19:40:18.66#ibcon#read 5, iclass 38, count 2 2006.257.19:40:18.66#ibcon#about to read 6, iclass 38, count 2 2006.257.19:40:18.66#ibcon#read 6, iclass 38, count 2 2006.257.19:40:18.66#ibcon#end of sib2, iclass 38, count 2 2006.257.19:40:18.66#ibcon#*mode == 0, iclass 38, count 2 2006.257.19:40:18.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.19:40:18.66#ibcon#[25=AT07-04\r\n] 2006.257.19:40:18.66#ibcon#*before write, iclass 38, count 2 2006.257.19:40:18.66#ibcon#enter sib2, iclass 38, count 2 2006.257.19:40:18.66#ibcon#flushed, iclass 38, count 2 2006.257.19:40:18.66#ibcon#about to write, iclass 38, count 2 2006.257.19:40:18.66#ibcon#wrote, iclass 38, count 2 2006.257.19:40:18.66#ibcon#about to read 3, iclass 38, count 2 2006.257.19:40:18.69#ibcon#read 3, iclass 38, count 2 2006.257.19:40:18.69#ibcon#about to read 4, iclass 38, count 2 2006.257.19:40:18.69#ibcon#read 4, iclass 38, count 2 2006.257.19:40:18.69#ibcon#about to read 5, iclass 38, count 2 2006.257.19:40:18.69#ibcon#read 5, iclass 38, count 2 2006.257.19:40:18.69#ibcon#about to read 6, iclass 38, count 2 2006.257.19:40:18.69#ibcon#read 6, iclass 38, count 2 2006.257.19:40:18.69#ibcon#end of sib2, iclass 38, count 2 2006.257.19:40:18.69#ibcon#*after write, iclass 38, count 2 2006.257.19:40:18.69#ibcon#*before return 0, iclass 38, count 2 2006.257.19:40:18.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:18.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:18.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.19:40:18.69#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:18.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:18.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:18.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:18.81#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:40:18.81#ibcon#first serial, iclass 38, count 0 2006.257.19:40:18.81#ibcon#enter sib2, iclass 38, count 0 2006.257.19:40:18.81#ibcon#flushed, iclass 38, count 0 2006.257.19:40:18.81#ibcon#about to write, iclass 38, count 0 2006.257.19:40:18.81#ibcon#wrote, iclass 38, count 0 2006.257.19:40:18.81#ibcon#about to read 3, iclass 38, count 0 2006.257.19:40:18.83#ibcon#read 3, iclass 38, count 0 2006.257.19:40:18.83#ibcon#about to read 4, iclass 38, count 0 2006.257.19:40:18.83#ibcon#read 4, iclass 38, count 0 2006.257.19:40:18.83#ibcon#about to read 5, iclass 38, count 0 2006.257.19:40:18.83#ibcon#read 5, iclass 38, count 0 2006.257.19:40:18.83#ibcon#about to read 6, iclass 38, count 0 2006.257.19:40:18.83#ibcon#read 6, iclass 38, count 0 2006.257.19:40:18.83#ibcon#end of sib2, iclass 38, count 0 2006.257.19:40:18.83#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:40:18.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:40:18.83#ibcon#[25=USB\r\n] 2006.257.19:40:18.83#ibcon#*before write, iclass 38, count 0 2006.257.19:40:18.83#ibcon#enter sib2, iclass 38, count 0 2006.257.19:40:18.83#ibcon#flushed, iclass 38, count 0 2006.257.19:40:18.83#ibcon#about to write, iclass 38, count 0 2006.257.19:40:18.83#ibcon#wrote, iclass 38, count 0 2006.257.19:40:18.83#ibcon#about to read 3, iclass 38, count 0 2006.257.19:40:18.86#ibcon#read 3, iclass 38, count 0 2006.257.19:40:18.86#ibcon#about to read 4, iclass 38, count 0 2006.257.19:40:18.86#ibcon#read 4, iclass 38, count 0 2006.257.19:40:18.86#ibcon#about to read 5, iclass 38, count 0 2006.257.19:40:18.86#ibcon#read 5, iclass 38, count 0 2006.257.19:40:18.86#ibcon#about to read 6, iclass 38, count 0 2006.257.19:40:18.86#ibcon#read 6, iclass 38, count 0 2006.257.19:40:18.86#ibcon#end of sib2, iclass 38, count 0 2006.257.19:40:18.86#ibcon#*after write, iclass 38, count 0 2006.257.19:40:18.86#ibcon#*before return 0, iclass 38, count 0 2006.257.19:40:18.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:18.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:18.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:40:18.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:40:18.86$vck44/valo=8,884.99 2006.257.19:40:18.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.19:40:18.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.19:40:18.86#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:18.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:18.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:18.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:18.86#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:40:18.86#ibcon#first serial, iclass 40, count 0 2006.257.19:40:18.86#ibcon#enter sib2, iclass 40, count 0 2006.257.19:40:18.86#ibcon#flushed, iclass 40, count 0 2006.257.19:40:18.86#ibcon#about to write, iclass 40, count 0 2006.257.19:40:18.86#ibcon#wrote, iclass 40, count 0 2006.257.19:40:18.86#ibcon#about to read 3, iclass 40, count 0 2006.257.19:40:18.88#ibcon#read 3, iclass 40, count 0 2006.257.19:40:18.88#ibcon#about to read 4, iclass 40, count 0 2006.257.19:40:18.88#ibcon#read 4, iclass 40, count 0 2006.257.19:40:18.88#ibcon#about to read 5, iclass 40, count 0 2006.257.19:40:18.88#ibcon#read 5, iclass 40, count 0 2006.257.19:40:18.88#ibcon#about to read 6, iclass 40, count 0 2006.257.19:40:18.88#ibcon#read 6, iclass 40, count 0 2006.257.19:40:18.88#ibcon#end of sib2, iclass 40, count 0 2006.257.19:40:18.88#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:40:18.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:40:18.88#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.19:40:18.88#ibcon#*before write, iclass 40, count 0 2006.257.19:40:18.88#ibcon#enter sib2, iclass 40, count 0 2006.257.19:40:18.88#ibcon#flushed, iclass 40, count 0 2006.257.19:40:18.88#ibcon#about to write, iclass 40, count 0 2006.257.19:40:18.88#ibcon#wrote, iclass 40, count 0 2006.257.19:40:18.88#ibcon#about to read 3, iclass 40, count 0 2006.257.19:40:18.92#ibcon#read 3, iclass 40, count 0 2006.257.19:40:18.92#ibcon#about to read 4, iclass 40, count 0 2006.257.19:40:18.92#ibcon#read 4, iclass 40, count 0 2006.257.19:40:18.92#ibcon#about to read 5, iclass 40, count 0 2006.257.19:40:18.92#ibcon#read 5, iclass 40, count 0 2006.257.19:40:18.92#ibcon#about to read 6, iclass 40, count 0 2006.257.19:40:18.92#ibcon#read 6, iclass 40, count 0 2006.257.19:40:18.92#ibcon#end of sib2, iclass 40, count 0 2006.257.19:40:18.92#ibcon#*after write, iclass 40, count 0 2006.257.19:40:18.92#ibcon#*before return 0, iclass 40, count 0 2006.257.19:40:18.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:18.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:18.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:40:18.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:40:18.92$vck44/va=8,4 2006.257.19:40:18.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.19:40:18.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.19:40:18.92#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:18.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:40:18.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:40:18.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:40:18.98#ibcon#enter wrdev, iclass 4, count 2 2006.257.19:40:18.98#ibcon#first serial, iclass 4, count 2 2006.257.19:40:18.98#ibcon#enter sib2, iclass 4, count 2 2006.257.19:40:18.98#ibcon#flushed, iclass 4, count 2 2006.257.19:40:18.98#ibcon#about to write, iclass 4, count 2 2006.257.19:40:18.98#ibcon#wrote, iclass 4, count 2 2006.257.19:40:18.98#ibcon#about to read 3, iclass 4, count 2 2006.257.19:40:19.00#ibcon#read 3, iclass 4, count 2 2006.257.19:40:19.00#ibcon#about to read 4, iclass 4, count 2 2006.257.19:40:19.00#ibcon#read 4, iclass 4, count 2 2006.257.19:40:19.00#ibcon#about to read 5, iclass 4, count 2 2006.257.19:40:19.00#ibcon#read 5, iclass 4, count 2 2006.257.19:40:19.00#ibcon#about to read 6, iclass 4, count 2 2006.257.19:40:19.00#ibcon#read 6, iclass 4, count 2 2006.257.19:40:19.00#ibcon#end of sib2, iclass 4, count 2 2006.257.19:40:19.00#ibcon#*mode == 0, iclass 4, count 2 2006.257.19:40:19.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.19:40:19.00#ibcon#[25=AT08-04\r\n] 2006.257.19:40:19.00#ibcon#*before write, iclass 4, count 2 2006.257.19:40:19.00#ibcon#enter sib2, iclass 4, count 2 2006.257.19:40:19.00#ibcon#flushed, iclass 4, count 2 2006.257.19:40:19.00#ibcon#about to write, iclass 4, count 2 2006.257.19:40:19.00#ibcon#wrote, iclass 4, count 2 2006.257.19:40:19.00#ibcon#about to read 3, iclass 4, count 2 2006.257.19:40:19.03#ibcon#read 3, iclass 4, count 2 2006.257.19:40:19.03#ibcon#about to read 4, iclass 4, count 2 2006.257.19:40:19.03#ibcon#read 4, iclass 4, count 2 2006.257.19:40:19.03#ibcon#about to read 5, iclass 4, count 2 2006.257.19:40:19.03#ibcon#read 5, iclass 4, count 2 2006.257.19:40:19.03#ibcon#about to read 6, iclass 4, count 2 2006.257.19:40:19.03#ibcon#read 6, iclass 4, count 2 2006.257.19:40:19.03#ibcon#end of sib2, iclass 4, count 2 2006.257.19:40:19.03#ibcon#*after write, iclass 4, count 2 2006.257.19:40:19.03#ibcon#*before return 0, iclass 4, count 2 2006.257.19:40:19.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:40:19.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:40:19.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.19:40:19.03#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:19.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:40:19.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:40:19.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:40:19.15#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:40:19.15#ibcon#first serial, iclass 4, count 0 2006.257.19:40:19.15#ibcon#enter sib2, iclass 4, count 0 2006.257.19:40:19.15#ibcon#flushed, iclass 4, count 0 2006.257.19:40:19.15#ibcon#about to write, iclass 4, count 0 2006.257.19:40:19.15#ibcon#wrote, iclass 4, count 0 2006.257.19:40:19.15#ibcon#about to read 3, iclass 4, count 0 2006.257.19:40:19.17#ibcon#read 3, iclass 4, count 0 2006.257.19:40:19.17#ibcon#about to read 4, iclass 4, count 0 2006.257.19:40:19.17#ibcon#read 4, iclass 4, count 0 2006.257.19:40:19.17#ibcon#about to read 5, iclass 4, count 0 2006.257.19:40:19.17#ibcon#read 5, iclass 4, count 0 2006.257.19:40:19.17#ibcon#about to read 6, iclass 4, count 0 2006.257.19:40:19.17#ibcon#read 6, iclass 4, count 0 2006.257.19:40:19.17#ibcon#end of sib2, iclass 4, count 0 2006.257.19:40:19.17#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:40:19.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:40:19.17#ibcon#[25=USB\r\n] 2006.257.19:40:19.17#ibcon#*before write, iclass 4, count 0 2006.257.19:40:19.17#ibcon#enter sib2, iclass 4, count 0 2006.257.19:40:19.17#ibcon#flushed, iclass 4, count 0 2006.257.19:40:19.17#ibcon#about to write, iclass 4, count 0 2006.257.19:40:19.17#ibcon#wrote, iclass 4, count 0 2006.257.19:40:19.17#ibcon#about to read 3, iclass 4, count 0 2006.257.19:40:19.20#ibcon#read 3, iclass 4, count 0 2006.257.19:40:19.20#ibcon#about to read 4, iclass 4, count 0 2006.257.19:40:19.20#ibcon#read 4, iclass 4, count 0 2006.257.19:40:19.20#ibcon#about to read 5, iclass 4, count 0 2006.257.19:40:19.20#ibcon#read 5, iclass 4, count 0 2006.257.19:40:19.20#ibcon#about to read 6, iclass 4, count 0 2006.257.19:40:19.20#ibcon#read 6, iclass 4, count 0 2006.257.19:40:19.20#ibcon#end of sib2, iclass 4, count 0 2006.257.19:40:19.20#ibcon#*after write, iclass 4, count 0 2006.257.19:40:19.20#ibcon#*before return 0, iclass 4, count 0 2006.257.19:40:19.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:40:19.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:40:19.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:40:19.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:40:19.20$vck44/vblo=1,629.99 2006.257.19:40:19.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.19:40:19.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.19:40:19.20#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:19.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:40:19.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:40:19.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:40:19.20#ibcon#enter wrdev, iclass 6, count 0 2006.257.19:40:19.20#ibcon#first serial, iclass 6, count 0 2006.257.19:40:19.20#ibcon#enter sib2, iclass 6, count 0 2006.257.19:40:19.20#ibcon#flushed, iclass 6, count 0 2006.257.19:40:19.20#ibcon#about to write, iclass 6, count 0 2006.257.19:40:19.20#ibcon#wrote, iclass 6, count 0 2006.257.19:40:19.20#ibcon#about to read 3, iclass 6, count 0 2006.257.19:40:19.22#ibcon#read 3, iclass 6, count 0 2006.257.19:40:19.22#ibcon#about to read 4, iclass 6, count 0 2006.257.19:40:19.22#ibcon#read 4, iclass 6, count 0 2006.257.19:40:19.22#ibcon#about to read 5, iclass 6, count 0 2006.257.19:40:19.22#ibcon#read 5, iclass 6, count 0 2006.257.19:40:19.22#ibcon#about to read 6, iclass 6, count 0 2006.257.19:40:19.22#ibcon#read 6, iclass 6, count 0 2006.257.19:40:19.22#ibcon#end of sib2, iclass 6, count 0 2006.257.19:40:19.22#ibcon#*mode == 0, iclass 6, count 0 2006.257.19:40:19.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.19:40:19.22#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.19:40:19.22#ibcon#*before write, iclass 6, count 0 2006.257.19:40:19.22#ibcon#enter sib2, iclass 6, count 0 2006.257.19:40:19.22#ibcon#flushed, iclass 6, count 0 2006.257.19:40:19.22#ibcon#about to write, iclass 6, count 0 2006.257.19:40:19.22#ibcon#wrote, iclass 6, count 0 2006.257.19:40:19.22#ibcon#about to read 3, iclass 6, count 0 2006.257.19:40:19.26#ibcon#read 3, iclass 6, count 0 2006.257.19:40:19.26#ibcon#about to read 4, iclass 6, count 0 2006.257.19:40:19.26#ibcon#read 4, iclass 6, count 0 2006.257.19:40:19.26#ibcon#about to read 5, iclass 6, count 0 2006.257.19:40:19.26#ibcon#read 5, iclass 6, count 0 2006.257.19:40:19.26#ibcon#about to read 6, iclass 6, count 0 2006.257.19:40:19.26#ibcon#read 6, iclass 6, count 0 2006.257.19:40:19.26#ibcon#end of sib2, iclass 6, count 0 2006.257.19:40:19.26#ibcon#*after write, iclass 6, count 0 2006.257.19:40:19.26#ibcon#*before return 0, iclass 6, count 0 2006.257.19:40:19.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:40:19.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:40:19.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.19:40:19.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.19:40:19.26$vck44/vb=1,4 2006.257.19:40:19.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.19:40:19.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.19:40:19.26#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:19.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:40:19.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:40:19.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:40:19.26#ibcon#enter wrdev, iclass 10, count 2 2006.257.19:40:19.26#ibcon#first serial, iclass 10, count 2 2006.257.19:40:19.26#ibcon#enter sib2, iclass 10, count 2 2006.257.19:40:19.26#ibcon#flushed, iclass 10, count 2 2006.257.19:40:19.26#ibcon#about to write, iclass 10, count 2 2006.257.19:40:19.26#ibcon#wrote, iclass 10, count 2 2006.257.19:40:19.26#ibcon#about to read 3, iclass 10, count 2 2006.257.19:40:19.28#ibcon#read 3, iclass 10, count 2 2006.257.19:40:19.28#ibcon#about to read 4, iclass 10, count 2 2006.257.19:40:19.28#ibcon#read 4, iclass 10, count 2 2006.257.19:40:19.28#ibcon#about to read 5, iclass 10, count 2 2006.257.19:40:19.28#ibcon#read 5, iclass 10, count 2 2006.257.19:40:19.28#ibcon#about to read 6, iclass 10, count 2 2006.257.19:40:19.28#ibcon#read 6, iclass 10, count 2 2006.257.19:40:19.28#ibcon#end of sib2, iclass 10, count 2 2006.257.19:40:19.28#ibcon#*mode == 0, iclass 10, count 2 2006.257.19:40:19.28#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.19:40:19.28#ibcon#[27=AT01-04\r\n] 2006.257.19:40:19.28#ibcon#*before write, iclass 10, count 2 2006.257.19:40:19.28#ibcon#enter sib2, iclass 10, count 2 2006.257.19:40:19.28#ibcon#flushed, iclass 10, count 2 2006.257.19:40:19.28#ibcon#about to write, iclass 10, count 2 2006.257.19:40:19.28#ibcon#wrote, iclass 10, count 2 2006.257.19:40:19.28#ibcon#about to read 3, iclass 10, count 2 2006.257.19:40:19.31#ibcon#read 3, iclass 10, count 2 2006.257.19:40:19.31#ibcon#about to read 4, iclass 10, count 2 2006.257.19:40:19.31#ibcon#read 4, iclass 10, count 2 2006.257.19:40:19.31#ibcon#about to read 5, iclass 10, count 2 2006.257.19:40:19.31#ibcon#read 5, iclass 10, count 2 2006.257.19:40:19.31#ibcon#about to read 6, iclass 10, count 2 2006.257.19:40:19.31#ibcon#read 6, iclass 10, count 2 2006.257.19:40:19.31#ibcon#end of sib2, iclass 10, count 2 2006.257.19:40:19.31#ibcon#*after write, iclass 10, count 2 2006.257.19:40:19.31#ibcon#*before return 0, iclass 10, count 2 2006.257.19:40:19.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:40:19.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:40:19.31#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.19:40:19.31#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:19.31#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:40:19.43#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:40:19.43#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:40:19.43#ibcon#enter wrdev, iclass 10, count 0 2006.257.19:40:19.43#ibcon#first serial, iclass 10, count 0 2006.257.19:40:19.43#ibcon#enter sib2, iclass 10, count 0 2006.257.19:40:19.43#ibcon#flushed, iclass 10, count 0 2006.257.19:40:19.43#ibcon#about to write, iclass 10, count 0 2006.257.19:40:19.43#ibcon#wrote, iclass 10, count 0 2006.257.19:40:19.43#ibcon#about to read 3, iclass 10, count 0 2006.257.19:40:19.45#ibcon#read 3, iclass 10, count 0 2006.257.19:40:19.45#ibcon#about to read 4, iclass 10, count 0 2006.257.19:40:19.45#ibcon#read 4, iclass 10, count 0 2006.257.19:40:19.45#ibcon#about to read 5, iclass 10, count 0 2006.257.19:40:19.45#ibcon#read 5, iclass 10, count 0 2006.257.19:40:19.45#ibcon#about to read 6, iclass 10, count 0 2006.257.19:40:19.45#ibcon#read 6, iclass 10, count 0 2006.257.19:40:19.45#ibcon#end of sib2, iclass 10, count 0 2006.257.19:40:19.45#ibcon#*mode == 0, iclass 10, count 0 2006.257.19:40:19.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.19:40:19.45#ibcon#[27=USB\r\n] 2006.257.19:40:19.45#ibcon#*before write, iclass 10, count 0 2006.257.19:40:19.45#ibcon#enter sib2, iclass 10, count 0 2006.257.19:40:19.45#ibcon#flushed, iclass 10, count 0 2006.257.19:40:19.45#ibcon#about to write, iclass 10, count 0 2006.257.19:40:19.45#ibcon#wrote, iclass 10, count 0 2006.257.19:40:19.45#ibcon#about to read 3, iclass 10, count 0 2006.257.19:40:19.48#ibcon#read 3, iclass 10, count 0 2006.257.19:40:19.48#ibcon#about to read 4, iclass 10, count 0 2006.257.19:40:19.48#ibcon#read 4, iclass 10, count 0 2006.257.19:40:19.48#ibcon#about to read 5, iclass 10, count 0 2006.257.19:40:19.48#ibcon#read 5, iclass 10, count 0 2006.257.19:40:19.48#ibcon#about to read 6, iclass 10, count 0 2006.257.19:40:19.48#ibcon#read 6, iclass 10, count 0 2006.257.19:40:19.48#ibcon#end of sib2, iclass 10, count 0 2006.257.19:40:19.48#ibcon#*after write, iclass 10, count 0 2006.257.19:40:19.48#ibcon#*before return 0, iclass 10, count 0 2006.257.19:40:19.48#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:40:19.48#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:40:19.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.19:40:19.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.19:40:19.48$vck44/vblo=2,634.99 2006.257.19:40:19.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.19:40:19.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.19:40:19.48#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:19.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:19.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:19.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:19.48#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:40:19.48#ibcon#first serial, iclass 12, count 0 2006.257.19:40:19.48#ibcon#enter sib2, iclass 12, count 0 2006.257.19:40:19.48#ibcon#flushed, iclass 12, count 0 2006.257.19:40:19.48#ibcon#about to write, iclass 12, count 0 2006.257.19:40:19.48#ibcon#wrote, iclass 12, count 0 2006.257.19:40:19.48#ibcon#about to read 3, iclass 12, count 0 2006.257.19:40:19.50#ibcon#read 3, iclass 12, count 0 2006.257.19:40:19.50#ibcon#about to read 4, iclass 12, count 0 2006.257.19:40:19.50#ibcon#read 4, iclass 12, count 0 2006.257.19:40:19.50#ibcon#about to read 5, iclass 12, count 0 2006.257.19:40:19.50#ibcon#read 5, iclass 12, count 0 2006.257.19:40:19.50#ibcon#about to read 6, iclass 12, count 0 2006.257.19:40:19.50#ibcon#read 6, iclass 12, count 0 2006.257.19:40:19.50#ibcon#end of sib2, iclass 12, count 0 2006.257.19:40:19.50#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:40:19.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:40:19.50#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.19:40:19.50#ibcon#*before write, iclass 12, count 0 2006.257.19:40:19.50#ibcon#enter sib2, iclass 12, count 0 2006.257.19:40:19.50#ibcon#flushed, iclass 12, count 0 2006.257.19:40:19.50#ibcon#about to write, iclass 12, count 0 2006.257.19:40:19.50#ibcon#wrote, iclass 12, count 0 2006.257.19:40:19.50#ibcon#about to read 3, iclass 12, count 0 2006.257.19:40:19.54#ibcon#read 3, iclass 12, count 0 2006.257.19:40:19.54#ibcon#about to read 4, iclass 12, count 0 2006.257.19:40:19.54#ibcon#read 4, iclass 12, count 0 2006.257.19:40:19.54#ibcon#about to read 5, iclass 12, count 0 2006.257.19:40:19.54#ibcon#read 5, iclass 12, count 0 2006.257.19:40:19.54#ibcon#about to read 6, iclass 12, count 0 2006.257.19:40:19.54#ibcon#read 6, iclass 12, count 0 2006.257.19:40:19.54#ibcon#end of sib2, iclass 12, count 0 2006.257.19:40:19.54#ibcon#*after write, iclass 12, count 0 2006.257.19:40:19.54#ibcon#*before return 0, iclass 12, count 0 2006.257.19:40:19.54#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:19.54#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:40:19.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:40:19.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:40:19.54$vck44/vb=2,5 2006.257.19:40:19.54#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.19:40:19.54#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.19:40:19.54#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:19.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:19.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:19.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:19.60#ibcon#enter wrdev, iclass 14, count 2 2006.257.19:40:19.60#ibcon#first serial, iclass 14, count 2 2006.257.19:40:19.60#ibcon#enter sib2, iclass 14, count 2 2006.257.19:40:19.60#ibcon#flushed, iclass 14, count 2 2006.257.19:40:19.60#ibcon#about to write, iclass 14, count 2 2006.257.19:40:19.60#ibcon#wrote, iclass 14, count 2 2006.257.19:40:19.60#ibcon#about to read 3, iclass 14, count 2 2006.257.19:40:19.62#ibcon#read 3, iclass 14, count 2 2006.257.19:40:19.62#ibcon#about to read 4, iclass 14, count 2 2006.257.19:40:19.62#ibcon#read 4, iclass 14, count 2 2006.257.19:40:19.62#ibcon#about to read 5, iclass 14, count 2 2006.257.19:40:19.62#ibcon#read 5, iclass 14, count 2 2006.257.19:40:19.62#ibcon#about to read 6, iclass 14, count 2 2006.257.19:40:19.62#ibcon#read 6, iclass 14, count 2 2006.257.19:40:19.62#ibcon#end of sib2, iclass 14, count 2 2006.257.19:40:19.62#ibcon#*mode == 0, iclass 14, count 2 2006.257.19:40:19.62#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.19:40:19.62#ibcon#[27=AT02-05\r\n] 2006.257.19:40:19.62#ibcon#*before write, iclass 14, count 2 2006.257.19:40:19.62#ibcon#enter sib2, iclass 14, count 2 2006.257.19:40:19.62#ibcon#flushed, iclass 14, count 2 2006.257.19:40:19.62#ibcon#about to write, iclass 14, count 2 2006.257.19:40:19.62#ibcon#wrote, iclass 14, count 2 2006.257.19:40:19.62#ibcon#about to read 3, iclass 14, count 2 2006.257.19:40:19.65#ibcon#read 3, iclass 14, count 2 2006.257.19:40:19.65#ibcon#about to read 4, iclass 14, count 2 2006.257.19:40:19.65#ibcon#read 4, iclass 14, count 2 2006.257.19:40:19.65#ibcon#about to read 5, iclass 14, count 2 2006.257.19:40:19.65#ibcon#read 5, iclass 14, count 2 2006.257.19:40:19.65#ibcon#about to read 6, iclass 14, count 2 2006.257.19:40:19.65#ibcon#read 6, iclass 14, count 2 2006.257.19:40:19.65#ibcon#end of sib2, iclass 14, count 2 2006.257.19:40:19.65#ibcon#*after write, iclass 14, count 2 2006.257.19:40:19.65#ibcon#*before return 0, iclass 14, count 2 2006.257.19:40:19.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:19.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:40:19.65#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.19:40:19.65#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:19.65#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:19.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:19.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:19.77#ibcon#enter wrdev, iclass 14, count 0 2006.257.19:40:19.77#ibcon#first serial, iclass 14, count 0 2006.257.19:40:19.77#ibcon#enter sib2, iclass 14, count 0 2006.257.19:40:19.77#ibcon#flushed, iclass 14, count 0 2006.257.19:40:19.77#ibcon#about to write, iclass 14, count 0 2006.257.19:40:19.77#ibcon#wrote, iclass 14, count 0 2006.257.19:40:19.77#ibcon#about to read 3, iclass 14, count 0 2006.257.19:40:19.79#ibcon#read 3, iclass 14, count 0 2006.257.19:40:19.79#ibcon#about to read 4, iclass 14, count 0 2006.257.19:40:19.79#ibcon#read 4, iclass 14, count 0 2006.257.19:40:19.79#ibcon#about to read 5, iclass 14, count 0 2006.257.19:40:19.79#ibcon#read 5, iclass 14, count 0 2006.257.19:40:19.79#ibcon#about to read 6, iclass 14, count 0 2006.257.19:40:19.79#ibcon#read 6, iclass 14, count 0 2006.257.19:40:19.79#ibcon#end of sib2, iclass 14, count 0 2006.257.19:40:19.79#ibcon#*mode == 0, iclass 14, count 0 2006.257.19:40:19.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.19:40:19.79#ibcon#[27=USB\r\n] 2006.257.19:40:19.79#ibcon#*before write, iclass 14, count 0 2006.257.19:40:19.79#ibcon#enter sib2, iclass 14, count 0 2006.257.19:40:19.79#ibcon#flushed, iclass 14, count 0 2006.257.19:40:19.79#ibcon#about to write, iclass 14, count 0 2006.257.19:40:19.79#ibcon#wrote, iclass 14, count 0 2006.257.19:40:19.79#ibcon#about to read 3, iclass 14, count 0 2006.257.19:40:19.82#ibcon#read 3, iclass 14, count 0 2006.257.19:40:19.82#ibcon#about to read 4, iclass 14, count 0 2006.257.19:40:19.82#ibcon#read 4, iclass 14, count 0 2006.257.19:40:19.82#ibcon#about to read 5, iclass 14, count 0 2006.257.19:40:19.82#ibcon#read 5, iclass 14, count 0 2006.257.19:40:19.82#ibcon#about to read 6, iclass 14, count 0 2006.257.19:40:19.82#ibcon#read 6, iclass 14, count 0 2006.257.19:40:19.82#ibcon#end of sib2, iclass 14, count 0 2006.257.19:40:19.82#ibcon#*after write, iclass 14, count 0 2006.257.19:40:19.82#ibcon#*before return 0, iclass 14, count 0 2006.257.19:40:19.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:19.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:40:19.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.19:40:19.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.19:40:19.82$vck44/vblo=3,649.99 2006.257.19:40:19.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.19:40:19.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.19:40:19.82#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:19.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:19.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:19.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:19.82#ibcon#enter wrdev, iclass 16, count 0 2006.257.19:40:19.82#ibcon#first serial, iclass 16, count 0 2006.257.19:40:19.82#ibcon#enter sib2, iclass 16, count 0 2006.257.19:40:19.82#ibcon#flushed, iclass 16, count 0 2006.257.19:40:19.82#ibcon#about to write, iclass 16, count 0 2006.257.19:40:19.82#ibcon#wrote, iclass 16, count 0 2006.257.19:40:19.82#ibcon#about to read 3, iclass 16, count 0 2006.257.19:40:19.84#ibcon#read 3, iclass 16, count 0 2006.257.19:40:19.84#ibcon#about to read 4, iclass 16, count 0 2006.257.19:40:19.84#ibcon#read 4, iclass 16, count 0 2006.257.19:40:19.84#ibcon#about to read 5, iclass 16, count 0 2006.257.19:40:19.84#ibcon#read 5, iclass 16, count 0 2006.257.19:40:19.84#ibcon#about to read 6, iclass 16, count 0 2006.257.19:40:19.84#ibcon#read 6, iclass 16, count 0 2006.257.19:40:19.84#ibcon#end of sib2, iclass 16, count 0 2006.257.19:40:19.84#ibcon#*mode == 0, iclass 16, count 0 2006.257.19:40:19.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.19:40:19.84#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.19:40:19.84#ibcon#*before write, iclass 16, count 0 2006.257.19:40:19.84#ibcon#enter sib2, iclass 16, count 0 2006.257.19:40:19.84#ibcon#flushed, iclass 16, count 0 2006.257.19:40:19.84#ibcon#about to write, iclass 16, count 0 2006.257.19:40:19.84#ibcon#wrote, iclass 16, count 0 2006.257.19:40:19.84#ibcon#about to read 3, iclass 16, count 0 2006.257.19:40:19.88#ibcon#read 3, iclass 16, count 0 2006.257.19:40:19.88#ibcon#about to read 4, iclass 16, count 0 2006.257.19:40:19.88#ibcon#read 4, iclass 16, count 0 2006.257.19:40:19.88#ibcon#about to read 5, iclass 16, count 0 2006.257.19:40:19.88#ibcon#read 5, iclass 16, count 0 2006.257.19:40:19.88#ibcon#about to read 6, iclass 16, count 0 2006.257.19:40:19.88#ibcon#read 6, iclass 16, count 0 2006.257.19:40:19.88#ibcon#end of sib2, iclass 16, count 0 2006.257.19:40:19.88#ibcon#*after write, iclass 16, count 0 2006.257.19:40:19.88#ibcon#*before return 0, iclass 16, count 0 2006.257.19:40:19.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:19.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:40:19.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.19:40:19.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.19:40:19.88$vck44/vb=3,4 2006.257.19:40:19.88#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.19:40:19.88#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.19:40:19.88#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:19.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:19.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:19.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:19.94#ibcon#enter wrdev, iclass 18, count 2 2006.257.19:40:19.94#ibcon#first serial, iclass 18, count 2 2006.257.19:40:19.94#ibcon#enter sib2, iclass 18, count 2 2006.257.19:40:19.94#ibcon#flushed, iclass 18, count 2 2006.257.19:40:19.94#ibcon#about to write, iclass 18, count 2 2006.257.19:40:19.94#ibcon#wrote, iclass 18, count 2 2006.257.19:40:19.94#ibcon#about to read 3, iclass 18, count 2 2006.257.19:40:19.96#ibcon#read 3, iclass 18, count 2 2006.257.19:40:19.96#ibcon#about to read 4, iclass 18, count 2 2006.257.19:40:19.96#ibcon#read 4, iclass 18, count 2 2006.257.19:40:19.96#ibcon#about to read 5, iclass 18, count 2 2006.257.19:40:19.96#ibcon#read 5, iclass 18, count 2 2006.257.19:40:19.96#ibcon#about to read 6, iclass 18, count 2 2006.257.19:40:19.96#ibcon#read 6, iclass 18, count 2 2006.257.19:40:19.96#ibcon#end of sib2, iclass 18, count 2 2006.257.19:40:19.96#ibcon#*mode == 0, iclass 18, count 2 2006.257.19:40:19.96#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.19:40:19.96#ibcon#[27=AT03-04\r\n] 2006.257.19:40:19.96#ibcon#*before write, iclass 18, count 2 2006.257.19:40:19.96#ibcon#enter sib2, iclass 18, count 2 2006.257.19:40:19.96#ibcon#flushed, iclass 18, count 2 2006.257.19:40:19.96#ibcon#about to write, iclass 18, count 2 2006.257.19:40:19.96#ibcon#wrote, iclass 18, count 2 2006.257.19:40:19.96#ibcon#about to read 3, iclass 18, count 2 2006.257.19:40:19.99#ibcon#read 3, iclass 18, count 2 2006.257.19:40:19.99#ibcon#about to read 4, iclass 18, count 2 2006.257.19:40:19.99#ibcon#read 4, iclass 18, count 2 2006.257.19:40:19.99#ibcon#about to read 5, iclass 18, count 2 2006.257.19:40:19.99#ibcon#read 5, iclass 18, count 2 2006.257.19:40:19.99#ibcon#about to read 6, iclass 18, count 2 2006.257.19:40:19.99#ibcon#read 6, iclass 18, count 2 2006.257.19:40:19.99#ibcon#end of sib2, iclass 18, count 2 2006.257.19:40:19.99#ibcon#*after write, iclass 18, count 2 2006.257.19:40:19.99#ibcon#*before return 0, iclass 18, count 2 2006.257.19:40:19.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:19.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:40:19.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.19:40:19.99#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:19.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:20.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:20.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:20.11#ibcon#enter wrdev, iclass 18, count 0 2006.257.19:40:20.11#ibcon#first serial, iclass 18, count 0 2006.257.19:40:20.11#ibcon#enter sib2, iclass 18, count 0 2006.257.19:40:20.11#ibcon#flushed, iclass 18, count 0 2006.257.19:40:20.11#ibcon#about to write, iclass 18, count 0 2006.257.19:40:20.11#ibcon#wrote, iclass 18, count 0 2006.257.19:40:20.11#ibcon#about to read 3, iclass 18, count 0 2006.257.19:40:20.13#ibcon#read 3, iclass 18, count 0 2006.257.19:40:20.13#ibcon#about to read 4, iclass 18, count 0 2006.257.19:40:20.13#ibcon#read 4, iclass 18, count 0 2006.257.19:40:20.13#ibcon#about to read 5, iclass 18, count 0 2006.257.19:40:20.13#ibcon#read 5, iclass 18, count 0 2006.257.19:40:20.13#ibcon#about to read 6, iclass 18, count 0 2006.257.19:40:20.13#ibcon#read 6, iclass 18, count 0 2006.257.19:40:20.13#ibcon#end of sib2, iclass 18, count 0 2006.257.19:40:20.13#ibcon#*mode == 0, iclass 18, count 0 2006.257.19:40:20.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.19:40:20.13#ibcon#[27=USB\r\n] 2006.257.19:40:20.13#ibcon#*before write, iclass 18, count 0 2006.257.19:40:20.13#ibcon#enter sib2, iclass 18, count 0 2006.257.19:40:20.13#ibcon#flushed, iclass 18, count 0 2006.257.19:40:20.13#ibcon#about to write, iclass 18, count 0 2006.257.19:40:20.13#ibcon#wrote, iclass 18, count 0 2006.257.19:40:20.13#ibcon#about to read 3, iclass 18, count 0 2006.257.19:40:20.16#ibcon#read 3, iclass 18, count 0 2006.257.19:40:20.16#ibcon#about to read 4, iclass 18, count 0 2006.257.19:40:20.16#ibcon#read 4, iclass 18, count 0 2006.257.19:40:20.16#ibcon#about to read 5, iclass 18, count 0 2006.257.19:40:20.16#ibcon#read 5, iclass 18, count 0 2006.257.19:40:20.16#ibcon#about to read 6, iclass 18, count 0 2006.257.19:40:20.16#ibcon#read 6, iclass 18, count 0 2006.257.19:40:20.16#ibcon#end of sib2, iclass 18, count 0 2006.257.19:40:20.16#ibcon#*after write, iclass 18, count 0 2006.257.19:40:20.16#ibcon#*before return 0, iclass 18, count 0 2006.257.19:40:20.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:20.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:40:20.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.19:40:20.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.19:40:20.16$vck44/vblo=4,679.99 2006.257.19:40:20.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.19:40:20.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.19:40:20.16#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:20.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:20.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:20.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:20.16#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:40:20.16#ibcon#first serial, iclass 20, count 0 2006.257.19:40:20.16#ibcon#enter sib2, iclass 20, count 0 2006.257.19:40:20.16#ibcon#flushed, iclass 20, count 0 2006.257.19:40:20.16#ibcon#about to write, iclass 20, count 0 2006.257.19:40:20.16#ibcon#wrote, iclass 20, count 0 2006.257.19:40:20.16#ibcon#about to read 3, iclass 20, count 0 2006.257.19:40:20.18#ibcon#read 3, iclass 20, count 0 2006.257.19:40:20.18#ibcon#about to read 4, iclass 20, count 0 2006.257.19:40:20.18#ibcon#read 4, iclass 20, count 0 2006.257.19:40:20.18#ibcon#about to read 5, iclass 20, count 0 2006.257.19:40:20.18#ibcon#read 5, iclass 20, count 0 2006.257.19:40:20.18#ibcon#about to read 6, iclass 20, count 0 2006.257.19:40:20.18#ibcon#read 6, iclass 20, count 0 2006.257.19:40:20.18#ibcon#end of sib2, iclass 20, count 0 2006.257.19:40:20.18#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:40:20.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:40:20.18#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.19:40:20.18#ibcon#*before write, iclass 20, count 0 2006.257.19:40:20.18#ibcon#enter sib2, iclass 20, count 0 2006.257.19:40:20.18#ibcon#flushed, iclass 20, count 0 2006.257.19:40:20.18#ibcon#about to write, iclass 20, count 0 2006.257.19:40:20.18#ibcon#wrote, iclass 20, count 0 2006.257.19:40:20.18#ibcon#about to read 3, iclass 20, count 0 2006.257.19:40:20.22#ibcon#read 3, iclass 20, count 0 2006.257.19:40:20.22#ibcon#about to read 4, iclass 20, count 0 2006.257.19:40:20.22#ibcon#read 4, iclass 20, count 0 2006.257.19:40:20.22#ibcon#about to read 5, iclass 20, count 0 2006.257.19:40:20.22#ibcon#read 5, iclass 20, count 0 2006.257.19:40:20.22#ibcon#about to read 6, iclass 20, count 0 2006.257.19:40:20.22#ibcon#read 6, iclass 20, count 0 2006.257.19:40:20.22#ibcon#end of sib2, iclass 20, count 0 2006.257.19:40:20.22#ibcon#*after write, iclass 20, count 0 2006.257.19:40:20.22#ibcon#*before return 0, iclass 20, count 0 2006.257.19:40:20.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:20.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:40:20.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:40:20.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:40:20.22$vck44/vb=4,5 2006.257.19:40:20.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.19:40:20.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.19:40:20.22#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:20.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:20.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:20.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:20.28#ibcon#enter wrdev, iclass 22, count 2 2006.257.19:40:20.28#ibcon#first serial, iclass 22, count 2 2006.257.19:40:20.28#ibcon#enter sib2, iclass 22, count 2 2006.257.19:40:20.28#ibcon#flushed, iclass 22, count 2 2006.257.19:40:20.28#ibcon#about to write, iclass 22, count 2 2006.257.19:40:20.28#ibcon#wrote, iclass 22, count 2 2006.257.19:40:20.28#ibcon#about to read 3, iclass 22, count 2 2006.257.19:40:20.30#ibcon#read 3, iclass 22, count 2 2006.257.19:40:20.30#ibcon#about to read 4, iclass 22, count 2 2006.257.19:40:20.30#ibcon#read 4, iclass 22, count 2 2006.257.19:40:20.30#ibcon#about to read 5, iclass 22, count 2 2006.257.19:40:20.30#ibcon#read 5, iclass 22, count 2 2006.257.19:40:20.30#ibcon#about to read 6, iclass 22, count 2 2006.257.19:40:20.30#ibcon#read 6, iclass 22, count 2 2006.257.19:40:20.30#ibcon#end of sib2, iclass 22, count 2 2006.257.19:40:20.30#ibcon#*mode == 0, iclass 22, count 2 2006.257.19:40:20.30#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.19:40:20.30#ibcon#[27=AT04-05\r\n] 2006.257.19:40:20.30#ibcon#*before write, iclass 22, count 2 2006.257.19:40:20.30#ibcon#enter sib2, iclass 22, count 2 2006.257.19:40:20.30#ibcon#flushed, iclass 22, count 2 2006.257.19:40:20.30#ibcon#about to write, iclass 22, count 2 2006.257.19:40:20.30#ibcon#wrote, iclass 22, count 2 2006.257.19:40:20.30#ibcon#about to read 3, iclass 22, count 2 2006.257.19:40:20.33#ibcon#read 3, iclass 22, count 2 2006.257.19:40:20.33#ibcon#about to read 4, iclass 22, count 2 2006.257.19:40:20.33#ibcon#read 4, iclass 22, count 2 2006.257.19:40:20.33#ibcon#about to read 5, iclass 22, count 2 2006.257.19:40:20.33#ibcon#read 5, iclass 22, count 2 2006.257.19:40:20.33#ibcon#about to read 6, iclass 22, count 2 2006.257.19:40:20.33#ibcon#read 6, iclass 22, count 2 2006.257.19:40:20.33#ibcon#end of sib2, iclass 22, count 2 2006.257.19:40:20.33#ibcon#*after write, iclass 22, count 2 2006.257.19:40:20.33#ibcon#*before return 0, iclass 22, count 2 2006.257.19:40:20.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:20.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:40:20.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.19:40:20.33#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:20.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:20.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:20.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:20.45#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:40:20.45#ibcon#first serial, iclass 22, count 0 2006.257.19:40:20.45#ibcon#enter sib2, iclass 22, count 0 2006.257.19:40:20.45#ibcon#flushed, iclass 22, count 0 2006.257.19:40:20.45#ibcon#about to write, iclass 22, count 0 2006.257.19:40:20.45#ibcon#wrote, iclass 22, count 0 2006.257.19:40:20.45#ibcon#about to read 3, iclass 22, count 0 2006.257.19:40:20.47#ibcon#read 3, iclass 22, count 0 2006.257.19:40:20.47#ibcon#about to read 4, iclass 22, count 0 2006.257.19:40:20.47#ibcon#read 4, iclass 22, count 0 2006.257.19:40:20.47#ibcon#about to read 5, iclass 22, count 0 2006.257.19:40:20.47#ibcon#read 5, iclass 22, count 0 2006.257.19:40:20.47#ibcon#about to read 6, iclass 22, count 0 2006.257.19:40:20.47#ibcon#read 6, iclass 22, count 0 2006.257.19:40:20.47#ibcon#end of sib2, iclass 22, count 0 2006.257.19:40:20.47#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:40:20.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:40:20.47#ibcon#[27=USB\r\n] 2006.257.19:40:20.47#ibcon#*before write, iclass 22, count 0 2006.257.19:40:20.47#ibcon#enter sib2, iclass 22, count 0 2006.257.19:40:20.47#ibcon#flushed, iclass 22, count 0 2006.257.19:40:20.47#ibcon#about to write, iclass 22, count 0 2006.257.19:40:20.47#ibcon#wrote, iclass 22, count 0 2006.257.19:40:20.47#ibcon#about to read 3, iclass 22, count 0 2006.257.19:40:20.50#ibcon#read 3, iclass 22, count 0 2006.257.19:40:20.50#ibcon#about to read 4, iclass 22, count 0 2006.257.19:40:20.50#ibcon#read 4, iclass 22, count 0 2006.257.19:40:20.50#ibcon#about to read 5, iclass 22, count 0 2006.257.19:40:20.50#ibcon#read 5, iclass 22, count 0 2006.257.19:40:20.50#ibcon#about to read 6, iclass 22, count 0 2006.257.19:40:20.50#ibcon#read 6, iclass 22, count 0 2006.257.19:40:20.50#ibcon#end of sib2, iclass 22, count 0 2006.257.19:40:20.50#ibcon#*after write, iclass 22, count 0 2006.257.19:40:20.50#ibcon#*before return 0, iclass 22, count 0 2006.257.19:40:20.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:20.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:40:20.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:40:20.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:40:20.50$vck44/vblo=5,709.99 2006.257.19:40:20.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.19:40:20.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.19:40:20.50#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:20.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:20.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:20.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:20.50#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:40:20.50#ibcon#first serial, iclass 24, count 0 2006.257.19:40:20.50#ibcon#enter sib2, iclass 24, count 0 2006.257.19:40:20.50#ibcon#flushed, iclass 24, count 0 2006.257.19:40:20.50#ibcon#about to write, iclass 24, count 0 2006.257.19:40:20.50#ibcon#wrote, iclass 24, count 0 2006.257.19:40:20.50#ibcon#about to read 3, iclass 24, count 0 2006.257.19:40:20.52#ibcon#read 3, iclass 24, count 0 2006.257.19:40:20.52#ibcon#about to read 4, iclass 24, count 0 2006.257.19:40:20.52#ibcon#read 4, iclass 24, count 0 2006.257.19:40:20.52#ibcon#about to read 5, iclass 24, count 0 2006.257.19:40:20.52#ibcon#read 5, iclass 24, count 0 2006.257.19:40:20.52#ibcon#about to read 6, iclass 24, count 0 2006.257.19:40:20.52#ibcon#read 6, iclass 24, count 0 2006.257.19:40:20.52#ibcon#end of sib2, iclass 24, count 0 2006.257.19:40:20.52#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:40:20.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:40:20.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.19:40:20.52#ibcon#*before write, iclass 24, count 0 2006.257.19:40:20.52#ibcon#enter sib2, iclass 24, count 0 2006.257.19:40:20.52#ibcon#flushed, iclass 24, count 0 2006.257.19:40:20.52#ibcon#about to write, iclass 24, count 0 2006.257.19:40:20.52#ibcon#wrote, iclass 24, count 0 2006.257.19:40:20.52#ibcon#about to read 3, iclass 24, count 0 2006.257.19:40:20.56#ibcon#read 3, iclass 24, count 0 2006.257.19:40:20.56#ibcon#about to read 4, iclass 24, count 0 2006.257.19:40:20.56#ibcon#read 4, iclass 24, count 0 2006.257.19:40:20.56#ibcon#about to read 5, iclass 24, count 0 2006.257.19:40:20.56#ibcon#read 5, iclass 24, count 0 2006.257.19:40:20.56#ibcon#about to read 6, iclass 24, count 0 2006.257.19:40:20.56#ibcon#read 6, iclass 24, count 0 2006.257.19:40:20.56#ibcon#end of sib2, iclass 24, count 0 2006.257.19:40:20.56#ibcon#*after write, iclass 24, count 0 2006.257.19:40:20.56#ibcon#*before return 0, iclass 24, count 0 2006.257.19:40:20.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:20.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:40:20.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:40:20.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:40:20.56$vck44/vb=5,4 2006.257.19:40:20.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.19:40:20.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.19:40:20.56#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:20.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:20.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:20.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:20.62#ibcon#enter wrdev, iclass 26, count 2 2006.257.19:40:20.62#ibcon#first serial, iclass 26, count 2 2006.257.19:40:20.62#ibcon#enter sib2, iclass 26, count 2 2006.257.19:40:20.62#ibcon#flushed, iclass 26, count 2 2006.257.19:40:20.62#ibcon#about to write, iclass 26, count 2 2006.257.19:40:20.62#ibcon#wrote, iclass 26, count 2 2006.257.19:40:20.62#ibcon#about to read 3, iclass 26, count 2 2006.257.19:40:20.64#ibcon#read 3, iclass 26, count 2 2006.257.19:40:20.64#ibcon#about to read 4, iclass 26, count 2 2006.257.19:40:20.64#ibcon#read 4, iclass 26, count 2 2006.257.19:40:20.64#ibcon#about to read 5, iclass 26, count 2 2006.257.19:40:20.64#ibcon#read 5, iclass 26, count 2 2006.257.19:40:20.64#ibcon#about to read 6, iclass 26, count 2 2006.257.19:40:20.64#ibcon#read 6, iclass 26, count 2 2006.257.19:40:20.64#ibcon#end of sib2, iclass 26, count 2 2006.257.19:40:20.64#ibcon#*mode == 0, iclass 26, count 2 2006.257.19:40:20.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.19:40:20.64#ibcon#[27=AT05-04\r\n] 2006.257.19:40:20.64#ibcon#*before write, iclass 26, count 2 2006.257.19:40:20.64#ibcon#enter sib2, iclass 26, count 2 2006.257.19:40:20.64#ibcon#flushed, iclass 26, count 2 2006.257.19:40:20.64#ibcon#about to write, iclass 26, count 2 2006.257.19:40:20.64#ibcon#wrote, iclass 26, count 2 2006.257.19:40:20.64#ibcon#about to read 3, iclass 26, count 2 2006.257.19:40:20.67#ibcon#read 3, iclass 26, count 2 2006.257.19:40:20.67#ibcon#about to read 4, iclass 26, count 2 2006.257.19:40:20.67#ibcon#read 4, iclass 26, count 2 2006.257.19:40:20.67#ibcon#about to read 5, iclass 26, count 2 2006.257.19:40:20.67#ibcon#read 5, iclass 26, count 2 2006.257.19:40:20.67#ibcon#about to read 6, iclass 26, count 2 2006.257.19:40:20.67#ibcon#read 6, iclass 26, count 2 2006.257.19:40:20.67#ibcon#end of sib2, iclass 26, count 2 2006.257.19:40:20.67#ibcon#*after write, iclass 26, count 2 2006.257.19:40:20.67#ibcon#*before return 0, iclass 26, count 2 2006.257.19:40:20.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:20.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:40:20.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.19:40:20.67#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:20.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:20.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:20.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:20.79#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:40:20.79#ibcon#first serial, iclass 26, count 0 2006.257.19:40:20.79#ibcon#enter sib2, iclass 26, count 0 2006.257.19:40:20.79#ibcon#flushed, iclass 26, count 0 2006.257.19:40:20.79#ibcon#about to write, iclass 26, count 0 2006.257.19:40:20.79#ibcon#wrote, iclass 26, count 0 2006.257.19:40:20.79#ibcon#about to read 3, iclass 26, count 0 2006.257.19:40:20.81#ibcon#read 3, iclass 26, count 0 2006.257.19:40:20.81#ibcon#about to read 4, iclass 26, count 0 2006.257.19:40:20.81#ibcon#read 4, iclass 26, count 0 2006.257.19:40:20.81#ibcon#about to read 5, iclass 26, count 0 2006.257.19:40:20.81#ibcon#read 5, iclass 26, count 0 2006.257.19:40:20.81#ibcon#about to read 6, iclass 26, count 0 2006.257.19:40:20.81#ibcon#read 6, iclass 26, count 0 2006.257.19:40:20.81#ibcon#end of sib2, iclass 26, count 0 2006.257.19:40:20.81#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:40:20.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:40:20.81#ibcon#[27=USB\r\n] 2006.257.19:40:20.81#ibcon#*before write, iclass 26, count 0 2006.257.19:40:20.81#ibcon#enter sib2, iclass 26, count 0 2006.257.19:40:20.81#ibcon#flushed, iclass 26, count 0 2006.257.19:40:20.81#ibcon#about to write, iclass 26, count 0 2006.257.19:40:20.81#ibcon#wrote, iclass 26, count 0 2006.257.19:40:20.81#ibcon#about to read 3, iclass 26, count 0 2006.257.19:40:20.84#ibcon#read 3, iclass 26, count 0 2006.257.19:40:20.84#ibcon#about to read 4, iclass 26, count 0 2006.257.19:40:20.84#ibcon#read 4, iclass 26, count 0 2006.257.19:40:20.84#ibcon#about to read 5, iclass 26, count 0 2006.257.19:40:20.84#ibcon#read 5, iclass 26, count 0 2006.257.19:40:20.84#ibcon#about to read 6, iclass 26, count 0 2006.257.19:40:20.84#ibcon#read 6, iclass 26, count 0 2006.257.19:40:20.84#ibcon#end of sib2, iclass 26, count 0 2006.257.19:40:20.84#ibcon#*after write, iclass 26, count 0 2006.257.19:40:20.84#ibcon#*before return 0, iclass 26, count 0 2006.257.19:40:20.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:20.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:40:20.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:40:20.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:40:20.84$vck44/vblo=6,719.99 2006.257.19:40:20.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.19:40:20.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.19:40:20.84#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:20.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:20.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:20.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:20.84#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:40:20.84#ibcon#first serial, iclass 28, count 0 2006.257.19:40:20.84#ibcon#enter sib2, iclass 28, count 0 2006.257.19:40:20.84#ibcon#flushed, iclass 28, count 0 2006.257.19:40:20.84#ibcon#about to write, iclass 28, count 0 2006.257.19:40:20.84#ibcon#wrote, iclass 28, count 0 2006.257.19:40:20.84#ibcon#about to read 3, iclass 28, count 0 2006.257.19:40:20.86#ibcon#read 3, iclass 28, count 0 2006.257.19:40:20.86#ibcon#about to read 4, iclass 28, count 0 2006.257.19:40:20.86#ibcon#read 4, iclass 28, count 0 2006.257.19:40:20.86#ibcon#about to read 5, iclass 28, count 0 2006.257.19:40:20.86#ibcon#read 5, iclass 28, count 0 2006.257.19:40:20.86#ibcon#about to read 6, iclass 28, count 0 2006.257.19:40:20.86#ibcon#read 6, iclass 28, count 0 2006.257.19:40:20.86#ibcon#end of sib2, iclass 28, count 0 2006.257.19:40:20.86#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:40:20.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:40:20.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.19:40:20.86#ibcon#*before write, iclass 28, count 0 2006.257.19:40:20.86#ibcon#enter sib2, iclass 28, count 0 2006.257.19:40:20.86#ibcon#flushed, iclass 28, count 0 2006.257.19:40:20.86#ibcon#about to write, iclass 28, count 0 2006.257.19:40:20.86#ibcon#wrote, iclass 28, count 0 2006.257.19:40:20.86#ibcon#about to read 3, iclass 28, count 0 2006.257.19:40:20.90#ibcon#read 3, iclass 28, count 0 2006.257.19:40:20.90#ibcon#about to read 4, iclass 28, count 0 2006.257.19:40:20.90#ibcon#read 4, iclass 28, count 0 2006.257.19:40:20.90#ibcon#about to read 5, iclass 28, count 0 2006.257.19:40:20.90#ibcon#read 5, iclass 28, count 0 2006.257.19:40:20.90#ibcon#about to read 6, iclass 28, count 0 2006.257.19:40:20.90#ibcon#read 6, iclass 28, count 0 2006.257.19:40:20.90#ibcon#end of sib2, iclass 28, count 0 2006.257.19:40:20.90#ibcon#*after write, iclass 28, count 0 2006.257.19:40:20.90#ibcon#*before return 0, iclass 28, count 0 2006.257.19:40:20.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:20.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:40:20.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:40:20.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:40:20.90$vck44/vb=6,4 2006.257.19:40:20.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.19:40:20.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.19:40:20.90#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:20.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:20.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:20.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:20.96#ibcon#enter wrdev, iclass 30, count 2 2006.257.19:40:20.96#ibcon#first serial, iclass 30, count 2 2006.257.19:40:20.96#ibcon#enter sib2, iclass 30, count 2 2006.257.19:40:20.96#ibcon#flushed, iclass 30, count 2 2006.257.19:40:20.96#ibcon#about to write, iclass 30, count 2 2006.257.19:40:20.96#ibcon#wrote, iclass 30, count 2 2006.257.19:40:20.96#ibcon#about to read 3, iclass 30, count 2 2006.257.19:40:20.98#ibcon#read 3, iclass 30, count 2 2006.257.19:40:20.98#ibcon#about to read 4, iclass 30, count 2 2006.257.19:40:20.98#ibcon#read 4, iclass 30, count 2 2006.257.19:40:20.98#ibcon#about to read 5, iclass 30, count 2 2006.257.19:40:20.98#ibcon#read 5, iclass 30, count 2 2006.257.19:40:20.98#ibcon#about to read 6, iclass 30, count 2 2006.257.19:40:20.98#ibcon#read 6, iclass 30, count 2 2006.257.19:40:20.98#ibcon#end of sib2, iclass 30, count 2 2006.257.19:40:20.98#ibcon#*mode == 0, iclass 30, count 2 2006.257.19:40:20.98#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.19:40:20.98#ibcon#[27=AT06-04\r\n] 2006.257.19:40:20.98#ibcon#*before write, iclass 30, count 2 2006.257.19:40:20.98#ibcon#enter sib2, iclass 30, count 2 2006.257.19:40:20.98#ibcon#flushed, iclass 30, count 2 2006.257.19:40:20.98#ibcon#about to write, iclass 30, count 2 2006.257.19:40:20.98#ibcon#wrote, iclass 30, count 2 2006.257.19:40:20.98#ibcon#about to read 3, iclass 30, count 2 2006.257.19:40:21.01#ibcon#read 3, iclass 30, count 2 2006.257.19:40:21.01#ibcon#about to read 4, iclass 30, count 2 2006.257.19:40:21.01#ibcon#read 4, iclass 30, count 2 2006.257.19:40:21.01#ibcon#about to read 5, iclass 30, count 2 2006.257.19:40:21.01#ibcon#read 5, iclass 30, count 2 2006.257.19:40:21.01#ibcon#about to read 6, iclass 30, count 2 2006.257.19:40:21.01#ibcon#read 6, iclass 30, count 2 2006.257.19:40:21.01#ibcon#end of sib2, iclass 30, count 2 2006.257.19:40:21.01#ibcon#*after write, iclass 30, count 2 2006.257.19:40:21.01#ibcon#*before return 0, iclass 30, count 2 2006.257.19:40:21.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:21.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:40:21.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.19:40:21.01#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:21.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:21.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:21.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:21.13#ibcon#enter wrdev, iclass 30, count 0 2006.257.19:40:21.13#ibcon#first serial, iclass 30, count 0 2006.257.19:40:21.13#ibcon#enter sib2, iclass 30, count 0 2006.257.19:40:21.13#ibcon#flushed, iclass 30, count 0 2006.257.19:40:21.13#ibcon#about to write, iclass 30, count 0 2006.257.19:40:21.13#ibcon#wrote, iclass 30, count 0 2006.257.19:40:21.13#ibcon#about to read 3, iclass 30, count 0 2006.257.19:40:21.15#ibcon#read 3, iclass 30, count 0 2006.257.19:40:21.15#ibcon#about to read 4, iclass 30, count 0 2006.257.19:40:21.15#ibcon#read 4, iclass 30, count 0 2006.257.19:40:21.15#ibcon#about to read 5, iclass 30, count 0 2006.257.19:40:21.15#ibcon#read 5, iclass 30, count 0 2006.257.19:40:21.15#ibcon#about to read 6, iclass 30, count 0 2006.257.19:40:21.15#ibcon#read 6, iclass 30, count 0 2006.257.19:40:21.15#ibcon#end of sib2, iclass 30, count 0 2006.257.19:40:21.15#ibcon#*mode == 0, iclass 30, count 0 2006.257.19:40:21.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.19:40:21.15#ibcon#[27=USB\r\n] 2006.257.19:40:21.15#ibcon#*before write, iclass 30, count 0 2006.257.19:40:21.15#ibcon#enter sib2, iclass 30, count 0 2006.257.19:40:21.15#ibcon#flushed, iclass 30, count 0 2006.257.19:40:21.15#ibcon#about to write, iclass 30, count 0 2006.257.19:40:21.15#ibcon#wrote, iclass 30, count 0 2006.257.19:40:21.15#ibcon#about to read 3, iclass 30, count 0 2006.257.19:40:21.18#ibcon#read 3, iclass 30, count 0 2006.257.19:40:21.18#ibcon#about to read 4, iclass 30, count 0 2006.257.19:40:21.18#ibcon#read 4, iclass 30, count 0 2006.257.19:40:21.18#ibcon#about to read 5, iclass 30, count 0 2006.257.19:40:21.18#ibcon#read 5, iclass 30, count 0 2006.257.19:40:21.18#ibcon#about to read 6, iclass 30, count 0 2006.257.19:40:21.18#ibcon#read 6, iclass 30, count 0 2006.257.19:40:21.18#ibcon#end of sib2, iclass 30, count 0 2006.257.19:40:21.18#ibcon#*after write, iclass 30, count 0 2006.257.19:40:21.18#ibcon#*before return 0, iclass 30, count 0 2006.257.19:40:21.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:21.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:40:21.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.19:40:21.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.19:40:21.18$vck44/vblo=7,734.99 2006.257.19:40:21.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.19:40:21.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.19:40:21.18#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:21.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:21.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:21.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:21.18#ibcon#enter wrdev, iclass 32, count 0 2006.257.19:40:21.18#ibcon#first serial, iclass 32, count 0 2006.257.19:40:21.18#ibcon#enter sib2, iclass 32, count 0 2006.257.19:40:21.18#ibcon#flushed, iclass 32, count 0 2006.257.19:40:21.18#ibcon#about to write, iclass 32, count 0 2006.257.19:40:21.18#ibcon#wrote, iclass 32, count 0 2006.257.19:40:21.18#ibcon#about to read 3, iclass 32, count 0 2006.257.19:40:21.20#ibcon#read 3, iclass 32, count 0 2006.257.19:40:21.20#ibcon#about to read 4, iclass 32, count 0 2006.257.19:40:21.20#ibcon#read 4, iclass 32, count 0 2006.257.19:40:21.20#ibcon#about to read 5, iclass 32, count 0 2006.257.19:40:21.20#ibcon#read 5, iclass 32, count 0 2006.257.19:40:21.20#ibcon#about to read 6, iclass 32, count 0 2006.257.19:40:21.20#ibcon#read 6, iclass 32, count 0 2006.257.19:40:21.20#ibcon#end of sib2, iclass 32, count 0 2006.257.19:40:21.20#ibcon#*mode == 0, iclass 32, count 0 2006.257.19:40:21.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.19:40:21.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.19:40:21.20#ibcon#*before write, iclass 32, count 0 2006.257.19:40:21.20#ibcon#enter sib2, iclass 32, count 0 2006.257.19:40:21.20#ibcon#flushed, iclass 32, count 0 2006.257.19:40:21.20#ibcon#about to write, iclass 32, count 0 2006.257.19:40:21.20#ibcon#wrote, iclass 32, count 0 2006.257.19:40:21.20#ibcon#about to read 3, iclass 32, count 0 2006.257.19:40:21.24#ibcon#read 3, iclass 32, count 0 2006.257.19:40:21.24#ibcon#about to read 4, iclass 32, count 0 2006.257.19:40:21.24#ibcon#read 4, iclass 32, count 0 2006.257.19:40:21.24#ibcon#about to read 5, iclass 32, count 0 2006.257.19:40:21.24#ibcon#read 5, iclass 32, count 0 2006.257.19:40:21.24#ibcon#about to read 6, iclass 32, count 0 2006.257.19:40:21.24#ibcon#read 6, iclass 32, count 0 2006.257.19:40:21.24#ibcon#end of sib2, iclass 32, count 0 2006.257.19:40:21.24#ibcon#*after write, iclass 32, count 0 2006.257.19:40:21.24#ibcon#*before return 0, iclass 32, count 0 2006.257.19:40:21.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:21.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:40:21.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.19:40:21.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.19:40:21.24$vck44/vb=7,4 2006.257.19:40:21.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.19:40:21.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.19:40:21.24#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:21.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:21.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:21.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:21.30#ibcon#enter wrdev, iclass 34, count 2 2006.257.19:40:21.30#ibcon#first serial, iclass 34, count 2 2006.257.19:40:21.30#ibcon#enter sib2, iclass 34, count 2 2006.257.19:40:21.30#ibcon#flushed, iclass 34, count 2 2006.257.19:40:21.30#ibcon#about to write, iclass 34, count 2 2006.257.19:40:21.30#ibcon#wrote, iclass 34, count 2 2006.257.19:40:21.30#ibcon#about to read 3, iclass 34, count 2 2006.257.19:40:21.32#ibcon#read 3, iclass 34, count 2 2006.257.19:40:21.32#ibcon#about to read 4, iclass 34, count 2 2006.257.19:40:21.32#ibcon#read 4, iclass 34, count 2 2006.257.19:40:21.32#ibcon#about to read 5, iclass 34, count 2 2006.257.19:40:21.32#ibcon#read 5, iclass 34, count 2 2006.257.19:40:21.32#ibcon#about to read 6, iclass 34, count 2 2006.257.19:40:21.32#ibcon#read 6, iclass 34, count 2 2006.257.19:40:21.32#ibcon#end of sib2, iclass 34, count 2 2006.257.19:40:21.32#ibcon#*mode == 0, iclass 34, count 2 2006.257.19:40:21.32#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.19:40:21.32#ibcon#[27=AT07-04\r\n] 2006.257.19:40:21.32#ibcon#*before write, iclass 34, count 2 2006.257.19:40:21.32#ibcon#enter sib2, iclass 34, count 2 2006.257.19:40:21.32#ibcon#flushed, iclass 34, count 2 2006.257.19:40:21.32#ibcon#about to write, iclass 34, count 2 2006.257.19:40:21.32#ibcon#wrote, iclass 34, count 2 2006.257.19:40:21.32#ibcon#about to read 3, iclass 34, count 2 2006.257.19:40:21.35#ibcon#read 3, iclass 34, count 2 2006.257.19:40:21.35#ibcon#about to read 4, iclass 34, count 2 2006.257.19:40:21.35#ibcon#read 4, iclass 34, count 2 2006.257.19:40:21.35#ibcon#about to read 5, iclass 34, count 2 2006.257.19:40:21.35#ibcon#read 5, iclass 34, count 2 2006.257.19:40:21.35#ibcon#about to read 6, iclass 34, count 2 2006.257.19:40:21.35#ibcon#read 6, iclass 34, count 2 2006.257.19:40:21.35#ibcon#end of sib2, iclass 34, count 2 2006.257.19:40:21.35#ibcon#*after write, iclass 34, count 2 2006.257.19:40:21.35#ibcon#*before return 0, iclass 34, count 2 2006.257.19:40:21.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:21.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:40:21.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.19:40:21.35#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:21.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:21.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:21.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:21.47#ibcon#enter wrdev, iclass 34, count 0 2006.257.19:40:21.47#ibcon#first serial, iclass 34, count 0 2006.257.19:40:21.47#ibcon#enter sib2, iclass 34, count 0 2006.257.19:40:21.47#ibcon#flushed, iclass 34, count 0 2006.257.19:40:21.47#ibcon#about to write, iclass 34, count 0 2006.257.19:40:21.47#ibcon#wrote, iclass 34, count 0 2006.257.19:40:21.47#ibcon#about to read 3, iclass 34, count 0 2006.257.19:40:21.49#ibcon#read 3, iclass 34, count 0 2006.257.19:40:21.49#ibcon#about to read 4, iclass 34, count 0 2006.257.19:40:21.49#ibcon#read 4, iclass 34, count 0 2006.257.19:40:21.49#ibcon#about to read 5, iclass 34, count 0 2006.257.19:40:21.49#ibcon#read 5, iclass 34, count 0 2006.257.19:40:21.49#ibcon#about to read 6, iclass 34, count 0 2006.257.19:40:21.49#ibcon#read 6, iclass 34, count 0 2006.257.19:40:21.49#ibcon#end of sib2, iclass 34, count 0 2006.257.19:40:21.49#ibcon#*mode == 0, iclass 34, count 0 2006.257.19:40:21.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.19:40:21.49#ibcon#[27=USB\r\n] 2006.257.19:40:21.49#ibcon#*before write, iclass 34, count 0 2006.257.19:40:21.49#ibcon#enter sib2, iclass 34, count 0 2006.257.19:40:21.49#ibcon#flushed, iclass 34, count 0 2006.257.19:40:21.49#ibcon#about to write, iclass 34, count 0 2006.257.19:40:21.49#ibcon#wrote, iclass 34, count 0 2006.257.19:40:21.49#ibcon#about to read 3, iclass 34, count 0 2006.257.19:40:21.52#ibcon#read 3, iclass 34, count 0 2006.257.19:40:21.52#ibcon#about to read 4, iclass 34, count 0 2006.257.19:40:21.52#ibcon#read 4, iclass 34, count 0 2006.257.19:40:21.52#ibcon#about to read 5, iclass 34, count 0 2006.257.19:40:21.52#ibcon#read 5, iclass 34, count 0 2006.257.19:40:21.52#ibcon#about to read 6, iclass 34, count 0 2006.257.19:40:21.52#ibcon#read 6, iclass 34, count 0 2006.257.19:40:21.52#ibcon#end of sib2, iclass 34, count 0 2006.257.19:40:21.52#ibcon#*after write, iclass 34, count 0 2006.257.19:40:21.52#ibcon#*before return 0, iclass 34, count 0 2006.257.19:40:21.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:21.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:40:21.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.19:40:21.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.19:40:21.52$vck44/vblo=8,744.99 2006.257.19:40:21.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.19:40:21.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.19:40:21.52#ibcon#ireg 17 cls_cnt 0 2006.257.19:40:21.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:21.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:21.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:21.52#ibcon#enter wrdev, iclass 36, count 0 2006.257.19:40:21.52#ibcon#first serial, iclass 36, count 0 2006.257.19:40:21.52#ibcon#enter sib2, iclass 36, count 0 2006.257.19:40:21.52#ibcon#flushed, iclass 36, count 0 2006.257.19:40:21.52#ibcon#about to write, iclass 36, count 0 2006.257.19:40:21.52#ibcon#wrote, iclass 36, count 0 2006.257.19:40:21.52#ibcon#about to read 3, iclass 36, count 0 2006.257.19:40:21.54#ibcon#read 3, iclass 36, count 0 2006.257.19:40:21.54#ibcon#about to read 4, iclass 36, count 0 2006.257.19:40:21.54#ibcon#read 4, iclass 36, count 0 2006.257.19:40:21.54#ibcon#about to read 5, iclass 36, count 0 2006.257.19:40:21.54#ibcon#read 5, iclass 36, count 0 2006.257.19:40:21.54#ibcon#about to read 6, iclass 36, count 0 2006.257.19:40:21.54#ibcon#read 6, iclass 36, count 0 2006.257.19:40:21.54#ibcon#end of sib2, iclass 36, count 0 2006.257.19:40:21.54#ibcon#*mode == 0, iclass 36, count 0 2006.257.19:40:21.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.19:40:21.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.19:40:21.54#ibcon#*before write, iclass 36, count 0 2006.257.19:40:21.54#ibcon#enter sib2, iclass 36, count 0 2006.257.19:40:21.54#ibcon#flushed, iclass 36, count 0 2006.257.19:40:21.54#ibcon#about to write, iclass 36, count 0 2006.257.19:40:21.54#ibcon#wrote, iclass 36, count 0 2006.257.19:40:21.54#ibcon#about to read 3, iclass 36, count 0 2006.257.19:40:21.58#ibcon#read 3, iclass 36, count 0 2006.257.19:40:21.58#ibcon#about to read 4, iclass 36, count 0 2006.257.19:40:21.58#ibcon#read 4, iclass 36, count 0 2006.257.19:40:21.58#ibcon#about to read 5, iclass 36, count 0 2006.257.19:40:21.58#ibcon#read 5, iclass 36, count 0 2006.257.19:40:21.58#ibcon#about to read 6, iclass 36, count 0 2006.257.19:40:21.58#ibcon#read 6, iclass 36, count 0 2006.257.19:40:21.58#ibcon#end of sib2, iclass 36, count 0 2006.257.19:40:21.58#ibcon#*after write, iclass 36, count 0 2006.257.19:40:21.58#ibcon#*before return 0, iclass 36, count 0 2006.257.19:40:21.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:21.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:40:21.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.19:40:21.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.19:40:21.58$vck44/vb=8,4 2006.257.19:40:21.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.19:40:21.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.19:40:21.58#ibcon#ireg 11 cls_cnt 2 2006.257.19:40:21.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:21.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:21.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:21.64#ibcon#enter wrdev, iclass 38, count 2 2006.257.19:40:21.64#ibcon#first serial, iclass 38, count 2 2006.257.19:40:21.64#ibcon#enter sib2, iclass 38, count 2 2006.257.19:40:21.64#ibcon#flushed, iclass 38, count 2 2006.257.19:40:21.64#ibcon#about to write, iclass 38, count 2 2006.257.19:40:21.64#ibcon#wrote, iclass 38, count 2 2006.257.19:40:21.64#ibcon#about to read 3, iclass 38, count 2 2006.257.19:40:21.66#ibcon#read 3, iclass 38, count 2 2006.257.19:40:21.66#ibcon#about to read 4, iclass 38, count 2 2006.257.19:40:21.66#ibcon#read 4, iclass 38, count 2 2006.257.19:40:21.66#ibcon#about to read 5, iclass 38, count 2 2006.257.19:40:21.66#ibcon#read 5, iclass 38, count 2 2006.257.19:40:21.66#ibcon#about to read 6, iclass 38, count 2 2006.257.19:40:21.66#ibcon#read 6, iclass 38, count 2 2006.257.19:40:21.66#ibcon#end of sib2, iclass 38, count 2 2006.257.19:40:21.66#ibcon#*mode == 0, iclass 38, count 2 2006.257.19:40:21.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.19:40:21.66#ibcon#[27=AT08-04\r\n] 2006.257.19:40:21.66#ibcon#*before write, iclass 38, count 2 2006.257.19:40:21.66#ibcon#enter sib2, iclass 38, count 2 2006.257.19:40:21.66#ibcon#flushed, iclass 38, count 2 2006.257.19:40:21.66#ibcon#about to write, iclass 38, count 2 2006.257.19:40:21.66#ibcon#wrote, iclass 38, count 2 2006.257.19:40:21.66#ibcon#about to read 3, iclass 38, count 2 2006.257.19:40:21.69#ibcon#read 3, iclass 38, count 2 2006.257.19:40:21.69#ibcon#about to read 4, iclass 38, count 2 2006.257.19:40:21.69#ibcon#read 4, iclass 38, count 2 2006.257.19:40:21.69#ibcon#about to read 5, iclass 38, count 2 2006.257.19:40:21.69#ibcon#read 5, iclass 38, count 2 2006.257.19:40:21.69#ibcon#about to read 6, iclass 38, count 2 2006.257.19:40:21.69#ibcon#read 6, iclass 38, count 2 2006.257.19:40:21.69#ibcon#end of sib2, iclass 38, count 2 2006.257.19:40:21.69#ibcon#*after write, iclass 38, count 2 2006.257.19:40:21.69#ibcon#*before return 0, iclass 38, count 2 2006.257.19:40:21.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:21.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:40:21.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.19:40:21.69#ibcon#ireg 7 cls_cnt 0 2006.257.19:40:21.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:21.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:21.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:21.81#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:40:21.81#ibcon#first serial, iclass 38, count 0 2006.257.19:40:21.81#ibcon#enter sib2, iclass 38, count 0 2006.257.19:40:21.81#ibcon#flushed, iclass 38, count 0 2006.257.19:40:21.81#ibcon#about to write, iclass 38, count 0 2006.257.19:40:21.81#ibcon#wrote, iclass 38, count 0 2006.257.19:40:21.81#ibcon#about to read 3, iclass 38, count 0 2006.257.19:40:21.83#ibcon#read 3, iclass 38, count 0 2006.257.19:40:21.83#ibcon#about to read 4, iclass 38, count 0 2006.257.19:40:21.83#ibcon#read 4, iclass 38, count 0 2006.257.19:40:21.83#ibcon#about to read 5, iclass 38, count 0 2006.257.19:40:21.83#ibcon#read 5, iclass 38, count 0 2006.257.19:40:21.83#ibcon#about to read 6, iclass 38, count 0 2006.257.19:40:21.83#ibcon#read 6, iclass 38, count 0 2006.257.19:40:21.83#ibcon#end of sib2, iclass 38, count 0 2006.257.19:40:21.83#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:40:21.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:40:21.83#ibcon#[27=USB\r\n] 2006.257.19:40:21.83#ibcon#*before write, iclass 38, count 0 2006.257.19:40:21.83#ibcon#enter sib2, iclass 38, count 0 2006.257.19:40:21.83#ibcon#flushed, iclass 38, count 0 2006.257.19:40:21.83#ibcon#about to write, iclass 38, count 0 2006.257.19:40:21.83#ibcon#wrote, iclass 38, count 0 2006.257.19:40:21.83#ibcon#about to read 3, iclass 38, count 0 2006.257.19:40:21.86#ibcon#read 3, iclass 38, count 0 2006.257.19:40:21.86#ibcon#about to read 4, iclass 38, count 0 2006.257.19:40:21.86#ibcon#read 4, iclass 38, count 0 2006.257.19:40:21.86#ibcon#about to read 5, iclass 38, count 0 2006.257.19:40:21.86#ibcon#read 5, iclass 38, count 0 2006.257.19:40:21.86#ibcon#about to read 6, iclass 38, count 0 2006.257.19:40:21.86#ibcon#read 6, iclass 38, count 0 2006.257.19:40:21.86#ibcon#end of sib2, iclass 38, count 0 2006.257.19:40:21.86#ibcon#*after write, iclass 38, count 0 2006.257.19:40:21.86#ibcon#*before return 0, iclass 38, count 0 2006.257.19:40:21.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:21.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:40:21.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:40:21.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:40:21.86$vck44/vabw=wide 2006.257.19:40:21.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.19:40:21.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.19:40:21.86#ibcon#ireg 8 cls_cnt 0 2006.257.19:40:21.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:21.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:21.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:21.86#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:40:21.86#ibcon#first serial, iclass 40, count 0 2006.257.19:40:21.86#ibcon#enter sib2, iclass 40, count 0 2006.257.19:40:21.86#ibcon#flushed, iclass 40, count 0 2006.257.19:40:21.86#ibcon#about to write, iclass 40, count 0 2006.257.19:40:21.86#ibcon#wrote, iclass 40, count 0 2006.257.19:40:21.86#ibcon#about to read 3, iclass 40, count 0 2006.257.19:40:21.88#ibcon#read 3, iclass 40, count 0 2006.257.19:40:21.88#ibcon#about to read 4, iclass 40, count 0 2006.257.19:40:21.88#ibcon#read 4, iclass 40, count 0 2006.257.19:40:21.88#ibcon#about to read 5, iclass 40, count 0 2006.257.19:40:21.88#ibcon#read 5, iclass 40, count 0 2006.257.19:40:21.88#ibcon#about to read 6, iclass 40, count 0 2006.257.19:40:21.88#ibcon#read 6, iclass 40, count 0 2006.257.19:40:21.88#ibcon#end of sib2, iclass 40, count 0 2006.257.19:40:21.88#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:40:21.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:40:21.88#ibcon#[25=BW32\r\n] 2006.257.19:40:21.88#ibcon#*before write, iclass 40, count 0 2006.257.19:40:21.88#ibcon#enter sib2, iclass 40, count 0 2006.257.19:40:21.88#ibcon#flushed, iclass 40, count 0 2006.257.19:40:21.88#ibcon#about to write, iclass 40, count 0 2006.257.19:40:21.88#ibcon#wrote, iclass 40, count 0 2006.257.19:40:21.88#ibcon#about to read 3, iclass 40, count 0 2006.257.19:40:21.91#ibcon#read 3, iclass 40, count 0 2006.257.19:40:21.91#ibcon#about to read 4, iclass 40, count 0 2006.257.19:40:21.91#ibcon#read 4, iclass 40, count 0 2006.257.19:40:21.91#ibcon#about to read 5, iclass 40, count 0 2006.257.19:40:21.91#ibcon#read 5, iclass 40, count 0 2006.257.19:40:21.91#ibcon#about to read 6, iclass 40, count 0 2006.257.19:40:21.91#ibcon#read 6, iclass 40, count 0 2006.257.19:40:21.91#ibcon#end of sib2, iclass 40, count 0 2006.257.19:40:21.91#ibcon#*after write, iclass 40, count 0 2006.257.19:40:21.91#ibcon#*before return 0, iclass 40, count 0 2006.257.19:40:21.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:21.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:40:21.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:40:21.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:40:21.91$vck44/vbbw=wide 2006.257.19:40:21.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.19:40:21.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.19:40:21.91#ibcon#ireg 8 cls_cnt 0 2006.257.19:40:21.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:40:21.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:40:21.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:40:21.98#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:40:21.98#ibcon#first serial, iclass 4, count 0 2006.257.19:40:21.98#ibcon#enter sib2, iclass 4, count 0 2006.257.19:40:21.98#ibcon#flushed, iclass 4, count 0 2006.257.19:40:21.98#ibcon#about to write, iclass 4, count 0 2006.257.19:40:21.98#ibcon#wrote, iclass 4, count 0 2006.257.19:40:21.98#ibcon#about to read 3, iclass 4, count 0 2006.257.19:40:22.00#ibcon#read 3, iclass 4, count 0 2006.257.19:40:22.00#ibcon#about to read 4, iclass 4, count 0 2006.257.19:40:22.00#ibcon#read 4, iclass 4, count 0 2006.257.19:40:22.00#ibcon#about to read 5, iclass 4, count 0 2006.257.19:40:22.00#ibcon#read 5, iclass 4, count 0 2006.257.19:40:22.00#ibcon#about to read 6, iclass 4, count 0 2006.257.19:40:22.00#ibcon#read 6, iclass 4, count 0 2006.257.19:40:22.00#ibcon#end of sib2, iclass 4, count 0 2006.257.19:40:22.00#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:40:22.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:40:22.00#ibcon#[27=BW32\r\n] 2006.257.19:40:22.00#ibcon#*before write, iclass 4, count 0 2006.257.19:40:22.00#ibcon#enter sib2, iclass 4, count 0 2006.257.19:40:22.00#ibcon#flushed, iclass 4, count 0 2006.257.19:40:22.00#ibcon#about to write, iclass 4, count 0 2006.257.19:40:22.00#ibcon#wrote, iclass 4, count 0 2006.257.19:40:22.00#ibcon#about to read 3, iclass 4, count 0 2006.257.19:40:22.03#ibcon#read 3, iclass 4, count 0 2006.257.19:40:22.03#ibcon#about to read 4, iclass 4, count 0 2006.257.19:40:22.03#ibcon#read 4, iclass 4, count 0 2006.257.19:40:22.03#ibcon#about to read 5, iclass 4, count 0 2006.257.19:40:22.03#ibcon#read 5, iclass 4, count 0 2006.257.19:40:22.03#ibcon#about to read 6, iclass 4, count 0 2006.257.19:40:22.03#ibcon#read 6, iclass 4, count 0 2006.257.19:40:22.03#ibcon#end of sib2, iclass 4, count 0 2006.257.19:40:22.03#ibcon#*after write, iclass 4, count 0 2006.257.19:40:22.03#ibcon#*before return 0, iclass 4, count 0 2006.257.19:40:22.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:40:22.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:40:22.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:40:22.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:40:22.03$setupk4/ifdk4 2006.257.19:40:22.03$ifdk4/lo= 2006.257.19:40:22.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.19:40:22.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.19:40:22.03$ifdk4/patch= 2006.257.19:40:22.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.19:40:22.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.19:40:22.03$setupk4/!*+20s 2006.257.19:40:25.68#abcon#<5=/14 1.4 4.1 17.52 961014.5\r\n> 2006.257.19:40:25.70#abcon#{5=INTERFACE CLEAR} 2006.257.19:40:25.76#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:40:35.14#trakl#Source acquired 2006.257.19:40:35.85#abcon#<5=/14 1.4 4.1 17.52 961014.5\r\n> 2006.257.19:40:35.87#abcon#{5=INTERFACE CLEAR} 2006.257.19:40:35.93#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:40:36.14#flagr#flagr/antenna,acquired 2006.257.19:40:36.54$setupk4/"tpicd 2006.257.19:40:36.54$setupk4/echo=off 2006.257.19:40:36.54$setupk4/xlog=off 2006.257.19:40:36.54:!2006.257.19:42:44 2006.257.19:42:44.00:preob 2006.257.19:42:44.14/onsource/TRACKING 2006.257.19:42:44.14:!2006.257.19:42:54 2006.257.19:42:54.00:"tape 2006.257.19:42:54.00:"st=record 2006.257.19:42:54.00:data_valid=on 2006.257.19:42:54.00:midob 2006.257.19:42:54.14/onsource/TRACKING 2006.257.19:42:54.14/wx/17.52,1014.5,96 2006.257.19:42:54.36/cable/+6.4856E-03 2006.257.19:42:55.45/va/01,08,usb,yes,35,38 2006.257.19:42:55.45/va/02,07,usb,yes,38,39 2006.257.19:42:55.45/va/03,08,usb,yes,34,36 2006.257.19:42:55.45/va/04,07,usb,yes,39,41 2006.257.19:42:55.45/va/05,04,usb,yes,35,36 2006.257.19:42:55.45/va/06,04,usb,yes,39,39 2006.257.19:42:55.45/va/07,04,usb,yes,40,40 2006.257.19:42:55.45/va/08,04,usb,yes,34,41 2006.257.19:42:55.68/valo/01,524.99,yes,locked 2006.257.19:42:55.68/valo/02,534.99,yes,locked 2006.257.19:42:55.68/valo/03,564.99,yes,locked 2006.257.19:42:55.68/valo/04,624.99,yes,locked 2006.257.19:42:55.68/valo/05,734.99,yes,locked 2006.257.19:42:55.68/valo/06,814.99,yes,locked 2006.257.19:42:55.68/valo/07,864.99,yes,locked 2006.257.19:42:55.68/valo/08,884.99,yes,locked 2006.257.19:42:56.77/vb/01,04,usb,yes,34,31 2006.257.19:42:56.77/vb/02,05,usb,yes,32,32 2006.257.19:42:56.77/vb/03,04,usb,yes,33,36 2006.257.19:42:56.77/vb/04,05,usb,yes,33,32 2006.257.19:42:56.77/vb/05,04,usb,yes,29,32 2006.257.19:42:56.77/vb/06,04,usb,yes,34,30 2006.257.19:42:56.77/vb/07,04,usb,yes,34,34 2006.257.19:42:56.77/vb/08,04,usb,yes,31,35 2006.257.19:42:57.01/vblo/01,629.99,yes,locked 2006.257.19:42:57.01/vblo/02,634.99,yes,locked 2006.257.19:42:57.01/vblo/03,649.99,yes,locked 2006.257.19:42:57.01/vblo/04,679.99,yes,locked 2006.257.19:42:57.01/vblo/05,709.99,yes,locked 2006.257.19:42:57.01/vblo/06,719.99,yes,locked 2006.257.19:42:57.01/vblo/07,734.99,yes,locked 2006.257.19:42:57.01/vblo/08,744.99,yes,locked 2006.257.19:42:57.16/vabw/8 2006.257.19:42:57.31/vbbw/8 2006.257.19:42:57.40/xfe/off,on,15.0 2006.257.19:42:57.77/ifatt/23,28,28,28 2006.257.19:42:58.08/fmout-gps/S +4.52E-07 2006.257.19:42:58.12:!2006.257.19:46:44 2006.257.19:46:44.01:data_valid=off 2006.257.19:46:44.01:"et 2006.257.19:46:44.01:!+3s 2006.257.19:46:47.02:"tape 2006.257.19:46:47.02:postob 2006.257.19:46:47.20/cable/+6.4858E-03 2006.257.19:46:47.20/wx/17.52,1014.6,96 2006.257.19:46:48.08/fmout-gps/S +4.53E-07 2006.257.19:46:48.08:scan_name=257-1949,jd0609,100 2006.257.19:46:48.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.257.19:46:49.14#flagr#flagr/antenna,new-source 2006.257.19:46:49.14:checkk5 2006.257.19:46:49.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.19:46:49.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.19:46:50.15/chk_autoobs//k5ts3/ autoobs is running! 2006.257.19:46:50.49/chk_autoobs//k5ts4/ autoobs is running! 2006.257.19:46:50.82/chk_obsdata//k5ts1/T2571942??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.257.19:46:51.15/chk_obsdata//k5ts2/T2571942??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.257.19:46:51.47/chk_obsdata//k5ts3/T2571942??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.257.19:46:51.81/chk_obsdata//k5ts4/T2571942??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.257.19:46:52.47/k5log//k5ts1_log_newline 2006.257.19:46:53.14/k5log//k5ts2_log_newline 2006.257.19:46:53.80/k5log//k5ts3_log_newline 2006.257.19:46:54.45/k5log//k5ts4_log_newline 2006.257.19:46:54.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.19:46:54.47:setupk4=1 2006.257.19:46:54.47$setupk4/echo=on 2006.257.19:46:54.47$setupk4/pcalon 2006.257.19:46:54.47$pcalon/"no phase cal control is implemented here 2006.257.19:46:54.47$setupk4/"tpicd=stop 2006.257.19:46:54.47$setupk4/"rec=synch_on 2006.257.19:46:54.47$setupk4/"rec_mode=128 2006.257.19:46:54.47$setupk4/!* 2006.257.19:46:54.47$setupk4/recpk4 2006.257.19:46:54.47$recpk4/recpatch= 2006.257.19:46:54.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.19:46:54.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.19:46:54.48$setupk4/vck44 2006.257.19:46:54.48$vck44/valo=1,524.99 2006.257.19:46:54.48#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.19:46:54.48#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.19:46:54.48#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:54.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:54.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:54.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:54.48#ibcon#enter wrdev, iclass 23, count 0 2006.257.19:46:54.48#ibcon#first serial, iclass 23, count 0 2006.257.19:46:54.48#ibcon#enter sib2, iclass 23, count 0 2006.257.19:46:54.48#ibcon#flushed, iclass 23, count 0 2006.257.19:46:54.48#ibcon#about to write, iclass 23, count 0 2006.257.19:46:54.48#ibcon#wrote, iclass 23, count 0 2006.257.19:46:54.48#ibcon#about to read 3, iclass 23, count 0 2006.257.19:46:54.50#ibcon#read 3, iclass 23, count 0 2006.257.19:46:54.50#ibcon#about to read 4, iclass 23, count 0 2006.257.19:46:54.50#ibcon#read 4, iclass 23, count 0 2006.257.19:46:54.50#ibcon#about to read 5, iclass 23, count 0 2006.257.19:46:54.50#ibcon#read 5, iclass 23, count 0 2006.257.19:46:54.50#ibcon#about to read 6, iclass 23, count 0 2006.257.19:46:54.50#ibcon#read 6, iclass 23, count 0 2006.257.19:46:54.50#ibcon#end of sib2, iclass 23, count 0 2006.257.19:46:54.50#ibcon#*mode == 0, iclass 23, count 0 2006.257.19:46:54.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.19:46:54.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.19:46:54.50#ibcon#*before write, iclass 23, count 0 2006.257.19:46:54.50#ibcon#enter sib2, iclass 23, count 0 2006.257.19:46:54.50#ibcon#flushed, iclass 23, count 0 2006.257.19:46:54.50#ibcon#about to write, iclass 23, count 0 2006.257.19:46:54.50#ibcon#wrote, iclass 23, count 0 2006.257.19:46:54.50#ibcon#about to read 3, iclass 23, count 0 2006.257.19:46:54.55#ibcon#read 3, iclass 23, count 0 2006.257.19:46:54.55#ibcon#about to read 4, iclass 23, count 0 2006.257.19:46:54.55#ibcon#read 4, iclass 23, count 0 2006.257.19:46:54.55#ibcon#about to read 5, iclass 23, count 0 2006.257.19:46:54.55#ibcon#read 5, iclass 23, count 0 2006.257.19:46:54.55#ibcon#about to read 6, iclass 23, count 0 2006.257.19:46:54.55#ibcon#read 6, iclass 23, count 0 2006.257.19:46:54.55#ibcon#end of sib2, iclass 23, count 0 2006.257.19:46:54.55#ibcon#*after write, iclass 23, count 0 2006.257.19:46:54.55#ibcon#*before return 0, iclass 23, count 0 2006.257.19:46:54.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:54.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:54.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.19:46:54.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.19:46:54.55$vck44/va=1,8 2006.257.19:46:54.55#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.19:46:54.55#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.19:46:54.55#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:54.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:54.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:54.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:54.55#ibcon#enter wrdev, iclass 25, count 2 2006.257.19:46:54.55#ibcon#first serial, iclass 25, count 2 2006.257.19:46:54.55#ibcon#enter sib2, iclass 25, count 2 2006.257.19:46:54.55#ibcon#flushed, iclass 25, count 2 2006.257.19:46:54.55#ibcon#about to write, iclass 25, count 2 2006.257.19:46:54.55#ibcon#wrote, iclass 25, count 2 2006.257.19:46:54.55#ibcon#about to read 3, iclass 25, count 2 2006.257.19:46:54.57#ibcon#read 3, iclass 25, count 2 2006.257.19:46:54.57#ibcon#about to read 4, iclass 25, count 2 2006.257.19:46:54.57#ibcon#read 4, iclass 25, count 2 2006.257.19:46:54.57#ibcon#about to read 5, iclass 25, count 2 2006.257.19:46:54.57#ibcon#read 5, iclass 25, count 2 2006.257.19:46:54.57#ibcon#about to read 6, iclass 25, count 2 2006.257.19:46:54.57#ibcon#read 6, iclass 25, count 2 2006.257.19:46:54.57#ibcon#end of sib2, iclass 25, count 2 2006.257.19:46:54.57#ibcon#*mode == 0, iclass 25, count 2 2006.257.19:46:54.57#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.19:46:54.57#ibcon#[25=AT01-08\r\n] 2006.257.19:46:54.57#ibcon#*before write, iclass 25, count 2 2006.257.19:46:54.57#ibcon#enter sib2, iclass 25, count 2 2006.257.19:46:54.57#ibcon#flushed, iclass 25, count 2 2006.257.19:46:54.57#ibcon#about to write, iclass 25, count 2 2006.257.19:46:54.57#ibcon#wrote, iclass 25, count 2 2006.257.19:46:54.57#ibcon#about to read 3, iclass 25, count 2 2006.257.19:46:54.60#ibcon#read 3, iclass 25, count 2 2006.257.19:46:54.60#ibcon#about to read 4, iclass 25, count 2 2006.257.19:46:54.60#ibcon#read 4, iclass 25, count 2 2006.257.19:46:54.60#ibcon#about to read 5, iclass 25, count 2 2006.257.19:46:54.60#ibcon#read 5, iclass 25, count 2 2006.257.19:46:54.60#ibcon#about to read 6, iclass 25, count 2 2006.257.19:46:54.60#ibcon#read 6, iclass 25, count 2 2006.257.19:46:54.60#ibcon#end of sib2, iclass 25, count 2 2006.257.19:46:54.60#ibcon#*after write, iclass 25, count 2 2006.257.19:46:54.60#ibcon#*before return 0, iclass 25, count 2 2006.257.19:46:54.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:54.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:54.60#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.19:46:54.60#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:54.60#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:54.72#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:54.72#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:54.72#ibcon#enter wrdev, iclass 25, count 0 2006.257.19:46:54.72#ibcon#first serial, iclass 25, count 0 2006.257.19:46:54.72#ibcon#enter sib2, iclass 25, count 0 2006.257.19:46:54.72#ibcon#flushed, iclass 25, count 0 2006.257.19:46:54.72#ibcon#about to write, iclass 25, count 0 2006.257.19:46:54.72#ibcon#wrote, iclass 25, count 0 2006.257.19:46:54.72#ibcon#about to read 3, iclass 25, count 0 2006.257.19:46:54.74#ibcon#read 3, iclass 25, count 0 2006.257.19:46:54.74#ibcon#about to read 4, iclass 25, count 0 2006.257.19:46:54.74#ibcon#read 4, iclass 25, count 0 2006.257.19:46:54.74#ibcon#about to read 5, iclass 25, count 0 2006.257.19:46:54.74#ibcon#read 5, iclass 25, count 0 2006.257.19:46:54.74#ibcon#about to read 6, iclass 25, count 0 2006.257.19:46:54.74#ibcon#read 6, iclass 25, count 0 2006.257.19:46:54.74#ibcon#end of sib2, iclass 25, count 0 2006.257.19:46:54.74#ibcon#*mode == 0, iclass 25, count 0 2006.257.19:46:54.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.19:46:54.74#ibcon#[25=USB\r\n] 2006.257.19:46:54.74#ibcon#*before write, iclass 25, count 0 2006.257.19:46:54.74#ibcon#enter sib2, iclass 25, count 0 2006.257.19:46:54.74#ibcon#flushed, iclass 25, count 0 2006.257.19:46:54.74#ibcon#about to write, iclass 25, count 0 2006.257.19:46:54.74#ibcon#wrote, iclass 25, count 0 2006.257.19:46:54.74#ibcon#about to read 3, iclass 25, count 0 2006.257.19:46:54.77#ibcon#read 3, iclass 25, count 0 2006.257.19:46:54.77#ibcon#about to read 4, iclass 25, count 0 2006.257.19:46:54.77#ibcon#read 4, iclass 25, count 0 2006.257.19:46:54.77#ibcon#about to read 5, iclass 25, count 0 2006.257.19:46:54.77#ibcon#read 5, iclass 25, count 0 2006.257.19:46:54.77#ibcon#about to read 6, iclass 25, count 0 2006.257.19:46:54.77#ibcon#read 6, iclass 25, count 0 2006.257.19:46:54.77#ibcon#end of sib2, iclass 25, count 0 2006.257.19:46:54.77#ibcon#*after write, iclass 25, count 0 2006.257.19:46:54.77#ibcon#*before return 0, iclass 25, count 0 2006.257.19:46:54.77#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:54.77#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:54.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.19:46:54.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.19:46:54.77$vck44/valo=2,534.99 2006.257.19:46:54.77#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.19:46:54.77#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.19:46:54.77#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:54.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:54.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:54.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:54.77#ibcon#enter wrdev, iclass 27, count 0 2006.257.19:46:54.77#ibcon#first serial, iclass 27, count 0 2006.257.19:46:54.77#ibcon#enter sib2, iclass 27, count 0 2006.257.19:46:54.77#ibcon#flushed, iclass 27, count 0 2006.257.19:46:54.77#ibcon#about to write, iclass 27, count 0 2006.257.19:46:54.77#ibcon#wrote, iclass 27, count 0 2006.257.19:46:54.77#ibcon#about to read 3, iclass 27, count 0 2006.257.19:46:54.79#ibcon#read 3, iclass 27, count 0 2006.257.19:46:54.79#ibcon#about to read 4, iclass 27, count 0 2006.257.19:46:54.79#ibcon#read 4, iclass 27, count 0 2006.257.19:46:54.79#ibcon#about to read 5, iclass 27, count 0 2006.257.19:46:54.79#ibcon#read 5, iclass 27, count 0 2006.257.19:46:54.79#ibcon#about to read 6, iclass 27, count 0 2006.257.19:46:54.79#ibcon#read 6, iclass 27, count 0 2006.257.19:46:54.79#ibcon#end of sib2, iclass 27, count 0 2006.257.19:46:54.79#ibcon#*mode == 0, iclass 27, count 0 2006.257.19:46:54.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.19:46:54.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.19:46:54.79#ibcon#*before write, iclass 27, count 0 2006.257.19:46:54.79#ibcon#enter sib2, iclass 27, count 0 2006.257.19:46:54.79#ibcon#flushed, iclass 27, count 0 2006.257.19:46:54.79#ibcon#about to write, iclass 27, count 0 2006.257.19:46:54.79#ibcon#wrote, iclass 27, count 0 2006.257.19:46:54.79#ibcon#about to read 3, iclass 27, count 0 2006.257.19:46:54.83#ibcon#read 3, iclass 27, count 0 2006.257.19:46:54.83#ibcon#about to read 4, iclass 27, count 0 2006.257.19:46:54.83#ibcon#read 4, iclass 27, count 0 2006.257.19:46:54.83#ibcon#about to read 5, iclass 27, count 0 2006.257.19:46:54.83#ibcon#read 5, iclass 27, count 0 2006.257.19:46:54.83#ibcon#about to read 6, iclass 27, count 0 2006.257.19:46:54.83#ibcon#read 6, iclass 27, count 0 2006.257.19:46:54.83#ibcon#end of sib2, iclass 27, count 0 2006.257.19:46:54.83#ibcon#*after write, iclass 27, count 0 2006.257.19:46:54.83#ibcon#*before return 0, iclass 27, count 0 2006.257.19:46:54.83#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:54.83#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:54.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.19:46:54.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.19:46:54.83$vck44/va=2,7 2006.257.19:46:54.83#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.19:46:54.83#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.19:46:54.83#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:54.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:54.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:54.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:54.89#ibcon#enter wrdev, iclass 29, count 2 2006.257.19:46:54.89#ibcon#first serial, iclass 29, count 2 2006.257.19:46:54.89#ibcon#enter sib2, iclass 29, count 2 2006.257.19:46:54.89#ibcon#flushed, iclass 29, count 2 2006.257.19:46:54.89#ibcon#about to write, iclass 29, count 2 2006.257.19:46:54.89#ibcon#wrote, iclass 29, count 2 2006.257.19:46:54.89#ibcon#about to read 3, iclass 29, count 2 2006.257.19:46:54.91#ibcon#read 3, iclass 29, count 2 2006.257.19:46:54.91#ibcon#about to read 4, iclass 29, count 2 2006.257.19:46:54.91#ibcon#read 4, iclass 29, count 2 2006.257.19:46:54.91#ibcon#about to read 5, iclass 29, count 2 2006.257.19:46:54.91#ibcon#read 5, iclass 29, count 2 2006.257.19:46:54.91#ibcon#about to read 6, iclass 29, count 2 2006.257.19:46:54.91#ibcon#read 6, iclass 29, count 2 2006.257.19:46:54.91#ibcon#end of sib2, iclass 29, count 2 2006.257.19:46:54.91#ibcon#*mode == 0, iclass 29, count 2 2006.257.19:46:54.91#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.19:46:54.91#ibcon#[25=AT02-07\r\n] 2006.257.19:46:54.91#ibcon#*before write, iclass 29, count 2 2006.257.19:46:54.91#ibcon#enter sib2, iclass 29, count 2 2006.257.19:46:54.91#ibcon#flushed, iclass 29, count 2 2006.257.19:46:54.91#ibcon#about to write, iclass 29, count 2 2006.257.19:46:54.91#ibcon#wrote, iclass 29, count 2 2006.257.19:46:54.91#ibcon#about to read 3, iclass 29, count 2 2006.257.19:46:54.94#ibcon#read 3, iclass 29, count 2 2006.257.19:46:54.94#ibcon#about to read 4, iclass 29, count 2 2006.257.19:46:54.94#ibcon#read 4, iclass 29, count 2 2006.257.19:46:54.94#ibcon#about to read 5, iclass 29, count 2 2006.257.19:46:54.94#ibcon#read 5, iclass 29, count 2 2006.257.19:46:54.94#ibcon#about to read 6, iclass 29, count 2 2006.257.19:46:54.94#ibcon#read 6, iclass 29, count 2 2006.257.19:46:54.94#ibcon#end of sib2, iclass 29, count 2 2006.257.19:46:54.94#ibcon#*after write, iclass 29, count 2 2006.257.19:46:54.94#ibcon#*before return 0, iclass 29, count 2 2006.257.19:46:54.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:54.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:54.94#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.19:46:54.94#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:54.94#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:55.06#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:55.06#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:55.06#ibcon#enter wrdev, iclass 29, count 0 2006.257.19:46:55.06#ibcon#first serial, iclass 29, count 0 2006.257.19:46:55.06#ibcon#enter sib2, iclass 29, count 0 2006.257.19:46:55.06#ibcon#flushed, iclass 29, count 0 2006.257.19:46:55.06#ibcon#about to write, iclass 29, count 0 2006.257.19:46:55.06#ibcon#wrote, iclass 29, count 0 2006.257.19:46:55.06#ibcon#about to read 3, iclass 29, count 0 2006.257.19:46:55.08#ibcon#read 3, iclass 29, count 0 2006.257.19:46:55.08#ibcon#about to read 4, iclass 29, count 0 2006.257.19:46:55.08#ibcon#read 4, iclass 29, count 0 2006.257.19:46:55.08#ibcon#about to read 5, iclass 29, count 0 2006.257.19:46:55.08#ibcon#read 5, iclass 29, count 0 2006.257.19:46:55.08#ibcon#about to read 6, iclass 29, count 0 2006.257.19:46:55.08#ibcon#read 6, iclass 29, count 0 2006.257.19:46:55.08#ibcon#end of sib2, iclass 29, count 0 2006.257.19:46:55.08#ibcon#*mode == 0, iclass 29, count 0 2006.257.19:46:55.08#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.19:46:55.08#ibcon#[25=USB\r\n] 2006.257.19:46:55.08#ibcon#*before write, iclass 29, count 0 2006.257.19:46:55.08#ibcon#enter sib2, iclass 29, count 0 2006.257.19:46:55.08#ibcon#flushed, iclass 29, count 0 2006.257.19:46:55.08#ibcon#about to write, iclass 29, count 0 2006.257.19:46:55.08#ibcon#wrote, iclass 29, count 0 2006.257.19:46:55.08#ibcon#about to read 3, iclass 29, count 0 2006.257.19:46:55.11#ibcon#read 3, iclass 29, count 0 2006.257.19:46:55.11#ibcon#about to read 4, iclass 29, count 0 2006.257.19:46:55.11#ibcon#read 4, iclass 29, count 0 2006.257.19:46:55.11#ibcon#about to read 5, iclass 29, count 0 2006.257.19:46:55.11#ibcon#read 5, iclass 29, count 0 2006.257.19:46:55.11#ibcon#about to read 6, iclass 29, count 0 2006.257.19:46:55.11#ibcon#read 6, iclass 29, count 0 2006.257.19:46:55.11#ibcon#end of sib2, iclass 29, count 0 2006.257.19:46:55.11#ibcon#*after write, iclass 29, count 0 2006.257.19:46:55.11#ibcon#*before return 0, iclass 29, count 0 2006.257.19:46:55.11#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:55.11#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:55.11#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.19:46:55.11#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.19:46:55.11$vck44/valo=3,564.99 2006.257.19:46:55.11#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.19:46:55.11#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.19:46:55.11#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:55.11#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:55.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:55.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:55.11#ibcon#enter wrdev, iclass 31, count 0 2006.257.19:46:55.11#ibcon#first serial, iclass 31, count 0 2006.257.19:46:55.11#ibcon#enter sib2, iclass 31, count 0 2006.257.19:46:55.11#ibcon#flushed, iclass 31, count 0 2006.257.19:46:55.11#ibcon#about to write, iclass 31, count 0 2006.257.19:46:55.11#ibcon#wrote, iclass 31, count 0 2006.257.19:46:55.11#ibcon#about to read 3, iclass 31, count 0 2006.257.19:46:55.13#ibcon#read 3, iclass 31, count 0 2006.257.19:46:55.13#ibcon#about to read 4, iclass 31, count 0 2006.257.19:46:55.13#ibcon#read 4, iclass 31, count 0 2006.257.19:46:55.13#ibcon#about to read 5, iclass 31, count 0 2006.257.19:46:55.13#ibcon#read 5, iclass 31, count 0 2006.257.19:46:55.13#ibcon#about to read 6, iclass 31, count 0 2006.257.19:46:55.13#ibcon#read 6, iclass 31, count 0 2006.257.19:46:55.13#ibcon#end of sib2, iclass 31, count 0 2006.257.19:46:55.13#ibcon#*mode == 0, iclass 31, count 0 2006.257.19:46:55.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.19:46:55.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.19:46:55.13#ibcon#*before write, iclass 31, count 0 2006.257.19:46:55.13#ibcon#enter sib2, iclass 31, count 0 2006.257.19:46:55.13#ibcon#flushed, iclass 31, count 0 2006.257.19:46:55.13#ibcon#about to write, iclass 31, count 0 2006.257.19:46:55.13#ibcon#wrote, iclass 31, count 0 2006.257.19:46:55.13#ibcon#about to read 3, iclass 31, count 0 2006.257.19:46:55.17#ibcon#read 3, iclass 31, count 0 2006.257.19:46:55.17#ibcon#about to read 4, iclass 31, count 0 2006.257.19:46:55.17#ibcon#read 4, iclass 31, count 0 2006.257.19:46:55.17#ibcon#about to read 5, iclass 31, count 0 2006.257.19:46:55.17#ibcon#read 5, iclass 31, count 0 2006.257.19:46:55.17#ibcon#about to read 6, iclass 31, count 0 2006.257.19:46:55.17#ibcon#read 6, iclass 31, count 0 2006.257.19:46:55.17#ibcon#end of sib2, iclass 31, count 0 2006.257.19:46:55.17#ibcon#*after write, iclass 31, count 0 2006.257.19:46:55.17#ibcon#*before return 0, iclass 31, count 0 2006.257.19:46:55.17#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:55.17#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:55.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.19:46:55.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.19:46:55.17$vck44/va=3,8 2006.257.19:46:55.17#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.19:46:55.17#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.19:46:55.17#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:55.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:55.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:55.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:55.23#ibcon#enter wrdev, iclass 33, count 2 2006.257.19:46:55.23#ibcon#first serial, iclass 33, count 2 2006.257.19:46:55.23#ibcon#enter sib2, iclass 33, count 2 2006.257.19:46:55.23#ibcon#flushed, iclass 33, count 2 2006.257.19:46:55.23#ibcon#about to write, iclass 33, count 2 2006.257.19:46:55.23#ibcon#wrote, iclass 33, count 2 2006.257.19:46:55.23#ibcon#about to read 3, iclass 33, count 2 2006.257.19:46:55.25#ibcon#read 3, iclass 33, count 2 2006.257.19:46:55.25#ibcon#about to read 4, iclass 33, count 2 2006.257.19:46:55.25#ibcon#read 4, iclass 33, count 2 2006.257.19:46:55.25#ibcon#about to read 5, iclass 33, count 2 2006.257.19:46:55.25#ibcon#read 5, iclass 33, count 2 2006.257.19:46:55.25#ibcon#about to read 6, iclass 33, count 2 2006.257.19:46:55.25#ibcon#read 6, iclass 33, count 2 2006.257.19:46:55.25#ibcon#end of sib2, iclass 33, count 2 2006.257.19:46:55.25#ibcon#*mode == 0, iclass 33, count 2 2006.257.19:46:55.25#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.19:46:55.25#ibcon#[25=AT03-08\r\n] 2006.257.19:46:55.25#ibcon#*before write, iclass 33, count 2 2006.257.19:46:55.25#ibcon#enter sib2, iclass 33, count 2 2006.257.19:46:55.25#ibcon#flushed, iclass 33, count 2 2006.257.19:46:55.25#ibcon#about to write, iclass 33, count 2 2006.257.19:46:55.25#ibcon#wrote, iclass 33, count 2 2006.257.19:46:55.25#ibcon#about to read 3, iclass 33, count 2 2006.257.19:46:55.28#ibcon#read 3, iclass 33, count 2 2006.257.19:46:55.28#ibcon#about to read 4, iclass 33, count 2 2006.257.19:46:55.28#ibcon#read 4, iclass 33, count 2 2006.257.19:46:55.28#ibcon#about to read 5, iclass 33, count 2 2006.257.19:46:55.28#ibcon#read 5, iclass 33, count 2 2006.257.19:46:55.28#ibcon#about to read 6, iclass 33, count 2 2006.257.19:46:55.28#ibcon#read 6, iclass 33, count 2 2006.257.19:46:55.28#ibcon#end of sib2, iclass 33, count 2 2006.257.19:46:55.28#ibcon#*after write, iclass 33, count 2 2006.257.19:46:55.28#ibcon#*before return 0, iclass 33, count 2 2006.257.19:46:55.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:55.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:55.28#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.19:46:55.28#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:55.28#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:55.40#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:55.40#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:55.40#ibcon#enter wrdev, iclass 33, count 0 2006.257.19:46:55.40#ibcon#first serial, iclass 33, count 0 2006.257.19:46:55.40#ibcon#enter sib2, iclass 33, count 0 2006.257.19:46:55.40#ibcon#flushed, iclass 33, count 0 2006.257.19:46:55.40#ibcon#about to write, iclass 33, count 0 2006.257.19:46:55.40#ibcon#wrote, iclass 33, count 0 2006.257.19:46:55.40#ibcon#about to read 3, iclass 33, count 0 2006.257.19:46:55.42#ibcon#read 3, iclass 33, count 0 2006.257.19:46:55.42#ibcon#about to read 4, iclass 33, count 0 2006.257.19:46:55.42#ibcon#read 4, iclass 33, count 0 2006.257.19:46:55.42#ibcon#about to read 5, iclass 33, count 0 2006.257.19:46:55.42#ibcon#read 5, iclass 33, count 0 2006.257.19:46:55.42#ibcon#about to read 6, iclass 33, count 0 2006.257.19:46:55.42#ibcon#read 6, iclass 33, count 0 2006.257.19:46:55.42#ibcon#end of sib2, iclass 33, count 0 2006.257.19:46:55.42#ibcon#*mode == 0, iclass 33, count 0 2006.257.19:46:55.42#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.19:46:55.42#ibcon#[25=USB\r\n] 2006.257.19:46:55.42#ibcon#*before write, iclass 33, count 0 2006.257.19:46:55.42#ibcon#enter sib2, iclass 33, count 0 2006.257.19:46:55.42#ibcon#flushed, iclass 33, count 0 2006.257.19:46:55.42#ibcon#about to write, iclass 33, count 0 2006.257.19:46:55.42#ibcon#wrote, iclass 33, count 0 2006.257.19:46:55.42#ibcon#about to read 3, iclass 33, count 0 2006.257.19:46:55.45#ibcon#read 3, iclass 33, count 0 2006.257.19:46:55.45#ibcon#about to read 4, iclass 33, count 0 2006.257.19:46:55.45#ibcon#read 4, iclass 33, count 0 2006.257.19:46:55.45#ibcon#about to read 5, iclass 33, count 0 2006.257.19:46:55.45#ibcon#read 5, iclass 33, count 0 2006.257.19:46:55.45#ibcon#about to read 6, iclass 33, count 0 2006.257.19:46:55.45#ibcon#read 6, iclass 33, count 0 2006.257.19:46:55.45#ibcon#end of sib2, iclass 33, count 0 2006.257.19:46:55.45#ibcon#*after write, iclass 33, count 0 2006.257.19:46:55.45#ibcon#*before return 0, iclass 33, count 0 2006.257.19:46:55.45#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:55.45#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:55.45#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.19:46:55.45#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.19:46:55.45$vck44/valo=4,624.99 2006.257.19:46:55.45#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.19:46:55.45#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.19:46:55.45#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:55.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:55.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:55.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:55.45#ibcon#enter wrdev, iclass 35, count 0 2006.257.19:46:55.45#ibcon#first serial, iclass 35, count 0 2006.257.19:46:55.45#ibcon#enter sib2, iclass 35, count 0 2006.257.19:46:55.45#ibcon#flushed, iclass 35, count 0 2006.257.19:46:55.45#ibcon#about to write, iclass 35, count 0 2006.257.19:46:55.45#ibcon#wrote, iclass 35, count 0 2006.257.19:46:55.45#ibcon#about to read 3, iclass 35, count 0 2006.257.19:46:55.47#ibcon#read 3, iclass 35, count 0 2006.257.19:46:55.47#ibcon#about to read 4, iclass 35, count 0 2006.257.19:46:55.47#ibcon#read 4, iclass 35, count 0 2006.257.19:46:55.47#ibcon#about to read 5, iclass 35, count 0 2006.257.19:46:55.47#ibcon#read 5, iclass 35, count 0 2006.257.19:46:55.47#ibcon#about to read 6, iclass 35, count 0 2006.257.19:46:55.47#ibcon#read 6, iclass 35, count 0 2006.257.19:46:55.47#ibcon#end of sib2, iclass 35, count 0 2006.257.19:46:55.47#ibcon#*mode == 0, iclass 35, count 0 2006.257.19:46:55.47#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.19:46:55.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.19:46:55.47#ibcon#*before write, iclass 35, count 0 2006.257.19:46:55.47#ibcon#enter sib2, iclass 35, count 0 2006.257.19:46:55.47#ibcon#flushed, iclass 35, count 0 2006.257.19:46:55.47#ibcon#about to write, iclass 35, count 0 2006.257.19:46:55.47#ibcon#wrote, iclass 35, count 0 2006.257.19:46:55.47#ibcon#about to read 3, iclass 35, count 0 2006.257.19:46:55.51#ibcon#read 3, iclass 35, count 0 2006.257.19:46:55.51#ibcon#about to read 4, iclass 35, count 0 2006.257.19:46:55.51#ibcon#read 4, iclass 35, count 0 2006.257.19:46:55.51#ibcon#about to read 5, iclass 35, count 0 2006.257.19:46:55.51#ibcon#read 5, iclass 35, count 0 2006.257.19:46:55.51#ibcon#about to read 6, iclass 35, count 0 2006.257.19:46:55.51#ibcon#read 6, iclass 35, count 0 2006.257.19:46:55.51#ibcon#end of sib2, iclass 35, count 0 2006.257.19:46:55.51#ibcon#*after write, iclass 35, count 0 2006.257.19:46:55.51#ibcon#*before return 0, iclass 35, count 0 2006.257.19:46:55.51#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:55.51#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:55.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.19:46:55.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.19:46:55.51$vck44/va=4,7 2006.257.19:46:55.51#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.19:46:55.51#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.19:46:55.51#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:55.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:55.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:55.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:55.57#ibcon#enter wrdev, iclass 37, count 2 2006.257.19:46:55.57#ibcon#first serial, iclass 37, count 2 2006.257.19:46:55.57#ibcon#enter sib2, iclass 37, count 2 2006.257.19:46:55.57#ibcon#flushed, iclass 37, count 2 2006.257.19:46:55.57#ibcon#about to write, iclass 37, count 2 2006.257.19:46:55.57#ibcon#wrote, iclass 37, count 2 2006.257.19:46:55.57#ibcon#about to read 3, iclass 37, count 2 2006.257.19:46:55.59#ibcon#read 3, iclass 37, count 2 2006.257.19:46:55.59#ibcon#about to read 4, iclass 37, count 2 2006.257.19:46:55.59#ibcon#read 4, iclass 37, count 2 2006.257.19:46:55.59#ibcon#about to read 5, iclass 37, count 2 2006.257.19:46:55.59#ibcon#read 5, iclass 37, count 2 2006.257.19:46:55.59#ibcon#about to read 6, iclass 37, count 2 2006.257.19:46:55.59#ibcon#read 6, iclass 37, count 2 2006.257.19:46:55.59#ibcon#end of sib2, iclass 37, count 2 2006.257.19:46:55.59#ibcon#*mode == 0, iclass 37, count 2 2006.257.19:46:55.59#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.19:46:55.59#ibcon#[25=AT04-07\r\n] 2006.257.19:46:55.59#ibcon#*before write, iclass 37, count 2 2006.257.19:46:55.59#ibcon#enter sib2, iclass 37, count 2 2006.257.19:46:55.59#ibcon#flushed, iclass 37, count 2 2006.257.19:46:55.59#ibcon#about to write, iclass 37, count 2 2006.257.19:46:55.59#ibcon#wrote, iclass 37, count 2 2006.257.19:46:55.59#ibcon#about to read 3, iclass 37, count 2 2006.257.19:46:55.62#ibcon#read 3, iclass 37, count 2 2006.257.19:46:55.62#ibcon#about to read 4, iclass 37, count 2 2006.257.19:46:55.62#ibcon#read 4, iclass 37, count 2 2006.257.19:46:55.62#ibcon#about to read 5, iclass 37, count 2 2006.257.19:46:55.62#ibcon#read 5, iclass 37, count 2 2006.257.19:46:55.62#ibcon#about to read 6, iclass 37, count 2 2006.257.19:46:55.62#ibcon#read 6, iclass 37, count 2 2006.257.19:46:55.62#ibcon#end of sib2, iclass 37, count 2 2006.257.19:46:55.62#ibcon#*after write, iclass 37, count 2 2006.257.19:46:55.62#ibcon#*before return 0, iclass 37, count 2 2006.257.19:46:55.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:55.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:55.62#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.19:46:55.62#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:55.62#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:55.74#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:55.74#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:55.74#ibcon#enter wrdev, iclass 37, count 0 2006.257.19:46:55.74#ibcon#first serial, iclass 37, count 0 2006.257.19:46:55.74#ibcon#enter sib2, iclass 37, count 0 2006.257.19:46:55.74#ibcon#flushed, iclass 37, count 0 2006.257.19:46:55.74#ibcon#about to write, iclass 37, count 0 2006.257.19:46:55.74#ibcon#wrote, iclass 37, count 0 2006.257.19:46:55.74#ibcon#about to read 3, iclass 37, count 0 2006.257.19:46:55.76#ibcon#read 3, iclass 37, count 0 2006.257.19:46:55.76#ibcon#about to read 4, iclass 37, count 0 2006.257.19:46:55.76#ibcon#read 4, iclass 37, count 0 2006.257.19:46:55.76#ibcon#about to read 5, iclass 37, count 0 2006.257.19:46:55.76#ibcon#read 5, iclass 37, count 0 2006.257.19:46:55.76#ibcon#about to read 6, iclass 37, count 0 2006.257.19:46:55.76#ibcon#read 6, iclass 37, count 0 2006.257.19:46:55.76#ibcon#end of sib2, iclass 37, count 0 2006.257.19:46:55.76#ibcon#*mode == 0, iclass 37, count 0 2006.257.19:46:55.76#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.19:46:55.76#ibcon#[25=USB\r\n] 2006.257.19:46:55.76#ibcon#*before write, iclass 37, count 0 2006.257.19:46:55.76#ibcon#enter sib2, iclass 37, count 0 2006.257.19:46:55.76#ibcon#flushed, iclass 37, count 0 2006.257.19:46:55.76#ibcon#about to write, iclass 37, count 0 2006.257.19:46:55.76#ibcon#wrote, iclass 37, count 0 2006.257.19:46:55.76#ibcon#about to read 3, iclass 37, count 0 2006.257.19:46:55.79#ibcon#read 3, iclass 37, count 0 2006.257.19:46:55.79#ibcon#about to read 4, iclass 37, count 0 2006.257.19:46:55.79#ibcon#read 4, iclass 37, count 0 2006.257.19:46:55.79#ibcon#about to read 5, iclass 37, count 0 2006.257.19:46:55.79#ibcon#read 5, iclass 37, count 0 2006.257.19:46:55.79#ibcon#about to read 6, iclass 37, count 0 2006.257.19:46:55.79#ibcon#read 6, iclass 37, count 0 2006.257.19:46:55.79#ibcon#end of sib2, iclass 37, count 0 2006.257.19:46:55.79#ibcon#*after write, iclass 37, count 0 2006.257.19:46:55.79#ibcon#*before return 0, iclass 37, count 0 2006.257.19:46:55.79#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:55.79#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:55.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.19:46:55.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.19:46:55.79$vck44/valo=5,734.99 2006.257.19:46:55.79#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.19:46:55.79#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.19:46:55.79#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:55.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:55.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:55.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:55.79#ibcon#enter wrdev, iclass 39, count 0 2006.257.19:46:55.79#ibcon#first serial, iclass 39, count 0 2006.257.19:46:55.79#ibcon#enter sib2, iclass 39, count 0 2006.257.19:46:55.79#ibcon#flushed, iclass 39, count 0 2006.257.19:46:55.79#ibcon#about to write, iclass 39, count 0 2006.257.19:46:55.79#ibcon#wrote, iclass 39, count 0 2006.257.19:46:55.79#ibcon#about to read 3, iclass 39, count 0 2006.257.19:46:55.81#ibcon#read 3, iclass 39, count 0 2006.257.19:46:55.81#ibcon#about to read 4, iclass 39, count 0 2006.257.19:46:55.81#ibcon#read 4, iclass 39, count 0 2006.257.19:46:55.81#ibcon#about to read 5, iclass 39, count 0 2006.257.19:46:55.81#ibcon#read 5, iclass 39, count 0 2006.257.19:46:55.81#ibcon#about to read 6, iclass 39, count 0 2006.257.19:46:55.81#ibcon#read 6, iclass 39, count 0 2006.257.19:46:55.81#ibcon#end of sib2, iclass 39, count 0 2006.257.19:46:55.81#ibcon#*mode == 0, iclass 39, count 0 2006.257.19:46:55.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.19:46:55.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.19:46:55.81#ibcon#*before write, iclass 39, count 0 2006.257.19:46:55.81#ibcon#enter sib2, iclass 39, count 0 2006.257.19:46:55.81#ibcon#flushed, iclass 39, count 0 2006.257.19:46:55.81#ibcon#about to write, iclass 39, count 0 2006.257.19:46:55.81#ibcon#wrote, iclass 39, count 0 2006.257.19:46:55.81#ibcon#about to read 3, iclass 39, count 0 2006.257.19:46:55.85#ibcon#read 3, iclass 39, count 0 2006.257.19:46:55.85#ibcon#about to read 4, iclass 39, count 0 2006.257.19:46:55.85#ibcon#read 4, iclass 39, count 0 2006.257.19:46:55.85#ibcon#about to read 5, iclass 39, count 0 2006.257.19:46:55.85#ibcon#read 5, iclass 39, count 0 2006.257.19:46:55.85#ibcon#about to read 6, iclass 39, count 0 2006.257.19:46:55.85#ibcon#read 6, iclass 39, count 0 2006.257.19:46:55.85#ibcon#end of sib2, iclass 39, count 0 2006.257.19:46:55.85#ibcon#*after write, iclass 39, count 0 2006.257.19:46:55.85#ibcon#*before return 0, iclass 39, count 0 2006.257.19:46:55.85#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:55.85#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:55.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.19:46:55.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.19:46:55.85$vck44/va=5,4 2006.257.19:46:55.85#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.19:46:55.85#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.19:46:55.85#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:55.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:55.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:55.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:55.91#ibcon#enter wrdev, iclass 3, count 2 2006.257.19:46:55.91#ibcon#first serial, iclass 3, count 2 2006.257.19:46:55.91#ibcon#enter sib2, iclass 3, count 2 2006.257.19:46:55.91#ibcon#flushed, iclass 3, count 2 2006.257.19:46:55.91#ibcon#about to write, iclass 3, count 2 2006.257.19:46:55.91#ibcon#wrote, iclass 3, count 2 2006.257.19:46:55.91#ibcon#about to read 3, iclass 3, count 2 2006.257.19:46:55.93#ibcon#read 3, iclass 3, count 2 2006.257.19:46:55.93#ibcon#about to read 4, iclass 3, count 2 2006.257.19:46:55.93#ibcon#read 4, iclass 3, count 2 2006.257.19:46:55.93#ibcon#about to read 5, iclass 3, count 2 2006.257.19:46:55.93#ibcon#read 5, iclass 3, count 2 2006.257.19:46:55.93#ibcon#about to read 6, iclass 3, count 2 2006.257.19:46:55.93#ibcon#read 6, iclass 3, count 2 2006.257.19:46:55.93#ibcon#end of sib2, iclass 3, count 2 2006.257.19:46:55.93#ibcon#*mode == 0, iclass 3, count 2 2006.257.19:46:55.93#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.19:46:55.93#ibcon#[25=AT05-04\r\n] 2006.257.19:46:55.93#ibcon#*before write, iclass 3, count 2 2006.257.19:46:55.93#ibcon#enter sib2, iclass 3, count 2 2006.257.19:46:55.93#ibcon#flushed, iclass 3, count 2 2006.257.19:46:55.93#ibcon#about to write, iclass 3, count 2 2006.257.19:46:55.93#ibcon#wrote, iclass 3, count 2 2006.257.19:46:55.93#ibcon#about to read 3, iclass 3, count 2 2006.257.19:46:55.96#ibcon#read 3, iclass 3, count 2 2006.257.19:46:55.96#ibcon#about to read 4, iclass 3, count 2 2006.257.19:46:55.96#ibcon#read 4, iclass 3, count 2 2006.257.19:46:55.96#ibcon#about to read 5, iclass 3, count 2 2006.257.19:46:55.96#ibcon#read 5, iclass 3, count 2 2006.257.19:46:55.96#ibcon#about to read 6, iclass 3, count 2 2006.257.19:46:55.96#ibcon#read 6, iclass 3, count 2 2006.257.19:46:55.96#ibcon#end of sib2, iclass 3, count 2 2006.257.19:46:55.96#ibcon#*after write, iclass 3, count 2 2006.257.19:46:55.96#ibcon#*before return 0, iclass 3, count 2 2006.257.19:46:55.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:55.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:55.96#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.19:46:55.96#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:55.96#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:56.08#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:56.08#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:56.08#ibcon#enter wrdev, iclass 3, count 0 2006.257.19:46:56.08#ibcon#first serial, iclass 3, count 0 2006.257.19:46:56.08#ibcon#enter sib2, iclass 3, count 0 2006.257.19:46:56.08#ibcon#flushed, iclass 3, count 0 2006.257.19:46:56.08#ibcon#about to write, iclass 3, count 0 2006.257.19:46:56.08#ibcon#wrote, iclass 3, count 0 2006.257.19:46:56.08#ibcon#about to read 3, iclass 3, count 0 2006.257.19:46:56.10#ibcon#read 3, iclass 3, count 0 2006.257.19:46:56.10#ibcon#about to read 4, iclass 3, count 0 2006.257.19:46:56.10#ibcon#read 4, iclass 3, count 0 2006.257.19:46:56.10#ibcon#about to read 5, iclass 3, count 0 2006.257.19:46:56.10#ibcon#read 5, iclass 3, count 0 2006.257.19:46:56.10#ibcon#about to read 6, iclass 3, count 0 2006.257.19:46:56.10#ibcon#read 6, iclass 3, count 0 2006.257.19:46:56.10#ibcon#end of sib2, iclass 3, count 0 2006.257.19:46:56.10#ibcon#*mode == 0, iclass 3, count 0 2006.257.19:46:56.10#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.19:46:56.10#ibcon#[25=USB\r\n] 2006.257.19:46:56.10#ibcon#*before write, iclass 3, count 0 2006.257.19:46:56.10#ibcon#enter sib2, iclass 3, count 0 2006.257.19:46:56.10#ibcon#flushed, iclass 3, count 0 2006.257.19:46:56.10#ibcon#about to write, iclass 3, count 0 2006.257.19:46:56.10#ibcon#wrote, iclass 3, count 0 2006.257.19:46:56.10#ibcon#about to read 3, iclass 3, count 0 2006.257.19:46:56.13#ibcon#read 3, iclass 3, count 0 2006.257.19:46:56.13#ibcon#about to read 4, iclass 3, count 0 2006.257.19:46:56.13#ibcon#read 4, iclass 3, count 0 2006.257.19:46:56.13#ibcon#about to read 5, iclass 3, count 0 2006.257.19:46:56.13#ibcon#read 5, iclass 3, count 0 2006.257.19:46:56.13#ibcon#about to read 6, iclass 3, count 0 2006.257.19:46:56.13#ibcon#read 6, iclass 3, count 0 2006.257.19:46:56.13#ibcon#end of sib2, iclass 3, count 0 2006.257.19:46:56.13#ibcon#*after write, iclass 3, count 0 2006.257.19:46:56.13#ibcon#*before return 0, iclass 3, count 0 2006.257.19:46:56.13#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:56.13#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:56.13#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.19:46:56.13#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.19:46:56.13$vck44/valo=6,814.99 2006.257.19:46:56.13#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.19:46:56.13#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.19:46:56.13#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:56.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:56.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:56.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:56.13#ibcon#enter wrdev, iclass 5, count 0 2006.257.19:46:56.13#ibcon#first serial, iclass 5, count 0 2006.257.19:46:56.13#ibcon#enter sib2, iclass 5, count 0 2006.257.19:46:56.13#ibcon#flushed, iclass 5, count 0 2006.257.19:46:56.13#ibcon#about to write, iclass 5, count 0 2006.257.19:46:56.13#ibcon#wrote, iclass 5, count 0 2006.257.19:46:56.13#ibcon#about to read 3, iclass 5, count 0 2006.257.19:46:56.15#ibcon#read 3, iclass 5, count 0 2006.257.19:46:56.15#ibcon#about to read 4, iclass 5, count 0 2006.257.19:46:56.15#ibcon#read 4, iclass 5, count 0 2006.257.19:46:56.15#ibcon#about to read 5, iclass 5, count 0 2006.257.19:46:56.15#ibcon#read 5, iclass 5, count 0 2006.257.19:46:56.15#ibcon#about to read 6, iclass 5, count 0 2006.257.19:46:56.15#ibcon#read 6, iclass 5, count 0 2006.257.19:46:56.15#ibcon#end of sib2, iclass 5, count 0 2006.257.19:46:56.15#ibcon#*mode == 0, iclass 5, count 0 2006.257.19:46:56.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.19:46:56.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.19:46:56.15#ibcon#*before write, iclass 5, count 0 2006.257.19:46:56.15#ibcon#enter sib2, iclass 5, count 0 2006.257.19:46:56.15#ibcon#flushed, iclass 5, count 0 2006.257.19:46:56.15#ibcon#about to write, iclass 5, count 0 2006.257.19:46:56.15#ibcon#wrote, iclass 5, count 0 2006.257.19:46:56.15#ibcon#about to read 3, iclass 5, count 0 2006.257.19:46:56.19#ibcon#read 3, iclass 5, count 0 2006.257.19:46:56.19#ibcon#about to read 4, iclass 5, count 0 2006.257.19:46:56.19#ibcon#read 4, iclass 5, count 0 2006.257.19:46:56.19#ibcon#about to read 5, iclass 5, count 0 2006.257.19:46:56.19#ibcon#read 5, iclass 5, count 0 2006.257.19:46:56.19#ibcon#about to read 6, iclass 5, count 0 2006.257.19:46:56.19#ibcon#read 6, iclass 5, count 0 2006.257.19:46:56.19#ibcon#end of sib2, iclass 5, count 0 2006.257.19:46:56.19#ibcon#*after write, iclass 5, count 0 2006.257.19:46:56.19#ibcon#*before return 0, iclass 5, count 0 2006.257.19:46:56.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:56.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:56.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.19:46:56.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.19:46:56.19$vck44/va=6,4 2006.257.19:46:56.19#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.19:46:56.19#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.19:46:56.19#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:56.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:56.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:56.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:56.25#ibcon#enter wrdev, iclass 7, count 2 2006.257.19:46:56.25#ibcon#first serial, iclass 7, count 2 2006.257.19:46:56.25#ibcon#enter sib2, iclass 7, count 2 2006.257.19:46:56.25#ibcon#flushed, iclass 7, count 2 2006.257.19:46:56.25#ibcon#about to write, iclass 7, count 2 2006.257.19:46:56.25#ibcon#wrote, iclass 7, count 2 2006.257.19:46:56.25#ibcon#about to read 3, iclass 7, count 2 2006.257.19:46:56.27#ibcon#read 3, iclass 7, count 2 2006.257.19:46:56.27#ibcon#about to read 4, iclass 7, count 2 2006.257.19:46:56.27#ibcon#read 4, iclass 7, count 2 2006.257.19:46:56.27#ibcon#about to read 5, iclass 7, count 2 2006.257.19:46:56.27#ibcon#read 5, iclass 7, count 2 2006.257.19:46:56.27#ibcon#about to read 6, iclass 7, count 2 2006.257.19:46:56.27#ibcon#read 6, iclass 7, count 2 2006.257.19:46:56.27#ibcon#end of sib2, iclass 7, count 2 2006.257.19:46:56.27#ibcon#*mode == 0, iclass 7, count 2 2006.257.19:46:56.27#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.19:46:56.27#ibcon#[25=AT06-04\r\n] 2006.257.19:46:56.27#ibcon#*before write, iclass 7, count 2 2006.257.19:46:56.27#ibcon#enter sib2, iclass 7, count 2 2006.257.19:46:56.27#ibcon#flushed, iclass 7, count 2 2006.257.19:46:56.27#ibcon#about to write, iclass 7, count 2 2006.257.19:46:56.27#ibcon#wrote, iclass 7, count 2 2006.257.19:46:56.27#ibcon#about to read 3, iclass 7, count 2 2006.257.19:46:56.30#ibcon#read 3, iclass 7, count 2 2006.257.19:46:56.30#ibcon#about to read 4, iclass 7, count 2 2006.257.19:46:56.30#ibcon#read 4, iclass 7, count 2 2006.257.19:46:56.30#ibcon#about to read 5, iclass 7, count 2 2006.257.19:46:56.30#ibcon#read 5, iclass 7, count 2 2006.257.19:46:56.30#ibcon#about to read 6, iclass 7, count 2 2006.257.19:46:56.30#ibcon#read 6, iclass 7, count 2 2006.257.19:46:56.30#ibcon#end of sib2, iclass 7, count 2 2006.257.19:46:56.30#ibcon#*after write, iclass 7, count 2 2006.257.19:46:56.30#ibcon#*before return 0, iclass 7, count 2 2006.257.19:46:56.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:56.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:56.30#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.19:46:56.30#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:56.30#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:56.42#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:56.42#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:56.42#ibcon#enter wrdev, iclass 7, count 0 2006.257.19:46:56.42#ibcon#first serial, iclass 7, count 0 2006.257.19:46:56.42#ibcon#enter sib2, iclass 7, count 0 2006.257.19:46:56.42#ibcon#flushed, iclass 7, count 0 2006.257.19:46:56.42#ibcon#about to write, iclass 7, count 0 2006.257.19:46:56.42#ibcon#wrote, iclass 7, count 0 2006.257.19:46:56.42#ibcon#about to read 3, iclass 7, count 0 2006.257.19:46:56.44#ibcon#read 3, iclass 7, count 0 2006.257.19:46:56.44#ibcon#about to read 4, iclass 7, count 0 2006.257.19:46:56.44#ibcon#read 4, iclass 7, count 0 2006.257.19:46:56.44#ibcon#about to read 5, iclass 7, count 0 2006.257.19:46:56.44#ibcon#read 5, iclass 7, count 0 2006.257.19:46:56.44#ibcon#about to read 6, iclass 7, count 0 2006.257.19:46:56.44#ibcon#read 6, iclass 7, count 0 2006.257.19:46:56.44#ibcon#end of sib2, iclass 7, count 0 2006.257.19:46:56.44#ibcon#*mode == 0, iclass 7, count 0 2006.257.19:46:56.44#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.19:46:56.44#ibcon#[25=USB\r\n] 2006.257.19:46:56.44#ibcon#*before write, iclass 7, count 0 2006.257.19:46:56.44#ibcon#enter sib2, iclass 7, count 0 2006.257.19:46:56.44#ibcon#flushed, iclass 7, count 0 2006.257.19:46:56.44#ibcon#about to write, iclass 7, count 0 2006.257.19:46:56.44#ibcon#wrote, iclass 7, count 0 2006.257.19:46:56.44#ibcon#about to read 3, iclass 7, count 0 2006.257.19:46:56.47#ibcon#read 3, iclass 7, count 0 2006.257.19:46:56.47#ibcon#about to read 4, iclass 7, count 0 2006.257.19:46:56.47#ibcon#read 4, iclass 7, count 0 2006.257.19:46:56.47#ibcon#about to read 5, iclass 7, count 0 2006.257.19:46:56.47#ibcon#read 5, iclass 7, count 0 2006.257.19:46:56.47#ibcon#about to read 6, iclass 7, count 0 2006.257.19:46:56.47#ibcon#read 6, iclass 7, count 0 2006.257.19:46:56.47#ibcon#end of sib2, iclass 7, count 0 2006.257.19:46:56.47#ibcon#*after write, iclass 7, count 0 2006.257.19:46:56.47#ibcon#*before return 0, iclass 7, count 0 2006.257.19:46:56.47#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:56.47#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:56.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.19:46:56.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.19:46:56.47$vck44/valo=7,864.99 2006.257.19:46:56.47#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.19:46:56.47#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.19:46:56.47#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:56.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:56.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:56.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:56.47#ibcon#enter wrdev, iclass 11, count 0 2006.257.19:46:56.47#ibcon#first serial, iclass 11, count 0 2006.257.19:46:56.47#ibcon#enter sib2, iclass 11, count 0 2006.257.19:46:56.47#ibcon#flushed, iclass 11, count 0 2006.257.19:46:56.47#ibcon#about to write, iclass 11, count 0 2006.257.19:46:56.47#ibcon#wrote, iclass 11, count 0 2006.257.19:46:56.47#ibcon#about to read 3, iclass 11, count 0 2006.257.19:46:56.49#ibcon#read 3, iclass 11, count 0 2006.257.19:46:56.49#ibcon#about to read 4, iclass 11, count 0 2006.257.19:46:56.49#ibcon#read 4, iclass 11, count 0 2006.257.19:46:56.49#ibcon#about to read 5, iclass 11, count 0 2006.257.19:46:56.49#ibcon#read 5, iclass 11, count 0 2006.257.19:46:56.49#ibcon#about to read 6, iclass 11, count 0 2006.257.19:46:56.49#ibcon#read 6, iclass 11, count 0 2006.257.19:46:56.49#ibcon#end of sib2, iclass 11, count 0 2006.257.19:46:56.49#ibcon#*mode == 0, iclass 11, count 0 2006.257.19:46:56.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.19:46:56.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.19:46:56.49#ibcon#*before write, iclass 11, count 0 2006.257.19:46:56.49#ibcon#enter sib2, iclass 11, count 0 2006.257.19:46:56.49#ibcon#flushed, iclass 11, count 0 2006.257.19:46:56.49#ibcon#about to write, iclass 11, count 0 2006.257.19:46:56.49#ibcon#wrote, iclass 11, count 0 2006.257.19:46:56.49#ibcon#about to read 3, iclass 11, count 0 2006.257.19:46:56.53#ibcon#read 3, iclass 11, count 0 2006.257.19:46:56.53#ibcon#about to read 4, iclass 11, count 0 2006.257.19:46:56.53#ibcon#read 4, iclass 11, count 0 2006.257.19:46:56.53#ibcon#about to read 5, iclass 11, count 0 2006.257.19:46:56.53#ibcon#read 5, iclass 11, count 0 2006.257.19:46:56.53#ibcon#about to read 6, iclass 11, count 0 2006.257.19:46:56.53#ibcon#read 6, iclass 11, count 0 2006.257.19:46:56.53#ibcon#end of sib2, iclass 11, count 0 2006.257.19:46:56.53#ibcon#*after write, iclass 11, count 0 2006.257.19:46:56.53#ibcon#*before return 0, iclass 11, count 0 2006.257.19:46:56.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:56.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:56.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.19:46:56.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.19:46:56.53$vck44/va=7,4 2006.257.19:46:56.53#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.19:46:56.53#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.19:46:56.53#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:56.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:56.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:56.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:56.59#ibcon#enter wrdev, iclass 13, count 2 2006.257.19:46:56.59#ibcon#first serial, iclass 13, count 2 2006.257.19:46:56.59#ibcon#enter sib2, iclass 13, count 2 2006.257.19:46:56.59#ibcon#flushed, iclass 13, count 2 2006.257.19:46:56.59#ibcon#about to write, iclass 13, count 2 2006.257.19:46:56.59#ibcon#wrote, iclass 13, count 2 2006.257.19:46:56.59#ibcon#about to read 3, iclass 13, count 2 2006.257.19:46:56.61#ibcon#read 3, iclass 13, count 2 2006.257.19:46:56.61#ibcon#about to read 4, iclass 13, count 2 2006.257.19:46:56.61#ibcon#read 4, iclass 13, count 2 2006.257.19:46:56.61#ibcon#about to read 5, iclass 13, count 2 2006.257.19:46:56.61#ibcon#read 5, iclass 13, count 2 2006.257.19:46:56.61#ibcon#about to read 6, iclass 13, count 2 2006.257.19:46:56.61#ibcon#read 6, iclass 13, count 2 2006.257.19:46:56.61#ibcon#end of sib2, iclass 13, count 2 2006.257.19:46:56.61#ibcon#*mode == 0, iclass 13, count 2 2006.257.19:46:56.61#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.19:46:56.61#ibcon#[25=AT07-04\r\n] 2006.257.19:46:56.61#ibcon#*before write, iclass 13, count 2 2006.257.19:46:56.61#ibcon#enter sib2, iclass 13, count 2 2006.257.19:46:56.61#ibcon#flushed, iclass 13, count 2 2006.257.19:46:56.61#ibcon#about to write, iclass 13, count 2 2006.257.19:46:56.61#ibcon#wrote, iclass 13, count 2 2006.257.19:46:56.61#ibcon#about to read 3, iclass 13, count 2 2006.257.19:46:56.64#ibcon#read 3, iclass 13, count 2 2006.257.19:46:56.64#ibcon#about to read 4, iclass 13, count 2 2006.257.19:46:56.64#ibcon#read 4, iclass 13, count 2 2006.257.19:46:56.64#ibcon#about to read 5, iclass 13, count 2 2006.257.19:46:56.64#ibcon#read 5, iclass 13, count 2 2006.257.19:46:56.64#ibcon#about to read 6, iclass 13, count 2 2006.257.19:46:56.64#ibcon#read 6, iclass 13, count 2 2006.257.19:46:56.64#ibcon#end of sib2, iclass 13, count 2 2006.257.19:46:56.64#ibcon#*after write, iclass 13, count 2 2006.257.19:46:56.64#ibcon#*before return 0, iclass 13, count 2 2006.257.19:46:56.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:56.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:56.64#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.19:46:56.64#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:56.64#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:56.76#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:56.76#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:56.76#ibcon#enter wrdev, iclass 13, count 0 2006.257.19:46:56.76#ibcon#first serial, iclass 13, count 0 2006.257.19:46:56.76#ibcon#enter sib2, iclass 13, count 0 2006.257.19:46:56.76#ibcon#flushed, iclass 13, count 0 2006.257.19:46:56.76#ibcon#about to write, iclass 13, count 0 2006.257.19:46:56.76#ibcon#wrote, iclass 13, count 0 2006.257.19:46:56.76#ibcon#about to read 3, iclass 13, count 0 2006.257.19:46:56.78#ibcon#read 3, iclass 13, count 0 2006.257.19:46:56.78#ibcon#about to read 4, iclass 13, count 0 2006.257.19:46:56.78#ibcon#read 4, iclass 13, count 0 2006.257.19:46:56.78#ibcon#about to read 5, iclass 13, count 0 2006.257.19:46:56.78#ibcon#read 5, iclass 13, count 0 2006.257.19:46:56.78#ibcon#about to read 6, iclass 13, count 0 2006.257.19:46:56.78#ibcon#read 6, iclass 13, count 0 2006.257.19:46:56.78#ibcon#end of sib2, iclass 13, count 0 2006.257.19:46:56.78#ibcon#*mode == 0, iclass 13, count 0 2006.257.19:46:56.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.19:46:56.78#ibcon#[25=USB\r\n] 2006.257.19:46:56.78#ibcon#*before write, iclass 13, count 0 2006.257.19:46:56.78#ibcon#enter sib2, iclass 13, count 0 2006.257.19:46:56.78#ibcon#flushed, iclass 13, count 0 2006.257.19:46:56.78#ibcon#about to write, iclass 13, count 0 2006.257.19:46:56.78#ibcon#wrote, iclass 13, count 0 2006.257.19:46:56.78#ibcon#about to read 3, iclass 13, count 0 2006.257.19:46:56.81#ibcon#read 3, iclass 13, count 0 2006.257.19:46:56.81#ibcon#about to read 4, iclass 13, count 0 2006.257.19:46:56.81#ibcon#read 4, iclass 13, count 0 2006.257.19:46:56.81#ibcon#about to read 5, iclass 13, count 0 2006.257.19:46:56.81#ibcon#read 5, iclass 13, count 0 2006.257.19:46:56.81#ibcon#about to read 6, iclass 13, count 0 2006.257.19:46:56.81#ibcon#read 6, iclass 13, count 0 2006.257.19:46:56.81#ibcon#end of sib2, iclass 13, count 0 2006.257.19:46:56.81#ibcon#*after write, iclass 13, count 0 2006.257.19:46:56.81#ibcon#*before return 0, iclass 13, count 0 2006.257.19:46:56.81#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:56.81#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:56.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.19:46:56.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.19:46:56.81$vck44/valo=8,884.99 2006.257.19:46:56.81#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.19:46:56.81#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.19:46:56.81#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:56.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:56.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:56.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:56.81#ibcon#enter wrdev, iclass 15, count 0 2006.257.19:46:56.81#ibcon#first serial, iclass 15, count 0 2006.257.19:46:56.81#ibcon#enter sib2, iclass 15, count 0 2006.257.19:46:56.81#ibcon#flushed, iclass 15, count 0 2006.257.19:46:56.81#ibcon#about to write, iclass 15, count 0 2006.257.19:46:56.81#ibcon#wrote, iclass 15, count 0 2006.257.19:46:56.81#ibcon#about to read 3, iclass 15, count 0 2006.257.19:46:56.83#ibcon#read 3, iclass 15, count 0 2006.257.19:46:56.83#ibcon#about to read 4, iclass 15, count 0 2006.257.19:46:56.83#ibcon#read 4, iclass 15, count 0 2006.257.19:46:56.83#ibcon#about to read 5, iclass 15, count 0 2006.257.19:46:56.83#ibcon#read 5, iclass 15, count 0 2006.257.19:46:56.83#ibcon#about to read 6, iclass 15, count 0 2006.257.19:46:56.83#ibcon#read 6, iclass 15, count 0 2006.257.19:46:56.83#ibcon#end of sib2, iclass 15, count 0 2006.257.19:46:56.83#ibcon#*mode == 0, iclass 15, count 0 2006.257.19:46:56.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.19:46:56.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.19:46:56.83#ibcon#*before write, iclass 15, count 0 2006.257.19:46:56.83#ibcon#enter sib2, iclass 15, count 0 2006.257.19:46:56.83#ibcon#flushed, iclass 15, count 0 2006.257.19:46:56.83#ibcon#about to write, iclass 15, count 0 2006.257.19:46:56.83#ibcon#wrote, iclass 15, count 0 2006.257.19:46:56.83#ibcon#about to read 3, iclass 15, count 0 2006.257.19:46:56.87#ibcon#read 3, iclass 15, count 0 2006.257.19:46:56.87#ibcon#about to read 4, iclass 15, count 0 2006.257.19:46:56.87#ibcon#read 4, iclass 15, count 0 2006.257.19:46:56.87#ibcon#about to read 5, iclass 15, count 0 2006.257.19:46:56.87#ibcon#read 5, iclass 15, count 0 2006.257.19:46:56.87#ibcon#about to read 6, iclass 15, count 0 2006.257.19:46:56.87#ibcon#read 6, iclass 15, count 0 2006.257.19:46:56.87#ibcon#end of sib2, iclass 15, count 0 2006.257.19:46:56.87#ibcon#*after write, iclass 15, count 0 2006.257.19:46:56.87#ibcon#*before return 0, iclass 15, count 0 2006.257.19:46:56.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:56.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:56.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.19:46:56.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.19:46:56.87$vck44/va=8,4 2006.257.19:46:56.87#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.19:46:56.87#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.19:46:56.87#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:56.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.19:46:56.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.19:46:56.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.19:46:56.93#ibcon#enter wrdev, iclass 17, count 2 2006.257.19:46:56.93#ibcon#first serial, iclass 17, count 2 2006.257.19:46:56.93#ibcon#enter sib2, iclass 17, count 2 2006.257.19:46:56.93#ibcon#flushed, iclass 17, count 2 2006.257.19:46:56.93#ibcon#about to write, iclass 17, count 2 2006.257.19:46:56.93#ibcon#wrote, iclass 17, count 2 2006.257.19:46:56.93#ibcon#about to read 3, iclass 17, count 2 2006.257.19:46:56.95#ibcon#read 3, iclass 17, count 2 2006.257.19:46:56.95#ibcon#about to read 4, iclass 17, count 2 2006.257.19:46:56.95#ibcon#read 4, iclass 17, count 2 2006.257.19:46:56.95#ibcon#about to read 5, iclass 17, count 2 2006.257.19:46:56.95#ibcon#read 5, iclass 17, count 2 2006.257.19:46:56.95#ibcon#about to read 6, iclass 17, count 2 2006.257.19:46:56.95#ibcon#read 6, iclass 17, count 2 2006.257.19:46:56.95#ibcon#end of sib2, iclass 17, count 2 2006.257.19:46:56.95#ibcon#*mode == 0, iclass 17, count 2 2006.257.19:46:56.95#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.19:46:56.95#ibcon#[25=AT08-04\r\n] 2006.257.19:46:56.95#ibcon#*before write, iclass 17, count 2 2006.257.19:46:56.95#ibcon#enter sib2, iclass 17, count 2 2006.257.19:46:56.95#ibcon#flushed, iclass 17, count 2 2006.257.19:46:56.95#ibcon#about to write, iclass 17, count 2 2006.257.19:46:56.95#ibcon#wrote, iclass 17, count 2 2006.257.19:46:56.95#ibcon#about to read 3, iclass 17, count 2 2006.257.19:46:56.98#ibcon#read 3, iclass 17, count 2 2006.257.19:46:56.98#ibcon#about to read 4, iclass 17, count 2 2006.257.19:46:56.98#ibcon#read 4, iclass 17, count 2 2006.257.19:46:56.98#ibcon#about to read 5, iclass 17, count 2 2006.257.19:46:56.98#ibcon#read 5, iclass 17, count 2 2006.257.19:46:56.98#ibcon#about to read 6, iclass 17, count 2 2006.257.19:46:56.98#ibcon#read 6, iclass 17, count 2 2006.257.19:46:56.98#ibcon#end of sib2, iclass 17, count 2 2006.257.19:46:56.98#ibcon#*after write, iclass 17, count 2 2006.257.19:46:56.98#ibcon#*before return 0, iclass 17, count 2 2006.257.19:46:56.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.19:46:56.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.19:46:56.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.19:46:56.98#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:56.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.19:46:57.10#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.19:46:57.10#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.19:46:57.10#ibcon#enter wrdev, iclass 17, count 0 2006.257.19:46:57.10#ibcon#first serial, iclass 17, count 0 2006.257.19:46:57.10#ibcon#enter sib2, iclass 17, count 0 2006.257.19:46:57.10#ibcon#flushed, iclass 17, count 0 2006.257.19:46:57.10#ibcon#about to write, iclass 17, count 0 2006.257.19:46:57.10#ibcon#wrote, iclass 17, count 0 2006.257.19:46:57.10#ibcon#about to read 3, iclass 17, count 0 2006.257.19:46:57.12#ibcon#read 3, iclass 17, count 0 2006.257.19:46:57.12#ibcon#about to read 4, iclass 17, count 0 2006.257.19:46:57.12#ibcon#read 4, iclass 17, count 0 2006.257.19:46:57.12#ibcon#about to read 5, iclass 17, count 0 2006.257.19:46:57.12#ibcon#read 5, iclass 17, count 0 2006.257.19:46:57.12#ibcon#about to read 6, iclass 17, count 0 2006.257.19:46:57.12#ibcon#read 6, iclass 17, count 0 2006.257.19:46:57.12#ibcon#end of sib2, iclass 17, count 0 2006.257.19:46:57.12#ibcon#*mode == 0, iclass 17, count 0 2006.257.19:46:57.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.19:46:57.12#ibcon#[25=USB\r\n] 2006.257.19:46:57.12#ibcon#*before write, iclass 17, count 0 2006.257.19:46:57.12#ibcon#enter sib2, iclass 17, count 0 2006.257.19:46:57.12#ibcon#flushed, iclass 17, count 0 2006.257.19:46:57.12#ibcon#about to write, iclass 17, count 0 2006.257.19:46:57.12#ibcon#wrote, iclass 17, count 0 2006.257.19:46:57.12#ibcon#about to read 3, iclass 17, count 0 2006.257.19:46:57.15#ibcon#read 3, iclass 17, count 0 2006.257.19:46:57.15#ibcon#about to read 4, iclass 17, count 0 2006.257.19:46:57.15#ibcon#read 4, iclass 17, count 0 2006.257.19:46:57.15#ibcon#about to read 5, iclass 17, count 0 2006.257.19:46:57.15#ibcon#read 5, iclass 17, count 0 2006.257.19:46:57.15#ibcon#about to read 6, iclass 17, count 0 2006.257.19:46:57.15#ibcon#read 6, iclass 17, count 0 2006.257.19:46:57.15#ibcon#end of sib2, iclass 17, count 0 2006.257.19:46:57.15#ibcon#*after write, iclass 17, count 0 2006.257.19:46:57.15#ibcon#*before return 0, iclass 17, count 0 2006.257.19:46:57.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.19:46:57.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.19:46:57.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.19:46:57.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.19:46:57.15$vck44/vblo=1,629.99 2006.257.19:46:57.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.19:46:57.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.19:46:57.15#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:57.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.19:46:57.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.19:46:57.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.19:46:57.15#ibcon#enter wrdev, iclass 19, count 0 2006.257.19:46:57.15#ibcon#first serial, iclass 19, count 0 2006.257.19:46:57.15#ibcon#enter sib2, iclass 19, count 0 2006.257.19:46:57.15#ibcon#flushed, iclass 19, count 0 2006.257.19:46:57.15#ibcon#about to write, iclass 19, count 0 2006.257.19:46:57.15#ibcon#wrote, iclass 19, count 0 2006.257.19:46:57.15#ibcon#about to read 3, iclass 19, count 0 2006.257.19:46:57.17#ibcon#read 3, iclass 19, count 0 2006.257.19:46:57.17#ibcon#about to read 4, iclass 19, count 0 2006.257.19:46:57.17#ibcon#read 4, iclass 19, count 0 2006.257.19:46:57.17#ibcon#about to read 5, iclass 19, count 0 2006.257.19:46:57.17#ibcon#read 5, iclass 19, count 0 2006.257.19:46:57.17#ibcon#about to read 6, iclass 19, count 0 2006.257.19:46:57.17#ibcon#read 6, iclass 19, count 0 2006.257.19:46:57.17#ibcon#end of sib2, iclass 19, count 0 2006.257.19:46:57.17#ibcon#*mode == 0, iclass 19, count 0 2006.257.19:46:57.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.19:46:57.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.19:46:57.17#ibcon#*before write, iclass 19, count 0 2006.257.19:46:57.17#ibcon#enter sib2, iclass 19, count 0 2006.257.19:46:57.17#ibcon#flushed, iclass 19, count 0 2006.257.19:46:57.17#ibcon#about to write, iclass 19, count 0 2006.257.19:46:57.17#ibcon#wrote, iclass 19, count 0 2006.257.19:46:57.17#ibcon#about to read 3, iclass 19, count 0 2006.257.19:46:57.21#ibcon#read 3, iclass 19, count 0 2006.257.19:46:57.21#ibcon#about to read 4, iclass 19, count 0 2006.257.19:46:57.21#ibcon#read 4, iclass 19, count 0 2006.257.19:46:57.21#ibcon#about to read 5, iclass 19, count 0 2006.257.19:46:57.21#ibcon#read 5, iclass 19, count 0 2006.257.19:46:57.21#ibcon#about to read 6, iclass 19, count 0 2006.257.19:46:57.21#ibcon#read 6, iclass 19, count 0 2006.257.19:46:57.21#ibcon#end of sib2, iclass 19, count 0 2006.257.19:46:57.21#ibcon#*after write, iclass 19, count 0 2006.257.19:46:57.21#ibcon#*before return 0, iclass 19, count 0 2006.257.19:46:57.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.19:46:57.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.19:46:57.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.19:46:57.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.19:46:57.21$vck44/vb=1,4 2006.257.19:46:57.21#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.19:46:57.21#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.19:46:57.21#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:57.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.19:46:57.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.19:46:57.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.19:46:57.21#ibcon#enter wrdev, iclass 21, count 2 2006.257.19:46:57.21#ibcon#first serial, iclass 21, count 2 2006.257.19:46:57.21#ibcon#enter sib2, iclass 21, count 2 2006.257.19:46:57.21#ibcon#flushed, iclass 21, count 2 2006.257.19:46:57.21#ibcon#about to write, iclass 21, count 2 2006.257.19:46:57.21#ibcon#wrote, iclass 21, count 2 2006.257.19:46:57.21#ibcon#about to read 3, iclass 21, count 2 2006.257.19:46:57.23#ibcon#read 3, iclass 21, count 2 2006.257.19:46:57.23#ibcon#about to read 4, iclass 21, count 2 2006.257.19:46:57.23#ibcon#read 4, iclass 21, count 2 2006.257.19:46:57.23#ibcon#about to read 5, iclass 21, count 2 2006.257.19:46:57.23#ibcon#read 5, iclass 21, count 2 2006.257.19:46:57.23#ibcon#about to read 6, iclass 21, count 2 2006.257.19:46:57.23#ibcon#read 6, iclass 21, count 2 2006.257.19:46:57.23#ibcon#end of sib2, iclass 21, count 2 2006.257.19:46:57.23#ibcon#*mode == 0, iclass 21, count 2 2006.257.19:46:57.23#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.19:46:57.23#ibcon#[27=AT01-04\r\n] 2006.257.19:46:57.23#ibcon#*before write, iclass 21, count 2 2006.257.19:46:57.23#ibcon#enter sib2, iclass 21, count 2 2006.257.19:46:57.23#ibcon#flushed, iclass 21, count 2 2006.257.19:46:57.23#ibcon#about to write, iclass 21, count 2 2006.257.19:46:57.23#ibcon#wrote, iclass 21, count 2 2006.257.19:46:57.23#ibcon#about to read 3, iclass 21, count 2 2006.257.19:46:57.26#ibcon#read 3, iclass 21, count 2 2006.257.19:46:57.26#ibcon#about to read 4, iclass 21, count 2 2006.257.19:46:57.26#ibcon#read 4, iclass 21, count 2 2006.257.19:46:57.26#ibcon#about to read 5, iclass 21, count 2 2006.257.19:46:57.26#ibcon#read 5, iclass 21, count 2 2006.257.19:46:57.26#ibcon#about to read 6, iclass 21, count 2 2006.257.19:46:57.26#ibcon#read 6, iclass 21, count 2 2006.257.19:46:57.26#ibcon#end of sib2, iclass 21, count 2 2006.257.19:46:57.26#ibcon#*after write, iclass 21, count 2 2006.257.19:46:57.26#ibcon#*before return 0, iclass 21, count 2 2006.257.19:46:57.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.19:46:57.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.19:46:57.26#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.19:46:57.26#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:57.26#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.19:46:57.38#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.19:46:57.38#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.19:46:57.38#ibcon#enter wrdev, iclass 21, count 0 2006.257.19:46:57.38#ibcon#first serial, iclass 21, count 0 2006.257.19:46:57.38#ibcon#enter sib2, iclass 21, count 0 2006.257.19:46:57.38#ibcon#flushed, iclass 21, count 0 2006.257.19:46:57.38#ibcon#about to write, iclass 21, count 0 2006.257.19:46:57.38#ibcon#wrote, iclass 21, count 0 2006.257.19:46:57.38#ibcon#about to read 3, iclass 21, count 0 2006.257.19:46:57.40#ibcon#read 3, iclass 21, count 0 2006.257.19:46:57.40#ibcon#about to read 4, iclass 21, count 0 2006.257.19:46:57.40#ibcon#read 4, iclass 21, count 0 2006.257.19:46:57.40#ibcon#about to read 5, iclass 21, count 0 2006.257.19:46:57.40#ibcon#read 5, iclass 21, count 0 2006.257.19:46:57.40#ibcon#about to read 6, iclass 21, count 0 2006.257.19:46:57.40#ibcon#read 6, iclass 21, count 0 2006.257.19:46:57.40#ibcon#end of sib2, iclass 21, count 0 2006.257.19:46:57.40#ibcon#*mode == 0, iclass 21, count 0 2006.257.19:46:57.40#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.19:46:57.40#ibcon#[27=USB\r\n] 2006.257.19:46:57.40#ibcon#*before write, iclass 21, count 0 2006.257.19:46:57.40#ibcon#enter sib2, iclass 21, count 0 2006.257.19:46:57.40#ibcon#flushed, iclass 21, count 0 2006.257.19:46:57.40#ibcon#about to write, iclass 21, count 0 2006.257.19:46:57.40#ibcon#wrote, iclass 21, count 0 2006.257.19:46:57.40#ibcon#about to read 3, iclass 21, count 0 2006.257.19:46:57.43#ibcon#read 3, iclass 21, count 0 2006.257.19:46:57.43#ibcon#about to read 4, iclass 21, count 0 2006.257.19:46:57.43#ibcon#read 4, iclass 21, count 0 2006.257.19:46:57.43#ibcon#about to read 5, iclass 21, count 0 2006.257.19:46:57.43#ibcon#read 5, iclass 21, count 0 2006.257.19:46:57.43#ibcon#about to read 6, iclass 21, count 0 2006.257.19:46:57.43#ibcon#read 6, iclass 21, count 0 2006.257.19:46:57.43#ibcon#end of sib2, iclass 21, count 0 2006.257.19:46:57.43#ibcon#*after write, iclass 21, count 0 2006.257.19:46:57.43#ibcon#*before return 0, iclass 21, count 0 2006.257.19:46:57.43#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.19:46:57.43#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.19:46:57.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.19:46:57.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.19:46:57.43$vck44/vblo=2,634.99 2006.257.19:46:57.43#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.19:46:57.43#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.19:46:57.43#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:57.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:57.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:57.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:57.43#ibcon#enter wrdev, iclass 23, count 0 2006.257.19:46:57.43#ibcon#first serial, iclass 23, count 0 2006.257.19:46:57.43#ibcon#enter sib2, iclass 23, count 0 2006.257.19:46:57.43#ibcon#flushed, iclass 23, count 0 2006.257.19:46:57.43#ibcon#about to write, iclass 23, count 0 2006.257.19:46:57.43#ibcon#wrote, iclass 23, count 0 2006.257.19:46:57.43#ibcon#about to read 3, iclass 23, count 0 2006.257.19:46:57.45#ibcon#read 3, iclass 23, count 0 2006.257.19:46:57.45#ibcon#about to read 4, iclass 23, count 0 2006.257.19:46:57.45#ibcon#read 4, iclass 23, count 0 2006.257.19:46:57.45#ibcon#about to read 5, iclass 23, count 0 2006.257.19:46:57.45#ibcon#read 5, iclass 23, count 0 2006.257.19:46:57.45#ibcon#about to read 6, iclass 23, count 0 2006.257.19:46:57.45#ibcon#read 6, iclass 23, count 0 2006.257.19:46:57.45#ibcon#end of sib2, iclass 23, count 0 2006.257.19:46:57.45#ibcon#*mode == 0, iclass 23, count 0 2006.257.19:46:57.45#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.19:46:57.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.19:46:57.45#ibcon#*before write, iclass 23, count 0 2006.257.19:46:57.45#ibcon#enter sib2, iclass 23, count 0 2006.257.19:46:57.45#ibcon#flushed, iclass 23, count 0 2006.257.19:46:57.45#ibcon#about to write, iclass 23, count 0 2006.257.19:46:57.45#ibcon#wrote, iclass 23, count 0 2006.257.19:46:57.45#ibcon#about to read 3, iclass 23, count 0 2006.257.19:46:57.49#ibcon#read 3, iclass 23, count 0 2006.257.19:46:57.49#ibcon#about to read 4, iclass 23, count 0 2006.257.19:46:57.49#ibcon#read 4, iclass 23, count 0 2006.257.19:46:57.49#ibcon#about to read 5, iclass 23, count 0 2006.257.19:46:57.49#ibcon#read 5, iclass 23, count 0 2006.257.19:46:57.49#ibcon#about to read 6, iclass 23, count 0 2006.257.19:46:57.49#ibcon#read 6, iclass 23, count 0 2006.257.19:46:57.49#ibcon#end of sib2, iclass 23, count 0 2006.257.19:46:57.49#ibcon#*after write, iclass 23, count 0 2006.257.19:46:57.49#ibcon#*before return 0, iclass 23, count 0 2006.257.19:46:57.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:57.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.19:46:57.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.19:46:57.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.19:46:57.49$vck44/vb=2,5 2006.257.19:46:57.49#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.19:46:57.49#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.19:46:57.49#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:57.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:57.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:57.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:57.55#ibcon#enter wrdev, iclass 25, count 2 2006.257.19:46:57.55#ibcon#first serial, iclass 25, count 2 2006.257.19:46:57.55#ibcon#enter sib2, iclass 25, count 2 2006.257.19:46:57.55#ibcon#flushed, iclass 25, count 2 2006.257.19:46:57.55#ibcon#about to write, iclass 25, count 2 2006.257.19:46:57.55#ibcon#wrote, iclass 25, count 2 2006.257.19:46:57.55#ibcon#about to read 3, iclass 25, count 2 2006.257.19:46:57.57#ibcon#read 3, iclass 25, count 2 2006.257.19:46:57.57#ibcon#about to read 4, iclass 25, count 2 2006.257.19:46:57.57#ibcon#read 4, iclass 25, count 2 2006.257.19:46:57.57#ibcon#about to read 5, iclass 25, count 2 2006.257.19:46:57.57#ibcon#read 5, iclass 25, count 2 2006.257.19:46:57.57#ibcon#about to read 6, iclass 25, count 2 2006.257.19:46:57.57#ibcon#read 6, iclass 25, count 2 2006.257.19:46:57.57#ibcon#end of sib2, iclass 25, count 2 2006.257.19:46:57.57#ibcon#*mode == 0, iclass 25, count 2 2006.257.19:46:57.57#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.19:46:57.57#ibcon#[27=AT02-05\r\n] 2006.257.19:46:57.57#ibcon#*before write, iclass 25, count 2 2006.257.19:46:57.57#ibcon#enter sib2, iclass 25, count 2 2006.257.19:46:57.57#ibcon#flushed, iclass 25, count 2 2006.257.19:46:57.57#ibcon#about to write, iclass 25, count 2 2006.257.19:46:57.57#ibcon#wrote, iclass 25, count 2 2006.257.19:46:57.57#ibcon#about to read 3, iclass 25, count 2 2006.257.19:46:57.60#ibcon#read 3, iclass 25, count 2 2006.257.19:46:57.60#ibcon#about to read 4, iclass 25, count 2 2006.257.19:46:57.60#ibcon#read 4, iclass 25, count 2 2006.257.19:46:57.60#ibcon#about to read 5, iclass 25, count 2 2006.257.19:46:57.60#ibcon#read 5, iclass 25, count 2 2006.257.19:46:57.60#ibcon#about to read 6, iclass 25, count 2 2006.257.19:46:57.60#ibcon#read 6, iclass 25, count 2 2006.257.19:46:57.60#ibcon#end of sib2, iclass 25, count 2 2006.257.19:46:57.60#ibcon#*after write, iclass 25, count 2 2006.257.19:46:57.60#ibcon#*before return 0, iclass 25, count 2 2006.257.19:46:57.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:57.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.19:46:57.60#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.19:46:57.60#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:57.60#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:57.72#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:57.72#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:57.72#ibcon#enter wrdev, iclass 25, count 0 2006.257.19:46:57.72#ibcon#first serial, iclass 25, count 0 2006.257.19:46:57.72#ibcon#enter sib2, iclass 25, count 0 2006.257.19:46:57.72#ibcon#flushed, iclass 25, count 0 2006.257.19:46:57.72#ibcon#about to write, iclass 25, count 0 2006.257.19:46:57.72#ibcon#wrote, iclass 25, count 0 2006.257.19:46:57.72#ibcon#about to read 3, iclass 25, count 0 2006.257.19:46:57.74#ibcon#read 3, iclass 25, count 0 2006.257.19:46:57.74#ibcon#about to read 4, iclass 25, count 0 2006.257.19:46:57.74#ibcon#read 4, iclass 25, count 0 2006.257.19:46:57.74#ibcon#about to read 5, iclass 25, count 0 2006.257.19:46:57.74#ibcon#read 5, iclass 25, count 0 2006.257.19:46:57.74#ibcon#about to read 6, iclass 25, count 0 2006.257.19:46:57.74#ibcon#read 6, iclass 25, count 0 2006.257.19:46:57.74#ibcon#end of sib2, iclass 25, count 0 2006.257.19:46:57.74#ibcon#*mode == 0, iclass 25, count 0 2006.257.19:46:57.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.19:46:57.74#ibcon#[27=USB\r\n] 2006.257.19:46:57.74#ibcon#*before write, iclass 25, count 0 2006.257.19:46:57.74#ibcon#enter sib2, iclass 25, count 0 2006.257.19:46:57.74#ibcon#flushed, iclass 25, count 0 2006.257.19:46:57.74#ibcon#about to write, iclass 25, count 0 2006.257.19:46:57.74#ibcon#wrote, iclass 25, count 0 2006.257.19:46:57.74#ibcon#about to read 3, iclass 25, count 0 2006.257.19:46:57.77#ibcon#read 3, iclass 25, count 0 2006.257.19:46:57.77#ibcon#about to read 4, iclass 25, count 0 2006.257.19:46:57.77#ibcon#read 4, iclass 25, count 0 2006.257.19:46:57.77#ibcon#about to read 5, iclass 25, count 0 2006.257.19:46:57.77#ibcon#read 5, iclass 25, count 0 2006.257.19:46:57.77#ibcon#about to read 6, iclass 25, count 0 2006.257.19:46:57.77#ibcon#read 6, iclass 25, count 0 2006.257.19:46:57.77#ibcon#end of sib2, iclass 25, count 0 2006.257.19:46:57.77#ibcon#*after write, iclass 25, count 0 2006.257.19:46:57.77#ibcon#*before return 0, iclass 25, count 0 2006.257.19:46:57.77#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:57.77#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.19:46:57.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.19:46:57.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.19:46:57.77$vck44/vblo=3,649.99 2006.257.19:46:57.77#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.19:46:57.77#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.19:46:57.77#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:57.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:57.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:57.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:57.77#ibcon#enter wrdev, iclass 27, count 0 2006.257.19:46:57.77#ibcon#first serial, iclass 27, count 0 2006.257.19:46:57.77#ibcon#enter sib2, iclass 27, count 0 2006.257.19:46:57.77#ibcon#flushed, iclass 27, count 0 2006.257.19:46:57.77#ibcon#about to write, iclass 27, count 0 2006.257.19:46:57.77#ibcon#wrote, iclass 27, count 0 2006.257.19:46:57.77#ibcon#about to read 3, iclass 27, count 0 2006.257.19:46:57.79#ibcon#read 3, iclass 27, count 0 2006.257.19:46:57.79#ibcon#about to read 4, iclass 27, count 0 2006.257.19:46:57.79#ibcon#read 4, iclass 27, count 0 2006.257.19:46:57.79#ibcon#about to read 5, iclass 27, count 0 2006.257.19:46:57.79#ibcon#read 5, iclass 27, count 0 2006.257.19:46:57.79#ibcon#about to read 6, iclass 27, count 0 2006.257.19:46:57.79#ibcon#read 6, iclass 27, count 0 2006.257.19:46:57.79#ibcon#end of sib2, iclass 27, count 0 2006.257.19:46:57.79#ibcon#*mode == 0, iclass 27, count 0 2006.257.19:46:57.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.19:46:57.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.19:46:57.79#ibcon#*before write, iclass 27, count 0 2006.257.19:46:57.79#ibcon#enter sib2, iclass 27, count 0 2006.257.19:46:57.79#ibcon#flushed, iclass 27, count 0 2006.257.19:46:57.79#ibcon#about to write, iclass 27, count 0 2006.257.19:46:57.79#ibcon#wrote, iclass 27, count 0 2006.257.19:46:57.79#ibcon#about to read 3, iclass 27, count 0 2006.257.19:46:57.83#ibcon#read 3, iclass 27, count 0 2006.257.19:46:57.83#ibcon#about to read 4, iclass 27, count 0 2006.257.19:46:57.83#ibcon#read 4, iclass 27, count 0 2006.257.19:46:57.83#ibcon#about to read 5, iclass 27, count 0 2006.257.19:46:57.83#ibcon#read 5, iclass 27, count 0 2006.257.19:46:57.83#ibcon#about to read 6, iclass 27, count 0 2006.257.19:46:57.83#ibcon#read 6, iclass 27, count 0 2006.257.19:46:57.83#ibcon#end of sib2, iclass 27, count 0 2006.257.19:46:57.83#ibcon#*after write, iclass 27, count 0 2006.257.19:46:57.83#ibcon#*before return 0, iclass 27, count 0 2006.257.19:46:57.83#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:57.83#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.19:46:57.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.19:46:57.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.19:46:57.83$vck44/vb=3,4 2006.257.19:46:57.83#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.19:46:57.83#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.19:46:57.83#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:57.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:57.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:57.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:57.89#ibcon#enter wrdev, iclass 29, count 2 2006.257.19:46:57.89#ibcon#first serial, iclass 29, count 2 2006.257.19:46:57.89#ibcon#enter sib2, iclass 29, count 2 2006.257.19:46:57.89#ibcon#flushed, iclass 29, count 2 2006.257.19:46:57.89#ibcon#about to write, iclass 29, count 2 2006.257.19:46:57.89#ibcon#wrote, iclass 29, count 2 2006.257.19:46:57.89#ibcon#about to read 3, iclass 29, count 2 2006.257.19:46:57.91#ibcon#read 3, iclass 29, count 2 2006.257.19:46:57.91#ibcon#about to read 4, iclass 29, count 2 2006.257.19:46:57.91#ibcon#read 4, iclass 29, count 2 2006.257.19:46:57.91#ibcon#about to read 5, iclass 29, count 2 2006.257.19:46:57.91#ibcon#read 5, iclass 29, count 2 2006.257.19:46:57.91#ibcon#about to read 6, iclass 29, count 2 2006.257.19:46:57.91#ibcon#read 6, iclass 29, count 2 2006.257.19:46:57.91#ibcon#end of sib2, iclass 29, count 2 2006.257.19:46:57.91#ibcon#*mode == 0, iclass 29, count 2 2006.257.19:46:57.91#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.19:46:57.91#ibcon#[27=AT03-04\r\n] 2006.257.19:46:57.91#ibcon#*before write, iclass 29, count 2 2006.257.19:46:57.91#ibcon#enter sib2, iclass 29, count 2 2006.257.19:46:57.91#ibcon#flushed, iclass 29, count 2 2006.257.19:46:57.91#ibcon#about to write, iclass 29, count 2 2006.257.19:46:57.91#ibcon#wrote, iclass 29, count 2 2006.257.19:46:57.91#ibcon#about to read 3, iclass 29, count 2 2006.257.19:46:57.94#ibcon#read 3, iclass 29, count 2 2006.257.19:46:57.94#ibcon#about to read 4, iclass 29, count 2 2006.257.19:46:57.94#ibcon#read 4, iclass 29, count 2 2006.257.19:46:57.94#ibcon#about to read 5, iclass 29, count 2 2006.257.19:46:57.94#ibcon#read 5, iclass 29, count 2 2006.257.19:46:57.94#ibcon#about to read 6, iclass 29, count 2 2006.257.19:46:57.94#ibcon#read 6, iclass 29, count 2 2006.257.19:46:57.94#ibcon#end of sib2, iclass 29, count 2 2006.257.19:46:57.94#ibcon#*after write, iclass 29, count 2 2006.257.19:46:57.94#ibcon#*before return 0, iclass 29, count 2 2006.257.19:46:57.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:57.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.19:46:57.94#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.19:46:57.94#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:57.94#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:58.06#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:58.06#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:58.06#ibcon#enter wrdev, iclass 29, count 0 2006.257.19:46:58.06#ibcon#first serial, iclass 29, count 0 2006.257.19:46:58.06#ibcon#enter sib2, iclass 29, count 0 2006.257.19:46:58.06#ibcon#flushed, iclass 29, count 0 2006.257.19:46:58.06#ibcon#about to write, iclass 29, count 0 2006.257.19:46:58.06#ibcon#wrote, iclass 29, count 0 2006.257.19:46:58.06#ibcon#about to read 3, iclass 29, count 0 2006.257.19:46:58.08#ibcon#read 3, iclass 29, count 0 2006.257.19:46:58.08#ibcon#about to read 4, iclass 29, count 0 2006.257.19:46:58.08#ibcon#read 4, iclass 29, count 0 2006.257.19:46:58.08#ibcon#about to read 5, iclass 29, count 0 2006.257.19:46:58.08#ibcon#read 5, iclass 29, count 0 2006.257.19:46:58.08#ibcon#about to read 6, iclass 29, count 0 2006.257.19:46:58.08#ibcon#read 6, iclass 29, count 0 2006.257.19:46:58.08#ibcon#end of sib2, iclass 29, count 0 2006.257.19:46:58.08#ibcon#*mode == 0, iclass 29, count 0 2006.257.19:46:58.08#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.19:46:58.08#ibcon#[27=USB\r\n] 2006.257.19:46:58.08#ibcon#*before write, iclass 29, count 0 2006.257.19:46:58.08#ibcon#enter sib2, iclass 29, count 0 2006.257.19:46:58.08#ibcon#flushed, iclass 29, count 0 2006.257.19:46:58.08#ibcon#about to write, iclass 29, count 0 2006.257.19:46:58.08#ibcon#wrote, iclass 29, count 0 2006.257.19:46:58.08#ibcon#about to read 3, iclass 29, count 0 2006.257.19:46:58.11#ibcon#read 3, iclass 29, count 0 2006.257.19:46:58.11#ibcon#about to read 4, iclass 29, count 0 2006.257.19:46:58.11#ibcon#read 4, iclass 29, count 0 2006.257.19:46:58.11#ibcon#about to read 5, iclass 29, count 0 2006.257.19:46:58.11#ibcon#read 5, iclass 29, count 0 2006.257.19:46:58.11#ibcon#about to read 6, iclass 29, count 0 2006.257.19:46:58.11#ibcon#read 6, iclass 29, count 0 2006.257.19:46:58.11#ibcon#end of sib2, iclass 29, count 0 2006.257.19:46:58.11#ibcon#*after write, iclass 29, count 0 2006.257.19:46:58.11#ibcon#*before return 0, iclass 29, count 0 2006.257.19:46:58.11#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:58.11#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.19:46:58.11#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.19:46:58.11#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.19:46:58.11$vck44/vblo=4,679.99 2006.257.19:46:58.11#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.19:46:58.11#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.19:46:58.11#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:58.11#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:58.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:58.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:58.11#ibcon#enter wrdev, iclass 31, count 0 2006.257.19:46:58.11#ibcon#first serial, iclass 31, count 0 2006.257.19:46:58.11#ibcon#enter sib2, iclass 31, count 0 2006.257.19:46:58.11#ibcon#flushed, iclass 31, count 0 2006.257.19:46:58.11#ibcon#about to write, iclass 31, count 0 2006.257.19:46:58.11#ibcon#wrote, iclass 31, count 0 2006.257.19:46:58.11#ibcon#about to read 3, iclass 31, count 0 2006.257.19:46:58.13#ibcon#read 3, iclass 31, count 0 2006.257.19:46:58.13#ibcon#about to read 4, iclass 31, count 0 2006.257.19:46:58.13#ibcon#read 4, iclass 31, count 0 2006.257.19:46:58.13#ibcon#about to read 5, iclass 31, count 0 2006.257.19:46:58.13#ibcon#read 5, iclass 31, count 0 2006.257.19:46:58.13#ibcon#about to read 6, iclass 31, count 0 2006.257.19:46:58.13#ibcon#read 6, iclass 31, count 0 2006.257.19:46:58.13#ibcon#end of sib2, iclass 31, count 0 2006.257.19:46:58.13#ibcon#*mode == 0, iclass 31, count 0 2006.257.19:46:58.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.19:46:58.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.19:46:58.13#ibcon#*before write, iclass 31, count 0 2006.257.19:46:58.13#ibcon#enter sib2, iclass 31, count 0 2006.257.19:46:58.13#ibcon#flushed, iclass 31, count 0 2006.257.19:46:58.13#ibcon#about to write, iclass 31, count 0 2006.257.19:46:58.13#ibcon#wrote, iclass 31, count 0 2006.257.19:46:58.13#ibcon#about to read 3, iclass 31, count 0 2006.257.19:46:58.17#ibcon#read 3, iclass 31, count 0 2006.257.19:46:58.17#ibcon#about to read 4, iclass 31, count 0 2006.257.19:46:58.17#ibcon#read 4, iclass 31, count 0 2006.257.19:46:58.17#ibcon#about to read 5, iclass 31, count 0 2006.257.19:46:58.17#ibcon#read 5, iclass 31, count 0 2006.257.19:46:58.17#ibcon#about to read 6, iclass 31, count 0 2006.257.19:46:58.17#ibcon#read 6, iclass 31, count 0 2006.257.19:46:58.17#ibcon#end of sib2, iclass 31, count 0 2006.257.19:46:58.17#ibcon#*after write, iclass 31, count 0 2006.257.19:46:58.17#ibcon#*before return 0, iclass 31, count 0 2006.257.19:46:58.17#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:58.17#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.19:46:58.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.19:46:58.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.19:46:58.17$vck44/vb=4,5 2006.257.19:46:58.17#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.19:46:58.17#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.19:46:58.17#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:58.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:58.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:58.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:58.23#ibcon#enter wrdev, iclass 33, count 2 2006.257.19:46:58.23#ibcon#first serial, iclass 33, count 2 2006.257.19:46:58.23#ibcon#enter sib2, iclass 33, count 2 2006.257.19:46:58.23#ibcon#flushed, iclass 33, count 2 2006.257.19:46:58.23#ibcon#about to write, iclass 33, count 2 2006.257.19:46:58.23#ibcon#wrote, iclass 33, count 2 2006.257.19:46:58.23#ibcon#about to read 3, iclass 33, count 2 2006.257.19:46:58.25#ibcon#read 3, iclass 33, count 2 2006.257.19:46:58.25#ibcon#about to read 4, iclass 33, count 2 2006.257.19:46:58.25#ibcon#read 4, iclass 33, count 2 2006.257.19:46:58.25#ibcon#about to read 5, iclass 33, count 2 2006.257.19:46:58.25#ibcon#read 5, iclass 33, count 2 2006.257.19:46:58.25#ibcon#about to read 6, iclass 33, count 2 2006.257.19:46:58.25#ibcon#read 6, iclass 33, count 2 2006.257.19:46:58.25#ibcon#end of sib2, iclass 33, count 2 2006.257.19:46:58.25#ibcon#*mode == 0, iclass 33, count 2 2006.257.19:46:58.25#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.19:46:58.25#ibcon#[27=AT04-05\r\n] 2006.257.19:46:58.25#ibcon#*before write, iclass 33, count 2 2006.257.19:46:58.25#ibcon#enter sib2, iclass 33, count 2 2006.257.19:46:58.25#ibcon#flushed, iclass 33, count 2 2006.257.19:46:58.25#ibcon#about to write, iclass 33, count 2 2006.257.19:46:58.25#ibcon#wrote, iclass 33, count 2 2006.257.19:46:58.25#ibcon#about to read 3, iclass 33, count 2 2006.257.19:46:58.28#ibcon#read 3, iclass 33, count 2 2006.257.19:46:58.28#ibcon#about to read 4, iclass 33, count 2 2006.257.19:46:58.28#ibcon#read 4, iclass 33, count 2 2006.257.19:46:58.28#ibcon#about to read 5, iclass 33, count 2 2006.257.19:46:58.28#ibcon#read 5, iclass 33, count 2 2006.257.19:46:58.28#ibcon#about to read 6, iclass 33, count 2 2006.257.19:46:58.28#ibcon#read 6, iclass 33, count 2 2006.257.19:46:58.28#ibcon#end of sib2, iclass 33, count 2 2006.257.19:46:58.28#ibcon#*after write, iclass 33, count 2 2006.257.19:46:58.28#ibcon#*before return 0, iclass 33, count 2 2006.257.19:46:58.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:58.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.19:46:58.28#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.19:46:58.28#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:58.28#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:58.40#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:58.40#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:58.40#ibcon#enter wrdev, iclass 33, count 0 2006.257.19:46:58.40#ibcon#first serial, iclass 33, count 0 2006.257.19:46:58.40#ibcon#enter sib2, iclass 33, count 0 2006.257.19:46:58.40#ibcon#flushed, iclass 33, count 0 2006.257.19:46:58.40#ibcon#about to write, iclass 33, count 0 2006.257.19:46:58.40#ibcon#wrote, iclass 33, count 0 2006.257.19:46:58.40#ibcon#about to read 3, iclass 33, count 0 2006.257.19:46:58.42#ibcon#read 3, iclass 33, count 0 2006.257.19:46:58.42#ibcon#about to read 4, iclass 33, count 0 2006.257.19:46:58.42#ibcon#read 4, iclass 33, count 0 2006.257.19:46:58.42#ibcon#about to read 5, iclass 33, count 0 2006.257.19:46:58.42#ibcon#read 5, iclass 33, count 0 2006.257.19:46:58.42#ibcon#about to read 6, iclass 33, count 0 2006.257.19:46:58.42#ibcon#read 6, iclass 33, count 0 2006.257.19:46:58.42#ibcon#end of sib2, iclass 33, count 0 2006.257.19:46:58.42#ibcon#*mode == 0, iclass 33, count 0 2006.257.19:46:58.42#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.19:46:58.42#ibcon#[27=USB\r\n] 2006.257.19:46:58.42#ibcon#*before write, iclass 33, count 0 2006.257.19:46:58.42#ibcon#enter sib2, iclass 33, count 0 2006.257.19:46:58.42#ibcon#flushed, iclass 33, count 0 2006.257.19:46:58.42#ibcon#about to write, iclass 33, count 0 2006.257.19:46:58.42#ibcon#wrote, iclass 33, count 0 2006.257.19:46:58.42#ibcon#about to read 3, iclass 33, count 0 2006.257.19:46:58.45#ibcon#read 3, iclass 33, count 0 2006.257.19:46:58.45#ibcon#about to read 4, iclass 33, count 0 2006.257.19:46:58.45#ibcon#read 4, iclass 33, count 0 2006.257.19:46:58.45#ibcon#about to read 5, iclass 33, count 0 2006.257.19:46:58.45#ibcon#read 5, iclass 33, count 0 2006.257.19:46:58.45#ibcon#about to read 6, iclass 33, count 0 2006.257.19:46:58.45#ibcon#read 6, iclass 33, count 0 2006.257.19:46:58.45#ibcon#end of sib2, iclass 33, count 0 2006.257.19:46:58.45#ibcon#*after write, iclass 33, count 0 2006.257.19:46:58.45#ibcon#*before return 0, iclass 33, count 0 2006.257.19:46:58.45#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:58.45#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.19:46:58.45#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.19:46:58.45#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.19:46:58.45$vck44/vblo=5,709.99 2006.257.19:46:58.45#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.19:46:58.45#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.19:46:58.45#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:58.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:58.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:58.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:58.45#ibcon#enter wrdev, iclass 35, count 0 2006.257.19:46:58.45#ibcon#first serial, iclass 35, count 0 2006.257.19:46:58.45#ibcon#enter sib2, iclass 35, count 0 2006.257.19:46:58.45#ibcon#flushed, iclass 35, count 0 2006.257.19:46:58.45#ibcon#about to write, iclass 35, count 0 2006.257.19:46:58.45#ibcon#wrote, iclass 35, count 0 2006.257.19:46:58.45#ibcon#about to read 3, iclass 35, count 0 2006.257.19:46:58.47#ibcon#read 3, iclass 35, count 0 2006.257.19:46:58.47#ibcon#about to read 4, iclass 35, count 0 2006.257.19:46:58.47#ibcon#read 4, iclass 35, count 0 2006.257.19:46:58.47#ibcon#about to read 5, iclass 35, count 0 2006.257.19:46:58.47#ibcon#read 5, iclass 35, count 0 2006.257.19:46:58.47#ibcon#about to read 6, iclass 35, count 0 2006.257.19:46:58.47#ibcon#read 6, iclass 35, count 0 2006.257.19:46:58.47#ibcon#end of sib2, iclass 35, count 0 2006.257.19:46:58.47#ibcon#*mode == 0, iclass 35, count 0 2006.257.19:46:58.47#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.19:46:58.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.19:46:58.47#ibcon#*before write, iclass 35, count 0 2006.257.19:46:58.47#ibcon#enter sib2, iclass 35, count 0 2006.257.19:46:58.47#ibcon#flushed, iclass 35, count 0 2006.257.19:46:58.47#ibcon#about to write, iclass 35, count 0 2006.257.19:46:58.47#ibcon#wrote, iclass 35, count 0 2006.257.19:46:58.47#ibcon#about to read 3, iclass 35, count 0 2006.257.19:46:58.51#ibcon#read 3, iclass 35, count 0 2006.257.19:46:58.51#ibcon#about to read 4, iclass 35, count 0 2006.257.19:46:58.51#ibcon#read 4, iclass 35, count 0 2006.257.19:46:58.51#ibcon#about to read 5, iclass 35, count 0 2006.257.19:46:58.51#ibcon#read 5, iclass 35, count 0 2006.257.19:46:58.51#ibcon#about to read 6, iclass 35, count 0 2006.257.19:46:58.51#ibcon#read 6, iclass 35, count 0 2006.257.19:46:58.51#ibcon#end of sib2, iclass 35, count 0 2006.257.19:46:58.51#ibcon#*after write, iclass 35, count 0 2006.257.19:46:58.51#ibcon#*before return 0, iclass 35, count 0 2006.257.19:46:58.51#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:58.51#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.19:46:58.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.19:46:58.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.19:46:58.51$vck44/vb=5,4 2006.257.19:46:58.51#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.19:46:58.51#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.19:46:58.51#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:58.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:58.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:58.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:58.57#ibcon#enter wrdev, iclass 37, count 2 2006.257.19:46:58.57#ibcon#first serial, iclass 37, count 2 2006.257.19:46:58.57#ibcon#enter sib2, iclass 37, count 2 2006.257.19:46:58.57#ibcon#flushed, iclass 37, count 2 2006.257.19:46:58.57#ibcon#about to write, iclass 37, count 2 2006.257.19:46:58.57#ibcon#wrote, iclass 37, count 2 2006.257.19:46:58.57#ibcon#about to read 3, iclass 37, count 2 2006.257.19:46:58.59#ibcon#read 3, iclass 37, count 2 2006.257.19:46:58.59#ibcon#about to read 4, iclass 37, count 2 2006.257.19:46:58.59#ibcon#read 4, iclass 37, count 2 2006.257.19:46:58.59#ibcon#about to read 5, iclass 37, count 2 2006.257.19:46:58.59#ibcon#read 5, iclass 37, count 2 2006.257.19:46:58.59#ibcon#about to read 6, iclass 37, count 2 2006.257.19:46:58.59#ibcon#read 6, iclass 37, count 2 2006.257.19:46:58.59#ibcon#end of sib2, iclass 37, count 2 2006.257.19:46:58.59#ibcon#*mode == 0, iclass 37, count 2 2006.257.19:46:58.59#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.19:46:58.59#ibcon#[27=AT05-04\r\n] 2006.257.19:46:58.59#ibcon#*before write, iclass 37, count 2 2006.257.19:46:58.59#ibcon#enter sib2, iclass 37, count 2 2006.257.19:46:58.59#ibcon#flushed, iclass 37, count 2 2006.257.19:46:58.59#ibcon#about to write, iclass 37, count 2 2006.257.19:46:58.59#ibcon#wrote, iclass 37, count 2 2006.257.19:46:58.59#ibcon#about to read 3, iclass 37, count 2 2006.257.19:46:58.62#ibcon#read 3, iclass 37, count 2 2006.257.19:46:58.62#ibcon#about to read 4, iclass 37, count 2 2006.257.19:46:58.62#ibcon#read 4, iclass 37, count 2 2006.257.19:46:58.62#ibcon#about to read 5, iclass 37, count 2 2006.257.19:46:58.62#ibcon#read 5, iclass 37, count 2 2006.257.19:46:58.62#ibcon#about to read 6, iclass 37, count 2 2006.257.19:46:58.62#ibcon#read 6, iclass 37, count 2 2006.257.19:46:58.62#ibcon#end of sib2, iclass 37, count 2 2006.257.19:46:58.62#ibcon#*after write, iclass 37, count 2 2006.257.19:46:58.62#ibcon#*before return 0, iclass 37, count 2 2006.257.19:46:58.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:58.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.19:46:58.62#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.19:46:58.62#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:58.62#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:58.74#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:58.74#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:58.74#ibcon#enter wrdev, iclass 37, count 0 2006.257.19:46:58.74#ibcon#first serial, iclass 37, count 0 2006.257.19:46:58.74#ibcon#enter sib2, iclass 37, count 0 2006.257.19:46:58.74#ibcon#flushed, iclass 37, count 0 2006.257.19:46:58.74#ibcon#about to write, iclass 37, count 0 2006.257.19:46:58.74#ibcon#wrote, iclass 37, count 0 2006.257.19:46:58.74#ibcon#about to read 3, iclass 37, count 0 2006.257.19:46:58.76#ibcon#read 3, iclass 37, count 0 2006.257.19:46:58.76#ibcon#about to read 4, iclass 37, count 0 2006.257.19:46:58.76#ibcon#read 4, iclass 37, count 0 2006.257.19:46:58.76#ibcon#about to read 5, iclass 37, count 0 2006.257.19:46:58.76#ibcon#read 5, iclass 37, count 0 2006.257.19:46:58.76#ibcon#about to read 6, iclass 37, count 0 2006.257.19:46:58.76#ibcon#read 6, iclass 37, count 0 2006.257.19:46:58.76#ibcon#end of sib2, iclass 37, count 0 2006.257.19:46:58.76#ibcon#*mode == 0, iclass 37, count 0 2006.257.19:46:58.76#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.19:46:58.76#ibcon#[27=USB\r\n] 2006.257.19:46:58.76#ibcon#*before write, iclass 37, count 0 2006.257.19:46:58.76#ibcon#enter sib2, iclass 37, count 0 2006.257.19:46:58.76#ibcon#flushed, iclass 37, count 0 2006.257.19:46:58.76#ibcon#about to write, iclass 37, count 0 2006.257.19:46:58.76#ibcon#wrote, iclass 37, count 0 2006.257.19:46:58.76#ibcon#about to read 3, iclass 37, count 0 2006.257.19:46:58.79#ibcon#read 3, iclass 37, count 0 2006.257.19:46:58.79#ibcon#about to read 4, iclass 37, count 0 2006.257.19:46:58.79#ibcon#read 4, iclass 37, count 0 2006.257.19:46:58.79#ibcon#about to read 5, iclass 37, count 0 2006.257.19:46:58.79#ibcon#read 5, iclass 37, count 0 2006.257.19:46:58.79#ibcon#about to read 6, iclass 37, count 0 2006.257.19:46:58.79#ibcon#read 6, iclass 37, count 0 2006.257.19:46:58.79#ibcon#end of sib2, iclass 37, count 0 2006.257.19:46:58.79#ibcon#*after write, iclass 37, count 0 2006.257.19:46:58.79#ibcon#*before return 0, iclass 37, count 0 2006.257.19:46:58.79#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:58.79#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.19:46:58.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.19:46:58.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.19:46:58.79$vck44/vblo=6,719.99 2006.257.19:46:58.79#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.19:46:58.79#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.19:46:58.79#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:58.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:58.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:58.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:58.79#ibcon#enter wrdev, iclass 39, count 0 2006.257.19:46:58.79#ibcon#first serial, iclass 39, count 0 2006.257.19:46:58.79#ibcon#enter sib2, iclass 39, count 0 2006.257.19:46:58.79#ibcon#flushed, iclass 39, count 0 2006.257.19:46:58.79#ibcon#about to write, iclass 39, count 0 2006.257.19:46:58.79#ibcon#wrote, iclass 39, count 0 2006.257.19:46:58.79#ibcon#about to read 3, iclass 39, count 0 2006.257.19:46:58.81#ibcon#read 3, iclass 39, count 0 2006.257.19:46:58.81#ibcon#about to read 4, iclass 39, count 0 2006.257.19:46:58.81#ibcon#read 4, iclass 39, count 0 2006.257.19:46:58.81#ibcon#about to read 5, iclass 39, count 0 2006.257.19:46:58.81#ibcon#read 5, iclass 39, count 0 2006.257.19:46:58.81#ibcon#about to read 6, iclass 39, count 0 2006.257.19:46:58.81#ibcon#read 6, iclass 39, count 0 2006.257.19:46:58.81#ibcon#end of sib2, iclass 39, count 0 2006.257.19:46:58.81#ibcon#*mode == 0, iclass 39, count 0 2006.257.19:46:58.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.19:46:58.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.19:46:58.81#ibcon#*before write, iclass 39, count 0 2006.257.19:46:58.81#ibcon#enter sib2, iclass 39, count 0 2006.257.19:46:58.81#ibcon#flushed, iclass 39, count 0 2006.257.19:46:58.81#ibcon#about to write, iclass 39, count 0 2006.257.19:46:58.81#ibcon#wrote, iclass 39, count 0 2006.257.19:46:58.81#ibcon#about to read 3, iclass 39, count 0 2006.257.19:46:58.85#ibcon#read 3, iclass 39, count 0 2006.257.19:46:58.85#ibcon#about to read 4, iclass 39, count 0 2006.257.19:46:58.85#ibcon#read 4, iclass 39, count 0 2006.257.19:46:58.85#ibcon#about to read 5, iclass 39, count 0 2006.257.19:46:58.85#ibcon#read 5, iclass 39, count 0 2006.257.19:46:58.85#ibcon#about to read 6, iclass 39, count 0 2006.257.19:46:58.85#ibcon#read 6, iclass 39, count 0 2006.257.19:46:58.85#ibcon#end of sib2, iclass 39, count 0 2006.257.19:46:58.85#ibcon#*after write, iclass 39, count 0 2006.257.19:46:58.85#ibcon#*before return 0, iclass 39, count 0 2006.257.19:46:58.85#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:58.85#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.19:46:58.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.19:46:58.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.19:46:58.85$vck44/vb=6,4 2006.257.19:46:58.85#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.19:46:58.85#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.19:46:58.85#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:58.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:58.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:58.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:58.91#ibcon#enter wrdev, iclass 3, count 2 2006.257.19:46:58.91#ibcon#first serial, iclass 3, count 2 2006.257.19:46:58.91#ibcon#enter sib2, iclass 3, count 2 2006.257.19:46:58.91#ibcon#flushed, iclass 3, count 2 2006.257.19:46:58.91#ibcon#about to write, iclass 3, count 2 2006.257.19:46:58.91#ibcon#wrote, iclass 3, count 2 2006.257.19:46:58.91#ibcon#about to read 3, iclass 3, count 2 2006.257.19:46:58.93#ibcon#read 3, iclass 3, count 2 2006.257.19:46:58.93#ibcon#about to read 4, iclass 3, count 2 2006.257.19:46:58.93#ibcon#read 4, iclass 3, count 2 2006.257.19:46:58.93#ibcon#about to read 5, iclass 3, count 2 2006.257.19:46:58.93#ibcon#read 5, iclass 3, count 2 2006.257.19:46:58.93#ibcon#about to read 6, iclass 3, count 2 2006.257.19:46:58.93#ibcon#read 6, iclass 3, count 2 2006.257.19:46:58.93#ibcon#end of sib2, iclass 3, count 2 2006.257.19:46:58.93#ibcon#*mode == 0, iclass 3, count 2 2006.257.19:46:58.93#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.19:46:58.93#ibcon#[27=AT06-04\r\n] 2006.257.19:46:58.93#ibcon#*before write, iclass 3, count 2 2006.257.19:46:58.93#ibcon#enter sib2, iclass 3, count 2 2006.257.19:46:58.93#ibcon#flushed, iclass 3, count 2 2006.257.19:46:58.93#ibcon#about to write, iclass 3, count 2 2006.257.19:46:58.93#ibcon#wrote, iclass 3, count 2 2006.257.19:46:58.93#ibcon#about to read 3, iclass 3, count 2 2006.257.19:46:58.96#ibcon#read 3, iclass 3, count 2 2006.257.19:46:58.96#ibcon#about to read 4, iclass 3, count 2 2006.257.19:46:58.96#ibcon#read 4, iclass 3, count 2 2006.257.19:46:58.96#ibcon#about to read 5, iclass 3, count 2 2006.257.19:46:58.96#ibcon#read 5, iclass 3, count 2 2006.257.19:46:58.96#ibcon#about to read 6, iclass 3, count 2 2006.257.19:46:58.96#ibcon#read 6, iclass 3, count 2 2006.257.19:46:58.96#ibcon#end of sib2, iclass 3, count 2 2006.257.19:46:58.96#ibcon#*after write, iclass 3, count 2 2006.257.19:46:58.96#ibcon#*before return 0, iclass 3, count 2 2006.257.19:46:58.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:58.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.19:46:58.96#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.19:46:58.96#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:58.96#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:59.08#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:59.08#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:59.08#ibcon#enter wrdev, iclass 3, count 0 2006.257.19:46:59.08#ibcon#first serial, iclass 3, count 0 2006.257.19:46:59.08#ibcon#enter sib2, iclass 3, count 0 2006.257.19:46:59.08#ibcon#flushed, iclass 3, count 0 2006.257.19:46:59.08#ibcon#about to write, iclass 3, count 0 2006.257.19:46:59.08#ibcon#wrote, iclass 3, count 0 2006.257.19:46:59.08#ibcon#about to read 3, iclass 3, count 0 2006.257.19:46:59.10#ibcon#read 3, iclass 3, count 0 2006.257.19:46:59.10#ibcon#about to read 4, iclass 3, count 0 2006.257.19:46:59.10#ibcon#read 4, iclass 3, count 0 2006.257.19:46:59.10#ibcon#about to read 5, iclass 3, count 0 2006.257.19:46:59.10#ibcon#read 5, iclass 3, count 0 2006.257.19:46:59.10#ibcon#about to read 6, iclass 3, count 0 2006.257.19:46:59.10#ibcon#read 6, iclass 3, count 0 2006.257.19:46:59.10#ibcon#end of sib2, iclass 3, count 0 2006.257.19:46:59.10#ibcon#*mode == 0, iclass 3, count 0 2006.257.19:46:59.10#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.19:46:59.10#ibcon#[27=USB\r\n] 2006.257.19:46:59.10#ibcon#*before write, iclass 3, count 0 2006.257.19:46:59.10#ibcon#enter sib2, iclass 3, count 0 2006.257.19:46:59.10#ibcon#flushed, iclass 3, count 0 2006.257.19:46:59.10#ibcon#about to write, iclass 3, count 0 2006.257.19:46:59.10#ibcon#wrote, iclass 3, count 0 2006.257.19:46:59.10#ibcon#about to read 3, iclass 3, count 0 2006.257.19:46:59.13#ibcon#read 3, iclass 3, count 0 2006.257.19:46:59.13#ibcon#about to read 4, iclass 3, count 0 2006.257.19:46:59.13#ibcon#read 4, iclass 3, count 0 2006.257.19:46:59.13#ibcon#about to read 5, iclass 3, count 0 2006.257.19:46:59.13#ibcon#read 5, iclass 3, count 0 2006.257.19:46:59.13#ibcon#about to read 6, iclass 3, count 0 2006.257.19:46:59.13#ibcon#read 6, iclass 3, count 0 2006.257.19:46:59.13#ibcon#end of sib2, iclass 3, count 0 2006.257.19:46:59.13#ibcon#*after write, iclass 3, count 0 2006.257.19:46:59.13#ibcon#*before return 0, iclass 3, count 0 2006.257.19:46:59.13#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:59.13#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.19:46:59.13#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.19:46:59.13#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.19:46:59.13$vck44/vblo=7,734.99 2006.257.19:46:59.13#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.19:46:59.13#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.19:46:59.13#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:59.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:59.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:59.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:59.13#ibcon#enter wrdev, iclass 5, count 0 2006.257.19:46:59.13#ibcon#first serial, iclass 5, count 0 2006.257.19:46:59.13#ibcon#enter sib2, iclass 5, count 0 2006.257.19:46:59.13#ibcon#flushed, iclass 5, count 0 2006.257.19:46:59.13#ibcon#about to write, iclass 5, count 0 2006.257.19:46:59.13#ibcon#wrote, iclass 5, count 0 2006.257.19:46:59.13#ibcon#about to read 3, iclass 5, count 0 2006.257.19:46:59.15#ibcon#read 3, iclass 5, count 0 2006.257.19:46:59.15#ibcon#about to read 4, iclass 5, count 0 2006.257.19:46:59.15#ibcon#read 4, iclass 5, count 0 2006.257.19:46:59.15#ibcon#about to read 5, iclass 5, count 0 2006.257.19:46:59.15#ibcon#read 5, iclass 5, count 0 2006.257.19:46:59.15#ibcon#about to read 6, iclass 5, count 0 2006.257.19:46:59.15#ibcon#read 6, iclass 5, count 0 2006.257.19:46:59.15#ibcon#end of sib2, iclass 5, count 0 2006.257.19:46:59.15#ibcon#*mode == 0, iclass 5, count 0 2006.257.19:46:59.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.19:46:59.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.19:46:59.15#ibcon#*before write, iclass 5, count 0 2006.257.19:46:59.15#ibcon#enter sib2, iclass 5, count 0 2006.257.19:46:59.15#ibcon#flushed, iclass 5, count 0 2006.257.19:46:59.15#ibcon#about to write, iclass 5, count 0 2006.257.19:46:59.15#ibcon#wrote, iclass 5, count 0 2006.257.19:46:59.15#ibcon#about to read 3, iclass 5, count 0 2006.257.19:46:59.19#ibcon#read 3, iclass 5, count 0 2006.257.19:46:59.19#ibcon#about to read 4, iclass 5, count 0 2006.257.19:46:59.19#ibcon#read 4, iclass 5, count 0 2006.257.19:46:59.19#ibcon#about to read 5, iclass 5, count 0 2006.257.19:46:59.19#ibcon#read 5, iclass 5, count 0 2006.257.19:46:59.19#ibcon#about to read 6, iclass 5, count 0 2006.257.19:46:59.19#ibcon#read 6, iclass 5, count 0 2006.257.19:46:59.19#ibcon#end of sib2, iclass 5, count 0 2006.257.19:46:59.19#ibcon#*after write, iclass 5, count 0 2006.257.19:46:59.19#ibcon#*before return 0, iclass 5, count 0 2006.257.19:46:59.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:59.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:46:59.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.19:46:59.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.19:46:59.19$vck44/vb=7,4 2006.257.19:46:59.19#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.19:46:59.19#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.19:46:59.19#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:59.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:59.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:59.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:59.25#ibcon#enter wrdev, iclass 7, count 2 2006.257.19:46:59.25#ibcon#first serial, iclass 7, count 2 2006.257.19:46:59.25#ibcon#enter sib2, iclass 7, count 2 2006.257.19:46:59.25#ibcon#flushed, iclass 7, count 2 2006.257.19:46:59.25#ibcon#about to write, iclass 7, count 2 2006.257.19:46:59.25#ibcon#wrote, iclass 7, count 2 2006.257.19:46:59.25#ibcon#about to read 3, iclass 7, count 2 2006.257.19:46:59.27#ibcon#read 3, iclass 7, count 2 2006.257.19:46:59.27#ibcon#about to read 4, iclass 7, count 2 2006.257.19:46:59.27#ibcon#read 4, iclass 7, count 2 2006.257.19:46:59.27#ibcon#about to read 5, iclass 7, count 2 2006.257.19:46:59.27#ibcon#read 5, iclass 7, count 2 2006.257.19:46:59.27#ibcon#about to read 6, iclass 7, count 2 2006.257.19:46:59.27#ibcon#read 6, iclass 7, count 2 2006.257.19:46:59.27#ibcon#end of sib2, iclass 7, count 2 2006.257.19:46:59.27#ibcon#*mode == 0, iclass 7, count 2 2006.257.19:46:59.27#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.19:46:59.27#ibcon#[27=AT07-04\r\n] 2006.257.19:46:59.27#ibcon#*before write, iclass 7, count 2 2006.257.19:46:59.27#ibcon#enter sib2, iclass 7, count 2 2006.257.19:46:59.27#ibcon#flushed, iclass 7, count 2 2006.257.19:46:59.27#ibcon#about to write, iclass 7, count 2 2006.257.19:46:59.27#ibcon#wrote, iclass 7, count 2 2006.257.19:46:59.27#ibcon#about to read 3, iclass 7, count 2 2006.257.19:46:59.30#ibcon#read 3, iclass 7, count 2 2006.257.19:46:59.30#ibcon#about to read 4, iclass 7, count 2 2006.257.19:46:59.30#ibcon#read 4, iclass 7, count 2 2006.257.19:46:59.30#ibcon#about to read 5, iclass 7, count 2 2006.257.19:46:59.30#ibcon#read 5, iclass 7, count 2 2006.257.19:46:59.30#ibcon#about to read 6, iclass 7, count 2 2006.257.19:46:59.30#ibcon#read 6, iclass 7, count 2 2006.257.19:46:59.30#ibcon#end of sib2, iclass 7, count 2 2006.257.19:46:59.30#ibcon#*after write, iclass 7, count 2 2006.257.19:46:59.30#ibcon#*before return 0, iclass 7, count 2 2006.257.19:46:59.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:59.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.19:46:59.30#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.19:46:59.30#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:59.30#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:59.42#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:59.42#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:59.42#ibcon#enter wrdev, iclass 7, count 0 2006.257.19:46:59.42#ibcon#first serial, iclass 7, count 0 2006.257.19:46:59.42#ibcon#enter sib2, iclass 7, count 0 2006.257.19:46:59.42#ibcon#flushed, iclass 7, count 0 2006.257.19:46:59.42#ibcon#about to write, iclass 7, count 0 2006.257.19:46:59.42#ibcon#wrote, iclass 7, count 0 2006.257.19:46:59.42#ibcon#about to read 3, iclass 7, count 0 2006.257.19:46:59.44#ibcon#read 3, iclass 7, count 0 2006.257.19:46:59.44#ibcon#about to read 4, iclass 7, count 0 2006.257.19:46:59.44#ibcon#read 4, iclass 7, count 0 2006.257.19:46:59.44#ibcon#about to read 5, iclass 7, count 0 2006.257.19:46:59.44#ibcon#read 5, iclass 7, count 0 2006.257.19:46:59.44#ibcon#about to read 6, iclass 7, count 0 2006.257.19:46:59.44#ibcon#read 6, iclass 7, count 0 2006.257.19:46:59.44#ibcon#end of sib2, iclass 7, count 0 2006.257.19:46:59.44#ibcon#*mode == 0, iclass 7, count 0 2006.257.19:46:59.44#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.19:46:59.44#ibcon#[27=USB\r\n] 2006.257.19:46:59.44#ibcon#*before write, iclass 7, count 0 2006.257.19:46:59.44#ibcon#enter sib2, iclass 7, count 0 2006.257.19:46:59.44#ibcon#flushed, iclass 7, count 0 2006.257.19:46:59.44#ibcon#about to write, iclass 7, count 0 2006.257.19:46:59.44#ibcon#wrote, iclass 7, count 0 2006.257.19:46:59.44#ibcon#about to read 3, iclass 7, count 0 2006.257.19:46:59.47#ibcon#read 3, iclass 7, count 0 2006.257.19:46:59.47#ibcon#about to read 4, iclass 7, count 0 2006.257.19:46:59.47#ibcon#read 4, iclass 7, count 0 2006.257.19:46:59.47#ibcon#about to read 5, iclass 7, count 0 2006.257.19:46:59.47#ibcon#read 5, iclass 7, count 0 2006.257.19:46:59.47#ibcon#about to read 6, iclass 7, count 0 2006.257.19:46:59.47#ibcon#read 6, iclass 7, count 0 2006.257.19:46:59.47#ibcon#end of sib2, iclass 7, count 0 2006.257.19:46:59.47#ibcon#*after write, iclass 7, count 0 2006.257.19:46:59.47#ibcon#*before return 0, iclass 7, count 0 2006.257.19:46:59.47#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:59.47#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.19:46:59.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.19:46:59.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.19:46:59.47$vck44/vblo=8,744.99 2006.257.19:46:59.47#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.19:46:59.47#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.19:46:59.47#ibcon#ireg 17 cls_cnt 0 2006.257.19:46:59.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:59.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:59.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:59.47#ibcon#enter wrdev, iclass 11, count 0 2006.257.19:46:59.47#ibcon#first serial, iclass 11, count 0 2006.257.19:46:59.47#ibcon#enter sib2, iclass 11, count 0 2006.257.19:46:59.47#ibcon#flushed, iclass 11, count 0 2006.257.19:46:59.47#ibcon#about to write, iclass 11, count 0 2006.257.19:46:59.47#ibcon#wrote, iclass 11, count 0 2006.257.19:46:59.47#ibcon#about to read 3, iclass 11, count 0 2006.257.19:46:59.49#ibcon#read 3, iclass 11, count 0 2006.257.19:46:59.49#ibcon#about to read 4, iclass 11, count 0 2006.257.19:46:59.49#ibcon#read 4, iclass 11, count 0 2006.257.19:46:59.49#ibcon#about to read 5, iclass 11, count 0 2006.257.19:46:59.49#ibcon#read 5, iclass 11, count 0 2006.257.19:46:59.49#ibcon#about to read 6, iclass 11, count 0 2006.257.19:46:59.49#ibcon#read 6, iclass 11, count 0 2006.257.19:46:59.49#ibcon#end of sib2, iclass 11, count 0 2006.257.19:46:59.49#ibcon#*mode == 0, iclass 11, count 0 2006.257.19:46:59.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.19:46:59.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.19:46:59.49#ibcon#*before write, iclass 11, count 0 2006.257.19:46:59.49#ibcon#enter sib2, iclass 11, count 0 2006.257.19:46:59.49#ibcon#flushed, iclass 11, count 0 2006.257.19:46:59.49#ibcon#about to write, iclass 11, count 0 2006.257.19:46:59.49#ibcon#wrote, iclass 11, count 0 2006.257.19:46:59.49#ibcon#about to read 3, iclass 11, count 0 2006.257.19:46:59.53#ibcon#read 3, iclass 11, count 0 2006.257.19:46:59.53#ibcon#about to read 4, iclass 11, count 0 2006.257.19:46:59.53#ibcon#read 4, iclass 11, count 0 2006.257.19:46:59.53#ibcon#about to read 5, iclass 11, count 0 2006.257.19:46:59.53#ibcon#read 5, iclass 11, count 0 2006.257.19:46:59.53#ibcon#about to read 6, iclass 11, count 0 2006.257.19:46:59.53#ibcon#read 6, iclass 11, count 0 2006.257.19:46:59.53#ibcon#end of sib2, iclass 11, count 0 2006.257.19:46:59.53#ibcon#*after write, iclass 11, count 0 2006.257.19:46:59.53#ibcon#*before return 0, iclass 11, count 0 2006.257.19:46:59.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:59.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.19:46:59.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.19:46:59.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.19:46:59.53$vck44/vb=8,4 2006.257.19:46:59.53#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.19:46:59.53#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.19:46:59.53#ibcon#ireg 11 cls_cnt 2 2006.257.19:46:59.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:59.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:59.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:59.59#ibcon#enter wrdev, iclass 13, count 2 2006.257.19:46:59.59#ibcon#first serial, iclass 13, count 2 2006.257.19:46:59.59#ibcon#enter sib2, iclass 13, count 2 2006.257.19:46:59.59#ibcon#flushed, iclass 13, count 2 2006.257.19:46:59.59#ibcon#about to write, iclass 13, count 2 2006.257.19:46:59.59#ibcon#wrote, iclass 13, count 2 2006.257.19:46:59.59#ibcon#about to read 3, iclass 13, count 2 2006.257.19:46:59.61#ibcon#read 3, iclass 13, count 2 2006.257.19:46:59.61#ibcon#about to read 4, iclass 13, count 2 2006.257.19:46:59.61#ibcon#read 4, iclass 13, count 2 2006.257.19:46:59.61#ibcon#about to read 5, iclass 13, count 2 2006.257.19:46:59.61#ibcon#read 5, iclass 13, count 2 2006.257.19:46:59.61#ibcon#about to read 6, iclass 13, count 2 2006.257.19:46:59.61#ibcon#read 6, iclass 13, count 2 2006.257.19:46:59.61#ibcon#end of sib2, iclass 13, count 2 2006.257.19:46:59.61#ibcon#*mode == 0, iclass 13, count 2 2006.257.19:46:59.61#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.19:46:59.61#ibcon#[27=AT08-04\r\n] 2006.257.19:46:59.61#ibcon#*before write, iclass 13, count 2 2006.257.19:46:59.61#ibcon#enter sib2, iclass 13, count 2 2006.257.19:46:59.61#ibcon#flushed, iclass 13, count 2 2006.257.19:46:59.61#ibcon#about to write, iclass 13, count 2 2006.257.19:46:59.61#ibcon#wrote, iclass 13, count 2 2006.257.19:46:59.61#ibcon#about to read 3, iclass 13, count 2 2006.257.19:46:59.64#ibcon#read 3, iclass 13, count 2 2006.257.19:46:59.64#ibcon#about to read 4, iclass 13, count 2 2006.257.19:46:59.64#ibcon#read 4, iclass 13, count 2 2006.257.19:46:59.64#ibcon#about to read 5, iclass 13, count 2 2006.257.19:46:59.64#ibcon#read 5, iclass 13, count 2 2006.257.19:46:59.64#ibcon#about to read 6, iclass 13, count 2 2006.257.19:46:59.64#ibcon#read 6, iclass 13, count 2 2006.257.19:46:59.64#ibcon#end of sib2, iclass 13, count 2 2006.257.19:46:59.64#ibcon#*after write, iclass 13, count 2 2006.257.19:46:59.64#ibcon#*before return 0, iclass 13, count 2 2006.257.19:46:59.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:59.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.19:46:59.64#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.19:46:59.64#ibcon#ireg 7 cls_cnt 0 2006.257.19:46:59.64#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:59.76#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:59.76#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:59.76#ibcon#enter wrdev, iclass 13, count 0 2006.257.19:46:59.76#ibcon#first serial, iclass 13, count 0 2006.257.19:46:59.76#ibcon#enter sib2, iclass 13, count 0 2006.257.19:46:59.76#ibcon#flushed, iclass 13, count 0 2006.257.19:46:59.76#ibcon#about to write, iclass 13, count 0 2006.257.19:46:59.76#ibcon#wrote, iclass 13, count 0 2006.257.19:46:59.76#ibcon#about to read 3, iclass 13, count 0 2006.257.19:46:59.78#ibcon#read 3, iclass 13, count 0 2006.257.19:46:59.78#ibcon#about to read 4, iclass 13, count 0 2006.257.19:46:59.78#ibcon#read 4, iclass 13, count 0 2006.257.19:46:59.78#ibcon#about to read 5, iclass 13, count 0 2006.257.19:46:59.78#ibcon#read 5, iclass 13, count 0 2006.257.19:46:59.78#ibcon#about to read 6, iclass 13, count 0 2006.257.19:46:59.78#ibcon#read 6, iclass 13, count 0 2006.257.19:46:59.78#ibcon#end of sib2, iclass 13, count 0 2006.257.19:46:59.78#ibcon#*mode == 0, iclass 13, count 0 2006.257.19:46:59.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.19:46:59.78#ibcon#[27=USB\r\n] 2006.257.19:46:59.78#ibcon#*before write, iclass 13, count 0 2006.257.19:46:59.78#ibcon#enter sib2, iclass 13, count 0 2006.257.19:46:59.78#ibcon#flushed, iclass 13, count 0 2006.257.19:46:59.78#ibcon#about to write, iclass 13, count 0 2006.257.19:46:59.78#ibcon#wrote, iclass 13, count 0 2006.257.19:46:59.78#ibcon#about to read 3, iclass 13, count 0 2006.257.19:46:59.81#ibcon#read 3, iclass 13, count 0 2006.257.19:46:59.81#ibcon#about to read 4, iclass 13, count 0 2006.257.19:46:59.81#ibcon#read 4, iclass 13, count 0 2006.257.19:46:59.81#ibcon#about to read 5, iclass 13, count 0 2006.257.19:46:59.81#ibcon#read 5, iclass 13, count 0 2006.257.19:46:59.81#ibcon#about to read 6, iclass 13, count 0 2006.257.19:46:59.81#ibcon#read 6, iclass 13, count 0 2006.257.19:46:59.81#ibcon#end of sib2, iclass 13, count 0 2006.257.19:46:59.81#ibcon#*after write, iclass 13, count 0 2006.257.19:46:59.81#ibcon#*before return 0, iclass 13, count 0 2006.257.19:46:59.81#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:59.81#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.19:46:59.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.19:46:59.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.19:46:59.81$vck44/vabw=wide 2006.257.19:46:59.81#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.19:46:59.81#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.19:46:59.81#ibcon#ireg 8 cls_cnt 0 2006.257.19:46:59.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:59.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:59.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:59.81#ibcon#enter wrdev, iclass 15, count 0 2006.257.19:46:59.81#ibcon#first serial, iclass 15, count 0 2006.257.19:46:59.81#ibcon#enter sib2, iclass 15, count 0 2006.257.19:46:59.81#ibcon#flushed, iclass 15, count 0 2006.257.19:46:59.81#ibcon#about to write, iclass 15, count 0 2006.257.19:46:59.81#ibcon#wrote, iclass 15, count 0 2006.257.19:46:59.81#ibcon#about to read 3, iclass 15, count 0 2006.257.19:46:59.83#ibcon#read 3, iclass 15, count 0 2006.257.19:46:59.83#ibcon#about to read 4, iclass 15, count 0 2006.257.19:46:59.83#ibcon#read 4, iclass 15, count 0 2006.257.19:46:59.83#ibcon#about to read 5, iclass 15, count 0 2006.257.19:46:59.83#ibcon#read 5, iclass 15, count 0 2006.257.19:46:59.83#ibcon#about to read 6, iclass 15, count 0 2006.257.19:46:59.83#ibcon#read 6, iclass 15, count 0 2006.257.19:46:59.83#ibcon#end of sib2, iclass 15, count 0 2006.257.19:46:59.83#ibcon#*mode == 0, iclass 15, count 0 2006.257.19:46:59.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.19:46:59.83#ibcon#[25=BW32\r\n] 2006.257.19:46:59.83#ibcon#*before write, iclass 15, count 0 2006.257.19:46:59.83#ibcon#enter sib2, iclass 15, count 0 2006.257.19:46:59.83#ibcon#flushed, iclass 15, count 0 2006.257.19:46:59.83#ibcon#about to write, iclass 15, count 0 2006.257.19:46:59.83#ibcon#wrote, iclass 15, count 0 2006.257.19:46:59.83#ibcon#about to read 3, iclass 15, count 0 2006.257.19:46:59.86#ibcon#read 3, iclass 15, count 0 2006.257.19:46:59.86#ibcon#about to read 4, iclass 15, count 0 2006.257.19:46:59.86#ibcon#read 4, iclass 15, count 0 2006.257.19:46:59.86#ibcon#about to read 5, iclass 15, count 0 2006.257.19:46:59.86#ibcon#read 5, iclass 15, count 0 2006.257.19:46:59.86#ibcon#about to read 6, iclass 15, count 0 2006.257.19:46:59.86#ibcon#read 6, iclass 15, count 0 2006.257.19:46:59.86#ibcon#end of sib2, iclass 15, count 0 2006.257.19:46:59.86#ibcon#*after write, iclass 15, count 0 2006.257.19:46:59.86#ibcon#*before return 0, iclass 15, count 0 2006.257.19:46:59.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:59.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.19:46:59.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.19:46:59.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.19:46:59.86$vck44/vbbw=wide 2006.257.19:46:59.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.19:46:59.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.19:46:59.86#ibcon#ireg 8 cls_cnt 0 2006.257.19:46:59.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:46:59.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:46:59.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:46:59.93#ibcon#enter wrdev, iclass 17, count 0 2006.257.19:46:59.93#ibcon#first serial, iclass 17, count 0 2006.257.19:46:59.93#ibcon#enter sib2, iclass 17, count 0 2006.257.19:46:59.93#ibcon#flushed, iclass 17, count 0 2006.257.19:46:59.93#ibcon#about to write, iclass 17, count 0 2006.257.19:46:59.93#ibcon#wrote, iclass 17, count 0 2006.257.19:46:59.93#ibcon#about to read 3, iclass 17, count 0 2006.257.19:46:59.95#ibcon#read 3, iclass 17, count 0 2006.257.19:46:59.95#ibcon#about to read 4, iclass 17, count 0 2006.257.19:46:59.95#ibcon#read 4, iclass 17, count 0 2006.257.19:46:59.95#ibcon#about to read 5, iclass 17, count 0 2006.257.19:46:59.95#ibcon#read 5, iclass 17, count 0 2006.257.19:46:59.95#ibcon#about to read 6, iclass 17, count 0 2006.257.19:46:59.95#ibcon#read 6, iclass 17, count 0 2006.257.19:46:59.95#ibcon#end of sib2, iclass 17, count 0 2006.257.19:46:59.95#ibcon#*mode == 0, iclass 17, count 0 2006.257.19:46:59.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.19:46:59.95#ibcon#[27=BW32\r\n] 2006.257.19:46:59.95#ibcon#*before write, iclass 17, count 0 2006.257.19:46:59.95#ibcon#enter sib2, iclass 17, count 0 2006.257.19:46:59.95#ibcon#flushed, iclass 17, count 0 2006.257.19:46:59.95#ibcon#about to write, iclass 17, count 0 2006.257.19:46:59.95#ibcon#wrote, iclass 17, count 0 2006.257.19:46:59.95#ibcon#about to read 3, iclass 17, count 0 2006.257.19:46:59.98#ibcon#read 3, iclass 17, count 0 2006.257.19:46:59.98#ibcon#about to read 4, iclass 17, count 0 2006.257.19:46:59.98#ibcon#read 4, iclass 17, count 0 2006.257.19:46:59.98#ibcon#about to read 5, iclass 17, count 0 2006.257.19:46:59.98#ibcon#read 5, iclass 17, count 0 2006.257.19:46:59.98#ibcon#about to read 6, iclass 17, count 0 2006.257.19:46:59.98#ibcon#read 6, iclass 17, count 0 2006.257.19:46:59.98#ibcon#end of sib2, iclass 17, count 0 2006.257.19:46:59.98#ibcon#*after write, iclass 17, count 0 2006.257.19:46:59.98#ibcon#*before return 0, iclass 17, count 0 2006.257.19:46:59.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:46:59.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:46:59.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.19:46:59.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.19:46:59.98$setupk4/ifdk4 2006.257.19:46:59.98$ifdk4/lo= 2006.257.19:46:59.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.19:46:59.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.19:46:59.98$ifdk4/patch= 2006.257.19:46:59.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.19:46:59.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.19:46:59.98$setupk4/!*+20s 2006.257.19:47:02.36#abcon#<5=/14 1.5 4.3 17.52 961014.6\r\n> 2006.257.19:47:02.38#abcon#{5=INTERFACE CLEAR} 2006.257.19:47:02.44#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:47:12.53#abcon#<5=/14 1.5 4.4 17.52 961014.6\r\n> 2006.257.19:47:12.55#abcon#{5=INTERFACE CLEAR} 2006.257.19:47:12.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:47:14.48$setupk4/"tpicd 2006.257.19:47:14.48$setupk4/echo=off 2006.257.19:47:14.48$setupk4/xlog=off 2006.257.19:47:14.48:!2006.257.19:49:20 2006.257.19:47:45.14#trakl#Source acquired 2006.257.19:47:45.14#flagr#flagr/antenna,acquired 2006.257.19:49:20.00:preob 2006.257.19:49:20.14/onsource/TRACKING 2006.257.19:49:20.14:!2006.257.19:49:30 2006.257.19:49:30.00:"tape 2006.257.19:49:30.00:"st=record 2006.257.19:49:30.00:data_valid=on 2006.257.19:49:30.00:midob 2006.257.19:49:30.14/onsource/TRACKING 2006.257.19:49:30.14/wx/17.52,1014.6,96 2006.257.19:49:30.31/cable/+6.4865E-03 2006.257.19:49:31.40/va/01,08,usb,yes,31,34 2006.257.19:49:31.40/va/02,07,usb,yes,34,34 2006.257.19:49:31.40/va/03,08,usb,yes,30,32 2006.257.19:49:31.40/va/04,07,usb,yes,35,36 2006.257.19:49:31.40/va/05,04,usb,yes,31,32 2006.257.19:49:31.40/va/06,04,usb,yes,35,34 2006.257.19:49:31.40/va/07,04,usb,yes,36,36 2006.257.19:49:31.40/va/08,04,usb,yes,30,36 2006.257.19:49:31.63/valo/01,524.99,yes,locked 2006.257.19:49:31.63/valo/02,534.99,yes,locked 2006.257.19:49:31.63/valo/03,564.99,yes,locked 2006.257.19:49:31.63/valo/04,624.99,yes,locked 2006.257.19:49:31.63/valo/05,734.99,yes,locked 2006.257.19:49:31.63/valo/06,814.99,yes,locked 2006.257.19:49:31.63/valo/07,864.99,yes,locked 2006.257.19:49:31.63/valo/08,884.99,yes,locked 2006.257.19:49:32.72/vb/01,04,usb,yes,30,28 2006.257.19:49:32.72/vb/02,05,usb,yes,29,28 2006.257.19:49:32.72/vb/03,04,usb,yes,30,32 2006.257.19:49:32.72/vb/04,05,usb,yes,30,29 2006.257.19:49:32.72/vb/05,04,usb,yes,26,29 2006.257.19:49:32.72/vb/06,04,usb,yes,31,27 2006.257.19:49:32.72/vb/07,04,usb,yes,31,30 2006.257.19:49:32.72/vb/08,04,usb,yes,28,31 2006.257.19:49:32.95/vblo/01,629.99,yes,locked 2006.257.19:49:32.95/vblo/02,634.99,yes,locked 2006.257.19:49:32.95/vblo/03,649.99,yes,locked 2006.257.19:49:32.95/vblo/04,679.99,yes,locked 2006.257.19:49:32.95/vblo/05,709.99,yes,locked 2006.257.19:49:32.95/vblo/06,719.99,yes,locked 2006.257.19:49:32.95/vblo/07,734.99,yes,locked 2006.257.19:49:32.95/vblo/08,744.99,yes,locked 2006.257.19:49:33.10/vabw/8 2006.257.19:49:33.25/vbbw/8 2006.257.19:49:33.42/xfe/off,on,15.0 2006.257.19:49:33.80/ifatt/23,28,28,28 2006.257.19:49:34.08/fmout-gps/S +4.54E-07 2006.257.19:49:34.11:!2006.257.19:51:10 2006.257.19:51:10.02:data_valid=off 2006.257.19:51:10.02:"et 2006.257.19:51:10.02:!+3s 2006.257.19:51:13.04:"tape 2006.257.19:51:13.05:postob 2006.257.19:51:13.16/cable/+6.4850E-03 2006.257.19:51:13.16/wx/17.53,1014.6,96 2006.257.19:51:13.22/fmout-gps/S +4.53E-07 2006.257.19:51:13.22:scan_name=257-1952,jd0609,60 2006.257.19:51:13.22:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.257.19:51:15.15#flagr#flagr/antenna,new-source 2006.257.19:51:15.15:checkk5 2006.257.19:51:15.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.19:51:15.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.19:51:16.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.19:51:16.48/chk_autoobs//k5ts4/ autoobs is running! 2006.257.19:51:16.81/chk_obsdata//k5ts1/T2571949??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.19:51:17.14/chk_obsdata//k5ts2/T2571949??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.19:51:17.47/chk_obsdata//k5ts3/T2571949??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.19:51:17.80/chk_obsdata//k5ts4/T2571949??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.19:51:18.47/k5log//k5ts1_log_newline 2006.257.19:51:19.13/k5log//k5ts2_log_newline 2006.257.19:51:19.79/k5log//k5ts3_log_newline 2006.257.19:51:20.46/k5log//k5ts4_log_newline 2006.257.19:51:20.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.19:51:20.48:setupk4=1 2006.257.19:51:20.48$setupk4/echo=on 2006.257.19:51:20.48$setupk4/pcalon 2006.257.19:51:20.48$pcalon/"no phase cal control is implemented here 2006.257.19:51:20.48$setupk4/"tpicd=stop 2006.257.19:51:20.48$setupk4/"rec=synch_on 2006.257.19:51:20.48$setupk4/"rec_mode=128 2006.257.19:51:20.48$setupk4/!* 2006.257.19:51:20.48$setupk4/recpk4 2006.257.19:51:20.49$recpk4/recpatch= 2006.257.19:51:20.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.19:51:20.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.19:51:20.49$setupk4/vck44 2006.257.19:51:20.49$vck44/valo=1,524.99 2006.257.19:51:20.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.19:51:20.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.19:51:20.49#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:20.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:20.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:20.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:20.49#ibcon#enter wrdev, iclass 18, count 0 2006.257.19:51:20.49#ibcon#first serial, iclass 18, count 0 2006.257.19:51:20.49#ibcon#enter sib2, iclass 18, count 0 2006.257.19:51:20.49#ibcon#flushed, iclass 18, count 0 2006.257.19:51:20.49#ibcon#about to write, iclass 18, count 0 2006.257.19:51:20.49#ibcon#wrote, iclass 18, count 0 2006.257.19:51:20.49#ibcon#about to read 3, iclass 18, count 0 2006.257.19:51:20.51#ibcon#read 3, iclass 18, count 0 2006.257.19:51:20.51#ibcon#about to read 4, iclass 18, count 0 2006.257.19:51:20.51#ibcon#read 4, iclass 18, count 0 2006.257.19:51:20.51#ibcon#about to read 5, iclass 18, count 0 2006.257.19:51:20.51#ibcon#read 5, iclass 18, count 0 2006.257.19:51:20.51#ibcon#about to read 6, iclass 18, count 0 2006.257.19:51:20.51#ibcon#read 6, iclass 18, count 0 2006.257.19:51:20.51#ibcon#end of sib2, iclass 18, count 0 2006.257.19:51:20.51#ibcon#*mode == 0, iclass 18, count 0 2006.257.19:51:20.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.19:51:20.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.19:51:20.51#ibcon#*before write, iclass 18, count 0 2006.257.19:51:20.51#ibcon#enter sib2, iclass 18, count 0 2006.257.19:51:20.51#ibcon#flushed, iclass 18, count 0 2006.257.19:51:20.51#ibcon#about to write, iclass 18, count 0 2006.257.19:51:20.51#ibcon#wrote, iclass 18, count 0 2006.257.19:51:20.51#ibcon#about to read 3, iclass 18, count 0 2006.257.19:51:20.55#ibcon#read 3, iclass 18, count 0 2006.257.19:51:20.55#ibcon#about to read 4, iclass 18, count 0 2006.257.19:51:20.55#ibcon#read 4, iclass 18, count 0 2006.257.19:51:20.55#ibcon#about to read 5, iclass 18, count 0 2006.257.19:51:20.55#ibcon#read 5, iclass 18, count 0 2006.257.19:51:20.55#ibcon#about to read 6, iclass 18, count 0 2006.257.19:51:20.55#ibcon#read 6, iclass 18, count 0 2006.257.19:51:20.55#ibcon#end of sib2, iclass 18, count 0 2006.257.19:51:20.55#ibcon#*after write, iclass 18, count 0 2006.257.19:51:20.55#ibcon#*before return 0, iclass 18, count 0 2006.257.19:51:20.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:20.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:20.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.19:51:20.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.19:51:20.56$vck44/va=1,8 2006.257.19:51:20.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.19:51:20.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.19:51:20.56#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:20.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:20.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:20.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:20.56#ibcon#enter wrdev, iclass 20, count 2 2006.257.19:51:20.56#ibcon#first serial, iclass 20, count 2 2006.257.19:51:20.56#ibcon#enter sib2, iclass 20, count 2 2006.257.19:51:20.56#ibcon#flushed, iclass 20, count 2 2006.257.19:51:20.56#ibcon#about to write, iclass 20, count 2 2006.257.19:51:20.56#ibcon#wrote, iclass 20, count 2 2006.257.19:51:20.56#ibcon#about to read 3, iclass 20, count 2 2006.257.19:51:20.57#ibcon#read 3, iclass 20, count 2 2006.257.19:51:20.57#ibcon#about to read 4, iclass 20, count 2 2006.257.19:51:20.57#ibcon#read 4, iclass 20, count 2 2006.257.19:51:20.57#ibcon#about to read 5, iclass 20, count 2 2006.257.19:51:20.57#ibcon#read 5, iclass 20, count 2 2006.257.19:51:20.57#ibcon#about to read 6, iclass 20, count 2 2006.257.19:51:20.57#ibcon#read 6, iclass 20, count 2 2006.257.19:51:20.57#ibcon#end of sib2, iclass 20, count 2 2006.257.19:51:20.57#ibcon#*mode == 0, iclass 20, count 2 2006.257.19:51:20.57#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.19:51:20.58#ibcon#[25=AT01-08\r\n] 2006.257.19:51:20.58#ibcon#*before write, iclass 20, count 2 2006.257.19:51:20.58#ibcon#enter sib2, iclass 20, count 2 2006.257.19:51:20.58#ibcon#flushed, iclass 20, count 2 2006.257.19:51:20.58#ibcon#about to write, iclass 20, count 2 2006.257.19:51:20.58#ibcon#wrote, iclass 20, count 2 2006.257.19:51:20.58#ibcon#about to read 3, iclass 20, count 2 2006.257.19:51:20.60#ibcon#read 3, iclass 20, count 2 2006.257.19:51:20.60#ibcon#about to read 4, iclass 20, count 2 2006.257.19:51:20.60#ibcon#read 4, iclass 20, count 2 2006.257.19:51:20.60#ibcon#about to read 5, iclass 20, count 2 2006.257.19:51:20.60#ibcon#read 5, iclass 20, count 2 2006.257.19:51:20.60#ibcon#about to read 6, iclass 20, count 2 2006.257.19:51:20.60#ibcon#read 6, iclass 20, count 2 2006.257.19:51:20.60#ibcon#end of sib2, iclass 20, count 2 2006.257.19:51:20.60#ibcon#*after write, iclass 20, count 2 2006.257.19:51:20.60#ibcon#*before return 0, iclass 20, count 2 2006.257.19:51:20.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:20.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:20.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.19:51:20.61#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:20.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:20.72#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:20.72#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:20.72#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:51:20.72#ibcon#first serial, iclass 20, count 0 2006.257.19:51:20.72#ibcon#enter sib2, iclass 20, count 0 2006.257.19:51:20.72#ibcon#flushed, iclass 20, count 0 2006.257.19:51:20.72#ibcon#about to write, iclass 20, count 0 2006.257.19:51:20.72#ibcon#wrote, iclass 20, count 0 2006.257.19:51:20.72#ibcon#about to read 3, iclass 20, count 0 2006.257.19:51:20.74#ibcon#read 3, iclass 20, count 0 2006.257.19:51:20.74#ibcon#about to read 4, iclass 20, count 0 2006.257.19:51:20.74#ibcon#read 4, iclass 20, count 0 2006.257.19:51:20.74#ibcon#about to read 5, iclass 20, count 0 2006.257.19:51:20.74#ibcon#read 5, iclass 20, count 0 2006.257.19:51:20.74#ibcon#about to read 6, iclass 20, count 0 2006.257.19:51:20.74#ibcon#read 6, iclass 20, count 0 2006.257.19:51:20.74#ibcon#end of sib2, iclass 20, count 0 2006.257.19:51:20.74#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:51:20.74#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:51:20.74#ibcon#[25=USB\r\n] 2006.257.19:51:20.75#ibcon#*before write, iclass 20, count 0 2006.257.19:51:20.75#ibcon#enter sib2, iclass 20, count 0 2006.257.19:51:20.75#ibcon#flushed, iclass 20, count 0 2006.257.19:51:20.75#ibcon#about to write, iclass 20, count 0 2006.257.19:51:20.75#ibcon#wrote, iclass 20, count 0 2006.257.19:51:20.75#ibcon#about to read 3, iclass 20, count 0 2006.257.19:51:20.77#ibcon#read 3, iclass 20, count 0 2006.257.19:51:20.77#ibcon#about to read 4, iclass 20, count 0 2006.257.19:51:20.77#ibcon#read 4, iclass 20, count 0 2006.257.19:51:20.77#ibcon#about to read 5, iclass 20, count 0 2006.257.19:51:20.77#ibcon#read 5, iclass 20, count 0 2006.257.19:51:20.77#ibcon#about to read 6, iclass 20, count 0 2006.257.19:51:20.77#ibcon#read 6, iclass 20, count 0 2006.257.19:51:20.77#ibcon#end of sib2, iclass 20, count 0 2006.257.19:51:20.77#ibcon#*after write, iclass 20, count 0 2006.257.19:51:20.77#ibcon#*before return 0, iclass 20, count 0 2006.257.19:51:20.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:20.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:20.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:51:20.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:51:20.78$vck44/valo=2,534.99 2006.257.19:51:20.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.19:51:20.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.19:51:20.78#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:20.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:20.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:20.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:20.78#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:51:20.78#ibcon#first serial, iclass 22, count 0 2006.257.19:51:20.78#ibcon#enter sib2, iclass 22, count 0 2006.257.19:51:20.78#ibcon#flushed, iclass 22, count 0 2006.257.19:51:20.78#ibcon#about to write, iclass 22, count 0 2006.257.19:51:20.78#ibcon#wrote, iclass 22, count 0 2006.257.19:51:20.78#ibcon#about to read 3, iclass 22, count 0 2006.257.19:51:20.79#ibcon#read 3, iclass 22, count 0 2006.257.19:51:20.79#ibcon#about to read 4, iclass 22, count 0 2006.257.19:51:20.79#ibcon#read 4, iclass 22, count 0 2006.257.19:51:20.79#ibcon#about to read 5, iclass 22, count 0 2006.257.19:51:20.79#ibcon#read 5, iclass 22, count 0 2006.257.19:51:20.79#ibcon#about to read 6, iclass 22, count 0 2006.257.19:51:20.79#ibcon#read 6, iclass 22, count 0 2006.257.19:51:20.79#ibcon#end of sib2, iclass 22, count 0 2006.257.19:51:20.79#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:51:20.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:51:20.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.19:51:20.80#ibcon#*before write, iclass 22, count 0 2006.257.19:51:20.80#ibcon#enter sib2, iclass 22, count 0 2006.257.19:51:20.80#ibcon#flushed, iclass 22, count 0 2006.257.19:51:20.80#ibcon#about to write, iclass 22, count 0 2006.257.19:51:20.80#ibcon#wrote, iclass 22, count 0 2006.257.19:51:20.80#ibcon#about to read 3, iclass 22, count 0 2006.257.19:51:20.83#ibcon#read 3, iclass 22, count 0 2006.257.19:51:20.83#ibcon#about to read 4, iclass 22, count 0 2006.257.19:51:20.83#ibcon#read 4, iclass 22, count 0 2006.257.19:51:20.83#ibcon#about to read 5, iclass 22, count 0 2006.257.19:51:20.83#ibcon#read 5, iclass 22, count 0 2006.257.19:51:20.83#ibcon#about to read 6, iclass 22, count 0 2006.257.19:51:20.83#ibcon#read 6, iclass 22, count 0 2006.257.19:51:20.83#ibcon#end of sib2, iclass 22, count 0 2006.257.19:51:20.83#ibcon#*after write, iclass 22, count 0 2006.257.19:51:20.83#ibcon#*before return 0, iclass 22, count 0 2006.257.19:51:20.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:20.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:20.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:51:20.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:51:20.84$vck44/va=2,7 2006.257.19:51:20.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.19:51:20.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.19:51:20.84#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:20.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:20.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:20.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:20.89#ibcon#enter wrdev, iclass 24, count 2 2006.257.19:51:20.89#ibcon#first serial, iclass 24, count 2 2006.257.19:51:20.89#ibcon#enter sib2, iclass 24, count 2 2006.257.19:51:20.89#ibcon#flushed, iclass 24, count 2 2006.257.19:51:20.89#ibcon#about to write, iclass 24, count 2 2006.257.19:51:20.89#ibcon#wrote, iclass 24, count 2 2006.257.19:51:20.89#ibcon#about to read 3, iclass 24, count 2 2006.257.19:51:20.91#ibcon#read 3, iclass 24, count 2 2006.257.19:51:20.91#ibcon#about to read 4, iclass 24, count 2 2006.257.19:51:20.91#ibcon#read 4, iclass 24, count 2 2006.257.19:51:20.91#ibcon#about to read 5, iclass 24, count 2 2006.257.19:51:20.91#ibcon#read 5, iclass 24, count 2 2006.257.19:51:20.91#ibcon#about to read 6, iclass 24, count 2 2006.257.19:51:20.91#ibcon#read 6, iclass 24, count 2 2006.257.19:51:20.91#ibcon#end of sib2, iclass 24, count 2 2006.257.19:51:20.91#ibcon#*mode == 0, iclass 24, count 2 2006.257.19:51:20.91#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.19:51:20.91#ibcon#[25=AT02-07\r\n] 2006.257.19:51:20.92#ibcon#*before write, iclass 24, count 2 2006.257.19:51:20.92#ibcon#enter sib2, iclass 24, count 2 2006.257.19:51:20.92#ibcon#flushed, iclass 24, count 2 2006.257.19:51:20.92#ibcon#about to write, iclass 24, count 2 2006.257.19:51:20.92#ibcon#wrote, iclass 24, count 2 2006.257.19:51:20.92#ibcon#about to read 3, iclass 24, count 2 2006.257.19:51:20.94#ibcon#read 3, iclass 24, count 2 2006.257.19:51:20.94#ibcon#about to read 4, iclass 24, count 2 2006.257.19:51:20.94#ibcon#read 4, iclass 24, count 2 2006.257.19:51:20.94#ibcon#about to read 5, iclass 24, count 2 2006.257.19:51:20.94#ibcon#read 5, iclass 24, count 2 2006.257.19:51:20.94#ibcon#about to read 6, iclass 24, count 2 2006.257.19:51:20.94#ibcon#read 6, iclass 24, count 2 2006.257.19:51:20.94#ibcon#end of sib2, iclass 24, count 2 2006.257.19:51:20.94#ibcon#*after write, iclass 24, count 2 2006.257.19:51:20.94#ibcon#*before return 0, iclass 24, count 2 2006.257.19:51:20.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:20.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:20.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.19:51:20.95#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:20.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:21.06#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:21.06#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:21.06#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:51:21.06#ibcon#first serial, iclass 24, count 0 2006.257.19:51:21.06#ibcon#enter sib2, iclass 24, count 0 2006.257.19:51:21.06#ibcon#flushed, iclass 24, count 0 2006.257.19:51:21.06#ibcon#about to write, iclass 24, count 0 2006.257.19:51:21.06#ibcon#wrote, iclass 24, count 0 2006.257.19:51:21.06#ibcon#about to read 3, iclass 24, count 0 2006.257.19:51:21.08#ibcon#read 3, iclass 24, count 0 2006.257.19:51:21.08#ibcon#about to read 4, iclass 24, count 0 2006.257.19:51:21.08#ibcon#read 4, iclass 24, count 0 2006.257.19:51:21.08#ibcon#about to read 5, iclass 24, count 0 2006.257.19:51:21.08#ibcon#read 5, iclass 24, count 0 2006.257.19:51:21.08#ibcon#about to read 6, iclass 24, count 0 2006.257.19:51:21.08#ibcon#read 6, iclass 24, count 0 2006.257.19:51:21.08#ibcon#end of sib2, iclass 24, count 0 2006.257.19:51:21.08#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:51:21.08#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:51:21.08#ibcon#[25=USB\r\n] 2006.257.19:51:21.09#ibcon#*before write, iclass 24, count 0 2006.257.19:51:21.09#ibcon#enter sib2, iclass 24, count 0 2006.257.19:51:21.09#ibcon#flushed, iclass 24, count 0 2006.257.19:51:21.09#ibcon#about to write, iclass 24, count 0 2006.257.19:51:21.09#ibcon#wrote, iclass 24, count 0 2006.257.19:51:21.09#ibcon#about to read 3, iclass 24, count 0 2006.257.19:51:21.11#ibcon#read 3, iclass 24, count 0 2006.257.19:51:21.11#ibcon#about to read 4, iclass 24, count 0 2006.257.19:51:21.11#ibcon#read 4, iclass 24, count 0 2006.257.19:51:21.11#ibcon#about to read 5, iclass 24, count 0 2006.257.19:51:21.11#ibcon#read 5, iclass 24, count 0 2006.257.19:51:21.11#ibcon#about to read 6, iclass 24, count 0 2006.257.19:51:21.11#ibcon#read 6, iclass 24, count 0 2006.257.19:51:21.11#ibcon#end of sib2, iclass 24, count 0 2006.257.19:51:21.11#ibcon#*after write, iclass 24, count 0 2006.257.19:51:21.11#ibcon#*before return 0, iclass 24, count 0 2006.257.19:51:21.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:21.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:21.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:51:21.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:51:21.12$vck44/valo=3,564.99 2006.257.19:51:21.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.19:51:21.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.19:51:21.12#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:21.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:21.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:21.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:21.12#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:51:21.12#ibcon#first serial, iclass 26, count 0 2006.257.19:51:21.12#ibcon#enter sib2, iclass 26, count 0 2006.257.19:51:21.12#ibcon#flushed, iclass 26, count 0 2006.257.19:51:21.12#ibcon#about to write, iclass 26, count 0 2006.257.19:51:21.12#ibcon#wrote, iclass 26, count 0 2006.257.19:51:21.12#ibcon#about to read 3, iclass 26, count 0 2006.257.19:51:21.13#ibcon#read 3, iclass 26, count 0 2006.257.19:51:21.13#ibcon#about to read 4, iclass 26, count 0 2006.257.19:51:21.13#ibcon#read 4, iclass 26, count 0 2006.257.19:51:21.13#ibcon#about to read 5, iclass 26, count 0 2006.257.19:51:21.13#ibcon#read 5, iclass 26, count 0 2006.257.19:51:21.13#ibcon#about to read 6, iclass 26, count 0 2006.257.19:51:21.13#ibcon#read 6, iclass 26, count 0 2006.257.19:51:21.13#ibcon#end of sib2, iclass 26, count 0 2006.257.19:51:21.13#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:51:21.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:51:21.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.19:51:21.14#ibcon#*before write, iclass 26, count 0 2006.257.19:51:21.14#ibcon#enter sib2, iclass 26, count 0 2006.257.19:51:21.14#ibcon#flushed, iclass 26, count 0 2006.257.19:51:21.14#ibcon#about to write, iclass 26, count 0 2006.257.19:51:21.14#ibcon#wrote, iclass 26, count 0 2006.257.19:51:21.14#ibcon#about to read 3, iclass 26, count 0 2006.257.19:51:21.17#ibcon#read 3, iclass 26, count 0 2006.257.19:51:21.17#ibcon#about to read 4, iclass 26, count 0 2006.257.19:51:21.17#ibcon#read 4, iclass 26, count 0 2006.257.19:51:21.17#ibcon#about to read 5, iclass 26, count 0 2006.257.19:51:21.17#ibcon#read 5, iclass 26, count 0 2006.257.19:51:21.17#ibcon#about to read 6, iclass 26, count 0 2006.257.19:51:21.17#ibcon#read 6, iclass 26, count 0 2006.257.19:51:21.17#ibcon#end of sib2, iclass 26, count 0 2006.257.19:51:21.17#ibcon#*after write, iclass 26, count 0 2006.257.19:51:21.17#ibcon#*before return 0, iclass 26, count 0 2006.257.19:51:21.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:21.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:21.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:51:21.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:51:21.18$vck44/va=3,8 2006.257.19:51:21.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.19:51:21.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.19:51:21.18#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:21.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:21.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:21.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:21.23#ibcon#enter wrdev, iclass 28, count 2 2006.257.19:51:21.23#ibcon#first serial, iclass 28, count 2 2006.257.19:51:21.23#ibcon#enter sib2, iclass 28, count 2 2006.257.19:51:21.23#ibcon#flushed, iclass 28, count 2 2006.257.19:51:21.23#ibcon#about to write, iclass 28, count 2 2006.257.19:51:21.23#ibcon#wrote, iclass 28, count 2 2006.257.19:51:21.23#ibcon#about to read 3, iclass 28, count 2 2006.257.19:51:21.25#ibcon#read 3, iclass 28, count 2 2006.257.19:51:21.25#ibcon#about to read 4, iclass 28, count 2 2006.257.19:51:21.25#ibcon#read 4, iclass 28, count 2 2006.257.19:51:21.25#ibcon#about to read 5, iclass 28, count 2 2006.257.19:51:21.25#ibcon#read 5, iclass 28, count 2 2006.257.19:51:21.25#ibcon#about to read 6, iclass 28, count 2 2006.257.19:51:21.25#ibcon#read 6, iclass 28, count 2 2006.257.19:51:21.25#ibcon#end of sib2, iclass 28, count 2 2006.257.19:51:21.25#ibcon#*mode == 0, iclass 28, count 2 2006.257.19:51:21.25#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.19:51:21.25#ibcon#[25=AT03-08\r\n] 2006.257.19:51:21.26#ibcon#*before write, iclass 28, count 2 2006.257.19:51:21.26#ibcon#enter sib2, iclass 28, count 2 2006.257.19:51:21.26#ibcon#flushed, iclass 28, count 2 2006.257.19:51:21.26#ibcon#about to write, iclass 28, count 2 2006.257.19:51:21.26#ibcon#wrote, iclass 28, count 2 2006.257.19:51:21.26#ibcon#about to read 3, iclass 28, count 2 2006.257.19:51:21.28#ibcon#read 3, iclass 28, count 2 2006.257.19:51:21.28#ibcon#about to read 4, iclass 28, count 2 2006.257.19:51:21.28#ibcon#read 4, iclass 28, count 2 2006.257.19:51:21.28#ibcon#about to read 5, iclass 28, count 2 2006.257.19:51:21.28#ibcon#read 5, iclass 28, count 2 2006.257.19:51:21.28#ibcon#about to read 6, iclass 28, count 2 2006.257.19:51:21.28#ibcon#read 6, iclass 28, count 2 2006.257.19:51:21.28#ibcon#end of sib2, iclass 28, count 2 2006.257.19:51:21.28#ibcon#*after write, iclass 28, count 2 2006.257.19:51:21.28#ibcon#*before return 0, iclass 28, count 2 2006.257.19:51:21.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:21.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:21.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.19:51:21.29#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:21.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:21.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:21.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:21.40#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:51:21.40#ibcon#first serial, iclass 28, count 0 2006.257.19:51:21.40#ibcon#enter sib2, iclass 28, count 0 2006.257.19:51:21.40#ibcon#flushed, iclass 28, count 0 2006.257.19:51:21.40#ibcon#about to write, iclass 28, count 0 2006.257.19:51:21.40#ibcon#wrote, iclass 28, count 0 2006.257.19:51:21.40#ibcon#about to read 3, iclass 28, count 0 2006.257.19:51:21.42#ibcon#read 3, iclass 28, count 0 2006.257.19:51:21.42#ibcon#about to read 4, iclass 28, count 0 2006.257.19:51:21.42#ibcon#read 4, iclass 28, count 0 2006.257.19:51:21.42#ibcon#about to read 5, iclass 28, count 0 2006.257.19:51:21.42#ibcon#read 5, iclass 28, count 0 2006.257.19:51:21.42#ibcon#about to read 6, iclass 28, count 0 2006.257.19:51:21.42#ibcon#read 6, iclass 28, count 0 2006.257.19:51:21.42#ibcon#end of sib2, iclass 28, count 0 2006.257.19:51:21.42#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:51:21.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:51:21.42#ibcon#[25=USB\r\n] 2006.257.19:51:21.43#ibcon#*before write, iclass 28, count 0 2006.257.19:51:21.43#ibcon#enter sib2, iclass 28, count 0 2006.257.19:51:21.43#ibcon#flushed, iclass 28, count 0 2006.257.19:51:21.43#ibcon#about to write, iclass 28, count 0 2006.257.19:51:21.43#ibcon#wrote, iclass 28, count 0 2006.257.19:51:21.43#ibcon#about to read 3, iclass 28, count 0 2006.257.19:51:21.45#ibcon#read 3, iclass 28, count 0 2006.257.19:51:21.45#ibcon#about to read 4, iclass 28, count 0 2006.257.19:51:21.45#ibcon#read 4, iclass 28, count 0 2006.257.19:51:21.45#ibcon#about to read 5, iclass 28, count 0 2006.257.19:51:21.45#ibcon#read 5, iclass 28, count 0 2006.257.19:51:21.45#ibcon#about to read 6, iclass 28, count 0 2006.257.19:51:21.45#ibcon#read 6, iclass 28, count 0 2006.257.19:51:21.45#ibcon#end of sib2, iclass 28, count 0 2006.257.19:51:21.45#ibcon#*after write, iclass 28, count 0 2006.257.19:51:21.45#ibcon#*before return 0, iclass 28, count 0 2006.257.19:51:21.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:21.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:21.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:51:21.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:51:21.46$vck44/valo=4,624.99 2006.257.19:51:21.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.19:51:21.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.19:51:21.46#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:21.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:21.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:21.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:21.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.19:51:21.46#ibcon#first serial, iclass 30, count 0 2006.257.19:51:21.46#ibcon#enter sib2, iclass 30, count 0 2006.257.19:51:21.46#ibcon#flushed, iclass 30, count 0 2006.257.19:51:21.46#ibcon#about to write, iclass 30, count 0 2006.257.19:51:21.46#ibcon#wrote, iclass 30, count 0 2006.257.19:51:21.46#ibcon#about to read 3, iclass 30, count 0 2006.257.19:51:21.47#ibcon#read 3, iclass 30, count 0 2006.257.19:51:21.47#ibcon#about to read 4, iclass 30, count 0 2006.257.19:51:21.47#ibcon#read 4, iclass 30, count 0 2006.257.19:51:21.47#ibcon#about to read 5, iclass 30, count 0 2006.257.19:51:21.47#ibcon#read 5, iclass 30, count 0 2006.257.19:51:21.47#ibcon#about to read 6, iclass 30, count 0 2006.257.19:51:21.47#ibcon#read 6, iclass 30, count 0 2006.257.19:51:21.47#ibcon#end of sib2, iclass 30, count 0 2006.257.19:51:21.47#ibcon#*mode == 0, iclass 30, count 0 2006.257.19:51:21.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.19:51:21.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.19:51:21.48#ibcon#*before write, iclass 30, count 0 2006.257.19:51:21.48#ibcon#enter sib2, iclass 30, count 0 2006.257.19:51:21.48#ibcon#flushed, iclass 30, count 0 2006.257.19:51:21.48#ibcon#about to write, iclass 30, count 0 2006.257.19:51:21.48#ibcon#wrote, iclass 30, count 0 2006.257.19:51:21.48#ibcon#about to read 3, iclass 30, count 0 2006.257.19:51:21.51#ibcon#read 3, iclass 30, count 0 2006.257.19:51:21.51#ibcon#about to read 4, iclass 30, count 0 2006.257.19:51:21.51#ibcon#read 4, iclass 30, count 0 2006.257.19:51:21.51#ibcon#about to read 5, iclass 30, count 0 2006.257.19:51:21.51#ibcon#read 5, iclass 30, count 0 2006.257.19:51:21.51#ibcon#about to read 6, iclass 30, count 0 2006.257.19:51:21.51#ibcon#read 6, iclass 30, count 0 2006.257.19:51:21.51#ibcon#end of sib2, iclass 30, count 0 2006.257.19:51:21.51#ibcon#*after write, iclass 30, count 0 2006.257.19:51:21.51#ibcon#*before return 0, iclass 30, count 0 2006.257.19:51:21.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:21.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:21.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.19:51:21.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.19:51:21.52$vck44/va=4,7 2006.257.19:51:21.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.19:51:21.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.19:51:21.52#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:21.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:21.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:21.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:21.57#ibcon#enter wrdev, iclass 32, count 2 2006.257.19:51:21.58#ibcon#first serial, iclass 32, count 2 2006.257.19:51:21.58#ibcon#enter sib2, iclass 32, count 2 2006.257.19:51:21.58#ibcon#flushed, iclass 32, count 2 2006.257.19:51:21.58#ibcon#about to write, iclass 32, count 2 2006.257.19:51:21.58#ibcon#wrote, iclass 32, count 2 2006.257.19:51:21.58#ibcon#about to read 3, iclass 32, count 2 2006.257.19:51:21.59#ibcon#read 3, iclass 32, count 2 2006.257.19:51:21.59#ibcon#about to read 4, iclass 32, count 2 2006.257.19:51:21.59#ibcon#read 4, iclass 32, count 2 2006.257.19:51:21.59#ibcon#about to read 5, iclass 32, count 2 2006.257.19:51:21.59#ibcon#read 5, iclass 32, count 2 2006.257.19:51:21.59#ibcon#about to read 6, iclass 32, count 2 2006.257.19:51:21.59#ibcon#read 6, iclass 32, count 2 2006.257.19:51:21.59#ibcon#end of sib2, iclass 32, count 2 2006.257.19:51:21.59#ibcon#*mode == 0, iclass 32, count 2 2006.257.19:51:21.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.19:51:21.59#ibcon#[25=AT04-07\r\n] 2006.257.19:51:21.60#ibcon#*before write, iclass 32, count 2 2006.257.19:51:21.60#ibcon#enter sib2, iclass 32, count 2 2006.257.19:51:21.60#ibcon#flushed, iclass 32, count 2 2006.257.19:51:21.60#ibcon#about to write, iclass 32, count 2 2006.257.19:51:21.60#ibcon#wrote, iclass 32, count 2 2006.257.19:51:21.60#ibcon#about to read 3, iclass 32, count 2 2006.257.19:51:21.62#ibcon#read 3, iclass 32, count 2 2006.257.19:51:21.62#ibcon#about to read 4, iclass 32, count 2 2006.257.19:51:21.62#ibcon#read 4, iclass 32, count 2 2006.257.19:51:21.62#ibcon#about to read 5, iclass 32, count 2 2006.257.19:51:21.62#ibcon#read 5, iclass 32, count 2 2006.257.19:51:21.62#ibcon#about to read 6, iclass 32, count 2 2006.257.19:51:21.62#ibcon#read 6, iclass 32, count 2 2006.257.19:51:21.62#ibcon#end of sib2, iclass 32, count 2 2006.257.19:51:21.62#ibcon#*after write, iclass 32, count 2 2006.257.19:51:21.62#ibcon#*before return 0, iclass 32, count 2 2006.257.19:51:21.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:21.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:21.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.19:51:21.63#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:21.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:21.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:21.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:21.74#ibcon#enter wrdev, iclass 32, count 0 2006.257.19:51:21.74#ibcon#first serial, iclass 32, count 0 2006.257.19:51:21.74#ibcon#enter sib2, iclass 32, count 0 2006.257.19:51:21.74#ibcon#flushed, iclass 32, count 0 2006.257.19:51:21.74#ibcon#about to write, iclass 32, count 0 2006.257.19:51:21.74#ibcon#wrote, iclass 32, count 0 2006.257.19:51:21.74#ibcon#about to read 3, iclass 32, count 0 2006.257.19:51:21.76#ibcon#read 3, iclass 32, count 0 2006.257.19:51:21.76#ibcon#about to read 4, iclass 32, count 0 2006.257.19:51:21.76#ibcon#read 4, iclass 32, count 0 2006.257.19:51:21.76#ibcon#about to read 5, iclass 32, count 0 2006.257.19:51:21.76#ibcon#read 5, iclass 32, count 0 2006.257.19:51:21.76#ibcon#about to read 6, iclass 32, count 0 2006.257.19:51:21.76#ibcon#read 6, iclass 32, count 0 2006.257.19:51:21.76#ibcon#end of sib2, iclass 32, count 0 2006.257.19:51:21.76#ibcon#*mode == 0, iclass 32, count 0 2006.257.19:51:21.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.19:51:21.76#ibcon#[25=USB\r\n] 2006.257.19:51:21.77#ibcon#*before write, iclass 32, count 0 2006.257.19:51:21.77#ibcon#enter sib2, iclass 32, count 0 2006.257.19:51:21.77#ibcon#flushed, iclass 32, count 0 2006.257.19:51:21.77#ibcon#about to write, iclass 32, count 0 2006.257.19:51:21.77#ibcon#wrote, iclass 32, count 0 2006.257.19:51:21.77#ibcon#about to read 3, iclass 32, count 0 2006.257.19:51:21.79#ibcon#read 3, iclass 32, count 0 2006.257.19:51:21.79#ibcon#about to read 4, iclass 32, count 0 2006.257.19:51:21.79#ibcon#read 4, iclass 32, count 0 2006.257.19:51:21.79#ibcon#about to read 5, iclass 32, count 0 2006.257.19:51:21.79#ibcon#read 5, iclass 32, count 0 2006.257.19:51:21.79#ibcon#about to read 6, iclass 32, count 0 2006.257.19:51:21.79#ibcon#read 6, iclass 32, count 0 2006.257.19:51:21.79#ibcon#end of sib2, iclass 32, count 0 2006.257.19:51:21.79#ibcon#*after write, iclass 32, count 0 2006.257.19:51:21.79#ibcon#*before return 0, iclass 32, count 0 2006.257.19:51:21.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:21.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:21.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.19:51:21.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.19:51:21.80$vck44/valo=5,734.99 2006.257.19:51:21.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.19:51:21.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.19:51:21.80#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:21.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:21.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:21.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:21.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.19:51:21.80#ibcon#first serial, iclass 34, count 0 2006.257.19:51:21.80#ibcon#enter sib2, iclass 34, count 0 2006.257.19:51:21.80#ibcon#flushed, iclass 34, count 0 2006.257.19:51:21.80#ibcon#about to write, iclass 34, count 0 2006.257.19:51:21.80#ibcon#wrote, iclass 34, count 0 2006.257.19:51:21.80#ibcon#about to read 3, iclass 34, count 0 2006.257.19:51:21.81#ibcon#read 3, iclass 34, count 0 2006.257.19:51:21.81#ibcon#about to read 4, iclass 34, count 0 2006.257.19:51:21.81#ibcon#read 4, iclass 34, count 0 2006.257.19:51:21.81#ibcon#about to read 5, iclass 34, count 0 2006.257.19:51:21.81#ibcon#read 5, iclass 34, count 0 2006.257.19:51:21.81#ibcon#about to read 6, iclass 34, count 0 2006.257.19:51:21.81#ibcon#read 6, iclass 34, count 0 2006.257.19:51:21.81#ibcon#end of sib2, iclass 34, count 0 2006.257.19:51:21.81#ibcon#*mode == 0, iclass 34, count 0 2006.257.19:51:21.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.19:51:21.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.19:51:21.82#ibcon#*before write, iclass 34, count 0 2006.257.19:51:21.82#ibcon#enter sib2, iclass 34, count 0 2006.257.19:51:21.82#ibcon#flushed, iclass 34, count 0 2006.257.19:51:21.82#ibcon#about to write, iclass 34, count 0 2006.257.19:51:21.82#ibcon#wrote, iclass 34, count 0 2006.257.19:51:21.82#ibcon#about to read 3, iclass 34, count 0 2006.257.19:51:21.85#ibcon#read 3, iclass 34, count 0 2006.257.19:51:21.85#ibcon#about to read 4, iclass 34, count 0 2006.257.19:51:21.85#ibcon#read 4, iclass 34, count 0 2006.257.19:51:21.85#ibcon#about to read 5, iclass 34, count 0 2006.257.19:51:21.85#ibcon#read 5, iclass 34, count 0 2006.257.19:51:21.85#ibcon#about to read 6, iclass 34, count 0 2006.257.19:51:21.85#ibcon#read 6, iclass 34, count 0 2006.257.19:51:21.85#ibcon#end of sib2, iclass 34, count 0 2006.257.19:51:21.85#ibcon#*after write, iclass 34, count 0 2006.257.19:51:21.85#ibcon#*before return 0, iclass 34, count 0 2006.257.19:51:21.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:21.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:21.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.19:51:21.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.19:51:21.86$vck44/va=5,4 2006.257.19:51:21.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.19:51:21.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.19:51:21.86#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:21.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:21.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:21.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:21.91#ibcon#enter wrdev, iclass 36, count 2 2006.257.19:51:21.91#ibcon#first serial, iclass 36, count 2 2006.257.19:51:21.91#ibcon#enter sib2, iclass 36, count 2 2006.257.19:51:21.91#ibcon#flushed, iclass 36, count 2 2006.257.19:51:21.91#ibcon#about to write, iclass 36, count 2 2006.257.19:51:21.91#ibcon#wrote, iclass 36, count 2 2006.257.19:51:21.91#ibcon#about to read 3, iclass 36, count 2 2006.257.19:51:21.93#ibcon#read 3, iclass 36, count 2 2006.257.19:51:21.93#ibcon#about to read 4, iclass 36, count 2 2006.257.19:51:21.93#ibcon#read 4, iclass 36, count 2 2006.257.19:51:21.93#ibcon#about to read 5, iclass 36, count 2 2006.257.19:51:21.93#ibcon#read 5, iclass 36, count 2 2006.257.19:51:21.93#ibcon#about to read 6, iclass 36, count 2 2006.257.19:51:21.93#ibcon#read 6, iclass 36, count 2 2006.257.19:51:21.93#ibcon#end of sib2, iclass 36, count 2 2006.257.19:51:21.93#ibcon#*mode == 0, iclass 36, count 2 2006.257.19:51:21.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.19:51:21.93#ibcon#[25=AT05-04\r\n] 2006.257.19:51:21.93#ibcon#*before write, iclass 36, count 2 2006.257.19:51:21.94#ibcon#enter sib2, iclass 36, count 2 2006.257.19:51:21.94#ibcon#flushed, iclass 36, count 2 2006.257.19:51:21.94#ibcon#about to write, iclass 36, count 2 2006.257.19:51:21.94#ibcon#wrote, iclass 36, count 2 2006.257.19:51:21.94#ibcon#about to read 3, iclass 36, count 2 2006.257.19:51:21.96#ibcon#read 3, iclass 36, count 2 2006.257.19:51:21.96#ibcon#about to read 4, iclass 36, count 2 2006.257.19:51:21.96#ibcon#read 4, iclass 36, count 2 2006.257.19:51:21.96#ibcon#about to read 5, iclass 36, count 2 2006.257.19:51:21.96#ibcon#read 5, iclass 36, count 2 2006.257.19:51:21.96#ibcon#about to read 6, iclass 36, count 2 2006.257.19:51:21.96#ibcon#read 6, iclass 36, count 2 2006.257.19:51:21.96#ibcon#end of sib2, iclass 36, count 2 2006.257.19:51:21.96#ibcon#*after write, iclass 36, count 2 2006.257.19:51:21.96#ibcon#*before return 0, iclass 36, count 2 2006.257.19:51:21.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:21.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:21.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.19:51:21.97#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:21.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:22.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:22.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:22.08#ibcon#enter wrdev, iclass 36, count 0 2006.257.19:51:22.08#ibcon#first serial, iclass 36, count 0 2006.257.19:51:22.08#ibcon#enter sib2, iclass 36, count 0 2006.257.19:51:22.08#ibcon#flushed, iclass 36, count 0 2006.257.19:51:22.08#ibcon#about to write, iclass 36, count 0 2006.257.19:51:22.08#ibcon#wrote, iclass 36, count 0 2006.257.19:51:22.08#ibcon#about to read 3, iclass 36, count 0 2006.257.19:51:22.10#ibcon#read 3, iclass 36, count 0 2006.257.19:51:22.10#ibcon#about to read 4, iclass 36, count 0 2006.257.19:51:22.10#ibcon#read 4, iclass 36, count 0 2006.257.19:51:22.10#ibcon#about to read 5, iclass 36, count 0 2006.257.19:51:22.10#ibcon#read 5, iclass 36, count 0 2006.257.19:51:22.10#ibcon#about to read 6, iclass 36, count 0 2006.257.19:51:22.10#ibcon#read 6, iclass 36, count 0 2006.257.19:51:22.10#ibcon#end of sib2, iclass 36, count 0 2006.257.19:51:22.10#ibcon#*mode == 0, iclass 36, count 0 2006.257.19:51:22.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.19:51:22.10#ibcon#[25=USB\r\n] 2006.257.19:51:22.10#ibcon#*before write, iclass 36, count 0 2006.257.19:51:22.11#ibcon#enter sib2, iclass 36, count 0 2006.257.19:51:22.11#ibcon#flushed, iclass 36, count 0 2006.257.19:51:22.11#ibcon#about to write, iclass 36, count 0 2006.257.19:51:22.11#ibcon#wrote, iclass 36, count 0 2006.257.19:51:22.11#ibcon#about to read 3, iclass 36, count 0 2006.257.19:51:22.13#ibcon#read 3, iclass 36, count 0 2006.257.19:51:22.13#ibcon#about to read 4, iclass 36, count 0 2006.257.19:51:22.13#ibcon#read 4, iclass 36, count 0 2006.257.19:51:22.13#ibcon#about to read 5, iclass 36, count 0 2006.257.19:51:22.13#ibcon#read 5, iclass 36, count 0 2006.257.19:51:22.13#ibcon#about to read 6, iclass 36, count 0 2006.257.19:51:22.13#ibcon#read 6, iclass 36, count 0 2006.257.19:51:22.13#ibcon#end of sib2, iclass 36, count 0 2006.257.19:51:22.13#ibcon#*after write, iclass 36, count 0 2006.257.19:51:22.14#ibcon#*before return 0, iclass 36, count 0 2006.257.19:51:22.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:22.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:22.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.19:51:22.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.19:51:22.14$vck44/valo=6,814.99 2006.257.19:51:22.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.19:51:22.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.19:51:22.14#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:22.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:22.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:22.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:22.14#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:51:22.14#ibcon#first serial, iclass 38, count 0 2006.257.19:51:22.14#ibcon#enter sib2, iclass 38, count 0 2006.257.19:51:22.14#ibcon#flushed, iclass 38, count 0 2006.257.19:51:22.14#ibcon#about to write, iclass 38, count 0 2006.257.19:51:22.14#ibcon#wrote, iclass 38, count 0 2006.257.19:51:22.14#ibcon#about to read 3, iclass 38, count 0 2006.257.19:51:22.15#ibcon#read 3, iclass 38, count 0 2006.257.19:51:22.15#ibcon#about to read 4, iclass 38, count 0 2006.257.19:51:22.15#ibcon#read 4, iclass 38, count 0 2006.257.19:51:22.15#ibcon#about to read 5, iclass 38, count 0 2006.257.19:51:22.15#ibcon#read 5, iclass 38, count 0 2006.257.19:51:22.15#ibcon#about to read 6, iclass 38, count 0 2006.257.19:51:22.15#ibcon#read 6, iclass 38, count 0 2006.257.19:51:22.15#ibcon#end of sib2, iclass 38, count 0 2006.257.19:51:22.15#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:51:22.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:51:22.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.19:51:22.16#ibcon#*before write, iclass 38, count 0 2006.257.19:51:22.16#ibcon#enter sib2, iclass 38, count 0 2006.257.19:51:22.16#ibcon#flushed, iclass 38, count 0 2006.257.19:51:22.16#ibcon#about to write, iclass 38, count 0 2006.257.19:51:22.16#ibcon#wrote, iclass 38, count 0 2006.257.19:51:22.16#ibcon#about to read 3, iclass 38, count 0 2006.257.19:51:22.19#ibcon#read 3, iclass 38, count 0 2006.257.19:51:22.19#ibcon#about to read 4, iclass 38, count 0 2006.257.19:51:22.19#ibcon#read 4, iclass 38, count 0 2006.257.19:51:22.19#ibcon#about to read 5, iclass 38, count 0 2006.257.19:51:22.19#ibcon#read 5, iclass 38, count 0 2006.257.19:51:22.19#ibcon#about to read 6, iclass 38, count 0 2006.257.19:51:22.19#ibcon#read 6, iclass 38, count 0 2006.257.19:51:22.19#ibcon#end of sib2, iclass 38, count 0 2006.257.19:51:22.19#ibcon#*after write, iclass 38, count 0 2006.257.19:51:22.19#ibcon#*before return 0, iclass 38, count 0 2006.257.19:51:22.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:22.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:22.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:51:22.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:51:22.20$vck44/va=6,4 2006.257.19:51:22.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.19:51:22.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.19:51:22.20#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:22.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:22.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:22.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:22.25#ibcon#enter wrdev, iclass 40, count 2 2006.257.19:51:22.25#ibcon#first serial, iclass 40, count 2 2006.257.19:51:22.25#ibcon#enter sib2, iclass 40, count 2 2006.257.19:51:22.25#ibcon#flushed, iclass 40, count 2 2006.257.19:51:22.25#ibcon#about to write, iclass 40, count 2 2006.257.19:51:22.25#ibcon#wrote, iclass 40, count 2 2006.257.19:51:22.25#ibcon#about to read 3, iclass 40, count 2 2006.257.19:51:22.27#ibcon#read 3, iclass 40, count 2 2006.257.19:51:22.27#ibcon#about to read 4, iclass 40, count 2 2006.257.19:51:22.27#ibcon#read 4, iclass 40, count 2 2006.257.19:51:22.27#ibcon#about to read 5, iclass 40, count 2 2006.257.19:51:22.27#ibcon#read 5, iclass 40, count 2 2006.257.19:51:22.27#ibcon#about to read 6, iclass 40, count 2 2006.257.19:51:22.27#ibcon#read 6, iclass 40, count 2 2006.257.19:51:22.27#ibcon#end of sib2, iclass 40, count 2 2006.257.19:51:22.27#ibcon#*mode == 0, iclass 40, count 2 2006.257.19:51:22.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.19:51:22.27#ibcon#[25=AT06-04\r\n] 2006.257.19:51:22.27#ibcon#*before write, iclass 40, count 2 2006.257.19:51:22.28#ibcon#enter sib2, iclass 40, count 2 2006.257.19:51:22.28#ibcon#flushed, iclass 40, count 2 2006.257.19:51:22.28#ibcon#about to write, iclass 40, count 2 2006.257.19:51:22.28#ibcon#wrote, iclass 40, count 2 2006.257.19:51:22.28#ibcon#about to read 3, iclass 40, count 2 2006.257.19:51:22.30#ibcon#read 3, iclass 40, count 2 2006.257.19:51:22.30#ibcon#about to read 4, iclass 40, count 2 2006.257.19:51:22.30#ibcon#read 4, iclass 40, count 2 2006.257.19:51:22.30#ibcon#about to read 5, iclass 40, count 2 2006.257.19:51:22.30#ibcon#read 5, iclass 40, count 2 2006.257.19:51:22.30#ibcon#about to read 6, iclass 40, count 2 2006.257.19:51:22.30#ibcon#read 6, iclass 40, count 2 2006.257.19:51:22.30#ibcon#end of sib2, iclass 40, count 2 2006.257.19:51:22.30#ibcon#*after write, iclass 40, count 2 2006.257.19:51:22.30#ibcon#*before return 0, iclass 40, count 2 2006.257.19:51:22.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:22.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:22.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.19:51:22.31#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:22.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:22.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:22.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:22.42#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:51:22.42#ibcon#first serial, iclass 40, count 0 2006.257.19:51:22.42#ibcon#enter sib2, iclass 40, count 0 2006.257.19:51:22.42#ibcon#flushed, iclass 40, count 0 2006.257.19:51:22.42#ibcon#about to write, iclass 40, count 0 2006.257.19:51:22.42#ibcon#wrote, iclass 40, count 0 2006.257.19:51:22.42#ibcon#about to read 3, iclass 40, count 0 2006.257.19:51:22.44#ibcon#read 3, iclass 40, count 0 2006.257.19:51:22.44#ibcon#about to read 4, iclass 40, count 0 2006.257.19:51:22.44#ibcon#read 4, iclass 40, count 0 2006.257.19:51:22.44#ibcon#about to read 5, iclass 40, count 0 2006.257.19:51:22.44#ibcon#read 5, iclass 40, count 0 2006.257.19:51:22.44#ibcon#about to read 6, iclass 40, count 0 2006.257.19:51:22.44#ibcon#read 6, iclass 40, count 0 2006.257.19:51:22.44#ibcon#end of sib2, iclass 40, count 0 2006.257.19:51:22.44#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:51:22.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:51:22.44#ibcon#[25=USB\r\n] 2006.257.19:51:22.44#ibcon#*before write, iclass 40, count 0 2006.257.19:51:22.45#ibcon#enter sib2, iclass 40, count 0 2006.257.19:51:22.45#ibcon#flushed, iclass 40, count 0 2006.257.19:51:22.45#ibcon#about to write, iclass 40, count 0 2006.257.19:51:22.45#ibcon#wrote, iclass 40, count 0 2006.257.19:51:22.45#ibcon#about to read 3, iclass 40, count 0 2006.257.19:51:22.47#ibcon#read 3, iclass 40, count 0 2006.257.19:51:22.47#ibcon#about to read 4, iclass 40, count 0 2006.257.19:51:22.47#ibcon#read 4, iclass 40, count 0 2006.257.19:51:22.47#ibcon#about to read 5, iclass 40, count 0 2006.257.19:51:22.47#ibcon#read 5, iclass 40, count 0 2006.257.19:51:22.47#ibcon#about to read 6, iclass 40, count 0 2006.257.19:51:22.47#ibcon#read 6, iclass 40, count 0 2006.257.19:51:22.47#ibcon#end of sib2, iclass 40, count 0 2006.257.19:51:22.47#ibcon#*after write, iclass 40, count 0 2006.257.19:51:22.47#ibcon#*before return 0, iclass 40, count 0 2006.257.19:51:22.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:22.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:22.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:51:22.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:51:22.48$vck44/valo=7,864.99 2006.257.19:51:22.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.19:51:22.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.19:51:22.48#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:22.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:22.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:22.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:22.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:51:22.48#ibcon#first serial, iclass 4, count 0 2006.257.19:51:22.48#ibcon#enter sib2, iclass 4, count 0 2006.257.19:51:22.48#ibcon#flushed, iclass 4, count 0 2006.257.19:51:22.48#ibcon#about to write, iclass 4, count 0 2006.257.19:51:22.48#ibcon#wrote, iclass 4, count 0 2006.257.19:51:22.48#ibcon#about to read 3, iclass 4, count 0 2006.257.19:51:22.49#ibcon#read 3, iclass 4, count 0 2006.257.19:51:22.49#ibcon#about to read 4, iclass 4, count 0 2006.257.19:51:22.49#ibcon#read 4, iclass 4, count 0 2006.257.19:51:22.49#ibcon#about to read 5, iclass 4, count 0 2006.257.19:51:22.49#ibcon#read 5, iclass 4, count 0 2006.257.19:51:22.49#ibcon#about to read 6, iclass 4, count 0 2006.257.19:51:22.49#ibcon#read 6, iclass 4, count 0 2006.257.19:51:22.49#ibcon#end of sib2, iclass 4, count 0 2006.257.19:51:22.49#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:51:22.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:51:22.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.19:51:22.50#ibcon#*before write, iclass 4, count 0 2006.257.19:51:22.50#ibcon#enter sib2, iclass 4, count 0 2006.257.19:51:22.50#ibcon#flushed, iclass 4, count 0 2006.257.19:51:22.50#ibcon#about to write, iclass 4, count 0 2006.257.19:51:22.50#ibcon#wrote, iclass 4, count 0 2006.257.19:51:22.50#ibcon#about to read 3, iclass 4, count 0 2006.257.19:51:22.53#ibcon#read 3, iclass 4, count 0 2006.257.19:51:22.53#ibcon#about to read 4, iclass 4, count 0 2006.257.19:51:22.53#ibcon#read 4, iclass 4, count 0 2006.257.19:51:22.53#ibcon#about to read 5, iclass 4, count 0 2006.257.19:51:22.53#ibcon#read 5, iclass 4, count 0 2006.257.19:51:22.53#ibcon#about to read 6, iclass 4, count 0 2006.257.19:51:22.53#ibcon#read 6, iclass 4, count 0 2006.257.19:51:22.53#ibcon#end of sib2, iclass 4, count 0 2006.257.19:51:22.53#ibcon#*after write, iclass 4, count 0 2006.257.19:51:22.53#ibcon#*before return 0, iclass 4, count 0 2006.257.19:51:22.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:22.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:22.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:51:22.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:51:22.54$vck44/va=7,4 2006.257.19:51:22.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.19:51:22.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.19:51:22.54#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:22.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:22.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:22.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:22.59#ibcon#enter wrdev, iclass 6, count 2 2006.257.19:51:22.59#ibcon#first serial, iclass 6, count 2 2006.257.19:51:22.59#ibcon#enter sib2, iclass 6, count 2 2006.257.19:51:22.59#ibcon#flushed, iclass 6, count 2 2006.257.19:51:22.59#ibcon#about to write, iclass 6, count 2 2006.257.19:51:22.59#ibcon#wrote, iclass 6, count 2 2006.257.19:51:22.59#ibcon#about to read 3, iclass 6, count 2 2006.257.19:51:22.61#ibcon#read 3, iclass 6, count 2 2006.257.19:51:22.61#ibcon#about to read 4, iclass 6, count 2 2006.257.19:51:22.61#ibcon#read 4, iclass 6, count 2 2006.257.19:51:22.61#ibcon#about to read 5, iclass 6, count 2 2006.257.19:51:22.61#ibcon#read 5, iclass 6, count 2 2006.257.19:51:22.61#ibcon#about to read 6, iclass 6, count 2 2006.257.19:51:22.61#ibcon#read 6, iclass 6, count 2 2006.257.19:51:22.61#ibcon#end of sib2, iclass 6, count 2 2006.257.19:51:22.61#ibcon#*mode == 0, iclass 6, count 2 2006.257.19:51:22.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.19:51:22.61#ibcon#[25=AT07-04\r\n] 2006.257.19:51:22.61#ibcon#*before write, iclass 6, count 2 2006.257.19:51:22.62#ibcon#enter sib2, iclass 6, count 2 2006.257.19:51:22.62#ibcon#flushed, iclass 6, count 2 2006.257.19:51:22.62#ibcon#about to write, iclass 6, count 2 2006.257.19:51:22.62#ibcon#wrote, iclass 6, count 2 2006.257.19:51:22.62#ibcon#about to read 3, iclass 6, count 2 2006.257.19:51:22.64#ibcon#read 3, iclass 6, count 2 2006.257.19:51:22.64#ibcon#about to read 4, iclass 6, count 2 2006.257.19:51:22.64#ibcon#read 4, iclass 6, count 2 2006.257.19:51:22.64#ibcon#about to read 5, iclass 6, count 2 2006.257.19:51:22.64#ibcon#read 5, iclass 6, count 2 2006.257.19:51:22.64#ibcon#about to read 6, iclass 6, count 2 2006.257.19:51:22.64#ibcon#read 6, iclass 6, count 2 2006.257.19:51:22.64#ibcon#end of sib2, iclass 6, count 2 2006.257.19:51:22.64#ibcon#*after write, iclass 6, count 2 2006.257.19:51:22.64#ibcon#*before return 0, iclass 6, count 2 2006.257.19:51:22.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:22.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:22.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.19:51:22.65#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:22.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:22.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:22.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:22.76#ibcon#enter wrdev, iclass 6, count 0 2006.257.19:51:22.76#ibcon#first serial, iclass 6, count 0 2006.257.19:51:22.76#ibcon#enter sib2, iclass 6, count 0 2006.257.19:51:22.76#ibcon#flushed, iclass 6, count 0 2006.257.19:51:22.76#ibcon#about to write, iclass 6, count 0 2006.257.19:51:22.76#ibcon#wrote, iclass 6, count 0 2006.257.19:51:22.76#ibcon#about to read 3, iclass 6, count 0 2006.257.19:51:22.78#ibcon#read 3, iclass 6, count 0 2006.257.19:51:22.78#ibcon#about to read 4, iclass 6, count 0 2006.257.19:51:22.78#ibcon#read 4, iclass 6, count 0 2006.257.19:51:22.78#ibcon#about to read 5, iclass 6, count 0 2006.257.19:51:22.78#ibcon#read 5, iclass 6, count 0 2006.257.19:51:22.78#ibcon#about to read 6, iclass 6, count 0 2006.257.19:51:22.78#ibcon#read 6, iclass 6, count 0 2006.257.19:51:22.78#ibcon#end of sib2, iclass 6, count 0 2006.257.19:51:22.78#ibcon#*mode == 0, iclass 6, count 0 2006.257.19:51:22.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.19:51:22.78#ibcon#[25=USB\r\n] 2006.257.19:51:22.78#ibcon#*before write, iclass 6, count 0 2006.257.19:51:22.79#ibcon#enter sib2, iclass 6, count 0 2006.257.19:51:22.79#ibcon#flushed, iclass 6, count 0 2006.257.19:51:22.79#ibcon#about to write, iclass 6, count 0 2006.257.19:51:22.79#ibcon#wrote, iclass 6, count 0 2006.257.19:51:22.79#ibcon#about to read 3, iclass 6, count 0 2006.257.19:51:22.81#ibcon#read 3, iclass 6, count 0 2006.257.19:51:22.81#ibcon#about to read 4, iclass 6, count 0 2006.257.19:51:22.81#ibcon#read 4, iclass 6, count 0 2006.257.19:51:22.81#ibcon#about to read 5, iclass 6, count 0 2006.257.19:51:22.81#ibcon#read 5, iclass 6, count 0 2006.257.19:51:22.81#ibcon#about to read 6, iclass 6, count 0 2006.257.19:51:22.81#ibcon#read 6, iclass 6, count 0 2006.257.19:51:22.81#ibcon#end of sib2, iclass 6, count 0 2006.257.19:51:22.81#ibcon#*after write, iclass 6, count 0 2006.257.19:51:22.81#ibcon#*before return 0, iclass 6, count 0 2006.257.19:51:22.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:22.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:22.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.19:51:22.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.19:51:22.82$vck44/valo=8,884.99 2006.257.19:51:22.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.19:51:22.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.19:51:22.82#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:22.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:22.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:22.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:22.82#ibcon#enter wrdev, iclass 10, count 0 2006.257.19:51:22.82#ibcon#first serial, iclass 10, count 0 2006.257.19:51:22.82#ibcon#enter sib2, iclass 10, count 0 2006.257.19:51:22.82#ibcon#flushed, iclass 10, count 0 2006.257.19:51:22.82#ibcon#about to write, iclass 10, count 0 2006.257.19:51:22.82#ibcon#wrote, iclass 10, count 0 2006.257.19:51:22.82#ibcon#about to read 3, iclass 10, count 0 2006.257.19:51:22.83#ibcon#read 3, iclass 10, count 0 2006.257.19:51:22.83#ibcon#about to read 4, iclass 10, count 0 2006.257.19:51:22.83#ibcon#read 4, iclass 10, count 0 2006.257.19:51:22.83#ibcon#about to read 5, iclass 10, count 0 2006.257.19:51:22.83#ibcon#read 5, iclass 10, count 0 2006.257.19:51:22.83#ibcon#about to read 6, iclass 10, count 0 2006.257.19:51:22.83#ibcon#read 6, iclass 10, count 0 2006.257.19:51:22.83#ibcon#end of sib2, iclass 10, count 0 2006.257.19:51:22.83#ibcon#*mode == 0, iclass 10, count 0 2006.257.19:51:22.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.19:51:22.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.19:51:22.84#ibcon#*before write, iclass 10, count 0 2006.257.19:51:22.84#ibcon#enter sib2, iclass 10, count 0 2006.257.19:51:22.84#ibcon#flushed, iclass 10, count 0 2006.257.19:51:22.84#ibcon#about to write, iclass 10, count 0 2006.257.19:51:22.84#ibcon#wrote, iclass 10, count 0 2006.257.19:51:22.84#ibcon#about to read 3, iclass 10, count 0 2006.257.19:51:22.87#ibcon#read 3, iclass 10, count 0 2006.257.19:51:22.87#ibcon#about to read 4, iclass 10, count 0 2006.257.19:51:22.87#ibcon#read 4, iclass 10, count 0 2006.257.19:51:22.87#ibcon#about to read 5, iclass 10, count 0 2006.257.19:51:22.87#ibcon#read 5, iclass 10, count 0 2006.257.19:51:22.87#ibcon#about to read 6, iclass 10, count 0 2006.257.19:51:22.87#ibcon#read 6, iclass 10, count 0 2006.257.19:51:22.87#ibcon#end of sib2, iclass 10, count 0 2006.257.19:51:22.87#ibcon#*after write, iclass 10, count 0 2006.257.19:51:22.87#ibcon#*before return 0, iclass 10, count 0 2006.257.19:51:22.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:22.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:22.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.19:51:22.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.19:51:22.88$vck44/va=8,4 2006.257.19:51:22.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.19:51:22.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.19:51:22.88#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:22.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:51:22.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:51:22.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:51:22.93#ibcon#enter wrdev, iclass 12, count 2 2006.257.19:51:22.93#ibcon#first serial, iclass 12, count 2 2006.257.19:51:22.93#ibcon#enter sib2, iclass 12, count 2 2006.257.19:51:22.93#ibcon#flushed, iclass 12, count 2 2006.257.19:51:22.93#ibcon#about to write, iclass 12, count 2 2006.257.19:51:22.93#ibcon#wrote, iclass 12, count 2 2006.257.19:51:22.93#ibcon#about to read 3, iclass 12, count 2 2006.257.19:51:22.95#ibcon#read 3, iclass 12, count 2 2006.257.19:51:22.95#ibcon#about to read 4, iclass 12, count 2 2006.257.19:51:22.95#ibcon#read 4, iclass 12, count 2 2006.257.19:51:22.95#ibcon#about to read 5, iclass 12, count 2 2006.257.19:51:22.95#ibcon#read 5, iclass 12, count 2 2006.257.19:51:22.95#ibcon#about to read 6, iclass 12, count 2 2006.257.19:51:22.95#ibcon#read 6, iclass 12, count 2 2006.257.19:51:22.95#ibcon#end of sib2, iclass 12, count 2 2006.257.19:51:22.95#ibcon#*mode == 0, iclass 12, count 2 2006.257.19:51:22.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.19:51:22.95#ibcon#[25=AT08-04\r\n] 2006.257.19:51:22.95#ibcon#*before write, iclass 12, count 2 2006.257.19:51:22.96#ibcon#enter sib2, iclass 12, count 2 2006.257.19:51:22.96#ibcon#flushed, iclass 12, count 2 2006.257.19:51:22.96#ibcon#about to write, iclass 12, count 2 2006.257.19:51:22.96#ibcon#wrote, iclass 12, count 2 2006.257.19:51:22.96#ibcon#about to read 3, iclass 12, count 2 2006.257.19:51:22.98#ibcon#read 3, iclass 12, count 2 2006.257.19:51:22.98#ibcon#about to read 4, iclass 12, count 2 2006.257.19:51:22.98#ibcon#read 4, iclass 12, count 2 2006.257.19:51:22.98#ibcon#about to read 5, iclass 12, count 2 2006.257.19:51:22.98#ibcon#read 5, iclass 12, count 2 2006.257.19:51:22.98#ibcon#about to read 6, iclass 12, count 2 2006.257.19:51:22.98#ibcon#read 6, iclass 12, count 2 2006.257.19:51:22.98#ibcon#end of sib2, iclass 12, count 2 2006.257.19:51:22.98#ibcon#*after write, iclass 12, count 2 2006.257.19:51:22.98#ibcon#*before return 0, iclass 12, count 2 2006.257.19:51:22.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:51:22.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.19:51:22.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.19:51:22.99#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:22.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:51:23.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:51:23.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:51:23.10#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:51:23.10#ibcon#first serial, iclass 12, count 0 2006.257.19:51:23.10#ibcon#enter sib2, iclass 12, count 0 2006.257.19:51:23.10#ibcon#flushed, iclass 12, count 0 2006.257.19:51:23.10#ibcon#about to write, iclass 12, count 0 2006.257.19:51:23.10#ibcon#wrote, iclass 12, count 0 2006.257.19:51:23.10#ibcon#about to read 3, iclass 12, count 0 2006.257.19:51:23.12#ibcon#read 3, iclass 12, count 0 2006.257.19:51:23.12#ibcon#about to read 4, iclass 12, count 0 2006.257.19:51:23.12#ibcon#read 4, iclass 12, count 0 2006.257.19:51:23.12#ibcon#about to read 5, iclass 12, count 0 2006.257.19:51:23.12#ibcon#read 5, iclass 12, count 0 2006.257.19:51:23.12#ibcon#about to read 6, iclass 12, count 0 2006.257.19:51:23.12#ibcon#read 6, iclass 12, count 0 2006.257.19:51:23.12#ibcon#end of sib2, iclass 12, count 0 2006.257.19:51:23.12#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:51:23.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:51:23.12#ibcon#[25=USB\r\n] 2006.257.19:51:23.12#ibcon#*before write, iclass 12, count 0 2006.257.19:51:23.13#ibcon#enter sib2, iclass 12, count 0 2006.257.19:51:23.13#ibcon#flushed, iclass 12, count 0 2006.257.19:51:23.13#ibcon#about to write, iclass 12, count 0 2006.257.19:51:23.13#ibcon#wrote, iclass 12, count 0 2006.257.19:51:23.13#ibcon#about to read 3, iclass 12, count 0 2006.257.19:51:23.15#ibcon#read 3, iclass 12, count 0 2006.257.19:51:23.15#ibcon#about to read 4, iclass 12, count 0 2006.257.19:51:23.15#ibcon#read 4, iclass 12, count 0 2006.257.19:51:23.15#ibcon#about to read 5, iclass 12, count 0 2006.257.19:51:23.15#ibcon#read 5, iclass 12, count 0 2006.257.19:51:23.15#ibcon#about to read 6, iclass 12, count 0 2006.257.19:51:23.15#ibcon#read 6, iclass 12, count 0 2006.257.19:51:23.15#ibcon#end of sib2, iclass 12, count 0 2006.257.19:51:23.15#ibcon#*after write, iclass 12, count 0 2006.257.19:51:23.15#ibcon#*before return 0, iclass 12, count 0 2006.257.19:51:23.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:51:23.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.19:51:23.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:51:23.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:51:23.16$vck44/vblo=1,629.99 2006.257.19:51:23.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.19:51:23.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.19:51:23.16#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:23.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:51:23.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:51:23.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:51:23.16#ibcon#enter wrdev, iclass 14, count 0 2006.257.19:51:23.16#ibcon#first serial, iclass 14, count 0 2006.257.19:51:23.16#ibcon#enter sib2, iclass 14, count 0 2006.257.19:51:23.16#ibcon#flushed, iclass 14, count 0 2006.257.19:51:23.16#ibcon#about to write, iclass 14, count 0 2006.257.19:51:23.16#ibcon#wrote, iclass 14, count 0 2006.257.19:51:23.16#ibcon#about to read 3, iclass 14, count 0 2006.257.19:51:23.17#ibcon#read 3, iclass 14, count 0 2006.257.19:51:23.17#ibcon#about to read 4, iclass 14, count 0 2006.257.19:51:23.17#ibcon#read 4, iclass 14, count 0 2006.257.19:51:23.17#ibcon#about to read 5, iclass 14, count 0 2006.257.19:51:23.17#ibcon#read 5, iclass 14, count 0 2006.257.19:51:23.17#ibcon#about to read 6, iclass 14, count 0 2006.257.19:51:23.17#ibcon#read 6, iclass 14, count 0 2006.257.19:51:23.17#ibcon#end of sib2, iclass 14, count 0 2006.257.19:51:23.17#ibcon#*mode == 0, iclass 14, count 0 2006.257.19:51:23.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.19:51:23.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.19:51:23.18#ibcon#*before write, iclass 14, count 0 2006.257.19:51:23.18#ibcon#enter sib2, iclass 14, count 0 2006.257.19:51:23.18#ibcon#flushed, iclass 14, count 0 2006.257.19:51:23.18#ibcon#about to write, iclass 14, count 0 2006.257.19:51:23.18#ibcon#wrote, iclass 14, count 0 2006.257.19:51:23.18#ibcon#about to read 3, iclass 14, count 0 2006.257.19:51:23.21#ibcon#read 3, iclass 14, count 0 2006.257.19:51:23.21#ibcon#about to read 4, iclass 14, count 0 2006.257.19:51:23.21#ibcon#read 4, iclass 14, count 0 2006.257.19:51:23.21#ibcon#about to read 5, iclass 14, count 0 2006.257.19:51:23.21#ibcon#read 5, iclass 14, count 0 2006.257.19:51:23.21#ibcon#about to read 6, iclass 14, count 0 2006.257.19:51:23.21#ibcon#read 6, iclass 14, count 0 2006.257.19:51:23.21#ibcon#end of sib2, iclass 14, count 0 2006.257.19:51:23.21#ibcon#*after write, iclass 14, count 0 2006.257.19:51:23.21#ibcon#*before return 0, iclass 14, count 0 2006.257.19:51:23.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:51:23.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:51:23.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.19:51:23.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.19:51:23.22$vck44/vb=1,4 2006.257.19:51:23.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.19:51:23.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.19:51:23.22#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:23.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:51:23.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:51:23.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:51:23.22#ibcon#enter wrdev, iclass 16, count 2 2006.257.19:51:23.22#ibcon#first serial, iclass 16, count 2 2006.257.19:51:23.22#ibcon#enter sib2, iclass 16, count 2 2006.257.19:51:23.22#ibcon#flushed, iclass 16, count 2 2006.257.19:51:23.22#ibcon#about to write, iclass 16, count 2 2006.257.19:51:23.22#ibcon#wrote, iclass 16, count 2 2006.257.19:51:23.22#ibcon#about to read 3, iclass 16, count 2 2006.257.19:51:23.23#ibcon#read 3, iclass 16, count 2 2006.257.19:51:23.23#ibcon#about to read 4, iclass 16, count 2 2006.257.19:51:23.23#ibcon#read 4, iclass 16, count 2 2006.257.19:51:23.23#ibcon#about to read 5, iclass 16, count 2 2006.257.19:51:23.23#ibcon#read 5, iclass 16, count 2 2006.257.19:51:23.23#ibcon#about to read 6, iclass 16, count 2 2006.257.19:51:23.23#ibcon#read 6, iclass 16, count 2 2006.257.19:51:23.23#ibcon#end of sib2, iclass 16, count 2 2006.257.19:51:23.23#ibcon#*mode == 0, iclass 16, count 2 2006.257.19:51:23.23#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.19:51:23.23#ibcon#[27=AT01-04\r\n] 2006.257.19:51:23.24#ibcon#*before write, iclass 16, count 2 2006.257.19:51:23.24#ibcon#enter sib2, iclass 16, count 2 2006.257.19:51:23.24#ibcon#flushed, iclass 16, count 2 2006.257.19:51:23.24#ibcon#about to write, iclass 16, count 2 2006.257.19:51:23.24#ibcon#wrote, iclass 16, count 2 2006.257.19:51:23.24#ibcon#about to read 3, iclass 16, count 2 2006.257.19:51:23.26#ibcon#read 3, iclass 16, count 2 2006.257.19:51:23.26#ibcon#about to read 4, iclass 16, count 2 2006.257.19:51:23.26#ibcon#read 4, iclass 16, count 2 2006.257.19:51:23.26#ibcon#about to read 5, iclass 16, count 2 2006.257.19:51:23.26#ibcon#read 5, iclass 16, count 2 2006.257.19:51:23.26#ibcon#about to read 6, iclass 16, count 2 2006.257.19:51:23.26#ibcon#read 6, iclass 16, count 2 2006.257.19:51:23.26#ibcon#end of sib2, iclass 16, count 2 2006.257.19:51:23.26#ibcon#*after write, iclass 16, count 2 2006.257.19:51:23.26#ibcon#*before return 0, iclass 16, count 2 2006.257.19:51:23.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:51:23.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.19:51:23.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.19:51:23.27#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:23.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:51:23.38#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:51:23.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:51:23.39#ibcon#enter wrdev, iclass 16, count 0 2006.257.19:51:23.39#ibcon#first serial, iclass 16, count 0 2006.257.19:51:23.39#ibcon#enter sib2, iclass 16, count 0 2006.257.19:51:23.39#ibcon#flushed, iclass 16, count 0 2006.257.19:51:23.39#ibcon#about to write, iclass 16, count 0 2006.257.19:51:23.39#ibcon#wrote, iclass 16, count 0 2006.257.19:51:23.39#ibcon#about to read 3, iclass 16, count 0 2006.257.19:51:23.40#ibcon#read 3, iclass 16, count 0 2006.257.19:51:23.40#ibcon#about to read 4, iclass 16, count 0 2006.257.19:51:23.40#ibcon#read 4, iclass 16, count 0 2006.257.19:51:23.40#ibcon#about to read 5, iclass 16, count 0 2006.257.19:51:23.40#ibcon#read 5, iclass 16, count 0 2006.257.19:51:23.40#ibcon#about to read 6, iclass 16, count 0 2006.257.19:51:23.40#ibcon#read 6, iclass 16, count 0 2006.257.19:51:23.40#ibcon#end of sib2, iclass 16, count 0 2006.257.19:51:23.40#ibcon#*mode == 0, iclass 16, count 0 2006.257.19:51:23.40#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.19:51:23.40#ibcon#[27=USB\r\n] 2006.257.19:51:23.40#ibcon#*before write, iclass 16, count 0 2006.257.19:51:23.41#ibcon#enter sib2, iclass 16, count 0 2006.257.19:51:23.41#ibcon#flushed, iclass 16, count 0 2006.257.19:51:23.41#ibcon#about to write, iclass 16, count 0 2006.257.19:51:23.41#ibcon#wrote, iclass 16, count 0 2006.257.19:51:23.41#ibcon#about to read 3, iclass 16, count 0 2006.257.19:51:23.43#ibcon#read 3, iclass 16, count 0 2006.257.19:51:23.43#ibcon#about to read 4, iclass 16, count 0 2006.257.19:51:23.43#ibcon#read 4, iclass 16, count 0 2006.257.19:51:23.43#ibcon#about to read 5, iclass 16, count 0 2006.257.19:51:23.43#ibcon#read 5, iclass 16, count 0 2006.257.19:51:23.43#ibcon#about to read 6, iclass 16, count 0 2006.257.19:51:23.43#ibcon#read 6, iclass 16, count 0 2006.257.19:51:23.43#ibcon#end of sib2, iclass 16, count 0 2006.257.19:51:23.43#ibcon#*after write, iclass 16, count 0 2006.257.19:51:23.43#ibcon#*before return 0, iclass 16, count 0 2006.257.19:51:23.43#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:51:23.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.19:51:23.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.19:51:23.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.19:51:23.44$vck44/vblo=2,634.99 2006.257.19:51:23.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.19:51:23.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.19:51:23.44#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:23.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:23.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:23.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:23.44#ibcon#enter wrdev, iclass 18, count 0 2006.257.19:51:23.44#ibcon#first serial, iclass 18, count 0 2006.257.19:51:23.44#ibcon#enter sib2, iclass 18, count 0 2006.257.19:51:23.44#ibcon#flushed, iclass 18, count 0 2006.257.19:51:23.44#ibcon#about to write, iclass 18, count 0 2006.257.19:51:23.44#ibcon#wrote, iclass 18, count 0 2006.257.19:51:23.44#ibcon#about to read 3, iclass 18, count 0 2006.257.19:51:23.45#ibcon#read 3, iclass 18, count 0 2006.257.19:51:23.45#ibcon#about to read 4, iclass 18, count 0 2006.257.19:51:23.45#ibcon#read 4, iclass 18, count 0 2006.257.19:51:23.45#ibcon#about to read 5, iclass 18, count 0 2006.257.19:51:23.45#ibcon#read 5, iclass 18, count 0 2006.257.19:51:23.45#ibcon#about to read 6, iclass 18, count 0 2006.257.19:51:23.45#ibcon#read 6, iclass 18, count 0 2006.257.19:51:23.45#ibcon#end of sib2, iclass 18, count 0 2006.257.19:51:23.45#ibcon#*mode == 0, iclass 18, count 0 2006.257.19:51:23.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.19:51:23.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.19:51:23.46#ibcon#*before write, iclass 18, count 0 2006.257.19:51:23.46#ibcon#enter sib2, iclass 18, count 0 2006.257.19:51:23.46#ibcon#flushed, iclass 18, count 0 2006.257.19:51:23.46#ibcon#about to write, iclass 18, count 0 2006.257.19:51:23.46#ibcon#wrote, iclass 18, count 0 2006.257.19:51:23.46#ibcon#about to read 3, iclass 18, count 0 2006.257.19:51:23.49#ibcon#read 3, iclass 18, count 0 2006.257.19:51:23.49#ibcon#about to read 4, iclass 18, count 0 2006.257.19:51:23.49#ibcon#read 4, iclass 18, count 0 2006.257.19:51:23.49#ibcon#about to read 5, iclass 18, count 0 2006.257.19:51:23.49#ibcon#read 5, iclass 18, count 0 2006.257.19:51:23.49#ibcon#about to read 6, iclass 18, count 0 2006.257.19:51:23.49#ibcon#read 6, iclass 18, count 0 2006.257.19:51:23.49#ibcon#end of sib2, iclass 18, count 0 2006.257.19:51:23.49#ibcon#*after write, iclass 18, count 0 2006.257.19:51:23.49#ibcon#*before return 0, iclass 18, count 0 2006.257.19:51:23.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:23.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.19:51:23.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.19:51:23.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.19:51:23.50$vck44/vb=2,5 2006.257.19:51:23.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.19:51:23.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.19:51:23.50#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:23.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:23.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:23.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:23.55#ibcon#enter wrdev, iclass 20, count 2 2006.257.19:51:23.55#ibcon#first serial, iclass 20, count 2 2006.257.19:51:23.55#ibcon#enter sib2, iclass 20, count 2 2006.257.19:51:23.55#ibcon#flushed, iclass 20, count 2 2006.257.19:51:23.55#ibcon#about to write, iclass 20, count 2 2006.257.19:51:23.55#ibcon#wrote, iclass 20, count 2 2006.257.19:51:23.55#ibcon#about to read 3, iclass 20, count 2 2006.257.19:51:23.57#ibcon#read 3, iclass 20, count 2 2006.257.19:51:23.57#ibcon#about to read 4, iclass 20, count 2 2006.257.19:51:23.57#ibcon#read 4, iclass 20, count 2 2006.257.19:51:23.57#ibcon#about to read 5, iclass 20, count 2 2006.257.19:51:23.57#ibcon#read 5, iclass 20, count 2 2006.257.19:51:23.57#ibcon#about to read 6, iclass 20, count 2 2006.257.19:51:23.57#ibcon#read 6, iclass 20, count 2 2006.257.19:51:23.57#ibcon#end of sib2, iclass 20, count 2 2006.257.19:51:23.57#ibcon#*mode == 0, iclass 20, count 2 2006.257.19:51:23.57#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.19:51:23.57#ibcon#[27=AT02-05\r\n] 2006.257.19:51:23.57#ibcon#*before write, iclass 20, count 2 2006.257.19:51:23.58#ibcon#enter sib2, iclass 20, count 2 2006.257.19:51:23.58#ibcon#flushed, iclass 20, count 2 2006.257.19:51:23.58#ibcon#about to write, iclass 20, count 2 2006.257.19:51:23.58#ibcon#wrote, iclass 20, count 2 2006.257.19:51:23.58#ibcon#about to read 3, iclass 20, count 2 2006.257.19:51:23.60#ibcon#read 3, iclass 20, count 2 2006.257.19:51:23.60#ibcon#about to read 4, iclass 20, count 2 2006.257.19:51:23.60#ibcon#read 4, iclass 20, count 2 2006.257.19:51:23.60#ibcon#about to read 5, iclass 20, count 2 2006.257.19:51:23.60#ibcon#read 5, iclass 20, count 2 2006.257.19:51:23.60#ibcon#about to read 6, iclass 20, count 2 2006.257.19:51:23.60#ibcon#read 6, iclass 20, count 2 2006.257.19:51:23.60#ibcon#end of sib2, iclass 20, count 2 2006.257.19:51:23.60#ibcon#*after write, iclass 20, count 2 2006.257.19:51:23.60#ibcon#*before return 0, iclass 20, count 2 2006.257.19:51:23.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:23.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.19:51:23.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.19:51:23.61#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:23.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:23.72#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:23.72#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:23.72#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:51:23.72#ibcon#first serial, iclass 20, count 0 2006.257.19:51:23.72#ibcon#enter sib2, iclass 20, count 0 2006.257.19:51:23.72#ibcon#flushed, iclass 20, count 0 2006.257.19:51:23.72#ibcon#about to write, iclass 20, count 0 2006.257.19:51:23.72#ibcon#wrote, iclass 20, count 0 2006.257.19:51:23.72#ibcon#about to read 3, iclass 20, count 0 2006.257.19:51:23.74#ibcon#read 3, iclass 20, count 0 2006.257.19:51:23.74#ibcon#about to read 4, iclass 20, count 0 2006.257.19:51:23.74#ibcon#read 4, iclass 20, count 0 2006.257.19:51:23.74#ibcon#about to read 5, iclass 20, count 0 2006.257.19:51:23.74#ibcon#read 5, iclass 20, count 0 2006.257.19:51:23.74#ibcon#about to read 6, iclass 20, count 0 2006.257.19:51:23.74#ibcon#read 6, iclass 20, count 0 2006.257.19:51:23.74#ibcon#end of sib2, iclass 20, count 0 2006.257.19:51:23.74#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:51:23.74#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:51:23.74#ibcon#[27=USB\r\n] 2006.257.19:51:23.74#ibcon#*before write, iclass 20, count 0 2006.257.19:51:23.75#ibcon#enter sib2, iclass 20, count 0 2006.257.19:51:23.75#ibcon#flushed, iclass 20, count 0 2006.257.19:51:23.75#ibcon#about to write, iclass 20, count 0 2006.257.19:51:23.75#ibcon#wrote, iclass 20, count 0 2006.257.19:51:23.75#ibcon#about to read 3, iclass 20, count 0 2006.257.19:51:23.77#ibcon#read 3, iclass 20, count 0 2006.257.19:51:23.77#ibcon#about to read 4, iclass 20, count 0 2006.257.19:51:23.77#ibcon#read 4, iclass 20, count 0 2006.257.19:51:23.77#ibcon#about to read 5, iclass 20, count 0 2006.257.19:51:23.77#ibcon#read 5, iclass 20, count 0 2006.257.19:51:23.77#ibcon#about to read 6, iclass 20, count 0 2006.257.19:51:23.77#ibcon#read 6, iclass 20, count 0 2006.257.19:51:23.77#ibcon#end of sib2, iclass 20, count 0 2006.257.19:51:23.77#ibcon#*after write, iclass 20, count 0 2006.257.19:51:23.77#ibcon#*before return 0, iclass 20, count 0 2006.257.19:51:23.77#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:23.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.19:51:23.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:51:23.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:51:23.78$vck44/vblo=3,649.99 2006.257.19:51:23.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.19:51:23.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.19:51:23.78#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:23.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:23.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:23.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:23.78#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:51:23.78#ibcon#first serial, iclass 22, count 0 2006.257.19:51:23.78#ibcon#enter sib2, iclass 22, count 0 2006.257.19:51:23.78#ibcon#flushed, iclass 22, count 0 2006.257.19:51:23.78#ibcon#about to write, iclass 22, count 0 2006.257.19:51:23.78#ibcon#wrote, iclass 22, count 0 2006.257.19:51:23.78#ibcon#about to read 3, iclass 22, count 0 2006.257.19:51:23.79#ibcon#read 3, iclass 22, count 0 2006.257.19:51:23.79#ibcon#about to read 4, iclass 22, count 0 2006.257.19:51:23.79#ibcon#read 4, iclass 22, count 0 2006.257.19:51:23.79#ibcon#about to read 5, iclass 22, count 0 2006.257.19:51:23.79#ibcon#read 5, iclass 22, count 0 2006.257.19:51:23.79#ibcon#about to read 6, iclass 22, count 0 2006.257.19:51:23.79#ibcon#read 6, iclass 22, count 0 2006.257.19:51:23.79#ibcon#end of sib2, iclass 22, count 0 2006.257.19:51:23.79#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:51:23.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:51:23.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.19:51:23.80#ibcon#*before write, iclass 22, count 0 2006.257.19:51:23.80#ibcon#enter sib2, iclass 22, count 0 2006.257.19:51:23.80#ibcon#flushed, iclass 22, count 0 2006.257.19:51:23.80#ibcon#about to write, iclass 22, count 0 2006.257.19:51:23.80#ibcon#wrote, iclass 22, count 0 2006.257.19:51:23.80#ibcon#about to read 3, iclass 22, count 0 2006.257.19:51:23.83#ibcon#read 3, iclass 22, count 0 2006.257.19:51:23.83#ibcon#about to read 4, iclass 22, count 0 2006.257.19:51:23.83#ibcon#read 4, iclass 22, count 0 2006.257.19:51:23.83#ibcon#about to read 5, iclass 22, count 0 2006.257.19:51:23.83#ibcon#read 5, iclass 22, count 0 2006.257.19:51:23.83#ibcon#about to read 6, iclass 22, count 0 2006.257.19:51:23.83#ibcon#read 6, iclass 22, count 0 2006.257.19:51:23.83#ibcon#end of sib2, iclass 22, count 0 2006.257.19:51:23.83#ibcon#*after write, iclass 22, count 0 2006.257.19:51:23.83#ibcon#*before return 0, iclass 22, count 0 2006.257.19:51:23.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:23.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.19:51:23.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:51:23.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:51:23.84$vck44/vb=3,4 2006.257.19:51:23.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.19:51:23.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.19:51:23.84#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:23.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:23.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:23.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:23.89#ibcon#enter wrdev, iclass 24, count 2 2006.257.19:51:23.89#ibcon#first serial, iclass 24, count 2 2006.257.19:51:23.89#ibcon#enter sib2, iclass 24, count 2 2006.257.19:51:23.89#ibcon#flushed, iclass 24, count 2 2006.257.19:51:23.89#ibcon#about to write, iclass 24, count 2 2006.257.19:51:23.89#ibcon#wrote, iclass 24, count 2 2006.257.19:51:23.89#ibcon#about to read 3, iclass 24, count 2 2006.257.19:51:23.91#ibcon#read 3, iclass 24, count 2 2006.257.19:51:23.91#ibcon#about to read 4, iclass 24, count 2 2006.257.19:51:23.91#ibcon#read 4, iclass 24, count 2 2006.257.19:51:23.91#ibcon#about to read 5, iclass 24, count 2 2006.257.19:51:23.91#ibcon#read 5, iclass 24, count 2 2006.257.19:51:23.91#ibcon#about to read 6, iclass 24, count 2 2006.257.19:51:23.91#ibcon#read 6, iclass 24, count 2 2006.257.19:51:23.91#ibcon#end of sib2, iclass 24, count 2 2006.257.19:51:23.91#ibcon#*mode == 0, iclass 24, count 2 2006.257.19:51:23.91#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.19:51:23.91#ibcon#[27=AT03-04\r\n] 2006.257.19:51:23.91#ibcon#*before write, iclass 24, count 2 2006.257.19:51:23.92#ibcon#enter sib2, iclass 24, count 2 2006.257.19:51:23.92#ibcon#flushed, iclass 24, count 2 2006.257.19:51:23.92#ibcon#about to write, iclass 24, count 2 2006.257.19:51:23.92#ibcon#wrote, iclass 24, count 2 2006.257.19:51:23.92#ibcon#about to read 3, iclass 24, count 2 2006.257.19:51:23.94#ibcon#read 3, iclass 24, count 2 2006.257.19:51:23.94#ibcon#about to read 4, iclass 24, count 2 2006.257.19:51:23.94#ibcon#read 4, iclass 24, count 2 2006.257.19:51:23.94#ibcon#about to read 5, iclass 24, count 2 2006.257.19:51:23.94#ibcon#read 5, iclass 24, count 2 2006.257.19:51:23.94#ibcon#about to read 6, iclass 24, count 2 2006.257.19:51:23.94#ibcon#read 6, iclass 24, count 2 2006.257.19:51:23.94#ibcon#end of sib2, iclass 24, count 2 2006.257.19:51:23.94#ibcon#*after write, iclass 24, count 2 2006.257.19:51:23.94#ibcon#*before return 0, iclass 24, count 2 2006.257.19:51:23.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:23.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.19:51:23.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.19:51:23.95#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:23.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:24.06#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:24.06#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:24.06#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:51:24.06#ibcon#first serial, iclass 24, count 0 2006.257.19:51:24.06#ibcon#enter sib2, iclass 24, count 0 2006.257.19:51:24.06#ibcon#flushed, iclass 24, count 0 2006.257.19:51:24.06#ibcon#about to write, iclass 24, count 0 2006.257.19:51:24.06#ibcon#wrote, iclass 24, count 0 2006.257.19:51:24.06#ibcon#about to read 3, iclass 24, count 0 2006.257.19:51:24.08#ibcon#read 3, iclass 24, count 0 2006.257.19:51:24.08#ibcon#about to read 4, iclass 24, count 0 2006.257.19:51:24.08#ibcon#read 4, iclass 24, count 0 2006.257.19:51:24.08#ibcon#about to read 5, iclass 24, count 0 2006.257.19:51:24.08#ibcon#read 5, iclass 24, count 0 2006.257.19:51:24.08#ibcon#about to read 6, iclass 24, count 0 2006.257.19:51:24.08#ibcon#read 6, iclass 24, count 0 2006.257.19:51:24.08#ibcon#end of sib2, iclass 24, count 0 2006.257.19:51:24.08#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:51:24.08#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:51:24.08#ibcon#[27=USB\r\n] 2006.257.19:51:24.08#ibcon#*before write, iclass 24, count 0 2006.257.19:51:24.09#ibcon#enter sib2, iclass 24, count 0 2006.257.19:51:24.09#ibcon#flushed, iclass 24, count 0 2006.257.19:51:24.09#ibcon#about to write, iclass 24, count 0 2006.257.19:51:24.09#ibcon#wrote, iclass 24, count 0 2006.257.19:51:24.09#ibcon#about to read 3, iclass 24, count 0 2006.257.19:51:24.11#ibcon#read 3, iclass 24, count 0 2006.257.19:51:24.11#ibcon#about to read 4, iclass 24, count 0 2006.257.19:51:24.11#ibcon#read 4, iclass 24, count 0 2006.257.19:51:24.11#ibcon#about to read 5, iclass 24, count 0 2006.257.19:51:24.11#ibcon#read 5, iclass 24, count 0 2006.257.19:51:24.11#ibcon#about to read 6, iclass 24, count 0 2006.257.19:51:24.11#ibcon#read 6, iclass 24, count 0 2006.257.19:51:24.11#ibcon#end of sib2, iclass 24, count 0 2006.257.19:51:24.11#ibcon#*after write, iclass 24, count 0 2006.257.19:51:24.11#ibcon#*before return 0, iclass 24, count 0 2006.257.19:51:24.11#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:24.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.19:51:24.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:51:24.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:51:24.12$vck44/vblo=4,679.99 2006.257.19:51:24.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.19:51:24.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.19:51:24.12#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:24.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:24.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:24.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:24.12#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:51:24.12#ibcon#first serial, iclass 26, count 0 2006.257.19:51:24.12#ibcon#enter sib2, iclass 26, count 0 2006.257.19:51:24.12#ibcon#flushed, iclass 26, count 0 2006.257.19:51:24.12#ibcon#about to write, iclass 26, count 0 2006.257.19:51:24.12#ibcon#wrote, iclass 26, count 0 2006.257.19:51:24.12#ibcon#about to read 3, iclass 26, count 0 2006.257.19:51:24.13#ibcon#read 3, iclass 26, count 0 2006.257.19:51:24.13#ibcon#about to read 4, iclass 26, count 0 2006.257.19:51:24.13#ibcon#read 4, iclass 26, count 0 2006.257.19:51:24.13#ibcon#about to read 5, iclass 26, count 0 2006.257.19:51:24.13#ibcon#read 5, iclass 26, count 0 2006.257.19:51:24.13#ibcon#about to read 6, iclass 26, count 0 2006.257.19:51:24.13#ibcon#read 6, iclass 26, count 0 2006.257.19:51:24.13#ibcon#end of sib2, iclass 26, count 0 2006.257.19:51:24.13#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:51:24.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:51:24.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.19:51:24.14#ibcon#*before write, iclass 26, count 0 2006.257.19:51:24.14#ibcon#enter sib2, iclass 26, count 0 2006.257.19:51:24.14#ibcon#flushed, iclass 26, count 0 2006.257.19:51:24.14#ibcon#about to write, iclass 26, count 0 2006.257.19:51:24.14#ibcon#wrote, iclass 26, count 0 2006.257.19:51:24.14#ibcon#about to read 3, iclass 26, count 0 2006.257.19:51:24.17#ibcon#read 3, iclass 26, count 0 2006.257.19:51:24.17#ibcon#about to read 4, iclass 26, count 0 2006.257.19:51:24.17#ibcon#read 4, iclass 26, count 0 2006.257.19:51:24.17#ibcon#about to read 5, iclass 26, count 0 2006.257.19:51:24.17#ibcon#read 5, iclass 26, count 0 2006.257.19:51:24.17#ibcon#about to read 6, iclass 26, count 0 2006.257.19:51:24.17#ibcon#read 6, iclass 26, count 0 2006.257.19:51:24.17#ibcon#end of sib2, iclass 26, count 0 2006.257.19:51:24.17#ibcon#*after write, iclass 26, count 0 2006.257.19:51:24.17#ibcon#*before return 0, iclass 26, count 0 2006.257.19:51:24.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:24.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.19:51:24.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:51:24.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:51:24.18$vck44/vb=4,5 2006.257.19:51:24.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.19:51:24.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.19:51:24.18#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:24.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:24.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:24.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:24.23#ibcon#enter wrdev, iclass 28, count 2 2006.257.19:51:24.23#ibcon#first serial, iclass 28, count 2 2006.257.19:51:24.23#ibcon#enter sib2, iclass 28, count 2 2006.257.19:51:24.23#ibcon#flushed, iclass 28, count 2 2006.257.19:51:24.23#ibcon#about to write, iclass 28, count 2 2006.257.19:51:24.23#ibcon#wrote, iclass 28, count 2 2006.257.19:51:24.23#ibcon#about to read 3, iclass 28, count 2 2006.257.19:51:24.25#ibcon#read 3, iclass 28, count 2 2006.257.19:51:24.25#ibcon#about to read 4, iclass 28, count 2 2006.257.19:51:24.25#ibcon#read 4, iclass 28, count 2 2006.257.19:51:24.25#ibcon#about to read 5, iclass 28, count 2 2006.257.19:51:24.25#ibcon#read 5, iclass 28, count 2 2006.257.19:51:24.25#ibcon#about to read 6, iclass 28, count 2 2006.257.19:51:24.25#ibcon#read 6, iclass 28, count 2 2006.257.19:51:24.25#ibcon#end of sib2, iclass 28, count 2 2006.257.19:51:24.25#ibcon#*mode == 0, iclass 28, count 2 2006.257.19:51:24.25#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.19:51:24.25#ibcon#[27=AT04-05\r\n] 2006.257.19:51:24.25#ibcon#*before write, iclass 28, count 2 2006.257.19:51:24.26#ibcon#enter sib2, iclass 28, count 2 2006.257.19:51:24.26#ibcon#flushed, iclass 28, count 2 2006.257.19:51:24.26#ibcon#about to write, iclass 28, count 2 2006.257.19:51:24.26#ibcon#wrote, iclass 28, count 2 2006.257.19:51:24.26#ibcon#about to read 3, iclass 28, count 2 2006.257.19:51:24.28#ibcon#read 3, iclass 28, count 2 2006.257.19:51:24.28#ibcon#about to read 4, iclass 28, count 2 2006.257.19:51:24.28#ibcon#read 4, iclass 28, count 2 2006.257.19:51:24.28#ibcon#about to read 5, iclass 28, count 2 2006.257.19:51:24.28#ibcon#read 5, iclass 28, count 2 2006.257.19:51:24.28#ibcon#about to read 6, iclass 28, count 2 2006.257.19:51:24.28#ibcon#read 6, iclass 28, count 2 2006.257.19:51:24.28#ibcon#end of sib2, iclass 28, count 2 2006.257.19:51:24.28#ibcon#*after write, iclass 28, count 2 2006.257.19:51:24.28#ibcon#*before return 0, iclass 28, count 2 2006.257.19:51:24.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:24.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.19:51:24.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.19:51:24.29#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:24.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:24.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:24.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:24.40#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:51:24.40#ibcon#first serial, iclass 28, count 0 2006.257.19:51:24.40#ibcon#enter sib2, iclass 28, count 0 2006.257.19:51:24.40#ibcon#flushed, iclass 28, count 0 2006.257.19:51:24.40#ibcon#about to write, iclass 28, count 0 2006.257.19:51:24.40#ibcon#wrote, iclass 28, count 0 2006.257.19:51:24.40#ibcon#about to read 3, iclass 28, count 0 2006.257.19:51:24.42#ibcon#read 3, iclass 28, count 0 2006.257.19:51:24.42#ibcon#about to read 4, iclass 28, count 0 2006.257.19:51:24.42#ibcon#read 4, iclass 28, count 0 2006.257.19:51:24.42#ibcon#about to read 5, iclass 28, count 0 2006.257.19:51:24.42#ibcon#read 5, iclass 28, count 0 2006.257.19:51:24.42#ibcon#about to read 6, iclass 28, count 0 2006.257.19:51:24.42#ibcon#read 6, iclass 28, count 0 2006.257.19:51:24.42#ibcon#end of sib2, iclass 28, count 0 2006.257.19:51:24.42#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:51:24.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:51:24.42#ibcon#[27=USB\r\n] 2006.257.19:51:24.42#ibcon#*before write, iclass 28, count 0 2006.257.19:51:24.43#ibcon#enter sib2, iclass 28, count 0 2006.257.19:51:24.43#ibcon#flushed, iclass 28, count 0 2006.257.19:51:24.43#ibcon#about to write, iclass 28, count 0 2006.257.19:51:24.43#ibcon#wrote, iclass 28, count 0 2006.257.19:51:24.43#ibcon#about to read 3, iclass 28, count 0 2006.257.19:51:24.45#ibcon#read 3, iclass 28, count 0 2006.257.19:51:24.45#ibcon#about to read 4, iclass 28, count 0 2006.257.19:51:24.45#ibcon#read 4, iclass 28, count 0 2006.257.19:51:24.45#ibcon#about to read 5, iclass 28, count 0 2006.257.19:51:24.45#ibcon#read 5, iclass 28, count 0 2006.257.19:51:24.45#ibcon#about to read 6, iclass 28, count 0 2006.257.19:51:24.45#ibcon#read 6, iclass 28, count 0 2006.257.19:51:24.45#ibcon#end of sib2, iclass 28, count 0 2006.257.19:51:24.45#ibcon#*after write, iclass 28, count 0 2006.257.19:51:24.45#ibcon#*before return 0, iclass 28, count 0 2006.257.19:51:24.45#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:24.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.19:51:24.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:51:24.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:51:24.46$vck44/vblo=5,709.99 2006.257.19:51:24.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.19:51:24.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.19:51:24.46#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:24.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:24.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:24.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:24.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.19:51:24.46#ibcon#first serial, iclass 30, count 0 2006.257.19:51:24.46#ibcon#enter sib2, iclass 30, count 0 2006.257.19:51:24.46#ibcon#flushed, iclass 30, count 0 2006.257.19:51:24.46#ibcon#about to write, iclass 30, count 0 2006.257.19:51:24.46#ibcon#wrote, iclass 30, count 0 2006.257.19:51:24.46#ibcon#about to read 3, iclass 30, count 0 2006.257.19:51:24.47#ibcon#read 3, iclass 30, count 0 2006.257.19:51:24.47#ibcon#about to read 4, iclass 30, count 0 2006.257.19:51:24.47#ibcon#read 4, iclass 30, count 0 2006.257.19:51:24.47#ibcon#about to read 5, iclass 30, count 0 2006.257.19:51:24.47#ibcon#read 5, iclass 30, count 0 2006.257.19:51:24.47#ibcon#about to read 6, iclass 30, count 0 2006.257.19:51:24.47#ibcon#read 6, iclass 30, count 0 2006.257.19:51:24.47#ibcon#end of sib2, iclass 30, count 0 2006.257.19:51:24.47#ibcon#*mode == 0, iclass 30, count 0 2006.257.19:51:24.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.19:51:24.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.19:51:24.48#ibcon#*before write, iclass 30, count 0 2006.257.19:51:24.48#ibcon#enter sib2, iclass 30, count 0 2006.257.19:51:24.48#ibcon#flushed, iclass 30, count 0 2006.257.19:51:24.48#ibcon#about to write, iclass 30, count 0 2006.257.19:51:24.48#ibcon#wrote, iclass 30, count 0 2006.257.19:51:24.48#ibcon#about to read 3, iclass 30, count 0 2006.257.19:51:24.51#ibcon#read 3, iclass 30, count 0 2006.257.19:51:24.51#ibcon#about to read 4, iclass 30, count 0 2006.257.19:51:24.51#ibcon#read 4, iclass 30, count 0 2006.257.19:51:24.51#ibcon#about to read 5, iclass 30, count 0 2006.257.19:51:24.51#ibcon#read 5, iclass 30, count 0 2006.257.19:51:24.51#ibcon#about to read 6, iclass 30, count 0 2006.257.19:51:24.51#ibcon#read 6, iclass 30, count 0 2006.257.19:51:24.51#ibcon#end of sib2, iclass 30, count 0 2006.257.19:51:24.51#ibcon#*after write, iclass 30, count 0 2006.257.19:51:24.51#ibcon#*before return 0, iclass 30, count 0 2006.257.19:51:24.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:24.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.19:51:24.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.19:51:24.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.19:51:24.52$vck44/vb=5,4 2006.257.19:51:24.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.19:51:24.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.19:51:24.52#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:24.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:24.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:24.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:24.57#ibcon#enter wrdev, iclass 32, count 2 2006.257.19:51:24.57#ibcon#first serial, iclass 32, count 2 2006.257.19:51:24.58#ibcon#enter sib2, iclass 32, count 2 2006.257.19:51:24.58#ibcon#flushed, iclass 32, count 2 2006.257.19:51:24.58#ibcon#about to write, iclass 32, count 2 2006.257.19:51:24.58#ibcon#wrote, iclass 32, count 2 2006.257.19:51:24.58#ibcon#about to read 3, iclass 32, count 2 2006.257.19:51:24.59#ibcon#read 3, iclass 32, count 2 2006.257.19:51:24.59#ibcon#about to read 4, iclass 32, count 2 2006.257.19:51:24.59#ibcon#read 4, iclass 32, count 2 2006.257.19:51:24.59#ibcon#about to read 5, iclass 32, count 2 2006.257.19:51:24.59#ibcon#read 5, iclass 32, count 2 2006.257.19:51:24.59#ibcon#about to read 6, iclass 32, count 2 2006.257.19:51:24.59#ibcon#read 6, iclass 32, count 2 2006.257.19:51:24.59#ibcon#end of sib2, iclass 32, count 2 2006.257.19:51:24.59#ibcon#*mode == 0, iclass 32, count 2 2006.257.19:51:24.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.19:51:24.59#ibcon#[27=AT05-04\r\n] 2006.257.19:51:24.59#ibcon#*before write, iclass 32, count 2 2006.257.19:51:24.60#ibcon#enter sib2, iclass 32, count 2 2006.257.19:51:24.60#ibcon#flushed, iclass 32, count 2 2006.257.19:51:24.60#ibcon#about to write, iclass 32, count 2 2006.257.19:51:24.60#ibcon#wrote, iclass 32, count 2 2006.257.19:51:24.60#ibcon#about to read 3, iclass 32, count 2 2006.257.19:51:24.62#ibcon#read 3, iclass 32, count 2 2006.257.19:51:24.62#ibcon#about to read 4, iclass 32, count 2 2006.257.19:51:24.62#ibcon#read 4, iclass 32, count 2 2006.257.19:51:24.62#ibcon#about to read 5, iclass 32, count 2 2006.257.19:51:24.62#ibcon#read 5, iclass 32, count 2 2006.257.19:51:24.62#ibcon#about to read 6, iclass 32, count 2 2006.257.19:51:24.62#ibcon#read 6, iclass 32, count 2 2006.257.19:51:24.62#ibcon#end of sib2, iclass 32, count 2 2006.257.19:51:24.62#ibcon#*after write, iclass 32, count 2 2006.257.19:51:24.62#ibcon#*before return 0, iclass 32, count 2 2006.257.19:51:24.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:24.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.19:51:24.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.19:51:24.63#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:24.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:24.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:24.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:24.74#ibcon#enter wrdev, iclass 32, count 0 2006.257.19:51:24.74#ibcon#first serial, iclass 32, count 0 2006.257.19:51:24.74#ibcon#enter sib2, iclass 32, count 0 2006.257.19:51:24.74#ibcon#flushed, iclass 32, count 0 2006.257.19:51:24.74#ibcon#about to write, iclass 32, count 0 2006.257.19:51:24.74#ibcon#wrote, iclass 32, count 0 2006.257.19:51:24.74#ibcon#about to read 3, iclass 32, count 0 2006.257.19:51:24.76#ibcon#read 3, iclass 32, count 0 2006.257.19:51:24.76#ibcon#about to read 4, iclass 32, count 0 2006.257.19:51:24.76#ibcon#read 4, iclass 32, count 0 2006.257.19:51:24.76#ibcon#about to read 5, iclass 32, count 0 2006.257.19:51:24.76#ibcon#read 5, iclass 32, count 0 2006.257.19:51:24.76#ibcon#about to read 6, iclass 32, count 0 2006.257.19:51:24.76#ibcon#read 6, iclass 32, count 0 2006.257.19:51:24.76#ibcon#end of sib2, iclass 32, count 0 2006.257.19:51:24.76#ibcon#*mode == 0, iclass 32, count 0 2006.257.19:51:24.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.19:51:24.76#ibcon#[27=USB\r\n] 2006.257.19:51:24.76#ibcon#*before write, iclass 32, count 0 2006.257.19:51:24.77#ibcon#enter sib2, iclass 32, count 0 2006.257.19:51:24.77#ibcon#flushed, iclass 32, count 0 2006.257.19:51:24.77#ibcon#about to write, iclass 32, count 0 2006.257.19:51:24.77#ibcon#wrote, iclass 32, count 0 2006.257.19:51:24.77#ibcon#about to read 3, iclass 32, count 0 2006.257.19:51:24.79#ibcon#read 3, iclass 32, count 0 2006.257.19:51:24.79#ibcon#about to read 4, iclass 32, count 0 2006.257.19:51:24.79#ibcon#read 4, iclass 32, count 0 2006.257.19:51:24.79#ibcon#about to read 5, iclass 32, count 0 2006.257.19:51:24.79#ibcon#read 5, iclass 32, count 0 2006.257.19:51:24.79#ibcon#about to read 6, iclass 32, count 0 2006.257.19:51:24.79#ibcon#read 6, iclass 32, count 0 2006.257.19:51:24.79#ibcon#end of sib2, iclass 32, count 0 2006.257.19:51:24.79#ibcon#*after write, iclass 32, count 0 2006.257.19:51:24.79#ibcon#*before return 0, iclass 32, count 0 2006.257.19:51:24.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:24.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.19:51:24.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.19:51:24.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.19:51:24.80$vck44/vblo=6,719.99 2006.257.19:51:24.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.19:51:24.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.19:51:24.80#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:24.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:24.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:24.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:24.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.19:51:24.80#ibcon#first serial, iclass 34, count 0 2006.257.19:51:24.80#ibcon#enter sib2, iclass 34, count 0 2006.257.19:51:24.80#ibcon#flushed, iclass 34, count 0 2006.257.19:51:24.80#ibcon#about to write, iclass 34, count 0 2006.257.19:51:24.80#ibcon#wrote, iclass 34, count 0 2006.257.19:51:24.80#ibcon#about to read 3, iclass 34, count 0 2006.257.19:51:24.81#ibcon#read 3, iclass 34, count 0 2006.257.19:51:24.81#ibcon#about to read 4, iclass 34, count 0 2006.257.19:51:24.81#ibcon#read 4, iclass 34, count 0 2006.257.19:51:24.81#ibcon#about to read 5, iclass 34, count 0 2006.257.19:51:24.81#ibcon#read 5, iclass 34, count 0 2006.257.19:51:24.81#ibcon#about to read 6, iclass 34, count 0 2006.257.19:51:24.81#ibcon#read 6, iclass 34, count 0 2006.257.19:51:24.81#ibcon#end of sib2, iclass 34, count 0 2006.257.19:51:24.81#ibcon#*mode == 0, iclass 34, count 0 2006.257.19:51:24.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.19:51:24.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.19:51:24.82#ibcon#*before write, iclass 34, count 0 2006.257.19:51:24.82#ibcon#enter sib2, iclass 34, count 0 2006.257.19:51:24.82#ibcon#flushed, iclass 34, count 0 2006.257.19:51:24.82#ibcon#about to write, iclass 34, count 0 2006.257.19:51:24.82#ibcon#wrote, iclass 34, count 0 2006.257.19:51:24.82#ibcon#about to read 3, iclass 34, count 0 2006.257.19:51:24.85#ibcon#read 3, iclass 34, count 0 2006.257.19:51:24.85#ibcon#about to read 4, iclass 34, count 0 2006.257.19:51:24.85#ibcon#read 4, iclass 34, count 0 2006.257.19:51:24.85#ibcon#about to read 5, iclass 34, count 0 2006.257.19:51:24.85#ibcon#read 5, iclass 34, count 0 2006.257.19:51:24.85#ibcon#about to read 6, iclass 34, count 0 2006.257.19:51:24.85#ibcon#read 6, iclass 34, count 0 2006.257.19:51:24.85#ibcon#end of sib2, iclass 34, count 0 2006.257.19:51:24.85#ibcon#*after write, iclass 34, count 0 2006.257.19:51:24.85#ibcon#*before return 0, iclass 34, count 0 2006.257.19:51:24.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:24.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.19:51:24.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.19:51:24.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.19:51:24.86$vck44/vb=6,4 2006.257.19:51:24.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.19:51:24.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.19:51:24.86#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:24.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:24.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:24.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:24.91#ibcon#enter wrdev, iclass 36, count 2 2006.257.19:51:24.91#ibcon#first serial, iclass 36, count 2 2006.257.19:51:24.91#ibcon#enter sib2, iclass 36, count 2 2006.257.19:51:24.91#ibcon#flushed, iclass 36, count 2 2006.257.19:51:24.91#ibcon#about to write, iclass 36, count 2 2006.257.19:51:24.91#ibcon#wrote, iclass 36, count 2 2006.257.19:51:24.91#ibcon#about to read 3, iclass 36, count 2 2006.257.19:51:24.93#ibcon#read 3, iclass 36, count 2 2006.257.19:51:24.93#ibcon#about to read 4, iclass 36, count 2 2006.257.19:51:24.93#ibcon#read 4, iclass 36, count 2 2006.257.19:51:24.93#ibcon#about to read 5, iclass 36, count 2 2006.257.19:51:24.93#ibcon#read 5, iclass 36, count 2 2006.257.19:51:24.93#ibcon#about to read 6, iclass 36, count 2 2006.257.19:51:24.93#ibcon#read 6, iclass 36, count 2 2006.257.19:51:24.93#ibcon#end of sib2, iclass 36, count 2 2006.257.19:51:24.93#ibcon#*mode == 0, iclass 36, count 2 2006.257.19:51:24.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.19:51:24.93#ibcon#[27=AT06-04\r\n] 2006.257.19:51:24.93#ibcon#*before write, iclass 36, count 2 2006.257.19:51:24.94#ibcon#enter sib2, iclass 36, count 2 2006.257.19:51:24.94#ibcon#flushed, iclass 36, count 2 2006.257.19:51:24.94#ibcon#about to write, iclass 36, count 2 2006.257.19:51:24.94#ibcon#wrote, iclass 36, count 2 2006.257.19:51:24.94#ibcon#about to read 3, iclass 36, count 2 2006.257.19:51:24.96#ibcon#read 3, iclass 36, count 2 2006.257.19:51:24.96#ibcon#about to read 4, iclass 36, count 2 2006.257.19:51:24.96#ibcon#read 4, iclass 36, count 2 2006.257.19:51:24.96#ibcon#about to read 5, iclass 36, count 2 2006.257.19:51:24.96#ibcon#read 5, iclass 36, count 2 2006.257.19:51:24.96#ibcon#about to read 6, iclass 36, count 2 2006.257.19:51:24.96#ibcon#read 6, iclass 36, count 2 2006.257.19:51:24.96#ibcon#end of sib2, iclass 36, count 2 2006.257.19:51:24.96#ibcon#*after write, iclass 36, count 2 2006.257.19:51:24.96#ibcon#*before return 0, iclass 36, count 2 2006.257.19:51:24.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:24.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.19:51:24.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.19:51:24.97#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:24.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:25.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:25.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:25.08#ibcon#enter wrdev, iclass 36, count 0 2006.257.19:51:25.08#ibcon#first serial, iclass 36, count 0 2006.257.19:51:25.08#ibcon#enter sib2, iclass 36, count 0 2006.257.19:51:25.08#ibcon#flushed, iclass 36, count 0 2006.257.19:51:25.08#ibcon#about to write, iclass 36, count 0 2006.257.19:51:25.08#ibcon#wrote, iclass 36, count 0 2006.257.19:51:25.08#ibcon#about to read 3, iclass 36, count 0 2006.257.19:51:25.10#ibcon#read 3, iclass 36, count 0 2006.257.19:51:25.10#ibcon#about to read 4, iclass 36, count 0 2006.257.19:51:25.10#ibcon#read 4, iclass 36, count 0 2006.257.19:51:25.10#ibcon#about to read 5, iclass 36, count 0 2006.257.19:51:25.10#ibcon#read 5, iclass 36, count 0 2006.257.19:51:25.10#ibcon#about to read 6, iclass 36, count 0 2006.257.19:51:25.10#ibcon#read 6, iclass 36, count 0 2006.257.19:51:25.10#ibcon#end of sib2, iclass 36, count 0 2006.257.19:51:25.10#ibcon#*mode == 0, iclass 36, count 0 2006.257.19:51:25.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.19:51:25.10#ibcon#[27=USB\r\n] 2006.257.19:51:25.10#ibcon#*before write, iclass 36, count 0 2006.257.19:51:25.11#ibcon#enter sib2, iclass 36, count 0 2006.257.19:51:25.11#ibcon#flushed, iclass 36, count 0 2006.257.19:51:25.11#ibcon#about to write, iclass 36, count 0 2006.257.19:51:25.11#ibcon#wrote, iclass 36, count 0 2006.257.19:51:25.11#ibcon#about to read 3, iclass 36, count 0 2006.257.19:51:25.14#ibcon#read 3, iclass 36, count 0 2006.257.19:51:25.14#ibcon#about to read 4, iclass 36, count 0 2006.257.19:51:25.14#ibcon#read 4, iclass 36, count 0 2006.257.19:51:25.14#ibcon#about to read 5, iclass 36, count 0 2006.257.19:51:25.14#ibcon#read 5, iclass 36, count 0 2006.257.19:51:25.14#ibcon#about to read 6, iclass 36, count 0 2006.257.19:51:25.14#ibcon#read 6, iclass 36, count 0 2006.257.19:51:25.14#ibcon#end of sib2, iclass 36, count 0 2006.257.19:51:25.14#ibcon#*after write, iclass 36, count 0 2006.257.19:51:25.14#ibcon#*before return 0, iclass 36, count 0 2006.257.19:51:25.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:25.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.19:51:25.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.19:51:25.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.19:51:25.14$vck44/vblo=7,734.99 2006.257.19:51:25.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.19:51:25.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.19:51:25.14#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:25.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:25.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:25.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:25.14#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:51:25.14#ibcon#first serial, iclass 38, count 0 2006.257.19:51:25.14#ibcon#enter sib2, iclass 38, count 0 2006.257.19:51:25.14#ibcon#flushed, iclass 38, count 0 2006.257.19:51:25.14#ibcon#about to write, iclass 38, count 0 2006.257.19:51:25.14#ibcon#wrote, iclass 38, count 0 2006.257.19:51:25.14#ibcon#about to read 3, iclass 38, count 0 2006.257.19:51:25.15#ibcon#read 3, iclass 38, count 0 2006.257.19:51:25.15#ibcon#about to read 4, iclass 38, count 0 2006.257.19:51:25.15#ibcon#read 4, iclass 38, count 0 2006.257.19:51:25.15#ibcon#about to read 5, iclass 38, count 0 2006.257.19:51:25.15#ibcon#read 5, iclass 38, count 0 2006.257.19:51:25.15#ibcon#about to read 6, iclass 38, count 0 2006.257.19:51:25.15#ibcon#read 6, iclass 38, count 0 2006.257.19:51:25.15#ibcon#end of sib2, iclass 38, count 0 2006.257.19:51:25.15#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:51:25.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:51:25.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.19:51:25.15#ibcon#*before write, iclass 38, count 0 2006.257.19:51:25.16#ibcon#enter sib2, iclass 38, count 0 2006.257.19:51:25.16#ibcon#flushed, iclass 38, count 0 2006.257.19:51:25.16#ibcon#about to write, iclass 38, count 0 2006.257.19:51:25.16#ibcon#wrote, iclass 38, count 0 2006.257.19:51:25.16#ibcon#about to read 3, iclass 38, count 0 2006.257.19:51:25.19#ibcon#read 3, iclass 38, count 0 2006.257.19:51:25.19#ibcon#about to read 4, iclass 38, count 0 2006.257.19:51:25.19#ibcon#read 4, iclass 38, count 0 2006.257.19:51:25.19#ibcon#about to read 5, iclass 38, count 0 2006.257.19:51:25.19#ibcon#read 5, iclass 38, count 0 2006.257.19:51:25.19#ibcon#about to read 6, iclass 38, count 0 2006.257.19:51:25.19#ibcon#read 6, iclass 38, count 0 2006.257.19:51:25.19#ibcon#end of sib2, iclass 38, count 0 2006.257.19:51:25.19#ibcon#*after write, iclass 38, count 0 2006.257.19:51:25.19#ibcon#*before return 0, iclass 38, count 0 2006.257.19:51:25.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:25.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.19:51:25.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:51:25.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:51:25.20$vck44/vb=7,4 2006.257.19:51:25.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.19:51:25.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.19:51:25.20#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:25.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:25.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:25.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:25.25#ibcon#enter wrdev, iclass 40, count 2 2006.257.19:51:25.25#ibcon#first serial, iclass 40, count 2 2006.257.19:51:25.25#ibcon#enter sib2, iclass 40, count 2 2006.257.19:51:25.25#ibcon#flushed, iclass 40, count 2 2006.257.19:51:25.25#ibcon#about to write, iclass 40, count 2 2006.257.19:51:25.25#ibcon#wrote, iclass 40, count 2 2006.257.19:51:25.25#ibcon#about to read 3, iclass 40, count 2 2006.257.19:51:25.27#ibcon#read 3, iclass 40, count 2 2006.257.19:51:25.27#ibcon#about to read 4, iclass 40, count 2 2006.257.19:51:25.27#ibcon#read 4, iclass 40, count 2 2006.257.19:51:25.27#ibcon#about to read 5, iclass 40, count 2 2006.257.19:51:25.27#ibcon#read 5, iclass 40, count 2 2006.257.19:51:25.27#ibcon#about to read 6, iclass 40, count 2 2006.257.19:51:25.27#ibcon#read 6, iclass 40, count 2 2006.257.19:51:25.27#ibcon#end of sib2, iclass 40, count 2 2006.257.19:51:25.27#ibcon#*mode == 0, iclass 40, count 2 2006.257.19:51:25.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.19:51:25.27#ibcon#[27=AT07-04\r\n] 2006.257.19:51:25.27#ibcon#*before write, iclass 40, count 2 2006.257.19:51:25.28#ibcon#enter sib2, iclass 40, count 2 2006.257.19:51:25.28#ibcon#flushed, iclass 40, count 2 2006.257.19:51:25.28#ibcon#about to write, iclass 40, count 2 2006.257.19:51:25.28#ibcon#wrote, iclass 40, count 2 2006.257.19:51:25.28#ibcon#about to read 3, iclass 40, count 2 2006.257.19:51:25.30#ibcon#read 3, iclass 40, count 2 2006.257.19:51:25.30#ibcon#about to read 4, iclass 40, count 2 2006.257.19:51:25.30#ibcon#read 4, iclass 40, count 2 2006.257.19:51:25.30#ibcon#about to read 5, iclass 40, count 2 2006.257.19:51:25.30#ibcon#read 5, iclass 40, count 2 2006.257.19:51:25.30#ibcon#about to read 6, iclass 40, count 2 2006.257.19:51:25.30#ibcon#read 6, iclass 40, count 2 2006.257.19:51:25.30#ibcon#end of sib2, iclass 40, count 2 2006.257.19:51:25.30#ibcon#*after write, iclass 40, count 2 2006.257.19:51:25.30#ibcon#*before return 0, iclass 40, count 2 2006.257.19:51:25.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:25.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.19:51:25.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.19:51:25.31#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:25.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:25.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:25.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:25.42#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:51:25.42#ibcon#first serial, iclass 40, count 0 2006.257.19:51:25.42#ibcon#enter sib2, iclass 40, count 0 2006.257.19:51:25.42#ibcon#flushed, iclass 40, count 0 2006.257.19:51:25.42#ibcon#about to write, iclass 40, count 0 2006.257.19:51:25.42#ibcon#wrote, iclass 40, count 0 2006.257.19:51:25.42#ibcon#about to read 3, iclass 40, count 0 2006.257.19:51:25.44#ibcon#read 3, iclass 40, count 0 2006.257.19:51:25.44#ibcon#about to read 4, iclass 40, count 0 2006.257.19:51:25.44#ibcon#read 4, iclass 40, count 0 2006.257.19:51:25.44#ibcon#about to read 5, iclass 40, count 0 2006.257.19:51:25.44#ibcon#read 5, iclass 40, count 0 2006.257.19:51:25.44#ibcon#about to read 6, iclass 40, count 0 2006.257.19:51:25.44#ibcon#read 6, iclass 40, count 0 2006.257.19:51:25.44#ibcon#end of sib2, iclass 40, count 0 2006.257.19:51:25.44#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:51:25.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:51:25.44#ibcon#[27=USB\r\n] 2006.257.19:51:25.44#ibcon#*before write, iclass 40, count 0 2006.257.19:51:25.44#ibcon#enter sib2, iclass 40, count 0 2006.257.19:51:25.45#ibcon#flushed, iclass 40, count 0 2006.257.19:51:25.45#ibcon#about to write, iclass 40, count 0 2006.257.19:51:25.45#ibcon#wrote, iclass 40, count 0 2006.257.19:51:25.45#ibcon#about to read 3, iclass 40, count 0 2006.257.19:51:25.47#ibcon#read 3, iclass 40, count 0 2006.257.19:51:25.47#ibcon#about to read 4, iclass 40, count 0 2006.257.19:51:25.47#ibcon#read 4, iclass 40, count 0 2006.257.19:51:25.47#ibcon#about to read 5, iclass 40, count 0 2006.257.19:51:25.47#ibcon#read 5, iclass 40, count 0 2006.257.19:51:25.47#ibcon#about to read 6, iclass 40, count 0 2006.257.19:51:25.47#ibcon#read 6, iclass 40, count 0 2006.257.19:51:25.47#ibcon#end of sib2, iclass 40, count 0 2006.257.19:51:25.47#ibcon#*after write, iclass 40, count 0 2006.257.19:51:25.47#ibcon#*before return 0, iclass 40, count 0 2006.257.19:51:25.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:25.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.19:51:25.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:51:25.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:51:25.48$vck44/vblo=8,744.99 2006.257.19:51:25.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.19:51:25.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.19:51:25.48#ibcon#ireg 17 cls_cnt 0 2006.257.19:51:25.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:25.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:25.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:25.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:51:25.48#ibcon#first serial, iclass 4, count 0 2006.257.19:51:25.48#ibcon#enter sib2, iclass 4, count 0 2006.257.19:51:25.48#ibcon#flushed, iclass 4, count 0 2006.257.19:51:25.48#ibcon#about to write, iclass 4, count 0 2006.257.19:51:25.48#ibcon#wrote, iclass 4, count 0 2006.257.19:51:25.48#ibcon#about to read 3, iclass 4, count 0 2006.257.19:51:25.49#ibcon#read 3, iclass 4, count 0 2006.257.19:51:25.49#ibcon#about to read 4, iclass 4, count 0 2006.257.19:51:25.49#ibcon#read 4, iclass 4, count 0 2006.257.19:51:25.49#ibcon#about to read 5, iclass 4, count 0 2006.257.19:51:25.49#ibcon#read 5, iclass 4, count 0 2006.257.19:51:25.49#ibcon#about to read 6, iclass 4, count 0 2006.257.19:51:25.49#ibcon#read 6, iclass 4, count 0 2006.257.19:51:25.49#ibcon#end of sib2, iclass 4, count 0 2006.257.19:51:25.49#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:51:25.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:51:25.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.19:51:25.49#ibcon#*before write, iclass 4, count 0 2006.257.19:51:25.50#ibcon#enter sib2, iclass 4, count 0 2006.257.19:51:25.50#ibcon#flushed, iclass 4, count 0 2006.257.19:51:25.50#ibcon#about to write, iclass 4, count 0 2006.257.19:51:25.50#ibcon#wrote, iclass 4, count 0 2006.257.19:51:25.50#ibcon#about to read 3, iclass 4, count 0 2006.257.19:51:25.53#ibcon#read 3, iclass 4, count 0 2006.257.19:51:25.53#ibcon#about to read 4, iclass 4, count 0 2006.257.19:51:25.53#ibcon#read 4, iclass 4, count 0 2006.257.19:51:25.53#ibcon#about to read 5, iclass 4, count 0 2006.257.19:51:25.53#ibcon#read 5, iclass 4, count 0 2006.257.19:51:25.53#ibcon#about to read 6, iclass 4, count 0 2006.257.19:51:25.53#ibcon#read 6, iclass 4, count 0 2006.257.19:51:25.53#ibcon#end of sib2, iclass 4, count 0 2006.257.19:51:25.53#ibcon#*after write, iclass 4, count 0 2006.257.19:51:25.53#ibcon#*before return 0, iclass 4, count 0 2006.257.19:51:25.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:25.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.19:51:25.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:51:25.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:51:25.54$vck44/vb=8,4 2006.257.19:51:25.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.19:51:25.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.19:51:25.54#ibcon#ireg 11 cls_cnt 2 2006.257.19:51:25.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:25.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:25.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:25.59#ibcon#enter wrdev, iclass 6, count 2 2006.257.19:51:25.59#ibcon#first serial, iclass 6, count 2 2006.257.19:51:25.59#ibcon#enter sib2, iclass 6, count 2 2006.257.19:51:25.59#ibcon#flushed, iclass 6, count 2 2006.257.19:51:25.59#ibcon#about to write, iclass 6, count 2 2006.257.19:51:25.59#ibcon#wrote, iclass 6, count 2 2006.257.19:51:25.59#ibcon#about to read 3, iclass 6, count 2 2006.257.19:51:25.61#ibcon#read 3, iclass 6, count 2 2006.257.19:51:25.61#ibcon#about to read 4, iclass 6, count 2 2006.257.19:51:25.61#ibcon#read 4, iclass 6, count 2 2006.257.19:51:25.61#ibcon#about to read 5, iclass 6, count 2 2006.257.19:51:25.61#ibcon#read 5, iclass 6, count 2 2006.257.19:51:25.61#ibcon#about to read 6, iclass 6, count 2 2006.257.19:51:25.61#ibcon#read 6, iclass 6, count 2 2006.257.19:51:25.61#ibcon#end of sib2, iclass 6, count 2 2006.257.19:51:25.61#ibcon#*mode == 0, iclass 6, count 2 2006.257.19:51:25.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.19:51:25.61#ibcon#[27=AT08-04\r\n] 2006.257.19:51:25.61#ibcon#*before write, iclass 6, count 2 2006.257.19:51:25.61#ibcon#enter sib2, iclass 6, count 2 2006.257.19:51:25.62#ibcon#flushed, iclass 6, count 2 2006.257.19:51:25.62#ibcon#about to write, iclass 6, count 2 2006.257.19:51:25.62#ibcon#wrote, iclass 6, count 2 2006.257.19:51:25.62#ibcon#about to read 3, iclass 6, count 2 2006.257.19:51:25.64#ibcon#read 3, iclass 6, count 2 2006.257.19:51:25.64#ibcon#about to read 4, iclass 6, count 2 2006.257.19:51:25.64#ibcon#read 4, iclass 6, count 2 2006.257.19:51:25.64#ibcon#about to read 5, iclass 6, count 2 2006.257.19:51:25.64#ibcon#read 5, iclass 6, count 2 2006.257.19:51:25.64#ibcon#about to read 6, iclass 6, count 2 2006.257.19:51:25.64#ibcon#read 6, iclass 6, count 2 2006.257.19:51:25.64#ibcon#end of sib2, iclass 6, count 2 2006.257.19:51:25.64#ibcon#*after write, iclass 6, count 2 2006.257.19:51:25.64#ibcon#*before return 0, iclass 6, count 2 2006.257.19:51:25.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:25.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.19:51:25.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.19:51:25.65#ibcon#ireg 7 cls_cnt 0 2006.257.19:51:25.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:25.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:25.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:25.76#ibcon#enter wrdev, iclass 6, count 0 2006.257.19:51:25.76#ibcon#first serial, iclass 6, count 0 2006.257.19:51:25.76#ibcon#enter sib2, iclass 6, count 0 2006.257.19:51:25.76#ibcon#flushed, iclass 6, count 0 2006.257.19:51:25.76#ibcon#about to write, iclass 6, count 0 2006.257.19:51:25.76#ibcon#wrote, iclass 6, count 0 2006.257.19:51:25.76#ibcon#about to read 3, iclass 6, count 0 2006.257.19:51:25.78#ibcon#read 3, iclass 6, count 0 2006.257.19:51:25.78#ibcon#about to read 4, iclass 6, count 0 2006.257.19:51:25.78#ibcon#read 4, iclass 6, count 0 2006.257.19:51:25.78#ibcon#about to read 5, iclass 6, count 0 2006.257.19:51:25.78#ibcon#read 5, iclass 6, count 0 2006.257.19:51:25.78#ibcon#about to read 6, iclass 6, count 0 2006.257.19:51:25.78#ibcon#read 6, iclass 6, count 0 2006.257.19:51:25.78#ibcon#end of sib2, iclass 6, count 0 2006.257.19:51:25.78#ibcon#*mode == 0, iclass 6, count 0 2006.257.19:51:25.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.19:51:25.78#ibcon#[27=USB\r\n] 2006.257.19:51:25.78#ibcon#*before write, iclass 6, count 0 2006.257.19:51:25.78#ibcon#enter sib2, iclass 6, count 0 2006.257.19:51:25.79#ibcon#flushed, iclass 6, count 0 2006.257.19:51:25.79#ibcon#about to write, iclass 6, count 0 2006.257.19:51:25.79#ibcon#wrote, iclass 6, count 0 2006.257.19:51:25.79#ibcon#about to read 3, iclass 6, count 0 2006.257.19:51:25.81#ibcon#read 3, iclass 6, count 0 2006.257.19:51:25.81#ibcon#about to read 4, iclass 6, count 0 2006.257.19:51:25.81#ibcon#read 4, iclass 6, count 0 2006.257.19:51:25.81#ibcon#about to read 5, iclass 6, count 0 2006.257.19:51:25.81#ibcon#read 5, iclass 6, count 0 2006.257.19:51:25.81#ibcon#about to read 6, iclass 6, count 0 2006.257.19:51:25.81#ibcon#read 6, iclass 6, count 0 2006.257.19:51:25.81#ibcon#end of sib2, iclass 6, count 0 2006.257.19:51:25.81#ibcon#*after write, iclass 6, count 0 2006.257.19:51:25.81#ibcon#*before return 0, iclass 6, count 0 2006.257.19:51:25.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:25.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.19:51:25.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.19:51:25.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.19:51:25.82$vck44/vabw=wide 2006.257.19:51:25.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.19:51:25.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.19:51:25.82#ibcon#ireg 8 cls_cnt 0 2006.257.19:51:25.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:25.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:25.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:25.82#ibcon#enter wrdev, iclass 10, count 0 2006.257.19:51:25.82#ibcon#first serial, iclass 10, count 0 2006.257.19:51:25.82#ibcon#enter sib2, iclass 10, count 0 2006.257.19:51:25.82#ibcon#flushed, iclass 10, count 0 2006.257.19:51:25.82#ibcon#about to write, iclass 10, count 0 2006.257.19:51:25.82#ibcon#wrote, iclass 10, count 0 2006.257.19:51:25.82#ibcon#about to read 3, iclass 10, count 0 2006.257.19:51:25.83#ibcon#read 3, iclass 10, count 0 2006.257.19:51:25.83#ibcon#about to read 4, iclass 10, count 0 2006.257.19:51:25.83#ibcon#read 4, iclass 10, count 0 2006.257.19:51:25.83#ibcon#about to read 5, iclass 10, count 0 2006.257.19:51:25.83#ibcon#read 5, iclass 10, count 0 2006.257.19:51:25.83#ibcon#about to read 6, iclass 10, count 0 2006.257.19:51:25.83#ibcon#read 6, iclass 10, count 0 2006.257.19:51:25.83#ibcon#end of sib2, iclass 10, count 0 2006.257.19:51:25.83#ibcon#*mode == 0, iclass 10, count 0 2006.257.19:51:25.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.19:51:25.83#ibcon#[25=BW32\r\n] 2006.257.19:51:25.83#ibcon#*before write, iclass 10, count 0 2006.257.19:51:25.84#ibcon#enter sib2, iclass 10, count 0 2006.257.19:51:25.84#ibcon#flushed, iclass 10, count 0 2006.257.19:51:25.84#ibcon#about to write, iclass 10, count 0 2006.257.19:51:25.84#ibcon#wrote, iclass 10, count 0 2006.257.19:51:25.84#ibcon#about to read 3, iclass 10, count 0 2006.257.19:51:25.86#ibcon#read 3, iclass 10, count 0 2006.257.19:51:25.86#ibcon#about to read 4, iclass 10, count 0 2006.257.19:51:25.86#ibcon#read 4, iclass 10, count 0 2006.257.19:51:25.86#ibcon#about to read 5, iclass 10, count 0 2006.257.19:51:25.86#ibcon#read 5, iclass 10, count 0 2006.257.19:51:25.86#ibcon#about to read 6, iclass 10, count 0 2006.257.19:51:25.86#ibcon#read 6, iclass 10, count 0 2006.257.19:51:25.86#ibcon#end of sib2, iclass 10, count 0 2006.257.19:51:25.86#ibcon#*after write, iclass 10, count 0 2006.257.19:51:25.86#ibcon#*before return 0, iclass 10, count 0 2006.257.19:51:25.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:25.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.19:51:25.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.19:51:25.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.19:51:25.87$vck44/vbbw=wide 2006.257.19:51:25.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.19:51:25.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.19:51:25.87#ibcon#ireg 8 cls_cnt 0 2006.257.19:51:25.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:51:25.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:51:25.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:51:25.93#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:51:25.93#ibcon#first serial, iclass 12, count 0 2006.257.19:51:25.93#ibcon#enter sib2, iclass 12, count 0 2006.257.19:51:25.93#ibcon#flushed, iclass 12, count 0 2006.257.19:51:25.93#ibcon#about to write, iclass 12, count 0 2006.257.19:51:25.93#ibcon#wrote, iclass 12, count 0 2006.257.19:51:25.93#ibcon#about to read 3, iclass 12, count 0 2006.257.19:51:25.95#ibcon#read 3, iclass 12, count 0 2006.257.19:51:25.95#ibcon#about to read 4, iclass 12, count 0 2006.257.19:51:25.95#ibcon#read 4, iclass 12, count 0 2006.257.19:51:25.95#ibcon#about to read 5, iclass 12, count 0 2006.257.19:51:25.95#ibcon#read 5, iclass 12, count 0 2006.257.19:51:25.95#ibcon#about to read 6, iclass 12, count 0 2006.257.19:51:25.95#ibcon#read 6, iclass 12, count 0 2006.257.19:51:25.95#ibcon#end of sib2, iclass 12, count 0 2006.257.19:51:25.95#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:51:25.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:51:25.95#ibcon#[27=BW32\r\n] 2006.257.19:51:25.95#ibcon#*before write, iclass 12, count 0 2006.257.19:51:25.95#ibcon#enter sib2, iclass 12, count 0 2006.257.19:51:25.96#ibcon#flushed, iclass 12, count 0 2006.257.19:51:25.96#ibcon#about to write, iclass 12, count 0 2006.257.19:51:25.96#ibcon#wrote, iclass 12, count 0 2006.257.19:51:25.96#ibcon#about to read 3, iclass 12, count 0 2006.257.19:51:25.98#ibcon#read 3, iclass 12, count 0 2006.257.19:51:25.98#ibcon#about to read 4, iclass 12, count 0 2006.257.19:51:25.98#ibcon#read 4, iclass 12, count 0 2006.257.19:51:25.98#ibcon#about to read 5, iclass 12, count 0 2006.257.19:51:25.98#ibcon#read 5, iclass 12, count 0 2006.257.19:51:25.98#ibcon#about to read 6, iclass 12, count 0 2006.257.19:51:25.98#ibcon#read 6, iclass 12, count 0 2006.257.19:51:25.98#ibcon#end of sib2, iclass 12, count 0 2006.257.19:51:25.98#ibcon#*after write, iclass 12, count 0 2006.257.19:51:25.98#ibcon#*before return 0, iclass 12, count 0 2006.257.19:51:25.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:51:25.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:51:25.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:51:25.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:51:25.99$setupk4/ifdk4 2006.257.19:51:25.99$ifdk4/lo= 2006.257.19:51:25.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.19:51:25.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.19:51:25.99$ifdk4/patch= 2006.257.19:51:25.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.19:51:25.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.19:51:25.99$setupk4/!*+20s 2006.257.19:51:26.77#abcon#<5=/14 1.4 4.3 17.53 961014.6\r\n> 2006.257.19:51:26.79#abcon#{5=INTERFACE CLEAR} 2006.257.19:51:26.85#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:51:36.94#abcon#<5=/14 1.4 4.3 17.53 961014.6\r\n> 2006.257.19:51:36.96#abcon#{5=INTERFACE CLEAR} 2006.257.19:51:37.02#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:51:40.13#trakl#Source acquired 2006.257.19:51:40.14#flagr#flagr/antenna,acquired 2006.257.19:51:40.50$setupk4/"tpicd 2006.257.19:51:40.50$setupk4/echo=off 2006.257.19:51:40.51$setupk4/xlog=off 2006.257.19:51:40.51:!2006.257.19:52:47 2006.257.19:52:47.02:preob 2006.257.19:52:48.14/onsource/TRACKING 2006.257.19:52:48.14:!2006.257.19:52:57 2006.257.19:52:57.01:"tape 2006.257.19:52:57.02:"st=record 2006.257.19:52:57.02:data_valid=on 2006.257.19:52:57.02:midob 2006.257.19:52:58.13/onsource/TRACKING 2006.257.19:52:58.14/wx/17.53,1014.6,96 2006.257.19:52:58.20/cable/+6.4853E-03 2006.257.19:52:59.29/va/01,08,usb,yes,32,35 2006.257.19:52:59.29/va/02,07,usb,yes,35,35 2006.257.19:52:59.29/va/03,08,usb,yes,31,33 2006.257.19:52:59.29/va/04,07,usb,yes,36,38 2006.257.19:52:59.29/va/05,04,usb,yes,32,33 2006.257.19:52:59.29/va/06,04,usb,yes,36,35 2006.257.19:52:59.29/va/07,04,usb,yes,37,37 2006.257.19:52:59.29/va/08,04,usb,yes,31,38 2006.257.19:52:59.52/valo/01,524.99,yes,locked 2006.257.19:52:59.52/valo/02,534.99,yes,locked 2006.257.19:52:59.52/valo/03,564.99,yes,locked 2006.257.19:52:59.52/valo/04,624.99,yes,locked 2006.257.19:52:59.52/valo/05,734.99,yes,locked 2006.257.19:52:59.52/valo/06,814.99,yes,locked 2006.257.19:52:59.52/valo/07,864.99,yes,locked 2006.257.19:52:59.52/valo/08,884.99,yes,locked 2006.257.19:53:00.61/vb/01,04,usb,yes,31,29 2006.257.19:53:00.61/vb/02,05,usb,yes,29,29 2006.257.19:53:00.61/vb/03,04,usb,yes,30,33 2006.257.19:53:00.61/vb/04,05,usb,yes,31,30 2006.257.19:53:00.61/vb/05,04,usb,yes,27,30 2006.257.19:53:00.61/vb/06,04,usb,yes,32,28 2006.257.19:53:00.61/vb/07,04,usb,yes,31,31 2006.257.19:53:00.61/vb/08,04,usb,yes,29,32 2006.257.19:53:00.84/vblo/01,629.99,yes,locked 2006.257.19:53:00.84/vblo/02,634.99,yes,locked 2006.257.19:53:00.84/vblo/03,649.99,yes,locked 2006.257.19:53:00.84/vblo/04,679.99,yes,locked 2006.257.19:53:00.84/vblo/05,709.99,yes,locked 2006.257.19:53:00.84/vblo/06,719.99,yes,locked 2006.257.19:53:00.84/vblo/07,734.99,yes,locked 2006.257.19:53:00.84/vblo/08,744.99,yes,locked 2006.257.19:53:00.99/vabw/8 2006.257.19:53:01.14/vbbw/8 2006.257.19:53:01.23/xfe/off,on,14.5 2006.257.19:53:01.61/ifatt/23,28,28,28 2006.257.19:53:02.07/fmout-gps/S +4.53E-07 2006.257.19:53:02.12:!2006.257.19:53:57 2006.257.19:53:57.01:data_valid=off 2006.257.19:53:57.02:"et 2006.257.19:53:57.02:!+3s 2006.257.19:54:00.03:"tape 2006.257.19:54:00.04:postob 2006.257.19:54:00.23/cable/+6.4863E-03 2006.257.19:54:00.24/wx/17.53,1014.6,96 2006.257.19:54:00.29/fmout-gps/S +4.53E-07 2006.257.19:54:00.30:scan_name=257-1956,jd0609,50 2006.257.19:54:00.30:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.19:54:01.14#flagr#flagr/antenna,new-source 2006.257.19:54:01.15:checkk5 2006.257.19:54:01.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.19:54:01.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.19:54:02.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.19:54:02.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.19:54:02.85/chk_obsdata//k5ts1/T2571952??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.19:54:03.18/chk_obsdata//k5ts2/T2571952??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.19:54:03.51/chk_obsdata//k5ts3/T2571952??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.19:54:03.84/chk_obsdata//k5ts4/T2571952??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.19:54:04.50/k5log//k5ts1_log_newline 2006.257.19:54:05.16/k5log//k5ts2_log_newline 2006.257.19:54:05.82/k5log//k5ts3_log_newline 2006.257.19:54:06.47/k5log//k5ts4_log_newline 2006.257.19:54:06.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.19:54:06.49:setupk4=1 2006.257.19:54:06.49$setupk4/echo=on 2006.257.19:54:06.49$setupk4/pcalon 2006.257.19:54:06.49$pcalon/"no phase cal control is implemented here 2006.257.19:54:06.49$setupk4/"tpicd=stop 2006.257.19:54:06.49$setupk4/"rec=synch_on 2006.257.19:54:06.49$setupk4/"rec_mode=128 2006.257.19:54:06.49$setupk4/!* 2006.257.19:54:06.49$setupk4/recpk4 2006.257.19:54:06.49$recpk4/recpatch= 2006.257.19:54:06.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.19:54:06.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.19:54:06.50$setupk4/vck44 2006.257.19:54:06.50$vck44/valo=1,524.99 2006.257.19:54:06.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.19:54:06.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.19:54:06.50#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:06.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:06.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:06.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:06.50#ibcon#enter wrdev, iclass 7, count 0 2006.257.19:54:06.50#ibcon#first serial, iclass 7, count 0 2006.257.19:54:06.50#ibcon#enter sib2, iclass 7, count 0 2006.257.19:54:06.50#ibcon#flushed, iclass 7, count 0 2006.257.19:54:06.50#ibcon#about to write, iclass 7, count 0 2006.257.19:54:06.50#ibcon#wrote, iclass 7, count 0 2006.257.19:54:06.50#ibcon#about to read 3, iclass 7, count 0 2006.257.19:54:06.51#ibcon#read 3, iclass 7, count 0 2006.257.19:54:06.51#ibcon#about to read 4, iclass 7, count 0 2006.257.19:54:06.51#ibcon#read 4, iclass 7, count 0 2006.257.19:54:06.51#ibcon#about to read 5, iclass 7, count 0 2006.257.19:54:06.51#ibcon#read 5, iclass 7, count 0 2006.257.19:54:06.51#ibcon#about to read 6, iclass 7, count 0 2006.257.19:54:06.51#ibcon#read 6, iclass 7, count 0 2006.257.19:54:06.51#ibcon#end of sib2, iclass 7, count 0 2006.257.19:54:06.51#ibcon#*mode == 0, iclass 7, count 0 2006.257.19:54:06.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.19:54:06.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.19:54:06.51#ibcon#*before write, iclass 7, count 0 2006.257.19:54:06.51#ibcon#enter sib2, iclass 7, count 0 2006.257.19:54:06.51#ibcon#flushed, iclass 7, count 0 2006.257.19:54:06.51#ibcon#about to write, iclass 7, count 0 2006.257.19:54:06.51#ibcon#wrote, iclass 7, count 0 2006.257.19:54:06.51#ibcon#about to read 3, iclass 7, count 0 2006.257.19:54:06.56#ibcon#read 3, iclass 7, count 0 2006.257.19:54:06.56#ibcon#about to read 4, iclass 7, count 0 2006.257.19:54:06.56#ibcon#read 4, iclass 7, count 0 2006.257.19:54:06.56#ibcon#about to read 5, iclass 7, count 0 2006.257.19:54:06.56#ibcon#read 5, iclass 7, count 0 2006.257.19:54:06.56#ibcon#about to read 6, iclass 7, count 0 2006.257.19:54:06.56#ibcon#read 6, iclass 7, count 0 2006.257.19:54:06.56#ibcon#end of sib2, iclass 7, count 0 2006.257.19:54:06.56#ibcon#*after write, iclass 7, count 0 2006.257.19:54:06.56#ibcon#*before return 0, iclass 7, count 0 2006.257.19:54:06.56#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:06.56#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:06.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.19:54:06.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.19:54:06.56$vck44/va=1,8 2006.257.19:54:06.56#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.19:54:06.56#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.19:54:06.56#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:06.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:06.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:06.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:06.56#ibcon#enter wrdev, iclass 11, count 2 2006.257.19:54:06.56#ibcon#first serial, iclass 11, count 2 2006.257.19:54:06.56#ibcon#enter sib2, iclass 11, count 2 2006.257.19:54:06.56#ibcon#flushed, iclass 11, count 2 2006.257.19:54:06.56#ibcon#about to write, iclass 11, count 2 2006.257.19:54:06.56#ibcon#wrote, iclass 11, count 2 2006.257.19:54:06.56#ibcon#about to read 3, iclass 11, count 2 2006.257.19:54:06.58#ibcon#read 3, iclass 11, count 2 2006.257.19:54:06.58#ibcon#about to read 4, iclass 11, count 2 2006.257.19:54:06.58#ibcon#read 4, iclass 11, count 2 2006.257.19:54:06.58#ibcon#about to read 5, iclass 11, count 2 2006.257.19:54:06.58#ibcon#read 5, iclass 11, count 2 2006.257.19:54:06.58#ibcon#about to read 6, iclass 11, count 2 2006.257.19:54:06.58#ibcon#read 6, iclass 11, count 2 2006.257.19:54:06.58#ibcon#end of sib2, iclass 11, count 2 2006.257.19:54:06.58#ibcon#*mode == 0, iclass 11, count 2 2006.257.19:54:06.58#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.19:54:06.58#ibcon#[25=AT01-08\r\n] 2006.257.19:54:06.58#ibcon#*before write, iclass 11, count 2 2006.257.19:54:06.58#ibcon#enter sib2, iclass 11, count 2 2006.257.19:54:06.58#ibcon#flushed, iclass 11, count 2 2006.257.19:54:06.58#ibcon#about to write, iclass 11, count 2 2006.257.19:54:06.58#ibcon#wrote, iclass 11, count 2 2006.257.19:54:06.58#ibcon#about to read 3, iclass 11, count 2 2006.257.19:54:06.61#ibcon#read 3, iclass 11, count 2 2006.257.19:54:06.61#ibcon#about to read 4, iclass 11, count 2 2006.257.19:54:06.61#ibcon#read 4, iclass 11, count 2 2006.257.19:54:06.61#ibcon#about to read 5, iclass 11, count 2 2006.257.19:54:06.61#ibcon#read 5, iclass 11, count 2 2006.257.19:54:06.61#ibcon#about to read 6, iclass 11, count 2 2006.257.19:54:06.61#ibcon#read 6, iclass 11, count 2 2006.257.19:54:06.61#ibcon#end of sib2, iclass 11, count 2 2006.257.19:54:06.61#ibcon#*after write, iclass 11, count 2 2006.257.19:54:06.61#ibcon#*before return 0, iclass 11, count 2 2006.257.19:54:06.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:06.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:06.61#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.19:54:06.61#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:06.61#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:06.73#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:06.73#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:06.73#ibcon#enter wrdev, iclass 11, count 0 2006.257.19:54:06.73#ibcon#first serial, iclass 11, count 0 2006.257.19:54:06.73#ibcon#enter sib2, iclass 11, count 0 2006.257.19:54:06.73#ibcon#flushed, iclass 11, count 0 2006.257.19:54:06.73#ibcon#about to write, iclass 11, count 0 2006.257.19:54:06.73#ibcon#wrote, iclass 11, count 0 2006.257.19:54:06.73#ibcon#about to read 3, iclass 11, count 0 2006.257.19:54:06.75#ibcon#read 3, iclass 11, count 0 2006.257.19:54:06.75#ibcon#about to read 4, iclass 11, count 0 2006.257.19:54:06.75#ibcon#read 4, iclass 11, count 0 2006.257.19:54:06.75#ibcon#about to read 5, iclass 11, count 0 2006.257.19:54:06.75#ibcon#read 5, iclass 11, count 0 2006.257.19:54:06.75#ibcon#about to read 6, iclass 11, count 0 2006.257.19:54:06.75#ibcon#read 6, iclass 11, count 0 2006.257.19:54:06.75#ibcon#end of sib2, iclass 11, count 0 2006.257.19:54:06.75#ibcon#*mode == 0, iclass 11, count 0 2006.257.19:54:06.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.19:54:06.75#ibcon#[25=USB\r\n] 2006.257.19:54:06.75#ibcon#*before write, iclass 11, count 0 2006.257.19:54:06.75#ibcon#enter sib2, iclass 11, count 0 2006.257.19:54:06.75#ibcon#flushed, iclass 11, count 0 2006.257.19:54:06.75#ibcon#about to write, iclass 11, count 0 2006.257.19:54:06.75#ibcon#wrote, iclass 11, count 0 2006.257.19:54:06.75#ibcon#about to read 3, iclass 11, count 0 2006.257.19:54:06.78#ibcon#read 3, iclass 11, count 0 2006.257.19:54:06.78#ibcon#about to read 4, iclass 11, count 0 2006.257.19:54:06.78#ibcon#read 4, iclass 11, count 0 2006.257.19:54:06.78#ibcon#about to read 5, iclass 11, count 0 2006.257.19:54:06.78#ibcon#read 5, iclass 11, count 0 2006.257.19:54:06.78#ibcon#about to read 6, iclass 11, count 0 2006.257.19:54:06.78#ibcon#read 6, iclass 11, count 0 2006.257.19:54:06.78#ibcon#end of sib2, iclass 11, count 0 2006.257.19:54:06.78#ibcon#*after write, iclass 11, count 0 2006.257.19:54:06.78#ibcon#*before return 0, iclass 11, count 0 2006.257.19:54:06.78#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:06.78#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:06.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.19:54:06.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.19:54:06.78$vck44/valo=2,534.99 2006.257.19:54:06.78#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.19:54:06.78#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.19:54:06.78#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:06.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:54:06.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:54:06.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:54:06.78#ibcon#enter wrdev, iclass 13, count 0 2006.257.19:54:06.78#ibcon#first serial, iclass 13, count 0 2006.257.19:54:06.78#ibcon#enter sib2, iclass 13, count 0 2006.257.19:54:06.78#ibcon#flushed, iclass 13, count 0 2006.257.19:54:06.78#ibcon#about to write, iclass 13, count 0 2006.257.19:54:06.78#ibcon#wrote, iclass 13, count 0 2006.257.19:54:06.78#ibcon#about to read 3, iclass 13, count 0 2006.257.19:54:06.80#ibcon#read 3, iclass 13, count 0 2006.257.19:54:06.80#ibcon#about to read 4, iclass 13, count 0 2006.257.19:54:06.80#ibcon#read 4, iclass 13, count 0 2006.257.19:54:06.80#ibcon#about to read 5, iclass 13, count 0 2006.257.19:54:06.80#ibcon#read 5, iclass 13, count 0 2006.257.19:54:06.80#ibcon#about to read 6, iclass 13, count 0 2006.257.19:54:06.80#ibcon#read 6, iclass 13, count 0 2006.257.19:54:06.80#ibcon#end of sib2, iclass 13, count 0 2006.257.19:54:06.80#ibcon#*mode == 0, iclass 13, count 0 2006.257.19:54:06.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.19:54:06.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.19:54:06.80#ibcon#*before write, iclass 13, count 0 2006.257.19:54:06.80#ibcon#enter sib2, iclass 13, count 0 2006.257.19:54:06.80#ibcon#flushed, iclass 13, count 0 2006.257.19:54:06.80#ibcon#about to write, iclass 13, count 0 2006.257.19:54:06.80#ibcon#wrote, iclass 13, count 0 2006.257.19:54:06.80#ibcon#about to read 3, iclass 13, count 0 2006.257.19:54:06.84#ibcon#read 3, iclass 13, count 0 2006.257.19:54:06.84#ibcon#about to read 4, iclass 13, count 0 2006.257.19:54:06.84#ibcon#read 4, iclass 13, count 0 2006.257.19:54:06.84#ibcon#about to read 5, iclass 13, count 0 2006.257.19:54:06.84#ibcon#read 5, iclass 13, count 0 2006.257.19:54:06.84#ibcon#about to read 6, iclass 13, count 0 2006.257.19:54:06.84#ibcon#read 6, iclass 13, count 0 2006.257.19:54:06.84#ibcon#end of sib2, iclass 13, count 0 2006.257.19:54:06.84#ibcon#*after write, iclass 13, count 0 2006.257.19:54:06.84#ibcon#*before return 0, iclass 13, count 0 2006.257.19:54:06.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:54:06.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.19:54:06.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.19:54:06.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.19:54:06.84$vck44/va=2,7 2006.257.19:54:06.84#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.19:54:06.84#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.19:54:06.84#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:06.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:54:06.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:54:06.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:54:06.90#ibcon#enter wrdev, iclass 15, count 2 2006.257.19:54:06.90#ibcon#first serial, iclass 15, count 2 2006.257.19:54:06.90#ibcon#enter sib2, iclass 15, count 2 2006.257.19:54:06.90#ibcon#flushed, iclass 15, count 2 2006.257.19:54:06.90#ibcon#about to write, iclass 15, count 2 2006.257.19:54:06.90#ibcon#wrote, iclass 15, count 2 2006.257.19:54:06.90#ibcon#about to read 3, iclass 15, count 2 2006.257.19:54:06.92#ibcon#read 3, iclass 15, count 2 2006.257.19:54:06.92#ibcon#about to read 4, iclass 15, count 2 2006.257.19:54:06.92#ibcon#read 4, iclass 15, count 2 2006.257.19:54:06.92#ibcon#about to read 5, iclass 15, count 2 2006.257.19:54:06.92#ibcon#read 5, iclass 15, count 2 2006.257.19:54:06.92#ibcon#about to read 6, iclass 15, count 2 2006.257.19:54:06.92#ibcon#read 6, iclass 15, count 2 2006.257.19:54:06.92#ibcon#end of sib2, iclass 15, count 2 2006.257.19:54:06.92#ibcon#*mode == 0, iclass 15, count 2 2006.257.19:54:06.92#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.19:54:06.92#ibcon#[25=AT02-07\r\n] 2006.257.19:54:06.92#ibcon#*before write, iclass 15, count 2 2006.257.19:54:06.92#ibcon#enter sib2, iclass 15, count 2 2006.257.19:54:06.92#ibcon#flushed, iclass 15, count 2 2006.257.19:54:06.92#ibcon#about to write, iclass 15, count 2 2006.257.19:54:06.92#ibcon#wrote, iclass 15, count 2 2006.257.19:54:06.92#ibcon#about to read 3, iclass 15, count 2 2006.257.19:54:06.95#ibcon#read 3, iclass 15, count 2 2006.257.19:54:06.95#ibcon#about to read 4, iclass 15, count 2 2006.257.19:54:06.95#ibcon#read 4, iclass 15, count 2 2006.257.19:54:06.95#ibcon#about to read 5, iclass 15, count 2 2006.257.19:54:06.95#ibcon#read 5, iclass 15, count 2 2006.257.19:54:06.95#ibcon#about to read 6, iclass 15, count 2 2006.257.19:54:06.95#ibcon#read 6, iclass 15, count 2 2006.257.19:54:06.95#ibcon#end of sib2, iclass 15, count 2 2006.257.19:54:06.95#ibcon#*after write, iclass 15, count 2 2006.257.19:54:06.95#ibcon#*before return 0, iclass 15, count 2 2006.257.19:54:06.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:54:06.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.19:54:06.95#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.19:54:06.95#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:06.95#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:54:07.07#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:54:07.07#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:54:07.07#ibcon#enter wrdev, iclass 15, count 0 2006.257.19:54:07.07#ibcon#first serial, iclass 15, count 0 2006.257.19:54:07.07#ibcon#enter sib2, iclass 15, count 0 2006.257.19:54:07.07#ibcon#flushed, iclass 15, count 0 2006.257.19:54:07.07#ibcon#about to write, iclass 15, count 0 2006.257.19:54:07.07#ibcon#wrote, iclass 15, count 0 2006.257.19:54:07.07#ibcon#about to read 3, iclass 15, count 0 2006.257.19:54:07.09#ibcon#read 3, iclass 15, count 0 2006.257.19:54:07.09#ibcon#about to read 4, iclass 15, count 0 2006.257.19:54:07.09#ibcon#read 4, iclass 15, count 0 2006.257.19:54:07.09#ibcon#about to read 5, iclass 15, count 0 2006.257.19:54:07.09#ibcon#read 5, iclass 15, count 0 2006.257.19:54:07.09#ibcon#about to read 6, iclass 15, count 0 2006.257.19:54:07.09#ibcon#read 6, iclass 15, count 0 2006.257.19:54:07.09#ibcon#end of sib2, iclass 15, count 0 2006.257.19:54:07.09#ibcon#*mode == 0, iclass 15, count 0 2006.257.19:54:07.09#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.19:54:07.09#ibcon#[25=USB\r\n] 2006.257.19:54:07.09#ibcon#*before write, iclass 15, count 0 2006.257.19:54:07.09#ibcon#enter sib2, iclass 15, count 0 2006.257.19:54:07.09#ibcon#flushed, iclass 15, count 0 2006.257.19:54:07.09#ibcon#about to write, iclass 15, count 0 2006.257.19:54:07.09#ibcon#wrote, iclass 15, count 0 2006.257.19:54:07.09#ibcon#about to read 3, iclass 15, count 0 2006.257.19:54:07.12#ibcon#read 3, iclass 15, count 0 2006.257.19:54:07.12#ibcon#about to read 4, iclass 15, count 0 2006.257.19:54:07.12#ibcon#read 4, iclass 15, count 0 2006.257.19:54:07.12#ibcon#about to read 5, iclass 15, count 0 2006.257.19:54:07.12#ibcon#read 5, iclass 15, count 0 2006.257.19:54:07.12#ibcon#about to read 6, iclass 15, count 0 2006.257.19:54:07.12#ibcon#read 6, iclass 15, count 0 2006.257.19:54:07.12#ibcon#end of sib2, iclass 15, count 0 2006.257.19:54:07.12#ibcon#*after write, iclass 15, count 0 2006.257.19:54:07.12#ibcon#*before return 0, iclass 15, count 0 2006.257.19:54:07.12#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:54:07.12#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.19:54:07.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.19:54:07.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.19:54:07.12$vck44/valo=3,564.99 2006.257.19:54:07.12#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.19:54:07.12#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.19:54:07.12#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:07.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:07.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:07.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:07.12#ibcon#enter wrdev, iclass 17, count 0 2006.257.19:54:07.12#ibcon#first serial, iclass 17, count 0 2006.257.19:54:07.12#ibcon#enter sib2, iclass 17, count 0 2006.257.19:54:07.12#ibcon#flushed, iclass 17, count 0 2006.257.19:54:07.12#ibcon#about to write, iclass 17, count 0 2006.257.19:54:07.12#ibcon#wrote, iclass 17, count 0 2006.257.19:54:07.12#ibcon#about to read 3, iclass 17, count 0 2006.257.19:54:07.14#ibcon#read 3, iclass 17, count 0 2006.257.19:54:07.14#ibcon#about to read 4, iclass 17, count 0 2006.257.19:54:07.14#ibcon#read 4, iclass 17, count 0 2006.257.19:54:07.14#ibcon#about to read 5, iclass 17, count 0 2006.257.19:54:07.14#ibcon#read 5, iclass 17, count 0 2006.257.19:54:07.14#ibcon#about to read 6, iclass 17, count 0 2006.257.19:54:07.14#ibcon#read 6, iclass 17, count 0 2006.257.19:54:07.14#ibcon#end of sib2, iclass 17, count 0 2006.257.19:54:07.14#ibcon#*mode == 0, iclass 17, count 0 2006.257.19:54:07.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.19:54:07.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.19:54:07.14#ibcon#*before write, iclass 17, count 0 2006.257.19:54:07.14#ibcon#enter sib2, iclass 17, count 0 2006.257.19:54:07.14#ibcon#flushed, iclass 17, count 0 2006.257.19:54:07.14#ibcon#about to write, iclass 17, count 0 2006.257.19:54:07.14#ibcon#wrote, iclass 17, count 0 2006.257.19:54:07.14#ibcon#about to read 3, iclass 17, count 0 2006.257.19:54:07.18#ibcon#read 3, iclass 17, count 0 2006.257.19:54:07.18#ibcon#about to read 4, iclass 17, count 0 2006.257.19:54:07.18#ibcon#read 4, iclass 17, count 0 2006.257.19:54:07.18#ibcon#about to read 5, iclass 17, count 0 2006.257.19:54:07.18#ibcon#read 5, iclass 17, count 0 2006.257.19:54:07.18#ibcon#about to read 6, iclass 17, count 0 2006.257.19:54:07.18#ibcon#read 6, iclass 17, count 0 2006.257.19:54:07.18#ibcon#end of sib2, iclass 17, count 0 2006.257.19:54:07.18#ibcon#*after write, iclass 17, count 0 2006.257.19:54:07.18#ibcon#*before return 0, iclass 17, count 0 2006.257.19:54:07.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:07.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:07.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.19:54:07.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.19:54:07.18$vck44/va=3,8 2006.257.19:54:07.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.19:54:07.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.19:54:07.18#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:07.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:07.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:07.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:07.24#ibcon#enter wrdev, iclass 19, count 2 2006.257.19:54:07.24#ibcon#first serial, iclass 19, count 2 2006.257.19:54:07.24#ibcon#enter sib2, iclass 19, count 2 2006.257.19:54:07.24#ibcon#flushed, iclass 19, count 2 2006.257.19:54:07.24#ibcon#about to write, iclass 19, count 2 2006.257.19:54:07.24#ibcon#wrote, iclass 19, count 2 2006.257.19:54:07.24#ibcon#about to read 3, iclass 19, count 2 2006.257.19:54:07.26#ibcon#read 3, iclass 19, count 2 2006.257.19:54:07.26#ibcon#about to read 4, iclass 19, count 2 2006.257.19:54:07.26#ibcon#read 4, iclass 19, count 2 2006.257.19:54:07.26#ibcon#about to read 5, iclass 19, count 2 2006.257.19:54:07.26#ibcon#read 5, iclass 19, count 2 2006.257.19:54:07.26#ibcon#about to read 6, iclass 19, count 2 2006.257.19:54:07.26#ibcon#read 6, iclass 19, count 2 2006.257.19:54:07.26#ibcon#end of sib2, iclass 19, count 2 2006.257.19:54:07.26#ibcon#*mode == 0, iclass 19, count 2 2006.257.19:54:07.26#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.19:54:07.26#ibcon#[25=AT03-08\r\n] 2006.257.19:54:07.26#ibcon#*before write, iclass 19, count 2 2006.257.19:54:07.26#ibcon#enter sib2, iclass 19, count 2 2006.257.19:54:07.26#ibcon#flushed, iclass 19, count 2 2006.257.19:54:07.26#ibcon#about to write, iclass 19, count 2 2006.257.19:54:07.26#ibcon#wrote, iclass 19, count 2 2006.257.19:54:07.26#ibcon#about to read 3, iclass 19, count 2 2006.257.19:54:07.29#ibcon#read 3, iclass 19, count 2 2006.257.19:54:07.29#ibcon#about to read 4, iclass 19, count 2 2006.257.19:54:07.29#ibcon#read 4, iclass 19, count 2 2006.257.19:54:07.29#ibcon#about to read 5, iclass 19, count 2 2006.257.19:54:07.29#ibcon#read 5, iclass 19, count 2 2006.257.19:54:07.29#ibcon#about to read 6, iclass 19, count 2 2006.257.19:54:07.29#ibcon#read 6, iclass 19, count 2 2006.257.19:54:07.29#ibcon#end of sib2, iclass 19, count 2 2006.257.19:54:07.29#ibcon#*after write, iclass 19, count 2 2006.257.19:54:07.29#ibcon#*before return 0, iclass 19, count 2 2006.257.19:54:07.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:07.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:07.29#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.19:54:07.29#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:07.29#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:07.41#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:07.41#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:07.41#ibcon#enter wrdev, iclass 19, count 0 2006.257.19:54:07.41#ibcon#first serial, iclass 19, count 0 2006.257.19:54:07.41#ibcon#enter sib2, iclass 19, count 0 2006.257.19:54:07.41#ibcon#flushed, iclass 19, count 0 2006.257.19:54:07.41#ibcon#about to write, iclass 19, count 0 2006.257.19:54:07.41#ibcon#wrote, iclass 19, count 0 2006.257.19:54:07.41#ibcon#about to read 3, iclass 19, count 0 2006.257.19:54:07.43#ibcon#read 3, iclass 19, count 0 2006.257.19:54:07.43#ibcon#about to read 4, iclass 19, count 0 2006.257.19:54:07.43#ibcon#read 4, iclass 19, count 0 2006.257.19:54:07.43#ibcon#about to read 5, iclass 19, count 0 2006.257.19:54:07.43#ibcon#read 5, iclass 19, count 0 2006.257.19:54:07.43#ibcon#about to read 6, iclass 19, count 0 2006.257.19:54:07.43#ibcon#read 6, iclass 19, count 0 2006.257.19:54:07.43#ibcon#end of sib2, iclass 19, count 0 2006.257.19:54:07.43#ibcon#*mode == 0, iclass 19, count 0 2006.257.19:54:07.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.19:54:07.43#ibcon#[25=USB\r\n] 2006.257.19:54:07.43#ibcon#*before write, iclass 19, count 0 2006.257.19:54:07.43#ibcon#enter sib2, iclass 19, count 0 2006.257.19:54:07.43#ibcon#flushed, iclass 19, count 0 2006.257.19:54:07.43#ibcon#about to write, iclass 19, count 0 2006.257.19:54:07.43#ibcon#wrote, iclass 19, count 0 2006.257.19:54:07.43#ibcon#about to read 3, iclass 19, count 0 2006.257.19:54:07.46#ibcon#read 3, iclass 19, count 0 2006.257.19:54:07.46#ibcon#about to read 4, iclass 19, count 0 2006.257.19:54:07.46#ibcon#read 4, iclass 19, count 0 2006.257.19:54:07.46#ibcon#about to read 5, iclass 19, count 0 2006.257.19:54:07.46#ibcon#read 5, iclass 19, count 0 2006.257.19:54:07.46#ibcon#about to read 6, iclass 19, count 0 2006.257.19:54:07.46#ibcon#read 6, iclass 19, count 0 2006.257.19:54:07.46#ibcon#end of sib2, iclass 19, count 0 2006.257.19:54:07.46#ibcon#*after write, iclass 19, count 0 2006.257.19:54:07.46#ibcon#*before return 0, iclass 19, count 0 2006.257.19:54:07.46#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:07.46#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:07.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.19:54:07.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.19:54:07.46$vck44/valo=4,624.99 2006.257.19:54:07.46#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.19:54:07.46#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.19:54:07.46#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:07.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:07.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:07.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:07.46#ibcon#enter wrdev, iclass 21, count 0 2006.257.19:54:07.46#ibcon#first serial, iclass 21, count 0 2006.257.19:54:07.46#ibcon#enter sib2, iclass 21, count 0 2006.257.19:54:07.46#ibcon#flushed, iclass 21, count 0 2006.257.19:54:07.46#ibcon#about to write, iclass 21, count 0 2006.257.19:54:07.46#ibcon#wrote, iclass 21, count 0 2006.257.19:54:07.46#ibcon#about to read 3, iclass 21, count 0 2006.257.19:54:07.48#ibcon#read 3, iclass 21, count 0 2006.257.19:54:07.48#ibcon#about to read 4, iclass 21, count 0 2006.257.19:54:07.48#ibcon#read 4, iclass 21, count 0 2006.257.19:54:07.48#ibcon#about to read 5, iclass 21, count 0 2006.257.19:54:07.48#ibcon#read 5, iclass 21, count 0 2006.257.19:54:07.48#ibcon#about to read 6, iclass 21, count 0 2006.257.19:54:07.48#ibcon#read 6, iclass 21, count 0 2006.257.19:54:07.48#ibcon#end of sib2, iclass 21, count 0 2006.257.19:54:07.48#ibcon#*mode == 0, iclass 21, count 0 2006.257.19:54:07.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.19:54:07.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.19:54:07.48#ibcon#*before write, iclass 21, count 0 2006.257.19:54:07.48#ibcon#enter sib2, iclass 21, count 0 2006.257.19:54:07.48#ibcon#flushed, iclass 21, count 0 2006.257.19:54:07.48#ibcon#about to write, iclass 21, count 0 2006.257.19:54:07.48#ibcon#wrote, iclass 21, count 0 2006.257.19:54:07.48#ibcon#about to read 3, iclass 21, count 0 2006.257.19:54:07.52#ibcon#read 3, iclass 21, count 0 2006.257.19:54:07.52#ibcon#about to read 4, iclass 21, count 0 2006.257.19:54:07.52#ibcon#read 4, iclass 21, count 0 2006.257.19:54:07.52#ibcon#about to read 5, iclass 21, count 0 2006.257.19:54:07.52#ibcon#read 5, iclass 21, count 0 2006.257.19:54:07.52#ibcon#about to read 6, iclass 21, count 0 2006.257.19:54:07.52#ibcon#read 6, iclass 21, count 0 2006.257.19:54:07.52#ibcon#end of sib2, iclass 21, count 0 2006.257.19:54:07.52#ibcon#*after write, iclass 21, count 0 2006.257.19:54:07.52#ibcon#*before return 0, iclass 21, count 0 2006.257.19:54:07.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:07.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:07.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.19:54:07.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.19:54:07.52$vck44/va=4,7 2006.257.19:54:07.52#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.19:54:07.52#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.19:54:07.52#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:07.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:07.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:07.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:07.58#ibcon#enter wrdev, iclass 23, count 2 2006.257.19:54:07.58#ibcon#first serial, iclass 23, count 2 2006.257.19:54:07.58#ibcon#enter sib2, iclass 23, count 2 2006.257.19:54:07.58#ibcon#flushed, iclass 23, count 2 2006.257.19:54:07.58#ibcon#about to write, iclass 23, count 2 2006.257.19:54:07.58#ibcon#wrote, iclass 23, count 2 2006.257.19:54:07.58#ibcon#about to read 3, iclass 23, count 2 2006.257.19:54:07.60#ibcon#read 3, iclass 23, count 2 2006.257.19:54:07.60#ibcon#about to read 4, iclass 23, count 2 2006.257.19:54:07.60#ibcon#read 4, iclass 23, count 2 2006.257.19:54:07.60#ibcon#about to read 5, iclass 23, count 2 2006.257.19:54:07.60#ibcon#read 5, iclass 23, count 2 2006.257.19:54:07.60#ibcon#about to read 6, iclass 23, count 2 2006.257.19:54:07.60#ibcon#read 6, iclass 23, count 2 2006.257.19:54:07.60#ibcon#end of sib2, iclass 23, count 2 2006.257.19:54:07.60#ibcon#*mode == 0, iclass 23, count 2 2006.257.19:54:07.60#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.19:54:07.60#ibcon#[25=AT04-07\r\n] 2006.257.19:54:07.60#ibcon#*before write, iclass 23, count 2 2006.257.19:54:07.60#ibcon#enter sib2, iclass 23, count 2 2006.257.19:54:07.60#ibcon#flushed, iclass 23, count 2 2006.257.19:54:07.60#ibcon#about to write, iclass 23, count 2 2006.257.19:54:07.60#ibcon#wrote, iclass 23, count 2 2006.257.19:54:07.60#ibcon#about to read 3, iclass 23, count 2 2006.257.19:54:07.63#ibcon#read 3, iclass 23, count 2 2006.257.19:54:07.63#ibcon#about to read 4, iclass 23, count 2 2006.257.19:54:07.63#ibcon#read 4, iclass 23, count 2 2006.257.19:54:07.63#ibcon#about to read 5, iclass 23, count 2 2006.257.19:54:07.63#ibcon#read 5, iclass 23, count 2 2006.257.19:54:07.63#ibcon#about to read 6, iclass 23, count 2 2006.257.19:54:07.63#ibcon#read 6, iclass 23, count 2 2006.257.19:54:07.63#ibcon#end of sib2, iclass 23, count 2 2006.257.19:54:07.63#ibcon#*after write, iclass 23, count 2 2006.257.19:54:07.63#ibcon#*before return 0, iclass 23, count 2 2006.257.19:54:07.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:07.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:07.63#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.19:54:07.63#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:07.63#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:07.75#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:07.75#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:07.75#ibcon#enter wrdev, iclass 23, count 0 2006.257.19:54:07.75#ibcon#first serial, iclass 23, count 0 2006.257.19:54:07.75#ibcon#enter sib2, iclass 23, count 0 2006.257.19:54:07.75#ibcon#flushed, iclass 23, count 0 2006.257.19:54:07.75#ibcon#about to write, iclass 23, count 0 2006.257.19:54:07.75#ibcon#wrote, iclass 23, count 0 2006.257.19:54:07.75#ibcon#about to read 3, iclass 23, count 0 2006.257.19:54:07.77#ibcon#read 3, iclass 23, count 0 2006.257.19:54:07.77#ibcon#about to read 4, iclass 23, count 0 2006.257.19:54:07.77#ibcon#read 4, iclass 23, count 0 2006.257.19:54:07.77#ibcon#about to read 5, iclass 23, count 0 2006.257.19:54:07.77#ibcon#read 5, iclass 23, count 0 2006.257.19:54:07.77#ibcon#about to read 6, iclass 23, count 0 2006.257.19:54:07.77#ibcon#read 6, iclass 23, count 0 2006.257.19:54:07.77#ibcon#end of sib2, iclass 23, count 0 2006.257.19:54:07.77#ibcon#*mode == 0, iclass 23, count 0 2006.257.19:54:07.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.19:54:07.77#ibcon#[25=USB\r\n] 2006.257.19:54:07.77#ibcon#*before write, iclass 23, count 0 2006.257.19:54:07.77#ibcon#enter sib2, iclass 23, count 0 2006.257.19:54:07.77#ibcon#flushed, iclass 23, count 0 2006.257.19:54:07.77#ibcon#about to write, iclass 23, count 0 2006.257.19:54:07.77#ibcon#wrote, iclass 23, count 0 2006.257.19:54:07.77#ibcon#about to read 3, iclass 23, count 0 2006.257.19:54:07.80#ibcon#read 3, iclass 23, count 0 2006.257.19:54:07.80#ibcon#about to read 4, iclass 23, count 0 2006.257.19:54:07.80#ibcon#read 4, iclass 23, count 0 2006.257.19:54:07.80#ibcon#about to read 5, iclass 23, count 0 2006.257.19:54:07.80#ibcon#read 5, iclass 23, count 0 2006.257.19:54:07.80#ibcon#about to read 6, iclass 23, count 0 2006.257.19:54:07.80#ibcon#read 6, iclass 23, count 0 2006.257.19:54:07.80#ibcon#end of sib2, iclass 23, count 0 2006.257.19:54:07.80#ibcon#*after write, iclass 23, count 0 2006.257.19:54:07.80#ibcon#*before return 0, iclass 23, count 0 2006.257.19:54:07.80#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:07.80#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:07.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.19:54:07.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.19:54:07.80$vck44/valo=5,734.99 2006.257.19:54:07.80#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.19:54:07.80#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.19:54:07.80#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:07.80#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:07.80#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:07.80#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:07.80#ibcon#enter wrdev, iclass 25, count 0 2006.257.19:54:07.80#ibcon#first serial, iclass 25, count 0 2006.257.19:54:07.80#ibcon#enter sib2, iclass 25, count 0 2006.257.19:54:07.80#ibcon#flushed, iclass 25, count 0 2006.257.19:54:07.80#ibcon#about to write, iclass 25, count 0 2006.257.19:54:07.80#ibcon#wrote, iclass 25, count 0 2006.257.19:54:07.80#ibcon#about to read 3, iclass 25, count 0 2006.257.19:54:07.82#ibcon#read 3, iclass 25, count 0 2006.257.19:54:07.82#ibcon#about to read 4, iclass 25, count 0 2006.257.19:54:07.82#ibcon#read 4, iclass 25, count 0 2006.257.19:54:07.82#ibcon#about to read 5, iclass 25, count 0 2006.257.19:54:07.82#ibcon#read 5, iclass 25, count 0 2006.257.19:54:07.82#ibcon#about to read 6, iclass 25, count 0 2006.257.19:54:07.82#ibcon#read 6, iclass 25, count 0 2006.257.19:54:07.82#ibcon#end of sib2, iclass 25, count 0 2006.257.19:54:07.82#ibcon#*mode == 0, iclass 25, count 0 2006.257.19:54:07.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.19:54:07.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.19:54:07.82#ibcon#*before write, iclass 25, count 0 2006.257.19:54:07.82#ibcon#enter sib2, iclass 25, count 0 2006.257.19:54:07.82#ibcon#flushed, iclass 25, count 0 2006.257.19:54:07.82#ibcon#about to write, iclass 25, count 0 2006.257.19:54:07.82#ibcon#wrote, iclass 25, count 0 2006.257.19:54:07.82#ibcon#about to read 3, iclass 25, count 0 2006.257.19:54:07.86#ibcon#read 3, iclass 25, count 0 2006.257.19:54:07.86#ibcon#about to read 4, iclass 25, count 0 2006.257.19:54:07.86#ibcon#read 4, iclass 25, count 0 2006.257.19:54:07.86#ibcon#about to read 5, iclass 25, count 0 2006.257.19:54:07.86#ibcon#read 5, iclass 25, count 0 2006.257.19:54:07.86#ibcon#about to read 6, iclass 25, count 0 2006.257.19:54:07.86#ibcon#read 6, iclass 25, count 0 2006.257.19:54:07.86#ibcon#end of sib2, iclass 25, count 0 2006.257.19:54:07.86#ibcon#*after write, iclass 25, count 0 2006.257.19:54:07.86#ibcon#*before return 0, iclass 25, count 0 2006.257.19:54:07.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:07.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:07.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.19:54:07.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.19:54:07.86$vck44/va=5,4 2006.257.19:54:07.86#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.19:54:07.86#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.19:54:07.86#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:07.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:07.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:07.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:07.92#ibcon#enter wrdev, iclass 27, count 2 2006.257.19:54:07.92#ibcon#first serial, iclass 27, count 2 2006.257.19:54:07.92#ibcon#enter sib2, iclass 27, count 2 2006.257.19:54:07.92#ibcon#flushed, iclass 27, count 2 2006.257.19:54:07.92#ibcon#about to write, iclass 27, count 2 2006.257.19:54:07.92#ibcon#wrote, iclass 27, count 2 2006.257.19:54:07.92#ibcon#about to read 3, iclass 27, count 2 2006.257.19:54:07.94#ibcon#read 3, iclass 27, count 2 2006.257.19:54:07.94#ibcon#about to read 4, iclass 27, count 2 2006.257.19:54:07.94#ibcon#read 4, iclass 27, count 2 2006.257.19:54:07.94#ibcon#about to read 5, iclass 27, count 2 2006.257.19:54:07.94#ibcon#read 5, iclass 27, count 2 2006.257.19:54:07.94#ibcon#about to read 6, iclass 27, count 2 2006.257.19:54:07.94#ibcon#read 6, iclass 27, count 2 2006.257.19:54:07.94#ibcon#end of sib2, iclass 27, count 2 2006.257.19:54:07.94#ibcon#*mode == 0, iclass 27, count 2 2006.257.19:54:07.94#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.19:54:07.94#ibcon#[25=AT05-04\r\n] 2006.257.19:54:07.94#ibcon#*before write, iclass 27, count 2 2006.257.19:54:07.94#ibcon#enter sib2, iclass 27, count 2 2006.257.19:54:07.94#ibcon#flushed, iclass 27, count 2 2006.257.19:54:07.94#ibcon#about to write, iclass 27, count 2 2006.257.19:54:07.94#ibcon#wrote, iclass 27, count 2 2006.257.19:54:07.94#ibcon#about to read 3, iclass 27, count 2 2006.257.19:54:07.97#ibcon#read 3, iclass 27, count 2 2006.257.19:54:07.97#ibcon#about to read 4, iclass 27, count 2 2006.257.19:54:07.97#ibcon#read 4, iclass 27, count 2 2006.257.19:54:07.97#ibcon#about to read 5, iclass 27, count 2 2006.257.19:54:07.97#ibcon#read 5, iclass 27, count 2 2006.257.19:54:07.97#ibcon#about to read 6, iclass 27, count 2 2006.257.19:54:07.97#ibcon#read 6, iclass 27, count 2 2006.257.19:54:07.97#ibcon#end of sib2, iclass 27, count 2 2006.257.19:54:07.97#ibcon#*after write, iclass 27, count 2 2006.257.19:54:07.97#ibcon#*before return 0, iclass 27, count 2 2006.257.19:54:07.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:07.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:07.97#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.19:54:07.97#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:07.97#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:08.09#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:08.09#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:08.09#ibcon#enter wrdev, iclass 27, count 0 2006.257.19:54:08.09#ibcon#first serial, iclass 27, count 0 2006.257.19:54:08.09#ibcon#enter sib2, iclass 27, count 0 2006.257.19:54:08.09#ibcon#flushed, iclass 27, count 0 2006.257.19:54:08.09#ibcon#about to write, iclass 27, count 0 2006.257.19:54:08.09#ibcon#wrote, iclass 27, count 0 2006.257.19:54:08.09#ibcon#about to read 3, iclass 27, count 0 2006.257.19:54:08.11#ibcon#read 3, iclass 27, count 0 2006.257.19:54:08.11#ibcon#about to read 4, iclass 27, count 0 2006.257.19:54:08.11#ibcon#read 4, iclass 27, count 0 2006.257.19:54:08.11#ibcon#about to read 5, iclass 27, count 0 2006.257.19:54:08.11#ibcon#read 5, iclass 27, count 0 2006.257.19:54:08.11#ibcon#about to read 6, iclass 27, count 0 2006.257.19:54:08.11#ibcon#read 6, iclass 27, count 0 2006.257.19:54:08.11#ibcon#end of sib2, iclass 27, count 0 2006.257.19:54:08.11#ibcon#*mode == 0, iclass 27, count 0 2006.257.19:54:08.11#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.19:54:08.11#ibcon#[25=USB\r\n] 2006.257.19:54:08.11#ibcon#*before write, iclass 27, count 0 2006.257.19:54:08.11#ibcon#enter sib2, iclass 27, count 0 2006.257.19:54:08.11#ibcon#flushed, iclass 27, count 0 2006.257.19:54:08.11#ibcon#about to write, iclass 27, count 0 2006.257.19:54:08.11#ibcon#wrote, iclass 27, count 0 2006.257.19:54:08.11#ibcon#about to read 3, iclass 27, count 0 2006.257.19:54:08.14#ibcon#read 3, iclass 27, count 0 2006.257.19:54:08.14#ibcon#about to read 4, iclass 27, count 0 2006.257.19:54:08.14#ibcon#read 4, iclass 27, count 0 2006.257.19:54:08.14#ibcon#about to read 5, iclass 27, count 0 2006.257.19:54:08.14#ibcon#read 5, iclass 27, count 0 2006.257.19:54:08.14#ibcon#about to read 6, iclass 27, count 0 2006.257.19:54:08.14#ibcon#read 6, iclass 27, count 0 2006.257.19:54:08.14#ibcon#end of sib2, iclass 27, count 0 2006.257.19:54:08.14#ibcon#*after write, iclass 27, count 0 2006.257.19:54:08.14#ibcon#*before return 0, iclass 27, count 0 2006.257.19:54:08.14#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:08.14#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:08.14#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.19:54:08.14#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.19:54:08.14$vck44/valo=6,814.99 2006.257.19:54:08.14#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.19:54:08.14#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.19:54:08.14#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:08.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:08.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:08.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:08.14#ibcon#enter wrdev, iclass 29, count 0 2006.257.19:54:08.14#ibcon#first serial, iclass 29, count 0 2006.257.19:54:08.14#ibcon#enter sib2, iclass 29, count 0 2006.257.19:54:08.14#ibcon#flushed, iclass 29, count 0 2006.257.19:54:08.14#ibcon#about to write, iclass 29, count 0 2006.257.19:54:08.14#ibcon#wrote, iclass 29, count 0 2006.257.19:54:08.14#ibcon#about to read 3, iclass 29, count 0 2006.257.19:54:08.16#ibcon#read 3, iclass 29, count 0 2006.257.19:54:08.16#ibcon#about to read 4, iclass 29, count 0 2006.257.19:54:08.16#ibcon#read 4, iclass 29, count 0 2006.257.19:54:08.16#ibcon#about to read 5, iclass 29, count 0 2006.257.19:54:08.16#ibcon#read 5, iclass 29, count 0 2006.257.19:54:08.16#ibcon#about to read 6, iclass 29, count 0 2006.257.19:54:08.16#ibcon#read 6, iclass 29, count 0 2006.257.19:54:08.16#ibcon#end of sib2, iclass 29, count 0 2006.257.19:54:08.16#ibcon#*mode == 0, iclass 29, count 0 2006.257.19:54:08.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.19:54:08.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.19:54:08.16#ibcon#*before write, iclass 29, count 0 2006.257.19:54:08.16#ibcon#enter sib2, iclass 29, count 0 2006.257.19:54:08.16#ibcon#flushed, iclass 29, count 0 2006.257.19:54:08.16#ibcon#about to write, iclass 29, count 0 2006.257.19:54:08.16#ibcon#wrote, iclass 29, count 0 2006.257.19:54:08.16#ibcon#about to read 3, iclass 29, count 0 2006.257.19:54:08.20#ibcon#read 3, iclass 29, count 0 2006.257.19:54:08.20#ibcon#about to read 4, iclass 29, count 0 2006.257.19:54:08.20#ibcon#read 4, iclass 29, count 0 2006.257.19:54:08.20#ibcon#about to read 5, iclass 29, count 0 2006.257.19:54:08.20#ibcon#read 5, iclass 29, count 0 2006.257.19:54:08.20#ibcon#about to read 6, iclass 29, count 0 2006.257.19:54:08.20#ibcon#read 6, iclass 29, count 0 2006.257.19:54:08.20#ibcon#end of sib2, iclass 29, count 0 2006.257.19:54:08.20#ibcon#*after write, iclass 29, count 0 2006.257.19:54:08.20#ibcon#*before return 0, iclass 29, count 0 2006.257.19:54:08.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:08.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:08.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.19:54:08.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.19:54:08.20$vck44/va=6,4 2006.257.19:54:08.20#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.19:54:08.20#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.19:54:08.20#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:08.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:08.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:08.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:08.26#ibcon#enter wrdev, iclass 31, count 2 2006.257.19:54:08.26#ibcon#first serial, iclass 31, count 2 2006.257.19:54:08.26#ibcon#enter sib2, iclass 31, count 2 2006.257.19:54:08.26#ibcon#flushed, iclass 31, count 2 2006.257.19:54:08.26#ibcon#about to write, iclass 31, count 2 2006.257.19:54:08.26#ibcon#wrote, iclass 31, count 2 2006.257.19:54:08.26#ibcon#about to read 3, iclass 31, count 2 2006.257.19:54:08.28#ibcon#read 3, iclass 31, count 2 2006.257.19:54:08.28#ibcon#about to read 4, iclass 31, count 2 2006.257.19:54:08.28#ibcon#read 4, iclass 31, count 2 2006.257.19:54:08.28#ibcon#about to read 5, iclass 31, count 2 2006.257.19:54:08.28#ibcon#read 5, iclass 31, count 2 2006.257.19:54:08.28#ibcon#about to read 6, iclass 31, count 2 2006.257.19:54:08.28#ibcon#read 6, iclass 31, count 2 2006.257.19:54:08.28#ibcon#end of sib2, iclass 31, count 2 2006.257.19:54:08.28#ibcon#*mode == 0, iclass 31, count 2 2006.257.19:54:08.28#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.19:54:08.28#ibcon#[25=AT06-04\r\n] 2006.257.19:54:08.28#ibcon#*before write, iclass 31, count 2 2006.257.19:54:08.28#ibcon#enter sib2, iclass 31, count 2 2006.257.19:54:08.28#ibcon#flushed, iclass 31, count 2 2006.257.19:54:08.28#ibcon#about to write, iclass 31, count 2 2006.257.19:54:08.28#ibcon#wrote, iclass 31, count 2 2006.257.19:54:08.28#ibcon#about to read 3, iclass 31, count 2 2006.257.19:54:08.31#ibcon#read 3, iclass 31, count 2 2006.257.19:54:08.31#ibcon#about to read 4, iclass 31, count 2 2006.257.19:54:08.31#ibcon#read 4, iclass 31, count 2 2006.257.19:54:08.31#ibcon#about to read 5, iclass 31, count 2 2006.257.19:54:08.31#ibcon#read 5, iclass 31, count 2 2006.257.19:54:08.31#ibcon#about to read 6, iclass 31, count 2 2006.257.19:54:08.31#ibcon#read 6, iclass 31, count 2 2006.257.19:54:08.31#ibcon#end of sib2, iclass 31, count 2 2006.257.19:54:08.31#ibcon#*after write, iclass 31, count 2 2006.257.19:54:08.31#ibcon#*before return 0, iclass 31, count 2 2006.257.19:54:08.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:08.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:08.31#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.19:54:08.31#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:08.31#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:08.43#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:08.43#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:08.43#ibcon#enter wrdev, iclass 31, count 0 2006.257.19:54:08.43#ibcon#first serial, iclass 31, count 0 2006.257.19:54:08.43#ibcon#enter sib2, iclass 31, count 0 2006.257.19:54:08.43#ibcon#flushed, iclass 31, count 0 2006.257.19:54:08.43#ibcon#about to write, iclass 31, count 0 2006.257.19:54:08.43#ibcon#wrote, iclass 31, count 0 2006.257.19:54:08.43#ibcon#about to read 3, iclass 31, count 0 2006.257.19:54:08.45#ibcon#read 3, iclass 31, count 0 2006.257.19:54:08.45#ibcon#about to read 4, iclass 31, count 0 2006.257.19:54:08.45#ibcon#read 4, iclass 31, count 0 2006.257.19:54:08.45#ibcon#about to read 5, iclass 31, count 0 2006.257.19:54:08.45#ibcon#read 5, iclass 31, count 0 2006.257.19:54:08.45#ibcon#about to read 6, iclass 31, count 0 2006.257.19:54:08.45#ibcon#read 6, iclass 31, count 0 2006.257.19:54:08.45#ibcon#end of sib2, iclass 31, count 0 2006.257.19:54:08.45#ibcon#*mode == 0, iclass 31, count 0 2006.257.19:54:08.45#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.19:54:08.45#ibcon#[25=USB\r\n] 2006.257.19:54:08.45#ibcon#*before write, iclass 31, count 0 2006.257.19:54:08.45#ibcon#enter sib2, iclass 31, count 0 2006.257.19:54:08.45#ibcon#flushed, iclass 31, count 0 2006.257.19:54:08.45#ibcon#about to write, iclass 31, count 0 2006.257.19:54:08.45#ibcon#wrote, iclass 31, count 0 2006.257.19:54:08.45#ibcon#about to read 3, iclass 31, count 0 2006.257.19:54:08.48#ibcon#read 3, iclass 31, count 0 2006.257.19:54:08.48#ibcon#about to read 4, iclass 31, count 0 2006.257.19:54:08.48#ibcon#read 4, iclass 31, count 0 2006.257.19:54:08.48#ibcon#about to read 5, iclass 31, count 0 2006.257.19:54:08.48#ibcon#read 5, iclass 31, count 0 2006.257.19:54:08.48#ibcon#about to read 6, iclass 31, count 0 2006.257.19:54:08.48#ibcon#read 6, iclass 31, count 0 2006.257.19:54:08.48#ibcon#end of sib2, iclass 31, count 0 2006.257.19:54:08.48#ibcon#*after write, iclass 31, count 0 2006.257.19:54:08.48#ibcon#*before return 0, iclass 31, count 0 2006.257.19:54:08.48#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:08.48#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:08.48#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.19:54:08.48#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.19:54:08.48$vck44/valo=7,864.99 2006.257.19:54:08.48#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.19:54:08.48#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.19:54:08.48#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:08.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:08.48#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:08.48#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:08.48#ibcon#enter wrdev, iclass 33, count 0 2006.257.19:54:08.48#ibcon#first serial, iclass 33, count 0 2006.257.19:54:08.48#ibcon#enter sib2, iclass 33, count 0 2006.257.19:54:08.48#ibcon#flushed, iclass 33, count 0 2006.257.19:54:08.48#ibcon#about to write, iclass 33, count 0 2006.257.19:54:08.48#ibcon#wrote, iclass 33, count 0 2006.257.19:54:08.48#ibcon#about to read 3, iclass 33, count 0 2006.257.19:54:08.50#ibcon#read 3, iclass 33, count 0 2006.257.19:54:08.50#ibcon#about to read 4, iclass 33, count 0 2006.257.19:54:08.50#ibcon#read 4, iclass 33, count 0 2006.257.19:54:08.50#ibcon#about to read 5, iclass 33, count 0 2006.257.19:54:08.50#ibcon#read 5, iclass 33, count 0 2006.257.19:54:08.50#ibcon#about to read 6, iclass 33, count 0 2006.257.19:54:08.50#ibcon#read 6, iclass 33, count 0 2006.257.19:54:08.50#ibcon#end of sib2, iclass 33, count 0 2006.257.19:54:08.50#ibcon#*mode == 0, iclass 33, count 0 2006.257.19:54:08.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.19:54:08.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.19:54:08.50#ibcon#*before write, iclass 33, count 0 2006.257.19:54:08.50#ibcon#enter sib2, iclass 33, count 0 2006.257.19:54:08.50#ibcon#flushed, iclass 33, count 0 2006.257.19:54:08.50#ibcon#about to write, iclass 33, count 0 2006.257.19:54:08.50#ibcon#wrote, iclass 33, count 0 2006.257.19:54:08.50#ibcon#about to read 3, iclass 33, count 0 2006.257.19:54:08.54#ibcon#read 3, iclass 33, count 0 2006.257.19:54:08.54#ibcon#about to read 4, iclass 33, count 0 2006.257.19:54:08.54#ibcon#read 4, iclass 33, count 0 2006.257.19:54:08.54#ibcon#about to read 5, iclass 33, count 0 2006.257.19:54:08.54#ibcon#read 5, iclass 33, count 0 2006.257.19:54:08.54#ibcon#about to read 6, iclass 33, count 0 2006.257.19:54:08.54#ibcon#read 6, iclass 33, count 0 2006.257.19:54:08.54#ibcon#end of sib2, iclass 33, count 0 2006.257.19:54:08.54#ibcon#*after write, iclass 33, count 0 2006.257.19:54:08.54#ibcon#*before return 0, iclass 33, count 0 2006.257.19:54:08.54#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:08.54#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:08.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.19:54:08.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.19:54:08.54$vck44/va=7,4 2006.257.19:54:08.54#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.19:54:08.54#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.19:54:08.54#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:08.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:08.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:08.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:08.60#ibcon#enter wrdev, iclass 35, count 2 2006.257.19:54:08.60#ibcon#first serial, iclass 35, count 2 2006.257.19:54:08.60#ibcon#enter sib2, iclass 35, count 2 2006.257.19:54:08.60#ibcon#flushed, iclass 35, count 2 2006.257.19:54:08.60#ibcon#about to write, iclass 35, count 2 2006.257.19:54:08.60#ibcon#wrote, iclass 35, count 2 2006.257.19:54:08.60#ibcon#about to read 3, iclass 35, count 2 2006.257.19:54:08.62#ibcon#read 3, iclass 35, count 2 2006.257.19:54:08.62#ibcon#about to read 4, iclass 35, count 2 2006.257.19:54:08.62#ibcon#read 4, iclass 35, count 2 2006.257.19:54:08.62#ibcon#about to read 5, iclass 35, count 2 2006.257.19:54:08.62#ibcon#read 5, iclass 35, count 2 2006.257.19:54:08.62#ibcon#about to read 6, iclass 35, count 2 2006.257.19:54:08.62#ibcon#read 6, iclass 35, count 2 2006.257.19:54:08.62#ibcon#end of sib2, iclass 35, count 2 2006.257.19:54:08.62#ibcon#*mode == 0, iclass 35, count 2 2006.257.19:54:08.62#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.19:54:08.62#ibcon#[25=AT07-04\r\n] 2006.257.19:54:08.62#ibcon#*before write, iclass 35, count 2 2006.257.19:54:08.62#ibcon#enter sib2, iclass 35, count 2 2006.257.19:54:08.62#ibcon#flushed, iclass 35, count 2 2006.257.19:54:08.62#ibcon#about to write, iclass 35, count 2 2006.257.19:54:08.62#ibcon#wrote, iclass 35, count 2 2006.257.19:54:08.62#ibcon#about to read 3, iclass 35, count 2 2006.257.19:54:08.65#ibcon#read 3, iclass 35, count 2 2006.257.19:54:08.65#ibcon#about to read 4, iclass 35, count 2 2006.257.19:54:08.65#ibcon#read 4, iclass 35, count 2 2006.257.19:54:08.65#ibcon#about to read 5, iclass 35, count 2 2006.257.19:54:08.65#ibcon#read 5, iclass 35, count 2 2006.257.19:54:08.65#ibcon#about to read 6, iclass 35, count 2 2006.257.19:54:08.65#ibcon#read 6, iclass 35, count 2 2006.257.19:54:08.65#ibcon#end of sib2, iclass 35, count 2 2006.257.19:54:08.65#ibcon#*after write, iclass 35, count 2 2006.257.19:54:08.65#ibcon#*before return 0, iclass 35, count 2 2006.257.19:54:08.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:08.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:08.65#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.19:54:08.65#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:08.65#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:08.77#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:08.77#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:08.77#ibcon#enter wrdev, iclass 35, count 0 2006.257.19:54:08.77#ibcon#first serial, iclass 35, count 0 2006.257.19:54:08.77#ibcon#enter sib2, iclass 35, count 0 2006.257.19:54:08.77#ibcon#flushed, iclass 35, count 0 2006.257.19:54:08.77#ibcon#about to write, iclass 35, count 0 2006.257.19:54:08.77#ibcon#wrote, iclass 35, count 0 2006.257.19:54:08.77#ibcon#about to read 3, iclass 35, count 0 2006.257.19:54:08.79#ibcon#read 3, iclass 35, count 0 2006.257.19:54:08.79#ibcon#about to read 4, iclass 35, count 0 2006.257.19:54:08.79#ibcon#read 4, iclass 35, count 0 2006.257.19:54:08.79#ibcon#about to read 5, iclass 35, count 0 2006.257.19:54:08.79#ibcon#read 5, iclass 35, count 0 2006.257.19:54:08.79#ibcon#about to read 6, iclass 35, count 0 2006.257.19:54:08.79#ibcon#read 6, iclass 35, count 0 2006.257.19:54:08.79#ibcon#end of sib2, iclass 35, count 0 2006.257.19:54:08.79#ibcon#*mode == 0, iclass 35, count 0 2006.257.19:54:08.79#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.19:54:08.79#ibcon#[25=USB\r\n] 2006.257.19:54:08.79#ibcon#*before write, iclass 35, count 0 2006.257.19:54:08.79#ibcon#enter sib2, iclass 35, count 0 2006.257.19:54:08.79#ibcon#flushed, iclass 35, count 0 2006.257.19:54:08.79#ibcon#about to write, iclass 35, count 0 2006.257.19:54:08.79#ibcon#wrote, iclass 35, count 0 2006.257.19:54:08.79#ibcon#about to read 3, iclass 35, count 0 2006.257.19:54:08.82#ibcon#read 3, iclass 35, count 0 2006.257.19:54:08.82#ibcon#about to read 4, iclass 35, count 0 2006.257.19:54:08.82#ibcon#read 4, iclass 35, count 0 2006.257.19:54:08.82#ibcon#about to read 5, iclass 35, count 0 2006.257.19:54:08.82#ibcon#read 5, iclass 35, count 0 2006.257.19:54:08.82#ibcon#about to read 6, iclass 35, count 0 2006.257.19:54:08.82#ibcon#read 6, iclass 35, count 0 2006.257.19:54:08.82#ibcon#end of sib2, iclass 35, count 0 2006.257.19:54:08.82#ibcon#*after write, iclass 35, count 0 2006.257.19:54:08.82#ibcon#*before return 0, iclass 35, count 0 2006.257.19:54:08.82#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:08.82#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:08.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.19:54:08.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.19:54:08.82$vck44/valo=8,884.99 2006.257.19:54:08.82#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.19:54:08.82#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.19:54:08.82#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:08.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:08.82#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:08.82#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:08.82#ibcon#enter wrdev, iclass 37, count 0 2006.257.19:54:08.82#ibcon#first serial, iclass 37, count 0 2006.257.19:54:08.82#ibcon#enter sib2, iclass 37, count 0 2006.257.19:54:08.82#ibcon#flushed, iclass 37, count 0 2006.257.19:54:08.82#ibcon#about to write, iclass 37, count 0 2006.257.19:54:08.82#ibcon#wrote, iclass 37, count 0 2006.257.19:54:08.82#ibcon#about to read 3, iclass 37, count 0 2006.257.19:54:08.84#ibcon#read 3, iclass 37, count 0 2006.257.19:54:08.84#ibcon#about to read 4, iclass 37, count 0 2006.257.19:54:08.84#ibcon#read 4, iclass 37, count 0 2006.257.19:54:08.84#ibcon#about to read 5, iclass 37, count 0 2006.257.19:54:08.84#ibcon#read 5, iclass 37, count 0 2006.257.19:54:08.84#ibcon#about to read 6, iclass 37, count 0 2006.257.19:54:08.84#ibcon#read 6, iclass 37, count 0 2006.257.19:54:08.84#ibcon#end of sib2, iclass 37, count 0 2006.257.19:54:08.84#ibcon#*mode == 0, iclass 37, count 0 2006.257.19:54:08.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.19:54:08.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.19:54:08.84#ibcon#*before write, iclass 37, count 0 2006.257.19:54:08.84#ibcon#enter sib2, iclass 37, count 0 2006.257.19:54:08.84#ibcon#flushed, iclass 37, count 0 2006.257.19:54:08.84#ibcon#about to write, iclass 37, count 0 2006.257.19:54:08.84#ibcon#wrote, iclass 37, count 0 2006.257.19:54:08.84#ibcon#about to read 3, iclass 37, count 0 2006.257.19:54:08.88#ibcon#read 3, iclass 37, count 0 2006.257.19:54:08.88#ibcon#about to read 4, iclass 37, count 0 2006.257.19:54:08.88#ibcon#read 4, iclass 37, count 0 2006.257.19:54:08.88#ibcon#about to read 5, iclass 37, count 0 2006.257.19:54:08.88#ibcon#read 5, iclass 37, count 0 2006.257.19:54:08.88#ibcon#about to read 6, iclass 37, count 0 2006.257.19:54:08.88#ibcon#read 6, iclass 37, count 0 2006.257.19:54:08.88#ibcon#end of sib2, iclass 37, count 0 2006.257.19:54:08.88#ibcon#*after write, iclass 37, count 0 2006.257.19:54:08.88#ibcon#*before return 0, iclass 37, count 0 2006.257.19:54:08.88#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:08.88#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:08.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.19:54:08.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.19:54:08.88$vck44/va=8,4 2006.257.19:54:08.88#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.19:54:08.88#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.19:54:08.88#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:08.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:08.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:08.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:08.94#ibcon#enter wrdev, iclass 39, count 2 2006.257.19:54:08.94#ibcon#first serial, iclass 39, count 2 2006.257.19:54:08.94#ibcon#enter sib2, iclass 39, count 2 2006.257.19:54:08.94#ibcon#flushed, iclass 39, count 2 2006.257.19:54:08.94#ibcon#about to write, iclass 39, count 2 2006.257.19:54:08.94#ibcon#wrote, iclass 39, count 2 2006.257.19:54:08.94#ibcon#about to read 3, iclass 39, count 2 2006.257.19:54:08.96#ibcon#read 3, iclass 39, count 2 2006.257.19:54:08.96#ibcon#about to read 4, iclass 39, count 2 2006.257.19:54:08.96#ibcon#read 4, iclass 39, count 2 2006.257.19:54:08.96#ibcon#about to read 5, iclass 39, count 2 2006.257.19:54:08.96#ibcon#read 5, iclass 39, count 2 2006.257.19:54:08.96#ibcon#about to read 6, iclass 39, count 2 2006.257.19:54:08.96#ibcon#read 6, iclass 39, count 2 2006.257.19:54:08.96#ibcon#end of sib2, iclass 39, count 2 2006.257.19:54:08.96#ibcon#*mode == 0, iclass 39, count 2 2006.257.19:54:08.96#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.19:54:08.96#ibcon#[25=AT08-04\r\n] 2006.257.19:54:08.96#ibcon#*before write, iclass 39, count 2 2006.257.19:54:08.96#ibcon#enter sib2, iclass 39, count 2 2006.257.19:54:08.96#ibcon#flushed, iclass 39, count 2 2006.257.19:54:08.96#ibcon#about to write, iclass 39, count 2 2006.257.19:54:08.96#ibcon#wrote, iclass 39, count 2 2006.257.19:54:08.96#ibcon#about to read 3, iclass 39, count 2 2006.257.19:54:08.99#ibcon#read 3, iclass 39, count 2 2006.257.19:54:08.99#ibcon#about to read 4, iclass 39, count 2 2006.257.19:54:08.99#ibcon#read 4, iclass 39, count 2 2006.257.19:54:08.99#ibcon#about to read 5, iclass 39, count 2 2006.257.19:54:08.99#ibcon#read 5, iclass 39, count 2 2006.257.19:54:08.99#ibcon#about to read 6, iclass 39, count 2 2006.257.19:54:08.99#ibcon#read 6, iclass 39, count 2 2006.257.19:54:08.99#ibcon#end of sib2, iclass 39, count 2 2006.257.19:54:08.99#ibcon#*after write, iclass 39, count 2 2006.257.19:54:08.99#ibcon#*before return 0, iclass 39, count 2 2006.257.19:54:08.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:08.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:08.99#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.19:54:08.99#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:08.99#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:09.11#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:09.11#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:09.11#ibcon#enter wrdev, iclass 39, count 0 2006.257.19:54:09.11#ibcon#first serial, iclass 39, count 0 2006.257.19:54:09.11#ibcon#enter sib2, iclass 39, count 0 2006.257.19:54:09.11#ibcon#flushed, iclass 39, count 0 2006.257.19:54:09.11#ibcon#about to write, iclass 39, count 0 2006.257.19:54:09.11#ibcon#wrote, iclass 39, count 0 2006.257.19:54:09.11#ibcon#about to read 3, iclass 39, count 0 2006.257.19:54:09.13#ibcon#read 3, iclass 39, count 0 2006.257.19:54:09.13#ibcon#about to read 4, iclass 39, count 0 2006.257.19:54:09.13#ibcon#read 4, iclass 39, count 0 2006.257.19:54:09.13#ibcon#about to read 5, iclass 39, count 0 2006.257.19:54:09.13#ibcon#read 5, iclass 39, count 0 2006.257.19:54:09.13#ibcon#about to read 6, iclass 39, count 0 2006.257.19:54:09.13#ibcon#read 6, iclass 39, count 0 2006.257.19:54:09.13#ibcon#end of sib2, iclass 39, count 0 2006.257.19:54:09.13#ibcon#*mode == 0, iclass 39, count 0 2006.257.19:54:09.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.19:54:09.13#ibcon#[25=USB\r\n] 2006.257.19:54:09.13#ibcon#*before write, iclass 39, count 0 2006.257.19:54:09.13#ibcon#enter sib2, iclass 39, count 0 2006.257.19:54:09.13#ibcon#flushed, iclass 39, count 0 2006.257.19:54:09.13#ibcon#about to write, iclass 39, count 0 2006.257.19:54:09.13#ibcon#wrote, iclass 39, count 0 2006.257.19:54:09.13#ibcon#about to read 3, iclass 39, count 0 2006.257.19:54:09.16#ibcon#read 3, iclass 39, count 0 2006.257.19:54:09.16#ibcon#about to read 4, iclass 39, count 0 2006.257.19:54:09.16#ibcon#read 4, iclass 39, count 0 2006.257.19:54:09.16#ibcon#about to read 5, iclass 39, count 0 2006.257.19:54:09.16#ibcon#read 5, iclass 39, count 0 2006.257.19:54:09.16#ibcon#about to read 6, iclass 39, count 0 2006.257.19:54:09.16#ibcon#read 6, iclass 39, count 0 2006.257.19:54:09.16#ibcon#end of sib2, iclass 39, count 0 2006.257.19:54:09.16#ibcon#*after write, iclass 39, count 0 2006.257.19:54:09.16#ibcon#*before return 0, iclass 39, count 0 2006.257.19:54:09.16#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:09.16#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:09.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.19:54:09.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.19:54:09.16$vck44/vblo=1,629.99 2006.257.19:54:09.16#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.19:54:09.16#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.19:54:09.16#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:09.16#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:09.16#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:09.16#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:09.16#ibcon#enter wrdev, iclass 3, count 0 2006.257.19:54:09.16#ibcon#first serial, iclass 3, count 0 2006.257.19:54:09.16#ibcon#enter sib2, iclass 3, count 0 2006.257.19:54:09.16#ibcon#flushed, iclass 3, count 0 2006.257.19:54:09.16#ibcon#about to write, iclass 3, count 0 2006.257.19:54:09.16#ibcon#wrote, iclass 3, count 0 2006.257.19:54:09.16#ibcon#about to read 3, iclass 3, count 0 2006.257.19:54:09.18#ibcon#read 3, iclass 3, count 0 2006.257.19:54:09.18#ibcon#about to read 4, iclass 3, count 0 2006.257.19:54:09.18#ibcon#read 4, iclass 3, count 0 2006.257.19:54:09.18#ibcon#about to read 5, iclass 3, count 0 2006.257.19:54:09.18#ibcon#read 5, iclass 3, count 0 2006.257.19:54:09.18#ibcon#about to read 6, iclass 3, count 0 2006.257.19:54:09.18#ibcon#read 6, iclass 3, count 0 2006.257.19:54:09.18#ibcon#end of sib2, iclass 3, count 0 2006.257.19:54:09.18#ibcon#*mode == 0, iclass 3, count 0 2006.257.19:54:09.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.19:54:09.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.19:54:09.18#ibcon#*before write, iclass 3, count 0 2006.257.19:54:09.18#ibcon#enter sib2, iclass 3, count 0 2006.257.19:54:09.18#ibcon#flushed, iclass 3, count 0 2006.257.19:54:09.18#ibcon#about to write, iclass 3, count 0 2006.257.19:54:09.18#ibcon#wrote, iclass 3, count 0 2006.257.19:54:09.18#ibcon#about to read 3, iclass 3, count 0 2006.257.19:54:09.22#ibcon#read 3, iclass 3, count 0 2006.257.19:54:09.22#ibcon#about to read 4, iclass 3, count 0 2006.257.19:54:09.22#ibcon#read 4, iclass 3, count 0 2006.257.19:54:09.22#ibcon#about to read 5, iclass 3, count 0 2006.257.19:54:09.22#ibcon#read 5, iclass 3, count 0 2006.257.19:54:09.22#ibcon#about to read 6, iclass 3, count 0 2006.257.19:54:09.22#ibcon#read 6, iclass 3, count 0 2006.257.19:54:09.22#ibcon#end of sib2, iclass 3, count 0 2006.257.19:54:09.22#ibcon#*after write, iclass 3, count 0 2006.257.19:54:09.22#ibcon#*before return 0, iclass 3, count 0 2006.257.19:54:09.22#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:09.22#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:09.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.19:54:09.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.19:54:09.22$vck44/vb=1,4 2006.257.19:54:09.22#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.19:54:09.22#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.19:54:09.22#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:09.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:54:09.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:54:09.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:54:09.22#ibcon#enter wrdev, iclass 5, count 2 2006.257.19:54:09.22#ibcon#first serial, iclass 5, count 2 2006.257.19:54:09.22#ibcon#enter sib2, iclass 5, count 2 2006.257.19:54:09.22#ibcon#flushed, iclass 5, count 2 2006.257.19:54:09.22#ibcon#about to write, iclass 5, count 2 2006.257.19:54:09.22#ibcon#wrote, iclass 5, count 2 2006.257.19:54:09.22#ibcon#about to read 3, iclass 5, count 2 2006.257.19:54:09.24#ibcon#read 3, iclass 5, count 2 2006.257.19:54:09.24#ibcon#about to read 4, iclass 5, count 2 2006.257.19:54:09.24#ibcon#read 4, iclass 5, count 2 2006.257.19:54:09.24#ibcon#about to read 5, iclass 5, count 2 2006.257.19:54:09.24#ibcon#read 5, iclass 5, count 2 2006.257.19:54:09.24#ibcon#about to read 6, iclass 5, count 2 2006.257.19:54:09.24#ibcon#read 6, iclass 5, count 2 2006.257.19:54:09.24#ibcon#end of sib2, iclass 5, count 2 2006.257.19:54:09.24#ibcon#*mode == 0, iclass 5, count 2 2006.257.19:54:09.24#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.19:54:09.24#ibcon#[27=AT01-04\r\n] 2006.257.19:54:09.24#ibcon#*before write, iclass 5, count 2 2006.257.19:54:09.24#ibcon#enter sib2, iclass 5, count 2 2006.257.19:54:09.24#ibcon#flushed, iclass 5, count 2 2006.257.19:54:09.24#ibcon#about to write, iclass 5, count 2 2006.257.19:54:09.24#ibcon#wrote, iclass 5, count 2 2006.257.19:54:09.24#ibcon#about to read 3, iclass 5, count 2 2006.257.19:54:09.27#ibcon#read 3, iclass 5, count 2 2006.257.19:54:09.27#ibcon#about to read 4, iclass 5, count 2 2006.257.19:54:09.27#ibcon#read 4, iclass 5, count 2 2006.257.19:54:09.27#ibcon#about to read 5, iclass 5, count 2 2006.257.19:54:09.27#ibcon#read 5, iclass 5, count 2 2006.257.19:54:09.27#ibcon#about to read 6, iclass 5, count 2 2006.257.19:54:09.27#ibcon#read 6, iclass 5, count 2 2006.257.19:54:09.27#ibcon#end of sib2, iclass 5, count 2 2006.257.19:54:09.27#ibcon#*after write, iclass 5, count 2 2006.257.19:54:09.27#ibcon#*before return 0, iclass 5, count 2 2006.257.19:54:09.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:54:09.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.19:54:09.27#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.19:54:09.27#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:09.27#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:54:09.39#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:54:09.39#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:54:09.39#ibcon#enter wrdev, iclass 5, count 0 2006.257.19:54:09.39#ibcon#first serial, iclass 5, count 0 2006.257.19:54:09.39#ibcon#enter sib2, iclass 5, count 0 2006.257.19:54:09.39#ibcon#flushed, iclass 5, count 0 2006.257.19:54:09.39#ibcon#about to write, iclass 5, count 0 2006.257.19:54:09.39#ibcon#wrote, iclass 5, count 0 2006.257.19:54:09.39#ibcon#about to read 3, iclass 5, count 0 2006.257.19:54:09.41#ibcon#read 3, iclass 5, count 0 2006.257.19:54:09.41#ibcon#about to read 4, iclass 5, count 0 2006.257.19:54:09.41#ibcon#read 4, iclass 5, count 0 2006.257.19:54:09.41#ibcon#about to read 5, iclass 5, count 0 2006.257.19:54:09.41#ibcon#read 5, iclass 5, count 0 2006.257.19:54:09.41#ibcon#about to read 6, iclass 5, count 0 2006.257.19:54:09.41#ibcon#read 6, iclass 5, count 0 2006.257.19:54:09.41#ibcon#end of sib2, iclass 5, count 0 2006.257.19:54:09.41#ibcon#*mode == 0, iclass 5, count 0 2006.257.19:54:09.41#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.19:54:09.41#ibcon#[27=USB\r\n] 2006.257.19:54:09.41#ibcon#*before write, iclass 5, count 0 2006.257.19:54:09.41#ibcon#enter sib2, iclass 5, count 0 2006.257.19:54:09.41#ibcon#flushed, iclass 5, count 0 2006.257.19:54:09.41#ibcon#about to write, iclass 5, count 0 2006.257.19:54:09.41#ibcon#wrote, iclass 5, count 0 2006.257.19:54:09.41#ibcon#about to read 3, iclass 5, count 0 2006.257.19:54:09.44#ibcon#read 3, iclass 5, count 0 2006.257.19:54:09.44#ibcon#about to read 4, iclass 5, count 0 2006.257.19:54:09.44#ibcon#read 4, iclass 5, count 0 2006.257.19:54:09.44#ibcon#about to read 5, iclass 5, count 0 2006.257.19:54:09.44#ibcon#read 5, iclass 5, count 0 2006.257.19:54:09.44#ibcon#about to read 6, iclass 5, count 0 2006.257.19:54:09.44#ibcon#read 6, iclass 5, count 0 2006.257.19:54:09.44#ibcon#end of sib2, iclass 5, count 0 2006.257.19:54:09.44#ibcon#*after write, iclass 5, count 0 2006.257.19:54:09.44#ibcon#*before return 0, iclass 5, count 0 2006.257.19:54:09.44#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:54:09.44#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.19:54:09.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.19:54:09.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.19:54:09.44$vck44/vblo=2,634.99 2006.257.19:54:09.44#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.19:54:09.44#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.19:54:09.44#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:09.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:09.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:09.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:09.44#ibcon#enter wrdev, iclass 7, count 0 2006.257.19:54:09.44#ibcon#first serial, iclass 7, count 0 2006.257.19:54:09.44#ibcon#enter sib2, iclass 7, count 0 2006.257.19:54:09.44#ibcon#flushed, iclass 7, count 0 2006.257.19:54:09.44#ibcon#about to write, iclass 7, count 0 2006.257.19:54:09.44#ibcon#wrote, iclass 7, count 0 2006.257.19:54:09.44#ibcon#about to read 3, iclass 7, count 0 2006.257.19:54:09.46#ibcon#read 3, iclass 7, count 0 2006.257.19:54:09.46#ibcon#about to read 4, iclass 7, count 0 2006.257.19:54:09.46#ibcon#read 4, iclass 7, count 0 2006.257.19:54:09.46#ibcon#about to read 5, iclass 7, count 0 2006.257.19:54:09.46#ibcon#read 5, iclass 7, count 0 2006.257.19:54:09.46#ibcon#about to read 6, iclass 7, count 0 2006.257.19:54:09.46#ibcon#read 6, iclass 7, count 0 2006.257.19:54:09.46#ibcon#end of sib2, iclass 7, count 0 2006.257.19:54:09.46#ibcon#*mode == 0, iclass 7, count 0 2006.257.19:54:09.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.19:54:09.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.19:54:09.46#ibcon#*before write, iclass 7, count 0 2006.257.19:54:09.46#ibcon#enter sib2, iclass 7, count 0 2006.257.19:54:09.46#ibcon#flushed, iclass 7, count 0 2006.257.19:54:09.46#ibcon#about to write, iclass 7, count 0 2006.257.19:54:09.46#ibcon#wrote, iclass 7, count 0 2006.257.19:54:09.46#ibcon#about to read 3, iclass 7, count 0 2006.257.19:54:09.50#ibcon#read 3, iclass 7, count 0 2006.257.19:54:09.50#ibcon#about to read 4, iclass 7, count 0 2006.257.19:54:09.50#ibcon#read 4, iclass 7, count 0 2006.257.19:54:09.50#ibcon#about to read 5, iclass 7, count 0 2006.257.19:54:09.50#ibcon#read 5, iclass 7, count 0 2006.257.19:54:09.50#ibcon#about to read 6, iclass 7, count 0 2006.257.19:54:09.50#ibcon#read 6, iclass 7, count 0 2006.257.19:54:09.50#ibcon#end of sib2, iclass 7, count 0 2006.257.19:54:09.50#ibcon#*after write, iclass 7, count 0 2006.257.19:54:09.50#ibcon#*before return 0, iclass 7, count 0 2006.257.19:54:09.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:09.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.19:54:09.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.19:54:09.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.19:54:09.50$vck44/vb=2,5 2006.257.19:54:09.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.19:54:09.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.19:54:09.50#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:09.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:09.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:09.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:09.56#ibcon#enter wrdev, iclass 11, count 2 2006.257.19:54:09.56#ibcon#first serial, iclass 11, count 2 2006.257.19:54:09.56#ibcon#enter sib2, iclass 11, count 2 2006.257.19:54:09.56#ibcon#flushed, iclass 11, count 2 2006.257.19:54:09.56#ibcon#about to write, iclass 11, count 2 2006.257.19:54:09.56#ibcon#wrote, iclass 11, count 2 2006.257.19:54:09.56#ibcon#about to read 3, iclass 11, count 2 2006.257.19:54:09.58#ibcon#read 3, iclass 11, count 2 2006.257.19:54:09.58#ibcon#about to read 4, iclass 11, count 2 2006.257.19:54:09.58#ibcon#read 4, iclass 11, count 2 2006.257.19:54:09.58#ibcon#about to read 5, iclass 11, count 2 2006.257.19:54:09.58#ibcon#read 5, iclass 11, count 2 2006.257.19:54:09.58#ibcon#about to read 6, iclass 11, count 2 2006.257.19:54:09.58#ibcon#read 6, iclass 11, count 2 2006.257.19:54:09.58#ibcon#end of sib2, iclass 11, count 2 2006.257.19:54:09.58#ibcon#*mode == 0, iclass 11, count 2 2006.257.19:54:09.58#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.19:54:09.58#ibcon#[27=AT02-05\r\n] 2006.257.19:54:09.58#ibcon#*before write, iclass 11, count 2 2006.257.19:54:09.58#ibcon#enter sib2, iclass 11, count 2 2006.257.19:54:09.58#ibcon#flushed, iclass 11, count 2 2006.257.19:54:09.58#ibcon#about to write, iclass 11, count 2 2006.257.19:54:09.58#ibcon#wrote, iclass 11, count 2 2006.257.19:54:09.58#ibcon#about to read 3, iclass 11, count 2 2006.257.19:54:09.61#ibcon#read 3, iclass 11, count 2 2006.257.19:54:09.61#ibcon#about to read 4, iclass 11, count 2 2006.257.19:54:09.61#ibcon#read 4, iclass 11, count 2 2006.257.19:54:09.61#ibcon#about to read 5, iclass 11, count 2 2006.257.19:54:09.61#ibcon#read 5, iclass 11, count 2 2006.257.19:54:09.61#ibcon#about to read 6, iclass 11, count 2 2006.257.19:54:09.61#ibcon#read 6, iclass 11, count 2 2006.257.19:54:09.61#ibcon#end of sib2, iclass 11, count 2 2006.257.19:54:09.61#ibcon#*after write, iclass 11, count 2 2006.257.19:54:09.61#ibcon#*before return 0, iclass 11, count 2 2006.257.19:54:09.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:09.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.19:54:09.61#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.19:54:09.61#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:09.61#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:09.63#abcon#<5=/14 1.3 4.4 17.53 961014.6\r\n> 2006.257.19:54:09.65#abcon#{5=INTERFACE CLEAR} 2006.257.19:54:09.71#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:54:09.73#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:09.73#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:09.73#ibcon#enter wrdev, iclass 11, count 0 2006.257.19:54:09.73#ibcon#first serial, iclass 11, count 0 2006.257.19:54:09.73#ibcon#enter sib2, iclass 11, count 0 2006.257.19:54:09.73#ibcon#flushed, iclass 11, count 0 2006.257.19:54:09.73#ibcon#about to write, iclass 11, count 0 2006.257.19:54:09.73#ibcon#wrote, iclass 11, count 0 2006.257.19:54:09.73#ibcon#about to read 3, iclass 11, count 0 2006.257.19:54:09.75#ibcon#read 3, iclass 11, count 0 2006.257.19:54:09.75#ibcon#about to read 4, iclass 11, count 0 2006.257.19:54:09.75#ibcon#read 4, iclass 11, count 0 2006.257.19:54:09.75#ibcon#about to read 5, iclass 11, count 0 2006.257.19:54:09.75#ibcon#read 5, iclass 11, count 0 2006.257.19:54:09.75#ibcon#about to read 6, iclass 11, count 0 2006.257.19:54:09.75#ibcon#read 6, iclass 11, count 0 2006.257.19:54:09.75#ibcon#end of sib2, iclass 11, count 0 2006.257.19:54:09.75#ibcon#*mode == 0, iclass 11, count 0 2006.257.19:54:09.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.19:54:09.75#ibcon#[27=USB\r\n] 2006.257.19:54:09.75#ibcon#*before write, iclass 11, count 0 2006.257.19:54:09.75#ibcon#enter sib2, iclass 11, count 0 2006.257.19:54:09.75#ibcon#flushed, iclass 11, count 0 2006.257.19:54:09.75#ibcon#about to write, iclass 11, count 0 2006.257.19:54:09.75#ibcon#wrote, iclass 11, count 0 2006.257.19:54:09.75#ibcon#about to read 3, iclass 11, count 0 2006.257.19:54:09.78#ibcon#read 3, iclass 11, count 0 2006.257.19:54:09.78#ibcon#about to read 4, iclass 11, count 0 2006.257.19:54:09.78#ibcon#read 4, iclass 11, count 0 2006.257.19:54:09.78#ibcon#about to read 5, iclass 11, count 0 2006.257.19:54:09.78#ibcon#read 5, iclass 11, count 0 2006.257.19:54:09.78#ibcon#about to read 6, iclass 11, count 0 2006.257.19:54:09.78#ibcon#read 6, iclass 11, count 0 2006.257.19:54:09.78#ibcon#end of sib2, iclass 11, count 0 2006.257.19:54:09.78#ibcon#*after write, iclass 11, count 0 2006.257.19:54:09.78#ibcon#*before return 0, iclass 11, count 0 2006.257.19:54:09.78#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:09.78#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.19:54:09.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.19:54:09.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.19:54:09.78$vck44/vblo=3,649.99 2006.257.19:54:09.78#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.19:54:09.78#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.19:54:09.78#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:09.78#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:09.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:09.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:09.78#ibcon#enter wrdev, iclass 17, count 0 2006.257.19:54:09.78#ibcon#first serial, iclass 17, count 0 2006.257.19:54:09.78#ibcon#enter sib2, iclass 17, count 0 2006.257.19:54:09.78#ibcon#flushed, iclass 17, count 0 2006.257.19:54:09.78#ibcon#about to write, iclass 17, count 0 2006.257.19:54:09.78#ibcon#wrote, iclass 17, count 0 2006.257.19:54:09.78#ibcon#about to read 3, iclass 17, count 0 2006.257.19:54:09.80#ibcon#read 3, iclass 17, count 0 2006.257.19:54:09.80#ibcon#about to read 4, iclass 17, count 0 2006.257.19:54:09.80#ibcon#read 4, iclass 17, count 0 2006.257.19:54:09.80#ibcon#about to read 5, iclass 17, count 0 2006.257.19:54:09.80#ibcon#read 5, iclass 17, count 0 2006.257.19:54:09.80#ibcon#about to read 6, iclass 17, count 0 2006.257.19:54:09.80#ibcon#read 6, iclass 17, count 0 2006.257.19:54:09.80#ibcon#end of sib2, iclass 17, count 0 2006.257.19:54:09.80#ibcon#*mode == 0, iclass 17, count 0 2006.257.19:54:09.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.19:54:09.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.19:54:09.80#ibcon#*before write, iclass 17, count 0 2006.257.19:54:09.80#ibcon#enter sib2, iclass 17, count 0 2006.257.19:54:09.80#ibcon#flushed, iclass 17, count 0 2006.257.19:54:09.80#ibcon#about to write, iclass 17, count 0 2006.257.19:54:09.80#ibcon#wrote, iclass 17, count 0 2006.257.19:54:09.80#ibcon#about to read 3, iclass 17, count 0 2006.257.19:54:09.84#ibcon#read 3, iclass 17, count 0 2006.257.19:54:09.84#ibcon#about to read 4, iclass 17, count 0 2006.257.19:54:09.84#ibcon#read 4, iclass 17, count 0 2006.257.19:54:09.84#ibcon#about to read 5, iclass 17, count 0 2006.257.19:54:09.84#ibcon#read 5, iclass 17, count 0 2006.257.19:54:09.84#ibcon#about to read 6, iclass 17, count 0 2006.257.19:54:09.84#ibcon#read 6, iclass 17, count 0 2006.257.19:54:09.84#ibcon#end of sib2, iclass 17, count 0 2006.257.19:54:09.84#ibcon#*after write, iclass 17, count 0 2006.257.19:54:09.84#ibcon#*before return 0, iclass 17, count 0 2006.257.19:54:09.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:09.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.19:54:09.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.19:54:09.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.19:54:09.84$vck44/vb=3,4 2006.257.19:54:09.84#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.19:54:09.84#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.19:54:09.84#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:09.84#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:09.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:09.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:09.90#ibcon#enter wrdev, iclass 19, count 2 2006.257.19:54:09.90#ibcon#first serial, iclass 19, count 2 2006.257.19:54:09.90#ibcon#enter sib2, iclass 19, count 2 2006.257.19:54:09.90#ibcon#flushed, iclass 19, count 2 2006.257.19:54:09.90#ibcon#about to write, iclass 19, count 2 2006.257.19:54:09.90#ibcon#wrote, iclass 19, count 2 2006.257.19:54:09.90#ibcon#about to read 3, iclass 19, count 2 2006.257.19:54:09.92#ibcon#read 3, iclass 19, count 2 2006.257.19:54:09.92#ibcon#about to read 4, iclass 19, count 2 2006.257.19:54:09.92#ibcon#read 4, iclass 19, count 2 2006.257.19:54:09.92#ibcon#about to read 5, iclass 19, count 2 2006.257.19:54:09.92#ibcon#read 5, iclass 19, count 2 2006.257.19:54:09.92#ibcon#about to read 6, iclass 19, count 2 2006.257.19:54:09.92#ibcon#read 6, iclass 19, count 2 2006.257.19:54:09.92#ibcon#end of sib2, iclass 19, count 2 2006.257.19:54:09.92#ibcon#*mode == 0, iclass 19, count 2 2006.257.19:54:09.92#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.19:54:09.92#ibcon#[27=AT03-04\r\n] 2006.257.19:54:09.92#ibcon#*before write, iclass 19, count 2 2006.257.19:54:09.92#ibcon#enter sib2, iclass 19, count 2 2006.257.19:54:09.92#ibcon#flushed, iclass 19, count 2 2006.257.19:54:09.92#ibcon#about to write, iclass 19, count 2 2006.257.19:54:09.92#ibcon#wrote, iclass 19, count 2 2006.257.19:54:09.92#ibcon#about to read 3, iclass 19, count 2 2006.257.19:54:09.95#ibcon#read 3, iclass 19, count 2 2006.257.19:54:09.95#ibcon#about to read 4, iclass 19, count 2 2006.257.19:54:09.95#ibcon#read 4, iclass 19, count 2 2006.257.19:54:09.95#ibcon#about to read 5, iclass 19, count 2 2006.257.19:54:09.95#ibcon#read 5, iclass 19, count 2 2006.257.19:54:09.95#ibcon#about to read 6, iclass 19, count 2 2006.257.19:54:09.95#ibcon#read 6, iclass 19, count 2 2006.257.19:54:09.95#ibcon#end of sib2, iclass 19, count 2 2006.257.19:54:09.95#ibcon#*after write, iclass 19, count 2 2006.257.19:54:09.95#ibcon#*before return 0, iclass 19, count 2 2006.257.19:54:09.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:09.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.19:54:09.95#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.19:54:09.95#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:09.95#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:10.07#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:10.07#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:10.07#ibcon#enter wrdev, iclass 19, count 0 2006.257.19:54:10.07#ibcon#first serial, iclass 19, count 0 2006.257.19:54:10.07#ibcon#enter sib2, iclass 19, count 0 2006.257.19:54:10.07#ibcon#flushed, iclass 19, count 0 2006.257.19:54:10.07#ibcon#about to write, iclass 19, count 0 2006.257.19:54:10.07#ibcon#wrote, iclass 19, count 0 2006.257.19:54:10.07#ibcon#about to read 3, iclass 19, count 0 2006.257.19:54:10.09#ibcon#read 3, iclass 19, count 0 2006.257.19:54:10.09#ibcon#about to read 4, iclass 19, count 0 2006.257.19:54:10.09#ibcon#read 4, iclass 19, count 0 2006.257.19:54:10.09#ibcon#about to read 5, iclass 19, count 0 2006.257.19:54:10.09#ibcon#read 5, iclass 19, count 0 2006.257.19:54:10.09#ibcon#about to read 6, iclass 19, count 0 2006.257.19:54:10.09#ibcon#read 6, iclass 19, count 0 2006.257.19:54:10.09#ibcon#end of sib2, iclass 19, count 0 2006.257.19:54:10.09#ibcon#*mode == 0, iclass 19, count 0 2006.257.19:54:10.09#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.19:54:10.09#ibcon#[27=USB\r\n] 2006.257.19:54:10.09#ibcon#*before write, iclass 19, count 0 2006.257.19:54:10.09#ibcon#enter sib2, iclass 19, count 0 2006.257.19:54:10.09#ibcon#flushed, iclass 19, count 0 2006.257.19:54:10.09#ibcon#about to write, iclass 19, count 0 2006.257.19:54:10.09#ibcon#wrote, iclass 19, count 0 2006.257.19:54:10.09#ibcon#about to read 3, iclass 19, count 0 2006.257.19:54:10.12#ibcon#read 3, iclass 19, count 0 2006.257.19:54:10.12#ibcon#about to read 4, iclass 19, count 0 2006.257.19:54:10.12#ibcon#read 4, iclass 19, count 0 2006.257.19:54:10.12#ibcon#about to read 5, iclass 19, count 0 2006.257.19:54:10.12#ibcon#read 5, iclass 19, count 0 2006.257.19:54:10.12#ibcon#about to read 6, iclass 19, count 0 2006.257.19:54:10.12#ibcon#read 6, iclass 19, count 0 2006.257.19:54:10.12#ibcon#end of sib2, iclass 19, count 0 2006.257.19:54:10.12#ibcon#*after write, iclass 19, count 0 2006.257.19:54:10.12#ibcon#*before return 0, iclass 19, count 0 2006.257.19:54:10.12#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:10.12#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.19:54:10.12#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.19:54:10.12#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.19:54:10.12$vck44/vblo=4,679.99 2006.257.19:54:10.12#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.19:54:10.12#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.19:54:10.12#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:10.12#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:10.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:10.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:10.12#ibcon#enter wrdev, iclass 21, count 0 2006.257.19:54:10.12#ibcon#first serial, iclass 21, count 0 2006.257.19:54:10.12#ibcon#enter sib2, iclass 21, count 0 2006.257.19:54:10.12#ibcon#flushed, iclass 21, count 0 2006.257.19:54:10.12#ibcon#about to write, iclass 21, count 0 2006.257.19:54:10.12#ibcon#wrote, iclass 21, count 0 2006.257.19:54:10.12#ibcon#about to read 3, iclass 21, count 0 2006.257.19:54:10.14#ibcon#read 3, iclass 21, count 0 2006.257.19:54:10.14#ibcon#about to read 4, iclass 21, count 0 2006.257.19:54:10.14#ibcon#read 4, iclass 21, count 0 2006.257.19:54:10.14#ibcon#about to read 5, iclass 21, count 0 2006.257.19:54:10.14#ibcon#read 5, iclass 21, count 0 2006.257.19:54:10.14#ibcon#about to read 6, iclass 21, count 0 2006.257.19:54:10.14#ibcon#read 6, iclass 21, count 0 2006.257.19:54:10.14#ibcon#end of sib2, iclass 21, count 0 2006.257.19:54:10.14#ibcon#*mode == 0, iclass 21, count 0 2006.257.19:54:10.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.19:54:10.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.19:54:10.14#ibcon#*before write, iclass 21, count 0 2006.257.19:54:10.14#ibcon#enter sib2, iclass 21, count 0 2006.257.19:54:10.14#ibcon#flushed, iclass 21, count 0 2006.257.19:54:10.14#ibcon#about to write, iclass 21, count 0 2006.257.19:54:10.14#ibcon#wrote, iclass 21, count 0 2006.257.19:54:10.14#ibcon#about to read 3, iclass 21, count 0 2006.257.19:54:10.18#ibcon#read 3, iclass 21, count 0 2006.257.19:54:10.18#ibcon#about to read 4, iclass 21, count 0 2006.257.19:54:10.18#ibcon#read 4, iclass 21, count 0 2006.257.19:54:10.18#ibcon#about to read 5, iclass 21, count 0 2006.257.19:54:10.18#ibcon#read 5, iclass 21, count 0 2006.257.19:54:10.18#ibcon#about to read 6, iclass 21, count 0 2006.257.19:54:10.18#ibcon#read 6, iclass 21, count 0 2006.257.19:54:10.18#ibcon#end of sib2, iclass 21, count 0 2006.257.19:54:10.18#ibcon#*after write, iclass 21, count 0 2006.257.19:54:10.18#ibcon#*before return 0, iclass 21, count 0 2006.257.19:54:10.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:10.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.19:54:10.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.19:54:10.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.19:54:10.18$vck44/vb=4,5 2006.257.19:54:10.18#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.19:54:10.18#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.19:54:10.18#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:10.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:10.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:10.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:10.24#ibcon#enter wrdev, iclass 23, count 2 2006.257.19:54:10.24#ibcon#first serial, iclass 23, count 2 2006.257.19:54:10.24#ibcon#enter sib2, iclass 23, count 2 2006.257.19:54:10.24#ibcon#flushed, iclass 23, count 2 2006.257.19:54:10.24#ibcon#about to write, iclass 23, count 2 2006.257.19:54:10.24#ibcon#wrote, iclass 23, count 2 2006.257.19:54:10.24#ibcon#about to read 3, iclass 23, count 2 2006.257.19:54:10.26#ibcon#read 3, iclass 23, count 2 2006.257.19:54:10.26#ibcon#about to read 4, iclass 23, count 2 2006.257.19:54:10.26#ibcon#read 4, iclass 23, count 2 2006.257.19:54:10.26#ibcon#about to read 5, iclass 23, count 2 2006.257.19:54:10.26#ibcon#read 5, iclass 23, count 2 2006.257.19:54:10.26#ibcon#about to read 6, iclass 23, count 2 2006.257.19:54:10.26#ibcon#read 6, iclass 23, count 2 2006.257.19:54:10.26#ibcon#end of sib2, iclass 23, count 2 2006.257.19:54:10.26#ibcon#*mode == 0, iclass 23, count 2 2006.257.19:54:10.26#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.19:54:10.26#ibcon#[27=AT04-05\r\n] 2006.257.19:54:10.26#ibcon#*before write, iclass 23, count 2 2006.257.19:54:10.26#ibcon#enter sib2, iclass 23, count 2 2006.257.19:54:10.26#ibcon#flushed, iclass 23, count 2 2006.257.19:54:10.26#ibcon#about to write, iclass 23, count 2 2006.257.19:54:10.26#ibcon#wrote, iclass 23, count 2 2006.257.19:54:10.26#ibcon#about to read 3, iclass 23, count 2 2006.257.19:54:10.29#ibcon#read 3, iclass 23, count 2 2006.257.19:54:10.29#ibcon#about to read 4, iclass 23, count 2 2006.257.19:54:10.29#ibcon#read 4, iclass 23, count 2 2006.257.19:54:10.29#ibcon#about to read 5, iclass 23, count 2 2006.257.19:54:10.29#ibcon#read 5, iclass 23, count 2 2006.257.19:54:10.29#ibcon#about to read 6, iclass 23, count 2 2006.257.19:54:10.29#ibcon#read 6, iclass 23, count 2 2006.257.19:54:10.29#ibcon#end of sib2, iclass 23, count 2 2006.257.19:54:10.29#ibcon#*after write, iclass 23, count 2 2006.257.19:54:10.29#ibcon#*before return 0, iclass 23, count 2 2006.257.19:54:10.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:10.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.19:54:10.29#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.19:54:10.29#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:10.29#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:10.41#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:10.41#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:10.41#ibcon#enter wrdev, iclass 23, count 0 2006.257.19:54:10.41#ibcon#first serial, iclass 23, count 0 2006.257.19:54:10.41#ibcon#enter sib2, iclass 23, count 0 2006.257.19:54:10.41#ibcon#flushed, iclass 23, count 0 2006.257.19:54:10.41#ibcon#about to write, iclass 23, count 0 2006.257.19:54:10.41#ibcon#wrote, iclass 23, count 0 2006.257.19:54:10.41#ibcon#about to read 3, iclass 23, count 0 2006.257.19:54:10.43#ibcon#read 3, iclass 23, count 0 2006.257.19:54:10.43#ibcon#about to read 4, iclass 23, count 0 2006.257.19:54:10.43#ibcon#read 4, iclass 23, count 0 2006.257.19:54:10.43#ibcon#about to read 5, iclass 23, count 0 2006.257.19:54:10.43#ibcon#read 5, iclass 23, count 0 2006.257.19:54:10.43#ibcon#about to read 6, iclass 23, count 0 2006.257.19:54:10.43#ibcon#read 6, iclass 23, count 0 2006.257.19:54:10.43#ibcon#end of sib2, iclass 23, count 0 2006.257.19:54:10.43#ibcon#*mode == 0, iclass 23, count 0 2006.257.19:54:10.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.19:54:10.43#ibcon#[27=USB\r\n] 2006.257.19:54:10.43#ibcon#*before write, iclass 23, count 0 2006.257.19:54:10.43#ibcon#enter sib2, iclass 23, count 0 2006.257.19:54:10.43#ibcon#flushed, iclass 23, count 0 2006.257.19:54:10.43#ibcon#about to write, iclass 23, count 0 2006.257.19:54:10.43#ibcon#wrote, iclass 23, count 0 2006.257.19:54:10.43#ibcon#about to read 3, iclass 23, count 0 2006.257.19:54:10.46#ibcon#read 3, iclass 23, count 0 2006.257.19:54:10.46#ibcon#about to read 4, iclass 23, count 0 2006.257.19:54:10.46#ibcon#read 4, iclass 23, count 0 2006.257.19:54:10.46#ibcon#about to read 5, iclass 23, count 0 2006.257.19:54:10.46#ibcon#read 5, iclass 23, count 0 2006.257.19:54:10.46#ibcon#about to read 6, iclass 23, count 0 2006.257.19:54:10.46#ibcon#read 6, iclass 23, count 0 2006.257.19:54:10.46#ibcon#end of sib2, iclass 23, count 0 2006.257.19:54:10.46#ibcon#*after write, iclass 23, count 0 2006.257.19:54:10.46#ibcon#*before return 0, iclass 23, count 0 2006.257.19:54:10.46#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:10.46#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.19:54:10.46#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.19:54:10.46#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.19:54:10.46$vck44/vblo=5,709.99 2006.257.19:54:10.46#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.19:54:10.46#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.19:54:10.46#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:10.46#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:10.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:10.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:10.46#ibcon#enter wrdev, iclass 25, count 0 2006.257.19:54:10.46#ibcon#first serial, iclass 25, count 0 2006.257.19:54:10.46#ibcon#enter sib2, iclass 25, count 0 2006.257.19:54:10.46#ibcon#flushed, iclass 25, count 0 2006.257.19:54:10.46#ibcon#about to write, iclass 25, count 0 2006.257.19:54:10.46#ibcon#wrote, iclass 25, count 0 2006.257.19:54:10.46#ibcon#about to read 3, iclass 25, count 0 2006.257.19:54:10.48#ibcon#read 3, iclass 25, count 0 2006.257.19:54:10.48#ibcon#about to read 4, iclass 25, count 0 2006.257.19:54:10.48#ibcon#read 4, iclass 25, count 0 2006.257.19:54:10.48#ibcon#about to read 5, iclass 25, count 0 2006.257.19:54:10.48#ibcon#read 5, iclass 25, count 0 2006.257.19:54:10.48#ibcon#about to read 6, iclass 25, count 0 2006.257.19:54:10.48#ibcon#read 6, iclass 25, count 0 2006.257.19:54:10.48#ibcon#end of sib2, iclass 25, count 0 2006.257.19:54:10.48#ibcon#*mode == 0, iclass 25, count 0 2006.257.19:54:10.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.19:54:10.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.19:54:10.48#ibcon#*before write, iclass 25, count 0 2006.257.19:54:10.48#ibcon#enter sib2, iclass 25, count 0 2006.257.19:54:10.48#ibcon#flushed, iclass 25, count 0 2006.257.19:54:10.48#ibcon#about to write, iclass 25, count 0 2006.257.19:54:10.48#ibcon#wrote, iclass 25, count 0 2006.257.19:54:10.48#ibcon#about to read 3, iclass 25, count 0 2006.257.19:54:10.52#ibcon#read 3, iclass 25, count 0 2006.257.19:54:10.52#ibcon#about to read 4, iclass 25, count 0 2006.257.19:54:10.52#ibcon#read 4, iclass 25, count 0 2006.257.19:54:10.52#ibcon#about to read 5, iclass 25, count 0 2006.257.19:54:10.52#ibcon#read 5, iclass 25, count 0 2006.257.19:54:10.52#ibcon#about to read 6, iclass 25, count 0 2006.257.19:54:10.52#ibcon#read 6, iclass 25, count 0 2006.257.19:54:10.52#ibcon#end of sib2, iclass 25, count 0 2006.257.19:54:10.52#ibcon#*after write, iclass 25, count 0 2006.257.19:54:10.52#ibcon#*before return 0, iclass 25, count 0 2006.257.19:54:10.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:10.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.19:54:10.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.19:54:10.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.19:54:10.52$vck44/vb=5,4 2006.257.19:54:10.52#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.19:54:10.52#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.19:54:10.52#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:10.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:10.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:10.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:10.58#ibcon#enter wrdev, iclass 27, count 2 2006.257.19:54:10.58#ibcon#first serial, iclass 27, count 2 2006.257.19:54:10.58#ibcon#enter sib2, iclass 27, count 2 2006.257.19:54:10.58#ibcon#flushed, iclass 27, count 2 2006.257.19:54:10.58#ibcon#about to write, iclass 27, count 2 2006.257.19:54:10.58#ibcon#wrote, iclass 27, count 2 2006.257.19:54:10.58#ibcon#about to read 3, iclass 27, count 2 2006.257.19:54:10.60#ibcon#read 3, iclass 27, count 2 2006.257.19:54:10.60#ibcon#about to read 4, iclass 27, count 2 2006.257.19:54:10.60#ibcon#read 4, iclass 27, count 2 2006.257.19:54:10.60#ibcon#about to read 5, iclass 27, count 2 2006.257.19:54:10.60#ibcon#read 5, iclass 27, count 2 2006.257.19:54:10.60#ibcon#about to read 6, iclass 27, count 2 2006.257.19:54:10.60#ibcon#read 6, iclass 27, count 2 2006.257.19:54:10.60#ibcon#end of sib2, iclass 27, count 2 2006.257.19:54:10.60#ibcon#*mode == 0, iclass 27, count 2 2006.257.19:54:10.60#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.19:54:10.60#ibcon#[27=AT05-04\r\n] 2006.257.19:54:10.60#ibcon#*before write, iclass 27, count 2 2006.257.19:54:10.60#ibcon#enter sib2, iclass 27, count 2 2006.257.19:54:10.60#ibcon#flushed, iclass 27, count 2 2006.257.19:54:10.60#ibcon#about to write, iclass 27, count 2 2006.257.19:54:10.60#ibcon#wrote, iclass 27, count 2 2006.257.19:54:10.60#ibcon#about to read 3, iclass 27, count 2 2006.257.19:54:10.63#ibcon#read 3, iclass 27, count 2 2006.257.19:54:10.63#ibcon#about to read 4, iclass 27, count 2 2006.257.19:54:10.63#ibcon#read 4, iclass 27, count 2 2006.257.19:54:10.63#ibcon#about to read 5, iclass 27, count 2 2006.257.19:54:10.63#ibcon#read 5, iclass 27, count 2 2006.257.19:54:10.63#ibcon#about to read 6, iclass 27, count 2 2006.257.19:54:10.63#ibcon#read 6, iclass 27, count 2 2006.257.19:54:10.63#ibcon#end of sib2, iclass 27, count 2 2006.257.19:54:10.63#ibcon#*after write, iclass 27, count 2 2006.257.19:54:10.63#ibcon#*before return 0, iclass 27, count 2 2006.257.19:54:10.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:10.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.19:54:10.63#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.19:54:10.63#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:10.63#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:10.75#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:10.75#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:10.75#ibcon#enter wrdev, iclass 27, count 0 2006.257.19:54:10.75#ibcon#first serial, iclass 27, count 0 2006.257.19:54:10.75#ibcon#enter sib2, iclass 27, count 0 2006.257.19:54:10.75#ibcon#flushed, iclass 27, count 0 2006.257.19:54:10.75#ibcon#about to write, iclass 27, count 0 2006.257.19:54:10.75#ibcon#wrote, iclass 27, count 0 2006.257.19:54:10.75#ibcon#about to read 3, iclass 27, count 0 2006.257.19:54:10.77#ibcon#read 3, iclass 27, count 0 2006.257.19:54:10.77#ibcon#about to read 4, iclass 27, count 0 2006.257.19:54:10.77#ibcon#read 4, iclass 27, count 0 2006.257.19:54:10.77#ibcon#about to read 5, iclass 27, count 0 2006.257.19:54:10.77#ibcon#read 5, iclass 27, count 0 2006.257.19:54:10.77#ibcon#about to read 6, iclass 27, count 0 2006.257.19:54:10.77#ibcon#read 6, iclass 27, count 0 2006.257.19:54:10.77#ibcon#end of sib2, iclass 27, count 0 2006.257.19:54:10.77#ibcon#*mode == 0, iclass 27, count 0 2006.257.19:54:10.77#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.19:54:10.77#ibcon#[27=USB\r\n] 2006.257.19:54:10.77#ibcon#*before write, iclass 27, count 0 2006.257.19:54:10.77#ibcon#enter sib2, iclass 27, count 0 2006.257.19:54:10.77#ibcon#flushed, iclass 27, count 0 2006.257.19:54:10.77#ibcon#about to write, iclass 27, count 0 2006.257.19:54:10.77#ibcon#wrote, iclass 27, count 0 2006.257.19:54:10.77#ibcon#about to read 3, iclass 27, count 0 2006.257.19:54:10.80#ibcon#read 3, iclass 27, count 0 2006.257.19:54:10.80#ibcon#about to read 4, iclass 27, count 0 2006.257.19:54:10.80#ibcon#read 4, iclass 27, count 0 2006.257.19:54:10.80#ibcon#about to read 5, iclass 27, count 0 2006.257.19:54:10.80#ibcon#read 5, iclass 27, count 0 2006.257.19:54:10.80#ibcon#about to read 6, iclass 27, count 0 2006.257.19:54:10.80#ibcon#read 6, iclass 27, count 0 2006.257.19:54:10.80#ibcon#end of sib2, iclass 27, count 0 2006.257.19:54:10.80#ibcon#*after write, iclass 27, count 0 2006.257.19:54:10.80#ibcon#*before return 0, iclass 27, count 0 2006.257.19:54:10.80#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:10.80#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.19:54:10.80#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.19:54:10.80#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.19:54:10.80$vck44/vblo=6,719.99 2006.257.19:54:10.80#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.19:54:10.80#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.19:54:10.80#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:10.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:10.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:10.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:10.80#ibcon#enter wrdev, iclass 29, count 0 2006.257.19:54:10.80#ibcon#first serial, iclass 29, count 0 2006.257.19:54:10.80#ibcon#enter sib2, iclass 29, count 0 2006.257.19:54:10.80#ibcon#flushed, iclass 29, count 0 2006.257.19:54:10.80#ibcon#about to write, iclass 29, count 0 2006.257.19:54:10.80#ibcon#wrote, iclass 29, count 0 2006.257.19:54:10.80#ibcon#about to read 3, iclass 29, count 0 2006.257.19:54:10.82#ibcon#read 3, iclass 29, count 0 2006.257.19:54:10.82#ibcon#about to read 4, iclass 29, count 0 2006.257.19:54:10.82#ibcon#read 4, iclass 29, count 0 2006.257.19:54:10.82#ibcon#about to read 5, iclass 29, count 0 2006.257.19:54:10.82#ibcon#read 5, iclass 29, count 0 2006.257.19:54:10.82#ibcon#about to read 6, iclass 29, count 0 2006.257.19:54:10.82#ibcon#read 6, iclass 29, count 0 2006.257.19:54:10.82#ibcon#end of sib2, iclass 29, count 0 2006.257.19:54:10.82#ibcon#*mode == 0, iclass 29, count 0 2006.257.19:54:10.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.19:54:10.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.19:54:10.82#ibcon#*before write, iclass 29, count 0 2006.257.19:54:10.82#ibcon#enter sib2, iclass 29, count 0 2006.257.19:54:10.82#ibcon#flushed, iclass 29, count 0 2006.257.19:54:10.82#ibcon#about to write, iclass 29, count 0 2006.257.19:54:10.82#ibcon#wrote, iclass 29, count 0 2006.257.19:54:10.82#ibcon#about to read 3, iclass 29, count 0 2006.257.19:54:10.86#ibcon#read 3, iclass 29, count 0 2006.257.19:54:10.86#ibcon#about to read 4, iclass 29, count 0 2006.257.19:54:10.86#ibcon#read 4, iclass 29, count 0 2006.257.19:54:10.86#ibcon#about to read 5, iclass 29, count 0 2006.257.19:54:10.86#ibcon#read 5, iclass 29, count 0 2006.257.19:54:10.86#ibcon#about to read 6, iclass 29, count 0 2006.257.19:54:10.86#ibcon#read 6, iclass 29, count 0 2006.257.19:54:10.86#ibcon#end of sib2, iclass 29, count 0 2006.257.19:54:10.86#ibcon#*after write, iclass 29, count 0 2006.257.19:54:10.86#ibcon#*before return 0, iclass 29, count 0 2006.257.19:54:10.86#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:10.86#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.19:54:10.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.19:54:10.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.19:54:10.86$vck44/vb=6,4 2006.257.19:54:10.86#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.19:54:10.86#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.19:54:10.86#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:10.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:10.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:10.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:10.92#ibcon#enter wrdev, iclass 31, count 2 2006.257.19:54:10.92#ibcon#first serial, iclass 31, count 2 2006.257.19:54:10.92#ibcon#enter sib2, iclass 31, count 2 2006.257.19:54:10.92#ibcon#flushed, iclass 31, count 2 2006.257.19:54:10.92#ibcon#about to write, iclass 31, count 2 2006.257.19:54:10.92#ibcon#wrote, iclass 31, count 2 2006.257.19:54:10.92#ibcon#about to read 3, iclass 31, count 2 2006.257.19:54:10.94#ibcon#read 3, iclass 31, count 2 2006.257.19:54:10.94#ibcon#about to read 4, iclass 31, count 2 2006.257.19:54:10.94#ibcon#read 4, iclass 31, count 2 2006.257.19:54:10.94#ibcon#about to read 5, iclass 31, count 2 2006.257.19:54:10.94#ibcon#read 5, iclass 31, count 2 2006.257.19:54:10.94#ibcon#about to read 6, iclass 31, count 2 2006.257.19:54:10.94#ibcon#read 6, iclass 31, count 2 2006.257.19:54:10.94#ibcon#end of sib2, iclass 31, count 2 2006.257.19:54:10.94#ibcon#*mode == 0, iclass 31, count 2 2006.257.19:54:10.94#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.19:54:10.94#ibcon#[27=AT06-04\r\n] 2006.257.19:54:10.94#ibcon#*before write, iclass 31, count 2 2006.257.19:54:10.94#ibcon#enter sib2, iclass 31, count 2 2006.257.19:54:10.94#ibcon#flushed, iclass 31, count 2 2006.257.19:54:10.94#ibcon#about to write, iclass 31, count 2 2006.257.19:54:10.94#ibcon#wrote, iclass 31, count 2 2006.257.19:54:10.94#ibcon#about to read 3, iclass 31, count 2 2006.257.19:54:10.97#ibcon#read 3, iclass 31, count 2 2006.257.19:54:10.97#ibcon#about to read 4, iclass 31, count 2 2006.257.19:54:10.97#ibcon#read 4, iclass 31, count 2 2006.257.19:54:10.97#ibcon#about to read 5, iclass 31, count 2 2006.257.19:54:10.97#ibcon#read 5, iclass 31, count 2 2006.257.19:54:10.97#ibcon#about to read 6, iclass 31, count 2 2006.257.19:54:10.97#ibcon#read 6, iclass 31, count 2 2006.257.19:54:10.97#ibcon#end of sib2, iclass 31, count 2 2006.257.19:54:10.97#ibcon#*after write, iclass 31, count 2 2006.257.19:54:10.97#ibcon#*before return 0, iclass 31, count 2 2006.257.19:54:10.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:10.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.19:54:10.97#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.19:54:10.97#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:10.97#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:11.09#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:11.09#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:11.09#ibcon#enter wrdev, iclass 31, count 0 2006.257.19:54:11.09#ibcon#first serial, iclass 31, count 0 2006.257.19:54:11.09#ibcon#enter sib2, iclass 31, count 0 2006.257.19:54:11.09#ibcon#flushed, iclass 31, count 0 2006.257.19:54:11.09#ibcon#about to write, iclass 31, count 0 2006.257.19:54:11.09#ibcon#wrote, iclass 31, count 0 2006.257.19:54:11.09#ibcon#about to read 3, iclass 31, count 0 2006.257.19:54:11.11#ibcon#read 3, iclass 31, count 0 2006.257.19:54:11.11#ibcon#about to read 4, iclass 31, count 0 2006.257.19:54:11.11#ibcon#read 4, iclass 31, count 0 2006.257.19:54:11.11#ibcon#about to read 5, iclass 31, count 0 2006.257.19:54:11.11#ibcon#read 5, iclass 31, count 0 2006.257.19:54:11.11#ibcon#about to read 6, iclass 31, count 0 2006.257.19:54:11.11#ibcon#read 6, iclass 31, count 0 2006.257.19:54:11.11#ibcon#end of sib2, iclass 31, count 0 2006.257.19:54:11.11#ibcon#*mode == 0, iclass 31, count 0 2006.257.19:54:11.11#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.19:54:11.11#ibcon#[27=USB\r\n] 2006.257.19:54:11.11#ibcon#*before write, iclass 31, count 0 2006.257.19:54:11.11#ibcon#enter sib2, iclass 31, count 0 2006.257.19:54:11.11#ibcon#flushed, iclass 31, count 0 2006.257.19:54:11.11#ibcon#about to write, iclass 31, count 0 2006.257.19:54:11.11#ibcon#wrote, iclass 31, count 0 2006.257.19:54:11.11#ibcon#about to read 3, iclass 31, count 0 2006.257.19:54:11.14#ibcon#read 3, iclass 31, count 0 2006.257.19:54:11.14#ibcon#about to read 4, iclass 31, count 0 2006.257.19:54:11.14#ibcon#read 4, iclass 31, count 0 2006.257.19:54:11.14#ibcon#about to read 5, iclass 31, count 0 2006.257.19:54:11.14#ibcon#read 5, iclass 31, count 0 2006.257.19:54:11.14#ibcon#about to read 6, iclass 31, count 0 2006.257.19:54:11.14#ibcon#read 6, iclass 31, count 0 2006.257.19:54:11.14#ibcon#end of sib2, iclass 31, count 0 2006.257.19:54:11.14#ibcon#*after write, iclass 31, count 0 2006.257.19:54:11.14#ibcon#*before return 0, iclass 31, count 0 2006.257.19:54:11.14#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:11.14#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.19:54:11.14#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.19:54:11.14#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.19:54:11.14$vck44/vblo=7,734.99 2006.257.19:54:11.14#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.19:54:11.14#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.19:54:11.14#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:11.14#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:11.14#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:11.14#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:11.14#ibcon#enter wrdev, iclass 33, count 0 2006.257.19:54:11.14#ibcon#first serial, iclass 33, count 0 2006.257.19:54:11.14#ibcon#enter sib2, iclass 33, count 0 2006.257.19:54:11.14#ibcon#flushed, iclass 33, count 0 2006.257.19:54:11.14#ibcon#about to write, iclass 33, count 0 2006.257.19:54:11.14#ibcon#wrote, iclass 33, count 0 2006.257.19:54:11.14#ibcon#about to read 3, iclass 33, count 0 2006.257.19:54:11.16#ibcon#read 3, iclass 33, count 0 2006.257.19:54:11.16#ibcon#about to read 4, iclass 33, count 0 2006.257.19:54:11.16#ibcon#read 4, iclass 33, count 0 2006.257.19:54:11.16#ibcon#about to read 5, iclass 33, count 0 2006.257.19:54:11.16#ibcon#read 5, iclass 33, count 0 2006.257.19:54:11.16#ibcon#about to read 6, iclass 33, count 0 2006.257.19:54:11.16#ibcon#read 6, iclass 33, count 0 2006.257.19:54:11.16#ibcon#end of sib2, iclass 33, count 0 2006.257.19:54:11.16#ibcon#*mode == 0, iclass 33, count 0 2006.257.19:54:11.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.19:54:11.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.19:54:11.16#ibcon#*before write, iclass 33, count 0 2006.257.19:54:11.16#ibcon#enter sib2, iclass 33, count 0 2006.257.19:54:11.16#ibcon#flushed, iclass 33, count 0 2006.257.19:54:11.16#ibcon#about to write, iclass 33, count 0 2006.257.19:54:11.16#ibcon#wrote, iclass 33, count 0 2006.257.19:54:11.16#ibcon#about to read 3, iclass 33, count 0 2006.257.19:54:11.20#ibcon#read 3, iclass 33, count 0 2006.257.19:54:11.20#ibcon#about to read 4, iclass 33, count 0 2006.257.19:54:11.20#ibcon#read 4, iclass 33, count 0 2006.257.19:54:11.20#ibcon#about to read 5, iclass 33, count 0 2006.257.19:54:11.20#ibcon#read 5, iclass 33, count 0 2006.257.19:54:11.20#ibcon#about to read 6, iclass 33, count 0 2006.257.19:54:11.20#ibcon#read 6, iclass 33, count 0 2006.257.19:54:11.20#ibcon#end of sib2, iclass 33, count 0 2006.257.19:54:11.20#ibcon#*after write, iclass 33, count 0 2006.257.19:54:11.20#ibcon#*before return 0, iclass 33, count 0 2006.257.19:54:11.20#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:11.20#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.19:54:11.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.19:54:11.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.19:54:11.20$vck44/vb=7,4 2006.257.19:54:11.20#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.19:54:11.20#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.19:54:11.20#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:11.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:11.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:11.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:11.26#ibcon#enter wrdev, iclass 35, count 2 2006.257.19:54:11.26#ibcon#first serial, iclass 35, count 2 2006.257.19:54:11.26#ibcon#enter sib2, iclass 35, count 2 2006.257.19:54:11.26#ibcon#flushed, iclass 35, count 2 2006.257.19:54:11.26#ibcon#about to write, iclass 35, count 2 2006.257.19:54:11.26#ibcon#wrote, iclass 35, count 2 2006.257.19:54:11.26#ibcon#about to read 3, iclass 35, count 2 2006.257.19:54:11.28#ibcon#read 3, iclass 35, count 2 2006.257.19:54:11.28#ibcon#about to read 4, iclass 35, count 2 2006.257.19:54:11.28#ibcon#read 4, iclass 35, count 2 2006.257.19:54:11.28#ibcon#about to read 5, iclass 35, count 2 2006.257.19:54:11.28#ibcon#read 5, iclass 35, count 2 2006.257.19:54:11.28#ibcon#about to read 6, iclass 35, count 2 2006.257.19:54:11.28#ibcon#read 6, iclass 35, count 2 2006.257.19:54:11.28#ibcon#end of sib2, iclass 35, count 2 2006.257.19:54:11.28#ibcon#*mode == 0, iclass 35, count 2 2006.257.19:54:11.28#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.19:54:11.28#ibcon#[27=AT07-04\r\n] 2006.257.19:54:11.28#ibcon#*before write, iclass 35, count 2 2006.257.19:54:11.28#ibcon#enter sib2, iclass 35, count 2 2006.257.19:54:11.28#ibcon#flushed, iclass 35, count 2 2006.257.19:54:11.28#ibcon#about to write, iclass 35, count 2 2006.257.19:54:11.28#ibcon#wrote, iclass 35, count 2 2006.257.19:54:11.28#ibcon#about to read 3, iclass 35, count 2 2006.257.19:54:11.31#ibcon#read 3, iclass 35, count 2 2006.257.19:54:11.31#ibcon#about to read 4, iclass 35, count 2 2006.257.19:54:11.31#ibcon#read 4, iclass 35, count 2 2006.257.19:54:11.31#ibcon#about to read 5, iclass 35, count 2 2006.257.19:54:11.31#ibcon#read 5, iclass 35, count 2 2006.257.19:54:11.31#ibcon#about to read 6, iclass 35, count 2 2006.257.19:54:11.31#ibcon#read 6, iclass 35, count 2 2006.257.19:54:11.31#ibcon#end of sib2, iclass 35, count 2 2006.257.19:54:11.31#ibcon#*after write, iclass 35, count 2 2006.257.19:54:11.31#ibcon#*before return 0, iclass 35, count 2 2006.257.19:54:11.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:11.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.19:54:11.31#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.19:54:11.31#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:11.31#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:11.43#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:11.43#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:11.43#ibcon#enter wrdev, iclass 35, count 0 2006.257.19:54:11.43#ibcon#first serial, iclass 35, count 0 2006.257.19:54:11.43#ibcon#enter sib2, iclass 35, count 0 2006.257.19:54:11.43#ibcon#flushed, iclass 35, count 0 2006.257.19:54:11.43#ibcon#about to write, iclass 35, count 0 2006.257.19:54:11.43#ibcon#wrote, iclass 35, count 0 2006.257.19:54:11.43#ibcon#about to read 3, iclass 35, count 0 2006.257.19:54:11.45#ibcon#read 3, iclass 35, count 0 2006.257.19:54:11.45#ibcon#about to read 4, iclass 35, count 0 2006.257.19:54:11.45#ibcon#read 4, iclass 35, count 0 2006.257.19:54:11.45#ibcon#about to read 5, iclass 35, count 0 2006.257.19:54:11.45#ibcon#read 5, iclass 35, count 0 2006.257.19:54:11.45#ibcon#about to read 6, iclass 35, count 0 2006.257.19:54:11.45#ibcon#read 6, iclass 35, count 0 2006.257.19:54:11.45#ibcon#end of sib2, iclass 35, count 0 2006.257.19:54:11.45#ibcon#*mode == 0, iclass 35, count 0 2006.257.19:54:11.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.19:54:11.45#ibcon#[27=USB\r\n] 2006.257.19:54:11.45#ibcon#*before write, iclass 35, count 0 2006.257.19:54:11.45#ibcon#enter sib2, iclass 35, count 0 2006.257.19:54:11.45#ibcon#flushed, iclass 35, count 0 2006.257.19:54:11.45#ibcon#about to write, iclass 35, count 0 2006.257.19:54:11.45#ibcon#wrote, iclass 35, count 0 2006.257.19:54:11.45#ibcon#about to read 3, iclass 35, count 0 2006.257.19:54:11.48#ibcon#read 3, iclass 35, count 0 2006.257.19:54:11.48#ibcon#about to read 4, iclass 35, count 0 2006.257.19:54:11.48#ibcon#read 4, iclass 35, count 0 2006.257.19:54:11.48#ibcon#about to read 5, iclass 35, count 0 2006.257.19:54:11.48#ibcon#read 5, iclass 35, count 0 2006.257.19:54:11.48#ibcon#about to read 6, iclass 35, count 0 2006.257.19:54:11.48#ibcon#read 6, iclass 35, count 0 2006.257.19:54:11.48#ibcon#end of sib2, iclass 35, count 0 2006.257.19:54:11.48#ibcon#*after write, iclass 35, count 0 2006.257.19:54:11.48#ibcon#*before return 0, iclass 35, count 0 2006.257.19:54:11.48#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:11.48#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.19:54:11.48#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.19:54:11.48#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.19:54:11.48$vck44/vblo=8,744.99 2006.257.19:54:11.48#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.19:54:11.48#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.19:54:11.48#ibcon#ireg 17 cls_cnt 0 2006.257.19:54:11.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:11.48#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:11.48#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:11.48#ibcon#enter wrdev, iclass 37, count 0 2006.257.19:54:11.48#ibcon#first serial, iclass 37, count 0 2006.257.19:54:11.48#ibcon#enter sib2, iclass 37, count 0 2006.257.19:54:11.48#ibcon#flushed, iclass 37, count 0 2006.257.19:54:11.48#ibcon#about to write, iclass 37, count 0 2006.257.19:54:11.48#ibcon#wrote, iclass 37, count 0 2006.257.19:54:11.48#ibcon#about to read 3, iclass 37, count 0 2006.257.19:54:11.50#ibcon#read 3, iclass 37, count 0 2006.257.19:54:11.50#ibcon#about to read 4, iclass 37, count 0 2006.257.19:54:11.50#ibcon#read 4, iclass 37, count 0 2006.257.19:54:11.50#ibcon#about to read 5, iclass 37, count 0 2006.257.19:54:11.50#ibcon#read 5, iclass 37, count 0 2006.257.19:54:11.50#ibcon#about to read 6, iclass 37, count 0 2006.257.19:54:11.50#ibcon#read 6, iclass 37, count 0 2006.257.19:54:11.50#ibcon#end of sib2, iclass 37, count 0 2006.257.19:54:11.50#ibcon#*mode == 0, iclass 37, count 0 2006.257.19:54:11.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.19:54:11.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.19:54:11.50#ibcon#*before write, iclass 37, count 0 2006.257.19:54:11.50#ibcon#enter sib2, iclass 37, count 0 2006.257.19:54:11.50#ibcon#flushed, iclass 37, count 0 2006.257.19:54:11.50#ibcon#about to write, iclass 37, count 0 2006.257.19:54:11.50#ibcon#wrote, iclass 37, count 0 2006.257.19:54:11.50#ibcon#about to read 3, iclass 37, count 0 2006.257.19:54:11.54#ibcon#read 3, iclass 37, count 0 2006.257.19:54:11.54#ibcon#about to read 4, iclass 37, count 0 2006.257.19:54:11.54#ibcon#read 4, iclass 37, count 0 2006.257.19:54:11.54#ibcon#about to read 5, iclass 37, count 0 2006.257.19:54:11.54#ibcon#read 5, iclass 37, count 0 2006.257.19:54:11.54#ibcon#about to read 6, iclass 37, count 0 2006.257.19:54:11.54#ibcon#read 6, iclass 37, count 0 2006.257.19:54:11.54#ibcon#end of sib2, iclass 37, count 0 2006.257.19:54:11.54#ibcon#*after write, iclass 37, count 0 2006.257.19:54:11.54#ibcon#*before return 0, iclass 37, count 0 2006.257.19:54:11.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:11.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.19:54:11.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.19:54:11.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.19:54:11.54$vck44/vb=8,4 2006.257.19:54:11.54#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.19:54:11.54#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.19:54:11.54#ibcon#ireg 11 cls_cnt 2 2006.257.19:54:11.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:11.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:11.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:11.60#ibcon#enter wrdev, iclass 39, count 2 2006.257.19:54:11.60#ibcon#first serial, iclass 39, count 2 2006.257.19:54:11.60#ibcon#enter sib2, iclass 39, count 2 2006.257.19:54:11.60#ibcon#flushed, iclass 39, count 2 2006.257.19:54:11.60#ibcon#about to write, iclass 39, count 2 2006.257.19:54:11.60#ibcon#wrote, iclass 39, count 2 2006.257.19:54:11.60#ibcon#about to read 3, iclass 39, count 2 2006.257.19:54:11.62#ibcon#read 3, iclass 39, count 2 2006.257.19:54:11.62#ibcon#about to read 4, iclass 39, count 2 2006.257.19:54:11.62#ibcon#read 4, iclass 39, count 2 2006.257.19:54:11.62#ibcon#about to read 5, iclass 39, count 2 2006.257.19:54:11.62#ibcon#read 5, iclass 39, count 2 2006.257.19:54:11.62#ibcon#about to read 6, iclass 39, count 2 2006.257.19:54:11.62#ibcon#read 6, iclass 39, count 2 2006.257.19:54:11.62#ibcon#end of sib2, iclass 39, count 2 2006.257.19:54:11.62#ibcon#*mode == 0, iclass 39, count 2 2006.257.19:54:11.62#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.19:54:11.62#ibcon#[27=AT08-04\r\n] 2006.257.19:54:11.62#ibcon#*before write, iclass 39, count 2 2006.257.19:54:11.62#ibcon#enter sib2, iclass 39, count 2 2006.257.19:54:11.62#ibcon#flushed, iclass 39, count 2 2006.257.19:54:11.62#ibcon#about to write, iclass 39, count 2 2006.257.19:54:11.62#ibcon#wrote, iclass 39, count 2 2006.257.19:54:11.62#ibcon#about to read 3, iclass 39, count 2 2006.257.19:54:11.65#ibcon#read 3, iclass 39, count 2 2006.257.19:54:11.65#ibcon#about to read 4, iclass 39, count 2 2006.257.19:54:11.65#ibcon#read 4, iclass 39, count 2 2006.257.19:54:11.65#ibcon#about to read 5, iclass 39, count 2 2006.257.19:54:11.65#ibcon#read 5, iclass 39, count 2 2006.257.19:54:11.65#ibcon#about to read 6, iclass 39, count 2 2006.257.19:54:11.65#ibcon#read 6, iclass 39, count 2 2006.257.19:54:11.65#ibcon#end of sib2, iclass 39, count 2 2006.257.19:54:11.65#ibcon#*after write, iclass 39, count 2 2006.257.19:54:11.65#ibcon#*before return 0, iclass 39, count 2 2006.257.19:54:11.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:11.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.19:54:11.65#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.19:54:11.65#ibcon#ireg 7 cls_cnt 0 2006.257.19:54:11.65#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:11.77#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:11.77#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:11.77#ibcon#enter wrdev, iclass 39, count 0 2006.257.19:54:11.77#ibcon#first serial, iclass 39, count 0 2006.257.19:54:11.77#ibcon#enter sib2, iclass 39, count 0 2006.257.19:54:11.77#ibcon#flushed, iclass 39, count 0 2006.257.19:54:11.77#ibcon#about to write, iclass 39, count 0 2006.257.19:54:11.77#ibcon#wrote, iclass 39, count 0 2006.257.19:54:11.77#ibcon#about to read 3, iclass 39, count 0 2006.257.19:54:11.79#ibcon#read 3, iclass 39, count 0 2006.257.19:54:11.79#ibcon#about to read 4, iclass 39, count 0 2006.257.19:54:11.79#ibcon#read 4, iclass 39, count 0 2006.257.19:54:11.79#ibcon#about to read 5, iclass 39, count 0 2006.257.19:54:11.79#ibcon#read 5, iclass 39, count 0 2006.257.19:54:11.79#ibcon#about to read 6, iclass 39, count 0 2006.257.19:54:11.79#ibcon#read 6, iclass 39, count 0 2006.257.19:54:11.79#ibcon#end of sib2, iclass 39, count 0 2006.257.19:54:11.79#ibcon#*mode == 0, iclass 39, count 0 2006.257.19:54:11.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.19:54:11.79#ibcon#[27=USB\r\n] 2006.257.19:54:11.79#ibcon#*before write, iclass 39, count 0 2006.257.19:54:11.79#ibcon#enter sib2, iclass 39, count 0 2006.257.19:54:11.79#ibcon#flushed, iclass 39, count 0 2006.257.19:54:11.79#ibcon#about to write, iclass 39, count 0 2006.257.19:54:11.79#ibcon#wrote, iclass 39, count 0 2006.257.19:54:11.79#ibcon#about to read 3, iclass 39, count 0 2006.257.19:54:11.82#ibcon#read 3, iclass 39, count 0 2006.257.19:54:11.82#ibcon#about to read 4, iclass 39, count 0 2006.257.19:54:11.82#ibcon#read 4, iclass 39, count 0 2006.257.19:54:11.82#ibcon#about to read 5, iclass 39, count 0 2006.257.19:54:11.82#ibcon#read 5, iclass 39, count 0 2006.257.19:54:11.82#ibcon#about to read 6, iclass 39, count 0 2006.257.19:54:11.82#ibcon#read 6, iclass 39, count 0 2006.257.19:54:11.82#ibcon#end of sib2, iclass 39, count 0 2006.257.19:54:11.82#ibcon#*after write, iclass 39, count 0 2006.257.19:54:11.82#ibcon#*before return 0, iclass 39, count 0 2006.257.19:54:11.82#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:11.82#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.19:54:11.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.19:54:11.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.19:54:11.82$vck44/vabw=wide 2006.257.19:54:11.82#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.19:54:11.82#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.19:54:11.82#ibcon#ireg 8 cls_cnt 0 2006.257.19:54:11.82#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:11.82#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:11.82#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:11.82#ibcon#enter wrdev, iclass 3, count 0 2006.257.19:54:11.82#ibcon#first serial, iclass 3, count 0 2006.257.19:54:11.82#ibcon#enter sib2, iclass 3, count 0 2006.257.19:54:11.82#ibcon#flushed, iclass 3, count 0 2006.257.19:54:11.82#ibcon#about to write, iclass 3, count 0 2006.257.19:54:11.82#ibcon#wrote, iclass 3, count 0 2006.257.19:54:11.82#ibcon#about to read 3, iclass 3, count 0 2006.257.19:54:11.84#ibcon#read 3, iclass 3, count 0 2006.257.19:54:11.84#ibcon#about to read 4, iclass 3, count 0 2006.257.19:54:11.84#ibcon#read 4, iclass 3, count 0 2006.257.19:54:11.84#ibcon#about to read 5, iclass 3, count 0 2006.257.19:54:11.84#ibcon#read 5, iclass 3, count 0 2006.257.19:54:11.84#ibcon#about to read 6, iclass 3, count 0 2006.257.19:54:11.84#ibcon#read 6, iclass 3, count 0 2006.257.19:54:11.84#ibcon#end of sib2, iclass 3, count 0 2006.257.19:54:11.84#ibcon#*mode == 0, iclass 3, count 0 2006.257.19:54:11.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.19:54:11.84#ibcon#[25=BW32\r\n] 2006.257.19:54:11.84#ibcon#*before write, iclass 3, count 0 2006.257.19:54:11.84#ibcon#enter sib2, iclass 3, count 0 2006.257.19:54:11.84#ibcon#flushed, iclass 3, count 0 2006.257.19:54:11.84#ibcon#about to write, iclass 3, count 0 2006.257.19:54:11.84#ibcon#wrote, iclass 3, count 0 2006.257.19:54:11.84#ibcon#about to read 3, iclass 3, count 0 2006.257.19:54:11.87#ibcon#read 3, iclass 3, count 0 2006.257.19:54:11.87#ibcon#about to read 4, iclass 3, count 0 2006.257.19:54:11.87#ibcon#read 4, iclass 3, count 0 2006.257.19:54:11.87#ibcon#about to read 5, iclass 3, count 0 2006.257.19:54:11.87#ibcon#read 5, iclass 3, count 0 2006.257.19:54:11.87#ibcon#about to read 6, iclass 3, count 0 2006.257.19:54:11.87#ibcon#read 6, iclass 3, count 0 2006.257.19:54:11.87#ibcon#end of sib2, iclass 3, count 0 2006.257.19:54:11.87#ibcon#*after write, iclass 3, count 0 2006.257.19:54:11.87#ibcon#*before return 0, iclass 3, count 0 2006.257.19:54:11.87#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:11.87#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.19:54:11.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.19:54:11.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.19:54:11.87$vck44/vbbw=wide 2006.257.19:54:11.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.19:54:11.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.19:54:11.87#ibcon#ireg 8 cls_cnt 0 2006.257.19:54:11.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:54:11.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:54:11.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:54:11.94#ibcon#enter wrdev, iclass 5, count 0 2006.257.19:54:11.94#ibcon#first serial, iclass 5, count 0 2006.257.19:54:11.94#ibcon#enter sib2, iclass 5, count 0 2006.257.19:54:11.94#ibcon#flushed, iclass 5, count 0 2006.257.19:54:11.94#ibcon#about to write, iclass 5, count 0 2006.257.19:54:11.94#ibcon#wrote, iclass 5, count 0 2006.257.19:54:11.94#ibcon#about to read 3, iclass 5, count 0 2006.257.19:54:11.96#ibcon#read 3, iclass 5, count 0 2006.257.19:54:11.96#ibcon#about to read 4, iclass 5, count 0 2006.257.19:54:11.96#ibcon#read 4, iclass 5, count 0 2006.257.19:54:11.96#ibcon#about to read 5, iclass 5, count 0 2006.257.19:54:11.96#ibcon#read 5, iclass 5, count 0 2006.257.19:54:11.96#ibcon#about to read 6, iclass 5, count 0 2006.257.19:54:11.96#ibcon#read 6, iclass 5, count 0 2006.257.19:54:11.96#ibcon#end of sib2, iclass 5, count 0 2006.257.19:54:11.96#ibcon#*mode == 0, iclass 5, count 0 2006.257.19:54:11.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.19:54:11.96#ibcon#[27=BW32\r\n] 2006.257.19:54:11.96#ibcon#*before write, iclass 5, count 0 2006.257.19:54:11.96#ibcon#enter sib2, iclass 5, count 0 2006.257.19:54:11.96#ibcon#flushed, iclass 5, count 0 2006.257.19:54:11.96#ibcon#about to write, iclass 5, count 0 2006.257.19:54:11.96#ibcon#wrote, iclass 5, count 0 2006.257.19:54:11.96#ibcon#about to read 3, iclass 5, count 0 2006.257.19:54:11.99#ibcon#read 3, iclass 5, count 0 2006.257.19:54:11.99#ibcon#about to read 4, iclass 5, count 0 2006.257.19:54:11.99#ibcon#read 4, iclass 5, count 0 2006.257.19:54:11.99#ibcon#about to read 5, iclass 5, count 0 2006.257.19:54:11.99#ibcon#read 5, iclass 5, count 0 2006.257.19:54:11.99#ibcon#about to read 6, iclass 5, count 0 2006.257.19:54:11.99#ibcon#read 6, iclass 5, count 0 2006.257.19:54:11.99#ibcon#end of sib2, iclass 5, count 0 2006.257.19:54:11.99#ibcon#*after write, iclass 5, count 0 2006.257.19:54:11.99#ibcon#*before return 0, iclass 5, count 0 2006.257.19:54:11.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:54:11.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.19:54:11.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.19:54:11.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.19:54:11.99$setupk4/ifdk4 2006.257.19:54:11.99$ifdk4/lo= 2006.257.19:54:11.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.19:54:12.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.19:54:12.00$ifdk4/patch= 2006.257.19:54:12.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.19:54:12.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.19:54:12.00$setupk4/!*+20s 2006.257.19:54:19.80#abcon#<5=/14 1.2 4.3 17.52 961014.6\r\n> 2006.257.19:54:19.82#abcon#{5=INTERFACE CLEAR} 2006.257.19:54:19.88#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:54:26.51$setupk4/"tpicd 2006.257.19:54:26.51$setupk4/echo=off 2006.257.19:54:26.51$setupk4/xlog=off 2006.257.19:54:26.51:!2006.257.19:56:24 2006.257.19:54:30.14#trakl#Source acquired 2006.257.19:54:32.14#flagr#flagr/antenna,acquired 2006.257.19:56:24.00:preob 2006.257.19:56:24.14/onsource/TRACKING 2006.257.19:56:24.14:!2006.257.19:56:34 2006.257.19:56:34.00:"tape 2006.257.19:56:34.00:"st=record 2006.257.19:56:34.00:data_valid=on 2006.257.19:56:34.00:midob 2006.257.19:56:35.14/onsource/TRACKING 2006.257.19:56:35.14/wx/17.51,1014.7,96 2006.257.19:56:35.32/cable/+6.4848E-03 2006.257.19:56:36.41/va/01,08,usb,yes,31,33 2006.257.19:56:36.41/va/02,07,usb,yes,34,34 2006.257.19:56:36.41/va/03,08,usb,yes,30,32 2006.257.19:56:36.41/va/04,07,usb,yes,35,36 2006.257.19:56:36.41/va/05,04,usb,yes,31,32 2006.257.19:56:36.41/va/06,04,usb,yes,35,34 2006.257.19:56:36.41/va/07,04,usb,yes,36,36 2006.257.19:56:36.41/va/08,04,usb,yes,30,36 2006.257.19:56:36.64/valo/01,524.99,yes,locked 2006.257.19:56:36.64/valo/02,534.99,yes,locked 2006.257.19:56:36.64/valo/03,564.99,yes,locked 2006.257.19:56:36.64/valo/04,624.99,yes,locked 2006.257.19:56:36.64/valo/05,734.99,yes,locked 2006.257.19:56:36.64/valo/06,814.99,yes,locked 2006.257.19:56:36.64/valo/07,864.99,yes,locked 2006.257.19:56:36.64/valo/08,884.99,yes,locked 2006.257.19:56:37.73/vb/01,04,usb,yes,30,28 2006.257.19:56:37.73/vb/02,05,usb,yes,28,28 2006.257.19:56:37.73/vb/03,04,usb,yes,29,32 2006.257.19:56:37.73/vb/04,05,usb,yes,30,29 2006.257.19:56:37.73/vb/05,04,usb,yes,26,29 2006.257.19:56:37.73/vb/06,04,usb,yes,31,27 2006.257.19:56:37.73/vb/07,04,usb,yes,30,30 2006.257.19:56:37.73/vb/08,04,usb,yes,28,31 2006.257.19:56:37.97/vblo/01,629.99,yes,locked 2006.257.19:56:37.97/vblo/02,634.99,yes,locked 2006.257.19:56:37.97/vblo/03,649.99,yes,locked 2006.257.19:56:37.97/vblo/04,679.99,yes,locked 2006.257.19:56:37.97/vblo/05,709.99,yes,locked 2006.257.19:56:37.97/vblo/06,719.99,yes,locked 2006.257.19:56:37.97/vblo/07,734.99,yes,locked 2006.257.19:56:37.97/vblo/08,744.99,yes,locked 2006.257.19:56:38.12/vabw/8 2006.257.19:56:38.27/vbbw/8 2006.257.19:56:38.38/xfe/off,on,16.0 2006.257.19:56:38.75/ifatt/23,28,28,28 2006.257.19:56:39.07/fmout-gps/S +4.52E-07 2006.257.19:56:39.11:!2006.257.19:57:24 2006.257.19:57:24.01:data_valid=off 2006.257.19:57:24.01:"et 2006.257.19:57:24.01:!+3s 2006.257.19:57:27.02:"tape 2006.257.19:57:27.02:postob 2006.257.19:57:27.15/cable/+6.4848E-03 2006.257.19:57:27.15/wx/17.50,1014.7,96 2006.257.19:57:27.21/fmout-gps/S +4.53E-07 2006.257.19:57:27.21:scan_name=257-2000,jd0609,40 2006.257.19:57:27.21:source=0537-441,053850.36,-440508.9,2000.0,ccw 2006.257.19:57:28.14#flagr#flagr/antenna,new-source 2006.257.19:57:28.14:checkk5 2006.257.19:57:28.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.19:57:28.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.19:57:29.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.19:57:29.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.19:57:29.83/chk_obsdata//k5ts1/T2571956??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.19:57:30.17/chk_obsdata//k5ts2/T2571956??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.19:57:30.50/chk_obsdata//k5ts3/T2571956??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.19:57:30.83/chk_obsdata//k5ts4/T2571956??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.19:57:31.48/k5log//k5ts1_log_newline 2006.257.19:57:32.14/k5log//k5ts2_log_newline 2006.257.19:57:32.79/k5log//k5ts3_log_newline 2006.257.19:57:33.44/k5log//k5ts4_log_newline 2006.257.19:57:33.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.19:57:33.46:setupk4=1 2006.257.19:57:33.46$setupk4/echo=on 2006.257.19:57:33.46$setupk4/pcalon 2006.257.19:57:33.46$pcalon/"no phase cal control is implemented here 2006.257.19:57:33.46$setupk4/"tpicd=stop 2006.257.19:57:33.46$setupk4/"rec=synch_on 2006.257.19:57:33.46$setupk4/"rec_mode=128 2006.257.19:57:33.46$setupk4/!* 2006.257.19:57:33.46$setupk4/recpk4 2006.257.19:57:33.46$recpk4/recpatch= 2006.257.19:57:33.46$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.19:57:33.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.19:57:33.47$setupk4/vck44 2006.257.19:57:33.47$vck44/valo=1,524.99 2006.257.19:57:33.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.19:57:33.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.19:57:33.47#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:33.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:33.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:33.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:33.47#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:57:33.47#ibcon#first serial, iclass 20, count 0 2006.257.19:57:33.47#ibcon#enter sib2, iclass 20, count 0 2006.257.19:57:33.47#ibcon#flushed, iclass 20, count 0 2006.257.19:57:33.47#ibcon#about to write, iclass 20, count 0 2006.257.19:57:33.47#ibcon#wrote, iclass 20, count 0 2006.257.19:57:33.47#ibcon#about to read 3, iclass 20, count 0 2006.257.19:57:33.48#ibcon#read 3, iclass 20, count 0 2006.257.19:57:33.48#ibcon#about to read 4, iclass 20, count 0 2006.257.19:57:33.48#ibcon#read 4, iclass 20, count 0 2006.257.19:57:33.48#ibcon#about to read 5, iclass 20, count 0 2006.257.19:57:33.48#ibcon#read 5, iclass 20, count 0 2006.257.19:57:33.48#ibcon#about to read 6, iclass 20, count 0 2006.257.19:57:33.48#ibcon#read 6, iclass 20, count 0 2006.257.19:57:33.48#ibcon#end of sib2, iclass 20, count 0 2006.257.19:57:33.48#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:57:33.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:57:33.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.19:57:33.48#ibcon#*before write, iclass 20, count 0 2006.257.19:57:33.48#ibcon#enter sib2, iclass 20, count 0 2006.257.19:57:33.48#ibcon#flushed, iclass 20, count 0 2006.257.19:57:33.48#ibcon#about to write, iclass 20, count 0 2006.257.19:57:33.48#ibcon#wrote, iclass 20, count 0 2006.257.19:57:33.48#ibcon#about to read 3, iclass 20, count 0 2006.257.19:57:33.53#ibcon#read 3, iclass 20, count 0 2006.257.19:57:33.53#ibcon#about to read 4, iclass 20, count 0 2006.257.19:57:33.53#ibcon#read 4, iclass 20, count 0 2006.257.19:57:33.53#ibcon#about to read 5, iclass 20, count 0 2006.257.19:57:33.53#ibcon#read 5, iclass 20, count 0 2006.257.19:57:33.53#ibcon#about to read 6, iclass 20, count 0 2006.257.19:57:33.53#ibcon#read 6, iclass 20, count 0 2006.257.19:57:33.53#ibcon#end of sib2, iclass 20, count 0 2006.257.19:57:33.53#ibcon#*after write, iclass 20, count 0 2006.257.19:57:33.53#ibcon#*before return 0, iclass 20, count 0 2006.257.19:57:33.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:33.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:33.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:57:33.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:57:33.53$vck44/va=1,8 2006.257.19:57:33.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.19:57:33.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.19:57:33.53#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:33.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:33.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:33.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:33.53#ibcon#enter wrdev, iclass 22, count 2 2006.257.19:57:33.53#ibcon#first serial, iclass 22, count 2 2006.257.19:57:33.53#ibcon#enter sib2, iclass 22, count 2 2006.257.19:57:33.53#ibcon#flushed, iclass 22, count 2 2006.257.19:57:33.53#ibcon#about to write, iclass 22, count 2 2006.257.19:57:33.53#ibcon#wrote, iclass 22, count 2 2006.257.19:57:33.53#ibcon#about to read 3, iclass 22, count 2 2006.257.19:57:33.55#ibcon#read 3, iclass 22, count 2 2006.257.19:57:33.55#ibcon#about to read 4, iclass 22, count 2 2006.257.19:57:33.55#ibcon#read 4, iclass 22, count 2 2006.257.19:57:33.55#ibcon#about to read 5, iclass 22, count 2 2006.257.19:57:33.55#ibcon#read 5, iclass 22, count 2 2006.257.19:57:33.55#ibcon#about to read 6, iclass 22, count 2 2006.257.19:57:33.55#ibcon#read 6, iclass 22, count 2 2006.257.19:57:33.55#ibcon#end of sib2, iclass 22, count 2 2006.257.19:57:33.55#ibcon#*mode == 0, iclass 22, count 2 2006.257.19:57:33.55#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.19:57:33.55#ibcon#[25=AT01-08\r\n] 2006.257.19:57:33.55#ibcon#*before write, iclass 22, count 2 2006.257.19:57:33.55#ibcon#enter sib2, iclass 22, count 2 2006.257.19:57:33.55#ibcon#flushed, iclass 22, count 2 2006.257.19:57:33.55#ibcon#about to write, iclass 22, count 2 2006.257.19:57:33.55#ibcon#wrote, iclass 22, count 2 2006.257.19:57:33.55#ibcon#about to read 3, iclass 22, count 2 2006.257.19:57:33.58#ibcon#read 3, iclass 22, count 2 2006.257.19:57:33.58#ibcon#about to read 4, iclass 22, count 2 2006.257.19:57:33.58#ibcon#read 4, iclass 22, count 2 2006.257.19:57:33.58#ibcon#about to read 5, iclass 22, count 2 2006.257.19:57:33.58#ibcon#read 5, iclass 22, count 2 2006.257.19:57:33.58#ibcon#about to read 6, iclass 22, count 2 2006.257.19:57:33.58#ibcon#read 6, iclass 22, count 2 2006.257.19:57:33.58#ibcon#end of sib2, iclass 22, count 2 2006.257.19:57:33.58#ibcon#*after write, iclass 22, count 2 2006.257.19:57:33.58#ibcon#*before return 0, iclass 22, count 2 2006.257.19:57:33.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:33.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:33.58#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.19:57:33.58#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:33.58#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:33.70#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:33.70#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:33.70#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:57:33.70#ibcon#first serial, iclass 22, count 0 2006.257.19:57:33.70#ibcon#enter sib2, iclass 22, count 0 2006.257.19:57:33.70#ibcon#flushed, iclass 22, count 0 2006.257.19:57:33.70#ibcon#about to write, iclass 22, count 0 2006.257.19:57:33.70#ibcon#wrote, iclass 22, count 0 2006.257.19:57:33.70#ibcon#about to read 3, iclass 22, count 0 2006.257.19:57:33.72#ibcon#read 3, iclass 22, count 0 2006.257.19:57:33.72#ibcon#about to read 4, iclass 22, count 0 2006.257.19:57:33.72#ibcon#read 4, iclass 22, count 0 2006.257.19:57:33.72#ibcon#about to read 5, iclass 22, count 0 2006.257.19:57:33.72#ibcon#read 5, iclass 22, count 0 2006.257.19:57:33.72#ibcon#about to read 6, iclass 22, count 0 2006.257.19:57:33.72#ibcon#read 6, iclass 22, count 0 2006.257.19:57:33.72#ibcon#end of sib2, iclass 22, count 0 2006.257.19:57:33.72#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:57:33.72#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:57:33.72#ibcon#[25=USB\r\n] 2006.257.19:57:33.72#ibcon#*before write, iclass 22, count 0 2006.257.19:57:33.72#ibcon#enter sib2, iclass 22, count 0 2006.257.19:57:33.72#ibcon#flushed, iclass 22, count 0 2006.257.19:57:33.72#ibcon#about to write, iclass 22, count 0 2006.257.19:57:33.72#ibcon#wrote, iclass 22, count 0 2006.257.19:57:33.72#ibcon#about to read 3, iclass 22, count 0 2006.257.19:57:33.75#ibcon#read 3, iclass 22, count 0 2006.257.19:57:33.75#ibcon#about to read 4, iclass 22, count 0 2006.257.19:57:33.75#ibcon#read 4, iclass 22, count 0 2006.257.19:57:33.75#ibcon#about to read 5, iclass 22, count 0 2006.257.19:57:33.75#ibcon#read 5, iclass 22, count 0 2006.257.19:57:33.75#ibcon#about to read 6, iclass 22, count 0 2006.257.19:57:33.75#ibcon#read 6, iclass 22, count 0 2006.257.19:57:33.75#ibcon#end of sib2, iclass 22, count 0 2006.257.19:57:33.75#ibcon#*after write, iclass 22, count 0 2006.257.19:57:33.75#ibcon#*before return 0, iclass 22, count 0 2006.257.19:57:33.75#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:33.75#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:33.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:57:33.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:57:33.75$vck44/valo=2,534.99 2006.257.19:57:33.75#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.19:57:33.75#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.19:57:33.75#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:33.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:33.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:33.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:33.75#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:57:33.75#ibcon#first serial, iclass 24, count 0 2006.257.19:57:33.75#ibcon#enter sib2, iclass 24, count 0 2006.257.19:57:33.75#ibcon#flushed, iclass 24, count 0 2006.257.19:57:33.75#ibcon#about to write, iclass 24, count 0 2006.257.19:57:33.75#ibcon#wrote, iclass 24, count 0 2006.257.19:57:33.75#ibcon#about to read 3, iclass 24, count 0 2006.257.19:57:33.77#ibcon#read 3, iclass 24, count 0 2006.257.19:57:33.77#ibcon#about to read 4, iclass 24, count 0 2006.257.19:57:33.77#ibcon#read 4, iclass 24, count 0 2006.257.19:57:33.77#ibcon#about to read 5, iclass 24, count 0 2006.257.19:57:33.77#ibcon#read 5, iclass 24, count 0 2006.257.19:57:33.77#ibcon#about to read 6, iclass 24, count 0 2006.257.19:57:33.77#ibcon#read 6, iclass 24, count 0 2006.257.19:57:33.77#ibcon#end of sib2, iclass 24, count 0 2006.257.19:57:33.77#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:57:33.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:57:33.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.19:57:33.77#ibcon#*before write, iclass 24, count 0 2006.257.19:57:33.77#ibcon#enter sib2, iclass 24, count 0 2006.257.19:57:33.77#ibcon#flushed, iclass 24, count 0 2006.257.19:57:33.77#ibcon#about to write, iclass 24, count 0 2006.257.19:57:33.77#ibcon#wrote, iclass 24, count 0 2006.257.19:57:33.77#ibcon#about to read 3, iclass 24, count 0 2006.257.19:57:33.81#ibcon#read 3, iclass 24, count 0 2006.257.19:57:33.81#ibcon#about to read 4, iclass 24, count 0 2006.257.19:57:33.81#ibcon#read 4, iclass 24, count 0 2006.257.19:57:33.81#ibcon#about to read 5, iclass 24, count 0 2006.257.19:57:33.81#ibcon#read 5, iclass 24, count 0 2006.257.19:57:33.81#ibcon#about to read 6, iclass 24, count 0 2006.257.19:57:33.81#ibcon#read 6, iclass 24, count 0 2006.257.19:57:33.81#ibcon#end of sib2, iclass 24, count 0 2006.257.19:57:33.81#ibcon#*after write, iclass 24, count 0 2006.257.19:57:33.81#ibcon#*before return 0, iclass 24, count 0 2006.257.19:57:33.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:33.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:33.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:57:33.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:57:33.81$vck44/va=2,7 2006.257.19:57:33.81#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.19:57:33.81#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.19:57:33.81#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:33.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:33.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:33.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:33.87#ibcon#enter wrdev, iclass 26, count 2 2006.257.19:57:33.87#ibcon#first serial, iclass 26, count 2 2006.257.19:57:33.87#ibcon#enter sib2, iclass 26, count 2 2006.257.19:57:33.87#ibcon#flushed, iclass 26, count 2 2006.257.19:57:33.87#ibcon#about to write, iclass 26, count 2 2006.257.19:57:33.87#ibcon#wrote, iclass 26, count 2 2006.257.19:57:33.87#ibcon#about to read 3, iclass 26, count 2 2006.257.19:57:33.89#ibcon#read 3, iclass 26, count 2 2006.257.19:57:33.89#ibcon#about to read 4, iclass 26, count 2 2006.257.19:57:33.89#ibcon#read 4, iclass 26, count 2 2006.257.19:57:33.89#ibcon#about to read 5, iclass 26, count 2 2006.257.19:57:33.89#ibcon#read 5, iclass 26, count 2 2006.257.19:57:33.89#ibcon#about to read 6, iclass 26, count 2 2006.257.19:57:33.89#ibcon#read 6, iclass 26, count 2 2006.257.19:57:33.89#ibcon#end of sib2, iclass 26, count 2 2006.257.19:57:33.89#ibcon#*mode == 0, iclass 26, count 2 2006.257.19:57:33.89#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.19:57:33.89#ibcon#[25=AT02-07\r\n] 2006.257.19:57:33.89#ibcon#*before write, iclass 26, count 2 2006.257.19:57:33.89#ibcon#enter sib2, iclass 26, count 2 2006.257.19:57:33.89#ibcon#flushed, iclass 26, count 2 2006.257.19:57:33.89#ibcon#about to write, iclass 26, count 2 2006.257.19:57:33.89#ibcon#wrote, iclass 26, count 2 2006.257.19:57:33.89#ibcon#about to read 3, iclass 26, count 2 2006.257.19:57:33.92#ibcon#read 3, iclass 26, count 2 2006.257.19:57:33.92#ibcon#about to read 4, iclass 26, count 2 2006.257.19:57:33.92#ibcon#read 4, iclass 26, count 2 2006.257.19:57:33.92#ibcon#about to read 5, iclass 26, count 2 2006.257.19:57:33.92#ibcon#read 5, iclass 26, count 2 2006.257.19:57:33.92#ibcon#about to read 6, iclass 26, count 2 2006.257.19:57:33.92#ibcon#read 6, iclass 26, count 2 2006.257.19:57:33.92#ibcon#end of sib2, iclass 26, count 2 2006.257.19:57:33.92#ibcon#*after write, iclass 26, count 2 2006.257.19:57:33.92#ibcon#*before return 0, iclass 26, count 2 2006.257.19:57:33.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:33.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:33.92#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.19:57:33.92#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:33.92#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:34.04#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:34.04#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:34.04#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:57:34.04#ibcon#first serial, iclass 26, count 0 2006.257.19:57:34.04#ibcon#enter sib2, iclass 26, count 0 2006.257.19:57:34.04#ibcon#flushed, iclass 26, count 0 2006.257.19:57:34.04#ibcon#about to write, iclass 26, count 0 2006.257.19:57:34.04#ibcon#wrote, iclass 26, count 0 2006.257.19:57:34.04#ibcon#about to read 3, iclass 26, count 0 2006.257.19:57:34.06#ibcon#read 3, iclass 26, count 0 2006.257.19:57:34.06#ibcon#about to read 4, iclass 26, count 0 2006.257.19:57:34.06#ibcon#read 4, iclass 26, count 0 2006.257.19:57:34.06#ibcon#about to read 5, iclass 26, count 0 2006.257.19:57:34.06#ibcon#read 5, iclass 26, count 0 2006.257.19:57:34.06#ibcon#about to read 6, iclass 26, count 0 2006.257.19:57:34.06#ibcon#read 6, iclass 26, count 0 2006.257.19:57:34.06#ibcon#end of sib2, iclass 26, count 0 2006.257.19:57:34.06#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:57:34.06#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:57:34.06#ibcon#[25=USB\r\n] 2006.257.19:57:34.06#ibcon#*before write, iclass 26, count 0 2006.257.19:57:34.06#ibcon#enter sib2, iclass 26, count 0 2006.257.19:57:34.06#ibcon#flushed, iclass 26, count 0 2006.257.19:57:34.06#ibcon#about to write, iclass 26, count 0 2006.257.19:57:34.06#ibcon#wrote, iclass 26, count 0 2006.257.19:57:34.06#ibcon#about to read 3, iclass 26, count 0 2006.257.19:57:34.09#ibcon#read 3, iclass 26, count 0 2006.257.19:57:34.09#ibcon#about to read 4, iclass 26, count 0 2006.257.19:57:34.09#ibcon#read 4, iclass 26, count 0 2006.257.19:57:34.09#ibcon#about to read 5, iclass 26, count 0 2006.257.19:57:34.09#ibcon#read 5, iclass 26, count 0 2006.257.19:57:34.09#ibcon#about to read 6, iclass 26, count 0 2006.257.19:57:34.09#ibcon#read 6, iclass 26, count 0 2006.257.19:57:34.09#ibcon#end of sib2, iclass 26, count 0 2006.257.19:57:34.09#ibcon#*after write, iclass 26, count 0 2006.257.19:57:34.09#ibcon#*before return 0, iclass 26, count 0 2006.257.19:57:34.09#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:34.09#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:34.09#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:57:34.09#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:57:34.09$vck44/valo=3,564.99 2006.257.19:57:34.09#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.19:57:34.09#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.19:57:34.09#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:34.09#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:34.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:34.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:34.09#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:57:34.09#ibcon#first serial, iclass 28, count 0 2006.257.19:57:34.09#ibcon#enter sib2, iclass 28, count 0 2006.257.19:57:34.09#ibcon#flushed, iclass 28, count 0 2006.257.19:57:34.09#ibcon#about to write, iclass 28, count 0 2006.257.19:57:34.09#ibcon#wrote, iclass 28, count 0 2006.257.19:57:34.09#ibcon#about to read 3, iclass 28, count 0 2006.257.19:57:34.11#ibcon#read 3, iclass 28, count 0 2006.257.19:57:34.11#ibcon#about to read 4, iclass 28, count 0 2006.257.19:57:34.11#ibcon#read 4, iclass 28, count 0 2006.257.19:57:34.11#ibcon#about to read 5, iclass 28, count 0 2006.257.19:57:34.11#ibcon#read 5, iclass 28, count 0 2006.257.19:57:34.11#ibcon#about to read 6, iclass 28, count 0 2006.257.19:57:34.11#ibcon#read 6, iclass 28, count 0 2006.257.19:57:34.11#ibcon#end of sib2, iclass 28, count 0 2006.257.19:57:34.11#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:57:34.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:57:34.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.19:57:34.11#ibcon#*before write, iclass 28, count 0 2006.257.19:57:34.11#ibcon#enter sib2, iclass 28, count 0 2006.257.19:57:34.11#ibcon#flushed, iclass 28, count 0 2006.257.19:57:34.11#ibcon#about to write, iclass 28, count 0 2006.257.19:57:34.11#ibcon#wrote, iclass 28, count 0 2006.257.19:57:34.11#ibcon#about to read 3, iclass 28, count 0 2006.257.19:57:34.15#ibcon#read 3, iclass 28, count 0 2006.257.19:57:34.15#ibcon#about to read 4, iclass 28, count 0 2006.257.19:57:34.15#ibcon#read 4, iclass 28, count 0 2006.257.19:57:34.15#ibcon#about to read 5, iclass 28, count 0 2006.257.19:57:34.15#ibcon#read 5, iclass 28, count 0 2006.257.19:57:34.15#ibcon#about to read 6, iclass 28, count 0 2006.257.19:57:34.15#ibcon#read 6, iclass 28, count 0 2006.257.19:57:34.15#ibcon#end of sib2, iclass 28, count 0 2006.257.19:57:34.15#ibcon#*after write, iclass 28, count 0 2006.257.19:57:34.15#ibcon#*before return 0, iclass 28, count 0 2006.257.19:57:34.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:34.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:34.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:57:34.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:57:34.15$vck44/va=3,8 2006.257.19:57:34.15#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.19:57:34.15#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.19:57:34.15#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:34.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:34.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:34.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:34.21#ibcon#enter wrdev, iclass 30, count 2 2006.257.19:57:34.21#ibcon#first serial, iclass 30, count 2 2006.257.19:57:34.21#ibcon#enter sib2, iclass 30, count 2 2006.257.19:57:34.21#ibcon#flushed, iclass 30, count 2 2006.257.19:57:34.21#ibcon#about to write, iclass 30, count 2 2006.257.19:57:34.21#ibcon#wrote, iclass 30, count 2 2006.257.19:57:34.21#ibcon#about to read 3, iclass 30, count 2 2006.257.19:57:34.23#ibcon#read 3, iclass 30, count 2 2006.257.19:57:34.23#ibcon#about to read 4, iclass 30, count 2 2006.257.19:57:34.23#ibcon#read 4, iclass 30, count 2 2006.257.19:57:34.23#ibcon#about to read 5, iclass 30, count 2 2006.257.19:57:34.23#ibcon#read 5, iclass 30, count 2 2006.257.19:57:34.23#ibcon#about to read 6, iclass 30, count 2 2006.257.19:57:34.23#ibcon#read 6, iclass 30, count 2 2006.257.19:57:34.23#ibcon#end of sib2, iclass 30, count 2 2006.257.19:57:34.23#ibcon#*mode == 0, iclass 30, count 2 2006.257.19:57:34.23#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.19:57:34.23#ibcon#[25=AT03-08\r\n] 2006.257.19:57:34.23#ibcon#*before write, iclass 30, count 2 2006.257.19:57:34.23#ibcon#enter sib2, iclass 30, count 2 2006.257.19:57:34.23#ibcon#flushed, iclass 30, count 2 2006.257.19:57:34.23#ibcon#about to write, iclass 30, count 2 2006.257.19:57:34.23#ibcon#wrote, iclass 30, count 2 2006.257.19:57:34.23#ibcon#about to read 3, iclass 30, count 2 2006.257.19:57:34.26#ibcon#read 3, iclass 30, count 2 2006.257.19:57:34.26#ibcon#about to read 4, iclass 30, count 2 2006.257.19:57:34.26#ibcon#read 4, iclass 30, count 2 2006.257.19:57:34.26#ibcon#about to read 5, iclass 30, count 2 2006.257.19:57:34.26#ibcon#read 5, iclass 30, count 2 2006.257.19:57:34.26#ibcon#about to read 6, iclass 30, count 2 2006.257.19:57:34.26#ibcon#read 6, iclass 30, count 2 2006.257.19:57:34.26#ibcon#end of sib2, iclass 30, count 2 2006.257.19:57:34.26#ibcon#*after write, iclass 30, count 2 2006.257.19:57:34.26#ibcon#*before return 0, iclass 30, count 2 2006.257.19:57:34.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:34.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:34.26#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.19:57:34.26#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:34.26#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:34.38#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:34.38#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:34.38#ibcon#enter wrdev, iclass 30, count 0 2006.257.19:57:34.38#ibcon#first serial, iclass 30, count 0 2006.257.19:57:34.38#ibcon#enter sib2, iclass 30, count 0 2006.257.19:57:34.38#ibcon#flushed, iclass 30, count 0 2006.257.19:57:34.38#ibcon#about to write, iclass 30, count 0 2006.257.19:57:34.38#ibcon#wrote, iclass 30, count 0 2006.257.19:57:34.38#ibcon#about to read 3, iclass 30, count 0 2006.257.19:57:34.40#ibcon#read 3, iclass 30, count 0 2006.257.19:57:34.40#ibcon#about to read 4, iclass 30, count 0 2006.257.19:57:34.40#ibcon#read 4, iclass 30, count 0 2006.257.19:57:34.40#ibcon#about to read 5, iclass 30, count 0 2006.257.19:57:34.40#ibcon#read 5, iclass 30, count 0 2006.257.19:57:34.40#ibcon#about to read 6, iclass 30, count 0 2006.257.19:57:34.40#ibcon#read 6, iclass 30, count 0 2006.257.19:57:34.40#ibcon#end of sib2, iclass 30, count 0 2006.257.19:57:34.40#ibcon#*mode == 0, iclass 30, count 0 2006.257.19:57:34.40#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.19:57:34.40#ibcon#[25=USB\r\n] 2006.257.19:57:34.40#ibcon#*before write, iclass 30, count 0 2006.257.19:57:34.40#ibcon#enter sib2, iclass 30, count 0 2006.257.19:57:34.40#ibcon#flushed, iclass 30, count 0 2006.257.19:57:34.40#ibcon#about to write, iclass 30, count 0 2006.257.19:57:34.40#ibcon#wrote, iclass 30, count 0 2006.257.19:57:34.40#ibcon#about to read 3, iclass 30, count 0 2006.257.19:57:34.43#ibcon#read 3, iclass 30, count 0 2006.257.19:57:34.43#ibcon#about to read 4, iclass 30, count 0 2006.257.19:57:34.43#ibcon#read 4, iclass 30, count 0 2006.257.19:57:34.43#ibcon#about to read 5, iclass 30, count 0 2006.257.19:57:34.43#ibcon#read 5, iclass 30, count 0 2006.257.19:57:34.43#ibcon#about to read 6, iclass 30, count 0 2006.257.19:57:34.43#ibcon#read 6, iclass 30, count 0 2006.257.19:57:34.43#ibcon#end of sib2, iclass 30, count 0 2006.257.19:57:34.43#ibcon#*after write, iclass 30, count 0 2006.257.19:57:34.43#ibcon#*before return 0, iclass 30, count 0 2006.257.19:57:34.43#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:34.43#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:34.43#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.19:57:34.43#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.19:57:34.43$vck44/valo=4,624.99 2006.257.19:57:34.43#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.19:57:34.43#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.19:57:34.43#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:34.43#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:34.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:34.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:34.43#ibcon#enter wrdev, iclass 32, count 0 2006.257.19:57:34.43#ibcon#first serial, iclass 32, count 0 2006.257.19:57:34.43#ibcon#enter sib2, iclass 32, count 0 2006.257.19:57:34.43#ibcon#flushed, iclass 32, count 0 2006.257.19:57:34.43#ibcon#about to write, iclass 32, count 0 2006.257.19:57:34.43#ibcon#wrote, iclass 32, count 0 2006.257.19:57:34.43#ibcon#about to read 3, iclass 32, count 0 2006.257.19:57:34.45#ibcon#read 3, iclass 32, count 0 2006.257.19:57:34.45#ibcon#about to read 4, iclass 32, count 0 2006.257.19:57:34.45#ibcon#read 4, iclass 32, count 0 2006.257.19:57:34.45#ibcon#about to read 5, iclass 32, count 0 2006.257.19:57:34.45#ibcon#read 5, iclass 32, count 0 2006.257.19:57:34.45#ibcon#about to read 6, iclass 32, count 0 2006.257.19:57:34.45#ibcon#read 6, iclass 32, count 0 2006.257.19:57:34.45#ibcon#end of sib2, iclass 32, count 0 2006.257.19:57:34.45#ibcon#*mode == 0, iclass 32, count 0 2006.257.19:57:34.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.19:57:34.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.19:57:34.45#ibcon#*before write, iclass 32, count 0 2006.257.19:57:34.45#ibcon#enter sib2, iclass 32, count 0 2006.257.19:57:34.45#ibcon#flushed, iclass 32, count 0 2006.257.19:57:34.45#ibcon#about to write, iclass 32, count 0 2006.257.19:57:34.45#ibcon#wrote, iclass 32, count 0 2006.257.19:57:34.45#ibcon#about to read 3, iclass 32, count 0 2006.257.19:57:34.49#ibcon#read 3, iclass 32, count 0 2006.257.19:57:34.49#ibcon#about to read 4, iclass 32, count 0 2006.257.19:57:34.49#ibcon#read 4, iclass 32, count 0 2006.257.19:57:34.49#ibcon#about to read 5, iclass 32, count 0 2006.257.19:57:34.49#ibcon#read 5, iclass 32, count 0 2006.257.19:57:34.49#ibcon#about to read 6, iclass 32, count 0 2006.257.19:57:34.49#ibcon#read 6, iclass 32, count 0 2006.257.19:57:34.49#ibcon#end of sib2, iclass 32, count 0 2006.257.19:57:34.49#ibcon#*after write, iclass 32, count 0 2006.257.19:57:34.49#ibcon#*before return 0, iclass 32, count 0 2006.257.19:57:34.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:34.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:34.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.19:57:34.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.19:57:34.49$vck44/va=4,7 2006.257.19:57:34.49#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.19:57:34.49#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.19:57:34.49#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:34.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:34.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:34.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:34.55#ibcon#enter wrdev, iclass 34, count 2 2006.257.19:57:34.55#ibcon#first serial, iclass 34, count 2 2006.257.19:57:34.55#ibcon#enter sib2, iclass 34, count 2 2006.257.19:57:34.55#ibcon#flushed, iclass 34, count 2 2006.257.19:57:34.55#ibcon#about to write, iclass 34, count 2 2006.257.19:57:34.55#ibcon#wrote, iclass 34, count 2 2006.257.19:57:34.55#ibcon#about to read 3, iclass 34, count 2 2006.257.19:57:34.57#ibcon#read 3, iclass 34, count 2 2006.257.19:57:34.57#ibcon#about to read 4, iclass 34, count 2 2006.257.19:57:34.57#ibcon#read 4, iclass 34, count 2 2006.257.19:57:34.57#ibcon#about to read 5, iclass 34, count 2 2006.257.19:57:34.57#ibcon#read 5, iclass 34, count 2 2006.257.19:57:34.57#ibcon#about to read 6, iclass 34, count 2 2006.257.19:57:34.57#ibcon#read 6, iclass 34, count 2 2006.257.19:57:34.57#ibcon#end of sib2, iclass 34, count 2 2006.257.19:57:34.57#ibcon#*mode == 0, iclass 34, count 2 2006.257.19:57:34.57#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.19:57:34.57#ibcon#[25=AT04-07\r\n] 2006.257.19:57:34.57#ibcon#*before write, iclass 34, count 2 2006.257.19:57:34.57#ibcon#enter sib2, iclass 34, count 2 2006.257.19:57:34.57#ibcon#flushed, iclass 34, count 2 2006.257.19:57:34.57#ibcon#about to write, iclass 34, count 2 2006.257.19:57:34.57#ibcon#wrote, iclass 34, count 2 2006.257.19:57:34.57#ibcon#about to read 3, iclass 34, count 2 2006.257.19:57:34.60#ibcon#read 3, iclass 34, count 2 2006.257.19:57:34.60#ibcon#about to read 4, iclass 34, count 2 2006.257.19:57:34.60#ibcon#read 4, iclass 34, count 2 2006.257.19:57:34.60#ibcon#about to read 5, iclass 34, count 2 2006.257.19:57:34.60#ibcon#read 5, iclass 34, count 2 2006.257.19:57:34.60#ibcon#about to read 6, iclass 34, count 2 2006.257.19:57:34.60#ibcon#read 6, iclass 34, count 2 2006.257.19:57:34.60#ibcon#end of sib2, iclass 34, count 2 2006.257.19:57:34.60#ibcon#*after write, iclass 34, count 2 2006.257.19:57:34.60#ibcon#*before return 0, iclass 34, count 2 2006.257.19:57:34.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:34.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:34.60#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.19:57:34.60#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:34.60#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:34.72#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:34.72#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:34.72#ibcon#enter wrdev, iclass 34, count 0 2006.257.19:57:34.72#ibcon#first serial, iclass 34, count 0 2006.257.19:57:34.72#ibcon#enter sib2, iclass 34, count 0 2006.257.19:57:34.72#ibcon#flushed, iclass 34, count 0 2006.257.19:57:34.72#ibcon#about to write, iclass 34, count 0 2006.257.19:57:34.72#ibcon#wrote, iclass 34, count 0 2006.257.19:57:34.72#ibcon#about to read 3, iclass 34, count 0 2006.257.19:57:34.74#ibcon#read 3, iclass 34, count 0 2006.257.19:57:34.74#ibcon#about to read 4, iclass 34, count 0 2006.257.19:57:34.74#ibcon#read 4, iclass 34, count 0 2006.257.19:57:34.74#ibcon#about to read 5, iclass 34, count 0 2006.257.19:57:34.74#ibcon#read 5, iclass 34, count 0 2006.257.19:57:34.74#ibcon#about to read 6, iclass 34, count 0 2006.257.19:57:34.74#ibcon#read 6, iclass 34, count 0 2006.257.19:57:34.74#ibcon#end of sib2, iclass 34, count 0 2006.257.19:57:34.74#ibcon#*mode == 0, iclass 34, count 0 2006.257.19:57:34.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.19:57:34.74#ibcon#[25=USB\r\n] 2006.257.19:57:34.74#ibcon#*before write, iclass 34, count 0 2006.257.19:57:34.74#ibcon#enter sib2, iclass 34, count 0 2006.257.19:57:34.74#ibcon#flushed, iclass 34, count 0 2006.257.19:57:34.74#ibcon#about to write, iclass 34, count 0 2006.257.19:57:34.74#ibcon#wrote, iclass 34, count 0 2006.257.19:57:34.74#ibcon#about to read 3, iclass 34, count 0 2006.257.19:57:34.77#ibcon#read 3, iclass 34, count 0 2006.257.19:57:34.77#ibcon#about to read 4, iclass 34, count 0 2006.257.19:57:34.77#ibcon#read 4, iclass 34, count 0 2006.257.19:57:34.77#ibcon#about to read 5, iclass 34, count 0 2006.257.19:57:34.77#ibcon#read 5, iclass 34, count 0 2006.257.19:57:34.77#ibcon#about to read 6, iclass 34, count 0 2006.257.19:57:34.77#ibcon#read 6, iclass 34, count 0 2006.257.19:57:34.77#ibcon#end of sib2, iclass 34, count 0 2006.257.19:57:34.77#ibcon#*after write, iclass 34, count 0 2006.257.19:57:34.77#ibcon#*before return 0, iclass 34, count 0 2006.257.19:57:34.77#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:34.77#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:34.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.19:57:34.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.19:57:34.77$vck44/valo=5,734.99 2006.257.19:57:34.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.19:57:34.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.19:57:34.77#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:34.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:34.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:34.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:34.77#ibcon#enter wrdev, iclass 36, count 0 2006.257.19:57:34.77#ibcon#first serial, iclass 36, count 0 2006.257.19:57:34.77#ibcon#enter sib2, iclass 36, count 0 2006.257.19:57:34.77#ibcon#flushed, iclass 36, count 0 2006.257.19:57:34.77#ibcon#about to write, iclass 36, count 0 2006.257.19:57:34.77#ibcon#wrote, iclass 36, count 0 2006.257.19:57:34.77#ibcon#about to read 3, iclass 36, count 0 2006.257.19:57:34.79#ibcon#read 3, iclass 36, count 0 2006.257.19:57:34.79#ibcon#about to read 4, iclass 36, count 0 2006.257.19:57:34.79#ibcon#read 4, iclass 36, count 0 2006.257.19:57:34.79#ibcon#about to read 5, iclass 36, count 0 2006.257.19:57:34.79#ibcon#read 5, iclass 36, count 0 2006.257.19:57:34.79#ibcon#about to read 6, iclass 36, count 0 2006.257.19:57:34.79#ibcon#read 6, iclass 36, count 0 2006.257.19:57:34.79#ibcon#end of sib2, iclass 36, count 0 2006.257.19:57:34.79#ibcon#*mode == 0, iclass 36, count 0 2006.257.19:57:34.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.19:57:34.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.19:57:34.79#ibcon#*before write, iclass 36, count 0 2006.257.19:57:34.79#ibcon#enter sib2, iclass 36, count 0 2006.257.19:57:34.79#ibcon#flushed, iclass 36, count 0 2006.257.19:57:34.79#ibcon#about to write, iclass 36, count 0 2006.257.19:57:34.79#ibcon#wrote, iclass 36, count 0 2006.257.19:57:34.79#ibcon#about to read 3, iclass 36, count 0 2006.257.19:57:34.83#ibcon#read 3, iclass 36, count 0 2006.257.19:57:34.83#ibcon#about to read 4, iclass 36, count 0 2006.257.19:57:34.83#ibcon#read 4, iclass 36, count 0 2006.257.19:57:34.83#ibcon#about to read 5, iclass 36, count 0 2006.257.19:57:34.83#ibcon#read 5, iclass 36, count 0 2006.257.19:57:34.83#ibcon#about to read 6, iclass 36, count 0 2006.257.19:57:34.83#ibcon#read 6, iclass 36, count 0 2006.257.19:57:34.83#ibcon#end of sib2, iclass 36, count 0 2006.257.19:57:34.83#ibcon#*after write, iclass 36, count 0 2006.257.19:57:34.83#ibcon#*before return 0, iclass 36, count 0 2006.257.19:57:34.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:34.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:34.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.19:57:34.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.19:57:34.83$vck44/va=5,4 2006.257.19:57:34.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.19:57:34.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.19:57:34.83#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:34.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:34.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:34.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:34.89#ibcon#enter wrdev, iclass 38, count 2 2006.257.19:57:34.89#ibcon#first serial, iclass 38, count 2 2006.257.19:57:34.89#ibcon#enter sib2, iclass 38, count 2 2006.257.19:57:34.89#ibcon#flushed, iclass 38, count 2 2006.257.19:57:34.89#ibcon#about to write, iclass 38, count 2 2006.257.19:57:34.89#ibcon#wrote, iclass 38, count 2 2006.257.19:57:34.89#ibcon#about to read 3, iclass 38, count 2 2006.257.19:57:34.91#ibcon#read 3, iclass 38, count 2 2006.257.19:57:34.91#ibcon#about to read 4, iclass 38, count 2 2006.257.19:57:34.91#ibcon#read 4, iclass 38, count 2 2006.257.19:57:34.91#ibcon#about to read 5, iclass 38, count 2 2006.257.19:57:34.91#ibcon#read 5, iclass 38, count 2 2006.257.19:57:34.91#ibcon#about to read 6, iclass 38, count 2 2006.257.19:57:34.91#ibcon#read 6, iclass 38, count 2 2006.257.19:57:34.91#ibcon#end of sib2, iclass 38, count 2 2006.257.19:57:34.91#ibcon#*mode == 0, iclass 38, count 2 2006.257.19:57:34.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.19:57:34.91#ibcon#[25=AT05-04\r\n] 2006.257.19:57:34.91#ibcon#*before write, iclass 38, count 2 2006.257.19:57:34.91#ibcon#enter sib2, iclass 38, count 2 2006.257.19:57:34.91#ibcon#flushed, iclass 38, count 2 2006.257.19:57:34.91#ibcon#about to write, iclass 38, count 2 2006.257.19:57:34.91#ibcon#wrote, iclass 38, count 2 2006.257.19:57:34.91#ibcon#about to read 3, iclass 38, count 2 2006.257.19:57:34.94#ibcon#read 3, iclass 38, count 2 2006.257.19:57:34.94#ibcon#about to read 4, iclass 38, count 2 2006.257.19:57:34.94#ibcon#read 4, iclass 38, count 2 2006.257.19:57:34.94#ibcon#about to read 5, iclass 38, count 2 2006.257.19:57:34.94#ibcon#read 5, iclass 38, count 2 2006.257.19:57:34.94#ibcon#about to read 6, iclass 38, count 2 2006.257.19:57:34.94#ibcon#read 6, iclass 38, count 2 2006.257.19:57:34.94#ibcon#end of sib2, iclass 38, count 2 2006.257.19:57:34.94#ibcon#*after write, iclass 38, count 2 2006.257.19:57:34.94#ibcon#*before return 0, iclass 38, count 2 2006.257.19:57:34.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:34.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:34.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.19:57:34.94#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:34.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:35.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:35.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:35.06#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:57:35.06#ibcon#first serial, iclass 38, count 0 2006.257.19:57:35.06#ibcon#enter sib2, iclass 38, count 0 2006.257.19:57:35.06#ibcon#flushed, iclass 38, count 0 2006.257.19:57:35.06#ibcon#about to write, iclass 38, count 0 2006.257.19:57:35.06#ibcon#wrote, iclass 38, count 0 2006.257.19:57:35.06#ibcon#about to read 3, iclass 38, count 0 2006.257.19:57:35.08#ibcon#read 3, iclass 38, count 0 2006.257.19:57:35.08#ibcon#about to read 4, iclass 38, count 0 2006.257.19:57:35.08#ibcon#read 4, iclass 38, count 0 2006.257.19:57:35.08#ibcon#about to read 5, iclass 38, count 0 2006.257.19:57:35.08#ibcon#read 5, iclass 38, count 0 2006.257.19:57:35.08#ibcon#about to read 6, iclass 38, count 0 2006.257.19:57:35.08#ibcon#read 6, iclass 38, count 0 2006.257.19:57:35.08#ibcon#end of sib2, iclass 38, count 0 2006.257.19:57:35.08#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:57:35.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:57:35.08#ibcon#[25=USB\r\n] 2006.257.19:57:35.08#ibcon#*before write, iclass 38, count 0 2006.257.19:57:35.08#ibcon#enter sib2, iclass 38, count 0 2006.257.19:57:35.08#ibcon#flushed, iclass 38, count 0 2006.257.19:57:35.08#ibcon#about to write, iclass 38, count 0 2006.257.19:57:35.08#ibcon#wrote, iclass 38, count 0 2006.257.19:57:35.08#ibcon#about to read 3, iclass 38, count 0 2006.257.19:57:35.11#ibcon#read 3, iclass 38, count 0 2006.257.19:57:35.11#ibcon#about to read 4, iclass 38, count 0 2006.257.19:57:35.11#ibcon#read 4, iclass 38, count 0 2006.257.19:57:35.11#ibcon#about to read 5, iclass 38, count 0 2006.257.19:57:35.11#ibcon#read 5, iclass 38, count 0 2006.257.19:57:35.11#ibcon#about to read 6, iclass 38, count 0 2006.257.19:57:35.11#ibcon#read 6, iclass 38, count 0 2006.257.19:57:35.11#ibcon#end of sib2, iclass 38, count 0 2006.257.19:57:35.11#ibcon#*after write, iclass 38, count 0 2006.257.19:57:35.11#ibcon#*before return 0, iclass 38, count 0 2006.257.19:57:35.11#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:35.11#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:35.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:57:35.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:57:35.11$vck44/valo=6,814.99 2006.257.19:57:35.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.19:57:35.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.19:57:35.11#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:35.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:35.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:35.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:35.11#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:57:35.11#ibcon#first serial, iclass 40, count 0 2006.257.19:57:35.11#ibcon#enter sib2, iclass 40, count 0 2006.257.19:57:35.11#ibcon#flushed, iclass 40, count 0 2006.257.19:57:35.11#ibcon#about to write, iclass 40, count 0 2006.257.19:57:35.11#ibcon#wrote, iclass 40, count 0 2006.257.19:57:35.11#ibcon#about to read 3, iclass 40, count 0 2006.257.19:57:35.13#ibcon#read 3, iclass 40, count 0 2006.257.19:57:35.13#ibcon#about to read 4, iclass 40, count 0 2006.257.19:57:35.13#ibcon#read 4, iclass 40, count 0 2006.257.19:57:35.13#ibcon#about to read 5, iclass 40, count 0 2006.257.19:57:35.13#ibcon#read 5, iclass 40, count 0 2006.257.19:57:35.13#ibcon#about to read 6, iclass 40, count 0 2006.257.19:57:35.13#ibcon#read 6, iclass 40, count 0 2006.257.19:57:35.13#ibcon#end of sib2, iclass 40, count 0 2006.257.19:57:35.13#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:57:35.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:57:35.13#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.19:57:35.13#ibcon#*before write, iclass 40, count 0 2006.257.19:57:35.13#ibcon#enter sib2, iclass 40, count 0 2006.257.19:57:35.13#ibcon#flushed, iclass 40, count 0 2006.257.19:57:35.13#ibcon#about to write, iclass 40, count 0 2006.257.19:57:35.13#ibcon#wrote, iclass 40, count 0 2006.257.19:57:35.13#ibcon#about to read 3, iclass 40, count 0 2006.257.19:57:35.17#ibcon#read 3, iclass 40, count 0 2006.257.19:57:35.17#ibcon#about to read 4, iclass 40, count 0 2006.257.19:57:35.17#ibcon#read 4, iclass 40, count 0 2006.257.19:57:35.17#ibcon#about to read 5, iclass 40, count 0 2006.257.19:57:35.17#ibcon#read 5, iclass 40, count 0 2006.257.19:57:35.17#ibcon#about to read 6, iclass 40, count 0 2006.257.19:57:35.17#ibcon#read 6, iclass 40, count 0 2006.257.19:57:35.17#ibcon#end of sib2, iclass 40, count 0 2006.257.19:57:35.17#ibcon#*after write, iclass 40, count 0 2006.257.19:57:35.17#ibcon#*before return 0, iclass 40, count 0 2006.257.19:57:35.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:35.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:35.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:57:35.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:57:35.17$vck44/va=6,4 2006.257.19:57:35.17#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.19:57:35.17#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.19:57:35.17#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:35.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:35.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:35.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:35.23#ibcon#enter wrdev, iclass 4, count 2 2006.257.19:57:35.23#ibcon#first serial, iclass 4, count 2 2006.257.19:57:35.23#ibcon#enter sib2, iclass 4, count 2 2006.257.19:57:35.23#ibcon#flushed, iclass 4, count 2 2006.257.19:57:35.23#ibcon#about to write, iclass 4, count 2 2006.257.19:57:35.23#ibcon#wrote, iclass 4, count 2 2006.257.19:57:35.23#ibcon#about to read 3, iclass 4, count 2 2006.257.19:57:35.25#ibcon#read 3, iclass 4, count 2 2006.257.19:57:35.25#ibcon#about to read 4, iclass 4, count 2 2006.257.19:57:35.25#ibcon#read 4, iclass 4, count 2 2006.257.19:57:35.25#ibcon#about to read 5, iclass 4, count 2 2006.257.19:57:35.25#ibcon#read 5, iclass 4, count 2 2006.257.19:57:35.25#ibcon#about to read 6, iclass 4, count 2 2006.257.19:57:35.25#ibcon#read 6, iclass 4, count 2 2006.257.19:57:35.25#ibcon#end of sib2, iclass 4, count 2 2006.257.19:57:35.25#ibcon#*mode == 0, iclass 4, count 2 2006.257.19:57:35.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.19:57:35.25#ibcon#[25=AT06-04\r\n] 2006.257.19:57:35.25#ibcon#*before write, iclass 4, count 2 2006.257.19:57:35.25#ibcon#enter sib2, iclass 4, count 2 2006.257.19:57:35.25#ibcon#flushed, iclass 4, count 2 2006.257.19:57:35.25#ibcon#about to write, iclass 4, count 2 2006.257.19:57:35.25#ibcon#wrote, iclass 4, count 2 2006.257.19:57:35.25#ibcon#about to read 3, iclass 4, count 2 2006.257.19:57:35.28#ibcon#read 3, iclass 4, count 2 2006.257.19:57:35.28#ibcon#about to read 4, iclass 4, count 2 2006.257.19:57:35.28#ibcon#read 4, iclass 4, count 2 2006.257.19:57:35.28#ibcon#about to read 5, iclass 4, count 2 2006.257.19:57:35.28#ibcon#read 5, iclass 4, count 2 2006.257.19:57:35.28#ibcon#about to read 6, iclass 4, count 2 2006.257.19:57:35.28#ibcon#read 6, iclass 4, count 2 2006.257.19:57:35.28#ibcon#end of sib2, iclass 4, count 2 2006.257.19:57:35.28#ibcon#*after write, iclass 4, count 2 2006.257.19:57:35.28#ibcon#*before return 0, iclass 4, count 2 2006.257.19:57:35.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:35.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:35.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.19:57:35.28#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:35.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:35.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:35.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:35.40#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:57:35.40#ibcon#first serial, iclass 4, count 0 2006.257.19:57:35.40#ibcon#enter sib2, iclass 4, count 0 2006.257.19:57:35.40#ibcon#flushed, iclass 4, count 0 2006.257.19:57:35.40#ibcon#about to write, iclass 4, count 0 2006.257.19:57:35.40#ibcon#wrote, iclass 4, count 0 2006.257.19:57:35.40#ibcon#about to read 3, iclass 4, count 0 2006.257.19:57:35.42#ibcon#read 3, iclass 4, count 0 2006.257.19:57:35.42#ibcon#about to read 4, iclass 4, count 0 2006.257.19:57:35.42#ibcon#read 4, iclass 4, count 0 2006.257.19:57:35.42#ibcon#about to read 5, iclass 4, count 0 2006.257.19:57:35.42#ibcon#read 5, iclass 4, count 0 2006.257.19:57:35.42#ibcon#about to read 6, iclass 4, count 0 2006.257.19:57:35.42#ibcon#read 6, iclass 4, count 0 2006.257.19:57:35.42#ibcon#end of sib2, iclass 4, count 0 2006.257.19:57:35.42#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:57:35.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:57:35.42#ibcon#[25=USB\r\n] 2006.257.19:57:35.42#ibcon#*before write, iclass 4, count 0 2006.257.19:57:35.42#ibcon#enter sib2, iclass 4, count 0 2006.257.19:57:35.42#ibcon#flushed, iclass 4, count 0 2006.257.19:57:35.42#ibcon#about to write, iclass 4, count 0 2006.257.19:57:35.42#ibcon#wrote, iclass 4, count 0 2006.257.19:57:35.42#ibcon#about to read 3, iclass 4, count 0 2006.257.19:57:35.45#ibcon#read 3, iclass 4, count 0 2006.257.19:57:35.45#ibcon#about to read 4, iclass 4, count 0 2006.257.19:57:35.45#ibcon#read 4, iclass 4, count 0 2006.257.19:57:35.45#ibcon#about to read 5, iclass 4, count 0 2006.257.19:57:35.45#ibcon#read 5, iclass 4, count 0 2006.257.19:57:35.45#ibcon#about to read 6, iclass 4, count 0 2006.257.19:57:35.45#ibcon#read 6, iclass 4, count 0 2006.257.19:57:35.45#ibcon#end of sib2, iclass 4, count 0 2006.257.19:57:35.45#ibcon#*after write, iclass 4, count 0 2006.257.19:57:35.45#ibcon#*before return 0, iclass 4, count 0 2006.257.19:57:35.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:35.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:35.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:57:35.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:57:35.45$vck44/valo=7,864.99 2006.257.19:57:35.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.19:57:35.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.19:57:35.45#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:35.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:35.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:35.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:35.45#ibcon#enter wrdev, iclass 6, count 0 2006.257.19:57:35.45#ibcon#first serial, iclass 6, count 0 2006.257.19:57:35.45#ibcon#enter sib2, iclass 6, count 0 2006.257.19:57:35.45#ibcon#flushed, iclass 6, count 0 2006.257.19:57:35.45#ibcon#about to write, iclass 6, count 0 2006.257.19:57:35.45#ibcon#wrote, iclass 6, count 0 2006.257.19:57:35.45#ibcon#about to read 3, iclass 6, count 0 2006.257.19:57:35.47#ibcon#read 3, iclass 6, count 0 2006.257.19:57:35.47#ibcon#about to read 4, iclass 6, count 0 2006.257.19:57:35.47#ibcon#read 4, iclass 6, count 0 2006.257.19:57:35.47#ibcon#about to read 5, iclass 6, count 0 2006.257.19:57:35.47#ibcon#read 5, iclass 6, count 0 2006.257.19:57:35.47#ibcon#about to read 6, iclass 6, count 0 2006.257.19:57:35.47#ibcon#read 6, iclass 6, count 0 2006.257.19:57:35.47#ibcon#end of sib2, iclass 6, count 0 2006.257.19:57:35.47#ibcon#*mode == 0, iclass 6, count 0 2006.257.19:57:35.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.19:57:35.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.19:57:35.47#ibcon#*before write, iclass 6, count 0 2006.257.19:57:35.47#ibcon#enter sib2, iclass 6, count 0 2006.257.19:57:35.47#ibcon#flushed, iclass 6, count 0 2006.257.19:57:35.47#ibcon#about to write, iclass 6, count 0 2006.257.19:57:35.47#ibcon#wrote, iclass 6, count 0 2006.257.19:57:35.47#ibcon#about to read 3, iclass 6, count 0 2006.257.19:57:35.51#ibcon#read 3, iclass 6, count 0 2006.257.19:57:35.51#ibcon#about to read 4, iclass 6, count 0 2006.257.19:57:35.51#ibcon#read 4, iclass 6, count 0 2006.257.19:57:35.51#ibcon#about to read 5, iclass 6, count 0 2006.257.19:57:35.51#ibcon#read 5, iclass 6, count 0 2006.257.19:57:35.51#ibcon#about to read 6, iclass 6, count 0 2006.257.19:57:35.51#ibcon#read 6, iclass 6, count 0 2006.257.19:57:35.51#ibcon#end of sib2, iclass 6, count 0 2006.257.19:57:35.51#ibcon#*after write, iclass 6, count 0 2006.257.19:57:35.51#ibcon#*before return 0, iclass 6, count 0 2006.257.19:57:35.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:35.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:35.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.19:57:35.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.19:57:35.51$vck44/va=7,4 2006.257.19:57:35.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.19:57:35.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.19:57:35.51#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:35.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:35.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:35.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:35.57#ibcon#enter wrdev, iclass 10, count 2 2006.257.19:57:35.57#ibcon#first serial, iclass 10, count 2 2006.257.19:57:35.57#ibcon#enter sib2, iclass 10, count 2 2006.257.19:57:35.57#ibcon#flushed, iclass 10, count 2 2006.257.19:57:35.57#ibcon#about to write, iclass 10, count 2 2006.257.19:57:35.57#ibcon#wrote, iclass 10, count 2 2006.257.19:57:35.57#ibcon#about to read 3, iclass 10, count 2 2006.257.19:57:35.59#ibcon#read 3, iclass 10, count 2 2006.257.19:57:35.59#ibcon#about to read 4, iclass 10, count 2 2006.257.19:57:35.59#ibcon#read 4, iclass 10, count 2 2006.257.19:57:35.59#ibcon#about to read 5, iclass 10, count 2 2006.257.19:57:35.59#ibcon#read 5, iclass 10, count 2 2006.257.19:57:35.59#ibcon#about to read 6, iclass 10, count 2 2006.257.19:57:35.59#ibcon#read 6, iclass 10, count 2 2006.257.19:57:35.59#ibcon#end of sib2, iclass 10, count 2 2006.257.19:57:35.59#ibcon#*mode == 0, iclass 10, count 2 2006.257.19:57:35.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.19:57:35.59#ibcon#[25=AT07-04\r\n] 2006.257.19:57:35.59#ibcon#*before write, iclass 10, count 2 2006.257.19:57:35.59#ibcon#enter sib2, iclass 10, count 2 2006.257.19:57:35.59#ibcon#flushed, iclass 10, count 2 2006.257.19:57:35.59#ibcon#about to write, iclass 10, count 2 2006.257.19:57:35.59#ibcon#wrote, iclass 10, count 2 2006.257.19:57:35.59#ibcon#about to read 3, iclass 10, count 2 2006.257.19:57:35.62#ibcon#read 3, iclass 10, count 2 2006.257.19:57:35.62#ibcon#about to read 4, iclass 10, count 2 2006.257.19:57:35.62#ibcon#read 4, iclass 10, count 2 2006.257.19:57:35.62#ibcon#about to read 5, iclass 10, count 2 2006.257.19:57:35.62#ibcon#read 5, iclass 10, count 2 2006.257.19:57:35.62#ibcon#about to read 6, iclass 10, count 2 2006.257.19:57:35.62#ibcon#read 6, iclass 10, count 2 2006.257.19:57:35.62#ibcon#end of sib2, iclass 10, count 2 2006.257.19:57:35.62#ibcon#*after write, iclass 10, count 2 2006.257.19:57:35.62#ibcon#*before return 0, iclass 10, count 2 2006.257.19:57:35.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:35.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:35.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.19:57:35.62#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:35.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:35.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:35.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:35.74#ibcon#enter wrdev, iclass 10, count 0 2006.257.19:57:35.74#ibcon#first serial, iclass 10, count 0 2006.257.19:57:35.74#ibcon#enter sib2, iclass 10, count 0 2006.257.19:57:35.74#ibcon#flushed, iclass 10, count 0 2006.257.19:57:35.74#ibcon#about to write, iclass 10, count 0 2006.257.19:57:35.74#ibcon#wrote, iclass 10, count 0 2006.257.19:57:35.74#ibcon#about to read 3, iclass 10, count 0 2006.257.19:57:35.76#ibcon#read 3, iclass 10, count 0 2006.257.19:57:35.76#ibcon#about to read 4, iclass 10, count 0 2006.257.19:57:35.76#ibcon#read 4, iclass 10, count 0 2006.257.19:57:35.76#ibcon#about to read 5, iclass 10, count 0 2006.257.19:57:35.76#ibcon#read 5, iclass 10, count 0 2006.257.19:57:35.76#ibcon#about to read 6, iclass 10, count 0 2006.257.19:57:35.76#ibcon#read 6, iclass 10, count 0 2006.257.19:57:35.76#ibcon#end of sib2, iclass 10, count 0 2006.257.19:57:35.76#ibcon#*mode == 0, iclass 10, count 0 2006.257.19:57:35.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.19:57:35.76#ibcon#[25=USB\r\n] 2006.257.19:57:35.76#ibcon#*before write, iclass 10, count 0 2006.257.19:57:35.76#ibcon#enter sib2, iclass 10, count 0 2006.257.19:57:35.76#ibcon#flushed, iclass 10, count 0 2006.257.19:57:35.76#ibcon#about to write, iclass 10, count 0 2006.257.19:57:35.76#ibcon#wrote, iclass 10, count 0 2006.257.19:57:35.76#ibcon#about to read 3, iclass 10, count 0 2006.257.19:57:35.79#ibcon#read 3, iclass 10, count 0 2006.257.19:57:35.79#ibcon#about to read 4, iclass 10, count 0 2006.257.19:57:35.79#ibcon#read 4, iclass 10, count 0 2006.257.19:57:35.79#ibcon#about to read 5, iclass 10, count 0 2006.257.19:57:35.79#ibcon#read 5, iclass 10, count 0 2006.257.19:57:35.79#ibcon#about to read 6, iclass 10, count 0 2006.257.19:57:35.79#ibcon#read 6, iclass 10, count 0 2006.257.19:57:35.79#ibcon#end of sib2, iclass 10, count 0 2006.257.19:57:35.79#ibcon#*after write, iclass 10, count 0 2006.257.19:57:35.79#ibcon#*before return 0, iclass 10, count 0 2006.257.19:57:35.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:35.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:35.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.19:57:35.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.19:57:35.79$vck44/valo=8,884.99 2006.257.19:57:35.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.19:57:35.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.19:57:35.79#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:35.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:35.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:35.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:35.79#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:57:35.79#ibcon#first serial, iclass 12, count 0 2006.257.19:57:35.79#ibcon#enter sib2, iclass 12, count 0 2006.257.19:57:35.79#ibcon#flushed, iclass 12, count 0 2006.257.19:57:35.79#ibcon#about to write, iclass 12, count 0 2006.257.19:57:35.79#ibcon#wrote, iclass 12, count 0 2006.257.19:57:35.79#ibcon#about to read 3, iclass 12, count 0 2006.257.19:57:35.81#ibcon#read 3, iclass 12, count 0 2006.257.19:57:35.81#ibcon#about to read 4, iclass 12, count 0 2006.257.19:57:35.81#ibcon#read 4, iclass 12, count 0 2006.257.19:57:35.81#ibcon#about to read 5, iclass 12, count 0 2006.257.19:57:35.81#ibcon#read 5, iclass 12, count 0 2006.257.19:57:35.81#ibcon#about to read 6, iclass 12, count 0 2006.257.19:57:35.81#ibcon#read 6, iclass 12, count 0 2006.257.19:57:35.81#ibcon#end of sib2, iclass 12, count 0 2006.257.19:57:35.81#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:57:35.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:57:35.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.19:57:35.81#ibcon#*before write, iclass 12, count 0 2006.257.19:57:35.81#ibcon#enter sib2, iclass 12, count 0 2006.257.19:57:35.81#ibcon#flushed, iclass 12, count 0 2006.257.19:57:35.81#ibcon#about to write, iclass 12, count 0 2006.257.19:57:35.81#ibcon#wrote, iclass 12, count 0 2006.257.19:57:35.81#ibcon#about to read 3, iclass 12, count 0 2006.257.19:57:35.85#ibcon#read 3, iclass 12, count 0 2006.257.19:57:35.85#ibcon#about to read 4, iclass 12, count 0 2006.257.19:57:35.85#ibcon#read 4, iclass 12, count 0 2006.257.19:57:35.85#ibcon#about to read 5, iclass 12, count 0 2006.257.19:57:35.85#ibcon#read 5, iclass 12, count 0 2006.257.19:57:35.85#ibcon#about to read 6, iclass 12, count 0 2006.257.19:57:35.85#ibcon#read 6, iclass 12, count 0 2006.257.19:57:35.85#ibcon#end of sib2, iclass 12, count 0 2006.257.19:57:35.85#ibcon#*after write, iclass 12, count 0 2006.257.19:57:35.85#ibcon#*before return 0, iclass 12, count 0 2006.257.19:57:35.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:35.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:35.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:57:35.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:57:35.85$vck44/va=8,4 2006.257.19:57:35.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.19:57:35.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.19:57:35.85#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:35.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:57:35.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:57:35.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:57:35.91#ibcon#enter wrdev, iclass 14, count 2 2006.257.19:57:35.91#ibcon#first serial, iclass 14, count 2 2006.257.19:57:35.91#ibcon#enter sib2, iclass 14, count 2 2006.257.19:57:35.91#ibcon#flushed, iclass 14, count 2 2006.257.19:57:35.91#ibcon#about to write, iclass 14, count 2 2006.257.19:57:35.91#ibcon#wrote, iclass 14, count 2 2006.257.19:57:35.91#ibcon#about to read 3, iclass 14, count 2 2006.257.19:57:35.93#ibcon#read 3, iclass 14, count 2 2006.257.19:57:35.93#ibcon#about to read 4, iclass 14, count 2 2006.257.19:57:35.93#ibcon#read 4, iclass 14, count 2 2006.257.19:57:35.93#ibcon#about to read 5, iclass 14, count 2 2006.257.19:57:35.93#ibcon#read 5, iclass 14, count 2 2006.257.19:57:35.93#ibcon#about to read 6, iclass 14, count 2 2006.257.19:57:35.93#ibcon#read 6, iclass 14, count 2 2006.257.19:57:35.93#ibcon#end of sib2, iclass 14, count 2 2006.257.19:57:35.93#ibcon#*mode == 0, iclass 14, count 2 2006.257.19:57:35.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.19:57:35.93#ibcon#[25=AT08-04\r\n] 2006.257.19:57:35.93#ibcon#*before write, iclass 14, count 2 2006.257.19:57:35.93#ibcon#enter sib2, iclass 14, count 2 2006.257.19:57:35.93#ibcon#flushed, iclass 14, count 2 2006.257.19:57:35.93#ibcon#about to write, iclass 14, count 2 2006.257.19:57:35.93#ibcon#wrote, iclass 14, count 2 2006.257.19:57:35.93#ibcon#about to read 3, iclass 14, count 2 2006.257.19:57:35.96#ibcon#read 3, iclass 14, count 2 2006.257.19:57:35.96#ibcon#about to read 4, iclass 14, count 2 2006.257.19:57:35.96#ibcon#read 4, iclass 14, count 2 2006.257.19:57:35.96#ibcon#about to read 5, iclass 14, count 2 2006.257.19:57:35.96#ibcon#read 5, iclass 14, count 2 2006.257.19:57:35.96#ibcon#about to read 6, iclass 14, count 2 2006.257.19:57:35.96#ibcon#read 6, iclass 14, count 2 2006.257.19:57:35.96#ibcon#end of sib2, iclass 14, count 2 2006.257.19:57:35.96#ibcon#*after write, iclass 14, count 2 2006.257.19:57:35.96#ibcon#*before return 0, iclass 14, count 2 2006.257.19:57:35.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:57:35.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.19:57:35.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.19:57:35.96#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:35.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:57:36.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:57:36.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:57:36.08#ibcon#enter wrdev, iclass 14, count 0 2006.257.19:57:36.08#ibcon#first serial, iclass 14, count 0 2006.257.19:57:36.08#ibcon#enter sib2, iclass 14, count 0 2006.257.19:57:36.08#ibcon#flushed, iclass 14, count 0 2006.257.19:57:36.08#ibcon#about to write, iclass 14, count 0 2006.257.19:57:36.08#ibcon#wrote, iclass 14, count 0 2006.257.19:57:36.08#ibcon#about to read 3, iclass 14, count 0 2006.257.19:57:36.10#ibcon#read 3, iclass 14, count 0 2006.257.19:57:36.10#ibcon#about to read 4, iclass 14, count 0 2006.257.19:57:36.10#ibcon#read 4, iclass 14, count 0 2006.257.19:57:36.10#ibcon#about to read 5, iclass 14, count 0 2006.257.19:57:36.10#ibcon#read 5, iclass 14, count 0 2006.257.19:57:36.10#ibcon#about to read 6, iclass 14, count 0 2006.257.19:57:36.10#ibcon#read 6, iclass 14, count 0 2006.257.19:57:36.10#ibcon#end of sib2, iclass 14, count 0 2006.257.19:57:36.10#ibcon#*mode == 0, iclass 14, count 0 2006.257.19:57:36.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.19:57:36.10#ibcon#[25=USB\r\n] 2006.257.19:57:36.10#ibcon#*before write, iclass 14, count 0 2006.257.19:57:36.10#ibcon#enter sib2, iclass 14, count 0 2006.257.19:57:36.10#ibcon#flushed, iclass 14, count 0 2006.257.19:57:36.10#ibcon#about to write, iclass 14, count 0 2006.257.19:57:36.10#ibcon#wrote, iclass 14, count 0 2006.257.19:57:36.10#ibcon#about to read 3, iclass 14, count 0 2006.257.19:57:36.13#ibcon#read 3, iclass 14, count 0 2006.257.19:57:36.13#ibcon#about to read 4, iclass 14, count 0 2006.257.19:57:36.13#ibcon#read 4, iclass 14, count 0 2006.257.19:57:36.13#ibcon#about to read 5, iclass 14, count 0 2006.257.19:57:36.13#ibcon#read 5, iclass 14, count 0 2006.257.19:57:36.13#ibcon#about to read 6, iclass 14, count 0 2006.257.19:57:36.13#ibcon#read 6, iclass 14, count 0 2006.257.19:57:36.13#ibcon#end of sib2, iclass 14, count 0 2006.257.19:57:36.13#ibcon#*after write, iclass 14, count 0 2006.257.19:57:36.13#ibcon#*before return 0, iclass 14, count 0 2006.257.19:57:36.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:57:36.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.19:57:36.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.19:57:36.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.19:57:36.13$vck44/vblo=1,629.99 2006.257.19:57:36.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.19:57:36.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.19:57:36.13#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:36.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:57:36.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:57:36.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:57:36.13#ibcon#enter wrdev, iclass 16, count 0 2006.257.19:57:36.13#ibcon#first serial, iclass 16, count 0 2006.257.19:57:36.13#ibcon#enter sib2, iclass 16, count 0 2006.257.19:57:36.13#ibcon#flushed, iclass 16, count 0 2006.257.19:57:36.13#ibcon#about to write, iclass 16, count 0 2006.257.19:57:36.13#ibcon#wrote, iclass 16, count 0 2006.257.19:57:36.13#ibcon#about to read 3, iclass 16, count 0 2006.257.19:57:36.15#ibcon#read 3, iclass 16, count 0 2006.257.19:57:36.15#ibcon#about to read 4, iclass 16, count 0 2006.257.19:57:36.15#ibcon#read 4, iclass 16, count 0 2006.257.19:57:36.15#ibcon#about to read 5, iclass 16, count 0 2006.257.19:57:36.15#ibcon#read 5, iclass 16, count 0 2006.257.19:57:36.15#ibcon#about to read 6, iclass 16, count 0 2006.257.19:57:36.15#ibcon#read 6, iclass 16, count 0 2006.257.19:57:36.15#ibcon#end of sib2, iclass 16, count 0 2006.257.19:57:36.15#ibcon#*mode == 0, iclass 16, count 0 2006.257.19:57:36.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.19:57:36.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.19:57:36.15#ibcon#*before write, iclass 16, count 0 2006.257.19:57:36.15#ibcon#enter sib2, iclass 16, count 0 2006.257.19:57:36.15#ibcon#flushed, iclass 16, count 0 2006.257.19:57:36.15#ibcon#about to write, iclass 16, count 0 2006.257.19:57:36.15#ibcon#wrote, iclass 16, count 0 2006.257.19:57:36.15#ibcon#about to read 3, iclass 16, count 0 2006.257.19:57:36.19#ibcon#read 3, iclass 16, count 0 2006.257.19:57:36.19#ibcon#about to read 4, iclass 16, count 0 2006.257.19:57:36.19#ibcon#read 4, iclass 16, count 0 2006.257.19:57:36.19#ibcon#about to read 5, iclass 16, count 0 2006.257.19:57:36.19#ibcon#read 5, iclass 16, count 0 2006.257.19:57:36.19#ibcon#about to read 6, iclass 16, count 0 2006.257.19:57:36.19#ibcon#read 6, iclass 16, count 0 2006.257.19:57:36.19#ibcon#end of sib2, iclass 16, count 0 2006.257.19:57:36.19#ibcon#*after write, iclass 16, count 0 2006.257.19:57:36.19#ibcon#*before return 0, iclass 16, count 0 2006.257.19:57:36.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:57:36.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.19:57:36.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.19:57:36.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.19:57:36.19$vck44/vb=1,4 2006.257.19:57:36.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.19:57:36.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.19:57:36.19#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:36.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:57:36.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:57:36.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:57:36.19#ibcon#enter wrdev, iclass 18, count 2 2006.257.19:57:36.19#ibcon#first serial, iclass 18, count 2 2006.257.19:57:36.19#ibcon#enter sib2, iclass 18, count 2 2006.257.19:57:36.19#ibcon#flushed, iclass 18, count 2 2006.257.19:57:36.19#ibcon#about to write, iclass 18, count 2 2006.257.19:57:36.19#ibcon#wrote, iclass 18, count 2 2006.257.19:57:36.19#ibcon#about to read 3, iclass 18, count 2 2006.257.19:57:36.21#ibcon#read 3, iclass 18, count 2 2006.257.19:57:36.21#ibcon#about to read 4, iclass 18, count 2 2006.257.19:57:36.21#ibcon#read 4, iclass 18, count 2 2006.257.19:57:36.21#ibcon#about to read 5, iclass 18, count 2 2006.257.19:57:36.21#ibcon#read 5, iclass 18, count 2 2006.257.19:57:36.21#ibcon#about to read 6, iclass 18, count 2 2006.257.19:57:36.21#ibcon#read 6, iclass 18, count 2 2006.257.19:57:36.21#ibcon#end of sib2, iclass 18, count 2 2006.257.19:57:36.21#ibcon#*mode == 0, iclass 18, count 2 2006.257.19:57:36.21#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.19:57:36.21#ibcon#[27=AT01-04\r\n] 2006.257.19:57:36.21#ibcon#*before write, iclass 18, count 2 2006.257.19:57:36.21#ibcon#enter sib2, iclass 18, count 2 2006.257.19:57:36.21#ibcon#flushed, iclass 18, count 2 2006.257.19:57:36.21#ibcon#about to write, iclass 18, count 2 2006.257.19:57:36.21#ibcon#wrote, iclass 18, count 2 2006.257.19:57:36.21#ibcon#about to read 3, iclass 18, count 2 2006.257.19:57:36.24#ibcon#read 3, iclass 18, count 2 2006.257.19:57:36.24#ibcon#about to read 4, iclass 18, count 2 2006.257.19:57:36.24#ibcon#read 4, iclass 18, count 2 2006.257.19:57:36.24#ibcon#about to read 5, iclass 18, count 2 2006.257.19:57:36.24#ibcon#read 5, iclass 18, count 2 2006.257.19:57:36.24#ibcon#about to read 6, iclass 18, count 2 2006.257.19:57:36.24#ibcon#read 6, iclass 18, count 2 2006.257.19:57:36.24#ibcon#end of sib2, iclass 18, count 2 2006.257.19:57:36.24#ibcon#*after write, iclass 18, count 2 2006.257.19:57:36.24#ibcon#*before return 0, iclass 18, count 2 2006.257.19:57:36.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:57:36.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.19:57:36.24#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.19:57:36.24#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:36.24#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:57:36.36#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:57:36.36#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:57:36.36#ibcon#enter wrdev, iclass 18, count 0 2006.257.19:57:36.36#ibcon#first serial, iclass 18, count 0 2006.257.19:57:36.36#ibcon#enter sib2, iclass 18, count 0 2006.257.19:57:36.36#ibcon#flushed, iclass 18, count 0 2006.257.19:57:36.36#ibcon#about to write, iclass 18, count 0 2006.257.19:57:36.36#ibcon#wrote, iclass 18, count 0 2006.257.19:57:36.36#ibcon#about to read 3, iclass 18, count 0 2006.257.19:57:36.38#ibcon#read 3, iclass 18, count 0 2006.257.19:57:36.38#ibcon#about to read 4, iclass 18, count 0 2006.257.19:57:36.38#ibcon#read 4, iclass 18, count 0 2006.257.19:57:36.38#ibcon#about to read 5, iclass 18, count 0 2006.257.19:57:36.38#ibcon#read 5, iclass 18, count 0 2006.257.19:57:36.38#ibcon#about to read 6, iclass 18, count 0 2006.257.19:57:36.38#ibcon#read 6, iclass 18, count 0 2006.257.19:57:36.38#ibcon#end of sib2, iclass 18, count 0 2006.257.19:57:36.38#ibcon#*mode == 0, iclass 18, count 0 2006.257.19:57:36.38#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.19:57:36.38#ibcon#[27=USB\r\n] 2006.257.19:57:36.38#ibcon#*before write, iclass 18, count 0 2006.257.19:57:36.38#ibcon#enter sib2, iclass 18, count 0 2006.257.19:57:36.38#ibcon#flushed, iclass 18, count 0 2006.257.19:57:36.38#ibcon#about to write, iclass 18, count 0 2006.257.19:57:36.38#ibcon#wrote, iclass 18, count 0 2006.257.19:57:36.38#ibcon#about to read 3, iclass 18, count 0 2006.257.19:57:36.41#ibcon#read 3, iclass 18, count 0 2006.257.19:57:36.41#ibcon#about to read 4, iclass 18, count 0 2006.257.19:57:36.41#ibcon#read 4, iclass 18, count 0 2006.257.19:57:36.41#ibcon#about to read 5, iclass 18, count 0 2006.257.19:57:36.41#ibcon#read 5, iclass 18, count 0 2006.257.19:57:36.41#ibcon#about to read 6, iclass 18, count 0 2006.257.19:57:36.41#ibcon#read 6, iclass 18, count 0 2006.257.19:57:36.41#ibcon#end of sib2, iclass 18, count 0 2006.257.19:57:36.41#ibcon#*after write, iclass 18, count 0 2006.257.19:57:36.41#ibcon#*before return 0, iclass 18, count 0 2006.257.19:57:36.41#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:57:36.41#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.19:57:36.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.19:57:36.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.19:57:36.41$vck44/vblo=2,634.99 2006.257.19:57:36.41#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.19:57:36.41#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.19:57:36.41#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:36.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:36.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:36.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:36.41#ibcon#enter wrdev, iclass 20, count 0 2006.257.19:57:36.41#ibcon#first serial, iclass 20, count 0 2006.257.19:57:36.41#ibcon#enter sib2, iclass 20, count 0 2006.257.19:57:36.41#ibcon#flushed, iclass 20, count 0 2006.257.19:57:36.41#ibcon#about to write, iclass 20, count 0 2006.257.19:57:36.41#ibcon#wrote, iclass 20, count 0 2006.257.19:57:36.41#ibcon#about to read 3, iclass 20, count 0 2006.257.19:57:36.43#ibcon#read 3, iclass 20, count 0 2006.257.19:57:36.43#ibcon#about to read 4, iclass 20, count 0 2006.257.19:57:36.43#ibcon#read 4, iclass 20, count 0 2006.257.19:57:36.43#ibcon#about to read 5, iclass 20, count 0 2006.257.19:57:36.43#ibcon#read 5, iclass 20, count 0 2006.257.19:57:36.43#ibcon#about to read 6, iclass 20, count 0 2006.257.19:57:36.43#ibcon#read 6, iclass 20, count 0 2006.257.19:57:36.43#ibcon#end of sib2, iclass 20, count 0 2006.257.19:57:36.43#ibcon#*mode == 0, iclass 20, count 0 2006.257.19:57:36.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.19:57:36.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.19:57:36.43#ibcon#*before write, iclass 20, count 0 2006.257.19:57:36.43#ibcon#enter sib2, iclass 20, count 0 2006.257.19:57:36.43#ibcon#flushed, iclass 20, count 0 2006.257.19:57:36.43#ibcon#about to write, iclass 20, count 0 2006.257.19:57:36.43#ibcon#wrote, iclass 20, count 0 2006.257.19:57:36.43#ibcon#about to read 3, iclass 20, count 0 2006.257.19:57:36.47#ibcon#read 3, iclass 20, count 0 2006.257.19:57:36.47#ibcon#about to read 4, iclass 20, count 0 2006.257.19:57:36.47#ibcon#read 4, iclass 20, count 0 2006.257.19:57:36.47#ibcon#about to read 5, iclass 20, count 0 2006.257.19:57:36.47#ibcon#read 5, iclass 20, count 0 2006.257.19:57:36.47#ibcon#about to read 6, iclass 20, count 0 2006.257.19:57:36.47#ibcon#read 6, iclass 20, count 0 2006.257.19:57:36.47#ibcon#end of sib2, iclass 20, count 0 2006.257.19:57:36.47#ibcon#*after write, iclass 20, count 0 2006.257.19:57:36.47#ibcon#*before return 0, iclass 20, count 0 2006.257.19:57:36.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:36.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.19:57:36.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.19:57:36.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.19:57:36.47$vck44/vb=2,5 2006.257.19:57:36.47#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.19:57:36.47#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.19:57:36.47#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:36.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:36.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:36.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:36.53#ibcon#enter wrdev, iclass 22, count 2 2006.257.19:57:36.53#ibcon#first serial, iclass 22, count 2 2006.257.19:57:36.53#ibcon#enter sib2, iclass 22, count 2 2006.257.19:57:36.53#ibcon#flushed, iclass 22, count 2 2006.257.19:57:36.53#ibcon#about to write, iclass 22, count 2 2006.257.19:57:36.53#ibcon#wrote, iclass 22, count 2 2006.257.19:57:36.53#ibcon#about to read 3, iclass 22, count 2 2006.257.19:57:36.55#ibcon#read 3, iclass 22, count 2 2006.257.19:57:36.55#ibcon#about to read 4, iclass 22, count 2 2006.257.19:57:36.55#ibcon#read 4, iclass 22, count 2 2006.257.19:57:36.55#ibcon#about to read 5, iclass 22, count 2 2006.257.19:57:36.55#ibcon#read 5, iclass 22, count 2 2006.257.19:57:36.55#ibcon#about to read 6, iclass 22, count 2 2006.257.19:57:36.55#ibcon#read 6, iclass 22, count 2 2006.257.19:57:36.55#ibcon#end of sib2, iclass 22, count 2 2006.257.19:57:36.55#ibcon#*mode == 0, iclass 22, count 2 2006.257.19:57:36.55#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.19:57:36.55#ibcon#[27=AT02-05\r\n] 2006.257.19:57:36.55#ibcon#*before write, iclass 22, count 2 2006.257.19:57:36.55#ibcon#enter sib2, iclass 22, count 2 2006.257.19:57:36.55#ibcon#flushed, iclass 22, count 2 2006.257.19:57:36.55#ibcon#about to write, iclass 22, count 2 2006.257.19:57:36.55#ibcon#wrote, iclass 22, count 2 2006.257.19:57:36.55#ibcon#about to read 3, iclass 22, count 2 2006.257.19:57:36.58#ibcon#read 3, iclass 22, count 2 2006.257.19:57:36.58#ibcon#about to read 4, iclass 22, count 2 2006.257.19:57:36.58#ibcon#read 4, iclass 22, count 2 2006.257.19:57:36.58#ibcon#about to read 5, iclass 22, count 2 2006.257.19:57:36.58#ibcon#read 5, iclass 22, count 2 2006.257.19:57:36.58#ibcon#about to read 6, iclass 22, count 2 2006.257.19:57:36.58#ibcon#read 6, iclass 22, count 2 2006.257.19:57:36.58#ibcon#end of sib2, iclass 22, count 2 2006.257.19:57:36.58#ibcon#*after write, iclass 22, count 2 2006.257.19:57:36.58#ibcon#*before return 0, iclass 22, count 2 2006.257.19:57:36.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:36.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.19:57:36.58#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.19:57:36.58#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:36.58#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:36.70#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:36.70#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:36.70#ibcon#enter wrdev, iclass 22, count 0 2006.257.19:57:36.70#ibcon#first serial, iclass 22, count 0 2006.257.19:57:36.70#ibcon#enter sib2, iclass 22, count 0 2006.257.19:57:36.70#ibcon#flushed, iclass 22, count 0 2006.257.19:57:36.70#ibcon#about to write, iclass 22, count 0 2006.257.19:57:36.70#ibcon#wrote, iclass 22, count 0 2006.257.19:57:36.70#ibcon#about to read 3, iclass 22, count 0 2006.257.19:57:36.72#ibcon#read 3, iclass 22, count 0 2006.257.19:57:36.72#ibcon#about to read 4, iclass 22, count 0 2006.257.19:57:36.72#ibcon#read 4, iclass 22, count 0 2006.257.19:57:36.72#ibcon#about to read 5, iclass 22, count 0 2006.257.19:57:36.72#ibcon#read 5, iclass 22, count 0 2006.257.19:57:36.72#ibcon#about to read 6, iclass 22, count 0 2006.257.19:57:36.72#ibcon#read 6, iclass 22, count 0 2006.257.19:57:36.72#ibcon#end of sib2, iclass 22, count 0 2006.257.19:57:36.72#ibcon#*mode == 0, iclass 22, count 0 2006.257.19:57:36.72#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.19:57:36.72#ibcon#[27=USB\r\n] 2006.257.19:57:36.72#ibcon#*before write, iclass 22, count 0 2006.257.19:57:36.72#ibcon#enter sib2, iclass 22, count 0 2006.257.19:57:36.72#ibcon#flushed, iclass 22, count 0 2006.257.19:57:36.72#ibcon#about to write, iclass 22, count 0 2006.257.19:57:36.72#ibcon#wrote, iclass 22, count 0 2006.257.19:57:36.72#ibcon#about to read 3, iclass 22, count 0 2006.257.19:57:36.75#ibcon#read 3, iclass 22, count 0 2006.257.19:57:36.75#ibcon#about to read 4, iclass 22, count 0 2006.257.19:57:36.75#ibcon#read 4, iclass 22, count 0 2006.257.19:57:36.75#ibcon#about to read 5, iclass 22, count 0 2006.257.19:57:36.75#ibcon#read 5, iclass 22, count 0 2006.257.19:57:36.75#ibcon#about to read 6, iclass 22, count 0 2006.257.19:57:36.75#ibcon#read 6, iclass 22, count 0 2006.257.19:57:36.75#ibcon#end of sib2, iclass 22, count 0 2006.257.19:57:36.75#ibcon#*after write, iclass 22, count 0 2006.257.19:57:36.75#ibcon#*before return 0, iclass 22, count 0 2006.257.19:57:36.75#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:36.75#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.19:57:36.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.19:57:36.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.19:57:36.75$vck44/vblo=3,649.99 2006.257.19:57:36.75#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.19:57:36.75#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.19:57:36.75#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:36.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:36.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:36.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:36.75#ibcon#enter wrdev, iclass 24, count 0 2006.257.19:57:36.75#ibcon#first serial, iclass 24, count 0 2006.257.19:57:36.75#ibcon#enter sib2, iclass 24, count 0 2006.257.19:57:36.75#ibcon#flushed, iclass 24, count 0 2006.257.19:57:36.75#ibcon#about to write, iclass 24, count 0 2006.257.19:57:36.75#ibcon#wrote, iclass 24, count 0 2006.257.19:57:36.75#ibcon#about to read 3, iclass 24, count 0 2006.257.19:57:36.77#ibcon#read 3, iclass 24, count 0 2006.257.19:57:36.77#ibcon#about to read 4, iclass 24, count 0 2006.257.19:57:36.77#ibcon#read 4, iclass 24, count 0 2006.257.19:57:36.77#ibcon#about to read 5, iclass 24, count 0 2006.257.19:57:36.77#ibcon#read 5, iclass 24, count 0 2006.257.19:57:36.77#ibcon#about to read 6, iclass 24, count 0 2006.257.19:57:36.77#ibcon#read 6, iclass 24, count 0 2006.257.19:57:36.77#ibcon#end of sib2, iclass 24, count 0 2006.257.19:57:36.77#ibcon#*mode == 0, iclass 24, count 0 2006.257.19:57:36.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.19:57:36.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.19:57:36.77#ibcon#*before write, iclass 24, count 0 2006.257.19:57:36.77#ibcon#enter sib2, iclass 24, count 0 2006.257.19:57:36.77#ibcon#flushed, iclass 24, count 0 2006.257.19:57:36.77#ibcon#about to write, iclass 24, count 0 2006.257.19:57:36.77#ibcon#wrote, iclass 24, count 0 2006.257.19:57:36.77#ibcon#about to read 3, iclass 24, count 0 2006.257.19:57:36.81#ibcon#read 3, iclass 24, count 0 2006.257.19:57:36.81#ibcon#about to read 4, iclass 24, count 0 2006.257.19:57:36.81#ibcon#read 4, iclass 24, count 0 2006.257.19:57:36.81#ibcon#about to read 5, iclass 24, count 0 2006.257.19:57:36.81#ibcon#read 5, iclass 24, count 0 2006.257.19:57:36.81#ibcon#about to read 6, iclass 24, count 0 2006.257.19:57:36.81#ibcon#read 6, iclass 24, count 0 2006.257.19:57:36.81#ibcon#end of sib2, iclass 24, count 0 2006.257.19:57:36.81#ibcon#*after write, iclass 24, count 0 2006.257.19:57:36.81#ibcon#*before return 0, iclass 24, count 0 2006.257.19:57:36.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:36.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.19:57:36.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.19:57:36.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.19:57:36.81$vck44/vb=3,4 2006.257.19:57:36.81#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.19:57:36.81#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.19:57:36.81#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:36.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:36.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:36.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:36.87#ibcon#enter wrdev, iclass 26, count 2 2006.257.19:57:36.87#ibcon#first serial, iclass 26, count 2 2006.257.19:57:36.87#ibcon#enter sib2, iclass 26, count 2 2006.257.19:57:36.87#ibcon#flushed, iclass 26, count 2 2006.257.19:57:36.87#ibcon#about to write, iclass 26, count 2 2006.257.19:57:36.87#ibcon#wrote, iclass 26, count 2 2006.257.19:57:36.87#ibcon#about to read 3, iclass 26, count 2 2006.257.19:57:36.89#ibcon#read 3, iclass 26, count 2 2006.257.19:57:36.89#ibcon#about to read 4, iclass 26, count 2 2006.257.19:57:36.89#ibcon#read 4, iclass 26, count 2 2006.257.19:57:36.89#ibcon#about to read 5, iclass 26, count 2 2006.257.19:57:36.89#ibcon#read 5, iclass 26, count 2 2006.257.19:57:36.89#ibcon#about to read 6, iclass 26, count 2 2006.257.19:57:36.89#ibcon#read 6, iclass 26, count 2 2006.257.19:57:36.89#ibcon#end of sib2, iclass 26, count 2 2006.257.19:57:36.89#ibcon#*mode == 0, iclass 26, count 2 2006.257.19:57:36.89#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.19:57:36.89#ibcon#[27=AT03-04\r\n] 2006.257.19:57:36.89#ibcon#*before write, iclass 26, count 2 2006.257.19:57:36.89#ibcon#enter sib2, iclass 26, count 2 2006.257.19:57:36.89#ibcon#flushed, iclass 26, count 2 2006.257.19:57:36.89#ibcon#about to write, iclass 26, count 2 2006.257.19:57:36.89#ibcon#wrote, iclass 26, count 2 2006.257.19:57:36.89#ibcon#about to read 3, iclass 26, count 2 2006.257.19:57:36.92#ibcon#read 3, iclass 26, count 2 2006.257.19:57:36.92#ibcon#about to read 4, iclass 26, count 2 2006.257.19:57:36.92#ibcon#read 4, iclass 26, count 2 2006.257.19:57:36.92#ibcon#about to read 5, iclass 26, count 2 2006.257.19:57:36.92#ibcon#read 5, iclass 26, count 2 2006.257.19:57:36.92#ibcon#about to read 6, iclass 26, count 2 2006.257.19:57:36.92#ibcon#read 6, iclass 26, count 2 2006.257.19:57:36.92#ibcon#end of sib2, iclass 26, count 2 2006.257.19:57:36.92#ibcon#*after write, iclass 26, count 2 2006.257.19:57:36.92#ibcon#*before return 0, iclass 26, count 2 2006.257.19:57:36.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:36.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.19:57:36.92#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.19:57:36.92#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:36.92#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:37.04#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:37.04#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:37.04#ibcon#enter wrdev, iclass 26, count 0 2006.257.19:57:37.04#ibcon#first serial, iclass 26, count 0 2006.257.19:57:37.04#ibcon#enter sib2, iclass 26, count 0 2006.257.19:57:37.04#ibcon#flushed, iclass 26, count 0 2006.257.19:57:37.04#ibcon#about to write, iclass 26, count 0 2006.257.19:57:37.04#ibcon#wrote, iclass 26, count 0 2006.257.19:57:37.04#ibcon#about to read 3, iclass 26, count 0 2006.257.19:57:37.06#ibcon#read 3, iclass 26, count 0 2006.257.19:57:37.06#ibcon#about to read 4, iclass 26, count 0 2006.257.19:57:37.06#ibcon#read 4, iclass 26, count 0 2006.257.19:57:37.06#ibcon#about to read 5, iclass 26, count 0 2006.257.19:57:37.06#ibcon#read 5, iclass 26, count 0 2006.257.19:57:37.06#ibcon#about to read 6, iclass 26, count 0 2006.257.19:57:37.06#ibcon#read 6, iclass 26, count 0 2006.257.19:57:37.06#ibcon#end of sib2, iclass 26, count 0 2006.257.19:57:37.06#ibcon#*mode == 0, iclass 26, count 0 2006.257.19:57:37.06#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.19:57:37.06#ibcon#[27=USB\r\n] 2006.257.19:57:37.06#ibcon#*before write, iclass 26, count 0 2006.257.19:57:37.06#ibcon#enter sib2, iclass 26, count 0 2006.257.19:57:37.06#ibcon#flushed, iclass 26, count 0 2006.257.19:57:37.06#ibcon#about to write, iclass 26, count 0 2006.257.19:57:37.06#ibcon#wrote, iclass 26, count 0 2006.257.19:57:37.06#ibcon#about to read 3, iclass 26, count 0 2006.257.19:57:37.09#ibcon#read 3, iclass 26, count 0 2006.257.19:57:37.09#ibcon#about to read 4, iclass 26, count 0 2006.257.19:57:37.09#ibcon#read 4, iclass 26, count 0 2006.257.19:57:37.09#ibcon#about to read 5, iclass 26, count 0 2006.257.19:57:37.09#ibcon#read 5, iclass 26, count 0 2006.257.19:57:37.09#ibcon#about to read 6, iclass 26, count 0 2006.257.19:57:37.09#ibcon#read 6, iclass 26, count 0 2006.257.19:57:37.09#ibcon#end of sib2, iclass 26, count 0 2006.257.19:57:37.09#ibcon#*after write, iclass 26, count 0 2006.257.19:57:37.09#ibcon#*before return 0, iclass 26, count 0 2006.257.19:57:37.09#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:37.09#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.19:57:37.09#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.19:57:37.09#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.19:57:37.09$vck44/vblo=4,679.99 2006.257.19:57:37.09#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.19:57:37.09#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.19:57:37.09#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:37.09#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:37.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:37.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:37.09#ibcon#enter wrdev, iclass 28, count 0 2006.257.19:57:37.09#ibcon#first serial, iclass 28, count 0 2006.257.19:57:37.09#ibcon#enter sib2, iclass 28, count 0 2006.257.19:57:37.09#ibcon#flushed, iclass 28, count 0 2006.257.19:57:37.09#ibcon#about to write, iclass 28, count 0 2006.257.19:57:37.09#ibcon#wrote, iclass 28, count 0 2006.257.19:57:37.09#ibcon#about to read 3, iclass 28, count 0 2006.257.19:57:37.11#ibcon#read 3, iclass 28, count 0 2006.257.19:57:37.11#ibcon#about to read 4, iclass 28, count 0 2006.257.19:57:37.11#ibcon#read 4, iclass 28, count 0 2006.257.19:57:37.11#ibcon#about to read 5, iclass 28, count 0 2006.257.19:57:37.11#ibcon#read 5, iclass 28, count 0 2006.257.19:57:37.11#ibcon#about to read 6, iclass 28, count 0 2006.257.19:57:37.11#ibcon#read 6, iclass 28, count 0 2006.257.19:57:37.11#ibcon#end of sib2, iclass 28, count 0 2006.257.19:57:37.11#ibcon#*mode == 0, iclass 28, count 0 2006.257.19:57:37.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.19:57:37.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.19:57:37.11#ibcon#*before write, iclass 28, count 0 2006.257.19:57:37.11#ibcon#enter sib2, iclass 28, count 0 2006.257.19:57:37.11#ibcon#flushed, iclass 28, count 0 2006.257.19:57:37.11#ibcon#about to write, iclass 28, count 0 2006.257.19:57:37.11#ibcon#wrote, iclass 28, count 0 2006.257.19:57:37.11#ibcon#about to read 3, iclass 28, count 0 2006.257.19:57:37.15#ibcon#read 3, iclass 28, count 0 2006.257.19:57:37.15#ibcon#about to read 4, iclass 28, count 0 2006.257.19:57:37.15#ibcon#read 4, iclass 28, count 0 2006.257.19:57:37.15#ibcon#about to read 5, iclass 28, count 0 2006.257.19:57:37.15#ibcon#read 5, iclass 28, count 0 2006.257.19:57:37.15#ibcon#about to read 6, iclass 28, count 0 2006.257.19:57:37.15#ibcon#read 6, iclass 28, count 0 2006.257.19:57:37.15#ibcon#end of sib2, iclass 28, count 0 2006.257.19:57:37.15#ibcon#*after write, iclass 28, count 0 2006.257.19:57:37.15#ibcon#*before return 0, iclass 28, count 0 2006.257.19:57:37.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:37.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.19:57:37.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.19:57:37.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.19:57:37.15$vck44/vb=4,5 2006.257.19:57:37.15#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.19:57:37.15#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.19:57:37.15#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:37.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:37.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:37.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:37.21#ibcon#enter wrdev, iclass 30, count 2 2006.257.19:57:37.21#ibcon#first serial, iclass 30, count 2 2006.257.19:57:37.21#ibcon#enter sib2, iclass 30, count 2 2006.257.19:57:37.21#ibcon#flushed, iclass 30, count 2 2006.257.19:57:37.21#ibcon#about to write, iclass 30, count 2 2006.257.19:57:37.21#ibcon#wrote, iclass 30, count 2 2006.257.19:57:37.21#ibcon#about to read 3, iclass 30, count 2 2006.257.19:57:37.23#ibcon#read 3, iclass 30, count 2 2006.257.19:57:37.23#ibcon#about to read 4, iclass 30, count 2 2006.257.19:57:37.23#ibcon#read 4, iclass 30, count 2 2006.257.19:57:37.23#ibcon#about to read 5, iclass 30, count 2 2006.257.19:57:37.23#ibcon#read 5, iclass 30, count 2 2006.257.19:57:37.23#ibcon#about to read 6, iclass 30, count 2 2006.257.19:57:37.23#ibcon#read 6, iclass 30, count 2 2006.257.19:57:37.23#ibcon#end of sib2, iclass 30, count 2 2006.257.19:57:37.23#ibcon#*mode == 0, iclass 30, count 2 2006.257.19:57:37.23#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.19:57:37.23#ibcon#[27=AT04-05\r\n] 2006.257.19:57:37.23#ibcon#*before write, iclass 30, count 2 2006.257.19:57:37.23#ibcon#enter sib2, iclass 30, count 2 2006.257.19:57:37.23#ibcon#flushed, iclass 30, count 2 2006.257.19:57:37.23#ibcon#about to write, iclass 30, count 2 2006.257.19:57:37.23#ibcon#wrote, iclass 30, count 2 2006.257.19:57:37.23#ibcon#about to read 3, iclass 30, count 2 2006.257.19:57:37.26#ibcon#read 3, iclass 30, count 2 2006.257.19:57:37.26#ibcon#about to read 4, iclass 30, count 2 2006.257.19:57:37.26#ibcon#read 4, iclass 30, count 2 2006.257.19:57:37.26#ibcon#about to read 5, iclass 30, count 2 2006.257.19:57:37.26#ibcon#read 5, iclass 30, count 2 2006.257.19:57:37.26#ibcon#about to read 6, iclass 30, count 2 2006.257.19:57:37.26#ibcon#read 6, iclass 30, count 2 2006.257.19:57:37.26#ibcon#end of sib2, iclass 30, count 2 2006.257.19:57:37.26#ibcon#*after write, iclass 30, count 2 2006.257.19:57:37.26#ibcon#*before return 0, iclass 30, count 2 2006.257.19:57:37.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:37.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.19:57:37.26#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.19:57:37.26#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:37.26#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:37.38#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:37.38#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:37.38#ibcon#enter wrdev, iclass 30, count 0 2006.257.19:57:37.38#ibcon#first serial, iclass 30, count 0 2006.257.19:57:37.38#ibcon#enter sib2, iclass 30, count 0 2006.257.19:57:37.38#ibcon#flushed, iclass 30, count 0 2006.257.19:57:37.38#ibcon#about to write, iclass 30, count 0 2006.257.19:57:37.38#ibcon#wrote, iclass 30, count 0 2006.257.19:57:37.38#ibcon#about to read 3, iclass 30, count 0 2006.257.19:57:37.40#ibcon#read 3, iclass 30, count 0 2006.257.19:57:37.40#ibcon#about to read 4, iclass 30, count 0 2006.257.19:57:37.40#ibcon#read 4, iclass 30, count 0 2006.257.19:57:37.40#ibcon#about to read 5, iclass 30, count 0 2006.257.19:57:37.40#ibcon#read 5, iclass 30, count 0 2006.257.19:57:37.40#ibcon#about to read 6, iclass 30, count 0 2006.257.19:57:37.40#ibcon#read 6, iclass 30, count 0 2006.257.19:57:37.40#ibcon#end of sib2, iclass 30, count 0 2006.257.19:57:37.40#ibcon#*mode == 0, iclass 30, count 0 2006.257.19:57:37.40#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.19:57:37.40#ibcon#[27=USB\r\n] 2006.257.19:57:37.40#ibcon#*before write, iclass 30, count 0 2006.257.19:57:37.40#ibcon#enter sib2, iclass 30, count 0 2006.257.19:57:37.40#ibcon#flushed, iclass 30, count 0 2006.257.19:57:37.40#ibcon#about to write, iclass 30, count 0 2006.257.19:57:37.40#ibcon#wrote, iclass 30, count 0 2006.257.19:57:37.40#ibcon#about to read 3, iclass 30, count 0 2006.257.19:57:37.43#ibcon#read 3, iclass 30, count 0 2006.257.19:57:37.43#ibcon#about to read 4, iclass 30, count 0 2006.257.19:57:37.43#ibcon#read 4, iclass 30, count 0 2006.257.19:57:37.43#ibcon#about to read 5, iclass 30, count 0 2006.257.19:57:37.43#ibcon#read 5, iclass 30, count 0 2006.257.19:57:37.43#ibcon#about to read 6, iclass 30, count 0 2006.257.19:57:37.43#ibcon#read 6, iclass 30, count 0 2006.257.19:57:37.43#ibcon#end of sib2, iclass 30, count 0 2006.257.19:57:37.43#ibcon#*after write, iclass 30, count 0 2006.257.19:57:37.43#ibcon#*before return 0, iclass 30, count 0 2006.257.19:57:37.43#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:37.43#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.19:57:37.43#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.19:57:37.43#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.19:57:37.43$vck44/vblo=5,709.99 2006.257.19:57:37.43#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.19:57:37.43#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.19:57:37.43#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:37.43#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:37.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:37.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:37.43#ibcon#enter wrdev, iclass 32, count 0 2006.257.19:57:37.43#ibcon#first serial, iclass 32, count 0 2006.257.19:57:37.43#ibcon#enter sib2, iclass 32, count 0 2006.257.19:57:37.43#ibcon#flushed, iclass 32, count 0 2006.257.19:57:37.43#ibcon#about to write, iclass 32, count 0 2006.257.19:57:37.43#ibcon#wrote, iclass 32, count 0 2006.257.19:57:37.43#ibcon#about to read 3, iclass 32, count 0 2006.257.19:57:37.45#ibcon#read 3, iclass 32, count 0 2006.257.19:57:37.45#ibcon#about to read 4, iclass 32, count 0 2006.257.19:57:37.45#ibcon#read 4, iclass 32, count 0 2006.257.19:57:37.45#ibcon#about to read 5, iclass 32, count 0 2006.257.19:57:37.45#ibcon#read 5, iclass 32, count 0 2006.257.19:57:37.45#ibcon#about to read 6, iclass 32, count 0 2006.257.19:57:37.45#ibcon#read 6, iclass 32, count 0 2006.257.19:57:37.45#ibcon#end of sib2, iclass 32, count 0 2006.257.19:57:37.45#ibcon#*mode == 0, iclass 32, count 0 2006.257.19:57:37.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.19:57:37.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.19:57:37.45#ibcon#*before write, iclass 32, count 0 2006.257.19:57:37.45#ibcon#enter sib2, iclass 32, count 0 2006.257.19:57:37.45#ibcon#flushed, iclass 32, count 0 2006.257.19:57:37.45#ibcon#about to write, iclass 32, count 0 2006.257.19:57:37.45#ibcon#wrote, iclass 32, count 0 2006.257.19:57:37.45#ibcon#about to read 3, iclass 32, count 0 2006.257.19:57:37.49#ibcon#read 3, iclass 32, count 0 2006.257.19:57:37.49#ibcon#about to read 4, iclass 32, count 0 2006.257.19:57:37.49#ibcon#read 4, iclass 32, count 0 2006.257.19:57:37.49#ibcon#about to read 5, iclass 32, count 0 2006.257.19:57:37.49#ibcon#read 5, iclass 32, count 0 2006.257.19:57:37.49#ibcon#about to read 6, iclass 32, count 0 2006.257.19:57:37.49#ibcon#read 6, iclass 32, count 0 2006.257.19:57:37.49#ibcon#end of sib2, iclass 32, count 0 2006.257.19:57:37.49#ibcon#*after write, iclass 32, count 0 2006.257.19:57:37.49#ibcon#*before return 0, iclass 32, count 0 2006.257.19:57:37.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:37.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.19:57:37.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.19:57:37.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.19:57:37.49$vck44/vb=5,4 2006.257.19:57:37.49#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.19:57:37.49#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.19:57:37.49#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:37.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:37.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:37.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:37.55#ibcon#enter wrdev, iclass 34, count 2 2006.257.19:57:37.55#ibcon#first serial, iclass 34, count 2 2006.257.19:57:37.55#ibcon#enter sib2, iclass 34, count 2 2006.257.19:57:37.55#ibcon#flushed, iclass 34, count 2 2006.257.19:57:37.55#ibcon#about to write, iclass 34, count 2 2006.257.19:57:37.55#ibcon#wrote, iclass 34, count 2 2006.257.19:57:37.55#ibcon#about to read 3, iclass 34, count 2 2006.257.19:57:37.57#ibcon#read 3, iclass 34, count 2 2006.257.19:57:37.57#ibcon#about to read 4, iclass 34, count 2 2006.257.19:57:37.57#ibcon#read 4, iclass 34, count 2 2006.257.19:57:37.57#ibcon#about to read 5, iclass 34, count 2 2006.257.19:57:37.57#ibcon#read 5, iclass 34, count 2 2006.257.19:57:37.57#ibcon#about to read 6, iclass 34, count 2 2006.257.19:57:37.57#ibcon#read 6, iclass 34, count 2 2006.257.19:57:37.57#ibcon#end of sib2, iclass 34, count 2 2006.257.19:57:37.57#ibcon#*mode == 0, iclass 34, count 2 2006.257.19:57:37.57#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.19:57:37.57#ibcon#[27=AT05-04\r\n] 2006.257.19:57:37.57#ibcon#*before write, iclass 34, count 2 2006.257.19:57:37.57#ibcon#enter sib2, iclass 34, count 2 2006.257.19:57:37.57#ibcon#flushed, iclass 34, count 2 2006.257.19:57:37.57#ibcon#about to write, iclass 34, count 2 2006.257.19:57:37.57#ibcon#wrote, iclass 34, count 2 2006.257.19:57:37.57#ibcon#about to read 3, iclass 34, count 2 2006.257.19:57:37.60#ibcon#read 3, iclass 34, count 2 2006.257.19:57:37.60#ibcon#about to read 4, iclass 34, count 2 2006.257.19:57:37.60#ibcon#read 4, iclass 34, count 2 2006.257.19:57:37.60#ibcon#about to read 5, iclass 34, count 2 2006.257.19:57:37.60#ibcon#read 5, iclass 34, count 2 2006.257.19:57:37.60#ibcon#about to read 6, iclass 34, count 2 2006.257.19:57:37.60#ibcon#read 6, iclass 34, count 2 2006.257.19:57:37.60#ibcon#end of sib2, iclass 34, count 2 2006.257.19:57:37.60#ibcon#*after write, iclass 34, count 2 2006.257.19:57:37.60#ibcon#*before return 0, iclass 34, count 2 2006.257.19:57:37.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:37.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.19:57:37.60#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.19:57:37.60#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:37.60#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:37.72#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:37.72#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:37.72#ibcon#enter wrdev, iclass 34, count 0 2006.257.19:57:37.72#ibcon#first serial, iclass 34, count 0 2006.257.19:57:37.72#ibcon#enter sib2, iclass 34, count 0 2006.257.19:57:37.72#ibcon#flushed, iclass 34, count 0 2006.257.19:57:37.72#ibcon#about to write, iclass 34, count 0 2006.257.19:57:37.72#ibcon#wrote, iclass 34, count 0 2006.257.19:57:37.72#ibcon#about to read 3, iclass 34, count 0 2006.257.19:57:37.74#ibcon#read 3, iclass 34, count 0 2006.257.19:57:37.74#ibcon#about to read 4, iclass 34, count 0 2006.257.19:57:37.74#ibcon#read 4, iclass 34, count 0 2006.257.19:57:37.74#ibcon#about to read 5, iclass 34, count 0 2006.257.19:57:37.74#ibcon#read 5, iclass 34, count 0 2006.257.19:57:37.74#ibcon#about to read 6, iclass 34, count 0 2006.257.19:57:37.74#ibcon#read 6, iclass 34, count 0 2006.257.19:57:37.74#ibcon#end of sib2, iclass 34, count 0 2006.257.19:57:37.74#ibcon#*mode == 0, iclass 34, count 0 2006.257.19:57:37.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.19:57:37.74#ibcon#[27=USB\r\n] 2006.257.19:57:37.74#ibcon#*before write, iclass 34, count 0 2006.257.19:57:37.74#ibcon#enter sib2, iclass 34, count 0 2006.257.19:57:37.74#ibcon#flushed, iclass 34, count 0 2006.257.19:57:37.74#ibcon#about to write, iclass 34, count 0 2006.257.19:57:37.74#ibcon#wrote, iclass 34, count 0 2006.257.19:57:37.74#ibcon#about to read 3, iclass 34, count 0 2006.257.19:57:37.77#ibcon#read 3, iclass 34, count 0 2006.257.19:57:37.77#ibcon#about to read 4, iclass 34, count 0 2006.257.19:57:37.77#ibcon#read 4, iclass 34, count 0 2006.257.19:57:37.77#ibcon#about to read 5, iclass 34, count 0 2006.257.19:57:37.77#ibcon#read 5, iclass 34, count 0 2006.257.19:57:37.77#ibcon#about to read 6, iclass 34, count 0 2006.257.19:57:37.77#ibcon#read 6, iclass 34, count 0 2006.257.19:57:37.77#ibcon#end of sib2, iclass 34, count 0 2006.257.19:57:37.77#ibcon#*after write, iclass 34, count 0 2006.257.19:57:37.77#ibcon#*before return 0, iclass 34, count 0 2006.257.19:57:37.77#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:37.77#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.19:57:37.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.19:57:37.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.19:57:37.77$vck44/vblo=6,719.99 2006.257.19:57:37.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.19:57:37.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.19:57:37.77#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:37.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:37.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:37.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:37.77#ibcon#enter wrdev, iclass 36, count 0 2006.257.19:57:37.77#ibcon#first serial, iclass 36, count 0 2006.257.19:57:37.77#ibcon#enter sib2, iclass 36, count 0 2006.257.19:57:37.77#ibcon#flushed, iclass 36, count 0 2006.257.19:57:37.77#ibcon#about to write, iclass 36, count 0 2006.257.19:57:37.77#ibcon#wrote, iclass 36, count 0 2006.257.19:57:37.77#ibcon#about to read 3, iclass 36, count 0 2006.257.19:57:37.79#ibcon#read 3, iclass 36, count 0 2006.257.19:57:37.79#ibcon#about to read 4, iclass 36, count 0 2006.257.19:57:37.79#ibcon#read 4, iclass 36, count 0 2006.257.19:57:37.79#ibcon#about to read 5, iclass 36, count 0 2006.257.19:57:37.79#ibcon#read 5, iclass 36, count 0 2006.257.19:57:37.79#ibcon#about to read 6, iclass 36, count 0 2006.257.19:57:37.79#ibcon#read 6, iclass 36, count 0 2006.257.19:57:37.79#ibcon#end of sib2, iclass 36, count 0 2006.257.19:57:37.79#ibcon#*mode == 0, iclass 36, count 0 2006.257.19:57:37.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.19:57:37.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.19:57:37.79#ibcon#*before write, iclass 36, count 0 2006.257.19:57:37.79#ibcon#enter sib2, iclass 36, count 0 2006.257.19:57:37.79#ibcon#flushed, iclass 36, count 0 2006.257.19:57:37.79#ibcon#about to write, iclass 36, count 0 2006.257.19:57:37.79#ibcon#wrote, iclass 36, count 0 2006.257.19:57:37.79#ibcon#about to read 3, iclass 36, count 0 2006.257.19:57:37.83#ibcon#read 3, iclass 36, count 0 2006.257.19:57:37.83#ibcon#about to read 4, iclass 36, count 0 2006.257.19:57:37.83#ibcon#read 4, iclass 36, count 0 2006.257.19:57:37.83#ibcon#about to read 5, iclass 36, count 0 2006.257.19:57:37.83#ibcon#read 5, iclass 36, count 0 2006.257.19:57:37.83#ibcon#about to read 6, iclass 36, count 0 2006.257.19:57:37.83#ibcon#read 6, iclass 36, count 0 2006.257.19:57:37.83#ibcon#end of sib2, iclass 36, count 0 2006.257.19:57:37.83#ibcon#*after write, iclass 36, count 0 2006.257.19:57:37.83#ibcon#*before return 0, iclass 36, count 0 2006.257.19:57:37.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:37.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.19:57:37.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.19:57:37.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.19:57:37.83$vck44/vb=6,4 2006.257.19:57:37.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.19:57:37.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.19:57:37.83#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:37.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:37.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:37.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:37.89#ibcon#enter wrdev, iclass 38, count 2 2006.257.19:57:37.89#ibcon#first serial, iclass 38, count 2 2006.257.19:57:37.89#ibcon#enter sib2, iclass 38, count 2 2006.257.19:57:37.89#ibcon#flushed, iclass 38, count 2 2006.257.19:57:37.89#ibcon#about to write, iclass 38, count 2 2006.257.19:57:37.89#ibcon#wrote, iclass 38, count 2 2006.257.19:57:37.89#ibcon#about to read 3, iclass 38, count 2 2006.257.19:57:37.91#ibcon#read 3, iclass 38, count 2 2006.257.19:57:37.91#ibcon#about to read 4, iclass 38, count 2 2006.257.19:57:37.91#ibcon#read 4, iclass 38, count 2 2006.257.19:57:37.91#ibcon#about to read 5, iclass 38, count 2 2006.257.19:57:37.91#ibcon#read 5, iclass 38, count 2 2006.257.19:57:37.91#ibcon#about to read 6, iclass 38, count 2 2006.257.19:57:37.91#ibcon#read 6, iclass 38, count 2 2006.257.19:57:37.91#ibcon#end of sib2, iclass 38, count 2 2006.257.19:57:37.91#ibcon#*mode == 0, iclass 38, count 2 2006.257.19:57:37.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.19:57:37.91#ibcon#[27=AT06-04\r\n] 2006.257.19:57:37.91#ibcon#*before write, iclass 38, count 2 2006.257.19:57:37.91#ibcon#enter sib2, iclass 38, count 2 2006.257.19:57:37.91#ibcon#flushed, iclass 38, count 2 2006.257.19:57:37.91#ibcon#about to write, iclass 38, count 2 2006.257.19:57:37.91#ibcon#wrote, iclass 38, count 2 2006.257.19:57:37.91#ibcon#about to read 3, iclass 38, count 2 2006.257.19:57:37.94#ibcon#read 3, iclass 38, count 2 2006.257.19:57:37.94#ibcon#about to read 4, iclass 38, count 2 2006.257.19:57:37.94#ibcon#read 4, iclass 38, count 2 2006.257.19:57:37.94#ibcon#about to read 5, iclass 38, count 2 2006.257.19:57:37.94#ibcon#read 5, iclass 38, count 2 2006.257.19:57:37.94#ibcon#about to read 6, iclass 38, count 2 2006.257.19:57:37.94#ibcon#read 6, iclass 38, count 2 2006.257.19:57:37.94#ibcon#end of sib2, iclass 38, count 2 2006.257.19:57:37.94#ibcon#*after write, iclass 38, count 2 2006.257.19:57:37.94#ibcon#*before return 0, iclass 38, count 2 2006.257.19:57:37.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:37.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.19:57:37.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.19:57:37.94#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:37.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:38.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:38.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:38.06#ibcon#enter wrdev, iclass 38, count 0 2006.257.19:57:38.06#ibcon#first serial, iclass 38, count 0 2006.257.19:57:38.06#ibcon#enter sib2, iclass 38, count 0 2006.257.19:57:38.06#ibcon#flushed, iclass 38, count 0 2006.257.19:57:38.06#ibcon#about to write, iclass 38, count 0 2006.257.19:57:38.06#ibcon#wrote, iclass 38, count 0 2006.257.19:57:38.06#ibcon#about to read 3, iclass 38, count 0 2006.257.19:57:38.08#ibcon#read 3, iclass 38, count 0 2006.257.19:57:38.08#ibcon#about to read 4, iclass 38, count 0 2006.257.19:57:38.08#ibcon#read 4, iclass 38, count 0 2006.257.19:57:38.08#ibcon#about to read 5, iclass 38, count 0 2006.257.19:57:38.08#ibcon#read 5, iclass 38, count 0 2006.257.19:57:38.08#ibcon#about to read 6, iclass 38, count 0 2006.257.19:57:38.08#ibcon#read 6, iclass 38, count 0 2006.257.19:57:38.08#ibcon#end of sib2, iclass 38, count 0 2006.257.19:57:38.08#ibcon#*mode == 0, iclass 38, count 0 2006.257.19:57:38.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.19:57:38.08#ibcon#[27=USB\r\n] 2006.257.19:57:38.08#ibcon#*before write, iclass 38, count 0 2006.257.19:57:38.08#ibcon#enter sib2, iclass 38, count 0 2006.257.19:57:38.08#ibcon#flushed, iclass 38, count 0 2006.257.19:57:38.08#ibcon#about to write, iclass 38, count 0 2006.257.19:57:38.08#ibcon#wrote, iclass 38, count 0 2006.257.19:57:38.08#ibcon#about to read 3, iclass 38, count 0 2006.257.19:57:38.11#ibcon#read 3, iclass 38, count 0 2006.257.19:57:38.11#ibcon#about to read 4, iclass 38, count 0 2006.257.19:57:38.11#ibcon#read 4, iclass 38, count 0 2006.257.19:57:38.11#ibcon#about to read 5, iclass 38, count 0 2006.257.19:57:38.11#ibcon#read 5, iclass 38, count 0 2006.257.19:57:38.11#ibcon#about to read 6, iclass 38, count 0 2006.257.19:57:38.11#ibcon#read 6, iclass 38, count 0 2006.257.19:57:38.11#ibcon#end of sib2, iclass 38, count 0 2006.257.19:57:38.11#ibcon#*after write, iclass 38, count 0 2006.257.19:57:38.11#ibcon#*before return 0, iclass 38, count 0 2006.257.19:57:38.11#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:38.11#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.19:57:38.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.19:57:38.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.19:57:38.11$vck44/vblo=7,734.99 2006.257.19:57:38.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.19:57:38.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.19:57:38.11#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:38.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:38.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:38.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:38.11#ibcon#enter wrdev, iclass 40, count 0 2006.257.19:57:38.11#ibcon#first serial, iclass 40, count 0 2006.257.19:57:38.11#ibcon#enter sib2, iclass 40, count 0 2006.257.19:57:38.11#ibcon#flushed, iclass 40, count 0 2006.257.19:57:38.11#ibcon#about to write, iclass 40, count 0 2006.257.19:57:38.11#ibcon#wrote, iclass 40, count 0 2006.257.19:57:38.11#ibcon#about to read 3, iclass 40, count 0 2006.257.19:57:38.13#ibcon#read 3, iclass 40, count 0 2006.257.19:57:38.13#ibcon#about to read 4, iclass 40, count 0 2006.257.19:57:38.13#ibcon#read 4, iclass 40, count 0 2006.257.19:57:38.13#ibcon#about to read 5, iclass 40, count 0 2006.257.19:57:38.13#ibcon#read 5, iclass 40, count 0 2006.257.19:57:38.13#ibcon#about to read 6, iclass 40, count 0 2006.257.19:57:38.13#ibcon#read 6, iclass 40, count 0 2006.257.19:57:38.13#ibcon#end of sib2, iclass 40, count 0 2006.257.19:57:38.13#ibcon#*mode == 0, iclass 40, count 0 2006.257.19:57:38.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.19:57:38.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.19:57:38.13#ibcon#*before write, iclass 40, count 0 2006.257.19:57:38.13#ibcon#enter sib2, iclass 40, count 0 2006.257.19:57:38.13#ibcon#flushed, iclass 40, count 0 2006.257.19:57:38.13#ibcon#about to write, iclass 40, count 0 2006.257.19:57:38.13#ibcon#wrote, iclass 40, count 0 2006.257.19:57:38.13#ibcon#about to read 3, iclass 40, count 0 2006.257.19:57:38.17#ibcon#read 3, iclass 40, count 0 2006.257.19:57:38.17#ibcon#about to read 4, iclass 40, count 0 2006.257.19:57:38.17#ibcon#read 4, iclass 40, count 0 2006.257.19:57:38.17#ibcon#about to read 5, iclass 40, count 0 2006.257.19:57:38.17#ibcon#read 5, iclass 40, count 0 2006.257.19:57:38.17#ibcon#about to read 6, iclass 40, count 0 2006.257.19:57:38.17#ibcon#read 6, iclass 40, count 0 2006.257.19:57:38.17#ibcon#end of sib2, iclass 40, count 0 2006.257.19:57:38.17#ibcon#*after write, iclass 40, count 0 2006.257.19:57:38.17#ibcon#*before return 0, iclass 40, count 0 2006.257.19:57:38.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:38.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.19:57:38.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.19:57:38.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.19:57:38.17$vck44/vb=7,4 2006.257.19:57:38.17#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.19:57:38.17#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.19:57:38.17#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:38.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:38.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:38.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:38.23#ibcon#enter wrdev, iclass 4, count 2 2006.257.19:57:38.23#ibcon#first serial, iclass 4, count 2 2006.257.19:57:38.23#ibcon#enter sib2, iclass 4, count 2 2006.257.19:57:38.23#ibcon#flushed, iclass 4, count 2 2006.257.19:57:38.23#ibcon#about to write, iclass 4, count 2 2006.257.19:57:38.23#ibcon#wrote, iclass 4, count 2 2006.257.19:57:38.23#ibcon#about to read 3, iclass 4, count 2 2006.257.19:57:38.25#ibcon#read 3, iclass 4, count 2 2006.257.19:57:38.25#ibcon#about to read 4, iclass 4, count 2 2006.257.19:57:38.25#ibcon#read 4, iclass 4, count 2 2006.257.19:57:38.25#ibcon#about to read 5, iclass 4, count 2 2006.257.19:57:38.25#ibcon#read 5, iclass 4, count 2 2006.257.19:57:38.25#ibcon#about to read 6, iclass 4, count 2 2006.257.19:57:38.25#ibcon#read 6, iclass 4, count 2 2006.257.19:57:38.25#ibcon#end of sib2, iclass 4, count 2 2006.257.19:57:38.25#ibcon#*mode == 0, iclass 4, count 2 2006.257.19:57:38.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.19:57:38.25#ibcon#[27=AT07-04\r\n] 2006.257.19:57:38.25#ibcon#*before write, iclass 4, count 2 2006.257.19:57:38.25#ibcon#enter sib2, iclass 4, count 2 2006.257.19:57:38.25#ibcon#flushed, iclass 4, count 2 2006.257.19:57:38.25#ibcon#about to write, iclass 4, count 2 2006.257.19:57:38.25#ibcon#wrote, iclass 4, count 2 2006.257.19:57:38.25#ibcon#about to read 3, iclass 4, count 2 2006.257.19:57:38.28#ibcon#read 3, iclass 4, count 2 2006.257.19:57:38.28#ibcon#about to read 4, iclass 4, count 2 2006.257.19:57:38.28#ibcon#read 4, iclass 4, count 2 2006.257.19:57:38.28#ibcon#about to read 5, iclass 4, count 2 2006.257.19:57:38.28#ibcon#read 5, iclass 4, count 2 2006.257.19:57:38.28#ibcon#about to read 6, iclass 4, count 2 2006.257.19:57:38.28#ibcon#read 6, iclass 4, count 2 2006.257.19:57:38.28#ibcon#end of sib2, iclass 4, count 2 2006.257.19:57:38.28#ibcon#*after write, iclass 4, count 2 2006.257.19:57:38.28#ibcon#*before return 0, iclass 4, count 2 2006.257.19:57:38.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:38.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.19:57:38.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.19:57:38.28#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:38.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:38.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:38.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:38.40#ibcon#enter wrdev, iclass 4, count 0 2006.257.19:57:38.40#ibcon#first serial, iclass 4, count 0 2006.257.19:57:38.40#ibcon#enter sib2, iclass 4, count 0 2006.257.19:57:38.40#ibcon#flushed, iclass 4, count 0 2006.257.19:57:38.40#ibcon#about to write, iclass 4, count 0 2006.257.19:57:38.40#ibcon#wrote, iclass 4, count 0 2006.257.19:57:38.40#ibcon#about to read 3, iclass 4, count 0 2006.257.19:57:38.42#ibcon#read 3, iclass 4, count 0 2006.257.19:57:38.42#ibcon#about to read 4, iclass 4, count 0 2006.257.19:57:38.42#ibcon#read 4, iclass 4, count 0 2006.257.19:57:38.42#ibcon#about to read 5, iclass 4, count 0 2006.257.19:57:38.42#ibcon#read 5, iclass 4, count 0 2006.257.19:57:38.42#ibcon#about to read 6, iclass 4, count 0 2006.257.19:57:38.42#ibcon#read 6, iclass 4, count 0 2006.257.19:57:38.42#ibcon#end of sib2, iclass 4, count 0 2006.257.19:57:38.42#ibcon#*mode == 0, iclass 4, count 0 2006.257.19:57:38.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.19:57:38.42#ibcon#[27=USB\r\n] 2006.257.19:57:38.42#ibcon#*before write, iclass 4, count 0 2006.257.19:57:38.42#ibcon#enter sib2, iclass 4, count 0 2006.257.19:57:38.42#ibcon#flushed, iclass 4, count 0 2006.257.19:57:38.42#ibcon#about to write, iclass 4, count 0 2006.257.19:57:38.42#ibcon#wrote, iclass 4, count 0 2006.257.19:57:38.42#ibcon#about to read 3, iclass 4, count 0 2006.257.19:57:38.45#ibcon#read 3, iclass 4, count 0 2006.257.19:57:38.45#ibcon#about to read 4, iclass 4, count 0 2006.257.19:57:38.45#ibcon#read 4, iclass 4, count 0 2006.257.19:57:38.45#ibcon#about to read 5, iclass 4, count 0 2006.257.19:57:38.45#ibcon#read 5, iclass 4, count 0 2006.257.19:57:38.45#ibcon#about to read 6, iclass 4, count 0 2006.257.19:57:38.45#ibcon#read 6, iclass 4, count 0 2006.257.19:57:38.45#ibcon#end of sib2, iclass 4, count 0 2006.257.19:57:38.45#ibcon#*after write, iclass 4, count 0 2006.257.19:57:38.45#ibcon#*before return 0, iclass 4, count 0 2006.257.19:57:38.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:38.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.19:57:38.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.19:57:38.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.19:57:38.45$vck44/vblo=8,744.99 2006.257.19:57:38.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.19:57:38.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.19:57:38.45#ibcon#ireg 17 cls_cnt 0 2006.257.19:57:38.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:38.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:38.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:38.45#ibcon#enter wrdev, iclass 6, count 0 2006.257.19:57:38.45#ibcon#first serial, iclass 6, count 0 2006.257.19:57:38.45#ibcon#enter sib2, iclass 6, count 0 2006.257.19:57:38.45#ibcon#flushed, iclass 6, count 0 2006.257.19:57:38.45#ibcon#about to write, iclass 6, count 0 2006.257.19:57:38.45#ibcon#wrote, iclass 6, count 0 2006.257.19:57:38.45#ibcon#about to read 3, iclass 6, count 0 2006.257.19:57:38.47#ibcon#read 3, iclass 6, count 0 2006.257.19:57:38.47#ibcon#about to read 4, iclass 6, count 0 2006.257.19:57:38.47#ibcon#read 4, iclass 6, count 0 2006.257.19:57:38.47#ibcon#about to read 5, iclass 6, count 0 2006.257.19:57:38.47#ibcon#read 5, iclass 6, count 0 2006.257.19:57:38.47#ibcon#about to read 6, iclass 6, count 0 2006.257.19:57:38.47#ibcon#read 6, iclass 6, count 0 2006.257.19:57:38.47#ibcon#end of sib2, iclass 6, count 0 2006.257.19:57:38.47#ibcon#*mode == 0, iclass 6, count 0 2006.257.19:57:38.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.19:57:38.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.19:57:38.47#ibcon#*before write, iclass 6, count 0 2006.257.19:57:38.47#ibcon#enter sib2, iclass 6, count 0 2006.257.19:57:38.47#ibcon#flushed, iclass 6, count 0 2006.257.19:57:38.47#ibcon#about to write, iclass 6, count 0 2006.257.19:57:38.47#ibcon#wrote, iclass 6, count 0 2006.257.19:57:38.47#ibcon#about to read 3, iclass 6, count 0 2006.257.19:57:38.51#ibcon#read 3, iclass 6, count 0 2006.257.19:57:38.51#ibcon#about to read 4, iclass 6, count 0 2006.257.19:57:38.51#ibcon#read 4, iclass 6, count 0 2006.257.19:57:38.51#ibcon#about to read 5, iclass 6, count 0 2006.257.19:57:38.51#ibcon#read 5, iclass 6, count 0 2006.257.19:57:38.51#ibcon#about to read 6, iclass 6, count 0 2006.257.19:57:38.51#ibcon#read 6, iclass 6, count 0 2006.257.19:57:38.51#ibcon#end of sib2, iclass 6, count 0 2006.257.19:57:38.51#ibcon#*after write, iclass 6, count 0 2006.257.19:57:38.51#ibcon#*before return 0, iclass 6, count 0 2006.257.19:57:38.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:38.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.19:57:38.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.19:57:38.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.19:57:38.51$vck44/vb=8,4 2006.257.19:57:38.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.19:57:38.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.19:57:38.51#ibcon#ireg 11 cls_cnt 2 2006.257.19:57:38.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:38.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:38.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:38.57#ibcon#enter wrdev, iclass 10, count 2 2006.257.19:57:38.57#ibcon#first serial, iclass 10, count 2 2006.257.19:57:38.57#ibcon#enter sib2, iclass 10, count 2 2006.257.19:57:38.57#ibcon#flushed, iclass 10, count 2 2006.257.19:57:38.57#ibcon#about to write, iclass 10, count 2 2006.257.19:57:38.57#ibcon#wrote, iclass 10, count 2 2006.257.19:57:38.57#ibcon#about to read 3, iclass 10, count 2 2006.257.19:57:38.59#ibcon#read 3, iclass 10, count 2 2006.257.19:57:38.59#ibcon#about to read 4, iclass 10, count 2 2006.257.19:57:38.59#ibcon#read 4, iclass 10, count 2 2006.257.19:57:38.59#ibcon#about to read 5, iclass 10, count 2 2006.257.19:57:38.59#ibcon#read 5, iclass 10, count 2 2006.257.19:57:38.59#ibcon#about to read 6, iclass 10, count 2 2006.257.19:57:38.59#ibcon#read 6, iclass 10, count 2 2006.257.19:57:38.59#ibcon#end of sib2, iclass 10, count 2 2006.257.19:57:38.59#ibcon#*mode == 0, iclass 10, count 2 2006.257.19:57:38.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.19:57:38.59#ibcon#[27=AT08-04\r\n] 2006.257.19:57:38.59#ibcon#*before write, iclass 10, count 2 2006.257.19:57:38.59#ibcon#enter sib2, iclass 10, count 2 2006.257.19:57:38.59#ibcon#flushed, iclass 10, count 2 2006.257.19:57:38.59#ibcon#about to write, iclass 10, count 2 2006.257.19:57:38.59#ibcon#wrote, iclass 10, count 2 2006.257.19:57:38.59#ibcon#about to read 3, iclass 10, count 2 2006.257.19:57:38.62#ibcon#read 3, iclass 10, count 2 2006.257.19:57:38.62#ibcon#about to read 4, iclass 10, count 2 2006.257.19:57:38.62#ibcon#read 4, iclass 10, count 2 2006.257.19:57:38.62#ibcon#about to read 5, iclass 10, count 2 2006.257.19:57:38.62#ibcon#read 5, iclass 10, count 2 2006.257.19:57:38.62#ibcon#about to read 6, iclass 10, count 2 2006.257.19:57:38.62#ibcon#read 6, iclass 10, count 2 2006.257.19:57:38.62#ibcon#end of sib2, iclass 10, count 2 2006.257.19:57:38.62#ibcon#*after write, iclass 10, count 2 2006.257.19:57:38.62#ibcon#*before return 0, iclass 10, count 2 2006.257.19:57:38.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:38.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.19:57:38.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.19:57:38.62#ibcon#ireg 7 cls_cnt 0 2006.257.19:57:38.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:38.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:38.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:38.74#ibcon#enter wrdev, iclass 10, count 0 2006.257.19:57:38.74#ibcon#first serial, iclass 10, count 0 2006.257.19:57:38.74#ibcon#enter sib2, iclass 10, count 0 2006.257.19:57:38.74#ibcon#flushed, iclass 10, count 0 2006.257.19:57:38.74#ibcon#about to write, iclass 10, count 0 2006.257.19:57:38.74#ibcon#wrote, iclass 10, count 0 2006.257.19:57:38.74#ibcon#about to read 3, iclass 10, count 0 2006.257.19:57:38.76#ibcon#read 3, iclass 10, count 0 2006.257.19:57:38.76#ibcon#about to read 4, iclass 10, count 0 2006.257.19:57:38.76#ibcon#read 4, iclass 10, count 0 2006.257.19:57:38.76#ibcon#about to read 5, iclass 10, count 0 2006.257.19:57:38.76#ibcon#read 5, iclass 10, count 0 2006.257.19:57:38.76#ibcon#about to read 6, iclass 10, count 0 2006.257.19:57:38.76#ibcon#read 6, iclass 10, count 0 2006.257.19:57:38.76#ibcon#end of sib2, iclass 10, count 0 2006.257.19:57:38.76#ibcon#*mode == 0, iclass 10, count 0 2006.257.19:57:38.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.19:57:38.76#ibcon#[27=USB\r\n] 2006.257.19:57:38.76#ibcon#*before write, iclass 10, count 0 2006.257.19:57:38.76#ibcon#enter sib2, iclass 10, count 0 2006.257.19:57:38.76#ibcon#flushed, iclass 10, count 0 2006.257.19:57:38.76#ibcon#about to write, iclass 10, count 0 2006.257.19:57:38.76#ibcon#wrote, iclass 10, count 0 2006.257.19:57:38.76#ibcon#about to read 3, iclass 10, count 0 2006.257.19:57:38.79#ibcon#read 3, iclass 10, count 0 2006.257.19:57:38.79#ibcon#about to read 4, iclass 10, count 0 2006.257.19:57:38.79#ibcon#read 4, iclass 10, count 0 2006.257.19:57:38.79#ibcon#about to read 5, iclass 10, count 0 2006.257.19:57:38.79#ibcon#read 5, iclass 10, count 0 2006.257.19:57:38.79#ibcon#about to read 6, iclass 10, count 0 2006.257.19:57:38.79#ibcon#read 6, iclass 10, count 0 2006.257.19:57:38.79#ibcon#end of sib2, iclass 10, count 0 2006.257.19:57:38.79#ibcon#*after write, iclass 10, count 0 2006.257.19:57:38.79#ibcon#*before return 0, iclass 10, count 0 2006.257.19:57:38.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:38.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.19:57:38.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.19:57:38.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.19:57:38.79$vck44/vabw=wide 2006.257.19:57:38.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.19:57:38.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.19:57:38.79#ibcon#ireg 8 cls_cnt 0 2006.257.19:57:38.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:38.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:38.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:38.79#ibcon#enter wrdev, iclass 12, count 0 2006.257.19:57:38.79#ibcon#first serial, iclass 12, count 0 2006.257.19:57:38.79#ibcon#enter sib2, iclass 12, count 0 2006.257.19:57:38.79#ibcon#flushed, iclass 12, count 0 2006.257.19:57:38.79#ibcon#about to write, iclass 12, count 0 2006.257.19:57:38.79#ibcon#wrote, iclass 12, count 0 2006.257.19:57:38.79#ibcon#about to read 3, iclass 12, count 0 2006.257.19:57:38.81#ibcon#read 3, iclass 12, count 0 2006.257.19:57:38.81#ibcon#about to read 4, iclass 12, count 0 2006.257.19:57:38.81#ibcon#read 4, iclass 12, count 0 2006.257.19:57:38.81#ibcon#about to read 5, iclass 12, count 0 2006.257.19:57:38.81#ibcon#read 5, iclass 12, count 0 2006.257.19:57:38.81#ibcon#about to read 6, iclass 12, count 0 2006.257.19:57:38.81#ibcon#read 6, iclass 12, count 0 2006.257.19:57:38.81#ibcon#end of sib2, iclass 12, count 0 2006.257.19:57:38.81#ibcon#*mode == 0, iclass 12, count 0 2006.257.19:57:38.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.19:57:38.81#ibcon#[25=BW32\r\n] 2006.257.19:57:38.81#ibcon#*before write, iclass 12, count 0 2006.257.19:57:38.81#ibcon#enter sib2, iclass 12, count 0 2006.257.19:57:38.81#ibcon#flushed, iclass 12, count 0 2006.257.19:57:38.81#ibcon#about to write, iclass 12, count 0 2006.257.19:57:38.81#ibcon#wrote, iclass 12, count 0 2006.257.19:57:38.81#ibcon#about to read 3, iclass 12, count 0 2006.257.19:57:38.84#ibcon#read 3, iclass 12, count 0 2006.257.19:57:38.84#ibcon#about to read 4, iclass 12, count 0 2006.257.19:57:38.84#ibcon#read 4, iclass 12, count 0 2006.257.19:57:38.84#ibcon#about to read 5, iclass 12, count 0 2006.257.19:57:38.84#ibcon#read 5, iclass 12, count 0 2006.257.19:57:38.84#ibcon#about to read 6, iclass 12, count 0 2006.257.19:57:38.84#ibcon#read 6, iclass 12, count 0 2006.257.19:57:38.84#ibcon#end of sib2, iclass 12, count 0 2006.257.19:57:38.84#ibcon#*after write, iclass 12, count 0 2006.257.19:57:38.84#ibcon#*before return 0, iclass 12, count 0 2006.257.19:57:38.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:38.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.19:57:38.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.19:57:38.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.19:57:38.84$vck44/vbbw=wide 2006.257.19:57:38.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.19:57:38.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.19:57:38.84#ibcon#ireg 8 cls_cnt 0 2006.257.19:57:38.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:57:38.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:57:38.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:57:38.91#ibcon#enter wrdev, iclass 14, count 0 2006.257.19:57:38.91#ibcon#first serial, iclass 14, count 0 2006.257.19:57:38.91#ibcon#enter sib2, iclass 14, count 0 2006.257.19:57:38.91#ibcon#flushed, iclass 14, count 0 2006.257.19:57:38.91#ibcon#about to write, iclass 14, count 0 2006.257.19:57:38.91#ibcon#wrote, iclass 14, count 0 2006.257.19:57:38.91#ibcon#about to read 3, iclass 14, count 0 2006.257.19:57:38.93#ibcon#read 3, iclass 14, count 0 2006.257.19:57:38.93#ibcon#about to read 4, iclass 14, count 0 2006.257.19:57:38.93#ibcon#read 4, iclass 14, count 0 2006.257.19:57:38.93#ibcon#about to read 5, iclass 14, count 0 2006.257.19:57:38.93#ibcon#read 5, iclass 14, count 0 2006.257.19:57:38.93#ibcon#about to read 6, iclass 14, count 0 2006.257.19:57:38.93#ibcon#read 6, iclass 14, count 0 2006.257.19:57:38.93#ibcon#end of sib2, iclass 14, count 0 2006.257.19:57:38.93#ibcon#*mode == 0, iclass 14, count 0 2006.257.19:57:38.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.19:57:38.93#ibcon#[27=BW32\r\n] 2006.257.19:57:38.93#ibcon#*before write, iclass 14, count 0 2006.257.19:57:38.93#ibcon#enter sib2, iclass 14, count 0 2006.257.19:57:38.93#ibcon#flushed, iclass 14, count 0 2006.257.19:57:38.93#ibcon#about to write, iclass 14, count 0 2006.257.19:57:38.93#ibcon#wrote, iclass 14, count 0 2006.257.19:57:38.93#ibcon#about to read 3, iclass 14, count 0 2006.257.19:57:38.96#ibcon#read 3, iclass 14, count 0 2006.257.19:57:38.96#ibcon#about to read 4, iclass 14, count 0 2006.257.19:57:38.96#ibcon#read 4, iclass 14, count 0 2006.257.19:57:38.96#ibcon#about to read 5, iclass 14, count 0 2006.257.19:57:38.96#ibcon#read 5, iclass 14, count 0 2006.257.19:57:38.96#ibcon#about to read 6, iclass 14, count 0 2006.257.19:57:38.96#ibcon#read 6, iclass 14, count 0 2006.257.19:57:38.96#ibcon#end of sib2, iclass 14, count 0 2006.257.19:57:38.96#ibcon#*after write, iclass 14, count 0 2006.257.19:57:38.96#ibcon#*before return 0, iclass 14, count 0 2006.257.19:57:38.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:57:38.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.19:57:38.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.19:57:38.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.19:57:38.96$setupk4/ifdk4 2006.257.19:57:38.96$ifdk4/lo= 2006.257.19:57:38.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.19:57:38.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.19:57:38.96$ifdk4/patch= 2006.257.19:57:38.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.19:57:38.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.19:57:38.96$setupk4/!*+20s 2006.257.19:57:43.20#abcon#<5=/14 0.9 3.3 17.50 961014.6\r\n> 2006.257.19:57:43.22#abcon#{5=INTERFACE CLEAR} 2006.257.19:57:43.28#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:57:53.37#abcon#<5=/14 0.9 3.3 17.50 961014.6\r\n> 2006.257.19:57:53.39#abcon#{5=INTERFACE CLEAR} 2006.257.19:57:53.45#abcon#[5=S1D000X0/0*\r\n] 2006.257.19:57:53.47$setupk4/"tpicd 2006.257.19:57:53.47$setupk4/echo=off 2006.257.19:57:53.47$setupk4/xlog=off 2006.257.19:57:53.47:!2006.257.20:00:06 2006.257.19:58:09.14#trakl#Source acquired 2006.257.19:58:11.14#flagr#flagr/antenna,acquired 2006.257.20:00:06.00:preob 2006.257.20:00:06.13/onsource/TRACKING 2006.257.20:00:06.13:!2006.257.20:00:16 2006.257.20:00:16.00:"tape 2006.257.20:00:16.00:"st=record 2006.257.20:00:16.00:data_valid=on 2006.257.20:00:16.00:midob 2006.257.20:00:17.13/onsource/TRACKING 2006.257.20:00:17.13/wx/17.48,1014.6,96 2006.257.20:00:17.31/cable/+6.4838E-03 2006.257.20:00:18.40/va/01,08,usb,yes,37,40 2006.257.20:00:18.40/va/02,07,usb,yes,40,41 2006.257.20:00:18.40/va/03,08,usb,yes,36,38 2006.257.20:00:18.40/va/04,07,usb,yes,41,43 2006.257.20:00:18.40/va/05,04,usb,yes,37,37 2006.257.20:00:18.40/va/06,04,usb,yes,41,40 2006.257.20:00:18.40/va/07,04,usb,yes,42,42 2006.257.20:00:18.40/va/08,04,usb,yes,35,43 2006.257.20:00:18.63/valo/01,524.99,yes,locked 2006.257.20:00:18.63/valo/02,534.99,yes,locked 2006.257.20:00:18.63/valo/03,564.99,yes,locked 2006.257.20:00:18.63/valo/04,624.99,yes,locked 2006.257.20:00:18.63/valo/05,734.99,yes,locked 2006.257.20:00:18.63/valo/06,814.99,yes,locked 2006.257.20:00:18.63/valo/07,864.99,yes,locked 2006.257.20:00:18.63/valo/08,884.99,yes,locked 2006.257.20:00:19.72/vb/01,04,usb,yes,34,32 2006.257.20:00:19.72/vb/02,05,usb,yes,32,32 2006.257.20:00:19.72/vb/03,04,usb,yes,33,37 2006.257.20:00:19.72/vb/04,05,usb,yes,34,33 2006.257.20:00:19.72/vb/05,04,usb,yes,30,33 2006.257.20:00:19.72/vb/06,04,usb,yes,35,31 2006.257.20:00:19.72/vb/07,04,usb,yes,35,35 2006.257.20:00:19.72/vb/08,04,usb,yes,32,36 2006.257.20:00:19.96/vblo/01,629.99,yes,locked 2006.257.20:00:19.96/vblo/02,634.99,yes,locked 2006.257.20:00:19.96/vblo/03,649.99,yes,locked 2006.257.20:00:19.96/vblo/04,679.99,yes,locked 2006.257.20:00:19.96/vblo/05,709.99,yes,locked 2006.257.20:00:19.96/vblo/06,719.99,yes,locked 2006.257.20:00:19.96/vblo/07,734.99,yes,locked 2006.257.20:00:19.96/vblo/08,744.99,yes,locked 2006.257.20:00:20.11/vabw/8 2006.257.20:00:20.26/vbbw/8 2006.257.20:00:20.35/xfe/off,on,16.0 2006.257.20:00:20.74/ifatt/23,28,28,28 2006.257.20:00:21.07/fmout-gps/S +4.51E-07 2006.257.20:00:21.11:!2006.257.20:00:56 2006.257.20:00:56.01:data_valid=off 2006.257.20:00:56.01:"et 2006.257.20:00:56.01:!+3s 2006.257.20:00:59.02:"tape 2006.257.20:00:59.02:postob 2006.257.20:00:59.20/cable/+6.4864E-03 2006.257.20:00:59.20/wx/17.47,1014.6,96 2006.257.20:00:59.26/fmout-gps/S +4.50E-07 2006.257.20:00:59.26:scan_name=257-2008,jd0609,200 2006.257.20:00:59.26:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.257.20:01:01.13#flagr#flagr/antenna,new-source 2006.257.20:01:01.13:checkk5 2006.257.20:01:01.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.20:01:01.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.20:01:02.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.20:01:02.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.20:01:02.83/chk_obsdata//k5ts1/T2572000??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.20:01:03.16/chk_obsdata//k5ts2/T2572000??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.20:01:03.49/chk_obsdata//k5ts3/T2572000??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.20:01:03.83/chk_obsdata//k5ts4/T2572000??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.257.20:01:04.49/k5log//k5ts1_log_newline 2006.257.20:01:05.14/k5log//k5ts2_log_newline 2006.257.20:01:05.79/k5log//k5ts3_log_newline 2006.257.20:01:06.44/k5log//k5ts4_log_newline 2006.257.20:01:06.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.20:01:06.46:setupk4=1 2006.257.20:01:06.46$setupk4/echo=on 2006.257.20:01:06.46$setupk4/pcalon 2006.257.20:01:06.46$pcalon/"no phase cal control is implemented here 2006.257.20:01:06.46$setupk4/"tpicd=stop 2006.257.20:01:06.46$setupk4/"rec=synch_on 2006.257.20:01:06.46$setupk4/"rec_mode=128 2006.257.20:01:06.46$setupk4/!* 2006.257.20:01:06.46$setupk4/recpk4 2006.257.20:01:06.46$recpk4/recpatch= 2006.257.20:01:06.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.20:01:06.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.20:01:06.47$setupk4/vck44 2006.257.20:01:06.47$vck44/valo=1,524.99 2006.257.20:01:06.47#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.20:01:06.47#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.20:01:06.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:06.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:06.47#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:06.47#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:06.47#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:01:06.47#ibcon#first serial, iclass 27, count 0 2006.257.20:01:06.47#ibcon#enter sib2, iclass 27, count 0 2006.257.20:01:06.47#ibcon#flushed, iclass 27, count 0 2006.257.20:01:06.47#ibcon#about to write, iclass 27, count 0 2006.257.20:01:06.47#ibcon#wrote, iclass 27, count 0 2006.257.20:01:06.47#ibcon#about to read 3, iclass 27, count 0 2006.257.20:01:06.48#ibcon#read 3, iclass 27, count 0 2006.257.20:01:06.48#ibcon#about to read 4, iclass 27, count 0 2006.257.20:01:06.48#ibcon#read 4, iclass 27, count 0 2006.257.20:01:06.48#ibcon#about to read 5, iclass 27, count 0 2006.257.20:01:06.48#ibcon#read 5, iclass 27, count 0 2006.257.20:01:06.48#ibcon#about to read 6, iclass 27, count 0 2006.257.20:01:06.48#ibcon#read 6, iclass 27, count 0 2006.257.20:01:06.48#ibcon#end of sib2, iclass 27, count 0 2006.257.20:01:06.48#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:01:06.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:01:06.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.20:01:06.48#ibcon#*before write, iclass 27, count 0 2006.257.20:01:06.48#ibcon#enter sib2, iclass 27, count 0 2006.257.20:01:06.48#ibcon#flushed, iclass 27, count 0 2006.257.20:01:06.48#ibcon#about to write, iclass 27, count 0 2006.257.20:01:06.48#ibcon#wrote, iclass 27, count 0 2006.257.20:01:06.48#ibcon#about to read 3, iclass 27, count 0 2006.257.20:01:06.53#ibcon#read 3, iclass 27, count 0 2006.257.20:01:06.53#ibcon#about to read 4, iclass 27, count 0 2006.257.20:01:06.53#ibcon#read 4, iclass 27, count 0 2006.257.20:01:06.53#ibcon#about to read 5, iclass 27, count 0 2006.257.20:01:06.53#ibcon#read 5, iclass 27, count 0 2006.257.20:01:06.53#ibcon#about to read 6, iclass 27, count 0 2006.257.20:01:06.53#ibcon#read 6, iclass 27, count 0 2006.257.20:01:06.53#ibcon#end of sib2, iclass 27, count 0 2006.257.20:01:06.53#ibcon#*after write, iclass 27, count 0 2006.257.20:01:06.53#ibcon#*before return 0, iclass 27, count 0 2006.257.20:01:06.53#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:06.53#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:06.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:01:06.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:01:06.53$vck44/va=1,8 2006.257.20:01:06.53#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.20:01:06.53#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.20:01:06.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:06.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:06.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:06.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:06.53#ibcon#enter wrdev, iclass 29, count 2 2006.257.20:01:06.53#ibcon#first serial, iclass 29, count 2 2006.257.20:01:06.53#ibcon#enter sib2, iclass 29, count 2 2006.257.20:01:06.53#ibcon#flushed, iclass 29, count 2 2006.257.20:01:06.53#ibcon#about to write, iclass 29, count 2 2006.257.20:01:06.53#ibcon#wrote, iclass 29, count 2 2006.257.20:01:06.53#ibcon#about to read 3, iclass 29, count 2 2006.257.20:01:06.55#ibcon#read 3, iclass 29, count 2 2006.257.20:01:06.55#ibcon#about to read 4, iclass 29, count 2 2006.257.20:01:06.55#ibcon#read 4, iclass 29, count 2 2006.257.20:01:06.55#ibcon#about to read 5, iclass 29, count 2 2006.257.20:01:06.55#ibcon#read 5, iclass 29, count 2 2006.257.20:01:06.55#ibcon#about to read 6, iclass 29, count 2 2006.257.20:01:06.55#ibcon#read 6, iclass 29, count 2 2006.257.20:01:06.55#ibcon#end of sib2, iclass 29, count 2 2006.257.20:01:06.55#ibcon#*mode == 0, iclass 29, count 2 2006.257.20:01:06.55#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.20:01:06.55#ibcon#[25=AT01-08\r\n] 2006.257.20:01:06.55#ibcon#*before write, iclass 29, count 2 2006.257.20:01:06.55#ibcon#enter sib2, iclass 29, count 2 2006.257.20:01:06.55#ibcon#flushed, iclass 29, count 2 2006.257.20:01:06.55#ibcon#about to write, iclass 29, count 2 2006.257.20:01:06.55#ibcon#wrote, iclass 29, count 2 2006.257.20:01:06.55#ibcon#about to read 3, iclass 29, count 2 2006.257.20:01:06.58#ibcon#read 3, iclass 29, count 2 2006.257.20:01:06.58#ibcon#about to read 4, iclass 29, count 2 2006.257.20:01:06.58#ibcon#read 4, iclass 29, count 2 2006.257.20:01:06.58#ibcon#about to read 5, iclass 29, count 2 2006.257.20:01:06.58#ibcon#read 5, iclass 29, count 2 2006.257.20:01:06.58#ibcon#about to read 6, iclass 29, count 2 2006.257.20:01:06.58#ibcon#read 6, iclass 29, count 2 2006.257.20:01:06.58#ibcon#end of sib2, iclass 29, count 2 2006.257.20:01:06.58#ibcon#*after write, iclass 29, count 2 2006.257.20:01:06.58#ibcon#*before return 0, iclass 29, count 2 2006.257.20:01:06.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:06.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:06.58#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.20:01:06.58#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:06.58#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:06.60#abcon#<5=/14 1.0 2.7 17.46 961014.6\r\n> 2006.257.20:01:06.62#abcon#{5=INTERFACE CLEAR} 2006.257.20:01:06.68#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:01:06.70#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:06.70#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:06.70#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:01:06.70#ibcon#first serial, iclass 29, count 0 2006.257.20:01:06.70#ibcon#enter sib2, iclass 29, count 0 2006.257.20:01:06.70#ibcon#flushed, iclass 29, count 0 2006.257.20:01:06.70#ibcon#about to write, iclass 29, count 0 2006.257.20:01:06.70#ibcon#wrote, iclass 29, count 0 2006.257.20:01:06.70#ibcon#about to read 3, iclass 29, count 0 2006.257.20:01:06.72#ibcon#read 3, iclass 29, count 0 2006.257.20:01:06.72#ibcon#about to read 4, iclass 29, count 0 2006.257.20:01:06.72#ibcon#read 4, iclass 29, count 0 2006.257.20:01:06.72#ibcon#about to read 5, iclass 29, count 0 2006.257.20:01:06.72#ibcon#read 5, iclass 29, count 0 2006.257.20:01:06.72#ibcon#about to read 6, iclass 29, count 0 2006.257.20:01:06.72#ibcon#read 6, iclass 29, count 0 2006.257.20:01:06.72#ibcon#end of sib2, iclass 29, count 0 2006.257.20:01:06.72#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:01:06.72#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:01:06.72#ibcon#[25=USB\r\n] 2006.257.20:01:06.72#ibcon#*before write, iclass 29, count 0 2006.257.20:01:06.72#ibcon#enter sib2, iclass 29, count 0 2006.257.20:01:06.72#ibcon#flushed, iclass 29, count 0 2006.257.20:01:06.72#ibcon#about to write, iclass 29, count 0 2006.257.20:01:06.72#ibcon#wrote, iclass 29, count 0 2006.257.20:01:06.72#ibcon#about to read 3, iclass 29, count 0 2006.257.20:01:06.75#ibcon#read 3, iclass 29, count 0 2006.257.20:01:06.75#ibcon#about to read 4, iclass 29, count 0 2006.257.20:01:06.75#ibcon#read 4, iclass 29, count 0 2006.257.20:01:06.75#ibcon#about to read 5, iclass 29, count 0 2006.257.20:01:06.75#ibcon#read 5, iclass 29, count 0 2006.257.20:01:06.75#ibcon#about to read 6, iclass 29, count 0 2006.257.20:01:06.75#ibcon#read 6, iclass 29, count 0 2006.257.20:01:06.75#ibcon#end of sib2, iclass 29, count 0 2006.257.20:01:06.75#ibcon#*after write, iclass 29, count 0 2006.257.20:01:06.75#ibcon#*before return 0, iclass 29, count 0 2006.257.20:01:06.75#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:06.75#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:06.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:01:06.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:01:06.75$vck44/valo=2,534.99 2006.257.20:01:06.75#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.20:01:06.75#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.20:01:06.75#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:06.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:06.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:06.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:06.75#ibcon#enter wrdev, iclass 35, count 0 2006.257.20:01:06.75#ibcon#first serial, iclass 35, count 0 2006.257.20:01:06.75#ibcon#enter sib2, iclass 35, count 0 2006.257.20:01:06.75#ibcon#flushed, iclass 35, count 0 2006.257.20:01:06.75#ibcon#about to write, iclass 35, count 0 2006.257.20:01:06.75#ibcon#wrote, iclass 35, count 0 2006.257.20:01:06.75#ibcon#about to read 3, iclass 35, count 0 2006.257.20:01:06.77#ibcon#read 3, iclass 35, count 0 2006.257.20:01:06.77#ibcon#about to read 4, iclass 35, count 0 2006.257.20:01:06.77#ibcon#read 4, iclass 35, count 0 2006.257.20:01:06.77#ibcon#about to read 5, iclass 35, count 0 2006.257.20:01:06.77#ibcon#read 5, iclass 35, count 0 2006.257.20:01:06.77#ibcon#about to read 6, iclass 35, count 0 2006.257.20:01:06.77#ibcon#read 6, iclass 35, count 0 2006.257.20:01:06.77#ibcon#end of sib2, iclass 35, count 0 2006.257.20:01:06.77#ibcon#*mode == 0, iclass 35, count 0 2006.257.20:01:06.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.20:01:06.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.20:01:06.77#ibcon#*before write, iclass 35, count 0 2006.257.20:01:06.77#ibcon#enter sib2, iclass 35, count 0 2006.257.20:01:06.77#ibcon#flushed, iclass 35, count 0 2006.257.20:01:06.77#ibcon#about to write, iclass 35, count 0 2006.257.20:01:06.77#ibcon#wrote, iclass 35, count 0 2006.257.20:01:06.77#ibcon#about to read 3, iclass 35, count 0 2006.257.20:01:06.81#ibcon#read 3, iclass 35, count 0 2006.257.20:01:06.81#ibcon#about to read 4, iclass 35, count 0 2006.257.20:01:06.81#ibcon#read 4, iclass 35, count 0 2006.257.20:01:06.81#ibcon#about to read 5, iclass 35, count 0 2006.257.20:01:06.81#ibcon#read 5, iclass 35, count 0 2006.257.20:01:06.81#ibcon#about to read 6, iclass 35, count 0 2006.257.20:01:06.81#ibcon#read 6, iclass 35, count 0 2006.257.20:01:06.81#ibcon#end of sib2, iclass 35, count 0 2006.257.20:01:06.81#ibcon#*after write, iclass 35, count 0 2006.257.20:01:06.81#ibcon#*before return 0, iclass 35, count 0 2006.257.20:01:06.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:06.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:06.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.20:01:06.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.20:01:06.81$vck44/va=2,7 2006.257.20:01:06.81#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.20:01:06.81#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.20:01:06.81#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:06.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:06.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:06.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:06.87#ibcon#enter wrdev, iclass 37, count 2 2006.257.20:01:06.87#ibcon#first serial, iclass 37, count 2 2006.257.20:01:06.87#ibcon#enter sib2, iclass 37, count 2 2006.257.20:01:06.87#ibcon#flushed, iclass 37, count 2 2006.257.20:01:06.87#ibcon#about to write, iclass 37, count 2 2006.257.20:01:06.87#ibcon#wrote, iclass 37, count 2 2006.257.20:01:06.87#ibcon#about to read 3, iclass 37, count 2 2006.257.20:01:06.89#ibcon#read 3, iclass 37, count 2 2006.257.20:01:06.89#ibcon#about to read 4, iclass 37, count 2 2006.257.20:01:06.89#ibcon#read 4, iclass 37, count 2 2006.257.20:01:06.89#ibcon#about to read 5, iclass 37, count 2 2006.257.20:01:06.89#ibcon#read 5, iclass 37, count 2 2006.257.20:01:06.89#ibcon#about to read 6, iclass 37, count 2 2006.257.20:01:06.89#ibcon#read 6, iclass 37, count 2 2006.257.20:01:06.89#ibcon#end of sib2, iclass 37, count 2 2006.257.20:01:06.89#ibcon#*mode == 0, iclass 37, count 2 2006.257.20:01:06.89#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.20:01:06.89#ibcon#[25=AT02-07\r\n] 2006.257.20:01:06.89#ibcon#*before write, iclass 37, count 2 2006.257.20:01:06.89#ibcon#enter sib2, iclass 37, count 2 2006.257.20:01:06.89#ibcon#flushed, iclass 37, count 2 2006.257.20:01:06.89#ibcon#about to write, iclass 37, count 2 2006.257.20:01:06.89#ibcon#wrote, iclass 37, count 2 2006.257.20:01:06.89#ibcon#about to read 3, iclass 37, count 2 2006.257.20:01:06.92#ibcon#read 3, iclass 37, count 2 2006.257.20:01:06.92#ibcon#about to read 4, iclass 37, count 2 2006.257.20:01:06.92#ibcon#read 4, iclass 37, count 2 2006.257.20:01:06.92#ibcon#about to read 5, iclass 37, count 2 2006.257.20:01:06.92#ibcon#read 5, iclass 37, count 2 2006.257.20:01:06.92#ibcon#about to read 6, iclass 37, count 2 2006.257.20:01:06.92#ibcon#read 6, iclass 37, count 2 2006.257.20:01:06.92#ibcon#end of sib2, iclass 37, count 2 2006.257.20:01:06.92#ibcon#*after write, iclass 37, count 2 2006.257.20:01:06.92#ibcon#*before return 0, iclass 37, count 2 2006.257.20:01:06.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:06.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:06.92#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.20:01:06.92#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:06.92#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:07.04#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:07.04#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:07.04#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:01:07.04#ibcon#first serial, iclass 37, count 0 2006.257.20:01:07.04#ibcon#enter sib2, iclass 37, count 0 2006.257.20:01:07.04#ibcon#flushed, iclass 37, count 0 2006.257.20:01:07.04#ibcon#about to write, iclass 37, count 0 2006.257.20:01:07.04#ibcon#wrote, iclass 37, count 0 2006.257.20:01:07.04#ibcon#about to read 3, iclass 37, count 0 2006.257.20:01:07.06#ibcon#read 3, iclass 37, count 0 2006.257.20:01:07.06#ibcon#about to read 4, iclass 37, count 0 2006.257.20:01:07.06#ibcon#read 4, iclass 37, count 0 2006.257.20:01:07.06#ibcon#about to read 5, iclass 37, count 0 2006.257.20:01:07.06#ibcon#read 5, iclass 37, count 0 2006.257.20:01:07.06#ibcon#about to read 6, iclass 37, count 0 2006.257.20:01:07.06#ibcon#read 6, iclass 37, count 0 2006.257.20:01:07.06#ibcon#end of sib2, iclass 37, count 0 2006.257.20:01:07.06#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:01:07.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:01:07.06#ibcon#[25=USB\r\n] 2006.257.20:01:07.06#ibcon#*before write, iclass 37, count 0 2006.257.20:01:07.06#ibcon#enter sib2, iclass 37, count 0 2006.257.20:01:07.06#ibcon#flushed, iclass 37, count 0 2006.257.20:01:07.06#ibcon#about to write, iclass 37, count 0 2006.257.20:01:07.06#ibcon#wrote, iclass 37, count 0 2006.257.20:01:07.06#ibcon#about to read 3, iclass 37, count 0 2006.257.20:01:07.09#ibcon#read 3, iclass 37, count 0 2006.257.20:01:07.09#ibcon#about to read 4, iclass 37, count 0 2006.257.20:01:07.09#ibcon#read 4, iclass 37, count 0 2006.257.20:01:07.09#ibcon#about to read 5, iclass 37, count 0 2006.257.20:01:07.09#ibcon#read 5, iclass 37, count 0 2006.257.20:01:07.09#ibcon#about to read 6, iclass 37, count 0 2006.257.20:01:07.09#ibcon#read 6, iclass 37, count 0 2006.257.20:01:07.09#ibcon#end of sib2, iclass 37, count 0 2006.257.20:01:07.09#ibcon#*after write, iclass 37, count 0 2006.257.20:01:07.09#ibcon#*before return 0, iclass 37, count 0 2006.257.20:01:07.09#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:07.09#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:07.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:01:07.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:01:07.09$vck44/valo=3,564.99 2006.257.20:01:07.09#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.20:01:07.09#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.20:01:07.09#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:07.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:07.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:07.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:07.09#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:01:07.09#ibcon#first serial, iclass 39, count 0 2006.257.20:01:07.09#ibcon#enter sib2, iclass 39, count 0 2006.257.20:01:07.09#ibcon#flushed, iclass 39, count 0 2006.257.20:01:07.09#ibcon#about to write, iclass 39, count 0 2006.257.20:01:07.09#ibcon#wrote, iclass 39, count 0 2006.257.20:01:07.09#ibcon#about to read 3, iclass 39, count 0 2006.257.20:01:07.11#ibcon#read 3, iclass 39, count 0 2006.257.20:01:07.11#ibcon#about to read 4, iclass 39, count 0 2006.257.20:01:07.11#ibcon#read 4, iclass 39, count 0 2006.257.20:01:07.11#ibcon#about to read 5, iclass 39, count 0 2006.257.20:01:07.11#ibcon#read 5, iclass 39, count 0 2006.257.20:01:07.11#ibcon#about to read 6, iclass 39, count 0 2006.257.20:01:07.11#ibcon#read 6, iclass 39, count 0 2006.257.20:01:07.11#ibcon#end of sib2, iclass 39, count 0 2006.257.20:01:07.11#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:01:07.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:01:07.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.20:01:07.11#ibcon#*before write, iclass 39, count 0 2006.257.20:01:07.11#ibcon#enter sib2, iclass 39, count 0 2006.257.20:01:07.11#ibcon#flushed, iclass 39, count 0 2006.257.20:01:07.11#ibcon#about to write, iclass 39, count 0 2006.257.20:01:07.11#ibcon#wrote, iclass 39, count 0 2006.257.20:01:07.11#ibcon#about to read 3, iclass 39, count 0 2006.257.20:01:07.15#ibcon#read 3, iclass 39, count 0 2006.257.20:01:07.15#ibcon#about to read 4, iclass 39, count 0 2006.257.20:01:07.15#ibcon#read 4, iclass 39, count 0 2006.257.20:01:07.15#ibcon#about to read 5, iclass 39, count 0 2006.257.20:01:07.15#ibcon#read 5, iclass 39, count 0 2006.257.20:01:07.15#ibcon#about to read 6, iclass 39, count 0 2006.257.20:01:07.15#ibcon#read 6, iclass 39, count 0 2006.257.20:01:07.15#ibcon#end of sib2, iclass 39, count 0 2006.257.20:01:07.15#ibcon#*after write, iclass 39, count 0 2006.257.20:01:07.15#ibcon#*before return 0, iclass 39, count 0 2006.257.20:01:07.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:07.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:07.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:01:07.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:01:07.15$vck44/va=3,8 2006.257.20:01:07.15#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.20:01:07.15#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.20:01:07.15#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:07.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:07.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:07.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:07.21#ibcon#enter wrdev, iclass 3, count 2 2006.257.20:01:07.21#ibcon#first serial, iclass 3, count 2 2006.257.20:01:07.21#ibcon#enter sib2, iclass 3, count 2 2006.257.20:01:07.21#ibcon#flushed, iclass 3, count 2 2006.257.20:01:07.21#ibcon#about to write, iclass 3, count 2 2006.257.20:01:07.21#ibcon#wrote, iclass 3, count 2 2006.257.20:01:07.21#ibcon#about to read 3, iclass 3, count 2 2006.257.20:01:07.23#ibcon#read 3, iclass 3, count 2 2006.257.20:01:07.23#ibcon#about to read 4, iclass 3, count 2 2006.257.20:01:07.23#ibcon#read 4, iclass 3, count 2 2006.257.20:01:07.23#ibcon#about to read 5, iclass 3, count 2 2006.257.20:01:07.23#ibcon#read 5, iclass 3, count 2 2006.257.20:01:07.23#ibcon#about to read 6, iclass 3, count 2 2006.257.20:01:07.23#ibcon#read 6, iclass 3, count 2 2006.257.20:01:07.23#ibcon#end of sib2, iclass 3, count 2 2006.257.20:01:07.23#ibcon#*mode == 0, iclass 3, count 2 2006.257.20:01:07.23#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.20:01:07.23#ibcon#[25=AT03-08\r\n] 2006.257.20:01:07.23#ibcon#*before write, iclass 3, count 2 2006.257.20:01:07.23#ibcon#enter sib2, iclass 3, count 2 2006.257.20:01:07.23#ibcon#flushed, iclass 3, count 2 2006.257.20:01:07.23#ibcon#about to write, iclass 3, count 2 2006.257.20:01:07.23#ibcon#wrote, iclass 3, count 2 2006.257.20:01:07.23#ibcon#about to read 3, iclass 3, count 2 2006.257.20:01:07.26#ibcon#read 3, iclass 3, count 2 2006.257.20:01:07.26#ibcon#about to read 4, iclass 3, count 2 2006.257.20:01:07.26#ibcon#read 4, iclass 3, count 2 2006.257.20:01:07.26#ibcon#about to read 5, iclass 3, count 2 2006.257.20:01:07.26#ibcon#read 5, iclass 3, count 2 2006.257.20:01:07.26#ibcon#about to read 6, iclass 3, count 2 2006.257.20:01:07.26#ibcon#read 6, iclass 3, count 2 2006.257.20:01:07.26#ibcon#end of sib2, iclass 3, count 2 2006.257.20:01:07.26#ibcon#*after write, iclass 3, count 2 2006.257.20:01:07.26#ibcon#*before return 0, iclass 3, count 2 2006.257.20:01:07.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:07.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:07.26#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.20:01:07.26#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:07.26#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:07.38#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:07.38#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:07.38#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:01:07.38#ibcon#first serial, iclass 3, count 0 2006.257.20:01:07.38#ibcon#enter sib2, iclass 3, count 0 2006.257.20:01:07.38#ibcon#flushed, iclass 3, count 0 2006.257.20:01:07.38#ibcon#about to write, iclass 3, count 0 2006.257.20:01:07.38#ibcon#wrote, iclass 3, count 0 2006.257.20:01:07.38#ibcon#about to read 3, iclass 3, count 0 2006.257.20:01:07.40#ibcon#read 3, iclass 3, count 0 2006.257.20:01:07.40#ibcon#about to read 4, iclass 3, count 0 2006.257.20:01:07.40#ibcon#read 4, iclass 3, count 0 2006.257.20:01:07.40#ibcon#about to read 5, iclass 3, count 0 2006.257.20:01:07.40#ibcon#read 5, iclass 3, count 0 2006.257.20:01:07.40#ibcon#about to read 6, iclass 3, count 0 2006.257.20:01:07.40#ibcon#read 6, iclass 3, count 0 2006.257.20:01:07.40#ibcon#end of sib2, iclass 3, count 0 2006.257.20:01:07.40#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:01:07.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:01:07.40#ibcon#[25=USB\r\n] 2006.257.20:01:07.40#ibcon#*before write, iclass 3, count 0 2006.257.20:01:07.40#ibcon#enter sib2, iclass 3, count 0 2006.257.20:01:07.40#ibcon#flushed, iclass 3, count 0 2006.257.20:01:07.40#ibcon#about to write, iclass 3, count 0 2006.257.20:01:07.40#ibcon#wrote, iclass 3, count 0 2006.257.20:01:07.40#ibcon#about to read 3, iclass 3, count 0 2006.257.20:01:07.43#ibcon#read 3, iclass 3, count 0 2006.257.20:01:07.43#ibcon#about to read 4, iclass 3, count 0 2006.257.20:01:07.43#ibcon#read 4, iclass 3, count 0 2006.257.20:01:07.43#ibcon#about to read 5, iclass 3, count 0 2006.257.20:01:07.43#ibcon#read 5, iclass 3, count 0 2006.257.20:01:07.43#ibcon#about to read 6, iclass 3, count 0 2006.257.20:01:07.43#ibcon#read 6, iclass 3, count 0 2006.257.20:01:07.43#ibcon#end of sib2, iclass 3, count 0 2006.257.20:01:07.43#ibcon#*after write, iclass 3, count 0 2006.257.20:01:07.43#ibcon#*before return 0, iclass 3, count 0 2006.257.20:01:07.43#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:07.43#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:07.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:01:07.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:01:07.43$vck44/valo=4,624.99 2006.257.20:01:07.43#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.20:01:07.43#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.20:01:07.43#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:07.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:07.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:07.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:07.43#ibcon#enter wrdev, iclass 5, count 0 2006.257.20:01:07.43#ibcon#first serial, iclass 5, count 0 2006.257.20:01:07.43#ibcon#enter sib2, iclass 5, count 0 2006.257.20:01:07.43#ibcon#flushed, iclass 5, count 0 2006.257.20:01:07.43#ibcon#about to write, iclass 5, count 0 2006.257.20:01:07.43#ibcon#wrote, iclass 5, count 0 2006.257.20:01:07.43#ibcon#about to read 3, iclass 5, count 0 2006.257.20:01:07.45#ibcon#read 3, iclass 5, count 0 2006.257.20:01:07.45#ibcon#about to read 4, iclass 5, count 0 2006.257.20:01:07.45#ibcon#read 4, iclass 5, count 0 2006.257.20:01:07.45#ibcon#about to read 5, iclass 5, count 0 2006.257.20:01:07.45#ibcon#read 5, iclass 5, count 0 2006.257.20:01:07.45#ibcon#about to read 6, iclass 5, count 0 2006.257.20:01:07.45#ibcon#read 6, iclass 5, count 0 2006.257.20:01:07.45#ibcon#end of sib2, iclass 5, count 0 2006.257.20:01:07.45#ibcon#*mode == 0, iclass 5, count 0 2006.257.20:01:07.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.20:01:07.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.20:01:07.45#ibcon#*before write, iclass 5, count 0 2006.257.20:01:07.45#ibcon#enter sib2, iclass 5, count 0 2006.257.20:01:07.45#ibcon#flushed, iclass 5, count 0 2006.257.20:01:07.45#ibcon#about to write, iclass 5, count 0 2006.257.20:01:07.45#ibcon#wrote, iclass 5, count 0 2006.257.20:01:07.45#ibcon#about to read 3, iclass 5, count 0 2006.257.20:01:07.49#ibcon#read 3, iclass 5, count 0 2006.257.20:01:07.49#ibcon#about to read 4, iclass 5, count 0 2006.257.20:01:07.49#ibcon#read 4, iclass 5, count 0 2006.257.20:01:07.49#ibcon#about to read 5, iclass 5, count 0 2006.257.20:01:07.49#ibcon#read 5, iclass 5, count 0 2006.257.20:01:07.49#ibcon#about to read 6, iclass 5, count 0 2006.257.20:01:07.49#ibcon#read 6, iclass 5, count 0 2006.257.20:01:07.49#ibcon#end of sib2, iclass 5, count 0 2006.257.20:01:07.49#ibcon#*after write, iclass 5, count 0 2006.257.20:01:07.49#ibcon#*before return 0, iclass 5, count 0 2006.257.20:01:07.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:07.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:07.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.20:01:07.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.20:01:07.49$vck44/va=4,7 2006.257.20:01:07.49#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.20:01:07.49#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.20:01:07.49#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:07.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:07.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:07.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:07.55#ibcon#enter wrdev, iclass 7, count 2 2006.257.20:01:07.55#ibcon#first serial, iclass 7, count 2 2006.257.20:01:07.55#ibcon#enter sib2, iclass 7, count 2 2006.257.20:01:07.55#ibcon#flushed, iclass 7, count 2 2006.257.20:01:07.55#ibcon#about to write, iclass 7, count 2 2006.257.20:01:07.55#ibcon#wrote, iclass 7, count 2 2006.257.20:01:07.55#ibcon#about to read 3, iclass 7, count 2 2006.257.20:01:07.57#ibcon#read 3, iclass 7, count 2 2006.257.20:01:07.57#ibcon#about to read 4, iclass 7, count 2 2006.257.20:01:07.57#ibcon#read 4, iclass 7, count 2 2006.257.20:01:07.57#ibcon#about to read 5, iclass 7, count 2 2006.257.20:01:07.57#ibcon#read 5, iclass 7, count 2 2006.257.20:01:07.57#ibcon#about to read 6, iclass 7, count 2 2006.257.20:01:07.57#ibcon#read 6, iclass 7, count 2 2006.257.20:01:07.57#ibcon#end of sib2, iclass 7, count 2 2006.257.20:01:07.57#ibcon#*mode == 0, iclass 7, count 2 2006.257.20:01:07.57#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.20:01:07.57#ibcon#[25=AT04-07\r\n] 2006.257.20:01:07.57#ibcon#*before write, iclass 7, count 2 2006.257.20:01:07.57#ibcon#enter sib2, iclass 7, count 2 2006.257.20:01:07.57#ibcon#flushed, iclass 7, count 2 2006.257.20:01:07.57#ibcon#about to write, iclass 7, count 2 2006.257.20:01:07.57#ibcon#wrote, iclass 7, count 2 2006.257.20:01:07.57#ibcon#about to read 3, iclass 7, count 2 2006.257.20:01:07.60#ibcon#read 3, iclass 7, count 2 2006.257.20:01:07.60#ibcon#about to read 4, iclass 7, count 2 2006.257.20:01:07.60#ibcon#read 4, iclass 7, count 2 2006.257.20:01:07.60#ibcon#about to read 5, iclass 7, count 2 2006.257.20:01:07.60#ibcon#read 5, iclass 7, count 2 2006.257.20:01:07.60#ibcon#about to read 6, iclass 7, count 2 2006.257.20:01:07.60#ibcon#read 6, iclass 7, count 2 2006.257.20:01:07.60#ibcon#end of sib2, iclass 7, count 2 2006.257.20:01:07.60#ibcon#*after write, iclass 7, count 2 2006.257.20:01:07.60#ibcon#*before return 0, iclass 7, count 2 2006.257.20:01:07.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:07.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:07.60#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.20:01:07.60#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:07.60#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:07.72#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:07.72#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:07.72#ibcon#enter wrdev, iclass 7, count 0 2006.257.20:01:07.72#ibcon#first serial, iclass 7, count 0 2006.257.20:01:07.72#ibcon#enter sib2, iclass 7, count 0 2006.257.20:01:07.72#ibcon#flushed, iclass 7, count 0 2006.257.20:01:07.72#ibcon#about to write, iclass 7, count 0 2006.257.20:01:07.72#ibcon#wrote, iclass 7, count 0 2006.257.20:01:07.72#ibcon#about to read 3, iclass 7, count 0 2006.257.20:01:07.74#ibcon#read 3, iclass 7, count 0 2006.257.20:01:07.74#ibcon#about to read 4, iclass 7, count 0 2006.257.20:01:07.74#ibcon#read 4, iclass 7, count 0 2006.257.20:01:07.74#ibcon#about to read 5, iclass 7, count 0 2006.257.20:01:07.74#ibcon#read 5, iclass 7, count 0 2006.257.20:01:07.74#ibcon#about to read 6, iclass 7, count 0 2006.257.20:01:07.74#ibcon#read 6, iclass 7, count 0 2006.257.20:01:07.74#ibcon#end of sib2, iclass 7, count 0 2006.257.20:01:07.74#ibcon#*mode == 0, iclass 7, count 0 2006.257.20:01:07.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.20:01:07.74#ibcon#[25=USB\r\n] 2006.257.20:01:07.74#ibcon#*before write, iclass 7, count 0 2006.257.20:01:07.74#ibcon#enter sib2, iclass 7, count 0 2006.257.20:01:07.74#ibcon#flushed, iclass 7, count 0 2006.257.20:01:07.74#ibcon#about to write, iclass 7, count 0 2006.257.20:01:07.74#ibcon#wrote, iclass 7, count 0 2006.257.20:01:07.74#ibcon#about to read 3, iclass 7, count 0 2006.257.20:01:07.77#ibcon#read 3, iclass 7, count 0 2006.257.20:01:07.77#ibcon#about to read 4, iclass 7, count 0 2006.257.20:01:07.77#ibcon#read 4, iclass 7, count 0 2006.257.20:01:07.77#ibcon#about to read 5, iclass 7, count 0 2006.257.20:01:07.77#ibcon#read 5, iclass 7, count 0 2006.257.20:01:07.77#ibcon#about to read 6, iclass 7, count 0 2006.257.20:01:07.77#ibcon#read 6, iclass 7, count 0 2006.257.20:01:07.77#ibcon#end of sib2, iclass 7, count 0 2006.257.20:01:07.77#ibcon#*after write, iclass 7, count 0 2006.257.20:01:07.77#ibcon#*before return 0, iclass 7, count 0 2006.257.20:01:07.77#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:07.77#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:07.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.20:01:07.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.20:01:07.77$vck44/valo=5,734.99 2006.257.20:01:07.77#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.20:01:07.77#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.20:01:07.77#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:07.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:07.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:07.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:07.77#ibcon#enter wrdev, iclass 11, count 0 2006.257.20:01:07.77#ibcon#first serial, iclass 11, count 0 2006.257.20:01:07.77#ibcon#enter sib2, iclass 11, count 0 2006.257.20:01:07.77#ibcon#flushed, iclass 11, count 0 2006.257.20:01:07.77#ibcon#about to write, iclass 11, count 0 2006.257.20:01:07.77#ibcon#wrote, iclass 11, count 0 2006.257.20:01:07.77#ibcon#about to read 3, iclass 11, count 0 2006.257.20:01:07.79#ibcon#read 3, iclass 11, count 0 2006.257.20:01:07.79#ibcon#about to read 4, iclass 11, count 0 2006.257.20:01:07.79#ibcon#read 4, iclass 11, count 0 2006.257.20:01:07.79#ibcon#about to read 5, iclass 11, count 0 2006.257.20:01:07.79#ibcon#read 5, iclass 11, count 0 2006.257.20:01:07.79#ibcon#about to read 6, iclass 11, count 0 2006.257.20:01:07.79#ibcon#read 6, iclass 11, count 0 2006.257.20:01:07.79#ibcon#end of sib2, iclass 11, count 0 2006.257.20:01:07.79#ibcon#*mode == 0, iclass 11, count 0 2006.257.20:01:07.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.20:01:07.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.20:01:07.79#ibcon#*before write, iclass 11, count 0 2006.257.20:01:07.79#ibcon#enter sib2, iclass 11, count 0 2006.257.20:01:07.79#ibcon#flushed, iclass 11, count 0 2006.257.20:01:07.79#ibcon#about to write, iclass 11, count 0 2006.257.20:01:07.79#ibcon#wrote, iclass 11, count 0 2006.257.20:01:07.79#ibcon#about to read 3, iclass 11, count 0 2006.257.20:01:07.83#ibcon#read 3, iclass 11, count 0 2006.257.20:01:07.83#ibcon#about to read 4, iclass 11, count 0 2006.257.20:01:07.83#ibcon#read 4, iclass 11, count 0 2006.257.20:01:07.83#ibcon#about to read 5, iclass 11, count 0 2006.257.20:01:07.83#ibcon#read 5, iclass 11, count 0 2006.257.20:01:07.83#ibcon#about to read 6, iclass 11, count 0 2006.257.20:01:07.83#ibcon#read 6, iclass 11, count 0 2006.257.20:01:07.83#ibcon#end of sib2, iclass 11, count 0 2006.257.20:01:07.83#ibcon#*after write, iclass 11, count 0 2006.257.20:01:07.83#ibcon#*before return 0, iclass 11, count 0 2006.257.20:01:07.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:07.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:07.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.20:01:07.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.20:01:07.83$vck44/va=5,4 2006.257.20:01:07.83#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.20:01:07.83#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.20:01:07.83#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:07.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:07.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:07.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:07.89#ibcon#enter wrdev, iclass 13, count 2 2006.257.20:01:07.89#ibcon#first serial, iclass 13, count 2 2006.257.20:01:07.89#ibcon#enter sib2, iclass 13, count 2 2006.257.20:01:07.89#ibcon#flushed, iclass 13, count 2 2006.257.20:01:07.89#ibcon#about to write, iclass 13, count 2 2006.257.20:01:07.89#ibcon#wrote, iclass 13, count 2 2006.257.20:01:07.89#ibcon#about to read 3, iclass 13, count 2 2006.257.20:01:07.91#ibcon#read 3, iclass 13, count 2 2006.257.20:01:07.91#ibcon#about to read 4, iclass 13, count 2 2006.257.20:01:07.91#ibcon#read 4, iclass 13, count 2 2006.257.20:01:07.91#ibcon#about to read 5, iclass 13, count 2 2006.257.20:01:07.91#ibcon#read 5, iclass 13, count 2 2006.257.20:01:07.91#ibcon#about to read 6, iclass 13, count 2 2006.257.20:01:07.91#ibcon#read 6, iclass 13, count 2 2006.257.20:01:07.91#ibcon#end of sib2, iclass 13, count 2 2006.257.20:01:07.91#ibcon#*mode == 0, iclass 13, count 2 2006.257.20:01:07.91#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.20:01:07.91#ibcon#[25=AT05-04\r\n] 2006.257.20:01:07.91#ibcon#*before write, iclass 13, count 2 2006.257.20:01:07.91#ibcon#enter sib2, iclass 13, count 2 2006.257.20:01:07.91#ibcon#flushed, iclass 13, count 2 2006.257.20:01:07.91#ibcon#about to write, iclass 13, count 2 2006.257.20:01:07.91#ibcon#wrote, iclass 13, count 2 2006.257.20:01:07.91#ibcon#about to read 3, iclass 13, count 2 2006.257.20:01:07.94#ibcon#read 3, iclass 13, count 2 2006.257.20:01:07.94#ibcon#about to read 4, iclass 13, count 2 2006.257.20:01:07.94#ibcon#read 4, iclass 13, count 2 2006.257.20:01:07.94#ibcon#about to read 5, iclass 13, count 2 2006.257.20:01:07.94#ibcon#read 5, iclass 13, count 2 2006.257.20:01:07.94#ibcon#about to read 6, iclass 13, count 2 2006.257.20:01:07.94#ibcon#read 6, iclass 13, count 2 2006.257.20:01:07.94#ibcon#end of sib2, iclass 13, count 2 2006.257.20:01:07.94#ibcon#*after write, iclass 13, count 2 2006.257.20:01:07.94#ibcon#*before return 0, iclass 13, count 2 2006.257.20:01:07.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:07.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:07.94#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.20:01:07.94#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:07.94#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:08.06#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:08.06#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:08.06#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:01:08.06#ibcon#first serial, iclass 13, count 0 2006.257.20:01:08.06#ibcon#enter sib2, iclass 13, count 0 2006.257.20:01:08.06#ibcon#flushed, iclass 13, count 0 2006.257.20:01:08.06#ibcon#about to write, iclass 13, count 0 2006.257.20:01:08.06#ibcon#wrote, iclass 13, count 0 2006.257.20:01:08.06#ibcon#about to read 3, iclass 13, count 0 2006.257.20:01:08.08#ibcon#read 3, iclass 13, count 0 2006.257.20:01:08.08#ibcon#about to read 4, iclass 13, count 0 2006.257.20:01:08.08#ibcon#read 4, iclass 13, count 0 2006.257.20:01:08.08#ibcon#about to read 5, iclass 13, count 0 2006.257.20:01:08.08#ibcon#read 5, iclass 13, count 0 2006.257.20:01:08.08#ibcon#about to read 6, iclass 13, count 0 2006.257.20:01:08.08#ibcon#read 6, iclass 13, count 0 2006.257.20:01:08.08#ibcon#end of sib2, iclass 13, count 0 2006.257.20:01:08.08#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:01:08.08#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:01:08.08#ibcon#[25=USB\r\n] 2006.257.20:01:08.08#ibcon#*before write, iclass 13, count 0 2006.257.20:01:08.08#ibcon#enter sib2, iclass 13, count 0 2006.257.20:01:08.08#ibcon#flushed, iclass 13, count 0 2006.257.20:01:08.08#ibcon#about to write, iclass 13, count 0 2006.257.20:01:08.08#ibcon#wrote, iclass 13, count 0 2006.257.20:01:08.08#ibcon#about to read 3, iclass 13, count 0 2006.257.20:01:08.11#ibcon#read 3, iclass 13, count 0 2006.257.20:01:08.11#ibcon#about to read 4, iclass 13, count 0 2006.257.20:01:08.11#ibcon#read 4, iclass 13, count 0 2006.257.20:01:08.11#ibcon#about to read 5, iclass 13, count 0 2006.257.20:01:08.11#ibcon#read 5, iclass 13, count 0 2006.257.20:01:08.11#ibcon#about to read 6, iclass 13, count 0 2006.257.20:01:08.11#ibcon#read 6, iclass 13, count 0 2006.257.20:01:08.11#ibcon#end of sib2, iclass 13, count 0 2006.257.20:01:08.11#ibcon#*after write, iclass 13, count 0 2006.257.20:01:08.11#ibcon#*before return 0, iclass 13, count 0 2006.257.20:01:08.11#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:08.11#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:08.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:01:08.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:01:08.11$vck44/valo=6,814.99 2006.257.20:01:08.11#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.20:01:08.11#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.20:01:08.11#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:08.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:08.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:08.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:08.11#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:01:08.11#ibcon#first serial, iclass 15, count 0 2006.257.20:01:08.11#ibcon#enter sib2, iclass 15, count 0 2006.257.20:01:08.11#ibcon#flushed, iclass 15, count 0 2006.257.20:01:08.11#ibcon#about to write, iclass 15, count 0 2006.257.20:01:08.11#ibcon#wrote, iclass 15, count 0 2006.257.20:01:08.11#ibcon#about to read 3, iclass 15, count 0 2006.257.20:01:08.13#ibcon#read 3, iclass 15, count 0 2006.257.20:01:08.13#ibcon#about to read 4, iclass 15, count 0 2006.257.20:01:08.13#ibcon#read 4, iclass 15, count 0 2006.257.20:01:08.13#ibcon#about to read 5, iclass 15, count 0 2006.257.20:01:08.13#ibcon#read 5, iclass 15, count 0 2006.257.20:01:08.13#ibcon#about to read 6, iclass 15, count 0 2006.257.20:01:08.13#ibcon#read 6, iclass 15, count 0 2006.257.20:01:08.13#ibcon#end of sib2, iclass 15, count 0 2006.257.20:01:08.13#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:01:08.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:01:08.13#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.20:01:08.13#ibcon#*before write, iclass 15, count 0 2006.257.20:01:08.13#ibcon#enter sib2, iclass 15, count 0 2006.257.20:01:08.13#ibcon#flushed, iclass 15, count 0 2006.257.20:01:08.13#ibcon#about to write, iclass 15, count 0 2006.257.20:01:08.13#ibcon#wrote, iclass 15, count 0 2006.257.20:01:08.13#ibcon#about to read 3, iclass 15, count 0 2006.257.20:01:08.17#ibcon#read 3, iclass 15, count 0 2006.257.20:01:08.17#ibcon#about to read 4, iclass 15, count 0 2006.257.20:01:08.17#ibcon#read 4, iclass 15, count 0 2006.257.20:01:08.17#ibcon#about to read 5, iclass 15, count 0 2006.257.20:01:08.17#ibcon#read 5, iclass 15, count 0 2006.257.20:01:08.17#ibcon#about to read 6, iclass 15, count 0 2006.257.20:01:08.17#ibcon#read 6, iclass 15, count 0 2006.257.20:01:08.17#ibcon#end of sib2, iclass 15, count 0 2006.257.20:01:08.17#ibcon#*after write, iclass 15, count 0 2006.257.20:01:08.17#ibcon#*before return 0, iclass 15, count 0 2006.257.20:01:08.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:08.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:08.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:01:08.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:01:08.17$vck44/va=6,4 2006.257.20:01:08.17#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.20:01:08.17#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.20:01:08.17#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:08.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:08.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:08.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:08.23#ibcon#enter wrdev, iclass 17, count 2 2006.257.20:01:08.23#ibcon#first serial, iclass 17, count 2 2006.257.20:01:08.23#ibcon#enter sib2, iclass 17, count 2 2006.257.20:01:08.23#ibcon#flushed, iclass 17, count 2 2006.257.20:01:08.23#ibcon#about to write, iclass 17, count 2 2006.257.20:01:08.23#ibcon#wrote, iclass 17, count 2 2006.257.20:01:08.23#ibcon#about to read 3, iclass 17, count 2 2006.257.20:01:08.25#ibcon#read 3, iclass 17, count 2 2006.257.20:01:08.25#ibcon#about to read 4, iclass 17, count 2 2006.257.20:01:08.25#ibcon#read 4, iclass 17, count 2 2006.257.20:01:08.25#ibcon#about to read 5, iclass 17, count 2 2006.257.20:01:08.25#ibcon#read 5, iclass 17, count 2 2006.257.20:01:08.25#ibcon#about to read 6, iclass 17, count 2 2006.257.20:01:08.25#ibcon#read 6, iclass 17, count 2 2006.257.20:01:08.25#ibcon#end of sib2, iclass 17, count 2 2006.257.20:01:08.25#ibcon#*mode == 0, iclass 17, count 2 2006.257.20:01:08.25#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.20:01:08.25#ibcon#[25=AT06-04\r\n] 2006.257.20:01:08.25#ibcon#*before write, iclass 17, count 2 2006.257.20:01:08.25#ibcon#enter sib2, iclass 17, count 2 2006.257.20:01:08.25#ibcon#flushed, iclass 17, count 2 2006.257.20:01:08.25#ibcon#about to write, iclass 17, count 2 2006.257.20:01:08.25#ibcon#wrote, iclass 17, count 2 2006.257.20:01:08.25#ibcon#about to read 3, iclass 17, count 2 2006.257.20:01:08.28#ibcon#read 3, iclass 17, count 2 2006.257.20:01:08.28#ibcon#about to read 4, iclass 17, count 2 2006.257.20:01:08.28#ibcon#read 4, iclass 17, count 2 2006.257.20:01:08.28#ibcon#about to read 5, iclass 17, count 2 2006.257.20:01:08.28#ibcon#read 5, iclass 17, count 2 2006.257.20:01:08.28#ibcon#about to read 6, iclass 17, count 2 2006.257.20:01:08.28#ibcon#read 6, iclass 17, count 2 2006.257.20:01:08.28#ibcon#end of sib2, iclass 17, count 2 2006.257.20:01:08.28#ibcon#*after write, iclass 17, count 2 2006.257.20:01:08.28#ibcon#*before return 0, iclass 17, count 2 2006.257.20:01:08.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:08.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:08.28#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.20:01:08.28#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:08.28#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:08.40#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:08.40#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:08.40#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:01:08.40#ibcon#first serial, iclass 17, count 0 2006.257.20:01:08.40#ibcon#enter sib2, iclass 17, count 0 2006.257.20:01:08.40#ibcon#flushed, iclass 17, count 0 2006.257.20:01:08.40#ibcon#about to write, iclass 17, count 0 2006.257.20:01:08.40#ibcon#wrote, iclass 17, count 0 2006.257.20:01:08.40#ibcon#about to read 3, iclass 17, count 0 2006.257.20:01:08.42#ibcon#read 3, iclass 17, count 0 2006.257.20:01:08.42#ibcon#about to read 4, iclass 17, count 0 2006.257.20:01:08.42#ibcon#read 4, iclass 17, count 0 2006.257.20:01:08.42#ibcon#about to read 5, iclass 17, count 0 2006.257.20:01:08.42#ibcon#read 5, iclass 17, count 0 2006.257.20:01:08.42#ibcon#about to read 6, iclass 17, count 0 2006.257.20:01:08.42#ibcon#read 6, iclass 17, count 0 2006.257.20:01:08.42#ibcon#end of sib2, iclass 17, count 0 2006.257.20:01:08.42#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:01:08.42#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:01:08.42#ibcon#[25=USB\r\n] 2006.257.20:01:08.42#ibcon#*before write, iclass 17, count 0 2006.257.20:01:08.42#ibcon#enter sib2, iclass 17, count 0 2006.257.20:01:08.42#ibcon#flushed, iclass 17, count 0 2006.257.20:01:08.42#ibcon#about to write, iclass 17, count 0 2006.257.20:01:08.42#ibcon#wrote, iclass 17, count 0 2006.257.20:01:08.42#ibcon#about to read 3, iclass 17, count 0 2006.257.20:01:08.45#ibcon#read 3, iclass 17, count 0 2006.257.20:01:08.45#ibcon#about to read 4, iclass 17, count 0 2006.257.20:01:08.45#ibcon#read 4, iclass 17, count 0 2006.257.20:01:08.45#ibcon#about to read 5, iclass 17, count 0 2006.257.20:01:08.45#ibcon#read 5, iclass 17, count 0 2006.257.20:01:08.45#ibcon#about to read 6, iclass 17, count 0 2006.257.20:01:08.45#ibcon#read 6, iclass 17, count 0 2006.257.20:01:08.45#ibcon#end of sib2, iclass 17, count 0 2006.257.20:01:08.45#ibcon#*after write, iclass 17, count 0 2006.257.20:01:08.45#ibcon#*before return 0, iclass 17, count 0 2006.257.20:01:08.45#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:08.45#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:08.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:01:08.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:01:08.45$vck44/valo=7,864.99 2006.257.20:01:08.45#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.20:01:08.45#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.20:01:08.45#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:08.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:08.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:08.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:08.45#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:01:08.45#ibcon#first serial, iclass 19, count 0 2006.257.20:01:08.45#ibcon#enter sib2, iclass 19, count 0 2006.257.20:01:08.45#ibcon#flushed, iclass 19, count 0 2006.257.20:01:08.45#ibcon#about to write, iclass 19, count 0 2006.257.20:01:08.45#ibcon#wrote, iclass 19, count 0 2006.257.20:01:08.45#ibcon#about to read 3, iclass 19, count 0 2006.257.20:01:08.47#ibcon#read 3, iclass 19, count 0 2006.257.20:01:08.47#ibcon#about to read 4, iclass 19, count 0 2006.257.20:01:08.47#ibcon#read 4, iclass 19, count 0 2006.257.20:01:08.47#ibcon#about to read 5, iclass 19, count 0 2006.257.20:01:08.47#ibcon#read 5, iclass 19, count 0 2006.257.20:01:08.47#ibcon#about to read 6, iclass 19, count 0 2006.257.20:01:08.47#ibcon#read 6, iclass 19, count 0 2006.257.20:01:08.47#ibcon#end of sib2, iclass 19, count 0 2006.257.20:01:08.47#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:01:08.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:01:08.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.20:01:08.47#ibcon#*before write, iclass 19, count 0 2006.257.20:01:08.47#ibcon#enter sib2, iclass 19, count 0 2006.257.20:01:08.47#ibcon#flushed, iclass 19, count 0 2006.257.20:01:08.47#ibcon#about to write, iclass 19, count 0 2006.257.20:01:08.47#ibcon#wrote, iclass 19, count 0 2006.257.20:01:08.47#ibcon#about to read 3, iclass 19, count 0 2006.257.20:01:08.51#ibcon#read 3, iclass 19, count 0 2006.257.20:01:08.51#ibcon#about to read 4, iclass 19, count 0 2006.257.20:01:08.51#ibcon#read 4, iclass 19, count 0 2006.257.20:01:08.51#ibcon#about to read 5, iclass 19, count 0 2006.257.20:01:08.51#ibcon#read 5, iclass 19, count 0 2006.257.20:01:08.51#ibcon#about to read 6, iclass 19, count 0 2006.257.20:01:08.51#ibcon#read 6, iclass 19, count 0 2006.257.20:01:08.51#ibcon#end of sib2, iclass 19, count 0 2006.257.20:01:08.51#ibcon#*after write, iclass 19, count 0 2006.257.20:01:08.51#ibcon#*before return 0, iclass 19, count 0 2006.257.20:01:08.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:08.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:08.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:01:08.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:01:08.51$vck44/va=7,4 2006.257.20:01:08.51#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.20:01:08.51#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.20:01:08.51#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:08.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:08.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:08.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:08.57#ibcon#enter wrdev, iclass 21, count 2 2006.257.20:01:08.57#ibcon#first serial, iclass 21, count 2 2006.257.20:01:08.57#ibcon#enter sib2, iclass 21, count 2 2006.257.20:01:08.57#ibcon#flushed, iclass 21, count 2 2006.257.20:01:08.57#ibcon#about to write, iclass 21, count 2 2006.257.20:01:08.57#ibcon#wrote, iclass 21, count 2 2006.257.20:01:08.57#ibcon#about to read 3, iclass 21, count 2 2006.257.20:01:08.59#ibcon#read 3, iclass 21, count 2 2006.257.20:01:08.59#ibcon#about to read 4, iclass 21, count 2 2006.257.20:01:08.59#ibcon#read 4, iclass 21, count 2 2006.257.20:01:08.59#ibcon#about to read 5, iclass 21, count 2 2006.257.20:01:08.59#ibcon#read 5, iclass 21, count 2 2006.257.20:01:08.59#ibcon#about to read 6, iclass 21, count 2 2006.257.20:01:08.59#ibcon#read 6, iclass 21, count 2 2006.257.20:01:08.59#ibcon#end of sib2, iclass 21, count 2 2006.257.20:01:08.59#ibcon#*mode == 0, iclass 21, count 2 2006.257.20:01:08.59#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.20:01:08.59#ibcon#[25=AT07-04\r\n] 2006.257.20:01:08.59#ibcon#*before write, iclass 21, count 2 2006.257.20:01:08.59#ibcon#enter sib2, iclass 21, count 2 2006.257.20:01:08.59#ibcon#flushed, iclass 21, count 2 2006.257.20:01:08.59#ibcon#about to write, iclass 21, count 2 2006.257.20:01:08.59#ibcon#wrote, iclass 21, count 2 2006.257.20:01:08.59#ibcon#about to read 3, iclass 21, count 2 2006.257.20:01:08.62#ibcon#read 3, iclass 21, count 2 2006.257.20:01:08.62#ibcon#about to read 4, iclass 21, count 2 2006.257.20:01:08.62#ibcon#read 4, iclass 21, count 2 2006.257.20:01:08.62#ibcon#about to read 5, iclass 21, count 2 2006.257.20:01:08.62#ibcon#read 5, iclass 21, count 2 2006.257.20:01:08.62#ibcon#about to read 6, iclass 21, count 2 2006.257.20:01:08.62#ibcon#read 6, iclass 21, count 2 2006.257.20:01:08.62#ibcon#end of sib2, iclass 21, count 2 2006.257.20:01:08.62#ibcon#*after write, iclass 21, count 2 2006.257.20:01:08.62#ibcon#*before return 0, iclass 21, count 2 2006.257.20:01:08.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:08.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:08.62#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.20:01:08.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:08.62#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:08.74#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:08.74#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:08.74#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:01:08.74#ibcon#first serial, iclass 21, count 0 2006.257.20:01:08.74#ibcon#enter sib2, iclass 21, count 0 2006.257.20:01:08.74#ibcon#flushed, iclass 21, count 0 2006.257.20:01:08.74#ibcon#about to write, iclass 21, count 0 2006.257.20:01:08.74#ibcon#wrote, iclass 21, count 0 2006.257.20:01:08.74#ibcon#about to read 3, iclass 21, count 0 2006.257.20:01:08.76#ibcon#read 3, iclass 21, count 0 2006.257.20:01:08.76#ibcon#about to read 4, iclass 21, count 0 2006.257.20:01:08.76#ibcon#read 4, iclass 21, count 0 2006.257.20:01:08.76#ibcon#about to read 5, iclass 21, count 0 2006.257.20:01:08.76#ibcon#read 5, iclass 21, count 0 2006.257.20:01:08.76#ibcon#about to read 6, iclass 21, count 0 2006.257.20:01:08.76#ibcon#read 6, iclass 21, count 0 2006.257.20:01:08.76#ibcon#end of sib2, iclass 21, count 0 2006.257.20:01:08.76#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:01:08.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:01:08.76#ibcon#[25=USB\r\n] 2006.257.20:01:08.76#ibcon#*before write, iclass 21, count 0 2006.257.20:01:08.76#ibcon#enter sib2, iclass 21, count 0 2006.257.20:01:08.76#ibcon#flushed, iclass 21, count 0 2006.257.20:01:08.76#ibcon#about to write, iclass 21, count 0 2006.257.20:01:08.76#ibcon#wrote, iclass 21, count 0 2006.257.20:01:08.76#ibcon#about to read 3, iclass 21, count 0 2006.257.20:01:08.79#ibcon#read 3, iclass 21, count 0 2006.257.20:01:08.79#ibcon#about to read 4, iclass 21, count 0 2006.257.20:01:08.79#ibcon#read 4, iclass 21, count 0 2006.257.20:01:08.79#ibcon#about to read 5, iclass 21, count 0 2006.257.20:01:08.79#ibcon#read 5, iclass 21, count 0 2006.257.20:01:08.79#ibcon#about to read 6, iclass 21, count 0 2006.257.20:01:08.79#ibcon#read 6, iclass 21, count 0 2006.257.20:01:08.79#ibcon#end of sib2, iclass 21, count 0 2006.257.20:01:08.79#ibcon#*after write, iclass 21, count 0 2006.257.20:01:08.79#ibcon#*before return 0, iclass 21, count 0 2006.257.20:01:08.79#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:08.79#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:08.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:01:08.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:01:08.79$vck44/valo=8,884.99 2006.257.20:01:08.79#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.20:01:08.79#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.20:01:08.79#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:08.79#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:08.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:08.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:08.79#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:01:08.79#ibcon#first serial, iclass 23, count 0 2006.257.20:01:08.79#ibcon#enter sib2, iclass 23, count 0 2006.257.20:01:08.79#ibcon#flushed, iclass 23, count 0 2006.257.20:01:08.79#ibcon#about to write, iclass 23, count 0 2006.257.20:01:08.79#ibcon#wrote, iclass 23, count 0 2006.257.20:01:08.79#ibcon#about to read 3, iclass 23, count 0 2006.257.20:01:08.81#ibcon#read 3, iclass 23, count 0 2006.257.20:01:08.81#ibcon#about to read 4, iclass 23, count 0 2006.257.20:01:08.81#ibcon#read 4, iclass 23, count 0 2006.257.20:01:08.81#ibcon#about to read 5, iclass 23, count 0 2006.257.20:01:08.81#ibcon#read 5, iclass 23, count 0 2006.257.20:01:08.81#ibcon#about to read 6, iclass 23, count 0 2006.257.20:01:08.81#ibcon#read 6, iclass 23, count 0 2006.257.20:01:08.81#ibcon#end of sib2, iclass 23, count 0 2006.257.20:01:08.81#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:01:08.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:01:08.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.20:01:08.81#ibcon#*before write, iclass 23, count 0 2006.257.20:01:08.81#ibcon#enter sib2, iclass 23, count 0 2006.257.20:01:08.81#ibcon#flushed, iclass 23, count 0 2006.257.20:01:08.81#ibcon#about to write, iclass 23, count 0 2006.257.20:01:08.81#ibcon#wrote, iclass 23, count 0 2006.257.20:01:08.81#ibcon#about to read 3, iclass 23, count 0 2006.257.20:01:08.85#ibcon#read 3, iclass 23, count 0 2006.257.20:01:08.85#ibcon#about to read 4, iclass 23, count 0 2006.257.20:01:08.85#ibcon#read 4, iclass 23, count 0 2006.257.20:01:08.85#ibcon#about to read 5, iclass 23, count 0 2006.257.20:01:08.85#ibcon#read 5, iclass 23, count 0 2006.257.20:01:08.85#ibcon#about to read 6, iclass 23, count 0 2006.257.20:01:08.85#ibcon#read 6, iclass 23, count 0 2006.257.20:01:08.85#ibcon#end of sib2, iclass 23, count 0 2006.257.20:01:08.85#ibcon#*after write, iclass 23, count 0 2006.257.20:01:08.85#ibcon#*before return 0, iclass 23, count 0 2006.257.20:01:08.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:08.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:08.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:01:08.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:01:08.85$vck44/va=8,4 2006.257.20:01:08.85#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.20:01:08.85#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.20:01:08.85#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:08.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:01:08.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:01:08.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:01:08.91#ibcon#enter wrdev, iclass 25, count 2 2006.257.20:01:08.91#ibcon#first serial, iclass 25, count 2 2006.257.20:01:08.91#ibcon#enter sib2, iclass 25, count 2 2006.257.20:01:08.91#ibcon#flushed, iclass 25, count 2 2006.257.20:01:08.91#ibcon#about to write, iclass 25, count 2 2006.257.20:01:08.91#ibcon#wrote, iclass 25, count 2 2006.257.20:01:08.91#ibcon#about to read 3, iclass 25, count 2 2006.257.20:01:08.93#ibcon#read 3, iclass 25, count 2 2006.257.20:01:08.93#ibcon#about to read 4, iclass 25, count 2 2006.257.20:01:08.93#ibcon#read 4, iclass 25, count 2 2006.257.20:01:08.93#ibcon#about to read 5, iclass 25, count 2 2006.257.20:01:08.93#ibcon#read 5, iclass 25, count 2 2006.257.20:01:08.93#ibcon#about to read 6, iclass 25, count 2 2006.257.20:01:08.93#ibcon#read 6, iclass 25, count 2 2006.257.20:01:08.93#ibcon#end of sib2, iclass 25, count 2 2006.257.20:01:08.93#ibcon#*mode == 0, iclass 25, count 2 2006.257.20:01:08.93#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.20:01:08.93#ibcon#[25=AT08-04\r\n] 2006.257.20:01:08.93#ibcon#*before write, iclass 25, count 2 2006.257.20:01:08.93#ibcon#enter sib2, iclass 25, count 2 2006.257.20:01:08.93#ibcon#flushed, iclass 25, count 2 2006.257.20:01:08.93#ibcon#about to write, iclass 25, count 2 2006.257.20:01:08.93#ibcon#wrote, iclass 25, count 2 2006.257.20:01:08.93#ibcon#about to read 3, iclass 25, count 2 2006.257.20:01:08.96#ibcon#read 3, iclass 25, count 2 2006.257.20:01:08.96#ibcon#about to read 4, iclass 25, count 2 2006.257.20:01:08.96#ibcon#read 4, iclass 25, count 2 2006.257.20:01:08.96#ibcon#about to read 5, iclass 25, count 2 2006.257.20:01:08.96#ibcon#read 5, iclass 25, count 2 2006.257.20:01:08.96#ibcon#about to read 6, iclass 25, count 2 2006.257.20:01:08.96#ibcon#read 6, iclass 25, count 2 2006.257.20:01:08.96#ibcon#end of sib2, iclass 25, count 2 2006.257.20:01:08.96#ibcon#*after write, iclass 25, count 2 2006.257.20:01:08.96#ibcon#*before return 0, iclass 25, count 2 2006.257.20:01:08.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:01:08.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:01:08.96#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.20:01:08.96#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:08.96#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:01:09.08#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:01:09.08#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:01:09.08#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:01:09.08#ibcon#first serial, iclass 25, count 0 2006.257.20:01:09.08#ibcon#enter sib2, iclass 25, count 0 2006.257.20:01:09.08#ibcon#flushed, iclass 25, count 0 2006.257.20:01:09.08#ibcon#about to write, iclass 25, count 0 2006.257.20:01:09.08#ibcon#wrote, iclass 25, count 0 2006.257.20:01:09.08#ibcon#about to read 3, iclass 25, count 0 2006.257.20:01:09.10#ibcon#read 3, iclass 25, count 0 2006.257.20:01:09.10#ibcon#about to read 4, iclass 25, count 0 2006.257.20:01:09.10#ibcon#read 4, iclass 25, count 0 2006.257.20:01:09.10#ibcon#about to read 5, iclass 25, count 0 2006.257.20:01:09.10#ibcon#read 5, iclass 25, count 0 2006.257.20:01:09.10#ibcon#about to read 6, iclass 25, count 0 2006.257.20:01:09.10#ibcon#read 6, iclass 25, count 0 2006.257.20:01:09.10#ibcon#end of sib2, iclass 25, count 0 2006.257.20:01:09.10#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:01:09.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:01:09.10#ibcon#[25=USB\r\n] 2006.257.20:01:09.10#ibcon#*before write, iclass 25, count 0 2006.257.20:01:09.10#ibcon#enter sib2, iclass 25, count 0 2006.257.20:01:09.10#ibcon#flushed, iclass 25, count 0 2006.257.20:01:09.10#ibcon#about to write, iclass 25, count 0 2006.257.20:01:09.10#ibcon#wrote, iclass 25, count 0 2006.257.20:01:09.10#ibcon#about to read 3, iclass 25, count 0 2006.257.20:01:09.13#ibcon#read 3, iclass 25, count 0 2006.257.20:01:09.13#ibcon#about to read 4, iclass 25, count 0 2006.257.20:01:09.13#ibcon#read 4, iclass 25, count 0 2006.257.20:01:09.13#ibcon#about to read 5, iclass 25, count 0 2006.257.20:01:09.13#ibcon#read 5, iclass 25, count 0 2006.257.20:01:09.13#ibcon#about to read 6, iclass 25, count 0 2006.257.20:01:09.13#ibcon#read 6, iclass 25, count 0 2006.257.20:01:09.13#ibcon#end of sib2, iclass 25, count 0 2006.257.20:01:09.13#ibcon#*after write, iclass 25, count 0 2006.257.20:01:09.13#ibcon#*before return 0, iclass 25, count 0 2006.257.20:01:09.13#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:01:09.13#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:01:09.13#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:01:09.13#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:01:09.13$vck44/vblo=1,629.99 2006.257.20:01:09.13#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.20:01:09.13#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.20:01:09.13#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:09.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:09.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:09.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:09.13#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:01:09.13#ibcon#first serial, iclass 27, count 0 2006.257.20:01:09.13#ibcon#enter sib2, iclass 27, count 0 2006.257.20:01:09.13#ibcon#flushed, iclass 27, count 0 2006.257.20:01:09.13#ibcon#about to write, iclass 27, count 0 2006.257.20:01:09.13#ibcon#wrote, iclass 27, count 0 2006.257.20:01:09.13#ibcon#about to read 3, iclass 27, count 0 2006.257.20:01:09.15#ibcon#read 3, iclass 27, count 0 2006.257.20:01:09.15#ibcon#about to read 4, iclass 27, count 0 2006.257.20:01:09.15#ibcon#read 4, iclass 27, count 0 2006.257.20:01:09.15#ibcon#about to read 5, iclass 27, count 0 2006.257.20:01:09.15#ibcon#read 5, iclass 27, count 0 2006.257.20:01:09.15#ibcon#about to read 6, iclass 27, count 0 2006.257.20:01:09.15#ibcon#read 6, iclass 27, count 0 2006.257.20:01:09.15#ibcon#end of sib2, iclass 27, count 0 2006.257.20:01:09.15#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:01:09.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:01:09.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.20:01:09.15#ibcon#*before write, iclass 27, count 0 2006.257.20:01:09.15#ibcon#enter sib2, iclass 27, count 0 2006.257.20:01:09.15#ibcon#flushed, iclass 27, count 0 2006.257.20:01:09.15#ibcon#about to write, iclass 27, count 0 2006.257.20:01:09.15#ibcon#wrote, iclass 27, count 0 2006.257.20:01:09.15#ibcon#about to read 3, iclass 27, count 0 2006.257.20:01:09.19#ibcon#read 3, iclass 27, count 0 2006.257.20:01:09.19#ibcon#about to read 4, iclass 27, count 0 2006.257.20:01:09.19#ibcon#read 4, iclass 27, count 0 2006.257.20:01:09.19#ibcon#about to read 5, iclass 27, count 0 2006.257.20:01:09.19#ibcon#read 5, iclass 27, count 0 2006.257.20:01:09.19#ibcon#about to read 6, iclass 27, count 0 2006.257.20:01:09.19#ibcon#read 6, iclass 27, count 0 2006.257.20:01:09.19#ibcon#end of sib2, iclass 27, count 0 2006.257.20:01:09.19#ibcon#*after write, iclass 27, count 0 2006.257.20:01:09.19#ibcon#*before return 0, iclass 27, count 0 2006.257.20:01:09.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:09.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:01:09.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:01:09.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:01:09.19$vck44/vb=1,4 2006.257.20:01:09.19#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.20:01:09.19#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.20:01:09.19#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:09.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:09.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:09.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:09.19#ibcon#enter wrdev, iclass 29, count 2 2006.257.20:01:09.19#ibcon#first serial, iclass 29, count 2 2006.257.20:01:09.19#ibcon#enter sib2, iclass 29, count 2 2006.257.20:01:09.19#ibcon#flushed, iclass 29, count 2 2006.257.20:01:09.19#ibcon#about to write, iclass 29, count 2 2006.257.20:01:09.19#ibcon#wrote, iclass 29, count 2 2006.257.20:01:09.19#ibcon#about to read 3, iclass 29, count 2 2006.257.20:01:09.21#ibcon#read 3, iclass 29, count 2 2006.257.20:01:09.21#ibcon#about to read 4, iclass 29, count 2 2006.257.20:01:09.21#ibcon#read 4, iclass 29, count 2 2006.257.20:01:09.21#ibcon#about to read 5, iclass 29, count 2 2006.257.20:01:09.21#ibcon#read 5, iclass 29, count 2 2006.257.20:01:09.21#ibcon#about to read 6, iclass 29, count 2 2006.257.20:01:09.21#ibcon#read 6, iclass 29, count 2 2006.257.20:01:09.21#ibcon#end of sib2, iclass 29, count 2 2006.257.20:01:09.21#ibcon#*mode == 0, iclass 29, count 2 2006.257.20:01:09.21#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.20:01:09.21#ibcon#[27=AT01-04\r\n] 2006.257.20:01:09.21#ibcon#*before write, iclass 29, count 2 2006.257.20:01:09.21#ibcon#enter sib2, iclass 29, count 2 2006.257.20:01:09.21#ibcon#flushed, iclass 29, count 2 2006.257.20:01:09.21#ibcon#about to write, iclass 29, count 2 2006.257.20:01:09.21#ibcon#wrote, iclass 29, count 2 2006.257.20:01:09.21#ibcon#about to read 3, iclass 29, count 2 2006.257.20:01:09.24#ibcon#read 3, iclass 29, count 2 2006.257.20:01:09.24#ibcon#about to read 4, iclass 29, count 2 2006.257.20:01:09.24#ibcon#read 4, iclass 29, count 2 2006.257.20:01:09.24#ibcon#about to read 5, iclass 29, count 2 2006.257.20:01:09.24#ibcon#read 5, iclass 29, count 2 2006.257.20:01:09.24#ibcon#about to read 6, iclass 29, count 2 2006.257.20:01:09.24#ibcon#read 6, iclass 29, count 2 2006.257.20:01:09.24#ibcon#end of sib2, iclass 29, count 2 2006.257.20:01:09.24#ibcon#*after write, iclass 29, count 2 2006.257.20:01:09.24#ibcon#*before return 0, iclass 29, count 2 2006.257.20:01:09.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:09.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:01:09.24#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.20:01:09.24#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:09.24#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:09.36#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:09.36#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:09.36#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:01:09.36#ibcon#first serial, iclass 29, count 0 2006.257.20:01:09.36#ibcon#enter sib2, iclass 29, count 0 2006.257.20:01:09.36#ibcon#flushed, iclass 29, count 0 2006.257.20:01:09.36#ibcon#about to write, iclass 29, count 0 2006.257.20:01:09.36#ibcon#wrote, iclass 29, count 0 2006.257.20:01:09.36#ibcon#about to read 3, iclass 29, count 0 2006.257.20:01:09.38#ibcon#read 3, iclass 29, count 0 2006.257.20:01:09.38#ibcon#about to read 4, iclass 29, count 0 2006.257.20:01:09.38#ibcon#read 4, iclass 29, count 0 2006.257.20:01:09.38#ibcon#about to read 5, iclass 29, count 0 2006.257.20:01:09.38#ibcon#read 5, iclass 29, count 0 2006.257.20:01:09.38#ibcon#about to read 6, iclass 29, count 0 2006.257.20:01:09.38#ibcon#read 6, iclass 29, count 0 2006.257.20:01:09.38#ibcon#end of sib2, iclass 29, count 0 2006.257.20:01:09.38#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:01:09.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:01:09.38#ibcon#[27=USB\r\n] 2006.257.20:01:09.38#ibcon#*before write, iclass 29, count 0 2006.257.20:01:09.38#ibcon#enter sib2, iclass 29, count 0 2006.257.20:01:09.38#ibcon#flushed, iclass 29, count 0 2006.257.20:01:09.38#ibcon#about to write, iclass 29, count 0 2006.257.20:01:09.38#ibcon#wrote, iclass 29, count 0 2006.257.20:01:09.38#ibcon#about to read 3, iclass 29, count 0 2006.257.20:01:09.41#ibcon#read 3, iclass 29, count 0 2006.257.20:01:09.41#ibcon#about to read 4, iclass 29, count 0 2006.257.20:01:09.41#ibcon#read 4, iclass 29, count 0 2006.257.20:01:09.41#ibcon#about to read 5, iclass 29, count 0 2006.257.20:01:09.41#ibcon#read 5, iclass 29, count 0 2006.257.20:01:09.41#ibcon#about to read 6, iclass 29, count 0 2006.257.20:01:09.41#ibcon#read 6, iclass 29, count 0 2006.257.20:01:09.41#ibcon#end of sib2, iclass 29, count 0 2006.257.20:01:09.41#ibcon#*after write, iclass 29, count 0 2006.257.20:01:09.41#ibcon#*before return 0, iclass 29, count 0 2006.257.20:01:09.41#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:09.41#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:01:09.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:01:09.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:01:09.41$vck44/vblo=2,634.99 2006.257.20:01:09.41#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.20:01:09.41#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.20:01:09.41#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:09.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:01:09.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:01:09.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:01:09.41#ibcon#enter wrdev, iclass 31, count 0 2006.257.20:01:09.41#ibcon#first serial, iclass 31, count 0 2006.257.20:01:09.41#ibcon#enter sib2, iclass 31, count 0 2006.257.20:01:09.41#ibcon#flushed, iclass 31, count 0 2006.257.20:01:09.41#ibcon#about to write, iclass 31, count 0 2006.257.20:01:09.41#ibcon#wrote, iclass 31, count 0 2006.257.20:01:09.41#ibcon#about to read 3, iclass 31, count 0 2006.257.20:01:09.43#ibcon#read 3, iclass 31, count 0 2006.257.20:01:09.43#ibcon#about to read 4, iclass 31, count 0 2006.257.20:01:09.43#ibcon#read 4, iclass 31, count 0 2006.257.20:01:09.43#ibcon#about to read 5, iclass 31, count 0 2006.257.20:01:09.43#ibcon#read 5, iclass 31, count 0 2006.257.20:01:09.43#ibcon#about to read 6, iclass 31, count 0 2006.257.20:01:09.43#ibcon#read 6, iclass 31, count 0 2006.257.20:01:09.43#ibcon#end of sib2, iclass 31, count 0 2006.257.20:01:09.43#ibcon#*mode == 0, iclass 31, count 0 2006.257.20:01:09.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.20:01:09.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.20:01:09.43#ibcon#*before write, iclass 31, count 0 2006.257.20:01:09.43#ibcon#enter sib2, iclass 31, count 0 2006.257.20:01:09.43#ibcon#flushed, iclass 31, count 0 2006.257.20:01:09.43#ibcon#about to write, iclass 31, count 0 2006.257.20:01:09.43#ibcon#wrote, iclass 31, count 0 2006.257.20:01:09.43#ibcon#about to read 3, iclass 31, count 0 2006.257.20:01:09.47#ibcon#read 3, iclass 31, count 0 2006.257.20:01:09.47#ibcon#about to read 4, iclass 31, count 0 2006.257.20:01:09.47#ibcon#read 4, iclass 31, count 0 2006.257.20:01:09.47#ibcon#about to read 5, iclass 31, count 0 2006.257.20:01:09.47#ibcon#read 5, iclass 31, count 0 2006.257.20:01:09.47#ibcon#about to read 6, iclass 31, count 0 2006.257.20:01:09.47#ibcon#read 6, iclass 31, count 0 2006.257.20:01:09.47#ibcon#end of sib2, iclass 31, count 0 2006.257.20:01:09.47#ibcon#*after write, iclass 31, count 0 2006.257.20:01:09.47#ibcon#*before return 0, iclass 31, count 0 2006.257.20:01:09.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:01:09.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:01:09.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.20:01:09.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.20:01:09.47$vck44/vb=2,5 2006.257.20:01:09.47#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.20:01:09.47#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.20:01:09.47#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:09.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:01:09.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:01:09.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:01:09.53#ibcon#enter wrdev, iclass 33, count 2 2006.257.20:01:09.53#ibcon#first serial, iclass 33, count 2 2006.257.20:01:09.53#ibcon#enter sib2, iclass 33, count 2 2006.257.20:01:09.53#ibcon#flushed, iclass 33, count 2 2006.257.20:01:09.53#ibcon#about to write, iclass 33, count 2 2006.257.20:01:09.53#ibcon#wrote, iclass 33, count 2 2006.257.20:01:09.53#ibcon#about to read 3, iclass 33, count 2 2006.257.20:01:09.55#ibcon#read 3, iclass 33, count 2 2006.257.20:01:09.55#ibcon#about to read 4, iclass 33, count 2 2006.257.20:01:09.55#ibcon#read 4, iclass 33, count 2 2006.257.20:01:09.55#ibcon#about to read 5, iclass 33, count 2 2006.257.20:01:09.55#ibcon#read 5, iclass 33, count 2 2006.257.20:01:09.55#ibcon#about to read 6, iclass 33, count 2 2006.257.20:01:09.55#ibcon#read 6, iclass 33, count 2 2006.257.20:01:09.55#ibcon#end of sib2, iclass 33, count 2 2006.257.20:01:09.55#ibcon#*mode == 0, iclass 33, count 2 2006.257.20:01:09.55#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.20:01:09.55#ibcon#[27=AT02-05\r\n] 2006.257.20:01:09.55#ibcon#*before write, iclass 33, count 2 2006.257.20:01:09.55#ibcon#enter sib2, iclass 33, count 2 2006.257.20:01:09.55#ibcon#flushed, iclass 33, count 2 2006.257.20:01:09.55#ibcon#about to write, iclass 33, count 2 2006.257.20:01:09.55#ibcon#wrote, iclass 33, count 2 2006.257.20:01:09.55#ibcon#about to read 3, iclass 33, count 2 2006.257.20:01:09.58#ibcon#read 3, iclass 33, count 2 2006.257.20:01:09.58#ibcon#about to read 4, iclass 33, count 2 2006.257.20:01:09.58#ibcon#read 4, iclass 33, count 2 2006.257.20:01:09.58#ibcon#about to read 5, iclass 33, count 2 2006.257.20:01:09.58#ibcon#read 5, iclass 33, count 2 2006.257.20:01:09.58#ibcon#about to read 6, iclass 33, count 2 2006.257.20:01:09.58#ibcon#read 6, iclass 33, count 2 2006.257.20:01:09.58#ibcon#end of sib2, iclass 33, count 2 2006.257.20:01:09.58#ibcon#*after write, iclass 33, count 2 2006.257.20:01:09.58#ibcon#*before return 0, iclass 33, count 2 2006.257.20:01:09.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:01:09.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:01:09.58#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.20:01:09.58#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:09.58#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:01:09.70#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:01:09.70#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:01:09.70#ibcon#enter wrdev, iclass 33, count 0 2006.257.20:01:09.70#ibcon#first serial, iclass 33, count 0 2006.257.20:01:09.70#ibcon#enter sib2, iclass 33, count 0 2006.257.20:01:09.70#ibcon#flushed, iclass 33, count 0 2006.257.20:01:09.70#ibcon#about to write, iclass 33, count 0 2006.257.20:01:09.70#ibcon#wrote, iclass 33, count 0 2006.257.20:01:09.70#ibcon#about to read 3, iclass 33, count 0 2006.257.20:01:09.72#ibcon#read 3, iclass 33, count 0 2006.257.20:01:09.72#ibcon#about to read 4, iclass 33, count 0 2006.257.20:01:09.72#ibcon#read 4, iclass 33, count 0 2006.257.20:01:09.72#ibcon#about to read 5, iclass 33, count 0 2006.257.20:01:09.72#ibcon#read 5, iclass 33, count 0 2006.257.20:01:09.72#ibcon#about to read 6, iclass 33, count 0 2006.257.20:01:09.72#ibcon#read 6, iclass 33, count 0 2006.257.20:01:09.72#ibcon#end of sib2, iclass 33, count 0 2006.257.20:01:09.72#ibcon#*mode == 0, iclass 33, count 0 2006.257.20:01:09.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.20:01:09.72#ibcon#[27=USB\r\n] 2006.257.20:01:09.72#ibcon#*before write, iclass 33, count 0 2006.257.20:01:09.72#ibcon#enter sib2, iclass 33, count 0 2006.257.20:01:09.72#ibcon#flushed, iclass 33, count 0 2006.257.20:01:09.72#ibcon#about to write, iclass 33, count 0 2006.257.20:01:09.72#ibcon#wrote, iclass 33, count 0 2006.257.20:01:09.72#ibcon#about to read 3, iclass 33, count 0 2006.257.20:01:09.75#ibcon#read 3, iclass 33, count 0 2006.257.20:01:09.75#ibcon#about to read 4, iclass 33, count 0 2006.257.20:01:09.75#ibcon#read 4, iclass 33, count 0 2006.257.20:01:09.75#ibcon#about to read 5, iclass 33, count 0 2006.257.20:01:09.75#ibcon#read 5, iclass 33, count 0 2006.257.20:01:09.75#ibcon#about to read 6, iclass 33, count 0 2006.257.20:01:09.75#ibcon#read 6, iclass 33, count 0 2006.257.20:01:09.75#ibcon#end of sib2, iclass 33, count 0 2006.257.20:01:09.75#ibcon#*after write, iclass 33, count 0 2006.257.20:01:09.75#ibcon#*before return 0, iclass 33, count 0 2006.257.20:01:09.75#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:01:09.75#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:01:09.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.20:01:09.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.20:01:09.75$vck44/vblo=3,649.99 2006.257.20:01:09.75#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.20:01:09.75#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.20:01:09.75#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:09.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:09.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:09.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:09.75#ibcon#enter wrdev, iclass 35, count 0 2006.257.20:01:09.75#ibcon#first serial, iclass 35, count 0 2006.257.20:01:09.75#ibcon#enter sib2, iclass 35, count 0 2006.257.20:01:09.75#ibcon#flushed, iclass 35, count 0 2006.257.20:01:09.75#ibcon#about to write, iclass 35, count 0 2006.257.20:01:09.75#ibcon#wrote, iclass 35, count 0 2006.257.20:01:09.75#ibcon#about to read 3, iclass 35, count 0 2006.257.20:01:09.77#ibcon#read 3, iclass 35, count 0 2006.257.20:01:09.77#ibcon#about to read 4, iclass 35, count 0 2006.257.20:01:09.77#ibcon#read 4, iclass 35, count 0 2006.257.20:01:09.77#ibcon#about to read 5, iclass 35, count 0 2006.257.20:01:09.77#ibcon#read 5, iclass 35, count 0 2006.257.20:01:09.77#ibcon#about to read 6, iclass 35, count 0 2006.257.20:01:09.77#ibcon#read 6, iclass 35, count 0 2006.257.20:01:09.77#ibcon#end of sib2, iclass 35, count 0 2006.257.20:01:09.77#ibcon#*mode == 0, iclass 35, count 0 2006.257.20:01:09.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.20:01:09.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.20:01:09.77#ibcon#*before write, iclass 35, count 0 2006.257.20:01:09.77#ibcon#enter sib2, iclass 35, count 0 2006.257.20:01:09.77#ibcon#flushed, iclass 35, count 0 2006.257.20:01:09.77#ibcon#about to write, iclass 35, count 0 2006.257.20:01:09.77#ibcon#wrote, iclass 35, count 0 2006.257.20:01:09.77#ibcon#about to read 3, iclass 35, count 0 2006.257.20:01:09.81#ibcon#read 3, iclass 35, count 0 2006.257.20:01:09.81#ibcon#about to read 4, iclass 35, count 0 2006.257.20:01:09.81#ibcon#read 4, iclass 35, count 0 2006.257.20:01:09.81#ibcon#about to read 5, iclass 35, count 0 2006.257.20:01:09.81#ibcon#read 5, iclass 35, count 0 2006.257.20:01:09.81#ibcon#about to read 6, iclass 35, count 0 2006.257.20:01:09.81#ibcon#read 6, iclass 35, count 0 2006.257.20:01:09.81#ibcon#end of sib2, iclass 35, count 0 2006.257.20:01:09.81#ibcon#*after write, iclass 35, count 0 2006.257.20:01:09.81#ibcon#*before return 0, iclass 35, count 0 2006.257.20:01:09.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:09.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:01:09.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.20:01:09.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.20:01:09.81$vck44/vb=3,4 2006.257.20:01:09.81#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.20:01:09.81#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.20:01:09.81#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:09.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:09.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:09.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:09.87#ibcon#enter wrdev, iclass 37, count 2 2006.257.20:01:09.87#ibcon#first serial, iclass 37, count 2 2006.257.20:01:09.87#ibcon#enter sib2, iclass 37, count 2 2006.257.20:01:09.87#ibcon#flushed, iclass 37, count 2 2006.257.20:01:09.87#ibcon#about to write, iclass 37, count 2 2006.257.20:01:09.87#ibcon#wrote, iclass 37, count 2 2006.257.20:01:09.87#ibcon#about to read 3, iclass 37, count 2 2006.257.20:01:09.89#ibcon#read 3, iclass 37, count 2 2006.257.20:01:09.89#ibcon#about to read 4, iclass 37, count 2 2006.257.20:01:09.89#ibcon#read 4, iclass 37, count 2 2006.257.20:01:09.89#ibcon#about to read 5, iclass 37, count 2 2006.257.20:01:09.89#ibcon#read 5, iclass 37, count 2 2006.257.20:01:09.89#ibcon#about to read 6, iclass 37, count 2 2006.257.20:01:09.89#ibcon#read 6, iclass 37, count 2 2006.257.20:01:09.89#ibcon#end of sib2, iclass 37, count 2 2006.257.20:01:09.89#ibcon#*mode == 0, iclass 37, count 2 2006.257.20:01:09.89#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.20:01:09.89#ibcon#[27=AT03-04\r\n] 2006.257.20:01:09.89#ibcon#*before write, iclass 37, count 2 2006.257.20:01:09.89#ibcon#enter sib2, iclass 37, count 2 2006.257.20:01:09.89#ibcon#flushed, iclass 37, count 2 2006.257.20:01:09.89#ibcon#about to write, iclass 37, count 2 2006.257.20:01:09.89#ibcon#wrote, iclass 37, count 2 2006.257.20:01:09.89#ibcon#about to read 3, iclass 37, count 2 2006.257.20:01:09.92#ibcon#read 3, iclass 37, count 2 2006.257.20:01:09.92#ibcon#about to read 4, iclass 37, count 2 2006.257.20:01:09.92#ibcon#read 4, iclass 37, count 2 2006.257.20:01:09.92#ibcon#about to read 5, iclass 37, count 2 2006.257.20:01:09.92#ibcon#read 5, iclass 37, count 2 2006.257.20:01:09.92#ibcon#about to read 6, iclass 37, count 2 2006.257.20:01:09.92#ibcon#read 6, iclass 37, count 2 2006.257.20:01:09.92#ibcon#end of sib2, iclass 37, count 2 2006.257.20:01:09.92#ibcon#*after write, iclass 37, count 2 2006.257.20:01:09.92#ibcon#*before return 0, iclass 37, count 2 2006.257.20:01:09.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:09.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:01:09.92#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.20:01:09.92#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:09.92#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:10.04#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:10.04#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:10.04#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:01:10.04#ibcon#first serial, iclass 37, count 0 2006.257.20:01:10.04#ibcon#enter sib2, iclass 37, count 0 2006.257.20:01:10.04#ibcon#flushed, iclass 37, count 0 2006.257.20:01:10.04#ibcon#about to write, iclass 37, count 0 2006.257.20:01:10.04#ibcon#wrote, iclass 37, count 0 2006.257.20:01:10.04#ibcon#about to read 3, iclass 37, count 0 2006.257.20:01:10.06#ibcon#read 3, iclass 37, count 0 2006.257.20:01:10.06#ibcon#about to read 4, iclass 37, count 0 2006.257.20:01:10.06#ibcon#read 4, iclass 37, count 0 2006.257.20:01:10.06#ibcon#about to read 5, iclass 37, count 0 2006.257.20:01:10.06#ibcon#read 5, iclass 37, count 0 2006.257.20:01:10.06#ibcon#about to read 6, iclass 37, count 0 2006.257.20:01:10.06#ibcon#read 6, iclass 37, count 0 2006.257.20:01:10.06#ibcon#end of sib2, iclass 37, count 0 2006.257.20:01:10.06#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:01:10.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:01:10.06#ibcon#[27=USB\r\n] 2006.257.20:01:10.06#ibcon#*before write, iclass 37, count 0 2006.257.20:01:10.06#ibcon#enter sib2, iclass 37, count 0 2006.257.20:01:10.06#ibcon#flushed, iclass 37, count 0 2006.257.20:01:10.06#ibcon#about to write, iclass 37, count 0 2006.257.20:01:10.06#ibcon#wrote, iclass 37, count 0 2006.257.20:01:10.06#ibcon#about to read 3, iclass 37, count 0 2006.257.20:01:10.09#ibcon#read 3, iclass 37, count 0 2006.257.20:01:10.09#ibcon#about to read 4, iclass 37, count 0 2006.257.20:01:10.09#ibcon#read 4, iclass 37, count 0 2006.257.20:01:10.09#ibcon#about to read 5, iclass 37, count 0 2006.257.20:01:10.09#ibcon#read 5, iclass 37, count 0 2006.257.20:01:10.09#ibcon#about to read 6, iclass 37, count 0 2006.257.20:01:10.09#ibcon#read 6, iclass 37, count 0 2006.257.20:01:10.09#ibcon#end of sib2, iclass 37, count 0 2006.257.20:01:10.09#ibcon#*after write, iclass 37, count 0 2006.257.20:01:10.09#ibcon#*before return 0, iclass 37, count 0 2006.257.20:01:10.09#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:10.09#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:01:10.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:01:10.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:01:10.09$vck44/vblo=4,679.99 2006.257.20:01:10.09#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.20:01:10.09#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.20:01:10.09#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:10.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:10.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:10.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:10.09#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:01:10.09#ibcon#first serial, iclass 39, count 0 2006.257.20:01:10.09#ibcon#enter sib2, iclass 39, count 0 2006.257.20:01:10.09#ibcon#flushed, iclass 39, count 0 2006.257.20:01:10.09#ibcon#about to write, iclass 39, count 0 2006.257.20:01:10.09#ibcon#wrote, iclass 39, count 0 2006.257.20:01:10.09#ibcon#about to read 3, iclass 39, count 0 2006.257.20:01:10.11#ibcon#read 3, iclass 39, count 0 2006.257.20:01:10.11#ibcon#about to read 4, iclass 39, count 0 2006.257.20:01:10.11#ibcon#read 4, iclass 39, count 0 2006.257.20:01:10.11#ibcon#about to read 5, iclass 39, count 0 2006.257.20:01:10.11#ibcon#read 5, iclass 39, count 0 2006.257.20:01:10.11#ibcon#about to read 6, iclass 39, count 0 2006.257.20:01:10.11#ibcon#read 6, iclass 39, count 0 2006.257.20:01:10.11#ibcon#end of sib2, iclass 39, count 0 2006.257.20:01:10.11#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:01:10.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:01:10.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.20:01:10.11#ibcon#*before write, iclass 39, count 0 2006.257.20:01:10.11#ibcon#enter sib2, iclass 39, count 0 2006.257.20:01:10.11#ibcon#flushed, iclass 39, count 0 2006.257.20:01:10.11#ibcon#about to write, iclass 39, count 0 2006.257.20:01:10.11#ibcon#wrote, iclass 39, count 0 2006.257.20:01:10.11#ibcon#about to read 3, iclass 39, count 0 2006.257.20:01:10.15#ibcon#read 3, iclass 39, count 0 2006.257.20:01:10.15#ibcon#about to read 4, iclass 39, count 0 2006.257.20:01:10.15#ibcon#read 4, iclass 39, count 0 2006.257.20:01:10.15#ibcon#about to read 5, iclass 39, count 0 2006.257.20:01:10.15#ibcon#read 5, iclass 39, count 0 2006.257.20:01:10.15#ibcon#about to read 6, iclass 39, count 0 2006.257.20:01:10.15#ibcon#read 6, iclass 39, count 0 2006.257.20:01:10.15#ibcon#end of sib2, iclass 39, count 0 2006.257.20:01:10.15#ibcon#*after write, iclass 39, count 0 2006.257.20:01:10.15#ibcon#*before return 0, iclass 39, count 0 2006.257.20:01:10.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:10.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:01:10.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:01:10.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:01:10.15$vck44/vb=4,5 2006.257.20:01:10.15#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.20:01:10.15#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.20:01:10.15#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:10.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:10.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:10.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:10.21#ibcon#enter wrdev, iclass 3, count 2 2006.257.20:01:10.21#ibcon#first serial, iclass 3, count 2 2006.257.20:01:10.21#ibcon#enter sib2, iclass 3, count 2 2006.257.20:01:10.21#ibcon#flushed, iclass 3, count 2 2006.257.20:01:10.21#ibcon#about to write, iclass 3, count 2 2006.257.20:01:10.21#ibcon#wrote, iclass 3, count 2 2006.257.20:01:10.21#ibcon#about to read 3, iclass 3, count 2 2006.257.20:01:10.23#ibcon#read 3, iclass 3, count 2 2006.257.20:01:10.23#ibcon#about to read 4, iclass 3, count 2 2006.257.20:01:10.23#ibcon#read 4, iclass 3, count 2 2006.257.20:01:10.23#ibcon#about to read 5, iclass 3, count 2 2006.257.20:01:10.23#ibcon#read 5, iclass 3, count 2 2006.257.20:01:10.23#ibcon#about to read 6, iclass 3, count 2 2006.257.20:01:10.23#ibcon#read 6, iclass 3, count 2 2006.257.20:01:10.23#ibcon#end of sib2, iclass 3, count 2 2006.257.20:01:10.23#ibcon#*mode == 0, iclass 3, count 2 2006.257.20:01:10.23#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.20:01:10.23#ibcon#[27=AT04-05\r\n] 2006.257.20:01:10.23#ibcon#*before write, iclass 3, count 2 2006.257.20:01:10.23#ibcon#enter sib2, iclass 3, count 2 2006.257.20:01:10.23#ibcon#flushed, iclass 3, count 2 2006.257.20:01:10.23#ibcon#about to write, iclass 3, count 2 2006.257.20:01:10.23#ibcon#wrote, iclass 3, count 2 2006.257.20:01:10.23#ibcon#about to read 3, iclass 3, count 2 2006.257.20:01:10.26#ibcon#read 3, iclass 3, count 2 2006.257.20:01:10.26#ibcon#about to read 4, iclass 3, count 2 2006.257.20:01:10.26#ibcon#read 4, iclass 3, count 2 2006.257.20:01:10.26#ibcon#about to read 5, iclass 3, count 2 2006.257.20:01:10.26#ibcon#read 5, iclass 3, count 2 2006.257.20:01:10.26#ibcon#about to read 6, iclass 3, count 2 2006.257.20:01:10.26#ibcon#read 6, iclass 3, count 2 2006.257.20:01:10.26#ibcon#end of sib2, iclass 3, count 2 2006.257.20:01:10.26#ibcon#*after write, iclass 3, count 2 2006.257.20:01:10.26#ibcon#*before return 0, iclass 3, count 2 2006.257.20:01:10.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:10.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:01:10.26#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.20:01:10.26#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:10.26#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:10.38#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:10.38#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:10.38#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:01:10.38#ibcon#first serial, iclass 3, count 0 2006.257.20:01:10.38#ibcon#enter sib2, iclass 3, count 0 2006.257.20:01:10.38#ibcon#flushed, iclass 3, count 0 2006.257.20:01:10.38#ibcon#about to write, iclass 3, count 0 2006.257.20:01:10.38#ibcon#wrote, iclass 3, count 0 2006.257.20:01:10.38#ibcon#about to read 3, iclass 3, count 0 2006.257.20:01:10.40#ibcon#read 3, iclass 3, count 0 2006.257.20:01:10.40#ibcon#about to read 4, iclass 3, count 0 2006.257.20:01:10.40#ibcon#read 4, iclass 3, count 0 2006.257.20:01:10.40#ibcon#about to read 5, iclass 3, count 0 2006.257.20:01:10.40#ibcon#read 5, iclass 3, count 0 2006.257.20:01:10.40#ibcon#about to read 6, iclass 3, count 0 2006.257.20:01:10.40#ibcon#read 6, iclass 3, count 0 2006.257.20:01:10.40#ibcon#end of sib2, iclass 3, count 0 2006.257.20:01:10.40#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:01:10.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:01:10.40#ibcon#[27=USB\r\n] 2006.257.20:01:10.40#ibcon#*before write, iclass 3, count 0 2006.257.20:01:10.40#ibcon#enter sib2, iclass 3, count 0 2006.257.20:01:10.40#ibcon#flushed, iclass 3, count 0 2006.257.20:01:10.40#ibcon#about to write, iclass 3, count 0 2006.257.20:01:10.40#ibcon#wrote, iclass 3, count 0 2006.257.20:01:10.40#ibcon#about to read 3, iclass 3, count 0 2006.257.20:01:10.43#ibcon#read 3, iclass 3, count 0 2006.257.20:01:10.43#ibcon#about to read 4, iclass 3, count 0 2006.257.20:01:10.43#ibcon#read 4, iclass 3, count 0 2006.257.20:01:10.43#ibcon#about to read 5, iclass 3, count 0 2006.257.20:01:10.43#ibcon#read 5, iclass 3, count 0 2006.257.20:01:10.43#ibcon#about to read 6, iclass 3, count 0 2006.257.20:01:10.43#ibcon#read 6, iclass 3, count 0 2006.257.20:01:10.43#ibcon#end of sib2, iclass 3, count 0 2006.257.20:01:10.43#ibcon#*after write, iclass 3, count 0 2006.257.20:01:10.43#ibcon#*before return 0, iclass 3, count 0 2006.257.20:01:10.43#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:10.43#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:01:10.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:01:10.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:01:10.43$vck44/vblo=5,709.99 2006.257.20:01:10.43#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.20:01:10.43#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.20:01:10.43#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:10.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:10.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:10.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:10.43#ibcon#enter wrdev, iclass 5, count 0 2006.257.20:01:10.43#ibcon#first serial, iclass 5, count 0 2006.257.20:01:10.43#ibcon#enter sib2, iclass 5, count 0 2006.257.20:01:10.43#ibcon#flushed, iclass 5, count 0 2006.257.20:01:10.43#ibcon#about to write, iclass 5, count 0 2006.257.20:01:10.43#ibcon#wrote, iclass 5, count 0 2006.257.20:01:10.43#ibcon#about to read 3, iclass 5, count 0 2006.257.20:01:10.45#ibcon#read 3, iclass 5, count 0 2006.257.20:01:10.45#ibcon#about to read 4, iclass 5, count 0 2006.257.20:01:10.45#ibcon#read 4, iclass 5, count 0 2006.257.20:01:10.45#ibcon#about to read 5, iclass 5, count 0 2006.257.20:01:10.45#ibcon#read 5, iclass 5, count 0 2006.257.20:01:10.45#ibcon#about to read 6, iclass 5, count 0 2006.257.20:01:10.45#ibcon#read 6, iclass 5, count 0 2006.257.20:01:10.45#ibcon#end of sib2, iclass 5, count 0 2006.257.20:01:10.45#ibcon#*mode == 0, iclass 5, count 0 2006.257.20:01:10.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.20:01:10.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.20:01:10.45#ibcon#*before write, iclass 5, count 0 2006.257.20:01:10.45#ibcon#enter sib2, iclass 5, count 0 2006.257.20:01:10.45#ibcon#flushed, iclass 5, count 0 2006.257.20:01:10.45#ibcon#about to write, iclass 5, count 0 2006.257.20:01:10.45#ibcon#wrote, iclass 5, count 0 2006.257.20:01:10.45#ibcon#about to read 3, iclass 5, count 0 2006.257.20:01:10.49#ibcon#read 3, iclass 5, count 0 2006.257.20:01:10.49#ibcon#about to read 4, iclass 5, count 0 2006.257.20:01:10.49#ibcon#read 4, iclass 5, count 0 2006.257.20:01:10.49#ibcon#about to read 5, iclass 5, count 0 2006.257.20:01:10.49#ibcon#read 5, iclass 5, count 0 2006.257.20:01:10.49#ibcon#about to read 6, iclass 5, count 0 2006.257.20:01:10.49#ibcon#read 6, iclass 5, count 0 2006.257.20:01:10.49#ibcon#end of sib2, iclass 5, count 0 2006.257.20:01:10.49#ibcon#*after write, iclass 5, count 0 2006.257.20:01:10.49#ibcon#*before return 0, iclass 5, count 0 2006.257.20:01:10.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:10.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:01:10.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.20:01:10.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.20:01:10.49$vck44/vb=5,4 2006.257.20:01:10.49#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.20:01:10.49#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.20:01:10.49#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:10.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:10.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:10.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:10.55#ibcon#enter wrdev, iclass 7, count 2 2006.257.20:01:10.55#ibcon#first serial, iclass 7, count 2 2006.257.20:01:10.55#ibcon#enter sib2, iclass 7, count 2 2006.257.20:01:10.55#ibcon#flushed, iclass 7, count 2 2006.257.20:01:10.55#ibcon#about to write, iclass 7, count 2 2006.257.20:01:10.55#ibcon#wrote, iclass 7, count 2 2006.257.20:01:10.55#ibcon#about to read 3, iclass 7, count 2 2006.257.20:01:10.57#ibcon#read 3, iclass 7, count 2 2006.257.20:01:10.57#ibcon#about to read 4, iclass 7, count 2 2006.257.20:01:10.57#ibcon#read 4, iclass 7, count 2 2006.257.20:01:10.57#ibcon#about to read 5, iclass 7, count 2 2006.257.20:01:10.57#ibcon#read 5, iclass 7, count 2 2006.257.20:01:10.57#ibcon#about to read 6, iclass 7, count 2 2006.257.20:01:10.57#ibcon#read 6, iclass 7, count 2 2006.257.20:01:10.57#ibcon#end of sib2, iclass 7, count 2 2006.257.20:01:10.57#ibcon#*mode == 0, iclass 7, count 2 2006.257.20:01:10.57#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.20:01:10.57#ibcon#[27=AT05-04\r\n] 2006.257.20:01:10.57#ibcon#*before write, iclass 7, count 2 2006.257.20:01:10.57#ibcon#enter sib2, iclass 7, count 2 2006.257.20:01:10.57#ibcon#flushed, iclass 7, count 2 2006.257.20:01:10.57#ibcon#about to write, iclass 7, count 2 2006.257.20:01:10.57#ibcon#wrote, iclass 7, count 2 2006.257.20:01:10.57#ibcon#about to read 3, iclass 7, count 2 2006.257.20:01:10.60#ibcon#read 3, iclass 7, count 2 2006.257.20:01:10.60#ibcon#about to read 4, iclass 7, count 2 2006.257.20:01:10.60#ibcon#read 4, iclass 7, count 2 2006.257.20:01:10.60#ibcon#about to read 5, iclass 7, count 2 2006.257.20:01:10.60#ibcon#read 5, iclass 7, count 2 2006.257.20:01:10.60#ibcon#about to read 6, iclass 7, count 2 2006.257.20:01:10.60#ibcon#read 6, iclass 7, count 2 2006.257.20:01:10.60#ibcon#end of sib2, iclass 7, count 2 2006.257.20:01:10.60#ibcon#*after write, iclass 7, count 2 2006.257.20:01:10.60#ibcon#*before return 0, iclass 7, count 2 2006.257.20:01:10.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:10.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:01:10.60#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.20:01:10.60#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:10.60#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:10.72#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:10.72#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:10.72#ibcon#enter wrdev, iclass 7, count 0 2006.257.20:01:10.72#ibcon#first serial, iclass 7, count 0 2006.257.20:01:10.72#ibcon#enter sib2, iclass 7, count 0 2006.257.20:01:10.72#ibcon#flushed, iclass 7, count 0 2006.257.20:01:10.72#ibcon#about to write, iclass 7, count 0 2006.257.20:01:10.72#ibcon#wrote, iclass 7, count 0 2006.257.20:01:10.72#ibcon#about to read 3, iclass 7, count 0 2006.257.20:01:10.74#ibcon#read 3, iclass 7, count 0 2006.257.20:01:10.74#ibcon#about to read 4, iclass 7, count 0 2006.257.20:01:10.74#ibcon#read 4, iclass 7, count 0 2006.257.20:01:10.74#ibcon#about to read 5, iclass 7, count 0 2006.257.20:01:10.74#ibcon#read 5, iclass 7, count 0 2006.257.20:01:10.74#ibcon#about to read 6, iclass 7, count 0 2006.257.20:01:10.74#ibcon#read 6, iclass 7, count 0 2006.257.20:01:10.74#ibcon#end of sib2, iclass 7, count 0 2006.257.20:01:10.74#ibcon#*mode == 0, iclass 7, count 0 2006.257.20:01:10.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.20:01:10.74#ibcon#[27=USB\r\n] 2006.257.20:01:10.74#ibcon#*before write, iclass 7, count 0 2006.257.20:01:10.74#ibcon#enter sib2, iclass 7, count 0 2006.257.20:01:10.74#ibcon#flushed, iclass 7, count 0 2006.257.20:01:10.74#ibcon#about to write, iclass 7, count 0 2006.257.20:01:10.74#ibcon#wrote, iclass 7, count 0 2006.257.20:01:10.74#ibcon#about to read 3, iclass 7, count 0 2006.257.20:01:10.77#ibcon#read 3, iclass 7, count 0 2006.257.20:01:10.77#ibcon#about to read 4, iclass 7, count 0 2006.257.20:01:10.77#ibcon#read 4, iclass 7, count 0 2006.257.20:01:10.77#ibcon#about to read 5, iclass 7, count 0 2006.257.20:01:10.77#ibcon#read 5, iclass 7, count 0 2006.257.20:01:10.77#ibcon#about to read 6, iclass 7, count 0 2006.257.20:01:10.77#ibcon#read 6, iclass 7, count 0 2006.257.20:01:10.77#ibcon#end of sib2, iclass 7, count 0 2006.257.20:01:10.77#ibcon#*after write, iclass 7, count 0 2006.257.20:01:10.77#ibcon#*before return 0, iclass 7, count 0 2006.257.20:01:10.77#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:10.77#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:01:10.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.20:01:10.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.20:01:10.77$vck44/vblo=6,719.99 2006.257.20:01:10.77#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.20:01:10.77#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.20:01:10.77#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:10.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:10.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:10.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:10.77#ibcon#enter wrdev, iclass 11, count 0 2006.257.20:01:10.77#ibcon#first serial, iclass 11, count 0 2006.257.20:01:10.77#ibcon#enter sib2, iclass 11, count 0 2006.257.20:01:10.77#ibcon#flushed, iclass 11, count 0 2006.257.20:01:10.77#ibcon#about to write, iclass 11, count 0 2006.257.20:01:10.77#ibcon#wrote, iclass 11, count 0 2006.257.20:01:10.77#ibcon#about to read 3, iclass 11, count 0 2006.257.20:01:10.79#ibcon#read 3, iclass 11, count 0 2006.257.20:01:10.79#ibcon#about to read 4, iclass 11, count 0 2006.257.20:01:10.79#ibcon#read 4, iclass 11, count 0 2006.257.20:01:10.79#ibcon#about to read 5, iclass 11, count 0 2006.257.20:01:10.79#ibcon#read 5, iclass 11, count 0 2006.257.20:01:10.79#ibcon#about to read 6, iclass 11, count 0 2006.257.20:01:10.79#ibcon#read 6, iclass 11, count 0 2006.257.20:01:10.79#ibcon#end of sib2, iclass 11, count 0 2006.257.20:01:10.79#ibcon#*mode == 0, iclass 11, count 0 2006.257.20:01:10.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.20:01:10.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.20:01:10.79#ibcon#*before write, iclass 11, count 0 2006.257.20:01:10.79#ibcon#enter sib2, iclass 11, count 0 2006.257.20:01:10.79#ibcon#flushed, iclass 11, count 0 2006.257.20:01:10.79#ibcon#about to write, iclass 11, count 0 2006.257.20:01:10.79#ibcon#wrote, iclass 11, count 0 2006.257.20:01:10.79#ibcon#about to read 3, iclass 11, count 0 2006.257.20:01:10.83#ibcon#read 3, iclass 11, count 0 2006.257.20:01:10.83#ibcon#about to read 4, iclass 11, count 0 2006.257.20:01:10.83#ibcon#read 4, iclass 11, count 0 2006.257.20:01:10.83#ibcon#about to read 5, iclass 11, count 0 2006.257.20:01:10.83#ibcon#read 5, iclass 11, count 0 2006.257.20:01:10.83#ibcon#about to read 6, iclass 11, count 0 2006.257.20:01:10.83#ibcon#read 6, iclass 11, count 0 2006.257.20:01:10.83#ibcon#end of sib2, iclass 11, count 0 2006.257.20:01:10.83#ibcon#*after write, iclass 11, count 0 2006.257.20:01:10.83#ibcon#*before return 0, iclass 11, count 0 2006.257.20:01:10.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:10.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:01:10.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.20:01:10.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.20:01:10.83$vck44/vb=6,4 2006.257.20:01:10.83#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.20:01:10.83#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.20:01:10.83#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:10.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:10.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:10.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:10.89#ibcon#enter wrdev, iclass 13, count 2 2006.257.20:01:10.89#ibcon#first serial, iclass 13, count 2 2006.257.20:01:10.89#ibcon#enter sib2, iclass 13, count 2 2006.257.20:01:10.89#ibcon#flushed, iclass 13, count 2 2006.257.20:01:10.89#ibcon#about to write, iclass 13, count 2 2006.257.20:01:10.89#ibcon#wrote, iclass 13, count 2 2006.257.20:01:10.89#ibcon#about to read 3, iclass 13, count 2 2006.257.20:01:10.91#ibcon#read 3, iclass 13, count 2 2006.257.20:01:10.91#ibcon#about to read 4, iclass 13, count 2 2006.257.20:01:10.91#ibcon#read 4, iclass 13, count 2 2006.257.20:01:10.91#ibcon#about to read 5, iclass 13, count 2 2006.257.20:01:10.91#ibcon#read 5, iclass 13, count 2 2006.257.20:01:10.91#ibcon#about to read 6, iclass 13, count 2 2006.257.20:01:10.91#ibcon#read 6, iclass 13, count 2 2006.257.20:01:10.91#ibcon#end of sib2, iclass 13, count 2 2006.257.20:01:10.91#ibcon#*mode == 0, iclass 13, count 2 2006.257.20:01:10.91#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.20:01:10.91#ibcon#[27=AT06-04\r\n] 2006.257.20:01:10.91#ibcon#*before write, iclass 13, count 2 2006.257.20:01:10.91#ibcon#enter sib2, iclass 13, count 2 2006.257.20:01:10.91#ibcon#flushed, iclass 13, count 2 2006.257.20:01:10.91#ibcon#about to write, iclass 13, count 2 2006.257.20:01:10.91#ibcon#wrote, iclass 13, count 2 2006.257.20:01:10.91#ibcon#about to read 3, iclass 13, count 2 2006.257.20:01:10.94#ibcon#read 3, iclass 13, count 2 2006.257.20:01:10.94#ibcon#about to read 4, iclass 13, count 2 2006.257.20:01:10.94#ibcon#read 4, iclass 13, count 2 2006.257.20:01:10.94#ibcon#about to read 5, iclass 13, count 2 2006.257.20:01:10.94#ibcon#read 5, iclass 13, count 2 2006.257.20:01:10.94#ibcon#about to read 6, iclass 13, count 2 2006.257.20:01:10.94#ibcon#read 6, iclass 13, count 2 2006.257.20:01:10.94#ibcon#end of sib2, iclass 13, count 2 2006.257.20:01:10.94#ibcon#*after write, iclass 13, count 2 2006.257.20:01:10.94#ibcon#*before return 0, iclass 13, count 2 2006.257.20:01:10.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:10.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:01:10.94#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.20:01:10.94#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:10.94#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:11.06#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:11.06#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:11.06#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:01:11.06#ibcon#first serial, iclass 13, count 0 2006.257.20:01:11.06#ibcon#enter sib2, iclass 13, count 0 2006.257.20:01:11.06#ibcon#flushed, iclass 13, count 0 2006.257.20:01:11.06#ibcon#about to write, iclass 13, count 0 2006.257.20:01:11.06#ibcon#wrote, iclass 13, count 0 2006.257.20:01:11.06#ibcon#about to read 3, iclass 13, count 0 2006.257.20:01:11.08#ibcon#read 3, iclass 13, count 0 2006.257.20:01:11.08#ibcon#about to read 4, iclass 13, count 0 2006.257.20:01:11.08#ibcon#read 4, iclass 13, count 0 2006.257.20:01:11.08#ibcon#about to read 5, iclass 13, count 0 2006.257.20:01:11.08#ibcon#read 5, iclass 13, count 0 2006.257.20:01:11.08#ibcon#about to read 6, iclass 13, count 0 2006.257.20:01:11.08#ibcon#read 6, iclass 13, count 0 2006.257.20:01:11.08#ibcon#end of sib2, iclass 13, count 0 2006.257.20:01:11.08#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:01:11.08#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:01:11.08#ibcon#[27=USB\r\n] 2006.257.20:01:11.08#ibcon#*before write, iclass 13, count 0 2006.257.20:01:11.08#ibcon#enter sib2, iclass 13, count 0 2006.257.20:01:11.08#ibcon#flushed, iclass 13, count 0 2006.257.20:01:11.08#ibcon#about to write, iclass 13, count 0 2006.257.20:01:11.08#ibcon#wrote, iclass 13, count 0 2006.257.20:01:11.08#ibcon#about to read 3, iclass 13, count 0 2006.257.20:01:11.11#ibcon#read 3, iclass 13, count 0 2006.257.20:01:11.11#ibcon#about to read 4, iclass 13, count 0 2006.257.20:01:11.11#ibcon#read 4, iclass 13, count 0 2006.257.20:01:11.11#ibcon#about to read 5, iclass 13, count 0 2006.257.20:01:11.11#ibcon#read 5, iclass 13, count 0 2006.257.20:01:11.11#ibcon#about to read 6, iclass 13, count 0 2006.257.20:01:11.11#ibcon#read 6, iclass 13, count 0 2006.257.20:01:11.11#ibcon#end of sib2, iclass 13, count 0 2006.257.20:01:11.11#ibcon#*after write, iclass 13, count 0 2006.257.20:01:11.11#ibcon#*before return 0, iclass 13, count 0 2006.257.20:01:11.11#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:11.11#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:01:11.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:01:11.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:01:11.11$vck44/vblo=7,734.99 2006.257.20:01:11.11#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.20:01:11.11#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.20:01:11.11#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:11.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:11.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:11.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:11.11#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:01:11.11#ibcon#first serial, iclass 15, count 0 2006.257.20:01:11.11#ibcon#enter sib2, iclass 15, count 0 2006.257.20:01:11.11#ibcon#flushed, iclass 15, count 0 2006.257.20:01:11.11#ibcon#about to write, iclass 15, count 0 2006.257.20:01:11.11#ibcon#wrote, iclass 15, count 0 2006.257.20:01:11.11#ibcon#about to read 3, iclass 15, count 0 2006.257.20:01:11.13#ibcon#read 3, iclass 15, count 0 2006.257.20:01:11.13#ibcon#about to read 4, iclass 15, count 0 2006.257.20:01:11.13#ibcon#read 4, iclass 15, count 0 2006.257.20:01:11.13#ibcon#about to read 5, iclass 15, count 0 2006.257.20:01:11.13#ibcon#read 5, iclass 15, count 0 2006.257.20:01:11.13#ibcon#about to read 6, iclass 15, count 0 2006.257.20:01:11.13#ibcon#read 6, iclass 15, count 0 2006.257.20:01:11.13#ibcon#end of sib2, iclass 15, count 0 2006.257.20:01:11.13#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:01:11.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:01:11.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.20:01:11.13#ibcon#*before write, iclass 15, count 0 2006.257.20:01:11.13#ibcon#enter sib2, iclass 15, count 0 2006.257.20:01:11.13#ibcon#flushed, iclass 15, count 0 2006.257.20:01:11.13#ibcon#about to write, iclass 15, count 0 2006.257.20:01:11.13#ibcon#wrote, iclass 15, count 0 2006.257.20:01:11.13#ibcon#about to read 3, iclass 15, count 0 2006.257.20:01:11.17#ibcon#read 3, iclass 15, count 0 2006.257.20:01:11.17#ibcon#about to read 4, iclass 15, count 0 2006.257.20:01:11.17#ibcon#read 4, iclass 15, count 0 2006.257.20:01:11.17#ibcon#about to read 5, iclass 15, count 0 2006.257.20:01:11.17#ibcon#read 5, iclass 15, count 0 2006.257.20:01:11.17#ibcon#about to read 6, iclass 15, count 0 2006.257.20:01:11.17#ibcon#read 6, iclass 15, count 0 2006.257.20:01:11.17#ibcon#end of sib2, iclass 15, count 0 2006.257.20:01:11.17#ibcon#*after write, iclass 15, count 0 2006.257.20:01:11.17#ibcon#*before return 0, iclass 15, count 0 2006.257.20:01:11.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:11.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:01:11.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:01:11.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:01:11.17$vck44/vb=7,4 2006.257.20:01:11.17#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.20:01:11.17#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.20:01:11.17#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:11.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:11.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:11.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:11.23#ibcon#enter wrdev, iclass 17, count 2 2006.257.20:01:11.23#ibcon#first serial, iclass 17, count 2 2006.257.20:01:11.23#ibcon#enter sib2, iclass 17, count 2 2006.257.20:01:11.23#ibcon#flushed, iclass 17, count 2 2006.257.20:01:11.23#ibcon#about to write, iclass 17, count 2 2006.257.20:01:11.23#ibcon#wrote, iclass 17, count 2 2006.257.20:01:11.23#ibcon#about to read 3, iclass 17, count 2 2006.257.20:01:11.25#ibcon#read 3, iclass 17, count 2 2006.257.20:01:11.25#ibcon#about to read 4, iclass 17, count 2 2006.257.20:01:11.25#ibcon#read 4, iclass 17, count 2 2006.257.20:01:11.25#ibcon#about to read 5, iclass 17, count 2 2006.257.20:01:11.25#ibcon#read 5, iclass 17, count 2 2006.257.20:01:11.25#ibcon#about to read 6, iclass 17, count 2 2006.257.20:01:11.25#ibcon#read 6, iclass 17, count 2 2006.257.20:01:11.25#ibcon#end of sib2, iclass 17, count 2 2006.257.20:01:11.25#ibcon#*mode == 0, iclass 17, count 2 2006.257.20:01:11.25#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.20:01:11.25#ibcon#[27=AT07-04\r\n] 2006.257.20:01:11.25#ibcon#*before write, iclass 17, count 2 2006.257.20:01:11.25#ibcon#enter sib2, iclass 17, count 2 2006.257.20:01:11.25#ibcon#flushed, iclass 17, count 2 2006.257.20:01:11.25#ibcon#about to write, iclass 17, count 2 2006.257.20:01:11.25#ibcon#wrote, iclass 17, count 2 2006.257.20:01:11.25#ibcon#about to read 3, iclass 17, count 2 2006.257.20:01:11.28#ibcon#read 3, iclass 17, count 2 2006.257.20:01:11.28#ibcon#about to read 4, iclass 17, count 2 2006.257.20:01:11.28#ibcon#read 4, iclass 17, count 2 2006.257.20:01:11.28#ibcon#about to read 5, iclass 17, count 2 2006.257.20:01:11.28#ibcon#read 5, iclass 17, count 2 2006.257.20:01:11.28#ibcon#about to read 6, iclass 17, count 2 2006.257.20:01:11.28#ibcon#read 6, iclass 17, count 2 2006.257.20:01:11.28#ibcon#end of sib2, iclass 17, count 2 2006.257.20:01:11.28#ibcon#*after write, iclass 17, count 2 2006.257.20:01:11.28#ibcon#*before return 0, iclass 17, count 2 2006.257.20:01:11.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:11.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:01:11.28#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.20:01:11.28#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:11.28#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:11.40#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:11.40#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:11.40#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:01:11.40#ibcon#first serial, iclass 17, count 0 2006.257.20:01:11.40#ibcon#enter sib2, iclass 17, count 0 2006.257.20:01:11.40#ibcon#flushed, iclass 17, count 0 2006.257.20:01:11.40#ibcon#about to write, iclass 17, count 0 2006.257.20:01:11.40#ibcon#wrote, iclass 17, count 0 2006.257.20:01:11.40#ibcon#about to read 3, iclass 17, count 0 2006.257.20:01:11.42#ibcon#read 3, iclass 17, count 0 2006.257.20:01:11.42#ibcon#about to read 4, iclass 17, count 0 2006.257.20:01:11.42#ibcon#read 4, iclass 17, count 0 2006.257.20:01:11.42#ibcon#about to read 5, iclass 17, count 0 2006.257.20:01:11.42#ibcon#read 5, iclass 17, count 0 2006.257.20:01:11.42#ibcon#about to read 6, iclass 17, count 0 2006.257.20:01:11.42#ibcon#read 6, iclass 17, count 0 2006.257.20:01:11.42#ibcon#end of sib2, iclass 17, count 0 2006.257.20:01:11.42#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:01:11.42#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:01:11.42#ibcon#[27=USB\r\n] 2006.257.20:01:11.42#ibcon#*before write, iclass 17, count 0 2006.257.20:01:11.42#ibcon#enter sib2, iclass 17, count 0 2006.257.20:01:11.42#ibcon#flushed, iclass 17, count 0 2006.257.20:01:11.42#ibcon#about to write, iclass 17, count 0 2006.257.20:01:11.42#ibcon#wrote, iclass 17, count 0 2006.257.20:01:11.42#ibcon#about to read 3, iclass 17, count 0 2006.257.20:01:11.45#ibcon#read 3, iclass 17, count 0 2006.257.20:01:11.45#ibcon#about to read 4, iclass 17, count 0 2006.257.20:01:11.45#ibcon#read 4, iclass 17, count 0 2006.257.20:01:11.45#ibcon#about to read 5, iclass 17, count 0 2006.257.20:01:11.45#ibcon#read 5, iclass 17, count 0 2006.257.20:01:11.45#ibcon#about to read 6, iclass 17, count 0 2006.257.20:01:11.45#ibcon#read 6, iclass 17, count 0 2006.257.20:01:11.45#ibcon#end of sib2, iclass 17, count 0 2006.257.20:01:11.45#ibcon#*after write, iclass 17, count 0 2006.257.20:01:11.45#ibcon#*before return 0, iclass 17, count 0 2006.257.20:01:11.45#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:11.45#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:01:11.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:01:11.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:01:11.45$vck44/vblo=8,744.99 2006.257.20:01:11.45#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.20:01:11.45#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.20:01:11.45#ibcon#ireg 17 cls_cnt 0 2006.257.20:01:11.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:11.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:11.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:11.45#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:01:11.45#ibcon#first serial, iclass 19, count 0 2006.257.20:01:11.45#ibcon#enter sib2, iclass 19, count 0 2006.257.20:01:11.45#ibcon#flushed, iclass 19, count 0 2006.257.20:01:11.45#ibcon#about to write, iclass 19, count 0 2006.257.20:01:11.45#ibcon#wrote, iclass 19, count 0 2006.257.20:01:11.45#ibcon#about to read 3, iclass 19, count 0 2006.257.20:01:11.47#ibcon#read 3, iclass 19, count 0 2006.257.20:01:11.47#ibcon#about to read 4, iclass 19, count 0 2006.257.20:01:11.47#ibcon#read 4, iclass 19, count 0 2006.257.20:01:11.47#ibcon#about to read 5, iclass 19, count 0 2006.257.20:01:11.47#ibcon#read 5, iclass 19, count 0 2006.257.20:01:11.47#ibcon#about to read 6, iclass 19, count 0 2006.257.20:01:11.47#ibcon#read 6, iclass 19, count 0 2006.257.20:01:11.47#ibcon#end of sib2, iclass 19, count 0 2006.257.20:01:11.47#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:01:11.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:01:11.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.20:01:11.47#ibcon#*before write, iclass 19, count 0 2006.257.20:01:11.47#ibcon#enter sib2, iclass 19, count 0 2006.257.20:01:11.47#ibcon#flushed, iclass 19, count 0 2006.257.20:01:11.47#ibcon#about to write, iclass 19, count 0 2006.257.20:01:11.47#ibcon#wrote, iclass 19, count 0 2006.257.20:01:11.47#ibcon#about to read 3, iclass 19, count 0 2006.257.20:01:11.51#ibcon#read 3, iclass 19, count 0 2006.257.20:01:11.51#ibcon#about to read 4, iclass 19, count 0 2006.257.20:01:11.51#ibcon#read 4, iclass 19, count 0 2006.257.20:01:11.51#ibcon#about to read 5, iclass 19, count 0 2006.257.20:01:11.51#ibcon#read 5, iclass 19, count 0 2006.257.20:01:11.51#ibcon#about to read 6, iclass 19, count 0 2006.257.20:01:11.51#ibcon#read 6, iclass 19, count 0 2006.257.20:01:11.51#ibcon#end of sib2, iclass 19, count 0 2006.257.20:01:11.51#ibcon#*after write, iclass 19, count 0 2006.257.20:01:11.51#ibcon#*before return 0, iclass 19, count 0 2006.257.20:01:11.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:11.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:01:11.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:01:11.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:01:11.51$vck44/vb=8,4 2006.257.20:01:11.51#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.20:01:11.51#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.20:01:11.51#ibcon#ireg 11 cls_cnt 2 2006.257.20:01:11.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:11.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:11.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:11.57#ibcon#enter wrdev, iclass 21, count 2 2006.257.20:01:11.57#ibcon#first serial, iclass 21, count 2 2006.257.20:01:11.57#ibcon#enter sib2, iclass 21, count 2 2006.257.20:01:11.57#ibcon#flushed, iclass 21, count 2 2006.257.20:01:11.57#ibcon#about to write, iclass 21, count 2 2006.257.20:01:11.57#ibcon#wrote, iclass 21, count 2 2006.257.20:01:11.57#ibcon#about to read 3, iclass 21, count 2 2006.257.20:01:11.59#ibcon#read 3, iclass 21, count 2 2006.257.20:01:11.59#ibcon#about to read 4, iclass 21, count 2 2006.257.20:01:11.59#ibcon#read 4, iclass 21, count 2 2006.257.20:01:11.59#ibcon#about to read 5, iclass 21, count 2 2006.257.20:01:11.59#ibcon#read 5, iclass 21, count 2 2006.257.20:01:11.59#ibcon#about to read 6, iclass 21, count 2 2006.257.20:01:11.59#ibcon#read 6, iclass 21, count 2 2006.257.20:01:11.59#ibcon#end of sib2, iclass 21, count 2 2006.257.20:01:11.59#ibcon#*mode == 0, iclass 21, count 2 2006.257.20:01:11.59#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.20:01:11.59#ibcon#[27=AT08-04\r\n] 2006.257.20:01:11.59#ibcon#*before write, iclass 21, count 2 2006.257.20:01:11.59#ibcon#enter sib2, iclass 21, count 2 2006.257.20:01:11.59#ibcon#flushed, iclass 21, count 2 2006.257.20:01:11.59#ibcon#about to write, iclass 21, count 2 2006.257.20:01:11.59#ibcon#wrote, iclass 21, count 2 2006.257.20:01:11.59#ibcon#about to read 3, iclass 21, count 2 2006.257.20:01:11.62#ibcon#read 3, iclass 21, count 2 2006.257.20:01:11.62#ibcon#about to read 4, iclass 21, count 2 2006.257.20:01:11.62#ibcon#read 4, iclass 21, count 2 2006.257.20:01:11.62#ibcon#about to read 5, iclass 21, count 2 2006.257.20:01:11.62#ibcon#read 5, iclass 21, count 2 2006.257.20:01:11.62#ibcon#about to read 6, iclass 21, count 2 2006.257.20:01:11.62#ibcon#read 6, iclass 21, count 2 2006.257.20:01:11.62#ibcon#end of sib2, iclass 21, count 2 2006.257.20:01:11.62#ibcon#*after write, iclass 21, count 2 2006.257.20:01:11.62#ibcon#*before return 0, iclass 21, count 2 2006.257.20:01:11.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:11.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:01:11.62#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.20:01:11.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:01:11.62#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:11.74#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:11.74#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:11.74#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:01:11.74#ibcon#first serial, iclass 21, count 0 2006.257.20:01:11.74#ibcon#enter sib2, iclass 21, count 0 2006.257.20:01:11.74#ibcon#flushed, iclass 21, count 0 2006.257.20:01:11.74#ibcon#about to write, iclass 21, count 0 2006.257.20:01:11.74#ibcon#wrote, iclass 21, count 0 2006.257.20:01:11.74#ibcon#about to read 3, iclass 21, count 0 2006.257.20:01:11.76#ibcon#read 3, iclass 21, count 0 2006.257.20:01:11.76#ibcon#about to read 4, iclass 21, count 0 2006.257.20:01:11.76#ibcon#read 4, iclass 21, count 0 2006.257.20:01:11.76#ibcon#about to read 5, iclass 21, count 0 2006.257.20:01:11.76#ibcon#read 5, iclass 21, count 0 2006.257.20:01:11.76#ibcon#about to read 6, iclass 21, count 0 2006.257.20:01:11.76#ibcon#read 6, iclass 21, count 0 2006.257.20:01:11.76#ibcon#end of sib2, iclass 21, count 0 2006.257.20:01:11.76#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:01:11.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:01:11.76#ibcon#[27=USB\r\n] 2006.257.20:01:11.76#ibcon#*before write, iclass 21, count 0 2006.257.20:01:11.76#ibcon#enter sib2, iclass 21, count 0 2006.257.20:01:11.76#ibcon#flushed, iclass 21, count 0 2006.257.20:01:11.76#ibcon#about to write, iclass 21, count 0 2006.257.20:01:11.76#ibcon#wrote, iclass 21, count 0 2006.257.20:01:11.76#ibcon#about to read 3, iclass 21, count 0 2006.257.20:01:11.79#ibcon#read 3, iclass 21, count 0 2006.257.20:01:11.79#ibcon#about to read 4, iclass 21, count 0 2006.257.20:01:11.79#ibcon#read 4, iclass 21, count 0 2006.257.20:01:11.79#ibcon#about to read 5, iclass 21, count 0 2006.257.20:01:11.79#ibcon#read 5, iclass 21, count 0 2006.257.20:01:11.79#ibcon#about to read 6, iclass 21, count 0 2006.257.20:01:11.79#ibcon#read 6, iclass 21, count 0 2006.257.20:01:11.79#ibcon#end of sib2, iclass 21, count 0 2006.257.20:01:11.79#ibcon#*after write, iclass 21, count 0 2006.257.20:01:11.79#ibcon#*before return 0, iclass 21, count 0 2006.257.20:01:11.79#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:11.79#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:01:11.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:01:11.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:01:11.79$vck44/vabw=wide 2006.257.20:01:11.79#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.20:01:11.79#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.20:01:11.79#ibcon#ireg 8 cls_cnt 0 2006.257.20:01:11.79#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:11.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:11.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:11.79#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:01:11.79#ibcon#first serial, iclass 23, count 0 2006.257.20:01:11.79#ibcon#enter sib2, iclass 23, count 0 2006.257.20:01:11.79#ibcon#flushed, iclass 23, count 0 2006.257.20:01:11.79#ibcon#about to write, iclass 23, count 0 2006.257.20:01:11.79#ibcon#wrote, iclass 23, count 0 2006.257.20:01:11.79#ibcon#about to read 3, iclass 23, count 0 2006.257.20:01:11.81#ibcon#read 3, iclass 23, count 0 2006.257.20:01:11.81#ibcon#about to read 4, iclass 23, count 0 2006.257.20:01:11.81#ibcon#read 4, iclass 23, count 0 2006.257.20:01:11.81#ibcon#about to read 5, iclass 23, count 0 2006.257.20:01:11.81#ibcon#read 5, iclass 23, count 0 2006.257.20:01:11.81#ibcon#about to read 6, iclass 23, count 0 2006.257.20:01:11.81#ibcon#read 6, iclass 23, count 0 2006.257.20:01:11.81#ibcon#end of sib2, iclass 23, count 0 2006.257.20:01:11.81#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:01:11.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:01:11.81#ibcon#[25=BW32\r\n] 2006.257.20:01:11.81#ibcon#*before write, iclass 23, count 0 2006.257.20:01:11.81#ibcon#enter sib2, iclass 23, count 0 2006.257.20:01:11.81#ibcon#flushed, iclass 23, count 0 2006.257.20:01:11.81#ibcon#about to write, iclass 23, count 0 2006.257.20:01:11.81#ibcon#wrote, iclass 23, count 0 2006.257.20:01:11.81#ibcon#about to read 3, iclass 23, count 0 2006.257.20:01:11.84#ibcon#read 3, iclass 23, count 0 2006.257.20:01:11.84#ibcon#about to read 4, iclass 23, count 0 2006.257.20:01:11.84#ibcon#read 4, iclass 23, count 0 2006.257.20:01:11.84#ibcon#about to read 5, iclass 23, count 0 2006.257.20:01:11.84#ibcon#read 5, iclass 23, count 0 2006.257.20:01:11.84#ibcon#about to read 6, iclass 23, count 0 2006.257.20:01:11.84#ibcon#read 6, iclass 23, count 0 2006.257.20:01:11.84#ibcon#end of sib2, iclass 23, count 0 2006.257.20:01:11.84#ibcon#*after write, iclass 23, count 0 2006.257.20:01:11.84#ibcon#*before return 0, iclass 23, count 0 2006.257.20:01:11.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:11.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:01:11.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:01:11.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:01:11.84$vck44/vbbw=wide 2006.257.20:01:11.84#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.20:01:11.84#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.20:01:11.84#ibcon#ireg 8 cls_cnt 0 2006.257.20:01:11.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:01:11.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:01:11.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:01:11.91#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:01:11.91#ibcon#first serial, iclass 25, count 0 2006.257.20:01:11.91#ibcon#enter sib2, iclass 25, count 0 2006.257.20:01:11.91#ibcon#flushed, iclass 25, count 0 2006.257.20:01:11.91#ibcon#about to write, iclass 25, count 0 2006.257.20:01:11.91#ibcon#wrote, iclass 25, count 0 2006.257.20:01:11.91#ibcon#about to read 3, iclass 25, count 0 2006.257.20:01:11.93#ibcon#read 3, iclass 25, count 0 2006.257.20:01:11.93#ibcon#about to read 4, iclass 25, count 0 2006.257.20:01:11.93#ibcon#read 4, iclass 25, count 0 2006.257.20:01:11.93#ibcon#about to read 5, iclass 25, count 0 2006.257.20:01:11.93#ibcon#read 5, iclass 25, count 0 2006.257.20:01:11.93#ibcon#about to read 6, iclass 25, count 0 2006.257.20:01:11.93#ibcon#read 6, iclass 25, count 0 2006.257.20:01:11.93#ibcon#end of sib2, iclass 25, count 0 2006.257.20:01:11.93#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:01:11.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:01:11.93#ibcon#[27=BW32\r\n] 2006.257.20:01:11.93#ibcon#*before write, iclass 25, count 0 2006.257.20:01:11.93#ibcon#enter sib2, iclass 25, count 0 2006.257.20:01:11.93#ibcon#flushed, iclass 25, count 0 2006.257.20:01:11.93#ibcon#about to write, iclass 25, count 0 2006.257.20:01:11.93#ibcon#wrote, iclass 25, count 0 2006.257.20:01:11.93#ibcon#about to read 3, iclass 25, count 0 2006.257.20:01:11.96#ibcon#read 3, iclass 25, count 0 2006.257.20:01:11.96#ibcon#about to read 4, iclass 25, count 0 2006.257.20:01:11.96#ibcon#read 4, iclass 25, count 0 2006.257.20:01:11.96#ibcon#about to read 5, iclass 25, count 0 2006.257.20:01:11.96#ibcon#read 5, iclass 25, count 0 2006.257.20:01:11.96#ibcon#about to read 6, iclass 25, count 0 2006.257.20:01:11.96#ibcon#read 6, iclass 25, count 0 2006.257.20:01:11.96#ibcon#end of sib2, iclass 25, count 0 2006.257.20:01:11.96#ibcon#*after write, iclass 25, count 0 2006.257.20:01:11.96#ibcon#*before return 0, iclass 25, count 0 2006.257.20:01:11.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:01:11.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:01:11.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:01:11.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:01:11.96$setupk4/ifdk4 2006.257.20:01:11.96$ifdk4/lo= 2006.257.20:01:11.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.20:01:11.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.20:01:11.96$ifdk4/patch= 2006.257.20:01:11.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.20:01:11.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.20:01:11.96$setupk4/!*+20s 2006.257.20:01:16.77#abcon#<5=/14 1.0 2.8 17.46 961014.6\r\n> 2006.257.20:01:16.79#abcon#{5=INTERFACE CLEAR} 2006.257.20:01:16.85#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:01:26.47$setupk4/"tpicd 2006.257.20:01:26.47$setupk4/echo=off 2006.257.20:01:26.47$setupk4/xlog=off 2006.257.20:01:26.47:!2006.257.20:08:27 2006.257.20:01:46.13#trakl#Source acquired 2006.257.20:01:47.13#flagr#flagr/antenna,acquired 2006.257.20:08:27.00:preob 2006.257.20:08:27.14/onsource/TRACKING 2006.257.20:08:27.14:!2006.257.20:08:37 2006.257.20:08:37.00:"tape 2006.257.20:08:37.00:"st=record 2006.257.20:08:37.00:data_valid=on 2006.257.20:08:37.00:midob 2006.257.20:08:38.13/onsource/TRACKING 2006.257.20:08:38.13/wx/17.30,1014.7,97 2006.257.20:08:38.32/cable/+6.4848E-03 2006.257.20:08:39.41/va/01,08,usb,yes,31,34 2006.257.20:08:39.41/va/02,07,usb,yes,34,34 2006.257.20:08:39.41/va/03,08,usb,yes,30,32 2006.257.20:08:39.41/va/04,07,usb,yes,35,37 2006.257.20:08:39.41/va/05,04,usb,yes,31,32 2006.257.20:08:39.41/va/06,04,usb,yes,35,34 2006.257.20:08:39.41/va/07,04,usb,yes,36,36 2006.257.20:08:39.41/va/08,04,usb,yes,30,37 2006.257.20:08:39.64/valo/01,524.99,yes,locked 2006.257.20:08:39.64/valo/02,534.99,yes,locked 2006.257.20:08:39.64/valo/03,564.99,yes,locked 2006.257.20:08:39.64/valo/04,624.99,yes,locked 2006.257.20:08:39.64/valo/05,734.99,yes,locked 2006.257.20:08:39.64/valo/06,814.99,yes,locked 2006.257.20:08:39.64/valo/07,864.99,yes,locked 2006.257.20:08:39.64/valo/08,884.99,yes,locked 2006.257.20:08:40.73/vb/01,04,usb,yes,30,28 2006.257.20:08:40.73/vb/02,05,usb,yes,28,28 2006.257.20:08:40.73/vb/03,04,usb,yes,29,32 2006.257.20:08:40.73/vb/04,05,usb,yes,30,29 2006.257.20:08:40.73/vb/05,04,usb,yes,26,28 2006.257.20:08:40.73/vb/06,04,usb,yes,31,27 2006.257.20:08:40.73/vb/07,04,usb,yes,30,30 2006.257.20:08:40.73/vb/08,04,usb,yes,28,31 2006.257.20:08:40.96/vblo/01,629.99,yes,locked 2006.257.20:08:40.96/vblo/02,634.99,yes,locked 2006.257.20:08:40.96/vblo/03,649.99,yes,locked 2006.257.20:08:40.96/vblo/04,679.99,yes,locked 2006.257.20:08:40.96/vblo/05,709.99,yes,locked 2006.257.20:08:40.96/vblo/06,719.99,yes,locked 2006.257.20:08:40.96/vblo/07,734.99,yes,locked 2006.257.20:08:40.96/vblo/08,744.99,yes,locked 2006.257.20:08:41.11/vabw/8 2006.257.20:08:41.26/vbbw/8 2006.257.20:08:41.35/xfe/off,on,16.0 2006.257.20:08:41.73/ifatt/23,28,28,28 2006.257.20:08:42.07/fmout-gps/S +4.52E-07 2006.257.20:08:42.11:!2006.257.20:11:57 2006.257.20:11:57.00:data_valid=off 2006.257.20:11:57.00:"et 2006.257.20:11:57.01:!+3s 2006.257.20:12:00.03:"tape 2006.257.20:12:00.03:postob 2006.257.20:12:00.19/cable/+6.4840E-03 2006.257.20:12:00.19/wx/17.24,1014.6,97 2006.257.20:12:00.25/fmout-gps/S +4.51E-07 2006.257.20:12:00.25:scan_name=257-2015,jd0609,440 2006.257.20:12:00.26:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.257.20:12:01.14#flagr#flagr/antenna,new-source 2006.257.20:12:01.14:checkk5 2006.257.20:12:01.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.20:12:01.84/chk_autoobs//k5ts2/ autoobs is running! 2006.257.20:12:02.19/chk_autoobs//k5ts3/ autoobs is running! 2006.257.20:12:02.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.20:12:02.86/chk_obsdata//k5ts1/T2572008??a.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.20:12:03.20/chk_obsdata//k5ts2/T2572008??b.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.20:12:03.53/chk_obsdata//k5ts3/T2572008??c.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.20:12:03.86/chk_obsdata//k5ts4/T2572008??d.dat file size is correct (nominal:800MB, actual:796MB). 2006.257.20:12:04.52/k5log//k5ts1_log_newline 2006.257.20:12:05.17/k5log//k5ts2_log_newline 2006.257.20:12:05.83/k5log//k5ts3_log_newline 2006.257.20:12:06.49/k5log//k5ts4_log_newline 2006.257.20:12:06.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.20:12:06.51:setupk4=1 2006.257.20:12:06.51$setupk4/echo=on 2006.257.20:12:06.52$setupk4/pcalon 2006.257.20:12:06.52$pcalon/"no phase cal control is implemented here 2006.257.20:12:06.52$setupk4/"tpicd=stop 2006.257.20:12:06.52$setupk4/"rec=synch_on 2006.257.20:12:06.52$setupk4/"rec_mode=128 2006.257.20:12:06.52$setupk4/!* 2006.257.20:12:06.52$setupk4/recpk4 2006.257.20:12:06.52$recpk4/recpatch= 2006.257.20:12:06.52$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.20:12:06.52$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.20:12:06.52$setupk4/vck44 2006.257.20:12:06.52$vck44/valo=1,524.99 2006.257.20:12:06.52#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.20:12:06.52#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.20:12:06.52#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:06.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:06.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:06.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:06.52#ibcon#enter wrdev, iclass 34, count 0 2006.257.20:12:06.52#ibcon#first serial, iclass 34, count 0 2006.257.20:12:06.52#ibcon#enter sib2, iclass 34, count 0 2006.257.20:12:06.52#ibcon#flushed, iclass 34, count 0 2006.257.20:12:06.52#ibcon#about to write, iclass 34, count 0 2006.257.20:12:06.52#ibcon#wrote, iclass 34, count 0 2006.257.20:12:06.52#ibcon#about to read 3, iclass 34, count 0 2006.257.20:12:06.54#ibcon#read 3, iclass 34, count 0 2006.257.20:12:06.54#ibcon#about to read 4, iclass 34, count 0 2006.257.20:12:06.54#ibcon#read 4, iclass 34, count 0 2006.257.20:12:06.54#ibcon#about to read 5, iclass 34, count 0 2006.257.20:12:06.54#ibcon#read 5, iclass 34, count 0 2006.257.20:12:06.54#ibcon#about to read 6, iclass 34, count 0 2006.257.20:12:06.54#ibcon#read 6, iclass 34, count 0 2006.257.20:12:06.54#ibcon#end of sib2, iclass 34, count 0 2006.257.20:12:06.54#ibcon#*mode == 0, iclass 34, count 0 2006.257.20:12:06.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.20:12:06.54#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.20:12:06.54#ibcon#*before write, iclass 34, count 0 2006.257.20:12:06.54#ibcon#enter sib2, iclass 34, count 0 2006.257.20:12:06.54#ibcon#flushed, iclass 34, count 0 2006.257.20:12:06.54#ibcon#about to write, iclass 34, count 0 2006.257.20:12:06.54#ibcon#wrote, iclass 34, count 0 2006.257.20:12:06.54#ibcon#about to read 3, iclass 34, count 0 2006.257.20:12:06.59#ibcon#read 3, iclass 34, count 0 2006.257.20:12:06.59#ibcon#about to read 4, iclass 34, count 0 2006.257.20:12:06.59#ibcon#read 4, iclass 34, count 0 2006.257.20:12:06.59#ibcon#about to read 5, iclass 34, count 0 2006.257.20:12:06.59#ibcon#read 5, iclass 34, count 0 2006.257.20:12:06.59#ibcon#about to read 6, iclass 34, count 0 2006.257.20:12:06.59#ibcon#read 6, iclass 34, count 0 2006.257.20:12:06.59#ibcon#end of sib2, iclass 34, count 0 2006.257.20:12:06.59#ibcon#*after write, iclass 34, count 0 2006.257.20:12:06.59#ibcon#*before return 0, iclass 34, count 0 2006.257.20:12:06.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:06.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:06.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.20:12:06.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.20:12:06.59$vck44/va=1,8 2006.257.20:12:06.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.20:12:06.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.20:12:06.59#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:06.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:06.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:06.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:06.59#ibcon#enter wrdev, iclass 36, count 2 2006.257.20:12:06.59#ibcon#first serial, iclass 36, count 2 2006.257.20:12:06.59#ibcon#enter sib2, iclass 36, count 2 2006.257.20:12:06.59#ibcon#flushed, iclass 36, count 2 2006.257.20:12:06.59#ibcon#about to write, iclass 36, count 2 2006.257.20:12:06.59#ibcon#wrote, iclass 36, count 2 2006.257.20:12:06.59#ibcon#about to read 3, iclass 36, count 2 2006.257.20:12:06.61#ibcon#read 3, iclass 36, count 2 2006.257.20:12:06.61#ibcon#about to read 4, iclass 36, count 2 2006.257.20:12:06.61#ibcon#read 4, iclass 36, count 2 2006.257.20:12:06.61#ibcon#about to read 5, iclass 36, count 2 2006.257.20:12:06.61#ibcon#read 5, iclass 36, count 2 2006.257.20:12:06.61#ibcon#about to read 6, iclass 36, count 2 2006.257.20:12:06.61#ibcon#read 6, iclass 36, count 2 2006.257.20:12:06.61#ibcon#end of sib2, iclass 36, count 2 2006.257.20:12:06.61#ibcon#*mode == 0, iclass 36, count 2 2006.257.20:12:06.61#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.20:12:06.61#ibcon#[25=AT01-08\r\n] 2006.257.20:12:06.61#ibcon#*before write, iclass 36, count 2 2006.257.20:12:06.61#ibcon#enter sib2, iclass 36, count 2 2006.257.20:12:06.61#ibcon#flushed, iclass 36, count 2 2006.257.20:12:06.61#ibcon#about to write, iclass 36, count 2 2006.257.20:12:06.61#ibcon#wrote, iclass 36, count 2 2006.257.20:12:06.61#ibcon#about to read 3, iclass 36, count 2 2006.257.20:12:06.64#ibcon#read 3, iclass 36, count 2 2006.257.20:12:06.64#ibcon#about to read 4, iclass 36, count 2 2006.257.20:12:06.64#ibcon#read 4, iclass 36, count 2 2006.257.20:12:06.64#ibcon#about to read 5, iclass 36, count 2 2006.257.20:12:06.64#ibcon#read 5, iclass 36, count 2 2006.257.20:12:06.64#ibcon#about to read 6, iclass 36, count 2 2006.257.20:12:06.64#ibcon#read 6, iclass 36, count 2 2006.257.20:12:06.64#ibcon#end of sib2, iclass 36, count 2 2006.257.20:12:06.64#ibcon#*after write, iclass 36, count 2 2006.257.20:12:06.64#ibcon#*before return 0, iclass 36, count 2 2006.257.20:12:06.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:06.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:06.64#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.20:12:06.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:06.64#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:06.76#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:06.76#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:06.76#ibcon#enter wrdev, iclass 36, count 0 2006.257.20:12:06.76#ibcon#first serial, iclass 36, count 0 2006.257.20:12:06.76#ibcon#enter sib2, iclass 36, count 0 2006.257.20:12:06.76#ibcon#flushed, iclass 36, count 0 2006.257.20:12:06.76#ibcon#about to write, iclass 36, count 0 2006.257.20:12:06.76#ibcon#wrote, iclass 36, count 0 2006.257.20:12:06.76#ibcon#about to read 3, iclass 36, count 0 2006.257.20:12:06.78#ibcon#read 3, iclass 36, count 0 2006.257.20:12:06.78#ibcon#about to read 4, iclass 36, count 0 2006.257.20:12:06.78#ibcon#read 4, iclass 36, count 0 2006.257.20:12:06.78#ibcon#about to read 5, iclass 36, count 0 2006.257.20:12:06.78#ibcon#read 5, iclass 36, count 0 2006.257.20:12:06.78#ibcon#about to read 6, iclass 36, count 0 2006.257.20:12:06.78#ibcon#read 6, iclass 36, count 0 2006.257.20:12:06.78#ibcon#end of sib2, iclass 36, count 0 2006.257.20:12:06.78#ibcon#*mode == 0, iclass 36, count 0 2006.257.20:12:06.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.20:12:06.78#ibcon#[25=USB\r\n] 2006.257.20:12:06.78#ibcon#*before write, iclass 36, count 0 2006.257.20:12:06.78#ibcon#enter sib2, iclass 36, count 0 2006.257.20:12:06.78#ibcon#flushed, iclass 36, count 0 2006.257.20:12:06.78#ibcon#about to write, iclass 36, count 0 2006.257.20:12:06.78#ibcon#wrote, iclass 36, count 0 2006.257.20:12:06.78#ibcon#about to read 3, iclass 36, count 0 2006.257.20:12:06.81#ibcon#read 3, iclass 36, count 0 2006.257.20:12:06.81#ibcon#about to read 4, iclass 36, count 0 2006.257.20:12:06.81#ibcon#read 4, iclass 36, count 0 2006.257.20:12:06.81#ibcon#about to read 5, iclass 36, count 0 2006.257.20:12:06.81#ibcon#read 5, iclass 36, count 0 2006.257.20:12:06.81#ibcon#about to read 6, iclass 36, count 0 2006.257.20:12:06.81#ibcon#read 6, iclass 36, count 0 2006.257.20:12:06.81#ibcon#end of sib2, iclass 36, count 0 2006.257.20:12:06.81#ibcon#*after write, iclass 36, count 0 2006.257.20:12:06.81#ibcon#*before return 0, iclass 36, count 0 2006.257.20:12:06.81#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:06.81#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:06.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.20:12:06.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.20:12:06.81$vck44/valo=2,534.99 2006.257.20:12:06.81#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.20:12:06.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.20:12:06.81#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:06.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:06.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:06.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:06.81#ibcon#enter wrdev, iclass 38, count 0 2006.257.20:12:06.81#ibcon#first serial, iclass 38, count 0 2006.257.20:12:06.81#ibcon#enter sib2, iclass 38, count 0 2006.257.20:12:06.81#ibcon#flushed, iclass 38, count 0 2006.257.20:12:06.81#ibcon#about to write, iclass 38, count 0 2006.257.20:12:06.81#ibcon#wrote, iclass 38, count 0 2006.257.20:12:06.81#ibcon#about to read 3, iclass 38, count 0 2006.257.20:12:06.83#ibcon#read 3, iclass 38, count 0 2006.257.20:12:06.83#ibcon#about to read 4, iclass 38, count 0 2006.257.20:12:06.83#ibcon#read 4, iclass 38, count 0 2006.257.20:12:06.83#ibcon#about to read 5, iclass 38, count 0 2006.257.20:12:06.83#ibcon#read 5, iclass 38, count 0 2006.257.20:12:06.83#ibcon#about to read 6, iclass 38, count 0 2006.257.20:12:06.83#ibcon#read 6, iclass 38, count 0 2006.257.20:12:06.83#ibcon#end of sib2, iclass 38, count 0 2006.257.20:12:06.83#ibcon#*mode == 0, iclass 38, count 0 2006.257.20:12:06.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.20:12:06.83#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.20:12:06.83#ibcon#*before write, iclass 38, count 0 2006.257.20:12:06.83#ibcon#enter sib2, iclass 38, count 0 2006.257.20:12:06.83#ibcon#flushed, iclass 38, count 0 2006.257.20:12:06.83#ibcon#about to write, iclass 38, count 0 2006.257.20:12:06.83#ibcon#wrote, iclass 38, count 0 2006.257.20:12:06.83#ibcon#about to read 3, iclass 38, count 0 2006.257.20:12:06.87#ibcon#read 3, iclass 38, count 0 2006.257.20:12:06.87#ibcon#about to read 4, iclass 38, count 0 2006.257.20:12:06.87#ibcon#read 4, iclass 38, count 0 2006.257.20:12:06.87#ibcon#about to read 5, iclass 38, count 0 2006.257.20:12:06.87#ibcon#read 5, iclass 38, count 0 2006.257.20:12:06.87#ibcon#about to read 6, iclass 38, count 0 2006.257.20:12:06.87#ibcon#read 6, iclass 38, count 0 2006.257.20:12:06.87#ibcon#end of sib2, iclass 38, count 0 2006.257.20:12:06.87#ibcon#*after write, iclass 38, count 0 2006.257.20:12:06.87#ibcon#*before return 0, iclass 38, count 0 2006.257.20:12:06.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:06.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:06.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.20:12:06.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.20:12:06.87$vck44/va=2,7 2006.257.20:12:06.87#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.20:12:06.87#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.20:12:06.87#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:06.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:06.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:06.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:06.93#ibcon#enter wrdev, iclass 40, count 2 2006.257.20:12:06.93#ibcon#first serial, iclass 40, count 2 2006.257.20:12:06.93#ibcon#enter sib2, iclass 40, count 2 2006.257.20:12:06.93#ibcon#flushed, iclass 40, count 2 2006.257.20:12:06.93#ibcon#about to write, iclass 40, count 2 2006.257.20:12:06.93#ibcon#wrote, iclass 40, count 2 2006.257.20:12:06.93#ibcon#about to read 3, iclass 40, count 2 2006.257.20:12:06.95#ibcon#read 3, iclass 40, count 2 2006.257.20:12:06.95#ibcon#about to read 4, iclass 40, count 2 2006.257.20:12:06.95#ibcon#read 4, iclass 40, count 2 2006.257.20:12:06.95#ibcon#about to read 5, iclass 40, count 2 2006.257.20:12:06.95#ibcon#read 5, iclass 40, count 2 2006.257.20:12:06.95#ibcon#about to read 6, iclass 40, count 2 2006.257.20:12:06.95#ibcon#read 6, iclass 40, count 2 2006.257.20:12:06.95#ibcon#end of sib2, iclass 40, count 2 2006.257.20:12:06.95#ibcon#*mode == 0, iclass 40, count 2 2006.257.20:12:06.95#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.20:12:06.95#ibcon#[25=AT02-07\r\n] 2006.257.20:12:06.95#ibcon#*before write, iclass 40, count 2 2006.257.20:12:06.95#ibcon#enter sib2, iclass 40, count 2 2006.257.20:12:06.95#ibcon#flushed, iclass 40, count 2 2006.257.20:12:06.95#ibcon#about to write, iclass 40, count 2 2006.257.20:12:06.95#ibcon#wrote, iclass 40, count 2 2006.257.20:12:06.95#ibcon#about to read 3, iclass 40, count 2 2006.257.20:12:06.98#ibcon#read 3, iclass 40, count 2 2006.257.20:12:06.98#ibcon#about to read 4, iclass 40, count 2 2006.257.20:12:06.98#ibcon#read 4, iclass 40, count 2 2006.257.20:12:06.98#ibcon#about to read 5, iclass 40, count 2 2006.257.20:12:06.98#ibcon#read 5, iclass 40, count 2 2006.257.20:12:06.98#ibcon#about to read 6, iclass 40, count 2 2006.257.20:12:06.98#ibcon#read 6, iclass 40, count 2 2006.257.20:12:06.98#ibcon#end of sib2, iclass 40, count 2 2006.257.20:12:06.98#ibcon#*after write, iclass 40, count 2 2006.257.20:12:06.98#ibcon#*before return 0, iclass 40, count 2 2006.257.20:12:06.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:06.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:06.98#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.20:12:06.98#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:06.98#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:07.10#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:07.10#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:07.10#ibcon#enter wrdev, iclass 40, count 0 2006.257.20:12:07.10#ibcon#first serial, iclass 40, count 0 2006.257.20:12:07.10#ibcon#enter sib2, iclass 40, count 0 2006.257.20:12:07.10#ibcon#flushed, iclass 40, count 0 2006.257.20:12:07.10#ibcon#about to write, iclass 40, count 0 2006.257.20:12:07.10#ibcon#wrote, iclass 40, count 0 2006.257.20:12:07.10#ibcon#about to read 3, iclass 40, count 0 2006.257.20:12:07.12#ibcon#read 3, iclass 40, count 0 2006.257.20:12:07.12#ibcon#about to read 4, iclass 40, count 0 2006.257.20:12:07.12#ibcon#read 4, iclass 40, count 0 2006.257.20:12:07.12#ibcon#about to read 5, iclass 40, count 0 2006.257.20:12:07.12#ibcon#read 5, iclass 40, count 0 2006.257.20:12:07.12#ibcon#about to read 6, iclass 40, count 0 2006.257.20:12:07.12#ibcon#read 6, iclass 40, count 0 2006.257.20:12:07.12#ibcon#end of sib2, iclass 40, count 0 2006.257.20:12:07.12#ibcon#*mode == 0, iclass 40, count 0 2006.257.20:12:07.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.20:12:07.12#ibcon#[25=USB\r\n] 2006.257.20:12:07.12#ibcon#*before write, iclass 40, count 0 2006.257.20:12:07.12#ibcon#enter sib2, iclass 40, count 0 2006.257.20:12:07.12#ibcon#flushed, iclass 40, count 0 2006.257.20:12:07.12#ibcon#about to write, iclass 40, count 0 2006.257.20:12:07.12#ibcon#wrote, iclass 40, count 0 2006.257.20:12:07.12#ibcon#about to read 3, iclass 40, count 0 2006.257.20:12:07.15#ibcon#read 3, iclass 40, count 0 2006.257.20:12:07.15#ibcon#about to read 4, iclass 40, count 0 2006.257.20:12:07.15#ibcon#read 4, iclass 40, count 0 2006.257.20:12:07.15#ibcon#about to read 5, iclass 40, count 0 2006.257.20:12:07.15#ibcon#read 5, iclass 40, count 0 2006.257.20:12:07.15#ibcon#about to read 6, iclass 40, count 0 2006.257.20:12:07.15#ibcon#read 6, iclass 40, count 0 2006.257.20:12:07.15#ibcon#end of sib2, iclass 40, count 0 2006.257.20:12:07.15#ibcon#*after write, iclass 40, count 0 2006.257.20:12:07.15#ibcon#*before return 0, iclass 40, count 0 2006.257.20:12:07.15#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:07.15#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:07.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.20:12:07.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.20:12:07.15$vck44/valo=3,564.99 2006.257.20:12:07.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.20:12:07.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.20:12:07.15#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:07.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:07.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:07.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:07.15#ibcon#enter wrdev, iclass 4, count 0 2006.257.20:12:07.15#ibcon#first serial, iclass 4, count 0 2006.257.20:12:07.15#ibcon#enter sib2, iclass 4, count 0 2006.257.20:12:07.15#ibcon#flushed, iclass 4, count 0 2006.257.20:12:07.15#ibcon#about to write, iclass 4, count 0 2006.257.20:12:07.15#ibcon#wrote, iclass 4, count 0 2006.257.20:12:07.15#ibcon#about to read 3, iclass 4, count 0 2006.257.20:12:07.17#ibcon#read 3, iclass 4, count 0 2006.257.20:12:07.17#ibcon#about to read 4, iclass 4, count 0 2006.257.20:12:07.17#ibcon#read 4, iclass 4, count 0 2006.257.20:12:07.17#ibcon#about to read 5, iclass 4, count 0 2006.257.20:12:07.17#ibcon#read 5, iclass 4, count 0 2006.257.20:12:07.17#ibcon#about to read 6, iclass 4, count 0 2006.257.20:12:07.17#ibcon#read 6, iclass 4, count 0 2006.257.20:12:07.17#ibcon#end of sib2, iclass 4, count 0 2006.257.20:12:07.17#ibcon#*mode == 0, iclass 4, count 0 2006.257.20:12:07.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.20:12:07.17#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.20:12:07.17#ibcon#*before write, iclass 4, count 0 2006.257.20:12:07.17#ibcon#enter sib2, iclass 4, count 0 2006.257.20:12:07.17#ibcon#flushed, iclass 4, count 0 2006.257.20:12:07.17#ibcon#about to write, iclass 4, count 0 2006.257.20:12:07.17#ibcon#wrote, iclass 4, count 0 2006.257.20:12:07.17#ibcon#about to read 3, iclass 4, count 0 2006.257.20:12:07.21#ibcon#read 3, iclass 4, count 0 2006.257.20:12:07.21#ibcon#about to read 4, iclass 4, count 0 2006.257.20:12:07.21#ibcon#read 4, iclass 4, count 0 2006.257.20:12:07.21#ibcon#about to read 5, iclass 4, count 0 2006.257.20:12:07.21#ibcon#read 5, iclass 4, count 0 2006.257.20:12:07.21#ibcon#about to read 6, iclass 4, count 0 2006.257.20:12:07.21#ibcon#read 6, iclass 4, count 0 2006.257.20:12:07.21#ibcon#end of sib2, iclass 4, count 0 2006.257.20:12:07.21#ibcon#*after write, iclass 4, count 0 2006.257.20:12:07.21#ibcon#*before return 0, iclass 4, count 0 2006.257.20:12:07.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:07.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:07.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.20:12:07.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.20:12:07.21$vck44/va=3,8 2006.257.20:12:07.21#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.20:12:07.21#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.20:12:07.21#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:07.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:07.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:07.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:07.27#ibcon#enter wrdev, iclass 6, count 2 2006.257.20:12:07.27#ibcon#first serial, iclass 6, count 2 2006.257.20:12:07.27#ibcon#enter sib2, iclass 6, count 2 2006.257.20:12:07.27#ibcon#flushed, iclass 6, count 2 2006.257.20:12:07.27#ibcon#about to write, iclass 6, count 2 2006.257.20:12:07.27#ibcon#wrote, iclass 6, count 2 2006.257.20:12:07.27#ibcon#about to read 3, iclass 6, count 2 2006.257.20:12:07.29#ibcon#read 3, iclass 6, count 2 2006.257.20:12:07.29#ibcon#about to read 4, iclass 6, count 2 2006.257.20:12:07.29#ibcon#read 4, iclass 6, count 2 2006.257.20:12:07.29#ibcon#about to read 5, iclass 6, count 2 2006.257.20:12:07.29#ibcon#read 5, iclass 6, count 2 2006.257.20:12:07.29#ibcon#about to read 6, iclass 6, count 2 2006.257.20:12:07.29#ibcon#read 6, iclass 6, count 2 2006.257.20:12:07.29#ibcon#end of sib2, iclass 6, count 2 2006.257.20:12:07.29#ibcon#*mode == 0, iclass 6, count 2 2006.257.20:12:07.29#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.20:12:07.29#ibcon#[25=AT03-08\r\n] 2006.257.20:12:07.29#ibcon#*before write, iclass 6, count 2 2006.257.20:12:07.29#ibcon#enter sib2, iclass 6, count 2 2006.257.20:12:07.29#ibcon#flushed, iclass 6, count 2 2006.257.20:12:07.29#ibcon#about to write, iclass 6, count 2 2006.257.20:12:07.29#ibcon#wrote, iclass 6, count 2 2006.257.20:12:07.29#ibcon#about to read 3, iclass 6, count 2 2006.257.20:12:07.32#ibcon#read 3, iclass 6, count 2 2006.257.20:12:07.32#ibcon#about to read 4, iclass 6, count 2 2006.257.20:12:07.32#ibcon#read 4, iclass 6, count 2 2006.257.20:12:07.32#ibcon#about to read 5, iclass 6, count 2 2006.257.20:12:07.32#ibcon#read 5, iclass 6, count 2 2006.257.20:12:07.32#ibcon#about to read 6, iclass 6, count 2 2006.257.20:12:07.32#ibcon#read 6, iclass 6, count 2 2006.257.20:12:07.32#ibcon#end of sib2, iclass 6, count 2 2006.257.20:12:07.32#ibcon#*after write, iclass 6, count 2 2006.257.20:12:07.32#ibcon#*before return 0, iclass 6, count 2 2006.257.20:12:07.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:07.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:07.32#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.20:12:07.32#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:07.32#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:07.44#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:07.44#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:07.44#ibcon#enter wrdev, iclass 6, count 0 2006.257.20:12:07.44#ibcon#first serial, iclass 6, count 0 2006.257.20:12:07.44#ibcon#enter sib2, iclass 6, count 0 2006.257.20:12:07.44#ibcon#flushed, iclass 6, count 0 2006.257.20:12:07.44#ibcon#about to write, iclass 6, count 0 2006.257.20:12:07.44#ibcon#wrote, iclass 6, count 0 2006.257.20:12:07.44#ibcon#about to read 3, iclass 6, count 0 2006.257.20:12:07.46#ibcon#read 3, iclass 6, count 0 2006.257.20:12:07.46#ibcon#about to read 4, iclass 6, count 0 2006.257.20:12:07.46#ibcon#read 4, iclass 6, count 0 2006.257.20:12:07.46#ibcon#about to read 5, iclass 6, count 0 2006.257.20:12:07.46#ibcon#read 5, iclass 6, count 0 2006.257.20:12:07.46#ibcon#about to read 6, iclass 6, count 0 2006.257.20:12:07.46#ibcon#read 6, iclass 6, count 0 2006.257.20:12:07.46#ibcon#end of sib2, iclass 6, count 0 2006.257.20:12:07.46#ibcon#*mode == 0, iclass 6, count 0 2006.257.20:12:07.46#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.20:12:07.46#ibcon#[25=USB\r\n] 2006.257.20:12:07.46#ibcon#*before write, iclass 6, count 0 2006.257.20:12:07.46#ibcon#enter sib2, iclass 6, count 0 2006.257.20:12:07.46#ibcon#flushed, iclass 6, count 0 2006.257.20:12:07.46#ibcon#about to write, iclass 6, count 0 2006.257.20:12:07.46#ibcon#wrote, iclass 6, count 0 2006.257.20:12:07.46#ibcon#about to read 3, iclass 6, count 0 2006.257.20:12:07.49#ibcon#read 3, iclass 6, count 0 2006.257.20:12:07.49#ibcon#about to read 4, iclass 6, count 0 2006.257.20:12:07.49#ibcon#read 4, iclass 6, count 0 2006.257.20:12:07.49#ibcon#about to read 5, iclass 6, count 0 2006.257.20:12:07.49#ibcon#read 5, iclass 6, count 0 2006.257.20:12:07.49#ibcon#about to read 6, iclass 6, count 0 2006.257.20:12:07.49#ibcon#read 6, iclass 6, count 0 2006.257.20:12:07.49#ibcon#end of sib2, iclass 6, count 0 2006.257.20:12:07.49#ibcon#*after write, iclass 6, count 0 2006.257.20:12:07.49#ibcon#*before return 0, iclass 6, count 0 2006.257.20:12:07.49#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:07.49#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:07.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.20:12:07.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.20:12:07.49$vck44/valo=4,624.99 2006.257.20:12:07.49#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.20:12:07.49#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.20:12:07.49#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:07.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:07.49#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:07.49#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:07.49#ibcon#enter wrdev, iclass 10, count 0 2006.257.20:12:07.49#ibcon#first serial, iclass 10, count 0 2006.257.20:12:07.49#ibcon#enter sib2, iclass 10, count 0 2006.257.20:12:07.49#ibcon#flushed, iclass 10, count 0 2006.257.20:12:07.49#ibcon#about to write, iclass 10, count 0 2006.257.20:12:07.49#ibcon#wrote, iclass 10, count 0 2006.257.20:12:07.49#ibcon#about to read 3, iclass 10, count 0 2006.257.20:12:07.51#ibcon#read 3, iclass 10, count 0 2006.257.20:12:07.51#ibcon#about to read 4, iclass 10, count 0 2006.257.20:12:07.51#ibcon#read 4, iclass 10, count 0 2006.257.20:12:07.51#ibcon#about to read 5, iclass 10, count 0 2006.257.20:12:07.51#ibcon#read 5, iclass 10, count 0 2006.257.20:12:07.51#ibcon#about to read 6, iclass 10, count 0 2006.257.20:12:07.51#ibcon#read 6, iclass 10, count 0 2006.257.20:12:07.51#ibcon#end of sib2, iclass 10, count 0 2006.257.20:12:07.51#ibcon#*mode == 0, iclass 10, count 0 2006.257.20:12:07.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.20:12:07.51#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.20:12:07.51#ibcon#*before write, iclass 10, count 0 2006.257.20:12:07.51#ibcon#enter sib2, iclass 10, count 0 2006.257.20:12:07.51#ibcon#flushed, iclass 10, count 0 2006.257.20:12:07.51#ibcon#about to write, iclass 10, count 0 2006.257.20:12:07.51#ibcon#wrote, iclass 10, count 0 2006.257.20:12:07.51#ibcon#about to read 3, iclass 10, count 0 2006.257.20:12:07.55#ibcon#read 3, iclass 10, count 0 2006.257.20:12:07.55#ibcon#about to read 4, iclass 10, count 0 2006.257.20:12:07.55#ibcon#read 4, iclass 10, count 0 2006.257.20:12:07.55#ibcon#about to read 5, iclass 10, count 0 2006.257.20:12:07.55#ibcon#read 5, iclass 10, count 0 2006.257.20:12:07.55#ibcon#about to read 6, iclass 10, count 0 2006.257.20:12:07.55#ibcon#read 6, iclass 10, count 0 2006.257.20:12:07.55#ibcon#end of sib2, iclass 10, count 0 2006.257.20:12:07.55#ibcon#*after write, iclass 10, count 0 2006.257.20:12:07.55#ibcon#*before return 0, iclass 10, count 0 2006.257.20:12:07.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:07.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:07.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.20:12:07.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.20:12:07.55$vck44/va=4,7 2006.257.20:12:07.55#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.20:12:07.55#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.20:12:07.55#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:07.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:07.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:07.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:07.61#ibcon#enter wrdev, iclass 12, count 2 2006.257.20:12:07.61#ibcon#first serial, iclass 12, count 2 2006.257.20:12:07.61#ibcon#enter sib2, iclass 12, count 2 2006.257.20:12:07.61#ibcon#flushed, iclass 12, count 2 2006.257.20:12:07.61#ibcon#about to write, iclass 12, count 2 2006.257.20:12:07.61#ibcon#wrote, iclass 12, count 2 2006.257.20:12:07.61#ibcon#about to read 3, iclass 12, count 2 2006.257.20:12:07.63#ibcon#read 3, iclass 12, count 2 2006.257.20:12:07.63#ibcon#about to read 4, iclass 12, count 2 2006.257.20:12:07.63#ibcon#read 4, iclass 12, count 2 2006.257.20:12:07.63#ibcon#about to read 5, iclass 12, count 2 2006.257.20:12:07.63#ibcon#read 5, iclass 12, count 2 2006.257.20:12:07.63#ibcon#about to read 6, iclass 12, count 2 2006.257.20:12:07.63#ibcon#read 6, iclass 12, count 2 2006.257.20:12:07.63#ibcon#end of sib2, iclass 12, count 2 2006.257.20:12:07.63#ibcon#*mode == 0, iclass 12, count 2 2006.257.20:12:07.63#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.20:12:07.63#ibcon#[25=AT04-07\r\n] 2006.257.20:12:07.63#ibcon#*before write, iclass 12, count 2 2006.257.20:12:07.63#ibcon#enter sib2, iclass 12, count 2 2006.257.20:12:07.63#ibcon#flushed, iclass 12, count 2 2006.257.20:12:07.63#ibcon#about to write, iclass 12, count 2 2006.257.20:12:07.63#ibcon#wrote, iclass 12, count 2 2006.257.20:12:07.63#ibcon#about to read 3, iclass 12, count 2 2006.257.20:12:07.66#ibcon#read 3, iclass 12, count 2 2006.257.20:12:07.66#ibcon#about to read 4, iclass 12, count 2 2006.257.20:12:07.66#ibcon#read 4, iclass 12, count 2 2006.257.20:12:07.66#ibcon#about to read 5, iclass 12, count 2 2006.257.20:12:07.66#ibcon#read 5, iclass 12, count 2 2006.257.20:12:07.66#ibcon#about to read 6, iclass 12, count 2 2006.257.20:12:07.66#ibcon#read 6, iclass 12, count 2 2006.257.20:12:07.66#ibcon#end of sib2, iclass 12, count 2 2006.257.20:12:07.66#ibcon#*after write, iclass 12, count 2 2006.257.20:12:07.66#ibcon#*before return 0, iclass 12, count 2 2006.257.20:12:07.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:07.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:07.66#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.20:12:07.66#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:07.66#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:07.78#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:07.78#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:07.78#ibcon#enter wrdev, iclass 12, count 0 2006.257.20:12:07.78#ibcon#first serial, iclass 12, count 0 2006.257.20:12:07.78#ibcon#enter sib2, iclass 12, count 0 2006.257.20:12:07.78#ibcon#flushed, iclass 12, count 0 2006.257.20:12:07.78#ibcon#about to write, iclass 12, count 0 2006.257.20:12:07.78#ibcon#wrote, iclass 12, count 0 2006.257.20:12:07.78#ibcon#about to read 3, iclass 12, count 0 2006.257.20:12:07.79#abcon#<5=/14 1.0 2.3 17.23 971014.6\r\n> 2006.257.20:12:07.80#ibcon#read 3, iclass 12, count 0 2006.257.20:12:07.80#ibcon#about to read 4, iclass 12, count 0 2006.257.20:12:07.80#ibcon#read 4, iclass 12, count 0 2006.257.20:12:07.80#ibcon#about to read 5, iclass 12, count 0 2006.257.20:12:07.80#ibcon#read 5, iclass 12, count 0 2006.257.20:12:07.80#ibcon#about to read 6, iclass 12, count 0 2006.257.20:12:07.80#ibcon#read 6, iclass 12, count 0 2006.257.20:12:07.80#ibcon#end of sib2, iclass 12, count 0 2006.257.20:12:07.80#ibcon#*mode == 0, iclass 12, count 0 2006.257.20:12:07.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.20:12:07.80#ibcon#[25=USB\r\n] 2006.257.20:12:07.80#ibcon#*before write, iclass 12, count 0 2006.257.20:12:07.80#ibcon#enter sib2, iclass 12, count 0 2006.257.20:12:07.80#ibcon#flushed, iclass 12, count 0 2006.257.20:12:07.80#ibcon#about to write, iclass 12, count 0 2006.257.20:12:07.80#ibcon#wrote, iclass 12, count 0 2006.257.20:12:07.80#ibcon#about to read 3, iclass 12, count 0 2006.257.20:12:07.81#abcon#{5=INTERFACE CLEAR} 2006.257.20:12:07.83#ibcon#read 3, iclass 12, count 0 2006.257.20:12:07.83#ibcon#about to read 4, iclass 12, count 0 2006.257.20:12:07.83#ibcon#read 4, iclass 12, count 0 2006.257.20:12:07.83#ibcon#about to read 5, iclass 12, count 0 2006.257.20:12:07.83#ibcon#read 5, iclass 12, count 0 2006.257.20:12:07.83#ibcon#about to read 6, iclass 12, count 0 2006.257.20:12:07.83#ibcon#read 6, iclass 12, count 0 2006.257.20:12:07.83#ibcon#end of sib2, iclass 12, count 0 2006.257.20:12:07.83#ibcon#*after write, iclass 12, count 0 2006.257.20:12:07.83#ibcon#*before return 0, iclass 12, count 0 2006.257.20:12:07.83#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:07.83#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:07.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.20:12:07.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.20:12:07.83$vck44/valo=5,734.99 2006.257.20:12:07.83#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.20:12:07.83#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.20:12:07.83#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:07.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:12:07.83#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:12:07.83#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:12:07.83#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:12:07.83#ibcon#first serial, iclass 17, count 0 2006.257.20:12:07.83#ibcon#enter sib2, iclass 17, count 0 2006.257.20:12:07.83#ibcon#flushed, iclass 17, count 0 2006.257.20:12:07.83#ibcon#about to write, iclass 17, count 0 2006.257.20:12:07.83#ibcon#wrote, iclass 17, count 0 2006.257.20:12:07.83#ibcon#about to read 3, iclass 17, count 0 2006.257.20:12:07.85#ibcon#read 3, iclass 17, count 0 2006.257.20:12:07.85#ibcon#about to read 4, iclass 17, count 0 2006.257.20:12:07.85#ibcon#read 4, iclass 17, count 0 2006.257.20:12:07.85#ibcon#about to read 5, iclass 17, count 0 2006.257.20:12:07.85#ibcon#read 5, iclass 17, count 0 2006.257.20:12:07.85#ibcon#about to read 6, iclass 17, count 0 2006.257.20:12:07.85#ibcon#read 6, iclass 17, count 0 2006.257.20:12:07.85#ibcon#end of sib2, iclass 17, count 0 2006.257.20:12:07.85#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:12:07.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:12:07.85#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.20:12:07.85#ibcon#*before write, iclass 17, count 0 2006.257.20:12:07.85#ibcon#enter sib2, iclass 17, count 0 2006.257.20:12:07.85#ibcon#flushed, iclass 17, count 0 2006.257.20:12:07.85#ibcon#about to write, iclass 17, count 0 2006.257.20:12:07.85#ibcon#wrote, iclass 17, count 0 2006.257.20:12:07.85#ibcon#about to read 3, iclass 17, count 0 2006.257.20:12:07.87#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:12:07.89#ibcon#read 3, iclass 17, count 0 2006.257.20:12:07.89#ibcon#about to read 4, iclass 17, count 0 2006.257.20:12:07.89#ibcon#read 4, iclass 17, count 0 2006.257.20:12:07.89#ibcon#about to read 5, iclass 17, count 0 2006.257.20:12:07.89#ibcon#read 5, iclass 17, count 0 2006.257.20:12:07.89#ibcon#about to read 6, iclass 17, count 0 2006.257.20:12:07.89#ibcon#read 6, iclass 17, count 0 2006.257.20:12:07.89#ibcon#end of sib2, iclass 17, count 0 2006.257.20:12:07.89#ibcon#*after write, iclass 17, count 0 2006.257.20:12:07.89#ibcon#*before return 0, iclass 17, count 0 2006.257.20:12:07.89#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:12:07.89#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:12:07.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:12:07.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:12:07.89$vck44/va=5,4 2006.257.20:12:07.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.20:12:07.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.20:12:07.89#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:07.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:07.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:07.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:07.95#ibcon#enter wrdev, iclass 20, count 2 2006.257.20:12:07.95#ibcon#first serial, iclass 20, count 2 2006.257.20:12:07.95#ibcon#enter sib2, iclass 20, count 2 2006.257.20:12:07.95#ibcon#flushed, iclass 20, count 2 2006.257.20:12:07.95#ibcon#about to write, iclass 20, count 2 2006.257.20:12:07.95#ibcon#wrote, iclass 20, count 2 2006.257.20:12:07.95#ibcon#about to read 3, iclass 20, count 2 2006.257.20:12:07.97#ibcon#read 3, iclass 20, count 2 2006.257.20:12:07.97#ibcon#about to read 4, iclass 20, count 2 2006.257.20:12:07.97#ibcon#read 4, iclass 20, count 2 2006.257.20:12:07.97#ibcon#about to read 5, iclass 20, count 2 2006.257.20:12:07.97#ibcon#read 5, iclass 20, count 2 2006.257.20:12:07.97#ibcon#about to read 6, iclass 20, count 2 2006.257.20:12:07.97#ibcon#read 6, iclass 20, count 2 2006.257.20:12:07.97#ibcon#end of sib2, iclass 20, count 2 2006.257.20:12:07.97#ibcon#*mode == 0, iclass 20, count 2 2006.257.20:12:07.97#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.20:12:07.97#ibcon#[25=AT05-04\r\n] 2006.257.20:12:07.97#ibcon#*before write, iclass 20, count 2 2006.257.20:12:07.97#ibcon#enter sib2, iclass 20, count 2 2006.257.20:12:07.97#ibcon#flushed, iclass 20, count 2 2006.257.20:12:07.97#ibcon#about to write, iclass 20, count 2 2006.257.20:12:07.97#ibcon#wrote, iclass 20, count 2 2006.257.20:12:07.97#ibcon#about to read 3, iclass 20, count 2 2006.257.20:12:08.00#ibcon#read 3, iclass 20, count 2 2006.257.20:12:08.00#ibcon#about to read 4, iclass 20, count 2 2006.257.20:12:08.00#ibcon#read 4, iclass 20, count 2 2006.257.20:12:08.00#ibcon#about to read 5, iclass 20, count 2 2006.257.20:12:08.00#ibcon#read 5, iclass 20, count 2 2006.257.20:12:08.00#ibcon#about to read 6, iclass 20, count 2 2006.257.20:12:08.00#ibcon#read 6, iclass 20, count 2 2006.257.20:12:08.00#ibcon#end of sib2, iclass 20, count 2 2006.257.20:12:08.00#ibcon#*after write, iclass 20, count 2 2006.257.20:12:08.00#ibcon#*before return 0, iclass 20, count 2 2006.257.20:12:08.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:08.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:08.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.20:12:08.00#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:08.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:08.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:08.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:08.12#ibcon#enter wrdev, iclass 20, count 0 2006.257.20:12:08.12#ibcon#first serial, iclass 20, count 0 2006.257.20:12:08.12#ibcon#enter sib2, iclass 20, count 0 2006.257.20:12:08.12#ibcon#flushed, iclass 20, count 0 2006.257.20:12:08.12#ibcon#about to write, iclass 20, count 0 2006.257.20:12:08.12#ibcon#wrote, iclass 20, count 0 2006.257.20:12:08.12#ibcon#about to read 3, iclass 20, count 0 2006.257.20:12:08.14#ibcon#read 3, iclass 20, count 0 2006.257.20:12:08.14#ibcon#about to read 4, iclass 20, count 0 2006.257.20:12:08.14#ibcon#read 4, iclass 20, count 0 2006.257.20:12:08.14#ibcon#about to read 5, iclass 20, count 0 2006.257.20:12:08.14#ibcon#read 5, iclass 20, count 0 2006.257.20:12:08.14#ibcon#about to read 6, iclass 20, count 0 2006.257.20:12:08.14#ibcon#read 6, iclass 20, count 0 2006.257.20:12:08.14#ibcon#end of sib2, iclass 20, count 0 2006.257.20:12:08.14#ibcon#*mode == 0, iclass 20, count 0 2006.257.20:12:08.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.20:12:08.14#ibcon#[25=USB\r\n] 2006.257.20:12:08.14#ibcon#*before write, iclass 20, count 0 2006.257.20:12:08.14#ibcon#enter sib2, iclass 20, count 0 2006.257.20:12:08.14#ibcon#flushed, iclass 20, count 0 2006.257.20:12:08.14#ibcon#about to write, iclass 20, count 0 2006.257.20:12:08.14#ibcon#wrote, iclass 20, count 0 2006.257.20:12:08.14#ibcon#about to read 3, iclass 20, count 0 2006.257.20:12:08.17#ibcon#read 3, iclass 20, count 0 2006.257.20:12:08.17#ibcon#about to read 4, iclass 20, count 0 2006.257.20:12:08.17#ibcon#read 4, iclass 20, count 0 2006.257.20:12:08.17#ibcon#about to read 5, iclass 20, count 0 2006.257.20:12:08.17#ibcon#read 5, iclass 20, count 0 2006.257.20:12:08.17#ibcon#about to read 6, iclass 20, count 0 2006.257.20:12:08.17#ibcon#read 6, iclass 20, count 0 2006.257.20:12:08.17#ibcon#end of sib2, iclass 20, count 0 2006.257.20:12:08.17#ibcon#*after write, iclass 20, count 0 2006.257.20:12:08.17#ibcon#*before return 0, iclass 20, count 0 2006.257.20:12:08.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:08.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:08.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.20:12:08.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.20:12:08.17$vck44/valo=6,814.99 2006.257.20:12:08.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.20:12:08.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.20:12:08.17#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:08.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:08.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:08.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:08.17#ibcon#enter wrdev, iclass 22, count 0 2006.257.20:12:08.17#ibcon#first serial, iclass 22, count 0 2006.257.20:12:08.17#ibcon#enter sib2, iclass 22, count 0 2006.257.20:12:08.17#ibcon#flushed, iclass 22, count 0 2006.257.20:12:08.17#ibcon#about to write, iclass 22, count 0 2006.257.20:12:08.17#ibcon#wrote, iclass 22, count 0 2006.257.20:12:08.17#ibcon#about to read 3, iclass 22, count 0 2006.257.20:12:08.19#ibcon#read 3, iclass 22, count 0 2006.257.20:12:08.19#ibcon#about to read 4, iclass 22, count 0 2006.257.20:12:08.19#ibcon#read 4, iclass 22, count 0 2006.257.20:12:08.19#ibcon#about to read 5, iclass 22, count 0 2006.257.20:12:08.19#ibcon#read 5, iclass 22, count 0 2006.257.20:12:08.19#ibcon#about to read 6, iclass 22, count 0 2006.257.20:12:08.19#ibcon#read 6, iclass 22, count 0 2006.257.20:12:08.19#ibcon#end of sib2, iclass 22, count 0 2006.257.20:12:08.19#ibcon#*mode == 0, iclass 22, count 0 2006.257.20:12:08.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.20:12:08.19#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.20:12:08.19#ibcon#*before write, iclass 22, count 0 2006.257.20:12:08.19#ibcon#enter sib2, iclass 22, count 0 2006.257.20:12:08.19#ibcon#flushed, iclass 22, count 0 2006.257.20:12:08.19#ibcon#about to write, iclass 22, count 0 2006.257.20:12:08.19#ibcon#wrote, iclass 22, count 0 2006.257.20:12:08.19#ibcon#about to read 3, iclass 22, count 0 2006.257.20:12:08.23#ibcon#read 3, iclass 22, count 0 2006.257.20:12:08.23#ibcon#about to read 4, iclass 22, count 0 2006.257.20:12:08.23#ibcon#read 4, iclass 22, count 0 2006.257.20:12:08.23#ibcon#about to read 5, iclass 22, count 0 2006.257.20:12:08.23#ibcon#read 5, iclass 22, count 0 2006.257.20:12:08.23#ibcon#about to read 6, iclass 22, count 0 2006.257.20:12:08.23#ibcon#read 6, iclass 22, count 0 2006.257.20:12:08.23#ibcon#end of sib2, iclass 22, count 0 2006.257.20:12:08.23#ibcon#*after write, iclass 22, count 0 2006.257.20:12:08.23#ibcon#*before return 0, iclass 22, count 0 2006.257.20:12:08.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:08.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:08.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.20:12:08.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.20:12:08.23$vck44/va=6,4 2006.257.20:12:08.23#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.20:12:08.23#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.20:12:08.23#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:08.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:08.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:08.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:08.29#ibcon#enter wrdev, iclass 24, count 2 2006.257.20:12:08.29#ibcon#first serial, iclass 24, count 2 2006.257.20:12:08.29#ibcon#enter sib2, iclass 24, count 2 2006.257.20:12:08.29#ibcon#flushed, iclass 24, count 2 2006.257.20:12:08.29#ibcon#about to write, iclass 24, count 2 2006.257.20:12:08.29#ibcon#wrote, iclass 24, count 2 2006.257.20:12:08.29#ibcon#about to read 3, iclass 24, count 2 2006.257.20:12:08.31#ibcon#read 3, iclass 24, count 2 2006.257.20:12:08.31#ibcon#about to read 4, iclass 24, count 2 2006.257.20:12:08.31#ibcon#read 4, iclass 24, count 2 2006.257.20:12:08.31#ibcon#about to read 5, iclass 24, count 2 2006.257.20:12:08.31#ibcon#read 5, iclass 24, count 2 2006.257.20:12:08.31#ibcon#about to read 6, iclass 24, count 2 2006.257.20:12:08.31#ibcon#read 6, iclass 24, count 2 2006.257.20:12:08.31#ibcon#end of sib2, iclass 24, count 2 2006.257.20:12:08.31#ibcon#*mode == 0, iclass 24, count 2 2006.257.20:12:08.31#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.20:12:08.31#ibcon#[25=AT06-04\r\n] 2006.257.20:12:08.31#ibcon#*before write, iclass 24, count 2 2006.257.20:12:08.31#ibcon#enter sib2, iclass 24, count 2 2006.257.20:12:08.31#ibcon#flushed, iclass 24, count 2 2006.257.20:12:08.31#ibcon#about to write, iclass 24, count 2 2006.257.20:12:08.31#ibcon#wrote, iclass 24, count 2 2006.257.20:12:08.31#ibcon#about to read 3, iclass 24, count 2 2006.257.20:12:08.34#ibcon#read 3, iclass 24, count 2 2006.257.20:12:08.34#ibcon#about to read 4, iclass 24, count 2 2006.257.20:12:08.34#ibcon#read 4, iclass 24, count 2 2006.257.20:12:08.34#ibcon#about to read 5, iclass 24, count 2 2006.257.20:12:08.34#ibcon#read 5, iclass 24, count 2 2006.257.20:12:08.34#ibcon#about to read 6, iclass 24, count 2 2006.257.20:12:08.34#ibcon#read 6, iclass 24, count 2 2006.257.20:12:08.34#ibcon#end of sib2, iclass 24, count 2 2006.257.20:12:08.34#ibcon#*after write, iclass 24, count 2 2006.257.20:12:08.34#ibcon#*before return 0, iclass 24, count 2 2006.257.20:12:08.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:08.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:08.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.20:12:08.34#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:08.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:08.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:08.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:08.46#ibcon#enter wrdev, iclass 24, count 0 2006.257.20:12:08.46#ibcon#first serial, iclass 24, count 0 2006.257.20:12:08.46#ibcon#enter sib2, iclass 24, count 0 2006.257.20:12:08.46#ibcon#flushed, iclass 24, count 0 2006.257.20:12:08.46#ibcon#about to write, iclass 24, count 0 2006.257.20:12:08.46#ibcon#wrote, iclass 24, count 0 2006.257.20:12:08.46#ibcon#about to read 3, iclass 24, count 0 2006.257.20:12:08.48#ibcon#read 3, iclass 24, count 0 2006.257.20:12:08.48#ibcon#about to read 4, iclass 24, count 0 2006.257.20:12:08.48#ibcon#read 4, iclass 24, count 0 2006.257.20:12:08.48#ibcon#about to read 5, iclass 24, count 0 2006.257.20:12:08.48#ibcon#read 5, iclass 24, count 0 2006.257.20:12:08.48#ibcon#about to read 6, iclass 24, count 0 2006.257.20:12:08.48#ibcon#read 6, iclass 24, count 0 2006.257.20:12:08.48#ibcon#end of sib2, iclass 24, count 0 2006.257.20:12:08.48#ibcon#*mode == 0, iclass 24, count 0 2006.257.20:12:08.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.20:12:08.48#ibcon#[25=USB\r\n] 2006.257.20:12:08.48#ibcon#*before write, iclass 24, count 0 2006.257.20:12:08.48#ibcon#enter sib2, iclass 24, count 0 2006.257.20:12:08.48#ibcon#flushed, iclass 24, count 0 2006.257.20:12:08.48#ibcon#about to write, iclass 24, count 0 2006.257.20:12:08.48#ibcon#wrote, iclass 24, count 0 2006.257.20:12:08.48#ibcon#about to read 3, iclass 24, count 0 2006.257.20:12:08.51#ibcon#read 3, iclass 24, count 0 2006.257.20:12:08.51#ibcon#about to read 4, iclass 24, count 0 2006.257.20:12:08.51#ibcon#read 4, iclass 24, count 0 2006.257.20:12:08.51#ibcon#about to read 5, iclass 24, count 0 2006.257.20:12:08.51#ibcon#read 5, iclass 24, count 0 2006.257.20:12:08.51#ibcon#about to read 6, iclass 24, count 0 2006.257.20:12:08.51#ibcon#read 6, iclass 24, count 0 2006.257.20:12:08.51#ibcon#end of sib2, iclass 24, count 0 2006.257.20:12:08.51#ibcon#*after write, iclass 24, count 0 2006.257.20:12:08.51#ibcon#*before return 0, iclass 24, count 0 2006.257.20:12:08.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:08.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:08.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.20:12:08.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.20:12:08.51$vck44/valo=7,864.99 2006.257.20:12:08.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.20:12:08.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.20:12:08.51#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:08.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:08.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:08.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:08.51#ibcon#enter wrdev, iclass 26, count 0 2006.257.20:12:08.51#ibcon#first serial, iclass 26, count 0 2006.257.20:12:08.51#ibcon#enter sib2, iclass 26, count 0 2006.257.20:12:08.51#ibcon#flushed, iclass 26, count 0 2006.257.20:12:08.51#ibcon#about to write, iclass 26, count 0 2006.257.20:12:08.51#ibcon#wrote, iclass 26, count 0 2006.257.20:12:08.51#ibcon#about to read 3, iclass 26, count 0 2006.257.20:12:08.53#ibcon#read 3, iclass 26, count 0 2006.257.20:12:08.53#ibcon#about to read 4, iclass 26, count 0 2006.257.20:12:08.53#ibcon#read 4, iclass 26, count 0 2006.257.20:12:08.53#ibcon#about to read 5, iclass 26, count 0 2006.257.20:12:08.53#ibcon#read 5, iclass 26, count 0 2006.257.20:12:08.53#ibcon#about to read 6, iclass 26, count 0 2006.257.20:12:08.53#ibcon#read 6, iclass 26, count 0 2006.257.20:12:08.53#ibcon#end of sib2, iclass 26, count 0 2006.257.20:12:08.53#ibcon#*mode == 0, iclass 26, count 0 2006.257.20:12:08.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.20:12:08.53#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.20:12:08.53#ibcon#*before write, iclass 26, count 0 2006.257.20:12:08.53#ibcon#enter sib2, iclass 26, count 0 2006.257.20:12:08.53#ibcon#flushed, iclass 26, count 0 2006.257.20:12:08.53#ibcon#about to write, iclass 26, count 0 2006.257.20:12:08.53#ibcon#wrote, iclass 26, count 0 2006.257.20:12:08.53#ibcon#about to read 3, iclass 26, count 0 2006.257.20:12:08.57#ibcon#read 3, iclass 26, count 0 2006.257.20:12:08.57#ibcon#about to read 4, iclass 26, count 0 2006.257.20:12:08.57#ibcon#read 4, iclass 26, count 0 2006.257.20:12:08.57#ibcon#about to read 5, iclass 26, count 0 2006.257.20:12:08.57#ibcon#read 5, iclass 26, count 0 2006.257.20:12:08.57#ibcon#about to read 6, iclass 26, count 0 2006.257.20:12:08.57#ibcon#read 6, iclass 26, count 0 2006.257.20:12:08.57#ibcon#end of sib2, iclass 26, count 0 2006.257.20:12:08.57#ibcon#*after write, iclass 26, count 0 2006.257.20:12:08.57#ibcon#*before return 0, iclass 26, count 0 2006.257.20:12:08.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:08.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:08.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.20:12:08.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.20:12:08.57$vck44/va=7,4 2006.257.20:12:08.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.20:12:08.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.20:12:08.57#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:08.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:08.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:08.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:08.63#ibcon#enter wrdev, iclass 28, count 2 2006.257.20:12:08.63#ibcon#first serial, iclass 28, count 2 2006.257.20:12:08.63#ibcon#enter sib2, iclass 28, count 2 2006.257.20:12:08.63#ibcon#flushed, iclass 28, count 2 2006.257.20:12:08.63#ibcon#about to write, iclass 28, count 2 2006.257.20:12:08.63#ibcon#wrote, iclass 28, count 2 2006.257.20:12:08.63#ibcon#about to read 3, iclass 28, count 2 2006.257.20:12:08.65#ibcon#read 3, iclass 28, count 2 2006.257.20:12:08.65#ibcon#about to read 4, iclass 28, count 2 2006.257.20:12:08.65#ibcon#read 4, iclass 28, count 2 2006.257.20:12:08.65#ibcon#about to read 5, iclass 28, count 2 2006.257.20:12:08.65#ibcon#read 5, iclass 28, count 2 2006.257.20:12:08.65#ibcon#about to read 6, iclass 28, count 2 2006.257.20:12:08.65#ibcon#read 6, iclass 28, count 2 2006.257.20:12:08.65#ibcon#end of sib2, iclass 28, count 2 2006.257.20:12:08.65#ibcon#*mode == 0, iclass 28, count 2 2006.257.20:12:08.65#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.20:12:08.65#ibcon#[25=AT07-04\r\n] 2006.257.20:12:08.65#ibcon#*before write, iclass 28, count 2 2006.257.20:12:08.65#ibcon#enter sib2, iclass 28, count 2 2006.257.20:12:08.65#ibcon#flushed, iclass 28, count 2 2006.257.20:12:08.65#ibcon#about to write, iclass 28, count 2 2006.257.20:12:08.65#ibcon#wrote, iclass 28, count 2 2006.257.20:12:08.65#ibcon#about to read 3, iclass 28, count 2 2006.257.20:12:08.68#ibcon#read 3, iclass 28, count 2 2006.257.20:12:08.68#ibcon#about to read 4, iclass 28, count 2 2006.257.20:12:08.68#ibcon#read 4, iclass 28, count 2 2006.257.20:12:08.68#ibcon#about to read 5, iclass 28, count 2 2006.257.20:12:08.68#ibcon#read 5, iclass 28, count 2 2006.257.20:12:08.68#ibcon#about to read 6, iclass 28, count 2 2006.257.20:12:08.68#ibcon#read 6, iclass 28, count 2 2006.257.20:12:08.68#ibcon#end of sib2, iclass 28, count 2 2006.257.20:12:08.68#ibcon#*after write, iclass 28, count 2 2006.257.20:12:08.68#ibcon#*before return 0, iclass 28, count 2 2006.257.20:12:08.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:08.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:08.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.20:12:08.68#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:08.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:08.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:08.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:08.80#ibcon#enter wrdev, iclass 28, count 0 2006.257.20:12:08.80#ibcon#first serial, iclass 28, count 0 2006.257.20:12:08.80#ibcon#enter sib2, iclass 28, count 0 2006.257.20:12:08.80#ibcon#flushed, iclass 28, count 0 2006.257.20:12:08.80#ibcon#about to write, iclass 28, count 0 2006.257.20:12:08.80#ibcon#wrote, iclass 28, count 0 2006.257.20:12:08.80#ibcon#about to read 3, iclass 28, count 0 2006.257.20:12:08.82#ibcon#read 3, iclass 28, count 0 2006.257.20:12:08.82#ibcon#about to read 4, iclass 28, count 0 2006.257.20:12:08.82#ibcon#read 4, iclass 28, count 0 2006.257.20:12:08.82#ibcon#about to read 5, iclass 28, count 0 2006.257.20:12:08.82#ibcon#read 5, iclass 28, count 0 2006.257.20:12:08.82#ibcon#about to read 6, iclass 28, count 0 2006.257.20:12:08.82#ibcon#read 6, iclass 28, count 0 2006.257.20:12:08.82#ibcon#end of sib2, iclass 28, count 0 2006.257.20:12:08.82#ibcon#*mode == 0, iclass 28, count 0 2006.257.20:12:08.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.20:12:08.82#ibcon#[25=USB\r\n] 2006.257.20:12:08.82#ibcon#*before write, iclass 28, count 0 2006.257.20:12:08.82#ibcon#enter sib2, iclass 28, count 0 2006.257.20:12:08.82#ibcon#flushed, iclass 28, count 0 2006.257.20:12:08.82#ibcon#about to write, iclass 28, count 0 2006.257.20:12:08.82#ibcon#wrote, iclass 28, count 0 2006.257.20:12:08.82#ibcon#about to read 3, iclass 28, count 0 2006.257.20:12:08.85#ibcon#read 3, iclass 28, count 0 2006.257.20:12:08.85#ibcon#about to read 4, iclass 28, count 0 2006.257.20:12:08.85#ibcon#read 4, iclass 28, count 0 2006.257.20:12:08.85#ibcon#about to read 5, iclass 28, count 0 2006.257.20:12:08.85#ibcon#read 5, iclass 28, count 0 2006.257.20:12:08.85#ibcon#about to read 6, iclass 28, count 0 2006.257.20:12:08.85#ibcon#read 6, iclass 28, count 0 2006.257.20:12:08.85#ibcon#end of sib2, iclass 28, count 0 2006.257.20:12:08.85#ibcon#*after write, iclass 28, count 0 2006.257.20:12:08.85#ibcon#*before return 0, iclass 28, count 0 2006.257.20:12:08.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:08.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:08.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.20:12:08.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.20:12:08.85$vck44/valo=8,884.99 2006.257.20:12:08.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.20:12:08.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.20:12:08.85#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:08.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:08.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:08.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:08.85#ibcon#enter wrdev, iclass 30, count 0 2006.257.20:12:08.85#ibcon#first serial, iclass 30, count 0 2006.257.20:12:08.85#ibcon#enter sib2, iclass 30, count 0 2006.257.20:12:08.85#ibcon#flushed, iclass 30, count 0 2006.257.20:12:08.85#ibcon#about to write, iclass 30, count 0 2006.257.20:12:08.85#ibcon#wrote, iclass 30, count 0 2006.257.20:12:08.85#ibcon#about to read 3, iclass 30, count 0 2006.257.20:12:08.87#ibcon#read 3, iclass 30, count 0 2006.257.20:12:08.87#ibcon#about to read 4, iclass 30, count 0 2006.257.20:12:08.87#ibcon#read 4, iclass 30, count 0 2006.257.20:12:08.87#ibcon#about to read 5, iclass 30, count 0 2006.257.20:12:08.87#ibcon#read 5, iclass 30, count 0 2006.257.20:12:08.87#ibcon#about to read 6, iclass 30, count 0 2006.257.20:12:08.87#ibcon#read 6, iclass 30, count 0 2006.257.20:12:08.87#ibcon#end of sib2, iclass 30, count 0 2006.257.20:12:08.87#ibcon#*mode == 0, iclass 30, count 0 2006.257.20:12:08.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.20:12:08.87#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.20:12:08.87#ibcon#*before write, iclass 30, count 0 2006.257.20:12:08.87#ibcon#enter sib2, iclass 30, count 0 2006.257.20:12:08.87#ibcon#flushed, iclass 30, count 0 2006.257.20:12:08.87#ibcon#about to write, iclass 30, count 0 2006.257.20:12:08.87#ibcon#wrote, iclass 30, count 0 2006.257.20:12:08.87#ibcon#about to read 3, iclass 30, count 0 2006.257.20:12:08.91#ibcon#read 3, iclass 30, count 0 2006.257.20:12:08.91#ibcon#about to read 4, iclass 30, count 0 2006.257.20:12:08.91#ibcon#read 4, iclass 30, count 0 2006.257.20:12:08.91#ibcon#about to read 5, iclass 30, count 0 2006.257.20:12:08.91#ibcon#read 5, iclass 30, count 0 2006.257.20:12:08.91#ibcon#about to read 6, iclass 30, count 0 2006.257.20:12:08.91#ibcon#read 6, iclass 30, count 0 2006.257.20:12:08.91#ibcon#end of sib2, iclass 30, count 0 2006.257.20:12:08.91#ibcon#*after write, iclass 30, count 0 2006.257.20:12:08.91#ibcon#*before return 0, iclass 30, count 0 2006.257.20:12:08.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:08.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:08.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.20:12:08.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.20:12:08.91$vck44/va=8,4 2006.257.20:12:08.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.20:12:08.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.20:12:08.91#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:08.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:12:08.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:12:08.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:12:08.97#ibcon#enter wrdev, iclass 32, count 2 2006.257.20:12:08.97#ibcon#first serial, iclass 32, count 2 2006.257.20:12:08.97#ibcon#enter sib2, iclass 32, count 2 2006.257.20:12:08.97#ibcon#flushed, iclass 32, count 2 2006.257.20:12:08.97#ibcon#about to write, iclass 32, count 2 2006.257.20:12:08.97#ibcon#wrote, iclass 32, count 2 2006.257.20:12:08.97#ibcon#about to read 3, iclass 32, count 2 2006.257.20:12:08.99#ibcon#read 3, iclass 32, count 2 2006.257.20:12:08.99#ibcon#about to read 4, iclass 32, count 2 2006.257.20:12:08.99#ibcon#read 4, iclass 32, count 2 2006.257.20:12:08.99#ibcon#about to read 5, iclass 32, count 2 2006.257.20:12:08.99#ibcon#read 5, iclass 32, count 2 2006.257.20:12:08.99#ibcon#about to read 6, iclass 32, count 2 2006.257.20:12:08.99#ibcon#read 6, iclass 32, count 2 2006.257.20:12:08.99#ibcon#end of sib2, iclass 32, count 2 2006.257.20:12:08.99#ibcon#*mode == 0, iclass 32, count 2 2006.257.20:12:08.99#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.20:12:08.99#ibcon#[25=AT08-04\r\n] 2006.257.20:12:08.99#ibcon#*before write, iclass 32, count 2 2006.257.20:12:08.99#ibcon#enter sib2, iclass 32, count 2 2006.257.20:12:08.99#ibcon#flushed, iclass 32, count 2 2006.257.20:12:08.99#ibcon#about to write, iclass 32, count 2 2006.257.20:12:08.99#ibcon#wrote, iclass 32, count 2 2006.257.20:12:08.99#ibcon#about to read 3, iclass 32, count 2 2006.257.20:12:09.02#ibcon#read 3, iclass 32, count 2 2006.257.20:12:09.02#ibcon#about to read 4, iclass 32, count 2 2006.257.20:12:09.02#ibcon#read 4, iclass 32, count 2 2006.257.20:12:09.02#ibcon#about to read 5, iclass 32, count 2 2006.257.20:12:09.02#ibcon#read 5, iclass 32, count 2 2006.257.20:12:09.02#ibcon#about to read 6, iclass 32, count 2 2006.257.20:12:09.02#ibcon#read 6, iclass 32, count 2 2006.257.20:12:09.02#ibcon#end of sib2, iclass 32, count 2 2006.257.20:12:09.02#ibcon#*after write, iclass 32, count 2 2006.257.20:12:09.02#ibcon#*before return 0, iclass 32, count 2 2006.257.20:12:09.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:12:09.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:12:09.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.20:12:09.02#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:09.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:12:09.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:12:09.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:12:09.14#ibcon#enter wrdev, iclass 32, count 0 2006.257.20:12:09.14#ibcon#first serial, iclass 32, count 0 2006.257.20:12:09.14#ibcon#enter sib2, iclass 32, count 0 2006.257.20:12:09.14#ibcon#flushed, iclass 32, count 0 2006.257.20:12:09.14#ibcon#about to write, iclass 32, count 0 2006.257.20:12:09.14#ibcon#wrote, iclass 32, count 0 2006.257.20:12:09.14#ibcon#about to read 3, iclass 32, count 0 2006.257.20:12:09.16#ibcon#read 3, iclass 32, count 0 2006.257.20:12:09.16#ibcon#about to read 4, iclass 32, count 0 2006.257.20:12:09.16#ibcon#read 4, iclass 32, count 0 2006.257.20:12:09.16#ibcon#about to read 5, iclass 32, count 0 2006.257.20:12:09.16#ibcon#read 5, iclass 32, count 0 2006.257.20:12:09.16#ibcon#about to read 6, iclass 32, count 0 2006.257.20:12:09.16#ibcon#read 6, iclass 32, count 0 2006.257.20:12:09.16#ibcon#end of sib2, iclass 32, count 0 2006.257.20:12:09.16#ibcon#*mode == 0, iclass 32, count 0 2006.257.20:12:09.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.20:12:09.16#ibcon#[25=USB\r\n] 2006.257.20:12:09.16#ibcon#*before write, iclass 32, count 0 2006.257.20:12:09.16#ibcon#enter sib2, iclass 32, count 0 2006.257.20:12:09.16#ibcon#flushed, iclass 32, count 0 2006.257.20:12:09.16#ibcon#about to write, iclass 32, count 0 2006.257.20:12:09.16#ibcon#wrote, iclass 32, count 0 2006.257.20:12:09.16#ibcon#about to read 3, iclass 32, count 0 2006.257.20:12:09.19#ibcon#read 3, iclass 32, count 0 2006.257.20:12:09.19#ibcon#about to read 4, iclass 32, count 0 2006.257.20:12:09.19#ibcon#read 4, iclass 32, count 0 2006.257.20:12:09.19#ibcon#about to read 5, iclass 32, count 0 2006.257.20:12:09.19#ibcon#read 5, iclass 32, count 0 2006.257.20:12:09.19#ibcon#about to read 6, iclass 32, count 0 2006.257.20:12:09.19#ibcon#read 6, iclass 32, count 0 2006.257.20:12:09.19#ibcon#end of sib2, iclass 32, count 0 2006.257.20:12:09.19#ibcon#*after write, iclass 32, count 0 2006.257.20:12:09.19#ibcon#*before return 0, iclass 32, count 0 2006.257.20:12:09.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:12:09.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:12:09.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.20:12:09.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.20:12:09.19$vck44/vblo=1,629.99 2006.257.20:12:09.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.20:12:09.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.20:12:09.19#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:09.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:09.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:09.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:09.19#ibcon#enter wrdev, iclass 34, count 0 2006.257.20:12:09.19#ibcon#first serial, iclass 34, count 0 2006.257.20:12:09.19#ibcon#enter sib2, iclass 34, count 0 2006.257.20:12:09.19#ibcon#flushed, iclass 34, count 0 2006.257.20:12:09.19#ibcon#about to write, iclass 34, count 0 2006.257.20:12:09.19#ibcon#wrote, iclass 34, count 0 2006.257.20:12:09.19#ibcon#about to read 3, iclass 34, count 0 2006.257.20:12:09.21#ibcon#read 3, iclass 34, count 0 2006.257.20:12:09.21#ibcon#about to read 4, iclass 34, count 0 2006.257.20:12:09.21#ibcon#read 4, iclass 34, count 0 2006.257.20:12:09.21#ibcon#about to read 5, iclass 34, count 0 2006.257.20:12:09.21#ibcon#read 5, iclass 34, count 0 2006.257.20:12:09.21#ibcon#about to read 6, iclass 34, count 0 2006.257.20:12:09.21#ibcon#read 6, iclass 34, count 0 2006.257.20:12:09.21#ibcon#end of sib2, iclass 34, count 0 2006.257.20:12:09.21#ibcon#*mode == 0, iclass 34, count 0 2006.257.20:12:09.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.20:12:09.21#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.20:12:09.21#ibcon#*before write, iclass 34, count 0 2006.257.20:12:09.21#ibcon#enter sib2, iclass 34, count 0 2006.257.20:12:09.21#ibcon#flushed, iclass 34, count 0 2006.257.20:12:09.21#ibcon#about to write, iclass 34, count 0 2006.257.20:12:09.21#ibcon#wrote, iclass 34, count 0 2006.257.20:12:09.21#ibcon#about to read 3, iclass 34, count 0 2006.257.20:12:09.25#ibcon#read 3, iclass 34, count 0 2006.257.20:12:09.25#ibcon#about to read 4, iclass 34, count 0 2006.257.20:12:09.25#ibcon#read 4, iclass 34, count 0 2006.257.20:12:09.25#ibcon#about to read 5, iclass 34, count 0 2006.257.20:12:09.25#ibcon#read 5, iclass 34, count 0 2006.257.20:12:09.25#ibcon#about to read 6, iclass 34, count 0 2006.257.20:12:09.25#ibcon#read 6, iclass 34, count 0 2006.257.20:12:09.25#ibcon#end of sib2, iclass 34, count 0 2006.257.20:12:09.25#ibcon#*after write, iclass 34, count 0 2006.257.20:12:09.25#ibcon#*before return 0, iclass 34, count 0 2006.257.20:12:09.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:09.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:12:09.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.20:12:09.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.20:12:09.25$vck44/vb=1,4 2006.257.20:12:09.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.20:12:09.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.20:12:09.25#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:09.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:09.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:09.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:09.25#ibcon#enter wrdev, iclass 36, count 2 2006.257.20:12:09.25#ibcon#first serial, iclass 36, count 2 2006.257.20:12:09.25#ibcon#enter sib2, iclass 36, count 2 2006.257.20:12:09.25#ibcon#flushed, iclass 36, count 2 2006.257.20:12:09.25#ibcon#about to write, iclass 36, count 2 2006.257.20:12:09.25#ibcon#wrote, iclass 36, count 2 2006.257.20:12:09.25#ibcon#about to read 3, iclass 36, count 2 2006.257.20:12:09.27#ibcon#read 3, iclass 36, count 2 2006.257.20:12:09.27#ibcon#about to read 4, iclass 36, count 2 2006.257.20:12:09.27#ibcon#read 4, iclass 36, count 2 2006.257.20:12:09.27#ibcon#about to read 5, iclass 36, count 2 2006.257.20:12:09.27#ibcon#read 5, iclass 36, count 2 2006.257.20:12:09.27#ibcon#about to read 6, iclass 36, count 2 2006.257.20:12:09.27#ibcon#read 6, iclass 36, count 2 2006.257.20:12:09.27#ibcon#end of sib2, iclass 36, count 2 2006.257.20:12:09.27#ibcon#*mode == 0, iclass 36, count 2 2006.257.20:12:09.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.20:12:09.27#ibcon#[27=AT01-04\r\n] 2006.257.20:12:09.27#ibcon#*before write, iclass 36, count 2 2006.257.20:12:09.27#ibcon#enter sib2, iclass 36, count 2 2006.257.20:12:09.27#ibcon#flushed, iclass 36, count 2 2006.257.20:12:09.27#ibcon#about to write, iclass 36, count 2 2006.257.20:12:09.27#ibcon#wrote, iclass 36, count 2 2006.257.20:12:09.27#ibcon#about to read 3, iclass 36, count 2 2006.257.20:12:09.30#ibcon#read 3, iclass 36, count 2 2006.257.20:12:09.30#ibcon#about to read 4, iclass 36, count 2 2006.257.20:12:09.30#ibcon#read 4, iclass 36, count 2 2006.257.20:12:09.30#ibcon#about to read 5, iclass 36, count 2 2006.257.20:12:09.30#ibcon#read 5, iclass 36, count 2 2006.257.20:12:09.30#ibcon#about to read 6, iclass 36, count 2 2006.257.20:12:09.30#ibcon#read 6, iclass 36, count 2 2006.257.20:12:09.30#ibcon#end of sib2, iclass 36, count 2 2006.257.20:12:09.30#ibcon#*after write, iclass 36, count 2 2006.257.20:12:09.30#ibcon#*before return 0, iclass 36, count 2 2006.257.20:12:09.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:09.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:12:09.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.20:12:09.30#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:09.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:09.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:09.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:09.42#ibcon#enter wrdev, iclass 36, count 0 2006.257.20:12:09.42#ibcon#first serial, iclass 36, count 0 2006.257.20:12:09.42#ibcon#enter sib2, iclass 36, count 0 2006.257.20:12:09.42#ibcon#flushed, iclass 36, count 0 2006.257.20:12:09.42#ibcon#about to write, iclass 36, count 0 2006.257.20:12:09.42#ibcon#wrote, iclass 36, count 0 2006.257.20:12:09.42#ibcon#about to read 3, iclass 36, count 0 2006.257.20:12:09.44#ibcon#read 3, iclass 36, count 0 2006.257.20:12:09.44#ibcon#about to read 4, iclass 36, count 0 2006.257.20:12:09.44#ibcon#read 4, iclass 36, count 0 2006.257.20:12:09.44#ibcon#about to read 5, iclass 36, count 0 2006.257.20:12:09.44#ibcon#read 5, iclass 36, count 0 2006.257.20:12:09.44#ibcon#about to read 6, iclass 36, count 0 2006.257.20:12:09.44#ibcon#read 6, iclass 36, count 0 2006.257.20:12:09.44#ibcon#end of sib2, iclass 36, count 0 2006.257.20:12:09.44#ibcon#*mode == 0, iclass 36, count 0 2006.257.20:12:09.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.20:12:09.44#ibcon#[27=USB\r\n] 2006.257.20:12:09.44#ibcon#*before write, iclass 36, count 0 2006.257.20:12:09.44#ibcon#enter sib2, iclass 36, count 0 2006.257.20:12:09.44#ibcon#flushed, iclass 36, count 0 2006.257.20:12:09.44#ibcon#about to write, iclass 36, count 0 2006.257.20:12:09.44#ibcon#wrote, iclass 36, count 0 2006.257.20:12:09.44#ibcon#about to read 3, iclass 36, count 0 2006.257.20:12:09.47#ibcon#read 3, iclass 36, count 0 2006.257.20:12:09.47#ibcon#about to read 4, iclass 36, count 0 2006.257.20:12:09.47#ibcon#read 4, iclass 36, count 0 2006.257.20:12:09.47#ibcon#about to read 5, iclass 36, count 0 2006.257.20:12:09.47#ibcon#read 5, iclass 36, count 0 2006.257.20:12:09.47#ibcon#about to read 6, iclass 36, count 0 2006.257.20:12:09.47#ibcon#read 6, iclass 36, count 0 2006.257.20:12:09.47#ibcon#end of sib2, iclass 36, count 0 2006.257.20:12:09.47#ibcon#*after write, iclass 36, count 0 2006.257.20:12:09.47#ibcon#*before return 0, iclass 36, count 0 2006.257.20:12:09.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:09.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:12:09.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.20:12:09.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.20:12:09.47$vck44/vblo=2,634.99 2006.257.20:12:09.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.20:12:09.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.20:12:09.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:09.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:09.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:09.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:09.47#ibcon#enter wrdev, iclass 38, count 0 2006.257.20:12:09.47#ibcon#first serial, iclass 38, count 0 2006.257.20:12:09.47#ibcon#enter sib2, iclass 38, count 0 2006.257.20:12:09.47#ibcon#flushed, iclass 38, count 0 2006.257.20:12:09.47#ibcon#about to write, iclass 38, count 0 2006.257.20:12:09.47#ibcon#wrote, iclass 38, count 0 2006.257.20:12:09.47#ibcon#about to read 3, iclass 38, count 0 2006.257.20:12:09.49#ibcon#read 3, iclass 38, count 0 2006.257.20:12:09.49#ibcon#about to read 4, iclass 38, count 0 2006.257.20:12:09.49#ibcon#read 4, iclass 38, count 0 2006.257.20:12:09.49#ibcon#about to read 5, iclass 38, count 0 2006.257.20:12:09.49#ibcon#read 5, iclass 38, count 0 2006.257.20:12:09.49#ibcon#about to read 6, iclass 38, count 0 2006.257.20:12:09.49#ibcon#read 6, iclass 38, count 0 2006.257.20:12:09.49#ibcon#end of sib2, iclass 38, count 0 2006.257.20:12:09.49#ibcon#*mode == 0, iclass 38, count 0 2006.257.20:12:09.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.20:12:09.49#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.20:12:09.49#ibcon#*before write, iclass 38, count 0 2006.257.20:12:09.49#ibcon#enter sib2, iclass 38, count 0 2006.257.20:12:09.49#ibcon#flushed, iclass 38, count 0 2006.257.20:12:09.49#ibcon#about to write, iclass 38, count 0 2006.257.20:12:09.49#ibcon#wrote, iclass 38, count 0 2006.257.20:12:09.49#ibcon#about to read 3, iclass 38, count 0 2006.257.20:12:09.53#ibcon#read 3, iclass 38, count 0 2006.257.20:12:09.53#ibcon#about to read 4, iclass 38, count 0 2006.257.20:12:09.53#ibcon#read 4, iclass 38, count 0 2006.257.20:12:09.53#ibcon#about to read 5, iclass 38, count 0 2006.257.20:12:09.53#ibcon#read 5, iclass 38, count 0 2006.257.20:12:09.53#ibcon#about to read 6, iclass 38, count 0 2006.257.20:12:09.53#ibcon#read 6, iclass 38, count 0 2006.257.20:12:09.53#ibcon#end of sib2, iclass 38, count 0 2006.257.20:12:09.53#ibcon#*after write, iclass 38, count 0 2006.257.20:12:09.53#ibcon#*before return 0, iclass 38, count 0 2006.257.20:12:09.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:09.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:12:09.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.20:12:09.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.20:12:09.53$vck44/vb=2,5 2006.257.20:12:09.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.20:12:09.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.20:12:09.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:09.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:09.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:09.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:09.59#ibcon#enter wrdev, iclass 40, count 2 2006.257.20:12:09.59#ibcon#first serial, iclass 40, count 2 2006.257.20:12:09.59#ibcon#enter sib2, iclass 40, count 2 2006.257.20:12:09.59#ibcon#flushed, iclass 40, count 2 2006.257.20:12:09.59#ibcon#about to write, iclass 40, count 2 2006.257.20:12:09.59#ibcon#wrote, iclass 40, count 2 2006.257.20:12:09.59#ibcon#about to read 3, iclass 40, count 2 2006.257.20:12:09.61#ibcon#read 3, iclass 40, count 2 2006.257.20:12:09.61#ibcon#about to read 4, iclass 40, count 2 2006.257.20:12:09.61#ibcon#read 4, iclass 40, count 2 2006.257.20:12:09.61#ibcon#about to read 5, iclass 40, count 2 2006.257.20:12:09.61#ibcon#read 5, iclass 40, count 2 2006.257.20:12:09.61#ibcon#about to read 6, iclass 40, count 2 2006.257.20:12:09.61#ibcon#read 6, iclass 40, count 2 2006.257.20:12:09.61#ibcon#end of sib2, iclass 40, count 2 2006.257.20:12:09.61#ibcon#*mode == 0, iclass 40, count 2 2006.257.20:12:09.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.20:12:09.61#ibcon#[27=AT02-05\r\n] 2006.257.20:12:09.61#ibcon#*before write, iclass 40, count 2 2006.257.20:12:09.61#ibcon#enter sib2, iclass 40, count 2 2006.257.20:12:09.61#ibcon#flushed, iclass 40, count 2 2006.257.20:12:09.61#ibcon#about to write, iclass 40, count 2 2006.257.20:12:09.61#ibcon#wrote, iclass 40, count 2 2006.257.20:12:09.61#ibcon#about to read 3, iclass 40, count 2 2006.257.20:12:09.64#ibcon#read 3, iclass 40, count 2 2006.257.20:12:09.64#ibcon#about to read 4, iclass 40, count 2 2006.257.20:12:09.64#ibcon#read 4, iclass 40, count 2 2006.257.20:12:09.64#ibcon#about to read 5, iclass 40, count 2 2006.257.20:12:09.64#ibcon#read 5, iclass 40, count 2 2006.257.20:12:09.64#ibcon#about to read 6, iclass 40, count 2 2006.257.20:12:09.64#ibcon#read 6, iclass 40, count 2 2006.257.20:12:09.64#ibcon#end of sib2, iclass 40, count 2 2006.257.20:12:09.64#ibcon#*after write, iclass 40, count 2 2006.257.20:12:09.64#ibcon#*before return 0, iclass 40, count 2 2006.257.20:12:09.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:09.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:12:09.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.20:12:09.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:09.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:09.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:09.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:09.76#ibcon#enter wrdev, iclass 40, count 0 2006.257.20:12:09.76#ibcon#first serial, iclass 40, count 0 2006.257.20:12:09.76#ibcon#enter sib2, iclass 40, count 0 2006.257.20:12:09.76#ibcon#flushed, iclass 40, count 0 2006.257.20:12:09.76#ibcon#about to write, iclass 40, count 0 2006.257.20:12:09.76#ibcon#wrote, iclass 40, count 0 2006.257.20:12:09.76#ibcon#about to read 3, iclass 40, count 0 2006.257.20:12:09.78#ibcon#read 3, iclass 40, count 0 2006.257.20:12:09.78#ibcon#about to read 4, iclass 40, count 0 2006.257.20:12:09.78#ibcon#read 4, iclass 40, count 0 2006.257.20:12:09.78#ibcon#about to read 5, iclass 40, count 0 2006.257.20:12:09.78#ibcon#read 5, iclass 40, count 0 2006.257.20:12:09.78#ibcon#about to read 6, iclass 40, count 0 2006.257.20:12:09.78#ibcon#read 6, iclass 40, count 0 2006.257.20:12:09.78#ibcon#end of sib2, iclass 40, count 0 2006.257.20:12:09.78#ibcon#*mode == 0, iclass 40, count 0 2006.257.20:12:09.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.20:12:09.78#ibcon#[27=USB\r\n] 2006.257.20:12:09.78#ibcon#*before write, iclass 40, count 0 2006.257.20:12:09.78#ibcon#enter sib2, iclass 40, count 0 2006.257.20:12:09.78#ibcon#flushed, iclass 40, count 0 2006.257.20:12:09.78#ibcon#about to write, iclass 40, count 0 2006.257.20:12:09.78#ibcon#wrote, iclass 40, count 0 2006.257.20:12:09.78#ibcon#about to read 3, iclass 40, count 0 2006.257.20:12:09.81#ibcon#read 3, iclass 40, count 0 2006.257.20:12:09.81#ibcon#about to read 4, iclass 40, count 0 2006.257.20:12:09.81#ibcon#read 4, iclass 40, count 0 2006.257.20:12:09.81#ibcon#about to read 5, iclass 40, count 0 2006.257.20:12:09.81#ibcon#read 5, iclass 40, count 0 2006.257.20:12:09.81#ibcon#about to read 6, iclass 40, count 0 2006.257.20:12:09.81#ibcon#read 6, iclass 40, count 0 2006.257.20:12:09.81#ibcon#end of sib2, iclass 40, count 0 2006.257.20:12:09.81#ibcon#*after write, iclass 40, count 0 2006.257.20:12:09.81#ibcon#*before return 0, iclass 40, count 0 2006.257.20:12:09.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:09.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:12:09.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.20:12:09.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.20:12:09.81$vck44/vblo=3,649.99 2006.257.20:12:09.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.20:12:09.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.20:12:09.81#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:09.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:09.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:09.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:09.81#ibcon#enter wrdev, iclass 4, count 0 2006.257.20:12:09.81#ibcon#first serial, iclass 4, count 0 2006.257.20:12:09.81#ibcon#enter sib2, iclass 4, count 0 2006.257.20:12:09.81#ibcon#flushed, iclass 4, count 0 2006.257.20:12:09.81#ibcon#about to write, iclass 4, count 0 2006.257.20:12:09.81#ibcon#wrote, iclass 4, count 0 2006.257.20:12:09.81#ibcon#about to read 3, iclass 4, count 0 2006.257.20:12:09.83#ibcon#read 3, iclass 4, count 0 2006.257.20:12:09.83#ibcon#about to read 4, iclass 4, count 0 2006.257.20:12:09.83#ibcon#read 4, iclass 4, count 0 2006.257.20:12:09.83#ibcon#about to read 5, iclass 4, count 0 2006.257.20:12:09.83#ibcon#read 5, iclass 4, count 0 2006.257.20:12:09.83#ibcon#about to read 6, iclass 4, count 0 2006.257.20:12:09.83#ibcon#read 6, iclass 4, count 0 2006.257.20:12:09.83#ibcon#end of sib2, iclass 4, count 0 2006.257.20:12:09.83#ibcon#*mode == 0, iclass 4, count 0 2006.257.20:12:09.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.20:12:09.83#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.20:12:09.83#ibcon#*before write, iclass 4, count 0 2006.257.20:12:09.83#ibcon#enter sib2, iclass 4, count 0 2006.257.20:12:09.83#ibcon#flushed, iclass 4, count 0 2006.257.20:12:09.83#ibcon#about to write, iclass 4, count 0 2006.257.20:12:09.83#ibcon#wrote, iclass 4, count 0 2006.257.20:12:09.83#ibcon#about to read 3, iclass 4, count 0 2006.257.20:12:09.87#ibcon#read 3, iclass 4, count 0 2006.257.20:12:09.87#ibcon#about to read 4, iclass 4, count 0 2006.257.20:12:09.87#ibcon#read 4, iclass 4, count 0 2006.257.20:12:09.87#ibcon#about to read 5, iclass 4, count 0 2006.257.20:12:09.87#ibcon#read 5, iclass 4, count 0 2006.257.20:12:09.87#ibcon#about to read 6, iclass 4, count 0 2006.257.20:12:09.87#ibcon#read 6, iclass 4, count 0 2006.257.20:12:09.87#ibcon#end of sib2, iclass 4, count 0 2006.257.20:12:09.87#ibcon#*after write, iclass 4, count 0 2006.257.20:12:09.87#ibcon#*before return 0, iclass 4, count 0 2006.257.20:12:09.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:09.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:12:09.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.20:12:09.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.20:12:09.87$vck44/vb=3,4 2006.257.20:12:09.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.20:12:09.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.20:12:09.87#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:09.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:09.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:09.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:09.93#ibcon#enter wrdev, iclass 6, count 2 2006.257.20:12:09.93#ibcon#first serial, iclass 6, count 2 2006.257.20:12:09.93#ibcon#enter sib2, iclass 6, count 2 2006.257.20:12:09.93#ibcon#flushed, iclass 6, count 2 2006.257.20:12:09.93#ibcon#about to write, iclass 6, count 2 2006.257.20:12:09.93#ibcon#wrote, iclass 6, count 2 2006.257.20:12:09.93#ibcon#about to read 3, iclass 6, count 2 2006.257.20:12:09.95#ibcon#read 3, iclass 6, count 2 2006.257.20:12:09.95#ibcon#about to read 4, iclass 6, count 2 2006.257.20:12:09.95#ibcon#read 4, iclass 6, count 2 2006.257.20:12:09.95#ibcon#about to read 5, iclass 6, count 2 2006.257.20:12:09.95#ibcon#read 5, iclass 6, count 2 2006.257.20:12:09.95#ibcon#about to read 6, iclass 6, count 2 2006.257.20:12:09.95#ibcon#read 6, iclass 6, count 2 2006.257.20:12:09.95#ibcon#end of sib2, iclass 6, count 2 2006.257.20:12:09.95#ibcon#*mode == 0, iclass 6, count 2 2006.257.20:12:09.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.20:12:09.95#ibcon#[27=AT03-04\r\n] 2006.257.20:12:09.95#ibcon#*before write, iclass 6, count 2 2006.257.20:12:09.95#ibcon#enter sib2, iclass 6, count 2 2006.257.20:12:09.95#ibcon#flushed, iclass 6, count 2 2006.257.20:12:09.95#ibcon#about to write, iclass 6, count 2 2006.257.20:12:09.95#ibcon#wrote, iclass 6, count 2 2006.257.20:12:09.95#ibcon#about to read 3, iclass 6, count 2 2006.257.20:12:09.98#ibcon#read 3, iclass 6, count 2 2006.257.20:12:09.98#ibcon#about to read 4, iclass 6, count 2 2006.257.20:12:09.98#ibcon#read 4, iclass 6, count 2 2006.257.20:12:09.98#ibcon#about to read 5, iclass 6, count 2 2006.257.20:12:09.98#ibcon#read 5, iclass 6, count 2 2006.257.20:12:09.98#ibcon#about to read 6, iclass 6, count 2 2006.257.20:12:09.98#ibcon#read 6, iclass 6, count 2 2006.257.20:12:09.98#ibcon#end of sib2, iclass 6, count 2 2006.257.20:12:09.98#ibcon#*after write, iclass 6, count 2 2006.257.20:12:09.98#ibcon#*before return 0, iclass 6, count 2 2006.257.20:12:09.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:09.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:12:09.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.20:12:09.98#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:09.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:10.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:10.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:10.10#ibcon#enter wrdev, iclass 6, count 0 2006.257.20:12:10.10#ibcon#first serial, iclass 6, count 0 2006.257.20:12:10.10#ibcon#enter sib2, iclass 6, count 0 2006.257.20:12:10.10#ibcon#flushed, iclass 6, count 0 2006.257.20:12:10.10#ibcon#about to write, iclass 6, count 0 2006.257.20:12:10.10#ibcon#wrote, iclass 6, count 0 2006.257.20:12:10.10#ibcon#about to read 3, iclass 6, count 0 2006.257.20:12:10.12#ibcon#read 3, iclass 6, count 0 2006.257.20:12:10.12#ibcon#about to read 4, iclass 6, count 0 2006.257.20:12:10.12#ibcon#read 4, iclass 6, count 0 2006.257.20:12:10.12#ibcon#about to read 5, iclass 6, count 0 2006.257.20:12:10.12#ibcon#read 5, iclass 6, count 0 2006.257.20:12:10.12#ibcon#about to read 6, iclass 6, count 0 2006.257.20:12:10.12#ibcon#read 6, iclass 6, count 0 2006.257.20:12:10.12#ibcon#end of sib2, iclass 6, count 0 2006.257.20:12:10.12#ibcon#*mode == 0, iclass 6, count 0 2006.257.20:12:10.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.20:12:10.12#ibcon#[27=USB\r\n] 2006.257.20:12:10.12#ibcon#*before write, iclass 6, count 0 2006.257.20:12:10.12#ibcon#enter sib2, iclass 6, count 0 2006.257.20:12:10.12#ibcon#flushed, iclass 6, count 0 2006.257.20:12:10.12#ibcon#about to write, iclass 6, count 0 2006.257.20:12:10.12#ibcon#wrote, iclass 6, count 0 2006.257.20:12:10.12#ibcon#about to read 3, iclass 6, count 0 2006.257.20:12:10.15#ibcon#read 3, iclass 6, count 0 2006.257.20:12:10.15#ibcon#about to read 4, iclass 6, count 0 2006.257.20:12:10.15#ibcon#read 4, iclass 6, count 0 2006.257.20:12:10.15#ibcon#about to read 5, iclass 6, count 0 2006.257.20:12:10.15#ibcon#read 5, iclass 6, count 0 2006.257.20:12:10.15#ibcon#about to read 6, iclass 6, count 0 2006.257.20:12:10.15#ibcon#read 6, iclass 6, count 0 2006.257.20:12:10.15#ibcon#end of sib2, iclass 6, count 0 2006.257.20:12:10.15#ibcon#*after write, iclass 6, count 0 2006.257.20:12:10.15#ibcon#*before return 0, iclass 6, count 0 2006.257.20:12:10.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:10.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:12:10.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.20:12:10.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.20:12:10.15$vck44/vblo=4,679.99 2006.257.20:12:10.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.20:12:10.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.20:12:10.15#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:10.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:10.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:10.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:10.15#ibcon#enter wrdev, iclass 10, count 0 2006.257.20:12:10.15#ibcon#first serial, iclass 10, count 0 2006.257.20:12:10.15#ibcon#enter sib2, iclass 10, count 0 2006.257.20:12:10.15#ibcon#flushed, iclass 10, count 0 2006.257.20:12:10.15#ibcon#about to write, iclass 10, count 0 2006.257.20:12:10.15#ibcon#wrote, iclass 10, count 0 2006.257.20:12:10.15#ibcon#about to read 3, iclass 10, count 0 2006.257.20:12:10.17#ibcon#read 3, iclass 10, count 0 2006.257.20:12:10.17#ibcon#about to read 4, iclass 10, count 0 2006.257.20:12:10.17#ibcon#read 4, iclass 10, count 0 2006.257.20:12:10.17#ibcon#about to read 5, iclass 10, count 0 2006.257.20:12:10.17#ibcon#read 5, iclass 10, count 0 2006.257.20:12:10.17#ibcon#about to read 6, iclass 10, count 0 2006.257.20:12:10.17#ibcon#read 6, iclass 10, count 0 2006.257.20:12:10.17#ibcon#end of sib2, iclass 10, count 0 2006.257.20:12:10.17#ibcon#*mode == 0, iclass 10, count 0 2006.257.20:12:10.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.20:12:10.17#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.20:12:10.17#ibcon#*before write, iclass 10, count 0 2006.257.20:12:10.17#ibcon#enter sib2, iclass 10, count 0 2006.257.20:12:10.17#ibcon#flushed, iclass 10, count 0 2006.257.20:12:10.17#ibcon#about to write, iclass 10, count 0 2006.257.20:12:10.17#ibcon#wrote, iclass 10, count 0 2006.257.20:12:10.17#ibcon#about to read 3, iclass 10, count 0 2006.257.20:12:10.21#ibcon#read 3, iclass 10, count 0 2006.257.20:12:10.21#ibcon#about to read 4, iclass 10, count 0 2006.257.20:12:10.21#ibcon#read 4, iclass 10, count 0 2006.257.20:12:10.21#ibcon#about to read 5, iclass 10, count 0 2006.257.20:12:10.21#ibcon#read 5, iclass 10, count 0 2006.257.20:12:10.21#ibcon#about to read 6, iclass 10, count 0 2006.257.20:12:10.21#ibcon#read 6, iclass 10, count 0 2006.257.20:12:10.21#ibcon#end of sib2, iclass 10, count 0 2006.257.20:12:10.21#ibcon#*after write, iclass 10, count 0 2006.257.20:12:10.21#ibcon#*before return 0, iclass 10, count 0 2006.257.20:12:10.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:10.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:12:10.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.20:12:10.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.20:12:10.21$vck44/vb=4,5 2006.257.20:12:10.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.20:12:10.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.20:12:10.21#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:10.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:10.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:10.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:10.27#ibcon#enter wrdev, iclass 12, count 2 2006.257.20:12:10.27#ibcon#first serial, iclass 12, count 2 2006.257.20:12:10.27#ibcon#enter sib2, iclass 12, count 2 2006.257.20:12:10.27#ibcon#flushed, iclass 12, count 2 2006.257.20:12:10.27#ibcon#about to write, iclass 12, count 2 2006.257.20:12:10.27#ibcon#wrote, iclass 12, count 2 2006.257.20:12:10.27#ibcon#about to read 3, iclass 12, count 2 2006.257.20:12:10.29#ibcon#read 3, iclass 12, count 2 2006.257.20:12:10.29#ibcon#about to read 4, iclass 12, count 2 2006.257.20:12:10.29#ibcon#read 4, iclass 12, count 2 2006.257.20:12:10.29#ibcon#about to read 5, iclass 12, count 2 2006.257.20:12:10.29#ibcon#read 5, iclass 12, count 2 2006.257.20:12:10.29#ibcon#about to read 6, iclass 12, count 2 2006.257.20:12:10.29#ibcon#read 6, iclass 12, count 2 2006.257.20:12:10.29#ibcon#end of sib2, iclass 12, count 2 2006.257.20:12:10.29#ibcon#*mode == 0, iclass 12, count 2 2006.257.20:12:10.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.20:12:10.29#ibcon#[27=AT04-05\r\n] 2006.257.20:12:10.29#ibcon#*before write, iclass 12, count 2 2006.257.20:12:10.29#ibcon#enter sib2, iclass 12, count 2 2006.257.20:12:10.29#ibcon#flushed, iclass 12, count 2 2006.257.20:12:10.29#ibcon#about to write, iclass 12, count 2 2006.257.20:12:10.29#ibcon#wrote, iclass 12, count 2 2006.257.20:12:10.29#ibcon#about to read 3, iclass 12, count 2 2006.257.20:12:10.32#ibcon#read 3, iclass 12, count 2 2006.257.20:12:10.32#ibcon#about to read 4, iclass 12, count 2 2006.257.20:12:10.32#ibcon#read 4, iclass 12, count 2 2006.257.20:12:10.32#ibcon#about to read 5, iclass 12, count 2 2006.257.20:12:10.32#ibcon#read 5, iclass 12, count 2 2006.257.20:12:10.32#ibcon#about to read 6, iclass 12, count 2 2006.257.20:12:10.32#ibcon#read 6, iclass 12, count 2 2006.257.20:12:10.32#ibcon#end of sib2, iclass 12, count 2 2006.257.20:12:10.32#ibcon#*after write, iclass 12, count 2 2006.257.20:12:10.32#ibcon#*before return 0, iclass 12, count 2 2006.257.20:12:10.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:10.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:12:10.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.20:12:10.32#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:10.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:10.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:10.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:10.44#ibcon#enter wrdev, iclass 12, count 0 2006.257.20:12:10.44#ibcon#first serial, iclass 12, count 0 2006.257.20:12:10.44#ibcon#enter sib2, iclass 12, count 0 2006.257.20:12:10.44#ibcon#flushed, iclass 12, count 0 2006.257.20:12:10.44#ibcon#about to write, iclass 12, count 0 2006.257.20:12:10.44#ibcon#wrote, iclass 12, count 0 2006.257.20:12:10.44#ibcon#about to read 3, iclass 12, count 0 2006.257.20:12:10.46#ibcon#read 3, iclass 12, count 0 2006.257.20:12:10.46#ibcon#about to read 4, iclass 12, count 0 2006.257.20:12:10.46#ibcon#read 4, iclass 12, count 0 2006.257.20:12:10.46#ibcon#about to read 5, iclass 12, count 0 2006.257.20:12:10.46#ibcon#read 5, iclass 12, count 0 2006.257.20:12:10.46#ibcon#about to read 6, iclass 12, count 0 2006.257.20:12:10.46#ibcon#read 6, iclass 12, count 0 2006.257.20:12:10.46#ibcon#end of sib2, iclass 12, count 0 2006.257.20:12:10.46#ibcon#*mode == 0, iclass 12, count 0 2006.257.20:12:10.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.20:12:10.46#ibcon#[27=USB\r\n] 2006.257.20:12:10.46#ibcon#*before write, iclass 12, count 0 2006.257.20:12:10.46#ibcon#enter sib2, iclass 12, count 0 2006.257.20:12:10.46#ibcon#flushed, iclass 12, count 0 2006.257.20:12:10.46#ibcon#about to write, iclass 12, count 0 2006.257.20:12:10.46#ibcon#wrote, iclass 12, count 0 2006.257.20:12:10.46#ibcon#about to read 3, iclass 12, count 0 2006.257.20:12:10.49#ibcon#read 3, iclass 12, count 0 2006.257.20:12:10.49#ibcon#about to read 4, iclass 12, count 0 2006.257.20:12:10.49#ibcon#read 4, iclass 12, count 0 2006.257.20:12:10.49#ibcon#about to read 5, iclass 12, count 0 2006.257.20:12:10.49#ibcon#read 5, iclass 12, count 0 2006.257.20:12:10.49#ibcon#about to read 6, iclass 12, count 0 2006.257.20:12:10.49#ibcon#read 6, iclass 12, count 0 2006.257.20:12:10.49#ibcon#end of sib2, iclass 12, count 0 2006.257.20:12:10.49#ibcon#*after write, iclass 12, count 0 2006.257.20:12:10.49#ibcon#*before return 0, iclass 12, count 0 2006.257.20:12:10.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:10.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:12:10.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.20:12:10.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.20:12:10.49$vck44/vblo=5,709.99 2006.257.20:12:10.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.20:12:10.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.20:12:10.49#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:10.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:12:10.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:12:10.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:12:10.49#ibcon#enter wrdev, iclass 14, count 0 2006.257.20:12:10.49#ibcon#first serial, iclass 14, count 0 2006.257.20:12:10.49#ibcon#enter sib2, iclass 14, count 0 2006.257.20:12:10.49#ibcon#flushed, iclass 14, count 0 2006.257.20:12:10.49#ibcon#about to write, iclass 14, count 0 2006.257.20:12:10.49#ibcon#wrote, iclass 14, count 0 2006.257.20:12:10.49#ibcon#about to read 3, iclass 14, count 0 2006.257.20:12:10.51#ibcon#read 3, iclass 14, count 0 2006.257.20:12:10.51#ibcon#about to read 4, iclass 14, count 0 2006.257.20:12:10.51#ibcon#read 4, iclass 14, count 0 2006.257.20:12:10.51#ibcon#about to read 5, iclass 14, count 0 2006.257.20:12:10.51#ibcon#read 5, iclass 14, count 0 2006.257.20:12:10.51#ibcon#about to read 6, iclass 14, count 0 2006.257.20:12:10.51#ibcon#read 6, iclass 14, count 0 2006.257.20:12:10.51#ibcon#end of sib2, iclass 14, count 0 2006.257.20:12:10.51#ibcon#*mode == 0, iclass 14, count 0 2006.257.20:12:10.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.20:12:10.51#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.20:12:10.51#ibcon#*before write, iclass 14, count 0 2006.257.20:12:10.51#ibcon#enter sib2, iclass 14, count 0 2006.257.20:12:10.51#ibcon#flushed, iclass 14, count 0 2006.257.20:12:10.51#ibcon#about to write, iclass 14, count 0 2006.257.20:12:10.51#ibcon#wrote, iclass 14, count 0 2006.257.20:12:10.51#ibcon#about to read 3, iclass 14, count 0 2006.257.20:12:10.55#ibcon#read 3, iclass 14, count 0 2006.257.20:12:10.55#ibcon#about to read 4, iclass 14, count 0 2006.257.20:12:10.55#ibcon#read 4, iclass 14, count 0 2006.257.20:12:10.55#ibcon#about to read 5, iclass 14, count 0 2006.257.20:12:10.55#ibcon#read 5, iclass 14, count 0 2006.257.20:12:10.55#ibcon#about to read 6, iclass 14, count 0 2006.257.20:12:10.55#ibcon#read 6, iclass 14, count 0 2006.257.20:12:10.55#ibcon#end of sib2, iclass 14, count 0 2006.257.20:12:10.55#ibcon#*after write, iclass 14, count 0 2006.257.20:12:10.55#ibcon#*before return 0, iclass 14, count 0 2006.257.20:12:10.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:12:10.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:12:10.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.20:12:10.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.20:12:10.55$vck44/vb=5,4 2006.257.20:12:10.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.20:12:10.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.20:12:10.55#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:10.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:12:10.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:12:10.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:12:10.61#ibcon#enter wrdev, iclass 16, count 2 2006.257.20:12:10.61#ibcon#first serial, iclass 16, count 2 2006.257.20:12:10.61#ibcon#enter sib2, iclass 16, count 2 2006.257.20:12:10.61#ibcon#flushed, iclass 16, count 2 2006.257.20:12:10.61#ibcon#about to write, iclass 16, count 2 2006.257.20:12:10.61#ibcon#wrote, iclass 16, count 2 2006.257.20:12:10.61#ibcon#about to read 3, iclass 16, count 2 2006.257.20:12:10.63#ibcon#read 3, iclass 16, count 2 2006.257.20:12:10.63#ibcon#about to read 4, iclass 16, count 2 2006.257.20:12:10.63#ibcon#read 4, iclass 16, count 2 2006.257.20:12:10.63#ibcon#about to read 5, iclass 16, count 2 2006.257.20:12:10.63#ibcon#read 5, iclass 16, count 2 2006.257.20:12:10.63#ibcon#about to read 6, iclass 16, count 2 2006.257.20:12:10.63#ibcon#read 6, iclass 16, count 2 2006.257.20:12:10.63#ibcon#end of sib2, iclass 16, count 2 2006.257.20:12:10.63#ibcon#*mode == 0, iclass 16, count 2 2006.257.20:12:10.63#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.20:12:10.63#ibcon#[27=AT05-04\r\n] 2006.257.20:12:10.63#ibcon#*before write, iclass 16, count 2 2006.257.20:12:10.63#ibcon#enter sib2, iclass 16, count 2 2006.257.20:12:10.63#ibcon#flushed, iclass 16, count 2 2006.257.20:12:10.63#ibcon#about to write, iclass 16, count 2 2006.257.20:12:10.63#ibcon#wrote, iclass 16, count 2 2006.257.20:12:10.63#ibcon#about to read 3, iclass 16, count 2 2006.257.20:12:10.66#ibcon#read 3, iclass 16, count 2 2006.257.20:12:10.66#ibcon#about to read 4, iclass 16, count 2 2006.257.20:12:10.66#ibcon#read 4, iclass 16, count 2 2006.257.20:12:10.66#ibcon#about to read 5, iclass 16, count 2 2006.257.20:12:10.66#ibcon#read 5, iclass 16, count 2 2006.257.20:12:10.66#ibcon#about to read 6, iclass 16, count 2 2006.257.20:12:10.66#ibcon#read 6, iclass 16, count 2 2006.257.20:12:10.66#ibcon#end of sib2, iclass 16, count 2 2006.257.20:12:10.66#ibcon#*after write, iclass 16, count 2 2006.257.20:12:10.66#ibcon#*before return 0, iclass 16, count 2 2006.257.20:12:10.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:12:10.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:12:10.66#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.20:12:10.66#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:10.66#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:12:10.78#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:12:10.78#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:12:10.78#ibcon#enter wrdev, iclass 16, count 0 2006.257.20:12:10.78#ibcon#first serial, iclass 16, count 0 2006.257.20:12:10.78#ibcon#enter sib2, iclass 16, count 0 2006.257.20:12:10.78#ibcon#flushed, iclass 16, count 0 2006.257.20:12:10.78#ibcon#about to write, iclass 16, count 0 2006.257.20:12:10.78#ibcon#wrote, iclass 16, count 0 2006.257.20:12:10.78#ibcon#about to read 3, iclass 16, count 0 2006.257.20:12:10.80#ibcon#read 3, iclass 16, count 0 2006.257.20:12:10.80#ibcon#about to read 4, iclass 16, count 0 2006.257.20:12:10.80#ibcon#read 4, iclass 16, count 0 2006.257.20:12:10.80#ibcon#about to read 5, iclass 16, count 0 2006.257.20:12:10.80#ibcon#read 5, iclass 16, count 0 2006.257.20:12:10.80#ibcon#about to read 6, iclass 16, count 0 2006.257.20:12:10.80#ibcon#read 6, iclass 16, count 0 2006.257.20:12:10.80#ibcon#end of sib2, iclass 16, count 0 2006.257.20:12:10.80#ibcon#*mode == 0, iclass 16, count 0 2006.257.20:12:10.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.20:12:10.80#ibcon#[27=USB\r\n] 2006.257.20:12:10.80#ibcon#*before write, iclass 16, count 0 2006.257.20:12:10.80#ibcon#enter sib2, iclass 16, count 0 2006.257.20:12:10.80#ibcon#flushed, iclass 16, count 0 2006.257.20:12:10.80#ibcon#about to write, iclass 16, count 0 2006.257.20:12:10.80#ibcon#wrote, iclass 16, count 0 2006.257.20:12:10.80#ibcon#about to read 3, iclass 16, count 0 2006.257.20:12:10.83#ibcon#read 3, iclass 16, count 0 2006.257.20:12:10.83#ibcon#about to read 4, iclass 16, count 0 2006.257.20:12:10.83#ibcon#read 4, iclass 16, count 0 2006.257.20:12:10.83#ibcon#about to read 5, iclass 16, count 0 2006.257.20:12:10.83#ibcon#read 5, iclass 16, count 0 2006.257.20:12:10.83#ibcon#about to read 6, iclass 16, count 0 2006.257.20:12:10.83#ibcon#read 6, iclass 16, count 0 2006.257.20:12:10.83#ibcon#end of sib2, iclass 16, count 0 2006.257.20:12:10.83#ibcon#*after write, iclass 16, count 0 2006.257.20:12:10.83#ibcon#*before return 0, iclass 16, count 0 2006.257.20:12:10.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:12:10.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:12:10.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.20:12:10.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.20:12:10.83$vck44/vblo=6,719.99 2006.257.20:12:10.83#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.20:12:10.83#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.20:12:10.83#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:10.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:12:10.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:12:10.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:12:10.83#ibcon#enter wrdev, iclass 18, count 0 2006.257.20:12:10.83#ibcon#first serial, iclass 18, count 0 2006.257.20:12:10.83#ibcon#enter sib2, iclass 18, count 0 2006.257.20:12:10.83#ibcon#flushed, iclass 18, count 0 2006.257.20:12:10.83#ibcon#about to write, iclass 18, count 0 2006.257.20:12:10.83#ibcon#wrote, iclass 18, count 0 2006.257.20:12:10.83#ibcon#about to read 3, iclass 18, count 0 2006.257.20:12:10.85#ibcon#read 3, iclass 18, count 0 2006.257.20:12:10.85#ibcon#about to read 4, iclass 18, count 0 2006.257.20:12:10.85#ibcon#read 4, iclass 18, count 0 2006.257.20:12:10.85#ibcon#about to read 5, iclass 18, count 0 2006.257.20:12:10.85#ibcon#read 5, iclass 18, count 0 2006.257.20:12:10.85#ibcon#about to read 6, iclass 18, count 0 2006.257.20:12:10.85#ibcon#read 6, iclass 18, count 0 2006.257.20:12:10.85#ibcon#end of sib2, iclass 18, count 0 2006.257.20:12:10.85#ibcon#*mode == 0, iclass 18, count 0 2006.257.20:12:10.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.20:12:10.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.20:12:10.85#ibcon#*before write, iclass 18, count 0 2006.257.20:12:10.85#ibcon#enter sib2, iclass 18, count 0 2006.257.20:12:10.85#ibcon#flushed, iclass 18, count 0 2006.257.20:12:10.85#ibcon#about to write, iclass 18, count 0 2006.257.20:12:10.85#ibcon#wrote, iclass 18, count 0 2006.257.20:12:10.85#ibcon#about to read 3, iclass 18, count 0 2006.257.20:12:10.89#ibcon#read 3, iclass 18, count 0 2006.257.20:12:10.89#ibcon#about to read 4, iclass 18, count 0 2006.257.20:12:10.89#ibcon#read 4, iclass 18, count 0 2006.257.20:12:10.89#ibcon#about to read 5, iclass 18, count 0 2006.257.20:12:10.89#ibcon#read 5, iclass 18, count 0 2006.257.20:12:10.89#ibcon#about to read 6, iclass 18, count 0 2006.257.20:12:10.89#ibcon#read 6, iclass 18, count 0 2006.257.20:12:10.89#ibcon#end of sib2, iclass 18, count 0 2006.257.20:12:10.89#ibcon#*after write, iclass 18, count 0 2006.257.20:12:10.89#ibcon#*before return 0, iclass 18, count 0 2006.257.20:12:10.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:12:10.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:12:10.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.20:12:10.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.20:12:10.89$vck44/vb=6,4 2006.257.20:12:10.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.20:12:10.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.20:12:10.89#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:10.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:10.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:10.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:10.95#ibcon#enter wrdev, iclass 20, count 2 2006.257.20:12:10.95#ibcon#first serial, iclass 20, count 2 2006.257.20:12:10.95#ibcon#enter sib2, iclass 20, count 2 2006.257.20:12:10.95#ibcon#flushed, iclass 20, count 2 2006.257.20:12:10.95#ibcon#about to write, iclass 20, count 2 2006.257.20:12:10.95#ibcon#wrote, iclass 20, count 2 2006.257.20:12:10.95#ibcon#about to read 3, iclass 20, count 2 2006.257.20:12:10.97#ibcon#read 3, iclass 20, count 2 2006.257.20:12:10.97#ibcon#about to read 4, iclass 20, count 2 2006.257.20:12:10.97#ibcon#read 4, iclass 20, count 2 2006.257.20:12:10.97#ibcon#about to read 5, iclass 20, count 2 2006.257.20:12:10.97#ibcon#read 5, iclass 20, count 2 2006.257.20:12:10.97#ibcon#about to read 6, iclass 20, count 2 2006.257.20:12:10.97#ibcon#read 6, iclass 20, count 2 2006.257.20:12:10.97#ibcon#end of sib2, iclass 20, count 2 2006.257.20:12:10.97#ibcon#*mode == 0, iclass 20, count 2 2006.257.20:12:10.97#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.20:12:10.97#ibcon#[27=AT06-04\r\n] 2006.257.20:12:10.97#ibcon#*before write, iclass 20, count 2 2006.257.20:12:10.97#ibcon#enter sib2, iclass 20, count 2 2006.257.20:12:10.97#ibcon#flushed, iclass 20, count 2 2006.257.20:12:10.97#ibcon#about to write, iclass 20, count 2 2006.257.20:12:10.97#ibcon#wrote, iclass 20, count 2 2006.257.20:12:10.97#ibcon#about to read 3, iclass 20, count 2 2006.257.20:12:11.00#ibcon#read 3, iclass 20, count 2 2006.257.20:12:11.00#ibcon#about to read 4, iclass 20, count 2 2006.257.20:12:11.00#ibcon#read 4, iclass 20, count 2 2006.257.20:12:11.00#ibcon#about to read 5, iclass 20, count 2 2006.257.20:12:11.00#ibcon#read 5, iclass 20, count 2 2006.257.20:12:11.00#ibcon#about to read 6, iclass 20, count 2 2006.257.20:12:11.00#ibcon#read 6, iclass 20, count 2 2006.257.20:12:11.00#ibcon#end of sib2, iclass 20, count 2 2006.257.20:12:11.00#ibcon#*after write, iclass 20, count 2 2006.257.20:12:11.00#ibcon#*before return 0, iclass 20, count 2 2006.257.20:12:11.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:11.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:12:11.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.20:12:11.00#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:11.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:11.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:11.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:11.12#ibcon#enter wrdev, iclass 20, count 0 2006.257.20:12:11.12#ibcon#first serial, iclass 20, count 0 2006.257.20:12:11.12#ibcon#enter sib2, iclass 20, count 0 2006.257.20:12:11.12#ibcon#flushed, iclass 20, count 0 2006.257.20:12:11.12#ibcon#about to write, iclass 20, count 0 2006.257.20:12:11.12#ibcon#wrote, iclass 20, count 0 2006.257.20:12:11.12#ibcon#about to read 3, iclass 20, count 0 2006.257.20:12:11.14#ibcon#read 3, iclass 20, count 0 2006.257.20:12:11.14#ibcon#about to read 4, iclass 20, count 0 2006.257.20:12:11.14#ibcon#read 4, iclass 20, count 0 2006.257.20:12:11.14#ibcon#about to read 5, iclass 20, count 0 2006.257.20:12:11.14#ibcon#read 5, iclass 20, count 0 2006.257.20:12:11.14#ibcon#about to read 6, iclass 20, count 0 2006.257.20:12:11.14#ibcon#read 6, iclass 20, count 0 2006.257.20:12:11.14#ibcon#end of sib2, iclass 20, count 0 2006.257.20:12:11.14#ibcon#*mode == 0, iclass 20, count 0 2006.257.20:12:11.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.20:12:11.14#ibcon#[27=USB\r\n] 2006.257.20:12:11.14#ibcon#*before write, iclass 20, count 0 2006.257.20:12:11.14#ibcon#enter sib2, iclass 20, count 0 2006.257.20:12:11.14#ibcon#flushed, iclass 20, count 0 2006.257.20:12:11.14#ibcon#about to write, iclass 20, count 0 2006.257.20:12:11.14#ibcon#wrote, iclass 20, count 0 2006.257.20:12:11.14#ibcon#about to read 3, iclass 20, count 0 2006.257.20:12:11.17#ibcon#read 3, iclass 20, count 0 2006.257.20:12:11.17#ibcon#about to read 4, iclass 20, count 0 2006.257.20:12:11.17#ibcon#read 4, iclass 20, count 0 2006.257.20:12:11.17#ibcon#about to read 5, iclass 20, count 0 2006.257.20:12:11.17#ibcon#read 5, iclass 20, count 0 2006.257.20:12:11.17#ibcon#about to read 6, iclass 20, count 0 2006.257.20:12:11.17#ibcon#read 6, iclass 20, count 0 2006.257.20:12:11.17#ibcon#end of sib2, iclass 20, count 0 2006.257.20:12:11.17#ibcon#*after write, iclass 20, count 0 2006.257.20:12:11.17#ibcon#*before return 0, iclass 20, count 0 2006.257.20:12:11.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:11.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:12:11.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.20:12:11.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.20:12:11.17$vck44/vblo=7,734.99 2006.257.20:12:11.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.20:12:11.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.20:12:11.17#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:11.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:11.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:11.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:11.17#ibcon#enter wrdev, iclass 22, count 0 2006.257.20:12:11.17#ibcon#first serial, iclass 22, count 0 2006.257.20:12:11.17#ibcon#enter sib2, iclass 22, count 0 2006.257.20:12:11.17#ibcon#flushed, iclass 22, count 0 2006.257.20:12:11.17#ibcon#about to write, iclass 22, count 0 2006.257.20:12:11.17#ibcon#wrote, iclass 22, count 0 2006.257.20:12:11.17#ibcon#about to read 3, iclass 22, count 0 2006.257.20:12:11.19#ibcon#read 3, iclass 22, count 0 2006.257.20:12:11.19#ibcon#about to read 4, iclass 22, count 0 2006.257.20:12:11.19#ibcon#read 4, iclass 22, count 0 2006.257.20:12:11.19#ibcon#about to read 5, iclass 22, count 0 2006.257.20:12:11.19#ibcon#read 5, iclass 22, count 0 2006.257.20:12:11.19#ibcon#about to read 6, iclass 22, count 0 2006.257.20:12:11.19#ibcon#read 6, iclass 22, count 0 2006.257.20:12:11.19#ibcon#end of sib2, iclass 22, count 0 2006.257.20:12:11.19#ibcon#*mode == 0, iclass 22, count 0 2006.257.20:12:11.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.20:12:11.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.20:12:11.19#ibcon#*before write, iclass 22, count 0 2006.257.20:12:11.19#ibcon#enter sib2, iclass 22, count 0 2006.257.20:12:11.19#ibcon#flushed, iclass 22, count 0 2006.257.20:12:11.19#ibcon#about to write, iclass 22, count 0 2006.257.20:12:11.19#ibcon#wrote, iclass 22, count 0 2006.257.20:12:11.19#ibcon#about to read 3, iclass 22, count 0 2006.257.20:12:11.23#ibcon#read 3, iclass 22, count 0 2006.257.20:12:11.23#ibcon#about to read 4, iclass 22, count 0 2006.257.20:12:11.23#ibcon#read 4, iclass 22, count 0 2006.257.20:12:11.23#ibcon#about to read 5, iclass 22, count 0 2006.257.20:12:11.23#ibcon#read 5, iclass 22, count 0 2006.257.20:12:11.23#ibcon#about to read 6, iclass 22, count 0 2006.257.20:12:11.23#ibcon#read 6, iclass 22, count 0 2006.257.20:12:11.23#ibcon#end of sib2, iclass 22, count 0 2006.257.20:12:11.23#ibcon#*after write, iclass 22, count 0 2006.257.20:12:11.23#ibcon#*before return 0, iclass 22, count 0 2006.257.20:12:11.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:11.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:12:11.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.20:12:11.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.20:12:11.23$vck44/vb=7,4 2006.257.20:12:11.23#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.20:12:11.23#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.20:12:11.23#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:11.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:11.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:11.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:11.29#ibcon#enter wrdev, iclass 24, count 2 2006.257.20:12:11.29#ibcon#first serial, iclass 24, count 2 2006.257.20:12:11.29#ibcon#enter sib2, iclass 24, count 2 2006.257.20:12:11.29#ibcon#flushed, iclass 24, count 2 2006.257.20:12:11.29#ibcon#about to write, iclass 24, count 2 2006.257.20:12:11.29#ibcon#wrote, iclass 24, count 2 2006.257.20:12:11.29#ibcon#about to read 3, iclass 24, count 2 2006.257.20:12:11.31#ibcon#read 3, iclass 24, count 2 2006.257.20:12:11.31#ibcon#about to read 4, iclass 24, count 2 2006.257.20:12:11.31#ibcon#read 4, iclass 24, count 2 2006.257.20:12:11.31#ibcon#about to read 5, iclass 24, count 2 2006.257.20:12:11.31#ibcon#read 5, iclass 24, count 2 2006.257.20:12:11.31#ibcon#about to read 6, iclass 24, count 2 2006.257.20:12:11.31#ibcon#read 6, iclass 24, count 2 2006.257.20:12:11.31#ibcon#end of sib2, iclass 24, count 2 2006.257.20:12:11.31#ibcon#*mode == 0, iclass 24, count 2 2006.257.20:12:11.31#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.20:12:11.31#ibcon#[27=AT07-04\r\n] 2006.257.20:12:11.31#ibcon#*before write, iclass 24, count 2 2006.257.20:12:11.31#ibcon#enter sib2, iclass 24, count 2 2006.257.20:12:11.31#ibcon#flushed, iclass 24, count 2 2006.257.20:12:11.31#ibcon#about to write, iclass 24, count 2 2006.257.20:12:11.31#ibcon#wrote, iclass 24, count 2 2006.257.20:12:11.31#ibcon#about to read 3, iclass 24, count 2 2006.257.20:12:11.34#ibcon#read 3, iclass 24, count 2 2006.257.20:12:11.34#ibcon#about to read 4, iclass 24, count 2 2006.257.20:12:11.34#ibcon#read 4, iclass 24, count 2 2006.257.20:12:11.34#ibcon#about to read 5, iclass 24, count 2 2006.257.20:12:11.34#ibcon#read 5, iclass 24, count 2 2006.257.20:12:11.34#ibcon#about to read 6, iclass 24, count 2 2006.257.20:12:11.34#ibcon#read 6, iclass 24, count 2 2006.257.20:12:11.34#ibcon#end of sib2, iclass 24, count 2 2006.257.20:12:11.34#ibcon#*after write, iclass 24, count 2 2006.257.20:12:11.34#ibcon#*before return 0, iclass 24, count 2 2006.257.20:12:11.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:11.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:12:11.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.20:12:11.34#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:11.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:11.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:11.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:11.46#ibcon#enter wrdev, iclass 24, count 0 2006.257.20:12:11.46#ibcon#first serial, iclass 24, count 0 2006.257.20:12:11.46#ibcon#enter sib2, iclass 24, count 0 2006.257.20:12:11.46#ibcon#flushed, iclass 24, count 0 2006.257.20:12:11.46#ibcon#about to write, iclass 24, count 0 2006.257.20:12:11.46#ibcon#wrote, iclass 24, count 0 2006.257.20:12:11.46#ibcon#about to read 3, iclass 24, count 0 2006.257.20:12:11.48#ibcon#read 3, iclass 24, count 0 2006.257.20:12:11.48#ibcon#about to read 4, iclass 24, count 0 2006.257.20:12:11.48#ibcon#read 4, iclass 24, count 0 2006.257.20:12:11.48#ibcon#about to read 5, iclass 24, count 0 2006.257.20:12:11.48#ibcon#read 5, iclass 24, count 0 2006.257.20:12:11.48#ibcon#about to read 6, iclass 24, count 0 2006.257.20:12:11.48#ibcon#read 6, iclass 24, count 0 2006.257.20:12:11.48#ibcon#end of sib2, iclass 24, count 0 2006.257.20:12:11.48#ibcon#*mode == 0, iclass 24, count 0 2006.257.20:12:11.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.20:12:11.48#ibcon#[27=USB\r\n] 2006.257.20:12:11.48#ibcon#*before write, iclass 24, count 0 2006.257.20:12:11.48#ibcon#enter sib2, iclass 24, count 0 2006.257.20:12:11.48#ibcon#flushed, iclass 24, count 0 2006.257.20:12:11.48#ibcon#about to write, iclass 24, count 0 2006.257.20:12:11.48#ibcon#wrote, iclass 24, count 0 2006.257.20:12:11.48#ibcon#about to read 3, iclass 24, count 0 2006.257.20:12:11.51#ibcon#read 3, iclass 24, count 0 2006.257.20:12:11.51#ibcon#about to read 4, iclass 24, count 0 2006.257.20:12:11.51#ibcon#read 4, iclass 24, count 0 2006.257.20:12:11.51#ibcon#about to read 5, iclass 24, count 0 2006.257.20:12:11.51#ibcon#read 5, iclass 24, count 0 2006.257.20:12:11.51#ibcon#about to read 6, iclass 24, count 0 2006.257.20:12:11.51#ibcon#read 6, iclass 24, count 0 2006.257.20:12:11.51#ibcon#end of sib2, iclass 24, count 0 2006.257.20:12:11.51#ibcon#*after write, iclass 24, count 0 2006.257.20:12:11.51#ibcon#*before return 0, iclass 24, count 0 2006.257.20:12:11.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:11.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:12:11.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.20:12:11.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.20:12:11.51$vck44/vblo=8,744.99 2006.257.20:12:11.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.20:12:11.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.20:12:11.51#ibcon#ireg 17 cls_cnt 0 2006.257.20:12:11.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:11.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:11.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:11.51#ibcon#enter wrdev, iclass 26, count 0 2006.257.20:12:11.51#ibcon#first serial, iclass 26, count 0 2006.257.20:12:11.51#ibcon#enter sib2, iclass 26, count 0 2006.257.20:12:11.51#ibcon#flushed, iclass 26, count 0 2006.257.20:12:11.51#ibcon#about to write, iclass 26, count 0 2006.257.20:12:11.51#ibcon#wrote, iclass 26, count 0 2006.257.20:12:11.51#ibcon#about to read 3, iclass 26, count 0 2006.257.20:12:11.53#ibcon#read 3, iclass 26, count 0 2006.257.20:12:11.53#ibcon#about to read 4, iclass 26, count 0 2006.257.20:12:11.53#ibcon#read 4, iclass 26, count 0 2006.257.20:12:11.53#ibcon#about to read 5, iclass 26, count 0 2006.257.20:12:11.53#ibcon#read 5, iclass 26, count 0 2006.257.20:12:11.53#ibcon#about to read 6, iclass 26, count 0 2006.257.20:12:11.53#ibcon#read 6, iclass 26, count 0 2006.257.20:12:11.53#ibcon#end of sib2, iclass 26, count 0 2006.257.20:12:11.53#ibcon#*mode == 0, iclass 26, count 0 2006.257.20:12:11.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.20:12:11.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.20:12:11.53#ibcon#*before write, iclass 26, count 0 2006.257.20:12:11.53#ibcon#enter sib2, iclass 26, count 0 2006.257.20:12:11.53#ibcon#flushed, iclass 26, count 0 2006.257.20:12:11.53#ibcon#about to write, iclass 26, count 0 2006.257.20:12:11.53#ibcon#wrote, iclass 26, count 0 2006.257.20:12:11.53#ibcon#about to read 3, iclass 26, count 0 2006.257.20:12:11.57#ibcon#read 3, iclass 26, count 0 2006.257.20:12:11.57#ibcon#about to read 4, iclass 26, count 0 2006.257.20:12:11.57#ibcon#read 4, iclass 26, count 0 2006.257.20:12:11.57#ibcon#about to read 5, iclass 26, count 0 2006.257.20:12:11.57#ibcon#read 5, iclass 26, count 0 2006.257.20:12:11.57#ibcon#about to read 6, iclass 26, count 0 2006.257.20:12:11.57#ibcon#read 6, iclass 26, count 0 2006.257.20:12:11.57#ibcon#end of sib2, iclass 26, count 0 2006.257.20:12:11.57#ibcon#*after write, iclass 26, count 0 2006.257.20:12:11.57#ibcon#*before return 0, iclass 26, count 0 2006.257.20:12:11.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:11.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:12:11.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.20:12:11.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.20:12:11.57$vck44/vb=8,4 2006.257.20:12:11.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.20:12:11.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.20:12:11.57#ibcon#ireg 11 cls_cnt 2 2006.257.20:12:11.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:11.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:11.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:11.63#ibcon#enter wrdev, iclass 28, count 2 2006.257.20:12:11.63#ibcon#first serial, iclass 28, count 2 2006.257.20:12:11.63#ibcon#enter sib2, iclass 28, count 2 2006.257.20:12:11.63#ibcon#flushed, iclass 28, count 2 2006.257.20:12:11.63#ibcon#about to write, iclass 28, count 2 2006.257.20:12:11.63#ibcon#wrote, iclass 28, count 2 2006.257.20:12:11.63#ibcon#about to read 3, iclass 28, count 2 2006.257.20:12:11.65#ibcon#read 3, iclass 28, count 2 2006.257.20:12:11.65#ibcon#about to read 4, iclass 28, count 2 2006.257.20:12:11.65#ibcon#read 4, iclass 28, count 2 2006.257.20:12:11.65#ibcon#about to read 5, iclass 28, count 2 2006.257.20:12:11.65#ibcon#read 5, iclass 28, count 2 2006.257.20:12:11.65#ibcon#about to read 6, iclass 28, count 2 2006.257.20:12:11.65#ibcon#read 6, iclass 28, count 2 2006.257.20:12:11.65#ibcon#end of sib2, iclass 28, count 2 2006.257.20:12:11.65#ibcon#*mode == 0, iclass 28, count 2 2006.257.20:12:11.65#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.20:12:11.65#ibcon#[27=AT08-04\r\n] 2006.257.20:12:11.65#ibcon#*before write, iclass 28, count 2 2006.257.20:12:11.65#ibcon#enter sib2, iclass 28, count 2 2006.257.20:12:11.65#ibcon#flushed, iclass 28, count 2 2006.257.20:12:11.65#ibcon#about to write, iclass 28, count 2 2006.257.20:12:11.65#ibcon#wrote, iclass 28, count 2 2006.257.20:12:11.65#ibcon#about to read 3, iclass 28, count 2 2006.257.20:12:11.68#ibcon#read 3, iclass 28, count 2 2006.257.20:12:11.68#ibcon#about to read 4, iclass 28, count 2 2006.257.20:12:11.68#ibcon#read 4, iclass 28, count 2 2006.257.20:12:11.68#ibcon#about to read 5, iclass 28, count 2 2006.257.20:12:11.68#ibcon#read 5, iclass 28, count 2 2006.257.20:12:11.68#ibcon#about to read 6, iclass 28, count 2 2006.257.20:12:11.68#ibcon#read 6, iclass 28, count 2 2006.257.20:12:11.68#ibcon#end of sib2, iclass 28, count 2 2006.257.20:12:11.68#ibcon#*after write, iclass 28, count 2 2006.257.20:12:11.68#ibcon#*before return 0, iclass 28, count 2 2006.257.20:12:11.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:11.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:12:11.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.20:12:11.68#ibcon#ireg 7 cls_cnt 0 2006.257.20:12:11.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:11.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:11.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:11.80#ibcon#enter wrdev, iclass 28, count 0 2006.257.20:12:11.80#ibcon#first serial, iclass 28, count 0 2006.257.20:12:11.80#ibcon#enter sib2, iclass 28, count 0 2006.257.20:12:11.80#ibcon#flushed, iclass 28, count 0 2006.257.20:12:11.80#ibcon#about to write, iclass 28, count 0 2006.257.20:12:11.80#ibcon#wrote, iclass 28, count 0 2006.257.20:12:11.80#ibcon#about to read 3, iclass 28, count 0 2006.257.20:12:11.82#ibcon#read 3, iclass 28, count 0 2006.257.20:12:11.82#ibcon#about to read 4, iclass 28, count 0 2006.257.20:12:11.82#ibcon#read 4, iclass 28, count 0 2006.257.20:12:11.82#ibcon#about to read 5, iclass 28, count 0 2006.257.20:12:11.82#ibcon#read 5, iclass 28, count 0 2006.257.20:12:11.82#ibcon#about to read 6, iclass 28, count 0 2006.257.20:12:11.82#ibcon#read 6, iclass 28, count 0 2006.257.20:12:11.82#ibcon#end of sib2, iclass 28, count 0 2006.257.20:12:11.82#ibcon#*mode == 0, iclass 28, count 0 2006.257.20:12:11.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.20:12:11.82#ibcon#[27=USB\r\n] 2006.257.20:12:11.82#ibcon#*before write, iclass 28, count 0 2006.257.20:12:11.82#ibcon#enter sib2, iclass 28, count 0 2006.257.20:12:11.82#ibcon#flushed, iclass 28, count 0 2006.257.20:12:11.82#ibcon#about to write, iclass 28, count 0 2006.257.20:12:11.82#ibcon#wrote, iclass 28, count 0 2006.257.20:12:11.82#ibcon#about to read 3, iclass 28, count 0 2006.257.20:12:11.85#ibcon#read 3, iclass 28, count 0 2006.257.20:12:11.85#ibcon#about to read 4, iclass 28, count 0 2006.257.20:12:11.85#ibcon#read 4, iclass 28, count 0 2006.257.20:12:11.85#ibcon#about to read 5, iclass 28, count 0 2006.257.20:12:11.85#ibcon#read 5, iclass 28, count 0 2006.257.20:12:11.85#ibcon#about to read 6, iclass 28, count 0 2006.257.20:12:11.85#ibcon#read 6, iclass 28, count 0 2006.257.20:12:11.85#ibcon#end of sib2, iclass 28, count 0 2006.257.20:12:11.85#ibcon#*after write, iclass 28, count 0 2006.257.20:12:11.85#ibcon#*before return 0, iclass 28, count 0 2006.257.20:12:11.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:11.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:12:11.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.20:12:11.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.20:12:11.85$vck44/vabw=wide 2006.257.20:12:11.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.20:12:11.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.20:12:11.85#ibcon#ireg 8 cls_cnt 0 2006.257.20:12:11.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:11.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:11.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:11.85#ibcon#enter wrdev, iclass 30, count 0 2006.257.20:12:11.85#ibcon#first serial, iclass 30, count 0 2006.257.20:12:11.85#ibcon#enter sib2, iclass 30, count 0 2006.257.20:12:11.85#ibcon#flushed, iclass 30, count 0 2006.257.20:12:11.85#ibcon#about to write, iclass 30, count 0 2006.257.20:12:11.85#ibcon#wrote, iclass 30, count 0 2006.257.20:12:11.85#ibcon#about to read 3, iclass 30, count 0 2006.257.20:12:11.87#ibcon#read 3, iclass 30, count 0 2006.257.20:12:11.87#ibcon#about to read 4, iclass 30, count 0 2006.257.20:12:11.87#ibcon#read 4, iclass 30, count 0 2006.257.20:12:11.87#ibcon#about to read 5, iclass 30, count 0 2006.257.20:12:11.87#ibcon#read 5, iclass 30, count 0 2006.257.20:12:11.87#ibcon#about to read 6, iclass 30, count 0 2006.257.20:12:11.87#ibcon#read 6, iclass 30, count 0 2006.257.20:12:11.87#ibcon#end of sib2, iclass 30, count 0 2006.257.20:12:11.87#ibcon#*mode == 0, iclass 30, count 0 2006.257.20:12:11.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.20:12:11.87#ibcon#[25=BW32\r\n] 2006.257.20:12:11.87#ibcon#*before write, iclass 30, count 0 2006.257.20:12:11.87#ibcon#enter sib2, iclass 30, count 0 2006.257.20:12:11.87#ibcon#flushed, iclass 30, count 0 2006.257.20:12:11.87#ibcon#about to write, iclass 30, count 0 2006.257.20:12:11.87#ibcon#wrote, iclass 30, count 0 2006.257.20:12:11.87#ibcon#about to read 3, iclass 30, count 0 2006.257.20:12:11.90#ibcon#read 3, iclass 30, count 0 2006.257.20:12:11.90#ibcon#about to read 4, iclass 30, count 0 2006.257.20:12:11.90#ibcon#read 4, iclass 30, count 0 2006.257.20:12:11.90#ibcon#about to read 5, iclass 30, count 0 2006.257.20:12:11.90#ibcon#read 5, iclass 30, count 0 2006.257.20:12:11.90#ibcon#about to read 6, iclass 30, count 0 2006.257.20:12:11.90#ibcon#read 6, iclass 30, count 0 2006.257.20:12:11.90#ibcon#end of sib2, iclass 30, count 0 2006.257.20:12:11.90#ibcon#*after write, iclass 30, count 0 2006.257.20:12:11.90#ibcon#*before return 0, iclass 30, count 0 2006.257.20:12:11.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:11.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:12:11.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.20:12:11.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.20:12:11.90$vck44/vbbw=wide 2006.257.20:12:11.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.20:12:11.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.20:12:11.90#ibcon#ireg 8 cls_cnt 0 2006.257.20:12:11.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:12:11.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:12:11.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:12:11.97#ibcon#enter wrdev, iclass 32, count 0 2006.257.20:12:11.97#ibcon#first serial, iclass 32, count 0 2006.257.20:12:11.97#ibcon#enter sib2, iclass 32, count 0 2006.257.20:12:11.97#ibcon#flushed, iclass 32, count 0 2006.257.20:12:11.97#ibcon#about to write, iclass 32, count 0 2006.257.20:12:11.97#ibcon#wrote, iclass 32, count 0 2006.257.20:12:11.97#ibcon#about to read 3, iclass 32, count 0 2006.257.20:12:11.99#ibcon#read 3, iclass 32, count 0 2006.257.20:12:11.99#ibcon#about to read 4, iclass 32, count 0 2006.257.20:12:11.99#ibcon#read 4, iclass 32, count 0 2006.257.20:12:11.99#ibcon#about to read 5, iclass 32, count 0 2006.257.20:12:11.99#ibcon#read 5, iclass 32, count 0 2006.257.20:12:11.99#ibcon#about to read 6, iclass 32, count 0 2006.257.20:12:11.99#ibcon#read 6, iclass 32, count 0 2006.257.20:12:11.99#ibcon#end of sib2, iclass 32, count 0 2006.257.20:12:11.99#ibcon#*mode == 0, iclass 32, count 0 2006.257.20:12:11.99#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.20:12:11.99#ibcon#[27=BW32\r\n] 2006.257.20:12:11.99#ibcon#*before write, iclass 32, count 0 2006.257.20:12:11.99#ibcon#enter sib2, iclass 32, count 0 2006.257.20:12:11.99#ibcon#flushed, iclass 32, count 0 2006.257.20:12:11.99#ibcon#about to write, iclass 32, count 0 2006.257.20:12:11.99#ibcon#wrote, iclass 32, count 0 2006.257.20:12:11.99#ibcon#about to read 3, iclass 32, count 0 2006.257.20:12:12.02#ibcon#read 3, iclass 32, count 0 2006.257.20:12:12.02#ibcon#about to read 4, iclass 32, count 0 2006.257.20:12:12.02#ibcon#read 4, iclass 32, count 0 2006.257.20:12:12.02#ibcon#about to read 5, iclass 32, count 0 2006.257.20:12:12.02#ibcon#read 5, iclass 32, count 0 2006.257.20:12:12.02#ibcon#about to read 6, iclass 32, count 0 2006.257.20:12:12.02#ibcon#read 6, iclass 32, count 0 2006.257.20:12:12.02#ibcon#end of sib2, iclass 32, count 0 2006.257.20:12:12.02#ibcon#*after write, iclass 32, count 0 2006.257.20:12:12.02#ibcon#*before return 0, iclass 32, count 0 2006.257.20:12:12.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:12:12.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:12:12.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.20:12:12.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.20:12:12.02$setupk4/ifdk4 2006.257.20:12:12.02$ifdk4/lo= 2006.257.20:12:12.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.20:12:12.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.20:12:12.02$ifdk4/patch= 2006.257.20:12:12.02$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.20:12:12.02$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.20:12:12.02$setupk4/!*+20s 2006.257.20:12:17.96#abcon#<5=/14 1.0 2.3 17.23 971014.7\r\n> 2006.257.20:12:17.98#abcon#{5=INTERFACE CLEAR} 2006.257.20:12:18.04#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:12:18.14#trakl#Source acquired 2006.257.20:12:20.14#flagr#flagr/antenna,acquired 2006.257.20:12:26.53$setupk4/"tpicd 2006.257.20:12:26.53$setupk4/echo=off 2006.257.20:12:26.53$setupk4/xlog=off 2006.257.20:12:26.53:!2006.257.20:14:54 2006.257.20:14:54.00:preob 2006.257.20:14:54.14/onsource/TRACKING 2006.257.20:14:54.14:!2006.257.20:15:04 2006.257.20:15:04.00:"tape 2006.257.20:15:04.00:"st=record 2006.257.20:15:04.00:data_valid=on 2006.257.20:15:04.00:midob 2006.257.20:15:05.14/onsource/TRACKING 2006.257.20:15:05.14/wx/17.20,1014.7,97 2006.257.20:15:05.19/cable/+6.4846E-03 2006.257.20:15:06.28/va/01,08,usb,yes,31,33 2006.257.20:15:06.28/va/02,07,usb,yes,33,34 2006.257.20:15:06.28/va/03,08,usb,yes,30,32 2006.257.20:15:06.28/va/04,07,usb,yes,34,36 2006.257.20:15:06.28/va/05,04,usb,yes,31,31 2006.257.20:15:06.28/va/06,04,usb,yes,34,34 2006.257.20:15:06.28/va/07,04,usb,yes,35,35 2006.257.20:15:06.28/va/08,04,usb,yes,29,36 2006.257.20:15:06.51/valo/01,524.99,yes,locked 2006.257.20:15:06.51/valo/02,534.99,yes,locked 2006.257.20:15:06.51/valo/03,564.99,yes,locked 2006.257.20:15:06.51/valo/04,624.99,yes,locked 2006.257.20:15:06.51/valo/05,734.99,yes,locked 2006.257.20:15:06.51/valo/06,814.99,yes,locked 2006.257.20:15:06.51/valo/07,864.99,yes,locked 2006.257.20:15:06.51/valo/08,884.99,yes,locked 2006.257.20:15:07.60/vb/01,04,usb,yes,30,28 2006.257.20:15:07.60/vb/02,05,usb,yes,28,28 2006.257.20:15:07.60/vb/03,04,usb,yes,29,32 2006.257.20:15:07.60/vb/04,05,usb,yes,29,28 2006.257.20:15:07.60/vb/05,04,usb,yes,26,28 2006.257.20:15:07.60/vb/06,04,usb,yes,30,27 2006.257.20:15:07.60/vb/07,04,usb,yes,30,30 2006.257.20:15:07.60/vb/08,04,usb,yes,28,31 2006.257.20:15:07.84/vblo/01,629.99,yes,locked 2006.257.20:15:07.84/vblo/02,634.99,yes,locked 2006.257.20:15:07.84/vblo/03,649.99,yes,locked 2006.257.20:15:07.84/vblo/04,679.99,yes,locked 2006.257.20:15:07.84/vblo/05,709.99,yes,locked 2006.257.20:15:07.84/vblo/06,719.99,yes,locked 2006.257.20:15:07.84/vblo/07,734.99,yes,locked 2006.257.20:15:07.84/vblo/08,744.99,yes,locked 2006.257.20:15:07.99/vabw/8 2006.257.20:15:08.14/vbbw/8 2006.257.20:15:08.23/xfe/off,on,15.2 2006.257.20:15:08.61/ifatt/23,28,28,28 2006.257.20:15:09.07/fmout-gps/S +4.53E-07 2006.257.20:15:09.11:!2006.257.20:22:24 2006.257.20:22:24.00:data_valid=off 2006.257.20:22:24.00:"et 2006.257.20:22:24.00:!+3s 2006.257.20:22:27.01:"tape 2006.257.20:22:27.01:postob 2006.257.20:22:27.20/cable/+6.4839E-03 2006.257.20:22:27.20/wx/17.14,1014.8,97 2006.257.20:22:28.08/fmout-gps/S +4.56E-07 2006.257.20:22:28.08:scan_name=257-2028,jd0609,300 2006.257.20:22:28.08:source=oj287,085448.87,200630.6,2000.0,ccw 2006.257.20:22:29.14#flagr#flagr/antenna,new-source 2006.257.20:22:29.14:checkk5 2006.257.20:22:29.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.20:22:29.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.20:22:30.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.20:22:30.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.20:22:30.86/chk_obsdata//k5ts1/T2572015??a.dat file size is correct (nominal:1760MB, actual:1756MB). 2006.257.20:22:31.20/chk_obsdata//k5ts2/T2572015??b.dat file size is correct (nominal:1760MB, actual:1756MB). 2006.257.20:22:31.54/chk_obsdata//k5ts3/T2572015??c.dat file size is correct (nominal:1760MB, actual:1756MB). 2006.257.20:22:31.87/chk_obsdata//k5ts4/T2572015??d.dat file size is correct (nominal:1760MB, actual:1756MB). 2006.257.20:22:32.54/k5log//k5ts1_log_newline 2006.257.20:22:33.19/k5log//k5ts2_log_newline 2006.257.20:22:33.84/k5log//k5ts3_log_newline 2006.257.20:22:34.50/k5log//k5ts4_log_newline 2006.257.20:22:34.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.20:22:34.52:setupk4=1 2006.257.20:22:34.52$setupk4/echo=on 2006.257.20:22:34.52$setupk4/pcalon 2006.257.20:22:34.52$pcalon/"no phase cal control is implemented here 2006.257.20:22:34.52$setupk4/"tpicd=stop 2006.257.20:22:34.52$setupk4/"rec=synch_on 2006.257.20:22:34.52$setupk4/"rec_mode=128 2006.257.20:22:34.53$setupk4/!* 2006.257.20:22:34.53$setupk4/recpk4 2006.257.20:22:34.53$recpk4/recpatch= 2006.257.20:22:34.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.20:22:34.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.20:22:34.53$setupk4/vck44 2006.257.20:22:34.53$vck44/valo=1,524.99 2006.257.20:22:34.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.20:22:34.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.20:22:34.53#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:34.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:34.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:34.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:34.53#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:22:34.53#ibcon#first serial, iclass 29, count 0 2006.257.20:22:34.53#ibcon#enter sib2, iclass 29, count 0 2006.257.20:22:34.53#ibcon#flushed, iclass 29, count 0 2006.257.20:22:34.53#ibcon#about to write, iclass 29, count 0 2006.257.20:22:34.53#ibcon#wrote, iclass 29, count 0 2006.257.20:22:34.53#ibcon#about to read 3, iclass 29, count 0 2006.257.20:22:34.55#ibcon#read 3, iclass 29, count 0 2006.257.20:22:34.55#ibcon#about to read 4, iclass 29, count 0 2006.257.20:22:34.55#ibcon#read 4, iclass 29, count 0 2006.257.20:22:34.55#ibcon#about to read 5, iclass 29, count 0 2006.257.20:22:34.55#ibcon#read 5, iclass 29, count 0 2006.257.20:22:34.55#ibcon#about to read 6, iclass 29, count 0 2006.257.20:22:34.55#ibcon#read 6, iclass 29, count 0 2006.257.20:22:34.55#ibcon#end of sib2, iclass 29, count 0 2006.257.20:22:34.55#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:22:34.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:22:34.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.20:22:34.55#ibcon#*before write, iclass 29, count 0 2006.257.20:22:34.55#ibcon#enter sib2, iclass 29, count 0 2006.257.20:22:34.55#ibcon#flushed, iclass 29, count 0 2006.257.20:22:34.55#ibcon#about to write, iclass 29, count 0 2006.257.20:22:34.55#ibcon#wrote, iclass 29, count 0 2006.257.20:22:34.55#ibcon#about to read 3, iclass 29, count 0 2006.257.20:22:34.60#ibcon#read 3, iclass 29, count 0 2006.257.20:22:34.60#ibcon#about to read 4, iclass 29, count 0 2006.257.20:22:34.60#ibcon#read 4, iclass 29, count 0 2006.257.20:22:34.60#ibcon#about to read 5, iclass 29, count 0 2006.257.20:22:34.60#ibcon#read 5, iclass 29, count 0 2006.257.20:22:34.60#ibcon#about to read 6, iclass 29, count 0 2006.257.20:22:34.60#ibcon#read 6, iclass 29, count 0 2006.257.20:22:34.60#ibcon#end of sib2, iclass 29, count 0 2006.257.20:22:34.60#ibcon#*after write, iclass 29, count 0 2006.257.20:22:34.60#ibcon#*before return 0, iclass 29, count 0 2006.257.20:22:34.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:34.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:34.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:22:34.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:22:34.60$vck44/va=1,8 2006.257.20:22:34.60#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.20:22:34.60#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.20:22:34.60#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:34.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:34.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:34.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:34.60#ibcon#enter wrdev, iclass 31, count 2 2006.257.20:22:34.60#ibcon#first serial, iclass 31, count 2 2006.257.20:22:34.60#ibcon#enter sib2, iclass 31, count 2 2006.257.20:22:34.60#ibcon#flushed, iclass 31, count 2 2006.257.20:22:34.60#ibcon#about to write, iclass 31, count 2 2006.257.20:22:34.60#ibcon#wrote, iclass 31, count 2 2006.257.20:22:34.60#ibcon#about to read 3, iclass 31, count 2 2006.257.20:22:34.62#ibcon#read 3, iclass 31, count 2 2006.257.20:22:34.62#ibcon#about to read 4, iclass 31, count 2 2006.257.20:22:34.62#ibcon#read 4, iclass 31, count 2 2006.257.20:22:34.62#ibcon#about to read 5, iclass 31, count 2 2006.257.20:22:34.62#ibcon#read 5, iclass 31, count 2 2006.257.20:22:34.62#ibcon#about to read 6, iclass 31, count 2 2006.257.20:22:34.62#ibcon#read 6, iclass 31, count 2 2006.257.20:22:34.62#ibcon#end of sib2, iclass 31, count 2 2006.257.20:22:34.62#ibcon#*mode == 0, iclass 31, count 2 2006.257.20:22:34.62#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.20:22:34.62#ibcon#[25=AT01-08\r\n] 2006.257.20:22:34.62#ibcon#*before write, iclass 31, count 2 2006.257.20:22:34.62#ibcon#enter sib2, iclass 31, count 2 2006.257.20:22:34.62#ibcon#flushed, iclass 31, count 2 2006.257.20:22:34.62#ibcon#about to write, iclass 31, count 2 2006.257.20:22:34.62#ibcon#wrote, iclass 31, count 2 2006.257.20:22:34.62#ibcon#about to read 3, iclass 31, count 2 2006.257.20:22:34.65#ibcon#read 3, iclass 31, count 2 2006.257.20:22:34.65#ibcon#about to read 4, iclass 31, count 2 2006.257.20:22:34.65#ibcon#read 4, iclass 31, count 2 2006.257.20:22:34.65#ibcon#about to read 5, iclass 31, count 2 2006.257.20:22:34.65#ibcon#read 5, iclass 31, count 2 2006.257.20:22:34.65#ibcon#about to read 6, iclass 31, count 2 2006.257.20:22:34.65#ibcon#read 6, iclass 31, count 2 2006.257.20:22:34.65#ibcon#end of sib2, iclass 31, count 2 2006.257.20:22:34.65#ibcon#*after write, iclass 31, count 2 2006.257.20:22:34.65#ibcon#*before return 0, iclass 31, count 2 2006.257.20:22:34.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:34.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:34.65#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.20:22:34.65#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:34.65#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:34.77#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:34.77#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:34.77#ibcon#enter wrdev, iclass 31, count 0 2006.257.20:22:34.77#ibcon#first serial, iclass 31, count 0 2006.257.20:22:34.77#ibcon#enter sib2, iclass 31, count 0 2006.257.20:22:34.77#ibcon#flushed, iclass 31, count 0 2006.257.20:22:34.77#ibcon#about to write, iclass 31, count 0 2006.257.20:22:34.77#ibcon#wrote, iclass 31, count 0 2006.257.20:22:34.77#ibcon#about to read 3, iclass 31, count 0 2006.257.20:22:34.79#ibcon#read 3, iclass 31, count 0 2006.257.20:22:34.79#ibcon#about to read 4, iclass 31, count 0 2006.257.20:22:34.79#ibcon#read 4, iclass 31, count 0 2006.257.20:22:34.79#ibcon#about to read 5, iclass 31, count 0 2006.257.20:22:34.79#ibcon#read 5, iclass 31, count 0 2006.257.20:22:34.79#ibcon#about to read 6, iclass 31, count 0 2006.257.20:22:34.79#ibcon#read 6, iclass 31, count 0 2006.257.20:22:34.79#ibcon#end of sib2, iclass 31, count 0 2006.257.20:22:34.79#ibcon#*mode == 0, iclass 31, count 0 2006.257.20:22:34.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.20:22:34.79#ibcon#[25=USB\r\n] 2006.257.20:22:34.79#ibcon#*before write, iclass 31, count 0 2006.257.20:22:34.79#ibcon#enter sib2, iclass 31, count 0 2006.257.20:22:34.79#ibcon#flushed, iclass 31, count 0 2006.257.20:22:34.79#ibcon#about to write, iclass 31, count 0 2006.257.20:22:34.79#ibcon#wrote, iclass 31, count 0 2006.257.20:22:34.79#ibcon#about to read 3, iclass 31, count 0 2006.257.20:22:34.82#ibcon#read 3, iclass 31, count 0 2006.257.20:22:34.82#ibcon#about to read 4, iclass 31, count 0 2006.257.20:22:34.82#ibcon#read 4, iclass 31, count 0 2006.257.20:22:34.82#ibcon#about to read 5, iclass 31, count 0 2006.257.20:22:34.82#ibcon#read 5, iclass 31, count 0 2006.257.20:22:34.82#ibcon#about to read 6, iclass 31, count 0 2006.257.20:22:34.82#ibcon#read 6, iclass 31, count 0 2006.257.20:22:34.82#ibcon#end of sib2, iclass 31, count 0 2006.257.20:22:34.82#ibcon#*after write, iclass 31, count 0 2006.257.20:22:34.82#ibcon#*before return 0, iclass 31, count 0 2006.257.20:22:34.82#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:34.82#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:34.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.20:22:34.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.20:22:34.82$vck44/valo=2,534.99 2006.257.20:22:34.82#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.20:22:34.82#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.20:22:34.82#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:34.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:34.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:34.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:34.82#ibcon#enter wrdev, iclass 33, count 0 2006.257.20:22:34.82#ibcon#first serial, iclass 33, count 0 2006.257.20:22:34.82#ibcon#enter sib2, iclass 33, count 0 2006.257.20:22:34.82#ibcon#flushed, iclass 33, count 0 2006.257.20:22:34.82#ibcon#about to write, iclass 33, count 0 2006.257.20:22:34.82#ibcon#wrote, iclass 33, count 0 2006.257.20:22:34.82#ibcon#about to read 3, iclass 33, count 0 2006.257.20:22:34.84#ibcon#read 3, iclass 33, count 0 2006.257.20:22:34.84#ibcon#about to read 4, iclass 33, count 0 2006.257.20:22:34.84#ibcon#read 4, iclass 33, count 0 2006.257.20:22:34.84#ibcon#about to read 5, iclass 33, count 0 2006.257.20:22:34.84#ibcon#read 5, iclass 33, count 0 2006.257.20:22:34.84#ibcon#about to read 6, iclass 33, count 0 2006.257.20:22:34.84#ibcon#read 6, iclass 33, count 0 2006.257.20:22:34.84#ibcon#end of sib2, iclass 33, count 0 2006.257.20:22:34.84#ibcon#*mode == 0, iclass 33, count 0 2006.257.20:22:34.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.20:22:34.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.20:22:34.84#ibcon#*before write, iclass 33, count 0 2006.257.20:22:34.84#ibcon#enter sib2, iclass 33, count 0 2006.257.20:22:34.84#ibcon#flushed, iclass 33, count 0 2006.257.20:22:34.84#ibcon#about to write, iclass 33, count 0 2006.257.20:22:34.84#ibcon#wrote, iclass 33, count 0 2006.257.20:22:34.84#ibcon#about to read 3, iclass 33, count 0 2006.257.20:22:34.88#ibcon#read 3, iclass 33, count 0 2006.257.20:22:34.88#ibcon#about to read 4, iclass 33, count 0 2006.257.20:22:34.88#ibcon#read 4, iclass 33, count 0 2006.257.20:22:34.88#ibcon#about to read 5, iclass 33, count 0 2006.257.20:22:34.88#ibcon#read 5, iclass 33, count 0 2006.257.20:22:34.88#ibcon#about to read 6, iclass 33, count 0 2006.257.20:22:34.88#ibcon#read 6, iclass 33, count 0 2006.257.20:22:34.88#ibcon#end of sib2, iclass 33, count 0 2006.257.20:22:34.88#ibcon#*after write, iclass 33, count 0 2006.257.20:22:34.88#ibcon#*before return 0, iclass 33, count 0 2006.257.20:22:34.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:34.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:34.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.20:22:34.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.20:22:34.88$vck44/va=2,7 2006.257.20:22:34.88#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.20:22:34.88#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.20:22:34.88#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:34.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:34.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:34.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:34.94#ibcon#enter wrdev, iclass 35, count 2 2006.257.20:22:34.94#ibcon#first serial, iclass 35, count 2 2006.257.20:22:34.94#ibcon#enter sib2, iclass 35, count 2 2006.257.20:22:34.94#ibcon#flushed, iclass 35, count 2 2006.257.20:22:34.94#ibcon#about to write, iclass 35, count 2 2006.257.20:22:34.94#ibcon#wrote, iclass 35, count 2 2006.257.20:22:34.94#ibcon#about to read 3, iclass 35, count 2 2006.257.20:22:34.96#ibcon#read 3, iclass 35, count 2 2006.257.20:22:34.96#ibcon#about to read 4, iclass 35, count 2 2006.257.20:22:34.96#ibcon#read 4, iclass 35, count 2 2006.257.20:22:34.96#ibcon#about to read 5, iclass 35, count 2 2006.257.20:22:34.96#ibcon#read 5, iclass 35, count 2 2006.257.20:22:34.96#ibcon#about to read 6, iclass 35, count 2 2006.257.20:22:34.96#ibcon#read 6, iclass 35, count 2 2006.257.20:22:34.96#ibcon#end of sib2, iclass 35, count 2 2006.257.20:22:34.96#ibcon#*mode == 0, iclass 35, count 2 2006.257.20:22:34.96#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.20:22:34.96#ibcon#[25=AT02-07\r\n] 2006.257.20:22:34.96#ibcon#*before write, iclass 35, count 2 2006.257.20:22:34.96#ibcon#enter sib2, iclass 35, count 2 2006.257.20:22:34.96#ibcon#flushed, iclass 35, count 2 2006.257.20:22:34.96#ibcon#about to write, iclass 35, count 2 2006.257.20:22:34.96#ibcon#wrote, iclass 35, count 2 2006.257.20:22:34.96#ibcon#about to read 3, iclass 35, count 2 2006.257.20:22:34.99#ibcon#read 3, iclass 35, count 2 2006.257.20:22:34.99#ibcon#about to read 4, iclass 35, count 2 2006.257.20:22:34.99#ibcon#read 4, iclass 35, count 2 2006.257.20:22:34.99#ibcon#about to read 5, iclass 35, count 2 2006.257.20:22:34.99#ibcon#read 5, iclass 35, count 2 2006.257.20:22:34.99#ibcon#about to read 6, iclass 35, count 2 2006.257.20:22:34.99#ibcon#read 6, iclass 35, count 2 2006.257.20:22:34.99#ibcon#end of sib2, iclass 35, count 2 2006.257.20:22:34.99#ibcon#*after write, iclass 35, count 2 2006.257.20:22:34.99#ibcon#*before return 0, iclass 35, count 2 2006.257.20:22:34.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:34.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:34.99#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.20:22:34.99#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:34.99#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:35.11#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:35.11#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:35.11#ibcon#enter wrdev, iclass 35, count 0 2006.257.20:22:35.11#ibcon#first serial, iclass 35, count 0 2006.257.20:22:35.11#ibcon#enter sib2, iclass 35, count 0 2006.257.20:22:35.11#ibcon#flushed, iclass 35, count 0 2006.257.20:22:35.11#ibcon#about to write, iclass 35, count 0 2006.257.20:22:35.11#ibcon#wrote, iclass 35, count 0 2006.257.20:22:35.11#ibcon#about to read 3, iclass 35, count 0 2006.257.20:22:35.13#ibcon#read 3, iclass 35, count 0 2006.257.20:22:35.13#ibcon#about to read 4, iclass 35, count 0 2006.257.20:22:35.13#ibcon#read 4, iclass 35, count 0 2006.257.20:22:35.13#ibcon#about to read 5, iclass 35, count 0 2006.257.20:22:35.13#ibcon#read 5, iclass 35, count 0 2006.257.20:22:35.13#ibcon#about to read 6, iclass 35, count 0 2006.257.20:22:35.13#ibcon#read 6, iclass 35, count 0 2006.257.20:22:35.13#ibcon#end of sib2, iclass 35, count 0 2006.257.20:22:35.13#ibcon#*mode == 0, iclass 35, count 0 2006.257.20:22:35.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.20:22:35.13#ibcon#[25=USB\r\n] 2006.257.20:22:35.13#ibcon#*before write, iclass 35, count 0 2006.257.20:22:35.13#ibcon#enter sib2, iclass 35, count 0 2006.257.20:22:35.13#ibcon#flushed, iclass 35, count 0 2006.257.20:22:35.13#ibcon#about to write, iclass 35, count 0 2006.257.20:22:35.13#ibcon#wrote, iclass 35, count 0 2006.257.20:22:35.13#ibcon#about to read 3, iclass 35, count 0 2006.257.20:22:35.16#ibcon#read 3, iclass 35, count 0 2006.257.20:22:35.16#ibcon#about to read 4, iclass 35, count 0 2006.257.20:22:35.16#ibcon#read 4, iclass 35, count 0 2006.257.20:22:35.16#ibcon#about to read 5, iclass 35, count 0 2006.257.20:22:35.16#ibcon#read 5, iclass 35, count 0 2006.257.20:22:35.16#ibcon#about to read 6, iclass 35, count 0 2006.257.20:22:35.16#ibcon#read 6, iclass 35, count 0 2006.257.20:22:35.16#ibcon#end of sib2, iclass 35, count 0 2006.257.20:22:35.16#ibcon#*after write, iclass 35, count 0 2006.257.20:22:35.16#ibcon#*before return 0, iclass 35, count 0 2006.257.20:22:35.16#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:35.16#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:35.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.20:22:35.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.20:22:35.16$vck44/valo=3,564.99 2006.257.20:22:35.16#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.20:22:35.16#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.20:22:35.16#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:35.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:35.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:35.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:35.16#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:22:35.16#ibcon#first serial, iclass 37, count 0 2006.257.20:22:35.16#ibcon#enter sib2, iclass 37, count 0 2006.257.20:22:35.16#ibcon#flushed, iclass 37, count 0 2006.257.20:22:35.16#ibcon#about to write, iclass 37, count 0 2006.257.20:22:35.16#ibcon#wrote, iclass 37, count 0 2006.257.20:22:35.16#ibcon#about to read 3, iclass 37, count 0 2006.257.20:22:35.18#ibcon#read 3, iclass 37, count 0 2006.257.20:22:35.18#ibcon#about to read 4, iclass 37, count 0 2006.257.20:22:35.18#ibcon#read 4, iclass 37, count 0 2006.257.20:22:35.18#ibcon#about to read 5, iclass 37, count 0 2006.257.20:22:35.18#ibcon#read 5, iclass 37, count 0 2006.257.20:22:35.18#ibcon#about to read 6, iclass 37, count 0 2006.257.20:22:35.18#ibcon#read 6, iclass 37, count 0 2006.257.20:22:35.18#ibcon#end of sib2, iclass 37, count 0 2006.257.20:22:35.18#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:22:35.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:22:35.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.20:22:35.18#ibcon#*before write, iclass 37, count 0 2006.257.20:22:35.18#ibcon#enter sib2, iclass 37, count 0 2006.257.20:22:35.18#ibcon#flushed, iclass 37, count 0 2006.257.20:22:35.18#ibcon#about to write, iclass 37, count 0 2006.257.20:22:35.18#ibcon#wrote, iclass 37, count 0 2006.257.20:22:35.18#ibcon#about to read 3, iclass 37, count 0 2006.257.20:22:35.22#ibcon#read 3, iclass 37, count 0 2006.257.20:22:35.22#ibcon#about to read 4, iclass 37, count 0 2006.257.20:22:35.22#ibcon#read 4, iclass 37, count 0 2006.257.20:22:35.22#ibcon#about to read 5, iclass 37, count 0 2006.257.20:22:35.22#ibcon#read 5, iclass 37, count 0 2006.257.20:22:35.22#ibcon#about to read 6, iclass 37, count 0 2006.257.20:22:35.22#ibcon#read 6, iclass 37, count 0 2006.257.20:22:35.22#ibcon#end of sib2, iclass 37, count 0 2006.257.20:22:35.22#ibcon#*after write, iclass 37, count 0 2006.257.20:22:35.22#ibcon#*before return 0, iclass 37, count 0 2006.257.20:22:35.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:35.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:35.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:22:35.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:22:35.22$vck44/va=3,8 2006.257.20:22:35.22#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.20:22:35.22#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.20:22:35.22#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:35.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:35.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:35.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:35.28#ibcon#enter wrdev, iclass 39, count 2 2006.257.20:22:35.28#ibcon#first serial, iclass 39, count 2 2006.257.20:22:35.28#ibcon#enter sib2, iclass 39, count 2 2006.257.20:22:35.28#ibcon#flushed, iclass 39, count 2 2006.257.20:22:35.28#ibcon#about to write, iclass 39, count 2 2006.257.20:22:35.28#ibcon#wrote, iclass 39, count 2 2006.257.20:22:35.28#ibcon#about to read 3, iclass 39, count 2 2006.257.20:22:35.30#ibcon#read 3, iclass 39, count 2 2006.257.20:22:35.30#ibcon#about to read 4, iclass 39, count 2 2006.257.20:22:35.30#ibcon#read 4, iclass 39, count 2 2006.257.20:22:35.30#ibcon#about to read 5, iclass 39, count 2 2006.257.20:22:35.30#ibcon#read 5, iclass 39, count 2 2006.257.20:22:35.30#ibcon#about to read 6, iclass 39, count 2 2006.257.20:22:35.30#ibcon#read 6, iclass 39, count 2 2006.257.20:22:35.30#ibcon#end of sib2, iclass 39, count 2 2006.257.20:22:35.30#ibcon#*mode == 0, iclass 39, count 2 2006.257.20:22:35.30#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.20:22:35.30#ibcon#[25=AT03-08\r\n] 2006.257.20:22:35.30#ibcon#*before write, iclass 39, count 2 2006.257.20:22:35.30#ibcon#enter sib2, iclass 39, count 2 2006.257.20:22:35.30#ibcon#flushed, iclass 39, count 2 2006.257.20:22:35.30#ibcon#about to write, iclass 39, count 2 2006.257.20:22:35.30#ibcon#wrote, iclass 39, count 2 2006.257.20:22:35.30#ibcon#about to read 3, iclass 39, count 2 2006.257.20:22:35.33#ibcon#read 3, iclass 39, count 2 2006.257.20:22:35.33#ibcon#about to read 4, iclass 39, count 2 2006.257.20:22:35.33#ibcon#read 4, iclass 39, count 2 2006.257.20:22:35.33#ibcon#about to read 5, iclass 39, count 2 2006.257.20:22:35.33#ibcon#read 5, iclass 39, count 2 2006.257.20:22:35.33#ibcon#about to read 6, iclass 39, count 2 2006.257.20:22:35.33#ibcon#read 6, iclass 39, count 2 2006.257.20:22:35.33#ibcon#end of sib2, iclass 39, count 2 2006.257.20:22:35.33#ibcon#*after write, iclass 39, count 2 2006.257.20:22:35.33#ibcon#*before return 0, iclass 39, count 2 2006.257.20:22:35.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:35.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:35.33#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.20:22:35.33#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:35.33#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:35.45#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:35.45#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:35.45#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:22:35.45#ibcon#first serial, iclass 39, count 0 2006.257.20:22:35.45#ibcon#enter sib2, iclass 39, count 0 2006.257.20:22:35.45#ibcon#flushed, iclass 39, count 0 2006.257.20:22:35.45#ibcon#about to write, iclass 39, count 0 2006.257.20:22:35.45#ibcon#wrote, iclass 39, count 0 2006.257.20:22:35.45#ibcon#about to read 3, iclass 39, count 0 2006.257.20:22:35.47#ibcon#read 3, iclass 39, count 0 2006.257.20:22:35.47#ibcon#about to read 4, iclass 39, count 0 2006.257.20:22:35.47#ibcon#read 4, iclass 39, count 0 2006.257.20:22:35.47#ibcon#about to read 5, iclass 39, count 0 2006.257.20:22:35.47#ibcon#read 5, iclass 39, count 0 2006.257.20:22:35.47#ibcon#about to read 6, iclass 39, count 0 2006.257.20:22:35.47#ibcon#read 6, iclass 39, count 0 2006.257.20:22:35.47#ibcon#end of sib2, iclass 39, count 0 2006.257.20:22:35.47#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:22:35.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:22:35.47#ibcon#[25=USB\r\n] 2006.257.20:22:35.47#ibcon#*before write, iclass 39, count 0 2006.257.20:22:35.47#ibcon#enter sib2, iclass 39, count 0 2006.257.20:22:35.47#ibcon#flushed, iclass 39, count 0 2006.257.20:22:35.47#ibcon#about to write, iclass 39, count 0 2006.257.20:22:35.47#ibcon#wrote, iclass 39, count 0 2006.257.20:22:35.47#ibcon#about to read 3, iclass 39, count 0 2006.257.20:22:35.50#ibcon#read 3, iclass 39, count 0 2006.257.20:22:35.50#ibcon#about to read 4, iclass 39, count 0 2006.257.20:22:35.50#ibcon#read 4, iclass 39, count 0 2006.257.20:22:35.50#ibcon#about to read 5, iclass 39, count 0 2006.257.20:22:35.50#ibcon#read 5, iclass 39, count 0 2006.257.20:22:35.50#ibcon#about to read 6, iclass 39, count 0 2006.257.20:22:35.50#ibcon#read 6, iclass 39, count 0 2006.257.20:22:35.50#ibcon#end of sib2, iclass 39, count 0 2006.257.20:22:35.50#ibcon#*after write, iclass 39, count 0 2006.257.20:22:35.50#ibcon#*before return 0, iclass 39, count 0 2006.257.20:22:35.50#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:35.50#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:35.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:22:35.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:22:35.50$vck44/valo=4,624.99 2006.257.20:22:35.50#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.20:22:35.50#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.20:22:35.50#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:35.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:35.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:35.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:35.50#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:22:35.50#ibcon#first serial, iclass 3, count 0 2006.257.20:22:35.50#ibcon#enter sib2, iclass 3, count 0 2006.257.20:22:35.50#ibcon#flushed, iclass 3, count 0 2006.257.20:22:35.50#ibcon#about to write, iclass 3, count 0 2006.257.20:22:35.50#ibcon#wrote, iclass 3, count 0 2006.257.20:22:35.50#ibcon#about to read 3, iclass 3, count 0 2006.257.20:22:35.52#ibcon#read 3, iclass 3, count 0 2006.257.20:22:35.52#ibcon#about to read 4, iclass 3, count 0 2006.257.20:22:35.52#ibcon#read 4, iclass 3, count 0 2006.257.20:22:35.52#ibcon#about to read 5, iclass 3, count 0 2006.257.20:22:35.52#ibcon#read 5, iclass 3, count 0 2006.257.20:22:35.52#ibcon#about to read 6, iclass 3, count 0 2006.257.20:22:35.52#ibcon#read 6, iclass 3, count 0 2006.257.20:22:35.52#ibcon#end of sib2, iclass 3, count 0 2006.257.20:22:35.52#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:22:35.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:22:35.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.20:22:35.52#ibcon#*before write, iclass 3, count 0 2006.257.20:22:35.52#ibcon#enter sib2, iclass 3, count 0 2006.257.20:22:35.52#ibcon#flushed, iclass 3, count 0 2006.257.20:22:35.52#ibcon#about to write, iclass 3, count 0 2006.257.20:22:35.52#ibcon#wrote, iclass 3, count 0 2006.257.20:22:35.52#ibcon#about to read 3, iclass 3, count 0 2006.257.20:22:35.56#ibcon#read 3, iclass 3, count 0 2006.257.20:22:35.56#ibcon#about to read 4, iclass 3, count 0 2006.257.20:22:35.56#ibcon#read 4, iclass 3, count 0 2006.257.20:22:35.56#ibcon#about to read 5, iclass 3, count 0 2006.257.20:22:35.56#ibcon#read 5, iclass 3, count 0 2006.257.20:22:35.56#ibcon#about to read 6, iclass 3, count 0 2006.257.20:22:35.56#ibcon#read 6, iclass 3, count 0 2006.257.20:22:35.56#ibcon#end of sib2, iclass 3, count 0 2006.257.20:22:35.56#ibcon#*after write, iclass 3, count 0 2006.257.20:22:35.56#ibcon#*before return 0, iclass 3, count 0 2006.257.20:22:35.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:35.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:35.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:22:35.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:22:35.56$vck44/va=4,7 2006.257.20:22:35.56#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.20:22:35.56#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.20:22:35.56#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:35.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:22:35.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:22:35.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:22:35.62#ibcon#enter wrdev, iclass 5, count 2 2006.257.20:22:35.62#ibcon#first serial, iclass 5, count 2 2006.257.20:22:35.62#ibcon#enter sib2, iclass 5, count 2 2006.257.20:22:35.62#ibcon#flushed, iclass 5, count 2 2006.257.20:22:35.62#ibcon#about to write, iclass 5, count 2 2006.257.20:22:35.62#ibcon#wrote, iclass 5, count 2 2006.257.20:22:35.62#ibcon#about to read 3, iclass 5, count 2 2006.257.20:22:35.64#ibcon#read 3, iclass 5, count 2 2006.257.20:22:35.64#ibcon#about to read 4, iclass 5, count 2 2006.257.20:22:35.64#ibcon#read 4, iclass 5, count 2 2006.257.20:22:35.64#ibcon#about to read 5, iclass 5, count 2 2006.257.20:22:35.64#ibcon#read 5, iclass 5, count 2 2006.257.20:22:35.64#ibcon#about to read 6, iclass 5, count 2 2006.257.20:22:35.64#ibcon#read 6, iclass 5, count 2 2006.257.20:22:35.64#ibcon#end of sib2, iclass 5, count 2 2006.257.20:22:35.64#ibcon#*mode == 0, iclass 5, count 2 2006.257.20:22:35.64#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.20:22:35.64#ibcon#[25=AT04-07\r\n] 2006.257.20:22:35.64#ibcon#*before write, iclass 5, count 2 2006.257.20:22:35.64#ibcon#enter sib2, iclass 5, count 2 2006.257.20:22:35.64#ibcon#flushed, iclass 5, count 2 2006.257.20:22:35.64#ibcon#about to write, iclass 5, count 2 2006.257.20:22:35.64#ibcon#wrote, iclass 5, count 2 2006.257.20:22:35.64#ibcon#about to read 3, iclass 5, count 2 2006.257.20:22:35.67#ibcon#read 3, iclass 5, count 2 2006.257.20:22:35.67#ibcon#about to read 4, iclass 5, count 2 2006.257.20:22:35.67#ibcon#read 4, iclass 5, count 2 2006.257.20:22:35.67#ibcon#about to read 5, iclass 5, count 2 2006.257.20:22:35.67#ibcon#read 5, iclass 5, count 2 2006.257.20:22:35.67#ibcon#about to read 6, iclass 5, count 2 2006.257.20:22:35.67#ibcon#read 6, iclass 5, count 2 2006.257.20:22:35.67#ibcon#end of sib2, iclass 5, count 2 2006.257.20:22:35.67#ibcon#*after write, iclass 5, count 2 2006.257.20:22:35.67#ibcon#*before return 0, iclass 5, count 2 2006.257.20:22:35.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:22:35.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:22:35.67#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.20:22:35.67#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:35.67#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:22:35.79#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:22:35.79#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:22:35.79#ibcon#enter wrdev, iclass 5, count 0 2006.257.20:22:35.79#ibcon#first serial, iclass 5, count 0 2006.257.20:22:35.79#ibcon#enter sib2, iclass 5, count 0 2006.257.20:22:35.79#ibcon#flushed, iclass 5, count 0 2006.257.20:22:35.79#ibcon#about to write, iclass 5, count 0 2006.257.20:22:35.79#ibcon#wrote, iclass 5, count 0 2006.257.20:22:35.79#ibcon#about to read 3, iclass 5, count 0 2006.257.20:22:35.81#ibcon#read 3, iclass 5, count 0 2006.257.20:22:35.81#ibcon#about to read 4, iclass 5, count 0 2006.257.20:22:35.81#ibcon#read 4, iclass 5, count 0 2006.257.20:22:35.81#ibcon#about to read 5, iclass 5, count 0 2006.257.20:22:35.81#ibcon#read 5, iclass 5, count 0 2006.257.20:22:35.81#ibcon#about to read 6, iclass 5, count 0 2006.257.20:22:35.81#ibcon#read 6, iclass 5, count 0 2006.257.20:22:35.81#ibcon#end of sib2, iclass 5, count 0 2006.257.20:22:35.81#ibcon#*mode == 0, iclass 5, count 0 2006.257.20:22:35.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.20:22:35.81#ibcon#[25=USB\r\n] 2006.257.20:22:35.81#ibcon#*before write, iclass 5, count 0 2006.257.20:22:35.81#ibcon#enter sib2, iclass 5, count 0 2006.257.20:22:35.81#ibcon#flushed, iclass 5, count 0 2006.257.20:22:35.81#ibcon#about to write, iclass 5, count 0 2006.257.20:22:35.81#ibcon#wrote, iclass 5, count 0 2006.257.20:22:35.81#ibcon#about to read 3, iclass 5, count 0 2006.257.20:22:35.84#ibcon#read 3, iclass 5, count 0 2006.257.20:22:35.84#ibcon#about to read 4, iclass 5, count 0 2006.257.20:22:35.84#ibcon#read 4, iclass 5, count 0 2006.257.20:22:35.84#ibcon#about to read 5, iclass 5, count 0 2006.257.20:22:35.84#ibcon#read 5, iclass 5, count 0 2006.257.20:22:35.84#ibcon#about to read 6, iclass 5, count 0 2006.257.20:22:35.84#ibcon#read 6, iclass 5, count 0 2006.257.20:22:35.84#ibcon#end of sib2, iclass 5, count 0 2006.257.20:22:35.84#ibcon#*after write, iclass 5, count 0 2006.257.20:22:35.84#ibcon#*before return 0, iclass 5, count 0 2006.257.20:22:35.84#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:22:35.84#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:22:35.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.20:22:35.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.20:22:35.84$vck44/valo=5,734.99 2006.257.20:22:35.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.20:22:35.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.20:22:35.84#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:35.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:22:35.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:22:35.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:22:35.84#ibcon#enter wrdev, iclass 7, count 0 2006.257.20:22:35.84#ibcon#first serial, iclass 7, count 0 2006.257.20:22:35.84#ibcon#enter sib2, iclass 7, count 0 2006.257.20:22:35.84#ibcon#flushed, iclass 7, count 0 2006.257.20:22:35.84#ibcon#about to write, iclass 7, count 0 2006.257.20:22:35.84#ibcon#wrote, iclass 7, count 0 2006.257.20:22:35.84#ibcon#about to read 3, iclass 7, count 0 2006.257.20:22:35.86#ibcon#read 3, iclass 7, count 0 2006.257.20:22:35.86#ibcon#about to read 4, iclass 7, count 0 2006.257.20:22:35.86#ibcon#read 4, iclass 7, count 0 2006.257.20:22:35.86#ibcon#about to read 5, iclass 7, count 0 2006.257.20:22:35.86#ibcon#read 5, iclass 7, count 0 2006.257.20:22:35.86#ibcon#about to read 6, iclass 7, count 0 2006.257.20:22:35.86#ibcon#read 6, iclass 7, count 0 2006.257.20:22:35.86#ibcon#end of sib2, iclass 7, count 0 2006.257.20:22:35.86#ibcon#*mode == 0, iclass 7, count 0 2006.257.20:22:35.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.20:22:35.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.20:22:35.86#ibcon#*before write, iclass 7, count 0 2006.257.20:22:35.86#ibcon#enter sib2, iclass 7, count 0 2006.257.20:22:35.86#ibcon#flushed, iclass 7, count 0 2006.257.20:22:35.86#ibcon#about to write, iclass 7, count 0 2006.257.20:22:35.86#ibcon#wrote, iclass 7, count 0 2006.257.20:22:35.86#ibcon#about to read 3, iclass 7, count 0 2006.257.20:22:35.90#ibcon#read 3, iclass 7, count 0 2006.257.20:22:35.90#ibcon#about to read 4, iclass 7, count 0 2006.257.20:22:35.90#ibcon#read 4, iclass 7, count 0 2006.257.20:22:35.90#ibcon#about to read 5, iclass 7, count 0 2006.257.20:22:35.90#ibcon#read 5, iclass 7, count 0 2006.257.20:22:35.90#ibcon#about to read 6, iclass 7, count 0 2006.257.20:22:35.90#ibcon#read 6, iclass 7, count 0 2006.257.20:22:35.90#ibcon#end of sib2, iclass 7, count 0 2006.257.20:22:35.90#ibcon#*after write, iclass 7, count 0 2006.257.20:22:35.90#ibcon#*before return 0, iclass 7, count 0 2006.257.20:22:35.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:22:35.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:22:35.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.20:22:35.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.20:22:35.90$vck44/va=5,4 2006.257.20:22:35.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.20:22:35.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.20:22:35.90#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:35.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:22:35.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:22:35.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:22:35.96#ibcon#enter wrdev, iclass 11, count 2 2006.257.20:22:35.96#ibcon#first serial, iclass 11, count 2 2006.257.20:22:35.96#ibcon#enter sib2, iclass 11, count 2 2006.257.20:22:35.96#ibcon#flushed, iclass 11, count 2 2006.257.20:22:35.96#ibcon#about to write, iclass 11, count 2 2006.257.20:22:35.96#ibcon#wrote, iclass 11, count 2 2006.257.20:22:35.96#ibcon#about to read 3, iclass 11, count 2 2006.257.20:22:35.98#ibcon#read 3, iclass 11, count 2 2006.257.20:22:35.98#ibcon#about to read 4, iclass 11, count 2 2006.257.20:22:35.98#ibcon#read 4, iclass 11, count 2 2006.257.20:22:35.98#ibcon#about to read 5, iclass 11, count 2 2006.257.20:22:35.98#ibcon#read 5, iclass 11, count 2 2006.257.20:22:35.98#ibcon#about to read 6, iclass 11, count 2 2006.257.20:22:35.98#ibcon#read 6, iclass 11, count 2 2006.257.20:22:35.98#ibcon#end of sib2, iclass 11, count 2 2006.257.20:22:35.98#ibcon#*mode == 0, iclass 11, count 2 2006.257.20:22:35.98#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.20:22:35.98#ibcon#[25=AT05-04\r\n] 2006.257.20:22:35.98#ibcon#*before write, iclass 11, count 2 2006.257.20:22:35.98#ibcon#enter sib2, iclass 11, count 2 2006.257.20:22:35.98#ibcon#flushed, iclass 11, count 2 2006.257.20:22:35.98#ibcon#about to write, iclass 11, count 2 2006.257.20:22:35.98#ibcon#wrote, iclass 11, count 2 2006.257.20:22:35.98#ibcon#about to read 3, iclass 11, count 2 2006.257.20:22:36.01#ibcon#read 3, iclass 11, count 2 2006.257.20:22:36.01#ibcon#about to read 4, iclass 11, count 2 2006.257.20:22:36.01#ibcon#read 4, iclass 11, count 2 2006.257.20:22:36.01#ibcon#about to read 5, iclass 11, count 2 2006.257.20:22:36.01#ibcon#read 5, iclass 11, count 2 2006.257.20:22:36.01#ibcon#about to read 6, iclass 11, count 2 2006.257.20:22:36.01#ibcon#read 6, iclass 11, count 2 2006.257.20:22:36.01#ibcon#end of sib2, iclass 11, count 2 2006.257.20:22:36.01#ibcon#*after write, iclass 11, count 2 2006.257.20:22:36.01#ibcon#*before return 0, iclass 11, count 2 2006.257.20:22:36.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:22:36.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:22:36.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.20:22:36.01#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:36.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:22:36.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:22:36.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:22:36.13#ibcon#enter wrdev, iclass 11, count 0 2006.257.20:22:36.13#ibcon#first serial, iclass 11, count 0 2006.257.20:22:36.13#ibcon#enter sib2, iclass 11, count 0 2006.257.20:22:36.13#ibcon#flushed, iclass 11, count 0 2006.257.20:22:36.13#ibcon#about to write, iclass 11, count 0 2006.257.20:22:36.13#ibcon#wrote, iclass 11, count 0 2006.257.20:22:36.13#ibcon#about to read 3, iclass 11, count 0 2006.257.20:22:36.15#ibcon#read 3, iclass 11, count 0 2006.257.20:22:36.15#ibcon#about to read 4, iclass 11, count 0 2006.257.20:22:36.15#ibcon#read 4, iclass 11, count 0 2006.257.20:22:36.15#ibcon#about to read 5, iclass 11, count 0 2006.257.20:22:36.15#ibcon#read 5, iclass 11, count 0 2006.257.20:22:36.15#ibcon#about to read 6, iclass 11, count 0 2006.257.20:22:36.15#ibcon#read 6, iclass 11, count 0 2006.257.20:22:36.15#ibcon#end of sib2, iclass 11, count 0 2006.257.20:22:36.15#ibcon#*mode == 0, iclass 11, count 0 2006.257.20:22:36.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.20:22:36.15#ibcon#[25=USB\r\n] 2006.257.20:22:36.15#ibcon#*before write, iclass 11, count 0 2006.257.20:22:36.15#ibcon#enter sib2, iclass 11, count 0 2006.257.20:22:36.15#ibcon#flushed, iclass 11, count 0 2006.257.20:22:36.15#ibcon#about to write, iclass 11, count 0 2006.257.20:22:36.15#ibcon#wrote, iclass 11, count 0 2006.257.20:22:36.15#ibcon#about to read 3, iclass 11, count 0 2006.257.20:22:36.18#ibcon#read 3, iclass 11, count 0 2006.257.20:22:36.18#ibcon#about to read 4, iclass 11, count 0 2006.257.20:22:36.18#ibcon#read 4, iclass 11, count 0 2006.257.20:22:36.18#ibcon#about to read 5, iclass 11, count 0 2006.257.20:22:36.18#ibcon#read 5, iclass 11, count 0 2006.257.20:22:36.18#ibcon#about to read 6, iclass 11, count 0 2006.257.20:22:36.18#ibcon#read 6, iclass 11, count 0 2006.257.20:22:36.18#ibcon#end of sib2, iclass 11, count 0 2006.257.20:22:36.18#ibcon#*after write, iclass 11, count 0 2006.257.20:22:36.18#ibcon#*before return 0, iclass 11, count 0 2006.257.20:22:36.18#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:22:36.18#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:22:36.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.20:22:36.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.20:22:36.18$vck44/valo=6,814.99 2006.257.20:22:36.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.20:22:36.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.20:22:36.18#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:36.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:36.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:36.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:36.18#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:22:36.18#ibcon#first serial, iclass 13, count 0 2006.257.20:22:36.18#ibcon#enter sib2, iclass 13, count 0 2006.257.20:22:36.18#ibcon#flushed, iclass 13, count 0 2006.257.20:22:36.18#ibcon#about to write, iclass 13, count 0 2006.257.20:22:36.18#ibcon#wrote, iclass 13, count 0 2006.257.20:22:36.18#ibcon#about to read 3, iclass 13, count 0 2006.257.20:22:36.20#ibcon#read 3, iclass 13, count 0 2006.257.20:22:36.20#ibcon#about to read 4, iclass 13, count 0 2006.257.20:22:36.20#ibcon#read 4, iclass 13, count 0 2006.257.20:22:36.20#ibcon#about to read 5, iclass 13, count 0 2006.257.20:22:36.20#ibcon#read 5, iclass 13, count 0 2006.257.20:22:36.20#ibcon#about to read 6, iclass 13, count 0 2006.257.20:22:36.20#ibcon#read 6, iclass 13, count 0 2006.257.20:22:36.20#ibcon#end of sib2, iclass 13, count 0 2006.257.20:22:36.20#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:22:36.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:22:36.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.20:22:36.20#ibcon#*before write, iclass 13, count 0 2006.257.20:22:36.20#ibcon#enter sib2, iclass 13, count 0 2006.257.20:22:36.20#ibcon#flushed, iclass 13, count 0 2006.257.20:22:36.20#ibcon#about to write, iclass 13, count 0 2006.257.20:22:36.20#ibcon#wrote, iclass 13, count 0 2006.257.20:22:36.20#ibcon#about to read 3, iclass 13, count 0 2006.257.20:22:36.24#ibcon#read 3, iclass 13, count 0 2006.257.20:22:36.24#ibcon#about to read 4, iclass 13, count 0 2006.257.20:22:36.24#ibcon#read 4, iclass 13, count 0 2006.257.20:22:36.24#ibcon#about to read 5, iclass 13, count 0 2006.257.20:22:36.24#ibcon#read 5, iclass 13, count 0 2006.257.20:22:36.24#ibcon#about to read 6, iclass 13, count 0 2006.257.20:22:36.24#ibcon#read 6, iclass 13, count 0 2006.257.20:22:36.24#ibcon#end of sib2, iclass 13, count 0 2006.257.20:22:36.24#ibcon#*after write, iclass 13, count 0 2006.257.20:22:36.24#ibcon#*before return 0, iclass 13, count 0 2006.257.20:22:36.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:36.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:36.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:22:36.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:22:36.24$vck44/va=6,4 2006.257.20:22:36.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.20:22:36.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.20:22:36.24#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:36.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:36.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:36.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:36.30#ibcon#enter wrdev, iclass 15, count 2 2006.257.20:22:36.30#ibcon#first serial, iclass 15, count 2 2006.257.20:22:36.30#ibcon#enter sib2, iclass 15, count 2 2006.257.20:22:36.30#ibcon#flushed, iclass 15, count 2 2006.257.20:22:36.30#ibcon#about to write, iclass 15, count 2 2006.257.20:22:36.30#ibcon#wrote, iclass 15, count 2 2006.257.20:22:36.30#ibcon#about to read 3, iclass 15, count 2 2006.257.20:22:36.32#ibcon#read 3, iclass 15, count 2 2006.257.20:22:36.32#ibcon#about to read 4, iclass 15, count 2 2006.257.20:22:36.32#ibcon#read 4, iclass 15, count 2 2006.257.20:22:36.32#ibcon#about to read 5, iclass 15, count 2 2006.257.20:22:36.32#ibcon#read 5, iclass 15, count 2 2006.257.20:22:36.32#ibcon#about to read 6, iclass 15, count 2 2006.257.20:22:36.32#ibcon#read 6, iclass 15, count 2 2006.257.20:22:36.32#ibcon#end of sib2, iclass 15, count 2 2006.257.20:22:36.32#ibcon#*mode == 0, iclass 15, count 2 2006.257.20:22:36.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.20:22:36.32#ibcon#[25=AT06-04\r\n] 2006.257.20:22:36.32#ibcon#*before write, iclass 15, count 2 2006.257.20:22:36.32#ibcon#enter sib2, iclass 15, count 2 2006.257.20:22:36.32#ibcon#flushed, iclass 15, count 2 2006.257.20:22:36.32#ibcon#about to write, iclass 15, count 2 2006.257.20:22:36.32#ibcon#wrote, iclass 15, count 2 2006.257.20:22:36.32#ibcon#about to read 3, iclass 15, count 2 2006.257.20:22:36.35#ibcon#read 3, iclass 15, count 2 2006.257.20:22:36.35#ibcon#about to read 4, iclass 15, count 2 2006.257.20:22:36.35#ibcon#read 4, iclass 15, count 2 2006.257.20:22:36.35#ibcon#about to read 5, iclass 15, count 2 2006.257.20:22:36.35#ibcon#read 5, iclass 15, count 2 2006.257.20:22:36.35#ibcon#about to read 6, iclass 15, count 2 2006.257.20:22:36.35#ibcon#read 6, iclass 15, count 2 2006.257.20:22:36.35#ibcon#end of sib2, iclass 15, count 2 2006.257.20:22:36.35#ibcon#*after write, iclass 15, count 2 2006.257.20:22:36.35#ibcon#*before return 0, iclass 15, count 2 2006.257.20:22:36.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:36.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:36.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.20:22:36.35#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:36.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:36.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:36.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:36.47#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:22:36.47#ibcon#first serial, iclass 15, count 0 2006.257.20:22:36.47#ibcon#enter sib2, iclass 15, count 0 2006.257.20:22:36.47#ibcon#flushed, iclass 15, count 0 2006.257.20:22:36.47#ibcon#about to write, iclass 15, count 0 2006.257.20:22:36.47#ibcon#wrote, iclass 15, count 0 2006.257.20:22:36.47#ibcon#about to read 3, iclass 15, count 0 2006.257.20:22:36.49#ibcon#read 3, iclass 15, count 0 2006.257.20:22:36.49#ibcon#about to read 4, iclass 15, count 0 2006.257.20:22:36.49#ibcon#read 4, iclass 15, count 0 2006.257.20:22:36.49#ibcon#about to read 5, iclass 15, count 0 2006.257.20:22:36.49#ibcon#read 5, iclass 15, count 0 2006.257.20:22:36.49#ibcon#about to read 6, iclass 15, count 0 2006.257.20:22:36.49#ibcon#read 6, iclass 15, count 0 2006.257.20:22:36.49#ibcon#end of sib2, iclass 15, count 0 2006.257.20:22:36.49#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:22:36.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:22:36.49#ibcon#[25=USB\r\n] 2006.257.20:22:36.49#ibcon#*before write, iclass 15, count 0 2006.257.20:22:36.49#ibcon#enter sib2, iclass 15, count 0 2006.257.20:22:36.49#ibcon#flushed, iclass 15, count 0 2006.257.20:22:36.49#ibcon#about to write, iclass 15, count 0 2006.257.20:22:36.49#ibcon#wrote, iclass 15, count 0 2006.257.20:22:36.49#ibcon#about to read 3, iclass 15, count 0 2006.257.20:22:36.52#ibcon#read 3, iclass 15, count 0 2006.257.20:22:36.52#ibcon#about to read 4, iclass 15, count 0 2006.257.20:22:36.52#ibcon#read 4, iclass 15, count 0 2006.257.20:22:36.52#ibcon#about to read 5, iclass 15, count 0 2006.257.20:22:36.52#ibcon#read 5, iclass 15, count 0 2006.257.20:22:36.52#ibcon#about to read 6, iclass 15, count 0 2006.257.20:22:36.52#ibcon#read 6, iclass 15, count 0 2006.257.20:22:36.52#ibcon#end of sib2, iclass 15, count 0 2006.257.20:22:36.52#ibcon#*after write, iclass 15, count 0 2006.257.20:22:36.52#ibcon#*before return 0, iclass 15, count 0 2006.257.20:22:36.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:36.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:36.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:22:36.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:22:36.52$vck44/valo=7,864.99 2006.257.20:22:36.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.20:22:36.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.20:22:36.52#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:36.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:36.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:36.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:36.52#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:22:36.52#ibcon#first serial, iclass 17, count 0 2006.257.20:22:36.52#ibcon#enter sib2, iclass 17, count 0 2006.257.20:22:36.52#ibcon#flushed, iclass 17, count 0 2006.257.20:22:36.52#ibcon#about to write, iclass 17, count 0 2006.257.20:22:36.52#ibcon#wrote, iclass 17, count 0 2006.257.20:22:36.52#ibcon#about to read 3, iclass 17, count 0 2006.257.20:22:36.54#ibcon#read 3, iclass 17, count 0 2006.257.20:22:36.54#ibcon#about to read 4, iclass 17, count 0 2006.257.20:22:36.54#ibcon#read 4, iclass 17, count 0 2006.257.20:22:36.54#ibcon#about to read 5, iclass 17, count 0 2006.257.20:22:36.54#ibcon#read 5, iclass 17, count 0 2006.257.20:22:36.54#ibcon#about to read 6, iclass 17, count 0 2006.257.20:22:36.54#ibcon#read 6, iclass 17, count 0 2006.257.20:22:36.54#ibcon#end of sib2, iclass 17, count 0 2006.257.20:22:36.54#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:22:36.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:22:36.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.20:22:36.54#ibcon#*before write, iclass 17, count 0 2006.257.20:22:36.54#ibcon#enter sib2, iclass 17, count 0 2006.257.20:22:36.54#ibcon#flushed, iclass 17, count 0 2006.257.20:22:36.54#ibcon#about to write, iclass 17, count 0 2006.257.20:22:36.54#ibcon#wrote, iclass 17, count 0 2006.257.20:22:36.54#ibcon#about to read 3, iclass 17, count 0 2006.257.20:22:36.58#ibcon#read 3, iclass 17, count 0 2006.257.20:22:36.58#ibcon#about to read 4, iclass 17, count 0 2006.257.20:22:36.58#ibcon#read 4, iclass 17, count 0 2006.257.20:22:36.58#ibcon#about to read 5, iclass 17, count 0 2006.257.20:22:36.58#ibcon#read 5, iclass 17, count 0 2006.257.20:22:36.58#ibcon#about to read 6, iclass 17, count 0 2006.257.20:22:36.58#ibcon#read 6, iclass 17, count 0 2006.257.20:22:36.58#ibcon#end of sib2, iclass 17, count 0 2006.257.20:22:36.58#ibcon#*after write, iclass 17, count 0 2006.257.20:22:36.58#ibcon#*before return 0, iclass 17, count 0 2006.257.20:22:36.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:36.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:36.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:22:36.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:22:36.58$vck44/va=7,4 2006.257.20:22:36.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.20:22:36.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.20:22:36.58#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:36.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:36.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:36.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:36.64#ibcon#enter wrdev, iclass 19, count 2 2006.257.20:22:36.64#ibcon#first serial, iclass 19, count 2 2006.257.20:22:36.64#ibcon#enter sib2, iclass 19, count 2 2006.257.20:22:36.64#ibcon#flushed, iclass 19, count 2 2006.257.20:22:36.64#ibcon#about to write, iclass 19, count 2 2006.257.20:22:36.64#ibcon#wrote, iclass 19, count 2 2006.257.20:22:36.64#ibcon#about to read 3, iclass 19, count 2 2006.257.20:22:36.66#ibcon#read 3, iclass 19, count 2 2006.257.20:22:36.66#ibcon#about to read 4, iclass 19, count 2 2006.257.20:22:36.66#ibcon#read 4, iclass 19, count 2 2006.257.20:22:36.66#ibcon#about to read 5, iclass 19, count 2 2006.257.20:22:36.66#ibcon#read 5, iclass 19, count 2 2006.257.20:22:36.66#ibcon#about to read 6, iclass 19, count 2 2006.257.20:22:36.66#ibcon#read 6, iclass 19, count 2 2006.257.20:22:36.66#ibcon#end of sib2, iclass 19, count 2 2006.257.20:22:36.66#ibcon#*mode == 0, iclass 19, count 2 2006.257.20:22:36.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.20:22:36.66#ibcon#[25=AT07-04\r\n] 2006.257.20:22:36.66#ibcon#*before write, iclass 19, count 2 2006.257.20:22:36.66#ibcon#enter sib2, iclass 19, count 2 2006.257.20:22:36.66#ibcon#flushed, iclass 19, count 2 2006.257.20:22:36.66#ibcon#about to write, iclass 19, count 2 2006.257.20:22:36.66#ibcon#wrote, iclass 19, count 2 2006.257.20:22:36.66#ibcon#about to read 3, iclass 19, count 2 2006.257.20:22:36.69#ibcon#read 3, iclass 19, count 2 2006.257.20:22:36.69#ibcon#about to read 4, iclass 19, count 2 2006.257.20:22:36.69#ibcon#read 4, iclass 19, count 2 2006.257.20:22:36.69#ibcon#about to read 5, iclass 19, count 2 2006.257.20:22:36.69#ibcon#read 5, iclass 19, count 2 2006.257.20:22:36.69#ibcon#about to read 6, iclass 19, count 2 2006.257.20:22:36.69#ibcon#read 6, iclass 19, count 2 2006.257.20:22:36.69#ibcon#end of sib2, iclass 19, count 2 2006.257.20:22:36.69#ibcon#*after write, iclass 19, count 2 2006.257.20:22:36.69#ibcon#*before return 0, iclass 19, count 2 2006.257.20:22:36.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:36.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:36.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.20:22:36.69#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:36.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:36.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:36.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:36.81#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:22:36.81#ibcon#first serial, iclass 19, count 0 2006.257.20:22:36.81#ibcon#enter sib2, iclass 19, count 0 2006.257.20:22:36.81#ibcon#flushed, iclass 19, count 0 2006.257.20:22:36.81#ibcon#about to write, iclass 19, count 0 2006.257.20:22:36.81#ibcon#wrote, iclass 19, count 0 2006.257.20:22:36.81#ibcon#about to read 3, iclass 19, count 0 2006.257.20:22:36.83#ibcon#read 3, iclass 19, count 0 2006.257.20:22:36.83#ibcon#about to read 4, iclass 19, count 0 2006.257.20:22:36.83#ibcon#read 4, iclass 19, count 0 2006.257.20:22:36.83#ibcon#about to read 5, iclass 19, count 0 2006.257.20:22:36.83#ibcon#read 5, iclass 19, count 0 2006.257.20:22:36.83#ibcon#about to read 6, iclass 19, count 0 2006.257.20:22:36.83#ibcon#read 6, iclass 19, count 0 2006.257.20:22:36.83#ibcon#end of sib2, iclass 19, count 0 2006.257.20:22:36.83#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:22:36.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:22:36.83#ibcon#[25=USB\r\n] 2006.257.20:22:36.83#ibcon#*before write, iclass 19, count 0 2006.257.20:22:36.83#ibcon#enter sib2, iclass 19, count 0 2006.257.20:22:36.83#ibcon#flushed, iclass 19, count 0 2006.257.20:22:36.83#ibcon#about to write, iclass 19, count 0 2006.257.20:22:36.83#ibcon#wrote, iclass 19, count 0 2006.257.20:22:36.83#ibcon#about to read 3, iclass 19, count 0 2006.257.20:22:36.86#ibcon#read 3, iclass 19, count 0 2006.257.20:22:36.86#ibcon#about to read 4, iclass 19, count 0 2006.257.20:22:36.86#ibcon#read 4, iclass 19, count 0 2006.257.20:22:36.86#ibcon#about to read 5, iclass 19, count 0 2006.257.20:22:36.86#ibcon#read 5, iclass 19, count 0 2006.257.20:22:36.86#ibcon#about to read 6, iclass 19, count 0 2006.257.20:22:36.86#ibcon#read 6, iclass 19, count 0 2006.257.20:22:36.86#ibcon#end of sib2, iclass 19, count 0 2006.257.20:22:36.86#ibcon#*after write, iclass 19, count 0 2006.257.20:22:36.86#ibcon#*before return 0, iclass 19, count 0 2006.257.20:22:36.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:36.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:36.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:22:36.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:22:36.86$vck44/valo=8,884.99 2006.257.20:22:36.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.20:22:36.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.20:22:36.86#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:36.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:36.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:36.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:36.86#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:22:36.86#ibcon#first serial, iclass 21, count 0 2006.257.20:22:36.86#ibcon#enter sib2, iclass 21, count 0 2006.257.20:22:36.86#ibcon#flushed, iclass 21, count 0 2006.257.20:22:36.86#ibcon#about to write, iclass 21, count 0 2006.257.20:22:36.86#ibcon#wrote, iclass 21, count 0 2006.257.20:22:36.86#ibcon#about to read 3, iclass 21, count 0 2006.257.20:22:36.88#ibcon#read 3, iclass 21, count 0 2006.257.20:22:36.88#ibcon#about to read 4, iclass 21, count 0 2006.257.20:22:36.88#ibcon#read 4, iclass 21, count 0 2006.257.20:22:36.88#ibcon#about to read 5, iclass 21, count 0 2006.257.20:22:36.88#ibcon#read 5, iclass 21, count 0 2006.257.20:22:36.88#ibcon#about to read 6, iclass 21, count 0 2006.257.20:22:36.88#ibcon#read 6, iclass 21, count 0 2006.257.20:22:36.88#ibcon#end of sib2, iclass 21, count 0 2006.257.20:22:36.88#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:22:36.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:22:36.88#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.20:22:36.88#ibcon#*before write, iclass 21, count 0 2006.257.20:22:36.88#ibcon#enter sib2, iclass 21, count 0 2006.257.20:22:36.88#ibcon#flushed, iclass 21, count 0 2006.257.20:22:36.88#ibcon#about to write, iclass 21, count 0 2006.257.20:22:36.88#ibcon#wrote, iclass 21, count 0 2006.257.20:22:36.88#ibcon#about to read 3, iclass 21, count 0 2006.257.20:22:36.92#ibcon#read 3, iclass 21, count 0 2006.257.20:22:36.92#ibcon#about to read 4, iclass 21, count 0 2006.257.20:22:36.92#ibcon#read 4, iclass 21, count 0 2006.257.20:22:36.92#ibcon#about to read 5, iclass 21, count 0 2006.257.20:22:36.92#ibcon#read 5, iclass 21, count 0 2006.257.20:22:36.92#ibcon#about to read 6, iclass 21, count 0 2006.257.20:22:36.92#ibcon#read 6, iclass 21, count 0 2006.257.20:22:36.92#ibcon#end of sib2, iclass 21, count 0 2006.257.20:22:36.92#ibcon#*after write, iclass 21, count 0 2006.257.20:22:36.92#ibcon#*before return 0, iclass 21, count 0 2006.257.20:22:36.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:36.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:36.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:22:36.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:22:36.92$vck44/va=8,4 2006.257.20:22:36.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.20:22:36.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.20:22:36.92#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:36.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:36.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:36.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:36.98#ibcon#enter wrdev, iclass 23, count 2 2006.257.20:22:36.98#ibcon#first serial, iclass 23, count 2 2006.257.20:22:36.98#ibcon#enter sib2, iclass 23, count 2 2006.257.20:22:36.98#ibcon#flushed, iclass 23, count 2 2006.257.20:22:36.98#ibcon#about to write, iclass 23, count 2 2006.257.20:22:36.98#ibcon#wrote, iclass 23, count 2 2006.257.20:22:36.98#ibcon#about to read 3, iclass 23, count 2 2006.257.20:22:37.00#ibcon#read 3, iclass 23, count 2 2006.257.20:22:37.00#ibcon#about to read 4, iclass 23, count 2 2006.257.20:22:37.00#ibcon#read 4, iclass 23, count 2 2006.257.20:22:37.00#ibcon#about to read 5, iclass 23, count 2 2006.257.20:22:37.00#ibcon#read 5, iclass 23, count 2 2006.257.20:22:37.00#ibcon#about to read 6, iclass 23, count 2 2006.257.20:22:37.00#ibcon#read 6, iclass 23, count 2 2006.257.20:22:37.00#ibcon#end of sib2, iclass 23, count 2 2006.257.20:22:37.00#ibcon#*mode == 0, iclass 23, count 2 2006.257.20:22:37.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.20:22:37.00#ibcon#[25=AT08-04\r\n] 2006.257.20:22:37.00#ibcon#*before write, iclass 23, count 2 2006.257.20:22:37.00#ibcon#enter sib2, iclass 23, count 2 2006.257.20:22:37.00#ibcon#flushed, iclass 23, count 2 2006.257.20:22:37.00#ibcon#about to write, iclass 23, count 2 2006.257.20:22:37.00#ibcon#wrote, iclass 23, count 2 2006.257.20:22:37.00#ibcon#about to read 3, iclass 23, count 2 2006.257.20:22:37.03#ibcon#read 3, iclass 23, count 2 2006.257.20:22:37.03#ibcon#about to read 4, iclass 23, count 2 2006.257.20:22:37.03#ibcon#read 4, iclass 23, count 2 2006.257.20:22:37.03#ibcon#about to read 5, iclass 23, count 2 2006.257.20:22:37.03#ibcon#read 5, iclass 23, count 2 2006.257.20:22:37.03#ibcon#about to read 6, iclass 23, count 2 2006.257.20:22:37.03#ibcon#read 6, iclass 23, count 2 2006.257.20:22:37.03#ibcon#end of sib2, iclass 23, count 2 2006.257.20:22:37.03#ibcon#*after write, iclass 23, count 2 2006.257.20:22:37.03#ibcon#*before return 0, iclass 23, count 2 2006.257.20:22:37.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:37.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:37.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.20:22:37.03#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:37.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:37.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:37.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:37.15#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:22:37.15#ibcon#first serial, iclass 23, count 0 2006.257.20:22:37.15#ibcon#enter sib2, iclass 23, count 0 2006.257.20:22:37.15#ibcon#flushed, iclass 23, count 0 2006.257.20:22:37.15#ibcon#about to write, iclass 23, count 0 2006.257.20:22:37.15#ibcon#wrote, iclass 23, count 0 2006.257.20:22:37.15#ibcon#about to read 3, iclass 23, count 0 2006.257.20:22:37.17#ibcon#read 3, iclass 23, count 0 2006.257.20:22:37.17#ibcon#about to read 4, iclass 23, count 0 2006.257.20:22:37.17#ibcon#read 4, iclass 23, count 0 2006.257.20:22:37.17#ibcon#about to read 5, iclass 23, count 0 2006.257.20:22:37.17#ibcon#read 5, iclass 23, count 0 2006.257.20:22:37.17#ibcon#about to read 6, iclass 23, count 0 2006.257.20:22:37.17#ibcon#read 6, iclass 23, count 0 2006.257.20:22:37.17#ibcon#end of sib2, iclass 23, count 0 2006.257.20:22:37.17#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:22:37.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:22:37.17#ibcon#[25=USB\r\n] 2006.257.20:22:37.17#ibcon#*before write, iclass 23, count 0 2006.257.20:22:37.17#ibcon#enter sib2, iclass 23, count 0 2006.257.20:22:37.17#ibcon#flushed, iclass 23, count 0 2006.257.20:22:37.17#ibcon#about to write, iclass 23, count 0 2006.257.20:22:37.17#ibcon#wrote, iclass 23, count 0 2006.257.20:22:37.17#ibcon#about to read 3, iclass 23, count 0 2006.257.20:22:37.20#ibcon#read 3, iclass 23, count 0 2006.257.20:22:37.20#ibcon#about to read 4, iclass 23, count 0 2006.257.20:22:37.20#ibcon#read 4, iclass 23, count 0 2006.257.20:22:37.20#ibcon#about to read 5, iclass 23, count 0 2006.257.20:22:37.20#ibcon#read 5, iclass 23, count 0 2006.257.20:22:37.20#ibcon#about to read 6, iclass 23, count 0 2006.257.20:22:37.20#ibcon#read 6, iclass 23, count 0 2006.257.20:22:37.20#ibcon#end of sib2, iclass 23, count 0 2006.257.20:22:37.20#ibcon#*after write, iclass 23, count 0 2006.257.20:22:37.20#ibcon#*before return 0, iclass 23, count 0 2006.257.20:22:37.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:37.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:37.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:22:37.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:22:37.20$vck44/vblo=1,629.99 2006.257.20:22:37.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.20:22:37.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.20:22:37.20#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:37.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:37.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:37.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:37.20#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:22:37.20#ibcon#first serial, iclass 25, count 0 2006.257.20:22:37.20#ibcon#enter sib2, iclass 25, count 0 2006.257.20:22:37.20#ibcon#flushed, iclass 25, count 0 2006.257.20:22:37.20#ibcon#about to write, iclass 25, count 0 2006.257.20:22:37.20#ibcon#wrote, iclass 25, count 0 2006.257.20:22:37.20#ibcon#about to read 3, iclass 25, count 0 2006.257.20:22:37.22#ibcon#read 3, iclass 25, count 0 2006.257.20:22:37.22#ibcon#about to read 4, iclass 25, count 0 2006.257.20:22:37.22#ibcon#read 4, iclass 25, count 0 2006.257.20:22:37.22#ibcon#about to read 5, iclass 25, count 0 2006.257.20:22:37.22#ibcon#read 5, iclass 25, count 0 2006.257.20:22:37.22#ibcon#about to read 6, iclass 25, count 0 2006.257.20:22:37.22#ibcon#read 6, iclass 25, count 0 2006.257.20:22:37.22#ibcon#end of sib2, iclass 25, count 0 2006.257.20:22:37.22#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:22:37.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:22:37.22#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.20:22:37.22#ibcon#*before write, iclass 25, count 0 2006.257.20:22:37.22#ibcon#enter sib2, iclass 25, count 0 2006.257.20:22:37.22#ibcon#flushed, iclass 25, count 0 2006.257.20:22:37.22#ibcon#about to write, iclass 25, count 0 2006.257.20:22:37.22#ibcon#wrote, iclass 25, count 0 2006.257.20:22:37.22#ibcon#about to read 3, iclass 25, count 0 2006.257.20:22:37.26#ibcon#read 3, iclass 25, count 0 2006.257.20:22:37.26#ibcon#about to read 4, iclass 25, count 0 2006.257.20:22:37.26#ibcon#read 4, iclass 25, count 0 2006.257.20:22:37.26#ibcon#about to read 5, iclass 25, count 0 2006.257.20:22:37.26#ibcon#read 5, iclass 25, count 0 2006.257.20:22:37.26#ibcon#about to read 6, iclass 25, count 0 2006.257.20:22:37.26#ibcon#read 6, iclass 25, count 0 2006.257.20:22:37.26#ibcon#end of sib2, iclass 25, count 0 2006.257.20:22:37.26#ibcon#*after write, iclass 25, count 0 2006.257.20:22:37.26#ibcon#*before return 0, iclass 25, count 0 2006.257.20:22:37.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:37.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:37.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:22:37.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:22:37.26$vck44/vb=1,4 2006.257.20:22:37.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.20:22:37.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.20:22:37.26#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:37.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:22:37.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:22:37.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:22:37.26#ibcon#enter wrdev, iclass 27, count 2 2006.257.20:22:37.26#ibcon#first serial, iclass 27, count 2 2006.257.20:22:37.26#ibcon#enter sib2, iclass 27, count 2 2006.257.20:22:37.26#ibcon#flushed, iclass 27, count 2 2006.257.20:22:37.26#ibcon#about to write, iclass 27, count 2 2006.257.20:22:37.26#ibcon#wrote, iclass 27, count 2 2006.257.20:22:37.26#ibcon#about to read 3, iclass 27, count 2 2006.257.20:22:37.28#ibcon#read 3, iclass 27, count 2 2006.257.20:22:37.28#ibcon#about to read 4, iclass 27, count 2 2006.257.20:22:37.28#ibcon#read 4, iclass 27, count 2 2006.257.20:22:37.28#ibcon#about to read 5, iclass 27, count 2 2006.257.20:22:37.28#ibcon#read 5, iclass 27, count 2 2006.257.20:22:37.28#ibcon#about to read 6, iclass 27, count 2 2006.257.20:22:37.28#ibcon#read 6, iclass 27, count 2 2006.257.20:22:37.28#ibcon#end of sib2, iclass 27, count 2 2006.257.20:22:37.28#ibcon#*mode == 0, iclass 27, count 2 2006.257.20:22:37.28#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.20:22:37.28#ibcon#[27=AT01-04\r\n] 2006.257.20:22:37.28#ibcon#*before write, iclass 27, count 2 2006.257.20:22:37.28#ibcon#enter sib2, iclass 27, count 2 2006.257.20:22:37.28#ibcon#flushed, iclass 27, count 2 2006.257.20:22:37.28#ibcon#about to write, iclass 27, count 2 2006.257.20:22:37.28#ibcon#wrote, iclass 27, count 2 2006.257.20:22:37.28#ibcon#about to read 3, iclass 27, count 2 2006.257.20:22:37.31#ibcon#read 3, iclass 27, count 2 2006.257.20:22:37.31#ibcon#about to read 4, iclass 27, count 2 2006.257.20:22:37.31#ibcon#read 4, iclass 27, count 2 2006.257.20:22:37.31#ibcon#about to read 5, iclass 27, count 2 2006.257.20:22:37.31#ibcon#read 5, iclass 27, count 2 2006.257.20:22:37.31#ibcon#about to read 6, iclass 27, count 2 2006.257.20:22:37.31#ibcon#read 6, iclass 27, count 2 2006.257.20:22:37.31#ibcon#end of sib2, iclass 27, count 2 2006.257.20:22:37.31#ibcon#*after write, iclass 27, count 2 2006.257.20:22:37.31#ibcon#*before return 0, iclass 27, count 2 2006.257.20:22:37.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:22:37.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:22:37.31#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.20:22:37.31#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:37.31#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:22:37.43#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:22:37.43#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:22:37.43#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:22:37.43#ibcon#first serial, iclass 27, count 0 2006.257.20:22:37.43#ibcon#enter sib2, iclass 27, count 0 2006.257.20:22:37.43#ibcon#flushed, iclass 27, count 0 2006.257.20:22:37.43#ibcon#about to write, iclass 27, count 0 2006.257.20:22:37.43#ibcon#wrote, iclass 27, count 0 2006.257.20:22:37.43#ibcon#about to read 3, iclass 27, count 0 2006.257.20:22:37.45#ibcon#read 3, iclass 27, count 0 2006.257.20:22:37.45#ibcon#about to read 4, iclass 27, count 0 2006.257.20:22:37.45#ibcon#read 4, iclass 27, count 0 2006.257.20:22:37.45#ibcon#about to read 5, iclass 27, count 0 2006.257.20:22:37.45#ibcon#read 5, iclass 27, count 0 2006.257.20:22:37.45#ibcon#about to read 6, iclass 27, count 0 2006.257.20:22:37.45#ibcon#read 6, iclass 27, count 0 2006.257.20:22:37.45#ibcon#end of sib2, iclass 27, count 0 2006.257.20:22:37.45#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:22:37.45#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:22:37.45#ibcon#[27=USB\r\n] 2006.257.20:22:37.45#ibcon#*before write, iclass 27, count 0 2006.257.20:22:37.45#ibcon#enter sib2, iclass 27, count 0 2006.257.20:22:37.45#ibcon#flushed, iclass 27, count 0 2006.257.20:22:37.45#ibcon#about to write, iclass 27, count 0 2006.257.20:22:37.45#ibcon#wrote, iclass 27, count 0 2006.257.20:22:37.45#ibcon#about to read 3, iclass 27, count 0 2006.257.20:22:37.48#ibcon#read 3, iclass 27, count 0 2006.257.20:22:37.48#ibcon#about to read 4, iclass 27, count 0 2006.257.20:22:37.48#ibcon#read 4, iclass 27, count 0 2006.257.20:22:37.48#ibcon#about to read 5, iclass 27, count 0 2006.257.20:22:37.48#ibcon#read 5, iclass 27, count 0 2006.257.20:22:37.48#ibcon#about to read 6, iclass 27, count 0 2006.257.20:22:37.48#ibcon#read 6, iclass 27, count 0 2006.257.20:22:37.48#ibcon#end of sib2, iclass 27, count 0 2006.257.20:22:37.48#ibcon#*after write, iclass 27, count 0 2006.257.20:22:37.48#ibcon#*before return 0, iclass 27, count 0 2006.257.20:22:37.48#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:22:37.48#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:22:37.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:22:37.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:22:37.48$vck44/vblo=2,634.99 2006.257.20:22:37.48#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.20:22:37.48#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.20:22:37.48#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:37.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:37.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:37.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:37.48#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:22:37.48#ibcon#first serial, iclass 29, count 0 2006.257.20:22:37.48#ibcon#enter sib2, iclass 29, count 0 2006.257.20:22:37.48#ibcon#flushed, iclass 29, count 0 2006.257.20:22:37.48#ibcon#about to write, iclass 29, count 0 2006.257.20:22:37.48#ibcon#wrote, iclass 29, count 0 2006.257.20:22:37.48#ibcon#about to read 3, iclass 29, count 0 2006.257.20:22:37.50#ibcon#read 3, iclass 29, count 0 2006.257.20:22:37.50#ibcon#about to read 4, iclass 29, count 0 2006.257.20:22:37.50#ibcon#read 4, iclass 29, count 0 2006.257.20:22:37.50#ibcon#about to read 5, iclass 29, count 0 2006.257.20:22:37.50#ibcon#read 5, iclass 29, count 0 2006.257.20:22:37.50#ibcon#about to read 6, iclass 29, count 0 2006.257.20:22:37.50#ibcon#read 6, iclass 29, count 0 2006.257.20:22:37.50#ibcon#end of sib2, iclass 29, count 0 2006.257.20:22:37.50#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:22:37.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:22:37.50#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.20:22:37.50#ibcon#*before write, iclass 29, count 0 2006.257.20:22:37.50#ibcon#enter sib2, iclass 29, count 0 2006.257.20:22:37.50#ibcon#flushed, iclass 29, count 0 2006.257.20:22:37.50#ibcon#about to write, iclass 29, count 0 2006.257.20:22:37.50#ibcon#wrote, iclass 29, count 0 2006.257.20:22:37.50#ibcon#about to read 3, iclass 29, count 0 2006.257.20:22:37.54#ibcon#read 3, iclass 29, count 0 2006.257.20:22:37.54#ibcon#about to read 4, iclass 29, count 0 2006.257.20:22:37.54#ibcon#read 4, iclass 29, count 0 2006.257.20:22:37.54#ibcon#about to read 5, iclass 29, count 0 2006.257.20:22:37.54#ibcon#read 5, iclass 29, count 0 2006.257.20:22:37.54#ibcon#about to read 6, iclass 29, count 0 2006.257.20:22:37.54#ibcon#read 6, iclass 29, count 0 2006.257.20:22:37.54#ibcon#end of sib2, iclass 29, count 0 2006.257.20:22:37.54#ibcon#*after write, iclass 29, count 0 2006.257.20:22:37.54#ibcon#*before return 0, iclass 29, count 0 2006.257.20:22:37.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:37.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:22:37.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:22:37.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:22:37.54$vck44/vb=2,5 2006.257.20:22:37.54#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.20:22:37.54#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.20:22:37.54#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:37.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:37.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:37.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:37.60#ibcon#enter wrdev, iclass 31, count 2 2006.257.20:22:37.60#ibcon#first serial, iclass 31, count 2 2006.257.20:22:37.60#ibcon#enter sib2, iclass 31, count 2 2006.257.20:22:37.60#ibcon#flushed, iclass 31, count 2 2006.257.20:22:37.60#ibcon#about to write, iclass 31, count 2 2006.257.20:22:37.60#ibcon#wrote, iclass 31, count 2 2006.257.20:22:37.60#ibcon#about to read 3, iclass 31, count 2 2006.257.20:22:37.62#ibcon#read 3, iclass 31, count 2 2006.257.20:22:37.62#ibcon#about to read 4, iclass 31, count 2 2006.257.20:22:37.62#ibcon#read 4, iclass 31, count 2 2006.257.20:22:37.62#ibcon#about to read 5, iclass 31, count 2 2006.257.20:22:37.62#ibcon#read 5, iclass 31, count 2 2006.257.20:22:37.62#ibcon#about to read 6, iclass 31, count 2 2006.257.20:22:37.62#ibcon#read 6, iclass 31, count 2 2006.257.20:22:37.62#ibcon#end of sib2, iclass 31, count 2 2006.257.20:22:37.62#ibcon#*mode == 0, iclass 31, count 2 2006.257.20:22:37.62#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.20:22:37.62#ibcon#[27=AT02-05\r\n] 2006.257.20:22:37.62#ibcon#*before write, iclass 31, count 2 2006.257.20:22:37.62#ibcon#enter sib2, iclass 31, count 2 2006.257.20:22:37.62#ibcon#flushed, iclass 31, count 2 2006.257.20:22:37.62#ibcon#about to write, iclass 31, count 2 2006.257.20:22:37.62#ibcon#wrote, iclass 31, count 2 2006.257.20:22:37.62#ibcon#about to read 3, iclass 31, count 2 2006.257.20:22:37.65#ibcon#read 3, iclass 31, count 2 2006.257.20:22:37.65#ibcon#about to read 4, iclass 31, count 2 2006.257.20:22:37.65#ibcon#read 4, iclass 31, count 2 2006.257.20:22:37.65#ibcon#about to read 5, iclass 31, count 2 2006.257.20:22:37.65#ibcon#read 5, iclass 31, count 2 2006.257.20:22:37.65#ibcon#about to read 6, iclass 31, count 2 2006.257.20:22:37.65#ibcon#read 6, iclass 31, count 2 2006.257.20:22:37.65#ibcon#end of sib2, iclass 31, count 2 2006.257.20:22:37.65#ibcon#*after write, iclass 31, count 2 2006.257.20:22:37.65#ibcon#*before return 0, iclass 31, count 2 2006.257.20:22:37.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:37.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:22:37.65#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.20:22:37.65#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:37.65#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:37.77#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:37.77#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:37.77#ibcon#enter wrdev, iclass 31, count 0 2006.257.20:22:37.77#ibcon#first serial, iclass 31, count 0 2006.257.20:22:37.77#ibcon#enter sib2, iclass 31, count 0 2006.257.20:22:37.77#ibcon#flushed, iclass 31, count 0 2006.257.20:22:37.77#ibcon#about to write, iclass 31, count 0 2006.257.20:22:37.77#ibcon#wrote, iclass 31, count 0 2006.257.20:22:37.77#ibcon#about to read 3, iclass 31, count 0 2006.257.20:22:37.79#ibcon#read 3, iclass 31, count 0 2006.257.20:22:37.79#ibcon#about to read 4, iclass 31, count 0 2006.257.20:22:37.79#ibcon#read 4, iclass 31, count 0 2006.257.20:22:37.79#ibcon#about to read 5, iclass 31, count 0 2006.257.20:22:37.79#ibcon#read 5, iclass 31, count 0 2006.257.20:22:37.79#ibcon#about to read 6, iclass 31, count 0 2006.257.20:22:37.79#ibcon#read 6, iclass 31, count 0 2006.257.20:22:37.79#ibcon#end of sib2, iclass 31, count 0 2006.257.20:22:37.79#ibcon#*mode == 0, iclass 31, count 0 2006.257.20:22:37.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.20:22:37.79#ibcon#[27=USB\r\n] 2006.257.20:22:37.79#ibcon#*before write, iclass 31, count 0 2006.257.20:22:37.79#ibcon#enter sib2, iclass 31, count 0 2006.257.20:22:37.79#ibcon#flushed, iclass 31, count 0 2006.257.20:22:37.79#ibcon#about to write, iclass 31, count 0 2006.257.20:22:37.79#ibcon#wrote, iclass 31, count 0 2006.257.20:22:37.79#ibcon#about to read 3, iclass 31, count 0 2006.257.20:22:37.82#ibcon#read 3, iclass 31, count 0 2006.257.20:22:37.82#ibcon#about to read 4, iclass 31, count 0 2006.257.20:22:37.82#ibcon#read 4, iclass 31, count 0 2006.257.20:22:37.82#ibcon#about to read 5, iclass 31, count 0 2006.257.20:22:37.82#ibcon#read 5, iclass 31, count 0 2006.257.20:22:37.82#ibcon#about to read 6, iclass 31, count 0 2006.257.20:22:37.82#ibcon#read 6, iclass 31, count 0 2006.257.20:22:37.82#ibcon#end of sib2, iclass 31, count 0 2006.257.20:22:37.82#ibcon#*after write, iclass 31, count 0 2006.257.20:22:37.82#ibcon#*before return 0, iclass 31, count 0 2006.257.20:22:37.82#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:37.82#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:22:37.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.20:22:37.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.20:22:37.82$vck44/vblo=3,649.99 2006.257.20:22:37.82#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.20:22:37.82#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.20:22:37.82#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:37.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:37.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:37.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:37.82#ibcon#enter wrdev, iclass 33, count 0 2006.257.20:22:37.82#ibcon#first serial, iclass 33, count 0 2006.257.20:22:37.82#ibcon#enter sib2, iclass 33, count 0 2006.257.20:22:37.82#ibcon#flushed, iclass 33, count 0 2006.257.20:22:37.82#ibcon#about to write, iclass 33, count 0 2006.257.20:22:37.82#ibcon#wrote, iclass 33, count 0 2006.257.20:22:37.82#ibcon#about to read 3, iclass 33, count 0 2006.257.20:22:37.84#ibcon#read 3, iclass 33, count 0 2006.257.20:22:37.84#ibcon#about to read 4, iclass 33, count 0 2006.257.20:22:37.84#ibcon#read 4, iclass 33, count 0 2006.257.20:22:37.84#ibcon#about to read 5, iclass 33, count 0 2006.257.20:22:37.84#ibcon#read 5, iclass 33, count 0 2006.257.20:22:37.84#ibcon#about to read 6, iclass 33, count 0 2006.257.20:22:37.84#ibcon#read 6, iclass 33, count 0 2006.257.20:22:37.84#ibcon#end of sib2, iclass 33, count 0 2006.257.20:22:37.84#ibcon#*mode == 0, iclass 33, count 0 2006.257.20:22:37.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.20:22:37.84#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.20:22:37.84#ibcon#*before write, iclass 33, count 0 2006.257.20:22:37.84#ibcon#enter sib2, iclass 33, count 0 2006.257.20:22:37.84#ibcon#flushed, iclass 33, count 0 2006.257.20:22:37.84#ibcon#about to write, iclass 33, count 0 2006.257.20:22:37.84#ibcon#wrote, iclass 33, count 0 2006.257.20:22:37.84#ibcon#about to read 3, iclass 33, count 0 2006.257.20:22:37.88#ibcon#read 3, iclass 33, count 0 2006.257.20:22:37.88#ibcon#about to read 4, iclass 33, count 0 2006.257.20:22:37.88#ibcon#read 4, iclass 33, count 0 2006.257.20:22:37.88#ibcon#about to read 5, iclass 33, count 0 2006.257.20:22:37.88#ibcon#read 5, iclass 33, count 0 2006.257.20:22:37.88#ibcon#about to read 6, iclass 33, count 0 2006.257.20:22:37.88#ibcon#read 6, iclass 33, count 0 2006.257.20:22:37.88#ibcon#end of sib2, iclass 33, count 0 2006.257.20:22:37.88#ibcon#*after write, iclass 33, count 0 2006.257.20:22:37.88#ibcon#*before return 0, iclass 33, count 0 2006.257.20:22:37.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:37.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:22:37.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.20:22:37.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.20:22:37.88$vck44/vb=3,4 2006.257.20:22:37.88#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.20:22:37.88#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.20:22:37.88#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:37.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:37.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:37.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:37.94#ibcon#enter wrdev, iclass 35, count 2 2006.257.20:22:37.94#ibcon#first serial, iclass 35, count 2 2006.257.20:22:37.94#ibcon#enter sib2, iclass 35, count 2 2006.257.20:22:37.94#ibcon#flushed, iclass 35, count 2 2006.257.20:22:37.94#ibcon#about to write, iclass 35, count 2 2006.257.20:22:37.94#ibcon#wrote, iclass 35, count 2 2006.257.20:22:37.94#ibcon#about to read 3, iclass 35, count 2 2006.257.20:22:37.96#ibcon#read 3, iclass 35, count 2 2006.257.20:22:37.96#ibcon#about to read 4, iclass 35, count 2 2006.257.20:22:37.96#ibcon#read 4, iclass 35, count 2 2006.257.20:22:37.96#ibcon#about to read 5, iclass 35, count 2 2006.257.20:22:37.96#ibcon#read 5, iclass 35, count 2 2006.257.20:22:37.96#ibcon#about to read 6, iclass 35, count 2 2006.257.20:22:37.96#ibcon#read 6, iclass 35, count 2 2006.257.20:22:37.96#ibcon#end of sib2, iclass 35, count 2 2006.257.20:22:37.96#ibcon#*mode == 0, iclass 35, count 2 2006.257.20:22:37.96#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.20:22:37.96#ibcon#[27=AT03-04\r\n] 2006.257.20:22:37.96#ibcon#*before write, iclass 35, count 2 2006.257.20:22:37.96#ibcon#enter sib2, iclass 35, count 2 2006.257.20:22:37.96#ibcon#flushed, iclass 35, count 2 2006.257.20:22:37.96#ibcon#about to write, iclass 35, count 2 2006.257.20:22:37.96#ibcon#wrote, iclass 35, count 2 2006.257.20:22:37.96#ibcon#about to read 3, iclass 35, count 2 2006.257.20:22:37.99#ibcon#read 3, iclass 35, count 2 2006.257.20:22:37.99#ibcon#about to read 4, iclass 35, count 2 2006.257.20:22:37.99#ibcon#read 4, iclass 35, count 2 2006.257.20:22:37.99#ibcon#about to read 5, iclass 35, count 2 2006.257.20:22:37.99#ibcon#read 5, iclass 35, count 2 2006.257.20:22:37.99#ibcon#about to read 6, iclass 35, count 2 2006.257.20:22:37.99#ibcon#read 6, iclass 35, count 2 2006.257.20:22:37.99#ibcon#end of sib2, iclass 35, count 2 2006.257.20:22:37.99#ibcon#*after write, iclass 35, count 2 2006.257.20:22:37.99#ibcon#*before return 0, iclass 35, count 2 2006.257.20:22:37.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:37.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:22:37.99#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.20:22:37.99#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:37.99#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:38.11#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:38.11#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:38.11#ibcon#enter wrdev, iclass 35, count 0 2006.257.20:22:38.11#ibcon#first serial, iclass 35, count 0 2006.257.20:22:38.11#ibcon#enter sib2, iclass 35, count 0 2006.257.20:22:38.11#ibcon#flushed, iclass 35, count 0 2006.257.20:22:38.11#ibcon#about to write, iclass 35, count 0 2006.257.20:22:38.11#ibcon#wrote, iclass 35, count 0 2006.257.20:22:38.11#ibcon#about to read 3, iclass 35, count 0 2006.257.20:22:38.13#ibcon#read 3, iclass 35, count 0 2006.257.20:22:38.13#ibcon#about to read 4, iclass 35, count 0 2006.257.20:22:38.13#ibcon#read 4, iclass 35, count 0 2006.257.20:22:38.13#ibcon#about to read 5, iclass 35, count 0 2006.257.20:22:38.13#ibcon#read 5, iclass 35, count 0 2006.257.20:22:38.13#ibcon#about to read 6, iclass 35, count 0 2006.257.20:22:38.13#ibcon#read 6, iclass 35, count 0 2006.257.20:22:38.13#ibcon#end of sib2, iclass 35, count 0 2006.257.20:22:38.13#ibcon#*mode == 0, iclass 35, count 0 2006.257.20:22:38.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.20:22:38.13#ibcon#[27=USB\r\n] 2006.257.20:22:38.13#ibcon#*before write, iclass 35, count 0 2006.257.20:22:38.13#ibcon#enter sib2, iclass 35, count 0 2006.257.20:22:38.13#ibcon#flushed, iclass 35, count 0 2006.257.20:22:38.13#ibcon#about to write, iclass 35, count 0 2006.257.20:22:38.13#ibcon#wrote, iclass 35, count 0 2006.257.20:22:38.13#ibcon#about to read 3, iclass 35, count 0 2006.257.20:22:38.16#ibcon#read 3, iclass 35, count 0 2006.257.20:22:38.16#ibcon#about to read 4, iclass 35, count 0 2006.257.20:22:38.16#ibcon#read 4, iclass 35, count 0 2006.257.20:22:38.16#ibcon#about to read 5, iclass 35, count 0 2006.257.20:22:38.16#ibcon#read 5, iclass 35, count 0 2006.257.20:22:38.16#ibcon#about to read 6, iclass 35, count 0 2006.257.20:22:38.16#ibcon#read 6, iclass 35, count 0 2006.257.20:22:38.16#ibcon#end of sib2, iclass 35, count 0 2006.257.20:22:38.16#ibcon#*after write, iclass 35, count 0 2006.257.20:22:38.16#ibcon#*before return 0, iclass 35, count 0 2006.257.20:22:38.16#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:38.16#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:22:38.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.20:22:38.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.20:22:38.16$vck44/vblo=4,679.99 2006.257.20:22:38.16#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.20:22:38.16#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.20:22:38.16#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:38.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:38.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:38.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:38.16#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:22:38.16#ibcon#first serial, iclass 37, count 0 2006.257.20:22:38.16#ibcon#enter sib2, iclass 37, count 0 2006.257.20:22:38.16#ibcon#flushed, iclass 37, count 0 2006.257.20:22:38.16#ibcon#about to write, iclass 37, count 0 2006.257.20:22:38.16#ibcon#wrote, iclass 37, count 0 2006.257.20:22:38.16#ibcon#about to read 3, iclass 37, count 0 2006.257.20:22:38.18#ibcon#read 3, iclass 37, count 0 2006.257.20:22:38.18#ibcon#about to read 4, iclass 37, count 0 2006.257.20:22:38.18#ibcon#read 4, iclass 37, count 0 2006.257.20:22:38.18#ibcon#about to read 5, iclass 37, count 0 2006.257.20:22:38.18#ibcon#read 5, iclass 37, count 0 2006.257.20:22:38.18#ibcon#about to read 6, iclass 37, count 0 2006.257.20:22:38.18#ibcon#read 6, iclass 37, count 0 2006.257.20:22:38.18#ibcon#end of sib2, iclass 37, count 0 2006.257.20:22:38.18#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:22:38.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:22:38.18#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.20:22:38.18#ibcon#*before write, iclass 37, count 0 2006.257.20:22:38.18#ibcon#enter sib2, iclass 37, count 0 2006.257.20:22:38.18#ibcon#flushed, iclass 37, count 0 2006.257.20:22:38.18#ibcon#about to write, iclass 37, count 0 2006.257.20:22:38.18#ibcon#wrote, iclass 37, count 0 2006.257.20:22:38.18#ibcon#about to read 3, iclass 37, count 0 2006.257.20:22:38.22#ibcon#read 3, iclass 37, count 0 2006.257.20:22:38.22#ibcon#about to read 4, iclass 37, count 0 2006.257.20:22:38.22#ibcon#read 4, iclass 37, count 0 2006.257.20:22:38.22#ibcon#about to read 5, iclass 37, count 0 2006.257.20:22:38.22#ibcon#read 5, iclass 37, count 0 2006.257.20:22:38.22#ibcon#about to read 6, iclass 37, count 0 2006.257.20:22:38.22#ibcon#read 6, iclass 37, count 0 2006.257.20:22:38.22#ibcon#end of sib2, iclass 37, count 0 2006.257.20:22:38.22#ibcon#*after write, iclass 37, count 0 2006.257.20:22:38.22#ibcon#*before return 0, iclass 37, count 0 2006.257.20:22:38.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:38.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:22:38.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:22:38.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:22:38.22$vck44/vb=4,5 2006.257.20:22:38.22#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.20:22:38.22#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.20:22:38.22#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:38.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:38.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:38.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:38.28#ibcon#enter wrdev, iclass 39, count 2 2006.257.20:22:38.28#ibcon#first serial, iclass 39, count 2 2006.257.20:22:38.28#ibcon#enter sib2, iclass 39, count 2 2006.257.20:22:38.28#ibcon#flushed, iclass 39, count 2 2006.257.20:22:38.28#ibcon#about to write, iclass 39, count 2 2006.257.20:22:38.28#ibcon#wrote, iclass 39, count 2 2006.257.20:22:38.28#ibcon#about to read 3, iclass 39, count 2 2006.257.20:22:38.30#ibcon#read 3, iclass 39, count 2 2006.257.20:22:38.30#ibcon#about to read 4, iclass 39, count 2 2006.257.20:22:38.30#ibcon#read 4, iclass 39, count 2 2006.257.20:22:38.30#ibcon#about to read 5, iclass 39, count 2 2006.257.20:22:38.30#ibcon#read 5, iclass 39, count 2 2006.257.20:22:38.30#ibcon#about to read 6, iclass 39, count 2 2006.257.20:22:38.30#ibcon#read 6, iclass 39, count 2 2006.257.20:22:38.30#ibcon#end of sib2, iclass 39, count 2 2006.257.20:22:38.30#ibcon#*mode == 0, iclass 39, count 2 2006.257.20:22:38.30#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.20:22:38.30#ibcon#[27=AT04-05\r\n] 2006.257.20:22:38.30#ibcon#*before write, iclass 39, count 2 2006.257.20:22:38.30#ibcon#enter sib2, iclass 39, count 2 2006.257.20:22:38.30#ibcon#flushed, iclass 39, count 2 2006.257.20:22:38.30#ibcon#about to write, iclass 39, count 2 2006.257.20:22:38.30#ibcon#wrote, iclass 39, count 2 2006.257.20:22:38.30#ibcon#about to read 3, iclass 39, count 2 2006.257.20:22:38.33#ibcon#read 3, iclass 39, count 2 2006.257.20:22:38.33#ibcon#about to read 4, iclass 39, count 2 2006.257.20:22:38.33#ibcon#read 4, iclass 39, count 2 2006.257.20:22:38.33#ibcon#about to read 5, iclass 39, count 2 2006.257.20:22:38.33#ibcon#read 5, iclass 39, count 2 2006.257.20:22:38.33#ibcon#about to read 6, iclass 39, count 2 2006.257.20:22:38.33#ibcon#read 6, iclass 39, count 2 2006.257.20:22:38.33#ibcon#end of sib2, iclass 39, count 2 2006.257.20:22:38.33#ibcon#*after write, iclass 39, count 2 2006.257.20:22:38.33#ibcon#*before return 0, iclass 39, count 2 2006.257.20:22:38.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:38.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:22:38.33#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.20:22:38.33#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:38.33#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:38.45#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:38.45#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:38.45#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:22:38.45#ibcon#first serial, iclass 39, count 0 2006.257.20:22:38.45#ibcon#enter sib2, iclass 39, count 0 2006.257.20:22:38.45#ibcon#flushed, iclass 39, count 0 2006.257.20:22:38.45#ibcon#about to write, iclass 39, count 0 2006.257.20:22:38.45#ibcon#wrote, iclass 39, count 0 2006.257.20:22:38.45#ibcon#about to read 3, iclass 39, count 0 2006.257.20:22:38.47#ibcon#read 3, iclass 39, count 0 2006.257.20:22:38.47#ibcon#about to read 4, iclass 39, count 0 2006.257.20:22:38.47#ibcon#read 4, iclass 39, count 0 2006.257.20:22:38.47#ibcon#about to read 5, iclass 39, count 0 2006.257.20:22:38.47#ibcon#read 5, iclass 39, count 0 2006.257.20:22:38.47#ibcon#about to read 6, iclass 39, count 0 2006.257.20:22:38.47#ibcon#read 6, iclass 39, count 0 2006.257.20:22:38.47#ibcon#end of sib2, iclass 39, count 0 2006.257.20:22:38.47#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:22:38.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:22:38.47#ibcon#[27=USB\r\n] 2006.257.20:22:38.47#ibcon#*before write, iclass 39, count 0 2006.257.20:22:38.47#ibcon#enter sib2, iclass 39, count 0 2006.257.20:22:38.47#ibcon#flushed, iclass 39, count 0 2006.257.20:22:38.47#ibcon#about to write, iclass 39, count 0 2006.257.20:22:38.47#ibcon#wrote, iclass 39, count 0 2006.257.20:22:38.47#ibcon#about to read 3, iclass 39, count 0 2006.257.20:22:38.50#ibcon#read 3, iclass 39, count 0 2006.257.20:22:38.50#ibcon#about to read 4, iclass 39, count 0 2006.257.20:22:38.50#ibcon#read 4, iclass 39, count 0 2006.257.20:22:38.50#ibcon#about to read 5, iclass 39, count 0 2006.257.20:22:38.50#ibcon#read 5, iclass 39, count 0 2006.257.20:22:38.50#ibcon#about to read 6, iclass 39, count 0 2006.257.20:22:38.50#ibcon#read 6, iclass 39, count 0 2006.257.20:22:38.50#ibcon#end of sib2, iclass 39, count 0 2006.257.20:22:38.50#ibcon#*after write, iclass 39, count 0 2006.257.20:22:38.50#ibcon#*before return 0, iclass 39, count 0 2006.257.20:22:38.50#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:38.50#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:22:38.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:22:38.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:22:38.50$vck44/vblo=5,709.99 2006.257.20:22:38.50#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.20:22:38.50#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.20:22:38.50#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:38.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:38.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:38.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:38.50#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:22:38.50#ibcon#first serial, iclass 3, count 0 2006.257.20:22:38.50#ibcon#enter sib2, iclass 3, count 0 2006.257.20:22:38.50#ibcon#flushed, iclass 3, count 0 2006.257.20:22:38.50#ibcon#about to write, iclass 3, count 0 2006.257.20:22:38.50#ibcon#wrote, iclass 3, count 0 2006.257.20:22:38.50#ibcon#about to read 3, iclass 3, count 0 2006.257.20:22:38.52#ibcon#read 3, iclass 3, count 0 2006.257.20:22:38.52#ibcon#about to read 4, iclass 3, count 0 2006.257.20:22:38.52#ibcon#read 4, iclass 3, count 0 2006.257.20:22:38.52#ibcon#about to read 5, iclass 3, count 0 2006.257.20:22:38.52#ibcon#read 5, iclass 3, count 0 2006.257.20:22:38.52#ibcon#about to read 6, iclass 3, count 0 2006.257.20:22:38.52#ibcon#read 6, iclass 3, count 0 2006.257.20:22:38.52#ibcon#end of sib2, iclass 3, count 0 2006.257.20:22:38.52#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:22:38.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:22:38.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.20:22:38.52#ibcon#*before write, iclass 3, count 0 2006.257.20:22:38.52#ibcon#enter sib2, iclass 3, count 0 2006.257.20:22:38.52#ibcon#flushed, iclass 3, count 0 2006.257.20:22:38.52#ibcon#about to write, iclass 3, count 0 2006.257.20:22:38.52#ibcon#wrote, iclass 3, count 0 2006.257.20:22:38.52#ibcon#about to read 3, iclass 3, count 0 2006.257.20:22:38.56#ibcon#read 3, iclass 3, count 0 2006.257.20:22:38.56#ibcon#about to read 4, iclass 3, count 0 2006.257.20:22:38.56#ibcon#read 4, iclass 3, count 0 2006.257.20:22:38.56#ibcon#about to read 5, iclass 3, count 0 2006.257.20:22:38.56#ibcon#read 5, iclass 3, count 0 2006.257.20:22:38.56#ibcon#about to read 6, iclass 3, count 0 2006.257.20:22:38.56#ibcon#read 6, iclass 3, count 0 2006.257.20:22:38.56#ibcon#end of sib2, iclass 3, count 0 2006.257.20:22:38.56#ibcon#*after write, iclass 3, count 0 2006.257.20:22:38.56#ibcon#*before return 0, iclass 3, count 0 2006.257.20:22:38.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:38.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:22:38.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:22:38.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:22:38.56$vck44/vb=5,4 2006.257.20:22:38.56#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.20:22:38.56#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.20:22:38.56#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:38.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:22:38.61#abcon#<5=/14 0.9 2.4 17.14 971014.8\r\n> 2006.257.20:22:38.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:22:38.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:22:38.62#ibcon#enter wrdev, iclass 6, count 2 2006.257.20:22:38.62#ibcon#first serial, iclass 6, count 2 2006.257.20:22:38.62#ibcon#enter sib2, iclass 6, count 2 2006.257.20:22:38.62#ibcon#flushed, iclass 6, count 2 2006.257.20:22:38.62#ibcon#about to write, iclass 6, count 2 2006.257.20:22:38.62#ibcon#wrote, iclass 6, count 2 2006.257.20:22:38.62#ibcon#about to read 3, iclass 6, count 2 2006.257.20:22:38.63#abcon#{5=INTERFACE CLEAR} 2006.257.20:22:38.64#ibcon#read 3, iclass 6, count 2 2006.257.20:22:38.64#ibcon#about to read 4, iclass 6, count 2 2006.257.20:22:38.64#ibcon#read 4, iclass 6, count 2 2006.257.20:22:38.64#ibcon#about to read 5, iclass 6, count 2 2006.257.20:22:38.64#ibcon#read 5, iclass 6, count 2 2006.257.20:22:38.64#ibcon#about to read 6, iclass 6, count 2 2006.257.20:22:38.64#ibcon#read 6, iclass 6, count 2 2006.257.20:22:38.64#ibcon#end of sib2, iclass 6, count 2 2006.257.20:22:38.64#ibcon#*mode == 0, iclass 6, count 2 2006.257.20:22:38.64#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.20:22:38.64#ibcon#[27=AT05-04\r\n] 2006.257.20:22:38.64#ibcon#*before write, iclass 6, count 2 2006.257.20:22:38.64#ibcon#enter sib2, iclass 6, count 2 2006.257.20:22:38.64#ibcon#flushed, iclass 6, count 2 2006.257.20:22:38.64#ibcon#about to write, iclass 6, count 2 2006.257.20:22:38.64#ibcon#wrote, iclass 6, count 2 2006.257.20:22:38.64#ibcon#about to read 3, iclass 6, count 2 2006.257.20:22:38.67#ibcon#read 3, iclass 6, count 2 2006.257.20:22:38.67#ibcon#about to read 4, iclass 6, count 2 2006.257.20:22:38.67#ibcon#read 4, iclass 6, count 2 2006.257.20:22:38.67#ibcon#about to read 5, iclass 6, count 2 2006.257.20:22:38.67#ibcon#read 5, iclass 6, count 2 2006.257.20:22:38.67#ibcon#about to read 6, iclass 6, count 2 2006.257.20:22:38.67#ibcon#read 6, iclass 6, count 2 2006.257.20:22:38.67#ibcon#end of sib2, iclass 6, count 2 2006.257.20:22:38.67#ibcon#*after write, iclass 6, count 2 2006.257.20:22:38.67#ibcon#*before return 0, iclass 6, count 2 2006.257.20:22:38.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:22:38.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:22:38.67#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.20:22:38.67#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:38.67#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:22:38.69#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:22:38.79#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:22:38.79#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:22:38.79#ibcon#enter wrdev, iclass 6, count 0 2006.257.20:22:38.79#ibcon#first serial, iclass 6, count 0 2006.257.20:22:38.79#ibcon#enter sib2, iclass 6, count 0 2006.257.20:22:38.79#ibcon#flushed, iclass 6, count 0 2006.257.20:22:38.79#ibcon#about to write, iclass 6, count 0 2006.257.20:22:38.79#ibcon#wrote, iclass 6, count 0 2006.257.20:22:38.79#ibcon#about to read 3, iclass 6, count 0 2006.257.20:22:38.81#ibcon#read 3, iclass 6, count 0 2006.257.20:22:38.81#ibcon#about to read 4, iclass 6, count 0 2006.257.20:22:38.81#ibcon#read 4, iclass 6, count 0 2006.257.20:22:38.81#ibcon#about to read 5, iclass 6, count 0 2006.257.20:22:38.81#ibcon#read 5, iclass 6, count 0 2006.257.20:22:38.81#ibcon#about to read 6, iclass 6, count 0 2006.257.20:22:38.81#ibcon#read 6, iclass 6, count 0 2006.257.20:22:38.81#ibcon#end of sib2, iclass 6, count 0 2006.257.20:22:38.81#ibcon#*mode == 0, iclass 6, count 0 2006.257.20:22:38.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.20:22:38.81#ibcon#[27=USB\r\n] 2006.257.20:22:38.81#ibcon#*before write, iclass 6, count 0 2006.257.20:22:38.81#ibcon#enter sib2, iclass 6, count 0 2006.257.20:22:38.81#ibcon#flushed, iclass 6, count 0 2006.257.20:22:38.81#ibcon#about to write, iclass 6, count 0 2006.257.20:22:38.81#ibcon#wrote, iclass 6, count 0 2006.257.20:22:38.81#ibcon#about to read 3, iclass 6, count 0 2006.257.20:22:38.84#ibcon#read 3, iclass 6, count 0 2006.257.20:22:38.84#ibcon#about to read 4, iclass 6, count 0 2006.257.20:22:38.84#ibcon#read 4, iclass 6, count 0 2006.257.20:22:38.84#ibcon#about to read 5, iclass 6, count 0 2006.257.20:22:38.84#ibcon#read 5, iclass 6, count 0 2006.257.20:22:38.84#ibcon#about to read 6, iclass 6, count 0 2006.257.20:22:38.84#ibcon#read 6, iclass 6, count 0 2006.257.20:22:38.84#ibcon#end of sib2, iclass 6, count 0 2006.257.20:22:38.84#ibcon#*after write, iclass 6, count 0 2006.257.20:22:38.84#ibcon#*before return 0, iclass 6, count 0 2006.257.20:22:38.84#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:22:38.84#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:22:38.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.20:22:38.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.20:22:38.84$vck44/vblo=6,719.99 2006.257.20:22:38.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.20:22:38.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.20:22:38.84#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:38.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:38.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:38.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:38.84#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:22:38.84#ibcon#first serial, iclass 13, count 0 2006.257.20:22:38.84#ibcon#enter sib2, iclass 13, count 0 2006.257.20:22:38.84#ibcon#flushed, iclass 13, count 0 2006.257.20:22:38.84#ibcon#about to write, iclass 13, count 0 2006.257.20:22:38.84#ibcon#wrote, iclass 13, count 0 2006.257.20:22:38.84#ibcon#about to read 3, iclass 13, count 0 2006.257.20:22:38.86#ibcon#read 3, iclass 13, count 0 2006.257.20:22:38.86#ibcon#about to read 4, iclass 13, count 0 2006.257.20:22:38.86#ibcon#read 4, iclass 13, count 0 2006.257.20:22:38.86#ibcon#about to read 5, iclass 13, count 0 2006.257.20:22:38.86#ibcon#read 5, iclass 13, count 0 2006.257.20:22:38.86#ibcon#about to read 6, iclass 13, count 0 2006.257.20:22:38.86#ibcon#read 6, iclass 13, count 0 2006.257.20:22:38.86#ibcon#end of sib2, iclass 13, count 0 2006.257.20:22:38.86#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:22:38.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:22:38.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.20:22:38.86#ibcon#*before write, iclass 13, count 0 2006.257.20:22:38.86#ibcon#enter sib2, iclass 13, count 0 2006.257.20:22:38.86#ibcon#flushed, iclass 13, count 0 2006.257.20:22:38.86#ibcon#about to write, iclass 13, count 0 2006.257.20:22:38.86#ibcon#wrote, iclass 13, count 0 2006.257.20:22:38.86#ibcon#about to read 3, iclass 13, count 0 2006.257.20:22:38.90#ibcon#read 3, iclass 13, count 0 2006.257.20:22:38.90#ibcon#about to read 4, iclass 13, count 0 2006.257.20:22:38.90#ibcon#read 4, iclass 13, count 0 2006.257.20:22:38.90#ibcon#about to read 5, iclass 13, count 0 2006.257.20:22:38.90#ibcon#read 5, iclass 13, count 0 2006.257.20:22:38.90#ibcon#about to read 6, iclass 13, count 0 2006.257.20:22:38.90#ibcon#read 6, iclass 13, count 0 2006.257.20:22:38.90#ibcon#end of sib2, iclass 13, count 0 2006.257.20:22:38.90#ibcon#*after write, iclass 13, count 0 2006.257.20:22:38.90#ibcon#*before return 0, iclass 13, count 0 2006.257.20:22:38.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:38.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:22:38.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:22:38.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:22:38.90$vck44/vb=6,4 2006.257.20:22:38.90#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.20:22:38.90#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.20:22:38.90#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:38.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:38.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:38.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:38.96#ibcon#enter wrdev, iclass 15, count 2 2006.257.20:22:38.96#ibcon#first serial, iclass 15, count 2 2006.257.20:22:38.96#ibcon#enter sib2, iclass 15, count 2 2006.257.20:22:38.96#ibcon#flushed, iclass 15, count 2 2006.257.20:22:38.96#ibcon#about to write, iclass 15, count 2 2006.257.20:22:38.96#ibcon#wrote, iclass 15, count 2 2006.257.20:22:38.96#ibcon#about to read 3, iclass 15, count 2 2006.257.20:22:38.98#ibcon#read 3, iclass 15, count 2 2006.257.20:22:38.98#ibcon#about to read 4, iclass 15, count 2 2006.257.20:22:38.98#ibcon#read 4, iclass 15, count 2 2006.257.20:22:38.98#ibcon#about to read 5, iclass 15, count 2 2006.257.20:22:38.98#ibcon#read 5, iclass 15, count 2 2006.257.20:22:38.98#ibcon#about to read 6, iclass 15, count 2 2006.257.20:22:38.98#ibcon#read 6, iclass 15, count 2 2006.257.20:22:38.98#ibcon#end of sib2, iclass 15, count 2 2006.257.20:22:38.98#ibcon#*mode == 0, iclass 15, count 2 2006.257.20:22:38.98#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.20:22:38.98#ibcon#[27=AT06-04\r\n] 2006.257.20:22:38.98#ibcon#*before write, iclass 15, count 2 2006.257.20:22:38.98#ibcon#enter sib2, iclass 15, count 2 2006.257.20:22:38.98#ibcon#flushed, iclass 15, count 2 2006.257.20:22:38.98#ibcon#about to write, iclass 15, count 2 2006.257.20:22:38.98#ibcon#wrote, iclass 15, count 2 2006.257.20:22:38.98#ibcon#about to read 3, iclass 15, count 2 2006.257.20:22:39.01#ibcon#read 3, iclass 15, count 2 2006.257.20:22:39.01#ibcon#about to read 4, iclass 15, count 2 2006.257.20:22:39.01#ibcon#read 4, iclass 15, count 2 2006.257.20:22:39.01#ibcon#about to read 5, iclass 15, count 2 2006.257.20:22:39.01#ibcon#read 5, iclass 15, count 2 2006.257.20:22:39.01#ibcon#about to read 6, iclass 15, count 2 2006.257.20:22:39.01#ibcon#read 6, iclass 15, count 2 2006.257.20:22:39.01#ibcon#end of sib2, iclass 15, count 2 2006.257.20:22:39.01#ibcon#*after write, iclass 15, count 2 2006.257.20:22:39.01#ibcon#*before return 0, iclass 15, count 2 2006.257.20:22:39.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:39.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:22:39.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.20:22:39.01#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:39.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:39.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:39.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:39.13#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:22:39.13#ibcon#first serial, iclass 15, count 0 2006.257.20:22:39.13#ibcon#enter sib2, iclass 15, count 0 2006.257.20:22:39.13#ibcon#flushed, iclass 15, count 0 2006.257.20:22:39.13#ibcon#about to write, iclass 15, count 0 2006.257.20:22:39.13#ibcon#wrote, iclass 15, count 0 2006.257.20:22:39.13#ibcon#about to read 3, iclass 15, count 0 2006.257.20:22:39.15#ibcon#read 3, iclass 15, count 0 2006.257.20:22:39.15#ibcon#about to read 4, iclass 15, count 0 2006.257.20:22:39.15#ibcon#read 4, iclass 15, count 0 2006.257.20:22:39.15#ibcon#about to read 5, iclass 15, count 0 2006.257.20:22:39.15#ibcon#read 5, iclass 15, count 0 2006.257.20:22:39.15#ibcon#about to read 6, iclass 15, count 0 2006.257.20:22:39.15#ibcon#read 6, iclass 15, count 0 2006.257.20:22:39.15#ibcon#end of sib2, iclass 15, count 0 2006.257.20:22:39.15#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:22:39.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:22:39.15#ibcon#[27=USB\r\n] 2006.257.20:22:39.15#ibcon#*before write, iclass 15, count 0 2006.257.20:22:39.15#ibcon#enter sib2, iclass 15, count 0 2006.257.20:22:39.15#ibcon#flushed, iclass 15, count 0 2006.257.20:22:39.15#ibcon#about to write, iclass 15, count 0 2006.257.20:22:39.15#ibcon#wrote, iclass 15, count 0 2006.257.20:22:39.15#ibcon#about to read 3, iclass 15, count 0 2006.257.20:22:39.18#ibcon#read 3, iclass 15, count 0 2006.257.20:22:39.18#ibcon#about to read 4, iclass 15, count 0 2006.257.20:22:39.18#ibcon#read 4, iclass 15, count 0 2006.257.20:22:39.18#ibcon#about to read 5, iclass 15, count 0 2006.257.20:22:39.18#ibcon#read 5, iclass 15, count 0 2006.257.20:22:39.18#ibcon#about to read 6, iclass 15, count 0 2006.257.20:22:39.18#ibcon#read 6, iclass 15, count 0 2006.257.20:22:39.18#ibcon#end of sib2, iclass 15, count 0 2006.257.20:22:39.18#ibcon#*after write, iclass 15, count 0 2006.257.20:22:39.18#ibcon#*before return 0, iclass 15, count 0 2006.257.20:22:39.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:39.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:22:39.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:22:39.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:22:39.18$vck44/vblo=7,734.99 2006.257.20:22:39.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.20:22:39.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.20:22:39.18#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:39.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:39.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:39.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:39.18#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:22:39.18#ibcon#first serial, iclass 17, count 0 2006.257.20:22:39.18#ibcon#enter sib2, iclass 17, count 0 2006.257.20:22:39.18#ibcon#flushed, iclass 17, count 0 2006.257.20:22:39.18#ibcon#about to write, iclass 17, count 0 2006.257.20:22:39.18#ibcon#wrote, iclass 17, count 0 2006.257.20:22:39.18#ibcon#about to read 3, iclass 17, count 0 2006.257.20:22:39.20#ibcon#read 3, iclass 17, count 0 2006.257.20:22:39.20#ibcon#about to read 4, iclass 17, count 0 2006.257.20:22:39.20#ibcon#read 4, iclass 17, count 0 2006.257.20:22:39.20#ibcon#about to read 5, iclass 17, count 0 2006.257.20:22:39.20#ibcon#read 5, iclass 17, count 0 2006.257.20:22:39.20#ibcon#about to read 6, iclass 17, count 0 2006.257.20:22:39.20#ibcon#read 6, iclass 17, count 0 2006.257.20:22:39.20#ibcon#end of sib2, iclass 17, count 0 2006.257.20:22:39.20#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:22:39.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:22:39.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.20:22:39.20#ibcon#*before write, iclass 17, count 0 2006.257.20:22:39.20#ibcon#enter sib2, iclass 17, count 0 2006.257.20:22:39.20#ibcon#flushed, iclass 17, count 0 2006.257.20:22:39.20#ibcon#about to write, iclass 17, count 0 2006.257.20:22:39.20#ibcon#wrote, iclass 17, count 0 2006.257.20:22:39.20#ibcon#about to read 3, iclass 17, count 0 2006.257.20:22:39.24#ibcon#read 3, iclass 17, count 0 2006.257.20:22:39.24#ibcon#about to read 4, iclass 17, count 0 2006.257.20:22:39.24#ibcon#read 4, iclass 17, count 0 2006.257.20:22:39.24#ibcon#about to read 5, iclass 17, count 0 2006.257.20:22:39.24#ibcon#read 5, iclass 17, count 0 2006.257.20:22:39.24#ibcon#about to read 6, iclass 17, count 0 2006.257.20:22:39.24#ibcon#read 6, iclass 17, count 0 2006.257.20:22:39.24#ibcon#end of sib2, iclass 17, count 0 2006.257.20:22:39.24#ibcon#*after write, iclass 17, count 0 2006.257.20:22:39.24#ibcon#*before return 0, iclass 17, count 0 2006.257.20:22:39.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:39.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:22:39.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:22:39.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:22:39.24$vck44/vb=7,4 2006.257.20:22:39.24#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.20:22:39.24#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.20:22:39.24#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:39.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:39.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:39.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:39.30#ibcon#enter wrdev, iclass 19, count 2 2006.257.20:22:39.30#ibcon#first serial, iclass 19, count 2 2006.257.20:22:39.30#ibcon#enter sib2, iclass 19, count 2 2006.257.20:22:39.30#ibcon#flushed, iclass 19, count 2 2006.257.20:22:39.30#ibcon#about to write, iclass 19, count 2 2006.257.20:22:39.30#ibcon#wrote, iclass 19, count 2 2006.257.20:22:39.30#ibcon#about to read 3, iclass 19, count 2 2006.257.20:22:39.32#ibcon#read 3, iclass 19, count 2 2006.257.20:22:39.32#ibcon#about to read 4, iclass 19, count 2 2006.257.20:22:39.32#ibcon#read 4, iclass 19, count 2 2006.257.20:22:39.32#ibcon#about to read 5, iclass 19, count 2 2006.257.20:22:39.32#ibcon#read 5, iclass 19, count 2 2006.257.20:22:39.32#ibcon#about to read 6, iclass 19, count 2 2006.257.20:22:39.32#ibcon#read 6, iclass 19, count 2 2006.257.20:22:39.32#ibcon#end of sib2, iclass 19, count 2 2006.257.20:22:39.32#ibcon#*mode == 0, iclass 19, count 2 2006.257.20:22:39.32#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.20:22:39.32#ibcon#[27=AT07-04\r\n] 2006.257.20:22:39.32#ibcon#*before write, iclass 19, count 2 2006.257.20:22:39.32#ibcon#enter sib2, iclass 19, count 2 2006.257.20:22:39.32#ibcon#flushed, iclass 19, count 2 2006.257.20:22:39.32#ibcon#about to write, iclass 19, count 2 2006.257.20:22:39.32#ibcon#wrote, iclass 19, count 2 2006.257.20:22:39.32#ibcon#about to read 3, iclass 19, count 2 2006.257.20:22:39.35#ibcon#read 3, iclass 19, count 2 2006.257.20:22:39.35#ibcon#about to read 4, iclass 19, count 2 2006.257.20:22:39.35#ibcon#read 4, iclass 19, count 2 2006.257.20:22:39.35#ibcon#about to read 5, iclass 19, count 2 2006.257.20:22:39.35#ibcon#read 5, iclass 19, count 2 2006.257.20:22:39.35#ibcon#about to read 6, iclass 19, count 2 2006.257.20:22:39.35#ibcon#read 6, iclass 19, count 2 2006.257.20:22:39.35#ibcon#end of sib2, iclass 19, count 2 2006.257.20:22:39.35#ibcon#*after write, iclass 19, count 2 2006.257.20:22:39.35#ibcon#*before return 0, iclass 19, count 2 2006.257.20:22:39.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:39.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:22:39.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.20:22:39.35#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:39.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:39.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:39.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:39.47#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:22:39.47#ibcon#first serial, iclass 19, count 0 2006.257.20:22:39.47#ibcon#enter sib2, iclass 19, count 0 2006.257.20:22:39.47#ibcon#flushed, iclass 19, count 0 2006.257.20:22:39.47#ibcon#about to write, iclass 19, count 0 2006.257.20:22:39.47#ibcon#wrote, iclass 19, count 0 2006.257.20:22:39.47#ibcon#about to read 3, iclass 19, count 0 2006.257.20:22:39.49#ibcon#read 3, iclass 19, count 0 2006.257.20:22:39.49#ibcon#about to read 4, iclass 19, count 0 2006.257.20:22:39.49#ibcon#read 4, iclass 19, count 0 2006.257.20:22:39.49#ibcon#about to read 5, iclass 19, count 0 2006.257.20:22:39.49#ibcon#read 5, iclass 19, count 0 2006.257.20:22:39.49#ibcon#about to read 6, iclass 19, count 0 2006.257.20:22:39.49#ibcon#read 6, iclass 19, count 0 2006.257.20:22:39.49#ibcon#end of sib2, iclass 19, count 0 2006.257.20:22:39.49#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:22:39.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:22:39.49#ibcon#[27=USB\r\n] 2006.257.20:22:39.49#ibcon#*before write, iclass 19, count 0 2006.257.20:22:39.49#ibcon#enter sib2, iclass 19, count 0 2006.257.20:22:39.49#ibcon#flushed, iclass 19, count 0 2006.257.20:22:39.49#ibcon#about to write, iclass 19, count 0 2006.257.20:22:39.49#ibcon#wrote, iclass 19, count 0 2006.257.20:22:39.49#ibcon#about to read 3, iclass 19, count 0 2006.257.20:22:39.52#ibcon#read 3, iclass 19, count 0 2006.257.20:22:39.52#ibcon#about to read 4, iclass 19, count 0 2006.257.20:22:39.52#ibcon#read 4, iclass 19, count 0 2006.257.20:22:39.52#ibcon#about to read 5, iclass 19, count 0 2006.257.20:22:39.52#ibcon#read 5, iclass 19, count 0 2006.257.20:22:39.52#ibcon#about to read 6, iclass 19, count 0 2006.257.20:22:39.52#ibcon#read 6, iclass 19, count 0 2006.257.20:22:39.52#ibcon#end of sib2, iclass 19, count 0 2006.257.20:22:39.52#ibcon#*after write, iclass 19, count 0 2006.257.20:22:39.52#ibcon#*before return 0, iclass 19, count 0 2006.257.20:22:39.52#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:39.52#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:22:39.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:22:39.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:22:39.52$vck44/vblo=8,744.99 2006.257.20:22:39.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.20:22:39.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.20:22:39.52#ibcon#ireg 17 cls_cnt 0 2006.257.20:22:39.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:39.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:39.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:39.52#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:22:39.52#ibcon#first serial, iclass 21, count 0 2006.257.20:22:39.52#ibcon#enter sib2, iclass 21, count 0 2006.257.20:22:39.52#ibcon#flushed, iclass 21, count 0 2006.257.20:22:39.52#ibcon#about to write, iclass 21, count 0 2006.257.20:22:39.52#ibcon#wrote, iclass 21, count 0 2006.257.20:22:39.52#ibcon#about to read 3, iclass 21, count 0 2006.257.20:22:39.54#ibcon#read 3, iclass 21, count 0 2006.257.20:22:39.54#ibcon#about to read 4, iclass 21, count 0 2006.257.20:22:39.54#ibcon#read 4, iclass 21, count 0 2006.257.20:22:39.54#ibcon#about to read 5, iclass 21, count 0 2006.257.20:22:39.54#ibcon#read 5, iclass 21, count 0 2006.257.20:22:39.54#ibcon#about to read 6, iclass 21, count 0 2006.257.20:22:39.54#ibcon#read 6, iclass 21, count 0 2006.257.20:22:39.54#ibcon#end of sib2, iclass 21, count 0 2006.257.20:22:39.54#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:22:39.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:22:39.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.20:22:39.54#ibcon#*before write, iclass 21, count 0 2006.257.20:22:39.54#ibcon#enter sib2, iclass 21, count 0 2006.257.20:22:39.54#ibcon#flushed, iclass 21, count 0 2006.257.20:22:39.54#ibcon#about to write, iclass 21, count 0 2006.257.20:22:39.54#ibcon#wrote, iclass 21, count 0 2006.257.20:22:39.54#ibcon#about to read 3, iclass 21, count 0 2006.257.20:22:39.58#ibcon#read 3, iclass 21, count 0 2006.257.20:22:39.58#ibcon#about to read 4, iclass 21, count 0 2006.257.20:22:39.58#ibcon#read 4, iclass 21, count 0 2006.257.20:22:39.58#ibcon#about to read 5, iclass 21, count 0 2006.257.20:22:39.58#ibcon#read 5, iclass 21, count 0 2006.257.20:22:39.58#ibcon#about to read 6, iclass 21, count 0 2006.257.20:22:39.58#ibcon#read 6, iclass 21, count 0 2006.257.20:22:39.58#ibcon#end of sib2, iclass 21, count 0 2006.257.20:22:39.58#ibcon#*after write, iclass 21, count 0 2006.257.20:22:39.58#ibcon#*before return 0, iclass 21, count 0 2006.257.20:22:39.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:39.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:22:39.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:22:39.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:22:39.58$vck44/vb=8,4 2006.257.20:22:39.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.20:22:39.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.20:22:39.58#ibcon#ireg 11 cls_cnt 2 2006.257.20:22:39.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:39.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:39.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:39.64#ibcon#enter wrdev, iclass 23, count 2 2006.257.20:22:39.64#ibcon#first serial, iclass 23, count 2 2006.257.20:22:39.64#ibcon#enter sib2, iclass 23, count 2 2006.257.20:22:39.64#ibcon#flushed, iclass 23, count 2 2006.257.20:22:39.64#ibcon#about to write, iclass 23, count 2 2006.257.20:22:39.64#ibcon#wrote, iclass 23, count 2 2006.257.20:22:39.64#ibcon#about to read 3, iclass 23, count 2 2006.257.20:22:39.66#ibcon#read 3, iclass 23, count 2 2006.257.20:22:39.66#ibcon#about to read 4, iclass 23, count 2 2006.257.20:22:39.66#ibcon#read 4, iclass 23, count 2 2006.257.20:22:39.66#ibcon#about to read 5, iclass 23, count 2 2006.257.20:22:39.66#ibcon#read 5, iclass 23, count 2 2006.257.20:22:39.66#ibcon#about to read 6, iclass 23, count 2 2006.257.20:22:39.66#ibcon#read 6, iclass 23, count 2 2006.257.20:22:39.66#ibcon#end of sib2, iclass 23, count 2 2006.257.20:22:39.66#ibcon#*mode == 0, iclass 23, count 2 2006.257.20:22:39.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.20:22:39.66#ibcon#[27=AT08-04\r\n] 2006.257.20:22:39.66#ibcon#*before write, iclass 23, count 2 2006.257.20:22:39.66#ibcon#enter sib2, iclass 23, count 2 2006.257.20:22:39.66#ibcon#flushed, iclass 23, count 2 2006.257.20:22:39.66#ibcon#about to write, iclass 23, count 2 2006.257.20:22:39.66#ibcon#wrote, iclass 23, count 2 2006.257.20:22:39.66#ibcon#about to read 3, iclass 23, count 2 2006.257.20:22:39.69#ibcon#read 3, iclass 23, count 2 2006.257.20:22:39.69#ibcon#about to read 4, iclass 23, count 2 2006.257.20:22:39.69#ibcon#read 4, iclass 23, count 2 2006.257.20:22:39.69#ibcon#about to read 5, iclass 23, count 2 2006.257.20:22:39.69#ibcon#read 5, iclass 23, count 2 2006.257.20:22:39.69#ibcon#about to read 6, iclass 23, count 2 2006.257.20:22:39.69#ibcon#read 6, iclass 23, count 2 2006.257.20:22:39.69#ibcon#end of sib2, iclass 23, count 2 2006.257.20:22:39.69#ibcon#*after write, iclass 23, count 2 2006.257.20:22:39.69#ibcon#*before return 0, iclass 23, count 2 2006.257.20:22:39.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:39.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:22:39.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.20:22:39.69#ibcon#ireg 7 cls_cnt 0 2006.257.20:22:39.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:39.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:39.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:39.81#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:22:39.81#ibcon#first serial, iclass 23, count 0 2006.257.20:22:39.81#ibcon#enter sib2, iclass 23, count 0 2006.257.20:22:39.81#ibcon#flushed, iclass 23, count 0 2006.257.20:22:39.81#ibcon#about to write, iclass 23, count 0 2006.257.20:22:39.81#ibcon#wrote, iclass 23, count 0 2006.257.20:22:39.81#ibcon#about to read 3, iclass 23, count 0 2006.257.20:22:39.83#ibcon#read 3, iclass 23, count 0 2006.257.20:22:39.83#ibcon#about to read 4, iclass 23, count 0 2006.257.20:22:39.83#ibcon#read 4, iclass 23, count 0 2006.257.20:22:39.83#ibcon#about to read 5, iclass 23, count 0 2006.257.20:22:39.83#ibcon#read 5, iclass 23, count 0 2006.257.20:22:39.83#ibcon#about to read 6, iclass 23, count 0 2006.257.20:22:39.83#ibcon#read 6, iclass 23, count 0 2006.257.20:22:39.83#ibcon#end of sib2, iclass 23, count 0 2006.257.20:22:39.83#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:22:39.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:22:39.83#ibcon#[27=USB\r\n] 2006.257.20:22:39.83#ibcon#*before write, iclass 23, count 0 2006.257.20:22:39.83#ibcon#enter sib2, iclass 23, count 0 2006.257.20:22:39.83#ibcon#flushed, iclass 23, count 0 2006.257.20:22:39.83#ibcon#about to write, iclass 23, count 0 2006.257.20:22:39.83#ibcon#wrote, iclass 23, count 0 2006.257.20:22:39.83#ibcon#about to read 3, iclass 23, count 0 2006.257.20:22:39.86#ibcon#read 3, iclass 23, count 0 2006.257.20:22:39.86#ibcon#about to read 4, iclass 23, count 0 2006.257.20:22:39.86#ibcon#read 4, iclass 23, count 0 2006.257.20:22:39.86#ibcon#about to read 5, iclass 23, count 0 2006.257.20:22:39.86#ibcon#read 5, iclass 23, count 0 2006.257.20:22:39.86#ibcon#about to read 6, iclass 23, count 0 2006.257.20:22:39.86#ibcon#read 6, iclass 23, count 0 2006.257.20:22:39.86#ibcon#end of sib2, iclass 23, count 0 2006.257.20:22:39.86#ibcon#*after write, iclass 23, count 0 2006.257.20:22:39.86#ibcon#*before return 0, iclass 23, count 0 2006.257.20:22:39.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:39.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:22:39.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:22:39.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:22:39.86$vck44/vabw=wide 2006.257.20:22:39.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.20:22:39.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.20:22:39.86#ibcon#ireg 8 cls_cnt 0 2006.257.20:22:39.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:39.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:39.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:39.86#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:22:39.86#ibcon#first serial, iclass 25, count 0 2006.257.20:22:39.86#ibcon#enter sib2, iclass 25, count 0 2006.257.20:22:39.86#ibcon#flushed, iclass 25, count 0 2006.257.20:22:39.86#ibcon#about to write, iclass 25, count 0 2006.257.20:22:39.86#ibcon#wrote, iclass 25, count 0 2006.257.20:22:39.86#ibcon#about to read 3, iclass 25, count 0 2006.257.20:22:39.88#ibcon#read 3, iclass 25, count 0 2006.257.20:22:39.88#ibcon#about to read 4, iclass 25, count 0 2006.257.20:22:39.88#ibcon#read 4, iclass 25, count 0 2006.257.20:22:39.88#ibcon#about to read 5, iclass 25, count 0 2006.257.20:22:39.88#ibcon#read 5, iclass 25, count 0 2006.257.20:22:39.88#ibcon#about to read 6, iclass 25, count 0 2006.257.20:22:39.88#ibcon#read 6, iclass 25, count 0 2006.257.20:22:39.88#ibcon#end of sib2, iclass 25, count 0 2006.257.20:22:39.88#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:22:39.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:22:39.88#ibcon#[25=BW32\r\n] 2006.257.20:22:39.88#ibcon#*before write, iclass 25, count 0 2006.257.20:22:39.88#ibcon#enter sib2, iclass 25, count 0 2006.257.20:22:39.88#ibcon#flushed, iclass 25, count 0 2006.257.20:22:39.88#ibcon#about to write, iclass 25, count 0 2006.257.20:22:39.88#ibcon#wrote, iclass 25, count 0 2006.257.20:22:39.88#ibcon#about to read 3, iclass 25, count 0 2006.257.20:22:39.91#ibcon#read 3, iclass 25, count 0 2006.257.20:22:39.91#ibcon#about to read 4, iclass 25, count 0 2006.257.20:22:39.91#ibcon#read 4, iclass 25, count 0 2006.257.20:22:39.91#ibcon#about to read 5, iclass 25, count 0 2006.257.20:22:39.91#ibcon#read 5, iclass 25, count 0 2006.257.20:22:39.91#ibcon#about to read 6, iclass 25, count 0 2006.257.20:22:39.91#ibcon#read 6, iclass 25, count 0 2006.257.20:22:39.91#ibcon#end of sib2, iclass 25, count 0 2006.257.20:22:39.91#ibcon#*after write, iclass 25, count 0 2006.257.20:22:39.91#ibcon#*before return 0, iclass 25, count 0 2006.257.20:22:39.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:39.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:22:39.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:22:39.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:22:39.91$vck44/vbbw=wide 2006.257.20:22:39.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.20:22:39.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.20:22:39.91#ibcon#ireg 8 cls_cnt 0 2006.257.20:22:39.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:22:39.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:22:39.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:22:39.98#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:22:39.98#ibcon#first serial, iclass 27, count 0 2006.257.20:22:39.98#ibcon#enter sib2, iclass 27, count 0 2006.257.20:22:39.98#ibcon#flushed, iclass 27, count 0 2006.257.20:22:39.98#ibcon#about to write, iclass 27, count 0 2006.257.20:22:39.98#ibcon#wrote, iclass 27, count 0 2006.257.20:22:39.98#ibcon#about to read 3, iclass 27, count 0 2006.257.20:22:40.00#ibcon#read 3, iclass 27, count 0 2006.257.20:22:40.00#ibcon#about to read 4, iclass 27, count 0 2006.257.20:22:40.00#ibcon#read 4, iclass 27, count 0 2006.257.20:22:40.00#ibcon#about to read 5, iclass 27, count 0 2006.257.20:22:40.00#ibcon#read 5, iclass 27, count 0 2006.257.20:22:40.00#ibcon#about to read 6, iclass 27, count 0 2006.257.20:22:40.00#ibcon#read 6, iclass 27, count 0 2006.257.20:22:40.00#ibcon#end of sib2, iclass 27, count 0 2006.257.20:22:40.00#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:22:40.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:22:40.00#ibcon#[27=BW32\r\n] 2006.257.20:22:40.00#ibcon#*before write, iclass 27, count 0 2006.257.20:22:40.00#ibcon#enter sib2, iclass 27, count 0 2006.257.20:22:40.00#ibcon#flushed, iclass 27, count 0 2006.257.20:22:40.00#ibcon#about to write, iclass 27, count 0 2006.257.20:22:40.00#ibcon#wrote, iclass 27, count 0 2006.257.20:22:40.00#ibcon#about to read 3, iclass 27, count 0 2006.257.20:22:40.03#ibcon#read 3, iclass 27, count 0 2006.257.20:22:40.03#ibcon#about to read 4, iclass 27, count 0 2006.257.20:22:40.03#ibcon#read 4, iclass 27, count 0 2006.257.20:22:40.03#ibcon#about to read 5, iclass 27, count 0 2006.257.20:22:40.03#ibcon#read 5, iclass 27, count 0 2006.257.20:22:40.03#ibcon#about to read 6, iclass 27, count 0 2006.257.20:22:40.03#ibcon#read 6, iclass 27, count 0 2006.257.20:22:40.03#ibcon#end of sib2, iclass 27, count 0 2006.257.20:22:40.03#ibcon#*after write, iclass 27, count 0 2006.257.20:22:40.03#ibcon#*before return 0, iclass 27, count 0 2006.257.20:22:40.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:22:40.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:22:40.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:22:40.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:22:40.03$setupk4/ifdk4 2006.257.20:22:40.03$ifdk4/lo= 2006.257.20:22:40.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.20:22:40.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.20:22:40.03$ifdk4/patch= 2006.257.20:22:40.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.20:22:40.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.20:22:40.03$setupk4/!*+20s 2006.257.20:22:48.78#abcon#<5=/14 0.9 2.4 17.13 971014.8\r\n> 2006.257.20:22:48.80#abcon#{5=INTERFACE CLEAR} 2006.257.20:22:48.86#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:22:51.14#trakl#Source acquired 2006.257.20:22:52.14#flagr#flagr/antenna,acquired 2006.257.20:22:54.54$setupk4/"tpicd 2006.257.20:22:54.54$setupk4/echo=off 2006.257.20:22:54.54$setupk4/xlog=off 2006.257.20:22:54.54:!2006.257.20:28:45 2006.257.20:28:45.00:preob 2006.257.20:28:45.15/onsource/TRACKING 2006.257.20:28:45.15:!2006.257.20:28:55 2006.257.20:28:55.01:"tape 2006.257.20:28:55.02:"st=record 2006.257.20:28:55.02:data_valid=on 2006.257.20:28:55.02:midob 2006.257.20:28:56.15/onsource/TRACKING 2006.257.20:28:56.15/wx/17.09,1014.8,98 2006.257.20:28:56.22/cable/+6.4871E-03 2006.257.20:28:57.31/va/01,08,usb,yes,31,33 2006.257.20:28:57.31/va/02,07,usb,yes,34,34 2006.257.20:28:57.31/va/03,08,usb,yes,30,32 2006.257.20:28:57.31/va/04,07,usb,yes,34,36 2006.257.20:28:57.31/va/05,04,usb,yes,31,31 2006.257.20:28:57.31/va/06,04,usb,yes,34,34 2006.257.20:28:57.31/va/07,04,usb,yes,35,35 2006.257.20:28:57.31/va/08,04,usb,yes,29,36 2006.257.20:28:57.54/valo/01,524.99,yes,locked 2006.257.20:28:57.54/valo/02,534.99,yes,locked 2006.257.20:28:57.54/valo/03,564.99,yes,locked 2006.257.20:28:57.54/valo/04,624.99,yes,locked 2006.257.20:28:57.54/valo/05,734.99,yes,locked 2006.257.20:28:57.54/valo/06,814.99,yes,locked 2006.257.20:28:57.54/valo/07,864.99,yes,locked 2006.257.20:28:57.54/valo/08,884.99,yes,locked 2006.257.20:28:58.63/vb/01,04,usb,yes,30,28 2006.257.20:28:58.63/vb/02,05,usb,yes,29,28 2006.257.20:28:58.63/vb/03,04,usb,yes,29,32 2006.257.20:28:58.63/vb/04,05,usb,yes,30,29 2006.257.20:28:58.63/vb/05,04,usb,yes,26,29 2006.257.20:28:58.63/vb/06,04,usb,yes,31,27 2006.257.20:28:58.63/vb/07,04,usb,yes,30,30 2006.257.20:28:58.63/vb/08,04,usb,yes,28,31 2006.257.20:28:58.86/vblo/01,629.99,yes,locked 2006.257.20:28:58.86/vblo/02,634.99,yes,locked 2006.257.20:28:58.86/vblo/03,649.99,yes,locked 2006.257.20:28:58.86/vblo/04,679.99,yes,locked 2006.257.20:28:58.86/vblo/05,709.99,yes,locked 2006.257.20:28:58.86/vblo/06,719.99,yes,locked 2006.257.20:28:58.86/vblo/07,734.99,yes,locked 2006.257.20:28:58.86/vblo/08,744.99,yes,locked 2006.257.20:28:59.01/vabw/8 2006.257.20:28:59.16/vbbw/8 2006.257.20:28:59.25/xfe/off,on,15.2 2006.257.20:28:59.63/ifatt/23,28,28,28 2006.257.20:29:00.07/fmout-gps/S +4.57E-07 2006.257.20:29:00.12:!2006.257.20:33:55 2006.257.20:33:55.01:data_valid=off 2006.257.20:33:55.02:"et 2006.257.20:33:55.02:!+3s 2006.257.20:33:58.03:"tape 2006.257.20:33:58.04:postob 2006.257.20:33:58.19/cable/+6.4838E-03 2006.257.20:33:58.20/wx/17.10,1014.9,98 2006.257.20:33:58.25/fmout-gps/S +4.56E-07 2006.257.20:33:58.26:scan_name=257-2038,jd0609,60 2006.257.20:33:58.26:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.257.20:33:59.13#flagr#flagr/antenna,new-source 2006.257.20:33:59.14:checkk5 2006.257.20:33:59.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.20:33:59.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.20:34:00.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.20:34:00.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.20:34:00.85/chk_obsdata//k5ts1/T2572028??a.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.257.20:34:01.18/chk_obsdata//k5ts2/T2572028??b.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.257.20:34:01.51/chk_obsdata//k5ts3/T2572028??c.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.257.20:34:01.84/chk_obsdata//k5ts4/T2572028??d.dat file size is correct (nominal:1200MB, actual:1200MB). 2006.257.20:34:02.51/k5log//k5ts1_log_newline 2006.257.20:34:03.16/k5log//k5ts2_log_newline 2006.257.20:34:03.81/k5log//k5ts3_log_newline 2006.257.20:34:04.46/k5log//k5ts4_log_newline 2006.257.20:34:04.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.20:34:04.49:setupk4=1 2006.257.20:34:04.49$setupk4/echo=on 2006.257.20:34:04.49$setupk4/pcalon 2006.257.20:34:04.49$pcalon/"no phase cal control is implemented here 2006.257.20:34:04.49$setupk4/"tpicd=stop 2006.257.20:34:04.49$setupk4/"rec=synch_on 2006.257.20:34:04.49$setupk4/"rec_mode=128 2006.257.20:34:04.49$setupk4/!* 2006.257.20:34:04.49$setupk4/recpk4 2006.257.20:34:04.49$recpk4/recpatch= 2006.257.20:34:04.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.20:34:04.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.20:34:04.50$setupk4/vck44 2006.257.20:34:04.50$vck44/valo=1,524.99 2006.257.20:34:04.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.20:34:04.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.20:34:04.50#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:04.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:04.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:04.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:04.50#ibcon#enter wrdev, iclass 12, count 0 2006.257.20:34:04.50#ibcon#first serial, iclass 12, count 0 2006.257.20:34:04.50#ibcon#enter sib2, iclass 12, count 0 2006.257.20:34:04.50#ibcon#flushed, iclass 12, count 0 2006.257.20:34:04.50#ibcon#about to write, iclass 12, count 0 2006.257.20:34:04.50#ibcon#wrote, iclass 12, count 0 2006.257.20:34:04.50#ibcon#about to read 3, iclass 12, count 0 2006.257.20:34:04.51#ibcon#read 3, iclass 12, count 0 2006.257.20:34:04.51#ibcon#about to read 4, iclass 12, count 0 2006.257.20:34:04.51#ibcon#read 4, iclass 12, count 0 2006.257.20:34:04.51#ibcon#about to read 5, iclass 12, count 0 2006.257.20:34:04.51#ibcon#read 5, iclass 12, count 0 2006.257.20:34:04.51#ibcon#about to read 6, iclass 12, count 0 2006.257.20:34:04.51#ibcon#read 6, iclass 12, count 0 2006.257.20:34:04.51#ibcon#end of sib2, iclass 12, count 0 2006.257.20:34:04.51#ibcon#*mode == 0, iclass 12, count 0 2006.257.20:34:04.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.20:34:04.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.20:34:04.51#ibcon#*before write, iclass 12, count 0 2006.257.20:34:04.51#ibcon#enter sib2, iclass 12, count 0 2006.257.20:34:04.51#ibcon#flushed, iclass 12, count 0 2006.257.20:34:04.51#ibcon#about to write, iclass 12, count 0 2006.257.20:34:04.51#ibcon#wrote, iclass 12, count 0 2006.257.20:34:04.51#ibcon#about to read 3, iclass 12, count 0 2006.257.20:34:04.56#ibcon#read 3, iclass 12, count 0 2006.257.20:34:04.56#ibcon#about to read 4, iclass 12, count 0 2006.257.20:34:04.56#ibcon#read 4, iclass 12, count 0 2006.257.20:34:04.56#ibcon#about to read 5, iclass 12, count 0 2006.257.20:34:04.56#ibcon#read 5, iclass 12, count 0 2006.257.20:34:04.56#ibcon#about to read 6, iclass 12, count 0 2006.257.20:34:04.56#ibcon#read 6, iclass 12, count 0 2006.257.20:34:04.56#ibcon#end of sib2, iclass 12, count 0 2006.257.20:34:04.56#ibcon#*after write, iclass 12, count 0 2006.257.20:34:04.56#ibcon#*before return 0, iclass 12, count 0 2006.257.20:34:04.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:04.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:04.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.20:34:04.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.20:34:04.56$vck44/va=1,8 2006.257.20:34:04.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.20:34:04.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.20:34:04.56#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:04.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:04.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:04.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:04.56#ibcon#enter wrdev, iclass 14, count 2 2006.257.20:34:04.56#ibcon#first serial, iclass 14, count 2 2006.257.20:34:04.56#ibcon#enter sib2, iclass 14, count 2 2006.257.20:34:04.56#ibcon#flushed, iclass 14, count 2 2006.257.20:34:04.56#ibcon#about to write, iclass 14, count 2 2006.257.20:34:04.56#ibcon#wrote, iclass 14, count 2 2006.257.20:34:04.56#ibcon#about to read 3, iclass 14, count 2 2006.257.20:34:04.58#ibcon#read 3, iclass 14, count 2 2006.257.20:34:04.58#ibcon#about to read 4, iclass 14, count 2 2006.257.20:34:04.58#ibcon#read 4, iclass 14, count 2 2006.257.20:34:04.58#ibcon#about to read 5, iclass 14, count 2 2006.257.20:34:04.58#ibcon#read 5, iclass 14, count 2 2006.257.20:34:04.58#ibcon#about to read 6, iclass 14, count 2 2006.257.20:34:04.58#ibcon#read 6, iclass 14, count 2 2006.257.20:34:04.58#ibcon#end of sib2, iclass 14, count 2 2006.257.20:34:04.58#ibcon#*mode == 0, iclass 14, count 2 2006.257.20:34:04.58#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.20:34:04.58#ibcon#[25=AT01-08\r\n] 2006.257.20:34:04.58#ibcon#*before write, iclass 14, count 2 2006.257.20:34:04.58#ibcon#enter sib2, iclass 14, count 2 2006.257.20:34:04.58#ibcon#flushed, iclass 14, count 2 2006.257.20:34:04.58#ibcon#about to write, iclass 14, count 2 2006.257.20:34:04.58#ibcon#wrote, iclass 14, count 2 2006.257.20:34:04.58#ibcon#about to read 3, iclass 14, count 2 2006.257.20:34:04.61#ibcon#read 3, iclass 14, count 2 2006.257.20:34:04.61#ibcon#about to read 4, iclass 14, count 2 2006.257.20:34:04.61#ibcon#read 4, iclass 14, count 2 2006.257.20:34:04.61#ibcon#about to read 5, iclass 14, count 2 2006.257.20:34:04.61#ibcon#read 5, iclass 14, count 2 2006.257.20:34:04.61#ibcon#about to read 6, iclass 14, count 2 2006.257.20:34:04.61#ibcon#read 6, iclass 14, count 2 2006.257.20:34:04.61#ibcon#end of sib2, iclass 14, count 2 2006.257.20:34:04.61#ibcon#*after write, iclass 14, count 2 2006.257.20:34:04.61#ibcon#*before return 0, iclass 14, count 2 2006.257.20:34:04.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:04.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:04.61#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.20:34:04.61#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:04.61#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:04.73#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:04.73#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:04.73#ibcon#enter wrdev, iclass 14, count 0 2006.257.20:34:04.73#ibcon#first serial, iclass 14, count 0 2006.257.20:34:04.73#ibcon#enter sib2, iclass 14, count 0 2006.257.20:34:04.73#ibcon#flushed, iclass 14, count 0 2006.257.20:34:04.73#ibcon#about to write, iclass 14, count 0 2006.257.20:34:04.73#ibcon#wrote, iclass 14, count 0 2006.257.20:34:04.73#ibcon#about to read 3, iclass 14, count 0 2006.257.20:34:04.75#ibcon#read 3, iclass 14, count 0 2006.257.20:34:04.75#ibcon#about to read 4, iclass 14, count 0 2006.257.20:34:04.75#ibcon#read 4, iclass 14, count 0 2006.257.20:34:04.75#ibcon#about to read 5, iclass 14, count 0 2006.257.20:34:04.75#ibcon#read 5, iclass 14, count 0 2006.257.20:34:04.75#ibcon#about to read 6, iclass 14, count 0 2006.257.20:34:04.75#ibcon#read 6, iclass 14, count 0 2006.257.20:34:04.75#ibcon#end of sib2, iclass 14, count 0 2006.257.20:34:04.75#ibcon#*mode == 0, iclass 14, count 0 2006.257.20:34:04.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.20:34:04.75#ibcon#[25=USB\r\n] 2006.257.20:34:04.75#ibcon#*before write, iclass 14, count 0 2006.257.20:34:04.75#ibcon#enter sib2, iclass 14, count 0 2006.257.20:34:04.75#ibcon#flushed, iclass 14, count 0 2006.257.20:34:04.75#ibcon#about to write, iclass 14, count 0 2006.257.20:34:04.75#ibcon#wrote, iclass 14, count 0 2006.257.20:34:04.75#ibcon#about to read 3, iclass 14, count 0 2006.257.20:34:04.78#ibcon#read 3, iclass 14, count 0 2006.257.20:34:04.78#ibcon#about to read 4, iclass 14, count 0 2006.257.20:34:04.78#ibcon#read 4, iclass 14, count 0 2006.257.20:34:04.78#ibcon#about to read 5, iclass 14, count 0 2006.257.20:34:04.78#ibcon#read 5, iclass 14, count 0 2006.257.20:34:04.78#ibcon#about to read 6, iclass 14, count 0 2006.257.20:34:04.78#ibcon#read 6, iclass 14, count 0 2006.257.20:34:04.78#ibcon#end of sib2, iclass 14, count 0 2006.257.20:34:04.78#ibcon#*after write, iclass 14, count 0 2006.257.20:34:04.78#ibcon#*before return 0, iclass 14, count 0 2006.257.20:34:04.78#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:04.78#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:04.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.20:34:04.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.20:34:04.78$vck44/valo=2,534.99 2006.257.20:34:04.78#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.20:34:04.78#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.20:34:04.78#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:04.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:04.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:04.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:04.78#ibcon#enter wrdev, iclass 16, count 0 2006.257.20:34:04.78#ibcon#first serial, iclass 16, count 0 2006.257.20:34:04.78#ibcon#enter sib2, iclass 16, count 0 2006.257.20:34:04.78#ibcon#flushed, iclass 16, count 0 2006.257.20:34:04.78#ibcon#about to write, iclass 16, count 0 2006.257.20:34:04.78#ibcon#wrote, iclass 16, count 0 2006.257.20:34:04.78#ibcon#about to read 3, iclass 16, count 0 2006.257.20:34:04.80#ibcon#read 3, iclass 16, count 0 2006.257.20:34:04.80#ibcon#about to read 4, iclass 16, count 0 2006.257.20:34:04.80#ibcon#read 4, iclass 16, count 0 2006.257.20:34:04.80#ibcon#about to read 5, iclass 16, count 0 2006.257.20:34:04.80#ibcon#read 5, iclass 16, count 0 2006.257.20:34:04.80#ibcon#about to read 6, iclass 16, count 0 2006.257.20:34:04.80#ibcon#read 6, iclass 16, count 0 2006.257.20:34:04.80#ibcon#end of sib2, iclass 16, count 0 2006.257.20:34:04.80#ibcon#*mode == 0, iclass 16, count 0 2006.257.20:34:04.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.20:34:04.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.20:34:04.80#ibcon#*before write, iclass 16, count 0 2006.257.20:34:04.80#ibcon#enter sib2, iclass 16, count 0 2006.257.20:34:04.80#ibcon#flushed, iclass 16, count 0 2006.257.20:34:04.80#ibcon#about to write, iclass 16, count 0 2006.257.20:34:04.80#ibcon#wrote, iclass 16, count 0 2006.257.20:34:04.80#ibcon#about to read 3, iclass 16, count 0 2006.257.20:34:04.84#ibcon#read 3, iclass 16, count 0 2006.257.20:34:04.84#ibcon#about to read 4, iclass 16, count 0 2006.257.20:34:04.84#ibcon#read 4, iclass 16, count 0 2006.257.20:34:04.84#ibcon#about to read 5, iclass 16, count 0 2006.257.20:34:04.84#ibcon#read 5, iclass 16, count 0 2006.257.20:34:04.84#ibcon#about to read 6, iclass 16, count 0 2006.257.20:34:04.84#ibcon#read 6, iclass 16, count 0 2006.257.20:34:04.84#ibcon#end of sib2, iclass 16, count 0 2006.257.20:34:04.84#ibcon#*after write, iclass 16, count 0 2006.257.20:34:04.84#ibcon#*before return 0, iclass 16, count 0 2006.257.20:34:04.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:04.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:04.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.20:34:04.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.20:34:04.84$vck44/va=2,7 2006.257.20:34:04.84#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.20:34:04.84#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.20:34:04.84#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:04.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:04.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:04.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:04.90#ibcon#enter wrdev, iclass 18, count 2 2006.257.20:34:04.90#ibcon#first serial, iclass 18, count 2 2006.257.20:34:04.90#ibcon#enter sib2, iclass 18, count 2 2006.257.20:34:04.90#ibcon#flushed, iclass 18, count 2 2006.257.20:34:04.90#ibcon#about to write, iclass 18, count 2 2006.257.20:34:04.90#ibcon#wrote, iclass 18, count 2 2006.257.20:34:04.90#ibcon#about to read 3, iclass 18, count 2 2006.257.20:34:04.92#ibcon#read 3, iclass 18, count 2 2006.257.20:34:04.92#ibcon#about to read 4, iclass 18, count 2 2006.257.20:34:04.92#ibcon#read 4, iclass 18, count 2 2006.257.20:34:04.92#ibcon#about to read 5, iclass 18, count 2 2006.257.20:34:04.92#ibcon#read 5, iclass 18, count 2 2006.257.20:34:04.92#ibcon#about to read 6, iclass 18, count 2 2006.257.20:34:04.92#ibcon#read 6, iclass 18, count 2 2006.257.20:34:04.92#ibcon#end of sib2, iclass 18, count 2 2006.257.20:34:04.92#ibcon#*mode == 0, iclass 18, count 2 2006.257.20:34:04.92#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.20:34:04.92#ibcon#[25=AT02-07\r\n] 2006.257.20:34:04.92#ibcon#*before write, iclass 18, count 2 2006.257.20:34:04.92#ibcon#enter sib2, iclass 18, count 2 2006.257.20:34:04.92#ibcon#flushed, iclass 18, count 2 2006.257.20:34:04.92#ibcon#about to write, iclass 18, count 2 2006.257.20:34:04.92#ibcon#wrote, iclass 18, count 2 2006.257.20:34:04.92#ibcon#about to read 3, iclass 18, count 2 2006.257.20:34:04.95#ibcon#read 3, iclass 18, count 2 2006.257.20:34:04.95#ibcon#about to read 4, iclass 18, count 2 2006.257.20:34:04.95#ibcon#read 4, iclass 18, count 2 2006.257.20:34:04.95#ibcon#about to read 5, iclass 18, count 2 2006.257.20:34:04.95#ibcon#read 5, iclass 18, count 2 2006.257.20:34:04.95#ibcon#about to read 6, iclass 18, count 2 2006.257.20:34:04.95#ibcon#read 6, iclass 18, count 2 2006.257.20:34:04.95#ibcon#end of sib2, iclass 18, count 2 2006.257.20:34:04.95#ibcon#*after write, iclass 18, count 2 2006.257.20:34:04.95#ibcon#*before return 0, iclass 18, count 2 2006.257.20:34:04.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:04.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:04.95#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.20:34:04.95#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:04.95#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:05.07#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:05.07#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:05.07#ibcon#enter wrdev, iclass 18, count 0 2006.257.20:34:05.07#ibcon#first serial, iclass 18, count 0 2006.257.20:34:05.07#ibcon#enter sib2, iclass 18, count 0 2006.257.20:34:05.07#ibcon#flushed, iclass 18, count 0 2006.257.20:34:05.07#ibcon#about to write, iclass 18, count 0 2006.257.20:34:05.07#ibcon#wrote, iclass 18, count 0 2006.257.20:34:05.07#ibcon#about to read 3, iclass 18, count 0 2006.257.20:34:05.09#ibcon#read 3, iclass 18, count 0 2006.257.20:34:05.09#ibcon#about to read 4, iclass 18, count 0 2006.257.20:34:05.09#ibcon#read 4, iclass 18, count 0 2006.257.20:34:05.09#ibcon#about to read 5, iclass 18, count 0 2006.257.20:34:05.09#ibcon#read 5, iclass 18, count 0 2006.257.20:34:05.09#ibcon#about to read 6, iclass 18, count 0 2006.257.20:34:05.09#ibcon#read 6, iclass 18, count 0 2006.257.20:34:05.09#ibcon#end of sib2, iclass 18, count 0 2006.257.20:34:05.09#ibcon#*mode == 0, iclass 18, count 0 2006.257.20:34:05.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.20:34:05.09#ibcon#[25=USB\r\n] 2006.257.20:34:05.09#ibcon#*before write, iclass 18, count 0 2006.257.20:34:05.09#ibcon#enter sib2, iclass 18, count 0 2006.257.20:34:05.09#ibcon#flushed, iclass 18, count 0 2006.257.20:34:05.09#ibcon#about to write, iclass 18, count 0 2006.257.20:34:05.09#ibcon#wrote, iclass 18, count 0 2006.257.20:34:05.09#ibcon#about to read 3, iclass 18, count 0 2006.257.20:34:05.12#ibcon#read 3, iclass 18, count 0 2006.257.20:34:05.12#ibcon#about to read 4, iclass 18, count 0 2006.257.20:34:05.12#ibcon#read 4, iclass 18, count 0 2006.257.20:34:05.12#ibcon#about to read 5, iclass 18, count 0 2006.257.20:34:05.12#ibcon#read 5, iclass 18, count 0 2006.257.20:34:05.12#ibcon#about to read 6, iclass 18, count 0 2006.257.20:34:05.12#ibcon#read 6, iclass 18, count 0 2006.257.20:34:05.12#ibcon#end of sib2, iclass 18, count 0 2006.257.20:34:05.12#ibcon#*after write, iclass 18, count 0 2006.257.20:34:05.12#ibcon#*before return 0, iclass 18, count 0 2006.257.20:34:05.12#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:05.12#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:05.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.20:34:05.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.20:34:05.12$vck44/valo=3,564.99 2006.257.20:34:05.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.20:34:05.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.20:34:05.12#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:05.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:05.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:05.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:05.12#ibcon#enter wrdev, iclass 20, count 0 2006.257.20:34:05.12#ibcon#first serial, iclass 20, count 0 2006.257.20:34:05.12#ibcon#enter sib2, iclass 20, count 0 2006.257.20:34:05.12#ibcon#flushed, iclass 20, count 0 2006.257.20:34:05.12#ibcon#about to write, iclass 20, count 0 2006.257.20:34:05.12#ibcon#wrote, iclass 20, count 0 2006.257.20:34:05.12#ibcon#about to read 3, iclass 20, count 0 2006.257.20:34:05.14#ibcon#read 3, iclass 20, count 0 2006.257.20:34:05.14#ibcon#about to read 4, iclass 20, count 0 2006.257.20:34:05.14#ibcon#read 4, iclass 20, count 0 2006.257.20:34:05.14#ibcon#about to read 5, iclass 20, count 0 2006.257.20:34:05.14#ibcon#read 5, iclass 20, count 0 2006.257.20:34:05.14#ibcon#about to read 6, iclass 20, count 0 2006.257.20:34:05.14#ibcon#read 6, iclass 20, count 0 2006.257.20:34:05.14#ibcon#end of sib2, iclass 20, count 0 2006.257.20:34:05.14#ibcon#*mode == 0, iclass 20, count 0 2006.257.20:34:05.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.20:34:05.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.20:34:05.14#ibcon#*before write, iclass 20, count 0 2006.257.20:34:05.14#ibcon#enter sib2, iclass 20, count 0 2006.257.20:34:05.14#ibcon#flushed, iclass 20, count 0 2006.257.20:34:05.14#ibcon#about to write, iclass 20, count 0 2006.257.20:34:05.14#ibcon#wrote, iclass 20, count 0 2006.257.20:34:05.14#ibcon#about to read 3, iclass 20, count 0 2006.257.20:34:05.18#ibcon#read 3, iclass 20, count 0 2006.257.20:34:05.18#ibcon#about to read 4, iclass 20, count 0 2006.257.20:34:05.18#ibcon#read 4, iclass 20, count 0 2006.257.20:34:05.18#ibcon#about to read 5, iclass 20, count 0 2006.257.20:34:05.18#ibcon#read 5, iclass 20, count 0 2006.257.20:34:05.18#ibcon#about to read 6, iclass 20, count 0 2006.257.20:34:05.18#ibcon#read 6, iclass 20, count 0 2006.257.20:34:05.18#ibcon#end of sib2, iclass 20, count 0 2006.257.20:34:05.18#ibcon#*after write, iclass 20, count 0 2006.257.20:34:05.18#ibcon#*before return 0, iclass 20, count 0 2006.257.20:34:05.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:05.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:05.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.20:34:05.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.20:34:05.18$vck44/va=3,8 2006.257.20:34:05.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.20:34:05.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.20:34:05.18#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:05.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:05.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:05.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:05.24#ibcon#enter wrdev, iclass 22, count 2 2006.257.20:34:05.24#ibcon#first serial, iclass 22, count 2 2006.257.20:34:05.24#ibcon#enter sib2, iclass 22, count 2 2006.257.20:34:05.24#ibcon#flushed, iclass 22, count 2 2006.257.20:34:05.24#ibcon#about to write, iclass 22, count 2 2006.257.20:34:05.24#ibcon#wrote, iclass 22, count 2 2006.257.20:34:05.24#ibcon#about to read 3, iclass 22, count 2 2006.257.20:34:05.26#ibcon#read 3, iclass 22, count 2 2006.257.20:34:05.26#ibcon#about to read 4, iclass 22, count 2 2006.257.20:34:05.26#ibcon#read 4, iclass 22, count 2 2006.257.20:34:05.26#ibcon#about to read 5, iclass 22, count 2 2006.257.20:34:05.26#ibcon#read 5, iclass 22, count 2 2006.257.20:34:05.26#ibcon#about to read 6, iclass 22, count 2 2006.257.20:34:05.26#ibcon#read 6, iclass 22, count 2 2006.257.20:34:05.26#ibcon#end of sib2, iclass 22, count 2 2006.257.20:34:05.26#ibcon#*mode == 0, iclass 22, count 2 2006.257.20:34:05.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.20:34:05.26#ibcon#[25=AT03-08\r\n] 2006.257.20:34:05.26#ibcon#*before write, iclass 22, count 2 2006.257.20:34:05.26#ibcon#enter sib2, iclass 22, count 2 2006.257.20:34:05.26#ibcon#flushed, iclass 22, count 2 2006.257.20:34:05.26#ibcon#about to write, iclass 22, count 2 2006.257.20:34:05.26#ibcon#wrote, iclass 22, count 2 2006.257.20:34:05.26#ibcon#about to read 3, iclass 22, count 2 2006.257.20:34:05.29#ibcon#read 3, iclass 22, count 2 2006.257.20:34:05.29#ibcon#about to read 4, iclass 22, count 2 2006.257.20:34:05.29#ibcon#read 4, iclass 22, count 2 2006.257.20:34:05.29#ibcon#about to read 5, iclass 22, count 2 2006.257.20:34:05.29#ibcon#read 5, iclass 22, count 2 2006.257.20:34:05.29#ibcon#about to read 6, iclass 22, count 2 2006.257.20:34:05.29#ibcon#read 6, iclass 22, count 2 2006.257.20:34:05.29#ibcon#end of sib2, iclass 22, count 2 2006.257.20:34:05.29#ibcon#*after write, iclass 22, count 2 2006.257.20:34:05.29#ibcon#*before return 0, iclass 22, count 2 2006.257.20:34:05.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:05.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:05.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.20:34:05.29#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:05.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:05.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:05.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:05.41#ibcon#enter wrdev, iclass 22, count 0 2006.257.20:34:05.41#ibcon#first serial, iclass 22, count 0 2006.257.20:34:05.41#ibcon#enter sib2, iclass 22, count 0 2006.257.20:34:05.41#ibcon#flushed, iclass 22, count 0 2006.257.20:34:05.41#ibcon#about to write, iclass 22, count 0 2006.257.20:34:05.41#ibcon#wrote, iclass 22, count 0 2006.257.20:34:05.41#ibcon#about to read 3, iclass 22, count 0 2006.257.20:34:05.43#ibcon#read 3, iclass 22, count 0 2006.257.20:34:05.43#ibcon#about to read 4, iclass 22, count 0 2006.257.20:34:05.43#ibcon#read 4, iclass 22, count 0 2006.257.20:34:05.43#ibcon#about to read 5, iclass 22, count 0 2006.257.20:34:05.43#ibcon#read 5, iclass 22, count 0 2006.257.20:34:05.43#ibcon#about to read 6, iclass 22, count 0 2006.257.20:34:05.43#ibcon#read 6, iclass 22, count 0 2006.257.20:34:05.43#ibcon#end of sib2, iclass 22, count 0 2006.257.20:34:05.43#ibcon#*mode == 0, iclass 22, count 0 2006.257.20:34:05.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.20:34:05.43#ibcon#[25=USB\r\n] 2006.257.20:34:05.43#ibcon#*before write, iclass 22, count 0 2006.257.20:34:05.43#ibcon#enter sib2, iclass 22, count 0 2006.257.20:34:05.43#ibcon#flushed, iclass 22, count 0 2006.257.20:34:05.43#ibcon#about to write, iclass 22, count 0 2006.257.20:34:05.43#ibcon#wrote, iclass 22, count 0 2006.257.20:34:05.43#ibcon#about to read 3, iclass 22, count 0 2006.257.20:34:05.46#ibcon#read 3, iclass 22, count 0 2006.257.20:34:05.46#ibcon#about to read 4, iclass 22, count 0 2006.257.20:34:05.46#ibcon#read 4, iclass 22, count 0 2006.257.20:34:05.46#ibcon#about to read 5, iclass 22, count 0 2006.257.20:34:05.46#ibcon#read 5, iclass 22, count 0 2006.257.20:34:05.46#ibcon#about to read 6, iclass 22, count 0 2006.257.20:34:05.46#ibcon#read 6, iclass 22, count 0 2006.257.20:34:05.46#ibcon#end of sib2, iclass 22, count 0 2006.257.20:34:05.46#ibcon#*after write, iclass 22, count 0 2006.257.20:34:05.46#ibcon#*before return 0, iclass 22, count 0 2006.257.20:34:05.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:05.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:05.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.20:34:05.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.20:34:05.46$vck44/valo=4,624.99 2006.257.20:34:05.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.20:34:05.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.20:34:05.46#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:05.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:05.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:05.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:05.46#ibcon#enter wrdev, iclass 24, count 0 2006.257.20:34:05.46#ibcon#first serial, iclass 24, count 0 2006.257.20:34:05.46#ibcon#enter sib2, iclass 24, count 0 2006.257.20:34:05.46#ibcon#flushed, iclass 24, count 0 2006.257.20:34:05.46#ibcon#about to write, iclass 24, count 0 2006.257.20:34:05.46#ibcon#wrote, iclass 24, count 0 2006.257.20:34:05.46#ibcon#about to read 3, iclass 24, count 0 2006.257.20:34:05.48#ibcon#read 3, iclass 24, count 0 2006.257.20:34:05.48#ibcon#about to read 4, iclass 24, count 0 2006.257.20:34:05.48#ibcon#read 4, iclass 24, count 0 2006.257.20:34:05.48#ibcon#about to read 5, iclass 24, count 0 2006.257.20:34:05.48#ibcon#read 5, iclass 24, count 0 2006.257.20:34:05.48#ibcon#about to read 6, iclass 24, count 0 2006.257.20:34:05.48#ibcon#read 6, iclass 24, count 0 2006.257.20:34:05.48#ibcon#end of sib2, iclass 24, count 0 2006.257.20:34:05.48#ibcon#*mode == 0, iclass 24, count 0 2006.257.20:34:05.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.20:34:05.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.20:34:05.48#ibcon#*before write, iclass 24, count 0 2006.257.20:34:05.48#ibcon#enter sib2, iclass 24, count 0 2006.257.20:34:05.48#ibcon#flushed, iclass 24, count 0 2006.257.20:34:05.48#ibcon#about to write, iclass 24, count 0 2006.257.20:34:05.48#ibcon#wrote, iclass 24, count 0 2006.257.20:34:05.48#ibcon#about to read 3, iclass 24, count 0 2006.257.20:34:05.52#ibcon#read 3, iclass 24, count 0 2006.257.20:34:05.52#ibcon#about to read 4, iclass 24, count 0 2006.257.20:34:05.52#ibcon#read 4, iclass 24, count 0 2006.257.20:34:05.52#ibcon#about to read 5, iclass 24, count 0 2006.257.20:34:05.52#ibcon#read 5, iclass 24, count 0 2006.257.20:34:05.52#ibcon#about to read 6, iclass 24, count 0 2006.257.20:34:05.52#ibcon#read 6, iclass 24, count 0 2006.257.20:34:05.52#ibcon#end of sib2, iclass 24, count 0 2006.257.20:34:05.52#ibcon#*after write, iclass 24, count 0 2006.257.20:34:05.52#ibcon#*before return 0, iclass 24, count 0 2006.257.20:34:05.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:05.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:05.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.20:34:05.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.20:34:05.52$vck44/va=4,7 2006.257.20:34:05.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.20:34:05.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.20:34:05.52#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:05.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:05.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:05.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:05.58#ibcon#enter wrdev, iclass 26, count 2 2006.257.20:34:05.58#ibcon#first serial, iclass 26, count 2 2006.257.20:34:05.58#ibcon#enter sib2, iclass 26, count 2 2006.257.20:34:05.58#ibcon#flushed, iclass 26, count 2 2006.257.20:34:05.58#ibcon#about to write, iclass 26, count 2 2006.257.20:34:05.58#ibcon#wrote, iclass 26, count 2 2006.257.20:34:05.58#ibcon#about to read 3, iclass 26, count 2 2006.257.20:34:05.60#ibcon#read 3, iclass 26, count 2 2006.257.20:34:05.60#ibcon#about to read 4, iclass 26, count 2 2006.257.20:34:05.60#ibcon#read 4, iclass 26, count 2 2006.257.20:34:05.60#ibcon#about to read 5, iclass 26, count 2 2006.257.20:34:05.60#ibcon#read 5, iclass 26, count 2 2006.257.20:34:05.60#ibcon#about to read 6, iclass 26, count 2 2006.257.20:34:05.60#ibcon#read 6, iclass 26, count 2 2006.257.20:34:05.60#ibcon#end of sib2, iclass 26, count 2 2006.257.20:34:05.60#ibcon#*mode == 0, iclass 26, count 2 2006.257.20:34:05.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.20:34:05.60#ibcon#[25=AT04-07\r\n] 2006.257.20:34:05.60#ibcon#*before write, iclass 26, count 2 2006.257.20:34:05.60#ibcon#enter sib2, iclass 26, count 2 2006.257.20:34:05.60#ibcon#flushed, iclass 26, count 2 2006.257.20:34:05.60#ibcon#about to write, iclass 26, count 2 2006.257.20:34:05.60#ibcon#wrote, iclass 26, count 2 2006.257.20:34:05.60#ibcon#about to read 3, iclass 26, count 2 2006.257.20:34:05.63#ibcon#read 3, iclass 26, count 2 2006.257.20:34:05.63#ibcon#about to read 4, iclass 26, count 2 2006.257.20:34:05.63#ibcon#read 4, iclass 26, count 2 2006.257.20:34:05.63#ibcon#about to read 5, iclass 26, count 2 2006.257.20:34:05.63#ibcon#read 5, iclass 26, count 2 2006.257.20:34:05.63#ibcon#about to read 6, iclass 26, count 2 2006.257.20:34:05.63#ibcon#read 6, iclass 26, count 2 2006.257.20:34:05.63#ibcon#end of sib2, iclass 26, count 2 2006.257.20:34:05.63#ibcon#*after write, iclass 26, count 2 2006.257.20:34:05.63#ibcon#*before return 0, iclass 26, count 2 2006.257.20:34:05.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:05.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:05.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.20:34:05.63#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:05.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:05.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:05.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:05.75#ibcon#enter wrdev, iclass 26, count 0 2006.257.20:34:05.75#ibcon#first serial, iclass 26, count 0 2006.257.20:34:05.75#ibcon#enter sib2, iclass 26, count 0 2006.257.20:34:05.75#ibcon#flushed, iclass 26, count 0 2006.257.20:34:05.75#ibcon#about to write, iclass 26, count 0 2006.257.20:34:05.75#ibcon#wrote, iclass 26, count 0 2006.257.20:34:05.75#ibcon#about to read 3, iclass 26, count 0 2006.257.20:34:05.77#ibcon#read 3, iclass 26, count 0 2006.257.20:34:05.77#ibcon#about to read 4, iclass 26, count 0 2006.257.20:34:05.77#ibcon#read 4, iclass 26, count 0 2006.257.20:34:05.77#ibcon#about to read 5, iclass 26, count 0 2006.257.20:34:05.77#ibcon#read 5, iclass 26, count 0 2006.257.20:34:05.77#ibcon#about to read 6, iclass 26, count 0 2006.257.20:34:05.77#ibcon#read 6, iclass 26, count 0 2006.257.20:34:05.77#ibcon#end of sib2, iclass 26, count 0 2006.257.20:34:05.77#ibcon#*mode == 0, iclass 26, count 0 2006.257.20:34:05.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.20:34:05.77#ibcon#[25=USB\r\n] 2006.257.20:34:05.77#ibcon#*before write, iclass 26, count 0 2006.257.20:34:05.77#ibcon#enter sib2, iclass 26, count 0 2006.257.20:34:05.77#ibcon#flushed, iclass 26, count 0 2006.257.20:34:05.77#ibcon#about to write, iclass 26, count 0 2006.257.20:34:05.77#ibcon#wrote, iclass 26, count 0 2006.257.20:34:05.77#ibcon#about to read 3, iclass 26, count 0 2006.257.20:34:05.80#ibcon#read 3, iclass 26, count 0 2006.257.20:34:05.80#ibcon#about to read 4, iclass 26, count 0 2006.257.20:34:05.80#ibcon#read 4, iclass 26, count 0 2006.257.20:34:05.80#ibcon#about to read 5, iclass 26, count 0 2006.257.20:34:05.80#ibcon#read 5, iclass 26, count 0 2006.257.20:34:05.80#ibcon#about to read 6, iclass 26, count 0 2006.257.20:34:05.80#ibcon#read 6, iclass 26, count 0 2006.257.20:34:05.80#ibcon#end of sib2, iclass 26, count 0 2006.257.20:34:05.80#ibcon#*after write, iclass 26, count 0 2006.257.20:34:05.80#ibcon#*before return 0, iclass 26, count 0 2006.257.20:34:05.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:05.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:05.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.20:34:05.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.20:34:05.80$vck44/valo=5,734.99 2006.257.20:34:05.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.20:34:05.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.20:34:05.80#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:05.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:05.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:05.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:05.80#ibcon#enter wrdev, iclass 28, count 0 2006.257.20:34:05.80#ibcon#first serial, iclass 28, count 0 2006.257.20:34:05.80#ibcon#enter sib2, iclass 28, count 0 2006.257.20:34:05.80#ibcon#flushed, iclass 28, count 0 2006.257.20:34:05.80#ibcon#about to write, iclass 28, count 0 2006.257.20:34:05.80#ibcon#wrote, iclass 28, count 0 2006.257.20:34:05.80#ibcon#about to read 3, iclass 28, count 0 2006.257.20:34:05.82#ibcon#read 3, iclass 28, count 0 2006.257.20:34:05.82#ibcon#about to read 4, iclass 28, count 0 2006.257.20:34:05.82#ibcon#read 4, iclass 28, count 0 2006.257.20:34:05.82#ibcon#about to read 5, iclass 28, count 0 2006.257.20:34:05.82#ibcon#read 5, iclass 28, count 0 2006.257.20:34:05.82#ibcon#about to read 6, iclass 28, count 0 2006.257.20:34:05.82#ibcon#read 6, iclass 28, count 0 2006.257.20:34:05.82#ibcon#end of sib2, iclass 28, count 0 2006.257.20:34:05.82#ibcon#*mode == 0, iclass 28, count 0 2006.257.20:34:05.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.20:34:05.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.20:34:05.82#ibcon#*before write, iclass 28, count 0 2006.257.20:34:05.82#ibcon#enter sib2, iclass 28, count 0 2006.257.20:34:05.82#ibcon#flushed, iclass 28, count 0 2006.257.20:34:05.82#ibcon#about to write, iclass 28, count 0 2006.257.20:34:05.82#ibcon#wrote, iclass 28, count 0 2006.257.20:34:05.82#ibcon#about to read 3, iclass 28, count 0 2006.257.20:34:05.86#ibcon#read 3, iclass 28, count 0 2006.257.20:34:05.86#ibcon#about to read 4, iclass 28, count 0 2006.257.20:34:05.86#ibcon#read 4, iclass 28, count 0 2006.257.20:34:05.86#ibcon#about to read 5, iclass 28, count 0 2006.257.20:34:05.86#ibcon#read 5, iclass 28, count 0 2006.257.20:34:05.86#ibcon#about to read 6, iclass 28, count 0 2006.257.20:34:05.86#ibcon#read 6, iclass 28, count 0 2006.257.20:34:05.86#ibcon#end of sib2, iclass 28, count 0 2006.257.20:34:05.86#ibcon#*after write, iclass 28, count 0 2006.257.20:34:05.86#ibcon#*before return 0, iclass 28, count 0 2006.257.20:34:05.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:05.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:05.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.20:34:05.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.20:34:05.86$vck44/va=5,4 2006.257.20:34:05.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.20:34:05.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.20:34:05.86#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:05.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:05.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:05.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:05.92#ibcon#enter wrdev, iclass 30, count 2 2006.257.20:34:05.92#ibcon#first serial, iclass 30, count 2 2006.257.20:34:05.92#ibcon#enter sib2, iclass 30, count 2 2006.257.20:34:05.92#ibcon#flushed, iclass 30, count 2 2006.257.20:34:05.92#ibcon#about to write, iclass 30, count 2 2006.257.20:34:05.92#ibcon#wrote, iclass 30, count 2 2006.257.20:34:05.92#ibcon#about to read 3, iclass 30, count 2 2006.257.20:34:05.94#ibcon#read 3, iclass 30, count 2 2006.257.20:34:05.94#ibcon#about to read 4, iclass 30, count 2 2006.257.20:34:05.94#ibcon#read 4, iclass 30, count 2 2006.257.20:34:05.94#ibcon#about to read 5, iclass 30, count 2 2006.257.20:34:05.94#ibcon#read 5, iclass 30, count 2 2006.257.20:34:05.94#ibcon#about to read 6, iclass 30, count 2 2006.257.20:34:05.94#ibcon#read 6, iclass 30, count 2 2006.257.20:34:05.94#ibcon#end of sib2, iclass 30, count 2 2006.257.20:34:05.94#ibcon#*mode == 0, iclass 30, count 2 2006.257.20:34:05.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.20:34:05.94#ibcon#[25=AT05-04\r\n] 2006.257.20:34:05.94#ibcon#*before write, iclass 30, count 2 2006.257.20:34:05.94#ibcon#enter sib2, iclass 30, count 2 2006.257.20:34:05.94#ibcon#flushed, iclass 30, count 2 2006.257.20:34:05.94#ibcon#about to write, iclass 30, count 2 2006.257.20:34:05.94#ibcon#wrote, iclass 30, count 2 2006.257.20:34:05.94#ibcon#about to read 3, iclass 30, count 2 2006.257.20:34:05.97#ibcon#read 3, iclass 30, count 2 2006.257.20:34:05.97#ibcon#about to read 4, iclass 30, count 2 2006.257.20:34:05.97#ibcon#read 4, iclass 30, count 2 2006.257.20:34:05.97#ibcon#about to read 5, iclass 30, count 2 2006.257.20:34:05.97#ibcon#read 5, iclass 30, count 2 2006.257.20:34:05.97#ibcon#about to read 6, iclass 30, count 2 2006.257.20:34:05.97#ibcon#read 6, iclass 30, count 2 2006.257.20:34:05.97#ibcon#end of sib2, iclass 30, count 2 2006.257.20:34:05.97#ibcon#*after write, iclass 30, count 2 2006.257.20:34:05.97#ibcon#*before return 0, iclass 30, count 2 2006.257.20:34:05.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:05.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:05.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.20:34:05.97#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:05.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:06.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:06.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:06.09#ibcon#enter wrdev, iclass 30, count 0 2006.257.20:34:06.09#ibcon#first serial, iclass 30, count 0 2006.257.20:34:06.09#ibcon#enter sib2, iclass 30, count 0 2006.257.20:34:06.09#ibcon#flushed, iclass 30, count 0 2006.257.20:34:06.09#ibcon#about to write, iclass 30, count 0 2006.257.20:34:06.09#ibcon#wrote, iclass 30, count 0 2006.257.20:34:06.09#ibcon#about to read 3, iclass 30, count 0 2006.257.20:34:06.11#ibcon#read 3, iclass 30, count 0 2006.257.20:34:06.11#ibcon#about to read 4, iclass 30, count 0 2006.257.20:34:06.11#ibcon#read 4, iclass 30, count 0 2006.257.20:34:06.11#ibcon#about to read 5, iclass 30, count 0 2006.257.20:34:06.11#ibcon#read 5, iclass 30, count 0 2006.257.20:34:06.11#ibcon#about to read 6, iclass 30, count 0 2006.257.20:34:06.11#ibcon#read 6, iclass 30, count 0 2006.257.20:34:06.11#ibcon#end of sib2, iclass 30, count 0 2006.257.20:34:06.11#ibcon#*mode == 0, iclass 30, count 0 2006.257.20:34:06.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.20:34:06.11#ibcon#[25=USB\r\n] 2006.257.20:34:06.11#ibcon#*before write, iclass 30, count 0 2006.257.20:34:06.11#ibcon#enter sib2, iclass 30, count 0 2006.257.20:34:06.11#ibcon#flushed, iclass 30, count 0 2006.257.20:34:06.11#ibcon#about to write, iclass 30, count 0 2006.257.20:34:06.11#ibcon#wrote, iclass 30, count 0 2006.257.20:34:06.11#ibcon#about to read 3, iclass 30, count 0 2006.257.20:34:06.14#ibcon#read 3, iclass 30, count 0 2006.257.20:34:06.14#ibcon#about to read 4, iclass 30, count 0 2006.257.20:34:06.14#ibcon#read 4, iclass 30, count 0 2006.257.20:34:06.14#ibcon#about to read 5, iclass 30, count 0 2006.257.20:34:06.14#ibcon#read 5, iclass 30, count 0 2006.257.20:34:06.14#ibcon#about to read 6, iclass 30, count 0 2006.257.20:34:06.14#ibcon#read 6, iclass 30, count 0 2006.257.20:34:06.14#ibcon#end of sib2, iclass 30, count 0 2006.257.20:34:06.14#ibcon#*after write, iclass 30, count 0 2006.257.20:34:06.14#ibcon#*before return 0, iclass 30, count 0 2006.257.20:34:06.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:06.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:06.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.20:34:06.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.20:34:06.14$vck44/valo=6,814.99 2006.257.20:34:06.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.20:34:06.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.20:34:06.14#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:06.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:06.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:06.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:06.14#ibcon#enter wrdev, iclass 32, count 0 2006.257.20:34:06.14#ibcon#first serial, iclass 32, count 0 2006.257.20:34:06.14#ibcon#enter sib2, iclass 32, count 0 2006.257.20:34:06.14#ibcon#flushed, iclass 32, count 0 2006.257.20:34:06.14#ibcon#about to write, iclass 32, count 0 2006.257.20:34:06.14#ibcon#wrote, iclass 32, count 0 2006.257.20:34:06.14#ibcon#about to read 3, iclass 32, count 0 2006.257.20:34:06.16#ibcon#read 3, iclass 32, count 0 2006.257.20:34:06.16#ibcon#about to read 4, iclass 32, count 0 2006.257.20:34:06.16#ibcon#read 4, iclass 32, count 0 2006.257.20:34:06.16#ibcon#about to read 5, iclass 32, count 0 2006.257.20:34:06.16#ibcon#read 5, iclass 32, count 0 2006.257.20:34:06.16#ibcon#about to read 6, iclass 32, count 0 2006.257.20:34:06.16#ibcon#read 6, iclass 32, count 0 2006.257.20:34:06.16#ibcon#end of sib2, iclass 32, count 0 2006.257.20:34:06.16#ibcon#*mode == 0, iclass 32, count 0 2006.257.20:34:06.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.20:34:06.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.20:34:06.16#ibcon#*before write, iclass 32, count 0 2006.257.20:34:06.16#ibcon#enter sib2, iclass 32, count 0 2006.257.20:34:06.16#ibcon#flushed, iclass 32, count 0 2006.257.20:34:06.16#ibcon#about to write, iclass 32, count 0 2006.257.20:34:06.16#ibcon#wrote, iclass 32, count 0 2006.257.20:34:06.16#ibcon#about to read 3, iclass 32, count 0 2006.257.20:34:06.20#ibcon#read 3, iclass 32, count 0 2006.257.20:34:06.20#ibcon#about to read 4, iclass 32, count 0 2006.257.20:34:06.20#ibcon#read 4, iclass 32, count 0 2006.257.20:34:06.20#ibcon#about to read 5, iclass 32, count 0 2006.257.20:34:06.20#ibcon#read 5, iclass 32, count 0 2006.257.20:34:06.20#ibcon#about to read 6, iclass 32, count 0 2006.257.20:34:06.20#ibcon#read 6, iclass 32, count 0 2006.257.20:34:06.20#ibcon#end of sib2, iclass 32, count 0 2006.257.20:34:06.20#ibcon#*after write, iclass 32, count 0 2006.257.20:34:06.20#ibcon#*before return 0, iclass 32, count 0 2006.257.20:34:06.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:06.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:06.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.20:34:06.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.20:34:06.20$vck44/va=6,4 2006.257.20:34:06.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.20:34:06.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.20:34:06.20#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:06.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:06.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:06.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:06.26#ibcon#enter wrdev, iclass 34, count 2 2006.257.20:34:06.26#ibcon#first serial, iclass 34, count 2 2006.257.20:34:06.26#ibcon#enter sib2, iclass 34, count 2 2006.257.20:34:06.26#ibcon#flushed, iclass 34, count 2 2006.257.20:34:06.26#ibcon#about to write, iclass 34, count 2 2006.257.20:34:06.26#ibcon#wrote, iclass 34, count 2 2006.257.20:34:06.26#ibcon#about to read 3, iclass 34, count 2 2006.257.20:34:06.28#ibcon#read 3, iclass 34, count 2 2006.257.20:34:06.28#ibcon#about to read 4, iclass 34, count 2 2006.257.20:34:06.28#ibcon#read 4, iclass 34, count 2 2006.257.20:34:06.28#ibcon#about to read 5, iclass 34, count 2 2006.257.20:34:06.28#ibcon#read 5, iclass 34, count 2 2006.257.20:34:06.28#ibcon#about to read 6, iclass 34, count 2 2006.257.20:34:06.28#ibcon#read 6, iclass 34, count 2 2006.257.20:34:06.28#ibcon#end of sib2, iclass 34, count 2 2006.257.20:34:06.28#ibcon#*mode == 0, iclass 34, count 2 2006.257.20:34:06.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.20:34:06.28#ibcon#[25=AT06-04\r\n] 2006.257.20:34:06.28#ibcon#*before write, iclass 34, count 2 2006.257.20:34:06.28#ibcon#enter sib2, iclass 34, count 2 2006.257.20:34:06.28#ibcon#flushed, iclass 34, count 2 2006.257.20:34:06.28#ibcon#about to write, iclass 34, count 2 2006.257.20:34:06.28#ibcon#wrote, iclass 34, count 2 2006.257.20:34:06.28#ibcon#about to read 3, iclass 34, count 2 2006.257.20:34:06.31#ibcon#read 3, iclass 34, count 2 2006.257.20:34:06.31#ibcon#about to read 4, iclass 34, count 2 2006.257.20:34:06.31#ibcon#read 4, iclass 34, count 2 2006.257.20:34:06.31#ibcon#about to read 5, iclass 34, count 2 2006.257.20:34:06.31#ibcon#read 5, iclass 34, count 2 2006.257.20:34:06.31#ibcon#about to read 6, iclass 34, count 2 2006.257.20:34:06.31#ibcon#read 6, iclass 34, count 2 2006.257.20:34:06.31#ibcon#end of sib2, iclass 34, count 2 2006.257.20:34:06.31#ibcon#*after write, iclass 34, count 2 2006.257.20:34:06.31#ibcon#*before return 0, iclass 34, count 2 2006.257.20:34:06.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:06.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:06.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.20:34:06.31#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:06.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:06.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:06.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:06.43#ibcon#enter wrdev, iclass 34, count 0 2006.257.20:34:06.43#ibcon#first serial, iclass 34, count 0 2006.257.20:34:06.43#ibcon#enter sib2, iclass 34, count 0 2006.257.20:34:06.43#ibcon#flushed, iclass 34, count 0 2006.257.20:34:06.43#ibcon#about to write, iclass 34, count 0 2006.257.20:34:06.43#ibcon#wrote, iclass 34, count 0 2006.257.20:34:06.43#ibcon#about to read 3, iclass 34, count 0 2006.257.20:34:06.45#ibcon#read 3, iclass 34, count 0 2006.257.20:34:06.45#ibcon#about to read 4, iclass 34, count 0 2006.257.20:34:06.45#ibcon#read 4, iclass 34, count 0 2006.257.20:34:06.45#ibcon#about to read 5, iclass 34, count 0 2006.257.20:34:06.45#ibcon#read 5, iclass 34, count 0 2006.257.20:34:06.45#ibcon#about to read 6, iclass 34, count 0 2006.257.20:34:06.45#ibcon#read 6, iclass 34, count 0 2006.257.20:34:06.45#ibcon#end of sib2, iclass 34, count 0 2006.257.20:34:06.45#ibcon#*mode == 0, iclass 34, count 0 2006.257.20:34:06.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.20:34:06.45#ibcon#[25=USB\r\n] 2006.257.20:34:06.45#ibcon#*before write, iclass 34, count 0 2006.257.20:34:06.45#ibcon#enter sib2, iclass 34, count 0 2006.257.20:34:06.45#ibcon#flushed, iclass 34, count 0 2006.257.20:34:06.45#ibcon#about to write, iclass 34, count 0 2006.257.20:34:06.45#ibcon#wrote, iclass 34, count 0 2006.257.20:34:06.45#ibcon#about to read 3, iclass 34, count 0 2006.257.20:34:06.48#ibcon#read 3, iclass 34, count 0 2006.257.20:34:06.48#ibcon#about to read 4, iclass 34, count 0 2006.257.20:34:06.48#ibcon#read 4, iclass 34, count 0 2006.257.20:34:06.48#ibcon#about to read 5, iclass 34, count 0 2006.257.20:34:06.48#ibcon#read 5, iclass 34, count 0 2006.257.20:34:06.48#ibcon#about to read 6, iclass 34, count 0 2006.257.20:34:06.48#ibcon#read 6, iclass 34, count 0 2006.257.20:34:06.48#ibcon#end of sib2, iclass 34, count 0 2006.257.20:34:06.48#ibcon#*after write, iclass 34, count 0 2006.257.20:34:06.48#ibcon#*before return 0, iclass 34, count 0 2006.257.20:34:06.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:06.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:06.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.20:34:06.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.20:34:06.48$vck44/valo=7,864.99 2006.257.20:34:06.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.20:34:06.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.20:34:06.48#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:06.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:06.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:06.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:06.48#ibcon#enter wrdev, iclass 36, count 0 2006.257.20:34:06.48#ibcon#first serial, iclass 36, count 0 2006.257.20:34:06.48#ibcon#enter sib2, iclass 36, count 0 2006.257.20:34:06.48#ibcon#flushed, iclass 36, count 0 2006.257.20:34:06.48#ibcon#about to write, iclass 36, count 0 2006.257.20:34:06.48#ibcon#wrote, iclass 36, count 0 2006.257.20:34:06.48#ibcon#about to read 3, iclass 36, count 0 2006.257.20:34:06.50#ibcon#read 3, iclass 36, count 0 2006.257.20:34:06.50#ibcon#about to read 4, iclass 36, count 0 2006.257.20:34:06.50#ibcon#read 4, iclass 36, count 0 2006.257.20:34:06.50#ibcon#about to read 5, iclass 36, count 0 2006.257.20:34:06.50#ibcon#read 5, iclass 36, count 0 2006.257.20:34:06.50#ibcon#about to read 6, iclass 36, count 0 2006.257.20:34:06.50#ibcon#read 6, iclass 36, count 0 2006.257.20:34:06.50#ibcon#end of sib2, iclass 36, count 0 2006.257.20:34:06.50#ibcon#*mode == 0, iclass 36, count 0 2006.257.20:34:06.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.20:34:06.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.20:34:06.50#ibcon#*before write, iclass 36, count 0 2006.257.20:34:06.50#ibcon#enter sib2, iclass 36, count 0 2006.257.20:34:06.50#ibcon#flushed, iclass 36, count 0 2006.257.20:34:06.50#ibcon#about to write, iclass 36, count 0 2006.257.20:34:06.50#ibcon#wrote, iclass 36, count 0 2006.257.20:34:06.50#ibcon#about to read 3, iclass 36, count 0 2006.257.20:34:06.54#ibcon#read 3, iclass 36, count 0 2006.257.20:34:06.54#ibcon#about to read 4, iclass 36, count 0 2006.257.20:34:06.54#ibcon#read 4, iclass 36, count 0 2006.257.20:34:06.54#ibcon#about to read 5, iclass 36, count 0 2006.257.20:34:06.54#ibcon#read 5, iclass 36, count 0 2006.257.20:34:06.54#ibcon#about to read 6, iclass 36, count 0 2006.257.20:34:06.54#ibcon#read 6, iclass 36, count 0 2006.257.20:34:06.54#ibcon#end of sib2, iclass 36, count 0 2006.257.20:34:06.54#ibcon#*after write, iclass 36, count 0 2006.257.20:34:06.54#ibcon#*before return 0, iclass 36, count 0 2006.257.20:34:06.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:06.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:06.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.20:34:06.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.20:34:06.54$vck44/va=7,4 2006.257.20:34:06.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.20:34:06.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.20:34:06.54#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:06.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:06.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:06.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:06.60#ibcon#enter wrdev, iclass 38, count 2 2006.257.20:34:06.60#ibcon#first serial, iclass 38, count 2 2006.257.20:34:06.60#ibcon#enter sib2, iclass 38, count 2 2006.257.20:34:06.60#ibcon#flushed, iclass 38, count 2 2006.257.20:34:06.60#ibcon#about to write, iclass 38, count 2 2006.257.20:34:06.60#ibcon#wrote, iclass 38, count 2 2006.257.20:34:06.60#ibcon#about to read 3, iclass 38, count 2 2006.257.20:34:06.62#ibcon#read 3, iclass 38, count 2 2006.257.20:34:06.62#ibcon#about to read 4, iclass 38, count 2 2006.257.20:34:06.62#ibcon#read 4, iclass 38, count 2 2006.257.20:34:06.62#ibcon#about to read 5, iclass 38, count 2 2006.257.20:34:06.62#ibcon#read 5, iclass 38, count 2 2006.257.20:34:06.62#ibcon#about to read 6, iclass 38, count 2 2006.257.20:34:06.62#ibcon#read 6, iclass 38, count 2 2006.257.20:34:06.62#ibcon#end of sib2, iclass 38, count 2 2006.257.20:34:06.62#ibcon#*mode == 0, iclass 38, count 2 2006.257.20:34:06.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.20:34:06.62#ibcon#[25=AT07-04\r\n] 2006.257.20:34:06.62#ibcon#*before write, iclass 38, count 2 2006.257.20:34:06.62#ibcon#enter sib2, iclass 38, count 2 2006.257.20:34:06.62#ibcon#flushed, iclass 38, count 2 2006.257.20:34:06.62#ibcon#about to write, iclass 38, count 2 2006.257.20:34:06.62#ibcon#wrote, iclass 38, count 2 2006.257.20:34:06.62#ibcon#about to read 3, iclass 38, count 2 2006.257.20:34:06.65#ibcon#read 3, iclass 38, count 2 2006.257.20:34:06.65#ibcon#about to read 4, iclass 38, count 2 2006.257.20:34:06.65#ibcon#read 4, iclass 38, count 2 2006.257.20:34:06.65#ibcon#about to read 5, iclass 38, count 2 2006.257.20:34:06.65#ibcon#read 5, iclass 38, count 2 2006.257.20:34:06.65#ibcon#about to read 6, iclass 38, count 2 2006.257.20:34:06.65#ibcon#read 6, iclass 38, count 2 2006.257.20:34:06.65#ibcon#end of sib2, iclass 38, count 2 2006.257.20:34:06.65#ibcon#*after write, iclass 38, count 2 2006.257.20:34:06.65#ibcon#*before return 0, iclass 38, count 2 2006.257.20:34:06.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:06.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:06.65#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.20:34:06.65#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:06.65#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:06.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:06.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:06.77#ibcon#enter wrdev, iclass 38, count 0 2006.257.20:34:06.77#ibcon#first serial, iclass 38, count 0 2006.257.20:34:06.77#ibcon#enter sib2, iclass 38, count 0 2006.257.20:34:06.77#ibcon#flushed, iclass 38, count 0 2006.257.20:34:06.77#ibcon#about to write, iclass 38, count 0 2006.257.20:34:06.77#ibcon#wrote, iclass 38, count 0 2006.257.20:34:06.77#ibcon#about to read 3, iclass 38, count 0 2006.257.20:34:06.79#ibcon#read 3, iclass 38, count 0 2006.257.20:34:06.79#ibcon#about to read 4, iclass 38, count 0 2006.257.20:34:06.79#ibcon#read 4, iclass 38, count 0 2006.257.20:34:06.79#ibcon#about to read 5, iclass 38, count 0 2006.257.20:34:06.79#ibcon#read 5, iclass 38, count 0 2006.257.20:34:06.79#ibcon#about to read 6, iclass 38, count 0 2006.257.20:34:06.79#ibcon#read 6, iclass 38, count 0 2006.257.20:34:06.79#ibcon#end of sib2, iclass 38, count 0 2006.257.20:34:06.79#ibcon#*mode == 0, iclass 38, count 0 2006.257.20:34:06.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.20:34:06.79#ibcon#[25=USB\r\n] 2006.257.20:34:06.79#ibcon#*before write, iclass 38, count 0 2006.257.20:34:06.79#ibcon#enter sib2, iclass 38, count 0 2006.257.20:34:06.79#ibcon#flushed, iclass 38, count 0 2006.257.20:34:06.79#ibcon#about to write, iclass 38, count 0 2006.257.20:34:06.79#ibcon#wrote, iclass 38, count 0 2006.257.20:34:06.79#ibcon#about to read 3, iclass 38, count 0 2006.257.20:34:06.82#ibcon#read 3, iclass 38, count 0 2006.257.20:34:06.82#ibcon#about to read 4, iclass 38, count 0 2006.257.20:34:06.82#ibcon#read 4, iclass 38, count 0 2006.257.20:34:06.82#ibcon#about to read 5, iclass 38, count 0 2006.257.20:34:06.82#ibcon#read 5, iclass 38, count 0 2006.257.20:34:06.82#ibcon#about to read 6, iclass 38, count 0 2006.257.20:34:06.82#ibcon#read 6, iclass 38, count 0 2006.257.20:34:06.82#ibcon#end of sib2, iclass 38, count 0 2006.257.20:34:06.82#ibcon#*after write, iclass 38, count 0 2006.257.20:34:06.82#ibcon#*before return 0, iclass 38, count 0 2006.257.20:34:06.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:06.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:06.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.20:34:06.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.20:34:06.82$vck44/valo=8,884.99 2006.257.20:34:06.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.20:34:06.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.20:34:06.82#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:06.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:06.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:06.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:06.82#ibcon#enter wrdev, iclass 40, count 0 2006.257.20:34:06.82#ibcon#first serial, iclass 40, count 0 2006.257.20:34:06.82#ibcon#enter sib2, iclass 40, count 0 2006.257.20:34:06.82#ibcon#flushed, iclass 40, count 0 2006.257.20:34:06.82#ibcon#about to write, iclass 40, count 0 2006.257.20:34:06.82#ibcon#wrote, iclass 40, count 0 2006.257.20:34:06.82#ibcon#about to read 3, iclass 40, count 0 2006.257.20:34:06.84#ibcon#read 3, iclass 40, count 0 2006.257.20:34:06.84#ibcon#about to read 4, iclass 40, count 0 2006.257.20:34:06.84#ibcon#read 4, iclass 40, count 0 2006.257.20:34:06.84#ibcon#about to read 5, iclass 40, count 0 2006.257.20:34:06.84#ibcon#read 5, iclass 40, count 0 2006.257.20:34:06.84#ibcon#about to read 6, iclass 40, count 0 2006.257.20:34:06.84#ibcon#read 6, iclass 40, count 0 2006.257.20:34:06.84#ibcon#end of sib2, iclass 40, count 0 2006.257.20:34:06.84#ibcon#*mode == 0, iclass 40, count 0 2006.257.20:34:06.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.20:34:06.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.20:34:06.84#ibcon#*before write, iclass 40, count 0 2006.257.20:34:06.84#ibcon#enter sib2, iclass 40, count 0 2006.257.20:34:06.84#ibcon#flushed, iclass 40, count 0 2006.257.20:34:06.84#ibcon#about to write, iclass 40, count 0 2006.257.20:34:06.84#ibcon#wrote, iclass 40, count 0 2006.257.20:34:06.84#ibcon#about to read 3, iclass 40, count 0 2006.257.20:34:06.88#ibcon#read 3, iclass 40, count 0 2006.257.20:34:06.88#ibcon#about to read 4, iclass 40, count 0 2006.257.20:34:06.88#ibcon#read 4, iclass 40, count 0 2006.257.20:34:06.88#ibcon#about to read 5, iclass 40, count 0 2006.257.20:34:06.88#ibcon#read 5, iclass 40, count 0 2006.257.20:34:06.88#ibcon#about to read 6, iclass 40, count 0 2006.257.20:34:06.88#ibcon#read 6, iclass 40, count 0 2006.257.20:34:06.88#ibcon#end of sib2, iclass 40, count 0 2006.257.20:34:06.88#ibcon#*after write, iclass 40, count 0 2006.257.20:34:06.88#ibcon#*before return 0, iclass 40, count 0 2006.257.20:34:06.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:06.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:06.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.20:34:06.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.20:34:06.88$vck44/va=8,4 2006.257.20:34:06.88#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.20:34:06.88#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.20:34:06.88#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:06.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:34:06.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:34:06.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:34:06.94#ibcon#enter wrdev, iclass 4, count 2 2006.257.20:34:06.94#ibcon#first serial, iclass 4, count 2 2006.257.20:34:06.94#ibcon#enter sib2, iclass 4, count 2 2006.257.20:34:06.94#ibcon#flushed, iclass 4, count 2 2006.257.20:34:06.94#ibcon#about to write, iclass 4, count 2 2006.257.20:34:06.94#ibcon#wrote, iclass 4, count 2 2006.257.20:34:06.94#ibcon#about to read 3, iclass 4, count 2 2006.257.20:34:06.96#ibcon#read 3, iclass 4, count 2 2006.257.20:34:06.96#ibcon#about to read 4, iclass 4, count 2 2006.257.20:34:06.96#ibcon#read 4, iclass 4, count 2 2006.257.20:34:06.96#ibcon#about to read 5, iclass 4, count 2 2006.257.20:34:06.96#ibcon#read 5, iclass 4, count 2 2006.257.20:34:06.96#ibcon#about to read 6, iclass 4, count 2 2006.257.20:34:06.96#ibcon#read 6, iclass 4, count 2 2006.257.20:34:06.96#ibcon#end of sib2, iclass 4, count 2 2006.257.20:34:06.96#ibcon#*mode == 0, iclass 4, count 2 2006.257.20:34:06.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.20:34:06.96#ibcon#[25=AT08-04\r\n] 2006.257.20:34:06.96#ibcon#*before write, iclass 4, count 2 2006.257.20:34:06.96#ibcon#enter sib2, iclass 4, count 2 2006.257.20:34:06.96#ibcon#flushed, iclass 4, count 2 2006.257.20:34:06.96#ibcon#about to write, iclass 4, count 2 2006.257.20:34:06.96#ibcon#wrote, iclass 4, count 2 2006.257.20:34:06.96#ibcon#about to read 3, iclass 4, count 2 2006.257.20:34:06.99#ibcon#read 3, iclass 4, count 2 2006.257.20:34:06.99#ibcon#about to read 4, iclass 4, count 2 2006.257.20:34:06.99#ibcon#read 4, iclass 4, count 2 2006.257.20:34:06.99#ibcon#about to read 5, iclass 4, count 2 2006.257.20:34:06.99#ibcon#read 5, iclass 4, count 2 2006.257.20:34:06.99#ibcon#about to read 6, iclass 4, count 2 2006.257.20:34:06.99#ibcon#read 6, iclass 4, count 2 2006.257.20:34:06.99#ibcon#end of sib2, iclass 4, count 2 2006.257.20:34:06.99#ibcon#*after write, iclass 4, count 2 2006.257.20:34:06.99#ibcon#*before return 0, iclass 4, count 2 2006.257.20:34:06.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:34:06.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:34:06.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.20:34:06.99#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:06.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:34:07.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:34:07.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:34:07.11#ibcon#enter wrdev, iclass 4, count 0 2006.257.20:34:07.11#ibcon#first serial, iclass 4, count 0 2006.257.20:34:07.11#ibcon#enter sib2, iclass 4, count 0 2006.257.20:34:07.11#ibcon#flushed, iclass 4, count 0 2006.257.20:34:07.11#ibcon#about to write, iclass 4, count 0 2006.257.20:34:07.11#ibcon#wrote, iclass 4, count 0 2006.257.20:34:07.11#ibcon#about to read 3, iclass 4, count 0 2006.257.20:34:07.13#ibcon#read 3, iclass 4, count 0 2006.257.20:34:07.13#ibcon#about to read 4, iclass 4, count 0 2006.257.20:34:07.13#ibcon#read 4, iclass 4, count 0 2006.257.20:34:07.13#ibcon#about to read 5, iclass 4, count 0 2006.257.20:34:07.13#ibcon#read 5, iclass 4, count 0 2006.257.20:34:07.13#ibcon#about to read 6, iclass 4, count 0 2006.257.20:34:07.13#ibcon#read 6, iclass 4, count 0 2006.257.20:34:07.13#ibcon#end of sib2, iclass 4, count 0 2006.257.20:34:07.13#ibcon#*mode == 0, iclass 4, count 0 2006.257.20:34:07.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.20:34:07.13#ibcon#[25=USB\r\n] 2006.257.20:34:07.13#ibcon#*before write, iclass 4, count 0 2006.257.20:34:07.13#ibcon#enter sib2, iclass 4, count 0 2006.257.20:34:07.13#ibcon#flushed, iclass 4, count 0 2006.257.20:34:07.13#ibcon#about to write, iclass 4, count 0 2006.257.20:34:07.13#ibcon#wrote, iclass 4, count 0 2006.257.20:34:07.13#ibcon#about to read 3, iclass 4, count 0 2006.257.20:34:07.16#ibcon#read 3, iclass 4, count 0 2006.257.20:34:07.16#ibcon#about to read 4, iclass 4, count 0 2006.257.20:34:07.16#ibcon#read 4, iclass 4, count 0 2006.257.20:34:07.16#ibcon#about to read 5, iclass 4, count 0 2006.257.20:34:07.16#ibcon#read 5, iclass 4, count 0 2006.257.20:34:07.16#ibcon#about to read 6, iclass 4, count 0 2006.257.20:34:07.16#ibcon#read 6, iclass 4, count 0 2006.257.20:34:07.16#ibcon#end of sib2, iclass 4, count 0 2006.257.20:34:07.16#ibcon#*after write, iclass 4, count 0 2006.257.20:34:07.16#ibcon#*before return 0, iclass 4, count 0 2006.257.20:34:07.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:34:07.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:34:07.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.20:34:07.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.20:34:07.16$vck44/vblo=1,629.99 2006.257.20:34:07.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.20:34:07.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.20:34:07.16#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:07.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:34:07.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:34:07.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:34:07.16#ibcon#enter wrdev, iclass 6, count 0 2006.257.20:34:07.16#ibcon#first serial, iclass 6, count 0 2006.257.20:34:07.16#ibcon#enter sib2, iclass 6, count 0 2006.257.20:34:07.16#ibcon#flushed, iclass 6, count 0 2006.257.20:34:07.16#ibcon#about to write, iclass 6, count 0 2006.257.20:34:07.16#ibcon#wrote, iclass 6, count 0 2006.257.20:34:07.16#ibcon#about to read 3, iclass 6, count 0 2006.257.20:34:07.18#ibcon#read 3, iclass 6, count 0 2006.257.20:34:07.18#ibcon#about to read 4, iclass 6, count 0 2006.257.20:34:07.18#ibcon#read 4, iclass 6, count 0 2006.257.20:34:07.18#ibcon#about to read 5, iclass 6, count 0 2006.257.20:34:07.18#ibcon#read 5, iclass 6, count 0 2006.257.20:34:07.18#ibcon#about to read 6, iclass 6, count 0 2006.257.20:34:07.18#ibcon#read 6, iclass 6, count 0 2006.257.20:34:07.18#ibcon#end of sib2, iclass 6, count 0 2006.257.20:34:07.18#ibcon#*mode == 0, iclass 6, count 0 2006.257.20:34:07.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.20:34:07.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.20:34:07.18#ibcon#*before write, iclass 6, count 0 2006.257.20:34:07.18#ibcon#enter sib2, iclass 6, count 0 2006.257.20:34:07.18#ibcon#flushed, iclass 6, count 0 2006.257.20:34:07.18#ibcon#about to write, iclass 6, count 0 2006.257.20:34:07.18#ibcon#wrote, iclass 6, count 0 2006.257.20:34:07.18#ibcon#about to read 3, iclass 6, count 0 2006.257.20:34:07.22#ibcon#read 3, iclass 6, count 0 2006.257.20:34:07.22#ibcon#about to read 4, iclass 6, count 0 2006.257.20:34:07.22#ibcon#read 4, iclass 6, count 0 2006.257.20:34:07.22#ibcon#about to read 5, iclass 6, count 0 2006.257.20:34:07.22#ibcon#read 5, iclass 6, count 0 2006.257.20:34:07.22#ibcon#about to read 6, iclass 6, count 0 2006.257.20:34:07.22#ibcon#read 6, iclass 6, count 0 2006.257.20:34:07.22#ibcon#end of sib2, iclass 6, count 0 2006.257.20:34:07.22#ibcon#*after write, iclass 6, count 0 2006.257.20:34:07.22#ibcon#*before return 0, iclass 6, count 0 2006.257.20:34:07.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:34:07.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:34:07.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.20:34:07.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.20:34:07.22$vck44/vb=1,4 2006.257.20:34:07.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.20:34:07.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.20:34:07.22#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:07.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:34:07.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:34:07.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:34:07.22#ibcon#enter wrdev, iclass 10, count 2 2006.257.20:34:07.22#ibcon#first serial, iclass 10, count 2 2006.257.20:34:07.22#ibcon#enter sib2, iclass 10, count 2 2006.257.20:34:07.22#ibcon#flushed, iclass 10, count 2 2006.257.20:34:07.22#ibcon#about to write, iclass 10, count 2 2006.257.20:34:07.22#ibcon#wrote, iclass 10, count 2 2006.257.20:34:07.22#ibcon#about to read 3, iclass 10, count 2 2006.257.20:34:07.24#ibcon#read 3, iclass 10, count 2 2006.257.20:34:07.24#ibcon#about to read 4, iclass 10, count 2 2006.257.20:34:07.24#ibcon#read 4, iclass 10, count 2 2006.257.20:34:07.24#ibcon#about to read 5, iclass 10, count 2 2006.257.20:34:07.24#ibcon#read 5, iclass 10, count 2 2006.257.20:34:07.24#ibcon#about to read 6, iclass 10, count 2 2006.257.20:34:07.24#ibcon#read 6, iclass 10, count 2 2006.257.20:34:07.24#ibcon#end of sib2, iclass 10, count 2 2006.257.20:34:07.24#ibcon#*mode == 0, iclass 10, count 2 2006.257.20:34:07.24#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.20:34:07.24#ibcon#[27=AT01-04\r\n] 2006.257.20:34:07.24#ibcon#*before write, iclass 10, count 2 2006.257.20:34:07.24#ibcon#enter sib2, iclass 10, count 2 2006.257.20:34:07.24#ibcon#flushed, iclass 10, count 2 2006.257.20:34:07.24#ibcon#about to write, iclass 10, count 2 2006.257.20:34:07.24#ibcon#wrote, iclass 10, count 2 2006.257.20:34:07.24#ibcon#about to read 3, iclass 10, count 2 2006.257.20:34:07.27#ibcon#read 3, iclass 10, count 2 2006.257.20:34:07.27#ibcon#about to read 4, iclass 10, count 2 2006.257.20:34:07.27#ibcon#read 4, iclass 10, count 2 2006.257.20:34:07.27#ibcon#about to read 5, iclass 10, count 2 2006.257.20:34:07.27#ibcon#read 5, iclass 10, count 2 2006.257.20:34:07.27#ibcon#about to read 6, iclass 10, count 2 2006.257.20:34:07.27#ibcon#read 6, iclass 10, count 2 2006.257.20:34:07.27#ibcon#end of sib2, iclass 10, count 2 2006.257.20:34:07.27#ibcon#*after write, iclass 10, count 2 2006.257.20:34:07.27#ibcon#*before return 0, iclass 10, count 2 2006.257.20:34:07.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:34:07.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:34:07.27#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.20:34:07.27#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:07.27#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:34:07.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:34:07.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:34:07.39#ibcon#enter wrdev, iclass 10, count 0 2006.257.20:34:07.39#ibcon#first serial, iclass 10, count 0 2006.257.20:34:07.39#ibcon#enter sib2, iclass 10, count 0 2006.257.20:34:07.39#ibcon#flushed, iclass 10, count 0 2006.257.20:34:07.39#ibcon#about to write, iclass 10, count 0 2006.257.20:34:07.39#ibcon#wrote, iclass 10, count 0 2006.257.20:34:07.39#ibcon#about to read 3, iclass 10, count 0 2006.257.20:34:07.41#ibcon#read 3, iclass 10, count 0 2006.257.20:34:07.41#ibcon#about to read 4, iclass 10, count 0 2006.257.20:34:07.41#ibcon#read 4, iclass 10, count 0 2006.257.20:34:07.41#ibcon#about to read 5, iclass 10, count 0 2006.257.20:34:07.41#ibcon#read 5, iclass 10, count 0 2006.257.20:34:07.41#ibcon#about to read 6, iclass 10, count 0 2006.257.20:34:07.41#ibcon#read 6, iclass 10, count 0 2006.257.20:34:07.41#ibcon#end of sib2, iclass 10, count 0 2006.257.20:34:07.41#ibcon#*mode == 0, iclass 10, count 0 2006.257.20:34:07.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.20:34:07.41#ibcon#[27=USB\r\n] 2006.257.20:34:07.41#ibcon#*before write, iclass 10, count 0 2006.257.20:34:07.41#ibcon#enter sib2, iclass 10, count 0 2006.257.20:34:07.41#ibcon#flushed, iclass 10, count 0 2006.257.20:34:07.41#ibcon#about to write, iclass 10, count 0 2006.257.20:34:07.41#ibcon#wrote, iclass 10, count 0 2006.257.20:34:07.41#ibcon#about to read 3, iclass 10, count 0 2006.257.20:34:07.44#ibcon#read 3, iclass 10, count 0 2006.257.20:34:07.44#ibcon#about to read 4, iclass 10, count 0 2006.257.20:34:07.44#ibcon#read 4, iclass 10, count 0 2006.257.20:34:07.44#ibcon#about to read 5, iclass 10, count 0 2006.257.20:34:07.44#ibcon#read 5, iclass 10, count 0 2006.257.20:34:07.44#ibcon#about to read 6, iclass 10, count 0 2006.257.20:34:07.44#ibcon#read 6, iclass 10, count 0 2006.257.20:34:07.44#ibcon#end of sib2, iclass 10, count 0 2006.257.20:34:07.44#ibcon#*after write, iclass 10, count 0 2006.257.20:34:07.44#ibcon#*before return 0, iclass 10, count 0 2006.257.20:34:07.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:34:07.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:34:07.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.20:34:07.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.20:34:07.44$vck44/vblo=2,634.99 2006.257.20:34:07.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.20:34:07.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.20:34:07.44#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:07.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:07.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:07.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:07.44#ibcon#enter wrdev, iclass 12, count 0 2006.257.20:34:07.44#ibcon#first serial, iclass 12, count 0 2006.257.20:34:07.44#ibcon#enter sib2, iclass 12, count 0 2006.257.20:34:07.44#ibcon#flushed, iclass 12, count 0 2006.257.20:34:07.44#ibcon#about to write, iclass 12, count 0 2006.257.20:34:07.44#ibcon#wrote, iclass 12, count 0 2006.257.20:34:07.44#ibcon#about to read 3, iclass 12, count 0 2006.257.20:34:07.46#ibcon#read 3, iclass 12, count 0 2006.257.20:34:07.46#ibcon#about to read 4, iclass 12, count 0 2006.257.20:34:07.46#ibcon#read 4, iclass 12, count 0 2006.257.20:34:07.46#ibcon#about to read 5, iclass 12, count 0 2006.257.20:34:07.46#ibcon#read 5, iclass 12, count 0 2006.257.20:34:07.46#ibcon#about to read 6, iclass 12, count 0 2006.257.20:34:07.46#ibcon#read 6, iclass 12, count 0 2006.257.20:34:07.46#ibcon#end of sib2, iclass 12, count 0 2006.257.20:34:07.46#ibcon#*mode == 0, iclass 12, count 0 2006.257.20:34:07.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.20:34:07.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.20:34:07.46#ibcon#*before write, iclass 12, count 0 2006.257.20:34:07.46#ibcon#enter sib2, iclass 12, count 0 2006.257.20:34:07.46#ibcon#flushed, iclass 12, count 0 2006.257.20:34:07.46#ibcon#about to write, iclass 12, count 0 2006.257.20:34:07.46#ibcon#wrote, iclass 12, count 0 2006.257.20:34:07.46#ibcon#about to read 3, iclass 12, count 0 2006.257.20:34:07.50#ibcon#read 3, iclass 12, count 0 2006.257.20:34:07.50#ibcon#about to read 4, iclass 12, count 0 2006.257.20:34:07.50#ibcon#read 4, iclass 12, count 0 2006.257.20:34:07.50#ibcon#about to read 5, iclass 12, count 0 2006.257.20:34:07.50#ibcon#read 5, iclass 12, count 0 2006.257.20:34:07.50#ibcon#about to read 6, iclass 12, count 0 2006.257.20:34:07.50#ibcon#read 6, iclass 12, count 0 2006.257.20:34:07.50#ibcon#end of sib2, iclass 12, count 0 2006.257.20:34:07.50#ibcon#*after write, iclass 12, count 0 2006.257.20:34:07.50#ibcon#*before return 0, iclass 12, count 0 2006.257.20:34:07.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:07.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:34:07.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.20:34:07.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.20:34:07.50$vck44/vb=2,5 2006.257.20:34:07.50#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.20:34:07.50#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.20:34:07.50#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:07.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:07.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:07.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:07.56#ibcon#enter wrdev, iclass 14, count 2 2006.257.20:34:07.56#ibcon#first serial, iclass 14, count 2 2006.257.20:34:07.56#ibcon#enter sib2, iclass 14, count 2 2006.257.20:34:07.56#ibcon#flushed, iclass 14, count 2 2006.257.20:34:07.56#ibcon#about to write, iclass 14, count 2 2006.257.20:34:07.56#ibcon#wrote, iclass 14, count 2 2006.257.20:34:07.56#ibcon#about to read 3, iclass 14, count 2 2006.257.20:34:07.58#ibcon#read 3, iclass 14, count 2 2006.257.20:34:07.58#ibcon#about to read 4, iclass 14, count 2 2006.257.20:34:07.58#ibcon#read 4, iclass 14, count 2 2006.257.20:34:07.58#ibcon#about to read 5, iclass 14, count 2 2006.257.20:34:07.58#ibcon#read 5, iclass 14, count 2 2006.257.20:34:07.58#ibcon#about to read 6, iclass 14, count 2 2006.257.20:34:07.58#ibcon#read 6, iclass 14, count 2 2006.257.20:34:07.58#ibcon#end of sib2, iclass 14, count 2 2006.257.20:34:07.58#ibcon#*mode == 0, iclass 14, count 2 2006.257.20:34:07.58#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.20:34:07.58#ibcon#[27=AT02-05\r\n] 2006.257.20:34:07.58#ibcon#*before write, iclass 14, count 2 2006.257.20:34:07.58#ibcon#enter sib2, iclass 14, count 2 2006.257.20:34:07.58#ibcon#flushed, iclass 14, count 2 2006.257.20:34:07.58#ibcon#about to write, iclass 14, count 2 2006.257.20:34:07.58#ibcon#wrote, iclass 14, count 2 2006.257.20:34:07.58#ibcon#about to read 3, iclass 14, count 2 2006.257.20:34:07.61#ibcon#read 3, iclass 14, count 2 2006.257.20:34:07.61#ibcon#about to read 4, iclass 14, count 2 2006.257.20:34:07.61#ibcon#read 4, iclass 14, count 2 2006.257.20:34:07.61#ibcon#about to read 5, iclass 14, count 2 2006.257.20:34:07.61#ibcon#read 5, iclass 14, count 2 2006.257.20:34:07.61#ibcon#about to read 6, iclass 14, count 2 2006.257.20:34:07.61#ibcon#read 6, iclass 14, count 2 2006.257.20:34:07.61#ibcon#end of sib2, iclass 14, count 2 2006.257.20:34:07.61#ibcon#*after write, iclass 14, count 2 2006.257.20:34:07.61#ibcon#*before return 0, iclass 14, count 2 2006.257.20:34:07.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:07.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:34:07.61#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.20:34:07.61#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:07.61#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:07.73#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:07.73#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:07.73#ibcon#enter wrdev, iclass 14, count 0 2006.257.20:34:07.73#ibcon#first serial, iclass 14, count 0 2006.257.20:34:07.73#ibcon#enter sib2, iclass 14, count 0 2006.257.20:34:07.73#ibcon#flushed, iclass 14, count 0 2006.257.20:34:07.73#ibcon#about to write, iclass 14, count 0 2006.257.20:34:07.73#ibcon#wrote, iclass 14, count 0 2006.257.20:34:07.73#ibcon#about to read 3, iclass 14, count 0 2006.257.20:34:07.75#ibcon#read 3, iclass 14, count 0 2006.257.20:34:07.75#ibcon#about to read 4, iclass 14, count 0 2006.257.20:34:07.75#ibcon#read 4, iclass 14, count 0 2006.257.20:34:07.75#ibcon#about to read 5, iclass 14, count 0 2006.257.20:34:07.75#ibcon#read 5, iclass 14, count 0 2006.257.20:34:07.75#ibcon#about to read 6, iclass 14, count 0 2006.257.20:34:07.75#ibcon#read 6, iclass 14, count 0 2006.257.20:34:07.75#ibcon#end of sib2, iclass 14, count 0 2006.257.20:34:07.75#ibcon#*mode == 0, iclass 14, count 0 2006.257.20:34:07.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.20:34:07.75#ibcon#[27=USB\r\n] 2006.257.20:34:07.75#ibcon#*before write, iclass 14, count 0 2006.257.20:34:07.75#ibcon#enter sib2, iclass 14, count 0 2006.257.20:34:07.75#ibcon#flushed, iclass 14, count 0 2006.257.20:34:07.75#ibcon#about to write, iclass 14, count 0 2006.257.20:34:07.75#ibcon#wrote, iclass 14, count 0 2006.257.20:34:07.75#ibcon#about to read 3, iclass 14, count 0 2006.257.20:34:07.78#ibcon#read 3, iclass 14, count 0 2006.257.20:34:07.78#ibcon#about to read 4, iclass 14, count 0 2006.257.20:34:07.78#ibcon#read 4, iclass 14, count 0 2006.257.20:34:07.78#ibcon#about to read 5, iclass 14, count 0 2006.257.20:34:07.78#ibcon#read 5, iclass 14, count 0 2006.257.20:34:07.78#ibcon#about to read 6, iclass 14, count 0 2006.257.20:34:07.78#ibcon#read 6, iclass 14, count 0 2006.257.20:34:07.78#ibcon#end of sib2, iclass 14, count 0 2006.257.20:34:07.78#ibcon#*after write, iclass 14, count 0 2006.257.20:34:07.78#ibcon#*before return 0, iclass 14, count 0 2006.257.20:34:07.78#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:07.78#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:34:07.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.20:34:07.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.20:34:07.78$vck44/vblo=3,649.99 2006.257.20:34:07.78#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.20:34:07.78#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.20:34:07.78#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:07.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:07.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:07.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:07.78#ibcon#enter wrdev, iclass 16, count 0 2006.257.20:34:07.78#ibcon#first serial, iclass 16, count 0 2006.257.20:34:07.78#ibcon#enter sib2, iclass 16, count 0 2006.257.20:34:07.78#ibcon#flushed, iclass 16, count 0 2006.257.20:34:07.78#ibcon#about to write, iclass 16, count 0 2006.257.20:34:07.78#ibcon#wrote, iclass 16, count 0 2006.257.20:34:07.78#ibcon#about to read 3, iclass 16, count 0 2006.257.20:34:07.80#ibcon#read 3, iclass 16, count 0 2006.257.20:34:07.80#ibcon#about to read 4, iclass 16, count 0 2006.257.20:34:07.80#ibcon#read 4, iclass 16, count 0 2006.257.20:34:07.80#ibcon#about to read 5, iclass 16, count 0 2006.257.20:34:07.80#ibcon#read 5, iclass 16, count 0 2006.257.20:34:07.80#ibcon#about to read 6, iclass 16, count 0 2006.257.20:34:07.80#ibcon#read 6, iclass 16, count 0 2006.257.20:34:07.80#ibcon#end of sib2, iclass 16, count 0 2006.257.20:34:07.80#ibcon#*mode == 0, iclass 16, count 0 2006.257.20:34:07.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.20:34:07.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.20:34:07.80#ibcon#*before write, iclass 16, count 0 2006.257.20:34:07.80#ibcon#enter sib2, iclass 16, count 0 2006.257.20:34:07.80#ibcon#flushed, iclass 16, count 0 2006.257.20:34:07.80#ibcon#about to write, iclass 16, count 0 2006.257.20:34:07.80#ibcon#wrote, iclass 16, count 0 2006.257.20:34:07.80#ibcon#about to read 3, iclass 16, count 0 2006.257.20:34:07.84#ibcon#read 3, iclass 16, count 0 2006.257.20:34:07.84#ibcon#about to read 4, iclass 16, count 0 2006.257.20:34:07.84#ibcon#read 4, iclass 16, count 0 2006.257.20:34:07.84#ibcon#about to read 5, iclass 16, count 0 2006.257.20:34:07.84#ibcon#read 5, iclass 16, count 0 2006.257.20:34:07.84#ibcon#about to read 6, iclass 16, count 0 2006.257.20:34:07.84#ibcon#read 6, iclass 16, count 0 2006.257.20:34:07.84#ibcon#end of sib2, iclass 16, count 0 2006.257.20:34:07.84#ibcon#*after write, iclass 16, count 0 2006.257.20:34:07.84#ibcon#*before return 0, iclass 16, count 0 2006.257.20:34:07.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:07.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:34:07.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.20:34:07.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.20:34:07.84$vck44/vb=3,4 2006.257.20:34:07.84#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.20:34:07.84#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.20:34:07.84#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:07.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:07.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:07.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:07.90#ibcon#enter wrdev, iclass 18, count 2 2006.257.20:34:07.90#ibcon#first serial, iclass 18, count 2 2006.257.20:34:07.90#ibcon#enter sib2, iclass 18, count 2 2006.257.20:34:07.90#ibcon#flushed, iclass 18, count 2 2006.257.20:34:07.90#ibcon#about to write, iclass 18, count 2 2006.257.20:34:07.90#ibcon#wrote, iclass 18, count 2 2006.257.20:34:07.90#ibcon#about to read 3, iclass 18, count 2 2006.257.20:34:07.92#ibcon#read 3, iclass 18, count 2 2006.257.20:34:07.92#ibcon#about to read 4, iclass 18, count 2 2006.257.20:34:07.92#ibcon#read 4, iclass 18, count 2 2006.257.20:34:07.92#ibcon#about to read 5, iclass 18, count 2 2006.257.20:34:07.92#ibcon#read 5, iclass 18, count 2 2006.257.20:34:07.92#ibcon#about to read 6, iclass 18, count 2 2006.257.20:34:07.92#ibcon#read 6, iclass 18, count 2 2006.257.20:34:07.92#ibcon#end of sib2, iclass 18, count 2 2006.257.20:34:07.92#ibcon#*mode == 0, iclass 18, count 2 2006.257.20:34:07.92#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.20:34:07.92#ibcon#[27=AT03-04\r\n] 2006.257.20:34:07.92#ibcon#*before write, iclass 18, count 2 2006.257.20:34:07.92#ibcon#enter sib2, iclass 18, count 2 2006.257.20:34:07.92#ibcon#flushed, iclass 18, count 2 2006.257.20:34:07.92#ibcon#about to write, iclass 18, count 2 2006.257.20:34:07.92#ibcon#wrote, iclass 18, count 2 2006.257.20:34:07.92#ibcon#about to read 3, iclass 18, count 2 2006.257.20:34:07.95#ibcon#read 3, iclass 18, count 2 2006.257.20:34:07.95#ibcon#about to read 4, iclass 18, count 2 2006.257.20:34:07.95#ibcon#read 4, iclass 18, count 2 2006.257.20:34:07.95#ibcon#about to read 5, iclass 18, count 2 2006.257.20:34:07.95#ibcon#read 5, iclass 18, count 2 2006.257.20:34:07.95#ibcon#about to read 6, iclass 18, count 2 2006.257.20:34:07.95#ibcon#read 6, iclass 18, count 2 2006.257.20:34:07.95#ibcon#end of sib2, iclass 18, count 2 2006.257.20:34:07.95#ibcon#*after write, iclass 18, count 2 2006.257.20:34:07.95#ibcon#*before return 0, iclass 18, count 2 2006.257.20:34:07.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:07.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:34:07.95#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.20:34:07.95#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:07.95#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:08.07#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:08.07#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:08.07#ibcon#enter wrdev, iclass 18, count 0 2006.257.20:34:08.07#ibcon#first serial, iclass 18, count 0 2006.257.20:34:08.07#ibcon#enter sib2, iclass 18, count 0 2006.257.20:34:08.07#ibcon#flushed, iclass 18, count 0 2006.257.20:34:08.07#ibcon#about to write, iclass 18, count 0 2006.257.20:34:08.07#ibcon#wrote, iclass 18, count 0 2006.257.20:34:08.07#ibcon#about to read 3, iclass 18, count 0 2006.257.20:34:08.09#ibcon#read 3, iclass 18, count 0 2006.257.20:34:08.09#ibcon#about to read 4, iclass 18, count 0 2006.257.20:34:08.09#ibcon#read 4, iclass 18, count 0 2006.257.20:34:08.09#ibcon#about to read 5, iclass 18, count 0 2006.257.20:34:08.09#ibcon#read 5, iclass 18, count 0 2006.257.20:34:08.09#ibcon#about to read 6, iclass 18, count 0 2006.257.20:34:08.09#ibcon#read 6, iclass 18, count 0 2006.257.20:34:08.09#ibcon#end of sib2, iclass 18, count 0 2006.257.20:34:08.09#ibcon#*mode == 0, iclass 18, count 0 2006.257.20:34:08.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.20:34:08.09#ibcon#[27=USB\r\n] 2006.257.20:34:08.09#ibcon#*before write, iclass 18, count 0 2006.257.20:34:08.09#ibcon#enter sib2, iclass 18, count 0 2006.257.20:34:08.09#ibcon#flushed, iclass 18, count 0 2006.257.20:34:08.09#ibcon#about to write, iclass 18, count 0 2006.257.20:34:08.09#ibcon#wrote, iclass 18, count 0 2006.257.20:34:08.09#ibcon#about to read 3, iclass 18, count 0 2006.257.20:34:08.12#ibcon#read 3, iclass 18, count 0 2006.257.20:34:08.12#ibcon#about to read 4, iclass 18, count 0 2006.257.20:34:08.12#ibcon#read 4, iclass 18, count 0 2006.257.20:34:08.12#ibcon#about to read 5, iclass 18, count 0 2006.257.20:34:08.12#ibcon#read 5, iclass 18, count 0 2006.257.20:34:08.12#ibcon#about to read 6, iclass 18, count 0 2006.257.20:34:08.12#ibcon#read 6, iclass 18, count 0 2006.257.20:34:08.12#ibcon#end of sib2, iclass 18, count 0 2006.257.20:34:08.12#ibcon#*after write, iclass 18, count 0 2006.257.20:34:08.12#ibcon#*before return 0, iclass 18, count 0 2006.257.20:34:08.12#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:08.12#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:34:08.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.20:34:08.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.20:34:08.12$vck44/vblo=4,679.99 2006.257.20:34:08.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.20:34:08.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.20:34:08.12#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:08.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:08.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:08.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:08.12#ibcon#enter wrdev, iclass 20, count 0 2006.257.20:34:08.12#ibcon#first serial, iclass 20, count 0 2006.257.20:34:08.12#ibcon#enter sib2, iclass 20, count 0 2006.257.20:34:08.12#ibcon#flushed, iclass 20, count 0 2006.257.20:34:08.12#ibcon#about to write, iclass 20, count 0 2006.257.20:34:08.12#ibcon#wrote, iclass 20, count 0 2006.257.20:34:08.12#ibcon#about to read 3, iclass 20, count 0 2006.257.20:34:08.14#ibcon#read 3, iclass 20, count 0 2006.257.20:34:08.14#ibcon#about to read 4, iclass 20, count 0 2006.257.20:34:08.14#ibcon#read 4, iclass 20, count 0 2006.257.20:34:08.14#ibcon#about to read 5, iclass 20, count 0 2006.257.20:34:08.14#ibcon#read 5, iclass 20, count 0 2006.257.20:34:08.14#ibcon#about to read 6, iclass 20, count 0 2006.257.20:34:08.14#ibcon#read 6, iclass 20, count 0 2006.257.20:34:08.14#ibcon#end of sib2, iclass 20, count 0 2006.257.20:34:08.14#ibcon#*mode == 0, iclass 20, count 0 2006.257.20:34:08.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.20:34:08.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.20:34:08.14#ibcon#*before write, iclass 20, count 0 2006.257.20:34:08.14#ibcon#enter sib2, iclass 20, count 0 2006.257.20:34:08.14#ibcon#flushed, iclass 20, count 0 2006.257.20:34:08.14#ibcon#about to write, iclass 20, count 0 2006.257.20:34:08.14#ibcon#wrote, iclass 20, count 0 2006.257.20:34:08.14#ibcon#about to read 3, iclass 20, count 0 2006.257.20:34:08.18#ibcon#read 3, iclass 20, count 0 2006.257.20:34:08.18#ibcon#about to read 4, iclass 20, count 0 2006.257.20:34:08.18#ibcon#read 4, iclass 20, count 0 2006.257.20:34:08.18#ibcon#about to read 5, iclass 20, count 0 2006.257.20:34:08.18#ibcon#read 5, iclass 20, count 0 2006.257.20:34:08.18#ibcon#about to read 6, iclass 20, count 0 2006.257.20:34:08.18#ibcon#read 6, iclass 20, count 0 2006.257.20:34:08.18#ibcon#end of sib2, iclass 20, count 0 2006.257.20:34:08.18#ibcon#*after write, iclass 20, count 0 2006.257.20:34:08.18#ibcon#*before return 0, iclass 20, count 0 2006.257.20:34:08.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:08.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:34:08.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.20:34:08.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.20:34:08.18$vck44/vb=4,5 2006.257.20:34:08.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.20:34:08.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.20:34:08.18#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:08.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:08.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:08.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:08.24#ibcon#enter wrdev, iclass 22, count 2 2006.257.20:34:08.24#ibcon#first serial, iclass 22, count 2 2006.257.20:34:08.24#ibcon#enter sib2, iclass 22, count 2 2006.257.20:34:08.24#ibcon#flushed, iclass 22, count 2 2006.257.20:34:08.24#ibcon#about to write, iclass 22, count 2 2006.257.20:34:08.24#ibcon#wrote, iclass 22, count 2 2006.257.20:34:08.24#ibcon#about to read 3, iclass 22, count 2 2006.257.20:34:08.26#ibcon#read 3, iclass 22, count 2 2006.257.20:34:08.26#ibcon#about to read 4, iclass 22, count 2 2006.257.20:34:08.26#ibcon#read 4, iclass 22, count 2 2006.257.20:34:08.26#ibcon#about to read 5, iclass 22, count 2 2006.257.20:34:08.26#ibcon#read 5, iclass 22, count 2 2006.257.20:34:08.26#ibcon#about to read 6, iclass 22, count 2 2006.257.20:34:08.26#ibcon#read 6, iclass 22, count 2 2006.257.20:34:08.26#ibcon#end of sib2, iclass 22, count 2 2006.257.20:34:08.26#ibcon#*mode == 0, iclass 22, count 2 2006.257.20:34:08.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.20:34:08.26#ibcon#[27=AT04-05\r\n] 2006.257.20:34:08.26#ibcon#*before write, iclass 22, count 2 2006.257.20:34:08.26#ibcon#enter sib2, iclass 22, count 2 2006.257.20:34:08.26#ibcon#flushed, iclass 22, count 2 2006.257.20:34:08.26#ibcon#about to write, iclass 22, count 2 2006.257.20:34:08.26#ibcon#wrote, iclass 22, count 2 2006.257.20:34:08.26#ibcon#about to read 3, iclass 22, count 2 2006.257.20:34:08.29#ibcon#read 3, iclass 22, count 2 2006.257.20:34:08.29#ibcon#about to read 4, iclass 22, count 2 2006.257.20:34:08.29#ibcon#read 4, iclass 22, count 2 2006.257.20:34:08.29#ibcon#about to read 5, iclass 22, count 2 2006.257.20:34:08.29#ibcon#read 5, iclass 22, count 2 2006.257.20:34:08.29#ibcon#about to read 6, iclass 22, count 2 2006.257.20:34:08.29#ibcon#read 6, iclass 22, count 2 2006.257.20:34:08.29#ibcon#end of sib2, iclass 22, count 2 2006.257.20:34:08.29#ibcon#*after write, iclass 22, count 2 2006.257.20:34:08.29#ibcon#*before return 0, iclass 22, count 2 2006.257.20:34:08.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:08.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:34:08.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.20:34:08.29#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:08.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:08.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:08.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:08.41#ibcon#enter wrdev, iclass 22, count 0 2006.257.20:34:08.41#ibcon#first serial, iclass 22, count 0 2006.257.20:34:08.41#ibcon#enter sib2, iclass 22, count 0 2006.257.20:34:08.41#ibcon#flushed, iclass 22, count 0 2006.257.20:34:08.41#ibcon#about to write, iclass 22, count 0 2006.257.20:34:08.41#ibcon#wrote, iclass 22, count 0 2006.257.20:34:08.41#ibcon#about to read 3, iclass 22, count 0 2006.257.20:34:08.43#ibcon#read 3, iclass 22, count 0 2006.257.20:34:08.43#ibcon#about to read 4, iclass 22, count 0 2006.257.20:34:08.43#ibcon#read 4, iclass 22, count 0 2006.257.20:34:08.43#ibcon#about to read 5, iclass 22, count 0 2006.257.20:34:08.43#ibcon#read 5, iclass 22, count 0 2006.257.20:34:08.43#ibcon#about to read 6, iclass 22, count 0 2006.257.20:34:08.43#ibcon#read 6, iclass 22, count 0 2006.257.20:34:08.43#ibcon#end of sib2, iclass 22, count 0 2006.257.20:34:08.43#ibcon#*mode == 0, iclass 22, count 0 2006.257.20:34:08.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.20:34:08.43#ibcon#[27=USB\r\n] 2006.257.20:34:08.43#ibcon#*before write, iclass 22, count 0 2006.257.20:34:08.43#ibcon#enter sib2, iclass 22, count 0 2006.257.20:34:08.43#ibcon#flushed, iclass 22, count 0 2006.257.20:34:08.43#ibcon#about to write, iclass 22, count 0 2006.257.20:34:08.43#ibcon#wrote, iclass 22, count 0 2006.257.20:34:08.43#ibcon#about to read 3, iclass 22, count 0 2006.257.20:34:08.46#ibcon#read 3, iclass 22, count 0 2006.257.20:34:08.46#ibcon#about to read 4, iclass 22, count 0 2006.257.20:34:08.46#ibcon#read 4, iclass 22, count 0 2006.257.20:34:08.46#ibcon#about to read 5, iclass 22, count 0 2006.257.20:34:08.46#ibcon#read 5, iclass 22, count 0 2006.257.20:34:08.46#ibcon#about to read 6, iclass 22, count 0 2006.257.20:34:08.46#ibcon#read 6, iclass 22, count 0 2006.257.20:34:08.46#ibcon#end of sib2, iclass 22, count 0 2006.257.20:34:08.46#ibcon#*after write, iclass 22, count 0 2006.257.20:34:08.46#ibcon#*before return 0, iclass 22, count 0 2006.257.20:34:08.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:08.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:34:08.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.20:34:08.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.20:34:08.46$vck44/vblo=5,709.99 2006.257.20:34:08.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.20:34:08.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.20:34:08.46#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:08.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:08.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:08.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:08.46#ibcon#enter wrdev, iclass 24, count 0 2006.257.20:34:08.46#ibcon#first serial, iclass 24, count 0 2006.257.20:34:08.46#ibcon#enter sib2, iclass 24, count 0 2006.257.20:34:08.46#ibcon#flushed, iclass 24, count 0 2006.257.20:34:08.46#ibcon#about to write, iclass 24, count 0 2006.257.20:34:08.46#ibcon#wrote, iclass 24, count 0 2006.257.20:34:08.46#ibcon#about to read 3, iclass 24, count 0 2006.257.20:34:08.48#ibcon#read 3, iclass 24, count 0 2006.257.20:34:08.48#ibcon#about to read 4, iclass 24, count 0 2006.257.20:34:08.48#ibcon#read 4, iclass 24, count 0 2006.257.20:34:08.48#ibcon#about to read 5, iclass 24, count 0 2006.257.20:34:08.48#ibcon#read 5, iclass 24, count 0 2006.257.20:34:08.48#ibcon#about to read 6, iclass 24, count 0 2006.257.20:34:08.48#ibcon#read 6, iclass 24, count 0 2006.257.20:34:08.48#ibcon#end of sib2, iclass 24, count 0 2006.257.20:34:08.48#ibcon#*mode == 0, iclass 24, count 0 2006.257.20:34:08.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.20:34:08.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.20:34:08.48#ibcon#*before write, iclass 24, count 0 2006.257.20:34:08.48#ibcon#enter sib2, iclass 24, count 0 2006.257.20:34:08.48#ibcon#flushed, iclass 24, count 0 2006.257.20:34:08.48#ibcon#about to write, iclass 24, count 0 2006.257.20:34:08.48#ibcon#wrote, iclass 24, count 0 2006.257.20:34:08.48#ibcon#about to read 3, iclass 24, count 0 2006.257.20:34:08.52#ibcon#read 3, iclass 24, count 0 2006.257.20:34:08.52#ibcon#about to read 4, iclass 24, count 0 2006.257.20:34:08.52#ibcon#read 4, iclass 24, count 0 2006.257.20:34:08.52#ibcon#about to read 5, iclass 24, count 0 2006.257.20:34:08.52#ibcon#read 5, iclass 24, count 0 2006.257.20:34:08.52#ibcon#about to read 6, iclass 24, count 0 2006.257.20:34:08.52#ibcon#read 6, iclass 24, count 0 2006.257.20:34:08.52#ibcon#end of sib2, iclass 24, count 0 2006.257.20:34:08.52#ibcon#*after write, iclass 24, count 0 2006.257.20:34:08.52#ibcon#*before return 0, iclass 24, count 0 2006.257.20:34:08.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:08.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:34:08.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.20:34:08.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.20:34:08.52$vck44/vb=5,4 2006.257.20:34:08.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.20:34:08.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.20:34:08.52#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:08.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:08.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:08.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:08.58#ibcon#enter wrdev, iclass 26, count 2 2006.257.20:34:08.58#ibcon#first serial, iclass 26, count 2 2006.257.20:34:08.58#ibcon#enter sib2, iclass 26, count 2 2006.257.20:34:08.58#ibcon#flushed, iclass 26, count 2 2006.257.20:34:08.58#ibcon#about to write, iclass 26, count 2 2006.257.20:34:08.58#ibcon#wrote, iclass 26, count 2 2006.257.20:34:08.58#ibcon#about to read 3, iclass 26, count 2 2006.257.20:34:08.60#ibcon#read 3, iclass 26, count 2 2006.257.20:34:08.60#ibcon#about to read 4, iclass 26, count 2 2006.257.20:34:08.60#ibcon#read 4, iclass 26, count 2 2006.257.20:34:08.60#ibcon#about to read 5, iclass 26, count 2 2006.257.20:34:08.60#ibcon#read 5, iclass 26, count 2 2006.257.20:34:08.60#ibcon#about to read 6, iclass 26, count 2 2006.257.20:34:08.60#ibcon#read 6, iclass 26, count 2 2006.257.20:34:08.60#ibcon#end of sib2, iclass 26, count 2 2006.257.20:34:08.60#ibcon#*mode == 0, iclass 26, count 2 2006.257.20:34:08.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.20:34:08.60#ibcon#[27=AT05-04\r\n] 2006.257.20:34:08.60#ibcon#*before write, iclass 26, count 2 2006.257.20:34:08.60#ibcon#enter sib2, iclass 26, count 2 2006.257.20:34:08.60#ibcon#flushed, iclass 26, count 2 2006.257.20:34:08.60#ibcon#about to write, iclass 26, count 2 2006.257.20:34:08.60#ibcon#wrote, iclass 26, count 2 2006.257.20:34:08.60#ibcon#about to read 3, iclass 26, count 2 2006.257.20:34:08.63#ibcon#read 3, iclass 26, count 2 2006.257.20:34:08.63#ibcon#about to read 4, iclass 26, count 2 2006.257.20:34:08.63#ibcon#read 4, iclass 26, count 2 2006.257.20:34:08.63#ibcon#about to read 5, iclass 26, count 2 2006.257.20:34:08.63#ibcon#read 5, iclass 26, count 2 2006.257.20:34:08.63#ibcon#about to read 6, iclass 26, count 2 2006.257.20:34:08.63#ibcon#read 6, iclass 26, count 2 2006.257.20:34:08.63#ibcon#end of sib2, iclass 26, count 2 2006.257.20:34:08.63#ibcon#*after write, iclass 26, count 2 2006.257.20:34:08.63#ibcon#*before return 0, iclass 26, count 2 2006.257.20:34:08.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:08.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:34:08.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.20:34:08.63#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:08.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:08.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:08.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:08.75#ibcon#enter wrdev, iclass 26, count 0 2006.257.20:34:08.75#ibcon#first serial, iclass 26, count 0 2006.257.20:34:08.75#ibcon#enter sib2, iclass 26, count 0 2006.257.20:34:08.75#ibcon#flushed, iclass 26, count 0 2006.257.20:34:08.75#ibcon#about to write, iclass 26, count 0 2006.257.20:34:08.75#ibcon#wrote, iclass 26, count 0 2006.257.20:34:08.75#ibcon#about to read 3, iclass 26, count 0 2006.257.20:34:08.77#ibcon#read 3, iclass 26, count 0 2006.257.20:34:08.77#ibcon#about to read 4, iclass 26, count 0 2006.257.20:34:08.77#ibcon#read 4, iclass 26, count 0 2006.257.20:34:08.77#ibcon#about to read 5, iclass 26, count 0 2006.257.20:34:08.77#ibcon#read 5, iclass 26, count 0 2006.257.20:34:08.77#ibcon#about to read 6, iclass 26, count 0 2006.257.20:34:08.77#ibcon#read 6, iclass 26, count 0 2006.257.20:34:08.77#ibcon#end of sib2, iclass 26, count 0 2006.257.20:34:08.77#ibcon#*mode == 0, iclass 26, count 0 2006.257.20:34:08.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.20:34:08.77#ibcon#[27=USB\r\n] 2006.257.20:34:08.77#ibcon#*before write, iclass 26, count 0 2006.257.20:34:08.77#ibcon#enter sib2, iclass 26, count 0 2006.257.20:34:08.77#ibcon#flushed, iclass 26, count 0 2006.257.20:34:08.77#ibcon#about to write, iclass 26, count 0 2006.257.20:34:08.77#ibcon#wrote, iclass 26, count 0 2006.257.20:34:08.77#ibcon#about to read 3, iclass 26, count 0 2006.257.20:34:08.80#ibcon#read 3, iclass 26, count 0 2006.257.20:34:08.80#ibcon#about to read 4, iclass 26, count 0 2006.257.20:34:08.80#ibcon#read 4, iclass 26, count 0 2006.257.20:34:08.80#ibcon#about to read 5, iclass 26, count 0 2006.257.20:34:08.80#ibcon#read 5, iclass 26, count 0 2006.257.20:34:08.80#ibcon#about to read 6, iclass 26, count 0 2006.257.20:34:08.80#ibcon#read 6, iclass 26, count 0 2006.257.20:34:08.80#ibcon#end of sib2, iclass 26, count 0 2006.257.20:34:08.80#ibcon#*after write, iclass 26, count 0 2006.257.20:34:08.80#ibcon#*before return 0, iclass 26, count 0 2006.257.20:34:08.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:08.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:34:08.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.20:34:08.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.20:34:08.80$vck44/vblo=6,719.99 2006.257.20:34:08.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.20:34:08.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.20:34:08.80#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:08.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:08.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:08.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:08.80#ibcon#enter wrdev, iclass 28, count 0 2006.257.20:34:08.80#ibcon#first serial, iclass 28, count 0 2006.257.20:34:08.80#ibcon#enter sib2, iclass 28, count 0 2006.257.20:34:08.80#ibcon#flushed, iclass 28, count 0 2006.257.20:34:08.80#ibcon#about to write, iclass 28, count 0 2006.257.20:34:08.80#ibcon#wrote, iclass 28, count 0 2006.257.20:34:08.80#ibcon#about to read 3, iclass 28, count 0 2006.257.20:34:08.82#ibcon#read 3, iclass 28, count 0 2006.257.20:34:08.82#ibcon#about to read 4, iclass 28, count 0 2006.257.20:34:08.82#ibcon#read 4, iclass 28, count 0 2006.257.20:34:08.82#ibcon#about to read 5, iclass 28, count 0 2006.257.20:34:08.82#ibcon#read 5, iclass 28, count 0 2006.257.20:34:08.82#ibcon#about to read 6, iclass 28, count 0 2006.257.20:34:08.82#ibcon#read 6, iclass 28, count 0 2006.257.20:34:08.82#ibcon#end of sib2, iclass 28, count 0 2006.257.20:34:08.82#ibcon#*mode == 0, iclass 28, count 0 2006.257.20:34:08.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.20:34:08.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.20:34:08.82#ibcon#*before write, iclass 28, count 0 2006.257.20:34:08.82#ibcon#enter sib2, iclass 28, count 0 2006.257.20:34:08.82#ibcon#flushed, iclass 28, count 0 2006.257.20:34:08.82#ibcon#about to write, iclass 28, count 0 2006.257.20:34:08.82#ibcon#wrote, iclass 28, count 0 2006.257.20:34:08.82#ibcon#about to read 3, iclass 28, count 0 2006.257.20:34:08.86#ibcon#read 3, iclass 28, count 0 2006.257.20:34:08.86#ibcon#about to read 4, iclass 28, count 0 2006.257.20:34:08.86#ibcon#read 4, iclass 28, count 0 2006.257.20:34:08.86#ibcon#about to read 5, iclass 28, count 0 2006.257.20:34:08.86#ibcon#read 5, iclass 28, count 0 2006.257.20:34:08.86#ibcon#about to read 6, iclass 28, count 0 2006.257.20:34:08.86#ibcon#read 6, iclass 28, count 0 2006.257.20:34:08.86#ibcon#end of sib2, iclass 28, count 0 2006.257.20:34:08.86#ibcon#*after write, iclass 28, count 0 2006.257.20:34:08.86#ibcon#*before return 0, iclass 28, count 0 2006.257.20:34:08.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:08.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:34:08.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.20:34:08.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.20:34:08.86$vck44/vb=6,4 2006.257.20:34:08.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.20:34:08.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.20:34:08.86#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:08.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:08.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:08.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:08.92#ibcon#enter wrdev, iclass 30, count 2 2006.257.20:34:08.92#ibcon#first serial, iclass 30, count 2 2006.257.20:34:08.92#ibcon#enter sib2, iclass 30, count 2 2006.257.20:34:08.92#ibcon#flushed, iclass 30, count 2 2006.257.20:34:08.92#ibcon#about to write, iclass 30, count 2 2006.257.20:34:08.92#ibcon#wrote, iclass 30, count 2 2006.257.20:34:08.92#ibcon#about to read 3, iclass 30, count 2 2006.257.20:34:08.94#ibcon#read 3, iclass 30, count 2 2006.257.20:34:08.94#ibcon#about to read 4, iclass 30, count 2 2006.257.20:34:08.94#ibcon#read 4, iclass 30, count 2 2006.257.20:34:08.94#ibcon#about to read 5, iclass 30, count 2 2006.257.20:34:08.94#ibcon#read 5, iclass 30, count 2 2006.257.20:34:08.94#ibcon#about to read 6, iclass 30, count 2 2006.257.20:34:08.94#ibcon#read 6, iclass 30, count 2 2006.257.20:34:08.94#ibcon#end of sib2, iclass 30, count 2 2006.257.20:34:08.94#ibcon#*mode == 0, iclass 30, count 2 2006.257.20:34:08.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.20:34:08.94#ibcon#[27=AT06-04\r\n] 2006.257.20:34:08.94#ibcon#*before write, iclass 30, count 2 2006.257.20:34:08.94#ibcon#enter sib2, iclass 30, count 2 2006.257.20:34:08.94#ibcon#flushed, iclass 30, count 2 2006.257.20:34:08.94#ibcon#about to write, iclass 30, count 2 2006.257.20:34:08.94#ibcon#wrote, iclass 30, count 2 2006.257.20:34:08.94#ibcon#about to read 3, iclass 30, count 2 2006.257.20:34:08.97#ibcon#read 3, iclass 30, count 2 2006.257.20:34:08.97#ibcon#about to read 4, iclass 30, count 2 2006.257.20:34:08.97#ibcon#read 4, iclass 30, count 2 2006.257.20:34:08.97#ibcon#about to read 5, iclass 30, count 2 2006.257.20:34:08.97#ibcon#read 5, iclass 30, count 2 2006.257.20:34:08.97#ibcon#about to read 6, iclass 30, count 2 2006.257.20:34:08.97#ibcon#read 6, iclass 30, count 2 2006.257.20:34:08.97#ibcon#end of sib2, iclass 30, count 2 2006.257.20:34:08.97#ibcon#*after write, iclass 30, count 2 2006.257.20:34:08.97#ibcon#*before return 0, iclass 30, count 2 2006.257.20:34:08.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:08.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:34:08.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.20:34:08.97#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:08.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:09.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:09.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:09.09#ibcon#enter wrdev, iclass 30, count 0 2006.257.20:34:09.09#ibcon#first serial, iclass 30, count 0 2006.257.20:34:09.09#ibcon#enter sib2, iclass 30, count 0 2006.257.20:34:09.09#ibcon#flushed, iclass 30, count 0 2006.257.20:34:09.09#ibcon#about to write, iclass 30, count 0 2006.257.20:34:09.09#ibcon#wrote, iclass 30, count 0 2006.257.20:34:09.09#ibcon#about to read 3, iclass 30, count 0 2006.257.20:34:09.11#ibcon#read 3, iclass 30, count 0 2006.257.20:34:09.11#ibcon#about to read 4, iclass 30, count 0 2006.257.20:34:09.11#ibcon#read 4, iclass 30, count 0 2006.257.20:34:09.11#ibcon#about to read 5, iclass 30, count 0 2006.257.20:34:09.11#ibcon#read 5, iclass 30, count 0 2006.257.20:34:09.11#ibcon#about to read 6, iclass 30, count 0 2006.257.20:34:09.11#ibcon#read 6, iclass 30, count 0 2006.257.20:34:09.11#ibcon#end of sib2, iclass 30, count 0 2006.257.20:34:09.11#ibcon#*mode == 0, iclass 30, count 0 2006.257.20:34:09.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.20:34:09.11#ibcon#[27=USB\r\n] 2006.257.20:34:09.11#ibcon#*before write, iclass 30, count 0 2006.257.20:34:09.11#ibcon#enter sib2, iclass 30, count 0 2006.257.20:34:09.11#ibcon#flushed, iclass 30, count 0 2006.257.20:34:09.11#ibcon#about to write, iclass 30, count 0 2006.257.20:34:09.11#ibcon#wrote, iclass 30, count 0 2006.257.20:34:09.11#ibcon#about to read 3, iclass 30, count 0 2006.257.20:34:09.14#ibcon#read 3, iclass 30, count 0 2006.257.20:34:09.14#ibcon#about to read 4, iclass 30, count 0 2006.257.20:34:09.14#ibcon#read 4, iclass 30, count 0 2006.257.20:34:09.14#ibcon#about to read 5, iclass 30, count 0 2006.257.20:34:09.14#ibcon#read 5, iclass 30, count 0 2006.257.20:34:09.14#ibcon#about to read 6, iclass 30, count 0 2006.257.20:34:09.14#ibcon#read 6, iclass 30, count 0 2006.257.20:34:09.14#ibcon#end of sib2, iclass 30, count 0 2006.257.20:34:09.14#ibcon#*after write, iclass 30, count 0 2006.257.20:34:09.14#ibcon#*before return 0, iclass 30, count 0 2006.257.20:34:09.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:09.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:34:09.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.20:34:09.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.20:34:09.14$vck44/vblo=7,734.99 2006.257.20:34:09.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.20:34:09.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.20:34:09.14#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:09.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:09.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:09.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:09.14#ibcon#enter wrdev, iclass 32, count 0 2006.257.20:34:09.14#ibcon#first serial, iclass 32, count 0 2006.257.20:34:09.14#ibcon#enter sib2, iclass 32, count 0 2006.257.20:34:09.14#ibcon#flushed, iclass 32, count 0 2006.257.20:34:09.14#ibcon#about to write, iclass 32, count 0 2006.257.20:34:09.14#ibcon#wrote, iclass 32, count 0 2006.257.20:34:09.14#ibcon#about to read 3, iclass 32, count 0 2006.257.20:34:09.16#ibcon#read 3, iclass 32, count 0 2006.257.20:34:09.16#ibcon#about to read 4, iclass 32, count 0 2006.257.20:34:09.16#ibcon#read 4, iclass 32, count 0 2006.257.20:34:09.16#ibcon#about to read 5, iclass 32, count 0 2006.257.20:34:09.16#ibcon#read 5, iclass 32, count 0 2006.257.20:34:09.16#ibcon#about to read 6, iclass 32, count 0 2006.257.20:34:09.16#ibcon#read 6, iclass 32, count 0 2006.257.20:34:09.16#ibcon#end of sib2, iclass 32, count 0 2006.257.20:34:09.16#ibcon#*mode == 0, iclass 32, count 0 2006.257.20:34:09.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.20:34:09.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.20:34:09.16#ibcon#*before write, iclass 32, count 0 2006.257.20:34:09.16#ibcon#enter sib2, iclass 32, count 0 2006.257.20:34:09.16#ibcon#flushed, iclass 32, count 0 2006.257.20:34:09.16#ibcon#about to write, iclass 32, count 0 2006.257.20:34:09.16#ibcon#wrote, iclass 32, count 0 2006.257.20:34:09.16#ibcon#about to read 3, iclass 32, count 0 2006.257.20:34:09.20#ibcon#read 3, iclass 32, count 0 2006.257.20:34:09.20#ibcon#about to read 4, iclass 32, count 0 2006.257.20:34:09.20#ibcon#read 4, iclass 32, count 0 2006.257.20:34:09.20#ibcon#about to read 5, iclass 32, count 0 2006.257.20:34:09.20#ibcon#read 5, iclass 32, count 0 2006.257.20:34:09.20#ibcon#about to read 6, iclass 32, count 0 2006.257.20:34:09.20#ibcon#read 6, iclass 32, count 0 2006.257.20:34:09.20#ibcon#end of sib2, iclass 32, count 0 2006.257.20:34:09.20#ibcon#*after write, iclass 32, count 0 2006.257.20:34:09.20#ibcon#*before return 0, iclass 32, count 0 2006.257.20:34:09.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:09.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:34:09.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.20:34:09.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.20:34:09.20$vck44/vb=7,4 2006.257.20:34:09.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.20:34:09.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.20:34:09.20#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:09.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:09.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:09.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:09.26#ibcon#enter wrdev, iclass 34, count 2 2006.257.20:34:09.26#ibcon#first serial, iclass 34, count 2 2006.257.20:34:09.26#ibcon#enter sib2, iclass 34, count 2 2006.257.20:34:09.26#ibcon#flushed, iclass 34, count 2 2006.257.20:34:09.26#ibcon#about to write, iclass 34, count 2 2006.257.20:34:09.26#ibcon#wrote, iclass 34, count 2 2006.257.20:34:09.26#ibcon#about to read 3, iclass 34, count 2 2006.257.20:34:09.28#ibcon#read 3, iclass 34, count 2 2006.257.20:34:09.28#ibcon#about to read 4, iclass 34, count 2 2006.257.20:34:09.28#ibcon#read 4, iclass 34, count 2 2006.257.20:34:09.28#ibcon#about to read 5, iclass 34, count 2 2006.257.20:34:09.28#ibcon#read 5, iclass 34, count 2 2006.257.20:34:09.28#ibcon#about to read 6, iclass 34, count 2 2006.257.20:34:09.28#ibcon#read 6, iclass 34, count 2 2006.257.20:34:09.28#ibcon#end of sib2, iclass 34, count 2 2006.257.20:34:09.28#ibcon#*mode == 0, iclass 34, count 2 2006.257.20:34:09.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.20:34:09.28#ibcon#[27=AT07-04\r\n] 2006.257.20:34:09.28#ibcon#*before write, iclass 34, count 2 2006.257.20:34:09.28#ibcon#enter sib2, iclass 34, count 2 2006.257.20:34:09.28#ibcon#flushed, iclass 34, count 2 2006.257.20:34:09.28#ibcon#about to write, iclass 34, count 2 2006.257.20:34:09.28#ibcon#wrote, iclass 34, count 2 2006.257.20:34:09.28#ibcon#about to read 3, iclass 34, count 2 2006.257.20:34:09.31#ibcon#read 3, iclass 34, count 2 2006.257.20:34:09.31#ibcon#about to read 4, iclass 34, count 2 2006.257.20:34:09.31#ibcon#read 4, iclass 34, count 2 2006.257.20:34:09.31#ibcon#about to read 5, iclass 34, count 2 2006.257.20:34:09.31#ibcon#read 5, iclass 34, count 2 2006.257.20:34:09.31#ibcon#about to read 6, iclass 34, count 2 2006.257.20:34:09.31#ibcon#read 6, iclass 34, count 2 2006.257.20:34:09.31#ibcon#end of sib2, iclass 34, count 2 2006.257.20:34:09.31#ibcon#*after write, iclass 34, count 2 2006.257.20:34:09.31#ibcon#*before return 0, iclass 34, count 2 2006.257.20:34:09.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:09.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:34:09.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.20:34:09.31#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:09.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:09.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:09.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:09.43#ibcon#enter wrdev, iclass 34, count 0 2006.257.20:34:09.43#ibcon#first serial, iclass 34, count 0 2006.257.20:34:09.43#ibcon#enter sib2, iclass 34, count 0 2006.257.20:34:09.43#ibcon#flushed, iclass 34, count 0 2006.257.20:34:09.43#ibcon#about to write, iclass 34, count 0 2006.257.20:34:09.43#ibcon#wrote, iclass 34, count 0 2006.257.20:34:09.43#ibcon#about to read 3, iclass 34, count 0 2006.257.20:34:09.45#ibcon#read 3, iclass 34, count 0 2006.257.20:34:09.45#ibcon#about to read 4, iclass 34, count 0 2006.257.20:34:09.45#ibcon#read 4, iclass 34, count 0 2006.257.20:34:09.45#ibcon#about to read 5, iclass 34, count 0 2006.257.20:34:09.45#ibcon#read 5, iclass 34, count 0 2006.257.20:34:09.45#ibcon#about to read 6, iclass 34, count 0 2006.257.20:34:09.45#ibcon#read 6, iclass 34, count 0 2006.257.20:34:09.45#ibcon#end of sib2, iclass 34, count 0 2006.257.20:34:09.45#ibcon#*mode == 0, iclass 34, count 0 2006.257.20:34:09.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.20:34:09.45#ibcon#[27=USB\r\n] 2006.257.20:34:09.45#ibcon#*before write, iclass 34, count 0 2006.257.20:34:09.45#ibcon#enter sib2, iclass 34, count 0 2006.257.20:34:09.45#ibcon#flushed, iclass 34, count 0 2006.257.20:34:09.45#ibcon#about to write, iclass 34, count 0 2006.257.20:34:09.45#ibcon#wrote, iclass 34, count 0 2006.257.20:34:09.45#ibcon#about to read 3, iclass 34, count 0 2006.257.20:34:09.48#ibcon#read 3, iclass 34, count 0 2006.257.20:34:09.48#ibcon#about to read 4, iclass 34, count 0 2006.257.20:34:09.48#ibcon#read 4, iclass 34, count 0 2006.257.20:34:09.48#ibcon#about to read 5, iclass 34, count 0 2006.257.20:34:09.48#ibcon#read 5, iclass 34, count 0 2006.257.20:34:09.48#ibcon#about to read 6, iclass 34, count 0 2006.257.20:34:09.48#ibcon#read 6, iclass 34, count 0 2006.257.20:34:09.48#ibcon#end of sib2, iclass 34, count 0 2006.257.20:34:09.48#ibcon#*after write, iclass 34, count 0 2006.257.20:34:09.48#ibcon#*before return 0, iclass 34, count 0 2006.257.20:34:09.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:09.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:34:09.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.20:34:09.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.20:34:09.48$vck44/vblo=8,744.99 2006.257.20:34:09.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.20:34:09.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.20:34:09.48#ibcon#ireg 17 cls_cnt 0 2006.257.20:34:09.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:09.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:09.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:09.48#ibcon#enter wrdev, iclass 36, count 0 2006.257.20:34:09.48#ibcon#first serial, iclass 36, count 0 2006.257.20:34:09.48#ibcon#enter sib2, iclass 36, count 0 2006.257.20:34:09.48#ibcon#flushed, iclass 36, count 0 2006.257.20:34:09.48#ibcon#about to write, iclass 36, count 0 2006.257.20:34:09.48#ibcon#wrote, iclass 36, count 0 2006.257.20:34:09.48#ibcon#about to read 3, iclass 36, count 0 2006.257.20:34:09.50#ibcon#read 3, iclass 36, count 0 2006.257.20:34:09.50#ibcon#about to read 4, iclass 36, count 0 2006.257.20:34:09.50#ibcon#read 4, iclass 36, count 0 2006.257.20:34:09.50#ibcon#about to read 5, iclass 36, count 0 2006.257.20:34:09.50#ibcon#read 5, iclass 36, count 0 2006.257.20:34:09.50#ibcon#about to read 6, iclass 36, count 0 2006.257.20:34:09.50#ibcon#read 6, iclass 36, count 0 2006.257.20:34:09.50#ibcon#end of sib2, iclass 36, count 0 2006.257.20:34:09.50#ibcon#*mode == 0, iclass 36, count 0 2006.257.20:34:09.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.20:34:09.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.20:34:09.50#ibcon#*before write, iclass 36, count 0 2006.257.20:34:09.50#ibcon#enter sib2, iclass 36, count 0 2006.257.20:34:09.50#ibcon#flushed, iclass 36, count 0 2006.257.20:34:09.50#ibcon#about to write, iclass 36, count 0 2006.257.20:34:09.50#ibcon#wrote, iclass 36, count 0 2006.257.20:34:09.50#ibcon#about to read 3, iclass 36, count 0 2006.257.20:34:09.54#ibcon#read 3, iclass 36, count 0 2006.257.20:34:09.54#ibcon#about to read 4, iclass 36, count 0 2006.257.20:34:09.54#ibcon#read 4, iclass 36, count 0 2006.257.20:34:09.54#ibcon#about to read 5, iclass 36, count 0 2006.257.20:34:09.54#ibcon#read 5, iclass 36, count 0 2006.257.20:34:09.54#ibcon#about to read 6, iclass 36, count 0 2006.257.20:34:09.54#ibcon#read 6, iclass 36, count 0 2006.257.20:34:09.54#ibcon#end of sib2, iclass 36, count 0 2006.257.20:34:09.54#ibcon#*after write, iclass 36, count 0 2006.257.20:34:09.54#ibcon#*before return 0, iclass 36, count 0 2006.257.20:34:09.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:09.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:34:09.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.20:34:09.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.20:34:09.54$vck44/vb=8,4 2006.257.20:34:09.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.20:34:09.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.20:34:09.54#ibcon#ireg 11 cls_cnt 2 2006.257.20:34:09.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:09.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:09.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:09.60#ibcon#enter wrdev, iclass 38, count 2 2006.257.20:34:09.60#ibcon#first serial, iclass 38, count 2 2006.257.20:34:09.60#ibcon#enter sib2, iclass 38, count 2 2006.257.20:34:09.60#ibcon#flushed, iclass 38, count 2 2006.257.20:34:09.60#ibcon#about to write, iclass 38, count 2 2006.257.20:34:09.60#ibcon#wrote, iclass 38, count 2 2006.257.20:34:09.60#ibcon#about to read 3, iclass 38, count 2 2006.257.20:34:09.62#ibcon#read 3, iclass 38, count 2 2006.257.20:34:09.62#ibcon#about to read 4, iclass 38, count 2 2006.257.20:34:09.62#ibcon#read 4, iclass 38, count 2 2006.257.20:34:09.62#ibcon#about to read 5, iclass 38, count 2 2006.257.20:34:09.62#ibcon#read 5, iclass 38, count 2 2006.257.20:34:09.62#ibcon#about to read 6, iclass 38, count 2 2006.257.20:34:09.62#ibcon#read 6, iclass 38, count 2 2006.257.20:34:09.62#ibcon#end of sib2, iclass 38, count 2 2006.257.20:34:09.62#ibcon#*mode == 0, iclass 38, count 2 2006.257.20:34:09.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.20:34:09.62#ibcon#[27=AT08-04\r\n] 2006.257.20:34:09.62#ibcon#*before write, iclass 38, count 2 2006.257.20:34:09.62#ibcon#enter sib2, iclass 38, count 2 2006.257.20:34:09.62#ibcon#flushed, iclass 38, count 2 2006.257.20:34:09.62#ibcon#about to write, iclass 38, count 2 2006.257.20:34:09.62#ibcon#wrote, iclass 38, count 2 2006.257.20:34:09.62#ibcon#about to read 3, iclass 38, count 2 2006.257.20:34:09.65#ibcon#read 3, iclass 38, count 2 2006.257.20:34:09.65#ibcon#about to read 4, iclass 38, count 2 2006.257.20:34:09.65#ibcon#read 4, iclass 38, count 2 2006.257.20:34:09.65#ibcon#about to read 5, iclass 38, count 2 2006.257.20:34:09.65#ibcon#read 5, iclass 38, count 2 2006.257.20:34:09.65#ibcon#about to read 6, iclass 38, count 2 2006.257.20:34:09.65#ibcon#read 6, iclass 38, count 2 2006.257.20:34:09.65#ibcon#end of sib2, iclass 38, count 2 2006.257.20:34:09.65#ibcon#*after write, iclass 38, count 2 2006.257.20:34:09.65#ibcon#*before return 0, iclass 38, count 2 2006.257.20:34:09.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:09.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:34:09.65#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.20:34:09.65#ibcon#ireg 7 cls_cnt 0 2006.257.20:34:09.65#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:09.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:09.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:09.77#ibcon#enter wrdev, iclass 38, count 0 2006.257.20:34:09.77#ibcon#first serial, iclass 38, count 0 2006.257.20:34:09.77#ibcon#enter sib2, iclass 38, count 0 2006.257.20:34:09.77#ibcon#flushed, iclass 38, count 0 2006.257.20:34:09.77#ibcon#about to write, iclass 38, count 0 2006.257.20:34:09.77#ibcon#wrote, iclass 38, count 0 2006.257.20:34:09.77#ibcon#about to read 3, iclass 38, count 0 2006.257.20:34:09.79#ibcon#read 3, iclass 38, count 0 2006.257.20:34:09.79#ibcon#about to read 4, iclass 38, count 0 2006.257.20:34:09.79#ibcon#read 4, iclass 38, count 0 2006.257.20:34:09.79#ibcon#about to read 5, iclass 38, count 0 2006.257.20:34:09.79#ibcon#read 5, iclass 38, count 0 2006.257.20:34:09.79#ibcon#about to read 6, iclass 38, count 0 2006.257.20:34:09.79#ibcon#read 6, iclass 38, count 0 2006.257.20:34:09.79#ibcon#end of sib2, iclass 38, count 0 2006.257.20:34:09.79#ibcon#*mode == 0, iclass 38, count 0 2006.257.20:34:09.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.20:34:09.79#ibcon#[27=USB\r\n] 2006.257.20:34:09.79#ibcon#*before write, iclass 38, count 0 2006.257.20:34:09.79#ibcon#enter sib2, iclass 38, count 0 2006.257.20:34:09.79#ibcon#flushed, iclass 38, count 0 2006.257.20:34:09.79#ibcon#about to write, iclass 38, count 0 2006.257.20:34:09.79#ibcon#wrote, iclass 38, count 0 2006.257.20:34:09.79#ibcon#about to read 3, iclass 38, count 0 2006.257.20:34:09.82#ibcon#read 3, iclass 38, count 0 2006.257.20:34:09.82#ibcon#about to read 4, iclass 38, count 0 2006.257.20:34:09.82#ibcon#read 4, iclass 38, count 0 2006.257.20:34:09.82#ibcon#about to read 5, iclass 38, count 0 2006.257.20:34:09.82#ibcon#read 5, iclass 38, count 0 2006.257.20:34:09.82#ibcon#about to read 6, iclass 38, count 0 2006.257.20:34:09.82#ibcon#read 6, iclass 38, count 0 2006.257.20:34:09.82#ibcon#end of sib2, iclass 38, count 0 2006.257.20:34:09.82#ibcon#*after write, iclass 38, count 0 2006.257.20:34:09.82#ibcon#*before return 0, iclass 38, count 0 2006.257.20:34:09.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:09.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:34:09.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.20:34:09.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.20:34:09.82$vck44/vabw=wide 2006.257.20:34:09.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.20:34:09.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.20:34:09.82#ibcon#ireg 8 cls_cnt 0 2006.257.20:34:09.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:09.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:09.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:09.82#ibcon#enter wrdev, iclass 40, count 0 2006.257.20:34:09.82#ibcon#first serial, iclass 40, count 0 2006.257.20:34:09.82#ibcon#enter sib2, iclass 40, count 0 2006.257.20:34:09.82#ibcon#flushed, iclass 40, count 0 2006.257.20:34:09.82#ibcon#about to write, iclass 40, count 0 2006.257.20:34:09.82#ibcon#wrote, iclass 40, count 0 2006.257.20:34:09.82#ibcon#about to read 3, iclass 40, count 0 2006.257.20:34:09.84#ibcon#read 3, iclass 40, count 0 2006.257.20:34:09.84#ibcon#about to read 4, iclass 40, count 0 2006.257.20:34:09.84#ibcon#read 4, iclass 40, count 0 2006.257.20:34:09.84#ibcon#about to read 5, iclass 40, count 0 2006.257.20:34:09.84#ibcon#read 5, iclass 40, count 0 2006.257.20:34:09.84#ibcon#about to read 6, iclass 40, count 0 2006.257.20:34:09.84#ibcon#read 6, iclass 40, count 0 2006.257.20:34:09.84#ibcon#end of sib2, iclass 40, count 0 2006.257.20:34:09.84#ibcon#*mode == 0, iclass 40, count 0 2006.257.20:34:09.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.20:34:09.84#ibcon#[25=BW32\r\n] 2006.257.20:34:09.84#ibcon#*before write, iclass 40, count 0 2006.257.20:34:09.84#ibcon#enter sib2, iclass 40, count 0 2006.257.20:34:09.84#ibcon#flushed, iclass 40, count 0 2006.257.20:34:09.84#ibcon#about to write, iclass 40, count 0 2006.257.20:34:09.84#ibcon#wrote, iclass 40, count 0 2006.257.20:34:09.84#ibcon#about to read 3, iclass 40, count 0 2006.257.20:34:09.87#ibcon#read 3, iclass 40, count 0 2006.257.20:34:09.87#ibcon#about to read 4, iclass 40, count 0 2006.257.20:34:09.87#ibcon#read 4, iclass 40, count 0 2006.257.20:34:09.87#ibcon#about to read 5, iclass 40, count 0 2006.257.20:34:09.87#ibcon#read 5, iclass 40, count 0 2006.257.20:34:09.87#ibcon#about to read 6, iclass 40, count 0 2006.257.20:34:09.87#ibcon#read 6, iclass 40, count 0 2006.257.20:34:09.87#ibcon#end of sib2, iclass 40, count 0 2006.257.20:34:09.87#ibcon#*after write, iclass 40, count 0 2006.257.20:34:09.87#ibcon#*before return 0, iclass 40, count 0 2006.257.20:34:09.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:09.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:34:09.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.20:34:09.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.20:34:09.87$vck44/vbbw=wide 2006.257.20:34:09.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.20:34:09.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.20:34:09.87#ibcon#ireg 8 cls_cnt 0 2006.257.20:34:09.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:34:09.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:34:09.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:34:09.94#ibcon#enter wrdev, iclass 4, count 0 2006.257.20:34:09.94#ibcon#first serial, iclass 4, count 0 2006.257.20:34:09.94#ibcon#enter sib2, iclass 4, count 0 2006.257.20:34:09.94#ibcon#flushed, iclass 4, count 0 2006.257.20:34:09.94#ibcon#about to write, iclass 4, count 0 2006.257.20:34:09.94#ibcon#wrote, iclass 4, count 0 2006.257.20:34:09.94#ibcon#about to read 3, iclass 4, count 0 2006.257.20:34:09.96#ibcon#read 3, iclass 4, count 0 2006.257.20:34:09.96#ibcon#about to read 4, iclass 4, count 0 2006.257.20:34:09.96#ibcon#read 4, iclass 4, count 0 2006.257.20:34:09.96#ibcon#about to read 5, iclass 4, count 0 2006.257.20:34:09.96#ibcon#read 5, iclass 4, count 0 2006.257.20:34:09.96#ibcon#about to read 6, iclass 4, count 0 2006.257.20:34:09.96#ibcon#read 6, iclass 4, count 0 2006.257.20:34:09.96#ibcon#end of sib2, iclass 4, count 0 2006.257.20:34:09.96#ibcon#*mode == 0, iclass 4, count 0 2006.257.20:34:09.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.20:34:09.96#ibcon#[27=BW32\r\n] 2006.257.20:34:09.96#ibcon#*before write, iclass 4, count 0 2006.257.20:34:09.96#ibcon#enter sib2, iclass 4, count 0 2006.257.20:34:09.96#ibcon#flushed, iclass 4, count 0 2006.257.20:34:09.96#ibcon#about to write, iclass 4, count 0 2006.257.20:34:09.96#ibcon#wrote, iclass 4, count 0 2006.257.20:34:09.96#ibcon#about to read 3, iclass 4, count 0 2006.257.20:34:09.99#ibcon#read 3, iclass 4, count 0 2006.257.20:34:09.99#ibcon#about to read 4, iclass 4, count 0 2006.257.20:34:09.99#ibcon#read 4, iclass 4, count 0 2006.257.20:34:09.99#ibcon#about to read 5, iclass 4, count 0 2006.257.20:34:09.99#ibcon#read 5, iclass 4, count 0 2006.257.20:34:09.99#ibcon#about to read 6, iclass 4, count 0 2006.257.20:34:09.99#ibcon#read 6, iclass 4, count 0 2006.257.20:34:09.99#ibcon#end of sib2, iclass 4, count 0 2006.257.20:34:09.99#ibcon#*after write, iclass 4, count 0 2006.257.20:34:09.99#ibcon#*before return 0, iclass 4, count 0 2006.257.20:34:09.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:34:09.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:34:09.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.20:34:09.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.20:34:09.99$setupk4/ifdk4 2006.257.20:34:09.99$ifdk4/lo= 2006.257.20:34:09.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.20:34:09.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.20:34:09.99$ifdk4/patch= 2006.257.20:34:09.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.20:34:09.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.20:34:09.99$setupk4/!*+20s 2006.257.20:34:10.39#abcon#<5=/14 0.8 3.5 17.10 981014.9\r\n> 2006.257.20:34:10.41#abcon#{5=INTERFACE CLEAR} 2006.257.20:34:10.47#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:34:20.56#abcon#<5=/14 0.8 3.5 17.10 981014.9\r\n> 2006.257.20:34:20.58#abcon#{5=INTERFACE CLEAR} 2006.257.20:34:20.64#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:34:23.13#trakl#Source acquired 2006.257.20:34:24.13#flagr#flagr/antenna,acquired 2006.257.20:34:24.50$setupk4/"tpicd 2006.257.20:34:24.50$setupk4/echo=off 2006.257.20:34:24.50$setupk4/xlog=off 2006.257.20:34:24.50:!2006.257.20:38:02 2006.257.20:38:02.00:preob 2006.257.20:38:02.14/onsource/TRACKING 2006.257.20:38:02.14:!2006.257.20:38:12 2006.257.20:38:12.00:"tape 2006.257.20:38:12.00:"st=record 2006.257.20:38:12.00:data_valid=on 2006.257.20:38:12.00:midob 2006.257.20:38:12.14/onsource/TRACKING 2006.257.20:38:12.14/wx/17.12,1014.9,98 2006.257.20:38:12.24/cable/+6.4856E-03 2006.257.20:38:13.33/va/01,08,usb,yes,32,34 2006.257.20:38:13.33/va/02,07,usb,yes,34,35 2006.257.20:38:13.33/va/03,08,usb,yes,31,33 2006.257.20:38:13.33/va/04,07,usb,yes,35,37 2006.257.20:38:13.33/va/05,04,usb,yes,31,32 2006.257.20:38:13.33/va/06,04,usb,yes,35,34 2006.257.20:38:13.33/va/07,04,usb,yes,35,36 2006.257.20:38:13.33/va/08,04,usb,yes,30,36 2006.257.20:38:13.56/valo/01,524.99,yes,locked 2006.257.20:38:13.56/valo/02,534.99,yes,locked 2006.257.20:38:13.56/valo/03,564.99,yes,locked 2006.257.20:38:13.56/valo/04,624.99,yes,locked 2006.257.20:38:13.56/valo/05,734.99,yes,locked 2006.257.20:38:13.56/valo/06,814.99,yes,locked 2006.257.20:38:13.56/valo/07,864.99,yes,locked 2006.257.20:38:13.56/valo/08,884.99,yes,locked 2006.257.20:38:14.65/vb/01,04,usb,yes,31,29 2006.257.20:38:14.65/vb/02,05,usb,yes,29,29 2006.257.20:38:14.65/vb/03,04,usb,yes,30,33 2006.257.20:38:14.65/vb/04,05,usb,yes,31,29 2006.257.20:38:14.65/vb/05,04,usb,yes,27,29 2006.257.20:38:14.65/vb/06,04,usb,yes,32,28 2006.257.20:38:14.65/vb/07,04,usb,yes,31,31 2006.257.20:38:14.65/vb/08,04,usb,yes,29,32 2006.257.20:38:14.89/vblo/01,629.99,yes,locked 2006.257.20:38:14.89/vblo/02,634.99,yes,locked 2006.257.20:38:14.89/vblo/03,649.99,yes,locked 2006.257.20:38:14.89/vblo/04,679.99,yes,locked 2006.257.20:38:14.89/vblo/05,709.99,yes,locked 2006.257.20:38:14.89/vblo/06,719.99,yes,locked 2006.257.20:38:14.89/vblo/07,734.99,yes,locked 2006.257.20:38:14.89/vblo/08,744.99,yes,locked 2006.257.20:38:15.04/vabw/8 2006.257.20:38:15.19/vbbw/8 2006.257.20:38:15.28/xfe/off,on,15.2 2006.257.20:38:15.66/ifatt/23,28,28,28 2006.257.20:38:16.07/fmout-gps/S +4.56E-07 2006.257.20:38:16.11:!2006.257.20:39:12 2006.257.20:39:12.01:data_valid=off 2006.257.20:39:12.02:"et 2006.257.20:39:12.02:!+3s 2006.257.20:39:15.03:"tape 2006.257.20:39:15.03:postob 2006.257.20:39:15.24/cable/+6.4840E-03 2006.257.20:39:15.24/wx/17.12,1014.9,98 2006.257.20:39:15.30/fmout-gps/S +4.56E-07 2006.257.20:39:15.30:scan_name=257-2041,jd0609,100 2006.257.20:39:15.30:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.257.20:39:16.14#flagr#flagr/antenna,new-source 2006.257.20:39:16.14:checkk5 2006.257.20:39:16.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.20:39:16.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.20:39:17.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.20:39:17.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.20:39:17.84/chk_obsdata//k5ts1/T2572038??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.20:39:18.16/chk_obsdata//k5ts2/T2572038??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.20:39:18.50/chk_obsdata//k5ts3/T2572038??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.20:39:18.84/chk_obsdata//k5ts4/T2572038??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.20:39:19.50/k5log//k5ts1_log_newline 2006.257.20:39:20.15/k5log//k5ts2_log_newline 2006.257.20:39:20.79/k5log//k5ts3_log_newline 2006.257.20:39:21.44/k5log//k5ts4_log_newline 2006.257.20:39:21.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.20:39:21.47:setupk4=1 2006.257.20:39:21.47$setupk4/echo=on 2006.257.20:39:21.47$setupk4/pcalon 2006.257.20:39:21.47$pcalon/"no phase cal control is implemented here 2006.257.20:39:21.47$setupk4/"tpicd=stop 2006.257.20:39:21.47$setupk4/"rec=synch_on 2006.257.20:39:21.47$setupk4/"rec_mode=128 2006.257.20:39:21.47$setupk4/!* 2006.257.20:39:21.47$setupk4/recpk4 2006.257.20:39:21.47$recpk4/recpatch= 2006.257.20:39:21.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.20:39:21.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.20:39:21.47$setupk4/vck44 2006.257.20:39:21.47$vck44/valo=1,524.99 2006.257.20:39:21.47#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.20:39:21.48#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.20:39:21.48#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:21.48#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:21.48#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:21.48#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:21.48#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:39:21.48#ibcon#first serial, iclass 27, count 0 2006.257.20:39:21.48#ibcon#enter sib2, iclass 27, count 0 2006.257.20:39:21.48#ibcon#flushed, iclass 27, count 0 2006.257.20:39:21.48#ibcon#about to write, iclass 27, count 0 2006.257.20:39:21.48#ibcon#wrote, iclass 27, count 0 2006.257.20:39:21.48#ibcon#about to read 3, iclass 27, count 0 2006.257.20:39:21.49#ibcon#read 3, iclass 27, count 0 2006.257.20:39:21.49#ibcon#about to read 4, iclass 27, count 0 2006.257.20:39:21.49#ibcon#read 4, iclass 27, count 0 2006.257.20:39:21.49#ibcon#about to read 5, iclass 27, count 0 2006.257.20:39:21.49#ibcon#read 5, iclass 27, count 0 2006.257.20:39:21.49#ibcon#about to read 6, iclass 27, count 0 2006.257.20:39:21.49#ibcon#read 6, iclass 27, count 0 2006.257.20:39:21.49#ibcon#end of sib2, iclass 27, count 0 2006.257.20:39:21.49#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:39:21.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:39:21.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.20:39:21.49#ibcon#*before write, iclass 27, count 0 2006.257.20:39:21.49#ibcon#enter sib2, iclass 27, count 0 2006.257.20:39:21.49#ibcon#flushed, iclass 27, count 0 2006.257.20:39:21.49#ibcon#about to write, iclass 27, count 0 2006.257.20:39:21.49#ibcon#wrote, iclass 27, count 0 2006.257.20:39:21.49#ibcon#about to read 3, iclass 27, count 0 2006.257.20:39:21.54#ibcon#read 3, iclass 27, count 0 2006.257.20:39:21.54#ibcon#about to read 4, iclass 27, count 0 2006.257.20:39:21.54#ibcon#read 4, iclass 27, count 0 2006.257.20:39:21.54#ibcon#about to read 5, iclass 27, count 0 2006.257.20:39:21.54#ibcon#read 5, iclass 27, count 0 2006.257.20:39:21.54#ibcon#about to read 6, iclass 27, count 0 2006.257.20:39:21.54#ibcon#read 6, iclass 27, count 0 2006.257.20:39:21.54#ibcon#end of sib2, iclass 27, count 0 2006.257.20:39:21.54#ibcon#*after write, iclass 27, count 0 2006.257.20:39:21.54#ibcon#*before return 0, iclass 27, count 0 2006.257.20:39:21.54#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:21.54#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:21.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:39:21.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:39:21.54$vck44/va=1,8 2006.257.20:39:21.54#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.20:39:21.54#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.20:39:21.54#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:21.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:21.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:21.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:21.54#ibcon#enter wrdev, iclass 29, count 2 2006.257.20:39:21.54#ibcon#first serial, iclass 29, count 2 2006.257.20:39:21.54#ibcon#enter sib2, iclass 29, count 2 2006.257.20:39:21.54#ibcon#flushed, iclass 29, count 2 2006.257.20:39:21.54#ibcon#about to write, iclass 29, count 2 2006.257.20:39:21.54#ibcon#wrote, iclass 29, count 2 2006.257.20:39:21.54#ibcon#about to read 3, iclass 29, count 2 2006.257.20:39:21.56#ibcon#read 3, iclass 29, count 2 2006.257.20:39:21.56#ibcon#about to read 4, iclass 29, count 2 2006.257.20:39:21.56#ibcon#read 4, iclass 29, count 2 2006.257.20:39:21.56#ibcon#about to read 5, iclass 29, count 2 2006.257.20:39:21.56#ibcon#read 5, iclass 29, count 2 2006.257.20:39:21.56#ibcon#about to read 6, iclass 29, count 2 2006.257.20:39:21.56#ibcon#read 6, iclass 29, count 2 2006.257.20:39:21.56#ibcon#end of sib2, iclass 29, count 2 2006.257.20:39:21.56#ibcon#*mode == 0, iclass 29, count 2 2006.257.20:39:21.56#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.20:39:21.56#ibcon#[25=AT01-08\r\n] 2006.257.20:39:21.56#ibcon#*before write, iclass 29, count 2 2006.257.20:39:21.56#ibcon#enter sib2, iclass 29, count 2 2006.257.20:39:21.56#ibcon#flushed, iclass 29, count 2 2006.257.20:39:21.56#ibcon#about to write, iclass 29, count 2 2006.257.20:39:21.56#ibcon#wrote, iclass 29, count 2 2006.257.20:39:21.56#ibcon#about to read 3, iclass 29, count 2 2006.257.20:39:21.59#ibcon#read 3, iclass 29, count 2 2006.257.20:39:21.59#ibcon#about to read 4, iclass 29, count 2 2006.257.20:39:21.59#ibcon#read 4, iclass 29, count 2 2006.257.20:39:21.59#ibcon#about to read 5, iclass 29, count 2 2006.257.20:39:21.59#ibcon#read 5, iclass 29, count 2 2006.257.20:39:21.59#ibcon#about to read 6, iclass 29, count 2 2006.257.20:39:21.59#ibcon#read 6, iclass 29, count 2 2006.257.20:39:21.59#ibcon#end of sib2, iclass 29, count 2 2006.257.20:39:21.59#ibcon#*after write, iclass 29, count 2 2006.257.20:39:21.59#ibcon#*before return 0, iclass 29, count 2 2006.257.20:39:21.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:21.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:21.59#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.20:39:21.59#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:21.59#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:21.71#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:21.71#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:21.71#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:39:21.71#ibcon#first serial, iclass 29, count 0 2006.257.20:39:21.71#ibcon#enter sib2, iclass 29, count 0 2006.257.20:39:21.71#ibcon#flushed, iclass 29, count 0 2006.257.20:39:21.71#ibcon#about to write, iclass 29, count 0 2006.257.20:39:21.71#ibcon#wrote, iclass 29, count 0 2006.257.20:39:21.71#ibcon#about to read 3, iclass 29, count 0 2006.257.20:39:21.73#ibcon#read 3, iclass 29, count 0 2006.257.20:39:21.73#ibcon#about to read 4, iclass 29, count 0 2006.257.20:39:21.73#ibcon#read 4, iclass 29, count 0 2006.257.20:39:21.73#ibcon#about to read 5, iclass 29, count 0 2006.257.20:39:21.73#ibcon#read 5, iclass 29, count 0 2006.257.20:39:21.73#ibcon#about to read 6, iclass 29, count 0 2006.257.20:39:21.73#ibcon#read 6, iclass 29, count 0 2006.257.20:39:21.73#ibcon#end of sib2, iclass 29, count 0 2006.257.20:39:21.73#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:39:21.73#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:39:21.73#ibcon#[25=USB\r\n] 2006.257.20:39:21.73#ibcon#*before write, iclass 29, count 0 2006.257.20:39:21.73#ibcon#enter sib2, iclass 29, count 0 2006.257.20:39:21.73#ibcon#flushed, iclass 29, count 0 2006.257.20:39:21.73#ibcon#about to write, iclass 29, count 0 2006.257.20:39:21.73#ibcon#wrote, iclass 29, count 0 2006.257.20:39:21.73#ibcon#about to read 3, iclass 29, count 0 2006.257.20:39:21.76#ibcon#read 3, iclass 29, count 0 2006.257.20:39:21.76#ibcon#about to read 4, iclass 29, count 0 2006.257.20:39:21.76#ibcon#read 4, iclass 29, count 0 2006.257.20:39:21.76#ibcon#about to read 5, iclass 29, count 0 2006.257.20:39:21.76#ibcon#read 5, iclass 29, count 0 2006.257.20:39:21.76#ibcon#about to read 6, iclass 29, count 0 2006.257.20:39:21.76#ibcon#read 6, iclass 29, count 0 2006.257.20:39:21.76#ibcon#end of sib2, iclass 29, count 0 2006.257.20:39:21.76#ibcon#*after write, iclass 29, count 0 2006.257.20:39:21.76#ibcon#*before return 0, iclass 29, count 0 2006.257.20:39:21.76#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:21.76#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:21.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:39:21.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:39:21.76$vck44/valo=2,534.99 2006.257.20:39:21.76#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.20:39:21.76#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.20:39:21.76#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:21.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:21.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:21.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:21.76#ibcon#enter wrdev, iclass 31, count 0 2006.257.20:39:21.76#ibcon#first serial, iclass 31, count 0 2006.257.20:39:21.76#ibcon#enter sib2, iclass 31, count 0 2006.257.20:39:21.76#ibcon#flushed, iclass 31, count 0 2006.257.20:39:21.76#ibcon#about to write, iclass 31, count 0 2006.257.20:39:21.76#ibcon#wrote, iclass 31, count 0 2006.257.20:39:21.76#ibcon#about to read 3, iclass 31, count 0 2006.257.20:39:21.78#ibcon#read 3, iclass 31, count 0 2006.257.20:39:21.78#ibcon#about to read 4, iclass 31, count 0 2006.257.20:39:21.78#ibcon#read 4, iclass 31, count 0 2006.257.20:39:21.78#ibcon#about to read 5, iclass 31, count 0 2006.257.20:39:21.78#ibcon#read 5, iclass 31, count 0 2006.257.20:39:21.78#ibcon#about to read 6, iclass 31, count 0 2006.257.20:39:21.78#ibcon#read 6, iclass 31, count 0 2006.257.20:39:21.78#ibcon#end of sib2, iclass 31, count 0 2006.257.20:39:21.78#ibcon#*mode == 0, iclass 31, count 0 2006.257.20:39:21.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.20:39:21.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.20:39:21.78#ibcon#*before write, iclass 31, count 0 2006.257.20:39:21.78#ibcon#enter sib2, iclass 31, count 0 2006.257.20:39:21.78#ibcon#flushed, iclass 31, count 0 2006.257.20:39:21.78#ibcon#about to write, iclass 31, count 0 2006.257.20:39:21.78#ibcon#wrote, iclass 31, count 0 2006.257.20:39:21.78#ibcon#about to read 3, iclass 31, count 0 2006.257.20:39:21.82#ibcon#read 3, iclass 31, count 0 2006.257.20:39:21.82#ibcon#about to read 4, iclass 31, count 0 2006.257.20:39:21.82#ibcon#read 4, iclass 31, count 0 2006.257.20:39:21.82#ibcon#about to read 5, iclass 31, count 0 2006.257.20:39:21.82#ibcon#read 5, iclass 31, count 0 2006.257.20:39:21.82#ibcon#about to read 6, iclass 31, count 0 2006.257.20:39:21.82#ibcon#read 6, iclass 31, count 0 2006.257.20:39:21.82#ibcon#end of sib2, iclass 31, count 0 2006.257.20:39:21.82#ibcon#*after write, iclass 31, count 0 2006.257.20:39:21.82#ibcon#*before return 0, iclass 31, count 0 2006.257.20:39:21.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:21.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:21.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.20:39:21.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.20:39:21.82$vck44/va=2,7 2006.257.20:39:21.82#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.20:39:21.82#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.20:39:21.82#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:21.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:21.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:21.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:21.88#ibcon#enter wrdev, iclass 33, count 2 2006.257.20:39:21.88#ibcon#first serial, iclass 33, count 2 2006.257.20:39:21.88#ibcon#enter sib2, iclass 33, count 2 2006.257.20:39:21.88#ibcon#flushed, iclass 33, count 2 2006.257.20:39:21.88#ibcon#about to write, iclass 33, count 2 2006.257.20:39:21.88#ibcon#wrote, iclass 33, count 2 2006.257.20:39:21.88#ibcon#about to read 3, iclass 33, count 2 2006.257.20:39:21.90#ibcon#read 3, iclass 33, count 2 2006.257.20:39:21.90#ibcon#about to read 4, iclass 33, count 2 2006.257.20:39:21.90#ibcon#read 4, iclass 33, count 2 2006.257.20:39:21.90#ibcon#about to read 5, iclass 33, count 2 2006.257.20:39:21.90#ibcon#read 5, iclass 33, count 2 2006.257.20:39:21.90#ibcon#about to read 6, iclass 33, count 2 2006.257.20:39:21.90#ibcon#read 6, iclass 33, count 2 2006.257.20:39:21.90#ibcon#end of sib2, iclass 33, count 2 2006.257.20:39:21.90#ibcon#*mode == 0, iclass 33, count 2 2006.257.20:39:21.90#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.20:39:21.90#ibcon#[25=AT02-07\r\n] 2006.257.20:39:21.90#ibcon#*before write, iclass 33, count 2 2006.257.20:39:21.90#ibcon#enter sib2, iclass 33, count 2 2006.257.20:39:21.90#ibcon#flushed, iclass 33, count 2 2006.257.20:39:21.90#ibcon#about to write, iclass 33, count 2 2006.257.20:39:21.90#ibcon#wrote, iclass 33, count 2 2006.257.20:39:21.90#ibcon#about to read 3, iclass 33, count 2 2006.257.20:39:21.93#ibcon#read 3, iclass 33, count 2 2006.257.20:39:21.93#ibcon#about to read 4, iclass 33, count 2 2006.257.20:39:21.93#ibcon#read 4, iclass 33, count 2 2006.257.20:39:21.93#ibcon#about to read 5, iclass 33, count 2 2006.257.20:39:21.93#ibcon#read 5, iclass 33, count 2 2006.257.20:39:21.93#ibcon#about to read 6, iclass 33, count 2 2006.257.20:39:21.93#ibcon#read 6, iclass 33, count 2 2006.257.20:39:21.93#ibcon#end of sib2, iclass 33, count 2 2006.257.20:39:21.93#ibcon#*after write, iclass 33, count 2 2006.257.20:39:21.93#ibcon#*before return 0, iclass 33, count 2 2006.257.20:39:21.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:21.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:21.93#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.20:39:21.93#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:21.93#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:22.05#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:22.05#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:22.05#ibcon#enter wrdev, iclass 33, count 0 2006.257.20:39:22.05#ibcon#first serial, iclass 33, count 0 2006.257.20:39:22.05#ibcon#enter sib2, iclass 33, count 0 2006.257.20:39:22.05#ibcon#flushed, iclass 33, count 0 2006.257.20:39:22.05#ibcon#about to write, iclass 33, count 0 2006.257.20:39:22.05#ibcon#wrote, iclass 33, count 0 2006.257.20:39:22.05#ibcon#about to read 3, iclass 33, count 0 2006.257.20:39:22.07#ibcon#read 3, iclass 33, count 0 2006.257.20:39:22.07#ibcon#about to read 4, iclass 33, count 0 2006.257.20:39:22.07#ibcon#read 4, iclass 33, count 0 2006.257.20:39:22.07#ibcon#about to read 5, iclass 33, count 0 2006.257.20:39:22.07#ibcon#read 5, iclass 33, count 0 2006.257.20:39:22.07#ibcon#about to read 6, iclass 33, count 0 2006.257.20:39:22.07#ibcon#read 6, iclass 33, count 0 2006.257.20:39:22.07#ibcon#end of sib2, iclass 33, count 0 2006.257.20:39:22.07#ibcon#*mode == 0, iclass 33, count 0 2006.257.20:39:22.07#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.20:39:22.07#ibcon#[25=USB\r\n] 2006.257.20:39:22.07#ibcon#*before write, iclass 33, count 0 2006.257.20:39:22.07#ibcon#enter sib2, iclass 33, count 0 2006.257.20:39:22.07#ibcon#flushed, iclass 33, count 0 2006.257.20:39:22.07#ibcon#about to write, iclass 33, count 0 2006.257.20:39:22.07#ibcon#wrote, iclass 33, count 0 2006.257.20:39:22.07#ibcon#about to read 3, iclass 33, count 0 2006.257.20:39:22.10#ibcon#read 3, iclass 33, count 0 2006.257.20:39:22.10#ibcon#about to read 4, iclass 33, count 0 2006.257.20:39:22.10#ibcon#read 4, iclass 33, count 0 2006.257.20:39:22.10#ibcon#about to read 5, iclass 33, count 0 2006.257.20:39:22.10#ibcon#read 5, iclass 33, count 0 2006.257.20:39:22.10#ibcon#about to read 6, iclass 33, count 0 2006.257.20:39:22.10#ibcon#read 6, iclass 33, count 0 2006.257.20:39:22.10#ibcon#end of sib2, iclass 33, count 0 2006.257.20:39:22.10#ibcon#*after write, iclass 33, count 0 2006.257.20:39:22.10#ibcon#*before return 0, iclass 33, count 0 2006.257.20:39:22.10#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:22.10#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:22.10#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.20:39:22.10#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.20:39:22.10$vck44/valo=3,564.99 2006.257.20:39:22.10#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.20:39:22.10#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.20:39:22.10#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:22.10#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:22.10#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:22.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:22.10#ibcon#enter wrdev, iclass 35, count 0 2006.257.20:39:22.10#ibcon#first serial, iclass 35, count 0 2006.257.20:39:22.10#ibcon#enter sib2, iclass 35, count 0 2006.257.20:39:22.10#ibcon#flushed, iclass 35, count 0 2006.257.20:39:22.10#ibcon#about to write, iclass 35, count 0 2006.257.20:39:22.10#ibcon#wrote, iclass 35, count 0 2006.257.20:39:22.10#ibcon#about to read 3, iclass 35, count 0 2006.257.20:39:22.12#ibcon#read 3, iclass 35, count 0 2006.257.20:39:22.12#ibcon#about to read 4, iclass 35, count 0 2006.257.20:39:22.12#ibcon#read 4, iclass 35, count 0 2006.257.20:39:22.12#ibcon#about to read 5, iclass 35, count 0 2006.257.20:39:22.12#ibcon#read 5, iclass 35, count 0 2006.257.20:39:22.12#ibcon#about to read 6, iclass 35, count 0 2006.257.20:39:22.12#ibcon#read 6, iclass 35, count 0 2006.257.20:39:22.12#ibcon#end of sib2, iclass 35, count 0 2006.257.20:39:22.12#ibcon#*mode == 0, iclass 35, count 0 2006.257.20:39:22.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.20:39:22.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.20:39:22.12#ibcon#*before write, iclass 35, count 0 2006.257.20:39:22.12#ibcon#enter sib2, iclass 35, count 0 2006.257.20:39:22.12#ibcon#flushed, iclass 35, count 0 2006.257.20:39:22.12#ibcon#about to write, iclass 35, count 0 2006.257.20:39:22.12#ibcon#wrote, iclass 35, count 0 2006.257.20:39:22.12#ibcon#about to read 3, iclass 35, count 0 2006.257.20:39:22.16#ibcon#read 3, iclass 35, count 0 2006.257.20:39:22.16#ibcon#about to read 4, iclass 35, count 0 2006.257.20:39:22.16#ibcon#read 4, iclass 35, count 0 2006.257.20:39:22.16#ibcon#about to read 5, iclass 35, count 0 2006.257.20:39:22.16#ibcon#read 5, iclass 35, count 0 2006.257.20:39:22.16#ibcon#about to read 6, iclass 35, count 0 2006.257.20:39:22.16#ibcon#read 6, iclass 35, count 0 2006.257.20:39:22.16#ibcon#end of sib2, iclass 35, count 0 2006.257.20:39:22.16#ibcon#*after write, iclass 35, count 0 2006.257.20:39:22.16#ibcon#*before return 0, iclass 35, count 0 2006.257.20:39:22.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:22.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:22.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.20:39:22.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.20:39:22.16$vck44/va=3,8 2006.257.20:39:22.16#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.20:39:22.16#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.20:39:22.16#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:22.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:22.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:22.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:22.22#ibcon#enter wrdev, iclass 37, count 2 2006.257.20:39:22.22#ibcon#first serial, iclass 37, count 2 2006.257.20:39:22.22#ibcon#enter sib2, iclass 37, count 2 2006.257.20:39:22.22#ibcon#flushed, iclass 37, count 2 2006.257.20:39:22.22#ibcon#about to write, iclass 37, count 2 2006.257.20:39:22.22#ibcon#wrote, iclass 37, count 2 2006.257.20:39:22.22#ibcon#about to read 3, iclass 37, count 2 2006.257.20:39:22.24#ibcon#read 3, iclass 37, count 2 2006.257.20:39:22.24#ibcon#about to read 4, iclass 37, count 2 2006.257.20:39:22.24#ibcon#read 4, iclass 37, count 2 2006.257.20:39:22.24#ibcon#about to read 5, iclass 37, count 2 2006.257.20:39:22.24#ibcon#read 5, iclass 37, count 2 2006.257.20:39:22.24#ibcon#about to read 6, iclass 37, count 2 2006.257.20:39:22.24#ibcon#read 6, iclass 37, count 2 2006.257.20:39:22.24#ibcon#end of sib2, iclass 37, count 2 2006.257.20:39:22.24#ibcon#*mode == 0, iclass 37, count 2 2006.257.20:39:22.24#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.20:39:22.24#ibcon#[25=AT03-08\r\n] 2006.257.20:39:22.24#ibcon#*before write, iclass 37, count 2 2006.257.20:39:22.24#ibcon#enter sib2, iclass 37, count 2 2006.257.20:39:22.24#ibcon#flushed, iclass 37, count 2 2006.257.20:39:22.24#ibcon#about to write, iclass 37, count 2 2006.257.20:39:22.24#ibcon#wrote, iclass 37, count 2 2006.257.20:39:22.24#ibcon#about to read 3, iclass 37, count 2 2006.257.20:39:22.27#ibcon#read 3, iclass 37, count 2 2006.257.20:39:22.27#ibcon#about to read 4, iclass 37, count 2 2006.257.20:39:22.27#ibcon#read 4, iclass 37, count 2 2006.257.20:39:22.27#ibcon#about to read 5, iclass 37, count 2 2006.257.20:39:22.27#ibcon#read 5, iclass 37, count 2 2006.257.20:39:22.27#ibcon#about to read 6, iclass 37, count 2 2006.257.20:39:22.27#ibcon#read 6, iclass 37, count 2 2006.257.20:39:22.27#ibcon#end of sib2, iclass 37, count 2 2006.257.20:39:22.27#ibcon#*after write, iclass 37, count 2 2006.257.20:39:22.27#ibcon#*before return 0, iclass 37, count 2 2006.257.20:39:22.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:22.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:22.27#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.20:39:22.27#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:22.27#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:22.39#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:22.39#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:22.39#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:39:22.39#ibcon#first serial, iclass 37, count 0 2006.257.20:39:22.39#ibcon#enter sib2, iclass 37, count 0 2006.257.20:39:22.39#ibcon#flushed, iclass 37, count 0 2006.257.20:39:22.39#ibcon#about to write, iclass 37, count 0 2006.257.20:39:22.39#ibcon#wrote, iclass 37, count 0 2006.257.20:39:22.39#ibcon#about to read 3, iclass 37, count 0 2006.257.20:39:22.41#ibcon#read 3, iclass 37, count 0 2006.257.20:39:22.41#ibcon#about to read 4, iclass 37, count 0 2006.257.20:39:22.41#ibcon#read 4, iclass 37, count 0 2006.257.20:39:22.41#ibcon#about to read 5, iclass 37, count 0 2006.257.20:39:22.41#ibcon#read 5, iclass 37, count 0 2006.257.20:39:22.41#ibcon#about to read 6, iclass 37, count 0 2006.257.20:39:22.41#ibcon#read 6, iclass 37, count 0 2006.257.20:39:22.41#ibcon#end of sib2, iclass 37, count 0 2006.257.20:39:22.41#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:39:22.41#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:39:22.41#ibcon#[25=USB\r\n] 2006.257.20:39:22.41#ibcon#*before write, iclass 37, count 0 2006.257.20:39:22.41#ibcon#enter sib2, iclass 37, count 0 2006.257.20:39:22.41#ibcon#flushed, iclass 37, count 0 2006.257.20:39:22.41#ibcon#about to write, iclass 37, count 0 2006.257.20:39:22.41#ibcon#wrote, iclass 37, count 0 2006.257.20:39:22.41#ibcon#about to read 3, iclass 37, count 0 2006.257.20:39:22.44#ibcon#read 3, iclass 37, count 0 2006.257.20:39:22.44#ibcon#about to read 4, iclass 37, count 0 2006.257.20:39:22.44#ibcon#read 4, iclass 37, count 0 2006.257.20:39:22.44#ibcon#about to read 5, iclass 37, count 0 2006.257.20:39:22.44#ibcon#read 5, iclass 37, count 0 2006.257.20:39:22.44#ibcon#about to read 6, iclass 37, count 0 2006.257.20:39:22.44#ibcon#read 6, iclass 37, count 0 2006.257.20:39:22.44#ibcon#end of sib2, iclass 37, count 0 2006.257.20:39:22.44#ibcon#*after write, iclass 37, count 0 2006.257.20:39:22.44#ibcon#*before return 0, iclass 37, count 0 2006.257.20:39:22.44#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:22.44#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:22.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:39:22.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:39:22.44$vck44/valo=4,624.99 2006.257.20:39:22.44#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.20:39:22.44#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.20:39:22.44#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:22.44#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:22.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:22.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:22.44#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:39:22.44#ibcon#first serial, iclass 39, count 0 2006.257.20:39:22.44#ibcon#enter sib2, iclass 39, count 0 2006.257.20:39:22.44#ibcon#flushed, iclass 39, count 0 2006.257.20:39:22.44#ibcon#about to write, iclass 39, count 0 2006.257.20:39:22.44#ibcon#wrote, iclass 39, count 0 2006.257.20:39:22.44#ibcon#about to read 3, iclass 39, count 0 2006.257.20:39:22.46#ibcon#read 3, iclass 39, count 0 2006.257.20:39:22.46#ibcon#about to read 4, iclass 39, count 0 2006.257.20:39:22.46#ibcon#read 4, iclass 39, count 0 2006.257.20:39:22.46#ibcon#about to read 5, iclass 39, count 0 2006.257.20:39:22.46#ibcon#read 5, iclass 39, count 0 2006.257.20:39:22.46#ibcon#about to read 6, iclass 39, count 0 2006.257.20:39:22.46#ibcon#read 6, iclass 39, count 0 2006.257.20:39:22.46#ibcon#end of sib2, iclass 39, count 0 2006.257.20:39:22.46#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:39:22.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:39:22.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.20:39:22.46#ibcon#*before write, iclass 39, count 0 2006.257.20:39:22.46#ibcon#enter sib2, iclass 39, count 0 2006.257.20:39:22.46#ibcon#flushed, iclass 39, count 0 2006.257.20:39:22.46#ibcon#about to write, iclass 39, count 0 2006.257.20:39:22.46#ibcon#wrote, iclass 39, count 0 2006.257.20:39:22.46#ibcon#about to read 3, iclass 39, count 0 2006.257.20:39:22.50#ibcon#read 3, iclass 39, count 0 2006.257.20:39:22.50#ibcon#about to read 4, iclass 39, count 0 2006.257.20:39:22.50#ibcon#read 4, iclass 39, count 0 2006.257.20:39:22.50#ibcon#about to read 5, iclass 39, count 0 2006.257.20:39:22.50#ibcon#read 5, iclass 39, count 0 2006.257.20:39:22.50#ibcon#about to read 6, iclass 39, count 0 2006.257.20:39:22.50#ibcon#read 6, iclass 39, count 0 2006.257.20:39:22.50#ibcon#end of sib2, iclass 39, count 0 2006.257.20:39:22.50#ibcon#*after write, iclass 39, count 0 2006.257.20:39:22.50#ibcon#*before return 0, iclass 39, count 0 2006.257.20:39:22.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:22.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:22.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:39:22.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:39:22.50$vck44/va=4,7 2006.257.20:39:22.50#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.20:39:22.50#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.20:39:22.50#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:22.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:22.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:22.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:22.56#ibcon#enter wrdev, iclass 3, count 2 2006.257.20:39:22.56#ibcon#first serial, iclass 3, count 2 2006.257.20:39:22.56#ibcon#enter sib2, iclass 3, count 2 2006.257.20:39:22.56#ibcon#flushed, iclass 3, count 2 2006.257.20:39:22.56#ibcon#about to write, iclass 3, count 2 2006.257.20:39:22.56#ibcon#wrote, iclass 3, count 2 2006.257.20:39:22.56#ibcon#about to read 3, iclass 3, count 2 2006.257.20:39:22.58#ibcon#read 3, iclass 3, count 2 2006.257.20:39:22.58#ibcon#about to read 4, iclass 3, count 2 2006.257.20:39:22.58#ibcon#read 4, iclass 3, count 2 2006.257.20:39:22.58#ibcon#about to read 5, iclass 3, count 2 2006.257.20:39:22.58#ibcon#read 5, iclass 3, count 2 2006.257.20:39:22.58#ibcon#about to read 6, iclass 3, count 2 2006.257.20:39:22.58#ibcon#read 6, iclass 3, count 2 2006.257.20:39:22.58#ibcon#end of sib2, iclass 3, count 2 2006.257.20:39:22.58#ibcon#*mode == 0, iclass 3, count 2 2006.257.20:39:22.58#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.20:39:22.58#ibcon#[25=AT04-07\r\n] 2006.257.20:39:22.58#ibcon#*before write, iclass 3, count 2 2006.257.20:39:22.58#ibcon#enter sib2, iclass 3, count 2 2006.257.20:39:22.58#ibcon#flushed, iclass 3, count 2 2006.257.20:39:22.58#ibcon#about to write, iclass 3, count 2 2006.257.20:39:22.58#ibcon#wrote, iclass 3, count 2 2006.257.20:39:22.58#ibcon#about to read 3, iclass 3, count 2 2006.257.20:39:22.61#ibcon#read 3, iclass 3, count 2 2006.257.20:39:22.61#ibcon#about to read 4, iclass 3, count 2 2006.257.20:39:22.61#ibcon#read 4, iclass 3, count 2 2006.257.20:39:22.61#ibcon#about to read 5, iclass 3, count 2 2006.257.20:39:22.61#ibcon#read 5, iclass 3, count 2 2006.257.20:39:22.61#ibcon#about to read 6, iclass 3, count 2 2006.257.20:39:22.61#ibcon#read 6, iclass 3, count 2 2006.257.20:39:22.61#ibcon#end of sib2, iclass 3, count 2 2006.257.20:39:22.61#ibcon#*after write, iclass 3, count 2 2006.257.20:39:22.61#ibcon#*before return 0, iclass 3, count 2 2006.257.20:39:22.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:22.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:22.61#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.20:39:22.61#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:22.61#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:22.73#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:22.73#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:22.73#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:39:22.73#ibcon#first serial, iclass 3, count 0 2006.257.20:39:22.73#ibcon#enter sib2, iclass 3, count 0 2006.257.20:39:22.73#ibcon#flushed, iclass 3, count 0 2006.257.20:39:22.73#ibcon#about to write, iclass 3, count 0 2006.257.20:39:22.73#ibcon#wrote, iclass 3, count 0 2006.257.20:39:22.73#ibcon#about to read 3, iclass 3, count 0 2006.257.20:39:22.75#ibcon#read 3, iclass 3, count 0 2006.257.20:39:22.75#ibcon#about to read 4, iclass 3, count 0 2006.257.20:39:22.75#ibcon#read 4, iclass 3, count 0 2006.257.20:39:22.75#ibcon#about to read 5, iclass 3, count 0 2006.257.20:39:22.75#ibcon#read 5, iclass 3, count 0 2006.257.20:39:22.75#ibcon#about to read 6, iclass 3, count 0 2006.257.20:39:22.75#ibcon#read 6, iclass 3, count 0 2006.257.20:39:22.75#ibcon#end of sib2, iclass 3, count 0 2006.257.20:39:22.75#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:39:22.75#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:39:22.75#ibcon#[25=USB\r\n] 2006.257.20:39:22.75#ibcon#*before write, iclass 3, count 0 2006.257.20:39:22.75#ibcon#enter sib2, iclass 3, count 0 2006.257.20:39:22.75#ibcon#flushed, iclass 3, count 0 2006.257.20:39:22.75#ibcon#about to write, iclass 3, count 0 2006.257.20:39:22.75#ibcon#wrote, iclass 3, count 0 2006.257.20:39:22.75#ibcon#about to read 3, iclass 3, count 0 2006.257.20:39:22.78#ibcon#read 3, iclass 3, count 0 2006.257.20:39:22.78#ibcon#about to read 4, iclass 3, count 0 2006.257.20:39:22.78#ibcon#read 4, iclass 3, count 0 2006.257.20:39:22.78#ibcon#about to read 5, iclass 3, count 0 2006.257.20:39:22.78#ibcon#read 5, iclass 3, count 0 2006.257.20:39:22.78#ibcon#about to read 6, iclass 3, count 0 2006.257.20:39:22.78#ibcon#read 6, iclass 3, count 0 2006.257.20:39:22.78#ibcon#end of sib2, iclass 3, count 0 2006.257.20:39:22.78#ibcon#*after write, iclass 3, count 0 2006.257.20:39:22.78#ibcon#*before return 0, iclass 3, count 0 2006.257.20:39:22.78#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:22.78#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:22.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:39:22.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:39:22.78$vck44/valo=5,734.99 2006.257.20:39:22.78#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.20:39:22.78#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.20:39:22.78#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:22.78#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:39:22.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:39:22.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:39:22.78#ibcon#enter wrdev, iclass 5, count 0 2006.257.20:39:22.78#ibcon#first serial, iclass 5, count 0 2006.257.20:39:22.78#ibcon#enter sib2, iclass 5, count 0 2006.257.20:39:22.78#ibcon#flushed, iclass 5, count 0 2006.257.20:39:22.78#ibcon#about to write, iclass 5, count 0 2006.257.20:39:22.78#ibcon#wrote, iclass 5, count 0 2006.257.20:39:22.78#ibcon#about to read 3, iclass 5, count 0 2006.257.20:39:22.80#ibcon#read 3, iclass 5, count 0 2006.257.20:39:22.80#ibcon#about to read 4, iclass 5, count 0 2006.257.20:39:22.80#ibcon#read 4, iclass 5, count 0 2006.257.20:39:22.80#ibcon#about to read 5, iclass 5, count 0 2006.257.20:39:22.80#ibcon#read 5, iclass 5, count 0 2006.257.20:39:22.80#ibcon#about to read 6, iclass 5, count 0 2006.257.20:39:22.80#ibcon#read 6, iclass 5, count 0 2006.257.20:39:22.80#ibcon#end of sib2, iclass 5, count 0 2006.257.20:39:22.80#ibcon#*mode == 0, iclass 5, count 0 2006.257.20:39:22.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.20:39:22.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.20:39:22.80#ibcon#*before write, iclass 5, count 0 2006.257.20:39:22.80#ibcon#enter sib2, iclass 5, count 0 2006.257.20:39:22.80#ibcon#flushed, iclass 5, count 0 2006.257.20:39:22.80#ibcon#about to write, iclass 5, count 0 2006.257.20:39:22.80#ibcon#wrote, iclass 5, count 0 2006.257.20:39:22.80#ibcon#about to read 3, iclass 5, count 0 2006.257.20:39:22.84#ibcon#read 3, iclass 5, count 0 2006.257.20:39:22.84#ibcon#about to read 4, iclass 5, count 0 2006.257.20:39:22.84#ibcon#read 4, iclass 5, count 0 2006.257.20:39:22.84#ibcon#about to read 5, iclass 5, count 0 2006.257.20:39:22.84#ibcon#read 5, iclass 5, count 0 2006.257.20:39:22.84#ibcon#about to read 6, iclass 5, count 0 2006.257.20:39:22.84#ibcon#read 6, iclass 5, count 0 2006.257.20:39:22.84#ibcon#end of sib2, iclass 5, count 0 2006.257.20:39:22.84#ibcon#*after write, iclass 5, count 0 2006.257.20:39:22.84#ibcon#*before return 0, iclass 5, count 0 2006.257.20:39:22.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:39:22.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:39:22.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.20:39:22.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.20:39:22.84$vck44/va=5,4 2006.257.20:39:22.84#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.20:39:22.84#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.20:39:22.84#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:22.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:39:22.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:39:22.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:39:22.90#ibcon#enter wrdev, iclass 7, count 2 2006.257.20:39:22.90#ibcon#first serial, iclass 7, count 2 2006.257.20:39:22.90#ibcon#enter sib2, iclass 7, count 2 2006.257.20:39:22.90#ibcon#flushed, iclass 7, count 2 2006.257.20:39:22.90#ibcon#about to write, iclass 7, count 2 2006.257.20:39:22.90#ibcon#wrote, iclass 7, count 2 2006.257.20:39:22.90#ibcon#about to read 3, iclass 7, count 2 2006.257.20:39:22.92#ibcon#read 3, iclass 7, count 2 2006.257.20:39:22.92#ibcon#about to read 4, iclass 7, count 2 2006.257.20:39:22.92#ibcon#read 4, iclass 7, count 2 2006.257.20:39:22.92#ibcon#about to read 5, iclass 7, count 2 2006.257.20:39:22.92#ibcon#read 5, iclass 7, count 2 2006.257.20:39:22.92#ibcon#about to read 6, iclass 7, count 2 2006.257.20:39:22.92#ibcon#read 6, iclass 7, count 2 2006.257.20:39:22.92#ibcon#end of sib2, iclass 7, count 2 2006.257.20:39:22.92#ibcon#*mode == 0, iclass 7, count 2 2006.257.20:39:22.92#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.20:39:22.92#ibcon#[25=AT05-04\r\n] 2006.257.20:39:22.92#ibcon#*before write, iclass 7, count 2 2006.257.20:39:22.92#ibcon#enter sib2, iclass 7, count 2 2006.257.20:39:22.92#ibcon#flushed, iclass 7, count 2 2006.257.20:39:22.92#ibcon#about to write, iclass 7, count 2 2006.257.20:39:22.92#ibcon#wrote, iclass 7, count 2 2006.257.20:39:22.92#ibcon#about to read 3, iclass 7, count 2 2006.257.20:39:22.95#ibcon#read 3, iclass 7, count 2 2006.257.20:39:22.95#ibcon#about to read 4, iclass 7, count 2 2006.257.20:39:22.95#ibcon#read 4, iclass 7, count 2 2006.257.20:39:22.95#ibcon#about to read 5, iclass 7, count 2 2006.257.20:39:22.95#ibcon#read 5, iclass 7, count 2 2006.257.20:39:22.95#ibcon#about to read 6, iclass 7, count 2 2006.257.20:39:22.95#ibcon#read 6, iclass 7, count 2 2006.257.20:39:22.95#ibcon#end of sib2, iclass 7, count 2 2006.257.20:39:22.95#ibcon#*after write, iclass 7, count 2 2006.257.20:39:22.95#ibcon#*before return 0, iclass 7, count 2 2006.257.20:39:22.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:39:22.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:39:22.95#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.20:39:22.95#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:22.95#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:39:23.07#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:39:23.07#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:39:23.07#ibcon#enter wrdev, iclass 7, count 0 2006.257.20:39:23.07#ibcon#first serial, iclass 7, count 0 2006.257.20:39:23.07#ibcon#enter sib2, iclass 7, count 0 2006.257.20:39:23.07#ibcon#flushed, iclass 7, count 0 2006.257.20:39:23.07#ibcon#about to write, iclass 7, count 0 2006.257.20:39:23.07#ibcon#wrote, iclass 7, count 0 2006.257.20:39:23.07#ibcon#about to read 3, iclass 7, count 0 2006.257.20:39:23.09#ibcon#read 3, iclass 7, count 0 2006.257.20:39:23.09#ibcon#about to read 4, iclass 7, count 0 2006.257.20:39:23.09#ibcon#read 4, iclass 7, count 0 2006.257.20:39:23.09#ibcon#about to read 5, iclass 7, count 0 2006.257.20:39:23.09#ibcon#read 5, iclass 7, count 0 2006.257.20:39:23.09#ibcon#about to read 6, iclass 7, count 0 2006.257.20:39:23.09#ibcon#read 6, iclass 7, count 0 2006.257.20:39:23.09#ibcon#end of sib2, iclass 7, count 0 2006.257.20:39:23.09#ibcon#*mode == 0, iclass 7, count 0 2006.257.20:39:23.09#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.20:39:23.09#ibcon#[25=USB\r\n] 2006.257.20:39:23.09#ibcon#*before write, iclass 7, count 0 2006.257.20:39:23.09#ibcon#enter sib2, iclass 7, count 0 2006.257.20:39:23.09#ibcon#flushed, iclass 7, count 0 2006.257.20:39:23.09#ibcon#about to write, iclass 7, count 0 2006.257.20:39:23.09#ibcon#wrote, iclass 7, count 0 2006.257.20:39:23.09#ibcon#about to read 3, iclass 7, count 0 2006.257.20:39:23.12#ibcon#read 3, iclass 7, count 0 2006.257.20:39:23.12#ibcon#about to read 4, iclass 7, count 0 2006.257.20:39:23.12#ibcon#read 4, iclass 7, count 0 2006.257.20:39:23.12#ibcon#about to read 5, iclass 7, count 0 2006.257.20:39:23.12#ibcon#read 5, iclass 7, count 0 2006.257.20:39:23.12#ibcon#about to read 6, iclass 7, count 0 2006.257.20:39:23.12#ibcon#read 6, iclass 7, count 0 2006.257.20:39:23.12#ibcon#end of sib2, iclass 7, count 0 2006.257.20:39:23.12#ibcon#*after write, iclass 7, count 0 2006.257.20:39:23.12#ibcon#*before return 0, iclass 7, count 0 2006.257.20:39:23.12#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:39:23.12#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:39:23.12#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.20:39:23.12#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.20:39:23.12$vck44/valo=6,814.99 2006.257.20:39:23.12#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.20:39:23.12#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.20:39:23.12#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:23.12#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:39:23.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:39:23.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:39:23.12#ibcon#enter wrdev, iclass 11, count 0 2006.257.20:39:23.12#ibcon#first serial, iclass 11, count 0 2006.257.20:39:23.12#ibcon#enter sib2, iclass 11, count 0 2006.257.20:39:23.12#ibcon#flushed, iclass 11, count 0 2006.257.20:39:23.12#ibcon#about to write, iclass 11, count 0 2006.257.20:39:23.12#ibcon#wrote, iclass 11, count 0 2006.257.20:39:23.12#ibcon#about to read 3, iclass 11, count 0 2006.257.20:39:23.14#ibcon#read 3, iclass 11, count 0 2006.257.20:39:23.14#ibcon#about to read 4, iclass 11, count 0 2006.257.20:39:23.14#ibcon#read 4, iclass 11, count 0 2006.257.20:39:23.14#ibcon#about to read 5, iclass 11, count 0 2006.257.20:39:23.14#ibcon#read 5, iclass 11, count 0 2006.257.20:39:23.14#ibcon#about to read 6, iclass 11, count 0 2006.257.20:39:23.14#ibcon#read 6, iclass 11, count 0 2006.257.20:39:23.14#ibcon#end of sib2, iclass 11, count 0 2006.257.20:39:23.14#ibcon#*mode == 0, iclass 11, count 0 2006.257.20:39:23.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.20:39:23.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.20:39:23.14#ibcon#*before write, iclass 11, count 0 2006.257.20:39:23.14#ibcon#enter sib2, iclass 11, count 0 2006.257.20:39:23.14#ibcon#flushed, iclass 11, count 0 2006.257.20:39:23.14#ibcon#about to write, iclass 11, count 0 2006.257.20:39:23.14#ibcon#wrote, iclass 11, count 0 2006.257.20:39:23.14#ibcon#about to read 3, iclass 11, count 0 2006.257.20:39:23.18#ibcon#read 3, iclass 11, count 0 2006.257.20:39:23.18#ibcon#about to read 4, iclass 11, count 0 2006.257.20:39:23.18#ibcon#read 4, iclass 11, count 0 2006.257.20:39:23.18#ibcon#about to read 5, iclass 11, count 0 2006.257.20:39:23.18#ibcon#read 5, iclass 11, count 0 2006.257.20:39:23.18#ibcon#about to read 6, iclass 11, count 0 2006.257.20:39:23.18#ibcon#read 6, iclass 11, count 0 2006.257.20:39:23.18#ibcon#end of sib2, iclass 11, count 0 2006.257.20:39:23.18#ibcon#*after write, iclass 11, count 0 2006.257.20:39:23.18#ibcon#*before return 0, iclass 11, count 0 2006.257.20:39:23.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:39:23.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:39:23.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.20:39:23.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.20:39:23.18$vck44/va=6,4 2006.257.20:39:23.18#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.20:39:23.18#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.20:39:23.18#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:23.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:23.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:23.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:23.24#ibcon#enter wrdev, iclass 13, count 2 2006.257.20:39:23.24#ibcon#first serial, iclass 13, count 2 2006.257.20:39:23.24#ibcon#enter sib2, iclass 13, count 2 2006.257.20:39:23.24#ibcon#flushed, iclass 13, count 2 2006.257.20:39:23.24#ibcon#about to write, iclass 13, count 2 2006.257.20:39:23.24#ibcon#wrote, iclass 13, count 2 2006.257.20:39:23.24#ibcon#about to read 3, iclass 13, count 2 2006.257.20:39:23.26#ibcon#read 3, iclass 13, count 2 2006.257.20:39:23.26#ibcon#about to read 4, iclass 13, count 2 2006.257.20:39:23.26#ibcon#read 4, iclass 13, count 2 2006.257.20:39:23.26#ibcon#about to read 5, iclass 13, count 2 2006.257.20:39:23.26#ibcon#read 5, iclass 13, count 2 2006.257.20:39:23.26#ibcon#about to read 6, iclass 13, count 2 2006.257.20:39:23.26#ibcon#read 6, iclass 13, count 2 2006.257.20:39:23.26#ibcon#end of sib2, iclass 13, count 2 2006.257.20:39:23.26#ibcon#*mode == 0, iclass 13, count 2 2006.257.20:39:23.26#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.20:39:23.26#ibcon#[25=AT06-04\r\n] 2006.257.20:39:23.26#ibcon#*before write, iclass 13, count 2 2006.257.20:39:23.26#ibcon#enter sib2, iclass 13, count 2 2006.257.20:39:23.26#ibcon#flushed, iclass 13, count 2 2006.257.20:39:23.26#ibcon#about to write, iclass 13, count 2 2006.257.20:39:23.26#ibcon#wrote, iclass 13, count 2 2006.257.20:39:23.26#ibcon#about to read 3, iclass 13, count 2 2006.257.20:39:23.29#ibcon#read 3, iclass 13, count 2 2006.257.20:39:23.29#ibcon#about to read 4, iclass 13, count 2 2006.257.20:39:23.29#ibcon#read 4, iclass 13, count 2 2006.257.20:39:23.29#ibcon#about to read 5, iclass 13, count 2 2006.257.20:39:23.29#ibcon#read 5, iclass 13, count 2 2006.257.20:39:23.29#ibcon#about to read 6, iclass 13, count 2 2006.257.20:39:23.29#ibcon#read 6, iclass 13, count 2 2006.257.20:39:23.29#ibcon#end of sib2, iclass 13, count 2 2006.257.20:39:23.29#ibcon#*after write, iclass 13, count 2 2006.257.20:39:23.29#ibcon#*before return 0, iclass 13, count 2 2006.257.20:39:23.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:23.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:23.29#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.20:39:23.29#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:23.29#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:23.41#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:23.41#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:23.41#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:39:23.41#ibcon#first serial, iclass 13, count 0 2006.257.20:39:23.41#ibcon#enter sib2, iclass 13, count 0 2006.257.20:39:23.41#ibcon#flushed, iclass 13, count 0 2006.257.20:39:23.41#ibcon#about to write, iclass 13, count 0 2006.257.20:39:23.41#ibcon#wrote, iclass 13, count 0 2006.257.20:39:23.41#ibcon#about to read 3, iclass 13, count 0 2006.257.20:39:23.43#ibcon#read 3, iclass 13, count 0 2006.257.20:39:23.43#ibcon#about to read 4, iclass 13, count 0 2006.257.20:39:23.43#ibcon#read 4, iclass 13, count 0 2006.257.20:39:23.43#ibcon#about to read 5, iclass 13, count 0 2006.257.20:39:23.43#ibcon#read 5, iclass 13, count 0 2006.257.20:39:23.43#ibcon#about to read 6, iclass 13, count 0 2006.257.20:39:23.43#ibcon#read 6, iclass 13, count 0 2006.257.20:39:23.43#ibcon#end of sib2, iclass 13, count 0 2006.257.20:39:23.43#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:39:23.43#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:39:23.43#ibcon#[25=USB\r\n] 2006.257.20:39:23.43#ibcon#*before write, iclass 13, count 0 2006.257.20:39:23.43#ibcon#enter sib2, iclass 13, count 0 2006.257.20:39:23.43#ibcon#flushed, iclass 13, count 0 2006.257.20:39:23.43#ibcon#about to write, iclass 13, count 0 2006.257.20:39:23.43#ibcon#wrote, iclass 13, count 0 2006.257.20:39:23.43#ibcon#about to read 3, iclass 13, count 0 2006.257.20:39:23.46#ibcon#read 3, iclass 13, count 0 2006.257.20:39:23.46#ibcon#about to read 4, iclass 13, count 0 2006.257.20:39:23.46#ibcon#read 4, iclass 13, count 0 2006.257.20:39:23.46#ibcon#about to read 5, iclass 13, count 0 2006.257.20:39:23.46#ibcon#read 5, iclass 13, count 0 2006.257.20:39:23.46#ibcon#about to read 6, iclass 13, count 0 2006.257.20:39:23.46#ibcon#read 6, iclass 13, count 0 2006.257.20:39:23.46#ibcon#end of sib2, iclass 13, count 0 2006.257.20:39:23.46#ibcon#*after write, iclass 13, count 0 2006.257.20:39:23.46#ibcon#*before return 0, iclass 13, count 0 2006.257.20:39:23.46#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:23.46#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:23.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:39:23.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:39:23.46$vck44/valo=7,864.99 2006.257.20:39:23.46#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.20:39:23.46#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.20:39:23.46#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:23.46#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:23.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:23.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:23.46#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:39:23.46#ibcon#first serial, iclass 15, count 0 2006.257.20:39:23.46#ibcon#enter sib2, iclass 15, count 0 2006.257.20:39:23.46#ibcon#flushed, iclass 15, count 0 2006.257.20:39:23.46#ibcon#about to write, iclass 15, count 0 2006.257.20:39:23.46#ibcon#wrote, iclass 15, count 0 2006.257.20:39:23.46#ibcon#about to read 3, iclass 15, count 0 2006.257.20:39:23.48#ibcon#read 3, iclass 15, count 0 2006.257.20:39:23.48#ibcon#about to read 4, iclass 15, count 0 2006.257.20:39:23.48#ibcon#read 4, iclass 15, count 0 2006.257.20:39:23.48#ibcon#about to read 5, iclass 15, count 0 2006.257.20:39:23.48#ibcon#read 5, iclass 15, count 0 2006.257.20:39:23.48#ibcon#about to read 6, iclass 15, count 0 2006.257.20:39:23.48#ibcon#read 6, iclass 15, count 0 2006.257.20:39:23.48#ibcon#end of sib2, iclass 15, count 0 2006.257.20:39:23.48#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:39:23.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:39:23.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.20:39:23.48#ibcon#*before write, iclass 15, count 0 2006.257.20:39:23.48#ibcon#enter sib2, iclass 15, count 0 2006.257.20:39:23.48#ibcon#flushed, iclass 15, count 0 2006.257.20:39:23.48#ibcon#about to write, iclass 15, count 0 2006.257.20:39:23.48#ibcon#wrote, iclass 15, count 0 2006.257.20:39:23.48#ibcon#about to read 3, iclass 15, count 0 2006.257.20:39:23.52#ibcon#read 3, iclass 15, count 0 2006.257.20:39:23.52#ibcon#about to read 4, iclass 15, count 0 2006.257.20:39:23.52#ibcon#read 4, iclass 15, count 0 2006.257.20:39:23.52#ibcon#about to read 5, iclass 15, count 0 2006.257.20:39:23.52#ibcon#read 5, iclass 15, count 0 2006.257.20:39:23.52#ibcon#about to read 6, iclass 15, count 0 2006.257.20:39:23.52#ibcon#read 6, iclass 15, count 0 2006.257.20:39:23.52#ibcon#end of sib2, iclass 15, count 0 2006.257.20:39:23.52#ibcon#*after write, iclass 15, count 0 2006.257.20:39:23.52#ibcon#*before return 0, iclass 15, count 0 2006.257.20:39:23.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:23.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:23.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:39:23.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:39:23.52$vck44/va=7,4 2006.257.20:39:23.52#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.20:39:23.52#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.20:39:23.52#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:23.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:23.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:23.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:23.58#ibcon#enter wrdev, iclass 17, count 2 2006.257.20:39:23.58#ibcon#first serial, iclass 17, count 2 2006.257.20:39:23.58#ibcon#enter sib2, iclass 17, count 2 2006.257.20:39:23.58#ibcon#flushed, iclass 17, count 2 2006.257.20:39:23.58#ibcon#about to write, iclass 17, count 2 2006.257.20:39:23.58#ibcon#wrote, iclass 17, count 2 2006.257.20:39:23.58#ibcon#about to read 3, iclass 17, count 2 2006.257.20:39:23.60#ibcon#read 3, iclass 17, count 2 2006.257.20:39:23.60#ibcon#about to read 4, iclass 17, count 2 2006.257.20:39:23.60#ibcon#read 4, iclass 17, count 2 2006.257.20:39:23.60#ibcon#about to read 5, iclass 17, count 2 2006.257.20:39:23.60#ibcon#read 5, iclass 17, count 2 2006.257.20:39:23.60#ibcon#about to read 6, iclass 17, count 2 2006.257.20:39:23.60#ibcon#read 6, iclass 17, count 2 2006.257.20:39:23.60#ibcon#end of sib2, iclass 17, count 2 2006.257.20:39:23.60#ibcon#*mode == 0, iclass 17, count 2 2006.257.20:39:23.60#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.20:39:23.60#ibcon#[25=AT07-04\r\n] 2006.257.20:39:23.60#ibcon#*before write, iclass 17, count 2 2006.257.20:39:23.60#ibcon#enter sib2, iclass 17, count 2 2006.257.20:39:23.60#ibcon#flushed, iclass 17, count 2 2006.257.20:39:23.60#ibcon#about to write, iclass 17, count 2 2006.257.20:39:23.60#ibcon#wrote, iclass 17, count 2 2006.257.20:39:23.60#ibcon#about to read 3, iclass 17, count 2 2006.257.20:39:23.63#ibcon#read 3, iclass 17, count 2 2006.257.20:39:23.63#ibcon#about to read 4, iclass 17, count 2 2006.257.20:39:23.63#ibcon#read 4, iclass 17, count 2 2006.257.20:39:23.63#ibcon#about to read 5, iclass 17, count 2 2006.257.20:39:23.63#ibcon#read 5, iclass 17, count 2 2006.257.20:39:23.63#ibcon#about to read 6, iclass 17, count 2 2006.257.20:39:23.63#ibcon#read 6, iclass 17, count 2 2006.257.20:39:23.63#ibcon#end of sib2, iclass 17, count 2 2006.257.20:39:23.63#ibcon#*after write, iclass 17, count 2 2006.257.20:39:23.63#ibcon#*before return 0, iclass 17, count 2 2006.257.20:39:23.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:23.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:23.63#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.20:39:23.63#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:23.63#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:23.75#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:23.75#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:23.75#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:39:23.75#ibcon#first serial, iclass 17, count 0 2006.257.20:39:23.75#ibcon#enter sib2, iclass 17, count 0 2006.257.20:39:23.75#ibcon#flushed, iclass 17, count 0 2006.257.20:39:23.75#ibcon#about to write, iclass 17, count 0 2006.257.20:39:23.75#ibcon#wrote, iclass 17, count 0 2006.257.20:39:23.75#ibcon#about to read 3, iclass 17, count 0 2006.257.20:39:23.77#ibcon#read 3, iclass 17, count 0 2006.257.20:39:23.77#ibcon#about to read 4, iclass 17, count 0 2006.257.20:39:23.77#ibcon#read 4, iclass 17, count 0 2006.257.20:39:23.77#ibcon#about to read 5, iclass 17, count 0 2006.257.20:39:23.77#ibcon#read 5, iclass 17, count 0 2006.257.20:39:23.77#ibcon#about to read 6, iclass 17, count 0 2006.257.20:39:23.77#ibcon#read 6, iclass 17, count 0 2006.257.20:39:23.77#ibcon#end of sib2, iclass 17, count 0 2006.257.20:39:23.77#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:39:23.77#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:39:23.77#ibcon#[25=USB\r\n] 2006.257.20:39:23.77#ibcon#*before write, iclass 17, count 0 2006.257.20:39:23.77#ibcon#enter sib2, iclass 17, count 0 2006.257.20:39:23.77#ibcon#flushed, iclass 17, count 0 2006.257.20:39:23.77#ibcon#about to write, iclass 17, count 0 2006.257.20:39:23.77#ibcon#wrote, iclass 17, count 0 2006.257.20:39:23.77#ibcon#about to read 3, iclass 17, count 0 2006.257.20:39:23.80#ibcon#read 3, iclass 17, count 0 2006.257.20:39:23.80#ibcon#about to read 4, iclass 17, count 0 2006.257.20:39:23.80#ibcon#read 4, iclass 17, count 0 2006.257.20:39:23.80#ibcon#about to read 5, iclass 17, count 0 2006.257.20:39:23.80#ibcon#read 5, iclass 17, count 0 2006.257.20:39:23.80#ibcon#about to read 6, iclass 17, count 0 2006.257.20:39:23.80#ibcon#read 6, iclass 17, count 0 2006.257.20:39:23.80#ibcon#end of sib2, iclass 17, count 0 2006.257.20:39:23.80#ibcon#*after write, iclass 17, count 0 2006.257.20:39:23.80#ibcon#*before return 0, iclass 17, count 0 2006.257.20:39:23.80#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:23.80#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:23.80#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:39:23.80#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:39:23.80$vck44/valo=8,884.99 2006.257.20:39:23.80#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.20:39:23.80#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.20:39:23.80#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:23.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:23.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:23.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:23.80#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:39:23.80#ibcon#first serial, iclass 19, count 0 2006.257.20:39:23.80#ibcon#enter sib2, iclass 19, count 0 2006.257.20:39:23.80#ibcon#flushed, iclass 19, count 0 2006.257.20:39:23.80#ibcon#about to write, iclass 19, count 0 2006.257.20:39:23.80#ibcon#wrote, iclass 19, count 0 2006.257.20:39:23.80#ibcon#about to read 3, iclass 19, count 0 2006.257.20:39:23.82#ibcon#read 3, iclass 19, count 0 2006.257.20:39:23.82#ibcon#about to read 4, iclass 19, count 0 2006.257.20:39:23.82#ibcon#read 4, iclass 19, count 0 2006.257.20:39:23.82#ibcon#about to read 5, iclass 19, count 0 2006.257.20:39:23.82#ibcon#read 5, iclass 19, count 0 2006.257.20:39:23.82#ibcon#about to read 6, iclass 19, count 0 2006.257.20:39:23.82#ibcon#read 6, iclass 19, count 0 2006.257.20:39:23.82#ibcon#end of sib2, iclass 19, count 0 2006.257.20:39:23.82#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:39:23.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:39:23.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.20:39:23.82#ibcon#*before write, iclass 19, count 0 2006.257.20:39:23.82#ibcon#enter sib2, iclass 19, count 0 2006.257.20:39:23.82#ibcon#flushed, iclass 19, count 0 2006.257.20:39:23.82#ibcon#about to write, iclass 19, count 0 2006.257.20:39:23.82#ibcon#wrote, iclass 19, count 0 2006.257.20:39:23.82#ibcon#about to read 3, iclass 19, count 0 2006.257.20:39:23.86#ibcon#read 3, iclass 19, count 0 2006.257.20:39:23.86#ibcon#about to read 4, iclass 19, count 0 2006.257.20:39:23.86#ibcon#read 4, iclass 19, count 0 2006.257.20:39:23.86#ibcon#about to read 5, iclass 19, count 0 2006.257.20:39:23.86#ibcon#read 5, iclass 19, count 0 2006.257.20:39:23.86#ibcon#about to read 6, iclass 19, count 0 2006.257.20:39:23.86#ibcon#read 6, iclass 19, count 0 2006.257.20:39:23.86#ibcon#end of sib2, iclass 19, count 0 2006.257.20:39:23.86#ibcon#*after write, iclass 19, count 0 2006.257.20:39:23.86#ibcon#*before return 0, iclass 19, count 0 2006.257.20:39:23.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:23.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:23.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:39:23.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:39:23.86$vck44/va=8,4 2006.257.20:39:23.86#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.20:39:23.86#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.20:39:23.86#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:23.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:23.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:23.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:23.92#ibcon#enter wrdev, iclass 21, count 2 2006.257.20:39:23.92#ibcon#first serial, iclass 21, count 2 2006.257.20:39:23.92#ibcon#enter sib2, iclass 21, count 2 2006.257.20:39:23.92#ibcon#flushed, iclass 21, count 2 2006.257.20:39:23.92#ibcon#about to write, iclass 21, count 2 2006.257.20:39:23.92#ibcon#wrote, iclass 21, count 2 2006.257.20:39:23.92#ibcon#about to read 3, iclass 21, count 2 2006.257.20:39:23.94#ibcon#read 3, iclass 21, count 2 2006.257.20:39:23.94#ibcon#about to read 4, iclass 21, count 2 2006.257.20:39:23.94#ibcon#read 4, iclass 21, count 2 2006.257.20:39:23.94#ibcon#about to read 5, iclass 21, count 2 2006.257.20:39:23.94#ibcon#read 5, iclass 21, count 2 2006.257.20:39:23.94#ibcon#about to read 6, iclass 21, count 2 2006.257.20:39:23.94#ibcon#read 6, iclass 21, count 2 2006.257.20:39:23.94#ibcon#end of sib2, iclass 21, count 2 2006.257.20:39:23.94#ibcon#*mode == 0, iclass 21, count 2 2006.257.20:39:23.94#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.20:39:23.94#ibcon#[25=AT08-04\r\n] 2006.257.20:39:23.94#ibcon#*before write, iclass 21, count 2 2006.257.20:39:23.94#ibcon#enter sib2, iclass 21, count 2 2006.257.20:39:23.94#ibcon#flushed, iclass 21, count 2 2006.257.20:39:23.94#ibcon#about to write, iclass 21, count 2 2006.257.20:39:23.94#ibcon#wrote, iclass 21, count 2 2006.257.20:39:23.94#ibcon#about to read 3, iclass 21, count 2 2006.257.20:39:23.97#ibcon#read 3, iclass 21, count 2 2006.257.20:39:23.97#ibcon#about to read 4, iclass 21, count 2 2006.257.20:39:23.97#ibcon#read 4, iclass 21, count 2 2006.257.20:39:23.97#ibcon#about to read 5, iclass 21, count 2 2006.257.20:39:23.97#ibcon#read 5, iclass 21, count 2 2006.257.20:39:23.97#ibcon#about to read 6, iclass 21, count 2 2006.257.20:39:23.97#ibcon#read 6, iclass 21, count 2 2006.257.20:39:23.97#ibcon#end of sib2, iclass 21, count 2 2006.257.20:39:23.97#ibcon#*after write, iclass 21, count 2 2006.257.20:39:23.97#ibcon#*before return 0, iclass 21, count 2 2006.257.20:39:23.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:23.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:23.97#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.20:39:23.97#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:23.97#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:24.09#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:24.09#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:24.09#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:39:24.09#ibcon#first serial, iclass 21, count 0 2006.257.20:39:24.09#ibcon#enter sib2, iclass 21, count 0 2006.257.20:39:24.09#ibcon#flushed, iclass 21, count 0 2006.257.20:39:24.09#ibcon#about to write, iclass 21, count 0 2006.257.20:39:24.09#ibcon#wrote, iclass 21, count 0 2006.257.20:39:24.09#ibcon#about to read 3, iclass 21, count 0 2006.257.20:39:24.11#ibcon#read 3, iclass 21, count 0 2006.257.20:39:24.11#ibcon#about to read 4, iclass 21, count 0 2006.257.20:39:24.11#ibcon#read 4, iclass 21, count 0 2006.257.20:39:24.11#ibcon#about to read 5, iclass 21, count 0 2006.257.20:39:24.11#ibcon#read 5, iclass 21, count 0 2006.257.20:39:24.11#ibcon#about to read 6, iclass 21, count 0 2006.257.20:39:24.11#ibcon#read 6, iclass 21, count 0 2006.257.20:39:24.11#ibcon#end of sib2, iclass 21, count 0 2006.257.20:39:24.11#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:39:24.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:39:24.11#ibcon#[25=USB\r\n] 2006.257.20:39:24.11#ibcon#*before write, iclass 21, count 0 2006.257.20:39:24.11#ibcon#enter sib2, iclass 21, count 0 2006.257.20:39:24.11#ibcon#flushed, iclass 21, count 0 2006.257.20:39:24.11#ibcon#about to write, iclass 21, count 0 2006.257.20:39:24.11#ibcon#wrote, iclass 21, count 0 2006.257.20:39:24.11#ibcon#about to read 3, iclass 21, count 0 2006.257.20:39:24.14#ibcon#read 3, iclass 21, count 0 2006.257.20:39:24.14#ibcon#about to read 4, iclass 21, count 0 2006.257.20:39:24.14#ibcon#read 4, iclass 21, count 0 2006.257.20:39:24.14#ibcon#about to read 5, iclass 21, count 0 2006.257.20:39:24.14#ibcon#read 5, iclass 21, count 0 2006.257.20:39:24.14#ibcon#about to read 6, iclass 21, count 0 2006.257.20:39:24.14#ibcon#read 6, iclass 21, count 0 2006.257.20:39:24.14#ibcon#end of sib2, iclass 21, count 0 2006.257.20:39:24.14#ibcon#*after write, iclass 21, count 0 2006.257.20:39:24.14#ibcon#*before return 0, iclass 21, count 0 2006.257.20:39:24.14#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:24.14#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:24.14#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:39:24.14#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:39:24.14$vck44/vblo=1,629.99 2006.257.20:39:24.14#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.20:39:24.14#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.20:39:24.14#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:24.14#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:24.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:24.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:24.14#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:39:24.14#ibcon#first serial, iclass 23, count 0 2006.257.20:39:24.14#ibcon#enter sib2, iclass 23, count 0 2006.257.20:39:24.14#ibcon#flushed, iclass 23, count 0 2006.257.20:39:24.14#ibcon#about to write, iclass 23, count 0 2006.257.20:39:24.14#ibcon#wrote, iclass 23, count 0 2006.257.20:39:24.14#ibcon#about to read 3, iclass 23, count 0 2006.257.20:39:24.16#ibcon#read 3, iclass 23, count 0 2006.257.20:39:24.16#ibcon#about to read 4, iclass 23, count 0 2006.257.20:39:24.16#ibcon#read 4, iclass 23, count 0 2006.257.20:39:24.16#ibcon#about to read 5, iclass 23, count 0 2006.257.20:39:24.16#ibcon#read 5, iclass 23, count 0 2006.257.20:39:24.16#ibcon#about to read 6, iclass 23, count 0 2006.257.20:39:24.16#ibcon#read 6, iclass 23, count 0 2006.257.20:39:24.16#ibcon#end of sib2, iclass 23, count 0 2006.257.20:39:24.16#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:39:24.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:39:24.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.20:39:24.16#ibcon#*before write, iclass 23, count 0 2006.257.20:39:24.16#ibcon#enter sib2, iclass 23, count 0 2006.257.20:39:24.16#ibcon#flushed, iclass 23, count 0 2006.257.20:39:24.16#ibcon#about to write, iclass 23, count 0 2006.257.20:39:24.16#ibcon#wrote, iclass 23, count 0 2006.257.20:39:24.16#ibcon#about to read 3, iclass 23, count 0 2006.257.20:39:24.20#ibcon#read 3, iclass 23, count 0 2006.257.20:39:24.20#ibcon#about to read 4, iclass 23, count 0 2006.257.20:39:24.20#ibcon#read 4, iclass 23, count 0 2006.257.20:39:24.20#ibcon#about to read 5, iclass 23, count 0 2006.257.20:39:24.20#ibcon#read 5, iclass 23, count 0 2006.257.20:39:24.20#ibcon#about to read 6, iclass 23, count 0 2006.257.20:39:24.20#ibcon#read 6, iclass 23, count 0 2006.257.20:39:24.20#ibcon#end of sib2, iclass 23, count 0 2006.257.20:39:24.20#ibcon#*after write, iclass 23, count 0 2006.257.20:39:24.20#ibcon#*before return 0, iclass 23, count 0 2006.257.20:39:24.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:24.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:24.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:39:24.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:39:24.20$vck44/vb=1,4 2006.257.20:39:24.20#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.20:39:24.20#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.20:39:24.20#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:24.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:39:24.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:39:24.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:39:24.20#ibcon#enter wrdev, iclass 25, count 2 2006.257.20:39:24.20#ibcon#first serial, iclass 25, count 2 2006.257.20:39:24.20#ibcon#enter sib2, iclass 25, count 2 2006.257.20:39:24.20#ibcon#flushed, iclass 25, count 2 2006.257.20:39:24.20#ibcon#about to write, iclass 25, count 2 2006.257.20:39:24.20#ibcon#wrote, iclass 25, count 2 2006.257.20:39:24.20#ibcon#about to read 3, iclass 25, count 2 2006.257.20:39:24.22#ibcon#read 3, iclass 25, count 2 2006.257.20:39:24.22#ibcon#about to read 4, iclass 25, count 2 2006.257.20:39:24.22#ibcon#read 4, iclass 25, count 2 2006.257.20:39:24.22#ibcon#about to read 5, iclass 25, count 2 2006.257.20:39:24.22#ibcon#read 5, iclass 25, count 2 2006.257.20:39:24.22#ibcon#about to read 6, iclass 25, count 2 2006.257.20:39:24.22#ibcon#read 6, iclass 25, count 2 2006.257.20:39:24.22#ibcon#end of sib2, iclass 25, count 2 2006.257.20:39:24.22#ibcon#*mode == 0, iclass 25, count 2 2006.257.20:39:24.22#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.20:39:24.22#ibcon#[27=AT01-04\r\n] 2006.257.20:39:24.22#ibcon#*before write, iclass 25, count 2 2006.257.20:39:24.22#ibcon#enter sib2, iclass 25, count 2 2006.257.20:39:24.22#ibcon#flushed, iclass 25, count 2 2006.257.20:39:24.22#ibcon#about to write, iclass 25, count 2 2006.257.20:39:24.22#ibcon#wrote, iclass 25, count 2 2006.257.20:39:24.22#ibcon#about to read 3, iclass 25, count 2 2006.257.20:39:24.25#ibcon#read 3, iclass 25, count 2 2006.257.20:39:24.25#ibcon#about to read 4, iclass 25, count 2 2006.257.20:39:24.25#ibcon#read 4, iclass 25, count 2 2006.257.20:39:24.25#ibcon#about to read 5, iclass 25, count 2 2006.257.20:39:24.25#ibcon#read 5, iclass 25, count 2 2006.257.20:39:24.25#ibcon#about to read 6, iclass 25, count 2 2006.257.20:39:24.25#ibcon#read 6, iclass 25, count 2 2006.257.20:39:24.25#ibcon#end of sib2, iclass 25, count 2 2006.257.20:39:24.25#ibcon#*after write, iclass 25, count 2 2006.257.20:39:24.25#ibcon#*before return 0, iclass 25, count 2 2006.257.20:39:24.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:39:24.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:39:24.25#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.20:39:24.25#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:24.25#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:39:24.37#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:39:24.37#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:39:24.37#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:39:24.37#ibcon#first serial, iclass 25, count 0 2006.257.20:39:24.37#ibcon#enter sib2, iclass 25, count 0 2006.257.20:39:24.37#ibcon#flushed, iclass 25, count 0 2006.257.20:39:24.37#ibcon#about to write, iclass 25, count 0 2006.257.20:39:24.37#ibcon#wrote, iclass 25, count 0 2006.257.20:39:24.37#ibcon#about to read 3, iclass 25, count 0 2006.257.20:39:24.39#ibcon#read 3, iclass 25, count 0 2006.257.20:39:24.39#ibcon#about to read 4, iclass 25, count 0 2006.257.20:39:24.39#ibcon#read 4, iclass 25, count 0 2006.257.20:39:24.39#ibcon#about to read 5, iclass 25, count 0 2006.257.20:39:24.39#ibcon#read 5, iclass 25, count 0 2006.257.20:39:24.39#ibcon#about to read 6, iclass 25, count 0 2006.257.20:39:24.39#ibcon#read 6, iclass 25, count 0 2006.257.20:39:24.39#ibcon#end of sib2, iclass 25, count 0 2006.257.20:39:24.39#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:39:24.39#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:39:24.39#ibcon#[27=USB\r\n] 2006.257.20:39:24.39#ibcon#*before write, iclass 25, count 0 2006.257.20:39:24.39#ibcon#enter sib2, iclass 25, count 0 2006.257.20:39:24.39#ibcon#flushed, iclass 25, count 0 2006.257.20:39:24.39#ibcon#about to write, iclass 25, count 0 2006.257.20:39:24.39#ibcon#wrote, iclass 25, count 0 2006.257.20:39:24.39#ibcon#about to read 3, iclass 25, count 0 2006.257.20:39:24.42#ibcon#read 3, iclass 25, count 0 2006.257.20:39:24.42#ibcon#about to read 4, iclass 25, count 0 2006.257.20:39:24.42#ibcon#read 4, iclass 25, count 0 2006.257.20:39:24.42#ibcon#about to read 5, iclass 25, count 0 2006.257.20:39:24.42#ibcon#read 5, iclass 25, count 0 2006.257.20:39:24.42#ibcon#about to read 6, iclass 25, count 0 2006.257.20:39:24.42#ibcon#read 6, iclass 25, count 0 2006.257.20:39:24.42#ibcon#end of sib2, iclass 25, count 0 2006.257.20:39:24.42#ibcon#*after write, iclass 25, count 0 2006.257.20:39:24.42#ibcon#*before return 0, iclass 25, count 0 2006.257.20:39:24.42#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:39:24.42#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:39:24.42#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:39:24.42#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:39:24.42$vck44/vblo=2,634.99 2006.257.20:39:24.42#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.20:39:24.42#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.20:39:24.42#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:24.42#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:24.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:24.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:24.42#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:39:24.42#ibcon#first serial, iclass 27, count 0 2006.257.20:39:24.42#ibcon#enter sib2, iclass 27, count 0 2006.257.20:39:24.42#ibcon#flushed, iclass 27, count 0 2006.257.20:39:24.42#ibcon#about to write, iclass 27, count 0 2006.257.20:39:24.42#ibcon#wrote, iclass 27, count 0 2006.257.20:39:24.42#ibcon#about to read 3, iclass 27, count 0 2006.257.20:39:24.44#ibcon#read 3, iclass 27, count 0 2006.257.20:39:24.44#ibcon#about to read 4, iclass 27, count 0 2006.257.20:39:24.44#ibcon#read 4, iclass 27, count 0 2006.257.20:39:24.44#ibcon#about to read 5, iclass 27, count 0 2006.257.20:39:24.44#ibcon#read 5, iclass 27, count 0 2006.257.20:39:24.44#ibcon#about to read 6, iclass 27, count 0 2006.257.20:39:24.44#ibcon#read 6, iclass 27, count 0 2006.257.20:39:24.44#ibcon#end of sib2, iclass 27, count 0 2006.257.20:39:24.44#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:39:24.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:39:24.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.20:39:24.44#ibcon#*before write, iclass 27, count 0 2006.257.20:39:24.44#ibcon#enter sib2, iclass 27, count 0 2006.257.20:39:24.44#ibcon#flushed, iclass 27, count 0 2006.257.20:39:24.44#ibcon#about to write, iclass 27, count 0 2006.257.20:39:24.44#ibcon#wrote, iclass 27, count 0 2006.257.20:39:24.44#ibcon#about to read 3, iclass 27, count 0 2006.257.20:39:24.48#ibcon#read 3, iclass 27, count 0 2006.257.20:39:24.48#ibcon#about to read 4, iclass 27, count 0 2006.257.20:39:24.48#ibcon#read 4, iclass 27, count 0 2006.257.20:39:24.48#ibcon#about to read 5, iclass 27, count 0 2006.257.20:39:24.48#ibcon#read 5, iclass 27, count 0 2006.257.20:39:24.48#ibcon#about to read 6, iclass 27, count 0 2006.257.20:39:24.48#ibcon#read 6, iclass 27, count 0 2006.257.20:39:24.48#ibcon#end of sib2, iclass 27, count 0 2006.257.20:39:24.48#ibcon#*after write, iclass 27, count 0 2006.257.20:39:24.48#ibcon#*before return 0, iclass 27, count 0 2006.257.20:39:24.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:24.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:39:24.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:39:24.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:39:24.48$vck44/vb=2,5 2006.257.20:39:24.48#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.20:39:24.48#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.20:39:24.48#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:24.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:24.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:24.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:24.54#ibcon#enter wrdev, iclass 29, count 2 2006.257.20:39:24.54#ibcon#first serial, iclass 29, count 2 2006.257.20:39:24.54#ibcon#enter sib2, iclass 29, count 2 2006.257.20:39:24.54#ibcon#flushed, iclass 29, count 2 2006.257.20:39:24.54#ibcon#about to write, iclass 29, count 2 2006.257.20:39:24.54#ibcon#wrote, iclass 29, count 2 2006.257.20:39:24.54#ibcon#about to read 3, iclass 29, count 2 2006.257.20:39:24.56#ibcon#read 3, iclass 29, count 2 2006.257.20:39:24.56#ibcon#about to read 4, iclass 29, count 2 2006.257.20:39:24.56#ibcon#read 4, iclass 29, count 2 2006.257.20:39:24.56#ibcon#about to read 5, iclass 29, count 2 2006.257.20:39:24.56#ibcon#read 5, iclass 29, count 2 2006.257.20:39:24.56#ibcon#about to read 6, iclass 29, count 2 2006.257.20:39:24.56#ibcon#read 6, iclass 29, count 2 2006.257.20:39:24.56#ibcon#end of sib2, iclass 29, count 2 2006.257.20:39:24.56#ibcon#*mode == 0, iclass 29, count 2 2006.257.20:39:24.56#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.20:39:24.56#ibcon#[27=AT02-05\r\n] 2006.257.20:39:24.56#ibcon#*before write, iclass 29, count 2 2006.257.20:39:24.56#ibcon#enter sib2, iclass 29, count 2 2006.257.20:39:24.56#ibcon#flushed, iclass 29, count 2 2006.257.20:39:24.56#ibcon#about to write, iclass 29, count 2 2006.257.20:39:24.56#ibcon#wrote, iclass 29, count 2 2006.257.20:39:24.56#ibcon#about to read 3, iclass 29, count 2 2006.257.20:39:24.59#ibcon#read 3, iclass 29, count 2 2006.257.20:39:24.59#ibcon#about to read 4, iclass 29, count 2 2006.257.20:39:24.59#ibcon#read 4, iclass 29, count 2 2006.257.20:39:24.59#ibcon#about to read 5, iclass 29, count 2 2006.257.20:39:24.59#ibcon#read 5, iclass 29, count 2 2006.257.20:39:24.59#ibcon#about to read 6, iclass 29, count 2 2006.257.20:39:24.59#ibcon#read 6, iclass 29, count 2 2006.257.20:39:24.59#ibcon#end of sib2, iclass 29, count 2 2006.257.20:39:24.59#ibcon#*after write, iclass 29, count 2 2006.257.20:39:24.59#ibcon#*before return 0, iclass 29, count 2 2006.257.20:39:24.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:24.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:39:24.59#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.20:39:24.59#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:24.59#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:24.71#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:24.71#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:24.71#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:39:24.71#ibcon#first serial, iclass 29, count 0 2006.257.20:39:24.71#ibcon#enter sib2, iclass 29, count 0 2006.257.20:39:24.71#ibcon#flushed, iclass 29, count 0 2006.257.20:39:24.71#ibcon#about to write, iclass 29, count 0 2006.257.20:39:24.71#ibcon#wrote, iclass 29, count 0 2006.257.20:39:24.71#ibcon#about to read 3, iclass 29, count 0 2006.257.20:39:24.73#ibcon#read 3, iclass 29, count 0 2006.257.20:39:24.73#ibcon#about to read 4, iclass 29, count 0 2006.257.20:39:24.73#ibcon#read 4, iclass 29, count 0 2006.257.20:39:24.73#ibcon#about to read 5, iclass 29, count 0 2006.257.20:39:24.73#ibcon#read 5, iclass 29, count 0 2006.257.20:39:24.73#ibcon#about to read 6, iclass 29, count 0 2006.257.20:39:24.73#ibcon#read 6, iclass 29, count 0 2006.257.20:39:24.73#ibcon#end of sib2, iclass 29, count 0 2006.257.20:39:24.73#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:39:24.73#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:39:24.73#ibcon#[27=USB\r\n] 2006.257.20:39:24.73#ibcon#*before write, iclass 29, count 0 2006.257.20:39:24.73#ibcon#enter sib2, iclass 29, count 0 2006.257.20:39:24.73#ibcon#flushed, iclass 29, count 0 2006.257.20:39:24.73#ibcon#about to write, iclass 29, count 0 2006.257.20:39:24.73#ibcon#wrote, iclass 29, count 0 2006.257.20:39:24.73#ibcon#about to read 3, iclass 29, count 0 2006.257.20:39:24.76#ibcon#read 3, iclass 29, count 0 2006.257.20:39:24.76#ibcon#about to read 4, iclass 29, count 0 2006.257.20:39:24.76#ibcon#read 4, iclass 29, count 0 2006.257.20:39:24.76#ibcon#about to read 5, iclass 29, count 0 2006.257.20:39:24.76#ibcon#read 5, iclass 29, count 0 2006.257.20:39:24.76#ibcon#about to read 6, iclass 29, count 0 2006.257.20:39:24.76#ibcon#read 6, iclass 29, count 0 2006.257.20:39:24.76#ibcon#end of sib2, iclass 29, count 0 2006.257.20:39:24.76#ibcon#*after write, iclass 29, count 0 2006.257.20:39:24.76#ibcon#*before return 0, iclass 29, count 0 2006.257.20:39:24.76#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:24.76#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:39:24.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:39:24.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:39:24.76$vck44/vblo=3,649.99 2006.257.20:39:24.76#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.20:39:24.76#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.20:39:24.76#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:24.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:24.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:24.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:24.76#ibcon#enter wrdev, iclass 31, count 0 2006.257.20:39:24.76#ibcon#first serial, iclass 31, count 0 2006.257.20:39:24.76#ibcon#enter sib2, iclass 31, count 0 2006.257.20:39:24.76#ibcon#flushed, iclass 31, count 0 2006.257.20:39:24.76#ibcon#about to write, iclass 31, count 0 2006.257.20:39:24.76#ibcon#wrote, iclass 31, count 0 2006.257.20:39:24.76#ibcon#about to read 3, iclass 31, count 0 2006.257.20:39:24.78#ibcon#read 3, iclass 31, count 0 2006.257.20:39:24.78#ibcon#about to read 4, iclass 31, count 0 2006.257.20:39:24.78#ibcon#read 4, iclass 31, count 0 2006.257.20:39:24.78#ibcon#about to read 5, iclass 31, count 0 2006.257.20:39:24.78#ibcon#read 5, iclass 31, count 0 2006.257.20:39:24.78#ibcon#about to read 6, iclass 31, count 0 2006.257.20:39:24.78#ibcon#read 6, iclass 31, count 0 2006.257.20:39:24.78#ibcon#end of sib2, iclass 31, count 0 2006.257.20:39:24.78#ibcon#*mode == 0, iclass 31, count 0 2006.257.20:39:24.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.20:39:24.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.20:39:24.78#ibcon#*before write, iclass 31, count 0 2006.257.20:39:24.78#ibcon#enter sib2, iclass 31, count 0 2006.257.20:39:24.78#ibcon#flushed, iclass 31, count 0 2006.257.20:39:24.78#ibcon#about to write, iclass 31, count 0 2006.257.20:39:24.78#ibcon#wrote, iclass 31, count 0 2006.257.20:39:24.78#ibcon#about to read 3, iclass 31, count 0 2006.257.20:39:24.82#ibcon#read 3, iclass 31, count 0 2006.257.20:39:24.82#ibcon#about to read 4, iclass 31, count 0 2006.257.20:39:24.82#ibcon#read 4, iclass 31, count 0 2006.257.20:39:24.82#ibcon#about to read 5, iclass 31, count 0 2006.257.20:39:24.82#ibcon#read 5, iclass 31, count 0 2006.257.20:39:24.82#ibcon#about to read 6, iclass 31, count 0 2006.257.20:39:24.82#ibcon#read 6, iclass 31, count 0 2006.257.20:39:24.82#ibcon#end of sib2, iclass 31, count 0 2006.257.20:39:24.82#ibcon#*after write, iclass 31, count 0 2006.257.20:39:24.82#ibcon#*before return 0, iclass 31, count 0 2006.257.20:39:24.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:24.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:39:24.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.20:39:24.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.20:39:24.82$vck44/vb=3,4 2006.257.20:39:24.82#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.20:39:24.82#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.20:39:24.82#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:24.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:24.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:24.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:24.88#ibcon#enter wrdev, iclass 33, count 2 2006.257.20:39:24.88#ibcon#first serial, iclass 33, count 2 2006.257.20:39:24.88#ibcon#enter sib2, iclass 33, count 2 2006.257.20:39:24.88#ibcon#flushed, iclass 33, count 2 2006.257.20:39:24.88#ibcon#about to write, iclass 33, count 2 2006.257.20:39:24.88#ibcon#wrote, iclass 33, count 2 2006.257.20:39:24.88#ibcon#about to read 3, iclass 33, count 2 2006.257.20:39:24.90#ibcon#read 3, iclass 33, count 2 2006.257.20:39:24.90#ibcon#about to read 4, iclass 33, count 2 2006.257.20:39:24.90#ibcon#read 4, iclass 33, count 2 2006.257.20:39:24.90#ibcon#about to read 5, iclass 33, count 2 2006.257.20:39:24.90#ibcon#read 5, iclass 33, count 2 2006.257.20:39:24.90#ibcon#about to read 6, iclass 33, count 2 2006.257.20:39:24.90#ibcon#read 6, iclass 33, count 2 2006.257.20:39:24.90#ibcon#end of sib2, iclass 33, count 2 2006.257.20:39:24.90#ibcon#*mode == 0, iclass 33, count 2 2006.257.20:39:24.90#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.20:39:24.90#ibcon#[27=AT03-04\r\n] 2006.257.20:39:24.90#ibcon#*before write, iclass 33, count 2 2006.257.20:39:24.90#ibcon#enter sib2, iclass 33, count 2 2006.257.20:39:24.90#ibcon#flushed, iclass 33, count 2 2006.257.20:39:24.90#ibcon#about to write, iclass 33, count 2 2006.257.20:39:24.90#ibcon#wrote, iclass 33, count 2 2006.257.20:39:24.90#ibcon#about to read 3, iclass 33, count 2 2006.257.20:39:24.93#ibcon#read 3, iclass 33, count 2 2006.257.20:39:24.93#ibcon#about to read 4, iclass 33, count 2 2006.257.20:39:24.93#ibcon#read 4, iclass 33, count 2 2006.257.20:39:24.93#ibcon#about to read 5, iclass 33, count 2 2006.257.20:39:24.93#ibcon#read 5, iclass 33, count 2 2006.257.20:39:24.93#ibcon#about to read 6, iclass 33, count 2 2006.257.20:39:24.93#ibcon#read 6, iclass 33, count 2 2006.257.20:39:24.93#ibcon#end of sib2, iclass 33, count 2 2006.257.20:39:24.93#ibcon#*after write, iclass 33, count 2 2006.257.20:39:24.93#ibcon#*before return 0, iclass 33, count 2 2006.257.20:39:24.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:24.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:39:24.93#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.20:39:24.93#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:24.93#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:25.05#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:25.05#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:25.05#ibcon#enter wrdev, iclass 33, count 0 2006.257.20:39:25.05#ibcon#first serial, iclass 33, count 0 2006.257.20:39:25.05#ibcon#enter sib2, iclass 33, count 0 2006.257.20:39:25.05#ibcon#flushed, iclass 33, count 0 2006.257.20:39:25.05#ibcon#about to write, iclass 33, count 0 2006.257.20:39:25.05#ibcon#wrote, iclass 33, count 0 2006.257.20:39:25.05#ibcon#about to read 3, iclass 33, count 0 2006.257.20:39:25.07#ibcon#read 3, iclass 33, count 0 2006.257.20:39:25.07#ibcon#about to read 4, iclass 33, count 0 2006.257.20:39:25.07#ibcon#read 4, iclass 33, count 0 2006.257.20:39:25.07#ibcon#about to read 5, iclass 33, count 0 2006.257.20:39:25.07#ibcon#read 5, iclass 33, count 0 2006.257.20:39:25.07#ibcon#about to read 6, iclass 33, count 0 2006.257.20:39:25.07#ibcon#read 6, iclass 33, count 0 2006.257.20:39:25.07#ibcon#end of sib2, iclass 33, count 0 2006.257.20:39:25.07#ibcon#*mode == 0, iclass 33, count 0 2006.257.20:39:25.07#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.20:39:25.07#ibcon#[27=USB\r\n] 2006.257.20:39:25.07#ibcon#*before write, iclass 33, count 0 2006.257.20:39:25.07#ibcon#enter sib2, iclass 33, count 0 2006.257.20:39:25.07#ibcon#flushed, iclass 33, count 0 2006.257.20:39:25.07#ibcon#about to write, iclass 33, count 0 2006.257.20:39:25.07#ibcon#wrote, iclass 33, count 0 2006.257.20:39:25.07#ibcon#about to read 3, iclass 33, count 0 2006.257.20:39:25.10#ibcon#read 3, iclass 33, count 0 2006.257.20:39:25.10#ibcon#about to read 4, iclass 33, count 0 2006.257.20:39:25.10#ibcon#read 4, iclass 33, count 0 2006.257.20:39:25.10#ibcon#about to read 5, iclass 33, count 0 2006.257.20:39:25.10#ibcon#read 5, iclass 33, count 0 2006.257.20:39:25.10#ibcon#about to read 6, iclass 33, count 0 2006.257.20:39:25.10#ibcon#read 6, iclass 33, count 0 2006.257.20:39:25.10#ibcon#end of sib2, iclass 33, count 0 2006.257.20:39:25.10#ibcon#*after write, iclass 33, count 0 2006.257.20:39:25.10#ibcon#*before return 0, iclass 33, count 0 2006.257.20:39:25.10#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:25.10#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:39:25.10#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.20:39:25.10#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.20:39:25.10$vck44/vblo=4,679.99 2006.257.20:39:25.10#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.20:39:25.10#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.20:39:25.10#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:25.10#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:25.10#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:25.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:25.10#ibcon#enter wrdev, iclass 35, count 0 2006.257.20:39:25.10#ibcon#first serial, iclass 35, count 0 2006.257.20:39:25.10#ibcon#enter sib2, iclass 35, count 0 2006.257.20:39:25.10#ibcon#flushed, iclass 35, count 0 2006.257.20:39:25.10#ibcon#about to write, iclass 35, count 0 2006.257.20:39:25.10#ibcon#wrote, iclass 35, count 0 2006.257.20:39:25.10#ibcon#about to read 3, iclass 35, count 0 2006.257.20:39:25.12#ibcon#read 3, iclass 35, count 0 2006.257.20:39:25.12#ibcon#about to read 4, iclass 35, count 0 2006.257.20:39:25.12#ibcon#read 4, iclass 35, count 0 2006.257.20:39:25.12#ibcon#about to read 5, iclass 35, count 0 2006.257.20:39:25.12#ibcon#read 5, iclass 35, count 0 2006.257.20:39:25.12#ibcon#about to read 6, iclass 35, count 0 2006.257.20:39:25.12#ibcon#read 6, iclass 35, count 0 2006.257.20:39:25.12#ibcon#end of sib2, iclass 35, count 0 2006.257.20:39:25.12#ibcon#*mode == 0, iclass 35, count 0 2006.257.20:39:25.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.20:39:25.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.20:39:25.12#ibcon#*before write, iclass 35, count 0 2006.257.20:39:25.12#ibcon#enter sib2, iclass 35, count 0 2006.257.20:39:25.12#ibcon#flushed, iclass 35, count 0 2006.257.20:39:25.12#ibcon#about to write, iclass 35, count 0 2006.257.20:39:25.12#ibcon#wrote, iclass 35, count 0 2006.257.20:39:25.12#ibcon#about to read 3, iclass 35, count 0 2006.257.20:39:25.16#ibcon#read 3, iclass 35, count 0 2006.257.20:39:25.16#ibcon#about to read 4, iclass 35, count 0 2006.257.20:39:25.16#ibcon#read 4, iclass 35, count 0 2006.257.20:39:25.16#ibcon#about to read 5, iclass 35, count 0 2006.257.20:39:25.16#ibcon#read 5, iclass 35, count 0 2006.257.20:39:25.16#ibcon#about to read 6, iclass 35, count 0 2006.257.20:39:25.16#ibcon#read 6, iclass 35, count 0 2006.257.20:39:25.16#ibcon#end of sib2, iclass 35, count 0 2006.257.20:39:25.16#ibcon#*after write, iclass 35, count 0 2006.257.20:39:25.16#ibcon#*before return 0, iclass 35, count 0 2006.257.20:39:25.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:25.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:39:25.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.20:39:25.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.20:39:25.16$vck44/vb=4,5 2006.257.20:39:25.16#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.20:39:25.16#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.20:39:25.16#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:25.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:25.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:25.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:25.22#ibcon#enter wrdev, iclass 37, count 2 2006.257.20:39:25.22#ibcon#first serial, iclass 37, count 2 2006.257.20:39:25.22#ibcon#enter sib2, iclass 37, count 2 2006.257.20:39:25.22#ibcon#flushed, iclass 37, count 2 2006.257.20:39:25.22#ibcon#about to write, iclass 37, count 2 2006.257.20:39:25.22#ibcon#wrote, iclass 37, count 2 2006.257.20:39:25.22#ibcon#about to read 3, iclass 37, count 2 2006.257.20:39:25.24#ibcon#read 3, iclass 37, count 2 2006.257.20:39:25.24#ibcon#about to read 4, iclass 37, count 2 2006.257.20:39:25.24#ibcon#read 4, iclass 37, count 2 2006.257.20:39:25.24#ibcon#about to read 5, iclass 37, count 2 2006.257.20:39:25.24#ibcon#read 5, iclass 37, count 2 2006.257.20:39:25.24#ibcon#about to read 6, iclass 37, count 2 2006.257.20:39:25.24#ibcon#read 6, iclass 37, count 2 2006.257.20:39:25.24#ibcon#end of sib2, iclass 37, count 2 2006.257.20:39:25.24#ibcon#*mode == 0, iclass 37, count 2 2006.257.20:39:25.24#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.20:39:25.24#ibcon#[27=AT04-05\r\n] 2006.257.20:39:25.24#ibcon#*before write, iclass 37, count 2 2006.257.20:39:25.24#ibcon#enter sib2, iclass 37, count 2 2006.257.20:39:25.24#ibcon#flushed, iclass 37, count 2 2006.257.20:39:25.24#ibcon#about to write, iclass 37, count 2 2006.257.20:39:25.24#ibcon#wrote, iclass 37, count 2 2006.257.20:39:25.24#ibcon#about to read 3, iclass 37, count 2 2006.257.20:39:25.27#ibcon#read 3, iclass 37, count 2 2006.257.20:39:25.27#ibcon#about to read 4, iclass 37, count 2 2006.257.20:39:25.27#ibcon#read 4, iclass 37, count 2 2006.257.20:39:25.27#ibcon#about to read 5, iclass 37, count 2 2006.257.20:39:25.27#ibcon#read 5, iclass 37, count 2 2006.257.20:39:25.27#ibcon#about to read 6, iclass 37, count 2 2006.257.20:39:25.27#ibcon#read 6, iclass 37, count 2 2006.257.20:39:25.27#ibcon#end of sib2, iclass 37, count 2 2006.257.20:39:25.27#ibcon#*after write, iclass 37, count 2 2006.257.20:39:25.27#ibcon#*before return 0, iclass 37, count 2 2006.257.20:39:25.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:25.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:39:25.27#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.20:39:25.27#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:25.27#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:25.39#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:25.39#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:25.39#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:39:25.39#ibcon#first serial, iclass 37, count 0 2006.257.20:39:25.39#ibcon#enter sib2, iclass 37, count 0 2006.257.20:39:25.39#ibcon#flushed, iclass 37, count 0 2006.257.20:39:25.39#ibcon#about to write, iclass 37, count 0 2006.257.20:39:25.39#ibcon#wrote, iclass 37, count 0 2006.257.20:39:25.39#ibcon#about to read 3, iclass 37, count 0 2006.257.20:39:25.41#ibcon#read 3, iclass 37, count 0 2006.257.20:39:25.41#ibcon#about to read 4, iclass 37, count 0 2006.257.20:39:25.41#ibcon#read 4, iclass 37, count 0 2006.257.20:39:25.41#ibcon#about to read 5, iclass 37, count 0 2006.257.20:39:25.41#ibcon#read 5, iclass 37, count 0 2006.257.20:39:25.41#ibcon#about to read 6, iclass 37, count 0 2006.257.20:39:25.41#ibcon#read 6, iclass 37, count 0 2006.257.20:39:25.41#ibcon#end of sib2, iclass 37, count 0 2006.257.20:39:25.41#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:39:25.41#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:39:25.41#ibcon#[27=USB\r\n] 2006.257.20:39:25.41#ibcon#*before write, iclass 37, count 0 2006.257.20:39:25.41#ibcon#enter sib2, iclass 37, count 0 2006.257.20:39:25.41#ibcon#flushed, iclass 37, count 0 2006.257.20:39:25.41#ibcon#about to write, iclass 37, count 0 2006.257.20:39:25.41#ibcon#wrote, iclass 37, count 0 2006.257.20:39:25.41#ibcon#about to read 3, iclass 37, count 0 2006.257.20:39:25.44#ibcon#read 3, iclass 37, count 0 2006.257.20:39:25.44#ibcon#about to read 4, iclass 37, count 0 2006.257.20:39:25.44#ibcon#read 4, iclass 37, count 0 2006.257.20:39:25.44#ibcon#about to read 5, iclass 37, count 0 2006.257.20:39:25.44#ibcon#read 5, iclass 37, count 0 2006.257.20:39:25.44#ibcon#about to read 6, iclass 37, count 0 2006.257.20:39:25.44#ibcon#read 6, iclass 37, count 0 2006.257.20:39:25.44#ibcon#end of sib2, iclass 37, count 0 2006.257.20:39:25.44#ibcon#*after write, iclass 37, count 0 2006.257.20:39:25.44#ibcon#*before return 0, iclass 37, count 0 2006.257.20:39:25.44#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:25.44#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:39:25.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:39:25.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:39:25.44$vck44/vblo=5,709.99 2006.257.20:39:25.44#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.20:39:25.44#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.20:39:25.44#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:25.44#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:25.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:25.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:25.44#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:39:25.44#ibcon#first serial, iclass 39, count 0 2006.257.20:39:25.44#ibcon#enter sib2, iclass 39, count 0 2006.257.20:39:25.44#ibcon#flushed, iclass 39, count 0 2006.257.20:39:25.44#ibcon#about to write, iclass 39, count 0 2006.257.20:39:25.44#ibcon#wrote, iclass 39, count 0 2006.257.20:39:25.44#ibcon#about to read 3, iclass 39, count 0 2006.257.20:39:25.46#ibcon#read 3, iclass 39, count 0 2006.257.20:39:25.46#ibcon#about to read 4, iclass 39, count 0 2006.257.20:39:25.46#ibcon#read 4, iclass 39, count 0 2006.257.20:39:25.46#ibcon#about to read 5, iclass 39, count 0 2006.257.20:39:25.46#ibcon#read 5, iclass 39, count 0 2006.257.20:39:25.46#ibcon#about to read 6, iclass 39, count 0 2006.257.20:39:25.46#ibcon#read 6, iclass 39, count 0 2006.257.20:39:25.46#ibcon#end of sib2, iclass 39, count 0 2006.257.20:39:25.46#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:39:25.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:39:25.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.20:39:25.46#ibcon#*before write, iclass 39, count 0 2006.257.20:39:25.46#ibcon#enter sib2, iclass 39, count 0 2006.257.20:39:25.46#ibcon#flushed, iclass 39, count 0 2006.257.20:39:25.46#ibcon#about to write, iclass 39, count 0 2006.257.20:39:25.46#ibcon#wrote, iclass 39, count 0 2006.257.20:39:25.46#ibcon#about to read 3, iclass 39, count 0 2006.257.20:39:25.50#ibcon#read 3, iclass 39, count 0 2006.257.20:39:25.50#ibcon#about to read 4, iclass 39, count 0 2006.257.20:39:25.50#ibcon#read 4, iclass 39, count 0 2006.257.20:39:25.50#ibcon#about to read 5, iclass 39, count 0 2006.257.20:39:25.50#ibcon#read 5, iclass 39, count 0 2006.257.20:39:25.50#ibcon#about to read 6, iclass 39, count 0 2006.257.20:39:25.50#ibcon#read 6, iclass 39, count 0 2006.257.20:39:25.50#ibcon#end of sib2, iclass 39, count 0 2006.257.20:39:25.50#ibcon#*after write, iclass 39, count 0 2006.257.20:39:25.50#ibcon#*before return 0, iclass 39, count 0 2006.257.20:39:25.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:25.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:39:25.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:39:25.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:39:25.50$vck44/vb=5,4 2006.257.20:39:25.50#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.20:39:25.50#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.20:39:25.50#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:25.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:25.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:25.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:25.56#ibcon#enter wrdev, iclass 3, count 2 2006.257.20:39:25.56#ibcon#first serial, iclass 3, count 2 2006.257.20:39:25.56#ibcon#enter sib2, iclass 3, count 2 2006.257.20:39:25.56#ibcon#flushed, iclass 3, count 2 2006.257.20:39:25.56#ibcon#about to write, iclass 3, count 2 2006.257.20:39:25.56#ibcon#wrote, iclass 3, count 2 2006.257.20:39:25.56#ibcon#about to read 3, iclass 3, count 2 2006.257.20:39:25.58#ibcon#read 3, iclass 3, count 2 2006.257.20:39:25.58#ibcon#about to read 4, iclass 3, count 2 2006.257.20:39:25.58#ibcon#read 4, iclass 3, count 2 2006.257.20:39:25.58#ibcon#about to read 5, iclass 3, count 2 2006.257.20:39:25.58#ibcon#read 5, iclass 3, count 2 2006.257.20:39:25.58#ibcon#about to read 6, iclass 3, count 2 2006.257.20:39:25.58#ibcon#read 6, iclass 3, count 2 2006.257.20:39:25.58#ibcon#end of sib2, iclass 3, count 2 2006.257.20:39:25.58#ibcon#*mode == 0, iclass 3, count 2 2006.257.20:39:25.58#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.20:39:25.58#ibcon#[27=AT05-04\r\n] 2006.257.20:39:25.58#ibcon#*before write, iclass 3, count 2 2006.257.20:39:25.58#ibcon#enter sib2, iclass 3, count 2 2006.257.20:39:25.58#ibcon#flushed, iclass 3, count 2 2006.257.20:39:25.58#ibcon#about to write, iclass 3, count 2 2006.257.20:39:25.58#ibcon#wrote, iclass 3, count 2 2006.257.20:39:25.58#ibcon#about to read 3, iclass 3, count 2 2006.257.20:39:25.61#ibcon#read 3, iclass 3, count 2 2006.257.20:39:25.61#ibcon#about to read 4, iclass 3, count 2 2006.257.20:39:25.61#ibcon#read 4, iclass 3, count 2 2006.257.20:39:25.61#ibcon#about to read 5, iclass 3, count 2 2006.257.20:39:25.61#ibcon#read 5, iclass 3, count 2 2006.257.20:39:25.61#ibcon#about to read 6, iclass 3, count 2 2006.257.20:39:25.61#ibcon#read 6, iclass 3, count 2 2006.257.20:39:25.61#ibcon#end of sib2, iclass 3, count 2 2006.257.20:39:25.61#ibcon#*after write, iclass 3, count 2 2006.257.20:39:25.61#ibcon#*before return 0, iclass 3, count 2 2006.257.20:39:25.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:25.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:39:25.61#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.20:39:25.61#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:25.61#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:25.73#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:25.73#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:25.73#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:39:25.73#ibcon#first serial, iclass 3, count 0 2006.257.20:39:25.73#ibcon#enter sib2, iclass 3, count 0 2006.257.20:39:25.73#ibcon#flushed, iclass 3, count 0 2006.257.20:39:25.73#ibcon#about to write, iclass 3, count 0 2006.257.20:39:25.73#ibcon#wrote, iclass 3, count 0 2006.257.20:39:25.73#ibcon#about to read 3, iclass 3, count 0 2006.257.20:39:25.75#ibcon#read 3, iclass 3, count 0 2006.257.20:39:25.75#ibcon#about to read 4, iclass 3, count 0 2006.257.20:39:25.75#ibcon#read 4, iclass 3, count 0 2006.257.20:39:25.75#ibcon#about to read 5, iclass 3, count 0 2006.257.20:39:25.75#ibcon#read 5, iclass 3, count 0 2006.257.20:39:25.75#ibcon#about to read 6, iclass 3, count 0 2006.257.20:39:25.75#ibcon#read 6, iclass 3, count 0 2006.257.20:39:25.75#ibcon#end of sib2, iclass 3, count 0 2006.257.20:39:25.75#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:39:25.75#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:39:25.75#ibcon#[27=USB\r\n] 2006.257.20:39:25.75#ibcon#*before write, iclass 3, count 0 2006.257.20:39:25.75#ibcon#enter sib2, iclass 3, count 0 2006.257.20:39:25.75#ibcon#flushed, iclass 3, count 0 2006.257.20:39:25.75#ibcon#about to write, iclass 3, count 0 2006.257.20:39:25.75#ibcon#wrote, iclass 3, count 0 2006.257.20:39:25.75#ibcon#about to read 3, iclass 3, count 0 2006.257.20:39:25.75#abcon#<5=/14 0.7 3.3 17.13 981014.9\r\n> 2006.257.20:39:25.77#abcon#{5=INTERFACE CLEAR} 2006.257.20:39:25.78#ibcon#read 3, iclass 3, count 0 2006.257.20:39:25.78#ibcon#about to read 4, iclass 3, count 0 2006.257.20:39:25.78#ibcon#read 4, iclass 3, count 0 2006.257.20:39:25.78#ibcon#about to read 5, iclass 3, count 0 2006.257.20:39:25.78#ibcon#read 5, iclass 3, count 0 2006.257.20:39:25.78#ibcon#about to read 6, iclass 3, count 0 2006.257.20:39:25.78#ibcon#read 6, iclass 3, count 0 2006.257.20:39:25.78#ibcon#end of sib2, iclass 3, count 0 2006.257.20:39:25.78#ibcon#*after write, iclass 3, count 0 2006.257.20:39:25.78#ibcon#*before return 0, iclass 3, count 0 2006.257.20:39:25.78#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:25.78#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:39:25.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:39:25.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:39:25.78$vck44/vblo=6,719.99 2006.257.20:39:25.78#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.20:39:25.78#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.20:39:25.78#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:25.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:39:25.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:39:25.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:39:25.78#ibcon#enter wrdev, iclass 10, count 0 2006.257.20:39:25.78#ibcon#first serial, iclass 10, count 0 2006.257.20:39:25.78#ibcon#enter sib2, iclass 10, count 0 2006.257.20:39:25.78#ibcon#flushed, iclass 10, count 0 2006.257.20:39:25.78#ibcon#about to write, iclass 10, count 0 2006.257.20:39:25.78#ibcon#wrote, iclass 10, count 0 2006.257.20:39:25.78#ibcon#about to read 3, iclass 10, count 0 2006.257.20:39:25.80#ibcon#read 3, iclass 10, count 0 2006.257.20:39:25.80#ibcon#about to read 4, iclass 10, count 0 2006.257.20:39:25.80#ibcon#read 4, iclass 10, count 0 2006.257.20:39:25.80#ibcon#about to read 5, iclass 10, count 0 2006.257.20:39:25.80#ibcon#read 5, iclass 10, count 0 2006.257.20:39:25.80#ibcon#about to read 6, iclass 10, count 0 2006.257.20:39:25.80#ibcon#read 6, iclass 10, count 0 2006.257.20:39:25.80#ibcon#end of sib2, iclass 10, count 0 2006.257.20:39:25.80#ibcon#*mode == 0, iclass 10, count 0 2006.257.20:39:25.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.20:39:25.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.20:39:25.80#ibcon#*before write, iclass 10, count 0 2006.257.20:39:25.80#ibcon#enter sib2, iclass 10, count 0 2006.257.20:39:25.80#ibcon#flushed, iclass 10, count 0 2006.257.20:39:25.80#ibcon#about to write, iclass 10, count 0 2006.257.20:39:25.80#ibcon#wrote, iclass 10, count 0 2006.257.20:39:25.80#ibcon#about to read 3, iclass 10, count 0 2006.257.20:39:25.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:39:25.84#ibcon#read 3, iclass 10, count 0 2006.257.20:39:25.84#ibcon#about to read 4, iclass 10, count 0 2006.257.20:39:25.84#ibcon#read 4, iclass 10, count 0 2006.257.20:39:25.84#ibcon#about to read 5, iclass 10, count 0 2006.257.20:39:25.84#ibcon#read 5, iclass 10, count 0 2006.257.20:39:25.84#ibcon#about to read 6, iclass 10, count 0 2006.257.20:39:25.84#ibcon#read 6, iclass 10, count 0 2006.257.20:39:25.84#ibcon#end of sib2, iclass 10, count 0 2006.257.20:39:25.84#ibcon#*after write, iclass 10, count 0 2006.257.20:39:25.84#ibcon#*before return 0, iclass 10, count 0 2006.257.20:39:25.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:39:25.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:39:25.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.20:39:25.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.20:39:25.84$vck44/vb=6,4 2006.257.20:39:25.84#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.20:39:25.84#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.20:39:25.84#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:25.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:25.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:25.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:25.90#ibcon#enter wrdev, iclass 13, count 2 2006.257.20:39:25.90#ibcon#first serial, iclass 13, count 2 2006.257.20:39:25.90#ibcon#enter sib2, iclass 13, count 2 2006.257.20:39:25.90#ibcon#flushed, iclass 13, count 2 2006.257.20:39:25.90#ibcon#about to write, iclass 13, count 2 2006.257.20:39:25.90#ibcon#wrote, iclass 13, count 2 2006.257.20:39:25.90#ibcon#about to read 3, iclass 13, count 2 2006.257.20:39:25.92#ibcon#read 3, iclass 13, count 2 2006.257.20:39:25.92#ibcon#about to read 4, iclass 13, count 2 2006.257.20:39:25.92#ibcon#read 4, iclass 13, count 2 2006.257.20:39:25.92#ibcon#about to read 5, iclass 13, count 2 2006.257.20:39:25.92#ibcon#read 5, iclass 13, count 2 2006.257.20:39:25.92#ibcon#about to read 6, iclass 13, count 2 2006.257.20:39:25.92#ibcon#read 6, iclass 13, count 2 2006.257.20:39:25.92#ibcon#end of sib2, iclass 13, count 2 2006.257.20:39:25.92#ibcon#*mode == 0, iclass 13, count 2 2006.257.20:39:25.92#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.20:39:25.92#ibcon#[27=AT06-04\r\n] 2006.257.20:39:25.92#ibcon#*before write, iclass 13, count 2 2006.257.20:39:25.92#ibcon#enter sib2, iclass 13, count 2 2006.257.20:39:25.92#ibcon#flushed, iclass 13, count 2 2006.257.20:39:25.92#ibcon#about to write, iclass 13, count 2 2006.257.20:39:25.92#ibcon#wrote, iclass 13, count 2 2006.257.20:39:25.92#ibcon#about to read 3, iclass 13, count 2 2006.257.20:39:25.95#ibcon#read 3, iclass 13, count 2 2006.257.20:39:25.95#ibcon#about to read 4, iclass 13, count 2 2006.257.20:39:25.95#ibcon#read 4, iclass 13, count 2 2006.257.20:39:25.95#ibcon#about to read 5, iclass 13, count 2 2006.257.20:39:25.95#ibcon#read 5, iclass 13, count 2 2006.257.20:39:25.95#ibcon#about to read 6, iclass 13, count 2 2006.257.20:39:25.95#ibcon#read 6, iclass 13, count 2 2006.257.20:39:25.95#ibcon#end of sib2, iclass 13, count 2 2006.257.20:39:25.95#ibcon#*after write, iclass 13, count 2 2006.257.20:39:25.95#ibcon#*before return 0, iclass 13, count 2 2006.257.20:39:25.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:25.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:39:25.95#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.20:39:25.95#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:25.95#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:26.07#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:26.07#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:26.07#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:39:26.07#ibcon#first serial, iclass 13, count 0 2006.257.20:39:26.07#ibcon#enter sib2, iclass 13, count 0 2006.257.20:39:26.07#ibcon#flushed, iclass 13, count 0 2006.257.20:39:26.07#ibcon#about to write, iclass 13, count 0 2006.257.20:39:26.07#ibcon#wrote, iclass 13, count 0 2006.257.20:39:26.07#ibcon#about to read 3, iclass 13, count 0 2006.257.20:39:26.09#ibcon#read 3, iclass 13, count 0 2006.257.20:39:26.09#ibcon#about to read 4, iclass 13, count 0 2006.257.20:39:26.09#ibcon#read 4, iclass 13, count 0 2006.257.20:39:26.09#ibcon#about to read 5, iclass 13, count 0 2006.257.20:39:26.09#ibcon#read 5, iclass 13, count 0 2006.257.20:39:26.09#ibcon#about to read 6, iclass 13, count 0 2006.257.20:39:26.09#ibcon#read 6, iclass 13, count 0 2006.257.20:39:26.09#ibcon#end of sib2, iclass 13, count 0 2006.257.20:39:26.09#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:39:26.09#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:39:26.09#ibcon#[27=USB\r\n] 2006.257.20:39:26.09#ibcon#*before write, iclass 13, count 0 2006.257.20:39:26.09#ibcon#enter sib2, iclass 13, count 0 2006.257.20:39:26.09#ibcon#flushed, iclass 13, count 0 2006.257.20:39:26.09#ibcon#about to write, iclass 13, count 0 2006.257.20:39:26.09#ibcon#wrote, iclass 13, count 0 2006.257.20:39:26.09#ibcon#about to read 3, iclass 13, count 0 2006.257.20:39:26.12#ibcon#read 3, iclass 13, count 0 2006.257.20:39:26.12#ibcon#about to read 4, iclass 13, count 0 2006.257.20:39:26.12#ibcon#read 4, iclass 13, count 0 2006.257.20:39:26.12#ibcon#about to read 5, iclass 13, count 0 2006.257.20:39:26.12#ibcon#read 5, iclass 13, count 0 2006.257.20:39:26.12#ibcon#about to read 6, iclass 13, count 0 2006.257.20:39:26.12#ibcon#read 6, iclass 13, count 0 2006.257.20:39:26.12#ibcon#end of sib2, iclass 13, count 0 2006.257.20:39:26.12#ibcon#*after write, iclass 13, count 0 2006.257.20:39:26.12#ibcon#*before return 0, iclass 13, count 0 2006.257.20:39:26.12#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:26.12#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:39:26.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:39:26.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:39:26.12$vck44/vblo=7,734.99 2006.257.20:39:26.12#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.20:39:26.12#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.20:39:26.12#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:26.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:26.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:26.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:26.12#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:39:26.12#ibcon#first serial, iclass 15, count 0 2006.257.20:39:26.12#ibcon#enter sib2, iclass 15, count 0 2006.257.20:39:26.12#ibcon#flushed, iclass 15, count 0 2006.257.20:39:26.12#ibcon#about to write, iclass 15, count 0 2006.257.20:39:26.12#ibcon#wrote, iclass 15, count 0 2006.257.20:39:26.12#ibcon#about to read 3, iclass 15, count 0 2006.257.20:39:26.14#ibcon#read 3, iclass 15, count 0 2006.257.20:39:26.14#ibcon#about to read 4, iclass 15, count 0 2006.257.20:39:26.14#ibcon#read 4, iclass 15, count 0 2006.257.20:39:26.14#ibcon#about to read 5, iclass 15, count 0 2006.257.20:39:26.14#ibcon#read 5, iclass 15, count 0 2006.257.20:39:26.14#ibcon#about to read 6, iclass 15, count 0 2006.257.20:39:26.14#ibcon#read 6, iclass 15, count 0 2006.257.20:39:26.14#ibcon#end of sib2, iclass 15, count 0 2006.257.20:39:26.14#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:39:26.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:39:26.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.20:39:26.14#ibcon#*before write, iclass 15, count 0 2006.257.20:39:26.14#ibcon#enter sib2, iclass 15, count 0 2006.257.20:39:26.14#ibcon#flushed, iclass 15, count 0 2006.257.20:39:26.14#ibcon#about to write, iclass 15, count 0 2006.257.20:39:26.14#ibcon#wrote, iclass 15, count 0 2006.257.20:39:26.14#ibcon#about to read 3, iclass 15, count 0 2006.257.20:39:26.18#ibcon#read 3, iclass 15, count 0 2006.257.20:39:26.18#ibcon#about to read 4, iclass 15, count 0 2006.257.20:39:26.18#ibcon#read 4, iclass 15, count 0 2006.257.20:39:26.18#ibcon#about to read 5, iclass 15, count 0 2006.257.20:39:26.18#ibcon#read 5, iclass 15, count 0 2006.257.20:39:26.18#ibcon#about to read 6, iclass 15, count 0 2006.257.20:39:26.18#ibcon#read 6, iclass 15, count 0 2006.257.20:39:26.18#ibcon#end of sib2, iclass 15, count 0 2006.257.20:39:26.18#ibcon#*after write, iclass 15, count 0 2006.257.20:39:26.18#ibcon#*before return 0, iclass 15, count 0 2006.257.20:39:26.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:26.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:39:26.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:39:26.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:39:26.18$vck44/vb=7,4 2006.257.20:39:26.18#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.20:39:26.18#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.20:39:26.18#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:26.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:26.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:26.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:26.24#ibcon#enter wrdev, iclass 17, count 2 2006.257.20:39:26.24#ibcon#first serial, iclass 17, count 2 2006.257.20:39:26.24#ibcon#enter sib2, iclass 17, count 2 2006.257.20:39:26.24#ibcon#flushed, iclass 17, count 2 2006.257.20:39:26.24#ibcon#about to write, iclass 17, count 2 2006.257.20:39:26.24#ibcon#wrote, iclass 17, count 2 2006.257.20:39:26.24#ibcon#about to read 3, iclass 17, count 2 2006.257.20:39:26.26#ibcon#read 3, iclass 17, count 2 2006.257.20:39:26.26#ibcon#about to read 4, iclass 17, count 2 2006.257.20:39:26.26#ibcon#read 4, iclass 17, count 2 2006.257.20:39:26.26#ibcon#about to read 5, iclass 17, count 2 2006.257.20:39:26.26#ibcon#read 5, iclass 17, count 2 2006.257.20:39:26.26#ibcon#about to read 6, iclass 17, count 2 2006.257.20:39:26.26#ibcon#read 6, iclass 17, count 2 2006.257.20:39:26.26#ibcon#end of sib2, iclass 17, count 2 2006.257.20:39:26.26#ibcon#*mode == 0, iclass 17, count 2 2006.257.20:39:26.26#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.20:39:26.26#ibcon#[27=AT07-04\r\n] 2006.257.20:39:26.26#ibcon#*before write, iclass 17, count 2 2006.257.20:39:26.26#ibcon#enter sib2, iclass 17, count 2 2006.257.20:39:26.26#ibcon#flushed, iclass 17, count 2 2006.257.20:39:26.26#ibcon#about to write, iclass 17, count 2 2006.257.20:39:26.26#ibcon#wrote, iclass 17, count 2 2006.257.20:39:26.26#ibcon#about to read 3, iclass 17, count 2 2006.257.20:39:26.29#ibcon#read 3, iclass 17, count 2 2006.257.20:39:26.29#ibcon#about to read 4, iclass 17, count 2 2006.257.20:39:26.29#ibcon#read 4, iclass 17, count 2 2006.257.20:39:26.29#ibcon#about to read 5, iclass 17, count 2 2006.257.20:39:26.29#ibcon#read 5, iclass 17, count 2 2006.257.20:39:26.29#ibcon#about to read 6, iclass 17, count 2 2006.257.20:39:26.29#ibcon#read 6, iclass 17, count 2 2006.257.20:39:26.29#ibcon#end of sib2, iclass 17, count 2 2006.257.20:39:26.29#ibcon#*after write, iclass 17, count 2 2006.257.20:39:26.29#ibcon#*before return 0, iclass 17, count 2 2006.257.20:39:26.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:26.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:39:26.29#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.20:39:26.29#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:26.29#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:26.41#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:26.41#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:26.41#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:39:26.41#ibcon#first serial, iclass 17, count 0 2006.257.20:39:26.41#ibcon#enter sib2, iclass 17, count 0 2006.257.20:39:26.41#ibcon#flushed, iclass 17, count 0 2006.257.20:39:26.41#ibcon#about to write, iclass 17, count 0 2006.257.20:39:26.41#ibcon#wrote, iclass 17, count 0 2006.257.20:39:26.41#ibcon#about to read 3, iclass 17, count 0 2006.257.20:39:26.43#ibcon#read 3, iclass 17, count 0 2006.257.20:39:26.43#ibcon#about to read 4, iclass 17, count 0 2006.257.20:39:26.43#ibcon#read 4, iclass 17, count 0 2006.257.20:39:26.43#ibcon#about to read 5, iclass 17, count 0 2006.257.20:39:26.43#ibcon#read 5, iclass 17, count 0 2006.257.20:39:26.43#ibcon#about to read 6, iclass 17, count 0 2006.257.20:39:26.43#ibcon#read 6, iclass 17, count 0 2006.257.20:39:26.43#ibcon#end of sib2, iclass 17, count 0 2006.257.20:39:26.43#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:39:26.43#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:39:26.43#ibcon#[27=USB\r\n] 2006.257.20:39:26.43#ibcon#*before write, iclass 17, count 0 2006.257.20:39:26.43#ibcon#enter sib2, iclass 17, count 0 2006.257.20:39:26.43#ibcon#flushed, iclass 17, count 0 2006.257.20:39:26.43#ibcon#about to write, iclass 17, count 0 2006.257.20:39:26.43#ibcon#wrote, iclass 17, count 0 2006.257.20:39:26.43#ibcon#about to read 3, iclass 17, count 0 2006.257.20:39:26.46#ibcon#read 3, iclass 17, count 0 2006.257.20:39:26.46#ibcon#about to read 4, iclass 17, count 0 2006.257.20:39:26.46#ibcon#read 4, iclass 17, count 0 2006.257.20:39:26.46#ibcon#about to read 5, iclass 17, count 0 2006.257.20:39:26.46#ibcon#read 5, iclass 17, count 0 2006.257.20:39:26.46#ibcon#about to read 6, iclass 17, count 0 2006.257.20:39:26.46#ibcon#read 6, iclass 17, count 0 2006.257.20:39:26.46#ibcon#end of sib2, iclass 17, count 0 2006.257.20:39:26.46#ibcon#*after write, iclass 17, count 0 2006.257.20:39:26.46#ibcon#*before return 0, iclass 17, count 0 2006.257.20:39:26.46#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:26.46#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:39:26.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:39:26.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:39:26.46$vck44/vblo=8,744.99 2006.257.20:39:26.46#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.20:39:26.46#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.20:39:26.46#ibcon#ireg 17 cls_cnt 0 2006.257.20:39:26.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:26.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:26.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:26.46#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:39:26.46#ibcon#first serial, iclass 19, count 0 2006.257.20:39:26.46#ibcon#enter sib2, iclass 19, count 0 2006.257.20:39:26.46#ibcon#flushed, iclass 19, count 0 2006.257.20:39:26.46#ibcon#about to write, iclass 19, count 0 2006.257.20:39:26.46#ibcon#wrote, iclass 19, count 0 2006.257.20:39:26.46#ibcon#about to read 3, iclass 19, count 0 2006.257.20:39:26.48#ibcon#read 3, iclass 19, count 0 2006.257.20:39:26.48#ibcon#about to read 4, iclass 19, count 0 2006.257.20:39:26.48#ibcon#read 4, iclass 19, count 0 2006.257.20:39:26.48#ibcon#about to read 5, iclass 19, count 0 2006.257.20:39:26.48#ibcon#read 5, iclass 19, count 0 2006.257.20:39:26.48#ibcon#about to read 6, iclass 19, count 0 2006.257.20:39:26.48#ibcon#read 6, iclass 19, count 0 2006.257.20:39:26.48#ibcon#end of sib2, iclass 19, count 0 2006.257.20:39:26.48#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:39:26.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:39:26.48#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.20:39:26.48#ibcon#*before write, iclass 19, count 0 2006.257.20:39:26.48#ibcon#enter sib2, iclass 19, count 0 2006.257.20:39:26.48#ibcon#flushed, iclass 19, count 0 2006.257.20:39:26.48#ibcon#about to write, iclass 19, count 0 2006.257.20:39:26.48#ibcon#wrote, iclass 19, count 0 2006.257.20:39:26.48#ibcon#about to read 3, iclass 19, count 0 2006.257.20:39:26.52#ibcon#read 3, iclass 19, count 0 2006.257.20:39:26.52#ibcon#about to read 4, iclass 19, count 0 2006.257.20:39:26.52#ibcon#read 4, iclass 19, count 0 2006.257.20:39:26.52#ibcon#about to read 5, iclass 19, count 0 2006.257.20:39:26.52#ibcon#read 5, iclass 19, count 0 2006.257.20:39:26.52#ibcon#about to read 6, iclass 19, count 0 2006.257.20:39:26.52#ibcon#read 6, iclass 19, count 0 2006.257.20:39:26.52#ibcon#end of sib2, iclass 19, count 0 2006.257.20:39:26.52#ibcon#*after write, iclass 19, count 0 2006.257.20:39:26.52#ibcon#*before return 0, iclass 19, count 0 2006.257.20:39:26.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:26.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:39:26.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:39:26.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:39:26.52$vck44/vb=8,4 2006.257.20:39:26.52#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.20:39:26.52#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.20:39:26.52#ibcon#ireg 11 cls_cnt 2 2006.257.20:39:26.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:26.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:26.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:26.58#ibcon#enter wrdev, iclass 21, count 2 2006.257.20:39:26.58#ibcon#first serial, iclass 21, count 2 2006.257.20:39:26.58#ibcon#enter sib2, iclass 21, count 2 2006.257.20:39:26.58#ibcon#flushed, iclass 21, count 2 2006.257.20:39:26.58#ibcon#about to write, iclass 21, count 2 2006.257.20:39:26.58#ibcon#wrote, iclass 21, count 2 2006.257.20:39:26.58#ibcon#about to read 3, iclass 21, count 2 2006.257.20:39:26.60#ibcon#read 3, iclass 21, count 2 2006.257.20:39:26.60#ibcon#about to read 4, iclass 21, count 2 2006.257.20:39:26.60#ibcon#read 4, iclass 21, count 2 2006.257.20:39:26.60#ibcon#about to read 5, iclass 21, count 2 2006.257.20:39:26.60#ibcon#read 5, iclass 21, count 2 2006.257.20:39:26.60#ibcon#about to read 6, iclass 21, count 2 2006.257.20:39:26.60#ibcon#read 6, iclass 21, count 2 2006.257.20:39:26.60#ibcon#end of sib2, iclass 21, count 2 2006.257.20:39:26.60#ibcon#*mode == 0, iclass 21, count 2 2006.257.20:39:26.60#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.20:39:26.60#ibcon#[27=AT08-04\r\n] 2006.257.20:39:26.60#ibcon#*before write, iclass 21, count 2 2006.257.20:39:26.60#ibcon#enter sib2, iclass 21, count 2 2006.257.20:39:26.60#ibcon#flushed, iclass 21, count 2 2006.257.20:39:26.60#ibcon#about to write, iclass 21, count 2 2006.257.20:39:26.60#ibcon#wrote, iclass 21, count 2 2006.257.20:39:26.60#ibcon#about to read 3, iclass 21, count 2 2006.257.20:39:26.63#ibcon#read 3, iclass 21, count 2 2006.257.20:39:26.63#ibcon#about to read 4, iclass 21, count 2 2006.257.20:39:26.63#ibcon#read 4, iclass 21, count 2 2006.257.20:39:26.63#ibcon#about to read 5, iclass 21, count 2 2006.257.20:39:26.63#ibcon#read 5, iclass 21, count 2 2006.257.20:39:26.63#ibcon#about to read 6, iclass 21, count 2 2006.257.20:39:26.63#ibcon#read 6, iclass 21, count 2 2006.257.20:39:26.63#ibcon#end of sib2, iclass 21, count 2 2006.257.20:39:26.63#ibcon#*after write, iclass 21, count 2 2006.257.20:39:26.63#ibcon#*before return 0, iclass 21, count 2 2006.257.20:39:26.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:26.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:39:26.63#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.20:39:26.63#ibcon#ireg 7 cls_cnt 0 2006.257.20:39:26.63#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:26.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:26.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:26.75#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:39:26.75#ibcon#first serial, iclass 21, count 0 2006.257.20:39:26.75#ibcon#enter sib2, iclass 21, count 0 2006.257.20:39:26.75#ibcon#flushed, iclass 21, count 0 2006.257.20:39:26.75#ibcon#about to write, iclass 21, count 0 2006.257.20:39:26.75#ibcon#wrote, iclass 21, count 0 2006.257.20:39:26.75#ibcon#about to read 3, iclass 21, count 0 2006.257.20:39:26.77#ibcon#read 3, iclass 21, count 0 2006.257.20:39:26.77#ibcon#about to read 4, iclass 21, count 0 2006.257.20:39:26.77#ibcon#read 4, iclass 21, count 0 2006.257.20:39:26.77#ibcon#about to read 5, iclass 21, count 0 2006.257.20:39:26.77#ibcon#read 5, iclass 21, count 0 2006.257.20:39:26.77#ibcon#about to read 6, iclass 21, count 0 2006.257.20:39:26.77#ibcon#read 6, iclass 21, count 0 2006.257.20:39:26.77#ibcon#end of sib2, iclass 21, count 0 2006.257.20:39:26.77#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:39:26.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:39:26.77#ibcon#[27=USB\r\n] 2006.257.20:39:26.77#ibcon#*before write, iclass 21, count 0 2006.257.20:39:26.77#ibcon#enter sib2, iclass 21, count 0 2006.257.20:39:26.77#ibcon#flushed, iclass 21, count 0 2006.257.20:39:26.77#ibcon#about to write, iclass 21, count 0 2006.257.20:39:26.77#ibcon#wrote, iclass 21, count 0 2006.257.20:39:26.77#ibcon#about to read 3, iclass 21, count 0 2006.257.20:39:26.80#ibcon#read 3, iclass 21, count 0 2006.257.20:39:26.80#ibcon#about to read 4, iclass 21, count 0 2006.257.20:39:26.80#ibcon#read 4, iclass 21, count 0 2006.257.20:39:26.80#ibcon#about to read 5, iclass 21, count 0 2006.257.20:39:26.80#ibcon#read 5, iclass 21, count 0 2006.257.20:39:26.80#ibcon#about to read 6, iclass 21, count 0 2006.257.20:39:26.80#ibcon#read 6, iclass 21, count 0 2006.257.20:39:26.80#ibcon#end of sib2, iclass 21, count 0 2006.257.20:39:26.80#ibcon#*after write, iclass 21, count 0 2006.257.20:39:26.80#ibcon#*before return 0, iclass 21, count 0 2006.257.20:39:26.80#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:26.80#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:39:26.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:39:26.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:39:26.80$vck44/vabw=wide 2006.257.20:39:26.80#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.20:39:26.80#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.20:39:26.80#ibcon#ireg 8 cls_cnt 0 2006.257.20:39:26.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:26.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:26.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:26.80#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:39:26.80#ibcon#first serial, iclass 23, count 0 2006.257.20:39:26.80#ibcon#enter sib2, iclass 23, count 0 2006.257.20:39:26.80#ibcon#flushed, iclass 23, count 0 2006.257.20:39:26.80#ibcon#about to write, iclass 23, count 0 2006.257.20:39:26.80#ibcon#wrote, iclass 23, count 0 2006.257.20:39:26.80#ibcon#about to read 3, iclass 23, count 0 2006.257.20:39:26.82#ibcon#read 3, iclass 23, count 0 2006.257.20:39:26.82#ibcon#about to read 4, iclass 23, count 0 2006.257.20:39:26.82#ibcon#read 4, iclass 23, count 0 2006.257.20:39:26.82#ibcon#about to read 5, iclass 23, count 0 2006.257.20:39:26.82#ibcon#read 5, iclass 23, count 0 2006.257.20:39:26.82#ibcon#about to read 6, iclass 23, count 0 2006.257.20:39:26.82#ibcon#read 6, iclass 23, count 0 2006.257.20:39:26.82#ibcon#end of sib2, iclass 23, count 0 2006.257.20:39:26.82#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:39:26.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:39:26.82#ibcon#[25=BW32\r\n] 2006.257.20:39:26.82#ibcon#*before write, iclass 23, count 0 2006.257.20:39:26.82#ibcon#enter sib2, iclass 23, count 0 2006.257.20:39:26.82#ibcon#flushed, iclass 23, count 0 2006.257.20:39:26.82#ibcon#about to write, iclass 23, count 0 2006.257.20:39:26.82#ibcon#wrote, iclass 23, count 0 2006.257.20:39:26.82#ibcon#about to read 3, iclass 23, count 0 2006.257.20:39:26.85#ibcon#read 3, iclass 23, count 0 2006.257.20:39:26.85#ibcon#about to read 4, iclass 23, count 0 2006.257.20:39:26.85#ibcon#read 4, iclass 23, count 0 2006.257.20:39:26.85#ibcon#about to read 5, iclass 23, count 0 2006.257.20:39:26.85#ibcon#read 5, iclass 23, count 0 2006.257.20:39:26.85#ibcon#about to read 6, iclass 23, count 0 2006.257.20:39:26.85#ibcon#read 6, iclass 23, count 0 2006.257.20:39:26.85#ibcon#end of sib2, iclass 23, count 0 2006.257.20:39:26.85#ibcon#*after write, iclass 23, count 0 2006.257.20:39:26.85#ibcon#*before return 0, iclass 23, count 0 2006.257.20:39:26.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:26.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:39:26.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:39:26.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:39:26.85$vck44/vbbw=wide 2006.257.20:39:26.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.20:39:26.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.20:39:26.85#ibcon#ireg 8 cls_cnt 0 2006.257.20:39:26.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:39:26.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:39:26.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:39:26.92#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:39:26.92#ibcon#first serial, iclass 25, count 0 2006.257.20:39:26.92#ibcon#enter sib2, iclass 25, count 0 2006.257.20:39:26.92#ibcon#flushed, iclass 25, count 0 2006.257.20:39:26.92#ibcon#about to write, iclass 25, count 0 2006.257.20:39:26.92#ibcon#wrote, iclass 25, count 0 2006.257.20:39:26.92#ibcon#about to read 3, iclass 25, count 0 2006.257.20:39:26.94#ibcon#read 3, iclass 25, count 0 2006.257.20:39:26.94#ibcon#about to read 4, iclass 25, count 0 2006.257.20:39:26.94#ibcon#read 4, iclass 25, count 0 2006.257.20:39:26.94#ibcon#about to read 5, iclass 25, count 0 2006.257.20:39:26.94#ibcon#read 5, iclass 25, count 0 2006.257.20:39:26.94#ibcon#about to read 6, iclass 25, count 0 2006.257.20:39:26.94#ibcon#read 6, iclass 25, count 0 2006.257.20:39:26.94#ibcon#end of sib2, iclass 25, count 0 2006.257.20:39:26.94#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:39:26.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:39:26.94#ibcon#[27=BW32\r\n] 2006.257.20:39:26.94#ibcon#*before write, iclass 25, count 0 2006.257.20:39:26.94#ibcon#enter sib2, iclass 25, count 0 2006.257.20:39:26.94#ibcon#flushed, iclass 25, count 0 2006.257.20:39:26.94#ibcon#about to write, iclass 25, count 0 2006.257.20:39:26.94#ibcon#wrote, iclass 25, count 0 2006.257.20:39:26.94#ibcon#about to read 3, iclass 25, count 0 2006.257.20:39:26.97#ibcon#read 3, iclass 25, count 0 2006.257.20:39:26.97#ibcon#about to read 4, iclass 25, count 0 2006.257.20:39:26.97#ibcon#read 4, iclass 25, count 0 2006.257.20:39:26.97#ibcon#about to read 5, iclass 25, count 0 2006.257.20:39:26.97#ibcon#read 5, iclass 25, count 0 2006.257.20:39:26.97#ibcon#about to read 6, iclass 25, count 0 2006.257.20:39:26.97#ibcon#read 6, iclass 25, count 0 2006.257.20:39:26.97#ibcon#end of sib2, iclass 25, count 0 2006.257.20:39:26.97#ibcon#*after write, iclass 25, count 0 2006.257.20:39:26.97#ibcon#*before return 0, iclass 25, count 0 2006.257.20:39:26.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:39:26.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:39:26.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:39:26.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:39:26.97$setupk4/ifdk4 2006.257.20:39:26.97$ifdk4/lo= 2006.257.20:39:26.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.20:39:26.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.20:39:26.97$ifdk4/patch= 2006.257.20:39:26.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.20:39:26.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.20:39:26.97$setupk4/!*+20s 2006.257.20:39:35.92#abcon#<5=/14 0.7 3.2 17.13 981014.9\r\n> 2006.257.20:39:35.94#abcon#{5=INTERFACE CLEAR} 2006.257.20:39:36.00#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:39:37.14#trakl#Source acquired 2006.257.20:39:39.14#flagr#flagr/antenna,acquired 2006.257.20:39:41.48$setupk4/"tpicd 2006.257.20:39:41.48$setupk4/echo=off 2006.257.20:39:41.48$setupk4/xlog=off 2006.257.20:39:41.48:!2006.257.20:41:09 2006.257.20:41:09.00:preob 2006.257.20:41:10.14/onsource/TRACKING 2006.257.20:41:10.14:!2006.257.20:41:19 2006.257.20:41:19.00:"tape 2006.257.20:41:19.00:"st=record 2006.257.20:41:19.00:data_valid=on 2006.257.20:41:19.00:midob 2006.257.20:41:19.14/onsource/TRACKING 2006.257.20:41:19.14/wx/17.14,1014.9,98 2006.257.20:41:19.32/cable/+6.4866E-03 2006.257.20:41:20.41/va/01,08,usb,yes,31,33 2006.257.20:41:20.41/va/02,07,usb,yes,34,34 2006.257.20:41:20.41/va/03,08,usb,yes,30,32 2006.257.20:41:20.41/va/04,07,usb,yes,34,36 2006.257.20:41:20.41/va/05,04,usb,yes,31,31 2006.257.20:41:20.41/va/06,04,usb,yes,34,34 2006.257.20:41:20.41/va/07,04,usb,yes,35,35 2006.257.20:41:20.41/va/08,04,usb,yes,29,35 2006.257.20:41:20.64/valo/01,524.99,yes,locked 2006.257.20:41:20.64/valo/02,534.99,yes,locked 2006.257.20:41:20.64/valo/03,564.99,yes,locked 2006.257.20:41:20.64/valo/04,624.99,yes,locked 2006.257.20:41:20.64/valo/05,734.99,yes,locked 2006.257.20:41:20.64/valo/06,814.99,yes,locked 2006.257.20:41:20.64/valo/07,864.99,yes,locked 2006.257.20:41:20.64/valo/08,884.99,yes,locked 2006.257.20:41:21.73/vb/01,04,usb,yes,30,28 2006.257.20:41:21.73/vb/02,05,usb,yes,29,28 2006.257.20:41:21.73/vb/03,04,usb,yes,29,32 2006.257.20:41:21.73/vb/04,05,usb,yes,30,29 2006.257.20:41:21.73/vb/05,04,usb,yes,26,29 2006.257.20:41:21.73/vb/06,04,usb,yes,31,27 2006.257.20:41:21.73/vb/07,04,usb,yes,30,30 2006.257.20:41:21.73/vb/08,04,usb,yes,28,31 2006.257.20:41:21.97/vblo/01,629.99,yes,locked 2006.257.20:41:21.97/vblo/02,634.99,yes,locked 2006.257.20:41:21.97/vblo/03,649.99,yes,locked 2006.257.20:41:21.97/vblo/04,679.99,yes,locked 2006.257.20:41:21.97/vblo/05,709.99,yes,locked 2006.257.20:41:21.97/vblo/06,719.99,yes,locked 2006.257.20:41:21.97/vblo/07,734.99,yes,locked 2006.257.20:41:21.97/vblo/08,744.99,yes,locked 2006.257.20:41:22.12/vabw/8 2006.257.20:41:22.27/vbbw/8 2006.257.20:41:22.36/xfe/off,on,15.2 2006.257.20:41:22.74/ifatt/23,28,28,28 2006.257.20:41:23.07/fmout-gps/S +4.56E-07 2006.257.20:41:23.11:!2006.257.20:42:59 2006.257.20:42:59.01:data_valid=off 2006.257.20:42:59.01:"et 2006.257.20:42:59.01:!+3s 2006.257.20:43:02.02:"tape 2006.257.20:43:02.02:postob 2006.257.20:43:02.12/cable/+6.4851E-03 2006.257.20:43:02.12/wx/17.15,1014.9,98 2006.257.20:43:02.18/fmout-gps/S +4.56E-07 2006.257.20:43:02.18:scan_name=257-2045,jd0609,50 2006.257.20:43:02.18:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.20:43:04.13#flagr#flagr/antenna,new-source 2006.257.20:43:04.13:checkk5 2006.257.20:43:04.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.20:43:04.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.20:43:05.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.20:43:05.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.20:43:05.85/chk_obsdata//k5ts1/T2572041??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.20:43:06.19/chk_obsdata//k5ts2/T2572041??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.20:43:06.52/chk_obsdata//k5ts3/T2572041??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.20:43:06.85/chk_obsdata//k5ts4/T2572041??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.20:43:07.51/k5log//k5ts1_log_newline 2006.257.20:43:08.17/k5log//k5ts2_log_newline 2006.257.20:43:08.82/k5log//k5ts3_log_newline 2006.257.20:43:09.47/k5log//k5ts4_log_newline 2006.257.20:43:09.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.20:43:09.50:setupk4=1 2006.257.20:43:09.50$setupk4/echo=on 2006.257.20:43:09.50$setupk4/pcalon 2006.257.20:43:09.50$pcalon/"no phase cal control is implemented here 2006.257.20:43:09.50$setupk4/"tpicd=stop 2006.257.20:43:09.50$setupk4/"rec=synch_on 2006.257.20:43:09.50$setupk4/"rec_mode=128 2006.257.20:43:09.50$setupk4/!* 2006.257.20:43:09.50$setupk4/recpk4 2006.257.20:43:09.50$recpk4/recpatch= 2006.257.20:43:09.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.20:43:09.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.20:43:09.50$setupk4/vck44 2006.257.20:43:09.50$vck44/valo=1,524.99 2006.257.20:43:09.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.20:43:09.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.20:43:09.50#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:09.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:09.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:09.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:09.50#ibcon#enter wrdev, iclass 4, count 0 2006.257.20:43:09.50#ibcon#first serial, iclass 4, count 0 2006.257.20:43:09.50#ibcon#enter sib2, iclass 4, count 0 2006.257.20:43:09.50#ibcon#flushed, iclass 4, count 0 2006.257.20:43:09.50#ibcon#about to write, iclass 4, count 0 2006.257.20:43:09.50#ibcon#wrote, iclass 4, count 0 2006.257.20:43:09.50#ibcon#about to read 3, iclass 4, count 0 2006.257.20:43:09.52#ibcon#read 3, iclass 4, count 0 2006.257.20:43:09.52#ibcon#about to read 4, iclass 4, count 0 2006.257.20:43:09.52#ibcon#read 4, iclass 4, count 0 2006.257.20:43:09.52#ibcon#about to read 5, iclass 4, count 0 2006.257.20:43:09.52#ibcon#read 5, iclass 4, count 0 2006.257.20:43:09.52#ibcon#about to read 6, iclass 4, count 0 2006.257.20:43:09.52#ibcon#read 6, iclass 4, count 0 2006.257.20:43:09.52#ibcon#end of sib2, iclass 4, count 0 2006.257.20:43:09.52#ibcon#*mode == 0, iclass 4, count 0 2006.257.20:43:09.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.20:43:09.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.20:43:09.52#ibcon#*before write, iclass 4, count 0 2006.257.20:43:09.52#ibcon#enter sib2, iclass 4, count 0 2006.257.20:43:09.52#ibcon#flushed, iclass 4, count 0 2006.257.20:43:09.52#ibcon#about to write, iclass 4, count 0 2006.257.20:43:09.52#ibcon#wrote, iclass 4, count 0 2006.257.20:43:09.52#ibcon#about to read 3, iclass 4, count 0 2006.257.20:43:09.57#ibcon#read 3, iclass 4, count 0 2006.257.20:43:09.57#ibcon#about to read 4, iclass 4, count 0 2006.257.20:43:09.57#ibcon#read 4, iclass 4, count 0 2006.257.20:43:09.57#ibcon#about to read 5, iclass 4, count 0 2006.257.20:43:09.57#ibcon#read 5, iclass 4, count 0 2006.257.20:43:09.57#ibcon#about to read 6, iclass 4, count 0 2006.257.20:43:09.57#ibcon#read 6, iclass 4, count 0 2006.257.20:43:09.57#ibcon#end of sib2, iclass 4, count 0 2006.257.20:43:09.57#ibcon#*after write, iclass 4, count 0 2006.257.20:43:09.57#ibcon#*before return 0, iclass 4, count 0 2006.257.20:43:09.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:09.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:09.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.20:43:09.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.20:43:09.57$vck44/va=1,8 2006.257.20:43:09.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.20:43:09.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.20:43:09.57#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:09.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:09.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:09.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:09.57#ibcon#enter wrdev, iclass 6, count 2 2006.257.20:43:09.57#ibcon#first serial, iclass 6, count 2 2006.257.20:43:09.57#ibcon#enter sib2, iclass 6, count 2 2006.257.20:43:09.57#ibcon#flushed, iclass 6, count 2 2006.257.20:43:09.57#ibcon#about to write, iclass 6, count 2 2006.257.20:43:09.57#ibcon#wrote, iclass 6, count 2 2006.257.20:43:09.57#ibcon#about to read 3, iclass 6, count 2 2006.257.20:43:09.59#ibcon#read 3, iclass 6, count 2 2006.257.20:43:09.59#ibcon#about to read 4, iclass 6, count 2 2006.257.20:43:09.59#ibcon#read 4, iclass 6, count 2 2006.257.20:43:09.59#ibcon#about to read 5, iclass 6, count 2 2006.257.20:43:09.59#ibcon#read 5, iclass 6, count 2 2006.257.20:43:09.59#ibcon#about to read 6, iclass 6, count 2 2006.257.20:43:09.59#ibcon#read 6, iclass 6, count 2 2006.257.20:43:09.59#ibcon#end of sib2, iclass 6, count 2 2006.257.20:43:09.59#ibcon#*mode == 0, iclass 6, count 2 2006.257.20:43:09.59#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.20:43:09.59#ibcon#[25=AT01-08\r\n] 2006.257.20:43:09.59#ibcon#*before write, iclass 6, count 2 2006.257.20:43:09.59#ibcon#enter sib2, iclass 6, count 2 2006.257.20:43:09.59#ibcon#flushed, iclass 6, count 2 2006.257.20:43:09.59#ibcon#about to write, iclass 6, count 2 2006.257.20:43:09.59#ibcon#wrote, iclass 6, count 2 2006.257.20:43:09.59#ibcon#about to read 3, iclass 6, count 2 2006.257.20:43:09.62#ibcon#read 3, iclass 6, count 2 2006.257.20:43:09.62#ibcon#about to read 4, iclass 6, count 2 2006.257.20:43:09.62#ibcon#read 4, iclass 6, count 2 2006.257.20:43:09.62#ibcon#about to read 5, iclass 6, count 2 2006.257.20:43:09.62#ibcon#read 5, iclass 6, count 2 2006.257.20:43:09.62#ibcon#about to read 6, iclass 6, count 2 2006.257.20:43:09.62#ibcon#read 6, iclass 6, count 2 2006.257.20:43:09.62#ibcon#end of sib2, iclass 6, count 2 2006.257.20:43:09.62#ibcon#*after write, iclass 6, count 2 2006.257.20:43:09.62#ibcon#*before return 0, iclass 6, count 2 2006.257.20:43:09.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:09.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:09.62#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.20:43:09.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:09.62#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:09.63#abcon#<5=/14 0.7 3.2 17.15 981014.9\r\n> 2006.257.20:43:09.65#abcon#{5=INTERFACE CLEAR} 2006.257.20:43:09.71#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:43:09.74#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:09.74#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:09.74#ibcon#enter wrdev, iclass 6, count 0 2006.257.20:43:09.74#ibcon#first serial, iclass 6, count 0 2006.257.20:43:09.74#ibcon#enter sib2, iclass 6, count 0 2006.257.20:43:09.74#ibcon#flushed, iclass 6, count 0 2006.257.20:43:09.74#ibcon#about to write, iclass 6, count 0 2006.257.20:43:09.74#ibcon#wrote, iclass 6, count 0 2006.257.20:43:09.74#ibcon#about to read 3, iclass 6, count 0 2006.257.20:43:09.76#ibcon#read 3, iclass 6, count 0 2006.257.20:43:09.76#ibcon#about to read 4, iclass 6, count 0 2006.257.20:43:09.76#ibcon#read 4, iclass 6, count 0 2006.257.20:43:09.76#ibcon#about to read 5, iclass 6, count 0 2006.257.20:43:09.76#ibcon#read 5, iclass 6, count 0 2006.257.20:43:09.76#ibcon#about to read 6, iclass 6, count 0 2006.257.20:43:09.76#ibcon#read 6, iclass 6, count 0 2006.257.20:43:09.76#ibcon#end of sib2, iclass 6, count 0 2006.257.20:43:09.76#ibcon#*mode == 0, iclass 6, count 0 2006.257.20:43:09.76#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.20:43:09.76#ibcon#[25=USB\r\n] 2006.257.20:43:09.76#ibcon#*before write, iclass 6, count 0 2006.257.20:43:09.76#ibcon#enter sib2, iclass 6, count 0 2006.257.20:43:09.76#ibcon#flushed, iclass 6, count 0 2006.257.20:43:09.76#ibcon#about to write, iclass 6, count 0 2006.257.20:43:09.76#ibcon#wrote, iclass 6, count 0 2006.257.20:43:09.76#ibcon#about to read 3, iclass 6, count 0 2006.257.20:43:09.79#ibcon#read 3, iclass 6, count 0 2006.257.20:43:09.79#ibcon#about to read 4, iclass 6, count 0 2006.257.20:43:09.79#ibcon#read 4, iclass 6, count 0 2006.257.20:43:09.79#ibcon#about to read 5, iclass 6, count 0 2006.257.20:43:09.79#ibcon#read 5, iclass 6, count 0 2006.257.20:43:09.79#ibcon#about to read 6, iclass 6, count 0 2006.257.20:43:09.79#ibcon#read 6, iclass 6, count 0 2006.257.20:43:09.79#ibcon#end of sib2, iclass 6, count 0 2006.257.20:43:09.79#ibcon#*after write, iclass 6, count 0 2006.257.20:43:09.79#ibcon#*before return 0, iclass 6, count 0 2006.257.20:43:09.79#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:09.79#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:09.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.20:43:09.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.20:43:09.79$vck44/valo=2,534.99 2006.257.20:43:09.79#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.20:43:09.79#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.20:43:09.79#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:09.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:09.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:09.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:09.79#ibcon#enter wrdev, iclass 14, count 0 2006.257.20:43:09.79#ibcon#first serial, iclass 14, count 0 2006.257.20:43:09.79#ibcon#enter sib2, iclass 14, count 0 2006.257.20:43:09.79#ibcon#flushed, iclass 14, count 0 2006.257.20:43:09.79#ibcon#about to write, iclass 14, count 0 2006.257.20:43:09.79#ibcon#wrote, iclass 14, count 0 2006.257.20:43:09.79#ibcon#about to read 3, iclass 14, count 0 2006.257.20:43:09.81#ibcon#read 3, iclass 14, count 0 2006.257.20:43:09.81#ibcon#about to read 4, iclass 14, count 0 2006.257.20:43:09.81#ibcon#read 4, iclass 14, count 0 2006.257.20:43:09.81#ibcon#about to read 5, iclass 14, count 0 2006.257.20:43:09.81#ibcon#read 5, iclass 14, count 0 2006.257.20:43:09.81#ibcon#about to read 6, iclass 14, count 0 2006.257.20:43:09.81#ibcon#read 6, iclass 14, count 0 2006.257.20:43:09.81#ibcon#end of sib2, iclass 14, count 0 2006.257.20:43:09.81#ibcon#*mode == 0, iclass 14, count 0 2006.257.20:43:09.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.20:43:09.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.20:43:09.81#ibcon#*before write, iclass 14, count 0 2006.257.20:43:09.81#ibcon#enter sib2, iclass 14, count 0 2006.257.20:43:09.81#ibcon#flushed, iclass 14, count 0 2006.257.20:43:09.81#ibcon#about to write, iclass 14, count 0 2006.257.20:43:09.81#ibcon#wrote, iclass 14, count 0 2006.257.20:43:09.81#ibcon#about to read 3, iclass 14, count 0 2006.257.20:43:09.85#ibcon#read 3, iclass 14, count 0 2006.257.20:43:09.85#ibcon#about to read 4, iclass 14, count 0 2006.257.20:43:09.85#ibcon#read 4, iclass 14, count 0 2006.257.20:43:09.85#ibcon#about to read 5, iclass 14, count 0 2006.257.20:43:09.85#ibcon#read 5, iclass 14, count 0 2006.257.20:43:09.85#ibcon#about to read 6, iclass 14, count 0 2006.257.20:43:09.85#ibcon#read 6, iclass 14, count 0 2006.257.20:43:09.85#ibcon#end of sib2, iclass 14, count 0 2006.257.20:43:09.85#ibcon#*after write, iclass 14, count 0 2006.257.20:43:09.85#ibcon#*before return 0, iclass 14, count 0 2006.257.20:43:09.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:09.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:09.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.20:43:09.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.20:43:09.85$vck44/va=2,7 2006.257.20:43:09.85#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.20:43:09.85#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.20:43:09.85#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:09.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:09.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:09.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:09.91#ibcon#enter wrdev, iclass 16, count 2 2006.257.20:43:09.91#ibcon#first serial, iclass 16, count 2 2006.257.20:43:09.91#ibcon#enter sib2, iclass 16, count 2 2006.257.20:43:09.91#ibcon#flushed, iclass 16, count 2 2006.257.20:43:09.91#ibcon#about to write, iclass 16, count 2 2006.257.20:43:09.91#ibcon#wrote, iclass 16, count 2 2006.257.20:43:09.91#ibcon#about to read 3, iclass 16, count 2 2006.257.20:43:09.93#ibcon#read 3, iclass 16, count 2 2006.257.20:43:09.93#ibcon#about to read 4, iclass 16, count 2 2006.257.20:43:09.93#ibcon#read 4, iclass 16, count 2 2006.257.20:43:09.93#ibcon#about to read 5, iclass 16, count 2 2006.257.20:43:09.93#ibcon#read 5, iclass 16, count 2 2006.257.20:43:09.93#ibcon#about to read 6, iclass 16, count 2 2006.257.20:43:09.93#ibcon#read 6, iclass 16, count 2 2006.257.20:43:09.93#ibcon#end of sib2, iclass 16, count 2 2006.257.20:43:09.93#ibcon#*mode == 0, iclass 16, count 2 2006.257.20:43:09.93#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.20:43:09.93#ibcon#[25=AT02-07\r\n] 2006.257.20:43:09.93#ibcon#*before write, iclass 16, count 2 2006.257.20:43:09.93#ibcon#enter sib2, iclass 16, count 2 2006.257.20:43:09.93#ibcon#flushed, iclass 16, count 2 2006.257.20:43:09.93#ibcon#about to write, iclass 16, count 2 2006.257.20:43:09.93#ibcon#wrote, iclass 16, count 2 2006.257.20:43:09.93#ibcon#about to read 3, iclass 16, count 2 2006.257.20:43:09.96#ibcon#read 3, iclass 16, count 2 2006.257.20:43:09.96#ibcon#about to read 4, iclass 16, count 2 2006.257.20:43:09.96#ibcon#read 4, iclass 16, count 2 2006.257.20:43:09.96#ibcon#about to read 5, iclass 16, count 2 2006.257.20:43:09.96#ibcon#read 5, iclass 16, count 2 2006.257.20:43:09.96#ibcon#about to read 6, iclass 16, count 2 2006.257.20:43:09.96#ibcon#read 6, iclass 16, count 2 2006.257.20:43:09.96#ibcon#end of sib2, iclass 16, count 2 2006.257.20:43:09.96#ibcon#*after write, iclass 16, count 2 2006.257.20:43:09.96#ibcon#*before return 0, iclass 16, count 2 2006.257.20:43:09.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:09.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:09.96#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.20:43:09.96#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:09.96#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:10.08#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:10.08#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:10.08#ibcon#enter wrdev, iclass 16, count 0 2006.257.20:43:10.08#ibcon#first serial, iclass 16, count 0 2006.257.20:43:10.08#ibcon#enter sib2, iclass 16, count 0 2006.257.20:43:10.08#ibcon#flushed, iclass 16, count 0 2006.257.20:43:10.08#ibcon#about to write, iclass 16, count 0 2006.257.20:43:10.08#ibcon#wrote, iclass 16, count 0 2006.257.20:43:10.08#ibcon#about to read 3, iclass 16, count 0 2006.257.20:43:10.10#ibcon#read 3, iclass 16, count 0 2006.257.20:43:10.10#ibcon#about to read 4, iclass 16, count 0 2006.257.20:43:10.10#ibcon#read 4, iclass 16, count 0 2006.257.20:43:10.10#ibcon#about to read 5, iclass 16, count 0 2006.257.20:43:10.10#ibcon#read 5, iclass 16, count 0 2006.257.20:43:10.10#ibcon#about to read 6, iclass 16, count 0 2006.257.20:43:10.10#ibcon#read 6, iclass 16, count 0 2006.257.20:43:10.10#ibcon#end of sib2, iclass 16, count 0 2006.257.20:43:10.10#ibcon#*mode == 0, iclass 16, count 0 2006.257.20:43:10.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.20:43:10.10#ibcon#[25=USB\r\n] 2006.257.20:43:10.10#ibcon#*before write, iclass 16, count 0 2006.257.20:43:10.10#ibcon#enter sib2, iclass 16, count 0 2006.257.20:43:10.10#ibcon#flushed, iclass 16, count 0 2006.257.20:43:10.10#ibcon#about to write, iclass 16, count 0 2006.257.20:43:10.10#ibcon#wrote, iclass 16, count 0 2006.257.20:43:10.10#ibcon#about to read 3, iclass 16, count 0 2006.257.20:43:10.13#ibcon#read 3, iclass 16, count 0 2006.257.20:43:10.13#ibcon#about to read 4, iclass 16, count 0 2006.257.20:43:10.13#ibcon#read 4, iclass 16, count 0 2006.257.20:43:10.13#ibcon#about to read 5, iclass 16, count 0 2006.257.20:43:10.13#ibcon#read 5, iclass 16, count 0 2006.257.20:43:10.13#ibcon#about to read 6, iclass 16, count 0 2006.257.20:43:10.13#ibcon#read 6, iclass 16, count 0 2006.257.20:43:10.13#ibcon#end of sib2, iclass 16, count 0 2006.257.20:43:10.13#ibcon#*after write, iclass 16, count 0 2006.257.20:43:10.13#ibcon#*before return 0, iclass 16, count 0 2006.257.20:43:10.13#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:10.13#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:10.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.20:43:10.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.20:43:10.13$vck44/valo=3,564.99 2006.257.20:43:10.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.20:43:10.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.20:43:10.13#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:10.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:10.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:10.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:10.13#ibcon#enter wrdev, iclass 18, count 0 2006.257.20:43:10.13#ibcon#first serial, iclass 18, count 0 2006.257.20:43:10.13#ibcon#enter sib2, iclass 18, count 0 2006.257.20:43:10.13#ibcon#flushed, iclass 18, count 0 2006.257.20:43:10.13#ibcon#about to write, iclass 18, count 0 2006.257.20:43:10.13#ibcon#wrote, iclass 18, count 0 2006.257.20:43:10.13#ibcon#about to read 3, iclass 18, count 0 2006.257.20:43:10.15#ibcon#read 3, iclass 18, count 0 2006.257.20:43:10.15#ibcon#about to read 4, iclass 18, count 0 2006.257.20:43:10.15#ibcon#read 4, iclass 18, count 0 2006.257.20:43:10.15#ibcon#about to read 5, iclass 18, count 0 2006.257.20:43:10.15#ibcon#read 5, iclass 18, count 0 2006.257.20:43:10.15#ibcon#about to read 6, iclass 18, count 0 2006.257.20:43:10.15#ibcon#read 6, iclass 18, count 0 2006.257.20:43:10.15#ibcon#end of sib2, iclass 18, count 0 2006.257.20:43:10.15#ibcon#*mode == 0, iclass 18, count 0 2006.257.20:43:10.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.20:43:10.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.20:43:10.15#ibcon#*before write, iclass 18, count 0 2006.257.20:43:10.15#ibcon#enter sib2, iclass 18, count 0 2006.257.20:43:10.15#ibcon#flushed, iclass 18, count 0 2006.257.20:43:10.15#ibcon#about to write, iclass 18, count 0 2006.257.20:43:10.15#ibcon#wrote, iclass 18, count 0 2006.257.20:43:10.15#ibcon#about to read 3, iclass 18, count 0 2006.257.20:43:10.19#ibcon#read 3, iclass 18, count 0 2006.257.20:43:10.19#ibcon#about to read 4, iclass 18, count 0 2006.257.20:43:10.19#ibcon#read 4, iclass 18, count 0 2006.257.20:43:10.19#ibcon#about to read 5, iclass 18, count 0 2006.257.20:43:10.19#ibcon#read 5, iclass 18, count 0 2006.257.20:43:10.19#ibcon#about to read 6, iclass 18, count 0 2006.257.20:43:10.19#ibcon#read 6, iclass 18, count 0 2006.257.20:43:10.19#ibcon#end of sib2, iclass 18, count 0 2006.257.20:43:10.19#ibcon#*after write, iclass 18, count 0 2006.257.20:43:10.19#ibcon#*before return 0, iclass 18, count 0 2006.257.20:43:10.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:10.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:10.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.20:43:10.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.20:43:10.19$vck44/va=3,8 2006.257.20:43:10.19#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.20:43:10.19#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.20:43:10.19#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:10.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:10.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:10.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:10.25#ibcon#enter wrdev, iclass 20, count 2 2006.257.20:43:10.25#ibcon#first serial, iclass 20, count 2 2006.257.20:43:10.25#ibcon#enter sib2, iclass 20, count 2 2006.257.20:43:10.25#ibcon#flushed, iclass 20, count 2 2006.257.20:43:10.25#ibcon#about to write, iclass 20, count 2 2006.257.20:43:10.25#ibcon#wrote, iclass 20, count 2 2006.257.20:43:10.25#ibcon#about to read 3, iclass 20, count 2 2006.257.20:43:10.27#ibcon#read 3, iclass 20, count 2 2006.257.20:43:10.27#ibcon#about to read 4, iclass 20, count 2 2006.257.20:43:10.27#ibcon#read 4, iclass 20, count 2 2006.257.20:43:10.27#ibcon#about to read 5, iclass 20, count 2 2006.257.20:43:10.27#ibcon#read 5, iclass 20, count 2 2006.257.20:43:10.27#ibcon#about to read 6, iclass 20, count 2 2006.257.20:43:10.27#ibcon#read 6, iclass 20, count 2 2006.257.20:43:10.27#ibcon#end of sib2, iclass 20, count 2 2006.257.20:43:10.27#ibcon#*mode == 0, iclass 20, count 2 2006.257.20:43:10.27#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.20:43:10.27#ibcon#[25=AT03-08\r\n] 2006.257.20:43:10.27#ibcon#*before write, iclass 20, count 2 2006.257.20:43:10.27#ibcon#enter sib2, iclass 20, count 2 2006.257.20:43:10.27#ibcon#flushed, iclass 20, count 2 2006.257.20:43:10.27#ibcon#about to write, iclass 20, count 2 2006.257.20:43:10.27#ibcon#wrote, iclass 20, count 2 2006.257.20:43:10.27#ibcon#about to read 3, iclass 20, count 2 2006.257.20:43:10.30#ibcon#read 3, iclass 20, count 2 2006.257.20:43:10.30#ibcon#about to read 4, iclass 20, count 2 2006.257.20:43:10.30#ibcon#read 4, iclass 20, count 2 2006.257.20:43:10.30#ibcon#about to read 5, iclass 20, count 2 2006.257.20:43:10.30#ibcon#read 5, iclass 20, count 2 2006.257.20:43:10.30#ibcon#about to read 6, iclass 20, count 2 2006.257.20:43:10.30#ibcon#read 6, iclass 20, count 2 2006.257.20:43:10.30#ibcon#end of sib2, iclass 20, count 2 2006.257.20:43:10.30#ibcon#*after write, iclass 20, count 2 2006.257.20:43:10.30#ibcon#*before return 0, iclass 20, count 2 2006.257.20:43:10.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:10.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:10.30#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.20:43:10.30#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:10.30#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:10.42#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:10.42#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:10.42#ibcon#enter wrdev, iclass 20, count 0 2006.257.20:43:10.42#ibcon#first serial, iclass 20, count 0 2006.257.20:43:10.42#ibcon#enter sib2, iclass 20, count 0 2006.257.20:43:10.42#ibcon#flushed, iclass 20, count 0 2006.257.20:43:10.42#ibcon#about to write, iclass 20, count 0 2006.257.20:43:10.42#ibcon#wrote, iclass 20, count 0 2006.257.20:43:10.42#ibcon#about to read 3, iclass 20, count 0 2006.257.20:43:10.44#ibcon#read 3, iclass 20, count 0 2006.257.20:43:10.44#ibcon#about to read 4, iclass 20, count 0 2006.257.20:43:10.44#ibcon#read 4, iclass 20, count 0 2006.257.20:43:10.44#ibcon#about to read 5, iclass 20, count 0 2006.257.20:43:10.44#ibcon#read 5, iclass 20, count 0 2006.257.20:43:10.44#ibcon#about to read 6, iclass 20, count 0 2006.257.20:43:10.44#ibcon#read 6, iclass 20, count 0 2006.257.20:43:10.44#ibcon#end of sib2, iclass 20, count 0 2006.257.20:43:10.44#ibcon#*mode == 0, iclass 20, count 0 2006.257.20:43:10.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.20:43:10.44#ibcon#[25=USB\r\n] 2006.257.20:43:10.44#ibcon#*before write, iclass 20, count 0 2006.257.20:43:10.44#ibcon#enter sib2, iclass 20, count 0 2006.257.20:43:10.44#ibcon#flushed, iclass 20, count 0 2006.257.20:43:10.44#ibcon#about to write, iclass 20, count 0 2006.257.20:43:10.44#ibcon#wrote, iclass 20, count 0 2006.257.20:43:10.44#ibcon#about to read 3, iclass 20, count 0 2006.257.20:43:10.47#ibcon#read 3, iclass 20, count 0 2006.257.20:43:10.47#ibcon#about to read 4, iclass 20, count 0 2006.257.20:43:10.47#ibcon#read 4, iclass 20, count 0 2006.257.20:43:10.47#ibcon#about to read 5, iclass 20, count 0 2006.257.20:43:10.47#ibcon#read 5, iclass 20, count 0 2006.257.20:43:10.47#ibcon#about to read 6, iclass 20, count 0 2006.257.20:43:10.47#ibcon#read 6, iclass 20, count 0 2006.257.20:43:10.47#ibcon#end of sib2, iclass 20, count 0 2006.257.20:43:10.47#ibcon#*after write, iclass 20, count 0 2006.257.20:43:10.47#ibcon#*before return 0, iclass 20, count 0 2006.257.20:43:10.47#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:10.47#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:10.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.20:43:10.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.20:43:10.47$vck44/valo=4,624.99 2006.257.20:43:10.47#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.20:43:10.47#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.20:43:10.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:10.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:10.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:10.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:10.47#ibcon#enter wrdev, iclass 22, count 0 2006.257.20:43:10.47#ibcon#first serial, iclass 22, count 0 2006.257.20:43:10.47#ibcon#enter sib2, iclass 22, count 0 2006.257.20:43:10.47#ibcon#flushed, iclass 22, count 0 2006.257.20:43:10.47#ibcon#about to write, iclass 22, count 0 2006.257.20:43:10.47#ibcon#wrote, iclass 22, count 0 2006.257.20:43:10.47#ibcon#about to read 3, iclass 22, count 0 2006.257.20:43:10.49#ibcon#read 3, iclass 22, count 0 2006.257.20:43:10.49#ibcon#about to read 4, iclass 22, count 0 2006.257.20:43:10.49#ibcon#read 4, iclass 22, count 0 2006.257.20:43:10.49#ibcon#about to read 5, iclass 22, count 0 2006.257.20:43:10.49#ibcon#read 5, iclass 22, count 0 2006.257.20:43:10.49#ibcon#about to read 6, iclass 22, count 0 2006.257.20:43:10.49#ibcon#read 6, iclass 22, count 0 2006.257.20:43:10.49#ibcon#end of sib2, iclass 22, count 0 2006.257.20:43:10.49#ibcon#*mode == 0, iclass 22, count 0 2006.257.20:43:10.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.20:43:10.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.20:43:10.49#ibcon#*before write, iclass 22, count 0 2006.257.20:43:10.49#ibcon#enter sib2, iclass 22, count 0 2006.257.20:43:10.49#ibcon#flushed, iclass 22, count 0 2006.257.20:43:10.49#ibcon#about to write, iclass 22, count 0 2006.257.20:43:10.49#ibcon#wrote, iclass 22, count 0 2006.257.20:43:10.49#ibcon#about to read 3, iclass 22, count 0 2006.257.20:43:10.53#ibcon#read 3, iclass 22, count 0 2006.257.20:43:10.53#ibcon#about to read 4, iclass 22, count 0 2006.257.20:43:10.53#ibcon#read 4, iclass 22, count 0 2006.257.20:43:10.53#ibcon#about to read 5, iclass 22, count 0 2006.257.20:43:10.53#ibcon#read 5, iclass 22, count 0 2006.257.20:43:10.53#ibcon#about to read 6, iclass 22, count 0 2006.257.20:43:10.53#ibcon#read 6, iclass 22, count 0 2006.257.20:43:10.53#ibcon#end of sib2, iclass 22, count 0 2006.257.20:43:10.53#ibcon#*after write, iclass 22, count 0 2006.257.20:43:10.53#ibcon#*before return 0, iclass 22, count 0 2006.257.20:43:10.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:10.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:10.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.20:43:10.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.20:43:10.53$vck44/va=4,7 2006.257.20:43:10.53#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.20:43:10.53#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.20:43:10.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:10.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:10.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:10.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:10.59#ibcon#enter wrdev, iclass 24, count 2 2006.257.20:43:10.59#ibcon#first serial, iclass 24, count 2 2006.257.20:43:10.59#ibcon#enter sib2, iclass 24, count 2 2006.257.20:43:10.59#ibcon#flushed, iclass 24, count 2 2006.257.20:43:10.59#ibcon#about to write, iclass 24, count 2 2006.257.20:43:10.59#ibcon#wrote, iclass 24, count 2 2006.257.20:43:10.59#ibcon#about to read 3, iclass 24, count 2 2006.257.20:43:10.61#ibcon#read 3, iclass 24, count 2 2006.257.20:43:10.61#ibcon#about to read 4, iclass 24, count 2 2006.257.20:43:10.61#ibcon#read 4, iclass 24, count 2 2006.257.20:43:10.61#ibcon#about to read 5, iclass 24, count 2 2006.257.20:43:10.61#ibcon#read 5, iclass 24, count 2 2006.257.20:43:10.61#ibcon#about to read 6, iclass 24, count 2 2006.257.20:43:10.61#ibcon#read 6, iclass 24, count 2 2006.257.20:43:10.61#ibcon#end of sib2, iclass 24, count 2 2006.257.20:43:10.61#ibcon#*mode == 0, iclass 24, count 2 2006.257.20:43:10.61#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.20:43:10.61#ibcon#[25=AT04-07\r\n] 2006.257.20:43:10.61#ibcon#*before write, iclass 24, count 2 2006.257.20:43:10.61#ibcon#enter sib2, iclass 24, count 2 2006.257.20:43:10.61#ibcon#flushed, iclass 24, count 2 2006.257.20:43:10.61#ibcon#about to write, iclass 24, count 2 2006.257.20:43:10.61#ibcon#wrote, iclass 24, count 2 2006.257.20:43:10.61#ibcon#about to read 3, iclass 24, count 2 2006.257.20:43:10.64#ibcon#read 3, iclass 24, count 2 2006.257.20:43:10.64#ibcon#about to read 4, iclass 24, count 2 2006.257.20:43:10.64#ibcon#read 4, iclass 24, count 2 2006.257.20:43:10.64#ibcon#about to read 5, iclass 24, count 2 2006.257.20:43:10.64#ibcon#read 5, iclass 24, count 2 2006.257.20:43:10.64#ibcon#about to read 6, iclass 24, count 2 2006.257.20:43:10.64#ibcon#read 6, iclass 24, count 2 2006.257.20:43:10.64#ibcon#end of sib2, iclass 24, count 2 2006.257.20:43:10.64#ibcon#*after write, iclass 24, count 2 2006.257.20:43:10.64#ibcon#*before return 0, iclass 24, count 2 2006.257.20:43:10.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:10.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:10.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.20:43:10.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:10.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:10.76#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:10.76#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:10.76#ibcon#enter wrdev, iclass 24, count 0 2006.257.20:43:10.76#ibcon#first serial, iclass 24, count 0 2006.257.20:43:10.76#ibcon#enter sib2, iclass 24, count 0 2006.257.20:43:10.76#ibcon#flushed, iclass 24, count 0 2006.257.20:43:10.76#ibcon#about to write, iclass 24, count 0 2006.257.20:43:10.76#ibcon#wrote, iclass 24, count 0 2006.257.20:43:10.76#ibcon#about to read 3, iclass 24, count 0 2006.257.20:43:10.78#ibcon#read 3, iclass 24, count 0 2006.257.20:43:10.78#ibcon#about to read 4, iclass 24, count 0 2006.257.20:43:10.78#ibcon#read 4, iclass 24, count 0 2006.257.20:43:10.78#ibcon#about to read 5, iclass 24, count 0 2006.257.20:43:10.78#ibcon#read 5, iclass 24, count 0 2006.257.20:43:10.78#ibcon#about to read 6, iclass 24, count 0 2006.257.20:43:10.78#ibcon#read 6, iclass 24, count 0 2006.257.20:43:10.78#ibcon#end of sib2, iclass 24, count 0 2006.257.20:43:10.78#ibcon#*mode == 0, iclass 24, count 0 2006.257.20:43:10.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.20:43:10.78#ibcon#[25=USB\r\n] 2006.257.20:43:10.78#ibcon#*before write, iclass 24, count 0 2006.257.20:43:10.78#ibcon#enter sib2, iclass 24, count 0 2006.257.20:43:10.78#ibcon#flushed, iclass 24, count 0 2006.257.20:43:10.78#ibcon#about to write, iclass 24, count 0 2006.257.20:43:10.78#ibcon#wrote, iclass 24, count 0 2006.257.20:43:10.78#ibcon#about to read 3, iclass 24, count 0 2006.257.20:43:10.81#ibcon#read 3, iclass 24, count 0 2006.257.20:43:10.81#ibcon#about to read 4, iclass 24, count 0 2006.257.20:43:10.81#ibcon#read 4, iclass 24, count 0 2006.257.20:43:10.81#ibcon#about to read 5, iclass 24, count 0 2006.257.20:43:10.81#ibcon#read 5, iclass 24, count 0 2006.257.20:43:10.81#ibcon#about to read 6, iclass 24, count 0 2006.257.20:43:10.81#ibcon#read 6, iclass 24, count 0 2006.257.20:43:10.81#ibcon#end of sib2, iclass 24, count 0 2006.257.20:43:10.81#ibcon#*after write, iclass 24, count 0 2006.257.20:43:10.81#ibcon#*before return 0, iclass 24, count 0 2006.257.20:43:10.81#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:10.81#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:10.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.20:43:10.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.20:43:10.81$vck44/valo=5,734.99 2006.257.20:43:10.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.20:43:10.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.20:43:10.81#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:10.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:10.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:10.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:10.81#ibcon#enter wrdev, iclass 26, count 0 2006.257.20:43:10.81#ibcon#first serial, iclass 26, count 0 2006.257.20:43:10.81#ibcon#enter sib2, iclass 26, count 0 2006.257.20:43:10.81#ibcon#flushed, iclass 26, count 0 2006.257.20:43:10.81#ibcon#about to write, iclass 26, count 0 2006.257.20:43:10.81#ibcon#wrote, iclass 26, count 0 2006.257.20:43:10.81#ibcon#about to read 3, iclass 26, count 0 2006.257.20:43:10.83#ibcon#read 3, iclass 26, count 0 2006.257.20:43:10.83#ibcon#about to read 4, iclass 26, count 0 2006.257.20:43:10.83#ibcon#read 4, iclass 26, count 0 2006.257.20:43:10.83#ibcon#about to read 5, iclass 26, count 0 2006.257.20:43:10.83#ibcon#read 5, iclass 26, count 0 2006.257.20:43:10.83#ibcon#about to read 6, iclass 26, count 0 2006.257.20:43:10.83#ibcon#read 6, iclass 26, count 0 2006.257.20:43:10.83#ibcon#end of sib2, iclass 26, count 0 2006.257.20:43:10.83#ibcon#*mode == 0, iclass 26, count 0 2006.257.20:43:10.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.20:43:10.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.20:43:10.83#ibcon#*before write, iclass 26, count 0 2006.257.20:43:10.83#ibcon#enter sib2, iclass 26, count 0 2006.257.20:43:10.83#ibcon#flushed, iclass 26, count 0 2006.257.20:43:10.83#ibcon#about to write, iclass 26, count 0 2006.257.20:43:10.83#ibcon#wrote, iclass 26, count 0 2006.257.20:43:10.83#ibcon#about to read 3, iclass 26, count 0 2006.257.20:43:10.87#ibcon#read 3, iclass 26, count 0 2006.257.20:43:10.87#ibcon#about to read 4, iclass 26, count 0 2006.257.20:43:10.87#ibcon#read 4, iclass 26, count 0 2006.257.20:43:10.87#ibcon#about to read 5, iclass 26, count 0 2006.257.20:43:10.87#ibcon#read 5, iclass 26, count 0 2006.257.20:43:10.87#ibcon#about to read 6, iclass 26, count 0 2006.257.20:43:10.87#ibcon#read 6, iclass 26, count 0 2006.257.20:43:10.87#ibcon#end of sib2, iclass 26, count 0 2006.257.20:43:10.87#ibcon#*after write, iclass 26, count 0 2006.257.20:43:10.87#ibcon#*before return 0, iclass 26, count 0 2006.257.20:43:10.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:10.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:10.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.20:43:10.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.20:43:10.87$vck44/va=5,4 2006.257.20:43:10.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.20:43:10.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.20:43:10.87#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:10.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:10.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:10.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:10.93#ibcon#enter wrdev, iclass 28, count 2 2006.257.20:43:10.93#ibcon#first serial, iclass 28, count 2 2006.257.20:43:10.93#ibcon#enter sib2, iclass 28, count 2 2006.257.20:43:10.93#ibcon#flushed, iclass 28, count 2 2006.257.20:43:10.93#ibcon#about to write, iclass 28, count 2 2006.257.20:43:10.93#ibcon#wrote, iclass 28, count 2 2006.257.20:43:10.93#ibcon#about to read 3, iclass 28, count 2 2006.257.20:43:10.95#ibcon#read 3, iclass 28, count 2 2006.257.20:43:10.95#ibcon#about to read 4, iclass 28, count 2 2006.257.20:43:10.95#ibcon#read 4, iclass 28, count 2 2006.257.20:43:10.95#ibcon#about to read 5, iclass 28, count 2 2006.257.20:43:10.95#ibcon#read 5, iclass 28, count 2 2006.257.20:43:10.95#ibcon#about to read 6, iclass 28, count 2 2006.257.20:43:10.95#ibcon#read 6, iclass 28, count 2 2006.257.20:43:10.95#ibcon#end of sib2, iclass 28, count 2 2006.257.20:43:10.95#ibcon#*mode == 0, iclass 28, count 2 2006.257.20:43:10.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.20:43:10.95#ibcon#[25=AT05-04\r\n] 2006.257.20:43:10.95#ibcon#*before write, iclass 28, count 2 2006.257.20:43:10.95#ibcon#enter sib2, iclass 28, count 2 2006.257.20:43:10.95#ibcon#flushed, iclass 28, count 2 2006.257.20:43:10.95#ibcon#about to write, iclass 28, count 2 2006.257.20:43:10.95#ibcon#wrote, iclass 28, count 2 2006.257.20:43:10.95#ibcon#about to read 3, iclass 28, count 2 2006.257.20:43:10.98#ibcon#read 3, iclass 28, count 2 2006.257.20:43:10.98#ibcon#about to read 4, iclass 28, count 2 2006.257.20:43:10.98#ibcon#read 4, iclass 28, count 2 2006.257.20:43:10.98#ibcon#about to read 5, iclass 28, count 2 2006.257.20:43:10.98#ibcon#read 5, iclass 28, count 2 2006.257.20:43:10.98#ibcon#about to read 6, iclass 28, count 2 2006.257.20:43:10.98#ibcon#read 6, iclass 28, count 2 2006.257.20:43:10.98#ibcon#end of sib2, iclass 28, count 2 2006.257.20:43:10.98#ibcon#*after write, iclass 28, count 2 2006.257.20:43:10.98#ibcon#*before return 0, iclass 28, count 2 2006.257.20:43:10.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:10.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:10.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.20:43:10.98#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:10.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:11.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:11.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:11.10#ibcon#enter wrdev, iclass 28, count 0 2006.257.20:43:11.10#ibcon#first serial, iclass 28, count 0 2006.257.20:43:11.10#ibcon#enter sib2, iclass 28, count 0 2006.257.20:43:11.10#ibcon#flushed, iclass 28, count 0 2006.257.20:43:11.10#ibcon#about to write, iclass 28, count 0 2006.257.20:43:11.10#ibcon#wrote, iclass 28, count 0 2006.257.20:43:11.10#ibcon#about to read 3, iclass 28, count 0 2006.257.20:43:11.12#ibcon#read 3, iclass 28, count 0 2006.257.20:43:11.12#ibcon#about to read 4, iclass 28, count 0 2006.257.20:43:11.12#ibcon#read 4, iclass 28, count 0 2006.257.20:43:11.12#ibcon#about to read 5, iclass 28, count 0 2006.257.20:43:11.12#ibcon#read 5, iclass 28, count 0 2006.257.20:43:11.12#ibcon#about to read 6, iclass 28, count 0 2006.257.20:43:11.12#ibcon#read 6, iclass 28, count 0 2006.257.20:43:11.12#ibcon#end of sib2, iclass 28, count 0 2006.257.20:43:11.12#ibcon#*mode == 0, iclass 28, count 0 2006.257.20:43:11.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.20:43:11.12#ibcon#[25=USB\r\n] 2006.257.20:43:11.12#ibcon#*before write, iclass 28, count 0 2006.257.20:43:11.12#ibcon#enter sib2, iclass 28, count 0 2006.257.20:43:11.12#ibcon#flushed, iclass 28, count 0 2006.257.20:43:11.12#ibcon#about to write, iclass 28, count 0 2006.257.20:43:11.12#ibcon#wrote, iclass 28, count 0 2006.257.20:43:11.12#ibcon#about to read 3, iclass 28, count 0 2006.257.20:43:11.15#ibcon#read 3, iclass 28, count 0 2006.257.20:43:11.15#ibcon#about to read 4, iclass 28, count 0 2006.257.20:43:11.15#ibcon#read 4, iclass 28, count 0 2006.257.20:43:11.15#ibcon#about to read 5, iclass 28, count 0 2006.257.20:43:11.15#ibcon#read 5, iclass 28, count 0 2006.257.20:43:11.15#ibcon#about to read 6, iclass 28, count 0 2006.257.20:43:11.15#ibcon#read 6, iclass 28, count 0 2006.257.20:43:11.15#ibcon#end of sib2, iclass 28, count 0 2006.257.20:43:11.15#ibcon#*after write, iclass 28, count 0 2006.257.20:43:11.15#ibcon#*before return 0, iclass 28, count 0 2006.257.20:43:11.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:11.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:11.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.20:43:11.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.20:43:11.15$vck44/valo=6,814.99 2006.257.20:43:11.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.20:43:11.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.20:43:11.15#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:11.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:11.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:11.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:11.15#ibcon#enter wrdev, iclass 30, count 0 2006.257.20:43:11.15#ibcon#first serial, iclass 30, count 0 2006.257.20:43:11.15#ibcon#enter sib2, iclass 30, count 0 2006.257.20:43:11.15#ibcon#flushed, iclass 30, count 0 2006.257.20:43:11.15#ibcon#about to write, iclass 30, count 0 2006.257.20:43:11.15#ibcon#wrote, iclass 30, count 0 2006.257.20:43:11.15#ibcon#about to read 3, iclass 30, count 0 2006.257.20:43:11.17#ibcon#read 3, iclass 30, count 0 2006.257.20:43:11.17#ibcon#about to read 4, iclass 30, count 0 2006.257.20:43:11.17#ibcon#read 4, iclass 30, count 0 2006.257.20:43:11.17#ibcon#about to read 5, iclass 30, count 0 2006.257.20:43:11.17#ibcon#read 5, iclass 30, count 0 2006.257.20:43:11.17#ibcon#about to read 6, iclass 30, count 0 2006.257.20:43:11.17#ibcon#read 6, iclass 30, count 0 2006.257.20:43:11.17#ibcon#end of sib2, iclass 30, count 0 2006.257.20:43:11.17#ibcon#*mode == 0, iclass 30, count 0 2006.257.20:43:11.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.20:43:11.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.20:43:11.17#ibcon#*before write, iclass 30, count 0 2006.257.20:43:11.17#ibcon#enter sib2, iclass 30, count 0 2006.257.20:43:11.17#ibcon#flushed, iclass 30, count 0 2006.257.20:43:11.17#ibcon#about to write, iclass 30, count 0 2006.257.20:43:11.17#ibcon#wrote, iclass 30, count 0 2006.257.20:43:11.17#ibcon#about to read 3, iclass 30, count 0 2006.257.20:43:11.21#ibcon#read 3, iclass 30, count 0 2006.257.20:43:11.21#ibcon#about to read 4, iclass 30, count 0 2006.257.20:43:11.21#ibcon#read 4, iclass 30, count 0 2006.257.20:43:11.21#ibcon#about to read 5, iclass 30, count 0 2006.257.20:43:11.21#ibcon#read 5, iclass 30, count 0 2006.257.20:43:11.21#ibcon#about to read 6, iclass 30, count 0 2006.257.20:43:11.21#ibcon#read 6, iclass 30, count 0 2006.257.20:43:11.21#ibcon#end of sib2, iclass 30, count 0 2006.257.20:43:11.21#ibcon#*after write, iclass 30, count 0 2006.257.20:43:11.21#ibcon#*before return 0, iclass 30, count 0 2006.257.20:43:11.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:11.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:11.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.20:43:11.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.20:43:11.21$vck44/va=6,4 2006.257.20:43:11.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.20:43:11.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.20:43:11.21#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:11.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:11.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:11.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:11.27#ibcon#enter wrdev, iclass 32, count 2 2006.257.20:43:11.27#ibcon#first serial, iclass 32, count 2 2006.257.20:43:11.27#ibcon#enter sib2, iclass 32, count 2 2006.257.20:43:11.27#ibcon#flushed, iclass 32, count 2 2006.257.20:43:11.27#ibcon#about to write, iclass 32, count 2 2006.257.20:43:11.27#ibcon#wrote, iclass 32, count 2 2006.257.20:43:11.27#ibcon#about to read 3, iclass 32, count 2 2006.257.20:43:11.29#ibcon#read 3, iclass 32, count 2 2006.257.20:43:11.29#ibcon#about to read 4, iclass 32, count 2 2006.257.20:43:11.29#ibcon#read 4, iclass 32, count 2 2006.257.20:43:11.29#ibcon#about to read 5, iclass 32, count 2 2006.257.20:43:11.29#ibcon#read 5, iclass 32, count 2 2006.257.20:43:11.29#ibcon#about to read 6, iclass 32, count 2 2006.257.20:43:11.29#ibcon#read 6, iclass 32, count 2 2006.257.20:43:11.29#ibcon#end of sib2, iclass 32, count 2 2006.257.20:43:11.29#ibcon#*mode == 0, iclass 32, count 2 2006.257.20:43:11.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.20:43:11.29#ibcon#[25=AT06-04\r\n] 2006.257.20:43:11.29#ibcon#*before write, iclass 32, count 2 2006.257.20:43:11.29#ibcon#enter sib2, iclass 32, count 2 2006.257.20:43:11.29#ibcon#flushed, iclass 32, count 2 2006.257.20:43:11.29#ibcon#about to write, iclass 32, count 2 2006.257.20:43:11.29#ibcon#wrote, iclass 32, count 2 2006.257.20:43:11.29#ibcon#about to read 3, iclass 32, count 2 2006.257.20:43:11.32#ibcon#read 3, iclass 32, count 2 2006.257.20:43:11.32#ibcon#about to read 4, iclass 32, count 2 2006.257.20:43:11.32#ibcon#read 4, iclass 32, count 2 2006.257.20:43:11.32#ibcon#about to read 5, iclass 32, count 2 2006.257.20:43:11.32#ibcon#read 5, iclass 32, count 2 2006.257.20:43:11.32#ibcon#about to read 6, iclass 32, count 2 2006.257.20:43:11.32#ibcon#read 6, iclass 32, count 2 2006.257.20:43:11.32#ibcon#end of sib2, iclass 32, count 2 2006.257.20:43:11.32#ibcon#*after write, iclass 32, count 2 2006.257.20:43:11.32#ibcon#*before return 0, iclass 32, count 2 2006.257.20:43:11.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:11.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:11.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.20:43:11.32#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:11.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:11.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:11.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:11.44#ibcon#enter wrdev, iclass 32, count 0 2006.257.20:43:11.44#ibcon#first serial, iclass 32, count 0 2006.257.20:43:11.44#ibcon#enter sib2, iclass 32, count 0 2006.257.20:43:11.44#ibcon#flushed, iclass 32, count 0 2006.257.20:43:11.44#ibcon#about to write, iclass 32, count 0 2006.257.20:43:11.44#ibcon#wrote, iclass 32, count 0 2006.257.20:43:11.44#ibcon#about to read 3, iclass 32, count 0 2006.257.20:43:11.46#ibcon#read 3, iclass 32, count 0 2006.257.20:43:11.46#ibcon#about to read 4, iclass 32, count 0 2006.257.20:43:11.46#ibcon#read 4, iclass 32, count 0 2006.257.20:43:11.46#ibcon#about to read 5, iclass 32, count 0 2006.257.20:43:11.46#ibcon#read 5, iclass 32, count 0 2006.257.20:43:11.46#ibcon#about to read 6, iclass 32, count 0 2006.257.20:43:11.46#ibcon#read 6, iclass 32, count 0 2006.257.20:43:11.46#ibcon#end of sib2, iclass 32, count 0 2006.257.20:43:11.46#ibcon#*mode == 0, iclass 32, count 0 2006.257.20:43:11.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.20:43:11.46#ibcon#[25=USB\r\n] 2006.257.20:43:11.46#ibcon#*before write, iclass 32, count 0 2006.257.20:43:11.46#ibcon#enter sib2, iclass 32, count 0 2006.257.20:43:11.46#ibcon#flushed, iclass 32, count 0 2006.257.20:43:11.46#ibcon#about to write, iclass 32, count 0 2006.257.20:43:11.46#ibcon#wrote, iclass 32, count 0 2006.257.20:43:11.46#ibcon#about to read 3, iclass 32, count 0 2006.257.20:43:11.49#ibcon#read 3, iclass 32, count 0 2006.257.20:43:11.49#ibcon#about to read 4, iclass 32, count 0 2006.257.20:43:11.49#ibcon#read 4, iclass 32, count 0 2006.257.20:43:11.49#ibcon#about to read 5, iclass 32, count 0 2006.257.20:43:11.49#ibcon#read 5, iclass 32, count 0 2006.257.20:43:11.49#ibcon#about to read 6, iclass 32, count 0 2006.257.20:43:11.49#ibcon#read 6, iclass 32, count 0 2006.257.20:43:11.49#ibcon#end of sib2, iclass 32, count 0 2006.257.20:43:11.49#ibcon#*after write, iclass 32, count 0 2006.257.20:43:11.49#ibcon#*before return 0, iclass 32, count 0 2006.257.20:43:11.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:11.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:11.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.20:43:11.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.20:43:11.49$vck44/valo=7,864.99 2006.257.20:43:11.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.20:43:11.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.20:43:11.49#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:11.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:11.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:11.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:11.49#ibcon#enter wrdev, iclass 34, count 0 2006.257.20:43:11.49#ibcon#first serial, iclass 34, count 0 2006.257.20:43:11.49#ibcon#enter sib2, iclass 34, count 0 2006.257.20:43:11.49#ibcon#flushed, iclass 34, count 0 2006.257.20:43:11.49#ibcon#about to write, iclass 34, count 0 2006.257.20:43:11.49#ibcon#wrote, iclass 34, count 0 2006.257.20:43:11.49#ibcon#about to read 3, iclass 34, count 0 2006.257.20:43:11.51#ibcon#read 3, iclass 34, count 0 2006.257.20:43:11.51#ibcon#about to read 4, iclass 34, count 0 2006.257.20:43:11.51#ibcon#read 4, iclass 34, count 0 2006.257.20:43:11.51#ibcon#about to read 5, iclass 34, count 0 2006.257.20:43:11.51#ibcon#read 5, iclass 34, count 0 2006.257.20:43:11.51#ibcon#about to read 6, iclass 34, count 0 2006.257.20:43:11.51#ibcon#read 6, iclass 34, count 0 2006.257.20:43:11.51#ibcon#end of sib2, iclass 34, count 0 2006.257.20:43:11.51#ibcon#*mode == 0, iclass 34, count 0 2006.257.20:43:11.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.20:43:11.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.20:43:11.51#ibcon#*before write, iclass 34, count 0 2006.257.20:43:11.51#ibcon#enter sib2, iclass 34, count 0 2006.257.20:43:11.51#ibcon#flushed, iclass 34, count 0 2006.257.20:43:11.51#ibcon#about to write, iclass 34, count 0 2006.257.20:43:11.51#ibcon#wrote, iclass 34, count 0 2006.257.20:43:11.51#ibcon#about to read 3, iclass 34, count 0 2006.257.20:43:11.55#ibcon#read 3, iclass 34, count 0 2006.257.20:43:11.55#ibcon#about to read 4, iclass 34, count 0 2006.257.20:43:11.55#ibcon#read 4, iclass 34, count 0 2006.257.20:43:11.55#ibcon#about to read 5, iclass 34, count 0 2006.257.20:43:11.55#ibcon#read 5, iclass 34, count 0 2006.257.20:43:11.55#ibcon#about to read 6, iclass 34, count 0 2006.257.20:43:11.55#ibcon#read 6, iclass 34, count 0 2006.257.20:43:11.55#ibcon#end of sib2, iclass 34, count 0 2006.257.20:43:11.55#ibcon#*after write, iclass 34, count 0 2006.257.20:43:11.55#ibcon#*before return 0, iclass 34, count 0 2006.257.20:43:11.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:11.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:11.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.20:43:11.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.20:43:11.55$vck44/va=7,4 2006.257.20:43:11.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.20:43:11.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.20:43:11.55#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:11.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:11.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:11.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:11.61#ibcon#enter wrdev, iclass 36, count 2 2006.257.20:43:11.61#ibcon#first serial, iclass 36, count 2 2006.257.20:43:11.61#ibcon#enter sib2, iclass 36, count 2 2006.257.20:43:11.61#ibcon#flushed, iclass 36, count 2 2006.257.20:43:11.61#ibcon#about to write, iclass 36, count 2 2006.257.20:43:11.61#ibcon#wrote, iclass 36, count 2 2006.257.20:43:11.61#ibcon#about to read 3, iclass 36, count 2 2006.257.20:43:11.63#ibcon#read 3, iclass 36, count 2 2006.257.20:43:11.63#ibcon#about to read 4, iclass 36, count 2 2006.257.20:43:11.63#ibcon#read 4, iclass 36, count 2 2006.257.20:43:11.63#ibcon#about to read 5, iclass 36, count 2 2006.257.20:43:11.63#ibcon#read 5, iclass 36, count 2 2006.257.20:43:11.63#ibcon#about to read 6, iclass 36, count 2 2006.257.20:43:11.63#ibcon#read 6, iclass 36, count 2 2006.257.20:43:11.63#ibcon#end of sib2, iclass 36, count 2 2006.257.20:43:11.63#ibcon#*mode == 0, iclass 36, count 2 2006.257.20:43:11.63#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.20:43:11.63#ibcon#[25=AT07-04\r\n] 2006.257.20:43:11.63#ibcon#*before write, iclass 36, count 2 2006.257.20:43:11.63#ibcon#enter sib2, iclass 36, count 2 2006.257.20:43:11.63#ibcon#flushed, iclass 36, count 2 2006.257.20:43:11.63#ibcon#about to write, iclass 36, count 2 2006.257.20:43:11.63#ibcon#wrote, iclass 36, count 2 2006.257.20:43:11.63#ibcon#about to read 3, iclass 36, count 2 2006.257.20:43:11.66#ibcon#read 3, iclass 36, count 2 2006.257.20:43:11.66#ibcon#about to read 4, iclass 36, count 2 2006.257.20:43:11.66#ibcon#read 4, iclass 36, count 2 2006.257.20:43:11.66#ibcon#about to read 5, iclass 36, count 2 2006.257.20:43:11.66#ibcon#read 5, iclass 36, count 2 2006.257.20:43:11.66#ibcon#about to read 6, iclass 36, count 2 2006.257.20:43:11.66#ibcon#read 6, iclass 36, count 2 2006.257.20:43:11.66#ibcon#end of sib2, iclass 36, count 2 2006.257.20:43:11.66#ibcon#*after write, iclass 36, count 2 2006.257.20:43:11.66#ibcon#*before return 0, iclass 36, count 2 2006.257.20:43:11.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:11.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:11.66#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.20:43:11.66#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:11.66#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:11.78#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:11.78#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:11.78#ibcon#enter wrdev, iclass 36, count 0 2006.257.20:43:11.78#ibcon#first serial, iclass 36, count 0 2006.257.20:43:11.78#ibcon#enter sib2, iclass 36, count 0 2006.257.20:43:11.78#ibcon#flushed, iclass 36, count 0 2006.257.20:43:11.78#ibcon#about to write, iclass 36, count 0 2006.257.20:43:11.78#ibcon#wrote, iclass 36, count 0 2006.257.20:43:11.78#ibcon#about to read 3, iclass 36, count 0 2006.257.20:43:11.80#ibcon#read 3, iclass 36, count 0 2006.257.20:43:11.80#ibcon#about to read 4, iclass 36, count 0 2006.257.20:43:11.80#ibcon#read 4, iclass 36, count 0 2006.257.20:43:11.80#ibcon#about to read 5, iclass 36, count 0 2006.257.20:43:11.80#ibcon#read 5, iclass 36, count 0 2006.257.20:43:11.80#ibcon#about to read 6, iclass 36, count 0 2006.257.20:43:11.80#ibcon#read 6, iclass 36, count 0 2006.257.20:43:11.80#ibcon#end of sib2, iclass 36, count 0 2006.257.20:43:11.80#ibcon#*mode == 0, iclass 36, count 0 2006.257.20:43:11.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.20:43:11.80#ibcon#[25=USB\r\n] 2006.257.20:43:11.80#ibcon#*before write, iclass 36, count 0 2006.257.20:43:11.80#ibcon#enter sib2, iclass 36, count 0 2006.257.20:43:11.80#ibcon#flushed, iclass 36, count 0 2006.257.20:43:11.80#ibcon#about to write, iclass 36, count 0 2006.257.20:43:11.80#ibcon#wrote, iclass 36, count 0 2006.257.20:43:11.80#ibcon#about to read 3, iclass 36, count 0 2006.257.20:43:11.83#ibcon#read 3, iclass 36, count 0 2006.257.20:43:11.83#ibcon#about to read 4, iclass 36, count 0 2006.257.20:43:11.83#ibcon#read 4, iclass 36, count 0 2006.257.20:43:11.83#ibcon#about to read 5, iclass 36, count 0 2006.257.20:43:11.83#ibcon#read 5, iclass 36, count 0 2006.257.20:43:11.83#ibcon#about to read 6, iclass 36, count 0 2006.257.20:43:11.83#ibcon#read 6, iclass 36, count 0 2006.257.20:43:11.83#ibcon#end of sib2, iclass 36, count 0 2006.257.20:43:11.83#ibcon#*after write, iclass 36, count 0 2006.257.20:43:11.83#ibcon#*before return 0, iclass 36, count 0 2006.257.20:43:11.83#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:11.83#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:11.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.20:43:11.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.20:43:11.83$vck44/valo=8,884.99 2006.257.20:43:11.83#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.20:43:11.83#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.20:43:11.83#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:11.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:11.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:11.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:11.83#ibcon#enter wrdev, iclass 38, count 0 2006.257.20:43:11.83#ibcon#first serial, iclass 38, count 0 2006.257.20:43:11.83#ibcon#enter sib2, iclass 38, count 0 2006.257.20:43:11.83#ibcon#flushed, iclass 38, count 0 2006.257.20:43:11.83#ibcon#about to write, iclass 38, count 0 2006.257.20:43:11.83#ibcon#wrote, iclass 38, count 0 2006.257.20:43:11.83#ibcon#about to read 3, iclass 38, count 0 2006.257.20:43:11.85#ibcon#read 3, iclass 38, count 0 2006.257.20:43:11.85#ibcon#about to read 4, iclass 38, count 0 2006.257.20:43:11.85#ibcon#read 4, iclass 38, count 0 2006.257.20:43:11.85#ibcon#about to read 5, iclass 38, count 0 2006.257.20:43:11.85#ibcon#read 5, iclass 38, count 0 2006.257.20:43:11.85#ibcon#about to read 6, iclass 38, count 0 2006.257.20:43:11.85#ibcon#read 6, iclass 38, count 0 2006.257.20:43:11.85#ibcon#end of sib2, iclass 38, count 0 2006.257.20:43:11.85#ibcon#*mode == 0, iclass 38, count 0 2006.257.20:43:11.85#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.20:43:11.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.20:43:11.85#ibcon#*before write, iclass 38, count 0 2006.257.20:43:11.85#ibcon#enter sib2, iclass 38, count 0 2006.257.20:43:11.85#ibcon#flushed, iclass 38, count 0 2006.257.20:43:11.85#ibcon#about to write, iclass 38, count 0 2006.257.20:43:11.85#ibcon#wrote, iclass 38, count 0 2006.257.20:43:11.85#ibcon#about to read 3, iclass 38, count 0 2006.257.20:43:11.89#ibcon#read 3, iclass 38, count 0 2006.257.20:43:11.89#ibcon#about to read 4, iclass 38, count 0 2006.257.20:43:11.89#ibcon#read 4, iclass 38, count 0 2006.257.20:43:11.89#ibcon#about to read 5, iclass 38, count 0 2006.257.20:43:11.89#ibcon#read 5, iclass 38, count 0 2006.257.20:43:11.89#ibcon#about to read 6, iclass 38, count 0 2006.257.20:43:11.89#ibcon#read 6, iclass 38, count 0 2006.257.20:43:11.89#ibcon#end of sib2, iclass 38, count 0 2006.257.20:43:11.89#ibcon#*after write, iclass 38, count 0 2006.257.20:43:11.89#ibcon#*before return 0, iclass 38, count 0 2006.257.20:43:11.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:11.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:11.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.20:43:11.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.20:43:11.89$vck44/va=8,4 2006.257.20:43:11.89#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.20:43:11.89#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.20:43:11.89#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:11.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:43:11.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:43:11.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:43:11.95#ibcon#enter wrdev, iclass 40, count 2 2006.257.20:43:11.95#ibcon#first serial, iclass 40, count 2 2006.257.20:43:11.95#ibcon#enter sib2, iclass 40, count 2 2006.257.20:43:11.95#ibcon#flushed, iclass 40, count 2 2006.257.20:43:11.95#ibcon#about to write, iclass 40, count 2 2006.257.20:43:11.95#ibcon#wrote, iclass 40, count 2 2006.257.20:43:11.95#ibcon#about to read 3, iclass 40, count 2 2006.257.20:43:11.97#ibcon#read 3, iclass 40, count 2 2006.257.20:43:11.97#ibcon#about to read 4, iclass 40, count 2 2006.257.20:43:11.97#ibcon#read 4, iclass 40, count 2 2006.257.20:43:11.97#ibcon#about to read 5, iclass 40, count 2 2006.257.20:43:11.97#ibcon#read 5, iclass 40, count 2 2006.257.20:43:11.97#ibcon#about to read 6, iclass 40, count 2 2006.257.20:43:11.97#ibcon#read 6, iclass 40, count 2 2006.257.20:43:11.97#ibcon#end of sib2, iclass 40, count 2 2006.257.20:43:11.97#ibcon#*mode == 0, iclass 40, count 2 2006.257.20:43:11.97#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.20:43:11.97#ibcon#[25=AT08-04\r\n] 2006.257.20:43:11.97#ibcon#*before write, iclass 40, count 2 2006.257.20:43:11.97#ibcon#enter sib2, iclass 40, count 2 2006.257.20:43:11.97#ibcon#flushed, iclass 40, count 2 2006.257.20:43:11.97#ibcon#about to write, iclass 40, count 2 2006.257.20:43:11.97#ibcon#wrote, iclass 40, count 2 2006.257.20:43:11.97#ibcon#about to read 3, iclass 40, count 2 2006.257.20:43:12.00#ibcon#read 3, iclass 40, count 2 2006.257.20:43:12.00#ibcon#about to read 4, iclass 40, count 2 2006.257.20:43:12.00#ibcon#read 4, iclass 40, count 2 2006.257.20:43:12.00#ibcon#about to read 5, iclass 40, count 2 2006.257.20:43:12.00#ibcon#read 5, iclass 40, count 2 2006.257.20:43:12.00#ibcon#about to read 6, iclass 40, count 2 2006.257.20:43:12.00#ibcon#read 6, iclass 40, count 2 2006.257.20:43:12.00#ibcon#end of sib2, iclass 40, count 2 2006.257.20:43:12.00#ibcon#*after write, iclass 40, count 2 2006.257.20:43:12.00#ibcon#*before return 0, iclass 40, count 2 2006.257.20:43:12.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:43:12.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.20:43:12.00#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.20:43:12.00#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:12.00#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:43:12.12#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:43:12.12#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:43:12.12#ibcon#enter wrdev, iclass 40, count 0 2006.257.20:43:12.12#ibcon#first serial, iclass 40, count 0 2006.257.20:43:12.12#ibcon#enter sib2, iclass 40, count 0 2006.257.20:43:12.12#ibcon#flushed, iclass 40, count 0 2006.257.20:43:12.12#ibcon#about to write, iclass 40, count 0 2006.257.20:43:12.12#ibcon#wrote, iclass 40, count 0 2006.257.20:43:12.12#ibcon#about to read 3, iclass 40, count 0 2006.257.20:43:12.14#ibcon#read 3, iclass 40, count 0 2006.257.20:43:12.14#ibcon#about to read 4, iclass 40, count 0 2006.257.20:43:12.14#ibcon#read 4, iclass 40, count 0 2006.257.20:43:12.14#ibcon#about to read 5, iclass 40, count 0 2006.257.20:43:12.14#ibcon#read 5, iclass 40, count 0 2006.257.20:43:12.14#ibcon#about to read 6, iclass 40, count 0 2006.257.20:43:12.14#ibcon#read 6, iclass 40, count 0 2006.257.20:43:12.14#ibcon#end of sib2, iclass 40, count 0 2006.257.20:43:12.14#ibcon#*mode == 0, iclass 40, count 0 2006.257.20:43:12.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.20:43:12.14#ibcon#[25=USB\r\n] 2006.257.20:43:12.14#ibcon#*before write, iclass 40, count 0 2006.257.20:43:12.14#ibcon#enter sib2, iclass 40, count 0 2006.257.20:43:12.14#ibcon#flushed, iclass 40, count 0 2006.257.20:43:12.14#ibcon#about to write, iclass 40, count 0 2006.257.20:43:12.14#ibcon#wrote, iclass 40, count 0 2006.257.20:43:12.14#ibcon#about to read 3, iclass 40, count 0 2006.257.20:43:12.17#ibcon#read 3, iclass 40, count 0 2006.257.20:43:12.17#ibcon#about to read 4, iclass 40, count 0 2006.257.20:43:12.17#ibcon#read 4, iclass 40, count 0 2006.257.20:43:12.17#ibcon#about to read 5, iclass 40, count 0 2006.257.20:43:12.17#ibcon#read 5, iclass 40, count 0 2006.257.20:43:12.17#ibcon#about to read 6, iclass 40, count 0 2006.257.20:43:12.17#ibcon#read 6, iclass 40, count 0 2006.257.20:43:12.17#ibcon#end of sib2, iclass 40, count 0 2006.257.20:43:12.17#ibcon#*after write, iclass 40, count 0 2006.257.20:43:12.17#ibcon#*before return 0, iclass 40, count 0 2006.257.20:43:12.17#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:43:12.17#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.20:43:12.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.20:43:12.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.20:43:12.17$vck44/vblo=1,629.99 2006.257.20:43:12.17#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.20:43:12.17#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.20:43:12.17#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:12.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:12.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:12.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:12.17#ibcon#enter wrdev, iclass 4, count 0 2006.257.20:43:12.17#ibcon#first serial, iclass 4, count 0 2006.257.20:43:12.17#ibcon#enter sib2, iclass 4, count 0 2006.257.20:43:12.17#ibcon#flushed, iclass 4, count 0 2006.257.20:43:12.17#ibcon#about to write, iclass 4, count 0 2006.257.20:43:12.17#ibcon#wrote, iclass 4, count 0 2006.257.20:43:12.17#ibcon#about to read 3, iclass 4, count 0 2006.257.20:43:12.19#ibcon#read 3, iclass 4, count 0 2006.257.20:43:12.19#ibcon#about to read 4, iclass 4, count 0 2006.257.20:43:12.19#ibcon#read 4, iclass 4, count 0 2006.257.20:43:12.19#ibcon#about to read 5, iclass 4, count 0 2006.257.20:43:12.19#ibcon#read 5, iclass 4, count 0 2006.257.20:43:12.19#ibcon#about to read 6, iclass 4, count 0 2006.257.20:43:12.19#ibcon#read 6, iclass 4, count 0 2006.257.20:43:12.19#ibcon#end of sib2, iclass 4, count 0 2006.257.20:43:12.19#ibcon#*mode == 0, iclass 4, count 0 2006.257.20:43:12.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.20:43:12.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.20:43:12.19#ibcon#*before write, iclass 4, count 0 2006.257.20:43:12.19#ibcon#enter sib2, iclass 4, count 0 2006.257.20:43:12.19#ibcon#flushed, iclass 4, count 0 2006.257.20:43:12.19#ibcon#about to write, iclass 4, count 0 2006.257.20:43:12.19#ibcon#wrote, iclass 4, count 0 2006.257.20:43:12.19#ibcon#about to read 3, iclass 4, count 0 2006.257.20:43:12.23#ibcon#read 3, iclass 4, count 0 2006.257.20:43:12.23#ibcon#about to read 4, iclass 4, count 0 2006.257.20:43:12.23#ibcon#read 4, iclass 4, count 0 2006.257.20:43:12.23#ibcon#about to read 5, iclass 4, count 0 2006.257.20:43:12.23#ibcon#read 5, iclass 4, count 0 2006.257.20:43:12.23#ibcon#about to read 6, iclass 4, count 0 2006.257.20:43:12.23#ibcon#read 6, iclass 4, count 0 2006.257.20:43:12.23#ibcon#end of sib2, iclass 4, count 0 2006.257.20:43:12.23#ibcon#*after write, iclass 4, count 0 2006.257.20:43:12.23#ibcon#*before return 0, iclass 4, count 0 2006.257.20:43:12.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:12.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.20:43:12.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.20:43:12.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.20:43:12.23$vck44/vb=1,4 2006.257.20:43:12.23#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.20:43:12.23#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.20:43:12.23#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:12.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:12.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:12.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:12.23#ibcon#enter wrdev, iclass 6, count 2 2006.257.20:43:12.23#ibcon#first serial, iclass 6, count 2 2006.257.20:43:12.23#ibcon#enter sib2, iclass 6, count 2 2006.257.20:43:12.23#ibcon#flushed, iclass 6, count 2 2006.257.20:43:12.23#ibcon#about to write, iclass 6, count 2 2006.257.20:43:12.23#ibcon#wrote, iclass 6, count 2 2006.257.20:43:12.23#ibcon#about to read 3, iclass 6, count 2 2006.257.20:43:12.25#ibcon#read 3, iclass 6, count 2 2006.257.20:43:12.25#ibcon#about to read 4, iclass 6, count 2 2006.257.20:43:12.25#ibcon#read 4, iclass 6, count 2 2006.257.20:43:12.25#ibcon#about to read 5, iclass 6, count 2 2006.257.20:43:12.25#ibcon#read 5, iclass 6, count 2 2006.257.20:43:12.25#ibcon#about to read 6, iclass 6, count 2 2006.257.20:43:12.25#ibcon#read 6, iclass 6, count 2 2006.257.20:43:12.25#ibcon#end of sib2, iclass 6, count 2 2006.257.20:43:12.25#ibcon#*mode == 0, iclass 6, count 2 2006.257.20:43:12.25#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.20:43:12.25#ibcon#[27=AT01-04\r\n] 2006.257.20:43:12.25#ibcon#*before write, iclass 6, count 2 2006.257.20:43:12.25#ibcon#enter sib2, iclass 6, count 2 2006.257.20:43:12.25#ibcon#flushed, iclass 6, count 2 2006.257.20:43:12.25#ibcon#about to write, iclass 6, count 2 2006.257.20:43:12.25#ibcon#wrote, iclass 6, count 2 2006.257.20:43:12.25#ibcon#about to read 3, iclass 6, count 2 2006.257.20:43:12.28#ibcon#read 3, iclass 6, count 2 2006.257.20:43:12.28#ibcon#about to read 4, iclass 6, count 2 2006.257.20:43:12.28#ibcon#read 4, iclass 6, count 2 2006.257.20:43:12.28#ibcon#about to read 5, iclass 6, count 2 2006.257.20:43:12.28#ibcon#read 5, iclass 6, count 2 2006.257.20:43:12.28#ibcon#about to read 6, iclass 6, count 2 2006.257.20:43:12.28#ibcon#read 6, iclass 6, count 2 2006.257.20:43:12.28#ibcon#end of sib2, iclass 6, count 2 2006.257.20:43:12.28#ibcon#*after write, iclass 6, count 2 2006.257.20:43:12.28#ibcon#*before return 0, iclass 6, count 2 2006.257.20:43:12.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:12.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.20:43:12.28#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.20:43:12.28#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:12.28#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:12.40#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:12.40#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:12.40#ibcon#enter wrdev, iclass 6, count 0 2006.257.20:43:12.40#ibcon#first serial, iclass 6, count 0 2006.257.20:43:12.40#ibcon#enter sib2, iclass 6, count 0 2006.257.20:43:12.40#ibcon#flushed, iclass 6, count 0 2006.257.20:43:12.40#ibcon#about to write, iclass 6, count 0 2006.257.20:43:12.40#ibcon#wrote, iclass 6, count 0 2006.257.20:43:12.40#ibcon#about to read 3, iclass 6, count 0 2006.257.20:43:12.42#ibcon#read 3, iclass 6, count 0 2006.257.20:43:12.42#ibcon#about to read 4, iclass 6, count 0 2006.257.20:43:12.42#ibcon#read 4, iclass 6, count 0 2006.257.20:43:12.42#ibcon#about to read 5, iclass 6, count 0 2006.257.20:43:12.42#ibcon#read 5, iclass 6, count 0 2006.257.20:43:12.42#ibcon#about to read 6, iclass 6, count 0 2006.257.20:43:12.42#ibcon#read 6, iclass 6, count 0 2006.257.20:43:12.42#ibcon#end of sib2, iclass 6, count 0 2006.257.20:43:12.42#ibcon#*mode == 0, iclass 6, count 0 2006.257.20:43:12.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.20:43:12.42#ibcon#[27=USB\r\n] 2006.257.20:43:12.42#ibcon#*before write, iclass 6, count 0 2006.257.20:43:12.42#ibcon#enter sib2, iclass 6, count 0 2006.257.20:43:12.42#ibcon#flushed, iclass 6, count 0 2006.257.20:43:12.42#ibcon#about to write, iclass 6, count 0 2006.257.20:43:12.42#ibcon#wrote, iclass 6, count 0 2006.257.20:43:12.42#ibcon#about to read 3, iclass 6, count 0 2006.257.20:43:12.45#ibcon#read 3, iclass 6, count 0 2006.257.20:43:12.45#ibcon#about to read 4, iclass 6, count 0 2006.257.20:43:12.45#ibcon#read 4, iclass 6, count 0 2006.257.20:43:12.45#ibcon#about to read 5, iclass 6, count 0 2006.257.20:43:12.45#ibcon#read 5, iclass 6, count 0 2006.257.20:43:12.45#ibcon#about to read 6, iclass 6, count 0 2006.257.20:43:12.45#ibcon#read 6, iclass 6, count 0 2006.257.20:43:12.45#ibcon#end of sib2, iclass 6, count 0 2006.257.20:43:12.45#ibcon#*after write, iclass 6, count 0 2006.257.20:43:12.45#ibcon#*before return 0, iclass 6, count 0 2006.257.20:43:12.45#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:12.45#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.20:43:12.45#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.20:43:12.45#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.20:43:12.45$vck44/vblo=2,634.99 2006.257.20:43:12.45#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.20:43:12.45#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.20:43:12.45#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:12.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:43:12.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:43:12.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:43:12.45#ibcon#enter wrdev, iclass 10, count 0 2006.257.20:43:12.45#ibcon#first serial, iclass 10, count 0 2006.257.20:43:12.45#ibcon#enter sib2, iclass 10, count 0 2006.257.20:43:12.45#ibcon#flushed, iclass 10, count 0 2006.257.20:43:12.45#ibcon#about to write, iclass 10, count 0 2006.257.20:43:12.45#ibcon#wrote, iclass 10, count 0 2006.257.20:43:12.45#ibcon#about to read 3, iclass 10, count 0 2006.257.20:43:12.47#ibcon#read 3, iclass 10, count 0 2006.257.20:43:12.47#ibcon#about to read 4, iclass 10, count 0 2006.257.20:43:12.47#ibcon#read 4, iclass 10, count 0 2006.257.20:43:12.47#ibcon#about to read 5, iclass 10, count 0 2006.257.20:43:12.47#ibcon#read 5, iclass 10, count 0 2006.257.20:43:12.47#ibcon#about to read 6, iclass 10, count 0 2006.257.20:43:12.47#ibcon#read 6, iclass 10, count 0 2006.257.20:43:12.47#ibcon#end of sib2, iclass 10, count 0 2006.257.20:43:12.47#ibcon#*mode == 0, iclass 10, count 0 2006.257.20:43:12.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.20:43:12.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.20:43:12.47#ibcon#*before write, iclass 10, count 0 2006.257.20:43:12.47#ibcon#enter sib2, iclass 10, count 0 2006.257.20:43:12.47#ibcon#flushed, iclass 10, count 0 2006.257.20:43:12.47#ibcon#about to write, iclass 10, count 0 2006.257.20:43:12.47#ibcon#wrote, iclass 10, count 0 2006.257.20:43:12.47#ibcon#about to read 3, iclass 10, count 0 2006.257.20:43:12.51#ibcon#read 3, iclass 10, count 0 2006.257.20:43:12.51#ibcon#about to read 4, iclass 10, count 0 2006.257.20:43:12.51#ibcon#read 4, iclass 10, count 0 2006.257.20:43:12.51#ibcon#about to read 5, iclass 10, count 0 2006.257.20:43:12.51#ibcon#read 5, iclass 10, count 0 2006.257.20:43:12.51#ibcon#about to read 6, iclass 10, count 0 2006.257.20:43:12.51#ibcon#read 6, iclass 10, count 0 2006.257.20:43:12.51#ibcon#end of sib2, iclass 10, count 0 2006.257.20:43:12.51#ibcon#*after write, iclass 10, count 0 2006.257.20:43:12.51#ibcon#*before return 0, iclass 10, count 0 2006.257.20:43:12.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:43:12.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:43:12.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.20:43:12.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.20:43:12.51$vck44/vb=2,5 2006.257.20:43:12.51#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.20:43:12.51#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.20:43:12.51#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:12.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:43:12.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:43:12.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:43:12.57#ibcon#enter wrdev, iclass 12, count 2 2006.257.20:43:12.57#ibcon#first serial, iclass 12, count 2 2006.257.20:43:12.57#ibcon#enter sib2, iclass 12, count 2 2006.257.20:43:12.57#ibcon#flushed, iclass 12, count 2 2006.257.20:43:12.57#ibcon#about to write, iclass 12, count 2 2006.257.20:43:12.57#ibcon#wrote, iclass 12, count 2 2006.257.20:43:12.57#ibcon#about to read 3, iclass 12, count 2 2006.257.20:43:12.59#ibcon#read 3, iclass 12, count 2 2006.257.20:43:12.59#ibcon#about to read 4, iclass 12, count 2 2006.257.20:43:12.59#ibcon#read 4, iclass 12, count 2 2006.257.20:43:12.59#ibcon#about to read 5, iclass 12, count 2 2006.257.20:43:12.59#ibcon#read 5, iclass 12, count 2 2006.257.20:43:12.59#ibcon#about to read 6, iclass 12, count 2 2006.257.20:43:12.59#ibcon#read 6, iclass 12, count 2 2006.257.20:43:12.59#ibcon#end of sib2, iclass 12, count 2 2006.257.20:43:12.59#ibcon#*mode == 0, iclass 12, count 2 2006.257.20:43:12.59#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.20:43:12.59#ibcon#[27=AT02-05\r\n] 2006.257.20:43:12.59#ibcon#*before write, iclass 12, count 2 2006.257.20:43:12.59#ibcon#enter sib2, iclass 12, count 2 2006.257.20:43:12.59#ibcon#flushed, iclass 12, count 2 2006.257.20:43:12.59#ibcon#about to write, iclass 12, count 2 2006.257.20:43:12.59#ibcon#wrote, iclass 12, count 2 2006.257.20:43:12.59#ibcon#about to read 3, iclass 12, count 2 2006.257.20:43:12.62#ibcon#read 3, iclass 12, count 2 2006.257.20:43:12.62#ibcon#about to read 4, iclass 12, count 2 2006.257.20:43:12.62#ibcon#read 4, iclass 12, count 2 2006.257.20:43:12.62#ibcon#about to read 5, iclass 12, count 2 2006.257.20:43:12.62#ibcon#read 5, iclass 12, count 2 2006.257.20:43:12.62#ibcon#about to read 6, iclass 12, count 2 2006.257.20:43:12.62#ibcon#read 6, iclass 12, count 2 2006.257.20:43:12.62#ibcon#end of sib2, iclass 12, count 2 2006.257.20:43:12.62#ibcon#*after write, iclass 12, count 2 2006.257.20:43:12.62#ibcon#*before return 0, iclass 12, count 2 2006.257.20:43:12.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:43:12.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.20:43:12.62#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.20:43:12.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:12.62#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:43:12.74#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:43:12.74#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:43:12.74#ibcon#enter wrdev, iclass 12, count 0 2006.257.20:43:12.74#ibcon#first serial, iclass 12, count 0 2006.257.20:43:12.74#ibcon#enter sib2, iclass 12, count 0 2006.257.20:43:12.74#ibcon#flushed, iclass 12, count 0 2006.257.20:43:12.74#ibcon#about to write, iclass 12, count 0 2006.257.20:43:12.74#ibcon#wrote, iclass 12, count 0 2006.257.20:43:12.74#ibcon#about to read 3, iclass 12, count 0 2006.257.20:43:12.76#ibcon#read 3, iclass 12, count 0 2006.257.20:43:12.76#ibcon#about to read 4, iclass 12, count 0 2006.257.20:43:12.76#ibcon#read 4, iclass 12, count 0 2006.257.20:43:12.76#ibcon#about to read 5, iclass 12, count 0 2006.257.20:43:12.76#ibcon#read 5, iclass 12, count 0 2006.257.20:43:12.76#ibcon#about to read 6, iclass 12, count 0 2006.257.20:43:12.76#ibcon#read 6, iclass 12, count 0 2006.257.20:43:12.76#ibcon#end of sib2, iclass 12, count 0 2006.257.20:43:12.76#ibcon#*mode == 0, iclass 12, count 0 2006.257.20:43:12.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.20:43:12.76#ibcon#[27=USB\r\n] 2006.257.20:43:12.76#ibcon#*before write, iclass 12, count 0 2006.257.20:43:12.76#ibcon#enter sib2, iclass 12, count 0 2006.257.20:43:12.76#ibcon#flushed, iclass 12, count 0 2006.257.20:43:12.76#ibcon#about to write, iclass 12, count 0 2006.257.20:43:12.76#ibcon#wrote, iclass 12, count 0 2006.257.20:43:12.76#ibcon#about to read 3, iclass 12, count 0 2006.257.20:43:12.79#ibcon#read 3, iclass 12, count 0 2006.257.20:43:12.79#ibcon#about to read 4, iclass 12, count 0 2006.257.20:43:12.79#ibcon#read 4, iclass 12, count 0 2006.257.20:43:12.79#ibcon#about to read 5, iclass 12, count 0 2006.257.20:43:12.79#ibcon#read 5, iclass 12, count 0 2006.257.20:43:12.79#ibcon#about to read 6, iclass 12, count 0 2006.257.20:43:12.79#ibcon#read 6, iclass 12, count 0 2006.257.20:43:12.79#ibcon#end of sib2, iclass 12, count 0 2006.257.20:43:12.79#ibcon#*after write, iclass 12, count 0 2006.257.20:43:12.79#ibcon#*before return 0, iclass 12, count 0 2006.257.20:43:12.79#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:43:12.79#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.20:43:12.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.20:43:12.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.20:43:12.79$vck44/vblo=3,649.99 2006.257.20:43:12.79#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.20:43:12.79#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.20:43:12.79#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:12.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:12.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:12.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:12.79#ibcon#enter wrdev, iclass 14, count 0 2006.257.20:43:12.79#ibcon#first serial, iclass 14, count 0 2006.257.20:43:12.79#ibcon#enter sib2, iclass 14, count 0 2006.257.20:43:12.79#ibcon#flushed, iclass 14, count 0 2006.257.20:43:12.79#ibcon#about to write, iclass 14, count 0 2006.257.20:43:12.79#ibcon#wrote, iclass 14, count 0 2006.257.20:43:12.79#ibcon#about to read 3, iclass 14, count 0 2006.257.20:43:12.81#ibcon#read 3, iclass 14, count 0 2006.257.20:43:12.81#ibcon#about to read 4, iclass 14, count 0 2006.257.20:43:12.81#ibcon#read 4, iclass 14, count 0 2006.257.20:43:12.81#ibcon#about to read 5, iclass 14, count 0 2006.257.20:43:12.81#ibcon#read 5, iclass 14, count 0 2006.257.20:43:12.81#ibcon#about to read 6, iclass 14, count 0 2006.257.20:43:12.81#ibcon#read 6, iclass 14, count 0 2006.257.20:43:12.81#ibcon#end of sib2, iclass 14, count 0 2006.257.20:43:12.81#ibcon#*mode == 0, iclass 14, count 0 2006.257.20:43:12.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.20:43:12.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.20:43:12.81#ibcon#*before write, iclass 14, count 0 2006.257.20:43:12.81#ibcon#enter sib2, iclass 14, count 0 2006.257.20:43:12.81#ibcon#flushed, iclass 14, count 0 2006.257.20:43:12.81#ibcon#about to write, iclass 14, count 0 2006.257.20:43:12.81#ibcon#wrote, iclass 14, count 0 2006.257.20:43:12.81#ibcon#about to read 3, iclass 14, count 0 2006.257.20:43:12.85#ibcon#read 3, iclass 14, count 0 2006.257.20:43:12.85#ibcon#about to read 4, iclass 14, count 0 2006.257.20:43:12.85#ibcon#read 4, iclass 14, count 0 2006.257.20:43:12.85#ibcon#about to read 5, iclass 14, count 0 2006.257.20:43:12.85#ibcon#read 5, iclass 14, count 0 2006.257.20:43:12.85#ibcon#about to read 6, iclass 14, count 0 2006.257.20:43:12.85#ibcon#read 6, iclass 14, count 0 2006.257.20:43:12.85#ibcon#end of sib2, iclass 14, count 0 2006.257.20:43:12.85#ibcon#*after write, iclass 14, count 0 2006.257.20:43:12.85#ibcon#*before return 0, iclass 14, count 0 2006.257.20:43:12.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:12.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.20:43:12.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.20:43:12.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.20:43:12.85$vck44/vb=3,4 2006.257.20:43:12.85#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.20:43:12.85#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.20:43:12.85#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:12.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:12.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:12.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:12.91#ibcon#enter wrdev, iclass 16, count 2 2006.257.20:43:12.91#ibcon#first serial, iclass 16, count 2 2006.257.20:43:12.91#ibcon#enter sib2, iclass 16, count 2 2006.257.20:43:12.91#ibcon#flushed, iclass 16, count 2 2006.257.20:43:12.91#ibcon#about to write, iclass 16, count 2 2006.257.20:43:12.91#ibcon#wrote, iclass 16, count 2 2006.257.20:43:12.91#ibcon#about to read 3, iclass 16, count 2 2006.257.20:43:12.93#ibcon#read 3, iclass 16, count 2 2006.257.20:43:12.93#ibcon#about to read 4, iclass 16, count 2 2006.257.20:43:12.93#ibcon#read 4, iclass 16, count 2 2006.257.20:43:12.93#ibcon#about to read 5, iclass 16, count 2 2006.257.20:43:12.93#ibcon#read 5, iclass 16, count 2 2006.257.20:43:12.93#ibcon#about to read 6, iclass 16, count 2 2006.257.20:43:12.93#ibcon#read 6, iclass 16, count 2 2006.257.20:43:12.93#ibcon#end of sib2, iclass 16, count 2 2006.257.20:43:12.93#ibcon#*mode == 0, iclass 16, count 2 2006.257.20:43:12.93#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.20:43:12.93#ibcon#[27=AT03-04\r\n] 2006.257.20:43:12.93#ibcon#*before write, iclass 16, count 2 2006.257.20:43:12.93#ibcon#enter sib2, iclass 16, count 2 2006.257.20:43:12.93#ibcon#flushed, iclass 16, count 2 2006.257.20:43:12.93#ibcon#about to write, iclass 16, count 2 2006.257.20:43:12.93#ibcon#wrote, iclass 16, count 2 2006.257.20:43:12.93#ibcon#about to read 3, iclass 16, count 2 2006.257.20:43:12.96#ibcon#read 3, iclass 16, count 2 2006.257.20:43:12.96#ibcon#about to read 4, iclass 16, count 2 2006.257.20:43:12.96#ibcon#read 4, iclass 16, count 2 2006.257.20:43:12.96#ibcon#about to read 5, iclass 16, count 2 2006.257.20:43:12.96#ibcon#read 5, iclass 16, count 2 2006.257.20:43:12.96#ibcon#about to read 6, iclass 16, count 2 2006.257.20:43:12.96#ibcon#read 6, iclass 16, count 2 2006.257.20:43:12.96#ibcon#end of sib2, iclass 16, count 2 2006.257.20:43:12.96#ibcon#*after write, iclass 16, count 2 2006.257.20:43:12.96#ibcon#*before return 0, iclass 16, count 2 2006.257.20:43:12.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:12.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.20:43:12.96#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.20:43:12.96#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:12.96#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:13.08#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:13.08#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:13.08#ibcon#enter wrdev, iclass 16, count 0 2006.257.20:43:13.08#ibcon#first serial, iclass 16, count 0 2006.257.20:43:13.08#ibcon#enter sib2, iclass 16, count 0 2006.257.20:43:13.08#ibcon#flushed, iclass 16, count 0 2006.257.20:43:13.08#ibcon#about to write, iclass 16, count 0 2006.257.20:43:13.08#ibcon#wrote, iclass 16, count 0 2006.257.20:43:13.08#ibcon#about to read 3, iclass 16, count 0 2006.257.20:43:13.10#ibcon#read 3, iclass 16, count 0 2006.257.20:43:13.10#ibcon#about to read 4, iclass 16, count 0 2006.257.20:43:13.10#ibcon#read 4, iclass 16, count 0 2006.257.20:43:13.10#ibcon#about to read 5, iclass 16, count 0 2006.257.20:43:13.10#ibcon#read 5, iclass 16, count 0 2006.257.20:43:13.10#ibcon#about to read 6, iclass 16, count 0 2006.257.20:43:13.10#ibcon#read 6, iclass 16, count 0 2006.257.20:43:13.10#ibcon#end of sib2, iclass 16, count 0 2006.257.20:43:13.10#ibcon#*mode == 0, iclass 16, count 0 2006.257.20:43:13.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.20:43:13.10#ibcon#[27=USB\r\n] 2006.257.20:43:13.10#ibcon#*before write, iclass 16, count 0 2006.257.20:43:13.10#ibcon#enter sib2, iclass 16, count 0 2006.257.20:43:13.10#ibcon#flushed, iclass 16, count 0 2006.257.20:43:13.10#ibcon#about to write, iclass 16, count 0 2006.257.20:43:13.10#ibcon#wrote, iclass 16, count 0 2006.257.20:43:13.10#ibcon#about to read 3, iclass 16, count 0 2006.257.20:43:13.13#ibcon#read 3, iclass 16, count 0 2006.257.20:43:13.13#ibcon#about to read 4, iclass 16, count 0 2006.257.20:43:13.13#ibcon#read 4, iclass 16, count 0 2006.257.20:43:13.13#ibcon#about to read 5, iclass 16, count 0 2006.257.20:43:13.13#ibcon#read 5, iclass 16, count 0 2006.257.20:43:13.13#ibcon#about to read 6, iclass 16, count 0 2006.257.20:43:13.13#ibcon#read 6, iclass 16, count 0 2006.257.20:43:13.13#ibcon#end of sib2, iclass 16, count 0 2006.257.20:43:13.13#ibcon#*after write, iclass 16, count 0 2006.257.20:43:13.13#ibcon#*before return 0, iclass 16, count 0 2006.257.20:43:13.13#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:13.13#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.20:43:13.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.20:43:13.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.20:43:13.13$vck44/vblo=4,679.99 2006.257.20:43:13.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.20:43:13.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.20:43:13.13#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:13.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:13.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:13.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:13.13#ibcon#enter wrdev, iclass 18, count 0 2006.257.20:43:13.13#ibcon#first serial, iclass 18, count 0 2006.257.20:43:13.13#ibcon#enter sib2, iclass 18, count 0 2006.257.20:43:13.13#ibcon#flushed, iclass 18, count 0 2006.257.20:43:13.13#ibcon#about to write, iclass 18, count 0 2006.257.20:43:13.13#ibcon#wrote, iclass 18, count 0 2006.257.20:43:13.13#ibcon#about to read 3, iclass 18, count 0 2006.257.20:43:13.15#ibcon#read 3, iclass 18, count 0 2006.257.20:43:13.15#ibcon#about to read 4, iclass 18, count 0 2006.257.20:43:13.15#ibcon#read 4, iclass 18, count 0 2006.257.20:43:13.15#ibcon#about to read 5, iclass 18, count 0 2006.257.20:43:13.15#ibcon#read 5, iclass 18, count 0 2006.257.20:43:13.15#ibcon#about to read 6, iclass 18, count 0 2006.257.20:43:13.15#ibcon#read 6, iclass 18, count 0 2006.257.20:43:13.15#ibcon#end of sib2, iclass 18, count 0 2006.257.20:43:13.15#ibcon#*mode == 0, iclass 18, count 0 2006.257.20:43:13.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.20:43:13.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.20:43:13.15#ibcon#*before write, iclass 18, count 0 2006.257.20:43:13.15#ibcon#enter sib2, iclass 18, count 0 2006.257.20:43:13.15#ibcon#flushed, iclass 18, count 0 2006.257.20:43:13.15#ibcon#about to write, iclass 18, count 0 2006.257.20:43:13.15#ibcon#wrote, iclass 18, count 0 2006.257.20:43:13.15#ibcon#about to read 3, iclass 18, count 0 2006.257.20:43:13.19#ibcon#read 3, iclass 18, count 0 2006.257.20:43:13.19#ibcon#about to read 4, iclass 18, count 0 2006.257.20:43:13.19#ibcon#read 4, iclass 18, count 0 2006.257.20:43:13.19#ibcon#about to read 5, iclass 18, count 0 2006.257.20:43:13.19#ibcon#read 5, iclass 18, count 0 2006.257.20:43:13.19#ibcon#about to read 6, iclass 18, count 0 2006.257.20:43:13.19#ibcon#read 6, iclass 18, count 0 2006.257.20:43:13.19#ibcon#end of sib2, iclass 18, count 0 2006.257.20:43:13.19#ibcon#*after write, iclass 18, count 0 2006.257.20:43:13.19#ibcon#*before return 0, iclass 18, count 0 2006.257.20:43:13.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:13.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.20:43:13.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.20:43:13.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.20:43:13.19$vck44/vb=4,5 2006.257.20:43:13.19#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.20:43:13.19#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.20:43:13.19#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:13.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:13.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:13.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:13.25#ibcon#enter wrdev, iclass 20, count 2 2006.257.20:43:13.25#ibcon#first serial, iclass 20, count 2 2006.257.20:43:13.25#ibcon#enter sib2, iclass 20, count 2 2006.257.20:43:13.25#ibcon#flushed, iclass 20, count 2 2006.257.20:43:13.25#ibcon#about to write, iclass 20, count 2 2006.257.20:43:13.25#ibcon#wrote, iclass 20, count 2 2006.257.20:43:13.25#ibcon#about to read 3, iclass 20, count 2 2006.257.20:43:13.27#ibcon#read 3, iclass 20, count 2 2006.257.20:43:13.27#ibcon#about to read 4, iclass 20, count 2 2006.257.20:43:13.27#ibcon#read 4, iclass 20, count 2 2006.257.20:43:13.27#ibcon#about to read 5, iclass 20, count 2 2006.257.20:43:13.27#ibcon#read 5, iclass 20, count 2 2006.257.20:43:13.27#ibcon#about to read 6, iclass 20, count 2 2006.257.20:43:13.27#ibcon#read 6, iclass 20, count 2 2006.257.20:43:13.27#ibcon#end of sib2, iclass 20, count 2 2006.257.20:43:13.27#ibcon#*mode == 0, iclass 20, count 2 2006.257.20:43:13.27#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.20:43:13.27#ibcon#[27=AT04-05\r\n] 2006.257.20:43:13.27#ibcon#*before write, iclass 20, count 2 2006.257.20:43:13.27#ibcon#enter sib2, iclass 20, count 2 2006.257.20:43:13.27#ibcon#flushed, iclass 20, count 2 2006.257.20:43:13.27#ibcon#about to write, iclass 20, count 2 2006.257.20:43:13.27#ibcon#wrote, iclass 20, count 2 2006.257.20:43:13.27#ibcon#about to read 3, iclass 20, count 2 2006.257.20:43:13.30#ibcon#read 3, iclass 20, count 2 2006.257.20:43:13.30#ibcon#about to read 4, iclass 20, count 2 2006.257.20:43:13.30#ibcon#read 4, iclass 20, count 2 2006.257.20:43:13.30#ibcon#about to read 5, iclass 20, count 2 2006.257.20:43:13.30#ibcon#read 5, iclass 20, count 2 2006.257.20:43:13.30#ibcon#about to read 6, iclass 20, count 2 2006.257.20:43:13.30#ibcon#read 6, iclass 20, count 2 2006.257.20:43:13.30#ibcon#end of sib2, iclass 20, count 2 2006.257.20:43:13.30#ibcon#*after write, iclass 20, count 2 2006.257.20:43:13.30#ibcon#*before return 0, iclass 20, count 2 2006.257.20:43:13.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:13.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.20:43:13.30#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.20:43:13.30#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:13.30#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:13.42#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:13.42#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:13.42#ibcon#enter wrdev, iclass 20, count 0 2006.257.20:43:13.42#ibcon#first serial, iclass 20, count 0 2006.257.20:43:13.42#ibcon#enter sib2, iclass 20, count 0 2006.257.20:43:13.42#ibcon#flushed, iclass 20, count 0 2006.257.20:43:13.42#ibcon#about to write, iclass 20, count 0 2006.257.20:43:13.42#ibcon#wrote, iclass 20, count 0 2006.257.20:43:13.42#ibcon#about to read 3, iclass 20, count 0 2006.257.20:43:13.44#ibcon#read 3, iclass 20, count 0 2006.257.20:43:13.44#ibcon#about to read 4, iclass 20, count 0 2006.257.20:43:13.44#ibcon#read 4, iclass 20, count 0 2006.257.20:43:13.44#ibcon#about to read 5, iclass 20, count 0 2006.257.20:43:13.44#ibcon#read 5, iclass 20, count 0 2006.257.20:43:13.44#ibcon#about to read 6, iclass 20, count 0 2006.257.20:43:13.44#ibcon#read 6, iclass 20, count 0 2006.257.20:43:13.44#ibcon#end of sib2, iclass 20, count 0 2006.257.20:43:13.44#ibcon#*mode == 0, iclass 20, count 0 2006.257.20:43:13.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.20:43:13.44#ibcon#[27=USB\r\n] 2006.257.20:43:13.44#ibcon#*before write, iclass 20, count 0 2006.257.20:43:13.44#ibcon#enter sib2, iclass 20, count 0 2006.257.20:43:13.44#ibcon#flushed, iclass 20, count 0 2006.257.20:43:13.44#ibcon#about to write, iclass 20, count 0 2006.257.20:43:13.44#ibcon#wrote, iclass 20, count 0 2006.257.20:43:13.44#ibcon#about to read 3, iclass 20, count 0 2006.257.20:43:13.47#ibcon#read 3, iclass 20, count 0 2006.257.20:43:13.47#ibcon#about to read 4, iclass 20, count 0 2006.257.20:43:13.47#ibcon#read 4, iclass 20, count 0 2006.257.20:43:13.47#ibcon#about to read 5, iclass 20, count 0 2006.257.20:43:13.47#ibcon#read 5, iclass 20, count 0 2006.257.20:43:13.47#ibcon#about to read 6, iclass 20, count 0 2006.257.20:43:13.47#ibcon#read 6, iclass 20, count 0 2006.257.20:43:13.47#ibcon#end of sib2, iclass 20, count 0 2006.257.20:43:13.47#ibcon#*after write, iclass 20, count 0 2006.257.20:43:13.47#ibcon#*before return 0, iclass 20, count 0 2006.257.20:43:13.47#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:13.47#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.20:43:13.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.20:43:13.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.20:43:13.47$vck44/vblo=5,709.99 2006.257.20:43:13.47#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.20:43:13.47#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.20:43:13.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:13.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:13.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:13.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:13.47#ibcon#enter wrdev, iclass 22, count 0 2006.257.20:43:13.47#ibcon#first serial, iclass 22, count 0 2006.257.20:43:13.47#ibcon#enter sib2, iclass 22, count 0 2006.257.20:43:13.47#ibcon#flushed, iclass 22, count 0 2006.257.20:43:13.47#ibcon#about to write, iclass 22, count 0 2006.257.20:43:13.47#ibcon#wrote, iclass 22, count 0 2006.257.20:43:13.47#ibcon#about to read 3, iclass 22, count 0 2006.257.20:43:13.49#ibcon#read 3, iclass 22, count 0 2006.257.20:43:13.49#ibcon#about to read 4, iclass 22, count 0 2006.257.20:43:13.49#ibcon#read 4, iclass 22, count 0 2006.257.20:43:13.49#ibcon#about to read 5, iclass 22, count 0 2006.257.20:43:13.49#ibcon#read 5, iclass 22, count 0 2006.257.20:43:13.49#ibcon#about to read 6, iclass 22, count 0 2006.257.20:43:13.49#ibcon#read 6, iclass 22, count 0 2006.257.20:43:13.49#ibcon#end of sib2, iclass 22, count 0 2006.257.20:43:13.49#ibcon#*mode == 0, iclass 22, count 0 2006.257.20:43:13.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.20:43:13.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.20:43:13.49#ibcon#*before write, iclass 22, count 0 2006.257.20:43:13.49#ibcon#enter sib2, iclass 22, count 0 2006.257.20:43:13.49#ibcon#flushed, iclass 22, count 0 2006.257.20:43:13.49#ibcon#about to write, iclass 22, count 0 2006.257.20:43:13.49#ibcon#wrote, iclass 22, count 0 2006.257.20:43:13.49#ibcon#about to read 3, iclass 22, count 0 2006.257.20:43:13.53#ibcon#read 3, iclass 22, count 0 2006.257.20:43:13.53#ibcon#about to read 4, iclass 22, count 0 2006.257.20:43:13.53#ibcon#read 4, iclass 22, count 0 2006.257.20:43:13.53#ibcon#about to read 5, iclass 22, count 0 2006.257.20:43:13.53#ibcon#read 5, iclass 22, count 0 2006.257.20:43:13.53#ibcon#about to read 6, iclass 22, count 0 2006.257.20:43:13.53#ibcon#read 6, iclass 22, count 0 2006.257.20:43:13.53#ibcon#end of sib2, iclass 22, count 0 2006.257.20:43:13.53#ibcon#*after write, iclass 22, count 0 2006.257.20:43:13.53#ibcon#*before return 0, iclass 22, count 0 2006.257.20:43:13.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:13.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.20:43:13.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.20:43:13.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.20:43:13.53$vck44/vb=5,4 2006.257.20:43:13.53#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.20:43:13.53#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.20:43:13.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:13.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:13.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:13.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:13.59#ibcon#enter wrdev, iclass 24, count 2 2006.257.20:43:13.59#ibcon#first serial, iclass 24, count 2 2006.257.20:43:13.59#ibcon#enter sib2, iclass 24, count 2 2006.257.20:43:13.59#ibcon#flushed, iclass 24, count 2 2006.257.20:43:13.59#ibcon#about to write, iclass 24, count 2 2006.257.20:43:13.59#ibcon#wrote, iclass 24, count 2 2006.257.20:43:13.59#ibcon#about to read 3, iclass 24, count 2 2006.257.20:43:13.61#ibcon#read 3, iclass 24, count 2 2006.257.20:43:13.61#ibcon#about to read 4, iclass 24, count 2 2006.257.20:43:13.61#ibcon#read 4, iclass 24, count 2 2006.257.20:43:13.61#ibcon#about to read 5, iclass 24, count 2 2006.257.20:43:13.61#ibcon#read 5, iclass 24, count 2 2006.257.20:43:13.61#ibcon#about to read 6, iclass 24, count 2 2006.257.20:43:13.61#ibcon#read 6, iclass 24, count 2 2006.257.20:43:13.61#ibcon#end of sib2, iclass 24, count 2 2006.257.20:43:13.61#ibcon#*mode == 0, iclass 24, count 2 2006.257.20:43:13.61#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.20:43:13.61#ibcon#[27=AT05-04\r\n] 2006.257.20:43:13.61#ibcon#*before write, iclass 24, count 2 2006.257.20:43:13.61#ibcon#enter sib2, iclass 24, count 2 2006.257.20:43:13.61#ibcon#flushed, iclass 24, count 2 2006.257.20:43:13.61#ibcon#about to write, iclass 24, count 2 2006.257.20:43:13.61#ibcon#wrote, iclass 24, count 2 2006.257.20:43:13.61#ibcon#about to read 3, iclass 24, count 2 2006.257.20:43:13.64#ibcon#read 3, iclass 24, count 2 2006.257.20:43:13.64#ibcon#about to read 4, iclass 24, count 2 2006.257.20:43:13.64#ibcon#read 4, iclass 24, count 2 2006.257.20:43:13.64#ibcon#about to read 5, iclass 24, count 2 2006.257.20:43:13.64#ibcon#read 5, iclass 24, count 2 2006.257.20:43:13.64#ibcon#about to read 6, iclass 24, count 2 2006.257.20:43:13.64#ibcon#read 6, iclass 24, count 2 2006.257.20:43:13.64#ibcon#end of sib2, iclass 24, count 2 2006.257.20:43:13.64#ibcon#*after write, iclass 24, count 2 2006.257.20:43:13.64#ibcon#*before return 0, iclass 24, count 2 2006.257.20:43:13.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:13.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.20:43:13.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.20:43:13.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:13.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:13.76#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:13.76#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:13.76#ibcon#enter wrdev, iclass 24, count 0 2006.257.20:43:13.76#ibcon#first serial, iclass 24, count 0 2006.257.20:43:13.76#ibcon#enter sib2, iclass 24, count 0 2006.257.20:43:13.76#ibcon#flushed, iclass 24, count 0 2006.257.20:43:13.76#ibcon#about to write, iclass 24, count 0 2006.257.20:43:13.76#ibcon#wrote, iclass 24, count 0 2006.257.20:43:13.76#ibcon#about to read 3, iclass 24, count 0 2006.257.20:43:13.78#ibcon#read 3, iclass 24, count 0 2006.257.20:43:13.78#ibcon#about to read 4, iclass 24, count 0 2006.257.20:43:13.78#ibcon#read 4, iclass 24, count 0 2006.257.20:43:13.78#ibcon#about to read 5, iclass 24, count 0 2006.257.20:43:13.78#ibcon#read 5, iclass 24, count 0 2006.257.20:43:13.78#ibcon#about to read 6, iclass 24, count 0 2006.257.20:43:13.78#ibcon#read 6, iclass 24, count 0 2006.257.20:43:13.78#ibcon#end of sib2, iclass 24, count 0 2006.257.20:43:13.78#ibcon#*mode == 0, iclass 24, count 0 2006.257.20:43:13.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.20:43:13.78#ibcon#[27=USB\r\n] 2006.257.20:43:13.78#ibcon#*before write, iclass 24, count 0 2006.257.20:43:13.78#ibcon#enter sib2, iclass 24, count 0 2006.257.20:43:13.78#ibcon#flushed, iclass 24, count 0 2006.257.20:43:13.78#ibcon#about to write, iclass 24, count 0 2006.257.20:43:13.78#ibcon#wrote, iclass 24, count 0 2006.257.20:43:13.78#ibcon#about to read 3, iclass 24, count 0 2006.257.20:43:13.81#ibcon#read 3, iclass 24, count 0 2006.257.20:43:13.81#ibcon#about to read 4, iclass 24, count 0 2006.257.20:43:13.81#ibcon#read 4, iclass 24, count 0 2006.257.20:43:13.81#ibcon#about to read 5, iclass 24, count 0 2006.257.20:43:13.81#ibcon#read 5, iclass 24, count 0 2006.257.20:43:13.81#ibcon#about to read 6, iclass 24, count 0 2006.257.20:43:13.81#ibcon#read 6, iclass 24, count 0 2006.257.20:43:13.81#ibcon#end of sib2, iclass 24, count 0 2006.257.20:43:13.81#ibcon#*after write, iclass 24, count 0 2006.257.20:43:13.81#ibcon#*before return 0, iclass 24, count 0 2006.257.20:43:13.81#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:13.81#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.20:43:13.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.20:43:13.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.20:43:13.81$vck44/vblo=6,719.99 2006.257.20:43:13.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.20:43:13.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.20:43:13.81#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:13.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:13.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:13.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:13.81#ibcon#enter wrdev, iclass 26, count 0 2006.257.20:43:13.81#ibcon#first serial, iclass 26, count 0 2006.257.20:43:13.81#ibcon#enter sib2, iclass 26, count 0 2006.257.20:43:13.81#ibcon#flushed, iclass 26, count 0 2006.257.20:43:13.81#ibcon#about to write, iclass 26, count 0 2006.257.20:43:13.81#ibcon#wrote, iclass 26, count 0 2006.257.20:43:13.81#ibcon#about to read 3, iclass 26, count 0 2006.257.20:43:13.83#ibcon#read 3, iclass 26, count 0 2006.257.20:43:13.83#ibcon#about to read 4, iclass 26, count 0 2006.257.20:43:13.83#ibcon#read 4, iclass 26, count 0 2006.257.20:43:13.83#ibcon#about to read 5, iclass 26, count 0 2006.257.20:43:13.83#ibcon#read 5, iclass 26, count 0 2006.257.20:43:13.83#ibcon#about to read 6, iclass 26, count 0 2006.257.20:43:13.83#ibcon#read 6, iclass 26, count 0 2006.257.20:43:13.83#ibcon#end of sib2, iclass 26, count 0 2006.257.20:43:13.83#ibcon#*mode == 0, iclass 26, count 0 2006.257.20:43:13.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.20:43:13.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.20:43:13.83#ibcon#*before write, iclass 26, count 0 2006.257.20:43:13.83#ibcon#enter sib2, iclass 26, count 0 2006.257.20:43:13.83#ibcon#flushed, iclass 26, count 0 2006.257.20:43:13.83#ibcon#about to write, iclass 26, count 0 2006.257.20:43:13.83#ibcon#wrote, iclass 26, count 0 2006.257.20:43:13.83#ibcon#about to read 3, iclass 26, count 0 2006.257.20:43:13.87#ibcon#read 3, iclass 26, count 0 2006.257.20:43:13.87#ibcon#about to read 4, iclass 26, count 0 2006.257.20:43:13.87#ibcon#read 4, iclass 26, count 0 2006.257.20:43:13.87#ibcon#about to read 5, iclass 26, count 0 2006.257.20:43:13.87#ibcon#read 5, iclass 26, count 0 2006.257.20:43:13.87#ibcon#about to read 6, iclass 26, count 0 2006.257.20:43:13.87#ibcon#read 6, iclass 26, count 0 2006.257.20:43:13.87#ibcon#end of sib2, iclass 26, count 0 2006.257.20:43:13.87#ibcon#*after write, iclass 26, count 0 2006.257.20:43:13.87#ibcon#*before return 0, iclass 26, count 0 2006.257.20:43:13.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:13.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.20:43:13.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.20:43:13.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.20:43:13.87$vck44/vb=6,4 2006.257.20:43:13.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.20:43:13.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.20:43:13.87#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:13.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:13.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:13.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:13.93#ibcon#enter wrdev, iclass 28, count 2 2006.257.20:43:13.93#ibcon#first serial, iclass 28, count 2 2006.257.20:43:13.93#ibcon#enter sib2, iclass 28, count 2 2006.257.20:43:13.93#ibcon#flushed, iclass 28, count 2 2006.257.20:43:13.93#ibcon#about to write, iclass 28, count 2 2006.257.20:43:13.93#ibcon#wrote, iclass 28, count 2 2006.257.20:43:13.93#ibcon#about to read 3, iclass 28, count 2 2006.257.20:43:13.95#ibcon#read 3, iclass 28, count 2 2006.257.20:43:13.95#ibcon#about to read 4, iclass 28, count 2 2006.257.20:43:13.95#ibcon#read 4, iclass 28, count 2 2006.257.20:43:13.95#ibcon#about to read 5, iclass 28, count 2 2006.257.20:43:13.95#ibcon#read 5, iclass 28, count 2 2006.257.20:43:13.95#ibcon#about to read 6, iclass 28, count 2 2006.257.20:43:13.95#ibcon#read 6, iclass 28, count 2 2006.257.20:43:13.95#ibcon#end of sib2, iclass 28, count 2 2006.257.20:43:13.95#ibcon#*mode == 0, iclass 28, count 2 2006.257.20:43:13.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.20:43:13.95#ibcon#[27=AT06-04\r\n] 2006.257.20:43:13.95#ibcon#*before write, iclass 28, count 2 2006.257.20:43:13.95#ibcon#enter sib2, iclass 28, count 2 2006.257.20:43:13.95#ibcon#flushed, iclass 28, count 2 2006.257.20:43:13.95#ibcon#about to write, iclass 28, count 2 2006.257.20:43:13.95#ibcon#wrote, iclass 28, count 2 2006.257.20:43:13.95#ibcon#about to read 3, iclass 28, count 2 2006.257.20:43:13.98#ibcon#read 3, iclass 28, count 2 2006.257.20:43:13.98#ibcon#about to read 4, iclass 28, count 2 2006.257.20:43:13.98#ibcon#read 4, iclass 28, count 2 2006.257.20:43:13.98#ibcon#about to read 5, iclass 28, count 2 2006.257.20:43:13.98#ibcon#read 5, iclass 28, count 2 2006.257.20:43:13.98#ibcon#about to read 6, iclass 28, count 2 2006.257.20:43:13.98#ibcon#read 6, iclass 28, count 2 2006.257.20:43:13.98#ibcon#end of sib2, iclass 28, count 2 2006.257.20:43:13.98#ibcon#*after write, iclass 28, count 2 2006.257.20:43:13.98#ibcon#*before return 0, iclass 28, count 2 2006.257.20:43:13.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:13.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.20:43:13.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.20:43:13.98#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:13.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:14.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:14.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:14.10#ibcon#enter wrdev, iclass 28, count 0 2006.257.20:43:14.10#ibcon#first serial, iclass 28, count 0 2006.257.20:43:14.10#ibcon#enter sib2, iclass 28, count 0 2006.257.20:43:14.10#ibcon#flushed, iclass 28, count 0 2006.257.20:43:14.10#ibcon#about to write, iclass 28, count 0 2006.257.20:43:14.10#ibcon#wrote, iclass 28, count 0 2006.257.20:43:14.10#ibcon#about to read 3, iclass 28, count 0 2006.257.20:43:14.12#ibcon#read 3, iclass 28, count 0 2006.257.20:43:14.12#ibcon#about to read 4, iclass 28, count 0 2006.257.20:43:14.12#ibcon#read 4, iclass 28, count 0 2006.257.20:43:14.12#ibcon#about to read 5, iclass 28, count 0 2006.257.20:43:14.12#ibcon#read 5, iclass 28, count 0 2006.257.20:43:14.12#ibcon#about to read 6, iclass 28, count 0 2006.257.20:43:14.12#ibcon#read 6, iclass 28, count 0 2006.257.20:43:14.12#ibcon#end of sib2, iclass 28, count 0 2006.257.20:43:14.12#ibcon#*mode == 0, iclass 28, count 0 2006.257.20:43:14.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.20:43:14.12#ibcon#[27=USB\r\n] 2006.257.20:43:14.12#ibcon#*before write, iclass 28, count 0 2006.257.20:43:14.12#ibcon#enter sib2, iclass 28, count 0 2006.257.20:43:14.12#ibcon#flushed, iclass 28, count 0 2006.257.20:43:14.12#ibcon#about to write, iclass 28, count 0 2006.257.20:43:14.12#ibcon#wrote, iclass 28, count 0 2006.257.20:43:14.12#ibcon#about to read 3, iclass 28, count 0 2006.257.20:43:14.15#ibcon#read 3, iclass 28, count 0 2006.257.20:43:14.15#ibcon#about to read 4, iclass 28, count 0 2006.257.20:43:14.15#ibcon#read 4, iclass 28, count 0 2006.257.20:43:14.15#ibcon#about to read 5, iclass 28, count 0 2006.257.20:43:14.15#ibcon#read 5, iclass 28, count 0 2006.257.20:43:14.15#ibcon#about to read 6, iclass 28, count 0 2006.257.20:43:14.15#ibcon#read 6, iclass 28, count 0 2006.257.20:43:14.15#ibcon#end of sib2, iclass 28, count 0 2006.257.20:43:14.15#ibcon#*after write, iclass 28, count 0 2006.257.20:43:14.15#ibcon#*before return 0, iclass 28, count 0 2006.257.20:43:14.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:14.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.20:43:14.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.20:43:14.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.20:43:14.15$vck44/vblo=7,734.99 2006.257.20:43:14.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.20:43:14.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.20:43:14.15#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:14.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:14.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:14.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:14.15#ibcon#enter wrdev, iclass 30, count 0 2006.257.20:43:14.15#ibcon#first serial, iclass 30, count 0 2006.257.20:43:14.15#ibcon#enter sib2, iclass 30, count 0 2006.257.20:43:14.15#ibcon#flushed, iclass 30, count 0 2006.257.20:43:14.15#ibcon#about to write, iclass 30, count 0 2006.257.20:43:14.15#ibcon#wrote, iclass 30, count 0 2006.257.20:43:14.15#ibcon#about to read 3, iclass 30, count 0 2006.257.20:43:14.17#ibcon#read 3, iclass 30, count 0 2006.257.20:43:14.17#ibcon#about to read 4, iclass 30, count 0 2006.257.20:43:14.17#ibcon#read 4, iclass 30, count 0 2006.257.20:43:14.17#ibcon#about to read 5, iclass 30, count 0 2006.257.20:43:14.17#ibcon#read 5, iclass 30, count 0 2006.257.20:43:14.17#ibcon#about to read 6, iclass 30, count 0 2006.257.20:43:14.17#ibcon#read 6, iclass 30, count 0 2006.257.20:43:14.17#ibcon#end of sib2, iclass 30, count 0 2006.257.20:43:14.17#ibcon#*mode == 0, iclass 30, count 0 2006.257.20:43:14.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.20:43:14.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.20:43:14.17#ibcon#*before write, iclass 30, count 0 2006.257.20:43:14.17#ibcon#enter sib2, iclass 30, count 0 2006.257.20:43:14.17#ibcon#flushed, iclass 30, count 0 2006.257.20:43:14.17#ibcon#about to write, iclass 30, count 0 2006.257.20:43:14.17#ibcon#wrote, iclass 30, count 0 2006.257.20:43:14.17#ibcon#about to read 3, iclass 30, count 0 2006.257.20:43:14.21#ibcon#read 3, iclass 30, count 0 2006.257.20:43:14.21#ibcon#about to read 4, iclass 30, count 0 2006.257.20:43:14.21#ibcon#read 4, iclass 30, count 0 2006.257.20:43:14.21#ibcon#about to read 5, iclass 30, count 0 2006.257.20:43:14.21#ibcon#read 5, iclass 30, count 0 2006.257.20:43:14.21#ibcon#about to read 6, iclass 30, count 0 2006.257.20:43:14.21#ibcon#read 6, iclass 30, count 0 2006.257.20:43:14.21#ibcon#end of sib2, iclass 30, count 0 2006.257.20:43:14.21#ibcon#*after write, iclass 30, count 0 2006.257.20:43:14.21#ibcon#*before return 0, iclass 30, count 0 2006.257.20:43:14.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:14.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.20:43:14.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.20:43:14.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.20:43:14.21$vck44/vb=7,4 2006.257.20:43:14.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.20:43:14.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.20:43:14.21#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:14.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:14.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:14.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:14.27#ibcon#enter wrdev, iclass 32, count 2 2006.257.20:43:14.27#ibcon#first serial, iclass 32, count 2 2006.257.20:43:14.27#ibcon#enter sib2, iclass 32, count 2 2006.257.20:43:14.27#ibcon#flushed, iclass 32, count 2 2006.257.20:43:14.27#ibcon#about to write, iclass 32, count 2 2006.257.20:43:14.27#ibcon#wrote, iclass 32, count 2 2006.257.20:43:14.27#ibcon#about to read 3, iclass 32, count 2 2006.257.20:43:14.29#ibcon#read 3, iclass 32, count 2 2006.257.20:43:14.29#ibcon#about to read 4, iclass 32, count 2 2006.257.20:43:14.29#ibcon#read 4, iclass 32, count 2 2006.257.20:43:14.29#ibcon#about to read 5, iclass 32, count 2 2006.257.20:43:14.29#ibcon#read 5, iclass 32, count 2 2006.257.20:43:14.29#ibcon#about to read 6, iclass 32, count 2 2006.257.20:43:14.29#ibcon#read 6, iclass 32, count 2 2006.257.20:43:14.29#ibcon#end of sib2, iclass 32, count 2 2006.257.20:43:14.29#ibcon#*mode == 0, iclass 32, count 2 2006.257.20:43:14.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.20:43:14.29#ibcon#[27=AT07-04\r\n] 2006.257.20:43:14.29#ibcon#*before write, iclass 32, count 2 2006.257.20:43:14.29#ibcon#enter sib2, iclass 32, count 2 2006.257.20:43:14.29#ibcon#flushed, iclass 32, count 2 2006.257.20:43:14.29#ibcon#about to write, iclass 32, count 2 2006.257.20:43:14.29#ibcon#wrote, iclass 32, count 2 2006.257.20:43:14.29#ibcon#about to read 3, iclass 32, count 2 2006.257.20:43:14.32#ibcon#read 3, iclass 32, count 2 2006.257.20:43:14.32#ibcon#about to read 4, iclass 32, count 2 2006.257.20:43:14.32#ibcon#read 4, iclass 32, count 2 2006.257.20:43:14.32#ibcon#about to read 5, iclass 32, count 2 2006.257.20:43:14.32#ibcon#read 5, iclass 32, count 2 2006.257.20:43:14.32#ibcon#about to read 6, iclass 32, count 2 2006.257.20:43:14.32#ibcon#read 6, iclass 32, count 2 2006.257.20:43:14.32#ibcon#end of sib2, iclass 32, count 2 2006.257.20:43:14.32#ibcon#*after write, iclass 32, count 2 2006.257.20:43:14.32#ibcon#*before return 0, iclass 32, count 2 2006.257.20:43:14.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:14.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.20:43:14.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.20:43:14.32#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:14.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:14.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:14.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:14.44#ibcon#enter wrdev, iclass 32, count 0 2006.257.20:43:14.44#ibcon#first serial, iclass 32, count 0 2006.257.20:43:14.44#ibcon#enter sib2, iclass 32, count 0 2006.257.20:43:14.44#ibcon#flushed, iclass 32, count 0 2006.257.20:43:14.44#ibcon#about to write, iclass 32, count 0 2006.257.20:43:14.44#ibcon#wrote, iclass 32, count 0 2006.257.20:43:14.44#ibcon#about to read 3, iclass 32, count 0 2006.257.20:43:14.46#ibcon#read 3, iclass 32, count 0 2006.257.20:43:14.46#ibcon#about to read 4, iclass 32, count 0 2006.257.20:43:14.46#ibcon#read 4, iclass 32, count 0 2006.257.20:43:14.46#ibcon#about to read 5, iclass 32, count 0 2006.257.20:43:14.46#ibcon#read 5, iclass 32, count 0 2006.257.20:43:14.46#ibcon#about to read 6, iclass 32, count 0 2006.257.20:43:14.46#ibcon#read 6, iclass 32, count 0 2006.257.20:43:14.46#ibcon#end of sib2, iclass 32, count 0 2006.257.20:43:14.46#ibcon#*mode == 0, iclass 32, count 0 2006.257.20:43:14.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.20:43:14.46#ibcon#[27=USB\r\n] 2006.257.20:43:14.46#ibcon#*before write, iclass 32, count 0 2006.257.20:43:14.46#ibcon#enter sib2, iclass 32, count 0 2006.257.20:43:14.46#ibcon#flushed, iclass 32, count 0 2006.257.20:43:14.46#ibcon#about to write, iclass 32, count 0 2006.257.20:43:14.46#ibcon#wrote, iclass 32, count 0 2006.257.20:43:14.46#ibcon#about to read 3, iclass 32, count 0 2006.257.20:43:14.49#ibcon#read 3, iclass 32, count 0 2006.257.20:43:14.49#ibcon#about to read 4, iclass 32, count 0 2006.257.20:43:14.49#ibcon#read 4, iclass 32, count 0 2006.257.20:43:14.49#ibcon#about to read 5, iclass 32, count 0 2006.257.20:43:14.49#ibcon#read 5, iclass 32, count 0 2006.257.20:43:14.49#ibcon#about to read 6, iclass 32, count 0 2006.257.20:43:14.49#ibcon#read 6, iclass 32, count 0 2006.257.20:43:14.49#ibcon#end of sib2, iclass 32, count 0 2006.257.20:43:14.49#ibcon#*after write, iclass 32, count 0 2006.257.20:43:14.49#ibcon#*before return 0, iclass 32, count 0 2006.257.20:43:14.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:14.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.20:43:14.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.20:43:14.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.20:43:14.49$vck44/vblo=8,744.99 2006.257.20:43:14.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.20:43:14.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.20:43:14.49#ibcon#ireg 17 cls_cnt 0 2006.257.20:43:14.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:14.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:14.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:14.49#ibcon#enter wrdev, iclass 34, count 0 2006.257.20:43:14.49#ibcon#first serial, iclass 34, count 0 2006.257.20:43:14.49#ibcon#enter sib2, iclass 34, count 0 2006.257.20:43:14.49#ibcon#flushed, iclass 34, count 0 2006.257.20:43:14.49#ibcon#about to write, iclass 34, count 0 2006.257.20:43:14.49#ibcon#wrote, iclass 34, count 0 2006.257.20:43:14.49#ibcon#about to read 3, iclass 34, count 0 2006.257.20:43:14.51#ibcon#read 3, iclass 34, count 0 2006.257.20:43:14.51#ibcon#about to read 4, iclass 34, count 0 2006.257.20:43:14.51#ibcon#read 4, iclass 34, count 0 2006.257.20:43:14.51#ibcon#about to read 5, iclass 34, count 0 2006.257.20:43:14.51#ibcon#read 5, iclass 34, count 0 2006.257.20:43:14.51#ibcon#about to read 6, iclass 34, count 0 2006.257.20:43:14.51#ibcon#read 6, iclass 34, count 0 2006.257.20:43:14.51#ibcon#end of sib2, iclass 34, count 0 2006.257.20:43:14.51#ibcon#*mode == 0, iclass 34, count 0 2006.257.20:43:14.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.20:43:14.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.20:43:14.51#ibcon#*before write, iclass 34, count 0 2006.257.20:43:14.51#ibcon#enter sib2, iclass 34, count 0 2006.257.20:43:14.51#ibcon#flushed, iclass 34, count 0 2006.257.20:43:14.51#ibcon#about to write, iclass 34, count 0 2006.257.20:43:14.51#ibcon#wrote, iclass 34, count 0 2006.257.20:43:14.51#ibcon#about to read 3, iclass 34, count 0 2006.257.20:43:14.55#ibcon#read 3, iclass 34, count 0 2006.257.20:43:14.55#ibcon#about to read 4, iclass 34, count 0 2006.257.20:43:14.55#ibcon#read 4, iclass 34, count 0 2006.257.20:43:14.55#ibcon#about to read 5, iclass 34, count 0 2006.257.20:43:14.55#ibcon#read 5, iclass 34, count 0 2006.257.20:43:14.55#ibcon#about to read 6, iclass 34, count 0 2006.257.20:43:14.55#ibcon#read 6, iclass 34, count 0 2006.257.20:43:14.55#ibcon#end of sib2, iclass 34, count 0 2006.257.20:43:14.55#ibcon#*after write, iclass 34, count 0 2006.257.20:43:14.55#ibcon#*before return 0, iclass 34, count 0 2006.257.20:43:14.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:14.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.20:43:14.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.20:43:14.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.20:43:14.55$vck44/vb=8,4 2006.257.20:43:14.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.20:43:14.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.20:43:14.55#ibcon#ireg 11 cls_cnt 2 2006.257.20:43:14.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:14.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:14.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:14.61#ibcon#enter wrdev, iclass 36, count 2 2006.257.20:43:14.61#ibcon#first serial, iclass 36, count 2 2006.257.20:43:14.61#ibcon#enter sib2, iclass 36, count 2 2006.257.20:43:14.61#ibcon#flushed, iclass 36, count 2 2006.257.20:43:14.61#ibcon#about to write, iclass 36, count 2 2006.257.20:43:14.61#ibcon#wrote, iclass 36, count 2 2006.257.20:43:14.61#ibcon#about to read 3, iclass 36, count 2 2006.257.20:43:14.63#ibcon#read 3, iclass 36, count 2 2006.257.20:43:14.63#ibcon#about to read 4, iclass 36, count 2 2006.257.20:43:14.63#ibcon#read 4, iclass 36, count 2 2006.257.20:43:14.63#ibcon#about to read 5, iclass 36, count 2 2006.257.20:43:14.63#ibcon#read 5, iclass 36, count 2 2006.257.20:43:14.63#ibcon#about to read 6, iclass 36, count 2 2006.257.20:43:14.63#ibcon#read 6, iclass 36, count 2 2006.257.20:43:14.63#ibcon#end of sib2, iclass 36, count 2 2006.257.20:43:14.63#ibcon#*mode == 0, iclass 36, count 2 2006.257.20:43:14.63#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.20:43:14.63#ibcon#[27=AT08-04\r\n] 2006.257.20:43:14.63#ibcon#*before write, iclass 36, count 2 2006.257.20:43:14.63#ibcon#enter sib2, iclass 36, count 2 2006.257.20:43:14.63#ibcon#flushed, iclass 36, count 2 2006.257.20:43:14.63#ibcon#about to write, iclass 36, count 2 2006.257.20:43:14.63#ibcon#wrote, iclass 36, count 2 2006.257.20:43:14.63#ibcon#about to read 3, iclass 36, count 2 2006.257.20:43:14.66#ibcon#read 3, iclass 36, count 2 2006.257.20:43:14.66#ibcon#about to read 4, iclass 36, count 2 2006.257.20:43:14.66#ibcon#read 4, iclass 36, count 2 2006.257.20:43:14.66#ibcon#about to read 5, iclass 36, count 2 2006.257.20:43:14.66#ibcon#read 5, iclass 36, count 2 2006.257.20:43:14.66#ibcon#about to read 6, iclass 36, count 2 2006.257.20:43:14.66#ibcon#read 6, iclass 36, count 2 2006.257.20:43:14.66#ibcon#end of sib2, iclass 36, count 2 2006.257.20:43:14.66#ibcon#*after write, iclass 36, count 2 2006.257.20:43:14.66#ibcon#*before return 0, iclass 36, count 2 2006.257.20:43:14.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:14.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.20:43:14.66#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.20:43:14.66#ibcon#ireg 7 cls_cnt 0 2006.257.20:43:14.66#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:14.78#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:14.78#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:14.78#ibcon#enter wrdev, iclass 36, count 0 2006.257.20:43:14.78#ibcon#first serial, iclass 36, count 0 2006.257.20:43:14.78#ibcon#enter sib2, iclass 36, count 0 2006.257.20:43:14.78#ibcon#flushed, iclass 36, count 0 2006.257.20:43:14.78#ibcon#about to write, iclass 36, count 0 2006.257.20:43:14.78#ibcon#wrote, iclass 36, count 0 2006.257.20:43:14.78#ibcon#about to read 3, iclass 36, count 0 2006.257.20:43:14.80#ibcon#read 3, iclass 36, count 0 2006.257.20:43:14.80#ibcon#about to read 4, iclass 36, count 0 2006.257.20:43:14.80#ibcon#read 4, iclass 36, count 0 2006.257.20:43:14.80#ibcon#about to read 5, iclass 36, count 0 2006.257.20:43:14.80#ibcon#read 5, iclass 36, count 0 2006.257.20:43:14.80#ibcon#about to read 6, iclass 36, count 0 2006.257.20:43:14.80#ibcon#read 6, iclass 36, count 0 2006.257.20:43:14.80#ibcon#end of sib2, iclass 36, count 0 2006.257.20:43:14.80#ibcon#*mode == 0, iclass 36, count 0 2006.257.20:43:14.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.20:43:14.80#ibcon#[27=USB\r\n] 2006.257.20:43:14.80#ibcon#*before write, iclass 36, count 0 2006.257.20:43:14.80#ibcon#enter sib2, iclass 36, count 0 2006.257.20:43:14.80#ibcon#flushed, iclass 36, count 0 2006.257.20:43:14.80#ibcon#about to write, iclass 36, count 0 2006.257.20:43:14.80#ibcon#wrote, iclass 36, count 0 2006.257.20:43:14.80#ibcon#about to read 3, iclass 36, count 0 2006.257.20:43:14.83#ibcon#read 3, iclass 36, count 0 2006.257.20:43:14.83#ibcon#about to read 4, iclass 36, count 0 2006.257.20:43:14.83#ibcon#read 4, iclass 36, count 0 2006.257.20:43:14.83#ibcon#about to read 5, iclass 36, count 0 2006.257.20:43:14.83#ibcon#read 5, iclass 36, count 0 2006.257.20:43:14.83#ibcon#about to read 6, iclass 36, count 0 2006.257.20:43:14.83#ibcon#read 6, iclass 36, count 0 2006.257.20:43:14.83#ibcon#end of sib2, iclass 36, count 0 2006.257.20:43:14.83#ibcon#*after write, iclass 36, count 0 2006.257.20:43:14.83#ibcon#*before return 0, iclass 36, count 0 2006.257.20:43:14.83#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:14.83#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.20:43:14.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.20:43:14.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.20:43:14.83$vck44/vabw=wide 2006.257.20:43:14.83#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.20:43:14.83#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.20:43:14.83#ibcon#ireg 8 cls_cnt 0 2006.257.20:43:14.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:14.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:14.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:14.83#ibcon#enter wrdev, iclass 38, count 0 2006.257.20:43:14.83#ibcon#first serial, iclass 38, count 0 2006.257.20:43:14.83#ibcon#enter sib2, iclass 38, count 0 2006.257.20:43:14.83#ibcon#flushed, iclass 38, count 0 2006.257.20:43:14.83#ibcon#about to write, iclass 38, count 0 2006.257.20:43:14.83#ibcon#wrote, iclass 38, count 0 2006.257.20:43:14.83#ibcon#about to read 3, iclass 38, count 0 2006.257.20:43:14.85#ibcon#read 3, iclass 38, count 0 2006.257.20:43:14.85#ibcon#about to read 4, iclass 38, count 0 2006.257.20:43:14.85#ibcon#read 4, iclass 38, count 0 2006.257.20:43:14.85#ibcon#about to read 5, iclass 38, count 0 2006.257.20:43:14.85#ibcon#read 5, iclass 38, count 0 2006.257.20:43:14.85#ibcon#about to read 6, iclass 38, count 0 2006.257.20:43:14.85#ibcon#read 6, iclass 38, count 0 2006.257.20:43:14.85#ibcon#end of sib2, iclass 38, count 0 2006.257.20:43:14.85#ibcon#*mode == 0, iclass 38, count 0 2006.257.20:43:14.85#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.20:43:14.85#ibcon#[25=BW32\r\n] 2006.257.20:43:14.85#ibcon#*before write, iclass 38, count 0 2006.257.20:43:14.85#ibcon#enter sib2, iclass 38, count 0 2006.257.20:43:14.85#ibcon#flushed, iclass 38, count 0 2006.257.20:43:14.85#ibcon#about to write, iclass 38, count 0 2006.257.20:43:14.85#ibcon#wrote, iclass 38, count 0 2006.257.20:43:14.85#ibcon#about to read 3, iclass 38, count 0 2006.257.20:43:14.88#ibcon#read 3, iclass 38, count 0 2006.257.20:43:14.88#ibcon#about to read 4, iclass 38, count 0 2006.257.20:43:14.88#ibcon#read 4, iclass 38, count 0 2006.257.20:43:14.88#ibcon#about to read 5, iclass 38, count 0 2006.257.20:43:14.88#ibcon#read 5, iclass 38, count 0 2006.257.20:43:14.88#ibcon#about to read 6, iclass 38, count 0 2006.257.20:43:14.88#ibcon#read 6, iclass 38, count 0 2006.257.20:43:14.88#ibcon#end of sib2, iclass 38, count 0 2006.257.20:43:14.88#ibcon#*after write, iclass 38, count 0 2006.257.20:43:14.88#ibcon#*before return 0, iclass 38, count 0 2006.257.20:43:14.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:14.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.20:43:14.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.20:43:14.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.20:43:14.88$vck44/vbbw=wide 2006.257.20:43:14.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.20:43:14.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.20:43:14.88#ibcon#ireg 8 cls_cnt 0 2006.257.20:43:14.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:43:14.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:43:14.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:43:14.95#ibcon#enter wrdev, iclass 40, count 0 2006.257.20:43:14.95#ibcon#first serial, iclass 40, count 0 2006.257.20:43:14.95#ibcon#enter sib2, iclass 40, count 0 2006.257.20:43:14.95#ibcon#flushed, iclass 40, count 0 2006.257.20:43:14.95#ibcon#about to write, iclass 40, count 0 2006.257.20:43:14.95#ibcon#wrote, iclass 40, count 0 2006.257.20:43:14.95#ibcon#about to read 3, iclass 40, count 0 2006.257.20:43:14.97#ibcon#read 3, iclass 40, count 0 2006.257.20:43:14.97#ibcon#about to read 4, iclass 40, count 0 2006.257.20:43:14.97#ibcon#read 4, iclass 40, count 0 2006.257.20:43:14.97#ibcon#about to read 5, iclass 40, count 0 2006.257.20:43:14.97#ibcon#read 5, iclass 40, count 0 2006.257.20:43:14.97#ibcon#about to read 6, iclass 40, count 0 2006.257.20:43:14.97#ibcon#read 6, iclass 40, count 0 2006.257.20:43:14.97#ibcon#end of sib2, iclass 40, count 0 2006.257.20:43:14.97#ibcon#*mode == 0, iclass 40, count 0 2006.257.20:43:14.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.20:43:14.97#ibcon#[27=BW32\r\n] 2006.257.20:43:14.97#ibcon#*before write, iclass 40, count 0 2006.257.20:43:14.97#ibcon#enter sib2, iclass 40, count 0 2006.257.20:43:14.97#ibcon#flushed, iclass 40, count 0 2006.257.20:43:14.97#ibcon#about to write, iclass 40, count 0 2006.257.20:43:14.97#ibcon#wrote, iclass 40, count 0 2006.257.20:43:14.97#ibcon#about to read 3, iclass 40, count 0 2006.257.20:43:15.00#ibcon#read 3, iclass 40, count 0 2006.257.20:43:15.00#ibcon#about to read 4, iclass 40, count 0 2006.257.20:43:15.00#ibcon#read 4, iclass 40, count 0 2006.257.20:43:15.00#ibcon#about to read 5, iclass 40, count 0 2006.257.20:43:15.00#ibcon#read 5, iclass 40, count 0 2006.257.20:43:15.00#ibcon#about to read 6, iclass 40, count 0 2006.257.20:43:15.00#ibcon#read 6, iclass 40, count 0 2006.257.20:43:15.00#ibcon#end of sib2, iclass 40, count 0 2006.257.20:43:15.00#ibcon#*after write, iclass 40, count 0 2006.257.20:43:15.00#ibcon#*before return 0, iclass 40, count 0 2006.257.20:43:15.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:43:15.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:43:15.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.20:43:15.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.20:43:15.00$setupk4/ifdk4 2006.257.20:43:15.00$ifdk4/lo= 2006.257.20:43:15.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.20:43:15.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.20:43:15.00$ifdk4/patch= 2006.257.20:43:15.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.20:43:15.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.20:43:15.00$setupk4/!*+20s 2006.257.20:43:19.80#abcon#<5=/14 0.7 3.2 17.16 981014.9\r\n> 2006.257.20:43:19.82#abcon#{5=INTERFACE CLEAR} 2006.257.20:43:19.88#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:43:29.51$setupk4/"tpicd 2006.257.20:43:29.51$setupk4/echo=off 2006.257.20:43:29.51$setupk4/xlog=off 2006.257.20:43:29.51:!2006.257.20:45:19 2006.257.20:43:57.13#trakl#Source acquired 2006.257.20:43:59.13#flagr#flagr/antenna,acquired 2006.257.20:45:19.00:preob 2006.257.20:45:19.14/onsource/TRACKING 2006.257.20:45:19.14:!2006.257.20:45:29 2006.257.20:45:29.00:"tape 2006.257.20:45:29.00:"st=record 2006.257.20:45:29.00:data_valid=on 2006.257.20:45:29.00:midob 2006.257.20:45:29.14/onsource/TRACKING 2006.257.20:45:29.14/wx/17.18,1014.9,98 2006.257.20:45:29.31/cable/+6.4834E-03 2006.257.20:45:30.40/va/01,08,usb,yes,31,33 2006.257.20:45:30.40/va/02,07,usb,yes,34,34 2006.257.20:45:30.40/va/03,08,usb,yes,30,32 2006.257.20:45:30.40/va/04,07,usb,yes,35,36 2006.257.20:45:30.40/va/05,04,usb,yes,31,31 2006.257.20:45:30.40/va/06,04,usb,yes,34,34 2006.257.20:45:30.40/va/07,04,usb,yes,35,35 2006.257.20:45:30.40/va/08,04,usb,yes,29,36 2006.257.20:45:30.63/valo/01,524.99,yes,locked 2006.257.20:45:30.63/valo/02,534.99,yes,locked 2006.257.20:45:30.63/valo/03,564.99,yes,locked 2006.257.20:45:30.63/valo/04,624.99,yes,locked 2006.257.20:45:30.63/valo/05,734.99,yes,locked 2006.257.20:45:30.63/valo/06,814.99,yes,locked 2006.257.20:45:30.63/valo/07,864.99,yes,locked 2006.257.20:45:30.63/valo/08,884.99,yes,locked 2006.257.20:45:31.72/vb/01,04,usb,yes,30,28 2006.257.20:45:31.72/vb/02,05,usb,yes,29,28 2006.257.20:45:31.72/vb/03,04,usb,yes,29,32 2006.257.20:45:31.72/vb/04,05,usb,yes,30,29 2006.257.20:45:31.72/vb/05,04,usb,yes,26,29 2006.257.20:45:31.72/vb/06,04,usb,yes,31,27 2006.257.20:45:31.72/vb/07,04,usb,yes,30,30 2006.257.20:45:31.72/vb/08,04,usb,yes,28,31 2006.257.20:45:31.95/vblo/01,629.99,yes,locked 2006.257.20:45:31.95/vblo/02,634.99,yes,locked 2006.257.20:45:31.95/vblo/03,649.99,yes,locked 2006.257.20:45:31.95/vblo/04,679.99,yes,locked 2006.257.20:45:31.95/vblo/05,709.99,yes,locked 2006.257.20:45:31.95/vblo/06,719.99,yes,locked 2006.257.20:45:31.95/vblo/07,734.99,yes,locked 2006.257.20:45:31.95/vblo/08,744.99,yes,locked 2006.257.20:45:32.10/vabw/8 2006.257.20:45:32.25/vbbw/8 2006.257.20:45:32.34/xfe/off,on,15.2 2006.257.20:45:32.71/ifatt/23,28,28,28 2006.257.20:45:33.07/fmout-gps/S +4.57E-07 2006.257.20:45:33.11:!2006.257.20:46:19 2006.257.20:46:19.01:data_valid=off 2006.257.20:46:19.01:"et 2006.257.20:46:19.01:!+3s 2006.257.20:46:22.02:"tape 2006.257.20:46:22.02:postob 2006.257.20:46:22.12/cable/+6.4840E-03 2006.257.20:46:22.12/wx/17.19,1014.9,98 2006.257.20:46:22.18/fmout-gps/S +4.57E-07 2006.257.20:46:22.18:scan_name=257-2048,jd0609,210 2006.257.20:46:22.18:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.257.20:46:23.14#flagr#flagr/antenna,new-source 2006.257.20:46:23.14:checkk5 2006.257.20:46:23.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.20:46:23.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.20:46:24.15/chk_autoobs//k5ts3/ autoobs is running! 2006.257.20:46:24.49/chk_autoobs//k5ts4/ autoobs is running! 2006.257.20:46:24.83/chk_obsdata//k5ts1/T2572045??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.20:46:25.17/chk_obsdata//k5ts2/T2572045??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.20:46:25.50/chk_obsdata//k5ts3/T2572045??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.20:46:25.84/chk_obsdata//k5ts4/T2572045??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.20:46:26.50/k5log//k5ts1_log_newline 2006.257.20:46:27.15/k5log//k5ts2_log_newline 2006.257.20:46:27.80/k5log//k5ts3_log_newline 2006.257.20:46:28.45/k5log//k5ts4_log_newline 2006.257.20:46:28.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.20:46:28.48:setupk4=1 2006.257.20:46:28.48$setupk4/echo=on 2006.257.20:46:28.48$setupk4/pcalon 2006.257.20:46:28.48$pcalon/"no phase cal control is implemented here 2006.257.20:46:28.48$setupk4/"tpicd=stop 2006.257.20:46:28.48$setupk4/"rec=synch_on 2006.257.20:46:28.48$setupk4/"rec_mode=128 2006.257.20:46:28.48$setupk4/!* 2006.257.20:46:28.48$setupk4/recpk4 2006.257.20:46:28.48$recpk4/recpatch= 2006.257.20:46:28.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.20:46:28.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.20:46:28.48$setupk4/vck44 2006.257.20:46:28.48$vck44/valo=1,524.99 2006.257.20:46:28.48#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.20:46:28.48#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.20:46:28.48#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:28.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:28.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:28.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:28.48#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:46:28.48#ibcon#first serial, iclass 13, count 0 2006.257.20:46:28.48#ibcon#enter sib2, iclass 13, count 0 2006.257.20:46:28.48#ibcon#flushed, iclass 13, count 0 2006.257.20:46:28.48#ibcon#about to write, iclass 13, count 0 2006.257.20:46:28.48#ibcon#wrote, iclass 13, count 0 2006.257.20:46:28.48#ibcon#about to read 3, iclass 13, count 0 2006.257.20:46:28.50#ibcon#read 3, iclass 13, count 0 2006.257.20:46:28.50#ibcon#about to read 4, iclass 13, count 0 2006.257.20:46:28.50#ibcon#read 4, iclass 13, count 0 2006.257.20:46:28.50#ibcon#about to read 5, iclass 13, count 0 2006.257.20:46:28.50#ibcon#read 5, iclass 13, count 0 2006.257.20:46:28.50#ibcon#about to read 6, iclass 13, count 0 2006.257.20:46:28.50#ibcon#read 6, iclass 13, count 0 2006.257.20:46:28.50#ibcon#end of sib2, iclass 13, count 0 2006.257.20:46:28.50#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:46:28.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:46:28.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.20:46:28.50#ibcon#*before write, iclass 13, count 0 2006.257.20:46:28.50#ibcon#enter sib2, iclass 13, count 0 2006.257.20:46:28.50#ibcon#flushed, iclass 13, count 0 2006.257.20:46:28.50#ibcon#about to write, iclass 13, count 0 2006.257.20:46:28.50#ibcon#wrote, iclass 13, count 0 2006.257.20:46:28.50#ibcon#about to read 3, iclass 13, count 0 2006.257.20:46:28.55#ibcon#read 3, iclass 13, count 0 2006.257.20:46:28.55#ibcon#about to read 4, iclass 13, count 0 2006.257.20:46:28.55#ibcon#read 4, iclass 13, count 0 2006.257.20:46:28.55#ibcon#about to read 5, iclass 13, count 0 2006.257.20:46:28.55#ibcon#read 5, iclass 13, count 0 2006.257.20:46:28.55#ibcon#about to read 6, iclass 13, count 0 2006.257.20:46:28.55#ibcon#read 6, iclass 13, count 0 2006.257.20:46:28.55#ibcon#end of sib2, iclass 13, count 0 2006.257.20:46:28.55#ibcon#*after write, iclass 13, count 0 2006.257.20:46:28.55#ibcon#*before return 0, iclass 13, count 0 2006.257.20:46:28.55#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:28.55#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:28.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:46:28.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:46:28.55$vck44/va=1,8 2006.257.20:46:28.55#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.20:46:28.55#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.20:46:28.55#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:28.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:28.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:28.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:28.55#ibcon#enter wrdev, iclass 15, count 2 2006.257.20:46:28.55#ibcon#first serial, iclass 15, count 2 2006.257.20:46:28.55#ibcon#enter sib2, iclass 15, count 2 2006.257.20:46:28.55#ibcon#flushed, iclass 15, count 2 2006.257.20:46:28.55#ibcon#about to write, iclass 15, count 2 2006.257.20:46:28.55#ibcon#wrote, iclass 15, count 2 2006.257.20:46:28.55#ibcon#about to read 3, iclass 15, count 2 2006.257.20:46:28.57#ibcon#read 3, iclass 15, count 2 2006.257.20:46:28.57#ibcon#about to read 4, iclass 15, count 2 2006.257.20:46:28.57#ibcon#read 4, iclass 15, count 2 2006.257.20:46:28.57#ibcon#about to read 5, iclass 15, count 2 2006.257.20:46:28.57#ibcon#read 5, iclass 15, count 2 2006.257.20:46:28.57#ibcon#about to read 6, iclass 15, count 2 2006.257.20:46:28.57#ibcon#read 6, iclass 15, count 2 2006.257.20:46:28.57#ibcon#end of sib2, iclass 15, count 2 2006.257.20:46:28.57#ibcon#*mode == 0, iclass 15, count 2 2006.257.20:46:28.57#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.20:46:28.57#ibcon#[25=AT01-08\r\n] 2006.257.20:46:28.57#ibcon#*before write, iclass 15, count 2 2006.257.20:46:28.57#ibcon#enter sib2, iclass 15, count 2 2006.257.20:46:28.57#ibcon#flushed, iclass 15, count 2 2006.257.20:46:28.57#ibcon#about to write, iclass 15, count 2 2006.257.20:46:28.57#ibcon#wrote, iclass 15, count 2 2006.257.20:46:28.57#ibcon#about to read 3, iclass 15, count 2 2006.257.20:46:28.60#ibcon#read 3, iclass 15, count 2 2006.257.20:46:28.60#ibcon#about to read 4, iclass 15, count 2 2006.257.20:46:28.60#ibcon#read 4, iclass 15, count 2 2006.257.20:46:28.60#ibcon#about to read 5, iclass 15, count 2 2006.257.20:46:28.60#ibcon#read 5, iclass 15, count 2 2006.257.20:46:28.60#ibcon#about to read 6, iclass 15, count 2 2006.257.20:46:28.60#ibcon#read 6, iclass 15, count 2 2006.257.20:46:28.60#ibcon#end of sib2, iclass 15, count 2 2006.257.20:46:28.60#ibcon#*after write, iclass 15, count 2 2006.257.20:46:28.60#ibcon#*before return 0, iclass 15, count 2 2006.257.20:46:28.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:28.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:28.60#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.20:46:28.60#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:28.60#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:28.72#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:28.72#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:28.72#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:46:28.72#ibcon#first serial, iclass 15, count 0 2006.257.20:46:28.72#ibcon#enter sib2, iclass 15, count 0 2006.257.20:46:28.72#ibcon#flushed, iclass 15, count 0 2006.257.20:46:28.72#ibcon#about to write, iclass 15, count 0 2006.257.20:46:28.72#ibcon#wrote, iclass 15, count 0 2006.257.20:46:28.72#ibcon#about to read 3, iclass 15, count 0 2006.257.20:46:28.74#ibcon#read 3, iclass 15, count 0 2006.257.20:46:28.74#ibcon#about to read 4, iclass 15, count 0 2006.257.20:46:28.74#ibcon#read 4, iclass 15, count 0 2006.257.20:46:28.74#ibcon#about to read 5, iclass 15, count 0 2006.257.20:46:28.74#ibcon#read 5, iclass 15, count 0 2006.257.20:46:28.74#ibcon#about to read 6, iclass 15, count 0 2006.257.20:46:28.74#ibcon#read 6, iclass 15, count 0 2006.257.20:46:28.74#ibcon#end of sib2, iclass 15, count 0 2006.257.20:46:28.74#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:46:28.74#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:46:28.74#ibcon#[25=USB\r\n] 2006.257.20:46:28.74#ibcon#*before write, iclass 15, count 0 2006.257.20:46:28.74#ibcon#enter sib2, iclass 15, count 0 2006.257.20:46:28.74#ibcon#flushed, iclass 15, count 0 2006.257.20:46:28.74#ibcon#about to write, iclass 15, count 0 2006.257.20:46:28.74#ibcon#wrote, iclass 15, count 0 2006.257.20:46:28.74#ibcon#about to read 3, iclass 15, count 0 2006.257.20:46:28.77#ibcon#read 3, iclass 15, count 0 2006.257.20:46:28.77#ibcon#about to read 4, iclass 15, count 0 2006.257.20:46:28.77#ibcon#read 4, iclass 15, count 0 2006.257.20:46:28.77#ibcon#about to read 5, iclass 15, count 0 2006.257.20:46:28.77#ibcon#read 5, iclass 15, count 0 2006.257.20:46:28.77#ibcon#about to read 6, iclass 15, count 0 2006.257.20:46:28.77#ibcon#read 6, iclass 15, count 0 2006.257.20:46:28.77#ibcon#end of sib2, iclass 15, count 0 2006.257.20:46:28.77#ibcon#*after write, iclass 15, count 0 2006.257.20:46:28.77#ibcon#*before return 0, iclass 15, count 0 2006.257.20:46:28.77#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:28.77#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:28.77#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:46:28.77#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:46:28.77$vck44/valo=2,534.99 2006.257.20:46:28.77#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.20:46:28.77#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.20:46:28.77#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:28.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:28.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:28.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:28.77#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:46:28.77#ibcon#first serial, iclass 17, count 0 2006.257.20:46:28.77#ibcon#enter sib2, iclass 17, count 0 2006.257.20:46:28.77#ibcon#flushed, iclass 17, count 0 2006.257.20:46:28.77#ibcon#about to write, iclass 17, count 0 2006.257.20:46:28.77#ibcon#wrote, iclass 17, count 0 2006.257.20:46:28.77#ibcon#about to read 3, iclass 17, count 0 2006.257.20:46:28.79#ibcon#read 3, iclass 17, count 0 2006.257.20:46:28.79#ibcon#about to read 4, iclass 17, count 0 2006.257.20:46:28.79#ibcon#read 4, iclass 17, count 0 2006.257.20:46:28.79#ibcon#about to read 5, iclass 17, count 0 2006.257.20:46:28.79#ibcon#read 5, iclass 17, count 0 2006.257.20:46:28.79#ibcon#about to read 6, iclass 17, count 0 2006.257.20:46:28.79#ibcon#read 6, iclass 17, count 0 2006.257.20:46:28.79#ibcon#end of sib2, iclass 17, count 0 2006.257.20:46:28.79#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:46:28.79#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:46:28.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.20:46:28.79#ibcon#*before write, iclass 17, count 0 2006.257.20:46:28.79#ibcon#enter sib2, iclass 17, count 0 2006.257.20:46:28.79#ibcon#flushed, iclass 17, count 0 2006.257.20:46:28.79#ibcon#about to write, iclass 17, count 0 2006.257.20:46:28.79#ibcon#wrote, iclass 17, count 0 2006.257.20:46:28.79#ibcon#about to read 3, iclass 17, count 0 2006.257.20:46:28.83#ibcon#read 3, iclass 17, count 0 2006.257.20:46:28.83#ibcon#about to read 4, iclass 17, count 0 2006.257.20:46:28.83#ibcon#read 4, iclass 17, count 0 2006.257.20:46:28.83#ibcon#about to read 5, iclass 17, count 0 2006.257.20:46:28.83#ibcon#read 5, iclass 17, count 0 2006.257.20:46:28.83#ibcon#about to read 6, iclass 17, count 0 2006.257.20:46:28.83#ibcon#read 6, iclass 17, count 0 2006.257.20:46:28.83#ibcon#end of sib2, iclass 17, count 0 2006.257.20:46:28.83#ibcon#*after write, iclass 17, count 0 2006.257.20:46:28.83#ibcon#*before return 0, iclass 17, count 0 2006.257.20:46:28.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:28.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:28.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:46:28.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:46:28.83$vck44/va=2,7 2006.257.20:46:28.83#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.20:46:28.83#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.20:46:28.83#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:28.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:28.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:28.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:28.89#ibcon#enter wrdev, iclass 19, count 2 2006.257.20:46:28.89#ibcon#first serial, iclass 19, count 2 2006.257.20:46:28.89#ibcon#enter sib2, iclass 19, count 2 2006.257.20:46:28.89#ibcon#flushed, iclass 19, count 2 2006.257.20:46:28.89#ibcon#about to write, iclass 19, count 2 2006.257.20:46:28.89#ibcon#wrote, iclass 19, count 2 2006.257.20:46:28.89#ibcon#about to read 3, iclass 19, count 2 2006.257.20:46:28.91#ibcon#read 3, iclass 19, count 2 2006.257.20:46:28.91#ibcon#about to read 4, iclass 19, count 2 2006.257.20:46:28.91#ibcon#read 4, iclass 19, count 2 2006.257.20:46:28.91#ibcon#about to read 5, iclass 19, count 2 2006.257.20:46:28.91#ibcon#read 5, iclass 19, count 2 2006.257.20:46:28.91#ibcon#about to read 6, iclass 19, count 2 2006.257.20:46:28.91#ibcon#read 6, iclass 19, count 2 2006.257.20:46:28.91#ibcon#end of sib2, iclass 19, count 2 2006.257.20:46:28.91#ibcon#*mode == 0, iclass 19, count 2 2006.257.20:46:28.91#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.20:46:28.91#ibcon#[25=AT02-07\r\n] 2006.257.20:46:28.91#ibcon#*before write, iclass 19, count 2 2006.257.20:46:28.91#ibcon#enter sib2, iclass 19, count 2 2006.257.20:46:28.91#ibcon#flushed, iclass 19, count 2 2006.257.20:46:28.91#ibcon#about to write, iclass 19, count 2 2006.257.20:46:28.91#ibcon#wrote, iclass 19, count 2 2006.257.20:46:28.91#ibcon#about to read 3, iclass 19, count 2 2006.257.20:46:28.94#ibcon#read 3, iclass 19, count 2 2006.257.20:46:28.94#ibcon#about to read 4, iclass 19, count 2 2006.257.20:46:28.94#ibcon#read 4, iclass 19, count 2 2006.257.20:46:28.94#ibcon#about to read 5, iclass 19, count 2 2006.257.20:46:28.94#ibcon#read 5, iclass 19, count 2 2006.257.20:46:28.94#ibcon#about to read 6, iclass 19, count 2 2006.257.20:46:28.94#ibcon#read 6, iclass 19, count 2 2006.257.20:46:28.94#ibcon#end of sib2, iclass 19, count 2 2006.257.20:46:28.94#ibcon#*after write, iclass 19, count 2 2006.257.20:46:28.94#ibcon#*before return 0, iclass 19, count 2 2006.257.20:46:28.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:28.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:28.94#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.20:46:28.94#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:28.94#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:29.06#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:29.06#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:29.06#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:46:29.06#ibcon#first serial, iclass 19, count 0 2006.257.20:46:29.06#ibcon#enter sib2, iclass 19, count 0 2006.257.20:46:29.06#ibcon#flushed, iclass 19, count 0 2006.257.20:46:29.06#ibcon#about to write, iclass 19, count 0 2006.257.20:46:29.06#ibcon#wrote, iclass 19, count 0 2006.257.20:46:29.06#ibcon#about to read 3, iclass 19, count 0 2006.257.20:46:29.08#ibcon#read 3, iclass 19, count 0 2006.257.20:46:29.08#ibcon#about to read 4, iclass 19, count 0 2006.257.20:46:29.08#ibcon#read 4, iclass 19, count 0 2006.257.20:46:29.08#ibcon#about to read 5, iclass 19, count 0 2006.257.20:46:29.08#ibcon#read 5, iclass 19, count 0 2006.257.20:46:29.08#ibcon#about to read 6, iclass 19, count 0 2006.257.20:46:29.08#ibcon#read 6, iclass 19, count 0 2006.257.20:46:29.08#ibcon#end of sib2, iclass 19, count 0 2006.257.20:46:29.08#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:46:29.08#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:46:29.08#ibcon#[25=USB\r\n] 2006.257.20:46:29.08#ibcon#*before write, iclass 19, count 0 2006.257.20:46:29.08#ibcon#enter sib2, iclass 19, count 0 2006.257.20:46:29.08#ibcon#flushed, iclass 19, count 0 2006.257.20:46:29.08#ibcon#about to write, iclass 19, count 0 2006.257.20:46:29.08#ibcon#wrote, iclass 19, count 0 2006.257.20:46:29.08#ibcon#about to read 3, iclass 19, count 0 2006.257.20:46:29.11#ibcon#read 3, iclass 19, count 0 2006.257.20:46:29.11#ibcon#about to read 4, iclass 19, count 0 2006.257.20:46:29.11#ibcon#read 4, iclass 19, count 0 2006.257.20:46:29.11#ibcon#about to read 5, iclass 19, count 0 2006.257.20:46:29.11#ibcon#read 5, iclass 19, count 0 2006.257.20:46:29.11#ibcon#about to read 6, iclass 19, count 0 2006.257.20:46:29.11#ibcon#read 6, iclass 19, count 0 2006.257.20:46:29.11#ibcon#end of sib2, iclass 19, count 0 2006.257.20:46:29.11#ibcon#*after write, iclass 19, count 0 2006.257.20:46:29.11#ibcon#*before return 0, iclass 19, count 0 2006.257.20:46:29.11#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:29.11#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:29.11#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:46:29.11#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:46:29.11$vck44/valo=3,564.99 2006.257.20:46:29.11#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.20:46:29.11#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.20:46:29.11#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:29.11#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:29.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:29.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:29.11#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:46:29.11#ibcon#first serial, iclass 21, count 0 2006.257.20:46:29.11#ibcon#enter sib2, iclass 21, count 0 2006.257.20:46:29.11#ibcon#flushed, iclass 21, count 0 2006.257.20:46:29.11#ibcon#about to write, iclass 21, count 0 2006.257.20:46:29.11#ibcon#wrote, iclass 21, count 0 2006.257.20:46:29.11#ibcon#about to read 3, iclass 21, count 0 2006.257.20:46:29.13#ibcon#read 3, iclass 21, count 0 2006.257.20:46:29.13#ibcon#about to read 4, iclass 21, count 0 2006.257.20:46:29.13#ibcon#read 4, iclass 21, count 0 2006.257.20:46:29.13#ibcon#about to read 5, iclass 21, count 0 2006.257.20:46:29.13#ibcon#read 5, iclass 21, count 0 2006.257.20:46:29.13#ibcon#about to read 6, iclass 21, count 0 2006.257.20:46:29.13#ibcon#read 6, iclass 21, count 0 2006.257.20:46:29.13#ibcon#end of sib2, iclass 21, count 0 2006.257.20:46:29.13#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:46:29.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:46:29.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.20:46:29.13#ibcon#*before write, iclass 21, count 0 2006.257.20:46:29.13#ibcon#enter sib2, iclass 21, count 0 2006.257.20:46:29.13#ibcon#flushed, iclass 21, count 0 2006.257.20:46:29.13#ibcon#about to write, iclass 21, count 0 2006.257.20:46:29.13#ibcon#wrote, iclass 21, count 0 2006.257.20:46:29.13#ibcon#about to read 3, iclass 21, count 0 2006.257.20:46:29.17#ibcon#read 3, iclass 21, count 0 2006.257.20:46:29.17#ibcon#about to read 4, iclass 21, count 0 2006.257.20:46:29.17#ibcon#read 4, iclass 21, count 0 2006.257.20:46:29.17#ibcon#about to read 5, iclass 21, count 0 2006.257.20:46:29.17#ibcon#read 5, iclass 21, count 0 2006.257.20:46:29.17#ibcon#about to read 6, iclass 21, count 0 2006.257.20:46:29.17#ibcon#read 6, iclass 21, count 0 2006.257.20:46:29.17#ibcon#end of sib2, iclass 21, count 0 2006.257.20:46:29.17#ibcon#*after write, iclass 21, count 0 2006.257.20:46:29.17#ibcon#*before return 0, iclass 21, count 0 2006.257.20:46:29.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:29.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:29.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:46:29.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:46:29.17$vck44/va=3,8 2006.257.20:46:29.17#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.20:46:29.17#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.20:46:29.17#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:29.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:29.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:29.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:29.23#ibcon#enter wrdev, iclass 23, count 2 2006.257.20:46:29.23#ibcon#first serial, iclass 23, count 2 2006.257.20:46:29.23#ibcon#enter sib2, iclass 23, count 2 2006.257.20:46:29.23#ibcon#flushed, iclass 23, count 2 2006.257.20:46:29.23#ibcon#about to write, iclass 23, count 2 2006.257.20:46:29.23#ibcon#wrote, iclass 23, count 2 2006.257.20:46:29.23#ibcon#about to read 3, iclass 23, count 2 2006.257.20:46:29.25#ibcon#read 3, iclass 23, count 2 2006.257.20:46:29.25#ibcon#about to read 4, iclass 23, count 2 2006.257.20:46:29.25#ibcon#read 4, iclass 23, count 2 2006.257.20:46:29.25#ibcon#about to read 5, iclass 23, count 2 2006.257.20:46:29.25#ibcon#read 5, iclass 23, count 2 2006.257.20:46:29.25#ibcon#about to read 6, iclass 23, count 2 2006.257.20:46:29.25#ibcon#read 6, iclass 23, count 2 2006.257.20:46:29.25#ibcon#end of sib2, iclass 23, count 2 2006.257.20:46:29.25#ibcon#*mode == 0, iclass 23, count 2 2006.257.20:46:29.25#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.20:46:29.25#ibcon#[25=AT03-08\r\n] 2006.257.20:46:29.25#ibcon#*before write, iclass 23, count 2 2006.257.20:46:29.25#ibcon#enter sib2, iclass 23, count 2 2006.257.20:46:29.25#ibcon#flushed, iclass 23, count 2 2006.257.20:46:29.25#ibcon#about to write, iclass 23, count 2 2006.257.20:46:29.25#ibcon#wrote, iclass 23, count 2 2006.257.20:46:29.25#ibcon#about to read 3, iclass 23, count 2 2006.257.20:46:29.28#ibcon#read 3, iclass 23, count 2 2006.257.20:46:29.28#ibcon#about to read 4, iclass 23, count 2 2006.257.20:46:29.28#ibcon#read 4, iclass 23, count 2 2006.257.20:46:29.28#ibcon#about to read 5, iclass 23, count 2 2006.257.20:46:29.28#ibcon#read 5, iclass 23, count 2 2006.257.20:46:29.28#ibcon#about to read 6, iclass 23, count 2 2006.257.20:46:29.28#ibcon#read 6, iclass 23, count 2 2006.257.20:46:29.28#ibcon#end of sib2, iclass 23, count 2 2006.257.20:46:29.28#ibcon#*after write, iclass 23, count 2 2006.257.20:46:29.28#ibcon#*before return 0, iclass 23, count 2 2006.257.20:46:29.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:29.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:29.28#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.20:46:29.28#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:29.28#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:29.40#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:29.40#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:29.40#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:46:29.40#ibcon#first serial, iclass 23, count 0 2006.257.20:46:29.40#ibcon#enter sib2, iclass 23, count 0 2006.257.20:46:29.40#ibcon#flushed, iclass 23, count 0 2006.257.20:46:29.40#ibcon#about to write, iclass 23, count 0 2006.257.20:46:29.40#ibcon#wrote, iclass 23, count 0 2006.257.20:46:29.40#ibcon#about to read 3, iclass 23, count 0 2006.257.20:46:29.42#ibcon#read 3, iclass 23, count 0 2006.257.20:46:29.42#ibcon#about to read 4, iclass 23, count 0 2006.257.20:46:29.42#ibcon#read 4, iclass 23, count 0 2006.257.20:46:29.42#ibcon#about to read 5, iclass 23, count 0 2006.257.20:46:29.42#ibcon#read 5, iclass 23, count 0 2006.257.20:46:29.42#ibcon#about to read 6, iclass 23, count 0 2006.257.20:46:29.42#ibcon#read 6, iclass 23, count 0 2006.257.20:46:29.42#ibcon#end of sib2, iclass 23, count 0 2006.257.20:46:29.42#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:46:29.42#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:46:29.42#ibcon#[25=USB\r\n] 2006.257.20:46:29.42#ibcon#*before write, iclass 23, count 0 2006.257.20:46:29.42#ibcon#enter sib2, iclass 23, count 0 2006.257.20:46:29.42#ibcon#flushed, iclass 23, count 0 2006.257.20:46:29.42#ibcon#about to write, iclass 23, count 0 2006.257.20:46:29.42#ibcon#wrote, iclass 23, count 0 2006.257.20:46:29.42#ibcon#about to read 3, iclass 23, count 0 2006.257.20:46:29.45#ibcon#read 3, iclass 23, count 0 2006.257.20:46:29.45#ibcon#about to read 4, iclass 23, count 0 2006.257.20:46:29.45#ibcon#read 4, iclass 23, count 0 2006.257.20:46:29.45#ibcon#about to read 5, iclass 23, count 0 2006.257.20:46:29.45#ibcon#read 5, iclass 23, count 0 2006.257.20:46:29.45#ibcon#about to read 6, iclass 23, count 0 2006.257.20:46:29.45#ibcon#read 6, iclass 23, count 0 2006.257.20:46:29.45#ibcon#end of sib2, iclass 23, count 0 2006.257.20:46:29.45#ibcon#*after write, iclass 23, count 0 2006.257.20:46:29.45#ibcon#*before return 0, iclass 23, count 0 2006.257.20:46:29.45#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:29.45#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:29.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:46:29.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:46:29.45$vck44/valo=4,624.99 2006.257.20:46:29.45#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.20:46:29.45#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.20:46:29.45#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:29.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:29.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:29.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:29.45#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:46:29.45#ibcon#first serial, iclass 25, count 0 2006.257.20:46:29.45#ibcon#enter sib2, iclass 25, count 0 2006.257.20:46:29.45#ibcon#flushed, iclass 25, count 0 2006.257.20:46:29.45#ibcon#about to write, iclass 25, count 0 2006.257.20:46:29.45#ibcon#wrote, iclass 25, count 0 2006.257.20:46:29.45#ibcon#about to read 3, iclass 25, count 0 2006.257.20:46:29.47#ibcon#read 3, iclass 25, count 0 2006.257.20:46:29.47#ibcon#about to read 4, iclass 25, count 0 2006.257.20:46:29.47#ibcon#read 4, iclass 25, count 0 2006.257.20:46:29.47#ibcon#about to read 5, iclass 25, count 0 2006.257.20:46:29.47#ibcon#read 5, iclass 25, count 0 2006.257.20:46:29.47#ibcon#about to read 6, iclass 25, count 0 2006.257.20:46:29.47#ibcon#read 6, iclass 25, count 0 2006.257.20:46:29.47#ibcon#end of sib2, iclass 25, count 0 2006.257.20:46:29.47#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:46:29.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:46:29.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.20:46:29.47#ibcon#*before write, iclass 25, count 0 2006.257.20:46:29.47#ibcon#enter sib2, iclass 25, count 0 2006.257.20:46:29.47#ibcon#flushed, iclass 25, count 0 2006.257.20:46:29.47#ibcon#about to write, iclass 25, count 0 2006.257.20:46:29.47#ibcon#wrote, iclass 25, count 0 2006.257.20:46:29.47#ibcon#about to read 3, iclass 25, count 0 2006.257.20:46:29.51#ibcon#read 3, iclass 25, count 0 2006.257.20:46:29.51#ibcon#about to read 4, iclass 25, count 0 2006.257.20:46:29.51#ibcon#read 4, iclass 25, count 0 2006.257.20:46:29.51#ibcon#about to read 5, iclass 25, count 0 2006.257.20:46:29.51#ibcon#read 5, iclass 25, count 0 2006.257.20:46:29.51#ibcon#about to read 6, iclass 25, count 0 2006.257.20:46:29.51#ibcon#read 6, iclass 25, count 0 2006.257.20:46:29.51#ibcon#end of sib2, iclass 25, count 0 2006.257.20:46:29.51#ibcon#*after write, iclass 25, count 0 2006.257.20:46:29.51#ibcon#*before return 0, iclass 25, count 0 2006.257.20:46:29.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:29.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:29.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:46:29.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:46:29.51$vck44/va=4,7 2006.257.20:46:29.51#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.20:46:29.51#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.20:46:29.51#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:29.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:29.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:29.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:29.57#ibcon#enter wrdev, iclass 27, count 2 2006.257.20:46:29.57#ibcon#first serial, iclass 27, count 2 2006.257.20:46:29.57#ibcon#enter sib2, iclass 27, count 2 2006.257.20:46:29.57#ibcon#flushed, iclass 27, count 2 2006.257.20:46:29.57#ibcon#about to write, iclass 27, count 2 2006.257.20:46:29.57#ibcon#wrote, iclass 27, count 2 2006.257.20:46:29.57#ibcon#about to read 3, iclass 27, count 2 2006.257.20:46:29.59#ibcon#read 3, iclass 27, count 2 2006.257.20:46:29.59#ibcon#about to read 4, iclass 27, count 2 2006.257.20:46:29.59#ibcon#read 4, iclass 27, count 2 2006.257.20:46:29.59#ibcon#about to read 5, iclass 27, count 2 2006.257.20:46:29.59#ibcon#read 5, iclass 27, count 2 2006.257.20:46:29.59#ibcon#about to read 6, iclass 27, count 2 2006.257.20:46:29.59#ibcon#read 6, iclass 27, count 2 2006.257.20:46:29.59#ibcon#end of sib2, iclass 27, count 2 2006.257.20:46:29.59#ibcon#*mode == 0, iclass 27, count 2 2006.257.20:46:29.59#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.20:46:29.59#ibcon#[25=AT04-07\r\n] 2006.257.20:46:29.59#ibcon#*before write, iclass 27, count 2 2006.257.20:46:29.59#ibcon#enter sib2, iclass 27, count 2 2006.257.20:46:29.59#ibcon#flushed, iclass 27, count 2 2006.257.20:46:29.59#ibcon#about to write, iclass 27, count 2 2006.257.20:46:29.59#ibcon#wrote, iclass 27, count 2 2006.257.20:46:29.59#ibcon#about to read 3, iclass 27, count 2 2006.257.20:46:29.62#ibcon#read 3, iclass 27, count 2 2006.257.20:46:29.62#ibcon#about to read 4, iclass 27, count 2 2006.257.20:46:29.62#ibcon#read 4, iclass 27, count 2 2006.257.20:46:29.62#ibcon#about to read 5, iclass 27, count 2 2006.257.20:46:29.62#ibcon#read 5, iclass 27, count 2 2006.257.20:46:29.62#ibcon#about to read 6, iclass 27, count 2 2006.257.20:46:29.62#ibcon#read 6, iclass 27, count 2 2006.257.20:46:29.62#ibcon#end of sib2, iclass 27, count 2 2006.257.20:46:29.62#ibcon#*after write, iclass 27, count 2 2006.257.20:46:29.62#ibcon#*before return 0, iclass 27, count 2 2006.257.20:46:29.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:29.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:29.62#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.20:46:29.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:29.62#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:29.74#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:29.74#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:29.74#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:46:29.74#ibcon#first serial, iclass 27, count 0 2006.257.20:46:29.74#ibcon#enter sib2, iclass 27, count 0 2006.257.20:46:29.74#ibcon#flushed, iclass 27, count 0 2006.257.20:46:29.74#ibcon#about to write, iclass 27, count 0 2006.257.20:46:29.74#ibcon#wrote, iclass 27, count 0 2006.257.20:46:29.74#ibcon#about to read 3, iclass 27, count 0 2006.257.20:46:29.76#ibcon#read 3, iclass 27, count 0 2006.257.20:46:29.76#ibcon#about to read 4, iclass 27, count 0 2006.257.20:46:29.76#ibcon#read 4, iclass 27, count 0 2006.257.20:46:29.76#ibcon#about to read 5, iclass 27, count 0 2006.257.20:46:29.76#ibcon#read 5, iclass 27, count 0 2006.257.20:46:29.76#ibcon#about to read 6, iclass 27, count 0 2006.257.20:46:29.76#ibcon#read 6, iclass 27, count 0 2006.257.20:46:29.76#ibcon#end of sib2, iclass 27, count 0 2006.257.20:46:29.76#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:46:29.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:46:29.76#ibcon#[25=USB\r\n] 2006.257.20:46:29.76#ibcon#*before write, iclass 27, count 0 2006.257.20:46:29.76#ibcon#enter sib2, iclass 27, count 0 2006.257.20:46:29.76#ibcon#flushed, iclass 27, count 0 2006.257.20:46:29.76#ibcon#about to write, iclass 27, count 0 2006.257.20:46:29.76#ibcon#wrote, iclass 27, count 0 2006.257.20:46:29.76#ibcon#about to read 3, iclass 27, count 0 2006.257.20:46:29.79#ibcon#read 3, iclass 27, count 0 2006.257.20:46:29.79#ibcon#about to read 4, iclass 27, count 0 2006.257.20:46:29.79#ibcon#read 4, iclass 27, count 0 2006.257.20:46:29.79#ibcon#about to read 5, iclass 27, count 0 2006.257.20:46:29.79#ibcon#read 5, iclass 27, count 0 2006.257.20:46:29.79#ibcon#about to read 6, iclass 27, count 0 2006.257.20:46:29.79#ibcon#read 6, iclass 27, count 0 2006.257.20:46:29.79#ibcon#end of sib2, iclass 27, count 0 2006.257.20:46:29.79#ibcon#*after write, iclass 27, count 0 2006.257.20:46:29.79#ibcon#*before return 0, iclass 27, count 0 2006.257.20:46:29.79#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:29.79#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:29.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:46:29.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:46:29.79$vck44/valo=5,734.99 2006.257.20:46:29.79#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.20:46:29.79#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.20:46:29.79#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:29.79#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:29.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:29.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:29.79#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:46:29.79#ibcon#first serial, iclass 29, count 0 2006.257.20:46:29.79#ibcon#enter sib2, iclass 29, count 0 2006.257.20:46:29.79#ibcon#flushed, iclass 29, count 0 2006.257.20:46:29.79#ibcon#about to write, iclass 29, count 0 2006.257.20:46:29.79#ibcon#wrote, iclass 29, count 0 2006.257.20:46:29.79#ibcon#about to read 3, iclass 29, count 0 2006.257.20:46:29.81#ibcon#read 3, iclass 29, count 0 2006.257.20:46:29.81#ibcon#about to read 4, iclass 29, count 0 2006.257.20:46:29.81#ibcon#read 4, iclass 29, count 0 2006.257.20:46:29.81#ibcon#about to read 5, iclass 29, count 0 2006.257.20:46:29.81#ibcon#read 5, iclass 29, count 0 2006.257.20:46:29.81#ibcon#about to read 6, iclass 29, count 0 2006.257.20:46:29.81#ibcon#read 6, iclass 29, count 0 2006.257.20:46:29.81#ibcon#end of sib2, iclass 29, count 0 2006.257.20:46:29.81#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:46:29.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:46:29.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.20:46:29.81#ibcon#*before write, iclass 29, count 0 2006.257.20:46:29.81#ibcon#enter sib2, iclass 29, count 0 2006.257.20:46:29.81#ibcon#flushed, iclass 29, count 0 2006.257.20:46:29.81#ibcon#about to write, iclass 29, count 0 2006.257.20:46:29.81#ibcon#wrote, iclass 29, count 0 2006.257.20:46:29.81#ibcon#about to read 3, iclass 29, count 0 2006.257.20:46:29.85#ibcon#read 3, iclass 29, count 0 2006.257.20:46:29.85#ibcon#about to read 4, iclass 29, count 0 2006.257.20:46:29.85#ibcon#read 4, iclass 29, count 0 2006.257.20:46:29.85#ibcon#about to read 5, iclass 29, count 0 2006.257.20:46:29.85#ibcon#read 5, iclass 29, count 0 2006.257.20:46:29.85#ibcon#about to read 6, iclass 29, count 0 2006.257.20:46:29.85#ibcon#read 6, iclass 29, count 0 2006.257.20:46:29.85#ibcon#end of sib2, iclass 29, count 0 2006.257.20:46:29.85#ibcon#*after write, iclass 29, count 0 2006.257.20:46:29.85#ibcon#*before return 0, iclass 29, count 0 2006.257.20:46:29.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:29.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:29.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:46:29.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:46:29.85$vck44/va=5,4 2006.257.20:46:29.85#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.20:46:29.85#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.20:46:29.85#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:29.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:29.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:29.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:29.91#ibcon#enter wrdev, iclass 31, count 2 2006.257.20:46:29.91#ibcon#first serial, iclass 31, count 2 2006.257.20:46:29.91#ibcon#enter sib2, iclass 31, count 2 2006.257.20:46:29.91#ibcon#flushed, iclass 31, count 2 2006.257.20:46:29.91#ibcon#about to write, iclass 31, count 2 2006.257.20:46:29.91#ibcon#wrote, iclass 31, count 2 2006.257.20:46:29.91#ibcon#about to read 3, iclass 31, count 2 2006.257.20:46:29.93#ibcon#read 3, iclass 31, count 2 2006.257.20:46:29.93#ibcon#about to read 4, iclass 31, count 2 2006.257.20:46:29.93#ibcon#read 4, iclass 31, count 2 2006.257.20:46:29.93#ibcon#about to read 5, iclass 31, count 2 2006.257.20:46:29.93#ibcon#read 5, iclass 31, count 2 2006.257.20:46:29.93#ibcon#about to read 6, iclass 31, count 2 2006.257.20:46:29.93#ibcon#read 6, iclass 31, count 2 2006.257.20:46:29.93#ibcon#end of sib2, iclass 31, count 2 2006.257.20:46:29.93#ibcon#*mode == 0, iclass 31, count 2 2006.257.20:46:29.93#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.20:46:29.93#ibcon#[25=AT05-04\r\n] 2006.257.20:46:29.93#ibcon#*before write, iclass 31, count 2 2006.257.20:46:29.93#ibcon#enter sib2, iclass 31, count 2 2006.257.20:46:29.93#ibcon#flushed, iclass 31, count 2 2006.257.20:46:29.93#ibcon#about to write, iclass 31, count 2 2006.257.20:46:29.93#ibcon#wrote, iclass 31, count 2 2006.257.20:46:29.93#ibcon#about to read 3, iclass 31, count 2 2006.257.20:46:29.96#ibcon#read 3, iclass 31, count 2 2006.257.20:46:29.96#ibcon#about to read 4, iclass 31, count 2 2006.257.20:46:29.96#ibcon#read 4, iclass 31, count 2 2006.257.20:46:29.96#ibcon#about to read 5, iclass 31, count 2 2006.257.20:46:29.96#ibcon#read 5, iclass 31, count 2 2006.257.20:46:29.96#ibcon#about to read 6, iclass 31, count 2 2006.257.20:46:29.96#ibcon#read 6, iclass 31, count 2 2006.257.20:46:29.96#ibcon#end of sib2, iclass 31, count 2 2006.257.20:46:29.96#ibcon#*after write, iclass 31, count 2 2006.257.20:46:29.96#ibcon#*before return 0, iclass 31, count 2 2006.257.20:46:29.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:29.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:29.96#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.20:46:29.96#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:29.96#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:30.08#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:30.08#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:30.08#ibcon#enter wrdev, iclass 31, count 0 2006.257.20:46:30.08#ibcon#first serial, iclass 31, count 0 2006.257.20:46:30.08#ibcon#enter sib2, iclass 31, count 0 2006.257.20:46:30.08#ibcon#flushed, iclass 31, count 0 2006.257.20:46:30.08#ibcon#about to write, iclass 31, count 0 2006.257.20:46:30.08#ibcon#wrote, iclass 31, count 0 2006.257.20:46:30.08#ibcon#about to read 3, iclass 31, count 0 2006.257.20:46:30.10#ibcon#read 3, iclass 31, count 0 2006.257.20:46:30.10#ibcon#about to read 4, iclass 31, count 0 2006.257.20:46:30.10#ibcon#read 4, iclass 31, count 0 2006.257.20:46:30.10#ibcon#about to read 5, iclass 31, count 0 2006.257.20:46:30.10#ibcon#read 5, iclass 31, count 0 2006.257.20:46:30.10#ibcon#about to read 6, iclass 31, count 0 2006.257.20:46:30.10#ibcon#read 6, iclass 31, count 0 2006.257.20:46:30.10#ibcon#end of sib2, iclass 31, count 0 2006.257.20:46:30.10#ibcon#*mode == 0, iclass 31, count 0 2006.257.20:46:30.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.20:46:30.10#ibcon#[25=USB\r\n] 2006.257.20:46:30.10#ibcon#*before write, iclass 31, count 0 2006.257.20:46:30.10#ibcon#enter sib2, iclass 31, count 0 2006.257.20:46:30.10#ibcon#flushed, iclass 31, count 0 2006.257.20:46:30.10#ibcon#about to write, iclass 31, count 0 2006.257.20:46:30.10#ibcon#wrote, iclass 31, count 0 2006.257.20:46:30.10#ibcon#about to read 3, iclass 31, count 0 2006.257.20:46:30.13#ibcon#read 3, iclass 31, count 0 2006.257.20:46:30.13#ibcon#about to read 4, iclass 31, count 0 2006.257.20:46:30.13#ibcon#read 4, iclass 31, count 0 2006.257.20:46:30.13#ibcon#about to read 5, iclass 31, count 0 2006.257.20:46:30.13#ibcon#read 5, iclass 31, count 0 2006.257.20:46:30.13#ibcon#about to read 6, iclass 31, count 0 2006.257.20:46:30.13#ibcon#read 6, iclass 31, count 0 2006.257.20:46:30.13#ibcon#end of sib2, iclass 31, count 0 2006.257.20:46:30.13#ibcon#*after write, iclass 31, count 0 2006.257.20:46:30.13#ibcon#*before return 0, iclass 31, count 0 2006.257.20:46:30.13#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:30.13#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:30.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.20:46:30.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.20:46:30.13$vck44/valo=6,814.99 2006.257.20:46:30.13#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.20:46:30.13#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.20:46:30.13#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:30.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:46:30.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:46:30.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:46:30.13#ibcon#enter wrdev, iclass 33, count 0 2006.257.20:46:30.13#ibcon#first serial, iclass 33, count 0 2006.257.20:46:30.13#ibcon#enter sib2, iclass 33, count 0 2006.257.20:46:30.13#ibcon#flushed, iclass 33, count 0 2006.257.20:46:30.13#ibcon#about to write, iclass 33, count 0 2006.257.20:46:30.13#ibcon#wrote, iclass 33, count 0 2006.257.20:46:30.13#ibcon#about to read 3, iclass 33, count 0 2006.257.20:46:30.15#ibcon#read 3, iclass 33, count 0 2006.257.20:46:30.15#ibcon#about to read 4, iclass 33, count 0 2006.257.20:46:30.15#ibcon#read 4, iclass 33, count 0 2006.257.20:46:30.15#ibcon#about to read 5, iclass 33, count 0 2006.257.20:46:30.15#ibcon#read 5, iclass 33, count 0 2006.257.20:46:30.15#ibcon#about to read 6, iclass 33, count 0 2006.257.20:46:30.15#ibcon#read 6, iclass 33, count 0 2006.257.20:46:30.15#ibcon#end of sib2, iclass 33, count 0 2006.257.20:46:30.15#ibcon#*mode == 0, iclass 33, count 0 2006.257.20:46:30.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.20:46:30.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.20:46:30.15#ibcon#*before write, iclass 33, count 0 2006.257.20:46:30.15#ibcon#enter sib2, iclass 33, count 0 2006.257.20:46:30.15#ibcon#flushed, iclass 33, count 0 2006.257.20:46:30.15#ibcon#about to write, iclass 33, count 0 2006.257.20:46:30.15#ibcon#wrote, iclass 33, count 0 2006.257.20:46:30.15#ibcon#about to read 3, iclass 33, count 0 2006.257.20:46:30.19#ibcon#read 3, iclass 33, count 0 2006.257.20:46:30.19#ibcon#about to read 4, iclass 33, count 0 2006.257.20:46:30.19#ibcon#read 4, iclass 33, count 0 2006.257.20:46:30.19#ibcon#about to read 5, iclass 33, count 0 2006.257.20:46:30.19#ibcon#read 5, iclass 33, count 0 2006.257.20:46:30.19#ibcon#about to read 6, iclass 33, count 0 2006.257.20:46:30.19#ibcon#read 6, iclass 33, count 0 2006.257.20:46:30.19#ibcon#end of sib2, iclass 33, count 0 2006.257.20:46:30.19#ibcon#*after write, iclass 33, count 0 2006.257.20:46:30.19#ibcon#*before return 0, iclass 33, count 0 2006.257.20:46:30.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:46:30.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.20:46:30.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.20:46:30.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.20:46:30.19$vck44/va=6,4 2006.257.20:46:30.19#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.20:46:30.19#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.20:46:30.19#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:30.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:46:30.25#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:46:30.25#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:46:30.25#ibcon#enter wrdev, iclass 35, count 2 2006.257.20:46:30.25#ibcon#first serial, iclass 35, count 2 2006.257.20:46:30.25#ibcon#enter sib2, iclass 35, count 2 2006.257.20:46:30.25#ibcon#flushed, iclass 35, count 2 2006.257.20:46:30.25#ibcon#about to write, iclass 35, count 2 2006.257.20:46:30.25#ibcon#wrote, iclass 35, count 2 2006.257.20:46:30.25#ibcon#about to read 3, iclass 35, count 2 2006.257.20:46:30.27#ibcon#read 3, iclass 35, count 2 2006.257.20:46:30.27#ibcon#about to read 4, iclass 35, count 2 2006.257.20:46:30.27#ibcon#read 4, iclass 35, count 2 2006.257.20:46:30.27#ibcon#about to read 5, iclass 35, count 2 2006.257.20:46:30.27#ibcon#read 5, iclass 35, count 2 2006.257.20:46:30.27#ibcon#about to read 6, iclass 35, count 2 2006.257.20:46:30.27#ibcon#read 6, iclass 35, count 2 2006.257.20:46:30.27#ibcon#end of sib2, iclass 35, count 2 2006.257.20:46:30.27#ibcon#*mode == 0, iclass 35, count 2 2006.257.20:46:30.27#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.20:46:30.27#ibcon#[25=AT06-04\r\n] 2006.257.20:46:30.27#ibcon#*before write, iclass 35, count 2 2006.257.20:46:30.27#ibcon#enter sib2, iclass 35, count 2 2006.257.20:46:30.27#ibcon#flushed, iclass 35, count 2 2006.257.20:46:30.27#ibcon#about to write, iclass 35, count 2 2006.257.20:46:30.27#ibcon#wrote, iclass 35, count 2 2006.257.20:46:30.27#ibcon#about to read 3, iclass 35, count 2 2006.257.20:46:30.30#ibcon#read 3, iclass 35, count 2 2006.257.20:46:30.30#ibcon#about to read 4, iclass 35, count 2 2006.257.20:46:30.30#ibcon#read 4, iclass 35, count 2 2006.257.20:46:30.30#ibcon#about to read 5, iclass 35, count 2 2006.257.20:46:30.30#ibcon#read 5, iclass 35, count 2 2006.257.20:46:30.30#ibcon#about to read 6, iclass 35, count 2 2006.257.20:46:30.30#ibcon#read 6, iclass 35, count 2 2006.257.20:46:30.30#ibcon#end of sib2, iclass 35, count 2 2006.257.20:46:30.30#ibcon#*after write, iclass 35, count 2 2006.257.20:46:30.30#ibcon#*before return 0, iclass 35, count 2 2006.257.20:46:30.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:46:30.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.20:46:30.30#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.20:46:30.30#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:30.30#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:46:30.42#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:46:30.42#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:46:30.42#ibcon#enter wrdev, iclass 35, count 0 2006.257.20:46:30.42#ibcon#first serial, iclass 35, count 0 2006.257.20:46:30.42#ibcon#enter sib2, iclass 35, count 0 2006.257.20:46:30.42#ibcon#flushed, iclass 35, count 0 2006.257.20:46:30.42#ibcon#about to write, iclass 35, count 0 2006.257.20:46:30.42#ibcon#wrote, iclass 35, count 0 2006.257.20:46:30.42#ibcon#about to read 3, iclass 35, count 0 2006.257.20:46:30.44#ibcon#read 3, iclass 35, count 0 2006.257.20:46:30.44#ibcon#about to read 4, iclass 35, count 0 2006.257.20:46:30.44#ibcon#read 4, iclass 35, count 0 2006.257.20:46:30.44#ibcon#about to read 5, iclass 35, count 0 2006.257.20:46:30.44#ibcon#read 5, iclass 35, count 0 2006.257.20:46:30.44#ibcon#about to read 6, iclass 35, count 0 2006.257.20:46:30.44#ibcon#read 6, iclass 35, count 0 2006.257.20:46:30.44#ibcon#end of sib2, iclass 35, count 0 2006.257.20:46:30.44#ibcon#*mode == 0, iclass 35, count 0 2006.257.20:46:30.44#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.20:46:30.44#ibcon#[25=USB\r\n] 2006.257.20:46:30.44#ibcon#*before write, iclass 35, count 0 2006.257.20:46:30.44#ibcon#enter sib2, iclass 35, count 0 2006.257.20:46:30.44#ibcon#flushed, iclass 35, count 0 2006.257.20:46:30.44#ibcon#about to write, iclass 35, count 0 2006.257.20:46:30.44#ibcon#wrote, iclass 35, count 0 2006.257.20:46:30.44#ibcon#about to read 3, iclass 35, count 0 2006.257.20:46:30.47#ibcon#read 3, iclass 35, count 0 2006.257.20:46:30.47#ibcon#about to read 4, iclass 35, count 0 2006.257.20:46:30.47#ibcon#read 4, iclass 35, count 0 2006.257.20:46:30.47#ibcon#about to read 5, iclass 35, count 0 2006.257.20:46:30.47#ibcon#read 5, iclass 35, count 0 2006.257.20:46:30.47#ibcon#about to read 6, iclass 35, count 0 2006.257.20:46:30.47#ibcon#read 6, iclass 35, count 0 2006.257.20:46:30.47#ibcon#end of sib2, iclass 35, count 0 2006.257.20:46:30.47#ibcon#*after write, iclass 35, count 0 2006.257.20:46:30.47#ibcon#*before return 0, iclass 35, count 0 2006.257.20:46:30.47#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:46:30.47#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.20:46:30.47#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.20:46:30.47#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.20:46:30.47$vck44/valo=7,864.99 2006.257.20:46:30.47#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.20:46:30.47#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.20:46:30.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:30.47#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:30.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:30.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:30.47#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:46:30.47#ibcon#first serial, iclass 37, count 0 2006.257.20:46:30.47#ibcon#enter sib2, iclass 37, count 0 2006.257.20:46:30.47#ibcon#flushed, iclass 37, count 0 2006.257.20:46:30.47#ibcon#about to write, iclass 37, count 0 2006.257.20:46:30.47#ibcon#wrote, iclass 37, count 0 2006.257.20:46:30.47#ibcon#about to read 3, iclass 37, count 0 2006.257.20:46:30.49#ibcon#read 3, iclass 37, count 0 2006.257.20:46:30.49#ibcon#about to read 4, iclass 37, count 0 2006.257.20:46:30.49#ibcon#read 4, iclass 37, count 0 2006.257.20:46:30.49#ibcon#about to read 5, iclass 37, count 0 2006.257.20:46:30.49#ibcon#read 5, iclass 37, count 0 2006.257.20:46:30.49#ibcon#about to read 6, iclass 37, count 0 2006.257.20:46:30.49#ibcon#read 6, iclass 37, count 0 2006.257.20:46:30.49#ibcon#end of sib2, iclass 37, count 0 2006.257.20:46:30.49#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:46:30.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:46:30.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.20:46:30.49#ibcon#*before write, iclass 37, count 0 2006.257.20:46:30.49#ibcon#enter sib2, iclass 37, count 0 2006.257.20:46:30.49#ibcon#flushed, iclass 37, count 0 2006.257.20:46:30.49#ibcon#about to write, iclass 37, count 0 2006.257.20:46:30.49#ibcon#wrote, iclass 37, count 0 2006.257.20:46:30.49#ibcon#about to read 3, iclass 37, count 0 2006.257.20:46:30.53#ibcon#read 3, iclass 37, count 0 2006.257.20:46:30.53#ibcon#about to read 4, iclass 37, count 0 2006.257.20:46:30.53#ibcon#read 4, iclass 37, count 0 2006.257.20:46:30.53#ibcon#about to read 5, iclass 37, count 0 2006.257.20:46:30.53#ibcon#read 5, iclass 37, count 0 2006.257.20:46:30.53#ibcon#about to read 6, iclass 37, count 0 2006.257.20:46:30.53#ibcon#read 6, iclass 37, count 0 2006.257.20:46:30.53#ibcon#end of sib2, iclass 37, count 0 2006.257.20:46:30.53#ibcon#*after write, iclass 37, count 0 2006.257.20:46:30.53#ibcon#*before return 0, iclass 37, count 0 2006.257.20:46:30.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:30.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:30.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:46:30.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:46:30.53$vck44/va=7,4 2006.257.20:46:30.53#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.20:46:30.53#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.20:46:30.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:30.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:30.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:30.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:30.59#ibcon#enter wrdev, iclass 39, count 2 2006.257.20:46:30.59#ibcon#first serial, iclass 39, count 2 2006.257.20:46:30.59#ibcon#enter sib2, iclass 39, count 2 2006.257.20:46:30.59#ibcon#flushed, iclass 39, count 2 2006.257.20:46:30.59#ibcon#about to write, iclass 39, count 2 2006.257.20:46:30.59#ibcon#wrote, iclass 39, count 2 2006.257.20:46:30.59#ibcon#about to read 3, iclass 39, count 2 2006.257.20:46:30.61#ibcon#read 3, iclass 39, count 2 2006.257.20:46:30.61#ibcon#about to read 4, iclass 39, count 2 2006.257.20:46:30.61#ibcon#read 4, iclass 39, count 2 2006.257.20:46:30.61#ibcon#about to read 5, iclass 39, count 2 2006.257.20:46:30.61#ibcon#read 5, iclass 39, count 2 2006.257.20:46:30.61#ibcon#about to read 6, iclass 39, count 2 2006.257.20:46:30.61#ibcon#read 6, iclass 39, count 2 2006.257.20:46:30.61#ibcon#end of sib2, iclass 39, count 2 2006.257.20:46:30.61#ibcon#*mode == 0, iclass 39, count 2 2006.257.20:46:30.61#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.20:46:30.61#ibcon#[25=AT07-04\r\n] 2006.257.20:46:30.61#ibcon#*before write, iclass 39, count 2 2006.257.20:46:30.61#ibcon#enter sib2, iclass 39, count 2 2006.257.20:46:30.61#ibcon#flushed, iclass 39, count 2 2006.257.20:46:30.61#ibcon#about to write, iclass 39, count 2 2006.257.20:46:30.61#ibcon#wrote, iclass 39, count 2 2006.257.20:46:30.61#ibcon#about to read 3, iclass 39, count 2 2006.257.20:46:30.64#ibcon#read 3, iclass 39, count 2 2006.257.20:46:30.64#ibcon#about to read 4, iclass 39, count 2 2006.257.20:46:30.64#ibcon#read 4, iclass 39, count 2 2006.257.20:46:30.64#ibcon#about to read 5, iclass 39, count 2 2006.257.20:46:30.64#ibcon#read 5, iclass 39, count 2 2006.257.20:46:30.64#ibcon#about to read 6, iclass 39, count 2 2006.257.20:46:30.64#ibcon#read 6, iclass 39, count 2 2006.257.20:46:30.64#ibcon#end of sib2, iclass 39, count 2 2006.257.20:46:30.64#ibcon#*after write, iclass 39, count 2 2006.257.20:46:30.64#ibcon#*before return 0, iclass 39, count 2 2006.257.20:46:30.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:30.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:30.64#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.20:46:30.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:30.64#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:30.76#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:30.76#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:30.76#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:46:30.76#ibcon#first serial, iclass 39, count 0 2006.257.20:46:30.76#ibcon#enter sib2, iclass 39, count 0 2006.257.20:46:30.76#ibcon#flushed, iclass 39, count 0 2006.257.20:46:30.76#ibcon#about to write, iclass 39, count 0 2006.257.20:46:30.76#ibcon#wrote, iclass 39, count 0 2006.257.20:46:30.76#ibcon#about to read 3, iclass 39, count 0 2006.257.20:46:30.78#ibcon#read 3, iclass 39, count 0 2006.257.20:46:30.78#ibcon#about to read 4, iclass 39, count 0 2006.257.20:46:30.78#ibcon#read 4, iclass 39, count 0 2006.257.20:46:30.78#ibcon#about to read 5, iclass 39, count 0 2006.257.20:46:30.78#ibcon#read 5, iclass 39, count 0 2006.257.20:46:30.78#ibcon#about to read 6, iclass 39, count 0 2006.257.20:46:30.78#ibcon#read 6, iclass 39, count 0 2006.257.20:46:30.78#ibcon#end of sib2, iclass 39, count 0 2006.257.20:46:30.78#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:46:30.78#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:46:30.78#ibcon#[25=USB\r\n] 2006.257.20:46:30.78#ibcon#*before write, iclass 39, count 0 2006.257.20:46:30.78#ibcon#enter sib2, iclass 39, count 0 2006.257.20:46:30.78#ibcon#flushed, iclass 39, count 0 2006.257.20:46:30.78#ibcon#about to write, iclass 39, count 0 2006.257.20:46:30.78#ibcon#wrote, iclass 39, count 0 2006.257.20:46:30.78#ibcon#about to read 3, iclass 39, count 0 2006.257.20:46:30.81#ibcon#read 3, iclass 39, count 0 2006.257.20:46:30.81#ibcon#about to read 4, iclass 39, count 0 2006.257.20:46:30.81#ibcon#read 4, iclass 39, count 0 2006.257.20:46:30.81#ibcon#about to read 5, iclass 39, count 0 2006.257.20:46:30.81#ibcon#read 5, iclass 39, count 0 2006.257.20:46:30.81#ibcon#about to read 6, iclass 39, count 0 2006.257.20:46:30.81#ibcon#read 6, iclass 39, count 0 2006.257.20:46:30.81#ibcon#end of sib2, iclass 39, count 0 2006.257.20:46:30.81#ibcon#*after write, iclass 39, count 0 2006.257.20:46:30.81#ibcon#*before return 0, iclass 39, count 0 2006.257.20:46:30.81#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:30.81#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:30.81#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:46:30.81#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:46:30.81$vck44/valo=8,884.99 2006.257.20:46:30.81#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.20:46:30.81#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.20:46:30.81#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:30.81#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:30.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:30.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:30.81#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:46:30.81#ibcon#first serial, iclass 3, count 0 2006.257.20:46:30.81#ibcon#enter sib2, iclass 3, count 0 2006.257.20:46:30.81#ibcon#flushed, iclass 3, count 0 2006.257.20:46:30.81#ibcon#about to write, iclass 3, count 0 2006.257.20:46:30.81#ibcon#wrote, iclass 3, count 0 2006.257.20:46:30.81#ibcon#about to read 3, iclass 3, count 0 2006.257.20:46:30.83#ibcon#read 3, iclass 3, count 0 2006.257.20:46:30.83#ibcon#about to read 4, iclass 3, count 0 2006.257.20:46:30.83#ibcon#read 4, iclass 3, count 0 2006.257.20:46:30.83#ibcon#about to read 5, iclass 3, count 0 2006.257.20:46:30.83#ibcon#read 5, iclass 3, count 0 2006.257.20:46:30.83#ibcon#about to read 6, iclass 3, count 0 2006.257.20:46:30.83#ibcon#read 6, iclass 3, count 0 2006.257.20:46:30.83#ibcon#end of sib2, iclass 3, count 0 2006.257.20:46:30.83#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:46:30.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:46:30.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.20:46:30.83#ibcon#*before write, iclass 3, count 0 2006.257.20:46:30.83#ibcon#enter sib2, iclass 3, count 0 2006.257.20:46:30.83#ibcon#flushed, iclass 3, count 0 2006.257.20:46:30.83#ibcon#about to write, iclass 3, count 0 2006.257.20:46:30.83#ibcon#wrote, iclass 3, count 0 2006.257.20:46:30.83#ibcon#about to read 3, iclass 3, count 0 2006.257.20:46:30.87#ibcon#read 3, iclass 3, count 0 2006.257.20:46:30.87#ibcon#about to read 4, iclass 3, count 0 2006.257.20:46:30.87#ibcon#read 4, iclass 3, count 0 2006.257.20:46:30.87#ibcon#about to read 5, iclass 3, count 0 2006.257.20:46:30.87#ibcon#read 5, iclass 3, count 0 2006.257.20:46:30.87#ibcon#about to read 6, iclass 3, count 0 2006.257.20:46:30.87#ibcon#read 6, iclass 3, count 0 2006.257.20:46:30.87#ibcon#end of sib2, iclass 3, count 0 2006.257.20:46:30.87#ibcon#*after write, iclass 3, count 0 2006.257.20:46:30.87#ibcon#*before return 0, iclass 3, count 0 2006.257.20:46:30.87#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:30.87#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:30.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:46:30.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:46:30.87$vck44/va=8,4 2006.257.20:46:30.87#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.20:46:30.87#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.20:46:30.87#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:30.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:30.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:30.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:30.93#ibcon#enter wrdev, iclass 5, count 2 2006.257.20:46:30.93#ibcon#first serial, iclass 5, count 2 2006.257.20:46:30.93#ibcon#enter sib2, iclass 5, count 2 2006.257.20:46:30.93#ibcon#flushed, iclass 5, count 2 2006.257.20:46:30.93#ibcon#about to write, iclass 5, count 2 2006.257.20:46:30.93#ibcon#wrote, iclass 5, count 2 2006.257.20:46:30.93#ibcon#about to read 3, iclass 5, count 2 2006.257.20:46:30.95#ibcon#read 3, iclass 5, count 2 2006.257.20:46:30.95#ibcon#about to read 4, iclass 5, count 2 2006.257.20:46:30.95#ibcon#read 4, iclass 5, count 2 2006.257.20:46:30.95#ibcon#about to read 5, iclass 5, count 2 2006.257.20:46:30.95#ibcon#read 5, iclass 5, count 2 2006.257.20:46:30.95#ibcon#about to read 6, iclass 5, count 2 2006.257.20:46:30.95#ibcon#read 6, iclass 5, count 2 2006.257.20:46:30.95#ibcon#end of sib2, iclass 5, count 2 2006.257.20:46:30.95#ibcon#*mode == 0, iclass 5, count 2 2006.257.20:46:30.95#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.20:46:30.95#ibcon#[25=AT08-04\r\n] 2006.257.20:46:30.95#ibcon#*before write, iclass 5, count 2 2006.257.20:46:30.95#ibcon#enter sib2, iclass 5, count 2 2006.257.20:46:30.95#ibcon#flushed, iclass 5, count 2 2006.257.20:46:30.95#ibcon#about to write, iclass 5, count 2 2006.257.20:46:30.95#ibcon#wrote, iclass 5, count 2 2006.257.20:46:30.95#ibcon#about to read 3, iclass 5, count 2 2006.257.20:46:30.98#ibcon#read 3, iclass 5, count 2 2006.257.20:46:30.98#ibcon#about to read 4, iclass 5, count 2 2006.257.20:46:30.98#ibcon#read 4, iclass 5, count 2 2006.257.20:46:30.98#ibcon#about to read 5, iclass 5, count 2 2006.257.20:46:30.98#ibcon#read 5, iclass 5, count 2 2006.257.20:46:30.98#ibcon#about to read 6, iclass 5, count 2 2006.257.20:46:30.98#ibcon#read 6, iclass 5, count 2 2006.257.20:46:30.98#ibcon#end of sib2, iclass 5, count 2 2006.257.20:46:30.98#ibcon#*after write, iclass 5, count 2 2006.257.20:46:30.98#ibcon#*before return 0, iclass 5, count 2 2006.257.20:46:30.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:30.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:30.98#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.20:46:30.98#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:30.98#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:31.10#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:31.10#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:31.10#ibcon#enter wrdev, iclass 5, count 0 2006.257.20:46:31.10#ibcon#first serial, iclass 5, count 0 2006.257.20:46:31.10#ibcon#enter sib2, iclass 5, count 0 2006.257.20:46:31.10#ibcon#flushed, iclass 5, count 0 2006.257.20:46:31.10#ibcon#about to write, iclass 5, count 0 2006.257.20:46:31.10#ibcon#wrote, iclass 5, count 0 2006.257.20:46:31.10#ibcon#about to read 3, iclass 5, count 0 2006.257.20:46:31.12#ibcon#read 3, iclass 5, count 0 2006.257.20:46:31.12#ibcon#about to read 4, iclass 5, count 0 2006.257.20:46:31.12#ibcon#read 4, iclass 5, count 0 2006.257.20:46:31.12#ibcon#about to read 5, iclass 5, count 0 2006.257.20:46:31.12#ibcon#read 5, iclass 5, count 0 2006.257.20:46:31.12#ibcon#about to read 6, iclass 5, count 0 2006.257.20:46:31.12#ibcon#read 6, iclass 5, count 0 2006.257.20:46:31.12#ibcon#end of sib2, iclass 5, count 0 2006.257.20:46:31.12#ibcon#*mode == 0, iclass 5, count 0 2006.257.20:46:31.12#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.20:46:31.12#ibcon#[25=USB\r\n] 2006.257.20:46:31.12#ibcon#*before write, iclass 5, count 0 2006.257.20:46:31.12#ibcon#enter sib2, iclass 5, count 0 2006.257.20:46:31.12#ibcon#flushed, iclass 5, count 0 2006.257.20:46:31.12#ibcon#about to write, iclass 5, count 0 2006.257.20:46:31.12#ibcon#wrote, iclass 5, count 0 2006.257.20:46:31.12#ibcon#about to read 3, iclass 5, count 0 2006.257.20:46:31.15#ibcon#read 3, iclass 5, count 0 2006.257.20:46:31.15#ibcon#about to read 4, iclass 5, count 0 2006.257.20:46:31.15#ibcon#read 4, iclass 5, count 0 2006.257.20:46:31.15#ibcon#about to read 5, iclass 5, count 0 2006.257.20:46:31.15#ibcon#read 5, iclass 5, count 0 2006.257.20:46:31.15#ibcon#about to read 6, iclass 5, count 0 2006.257.20:46:31.15#ibcon#read 6, iclass 5, count 0 2006.257.20:46:31.15#ibcon#end of sib2, iclass 5, count 0 2006.257.20:46:31.15#ibcon#*after write, iclass 5, count 0 2006.257.20:46:31.15#ibcon#*before return 0, iclass 5, count 0 2006.257.20:46:31.15#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:31.15#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:31.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.20:46:31.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.20:46:31.15$vck44/vblo=1,629.99 2006.257.20:46:31.15#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.20:46:31.15#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.20:46:31.15#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:31.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:31.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:31.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:31.15#ibcon#enter wrdev, iclass 7, count 0 2006.257.20:46:31.15#ibcon#first serial, iclass 7, count 0 2006.257.20:46:31.15#ibcon#enter sib2, iclass 7, count 0 2006.257.20:46:31.15#ibcon#flushed, iclass 7, count 0 2006.257.20:46:31.15#ibcon#about to write, iclass 7, count 0 2006.257.20:46:31.15#ibcon#wrote, iclass 7, count 0 2006.257.20:46:31.15#ibcon#about to read 3, iclass 7, count 0 2006.257.20:46:31.17#ibcon#read 3, iclass 7, count 0 2006.257.20:46:31.17#ibcon#about to read 4, iclass 7, count 0 2006.257.20:46:31.17#ibcon#read 4, iclass 7, count 0 2006.257.20:46:31.17#ibcon#about to read 5, iclass 7, count 0 2006.257.20:46:31.17#ibcon#read 5, iclass 7, count 0 2006.257.20:46:31.17#ibcon#about to read 6, iclass 7, count 0 2006.257.20:46:31.17#ibcon#read 6, iclass 7, count 0 2006.257.20:46:31.17#ibcon#end of sib2, iclass 7, count 0 2006.257.20:46:31.17#ibcon#*mode == 0, iclass 7, count 0 2006.257.20:46:31.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.20:46:31.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.20:46:31.17#ibcon#*before write, iclass 7, count 0 2006.257.20:46:31.17#ibcon#enter sib2, iclass 7, count 0 2006.257.20:46:31.17#ibcon#flushed, iclass 7, count 0 2006.257.20:46:31.17#ibcon#about to write, iclass 7, count 0 2006.257.20:46:31.17#ibcon#wrote, iclass 7, count 0 2006.257.20:46:31.17#ibcon#about to read 3, iclass 7, count 0 2006.257.20:46:31.21#ibcon#read 3, iclass 7, count 0 2006.257.20:46:31.21#ibcon#about to read 4, iclass 7, count 0 2006.257.20:46:31.21#ibcon#read 4, iclass 7, count 0 2006.257.20:46:31.21#ibcon#about to read 5, iclass 7, count 0 2006.257.20:46:31.21#ibcon#read 5, iclass 7, count 0 2006.257.20:46:31.21#ibcon#about to read 6, iclass 7, count 0 2006.257.20:46:31.21#ibcon#read 6, iclass 7, count 0 2006.257.20:46:31.21#ibcon#end of sib2, iclass 7, count 0 2006.257.20:46:31.21#ibcon#*after write, iclass 7, count 0 2006.257.20:46:31.21#ibcon#*before return 0, iclass 7, count 0 2006.257.20:46:31.21#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:31.21#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:31.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.20:46:31.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.20:46:31.21$vck44/vb=1,4 2006.257.20:46:31.21#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.20:46:31.21#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.20:46:31.21#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:31.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:46:31.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:46:31.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:46:31.21#ibcon#enter wrdev, iclass 11, count 2 2006.257.20:46:31.21#ibcon#first serial, iclass 11, count 2 2006.257.20:46:31.21#ibcon#enter sib2, iclass 11, count 2 2006.257.20:46:31.21#ibcon#flushed, iclass 11, count 2 2006.257.20:46:31.21#ibcon#about to write, iclass 11, count 2 2006.257.20:46:31.21#ibcon#wrote, iclass 11, count 2 2006.257.20:46:31.21#ibcon#about to read 3, iclass 11, count 2 2006.257.20:46:31.23#ibcon#read 3, iclass 11, count 2 2006.257.20:46:31.23#ibcon#about to read 4, iclass 11, count 2 2006.257.20:46:31.23#ibcon#read 4, iclass 11, count 2 2006.257.20:46:31.23#ibcon#about to read 5, iclass 11, count 2 2006.257.20:46:31.23#ibcon#read 5, iclass 11, count 2 2006.257.20:46:31.23#ibcon#about to read 6, iclass 11, count 2 2006.257.20:46:31.23#ibcon#read 6, iclass 11, count 2 2006.257.20:46:31.23#ibcon#end of sib2, iclass 11, count 2 2006.257.20:46:31.23#ibcon#*mode == 0, iclass 11, count 2 2006.257.20:46:31.23#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.20:46:31.23#ibcon#[27=AT01-04\r\n] 2006.257.20:46:31.23#ibcon#*before write, iclass 11, count 2 2006.257.20:46:31.23#ibcon#enter sib2, iclass 11, count 2 2006.257.20:46:31.23#ibcon#flushed, iclass 11, count 2 2006.257.20:46:31.23#ibcon#about to write, iclass 11, count 2 2006.257.20:46:31.23#ibcon#wrote, iclass 11, count 2 2006.257.20:46:31.23#ibcon#about to read 3, iclass 11, count 2 2006.257.20:46:31.26#ibcon#read 3, iclass 11, count 2 2006.257.20:46:31.26#ibcon#about to read 4, iclass 11, count 2 2006.257.20:46:31.26#ibcon#read 4, iclass 11, count 2 2006.257.20:46:31.26#ibcon#about to read 5, iclass 11, count 2 2006.257.20:46:31.26#ibcon#read 5, iclass 11, count 2 2006.257.20:46:31.26#ibcon#about to read 6, iclass 11, count 2 2006.257.20:46:31.26#ibcon#read 6, iclass 11, count 2 2006.257.20:46:31.26#ibcon#end of sib2, iclass 11, count 2 2006.257.20:46:31.26#ibcon#*after write, iclass 11, count 2 2006.257.20:46:31.26#ibcon#*before return 0, iclass 11, count 2 2006.257.20:46:31.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:46:31.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.20:46:31.26#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.20:46:31.26#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:31.26#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:46:31.38#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:46:31.38#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:46:31.38#ibcon#enter wrdev, iclass 11, count 0 2006.257.20:46:31.38#ibcon#first serial, iclass 11, count 0 2006.257.20:46:31.38#ibcon#enter sib2, iclass 11, count 0 2006.257.20:46:31.38#ibcon#flushed, iclass 11, count 0 2006.257.20:46:31.38#ibcon#about to write, iclass 11, count 0 2006.257.20:46:31.38#ibcon#wrote, iclass 11, count 0 2006.257.20:46:31.38#ibcon#about to read 3, iclass 11, count 0 2006.257.20:46:31.40#ibcon#read 3, iclass 11, count 0 2006.257.20:46:31.40#ibcon#about to read 4, iclass 11, count 0 2006.257.20:46:31.40#ibcon#read 4, iclass 11, count 0 2006.257.20:46:31.40#ibcon#about to read 5, iclass 11, count 0 2006.257.20:46:31.40#ibcon#read 5, iclass 11, count 0 2006.257.20:46:31.40#ibcon#about to read 6, iclass 11, count 0 2006.257.20:46:31.40#ibcon#read 6, iclass 11, count 0 2006.257.20:46:31.40#ibcon#end of sib2, iclass 11, count 0 2006.257.20:46:31.40#ibcon#*mode == 0, iclass 11, count 0 2006.257.20:46:31.40#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.20:46:31.40#ibcon#[27=USB\r\n] 2006.257.20:46:31.40#ibcon#*before write, iclass 11, count 0 2006.257.20:46:31.40#ibcon#enter sib2, iclass 11, count 0 2006.257.20:46:31.40#ibcon#flushed, iclass 11, count 0 2006.257.20:46:31.40#ibcon#about to write, iclass 11, count 0 2006.257.20:46:31.40#ibcon#wrote, iclass 11, count 0 2006.257.20:46:31.40#ibcon#about to read 3, iclass 11, count 0 2006.257.20:46:31.43#ibcon#read 3, iclass 11, count 0 2006.257.20:46:31.43#ibcon#about to read 4, iclass 11, count 0 2006.257.20:46:31.43#ibcon#read 4, iclass 11, count 0 2006.257.20:46:31.43#ibcon#about to read 5, iclass 11, count 0 2006.257.20:46:31.43#ibcon#read 5, iclass 11, count 0 2006.257.20:46:31.43#ibcon#about to read 6, iclass 11, count 0 2006.257.20:46:31.43#ibcon#read 6, iclass 11, count 0 2006.257.20:46:31.43#ibcon#end of sib2, iclass 11, count 0 2006.257.20:46:31.43#ibcon#*after write, iclass 11, count 0 2006.257.20:46:31.43#ibcon#*before return 0, iclass 11, count 0 2006.257.20:46:31.43#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:46:31.43#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.20:46:31.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.20:46:31.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.20:46:31.43$vck44/vblo=2,634.99 2006.257.20:46:31.43#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.20:46:31.43#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.20:46:31.43#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:31.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:31.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:31.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:31.43#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:46:31.43#ibcon#first serial, iclass 13, count 0 2006.257.20:46:31.43#ibcon#enter sib2, iclass 13, count 0 2006.257.20:46:31.43#ibcon#flushed, iclass 13, count 0 2006.257.20:46:31.43#ibcon#about to write, iclass 13, count 0 2006.257.20:46:31.43#ibcon#wrote, iclass 13, count 0 2006.257.20:46:31.43#ibcon#about to read 3, iclass 13, count 0 2006.257.20:46:31.45#ibcon#read 3, iclass 13, count 0 2006.257.20:46:31.45#ibcon#about to read 4, iclass 13, count 0 2006.257.20:46:31.45#ibcon#read 4, iclass 13, count 0 2006.257.20:46:31.45#ibcon#about to read 5, iclass 13, count 0 2006.257.20:46:31.45#ibcon#read 5, iclass 13, count 0 2006.257.20:46:31.45#ibcon#about to read 6, iclass 13, count 0 2006.257.20:46:31.45#ibcon#read 6, iclass 13, count 0 2006.257.20:46:31.45#ibcon#end of sib2, iclass 13, count 0 2006.257.20:46:31.45#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:46:31.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:46:31.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.20:46:31.45#ibcon#*before write, iclass 13, count 0 2006.257.20:46:31.45#ibcon#enter sib2, iclass 13, count 0 2006.257.20:46:31.45#ibcon#flushed, iclass 13, count 0 2006.257.20:46:31.45#ibcon#about to write, iclass 13, count 0 2006.257.20:46:31.45#ibcon#wrote, iclass 13, count 0 2006.257.20:46:31.45#ibcon#about to read 3, iclass 13, count 0 2006.257.20:46:31.49#ibcon#read 3, iclass 13, count 0 2006.257.20:46:31.49#ibcon#about to read 4, iclass 13, count 0 2006.257.20:46:31.49#ibcon#read 4, iclass 13, count 0 2006.257.20:46:31.49#ibcon#about to read 5, iclass 13, count 0 2006.257.20:46:31.49#ibcon#read 5, iclass 13, count 0 2006.257.20:46:31.49#ibcon#about to read 6, iclass 13, count 0 2006.257.20:46:31.49#ibcon#read 6, iclass 13, count 0 2006.257.20:46:31.49#ibcon#end of sib2, iclass 13, count 0 2006.257.20:46:31.49#ibcon#*after write, iclass 13, count 0 2006.257.20:46:31.49#ibcon#*before return 0, iclass 13, count 0 2006.257.20:46:31.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:31.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.20:46:31.49#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:46:31.49#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:46:31.49$vck44/vb=2,5 2006.257.20:46:31.49#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.20:46:31.49#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.20:46:31.49#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:31.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:31.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:31.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:31.55#ibcon#enter wrdev, iclass 15, count 2 2006.257.20:46:31.55#ibcon#first serial, iclass 15, count 2 2006.257.20:46:31.55#ibcon#enter sib2, iclass 15, count 2 2006.257.20:46:31.55#ibcon#flushed, iclass 15, count 2 2006.257.20:46:31.55#ibcon#about to write, iclass 15, count 2 2006.257.20:46:31.55#ibcon#wrote, iclass 15, count 2 2006.257.20:46:31.55#ibcon#about to read 3, iclass 15, count 2 2006.257.20:46:31.57#ibcon#read 3, iclass 15, count 2 2006.257.20:46:31.57#ibcon#about to read 4, iclass 15, count 2 2006.257.20:46:31.57#ibcon#read 4, iclass 15, count 2 2006.257.20:46:31.57#ibcon#about to read 5, iclass 15, count 2 2006.257.20:46:31.57#ibcon#read 5, iclass 15, count 2 2006.257.20:46:31.57#ibcon#about to read 6, iclass 15, count 2 2006.257.20:46:31.57#ibcon#read 6, iclass 15, count 2 2006.257.20:46:31.57#ibcon#end of sib2, iclass 15, count 2 2006.257.20:46:31.57#ibcon#*mode == 0, iclass 15, count 2 2006.257.20:46:31.57#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.20:46:31.57#ibcon#[27=AT02-05\r\n] 2006.257.20:46:31.57#ibcon#*before write, iclass 15, count 2 2006.257.20:46:31.57#ibcon#enter sib2, iclass 15, count 2 2006.257.20:46:31.57#ibcon#flushed, iclass 15, count 2 2006.257.20:46:31.57#ibcon#about to write, iclass 15, count 2 2006.257.20:46:31.57#ibcon#wrote, iclass 15, count 2 2006.257.20:46:31.57#ibcon#about to read 3, iclass 15, count 2 2006.257.20:46:31.60#ibcon#read 3, iclass 15, count 2 2006.257.20:46:31.60#ibcon#about to read 4, iclass 15, count 2 2006.257.20:46:31.60#ibcon#read 4, iclass 15, count 2 2006.257.20:46:31.60#ibcon#about to read 5, iclass 15, count 2 2006.257.20:46:31.60#ibcon#read 5, iclass 15, count 2 2006.257.20:46:31.60#ibcon#about to read 6, iclass 15, count 2 2006.257.20:46:31.60#ibcon#read 6, iclass 15, count 2 2006.257.20:46:31.60#ibcon#end of sib2, iclass 15, count 2 2006.257.20:46:31.60#ibcon#*after write, iclass 15, count 2 2006.257.20:46:31.60#ibcon#*before return 0, iclass 15, count 2 2006.257.20:46:31.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:31.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.20:46:31.60#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.20:46:31.60#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:31.60#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:31.72#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:31.72#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:31.72#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:46:31.72#ibcon#first serial, iclass 15, count 0 2006.257.20:46:31.72#ibcon#enter sib2, iclass 15, count 0 2006.257.20:46:31.72#ibcon#flushed, iclass 15, count 0 2006.257.20:46:31.72#ibcon#about to write, iclass 15, count 0 2006.257.20:46:31.72#ibcon#wrote, iclass 15, count 0 2006.257.20:46:31.72#ibcon#about to read 3, iclass 15, count 0 2006.257.20:46:31.74#ibcon#read 3, iclass 15, count 0 2006.257.20:46:31.74#ibcon#about to read 4, iclass 15, count 0 2006.257.20:46:31.74#ibcon#read 4, iclass 15, count 0 2006.257.20:46:31.74#ibcon#about to read 5, iclass 15, count 0 2006.257.20:46:31.74#ibcon#read 5, iclass 15, count 0 2006.257.20:46:31.74#ibcon#about to read 6, iclass 15, count 0 2006.257.20:46:31.74#ibcon#read 6, iclass 15, count 0 2006.257.20:46:31.74#ibcon#end of sib2, iclass 15, count 0 2006.257.20:46:31.74#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:46:31.74#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:46:31.74#ibcon#[27=USB\r\n] 2006.257.20:46:31.74#ibcon#*before write, iclass 15, count 0 2006.257.20:46:31.74#ibcon#enter sib2, iclass 15, count 0 2006.257.20:46:31.74#ibcon#flushed, iclass 15, count 0 2006.257.20:46:31.74#ibcon#about to write, iclass 15, count 0 2006.257.20:46:31.74#ibcon#wrote, iclass 15, count 0 2006.257.20:46:31.74#ibcon#about to read 3, iclass 15, count 0 2006.257.20:46:31.77#ibcon#read 3, iclass 15, count 0 2006.257.20:46:31.77#ibcon#about to read 4, iclass 15, count 0 2006.257.20:46:31.77#ibcon#read 4, iclass 15, count 0 2006.257.20:46:31.77#ibcon#about to read 5, iclass 15, count 0 2006.257.20:46:31.77#ibcon#read 5, iclass 15, count 0 2006.257.20:46:31.77#ibcon#about to read 6, iclass 15, count 0 2006.257.20:46:31.77#ibcon#read 6, iclass 15, count 0 2006.257.20:46:31.77#ibcon#end of sib2, iclass 15, count 0 2006.257.20:46:31.77#ibcon#*after write, iclass 15, count 0 2006.257.20:46:31.77#ibcon#*before return 0, iclass 15, count 0 2006.257.20:46:31.77#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:31.77#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.20:46:31.77#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:46:31.77#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:46:31.77$vck44/vblo=3,649.99 2006.257.20:46:31.77#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.20:46:31.77#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.20:46:31.77#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:31.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:31.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:31.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:31.77#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:46:31.77#ibcon#first serial, iclass 17, count 0 2006.257.20:46:31.77#ibcon#enter sib2, iclass 17, count 0 2006.257.20:46:31.77#ibcon#flushed, iclass 17, count 0 2006.257.20:46:31.77#ibcon#about to write, iclass 17, count 0 2006.257.20:46:31.77#ibcon#wrote, iclass 17, count 0 2006.257.20:46:31.77#ibcon#about to read 3, iclass 17, count 0 2006.257.20:46:31.79#ibcon#read 3, iclass 17, count 0 2006.257.20:46:31.79#ibcon#about to read 4, iclass 17, count 0 2006.257.20:46:31.79#ibcon#read 4, iclass 17, count 0 2006.257.20:46:31.79#ibcon#about to read 5, iclass 17, count 0 2006.257.20:46:31.79#ibcon#read 5, iclass 17, count 0 2006.257.20:46:31.79#ibcon#about to read 6, iclass 17, count 0 2006.257.20:46:31.79#ibcon#read 6, iclass 17, count 0 2006.257.20:46:31.79#ibcon#end of sib2, iclass 17, count 0 2006.257.20:46:31.79#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:46:31.79#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:46:31.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.20:46:31.79#ibcon#*before write, iclass 17, count 0 2006.257.20:46:31.79#ibcon#enter sib2, iclass 17, count 0 2006.257.20:46:31.79#ibcon#flushed, iclass 17, count 0 2006.257.20:46:31.79#ibcon#about to write, iclass 17, count 0 2006.257.20:46:31.79#ibcon#wrote, iclass 17, count 0 2006.257.20:46:31.79#ibcon#about to read 3, iclass 17, count 0 2006.257.20:46:31.83#ibcon#read 3, iclass 17, count 0 2006.257.20:46:31.83#ibcon#about to read 4, iclass 17, count 0 2006.257.20:46:31.83#ibcon#read 4, iclass 17, count 0 2006.257.20:46:31.83#ibcon#about to read 5, iclass 17, count 0 2006.257.20:46:31.83#ibcon#read 5, iclass 17, count 0 2006.257.20:46:31.83#ibcon#about to read 6, iclass 17, count 0 2006.257.20:46:31.83#ibcon#read 6, iclass 17, count 0 2006.257.20:46:31.83#ibcon#end of sib2, iclass 17, count 0 2006.257.20:46:31.83#ibcon#*after write, iclass 17, count 0 2006.257.20:46:31.83#ibcon#*before return 0, iclass 17, count 0 2006.257.20:46:31.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:31.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.20:46:31.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:46:31.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:46:31.83$vck44/vb=3,4 2006.257.20:46:31.83#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.20:46:31.83#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.20:46:31.83#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:31.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:31.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:31.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:31.89#ibcon#enter wrdev, iclass 19, count 2 2006.257.20:46:31.89#ibcon#first serial, iclass 19, count 2 2006.257.20:46:31.89#ibcon#enter sib2, iclass 19, count 2 2006.257.20:46:31.89#ibcon#flushed, iclass 19, count 2 2006.257.20:46:31.89#ibcon#about to write, iclass 19, count 2 2006.257.20:46:31.89#ibcon#wrote, iclass 19, count 2 2006.257.20:46:31.89#ibcon#about to read 3, iclass 19, count 2 2006.257.20:46:31.91#ibcon#read 3, iclass 19, count 2 2006.257.20:46:31.91#ibcon#about to read 4, iclass 19, count 2 2006.257.20:46:31.91#ibcon#read 4, iclass 19, count 2 2006.257.20:46:31.91#ibcon#about to read 5, iclass 19, count 2 2006.257.20:46:31.91#ibcon#read 5, iclass 19, count 2 2006.257.20:46:31.91#ibcon#about to read 6, iclass 19, count 2 2006.257.20:46:31.91#ibcon#read 6, iclass 19, count 2 2006.257.20:46:31.91#ibcon#end of sib2, iclass 19, count 2 2006.257.20:46:31.91#ibcon#*mode == 0, iclass 19, count 2 2006.257.20:46:31.91#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.20:46:31.91#ibcon#[27=AT03-04\r\n] 2006.257.20:46:31.91#ibcon#*before write, iclass 19, count 2 2006.257.20:46:31.91#ibcon#enter sib2, iclass 19, count 2 2006.257.20:46:31.91#ibcon#flushed, iclass 19, count 2 2006.257.20:46:31.91#ibcon#about to write, iclass 19, count 2 2006.257.20:46:31.91#ibcon#wrote, iclass 19, count 2 2006.257.20:46:31.91#ibcon#about to read 3, iclass 19, count 2 2006.257.20:46:31.94#ibcon#read 3, iclass 19, count 2 2006.257.20:46:31.94#ibcon#about to read 4, iclass 19, count 2 2006.257.20:46:31.94#ibcon#read 4, iclass 19, count 2 2006.257.20:46:31.94#ibcon#about to read 5, iclass 19, count 2 2006.257.20:46:31.94#ibcon#read 5, iclass 19, count 2 2006.257.20:46:31.94#ibcon#about to read 6, iclass 19, count 2 2006.257.20:46:31.94#ibcon#read 6, iclass 19, count 2 2006.257.20:46:31.94#ibcon#end of sib2, iclass 19, count 2 2006.257.20:46:31.94#ibcon#*after write, iclass 19, count 2 2006.257.20:46:31.94#ibcon#*before return 0, iclass 19, count 2 2006.257.20:46:31.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:31.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.20:46:31.94#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.20:46:31.94#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:31.94#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:32.06#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:32.06#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:32.06#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:46:32.06#ibcon#first serial, iclass 19, count 0 2006.257.20:46:32.06#ibcon#enter sib2, iclass 19, count 0 2006.257.20:46:32.06#ibcon#flushed, iclass 19, count 0 2006.257.20:46:32.06#ibcon#about to write, iclass 19, count 0 2006.257.20:46:32.06#ibcon#wrote, iclass 19, count 0 2006.257.20:46:32.06#ibcon#about to read 3, iclass 19, count 0 2006.257.20:46:32.08#ibcon#read 3, iclass 19, count 0 2006.257.20:46:32.08#ibcon#about to read 4, iclass 19, count 0 2006.257.20:46:32.08#ibcon#read 4, iclass 19, count 0 2006.257.20:46:32.08#ibcon#about to read 5, iclass 19, count 0 2006.257.20:46:32.08#ibcon#read 5, iclass 19, count 0 2006.257.20:46:32.08#ibcon#about to read 6, iclass 19, count 0 2006.257.20:46:32.08#ibcon#read 6, iclass 19, count 0 2006.257.20:46:32.08#ibcon#end of sib2, iclass 19, count 0 2006.257.20:46:32.08#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:46:32.08#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:46:32.08#ibcon#[27=USB\r\n] 2006.257.20:46:32.08#ibcon#*before write, iclass 19, count 0 2006.257.20:46:32.08#ibcon#enter sib2, iclass 19, count 0 2006.257.20:46:32.08#ibcon#flushed, iclass 19, count 0 2006.257.20:46:32.08#ibcon#about to write, iclass 19, count 0 2006.257.20:46:32.08#ibcon#wrote, iclass 19, count 0 2006.257.20:46:32.08#ibcon#about to read 3, iclass 19, count 0 2006.257.20:46:32.11#ibcon#read 3, iclass 19, count 0 2006.257.20:46:32.11#ibcon#about to read 4, iclass 19, count 0 2006.257.20:46:32.11#ibcon#read 4, iclass 19, count 0 2006.257.20:46:32.11#ibcon#about to read 5, iclass 19, count 0 2006.257.20:46:32.11#ibcon#read 5, iclass 19, count 0 2006.257.20:46:32.11#ibcon#about to read 6, iclass 19, count 0 2006.257.20:46:32.11#ibcon#read 6, iclass 19, count 0 2006.257.20:46:32.11#ibcon#end of sib2, iclass 19, count 0 2006.257.20:46:32.11#ibcon#*after write, iclass 19, count 0 2006.257.20:46:32.11#ibcon#*before return 0, iclass 19, count 0 2006.257.20:46:32.11#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:32.11#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.20:46:32.11#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:46:32.11#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:46:32.11$vck44/vblo=4,679.99 2006.257.20:46:32.11#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.20:46:32.11#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.20:46:32.11#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:32.11#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:32.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:32.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:32.11#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:46:32.11#ibcon#first serial, iclass 21, count 0 2006.257.20:46:32.11#ibcon#enter sib2, iclass 21, count 0 2006.257.20:46:32.11#ibcon#flushed, iclass 21, count 0 2006.257.20:46:32.11#ibcon#about to write, iclass 21, count 0 2006.257.20:46:32.11#ibcon#wrote, iclass 21, count 0 2006.257.20:46:32.11#ibcon#about to read 3, iclass 21, count 0 2006.257.20:46:32.13#ibcon#read 3, iclass 21, count 0 2006.257.20:46:32.13#ibcon#about to read 4, iclass 21, count 0 2006.257.20:46:32.13#ibcon#read 4, iclass 21, count 0 2006.257.20:46:32.13#ibcon#about to read 5, iclass 21, count 0 2006.257.20:46:32.13#ibcon#read 5, iclass 21, count 0 2006.257.20:46:32.13#ibcon#about to read 6, iclass 21, count 0 2006.257.20:46:32.13#ibcon#read 6, iclass 21, count 0 2006.257.20:46:32.13#ibcon#end of sib2, iclass 21, count 0 2006.257.20:46:32.13#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:46:32.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:46:32.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.20:46:32.13#ibcon#*before write, iclass 21, count 0 2006.257.20:46:32.13#ibcon#enter sib2, iclass 21, count 0 2006.257.20:46:32.13#ibcon#flushed, iclass 21, count 0 2006.257.20:46:32.13#ibcon#about to write, iclass 21, count 0 2006.257.20:46:32.13#ibcon#wrote, iclass 21, count 0 2006.257.20:46:32.13#ibcon#about to read 3, iclass 21, count 0 2006.257.20:46:32.17#ibcon#read 3, iclass 21, count 0 2006.257.20:46:32.17#ibcon#about to read 4, iclass 21, count 0 2006.257.20:46:32.17#ibcon#read 4, iclass 21, count 0 2006.257.20:46:32.17#ibcon#about to read 5, iclass 21, count 0 2006.257.20:46:32.17#ibcon#read 5, iclass 21, count 0 2006.257.20:46:32.17#ibcon#about to read 6, iclass 21, count 0 2006.257.20:46:32.17#ibcon#read 6, iclass 21, count 0 2006.257.20:46:32.17#ibcon#end of sib2, iclass 21, count 0 2006.257.20:46:32.17#ibcon#*after write, iclass 21, count 0 2006.257.20:46:32.17#ibcon#*before return 0, iclass 21, count 0 2006.257.20:46:32.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:32.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.20:46:32.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:46:32.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:46:32.17$vck44/vb=4,5 2006.257.20:46:32.17#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.20:46:32.17#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.20:46:32.17#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:32.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:32.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:32.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:32.23#ibcon#enter wrdev, iclass 23, count 2 2006.257.20:46:32.23#ibcon#first serial, iclass 23, count 2 2006.257.20:46:32.23#ibcon#enter sib2, iclass 23, count 2 2006.257.20:46:32.23#ibcon#flushed, iclass 23, count 2 2006.257.20:46:32.23#ibcon#about to write, iclass 23, count 2 2006.257.20:46:32.23#ibcon#wrote, iclass 23, count 2 2006.257.20:46:32.23#ibcon#about to read 3, iclass 23, count 2 2006.257.20:46:32.25#ibcon#read 3, iclass 23, count 2 2006.257.20:46:32.25#ibcon#about to read 4, iclass 23, count 2 2006.257.20:46:32.25#ibcon#read 4, iclass 23, count 2 2006.257.20:46:32.25#ibcon#about to read 5, iclass 23, count 2 2006.257.20:46:32.25#ibcon#read 5, iclass 23, count 2 2006.257.20:46:32.25#ibcon#about to read 6, iclass 23, count 2 2006.257.20:46:32.25#ibcon#read 6, iclass 23, count 2 2006.257.20:46:32.25#ibcon#end of sib2, iclass 23, count 2 2006.257.20:46:32.25#ibcon#*mode == 0, iclass 23, count 2 2006.257.20:46:32.25#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.20:46:32.25#ibcon#[27=AT04-05\r\n] 2006.257.20:46:32.25#ibcon#*before write, iclass 23, count 2 2006.257.20:46:32.25#ibcon#enter sib2, iclass 23, count 2 2006.257.20:46:32.25#ibcon#flushed, iclass 23, count 2 2006.257.20:46:32.25#ibcon#about to write, iclass 23, count 2 2006.257.20:46:32.25#ibcon#wrote, iclass 23, count 2 2006.257.20:46:32.25#ibcon#about to read 3, iclass 23, count 2 2006.257.20:46:32.28#ibcon#read 3, iclass 23, count 2 2006.257.20:46:32.28#ibcon#about to read 4, iclass 23, count 2 2006.257.20:46:32.28#ibcon#read 4, iclass 23, count 2 2006.257.20:46:32.28#ibcon#about to read 5, iclass 23, count 2 2006.257.20:46:32.28#ibcon#read 5, iclass 23, count 2 2006.257.20:46:32.28#ibcon#about to read 6, iclass 23, count 2 2006.257.20:46:32.28#ibcon#read 6, iclass 23, count 2 2006.257.20:46:32.28#ibcon#end of sib2, iclass 23, count 2 2006.257.20:46:32.28#ibcon#*after write, iclass 23, count 2 2006.257.20:46:32.28#ibcon#*before return 0, iclass 23, count 2 2006.257.20:46:32.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:32.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.20:46:32.28#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.20:46:32.28#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:32.28#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:32.40#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:32.40#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:32.40#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:46:32.40#ibcon#first serial, iclass 23, count 0 2006.257.20:46:32.40#ibcon#enter sib2, iclass 23, count 0 2006.257.20:46:32.40#ibcon#flushed, iclass 23, count 0 2006.257.20:46:32.40#ibcon#about to write, iclass 23, count 0 2006.257.20:46:32.40#ibcon#wrote, iclass 23, count 0 2006.257.20:46:32.40#ibcon#about to read 3, iclass 23, count 0 2006.257.20:46:32.42#ibcon#read 3, iclass 23, count 0 2006.257.20:46:32.42#ibcon#about to read 4, iclass 23, count 0 2006.257.20:46:32.42#ibcon#read 4, iclass 23, count 0 2006.257.20:46:32.42#ibcon#about to read 5, iclass 23, count 0 2006.257.20:46:32.42#ibcon#read 5, iclass 23, count 0 2006.257.20:46:32.42#ibcon#about to read 6, iclass 23, count 0 2006.257.20:46:32.42#ibcon#read 6, iclass 23, count 0 2006.257.20:46:32.42#ibcon#end of sib2, iclass 23, count 0 2006.257.20:46:32.42#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:46:32.42#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:46:32.42#ibcon#[27=USB\r\n] 2006.257.20:46:32.42#ibcon#*before write, iclass 23, count 0 2006.257.20:46:32.42#ibcon#enter sib2, iclass 23, count 0 2006.257.20:46:32.42#ibcon#flushed, iclass 23, count 0 2006.257.20:46:32.42#ibcon#about to write, iclass 23, count 0 2006.257.20:46:32.42#ibcon#wrote, iclass 23, count 0 2006.257.20:46:32.42#ibcon#about to read 3, iclass 23, count 0 2006.257.20:46:32.45#ibcon#read 3, iclass 23, count 0 2006.257.20:46:32.45#ibcon#about to read 4, iclass 23, count 0 2006.257.20:46:32.45#ibcon#read 4, iclass 23, count 0 2006.257.20:46:32.45#ibcon#about to read 5, iclass 23, count 0 2006.257.20:46:32.45#ibcon#read 5, iclass 23, count 0 2006.257.20:46:32.45#ibcon#about to read 6, iclass 23, count 0 2006.257.20:46:32.45#ibcon#read 6, iclass 23, count 0 2006.257.20:46:32.45#ibcon#end of sib2, iclass 23, count 0 2006.257.20:46:32.45#ibcon#*after write, iclass 23, count 0 2006.257.20:46:32.45#ibcon#*before return 0, iclass 23, count 0 2006.257.20:46:32.45#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:32.45#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.20:46:32.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:46:32.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:46:32.45$vck44/vblo=5,709.99 2006.257.20:46:32.45#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.20:46:32.45#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.20:46:32.45#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:32.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:32.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:32.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:32.45#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:46:32.45#ibcon#first serial, iclass 25, count 0 2006.257.20:46:32.45#ibcon#enter sib2, iclass 25, count 0 2006.257.20:46:32.45#ibcon#flushed, iclass 25, count 0 2006.257.20:46:32.45#ibcon#about to write, iclass 25, count 0 2006.257.20:46:32.45#ibcon#wrote, iclass 25, count 0 2006.257.20:46:32.45#ibcon#about to read 3, iclass 25, count 0 2006.257.20:46:32.47#ibcon#read 3, iclass 25, count 0 2006.257.20:46:32.47#ibcon#about to read 4, iclass 25, count 0 2006.257.20:46:32.47#ibcon#read 4, iclass 25, count 0 2006.257.20:46:32.47#ibcon#about to read 5, iclass 25, count 0 2006.257.20:46:32.47#ibcon#read 5, iclass 25, count 0 2006.257.20:46:32.47#ibcon#about to read 6, iclass 25, count 0 2006.257.20:46:32.47#ibcon#read 6, iclass 25, count 0 2006.257.20:46:32.47#ibcon#end of sib2, iclass 25, count 0 2006.257.20:46:32.47#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:46:32.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:46:32.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.20:46:32.47#ibcon#*before write, iclass 25, count 0 2006.257.20:46:32.47#ibcon#enter sib2, iclass 25, count 0 2006.257.20:46:32.47#ibcon#flushed, iclass 25, count 0 2006.257.20:46:32.47#ibcon#about to write, iclass 25, count 0 2006.257.20:46:32.47#ibcon#wrote, iclass 25, count 0 2006.257.20:46:32.47#ibcon#about to read 3, iclass 25, count 0 2006.257.20:46:32.51#ibcon#read 3, iclass 25, count 0 2006.257.20:46:32.51#ibcon#about to read 4, iclass 25, count 0 2006.257.20:46:32.51#ibcon#read 4, iclass 25, count 0 2006.257.20:46:32.51#ibcon#about to read 5, iclass 25, count 0 2006.257.20:46:32.51#ibcon#read 5, iclass 25, count 0 2006.257.20:46:32.51#ibcon#about to read 6, iclass 25, count 0 2006.257.20:46:32.51#ibcon#read 6, iclass 25, count 0 2006.257.20:46:32.51#ibcon#end of sib2, iclass 25, count 0 2006.257.20:46:32.51#ibcon#*after write, iclass 25, count 0 2006.257.20:46:32.51#ibcon#*before return 0, iclass 25, count 0 2006.257.20:46:32.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:32.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.20:46:32.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:46:32.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:46:32.51$vck44/vb=5,4 2006.257.20:46:32.51#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.20:46:32.51#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.20:46:32.51#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:32.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:32.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:32.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:32.57#ibcon#enter wrdev, iclass 27, count 2 2006.257.20:46:32.57#ibcon#first serial, iclass 27, count 2 2006.257.20:46:32.57#ibcon#enter sib2, iclass 27, count 2 2006.257.20:46:32.57#ibcon#flushed, iclass 27, count 2 2006.257.20:46:32.57#ibcon#about to write, iclass 27, count 2 2006.257.20:46:32.57#ibcon#wrote, iclass 27, count 2 2006.257.20:46:32.57#ibcon#about to read 3, iclass 27, count 2 2006.257.20:46:32.59#ibcon#read 3, iclass 27, count 2 2006.257.20:46:32.59#ibcon#about to read 4, iclass 27, count 2 2006.257.20:46:32.59#ibcon#read 4, iclass 27, count 2 2006.257.20:46:32.59#ibcon#about to read 5, iclass 27, count 2 2006.257.20:46:32.59#ibcon#read 5, iclass 27, count 2 2006.257.20:46:32.59#ibcon#about to read 6, iclass 27, count 2 2006.257.20:46:32.59#ibcon#read 6, iclass 27, count 2 2006.257.20:46:32.59#ibcon#end of sib2, iclass 27, count 2 2006.257.20:46:32.59#ibcon#*mode == 0, iclass 27, count 2 2006.257.20:46:32.59#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.20:46:32.59#ibcon#[27=AT05-04\r\n] 2006.257.20:46:32.59#ibcon#*before write, iclass 27, count 2 2006.257.20:46:32.59#ibcon#enter sib2, iclass 27, count 2 2006.257.20:46:32.59#ibcon#flushed, iclass 27, count 2 2006.257.20:46:32.59#ibcon#about to write, iclass 27, count 2 2006.257.20:46:32.59#ibcon#wrote, iclass 27, count 2 2006.257.20:46:32.59#ibcon#about to read 3, iclass 27, count 2 2006.257.20:46:32.62#ibcon#read 3, iclass 27, count 2 2006.257.20:46:32.62#ibcon#about to read 4, iclass 27, count 2 2006.257.20:46:32.62#ibcon#read 4, iclass 27, count 2 2006.257.20:46:32.62#ibcon#about to read 5, iclass 27, count 2 2006.257.20:46:32.62#ibcon#read 5, iclass 27, count 2 2006.257.20:46:32.62#ibcon#about to read 6, iclass 27, count 2 2006.257.20:46:32.62#ibcon#read 6, iclass 27, count 2 2006.257.20:46:32.62#ibcon#end of sib2, iclass 27, count 2 2006.257.20:46:32.62#ibcon#*after write, iclass 27, count 2 2006.257.20:46:32.62#ibcon#*before return 0, iclass 27, count 2 2006.257.20:46:32.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:32.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.20:46:32.62#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.20:46:32.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:32.62#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:32.74#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:32.74#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:32.74#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:46:32.74#ibcon#first serial, iclass 27, count 0 2006.257.20:46:32.74#ibcon#enter sib2, iclass 27, count 0 2006.257.20:46:32.74#ibcon#flushed, iclass 27, count 0 2006.257.20:46:32.74#ibcon#about to write, iclass 27, count 0 2006.257.20:46:32.74#ibcon#wrote, iclass 27, count 0 2006.257.20:46:32.74#ibcon#about to read 3, iclass 27, count 0 2006.257.20:46:32.76#ibcon#read 3, iclass 27, count 0 2006.257.20:46:32.76#ibcon#about to read 4, iclass 27, count 0 2006.257.20:46:32.76#ibcon#read 4, iclass 27, count 0 2006.257.20:46:32.76#ibcon#about to read 5, iclass 27, count 0 2006.257.20:46:32.76#ibcon#read 5, iclass 27, count 0 2006.257.20:46:32.76#ibcon#about to read 6, iclass 27, count 0 2006.257.20:46:32.76#ibcon#read 6, iclass 27, count 0 2006.257.20:46:32.76#ibcon#end of sib2, iclass 27, count 0 2006.257.20:46:32.76#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:46:32.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:46:32.76#ibcon#[27=USB\r\n] 2006.257.20:46:32.76#ibcon#*before write, iclass 27, count 0 2006.257.20:46:32.76#ibcon#enter sib2, iclass 27, count 0 2006.257.20:46:32.76#ibcon#flushed, iclass 27, count 0 2006.257.20:46:32.76#ibcon#about to write, iclass 27, count 0 2006.257.20:46:32.76#ibcon#wrote, iclass 27, count 0 2006.257.20:46:32.76#ibcon#about to read 3, iclass 27, count 0 2006.257.20:46:32.79#ibcon#read 3, iclass 27, count 0 2006.257.20:46:32.79#ibcon#about to read 4, iclass 27, count 0 2006.257.20:46:32.79#ibcon#read 4, iclass 27, count 0 2006.257.20:46:32.79#ibcon#about to read 5, iclass 27, count 0 2006.257.20:46:32.79#ibcon#read 5, iclass 27, count 0 2006.257.20:46:32.79#ibcon#about to read 6, iclass 27, count 0 2006.257.20:46:32.79#ibcon#read 6, iclass 27, count 0 2006.257.20:46:32.79#ibcon#end of sib2, iclass 27, count 0 2006.257.20:46:32.79#ibcon#*after write, iclass 27, count 0 2006.257.20:46:32.79#ibcon#*before return 0, iclass 27, count 0 2006.257.20:46:32.79#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:32.79#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.20:46:32.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:46:32.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:46:32.79$vck44/vblo=6,719.99 2006.257.20:46:32.79#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.20:46:32.79#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.20:46:32.79#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:32.79#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:32.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:32.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:32.79#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:46:32.79#ibcon#first serial, iclass 29, count 0 2006.257.20:46:32.79#ibcon#enter sib2, iclass 29, count 0 2006.257.20:46:32.79#ibcon#flushed, iclass 29, count 0 2006.257.20:46:32.79#ibcon#about to write, iclass 29, count 0 2006.257.20:46:32.79#ibcon#wrote, iclass 29, count 0 2006.257.20:46:32.79#ibcon#about to read 3, iclass 29, count 0 2006.257.20:46:32.81#ibcon#read 3, iclass 29, count 0 2006.257.20:46:32.81#ibcon#about to read 4, iclass 29, count 0 2006.257.20:46:32.81#ibcon#read 4, iclass 29, count 0 2006.257.20:46:32.81#ibcon#about to read 5, iclass 29, count 0 2006.257.20:46:32.81#ibcon#read 5, iclass 29, count 0 2006.257.20:46:32.81#ibcon#about to read 6, iclass 29, count 0 2006.257.20:46:32.81#ibcon#read 6, iclass 29, count 0 2006.257.20:46:32.81#ibcon#end of sib2, iclass 29, count 0 2006.257.20:46:32.81#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:46:32.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:46:32.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.20:46:32.81#ibcon#*before write, iclass 29, count 0 2006.257.20:46:32.81#ibcon#enter sib2, iclass 29, count 0 2006.257.20:46:32.81#ibcon#flushed, iclass 29, count 0 2006.257.20:46:32.81#ibcon#about to write, iclass 29, count 0 2006.257.20:46:32.81#ibcon#wrote, iclass 29, count 0 2006.257.20:46:32.81#ibcon#about to read 3, iclass 29, count 0 2006.257.20:46:32.85#ibcon#read 3, iclass 29, count 0 2006.257.20:46:32.85#ibcon#about to read 4, iclass 29, count 0 2006.257.20:46:32.85#ibcon#read 4, iclass 29, count 0 2006.257.20:46:32.85#ibcon#about to read 5, iclass 29, count 0 2006.257.20:46:32.85#ibcon#read 5, iclass 29, count 0 2006.257.20:46:32.85#ibcon#about to read 6, iclass 29, count 0 2006.257.20:46:32.85#ibcon#read 6, iclass 29, count 0 2006.257.20:46:32.85#ibcon#end of sib2, iclass 29, count 0 2006.257.20:46:32.85#ibcon#*after write, iclass 29, count 0 2006.257.20:46:32.85#ibcon#*before return 0, iclass 29, count 0 2006.257.20:46:32.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:32.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.20:46:32.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:46:32.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:46:32.85$vck44/vb=6,4 2006.257.20:46:32.85#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.20:46:32.85#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.20:46:32.85#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:32.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:32.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:32.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:32.91#ibcon#enter wrdev, iclass 31, count 2 2006.257.20:46:32.91#ibcon#first serial, iclass 31, count 2 2006.257.20:46:32.91#ibcon#enter sib2, iclass 31, count 2 2006.257.20:46:32.91#ibcon#flushed, iclass 31, count 2 2006.257.20:46:32.91#ibcon#about to write, iclass 31, count 2 2006.257.20:46:32.91#ibcon#wrote, iclass 31, count 2 2006.257.20:46:32.91#ibcon#about to read 3, iclass 31, count 2 2006.257.20:46:32.93#ibcon#read 3, iclass 31, count 2 2006.257.20:46:32.93#ibcon#about to read 4, iclass 31, count 2 2006.257.20:46:32.93#ibcon#read 4, iclass 31, count 2 2006.257.20:46:32.93#ibcon#about to read 5, iclass 31, count 2 2006.257.20:46:32.93#ibcon#read 5, iclass 31, count 2 2006.257.20:46:32.93#ibcon#about to read 6, iclass 31, count 2 2006.257.20:46:32.93#ibcon#read 6, iclass 31, count 2 2006.257.20:46:32.93#ibcon#end of sib2, iclass 31, count 2 2006.257.20:46:32.93#ibcon#*mode == 0, iclass 31, count 2 2006.257.20:46:32.93#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.20:46:32.93#ibcon#[27=AT06-04\r\n] 2006.257.20:46:32.93#ibcon#*before write, iclass 31, count 2 2006.257.20:46:32.93#ibcon#enter sib2, iclass 31, count 2 2006.257.20:46:32.93#ibcon#flushed, iclass 31, count 2 2006.257.20:46:32.93#ibcon#about to write, iclass 31, count 2 2006.257.20:46:32.93#ibcon#wrote, iclass 31, count 2 2006.257.20:46:32.93#ibcon#about to read 3, iclass 31, count 2 2006.257.20:46:32.96#ibcon#read 3, iclass 31, count 2 2006.257.20:46:32.96#ibcon#about to read 4, iclass 31, count 2 2006.257.20:46:32.96#ibcon#read 4, iclass 31, count 2 2006.257.20:46:32.96#ibcon#about to read 5, iclass 31, count 2 2006.257.20:46:32.96#ibcon#read 5, iclass 31, count 2 2006.257.20:46:32.96#ibcon#about to read 6, iclass 31, count 2 2006.257.20:46:32.96#ibcon#read 6, iclass 31, count 2 2006.257.20:46:32.96#ibcon#end of sib2, iclass 31, count 2 2006.257.20:46:32.96#ibcon#*after write, iclass 31, count 2 2006.257.20:46:32.96#ibcon#*before return 0, iclass 31, count 2 2006.257.20:46:32.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:32.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.20:46:32.96#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.20:46:32.96#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:32.96#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:33.03#abcon#<5=/14 0.9 2.1 17.19 981014.9\r\n> 2006.257.20:46:33.05#abcon#{5=INTERFACE CLEAR} 2006.257.20:46:33.08#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:33.08#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:33.08#ibcon#enter wrdev, iclass 31, count 0 2006.257.20:46:33.08#ibcon#first serial, iclass 31, count 0 2006.257.20:46:33.08#ibcon#enter sib2, iclass 31, count 0 2006.257.20:46:33.08#ibcon#flushed, iclass 31, count 0 2006.257.20:46:33.08#ibcon#about to write, iclass 31, count 0 2006.257.20:46:33.08#ibcon#wrote, iclass 31, count 0 2006.257.20:46:33.08#ibcon#about to read 3, iclass 31, count 0 2006.257.20:46:33.10#ibcon#read 3, iclass 31, count 0 2006.257.20:46:33.10#ibcon#about to read 4, iclass 31, count 0 2006.257.20:46:33.10#ibcon#read 4, iclass 31, count 0 2006.257.20:46:33.10#ibcon#about to read 5, iclass 31, count 0 2006.257.20:46:33.10#ibcon#read 5, iclass 31, count 0 2006.257.20:46:33.10#ibcon#about to read 6, iclass 31, count 0 2006.257.20:46:33.10#ibcon#read 6, iclass 31, count 0 2006.257.20:46:33.10#ibcon#end of sib2, iclass 31, count 0 2006.257.20:46:33.10#ibcon#*mode == 0, iclass 31, count 0 2006.257.20:46:33.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.20:46:33.10#ibcon#[27=USB\r\n] 2006.257.20:46:33.10#ibcon#*before write, iclass 31, count 0 2006.257.20:46:33.10#ibcon#enter sib2, iclass 31, count 0 2006.257.20:46:33.10#ibcon#flushed, iclass 31, count 0 2006.257.20:46:33.10#ibcon#about to write, iclass 31, count 0 2006.257.20:46:33.10#ibcon#wrote, iclass 31, count 0 2006.257.20:46:33.10#ibcon#about to read 3, iclass 31, count 0 2006.257.20:46:33.11#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:46:33.13#ibcon#read 3, iclass 31, count 0 2006.257.20:46:33.13#ibcon#about to read 4, iclass 31, count 0 2006.257.20:46:33.13#ibcon#read 4, iclass 31, count 0 2006.257.20:46:33.13#ibcon#about to read 5, iclass 31, count 0 2006.257.20:46:33.13#ibcon#read 5, iclass 31, count 0 2006.257.20:46:33.13#ibcon#about to read 6, iclass 31, count 0 2006.257.20:46:33.13#ibcon#read 6, iclass 31, count 0 2006.257.20:46:33.13#ibcon#end of sib2, iclass 31, count 0 2006.257.20:46:33.13#ibcon#*after write, iclass 31, count 0 2006.257.20:46:33.13#ibcon#*before return 0, iclass 31, count 0 2006.257.20:46:33.13#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:33.13#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.20:46:33.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.20:46:33.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.20:46:33.13$vck44/vblo=7,734.99 2006.257.20:46:33.13#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.20:46:33.13#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.20:46:33.13#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:33.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:33.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:33.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:33.13#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:46:33.13#ibcon#first serial, iclass 37, count 0 2006.257.20:46:33.13#ibcon#enter sib2, iclass 37, count 0 2006.257.20:46:33.13#ibcon#flushed, iclass 37, count 0 2006.257.20:46:33.13#ibcon#about to write, iclass 37, count 0 2006.257.20:46:33.13#ibcon#wrote, iclass 37, count 0 2006.257.20:46:33.13#ibcon#about to read 3, iclass 37, count 0 2006.257.20:46:33.15#ibcon#read 3, iclass 37, count 0 2006.257.20:46:33.15#ibcon#about to read 4, iclass 37, count 0 2006.257.20:46:33.15#ibcon#read 4, iclass 37, count 0 2006.257.20:46:33.15#ibcon#about to read 5, iclass 37, count 0 2006.257.20:46:33.15#ibcon#read 5, iclass 37, count 0 2006.257.20:46:33.15#ibcon#about to read 6, iclass 37, count 0 2006.257.20:46:33.15#ibcon#read 6, iclass 37, count 0 2006.257.20:46:33.15#ibcon#end of sib2, iclass 37, count 0 2006.257.20:46:33.15#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:46:33.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:46:33.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.20:46:33.15#ibcon#*before write, iclass 37, count 0 2006.257.20:46:33.15#ibcon#enter sib2, iclass 37, count 0 2006.257.20:46:33.15#ibcon#flushed, iclass 37, count 0 2006.257.20:46:33.15#ibcon#about to write, iclass 37, count 0 2006.257.20:46:33.15#ibcon#wrote, iclass 37, count 0 2006.257.20:46:33.15#ibcon#about to read 3, iclass 37, count 0 2006.257.20:46:33.19#ibcon#read 3, iclass 37, count 0 2006.257.20:46:33.19#ibcon#about to read 4, iclass 37, count 0 2006.257.20:46:33.19#ibcon#read 4, iclass 37, count 0 2006.257.20:46:33.19#ibcon#about to read 5, iclass 37, count 0 2006.257.20:46:33.19#ibcon#read 5, iclass 37, count 0 2006.257.20:46:33.19#ibcon#about to read 6, iclass 37, count 0 2006.257.20:46:33.19#ibcon#read 6, iclass 37, count 0 2006.257.20:46:33.19#ibcon#end of sib2, iclass 37, count 0 2006.257.20:46:33.19#ibcon#*after write, iclass 37, count 0 2006.257.20:46:33.19#ibcon#*before return 0, iclass 37, count 0 2006.257.20:46:33.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:33.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:46:33.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:46:33.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:46:33.19$vck44/vb=7,4 2006.257.20:46:33.19#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.20:46:33.19#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.20:46:33.19#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:33.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:33.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:33.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:33.25#ibcon#enter wrdev, iclass 39, count 2 2006.257.20:46:33.25#ibcon#first serial, iclass 39, count 2 2006.257.20:46:33.25#ibcon#enter sib2, iclass 39, count 2 2006.257.20:46:33.25#ibcon#flushed, iclass 39, count 2 2006.257.20:46:33.25#ibcon#about to write, iclass 39, count 2 2006.257.20:46:33.25#ibcon#wrote, iclass 39, count 2 2006.257.20:46:33.25#ibcon#about to read 3, iclass 39, count 2 2006.257.20:46:33.27#ibcon#read 3, iclass 39, count 2 2006.257.20:46:33.27#ibcon#about to read 4, iclass 39, count 2 2006.257.20:46:33.27#ibcon#read 4, iclass 39, count 2 2006.257.20:46:33.27#ibcon#about to read 5, iclass 39, count 2 2006.257.20:46:33.27#ibcon#read 5, iclass 39, count 2 2006.257.20:46:33.27#ibcon#about to read 6, iclass 39, count 2 2006.257.20:46:33.27#ibcon#read 6, iclass 39, count 2 2006.257.20:46:33.27#ibcon#end of sib2, iclass 39, count 2 2006.257.20:46:33.27#ibcon#*mode == 0, iclass 39, count 2 2006.257.20:46:33.27#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.20:46:33.27#ibcon#[27=AT07-04\r\n] 2006.257.20:46:33.27#ibcon#*before write, iclass 39, count 2 2006.257.20:46:33.27#ibcon#enter sib2, iclass 39, count 2 2006.257.20:46:33.27#ibcon#flushed, iclass 39, count 2 2006.257.20:46:33.27#ibcon#about to write, iclass 39, count 2 2006.257.20:46:33.27#ibcon#wrote, iclass 39, count 2 2006.257.20:46:33.27#ibcon#about to read 3, iclass 39, count 2 2006.257.20:46:33.30#ibcon#read 3, iclass 39, count 2 2006.257.20:46:33.30#ibcon#about to read 4, iclass 39, count 2 2006.257.20:46:33.30#ibcon#read 4, iclass 39, count 2 2006.257.20:46:33.30#ibcon#about to read 5, iclass 39, count 2 2006.257.20:46:33.30#ibcon#read 5, iclass 39, count 2 2006.257.20:46:33.30#ibcon#about to read 6, iclass 39, count 2 2006.257.20:46:33.30#ibcon#read 6, iclass 39, count 2 2006.257.20:46:33.30#ibcon#end of sib2, iclass 39, count 2 2006.257.20:46:33.30#ibcon#*after write, iclass 39, count 2 2006.257.20:46:33.30#ibcon#*before return 0, iclass 39, count 2 2006.257.20:46:33.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:33.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.20:46:33.30#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.20:46:33.30#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:33.30#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:33.42#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:33.42#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:33.42#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:46:33.42#ibcon#first serial, iclass 39, count 0 2006.257.20:46:33.42#ibcon#enter sib2, iclass 39, count 0 2006.257.20:46:33.42#ibcon#flushed, iclass 39, count 0 2006.257.20:46:33.42#ibcon#about to write, iclass 39, count 0 2006.257.20:46:33.42#ibcon#wrote, iclass 39, count 0 2006.257.20:46:33.42#ibcon#about to read 3, iclass 39, count 0 2006.257.20:46:33.44#ibcon#read 3, iclass 39, count 0 2006.257.20:46:33.44#ibcon#about to read 4, iclass 39, count 0 2006.257.20:46:33.44#ibcon#read 4, iclass 39, count 0 2006.257.20:46:33.44#ibcon#about to read 5, iclass 39, count 0 2006.257.20:46:33.44#ibcon#read 5, iclass 39, count 0 2006.257.20:46:33.44#ibcon#about to read 6, iclass 39, count 0 2006.257.20:46:33.44#ibcon#read 6, iclass 39, count 0 2006.257.20:46:33.44#ibcon#end of sib2, iclass 39, count 0 2006.257.20:46:33.44#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:46:33.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:46:33.44#ibcon#[27=USB\r\n] 2006.257.20:46:33.44#ibcon#*before write, iclass 39, count 0 2006.257.20:46:33.44#ibcon#enter sib2, iclass 39, count 0 2006.257.20:46:33.44#ibcon#flushed, iclass 39, count 0 2006.257.20:46:33.44#ibcon#about to write, iclass 39, count 0 2006.257.20:46:33.44#ibcon#wrote, iclass 39, count 0 2006.257.20:46:33.44#ibcon#about to read 3, iclass 39, count 0 2006.257.20:46:33.47#ibcon#read 3, iclass 39, count 0 2006.257.20:46:33.47#ibcon#about to read 4, iclass 39, count 0 2006.257.20:46:33.47#ibcon#read 4, iclass 39, count 0 2006.257.20:46:33.47#ibcon#about to read 5, iclass 39, count 0 2006.257.20:46:33.47#ibcon#read 5, iclass 39, count 0 2006.257.20:46:33.47#ibcon#about to read 6, iclass 39, count 0 2006.257.20:46:33.47#ibcon#read 6, iclass 39, count 0 2006.257.20:46:33.47#ibcon#end of sib2, iclass 39, count 0 2006.257.20:46:33.47#ibcon#*after write, iclass 39, count 0 2006.257.20:46:33.47#ibcon#*before return 0, iclass 39, count 0 2006.257.20:46:33.47#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:33.47#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.20:46:33.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:46:33.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:46:33.47$vck44/vblo=8,744.99 2006.257.20:46:33.47#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.20:46:33.47#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.20:46:33.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:46:33.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:33.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:33.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:33.47#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:46:33.47#ibcon#first serial, iclass 3, count 0 2006.257.20:46:33.47#ibcon#enter sib2, iclass 3, count 0 2006.257.20:46:33.47#ibcon#flushed, iclass 3, count 0 2006.257.20:46:33.47#ibcon#about to write, iclass 3, count 0 2006.257.20:46:33.47#ibcon#wrote, iclass 3, count 0 2006.257.20:46:33.47#ibcon#about to read 3, iclass 3, count 0 2006.257.20:46:33.49#ibcon#read 3, iclass 3, count 0 2006.257.20:46:33.49#ibcon#about to read 4, iclass 3, count 0 2006.257.20:46:33.49#ibcon#read 4, iclass 3, count 0 2006.257.20:46:33.49#ibcon#about to read 5, iclass 3, count 0 2006.257.20:46:33.49#ibcon#read 5, iclass 3, count 0 2006.257.20:46:33.49#ibcon#about to read 6, iclass 3, count 0 2006.257.20:46:33.49#ibcon#read 6, iclass 3, count 0 2006.257.20:46:33.49#ibcon#end of sib2, iclass 3, count 0 2006.257.20:46:33.49#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:46:33.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:46:33.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.20:46:33.49#ibcon#*before write, iclass 3, count 0 2006.257.20:46:33.49#ibcon#enter sib2, iclass 3, count 0 2006.257.20:46:33.49#ibcon#flushed, iclass 3, count 0 2006.257.20:46:33.49#ibcon#about to write, iclass 3, count 0 2006.257.20:46:33.49#ibcon#wrote, iclass 3, count 0 2006.257.20:46:33.49#ibcon#about to read 3, iclass 3, count 0 2006.257.20:46:33.53#ibcon#read 3, iclass 3, count 0 2006.257.20:46:33.53#ibcon#about to read 4, iclass 3, count 0 2006.257.20:46:33.53#ibcon#read 4, iclass 3, count 0 2006.257.20:46:33.53#ibcon#about to read 5, iclass 3, count 0 2006.257.20:46:33.53#ibcon#read 5, iclass 3, count 0 2006.257.20:46:33.53#ibcon#about to read 6, iclass 3, count 0 2006.257.20:46:33.53#ibcon#read 6, iclass 3, count 0 2006.257.20:46:33.53#ibcon#end of sib2, iclass 3, count 0 2006.257.20:46:33.53#ibcon#*after write, iclass 3, count 0 2006.257.20:46:33.53#ibcon#*before return 0, iclass 3, count 0 2006.257.20:46:33.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:33.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.20:46:33.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:46:33.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:46:33.53$vck44/vb=8,4 2006.257.20:46:33.53#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.20:46:33.53#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.20:46:33.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:46:33.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:33.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:33.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:33.59#ibcon#enter wrdev, iclass 5, count 2 2006.257.20:46:33.59#ibcon#first serial, iclass 5, count 2 2006.257.20:46:33.59#ibcon#enter sib2, iclass 5, count 2 2006.257.20:46:33.59#ibcon#flushed, iclass 5, count 2 2006.257.20:46:33.59#ibcon#about to write, iclass 5, count 2 2006.257.20:46:33.59#ibcon#wrote, iclass 5, count 2 2006.257.20:46:33.59#ibcon#about to read 3, iclass 5, count 2 2006.257.20:46:33.61#ibcon#read 3, iclass 5, count 2 2006.257.20:46:33.61#ibcon#about to read 4, iclass 5, count 2 2006.257.20:46:33.61#ibcon#read 4, iclass 5, count 2 2006.257.20:46:33.61#ibcon#about to read 5, iclass 5, count 2 2006.257.20:46:33.61#ibcon#read 5, iclass 5, count 2 2006.257.20:46:33.61#ibcon#about to read 6, iclass 5, count 2 2006.257.20:46:33.61#ibcon#read 6, iclass 5, count 2 2006.257.20:46:33.61#ibcon#end of sib2, iclass 5, count 2 2006.257.20:46:33.61#ibcon#*mode == 0, iclass 5, count 2 2006.257.20:46:33.61#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.20:46:33.61#ibcon#[27=AT08-04\r\n] 2006.257.20:46:33.61#ibcon#*before write, iclass 5, count 2 2006.257.20:46:33.61#ibcon#enter sib2, iclass 5, count 2 2006.257.20:46:33.61#ibcon#flushed, iclass 5, count 2 2006.257.20:46:33.61#ibcon#about to write, iclass 5, count 2 2006.257.20:46:33.61#ibcon#wrote, iclass 5, count 2 2006.257.20:46:33.61#ibcon#about to read 3, iclass 5, count 2 2006.257.20:46:33.64#ibcon#read 3, iclass 5, count 2 2006.257.20:46:33.64#ibcon#about to read 4, iclass 5, count 2 2006.257.20:46:33.64#ibcon#read 4, iclass 5, count 2 2006.257.20:46:33.64#ibcon#about to read 5, iclass 5, count 2 2006.257.20:46:33.64#ibcon#read 5, iclass 5, count 2 2006.257.20:46:33.64#ibcon#about to read 6, iclass 5, count 2 2006.257.20:46:33.64#ibcon#read 6, iclass 5, count 2 2006.257.20:46:33.64#ibcon#end of sib2, iclass 5, count 2 2006.257.20:46:33.64#ibcon#*after write, iclass 5, count 2 2006.257.20:46:33.64#ibcon#*before return 0, iclass 5, count 2 2006.257.20:46:33.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:33.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.20:46:33.64#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.20:46:33.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:46:33.64#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:33.76#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:33.76#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:33.76#ibcon#enter wrdev, iclass 5, count 0 2006.257.20:46:33.76#ibcon#first serial, iclass 5, count 0 2006.257.20:46:33.76#ibcon#enter sib2, iclass 5, count 0 2006.257.20:46:33.76#ibcon#flushed, iclass 5, count 0 2006.257.20:46:33.76#ibcon#about to write, iclass 5, count 0 2006.257.20:46:33.76#ibcon#wrote, iclass 5, count 0 2006.257.20:46:33.76#ibcon#about to read 3, iclass 5, count 0 2006.257.20:46:33.78#ibcon#read 3, iclass 5, count 0 2006.257.20:46:33.78#ibcon#about to read 4, iclass 5, count 0 2006.257.20:46:33.78#ibcon#read 4, iclass 5, count 0 2006.257.20:46:33.78#ibcon#about to read 5, iclass 5, count 0 2006.257.20:46:33.78#ibcon#read 5, iclass 5, count 0 2006.257.20:46:33.78#ibcon#about to read 6, iclass 5, count 0 2006.257.20:46:33.78#ibcon#read 6, iclass 5, count 0 2006.257.20:46:33.78#ibcon#end of sib2, iclass 5, count 0 2006.257.20:46:33.78#ibcon#*mode == 0, iclass 5, count 0 2006.257.20:46:33.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.20:46:33.78#ibcon#[27=USB\r\n] 2006.257.20:46:33.78#ibcon#*before write, iclass 5, count 0 2006.257.20:46:33.78#ibcon#enter sib2, iclass 5, count 0 2006.257.20:46:33.78#ibcon#flushed, iclass 5, count 0 2006.257.20:46:33.78#ibcon#about to write, iclass 5, count 0 2006.257.20:46:33.78#ibcon#wrote, iclass 5, count 0 2006.257.20:46:33.78#ibcon#about to read 3, iclass 5, count 0 2006.257.20:46:33.81#ibcon#read 3, iclass 5, count 0 2006.257.20:46:33.81#ibcon#about to read 4, iclass 5, count 0 2006.257.20:46:33.81#ibcon#read 4, iclass 5, count 0 2006.257.20:46:33.81#ibcon#about to read 5, iclass 5, count 0 2006.257.20:46:33.81#ibcon#read 5, iclass 5, count 0 2006.257.20:46:33.81#ibcon#about to read 6, iclass 5, count 0 2006.257.20:46:33.81#ibcon#read 6, iclass 5, count 0 2006.257.20:46:33.81#ibcon#end of sib2, iclass 5, count 0 2006.257.20:46:33.81#ibcon#*after write, iclass 5, count 0 2006.257.20:46:33.81#ibcon#*before return 0, iclass 5, count 0 2006.257.20:46:33.81#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:33.81#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.20:46:33.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.20:46:33.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.20:46:33.81$vck44/vabw=wide 2006.257.20:46:33.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.20:46:33.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.20:46:33.81#ibcon#ireg 8 cls_cnt 0 2006.257.20:46:33.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:33.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:33.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:33.81#ibcon#enter wrdev, iclass 7, count 0 2006.257.20:46:33.81#ibcon#first serial, iclass 7, count 0 2006.257.20:46:33.81#ibcon#enter sib2, iclass 7, count 0 2006.257.20:46:33.81#ibcon#flushed, iclass 7, count 0 2006.257.20:46:33.81#ibcon#about to write, iclass 7, count 0 2006.257.20:46:33.81#ibcon#wrote, iclass 7, count 0 2006.257.20:46:33.81#ibcon#about to read 3, iclass 7, count 0 2006.257.20:46:33.83#ibcon#read 3, iclass 7, count 0 2006.257.20:46:33.83#ibcon#about to read 4, iclass 7, count 0 2006.257.20:46:33.83#ibcon#read 4, iclass 7, count 0 2006.257.20:46:33.83#ibcon#about to read 5, iclass 7, count 0 2006.257.20:46:33.83#ibcon#read 5, iclass 7, count 0 2006.257.20:46:33.83#ibcon#about to read 6, iclass 7, count 0 2006.257.20:46:33.83#ibcon#read 6, iclass 7, count 0 2006.257.20:46:33.83#ibcon#end of sib2, iclass 7, count 0 2006.257.20:46:33.83#ibcon#*mode == 0, iclass 7, count 0 2006.257.20:46:33.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.20:46:33.83#ibcon#[25=BW32\r\n] 2006.257.20:46:33.83#ibcon#*before write, iclass 7, count 0 2006.257.20:46:33.83#ibcon#enter sib2, iclass 7, count 0 2006.257.20:46:33.83#ibcon#flushed, iclass 7, count 0 2006.257.20:46:33.83#ibcon#about to write, iclass 7, count 0 2006.257.20:46:33.83#ibcon#wrote, iclass 7, count 0 2006.257.20:46:33.83#ibcon#about to read 3, iclass 7, count 0 2006.257.20:46:33.86#ibcon#read 3, iclass 7, count 0 2006.257.20:46:33.86#ibcon#about to read 4, iclass 7, count 0 2006.257.20:46:33.86#ibcon#read 4, iclass 7, count 0 2006.257.20:46:33.86#ibcon#about to read 5, iclass 7, count 0 2006.257.20:46:33.86#ibcon#read 5, iclass 7, count 0 2006.257.20:46:33.86#ibcon#about to read 6, iclass 7, count 0 2006.257.20:46:33.86#ibcon#read 6, iclass 7, count 0 2006.257.20:46:33.86#ibcon#end of sib2, iclass 7, count 0 2006.257.20:46:33.86#ibcon#*after write, iclass 7, count 0 2006.257.20:46:33.86#ibcon#*before return 0, iclass 7, count 0 2006.257.20:46:33.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:33.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.20:46:33.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.20:46:33.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.20:46:33.86$vck44/vbbw=wide 2006.257.20:46:33.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.20:46:33.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.20:46:33.86#ibcon#ireg 8 cls_cnt 0 2006.257.20:46:33.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:46:33.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:46:33.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:46:33.93#ibcon#enter wrdev, iclass 11, count 0 2006.257.20:46:33.93#ibcon#first serial, iclass 11, count 0 2006.257.20:46:33.93#ibcon#enter sib2, iclass 11, count 0 2006.257.20:46:33.93#ibcon#flushed, iclass 11, count 0 2006.257.20:46:33.93#ibcon#about to write, iclass 11, count 0 2006.257.20:46:33.93#ibcon#wrote, iclass 11, count 0 2006.257.20:46:33.93#ibcon#about to read 3, iclass 11, count 0 2006.257.20:46:33.95#ibcon#read 3, iclass 11, count 0 2006.257.20:46:33.95#ibcon#about to read 4, iclass 11, count 0 2006.257.20:46:33.95#ibcon#read 4, iclass 11, count 0 2006.257.20:46:33.95#ibcon#about to read 5, iclass 11, count 0 2006.257.20:46:33.95#ibcon#read 5, iclass 11, count 0 2006.257.20:46:33.95#ibcon#about to read 6, iclass 11, count 0 2006.257.20:46:33.95#ibcon#read 6, iclass 11, count 0 2006.257.20:46:33.95#ibcon#end of sib2, iclass 11, count 0 2006.257.20:46:33.95#ibcon#*mode == 0, iclass 11, count 0 2006.257.20:46:33.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.20:46:33.95#ibcon#[27=BW32\r\n] 2006.257.20:46:33.95#ibcon#*before write, iclass 11, count 0 2006.257.20:46:33.95#ibcon#enter sib2, iclass 11, count 0 2006.257.20:46:33.95#ibcon#flushed, iclass 11, count 0 2006.257.20:46:33.95#ibcon#about to write, iclass 11, count 0 2006.257.20:46:33.95#ibcon#wrote, iclass 11, count 0 2006.257.20:46:33.95#ibcon#about to read 3, iclass 11, count 0 2006.257.20:46:33.98#ibcon#read 3, iclass 11, count 0 2006.257.20:46:33.98#ibcon#about to read 4, iclass 11, count 0 2006.257.20:46:33.98#ibcon#read 4, iclass 11, count 0 2006.257.20:46:33.98#ibcon#about to read 5, iclass 11, count 0 2006.257.20:46:33.98#ibcon#read 5, iclass 11, count 0 2006.257.20:46:33.98#ibcon#about to read 6, iclass 11, count 0 2006.257.20:46:33.98#ibcon#read 6, iclass 11, count 0 2006.257.20:46:33.98#ibcon#end of sib2, iclass 11, count 0 2006.257.20:46:33.98#ibcon#*after write, iclass 11, count 0 2006.257.20:46:33.98#ibcon#*before return 0, iclass 11, count 0 2006.257.20:46:33.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:46:33.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:46:33.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.20:46:33.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.20:46:33.98$setupk4/ifdk4 2006.257.20:46:33.98$ifdk4/lo= 2006.257.20:46:33.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.20:46:33.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.20:46:33.98$ifdk4/patch= 2006.257.20:46:33.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.20:46:33.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.20:46:33.98$setupk4/!*+20s 2006.257.20:46:43.20#abcon#<5=/14 0.8 2.0 17.20 981014.9\r\n> 2006.257.20:46:43.22#abcon#{5=INTERFACE CLEAR} 2006.257.20:46:43.28#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:46:48.49$setupk4/"tpicd 2006.257.20:46:48.49$setupk4/echo=off 2006.257.20:46:48.49$setupk4/xlog=off 2006.257.20:46:48.49:!2006.257.20:48:48 2006.257.20:46:50.14#trakl#Source acquired 2006.257.20:46:51.14#flagr#flagr/antenna,acquired 2006.257.20:48:48.00:preob 2006.257.20:48:49.14/onsource/TRACKING 2006.257.20:48:49.14:!2006.257.20:48:58 2006.257.20:48:58.00:"tape 2006.257.20:48:58.00:"st=record 2006.257.20:48:58.00:data_valid=on 2006.257.20:48:58.00:midob 2006.257.20:48:58.14/onsource/TRACKING 2006.257.20:48:58.14/wx/17.23,1015.0,97 2006.257.20:48:58.36/cable/+6.4851E-03 2006.257.20:48:59.45/va/01,08,usb,yes,31,34 2006.257.20:48:59.45/va/02,07,usb,yes,34,35 2006.257.20:48:59.45/va/03,08,usb,yes,31,32 2006.257.20:48:59.45/va/04,07,usb,yes,35,37 2006.257.20:48:59.45/va/05,04,usb,yes,31,32 2006.257.20:48:59.45/va/06,04,usb,yes,35,34 2006.257.20:48:59.45/va/07,04,usb,yes,35,36 2006.257.20:48:59.45/va/08,04,usb,yes,30,36 2006.257.20:48:59.68/valo/01,524.99,yes,locked 2006.257.20:48:59.68/valo/02,534.99,yes,locked 2006.257.20:48:59.68/valo/03,564.99,yes,locked 2006.257.20:48:59.68/valo/04,624.99,yes,locked 2006.257.20:48:59.68/valo/05,734.99,yes,locked 2006.257.20:48:59.68/valo/06,814.99,yes,locked 2006.257.20:48:59.68/valo/07,864.99,yes,locked 2006.257.20:48:59.68/valo/08,884.99,yes,locked 2006.257.20:49:00.77/vb/01,04,usb,yes,31,29 2006.257.20:49:00.77/vb/02,05,usb,yes,29,29 2006.257.20:49:00.77/vb/03,04,usb,yes,30,33 2006.257.20:49:00.77/vb/04,05,usb,yes,30,29 2006.257.20:49:00.77/vb/05,04,usb,yes,27,29 2006.257.20:49:00.77/vb/06,04,usb,yes,32,28 2006.257.20:49:00.77/vb/07,04,usb,yes,31,31 2006.257.20:49:00.77/vb/08,04,usb,yes,29,32 2006.257.20:49:01.00/vblo/01,629.99,yes,locked 2006.257.20:49:01.00/vblo/02,634.99,yes,locked 2006.257.20:49:01.00/vblo/03,649.99,yes,locked 2006.257.20:49:01.00/vblo/04,679.99,yes,locked 2006.257.20:49:01.00/vblo/05,709.99,yes,locked 2006.257.20:49:01.00/vblo/06,719.99,yes,locked 2006.257.20:49:01.00/vblo/07,734.99,yes,locked 2006.257.20:49:01.00/vblo/08,744.99,yes,locked 2006.257.20:49:01.15/vabw/8 2006.257.20:49:01.30/vbbw/8 2006.257.20:49:01.39/xfe/off,on,15.2 2006.257.20:49:01.78/ifatt/23,28,28,28 2006.257.20:49:02.07/fmout-gps/S +4.58E-07 2006.257.20:49:02.11:!2006.257.20:52:28 2006.257.20:52:28.01:data_valid=off 2006.257.20:52:28.01:"et 2006.257.20:52:28.01:!+3s 2006.257.20:52:31.02:"tape 2006.257.20:52:31.02:postob 2006.257.20:52:31.08/cable/+6.4836E-03 2006.257.20:52:31.08/wx/17.32,1015.0,97 2006.257.20:52:31.14/fmout-gps/S +4.61E-07 2006.257.20:52:31.14:scan_name=257-2057,jd0609,120 2006.257.20:52:31.14:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.257.20:52:32.13#flagr#flagr/antenna,new-source 2006.257.20:52:32.13:checkk5 2006.257.20:52:32.46/chk_autoobs//k5ts1/ autoobs is running! 2006.257.20:52:32.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.20:52:33.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.20:52:33.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.20:52:33.84/chk_obsdata//k5ts1/T2572048??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.20:52:34.17/chk_obsdata//k5ts2/T2572048??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.20:52:34.51/chk_obsdata//k5ts3/T2572048??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.20:52:34.84/chk_obsdata//k5ts4/T2572048??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.20:52:35.49/k5log//k5ts1_log_newline 2006.257.20:52:36.16/k5log//k5ts2_log_newline 2006.257.20:52:36.80/k5log//k5ts3_log_newline 2006.257.20:52:37.46/k5log//k5ts4_log_newline 2006.257.20:52:37.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.20:52:37.48:setupk4=1 2006.257.20:52:37.48$setupk4/echo=on 2006.257.20:52:37.48$setupk4/pcalon 2006.257.20:52:37.48$pcalon/"no phase cal control is implemented here 2006.257.20:52:37.48$setupk4/"tpicd=stop 2006.257.20:52:37.48$setupk4/"rec=synch_on 2006.257.20:52:37.48$setupk4/"rec_mode=128 2006.257.20:52:37.48$setupk4/!* 2006.257.20:52:37.48$setupk4/recpk4 2006.257.20:52:37.48$recpk4/recpatch= 2006.257.20:52:37.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.20:52:37.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.20:52:37.48$setupk4/vck44 2006.257.20:52:37.48$vck44/valo=1,524.99 2006.257.20:52:37.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.20:52:37.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.20:52:37.48#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:37.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:37.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:37.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:37.48#ibcon#enter wrdev, iclass 12, count 0 2006.257.20:52:37.48#ibcon#first serial, iclass 12, count 0 2006.257.20:52:37.48#ibcon#enter sib2, iclass 12, count 0 2006.257.20:52:37.48#ibcon#flushed, iclass 12, count 0 2006.257.20:52:37.48#ibcon#about to write, iclass 12, count 0 2006.257.20:52:37.48#ibcon#wrote, iclass 12, count 0 2006.257.20:52:37.48#ibcon#about to read 3, iclass 12, count 0 2006.257.20:52:37.50#ibcon#read 3, iclass 12, count 0 2006.257.20:52:37.50#ibcon#about to read 4, iclass 12, count 0 2006.257.20:52:37.50#ibcon#read 4, iclass 12, count 0 2006.257.20:52:37.50#ibcon#about to read 5, iclass 12, count 0 2006.257.20:52:37.50#ibcon#read 5, iclass 12, count 0 2006.257.20:52:37.50#ibcon#about to read 6, iclass 12, count 0 2006.257.20:52:37.50#ibcon#read 6, iclass 12, count 0 2006.257.20:52:37.50#ibcon#end of sib2, iclass 12, count 0 2006.257.20:52:37.50#ibcon#*mode == 0, iclass 12, count 0 2006.257.20:52:37.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.20:52:37.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.20:52:37.50#ibcon#*before write, iclass 12, count 0 2006.257.20:52:37.50#ibcon#enter sib2, iclass 12, count 0 2006.257.20:52:37.50#ibcon#flushed, iclass 12, count 0 2006.257.20:52:37.50#ibcon#about to write, iclass 12, count 0 2006.257.20:52:37.50#ibcon#wrote, iclass 12, count 0 2006.257.20:52:37.50#ibcon#about to read 3, iclass 12, count 0 2006.257.20:52:37.55#ibcon#read 3, iclass 12, count 0 2006.257.20:52:37.55#ibcon#about to read 4, iclass 12, count 0 2006.257.20:52:37.55#ibcon#read 4, iclass 12, count 0 2006.257.20:52:37.55#ibcon#about to read 5, iclass 12, count 0 2006.257.20:52:37.55#ibcon#read 5, iclass 12, count 0 2006.257.20:52:37.55#ibcon#about to read 6, iclass 12, count 0 2006.257.20:52:37.55#ibcon#read 6, iclass 12, count 0 2006.257.20:52:37.55#ibcon#end of sib2, iclass 12, count 0 2006.257.20:52:37.55#ibcon#*after write, iclass 12, count 0 2006.257.20:52:37.55#ibcon#*before return 0, iclass 12, count 0 2006.257.20:52:37.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:37.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:37.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.20:52:37.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.20:52:37.55$vck44/va=1,8 2006.257.20:52:37.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.20:52:37.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.20:52:37.55#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:37.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:37.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:37.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:37.55#ibcon#enter wrdev, iclass 14, count 2 2006.257.20:52:37.55#ibcon#first serial, iclass 14, count 2 2006.257.20:52:37.55#ibcon#enter sib2, iclass 14, count 2 2006.257.20:52:37.55#ibcon#flushed, iclass 14, count 2 2006.257.20:52:37.55#ibcon#about to write, iclass 14, count 2 2006.257.20:52:37.55#ibcon#wrote, iclass 14, count 2 2006.257.20:52:37.55#ibcon#about to read 3, iclass 14, count 2 2006.257.20:52:37.57#ibcon#read 3, iclass 14, count 2 2006.257.20:52:37.57#ibcon#about to read 4, iclass 14, count 2 2006.257.20:52:37.57#ibcon#read 4, iclass 14, count 2 2006.257.20:52:37.57#ibcon#about to read 5, iclass 14, count 2 2006.257.20:52:37.57#ibcon#read 5, iclass 14, count 2 2006.257.20:52:37.57#ibcon#about to read 6, iclass 14, count 2 2006.257.20:52:37.57#ibcon#read 6, iclass 14, count 2 2006.257.20:52:37.57#ibcon#end of sib2, iclass 14, count 2 2006.257.20:52:37.57#ibcon#*mode == 0, iclass 14, count 2 2006.257.20:52:37.57#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.20:52:37.57#ibcon#[25=AT01-08\r\n] 2006.257.20:52:37.57#ibcon#*before write, iclass 14, count 2 2006.257.20:52:37.57#ibcon#enter sib2, iclass 14, count 2 2006.257.20:52:37.57#ibcon#flushed, iclass 14, count 2 2006.257.20:52:37.57#ibcon#about to write, iclass 14, count 2 2006.257.20:52:37.57#ibcon#wrote, iclass 14, count 2 2006.257.20:52:37.57#ibcon#about to read 3, iclass 14, count 2 2006.257.20:52:37.60#ibcon#read 3, iclass 14, count 2 2006.257.20:52:37.60#ibcon#about to read 4, iclass 14, count 2 2006.257.20:52:37.60#ibcon#read 4, iclass 14, count 2 2006.257.20:52:37.60#ibcon#about to read 5, iclass 14, count 2 2006.257.20:52:37.60#ibcon#read 5, iclass 14, count 2 2006.257.20:52:37.60#ibcon#about to read 6, iclass 14, count 2 2006.257.20:52:37.60#ibcon#read 6, iclass 14, count 2 2006.257.20:52:37.60#ibcon#end of sib2, iclass 14, count 2 2006.257.20:52:37.60#ibcon#*after write, iclass 14, count 2 2006.257.20:52:37.60#ibcon#*before return 0, iclass 14, count 2 2006.257.20:52:37.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:37.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:37.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.20:52:37.60#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:37.60#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:37.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:37.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:37.72#ibcon#enter wrdev, iclass 14, count 0 2006.257.20:52:37.72#ibcon#first serial, iclass 14, count 0 2006.257.20:52:37.72#ibcon#enter sib2, iclass 14, count 0 2006.257.20:52:37.72#ibcon#flushed, iclass 14, count 0 2006.257.20:52:37.72#ibcon#about to write, iclass 14, count 0 2006.257.20:52:37.72#ibcon#wrote, iclass 14, count 0 2006.257.20:52:37.72#ibcon#about to read 3, iclass 14, count 0 2006.257.20:52:37.74#ibcon#read 3, iclass 14, count 0 2006.257.20:52:37.74#ibcon#about to read 4, iclass 14, count 0 2006.257.20:52:37.74#ibcon#read 4, iclass 14, count 0 2006.257.20:52:37.74#ibcon#about to read 5, iclass 14, count 0 2006.257.20:52:37.74#ibcon#read 5, iclass 14, count 0 2006.257.20:52:37.74#ibcon#about to read 6, iclass 14, count 0 2006.257.20:52:37.74#ibcon#read 6, iclass 14, count 0 2006.257.20:52:37.74#ibcon#end of sib2, iclass 14, count 0 2006.257.20:52:37.74#ibcon#*mode == 0, iclass 14, count 0 2006.257.20:52:37.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.20:52:37.74#ibcon#[25=USB\r\n] 2006.257.20:52:37.74#ibcon#*before write, iclass 14, count 0 2006.257.20:52:37.74#ibcon#enter sib2, iclass 14, count 0 2006.257.20:52:37.74#ibcon#flushed, iclass 14, count 0 2006.257.20:52:37.74#ibcon#about to write, iclass 14, count 0 2006.257.20:52:37.74#ibcon#wrote, iclass 14, count 0 2006.257.20:52:37.74#ibcon#about to read 3, iclass 14, count 0 2006.257.20:52:37.77#ibcon#read 3, iclass 14, count 0 2006.257.20:52:37.77#ibcon#about to read 4, iclass 14, count 0 2006.257.20:52:37.77#ibcon#read 4, iclass 14, count 0 2006.257.20:52:37.77#ibcon#about to read 5, iclass 14, count 0 2006.257.20:52:37.77#ibcon#read 5, iclass 14, count 0 2006.257.20:52:37.77#ibcon#about to read 6, iclass 14, count 0 2006.257.20:52:37.77#ibcon#read 6, iclass 14, count 0 2006.257.20:52:37.77#ibcon#end of sib2, iclass 14, count 0 2006.257.20:52:37.77#ibcon#*after write, iclass 14, count 0 2006.257.20:52:37.77#ibcon#*before return 0, iclass 14, count 0 2006.257.20:52:37.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:37.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:37.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.20:52:37.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.20:52:37.77$vck44/valo=2,534.99 2006.257.20:52:37.77#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.20:52:37.77#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.20:52:37.77#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:37.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:37.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:37.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:37.77#ibcon#enter wrdev, iclass 16, count 0 2006.257.20:52:37.77#ibcon#first serial, iclass 16, count 0 2006.257.20:52:37.77#ibcon#enter sib2, iclass 16, count 0 2006.257.20:52:37.77#ibcon#flushed, iclass 16, count 0 2006.257.20:52:37.77#ibcon#about to write, iclass 16, count 0 2006.257.20:52:37.77#ibcon#wrote, iclass 16, count 0 2006.257.20:52:37.77#ibcon#about to read 3, iclass 16, count 0 2006.257.20:52:37.79#ibcon#read 3, iclass 16, count 0 2006.257.20:52:37.79#ibcon#about to read 4, iclass 16, count 0 2006.257.20:52:37.79#ibcon#read 4, iclass 16, count 0 2006.257.20:52:37.79#ibcon#about to read 5, iclass 16, count 0 2006.257.20:52:37.79#ibcon#read 5, iclass 16, count 0 2006.257.20:52:37.79#ibcon#about to read 6, iclass 16, count 0 2006.257.20:52:37.79#ibcon#read 6, iclass 16, count 0 2006.257.20:52:37.79#ibcon#end of sib2, iclass 16, count 0 2006.257.20:52:37.79#ibcon#*mode == 0, iclass 16, count 0 2006.257.20:52:37.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.20:52:37.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.20:52:37.79#ibcon#*before write, iclass 16, count 0 2006.257.20:52:37.79#ibcon#enter sib2, iclass 16, count 0 2006.257.20:52:37.79#ibcon#flushed, iclass 16, count 0 2006.257.20:52:37.79#ibcon#about to write, iclass 16, count 0 2006.257.20:52:37.79#ibcon#wrote, iclass 16, count 0 2006.257.20:52:37.79#ibcon#about to read 3, iclass 16, count 0 2006.257.20:52:37.83#ibcon#read 3, iclass 16, count 0 2006.257.20:52:37.83#ibcon#about to read 4, iclass 16, count 0 2006.257.20:52:37.83#ibcon#read 4, iclass 16, count 0 2006.257.20:52:37.83#ibcon#about to read 5, iclass 16, count 0 2006.257.20:52:37.83#ibcon#read 5, iclass 16, count 0 2006.257.20:52:37.83#ibcon#about to read 6, iclass 16, count 0 2006.257.20:52:37.83#ibcon#read 6, iclass 16, count 0 2006.257.20:52:37.83#ibcon#end of sib2, iclass 16, count 0 2006.257.20:52:37.83#ibcon#*after write, iclass 16, count 0 2006.257.20:52:37.83#ibcon#*before return 0, iclass 16, count 0 2006.257.20:52:37.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:37.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:37.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.20:52:37.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.20:52:37.83$vck44/va=2,7 2006.257.20:52:37.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.20:52:37.83#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.20:52:37.83#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:37.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:37.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:37.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:37.89#ibcon#enter wrdev, iclass 18, count 2 2006.257.20:52:37.89#ibcon#first serial, iclass 18, count 2 2006.257.20:52:37.89#ibcon#enter sib2, iclass 18, count 2 2006.257.20:52:37.89#ibcon#flushed, iclass 18, count 2 2006.257.20:52:37.89#ibcon#about to write, iclass 18, count 2 2006.257.20:52:37.89#ibcon#wrote, iclass 18, count 2 2006.257.20:52:37.89#ibcon#about to read 3, iclass 18, count 2 2006.257.20:52:37.91#ibcon#read 3, iclass 18, count 2 2006.257.20:52:37.91#ibcon#about to read 4, iclass 18, count 2 2006.257.20:52:37.91#ibcon#read 4, iclass 18, count 2 2006.257.20:52:37.91#ibcon#about to read 5, iclass 18, count 2 2006.257.20:52:37.91#ibcon#read 5, iclass 18, count 2 2006.257.20:52:37.91#ibcon#about to read 6, iclass 18, count 2 2006.257.20:52:37.91#ibcon#read 6, iclass 18, count 2 2006.257.20:52:37.91#ibcon#end of sib2, iclass 18, count 2 2006.257.20:52:37.91#ibcon#*mode == 0, iclass 18, count 2 2006.257.20:52:37.91#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.20:52:37.91#ibcon#[25=AT02-07\r\n] 2006.257.20:52:37.91#ibcon#*before write, iclass 18, count 2 2006.257.20:52:37.91#ibcon#enter sib2, iclass 18, count 2 2006.257.20:52:37.91#ibcon#flushed, iclass 18, count 2 2006.257.20:52:37.91#ibcon#about to write, iclass 18, count 2 2006.257.20:52:37.91#ibcon#wrote, iclass 18, count 2 2006.257.20:52:37.91#ibcon#about to read 3, iclass 18, count 2 2006.257.20:52:37.94#ibcon#read 3, iclass 18, count 2 2006.257.20:52:37.94#ibcon#about to read 4, iclass 18, count 2 2006.257.20:52:37.94#ibcon#read 4, iclass 18, count 2 2006.257.20:52:37.94#ibcon#about to read 5, iclass 18, count 2 2006.257.20:52:37.94#ibcon#read 5, iclass 18, count 2 2006.257.20:52:37.94#ibcon#about to read 6, iclass 18, count 2 2006.257.20:52:37.94#ibcon#read 6, iclass 18, count 2 2006.257.20:52:37.94#ibcon#end of sib2, iclass 18, count 2 2006.257.20:52:37.94#ibcon#*after write, iclass 18, count 2 2006.257.20:52:37.94#ibcon#*before return 0, iclass 18, count 2 2006.257.20:52:37.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:37.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:37.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.20:52:37.94#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:37.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:38.06#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:38.06#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:38.06#ibcon#enter wrdev, iclass 18, count 0 2006.257.20:52:38.06#ibcon#first serial, iclass 18, count 0 2006.257.20:52:38.06#ibcon#enter sib2, iclass 18, count 0 2006.257.20:52:38.06#ibcon#flushed, iclass 18, count 0 2006.257.20:52:38.06#ibcon#about to write, iclass 18, count 0 2006.257.20:52:38.06#ibcon#wrote, iclass 18, count 0 2006.257.20:52:38.06#ibcon#about to read 3, iclass 18, count 0 2006.257.20:52:38.08#ibcon#read 3, iclass 18, count 0 2006.257.20:52:38.08#ibcon#about to read 4, iclass 18, count 0 2006.257.20:52:38.08#ibcon#read 4, iclass 18, count 0 2006.257.20:52:38.08#ibcon#about to read 5, iclass 18, count 0 2006.257.20:52:38.08#ibcon#read 5, iclass 18, count 0 2006.257.20:52:38.08#ibcon#about to read 6, iclass 18, count 0 2006.257.20:52:38.08#ibcon#read 6, iclass 18, count 0 2006.257.20:52:38.08#ibcon#end of sib2, iclass 18, count 0 2006.257.20:52:38.08#ibcon#*mode == 0, iclass 18, count 0 2006.257.20:52:38.08#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.20:52:38.08#ibcon#[25=USB\r\n] 2006.257.20:52:38.08#ibcon#*before write, iclass 18, count 0 2006.257.20:52:38.08#ibcon#enter sib2, iclass 18, count 0 2006.257.20:52:38.08#ibcon#flushed, iclass 18, count 0 2006.257.20:52:38.08#ibcon#about to write, iclass 18, count 0 2006.257.20:52:38.08#ibcon#wrote, iclass 18, count 0 2006.257.20:52:38.08#ibcon#about to read 3, iclass 18, count 0 2006.257.20:52:38.11#ibcon#read 3, iclass 18, count 0 2006.257.20:52:38.11#ibcon#about to read 4, iclass 18, count 0 2006.257.20:52:38.11#ibcon#read 4, iclass 18, count 0 2006.257.20:52:38.11#ibcon#about to read 5, iclass 18, count 0 2006.257.20:52:38.11#ibcon#read 5, iclass 18, count 0 2006.257.20:52:38.11#ibcon#about to read 6, iclass 18, count 0 2006.257.20:52:38.11#ibcon#read 6, iclass 18, count 0 2006.257.20:52:38.11#ibcon#end of sib2, iclass 18, count 0 2006.257.20:52:38.11#ibcon#*after write, iclass 18, count 0 2006.257.20:52:38.11#ibcon#*before return 0, iclass 18, count 0 2006.257.20:52:38.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:38.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:38.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.20:52:38.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.20:52:38.11$vck44/valo=3,564.99 2006.257.20:52:38.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.20:52:38.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.20:52:38.11#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:38.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:38.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:38.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:38.11#ibcon#enter wrdev, iclass 20, count 0 2006.257.20:52:38.11#ibcon#first serial, iclass 20, count 0 2006.257.20:52:38.11#ibcon#enter sib2, iclass 20, count 0 2006.257.20:52:38.11#ibcon#flushed, iclass 20, count 0 2006.257.20:52:38.11#ibcon#about to write, iclass 20, count 0 2006.257.20:52:38.11#ibcon#wrote, iclass 20, count 0 2006.257.20:52:38.11#ibcon#about to read 3, iclass 20, count 0 2006.257.20:52:38.13#ibcon#read 3, iclass 20, count 0 2006.257.20:52:38.13#ibcon#about to read 4, iclass 20, count 0 2006.257.20:52:38.13#ibcon#read 4, iclass 20, count 0 2006.257.20:52:38.13#ibcon#about to read 5, iclass 20, count 0 2006.257.20:52:38.13#ibcon#read 5, iclass 20, count 0 2006.257.20:52:38.13#ibcon#about to read 6, iclass 20, count 0 2006.257.20:52:38.13#ibcon#read 6, iclass 20, count 0 2006.257.20:52:38.13#ibcon#end of sib2, iclass 20, count 0 2006.257.20:52:38.13#ibcon#*mode == 0, iclass 20, count 0 2006.257.20:52:38.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.20:52:38.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.20:52:38.13#ibcon#*before write, iclass 20, count 0 2006.257.20:52:38.13#ibcon#enter sib2, iclass 20, count 0 2006.257.20:52:38.13#ibcon#flushed, iclass 20, count 0 2006.257.20:52:38.13#ibcon#about to write, iclass 20, count 0 2006.257.20:52:38.13#ibcon#wrote, iclass 20, count 0 2006.257.20:52:38.13#ibcon#about to read 3, iclass 20, count 0 2006.257.20:52:38.17#ibcon#read 3, iclass 20, count 0 2006.257.20:52:38.17#ibcon#about to read 4, iclass 20, count 0 2006.257.20:52:38.17#ibcon#read 4, iclass 20, count 0 2006.257.20:52:38.17#ibcon#about to read 5, iclass 20, count 0 2006.257.20:52:38.17#ibcon#read 5, iclass 20, count 0 2006.257.20:52:38.17#ibcon#about to read 6, iclass 20, count 0 2006.257.20:52:38.17#ibcon#read 6, iclass 20, count 0 2006.257.20:52:38.17#ibcon#end of sib2, iclass 20, count 0 2006.257.20:52:38.17#ibcon#*after write, iclass 20, count 0 2006.257.20:52:38.17#ibcon#*before return 0, iclass 20, count 0 2006.257.20:52:38.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:38.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:38.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.20:52:38.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.20:52:38.17$vck44/va=3,8 2006.257.20:52:38.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.20:52:38.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.20:52:38.17#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:38.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:38.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:38.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:38.23#ibcon#enter wrdev, iclass 22, count 2 2006.257.20:52:38.23#ibcon#first serial, iclass 22, count 2 2006.257.20:52:38.23#ibcon#enter sib2, iclass 22, count 2 2006.257.20:52:38.23#ibcon#flushed, iclass 22, count 2 2006.257.20:52:38.23#ibcon#about to write, iclass 22, count 2 2006.257.20:52:38.23#ibcon#wrote, iclass 22, count 2 2006.257.20:52:38.23#ibcon#about to read 3, iclass 22, count 2 2006.257.20:52:38.25#ibcon#read 3, iclass 22, count 2 2006.257.20:52:38.25#ibcon#about to read 4, iclass 22, count 2 2006.257.20:52:38.25#ibcon#read 4, iclass 22, count 2 2006.257.20:52:38.25#ibcon#about to read 5, iclass 22, count 2 2006.257.20:52:38.25#ibcon#read 5, iclass 22, count 2 2006.257.20:52:38.25#ibcon#about to read 6, iclass 22, count 2 2006.257.20:52:38.25#ibcon#read 6, iclass 22, count 2 2006.257.20:52:38.25#ibcon#end of sib2, iclass 22, count 2 2006.257.20:52:38.25#ibcon#*mode == 0, iclass 22, count 2 2006.257.20:52:38.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.20:52:38.25#ibcon#[25=AT03-08\r\n] 2006.257.20:52:38.25#ibcon#*before write, iclass 22, count 2 2006.257.20:52:38.25#ibcon#enter sib2, iclass 22, count 2 2006.257.20:52:38.25#ibcon#flushed, iclass 22, count 2 2006.257.20:52:38.25#ibcon#about to write, iclass 22, count 2 2006.257.20:52:38.25#ibcon#wrote, iclass 22, count 2 2006.257.20:52:38.25#ibcon#about to read 3, iclass 22, count 2 2006.257.20:52:38.28#ibcon#read 3, iclass 22, count 2 2006.257.20:52:38.28#ibcon#about to read 4, iclass 22, count 2 2006.257.20:52:38.28#ibcon#read 4, iclass 22, count 2 2006.257.20:52:38.28#ibcon#about to read 5, iclass 22, count 2 2006.257.20:52:38.28#ibcon#read 5, iclass 22, count 2 2006.257.20:52:38.28#ibcon#about to read 6, iclass 22, count 2 2006.257.20:52:38.28#ibcon#read 6, iclass 22, count 2 2006.257.20:52:38.28#ibcon#end of sib2, iclass 22, count 2 2006.257.20:52:38.28#ibcon#*after write, iclass 22, count 2 2006.257.20:52:38.28#ibcon#*before return 0, iclass 22, count 2 2006.257.20:52:38.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:38.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:38.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.20:52:38.28#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:38.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:38.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:38.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:38.40#ibcon#enter wrdev, iclass 22, count 0 2006.257.20:52:38.40#ibcon#first serial, iclass 22, count 0 2006.257.20:52:38.40#ibcon#enter sib2, iclass 22, count 0 2006.257.20:52:38.40#ibcon#flushed, iclass 22, count 0 2006.257.20:52:38.40#ibcon#about to write, iclass 22, count 0 2006.257.20:52:38.40#ibcon#wrote, iclass 22, count 0 2006.257.20:52:38.40#ibcon#about to read 3, iclass 22, count 0 2006.257.20:52:38.42#ibcon#read 3, iclass 22, count 0 2006.257.20:52:38.42#ibcon#about to read 4, iclass 22, count 0 2006.257.20:52:38.42#ibcon#read 4, iclass 22, count 0 2006.257.20:52:38.42#ibcon#about to read 5, iclass 22, count 0 2006.257.20:52:38.42#ibcon#read 5, iclass 22, count 0 2006.257.20:52:38.42#ibcon#about to read 6, iclass 22, count 0 2006.257.20:52:38.42#ibcon#read 6, iclass 22, count 0 2006.257.20:52:38.42#ibcon#end of sib2, iclass 22, count 0 2006.257.20:52:38.42#ibcon#*mode == 0, iclass 22, count 0 2006.257.20:52:38.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.20:52:38.42#ibcon#[25=USB\r\n] 2006.257.20:52:38.42#ibcon#*before write, iclass 22, count 0 2006.257.20:52:38.42#ibcon#enter sib2, iclass 22, count 0 2006.257.20:52:38.42#ibcon#flushed, iclass 22, count 0 2006.257.20:52:38.42#ibcon#about to write, iclass 22, count 0 2006.257.20:52:38.42#ibcon#wrote, iclass 22, count 0 2006.257.20:52:38.42#ibcon#about to read 3, iclass 22, count 0 2006.257.20:52:38.45#ibcon#read 3, iclass 22, count 0 2006.257.20:52:38.45#ibcon#about to read 4, iclass 22, count 0 2006.257.20:52:38.45#ibcon#read 4, iclass 22, count 0 2006.257.20:52:38.45#ibcon#about to read 5, iclass 22, count 0 2006.257.20:52:38.45#ibcon#read 5, iclass 22, count 0 2006.257.20:52:38.45#ibcon#about to read 6, iclass 22, count 0 2006.257.20:52:38.45#ibcon#read 6, iclass 22, count 0 2006.257.20:52:38.45#ibcon#end of sib2, iclass 22, count 0 2006.257.20:52:38.45#ibcon#*after write, iclass 22, count 0 2006.257.20:52:38.45#ibcon#*before return 0, iclass 22, count 0 2006.257.20:52:38.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:38.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:38.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.20:52:38.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.20:52:38.45$vck44/valo=4,624.99 2006.257.20:52:38.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.20:52:38.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.20:52:38.45#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:38.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:38.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:38.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:38.45#ibcon#enter wrdev, iclass 24, count 0 2006.257.20:52:38.45#ibcon#first serial, iclass 24, count 0 2006.257.20:52:38.45#ibcon#enter sib2, iclass 24, count 0 2006.257.20:52:38.45#ibcon#flushed, iclass 24, count 0 2006.257.20:52:38.45#ibcon#about to write, iclass 24, count 0 2006.257.20:52:38.45#ibcon#wrote, iclass 24, count 0 2006.257.20:52:38.45#ibcon#about to read 3, iclass 24, count 0 2006.257.20:52:38.47#ibcon#read 3, iclass 24, count 0 2006.257.20:52:38.47#ibcon#about to read 4, iclass 24, count 0 2006.257.20:52:38.47#ibcon#read 4, iclass 24, count 0 2006.257.20:52:38.47#ibcon#about to read 5, iclass 24, count 0 2006.257.20:52:38.47#ibcon#read 5, iclass 24, count 0 2006.257.20:52:38.47#ibcon#about to read 6, iclass 24, count 0 2006.257.20:52:38.47#ibcon#read 6, iclass 24, count 0 2006.257.20:52:38.47#ibcon#end of sib2, iclass 24, count 0 2006.257.20:52:38.47#ibcon#*mode == 0, iclass 24, count 0 2006.257.20:52:38.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.20:52:38.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.20:52:38.47#ibcon#*before write, iclass 24, count 0 2006.257.20:52:38.47#ibcon#enter sib2, iclass 24, count 0 2006.257.20:52:38.47#ibcon#flushed, iclass 24, count 0 2006.257.20:52:38.47#ibcon#about to write, iclass 24, count 0 2006.257.20:52:38.47#ibcon#wrote, iclass 24, count 0 2006.257.20:52:38.47#ibcon#about to read 3, iclass 24, count 0 2006.257.20:52:38.51#ibcon#read 3, iclass 24, count 0 2006.257.20:52:38.51#ibcon#about to read 4, iclass 24, count 0 2006.257.20:52:38.51#ibcon#read 4, iclass 24, count 0 2006.257.20:52:38.51#ibcon#about to read 5, iclass 24, count 0 2006.257.20:52:38.51#ibcon#read 5, iclass 24, count 0 2006.257.20:52:38.51#ibcon#about to read 6, iclass 24, count 0 2006.257.20:52:38.51#ibcon#read 6, iclass 24, count 0 2006.257.20:52:38.51#ibcon#end of sib2, iclass 24, count 0 2006.257.20:52:38.51#ibcon#*after write, iclass 24, count 0 2006.257.20:52:38.51#ibcon#*before return 0, iclass 24, count 0 2006.257.20:52:38.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:38.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:38.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.20:52:38.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.20:52:38.51$vck44/va=4,7 2006.257.20:52:38.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.20:52:38.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.20:52:38.51#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:38.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:38.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:38.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:38.57#ibcon#enter wrdev, iclass 26, count 2 2006.257.20:52:38.57#ibcon#first serial, iclass 26, count 2 2006.257.20:52:38.57#ibcon#enter sib2, iclass 26, count 2 2006.257.20:52:38.57#ibcon#flushed, iclass 26, count 2 2006.257.20:52:38.57#ibcon#about to write, iclass 26, count 2 2006.257.20:52:38.57#ibcon#wrote, iclass 26, count 2 2006.257.20:52:38.57#ibcon#about to read 3, iclass 26, count 2 2006.257.20:52:38.59#ibcon#read 3, iclass 26, count 2 2006.257.20:52:38.59#ibcon#about to read 4, iclass 26, count 2 2006.257.20:52:38.59#ibcon#read 4, iclass 26, count 2 2006.257.20:52:38.59#ibcon#about to read 5, iclass 26, count 2 2006.257.20:52:38.59#ibcon#read 5, iclass 26, count 2 2006.257.20:52:38.59#ibcon#about to read 6, iclass 26, count 2 2006.257.20:52:38.59#ibcon#read 6, iclass 26, count 2 2006.257.20:52:38.59#ibcon#end of sib2, iclass 26, count 2 2006.257.20:52:38.59#ibcon#*mode == 0, iclass 26, count 2 2006.257.20:52:38.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.20:52:38.59#ibcon#[25=AT04-07\r\n] 2006.257.20:52:38.59#ibcon#*before write, iclass 26, count 2 2006.257.20:52:38.59#ibcon#enter sib2, iclass 26, count 2 2006.257.20:52:38.59#ibcon#flushed, iclass 26, count 2 2006.257.20:52:38.59#ibcon#about to write, iclass 26, count 2 2006.257.20:52:38.59#ibcon#wrote, iclass 26, count 2 2006.257.20:52:38.59#ibcon#about to read 3, iclass 26, count 2 2006.257.20:52:38.62#ibcon#read 3, iclass 26, count 2 2006.257.20:52:38.62#ibcon#about to read 4, iclass 26, count 2 2006.257.20:52:38.62#ibcon#read 4, iclass 26, count 2 2006.257.20:52:38.62#ibcon#about to read 5, iclass 26, count 2 2006.257.20:52:38.62#ibcon#read 5, iclass 26, count 2 2006.257.20:52:38.62#ibcon#about to read 6, iclass 26, count 2 2006.257.20:52:38.62#ibcon#read 6, iclass 26, count 2 2006.257.20:52:38.62#ibcon#end of sib2, iclass 26, count 2 2006.257.20:52:38.62#ibcon#*after write, iclass 26, count 2 2006.257.20:52:38.62#ibcon#*before return 0, iclass 26, count 2 2006.257.20:52:38.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:38.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:38.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.20:52:38.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:38.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:38.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:38.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:38.74#ibcon#enter wrdev, iclass 26, count 0 2006.257.20:52:38.74#ibcon#first serial, iclass 26, count 0 2006.257.20:52:38.74#ibcon#enter sib2, iclass 26, count 0 2006.257.20:52:38.74#ibcon#flushed, iclass 26, count 0 2006.257.20:52:38.74#ibcon#about to write, iclass 26, count 0 2006.257.20:52:38.74#ibcon#wrote, iclass 26, count 0 2006.257.20:52:38.74#ibcon#about to read 3, iclass 26, count 0 2006.257.20:52:38.76#ibcon#read 3, iclass 26, count 0 2006.257.20:52:38.76#ibcon#about to read 4, iclass 26, count 0 2006.257.20:52:38.76#ibcon#read 4, iclass 26, count 0 2006.257.20:52:38.76#ibcon#about to read 5, iclass 26, count 0 2006.257.20:52:38.76#ibcon#read 5, iclass 26, count 0 2006.257.20:52:38.76#ibcon#about to read 6, iclass 26, count 0 2006.257.20:52:38.76#ibcon#read 6, iclass 26, count 0 2006.257.20:52:38.76#ibcon#end of sib2, iclass 26, count 0 2006.257.20:52:38.76#ibcon#*mode == 0, iclass 26, count 0 2006.257.20:52:38.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.20:52:38.76#ibcon#[25=USB\r\n] 2006.257.20:52:38.76#ibcon#*before write, iclass 26, count 0 2006.257.20:52:38.76#ibcon#enter sib2, iclass 26, count 0 2006.257.20:52:38.76#ibcon#flushed, iclass 26, count 0 2006.257.20:52:38.76#ibcon#about to write, iclass 26, count 0 2006.257.20:52:38.76#ibcon#wrote, iclass 26, count 0 2006.257.20:52:38.76#ibcon#about to read 3, iclass 26, count 0 2006.257.20:52:38.79#ibcon#read 3, iclass 26, count 0 2006.257.20:52:38.79#ibcon#about to read 4, iclass 26, count 0 2006.257.20:52:38.79#ibcon#read 4, iclass 26, count 0 2006.257.20:52:38.79#ibcon#about to read 5, iclass 26, count 0 2006.257.20:52:38.79#ibcon#read 5, iclass 26, count 0 2006.257.20:52:38.79#ibcon#about to read 6, iclass 26, count 0 2006.257.20:52:38.79#ibcon#read 6, iclass 26, count 0 2006.257.20:52:38.79#ibcon#end of sib2, iclass 26, count 0 2006.257.20:52:38.79#ibcon#*after write, iclass 26, count 0 2006.257.20:52:38.79#ibcon#*before return 0, iclass 26, count 0 2006.257.20:52:38.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:38.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:38.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.20:52:38.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.20:52:38.79$vck44/valo=5,734.99 2006.257.20:52:38.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.20:52:38.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.20:52:38.79#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:38.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:38.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:38.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:38.79#ibcon#enter wrdev, iclass 28, count 0 2006.257.20:52:38.79#ibcon#first serial, iclass 28, count 0 2006.257.20:52:38.79#ibcon#enter sib2, iclass 28, count 0 2006.257.20:52:38.79#ibcon#flushed, iclass 28, count 0 2006.257.20:52:38.79#ibcon#about to write, iclass 28, count 0 2006.257.20:52:38.79#ibcon#wrote, iclass 28, count 0 2006.257.20:52:38.79#ibcon#about to read 3, iclass 28, count 0 2006.257.20:52:38.81#ibcon#read 3, iclass 28, count 0 2006.257.20:52:38.81#ibcon#about to read 4, iclass 28, count 0 2006.257.20:52:38.81#ibcon#read 4, iclass 28, count 0 2006.257.20:52:38.81#ibcon#about to read 5, iclass 28, count 0 2006.257.20:52:38.81#ibcon#read 5, iclass 28, count 0 2006.257.20:52:38.81#ibcon#about to read 6, iclass 28, count 0 2006.257.20:52:38.81#ibcon#read 6, iclass 28, count 0 2006.257.20:52:38.81#ibcon#end of sib2, iclass 28, count 0 2006.257.20:52:38.81#ibcon#*mode == 0, iclass 28, count 0 2006.257.20:52:38.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.20:52:38.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.20:52:38.81#ibcon#*before write, iclass 28, count 0 2006.257.20:52:38.81#ibcon#enter sib2, iclass 28, count 0 2006.257.20:52:38.81#ibcon#flushed, iclass 28, count 0 2006.257.20:52:38.81#ibcon#about to write, iclass 28, count 0 2006.257.20:52:38.81#ibcon#wrote, iclass 28, count 0 2006.257.20:52:38.81#ibcon#about to read 3, iclass 28, count 0 2006.257.20:52:38.85#ibcon#read 3, iclass 28, count 0 2006.257.20:52:38.85#ibcon#about to read 4, iclass 28, count 0 2006.257.20:52:38.85#ibcon#read 4, iclass 28, count 0 2006.257.20:52:38.85#ibcon#about to read 5, iclass 28, count 0 2006.257.20:52:38.85#ibcon#read 5, iclass 28, count 0 2006.257.20:52:38.85#ibcon#about to read 6, iclass 28, count 0 2006.257.20:52:38.85#ibcon#read 6, iclass 28, count 0 2006.257.20:52:38.85#ibcon#end of sib2, iclass 28, count 0 2006.257.20:52:38.85#ibcon#*after write, iclass 28, count 0 2006.257.20:52:38.85#ibcon#*before return 0, iclass 28, count 0 2006.257.20:52:38.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:38.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:38.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.20:52:38.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.20:52:38.85$vck44/va=5,4 2006.257.20:52:38.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.20:52:38.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.20:52:38.85#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:38.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:38.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:38.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:38.91#ibcon#enter wrdev, iclass 30, count 2 2006.257.20:52:38.91#ibcon#first serial, iclass 30, count 2 2006.257.20:52:38.91#ibcon#enter sib2, iclass 30, count 2 2006.257.20:52:38.91#ibcon#flushed, iclass 30, count 2 2006.257.20:52:38.91#ibcon#about to write, iclass 30, count 2 2006.257.20:52:38.91#ibcon#wrote, iclass 30, count 2 2006.257.20:52:38.91#ibcon#about to read 3, iclass 30, count 2 2006.257.20:52:38.93#ibcon#read 3, iclass 30, count 2 2006.257.20:52:38.93#ibcon#about to read 4, iclass 30, count 2 2006.257.20:52:38.93#ibcon#read 4, iclass 30, count 2 2006.257.20:52:38.93#ibcon#about to read 5, iclass 30, count 2 2006.257.20:52:38.93#ibcon#read 5, iclass 30, count 2 2006.257.20:52:38.93#ibcon#about to read 6, iclass 30, count 2 2006.257.20:52:38.93#ibcon#read 6, iclass 30, count 2 2006.257.20:52:38.93#ibcon#end of sib2, iclass 30, count 2 2006.257.20:52:38.93#ibcon#*mode == 0, iclass 30, count 2 2006.257.20:52:38.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.20:52:38.93#ibcon#[25=AT05-04\r\n] 2006.257.20:52:38.93#ibcon#*before write, iclass 30, count 2 2006.257.20:52:38.93#ibcon#enter sib2, iclass 30, count 2 2006.257.20:52:38.93#ibcon#flushed, iclass 30, count 2 2006.257.20:52:38.93#ibcon#about to write, iclass 30, count 2 2006.257.20:52:38.93#ibcon#wrote, iclass 30, count 2 2006.257.20:52:38.93#ibcon#about to read 3, iclass 30, count 2 2006.257.20:52:38.96#ibcon#read 3, iclass 30, count 2 2006.257.20:52:38.96#ibcon#about to read 4, iclass 30, count 2 2006.257.20:52:38.96#ibcon#read 4, iclass 30, count 2 2006.257.20:52:38.96#ibcon#about to read 5, iclass 30, count 2 2006.257.20:52:38.96#ibcon#read 5, iclass 30, count 2 2006.257.20:52:38.96#ibcon#about to read 6, iclass 30, count 2 2006.257.20:52:38.96#ibcon#read 6, iclass 30, count 2 2006.257.20:52:38.96#ibcon#end of sib2, iclass 30, count 2 2006.257.20:52:38.96#ibcon#*after write, iclass 30, count 2 2006.257.20:52:38.96#ibcon#*before return 0, iclass 30, count 2 2006.257.20:52:38.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:38.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:38.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.20:52:38.96#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:38.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:39.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:39.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:39.08#ibcon#enter wrdev, iclass 30, count 0 2006.257.20:52:39.08#ibcon#first serial, iclass 30, count 0 2006.257.20:52:39.08#ibcon#enter sib2, iclass 30, count 0 2006.257.20:52:39.08#ibcon#flushed, iclass 30, count 0 2006.257.20:52:39.08#ibcon#about to write, iclass 30, count 0 2006.257.20:52:39.08#ibcon#wrote, iclass 30, count 0 2006.257.20:52:39.08#ibcon#about to read 3, iclass 30, count 0 2006.257.20:52:39.10#ibcon#read 3, iclass 30, count 0 2006.257.20:52:39.10#ibcon#about to read 4, iclass 30, count 0 2006.257.20:52:39.10#ibcon#read 4, iclass 30, count 0 2006.257.20:52:39.10#ibcon#about to read 5, iclass 30, count 0 2006.257.20:52:39.10#ibcon#read 5, iclass 30, count 0 2006.257.20:52:39.10#ibcon#about to read 6, iclass 30, count 0 2006.257.20:52:39.10#ibcon#read 6, iclass 30, count 0 2006.257.20:52:39.10#ibcon#end of sib2, iclass 30, count 0 2006.257.20:52:39.10#ibcon#*mode == 0, iclass 30, count 0 2006.257.20:52:39.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.20:52:39.10#ibcon#[25=USB\r\n] 2006.257.20:52:39.10#ibcon#*before write, iclass 30, count 0 2006.257.20:52:39.10#ibcon#enter sib2, iclass 30, count 0 2006.257.20:52:39.10#ibcon#flushed, iclass 30, count 0 2006.257.20:52:39.10#ibcon#about to write, iclass 30, count 0 2006.257.20:52:39.10#ibcon#wrote, iclass 30, count 0 2006.257.20:52:39.10#ibcon#about to read 3, iclass 30, count 0 2006.257.20:52:39.13#ibcon#read 3, iclass 30, count 0 2006.257.20:52:39.13#ibcon#about to read 4, iclass 30, count 0 2006.257.20:52:39.13#ibcon#read 4, iclass 30, count 0 2006.257.20:52:39.13#ibcon#about to read 5, iclass 30, count 0 2006.257.20:52:39.13#ibcon#read 5, iclass 30, count 0 2006.257.20:52:39.13#ibcon#about to read 6, iclass 30, count 0 2006.257.20:52:39.13#ibcon#read 6, iclass 30, count 0 2006.257.20:52:39.13#ibcon#end of sib2, iclass 30, count 0 2006.257.20:52:39.13#ibcon#*after write, iclass 30, count 0 2006.257.20:52:39.13#ibcon#*before return 0, iclass 30, count 0 2006.257.20:52:39.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:39.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:39.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.20:52:39.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.20:52:39.13$vck44/valo=6,814.99 2006.257.20:52:39.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.20:52:39.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.20:52:39.13#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:39.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:39.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:39.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:39.13#ibcon#enter wrdev, iclass 32, count 0 2006.257.20:52:39.13#ibcon#first serial, iclass 32, count 0 2006.257.20:52:39.13#ibcon#enter sib2, iclass 32, count 0 2006.257.20:52:39.13#ibcon#flushed, iclass 32, count 0 2006.257.20:52:39.13#ibcon#about to write, iclass 32, count 0 2006.257.20:52:39.13#ibcon#wrote, iclass 32, count 0 2006.257.20:52:39.13#ibcon#about to read 3, iclass 32, count 0 2006.257.20:52:39.15#ibcon#read 3, iclass 32, count 0 2006.257.20:52:39.15#ibcon#about to read 4, iclass 32, count 0 2006.257.20:52:39.15#ibcon#read 4, iclass 32, count 0 2006.257.20:52:39.15#ibcon#about to read 5, iclass 32, count 0 2006.257.20:52:39.15#ibcon#read 5, iclass 32, count 0 2006.257.20:52:39.15#ibcon#about to read 6, iclass 32, count 0 2006.257.20:52:39.15#ibcon#read 6, iclass 32, count 0 2006.257.20:52:39.15#ibcon#end of sib2, iclass 32, count 0 2006.257.20:52:39.15#ibcon#*mode == 0, iclass 32, count 0 2006.257.20:52:39.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.20:52:39.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.20:52:39.15#ibcon#*before write, iclass 32, count 0 2006.257.20:52:39.15#ibcon#enter sib2, iclass 32, count 0 2006.257.20:52:39.15#ibcon#flushed, iclass 32, count 0 2006.257.20:52:39.15#ibcon#about to write, iclass 32, count 0 2006.257.20:52:39.15#ibcon#wrote, iclass 32, count 0 2006.257.20:52:39.15#ibcon#about to read 3, iclass 32, count 0 2006.257.20:52:39.19#ibcon#read 3, iclass 32, count 0 2006.257.20:52:39.19#ibcon#about to read 4, iclass 32, count 0 2006.257.20:52:39.19#ibcon#read 4, iclass 32, count 0 2006.257.20:52:39.19#ibcon#about to read 5, iclass 32, count 0 2006.257.20:52:39.19#ibcon#read 5, iclass 32, count 0 2006.257.20:52:39.19#ibcon#about to read 6, iclass 32, count 0 2006.257.20:52:39.19#ibcon#read 6, iclass 32, count 0 2006.257.20:52:39.19#ibcon#end of sib2, iclass 32, count 0 2006.257.20:52:39.19#ibcon#*after write, iclass 32, count 0 2006.257.20:52:39.19#ibcon#*before return 0, iclass 32, count 0 2006.257.20:52:39.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:39.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:39.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.20:52:39.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.20:52:39.19$vck44/va=6,4 2006.257.20:52:39.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.20:52:39.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.20:52:39.19#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:39.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:39.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:39.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:39.25#ibcon#enter wrdev, iclass 34, count 2 2006.257.20:52:39.25#ibcon#first serial, iclass 34, count 2 2006.257.20:52:39.25#ibcon#enter sib2, iclass 34, count 2 2006.257.20:52:39.25#ibcon#flushed, iclass 34, count 2 2006.257.20:52:39.25#ibcon#about to write, iclass 34, count 2 2006.257.20:52:39.25#ibcon#wrote, iclass 34, count 2 2006.257.20:52:39.25#ibcon#about to read 3, iclass 34, count 2 2006.257.20:52:39.27#ibcon#read 3, iclass 34, count 2 2006.257.20:52:39.27#ibcon#about to read 4, iclass 34, count 2 2006.257.20:52:39.27#ibcon#read 4, iclass 34, count 2 2006.257.20:52:39.27#ibcon#about to read 5, iclass 34, count 2 2006.257.20:52:39.27#ibcon#read 5, iclass 34, count 2 2006.257.20:52:39.27#ibcon#about to read 6, iclass 34, count 2 2006.257.20:52:39.27#ibcon#read 6, iclass 34, count 2 2006.257.20:52:39.27#ibcon#end of sib2, iclass 34, count 2 2006.257.20:52:39.27#ibcon#*mode == 0, iclass 34, count 2 2006.257.20:52:39.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.20:52:39.27#ibcon#[25=AT06-04\r\n] 2006.257.20:52:39.27#ibcon#*before write, iclass 34, count 2 2006.257.20:52:39.27#ibcon#enter sib2, iclass 34, count 2 2006.257.20:52:39.27#ibcon#flushed, iclass 34, count 2 2006.257.20:52:39.27#ibcon#about to write, iclass 34, count 2 2006.257.20:52:39.27#ibcon#wrote, iclass 34, count 2 2006.257.20:52:39.27#ibcon#about to read 3, iclass 34, count 2 2006.257.20:52:39.29#abcon#<5=/14 1.2 2.8 17.33 971015.0\r\n> 2006.257.20:52:39.30#ibcon#read 3, iclass 34, count 2 2006.257.20:52:39.30#ibcon#about to read 4, iclass 34, count 2 2006.257.20:52:39.30#ibcon#read 4, iclass 34, count 2 2006.257.20:52:39.30#ibcon#about to read 5, iclass 34, count 2 2006.257.20:52:39.30#ibcon#read 5, iclass 34, count 2 2006.257.20:52:39.30#ibcon#about to read 6, iclass 34, count 2 2006.257.20:52:39.30#ibcon#read 6, iclass 34, count 2 2006.257.20:52:39.30#ibcon#end of sib2, iclass 34, count 2 2006.257.20:52:39.30#ibcon#*after write, iclass 34, count 2 2006.257.20:52:39.30#ibcon#*before return 0, iclass 34, count 2 2006.257.20:52:39.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:39.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:39.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.20:52:39.30#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:39.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:39.31#abcon#{5=INTERFACE CLEAR} 2006.257.20:52:39.37#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:52:39.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:39.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:39.42#ibcon#enter wrdev, iclass 34, count 0 2006.257.20:52:39.42#ibcon#first serial, iclass 34, count 0 2006.257.20:52:39.42#ibcon#enter sib2, iclass 34, count 0 2006.257.20:52:39.42#ibcon#flushed, iclass 34, count 0 2006.257.20:52:39.42#ibcon#about to write, iclass 34, count 0 2006.257.20:52:39.42#ibcon#wrote, iclass 34, count 0 2006.257.20:52:39.42#ibcon#about to read 3, iclass 34, count 0 2006.257.20:52:39.44#ibcon#read 3, iclass 34, count 0 2006.257.20:52:39.44#ibcon#about to read 4, iclass 34, count 0 2006.257.20:52:39.44#ibcon#read 4, iclass 34, count 0 2006.257.20:52:39.44#ibcon#about to read 5, iclass 34, count 0 2006.257.20:52:39.44#ibcon#read 5, iclass 34, count 0 2006.257.20:52:39.44#ibcon#about to read 6, iclass 34, count 0 2006.257.20:52:39.44#ibcon#read 6, iclass 34, count 0 2006.257.20:52:39.44#ibcon#end of sib2, iclass 34, count 0 2006.257.20:52:39.44#ibcon#*mode == 0, iclass 34, count 0 2006.257.20:52:39.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.20:52:39.44#ibcon#[25=USB\r\n] 2006.257.20:52:39.44#ibcon#*before write, iclass 34, count 0 2006.257.20:52:39.44#ibcon#enter sib2, iclass 34, count 0 2006.257.20:52:39.44#ibcon#flushed, iclass 34, count 0 2006.257.20:52:39.44#ibcon#about to write, iclass 34, count 0 2006.257.20:52:39.44#ibcon#wrote, iclass 34, count 0 2006.257.20:52:39.44#ibcon#about to read 3, iclass 34, count 0 2006.257.20:52:39.47#ibcon#read 3, iclass 34, count 0 2006.257.20:52:39.47#ibcon#about to read 4, iclass 34, count 0 2006.257.20:52:39.47#ibcon#read 4, iclass 34, count 0 2006.257.20:52:39.47#ibcon#about to read 5, iclass 34, count 0 2006.257.20:52:39.47#ibcon#read 5, iclass 34, count 0 2006.257.20:52:39.47#ibcon#about to read 6, iclass 34, count 0 2006.257.20:52:39.47#ibcon#read 6, iclass 34, count 0 2006.257.20:52:39.47#ibcon#end of sib2, iclass 34, count 0 2006.257.20:52:39.47#ibcon#*after write, iclass 34, count 0 2006.257.20:52:39.47#ibcon#*before return 0, iclass 34, count 0 2006.257.20:52:39.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:39.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:39.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.20:52:39.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.20:52:39.47$vck44/valo=7,864.99 2006.257.20:52:39.47#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.20:52:39.47#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.20:52:39.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:39.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:39.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:39.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:39.47#ibcon#enter wrdev, iclass 40, count 0 2006.257.20:52:39.47#ibcon#first serial, iclass 40, count 0 2006.257.20:52:39.47#ibcon#enter sib2, iclass 40, count 0 2006.257.20:52:39.47#ibcon#flushed, iclass 40, count 0 2006.257.20:52:39.47#ibcon#about to write, iclass 40, count 0 2006.257.20:52:39.47#ibcon#wrote, iclass 40, count 0 2006.257.20:52:39.47#ibcon#about to read 3, iclass 40, count 0 2006.257.20:52:39.49#ibcon#read 3, iclass 40, count 0 2006.257.20:52:39.49#ibcon#about to read 4, iclass 40, count 0 2006.257.20:52:39.49#ibcon#read 4, iclass 40, count 0 2006.257.20:52:39.49#ibcon#about to read 5, iclass 40, count 0 2006.257.20:52:39.49#ibcon#read 5, iclass 40, count 0 2006.257.20:52:39.49#ibcon#about to read 6, iclass 40, count 0 2006.257.20:52:39.49#ibcon#read 6, iclass 40, count 0 2006.257.20:52:39.49#ibcon#end of sib2, iclass 40, count 0 2006.257.20:52:39.49#ibcon#*mode == 0, iclass 40, count 0 2006.257.20:52:39.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.20:52:39.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.20:52:39.49#ibcon#*before write, iclass 40, count 0 2006.257.20:52:39.49#ibcon#enter sib2, iclass 40, count 0 2006.257.20:52:39.49#ibcon#flushed, iclass 40, count 0 2006.257.20:52:39.49#ibcon#about to write, iclass 40, count 0 2006.257.20:52:39.49#ibcon#wrote, iclass 40, count 0 2006.257.20:52:39.49#ibcon#about to read 3, iclass 40, count 0 2006.257.20:52:39.53#ibcon#read 3, iclass 40, count 0 2006.257.20:52:39.53#ibcon#about to read 4, iclass 40, count 0 2006.257.20:52:39.53#ibcon#read 4, iclass 40, count 0 2006.257.20:52:39.53#ibcon#about to read 5, iclass 40, count 0 2006.257.20:52:39.53#ibcon#read 5, iclass 40, count 0 2006.257.20:52:39.53#ibcon#about to read 6, iclass 40, count 0 2006.257.20:52:39.53#ibcon#read 6, iclass 40, count 0 2006.257.20:52:39.53#ibcon#end of sib2, iclass 40, count 0 2006.257.20:52:39.53#ibcon#*after write, iclass 40, count 0 2006.257.20:52:39.53#ibcon#*before return 0, iclass 40, count 0 2006.257.20:52:39.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:39.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:39.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.20:52:39.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.20:52:39.53$vck44/va=7,4 2006.257.20:52:39.53#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.20:52:39.53#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.20:52:39.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:39.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:39.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:39.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:39.59#ibcon#enter wrdev, iclass 4, count 2 2006.257.20:52:39.59#ibcon#first serial, iclass 4, count 2 2006.257.20:52:39.59#ibcon#enter sib2, iclass 4, count 2 2006.257.20:52:39.59#ibcon#flushed, iclass 4, count 2 2006.257.20:52:39.59#ibcon#about to write, iclass 4, count 2 2006.257.20:52:39.59#ibcon#wrote, iclass 4, count 2 2006.257.20:52:39.59#ibcon#about to read 3, iclass 4, count 2 2006.257.20:52:39.61#ibcon#read 3, iclass 4, count 2 2006.257.20:52:39.61#ibcon#about to read 4, iclass 4, count 2 2006.257.20:52:39.61#ibcon#read 4, iclass 4, count 2 2006.257.20:52:39.61#ibcon#about to read 5, iclass 4, count 2 2006.257.20:52:39.61#ibcon#read 5, iclass 4, count 2 2006.257.20:52:39.61#ibcon#about to read 6, iclass 4, count 2 2006.257.20:52:39.61#ibcon#read 6, iclass 4, count 2 2006.257.20:52:39.61#ibcon#end of sib2, iclass 4, count 2 2006.257.20:52:39.61#ibcon#*mode == 0, iclass 4, count 2 2006.257.20:52:39.61#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.20:52:39.61#ibcon#[25=AT07-04\r\n] 2006.257.20:52:39.61#ibcon#*before write, iclass 4, count 2 2006.257.20:52:39.61#ibcon#enter sib2, iclass 4, count 2 2006.257.20:52:39.61#ibcon#flushed, iclass 4, count 2 2006.257.20:52:39.61#ibcon#about to write, iclass 4, count 2 2006.257.20:52:39.61#ibcon#wrote, iclass 4, count 2 2006.257.20:52:39.61#ibcon#about to read 3, iclass 4, count 2 2006.257.20:52:39.64#ibcon#read 3, iclass 4, count 2 2006.257.20:52:39.64#ibcon#about to read 4, iclass 4, count 2 2006.257.20:52:39.64#ibcon#read 4, iclass 4, count 2 2006.257.20:52:39.64#ibcon#about to read 5, iclass 4, count 2 2006.257.20:52:39.64#ibcon#read 5, iclass 4, count 2 2006.257.20:52:39.64#ibcon#about to read 6, iclass 4, count 2 2006.257.20:52:39.64#ibcon#read 6, iclass 4, count 2 2006.257.20:52:39.64#ibcon#end of sib2, iclass 4, count 2 2006.257.20:52:39.64#ibcon#*after write, iclass 4, count 2 2006.257.20:52:39.64#ibcon#*before return 0, iclass 4, count 2 2006.257.20:52:39.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:39.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:39.64#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.20:52:39.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:39.64#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:39.76#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:39.76#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:39.76#ibcon#enter wrdev, iclass 4, count 0 2006.257.20:52:39.76#ibcon#first serial, iclass 4, count 0 2006.257.20:52:39.76#ibcon#enter sib2, iclass 4, count 0 2006.257.20:52:39.76#ibcon#flushed, iclass 4, count 0 2006.257.20:52:39.76#ibcon#about to write, iclass 4, count 0 2006.257.20:52:39.76#ibcon#wrote, iclass 4, count 0 2006.257.20:52:39.76#ibcon#about to read 3, iclass 4, count 0 2006.257.20:52:39.78#ibcon#read 3, iclass 4, count 0 2006.257.20:52:39.78#ibcon#about to read 4, iclass 4, count 0 2006.257.20:52:39.78#ibcon#read 4, iclass 4, count 0 2006.257.20:52:39.78#ibcon#about to read 5, iclass 4, count 0 2006.257.20:52:39.78#ibcon#read 5, iclass 4, count 0 2006.257.20:52:39.78#ibcon#about to read 6, iclass 4, count 0 2006.257.20:52:39.78#ibcon#read 6, iclass 4, count 0 2006.257.20:52:39.78#ibcon#end of sib2, iclass 4, count 0 2006.257.20:52:39.78#ibcon#*mode == 0, iclass 4, count 0 2006.257.20:52:39.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.20:52:39.78#ibcon#[25=USB\r\n] 2006.257.20:52:39.78#ibcon#*before write, iclass 4, count 0 2006.257.20:52:39.78#ibcon#enter sib2, iclass 4, count 0 2006.257.20:52:39.78#ibcon#flushed, iclass 4, count 0 2006.257.20:52:39.78#ibcon#about to write, iclass 4, count 0 2006.257.20:52:39.78#ibcon#wrote, iclass 4, count 0 2006.257.20:52:39.78#ibcon#about to read 3, iclass 4, count 0 2006.257.20:52:39.81#ibcon#read 3, iclass 4, count 0 2006.257.20:52:39.81#ibcon#about to read 4, iclass 4, count 0 2006.257.20:52:39.81#ibcon#read 4, iclass 4, count 0 2006.257.20:52:39.81#ibcon#about to read 5, iclass 4, count 0 2006.257.20:52:39.81#ibcon#read 5, iclass 4, count 0 2006.257.20:52:39.81#ibcon#about to read 6, iclass 4, count 0 2006.257.20:52:39.81#ibcon#read 6, iclass 4, count 0 2006.257.20:52:39.81#ibcon#end of sib2, iclass 4, count 0 2006.257.20:52:39.81#ibcon#*after write, iclass 4, count 0 2006.257.20:52:39.81#ibcon#*before return 0, iclass 4, count 0 2006.257.20:52:39.81#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:39.81#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:39.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.20:52:39.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.20:52:39.81$vck44/valo=8,884.99 2006.257.20:52:39.81#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.20:52:39.81#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.20:52:39.81#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:39.81#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:39.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:39.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:39.81#ibcon#enter wrdev, iclass 6, count 0 2006.257.20:52:39.81#ibcon#first serial, iclass 6, count 0 2006.257.20:52:39.81#ibcon#enter sib2, iclass 6, count 0 2006.257.20:52:39.81#ibcon#flushed, iclass 6, count 0 2006.257.20:52:39.81#ibcon#about to write, iclass 6, count 0 2006.257.20:52:39.81#ibcon#wrote, iclass 6, count 0 2006.257.20:52:39.81#ibcon#about to read 3, iclass 6, count 0 2006.257.20:52:39.83#ibcon#read 3, iclass 6, count 0 2006.257.20:52:39.83#ibcon#about to read 4, iclass 6, count 0 2006.257.20:52:39.83#ibcon#read 4, iclass 6, count 0 2006.257.20:52:39.83#ibcon#about to read 5, iclass 6, count 0 2006.257.20:52:39.83#ibcon#read 5, iclass 6, count 0 2006.257.20:52:39.83#ibcon#about to read 6, iclass 6, count 0 2006.257.20:52:39.83#ibcon#read 6, iclass 6, count 0 2006.257.20:52:39.83#ibcon#end of sib2, iclass 6, count 0 2006.257.20:52:39.83#ibcon#*mode == 0, iclass 6, count 0 2006.257.20:52:39.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.20:52:39.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.20:52:39.83#ibcon#*before write, iclass 6, count 0 2006.257.20:52:39.83#ibcon#enter sib2, iclass 6, count 0 2006.257.20:52:39.83#ibcon#flushed, iclass 6, count 0 2006.257.20:52:39.83#ibcon#about to write, iclass 6, count 0 2006.257.20:52:39.83#ibcon#wrote, iclass 6, count 0 2006.257.20:52:39.83#ibcon#about to read 3, iclass 6, count 0 2006.257.20:52:39.87#ibcon#read 3, iclass 6, count 0 2006.257.20:52:39.87#ibcon#about to read 4, iclass 6, count 0 2006.257.20:52:39.87#ibcon#read 4, iclass 6, count 0 2006.257.20:52:39.87#ibcon#about to read 5, iclass 6, count 0 2006.257.20:52:39.87#ibcon#read 5, iclass 6, count 0 2006.257.20:52:39.87#ibcon#about to read 6, iclass 6, count 0 2006.257.20:52:39.87#ibcon#read 6, iclass 6, count 0 2006.257.20:52:39.87#ibcon#end of sib2, iclass 6, count 0 2006.257.20:52:39.87#ibcon#*after write, iclass 6, count 0 2006.257.20:52:39.87#ibcon#*before return 0, iclass 6, count 0 2006.257.20:52:39.87#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:39.87#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:39.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.20:52:39.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.20:52:39.87$vck44/va=8,4 2006.257.20:52:39.87#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.20:52:39.87#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.20:52:39.87#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:39.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:52:39.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:52:39.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:52:39.93#ibcon#enter wrdev, iclass 10, count 2 2006.257.20:52:39.93#ibcon#first serial, iclass 10, count 2 2006.257.20:52:39.93#ibcon#enter sib2, iclass 10, count 2 2006.257.20:52:39.93#ibcon#flushed, iclass 10, count 2 2006.257.20:52:39.93#ibcon#about to write, iclass 10, count 2 2006.257.20:52:39.93#ibcon#wrote, iclass 10, count 2 2006.257.20:52:39.93#ibcon#about to read 3, iclass 10, count 2 2006.257.20:52:39.95#ibcon#read 3, iclass 10, count 2 2006.257.20:52:39.95#ibcon#about to read 4, iclass 10, count 2 2006.257.20:52:39.95#ibcon#read 4, iclass 10, count 2 2006.257.20:52:39.95#ibcon#about to read 5, iclass 10, count 2 2006.257.20:52:39.95#ibcon#read 5, iclass 10, count 2 2006.257.20:52:39.95#ibcon#about to read 6, iclass 10, count 2 2006.257.20:52:39.95#ibcon#read 6, iclass 10, count 2 2006.257.20:52:39.95#ibcon#end of sib2, iclass 10, count 2 2006.257.20:52:39.95#ibcon#*mode == 0, iclass 10, count 2 2006.257.20:52:39.95#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.20:52:39.95#ibcon#[25=AT08-04\r\n] 2006.257.20:52:39.95#ibcon#*before write, iclass 10, count 2 2006.257.20:52:39.95#ibcon#enter sib2, iclass 10, count 2 2006.257.20:52:39.95#ibcon#flushed, iclass 10, count 2 2006.257.20:52:39.95#ibcon#about to write, iclass 10, count 2 2006.257.20:52:39.95#ibcon#wrote, iclass 10, count 2 2006.257.20:52:39.95#ibcon#about to read 3, iclass 10, count 2 2006.257.20:52:39.98#ibcon#read 3, iclass 10, count 2 2006.257.20:52:39.98#ibcon#about to read 4, iclass 10, count 2 2006.257.20:52:39.98#ibcon#read 4, iclass 10, count 2 2006.257.20:52:39.98#ibcon#about to read 5, iclass 10, count 2 2006.257.20:52:39.98#ibcon#read 5, iclass 10, count 2 2006.257.20:52:39.98#ibcon#about to read 6, iclass 10, count 2 2006.257.20:52:39.98#ibcon#read 6, iclass 10, count 2 2006.257.20:52:39.98#ibcon#end of sib2, iclass 10, count 2 2006.257.20:52:39.98#ibcon#*after write, iclass 10, count 2 2006.257.20:52:39.98#ibcon#*before return 0, iclass 10, count 2 2006.257.20:52:39.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:52:39.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.20:52:39.98#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.20:52:39.98#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:39.98#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:52:40.10#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:52:40.10#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:52:40.10#ibcon#enter wrdev, iclass 10, count 0 2006.257.20:52:40.10#ibcon#first serial, iclass 10, count 0 2006.257.20:52:40.10#ibcon#enter sib2, iclass 10, count 0 2006.257.20:52:40.10#ibcon#flushed, iclass 10, count 0 2006.257.20:52:40.10#ibcon#about to write, iclass 10, count 0 2006.257.20:52:40.10#ibcon#wrote, iclass 10, count 0 2006.257.20:52:40.10#ibcon#about to read 3, iclass 10, count 0 2006.257.20:52:40.12#ibcon#read 3, iclass 10, count 0 2006.257.20:52:40.12#ibcon#about to read 4, iclass 10, count 0 2006.257.20:52:40.12#ibcon#read 4, iclass 10, count 0 2006.257.20:52:40.12#ibcon#about to read 5, iclass 10, count 0 2006.257.20:52:40.12#ibcon#read 5, iclass 10, count 0 2006.257.20:52:40.12#ibcon#about to read 6, iclass 10, count 0 2006.257.20:52:40.12#ibcon#read 6, iclass 10, count 0 2006.257.20:52:40.12#ibcon#end of sib2, iclass 10, count 0 2006.257.20:52:40.12#ibcon#*mode == 0, iclass 10, count 0 2006.257.20:52:40.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.20:52:40.12#ibcon#[25=USB\r\n] 2006.257.20:52:40.12#ibcon#*before write, iclass 10, count 0 2006.257.20:52:40.12#ibcon#enter sib2, iclass 10, count 0 2006.257.20:52:40.12#ibcon#flushed, iclass 10, count 0 2006.257.20:52:40.12#ibcon#about to write, iclass 10, count 0 2006.257.20:52:40.12#ibcon#wrote, iclass 10, count 0 2006.257.20:52:40.12#ibcon#about to read 3, iclass 10, count 0 2006.257.20:52:40.15#ibcon#read 3, iclass 10, count 0 2006.257.20:52:40.15#ibcon#about to read 4, iclass 10, count 0 2006.257.20:52:40.15#ibcon#read 4, iclass 10, count 0 2006.257.20:52:40.15#ibcon#about to read 5, iclass 10, count 0 2006.257.20:52:40.15#ibcon#read 5, iclass 10, count 0 2006.257.20:52:40.15#ibcon#about to read 6, iclass 10, count 0 2006.257.20:52:40.15#ibcon#read 6, iclass 10, count 0 2006.257.20:52:40.15#ibcon#end of sib2, iclass 10, count 0 2006.257.20:52:40.15#ibcon#*after write, iclass 10, count 0 2006.257.20:52:40.15#ibcon#*before return 0, iclass 10, count 0 2006.257.20:52:40.15#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:52:40.15#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.20:52:40.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.20:52:40.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.20:52:40.15$vck44/vblo=1,629.99 2006.257.20:52:40.15#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.20:52:40.15#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.20:52:40.15#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:40.15#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:40.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:40.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:40.15#ibcon#enter wrdev, iclass 12, count 0 2006.257.20:52:40.15#ibcon#first serial, iclass 12, count 0 2006.257.20:52:40.15#ibcon#enter sib2, iclass 12, count 0 2006.257.20:52:40.15#ibcon#flushed, iclass 12, count 0 2006.257.20:52:40.15#ibcon#about to write, iclass 12, count 0 2006.257.20:52:40.15#ibcon#wrote, iclass 12, count 0 2006.257.20:52:40.15#ibcon#about to read 3, iclass 12, count 0 2006.257.20:52:40.17#ibcon#read 3, iclass 12, count 0 2006.257.20:52:40.17#ibcon#about to read 4, iclass 12, count 0 2006.257.20:52:40.17#ibcon#read 4, iclass 12, count 0 2006.257.20:52:40.17#ibcon#about to read 5, iclass 12, count 0 2006.257.20:52:40.17#ibcon#read 5, iclass 12, count 0 2006.257.20:52:40.17#ibcon#about to read 6, iclass 12, count 0 2006.257.20:52:40.17#ibcon#read 6, iclass 12, count 0 2006.257.20:52:40.17#ibcon#end of sib2, iclass 12, count 0 2006.257.20:52:40.17#ibcon#*mode == 0, iclass 12, count 0 2006.257.20:52:40.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.20:52:40.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.20:52:40.17#ibcon#*before write, iclass 12, count 0 2006.257.20:52:40.17#ibcon#enter sib2, iclass 12, count 0 2006.257.20:52:40.17#ibcon#flushed, iclass 12, count 0 2006.257.20:52:40.17#ibcon#about to write, iclass 12, count 0 2006.257.20:52:40.17#ibcon#wrote, iclass 12, count 0 2006.257.20:52:40.17#ibcon#about to read 3, iclass 12, count 0 2006.257.20:52:40.21#ibcon#read 3, iclass 12, count 0 2006.257.20:52:40.21#ibcon#about to read 4, iclass 12, count 0 2006.257.20:52:40.21#ibcon#read 4, iclass 12, count 0 2006.257.20:52:40.21#ibcon#about to read 5, iclass 12, count 0 2006.257.20:52:40.21#ibcon#read 5, iclass 12, count 0 2006.257.20:52:40.21#ibcon#about to read 6, iclass 12, count 0 2006.257.20:52:40.21#ibcon#read 6, iclass 12, count 0 2006.257.20:52:40.21#ibcon#end of sib2, iclass 12, count 0 2006.257.20:52:40.21#ibcon#*after write, iclass 12, count 0 2006.257.20:52:40.21#ibcon#*before return 0, iclass 12, count 0 2006.257.20:52:40.21#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:40.21#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.20:52:40.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.20:52:40.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.20:52:40.21$vck44/vb=1,4 2006.257.20:52:40.21#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.20:52:40.21#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.20:52:40.21#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:40.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:40.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:40.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:40.21#ibcon#enter wrdev, iclass 14, count 2 2006.257.20:52:40.21#ibcon#first serial, iclass 14, count 2 2006.257.20:52:40.21#ibcon#enter sib2, iclass 14, count 2 2006.257.20:52:40.21#ibcon#flushed, iclass 14, count 2 2006.257.20:52:40.21#ibcon#about to write, iclass 14, count 2 2006.257.20:52:40.21#ibcon#wrote, iclass 14, count 2 2006.257.20:52:40.21#ibcon#about to read 3, iclass 14, count 2 2006.257.20:52:40.23#ibcon#read 3, iclass 14, count 2 2006.257.20:52:40.23#ibcon#about to read 4, iclass 14, count 2 2006.257.20:52:40.23#ibcon#read 4, iclass 14, count 2 2006.257.20:52:40.23#ibcon#about to read 5, iclass 14, count 2 2006.257.20:52:40.23#ibcon#read 5, iclass 14, count 2 2006.257.20:52:40.23#ibcon#about to read 6, iclass 14, count 2 2006.257.20:52:40.23#ibcon#read 6, iclass 14, count 2 2006.257.20:52:40.23#ibcon#end of sib2, iclass 14, count 2 2006.257.20:52:40.23#ibcon#*mode == 0, iclass 14, count 2 2006.257.20:52:40.23#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.20:52:40.23#ibcon#[27=AT01-04\r\n] 2006.257.20:52:40.23#ibcon#*before write, iclass 14, count 2 2006.257.20:52:40.23#ibcon#enter sib2, iclass 14, count 2 2006.257.20:52:40.23#ibcon#flushed, iclass 14, count 2 2006.257.20:52:40.23#ibcon#about to write, iclass 14, count 2 2006.257.20:52:40.23#ibcon#wrote, iclass 14, count 2 2006.257.20:52:40.23#ibcon#about to read 3, iclass 14, count 2 2006.257.20:52:40.26#ibcon#read 3, iclass 14, count 2 2006.257.20:52:40.26#ibcon#about to read 4, iclass 14, count 2 2006.257.20:52:40.26#ibcon#read 4, iclass 14, count 2 2006.257.20:52:40.26#ibcon#about to read 5, iclass 14, count 2 2006.257.20:52:40.26#ibcon#read 5, iclass 14, count 2 2006.257.20:52:40.26#ibcon#about to read 6, iclass 14, count 2 2006.257.20:52:40.26#ibcon#read 6, iclass 14, count 2 2006.257.20:52:40.26#ibcon#end of sib2, iclass 14, count 2 2006.257.20:52:40.26#ibcon#*after write, iclass 14, count 2 2006.257.20:52:40.26#ibcon#*before return 0, iclass 14, count 2 2006.257.20:52:40.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:40.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.20:52:40.26#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.20:52:40.26#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:40.26#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:40.38#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:40.38#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:40.38#ibcon#enter wrdev, iclass 14, count 0 2006.257.20:52:40.38#ibcon#first serial, iclass 14, count 0 2006.257.20:52:40.38#ibcon#enter sib2, iclass 14, count 0 2006.257.20:52:40.38#ibcon#flushed, iclass 14, count 0 2006.257.20:52:40.38#ibcon#about to write, iclass 14, count 0 2006.257.20:52:40.38#ibcon#wrote, iclass 14, count 0 2006.257.20:52:40.38#ibcon#about to read 3, iclass 14, count 0 2006.257.20:52:40.40#ibcon#read 3, iclass 14, count 0 2006.257.20:52:40.40#ibcon#about to read 4, iclass 14, count 0 2006.257.20:52:40.40#ibcon#read 4, iclass 14, count 0 2006.257.20:52:40.40#ibcon#about to read 5, iclass 14, count 0 2006.257.20:52:40.40#ibcon#read 5, iclass 14, count 0 2006.257.20:52:40.40#ibcon#about to read 6, iclass 14, count 0 2006.257.20:52:40.40#ibcon#read 6, iclass 14, count 0 2006.257.20:52:40.40#ibcon#end of sib2, iclass 14, count 0 2006.257.20:52:40.40#ibcon#*mode == 0, iclass 14, count 0 2006.257.20:52:40.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.20:52:40.40#ibcon#[27=USB\r\n] 2006.257.20:52:40.40#ibcon#*before write, iclass 14, count 0 2006.257.20:52:40.40#ibcon#enter sib2, iclass 14, count 0 2006.257.20:52:40.40#ibcon#flushed, iclass 14, count 0 2006.257.20:52:40.40#ibcon#about to write, iclass 14, count 0 2006.257.20:52:40.40#ibcon#wrote, iclass 14, count 0 2006.257.20:52:40.40#ibcon#about to read 3, iclass 14, count 0 2006.257.20:52:40.43#ibcon#read 3, iclass 14, count 0 2006.257.20:52:40.43#ibcon#about to read 4, iclass 14, count 0 2006.257.20:52:40.43#ibcon#read 4, iclass 14, count 0 2006.257.20:52:40.43#ibcon#about to read 5, iclass 14, count 0 2006.257.20:52:40.43#ibcon#read 5, iclass 14, count 0 2006.257.20:52:40.43#ibcon#about to read 6, iclass 14, count 0 2006.257.20:52:40.43#ibcon#read 6, iclass 14, count 0 2006.257.20:52:40.43#ibcon#end of sib2, iclass 14, count 0 2006.257.20:52:40.43#ibcon#*after write, iclass 14, count 0 2006.257.20:52:40.43#ibcon#*before return 0, iclass 14, count 0 2006.257.20:52:40.43#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:40.43#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.20:52:40.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.20:52:40.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.20:52:40.43$vck44/vblo=2,634.99 2006.257.20:52:40.43#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.20:52:40.43#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.20:52:40.43#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:40.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:40.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:40.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:40.43#ibcon#enter wrdev, iclass 16, count 0 2006.257.20:52:40.43#ibcon#first serial, iclass 16, count 0 2006.257.20:52:40.43#ibcon#enter sib2, iclass 16, count 0 2006.257.20:52:40.43#ibcon#flushed, iclass 16, count 0 2006.257.20:52:40.43#ibcon#about to write, iclass 16, count 0 2006.257.20:52:40.43#ibcon#wrote, iclass 16, count 0 2006.257.20:52:40.43#ibcon#about to read 3, iclass 16, count 0 2006.257.20:52:40.45#ibcon#read 3, iclass 16, count 0 2006.257.20:52:40.45#ibcon#about to read 4, iclass 16, count 0 2006.257.20:52:40.45#ibcon#read 4, iclass 16, count 0 2006.257.20:52:40.45#ibcon#about to read 5, iclass 16, count 0 2006.257.20:52:40.45#ibcon#read 5, iclass 16, count 0 2006.257.20:52:40.45#ibcon#about to read 6, iclass 16, count 0 2006.257.20:52:40.45#ibcon#read 6, iclass 16, count 0 2006.257.20:52:40.45#ibcon#end of sib2, iclass 16, count 0 2006.257.20:52:40.45#ibcon#*mode == 0, iclass 16, count 0 2006.257.20:52:40.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.20:52:40.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.20:52:40.45#ibcon#*before write, iclass 16, count 0 2006.257.20:52:40.45#ibcon#enter sib2, iclass 16, count 0 2006.257.20:52:40.45#ibcon#flushed, iclass 16, count 0 2006.257.20:52:40.45#ibcon#about to write, iclass 16, count 0 2006.257.20:52:40.45#ibcon#wrote, iclass 16, count 0 2006.257.20:52:40.45#ibcon#about to read 3, iclass 16, count 0 2006.257.20:52:40.49#ibcon#read 3, iclass 16, count 0 2006.257.20:52:40.49#ibcon#about to read 4, iclass 16, count 0 2006.257.20:52:40.49#ibcon#read 4, iclass 16, count 0 2006.257.20:52:40.49#ibcon#about to read 5, iclass 16, count 0 2006.257.20:52:40.49#ibcon#read 5, iclass 16, count 0 2006.257.20:52:40.49#ibcon#about to read 6, iclass 16, count 0 2006.257.20:52:40.49#ibcon#read 6, iclass 16, count 0 2006.257.20:52:40.49#ibcon#end of sib2, iclass 16, count 0 2006.257.20:52:40.49#ibcon#*after write, iclass 16, count 0 2006.257.20:52:40.49#ibcon#*before return 0, iclass 16, count 0 2006.257.20:52:40.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:40.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.20:52:40.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.20:52:40.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.20:52:40.49$vck44/vb=2,5 2006.257.20:52:40.49#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.20:52:40.49#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.20:52:40.49#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:40.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:40.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:40.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:40.55#ibcon#enter wrdev, iclass 18, count 2 2006.257.20:52:40.55#ibcon#first serial, iclass 18, count 2 2006.257.20:52:40.55#ibcon#enter sib2, iclass 18, count 2 2006.257.20:52:40.55#ibcon#flushed, iclass 18, count 2 2006.257.20:52:40.55#ibcon#about to write, iclass 18, count 2 2006.257.20:52:40.55#ibcon#wrote, iclass 18, count 2 2006.257.20:52:40.55#ibcon#about to read 3, iclass 18, count 2 2006.257.20:52:40.57#ibcon#read 3, iclass 18, count 2 2006.257.20:52:40.57#ibcon#about to read 4, iclass 18, count 2 2006.257.20:52:40.57#ibcon#read 4, iclass 18, count 2 2006.257.20:52:40.57#ibcon#about to read 5, iclass 18, count 2 2006.257.20:52:40.57#ibcon#read 5, iclass 18, count 2 2006.257.20:52:40.57#ibcon#about to read 6, iclass 18, count 2 2006.257.20:52:40.57#ibcon#read 6, iclass 18, count 2 2006.257.20:52:40.57#ibcon#end of sib2, iclass 18, count 2 2006.257.20:52:40.57#ibcon#*mode == 0, iclass 18, count 2 2006.257.20:52:40.57#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.20:52:40.57#ibcon#[27=AT02-05\r\n] 2006.257.20:52:40.57#ibcon#*before write, iclass 18, count 2 2006.257.20:52:40.57#ibcon#enter sib2, iclass 18, count 2 2006.257.20:52:40.57#ibcon#flushed, iclass 18, count 2 2006.257.20:52:40.57#ibcon#about to write, iclass 18, count 2 2006.257.20:52:40.57#ibcon#wrote, iclass 18, count 2 2006.257.20:52:40.57#ibcon#about to read 3, iclass 18, count 2 2006.257.20:52:40.60#ibcon#read 3, iclass 18, count 2 2006.257.20:52:40.60#ibcon#about to read 4, iclass 18, count 2 2006.257.20:52:40.60#ibcon#read 4, iclass 18, count 2 2006.257.20:52:40.60#ibcon#about to read 5, iclass 18, count 2 2006.257.20:52:40.60#ibcon#read 5, iclass 18, count 2 2006.257.20:52:40.60#ibcon#about to read 6, iclass 18, count 2 2006.257.20:52:40.60#ibcon#read 6, iclass 18, count 2 2006.257.20:52:40.60#ibcon#end of sib2, iclass 18, count 2 2006.257.20:52:40.60#ibcon#*after write, iclass 18, count 2 2006.257.20:52:40.60#ibcon#*before return 0, iclass 18, count 2 2006.257.20:52:40.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:40.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.20:52:40.60#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.20:52:40.60#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:40.60#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:40.72#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:40.72#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:40.72#ibcon#enter wrdev, iclass 18, count 0 2006.257.20:52:40.72#ibcon#first serial, iclass 18, count 0 2006.257.20:52:40.72#ibcon#enter sib2, iclass 18, count 0 2006.257.20:52:40.72#ibcon#flushed, iclass 18, count 0 2006.257.20:52:40.72#ibcon#about to write, iclass 18, count 0 2006.257.20:52:40.72#ibcon#wrote, iclass 18, count 0 2006.257.20:52:40.72#ibcon#about to read 3, iclass 18, count 0 2006.257.20:52:40.74#ibcon#read 3, iclass 18, count 0 2006.257.20:52:40.74#ibcon#about to read 4, iclass 18, count 0 2006.257.20:52:40.74#ibcon#read 4, iclass 18, count 0 2006.257.20:52:40.74#ibcon#about to read 5, iclass 18, count 0 2006.257.20:52:40.74#ibcon#read 5, iclass 18, count 0 2006.257.20:52:40.74#ibcon#about to read 6, iclass 18, count 0 2006.257.20:52:40.74#ibcon#read 6, iclass 18, count 0 2006.257.20:52:40.74#ibcon#end of sib2, iclass 18, count 0 2006.257.20:52:40.74#ibcon#*mode == 0, iclass 18, count 0 2006.257.20:52:40.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.20:52:40.74#ibcon#[27=USB\r\n] 2006.257.20:52:40.74#ibcon#*before write, iclass 18, count 0 2006.257.20:52:40.74#ibcon#enter sib2, iclass 18, count 0 2006.257.20:52:40.74#ibcon#flushed, iclass 18, count 0 2006.257.20:52:40.74#ibcon#about to write, iclass 18, count 0 2006.257.20:52:40.74#ibcon#wrote, iclass 18, count 0 2006.257.20:52:40.74#ibcon#about to read 3, iclass 18, count 0 2006.257.20:52:40.77#ibcon#read 3, iclass 18, count 0 2006.257.20:52:40.77#ibcon#about to read 4, iclass 18, count 0 2006.257.20:52:40.77#ibcon#read 4, iclass 18, count 0 2006.257.20:52:40.77#ibcon#about to read 5, iclass 18, count 0 2006.257.20:52:40.77#ibcon#read 5, iclass 18, count 0 2006.257.20:52:40.77#ibcon#about to read 6, iclass 18, count 0 2006.257.20:52:40.77#ibcon#read 6, iclass 18, count 0 2006.257.20:52:40.77#ibcon#end of sib2, iclass 18, count 0 2006.257.20:52:40.77#ibcon#*after write, iclass 18, count 0 2006.257.20:52:40.77#ibcon#*before return 0, iclass 18, count 0 2006.257.20:52:40.77#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:40.77#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.20:52:40.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.20:52:40.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.20:52:40.77$vck44/vblo=3,649.99 2006.257.20:52:40.77#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.20:52:40.77#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.20:52:40.77#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:40.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:40.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:40.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:40.77#ibcon#enter wrdev, iclass 20, count 0 2006.257.20:52:40.77#ibcon#first serial, iclass 20, count 0 2006.257.20:52:40.77#ibcon#enter sib2, iclass 20, count 0 2006.257.20:52:40.77#ibcon#flushed, iclass 20, count 0 2006.257.20:52:40.77#ibcon#about to write, iclass 20, count 0 2006.257.20:52:40.77#ibcon#wrote, iclass 20, count 0 2006.257.20:52:40.77#ibcon#about to read 3, iclass 20, count 0 2006.257.20:52:40.79#ibcon#read 3, iclass 20, count 0 2006.257.20:52:40.79#ibcon#about to read 4, iclass 20, count 0 2006.257.20:52:40.79#ibcon#read 4, iclass 20, count 0 2006.257.20:52:40.79#ibcon#about to read 5, iclass 20, count 0 2006.257.20:52:40.79#ibcon#read 5, iclass 20, count 0 2006.257.20:52:40.79#ibcon#about to read 6, iclass 20, count 0 2006.257.20:52:40.79#ibcon#read 6, iclass 20, count 0 2006.257.20:52:40.79#ibcon#end of sib2, iclass 20, count 0 2006.257.20:52:40.79#ibcon#*mode == 0, iclass 20, count 0 2006.257.20:52:40.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.20:52:40.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.20:52:40.79#ibcon#*before write, iclass 20, count 0 2006.257.20:52:40.79#ibcon#enter sib2, iclass 20, count 0 2006.257.20:52:40.79#ibcon#flushed, iclass 20, count 0 2006.257.20:52:40.79#ibcon#about to write, iclass 20, count 0 2006.257.20:52:40.79#ibcon#wrote, iclass 20, count 0 2006.257.20:52:40.79#ibcon#about to read 3, iclass 20, count 0 2006.257.20:52:40.83#ibcon#read 3, iclass 20, count 0 2006.257.20:52:40.83#ibcon#about to read 4, iclass 20, count 0 2006.257.20:52:40.83#ibcon#read 4, iclass 20, count 0 2006.257.20:52:40.83#ibcon#about to read 5, iclass 20, count 0 2006.257.20:52:40.83#ibcon#read 5, iclass 20, count 0 2006.257.20:52:40.83#ibcon#about to read 6, iclass 20, count 0 2006.257.20:52:40.83#ibcon#read 6, iclass 20, count 0 2006.257.20:52:40.83#ibcon#end of sib2, iclass 20, count 0 2006.257.20:52:40.83#ibcon#*after write, iclass 20, count 0 2006.257.20:52:40.83#ibcon#*before return 0, iclass 20, count 0 2006.257.20:52:40.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:40.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.20:52:40.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.20:52:40.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.20:52:40.83$vck44/vb=3,4 2006.257.20:52:40.83#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.20:52:40.83#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.20:52:40.83#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:40.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:40.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:40.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:40.89#ibcon#enter wrdev, iclass 22, count 2 2006.257.20:52:40.89#ibcon#first serial, iclass 22, count 2 2006.257.20:52:40.89#ibcon#enter sib2, iclass 22, count 2 2006.257.20:52:40.89#ibcon#flushed, iclass 22, count 2 2006.257.20:52:40.89#ibcon#about to write, iclass 22, count 2 2006.257.20:52:40.89#ibcon#wrote, iclass 22, count 2 2006.257.20:52:40.89#ibcon#about to read 3, iclass 22, count 2 2006.257.20:52:40.91#ibcon#read 3, iclass 22, count 2 2006.257.20:52:40.91#ibcon#about to read 4, iclass 22, count 2 2006.257.20:52:40.91#ibcon#read 4, iclass 22, count 2 2006.257.20:52:40.91#ibcon#about to read 5, iclass 22, count 2 2006.257.20:52:40.91#ibcon#read 5, iclass 22, count 2 2006.257.20:52:40.91#ibcon#about to read 6, iclass 22, count 2 2006.257.20:52:40.91#ibcon#read 6, iclass 22, count 2 2006.257.20:52:40.91#ibcon#end of sib2, iclass 22, count 2 2006.257.20:52:40.91#ibcon#*mode == 0, iclass 22, count 2 2006.257.20:52:40.91#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.20:52:40.91#ibcon#[27=AT03-04\r\n] 2006.257.20:52:40.91#ibcon#*before write, iclass 22, count 2 2006.257.20:52:40.91#ibcon#enter sib2, iclass 22, count 2 2006.257.20:52:40.91#ibcon#flushed, iclass 22, count 2 2006.257.20:52:40.91#ibcon#about to write, iclass 22, count 2 2006.257.20:52:40.91#ibcon#wrote, iclass 22, count 2 2006.257.20:52:40.91#ibcon#about to read 3, iclass 22, count 2 2006.257.20:52:40.94#ibcon#read 3, iclass 22, count 2 2006.257.20:52:40.94#ibcon#about to read 4, iclass 22, count 2 2006.257.20:52:40.94#ibcon#read 4, iclass 22, count 2 2006.257.20:52:40.94#ibcon#about to read 5, iclass 22, count 2 2006.257.20:52:40.94#ibcon#read 5, iclass 22, count 2 2006.257.20:52:40.94#ibcon#about to read 6, iclass 22, count 2 2006.257.20:52:40.94#ibcon#read 6, iclass 22, count 2 2006.257.20:52:40.94#ibcon#end of sib2, iclass 22, count 2 2006.257.20:52:40.94#ibcon#*after write, iclass 22, count 2 2006.257.20:52:40.94#ibcon#*before return 0, iclass 22, count 2 2006.257.20:52:40.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:40.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.20:52:40.94#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.20:52:40.94#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:40.94#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:41.06#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:41.06#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:41.06#ibcon#enter wrdev, iclass 22, count 0 2006.257.20:52:41.06#ibcon#first serial, iclass 22, count 0 2006.257.20:52:41.06#ibcon#enter sib2, iclass 22, count 0 2006.257.20:52:41.06#ibcon#flushed, iclass 22, count 0 2006.257.20:52:41.06#ibcon#about to write, iclass 22, count 0 2006.257.20:52:41.06#ibcon#wrote, iclass 22, count 0 2006.257.20:52:41.06#ibcon#about to read 3, iclass 22, count 0 2006.257.20:52:41.08#ibcon#read 3, iclass 22, count 0 2006.257.20:52:41.08#ibcon#about to read 4, iclass 22, count 0 2006.257.20:52:41.08#ibcon#read 4, iclass 22, count 0 2006.257.20:52:41.08#ibcon#about to read 5, iclass 22, count 0 2006.257.20:52:41.08#ibcon#read 5, iclass 22, count 0 2006.257.20:52:41.08#ibcon#about to read 6, iclass 22, count 0 2006.257.20:52:41.08#ibcon#read 6, iclass 22, count 0 2006.257.20:52:41.08#ibcon#end of sib2, iclass 22, count 0 2006.257.20:52:41.08#ibcon#*mode == 0, iclass 22, count 0 2006.257.20:52:41.08#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.20:52:41.08#ibcon#[27=USB\r\n] 2006.257.20:52:41.08#ibcon#*before write, iclass 22, count 0 2006.257.20:52:41.08#ibcon#enter sib2, iclass 22, count 0 2006.257.20:52:41.08#ibcon#flushed, iclass 22, count 0 2006.257.20:52:41.08#ibcon#about to write, iclass 22, count 0 2006.257.20:52:41.08#ibcon#wrote, iclass 22, count 0 2006.257.20:52:41.08#ibcon#about to read 3, iclass 22, count 0 2006.257.20:52:41.11#ibcon#read 3, iclass 22, count 0 2006.257.20:52:41.11#ibcon#about to read 4, iclass 22, count 0 2006.257.20:52:41.11#ibcon#read 4, iclass 22, count 0 2006.257.20:52:41.11#ibcon#about to read 5, iclass 22, count 0 2006.257.20:52:41.11#ibcon#read 5, iclass 22, count 0 2006.257.20:52:41.11#ibcon#about to read 6, iclass 22, count 0 2006.257.20:52:41.11#ibcon#read 6, iclass 22, count 0 2006.257.20:52:41.11#ibcon#end of sib2, iclass 22, count 0 2006.257.20:52:41.11#ibcon#*after write, iclass 22, count 0 2006.257.20:52:41.11#ibcon#*before return 0, iclass 22, count 0 2006.257.20:52:41.11#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:41.11#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.20:52:41.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.20:52:41.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.20:52:41.11$vck44/vblo=4,679.99 2006.257.20:52:41.11#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.20:52:41.11#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.20:52:41.11#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:41.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:41.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:41.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:41.11#ibcon#enter wrdev, iclass 24, count 0 2006.257.20:52:41.11#ibcon#first serial, iclass 24, count 0 2006.257.20:52:41.11#ibcon#enter sib2, iclass 24, count 0 2006.257.20:52:41.11#ibcon#flushed, iclass 24, count 0 2006.257.20:52:41.11#ibcon#about to write, iclass 24, count 0 2006.257.20:52:41.11#ibcon#wrote, iclass 24, count 0 2006.257.20:52:41.11#ibcon#about to read 3, iclass 24, count 0 2006.257.20:52:41.13#ibcon#read 3, iclass 24, count 0 2006.257.20:52:41.13#ibcon#about to read 4, iclass 24, count 0 2006.257.20:52:41.13#ibcon#read 4, iclass 24, count 0 2006.257.20:52:41.13#ibcon#about to read 5, iclass 24, count 0 2006.257.20:52:41.13#ibcon#read 5, iclass 24, count 0 2006.257.20:52:41.13#ibcon#about to read 6, iclass 24, count 0 2006.257.20:52:41.13#ibcon#read 6, iclass 24, count 0 2006.257.20:52:41.13#ibcon#end of sib2, iclass 24, count 0 2006.257.20:52:41.13#ibcon#*mode == 0, iclass 24, count 0 2006.257.20:52:41.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.20:52:41.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.20:52:41.13#ibcon#*before write, iclass 24, count 0 2006.257.20:52:41.13#ibcon#enter sib2, iclass 24, count 0 2006.257.20:52:41.13#ibcon#flushed, iclass 24, count 0 2006.257.20:52:41.13#ibcon#about to write, iclass 24, count 0 2006.257.20:52:41.13#ibcon#wrote, iclass 24, count 0 2006.257.20:52:41.13#ibcon#about to read 3, iclass 24, count 0 2006.257.20:52:41.17#ibcon#read 3, iclass 24, count 0 2006.257.20:52:41.17#ibcon#about to read 4, iclass 24, count 0 2006.257.20:52:41.17#ibcon#read 4, iclass 24, count 0 2006.257.20:52:41.17#ibcon#about to read 5, iclass 24, count 0 2006.257.20:52:41.17#ibcon#read 5, iclass 24, count 0 2006.257.20:52:41.17#ibcon#about to read 6, iclass 24, count 0 2006.257.20:52:41.17#ibcon#read 6, iclass 24, count 0 2006.257.20:52:41.17#ibcon#end of sib2, iclass 24, count 0 2006.257.20:52:41.17#ibcon#*after write, iclass 24, count 0 2006.257.20:52:41.17#ibcon#*before return 0, iclass 24, count 0 2006.257.20:52:41.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:41.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.20:52:41.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.20:52:41.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.20:52:41.17$vck44/vb=4,5 2006.257.20:52:41.17#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.20:52:41.17#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.20:52:41.17#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:41.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:41.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:41.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:41.23#ibcon#enter wrdev, iclass 26, count 2 2006.257.20:52:41.23#ibcon#first serial, iclass 26, count 2 2006.257.20:52:41.23#ibcon#enter sib2, iclass 26, count 2 2006.257.20:52:41.23#ibcon#flushed, iclass 26, count 2 2006.257.20:52:41.23#ibcon#about to write, iclass 26, count 2 2006.257.20:52:41.23#ibcon#wrote, iclass 26, count 2 2006.257.20:52:41.23#ibcon#about to read 3, iclass 26, count 2 2006.257.20:52:41.25#ibcon#read 3, iclass 26, count 2 2006.257.20:52:41.25#ibcon#about to read 4, iclass 26, count 2 2006.257.20:52:41.25#ibcon#read 4, iclass 26, count 2 2006.257.20:52:41.25#ibcon#about to read 5, iclass 26, count 2 2006.257.20:52:41.25#ibcon#read 5, iclass 26, count 2 2006.257.20:52:41.25#ibcon#about to read 6, iclass 26, count 2 2006.257.20:52:41.25#ibcon#read 6, iclass 26, count 2 2006.257.20:52:41.25#ibcon#end of sib2, iclass 26, count 2 2006.257.20:52:41.25#ibcon#*mode == 0, iclass 26, count 2 2006.257.20:52:41.25#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.20:52:41.25#ibcon#[27=AT04-05\r\n] 2006.257.20:52:41.25#ibcon#*before write, iclass 26, count 2 2006.257.20:52:41.25#ibcon#enter sib2, iclass 26, count 2 2006.257.20:52:41.25#ibcon#flushed, iclass 26, count 2 2006.257.20:52:41.25#ibcon#about to write, iclass 26, count 2 2006.257.20:52:41.25#ibcon#wrote, iclass 26, count 2 2006.257.20:52:41.25#ibcon#about to read 3, iclass 26, count 2 2006.257.20:52:41.28#ibcon#read 3, iclass 26, count 2 2006.257.20:52:41.28#ibcon#about to read 4, iclass 26, count 2 2006.257.20:52:41.28#ibcon#read 4, iclass 26, count 2 2006.257.20:52:41.28#ibcon#about to read 5, iclass 26, count 2 2006.257.20:52:41.28#ibcon#read 5, iclass 26, count 2 2006.257.20:52:41.28#ibcon#about to read 6, iclass 26, count 2 2006.257.20:52:41.28#ibcon#read 6, iclass 26, count 2 2006.257.20:52:41.28#ibcon#end of sib2, iclass 26, count 2 2006.257.20:52:41.28#ibcon#*after write, iclass 26, count 2 2006.257.20:52:41.28#ibcon#*before return 0, iclass 26, count 2 2006.257.20:52:41.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:41.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.20:52:41.28#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.20:52:41.28#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:41.28#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:41.40#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:41.40#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:41.40#ibcon#enter wrdev, iclass 26, count 0 2006.257.20:52:41.40#ibcon#first serial, iclass 26, count 0 2006.257.20:52:41.40#ibcon#enter sib2, iclass 26, count 0 2006.257.20:52:41.40#ibcon#flushed, iclass 26, count 0 2006.257.20:52:41.40#ibcon#about to write, iclass 26, count 0 2006.257.20:52:41.40#ibcon#wrote, iclass 26, count 0 2006.257.20:52:41.40#ibcon#about to read 3, iclass 26, count 0 2006.257.20:52:41.42#ibcon#read 3, iclass 26, count 0 2006.257.20:52:41.42#ibcon#about to read 4, iclass 26, count 0 2006.257.20:52:41.42#ibcon#read 4, iclass 26, count 0 2006.257.20:52:41.42#ibcon#about to read 5, iclass 26, count 0 2006.257.20:52:41.42#ibcon#read 5, iclass 26, count 0 2006.257.20:52:41.42#ibcon#about to read 6, iclass 26, count 0 2006.257.20:52:41.42#ibcon#read 6, iclass 26, count 0 2006.257.20:52:41.42#ibcon#end of sib2, iclass 26, count 0 2006.257.20:52:41.42#ibcon#*mode == 0, iclass 26, count 0 2006.257.20:52:41.42#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.20:52:41.42#ibcon#[27=USB\r\n] 2006.257.20:52:41.42#ibcon#*before write, iclass 26, count 0 2006.257.20:52:41.42#ibcon#enter sib2, iclass 26, count 0 2006.257.20:52:41.42#ibcon#flushed, iclass 26, count 0 2006.257.20:52:41.42#ibcon#about to write, iclass 26, count 0 2006.257.20:52:41.42#ibcon#wrote, iclass 26, count 0 2006.257.20:52:41.42#ibcon#about to read 3, iclass 26, count 0 2006.257.20:52:41.45#ibcon#read 3, iclass 26, count 0 2006.257.20:52:41.45#ibcon#about to read 4, iclass 26, count 0 2006.257.20:52:41.45#ibcon#read 4, iclass 26, count 0 2006.257.20:52:41.45#ibcon#about to read 5, iclass 26, count 0 2006.257.20:52:41.45#ibcon#read 5, iclass 26, count 0 2006.257.20:52:41.45#ibcon#about to read 6, iclass 26, count 0 2006.257.20:52:41.45#ibcon#read 6, iclass 26, count 0 2006.257.20:52:41.45#ibcon#end of sib2, iclass 26, count 0 2006.257.20:52:41.45#ibcon#*after write, iclass 26, count 0 2006.257.20:52:41.45#ibcon#*before return 0, iclass 26, count 0 2006.257.20:52:41.45#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:41.45#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.20:52:41.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.20:52:41.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.20:52:41.45$vck44/vblo=5,709.99 2006.257.20:52:41.45#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.20:52:41.45#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.20:52:41.45#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:41.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:41.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:41.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:41.45#ibcon#enter wrdev, iclass 28, count 0 2006.257.20:52:41.45#ibcon#first serial, iclass 28, count 0 2006.257.20:52:41.45#ibcon#enter sib2, iclass 28, count 0 2006.257.20:52:41.45#ibcon#flushed, iclass 28, count 0 2006.257.20:52:41.45#ibcon#about to write, iclass 28, count 0 2006.257.20:52:41.45#ibcon#wrote, iclass 28, count 0 2006.257.20:52:41.45#ibcon#about to read 3, iclass 28, count 0 2006.257.20:52:41.47#ibcon#read 3, iclass 28, count 0 2006.257.20:52:41.47#ibcon#about to read 4, iclass 28, count 0 2006.257.20:52:41.47#ibcon#read 4, iclass 28, count 0 2006.257.20:52:41.47#ibcon#about to read 5, iclass 28, count 0 2006.257.20:52:41.47#ibcon#read 5, iclass 28, count 0 2006.257.20:52:41.47#ibcon#about to read 6, iclass 28, count 0 2006.257.20:52:41.47#ibcon#read 6, iclass 28, count 0 2006.257.20:52:41.47#ibcon#end of sib2, iclass 28, count 0 2006.257.20:52:41.47#ibcon#*mode == 0, iclass 28, count 0 2006.257.20:52:41.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.20:52:41.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.20:52:41.47#ibcon#*before write, iclass 28, count 0 2006.257.20:52:41.47#ibcon#enter sib2, iclass 28, count 0 2006.257.20:52:41.47#ibcon#flushed, iclass 28, count 0 2006.257.20:52:41.47#ibcon#about to write, iclass 28, count 0 2006.257.20:52:41.47#ibcon#wrote, iclass 28, count 0 2006.257.20:52:41.47#ibcon#about to read 3, iclass 28, count 0 2006.257.20:52:41.51#ibcon#read 3, iclass 28, count 0 2006.257.20:52:41.51#ibcon#about to read 4, iclass 28, count 0 2006.257.20:52:41.51#ibcon#read 4, iclass 28, count 0 2006.257.20:52:41.51#ibcon#about to read 5, iclass 28, count 0 2006.257.20:52:41.51#ibcon#read 5, iclass 28, count 0 2006.257.20:52:41.51#ibcon#about to read 6, iclass 28, count 0 2006.257.20:52:41.51#ibcon#read 6, iclass 28, count 0 2006.257.20:52:41.51#ibcon#end of sib2, iclass 28, count 0 2006.257.20:52:41.51#ibcon#*after write, iclass 28, count 0 2006.257.20:52:41.51#ibcon#*before return 0, iclass 28, count 0 2006.257.20:52:41.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:41.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.20:52:41.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.20:52:41.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.20:52:41.51$vck44/vb=5,4 2006.257.20:52:41.51#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.20:52:41.51#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.20:52:41.51#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:41.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:41.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:41.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:41.57#ibcon#enter wrdev, iclass 30, count 2 2006.257.20:52:41.57#ibcon#first serial, iclass 30, count 2 2006.257.20:52:41.57#ibcon#enter sib2, iclass 30, count 2 2006.257.20:52:41.57#ibcon#flushed, iclass 30, count 2 2006.257.20:52:41.57#ibcon#about to write, iclass 30, count 2 2006.257.20:52:41.57#ibcon#wrote, iclass 30, count 2 2006.257.20:52:41.57#ibcon#about to read 3, iclass 30, count 2 2006.257.20:52:41.59#ibcon#read 3, iclass 30, count 2 2006.257.20:52:41.59#ibcon#about to read 4, iclass 30, count 2 2006.257.20:52:41.59#ibcon#read 4, iclass 30, count 2 2006.257.20:52:41.59#ibcon#about to read 5, iclass 30, count 2 2006.257.20:52:41.59#ibcon#read 5, iclass 30, count 2 2006.257.20:52:41.59#ibcon#about to read 6, iclass 30, count 2 2006.257.20:52:41.59#ibcon#read 6, iclass 30, count 2 2006.257.20:52:41.59#ibcon#end of sib2, iclass 30, count 2 2006.257.20:52:41.59#ibcon#*mode == 0, iclass 30, count 2 2006.257.20:52:41.59#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.20:52:41.59#ibcon#[27=AT05-04\r\n] 2006.257.20:52:41.59#ibcon#*before write, iclass 30, count 2 2006.257.20:52:41.59#ibcon#enter sib2, iclass 30, count 2 2006.257.20:52:41.59#ibcon#flushed, iclass 30, count 2 2006.257.20:52:41.59#ibcon#about to write, iclass 30, count 2 2006.257.20:52:41.59#ibcon#wrote, iclass 30, count 2 2006.257.20:52:41.59#ibcon#about to read 3, iclass 30, count 2 2006.257.20:52:41.62#ibcon#read 3, iclass 30, count 2 2006.257.20:52:41.62#ibcon#about to read 4, iclass 30, count 2 2006.257.20:52:41.62#ibcon#read 4, iclass 30, count 2 2006.257.20:52:41.62#ibcon#about to read 5, iclass 30, count 2 2006.257.20:52:41.62#ibcon#read 5, iclass 30, count 2 2006.257.20:52:41.62#ibcon#about to read 6, iclass 30, count 2 2006.257.20:52:41.62#ibcon#read 6, iclass 30, count 2 2006.257.20:52:41.62#ibcon#end of sib2, iclass 30, count 2 2006.257.20:52:41.62#ibcon#*after write, iclass 30, count 2 2006.257.20:52:41.62#ibcon#*before return 0, iclass 30, count 2 2006.257.20:52:41.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:41.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.20:52:41.62#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.20:52:41.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:41.62#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:41.74#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:41.74#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:41.74#ibcon#enter wrdev, iclass 30, count 0 2006.257.20:52:41.74#ibcon#first serial, iclass 30, count 0 2006.257.20:52:41.74#ibcon#enter sib2, iclass 30, count 0 2006.257.20:52:41.74#ibcon#flushed, iclass 30, count 0 2006.257.20:52:41.74#ibcon#about to write, iclass 30, count 0 2006.257.20:52:41.74#ibcon#wrote, iclass 30, count 0 2006.257.20:52:41.74#ibcon#about to read 3, iclass 30, count 0 2006.257.20:52:41.76#ibcon#read 3, iclass 30, count 0 2006.257.20:52:41.76#ibcon#about to read 4, iclass 30, count 0 2006.257.20:52:41.76#ibcon#read 4, iclass 30, count 0 2006.257.20:52:41.76#ibcon#about to read 5, iclass 30, count 0 2006.257.20:52:41.76#ibcon#read 5, iclass 30, count 0 2006.257.20:52:41.76#ibcon#about to read 6, iclass 30, count 0 2006.257.20:52:41.76#ibcon#read 6, iclass 30, count 0 2006.257.20:52:41.76#ibcon#end of sib2, iclass 30, count 0 2006.257.20:52:41.76#ibcon#*mode == 0, iclass 30, count 0 2006.257.20:52:41.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.20:52:41.76#ibcon#[27=USB\r\n] 2006.257.20:52:41.76#ibcon#*before write, iclass 30, count 0 2006.257.20:52:41.76#ibcon#enter sib2, iclass 30, count 0 2006.257.20:52:41.76#ibcon#flushed, iclass 30, count 0 2006.257.20:52:41.76#ibcon#about to write, iclass 30, count 0 2006.257.20:52:41.76#ibcon#wrote, iclass 30, count 0 2006.257.20:52:41.76#ibcon#about to read 3, iclass 30, count 0 2006.257.20:52:41.79#ibcon#read 3, iclass 30, count 0 2006.257.20:52:41.79#ibcon#about to read 4, iclass 30, count 0 2006.257.20:52:41.79#ibcon#read 4, iclass 30, count 0 2006.257.20:52:41.79#ibcon#about to read 5, iclass 30, count 0 2006.257.20:52:41.79#ibcon#read 5, iclass 30, count 0 2006.257.20:52:41.79#ibcon#about to read 6, iclass 30, count 0 2006.257.20:52:41.79#ibcon#read 6, iclass 30, count 0 2006.257.20:52:41.79#ibcon#end of sib2, iclass 30, count 0 2006.257.20:52:41.79#ibcon#*after write, iclass 30, count 0 2006.257.20:52:41.79#ibcon#*before return 0, iclass 30, count 0 2006.257.20:52:41.79#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:41.79#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.20:52:41.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.20:52:41.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.20:52:41.79$vck44/vblo=6,719.99 2006.257.20:52:41.79#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.20:52:41.79#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.20:52:41.79#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:41.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:41.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:41.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:41.79#ibcon#enter wrdev, iclass 32, count 0 2006.257.20:52:41.79#ibcon#first serial, iclass 32, count 0 2006.257.20:52:41.79#ibcon#enter sib2, iclass 32, count 0 2006.257.20:52:41.79#ibcon#flushed, iclass 32, count 0 2006.257.20:52:41.79#ibcon#about to write, iclass 32, count 0 2006.257.20:52:41.79#ibcon#wrote, iclass 32, count 0 2006.257.20:52:41.79#ibcon#about to read 3, iclass 32, count 0 2006.257.20:52:41.81#ibcon#read 3, iclass 32, count 0 2006.257.20:52:41.81#ibcon#about to read 4, iclass 32, count 0 2006.257.20:52:41.81#ibcon#read 4, iclass 32, count 0 2006.257.20:52:41.81#ibcon#about to read 5, iclass 32, count 0 2006.257.20:52:41.81#ibcon#read 5, iclass 32, count 0 2006.257.20:52:41.81#ibcon#about to read 6, iclass 32, count 0 2006.257.20:52:41.81#ibcon#read 6, iclass 32, count 0 2006.257.20:52:41.81#ibcon#end of sib2, iclass 32, count 0 2006.257.20:52:41.81#ibcon#*mode == 0, iclass 32, count 0 2006.257.20:52:41.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.20:52:41.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.20:52:41.81#ibcon#*before write, iclass 32, count 0 2006.257.20:52:41.81#ibcon#enter sib2, iclass 32, count 0 2006.257.20:52:41.81#ibcon#flushed, iclass 32, count 0 2006.257.20:52:41.81#ibcon#about to write, iclass 32, count 0 2006.257.20:52:41.81#ibcon#wrote, iclass 32, count 0 2006.257.20:52:41.81#ibcon#about to read 3, iclass 32, count 0 2006.257.20:52:41.85#ibcon#read 3, iclass 32, count 0 2006.257.20:52:41.85#ibcon#about to read 4, iclass 32, count 0 2006.257.20:52:41.85#ibcon#read 4, iclass 32, count 0 2006.257.20:52:41.85#ibcon#about to read 5, iclass 32, count 0 2006.257.20:52:41.85#ibcon#read 5, iclass 32, count 0 2006.257.20:52:41.85#ibcon#about to read 6, iclass 32, count 0 2006.257.20:52:41.85#ibcon#read 6, iclass 32, count 0 2006.257.20:52:41.85#ibcon#end of sib2, iclass 32, count 0 2006.257.20:52:41.85#ibcon#*after write, iclass 32, count 0 2006.257.20:52:41.85#ibcon#*before return 0, iclass 32, count 0 2006.257.20:52:41.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:41.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.20:52:41.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.20:52:41.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.20:52:41.85$vck44/vb=6,4 2006.257.20:52:41.85#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.20:52:41.85#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.20:52:41.85#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:41.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:41.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:41.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:41.91#ibcon#enter wrdev, iclass 34, count 2 2006.257.20:52:41.91#ibcon#first serial, iclass 34, count 2 2006.257.20:52:41.91#ibcon#enter sib2, iclass 34, count 2 2006.257.20:52:41.91#ibcon#flushed, iclass 34, count 2 2006.257.20:52:41.91#ibcon#about to write, iclass 34, count 2 2006.257.20:52:41.91#ibcon#wrote, iclass 34, count 2 2006.257.20:52:41.91#ibcon#about to read 3, iclass 34, count 2 2006.257.20:52:41.93#ibcon#read 3, iclass 34, count 2 2006.257.20:52:41.93#ibcon#about to read 4, iclass 34, count 2 2006.257.20:52:41.93#ibcon#read 4, iclass 34, count 2 2006.257.20:52:41.93#ibcon#about to read 5, iclass 34, count 2 2006.257.20:52:41.93#ibcon#read 5, iclass 34, count 2 2006.257.20:52:41.93#ibcon#about to read 6, iclass 34, count 2 2006.257.20:52:41.93#ibcon#read 6, iclass 34, count 2 2006.257.20:52:41.93#ibcon#end of sib2, iclass 34, count 2 2006.257.20:52:41.93#ibcon#*mode == 0, iclass 34, count 2 2006.257.20:52:41.93#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.20:52:41.93#ibcon#[27=AT06-04\r\n] 2006.257.20:52:41.93#ibcon#*before write, iclass 34, count 2 2006.257.20:52:41.93#ibcon#enter sib2, iclass 34, count 2 2006.257.20:52:41.93#ibcon#flushed, iclass 34, count 2 2006.257.20:52:41.93#ibcon#about to write, iclass 34, count 2 2006.257.20:52:41.93#ibcon#wrote, iclass 34, count 2 2006.257.20:52:41.93#ibcon#about to read 3, iclass 34, count 2 2006.257.20:52:41.96#ibcon#read 3, iclass 34, count 2 2006.257.20:52:41.96#ibcon#about to read 4, iclass 34, count 2 2006.257.20:52:41.96#ibcon#read 4, iclass 34, count 2 2006.257.20:52:41.96#ibcon#about to read 5, iclass 34, count 2 2006.257.20:52:41.96#ibcon#read 5, iclass 34, count 2 2006.257.20:52:41.96#ibcon#about to read 6, iclass 34, count 2 2006.257.20:52:41.96#ibcon#read 6, iclass 34, count 2 2006.257.20:52:41.96#ibcon#end of sib2, iclass 34, count 2 2006.257.20:52:41.96#ibcon#*after write, iclass 34, count 2 2006.257.20:52:41.96#ibcon#*before return 0, iclass 34, count 2 2006.257.20:52:41.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:41.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.20:52:41.96#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.20:52:41.96#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:41.96#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:42.08#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:42.08#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:42.08#ibcon#enter wrdev, iclass 34, count 0 2006.257.20:52:42.08#ibcon#first serial, iclass 34, count 0 2006.257.20:52:42.08#ibcon#enter sib2, iclass 34, count 0 2006.257.20:52:42.08#ibcon#flushed, iclass 34, count 0 2006.257.20:52:42.08#ibcon#about to write, iclass 34, count 0 2006.257.20:52:42.08#ibcon#wrote, iclass 34, count 0 2006.257.20:52:42.08#ibcon#about to read 3, iclass 34, count 0 2006.257.20:52:42.10#ibcon#read 3, iclass 34, count 0 2006.257.20:52:42.10#ibcon#about to read 4, iclass 34, count 0 2006.257.20:52:42.10#ibcon#read 4, iclass 34, count 0 2006.257.20:52:42.10#ibcon#about to read 5, iclass 34, count 0 2006.257.20:52:42.10#ibcon#read 5, iclass 34, count 0 2006.257.20:52:42.10#ibcon#about to read 6, iclass 34, count 0 2006.257.20:52:42.10#ibcon#read 6, iclass 34, count 0 2006.257.20:52:42.10#ibcon#end of sib2, iclass 34, count 0 2006.257.20:52:42.10#ibcon#*mode == 0, iclass 34, count 0 2006.257.20:52:42.10#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.20:52:42.10#ibcon#[27=USB\r\n] 2006.257.20:52:42.10#ibcon#*before write, iclass 34, count 0 2006.257.20:52:42.10#ibcon#enter sib2, iclass 34, count 0 2006.257.20:52:42.10#ibcon#flushed, iclass 34, count 0 2006.257.20:52:42.10#ibcon#about to write, iclass 34, count 0 2006.257.20:52:42.10#ibcon#wrote, iclass 34, count 0 2006.257.20:52:42.10#ibcon#about to read 3, iclass 34, count 0 2006.257.20:52:42.13#ibcon#read 3, iclass 34, count 0 2006.257.20:52:42.13#ibcon#about to read 4, iclass 34, count 0 2006.257.20:52:42.13#ibcon#read 4, iclass 34, count 0 2006.257.20:52:42.13#ibcon#about to read 5, iclass 34, count 0 2006.257.20:52:42.13#ibcon#read 5, iclass 34, count 0 2006.257.20:52:42.13#ibcon#about to read 6, iclass 34, count 0 2006.257.20:52:42.13#ibcon#read 6, iclass 34, count 0 2006.257.20:52:42.13#ibcon#end of sib2, iclass 34, count 0 2006.257.20:52:42.13#ibcon#*after write, iclass 34, count 0 2006.257.20:52:42.13#ibcon#*before return 0, iclass 34, count 0 2006.257.20:52:42.13#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:42.13#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.20:52:42.13#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.20:52:42.13#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.20:52:42.13$vck44/vblo=7,734.99 2006.257.20:52:42.13#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.20:52:42.13#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.20:52:42.13#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:42.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:52:42.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:52:42.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:52:42.13#ibcon#enter wrdev, iclass 36, count 0 2006.257.20:52:42.13#ibcon#first serial, iclass 36, count 0 2006.257.20:52:42.13#ibcon#enter sib2, iclass 36, count 0 2006.257.20:52:42.13#ibcon#flushed, iclass 36, count 0 2006.257.20:52:42.13#ibcon#about to write, iclass 36, count 0 2006.257.20:52:42.13#ibcon#wrote, iclass 36, count 0 2006.257.20:52:42.13#ibcon#about to read 3, iclass 36, count 0 2006.257.20:52:42.15#ibcon#read 3, iclass 36, count 0 2006.257.20:52:42.15#ibcon#about to read 4, iclass 36, count 0 2006.257.20:52:42.15#ibcon#read 4, iclass 36, count 0 2006.257.20:52:42.15#ibcon#about to read 5, iclass 36, count 0 2006.257.20:52:42.15#ibcon#read 5, iclass 36, count 0 2006.257.20:52:42.15#ibcon#about to read 6, iclass 36, count 0 2006.257.20:52:42.15#ibcon#read 6, iclass 36, count 0 2006.257.20:52:42.15#ibcon#end of sib2, iclass 36, count 0 2006.257.20:52:42.15#ibcon#*mode == 0, iclass 36, count 0 2006.257.20:52:42.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.20:52:42.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.20:52:42.15#ibcon#*before write, iclass 36, count 0 2006.257.20:52:42.15#ibcon#enter sib2, iclass 36, count 0 2006.257.20:52:42.15#ibcon#flushed, iclass 36, count 0 2006.257.20:52:42.15#ibcon#about to write, iclass 36, count 0 2006.257.20:52:42.15#ibcon#wrote, iclass 36, count 0 2006.257.20:52:42.15#ibcon#about to read 3, iclass 36, count 0 2006.257.20:52:42.19#ibcon#read 3, iclass 36, count 0 2006.257.20:52:42.19#ibcon#about to read 4, iclass 36, count 0 2006.257.20:52:42.19#ibcon#read 4, iclass 36, count 0 2006.257.20:52:42.19#ibcon#about to read 5, iclass 36, count 0 2006.257.20:52:42.19#ibcon#read 5, iclass 36, count 0 2006.257.20:52:42.19#ibcon#about to read 6, iclass 36, count 0 2006.257.20:52:42.19#ibcon#read 6, iclass 36, count 0 2006.257.20:52:42.19#ibcon#end of sib2, iclass 36, count 0 2006.257.20:52:42.19#ibcon#*after write, iclass 36, count 0 2006.257.20:52:42.19#ibcon#*before return 0, iclass 36, count 0 2006.257.20:52:42.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:52:42.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.20:52:42.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.20:52:42.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.20:52:42.19$vck44/vb=7,4 2006.257.20:52:42.19#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.20:52:42.19#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.20:52:42.19#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:42.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:52:42.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:52:42.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:52:42.25#ibcon#enter wrdev, iclass 38, count 2 2006.257.20:52:42.25#ibcon#first serial, iclass 38, count 2 2006.257.20:52:42.25#ibcon#enter sib2, iclass 38, count 2 2006.257.20:52:42.25#ibcon#flushed, iclass 38, count 2 2006.257.20:52:42.25#ibcon#about to write, iclass 38, count 2 2006.257.20:52:42.25#ibcon#wrote, iclass 38, count 2 2006.257.20:52:42.25#ibcon#about to read 3, iclass 38, count 2 2006.257.20:52:42.27#ibcon#read 3, iclass 38, count 2 2006.257.20:52:42.27#ibcon#about to read 4, iclass 38, count 2 2006.257.20:52:42.27#ibcon#read 4, iclass 38, count 2 2006.257.20:52:42.27#ibcon#about to read 5, iclass 38, count 2 2006.257.20:52:42.27#ibcon#read 5, iclass 38, count 2 2006.257.20:52:42.27#ibcon#about to read 6, iclass 38, count 2 2006.257.20:52:42.27#ibcon#read 6, iclass 38, count 2 2006.257.20:52:42.27#ibcon#end of sib2, iclass 38, count 2 2006.257.20:52:42.27#ibcon#*mode == 0, iclass 38, count 2 2006.257.20:52:42.27#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.20:52:42.27#ibcon#[27=AT07-04\r\n] 2006.257.20:52:42.27#ibcon#*before write, iclass 38, count 2 2006.257.20:52:42.27#ibcon#enter sib2, iclass 38, count 2 2006.257.20:52:42.27#ibcon#flushed, iclass 38, count 2 2006.257.20:52:42.27#ibcon#about to write, iclass 38, count 2 2006.257.20:52:42.27#ibcon#wrote, iclass 38, count 2 2006.257.20:52:42.27#ibcon#about to read 3, iclass 38, count 2 2006.257.20:52:42.30#ibcon#read 3, iclass 38, count 2 2006.257.20:52:42.30#ibcon#about to read 4, iclass 38, count 2 2006.257.20:52:42.30#ibcon#read 4, iclass 38, count 2 2006.257.20:52:42.30#ibcon#about to read 5, iclass 38, count 2 2006.257.20:52:42.30#ibcon#read 5, iclass 38, count 2 2006.257.20:52:42.30#ibcon#about to read 6, iclass 38, count 2 2006.257.20:52:42.30#ibcon#read 6, iclass 38, count 2 2006.257.20:52:42.30#ibcon#end of sib2, iclass 38, count 2 2006.257.20:52:42.30#ibcon#*after write, iclass 38, count 2 2006.257.20:52:42.30#ibcon#*before return 0, iclass 38, count 2 2006.257.20:52:42.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:52:42.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.20:52:42.30#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.20:52:42.30#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:42.30#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:52:42.42#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:52:42.42#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:52:42.42#ibcon#enter wrdev, iclass 38, count 0 2006.257.20:52:42.42#ibcon#first serial, iclass 38, count 0 2006.257.20:52:42.42#ibcon#enter sib2, iclass 38, count 0 2006.257.20:52:42.42#ibcon#flushed, iclass 38, count 0 2006.257.20:52:42.42#ibcon#about to write, iclass 38, count 0 2006.257.20:52:42.42#ibcon#wrote, iclass 38, count 0 2006.257.20:52:42.42#ibcon#about to read 3, iclass 38, count 0 2006.257.20:52:42.44#ibcon#read 3, iclass 38, count 0 2006.257.20:52:42.44#ibcon#about to read 4, iclass 38, count 0 2006.257.20:52:42.44#ibcon#read 4, iclass 38, count 0 2006.257.20:52:42.44#ibcon#about to read 5, iclass 38, count 0 2006.257.20:52:42.44#ibcon#read 5, iclass 38, count 0 2006.257.20:52:42.44#ibcon#about to read 6, iclass 38, count 0 2006.257.20:52:42.44#ibcon#read 6, iclass 38, count 0 2006.257.20:52:42.44#ibcon#end of sib2, iclass 38, count 0 2006.257.20:52:42.44#ibcon#*mode == 0, iclass 38, count 0 2006.257.20:52:42.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.20:52:42.44#ibcon#[27=USB\r\n] 2006.257.20:52:42.44#ibcon#*before write, iclass 38, count 0 2006.257.20:52:42.44#ibcon#enter sib2, iclass 38, count 0 2006.257.20:52:42.44#ibcon#flushed, iclass 38, count 0 2006.257.20:52:42.44#ibcon#about to write, iclass 38, count 0 2006.257.20:52:42.44#ibcon#wrote, iclass 38, count 0 2006.257.20:52:42.44#ibcon#about to read 3, iclass 38, count 0 2006.257.20:52:42.47#ibcon#read 3, iclass 38, count 0 2006.257.20:52:42.47#ibcon#about to read 4, iclass 38, count 0 2006.257.20:52:42.47#ibcon#read 4, iclass 38, count 0 2006.257.20:52:42.47#ibcon#about to read 5, iclass 38, count 0 2006.257.20:52:42.47#ibcon#read 5, iclass 38, count 0 2006.257.20:52:42.47#ibcon#about to read 6, iclass 38, count 0 2006.257.20:52:42.47#ibcon#read 6, iclass 38, count 0 2006.257.20:52:42.47#ibcon#end of sib2, iclass 38, count 0 2006.257.20:52:42.47#ibcon#*after write, iclass 38, count 0 2006.257.20:52:42.47#ibcon#*before return 0, iclass 38, count 0 2006.257.20:52:42.47#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:52:42.47#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.20:52:42.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.20:52:42.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.20:52:42.47$vck44/vblo=8,744.99 2006.257.20:52:42.47#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.20:52:42.47#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.20:52:42.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:52:42.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:42.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:42.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:42.47#ibcon#enter wrdev, iclass 40, count 0 2006.257.20:52:42.47#ibcon#first serial, iclass 40, count 0 2006.257.20:52:42.47#ibcon#enter sib2, iclass 40, count 0 2006.257.20:52:42.47#ibcon#flushed, iclass 40, count 0 2006.257.20:52:42.47#ibcon#about to write, iclass 40, count 0 2006.257.20:52:42.47#ibcon#wrote, iclass 40, count 0 2006.257.20:52:42.47#ibcon#about to read 3, iclass 40, count 0 2006.257.20:52:42.49#ibcon#read 3, iclass 40, count 0 2006.257.20:52:42.49#ibcon#about to read 4, iclass 40, count 0 2006.257.20:52:42.49#ibcon#read 4, iclass 40, count 0 2006.257.20:52:42.49#ibcon#about to read 5, iclass 40, count 0 2006.257.20:52:42.49#ibcon#read 5, iclass 40, count 0 2006.257.20:52:42.49#ibcon#about to read 6, iclass 40, count 0 2006.257.20:52:42.49#ibcon#read 6, iclass 40, count 0 2006.257.20:52:42.49#ibcon#end of sib2, iclass 40, count 0 2006.257.20:52:42.49#ibcon#*mode == 0, iclass 40, count 0 2006.257.20:52:42.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.20:52:42.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.20:52:42.49#ibcon#*before write, iclass 40, count 0 2006.257.20:52:42.49#ibcon#enter sib2, iclass 40, count 0 2006.257.20:52:42.49#ibcon#flushed, iclass 40, count 0 2006.257.20:52:42.49#ibcon#about to write, iclass 40, count 0 2006.257.20:52:42.49#ibcon#wrote, iclass 40, count 0 2006.257.20:52:42.49#ibcon#about to read 3, iclass 40, count 0 2006.257.20:52:42.53#ibcon#read 3, iclass 40, count 0 2006.257.20:52:42.53#ibcon#about to read 4, iclass 40, count 0 2006.257.20:52:42.53#ibcon#read 4, iclass 40, count 0 2006.257.20:52:42.53#ibcon#about to read 5, iclass 40, count 0 2006.257.20:52:42.53#ibcon#read 5, iclass 40, count 0 2006.257.20:52:42.53#ibcon#about to read 6, iclass 40, count 0 2006.257.20:52:42.53#ibcon#read 6, iclass 40, count 0 2006.257.20:52:42.53#ibcon#end of sib2, iclass 40, count 0 2006.257.20:52:42.53#ibcon#*after write, iclass 40, count 0 2006.257.20:52:42.53#ibcon#*before return 0, iclass 40, count 0 2006.257.20:52:42.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:42.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.20:52:42.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.20:52:42.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.20:52:42.53$vck44/vb=8,4 2006.257.20:52:42.53#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.20:52:42.53#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.20:52:42.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:52:42.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:42.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:42.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:42.59#ibcon#enter wrdev, iclass 4, count 2 2006.257.20:52:42.59#ibcon#first serial, iclass 4, count 2 2006.257.20:52:42.59#ibcon#enter sib2, iclass 4, count 2 2006.257.20:52:42.59#ibcon#flushed, iclass 4, count 2 2006.257.20:52:42.59#ibcon#about to write, iclass 4, count 2 2006.257.20:52:42.59#ibcon#wrote, iclass 4, count 2 2006.257.20:52:42.59#ibcon#about to read 3, iclass 4, count 2 2006.257.20:52:42.61#ibcon#read 3, iclass 4, count 2 2006.257.20:52:42.61#ibcon#about to read 4, iclass 4, count 2 2006.257.20:52:42.61#ibcon#read 4, iclass 4, count 2 2006.257.20:52:42.61#ibcon#about to read 5, iclass 4, count 2 2006.257.20:52:42.61#ibcon#read 5, iclass 4, count 2 2006.257.20:52:42.61#ibcon#about to read 6, iclass 4, count 2 2006.257.20:52:42.61#ibcon#read 6, iclass 4, count 2 2006.257.20:52:42.61#ibcon#end of sib2, iclass 4, count 2 2006.257.20:52:42.61#ibcon#*mode == 0, iclass 4, count 2 2006.257.20:52:42.61#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.20:52:42.61#ibcon#[27=AT08-04\r\n] 2006.257.20:52:42.61#ibcon#*before write, iclass 4, count 2 2006.257.20:52:42.61#ibcon#enter sib2, iclass 4, count 2 2006.257.20:52:42.61#ibcon#flushed, iclass 4, count 2 2006.257.20:52:42.61#ibcon#about to write, iclass 4, count 2 2006.257.20:52:42.61#ibcon#wrote, iclass 4, count 2 2006.257.20:52:42.61#ibcon#about to read 3, iclass 4, count 2 2006.257.20:52:42.64#ibcon#read 3, iclass 4, count 2 2006.257.20:52:42.64#ibcon#about to read 4, iclass 4, count 2 2006.257.20:52:42.64#ibcon#read 4, iclass 4, count 2 2006.257.20:52:42.64#ibcon#about to read 5, iclass 4, count 2 2006.257.20:52:42.64#ibcon#read 5, iclass 4, count 2 2006.257.20:52:42.64#ibcon#about to read 6, iclass 4, count 2 2006.257.20:52:42.64#ibcon#read 6, iclass 4, count 2 2006.257.20:52:42.64#ibcon#end of sib2, iclass 4, count 2 2006.257.20:52:42.64#ibcon#*after write, iclass 4, count 2 2006.257.20:52:42.64#ibcon#*before return 0, iclass 4, count 2 2006.257.20:52:42.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:42.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.20:52:42.64#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.20:52:42.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:52:42.64#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:42.76#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:42.76#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:42.76#ibcon#enter wrdev, iclass 4, count 0 2006.257.20:52:42.76#ibcon#first serial, iclass 4, count 0 2006.257.20:52:42.76#ibcon#enter sib2, iclass 4, count 0 2006.257.20:52:42.76#ibcon#flushed, iclass 4, count 0 2006.257.20:52:42.76#ibcon#about to write, iclass 4, count 0 2006.257.20:52:42.76#ibcon#wrote, iclass 4, count 0 2006.257.20:52:42.76#ibcon#about to read 3, iclass 4, count 0 2006.257.20:52:42.78#ibcon#read 3, iclass 4, count 0 2006.257.20:52:42.78#ibcon#about to read 4, iclass 4, count 0 2006.257.20:52:42.78#ibcon#read 4, iclass 4, count 0 2006.257.20:52:42.78#ibcon#about to read 5, iclass 4, count 0 2006.257.20:52:42.78#ibcon#read 5, iclass 4, count 0 2006.257.20:52:42.78#ibcon#about to read 6, iclass 4, count 0 2006.257.20:52:42.78#ibcon#read 6, iclass 4, count 0 2006.257.20:52:42.78#ibcon#end of sib2, iclass 4, count 0 2006.257.20:52:42.78#ibcon#*mode == 0, iclass 4, count 0 2006.257.20:52:42.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.20:52:42.78#ibcon#[27=USB\r\n] 2006.257.20:52:42.78#ibcon#*before write, iclass 4, count 0 2006.257.20:52:42.78#ibcon#enter sib2, iclass 4, count 0 2006.257.20:52:42.78#ibcon#flushed, iclass 4, count 0 2006.257.20:52:42.78#ibcon#about to write, iclass 4, count 0 2006.257.20:52:42.78#ibcon#wrote, iclass 4, count 0 2006.257.20:52:42.78#ibcon#about to read 3, iclass 4, count 0 2006.257.20:52:42.81#ibcon#read 3, iclass 4, count 0 2006.257.20:52:42.81#ibcon#about to read 4, iclass 4, count 0 2006.257.20:52:42.81#ibcon#read 4, iclass 4, count 0 2006.257.20:52:42.81#ibcon#about to read 5, iclass 4, count 0 2006.257.20:52:42.81#ibcon#read 5, iclass 4, count 0 2006.257.20:52:42.81#ibcon#about to read 6, iclass 4, count 0 2006.257.20:52:42.81#ibcon#read 6, iclass 4, count 0 2006.257.20:52:42.81#ibcon#end of sib2, iclass 4, count 0 2006.257.20:52:42.81#ibcon#*after write, iclass 4, count 0 2006.257.20:52:42.81#ibcon#*before return 0, iclass 4, count 0 2006.257.20:52:42.81#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:42.81#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.20:52:42.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.20:52:42.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.20:52:42.81$vck44/vabw=wide 2006.257.20:52:42.81#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.20:52:42.81#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.20:52:42.81#ibcon#ireg 8 cls_cnt 0 2006.257.20:52:42.81#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:42.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:42.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:42.81#ibcon#enter wrdev, iclass 6, count 0 2006.257.20:52:42.81#ibcon#first serial, iclass 6, count 0 2006.257.20:52:42.81#ibcon#enter sib2, iclass 6, count 0 2006.257.20:52:42.81#ibcon#flushed, iclass 6, count 0 2006.257.20:52:42.81#ibcon#about to write, iclass 6, count 0 2006.257.20:52:42.81#ibcon#wrote, iclass 6, count 0 2006.257.20:52:42.81#ibcon#about to read 3, iclass 6, count 0 2006.257.20:52:42.83#ibcon#read 3, iclass 6, count 0 2006.257.20:52:42.83#ibcon#about to read 4, iclass 6, count 0 2006.257.20:52:42.83#ibcon#read 4, iclass 6, count 0 2006.257.20:52:42.83#ibcon#about to read 5, iclass 6, count 0 2006.257.20:52:42.83#ibcon#read 5, iclass 6, count 0 2006.257.20:52:42.83#ibcon#about to read 6, iclass 6, count 0 2006.257.20:52:42.83#ibcon#read 6, iclass 6, count 0 2006.257.20:52:42.83#ibcon#end of sib2, iclass 6, count 0 2006.257.20:52:42.83#ibcon#*mode == 0, iclass 6, count 0 2006.257.20:52:42.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.20:52:42.83#ibcon#[25=BW32\r\n] 2006.257.20:52:42.83#ibcon#*before write, iclass 6, count 0 2006.257.20:52:42.83#ibcon#enter sib2, iclass 6, count 0 2006.257.20:52:42.83#ibcon#flushed, iclass 6, count 0 2006.257.20:52:42.83#ibcon#about to write, iclass 6, count 0 2006.257.20:52:42.83#ibcon#wrote, iclass 6, count 0 2006.257.20:52:42.83#ibcon#about to read 3, iclass 6, count 0 2006.257.20:52:42.86#ibcon#read 3, iclass 6, count 0 2006.257.20:52:42.86#ibcon#about to read 4, iclass 6, count 0 2006.257.20:52:42.86#ibcon#read 4, iclass 6, count 0 2006.257.20:52:42.86#ibcon#about to read 5, iclass 6, count 0 2006.257.20:52:42.86#ibcon#read 5, iclass 6, count 0 2006.257.20:52:42.86#ibcon#about to read 6, iclass 6, count 0 2006.257.20:52:42.86#ibcon#read 6, iclass 6, count 0 2006.257.20:52:42.86#ibcon#end of sib2, iclass 6, count 0 2006.257.20:52:42.86#ibcon#*after write, iclass 6, count 0 2006.257.20:52:42.86#ibcon#*before return 0, iclass 6, count 0 2006.257.20:52:42.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:42.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.20:52:42.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.20:52:42.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.20:52:42.86$vck44/vbbw=wide 2006.257.20:52:42.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.20:52:42.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.20:52:42.86#ibcon#ireg 8 cls_cnt 0 2006.257.20:52:42.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:52:42.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:52:42.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:52:42.93#ibcon#enter wrdev, iclass 10, count 0 2006.257.20:52:42.93#ibcon#first serial, iclass 10, count 0 2006.257.20:52:42.93#ibcon#enter sib2, iclass 10, count 0 2006.257.20:52:42.93#ibcon#flushed, iclass 10, count 0 2006.257.20:52:42.93#ibcon#about to write, iclass 10, count 0 2006.257.20:52:42.93#ibcon#wrote, iclass 10, count 0 2006.257.20:52:42.93#ibcon#about to read 3, iclass 10, count 0 2006.257.20:52:42.95#ibcon#read 3, iclass 10, count 0 2006.257.20:52:42.95#ibcon#about to read 4, iclass 10, count 0 2006.257.20:52:42.95#ibcon#read 4, iclass 10, count 0 2006.257.20:52:42.95#ibcon#about to read 5, iclass 10, count 0 2006.257.20:52:42.95#ibcon#read 5, iclass 10, count 0 2006.257.20:52:42.95#ibcon#about to read 6, iclass 10, count 0 2006.257.20:52:42.95#ibcon#read 6, iclass 10, count 0 2006.257.20:52:42.95#ibcon#end of sib2, iclass 10, count 0 2006.257.20:52:42.95#ibcon#*mode == 0, iclass 10, count 0 2006.257.20:52:42.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.20:52:42.95#ibcon#[27=BW32\r\n] 2006.257.20:52:42.95#ibcon#*before write, iclass 10, count 0 2006.257.20:52:42.95#ibcon#enter sib2, iclass 10, count 0 2006.257.20:52:42.95#ibcon#flushed, iclass 10, count 0 2006.257.20:52:42.95#ibcon#about to write, iclass 10, count 0 2006.257.20:52:42.95#ibcon#wrote, iclass 10, count 0 2006.257.20:52:42.95#ibcon#about to read 3, iclass 10, count 0 2006.257.20:52:42.98#ibcon#read 3, iclass 10, count 0 2006.257.20:52:42.98#ibcon#about to read 4, iclass 10, count 0 2006.257.20:52:42.98#ibcon#read 4, iclass 10, count 0 2006.257.20:52:42.98#ibcon#about to read 5, iclass 10, count 0 2006.257.20:52:42.98#ibcon#read 5, iclass 10, count 0 2006.257.20:52:42.98#ibcon#about to read 6, iclass 10, count 0 2006.257.20:52:42.98#ibcon#read 6, iclass 10, count 0 2006.257.20:52:42.98#ibcon#end of sib2, iclass 10, count 0 2006.257.20:52:42.98#ibcon#*after write, iclass 10, count 0 2006.257.20:52:42.98#ibcon#*before return 0, iclass 10, count 0 2006.257.20:52:42.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:52:42.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.20:52:42.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.20:52:42.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.20:52:42.98$setupk4/ifdk4 2006.257.20:52:42.98$ifdk4/lo= 2006.257.20:52:42.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.20:52:42.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.20:52:42.98$ifdk4/patch= 2006.257.20:52:42.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.20:52:42.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.20:52:42.98$setupk4/!*+20s 2006.257.20:52:49.46#abcon#<5=/14 1.2 2.8 17.33 971015.0\r\n> 2006.257.20:52:49.48#abcon#{5=INTERFACE CLEAR} 2006.257.20:52:49.54#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:52:57.49$setupk4/"tpicd 2006.257.20:52:57.49$setupk4/echo=off 2006.257.20:52:57.49$setupk4/xlog=off 2006.257.20:52:57.49:!2006.257.20:57:35 2006.257.20:54:13.14#trakl#Source acquired 2006.257.20:54:13.14#flagr#flagr/antenna,acquired 2006.257.20:57:35.00:preob 2006.257.20:57:35.14/onsource/TRACKING 2006.257.20:57:35.14:!2006.257.20:57:45 2006.257.20:57:45.00:"tape 2006.257.20:57:45.00:"st=record 2006.257.20:57:45.00:data_valid=on 2006.257.20:57:45.00:midob 2006.257.20:57:46.14/onsource/TRACKING 2006.257.20:57:46.14/wx/17.48,1015.1,96 2006.257.20:57:46.29/cable/+6.4861E-03 2006.257.20:57:47.38/va/01,08,usb,yes,32,34 2006.257.20:57:47.38/va/02,07,usb,yes,34,35 2006.257.20:57:47.38/va/03,08,usb,yes,31,33 2006.257.20:57:47.38/va/04,07,usb,yes,35,37 2006.257.20:57:47.38/va/05,04,usb,yes,32,32 2006.257.20:57:47.38/va/06,04,usb,yes,35,35 2006.257.20:57:47.38/va/07,04,usb,yes,36,36 2006.257.20:57:47.38/va/08,04,usb,yes,30,37 2006.257.20:57:47.61/valo/01,524.99,yes,locked 2006.257.20:57:47.61/valo/02,534.99,yes,locked 2006.257.20:57:47.61/valo/03,564.99,yes,locked 2006.257.20:57:47.61/valo/04,624.99,yes,locked 2006.257.20:57:47.61/valo/05,734.99,yes,locked 2006.257.20:57:47.61/valo/06,814.99,yes,locked 2006.257.20:57:47.61/valo/07,864.99,yes,locked 2006.257.20:57:47.61/valo/08,884.99,yes,locked 2006.257.20:57:48.70/vb/01,04,usb,yes,31,29 2006.257.20:57:48.70/vb/02,05,usb,yes,29,29 2006.257.20:57:48.70/vb/03,04,usb,yes,30,33 2006.257.20:57:48.70/vb/04,05,usb,yes,30,29 2006.257.20:57:48.70/vb/05,04,usb,yes,27,29 2006.257.20:57:48.70/vb/06,04,usb,yes,31,27 2006.257.20:57:48.70/vb/07,04,usb,yes,31,31 2006.257.20:57:48.70/vb/08,04,usb,yes,28,32 2006.257.20:57:48.94/vblo/01,629.99,yes,locked 2006.257.20:57:48.94/vblo/02,634.99,yes,locked 2006.257.20:57:48.94/vblo/03,649.99,yes,locked 2006.257.20:57:48.94/vblo/04,679.99,yes,locked 2006.257.20:57:48.94/vblo/05,709.99,yes,locked 2006.257.20:57:48.94/vblo/06,719.99,yes,locked 2006.257.20:57:48.94/vblo/07,734.99,yes,locked 2006.257.20:57:48.94/vblo/08,744.99,yes,locked 2006.257.20:57:49.09/vabw/8 2006.257.20:57:49.24/vbbw/8 2006.257.20:57:49.33/xfe/off,on,15.2 2006.257.20:57:49.70/ifatt/23,28,28,28 2006.257.20:57:50.08/fmout-gps/S +4.62E-07 2006.257.20:57:50.12:!2006.257.20:59:45 2006.257.20:59:45.00:data_valid=off 2006.257.20:59:45.00:"et 2006.257.20:59:45.00:!+3s 2006.257.20:59:48.02:"tape 2006.257.20:59:48.02:postob 2006.257.20:59:48.15/cable/+6.4866E-03 2006.257.20:59:48.15/wx/17.56,1015.2,96 2006.257.20:59:48.21/fmout-gps/S +4.61E-07 2006.257.20:59:48.21:scan_name=257-2102,jd0609,260 2006.257.20:59:48.21:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.257.20:59:49.13#flagr#flagr/antenna,new-source 2006.257.20:59:49.13:checkk5 2006.257.20:59:49.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.20:59:49.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.20:59:50.15/chk_autoobs//k5ts3/ autoobs is running! 2006.257.20:59:50.48/chk_autoobs//k5ts4/ autoobs is running! 2006.257.20:59:50.82/chk_obsdata//k5ts1/T2572057??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.20:59:51.15/chk_obsdata//k5ts2/T2572057??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.20:59:51.49/chk_obsdata//k5ts3/T2572057??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.20:59:51.82/chk_obsdata//k5ts4/T2572057??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.20:59:52.47/k5log//k5ts1_log_newline 2006.257.20:59:53.13/k5log//k5ts2_log_newline 2006.257.20:59:53.79/k5log//k5ts3_log_newline 2006.257.20:59:54.45/k5log//k5ts4_log_newline 2006.257.20:59:54.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.20:59:54.47:setupk4=1 2006.257.20:59:54.47$setupk4/echo=on 2006.257.20:59:54.47$setupk4/pcalon 2006.257.20:59:54.47$pcalon/"no phase cal control is implemented here 2006.257.20:59:54.47$setupk4/"tpicd=stop 2006.257.20:59:54.47$setupk4/"rec=synch_on 2006.257.20:59:54.47$setupk4/"rec_mode=128 2006.257.20:59:54.47$setupk4/!* 2006.257.20:59:54.47$setupk4/recpk4 2006.257.20:59:54.47$recpk4/recpatch= 2006.257.20:59:54.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.20:59:54.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.20:59:54.48$setupk4/vck44 2006.257.20:59:54.48$vck44/valo=1,524.99 2006.257.20:59:54.48#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.20:59:54.48#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.20:59:54.48#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:54.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:54.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:54.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:54.48#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:59:54.48#ibcon#first serial, iclass 39, count 0 2006.257.20:59:54.48#ibcon#enter sib2, iclass 39, count 0 2006.257.20:59:54.48#ibcon#flushed, iclass 39, count 0 2006.257.20:59:54.48#ibcon#about to write, iclass 39, count 0 2006.257.20:59:54.48#ibcon#wrote, iclass 39, count 0 2006.257.20:59:54.48#ibcon#about to read 3, iclass 39, count 0 2006.257.20:59:54.50#ibcon#read 3, iclass 39, count 0 2006.257.20:59:54.50#ibcon#about to read 4, iclass 39, count 0 2006.257.20:59:54.50#ibcon#read 4, iclass 39, count 0 2006.257.20:59:54.50#ibcon#about to read 5, iclass 39, count 0 2006.257.20:59:54.50#ibcon#read 5, iclass 39, count 0 2006.257.20:59:54.50#ibcon#about to read 6, iclass 39, count 0 2006.257.20:59:54.50#ibcon#read 6, iclass 39, count 0 2006.257.20:59:54.50#ibcon#end of sib2, iclass 39, count 0 2006.257.20:59:54.50#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:59:54.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:59:54.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.20:59:54.50#ibcon#*before write, iclass 39, count 0 2006.257.20:59:54.50#ibcon#enter sib2, iclass 39, count 0 2006.257.20:59:54.50#ibcon#flushed, iclass 39, count 0 2006.257.20:59:54.50#ibcon#about to write, iclass 39, count 0 2006.257.20:59:54.50#ibcon#wrote, iclass 39, count 0 2006.257.20:59:54.50#ibcon#about to read 3, iclass 39, count 0 2006.257.20:59:54.55#ibcon#read 3, iclass 39, count 0 2006.257.20:59:54.55#ibcon#about to read 4, iclass 39, count 0 2006.257.20:59:54.55#ibcon#read 4, iclass 39, count 0 2006.257.20:59:54.55#ibcon#about to read 5, iclass 39, count 0 2006.257.20:59:54.55#ibcon#read 5, iclass 39, count 0 2006.257.20:59:54.55#ibcon#about to read 6, iclass 39, count 0 2006.257.20:59:54.55#ibcon#read 6, iclass 39, count 0 2006.257.20:59:54.55#ibcon#end of sib2, iclass 39, count 0 2006.257.20:59:54.55#ibcon#*after write, iclass 39, count 0 2006.257.20:59:54.55#ibcon#*before return 0, iclass 39, count 0 2006.257.20:59:54.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:54.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:54.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:59:54.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:59:54.55$vck44/va=1,8 2006.257.20:59:54.55#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.20:59:54.55#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.20:59:54.55#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:54.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:54.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:54.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:54.55#ibcon#enter wrdev, iclass 3, count 2 2006.257.20:59:54.55#ibcon#first serial, iclass 3, count 2 2006.257.20:59:54.55#ibcon#enter sib2, iclass 3, count 2 2006.257.20:59:54.55#ibcon#flushed, iclass 3, count 2 2006.257.20:59:54.55#ibcon#about to write, iclass 3, count 2 2006.257.20:59:54.55#ibcon#wrote, iclass 3, count 2 2006.257.20:59:54.55#ibcon#about to read 3, iclass 3, count 2 2006.257.20:59:54.57#ibcon#read 3, iclass 3, count 2 2006.257.20:59:54.57#ibcon#about to read 4, iclass 3, count 2 2006.257.20:59:54.57#ibcon#read 4, iclass 3, count 2 2006.257.20:59:54.57#ibcon#about to read 5, iclass 3, count 2 2006.257.20:59:54.57#ibcon#read 5, iclass 3, count 2 2006.257.20:59:54.57#ibcon#about to read 6, iclass 3, count 2 2006.257.20:59:54.57#ibcon#read 6, iclass 3, count 2 2006.257.20:59:54.57#ibcon#end of sib2, iclass 3, count 2 2006.257.20:59:54.57#ibcon#*mode == 0, iclass 3, count 2 2006.257.20:59:54.57#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.20:59:54.57#ibcon#[25=AT01-08\r\n] 2006.257.20:59:54.57#ibcon#*before write, iclass 3, count 2 2006.257.20:59:54.57#ibcon#enter sib2, iclass 3, count 2 2006.257.20:59:54.57#ibcon#flushed, iclass 3, count 2 2006.257.20:59:54.57#ibcon#about to write, iclass 3, count 2 2006.257.20:59:54.57#ibcon#wrote, iclass 3, count 2 2006.257.20:59:54.57#ibcon#about to read 3, iclass 3, count 2 2006.257.20:59:54.60#ibcon#read 3, iclass 3, count 2 2006.257.20:59:54.60#ibcon#about to read 4, iclass 3, count 2 2006.257.20:59:54.60#ibcon#read 4, iclass 3, count 2 2006.257.20:59:54.60#ibcon#about to read 5, iclass 3, count 2 2006.257.20:59:54.60#ibcon#read 5, iclass 3, count 2 2006.257.20:59:54.60#ibcon#about to read 6, iclass 3, count 2 2006.257.20:59:54.60#ibcon#read 6, iclass 3, count 2 2006.257.20:59:54.60#ibcon#end of sib2, iclass 3, count 2 2006.257.20:59:54.60#ibcon#*after write, iclass 3, count 2 2006.257.20:59:54.60#ibcon#*before return 0, iclass 3, count 2 2006.257.20:59:54.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:54.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:54.60#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.20:59:54.60#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:54.60#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:54.72#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:54.72#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:54.72#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:59:54.72#ibcon#first serial, iclass 3, count 0 2006.257.20:59:54.72#ibcon#enter sib2, iclass 3, count 0 2006.257.20:59:54.72#ibcon#flushed, iclass 3, count 0 2006.257.20:59:54.72#ibcon#about to write, iclass 3, count 0 2006.257.20:59:54.72#ibcon#wrote, iclass 3, count 0 2006.257.20:59:54.72#ibcon#about to read 3, iclass 3, count 0 2006.257.20:59:54.74#ibcon#read 3, iclass 3, count 0 2006.257.20:59:54.74#ibcon#about to read 4, iclass 3, count 0 2006.257.20:59:54.74#ibcon#read 4, iclass 3, count 0 2006.257.20:59:54.74#ibcon#about to read 5, iclass 3, count 0 2006.257.20:59:54.74#ibcon#read 5, iclass 3, count 0 2006.257.20:59:54.74#ibcon#about to read 6, iclass 3, count 0 2006.257.20:59:54.74#ibcon#read 6, iclass 3, count 0 2006.257.20:59:54.74#ibcon#end of sib2, iclass 3, count 0 2006.257.20:59:54.74#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:59:54.74#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:59:54.74#ibcon#[25=USB\r\n] 2006.257.20:59:54.74#ibcon#*before write, iclass 3, count 0 2006.257.20:59:54.74#ibcon#enter sib2, iclass 3, count 0 2006.257.20:59:54.74#ibcon#flushed, iclass 3, count 0 2006.257.20:59:54.74#ibcon#about to write, iclass 3, count 0 2006.257.20:59:54.74#ibcon#wrote, iclass 3, count 0 2006.257.20:59:54.74#ibcon#about to read 3, iclass 3, count 0 2006.257.20:59:54.77#ibcon#read 3, iclass 3, count 0 2006.257.20:59:54.77#ibcon#about to read 4, iclass 3, count 0 2006.257.20:59:54.77#ibcon#read 4, iclass 3, count 0 2006.257.20:59:54.77#ibcon#about to read 5, iclass 3, count 0 2006.257.20:59:54.77#ibcon#read 5, iclass 3, count 0 2006.257.20:59:54.77#ibcon#about to read 6, iclass 3, count 0 2006.257.20:59:54.77#ibcon#read 6, iclass 3, count 0 2006.257.20:59:54.77#ibcon#end of sib2, iclass 3, count 0 2006.257.20:59:54.77#ibcon#*after write, iclass 3, count 0 2006.257.20:59:54.77#ibcon#*before return 0, iclass 3, count 0 2006.257.20:59:54.77#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:54.77#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:54.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:59:54.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:59:54.77$vck44/valo=2,534.99 2006.257.20:59:54.77#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.20:59:54.77#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.20:59:54.77#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:54.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:54.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:54.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:54.77#ibcon#enter wrdev, iclass 5, count 0 2006.257.20:59:54.77#ibcon#first serial, iclass 5, count 0 2006.257.20:59:54.77#ibcon#enter sib2, iclass 5, count 0 2006.257.20:59:54.77#ibcon#flushed, iclass 5, count 0 2006.257.20:59:54.77#ibcon#about to write, iclass 5, count 0 2006.257.20:59:54.77#ibcon#wrote, iclass 5, count 0 2006.257.20:59:54.77#ibcon#about to read 3, iclass 5, count 0 2006.257.20:59:54.79#ibcon#read 3, iclass 5, count 0 2006.257.20:59:54.79#ibcon#about to read 4, iclass 5, count 0 2006.257.20:59:54.79#ibcon#read 4, iclass 5, count 0 2006.257.20:59:54.79#ibcon#about to read 5, iclass 5, count 0 2006.257.20:59:54.79#ibcon#read 5, iclass 5, count 0 2006.257.20:59:54.79#ibcon#about to read 6, iclass 5, count 0 2006.257.20:59:54.79#ibcon#read 6, iclass 5, count 0 2006.257.20:59:54.79#ibcon#end of sib2, iclass 5, count 0 2006.257.20:59:54.79#ibcon#*mode == 0, iclass 5, count 0 2006.257.20:59:54.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.20:59:54.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.20:59:54.79#ibcon#*before write, iclass 5, count 0 2006.257.20:59:54.79#ibcon#enter sib2, iclass 5, count 0 2006.257.20:59:54.79#ibcon#flushed, iclass 5, count 0 2006.257.20:59:54.79#ibcon#about to write, iclass 5, count 0 2006.257.20:59:54.79#ibcon#wrote, iclass 5, count 0 2006.257.20:59:54.79#ibcon#about to read 3, iclass 5, count 0 2006.257.20:59:54.83#ibcon#read 3, iclass 5, count 0 2006.257.20:59:54.83#ibcon#about to read 4, iclass 5, count 0 2006.257.20:59:54.83#ibcon#read 4, iclass 5, count 0 2006.257.20:59:54.83#ibcon#about to read 5, iclass 5, count 0 2006.257.20:59:54.83#ibcon#read 5, iclass 5, count 0 2006.257.20:59:54.83#ibcon#about to read 6, iclass 5, count 0 2006.257.20:59:54.83#ibcon#read 6, iclass 5, count 0 2006.257.20:59:54.83#ibcon#end of sib2, iclass 5, count 0 2006.257.20:59:54.83#ibcon#*after write, iclass 5, count 0 2006.257.20:59:54.83#ibcon#*before return 0, iclass 5, count 0 2006.257.20:59:54.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:54.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:54.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.20:59:54.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.20:59:54.83$vck44/va=2,7 2006.257.20:59:54.83#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.20:59:54.83#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.20:59:54.83#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:54.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:54.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:54.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:54.89#ibcon#enter wrdev, iclass 7, count 2 2006.257.20:59:54.89#ibcon#first serial, iclass 7, count 2 2006.257.20:59:54.89#ibcon#enter sib2, iclass 7, count 2 2006.257.20:59:54.89#ibcon#flushed, iclass 7, count 2 2006.257.20:59:54.89#ibcon#about to write, iclass 7, count 2 2006.257.20:59:54.89#ibcon#wrote, iclass 7, count 2 2006.257.20:59:54.89#ibcon#about to read 3, iclass 7, count 2 2006.257.20:59:54.91#ibcon#read 3, iclass 7, count 2 2006.257.20:59:54.91#ibcon#about to read 4, iclass 7, count 2 2006.257.20:59:54.91#ibcon#read 4, iclass 7, count 2 2006.257.20:59:54.91#ibcon#about to read 5, iclass 7, count 2 2006.257.20:59:54.91#ibcon#read 5, iclass 7, count 2 2006.257.20:59:54.91#ibcon#about to read 6, iclass 7, count 2 2006.257.20:59:54.91#ibcon#read 6, iclass 7, count 2 2006.257.20:59:54.91#ibcon#end of sib2, iclass 7, count 2 2006.257.20:59:54.91#ibcon#*mode == 0, iclass 7, count 2 2006.257.20:59:54.91#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.20:59:54.91#ibcon#[25=AT02-07\r\n] 2006.257.20:59:54.91#ibcon#*before write, iclass 7, count 2 2006.257.20:59:54.91#ibcon#enter sib2, iclass 7, count 2 2006.257.20:59:54.91#ibcon#flushed, iclass 7, count 2 2006.257.20:59:54.91#ibcon#about to write, iclass 7, count 2 2006.257.20:59:54.91#ibcon#wrote, iclass 7, count 2 2006.257.20:59:54.91#ibcon#about to read 3, iclass 7, count 2 2006.257.20:59:54.94#ibcon#read 3, iclass 7, count 2 2006.257.20:59:54.94#ibcon#about to read 4, iclass 7, count 2 2006.257.20:59:54.94#ibcon#read 4, iclass 7, count 2 2006.257.20:59:54.94#ibcon#about to read 5, iclass 7, count 2 2006.257.20:59:54.94#ibcon#read 5, iclass 7, count 2 2006.257.20:59:54.94#ibcon#about to read 6, iclass 7, count 2 2006.257.20:59:54.94#ibcon#read 6, iclass 7, count 2 2006.257.20:59:54.94#ibcon#end of sib2, iclass 7, count 2 2006.257.20:59:54.94#ibcon#*after write, iclass 7, count 2 2006.257.20:59:54.94#ibcon#*before return 0, iclass 7, count 2 2006.257.20:59:54.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:54.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:54.94#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.20:59:54.94#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:54.94#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:55.06#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:55.06#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:55.06#ibcon#enter wrdev, iclass 7, count 0 2006.257.20:59:55.06#ibcon#first serial, iclass 7, count 0 2006.257.20:59:55.06#ibcon#enter sib2, iclass 7, count 0 2006.257.20:59:55.06#ibcon#flushed, iclass 7, count 0 2006.257.20:59:55.06#ibcon#about to write, iclass 7, count 0 2006.257.20:59:55.06#ibcon#wrote, iclass 7, count 0 2006.257.20:59:55.06#ibcon#about to read 3, iclass 7, count 0 2006.257.20:59:55.08#ibcon#read 3, iclass 7, count 0 2006.257.20:59:55.08#ibcon#about to read 4, iclass 7, count 0 2006.257.20:59:55.08#ibcon#read 4, iclass 7, count 0 2006.257.20:59:55.08#ibcon#about to read 5, iclass 7, count 0 2006.257.20:59:55.08#ibcon#read 5, iclass 7, count 0 2006.257.20:59:55.08#ibcon#about to read 6, iclass 7, count 0 2006.257.20:59:55.08#ibcon#read 6, iclass 7, count 0 2006.257.20:59:55.08#ibcon#end of sib2, iclass 7, count 0 2006.257.20:59:55.08#ibcon#*mode == 0, iclass 7, count 0 2006.257.20:59:55.08#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.20:59:55.08#ibcon#[25=USB\r\n] 2006.257.20:59:55.08#ibcon#*before write, iclass 7, count 0 2006.257.20:59:55.08#ibcon#enter sib2, iclass 7, count 0 2006.257.20:59:55.08#ibcon#flushed, iclass 7, count 0 2006.257.20:59:55.08#ibcon#about to write, iclass 7, count 0 2006.257.20:59:55.08#ibcon#wrote, iclass 7, count 0 2006.257.20:59:55.08#ibcon#about to read 3, iclass 7, count 0 2006.257.20:59:55.11#ibcon#read 3, iclass 7, count 0 2006.257.20:59:55.11#ibcon#about to read 4, iclass 7, count 0 2006.257.20:59:55.11#ibcon#read 4, iclass 7, count 0 2006.257.20:59:55.11#ibcon#about to read 5, iclass 7, count 0 2006.257.20:59:55.11#ibcon#read 5, iclass 7, count 0 2006.257.20:59:55.11#ibcon#about to read 6, iclass 7, count 0 2006.257.20:59:55.11#ibcon#read 6, iclass 7, count 0 2006.257.20:59:55.11#ibcon#end of sib2, iclass 7, count 0 2006.257.20:59:55.11#ibcon#*after write, iclass 7, count 0 2006.257.20:59:55.11#ibcon#*before return 0, iclass 7, count 0 2006.257.20:59:55.11#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:55.11#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:55.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.20:59:55.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.20:59:55.11$vck44/valo=3,564.99 2006.257.20:59:55.11#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.20:59:55.11#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.20:59:55.11#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:55.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:55.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:55.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:55.11#ibcon#enter wrdev, iclass 11, count 0 2006.257.20:59:55.11#ibcon#first serial, iclass 11, count 0 2006.257.20:59:55.11#ibcon#enter sib2, iclass 11, count 0 2006.257.20:59:55.11#ibcon#flushed, iclass 11, count 0 2006.257.20:59:55.11#ibcon#about to write, iclass 11, count 0 2006.257.20:59:55.11#ibcon#wrote, iclass 11, count 0 2006.257.20:59:55.11#ibcon#about to read 3, iclass 11, count 0 2006.257.20:59:55.13#ibcon#read 3, iclass 11, count 0 2006.257.20:59:55.13#ibcon#about to read 4, iclass 11, count 0 2006.257.20:59:55.13#ibcon#read 4, iclass 11, count 0 2006.257.20:59:55.13#ibcon#about to read 5, iclass 11, count 0 2006.257.20:59:55.13#ibcon#read 5, iclass 11, count 0 2006.257.20:59:55.13#ibcon#about to read 6, iclass 11, count 0 2006.257.20:59:55.13#ibcon#read 6, iclass 11, count 0 2006.257.20:59:55.13#ibcon#end of sib2, iclass 11, count 0 2006.257.20:59:55.13#ibcon#*mode == 0, iclass 11, count 0 2006.257.20:59:55.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.20:59:55.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.20:59:55.13#ibcon#*before write, iclass 11, count 0 2006.257.20:59:55.13#ibcon#enter sib2, iclass 11, count 0 2006.257.20:59:55.13#ibcon#flushed, iclass 11, count 0 2006.257.20:59:55.13#ibcon#about to write, iclass 11, count 0 2006.257.20:59:55.13#ibcon#wrote, iclass 11, count 0 2006.257.20:59:55.13#ibcon#about to read 3, iclass 11, count 0 2006.257.20:59:55.17#ibcon#read 3, iclass 11, count 0 2006.257.20:59:55.17#ibcon#about to read 4, iclass 11, count 0 2006.257.20:59:55.17#ibcon#read 4, iclass 11, count 0 2006.257.20:59:55.17#ibcon#about to read 5, iclass 11, count 0 2006.257.20:59:55.17#ibcon#read 5, iclass 11, count 0 2006.257.20:59:55.17#ibcon#about to read 6, iclass 11, count 0 2006.257.20:59:55.17#ibcon#read 6, iclass 11, count 0 2006.257.20:59:55.17#ibcon#end of sib2, iclass 11, count 0 2006.257.20:59:55.17#ibcon#*after write, iclass 11, count 0 2006.257.20:59:55.17#ibcon#*before return 0, iclass 11, count 0 2006.257.20:59:55.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:55.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:55.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.20:59:55.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.20:59:55.17$vck44/va=3,8 2006.257.20:59:55.17#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.20:59:55.17#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.20:59:55.17#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:55.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:55.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:55.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:55.23#ibcon#enter wrdev, iclass 13, count 2 2006.257.20:59:55.23#ibcon#first serial, iclass 13, count 2 2006.257.20:59:55.23#ibcon#enter sib2, iclass 13, count 2 2006.257.20:59:55.23#ibcon#flushed, iclass 13, count 2 2006.257.20:59:55.23#ibcon#about to write, iclass 13, count 2 2006.257.20:59:55.23#ibcon#wrote, iclass 13, count 2 2006.257.20:59:55.23#ibcon#about to read 3, iclass 13, count 2 2006.257.20:59:55.25#ibcon#read 3, iclass 13, count 2 2006.257.20:59:55.25#ibcon#about to read 4, iclass 13, count 2 2006.257.20:59:55.25#ibcon#read 4, iclass 13, count 2 2006.257.20:59:55.25#ibcon#about to read 5, iclass 13, count 2 2006.257.20:59:55.25#ibcon#read 5, iclass 13, count 2 2006.257.20:59:55.25#ibcon#about to read 6, iclass 13, count 2 2006.257.20:59:55.25#ibcon#read 6, iclass 13, count 2 2006.257.20:59:55.25#ibcon#end of sib2, iclass 13, count 2 2006.257.20:59:55.25#ibcon#*mode == 0, iclass 13, count 2 2006.257.20:59:55.25#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.20:59:55.25#ibcon#[25=AT03-08\r\n] 2006.257.20:59:55.25#ibcon#*before write, iclass 13, count 2 2006.257.20:59:55.25#ibcon#enter sib2, iclass 13, count 2 2006.257.20:59:55.25#ibcon#flushed, iclass 13, count 2 2006.257.20:59:55.25#ibcon#about to write, iclass 13, count 2 2006.257.20:59:55.25#ibcon#wrote, iclass 13, count 2 2006.257.20:59:55.25#ibcon#about to read 3, iclass 13, count 2 2006.257.20:59:55.28#ibcon#read 3, iclass 13, count 2 2006.257.20:59:55.28#ibcon#about to read 4, iclass 13, count 2 2006.257.20:59:55.28#ibcon#read 4, iclass 13, count 2 2006.257.20:59:55.28#ibcon#about to read 5, iclass 13, count 2 2006.257.20:59:55.28#ibcon#read 5, iclass 13, count 2 2006.257.20:59:55.28#ibcon#about to read 6, iclass 13, count 2 2006.257.20:59:55.28#ibcon#read 6, iclass 13, count 2 2006.257.20:59:55.28#ibcon#end of sib2, iclass 13, count 2 2006.257.20:59:55.28#ibcon#*after write, iclass 13, count 2 2006.257.20:59:55.28#ibcon#*before return 0, iclass 13, count 2 2006.257.20:59:55.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:55.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:55.28#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.20:59:55.28#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:55.28#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:55.40#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:55.40#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:55.40#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:59:55.40#ibcon#first serial, iclass 13, count 0 2006.257.20:59:55.40#ibcon#enter sib2, iclass 13, count 0 2006.257.20:59:55.40#ibcon#flushed, iclass 13, count 0 2006.257.20:59:55.40#ibcon#about to write, iclass 13, count 0 2006.257.20:59:55.40#ibcon#wrote, iclass 13, count 0 2006.257.20:59:55.40#ibcon#about to read 3, iclass 13, count 0 2006.257.20:59:55.42#ibcon#read 3, iclass 13, count 0 2006.257.20:59:55.42#ibcon#about to read 4, iclass 13, count 0 2006.257.20:59:55.42#ibcon#read 4, iclass 13, count 0 2006.257.20:59:55.42#ibcon#about to read 5, iclass 13, count 0 2006.257.20:59:55.42#ibcon#read 5, iclass 13, count 0 2006.257.20:59:55.42#ibcon#about to read 6, iclass 13, count 0 2006.257.20:59:55.42#ibcon#read 6, iclass 13, count 0 2006.257.20:59:55.42#ibcon#end of sib2, iclass 13, count 0 2006.257.20:59:55.42#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:59:55.42#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:59:55.42#ibcon#[25=USB\r\n] 2006.257.20:59:55.42#ibcon#*before write, iclass 13, count 0 2006.257.20:59:55.42#ibcon#enter sib2, iclass 13, count 0 2006.257.20:59:55.42#ibcon#flushed, iclass 13, count 0 2006.257.20:59:55.42#ibcon#about to write, iclass 13, count 0 2006.257.20:59:55.42#ibcon#wrote, iclass 13, count 0 2006.257.20:59:55.42#ibcon#about to read 3, iclass 13, count 0 2006.257.20:59:55.45#ibcon#read 3, iclass 13, count 0 2006.257.20:59:55.45#ibcon#about to read 4, iclass 13, count 0 2006.257.20:59:55.45#ibcon#read 4, iclass 13, count 0 2006.257.20:59:55.45#ibcon#about to read 5, iclass 13, count 0 2006.257.20:59:55.45#ibcon#read 5, iclass 13, count 0 2006.257.20:59:55.45#ibcon#about to read 6, iclass 13, count 0 2006.257.20:59:55.45#ibcon#read 6, iclass 13, count 0 2006.257.20:59:55.45#ibcon#end of sib2, iclass 13, count 0 2006.257.20:59:55.45#ibcon#*after write, iclass 13, count 0 2006.257.20:59:55.45#ibcon#*before return 0, iclass 13, count 0 2006.257.20:59:55.45#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:55.45#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:55.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:59:55.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:59:55.45$vck44/valo=4,624.99 2006.257.20:59:55.45#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.20:59:55.45#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.20:59:55.45#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:55.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:55.45#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:55.45#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:55.45#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:59:55.45#ibcon#first serial, iclass 15, count 0 2006.257.20:59:55.45#ibcon#enter sib2, iclass 15, count 0 2006.257.20:59:55.45#ibcon#flushed, iclass 15, count 0 2006.257.20:59:55.45#ibcon#about to write, iclass 15, count 0 2006.257.20:59:55.45#ibcon#wrote, iclass 15, count 0 2006.257.20:59:55.45#ibcon#about to read 3, iclass 15, count 0 2006.257.20:59:55.47#ibcon#read 3, iclass 15, count 0 2006.257.20:59:55.47#ibcon#about to read 4, iclass 15, count 0 2006.257.20:59:55.47#ibcon#read 4, iclass 15, count 0 2006.257.20:59:55.47#ibcon#about to read 5, iclass 15, count 0 2006.257.20:59:55.47#ibcon#read 5, iclass 15, count 0 2006.257.20:59:55.47#ibcon#about to read 6, iclass 15, count 0 2006.257.20:59:55.47#ibcon#read 6, iclass 15, count 0 2006.257.20:59:55.47#ibcon#end of sib2, iclass 15, count 0 2006.257.20:59:55.47#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:59:55.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:59:55.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.20:59:55.47#ibcon#*before write, iclass 15, count 0 2006.257.20:59:55.47#ibcon#enter sib2, iclass 15, count 0 2006.257.20:59:55.47#ibcon#flushed, iclass 15, count 0 2006.257.20:59:55.47#ibcon#about to write, iclass 15, count 0 2006.257.20:59:55.47#ibcon#wrote, iclass 15, count 0 2006.257.20:59:55.47#ibcon#about to read 3, iclass 15, count 0 2006.257.20:59:55.51#ibcon#read 3, iclass 15, count 0 2006.257.20:59:55.51#ibcon#about to read 4, iclass 15, count 0 2006.257.20:59:55.51#ibcon#read 4, iclass 15, count 0 2006.257.20:59:55.51#ibcon#about to read 5, iclass 15, count 0 2006.257.20:59:55.51#ibcon#read 5, iclass 15, count 0 2006.257.20:59:55.51#ibcon#about to read 6, iclass 15, count 0 2006.257.20:59:55.51#ibcon#read 6, iclass 15, count 0 2006.257.20:59:55.51#ibcon#end of sib2, iclass 15, count 0 2006.257.20:59:55.51#ibcon#*after write, iclass 15, count 0 2006.257.20:59:55.51#ibcon#*before return 0, iclass 15, count 0 2006.257.20:59:55.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:55.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:55.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:59:55.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:59:55.51$vck44/va=4,7 2006.257.20:59:55.51#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.20:59:55.51#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.20:59:55.51#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:55.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:55.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:55.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:55.57#ibcon#enter wrdev, iclass 17, count 2 2006.257.20:59:55.57#ibcon#first serial, iclass 17, count 2 2006.257.20:59:55.57#ibcon#enter sib2, iclass 17, count 2 2006.257.20:59:55.57#ibcon#flushed, iclass 17, count 2 2006.257.20:59:55.57#ibcon#about to write, iclass 17, count 2 2006.257.20:59:55.57#ibcon#wrote, iclass 17, count 2 2006.257.20:59:55.57#ibcon#about to read 3, iclass 17, count 2 2006.257.20:59:55.59#ibcon#read 3, iclass 17, count 2 2006.257.20:59:55.59#ibcon#about to read 4, iclass 17, count 2 2006.257.20:59:55.59#ibcon#read 4, iclass 17, count 2 2006.257.20:59:55.59#ibcon#about to read 5, iclass 17, count 2 2006.257.20:59:55.59#ibcon#read 5, iclass 17, count 2 2006.257.20:59:55.59#ibcon#about to read 6, iclass 17, count 2 2006.257.20:59:55.59#ibcon#read 6, iclass 17, count 2 2006.257.20:59:55.59#ibcon#end of sib2, iclass 17, count 2 2006.257.20:59:55.59#ibcon#*mode == 0, iclass 17, count 2 2006.257.20:59:55.59#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.20:59:55.59#ibcon#[25=AT04-07\r\n] 2006.257.20:59:55.59#ibcon#*before write, iclass 17, count 2 2006.257.20:59:55.59#ibcon#enter sib2, iclass 17, count 2 2006.257.20:59:55.59#ibcon#flushed, iclass 17, count 2 2006.257.20:59:55.59#ibcon#about to write, iclass 17, count 2 2006.257.20:59:55.59#ibcon#wrote, iclass 17, count 2 2006.257.20:59:55.59#ibcon#about to read 3, iclass 17, count 2 2006.257.20:59:55.62#ibcon#read 3, iclass 17, count 2 2006.257.20:59:55.62#ibcon#about to read 4, iclass 17, count 2 2006.257.20:59:55.62#ibcon#read 4, iclass 17, count 2 2006.257.20:59:55.62#ibcon#about to read 5, iclass 17, count 2 2006.257.20:59:55.62#ibcon#read 5, iclass 17, count 2 2006.257.20:59:55.62#ibcon#about to read 6, iclass 17, count 2 2006.257.20:59:55.62#ibcon#read 6, iclass 17, count 2 2006.257.20:59:55.62#ibcon#end of sib2, iclass 17, count 2 2006.257.20:59:55.62#ibcon#*after write, iclass 17, count 2 2006.257.20:59:55.62#ibcon#*before return 0, iclass 17, count 2 2006.257.20:59:55.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:55.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:55.62#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.20:59:55.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:55.62#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:55.74#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:55.74#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:55.74#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:59:55.74#ibcon#first serial, iclass 17, count 0 2006.257.20:59:55.74#ibcon#enter sib2, iclass 17, count 0 2006.257.20:59:55.74#ibcon#flushed, iclass 17, count 0 2006.257.20:59:55.74#ibcon#about to write, iclass 17, count 0 2006.257.20:59:55.74#ibcon#wrote, iclass 17, count 0 2006.257.20:59:55.74#ibcon#about to read 3, iclass 17, count 0 2006.257.20:59:55.76#ibcon#read 3, iclass 17, count 0 2006.257.20:59:55.76#ibcon#about to read 4, iclass 17, count 0 2006.257.20:59:55.76#ibcon#read 4, iclass 17, count 0 2006.257.20:59:55.76#ibcon#about to read 5, iclass 17, count 0 2006.257.20:59:55.76#ibcon#read 5, iclass 17, count 0 2006.257.20:59:55.76#ibcon#about to read 6, iclass 17, count 0 2006.257.20:59:55.76#ibcon#read 6, iclass 17, count 0 2006.257.20:59:55.76#ibcon#end of sib2, iclass 17, count 0 2006.257.20:59:55.76#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:59:55.76#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:59:55.76#ibcon#[25=USB\r\n] 2006.257.20:59:55.76#ibcon#*before write, iclass 17, count 0 2006.257.20:59:55.76#ibcon#enter sib2, iclass 17, count 0 2006.257.20:59:55.76#ibcon#flushed, iclass 17, count 0 2006.257.20:59:55.76#ibcon#about to write, iclass 17, count 0 2006.257.20:59:55.76#ibcon#wrote, iclass 17, count 0 2006.257.20:59:55.76#ibcon#about to read 3, iclass 17, count 0 2006.257.20:59:55.79#ibcon#read 3, iclass 17, count 0 2006.257.20:59:55.79#ibcon#about to read 4, iclass 17, count 0 2006.257.20:59:55.79#ibcon#read 4, iclass 17, count 0 2006.257.20:59:55.79#ibcon#about to read 5, iclass 17, count 0 2006.257.20:59:55.79#ibcon#read 5, iclass 17, count 0 2006.257.20:59:55.79#ibcon#about to read 6, iclass 17, count 0 2006.257.20:59:55.79#ibcon#read 6, iclass 17, count 0 2006.257.20:59:55.79#ibcon#end of sib2, iclass 17, count 0 2006.257.20:59:55.79#ibcon#*after write, iclass 17, count 0 2006.257.20:59:55.79#ibcon#*before return 0, iclass 17, count 0 2006.257.20:59:55.79#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:55.79#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:55.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:59:55.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:59:55.79$vck44/valo=5,734.99 2006.257.20:59:55.79#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.20:59:55.79#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.20:59:55.79#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:55.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:55.79#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:55.79#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:55.79#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:59:55.79#ibcon#first serial, iclass 19, count 0 2006.257.20:59:55.79#ibcon#enter sib2, iclass 19, count 0 2006.257.20:59:55.79#ibcon#flushed, iclass 19, count 0 2006.257.20:59:55.79#ibcon#about to write, iclass 19, count 0 2006.257.20:59:55.79#ibcon#wrote, iclass 19, count 0 2006.257.20:59:55.79#ibcon#about to read 3, iclass 19, count 0 2006.257.20:59:55.81#ibcon#read 3, iclass 19, count 0 2006.257.20:59:55.81#ibcon#about to read 4, iclass 19, count 0 2006.257.20:59:55.81#ibcon#read 4, iclass 19, count 0 2006.257.20:59:55.81#ibcon#about to read 5, iclass 19, count 0 2006.257.20:59:55.81#ibcon#read 5, iclass 19, count 0 2006.257.20:59:55.81#ibcon#about to read 6, iclass 19, count 0 2006.257.20:59:55.81#ibcon#read 6, iclass 19, count 0 2006.257.20:59:55.81#ibcon#end of sib2, iclass 19, count 0 2006.257.20:59:55.81#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:59:55.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:59:55.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.20:59:55.81#ibcon#*before write, iclass 19, count 0 2006.257.20:59:55.81#ibcon#enter sib2, iclass 19, count 0 2006.257.20:59:55.81#ibcon#flushed, iclass 19, count 0 2006.257.20:59:55.81#ibcon#about to write, iclass 19, count 0 2006.257.20:59:55.81#ibcon#wrote, iclass 19, count 0 2006.257.20:59:55.81#ibcon#about to read 3, iclass 19, count 0 2006.257.20:59:55.85#ibcon#read 3, iclass 19, count 0 2006.257.20:59:55.85#ibcon#about to read 4, iclass 19, count 0 2006.257.20:59:55.85#ibcon#read 4, iclass 19, count 0 2006.257.20:59:55.85#ibcon#about to read 5, iclass 19, count 0 2006.257.20:59:55.85#ibcon#read 5, iclass 19, count 0 2006.257.20:59:55.85#ibcon#about to read 6, iclass 19, count 0 2006.257.20:59:55.85#ibcon#read 6, iclass 19, count 0 2006.257.20:59:55.85#ibcon#end of sib2, iclass 19, count 0 2006.257.20:59:55.85#ibcon#*after write, iclass 19, count 0 2006.257.20:59:55.85#ibcon#*before return 0, iclass 19, count 0 2006.257.20:59:55.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:55.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:55.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:59:55.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:59:55.85$vck44/va=5,4 2006.257.20:59:55.85#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.20:59:55.85#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.20:59:55.85#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:55.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:55.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:55.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:55.91#ibcon#enter wrdev, iclass 21, count 2 2006.257.20:59:55.91#ibcon#first serial, iclass 21, count 2 2006.257.20:59:55.91#ibcon#enter sib2, iclass 21, count 2 2006.257.20:59:55.91#ibcon#flushed, iclass 21, count 2 2006.257.20:59:55.91#ibcon#about to write, iclass 21, count 2 2006.257.20:59:55.91#ibcon#wrote, iclass 21, count 2 2006.257.20:59:55.91#ibcon#about to read 3, iclass 21, count 2 2006.257.20:59:55.93#ibcon#read 3, iclass 21, count 2 2006.257.20:59:55.93#ibcon#about to read 4, iclass 21, count 2 2006.257.20:59:55.93#ibcon#read 4, iclass 21, count 2 2006.257.20:59:55.93#ibcon#about to read 5, iclass 21, count 2 2006.257.20:59:55.93#ibcon#read 5, iclass 21, count 2 2006.257.20:59:55.93#ibcon#about to read 6, iclass 21, count 2 2006.257.20:59:55.93#ibcon#read 6, iclass 21, count 2 2006.257.20:59:55.93#ibcon#end of sib2, iclass 21, count 2 2006.257.20:59:55.93#ibcon#*mode == 0, iclass 21, count 2 2006.257.20:59:55.93#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.20:59:55.93#ibcon#[25=AT05-04\r\n] 2006.257.20:59:55.93#ibcon#*before write, iclass 21, count 2 2006.257.20:59:55.93#ibcon#enter sib2, iclass 21, count 2 2006.257.20:59:55.93#ibcon#flushed, iclass 21, count 2 2006.257.20:59:55.93#ibcon#about to write, iclass 21, count 2 2006.257.20:59:55.93#ibcon#wrote, iclass 21, count 2 2006.257.20:59:55.93#ibcon#about to read 3, iclass 21, count 2 2006.257.20:59:55.96#ibcon#read 3, iclass 21, count 2 2006.257.20:59:55.96#ibcon#about to read 4, iclass 21, count 2 2006.257.20:59:55.96#ibcon#read 4, iclass 21, count 2 2006.257.20:59:55.96#ibcon#about to read 5, iclass 21, count 2 2006.257.20:59:55.96#ibcon#read 5, iclass 21, count 2 2006.257.20:59:55.96#ibcon#about to read 6, iclass 21, count 2 2006.257.20:59:55.96#ibcon#read 6, iclass 21, count 2 2006.257.20:59:55.96#ibcon#end of sib2, iclass 21, count 2 2006.257.20:59:55.96#ibcon#*after write, iclass 21, count 2 2006.257.20:59:55.96#ibcon#*before return 0, iclass 21, count 2 2006.257.20:59:55.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:55.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:55.96#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.20:59:55.96#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:55.96#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:56.08#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:56.08#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:56.08#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:59:56.08#ibcon#first serial, iclass 21, count 0 2006.257.20:59:56.08#ibcon#enter sib2, iclass 21, count 0 2006.257.20:59:56.08#ibcon#flushed, iclass 21, count 0 2006.257.20:59:56.08#ibcon#about to write, iclass 21, count 0 2006.257.20:59:56.08#ibcon#wrote, iclass 21, count 0 2006.257.20:59:56.08#ibcon#about to read 3, iclass 21, count 0 2006.257.20:59:56.10#ibcon#read 3, iclass 21, count 0 2006.257.20:59:56.10#ibcon#about to read 4, iclass 21, count 0 2006.257.20:59:56.10#ibcon#read 4, iclass 21, count 0 2006.257.20:59:56.10#ibcon#about to read 5, iclass 21, count 0 2006.257.20:59:56.10#ibcon#read 5, iclass 21, count 0 2006.257.20:59:56.10#ibcon#about to read 6, iclass 21, count 0 2006.257.20:59:56.10#ibcon#read 6, iclass 21, count 0 2006.257.20:59:56.10#ibcon#end of sib2, iclass 21, count 0 2006.257.20:59:56.10#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:59:56.10#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:59:56.10#ibcon#[25=USB\r\n] 2006.257.20:59:56.10#ibcon#*before write, iclass 21, count 0 2006.257.20:59:56.10#ibcon#enter sib2, iclass 21, count 0 2006.257.20:59:56.10#ibcon#flushed, iclass 21, count 0 2006.257.20:59:56.10#ibcon#about to write, iclass 21, count 0 2006.257.20:59:56.10#ibcon#wrote, iclass 21, count 0 2006.257.20:59:56.10#ibcon#about to read 3, iclass 21, count 0 2006.257.20:59:56.13#ibcon#read 3, iclass 21, count 0 2006.257.20:59:56.13#ibcon#about to read 4, iclass 21, count 0 2006.257.20:59:56.13#ibcon#read 4, iclass 21, count 0 2006.257.20:59:56.13#ibcon#about to read 5, iclass 21, count 0 2006.257.20:59:56.13#ibcon#read 5, iclass 21, count 0 2006.257.20:59:56.13#ibcon#about to read 6, iclass 21, count 0 2006.257.20:59:56.13#ibcon#read 6, iclass 21, count 0 2006.257.20:59:56.13#ibcon#end of sib2, iclass 21, count 0 2006.257.20:59:56.13#ibcon#*after write, iclass 21, count 0 2006.257.20:59:56.13#ibcon#*before return 0, iclass 21, count 0 2006.257.20:59:56.13#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:56.13#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:56.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:59:56.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:59:56.13$vck44/valo=6,814.99 2006.257.20:59:56.13#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.20:59:56.13#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.20:59:56.13#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:56.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:56.13#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:56.13#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:56.13#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:59:56.13#ibcon#first serial, iclass 23, count 0 2006.257.20:59:56.13#ibcon#enter sib2, iclass 23, count 0 2006.257.20:59:56.13#ibcon#flushed, iclass 23, count 0 2006.257.20:59:56.13#ibcon#about to write, iclass 23, count 0 2006.257.20:59:56.13#ibcon#wrote, iclass 23, count 0 2006.257.20:59:56.13#ibcon#about to read 3, iclass 23, count 0 2006.257.20:59:56.15#ibcon#read 3, iclass 23, count 0 2006.257.20:59:56.15#ibcon#about to read 4, iclass 23, count 0 2006.257.20:59:56.15#ibcon#read 4, iclass 23, count 0 2006.257.20:59:56.15#ibcon#about to read 5, iclass 23, count 0 2006.257.20:59:56.15#ibcon#read 5, iclass 23, count 0 2006.257.20:59:56.15#ibcon#about to read 6, iclass 23, count 0 2006.257.20:59:56.15#ibcon#read 6, iclass 23, count 0 2006.257.20:59:56.15#ibcon#end of sib2, iclass 23, count 0 2006.257.20:59:56.15#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:59:56.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:59:56.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.20:59:56.15#ibcon#*before write, iclass 23, count 0 2006.257.20:59:56.15#ibcon#enter sib2, iclass 23, count 0 2006.257.20:59:56.15#ibcon#flushed, iclass 23, count 0 2006.257.20:59:56.15#ibcon#about to write, iclass 23, count 0 2006.257.20:59:56.15#ibcon#wrote, iclass 23, count 0 2006.257.20:59:56.15#ibcon#about to read 3, iclass 23, count 0 2006.257.20:59:56.19#ibcon#read 3, iclass 23, count 0 2006.257.20:59:56.19#ibcon#about to read 4, iclass 23, count 0 2006.257.20:59:56.19#ibcon#read 4, iclass 23, count 0 2006.257.20:59:56.19#ibcon#about to read 5, iclass 23, count 0 2006.257.20:59:56.19#ibcon#read 5, iclass 23, count 0 2006.257.20:59:56.19#ibcon#about to read 6, iclass 23, count 0 2006.257.20:59:56.19#ibcon#read 6, iclass 23, count 0 2006.257.20:59:56.19#ibcon#end of sib2, iclass 23, count 0 2006.257.20:59:56.19#ibcon#*after write, iclass 23, count 0 2006.257.20:59:56.19#ibcon#*before return 0, iclass 23, count 0 2006.257.20:59:56.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:56.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:56.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:59:56.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:59:56.19$vck44/va=6,4 2006.257.20:59:56.19#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.20:59:56.19#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.20:59:56.19#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:56.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:56.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:56.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:56.25#ibcon#enter wrdev, iclass 25, count 2 2006.257.20:59:56.25#ibcon#first serial, iclass 25, count 2 2006.257.20:59:56.25#ibcon#enter sib2, iclass 25, count 2 2006.257.20:59:56.25#ibcon#flushed, iclass 25, count 2 2006.257.20:59:56.25#ibcon#about to write, iclass 25, count 2 2006.257.20:59:56.25#ibcon#wrote, iclass 25, count 2 2006.257.20:59:56.25#ibcon#about to read 3, iclass 25, count 2 2006.257.20:59:56.27#ibcon#read 3, iclass 25, count 2 2006.257.20:59:56.27#ibcon#about to read 4, iclass 25, count 2 2006.257.20:59:56.27#ibcon#read 4, iclass 25, count 2 2006.257.20:59:56.27#ibcon#about to read 5, iclass 25, count 2 2006.257.20:59:56.27#ibcon#read 5, iclass 25, count 2 2006.257.20:59:56.27#ibcon#about to read 6, iclass 25, count 2 2006.257.20:59:56.27#ibcon#read 6, iclass 25, count 2 2006.257.20:59:56.27#ibcon#end of sib2, iclass 25, count 2 2006.257.20:59:56.27#ibcon#*mode == 0, iclass 25, count 2 2006.257.20:59:56.27#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.20:59:56.27#ibcon#[25=AT06-04\r\n] 2006.257.20:59:56.27#ibcon#*before write, iclass 25, count 2 2006.257.20:59:56.27#ibcon#enter sib2, iclass 25, count 2 2006.257.20:59:56.27#ibcon#flushed, iclass 25, count 2 2006.257.20:59:56.27#ibcon#about to write, iclass 25, count 2 2006.257.20:59:56.27#ibcon#wrote, iclass 25, count 2 2006.257.20:59:56.27#ibcon#about to read 3, iclass 25, count 2 2006.257.20:59:56.30#ibcon#read 3, iclass 25, count 2 2006.257.20:59:56.30#ibcon#about to read 4, iclass 25, count 2 2006.257.20:59:56.30#ibcon#read 4, iclass 25, count 2 2006.257.20:59:56.30#ibcon#about to read 5, iclass 25, count 2 2006.257.20:59:56.30#ibcon#read 5, iclass 25, count 2 2006.257.20:59:56.30#ibcon#about to read 6, iclass 25, count 2 2006.257.20:59:56.30#ibcon#read 6, iclass 25, count 2 2006.257.20:59:56.30#ibcon#end of sib2, iclass 25, count 2 2006.257.20:59:56.30#ibcon#*after write, iclass 25, count 2 2006.257.20:59:56.30#ibcon#*before return 0, iclass 25, count 2 2006.257.20:59:56.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:56.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:56.30#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.20:59:56.30#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:56.30#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:56.42#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:56.42#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:56.42#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:59:56.42#ibcon#first serial, iclass 25, count 0 2006.257.20:59:56.42#ibcon#enter sib2, iclass 25, count 0 2006.257.20:59:56.42#ibcon#flushed, iclass 25, count 0 2006.257.20:59:56.42#ibcon#about to write, iclass 25, count 0 2006.257.20:59:56.42#ibcon#wrote, iclass 25, count 0 2006.257.20:59:56.42#ibcon#about to read 3, iclass 25, count 0 2006.257.20:59:56.44#ibcon#read 3, iclass 25, count 0 2006.257.20:59:56.44#ibcon#about to read 4, iclass 25, count 0 2006.257.20:59:56.44#ibcon#read 4, iclass 25, count 0 2006.257.20:59:56.44#ibcon#about to read 5, iclass 25, count 0 2006.257.20:59:56.44#ibcon#read 5, iclass 25, count 0 2006.257.20:59:56.44#ibcon#about to read 6, iclass 25, count 0 2006.257.20:59:56.44#ibcon#read 6, iclass 25, count 0 2006.257.20:59:56.44#ibcon#end of sib2, iclass 25, count 0 2006.257.20:59:56.44#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:59:56.44#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:59:56.44#ibcon#[25=USB\r\n] 2006.257.20:59:56.44#ibcon#*before write, iclass 25, count 0 2006.257.20:59:56.44#ibcon#enter sib2, iclass 25, count 0 2006.257.20:59:56.44#ibcon#flushed, iclass 25, count 0 2006.257.20:59:56.44#ibcon#about to write, iclass 25, count 0 2006.257.20:59:56.44#ibcon#wrote, iclass 25, count 0 2006.257.20:59:56.44#ibcon#about to read 3, iclass 25, count 0 2006.257.20:59:56.47#ibcon#read 3, iclass 25, count 0 2006.257.20:59:56.47#ibcon#about to read 4, iclass 25, count 0 2006.257.20:59:56.47#ibcon#read 4, iclass 25, count 0 2006.257.20:59:56.47#ibcon#about to read 5, iclass 25, count 0 2006.257.20:59:56.47#ibcon#read 5, iclass 25, count 0 2006.257.20:59:56.47#ibcon#about to read 6, iclass 25, count 0 2006.257.20:59:56.47#ibcon#read 6, iclass 25, count 0 2006.257.20:59:56.47#ibcon#end of sib2, iclass 25, count 0 2006.257.20:59:56.47#ibcon#*after write, iclass 25, count 0 2006.257.20:59:56.47#ibcon#*before return 0, iclass 25, count 0 2006.257.20:59:56.47#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:56.47#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:56.47#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:59:56.47#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:59:56.47$vck44/valo=7,864.99 2006.257.20:59:56.47#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.20:59:56.47#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.20:59:56.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:56.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:56.47#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:56.47#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:56.47#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:59:56.47#ibcon#first serial, iclass 27, count 0 2006.257.20:59:56.47#ibcon#enter sib2, iclass 27, count 0 2006.257.20:59:56.47#ibcon#flushed, iclass 27, count 0 2006.257.20:59:56.47#ibcon#about to write, iclass 27, count 0 2006.257.20:59:56.47#ibcon#wrote, iclass 27, count 0 2006.257.20:59:56.47#ibcon#about to read 3, iclass 27, count 0 2006.257.20:59:56.49#ibcon#read 3, iclass 27, count 0 2006.257.20:59:56.49#ibcon#about to read 4, iclass 27, count 0 2006.257.20:59:56.49#ibcon#read 4, iclass 27, count 0 2006.257.20:59:56.49#ibcon#about to read 5, iclass 27, count 0 2006.257.20:59:56.49#ibcon#read 5, iclass 27, count 0 2006.257.20:59:56.49#ibcon#about to read 6, iclass 27, count 0 2006.257.20:59:56.49#ibcon#read 6, iclass 27, count 0 2006.257.20:59:56.49#ibcon#end of sib2, iclass 27, count 0 2006.257.20:59:56.49#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:59:56.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:59:56.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.20:59:56.49#ibcon#*before write, iclass 27, count 0 2006.257.20:59:56.49#ibcon#enter sib2, iclass 27, count 0 2006.257.20:59:56.49#ibcon#flushed, iclass 27, count 0 2006.257.20:59:56.49#ibcon#about to write, iclass 27, count 0 2006.257.20:59:56.49#ibcon#wrote, iclass 27, count 0 2006.257.20:59:56.49#ibcon#about to read 3, iclass 27, count 0 2006.257.20:59:56.53#ibcon#read 3, iclass 27, count 0 2006.257.20:59:56.53#ibcon#about to read 4, iclass 27, count 0 2006.257.20:59:56.53#ibcon#read 4, iclass 27, count 0 2006.257.20:59:56.53#ibcon#about to read 5, iclass 27, count 0 2006.257.20:59:56.53#ibcon#read 5, iclass 27, count 0 2006.257.20:59:56.53#ibcon#about to read 6, iclass 27, count 0 2006.257.20:59:56.53#ibcon#read 6, iclass 27, count 0 2006.257.20:59:56.53#ibcon#end of sib2, iclass 27, count 0 2006.257.20:59:56.53#ibcon#*after write, iclass 27, count 0 2006.257.20:59:56.53#ibcon#*before return 0, iclass 27, count 0 2006.257.20:59:56.53#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:56.53#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:56.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:59:56.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:59:56.53$vck44/va=7,4 2006.257.20:59:56.53#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.20:59:56.53#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.20:59:56.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:56.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:56.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:56.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:56.59#ibcon#enter wrdev, iclass 29, count 2 2006.257.20:59:56.59#ibcon#first serial, iclass 29, count 2 2006.257.20:59:56.59#ibcon#enter sib2, iclass 29, count 2 2006.257.20:59:56.59#ibcon#flushed, iclass 29, count 2 2006.257.20:59:56.59#ibcon#about to write, iclass 29, count 2 2006.257.20:59:56.59#ibcon#wrote, iclass 29, count 2 2006.257.20:59:56.59#ibcon#about to read 3, iclass 29, count 2 2006.257.20:59:56.61#ibcon#read 3, iclass 29, count 2 2006.257.20:59:56.61#ibcon#about to read 4, iclass 29, count 2 2006.257.20:59:56.61#ibcon#read 4, iclass 29, count 2 2006.257.20:59:56.61#ibcon#about to read 5, iclass 29, count 2 2006.257.20:59:56.61#ibcon#read 5, iclass 29, count 2 2006.257.20:59:56.61#ibcon#about to read 6, iclass 29, count 2 2006.257.20:59:56.61#ibcon#read 6, iclass 29, count 2 2006.257.20:59:56.61#ibcon#end of sib2, iclass 29, count 2 2006.257.20:59:56.61#ibcon#*mode == 0, iclass 29, count 2 2006.257.20:59:56.61#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.20:59:56.61#ibcon#[25=AT07-04\r\n] 2006.257.20:59:56.61#ibcon#*before write, iclass 29, count 2 2006.257.20:59:56.61#ibcon#enter sib2, iclass 29, count 2 2006.257.20:59:56.61#ibcon#flushed, iclass 29, count 2 2006.257.20:59:56.61#ibcon#about to write, iclass 29, count 2 2006.257.20:59:56.61#ibcon#wrote, iclass 29, count 2 2006.257.20:59:56.61#ibcon#about to read 3, iclass 29, count 2 2006.257.20:59:56.64#ibcon#read 3, iclass 29, count 2 2006.257.20:59:56.64#ibcon#about to read 4, iclass 29, count 2 2006.257.20:59:56.64#ibcon#read 4, iclass 29, count 2 2006.257.20:59:56.64#ibcon#about to read 5, iclass 29, count 2 2006.257.20:59:56.64#ibcon#read 5, iclass 29, count 2 2006.257.20:59:56.64#ibcon#about to read 6, iclass 29, count 2 2006.257.20:59:56.64#ibcon#read 6, iclass 29, count 2 2006.257.20:59:56.64#ibcon#end of sib2, iclass 29, count 2 2006.257.20:59:56.64#ibcon#*after write, iclass 29, count 2 2006.257.20:59:56.64#ibcon#*before return 0, iclass 29, count 2 2006.257.20:59:56.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:56.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:56.64#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.20:59:56.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:56.64#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:56.69#abcon#<5=/14 0.9 2.4 17.57 961015.2\r\n> 2006.257.20:59:56.71#abcon#{5=INTERFACE CLEAR} 2006.257.20:59:56.76#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:56.76#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:56.76#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:59:56.76#ibcon#first serial, iclass 29, count 0 2006.257.20:59:56.76#ibcon#enter sib2, iclass 29, count 0 2006.257.20:59:56.76#ibcon#flushed, iclass 29, count 0 2006.257.20:59:56.76#ibcon#about to write, iclass 29, count 0 2006.257.20:59:56.76#ibcon#wrote, iclass 29, count 0 2006.257.20:59:56.76#ibcon#about to read 3, iclass 29, count 0 2006.257.20:59:56.77#abcon#[5=S1D000X0/0*\r\n] 2006.257.20:59:56.78#ibcon#read 3, iclass 29, count 0 2006.257.20:59:56.78#ibcon#about to read 4, iclass 29, count 0 2006.257.20:59:56.78#ibcon#read 4, iclass 29, count 0 2006.257.20:59:56.78#ibcon#about to read 5, iclass 29, count 0 2006.257.20:59:56.78#ibcon#read 5, iclass 29, count 0 2006.257.20:59:56.78#ibcon#about to read 6, iclass 29, count 0 2006.257.20:59:56.78#ibcon#read 6, iclass 29, count 0 2006.257.20:59:56.78#ibcon#end of sib2, iclass 29, count 0 2006.257.20:59:56.78#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:59:56.78#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:59:56.78#ibcon#[25=USB\r\n] 2006.257.20:59:56.78#ibcon#*before write, iclass 29, count 0 2006.257.20:59:56.78#ibcon#enter sib2, iclass 29, count 0 2006.257.20:59:56.78#ibcon#flushed, iclass 29, count 0 2006.257.20:59:56.78#ibcon#about to write, iclass 29, count 0 2006.257.20:59:56.78#ibcon#wrote, iclass 29, count 0 2006.257.20:59:56.78#ibcon#about to read 3, iclass 29, count 0 2006.257.20:59:56.81#ibcon#read 3, iclass 29, count 0 2006.257.20:59:56.81#ibcon#about to read 4, iclass 29, count 0 2006.257.20:59:56.81#ibcon#read 4, iclass 29, count 0 2006.257.20:59:56.81#ibcon#about to read 5, iclass 29, count 0 2006.257.20:59:56.81#ibcon#read 5, iclass 29, count 0 2006.257.20:59:56.81#ibcon#about to read 6, iclass 29, count 0 2006.257.20:59:56.81#ibcon#read 6, iclass 29, count 0 2006.257.20:59:56.81#ibcon#end of sib2, iclass 29, count 0 2006.257.20:59:56.81#ibcon#*after write, iclass 29, count 0 2006.257.20:59:56.81#ibcon#*before return 0, iclass 29, count 0 2006.257.20:59:56.81#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:56.81#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:56.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:59:56.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:59:56.81$vck44/valo=8,884.99 2006.257.20:59:56.81#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.20:59:56.81#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.20:59:56.81#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:56.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:56.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:56.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:56.81#ibcon#enter wrdev, iclass 35, count 0 2006.257.20:59:56.81#ibcon#first serial, iclass 35, count 0 2006.257.20:59:56.81#ibcon#enter sib2, iclass 35, count 0 2006.257.20:59:56.81#ibcon#flushed, iclass 35, count 0 2006.257.20:59:56.81#ibcon#about to write, iclass 35, count 0 2006.257.20:59:56.81#ibcon#wrote, iclass 35, count 0 2006.257.20:59:56.81#ibcon#about to read 3, iclass 35, count 0 2006.257.20:59:56.83#ibcon#read 3, iclass 35, count 0 2006.257.20:59:56.83#ibcon#about to read 4, iclass 35, count 0 2006.257.20:59:56.83#ibcon#read 4, iclass 35, count 0 2006.257.20:59:56.83#ibcon#about to read 5, iclass 35, count 0 2006.257.20:59:56.83#ibcon#read 5, iclass 35, count 0 2006.257.20:59:56.83#ibcon#about to read 6, iclass 35, count 0 2006.257.20:59:56.83#ibcon#read 6, iclass 35, count 0 2006.257.20:59:56.83#ibcon#end of sib2, iclass 35, count 0 2006.257.20:59:56.83#ibcon#*mode == 0, iclass 35, count 0 2006.257.20:59:56.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.20:59:56.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.20:59:56.83#ibcon#*before write, iclass 35, count 0 2006.257.20:59:56.83#ibcon#enter sib2, iclass 35, count 0 2006.257.20:59:56.83#ibcon#flushed, iclass 35, count 0 2006.257.20:59:56.83#ibcon#about to write, iclass 35, count 0 2006.257.20:59:56.83#ibcon#wrote, iclass 35, count 0 2006.257.20:59:56.83#ibcon#about to read 3, iclass 35, count 0 2006.257.20:59:56.87#ibcon#read 3, iclass 35, count 0 2006.257.20:59:56.87#ibcon#about to read 4, iclass 35, count 0 2006.257.20:59:56.87#ibcon#read 4, iclass 35, count 0 2006.257.20:59:56.87#ibcon#about to read 5, iclass 35, count 0 2006.257.20:59:56.87#ibcon#read 5, iclass 35, count 0 2006.257.20:59:56.87#ibcon#about to read 6, iclass 35, count 0 2006.257.20:59:56.87#ibcon#read 6, iclass 35, count 0 2006.257.20:59:56.87#ibcon#end of sib2, iclass 35, count 0 2006.257.20:59:56.87#ibcon#*after write, iclass 35, count 0 2006.257.20:59:56.87#ibcon#*before return 0, iclass 35, count 0 2006.257.20:59:56.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:56.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:56.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.20:59:56.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.20:59:56.87$vck44/va=8,4 2006.257.20:59:56.87#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.20:59:56.87#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.20:59:56.87#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:56.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:59:56.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:59:56.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:59:56.93#ibcon#enter wrdev, iclass 37, count 2 2006.257.20:59:56.93#ibcon#first serial, iclass 37, count 2 2006.257.20:59:56.93#ibcon#enter sib2, iclass 37, count 2 2006.257.20:59:56.93#ibcon#flushed, iclass 37, count 2 2006.257.20:59:56.93#ibcon#about to write, iclass 37, count 2 2006.257.20:59:56.93#ibcon#wrote, iclass 37, count 2 2006.257.20:59:56.93#ibcon#about to read 3, iclass 37, count 2 2006.257.20:59:56.95#ibcon#read 3, iclass 37, count 2 2006.257.20:59:56.95#ibcon#about to read 4, iclass 37, count 2 2006.257.20:59:56.95#ibcon#read 4, iclass 37, count 2 2006.257.20:59:56.95#ibcon#about to read 5, iclass 37, count 2 2006.257.20:59:56.95#ibcon#read 5, iclass 37, count 2 2006.257.20:59:56.95#ibcon#about to read 6, iclass 37, count 2 2006.257.20:59:56.95#ibcon#read 6, iclass 37, count 2 2006.257.20:59:56.95#ibcon#end of sib2, iclass 37, count 2 2006.257.20:59:56.95#ibcon#*mode == 0, iclass 37, count 2 2006.257.20:59:56.95#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.20:59:56.95#ibcon#[25=AT08-04\r\n] 2006.257.20:59:56.95#ibcon#*before write, iclass 37, count 2 2006.257.20:59:56.95#ibcon#enter sib2, iclass 37, count 2 2006.257.20:59:56.95#ibcon#flushed, iclass 37, count 2 2006.257.20:59:56.95#ibcon#about to write, iclass 37, count 2 2006.257.20:59:56.95#ibcon#wrote, iclass 37, count 2 2006.257.20:59:56.95#ibcon#about to read 3, iclass 37, count 2 2006.257.20:59:56.98#ibcon#read 3, iclass 37, count 2 2006.257.20:59:56.98#ibcon#about to read 4, iclass 37, count 2 2006.257.20:59:56.98#ibcon#read 4, iclass 37, count 2 2006.257.20:59:56.98#ibcon#about to read 5, iclass 37, count 2 2006.257.20:59:56.98#ibcon#read 5, iclass 37, count 2 2006.257.20:59:56.98#ibcon#about to read 6, iclass 37, count 2 2006.257.20:59:56.98#ibcon#read 6, iclass 37, count 2 2006.257.20:59:56.98#ibcon#end of sib2, iclass 37, count 2 2006.257.20:59:56.98#ibcon#*after write, iclass 37, count 2 2006.257.20:59:56.98#ibcon#*before return 0, iclass 37, count 2 2006.257.20:59:56.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:59:56.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.20:59:56.98#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.20:59:56.98#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:56.98#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:59:57.10#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:59:57.10#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:59:57.10#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:59:57.10#ibcon#first serial, iclass 37, count 0 2006.257.20:59:57.10#ibcon#enter sib2, iclass 37, count 0 2006.257.20:59:57.10#ibcon#flushed, iclass 37, count 0 2006.257.20:59:57.10#ibcon#about to write, iclass 37, count 0 2006.257.20:59:57.10#ibcon#wrote, iclass 37, count 0 2006.257.20:59:57.10#ibcon#about to read 3, iclass 37, count 0 2006.257.20:59:57.12#ibcon#read 3, iclass 37, count 0 2006.257.20:59:57.12#ibcon#about to read 4, iclass 37, count 0 2006.257.20:59:57.12#ibcon#read 4, iclass 37, count 0 2006.257.20:59:57.12#ibcon#about to read 5, iclass 37, count 0 2006.257.20:59:57.12#ibcon#read 5, iclass 37, count 0 2006.257.20:59:57.12#ibcon#about to read 6, iclass 37, count 0 2006.257.20:59:57.12#ibcon#read 6, iclass 37, count 0 2006.257.20:59:57.12#ibcon#end of sib2, iclass 37, count 0 2006.257.20:59:57.12#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:59:57.12#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:59:57.12#ibcon#[25=USB\r\n] 2006.257.20:59:57.12#ibcon#*before write, iclass 37, count 0 2006.257.20:59:57.12#ibcon#enter sib2, iclass 37, count 0 2006.257.20:59:57.12#ibcon#flushed, iclass 37, count 0 2006.257.20:59:57.12#ibcon#about to write, iclass 37, count 0 2006.257.20:59:57.12#ibcon#wrote, iclass 37, count 0 2006.257.20:59:57.12#ibcon#about to read 3, iclass 37, count 0 2006.257.20:59:57.15#ibcon#read 3, iclass 37, count 0 2006.257.20:59:57.15#ibcon#about to read 4, iclass 37, count 0 2006.257.20:59:57.15#ibcon#read 4, iclass 37, count 0 2006.257.20:59:57.15#ibcon#about to read 5, iclass 37, count 0 2006.257.20:59:57.15#ibcon#read 5, iclass 37, count 0 2006.257.20:59:57.15#ibcon#about to read 6, iclass 37, count 0 2006.257.20:59:57.15#ibcon#read 6, iclass 37, count 0 2006.257.20:59:57.15#ibcon#end of sib2, iclass 37, count 0 2006.257.20:59:57.15#ibcon#*after write, iclass 37, count 0 2006.257.20:59:57.15#ibcon#*before return 0, iclass 37, count 0 2006.257.20:59:57.15#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:59:57.15#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.20:59:57.15#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:59:57.15#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:59:57.15$vck44/vblo=1,629.99 2006.257.20:59:57.15#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.20:59:57.15#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.20:59:57.15#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:57.15#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:57.15#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:57.15#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:57.15#ibcon#enter wrdev, iclass 39, count 0 2006.257.20:59:57.15#ibcon#first serial, iclass 39, count 0 2006.257.20:59:57.15#ibcon#enter sib2, iclass 39, count 0 2006.257.20:59:57.15#ibcon#flushed, iclass 39, count 0 2006.257.20:59:57.15#ibcon#about to write, iclass 39, count 0 2006.257.20:59:57.15#ibcon#wrote, iclass 39, count 0 2006.257.20:59:57.15#ibcon#about to read 3, iclass 39, count 0 2006.257.20:59:57.17#ibcon#read 3, iclass 39, count 0 2006.257.20:59:57.17#ibcon#about to read 4, iclass 39, count 0 2006.257.20:59:57.17#ibcon#read 4, iclass 39, count 0 2006.257.20:59:57.17#ibcon#about to read 5, iclass 39, count 0 2006.257.20:59:57.17#ibcon#read 5, iclass 39, count 0 2006.257.20:59:57.17#ibcon#about to read 6, iclass 39, count 0 2006.257.20:59:57.17#ibcon#read 6, iclass 39, count 0 2006.257.20:59:57.17#ibcon#end of sib2, iclass 39, count 0 2006.257.20:59:57.17#ibcon#*mode == 0, iclass 39, count 0 2006.257.20:59:57.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.20:59:57.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.20:59:57.17#ibcon#*before write, iclass 39, count 0 2006.257.20:59:57.17#ibcon#enter sib2, iclass 39, count 0 2006.257.20:59:57.17#ibcon#flushed, iclass 39, count 0 2006.257.20:59:57.17#ibcon#about to write, iclass 39, count 0 2006.257.20:59:57.17#ibcon#wrote, iclass 39, count 0 2006.257.20:59:57.17#ibcon#about to read 3, iclass 39, count 0 2006.257.20:59:57.21#ibcon#read 3, iclass 39, count 0 2006.257.20:59:57.21#ibcon#about to read 4, iclass 39, count 0 2006.257.20:59:57.21#ibcon#read 4, iclass 39, count 0 2006.257.20:59:57.21#ibcon#about to read 5, iclass 39, count 0 2006.257.20:59:57.21#ibcon#read 5, iclass 39, count 0 2006.257.20:59:57.21#ibcon#about to read 6, iclass 39, count 0 2006.257.20:59:57.21#ibcon#read 6, iclass 39, count 0 2006.257.20:59:57.21#ibcon#end of sib2, iclass 39, count 0 2006.257.20:59:57.21#ibcon#*after write, iclass 39, count 0 2006.257.20:59:57.21#ibcon#*before return 0, iclass 39, count 0 2006.257.20:59:57.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:57.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.20:59:57.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.20:59:57.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.20:59:57.21$vck44/vb=1,4 2006.257.20:59:57.21#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.20:59:57.21#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.20:59:57.21#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:57.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:57.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:57.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:57.21#ibcon#enter wrdev, iclass 3, count 2 2006.257.20:59:57.21#ibcon#first serial, iclass 3, count 2 2006.257.20:59:57.21#ibcon#enter sib2, iclass 3, count 2 2006.257.20:59:57.21#ibcon#flushed, iclass 3, count 2 2006.257.20:59:57.21#ibcon#about to write, iclass 3, count 2 2006.257.20:59:57.21#ibcon#wrote, iclass 3, count 2 2006.257.20:59:57.21#ibcon#about to read 3, iclass 3, count 2 2006.257.20:59:57.23#ibcon#read 3, iclass 3, count 2 2006.257.20:59:57.23#ibcon#about to read 4, iclass 3, count 2 2006.257.20:59:57.23#ibcon#read 4, iclass 3, count 2 2006.257.20:59:57.23#ibcon#about to read 5, iclass 3, count 2 2006.257.20:59:57.23#ibcon#read 5, iclass 3, count 2 2006.257.20:59:57.23#ibcon#about to read 6, iclass 3, count 2 2006.257.20:59:57.23#ibcon#read 6, iclass 3, count 2 2006.257.20:59:57.23#ibcon#end of sib2, iclass 3, count 2 2006.257.20:59:57.23#ibcon#*mode == 0, iclass 3, count 2 2006.257.20:59:57.23#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.20:59:57.23#ibcon#[27=AT01-04\r\n] 2006.257.20:59:57.23#ibcon#*before write, iclass 3, count 2 2006.257.20:59:57.23#ibcon#enter sib2, iclass 3, count 2 2006.257.20:59:57.23#ibcon#flushed, iclass 3, count 2 2006.257.20:59:57.23#ibcon#about to write, iclass 3, count 2 2006.257.20:59:57.23#ibcon#wrote, iclass 3, count 2 2006.257.20:59:57.23#ibcon#about to read 3, iclass 3, count 2 2006.257.20:59:57.26#ibcon#read 3, iclass 3, count 2 2006.257.20:59:57.26#ibcon#about to read 4, iclass 3, count 2 2006.257.20:59:57.26#ibcon#read 4, iclass 3, count 2 2006.257.20:59:57.26#ibcon#about to read 5, iclass 3, count 2 2006.257.20:59:57.26#ibcon#read 5, iclass 3, count 2 2006.257.20:59:57.26#ibcon#about to read 6, iclass 3, count 2 2006.257.20:59:57.26#ibcon#read 6, iclass 3, count 2 2006.257.20:59:57.26#ibcon#end of sib2, iclass 3, count 2 2006.257.20:59:57.26#ibcon#*after write, iclass 3, count 2 2006.257.20:59:57.26#ibcon#*before return 0, iclass 3, count 2 2006.257.20:59:57.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:57.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.20:59:57.26#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.20:59:57.26#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:57.26#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:57.38#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:57.38#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:57.38#ibcon#enter wrdev, iclass 3, count 0 2006.257.20:59:57.38#ibcon#first serial, iclass 3, count 0 2006.257.20:59:57.38#ibcon#enter sib2, iclass 3, count 0 2006.257.20:59:57.38#ibcon#flushed, iclass 3, count 0 2006.257.20:59:57.38#ibcon#about to write, iclass 3, count 0 2006.257.20:59:57.38#ibcon#wrote, iclass 3, count 0 2006.257.20:59:57.38#ibcon#about to read 3, iclass 3, count 0 2006.257.20:59:57.40#ibcon#read 3, iclass 3, count 0 2006.257.20:59:57.40#ibcon#about to read 4, iclass 3, count 0 2006.257.20:59:57.40#ibcon#read 4, iclass 3, count 0 2006.257.20:59:57.40#ibcon#about to read 5, iclass 3, count 0 2006.257.20:59:57.40#ibcon#read 5, iclass 3, count 0 2006.257.20:59:57.40#ibcon#about to read 6, iclass 3, count 0 2006.257.20:59:57.40#ibcon#read 6, iclass 3, count 0 2006.257.20:59:57.40#ibcon#end of sib2, iclass 3, count 0 2006.257.20:59:57.40#ibcon#*mode == 0, iclass 3, count 0 2006.257.20:59:57.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.20:59:57.40#ibcon#[27=USB\r\n] 2006.257.20:59:57.40#ibcon#*before write, iclass 3, count 0 2006.257.20:59:57.40#ibcon#enter sib2, iclass 3, count 0 2006.257.20:59:57.40#ibcon#flushed, iclass 3, count 0 2006.257.20:59:57.40#ibcon#about to write, iclass 3, count 0 2006.257.20:59:57.40#ibcon#wrote, iclass 3, count 0 2006.257.20:59:57.40#ibcon#about to read 3, iclass 3, count 0 2006.257.20:59:57.43#ibcon#read 3, iclass 3, count 0 2006.257.20:59:57.43#ibcon#about to read 4, iclass 3, count 0 2006.257.20:59:57.43#ibcon#read 4, iclass 3, count 0 2006.257.20:59:57.43#ibcon#about to read 5, iclass 3, count 0 2006.257.20:59:57.43#ibcon#read 5, iclass 3, count 0 2006.257.20:59:57.43#ibcon#about to read 6, iclass 3, count 0 2006.257.20:59:57.43#ibcon#read 6, iclass 3, count 0 2006.257.20:59:57.43#ibcon#end of sib2, iclass 3, count 0 2006.257.20:59:57.43#ibcon#*after write, iclass 3, count 0 2006.257.20:59:57.43#ibcon#*before return 0, iclass 3, count 0 2006.257.20:59:57.43#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:57.43#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.20:59:57.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.20:59:57.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.20:59:57.43$vck44/vblo=2,634.99 2006.257.20:59:57.43#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.20:59:57.43#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.20:59:57.43#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:57.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:57.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:57.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:57.43#ibcon#enter wrdev, iclass 5, count 0 2006.257.20:59:57.43#ibcon#first serial, iclass 5, count 0 2006.257.20:59:57.43#ibcon#enter sib2, iclass 5, count 0 2006.257.20:59:57.43#ibcon#flushed, iclass 5, count 0 2006.257.20:59:57.43#ibcon#about to write, iclass 5, count 0 2006.257.20:59:57.43#ibcon#wrote, iclass 5, count 0 2006.257.20:59:57.43#ibcon#about to read 3, iclass 5, count 0 2006.257.20:59:57.45#ibcon#read 3, iclass 5, count 0 2006.257.20:59:57.45#ibcon#about to read 4, iclass 5, count 0 2006.257.20:59:57.45#ibcon#read 4, iclass 5, count 0 2006.257.20:59:57.45#ibcon#about to read 5, iclass 5, count 0 2006.257.20:59:57.45#ibcon#read 5, iclass 5, count 0 2006.257.20:59:57.45#ibcon#about to read 6, iclass 5, count 0 2006.257.20:59:57.45#ibcon#read 6, iclass 5, count 0 2006.257.20:59:57.45#ibcon#end of sib2, iclass 5, count 0 2006.257.20:59:57.45#ibcon#*mode == 0, iclass 5, count 0 2006.257.20:59:57.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.20:59:57.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.20:59:57.45#ibcon#*before write, iclass 5, count 0 2006.257.20:59:57.45#ibcon#enter sib2, iclass 5, count 0 2006.257.20:59:57.45#ibcon#flushed, iclass 5, count 0 2006.257.20:59:57.45#ibcon#about to write, iclass 5, count 0 2006.257.20:59:57.45#ibcon#wrote, iclass 5, count 0 2006.257.20:59:57.45#ibcon#about to read 3, iclass 5, count 0 2006.257.20:59:57.49#ibcon#read 3, iclass 5, count 0 2006.257.20:59:57.49#ibcon#about to read 4, iclass 5, count 0 2006.257.20:59:57.49#ibcon#read 4, iclass 5, count 0 2006.257.20:59:57.49#ibcon#about to read 5, iclass 5, count 0 2006.257.20:59:57.49#ibcon#read 5, iclass 5, count 0 2006.257.20:59:57.49#ibcon#about to read 6, iclass 5, count 0 2006.257.20:59:57.49#ibcon#read 6, iclass 5, count 0 2006.257.20:59:57.49#ibcon#end of sib2, iclass 5, count 0 2006.257.20:59:57.49#ibcon#*after write, iclass 5, count 0 2006.257.20:59:57.49#ibcon#*before return 0, iclass 5, count 0 2006.257.20:59:57.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:57.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.20:59:57.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.20:59:57.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.20:59:57.49$vck44/vb=2,5 2006.257.20:59:57.49#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.20:59:57.49#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.20:59:57.49#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:57.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:57.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:57.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:57.55#ibcon#enter wrdev, iclass 7, count 2 2006.257.20:59:57.55#ibcon#first serial, iclass 7, count 2 2006.257.20:59:57.55#ibcon#enter sib2, iclass 7, count 2 2006.257.20:59:57.55#ibcon#flushed, iclass 7, count 2 2006.257.20:59:57.55#ibcon#about to write, iclass 7, count 2 2006.257.20:59:57.55#ibcon#wrote, iclass 7, count 2 2006.257.20:59:57.55#ibcon#about to read 3, iclass 7, count 2 2006.257.20:59:57.57#ibcon#read 3, iclass 7, count 2 2006.257.20:59:57.57#ibcon#about to read 4, iclass 7, count 2 2006.257.20:59:57.57#ibcon#read 4, iclass 7, count 2 2006.257.20:59:57.57#ibcon#about to read 5, iclass 7, count 2 2006.257.20:59:57.57#ibcon#read 5, iclass 7, count 2 2006.257.20:59:57.57#ibcon#about to read 6, iclass 7, count 2 2006.257.20:59:57.57#ibcon#read 6, iclass 7, count 2 2006.257.20:59:57.57#ibcon#end of sib2, iclass 7, count 2 2006.257.20:59:57.57#ibcon#*mode == 0, iclass 7, count 2 2006.257.20:59:57.57#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.20:59:57.57#ibcon#[27=AT02-05\r\n] 2006.257.20:59:57.57#ibcon#*before write, iclass 7, count 2 2006.257.20:59:57.57#ibcon#enter sib2, iclass 7, count 2 2006.257.20:59:57.57#ibcon#flushed, iclass 7, count 2 2006.257.20:59:57.57#ibcon#about to write, iclass 7, count 2 2006.257.20:59:57.57#ibcon#wrote, iclass 7, count 2 2006.257.20:59:57.57#ibcon#about to read 3, iclass 7, count 2 2006.257.20:59:57.60#ibcon#read 3, iclass 7, count 2 2006.257.20:59:57.60#ibcon#about to read 4, iclass 7, count 2 2006.257.20:59:57.60#ibcon#read 4, iclass 7, count 2 2006.257.20:59:57.60#ibcon#about to read 5, iclass 7, count 2 2006.257.20:59:57.60#ibcon#read 5, iclass 7, count 2 2006.257.20:59:57.60#ibcon#about to read 6, iclass 7, count 2 2006.257.20:59:57.60#ibcon#read 6, iclass 7, count 2 2006.257.20:59:57.60#ibcon#end of sib2, iclass 7, count 2 2006.257.20:59:57.60#ibcon#*after write, iclass 7, count 2 2006.257.20:59:57.60#ibcon#*before return 0, iclass 7, count 2 2006.257.20:59:57.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:57.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.20:59:57.60#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.20:59:57.60#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:57.60#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:57.72#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:57.72#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:57.72#ibcon#enter wrdev, iclass 7, count 0 2006.257.20:59:57.72#ibcon#first serial, iclass 7, count 0 2006.257.20:59:57.72#ibcon#enter sib2, iclass 7, count 0 2006.257.20:59:57.72#ibcon#flushed, iclass 7, count 0 2006.257.20:59:57.72#ibcon#about to write, iclass 7, count 0 2006.257.20:59:57.72#ibcon#wrote, iclass 7, count 0 2006.257.20:59:57.72#ibcon#about to read 3, iclass 7, count 0 2006.257.20:59:57.74#ibcon#read 3, iclass 7, count 0 2006.257.20:59:57.74#ibcon#about to read 4, iclass 7, count 0 2006.257.20:59:57.74#ibcon#read 4, iclass 7, count 0 2006.257.20:59:57.74#ibcon#about to read 5, iclass 7, count 0 2006.257.20:59:57.74#ibcon#read 5, iclass 7, count 0 2006.257.20:59:57.74#ibcon#about to read 6, iclass 7, count 0 2006.257.20:59:57.74#ibcon#read 6, iclass 7, count 0 2006.257.20:59:57.74#ibcon#end of sib2, iclass 7, count 0 2006.257.20:59:57.74#ibcon#*mode == 0, iclass 7, count 0 2006.257.20:59:57.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.20:59:57.74#ibcon#[27=USB\r\n] 2006.257.20:59:57.74#ibcon#*before write, iclass 7, count 0 2006.257.20:59:57.74#ibcon#enter sib2, iclass 7, count 0 2006.257.20:59:57.74#ibcon#flushed, iclass 7, count 0 2006.257.20:59:57.74#ibcon#about to write, iclass 7, count 0 2006.257.20:59:57.74#ibcon#wrote, iclass 7, count 0 2006.257.20:59:57.74#ibcon#about to read 3, iclass 7, count 0 2006.257.20:59:57.77#ibcon#read 3, iclass 7, count 0 2006.257.20:59:57.77#ibcon#about to read 4, iclass 7, count 0 2006.257.20:59:57.77#ibcon#read 4, iclass 7, count 0 2006.257.20:59:57.77#ibcon#about to read 5, iclass 7, count 0 2006.257.20:59:57.77#ibcon#read 5, iclass 7, count 0 2006.257.20:59:57.77#ibcon#about to read 6, iclass 7, count 0 2006.257.20:59:57.77#ibcon#read 6, iclass 7, count 0 2006.257.20:59:57.77#ibcon#end of sib2, iclass 7, count 0 2006.257.20:59:57.77#ibcon#*after write, iclass 7, count 0 2006.257.20:59:57.77#ibcon#*before return 0, iclass 7, count 0 2006.257.20:59:57.77#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:57.77#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.20:59:57.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.20:59:57.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.20:59:57.77$vck44/vblo=3,649.99 2006.257.20:59:57.77#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.20:59:57.77#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.20:59:57.77#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:57.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:57.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:57.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:57.77#ibcon#enter wrdev, iclass 11, count 0 2006.257.20:59:57.77#ibcon#first serial, iclass 11, count 0 2006.257.20:59:57.77#ibcon#enter sib2, iclass 11, count 0 2006.257.20:59:57.77#ibcon#flushed, iclass 11, count 0 2006.257.20:59:57.77#ibcon#about to write, iclass 11, count 0 2006.257.20:59:57.77#ibcon#wrote, iclass 11, count 0 2006.257.20:59:57.77#ibcon#about to read 3, iclass 11, count 0 2006.257.20:59:57.79#ibcon#read 3, iclass 11, count 0 2006.257.20:59:57.79#ibcon#about to read 4, iclass 11, count 0 2006.257.20:59:57.79#ibcon#read 4, iclass 11, count 0 2006.257.20:59:57.79#ibcon#about to read 5, iclass 11, count 0 2006.257.20:59:57.79#ibcon#read 5, iclass 11, count 0 2006.257.20:59:57.79#ibcon#about to read 6, iclass 11, count 0 2006.257.20:59:57.79#ibcon#read 6, iclass 11, count 0 2006.257.20:59:57.79#ibcon#end of sib2, iclass 11, count 0 2006.257.20:59:57.79#ibcon#*mode == 0, iclass 11, count 0 2006.257.20:59:57.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.20:59:57.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.20:59:57.79#ibcon#*before write, iclass 11, count 0 2006.257.20:59:57.79#ibcon#enter sib2, iclass 11, count 0 2006.257.20:59:57.79#ibcon#flushed, iclass 11, count 0 2006.257.20:59:57.79#ibcon#about to write, iclass 11, count 0 2006.257.20:59:57.79#ibcon#wrote, iclass 11, count 0 2006.257.20:59:57.79#ibcon#about to read 3, iclass 11, count 0 2006.257.20:59:57.83#ibcon#read 3, iclass 11, count 0 2006.257.20:59:57.83#ibcon#about to read 4, iclass 11, count 0 2006.257.20:59:57.83#ibcon#read 4, iclass 11, count 0 2006.257.20:59:57.83#ibcon#about to read 5, iclass 11, count 0 2006.257.20:59:57.83#ibcon#read 5, iclass 11, count 0 2006.257.20:59:57.83#ibcon#about to read 6, iclass 11, count 0 2006.257.20:59:57.83#ibcon#read 6, iclass 11, count 0 2006.257.20:59:57.83#ibcon#end of sib2, iclass 11, count 0 2006.257.20:59:57.83#ibcon#*after write, iclass 11, count 0 2006.257.20:59:57.83#ibcon#*before return 0, iclass 11, count 0 2006.257.20:59:57.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:57.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.20:59:57.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.20:59:57.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.20:59:57.83$vck44/vb=3,4 2006.257.20:59:57.83#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.20:59:57.83#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.20:59:57.83#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:57.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:57.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:57.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:57.89#ibcon#enter wrdev, iclass 13, count 2 2006.257.20:59:57.89#ibcon#first serial, iclass 13, count 2 2006.257.20:59:57.89#ibcon#enter sib2, iclass 13, count 2 2006.257.20:59:57.89#ibcon#flushed, iclass 13, count 2 2006.257.20:59:57.89#ibcon#about to write, iclass 13, count 2 2006.257.20:59:57.89#ibcon#wrote, iclass 13, count 2 2006.257.20:59:57.89#ibcon#about to read 3, iclass 13, count 2 2006.257.20:59:57.91#ibcon#read 3, iclass 13, count 2 2006.257.20:59:57.91#ibcon#about to read 4, iclass 13, count 2 2006.257.20:59:57.91#ibcon#read 4, iclass 13, count 2 2006.257.20:59:57.91#ibcon#about to read 5, iclass 13, count 2 2006.257.20:59:57.91#ibcon#read 5, iclass 13, count 2 2006.257.20:59:57.91#ibcon#about to read 6, iclass 13, count 2 2006.257.20:59:57.91#ibcon#read 6, iclass 13, count 2 2006.257.20:59:57.91#ibcon#end of sib2, iclass 13, count 2 2006.257.20:59:57.91#ibcon#*mode == 0, iclass 13, count 2 2006.257.20:59:57.91#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.20:59:57.91#ibcon#[27=AT03-04\r\n] 2006.257.20:59:57.91#ibcon#*before write, iclass 13, count 2 2006.257.20:59:57.91#ibcon#enter sib2, iclass 13, count 2 2006.257.20:59:57.91#ibcon#flushed, iclass 13, count 2 2006.257.20:59:57.91#ibcon#about to write, iclass 13, count 2 2006.257.20:59:57.91#ibcon#wrote, iclass 13, count 2 2006.257.20:59:57.91#ibcon#about to read 3, iclass 13, count 2 2006.257.20:59:57.94#ibcon#read 3, iclass 13, count 2 2006.257.20:59:57.94#ibcon#about to read 4, iclass 13, count 2 2006.257.20:59:57.94#ibcon#read 4, iclass 13, count 2 2006.257.20:59:57.94#ibcon#about to read 5, iclass 13, count 2 2006.257.20:59:57.94#ibcon#read 5, iclass 13, count 2 2006.257.20:59:57.94#ibcon#about to read 6, iclass 13, count 2 2006.257.20:59:57.94#ibcon#read 6, iclass 13, count 2 2006.257.20:59:57.94#ibcon#end of sib2, iclass 13, count 2 2006.257.20:59:57.94#ibcon#*after write, iclass 13, count 2 2006.257.20:59:57.94#ibcon#*before return 0, iclass 13, count 2 2006.257.20:59:57.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:57.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.20:59:57.94#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.20:59:57.94#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:57.94#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:58.06#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:58.06#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:58.06#ibcon#enter wrdev, iclass 13, count 0 2006.257.20:59:58.06#ibcon#first serial, iclass 13, count 0 2006.257.20:59:58.06#ibcon#enter sib2, iclass 13, count 0 2006.257.20:59:58.06#ibcon#flushed, iclass 13, count 0 2006.257.20:59:58.06#ibcon#about to write, iclass 13, count 0 2006.257.20:59:58.06#ibcon#wrote, iclass 13, count 0 2006.257.20:59:58.06#ibcon#about to read 3, iclass 13, count 0 2006.257.20:59:58.08#ibcon#read 3, iclass 13, count 0 2006.257.20:59:58.08#ibcon#about to read 4, iclass 13, count 0 2006.257.20:59:58.08#ibcon#read 4, iclass 13, count 0 2006.257.20:59:58.08#ibcon#about to read 5, iclass 13, count 0 2006.257.20:59:58.08#ibcon#read 5, iclass 13, count 0 2006.257.20:59:58.08#ibcon#about to read 6, iclass 13, count 0 2006.257.20:59:58.08#ibcon#read 6, iclass 13, count 0 2006.257.20:59:58.08#ibcon#end of sib2, iclass 13, count 0 2006.257.20:59:58.08#ibcon#*mode == 0, iclass 13, count 0 2006.257.20:59:58.08#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.20:59:58.08#ibcon#[27=USB\r\n] 2006.257.20:59:58.08#ibcon#*before write, iclass 13, count 0 2006.257.20:59:58.08#ibcon#enter sib2, iclass 13, count 0 2006.257.20:59:58.08#ibcon#flushed, iclass 13, count 0 2006.257.20:59:58.08#ibcon#about to write, iclass 13, count 0 2006.257.20:59:58.08#ibcon#wrote, iclass 13, count 0 2006.257.20:59:58.08#ibcon#about to read 3, iclass 13, count 0 2006.257.20:59:58.11#ibcon#read 3, iclass 13, count 0 2006.257.20:59:58.11#ibcon#about to read 4, iclass 13, count 0 2006.257.20:59:58.11#ibcon#read 4, iclass 13, count 0 2006.257.20:59:58.11#ibcon#about to read 5, iclass 13, count 0 2006.257.20:59:58.11#ibcon#read 5, iclass 13, count 0 2006.257.20:59:58.11#ibcon#about to read 6, iclass 13, count 0 2006.257.20:59:58.11#ibcon#read 6, iclass 13, count 0 2006.257.20:59:58.11#ibcon#end of sib2, iclass 13, count 0 2006.257.20:59:58.11#ibcon#*after write, iclass 13, count 0 2006.257.20:59:58.11#ibcon#*before return 0, iclass 13, count 0 2006.257.20:59:58.11#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:58.11#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.20:59:58.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.20:59:58.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.20:59:58.11$vck44/vblo=4,679.99 2006.257.20:59:58.11#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.20:59:58.11#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.20:59:58.11#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:58.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:58.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:58.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:58.11#ibcon#enter wrdev, iclass 15, count 0 2006.257.20:59:58.11#ibcon#first serial, iclass 15, count 0 2006.257.20:59:58.11#ibcon#enter sib2, iclass 15, count 0 2006.257.20:59:58.11#ibcon#flushed, iclass 15, count 0 2006.257.20:59:58.11#ibcon#about to write, iclass 15, count 0 2006.257.20:59:58.11#ibcon#wrote, iclass 15, count 0 2006.257.20:59:58.11#ibcon#about to read 3, iclass 15, count 0 2006.257.20:59:58.13#ibcon#read 3, iclass 15, count 0 2006.257.20:59:58.13#ibcon#about to read 4, iclass 15, count 0 2006.257.20:59:58.13#ibcon#read 4, iclass 15, count 0 2006.257.20:59:58.13#ibcon#about to read 5, iclass 15, count 0 2006.257.20:59:58.13#ibcon#read 5, iclass 15, count 0 2006.257.20:59:58.13#ibcon#about to read 6, iclass 15, count 0 2006.257.20:59:58.13#ibcon#read 6, iclass 15, count 0 2006.257.20:59:58.13#ibcon#end of sib2, iclass 15, count 0 2006.257.20:59:58.13#ibcon#*mode == 0, iclass 15, count 0 2006.257.20:59:58.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.20:59:58.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.20:59:58.13#ibcon#*before write, iclass 15, count 0 2006.257.20:59:58.13#ibcon#enter sib2, iclass 15, count 0 2006.257.20:59:58.13#ibcon#flushed, iclass 15, count 0 2006.257.20:59:58.13#ibcon#about to write, iclass 15, count 0 2006.257.20:59:58.13#ibcon#wrote, iclass 15, count 0 2006.257.20:59:58.13#ibcon#about to read 3, iclass 15, count 0 2006.257.20:59:58.17#ibcon#read 3, iclass 15, count 0 2006.257.20:59:58.17#ibcon#about to read 4, iclass 15, count 0 2006.257.20:59:58.17#ibcon#read 4, iclass 15, count 0 2006.257.20:59:58.17#ibcon#about to read 5, iclass 15, count 0 2006.257.20:59:58.17#ibcon#read 5, iclass 15, count 0 2006.257.20:59:58.17#ibcon#about to read 6, iclass 15, count 0 2006.257.20:59:58.17#ibcon#read 6, iclass 15, count 0 2006.257.20:59:58.17#ibcon#end of sib2, iclass 15, count 0 2006.257.20:59:58.17#ibcon#*after write, iclass 15, count 0 2006.257.20:59:58.17#ibcon#*before return 0, iclass 15, count 0 2006.257.20:59:58.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:58.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.20:59:58.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.20:59:58.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.20:59:58.17$vck44/vb=4,5 2006.257.20:59:58.17#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.20:59:58.17#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.20:59:58.17#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:58.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:58.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:58.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:58.23#ibcon#enter wrdev, iclass 17, count 2 2006.257.20:59:58.23#ibcon#first serial, iclass 17, count 2 2006.257.20:59:58.23#ibcon#enter sib2, iclass 17, count 2 2006.257.20:59:58.23#ibcon#flushed, iclass 17, count 2 2006.257.20:59:58.23#ibcon#about to write, iclass 17, count 2 2006.257.20:59:58.23#ibcon#wrote, iclass 17, count 2 2006.257.20:59:58.23#ibcon#about to read 3, iclass 17, count 2 2006.257.20:59:58.25#ibcon#read 3, iclass 17, count 2 2006.257.20:59:58.25#ibcon#about to read 4, iclass 17, count 2 2006.257.20:59:58.25#ibcon#read 4, iclass 17, count 2 2006.257.20:59:58.25#ibcon#about to read 5, iclass 17, count 2 2006.257.20:59:58.25#ibcon#read 5, iclass 17, count 2 2006.257.20:59:58.25#ibcon#about to read 6, iclass 17, count 2 2006.257.20:59:58.25#ibcon#read 6, iclass 17, count 2 2006.257.20:59:58.25#ibcon#end of sib2, iclass 17, count 2 2006.257.20:59:58.25#ibcon#*mode == 0, iclass 17, count 2 2006.257.20:59:58.25#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.20:59:58.25#ibcon#[27=AT04-05\r\n] 2006.257.20:59:58.25#ibcon#*before write, iclass 17, count 2 2006.257.20:59:58.25#ibcon#enter sib2, iclass 17, count 2 2006.257.20:59:58.25#ibcon#flushed, iclass 17, count 2 2006.257.20:59:58.25#ibcon#about to write, iclass 17, count 2 2006.257.20:59:58.25#ibcon#wrote, iclass 17, count 2 2006.257.20:59:58.25#ibcon#about to read 3, iclass 17, count 2 2006.257.20:59:58.28#ibcon#read 3, iclass 17, count 2 2006.257.20:59:58.28#ibcon#about to read 4, iclass 17, count 2 2006.257.20:59:58.28#ibcon#read 4, iclass 17, count 2 2006.257.20:59:58.28#ibcon#about to read 5, iclass 17, count 2 2006.257.20:59:58.28#ibcon#read 5, iclass 17, count 2 2006.257.20:59:58.28#ibcon#about to read 6, iclass 17, count 2 2006.257.20:59:58.28#ibcon#read 6, iclass 17, count 2 2006.257.20:59:58.28#ibcon#end of sib2, iclass 17, count 2 2006.257.20:59:58.28#ibcon#*after write, iclass 17, count 2 2006.257.20:59:58.28#ibcon#*before return 0, iclass 17, count 2 2006.257.20:59:58.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:58.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.20:59:58.28#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.20:59:58.28#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:58.28#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:58.40#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:58.40#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:58.40#ibcon#enter wrdev, iclass 17, count 0 2006.257.20:59:58.40#ibcon#first serial, iclass 17, count 0 2006.257.20:59:58.40#ibcon#enter sib2, iclass 17, count 0 2006.257.20:59:58.40#ibcon#flushed, iclass 17, count 0 2006.257.20:59:58.40#ibcon#about to write, iclass 17, count 0 2006.257.20:59:58.40#ibcon#wrote, iclass 17, count 0 2006.257.20:59:58.40#ibcon#about to read 3, iclass 17, count 0 2006.257.20:59:58.42#ibcon#read 3, iclass 17, count 0 2006.257.20:59:58.42#ibcon#about to read 4, iclass 17, count 0 2006.257.20:59:58.42#ibcon#read 4, iclass 17, count 0 2006.257.20:59:58.42#ibcon#about to read 5, iclass 17, count 0 2006.257.20:59:58.42#ibcon#read 5, iclass 17, count 0 2006.257.20:59:58.42#ibcon#about to read 6, iclass 17, count 0 2006.257.20:59:58.42#ibcon#read 6, iclass 17, count 0 2006.257.20:59:58.42#ibcon#end of sib2, iclass 17, count 0 2006.257.20:59:58.42#ibcon#*mode == 0, iclass 17, count 0 2006.257.20:59:58.42#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.20:59:58.42#ibcon#[27=USB\r\n] 2006.257.20:59:58.42#ibcon#*before write, iclass 17, count 0 2006.257.20:59:58.42#ibcon#enter sib2, iclass 17, count 0 2006.257.20:59:58.42#ibcon#flushed, iclass 17, count 0 2006.257.20:59:58.42#ibcon#about to write, iclass 17, count 0 2006.257.20:59:58.42#ibcon#wrote, iclass 17, count 0 2006.257.20:59:58.42#ibcon#about to read 3, iclass 17, count 0 2006.257.20:59:58.45#ibcon#read 3, iclass 17, count 0 2006.257.20:59:58.45#ibcon#about to read 4, iclass 17, count 0 2006.257.20:59:58.45#ibcon#read 4, iclass 17, count 0 2006.257.20:59:58.45#ibcon#about to read 5, iclass 17, count 0 2006.257.20:59:58.45#ibcon#read 5, iclass 17, count 0 2006.257.20:59:58.45#ibcon#about to read 6, iclass 17, count 0 2006.257.20:59:58.45#ibcon#read 6, iclass 17, count 0 2006.257.20:59:58.45#ibcon#end of sib2, iclass 17, count 0 2006.257.20:59:58.45#ibcon#*after write, iclass 17, count 0 2006.257.20:59:58.45#ibcon#*before return 0, iclass 17, count 0 2006.257.20:59:58.45#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:58.45#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.20:59:58.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.20:59:58.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.20:59:58.45$vck44/vblo=5,709.99 2006.257.20:59:58.45#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.20:59:58.45#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.20:59:58.45#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:58.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:58.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:58.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:58.45#ibcon#enter wrdev, iclass 19, count 0 2006.257.20:59:58.45#ibcon#first serial, iclass 19, count 0 2006.257.20:59:58.45#ibcon#enter sib2, iclass 19, count 0 2006.257.20:59:58.45#ibcon#flushed, iclass 19, count 0 2006.257.20:59:58.45#ibcon#about to write, iclass 19, count 0 2006.257.20:59:58.45#ibcon#wrote, iclass 19, count 0 2006.257.20:59:58.45#ibcon#about to read 3, iclass 19, count 0 2006.257.20:59:58.47#ibcon#read 3, iclass 19, count 0 2006.257.20:59:58.47#ibcon#about to read 4, iclass 19, count 0 2006.257.20:59:58.47#ibcon#read 4, iclass 19, count 0 2006.257.20:59:58.47#ibcon#about to read 5, iclass 19, count 0 2006.257.20:59:58.47#ibcon#read 5, iclass 19, count 0 2006.257.20:59:58.47#ibcon#about to read 6, iclass 19, count 0 2006.257.20:59:58.47#ibcon#read 6, iclass 19, count 0 2006.257.20:59:58.47#ibcon#end of sib2, iclass 19, count 0 2006.257.20:59:58.47#ibcon#*mode == 0, iclass 19, count 0 2006.257.20:59:58.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.20:59:58.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.20:59:58.47#ibcon#*before write, iclass 19, count 0 2006.257.20:59:58.47#ibcon#enter sib2, iclass 19, count 0 2006.257.20:59:58.47#ibcon#flushed, iclass 19, count 0 2006.257.20:59:58.47#ibcon#about to write, iclass 19, count 0 2006.257.20:59:58.47#ibcon#wrote, iclass 19, count 0 2006.257.20:59:58.47#ibcon#about to read 3, iclass 19, count 0 2006.257.20:59:58.51#ibcon#read 3, iclass 19, count 0 2006.257.20:59:58.51#ibcon#about to read 4, iclass 19, count 0 2006.257.20:59:58.51#ibcon#read 4, iclass 19, count 0 2006.257.20:59:58.51#ibcon#about to read 5, iclass 19, count 0 2006.257.20:59:58.51#ibcon#read 5, iclass 19, count 0 2006.257.20:59:58.51#ibcon#about to read 6, iclass 19, count 0 2006.257.20:59:58.51#ibcon#read 6, iclass 19, count 0 2006.257.20:59:58.51#ibcon#end of sib2, iclass 19, count 0 2006.257.20:59:58.51#ibcon#*after write, iclass 19, count 0 2006.257.20:59:58.51#ibcon#*before return 0, iclass 19, count 0 2006.257.20:59:58.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:58.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.20:59:58.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.20:59:58.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.20:59:58.51$vck44/vb=5,4 2006.257.20:59:58.51#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.20:59:58.51#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.20:59:58.51#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:58.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:58.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:58.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:58.57#ibcon#enter wrdev, iclass 21, count 2 2006.257.20:59:58.57#ibcon#first serial, iclass 21, count 2 2006.257.20:59:58.57#ibcon#enter sib2, iclass 21, count 2 2006.257.20:59:58.57#ibcon#flushed, iclass 21, count 2 2006.257.20:59:58.57#ibcon#about to write, iclass 21, count 2 2006.257.20:59:58.57#ibcon#wrote, iclass 21, count 2 2006.257.20:59:58.57#ibcon#about to read 3, iclass 21, count 2 2006.257.20:59:58.59#ibcon#read 3, iclass 21, count 2 2006.257.20:59:58.59#ibcon#about to read 4, iclass 21, count 2 2006.257.20:59:58.59#ibcon#read 4, iclass 21, count 2 2006.257.20:59:58.59#ibcon#about to read 5, iclass 21, count 2 2006.257.20:59:58.59#ibcon#read 5, iclass 21, count 2 2006.257.20:59:58.59#ibcon#about to read 6, iclass 21, count 2 2006.257.20:59:58.59#ibcon#read 6, iclass 21, count 2 2006.257.20:59:58.59#ibcon#end of sib2, iclass 21, count 2 2006.257.20:59:58.59#ibcon#*mode == 0, iclass 21, count 2 2006.257.20:59:58.59#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.20:59:58.59#ibcon#[27=AT05-04\r\n] 2006.257.20:59:58.59#ibcon#*before write, iclass 21, count 2 2006.257.20:59:58.59#ibcon#enter sib2, iclass 21, count 2 2006.257.20:59:58.59#ibcon#flushed, iclass 21, count 2 2006.257.20:59:58.59#ibcon#about to write, iclass 21, count 2 2006.257.20:59:58.59#ibcon#wrote, iclass 21, count 2 2006.257.20:59:58.59#ibcon#about to read 3, iclass 21, count 2 2006.257.20:59:58.62#ibcon#read 3, iclass 21, count 2 2006.257.20:59:58.62#ibcon#about to read 4, iclass 21, count 2 2006.257.20:59:58.62#ibcon#read 4, iclass 21, count 2 2006.257.20:59:58.62#ibcon#about to read 5, iclass 21, count 2 2006.257.20:59:58.62#ibcon#read 5, iclass 21, count 2 2006.257.20:59:58.62#ibcon#about to read 6, iclass 21, count 2 2006.257.20:59:58.62#ibcon#read 6, iclass 21, count 2 2006.257.20:59:58.62#ibcon#end of sib2, iclass 21, count 2 2006.257.20:59:58.62#ibcon#*after write, iclass 21, count 2 2006.257.20:59:58.62#ibcon#*before return 0, iclass 21, count 2 2006.257.20:59:58.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:58.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.20:59:58.62#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.20:59:58.62#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:58.62#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:58.74#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:58.74#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:58.74#ibcon#enter wrdev, iclass 21, count 0 2006.257.20:59:58.74#ibcon#first serial, iclass 21, count 0 2006.257.20:59:58.74#ibcon#enter sib2, iclass 21, count 0 2006.257.20:59:58.74#ibcon#flushed, iclass 21, count 0 2006.257.20:59:58.74#ibcon#about to write, iclass 21, count 0 2006.257.20:59:58.74#ibcon#wrote, iclass 21, count 0 2006.257.20:59:58.74#ibcon#about to read 3, iclass 21, count 0 2006.257.20:59:58.76#ibcon#read 3, iclass 21, count 0 2006.257.20:59:58.76#ibcon#about to read 4, iclass 21, count 0 2006.257.20:59:58.76#ibcon#read 4, iclass 21, count 0 2006.257.20:59:58.76#ibcon#about to read 5, iclass 21, count 0 2006.257.20:59:58.76#ibcon#read 5, iclass 21, count 0 2006.257.20:59:58.76#ibcon#about to read 6, iclass 21, count 0 2006.257.20:59:58.76#ibcon#read 6, iclass 21, count 0 2006.257.20:59:58.76#ibcon#end of sib2, iclass 21, count 0 2006.257.20:59:58.76#ibcon#*mode == 0, iclass 21, count 0 2006.257.20:59:58.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.20:59:58.76#ibcon#[27=USB\r\n] 2006.257.20:59:58.76#ibcon#*before write, iclass 21, count 0 2006.257.20:59:58.76#ibcon#enter sib2, iclass 21, count 0 2006.257.20:59:58.76#ibcon#flushed, iclass 21, count 0 2006.257.20:59:58.76#ibcon#about to write, iclass 21, count 0 2006.257.20:59:58.76#ibcon#wrote, iclass 21, count 0 2006.257.20:59:58.76#ibcon#about to read 3, iclass 21, count 0 2006.257.20:59:58.79#ibcon#read 3, iclass 21, count 0 2006.257.20:59:58.79#ibcon#about to read 4, iclass 21, count 0 2006.257.20:59:58.79#ibcon#read 4, iclass 21, count 0 2006.257.20:59:58.79#ibcon#about to read 5, iclass 21, count 0 2006.257.20:59:58.79#ibcon#read 5, iclass 21, count 0 2006.257.20:59:58.79#ibcon#about to read 6, iclass 21, count 0 2006.257.20:59:58.79#ibcon#read 6, iclass 21, count 0 2006.257.20:59:58.79#ibcon#end of sib2, iclass 21, count 0 2006.257.20:59:58.79#ibcon#*after write, iclass 21, count 0 2006.257.20:59:58.79#ibcon#*before return 0, iclass 21, count 0 2006.257.20:59:58.79#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:58.79#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.20:59:58.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.20:59:58.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.20:59:58.79$vck44/vblo=6,719.99 2006.257.20:59:58.79#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.20:59:58.79#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.20:59:58.79#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:58.79#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:58.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:58.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:58.79#ibcon#enter wrdev, iclass 23, count 0 2006.257.20:59:58.79#ibcon#first serial, iclass 23, count 0 2006.257.20:59:58.79#ibcon#enter sib2, iclass 23, count 0 2006.257.20:59:58.79#ibcon#flushed, iclass 23, count 0 2006.257.20:59:58.79#ibcon#about to write, iclass 23, count 0 2006.257.20:59:58.79#ibcon#wrote, iclass 23, count 0 2006.257.20:59:58.79#ibcon#about to read 3, iclass 23, count 0 2006.257.20:59:58.81#ibcon#read 3, iclass 23, count 0 2006.257.20:59:58.81#ibcon#about to read 4, iclass 23, count 0 2006.257.20:59:58.81#ibcon#read 4, iclass 23, count 0 2006.257.20:59:58.81#ibcon#about to read 5, iclass 23, count 0 2006.257.20:59:58.81#ibcon#read 5, iclass 23, count 0 2006.257.20:59:58.81#ibcon#about to read 6, iclass 23, count 0 2006.257.20:59:58.81#ibcon#read 6, iclass 23, count 0 2006.257.20:59:58.81#ibcon#end of sib2, iclass 23, count 0 2006.257.20:59:58.81#ibcon#*mode == 0, iclass 23, count 0 2006.257.20:59:58.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.20:59:58.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.20:59:58.81#ibcon#*before write, iclass 23, count 0 2006.257.20:59:58.81#ibcon#enter sib2, iclass 23, count 0 2006.257.20:59:58.81#ibcon#flushed, iclass 23, count 0 2006.257.20:59:58.81#ibcon#about to write, iclass 23, count 0 2006.257.20:59:58.81#ibcon#wrote, iclass 23, count 0 2006.257.20:59:58.81#ibcon#about to read 3, iclass 23, count 0 2006.257.20:59:58.85#ibcon#read 3, iclass 23, count 0 2006.257.20:59:58.85#ibcon#about to read 4, iclass 23, count 0 2006.257.20:59:58.85#ibcon#read 4, iclass 23, count 0 2006.257.20:59:58.85#ibcon#about to read 5, iclass 23, count 0 2006.257.20:59:58.85#ibcon#read 5, iclass 23, count 0 2006.257.20:59:58.85#ibcon#about to read 6, iclass 23, count 0 2006.257.20:59:58.85#ibcon#read 6, iclass 23, count 0 2006.257.20:59:58.85#ibcon#end of sib2, iclass 23, count 0 2006.257.20:59:58.85#ibcon#*after write, iclass 23, count 0 2006.257.20:59:58.85#ibcon#*before return 0, iclass 23, count 0 2006.257.20:59:58.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:58.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.20:59:58.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.20:59:58.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.20:59:58.85$vck44/vb=6,4 2006.257.20:59:58.85#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.20:59:58.85#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.20:59:58.85#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:58.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:58.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:58.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:58.91#ibcon#enter wrdev, iclass 25, count 2 2006.257.20:59:58.91#ibcon#first serial, iclass 25, count 2 2006.257.20:59:58.91#ibcon#enter sib2, iclass 25, count 2 2006.257.20:59:58.91#ibcon#flushed, iclass 25, count 2 2006.257.20:59:58.91#ibcon#about to write, iclass 25, count 2 2006.257.20:59:58.91#ibcon#wrote, iclass 25, count 2 2006.257.20:59:58.91#ibcon#about to read 3, iclass 25, count 2 2006.257.20:59:58.93#ibcon#read 3, iclass 25, count 2 2006.257.20:59:58.93#ibcon#about to read 4, iclass 25, count 2 2006.257.20:59:58.93#ibcon#read 4, iclass 25, count 2 2006.257.20:59:58.93#ibcon#about to read 5, iclass 25, count 2 2006.257.20:59:58.93#ibcon#read 5, iclass 25, count 2 2006.257.20:59:58.93#ibcon#about to read 6, iclass 25, count 2 2006.257.20:59:58.93#ibcon#read 6, iclass 25, count 2 2006.257.20:59:58.93#ibcon#end of sib2, iclass 25, count 2 2006.257.20:59:58.93#ibcon#*mode == 0, iclass 25, count 2 2006.257.20:59:58.93#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.20:59:58.93#ibcon#[27=AT06-04\r\n] 2006.257.20:59:58.93#ibcon#*before write, iclass 25, count 2 2006.257.20:59:58.93#ibcon#enter sib2, iclass 25, count 2 2006.257.20:59:58.93#ibcon#flushed, iclass 25, count 2 2006.257.20:59:58.93#ibcon#about to write, iclass 25, count 2 2006.257.20:59:58.93#ibcon#wrote, iclass 25, count 2 2006.257.20:59:58.93#ibcon#about to read 3, iclass 25, count 2 2006.257.20:59:58.96#ibcon#read 3, iclass 25, count 2 2006.257.20:59:58.96#ibcon#about to read 4, iclass 25, count 2 2006.257.20:59:58.96#ibcon#read 4, iclass 25, count 2 2006.257.20:59:58.96#ibcon#about to read 5, iclass 25, count 2 2006.257.20:59:58.96#ibcon#read 5, iclass 25, count 2 2006.257.20:59:58.96#ibcon#about to read 6, iclass 25, count 2 2006.257.20:59:58.96#ibcon#read 6, iclass 25, count 2 2006.257.20:59:58.96#ibcon#end of sib2, iclass 25, count 2 2006.257.20:59:58.96#ibcon#*after write, iclass 25, count 2 2006.257.20:59:58.96#ibcon#*before return 0, iclass 25, count 2 2006.257.20:59:58.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:58.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.20:59:58.96#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.20:59:58.96#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:58.96#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:59.08#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:59.08#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:59.08#ibcon#enter wrdev, iclass 25, count 0 2006.257.20:59:59.08#ibcon#first serial, iclass 25, count 0 2006.257.20:59:59.08#ibcon#enter sib2, iclass 25, count 0 2006.257.20:59:59.08#ibcon#flushed, iclass 25, count 0 2006.257.20:59:59.08#ibcon#about to write, iclass 25, count 0 2006.257.20:59:59.08#ibcon#wrote, iclass 25, count 0 2006.257.20:59:59.08#ibcon#about to read 3, iclass 25, count 0 2006.257.20:59:59.10#ibcon#read 3, iclass 25, count 0 2006.257.20:59:59.10#ibcon#about to read 4, iclass 25, count 0 2006.257.20:59:59.10#ibcon#read 4, iclass 25, count 0 2006.257.20:59:59.10#ibcon#about to read 5, iclass 25, count 0 2006.257.20:59:59.10#ibcon#read 5, iclass 25, count 0 2006.257.20:59:59.10#ibcon#about to read 6, iclass 25, count 0 2006.257.20:59:59.10#ibcon#read 6, iclass 25, count 0 2006.257.20:59:59.10#ibcon#end of sib2, iclass 25, count 0 2006.257.20:59:59.10#ibcon#*mode == 0, iclass 25, count 0 2006.257.20:59:59.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.20:59:59.10#ibcon#[27=USB\r\n] 2006.257.20:59:59.10#ibcon#*before write, iclass 25, count 0 2006.257.20:59:59.10#ibcon#enter sib2, iclass 25, count 0 2006.257.20:59:59.10#ibcon#flushed, iclass 25, count 0 2006.257.20:59:59.10#ibcon#about to write, iclass 25, count 0 2006.257.20:59:59.10#ibcon#wrote, iclass 25, count 0 2006.257.20:59:59.10#ibcon#about to read 3, iclass 25, count 0 2006.257.20:59:59.13#ibcon#read 3, iclass 25, count 0 2006.257.20:59:59.13#ibcon#about to read 4, iclass 25, count 0 2006.257.20:59:59.13#ibcon#read 4, iclass 25, count 0 2006.257.20:59:59.13#ibcon#about to read 5, iclass 25, count 0 2006.257.20:59:59.13#ibcon#read 5, iclass 25, count 0 2006.257.20:59:59.13#ibcon#about to read 6, iclass 25, count 0 2006.257.20:59:59.13#ibcon#read 6, iclass 25, count 0 2006.257.20:59:59.13#ibcon#end of sib2, iclass 25, count 0 2006.257.20:59:59.13#ibcon#*after write, iclass 25, count 0 2006.257.20:59:59.13#ibcon#*before return 0, iclass 25, count 0 2006.257.20:59:59.13#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:59.13#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.20:59:59.13#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.20:59:59.13#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.20:59:59.13$vck44/vblo=7,734.99 2006.257.20:59:59.13#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.20:59:59.13#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.20:59:59.13#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:59.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:59.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:59.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:59.13#ibcon#enter wrdev, iclass 27, count 0 2006.257.20:59:59.13#ibcon#first serial, iclass 27, count 0 2006.257.20:59:59.13#ibcon#enter sib2, iclass 27, count 0 2006.257.20:59:59.13#ibcon#flushed, iclass 27, count 0 2006.257.20:59:59.13#ibcon#about to write, iclass 27, count 0 2006.257.20:59:59.13#ibcon#wrote, iclass 27, count 0 2006.257.20:59:59.13#ibcon#about to read 3, iclass 27, count 0 2006.257.20:59:59.15#ibcon#read 3, iclass 27, count 0 2006.257.20:59:59.15#ibcon#about to read 4, iclass 27, count 0 2006.257.20:59:59.15#ibcon#read 4, iclass 27, count 0 2006.257.20:59:59.15#ibcon#about to read 5, iclass 27, count 0 2006.257.20:59:59.15#ibcon#read 5, iclass 27, count 0 2006.257.20:59:59.15#ibcon#about to read 6, iclass 27, count 0 2006.257.20:59:59.15#ibcon#read 6, iclass 27, count 0 2006.257.20:59:59.15#ibcon#end of sib2, iclass 27, count 0 2006.257.20:59:59.15#ibcon#*mode == 0, iclass 27, count 0 2006.257.20:59:59.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.20:59:59.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.20:59:59.15#ibcon#*before write, iclass 27, count 0 2006.257.20:59:59.15#ibcon#enter sib2, iclass 27, count 0 2006.257.20:59:59.15#ibcon#flushed, iclass 27, count 0 2006.257.20:59:59.15#ibcon#about to write, iclass 27, count 0 2006.257.20:59:59.15#ibcon#wrote, iclass 27, count 0 2006.257.20:59:59.15#ibcon#about to read 3, iclass 27, count 0 2006.257.20:59:59.19#ibcon#read 3, iclass 27, count 0 2006.257.20:59:59.19#ibcon#about to read 4, iclass 27, count 0 2006.257.20:59:59.19#ibcon#read 4, iclass 27, count 0 2006.257.20:59:59.19#ibcon#about to read 5, iclass 27, count 0 2006.257.20:59:59.19#ibcon#read 5, iclass 27, count 0 2006.257.20:59:59.19#ibcon#about to read 6, iclass 27, count 0 2006.257.20:59:59.19#ibcon#read 6, iclass 27, count 0 2006.257.20:59:59.19#ibcon#end of sib2, iclass 27, count 0 2006.257.20:59:59.19#ibcon#*after write, iclass 27, count 0 2006.257.20:59:59.19#ibcon#*before return 0, iclass 27, count 0 2006.257.20:59:59.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:59.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.20:59:59.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.20:59:59.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.20:59:59.19$vck44/vb=7,4 2006.257.20:59:59.19#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.20:59:59.19#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.20:59:59.19#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:59.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:59.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:59.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:59.25#ibcon#enter wrdev, iclass 29, count 2 2006.257.20:59:59.25#ibcon#first serial, iclass 29, count 2 2006.257.20:59:59.25#ibcon#enter sib2, iclass 29, count 2 2006.257.20:59:59.25#ibcon#flushed, iclass 29, count 2 2006.257.20:59:59.25#ibcon#about to write, iclass 29, count 2 2006.257.20:59:59.25#ibcon#wrote, iclass 29, count 2 2006.257.20:59:59.25#ibcon#about to read 3, iclass 29, count 2 2006.257.20:59:59.27#ibcon#read 3, iclass 29, count 2 2006.257.20:59:59.27#ibcon#about to read 4, iclass 29, count 2 2006.257.20:59:59.27#ibcon#read 4, iclass 29, count 2 2006.257.20:59:59.27#ibcon#about to read 5, iclass 29, count 2 2006.257.20:59:59.27#ibcon#read 5, iclass 29, count 2 2006.257.20:59:59.27#ibcon#about to read 6, iclass 29, count 2 2006.257.20:59:59.27#ibcon#read 6, iclass 29, count 2 2006.257.20:59:59.27#ibcon#end of sib2, iclass 29, count 2 2006.257.20:59:59.27#ibcon#*mode == 0, iclass 29, count 2 2006.257.20:59:59.27#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.20:59:59.27#ibcon#[27=AT07-04\r\n] 2006.257.20:59:59.27#ibcon#*before write, iclass 29, count 2 2006.257.20:59:59.27#ibcon#enter sib2, iclass 29, count 2 2006.257.20:59:59.27#ibcon#flushed, iclass 29, count 2 2006.257.20:59:59.27#ibcon#about to write, iclass 29, count 2 2006.257.20:59:59.27#ibcon#wrote, iclass 29, count 2 2006.257.20:59:59.27#ibcon#about to read 3, iclass 29, count 2 2006.257.20:59:59.30#ibcon#read 3, iclass 29, count 2 2006.257.20:59:59.30#ibcon#about to read 4, iclass 29, count 2 2006.257.20:59:59.30#ibcon#read 4, iclass 29, count 2 2006.257.20:59:59.30#ibcon#about to read 5, iclass 29, count 2 2006.257.20:59:59.30#ibcon#read 5, iclass 29, count 2 2006.257.20:59:59.30#ibcon#about to read 6, iclass 29, count 2 2006.257.20:59:59.30#ibcon#read 6, iclass 29, count 2 2006.257.20:59:59.30#ibcon#end of sib2, iclass 29, count 2 2006.257.20:59:59.30#ibcon#*after write, iclass 29, count 2 2006.257.20:59:59.30#ibcon#*before return 0, iclass 29, count 2 2006.257.20:59:59.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:59.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.20:59:59.30#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.20:59:59.30#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:59.30#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:59.42#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:59.42#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:59.42#ibcon#enter wrdev, iclass 29, count 0 2006.257.20:59:59.42#ibcon#first serial, iclass 29, count 0 2006.257.20:59:59.42#ibcon#enter sib2, iclass 29, count 0 2006.257.20:59:59.42#ibcon#flushed, iclass 29, count 0 2006.257.20:59:59.42#ibcon#about to write, iclass 29, count 0 2006.257.20:59:59.42#ibcon#wrote, iclass 29, count 0 2006.257.20:59:59.42#ibcon#about to read 3, iclass 29, count 0 2006.257.20:59:59.44#ibcon#read 3, iclass 29, count 0 2006.257.20:59:59.44#ibcon#about to read 4, iclass 29, count 0 2006.257.20:59:59.44#ibcon#read 4, iclass 29, count 0 2006.257.20:59:59.44#ibcon#about to read 5, iclass 29, count 0 2006.257.20:59:59.44#ibcon#read 5, iclass 29, count 0 2006.257.20:59:59.44#ibcon#about to read 6, iclass 29, count 0 2006.257.20:59:59.44#ibcon#read 6, iclass 29, count 0 2006.257.20:59:59.44#ibcon#end of sib2, iclass 29, count 0 2006.257.20:59:59.44#ibcon#*mode == 0, iclass 29, count 0 2006.257.20:59:59.44#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.20:59:59.44#ibcon#[27=USB\r\n] 2006.257.20:59:59.44#ibcon#*before write, iclass 29, count 0 2006.257.20:59:59.44#ibcon#enter sib2, iclass 29, count 0 2006.257.20:59:59.44#ibcon#flushed, iclass 29, count 0 2006.257.20:59:59.44#ibcon#about to write, iclass 29, count 0 2006.257.20:59:59.44#ibcon#wrote, iclass 29, count 0 2006.257.20:59:59.44#ibcon#about to read 3, iclass 29, count 0 2006.257.20:59:59.47#ibcon#read 3, iclass 29, count 0 2006.257.20:59:59.47#ibcon#about to read 4, iclass 29, count 0 2006.257.20:59:59.47#ibcon#read 4, iclass 29, count 0 2006.257.20:59:59.47#ibcon#about to read 5, iclass 29, count 0 2006.257.20:59:59.47#ibcon#read 5, iclass 29, count 0 2006.257.20:59:59.47#ibcon#about to read 6, iclass 29, count 0 2006.257.20:59:59.47#ibcon#read 6, iclass 29, count 0 2006.257.20:59:59.47#ibcon#end of sib2, iclass 29, count 0 2006.257.20:59:59.47#ibcon#*after write, iclass 29, count 0 2006.257.20:59:59.47#ibcon#*before return 0, iclass 29, count 0 2006.257.20:59:59.47#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:59.47#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.20:59:59.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.20:59:59.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.20:59:59.47$vck44/vblo=8,744.99 2006.257.20:59:59.47#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.20:59:59.47#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.20:59:59.47#ibcon#ireg 17 cls_cnt 0 2006.257.20:59:59.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:59:59.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:59:59.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:59:59.47#ibcon#enter wrdev, iclass 31, count 0 2006.257.20:59:59.47#ibcon#first serial, iclass 31, count 0 2006.257.20:59:59.47#ibcon#enter sib2, iclass 31, count 0 2006.257.20:59:59.47#ibcon#flushed, iclass 31, count 0 2006.257.20:59:59.47#ibcon#about to write, iclass 31, count 0 2006.257.20:59:59.47#ibcon#wrote, iclass 31, count 0 2006.257.20:59:59.47#ibcon#about to read 3, iclass 31, count 0 2006.257.20:59:59.49#ibcon#read 3, iclass 31, count 0 2006.257.20:59:59.49#ibcon#about to read 4, iclass 31, count 0 2006.257.20:59:59.49#ibcon#read 4, iclass 31, count 0 2006.257.20:59:59.49#ibcon#about to read 5, iclass 31, count 0 2006.257.20:59:59.49#ibcon#read 5, iclass 31, count 0 2006.257.20:59:59.49#ibcon#about to read 6, iclass 31, count 0 2006.257.20:59:59.49#ibcon#read 6, iclass 31, count 0 2006.257.20:59:59.49#ibcon#end of sib2, iclass 31, count 0 2006.257.20:59:59.49#ibcon#*mode == 0, iclass 31, count 0 2006.257.20:59:59.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.20:59:59.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.20:59:59.49#ibcon#*before write, iclass 31, count 0 2006.257.20:59:59.49#ibcon#enter sib2, iclass 31, count 0 2006.257.20:59:59.49#ibcon#flushed, iclass 31, count 0 2006.257.20:59:59.49#ibcon#about to write, iclass 31, count 0 2006.257.20:59:59.49#ibcon#wrote, iclass 31, count 0 2006.257.20:59:59.49#ibcon#about to read 3, iclass 31, count 0 2006.257.20:59:59.53#ibcon#read 3, iclass 31, count 0 2006.257.20:59:59.53#ibcon#about to read 4, iclass 31, count 0 2006.257.20:59:59.53#ibcon#read 4, iclass 31, count 0 2006.257.20:59:59.53#ibcon#about to read 5, iclass 31, count 0 2006.257.20:59:59.53#ibcon#read 5, iclass 31, count 0 2006.257.20:59:59.53#ibcon#about to read 6, iclass 31, count 0 2006.257.20:59:59.53#ibcon#read 6, iclass 31, count 0 2006.257.20:59:59.53#ibcon#end of sib2, iclass 31, count 0 2006.257.20:59:59.53#ibcon#*after write, iclass 31, count 0 2006.257.20:59:59.53#ibcon#*before return 0, iclass 31, count 0 2006.257.20:59:59.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:59:59.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.20:59:59.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.20:59:59.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.20:59:59.53$vck44/vb=8,4 2006.257.20:59:59.53#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.20:59:59.53#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.20:59:59.53#ibcon#ireg 11 cls_cnt 2 2006.257.20:59:59.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:59:59.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:59:59.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:59:59.59#ibcon#enter wrdev, iclass 33, count 2 2006.257.20:59:59.59#ibcon#first serial, iclass 33, count 2 2006.257.20:59:59.59#ibcon#enter sib2, iclass 33, count 2 2006.257.20:59:59.59#ibcon#flushed, iclass 33, count 2 2006.257.20:59:59.59#ibcon#about to write, iclass 33, count 2 2006.257.20:59:59.59#ibcon#wrote, iclass 33, count 2 2006.257.20:59:59.59#ibcon#about to read 3, iclass 33, count 2 2006.257.20:59:59.61#ibcon#read 3, iclass 33, count 2 2006.257.20:59:59.61#ibcon#about to read 4, iclass 33, count 2 2006.257.20:59:59.61#ibcon#read 4, iclass 33, count 2 2006.257.20:59:59.61#ibcon#about to read 5, iclass 33, count 2 2006.257.20:59:59.61#ibcon#read 5, iclass 33, count 2 2006.257.20:59:59.61#ibcon#about to read 6, iclass 33, count 2 2006.257.20:59:59.61#ibcon#read 6, iclass 33, count 2 2006.257.20:59:59.61#ibcon#end of sib2, iclass 33, count 2 2006.257.20:59:59.61#ibcon#*mode == 0, iclass 33, count 2 2006.257.20:59:59.61#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.20:59:59.61#ibcon#[27=AT08-04\r\n] 2006.257.20:59:59.61#ibcon#*before write, iclass 33, count 2 2006.257.20:59:59.61#ibcon#enter sib2, iclass 33, count 2 2006.257.20:59:59.61#ibcon#flushed, iclass 33, count 2 2006.257.20:59:59.61#ibcon#about to write, iclass 33, count 2 2006.257.20:59:59.61#ibcon#wrote, iclass 33, count 2 2006.257.20:59:59.61#ibcon#about to read 3, iclass 33, count 2 2006.257.20:59:59.64#ibcon#read 3, iclass 33, count 2 2006.257.20:59:59.64#ibcon#about to read 4, iclass 33, count 2 2006.257.20:59:59.64#ibcon#read 4, iclass 33, count 2 2006.257.20:59:59.64#ibcon#about to read 5, iclass 33, count 2 2006.257.20:59:59.64#ibcon#read 5, iclass 33, count 2 2006.257.20:59:59.64#ibcon#about to read 6, iclass 33, count 2 2006.257.20:59:59.64#ibcon#read 6, iclass 33, count 2 2006.257.20:59:59.64#ibcon#end of sib2, iclass 33, count 2 2006.257.20:59:59.64#ibcon#*after write, iclass 33, count 2 2006.257.20:59:59.64#ibcon#*before return 0, iclass 33, count 2 2006.257.20:59:59.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:59:59.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.20:59:59.64#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.20:59:59.64#ibcon#ireg 7 cls_cnt 0 2006.257.20:59:59.64#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:59:59.76#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:59:59.76#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:59:59.76#ibcon#enter wrdev, iclass 33, count 0 2006.257.20:59:59.76#ibcon#first serial, iclass 33, count 0 2006.257.20:59:59.76#ibcon#enter sib2, iclass 33, count 0 2006.257.20:59:59.76#ibcon#flushed, iclass 33, count 0 2006.257.20:59:59.76#ibcon#about to write, iclass 33, count 0 2006.257.20:59:59.76#ibcon#wrote, iclass 33, count 0 2006.257.20:59:59.76#ibcon#about to read 3, iclass 33, count 0 2006.257.20:59:59.78#ibcon#read 3, iclass 33, count 0 2006.257.20:59:59.78#ibcon#about to read 4, iclass 33, count 0 2006.257.20:59:59.78#ibcon#read 4, iclass 33, count 0 2006.257.20:59:59.78#ibcon#about to read 5, iclass 33, count 0 2006.257.20:59:59.78#ibcon#read 5, iclass 33, count 0 2006.257.20:59:59.78#ibcon#about to read 6, iclass 33, count 0 2006.257.20:59:59.78#ibcon#read 6, iclass 33, count 0 2006.257.20:59:59.78#ibcon#end of sib2, iclass 33, count 0 2006.257.20:59:59.78#ibcon#*mode == 0, iclass 33, count 0 2006.257.20:59:59.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.20:59:59.78#ibcon#[27=USB\r\n] 2006.257.20:59:59.78#ibcon#*before write, iclass 33, count 0 2006.257.20:59:59.78#ibcon#enter sib2, iclass 33, count 0 2006.257.20:59:59.78#ibcon#flushed, iclass 33, count 0 2006.257.20:59:59.78#ibcon#about to write, iclass 33, count 0 2006.257.20:59:59.78#ibcon#wrote, iclass 33, count 0 2006.257.20:59:59.78#ibcon#about to read 3, iclass 33, count 0 2006.257.20:59:59.81#ibcon#read 3, iclass 33, count 0 2006.257.20:59:59.81#ibcon#about to read 4, iclass 33, count 0 2006.257.20:59:59.81#ibcon#read 4, iclass 33, count 0 2006.257.20:59:59.81#ibcon#about to read 5, iclass 33, count 0 2006.257.20:59:59.81#ibcon#read 5, iclass 33, count 0 2006.257.20:59:59.81#ibcon#about to read 6, iclass 33, count 0 2006.257.20:59:59.81#ibcon#read 6, iclass 33, count 0 2006.257.20:59:59.81#ibcon#end of sib2, iclass 33, count 0 2006.257.20:59:59.81#ibcon#*after write, iclass 33, count 0 2006.257.20:59:59.81#ibcon#*before return 0, iclass 33, count 0 2006.257.20:59:59.81#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:59:59.81#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.20:59:59.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.20:59:59.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.20:59:59.81$vck44/vabw=wide 2006.257.20:59:59.81#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.20:59:59.81#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.20:59:59.81#ibcon#ireg 8 cls_cnt 0 2006.257.20:59:59.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:59.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:59.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:59.81#ibcon#enter wrdev, iclass 35, count 0 2006.257.20:59:59.81#ibcon#first serial, iclass 35, count 0 2006.257.20:59:59.81#ibcon#enter sib2, iclass 35, count 0 2006.257.20:59:59.81#ibcon#flushed, iclass 35, count 0 2006.257.20:59:59.81#ibcon#about to write, iclass 35, count 0 2006.257.20:59:59.81#ibcon#wrote, iclass 35, count 0 2006.257.20:59:59.81#ibcon#about to read 3, iclass 35, count 0 2006.257.20:59:59.83#ibcon#read 3, iclass 35, count 0 2006.257.20:59:59.83#ibcon#about to read 4, iclass 35, count 0 2006.257.20:59:59.83#ibcon#read 4, iclass 35, count 0 2006.257.20:59:59.83#ibcon#about to read 5, iclass 35, count 0 2006.257.20:59:59.83#ibcon#read 5, iclass 35, count 0 2006.257.20:59:59.83#ibcon#about to read 6, iclass 35, count 0 2006.257.20:59:59.83#ibcon#read 6, iclass 35, count 0 2006.257.20:59:59.83#ibcon#end of sib2, iclass 35, count 0 2006.257.20:59:59.83#ibcon#*mode == 0, iclass 35, count 0 2006.257.20:59:59.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.20:59:59.83#ibcon#[25=BW32\r\n] 2006.257.20:59:59.83#ibcon#*before write, iclass 35, count 0 2006.257.20:59:59.83#ibcon#enter sib2, iclass 35, count 0 2006.257.20:59:59.83#ibcon#flushed, iclass 35, count 0 2006.257.20:59:59.83#ibcon#about to write, iclass 35, count 0 2006.257.20:59:59.83#ibcon#wrote, iclass 35, count 0 2006.257.20:59:59.83#ibcon#about to read 3, iclass 35, count 0 2006.257.20:59:59.86#ibcon#read 3, iclass 35, count 0 2006.257.20:59:59.86#ibcon#about to read 4, iclass 35, count 0 2006.257.20:59:59.86#ibcon#read 4, iclass 35, count 0 2006.257.20:59:59.86#ibcon#about to read 5, iclass 35, count 0 2006.257.20:59:59.86#ibcon#read 5, iclass 35, count 0 2006.257.20:59:59.86#ibcon#about to read 6, iclass 35, count 0 2006.257.20:59:59.86#ibcon#read 6, iclass 35, count 0 2006.257.20:59:59.86#ibcon#end of sib2, iclass 35, count 0 2006.257.20:59:59.86#ibcon#*after write, iclass 35, count 0 2006.257.20:59:59.86#ibcon#*before return 0, iclass 35, count 0 2006.257.20:59:59.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:59.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.20:59:59.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.20:59:59.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.20:59:59.86$vck44/vbbw=wide 2006.257.20:59:59.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.20:59:59.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.20:59:59.86#ibcon#ireg 8 cls_cnt 0 2006.257.20:59:59.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:59:59.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:59:59.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:59:59.93#ibcon#enter wrdev, iclass 37, count 0 2006.257.20:59:59.93#ibcon#first serial, iclass 37, count 0 2006.257.20:59:59.93#ibcon#enter sib2, iclass 37, count 0 2006.257.20:59:59.93#ibcon#flushed, iclass 37, count 0 2006.257.20:59:59.93#ibcon#about to write, iclass 37, count 0 2006.257.20:59:59.93#ibcon#wrote, iclass 37, count 0 2006.257.20:59:59.93#ibcon#about to read 3, iclass 37, count 0 2006.257.20:59:59.95#ibcon#read 3, iclass 37, count 0 2006.257.20:59:59.95#ibcon#about to read 4, iclass 37, count 0 2006.257.20:59:59.95#ibcon#read 4, iclass 37, count 0 2006.257.20:59:59.95#ibcon#about to read 5, iclass 37, count 0 2006.257.20:59:59.95#ibcon#read 5, iclass 37, count 0 2006.257.20:59:59.95#ibcon#about to read 6, iclass 37, count 0 2006.257.20:59:59.95#ibcon#read 6, iclass 37, count 0 2006.257.20:59:59.95#ibcon#end of sib2, iclass 37, count 0 2006.257.20:59:59.95#ibcon#*mode == 0, iclass 37, count 0 2006.257.20:59:59.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.20:59:59.95#ibcon#[27=BW32\r\n] 2006.257.20:59:59.95#ibcon#*before write, iclass 37, count 0 2006.257.20:59:59.95#ibcon#enter sib2, iclass 37, count 0 2006.257.20:59:59.95#ibcon#flushed, iclass 37, count 0 2006.257.20:59:59.95#ibcon#about to write, iclass 37, count 0 2006.257.20:59:59.95#ibcon#wrote, iclass 37, count 0 2006.257.20:59:59.95#ibcon#about to read 3, iclass 37, count 0 2006.257.20:59:59.98#ibcon#read 3, iclass 37, count 0 2006.257.20:59:59.98#ibcon#about to read 4, iclass 37, count 0 2006.257.20:59:59.98#ibcon#read 4, iclass 37, count 0 2006.257.20:59:59.98#ibcon#about to read 5, iclass 37, count 0 2006.257.20:59:59.98#ibcon#read 5, iclass 37, count 0 2006.257.20:59:59.98#ibcon#about to read 6, iclass 37, count 0 2006.257.20:59:59.98#ibcon#read 6, iclass 37, count 0 2006.257.20:59:59.98#ibcon#end of sib2, iclass 37, count 0 2006.257.20:59:59.98#ibcon#*after write, iclass 37, count 0 2006.257.20:59:59.98#ibcon#*before return 0, iclass 37, count 0 2006.257.20:59:59.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:59:59.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.20:59:59.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.20:59:59.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.20:59:59.98$setupk4/ifdk4 2006.257.20:59:59.98$ifdk4/lo= 2006.257.20:59:59.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.20:59:59.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.20:59:59.98$ifdk4/patch= 2006.257.20:59:59.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.20:59:59.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.20:59:59.98$setupk4/!*+20s 2006.257.21:00:06.86#abcon#<5=/14 0.9 2.4 17.57 961015.2\r\n> 2006.257.21:00:06.88#abcon#{5=INTERFACE CLEAR} 2006.257.21:00:06.94#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:00:11.13#trakl#Source acquired 2006.257.21:00:12.13#flagr#flagr/antenna,acquired 2006.257.21:00:14.48$setupk4/"tpicd 2006.257.21:00:14.48$setupk4/echo=off 2006.257.21:00:14.48$setupk4/xlog=off 2006.257.21:00:14.48:!2006.257.21:02:32 2006.257.21:02:32.00:preob 2006.257.21:02:32.14/onsource/TRACKING 2006.257.21:02:32.14:!2006.257.21:02:42 2006.257.21:02:42.02:"tape 2006.257.21:02:42.02:"st=record 2006.257.21:02:42.02:data_valid=on 2006.257.21:02:42.02:midob 2006.257.21:02:43.14/onsource/TRACKING 2006.257.21:02:43.14/wx/17.67,1015.3,95 2006.257.21:02:43.29/cable/+6.4857E-03 2006.257.21:02:44.38/va/01,08,usb,yes,33,35 2006.257.21:02:44.38/va/02,07,usb,yes,35,36 2006.257.21:02:44.38/va/03,08,usb,yes,32,34 2006.257.21:02:44.38/va/04,07,usb,yes,36,38 2006.257.21:02:44.38/va/05,04,usb,yes,33,33 2006.257.21:02:44.38/va/06,04,usb,yes,36,36 2006.257.21:02:44.38/va/07,04,usb,yes,37,37 2006.257.21:02:44.38/va/08,04,usb,yes,31,38 2006.257.21:02:44.61/valo/01,524.99,yes,locked 2006.257.21:02:44.61/valo/02,534.99,yes,locked 2006.257.21:02:44.61/valo/03,564.99,yes,locked 2006.257.21:02:44.61/valo/04,624.99,yes,locked 2006.257.21:02:44.61/valo/05,734.99,yes,locked 2006.257.21:02:44.61/valo/06,814.99,yes,locked 2006.257.21:02:44.61/valo/07,864.99,yes,locked 2006.257.21:02:44.61/valo/08,884.99,yes,locked 2006.257.21:02:45.70/vb/01,04,usb,yes,31,29 2006.257.21:02:45.70/vb/02,05,usb,yes,30,30 2006.257.21:02:45.70/vb/03,04,usb,yes,31,34 2006.257.21:02:45.70/vb/04,05,usb,yes,31,30 2006.257.21:02:45.70/vb/05,04,usb,yes,27,30 2006.257.21:02:45.70/vb/06,04,usb,yes,32,28 2006.257.21:02:45.70/vb/07,04,usb,yes,32,32 2006.257.21:02:45.70/vb/08,04,usb,yes,29,33 2006.257.21:02:45.93/vblo/01,629.99,yes,locked 2006.257.21:02:45.93/vblo/02,634.99,yes,locked 2006.257.21:02:45.93/vblo/03,649.99,yes,locked 2006.257.21:02:45.93/vblo/04,679.99,yes,locked 2006.257.21:02:45.93/vblo/05,709.99,yes,locked 2006.257.21:02:45.93/vblo/06,719.99,yes,locked 2006.257.21:02:45.93/vblo/07,734.99,yes,locked 2006.257.21:02:45.93/vblo/08,744.99,yes,locked 2006.257.21:02:46.08/vabw/8 2006.257.21:02:46.23/vbbw/8 2006.257.21:02:46.32/xfe/off,on,15.2 2006.257.21:02:46.70/ifatt/23,28,28,28 2006.257.21:02:47.08/fmout-gps/S +4.60E-07 2006.257.21:02:47.11:!2006.257.21:07:02 2006.257.21:07:02.01:data_valid=off 2006.257.21:07:02.02:"et 2006.257.21:07:02.02:!+3s 2006.257.21:07:05.04:"tape 2006.257.21:07:05.04:postob 2006.257.21:07:05.11/cable/+6.4856E-03 2006.257.21:07:05.11/wx/17.74,1015.3,94 2006.257.21:07:05.17/fmout-gps/S +4.59E-07 2006.257.21:07:05.17:scan_name=257-2116,jd0609,310 2006.257.21:07:05.17:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.257.21:07:07.14#flagr#flagr/antenna,new-source 2006.257.21:07:07.14:checkk5 2006.257.21:07:07.52/chk_autoobs//k5ts1/ autoobs is running! 2006.257.21:07:07.86/chk_autoobs//k5ts2/ autoobs is running! 2006.257.21:07:08.21/chk_autoobs//k5ts3/ autoobs is running! 2006.257.21:07:08.55/chk_autoobs//k5ts4/ autoobs is running! 2006.257.21:07:08.87/chk_obsdata//k5ts1/T2572102??a.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.257.21:07:09.21/chk_obsdata//k5ts2/T2572102??b.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.257.21:07:09.54/chk_obsdata//k5ts3/T2572102??c.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.257.21:07:09.88/chk_obsdata//k5ts4/T2572102??d.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.257.21:07:10.53/k5log//k5ts1_log_newline 2006.257.21:07:11.20/k5log//k5ts2_log_newline 2006.257.21:07:11.85/k5log//k5ts3_log_newline 2006.257.21:07:12.51/k5log//k5ts4_log_newline 2006.257.21:07:12.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.21:07:12.53:setupk4=1 2006.257.21:07:12.53$setupk4/echo=on 2006.257.21:07:12.53$setupk4/pcalon 2006.257.21:07:12.53$pcalon/"no phase cal control is implemented here 2006.257.21:07:12.53$setupk4/"tpicd=stop 2006.257.21:07:12.53$setupk4/"rec=synch_on 2006.257.21:07:12.53$setupk4/"rec_mode=128 2006.257.21:07:12.53$setupk4/!* 2006.257.21:07:12.53$setupk4/recpk4 2006.257.21:07:12.53$recpk4/recpatch= 2006.257.21:07:12.54$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.21:07:12.54$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.21:07:12.54$setupk4/vck44 2006.257.21:07:12.54$vck44/valo=1,524.99 2006.257.21:07:12.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.21:07:12.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.21:07:12.54#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:12.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:12.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:12.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:12.54#ibcon#enter wrdev, iclass 30, count 0 2006.257.21:07:12.54#ibcon#first serial, iclass 30, count 0 2006.257.21:07:12.54#ibcon#enter sib2, iclass 30, count 0 2006.257.21:07:12.54#ibcon#flushed, iclass 30, count 0 2006.257.21:07:12.54#ibcon#about to write, iclass 30, count 0 2006.257.21:07:12.54#ibcon#wrote, iclass 30, count 0 2006.257.21:07:12.54#ibcon#about to read 3, iclass 30, count 0 2006.257.21:07:12.55#ibcon#read 3, iclass 30, count 0 2006.257.21:07:12.55#ibcon#about to read 4, iclass 30, count 0 2006.257.21:07:12.55#ibcon#read 4, iclass 30, count 0 2006.257.21:07:12.55#ibcon#about to read 5, iclass 30, count 0 2006.257.21:07:12.55#ibcon#read 5, iclass 30, count 0 2006.257.21:07:12.55#ibcon#about to read 6, iclass 30, count 0 2006.257.21:07:12.55#ibcon#read 6, iclass 30, count 0 2006.257.21:07:12.55#ibcon#end of sib2, iclass 30, count 0 2006.257.21:07:12.55#ibcon#*mode == 0, iclass 30, count 0 2006.257.21:07:12.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.21:07:12.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.21:07:12.55#ibcon#*before write, iclass 30, count 0 2006.257.21:07:12.55#ibcon#enter sib2, iclass 30, count 0 2006.257.21:07:12.55#ibcon#flushed, iclass 30, count 0 2006.257.21:07:12.55#ibcon#about to write, iclass 30, count 0 2006.257.21:07:12.55#ibcon#wrote, iclass 30, count 0 2006.257.21:07:12.55#ibcon#about to read 3, iclass 30, count 0 2006.257.21:07:12.60#ibcon#read 3, iclass 30, count 0 2006.257.21:07:12.60#ibcon#about to read 4, iclass 30, count 0 2006.257.21:07:12.60#ibcon#read 4, iclass 30, count 0 2006.257.21:07:12.60#ibcon#about to read 5, iclass 30, count 0 2006.257.21:07:12.60#ibcon#read 5, iclass 30, count 0 2006.257.21:07:12.60#ibcon#about to read 6, iclass 30, count 0 2006.257.21:07:12.60#ibcon#read 6, iclass 30, count 0 2006.257.21:07:12.60#ibcon#end of sib2, iclass 30, count 0 2006.257.21:07:12.60#ibcon#*after write, iclass 30, count 0 2006.257.21:07:12.60#ibcon#*before return 0, iclass 30, count 0 2006.257.21:07:12.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:12.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:12.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.21:07:12.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.21:07:12.60$vck44/va=1,8 2006.257.21:07:12.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.21:07:12.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.21:07:12.60#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:12.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:12.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:12.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:12.60#ibcon#enter wrdev, iclass 32, count 2 2006.257.21:07:12.60#ibcon#first serial, iclass 32, count 2 2006.257.21:07:12.60#ibcon#enter sib2, iclass 32, count 2 2006.257.21:07:12.60#ibcon#flushed, iclass 32, count 2 2006.257.21:07:12.60#ibcon#about to write, iclass 32, count 2 2006.257.21:07:12.60#ibcon#wrote, iclass 32, count 2 2006.257.21:07:12.60#ibcon#about to read 3, iclass 32, count 2 2006.257.21:07:12.62#ibcon#read 3, iclass 32, count 2 2006.257.21:07:12.62#ibcon#about to read 4, iclass 32, count 2 2006.257.21:07:12.62#ibcon#read 4, iclass 32, count 2 2006.257.21:07:12.62#ibcon#about to read 5, iclass 32, count 2 2006.257.21:07:12.62#ibcon#read 5, iclass 32, count 2 2006.257.21:07:12.62#ibcon#about to read 6, iclass 32, count 2 2006.257.21:07:12.62#ibcon#read 6, iclass 32, count 2 2006.257.21:07:12.62#ibcon#end of sib2, iclass 32, count 2 2006.257.21:07:12.62#ibcon#*mode == 0, iclass 32, count 2 2006.257.21:07:12.62#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.21:07:12.62#ibcon#[25=AT01-08\r\n] 2006.257.21:07:12.62#ibcon#*before write, iclass 32, count 2 2006.257.21:07:12.62#ibcon#enter sib2, iclass 32, count 2 2006.257.21:07:12.62#ibcon#flushed, iclass 32, count 2 2006.257.21:07:12.62#ibcon#about to write, iclass 32, count 2 2006.257.21:07:12.62#ibcon#wrote, iclass 32, count 2 2006.257.21:07:12.62#ibcon#about to read 3, iclass 32, count 2 2006.257.21:07:12.65#ibcon#read 3, iclass 32, count 2 2006.257.21:07:12.65#ibcon#about to read 4, iclass 32, count 2 2006.257.21:07:12.65#ibcon#read 4, iclass 32, count 2 2006.257.21:07:12.65#ibcon#about to read 5, iclass 32, count 2 2006.257.21:07:12.65#ibcon#read 5, iclass 32, count 2 2006.257.21:07:12.65#ibcon#about to read 6, iclass 32, count 2 2006.257.21:07:12.65#ibcon#read 6, iclass 32, count 2 2006.257.21:07:12.65#ibcon#end of sib2, iclass 32, count 2 2006.257.21:07:12.65#ibcon#*after write, iclass 32, count 2 2006.257.21:07:12.65#ibcon#*before return 0, iclass 32, count 2 2006.257.21:07:12.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:12.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:12.65#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.21:07:12.65#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:12.65#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:12.77#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:12.77#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:12.77#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:07:12.77#ibcon#first serial, iclass 32, count 0 2006.257.21:07:12.77#ibcon#enter sib2, iclass 32, count 0 2006.257.21:07:12.77#ibcon#flushed, iclass 32, count 0 2006.257.21:07:12.77#ibcon#about to write, iclass 32, count 0 2006.257.21:07:12.77#ibcon#wrote, iclass 32, count 0 2006.257.21:07:12.77#ibcon#about to read 3, iclass 32, count 0 2006.257.21:07:12.79#ibcon#read 3, iclass 32, count 0 2006.257.21:07:12.79#ibcon#about to read 4, iclass 32, count 0 2006.257.21:07:12.79#ibcon#read 4, iclass 32, count 0 2006.257.21:07:12.79#ibcon#about to read 5, iclass 32, count 0 2006.257.21:07:12.79#ibcon#read 5, iclass 32, count 0 2006.257.21:07:12.79#ibcon#about to read 6, iclass 32, count 0 2006.257.21:07:12.79#ibcon#read 6, iclass 32, count 0 2006.257.21:07:12.79#ibcon#end of sib2, iclass 32, count 0 2006.257.21:07:12.79#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:07:12.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:07:12.79#ibcon#[25=USB\r\n] 2006.257.21:07:12.79#ibcon#*before write, iclass 32, count 0 2006.257.21:07:12.79#ibcon#enter sib2, iclass 32, count 0 2006.257.21:07:12.79#ibcon#flushed, iclass 32, count 0 2006.257.21:07:12.79#ibcon#about to write, iclass 32, count 0 2006.257.21:07:12.79#ibcon#wrote, iclass 32, count 0 2006.257.21:07:12.79#ibcon#about to read 3, iclass 32, count 0 2006.257.21:07:12.82#ibcon#read 3, iclass 32, count 0 2006.257.21:07:12.82#ibcon#about to read 4, iclass 32, count 0 2006.257.21:07:12.82#ibcon#read 4, iclass 32, count 0 2006.257.21:07:12.82#ibcon#about to read 5, iclass 32, count 0 2006.257.21:07:12.82#ibcon#read 5, iclass 32, count 0 2006.257.21:07:12.82#ibcon#about to read 6, iclass 32, count 0 2006.257.21:07:12.82#ibcon#read 6, iclass 32, count 0 2006.257.21:07:12.82#ibcon#end of sib2, iclass 32, count 0 2006.257.21:07:12.82#ibcon#*after write, iclass 32, count 0 2006.257.21:07:12.82#ibcon#*before return 0, iclass 32, count 0 2006.257.21:07:12.82#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:12.82#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:12.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:07:12.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:07:12.82$vck44/valo=2,534.99 2006.257.21:07:12.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.21:07:12.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.21:07:12.82#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:12.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:12.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:12.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:12.82#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:07:12.82#ibcon#first serial, iclass 34, count 0 2006.257.21:07:12.82#ibcon#enter sib2, iclass 34, count 0 2006.257.21:07:12.82#ibcon#flushed, iclass 34, count 0 2006.257.21:07:12.82#ibcon#about to write, iclass 34, count 0 2006.257.21:07:12.82#ibcon#wrote, iclass 34, count 0 2006.257.21:07:12.82#ibcon#about to read 3, iclass 34, count 0 2006.257.21:07:12.84#ibcon#read 3, iclass 34, count 0 2006.257.21:07:12.84#ibcon#about to read 4, iclass 34, count 0 2006.257.21:07:12.84#ibcon#read 4, iclass 34, count 0 2006.257.21:07:12.84#ibcon#about to read 5, iclass 34, count 0 2006.257.21:07:12.84#ibcon#read 5, iclass 34, count 0 2006.257.21:07:12.84#ibcon#about to read 6, iclass 34, count 0 2006.257.21:07:12.84#ibcon#read 6, iclass 34, count 0 2006.257.21:07:12.84#ibcon#end of sib2, iclass 34, count 0 2006.257.21:07:12.84#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:07:12.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:07:12.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.21:07:12.84#ibcon#*before write, iclass 34, count 0 2006.257.21:07:12.84#ibcon#enter sib2, iclass 34, count 0 2006.257.21:07:12.84#ibcon#flushed, iclass 34, count 0 2006.257.21:07:12.84#ibcon#about to write, iclass 34, count 0 2006.257.21:07:12.84#ibcon#wrote, iclass 34, count 0 2006.257.21:07:12.84#ibcon#about to read 3, iclass 34, count 0 2006.257.21:07:12.88#ibcon#read 3, iclass 34, count 0 2006.257.21:07:12.88#ibcon#about to read 4, iclass 34, count 0 2006.257.21:07:12.88#ibcon#read 4, iclass 34, count 0 2006.257.21:07:12.88#ibcon#about to read 5, iclass 34, count 0 2006.257.21:07:12.88#ibcon#read 5, iclass 34, count 0 2006.257.21:07:12.88#ibcon#about to read 6, iclass 34, count 0 2006.257.21:07:12.88#ibcon#read 6, iclass 34, count 0 2006.257.21:07:12.88#ibcon#end of sib2, iclass 34, count 0 2006.257.21:07:12.88#ibcon#*after write, iclass 34, count 0 2006.257.21:07:12.88#ibcon#*before return 0, iclass 34, count 0 2006.257.21:07:12.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:12.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:12.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:07:12.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:07:12.88$vck44/va=2,7 2006.257.21:07:12.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.21:07:12.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.21:07:12.88#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:12.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:12.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:12.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:12.94#ibcon#enter wrdev, iclass 36, count 2 2006.257.21:07:12.94#ibcon#first serial, iclass 36, count 2 2006.257.21:07:12.94#ibcon#enter sib2, iclass 36, count 2 2006.257.21:07:12.94#ibcon#flushed, iclass 36, count 2 2006.257.21:07:12.94#ibcon#about to write, iclass 36, count 2 2006.257.21:07:12.94#ibcon#wrote, iclass 36, count 2 2006.257.21:07:12.94#ibcon#about to read 3, iclass 36, count 2 2006.257.21:07:12.96#ibcon#read 3, iclass 36, count 2 2006.257.21:07:12.96#ibcon#about to read 4, iclass 36, count 2 2006.257.21:07:12.96#ibcon#read 4, iclass 36, count 2 2006.257.21:07:12.96#ibcon#about to read 5, iclass 36, count 2 2006.257.21:07:12.96#ibcon#read 5, iclass 36, count 2 2006.257.21:07:12.96#ibcon#about to read 6, iclass 36, count 2 2006.257.21:07:12.96#ibcon#read 6, iclass 36, count 2 2006.257.21:07:12.96#ibcon#end of sib2, iclass 36, count 2 2006.257.21:07:12.96#ibcon#*mode == 0, iclass 36, count 2 2006.257.21:07:12.96#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.21:07:12.96#ibcon#[25=AT02-07\r\n] 2006.257.21:07:12.96#ibcon#*before write, iclass 36, count 2 2006.257.21:07:12.96#ibcon#enter sib2, iclass 36, count 2 2006.257.21:07:12.96#ibcon#flushed, iclass 36, count 2 2006.257.21:07:12.96#ibcon#about to write, iclass 36, count 2 2006.257.21:07:12.96#ibcon#wrote, iclass 36, count 2 2006.257.21:07:12.96#ibcon#about to read 3, iclass 36, count 2 2006.257.21:07:12.99#ibcon#read 3, iclass 36, count 2 2006.257.21:07:12.99#ibcon#about to read 4, iclass 36, count 2 2006.257.21:07:12.99#ibcon#read 4, iclass 36, count 2 2006.257.21:07:12.99#ibcon#about to read 5, iclass 36, count 2 2006.257.21:07:12.99#ibcon#read 5, iclass 36, count 2 2006.257.21:07:12.99#ibcon#about to read 6, iclass 36, count 2 2006.257.21:07:12.99#ibcon#read 6, iclass 36, count 2 2006.257.21:07:12.99#ibcon#end of sib2, iclass 36, count 2 2006.257.21:07:12.99#ibcon#*after write, iclass 36, count 2 2006.257.21:07:12.99#ibcon#*before return 0, iclass 36, count 2 2006.257.21:07:12.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:12.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:12.99#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.21:07:12.99#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:12.99#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:13.11#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:13.11#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:13.11#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:07:13.11#ibcon#first serial, iclass 36, count 0 2006.257.21:07:13.11#ibcon#enter sib2, iclass 36, count 0 2006.257.21:07:13.11#ibcon#flushed, iclass 36, count 0 2006.257.21:07:13.11#ibcon#about to write, iclass 36, count 0 2006.257.21:07:13.11#ibcon#wrote, iclass 36, count 0 2006.257.21:07:13.11#ibcon#about to read 3, iclass 36, count 0 2006.257.21:07:13.13#ibcon#read 3, iclass 36, count 0 2006.257.21:07:13.13#ibcon#about to read 4, iclass 36, count 0 2006.257.21:07:13.13#ibcon#read 4, iclass 36, count 0 2006.257.21:07:13.13#ibcon#about to read 5, iclass 36, count 0 2006.257.21:07:13.13#ibcon#read 5, iclass 36, count 0 2006.257.21:07:13.13#ibcon#about to read 6, iclass 36, count 0 2006.257.21:07:13.13#ibcon#read 6, iclass 36, count 0 2006.257.21:07:13.13#ibcon#end of sib2, iclass 36, count 0 2006.257.21:07:13.13#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:07:13.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:07:13.13#ibcon#[25=USB\r\n] 2006.257.21:07:13.13#ibcon#*before write, iclass 36, count 0 2006.257.21:07:13.13#ibcon#enter sib2, iclass 36, count 0 2006.257.21:07:13.13#ibcon#flushed, iclass 36, count 0 2006.257.21:07:13.13#ibcon#about to write, iclass 36, count 0 2006.257.21:07:13.13#ibcon#wrote, iclass 36, count 0 2006.257.21:07:13.13#ibcon#about to read 3, iclass 36, count 0 2006.257.21:07:13.16#ibcon#read 3, iclass 36, count 0 2006.257.21:07:13.16#ibcon#about to read 4, iclass 36, count 0 2006.257.21:07:13.16#ibcon#read 4, iclass 36, count 0 2006.257.21:07:13.16#ibcon#about to read 5, iclass 36, count 0 2006.257.21:07:13.16#ibcon#read 5, iclass 36, count 0 2006.257.21:07:13.16#ibcon#about to read 6, iclass 36, count 0 2006.257.21:07:13.16#ibcon#read 6, iclass 36, count 0 2006.257.21:07:13.16#ibcon#end of sib2, iclass 36, count 0 2006.257.21:07:13.16#ibcon#*after write, iclass 36, count 0 2006.257.21:07:13.16#ibcon#*before return 0, iclass 36, count 0 2006.257.21:07:13.16#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:13.16#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:13.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:07:13.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:07:13.16$vck44/valo=3,564.99 2006.257.21:07:13.16#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.21:07:13.16#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.21:07:13.16#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:13.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:13.16#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:13.16#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:13.16#ibcon#enter wrdev, iclass 38, count 0 2006.257.21:07:13.16#ibcon#first serial, iclass 38, count 0 2006.257.21:07:13.16#ibcon#enter sib2, iclass 38, count 0 2006.257.21:07:13.16#ibcon#flushed, iclass 38, count 0 2006.257.21:07:13.16#ibcon#about to write, iclass 38, count 0 2006.257.21:07:13.16#ibcon#wrote, iclass 38, count 0 2006.257.21:07:13.16#ibcon#about to read 3, iclass 38, count 0 2006.257.21:07:13.18#ibcon#read 3, iclass 38, count 0 2006.257.21:07:13.18#ibcon#about to read 4, iclass 38, count 0 2006.257.21:07:13.18#ibcon#read 4, iclass 38, count 0 2006.257.21:07:13.18#ibcon#about to read 5, iclass 38, count 0 2006.257.21:07:13.18#ibcon#read 5, iclass 38, count 0 2006.257.21:07:13.18#ibcon#about to read 6, iclass 38, count 0 2006.257.21:07:13.18#ibcon#read 6, iclass 38, count 0 2006.257.21:07:13.18#ibcon#end of sib2, iclass 38, count 0 2006.257.21:07:13.18#ibcon#*mode == 0, iclass 38, count 0 2006.257.21:07:13.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.21:07:13.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.21:07:13.18#ibcon#*before write, iclass 38, count 0 2006.257.21:07:13.18#ibcon#enter sib2, iclass 38, count 0 2006.257.21:07:13.18#ibcon#flushed, iclass 38, count 0 2006.257.21:07:13.18#ibcon#about to write, iclass 38, count 0 2006.257.21:07:13.18#ibcon#wrote, iclass 38, count 0 2006.257.21:07:13.18#ibcon#about to read 3, iclass 38, count 0 2006.257.21:07:13.22#ibcon#read 3, iclass 38, count 0 2006.257.21:07:13.22#ibcon#about to read 4, iclass 38, count 0 2006.257.21:07:13.22#ibcon#read 4, iclass 38, count 0 2006.257.21:07:13.22#ibcon#about to read 5, iclass 38, count 0 2006.257.21:07:13.22#ibcon#read 5, iclass 38, count 0 2006.257.21:07:13.22#ibcon#about to read 6, iclass 38, count 0 2006.257.21:07:13.22#ibcon#read 6, iclass 38, count 0 2006.257.21:07:13.22#ibcon#end of sib2, iclass 38, count 0 2006.257.21:07:13.22#ibcon#*after write, iclass 38, count 0 2006.257.21:07:13.22#ibcon#*before return 0, iclass 38, count 0 2006.257.21:07:13.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:13.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:13.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.21:07:13.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.21:07:13.22$vck44/va=3,8 2006.257.21:07:13.22#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.21:07:13.22#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.21:07:13.22#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:13.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:13.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:13.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:13.28#ibcon#enter wrdev, iclass 40, count 2 2006.257.21:07:13.28#ibcon#first serial, iclass 40, count 2 2006.257.21:07:13.28#ibcon#enter sib2, iclass 40, count 2 2006.257.21:07:13.28#ibcon#flushed, iclass 40, count 2 2006.257.21:07:13.28#ibcon#about to write, iclass 40, count 2 2006.257.21:07:13.28#ibcon#wrote, iclass 40, count 2 2006.257.21:07:13.28#ibcon#about to read 3, iclass 40, count 2 2006.257.21:07:13.30#ibcon#read 3, iclass 40, count 2 2006.257.21:07:13.30#ibcon#about to read 4, iclass 40, count 2 2006.257.21:07:13.30#ibcon#read 4, iclass 40, count 2 2006.257.21:07:13.30#ibcon#about to read 5, iclass 40, count 2 2006.257.21:07:13.30#ibcon#read 5, iclass 40, count 2 2006.257.21:07:13.30#ibcon#about to read 6, iclass 40, count 2 2006.257.21:07:13.30#ibcon#read 6, iclass 40, count 2 2006.257.21:07:13.30#ibcon#end of sib2, iclass 40, count 2 2006.257.21:07:13.30#ibcon#*mode == 0, iclass 40, count 2 2006.257.21:07:13.30#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.21:07:13.30#ibcon#[25=AT03-08\r\n] 2006.257.21:07:13.30#ibcon#*before write, iclass 40, count 2 2006.257.21:07:13.30#ibcon#enter sib2, iclass 40, count 2 2006.257.21:07:13.30#ibcon#flushed, iclass 40, count 2 2006.257.21:07:13.30#ibcon#about to write, iclass 40, count 2 2006.257.21:07:13.30#ibcon#wrote, iclass 40, count 2 2006.257.21:07:13.30#ibcon#about to read 3, iclass 40, count 2 2006.257.21:07:13.33#ibcon#read 3, iclass 40, count 2 2006.257.21:07:13.33#ibcon#about to read 4, iclass 40, count 2 2006.257.21:07:13.33#ibcon#read 4, iclass 40, count 2 2006.257.21:07:13.33#ibcon#about to read 5, iclass 40, count 2 2006.257.21:07:13.33#ibcon#read 5, iclass 40, count 2 2006.257.21:07:13.33#ibcon#about to read 6, iclass 40, count 2 2006.257.21:07:13.33#ibcon#read 6, iclass 40, count 2 2006.257.21:07:13.33#ibcon#end of sib2, iclass 40, count 2 2006.257.21:07:13.33#ibcon#*after write, iclass 40, count 2 2006.257.21:07:13.33#ibcon#*before return 0, iclass 40, count 2 2006.257.21:07:13.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:13.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:13.33#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.21:07:13.33#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:13.33#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:13.45#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:13.45#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:13.45#ibcon#enter wrdev, iclass 40, count 0 2006.257.21:07:13.45#ibcon#first serial, iclass 40, count 0 2006.257.21:07:13.45#ibcon#enter sib2, iclass 40, count 0 2006.257.21:07:13.45#ibcon#flushed, iclass 40, count 0 2006.257.21:07:13.45#ibcon#about to write, iclass 40, count 0 2006.257.21:07:13.45#ibcon#wrote, iclass 40, count 0 2006.257.21:07:13.45#ibcon#about to read 3, iclass 40, count 0 2006.257.21:07:13.47#ibcon#read 3, iclass 40, count 0 2006.257.21:07:13.47#ibcon#about to read 4, iclass 40, count 0 2006.257.21:07:13.47#ibcon#read 4, iclass 40, count 0 2006.257.21:07:13.47#ibcon#about to read 5, iclass 40, count 0 2006.257.21:07:13.47#ibcon#read 5, iclass 40, count 0 2006.257.21:07:13.47#ibcon#about to read 6, iclass 40, count 0 2006.257.21:07:13.47#ibcon#read 6, iclass 40, count 0 2006.257.21:07:13.47#ibcon#end of sib2, iclass 40, count 0 2006.257.21:07:13.47#ibcon#*mode == 0, iclass 40, count 0 2006.257.21:07:13.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.21:07:13.47#ibcon#[25=USB\r\n] 2006.257.21:07:13.47#ibcon#*before write, iclass 40, count 0 2006.257.21:07:13.47#ibcon#enter sib2, iclass 40, count 0 2006.257.21:07:13.47#ibcon#flushed, iclass 40, count 0 2006.257.21:07:13.47#ibcon#about to write, iclass 40, count 0 2006.257.21:07:13.47#ibcon#wrote, iclass 40, count 0 2006.257.21:07:13.47#ibcon#about to read 3, iclass 40, count 0 2006.257.21:07:13.50#ibcon#read 3, iclass 40, count 0 2006.257.21:07:13.50#ibcon#about to read 4, iclass 40, count 0 2006.257.21:07:13.50#ibcon#read 4, iclass 40, count 0 2006.257.21:07:13.50#ibcon#about to read 5, iclass 40, count 0 2006.257.21:07:13.50#ibcon#read 5, iclass 40, count 0 2006.257.21:07:13.50#ibcon#about to read 6, iclass 40, count 0 2006.257.21:07:13.50#ibcon#read 6, iclass 40, count 0 2006.257.21:07:13.50#ibcon#end of sib2, iclass 40, count 0 2006.257.21:07:13.50#ibcon#*after write, iclass 40, count 0 2006.257.21:07:13.50#ibcon#*before return 0, iclass 40, count 0 2006.257.21:07:13.50#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:13.50#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:13.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.21:07:13.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.21:07:13.50$vck44/valo=4,624.99 2006.257.21:07:13.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.21:07:13.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.21:07:13.50#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:13.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:13.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:13.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:13.50#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:07:13.50#ibcon#first serial, iclass 4, count 0 2006.257.21:07:13.50#ibcon#enter sib2, iclass 4, count 0 2006.257.21:07:13.50#ibcon#flushed, iclass 4, count 0 2006.257.21:07:13.50#ibcon#about to write, iclass 4, count 0 2006.257.21:07:13.50#ibcon#wrote, iclass 4, count 0 2006.257.21:07:13.50#ibcon#about to read 3, iclass 4, count 0 2006.257.21:07:13.52#ibcon#read 3, iclass 4, count 0 2006.257.21:07:13.52#ibcon#about to read 4, iclass 4, count 0 2006.257.21:07:13.52#ibcon#read 4, iclass 4, count 0 2006.257.21:07:13.52#ibcon#about to read 5, iclass 4, count 0 2006.257.21:07:13.52#ibcon#read 5, iclass 4, count 0 2006.257.21:07:13.52#ibcon#about to read 6, iclass 4, count 0 2006.257.21:07:13.52#ibcon#read 6, iclass 4, count 0 2006.257.21:07:13.52#ibcon#end of sib2, iclass 4, count 0 2006.257.21:07:13.52#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:07:13.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:07:13.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.21:07:13.52#ibcon#*before write, iclass 4, count 0 2006.257.21:07:13.52#ibcon#enter sib2, iclass 4, count 0 2006.257.21:07:13.52#ibcon#flushed, iclass 4, count 0 2006.257.21:07:13.52#ibcon#about to write, iclass 4, count 0 2006.257.21:07:13.52#ibcon#wrote, iclass 4, count 0 2006.257.21:07:13.52#ibcon#about to read 3, iclass 4, count 0 2006.257.21:07:13.56#ibcon#read 3, iclass 4, count 0 2006.257.21:07:13.56#ibcon#about to read 4, iclass 4, count 0 2006.257.21:07:13.56#ibcon#read 4, iclass 4, count 0 2006.257.21:07:13.56#ibcon#about to read 5, iclass 4, count 0 2006.257.21:07:13.56#ibcon#read 5, iclass 4, count 0 2006.257.21:07:13.56#ibcon#about to read 6, iclass 4, count 0 2006.257.21:07:13.56#ibcon#read 6, iclass 4, count 0 2006.257.21:07:13.56#ibcon#end of sib2, iclass 4, count 0 2006.257.21:07:13.56#ibcon#*after write, iclass 4, count 0 2006.257.21:07:13.56#ibcon#*before return 0, iclass 4, count 0 2006.257.21:07:13.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:13.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:13.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:07:13.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:07:13.56$vck44/va=4,7 2006.257.21:07:13.56#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.21:07:13.56#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.21:07:13.56#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:13.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:13.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:13.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:13.62#ibcon#enter wrdev, iclass 6, count 2 2006.257.21:07:13.62#ibcon#first serial, iclass 6, count 2 2006.257.21:07:13.62#ibcon#enter sib2, iclass 6, count 2 2006.257.21:07:13.62#ibcon#flushed, iclass 6, count 2 2006.257.21:07:13.62#ibcon#about to write, iclass 6, count 2 2006.257.21:07:13.62#ibcon#wrote, iclass 6, count 2 2006.257.21:07:13.62#ibcon#about to read 3, iclass 6, count 2 2006.257.21:07:13.64#ibcon#read 3, iclass 6, count 2 2006.257.21:07:13.64#ibcon#about to read 4, iclass 6, count 2 2006.257.21:07:13.64#ibcon#read 4, iclass 6, count 2 2006.257.21:07:13.64#ibcon#about to read 5, iclass 6, count 2 2006.257.21:07:13.64#ibcon#read 5, iclass 6, count 2 2006.257.21:07:13.64#ibcon#about to read 6, iclass 6, count 2 2006.257.21:07:13.64#ibcon#read 6, iclass 6, count 2 2006.257.21:07:13.64#ibcon#end of sib2, iclass 6, count 2 2006.257.21:07:13.64#ibcon#*mode == 0, iclass 6, count 2 2006.257.21:07:13.64#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.21:07:13.64#ibcon#[25=AT04-07\r\n] 2006.257.21:07:13.64#ibcon#*before write, iclass 6, count 2 2006.257.21:07:13.64#ibcon#enter sib2, iclass 6, count 2 2006.257.21:07:13.64#ibcon#flushed, iclass 6, count 2 2006.257.21:07:13.64#ibcon#about to write, iclass 6, count 2 2006.257.21:07:13.64#ibcon#wrote, iclass 6, count 2 2006.257.21:07:13.64#ibcon#about to read 3, iclass 6, count 2 2006.257.21:07:13.67#ibcon#read 3, iclass 6, count 2 2006.257.21:07:13.67#ibcon#about to read 4, iclass 6, count 2 2006.257.21:07:13.67#ibcon#read 4, iclass 6, count 2 2006.257.21:07:13.67#ibcon#about to read 5, iclass 6, count 2 2006.257.21:07:13.67#ibcon#read 5, iclass 6, count 2 2006.257.21:07:13.67#ibcon#about to read 6, iclass 6, count 2 2006.257.21:07:13.67#ibcon#read 6, iclass 6, count 2 2006.257.21:07:13.67#ibcon#end of sib2, iclass 6, count 2 2006.257.21:07:13.67#ibcon#*after write, iclass 6, count 2 2006.257.21:07:13.67#ibcon#*before return 0, iclass 6, count 2 2006.257.21:07:13.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:13.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:13.67#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.21:07:13.67#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:13.67#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:13.79#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:13.79#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:13.79#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:07:13.79#ibcon#first serial, iclass 6, count 0 2006.257.21:07:13.79#ibcon#enter sib2, iclass 6, count 0 2006.257.21:07:13.79#ibcon#flushed, iclass 6, count 0 2006.257.21:07:13.79#ibcon#about to write, iclass 6, count 0 2006.257.21:07:13.79#ibcon#wrote, iclass 6, count 0 2006.257.21:07:13.79#ibcon#about to read 3, iclass 6, count 0 2006.257.21:07:13.81#ibcon#read 3, iclass 6, count 0 2006.257.21:07:13.81#ibcon#about to read 4, iclass 6, count 0 2006.257.21:07:13.81#ibcon#read 4, iclass 6, count 0 2006.257.21:07:13.81#ibcon#about to read 5, iclass 6, count 0 2006.257.21:07:13.81#ibcon#read 5, iclass 6, count 0 2006.257.21:07:13.81#ibcon#about to read 6, iclass 6, count 0 2006.257.21:07:13.81#ibcon#read 6, iclass 6, count 0 2006.257.21:07:13.81#ibcon#end of sib2, iclass 6, count 0 2006.257.21:07:13.81#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:07:13.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:07:13.81#ibcon#[25=USB\r\n] 2006.257.21:07:13.81#ibcon#*before write, iclass 6, count 0 2006.257.21:07:13.81#ibcon#enter sib2, iclass 6, count 0 2006.257.21:07:13.81#ibcon#flushed, iclass 6, count 0 2006.257.21:07:13.81#ibcon#about to write, iclass 6, count 0 2006.257.21:07:13.81#ibcon#wrote, iclass 6, count 0 2006.257.21:07:13.81#ibcon#about to read 3, iclass 6, count 0 2006.257.21:07:13.84#ibcon#read 3, iclass 6, count 0 2006.257.21:07:13.84#ibcon#about to read 4, iclass 6, count 0 2006.257.21:07:13.84#ibcon#read 4, iclass 6, count 0 2006.257.21:07:13.84#ibcon#about to read 5, iclass 6, count 0 2006.257.21:07:13.84#ibcon#read 5, iclass 6, count 0 2006.257.21:07:13.84#ibcon#about to read 6, iclass 6, count 0 2006.257.21:07:13.84#ibcon#read 6, iclass 6, count 0 2006.257.21:07:13.84#ibcon#end of sib2, iclass 6, count 0 2006.257.21:07:13.84#ibcon#*after write, iclass 6, count 0 2006.257.21:07:13.84#ibcon#*before return 0, iclass 6, count 0 2006.257.21:07:13.84#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:13.84#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:13.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:07:13.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:07:13.84$vck44/valo=5,734.99 2006.257.21:07:13.84#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.21:07:13.84#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.21:07:13.84#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:13.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:13.84#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:13.84#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:13.84#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:07:13.84#ibcon#first serial, iclass 10, count 0 2006.257.21:07:13.84#ibcon#enter sib2, iclass 10, count 0 2006.257.21:07:13.84#ibcon#flushed, iclass 10, count 0 2006.257.21:07:13.84#ibcon#about to write, iclass 10, count 0 2006.257.21:07:13.84#ibcon#wrote, iclass 10, count 0 2006.257.21:07:13.84#ibcon#about to read 3, iclass 10, count 0 2006.257.21:07:13.86#ibcon#read 3, iclass 10, count 0 2006.257.21:07:13.86#ibcon#about to read 4, iclass 10, count 0 2006.257.21:07:13.86#ibcon#read 4, iclass 10, count 0 2006.257.21:07:13.86#ibcon#about to read 5, iclass 10, count 0 2006.257.21:07:13.86#ibcon#read 5, iclass 10, count 0 2006.257.21:07:13.86#ibcon#about to read 6, iclass 10, count 0 2006.257.21:07:13.86#ibcon#read 6, iclass 10, count 0 2006.257.21:07:13.86#ibcon#end of sib2, iclass 10, count 0 2006.257.21:07:13.86#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:07:13.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:07:13.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.21:07:13.86#ibcon#*before write, iclass 10, count 0 2006.257.21:07:13.86#ibcon#enter sib2, iclass 10, count 0 2006.257.21:07:13.86#ibcon#flushed, iclass 10, count 0 2006.257.21:07:13.86#ibcon#about to write, iclass 10, count 0 2006.257.21:07:13.86#ibcon#wrote, iclass 10, count 0 2006.257.21:07:13.86#ibcon#about to read 3, iclass 10, count 0 2006.257.21:07:13.90#ibcon#read 3, iclass 10, count 0 2006.257.21:07:13.90#ibcon#about to read 4, iclass 10, count 0 2006.257.21:07:13.90#ibcon#read 4, iclass 10, count 0 2006.257.21:07:13.90#ibcon#about to read 5, iclass 10, count 0 2006.257.21:07:13.90#ibcon#read 5, iclass 10, count 0 2006.257.21:07:13.90#ibcon#about to read 6, iclass 10, count 0 2006.257.21:07:13.90#ibcon#read 6, iclass 10, count 0 2006.257.21:07:13.90#ibcon#end of sib2, iclass 10, count 0 2006.257.21:07:13.90#ibcon#*after write, iclass 10, count 0 2006.257.21:07:13.90#ibcon#*before return 0, iclass 10, count 0 2006.257.21:07:13.90#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:13.90#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:13.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:07:13.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:07:13.90$vck44/va=5,4 2006.257.21:07:13.90#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.21:07:13.90#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.21:07:13.90#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:13.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:13.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:13.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:13.96#ibcon#enter wrdev, iclass 12, count 2 2006.257.21:07:13.96#ibcon#first serial, iclass 12, count 2 2006.257.21:07:13.96#ibcon#enter sib2, iclass 12, count 2 2006.257.21:07:13.96#ibcon#flushed, iclass 12, count 2 2006.257.21:07:13.96#ibcon#about to write, iclass 12, count 2 2006.257.21:07:13.96#ibcon#wrote, iclass 12, count 2 2006.257.21:07:13.96#ibcon#about to read 3, iclass 12, count 2 2006.257.21:07:13.98#ibcon#read 3, iclass 12, count 2 2006.257.21:07:13.98#ibcon#about to read 4, iclass 12, count 2 2006.257.21:07:13.98#ibcon#read 4, iclass 12, count 2 2006.257.21:07:13.98#ibcon#about to read 5, iclass 12, count 2 2006.257.21:07:13.98#ibcon#read 5, iclass 12, count 2 2006.257.21:07:13.98#ibcon#about to read 6, iclass 12, count 2 2006.257.21:07:13.98#ibcon#read 6, iclass 12, count 2 2006.257.21:07:13.98#ibcon#end of sib2, iclass 12, count 2 2006.257.21:07:13.98#ibcon#*mode == 0, iclass 12, count 2 2006.257.21:07:13.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.21:07:13.98#ibcon#[25=AT05-04\r\n] 2006.257.21:07:13.98#ibcon#*before write, iclass 12, count 2 2006.257.21:07:13.98#ibcon#enter sib2, iclass 12, count 2 2006.257.21:07:13.98#ibcon#flushed, iclass 12, count 2 2006.257.21:07:13.98#ibcon#about to write, iclass 12, count 2 2006.257.21:07:13.98#ibcon#wrote, iclass 12, count 2 2006.257.21:07:13.98#ibcon#about to read 3, iclass 12, count 2 2006.257.21:07:14.01#ibcon#read 3, iclass 12, count 2 2006.257.21:07:14.01#ibcon#about to read 4, iclass 12, count 2 2006.257.21:07:14.01#ibcon#read 4, iclass 12, count 2 2006.257.21:07:14.01#ibcon#about to read 5, iclass 12, count 2 2006.257.21:07:14.01#ibcon#read 5, iclass 12, count 2 2006.257.21:07:14.01#ibcon#about to read 6, iclass 12, count 2 2006.257.21:07:14.01#ibcon#read 6, iclass 12, count 2 2006.257.21:07:14.01#ibcon#end of sib2, iclass 12, count 2 2006.257.21:07:14.01#ibcon#*after write, iclass 12, count 2 2006.257.21:07:14.01#ibcon#*before return 0, iclass 12, count 2 2006.257.21:07:14.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:14.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:14.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.21:07:14.01#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:14.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:14.04#abcon#<5=/14 1.1 2.7 17.74 941015.3\r\n> 2006.257.21:07:14.06#abcon#{5=INTERFACE CLEAR} 2006.257.21:07:14.12#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:07:14.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:14.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:14.13#ibcon#enter wrdev, iclass 12, count 0 2006.257.21:07:14.13#ibcon#first serial, iclass 12, count 0 2006.257.21:07:14.13#ibcon#enter sib2, iclass 12, count 0 2006.257.21:07:14.13#ibcon#flushed, iclass 12, count 0 2006.257.21:07:14.13#ibcon#about to write, iclass 12, count 0 2006.257.21:07:14.13#ibcon#wrote, iclass 12, count 0 2006.257.21:07:14.13#ibcon#about to read 3, iclass 12, count 0 2006.257.21:07:14.15#ibcon#read 3, iclass 12, count 0 2006.257.21:07:14.15#ibcon#about to read 4, iclass 12, count 0 2006.257.21:07:14.15#ibcon#read 4, iclass 12, count 0 2006.257.21:07:14.15#ibcon#about to read 5, iclass 12, count 0 2006.257.21:07:14.15#ibcon#read 5, iclass 12, count 0 2006.257.21:07:14.15#ibcon#about to read 6, iclass 12, count 0 2006.257.21:07:14.15#ibcon#read 6, iclass 12, count 0 2006.257.21:07:14.15#ibcon#end of sib2, iclass 12, count 0 2006.257.21:07:14.15#ibcon#*mode == 0, iclass 12, count 0 2006.257.21:07:14.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.21:07:14.15#ibcon#[25=USB\r\n] 2006.257.21:07:14.15#ibcon#*before write, iclass 12, count 0 2006.257.21:07:14.15#ibcon#enter sib2, iclass 12, count 0 2006.257.21:07:14.15#ibcon#flushed, iclass 12, count 0 2006.257.21:07:14.15#ibcon#about to write, iclass 12, count 0 2006.257.21:07:14.15#ibcon#wrote, iclass 12, count 0 2006.257.21:07:14.15#ibcon#about to read 3, iclass 12, count 0 2006.257.21:07:14.18#ibcon#read 3, iclass 12, count 0 2006.257.21:07:14.18#ibcon#about to read 4, iclass 12, count 0 2006.257.21:07:14.18#ibcon#read 4, iclass 12, count 0 2006.257.21:07:14.18#ibcon#about to read 5, iclass 12, count 0 2006.257.21:07:14.18#ibcon#read 5, iclass 12, count 0 2006.257.21:07:14.18#ibcon#about to read 6, iclass 12, count 0 2006.257.21:07:14.18#ibcon#read 6, iclass 12, count 0 2006.257.21:07:14.18#ibcon#end of sib2, iclass 12, count 0 2006.257.21:07:14.18#ibcon#*after write, iclass 12, count 0 2006.257.21:07:14.18#ibcon#*before return 0, iclass 12, count 0 2006.257.21:07:14.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:14.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:14.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.21:07:14.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.21:07:14.18$vck44/valo=6,814.99 2006.257.21:07:14.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.21:07:14.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.21:07:14.18#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:14.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:14.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:14.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:14.18#ibcon#enter wrdev, iclass 18, count 0 2006.257.21:07:14.18#ibcon#first serial, iclass 18, count 0 2006.257.21:07:14.18#ibcon#enter sib2, iclass 18, count 0 2006.257.21:07:14.18#ibcon#flushed, iclass 18, count 0 2006.257.21:07:14.18#ibcon#about to write, iclass 18, count 0 2006.257.21:07:14.18#ibcon#wrote, iclass 18, count 0 2006.257.21:07:14.18#ibcon#about to read 3, iclass 18, count 0 2006.257.21:07:14.20#ibcon#read 3, iclass 18, count 0 2006.257.21:07:14.20#ibcon#about to read 4, iclass 18, count 0 2006.257.21:07:14.20#ibcon#read 4, iclass 18, count 0 2006.257.21:07:14.20#ibcon#about to read 5, iclass 18, count 0 2006.257.21:07:14.20#ibcon#read 5, iclass 18, count 0 2006.257.21:07:14.20#ibcon#about to read 6, iclass 18, count 0 2006.257.21:07:14.20#ibcon#read 6, iclass 18, count 0 2006.257.21:07:14.20#ibcon#end of sib2, iclass 18, count 0 2006.257.21:07:14.20#ibcon#*mode == 0, iclass 18, count 0 2006.257.21:07:14.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.21:07:14.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.21:07:14.20#ibcon#*before write, iclass 18, count 0 2006.257.21:07:14.20#ibcon#enter sib2, iclass 18, count 0 2006.257.21:07:14.20#ibcon#flushed, iclass 18, count 0 2006.257.21:07:14.20#ibcon#about to write, iclass 18, count 0 2006.257.21:07:14.20#ibcon#wrote, iclass 18, count 0 2006.257.21:07:14.20#ibcon#about to read 3, iclass 18, count 0 2006.257.21:07:14.24#ibcon#read 3, iclass 18, count 0 2006.257.21:07:14.24#ibcon#about to read 4, iclass 18, count 0 2006.257.21:07:14.24#ibcon#read 4, iclass 18, count 0 2006.257.21:07:14.24#ibcon#about to read 5, iclass 18, count 0 2006.257.21:07:14.24#ibcon#read 5, iclass 18, count 0 2006.257.21:07:14.24#ibcon#about to read 6, iclass 18, count 0 2006.257.21:07:14.24#ibcon#read 6, iclass 18, count 0 2006.257.21:07:14.24#ibcon#end of sib2, iclass 18, count 0 2006.257.21:07:14.24#ibcon#*after write, iclass 18, count 0 2006.257.21:07:14.24#ibcon#*before return 0, iclass 18, count 0 2006.257.21:07:14.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:14.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:14.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.21:07:14.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.21:07:14.24$vck44/va=6,4 2006.257.21:07:14.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.21:07:14.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.21:07:14.24#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:14.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:14.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:14.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:14.30#ibcon#enter wrdev, iclass 20, count 2 2006.257.21:07:14.30#ibcon#first serial, iclass 20, count 2 2006.257.21:07:14.30#ibcon#enter sib2, iclass 20, count 2 2006.257.21:07:14.30#ibcon#flushed, iclass 20, count 2 2006.257.21:07:14.30#ibcon#about to write, iclass 20, count 2 2006.257.21:07:14.30#ibcon#wrote, iclass 20, count 2 2006.257.21:07:14.30#ibcon#about to read 3, iclass 20, count 2 2006.257.21:07:14.32#ibcon#read 3, iclass 20, count 2 2006.257.21:07:14.32#ibcon#about to read 4, iclass 20, count 2 2006.257.21:07:14.32#ibcon#read 4, iclass 20, count 2 2006.257.21:07:14.32#ibcon#about to read 5, iclass 20, count 2 2006.257.21:07:14.32#ibcon#read 5, iclass 20, count 2 2006.257.21:07:14.32#ibcon#about to read 6, iclass 20, count 2 2006.257.21:07:14.32#ibcon#read 6, iclass 20, count 2 2006.257.21:07:14.32#ibcon#end of sib2, iclass 20, count 2 2006.257.21:07:14.32#ibcon#*mode == 0, iclass 20, count 2 2006.257.21:07:14.32#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.21:07:14.32#ibcon#[25=AT06-04\r\n] 2006.257.21:07:14.32#ibcon#*before write, iclass 20, count 2 2006.257.21:07:14.32#ibcon#enter sib2, iclass 20, count 2 2006.257.21:07:14.32#ibcon#flushed, iclass 20, count 2 2006.257.21:07:14.32#ibcon#about to write, iclass 20, count 2 2006.257.21:07:14.32#ibcon#wrote, iclass 20, count 2 2006.257.21:07:14.32#ibcon#about to read 3, iclass 20, count 2 2006.257.21:07:14.35#ibcon#read 3, iclass 20, count 2 2006.257.21:07:14.35#ibcon#about to read 4, iclass 20, count 2 2006.257.21:07:14.35#ibcon#read 4, iclass 20, count 2 2006.257.21:07:14.35#ibcon#about to read 5, iclass 20, count 2 2006.257.21:07:14.35#ibcon#read 5, iclass 20, count 2 2006.257.21:07:14.35#ibcon#about to read 6, iclass 20, count 2 2006.257.21:07:14.35#ibcon#read 6, iclass 20, count 2 2006.257.21:07:14.35#ibcon#end of sib2, iclass 20, count 2 2006.257.21:07:14.35#ibcon#*after write, iclass 20, count 2 2006.257.21:07:14.35#ibcon#*before return 0, iclass 20, count 2 2006.257.21:07:14.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:14.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:14.35#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.21:07:14.35#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:14.35#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:14.47#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:14.47#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:14.47#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:07:14.47#ibcon#first serial, iclass 20, count 0 2006.257.21:07:14.47#ibcon#enter sib2, iclass 20, count 0 2006.257.21:07:14.47#ibcon#flushed, iclass 20, count 0 2006.257.21:07:14.47#ibcon#about to write, iclass 20, count 0 2006.257.21:07:14.47#ibcon#wrote, iclass 20, count 0 2006.257.21:07:14.47#ibcon#about to read 3, iclass 20, count 0 2006.257.21:07:14.49#ibcon#read 3, iclass 20, count 0 2006.257.21:07:14.49#ibcon#about to read 4, iclass 20, count 0 2006.257.21:07:14.49#ibcon#read 4, iclass 20, count 0 2006.257.21:07:14.49#ibcon#about to read 5, iclass 20, count 0 2006.257.21:07:14.49#ibcon#read 5, iclass 20, count 0 2006.257.21:07:14.49#ibcon#about to read 6, iclass 20, count 0 2006.257.21:07:14.49#ibcon#read 6, iclass 20, count 0 2006.257.21:07:14.49#ibcon#end of sib2, iclass 20, count 0 2006.257.21:07:14.49#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:07:14.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:07:14.49#ibcon#[25=USB\r\n] 2006.257.21:07:14.49#ibcon#*before write, iclass 20, count 0 2006.257.21:07:14.49#ibcon#enter sib2, iclass 20, count 0 2006.257.21:07:14.49#ibcon#flushed, iclass 20, count 0 2006.257.21:07:14.49#ibcon#about to write, iclass 20, count 0 2006.257.21:07:14.49#ibcon#wrote, iclass 20, count 0 2006.257.21:07:14.49#ibcon#about to read 3, iclass 20, count 0 2006.257.21:07:14.52#ibcon#read 3, iclass 20, count 0 2006.257.21:07:14.52#ibcon#about to read 4, iclass 20, count 0 2006.257.21:07:14.52#ibcon#read 4, iclass 20, count 0 2006.257.21:07:14.52#ibcon#about to read 5, iclass 20, count 0 2006.257.21:07:14.52#ibcon#read 5, iclass 20, count 0 2006.257.21:07:14.52#ibcon#about to read 6, iclass 20, count 0 2006.257.21:07:14.52#ibcon#read 6, iclass 20, count 0 2006.257.21:07:14.52#ibcon#end of sib2, iclass 20, count 0 2006.257.21:07:14.52#ibcon#*after write, iclass 20, count 0 2006.257.21:07:14.52#ibcon#*before return 0, iclass 20, count 0 2006.257.21:07:14.52#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:14.52#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:14.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:07:14.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:07:14.52$vck44/valo=7,864.99 2006.257.21:07:14.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.21:07:14.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.21:07:14.52#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:14.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:14.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:14.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:14.52#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:07:14.52#ibcon#first serial, iclass 22, count 0 2006.257.21:07:14.52#ibcon#enter sib2, iclass 22, count 0 2006.257.21:07:14.52#ibcon#flushed, iclass 22, count 0 2006.257.21:07:14.52#ibcon#about to write, iclass 22, count 0 2006.257.21:07:14.52#ibcon#wrote, iclass 22, count 0 2006.257.21:07:14.52#ibcon#about to read 3, iclass 22, count 0 2006.257.21:07:14.54#ibcon#read 3, iclass 22, count 0 2006.257.21:07:14.54#ibcon#about to read 4, iclass 22, count 0 2006.257.21:07:14.54#ibcon#read 4, iclass 22, count 0 2006.257.21:07:14.54#ibcon#about to read 5, iclass 22, count 0 2006.257.21:07:14.54#ibcon#read 5, iclass 22, count 0 2006.257.21:07:14.54#ibcon#about to read 6, iclass 22, count 0 2006.257.21:07:14.54#ibcon#read 6, iclass 22, count 0 2006.257.21:07:14.54#ibcon#end of sib2, iclass 22, count 0 2006.257.21:07:14.54#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:07:14.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:07:14.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.21:07:14.54#ibcon#*before write, iclass 22, count 0 2006.257.21:07:14.54#ibcon#enter sib2, iclass 22, count 0 2006.257.21:07:14.54#ibcon#flushed, iclass 22, count 0 2006.257.21:07:14.54#ibcon#about to write, iclass 22, count 0 2006.257.21:07:14.54#ibcon#wrote, iclass 22, count 0 2006.257.21:07:14.54#ibcon#about to read 3, iclass 22, count 0 2006.257.21:07:14.58#ibcon#read 3, iclass 22, count 0 2006.257.21:07:14.58#ibcon#about to read 4, iclass 22, count 0 2006.257.21:07:14.58#ibcon#read 4, iclass 22, count 0 2006.257.21:07:14.58#ibcon#about to read 5, iclass 22, count 0 2006.257.21:07:14.58#ibcon#read 5, iclass 22, count 0 2006.257.21:07:14.58#ibcon#about to read 6, iclass 22, count 0 2006.257.21:07:14.58#ibcon#read 6, iclass 22, count 0 2006.257.21:07:14.58#ibcon#end of sib2, iclass 22, count 0 2006.257.21:07:14.58#ibcon#*after write, iclass 22, count 0 2006.257.21:07:14.58#ibcon#*before return 0, iclass 22, count 0 2006.257.21:07:14.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:14.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:14.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:07:14.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:07:14.58$vck44/va=7,4 2006.257.21:07:14.58#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.21:07:14.58#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.21:07:14.58#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:14.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:14.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:14.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:14.64#ibcon#enter wrdev, iclass 24, count 2 2006.257.21:07:14.64#ibcon#first serial, iclass 24, count 2 2006.257.21:07:14.64#ibcon#enter sib2, iclass 24, count 2 2006.257.21:07:14.64#ibcon#flushed, iclass 24, count 2 2006.257.21:07:14.64#ibcon#about to write, iclass 24, count 2 2006.257.21:07:14.64#ibcon#wrote, iclass 24, count 2 2006.257.21:07:14.64#ibcon#about to read 3, iclass 24, count 2 2006.257.21:07:14.66#ibcon#read 3, iclass 24, count 2 2006.257.21:07:14.66#ibcon#about to read 4, iclass 24, count 2 2006.257.21:07:14.66#ibcon#read 4, iclass 24, count 2 2006.257.21:07:14.66#ibcon#about to read 5, iclass 24, count 2 2006.257.21:07:14.66#ibcon#read 5, iclass 24, count 2 2006.257.21:07:14.66#ibcon#about to read 6, iclass 24, count 2 2006.257.21:07:14.66#ibcon#read 6, iclass 24, count 2 2006.257.21:07:14.66#ibcon#end of sib2, iclass 24, count 2 2006.257.21:07:14.66#ibcon#*mode == 0, iclass 24, count 2 2006.257.21:07:14.66#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.21:07:14.66#ibcon#[25=AT07-04\r\n] 2006.257.21:07:14.66#ibcon#*before write, iclass 24, count 2 2006.257.21:07:14.66#ibcon#enter sib2, iclass 24, count 2 2006.257.21:07:14.66#ibcon#flushed, iclass 24, count 2 2006.257.21:07:14.66#ibcon#about to write, iclass 24, count 2 2006.257.21:07:14.66#ibcon#wrote, iclass 24, count 2 2006.257.21:07:14.66#ibcon#about to read 3, iclass 24, count 2 2006.257.21:07:14.69#ibcon#read 3, iclass 24, count 2 2006.257.21:07:14.69#ibcon#about to read 4, iclass 24, count 2 2006.257.21:07:14.69#ibcon#read 4, iclass 24, count 2 2006.257.21:07:14.69#ibcon#about to read 5, iclass 24, count 2 2006.257.21:07:14.69#ibcon#read 5, iclass 24, count 2 2006.257.21:07:14.69#ibcon#about to read 6, iclass 24, count 2 2006.257.21:07:14.69#ibcon#read 6, iclass 24, count 2 2006.257.21:07:14.69#ibcon#end of sib2, iclass 24, count 2 2006.257.21:07:14.69#ibcon#*after write, iclass 24, count 2 2006.257.21:07:14.69#ibcon#*before return 0, iclass 24, count 2 2006.257.21:07:14.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:14.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:14.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.21:07:14.69#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:14.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:14.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:14.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:14.81#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:07:14.81#ibcon#first serial, iclass 24, count 0 2006.257.21:07:14.81#ibcon#enter sib2, iclass 24, count 0 2006.257.21:07:14.81#ibcon#flushed, iclass 24, count 0 2006.257.21:07:14.81#ibcon#about to write, iclass 24, count 0 2006.257.21:07:14.81#ibcon#wrote, iclass 24, count 0 2006.257.21:07:14.81#ibcon#about to read 3, iclass 24, count 0 2006.257.21:07:14.83#ibcon#read 3, iclass 24, count 0 2006.257.21:07:14.83#ibcon#about to read 4, iclass 24, count 0 2006.257.21:07:14.83#ibcon#read 4, iclass 24, count 0 2006.257.21:07:14.83#ibcon#about to read 5, iclass 24, count 0 2006.257.21:07:14.83#ibcon#read 5, iclass 24, count 0 2006.257.21:07:14.83#ibcon#about to read 6, iclass 24, count 0 2006.257.21:07:14.83#ibcon#read 6, iclass 24, count 0 2006.257.21:07:14.83#ibcon#end of sib2, iclass 24, count 0 2006.257.21:07:14.83#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:07:14.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:07:14.83#ibcon#[25=USB\r\n] 2006.257.21:07:14.83#ibcon#*before write, iclass 24, count 0 2006.257.21:07:14.83#ibcon#enter sib2, iclass 24, count 0 2006.257.21:07:14.83#ibcon#flushed, iclass 24, count 0 2006.257.21:07:14.83#ibcon#about to write, iclass 24, count 0 2006.257.21:07:14.83#ibcon#wrote, iclass 24, count 0 2006.257.21:07:14.83#ibcon#about to read 3, iclass 24, count 0 2006.257.21:07:14.86#ibcon#read 3, iclass 24, count 0 2006.257.21:07:14.86#ibcon#about to read 4, iclass 24, count 0 2006.257.21:07:14.86#ibcon#read 4, iclass 24, count 0 2006.257.21:07:14.86#ibcon#about to read 5, iclass 24, count 0 2006.257.21:07:14.86#ibcon#read 5, iclass 24, count 0 2006.257.21:07:14.86#ibcon#about to read 6, iclass 24, count 0 2006.257.21:07:14.86#ibcon#read 6, iclass 24, count 0 2006.257.21:07:14.86#ibcon#end of sib2, iclass 24, count 0 2006.257.21:07:14.86#ibcon#*after write, iclass 24, count 0 2006.257.21:07:14.86#ibcon#*before return 0, iclass 24, count 0 2006.257.21:07:14.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:14.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:14.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:07:14.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:07:14.86$vck44/valo=8,884.99 2006.257.21:07:14.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.21:07:14.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.21:07:14.86#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:14.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:14.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:14.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:14.86#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:07:14.86#ibcon#first serial, iclass 26, count 0 2006.257.21:07:14.86#ibcon#enter sib2, iclass 26, count 0 2006.257.21:07:14.86#ibcon#flushed, iclass 26, count 0 2006.257.21:07:14.86#ibcon#about to write, iclass 26, count 0 2006.257.21:07:14.86#ibcon#wrote, iclass 26, count 0 2006.257.21:07:14.86#ibcon#about to read 3, iclass 26, count 0 2006.257.21:07:14.88#ibcon#read 3, iclass 26, count 0 2006.257.21:07:14.88#ibcon#about to read 4, iclass 26, count 0 2006.257.21:07:14.88#ibcon#read 4, iclass 26, count 0 2006.257.21:07:14.88#ibcon#about to read 5, iclass 26, count 0 2006.257.21:07:14.88#ibcon#read 5, iclass 26, count 0 2006.257.21:07:14.88#ibcon#about to read 6, iclass 26, count 0 2006.257.21:07:14.88#ibcon#read 6, iclass 26, count 0 2006.257.21:07:14.88#ibcon#end of sib2, iclass 26, count 0 2006.257.21:07:14.88#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:07:14.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:07:14.88#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.21:07:14.88#ibcon#*before write, iclass 26, count 0 2006.257.21:07:14.88#ibcon#enter sib2, iclass 26, count 0 2006.257.21:07:14.88#ibcon#flushed, iclass 26, count 0 2006.257.21:07:14.88#ibcon#about to write, iclass 26, count 0 2006.257.21:07:14.88#ibcon#wrote, iclass 26, count 0 2006.257.21:07:14.88#ibcon#about to read 3, iclass 26, count 0 2006.257.21:07:14.92#ibcon#read 3, iclass 26, count 0 2006.257.21:07:14.92#ibcon#about to read 4, iclass 26, count 0 2006.257.21:07:14.92#ibcon#read 4, iclass 26, count 0 2006.257.21:07:14.92#ibcon#about to read 5, iclass 26, count 0 2006.257.21:07:14.92#ibcon#read 5, iclass 26, count 0 2006.257.21:07:14.92#ibcon#about to read 6, iclass 26, count 0 2006.257.21:07:14.92#ibcon#read 6, iclass 26, count 0 2006.257.21:07:14.92#ibcon#end of sib2, iclass 26, count 0 2006.257.21:07:14.92#ibcon#*after write, iclass 26, count 0 2006.257.21:07:14.92#ibcon#*before return 0, iclass 26, count 0 2006.257.21:07:14.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:14.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:14.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:07:14.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:07:14.92$vck44/va=8,4 2006.257.21:07:14.92#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.21:07:14.92#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.21:07:14.92#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:14.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:07:14.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:07:14.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:07:14.98#ibcon#enter wrdev, iclass 28, count 2 2006.257.21:07:14.98#ibcon#first serial, iclass 28, count 2 2006.257.21:07:14.98#ibcon#enter sib2, iclass 28, count 2 2006.257.21:07:14.98#ibcon#flushed, iclass 28, count 2 2006.257.21:07:14.98#ibcon#about to write, iclass 28, count 2 2006.257.21:07:14.98#ibcon#wrote, iclass 28, count 2 2006.257.21:07:14.98#ibcon#about to read 3, iclass 28, count 2 2006.257.21:07:15.00#ibcon#read 3, iclass 28, count 2 2006.257.21:07:15.00#ibcon#about to read 4, iclass 28, count 2 2006.257.21:07:15.00#ibcon#read 4, iclass 28, count 2 2006.257.21:07:15.00#ibcon#about to read 5, iclass 28, count 2 2006.257.21:07:15.00#ibcon#read 5, iclass 28, count 2 2006.257.21:07:15.00#ibcon#about to read 6, iclass 28, count 2 2006.257.21:07:15.00#ibcon#read 6, iclass 28, count 2 2006.257.21:07:15.00#ibcon#end of sib2, iclass 28, count 2 2006.257.21:07:15.00#ibcon#*mode == 0, iclass 28, count 2 2006.257.21:07:15.00#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.21:07:15.00#ibcon#[25=AT08-04\r\n] 2006.257.21:07:15.00#ibcon#*before write, iclass 28, count 2 2006.257.21:07:15.00#ibcon#enter sib2, iclass 28, count 2 2006.257.21:07:15.00#ibcon#flushed, iclass 28, count 2 2006.257.21:07:15.00#ibcon#about to write, iclass 28, count 2 2006.257.21:07:15.00#ibcon#wrote, iclass 28, count 2 2006.257.21:07:15.00#ibcon#about to read 3, iclass 28, count 2 2006.257.21:07:15.03#ibcon#read 3, iclass 28, count 2 2006.257.21:07:15.03#ibcon#about to read 4, iclass 28, count 2 2006.257.21:07:15.03#ibcon#read 4, iclass 28, count 2 2006.257.21:07:15.03#ibcon#about to read 5, iclass 28, count 2 2006.257.21:07:15.03#ibcon#read 5, iclass 28, count 2 2006.257.21:07:15.03#ibcon#about to read 6, iclass 28, count 2 2006.257.21:07:15.03#ibcon#read 6, iclass 28, count 2 2006.257.21:07:15.03#ibcon#end of sib2, iclass 28, count 2 2006.257.21:07:15.03#ibcon#*after write, iclass 28, count 2 2006.257.21:07:15.03#ibcon#*before return 0, iclass 28, count 2 2006.257.21:07:15.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:07:15.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:07:15.03#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.21:07:15.03#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:15.03#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:07:15.15#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:07:15.15#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:07:15.15#ibcon#enter wrdev, iclass 28, count 0 2006.257.21:07:15.15#ibcon#first serial, iclass 28, count 0 2006.257.21:07:15.15#ibcon#enter sib2, iclass 28, count 0 2006.257.21:07:15.15#ibcon#flushed, iclass 28, count 0 2006.257.21:07:15.15#ibcon#about to write, iclass 28, count 0 2006.257.21:07:15.15#ibcon#wrote, iclass 28, count 0 2006.257.21:07:15.15#ibcon#about to read 3, iclass 28, count 0 2006.257.21:07:15.17#ibcon#read 3, iclass 28, count 0 2006.257.21:07:15.17#ibcon#about to read 4, iclass 28, count 0 2006.257.21:07:15.17#ibcon#read 4, iclass 28, count 0 2006.257.21:07:15.17#ibcon#about to read 5, iclass 28, count 0 2006.257.21:07:15.17#ibcon#read 5, iclass 28, count 0 2006.257.21:07:15.17#ibcon#about to read 6, iclass 28, count 0 2006.257.21:07:15.17#ibcon#read 6, iclass 28, count 0 2006.257.21:07:15.17#ibcon#end of sib2, iclass 28, count 0 2006.257.21:07:15.17#ibcon#*mode == 0, iclass 28, count 0 2006.257.21:07:15.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.21:07:15.17#ibcon#[25=USB\r\n] 2006.257.21:07:15.17#ibcon#*before write, iclass 28, count 0 2006.257.21:07:15.17#ibcon#enter sib2, iclass 28, count 0 2006.257.21:07:15.17#ibcon#flushed, iclass 28, count 0 2006.257.21:07:15.17#ibcon#about to write, iclass 28, count 0 2006.257.21:07:15.17#ibcon#wrote, iclass 28, count 0 2006.257.21:07:15.17#ibcon#about to read 3, iclass 28, count 0 2006.257.21:07:15.20#ibcon#read 3, iclass 28, count 0 2006.257.21:07:15.20#ibcon#about to read 4, iclass 28, count 0 2006.257.21:07:15.20#ibcon#read 4, iclass 28, count 0 2006.257.21:07:15.20#ibcon#about to read 5, iclass 28, count 0 2006.257.21:07:15.20#ibcon#read 5, iclass 28, count 0 2006.257.21:07:15.20#ibcon#about to read 6, iclass 28, count 0 2006.257.21:07:15.20#ibcon#read 6, iclass 28, count 0 2006.257.21:07:15.20#ibcon#end of sib2, iclass 28, count 0 2006.257.21:07:15.20#ibcon#*after write, iclass 28, count 0 2006.257.21:07:15.20#ibcon#*before return 0, iclass 28, count 0 2006.257.21:07:15.20#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:07:15.20#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:07:15.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.21:07:15.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.21:07:15.20$vck44/vblo=1,629.99 2006.257.21:07:15.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.21:07:15.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.21:07:15.20#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:15.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:15.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:15.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:15.20#ibcon#enter wrdev, iclass 30, count 0 2006.257.21:07:15.20#ibcon#first serial, iclass 30, count 0 2006.257.21:07:15.20#ibcon#enter sib2, iclass 30, count 0 2006.257.21:07:15.20#ibcon#flushed, iclass 30, count 0 2006.257.21:07:15.20#ibcon#about to write, iclass 30, count 0 2006.257.21:07:15.20#ibcon#wrote, iclass 30, count 0 2006.257.21:07:15.20#ibcon#about to read 3, iclass 30, count 0 2006.257.21:07:15.22#ibcon#read 3, iclass 30, count 0 2006.257.21:07:15.22#ibcon#about to read 4, iclass 30, count 0 2006.257.21:07:15.22#ibcon#read 4, iclass 30, count 0 2006.257.21:07:15.22#ibcon#about to read 5, iclass 30, count 0 2006.257.21:07:15.22#ibcon#read 5, iclass 30, count 0 2006.257.21:07:15.22#ibcon#about to read 6, iclass 30, count 0 2006.257.21:07:15.22#ibcon#read 6, iclass 30, count 0 2006.257.21:07:15.22#ibcon#end of sib2, iclass 30, count 0 2006.257.21:07:15.22#ibcon#*mode == 0, iclass 30, count 0 2006.257.21:07:15.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.21:07:15.22#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.21:07:15.22#ibcon#*before write, iclass 30, count 0 2006.257.21:07:15.22#ibcon#enter sib2, iclass 30, count 0 2006.257.21:07:15.22#ibcon#flushed, iclass 30, count 0 2006.257.21:07:15.22#ibcon#about to write, iclass 30, count 0 2006.257.21:07:15.22#ibcon#wrote, iclass 30, count 0 2006.257.21:07:15.22#ibcon#about to read 3, iclass 30, count 0 2006.257.21:07:15.26#ibcon#read 3, iclass 30, count 0 2006.257.21:07:15.26#ibcon#about to read 4, iclass 30, count 0 2006.257.21:07:15.26#ibcon#read 4, iclass 30, count 0 2006.257.21:07:15.26#ibcon#about to read 5, iclass 30, count 0 2006.257.21:07:15.26#ibcon#read 5, iclass 30, count 0 2006.257.21:07:15.26#ibcon#about to read 6, iclass 30, count 0 2006.257.21:07:15.26#ibcon#read 6, iclass 30, count 0 2006.257.21:07:15.26#ibcon#end of sib2, iclass 30, count 0 2006.257.21:07:15.26#ibcon#*after write, iclass 30, count 0 2006.257.21:07:15.26#ibcon#*before return 0, iclass 30, count 0 2006.257.21:07:15.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:15.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:07:15.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.21:07:15.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.21:07:15.26$vck44/vb=1,4 2006.257.21:07:15.26#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.21:07:15.26#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.21:07:15.26#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:15.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:15.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:15.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:15.26#ibcon#enter wrdev, iclass 32, count 2 2006.257.21:07:15.26#ibcon#first serial, iclass 32, count 2 2006.257.21:07:15.26#ibcon#enter sib2, iclass 32, count 2 2006.257.21:07:15.26#ibcon#flushed, iclass 32, count 2 2006.257.21:07:15.26#ibcon#about to write, iclass 32, count 2 2006.257.21:07:15.26#ibcon#wrote, iclass 32, count 2 2006.257.21:07:15.26#ibcon#about to read 3, iclass 32, count 2 2006.257.21:07:15.28#ibcon#read 3, iclass 32, count 2 2006.257.21:07:15.28#ibcon#about to read 4, iclass 32, count 2 2006.257.21:07:15.28#ibcon#read 4, iclass 32, count 2 2006.257.21:07:15.28#ibcon#about to read 5, iclass 32, count 2 2006.257.21:07:15.28#ibcon#read 5, iclass 32, count 2 2006.257.21:07:15.28#ibcon#about to read 6, iclass 32, count 2 2006.257.21:07:15.28#ibcon#read 6, iclass 32, count 2 2006.257.21:07:15.28#ibcon#end of sib2, iclass 32, count 2 2006.257.21:07:15.28#ibcon#*mode == 0, iclass 32, count 2 2006.257.21:07:15.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.21:07:15.28#ibcon#[27=AT01-04\r\n] 2006.257.21:07:15.28#ibcon#*before write, iclass 32, count 2 2006.257.21:07:15.28#ibcon#enter sib2, iclass 32, count 2 2006.257.21:07:15.28#ibcon#flushed, iclass 32, count 2 2006.257.21:07:15.28#ibcon#about to write, iclass 32, count 2 2006.257.21:07:15.28#ibcon#wrote, iclass 32, count 2 2006.257.21:07:15.28#ibcon#about to read 3, iclass 32, count 2 2006.257.21:07:15.31#ibcon#read 3, iclass 32, count 2 2006.257.21:07:15.31#ibcon#about to read 4, iclass 32, count 2 2006.257.21:07:15.31#ibcon#read 4, iclass 32, count 2 2006.257.21:07:15.31#ibcon#about to read 5, iclass 32, count 2 2006.257.21:07:15.31#ibcon#read 5, iclass 32, count 2 2006.257.21:07:15.31#ibcon#about to read 6, iclass 32, count 2 2006.257.21:07:15.31#ibcon#read 6, iclass 32, count 2 2006.257.21:07:15.31#ibcon#end of sib2, iclass 32, count 2 2006.257.21:07:15.31#ibcon#*after write, iclass 32, count 2 2006.257.21:07:15.31#ibcon#*before return 0, iclass 32, count 2 2006.257.21:07:15.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:15.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:07:15.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.21:07:15.31#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:15.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:15.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:15.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:15.43#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:07:15.43#ibcon#first serial, iclass 32, count 0 2006.257.21:07:15.43#ibcon#enter sib2, iclass 32, count 0 2006.257.21:07:15.43#ibcon#flushed, iclass 32, count 0 2006.257.21:07:15.43#ibcon#about to write, iclass 32, count 0 2006.257.21:07:15.43#ibcon#wrote, iclass 32, count 0 2006.257.21:07:15.43#ibcon#about to read 3, iclass 32, count 0 2006.257.21:07:15.45#ibcon#read 3, iclass 32, count 0 2006.257.21:07:15.45#ibcon#about to read 4, iclass 32, count 0 2006.257.21:07:15.45#ibcon#read 4, iclass 32, count 0 2006.257.21:07:15.45#ibcon#about to read 5, iclass 32, count 0 2006.257.21:07:15.45#ibcon#read 5, iclass 32, count 0 2006.257.21:07:15.45#ibcon#about to read 6, iclass 32, count 0 2006.257.21:07:15.45#ibcon#read 6, iclass 32, count 0 2006.257.21:07:15.45#ibcon#end of sib2, iclass 32, count 0 2006.257.21:07:15.45#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:07:15.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:07:15.45#ibcon#[27=USB\r\n] 2006.257.21:07:15.45#ibcon#*before write, iclass 32, count 0 2006.257.21:07:15.45#ibcon#enter sib2, iclass 32, count 0 2006.257.21:07:15.45#ibcon#flushed, iclass 32, count 0 2006.257.21:07:15.45#ibcon#about to write, iclass 32, count 0 2006.257.21:07:15.45#ibcon#wrote, iclass 32, count 0 2006.257.21:07:15.45#ibcon#about to read 3, iclass 32, count 0 2006.257.21:07:15.48#ibcon#read 3, iclass 32, count 0 2006.257.21:07:15.48#ibcon#about to read 4, iclass 32, count 0 2006.257.21:07:15.48#ibcon#read 4, iclass 32, count 0 2006.257.21:07:15.48#ibcon#about to read 5, iclass 32, count 0 2006.257.21:07:15.48#ibcon#read 5, iclass 32, count 0 2006.257.21:07:15.48#ibcon#about to read 6, iclass 32, count 0 2006.257.21:07:15.48#ibcon#read 6, iclass 32, count 0 2006.257.21:07:15.48#ibcon#end of sib2, iclass 32, count 0 2006.257.21:07:15.48#ibcon#*after write, iclass 32, count 0 2006.257.21:07:15.48#ibcon#*before return 0, iclass 32, count 0 2006.257.21:07:15.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:15.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:07:15.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:07:15.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:07:15.48$vck44/vblo=2,634.99 2006.257.21:07:15.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.21:07:15.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.21:07:15.48#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:15.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:15.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:15.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:15.48#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:07:15.48#ibcon#first serial, iclass 34, count 0 2006.257.21:07:15.48#ibcon#enter sib2, iclass 34, count 0 2006.257.21:07:15.48#ibcon#flushed, iclass 34, count 0 2006.257.21:07:15.48#ibcon#about to write, iclass 34, count 0 2006.257.21:07:15.48#ibcon#wrote, iclass 34, count 0 2006.257.21:07:15.48#ibcon#about to read 3, iclass 34, count 0 2006.257.21:07:15.50#ibcon#read 3, iclass 34, count 0 2006.257.21:07:15.50#ibcon#about to read 4, iclass 34, count 0 2006.257.21:07:15.50#ibcon#read 4, iclass 34, count 0 2006.257.21:07:15.50#ibcon#about to read 5, iclass 34, count 0 2006.257.21:07:15.50#ibcon#read 5, iclass 34, count 0 2006.257.21:07:15.50#ibcon#about to read 6, iclass 34, count 0 2006.257.21:07:15.50#ibcon#read 6, iclass 34, count 0 2006.257.21:07:15.50#ibcon#end of sib2, iclass 34, count 0 2006.257.21:07:15.50#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:07:15.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:07:15.50#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.21:07:15.50#ibcon#*before write, iclass 34, count 0 2006.257.21:07:15.50#ibcon#enter sib2, iclass 34, count 0 2006.257.21:07:15.50#ibcon#flushed, iclass 34, count 0 2006.257.21:07:15.50#ibcon#about to write, iclass 34, count 0 2006.257.21:07:15.50#ibcon#wrote, iclass 34, count 0 2006.257.21:07:15.50#ibcon#about to read 3, iclass 34, count 0 2006.257.21:07:15.54#ibcon#read 3, iclass 34, count 0 2006.257.21:07:15.54#ibcon#about to read 4, iclass 34, count 0 2006.257.21:07:15.54#ibcon#read 4, iclass 34, count 0 2006.257.21:07:15.54#ibcon#about to read 5, iclass 34, count 0 2006.257.21:07:15.54#ibcon#read 5, iclass 34, count 0 2006.257.21:07:15.54#ibcon#about to read 6, iclass 34, count 0 2006.257.21:07:15.54#ibcon#read 6, iclass 34, count 0 2006.257.21:07:15.54#ibcon#end of sib2, iclass 34, count 0 2006.257.21:07:15.54#ibcon#*after write, iclass 34, count 0 2006.257.21:07:15.54#ibcon#*before return 0, iclass 34, count 0 2006.257.21:07:15.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:15.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:07:15.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:07:15.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:07:15.54$vck44/vb=2,5 2006.257.21:07:15.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.21:07:15.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.21:07:15.54#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:15.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:15.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:15.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:15.60#ibcon#enter wrdev, iclass 36, count 2 2006.257.21:07:15.60#ibcon#first serial, iclass 36, count 2 2006.257.21:07:15.60#ibcon#enter sib2, iclass 36, count 2 2006.257.21:07:15.60#ibcon#flushed, iclass 36, count 2 2006.257.21:07:15.60#ibcon#about to write, iclass 36, count 2 2006.257.21:07:15.60#ibcon#wrote, iclass 36, count 2 2006.257.21:07:15.60#ibcon#about to read 3, iclass 36, count 2 2006.257.21:07:15.62#ibcon#read 3, iclass 36, count 2 2006.257.21:07:15.62#ibcon#about to read 4, iclass 36, count 2 2006.257.21:07:15.62#ibcon#read 4, iclass 36, count 2 2006.257.21:07:15.62#ibcon#about to read 5, iclass 36, count 2 2006.257.21:07:15.62#ibcon#read 5, iclass 36, count 2 2006.257.21:07:15.62#ibcon#about to read 6, iclass 36, count 2 2006.257.21:07:15.62#ibcon#read 6, iclass 36, count 2 2006.257.21:07:15.62#ibcon#end of sib2, iclass 36, count 2 2006.257.21:07:15.62#ibcon#*mode == 0, iclass 36, count 2 2006.257.21:07:15.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.21:07:15.62#ibcon#[27=AT02-05\r\n] 2006.257.21:07:15.62#ibcon#*before write, iclass 36, count 2 2006.257.21:07:15.62#ibcon#enter sib2, iclass 36, count 2 2006.257.21:07:15.62#ibcon#flushed, iclass 36, count 2 2006.257.21:07:15.62#ibcon#about to write, iclass 36, count 2 2006.257.21:07:15.62#ibcon#wrote, iclass 36, count 2 2006.257.21:07:15.62#ibcon#about to read 3, iclass 36, count 2 2006.257.21:07:15.65#ibcon#read 3, iclass 36, count 2 2006.257.21:07:15.65#ibcon#about to read 4, iclass 36, count 2 2006.257.21:07:15.65#ibcon#read 4, iclass 36, count 2 2006.257.21:07:15.65#ibcon#about to read 5, iclass 36, count 2 2006.257.21:07:15.65#ibcon#read 5, iclass 36, count 2 2006.257.21:07:15.65#ibcon#about to read 6, iclass 36, count 2 2006.257.21:07:15.65#ibcon#read 6, iclass 36, count 2 2006.257.21:07:15.65#ibcon#end of sib2, iclass 36, count 2 2006.257.21:07:15.65#ibcon#*after write, iclass 36, count 2 2006.257.21:07:15.65#ibcon#*before return 0, iclass 36, count 2 2006.257.21:07:15.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:15.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:07:15.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.21:07:15.65#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:15.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:15.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:15.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:15.77#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:07:15.77#ibcon#first serial, iclass 36, count 0 2006.257.21:07:15.77#ibcon#enter sib2, iclass 36, count 0 2006.257.21:07:15.77#ibcon#flushed, iclass 36, count 0 2006.257.21:07:15.77#ibcon#about to write, iclass 36, count 0 2006.257.21:07:15.77#ibcon#wrote, iclass 36, count 0 2006.257.21:07:15.77#ibcon#about to read 3, iclass 36, count 0 2006.257.21:07:15.79#ibcon#read 3, iclass 36, count 0 2006.257.21:07:15.79#ibcon#about to read 4, iclass 36, count 0 2006.257.21:07:15.79#ibcon#read 4, iclass 36, count 0 2006.257.21:07:15.79#ibcon#about to read 5, iclass 36, count 0 2006.257.21:07:15.79#ibcon#read 5, iclass 36, count 0 2006.257.21:07:15.79#ibcon#about to read 6, iclass 36, count 0 2006.257.21:07:15.79#ibcon#read 6, iclass 36, count 0 2006.257.21:07:15.79#ibcon#end of sib2, iclass 36, count 0 2006.257.21:07:15.79#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:07:15.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:07:15.79#ibcon#[27=USB\r\n] 2006.257.21:07:15.79#ibcon#*before write, iclass 36, count 0 2006.257.21:07:15.79#ibcon#enter sib2, iclass 36, count 0 2006.257.21:07:15.79#ibcon#flushed, iclass 36, count 0 2006.257.21:07:15.79#ibcon#about to write, iclass 36, count 0 2006.257.21:07:15.79#ibcon#wrote, iclass 36, count 0 2006.257.21:07:15.79#ibcon#about to read 3, iclass 36, count 0 2006.257.21:07:15.82#ibcon#read 3, iclass 36, count 0 2006.257.21:07:15.82#ibcon#about to read 4, iclass 36, count 0 2006.257.21:07:15.82#ibcon#read 4, iclass 36, count 0 2006.257.21:07:15.82#ibcon#about to read 5, iclass 36, count 0 2006.257.21:07:15.82#ibcon#read 5, iclass 36, count 0 2006.257.21:07:15.82#ibcon#about to read 6, iclass 36, count 0 2006.257.21:07:15.82#ibcon#read 6, iclass 36, count 0 2006.257.21:07:15.82#ibcon#end of sib2, iclass 36, count 0 2006.257.21:07:15.82#ibcon#*after write, iclass 36, count 0 2006.257.21:07:15.82#ibcon#*before return 0, iclass 36, count 0 2006.257.21:07:15.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:15.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:07:15.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:07:15.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:07:15.82$vck44/vblo=3,649.99 2006.257.21:07:15.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.21:07:15.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.21:07:15.82#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:15.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:15.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:15.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:15.82#ibcon#enter wrdev, iclass 38, count 0 2006.257.21:07:15.82#ibcon#first serial, iclass 38, count 0 2006.257.21:07:15.82#ibcon#enter sib2, iclass 38, count 0 2006.257.21:07:15.82#ibcon#flushed, iclass 38, count 0 2006.257.21:07:15.82#ibcon#about to write, iclass 38, count 0 2006.257.21:07:15.82#ibcon#wrote, iclass 38, count 0 2006.257.21:07:15.82#ibcon#about to read 3, iclass 38, count 0 2006.257.21:07:15.84#ibcon#read 3, iclass 38, count 0 2006.257.21:07:15.84#ibcon#about to read 4, iclass 38, count 0 2006.257.21:07:15.84#ibcon#read 4, iclass 38, count 0 2006.257.21:07:15.84#ibcon#about to read 5, iclass 38, count 0 2006.257.21:07:15.84#ibcon#read 5, iclass 38, count 0 2006.257.21:07:15.84#ibcon#about to read 6, iclass 38, count 0 2006.257.21:07:15.84#ibcon#read 6, iclass 38, count 0 2006.257.21:07:15.84#ibcon#end of sib2, iclass 38, count 0 2006.257.21:07:15.84#ibcon#*mode == 0, iclass 38, count 0 2006.257.21:07:15.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.21:07:15.84#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.21:07:15.84#ibcon#*before write, iclass 38, count 0 2006.257.21:07:15.84#ibcon#enter sib2, iclass 38, count 0 2006.257.21:07:15.84#ibcon#flushed, iclass 38, count 0 2006.257.21:07:15.84#ibcon#about to write, iclass 38, count 0 2006.257.21:07:15.84#ibcon#wrote, iclass 38, count 0 2006.257.21:07:15.84#ibcon#about to read 3, iclass 38, count 0 2006.257.21:07:15.88#ibcon#read 3, iclass 38, count 0 2006.257.21:07:15.88#ibcon#about to read 4, iclass 38, count 0 2006.257.21:07:15.88#ibcon#read 4, iclass 38, count 0 2006.257.21:07:15.88#ibcon#about to read 5, iclass 38, count 0 2006.257.21:07:15.88#ibcon#read 5, iclass 38, count 0 2006.257.21:07:15.88#ibcon#about to read 6, iclass 38, count 0 2006.257.21:07:15.88#ibcon#read 6, iclass 38, count 0 2006.257.21:07:15.88#ibcon#end of sib2, iclass 38, count 0 2006.257.21:07:15.88#ibcon#*after write, iclass 38, count 0 2006.257.21:07:15.88#ibcon#*before return 0, iclass 38, count 0 2006.257.21:07:15.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:15.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:07:15.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.21:07:15.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.21:07:15.88$vck44/vb=3,4 2006.257.21:07:15.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.21:07:15.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.21:07:15.88#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:15.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:15.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:15.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:15.94#ibcon#enter wrdev, iclass 40, count 2 2006.257.21:07:15.94#ibcon#first serial, iclass 40, count 2 2006.257.21:07:15.94#ibcon#enter sib2, iclass 40, count 2 2006.257.21:07:15.94#ibcon#flushed, iclass 40, count 2 2006.257.21:07:15.94#ibcon#about to write, iclass 40, count 2 2006.257.21:07:15.94#ibcon#wrote, iclass 40, count 2 2006.257.21:07:15.94#ibcon#about to read 3, iclass 40, count 2 2006.257.21:07:15.96#ibcon#read 3, iclass 40, count 2 2006.257.21:07:15.96#ibcon#about to read 4, iclass 40, count 2 2006.257.21:07:15.96#ibcon#read 4, iclass 40, count 2 2006.257.21:07:15.96#ibcon#about to read 5, iclass 40, count 2 2006.257.21:07:15.96#ibcon#read 5, iclass 40, count 2 2006.257.21:07:15.96#ibcon#about to read 6, iclass 40, count 2 2006.257.21:07:15.96#ibcon#read 6, iclass 40, count 2 2006.257.21:07:15.96#ibcon#end of sib2, iclass 40, count 2 2006.257.21:07:15.96#ibcon#*mode == 0, iclass 40, count 2 2006.257.21:07:15.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.21:07:15.96#ibcon#[27=AT03-04\r\n] 2006.257.21:07:15.96#ibcon#*before write, iclass 40, count 2 2006.257.21:07:15.96#ibcon#enter sib2, iclass 40, count 2 2006.257.21:07:15.96#ibcon#flushed, iclass 40, count 2 2006.257.21:07:15.96#ibcon#about to write, iclass 40, count 2 2006.257.21:07:15.96#ibcon#wrote, iclass 40, count 2 2006.257.21:07:15.96#ibcon#about to read 3, iclass 40, count 2 2006.257.21:07:15.99#ibcon#read 3, iclass 40, count 2 2006.257.21:07:15.99#ibcon#about to read 4, iclass 40, count 2 2006.257.21:07:15.99#ibcon#read 4, iclass 40, count 2 2006.257.21:07:15.99#ibcon#about to read 5, iclass 40, count 2 2006.257.21:07:15.99#ibcon#read 5, iclass 40, count 2 2006.257.21:07:15.99#ibcon#about to read 6, iclass 40, count 2 2006.257.21:07:15.99#ibcon#read 6, iclass 40, count 2 2006.257.21:07:15.99#ibcon#end of sib2, iclass 40, count 2 2006.257.21:07:15.99#ibcon#*after write, iclass 40, count 2 2006.257.21:07:15.99#ibcon#*before return 0, iclass 40, count 2 2006.257.21:07:15.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:15.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:07:15.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.21:07:15.99#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:15.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:16.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:16.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:16.11#ibcon#enter wrdev, iclass 40, count 0 2006.257.21:07:16.11#ibcon#first serial, iclass 40, count 0 2006.257.21:07:16.11#ibcon#enter sib2, iclass 40, count 0 2006.257.21:07:16.11#ibcon#flushed, iclass 40, count 0 2006.257.21:07:16.11#ibcon#about to write, iclass 40, count 0 2006.257.21:07:16.11#ibcon#wrote, iclass 40, count 0 2006.257.21:07:16.11#ibcon#about to read 3, iclass 40, count 0 2006.257.21:07:16.13#ibcon#read 3, iclass 40, count 0 2006.257.21:07:16.13#ibcon#about to read 4, iclass 40, count 0 2006.257.21:07:16.13#ibcon#read 4, iclass 40, count 0 2006.257.21:07:16.13#ibcon#about to read 5, iclass 40, count 0 2006.257.21:07:16.13#ibcon#read 5, iclass 40, count 0 2006.257.21:07:16.13#ibcon#about to read 6, iclass 40, count 0 2006.257.21:07:16.13#ibcon#read 6, iclass 40, count 0 2006.257.21:07:16.13#ibcon#end of sib2, iclass 40, count 0 2006.257.21:07:16.13#ibcon#*mode == 0, iclass 40, count 0 2006.257.21:07:16.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.21:07:16.13#ibcon#[27=USB\r\n] 2006.257.21:07:16.13#ibcon#*before write, iclass 40, count 0 2006.257.21:07:16.13#ibcon#enter sib2, iclass 40, count 0 2006.257.21:07:16.13#ibcon#flushed, iclass 40, count 0 2006.257.21:07:16.13#ibcon#about to write, iclass 40, count 0 2006.257.21:07:16.13#ibcon#wrote, iclass 40, count 0 2006.257.21:07:16.13#ibcon#about to read 3, iclass 40, count 0 2006.257.21:07:16.16#ibcon#read 3, iclass 40, count 0 2006.257.21:07:16.16#ibcon#about to read 4, iclass 40, count 0 2006.257.21:07:16.16#ibcon#read 4, iclass 40, count 0 2006.257.21:07:16.16#ibcon#about to read 5, iclass 40, count 0 2006.257.21:07:16.16#ibcon#read 5, iclass 40, count 0 2006.257.21:07:16.16#ibcon#about to read 6, iclass 40, count 0 2006.257.21:07:16.16#ibcon#read 6, iclass 40, count 0 2006.257.21:07:16.16#ibcon#end of sib2, iclass 40, count 0 2006.257.21:07:16.16#ibcon#*after write, iclass 40, count 0 2006.257.21:07:16.16#ibcon#*before return 0, iclass 40, count 0 2006.257.21:07:16.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:16.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:07:16.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.21:07:16.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.21:07:16.16$vck44/vblo=4,679.99 2006.257.21:07:16.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.21:07:16.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.21:07:16.16#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:16.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:16.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:16.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:16.16#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:07:16.16#ibcon#first serial, iclass 4, count 0 2006.257.21:07:16.16#ibcon#enter sib2, iclass 4, count 0 2006.257.21:07:16.16#ibcon#flushed, iclass 4, count 0 2006.257.21:07:16.16#ibcon#about to write, iclass 4, count 0 2006.257.21:07:16.16#ibcon#wrote, iclass 4, count 0 2006.257.21:07:16.16#ibcon#about to read 3, iclass 4, count 0 2006.257.21:07:16.18#ibcon#read 3, iclass 4, count 0 2006.257.21:07:16.18#ibcon#about to read 4, iclass 4, count 0 2006.257.21:07:16.18#ibcon#read 4, iclass 4, count 0 2006.257.21:07:16.18#ibcon#about to read 5, iclass 4, count 0 2006.257.21:07:16.18#ibcon#read 5, iclass 4, count 0 2006.257.21:07:16.18#ibcon#about to read 6, iclass 4, count 0 2006.257.21:07:16.18#ibcon#read 6, iclass 4, count 0 2006.257.21:07:16.18#ibcon#end of sib2, iclass 4, count 0 2006.257.21:07:16.18#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:07:16.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:07:16.18#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.21:07:16.18#ibcon#*before write, iclass 4, count 0 2006.257.21:07:16.18#ibcon#enter sib2, iclass 4, count 0 2006.257.21:07:16.18#ibcon#flushed, iclass 4, count 0 2006.257.21:07:16.18#ibcon#about to write, iclass 4, count 0 2006.257.21:07:16.18#ibcon#wrote, iclass 4, count 0 2006.257.21:07:16.18#ibcon#about to read 3, iclass 4, count 0 2006.257.21:07:16.22#ibcon#read 3, iclass 4, count 0 2006.257.21:07:16.22#ibcon#about to read 4, iclass 4, count 0 2006.257.21:07:16.22#ibcon#read 4, iclass 4, count 0 2006.257.21:07:16.22#ibcon#about to read 5, iclass 4, count 0 2006.257.21:07:16.22#ibcon#read 5, iclass 4, count 0 2006.257.21:07:16.22#ibcon#about to read 6, iclass 4, count 0 2006.257.21:07:16.22#ibcon#read 6, iclass 4, count 0 2006.257.21:07:16.22#ibcon#end of sib2, iclass 4, count 0 2006.257.21:07:16.22#ibcon#*after write, iclass 4, count 0 2006.257.21:07:16.22#ibcon#*before return 0, iclass 4, count 0 2006.257.21:07:16.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:16.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:07:16.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:07:16.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:07:16.22$vck44/vb=4,5 2006.257.21:07:16.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.21:07:16.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.21:07:16.22#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:16.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:16.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:16.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:16.28#ibcon#enter wrdev, iclass 6, count 2 2006.257.21:07:16.28#ibcon#first serial, iclass 6, count 2 2006.257.21:07:16.28#ibcon#enter sib2, iclass 6, count 2 2006.257.21:07:16.28#ibcon#flushed, iclass 6, count 2 2006.257.21:07:16.28#ibcon#about to write, iclass 6, count 2 2006.257.21:07:16.28#ibcon#wrote, iclass 6, count 2 2006.257.21:07:16.28#ibcon#about to read 3, iclass 6, count 2 2006.257.21:07:16.30#ibcon#read 3, iclass 6, count 2 2006.257.21:07:16.30#ibcon#about to read 4, iclass 6, count 2 2006.257.21:07:16.30#ibcon#read 4, iclass 6, count 2 2006.257.21:07:16.30#ibcon#about to read 5, iclass 6, count 2 2006.257.21:07:16.30#ibcon#read 5, iclass 6, count 2 2006.257.21:07:16.30#ibcon#about to read 6, iclass 6, count 2 2006.257.21:07:16.30#ibcon#read 6, iclass 6, count 2 2006.257.21:07:16.30#ibcon#end of sib2, iclass 6, count 2 2006.257.21:07:16.30#ibcon#*mode == 0, iclass 6, count 2 2006.257.21:07:16.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.21:07:16.30#ibcon#[27=AT04-05\r\n] 2006.257.21:07:16.30#ibcon#*before write, iclass 6, count 2 2006.257.21:07:16.30#ibcon#enter sib2, iclass 6, count 2 2006.257.21:07:16.30#ibcon#flushed, iclass 6, count 2 2006.257.21:07:16.30#ibcon#about to write, iclass 6, count 2 2006.257.21:07:16.30#ibcon#wrote, iclass 6, count 2 2006.257.21:07:16.30#ibcon#about to read 3, iclass 6, count 2 2006.257.21:07:16.33#ibcon#read 3, iclass 6, count 2 2006.257.21:07:16.33#ibcon#about to read 4, iclass 6, count 2 2006.257.21:07:16.33#ibcon#read 4, iclass 6, count 2 2006.257.21:07:16.33#ibcon#about to read 5, iclass 6, count 2 2006.257.21:07:16.33#ibcon#read 5, iclass 6, count 2 2006.257.21:07:16.33#ibcon#about to read 6, iclass 6, count 2 2006.257.21:07:16.33#ibcon#read 6, iclass 6, count 2 2006.257.21:07:16.33#ibcon#end of sib2, iclass 6, count 2 2006.257.21:07:16.33#ibcon#*after write, iclass 6, count 2 2006.257.21:07:16.33#ibcon#*before return 0, iclass 6, count 2 2006.257.21:07:16.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:16.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:07:16.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.21:07:16.33#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:16.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:16.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:16.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:16.45#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:07:16.45#ibcon#first serial, iclass 6, count 0 2006.257.21:07:16.45#ibcon#enter sib2, iclass 6, count 0 2006.257.21:07:16.45#ibcon#flushed, iclass 6, count 0 2006.257.21:07:16.45#ibcon#about to write, iclass 6, count 0 2006.257.21:07:16.45#ibcon#wrote, iclass 6, count 0 2006.257.21:07:16.45#ibcon#about to read 3, iclass 6, count 0 2006.257.21:07:16.47#ibcon#read 3, iclass 6, count 0 2006.257.21:07:16.47#ibcon#about to read 4, iclass 6, count 0 2006.257.21:07:16.47#ibcon#read 4, iclass 6, count 0 2006.257.21:07:16.47#ibcon#about to read 5, iclass 6, count 0 2006.257.21:07:16.47#ibcon#read 5, iclass 6, count 0 2006.257.21:07:16.47#ibcon#about to read 6, iclass 6, count 0 2006.257.21:07:16.47#ibcon#read 6, iclass 6, count 0 2006.257.21:07:16.47#ibcon#end of sib2, iclass 6, count 0 2006.257.21:07:16.47#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:07:16.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:07:16.47#ibcon#[27=USB\r\n] 2006.257.21:07:16.47#ibcon#*before write, iclass 6, count 0 2006.257.21:07:16.47#ibcon#enter sib2, iclass 6, count 0 2006.257.21:07:16.47#ibcon#flushed, iclass 6, count 0 2006.257.21:07:16.47#ibcon#about to write, iclass 6, count 0 2006.257.21:07:16.47#ibcon#wrote, iclass 6, count 0 2006.257.21:07:16.47#ibcon#about to read 3, iclass 6, count 0 2006.257.21:07:16.50#ibcon#read 3, iclass 6, count 0 2006.257.21:07:16.50#ibcon#about to read 4, iclass 6, count 0 2006.257.21:07:16.50#ibcon#read 4, iclass 6, count 0 2006.257.21:07:16.50#ibcon#about to read 5, iclass 6, count 0 2006.257.21:07:16.50#ibcon#read 5, iclass 6, count 0 2006.257.21:07:16.50#ibcon#about to read 6, iclass 6, count 0 2006.257.21:07:16.50#ibcon#read 6, iclass 6, count 0 2006.257.21:07:16.50#ibcon#end of sib2, iclass 6, count 0 2006.257.21:07:16.50#ibcon#*after write, iclass 6, count 0 2006.257.21:07:16.50#ibcon#*before return 0, iclass 6, count 0 2006.257.21:07:16.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:16.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:07:16.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:07:16.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:07:16.50$vck44/vblo=5,709.99 2006.257.21:07:16.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.21:07:16.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.21:07:16.50#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:16.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:16.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:16.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:16.50#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:07:16.50#ibcon#first serial, iclass 10, count 0 2006.257.21:07:16.50#ibcon#enter sib2, iclass 10, count 0 2006.257.21:07:16.50#ibcon#flushed, iclass 10, count 0 2006.257.21:07:16.50#ibcon#about to write, iclass 10, count 0 2006.257.21:07:16.50#ibcon#wrote, iclass 10, count 0 2006.257.21:07:16.50#ibcon#about to read 3, iclass 10, count 0 2006.257.21:07:16.52#ibcon#read 3, iclass 10, count 0 2006.257.21:07:16.52#ibcon#about to read 4, iclass 10, count 0 2006.257.21:07:16.52#ibcon#read 4, iclass 10, count 0 2006.257.21:07:16.52#ibcon#about to read 5, iclass 10, count 0 2006.257.21:07:16.52#ibcon#read 5, iclass 10, count 0 2006.257.21:07:16.52#ibcon#about to read 6, iclass 10, count 0 2006.257.21:07:16.52#ibcon#read 6, iclass 10, count 0 2006.257.21:07:16.52#ibcon#end of sib2, iclass 10, count 0 2006.257.21:07:16.52#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:07:16.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:07:16.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.21:07:16.52#ibcon#*before write, iclass 10, count 0 2006.257.21:07:16.52#ibcon#enter sib2, iclass 10, count 0 2006.257.21:07:16.52#ibcon#flushed, iclass 10, count 0 2006.257.21:07:16.52#ibcon#about to write, iclass 10, count 0 2006.257.21:07:16.52#ibcon#wrote, iclass 10, count 0 2006.257.21:07:16.52#ibcon#about to read 3, iclass 10, count 0 2006.257.21:07:16.56#ibcon#read 3, iclass 10, count 0 2006.257.21:07:16.56#ibcon#about to read 4, iclass 10, count 0 2006.257.21:07:16.56#ibcon#read 4, iclass 10, count 0 2006.257.21:07:16.56#ibcon#about to read 5, iclass 10, count 0 2006.257.21:07:16.56#ibcon#read 5, iclass 10, count 0 2006.257.21:07:16.56#ibcon#about to read 6, iclass 10, count 0 2006.257.21:07:16.56#ibcon#read 6, iclass 10, count 0 2006.257.21:07:16.56#ibcon#end of sib2, iclass 10, count 0 2006.257.21:07:16.56#ibcon#*after write, iclass 10, count 0 2006.257.21:07:16.56#ibcon#*before return 0, iclass 10, count 0 2006.257.21:07:16.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:16.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:07:16.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:07:16.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:07:16.56$vck44/vb=5,4 2006.257.21:07:16.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.21:07:16.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.21:07:16.56#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:16.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:16.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:16.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:16.62#ibcon#enter wrdev, iclass 12, count 2 2006.257.21:07:16.62#ibcon#first serial, iclass 12, count 2 2006.257.21:07:16.62#ibcon#enter sib2, iclass 12, count 2 2006.257.21:07:16.62#ibcon#flushed, iclass 12, count 2 2006.257.21:07:16.62#ibcon#about to write, iclass 12, count 2 2006.257.21:07:16.62#ibcon#wrote, iclass 12, count 2 2006.257.21:07:16.62#ibcon#about to read 3, iclass 12, count 2 2006.257.21:07:16.64#ibcon#read 3, iclass 12, count 2 2006.257.21:07:16.64#ibcon#about to read 4, iclass 12, count 2 2006.257.21:07:16.64#ibcon#read 4, iclass 12, count 2 2006.257.21:07:16.64#ibcon#about to read 5, iclass 12, count 2 2006.257.21:07:16.64#ibcon#read 5, iclass 12, count 2 2006.257.21:07:16.64#ibcon#about to read 6, iclass 12, count 2 2006.257.21:07:16.64#ibcon#read 6, iclass 12, count 2 2006.257.21:07:16.64#ibcon#end of sib2, iclass 12, count 2 2006.257.21:07:16.64#ibcon#*mode == 0, iclass 12, count 2 2006.257.21:07:16.64#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.21:07:16.64#ibcon#[27=AT05-04\r\n] 2006.257.21:07:16.64#ibcon#*before write, iclass 12, count 2 2006.257.21:07:16.64#ibcon#enter sib2, iclass 12, count 2 2006.257.21:07:16.64#ibcon#flushed, iclass 12, count 2 2006.257.21:07:16.64#ibcon#about to write, iclass 12, count 2 2006.257.21:07:16.64#ibcon#wrote, iclass 12, count 2 2006.257.21:07:16.64#ibcon#about to read 3, iclass 12, count 2 2006.257.21:07:16.67#ibcon#read 3, iclass 12, count 2 2006.257.21:07:16.67#ibcon#about to read 4, iclass 12, count 2 2006.257.21:07:16.67#ibcon#read 4, iclass 12, count 2 2006.257.21:07:16.67#ibcon#about to read 5, iclass 12, count 2 2006.257.21:07:16.67#ibcon#read 5, iclass 12, count 2 2006.257.21:07:16.67#ibcon#about to read 6, iclass 12, count 2 2006.257.21:07:16.67#ibcon#read 6, iclass 12, count 2 2006.257.21:07:16.67#ibcon#end of sib2, iclass 12, count 2 2006.257.21:07:16.67#ibcon#*after write, iclass 12, count 2 2006.257.21:07:16.67#ibcon#*before return 0, iclass 12, count 2 2006.257.21:07:16.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:16.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:07:16.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.21:07:16.67#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:16.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:16.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:16.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:16.79#ibcon#enter wrdev, iclass 12, count 0 2006.257.21:07:16.79#ibcon#first serial, iclass 12, count 0 2006.257.21:07:16.79#ibcon#enter sib2, iclass 12, count 0 2006.257.21:07:16.79#ibcon#flushed, iclass 12, count 0 2006.257.21:07:16.79#ibcon#about to write, iclass 12, count 0 2006.257.21:07:16.79#ibcon#wrote, iclass 12, count 0 2006.257.21:07:16.79#ibcon#about to read 3, iclass 12, count 0 2006.257.21:07:16.81#ibcon#read 3, iclass 12, count 0 2006.257.21:07:16.81#ibcon#about to read 4, iclass 12, count 0 2006.257.21:07:16.81#ibcon#read 4, iclass 12, count 0 2006.257.21:07:16.81#ibcon#about to read 5, iclass 12, count 0 2006.257.21:07:16.81#ibcon#read 5, iclass 12, count 0 2006.257.21:07:16.81#ibcon#about to read 6, iclass 12, count 0 2006.257.21:07:16.81#ibcon#read 6, iclass 12, count 0 2006.257.21:07:16.81#ibcon#end of sib2, iclass 12, count 0 2006.257.21:07:16.81#ibcon#*mode == 0, iclass 12, count 0 2006.257.21:07:16.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.21:07:16.81#ibcon#[27=USB\r\n] 2006.257.21:07:16.81#ibcon#*before write, iclass 12, count 0 2006.257.21:07:16.81#ibcon#enter sib2, iclass 12, count 0 2006.257.21:07:16.81#ibcon#flushed, iclass 12, count 0 2006.257.21:07:16.81#ibcon#about to write, iclass 12, count 0 2006.257.21:07:16.81#ibcon#wrote, iclass 12, count 0 2006.257.21:07:16.81#ibcon#about to read 3, iclass 12, count 0 2006.257.21:07:16.84#ibcon#read 3, iclass 12, count 0 2006.257.21:07:16.84#ibcon#about to read 4, iclass 12, count 0 2006.257.21:07:16.84#ibcon#read 4, iclass 12, count 0 2006.257.21:07:16.84#ibcon#about to read 5, iclass 12, count 0 2006.257.21:07:16.84#ibcon#read 5, iclass 12, count 0 2006.257.21:07:16.84#ibcon#about to read 6, iclass 12, count 0 2006.257.21:07:16.84#ibcon#read 6, iclass 12, count 0 2006.257.21:07:16.84#ibcon#end of sib2, iclass 12, count 0 2006.257.21:07:16.84#ibcon#*after write, iclass 12, count 0 2006.257.21:07:16.84#ibcon#*before return 0, iclass 12, count 0 2006.257.21:07:16.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:16.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:07:16.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.21:07:16.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.21:07:16.84$vck44/vblo=6,719.99 2006.257.21:07:16.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.21:07:16.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.21:07:16.84#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:16.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:07:16.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:07:16.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:07:16.84#ibcon#enter wrdev, iclass 14, count 0 2006.257.21:07:16.84#ibcon#first serial, iclass 14, count 0 2006.257.21:07:16.84#ibcon#enter sib2, iclass 14, count 0 2006.257.21:07:16.84#ibcon#flushed, iclass 14, count 0 2006.257.21:07:16.84#ibcon#about to write, iclass 14, count 0 2006.257.21:07:16.84#ibcon#wrote, iclass 14, count 0 2006.257.21:07:16.84#ibcon#about to read 3, iclass 14, count 0 2006.257.21:07:16.86#ibcon#read 3, iclass 14, count 0 2006.257.21:07:16.86#ibcon#about to read 4, iclass 14, count 0 2006.257.21:07:16.86#ibcon#read 4, iclass 14, count 0 2006.257.21:07:16.86#ibcon#about to read 5, iclass 14, count 0 2006.257.21:07:16.86#ibcon#read 5, iclass 14, count 0 2006.257.21:07:16.86#ibcon#about to read 6, iclass 14, count 0 2006.257.21:07:16.86#ibcon#read 6, iclass 14, count 0 2006.257.21:07:16.86#ibcon#end of sib2, iclass 14, count 0 2006.257.21:07:16.86#ibcon#*mode == 0, iclass 14, count 0 2006.257.21:07:16.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.21:07:16.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.21:07:16.86#ibcon#*before write, iclass 14, count 0 2006.257.21:07:16.86#ibcon#enter sib2, iclass 14, count 0 2006.257.21:07:16.86#ibcon#flushed, iclass 14, count 0 2006.257.21:07:16.86#ibcon#about to write, iclass 14, count 0 2006.257.21:07:16.86#ibcon#wrote, iclass 14, count 0 2006.257.21:07:16.86#ibcon#about to read 3, iclass 14, count 0 2006.257.21:07:16.90#ibcon#read 3, iclass 14, count 0 2006.257.21:07:16.90#ibcon#about to read 4, iclass 14, count 0 2006.257.21:07:16.90#ibcon#read 4, iclass 14, count 0 2006.257.21:07:16.90#ibcon#about to read 5, iclass 14, count 0 2006.257.21:07:16.90#ibcon#read 5, iclass 14, count 0 2006.257.21:07:16.90#ibcon#about to read 6, iclass 14, count 0 2006.257.21:07:16.90#ibcon#read 6, iclass 14, count 0 2006.257.21:07:16.90#ibcon#end of sib2, iclass 14, count 0 2006.257.21:07:16.90#ibcon#*after write, iclass 14, count 0 2006.257.21:07:16.90#ibcon#*before return 0, iclass 14, count 0 2006.257.21:07:16.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:07:16.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:07:16.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.21:07:16.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.21:07:16.90$vck44/vb=6,4 2006.257.21:07:16.90#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.21:07:16.90#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.21:07:16.90#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:16.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:07:16.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:07:16.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:07:16.96#ibcon#enter wrdev, iclass 16, count 2 2006.257.21:07:16.96#ibcon#first serial, iclass 16, count 2 2006.257.21:07:16.96#ibcon#enter sib2, iclass 16, count 2 2006.257.21:07:16.96#ibcon#flushed, iclass 16, count 2 2006.257.21:07:16.96#ibcon#about to write, iclass 16, count 2 2006.257.21:07:16.96#ibcon#wrote, iclass 16, count 2 2006.257.21:07:16.96#ibcon#about to read 3, iclass 16, count 2 2006.257.21:07:16.98#ibcon#read 3, iclass 16, count 2 2006.257.21:07:16.98#ibcon#about to read 4, iclass 16, count 2 2006.257.21:07:16.98#ibcon#read 4, iclass 16, count 2 2006.257.21:07:16.98#ibcon#about to read 5, iclass 16, count 2 2006.257.21:07:16.98#ibcon#read 5, iclass 16, count 2 2006.257.21:07:16.98#ibcon#about to read 6, iclass 16, count 2 2006.257.21:07:16.98#ibcon#read 6, iclass 16, count 2 2006.257.21:07:16.98#ibcon#end of sib2, iclass 16, count 2 2006.257.21:07:16.98#ibcon#*mode == 0, iclass 16, count 2 2006.257.21:07:16.98#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.21:07:16.98#ibcon#[27=AT06-04\r\n] 2006.257.21:07:16.98#ibcon#*before write, iclass 16, count 2 2006.257.21:07:16.98#ibcon#enter sib2, iclass 16, count 2 2006.257.21:07:16.98#ibcon#flushed, iclass 16, count 2 2006.257.21:07:16.98#ibcon#about to write, iclass 16, count 2 2006.257.21:07:16.98#ibcon#wrote, iclass 16, count 2 2006.257.21:07:16.98#ibcon#about to read 3, iclass 16, count 2 2006.257.21:07:17.01#ibcon#read 3, iclass 16, count 2 2006.257.21:07:17.01#ibcon#about to read 4, iclass 16, count 2 2006.257.21:07:17.01#ibcon#read 4, iclass 16, count 2 2006.257.21:07:17.01#ibcon#about to read 5, iclass 16, count 2 2006.257.21:07:17.01#ibcon#read 5, iclass 16, count 2 2006.257.21:07:17.01#ibcon#about to read 6, iclass 16, count 2 2006.257.21:07:17.01#ibcon#read 6, iclass 16, count 2 2006.257.21:07:17.01#ibcon#end of sib2, iclass 16, count 2 2006.257.21:07:17.01#ibcon#*after write, iclass 16, count 2 2006.257.21:07:17.01#ibcon#*before return 0, iclass 16, count 2 2006.257.21:07:17.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:07:17.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:07:17.01#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.21:07:17.01#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:17.01#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:07:17.13#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:07:17.13#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:07:17.13#ibcon#enter wrdev, iclass 16, count 0 2006.257.21:07:17.13#ibcon#first serial, iclass 16, count 0 2006.257.21:07:17.13#ibcon#enter sib2, iclass 16, count 0 2006.257.21:07:17.13#ibcon#flushed, iclass 16, count 0 2006.257.21:07:17.13#ibcon#about to write, iclass 16, count 0 2006.257.21:07:17.13#ibcon#wrote, iclass 16, count 0 2006.257.21:07:17.13#ibcon#about to read 3, iclass 16, count 0 2006.257.21:07:17.15#ibcon#read 3, iclass 16, count 0 2006.257.21:07:17.15#ibcon#about to read 4, iclass 16, count 0 2006.257.21:07:17.15#ibcon#read 4, iclass 16, count 0 2006.257.21:07:17.15#ibcon#about to read 5, iclass 16, count 0 2006.257.21:07:17.15#ibcon#read 5, iclass 16, count 0 2006.257.21:07:17.15#ibcon#about to read 6, iclass 16, count 0 2006.257.21:07:17.15#ibcon#read 6, iclass 16, count 0 2006.257.21:07:17.15#ibcon#end of sib2, iclass 16, count 0 2006.257.21:07:17.15#ibcon#*mode == 0, iclass 16, count 0 2006.257.21:07:17.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.21:07:17.15#ibcon#[27=USB\r\n] 2006.257.21:07:17.15#ibcon#*before write, iclass 16, count 0 2006.257.21:07:17.15#ibcon#enter sib2, iclass 16, count 0 2006.257.21:07:17.15#ibcon#flushed, iclass 16, count 0 2006.257.21:07:17.15#ibcon#about to write, iclass 16, count 0 2006.257.21:07:17.15#ibcon#wrote, iclass 16, count 0 2006.257.21:07:17.15#ibcon#about to read 3, iclass 16, count 0 2006.257.21:07:17.18#ibcon#read 3, iclass 16, count 0 2006.257.21:07:17.18#ibcon#about to read 4, iclass 16, count 0 2006.257.21:07:17.18#ibcon#read 4, iclass 16, count 0 2006.257.21:07:17.18#ibcon#about to read 5, iclass 16, count 0 2006.257.21:07:17.18#ibcon#read 5, iclass 16, count 0 2006.257.21:07:17.18#ibcon#about to read 6, iclass 16, count 0 2006.257.21:07:17.18#ibcon#read 6, iclass 16, count 0 2006.257.21:07:17.18#ibcon#end of sib2, iclass 16, count 0 2006.257.21:07:17.18#ibcon#*after write, iclass 16, count 0 2006.257.21:07:17.18#ibcon#*before return 0, iclass 16, count 0 2006.257.21:07:17.18#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:07:17.18#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:07:17.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.21:07:17.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.21:07:17.18$vck44/vblo=7,734.99 2006.257.21:07:17.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.21:07:17.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.21:07:17.18#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:17.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:17.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:17.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:17.18#ibcon#enter wrdev, iclass 18, count 0 2006.257.21:07:17.18#ibcon#first serial, iclass 18, count 0 2006.257.21:07:17.18#ibcon#enter sib2, iclass 18, count 0 2006.257.21:07:17.18#ibcon#flushed, iclass 18, count 0 2006.257.21:07:17.18#ibcon#about to write, iclass 18, count 0 2006.257.21:07:17.18#ibcon#wrote, iclass 18, count 0 2006.257.21:07:17.18#ibcon#about to read 3, iclass 18, count 0 2006.257.21:07:17.20#ibcon#read 3, iclass 18, count 0 2006.257.21:07:17.20#ibcon#about to read 4, iclass 18, count 0 2006.257.21:07:17.20#ibcon#read 4, iclass 18, count 0 2006.257.21:07:17.20#ibcon#about to read 5, iclass 18, count 0 2006.257.21:07:17.20#ibcon#read 5, iclass 18, count 0 2006.257.21:07:17.20#ibcon#about to read 6, iclass 18, count 0 2006.257.21:07:17.20#ibcon#read 6, iclass 18, count 0 2006.257.21:07:17.20#ibcon#end of sib2, iclass 18, count 0 2006.257.21:07:17.20#ibcon#*mode == 0, iclass 18, count 0 2006.257.21:07:17.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.21:07:17.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.21:07:17.20#ibcon#*before write, iclass 18, count 0 2006.257.21:07:17.20#ibcon#enter sib2, iclass 18, count 0 2006.257.21:07:17.20#ibcon#flushed, iclass 18, count 0 2006.257.21:07:17.20#ibcon#about to write, iclass 18, count 0 2006.257.21:07:17.20#ibcon#wrote, iclass 18, count 0 2006.257.21:07:17.20#ibcon#about to read 3, iclass 18, count 0 2006.257.21:07:17.24#ibcon#read 3, iclass 18, count 0 2006.257.21:07:17.24#ibcon#about to read 4, iclass 18, count 0 2006.257.21:07:17.24#ibcon#read 4, iclass 18, count 0 2006.257.21:07:17.24#ibcon#about to read 5, iclass 18, count 0 2006.257.21:07:17.24#ibcon#read 5, iclass 18, count 0 2006.257.21:07:17.24#ibcon#about to read 6, iclass 18, count 0 2006.257.21:07:17.24#ibcon#read 6, iclass 18, count 0 2006.257.21:07:17.24#ibcon#end of sib2, iclass 18, count 0 2006.257.21:07:17.24#ibcon#*after write, iclass 18, count 0 2006.257.21:07:17.24#ibcon#*before return 0, iclass 18, count 0 2006.257.21:07:17.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:17.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:07:17.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.21:07:17.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.21:07:17.24$vck44/vb=7,4 2006.257.21:07:17.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.21:07:17.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.21:07:17.24#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:17.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:17.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:17.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:17.30#ibcon#enter wrdev, iclass 20, count 2 2006.257.21:07:17.30#ibcon#first serial, iclass 20, count 2 2006.257.21:07:17.30#ibcon#enter sib2, iclass 20, count 2 2006.257.21:07:17.30#ibcon#flushed, iclass 20, count 2 2006.257.21:07:17.30#ibcon#about to write, iclass 20, count 2 2006.257.21:07:17.30#ibcon#wrote, iclass 20, count 2 2006.257.21:07:17.30#ibcon#about to read 3, iclass 20, count 2 2006.257.21:07:17.32#ibcon#read 3, iclass 20, count 2 2006.257.21:07:17.32#ibcon#about to read 4, iclass 20, count 2 2006.257.21:07:17.32#ibcon#read 4, iclass 20, count 2 2006.257.21:07:17.32#ibcon#about to read 5, iclass 20, count 2 2006.257.21:07:17.32#ibcon#read 5, iclass 20, count 2 2006.257.21:07:17.32#ibcon#about to read 6, iclass 20, count 2 2006.257.21:07:17.32#ibcon#read 6, iclass 20, count 2 2006.257.21:07:17.32#ibcon#end of sib2, iclass 20, count 2 2006.257.21:07:17.32#ibcon#*mode == 0, iclass 20, count 2 2006.257.21:07:17.32#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.21:07:17.32#ibcon#[27=AT07-04\r\n] 2006.257.21:07:17.32#ibcon#*before write, iclass 20, count 2 2006.257.21:07:17.32#ibcon#enter sib2, iclass 20, count 2 2006.257.21:07:17.32#ibcon#flushed, iclass 20, count 2 2006.257.21:07:17.32#ibcon#about to write, iclass 20, count 2 2006.257.21:07:17.32#ibcon#wrote, iclass 20, count 2 2006.257.21:07:17.32#ibcon#about to read 3, iclass 20, count 2 2006.257.21:07:17.35#ibcon#read 3, iclass 20, count 2 2006.257.21:07:17.35#ibcon#about to read 4, iclass 20, count 2 2006.257.21:07:17.35#ibcon#read 4, iclass 20, count 2 2006.257.21:07:17.35#ibcon#about to read 5, iclass 20, count 2 2006.257.21:07:17.35#ibcon#read 5, iclass 20, count 2 2006.257.21:07:17.35#ibcon#about to read 6, iclass 20, count 2 2006.257.21:07:17.35#ibcon#read 6, iclass 20, count 2 2006.257.21:07:17.35#ibcon#end of sib2, iclass 20, count 2 2006.257.21:07:17.35#ibcon#*after write, iclass 20, count 2 2006.257.21:07:17.35#ibcon#*before return 0, iclass 20, count 2 2006.257.21:07:17.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:17.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:07:17.35#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.21:07:17.35#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:17.35#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:17.47#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:17.47#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:17.47#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:07:17.47#ibcon#first serial, iclass 20, count 0 2006.257.21:07:17.47#ibcon#enter sib2, iclass 20, count 0 2006.257.21:07:17.47#ibcon#flushed, iclass 20, count 0 2006.257.21:07:17.47#ibcon#about to write, iclass 20, count 0 2006.257.21:07:17.47#ibcon#wrote, iclass 20, count 0 2006.257.21:07:17.47#ibcon#about to read 3, iclass 20, count 0 2006.257.21:07:17.49#ibcon#read 3, iclass 20, count 0 2006.257.21:07:17.49#ibcon#about to read 4, iclass 20, count 0 2006.257.21:07:17.49#ibcon#read 4, iclass 20, count 0 2006.257.21:07:17.49#ibcon#about to read 5, iclass 20, count 0 2006.257.21:07:17.49#ibcon#read 5, iclass 20, count 0 2006.257.21:07:17.49#ibcon#about to read 6, iclass 20, count 0 2006.257.21:07:17.49#ibcon#read 6, iclass 20, count 0 2006.257.21:07:17.49#ibcon#end of sib2, iclass 20, count 0 2006.257.21:07:17.49#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:07:17.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:07:17.49#ibcon#[27=USB\r\n] 2006.257.21:07:17.49#ibcon#*before write, iclass 20, count 0 2006.257.21:07:17.49#ibcon#enter sib2, iclass 20, count 0 2006.257.21:07:17.49#ibcon#flushed, iclass 20, count 0 2006.257.21:07:17.49#ibcon#about to write, iclass 20, count 0 2006.257.21:07:17.49#ibcon#wrote, iclass 20, count 0 2006.257.21:07:17.49#ibcon#about to read 3, iclass 20, count 0 2006.257.21:07:17.52#ibcon#read 3, iclass 20, count 0 2006.257.21:07:17.52#ibcon#about to read 4, iclass 20, count 0 2006.257.21:07:17.52#ibcon#read 4, iclass 20, count 0 2006.257.21:07:17.52#ibcon#about to read 5, iclass 20, count 0 2006.257.21:07:17.52#ibcon#read 5, iclass 20, count 0 2006.257.21:07:17.52#ibcon#about to read 6, iclass 20, count 0 2006.257.21:07:17.52#ibcon#read 6, iclass 20, count 0 2006.257.21:07:17.52#ibcon#end of sib2, iclass 20, count 0 2006.257.21:07:17.52#ibcon#*after write, iclass 20, count 0 2006.257.21:07:17.52#ibcon#*before return 0, iclass 20, count 0 2006.257.21:07:17.52#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:17.52#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:07:17.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:07:17.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:07:17.52$vck44/vblo=8,744.99 2006.257.21:07:17.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.21:07:17.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.21:07:17.52#ibcon#ireg 17 cls_cnt 0 2006.257.21:07:17.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:17.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:17.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:17.52#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:07:17.52#ibcon#first serial, iclass 22, count 0 2006.257.21:07:17.52#ibcon#enter sib2, iclass 22, count 0 2006.257.21:07:17.52#ibcon#flushed, iclass 22, count 0 2006.257.21:07:17.52#ibcon#about to write, iclass 22, count 0 2006.257.21:07:17.52#ibcon#wrote, iclass 22, count 0 2006.257.21:07:17.52#ibcon#about to read 3, iclass 22, count 0 2006.257.21:07:17.54#ibcon#read 3, iclass 22, count 0 2006.257.21:07:17.54#ibcon#about to read 4, iclass 22, count 0 2006.257.21:07:17.54#ibcon#read 4, iclass 22, count 0 2006.257.21:07:17.54#ibcon#about to read 5, iclass 22, count 0 2006.257.21:07:17.54#ibcon#read 5, iclass 22, count 0 2006.257.21:07:17.54#ibcon#about to read 6, iclass 22, count 0 2006.257.21:07:17.54#ibcon#read 6, iclass 22, count 0 2006.257.21:07:17.54#ibcon#end of sib2, iclass 22, count 0 2006.257.21:07:17.54#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:07:17.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:07:17.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.21:07:17.54#ibcon#*before write, iclass 22, count 0 2006.257.21:07:17.54#ibcon#enter sib2, iclass 22, count 0 2006.257.21:07:17.54#ibcon#flushed, iclass 22, count 0 2006.257.21:07:17.54#ibcon#about to write, iclass 22, count 0 2006.257.21:07:17.54#ibcon#wrote, iclass 22, count 0 2006.257.21:07:17.54#ibcon#about to read 3, iclass 22, count 0 2006.257.21:07:17.58#ibcon#read 3, iclass 22, count 0 2006.257.21:07:17.58#ibcon#about to read 4, iclass 22, count 0 2006.257.21:07:17.58#ibcon#read 4, iclass 22, count 0 2006.257.21:07:17.58#ibcon#about to read 5, iclass 22, count 0 2006.257.21:07:17.58#ibcon#read 5, iclass 22, count 0 2006.257.21:07:17.58#ibcon#about to read 6, iclass 22, count 0 2006.257.21:07:17.58#ibcon#read 6, iclass 22, count 0 2006.257.21:07:17.58#ibcon#end of sib2, iclass 22, count 0 2006.257.21:07:17.58#ibcon#*after write, iclass 22, count 0 2006.257.21:07:17.58#ibcon#*before return 0, iclass 22, count 0 2006.257.21:07:17.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:17.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:07:17.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:07:17.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:07:17.58$vck44/vb=8,4 2006.257.21:07:17.58#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.21:07:17.58#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.21:07:17.58#ibcon#ireg 11 cls_cnt 2 2006.257.21:07:17.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:17.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:17.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:17.64#ibcon#enter wrdev, iclass 24, count 2 2006.257.21:07:17.64#ibcon#first serial, iclass 24, count 2 2006.257.21:07:17.64#ibcon#enter sib2, iclass 24, count 2 2006.257.21:07:17.64#ibcon#flushed, iclass 24, count 2 2006.257.21:07:17.64#ibcon#about to write, iclass 24, count 2 2006.257.21:07:17.64#ibcon#wrote, iclass 24, count 2 2006.257.21:07:17.64#ibcon#about to read 3, iclass 24, count 2 2006.257.21:07:17.66#ibcon#read 3, iclass 24, count 2 2006.257.21:07:17.66#ibcon#about to read 4, iclass 24, count 2 2006.257.21:07:17.66#ibcon#read 4, iclass 24, count 2 2006.257.21:07:17.66#ibcon#about to read 5, iclass 24, count 2 2006.257.21:07:17.66#ibcon#read 5, iclass 24, count 2 2006.257.21:07:17.66#ibcon#about to read 6, iclass 24, count 2 2006.257.21:07:17.66#ibcon#read 6, iclass 24, count 2 2006.257.21:07:17.66#ibcon#end of sib2, iclass 24, count 2 2006.257.21:07:17.66#ibcon#*mode == 0, iclass 24, count 2 2006.257.21:07:17.66#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.21:07:17.66#ibcon#[27=AT08-04\r\n] 2006.257.21:07:17.66#ibcon#*before write, iclass 24, count 2 2006.257.21:07:17.66#ibcon#enter sib2, iclass 24, count 2 2006.257.21:07:17.66#ibcon#flushed, iclass 24, count 2 2006.257.21:07:17.66#ibcon#about to write, iclass 24, count 2 2006.257.21:07:17.66#ibcon#wrote, iclass 24, count 2 2006.257.21:07:17.66#ibcon#about to read 3, iclass 24, count 2 2006.257.21:07:17.69#ibcon#read 3, iclass 24, count 2 2006.257.21:07:17.69#ibcon#about to read 4, iclass 24, count 2 2006.257.21:07:17.69#ibcon#read 4, iclass 24, count 2 2006.257.21:07:17.69#ibcon#about to read 5, iclass 24, count 2 2006.257.21:07:17.69#ibcon#read 5, iclass 24, count 2 2006.257.21:07:17.69#ibcon#about to read 6, iclass 24, count 2 2006.257.21:07:17.69#ibcon#read 6, iclass 24, count 2 2006.257.21:07:17.69#ibcon#end of sib2, iclass 24, count 2 2006.257.21:07:17.69#ibcon#*after write, iclass 24, count 2 2006.257.21:07:17.69#ibcon#*before return 0, iclass 24, count 2 2006.257.21:07:17.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:17.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:07:17.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.21:07:17.69#ibcon#ireg 7 cls_cnt 0 2006.257.21:07:17.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:17.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:17.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:17.81#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:07:17.81#ibcon#first serial, iclass 24, count 0 2006.257.21:07:17.81#ibcon#enter sib2, iclass 24, count 0 2006.257.21:07:17.81#ibcon#flushed, iclass 24, count 0 2006.257.21:07:17.81#ibcon#about to write, iclass 24, count 0 2006.257.21:07:17.81#ibcon#wrote, iclass 24, count 0 2006.257.21:07:17.81#ibcon#about to read 3, iclass 24, count 0 2006.257.21:07:17.83#ibcon#read 3, iclass 24, count 0 2006.257.21:07:17.83#ibcon#about to read 4, iclass 24, count 0 2006.257.21:07:17.83#ibcon#read 4, iclass 24, count 0 2006.257.21:07:17.83#ibcon#about to read 5, iclass 24, count 0 2006.257.21:07:17.83#ibcon#read 5, iclass 24, count 0 2006.257.21:07:17.83#ibcon#about to read 6, iclass 24, count 0 2006.257.21:07:17.83#ibcon#read 6, iclass 24, count 0 2006.257.21:07:17.83#ibcon#end of sib2, iclass 24, count 0 2006.257.21:07:17.83#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:07:17.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:07:17.83#ibcon#[27=USB\r\n] 2006.257.21:07:17.83#ibcon#*before write, iclass 24, count 0 2006.257.21:07:17.83#ibcon#enter sib2, iclass 24, count 0 2006.257.21:07:17.83#ibcon#flushed, iclass 24, count 0 2006.257.21:07:17.83#ibcon#about to write, iclass 24, count 0 2006.257.21:07:17.83#ibcon#wrote, iclass 24, count 0 2006.257.21:07:17.83#ibcon#about to read 3, iclass 24, count 0 2006.257.21:07:17.86#ibcon#read 3, iclass 24, count 0 2006.257.21:07:17.86#ibcon#about to read 4, iclass 24, count 0 2006.257.21:07:17.86#ibcon#read 4, iclass 24, count 0 2006.257.21:07:17.86#ibcon#about to read 5, iclass 24, count 0 2006.257.21:07:17.86#ibcon#read 5, iclass 24, count 0 2006.257.21:07:17.86#ibcon#about to read 6, iclass 24, count 0 2006.257.21:07:17.86#ibcon#read 6, iclass 24, count 0 2006.257.21:07:17.86#ibcon#end of sib2, iclass 24, count 0 2006.257.21:07:17.86#ibcon#*after write, iclass 24, count 0 2006.257.21:07:17.86#ibcon#*before return 0, iclass 24, count 0 2006.257.21:07:17.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:17.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:07:17.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:07:17.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:07:17.86$vck44/vabw=wide 2006.257.21:07:17.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.21:07:17.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.21:07:17.86#ibcon#ireg 8 cls_cnt 0 2006.257.21:07:17.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:17.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:17.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:17.86#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:07:17.86#ibcon#first serial, iclass 26, count 0 2006.257.21:07:17.86#ibcon#enter sib2, iclass 26, count 0 2006.257.21:07:17.86#ibcon#flushed, iclass 26, count 0 2006.257.21:07:17.86#ibcon#about to write, iclass 26, count 0 2006.257.21:07:17.86#ibcon#wrote, iclass 26, count 0 2006.257.21:07:17.86#ibcon#about to read 3, iclass 26, count 0 2006.257.21:07:17.88#ibcon#read 3, iclass 26, count 0 2006.257.21:07:17.88#ibcon#about to read 4, iclass 26, count 0 2006.257.21:07:17.88#ibcon#read 4, iclass 26, count 0 2006.257.21:07:17.88#ibcon#about to read 5, iclass 26, count 0 2006.257.21:07:17.88#ibcon#read 5, iclass 26, count 0 2006.257.21:07:17.88#ibcon#about to read 6, iclass 26, count 0 2006.257.21:07:17.88#ibcon#read 6, iclass 26, count 0 2006.257.21:07:17.88#ibcon#end of sib2, iclass 26, count 0 2006.257.21:07:17.88#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:07:17.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:07:17.88#ibcon#[25=BW32\r\n] 2006.257.21:07:17.88#ibcon#*before write, iclass 26, count 0 2006.257.21:07:17.88#ibcon#enter sib2, iclass 26, count 0 2006.257.21:07:17.88#ibcon#flushed, iclass 26, count 0 2006.257.21:07:17.88#ibcon#about to write, iclass 26, count 0 2006.257.21:07:17.88#ibcon#wrote, iclass 26, count 0 2006.257.21:07:17.88#ibcon#about to read 3, iclass 26, count 0 2006.257.21:07:17.91#ibcon#read 3, iclass 26, count 0 2006.257.21:07:17.91#ibcon#about to read 4, iclass 26, count 0 2006.257.21:07:17.91#ibcon#read 4, iclass 26, count 0 2006.257.21:07:17.91#ibcon#about to read 5, iclass 26, count 0 2006.257.21:07:17.91#ibcon#read 5, iclass 26, count 0 2006.257.21:07:17.91#ibcon#about to read 6, iclass 26, count 0 2006.257.21:07:17.91#ibcon#read 6, iclass 26, count 0 2006.257.21:07:17.91#ibcon#end of sib2, iclass 26, count 0 2006.257.21:07:17.91#ibcon#*after write, iclass 26, count 0 2006.257.21:07:17.91#ibcon#*before return 0, iclass 26, count 0 2006.257.21:07:17.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:17.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:07:17.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:07:17.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:07:17.91$vck44/vbbw=wide 2006.257.21:07:17.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.21:07:17.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.21:07:17.91#ibcon#ireg 8 cls_cnt 0 2006.257.21:07:17.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:07:17.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:07:17.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:07:17.98#ibcon#enter wrdev, iclass 28, count 0 2006.257.21:07:17.98#ibcon#first serial, iclass 28, count 0 2006.257.21:07:17.98#ibcon#enter sib2, iclass 28, count 0 2006.257.21:07:17.98#ibcon#flushed, iclass 28, count 0 2006.257.21:07:17.98#ibcon#about to write, iclass 28, count 0 2006.257.21:07:17.98#ibcon#wrote, iclass 28, count 0 2006.257.21:07:17.98#ibcon#about to read 3, iclass 28, count 0 2006.257.21:07:18.00#ibcon#read 3, iclass 28, count 0 2006.257.21:07:18.00#ibcon#about to read 4, iclass 28, count 0 2006.257.21:07:18.00#ibcon#read 4, iclass 28, count 0 2006.257.21:07:18.00#ibcon#about to read 5, iclass 28, count 0 2006.257.21:07:18.00#ibcon#read 5, iclass 28, count 0 2006.257.21:07:18.00#ibcon#about to read 6, iclass 28, count 0 2006.257.21:07:18.00#ibcon#read 6, iclass 28, count 0 2006.257.21:07:18.00#ibcon#end of sib2, iclass 28, count 0 2006.257.21:07:18.00#ibcon#*mode == 0, iclass 28, count 0 2006.257.21:07:18.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.21:07:18.00#ibcon#[27=BW32\r\n] 2006.257.21:07:18.00#ibcon#*before write, iclass 28, count 0 2006.257.21:07:18.00#ibcon#enter sib2, iclass 28, count 0 2006.257.21:07:18.00#ibcon#flushed, iclass 28, count 0 2006.257.21:07:18.00#ibcon#about to write, iclass 28, count 0 2006.257.21:07:18.00#ibcon#wrote, iclass 28, count 0 2006.257.21:07:18.00#ibcon#about to read 3, iclass 28, count 0 2006.257.21:07:18.03#ibcon#read 3, iclass 28, count 0 2006.257.21:07:18.03#ibcon#about to read 4, iclass 28, count 0 2006.257.21:07:18.03#ibcon#read 4, iclass 28, count 0 2006.257.21:07:18.03#ibcon#about to read 5, iclass 28, count 0 2006.257.21:07:18.03#ibcon#read 5, iclass 28, count 0 2006.257.21:07:18.03#ibcon#about to read 6, iclass 28, count 0 2006.257.21:07:18.03#ibcon#read 6, iclass 28, count 0 2006.257.21:07:18.03#ibcon#end of sib2, iclass 28, count 0 2006.257.21:07:18.03#ibcon#*after write, iclass 28, count 0 2006.257.21:07:18.03#ibcon#*before return 0, iclass 28, count 0 2006.257.21:07:18.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:07:18.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:07:18.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.21:07:18.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.21:07:18.03$setupk4/ifdk4 2006.257.21:07:18.03$ifdk4/lo= 2006.257.21:07:18.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.21:07:18.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.21:07:18.03$ifdk4/patch= 2006.257.21:07:18.04$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.21:07:18.04$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.21:07:18.04$setupk4/!*+20s 2006.257.21:07:24.21#abcon#<5=/14 1.1 2.7 17.74 941015.3\r\n> 2006.257.21:07:24.23#abcon#{5=INTERFACE CLEAR} 2006.257.21:07:24.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:07:31.14#trakl#Source acquired 2006.257.21:07:32.14#flagr#flagr/antenna,acquired 2006.257.21:07:32.55$setupk4/"tpicd 2006.257.21:07:32.55$setupk4/echo=off 2006.257.21:07:32.55$setupk4/xlog=off 2006.257.21:07:32.55:!2006.257.21:16:23 2006.257.21:16:23.00:preob 2006.257.21:16:24.13/onsource/TRACKING 2006.257.21:16:24.13:!2006.257.21:16:33 2006.257.21:16:33.00:"tape 2006.257.21:16:33.00:"st=record 2006.257.21:16:33.00:data_valid=on 2006.257.21:16:33.00:midob 2006.257.21:16:33.13/onsource/TRACKING 2006.257.21:16:33.13/wx/17.75,1015.4,94 2006.257.21:16:33.20/cable/+6.4850E-03 2006.257.21:16:34.29/va/01,08,usb,yes,32,34 2006.257.21:16:34.29/va/02,07,usb,yes,34,35 2006.257.21:16:34.29/va/03,08,usb,yes,31,33 2006.257.21:16:34.29/va/04,07,usb,yes,35,37 2006.257.21:16:34.29/va/05,04,usb,yes,32,32 2006.257.21:16:34.29/va/06,04,usb,yes,35,35 2006.257.21:16:34.29/va/07,04,usb,yes,36,36 2006.257.21:16:34.29/va/08,04,usb,yes,30,37 2006.257.21:16:34.52/valo/01,524.99,yes,locked 2006.257.21:16:34.52/valo/02,534.99,yes,locked 2006.257.21:16:34.52/valo/03,564.99,yes,locked 2006.257.21:16:34.52/valo/04,624.99,yes,locked 2006.257.21:16:34.52/valo/05,734.99,yes,locked 2006.257.21:16:34.52/valo/06,814.99,yes,locked 2006.257.21:16:34.52/valo/07,864.99,yes,locked 2006.257.21:16:34.52/valo/08,884.99,yes,locked 2006.257.21:16:35.61/vb/01,04,usb,yes,30,28 2006.257.21:16:35.61/vb/02,05,usb,yes,29,29 2006.257.21:16:35.61/vb/03,04,usb,yes,30,33 2006.257.21:16:35.61/vb/04,05,usb,yes,30,29 2006.257.21:16:35.61/vb/05,04,usb,yes,26,29 2006.257.21:16:35.61/vb/06,04,usb,yes,31,27 2006.257.21:16:35.61/vb/07,04,usb,yes,31,31 2006.257.21:16:35.61/vb/08,04,usb,yes,28,31 2006.257.21:16:35.84/vblo/01,629.99,yes,locked 2006.257.21:16:35.84/vblo/02,634.99,yes,locked 2006.257.21:16:35.84/vblo/03,649.99,yes,locked 2006.257.21:16:35.84/vblo/04,679.99,yes,locked 2006.257.21:16:35.84/vblo/05,709.99,yes,locked 2006.257.21:16:35.84/vblo/06,719.99,yes,locked 2006.257.21:16:35.84/vblo/07,734.99,yes,locked 2006.257.21:16:35.84/vblo/08,744.99,yes,locked 2006.257.21:16:35.99/vabw/8 2006.257.21:16:36.14/vbbw/8 2006.257.21:16:36.23/xfe/off,on,15.2 2006.257.21:16:36.60/ifatt/23,28,28,28 2006.257.21:16:37.07/fmout-gps/S +4.56E-07 2006.257.21:16:37.11:!2006.257.21:21:43 2006.257.21:21:43.00:data_valid=off 2006.257.21:21:43.00:"et 2006.257.21:21:43.01:!+3s 2006.257.21:21:46.03:"tape 2006.257.21:21:46.03:postob 2006.257.21:21:46.16/cable/+6.4853E-03 2006.257.21:21:46.16/wx/17.76,1015.5,95 2006.257.21:21:46.22/fmout-gps/S +4.55E-07 2006.257.21:21:46.22:scan_name=257-2126,jd0609,100 2006.257.21:21:46.23:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.257.21:21:48.14#flagr#flagr/antenna,new-source 2006.257.21:21:48.14:checkk5 2006.257.21:21:48.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.21:21:48.85/chk_autoobs//k5ts2/ autoobs is running! 2006.257.21:21:49.20/chk_autoobs//k5ts3/ autoobs is running! 2006.257.21:21:49.55/chk_autoobs//k5ts4/ autoobs is running! 2006.257.21:21:49.88/chk_obsdata//k5ts1/T2572116??a.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.257.21:21:50.21/chk_obsdata//k5ts2/T2572116??b.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.257.21:21:50.54/chk_obsdata//k5ts3/T2572116??c.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.257.21:21:50.87/chk_obsdata//k5ts4/T2572116??d.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.257.21:21:51.53/k5log//k5ts1_log_newline 2006.257.21:21:52.21/k5log//k5ts2_log_newline 2006.257.21:21:52.88/k5log//k5ts3_log_newline 2006.257.21:21:53.54/k5log//k5ts4_log_newline 2006.257.21:21:53.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.21:21:53.56:setupk4=1 2006.257.21:21:53.56$setupk4/echo=on 2006.257.21:21:53.56$setupk4/pcalon 2006.257.21:21:53.56$pcalon/"no phase cal control is implemented here 2006.257.21:21:53.56$setupk4/"tpicd=stop 2006.257.21:21:53.56$setupk4/"rec=synch_on 2006.257.21:21:53.56$setupk4/"rec_mode=128 2006.257.21:21:53.56$setupk4/!* 2006.257.21:21:53.56$setupk4/recpk4 2006.257.21:21:53.56$recpk4/recpatch= 2006.257.21:21:53.56$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.21:21:53.56$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.21:21:53.56$setupk4/vck44 2006.257.21:21:53.56$vck44/valo=1,524.99 2006.257.21:21:53.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.21:21:53.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.21:21:53.56#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:53.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:53.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:53.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:53.56#ibcon#enter wrdev, iclass 17, count 0 2006.257.21:21:53.56#ibcon#first serial, iclass 17, count 0 2006.257.21:21:53.56#ibcon#enter sib2, iclass 17, count 0 2006.257.21:21:53.56#ibcon#flushed, iclass 17, count 0 2006.257.21:21:53.56#ibcon#about to write, iclass 17, count 0 2006.257.21:21:53.56#ibcon#wrote, iclass 17, count 0 2006.257.21:21:53.56#ibcon#about to read 3, iclass 17, count 0 2006.257.21:21:53.58#ibcon#read 3, iclass 17, count 0 2006.257.21:21:53.58#ibcon#about to read 4, iclass 17, count 0 2006.257.21:21:53.58#ibcon#read 4, iclass 17, count 0 2006.257.21:21:53.58#ibcon#about to read 5, iclass 17, count 0 2006.257.21:21:53.58#ibcon#read 5, iclass 17, count 0 2006.257.21:21:53.58#ibcon#about to read 6, iclass 17, count 0 2006.257.21:21:53.58#ibcon#read 6, iclass 17, count 0 2006.257.21:21:53.58#ibcon#end of sib2, iclass 17, count 0 2006.257.21:21:53.58#ibcon#*mode == 0, iclass 17, count 0 2006.257.21:21:53.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.21:21:53.58#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.21:21:53.58#ibcon#*before write, iclass 17, count 0 2006.257.21:21:53.58#ibcon#enter sib2, iclass 17, count 0 2006.257.21:21:53.58#ibcon#flushed, iclass 17, count 0 2006.257.21:21:53.58#ibcon#about to write, iclass 17, count 0 2006.257.21:21:53.58#ibcon#wrote, iclass 17, count 0 2006.257.21:21:53.58#ibcon#about to read 3, iclass 17, count 0 2006.257.21:21:53.63#ibcon#read 3, iclass 17, count 0 2006.257.21:21:53.63#ibcon#about to read 4, iclass 17, count 0 2006.257.21:21:53.63#ibcon#read 4, iclass 17, count 0 2006.257.21:21:53.63#ibcon#about to read 5, iclass 17, count 0 2006.257.21:21:53.63#ibcon#read 5, iclass 17, count 0 2006.257.21:21:53.63#ibcon#about to read 6, iclass 17, count 0 2006.257.21:21:53.63#ibcon#read 6, iclass 17, count 0 2006.257.21:21:53.63#ibcon#end of sib2, iclass 17, count 0 2006.257.21:21:53.63#ibcon#*after write, iclass 17, count 0 2006.257.21:21:53.63#ibcon#*before return 0, iclass 17, count 0 2006.257.21:21:53.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:53.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:53.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.21:21:53.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.21:21:53.63$vck44/va=1,8 2006.257.21:21:53.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.21:21:53.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.21:21:53.63#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:53.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:53.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:53.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:53.63#ibcon#enter wrdev, iclass 19, count 2 2006.257.21:21:53.63#ibcon#first serial, iclass 19, count 2 2006.257.21:21:53.63#ibcon#enter sib2, iclass 19, count 2 2006.257.21:21:53.63#ibcon#flushed, iclass 19, count 2 2006.257.21:21:53.63#ibcon#about to write, iclass 19, count 2 2006.257.21:21:53.63#ibcon#wrote, iclass 19, count 2 2006.257.21:21:53.63#ibcon#about to read 3, iclass 19, count 2 2006.257.21:21:53.65#ibcon#read 3, iclass 19, count 2 2006.257.21:21:53.65#ibcon#about to read 4, iclass 19, count 2 2006.257.21:21:53.65#ibcon#read 4, iclass 19, count 2 2006.257.21:21:53.65#ibcon#about to read 5, iclass 19, count 2 2006.257.21:21:53.65#ibcon#read 5, iclass 19, count 2 2006.257.21:21:53.65#ibcon#about to read 6, iclass 19, count 2 2006.257.21:21:53.65#ibcon#read 6, iclass 19, count 2 2006.257.21:21:53.65#ibcon#end of sib2, iclass 19, count 2 2006.257.21:21:53.65#ibcon#*mode == 0, iclass 19, count 2 2006.257.21:21:53.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.21:21:53.65#ibcon#[25=AT01-08\r\n] 2006.257.21:21:53.65#ibcon#*before write, iclass 19, count 2 2006.257.21:21:53.65#ibcon#enter sib2, iclass 19, count 2 2006.257.21:21:53.65#ibcon#flushed, iclass 19, count 2 2006.257.21:21:53.65#ibcon#about to write, iclass 19, count 2 2006.257.21:21:53.65#ibcon#wrote, iclass 19, count 2 2006.257.21:21:53.65#ibcon#about to read 3, iclass 19, count 2 2006.257.21:21:53.68#ibcon#read 3, iclass 19, count 2 2006.257.21:21:53.68#ibcon#about to read 4, iclass 19, count 2 2006.257.21:21:53.68#ibcon#read 4, iclass 19, count 2 2006.257.21:21:53.68#ibcon#about to read 5, iclass 19, count 2 2006.257.21:21:53.68#ibcon#read 5, iclass 19, count 2 2006.257.21:21:53.68#ibcon#about to read 6, iclass 19, count 2 2006.257.21:21:53.68#ibcon#read 6, iclass 19, count 2 2006.257.21:21:53.68#ibcon#end of sib2, iclass 19, count 2 2006.257.21:21:53.68#ibcon#*after write, iclass 19, count 2 2006.257.21:21:53.68#ibcon#*before return 0, iclass 19, count 2 2006.257.21:21:53.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:53.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:53.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.21:21:53.68#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:53.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:53.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:53.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:53.80#ibcon#enter wrdev, iclass 19, count 0 2006.257.21:21:53.80#ibcon#first serial, iclass 19, count 0 2006.257.21:21:53.80#ibcon#enter sib2, iclass 19, count 0 2006.257.21:21:53.80#ibcon#flushed, iclass 19, count 0 2006.257.21:21:53.80#ibcon#about to write, iclass 19, count 0 2006.257.21:21:53.80#ibcon#wrote, iclass 19, count 0 2006.257.21:21:53.80#ibcon#about to read 3, iclass 19, count 0 2006.257.21:21:53.82#ibcon#read 3, iclass 19, count 0 2006.257.21:21:53.82#ibcon#about to read 4, iclass 19, count 0 2006.257.21:21:53.82#ibcon#read 4, iclass 19, count 0 2006.257.21:21:53.82#ibcon#about to read 5, iclass 19, count 0 2006.257.21:21:53.82#ibcon#read 5, iclass 19, count 0 2006.257.21:21:53.82#ibcon#about to read 6, iclass 19, count 0 2006.257.21:21:53.82#ibcon#read 6, iclass 19, count 0 2006.257.21:21:53.82#ibcon#end of sib2, iclass 19, count 0 2006.257.21:21:53.82#ibcon#*mode == 0, iclass 19, count 0 2006.257.21:21:53.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.21:21:53.82#ibcon#[25=USB\r\n] 2006.257.21:21:53.82#ibcon#*before write, iclass 19, count 0 2006.257.21:21:53.82#ibcon#enter sib2, iclass 19, count 0 2006.257.21:21:53.82#ibcon#flushed, iclass 19, count 0 2006.257.21:21:53.82#ibcon#about to write, iclass 19, count 0 2006.257.21:21:53.82#ibcon#wrote, iclass 19, count 0 2006.257.21:21:53.82#ibcon#about to read 3, iclass 19, count 0 2006.257.21:21:53.85#ibcon#read 3, iclass 19, count 0 2006.257.21:21:53.85#ibcon#about to read 4, iclass 19, count 0 2006.257.21:21:53.85#ibcon#read 4, iclass 19, count 0 2006.257.21:21:53.85#ibcon#about to read 5, iclass 19, count 0 2006.257.21:21:53.85#ibcon#read 5, iclass 19, count 0 2006.257.21:21:53.85#ibcon#about to read 6, iclass 19, count 0 2006.257.21:21:53.85#ibcon#read 6, iclass 19, count 0 2006.257.21:21:53.85#ibcon#end of sib2, iclass 19, count 0 2006.257.21:21:53.85#ibcon#*after write, iclass 19, count 0 2006.257.21:21:53.85#ibcon#*before return 0, iclass 19, count 0 2006.257.21:21:53.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:53.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:53.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.21:21:53.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.21:21:53.85$vck44/valo=2,534.99 2006.257.21:21:53.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.21:21:53.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.21:21:53.85#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:53.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:53.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:53.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:53.85#ibcon#enter wrdev, iclass 21, count 0 2006.257.21:21:53.85#ibcon#first serial, iclass 21, count 0 2006.257.21:21:53.85#ibcon#enter sib2, iclass 21, count 0 2006.257.21:21:53.85#ibcon#flushed, iclass 21, count 0 2006.257.21:21:53.85#ibcon#about to write, iclass 21, count 0 2006.257.21:21:53.85#ibcon#wrote, iclass 21, count 0 2006.257.21:21:53.85#ibcon#about to read 3, iclass 21, count 0 2006.257.21:21:53.87#ibcon#read 3, iclass 21, count 0 2006.257.21:21:53.87#ibcon#about to read 4, iclass 21, count 0 2006.257.21:21:53.87#ibcon#read 4, iclass 21, count 0 2006.257.21:21:53.87#ibcon#about to read 5, iclass 21, count 0 2006.257.21:21:53.87#ibcon#read 5, iclass 21, count 0 2006.257.21:21:53.87#ibcon#about to read 6, iclass 21, count 0 2006.257.21:21:53.87#ibcon#read 6, iclass 21, count 0 2006.257.21:21:53.87#ibcon#end of sib2, iclass 21, count 0 2006.257.21:21:53.87#ibcon#*mode == 0, iclass 21, count 0 2006.257.21:21:53.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.21:21:53.87#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.21:21:53.87#ibcon#*before write, iclass 21, count 0 2006.257.21:21:53.87#ibcon#enter sib2, iclass 21, count 0 2006.257.21:21:53.87#ibcon#flushed, iclass 21, count 0 2006.257.21:21:53.87#ibcon#about to write, iclass 21, count 0 2006.257.21:21:53.87#ibcon#wrote, iclass 21, count 0 2006.257.21:21:53.87#ibcon#about to read 3, iclass 21, count 0 2006.257.21:21:53.91#ibcon#read 3, iclass 21, count 0 2006.257.21:21:53.91#ibcon#about to read 4, iclass 21, count 0 2006.257.21:21:53.91#ibcon#read 4, iclass 21, count 0 2006.257.21:21:53.91#ibcon#about to read 5, iclass 21, count 0 2006.257.21:21:53.91#ibcon#read 5, iclass 21, count 0 2006.257.21:21:53.91#ibcon#about to read 6, iclass 21, count 0 2006.257.21:21:53.91#ibcon#read 6, iclass 21, count 0 2006.257.21:21:53.91#ibcon#end of sib2, iclass 21, count 0 2006.257.21:21:53.91#ibcon#*after write, iclass 21, count 0 2006.257.21:21:53.91#ibcon#*before return 0, iclass 21, count 0 2006.257.21:21:53.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:53.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:53.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.21:21:53.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.21:21:53.91$vck44/va=2,7 2006.257.21:21:53.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.21:21:53.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.21:21:53.91#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:53.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:53.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:53.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:53.97#ibcon#enter wrdev, iclass 23, count 2 2006.257.21:21:53.97#ibcon#first serial, iclass 23, count 2 2006.257.21:21:53.97#ibcon#enter sib2, iclass 23, count 2 2006.257.21:21:53.97#ibcon#flushed, iclass 23, count 2 2006.257.21:21:53.97#ibcon#about to write, iclass 23, count 2 2006.257.21:21:53.97#ibcon#wrote, iclass 23, count 2 2006.257.21:21:53.97#ibcon#about to read 3, iclass 23, count 2 2006.257.21:21:53.99#ibcon#read 3, iclass 23, count 2 2006.257.21:21:53.99#ibcon#about to read 4, iclass 23, count 2 2006.257.21:21:53.99#ibcon#read 4, iclass 23, count 2 2006.257.21:21:53.99#ibcon#about to read 5, iclass 23, count 2 2006.257.21:21:53.99#ibcon#read 5, iclass 23, count 2 2006.257.21:21:53.99#ibcon#about to read 6, iclass 23, count 2 2006.257.21:21:53.99#ibcon#read 6, iclass 23, count 2 2006.257.21:21:53.99#ibcon#end of sib2, iclass 23, count 2 2006.257.21:21:53.99#ibcon#*mode == 0, iclass 23, count 2 2006.257.21:21:53.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.21:21:53.99#ibcon#[25=AT02-07\r\n] 2006.257.21:21:53.99#ibcon#*before write, iclass 23, count 2 2006.257.21:21:53.99#ibcon#enter sib2, iclass 23, count 2 2006.257.21:21:53.99#ibcon#flushed, iclass 23, count 2 2006.257.21:21:53.99#ibcon#about to write, iclass 23, count 2 2006.257.21:21:53.99#ibcon#wrote, iclass 23, count 2 2006.257.21:21:53.99#ibcon#about to read 3, iclass 23, count 2 2006.257.21:21:54.02#ibcon#read 3, iclass 23, count 2 2006.257.21:21:54.02#ibcon#about to read 4, iclass 23, count 2 2006.257.21:21:54.02#ibcon#read 4, iclass 23, count 2 2006.257.21:21:54.02#ibcon#about to read 5, iclass 23, count 2 2006.257.21:21:54.02#ibcon#read 5, iclass 23, count 2 2006.257.21:21:54.02#ibcon#about to read 6, iclass 23, count 2 2006.257.21:21:54.02#ibcon#read 6, iclass 23, count 2 2006.257.21:21:54.02#ibcon#end of sib2, iclass 23, count 2 2006.257.21:21:54.02#ibcon#*after write, iclass 23, count 2 2006.257.21:21:54.02#ibcon#*before return 0, iclass 23, count 2 2006.257.21:21:54.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:54.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:54.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.21:21:54.02#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:54.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:54.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:54.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:54.14#ibcon#enter wrdev, iclass 23, count 0 2006.257.21:21:54.14#ibcon#first serial, iclass 23, count 0 2006.257.21:21:54.14#ibcon#enter sib2, iclass 23, count 0 2006.257.21:21:54.14#ibcon#flushed, iclass 23, count 0 2006.257.21:21:54.14#ibcon#about to write, iclass 23, count 0 2006.257.21:21:54.14#ibcon#wrote, iclass 23, count 0 2006.257.21:21:54.14#ibcon#about to read 3, iclass 23, count 0 2006.257.21:21:54.16#ibcon#read 3, iclass 23, count 0 2006.257.21:21:54.16#ibcon#about to read 4, iclass 23, count 0 2006.257.21:21:54.16#ibcon#read 4, iclass 23, count 0 2006.257.21:21:54.16#ibcon#about to read 5, iclass 23, count 0 2006.257.21:21:54.16#ibcon#read 5, iclass 23, count 0 2006.257.21:21:54.16#ibcon#about to read 6, iclass 23, count 0 2006.257.21:21:54.16#ibcon#read 6, iclass 23, count 0 2006.257.21:21:54.16#ibcon#end of sib2, iclass 23, count 0 2006.257.21:21:54.16#ibcon#*mode == 0, iclass 23, count 0 2006.257.21:21:54.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.21:21:54.16#ibcon#[25=USB\r\n] 2006.257.21:21:54.16#ibcon#*before write, iclass 23, count 0 2006.257.21:21:54.16#ibcon#enter sib2, iclass 23, count 0 2006.257.21:21:54.16#ibcon#flushed, iclass 23, count 0 2006.257.21:21:54.16#ibcon#about to write, iclass 23, count 0 2006.257.21:21:54.16#ibcon#wrote, iclass 23, count 0 2006.257.21:21:54.16#ibcon#about to read 3, iclass 23, count 0 2006.257.21:21:54.19#ibcon#read 3, iclass 23, count 0 2006.257.21:21:54.19#ibcon#about to read 4, iclass 23, count 0 2006.257.21:21:54.19#ibcon#read 4, iclass 23, count 0 2006.257.21:21:54.19#ibcon#about to read 5, iclass 23, count 0 2006.257.21:21:54.19#ibcon#read 5, iclass 23, count 0 2006.257.21:21:54.19#ibcon#about to read 6, iclass 23, count 0 2006.257.21:21:54.19#ibcon#read 6, iclass 23, count 0 2006.257.21:21:54.19#ibcon#end of sib2, iclass 23, count 0 2006.257.21:21:54.19#ibcon#*after write, iclass 23, count 0 2006.257.21:21:54.19#ibcon#*before return 0, iclass 23, count 0 2006.257.21:21:54.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:54.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:54.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.21:21:54.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.21:21:54.19$vck44/valo=3,564.99 2006.257.21:21:54.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.21:21:54.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.21:21:54.19#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:54.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:54.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:54.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:54.19#ibcon#enter wrdev, iclass 25, count 0 2006.257.21:21:54.19#ibcon#first serial, iclass 25, count 0 2006.257.21:21:54.19#ibcon#enter sib2, iclass 25, count 0 2006.257.21:21:54.19#ibcon#flushed, iclass 25, count 0 2006.257.21:21:54.19#ibcon#about to write, iclass 25, count 0 2006.257.21:21:54.19#ibcon#wrote, iclass 25, count 0 2006.257.21:21:54.19#ibcon#about to read 3, iclass 25, count 0 2006.257.21:21:54.21#ibcon#read 3, iclass 25, count 0 2006.257.21:21:54.21#ibcon#about to read 4, iclass 25, count 0 2006.257.21:21:54.21#ibcon#read 4, iclass 25, count 0 2006.257.21:21:54.21#ibcon#about to read 5, iclass 25, count 0 2006.257.21:21:54.21#ibcon#read 5, iclass 25, count 0 2006.257.21:21:54.21#ibcon#about to read 6, iclass 25, count 0 2006.257.21:21:54.21#ibcon#read 6, iclass 25, count 0 2006.257.21:21:54.21#ibcon#end of sib2, iclass 25, count 0 2006.257.21:21:54.21#ibcon#*mode == 0, iclass 25, count 0 2006.257.21:21:54.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.21:21:54.21#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.21:21:54.21#ibcon#*before write, iclass 25, count 0 2006.257.21:21:54.21#ibcon#enter sib2, iclass 25, count 0 2006.257.21:21:54.21#ibcon#flushed, iclass 25, count 0 2006.257.21:21:54.21#ibcon#about to write, iclass 25, count 0 2006.257.21:21:54.21#ibcon#wrote, iclass 25, count 0 2006.257.21:21:54.21#ibcon#about to read 3, iclass 25, count 0 2006.257.21:21:54.25#ibcon#read 3, iclass 25, count 0 2006.257.21:21:54.25#ibcon#about to read 4, iclass 25, count 0 2006.257.21:21:54.25#ibcon#read 4, iclass 25, count 0 2006.257.21:21:54.25#ibcon#about to read 5, iclass 25, count 0 2006.257.21:21:54.25#ibcon#read 5, iclass 25, count 0 2006.257.21:21:54.25#ibcon#about to read 6, iclass 25, count 0 2006.257.21:21:54.25#ibcon#read 6, iclass 25, count 0 2006.257.21:21:54.25#ibcon#end of sib2, iclass 25, count 0 2006.257.21:21:54.25#ibcon#*after write, iclass 25, count 0 2006.257.21:21:54.25#ibcon#*before return 0, iclass 25, count 0 2006.257.21:21:54.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:54.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:54.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.21:21:54.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.21:21:54.25$vck44/va=3,8 2006.257.21:21:54.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.21:21:54.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.21:21:54.25#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:54.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:54.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:54.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:54.31#ibcon#enter wrdev, iclass 27, count 2 2006.257.21:21:54.31#ibcon#first serial, iclass 27, count 2 2006.257.21:21:54.31#ibcon#enter sib2, iclass 27, count 2 2006.257.21:21:54.31#ibcon#flushed, iclass 27, count 2 2006.257.21:21:54.31#ibcon#about to write, iclass 27, count 2 2006.257.21:21:54.31#ibcon#wrote, iclass 27, count 2 2006.257.21:21:54.31#ibcon#about to read 3, iclass 27, count 2 2006.257.21:21:54.33#ibcon#read 3, iclass 27, count 2 2006.257.21:21:54.33#ibcon#about to read 4, iclass 27, count 2 2006.257.21:21:54.33#ibcon#read 4, iclass 27, count 2 2006.257.21:21:54.33#ibcon#about to read 5, iclass 27, count 2 2006.257.21:21:54.33#ibcon#read 5, iclass 27, count 2 2006.257.21:21:54.33#ibcon#about to read 6, iclass 27, count 2 2006.257.21:21:54.33#ibcon#read 6, iclass 27, count 2 2006.257.21:21:54.33#ibcon#end of sib2, iclass 27, count 2 2006.257.21:21:54.33#ibcon#*mode == 0, iclass 27, count 2 2006.257.21:21:54.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.21:21:54.33#ibcon#[25=AT03-08\r\n] 2006.257.21:21:54.33#ibcon#*before write, iclass 27, count 2 2006.257.21:21:54.33#ibcon#enter sib2, iclass 27, count 2 2006.257.21:21:54.33#ibcon#flushed, iclass 27, count 2 2006.257.21:21:54.33#ibcon#about to write, iclass 27, count 2 2006.257.21:21:54.33#ibcon#wrote, iclass 27, count 2 2006.257.21:21:54.33#ibcon#about to read 3, iclass 27, count 2 2006.257.21:21:54.36#ibcon#read 3, iclass 27, count 2 2006.257.21:21:54.36#ibcon#about to read 4, iclass 27, count 2 2006.257.21:21:54.36#ibcon#read 4, iclass 27, count 2 2006.257.21:21:54.36#ibcon#about to read 5, iclass 27, count 2 2006.257.21:21:54.36#ibcon#read 5, iclass 27, count 2 2006.257.21:21:54.36#ibcon#about to read 6, iclass 27, count 2 2006.257.21:21:54.36#ibcon#read 6, iclass 27, count 2 2006.257.21:21:54.36#ibcon#end of sib2, iclass 27, count 2 2006.257.21:21:54.36#ibcon#*after write, iclass 27, count 2 2006.257.21:21:54.36#ibcon#*before return 0, iclass 27, count 2 2006.257.21:21:54.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:54.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:54.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.21:21:54.36#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:54.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:54.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:54.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:54.48#ibcon#enter wrdev, iclass 27, count 0 2006.257.21:21:54.48#ibcon#first serial, iclass 27, count 0 2006.257.21:21:54.48#ibcon#enter sib2, iclass 27, count 0 2006.257.21:21:54.48#ibcon#flushed, iclass 27, count 0 2006.257.21:21:54.48#ibcon#about to write, iclass 27, count 0 2006.257.21:21:54.48#ibcon#wrote, iclass 27, count 0 2006.257.21:21:54.48#ibcon#about to read 3, iclass 27, count 0 2006.257.21:21:54.50#ibcon#read 3, iclass 27, count 0 2006.257.21:21:54.50#ibcon#about to read 4, iclass 27, count 0 2006.257.21:21:54.50#ibcon#read 4, iclass 27, count 0 2006.257.21:21:54.50#ibcon#about to read 5, iclass 27, count 0 2006.257.21:21:54.50#ibcon#read 5, iclass 27, count 0 2006.257.21:21:54.50#ibcon#about to read 6, iclass 27, count 0 2006.257.21:21:54.50#ibcon#read 6, iclass 27, count 0 2006.257.21:21:54.50#ibcon#end of sib2, iclass 27, count 0 2006.257.21:21:54.50#ibcon#*mode == 0, iclass 27, count 0 2006.257.21:21:54.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.21:21:54.50#ibcon#[25=USB\r\n] 2006.257.21:21:54.50#ibcon#*before write, iclass 27, count 0 2006.257.21:21:54.50#ibcon#enter sib2, iclass 27, count 0 2006.257.21:21:54.50#ibcon#flushed, iclass 27, count 0 2006.257.21:21:54.50#ibcon#about to write, iclass 27, count 0 2006.257.21:21:54.50#ibcon#wrote, iclass 27, count 0 2006.257.21:21:54.50#ibcon#about to read 3, iclass 27, count 0 2006.257.21:21:54.53#ibcon#read 3, iclass 27, count 0 2006.257.21:21:54.53#ibcon#about to read 4, iclass 27, count 0 2006.257.21:21:54.53#ibcon#read 4, iclass 27, count 0 2006.257.21:21:54.53#ibcon#about to read 5, iclass 27, count 0 2006.257.21:21:54.53#ibcon#read 5, iclass 27, count 0 2006.257.21:21:54.53#ibcon#about to read 6, iclass 27, count 0 2006.257.21:21:54.53#ibcon#read 6, iclass 27, count 0 2006.257.21:21:54.53#ibcon#end of sib2, iclass 27, count 0 2006.257.21:21:54.53#ibcon#*after write, iclass 27, count 0 2006.257.21:21:54.53#ibcon#*before return 0, iclass 27, count 0 2006.257.21:21:54.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:54.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:54.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.21:21:54.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.21:21:54.53$vck44/valo=4,624.99 2006.257.21:21:54.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.21:21:54.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.21:21:54.53#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:54.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:54.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:54.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:54.53#ibcon#enter wrdev, iclass 29, count 0 2006.257.21:21:54.53#ibcon#first serial, iclass 29, count 0 2006.257.21:21:54.53#ibcon#enter sib2, iclass 29, count 0 2006.257.21:21:54.53#ibcon#flushed, iclass 29, count 0 2006.257.21:21:54.53#ibcon#about to write, iclass 29, count 0 2006.257.21:21:54.53#ibcon#wrote, iclass 29, count 0 2006.257.21:21:54.53#ibcon#about to read 3, iclass 29, count 0 2006.257.21:21:54.55#ibcon#read 3, iclass 29, count 0 2006.257.21:21:54.55#ibcon#about to read 4, iclass 29, count 0 2006.257.21:21:54.55#ibcon#read 4, iclass 29, count 0 2006.257.21:21:54.55#ibcon#about to read 5, iclass 29, count 0 2006.257.21:21:54.55#ibcon#read 5, iclass 29, count 0 2006.257.21:21:54.55#ibcon#about to read 6, iclass 29, count 0 2006.257.21:21:54.55#ibcon#read 6, iclass 29, count 0 2006.257.21:21:54.55#ibcon#end of sib2, iclass 29, count 0 2006.257.21:21:54.55#ibcon#*mode == 0, iclass 29, count 0 2006.257.21:21:54.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.21:21:54.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.21:21:54.55#ibcon#*before write, iclass 29, count 0 2006.257.21:21:54.55#ibcon#enter sib2, iclass 29, count 0 2006.257.21:21:54.55#ibcon#flushed, iclass 29, count 0 2006.257.21:21:54.55#ibcon#about to write, iclass 29, count 0 2006.257.21:21:54.55#ibcon#wrote, iclass 29, count 0 2006.257.21:21:54.55#ibcon#about to read 3, iclass 29, count 0 2006.257.21:21:54.59#ibcon#read 3, iclass 29, count 0 2006.257.21:21:54.59#ibcon#about to read 4, iclass 29, count 0 2006.257.21:21:54.59#ibcon#read 4, iclass 29, count 0 2006.257.21:21:54.59#ibcon#about to read 5, iclass 29, count 0 2006.257.21:21:54.59#ibcon#read 5, iclass 29, count 0 2006.257.21:21:54.59#ibcon#about to read 6, iclass 29, count 0 2006.257.21:21:54.59#ibcon#read 6, iclass 29, count 0 2006.257.21:21:54.59#ibcon#end of sib2, iclass 29, count 0 2006.257.21:21:54.59#ibcon#*after write, iclass 29, count 0 2006.257.21:21:54.59#ibcon#*before return 0, iclass 29, count 0 2006.257.21:21:54.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:54.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:54.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.21:21:54.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.21:21:54.59$vck44/va=4,7 2006.257.21:21:54.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.21:21:54.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.21:21:54.59#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:54.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:54.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:54.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:54.65#ibcon#enter wrdev, iclass 31, count 2 2006.257.21:21:54.65#ibcon#first serial, iclass 31, count 2 2006.257.21:21:54.65#ibcon#enter sib2, iclass 31, count 2 2006.257.21:21:54.65#ibcon#flushed, iclass 31, count 2 2006.257.21:21:54.65#ibcon#about to write, iclass 31, count 2 2006.257.21:21:54.65#ibcon#wrote, iclass 31, count 2 2006.257.21:21:54.65#ibcon#about to read 3, iclass 31, count 2 2006.257.21:21:54.67#ibcon#read 3, iclass 31, count 2 2006.257.21:21:54.67#ibcon#about to read 4, iclass 31, count 2 2006.257.21:21:54.67#ibcon#read 4, iclass 31, count 2 2006.257.21:21:54.67#ibcon#about to read 5, iclass 31, count 2 2006.257.21:21:54.67#ibcon#read 5, iclass 31, count 2 2006.257.21:21:54.67#ibcon#about to read 6, iclass 31, count 2 2006.257.21:21:54.67#ibcon#read 6, iclass 31, count 2 2006.257.21:21:54.67#ibcon#end of sib2, iclass 31, count 2 2006.257.21:21:54.67#ibcon#*mode == 0, iclass 31, count 2 2006.257.21:21:54.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.21:21:54.67#ibcon#[25=AT04-07\r\n] 2006.257.21:21:54.67#ibcon#*before write, iclass 31, count 2 2006.257.21:21:54.67#ibcon#enter sib2, iclass 31, count 2 2006.257.21:21:54.67#ibcon#flushed, iclass 31, count 2 2006.257.21:21:54.67#ibcon#about to write, iclass 31, count 2 2006.257.21:21:54.67#ibcon#wrote, iclass 31, count 2 2006.257.21:21:54.67#ibcon#about to read 3, iclass 31, count 2 2006.257.21:21:54.70#ibcon#read 3, iclass 31, count 2 2006.257.21:21:54.70#ibcon#about to read 4, iclass 31, count 2 2006.257.21:21:54.70#ibcon#read 4, iclass 31, count 2 2006.257.21:21:54.70#ibcon#about to read 5, iclass 31, count 2 2006.257.21:21:54.70#ibcon#read 5, iclass 31, count 2 2006.257.21:21:54.70#ibcon#about to read 6, iclass 31, count 2 2006.257.21:21:54.70#ibcon#read 6, iclass 31, count 2 2006.257.21:21:54.70#ibcon#end of sib2, iclass 31, count 2 2006.257.21:21:54.70#ibcon#*after write, iclass 31, count 2 2006.257.21:21:54.70#ibcon#*before return 0, iclass 31, count 2 2006.257.21:21:54.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:54.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:54.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.21:21:54.70#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:54.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:54.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:54.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:54.82#ibcon#enter wrdev, iclass 31, count 0 2006.257.21:21:54.82#ibcon#first serial, iclass 31, count 0 2006.257.21:21:54.82#ibcon#enter sib2, iclass 31, count 0 2006.257.21:21:54.82#ibcon#flushed, iclass 31, count 0 2006.257.21:21:54.82#ibcon#about to write, iclass 31, count 0 2006.257.21:21:54.82#ibcon#wrote, iclass 31, count 0 2006.257.21:21:54.82#ibcon#about to read 3, iclass 31, count 0 2006.257.21:21:54.84#ibcon#read 3, iclass 31, count 0 2006.257.21:21:54.84#ibcon#about to read 4, iclass 31, count 0 2006.257.21:21:54.84#ibcon#read 4, iclass 31, count 0 2006.257.21:21:54.84#ibcon#about to read 5, iclass 31, count 0 2006.257.21:21:54.84#ibcon#read 5, iclass 31, count 0 2006.257.21:21:54.84#ibcon#about to read 6, iclass 31, count 0 2006.257.21:21:54.84#ibcon#read 6, iclass 31, count 0 2006.257.21:21:54.84#ibcon#end of sib2, iclass 31, count 0 2006.257.21:21:54.84#ibcon#*mode == 0, iclass 31, count 0 2006.257.21:21:54.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.21:21:54.84#ibcon#[25=USB\r\n] 2006.257.21:21:54.84#ibcon#*before write, iclass 31, count 0 2006.257.21:21:54.84#ibcon#enter sib2, iclass 31, count 0 2006.257.21:21:54.84#ibcon#flushed, iclass 31, count 0 2006.257.21:21:54.84#ibcon#about to write, iclass 31, count 0 2006.257.21:21:54.84#ibcon#wrote, iclass 31, count 0 2006.257.21:21:54.84#ibcon#about to read 3, iclass 31, count 0 2006.257.21:21:54.87#ibcon#read 3, iclass 31, count 0 2006.257.21:21:54.87#ibcon#about to read 4, iclass 31, count 0 2006.257.21:21:54.87#ibcon#read 4, iclass 31, count 0 2006.257.21:21:54.87#ibcon#about to read 5, iclass 31, count 0 2006.257.21:21:54.87#ibcon#read 5, iclass 31, count 0 2006.257.21:21:54.87#ibcon#about to read 6, iclass 31, count 0 2006.257.21:21:54.87#ibcon#read 6, iclass 31, count 0 2006.257.21:21:54.87#ibcon#end of sib2, iclass 31, count 0 2006.257.21:21:54.87#ibcon#*after write, iclass 31, count 0 2006.257.21:21:54.87#ibcon#*before return 0, iclass 31, count 0 2006.257.21:21:54.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:54.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:54.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.21:21:54.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.21:21:54.87$vck44/valo=5,734.99 2006.257.21:21:54.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.21:21:54.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.21:21:54.87#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:54.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:54.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:54.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:54.87#ibcon#enter wrdev, iclass 33, count 0 2006.257.21:21:54.87#ibcon#first serial, iclass 33, count 0 2006.257.21:21:54.87#ibcon#enter sib2, iclass 33, count 0 2006.257.21:21:54.87#ibcon#flushed, iclass 33, count 0 2006.257.21:21:54.87#ibcon#about to write, iclass 33, count 0 2006.257.21:21:54.87#ibcon#wrote, iclass 33, count 0 2006.257.21:21:54.87#ibcon#about to read 3, iclass 33, count 0 2006.257.21:21:54.89#ibcon#read 3, iclass 33, count 0 2006.257.21:21:54.89#ibcon#about to read 4, iclass 33, count 0 2006.257.21:21:54.89#ibcon#read 4, iclass 33, count 0 2006.257.21:21:54.89#ibcon#about to read 5, iclass 33, count 0 2006.257.21:21:54.89#ibcon#read 5, iclass 33, count 0 2006.257.21:21:54.89#ibcon#about to read 6, iclass 33, count 0 2006.257.21:21:54.89#ibcon#read 6, iclass 33, count 0 2006.257.21:21:54.89#ibcon#end of sib2, iclass 33, count 0 2006.257.21:21:54.89#ibcon#*mode == 0, iclass 33, count 0 2006.257.21:21:54.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.21:21:54.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.21:21:54.89#ibcon#*before write, iclass 33, count 0 2006.257.21:21:54.89#ibcon#enter sib2, iclass 33, count 0 2006.257.21:21:54.89#ibcon#flushed, iclass 33, count 0 2006.257.21:21:54.89#ibcon#about to write, iclass 33, count 0 2006.257.21:21:54.89#ibcon#wrote, iclass 33, count 0 2006.257.21:21:54.89#ibcon#about to read 3, iclass 33, count 0 2006.257.21:21:54.93#ibcon#read 3, iclass 33, count 0 2006.257.21:21:54.93#ibcon#about to read 4, iclass 33, count 0 2006.257.21:21:54.93#ibcon#read 4, iclass 33, count 0 2006.257.21:21:54.93#ibcon#about to read 5, iclass 33, count 0 2006.257.21:21:54.93#ibcon#read 5, iclass 33, count 0 2006.257.21:21:54.93#ibcon#about to read 6, iclass 33, count 0 2006.257.21:21:54.93#ibcon#read 6, iclass 33, count 0 2006.257.21:21:54.93#ibcon#end of sib2, iclass 33, count 0 2006.257.21:21:54.93#ibcon#*after write, iclass 33, count 0 2006.257.21:21:54.93#ibcon#*before return 0, iclass 33, count 0 2006.257.21:21:54.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:54.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:54.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.21:21:54.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.21:21:54.93$vck44/va=5,4 2006.257.21:21:54.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.21:21:54.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.21:21:54.93#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:54.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:54.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:54.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:54.99#ibcon#enter wrdev, iclass 35, count 2 2006.257.21:21:54.99#ibcon#first serial, iclass 35, count 2 2006.257.21:21:54.99#ibcon#enter sib2, iclass 35, count 2 2006.257.21:21:54.99#ibcon#flushed, iclass 35, count 2 2006.257.21:21:54.99#ibcon#about to write, iclass 35, count 2 2006.257.21:21:54.99#ibcon#wrote, iclass 35, count 2 2006.257.21:21:54.99#ibcon#about to read 3, iclass 35, count 2 2006.257.21:21:55.01#ibcon#read 3, iclass 35, count 2 2006.257.21:21:55.01#ibcon#about to read 4, iclass 35, count 2 2006.257.21:21:55.01#ibcon#read 4, iclass 35, count 2 2006.257.21:21:55.01#ibcon#about to read 5, iclass 35, count 2 2006.257.21:21:55.01#ibcon#read 5, iclass 35, count 2 2006.257.21:21:55.01#ibcon#about to read 6, iclass 35, count 2 2006.257.21:21:55.01#ibcon#read 6, iclass 35, count 2 2006.257.21:21:55.01#ibcon#end of sib2, iclass 35, count 2 2006.257.21:21:55.01#ibcon#*mode == 0, iclass 35, count 2 2006.257.21:21:55.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.21:21:55.01#ibcon#[25=AT05-04\r\n] 2006.257.21:21:55.01#ibcon#*before write, iclass 35, count 2 2006.257.21:21:55.01#ibcon#enter sib2, iclass 35, count 2 2006.257.21:21:55.01#ibcon#flushed, iclass 35, count 2 2006.257.21:21:55.01#ibcon#about to write, iclass 35, count 2 2006.257.21:21:55.01#ibcon#wrote, iclass 35, count 2 2006.257.21:21:55.01#ibcon#about to read 3, iclass 35, count 2 2006.257.21:21:55.04#ibcon#read 3, iclass 35, count 2 2006.257.21:21:55.04#ibcon#about to read 4, iclass 35, count 2 2006.257.21:21:55.04#ibcon#read 4, iclass 35, count 2 2006.257.21:21:55.04#ibcon#about to read 5, iclass 35, count 2 2006.257.21:21:55.04#ibcon#read 5, iclass 35, count 2 2006.257.21:21:55.04#ibcon#about to read 6, iclass 35, count 2 2006.257.21:21:55.04#ibcon#read 6, iclass 35, count 2 2006.257.21:21:55.04#ibcon#end of sib2, iclass 35, count 2 2006.257.21:21:55.04#ibcon#*after write, iclass 35, count 2 2006.257.21:21:55.04#ibcon#*before return 0, iclass 35, count 2 2006.257.21:21:55.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:55.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:55.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.21:21:55.04#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:55.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:55.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:55.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:55.16#ibcon#enter wrdev, iclass 35, count 0 2006.257.21:21:55.16#ibcon#first serial, iclass 35, count 0 2006.257.21:21:55.16#ibcon#enter sib2, iclass 35, count 0 2006.257.21:21:55.16#ibcon#flushed, iclass 35, count 0 2006.257.21:21:55.16#ibcon#about to write, iclass 35, count 0 2006.257.21:21:55.16#ibcon#wrote, iclass 35, count 0 2006.257.21:21:55.16#ibcon#about to read 3, iclass 35, count 0 2006.257.21:21:55.18#ibcon#read 3, iclass 35, count 0 2006.257.21:21:55.18#ibcon#about to read 4, iclass 35, count 0 2006.257.21:21:55.18#ibcon#read 4, iclass 35, count 0 2006.257.21:21:55.18#ibcon#about to read 5, iclass 35, count 0 2006.257.21:21:55.18#ibcon#read 5, iclass 35, count 0 2006.257.21:21:55.18#ibcon#about to read 6, iclass 35, count 0 2006.257.21:21:55.18#ibcon#read 6, iclass 35, count 0 2006.257.21:21:55.18#ibcon#end of sib2, iclass 35, count 0 2006.257.21:21:55.18#ibcon#*mode == 0, iclass 35, count 0 2006.257.21:21:55.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.21:21:55.18#ibcon#[25=USB\r\n] 2006.257.21:21:55.18#ibcon#*before write, iclass 35, count 0 2006.257.21:21:55.18#ibcon#enter sib2, iclass 35, count 0 2006.257.21:21:55.18#ibcon#flushed, iclass 35, count 0 2006.257.21:21:55.18#ibcon#about to write, iclass 35, count 0 2006.257.21:21:55.18#ibcon#wrote, iclass 35, count 0 2006.257.21:21:55.18#ibcon#about to read 3, iclass 35, count 0 2006.257.21:21:55.21#ibcon#read 3, iclass 35, count 0 2006.257.21:21:55.21#ibcon#about to read 4, iclass 35, count 0 2006.257.21:21:55.21#ibcon#read 4, iclass 35, count 0 2006.257.21:21:55.21#ibcon#about to read 5, iclass 35, count 0 2006.257.21:21:55.21#ibcon#read 5, iclass 35, count 0 2006.257.21:21:55.21#ibcon#about to read 6, iclass 35, count 0 2006.257.21:21:55.21#ibcon#read 6, iclass 35, count 0 2006.257.21:21:55.21#ibcon#end of sib2, iclass 35, count 0 2006.257.21:21:55.21#ibcon#*after write, iclass 35, count 0 2006.257.21:21:55.21#ibcon#*before return 0, iclass 35, count 0 2006.257.21:21:55.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:55.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:55.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.21:21:55.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.21:21:55.21$vck44/valo=6,814.99 2006.257.21:21:55.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.21:21:55.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.21:21:55.21#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:55.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:55.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:55.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:55.21#ibcon#enter wrdev, iclass 37, count 0 2006.257.21:21:55.21#ibcon#first serial, iclass 37, count 0 2006.257.21:21:55.21#ibcon#enter sib2, iclass 37, count 0 2006.257.21:21:55.21#ibcon#flushed, iclass 37, count 0 2006.257.21:21:55.21#ibcon#about to write, iclass 37, count 0 2006.257.21:21:55.21#ibcon#wrote, iclass 37, count 0 2006.257.21:21:55.21#ibcon#about to read 3, iclass 37, count 0 2006.257.21:21:55.23#ibcon#read 3, iclass 37, count 0 2006.257.21:21:55.23#ibcon#about to read 4, iclass 37, count 0 2006.257.21:21:55.23#ibcon#read 4, iclass 37, count 0 2006.257.21:21:55.23#ibcon#about to read 5, iclass 37, count 0 2006.257.21:21:55.23#ibcon#read 5, iclass 37, count 0 2006.257.21:21:55.23#ibcon#about to read 6, iclass 37, count 0 2006.257.21:21:55.23#ibcon#read 6, iclass 37, count 0 2006.257.21:21:55.23#ibcon#end of sib2, iclass 37, count 0 2006.257.21:21:55.23#ibcon#*mode == 0, iclass 37, count 0 2006.257.21:21:55.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.21:21:55.23#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.21:21:55.23#ibcon#*before write, iclass 37, count 0 2006.257.21:21:55.23#ibcon#enter sib2, iclass 37, count 0 2006.257.21:21:55.23#ibcon#flushed, iclass 37, count 0 2006.257.21:21:55.23#ibcon#about to write, iclass 37, count 0 2006.257.21:21:55.23#ibcon#wrote, iclass 37, count 0 2006.257.21:21:55.23#ibcon#about to read 3, iclass 37, count 0 2006.257.21:21:55.27#ibcon#read 3, iclass 37, count 0 2006.257.21:21:55.27#ibcon#about to read 4, iclass 37, count 0 2006.257.21:21:55.27#ibcon#read 4, iclass 37, count 0 2006.257.21:21:55.27#ibcon#about to read 5, iclass 37, count 0 2006.257.21:21:55.27#ibcon#read 5, iclass 37, count 0 2006.257.21:21:55.27#ibcon#about to read 6, iclass 37, count 0 2006.257.21:21:55.27#ibcon#read 6, iclass 37, count 0 2006.257.21:21:55.27#ibcon#end of sib2, iclass 37, count 0 2006.257.21:21:55.27#ibcon#*after write, iclass 37, count 0 2006.257.21:21:55.27#ibcon#*before return 0, iclass 37, count 0 2006.257.21:21:55.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:55.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:55.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.21:21:55.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.21:21:55.27$vck44/va=6,4 2006.257.21:21:55.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.21:21:55.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.21:21:55.27#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:55.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:55.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:55.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:55.33#ibcon#enter wrdev, iclass 39, count 2 2006.257.21:21:55.33#ibcon#first serial, iclass 39, count 2 2006.257.21:21:55.33#ibcon#enter sib2, iclass 39, count 2 2006.257.21:21:55.33#ibcon#flushed, iclass 39, count 2 2006.257.21:21:55.33#ibcon#about to write, iclass 39, count 2 2006.257.21:21:55.33#ibcon#wrote, iclass 39, count 2 2006.257.21:21:55.33#ibcon#about to read 3, iclass 39, count 2 2006.257.21:21:55.35#ibcon#read 3, iclass 39, count 2 2006.257.21:21:55.35#ibcon#about to read 4, iclass 39, count 2 2006.257.21:21:55.35#ibcon#read 4, iclass 39, count 2 2006.257.21:21:55.35#ibcon#about to read 5, iclass 39, count 2 2006.257.21:21:55.35#ibcon#read 5, iclass 39, count 2 2006.257.21:21:55.35#ibcon#about to read 6, iclass 39, count 2 2006.257.21:21:55.35#ibcon#read 6, iclass 39, count 2 2006.257.21:21:55.35#ibcon#end of sib2, iclass 39, count 2 2006.257.21:21:55.35#ibcon#*mode == 0, iclass 39, count 2 2006.257.21:21:55.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.21:21:55.35#ibcon#[25=AT06-04\r\n] 2006.257.21:21:55.35#ibcon#*before write, iclass 39, count 2 2006.257.21:21:55.35#ibcon#enter sib2, iclass 39, count 2 2006.257.21:21:55.35#ibcon#flushed, iclass 39, count 2 2006.257.21:21:55.35#ibcon#about to write, iclass 39, count 2 2006.257.21:21:55.35#ibcon#wrote, iclass 39, count 2 2006.257.21:21:55.35#ibcon#about to read 3, iclass 39, count 2 2006.257.21:21:55.38#ibcon#read 3, iclass 39, count 2 2006.257.21:21:55.38#ibcon#about to read 4, iclass 39, count 2 2006.257.21:21:55.38#ibcon#read 4, iclass 39, count 2 2006.257.21:21:55.38#ibcon#about to read 5, iclass 39, count 2 2006.257.21:21:55.38#ibcon#read 5, iclass 39, count 2 2006.257.21:21:55.38#ibcon#about to read 6, iclass 39, count 2 2006.257.21:21:55.38#ibcon#read 6, iclass 39, count 2 2006.257.21:21:55.38#ibcon#end of sib2, iclass 39, count 2 2006.257.21:21:55.38#ibcon#*after write, iclass 39, count 2 2006.257.21:21:55.38#ibcon#*before return 0, iclass 39, count 2 2006.257.21:21:55.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:55.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:55.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.21:21:55.38#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:55.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:55.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:55.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:55.50#ibcon#enter wrdev, iclass 39, count 0 2006.257.21:21:55.50#ibcon#first serial, iclass 39, count 0 2006.257.21:21:55.50#ibcon#enter sib2, iclass 39, count 0 2006.257.21:21:55.50#ibcon#flushed, iclass 39, count 0 2006.257.21:21:55.50#ibcon#about to write, iclass 39, count 0 2006.257.21:21:55.50#ibcon#wrote, iclass 39, count 0 2006.257.21:21:55.50#ibcon#about to read 3, iclass 39, count 0 2006.257.21:21:55.52#ibcon#read 3, iclass 39, count 0 2006.257.21:21:55.52#ibcon#about to read 4, iclass 39, count 0 2006.257.21:21:55.52#ibcon#read 4, iclass 39, count 0 2006.257.21:21:55.52#ibcon#about to read 5, iclass 39, count 0 2006.257.21:21:55.52#ibcon#read 5, iclass 39, count 0 2006.257.21:21:55.52#ibcon#about to read 6, iclass 39, count 0 2006.257.21:21:55.52#ibcon#read 6, iclass 39, count 0 2006.257.21:21:55.52#ibcon#end of sib2, iclass 39, count 0 2006.257.21:21:55.52#ibcon#*mode == 0, iclass 39, count 0 2006.257.21:21:55.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.21:21:55.52#ibcon#[25=USB\r\n] 2006.257.21:21:55.52#ibcon#*before write, iclass 39, count 0 2006.257.21:21:55.52#ibcon#enter sib2, iclass 39, count 0 2006.257.21:21:55.52#ibcon#flushed, iclass 39, count 0 2006.257.21:21:55.52#ibcon#about to write, iclass 39, count 0 2006.257.21:21:55.52#ibcon#wrote, iclass 39, count 0 2006.257.21:21:55.52#ibcon#about to read 3, iclass 39, count 0 2006.257.21:21:55.55#ibcon#read 3, iclass 39, count 0 2006.257.21:21:55.55#ibcon#about to read 4, iclass 39, count 0 2006.257.21:21:55.55#ibcon#read 4, iclass 39, count 0 2006.257.21:21:55.55#ibcon#about to read 5, iclass 39, count 0 2006.257.21:21:55.55#ibcon#read 5, iclass 39, count 0 2006.257.21:21:55.55#ibcon#about to read 6, iclass 39, count 0 2006.257.21:21:55.55#ibcon#read 6, iclass 39, count 0 2006.257.21:21:55.55#ibcon#end of sib2, iclass 39, count 0 2006.257.21:21:55.55#ibcon#*after write, iclass 39, count 0 2006.257.21:21:55.55#ibcon#*before return 0, iclass 39, count 0 2006.257.21:21:55.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:55.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:55.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.21:21:55.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.21:21:55.55$vck44/valo=7,864.99 2006.257.21:21:55.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.21:21:55.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.21:21:55.55#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:55.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:55.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:55.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:55.55#ibcon#enter wrdev, iclass 3, count 0 2006.257.21:21:55.55#ibcon#first serial, iclass 3, count 0 2006.257.21:21:55.55#ibcon#enter sib2, iclass 3, count 0 2006.257.21:21:55.55#ibcon#flushed, iclass 3, count 0 2006.257.21:21:55.55#ibcon#about to write, iclass 3, count 0 2006.257.21:21:55.55#ibcon#wrote, iclass 3, count 0 2006.257.21:21:55.55#ibcon#about to read 3, iclass 3, count 0 2006.257.21:21:55.57#ibcon#read 3, iclass 3, count 0 2006.257.21:21:55.57#ibcon#about to read 4, iclass 3, count 0 2006.257.21:21:55.57#ibcon#read 4, iclass 3, count 0 2006.257.21:21:55.57#ibcon#about to read 5, iclass 3, count 0 2006.257.21:21:55.57#ibcon#read 5, iclass 3, count 0 2006.257.21:21:55.57#ibcon#about to read 6, iclass 3, count 0 2006.257.21:21:55.57#ibcon#read 6, iclass 3, count 0 2006.257.21:21:55.57#ibcon#end of sib2, iclass 3, count 0 2006.257.21:21:55.57#ibcon#*mode == 0, iclass 3, count 0 2006.257.21:21:55.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.21:21:55.57#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.21:21:55.57#ibcon#*before write, iclass 3, count 0 2006.257.21:21:55.57#ibcon#enter sib2, iclass 3, count 0 2006.257.21:21:55.57#ibcon#flushed, iclass 3, count 0 2006.257.21:21:55.57#ibcon#about to write, iclass 3, count 0 2006.257.21:21:55.57#ibcon#wrote, iclass 3, count 0 2006.257.21:21:55.57#ibcon#about to read 3, iclass 3, count 0 2006.257.21:21:55.61#ibcon#read 3, iclass 3, count 0 2006.257.21:21:55.61#ibcon#about to read 4, iclass 3, count 0 2006.257.21:21:55.61#ibcon#read 4, iclass 3, count 0 2006.257.21:21:55.61#ibcon#about to read 5, iclass 3, count 0 2006.257.21:21:55.61#ibcon#read 5, iclass 3, count 0 2006.257.21:21:55.61#ibcon#about to read 6, iclass 3, count 0 2006.257.21:21:55.61#ibcon#read 6, iclass 3, count 0 2006.257.21:21:55.61#ibcon#end of sib2, iclass 3, count 0 2006.257.21:21:55.61#ibcon#*after write, iclass 3, count 0 2006.257.21:21:55.61#ibcon#*before return 0, iclass 3, count 0 2006.257.21:21:55.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:55.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:55.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.21:21:55.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.21:21:55.61$vck44/va=7,4 2006.257.21:21:55.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.21:21:55.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.21:21:55.61#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:55.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:55.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:55.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:55.67#ibcon#enter wrdev, iclass 5, count 2 2006.257.21:21:55.67#ibcon#first serial, iclass 5, count 2 2006.257.21:21:55.67#ibcon#enter sib2, iclass 5, count 2 2006.257.21:21:55.67#ibcon#flushed, iclass 5, count 2 2006.257.21:21:55.67#ibcon#about to write, iclass 5, count 2 2006.257.21:21:55.67#ibcon#wrote, iclass 5, count 2 2006.257.21:21:55.67#ibcon#about to read 3, iclass 5, count 2 2006.257.21:21:55.69#ibcon#read 3, iclass 5, count 2 2006.257.21:21:55.69#ibcon#about to read 4, iclass 5, count 2 2006.257.21:21:55.69#ibcon#read 4, iclass 5, count 2 2006.257.21:21:55.69#ibcon#about to read 5, iclass 5, count 2 2006.257.21:21:55.69#ibcon#read 5, iclass 5, count 2 2006.257.21:21:55.69#ibcon#about to read 6, iclass 5, count 2 2006.257.21:21:55.69#ibcon#read 6, iclass 5, count 2 2006.257.21:21:55.69#ibcon#end of sib2, iclass 5, count 2 2006.257.21:21:55.69#ibcon#*mode == 0, iclass 5, count 2 2006.257.21:21:55.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.21:21:55.69#ibcon#[25=AT07-04\r\n] 2006.257.21:21:55.69#ibcon#*before write, iclass 5, count 2 2006.257.21:21:55.69#ibcon#enter sib2, iclass 5, count 2 2006.257.21:21:55.69#ibcon#flushed, iclass 5, count 2 2006.257.21:21:55.69#ibcon#about to write, iclass 5, count 2 2006.257.21:21:55.69#ibcon#wrote, iclass 5, count 2 2006.257.21:21:55.69#ibcon#about to read 3, iclass 5, count 2 2006.257.21:21:55.72#ibcon#read 3, iclass 5, count 2 2006.257.21:21:55.72#ibcon#about to read 4, iclass 5, count 2 2006.257.21:21:55.72#ibcon#read 4, iclass 5, count 2 2006.257.21:21:55.72#ibcon#about to read 5, iclass 5, count 2 2006.257.21:21:55.72#ibcon#read 5, iclass 5, count 2 2006.257.21:21:55.72#ibcon#about to read 6, iclass 5, count 2 2006.257.21:21:55.72#ibcon#read 6, iclass 5, count 2 2006.257.21:21:55.72#ibcon#end of sib2, iclass 5, count 2 2006.257.21:21:55.72#ibcon#*after write, iclass 5, count 2 2006.257.21:21:55.72#ibcon#*before return 0, iclass 5, count 2 2006.257.21:21:55.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:55.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:55.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.21:21:55.72#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:55.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:55.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:55.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:55.84#ibcon#enter wrdev, iclass 5, count 0 2006.257.21:21:55.84#ibcon#first serial, iclass 5, count 0 2006.257.21:21:55.84#ibcon#enter sib2, iclass 5, count 0 2006.257.21:21:55.84#ibcon#flushed, iclass 5, count 0 2006.257.21:21:55.84#ibcon#about to write, iclass 5, count 0 2006.257.21:21:55.84#ibcon#wrote, iclass 5, count 0 2006.257.21:21:55.84#ibcon#about to read 3, iclass 5, count 0 2006.257.21:21:55.86#ibcon#read 3, iclass 5, count 0 2006.257.21:21:55.86#ibcon#about to read 4, iclass 5, count 0 2006.257.21:21:55.86#ibcon#read 4, iclass 5, count 0 2006.257.21:21:55.86#ibcon#about to read 5, iclass 5, count 0 2006.257.21:21:55.86#ibcon#read 5, iclass 5, count 0 2006.257.21:21:55.86#ibcon#about to read 6, iclass 5, count 0 2006.257.21:21:55.86#ibcon#read 6, iclass 5, count 0 2006.257.21:21:55.86#ibcon#end of sib2, iclass 5, count 0 2006.257.21:21:55.86#ibcon#*mode == 0, iclass 5, count 0 2006.257.21:21:55.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.21:21:55.86#ibcon#[25=USB\r\n] 2006.257.21:21:55.86#ibcon#*before write, iclass 5, count 0 2006.257.21:21:55.86#ibcon#enter sib2, iclass 5, count 0 2006.257.21:21:55.86#ibcon#flushed, iclass 5, count 0 2006.257.21:21:55.86#ibcon#about to write, iclass 5, count 0 2006.257.21:21:55.86#ibcon#wrote, iclass 5, count 0 2006.257.21:21:55.86#ibcon#about to read 3, iclass 5, count 0 2006.257.21:21:55.89#ibcon#read 3, iclass 5, count 0 2006.257.21:21:55.89#ibcon#about to read 4, iclass 5, count 0 2006.257.21:21:55.89#ibcon#read 4, iclass 5, count 0 2006.257.21:21:55.89#ibcon#about to read 5, iclass 5, count 0 2006.257.21:21:55.89#ibcon#read 5, iclass 5, count 0 2006.257.21:21:55.89#ibcon#about to read 6, iclass 5, count 0 2006.257.21:21:55.89#ibcon#read 6, iclass 5, count 0 2006.257.21:21:55.89#ibcon#end of sib2, iclass 5, count 0 2006.257.21:21:55.89#ibcon#*after write, iclass 5, count 0 2006.257.21:21:55.89#ibcon#*before return 0, iclass 5, count 0 2006.257.21:21:55.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:55.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:55.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.21:21:55.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.21:21:55.89$vck44/valo=8,884.99 2006.257.21:21:55.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.21:21:55.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.21:21:55.89#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:55.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:55.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:55.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:55.89#ibcon#enter wrdev, iclass 7, count 0 2006.257.21:21:55.89#ibcon#first serial, iclass 7, count 0 2006.257.21:21:55.89#ibcon#enter sib2, iclass 7, count 0 2006.257.21:21:55.89#ibcon#flushed, iclass 7, count 0 2006.257.21:21:55.89#ibcon#about to write, iclass 7, count 0 2006.257.21:21:55.89#ibcon#wrote, iclass 7, count 0 2006.257.21:21:55.89#ibcon#about to read 3, iclass 7, count 0 2006.257.21:21:55.91#ibcon#read 3, iclass 7, count 0 2006.257.21:21:55.91#ibcon#about to read 4, iclass 7, count 0 2006.257.21:21:55.91#ibcon#read 4, iclass 7, count 0 2006.257.21:21:55.91#ibcon#about to read 5, iclass 7, count 0 2006.257.21:21:55.91#ibcon#read 5, iclass 7, count 0 2006.257.21:21:55.91#ibcon#about to read 6, iclass 7, count 0 2006.257.21:21:55.91#ibcon#read 6, iclass 7, count 0 2006.257.21:21:55.91#ibcon#end of sib2, iclass 7, count 0 2006.257.21:21:55.91#ibcon#*mode == 0, iclass 7, count 0 2006.257.21:21:55.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.21:21:55.91#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.21:21:55.91#ibcon#*before write, iclass 7, count 0 2006.257.21:21:55.91#ibcon#enter sib2, iclass 7, count 0 2006.257.21:21:55.91#ibcon#flushed, iclass 7, count 0 2006.257.21:21:55.91#ibcon#about to write, iclass 7, count 0 2006.257.21:21:55.91#ibcon#wrote, iclass 7, count 0 2006.257.21:21:55.91#ibcon#about to read 3, iclass 7, count 0 2006.257.21:21:55.95#ibcon#read 3, iclass 7, count 0 2006.257.21:21:55.95#ibcon#about to read 4, iclass 7, count 0 2006.257.21:21:55.95#ibcon#read 4, iclass 7, count 0 2006.257.21:21:55.95#ibcon#about to read 5, iclass 7, count 0 2006.257.21:21:55.95#ibcon#read 5, iclass 7, count 0 2006.257.21:21:55.95#ibcon#about to read 6, iclass 7, count 0 2006.257.21:21:55.95#ibcon#read 6, iclass 7, count 0 2006.257.21:21:55.95#ibcon#end of sib2, iclass 7, count 0 2006.257.21:21:55.95#ibcon#*after write, iclass 7, count 0 2006.257.21:21:55.95#ibcon#*before return 0, iclass 7, count 0 2006.257.21:21:55.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:55.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:55.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.21:21:55.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.21:21:55.95$vck44/va=8,4 2006.257.21:21:55.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.21:21:55.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.21:21:55.95#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:55.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:21:56.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:21:56.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:21:56.01#ibcon#enter wrdev, iclass 11, count 2 2006.257.21:21:56.01#ibcon#first serial, iclass 11, count 2 2006.257.21:21:56.01#ibcon#enter sib2, iclass 11, count 2 2006.257.21:21:56.01#ibcon#flushed, iclass 11, count 2 2006.257.21:21:56.01#ibcon#about to write, iclass 11, count 2 2006.257.21:21:56.01#ibcon#wrote, iclass 11, count 2 2006.257.21:21:56.01#ibcon#about to read 3, iclass 11, count 2 2006.257.21:21:56.03#ibcon#read 3, iclass 11, count 2 2006.257.21:21:56.03#ibcon#about to read 4, iclass 11, count 2 2006.257.21:21:56.03#ibcon#read 4, iclass 11, count 2 2006.257.21:21:56.03#ibcon#about to read 5, iclass 11, count 2 2006.257.21:21:56.03#ibcon#read 5, iclass 11, count 2 2006.257.21:21:56.03#ibcon#about to read 6, iclass 11, count 2 2006.257.21:21:56.03#ibcon#read 6, iclass 11, count 2 2006.257.21:21:56.03#ibcon#end of sib2, iclass 11, count 2 2006.257.21:21:56.03#ibcon#*mode == 0, iclass 11, count 2 2006.257.21:21:56.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.21:21:56.03#ibcon#[25=AT08-04\r\n] 2006.257.21:21:56.03#ibcon#*before write, iclass 11, count 2 2006.257.21:21:56.03#ibcon#enter sib2, iclass 11, count 2 2006.257.21:21:56.03#ibcon#flushed, iclass 11, count 2 2006.257.21:21:56.03#ibcon#about to write, iclass 11, count 2 2006.257.21:21:56.03#ibcon#wrote, iclass 11, count 2 2006.257.21:21:56.03#ibcon#about to read 3, iclass 11, count 2 2006.257.21:21:56.06#ibcon#read 3, iclass 11, count 2 2006.257.21:21:56.06#ibcon#about to read 4, iclass 11, count 2 2006.257.21:21:56.06#ibcon#read 4, iclass 11, count 2 2006.257.21:21:56.06#ibcon#about to read 5, iclass 11, count 2 2006.257.21:21:56.06#ibcon#read 5, iclass 11, count 2 2006.257.21:21:56.06#ibcon#about to read 6, iclass 11, count 2 2006.257.21:21:56.06#ibcon#read 6, iclass 11, count 2 2006.257.21:21:56.06#ibcon#end of sib2, iclass 11, count 2 2006.257.21:21:56.06#ibcon#*after write, iclass 11, count 2 2006.257.21:21:56.06#ibcon#*before return 0, iclass 11, count 2 2006.257.21:21:56.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:21:56.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:21:56.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.21:21:56.06#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:56.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:21:56.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:21:56.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:21:56.18#ibcon#enter wrdev, iclass 11, count 0 2006.257.21:21:56.18#ibcon#first serial, iclass 11, count 0 2006.257.21:21:56.18#ibcon#enter sib2, iclass 11, count 0 2006.257.21:21:56.18#ibcon#flushed, iclass 11, count 0 2006.257.21:21:56.18#ibcon#about to write, iclass 11, count 0 2006.257.21:21:56.18#ibcon#wrote, iclass 11, count 0 2006.257.21:21:56.18#ibcon#about to read 3, iclass 11, count 0 2006.257.21:21:56.20#ibcon#read 3, iclass 11, count 0 2006.257.21:21:56.20#ibcon#about to read 4, iclass 11, count 0 2006.257.21:21:56.20#ibcon#read 4, iclass 11, count 0 2006.257.21:21:56.20#ibcon#about to read 5, iclass 11, count 0 2006.257.21:21:56.20#ibcon#read 5, iclass 11, count 0 2006.257.21:21:56.20#ibcon#about to read 6, iclass 11, count 0 2006.257.21:21:56.20#ibcon#read 6, iclass 11, count 0 2006.257.21:21:56.20#ibcon#end of sib2, iclass 11, count 0 2006.257.21:21:56.20#ibcon#*mode == 0, iclass 11, count 0 2006.257.21:21:56.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.21:21:56.20#ibcon#[25=USB\r\n] 2006.257.21:21:56.20#ibcon#*before write, iclass 11, count 0 2006.257.21:21:56.20#ibcon#enter sib2, iclass 11, count 0 2006.257.21:21:56.20#ibcon#flushed, iclass 11, count 0 2006.257.21:21:56.20#ibcon#about to write, iclass 11, count 0 2006.257.21:21:56.20#ibcon#wrote, iclass 11, count 0 2006.257.21:21:56.20#ibcon#about to read 3, iclass 11, count 0 2006.257.21:21:56.23#ibcon#read 3, iclass 11, count 0 2006.257.21:21:56.23#ibcon#about to read 4, iclass 11, count 0 2006.257.21:21:56.23#ibcon#read 4, iclass 11, count 0 2006.257.21:21:56.23#ibcon#about to read 5, iclass 11, count 0 2006.257.21:21:56.23#ibcon#read 5, iclass 11, count 0 2006.257.21:21:56.23#ibcon#about to read 6, iclass 11, count 0 2006.257.21:21:56.23#ibcon#read 6, iclass 11, count 0 2006.257.21:21:56.23#ibcon#end of sib2, iclass 11, count 0 2006.257.21:21:56.23#ibcon#*after write, iclass 11, count 0 2006.257.21:21:56.23#ibcon#*before return 0, iclass 11, count 0 2006.257.21:21:56.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:21:56.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:21:56.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.21:21:56.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.21:21:56.23$vck44/vblo=1,629.99 2006.257.21:21:56.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.21:21:56.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.21:21:56.23#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:56.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:21:56.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:21:56.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:21:56.23#ibcon#enter wrdev, iclass 13, count 0 2006.257.21:21:56.23#ibcon#first serial, iclass 13, count 0 2006.257.21:21:56.23#ibcon#enter sib2, iclass 13, count 0 2006.257.21:21:56.23#ibcon#flushed, iclass 13, count 0 2006.257.21:21:56.23#ibcon#about to write, iclass 13, count 0 2006.257.21:21:56.23#ibcon#wrote, iclass 13, count 0 2006.257.21:21:56.23#ibcon#about to read 3, iclass 13, count 0 2006.257.21:21:56.25#ibcon#read 3, iclass 13, count 0 2006.257.21:21:56.25#ibcon#about to read 4, iclass 13, count 0 2006.257.21:21:56.25#ibcon#read 4, iclass 13, count 0 2006.257.21:21:56.25#ibcon#about to read 5, iclass 13, count 0 2006.257.21:21:56.25#ibcon#read 5, iclass 13, count 0 2006.257.21:21:56.25#ibcon#about to read 6, iclass 13, count 0 2006.257.21:21:56.25#ibcon#read 6, iclass 13, count 0 2006.257.21:21:56.25#ibcon#end of sib2, iclass 13, count 0 2006.257.21:21:56.25#ibcon#*mode == 0, iclass 13, count 0 2006.257.21:21:56.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.21:21:56.25#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.21:21:56.25#ibcon#*before write, iclass 13, count 0 2006.257.21:21:56.25#ibcon#enter sib2, iclass 13, count 0 2006.257.21:21:56.25#ibcon#flushed, iclass 13, count 0 2006.257.21:21:56.25#ibcon#about to write, iclass 13, count 0 2006.257.21:21:56.25#ibcon#wrote, iclass 13, count 0 2006.257.21:21:56.25#ibcon#about to read 3, iclass 13, count 0 2006.257.21:21:56.29#ibcon#read 3, iclass 13, count 0 2006.257.21:21:56.29#ibcon#about to read 4, iclass 13, count 0 2006.257.21:21:56.29#ibcon#read 4, iclass 13, count 0 2006.257.21:21:56.29#ibcon#about to read 5, iclass 13, count 0 2006.257.21:21:56.29#ibcon#read 5, iclass 13, count 0 2006.257.21:21:56.29#ibcon#about to read 6, iclass 13, count 0 2006.257.21:21:56.29#ibcon#read 6, iclass 13, count 0 2006.257.21:21:56.29#ibcon#end of sib2, iclass 13, count 0 2006.257.21:21:56.29#ibcon#*after write, iclass 13, count 0 2006.257.21:21:56.29#ibcon#*before return 0, iclass 13, count 0 2006.257.21:21:56.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:21:56.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:21:56.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.21:21:56.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.21:21:56.29$vck44/vb=1,4 2006.257.21:21:56.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.21:21:56.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.21:21:56.29#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:56.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:21:56.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:21:56.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:21:56.29#ibcon#enter wrdev, iclass 15, count 2 2006.257.21:21:56.29#ibcon#first serial, iclass 15, count 2 2006.257.21:21:56.29#ibcon#enter sib2, iclass 15, count 2 2006.257.21:21:56.29#ibcon#flushed, iclass 15, count 2 2006.257.21:21:56.29#ibcon#about to write, iclass 15, count 2 2006.257.21:21:56.29#ibcon#wrote, iclass 15, count 2 2006.257.21:21:56.29#ibcon#about to read 3, iclass 15, count 2 2006.257.21:21:56.31#ibcon#read 3, iclass 15, count 2 2006.257.21:21:56.31#ibcon#about to read 4, iclass 15, count 2 2006.257.21:21:56.31#ibcon#read 4, iclass 15, count 2 2006.257.21:21:56.31#ibcon#about to read 5, iclass 15, count 2 2006.257.21:21:56.31#ibcon#read 5, iclass 15, count 2 2006.257.21:21:56.31#ibcon#about to read 6, iclass 15, count 2 2006.257.21:21:56.31#ibcon#read 6, iclass 15, count 2 2006.257.21:21:56.31#ibcon#end of sib2, iclass 15, count 2 2006.257.21:21:56.31#ibcon#*mode == 0, iclass 15, count 2 2006.257.21:21:56.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.21:21:56.31#ibcon#[27=AT01-04\r\n] 2006.257.21:21:56.31#ibcon#*before write, iclass 15, count 2 2006.257.21:21:56.31#ibcon#enter sib2, iclass 15, count 2 2006.257.21:21:56.31#ibcon#flushed, iclass 15, count 2 2006.257.21:21:56.31#ibcon#about to write, iclass 15, count 2 2006.257.21:21:56.31#ibcon#wrote, iclass 15, count 2 2006.257.21:21:56.31#ibcon#about to read 3, iclass 15, count 2 2006.257.21:21:56.34#ibcon#read 3, iclass 15, count 2 2006.257.21:21:56.34#ibcon#about to read 4, iclass 15, count 2 2006.257.21:21:56.34#ibcon#read 4, iclass 15, count 2 2006.257.21:21:56.34#ibcon#about to read 5, iclass 15, count 2 2006.257.21:21:56.34#ibcon#read 5, iclass 15, count 2 2006.257.21:21:56.34#ibcon#about to read 6, iclass 15, count 2 2006.257.21:21:56.34#ibcon#read 6, iclass 15, count 2 2006.257.21:21:56.34#ibcon#end of sib2, iclass 15, count 2 2006.257.21:21:56.34#ibcon#*after write, iclass 15, count 2 2006.257.21:21:56.34#ibcon#*before return 0, iclass 15, count 2 2006.257.21:21:56.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:21:56.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:21:56.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.21:21:56.34#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:56.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:21:56.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:21:56.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:21:56.46#ibcon#enter wrdev, iclass 15, count 0 2006.257.21:21:56.46#ibcon#first serial, iclass 15, count 0 2006.257.21:21:56.46#ibcon#enter sib2, iclass 15, count 0 2006.257.21:21:56.46#ibcon#flushed, iclass 15, count 0 2006.257.21:21:56.46#ibcon#about to write, iclass 15, count 0 2006.257.21:21:56.46#ibcon#wrote, iclass 15, count 0 2006.257.21:21:56.46#ibcon#about to read 3, iclass 15, count 0 2006.257.21:21:56.48#ibcon#read 3, iclass 15, count 0 2006.257.21:21:56.48#ibcon#about to read 4, iclass 15, count 0 2006.257.21:21:56.48#ibcon#read 4, iclass 15, count 0 2006.257.21:21:56.48#ibcon#about to read 5, iclass 15, count 0 2006.257.21:21:56.48#ibcon#read 5, iclass 15, count 0 2006.257.21:21:56.48#ibcon#about to read 6, iclass 15, count 0 2006.257.21:21:56.48#ibcon#read 6, iclass 15, count 0 2006.257.21:21:56.48#ibcon#end of sib2, iclass 15, count 0 2006.257.21:21:56.48#ibcon#*mode == 0, iclass 15, count 0 2006.257.21:21:56.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.21:21:56.48#ibcon#[27=USB\r\n] 2006.257.21:21:56.48#ibcon#*before write, iclass 15, count 0 2006.257.21:21:56.48#ibcon#enter sib2, iclass 15, count 0 2006.257.21:21:56.48#ibcon#flushed, iclass 15, count 0 2006.257.21:21:56.48#ibcon#about to write, iclass 15, count 0 2006.257.21:21:56.48#ibcon#wrote, iclass 15, count 0 2006.257.21:21:56.48#ibcon#about to read 3, iclass 15, count 0 2006.257.21:21:56.51#ibcon#read 3, iclass 15, count 0 2006.257.21:21:56.51#ibcon#about to read 4, iclass 15, count 0 2006.257.21:21:56.51#ibcon#read 4, iclass 15, count 0 2006.257.21:21:56.51#ibcon#about to read 5, iclass 15, count 0 2006.257.21:21:56.51#ibcon#read 5, iclass 15, count 0 2006.257.21:21:56.51#ibcon#about to read 6, iclass 15, count 0 2006.257.21:21:56.51#ibcon#read 6, iclass 15, count 0 2006.257.21:21:56.51#ibcon#end of sib2, iclass 15, count 0 2006.257.21:21:56.51#ibcon#*after write, iclass 15, count 0 2006.257.21:21:56.51#ibcon#*before return 0, iclass 15, count 0 2006.257.21:21:56.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:21:56.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:21:56.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.21:21:56.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.21:21:56.51$vck44/vblo=2,634.99 2006.257.21:21:56.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.21:21:56.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.21:21:56.51#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:56.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:56.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:56.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:56.51#ibcon#enter wrdev, iclass 17, count 0 2006.257.21:21:56.51#ibcon#first serial, iclass 17, count 0 2006.257.21:21:56.51#ibcon#enter sib2, iclass 17, count 0 2006.257.21:21:56.51#ibcon#flushed, iclass 17, count 0 2006.257.21:21:56.51#ibcon#about to write, iclass 17, count 0 2006.257.21:21:56.51#ibcon#wrote, iclass 17, count 0 2006.257.21:21:56.51#ibcon#about to read 3, iclass 17, count 0 2006.257.21:21:56.53#ibcon#read 3, iclass 17, count 0 2006.257.21:21:56.53#ibcon#about to read 4, iclass 17, count 0 2006.257.21:21:56.53#ibcon#read 4, iclass 17, count 0 2006.257.21:21:56.53#ibcon#about to read 5, iclass 17, count 0 2006.257.21:21:56.53#ibcon#read 5, iclass 17, count 0 2006.257.21:21:56.53#ibcon#about to read 6, iclass 17, count 0 2006.257.21:21:56.53#ibcon#read 6, iclass 17, count 0 2006.257.21:21:56.53#ibcon#end of sib2, iclass 17, count 0 2006.257.21:21:56.53#ibcon#*mode == 0, iclass 17, count 0 2006.257.21:21:56.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.21:21:56.53#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.21:21:56.53#ibcon#*before write, iclass 17, count 0 2006.257.21:21:56.53#ibcon#enter sib2, iclass 17, count 0 2006.257.21:21:56.53#ibcon#flushed, iclass 17, count 0 2006.257.21:21:56.53#ibcon#about to write, iclass 17, count 0 2006.257.21:21:56.53#ibcon#wrote, iclass 17, count 0 2006.257.21:21:56.53#ibcon#about to read 3, iclass 17, count 0 2006.257.21:21:56.57#ibcon#read 3, iclass 17, count 0 2006.257.21:21:56.57#ibcon#about to read 4, iclass 17, count 0 2006.257.21:21:56.57#ibcon#read 4, iclass 17, count 0 2006.257.21:21:56.57#ibcon#about to read 5, iclass 17, count 0 2006.257.21:21:56.57#ibcon#read 5, iclass 17, count 0 2006.257.21:21:56.57#ibcon#about to read 6, iclass 17, count 0 2006.257.21:21:56.57#ibcon#read 6, iclass 17, count 0 2006.257.21:21:56.57#ibcon#end of sib2, iclass 17, count 0 2006.257.21:21:56.57#ibcon#*after write, iclass 17, count 0 2006.257.21:21:56.57#ibcon#*before return 0, iclass 17, count 0 2006.257.21:21:56.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:56.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:21:56.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.21:21:56.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.21:21:56.57$vck44/vb=2,5 2006.257.21:21:56.57#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.21:21:56.57#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.21:21:56.57#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:56.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:56.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:56.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:56.63#ibcon#enter wrdev, iclass 19, count 2 2006.257.21:21:56.63#ibcon#first serial, iclass 19, count 2 2006.257.21:21:56.63#ibcon#enter sib2, iclass 19, count 2 2006.257.21:21:56.63#ibcon#flushed, iclass 19, count 2 2006.257.21:21:56.63#ibcon#about to write, iclass 19, count 2 2006.257.21:21:56.63#ibcon#wrote, iclass 19, count 2 2006.257.21:21:56.63#ibcon#about to read 3, iclass 19, count 2 2006.257.21:21:56.65#ibcon#read 3, iclass 19, count 2 2006.257.21:21:56.65#ibcon#about to read 4, iclass 19, count 2 2006.257.21:21:56.65#ibcon#read 4, iclass 19, count 2 2006.257.21:21:56.65#ibcon#about to read 5, iclass 19, count 2 2006.257.21:21:56.65#ibcon#read 5, iclass 19, count 2 2006.257.21:21:56.65#ibcon#about to read 6, iclass 19, count 2 2006.257.21:21:56.65#ibcon#read 6, iclass 19, count 2 2006.257.21:21:56.65#ibcon#end of sib2, iclass 19, count 2 2006.257.21:21:56.65#ibcon#*mode == 0, iclass 19, count 2 2006.257.21:21:56.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.21:21:56.65#ibcon#[27=AT02-05\r\n] 2006.257.21:21:56.65#ibcon#*before write, iclass 19, count 2 2006.257.21:21:56.65#ibcon#enter sib2, iclass 19, count 2 2006.257.21:21:56.65#ibcon#flushed, iclass 19, count 2 2006.257.21:21:56.65#ibcon#about to write, iclass 19, count 2 2006.257.21:21:56.65#ibcon#wrote, iclass 19, count 2 2006.257.21:21:56.65#ibcon#about to read 3, iclass 19, count 2 2006.257.21:21:56.68#ibcon#read 3, iclass 19, count 2 2006.257.21:21:56.68#ibcon#about to read 4, iclass 19, count 2 2006.257.21:21:56.68#ibcon#read 4, iclass 19, count 2 2006.257.21:21:56.68#ibcon#about to read 5, iclass 19, count 2 2006.257.21:21:56.68#ibcon#read 5, iclass 19, count 2 2006.257.21:21:56.68#ibcon#about to read 6, iclass 19, count 2 2006.257.21:21:56.68#ibcon#read 6, iclass 19, count 2 2006.257.21:21:56.68#ibcon#end of sib2, iclass 19, count 2 2006.257.21:21:56.68#ibcon#*after write, iclass 19, count 2 2006.257.21:21:56.68#ibcon#*before return 0, iclass 19, count 2 2006.257.21:21:56.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:56.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:21:56.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.21:21:56.68#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:56.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:56.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:56.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:56.80#ibcon#enter wrdev, iclass 19, count 0 2006.257.21:21:56.80#ibcon#first serial, iclass 19, count 0 2006.257.21:21:56.80#ibcon#enter sib2, iclass 19, count 0 2006.257.21:21:56.80#ibcon#flushed, iclass 19, count 0 2006.257.21:21:56.80#ibcon#about to write, iclass 19, count 0 2006.257.21:21:56.80#ibcon#wrote, iclass 19, count 0 2006.257.21:21:56.80#ibcon#about to read 3, iclass 19, count 0 2006.257.21:21:56.82#ibcon#read 3, iclass 19, count 0 2006.257.21:21:56.82#ibcon#about to read 4, iclass 19, count 0 2006.257.21:21:56.82#ibcon#read 4, iclass 19, count 0 2006.257.21:21:56.82#ibcon#about to read 5, iclass 19, count 0 2006.257.21:21:56.82#ibcon#read 5, iclass 19, count 0 2006.257.21:21:56.82#ibcon#about to read 6, iclass 19, count 0 2006.257.21:21:56.82#ibcon#read 6, iclass 19, count 0 2006.257.21:21:56.82#ibcon#end of sib2, iclass 19, count 0 2006.257.21:21:56.82#ibcon#*mode == 0, iclass 19, count 0 2006.257.21:21:56.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.21:21:56.82#ibcon#[27=USB\r\n] 2006.257.21:21:56.82#ibcon#*before write, iclass 19, count 0 2006.257.21:21:56.82#ibcon#enter sib2, iclass 19, count 0 2006.257.21:21:56.82#ibcon#flushed, iclass 19, count 0 2006.257.21:21:56.82#ibcon#about to write, iclass 19, count 0 2006.257.21:21:56.82#ibcon#wrote, iclass 19, count 0 2006.257.21:21:56.82#ibcon#about to read 3, iclass 19, count 0 2006.257.21:21:56.85#ibcon#read 3, iclass 19, count 0 2006.257.21:21:56.85#ibcon#about to read 4, iclass 19, count 0 2006.257.21:21:56.85#ibcon#read 4, iclass 19, count 0 2006.257.21:21:56.85#ibcon#about to read 5, iclass 19, count 0 2006.257.21:21:56.85#ibcon#read 5, iclass 19, count 0 2006.257.21:21:56.85#ibcon#about to read 6, iclass 19, count 0 2006.257.21:21:56.85#ibcon#read 6, iclass 19, count 0 2006.257.21:21:56.85#ibcon#end of sib2, iclass 19, count 0 2006.257.21:21:56.85#ibcon#*after write, iclass 19, count 0 2006.257.21:21:56.85#ibcon#*before return 0, iclass 19, count 0 2006.257.21:21:56.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:56.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:21:56.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.21:21:56.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.21:21:56.85$vck44/vblo=3,649.99 2006.257.21:21:56.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.21:21:56.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.21:21:56.85#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:56.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:56.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:56.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:56.85#ibcon#enter wrdev, iclass 21, count 0 2006.257.21:21:56.85#ibcon#first serial, iclass 21, count 0 2006.257.21:21:56.85#ibcon#enter sib2, iclass 21, count 0 2006.257.21:21:56.85#ibcon#flushed, iclass 21, count 0 2006.257.21:21:56.85#ibcon#about to write, iclass 21, count 0 2006.257.21:21:56.85#ibcon#wrote, iclass 21, count 0 2006.257.21:21:56.85#ibcon#about to read 3, iclass 21, count 0 2006.257.21:21:56.87#ibcon#read 3, iclass 21, count 0 2006.257.21:21:56.87#ibcon#about to read 4, iclass 21, count 0 2006.257.21:21:56.87#ibcon#read 4, iclass 21, count 0 2006.257.21:21:56.87#ibcon#about to read 5, iclass 21, count 0 2006.257.21:21:56.87#ibcon#read 5, iclass 21, count 0 2006.257.21:21:56.87#ibcon#about to read 6, iclass 21, count 0 2006.257.21:21:56.87#ibcon#read 6, iclass 21, count 0 2006.257.21:21:56.87#ibcon#end of sib2, iclass 21, count 0 2006.257.21:21:56.87#ibcon#*mode == 0, iclass 21, count 0 2006.257.21:21:56.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.21:21:56.87#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.21:21:56.87#ibcon#*before write, iclass 21, count 0 2006.257.21:21:56.87#ibcon#enter sib2, iclass 21, count 0 2006.257.21:21:56.87#ibcon#flushed, iclass 21, count 0 2006.257.21:21:56.87#ibcon#about to write, iclass 21, count 0 2006.257.21:21:56.87#ibcon#wrote, iclass 21, count 0 2006.257.21:21:56.87#ibcon#about to read 3, iclass 21, count 0 2006.257.21:21:56.91#ibcon#read 3, iclass 21, count 0 2006.257.21:21:56.91#ibcon#about to read 4, iclass 21, count 0 2006.257.21:21:56.91#ibcon#read 4, iclass 21, count 0 2006.257.21:21:56.91#ibcon#about to read 5, iclass 21, count 0 2006.257.21:21:56.91#ibcon#read 5, iclass 21, count 0 2006.257.21:21:56.91#ibcon#about to read 6, iclass 21, count 0 2006.257.21:21:56.91#ibcon#read 6, iclass 21, count 0 2006.257.21:21:56.91#ibcon#end of sib2, iclass 21, count 0 2006.257.21:21:56.91#ibcon#*after write, iclass 21, count 0 2006.257.21:21:56.91#ibcon#*before return 0, iclass 21, count 0 2006.257.21:21:56.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:56.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:21:56.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.21:21:56.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.21:21:56.91$vck44/vb=3,4 2006.257.21:21:56.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.21:21:56.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.21:21:56.91#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:56.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:56.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:56.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:56.97#ibcon#enter wrdev, iclass 23, count 2 2006.257.21:21:56.97#ibcon#first serial, iclass 23, count 2 2006.257.21:21:56.97#ibcon#enter sib2, iclass 23, count 2 2006.257.21:21:56.97#ibcon#flushed, iclass 23, count 2 2006.257.21:21:56.97#ibcon#about to write, iclass 23, count 2 2006.257.21:21:56.97#ibcon#wrote, iclass 23, count 2 2006.257.21:21:56.97#ibcon#about to read 3, iclass 23, count 2 2006.257.21:21:56.99#ibcon#read 3, iclass 23, count 2 2006.257.21:21:56.99#ibcon#about to read 4, iclass 23, count 2 2006.257.21:21:56.99#ibcon#read 4, iclass 23, count 2 2006.257.21:21:56.99#ibcon#about to read 5, iclass 23, count 2 2006.257.21:21:56.99#ibcon#read 5, iclass 23, count 2 2006.257.21:21:56.99#ibcon#about to read 6, iclass 23, count 2 2006.257.21:21:56.99#ibcon#read 6, iclass 23, count 2 2006.257.21:21:56.99#ibcon#end of sib2, iclass 23, count 2 2006.257.21:21:56.99#ibcon#*mode == 0, iclass 23, count 2 2006.257.21:21:56.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.21:21:56.99#ibcon#[27=AT03-04\r\n] 2006.257.21:21:56.99#ibcon#*before write, iclass 23, count 2 2006.257.21:21:56.99#ibcon#enter sib2, iclass 23, count 2 2006.257.21:21:56.99#ibcon#flushed, iclass 23, count 2 2006.257.21:21:56.99#ibcon#about to write, iclass 23, count 2 2006.257.21:21:56.99#ibcon#wrote, iclass 23, count 2 2006.257.21:21:56.99#ibcon#about to read 3, iclass 23, count 2 2006.257.21:21:57.02#ibcon#read 3, iclass 23, count 2 2006.257.21:21:57.02#ibcon#about to read 4, iclass 23, count 2 2006.257.21:21:57.02#ibcon#read 4, iclass 23, count 2 2006.257.21:21:57.02#ibcon#about to read 5, iclass 23, count 2 2006.257.21:21:57.02#ibcon#read 5, iclass 23, count 2 2006.257.21:21:57.02#ibcon#about to read 6, iclass 23, count 2 2006.257.21:21:57.02#ibcon#read 6, iclass 23, count 2 2006.257.21:21:57.02#ibcon#end of sib2, iclass 23, count 2 2006.257.21:21:57.02#ibcon#*after write, iclass 23, count 2 2006.257.21:21:57.02#ibcon#*before return 0, iclass 23, count 2 2006.257.21:21:57.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:57.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:21:57.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.21:21:57.02#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:57.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:57.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:57.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:57.14#ibcon#enter wrdev, iclass 23, count 0 2006.257.21:21:57.14#ibcon#first serial, iclass 23, count 0 2006.257.21:21:57.14#ibcon#enter sib2, iclass 23, count 0 2006.257.21:21:57.14#ibcon#flushed, iclass 23, count 0 2006.257.21:21:57.14#ibcon#about to write, iclass 23, count 0 2006.257.21:21:57.14#ibcon#wrote, iclass 23, count 0 2006.257.21:21:57.14#ibcon#about to read 3, iclass 23, count 0 2006.257.21:21:57.16#ibcon#read 3, iclass 23, count 0 2006.257.21:21:57.16#ibcon#about to read 4, iclass 23, count 0 2006.257.21:21:57.16#ibcon#read 4, iclass 23, count 0 2006.257.21:21:57.16#ibcon#about to read 5, iclass 23, count 0 2006.257.21:21:57.16#ibcon#read 5, iclass 23, count 0 2006.257.21:21:57.16#ibcon#about to read 6, iclass 23, count 0 2006.257.21:21:57.16#ibcon#read 6, iclass 23, count 0 2006.257.21:21:57.16#ibcon#end of sib2, iclass 23, count 0 2006.257.21:21:57.16#ibcon#*mode == 0, iclass 23, count 0 2006.257.21:21:57.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.21:21:57.16#ibcon#[27=USB\r\n] 2006.257.21:21:57.16#ibcon#*before write, iclass 23, count 0 2006.257.21:21:57.16#ibcon#enter sib2, iclass 23, count 0 2006.257.21:21:57.16#ibcon#flushed, iclass 23, count 0 2006.257.21:21:57.16#ibcon#about to write, iclass 23, count 0 2006.257.21:21:57.16#ibcon#wrote, iclass 23, count 0 2006.257.21:21:57.16#ibcon#about to read 3, iclass 23, count 0 2006.257.21:21:57.19#ibcon#read 3, iclass 23, count 0 2006.257.21:21:57.19#ibcon#about to read 4, iclass 23, count 0 2006.257.21:21:57.19#ibcon#read 4, iclass 23, count 0 2006.257.21:21:57.19#ibcon#about to read 5, iclass 23, count 0 2006.257.21:21:57.19#ibcon#read 5, iclass 23, count 0 2006.257.21:21:57.19#ibcon#about to read 6, iclass 23, count 0 2006.257.21:21:57.19#ibcon#read 6, iclass 23, count 0 2006.257.21:21:57.19#ibcon#end of sib2, iclass 23, count 0 2006.257.21:21:57.19#ibcon#*after write, iclass 23, count 0 2006.257.21:21:57.19#ibcon#*before return 0, iclass 23, count 0 2006.257.21:21:57.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:57.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:21:57.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.21:21:57.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.21:21:57.19$vck44/vblo=4,679.99 2006.257.21:21:57.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.21:21:57.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.21:21:57.19#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:57.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:57.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:57.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:57.19#ibcon#enter wrdev, iclass 25, count 0 2006.257.21:21:57.19#ibcon#first serial, iclass 25, count 0 2006.257.21:21:57.19#ibcon#enter sib2, iclass 25, count 0 2006.257.21:21:57.19#ibcon#flushed, iclass 25, count 0 2006.257.21:21:57.19#ibcon#about to write, iclass 25, count 0 2006.257.21:21:57.19#ibcon#wrote, iclass 25, count 0 2006.257.21:21:57.19#ibcon#about to read 3, iclass 25, count 0 2006.257.21:21:57.21#ibcon#read 3, iclass 25, count 0 2006.257.21:21:57.21#ibcon#about to read 4, iclass 25, count 0 2006.257.21:21:57.21#ibcon#read 4, iclass 25, count 0 2006.257.21:21:57.21#ibcon#about to read 5, iclass 25, count 0 2006.257.21:21:57.21#ibcon#read 5, iclass 25, count 0 2006.257.21:21:57.21#ibcon#about to read 6, iclass 25, count 0 2006.257.21:21:57.21#ibcon#read 6, iclass 25, count 0 2006.257.21:21:57.21#ibcon#end of sib2, iclass 25, count 0 2006.257.21:21:57.21#ibcon#*mode == 0, iclass 25, count 0 2006.257.21:21:57.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.21:21:57.21#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.21:21:57.21#ibcon#*before write, iclass 25, count 0 2006.257.21:21:57.21#ibcon#enter sib2, iclass 25, count 0 2006.257.21:21:57.21#ibcon#flushed, iclass 25, count 0 2006.257.21:21:57.21#ibcon#about to write, iclass 25, count 0 2006.257.21:21:57.21#ibcon#wrote, iclass 25, count 0 2006.257.21:21:57.21#ibcon#about to read 3, iclass 25, count 0 2006.257.21:21:57.25#ibcon#read 3, iclass 25, count 0 2006.257.21:21:57.25#ibcon#about to read 4, iclass 25, count 0 2006.257.21:21:57.25#ibcon#read 4, iclass 25, count 0 2006.257.21:21:57.25#ibcon#about to read 5, iclass 25, count 0 2006.257.21:21:57.25#ibcon#read 5, iclass 25, count 0 2006.257.21:21:57.25#ibcon#about to read 6, iclass 25, count 0 2006.257.21:21:57.25#ibcon#read 6, iclass 25, count 0 2006.257.21:21:57.25#ibcon#end of sib2, iclass 25, count 0 2006.257.21:21:57.25#ibcon#*after write, iclass 25, count 0 2006.257.21:21:57.25#ibcon#*before return 0, iclass 25, count 0 2006.257.21:21:57.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:57.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:21:57.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.21:21:57.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.21:21:57.25$vck44/vb=4,5 2006.257.21:21:57.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.21:21:57.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.21:21:57.25#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:57.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:57.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:57.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:57.31#ibcon#enter wrdev, iclass 27, count 2 2006.257.21:21:57.31#ibcon#first serial, iclass 27, count 2 2006.257.21:21:57.31#ibcon#enter sib2, iclass 27, count 2 2006.257.21:21:57.31#ibcon#flushed, iclass 27, count 2 2006.257.21:21:57.31#ibcon#about to write, iclass 27, count 2 2006.257.21:21:57.31#ibcon#wrote, iclass 27, count 2 2006.257.21:21:57.31#ibcon#about to read 3, iclass 27, count 2 2006.257.21:21:57.33#ibcon#read 3, iclass 27, count 2 2006.257.21:21:57.33#ibcon#about to read 4, iclass 27, count 2 2006.257.21:21:57.33#ibcon#read 4, iclass 27, count 2 2006.257.21:21:57.33#ibcon#about to read 5, iclass 27, count 2 2006.257.21:21:57.33#ibcon#read 5, iclass 27, count 2 2006.257.21:21:57.33#ibcon#about to read 6, iclass 27, count 2 2006.257.21:21:57.33#ibcon#read 6, iclass 27, count 2 2006.257.21:21:57.33#ibcon#end of sib2, iclass 27, count 2 2006.257.21:21:57.33#ibcon#*mode == 0, iclass 27, count 2 2006.257.21:21:57.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.21:21:57.33#ibcon#[27=AT04-05\r\n] 2006.257.21:21:57.33#ibcon#*before write, iclass 27, count 2 2006.257.21:21:57.33#ibcon#enter sib2, iclass 27, count 2 2006.257.21:21:57.33#ibcon#flushed, iclass 27, count 2 2006.257.21:21:57.33#ibcon#about to write, iclass 27, count 2 2006.257.21:21:57.33#ibcon#wrote, iclass 27, count 2 2006.257.21:21:57.33#ibcon#about to read 3, iclass 27, count 2 2006.257.21:21:57.36#ibcon#read 3, iclass 27, count 2 2006.257.21:21:57.36#ibcon#about to read 4, iclass 27, count 2 2006.257.21:21:57.36#ibcon#read 4, iclass 27, count 2 2006.257.21:21:57.36#ibcon#about to read 5, iclass 27, count 2 2006.257.21:21:57.36#ibcon#read 5, iclass 27, count 2 2006.257.21:21:57.36#ibcon#about to read 6, iclass 27, count 2 2006.257.21:21:57.36#ibcon#read 6, iclass 27, count 2 2006.257.21:21:57.36#ibcon#end of sib2, iclass 27, count 2 2006.257.21:21:57.36#ibcon#*after write, iclass 27, count 2 2006.257.21:21:57.36#ibcon#*before return 0, iclass 27, count 2 2006.257.21:21:57.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:57.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:21:57.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.21:21:57.36#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:57.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:57.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:57.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:57.48#ibcon#enter wrdev, iclass 27, count 0 2006.257.21:21:57.48#ibcon#first serial, iclass 27, count 0 2006.257.21:21:57.48#ibcon#enter sib2, iclass 27, count 0 2006.257.21:21:57.48#ibcon#flushed, iclass 27, count 0 2006.257.21:21:57.48#ibcon#about to write, iclass 27, count 0 2006.257.21:21:57.48#ibcon#wrote, iclass 27, count 0 2006.257.21:21:57.48#ibcon#about to read 3, iclass 27, count 0 2006.257.21:21:57.50#ibcon#read 3, iclass 27, count 0 2006.257.21:21:57.50#ibcon#about to read 4, iclass 27, count 0 2006.257.21:21:57.50#ibcon#read 4, iclass 27, count 0 2006.257.21:21:57.50#ibcon#about to read 5, iclass 27, count 0 2006.257.21:21:57.50#ibcon#read 5, iclass 27, count 0 2006.257.21:21:57.50#ibcon#about to read 6, iclass 27, count 0 2006.257.21:21:57.50#ibcon#read 6, iclass 27, count 0 2006.257.21:21:57.50#ibcon#end of sib2, iclass 27, count 0 2006.257.21:21:57.50#ibcon#*mode == 0, iclass 27, count 0 2006.257.21:21:57.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.21:21:57.50#ibcon#[27=USB\r\n] 2006.257.21:21:57.50#ibcon#*before write, iclass 27, count 0 2006.257.21:21:57.50#ibcon#enter sib2, iclass 27, count 0 2006.257.21:21:57.50#ibcon#flushed, iclass 27, count 0 2006.257.21:21:57.50#ibcon#about to write, iclass 27, count 0 2006.257.21:21:57.50#ibcon#wrote, iclass 27, count 0 2006.257.21:21:57.50#ibcon#about to read 3, iclass 27, count 0 2006.257.21:21:57.53#ibcon#read 3, iclass 27, count 0 2006.257.21:21:57.53#ibcon#about to read 4, iclass 27, count 0 2006.257.21:21:57.53#ibcon#read 4, iclass 27, count 0 2006.257.21:21:57.53#ibcon#about to read 5, iclass 27, count 0 2006.257.21:21:57.53#ibcon#read 5, iclass 27, count 0 2006.257.21:21:57.53#ibcon#about to read 6, iclass 27, count 0 2006.257.21:21:57.53#ibcon#read 6, iclass 27, count 0 2006.257.21:21:57.53#ibcon#end of sib2, iclass 27, count 0 2006.257.21:21:57.53#ibcon#*after write, iclass 27, count 0 2006.257.21:21:57.53#ibcon#*before return 0, iclass 27, count 0 2006.257.21:21:57.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:57.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:21:57.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.21:21:57.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.21:21:57.53$vck44/vblo=5,709.99 2006.257.21:21:57.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.21:21:57.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.21:21:57.53#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:57.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:57.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:57.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:57.53#ibcon#enter wrdev, iclass 29, count 0 2006.257.21:21:57.53#ibcon#first serial, iclass 29, count 0 2006.257.21:21:57.53#ibcon#enter sib2, iclass 29, count 0 2006.257.21:21:57.53#ibcon#flushed, iclass 29, count 0 2006.257.21:21:57.53#ibcon#about to write, iclass 29, count 0 2006.257.21:21:57.53#ibcon#wrote, iclass 29, count 0 2006.257.21:21:57.53#ibcon#about to read 3, iclass 29, count 0 2006.257.21:21:57.55#ibcon#read 3, iclass 29, count 0 2006.257.21:21:57.55#ibcon#about to read 4, iclass 29, count 0 2006.257.21:21:57.55#ibcon#read 4, iclass 29, count 0 2006.257.21:21:57.55#ibcon#about to read 5, iclass 29, count 0 2006.257.21:21:57.55#ibcon#read 5, iclass 29, count 0 2006.257.21:21:57.55#ibcon#about to read 6, iclass 29, count 0 2006.257.21:21:57.55#ibcon#read 6, iclass 29, count 0 2006.257.21:21:57.55#ibcon#end of sib2, iclass 29, count 0 2006.257.21:21:57.55#ibcon#*mode == 0, iclass 29, count 0 2006.257.21:21:57.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.21:21:57.55#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.21:21:57.55#ibcon#*before write, iclass 29, count 0 2006.257.21:21:57.55#ibcon#enter sib2, iclass 29, count 0 2006.257.21:21:57.55#ibcon#flushed, iclass 29, count 0 2006.257.21:21:57.55#ibcon#about to write, iclass 29, count 0 2006.257.21:21:57.55#ibcon#wrote, iclass 29, count 0 2006.257.21:21:57.55#ibcon#about to read 3, iclass 29, count 0 2006.257.21:21:57.59#ibcon#read 3, iclass 29, count 0 2006.257.21:21:57.59#ibcon#about to read 4, iclass 29, count 0 2006.257.21:21:57.59#ibcon#read 4, iclass 29, count 0 2006.257.21:21:57.59#ibcon#about to read 5, iclass 29, count 0 2006.257.21:21:57.59#ibcon#read 5, iclass 29, count 0 2006.257.21:21:57.59#ibcon#about to read 6, iclass 29, count 0 2006.257.21:21:57.59#ibcon#read 6, iclass 29, count 0 2006.257.21:21:57.59#ibcon#end of sib2, iclass 29, count 0 2006.257.21:21:57.59#ibcon#*after write, iclass 29, count 0 2006.257.21:21:57.59#ibcon#*before return 0, iclass 29, count 0 2006.257.21:21:57.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:57.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:21:57.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.21:21:57.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.21:21:57.59$vck44/vb=5,4 2006.257.21:21:57.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.21:21:57.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.21:21:57.59#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:57.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:57.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:57.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:57.65#ibcon#enter wrdev, iclass 31, count 2 2006.257.21:21:57.65#ibcon#first serial, iclass 31, count 2 2006.257.21:21:57.65#ibcon#enter sib2, iclass 31, count 2 2006.257.21:21:57.65#ibcon#flushed, iclass 31, count 2 2006.257.21:21:57.65#ibcon#about to write, iclass 31, count 2 2006.257.21:21:57.65#ibcon#wrote, iclass 31, count 2 2006.257.21:21:57.65#ibcon#about to read 3, iclass 31, count 2 2006.257.21:21:57.67#ibcon#read 3, iclass 31, count 2 2006.257.21:21:57.67#ibcon#about to read 4, iclass 31, count 2 2006.257.21:21:57.67#ibcon#read 4, iclass 31, count 2 2006.257.21:21:57.67#ibcon#about to read 5, iclass 31, count 2 2006.257.21:21:57.67#ibcon#read 5, iclass 31, count 2 2006.257.21:21:57.67#ibcon#about to read 6, iclass 31, count 2 2006.257.21:21:57.67#ibcon#read 6, iclass 31, count 2 2006.257.21:21:57.67#ibcon#end of sib2, iclass 31, count 2 2006.257.21:21:57.67#ibcon#*mode == 0, iclass 31, count 2 2006.257.21:21:57.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.21:21:57.67#ibcon#[27=AT05-04\r\n] 2006.257.21:21:57.67#ibcon#*before write, iclass 31, count 2 2006.257.21:21:57.67#ibcon#enter sib2, iclass 31, count 2 2006.257.21:21:57.67#ibcon#flushed, iclass 31, count 2 2006.257.21:21:57.67#ibcon#about to write, iclass 31, count 2 2006.257.21:21:57.67#ibcon#wrote, iclass 31, count 2 2006.257.21:21:57.67#ibcon#about to read 3, iclass 31, count 2 2006.257.21:21:57.70#ibcon#read 3, iclass 31, count 2 2006.257.21:21:57.70#ibcon#about to read 4, iclass 31, count 2 2006.257.21:21:57.70#ibcon#read 4, iclass 31, count 2 2006.257.21:21:57.70#ibcon#about to read 5, iclass 31, count 2 2006.257.21:21:57.70#ibcon#read 5, iclass 31, count 2 2006.257.21:21:57.70#ibcon#about to read 6, iclass 31, count 2 2006.257.21:21:57.70#ibcon#read 6, iclass 31, count 2 2006.257.21:21:57.70#ibcon#end of sib2, iclass 31, count 2 2006.257.21:21:57.70#ibcon#*after write, iclass 31, count 2 2006.257.21:21:57.70#ibcon#*before return 0, iclass 31, count 2 2006.257.21:21:57.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:57.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:21:57.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.21:21:57.70#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:57.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:57.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:57.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:57.82#ibcon#enter wrdev, iclass 31, count 0 2006.257.21:21:57.82#ibcon#first serial, iclass 31, count 0 2006.257.21:21:57.82#ibcon#enter sib2, iclass 31, count 0 2006.257.21:21:57.82#ibcon#flushed, iclass 31, count 0 2006.257.21:21:57.82#ibcon#about to write, iclass 31, count 0 2006.257.21:21:57.82#ibcon#wrote, iclass 31, count 0 2006.257.21:21:57.82#ibcon#about to read 3, iclass 31, count 0 2006.257.21:21:57.84#ibcon#read 3, iclass 31, count 0 2006.257.21:21:57.84#ibcon#about to read 4, iclass 31, count 0 2006.257.21:21:57.84#ibcon#read 4, iclass 31, count 0 2006.257.21:21:57.84#ibcon#about to read 5, iclass 31, count 0 2006.257.21:21:57.84#ibcon#read 5, iclass 31, count 0 2006.257.21:21:57.84#ibcon#about to read 6, iclass 31, count 0 2006.257.21:21:57.84#ibcon#read 6, iclass 31, count 0 2006.257.21:21:57.84#ibcon#end of sib2, iclass 31, count 0 2006.257.21:21:57.84#ibcon#*mode == 0, iclass 31, count 0 2006.257.21:21:57.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.21:21:57.84#ibcon#[27=USB\r\n] 2006.257.21:21:57.84#ibcon#*before write, iclass 31, count 0 2006.257.21:21:57.84#ibcon#enter sib2, iclass 31, count 0 2006.257.21:21:57.84#ibcon#flushed, iclass 31, count 0 2006.257.21:21:57.84#ibcon#about to write, iclass 31, count 0 2006.257.21:21:57.84#ibcon#wrote, iclass 31, count 0 2006.257.21:21:57.84#ibcon#about to read 3, iclass 31, count 0 2006.257.21:21:57.87#ibcon#read 3, iclass 31, count 0 2006.257.21:21:57.87#ibcon#about to read 4, iclass 31, count 0 2006.257.21:21:57.87#ibcon#read 4, iclass 31, count 0 2006.257.21:21:57.87#ibcon#about to read 5, iclass 31, count 0 2006.257.21:21:57.87#ibcon#read 5, iclass 31, count 0 2006.257.21:21:57.87#ibcon#about to read 6, iclass 31, count 0 2006.257.21:21:57.87#ibcon#read 6, iclass 31, count 0 2006.257.21:21:57.87#ibcon#end of sib2, iclass 31, count 0 2006.257.21:21:57.87#ibcon#*after write, iclass 31, count 0 2006.257.21:21:57.87#ibcon#*before return 0, iclass 31, count 0 2006.257.21:21:57.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:57.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:21:57.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.21:21:57.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.21:21:57.87$vck44/vblo=6,719.99 2006.257.21:21:57.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.21:21:57.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.21:21:57.87#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:57.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:57.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:57.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:57.87#ibcon#enter wrdev, iclass 33, count 0 2006.257.21:21:57.87#ibcon#first serial, iclass 33, count 0 2006.257.21:21:57.87#ibcon#enter sib2, iclass 33, count 0 2006.257.21:21:57.87#ibcon#flushed, iclass 33, count 0 2006.257.21:21:57.87#ibcon#about to write, iclass 33, count 0 2006.257.21:21:57.87#ibcon#wrote, iclass 33, count 0 2006.257.21:21:57.87#ibcon#about to read 3, iclass 33, count 0 2006.257.21:21:57.89#ibcon#read 3, iclass 33, count 0 2006.257.21:21:57.89#ibcon#about to read 4, iclass 33, count 0 2006.257.21:21:57.89#ibcon#read 4, iclass 33, count 0 2006.257.21:21:57.89#ibcon#about to read 5, iclass 33, count 0 2006.257.21:21:57.89#ibcon#read 5, iclass 33, count 0 2006.257.21:21:57.89#ibcon#about to read 6, iclass 33, count 0 2006.257.21:21:57.89#ibcon#read 6, iclass 33, count 0 2006.257.21:21:57.89#ibcon#end of sib2, iclass 33, count 0 2006.257.21:21:57.89#ibcon#*mode == 0, iclass 33, count 0 2006.257.21:21:57.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.21:21:57.89#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.21:21:57.89#ibcon#*before write, iclass 33, count 0 2006.257.21:21:57.89#ibcon#enter sib2, iclass 33, count 0 2006.257.21:21:57.89#ibcon#flushed, iclass 33, count 0 2006.257.21:21:57.89#ibcon#about to write, iclass 33, count 0 2006.257.21:21:57.89#ibcon#wrote, iclass 33, count 0 2006.257.21:21:57.89#ibcon#about to read 3, iclass 33, count 0 2006.257.21:21:57.93#ibcon#read 3, iclass 33, count 0 2006.257.21:21:57.93#ibcon#about to read 4, iclass 33, count 0 2006.257.21:21:57.93#ibcon#read 4, iclass 33, count 0 2006.257.21:21:57.93#ibcon#about to read 5, iclass 33, count 0 2006.257.21:21:57.93#ibcon#read 5, iclass 33, count 0 2006.257.21:21:57.93#ibcon#about to read 6, iclass 33, count 0 2006.257.21:21:57.93#ibcon#read 6, iclass 33, count 0 2006.257.21:21:57.93#ibcon#end of sib2, iclass 33, count 0 2006.257.21:21:57.93#ibcon#*after write, iclass 33, count 0 2006.257.21:21:57.93#ibcon#*before return 0, iclass 33, count 0 2006.257.21:21:57.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:57.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:21:57.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.21:21:57.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.21:21:57.93$vck44/vb=6,4 2006.257.21:21:57.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.21:21:57.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.21:21:57.93#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:57.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:57.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:57.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:57.99#ibcon#enter wrdev, iclass 35, count 2 2006.257.21:21:57.99#ibcon#first serial, iclass 35, count 2 2006.257.21:21:57.99#ibcon#enter sib2, iclass 35, count 2 2006.257.21:21:57.99#ibcon#flushed, iclass 35, count 2 2006.257.21:21:57.99#ibcon#about to write, iclass 35, count 2 2006.257.21:21:57.99#ibcon#wrote, iclass 35, count 2 2006.257.21:21:57.99#ibcon#about to read 3, iclass 35, count 2 2006.257.21:21:58.01#ibcon#read 3, iclass 35, count 2 2006.257.21:21:58.01#ibcon#about to read 4, iclass 35, count 2 2006.257.21:21:58.01#ibcon#read 4, iclass 35, count 2 2006.257.21:21:58.01#ibcon#about to read 5, iclass 35, count 2 2006.257.21:21:58.01#ibcon#read 5, iclass 35, count 2 2006.257.21:21:58.01#ibcon#about to read 6, iclass 35, count 2 2006.257.21:21:58.01#ibcon#read 6, iclass 35, count 2 2006.257.21:21:58.01#ibcon#end of sib2, iclass 35, count 2 2006.257.21:21:58.01#ibcon#*mode == 0, iclass 35, count 2 2006.257.21:21:58.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.21:21:58.01#ibcon#[27=AT06-04\r\n] 2006.257.21:21:58.01#ibcon#*before write, iclass 35, count 2 2006.257.21:21:58.01#ibcon#enter sib2, iclass 35, count 2 2006.257.21:21:58.01#ibcon#flushed, iclass 35, count 2 2006.257.21:21:58.01#ibcon#about to write, iclass 35, count 2 2006.257.21:21:58.01#ibcon#wrote, iclass 35, count 2 2006.257.21:21:58.01#ibcon#about to read 3, iclass 35, count 2 2006.257.21:21:58.04#ibcon#read 3, iclass 35, count 2 2006.257.21:21:58.04#ibcon#about to read 4, iclass 35, count 2 2006.257.21:21:58.04#ibcon#read 4, iclass 35, count 2 2006.257.21:21:58.04#ibcon#about to read 5, iclass 35, count 2 2006.257.21:21:58.04#ibcon#read 5, iclass 35, count 2 2006.257.21:21:58.04#ibcon#about to read 6, iclass 35, count 2 2006.257.21:21:58.04#ibcon#read 6, iclass 35, count 2 2006.257.21:21:58.04#ibcon#end of sib2, iclass 35, count 2 2006.257.21:21:58.04#ibcon#*after write, iclass 35, count 2 2006.257.21:21:58.04#ibcon#*before return 0, iclass 35, count 2 2006.257.21:21:58.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:58.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:21:58.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.21:21:58.04#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:58.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:58.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:58.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:58.16#ibcon#enter wrdev, iclass 35, count 0 2006.257.21:21:58.16#ibcon#first serial, iclass 35, count 0 2006.257.21:21:58.16#ibcon#enter sib2, iclass 35, count 0 2006.257.21:21:58.16#ibcon#flushed, iclass 35, count 0 2006.257.21:21:58.16#ibcon#about to write, iclass 35, count 0 2006.257.21:21:58.16#ibcon#wrote, iclass 35, count 0 2006.257.21:21:58.16#ibcon#about to read 3, iclass 35, count 0 2006.257.21:21:58.18#ibcon#read 3, iclass 35, count 0 2006.257.21:21:58.18#ibcon#about to read 4, iclass 35, count 0 2006.257.21:21:58.18#ibcon#read 4, iclass 35, count 0 2006.257.21:21:58.18#ibcon#about to read 5, iclass 35, count 0 2006.257.21:21:58.18#ibcon#read 5, iclass 35, count 0 2006.257.21:21:58.18#ibcon#about to read 6, iclass 35, count 0 2006.257.21:21:58.18#ibcon#read 6, iclass 35, count 0 2006.257.21:21:58.18#ibcon#end of sib2, iclass 35, count 0 2006.257.21:21:58.18#ibcon#*mode == 0, iclass 35, count 0 2006.257.21:21:58.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.21:21:58.18#ibcon#[27=USB\r\n] 2006.257.21:21:58.18#ibcon#*before write, iclass 35, count 0 2006.257.21:21:58.18#ibcon#enter sib2, iclass 35, count 0 2006.257.21:21:58.18#ibcon#flushed, iclass 35, count 0 2006.257.21:21:58.18#ibcon#about to write, iclass 35, count 0 2006.257.21:21:58.18#ibcon#wrote, iclass 35, count 0 2006.257.21:21:58.18#ibcon#about to read 3, iclass 35, count 0 2006.257.21:21:58.21#ibcon#read 3, iclass 35, count 0 2006.257.21:21:58.21#ibcon#about to read 4, iclass 35, count 0 2006.257.21:21:58.21#ibcon#read 4, iclass 35, count 0 2006.257.21:21:58.21#ibcon#about to read 5, iclass 35, count 0 2006.257.21:21:58.21#ibcon#read 5, iclass 35, count 0 2006.257.21:21:58.21#ibcon#about to read 6, iclass 35, count 0 2006.257.21:21:58.21#ibcon#read 6, iclass 35, count 0 2006.257.21:21:58.21#ibcon#end of sib2, iclass 35, count 0 2006.257.21:21:58.21#ibcon#*after write, iclass 35, count 0 2006.257.21:21:58.21#ibcon#*before return 0, iclass 35, count 0 2006.257.21:21:58.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:58.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:21:58.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.21:21:58.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.21:21:58.21$vck44/vblo=7,734.99 2006.257.21:21:58.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.21:21:58.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.21:21:58.21#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:58.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:58.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:58.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:58.21#ibcon#enter wrdev, iclass 37, count 0 2006.257.21:21:58.21#ibcon#first serial, iclass 37, count 0 2006.257.21:21:58.21#ibcon#enter sib2, iclass 37, count 0 2006.257.21:21:58.21#ibcon#flushed, iclass 37, count 0 2006.257.21:21:58.21#ibcon#about to write, iclass 37, count 0 2006.257.21:21:58.21#ibcon#wrote, iclass 37, count 0 2006.257.21:21:58.21#ibcon#about to read 3, iclass 37, count 0 2006.257.21:21:58.23#ibcon#read 3, iclass 37, count 0 2006.257.21:21:58.23#ibcon#about to read 4, iclass 37, count 0 2006.257.21:21:58.23#ibcon#read 4, iclass 37, count 0 2006.257.21:21:58.23#ibcon#about to read 5, iclass 37, count 0 2006.257.21:21:58.23#ibcon#read 5, iclass 37, count 0 2006.257.21:21:58.23#ibcon#about to read 6, iclass 37, count 0 2006.257.21:21:58.23#ibcon#read 6, iclass 37, count 0 2006.257.21:21:58.23#ibcon#end of sib2, iclass 37, count 0 2006.257.21:21:58.23#ibcon#*mode == 0, iclass 37, count 0 2006.257.21:21:58.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.21:21:58.23#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.21:21:58.23#ibcon#*before write, iclass 37, count 0 2006.257.21:21:58.23#ibcon#enter sib2, iclass 37, count 0 2006.257.21:21:58.23#ibcon#flushed, iclass 37, count 0 2006.257.21:21:58.23#ibcon#about to write, iclass 37, count 0 2006.257.21:21:58.23#ibcon#wrote, iclass 37, count 0 2006.257.21:21:58.23#ibcon#about to read 3, iclass 37, count 0 2006.257.21:21:58.27#ibcon#read 3, iclass 37, count 0 2006.257.21:21:58.27#ibcon#about to read 4, iclass 37, count 0 2006.257.21:21:58.27#ibcon#read 4, iclass 37, count 0 2006.257.21:21:58.27#ibcon#about to read 5, iclass 37, count 0 2006.257.21:21:58.27#ibcon#read 5, iclass 37, count 0 2006.257.21:21:58.27#ibcon#about to read 6, iclass 37, count 0 2006.257.21:21:58.27#ibcon#read 6, iclass 37, count 0 2006.257.21:21:58.27#ibcon#end of sib2, iclass 37, count 0 2006.257.21:21:58.27#ibcon#*after write, iclass 37, count 0 2006.257.21:21:58.27#ibcon#*before return 0, iclass 37, count 0 2006.257.21:21:58.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:58.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:21:58.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.21:21:58.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.21:21:58.27$vck44/vb=7,4 2006.257.21:21:58.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.21:21:58.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.21:21:58.27#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:58.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:58.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:58.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:58.33#ibcon#enter wrdev, iclass 39, count 2 2006.257.21:21:58.33#ibcon#first serial, iclass 39, count 2 2006.257.21:21:58.33#ibcon#enter sib2, iclass 39, count 2 2006.257.21:21:58.33#ibcon#flushed, iclass 39, count 2 2006.257.21:21:58.33#ibcon#about to write, iclass 39, count 2 2006.257.21:21:58.33#ibcon#wrote, iclass 39, count 2 2006.257.21:21:58.33#ibcon#about to read 3, iclass 39, count 2 2006.257.21:21:58.35#ibcon#read 3, iclass 39, count 2 2006.257.21:21:58.35#ibcon#about to read 4, iclass 39, count 2 2006.257.21:21:58.35#ibcon#read 4, iclass 39, count 2 2006.257.21:21:58.35#ibcon#about to read 5, iclass 39, count 2 2006.257.21:21:58.35#ibcon#read 5, iclass 39, count 2 2006.257.21:21:58.35#ibcon#about to read 6, iclass 39, count 2 2006.257.21:21:58.35#ibcon#read 6, iclass 39, count 2 2006.257.21:21:58.35#ibcon#end of sib2, iclass 39, count 2 2006.257.21:21:58.35#ibcon#*mode == 0, iclass 39, count 2 2006.257.21:21:58.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.21:21:58.35#ibcon#[27=AT07-04\r\n] 2006.257.21:21:58.35#ibcon#*before write, iclass 39, count 2 2006.257.21:21:58.35#ibcon#enter sib2, iclass 39, count 2 2006.257.21:21:58.35#ibcon#flushed, iclass 39, count 2 2006.257.21:21:58.35#ibcon#about to write, iclass 39, count 2 2006.257.21:21:58.35#ibcon#wrote, iclass 39, count 2 2006.257.21:21:58.35#ibcon#about to read 3, iclass 39, count 2 2006.257.21:21:58.38#ibcon#read 3, iclass 39, count 2 2006.257.21:21:58.38#ibcon#about to read 4, iclass 39, count 2 2006.257.21:21:58.38#ibcon#read 4, iclass 39, count 2 2006.257.21:21:58.38#ibcon#about to read 5, iclass 39, count 2 2006.257.21:21:58.38#ibcon#read 5, iclass 39, count 2 2006.257.21:21:58.38#ibcon#about to read 6, iclass 39, count 2 2006.257.21:21:58.38#ibcon#read 6, iclass 39, count 2 2006.257.21:21:58.38#ibcon#end of sib2, iclass 39, count 2 2006.257.21:21:58.38#ibcon#*after write, iclass 39, count 2 2006.257.21:21:58.38#ibcon#*before return 0, iclass 39, count 2 2006.257.21:21:58.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:58.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:21:58.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.21:21:58.38#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:58.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:58.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:58.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:58.50#ibcon#enter wrdev, iclass 39, count 0 2006.257.21:21:58.50#ibcon#first serial, iclass 39, count 0 2006.257.21:21:58.50#ibcon#enter sib2, iclass 39, count 0 2006.257.21:21:58.50#ibcon#flushed, iclass 39, count 0 2006.257.21:21:58.50#ibcon#about to write, iclass 39, count 0 2006.257.21:21:58.50#ibcon#wrote, iclass 39, count 0 2006.257.21:21:58.50#ibcon#about to read 3, iclass 39, count 0 2006.257.21:21:58.52#ibcon#read 3, iclass 39, count 0 2006.257.21:21:58.52#ibcon#about to read 4, iclass 39, count 0 2006.257.21:21:58.52#ibcon#read 4, iclass 39, count 0 2006.257.21:21:58.52#ibcon#about to read 5, iclass 39, count 0 2006.257.21:21:58.52#ibcon#read 5, iclass 39, count 0 2006.257.21:21:58.52#ibcon#about to read 6, iclass 39, count 0 2006.257.21:21:58.52#ibcon#read 6, iclass 39, count 0 2006.257.21:21:58.52#ibcon#end of sib2, iclass 39, count 0 2006.257.21:21:58.52#ibcon#*mode == 0, iclass 39, count 0 2006.257.21:21:58.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.21:21:58.52#ibcon#[27=USB\r\n] 2006.257.21:21:58.52#ibcon#*before write, iclass 39, count 0 2006.257.21:21:58.52#ibcon#enter sib2, iclass 39, count 0 2006.257.21:21:58.52#ibcon#flushed, iclass 39, count 0 2006.257.21:21:58.52#ibcon#about to write, iclass 39, count 0 2006.257.21:21:58.52#ibcon#wrote, iclass 39, count 0 2006.257.21:21:58.52#ibcon#about to read 3, iclass 39, count 0 2006.257.21:21:58.55#ibcon#read 3, iclass 39, count 0 2006.257.21:21:58.55#ibcon#about to read 4, iclass 39, count 0 2006.257.21:21:58.55#ibcon#read 4, iclass 39, count 0 2006.257.21:21:58.55#ibcon#about to read 5, iclass 39, count 0 2006.257.21:21:58.55#ibcon#read 5, iclass 39, count 0 2006.257.21:21:58.55#ibcon#about to read 6, iclass 39, count 0 2006.257.21:21:58.55#ibcon#read 6, iclass 39, count 0 2006.257.21:21:58.55#ibcon#end of sib2, iclass 39, count 0 2006.257.21:21:58.55#ibcon#*after write, iclass 39, count 0 2006.257.21:21:58.55#ibcon#*before return 0, iclass 39, count 0 2006.257.21:21:58.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:58.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:21:58.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.21:21:58.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.21:21:58.55$vck44/vblo=8,744.99 2006.257.21:21:58.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.21:21:58.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.21:21:58.55#ibcon#ireg 17 cls_cnt 0 2006.257.21:21:58.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:58.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:58.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:58.55#ibcon#enter wrdev, iclass 3, count 0 2006.257.21:21:58.55#ibcon#first serial, iclass 3, count 0 2006.257.21:21:58.55#ibcon#enter sib2, iclass 3, count 0 2006.257.21:21:58.55#ibcon#flushed, iclass 3, count 0 2006.257.21:21:58.55#ibcon#about to write, iclass 3, count 0 2006.257.21:21:58.55#ibcon#wrote, iclass 3, count 0 2006.257.21:21:58.55#ibcon#about to read 3, iclass 3, count 0 2006.257.21:21:58.57#ibcon#read 3, iclass 3, count 0 2006.257.21:21:58.57#ibcon#about to read 4, iclass 3, count 0 2006.257.21:21:58.57#ibcon#read 4, iclass 3, count 0 2006.257.21:21:58.57#ibcon#about to read 5, iclass 3, count 0 2006.257.21:21:58.57#ibcon#read 5, iclass 3, count 0 2006.257.21:21:58.57#ibcon#about to read 6, iclass 3, count 0 2006.257.21:21:58.57#ibcon#read 6, iclass 3, count 0 2006.257.21:21:58.57#ibcon#end of sib2, iclass 3, count 0 2006.257.21:21:58.57#ibcon#*mode == 0, iclass 3, count 0 2006.257.21:21:58.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.21:21:58.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.21:21:58.57#ibcon#*before write, iclass 3, count 0 2006.257.21:21:58.57#ibcon#enter sib2, iclass 3, count 0 2006.257.21:21:58.57#ibcon#flushed, iclass 3, count 0 2006.257.21:21:58.57#ibcon#about to write, iclass 3, count 0 2006.257.21:21:58.57#ibcon#wrote, iclass 3, count 0 2006.257.21:21:58.57#ibcon#about to read 3, iclass 3, count 0 2006.257.21:21:58.61#ibcon#read 3, iclass 3, count 0 2006.257.21:21:58.61#ibcon#about to read 4, iclass 3, count 0 2006.257.21:21:58.61#ibcon#read 4, iclass 3, count 0 2006.257.21:21:58.61#ibcon#about to read 5, iclass 3, count 0 2006.257.21:21:58.61#ibcon#read 5, iclass 3, count 0 2006.257.21:21:58.61#ibcon#about to read 6, iclass 3, count 0 2006.257.21:21:58.61#ibcon#read 6, iclass 3, count 0 2006.257.21:21:58.61#ibcon#end of sib2, iclass 3, count 0 2006.257.21:21:58.61#ibcon#*after write, iclass 3, count 0 2006.257.21:21:58.61#ibcon#*before return 0, iclass 3, count 0 2006.257.21:21:58.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:58.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:21:58.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.21:21:58.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.21:21:58.61$vck44/vb=8,4 2006.257.21:21:58.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.21:21:58.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.21:21:58.61#ibcon#ireg 11 cls_cnt 2 2006.257.21:21:58.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:58.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:58.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:58.67#ibcon#enter wrdev, iclass 5, count 2 2006.257.21:21:58.67#ibcon#first serial, iclass 5, count 2 2006.257.21:21:58.67#ibcon#enter sib2, iclass 5, count 2 2006.257.21:21:58.67#ibcon#flushed, iclass 5, count 2 2006.257.21:21:58.67#ibcon#about to write, iclass 5, count 2 2006.257.21:21:58.67#ibcon#wrote, iclass 5, count 2 2006.257.21:21:58.67#ibcon#about to read 3, iclass 5, count 2 2006.257.21:21:58.69#ibcon#read 3, iclass 5, count 2 2006.257.21:21:58.69#ibcon#about to read 4, iclass 5, count 2 2006.257.21:21:58.69#ibcon#read 4, iclass 5, count 2 2006.257.21:21:58.69#ibcon#about to read 5, iclass 5, count 2 2006.257.21:21:58.69#ibcon#read 5, iclass 5, count 2 2006.257.21:21:58.69#ibcon#about to read 6, iclass 5, count 2 2006.257.21:21:58.69#ibcon#read 6, iclass 5, count 2 2006.257.21:21:58.69#ibcon#end of sib2, iclass 5, count 2 2006.257.21:21:58.69#ibcon#*mode == 0, iclass 5, count 2 2006.257.21:21:58.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.21:21:58.69#ibcon#[27=AT08-04\r\n] 2006.257.21:21:58.69#ibcon#*before write, iclass 5, count 2 2006.257.21:21:58.69#ibcon#enter sib2, iclass 5, count 2 2006.257.21:21:58.69#ibcon#flushed, iclass 5, count 2 2006.257.21:21:58.69#ibcon#about to write, iclass 5, count 2 2006.257.21:21:58.69#ibcon#wrote, iclass 5, count 2 2006.257.21:21:58.69#ibcon#about to read 3, iclass 5, count 2 2006.257.21:21:58.72#ibcon#read 3, iclass 5, count 2 2006.257.21:21:58.72#ibcon#about to read 4, iclass 5, count 2 2006.257.21:21:58.72#ibcon#read 4, iclass 5, count 2 2006.257.21:21:58.72#ibcon#about to read 5, iclass 5, count 2 2006.257.21:21:58.72#ibcon#read 5, iclass 5, count 2 2006.257.21:21:58.72#ibcon#about to read 6, iclass 5, count 2 2006.257.21:21:58.72#ibcon#read 6, iclass 5, count 2 2006.257.21:21:58.72#ibcon#end of sib2, iclass 5, count 2 2006.257.21:21:58.72#ibcon#*after write, iclass 5, count 2 2006.257.21:21:58.72#ibcon#*before return 0, iclass 5, count 2 2006.257.21:21:58.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:58.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:21:58.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.21:21:58.72#ibcon#ireg 7 cls_cnt 0 2006.257.21:21:58.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:58.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:58.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:58.84#ibcon#enter wrdev, iclass 5, count 0 2006.257.21:21:58.84#ibcon#first serial, iclass 5, count 0 2006.257.21:21:58.84#ibcon#enter sib2, iclass 5, count 0 2006.257.21:21:58.84#ibcon#flushed, iclass 5, count 0 2006.257.21:21:58.84#ibcon#about to write, iclass 5, count 0 2006.257.21:21:58.84#ibcon#wrote, iclass 5, count 0 2006.257.21:21:58.84#ibcon#about to read 3, iclass 5, count 0 2006.257.21:21:58.86#ibcon#read 3, iclass 5, count 0 2006.257.21:21:58.86#ibcon#about to read 4, iclass 5, count 0 2006.257.21:21:58.86#ibcon#read 4, iclass 5, count 0 2006.257.21:21:58.86#ibcon#about to read 5, iclass 5, count 0 2006.257.21:21:58.86#ibcon#read 5, iclass 5, count 0 2006.257.21:21:58.86#ibcon#about to read 6, iclass 5, count 0 2006.257.21:21:58.86#ibcon#read 6, iclass 5, count 0 2006.257.21:21:58.86#ibcon#end of sib2, iclass 5, count 0 2006.257.21:21:58.86#ibcon#*mode == 0, iclass 5, count 0 2006.257.21:21:58.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.21:21:58.86#ibcon#[27=USB\r\n] 2006.257.21:21:58.86#ibcon#*before write, iclass 5, count 0 2006.257.21:21:58.86#ibcon#enter sib2, iclass 5, count 0 2006.257.21:21:58.86#ibcon#flushed, iclass 5, count 0 2006.257.21:21:58.86#ibcon#about to write, iclass 5, count 0 2006.257.21:21:58.86#ibcon#wrote, iclass 5, count 0 2006.257.21:21:58.86#ibcon#about to read 3, iclass 5, count 0 2006.257.21:21:58.89#ibcon#read 3, iclass 5, count 0 2006.257.21:21:58.89#ibcon#about to read 4, iclass 5, count 0 2006.257.21:21:58.89#ibcon#read 4, iclass 5, count 0 2006.257.21:21:58.89#ibcon#about to read 5, iclass 5, count 0 2006.257.21:21:58.89#ibcon#read 5, iclass 5, count 0 2006.257.21:21:58.89#ibcon#about to read 6, iclass 5, count 0 2006.257.21:21:58.89#ibcon#read 6, iclass 5, count 0 2006.257.21:21:58.89#ibcon#end of sib2, iclass 5, count 0 2006.257.21:21:58.89#ibcon#*after write, iclass 5, count 0 2006.257.21:21:58.89#ibcon#*before return 0, iclass 5, count 0 2006.257.21:21:58.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:58.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:21:58.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.21:21:58.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.21:21:58.89$vck44/vabw=wide 2006.257.21:21:58.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.21:21:58.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.21:21:58.89#ibcon#ireg 8 cls_cnt 0 2006.257.21:21:58.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:58.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:58.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:58.89#ibcon#enter wrdev, iclass 7, count 0 2006.257.21:21:58.89#ibcon#first serial, iclass 7, count 0 2006.257.21:21:58.89#ibcon#enter sib2, iclass 7, count 0 2006.257.21:21:58.89#ibcon#flushed, iclass 7, count 0 2006.257.21:21:58.89#ibcon#about to write, iclass 7, count 0 2006.257.21:21:58.89#ibcon#wrote, iclass 7, count 0 2006.257.21:21:58.89#ibcon#about to read 3, iclass 7, count 0 2006.257.21:21:58.91#ibcon#read 3, iclass 7, count 0 2006.257.21:21:58.91#ibcon#about to read 4, iclass 7, count 0 2006.257.21:21:58.91#ibcon#read 4, iclass 7, count 0 2006.257.21:21:58.91#ibcon#about to read 5, iclass 7, count 0 2006.257.21:21:58.91#ibcon#read 5, iclass 7, count 0 2006.257.21:21:58.91#ibcon#about to read 6, iclass 7, count 0 2006.257.21:21:58.91#ibcon#read 6, iclass 7, count 0 2006.257.21:21:58.91#ibcon#end of sib2, iclass 7, count 0 2006.257.21:21:58.91#ibcon#*mode == 0, iclass 7, count 0 2006.257.21:21:58.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.21:21:58.91#ibcon#[25=BW32\r\n] 2006.257.21:21:58.91#ibcon#*before write, iclass 7, count 0 2006.257.21:21:58.91#ibcon#enter sib2, iclass 7, count 0 2006.257.21:21:58.91#ibcon#flushed, iclass 7, count 0 2006.257.21:21:58.91#ibcon#about to write, iclass 7, count 0 2006.257.21:21:58.91#ibcon#wrote, iclass 7, count 0 2006.257.21:21:58.91#ibcon#about to read 3, iclass 7, count 0 2006.257.21:21:58.94#ibcon#read 3, iclass 7, count 0 2006.257.21:21:58.94#ibcon#about to read 4, iclass 7, count 0 2006.257.21:21:58.94#ibcon#read 4, iclass 7, count 0 2006.257.21:21:58.94#ibcon#about to read 5, iclass 7, count 0 2006.257.21:21:58.94#ibcon#read 5, iclass 7, count 0 2006.257.21:21:58.94#ibcon#about to read 6, iclass 7, count 0 2006.257.21:21:58.94#ibcon#read 6, iclass 7, count 0 2006.257.21:21:58.94#ibcon#end of sib2, iclass 7, count 0 2006.257.21:21:58.94#ibcon#*after write, iclass 7, count 0 2006.257.21:21:58.94#ibcon#*before return 0, iclass 7, count 0 2006.257.21:21:58.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:58.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:21:58.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.21:21:58.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.21:21:58.94$vck44/vbbw=wide 2006.257.21:21:58.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.21:21:58.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.21:21:58.94#ibcon#ireg 8 cls_cnt 0 2006.257.21:21:58.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:21:59.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:21:59.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:21:59.01#ibcon#enter wrdev, iclass 11, count 0 2006.257.21:21:59.01#ibcon#first serial, iclass 11, count 0 2006.257.21:21:59.01#ibcon#enter sib2, iclass 11, count 0 2006.257.21:21:59.01#ibcon#flushed, iclass 11, count 0 2006.257.21:21:59.01#ibcon#about to write, iclass 11, count 0 2006.257.21:21:59.01#ibcon#wrote, iclass 11, count 0 2006.257.21:21:59.01#ibcon#about to read 3, iclass 11, count 0 2006.257.21:21:59.03#ibcon#read 3, iclass 11, count 0 2006.257.21:21:59.03#ibcon#about to read 4, iclass 11, count 0 2006.257.21:21:59.03#ibcon#read 4, iclass 11, count 0 2006.257.21:21:59.03#ibcon#about to read 5, iclass 11, count 0 2006.257.21:21:59.03#ibcon#read 5, iclass 11, count 0 2006.257.21:21:59.03#ibcon#about to read 6, iclass 11, count 0 2006.257.21:21:59.03#ibcon#read 6, iclass 11, count 0 2006.257.21:21:59.03#ibcon#end of sib2, iclass 11, count 0 2006.257.21:21:59.03#ibcon#*mode == 0, iclass 11, count 0 2006.257.21:21:59.03#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.21:21:59.03#ibcon#[27=BW32\r\n] 2006.257.21:21:59.03#ibcon#*before write, iclass 11, count 0 2006.257.21:21:59.03#ibcon#enter sib2, iclass 11, count 0 2006.257.21:21:59.03#ibcon#flushed, iclass 11, count 0 2006.257.21:21:59.03#ibcon#about to write, iclass 11, count 0 2006.257.21:21:59.03#ibcon#wrote, iclass 11, count 0 2006.257.21:21:59.03#ibcon#about to read 3, iclass 11, count 0 2006.257.21:21:59.06#ibcon#read 3, iclass 11, count 0 2006.257.21:21:59.06#ibcon#about to read 4, iclass 11, count 0 2006.257.21:21:59.06#ibcon#read 4, iclass 11, count 0 2006.257.21:21:59.06#ibcon#about to read 5, iclass 11, count 0 2006.257.21:21:59.06#ibcon#read 5, iclass 11, count 0 2006.257.21:21:59.06#ibcon#about to read 6, iclass 11, count 0 2006.257.21:21:59.06#ibcon#read 6, iclass 11, count 0 2006.257.21:21:59.06#ibcon#end of sib2, iclass 11, count 0 2006.257.21:21:59.06#ibcon#*after write, iclass 11, count 0 2006.257.21:21:59.06#ibcon#*before return 0, iclass 11, count 0 2006.257.21:21:59.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:21:59.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:21:59.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.21:21:59.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.21:21:59.06$setupk4/ifdk4 2006.257.21:21:59.06$ifdk4/lo= 2006.257.21:21:59.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.21:21:59.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.21:21:59.06$ifdk4/patch= 2006.257.21:21:59.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.21:21:59.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.21:21:59.06$setupk4/!*+20s 2006.257.21:21:59.46#abcon#<5=/14 1.2 2.5 17.77 951015.5\r\n> 2006.257.21:21:59.48#abcon#{5=INTERFACE CLEAR} 2006.257.21:21:59.54#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:22:09.63#abcon#<5=/14 1.1 2.5 17.77 951015.5\r\n> 2006.257.21:22:09.65#abcon#{5=INTERFACE CLEAR} 2006.257.21:22:09.71#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:22:13.57$setupk4/"tpicd 2006.257.21:22:13.57$setupk4/echo=off 2006.257.21:22:13.57$setupk4/xlog=off 2006.257.21:22:13.57:!2006.257.21:26:34 2006.257.21:22:30.14#trakl#Source acquired 2006.257.21:22:31.14#flagr#flagr/antenna,acquired 2006.257.21:26:34.00:preob 2006.257.21:26:35.13/onsource/TRACKING 2006.257.21:26:35.13:!2006.257.21:26:44 2006.257.21:26:44.00:"tape 2006.257.21:26:44.00:"st=record 2006.257.21:26:44.00:data_valid=on 2006.257.21:26:44.00:midob 2006.257.21:26:44.13/onsource/TRACKING 2006.257.21:26:44.13/wx/17.81,1015.5,95 2006.257.21:26:44.27/cable/+6.4851E-03 2006.257.21:26:45.36/va/01,08,usb,yes,31,34 2006.257.21:26:45.36/va/02,07,usb,yes,34,34 2006.257.21:26:45.36/va/03,08,usb,yes,30,32 2006.257.21:26:45.36/va/04,07,usb,yes,35,37 2006.257.21:26:45.36/va/05,04,usb,yes,31,32 2006.257.21:26:45.36/va/06,04,usb,yes,35,34 2006.257.21:26:45.36/va/07,04,usb,yes,36,36 2006.257.21:26:45.36/va/08,04,usb,yes,30,36 2006.257.21:26:45.59/valo/01,524.99,yes,locked 2006.257.21:26:45.59/valo/02,534.99,yes,locked 2006.257.21:26:45.59/valo/03,564.99,yes,locked 2006.257.21:26:45.59/valo/04,624.99,yes,locked 2006.257.21:26:45.59/valo/05,734.99,yes,locked 2006.257.21:26:45.59/valo/06,814.99,yes,locked 2006.257.21:26:45.59/valo/07,864.99,yes,locked 2006.257.21:26:45.59/valo/08,884.99,yes,locked 2006.257.21:26:46.68/vb/01,04,usb,yes,29,27 2006.257.21:26:46.68/vb/02,05,usb,yes,28,28 2006.257.21:26:46.68/vb/03,04,usb,yes,29,32 2006.257.21:26:46.68/vb/04,05,usb,yes,29,28 2006.257.21:26:46.68/vb/05,04,usb,yes,26,28 2006.257.21:26:46.68/vb/06,04,usb,yes,30,26 2006.257.21:26:46.68/vb/07,04,usb,yes,30,30 2006.257.21:26:46.68/vb/08,04,usb,yes,27,31 2006.257.21:26:46.91/vblo/01,629.99,yes,locked 2006.257.21:26:46.91/vblo/02,634.99,yes,locked 2006.257.21:26:46.91/vblo/03,649.99,yes,locked 2006.257.21:26:46.91/vblo/04,679.99,yes,locked 2006.257.21:26:46.91/vblo/05,709.99,yes,locked 2006.257.21:26:46.91/vblo/06,719.99,yes,locked 2006.257.21:26:46.91/vblo/07,734.99,yes,locked 2006.257.21:26:46.91/vblo/08,744.99,yes,locked 2006.257.21:26:47.06/vabw/8 2006.257.21:26:47.21/vbbw/8 2006.257.21:26:47.30/xfe/off,on,15.2 2006.257.21:26:47.67/ifatt/23,28,28,28 2006.257.21:26:48.07/fmout-gps/S +4.56E-07 2006.257.21:26:48.11:!2006.257.21:28:24 2006.257.21:28:24.00:data_valid=off 2006.257.21:28:24.00:"et 2006.257.21:28:24.00:!+3s 2006.257.21:28:27.02:"tape 2006.257.21:28:27.02:postob 2006.257.21:28:27.11/cable/+6.4849E-03 2006.257.21:28:27.11/wx/17.81,1015.5,95 2006.257.21:28:27.17/fmout-gps/S +4.56E-07 2006.257.21:28:27.17:scan_name=257-2130,jd0609,60 2006.257.21:28:27.17:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.257.21:28:29.14#flagr#flagr/antenna,new-source 2006.257.21:28:29.14:checkk5 2006.257.21:28:29.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.21:28:29.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.21:28:30.20/chk_autoobs//k5ts3/ autoobs is running! 2006.257.21:28:30.54/chk_autoobs//k5ts4/ autoobs is running! 2006.257.21:28:30.87/chk_obsdata//k5ts1/T2572126??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.21:28:31.20/chk_obsdata//k5ts2/T2572126??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.21:28:31.53/chk_obsdata//k5ts3/T2572126??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.21:28:31.86/chk_obsdata//k5ts4/T2572126??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.21:28:32.52/k5log//k5ts1_log_newline 2006.257.21:28:33.18/k5log//k5ts2_log_newline 2006.257.21:28:33.83/k5log//k5ts3_log_newline 2006.257.21:28:34.49/k5log//k5ts4_log_newline 2006.257.21:28:34.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.21:28:34.51:setupk4=1 2006.257.21:28:34.51$setupk4/echo=on 2006.257.21:28:34.51$setupk4/pcalon 2006.257.21:28:34.51$pcalon/"no phase cal control is implemented here 2006.257.21:28:34.51$setupk4/"tpicd=stop 2006.257.21:28:34.51$setupk4/"rec=synch_on 2006.257.21:28:34.51$setupk4/"rec_mode=128 2006.257.21:28:34.51$setupk4/!* 2006.257.21:28:34.51$setupk4/recpk4 2006.257.21:28:34.51$recpk4/recpatch= 2006.257.21:28:34.52$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.21:28:34.52$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.21:28:34.52$setupk4/vck44 2006.257.21:28:34.52$vck44/valo=1,524.99 2006.257.21:28:34.52#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.21:28:34.52#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.21:28:34.52#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:34.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:34.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:34.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:34.52#ibcon#enter wrdev, iclass 28, count 0 2006.257.21:28:34.52#ibcon#first serial, iclass 28, count 0 2006.257.21:28:34.52#ibcon#enter sib2, iclass 28, count 0 2006.257.21:28:34.52#ibcon#flushed, iclass 28, count 0 2006.257.21:28:34.52#ibcon#about to write, iclass 28, count 0 2006.257.21:28:34.52#ibcon#wrote, iclass 28, count 0 2006.257.21:28:34.52#ibcon#about to read 3, iclass 28, count 0 2006.257.21:28:34.54#ibcon#read 3, iclass 28, count 0 2006.257.21:28:34.54#ibcon#about to read 4, iclass 28, count 0 2006.257.21:28:34.54#ibcon#read 4, iclass 28, count 0 2006.257.21:28:34.54#ibcon#about to read 5, iclass 28, count 0 2006.257.21:28:34.54#ibcon#read 5, iclass 28, count 0 2006.257.21:28:34.54#ibcon#about to read 6, iclass 28, count 0 2006.257.21:28:34.54#ibcon#read 6, iclass 28, count 0 2006.257.21:28:34.54#ibcon#end of sib2, iclass 28, count 0 2006.257.21:28:34.54#ibcon#*mode == 0, iclass 28, count 0 2006.257.21:28:34.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.21:28:34.54#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.21:28:34.54#ibcon#*before write, iclass 28, count 0 2006.257.21:28:34.54#ibcon#enter sib2, iclass 28, count 0 2006.257.21:28:34.54#ibcon#flushed, iclass 28, count 0 2006.257.21:28:34.54#ibcon#about to write, iclass 28, count 0 2006.257.21:28:34.54#ibcon#wrote, iclass 28, count 0 2006.257.21:28:34.54#ibcon#about to read 3, iclass 28, count 0 2006.257.21:28:34.59#ibcon#read 3, iclass 28, count 0 2006.257.21:28:34.59#ibcon#about to read 4, iclass 28, count 0 2006.257.21:28:34.59#ibcon#read 4, iclass 28, count 0 2006.257.21:28:34.59#ibcon#about to read 5, iclass 28, count 0 2006.257.21:28:34.59#ibcon#read 5, iclass 28, count 0 2006.257.21:28:34.59#ibcon#about to read 6, iclass 28, count 0 2006.257.21:28:34.59#ibcon#read 6, iclass 28, count 0 2006.257.21:28:34.59#ibcon#end of sib2, iclass 28, count 0 2006.257.21:28:34.59#ibcon#*after write, iclass 28, count 0 2006.257.21:28:34.59#ibcon#*before return 0, iclass 28, count 0 2006.257.21:28:34.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:34.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:34.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.21:28:34.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.21:28:34.59$vck44/va=1,8 2006.257.21:28:34.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.21:28:34.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.21:28:34.59#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:34.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:34.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:34.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:34.59#ibcon#enter wrdev, iclass 30, count 2 2006.257.21:28:34.59#ibcon#first serial, iclass 30, count 2 2006.257.21:28:34.59#ibcon#enter sib2, iclass 30, count 2 2006.257.21:28:34.59#ibcon#flushed, iclass 30, count 2 2006.257.21:28:34.59#ibcon#about to write, iclass 30, count 2 2006.257.21:28:34.59#ibcon#wrote, iclass 30, count 2 2006.257.21:28:34.59#ibcon#about to read 3, iclass 30, count 2 2006.257.21:28:34.61#ibcon#read 3, iclass 30, count 2 2006.257.21:28:34.61#ibcon#about to read 4, iclass 30, count 2 2006.257.21:28:34.61#ibcon#read 4, iclass 30, count 2 2006.257.21:28:34.61#ibcon#about to read 5, iclass 30, count 2 2006.257.21:28:34.61#ibcon#read 5, iclass 30, count 2 2006.257.21:28:34.61#ibcon#about to read 6, iclass 30, count 2 2006.257.21:28:34.61#ibcon#read 6, iclass 30, count 2 2006.257.21:28:34.61#ibcon#end of sib2, iclass 30, count 2 2006.257.21:28:34.61#ibcon#*mode == 0, iclass 30, count 2 2006.257.21:28:34.61#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.21:28:34.61#ibcon#[25=AT01-08\r\n] 2006.257.21:28:34.61#ibcon#*before write, iclass 30, count 2 2006.257.21:28:34.61#ibcon#enter sib2, iclass 30, count 2 2006.257.21:28:34.61#ibcon#flushed, iclass 30, count 2 2006.257.21:28:34.61#ibcon#about to write, iclass 30, count 2 2006.257.21:28:34.61#ibcon#wrote, iclass 30, count 2 2006.257.21:28:34.61#ibcon#about to read 3, iclass 30, count 2 2006.257.21:28:34.64#ibcon#read 3, iclass 30, count 2 2006.257.21:28:34.64#ibcon#about to read 4, iclass 30, count 2 2006.257.21:28:34.64#ibcon#read 4, iclass 30, count 2 2006.257.21:28:34.64#ibcon#about to read 5, iclass 30, count 2 2006.257.21:28:34.64#ibcon#read 5, iclass 30, count 2 2006.257.21:28:34.64#ibcon#about to read 6, iclass 30, count 2 2006.257.21:28:34.64#ibcon#read 6, iclass 30, count 2 2006.257.21:28:34.64#ibcon#end of sib2, iclass 30, count 2 2006.257.21:28:34.64#ibcon#*after write, iclass 30, count 2 2006.257.21:28:34.64#ibcon#*before return 0, iclass 30, count 2 2006.257.21:28:34.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:34.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:34.64#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.21:28:34.64#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:34.64#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:34.76#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:34.76#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:34.76#ibcon#enter wrdev, iclass 30, count 0 2006.257.21:28:34.76#ibcon#first serial, iclass 30, count 0 2006.257.21:28:34.76#ibcon#enter sib2, iclass 30, count 0 2006.257.21:28:34.76#ibcon#flushed, iclass 30, count 0 2006.257.21:28:34.76#ibcon#about to write, iclass 30, count 0 2006.257.21:28:34.76#ibcon#wrote, iclass 30, count 0 2006.257.21:28:34.76#ibcon#about to read 3, iclass 30, count 0 2006.257.21:28:34.78#ibcon#read 3, iclass 30, count 0 2006.257.21:28:34.78#ibcon#about to read 4, iclass 30, count 0 2006.257.21:28:34.78#ibcon#read 4, iclass 30, count 0 2006.257.21:28:34.78#ibcon#about to read 5, iclass 30, count 0 2006.257.21:28:34.78#ibcon#read 5, iclass 30, count 0 2006.257.21:28:34.78#ibcon#about to read 6, iclass 30, count 0 2006.257.21:28:34.78#ibcon#read 6, iclass 30, count 0 2006.257.21:28:34.78#ibcon#end of sib2, iclass 30, count 0 2006.257.21:28:34.78#ibcon#*mode == 0, iclass 30, count 0 2006.257.21:28:34.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.21:28:34.78#ibcon#[25=USB\r\n] 2006.257.21:28:34.78#ibcon#*before write, iclass 30, count 0 2006.257.21:28:34.78#ibcon#enter sib2, iclass 30, count 0 2006.257.21:28:34.78#ibcon#flushed, iclass 30, count 0 2006.257.21:28:34.78#ibcon#about to write, iclass 30, count 0 2006.257.21:28:34.78#ibcon#wrote, iclass 30, count 0 2006.257.21:28:34.78#ibcon#about to read 3, iclass 30, count 0 2006.257.21:28:34.81#ibcon#read 3, iclass 30, count 0 2006.257.21:28:34.81#ibcon#about to read 4, iclass 30, count 0 2006.257.21:28:34.81#ibcon#read 4, iclass 30, count 0 2006.257.21:28:34.81#ibcon#about to read 5, iclass 30, count 0 2006.257.21:28:34.81#ibcon#read 5, iclass 30, count 0 2006.257.21:28:34.81#ibcon#about to read 6, iclass 30, count 0 2006.257.21:28:34.81#ibcon#read 6, iclass 30, count 0 2006.257.21:28:34.81#ibcon#end of sib2, iclass 30, count 0 2006.257.21:28:34.81#ibcon#*after write, iclass 30, count 0 2006.257.21:28:34.81#ibcon#*before return 0, iclass 30, count 0 2006.257.21:28:34.81#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:34.81#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:34.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.21:28:34.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.21:28:34.81$vck44/valo=2,534.99 2006.257.21:28:34.81#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.21:28:34.81#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.21:28:34.81#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:34.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:34.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:34.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:34.81#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:28:34.81#ibcon#first serial, iclass 32, count 0 2006.257.21:28:34.81#ibcon#enter sib2, iclass 32, count 0 2006.257.21:28:34.81#ibcon#flushed, iclass 32, count 0 2006.257.21:28:34.81#ibcon#about to write, iclass 32, count 0 2006.257.21:28:34.81#ibcon#wrote, iclass 32, count 0 2006.257.21:28:34.81#ibcon#about to read 3, iclass 32, count 0 2006.257.21:28:34.83#ibcon#read 3, iclass 32, count 0 2006.257.21:28:34.83#ibcon#about to read 4, iclass 32, count 0 2006.257.21:28:34.83#ibcon#read 4, iclass 32, count 0 2006.257.21:28:34.83#ibcon#about to read 5, iclass 32, count 0 2006.257.21:28:34.83#ibcon#read 5, iclass 32, count 0 2006.257.21:28:34.83#ibcon#about to read 6, iclass 32, count 0 2006.257.21:28:34.83#ibcon#read 6, iclass 32, count 0 2006.257.21:28:34.83#ibcon#end of sib2, iclass 32, count 0 2006.257.21:28:34.83#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:28:34.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:28:34.83#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.21:28:34.83#ibcon#*before write, iclass 32, count 0 2006.257.21:28:34.83#ibcon#enter sib2, iclass 32, count 0 2006.257.21:28:34.83#ibcon#flushed, iclass 32, count 0 2006.257.21:28:34.83#ibcon#about to write, iclass 32, count 0 2006.257.21:28:34.83#ibcon#wrote, iclass 32, count 0 2006.257.21:28:34.83#ibcon#about to read 3, iclass 32, count 0 2006.257.21:28:34.87#ibcon#read 3, iclass 32, count 0 2006.257.21:28:34.87#ibcon#about to read 4, iclass 32, count 0 2006.257.21:28:34.87#ibcon#read 4, iclass 32, count 0 2006.257.21:28:34.87#ibcon#about to read 5, iclass 32, count 0 2006.257.21:28:34.87#ibcon#read 5, iclass 32, count 0 2006.257.21:28:34.87#ibcon#about to read 6, iclass 32, count 0 2006.257.21:28:34.87#ibcon#read 6, iclass 32, count 0 2006.257.21:28:34.87#ibcon#end of sib2, iclass 32, count 0 2006.257.21:28:34.87#ibcon#*after write, iclass 32, count 0 2006.257.21:28:34.87#ibcon#*before return 0, iclass 32, count 0 2006.257.21:28:34.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:34.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:34.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:28:34.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:28:34.87$vck44/va=2,7 2006.257.21:28:34.87#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.21:28:34.87#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.21:28:34.87#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:34.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:34.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:34.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:34.93#ibcon#enter wrdev, iclass 34, count 2 2006.257.21:28:34.93#ibcon#first serial, iclass 34, count 2 2006.257.21:28:34.93#ibcon#enter sib2, iclass 34, count 2 2006.257.21:28:34.93#ibcon#flushed, iclass 34, count 2 2006.257.21:28:34.93#ibcon#about to write, iclass 34, count 2 2006.257.21:28:34.93#ibcon#wrote, iclass 34, count 2 2006.257.21:28:34.93#ibcon#about to read 3, iclass 34, count 2 2006.257.21:28:34.95#ibcon#read 3, iclass 34, count 2 2006.257.21:28:34.95#ibcon#about to read 4, iclass 34, count 2 2006.257.21:28:34.95#ibcon#read 4, iclass 34, count 2 2006.257.21:28:34.95#ibcon#about to read 5, iclass 34, count 2 2006.257.21:28:34.95#ibcon#read 5, iclass 34, count 2 2006.257.21:28:34.95#ibcon#about to read 6, iclass 34, count 2 2006.257.21:28:34.95#ibcon#read 6, iclass 34, count 2 2006.257.21:28:34.95#ibcon#end of sib2, iclass 34, count 2 2006.257.21:28:34.95#ibcon#*mode == 0, iclass 34, count 2 2006.257.21:28:34.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.21:28:34.95#ibcon#[25=AT02-07\r\n] 2006.257.21:28:34.95#ibcon#*before write, iclass 34, count 2 2006.257.21:28:34.95#ibcon#enter sib2, iclass 34, count 2 2006.257.21:28:34.95#ibcon#flushed, iclass 34, count 2 2006.257.21:28:34.95#ibcon#about to write, iclass 34, count 2 2006.257.21:28:34.95#ibcon#wrote, iclass 34, count 2 2006.257.21:28:34.95#ibcon#about to read 3, iclass 34, count 2 2006.257.21:28:34.98#ibcon#read 3, iclass 34, count 2 2006.257.21:28:34.98#ibcon#about to read 4, iclass 34, count 2 2006.257.21:28:34.98#ibcon#read 4, iclass 34, count 2 2006.257.21:28:34.98#ibcon#about to read 5, iclass 34, count 2 2006.257.21:28:34.98#ibcon#read 5, iclass 34, count 2 2006.257.21:28:34.98#ibcon#about to read 6, iclass 34, count 2 2006.257.21:28:34.98#ibcon#read 6, iclass 34, count 2 2006.257.21:28:34.98#ibcon#end of sib2, iclass 34, count 2 2006.257.21:28:34.98#ibcon#*after write, iclass 34, count 2 2006.257.21:28:34.98#ibcon#*before return 0, iclass 34, count 2 2006.257.21:28:34.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:34.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:34.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.21:28:34.98#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:34.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:35.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:35.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:35.10#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:28:35.10#ibcon#first serial, iclass 34, count 0 2006.257.21:28:35.10#ibcon#enter sib2, iclass 34, count 0 2006.257.21:28:35.10#ibcon#flushed, iclass 34, count 0 2006.257.21:28:35.10#ibcon#about to write, iclass 34, count 0 2006.257.21:28:35.10#ibcon#wrote, iclass 34, count 0 2006.257.21:28:35.10#ibcon#about to read 3, iclass 34, count 0 2006.257.21:28:35.12#ibcon#read 3, iclass 34, count 0 2006.257.21:28:35.12#ibcon#about to read 4, iclass 34, count 0 2006.257.21:28:35.12#ibcon#read 4, iclass 34, count 0 2006.257.21:28:35.12#ibcon#about to read 5, iclass 34, count 0 2006.257.21:28:35.12#ibcon#read 5, iclass 34, count 0 2006.257.21:28:35.12#ibcon#about to read 6, iclass 34, count 0 2006.257.21:28:35.12#ibcon#read 6, iclass 34, count 0 2006.257.21:28:35.12#ibcon#end of sib2, iclass 34, count 0 2006.257.21:28:35.12#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:28:35.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:28:35.12#ibcon#[25=USB\r\n] 2006.257.21:28:35.12#ibcon#*before write, iclass 34, count 0 2006.257.21:28:35.12#ibcon#enter sib2, iclass 34, count 0 2006.257.21:28:35.12#ibcon#flushed, iclass 34, count 0 2006.257.21:28:35.12#ibcon#about to write, iclass 34, count 0 2006.257.21:28:35.12#ibcon#wrote, iclass 34, count 0 2006.257.21:28:35.12#ibcon#about to read 3, iclass 34, count 0 2006.257.21:28:35.15#ibcon#read 3, iclass 34, count 0 2006.257.21:28:35.15#ibcon#about to read 4, iclass 34, count 0 2006.257.21:28:35.15#ibcon#read 4, iclass 34, count 0 2006.257.21:28:35.15#ibcon#about to read 5, iclass 34, count 0 2006.257.21:28:35.15#ibcon#read 5, iclass 34, count 0 2006.257.21:28:35.15#ibcon#about to read 6, iclass 34, count 0 2006.257.21:28:35.15#ibcon#read 6, iclass 34, count 0 2006.257.21:28:35.15#ibcon#end of sib2, iclass 34, count 0 2006.257.21:28:35.15#ibcon#*after write, iclass 34, count 0 2006.257.21:28:35.15#ibcon#*before return 0, iclass 34, count 0 2006.257.21:28:35.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:35.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:35.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:28:35.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:28:35.15$vck44/valo=3,564.99 2006.257.21:28:35.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.21:28:35.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.21:28:35.15#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:35.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:35.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:35.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:35.15#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:28:35.15#ibcon#first serial, iclass 36, count 0 2006.257.21:28:35.15#ibcon#enter sib2, iclass 36, count 0 2006.257.21:28:35.15#ibcon#flushed, iclass 36, count 0 2006.257.21:28:35.15#ibcon#about to write, iclass 36, count 0 2006.257.21:28:35.15#ibcon#wrote, iclass 36, count 0 2006.257.21:28:35.15#ibcon#about to read 3, iclass 36, count 0 2006.257.21:28:35.17#ibcon#read 3, iclass 36, count 0 2006.257.21:28:35.17#ibcon#about to read 4, iclass 36, count 0 2006.257.21:28:35.17#ibcon#read 4, iclass 36, count 0 2006.257.21:28:35.17#ibcon#about to read 5, iclass 36, count 0 2006.257.21:28:35.17#ibcon#read 5, iclass 36, count 0 2006.257.21:28:35.17#ibcon#about to read 6, iclass 36, count 0 2006.257.21:28:35.17#ibcon#read 6, iclass 36, count 0 2006.257.21:28:35.17#ibcon#end of sib2, iclass 36, count 0 2006.257.21:28:35.17#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:28:35.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:28:35.17#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.21:28:35.17#ibcon#*before write, iclass 36, count 0 2006.257.21:28:35.17#ibcon#enter sib2, iclass 36, count 0 2006.257.21:28:35.17#ibcon#flushed, iclass 36, count 0 2006.257.21:28:35.17#ibcon#about to write, iclass 36, count 0 2006.257.21:28:35.17#ibcon#wrote, iclass 36, count 0 2006.257.21:28:35.17#ibcon#about to read 3, iclass 36, count 0 2006.257.21:28:35.21#ibcon#read 3, iclass 36, count 0 2006.257.21:28:35.21#ibcon#about to read 4, iclass 36, count 0 2006.257.21:28:35.21#ibcon#read 4, iclass 36, count 0 2006.257.21:28:35.21#ibcon#about to read 5, iclass 36, count 0 2006.257.21:28:35.21#ibcon#read 5, iclass 36, count 0 2006.257.21:28:35.21#ibcon#about to read 6, iclass 36, count 0 2006.257.21:28:35.21#ibcon#read 6, iclass 36, count 0 2006.257.21:28:35.21#ibcon#end of sib2, iclass 36, count 0 2006.257.21:28:35.21#ibcon#*after write, iclass 36, count 0 2006.257.21:28:35.21#ibcon#*before return 0, iclass 36, count 0 2006.257.21:28:35.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:35.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:35.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:28:35.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:28:35.21$vck44/va=3,8 2006.257.21:28:35.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.21:28:35.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.21:28:35.21#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:35.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:35.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:35.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:35.27#ibcon#enter wrdev, iclass 38, count 2 2006.257.21:28:35.27#ibcon#first serial, iclass 38, count 2 2006.257.21:28:35.27#ibcon#enter sib2, iclass 38, count 2 2006.257.21:28:35.27#ibcon#flushed, iclass 38, count 2 2006.257.21:28:35.27#ibcon#about to write, iclass 38, count 2 2006.257.21:28:35.27#ibcon#wrote, iclass 38, count 2 2006.257.21:28:35.27#ibcon#about to read 3, iclass 38, count 2 2006.257.21:28:35.29#ibcon#read 3, iclass 38, count 2 2006.257.21:28:35.29#ibcon#about to read 4, iclass 38, count 2 2006.257.21:28:35.29#ibcon#read 4, iclass 38, count 2 2006.257.21:28:35.29#ibcon#about to read 5, iclass 38, count 2 2006.257.21:28:35.29#ibcon#read 5, iclass 38, count 2 2006.257.21:28:35.29#ibcon#about to read 6, iclass 38, count 2 2006.257.21:28:35.29#ibcon#read 6, iclass 38, count 2 2006.257.21:28:35.29#ibcon#end of sib2, iclass 38, count 2 2006.257.21:28:35.29#ibcon#*mode == 0, iclass 38, count 2 2006.257.21:28:35.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.21:28:35.29#ibcon#[25=AT03-08\r\n] 2006.257.21:28:35.29#ibcon#*before write, iclass 38, count 2 2006.257.21:28:35.29#ibcon#enter sib2, iclass 38, count 2 2006.257.21:28:35.29#ibcon#flushed, iclass 38, count 2 2006.257.21:28:35.29#ibcon#about to write, iclass 38, count 2 2006.257.21:28:35.29#ibcon#wrote, iclass 38, count 2 2006.257.21:28:35.29#ibcon#about to read 3, iclass 38, count 2 2006.257.21:28:35.32#ibcon#read 3, iclass 38, count 2 2006.257.21:28:35.32#ibcon#about to read 4, iclass 38, count 2 2006.257.21:28:35.32#ibcon#read 4, iclass 38, count 2 2006.257.21:28:35.32#ibcon#about to read 5, iclass 38, count 2 2006.257.21:28:35.32#ibcon#read 5, iclass 38, count 2 2006.257.21:28:35.32#ibcon#about to read 6, iclass 38, count 2 2006.257.21:28:35.32#ibcon#read 6, iclass 38, count 2 2006.257.21:28:35.32#ibcon#end of sib2, iclass 38, count 2 2006.257.21:28:35.32#ibcon#*after write, iclass 38, count 2 2006.257.21:28:35.32#ibcon#*before return 0, iclass 38, count 2 2006.257.21:28:35.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:35.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:35.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.21:28:35.32#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:35.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:35.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:35.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:35.44#ibcon#enter wrdev, iclass 38, count 0 2006.257.21:28:35.44#ibcon#first serial, iclass 38, count 0 2006.257.21:28:35.44#ibcon#enter sib2, iclass 38, count 0 2006.257.21:28:35.44#ibcon#flushed, iclass 38, count 0 2006.257.21:28:35.44#ibcon#about to write, iclass 38, count 0 2006.257.21:28:35.44#ibcon#wrote, iclass 38, count 0 2006.257.21:28:35.44#ibcon#about to read 3, iclass 38, count 0 2006.257.21:28:35.46#ibcon#read 3, iclass 38, count 0 2006.257.21:28:35.46#ibcon#about to read 4, iclass 38, count 0 2006.257.21:28:35.46#ibcon#read 4, iclass 38, count 0 2006.257.21:28:35.46#ibcon#about to read 5, iclass 38, count 0 2006.257.21:28:35.46#ibcon#read 5, iclass 38, count 0 2006.257.21:28:35.46#ibcon#about to read 6, iclass 38, count 0 2006.257.21:28:35.46#ibcon#read 6, iclass 38, count 0 2006.257.21:28:35.46#ibcon#end of sib2, iclass 38, count 0 2006.257.21:28:35.46#ibcon#*mode == 0, iclass 38, count 0 2006.257.21:28:35.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.21:28:35.46#ibcon#[25=USB\r\n] 2006.257.21:28:35.46#ibcon#*before write, iclass 38, count 0 2006.257.21:28:35.46#ibcon#enter sib2, iclass 38, count 0 2006.257.21:28:35.46#ibcon#flushed, iclass 38, count 0 2006.257.21:28:35.46#ibcon#about to write, iclass 38, count 0 2006.257.21:28:35.46#ibcon#wrote, iclass 38, count 0 2006.257.21:28:35.46#ibcon#about to read 3, iclass 38, count 0 2006.257.21:28:35.49#ibcon#read 3, iclass 38, count 0 2006.257.21:28:35.49#ibcon#about to read 4, iclass 38, count 0 2006.257.21:28:35.49#ibcon#read 4, iclass 38, count 0 2006.257.21:28:35.49#ibcon#about to read 5, iclass 38, count 0 2006.257.21:28:35.49#ibcon#read 5, iclass 38, count 0 2006.257.21:28:35.49#ibcon#about to read 6, iclass 38, count 0 2006.257.21:28:35.49#ibcon#read 6, iclass 38, count 0 2006.257.21:28:35.49#ibcon#end of sib2, iclass 38, count 0 2006.257.21:28:35.49#ibcon#*after write, iclass 38, count 0 2006.257.21:28:35.49#ibcon#*before return 0, iclass 38, count 0 2006.257.21:28:35.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:35.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:35.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.21:28:35.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.21:28:35.49$vck44/valo=4,624.99 2006.257.21:28:35.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.21:28:35.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.21:28:35.49#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:35.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:35.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:35.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:35.49#ibcon#enter wrdev, iclass 40, count 0 2006.257.21:28:35.49#ibcon#first serial, iclass 40, count 0 2006.257.21:28:35.49#ibcon#enter sib2, iclass 40, count 0 2006.257.21:28:35.49#ibcon#flushed, iclass 40, count 0 2006.257.21:28:35.49#ibcon#about to write, iclass 40, count 0 2006.257.21:28:35.49#ibcon#wrote, iclass 40, count 0 2006.257.21:28:35.49#ibcon#about to read 3, iclass 40, count 0 2006.257.21:28:35.51#ibcon#read 3, iclass 40, count 0 2006.257.21:28:35.51#ibcon#about to read 4, iclass 40, count 0 2006.257.21:28:35.51#ibcon#read 4, iclass 40, count 0 2006.257.21:28:35.51#ibcon#about to read 5, iclass 40, count 0 2006.257.21:28:35.51#ibcon#read 5, iclass 40, count 0 2006.257.21:28:35.51#ibcon#about to read 6, iclass 40, count 0 2006.257.21:28:35.51#ibcon#read 6, iclass 40, count 0 2006.257.21:28:35.51#ibcon#end of sib2, iclass 40, count 0 2006.257.21:28:35.51#ibcon#*mode == 0, iclass 40, count 0 2006.257.21:28:35.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.21:28:35.51#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.21:28:35.51#ibcon#*before write, iclass 40, count 0 2006.257.21:28:35.51#ibcon#enter sib2, iclass 40, count 0 2006.257.21:28:35.51#ibcon#flushed, iclass 40, count 0 2006.257.21:28:35.51#ibcon#about to write, iclass 40, count 0 2006.257.21:28:35.51#ibcon#wrote, iclass 40, count 0 2006.257.21:28:35.51#ibcon#about to read 3, iclass 40, count 0 2006.257.21:28:35.55#ibcon#read 3, iclass 40, count 0 2006.257.21:28:35.55#ibcon#about to read 4, iclass 40, count 0 2006.257.21:28:35.55#ibcon#read 4, iclass 40, count 0 2006.257.21:28:35.55#ibcon#about to read 5, iclass 40, count 0 2006.257.21:28:35.55#ibcon#read 5, iclass 40, count 0 2006.257.21:28:35.55#ibcon#about to read 6, iclass 40, count 0 2006.257.21:28:35.55#ibcon#read 6, iclass 40, count 0 2006.257.21:28:35.55#ibcon#end of sib2, iclass 40, count 0 2006.257.21:28:35.55#ibcon#*after write, iclass 40, count 0 2006.257.21:28:35.55#ibcon#*before return 0, iclass 40, count 0 2006.257.21:28:35.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:35.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:35.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.21:28:35.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.21:28:35.55$vck44/va=4,7 2006.257.21:28:35.55#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.21:28:35.55#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.21:28:35.55#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:35.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:35.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:35.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:35.61#ibcon#enter wrdev, iclass 4, count 2 2006.257.21:28:35.61#ibcon#first serial, iclass 4, count 2 2006.257.21:28:35.61#ibcon#enter sib2, iclass 4, count 2 2006.257.21:28:35.61#ibcon#flushed, iclass 4, count 2 2006.257.21:28:35.61#ibcon#about to write, iclass 4, count 2 2006.257.21:28:35.61#ibcon#wrote, iclass 4, count 2 2006.257.21:28:35.61#ibcon#about to read 3, iclass 4, count 2 2006.257.21:28:35.63#ibcon#read 3, iclass 4, count 2 2006.257.21:28:35.63#ibcon#about to read 4, iclass 4, count 2 2006.257.21:28:35.63#ibcon#read 4, iclass 4, count 2 2006.257.21:28:35.63#ibcon#about to read 5, iclass 4, count 2 2006.257.21:28:35.63#ibcon#read 5, iclass 4, count 2 2006.257.21:28:35.63#ibcon#about to read 6, iclass 4, count 2 2006.257.21:28:35.63#ibcon#read 6, iclass 4, count 2 2006.257.21:28:35.63#ibcon#end of sib2, iclass 4, count 2 2006.257.21:28:35.63#ibcon#*mode == 0, iclass 4, count 2 2006.257.21:28:35.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.21:28:35.63#ibcon#[25=AT04-07\r\n] 2006.257.21:28:35.63#ibcon#*before write, iclass 4, count 2 2006.257.21:28:35.63#ibcon#enter sib2, iclass 4, count 2 2006.257.21:28:35.63#ibcon#flushed, iclass 4, count 2 2006.257.21:28:35.63#ibcon#about to write, iclass 4, count 2 2006.257.21:28:35.63#ibcon#wrote, iclass 4, count 2 2006.257.21:28:35.63#ibcon#about to read 3, iclass 4, count 2 2006.257.21:28:35.66#ibcon#read 3, iclass 4, count 2 2006.257.21:28:35.66#ibcon#about to read 4, iclass 4, count 2 2006.257.21:28:35.66#ibcon#read 4, iclass 4, count 2 2006.257.21:28:35.66#ibcon#about to read 5, iclass 4, count 2 2006.257.21:28:35.66#ibcon#read 5, iclass 4, count 2 2006.257.21:28:35.66#ibcon#about to read 6, iclass 4, count 2 2006.257.21:28:35.66#ibcon#read 6, iclass 4, count 2 2006.257.21:28:35.66#ibcon#end of sib2, iclass 4, count 2 2006.257.21:28:35.66#ibcon#*after write, iclass 4, count 2 2006.257.21:28:35.66#ibcon#*before return 0, iclass 4, count 2 2006.257.21:28:35.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:35.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:35.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.21:28:35.66#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:35.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:35.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:35.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:35.78#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:28:35.78#ibcon#first serial, iclass 4, count 0 2006.257.21:28:35.78#ibcon#enter sib2, iclass 4, count 0 2006.257.21:28:35.78#ibcon#flushed, iclass 4, count 0 2006.257.21:28:35.78#ibcon#about to write, iclass 4, count 0 2006.257.21:28:35.78#ibcon#wrote, iclass 4, count 0 2006.257.21:28:35.78#ibcon#about to read 3, iclass 4, count 0 2006.257.21:28:35.80#ibcon#read 3, iclass 4, count 0 2006.257.21:28:35.80#ibcon#about to read 4, iclass 4, count 0 2006.257.21:28:35.80#ibcon#read 4, iclass 4, count 0 2006.257.21:28:35.80#ibcon#about to read 5, iclass 4, count 0 2006.257.21:28:35.80#ibcon#read 5, iclass 4, count 0 2006.257.21:28:35.80#ibcon#about to read 6, iclass 4, count 0 2006.257.21:28:35.80#ibcon#read 6, iclass 4, count 0 2006.257.21:28:35.80#ibcon#end of sib2, iclass 4, count 0 2006.257.21:28:35.80#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:28:35.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:28:35.80#ibcon#[25=USB\r\n] 2006.257.21:28:35.80#ibcon#*before write, iclass 4, count 0 2006.257.21:28:35.80#ibcon#enter sib2, iclass 4, count 0 2006.257.21:28:35.80#ibcon#flushed, iclass 4, count 0 2006.257.21:28:35.80#ibcon#about to write, iclass 4, count 0 2006.257.21:28:35.80#ibcon#wrote, iclass 4, count 0 2006.257.21:28:35.80#ibcon#about to read 3, iclass 4, count 0 2006.257.21:28:35.83#ibcon#read 3, iclass 4, count 0 2006.257.21:28:35.83#ibcon#about to read 4, iclass 4, count 0 2006.257.21:28:35.83#ibcon#read 4, iclass 4, count 0 2006.257.21:28:35.83#ibcon#about to read 5, iclass 4, count 0 2006.257.21:28:35.83#ibcon#read 5, iclass 4, count 0 2006.257.21:28:35.83#ibcon#about to read 6, iclass 4, count 0 2006.257.21:28:35.83#ibcon#read 6, iclass 4, count 0 2006.257.21:28:35.83#ibcon#end of sib2, iclass 4, count 0 2006.257.21:28:35.83#ibcon#*after write, iclass 4, count 0 2006.257.21:28:35.83#ibcon#*before return 0, iclass 4, count 0 2006.257.21:28:35.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:35.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:35.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:28:35.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:28:35.83$vck44/valo=5,734.99 2006.257.21:28:35.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.21:28:35.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.21:28:35.83#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:35.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:35.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:35.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:35.83#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:28:35.83#ibcon#first serial, iclass 6, count 0 2006.257.21:28:35.83#ibcon#enter sib2, iclass 6, count 0 2006.257.21:28:35.83#ibcon#flushed, iclass 6, count 0 2006.257.21:28:35.83#ibcon#about to write, iclass 6, count 0 2006.257.21:28:35.83#ibcon#wrote, iclass 6, count 0 2006.257.21:28:35.83#ibcon#about to read 3, iclass 6, count 0 2006.257.21:28:35.85#ibcon#read 3, iclass 6, count 0 2006.257.21:28:35.85#ibcon#about to read 4, iclass 6, count 0 2006.257.21:28:35.85#ibcon#read 4, iclass 6, count 0 2006.257.21:28:35.85#ibcon#about to read 5, iclass 6, count 0 2006.257.21:28:35.85#ibcon#read 5, iclass 6, count 0 2006.257.21:28:35.85#ibcon#about to read 6, iclass 6, count 0 2006.257.21:28:35.85#ibcon#read 6, iclass 6, count 0 2006.257.21:28:35.85#ibcon#end of sib2, iclass 6, count 0 2006.257.21:28:35.85#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:28:35.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:28:35.85#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.21:28:35.85#ibcon#*before write, iclass 6, count 0 2006.257.21:28:35.85#ibcon#enter sib2, iclass 6, count 0 2006.257.21:28:35.85#ibcon#flushed, iclass 6, count 0 2006.257.21:28:35.85#ibcon#about to write, iclass 6, count 0 2006.257.21:28:35.85#ibcon#wrote, iclass 6, count 0 2006.257.21:28:35.85#ibcon#about to read 3, iclass 6, count 0 2006.257.21:28:35.89#ibcon#read 3, iclass 6, count 0 2006.257.21:28:35.89#ibcon#about to read 4, iclass 6, count 0 2006.257.21:28:35.89#ibcon#read 4, iclass 6, count 0 2006.257.21:28:35.89#ibcon#about to read 5, iclass 6, count 0 2006.257.21:28:35.89#ibcon#read 5, iclass 6, count 0 2006.257.21:28:35.89#ibcon#about to read 6, iclass 6, count 0 2006.257.21:28:35.89#ibcon#read 6, iclass 6, count 0 2006.257.21:28:35.89#ibcon#end of sib2, iclass 6, count 0 2006.257.21:28:35.89#ibcon#*after write, iclass 6, count 0 2006.257.21:28:35.89#ibcon#*before return 0, iclass 6, count 0 2006.257.21:28:35.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:35.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:35.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:28:35.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:28:35.89$vck44/va=5,4 2006.257.21:28:35.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.21:28:35.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.21:28:35.89#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:35.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:35.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:35.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:35.95#ibcon#enter wrdev, iclass 10, count 2 2006.257.21:28:35.95#ibcon#first serial, iclass 10, count 2 2006.257.21:28:35.95#ibcon#enter sib2, iclass 10, count 2 2006.257.21:28:35.95#ibcon#flushed, iclass 10, count 2 2006.257.21:28:35.95#ibcon#about to write, iclass 10, count 2 2006.257.21:28:35.95#ibcon#wrote, iclass 10, count 2 2006.257.21:28:35.95#ibcon#about to read 3, iclass 10, count 2 2006.257.21:28:35.97#ibcon#read 3, iclass 10, count 2 2006.257.21:28:35.97#ibcon#about to read 4, iclass 10, count 2 2006.257.21:28:35.97#ibcon#read 4, iclass 10, count 2 2006.257.21:28:35.97#ibcon#about to read 5, iclass 10, count 2 2006.257.21:28:35.97#ibcon#read 5, iclass 10, count 2 2006.257.21:28:35.97#ibcon#about to read 6, iclass 10, count 2 2006.257.21:28:35.97#ibcon#read 6, iclass 10, count 2 2006.257.21:28:35.97#ibcon#end of sib2, iclass 10, count 2 2006.257.21:28:35.97#ibcon#*mode == 0, iclass 10, count 2 2006.257.21:28:35.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.21:28:35.97#ibcon#[25=AT05-04\r\n] 2006.257.21:28:35.97#ibcon#*before write, iclass 10, count 2 2006.257.21:28:35.97#ibcon#enter sib2, iclass 10, count 2 2006.257.21:28:35.97#ibcon#flushed, iclass 10, count 2 2006.257.21:28:35.97#ibcon#about to write, iclass 10, count 2 2006.257.21:28:35.97#ibcon#wrote, iclass 10, count 2 2006.257.21:28:35.97#ibcon#about to read 3, iclass 10, count 2 2006.257.21:28:36.00#ibcon#read 3, iclass 10, count 2 2006.257.21:28:36.00#ibcon#about to read 4, iclass 10, count 2 2006.257.21:28:36.00#ibcon#read 4, iclass 10, count 2 2006.257.21:28:36.00#ibcon#about to read 5, iclass 10, count 2 2006.257.21:28:36.00#ibcon#read 5, iclass 10, count 2 2006.257.21:28:36.00#ibcon#about to read 6, iclass 10, count 2 2006.257.21:28:36.00#ibcon#read 6, iclass 10, count 2 2006.257.21:28:36.00#ibcon#end of sib2, iclass 10, count 2 2006.257.21:28:36.00#ibcon#*after write, iclass 10, count 2 2006.257.21:28:36.00#ibcon#*before return 0, iclass 10, count 2 2006.257.21:28:36.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:36.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:36.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.21:28:36.00#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:36.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:36.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:36.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:36.12#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:28:36.12#ibcon#first serial, iclass 10, count 0 2006.257.21:28:36.12#ibcon#enter sib2, iclass 10, count 0 2006.257.21:28:36.12#ibcon#flushed, iclass 10, count 0 2006.257.21:28:36.12#ibcon#about to write, iclass 10, count 0 2006.257.21:28:36.12#ibcon#wrote, iclass 10, count 0 2006.257.21:28:36.12#ibcon#about to read 3, iclass 10, count 0 2006.257.21:28:36.14#ibcon#read 3, iclass 10, count 0 2006.257.21:28:36.14#ibcon#about to read 4, iclass 10, count 0 2006.257.21:28:36.14#ibcon#read 4, iclass 10, count 0 2006.257.21:28:36.14#ibcon#about to read 5, iclass 10, count 0 2006.257.21:28:36.14#ibcon#read 5, iclass 10, count 0 2006.257.21:28:36.14#ibcon#about to read 6, iclass 10, count 0 2006.257.21:28:36.14#ibcon#read 6, iclass 10, count 0 2006.257.21:28:36.14#ibcon#end of sib2, iclass 10, count 0 2006.257.21:28:36.14#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:28:36.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:28:36.14#ibcon#[25=USB\r\n] 2006.257.21:28:36.14#ibcon#*before write, iclass 10, count 0 2006.257.21:28:36.14#ibcon#enter sib2, iclass 10, count 0 2006.257.21:28:36.14#ibcon#flushed, iclass 10, count 0 2006.257.21:28:36.14#ibcon#about to write, iclass 10, count 0 2006.257.21:28:36.14#ibcon#wrote, iclass 10, count 0 2006.257.21:28:36.14#ibcon#about to read 3, iclass 10, count 0 2006.257.21:28:36.17#ibcon#read 3, iclass 10, count 0 2006.257.21:28:36.17#ibcon#about to read 4, iclass 10, count 0 2006.257.21:28:36.17#ibcon#read 4, iclass 10, count 0 2006.257.21:28:36.17#ibcon#about to read 5, iclass 10, count 0 2006.257.21:28:36.17#ibcon#read 5, iclass 10, count 0 2006.257.21:28:36.17#ibcon#about to read 6, iclass 10, count 0 2006.257.21:28:36.17#ibcon#read 6, iclass 10, count 0 2006.257.21:28:36.17#ibcon#end of sib2, iclass 10, count 0 2006.257.21:28:36.17#ibcon#*after write, iclass 10, count 0 2006.257.21:28:36.17#ibcon#*before return 0, iclass 10, count 0 2006.257.21:28:36.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:36.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:36.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:28:36.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:28:36.17$vck44/valo=6,814.99 2006.257.21:28:36.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.21:28:36.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.21:28:36.17#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:36.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:28:36.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:28:36.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:28:36.17#ibcon#enter wrdev, iclass 13, count 0 2006.257.21:28:36.17#ibcon#first serial, iclass 13, count 0 2006.257.21:28:36.17#ibcon#enter sib2, iclass 13, count 0 2006.257.21:28:36.17#ibcon#flushed, iclass 13, count 0 2006.257.21:28:36.17#ibcon#about to write, iclass 13, count 0 2006.257.21:28:36.17#ibcon#wrote, iclass 13, count 0 2006.257.21:28:36.17#ibcon#about to read 3, iclass 13, count 0 2006.257.21:28:36.18#abcon#<5=/14 1.1 2.9 17.81 951015.5\r\n> 2006.257.21:28:36.19#ibcon#read 3, iclass 13, count 0 2006.257.21:28:36.19#ibcon#about to read 4, iclass 13, count 0 2006.257.21:28:36.19#ibcon#read 4, iclass 13, count 0 2006.257.21:28:36.19#ibcon#about to read 5, iclass 13, count 0 2006.257.21:28:36.19#ibcon#read 5, iclass 13, count 0 2006.257.21:28:36.19#ibcon#about to read 6, iclass 13, count 0 2006.257.21:28:36.19#ibcon#read 6, iclass 13, count 0 2006.257.21:28:36.19#ibcon#end of sib2, iclass 13, count 0 2006.257.21:28:36.19#ibcon#*mode == 0, iclass 13, count 0 2006.257.21:28:36.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.21:28:36.19#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.21:28:36.19#ibcon#*before write, iclass 13, count 0 2006.257.21:28:36.19#ibcon#enter sib2, iclass 13, count 0 2006.257.21:28:36.19#ibcon#flushed, iclass 13, count 0 2006.257.21:28:36.19#ibcon#about to write, iclass 13, count 0 2006.257.21:28:36.19#ibcon#wrote, iclass 13, count 0 2006.257.21:28:36.19#ibcon#about to read 3, iclass 13, count 0 2006.257.21:28:36.20#abcon#{5=INTERFACE CLEAR} 2006.257.21:28:36.23#ibcon#read 3, iclass 13, count 0 2006.257.21:28:36.23#ibcon#about to read 4, iclass 13, count 0 2006.257.21:28:36.23#ibcon#read 4, iclass 13, count 0 2006.257.21:28:36.23#ibcon#about to read 5, iclass 13, count 0 2006.257.21:28:36.23#ibcon#read 5, iclass 13, count 0 2006.257.21:28:36.23#ibcon#about to read 6, iclass 13, count 0 2006.257.21:28:36.23#ibcon#read 6, iclass 13, count 0 2006.257.21:28:36.23#ibcon#end of sib2, iclass 13, count 0 2006.257.21:28:36.23#ibcon#*after write, iclass 13, count 0 2006.257.21:28:36.23#ibcon#*before return 0, iclass 13, count 0 2006.257.21:28:36.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:28:36.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:28:36.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.21:28:36.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.21:28:36.23$vck44/va=6,4 2006.257.21:28:36.23#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.21:28:36.23#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.21:28:36.23#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:36.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:28:36.26#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:28:36.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:28:36.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:28:36.29#ibcon#enter wrdev, iclass 17, count 2 2006.257.21:28:36.29#ibcon#first serial, iclass 17, count 2 2006.257.21:28:36.29#ibcon#enter sib2, iclass 17, count 2 2006.257.21:28:36.29#ibcon#flushed, iclass 17, count 2 2006.257.21:28:36.29#ibcon#about to write, iclass 17, count 2 2006.257.21:28:36.29#ibcon#wrote, iclass 17, count 2 2006.257.21:28:36.29#ibcon#about to read 3, iclass 17, count 2 2006.257.21:28:36.31#ibcon#read 3, iclass 17, count 2 2006.257.21:28:36.31#ibcon#about to read 4, iclass 17, count 2 2006.257.21:28:36.31#ibcon#read 4, iclass 17, count 2 2006.257.21:28:36.31#ibcon#about to read 5, iclass 17, count 2 2006.257.21:28:36.31#ibcon#read 5, iclass 17, count 2 2006.257.21:28:36.31#ibcon#about to read 6, iclass 17, count 2 2006.257.21:28:36.31#ibcon#read 6, iclass 17, count 2 2006.257.21:28:36.31#ibcon#end of sib2, iclass 17, count 2 2006.257.21:28:36.31#ibcon#*mode == 0, iclass 17, count 2 2006.257.21:28:36.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.21:28:36.31#ibcon#[25=AT06-04\r\n] 2006.257.21:28:36.31#ibcon#*before write, iclass 17, count 2 2006.257.21:28:36.31#ibcon#enter sib2, iclass 17, count 2 2006.257.21:28:36.31#ibcon#flushed, iclass 17, count 2 2006.257.21:28:36.31#ibcon#about to write, iclass 17, count 2 2006.257.21:28:36.31#ibcon#wrote, iclass 17, count 2 2006.257.21:28:36.31#ibcon#about to read 3, iclass 17, count 2 2006.257.21:28:36.34#ibcon#read 3, iclass 17, count 2 2006.257.21:28:36.34#ibcon#about to read 4, iclass 17, count 2 2006.257.21:28:36.34#ibcon#read 4, iclass 17, count 2 2006.257.21:28:36.34#ibcon#about to read 5, iclass 17, count 2 2006.257.21:28:36.34#ibcon#read 5, iclass 17, count 2 2006.257.21:28:36.34#ibcon#about to read 6, iclass 17, count 2 2006.257.21:28:36.34#ibcon#read 6, iclass 17, count 2 2006.257.21:28:36.34#ibcon#end of sib2, iclass 17, count 2 2006.257.21:28:36.34#ibcon#*after write, iclass 17, count 2 2006.257.21:28:36.34#ibcon#*before return 0, iclass 17, count 2 2006.257.21:28:36.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:28:36.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:28:36.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.21:28:36.34#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:36.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:28:36.46#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:28:36.46#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:28:36.46#ibcon#enter wrdev, iclass 17, count 0 2006.257.21:28:36.46#ibcon#first serial, iclass 17, count 0 2006.257.21:28:36.46#ibcon#enter sib2, iclass 17, count 0 2006.257.21:28:36.46#ibcon#flushed, iclass 17, count 0 2006.257.21:28:36.46#ibcon#about to write, iclass 17, count 0 2006.257.21:28:36.46#ibcon#wrote, iclass 17, count 0 2006.257.21:28:36.46#ibcon#about to read 3, iclass 17, count 0 2006.257.21:28:36.48#ibcon#read 3, iclass 17, count 0 2006.257.21:28:36.48#ibcon#about to read 4, iclass 17, count 0 2006.257.21:28:36.48#ibcon#read 4, iclass 17, count 0 2006.257.21:28:36.48#ibcon#about to read 5, iclass 17, count 0 2006.257.21:28:36.48#ibcon#read 5, iclass 17, count 0 2006.257.21:28:36.48#ibcon#about to read 6, iclass 17, count 0 2006.257.21:28:36.48#ibcon#read 6, iclass 17, count 0 2006.257.21:28:36.48#ibcon#end of sib2, iclass 17, count 0 2006.257.21:28:36.48#ibcon#*mode == 0, iclass 17, count 0 2006.257.21:28:36.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.21:28:36.48#ibcon#[25=USB\r\n] 2006.257.21:28:36.48#ibcon#*before write, iclass 17, count 0 2006.257.21:28:36.48#ibcon#enter sib2, iclass 17, count 0 2006.257.21:28:36.48#ibcon#flushed, iclass 17, count 0 2006.257.21:28:36.48#ibcon#about to write, iclass 17, count 0 2006.257.21:28:36.48#ibcon#wrote, iclass 17, count 0 2006.257.21:28:36.48#ibcon#about to read 3, iclass 17, count 0 2006.257.21:28:36.51#ibcon#read 3, iclass 17, count 0 2006.257.21:28:36.51#ibcon#about to read 4, iclass 17, count 0 2006.257.21:28:36.51#ibcon#read 4, iclass 17, count 0 2006.257.21:28:36.51#ibcon#about to read 5, iclass 17, count 0 2006.257.21:28:36.51#ibcon#read 5, iclass 17, count 0 2006.257.21:28:36.51#ibcon#about to read 6, iclass 17, count 0 2006.257.21:28:36.51#ibcon#read 6, iclass 17, count 0 2006.257.21:28:36.51#ibcon#end of sib2, iclass 17, count 0 2006.257.21:28:36.51#ibcon#*after write, iclass 17, count 0 2006.257.21:28:36.51#ibcon#*before return 0, iclass 17, count 0 2006.257.21:28:36.51#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:28:36.51#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:28:36.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.21:28:36.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.21:28:36.51$vck44/valo=7,864.99 2006.257.21:28:36.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.21:28:36.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.21:28:36.51#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:36.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:36.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:36.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:36.51#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:28:36.51#ibcon#first serial, iclass 20, count 0 2006.257.21:28:36.51#ibcon#enter sib2, iclass 20, count 0 2006.257.21:28:36.51#ibcon#flushed, iclass 20, count 0 2006.257.21:28:36.51#ibcon#about to write, iclass 20, count 0 2006.257.21:28:36.51#ibcon#wrote, iclass 20, count 0 2006.257.21:28:36.51#ibcon#about to read 3, iclass 20, count 0 2006.257.21:28:36.53#ibcon#read 3, iclass 20, count 0 2006.257.21:28:36.53#ibcon#about to read 4, iclass 20, count 0 2006.257.21:28:36.53#ibcon#read 4, iclass 20, count 0 2006.257.21:28:36.53#ibcon#about to read 5, iclass 20, count 0 2006.257.21:28:36.53#ibcon#read 5, iclass 20, count 0 2006.257.21:28:36.53#ibcon#about to read 6, iclass 20, count 0 2006.257.21:28:36.53#ibcon#read 6, iclass 20, count 0 2006.257.21:28:36.53#ibcon#end of sib2, iclass 20, count 0 2006.257.21:28:36.53#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:28:36.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:28:36.53#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.21:28:36.53#ibcon#*before write, iclass 20, count 0 2006.257.21:28:36.53#ibcon#enter sib2, iclass 20, count 0 2006.257.21:28:36.53#ibcon#flushed, iclass 20, count 0 2006.257.21:28:36.53#ibcon#about to write, iclass 20, count 0 2006.257.21:28:36.53#ibcon#wrote, iclass 20, count 0 2006.257.21:28:36.53#ibcon#about to read 3, iclass 20, count 0 2006.257.21:28:36.57#ibcon#read 3, iclass 20, count 0 2006.257.21:28:36.57#ibcon#about to read 4, iclass 20, count 0 2006.257.21:28:36.57#ibcon#read 4, iclass 20, count 0 2006.257.21:28:36.57#ibcon#about to read 5, iclass 20, count 0 2006.257.21:28:36.57#ibcon#read 5, iclass 20, count 0 2006.257.21:28:36.57#ibcon#about to read 6, iclass 20, count 0 2006.257.21:28:36.57#ibcon#read 6, iclass 20, count 0 2006.257.21:28:36.57#ibcon#end of sib2, iclass 20, count 0 2006.257.21:28:36.57#ibcon#*after write, iclass 20, count 0 2006.257.21:28:36.57#ibcon#*before return 0, iclass 20, count 0 2006.257.21:28:36.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:36.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:36.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:28:36.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:28:36.57$vck44/va=7,4 2006.257.21:28:36.57#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.21:28:36.57#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.21:28:36.57#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:36.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:36.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:36.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:36.63#ibcon#enter wrdev, iclass 22, count 2 2006.257.21:28:36.63#ibcon#first serial, iclass 22, count 2 2006.257.21:28:36.63#ibcon#enter sib2, iclass 22, count 2 2006.257.21:28:36.63#ibcon#flushed, iclass 22, count 2 2006.257.21:28:36.63#ibcon#about to write, iclass 22, count 2 2006.257.21:28:36.63#ibcon#wrote, iclass 22, count 2 2006.257.21:28:36.63#ibcon#about to read 3, iclass 22, count 2 2006.257.21:28:36.65#ibcon#read 3, iclass 22, count 2 2006.257.21:28:36.65#ibcon#about to read 4, iclass 22, count 2 2006.257.21:28:36.65#ibcon#read 4, iclass 22, count 2 2006.257.21:28:36.65#ibcon#about to read 5, iclass 22, count 2 2006.257.21:28:36.65#ibcon#read 5, iclass 22, count 2 2006.257.21:28:36.65#ibcon#about to read 6, iclass 22, count 2 2006.257.21:28:36.65#ibcon#read 6, iclass 22, count 2 2006.257.21:28:36.65#ibcon#end of sib2, iclass 22, count 2 2006.257.21:28:36.65#ibcon#*mode == 0, iclass 22, count 2 2006.257.21:28:36.65#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.21:28:36.65#ibcon#[25=AT07-04\r\n] 2006.257.21:28:36.65#ibcon#*before write, iclass 22, count 2 2006.257.21:28:36.65#ibcon#enter sib2, iclass 22, count 2 2006.257.21:28:36.65#ibcon#flushed, iclass 22, count 2 2006.257.21:28:36.65#ibcon#about to write, iclass 22, count 2 2006.257.21:28:36.65#ibcon#wrote, iclass 22, count 2 2006.257.21:28:36.65#ibcon#about to read 3, iclass 22, count 2 2006.257.21:28:36.68#ibcon#read 3, iclass 22, count 2 2006.257.21:28:36.68#ibcon#about to read 4, iclass 22, count 2 2006.257.21:28:36.68#ibcon#read 4, iclass 22, count 2 2006.257.21:28:36.68#ibcon#about to read 5, iclass 22, count 2 2006.257.21:28:36.68#ibcon#read 5, iclass 22, count 2 2006.257.21:28:36.68#ibcon#about to read 6, iclass 22, count 2 2006.257.21:28:36.68#ibcon#read 6, iclass 22, count 2 2006.257.21:28:36.68#ibcon#end of sib2, iclass 22, count 2 2006.257.21:28:36.68#ibcon#*after write, iclass 22, count 2 2006.257.21:28:36.68#ibcon#*before return 0, iclass 22, count 2 2006.257.21:28:36.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:36.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:36.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.21:28:36.68#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:36.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:36.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:36.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:36.80#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:28:36.80#ibcon#first serial, iclass 22, count 0 2006.257.21:28:36.80#ibcon#enter sib2, iclass 22, count 0 2006.257.21:28:36.80#ibcon#flushed, iclass 22, count 0 2006.257.21:28:36.80#ibcon#about to write, iclass 22, count 0 2006.257.21:28:36.80#ibcon#wrote, iclass 22, count 0 2006.257.21:28:36.80#ibcon#about to read 3, iclass 22, count 0 2006.257.21:28:36.82#ibcon#read 3, iclass 22, count 0 2006.257.21:28:36.82#ibcon#about to read 4, iclass 22, count 0 2006.257.21:28:36.82#ibcon#read 4, iclass 22, count 0 2006.257.21:28:36.82#ibcon#about to read 5, iclass 22, count 0 2006.257.21:28:36.82#ibcon#read 5, iclass 22, count 0 2006.257.21:28:36.82#ibcon#about to read 6, iclass 22, count 0 2006.257.21:28:36.82#ibcon#read 6, iclass 22, count 0 2006.257.21:28:36.82#ibcon#end of sib2, iclass 22, count 0 2006.257.21:28:36.82#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:28:36.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:28:36.82#ibcon#[25=USB\r\n] 2006.257.21:28:36.82#ibcon#*before write, iclass 22, count 0 2006.257.21:28:36.82#ibcon#enter sib2, iclass 22, count 0 2006.257.21:28:36.82#ibcon#flushed, iclass 22, count 0 2006.257.21:28:36.82#ibcon#about to write, iclass 22, count 0 2006.257.21:28:36.82#ibcon#wrote, iclass 22, count 0 2006.257.21:28:36.82#ibcon#about to read 3, iclass 22, count 0 2006.257.21:28:36.85#ibcon#read 3, iclass 22, count 0 2006.257.21:28:36.85#ibcon#about to read 4, iclass 22, count 0 2006.257.21:28:36.85#ibcon#read 4, iclass 22, count 0 2006.257.21:28:36.85#ibcon#about to read 5, iclass 22, count 0 2006.257.21:28:36.85#ibcon#read 5, iclass 22, count 0 2006.257.21:28:36.85#ibcon#about to read 6, iclass 22, count 0 2006.257.21:28:36.85#ibcon#read 6, iclass 22, count 0 2006.257.21:28:36.85#ibcon#end of sib2, iclass 22, count 0 2006.257.21:28:36.85#ibcon#*after write, iclass 22, count 0 2006.257.21:28:36.85#ibcon#*before return 0, iclass 22, count 0 2006.257.21:28:36.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:36.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:36.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:28:36.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:28:36.85$vck44/valo=8,884.99 2006.257.21:28:36.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.21:28:36.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.21:28:36.85#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:36.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:36.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:36.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:36.85#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:28:36.85#ibcon#first serial, iclass 24, count 0 2006.257.21:28:36.85#ibcon#enter sib2, iclass 24, count 0 2006.257.21:28:36.85#ibcon#flushed, iclass 24, count 0 2006.257.21:28:36.85#ibcon#about to write, iclass 24, count 0 2006.257.21:28:36.85#ibcon#wrote, iclass 24, count 0 2006.257.21:28:36.85#ibcon#about to read 3, iclass 24, count 0 2006.257.21:28:36.87#ibcon#read 3, iclass 24, count 0 2006.257.21:28:36.87#ibcon#about to read 4, iclass 24, count 0 2006.257.21:28:36.87#ibcon#read 4, iclass 24, count 0 2006.257.21:28:36.87#ibcon#about to read 5, iclass 24, count 0 2006.257.21:28:36.87#ibcon#read 5, iclass 24, count 0 2006.257.21:28:36.87#ibcon#about to read 6, iclass 24, count 0 2006.257.21:28:36.87#ibcon#read 6, iclass 24, count 0 2006.257.21:28:36.87#ibcon#end of sib2, iclass 24, count 0 2006.257.21:28:36.87#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:28:36.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:28:36.87#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.21:28:36.87#ibcon#*before write, iclass 24, count 0 2006.257.21:28:36.87#ibcon#enter sib2, iclass 24, count 0 2006.257.21:28:36.87#ibcon#flushed, iclass 24, count 0 2006.257.21:28:36.87#ibcon#about to write, iclass 24, count 0 2006.257.21:28:36.87#ibcon#wrote, iclass 24, count 0 2006.257.21:28:36.87#ibcon#about to read 3, iclass 24, count 0 2006.257.21:28:36.91#ibcon#read 3, iclass 24, count 0 2006.257.21:28:36.91#ibcon#about to read 4, iclass 24, count 0 2006.257.21:28:36.91#ibcon#read 4, iclass 24, count 0 2006.257.21:28:36.91#ibcon#about to read 5, iclass 24, count 0 2006.257.21:28:36.91#ibcon#read 5, iclass 24, count 0 2006.257.21:28:36.91#ibcon#about to read 6, iclass 24, count 0 2006.257.21:28:36.91#ibcon#read 6, iclass 24, count 0 2006.257.21:28:36.91#ibcon#end of sib2, iclass 24, count 0 2006.257.21:28:36.91#ibcon#*after write, iclass 24, count 0 2006.257.21:28:36.91#ibcon#*before return 0, iclass 24, count 0 2006.257.21:28:36.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:36.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:36.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:28:36.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:28:36.91$vck44/va=8,4 2006.257.21:28:36.91#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.21:28:36.91#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.21:28:36.91#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:36.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:28:36.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:28:36.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:28:36.97#ibcon#enter wrdev, iclass 26, count 2 2006.257.21:28:36.97#ibcon#first serial, iclass 26, count 2 2006.257.21:28:36.97#ibcon#enter sib2, iclass 26, count 2 2006.257.21:28:36.97#ibcon#flushed, iclass 26, count 2 2006.257.21:28:36.97#ibcon#about to write, iclass 26, count 2 2006.257.21:28:36.97#ibcon#wrote, iclass 26, count 2 2006.257.21:28:36.97#ibcon#about to read 3, iclass 26, count 2 2006.257.21:28:36.99#ibcon#read 3, iclass 26, count 2 2006.257.21:28:36.99#ibcon#about to read 4, iclass 26, count 2 2006.257.21:28:36.99#ibcon#read 4, iclass 26, count 2 2006.257.21:28:36.99#ibcon#about to read 5, iclass 26, count 2 2006.257.21:28:36.99#ibcon#read 5, iclass 26, count 2 2006.257.21:28:36.99#ibcon#about to read 6, iclass 26, count 2 2006.257.21:28:36.99#ibcon#read 6, iclass 26, count 2 2006.257.21:28:36.99#ibcon#end of sib2, iclass 26, count 2 2006.257.21:28:36.99#ibcon#*mode == 0, iclass 26, count 2 2006.257.21:28:36.99#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.21:28:36.99#ibcon#[25=AT08-04\r\n] 2006.257.21:28:36.99#ibcon#*before write, iclass 26, count 2 2006.257.21:28:36.99#ibcon#enter sib2, iclass 26, count 2 2006.257.21:28:36.99#ibcon#flushed, iclass 26, count 2 2006.257.21:28:36.99#ibcon#about to write, iclass 26, count 2 2006.257.21:28:36.99#ibcon#wrote, iclass 26, count 2 2006.257.21:28:36.99#ibcon#about to read 3, iclass 26, count 2 2006.257.21:28:37.02#ibcon#read 3, iclass 26, count 2 2006.257.21:28:37.02#ibcon#about to read 4, iclass 26, count 2 2006.257.21:28:37.02#ibcon#read 4, iclass 26, count 2 2006.257.21:28:37.02#ibcon#about to read 5, iclass 26, count 2 2006.257.21:28:37.02#ibcon#read 5, iclass 26, count 2 2006.257.21:28:37.02#ibcon#about to read 6, iclass 26, count 2 2006.257.21:28:37.02#ibcon#read 6, iclass 26, count 2 2006.257.21:28:37.02#ibcon#end of sib2, iclass 26, count 2 2006.257.21:28:37.02#ibcon#*after write, iclass 26, count 2 2006.257.21:28:37.02#ibcon#*before return 0, iclass 26, count 2 2006.257.21:28:37.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:28:37.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:28:37.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.21:28:37.02#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:37.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:28:37.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:28:37.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:28:37.14#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:28:37.14#ibcon#first serial, iclass 26, count 0 2006.257.21:28:37.14#ibcon#enter sib2, iclass 26, count 0 2006.257.21:28:37.14#ibcon#flushed, iclass 26, count 0 2006.257.21:28:37.14#ibcon#about to write, iclass 26, count 0 2006.257.21:28:37.14#ibcon#wrote, iclass 26, count 0 2006.257.21:28:37.14#ibcon#about to read 3, iclass 26, count 0 2006.257.21:28:37.16#ibcon#read 3, iclass 26, count 0 2006.257.21:28:37.16#ibcon#about to read 4, iclass 26, count 0 2006.257.21:28:37.16#ibcon#read 4, iclass 26, count 0 2006.257.21:28:37.16#ibcon#about to read 5, iclass 26, count 0 2006.257.21:28:37.16#ibcon#read 5, iclass 26, count 0 2006.257.21:28:37.16#ibcon#about to read 6, iclass 26, count 0 2006.257.21:28:37.16#ibcon#read 6, iclass 26, count 0 2006.257.21:28:37.16#ibcon#end of sib2, iclass 26, count 0 2006.257.21:28:37.16#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:28:37.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:28:37.16#ibcon#[25=USB\r\n] 2006.257.21:28:37.16#ibcon#*before write, iclass 26, count 0 2006.257.21:28:37.16#ibcon#enter sib2, iclass 26, count 0 2006.257.21:28:37.16#ibcon#flushed, iclass 26, count 0 2006.257.21:28:37.16#ibcon#about to write, iclass 26, count 0 2006.257.21:28:37.16#ibcon#wrote, iclass 26, count 0 2006.257.21:28:37.16#ibcon#about to read 3, iclass 26, count 0 2006.257.21:28:37.19#ibcon#read 3, iclass 26, count 0 2006.257.21:28:37.19#ibcon#about to read 4, iclass 26, count 0 2006.257.21:28:37.19#ibcon#read 4, iclass 26, count 0 2006.257.21:28:37.19#ibcon#about to read 5, iclass 26, count 0 2006.257.21:28:37.19#ibcon#read 5, iclass 26, count 0 2006.257.21:28:37.19#ibcon#about to read 6, iclass 26, count 0 2006.257.21:28:37.19#ibcon#read 6, iclass 26, count 0 2006.257.21:28:37.19#ibcon#end of sib2, iclass 26, count 0 2006.257.21:28:37.19#ibcon#*after write, iclass 26, count 0 2006.257.21:28:37.19#ibcon#*before return 0, iclass 26, count 0 2006.257.21:28:37.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:28:37.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:28:37.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:28:37.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:28:37.19$vck44/vblo=1,629.99 2006.257.21:28:37.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.21:28:37.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.21:28:37.19#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:37.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:37.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:37.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:37.19#ibcon#enter wrdev, iclass 28, count 0 2006.257.21:28:37.19#ibcon#first serial, iclass 28, count 0 2006.257.21:28:37.19#ibcon#enter sib2, iclass 28, count 0 2006.257.21:28:37.19#ibcon#flushed, iclass 28, count 0 2006.257.21:28:37.19#ibcon#about to write, iclass 28, count 0 2006.257.21:28:37.19#ibcon#wrote, iclass 28, count 0 2006.257.21:28:37.19#ibcon#about to read 3, iclass 28, count 0 2006.257.21:28:37.21#ibcon#read 3, iclass 28, count 0 2006.257.21:28:37.21#ibcon#about to read 4, iclass 28, count 0 2006.257.21:28:37.21#ibcon#read 4, iclass 28, count 0 2006.257.21:28:37.21#ibcon#about to read 5, iclass 28, count 0 2006.257.21:28:37.21#ibcon#read 5, iclass 28, count 0 2006.257.21:28:37.21#ibcon#about to read 6, iclass 28, count 0 2006.257.21:28:37.21#ibcon#read 6, iclass 28, count 0 2006.257.21:28:37.21#ibcon#end of sib2, iclass 28, count 0 2006.257.21:28:37.21#ibcon#*mode == 0, iclass 28, count 0 2006.257.21:28:37.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.21:28:37.21#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.21:28:37.21#ibcon#*before write, iclass 28, count 0 2006.257.21:28:37.21#ibcon#enter sib2, iclass 28, count 0 2006.257.21:28:37.21#ibcon#flushed, iclass 28, count 0 2006.257.21:28:37.21#ibcon#about to write, iclass 28, count 0 2006.257.21:28:37.21#ibcon#wrote, iclass 28, count 0 2006.257.21:28:37.21#ibcon#about to read 3, iclass 28, count 0 2006.257.21:28:37.25#ibcon#read 3, iclass 28, count 0 2006.257.21:28:37.25#ibcon#about to read 4, iclass 28, count 0 2006.257.21:28:37.25#ibcon#read 4, iclass 28, count 0 2006.257.21:28:37.25#ibcon#about to read 5, iclass 28, count 0 2006.257.21:28:37.25#ibcon#read 5, iclass 28, count 0 2006.257.21:28:37.25#ibcon#about to read 6, iclass 28, count 0 2006.257.21:28:37.25#ibcon#read 6, iclass 28, count 0 2006.257.21:28:37.25#ibcon#end of sib2, iclass 28, count 0 2006.257.21:28:37.25#ibcon#*after write, iclass 28, count 0 2006.257.21:28:37.25#ibcon#*before return 0, iclass 28, count 0 2006.257.21:28:37.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:37.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:28:37.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.21:28:37.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.21:28:37.25$vck44/vb=1,4 2006.257.21:28:37.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.21:28:37.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.21:28:37.25#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:37.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:37.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:37.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:37.25#ibcon#enter wrdev, iclass 30, count 2 2006.257.21:28:37.25#ibcon#first serial, iclass 30, count 2 2006.257.21:28:37.25#ibcon#enter sib2, iclass 30, count 2 2006.257.21:28:37.25#ibcon#flushed, iclass 30, count 2 2006.257.21:28:37.25#ibcon#about to write, iclass 30, count 2 2006.257.21:28:37.25#ibcon#wrote, iclass 30, count 2 2006.257.21:28:37.25#ibcon#about to read 3, iclass 30, count 2 2006.257.21:28:37.27#ibcon#read 3, iclass 30, count 2 2006.257.21:28:37.27#ibcon#about to read 4, iclass 30, count 2 2006.257.21:28:37.27#ibcon#read 4, iclass 30, count 2 2006.257.21:28:37.27#ibcon#about to read 5, iclass 30, count 2 2006.257.21:28:37.27#ibcon#read 5, iclass 30, count 2 2006.257.21:28:37.27#ibcon#about to read 6, iclass 30, count 2 2006.257.21:28:37.27#ibcon#read 6, iclass 30, count 2 2006.257.21:28:37.27#ibcon#end of sib2, iclass 30, count 2 2006.257.21:28:37.27#ibcon#*mode == 0, iclass 30, count 2 2006.257.21:28:37.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.21:28:37.27#ibcon#[27=AT01-04\r\n] 2006.257.21:28:37.27#ibcon#*before write, iclass 30, count 2 2006.257.21:28:37.27#ibcon#enter sib2, iclass 30, count 2 2006.257.21:28:37.27#ibcon#flushed, iclass 30, count 2 2006.257.21:28:37.27#ibcon#about to write, iclass 30, count 2 2006.257.21:28:37.27#ibcon#wrote, iclass 30, count 2 2006.257.21:28:37.27#ibcon#about to read 3, iclass 30, count 2 2006.257.21:28:37.30#ibcon#read 3, iclass 30, count 2 2006.257.21:28:37.30#ibcon#about to read 4, iclass 30, count 2 2006.257.21:28:37.30#ibcon#read 4, iclass 30, count 2 2006.257.21:28:37.30#ibcon#about to read 5, iclass 30, count 2 2006.257.21:28:37.30#ibcon#read 5, iclass 30, count 2 2006.257.21:28:37.30#ibcon#about to read 6, iclass 30, count 2 2006.257.21:28:37.30#ibcon#read 6, iclass 30, count 2 2006.257.21:28:37.30#ibcon#end of sib2, iclass 30, count 2 2006.257.21:28:37.30#ibcon#*after write, iclass 30, count 2 2006.257.21:28:37.30#ibcon#*before return 0, iclass 30, count 2 2006.257.21:28:37.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:37.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:28:37.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.21:28:37.30#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:37.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:37.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:37.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:37.42#ibcon#enter wrdev, iclass 30, count 0 2006.257.21:28:37.42#ibcon#first serial, iclass 30, count 0 2006.257.21:28:37.42#ibcon#enter sib2, iclass 30, count 0 2006.257.21:28:37.42#ibcon#flushed, iclass 30, count 0 2006.257.21:28:37.42#ibcon#about to write, iclass 30, count 0 2006.257.21:28:37.42#ibcon#wrote, iclass 30, count 0 2006.257.21:28:37.42#ibcon#about to read 3, iclass 30, count 0 2006.257.21:28:37.44#ibcon#read 3, iclass 30, count 0 2006.257.21:28:37.44#ibcon#about to read 4, iclass 30, count 0 2006.257.21:28:37.44#ibcon#read 4, iclass 30, count 0 2006.257.21:28:37.44#ibcon#about to read 5, iclass 30, count 0 2006.257.21:28:37.44#ibcon#read 5, iclass 30, count 0 2006.257.21:28:37.44#ibcon#about to read 6, iclass 30, count 0 2006.257.21:28:37.44#ibcon#read 6, iclass 30, count 0 2006.257.21:28:37.44#ibcon#end of sib2, iclass 30, count 0 2006.257.21:28:37.44#ibcon#*mode == 0, iclass 30, count 0 2006.257.21:28:37.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.21:28:37.44#ibcon#[27=USB\r\n] 2006.257.21:28:37.44#ibcon#*before write, iclass 30, count 0 2006.257.21:28:37.44#ibcon#enter sib2, iclass 30, count 0 2006.257.21:28:37.44#ibcon#flushed, iclass 30, count 0 2006.257.21:28:37.44#ibcon#about to write, iclass 30, count 0 2006.257.21:28:37.44#ibcon#wrote, iclass 30, count 0 2006.257.21:28:37.44#ibcon#about to read 3, iclass 30, count 0 2006.257.21:28:37.47#ibcon#read 3, iclass 30, count 0 2006.257.21:28:37.47#ibcon#about to read 4, iclass 30, count 0 2006.257.21:28:37.47#ibcon#read 4, iclass 30, count 0 2006.257.21:28:37.47#ibcon#about to read 5, iclass 30, count 0 2006.257.21:28:37.47#ibcon#read 5, iclass 30, count 0 2006.257.21:28:37.47#ibcon#about to read 6, iclass 30, count 0 2006.257.21:28:37.47#ibcon#read 6, iclass 30, count 0 2006.257.21:28:37.47#ibcon#end of sib2, iclass 30, count 0 2006.257.21:28:37.47#ibcon#*after write, iclass 30, count 0 2006.257.21:28:37.47#ibcon#*before return 0, iclass 30, count 0 2006.257.21:28:37.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:37.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:28:37.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.21:28:37.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.21:28:37.47$vck44/vblo=2,634.99 2006.257.21:28:37.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.21:28:37.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.21:28:37.47#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:37.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:37.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:37.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:37.47#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:28:37.47#ibcon#first serial, iclass 32, count 0 2006.257.21:28:37.47#ibcon#enter sib2, iclass 32, count 0 2006.257.21:28:37.47#ibcon#flushed, iclass 32, count 0 2006.257.21:28:37.47#ibcon#about to write, iclass 32, count 0 2006.257.21:28:37.47#ibcon#wrote, iclass 32, count 0 2006.257.21:28:37.47#ibcon#about to read 3, iclass 32, count 0 2006.257.21:28:37.49#ibcon#read 3, iclass 32, count 0 2006.257.21:28:37.49#ibcon#about to read 4, iclass 32, count 0 2006.257.21:28:37.49#ibcon#read 4, iclass 32, count 0 2006.257.21:28:37.49#ibcon#about to read 5, iclass 32, count 0 2006.257.21:28:37.49#ibcon#read 5, iclass 32, count 0 2006.257.21:28:37.49#ibcon#about to read 6, iclass 32, count 0 2006.257.21:28:37.49#ibcon#read 6, iclass 32, count 0 2006.257.21:28:37.49#ibcon#end of sib2, iclass 32, count 0 2006.257.21:28:37.49#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:28:37.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:28:37.49#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.21:28:37.49#ibcon#*before write, iclass 32, count 0 2006.257.21:28:37.49#ibcon#enter sib2, iclass 32, count 0 2006.257.21:28:37.49#ibcon#flushed, iclass 32, count 0 2006.257.21:28:37.49#ibcon#about to write, iclass 32, count 0 2006.257.21:28:37.49#ibcon#wrote, iclass 32, count 0 2006.257.21:28:37.49#ibcon#about to read 3, iclass 32, count 0 2006.257.21:28:37.53#ibcon#read 3, iclass 32, count 0 2006.257.21:28:37.53#ibcon#about to read 4, iclass 32, count 0 2006.257.21:28:37.53#ibcon#read 4, iclass 32, count 0 2006.257.21:28:37.53#ibcon#about to read 5, iclass 32, count 0 2006.257.21:28:37.53#ibcon#read 5, iclass 32, count 0 2006.257.21:28:37.53#ibcon#about to read 6, iclass 32, count 0 2006.257.21:28:37.53#ibcon#read 6, iclass 32, count 0 2006.257.21:28:37.53#ibcon#end of sib2, iclass 32, count 0 2006.257.21:28:37.53#ibcon#*after write, iclass 32, count 0 2006.257.21:28:37.53#ibcon#*before return 0, iclass 32, count 0 2006.257.21:28:37.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:37.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:28:37.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:28:37.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:28:37.53$vck44/vb=2,5 2006.257.21:28:37.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.21:28:37.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.21:28:37.53#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:37.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:37.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:37.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:37.59#ibcon#enter wrdev, iclass 34, count 2 2006.257.21:28:37.59#ibcon#first serial, iclass 34, count 2 2006.257.21:28:37.59#ibcon#enter sib2, iclass 34, count 2 2006.257.21:28:37.59#ibcon#flushed, iclass 34, count 2 2006.257.21:28:37.59#ibcon#about to write, iclass 34, count 2 2006.257.21:28:37.59#ibcon#wrote, iclass 34, count 2 2006.257.21:28:37.59#ibcon#about to read 3, iclass 34, count 2 2006.257.21:28:37.61#ibcon#read 3, iclass 34, count 2 2006.257.21:28:37.61#ibcon#about to read 4, iclass 34, count 2 2006.257.21:28:37.61#ibcon#read 4, iclass 34, count 2 2006.257.21:28:37.61#ibcon#about to read 5, iclass 34, count 2 2006.257.21:28:37.61#ibcon#read 5, iclass 34, count 2 2006.257.21:28:37.61#ibcon#about to read 6, iclass 34, count 2 2006.257.21:28:37.61#ibcon#read 6, iclass 34, count 2 2006.257.21:28:37.61#ibcon#end of sib2, iclass 34, count 2 2006.257.21:28:37.61#ibcon#*mode == 0, iclass 34, count 2 2006.257.21:28:37.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.21:28:37.61#ibcon#[27=AT02-05\r\n] 2006.257.21:28:37.61#ibcon#*before write, iclass 34, count 2 2006.257.21:28:37.61#ibcon#enter sib2, iclass 34, count 2 2006.257.21:28:37.61#ibcon#flushed, iclass 34, count 2 2006.257.21:28:37.61#ibcon#about to write, iclass 34, count 2 2006.257.21:28:37.61#ibcon#wrote, iclass 34, count 2 2006.257.21:28:37.61#ibcon#about to read 3, iclass 34, count 2 2006.257.21:28:37.64#ibcon#read 3, iclass 34, count 2 2006.257.21:28:37.64#ibcon#about to read 4, iclass 34, count 2 2006.257.21:28:37.64#ibcon#read 4, iclass 34, count 2 2006.257.21:28:37.64#ibcon#about to read 5, iclass 34, count 2 2006.257.21:28:37.64#ibcon#read 5, iclass 34, count 2 2006.257.21:28:37.64#ibcon#about to read 6, iclass 34, count 2 2006.257.21:28:37.64#ibcon#read 6, iclass 34, count 2 2006.257.21:28:37.64#ibcon#end of sib2, iclass 34, count 2 2006.257.21:28:37.64#ibcon#*after write, iclass 34, count 2 2006.257.21:28:37.64#ibcon#*before return 0, iclass 34, count 2 2006.257.21:28:37.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:37.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:28:37.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.21:28:37.64#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:37.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:37.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:37.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:37.76#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:28:37.76#ibcon#first serial, iclass 34, count 0 2006.257.21:28:37.76#ibcon#enter sib2, iclass 34, count 0 2006.257.21:28:37.76#ibcon#flushed, iclass 34, count 0 2006.257.21:28:37.76#ibcon#about to write, iclass 34, count 0 2006.257.21:28:37.76#ibcon#wrote, iclass 34, count 0 2006.257.21:28:37.76#ibcon#about to read 3, iclass 34, count 0 2006.257.21:28:37.78#ibcon#read 3, iclass 34, count 0 2006.257.21:28:37.78#ibcon#about to read 4, iclass 34, count 0 2006.257.21:28:37.78#ibcon#read 4, iclass 34, count 0 2006.257.21:28:37.78#ibcon#about to read 5, iclass 34, count 0 2006.257.21:28:37.78#ibcon#read 5, iclass 34, count 0 2006.257.21:28:37.78#ibcon#about to read 6, iclass 34, count 0 2006.257.21:28:37.78#ibcon#read 6, iclass 34, count 0 2006.257.21:28:37.78#ibcon#end of sib2, iclass 34, count 0 2006.257.21:28:37.78#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:28:37.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:28:37.78#ibcon#[27=USB\r\n] 2006.257.21:28:37.78#ibcon#*before write, iclass 34, count 0 2006.257.21:28:37.78#ibcon#enter sib2, iclass 34, count 0 2006.257.21:28:37.78#ibcon#flushed, iclass 34, count 0 2006.257.21:28:37.78#ibcon#about to write, iclass 34, count 0 2006.257.21:28:37.78#ibcon#wrote, iclass 34, count 0 2006.257.21:28:37.78#ibcon#about to read 3, iclass 34, count 0 2006.257.21:28:37.81#ibcon#read 3, iclass 34, count 0 2006.257.21:28:37.81#ibcon#about to read 4, iclass 34, count 0 2006.257.21:28:37.81#ibcon#read 4, iclass 34, count 0 2006.257.21:28:37.81#ibcon#about to read 5, iclass 34, count 0 2006.257.21:28:37.81#ibcon#read 5, iclass 34, count 0 2006.257.21:28:37.81#ibcon#about to read 6, iclass 34, count 0 2006.257.21:28:37.81#ibcon#read 6, iclass 34, count 0 2006.257.21:28:37.81#ibcon#end of sib2, iclass 34, count 0 2006.257.21:28:37.81#ibcon#*after write, iclass 34, count 0 2006.257.21:28:37.81#ibcon#*before return 0, iclass 34, count 0 2006.257.21:28:37.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:37.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:28:37.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:28:37.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:28:37.81$vck44/vblo=3,649.99 2006.257.21:28:37.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.21:28:37.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.21:28:37.81#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:37.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:37.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:37.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:37.81#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:28:37.81#ibcon#first serial, iclass 36, count 0 2006.257.21:28:37.81#ibcon#enter sib2, iclass 36, count 0 2006.257.21:28:37.81#ibcon#flushed, iclass 36, count 0 2006.257.21:28:37.81#ibcon#about to write, iclass 36, count 0 2006.257.21:28:37.81#ibcon#wrote, iclass 36, count 0 2006.257.21:28:37.81#ibcon#about to read 3, iclass 36, count 0 2006.257.21:28:37.83#ibcon#read 3, iclass 36, count 0 2006.257.21:28:37.83#ibcon#about to read 4, iclass 36, count 0 2006.257.21:28:37.83#ibcon#read 4, iclass 36, count 0 2006.257.21:28:37.83#ibcon#about to read 5, iclass 36, count 0 2006.257.21:28:37.83#ibcon#read 5, iclass 36, count 0 2006.257.21:28:37.83#ibcon#about to read 6, iclass 36, count 0 2006.257.21:28:37.83#ibcon#read 6, iclass 36, count 0 2006.257.21:28:37.83#ibcon#end of sib2, iclass 36, count 0 2006.257.21:28:37.83#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:28:37.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:28:37.83#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.21:28:37.83#ibcon#*before write, iclass 36, count 0 2006.257.21:28:37.83#ibcon#enter sib2, iclass 36, count 0 2006.257.21:28:37.83#ibcon#flushed, iclass 36, count 0 2006.257.21:28:37.83#ibcon#about to write, iclass 36, count 0 2006.257.21:28:37.83#ibcon#wrote, iclass 36, count 0 2006.257.21:28:37.83#ibcon#about to read 3, iclass 36, count 0 2006.257.21:28:37.87#ibcon#read 3, iclass 36, count 0 2006.257.21:28:37.87#ibcon#about to read 4, iclass 36, count 0 2006.257.21:28:37.87#ibcon#read 4, iclass 36, count 0 2006.257.21:28:37.87#ibcon#about to read 5, iclass 36, count 0 2006.257.21:28:37.87#ibcon#read 5, iclass 36, count 0 2006.257.21:28:37.87#ibcon#about to read 6, iclass 36, count 0 2006.257.21:28:37.87#ibcon#read 6, iclass 36, count 0 2006.257.21:28:37.87#ibcon#end of sib2, iclass 36, count 0 2006.257.21:28:37.87#ibcon#*after write, iclass 36, count 0 2006.257.21:28:37.87#ibcon#*before return 0, iclass 36, count 0 2006.257.21:28:37.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:37.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:28:37.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:28:37.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:28:37.87$vck44/vb=3,4 2006.257.21:28:37.87#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.21:28:37.87#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.21:28:37.87#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:37.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:37.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:37.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:37.93#ibcon#enter wrdev, iclass 38, count 2 2006.257.21:28:37.93#ibcon#first serial, iclass 38, count 2 2006.257.21:28:37.93#ibcon#enter sib2, iclass 38, count 2 2006.257.21:28:37.93#ibcon#flushed, iclass 38, count 2 2006.257.21:28:37.93#ibcon#about to write, iclass 38, count 2 2006.257.21:28:37.93#ibcon#wrote, iclass 38, count 2 2006.257.21:28:37.93#ibcon#about to read 3, iclass 38, count 2 2006.257.21:28:37.95#ibcon#read 3, iclass 38, count 2 2006.257.21:28:37.95#ibcon#about to read 4, iclass 38, count 2 2006.257.21:28:37.95#ibcon#read 4, iclass 38, count 2 2006.257.21:28:37.95#ibcon#about to read 5, iclass 38, count 2 2006.257.21:28:37.95#ibcon#read 5, iclass 38, count 2 2006.257.21:28:37.95#ibcon#about to read 6, iclass 38, count 2 2006.257.21:28:37.95#ibcon#read 6, iclass 38, count 2 2006.257.21:28:37.95#ibcon#end of sib2, iclass 38, count 2 2006.257.21:28:37.95#ibcon#*mode == 0, iclass 38, count 2 2006.257.21:28:37.95#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.21:28:37.95#ibcon#[27=AT03-04\r\n] 2006.257.21:28:37.95#ibcon#*before write, iclass 38, count 2 2006.257.21:28:37.95#ibcon#enter sib2, iclass 38, count 2 2006.257.21:28:37.95#ibcon#flushed, iclass 38, count 2 2006.257.21:28:37.95#ibcon#about to write, iclass 38, count 2 2006.257.21:28:37.95#ibcon#wrote, iclass 38, count 2 2006.257.21:28:37.95#ibcon#about to read 3, iclass 38, count 2 2006.257.21:28:37.98#ibcon#read 3, iclass 38, count 2 2006.257.21:28:37.98#ibcon#about to read 4, iclass 38, count 2 2006.257.21:28:37.98#ibcon#read 4, iclass 38, count 2 2006.257.21:28:37.98#ibcon#about to read 5, iclass 38, count 2 2006.257.21:28:37.98#ibcon#read 5, iclass 38, count 2 2006.257.21:28:37.98#ibcon#about to read 6, iclass 38, count 2 2006.257.21:28:37.98#ibcon#read 6, iclass 38, count 2 2006.257.21:28:37.98#ibcon#end of sib2, iclass 38, count 2 2006.257.21:28:37.98#ibcon#*after write, iclass 38, count 2 2006.257.21:28:37.98#ibcon#*before return 0, iclass 38, count 2 2006.257.21:28:37.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:37.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:28:37.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.21:28:37.98#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:37.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:38.10#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:38.10#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:38.10#ibcon#enter wrdev, iclass 38, count 0 2006.257.21:28:38.10#ibcon#first serial, iclass 38, count 0 2006.257.21:28:38.10#ibcon#enter sib2, iclass 38, count 0 2006.257.21:28:38.10#ibcon#flushed, iclass 38, count 0 2006.257.21:28:38.10#ibcon#about to write, iclass 38, count 0 2006.257.21:28:38.10#ibcon#wrote, iclass 38, count 0 2006.257.21:28:38.10#ibcon#about to read 3, iclass 38, count 0 2006.257.21:28:38.12#ibcon#read 3, iclass 38, count 0 2006.257.21:28:38.12#ibcon#about to read 4, iclass 38, count 0 2006.257.21:28:38.12#ibcon#read 4, iclass 38, count 0 2006.257.21:28:38.12#ibcon#about to read 5, iclass 38, count 0 2006.257.21:28:38.12#ibcon#read 5, iclass 38, count 0 2006.257.21:28:38.12#ibcon#about to read 6, iclass 38, count 0 2006.257.21:28:38.12#ibcon#read 6, iclass 38, count 0 2006.257.21:28:38.12#ibcon#end of sib2, iclass 38, count 0 2006.257.21:28:38.12#ibcon#*mode == 0, iclass 38, count 0 2006.257.21:28:38.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.21:28:38.12#ibcon#[27=USB\r\n] 2006.257.21:28:38.12#ibcon#*before write, iclass 38, count 0 2006.257.21:28:38.12#ibcon#enter sib2, iclass 38, count 0 2006.257.21:28:38.12#ibcon#flushed, iclass 38, count 0 2006.257.21:28:38.12#ibcon#about to write, iclass 38, count 0 2006.257.21:28:38.12#ibcon#wrote, iclass 38, count 0 2006.257.21:28:38.12#ibcon#about to read 3, iclass 38, count 0 2006.257.21:28:38.15#ibcon#read 3, iclass 38, count 0 2006.257.21:28:38.15#ibcon#about to read 4, iclass 38, count 0 2006.257.21:28:38.15#ibcon#read 4, iclass 38, count 0 2006.257.21:28:38.15#ibcon#about to read 5, iclass 38, count 0 2006.257.21:28:38.15#ibcon#read 5, iclass 38, count 0 2006.257.21:28:38.15#ibcon#about to read 6, iclass 38, count 0 2006.257.21:28:38.15#ibcon#read 6, iclass 38, count 0 2006.257.21:28:38.15#ibcon#end of sib2, iclass 38, count 0 2006.257.21:28:38.15#ibcon#*after write, iclass 38, count 0 2006.257.21:28:38.15#ibcon#*before return 0, iclass 38, count 0 2006.257.21:28:38.15#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:38.15#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:28:38.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.21:28:38.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.21:28:38.15$vck44/vblo=4,679.99 2006.257.21:28:38.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.21:28:38.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.21:28:38.15#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:38.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:38.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:38.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:38.15#ibcon#enter wrdev, iclass 40, count 0 2006.257.21:28:38.15#ibcon#first serial, iclass 40, count 0 2006.257.21:28:38.15#ibcon#enter sib2, iclass 40, count 0 2006.257.21:28:38.15#ibcon#flushed, iclass 40, count 0 2006.257.21:28:38.15#ibcon#about to write, iclass 40, count 0 2006.257.21:28:38.15#ibcon#wrote, iclass 40, count 0 2006.257.21:28:38.15#ibcon#about to read 3, iclass 40, count 0 2006.257.21:28:38.17#ibcon#read 3, iclass 40, count 0 2006.257.21:28:38.17#ibcon#about to read 4, iclass 40, count 0 2006.257.21:28:38.17#ibcon#read 4, iclass 40, count 0 2006.257.21:28:38.17#ibcon#about to read 5, iclass 40, count 0 2006.257.21:28:38.17#ibcon#read 5, iclass 40, count 0 2006.257.21:28:38.17#ibcon#about to read 6, iclass 40, count 0 2006.257.21:28:38.17#ibcon#read 6, iclass 40, count 0 2006.257.21:28:38.17#ibcon#end of sib2, iclass 40, count 0 2006.257.21:28:38.17#ibcon#*mode == 0, iclass 40, count 0 2006.257.21:28:38.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.21:28:38.17#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.21:28:38.17#ibcon#*before write, iclass 40, count 0 2006.257.21:28:38.17#ibcon#enter sib2, iclass 40, count 0 2006.257.21:28:38.17#ibcon#flushed, iclass 40, count 0 2006.257.21:28:38.17#ibcon#about to write, iclass 40, count 0 2006.257.21:28:38.17#ibcon#wrote, iclass 40, count 0 2006.257.21:28:38.17#ibcon#about to read 3, iclass 40, count 0 2006.257.21:28:38.21#ibcon#read 3, iclass 40, count 0 2006.257.21:28:38.21#ibcon#about to read 4, iclass 40, count 0 2006.257.21:28:38.21#ibcon#read 4, iclass 40, count 0 2006.257.21:28:38.21#ibcon#about to read 5, iclass 40, count 0 2006.257.21:28:38.21#ibcon#read 5, iclass 40, count 0 2006.257.21:28:38.21#ibcon#about to read 6, iclass 40, count 0 2006.257.21:28:38.21#ibcon#read 6, iclass 40, count 0 2006.257.21:28:38.21#ibcon#end of sib2, iclass 40, count 0 2006.257.21:28:38.21#ibcon#*after write, iclass 40, count 0 2006.257.21:28:38.21#ibcon#*before return 0, iclass 40, count 0 2006.257.21:28:38.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:38.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:28:38.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.21:28:38.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.21:28:38.21$vck44/vb=4,5 2006.257.21:28:38.21#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.21:28:38.21#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.21:28:38.21#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:38.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:38.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:38.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:38.27#ibcon#enter wrdev, iclass 4, count 2 2006.257.21:28:38.27#ibcon#first serial, iclass 4, count 2 2006.257.21:28:38.27#ibcon#enter sib2, iclass 4, count 2 2006.257.21:28:38.27#ibcon#flushed, iclass 4, count 2 2006.257.21:28:38.27#ibcon#about to write, iclass 4, count 2 2006.257.21:28:38.27#ibcon#wrote, iclass 4, count 2 2006.257.21:28:38.27#ibcon#about to read 3, iclass 4, count 2 2006.257.21:28:38.29#ibcon#read 3, iclass 4, count 2 2006.257.21:28:38.29#ibcon#about to read 4, iclass 4, count 2 2006.257.21:28:38.29#ibcon#read 4, iclass 4, count 2 2006.257.21:28:38.29#ibcon#about to read 5, iclass 4, count 2 2006.257.21:28:38.29#ibcon#read 5, iclass 4, count 2 2006.257.21:28:38.29#ibcon#about to read 6, iclass 4, count 2 2006.257.21:28:38.29#ibcon#read 6, iclass 4, count 2 2006.257.21:28:38.29#ibcon#end of sib2, iclass 4, count 2 2006.257.21:28:38.29#ibcon#*mode == 0, iclass 4, count 2 2006.257.21:28:38.29#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.21:28:38.29#ibcon#[27=AT04-05\r\n] 2006.257.21:28:38.29#ibcon#*before write, iclass 4, count 2 2006.257.21:28:38.29#ibcon#enter sib2, iclass 4, count 2 2006.257.21:28:38.29#ibcon#flushed, iclass 4, count 2 2006.257.21:28:38.29#ibcon#about to write, iclass 4, count 2 2006.257.21:28:38.29#ibcon#wrote, iclass 4, count 2 2006.257.21:28:38.29#ibcon#about to read 3, iclass 4, count 2 2006.257.21:28:38.32#ibcon#read 3, iclass 4, count 2 2006.257.21:28:38.32#ibcon#about to read 4, iclass 4, count 2 2006.257.21:28:38.32#ibcon#read 4, iclass 4, count 2 2006.257.21:28:38.32#ibcon#about to read 5, iclass 4, count 2 2006.257.21:28:38.32#ibcon#read 5, iclass 4, count 2 2006.257.21:28:38.32#ibcon#about to read 6, iclass 4, count 2 2006.257.21:28:38.32#ibcon#read 6, iclass 4, count 2 2006.257.21:28:38.32#ibcon#end of sib2, iclass 4, count 2 2006.257.21:28:38.32#ibcon#*after write, iclass 4, count 2 2006.257.21:28:38.32#ibcon#*before return 0, iclass 4, count 2 2006.257.21:28:38.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:38.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:28:38.32#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.21:28:38.32#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:38.32#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:38.44#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:38.44#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:38.44#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:28:38.44#ibcon#first serial, iclass 4, count 0 2006.257.21:28:38.44#ibcon#enter sib2, iclass 4, count 0 2006.257.21:28:38.44#ibcon#flushed, iclass 4, count 0 2006.257.21:28:38.44#ibcon#about to write, iclass 4, count 0 2006.257.21:28:38.44#ibcon#wrote, iclass 4, count 0 2006.257.21:28:38.44#ibcon#about to read 3, iclass 4, count 0 2006.257.21:28:38.46#ibcon#read 3, iclass 4, count 0 2006.257.21:28:38.46#ibcon#about to read 4, iclass 4, count 0 2006.257.21:28:38.46#ibcon#read 4, iclass 4, count 0 2006.257.21:28:38.46#ibcon#about to read 5, iclass 4, count 0 2006.257.21:28:38.46#ibcon#read 5, iclass 4, count 0 2006.257.21:28:38.46#ibcon#about to read 6, iclass 4, count 0 2006.257.21:28:38.46#ibcon#read 6, iclass 4, count 0 2006.257.21:28:38.46#ibcon#end of sib2, iclass 4, count 0 2006.257.21:28:38.46#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:28:38.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:28:38.46#ibcon#[27=USB\r\n] 2006.257.21:28:38.46#ibcon#*before write, iclass 4, count 0 2006.257.21:28:38.46#ibcon#enter sib2, iclass 4, count 0 2006.257.21:28:38.46#ibcon#flushed, iclass 4, count 0 2006.257.21:28:38.46#ibcon#about to write, iclass 4, count 0 2006.257.21:28:38.46#ibcon#wrote, iclass 4, count 0 2006.257.21:28:38.46#ibcon#about to read 3, iclass 4, count 0 2006.257.21:28:38.49#ibcon#read 3, iclass 4, count 0 2006.257.21:28:38.49#ibcon#about to read 4, iclass 4, count 0 2006.257.21:28:38.49#ibcon#read 4, iclass 4, count 0 2006.257.21:28:38.49#ibcon#about to read 5, iclass 4, count 0 2006.257.21:28:38.49#ibcon#read 5, iclass 4, count 0 2006.257.21:28:38.49#ibcon#about to read 6, iclass 4, count 0 2006.257.21:28:38.49#ibcon#read 6, iclass 4, count 0 2006.257.21:28:38.49#ibcon#end of sib2, iclass 4, count 0 2006.257.21:28:38.49#ibcon#*after write, iclass 4, count 0 2006.257.21:28:38.49#ibcon#*before return 0, iclass 4, count 0 2006.257.21:28:38.49#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:38.49#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:28:38.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:28:38.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:28:38.49$vck44/vblo=5,709.99 2006.257.21:28:38.49#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.21:28:38.49#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.21:28:38.49#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:38.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:38.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:38.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:38.49#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:28:38.49#ibcon#first serial, iclass 6, count 0 2006.257.21:28:38.49#ibcon#enter sib2, iclass 6, count 0 2006.257.21:28:38.49#ibcon#flushed, iclass 6, count 0 2006.257.21:28:38.49#ibcon#about to write, iclass 6, count 0 2006.257.21:28:38.49#ibcon#wrote, iclass 6, count 0 2006.257.21:28:38.49#ibcon#about to read 3, iclass 6, count 0 2006.257.21:28:38.51#ibcon#read 3, iclass 6, count 0 2006.257.21:28:38.51#ibcon#about to read 4, iclass 6, count 0 2006.257.21:28:38.51#ibcon#read 4, iclass 6, count 0 2006.257.21:28:38.51#ibcon#about to read 5, iclass 6, count 0 2006.257.21:28:38.51#ibcon#read 5, iclass 6, count 0 2006.257.21:28:38.51#ibcon#about to read 6, iclass 6, count 0 2006.257.21:28:38.51#ibcon#read 6, iclass 6, count 0 2006.257.21:28:38.51#ibcon#end of sib2, iclass 6, count 0 2006.257.21:28:38.51#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:28:38.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:28:38.51#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.21:28:38.51#ibcon#*before write, iclass 6, count 0 2006.257.21:28:38.51#ibcon#enter sib2, iclass 6, count 0 2006.257.21:28:38.51#ibcon#flushed, iclass 6, count 0 2006.257.21:28:38.51#ibcon#about to write, iclass 6, count 0 2006.257.21:28:38.51#ibcon#wrote, iclass 6, count 0 2006.257.21:28:38.51#ibcon#about to read 3, iclass 6, count 0 2006.257.21:28:38.55#ibcon#read 3, iclass 6, count 0 2006.257.21:28:38.55#ibcon#about to read 4, iclass 6, count 0 2006.257.21:28:38.55#ibcon#read 4, iclass 6, count 0 2006.257.21:28:38.55#ibcon#about to read 5, iclass 6, count 0 2006.257.21:28:38.55#ibcon#read 5, iclass 6, count 0 2006.257.21:28:38.55#ibcon#about to read 6, iclass 6, count 0 2006.257.21:28:38.55#ibcon#read 6, iclass 6, count 0 2006.257.21:28:38.55#ibcon#end of sib2, iclass 6, count 0 2006.257.21:28:38.55#ibcon#*after write, iclass 6, count 0 2006.257.21:28:38.55#ibcon#*before return 0, iclass 6, count 0 2006.257.21:28:38.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:38.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:28:38.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:28:38.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:28:38.55$vck44/vb=5,4 2006.257.21:28:38.55#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.21:28:38.55#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.21:28:38.55#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:38.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:38.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:38.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:38.61#ibcon#enter wrdev, iclass 10, count 2 2006.257.21:28:38.61#ibcon#first serial, iclass 10, count 2 2006.257.21:28:38.61#ibcon#enter sib2, iclass 10, count 2 2006.257.21:28:38.61#ibcon#flushed, iclass 10, count 2 2006.257.21:28:38.61#ibcon#about to write, iclass 10, count 2 2006.257.21:28:38.61#ibcon#wrote, iclass 10, count 2 2006.257.21:28:38.61#ibcon#about to read 3, iclass 10, count 2 2006.257.21:28:38.63#ibcon#read 3, iclass 10, count 2 2006.257.21:28:38.63#ibcon#about to read 4, iclass 10, count 2 2006.257.21:28:38.63#ibcon#read 4, iclass 10, count 2 2006.257.21:28:38.63#ibcon#about to read 5, iclass 10, count 2 2006.257.21:28:38.63#ibcon#read 5, iclass 10, count 2 2006.257.21:28:38.63#ibcon#about to read 6, iclass 10, count 2 2006.257.21:28:38.63#ibcon#read 6, iclass 10, count 2 2006.257.21:28:38.63#ibcon#end of sib2, iclass 10, count 2 2006.257.21:28:38.63#ibcon#*mode == 0, iclass 10, count 2 2006.257.21:28:38.63#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.21:28:38.63#ibcon#[27=AT05-04\r\n] 2006.257.21:28:38.63#ibcon#*before write, iclass 10, count 2 2006.257.21:28:38.63#ibcon#enter sib2, iclass 10, count 2 2006.257.21:28:38.63#ibcon#flushed, iclass 10, count 2 2006.257.21:28:38.63#ibcon#about to write, iclass 10, count 2 2006.257.21:28:38.63#ibcon#wrote, iclass 10, count 2 2006.257.21:28:38.63#ibcon#about to read 3, iclass 10, count 2 2006.257.21:28:38.66#ibcon#read 3, iclass 10, count 2 2006.257.21:28:38.66#ibcon#about to read 4, iclass 10, count 2 2006.257.21:28:38.66#ibcon#read 4, iclass 10, count 2 2006.257.21:28:38.66#ibcon#about to read 5, iclass 10, count 2 2006.257.21:28:38.66#ibcon#read 5, iclass 10, count 2 2006.257.21:28:38.66#ibcon#about to read 6, iclass 10, count 2 2006.257.21:28:38.66#ibcon#read 6, iclass 10, count 2 2006.257.21:28:38.66#ibcon#end of sib2, iclass 10, count 2 2006.257.21:28:38.66#ibcon#*after write, iclass 10, count 2 2006.257.21:28:38.66#ibcon#*before return 0, iclass 10, count 2 2006.257.21:28:38.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:38.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:28:38.66#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.21:28:38.66#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:38.66#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:38.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:38.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:38.78#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:28:38.78#ibcon#first serial, iclass 10, count 0 2006.257.21:28:38.78#ibcon#enter sib2, iclass 10, count 0 2006.257.21:28:38.78#ibcon#flushed, iclass 10, count 0 2006.257.21:28:38.78#ibcon#about to write, iclass 10, count 0 2006.257.21:28:38.78#ibcon#wrote, iclass 10, count 0 2006.257.21:28:38.78#ibcon#about to read 3, iclass 10, count 0 2006.257.21:28:38.80#ibcon#read 3, iclass 10, count 0 2006.257.21:28:38.80#ibcon#about to read 4, iclass 10, count 0 2006.257.21:28:38.80#ibcon#read 4, iclass 10, count 0 2006.257.21:28:38.80#ibcon#about to read 5, iclass 10, count 0 2006.257.21:28:38.80#ibcon#read 5, iclass 10, count 0 2006.257.21:28:38.80#ibcon#about to read 6, iclass 10, count 0 2006.257.21:28:38.80#ibcon#read 6, iclass 10, count 0 2006.257.21:28:38.80#ibcon#end of sib2, iclass 10, count 0 2006.257.21:28:38.80#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:28:38.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:28:38.80#ibcon#[27=USB\r\n] 2006.257.21:28:38.80#ibcon#*before write, iclass 10, count 0 2006.257.21:28:38.80#ibcon#enter sib2, iclass 10, count 0 2006.257.21:28:38.80#ibcon#flushed, iclass 10, count 0 2006.257.21:28:38.80#ibcon#about to write, iclass 10, count 0 2006.257.21:28:38.80#ibcon#wrote, iclass 10, count 0 2006.257.21:28:38.80#ibcon#about to read 3, iclass 10, count 0 2006.257.21:28:38.83#ibcon#read 3, iclass 10, count 0 2006.257.21:28:38.83#ibcon#about to read 4, iclass 10, count 0 2006.257.21:28:38.83#ibcon#read 4, iclass 10, count 0 2006.257.21:28:38.83#ibcon#about to read 5, iclass 10, count 0 2006.257.21:28:38.83#ibcon#read 5, iclass 10, count 0 2006.257.21:28:38.83#ibcon#about to read 6, iclass 10, count 0 2006.257.21:28:38.83#ibcon#read 6, iclass 10, count 0 2006.257.21:28:38.83#ibcon#end of sib2, iclass 10, count 0 2006.257.21:28:38.83#ibcon#*after write, iclass 10, count 0 2006.257.21:28:38.83#ibcon#*before return 0, iclass 10, count 0 2006.257.21:28:38.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:38.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:28:38.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:28:38.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:28:38.83$vck44/vblo=6,719.99 2006.257.21:28:38.83#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.21:28:38.83#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.21:28:38.83#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:38.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:28:38.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:28:38.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:28:38.83#ibcon#enter wrdev, iclass 12, count 0 2006.257.21:28:38.83#ibcon#first serial, iclass 12, count 0 2006.257.21:28:38.83#ibcon#enter sib2, iclass 12, count 0 2006.257.21:28:38.83#ibcon#flushed, iclass 12, count 0 2006.257.21:28:38.83#ibcon#about to write, iclass 12, count 0 2006.257.21:28:38.83#ibcon#wrote, iclass 12, count 0 2006.257.21:28:38.83#ibcon#about to read 3, iclass 12, count 0 2006.257.21:28:38.85#ibcon#read 3, iclass 12, count 0 2006.257.21:28:38.85#ibcon#about to read 4, iclass 12, count 0 2006.257.21:28:38.85#ibcon#read 4, iclass 12, count 0 2006.257.21:28:38.85#ibcon#about to read 5, iclass 12, count 0 2006.257.21:28:38.85#ibcon#read 5, iclass 12, count 0 2006.257.21:28:38.85#ibcon#about to read 6, iclass 12, count 0 2006.257.21:28:38.85#ibcon#read 6, iclass 12, count 0 2006.257.21:28:38.85#ibcon#end of sib2, iclass 12, count 0 2006.257.21:28:38.85#ibcon#*mode == 0, iclass 12, count 0 2006.257.21:28:38.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.21:28:38.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.21:28:38.85#ibcon#*before write, iclass 12, count 0 2006.257.21:28:38.85#ibcon#enter sib2, iclass 12, count 0 2006.257.21:28:38.85#ibcon#flushed, iclass 12, count 0 2006.257.21:28:38.85#ibcon#about to write, iclass 12, count 0 2006.257.21:28:38.85#ibcon#wrote, iclass 12, count 0 2006.257.21:28:38.85#ibcon#about to read 3, iclass 12, count 0 2006.257.21:28:38.89#ibcon#read 3, iclass 12, count 0 2006.257.21:28:38.89#ibcon#about to read 4, iclass 12, count 0 2006.257.21:28:38.89#ibcon#read 4, iclass 12, count 0 2006.257.21:28:38.89#ibcon#about to read 5, iclass 12, count 0 2006.257.21:28:38.89#ibcon#read 5, iclass 12, count 0 2006.257.21:28:38.89#ibcon#about to read 6, iclass 12, count 0 2006.257.21:28:38.89#ibcon#read 6, iclass 12, count 0 2006.257.21:28:38.89#ibcon#end of sib2, iclass 12, count 0 2006.257.21:28:38.89#ibcon#*after write, iclass 12, count 0 2006.257.21:28:38.89#ibcon#*before return 0, iclass 12, count 0 2006.257.21:28:38.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:28:38.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:28:38.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.21:28:38.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.21:28:38.89$vck44/vb=6,4 2006.257.21:28:38.89#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.21:28:38.89#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.21:28:38.89#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:38.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:28:38.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:28:38.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:28:38.95#ibcon#enter wrdev, iclass 14, count 2 2006.257.21:28:38.95#ibcon#first serial, iclass 14, count 2 2006.257.21:28:38.95#ibcon#enter sib2, iclass 14, count 2 2006.257.21:28:38.95#ibcon#flushed, iclass 14, count 2 2006.257.21:28:38.95#ibcon#about to write, iclass 14, count 2 2006.257.21:28:38.95#ibcon#wrote, iclass 14, count 2 2006.257.21:28:38.95#ibcon#about to read 3, iclass 14, count 2 2006.257.21:28:38.97#ibcon#read 3, iclass 14, count 2 2006.257.21:28:38.97#ibcon#about to read 4, iclass 14, count 2 2006.257.21:28:38.97#ibcon#read 4, iclass 14, count 2 2006.257.21:28:38.97#ibcon#about to read 5, iclass 14, count 2 2006.257.21:28:38.97#ibcon#read 5, iclass 14, count 2 2006.257.21:28:38.97#ibcon#about to read 6, iclass 14, count 2 2006.257.21:28:38.97#ibcon#read 6, iclass 14, count 2 2006.257.21:28:38.97#ibcon#end of sib2, iclass 14, count 2 2006.257.21:28:38.97#ibcon#*mode == 0, iclass 14, count 2 2006.257.21:28:38.97#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.21:28:38.97#ibcon#[27=AT06-04\r\n] 2006.257.21:28:38.97#ibcon#*before write, iclass 14, count 2 2006.257.21:28:38.97#ibcon#enter sib2, iclass 14, count 2 2006.257.21:28:38.97#ibcon#flushed, iclass 14, count 2 2006.257.21:28:38.97#ibcon#about to write, iclass 14, count 2 2006.257.21:28:38.97#ibcon#wrote, iclass 14, count 2 2006.257.21:28:38.97#ibcon#about to read 3, iclass 14, count 2 2006.257.21:28:39.00#ibcon#read 3, iclass 14, count 2 2006.257.21:28:39.00#ibcon#about to read 4, iclass 14, count 2 2006.257.21:28:39.00#ibcon#read 4, iclass 14, count 2 2006.257.21:28:39.00#ibcon#about to read 5, iclass 14, count 2 2006.257.21:28:39.00#ibcon#read 5, iclass 14, count 2 2006.257.21:28:39.00#ibcon#about to read 6, iclass 14, count 2 2006.257.21:28:39.00#ibcon#read 6, iclass 14, count 2 2006.257.21:28:39.00#ibcon#end of sib2, iclass 14, count 2 2006.257.21:28:39.00#ibcon#*after write, iclass 14, count 2 2006.257.21:28:39.00#ibcon#*before return 0, iclass 14, count 2 2006.257.21:28:39.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:28:39.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:28:39.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.21:28:39.00#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:39.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:28:39.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:28:39.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:28:39.12#ibcon#enter wrdev, iclass 14, count 0 2006.257.21:28:39.12#ibcon#first serial, iclass 14, count 0 2006.257.21:28:39.12#ibcon#enter sib2, iclass 14, count 0 2006.257.21:28:39.12#ibcon#flushed, iclass 14, count 0 2006.257.21:28:39.12#ibcon#about to write, iclass 14, count 0 2006.257.21:28:39.12#ibcon#wrote, iclass 14, count 0 2006.257.21:28:39.12#ibcon#about to read 3, iclass 14, count 0 2006.257.21:28:39.14#ibcon#read 3, iclass 14, count 0 2006.257.21:28:39.14#ibcon#about to read 4, iclass 14, count 0 2006.257.21:28:39.14#ibcon#read 4, iclass 14, count 0 2006.257.21:28:39.14#ibcon#about to read 5, iclass 14, count 0 2006.257.21:28:39.14#ibcon#read 5, iclass 14, count 0 2006.257.21:28:39.14#ibcon#about to read 6, iclass 14, count 0 2006.257.21:28:39.14#ibcon#read 6, iclass 14, count 0 2006.257.21:28:39.14#ibcon#end of sib2, iclass 14, count 0 2006.257.21:28:39.14#ibcon#*mode == 0, iclass 14, count 0 2006.257.21:28:39.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.21:28:39.14#ibcon#[27=USB\r\n] 2006.257.21:28:39.14#ibcon#*before write, iclass 14, count 0 2006.257.21:28:39.14#ibcon#enter sib2, iclass 14, count 0 2006.257.21:28:39.14#ibcon#flushed, iclass 14, count 0 2006.257.21:28:39.14#ibcon#about to write, iclass 14, count 0 2006.257.21:28:39.14#ibcon#wrote, iclass 14, count 0 2006.257.21:28:39.14#ibcon#about to read 3, iclass 14, count 0 2006.257.21:28:39.17#ibcon#read 3, iclass 14, count 0 2006.257.21:28:39.17#ibcon#about to read 4, iclass 14, count 0 2006.257.21:28:39.17#ibcon#read 4, iclass 14, count 0 2006.257.21:28:39.17#ibcon#about to read 5, iclass 14, count 0 2006.257.21:28:39.17#ibcon#read 5, iclass 14, count 0 2006.257.21:28:39.17#ibcon#about to read 6, iclass 14, count 0 2006.257.21:28:39.17#ibcon#read 6, iclass 14, count 0 2006.257.21:28:39.17#ibcon#end of sib2, iclass 14, count 0 2006.257.21:28:39.17#ibcon#*after write, iclass 14, count 0 2006.257.21:28:39.17#ibcon#*before return 0, iclass 14, count 0 2006.257.21:28:39.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:28:39.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:28:39.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.21:28:39.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.21:28:39.17$vck44/vblo=7,734.99 2006.257.21:28:39.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.21:28:39.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.21:28:39.17#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:39.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:28:39.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:28:39.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:28:39.17#ibcon#enter wrdev, iclass 16, count 0 2006.257.21:28:39.17#ibcon#first serial, iclass 16, count 0 2006.257.21:28:39.17#ibcon#enter sib2, iclass 16, count 0 2006.257.21:28:39.17#ibcon#flushed, iclass 16, count 0 2006.257.21:28:39.17#ibcon#about to write, iclass 16, count 0 2006.257.21:28:39.17#ibcon#wrote, iclass 16, count 0 2006.257.21:28:39.17#ibcon#about to read 3, iclass 16, count 0 2006.257.21:28:39.19#ibcon#read 3, iclass 16, count 0 2006.257.21:28:39.19#ibcon#about to read 4, iclass 16, count 0 2006.257.21:28:39.19#ibcon#read 4, iclass 16, count 0 2006.257.21:28:39.19#ibcon#about to read 5, iclass 16, count 0 2006.257.21:28:39.19#ibcon#read 5, iclass 16, count 0 2006.257.21:28:39.19#ibcon#about to read 6, iclass 16, count 0 2006.257.21:28:39.19#ibcon#read 6, iclass 16, count 0 2006.257.21:28:39.19#ibcon#end of sib2, iclass 16, count 0 2006.257.21:28:39.19#ibcon#*mode == 0, iclass 16, count 0 2006.257.21:28:39.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.21:28:39.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.21:28:39.19#ibcon#*before write, iclass 16, count 0 2006.257.21:28:39.19#ibcon#enter sib2, iclass 16, count 0 2006.257.21:28:39.19#ibcon#flushed, iclass 16, count 0 2006.257.21:28:39.19#ibcon#about to write, iclass 16, count 0 2006.257.21:28:39.19#ibcon#wrote, iclass 16, count 0 2006.257.21:28:39.19#ibcon#about to read 3, iclass 16, count 0 2006.257.21:28:39.23#ibcon#read 3, iclass 16, count 0 2006.257.21:28:39.23#ibcon#about to read 4, iclass 16, count 0 2006.257.21:28:39.23#ibcon#read 4, iclass 16, count 0 2006.257.21:28:39.23#ibcon#about to read 5, iclass 16, count 0 2006.257.21:28:39.23#ibcon#read 5, iclass 16, count 0 2006.257.21:28:39.23#ibcon#about to read 6, iclass 16, count 0 2006.257.21:28:39.23#ibcon#read 6, iclass 16, count 0 2006.257.21:28:39.23#ibcon#end of sib2, iclass 16, count 0 2006.257.21:28:39.23#ibcon#*after write, iclass 16, count 0 2006.257.21:28:39.23#ibcon#*before return 0, iclass 16, count 0 2006.257.21:28:39.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:28:39.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:28:39.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.21:28:39.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.21:28:39.23$vck44/vb=7,4 2006.257.21:28:39.23#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.21:28:39.23#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.21:28:39.23#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:39.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:28:39.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:28:39.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:28:39.29#ibcon#enter wrdev, iclass 18, count 2 2006.257.21:28:39.29#ibcon#first serial, iclass 18, count 2 2006.257.21:28:39.29#ibcon#enter sib2, iclass 18, count 2 2006.257.21:28:39.29#ibcon#flushed, iclass 18, count 2 2006.257.21:28:39.29#ibcon#about to write, iclass 18, count 2 2006.257.21:28:39.29#ibcon#wrote, iclass 18, count 2 2006.257.21:28:39.29#ibcon#about to read 3, iclass 18, count 2 2006.257.21:28:39.31#ibcon#read 3, iclass 18, count 2 2006.257.21:28:39.31#ibcon#about to read 4, iclass 18, count 2 2006.257.21:28:39.31#ibcon#read 4, iclass 18, count 2 2006.257.21:28:39.31#ibcon#about to read 5, iclass 18, count 2 2006.257.21:28:39.31#ibcon#read 5, iclass 18, count 2 2006.257.21:28:39.31#ibcon#about to read 6, iclass 18, count 2 2006.257.21:28:39.31#ibcon#read 6, iclass 18, count 2 2006.257.21:28:39.31#ibcon#end of sib2, iclass 18, count 2 2006.257.21:28:39.31#ibcon#*mode == 0, iclass 18, count 2 2006.257.21:28:39.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.21:28:39.31#ibcon#[27=AT07-04\r\n] 2006.257.21:28:39.31#ibcon#*before write, iclass 18, count 2 2006.257.21:28:39.31#ibcon#enter sib2, iclass 18, count 2 2006.257.21:28:39.31#ibcon#flushed, iclass 18, count 2 2006.257.21:28:39.31#ibcon#about to write, iclass 18, count 2 2006.257.21:28:39.31#ibcon#wrote, iclass 18, count 2 2006.257.21:28:39.31#ibcon#about to read 3, iclass 18, count 2 2006.257.21:28:39.34#ibcon#read 3, iclass 18, count 2 2006.257.21:28:39.34#ibcon#about to read 4, iclass 18, count 2 2006.257.21:28:39.34#ibcon#read 4, iclass 18, count 2 2006.257.21:28:39.34#ibcon#about to read 5, iclass 18, count 2 2006.257.21:28:39.34#ibcon#read 5, iclass 18, count 2 2006.257.21:28:39.34#ibcon#about to read 6, iclass 18, count 2 2006.257.21:28:39.34#ibcon#read 6, iclass 18, count 2 2006.257.21:28:39.34#ibcon#end of sib2, iclass 18, count 2 2006.257.21:28:39.34#ibcon#*after write, iclass 18, count 2 2006.257.21:28:39.34#ibcon#*before return 0, iclass 18, count 2 2006.257.21:28:39.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:28:39.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:28:39.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.21:28:39.34#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:39.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:28:39.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:28:39.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:28:39.46#ibcon#enter wrdev, iclass 18, count 0 2006.257.21:28:39.46#ibcon#first serial, iclass 18, count 0 2006.257.21:28:39.46#ibcon#enter sib2, iclass 18, count 0 2006.257.21:28:39.46#ibcon#flushed, iclass 18, count 0 2006.257.21:28:39.46#ibcon#about to write, iclass 18, count 0 2006.257.21:28:39.46#ibcon#wrote, iclass 18, count 0 2006.257.21:28:39.46#ibcon#about to read 3, iclass 18, count 0 2006.257.21:28:39.48#ibcon#read 3, iclass 18, count 0 2006.257.21:28:39.48#ibcon#about to read 4, iclass 18, count 0 2006.257.21:28:39.48#ibcon#read 4, iclass 18, count 0 2006.257.21:28:39.48#ibcon#about to read 5, iclass 18, count 0 2006.257.21:28:39.48#ibcon#read 5, iclass 18, count 0 2006.257.21:28:39.48#ibcon#about to read 6, iclass 18, count 0 2006.257.21:28:39.48#ibcon#read 6, iclass 18, count 0 2006.257.21:28:39.48#ibcon#end of sib2, iclass 18, count 0 2006.257.21:28:39.48#ibcon#*mode == 0, iclass 18, count 0 2006.257.21:28:39.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.21:28:39.48#ibcon#[27=USB\r\n] 2006.257.21:28:39.48#ibcon#*before write, iclass 18, count 0 2006.257.21:28:39.48#ibcon#enter sib2, iclass 18, count 0 2006.257.21:28:39.48#ibcon#flushed, iclass 18, count 0 2006.257.21:28:39.48#ibcon#about to write, iclass 18, count 0 2006.257.21:28:39.48#ibcon#wrote, iclass 18, count 0 2006.257.21:28:39.48#ibcon#about to read 3, iclass 18, count 0 2006.257.21:28:39.51#ibcon#read 3, iclass 18, count 0 2006.257.21:28:39.51#ibcon#about to read 4, iclass 18, count 0 2006.257.21:28:39.51#ibcon#read 4, iclass 18, count 0 2006.257.21:28:39.51#ibcon#about to read 5, iclass 18, count 0 2006.257.21:28:39.51#ibcon#read 5, iclass 18, count 0 2006.257.21:28:39.51#ibcon#about to read 6, iclass 18, count 0 2006.257.21:28:39.51#ibcon#read 6, iclass 18, count 0 2006.257.21:28:39.51#ibcon#end of sib2, iclass 18, count 0 2006.257.21:28:39.51#ibcon#*after write, iclass 18, count 0 2006.257.21:28:39.51#ibcon#*before return 0, iclass 18, count 0 2006.257.21:28:39.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:28:39.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:28:39.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.21:28:39.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.21:28:39.51$vck44/vblo=8,744.99 2006.257.21:28:39.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.21:28:39.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.21:28:39.51#ibcon#ireg 17 cls_cnt 0 2006.257.21:28:39.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:39.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:39.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:39.51#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:28:39.51#ibcon#first serial, iclass 20, count 0 2006.257.21:28:39.51#ibcon#enter sib2, iclass 20, count 0 2006.257.21:28:39.51#ibcon#flushed, iclass 20, count 0 2006.257.21:28:39.51#ibcon#about to write, iclass 20, count 0 2006.257.21:28:39.51#ibcon#wrote, iclass 20, count 0 2006.257.21:28:39.51#ibcon#about to read 3, iclass 20, count 0 2006.257.21:28:39.53#ibcon#read 3, iclass 20, count 0 2006.257.21:28:39.53#ibcon#about to read 4, iclass 20, count 0 2006.257.21:28:39.53#ibcon#read 4, iclass 20, count 0 2006.257.21:28:39.53#ibcon#about to read 5, iclass 20, count 0 2006.257.21:28:39.53#ibcon#read 5, iclass 20, count 0 2006.257.21:28:39.53#ibcon#about to read 6, iclass 20, count 0 2006.257.21:28:39.53#ibcon#read 6, iclass 20, count 0 2006.257.21:28:39.53#ibcon#end of sib2, iclass 20, count 0 2006.257.21:28:39.53#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:28:39.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:28:39.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.21:28:39.53#ibcon#*before write, iclass 20, count 0 2006.257.21:28:39.53#ibcon#enter sib2, iclass 20, count 0 2006.257.21:28:39.53#ibcon#flushed, iclass 20, count 0 2006.257.21:28:39.53#ibcon#about to write, iclass 20, count 0 2006.257.21:28:39.53#ibcon#wrote, iclass 20, count 0 2006.257.21:28:39.53#ibcon#about to read 3, iclass 20, count 0 2006.257.21:28:39.57#ibcon#read 3, iclass 20, count 0 2006.257.21:28:39.57#ibcon#about to read 4, iclass 20, count 0 2006.257.21:28:39.57#ibcon#read 4, iclass 20, count 0 2006.257.21:28:39.57#ibcon#about to read 5, iclass 20, count 0 2006.257.21:28:39.57#ibcon#read 5, iclass 20, count 0 2006.257.21:28:39.57#ibcon#about to read 6, iclass 20, count 0 2006.257.21:28:39.57#ibcon#read 6, iclass 20, count 0 2006.257.21:28:39.57#ibcon#end of sib2, iclass 20, count 0 2006.257.21:28:39.57#ibcon#*after write, iclass 20, count 0 2006.257.21:28:39.57#ibcon#*before return 0, iclass 20, count 0 2006.257.21:28:39.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:39.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:28:39.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:28:39.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:28:39.57$vck44/vb=8,4 2006.257.21:28:39.57#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.21:28:39.57#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.21:28:39.57#ibcon#ireg 11 cls_cnt 2 2006.257.21:28:39.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:39.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:39.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:39.63#ibcon#enter wrdev, iclass 22, count 2 2006.257.21:28:39.63#ibcon#first serial, iclass 22, count 2 2006.257.21:28:39.63#ibcon#enter sib2, iclass 22, count 2 2006.257.21:28:39.63#ibcon#flushed, iclass 22, count 2 2006.257.21:28:39.63#ibcon#about to write, iclass 22, count 2 2006.257.21:28:39.63#ibcon#wrote, iclass 22, count 2 2006.257.21:28:39.63#ibcon#about to read 3, iclass 22, count 2 2006.257.21:28:39.65#ibcon#read 3, iclass 22, count 2 2006.257.21:28:39.65#ibcon#about to read 4, iclass 22, count 2 2006.257.21:28:39.65#ibcon#read 4, iclass 22, count 2 2006.257.21:28:39.65#ibcon#about to read 5, iclass 22, count 2 2006.257.21:28:39.65#ibcon#read 5, iclass 22, count 2 2006.257.21:28:39.65#ibcon#about to read 6, iclass 22, count 2 2006.257.21:28:39.65#ibcon#read 6, iclass 22, count 2 2006.257.21:28:39.65#ibcon#end of sib2, iclass 22, count 2 2006.257.21:28:39.65#ibcon#*mode == 0, iclass 22, count 2 2006.257.21:28:39.65#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.21:28:39.65#ibcon#[27=AT08-04\r\n] 2006.257.21:28:39.65#ibcon#*before write, iclass 22, count 2 2006.257.21:28:39.65#ibcon#enter sib2, iclass 22, count 2 2006.257.21:28:39.65#ibcon#flushed, iclass 22, count 2 2006.257.21:28:39.65#ibcon#about to write, iclass 22, count 2 2006.257.21:28:39.65#ibcon#wrote, iclass 22, count 2 2006.257.21:28:39.65#ibcon#about to read 3, iclass 22, count 2 2006.257.21:28:39.68#ibcon#read 3, iclass 22, count 2 2006.257.21:28:39.68#ibcon#about to read 4, iclass 22, count 2 2006.257.21:28:39.68#ibcon#read 4, iclass 22, count 2 2006.257.21:28:39.68#ibcon#about to read 5, iclass 22, count 2 2006.257.21:28:39.68#ibcon#read 5, iclass 22, count 2 2006.257.21:28:39.68#ibcon#about to read 6, iclass 22, count 2 2006.257.21:28:39.68#ibcon#read 6, iclass 22, count 2 2006.257.21:28:39.68#ibcon#end of sib2, iclass 22, count 2 2006.257.21:28:39.68#ibcon#*after write, iclass 22, count 2 2006.257.21:28:39.68#ibcon#*before return 0, iclass 22, count 2 2006.257.21:28:39.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:39.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:28:39.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.21:28:39.68#ibcon#ireg 7 cls_cnt 0 2006.257.21:28:39.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:39.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:39.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:39.80#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:28:39.80#ibcon#first serial, iclass 22, count 0 2006.257.21:28:39.80#ibcon#enter sib2, iclass 22, count 0 2006.257.21:28:39.80#ibcon#flushed, iclass 22, count 0 2006.257.21:28:39.80#ibcon#about to write, iclass 22, count 0 2006.257.21:28:39.80#ibcon#wrote, iclass 22, count 0 2006.257.21:28:39.80#ibcon#about to read 3, iclass 22, count 0 2006.257.21:28:39.82#ibcon#read 3, iclass 22, count 0 2006.257.21:28:39.82#ibcon#about to read 4, iclass 22, count 0 2006.257.21:28:39.82#ibcon#read 4, iclass 22, count 0 2006.257.21:28:39.82#ibcon#about to read 5, iclass 22, count 0 2006.257.21:28:39.82#ibcon#read 5, iclass 22, count 0 2006.257.21:28:39.82#ibcon#about to read 6, iclass 22, count 0 2006.257.21:28:39.82#ibcon#read 6, iclass 22, count 0 2006.257.21:28:39.82#ibcon#end of sib2, iclass 22, count 0 2006.257.21:28:39.82#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:28:39.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:28:39.82#ibcon#[27=USB\r\n] 2006.257.21:28:39.82#ibcon#*before write, iclass 22, count 0 2006.257.21:28:39.82#ibcon#enter sib2, iclass 22, count 0 2006.257.21:28:39.82#ibcon#flushed, iclass 22, count 0 2006.257.21:28:39.82#ibcon#about to write, iclass 22, count 0 2006.257.21:28:39.82#ibcon#wrote, iclass 22, count 0 2006.257.21:28:39.82#ibcon#about to read 3, iclass 22, count 0 2006.257.21:28:39.85#ibcon#read 3, iclass 22, count 0 2006.257.21:28:39.85#ibcon#about to read 4, iclass 22, count 0 2006.257.21:28:39.85#ibcon#read 4, iclass 22, count 0 2006.257.21:28:39.85#ibcon#about to read 5, iclass 22, count 0 2006.257.21:28:39.85#ibcon#read 5, iclass 22, count 0 2006.257.21:28:39.85#ibcon#about to read 6, iclass 22, count 0 2006.257.21:28:39.85#ibcon#read 6, iclass 22, count 0 2006.257.21:28:39.85#ibcon#end of sib2, iclass 22, count 0 2006.257.21:28:39.85#ibcon#*after write, iclass 22, count 0 2006.257.21:28:39.85#ibcon#*before return 0, iclass 22, count 0 2006.257.21:28:39.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:39.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:28:39.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:28:39.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:28:39.85$vck44/vabw=wide 2006.257.21:28:39.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.21:28:39.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.21:28:39.85#ibcon#ireg 8 cls_cnt 0 2006.257.21:28:39.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:39.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:39.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:39.85#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:28:39.85#ibcon#first serial, iclass 24, count 0 2006.257.21:28:39.85#ibcon#enter sib2, iclass 24, count 0 2006.257.21:28:39.85#ibcon#flushed, iclass 24, count 0 2006.257.21:28:39.85#ibcon#about to write, iclass 24, count 0 2006.257.21:28:39.85#ibcon#wrote, iclass 24, count 0 2006.257.21:28:39.85#ibcon#about to read 3, iclass 24, count 0 2006.257.21:28:39.87#ibcon#read 3, iclass 24, count 0 2006.257.21:28:39.87#ibcon#about to read 4, iclass 24, count 0 2006.257.21:28:39.87#ibcon#read 4, iclass 24, count 0 2006.257.21:28:39.87#ibcon#about to read 5, iclass 24, count 0 2006.257.21:28:39.87#ibcon#read 5, iclass 24, count 0 2006.257.21:28:39.87#ibcon#about to read 6, iclass 24, count 0 2006.257.21:28:39.87#ibcon#read 6, iclass 24, count 0 2006.257.21:28:39.87#ibcon#end of sib2, iclass 24, count 0 2006.257.21:28:39.87#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:28:39.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:28:39.87#ibcon#[25=BW32\r\n] 2006.257.21:28:39.87#ibcon#*before write, iclass 24, count 0 2006.257.21:28:39.87#ibcon#enter sib2, iclass 24, count 0 2006.257.21:28:39.87#ibcon#flushed, iclass 24, count 0 2006.257.21:28:39.87#ibcon#about to write, iclass 24, count 0 2006.257.21:28:39.87#ibcon#wrote, iclass 24, count 0 2006.257.21:28:39.87#ibcon#about to read 3, iclass 24, count 0 2006.257.21:28:39.90#ibcon#read 3, iclass 24, count 0 2006.257.21:28:39.90#ibcon#about to read 4, iclass 24, count 0 2006.257.21:28:39.90#ibcon#read 4, iclass 24, count 0 2006.257.21:28:39.90#ibcon#about to read 5, iclass 24, count 0 2006.257.21:28:39.90#ibcon#read 5, iclass 24, count 0 2006.257.21:28:39.90#ibcon#about to read 6, iclass 24, count 0 2006.257.21:28:39.90#ibcon#read 6, iclass 24, count 0 2006.257.21:28:39.90#ibcon#end of sib2, iclass 24, count 0 2006.257.21:28:39.90#ibcon#*after write, iclass 24, count 0 2006.257.21:28:39.90#ibcon#*before return 0, iclass 24, count 0 2006.257.21:28:39.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:39.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:28:39.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:28:39.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:28:39.90$vck44/vbbw=wide 2006.257.21:28:39.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.21:28:39.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.21:28:39.90#ibcon#ireg 8 cls_cnt 0 2006.257.21:28:39.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:28:39.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:28:39.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:28:39.97#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:28:39.97#ibcon#first serial, iclass 26, count 0 2006.257.21:28:39.97#ibcon#enter sib2, iclass 26, count 0 2006.257.21:28:39.97#ibcon#flushed, iclass 26, count 0 2006.257.21:28:39.97#ibcon#about to write, iclass 26, count 0 2006.257.21:28:39.97#ibcon#wrote, iclass 26, count 0 2006.257.21:28:39.97#ibcon#about to read 3, iclass 26, count 0 2006.257.21:28:39.99#ibcon#read 3, iclass 26, count 0 2006.257.21:28:39.99#ibcon#about to read 4, iclass 26, count 0 2006.257.21:28:39.99#ibcon#read 4, iclass 26, count 0 2006.257.21:28:39.99#ibcon#about to read 5, iclass 26, count 0 2006.257.21:28:39.99#ibcon#read 5, iclass 26, count 0 2006.257.21:28:39.99#ibcon#about to read 6, iclass 26, count 0 2006.257.21:28:39.99#ibcon#read 6, iclass 26, count 0 2006.257.21:28:39.99#ibcon#end of sib2, iclass 26, count 0 2006.257.21:28:39.99#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:28:39.99#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:28:39.99#ibcon#[27=BW32\r\n] 2006.257.21:28:39.99#ibcon#*before write, iclass 26, count 0 2006.257.21:28:39.99#ibcon#enter sib2, iclass 26, count 0 2006.257.21:28:39.99#ibcon#flushed, iclass 26, count 0 2006.257.21:28:39.99#ibcon#about to write, iclass 26, count 0 2006.257.21:28:39.99#ibcon#wrote, iclass 26, count 0 2006.257.21:28:39.99#ibcon#about to read 3, iclass 26, count 0 2006.257.21:28:40.02#ibcon#read 3, iclass 26, count 0 2006.257.21:28:40.02#ibcon#about to read 4, iclass 26, count 0 2006.257.21:28:40.02#ibcon#read 4, iclass 26, count 0 2006.257.21:28:40.02#ibcon#about to read 5, iclass 26, count 0 2006.257.21:28:40.02#ibcon#read 5, iclass 26, count 0 2006.257.21:28:40.02#ibcon#about to read 6, iclass 26, count 0 2006.257.21:28:40.02#ibcon#read 6, iclass 26, count 0 2006.257.21:28:40.02#ibcon#end of sib2, iclass 26, count 0 2006.257.21:28:40.02#ibcon#*after write, iclass 26, count 0 2006.257.21:28:40.02#ibcon#*before return 0, iclass 26, count 0 2006.257.21:28:40.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:28:40.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:28:40.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:28:40.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:28:40.02$setupk4/ifdk4 2006.257.21:28:40.02$ifdk4/lo= 2006.257.21:28:40.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.21:28:40.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.21:28:40.02$ifdk4/patch= 2006.257.21:28:40.02$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.21:28:40.02$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.21:28:40.02$setupk4/!*+20s 2006.257.21:28:46.35#abcon#<5=/14 1.1 2.9 17.81 951015.5\r\n> 2006.257.21:28:46.37#abcon#{5=INTERFACE CLEAR} 2006.257.21:28:46.43#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:28:54.52$setupk4/"tpicd 2006.257.21:28:54.52$setupk4/echo=off 2006.257.21:28:54.52$setupk4/xlog=off 2006.257.21:28:54.52:!2006.257.21:30:04 2006.257.21:28:55.14#trakl#Source acquired 2006.257.21:28:57.14#flagr#flagr/antenna,acquired 2006.257.21:30:04.00:preob 2006.257.21:30:04.14/onsource/TRACKING 2006.257.21:30:04.14:!2006.257.21:30:14 2006.257.21:30:14.00:"tape 2006.257.21:30:14.00:"st=record 2006.257.21:30:14.00:data_valid=on 2006.257.21:30:14.00:midob 2006.257.21:30:15.14/onsource/TRACKING 2006.257.21:30:15.14/wx/17.82,1015.5,95 2006.257.21:30:15.28/cable/+6.4847E-03 2006.257.21:30:16.37/va/01,08,usb,yes,32,34 2006.257.21:30:16.37/va/02,07,usb,yes,35,35 2006.257.21:30:16.37/va/03,08,usb,yes,31,33 2006.257.21:30:16.37/va/04,07,usb,yes,35,37 2006.257.21:30:16.37/va/05,04,usb,yes,32,32 2006.257.21:30:16.37/va/06,04,usb,yes,35,35 2006.257.21:30:16.37/va/07,04,usb,yes,36,37 2006.257.21:30:16.37/va/08,04,usb,yes,30,37 2006.257.21:30:16.60/valo/01,524.99,yes,locked 2006.257.21:30:16.60/valo/02,534.99,yes,locked 2006.257.21:30:16.60/valo/03,564.99,yes,locked 2006.257.21:30:16.60/valo/04,624.99,yes,locked 2006.257.21:30:16.60/valo/05,734.99,yes,locked 2006.257.21:30:16.60/valo/06,814.99,yes,locked 2006.257.21:30:16.60/valo/07,864.99,yes,locked 2006.257.21:30:16.60/valo/08,884.99,yes,locked 2006.257.21:30:17.69/vb/01,04,usb,yes,31,28 2006.257.21:30:17.69/vb/02,05,usb,yes,29,29 2006.257.21:30:17.69/vb/03,04,usb,yes,30,33 2006.257.21:30:17.69/vb/04,05,usb,yes,30,29 2006.257.21:30:17.69/vb/05,04,usb,yes,26,29 2006.257.21:30:17.69/vb/06,04,usb,yes,31,27 2006.257.21:30:17.69/vb/07,04,usb,yes,31,31 2006.257.21:30:17.69/vb/08,04,usb,yes,28,32 2006.257.21:30:17.92/vblo/01,629.99,yes,locked 2006.257.21:30:17.92/vblo/02,634.99,yes,locked 2006.257.21:30:17.92/vblo/03,649.99,yes,locked 2006.257.21:30:17.92/vblo/04,679.99,yes,locked 2006.257.21:30:17.92/vblo/05,709.99,yes,locked 2006.257.21:30:17.92/vblo/06,719.99,yes,locked 2006.257.21:30:17.92/vblo/07,734.99,yes,locked 2006.257.21:30:17.92/vblo/08,744.99,yes,locked 2006.257.21:30:18.07/vabw/8 2006.257.21:30:18.22/vbbw/8 2006.257.21:30:18.31/xfe/off,on,15.2 2006.257.21:30:18.69/ifatt/23,28,28,28 2006.257.21:30:19.08/fmout-gps/S +4.57E-07 2006.257.21:30:19.12:!2006.257.21:31:14 2006.257.21:31:14.01:data_valid=off 2006.257.21:31:14.01:"et 2006.257.21:31:14.01:!+3s 2006.257.21:31:17.02:"tape 2006.257.21:31:17.02:postob 2006.257.21:31:17.16/cable/+6.4837E-03 2006.257.21:31:17.16/wx/17.82,1015.5,95 2006.257.21:31:18.08/fmout-gps/S +4.56E-07 2006.257.21:31:18.08:scan_name=257-2134,jd0609,50 2006.257.21:31:18.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.21:31:18.14#flagr#flagr/antenna,new-source 2006.257.21:31:19.14:checkk5 2006.257.21:31:19.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.21:31:19.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.21:31:20.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.21:31:20.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.21:31:20.84/chk_obsdata//k5ts1/T2572130??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.21:31:21.18/chk_obsdata//k5ts2/T2572130??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.21:31:21.51/chk_obsdata//k5ts3/T2572130??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.21:31:21.84/chk_obsdata//k5ts4/T2572130??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.21:31:22.49/k5log//k5ts1_log_newline 2006.257.21:31:23.17/k5log//k5ts2_log_newline 2006.257.21:31:23.82/k5log//k5ts3_log_newline 2006.257.21:31:24.47/k5log//k5ts4_log_newline 2006.257.21:31:24.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.21:31:24.50:setupk4=1 2006.257.21:31:24.50$setupk4/echo=on 2006.257.21:31:24.50$setupk4/pcalon 2006.257.21:31:24.50$pcalon/"no phase cal control is implemented here 2006.257.21:31:24.50$setupk4/"tpicd=stop 2006.257.21:31:24.50$setupk4/"rec=synch_on 2006.257.21:31:24.50$setupk4/"rec_mode=128 2006.257.21:31:24.50$setupk4/!* 2006.257.21:31:24.50$setupk4/recpk4 2006.257.21:31:24.50$recpk4/recpatch= 2006.257.21:31:24.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.21:31:24.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.21:31:24.50$setupk4/vck44 2006.257.21:31:24.50$vck44/valo=1,524.99 2006.257.21:31:24.50#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.21:31:24.50#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.21:31:24.50#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:24.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:24.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:24.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:24.50#ibcon#enter wrdev, iclass 23, count 0 2006.257.21:31:24.50#ibcon#first serial, iclass 23, count 0 2006.257.21:31:24.50#ibcon#enter sib2, iclass 23, count 0 2006.257.21:31:24.50#ibcon#flushed, iclass 23, count 0 2006.257.21:31:24.50#ibcon#about to write, iclass 23, count 0 2006.257.21:31:24.50#ibcon#wrote, iclass 23, count 0 2006.257.21:31:24.50#ibcon#about to read 3, iclass 23, count 0 2006.257.21:31:24.52#ibcon#read 3, iclass 23, count 0 2006.257.21:31:24.52#ibcon#about to read 4, iclass 23, count 0 2006.257.21:31:24.52#ibcon#read 4, iclass 23, count 0 2006.257.21:31:24.52#ibcon#about to read 5, iclass 23, count 0 2006.257.21:31:24.52#ibcon#read 5, iclass 23, count 0 2006.257.21:31:24.52#ibcon#about to read 6, iclass 23, count 0 2006.257.21:31:24.52#ibcon#read 6, iclass 23, count 0 2006.257.21:31:24.52#ibcon#end of sib2, iclass 23, count 0 2006.257.21:31:24.52#ibcon#*mode == 0, iclass 23, count 0 2006.257.21:31:24.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.21:31:24.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.21:31:24.52#ibcon#*before write, iclass 23, count 0 2006.257.21:31:24.52#ibcon#enter sib2, iclass 23, count 0 2006.257.21:31:24.52#ibcon#flushed, iclass 23, count 0 2006.257.21:31:24.52#ibcon#about to write, iclass 23, count 0 2006.257.21:31:24.52#ibcon#wrote, iclass 23, count 0 2006.257.21:31:24.52#ibcon#about to read 3, iclass 23, count 0 2006.257.21:31:24.57#ibcon#read 3, iclass 23, count 0 2006.257.21:31:24.57#ibcon#about to read 4, iclass 23, count 0 2006.257.21:31:24.57#ibcon#read 4, iclass 23, count 0 2006.257.21:31:24.57#ibcon#about to read 5, iclass 23, count 0 2006.257.21:31:24.57#ibcon#read 5, iclass 23, count 0 2006.257.21:31:24.57#ibcon#about to read 6, iclass 23, count 0 2006.257.21:31:24.57#ibcon#read 6, iclass 23, count 0 2006.257.21:31:24.57#ibcon#end of sib2, iclass 23, count 0 2006.257.21:31:24.57#ibcon#*after write, iclass 23, count 0 2006.257.21:31:24.57#ibcon#*before return 0, iclass 23, count 0 2006.257.21:31:24.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:24.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:24.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.21:31:24.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.21:31:24.57$vck44/va=1,8 2006.257.21:31:24.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.21:31:24.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.21:31:24.57#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:24.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:24.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:24.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:24.57#ibcon#enter wrdev, iclass 25, count 2 2006.257.21:31:24.57#ibcon#first serial, iclass 25, count 2 2006.257.21:31:24.57#ibcon#enter sib2, iclass 25, count 2 2006.257.21:31:24.57#ibcon#flushed, iclass 25, count 2 2006.257.21:31:24.57#ibcon#about to write, iclass 25, count 2 2006.257.21:31:24.57#ibcon#wrote, iclass 25, count 2 2006.257.21:31:24.57#ibcon#about to read 3, iclass 25, count 2 2006.257.21:31:24.59#ibcon#read 3, iclass 25, count 2 2006.257.21:31:24.59#ibcon#about to read 4, iclass 25, count 2 2006.257.21:31:24.59#ibcon#read 4, iclass 25, count 2 2006.257.21:31:24.59#ibcon#about to read 5, iclass 25, count 2 2006.257.21:31:24.59#ibcon#read 5, iclass 25, count 2 2006.257.21:31:24.59#ibcon#about to read 6, iclass 25, count 2 2006.257.21:31:24.59#ibcon#read 6, iclass 25, count 2 2006.257.21:31:24.59#ibcon#end of sib2, iclass 25, count 2 2006.257.21:31:24.59#ibcon#*mode == 0, iclass 25, count 2 2006.257.21:31:24.59#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.21:31:24.59#ibcon#[25=AT01-08\r\n] 2006.257.21:31:24.59#ibcon#*before write, iclass 25, count 2 2006.257.21:31:24.59#ibcon#enter sib2, iclass 25, count 2 2006.257.21:31:24.59#ibcon#flushed, iclass 25, count 2 2006.257.21:31:24.59#ibcon#about to write, iclass 25, count 2 2006.257.21:31:24.59#ibcon#wrote, iclass 25, count 2 2006.257.21:31:24.59#ibcon#about to read 3, iclass 25, count 2 2006.257.21:31:24.62#ibcon#read 3, iclass 25, count 2 2006.257.21:31:24.62#ibcon#about to read 4, iclass 25, count 2 2006.257.21:31:24.62#ibcon#read 4, iclass 25, count 2 2006.257.21:31:24.62#ibcon#about to read 5, iclass 25, count 2 2006.257.21:31:24.62#ibcon#read 5, iclass 25, count 2 2006.257.21:31:24.62#ibcon#about to read 6, iclass 25, count 2 2006.257.21:31:24.62#ibcon#read 6, iclass 25, count 2 2006.257.21:31:24.62#ibcon#end of sib2, iclass 25, count 2 2006.257.21:31:24.62#ibcon#*after write, iclass 25, count 2 2006.257.21:31:24.62#ibcon#*before return 0, iclass 25, count 2 2006.257.21:31:24.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:24.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:24.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.21:31:24.62#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:24.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:24.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:24.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:24.74#ibcon#enter wrdev, iclass 25, count 0 2006.257.21:31:24.74#ibcon#first serial, iclass 25, count 0 2006.257.21:31:24.74#ibcon#enter sib2, iclass 25, count 0 2006.257.21:31:24.74#ibcon#flushed, iclass 25, count 0 2006.257.21:31:24.74#ibcon#about to write, iclass 25, count 0 2006.257.21:31:24.74#ibcon#wrote, iclass 25, count 0 2006.257.21:31:24.74#ibcon#about to read 3, iclass 25, count 0 2006.257.21:31:24.76#ibcon#read 3, iclass 25, count 0 2006.257.21:31:24.76#ibcon#about to read 4, iclass 25, count 0 2006.257.21:31:24.76#ibcon#read 4, iclass 25, count 0 2006.257.21:31:24.76#ibcon#about to read 5, iclass 25, count 0 2006.257.21:31:24.76#ibcon#read 5, iclass 25, count 0 2006.257.21:31:24.76#ibcon#about to read 6, iclass 25, count 0 2006.257.21:31:24.76#ibcon#read 6, iclass 25, count 0 2006.257.21:31:24.76#ibcon#end of sib2, iclass 25, count 0 2006.257.21:31:24.76#ibcon#*mode == 0, iclass 25, count 0 2006.257.21:31:24.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.21:31:24.76#ibcon#[25=USB\r\n] 2006.257.21:31:24.76#ibcon#*before write, iclass 25, count 0 2006.257.21:31:24.76#ibcon#enter sib2, iclass 25, count 0 2006.257.21:31:24.76#ibcon#flushed, iclass 25, count 0 2006.257.21:31:24.76#ibcon#about to write, iclass 25, count 0 2006.257.21:31:24.76#ibcon#wrote, iclass 25, count 0 2006.257.21:31:24.76#ibcon#about to read 3, iclass 25, count 0 2006.257.21:31:24.79#ibcon#read 3, iclass 25, count 0 2006.257.21:31:24.79#ibcon#about to read 4, iclass 25, count 0 2006.257.21:31:24.79#ibcon#read 4, iclass 25, count 0 2006.257.21:31:24.79#ibcon#about to read 5, iclass 25, count 0 2006.257.21:31:24.79#ibcon#read 5, iclass 25, count 0 2006.257.21:31:24.79#ibcon#about to read 6, iclass 25, count 0 2006.257.21:31:24.79#ibcon#read 6, iclass 25, count 0 2006.257.21:31:24.79#ibcon#end of sib2, iclass 25, count 0 2006.257.21:31:24.79#ibcon#*after write, iclass 25, count 0 2006.257.21:31:24.79#ibcon#*before return 0, iclass 25, count 0 2006.257.21:31:24.79#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:24.79#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:24.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.21:31:24.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.21:31:24.79$vck44/valo=2,534.99 2006.257.21:31:24.79#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.21:31:24.79#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.21:31:24.79#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:24.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:24.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:24.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:24.79#ibcon#enter wrdev, iclass 27, count 0 2006.257.21:31:24.79#ibcon#first serial, iclass 27, count 0 2006.257.21:31:24.79#ibcon#enter sib2, iclass 27, count 0 2006.257.21:31:24.79#ibcon#flushed, iclass 27, count 0 2006.257.21:31:24.79#ibcon#about to write, iclass 27, count 0 2006.257.21:31:24.79#ibcon#wrote, iclass 27, count 0 2006.257.21:31:24.79#ibcon#about to read 3, iclass 27, count 0 2006.257.21:31:24.81#ibcon#read 3, iclass 27, count 0 2006.257.21:31:24.81#ibcon#about to read 4, iclass 27, count 0 2006.257.21:31:24.81#ibcon#read 4, iclass 27, count 0 2006.257.21:31:24.81#ibcon#about to read 5, iclass 27, count 0 2006.257.21:31:24.81#ibcon#read 5, iclass 27, count 0 2006.257.21:31:24.81#ibcon#about to read 6, iclass 27, count 0 2006.257.21:31:24.81#ibcon#read 6, iclass 27, count 0 2006.257.21:31:24.81#ibcon#end of sib2, iclass 27, count 0 2006.257.21:31:24.81#ibcon#*mode == 0, iclass 27, count 0 2006.257.21:31:24.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.21:31:24.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.21:31:24.81#ibcon#*before write, iclass 27, count 0 2006.257.21:31:24.81#ibcon#enter sib2, iclass 27, count 0 2006.257.21:31:24.81#ibcon#flushed, iclass 27, count 0 2006.257.21:31:24.81#ibcon#about to write, iclass 27, count 0 2006.257.21:31:24.81#ibcon#wrote, iclass 27, count 0 2006.257.21:31:24.81#ibcon#about to read 3, iclass 27, count 0 2006.257.21:31:24.85#ibcon#read 3, iclass 27, count 0 2006.257.21:31:24.85#ibcon#about to read 4, iclass 27, count 0 2006.257.21:31:24.85#ibcon#read 4, iclass 27, count 0 2006.257.21:31:24.85#ibcon#about to read 5, iclass 27, count 0 2006.257.21:31:24.85#ibcon#read 5, iclass 27, count 0 2006.257.21:31:24.85#ibcon#about to read 6, iclass 27, count 0 2006.257.21:31:24.85#ibcon#read 6, iclass 27, count 0 2006.257.21:31:24.85#ibcon#end of sib2, iclass 27, count 0 2006.257.21:31:24.85#ibcon#*after write, iclass 27, count 0 2006.257.21:31:24.85#ibcon#*before return 0, iclass 27, count 0 2006.257.21:31:24.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:24.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:24.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.21:31:24.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.21:31:24.85$vck44/va=2,7 2006.257.21:31:24.85#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.21:31:24.85#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.21:31:24.85#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:24.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:24.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:24.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:24.91#ibcon#enter wrdev, iclass 29, count 2 2006.257.21:31:24.91#ibcon#first serial, iclass 29, count 2 2006.257.21:31:24.91#ibcon#enter sib2, iclass 29, count 2 2006.257.21:31:24.91#ibcon#flushed, iclass 29, count 2 2006.257.21:31:24.91#ibcon#about to write, iclass 29, count 2 2006.257.21:31:24.91#ibcon#wrote, iclass 29, count 2 2006.257.21:31:24.91#ibcon#about to read 3, iclass 29, count 2 2006.257.21:31:24.93#ibcon#read 3, iclass 29, count 2 2006.257.21:31:24.93#ibcon#about to read 4, iclass 29, count 2 2006.257.21:31:24.93#ibcon#read 4, iclass 29, count 2 2006.257.21:31:24.93#ibcon#about to read 5, iclass 29, count 2 2006.257.21:31:24.93#ibcon#read 5, iclass 29, count 2 2006.257.21:31:24.93#ibcon#about to read 6, iclass 29, count 2 2006.257.21:31:24.93#ibcon#read 6, iclass 29, count 2 2006.257.21:31:24.93#ibcon#end of sib2, iclass 29, count 2 2006.257.21:31:24.93#ibcon#*mode == 0, iclass 29, count 2 2006.257.21:31:24.93#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.21:31:24.93#ibcon#[25=AT02-07\r\n] 2006.257.21:31:24.93#ibcon#*before write, iclass 29, count 2 2006.257.21:31:24.93#ibcon#enter sib2, iclass 29, count 2 2006.257.21:31:24.93#ibcon#flushed, iclass 29, count 2 2006.257.21:31:24.93#ibcon#about to write, iclass 29, count 2 2006.257.21:31:24.93#ibcon#wrote, iclass 29, count 2 2006.257.21:31:24.93#ibcon#about to read 3, iclass 29, count 2 2006.257.21:31:24.96#ibcon#read 3, iclass 29, count 2 2006.257.21:31:24.96#ibcon#about to read 4, iclass 29, count 2 2006.257.21:31:24.96#ibcon#read 4, iclass 29, count 2 2006.257.21:31:24.96#ibcon#about to read 5, iclass 29, count 2 2006.257.21:31:24.96#ibcon#read 5, iclass 29, count 2 2006.257.21:31:24.96#ibcon#about to read 6, iclass 29, count 2 2006.257.21:31:24.96#ibcon#read 6, iclass 29, count 2 2006.257.21:31:24.96#ibcon#end of sib2, iclass 29, count 2 2006.257.21:31:24.96#ibcon#*after write, iclass 29, count 2 2006.257.21:31:24.96#ibcon#*before return 0, iclass 29, count 2 2006.257.21:31:24.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:24.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:24.96#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.21:31:24.96#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:24.96#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:25.08#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:25.08#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:25.08#ibcon#enter wrdev, iclass 29, count 0 2006.257.21:31:25.08#ibcon#first serial, iclass 29, count 0 2006.257.21:31:25.08#ibcon#enter sib2, iclass 29, count 0 2006.257.21:31:25.08#ibcon#flushed, iclass 29, count 0 2006.257.21:31:25.08#ibcon#about to write, iclass 29, count 0 2006.257.21:31:25.08#ibcon#wrote, iclass 29, count 0 2006.257.21:31:25.08#ibcon#about to read 3, iclass 29, count 0 2006.257.21:31:25.10#ibcon#read 3, iclass 29, count 0 2006.257.21:31:25.10#ibcon#about to read 4, iclass 29, count 0 2006.257.21:31:25.10#ibcon#read 4, iclass 29, count 0 2006.257.21:31:25.10#ibcon#about to read 5, iclass 29, count 0 2006.257.21:31:25.10#ibcon#read 5, iclass 29, count 0 2006.257.21:31:25.10#ibcon#about to read 6, iclass 29, count 0 2006.257.21:31:25.10#ibcon#read 6, iclass 29, count 0 2006.257.21:31:25.10#ibcon#end of sib2, iclass 29, count 0 2006.257.21:31:25.10#ibcon#*mode == 0, iclass 29, count 0 2006.257.21:31:25.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.21:31:25.10#ibcon#[25=USB\r\n] 2006.257.21:31:25.10#ibcon#*before write, iclass 29, count 0 2006.257.21:31:25.10#ibcon#enter sib2, iclass 29, count 0 2006.257.21:31:25.10#ibcon#flushed, iclass 29, count 0 2006.257.21:31:25.10#ibcon#about to write, iclass 29, count 0 2006.257.21:31:25.10#ibcon#wrote, iclass 29, count 0 2006.257.21:31:25.10#ibcon#about to read 3, iclass 29, count 0 2006.257.21:31:25.13#ibcon#read 3, iclass 29, count 0 2006.257.21:31:25.13#ibcon#about to read 4, iclass 29, count 0 2006.257.21:31:25.13#ibcon#read 4, iclass 29, count 0 2006.257.21:31:25.13#ibcon#about to read 5, iclass 29, count 0 2006.257.21:31:25.13#ibcon#read 5, iclass 29, count 0 2006.257.21:31:25.13#ibcon#about to read 6, iclass 29, count 0 2006.257.21:31:25.13#ibcon#read 6, iclass 29, count 0 2006.257.21:31:25.13#ibcon#end of sib2, iclass 29, count 0 2006.257.21:31:25.13#ibcon#*after write, iclass 29, count 0 2006.257.21:31:25.13#ibcon#*before return 0, iclass 29, count 0 2006.257.21:31:25.13#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:25.13#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:25.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.21:31:25.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.21:31:25.13$vck44/valo=3,564.99 2006.257.21:31:25.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.21:31:25.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.21:31:25.13#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:25.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:25.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:25.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:25.13#ibcon#enter wrdev, iclass 31, count 0 2006.257.21:31:25.13#ibcon#first serial, iclass 31, count 0 2006.257.21:31:25.13#ibcon#enter sib2, iclass 31, count 0 2006.257.21:31:25.13#ibcon#flushed, iclass 31, count 0 2006.257.21:31:25.13#ibcon#about to write, iclass 31, count 0 2006.257.21:31:25.13#ibcon#wrote, iclass 31, count 0 2006.257.21:31:25.13#ibcon#about to read 3, iclass 31, count 0 2006.257.21:31:25.15#ibcon#read 3, iclass 31, count 0 2006.257.21:31:25.15#ibcon#about to read 4, iclass 31, count 0 2006.257.21:31:25.15#ibcon#read 4, iclass 31, count 0 2006.257.21:31:25.15#ibcon#about to read 5, iclass 31, count 0 2006.257.21:31:25.15#ibcon#read 5, iclass 31, count 0 2006.257.21:31:25.15#ibcon#about to read 6, iclass 31, count 0 2006.257.21:31:25.15#ibcon#read 6, iclass 31, count 0 2006.257.21:31:25.15#ibcon#end of sib2, iclass 31, count 0 2006.257.21:31:25.15#ibcon#*mode == 0, iclass 31, count 0 2006.257.21:31:25.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.21:31:25.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.21:31:25.15#ibcon#*before write, iclass 31, count 0 2006.257.21:31:25.15#ibcon#enter sib2, iclass 31, count 0 2006.257.21:31:25.15#ibcon#flushed, iclass 31, count 0 2006.257.21:31:25.15#ibcon#about to write, iclass 31, count 0 2006.257.21:31:25.15#ibcon#wrote, iclass 31, count 0 2006.257.21:31:25.15#ibcon#about to read 3, iclass 31, count 0 2006.257.21:31:25.19#ibcon#read 3, iclass 31, count 0 2006.257.21:31:25.19#ibcon#about to read 4, iclass 31, count 0 2006.257.21:31:25.19#ibcon#read 4, iclass 31, count 0 2006.257.21:31:25.19#ibcon#about to read 5, iclass 31, count 0 2006.257.21:31:25.19#ibcon#read 5, iclass 31, count 0 2006.257.21:31:25.19#ibcon#about to read 6, iclass 31, count 0 2006.257.21:31:25.19#ibcon#read 6, iclass 31, count 0 2006.257.21:31:25.19#ibcon#end of sib2, iclass 31, count 0 2006.257.21:31:25.19#ibcon#*after write, iclass 31, count 0 2006.257.21:31:25.19#ibcon#*before return 0, iclass 31, count 0 2006.257.21:31:25.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:25.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:25.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.21:31:25.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.21:31:25.19$vck44/va=3,8 2006.257.21:31:25.19#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.21:31:25.19#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.21:31:25.19#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:25.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:25.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:25.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:25.25#ibcon#enter wrdev, iclass 33, count 2 2006.257.21:31:25.25#ibcon#first serial, iclass 33, count 2 2006.257.21:31:25.25#ibcon#enter sib2, iclass 33, count 2 2006.257.21:31:25.25#ibcon#flushed, iclass 33, count 2 2006.257.21:31:25.25#ibcon#about to write, iclass 33, count 2 2006.257.21:31:25.25#ibcon#wrote, iclass 33, count 2 2006.257.21:31:25.25#ibcon#about to read 3, iclass 33, count 2 2006.257.21:31:25.27#ibcon#read 3, iclass 33, count 2 2006.257.21:31:25.27#ibcon#about to read 4, iclass 33, count 2 2006.257.21:31:25.27#ibcon#read 4, iclass 33, count 2 2006.257.21:31:25.27#ibcon#about to read 5, iclass 33, count 2 2006.257.21:31:25.27#ibcon#read 5, iclass 33, count 2 2006.257.21:31:25.27#ibcon#about to read 6, iclass 33, count 2 2006.257.21:31:25.27#ibcon#read 6, iclass 33, count 2 2006.257.21:31:25.27#ibcon#end of sib2, iclass 33, count 2 2006.257.21:31:25.27#ibcon#*mode == 0, iclass 33, count 2 2006.257.21:31:25.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.21:31:25.27#ibcon#[25=AT03-08\r\n] 2006.257.21:31:25.27#ibcon#*before write, iclass 33, count 2 2006.257.21:31:25.27#ibcon#enter sib2, iclass 33, count 2 2006.257.21:31:25.27#ibcon#flushed, iclass 33, count 2 2006.257.21:31:25.27#ibcon#about to write, iclass 33, count 2 2006.257.21:31:25.27#ibcon#wrote, iclass 33, count 2 2006.257.21:31:25.27#ibcon#about to read 3, iclass 33, count 2 2006.257.21:31:25.30#ibcon#read 3, iclass 33, count 2 2006.257.21:31:25.30#ibcon#about to read 4, iclass 33, count 2 2006.257.21:31:25.30#ibcon#read 4, iclass 33, count 2 2006.257.21:31:25.30#ibcon#about to read 5, iclass 33, count 2 2006.257.21:31:25.30#ibcon#read 5, iclass 33, count 2 2006.257.21:31:25.30#ibcon#about to read 6, iclass 33, count 2 2006.257.21:31:25.30#ibcon#read 6, iclass 33, count 2 2006.257.21:31:25.30#ibcon#end of sib2, iclass 33, count 2 2006.257.21:31:25.30#ibcon#*after write, iclass 33, count 2 2006.257.21:31:25.30#ibcon#*before return 0, iclass 33, count 2 2006.257.21:31:25.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:25.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:25.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.21:31:25.30#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:25.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:25.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:25.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:25.42#ibcon#enter wrdev, iclass 33, count 0 2006.257.21:31:25.42#ibcon#first serial, iclass 33, count 0 2006.257.21:31:25.42#ibcon#enter sib2, iclass 33, count 0 2006.257.21:31:25.42#ibcon#flushed, iclass 33, count 0 2006.257.21:31:25.42#ibcon#about to write, iclass 33, count 0 2006.257.21:31:25.42#ibcon#wrote, iclass 33, count 0 2006.257.21:31:25.42#ibcon#about to read 3, iclass 33, count 0 2006.257.21:31:25.44#ibcon#read 3, iclass 33, count 0 2006.257.21:31:25.44#ibcon#about to read 4, iclass 33, count 0 2006.257.21:31:25.44#ibcon#read 4, iclass 33, count 0 2006.257.21:31:25.44#ibcon#about to read 5, iclass 33, count 0 2006.257.21:31:25.44#ibcon#read 5, iclass 33, count 0 2006.257.21:31:25.44#ibcon#about to read 6, iclass 33, count 0 2006.257.21:31:25.44#ibcon#read 6, iclass 33, count 0 2006.257.21:31:25.44#ibcon#end of sib2, iclass 33, count 0 2006.257.21:31:25.44#ibcon#*mode == 0, iclass 33, count 0 2006.257.21:31:25.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.21:31:25.44#ibcon#[25=USB\r\n] 2006.257.21:31:25.44#ibcon#*before write, iclass 33, count 0 2006.257.21:31:25.44#ibcon#enter sib2, iclass 33, count 0 2006.257.21:31:25.44#ibcon#flushed, iclass 33, count 0 2006.257.21:31:25.44#ibcon#about to write, iclass 33, count 0 2006.257.21:31:25.44#ibcon#wrote, iclass 33, count 0 2006.257.21:31:25.44#ibcon#about to read 3, iclass 33, count 0 2006.257.21:31:25.47#ibcon#read 3, iclass 33, count 0 2006.257.21:31:25.47#ibcon#about to read 4, iclass 33, count 0 2006.257.21:31:25.47#ibcon#read 4, iclass 33, count 0 2006.257.21:31:25.47#ibcon#about to read 5, iclass 33, count 0 2006.257.21:31:25.47#ibcon#read 5, iclass 33, count 0 2006.257.21:31:25.47#ibcon#about to read 6, iclass 33, count 0 2006.257.21:31:25.47#ibcon#read 6, iclass 33, count 0 2006.257.21:31:25.47#ibcon#end of sib2, iclass 33, count 0 2006.257.21:31:25.47#ibcon#*after write, iclass 33, count 0 2006.257.21:31:25.47#ibcon#*before return 0, iclass 33, count 0 2006.257.21:31:25.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:25.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:25.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.21:31:25.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.21:31:25.47$vck44/valo=4,624.99 2006.257.21:31:25.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.21:31:25.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.21:31:25.47#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:25.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:25.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:25.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:25.47#ibcon#enter wrdev, iclass 35, count 0 2006.257.21:31:25.47#ibcon#first serial, iclass 35, count 0 2006.257.21:31:25.47#ibcon#enter sib2, iclass 35, count 0 2006.257.21:31:25.47#ibcon#flushed, iclass 35, count 0 2006.257.21:31:25.47#ibcon#about to write, iclass 35, count 0 2006.257.21:31:25.47#ibcon#wrote, iclass 35, count 0 2006.257.21:31:25.47#ibcon#about to read 3, iclass 35, count 0 2006.257.21:31:25.49#ibcon#read 3, iclass 35, count 0 2006.257.21:31:25.49#ibcon#about to read 4, iclass 35, count 0 2006.257.21:31:25.49#ibcon#read 4, iclass 35, count 0 2006.257.21:31:25.49#ibcon#about to read 5, iclass 35, count 0 2006.257.21:31:25.49#ibcon#read 5, iclass 35, count 0 2006.257.21:31:25.49#ibcon#about to read 6, iclass 35, count 0 2006.257.21:31:25.49#ibcon#read 6, iclass 35, count 0 2006.257.21:31:25.49#ibcon#end of sib2, iclass 35, count 0 2006.257.21:31:25.49#ibcon#*mode == 0, iclass 35, count 0 2006.257.21:31:25.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.21:31:25.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.21:31:25.49#ibcon#*before write, iclass 35, count 0 2006.257.21:31:25.49#ibcon#enter sib2, iclass 35, count 0 2006.257.21:31:25.49#ibcon#flushed, iclass 35, count 0 2006.257.21:31:25.49#ibcon#about to write, iclass 35, count 0 2006.257.21:31:25.49#ibcon#wrote, iclass 35, count 0 2006.257.21:31:25.49#ibcon#about to read 3, iclass 35, count 0 2006.257.21:31:25.53#ibcon#read 3, iclass 35, count 0 2006.257.21:31:25.53#ibcon#about to read 4, iclass 35, count 0 2006.257.21:31:25.53#ibcon#read 4, iclass 35, count 0 2006.257.21:31:25.53#ibcon#about to read 5, iclass 35, count 0 2006.257.21:31:25.53#ibcon#read 5, iclass 35, count 0 2006.257.21:31:25.53#ibcon#about to read 6, iclass 35, count 0 2006.257.21:31:25.53#ibcon#read 6, iclass 35, count 0 2006.257.21:31:25.53#ibcon#end of sib2, iclass 35, count 0 2006.257.21:31:25.53#ibcon#*after write, iclass 35, count 0 2006.257.21:31:25.53#ibcon#*before return 0, iclass 35, count 0 2006.257.21:31:25.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:25.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:25.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.21:31:25.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.21:31:25.53$vck44/va=4,7 2006.257.21:31:25.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.21:31:25.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.21:31:25.53#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:25.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:25.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:25.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:25.59#ibcon#enter wrdev, iclass 37, count 2 2006.257.21:31:25.59#ibcon#first serial, iclass 37, count 2 2006.257.21:31:25.59#ibcon#enter sib2, iclass 37, count 2 2006.257.21:31:25.59#ibcon#flushed, iclass 37, count 2 2006.257.21:31:25.59#ibcon#about to write, iclass 37, count 2 2006.257.21:31:25.59#ibcon#wrote, iclass 37, count 2 2006.257.21:31:25.59#ibcon#about to read 3, iclass 37, count 2 2006.257.21:31:25.61#ibcon#read 3, iclass 37, count 2 2006.257.21:31:25.61#ibcon#about to read 4, iclass 37, count 2 2006.257.21:31:25.61#ibcon#read 4, iclass 37, count 2 2006.257.21:31:25.61#ibcon#about to read 5, iclass 37, count 2 2006.257.21:31:25.61#ibcon#read 5, iclass 37, count 2 2006.257.21:31:25.61#ibcon#about to read 6, iclass 37, count 2 2006.257.21:31:25.61#ibcon#read 6, iclass 37, count 2 2006.257.21:31:25.61#ibcon#end of sib2, iclass 37, count 2 2006.257.21:31:25.61#ibcon#*mode == 0, iclass 37, count 2 2006.257.21:31:25.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.21:31:25.61#ibcon#[25=AT04-07\r\n] 2006.257.21:31:25.61#ibcon#*before write, iclass 37, count 2 2006.257.21:31:25.61#ibcon#enter sib2, iclass 37, count 2 2006.257.21:31:25.61#ibcon#flushed, iclass 37, count 2 2006.257.21:31:25.61#ibcon#about to write, iclass 37, count 2 2006.257.21:31:25.61#ibcon#wrote, iclass 37, count 2 2006.257.21:31:25.61#ibcon#about to read 3, iclass 37, count 2 2006.257.21:31:25.64#ibcon#read 3, iclass 37, count 2 2006.257.21:31:25.64#ibcon#about to read 4, iclass 37, count 2 2006.257.21:31:25.64#ibcon#read 4, iclass 37, count 2 2006.257.21:31:25.64#ibcon#about to read 5, iclass 37, count 2 2006.257.21:31:25.64#ibcon#read 5, iclass 37, count 2 2006.257.21:31:25.64#ibcon#about to read 6, iclass 37, count 2 2006.257.21:31:25.64#ibcon#read 6, iclass 37, count 2 2006.257.21:31:25.64#ibcon#end of sib2, iclass 37, count 2 2006.257.21:31:25.64#ibcon#*after write, iclass 37, count 2 2006.257.21:31:25.64#ibcon#*before return 0, iclass 37, count 2 2006.257.21:31:25.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:25.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:25.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.21:31:25.64#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:25.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:25.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:25.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:25.76#ibcon#enter wrdev, iclass 37, count 0 2006.257.21:31:25.76#ibcon#first serial, iclass 37, count 0 2006.257.21:31:25.76#ibcon#enter sib2, iclass 37, count 0 2006.257.21:31:25.76#ibcon#flushed, iclass 37, count 0 2006.257.21:31:25.76#ibcon#about to write, iclass 37, count 0 2006.257.21:31:25.76#ibcon#wrote, iclass 37, count 0 2006.257.21:31:25.76#ibcon#about to read 3, iclass 37, count 0 2006.257.21:31:25.78#ibcon#read 3, iclass 37, count 0 2006.257.21:31:25.78#ibcon#about to read 4, iclass 37, count 0 2006.257.21:31:25.78#ibcon#read 4, iclass 37, count 0 2006.257.21:31:25.78#ibcon#about to read 5, iclass 37, count 0 2006.257.21:31:25.78#ibcon#read 5, iclass 37, count 0 2006.257.21:31:25.78#ibcon#about to read 6, iclass 37, count 0 2006.257.21:31:25.78#ibcon#read 6, iclass 37, count 0 2006.257.21:31:25.78#ibcon#end of sib2, iclass 37, count 0 2006.257.21:31:25.78#ibcon#*mode == 0, iclass 37, count 0 2006.257.21:31:25.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.21:31:25.78#ibcon#[25=USB\r\n] 2006.257.21:31:25.78#ibcon#*before write, iclass 37, count 0 2006.257.21:31:25.78#ibcon#enter sib2, iclass 37, count 0 2006.257.21:31:25.78#ibcon#flushed, iclass 37, count 0 2006.257.21:31:25.78#ibcon#about to write, iclass 37, count 0 2006.257.21:31:25.78#ibcon#wrote, iclass 37, count 0 2006.257.21:31:25.78#ibcon#about to read 3, iclass 37, count 0 2006.257.21:31:25.81#ibcon#read 3, iclass 37, count 0 2006.257.21:31:25.81#ibcon#about to read 4, iclass 37, count 0 2006.257.21:31:25.81#ibcon#read 4, iclass 37, count 0 2006.257.21:31:25.81#ibcon#about to read 5, iclass 37, count 0 2006.257.21:31:25.81#ibcon#read 5, iclass 37, count 0 2006.257.21:31:25.81#ibcon#about to read 6, iclass 37, count 0 2006.257.21:31:25.81#ibcon#read 6, iclass 37, count 0 2006.257.21:31:25.81#ibcon#end of sib2, iclass 37, count 0 2006.257.21:31:25.81#ibcon#*after write, iclass 37, count 0 2006.257.21:31:25.81#ibcon#*before return 0, iclass 37, count 0 2006.257.21:31:25.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:25.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:25.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.21:31:25.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.21:31:25.81$vck44/valo=5,734.99 2006.257.21:31:25.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.21:31:25.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.21:31:25.81#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:25.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:25.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:25.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:25.81#ibcon#enter wrdev, iclass 39, count 0 2006.257.21:31:25.81#ibcon#first serial, iclass 39, count 0 2006.257.21:31:25.81#ibcon#enter sib2, iclass 39, count 0 2006.257.21:31:25.81#ibcon#flushed, iclass 39, count 0 2006.257.21:31:25.81#ibcon#about to write, iclass 39, count 0 2006.257.21:31:25.81#ibcon#wrote, iclass 39, count 0 2006.257.21:31:25.81#ibcon#about to read 3, iclass 39, count 0 2006.257.21:31:25.83#ibcon#read 3, iclass 39, count 0 2006.257.21:31:25.83#ibcon#about to read 4, iclass 39, count 0 2006.257.21:31:25.83#ibcon#read 4, iclass 39, count 0 2006.257.21:31:25.83#ibcon#about to read 5, iclass 39, count 0 2006.257.21:31:25.83#ibcon#read 5, iclass 39, count 0 2006.257.21:31:25.83#ibcon#about to read 6, iclass 39, count 0 2006.257.21:31:25.83#ibcon#read 6, iclass 39, count 0 2006.257.21:31:25.83#ibcon#end of sib2, iclass 39, count 0 2006.257.21:31:25.83#ibcon#*mode == 0, iclass 39, count 0 2006.257.21:31:25.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.21:31:25.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.21:31:25.83#ibcon#*before write, iclass 39, count 0 2006.257.21:31:25.83#ibcon#enter sib2, iclass 39, count 0 2006.257.21:31:25.83#ibcon#flushed, iclass 39, count 0 2006.257.21:31:25.83#ibcon#about to write, iclass 39, count 0 2006.257.21:31:25.83#ibcon#wrote, iclass 39, count 0 2006.257.21:31:25.83#ibcon#about to read 3, iclass 39, count 0 2006.257.21:31:25.87#ibcon#read 3, iclass 39, count 0 2006.257.21:31:25.87#ibcon#about to read 4, iclass 39, count 0 2006.257.21:31:25.87#ibcon#read 4, iclass 39, count 0 2006.257.21:31:25.87#ibcon#about to read 5, iclass 39, count 0 2006.257.21:31:25.87#ibcon#read 5, iclass 39, count 0 2006.257.21:31:25.87#ibcon#about to read 6, iclass 39, count 0 2006.257.21:31:25.87#ibcon#read 6, iclass 39, count 0 2006.257.21:31:25.87#ibcon#end of sib2, iclass 39, count 0 2006.257.21:31:25.87#ibcon#*after write, iclass 39, count 0 2006.257.21:31:25.87#ibcon#*before return 0, iclass 39, count 0 2006.257.21:31:25.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:25.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:25.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.21:31:25.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.21:31:25.87$vck44/va=5,4 2006.257.21:31:25.87#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.21:31:25.87#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.21:31:25.87#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:25.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:25.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:25.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:25.93#ibcon#enter wrdev, iclass 3, count 2 2006.257.21:31:25.93#ibcon#first serial, iclass 3, count 2 2006.257.21:31:25.93#ibcon#enter sib2, iclass 3, count 2 2006.257.21:31:25.93#ibcon#flushed, iclass 3, count 2 2006.257.21:31:25.93#ibcon#about to write, iclass 3, count 2 2006.257.21:31:25.93#ibcon#wrote, iclass 3, count 2 2006.257.21:31:25.93#ibcon#about to read 3, iclass 3, count 2 2006.257.21:31:25.95#ibcon#read 3, iclass 3, count 2 2006.257.21:31:25.95#ibcon#about to read 4, iclass 3, count 2 2006.257.21:31:25.95#ibcon#read 4, iclass 3, count 2 2006.257.21:31:25.95#ibcon#about to read 5, iclass 3, count 2 2006.257.21:31:25.95#ibcon#read 5, iclass 3, count 2 2006.257.21:31:25.95#ibcon#about to read 6, iclass 3, count 2 2006.257.21:31:25.95#ibcon#read 6, iclass 3, count 2 2006.257.21:31:25.95#ibcon#end of sib2, iclass 3, count 2 2006.257.21:31:25.95#ibcon#*mode == 0, iclass 3, count 2 2006.257.21:31:25.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.21:31:25.95#ibcon#[25=AT05-04\r\n] 2006.257.21:31:25.95#ibcon#*before write, iclass 3, count 2 2006.257.21:31:25.95#ibcon#enter sib2, iclass 3, count 2 2006.257.21:31:25.95#ibcon#flushed, iclass 3, count 2 2006.257.21:31:25.95#ibcon#about to write, iclass 3, count 2 2006.257.21:31:25.95#ibcon#wrote, iclass 3, count 2 2006.257.21:31:25.95#ibcon#about to read 3, iclass 3, count 2 2006.257.21:31:25.98#ibcon#read 3, iclass 3, count 2 2006.257.21:31:25.98#ibcon#about to read 4, iclass 3, count 2 2006.257.21:31:25.98#ibcon#read 4, iclass 3, count 2 2006.257.21:31:25.98#ibcon#about to read 5, iclass 3, count 2 2006.257.21:31:25.98#ibcon#read 5, iclass 3, count 2 2006.257.21:31:25.98#ibcon#about to read 6, iclass 3, count 2 2006.257.21:31:25.98#ibcon#read 6, iclass 3, count 2 2006.257.21:31:25.98#ibcon#end of sib2, iclass 3, count 2 2006.257.21:31:25.98#ibcon#*after write, iclass 3, count 2 2006.257.21:31:25.98#ibcon#*before return 0, iclass 3, count 2 2006.257.21:31:25.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:25.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:25.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.21:31:25.98#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:25.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:26.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:26.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:26.10#ibcon#enter wrdev, iclass 3, count 0 2006.257.21:31:26.10#ibcon#first serial, iclass 3, count 0 2006.257.21:31:26.10#ibcon#enter sib2, iclass 3, count 0 2006.257.21:31:26.10#ibcon#flushed, iclass 3, count 0 2006.257.21:31:26.10#ibcon#about to write, iclass 3, count 0 2006.257.21:31:26.10#ibcon#wrote, iclass 3, count 0 2006.257.21:31:26.10#ibcon#about to read 3, iclass 3, count 0 2006.257.21:31:26.12#ibcon#read 3, iclass 3, count 0 2006.257.21:31:26.12#ibcon#about to read 4, iclass 3, count 0 2006.257.21:31:26.12#ibcon#read 4, iclass 3, count 0 2006.257.21:31:26.12#ibcon#about to read 5, iclass 3, count 0 2006.257.21:31:26.12#ibcon#read 5, iclass 3, count 0 2006.257.21:31:26.12#ibcon#about to read 6, iclass 3, count 0 2006.257.21:31:26.12#ibcon#read 6, iclass 3, count 0 2006.257.21:31:26.12#ibcon#end of sib2, iclass 3, count 0 2006.257.21:31:26.12#ibcon#*mode == 0, iclass 3, count 0 2006.257.21:31:26.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.21:31:26.12#ibcon#[25=USB\r\n] 2006.257.21:31:26.12#ibcon#*before write, iclass 3, count 0 2006.257.21:31:26.12#ibcon#enter sib2, iclass 3, count 0 2006.257.21:31:26.12#ibcon#flushed, iclass 3, count 0 2006.257.21:31:26.12#ibcon#about to write, iclass 3, count 0 2006.257.21:31:26.12#ibcon#wrote, iclass 3, count 0 2006.257.21:31:26.12#ibcon#about to read 3, iclass 3, count 0 2006.257.21:31:26.15#ibcon#read 3, iclass 3, count 0 2006.257.21:31:26.15#ibcon#about to read 4, iclass 3, count 0 2006.257.21:31:26.15#ibcon#read 4, iclass 3, count 0 2006.257.21:31:26.15#ibcon#about to read 5, iclass 3, count 0 2006.257.21:31:26.15#ibcon#read 5, iclass 3, count 0 2006.257.21:31:26.15#ibcon#about to read 6, iclass 3, count 0 2006.257.21:31:26.15#ibcon#read 6, iclass 3, count 0 2006.257.21:31:26.15#ibcon#end of sib2, iclass 3, count 0 2006.257.21:31:26.15#ibcon#*after write, iclass 3, count 0 2006.257.21:31:26.15#ibcon#*before return 0, iclass 3, count 0 2006.257.21:31:26.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:26.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:26.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.21:31:26.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.21:31:26.15$vck44/valo=6,814.99 2006.257.21:31:26.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.21:31:26.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.21:31:26.15#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:26.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:26.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:26.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:26.15#ibcon#enter wrdev, iclass 5, count 0 2006.257.21:31:26.15#ibcon#first serial, iclass 5, count 0 2006.257.21:31:26.15#ibcon#enter sib2, iclass 5, count 0 2006.257.21:31:26.15#ibcon#flushed, iclass 5, count 0 2006.257.21:31:26.15#ibcon#about to write, iclass 5, count 0 2006.257.21:31:26.15#ibcon#wrote, iclass 5, count 0 2006.257.21:31:26.15#ibcon#about to read 3, iclass 5, count 0 2006.257.21:31:26.17#ibcon#read 3, iclass 5, count 0 2006.257.21:31:26.17#ibcon#about to read 4, iclass 5, count 0 2006.257.21:31:26.17#ibcon#read 4, iclass 5, count 0 2006.257.21:31:26.17#ibcon#about to read 5, iclass 5, count 0 2006.257.21:31:26.17#ibcon#read 5, iclass 5, count 0 2006.257.21:31:26.17#ibcon#about to read 6, iclass 5, count 0 2006.257.21:31:26.17#ibcon#read 6, iclass 5, count 0 2006.257.21:31:26.17#ibcon#end of sib2, iclass 5, count 0 2006.257.21:31:26.17#ibcon#*mode == 0, iclass 5, count 0 2006.257.21:31:26.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.21:31:26.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.21:31:26.17#ibcon#*before write, iclass 5, count 0 2006.257.21:31:26.17#ibcon#enter sib2, iclass 5, count 0 2006.257.21:31:26.17#ibcon#flushed, iclass 5, count 0 2006.257.21:31:26.17#ibcon#about to write, iclass 5, count 0 2006.257.21:31:26.17#ibcon#wrote, iclass 5, count 0 2006.257.21:31:26.17#ibcon#about to read 3, iclass 5, count 0 2006.257.21:31:26.21#ibcon#read 3, iclass 5, count 0 2006.257.21:31:26.21#ibcon#about to read 4, iclass 5, count 0 2006.257.21:31:26.21#ibcon#read 4, iclass 5, count 0 2006.257.21:31:26.21#ibcon#about to read 5, iclass 5, count 0 2006.257.21:31:26.21#ibcon#read 5, iclass 5, count 0 2006.257.21:31:26.21#ibcon#about to read 6, iclass 5, count 0 2006.257.21:31:26.21#ibcon#read 6, iclass 5, count 0 2006.257.21:31:26.21#ibcon#end of sib2, iclass 5, count 0 2006.257.21:31:26.21#ibcon#*after write, iclass 5, count 0 2006.257.21:31:26.21#ibcon#*before return 0, iclass 5, count 0 2006.257.21:31:26.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:26.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:26.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.21:31:26.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.21:31:26.21$vck44/va=6,4 2006.257.21:31:26.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.21:31:26.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.21:31:26.21#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:26.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:26.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:26.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:26.27#ibcon#enter wrdev, iclass 7, count 2 2006.257.21:31:26.27#ibcon#first serial, iclass 7, count 2 2006.257.21:31:26.27#ibcon#enter sib2, iclass 7, count 2 2006.257.21:31:26.27#ibcon#flushed, iclass 7, count 2 2006.257.21:31:26.27#ibcon#about to write, iclass 7, count 2 2006.257.21:31:26.27#ibcon#wrote, iclass 7, count 2 2006.257.21:31:26.27#ibcon#about to read 3, iclass 7, count 2 2006.257.21:31:26.29#ibcon#read 3, iclass 7, count 2 2006.257.21:31:26.29#ibcon#about to read 4, iclass 7, count 2 2006.257.21:31:26.29#ibcon#read 4, iclass 7, count 2 2006.257.21:31:26.29#ibcon#about to read 5, iclass 7, count 2 2006.257.21:31:26.29#ibcon#read 5, iclass 7, count 2 2006.257.21:31:26.29#ibcon#about to read 6, iclass 7, count 2 2006.257.21:31:26.29#ibcon#read 6, iclass 7, count 2 2006.257.21:31:26.29#ibcon#end of sib2, iclass 7, count 2 2006.257.21:31:26.29#ibcon#*mode == 0, iclass 7, count 2 2006.257.21:31:26.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.21:31:26.29#ibcon#[25=AT06-04\r\n] 2006.257.21:31:26.29#ibcon#*before write, iclass 7, count 2 2006.257.21:31:26.29#ibcon#enter sib2, iclass 7, count 2 2006.257.21:31:26.29#ibcon#flushed, iclass 7, count 2 2006.257.21:31:26.29#ibcon#about to write, iclass 7, count 2 2006.257.21:31:26.29#ibcon#wrote, iclass 7, count 2 2006.257.21:31:26.29#ibcon#about to read 3, iclass 7, count 2 2006.257.21:31:26.32#ibcon#read 3, iclass 7, count 2 2006.257.21:31:26.32#ibcon#about to read 4, iclass 7, count 2 2006.257.21:31:26.32#ibcon#read 4, iclass 7, count 2 2006.257.21:31:26.32#ibcon#about to read 5, iclass 7, count 2 2006.257.21:31:26.32#ibcon#read 5, iclass 7, count 2 2006.257.21:31:26.32#ibcon#about to read 6, iclass 7, count 2 2006.257.21:31:26.32#ibcon#read 6, iclass 7, count 2 2006.257.21:31:26.32#ibcon#end of sib2, iclass 7, count 2 2006.257.21:31:26.32#ibcon#*after write, iclass 7, count 2 2006.257.21:31:26.32#ibcon#*before return 0, iclass 7, count 2 2006.257.21:31:26.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:26.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:26.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.21:31:26.32#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:26.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:26.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:26.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:26.44#ibcon#enter wrdev, iclass 7, count 0 2006.257.21:31:26.44#ibcon#first serial, iclass 7, count 0 2006.257.21:31:26.44#ibcon#enter sib2, iclass 7, count 0 2006.257.21:31:26.44#ibcon#flushed, iclass 7, count 0 2006.257.21:31:26.44#ibcon#about to write, iclass 7, count 0 2006.257.21:31:26.44#ibcon#wrote, iclass 7, count 0 2006.257.21:31:26.44#ibcon#about to read 3, iclass 7, count 0 2006.257.21:31:26.46#ibcon#read 3, iclass 7, count 0 2006.257.21:31:26.46#ibcon#about to read 4, iclass 7, count 0 2006.257.21:31:26.46#ibcon#read 4, iclass 7, count 0 2006.257.21:31:26.46#ibcon#about to read 5, iclass 7, count 0 2006.257.21:31:26.46#ibcon#read 5, iclass 7, count 0 2006.257.21:31:26.46#ibcon#about to read 6, iclass 7, count 0 2006.257.21:31:26.46#ibcon#read 6, iclass 7, count 0 2006.257.21:31:26.46#ibcon#end of sib2, iclass 7, count 0 2006.257.21:31:26.46#ibcon#*mode == 0, iclass 7, count 0 2006.257.21:31:26.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.21:31:26.46#ibcon#[25=USB\r\n] 2006.257.21:31:26.46#ibcon#*before write, iclass 7, count 0 2006.257.21:31:26.46#ibcon#enter sib2, iclass 7, count 0 2006.257.21:31:26.46#ibcon#flushed, iclass 7, count 0 2006.257.21:31:26.46#ibcon#about to write, iclass 7, count 0 2006.257.21:31:26.46#ibcon#wrote, iclass 7, count 0 2006.257.21:31:26.46#ibcon#about to read 3, iclass 7, count 0 2006.257.21:31:26.49#ibcon#read 3, iclass 7, count 0 2006.257.21:31:26.49#ibcon#about to read 4, iclass 7, count 0 2006.257.21:31:26.49#ibcon#read 4, iclass 7, count 0 2006.257.21:31:26.49#ibcon#about to read 5, iclass 7, count 0 2006.257.21:31:26.49#ibcon#read 5, iclass 7, count 0 2006.257.21:31:26.49#ibcon#about to read 6, iclass 7, count 0 2006.257.21:31:26.49#ibcon#read 6, iclass 7, count 0 2006.257.21:31:26.49#ibcon#end of sib2, iclass 7, count 0 2006.257.21:31:26.49#ibcon#*after write, iclass 7, count 0 2006.257.21:31:26.49#ibcon#*before return 0, iclass 7, count 0 2006.257.21:31:26.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:26.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:26.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.21:31:26.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.21:31:26.49$vck44/valo=7,864.99 2006.257.21:31:26.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.21:31:26.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.21:31:26.49#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:26.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:31:26.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:31:26.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:31:26.49#ibcon#enter wrdev, iclass 11, count 0 2006.257.21:31:26.49#ibcon#first serial, iclass 11, count 0 2006.257.21:31:26.49#ibcon#enter sib2, iclass 11, count 0 2006.257.21:31:26.49#ibcon#flushed, iclass 11, count 0 2006.257.21:31:26.49#ibcon#about to write, iclass 11, count 0 2006.257.21:31:26.49#ibcon#wrote, iclass 11, count 0 2006.257.21:31:26.49#ibcon#about to read 3, iclass 11, count 0 2006.257.21:31:26.51#ibcon#read 3, iclass 11, count 0 2006.257.21:31:26.51#ibcon#about to read 4, iclass 11, count 0 2006.257.21:31:26.51#ibcon#read 4, iclass 11, count 0 2006.257.21:31:26.51#ibcon#about to read 5, iclass 11, count 0 2006.257.21:31:26.51#ibcon#read 5, iclass 11, count 0 2006.257.21:31:26.51#ibcon#about to read 6, iclass 11, count 0 2006.257.21:31:26.51#ibcon#read 6, iclass 11, count 0 2006.257.21:31:26.51#ibcon#end of sib2, iclass 11, count 0 2006.257.21:31:26.51#ibcon#*mode == 0, iclass 11, count 0 2006.257.21:31:26.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.21:31:26.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.21:31:26.51#ibcon#*before write, iclass 11, count 0 2006.257.21:31:26.51#ibcon#enter sib2, iclass 11, count 0 2006.257.21:31:26.51#ibcon#flushed, iclass 11, count 0 2006.257.21:31:26.51#ibcon#about to write, iclass 11, count 0 2006.257.21:31:26.51#ibcon#wrote, iclass 11, count 0 2006.257.21:31:26.51#ibcon#about to read 3, iclass 11, count 0 2006.257.21:31:26.55#ibcon#read 3, iclass 11, count 0 2006.257.21:31:26.55#ibcon#about to read 4, iclass 11, count 0 2006.257.21:31:26.55#ibcon#read 4, iclass 11, count 0 2006.257.21:31:26.55#ibcon#about to read 5, iclass 11, count 0 2006.257.21:31:26.55#ibcon#read 5, iclass 11, count 0 2006.257.21:31:26.55#ibcon#about to read 6, iclass 11, count 0 2006.257.21:31:26.55#ibcon#read 6, iclass 11, count 0 2006.257.21:31:26.55#ibcon#end of sib2, iclass 11, count 0 2006.257.21:31:26.55#ibcon#*after write, iclass 11, count 0 2006.257.21:31:26.55#ibcon#*before return 0, iclass 11, count 0 2006.257.21:31:26.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:31:26.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:31:26.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.21:31:26.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.21:31:26.55$vck44/va=7,4 2006.257.21:31:26.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.21:31:26.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.21:31:26.55#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:26.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:31:26.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:31:26.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:31:26.61#ibcon#enter wrdev, iclass 13, count 2 2006.257.21:31:26.61#ibcon#first serial, iclass 13, count 2 2006.257.21:31:26.61#ibcon#enter sib2, iclass 13, count 2 2006.257.21:31:26.61#ibcon#flushed, iclass 13, count 2 2006.257.21:31:26.61#ibcon#about to write, iclass 13, count 2 2006.257.21:31:26.61#ibcon#wrote, iclass 13, count 2 2006.257.21:31:26.61#ibcon#about to read 3, iclass 13, count 2 2006.257.21:31:26.63#ibcon#read 3, iclass 13, count 2 2006.257.21:31:26.63#ibcon#about to read 4, iclass 13, count 2 2006.257.21:31:26.63#ibcon#read 4, iclass 13, count 2 2006.257.21:31:26.63#ibcon#about to read 5, iclass 13, count 2 2006.257.21:31:26.63#ibcon#read 5, iclass 13, count 2 2006.257.21:31:26.63#ibcon#about to read 6, iclass 13, count 2 2006.257.21:31:26.63#ibcon#read 6, iclass 13, count 2 2006.257.21:31:26.63#ibcon#end of sib2, iclass 13, count 2 2006.257.21:31:26.63#ibcon#*mode == 0, iclass 13, count 2 2006.257.21:31:26.63#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.21:31:26.63#ibcon#[25=AT07-04\r\n] 2006.257.21:31:26.63#ibcon#*before write, iclass 13, count 2 2006.257.21:31:26.63#ibcon#enter sib2, iclass 13, count 2 2006.257.21:31:26.63#ibcon#flushed, iclass 13, count 2 2006.257.21:31:26.63#ibcon#about to write, iclass 13, count 2 2006.257.21:31:26.63#ibcon#wrote, iclass 13, count 2 2006.257.21:31:26.63#ibcon#about to read 3, iclass 13, count 2 2006.257.21:31:26.66#ibcon#read 3, iclass 13, count 2 2006.257.21:31:26.66#ibcon#about to read 4, iclass 13, count 2 2006.257.21:31:26.66#ibcon#read 4, iclass 13, count 2 2006.257.21:31:26.66#ibcon#about to read 5, iclass 13, count 2 2006.257.21:31:26.66#ibcon#read 5, iclass 13, count 2 2006.257.21:31:26.66#ibcon#about to read 6, iclass 13, count 2 2006.257.21:31:26.66#ibcon#read 6, iclass 13, count 2 2006.257.21:31:26.66#ibcon#end of sib2, iclass 13, count 2 2006.257.21:31:26.66#ibcon#*after write, iclass 13, count 2 2006.257.21:31:26.66#ibcon#*before return 0, iclass 13, count 2 2006.257.21:31:26.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:31:26.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:31:26.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.21:31:26.66#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:26.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:31:26.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:31:26.78#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:31:26.78#ibcon#enter wrdev, iclass 13, count 0 2006.257.21:31:26.78#ibcon#first serial, iclass 13, count 0 2006.257.21:31:26.78#ibcon#enter sib2, iclass 13, count 0 2006.257.21:31:26.78#ibcon#flushed, iclass 13, count 0 2006.257.21:31:26.78#ibcon#about to write, iclass 13, count 0 2006.257.21:31:26.78#ibcon#wrote, iclass 13, count 0 2006.257.21:31:26.78#ibcon#about to read 3, iclass 13, count 0 2006.257.21:31:26.80#ibcon#read 3, iclass 13, count 0 2006.257.21:31:26.80#ibcon#about to read 4, iclass 13, count 0 2006.257.21:31:26.80#ibcon#read 4, iclass 13, count 0 2006.257.21:31:26.80#ibcon#about to read 5, iclass 13, count 0 2006.257.21:31:26.80#ibcon#read 5, iclass 13, count 0 2006.257.21:31:26.80#ibcon#about to read 6, iclass 13, count 0 2006.257.21:31:26.80#ibcon#read 6, iclass 13, count 0 2006.257.21:31:26.80#ibcon#end of sib2, iclass 13, count 0 2006.257.21:31:26.80#ibcon#*mode == 0, iclass 13, count 0 2006.257.21:31:26.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.21:31:26.80#ibcon#[25=USB\r\n] 2006.257.21:31:26.80#ibcon#*before write, iclass 13, count 0 2006.257.21:31:26.80#ibcon#enter sib2, iclass 13, count 0 2006.257.21:31:26.80#ibcon#flushed, iclass 13, count 0 2006.257.21:31:26.80#ibcon#about to write, iclass 13, count 0 2006.257.21:31:26.80#ibcon#wrote, iclass 13, count 0 2006.257.21:31:26.80#ibcon#about to read 3, iclass 13, count 0 2006.257.21:31:26.83#ibcon#read 3, iclass 13, count 0 2006.257.21:31:26.83#ibcon#about to read 4, iclass 13, count 0 2006.257.21:31:26.83#ibcon#read 4, iclass 13, count 0 2006.257.21:31:26.83#ibcon#about to read 5, iclass 13, count 0 2006.257.21:31:26.83#ibcon#read 5, iclass 13, count 0 2006.257.21:31:26.83#ibcon#about to read 6, iclass 13, count 0 2006.257.21:31:26.83#ibcon#read 6, iclass 13, count 0 2006.257.21:31:26.83#ibcon#end of sib2, iclass 13, count 0 2006.257.21:31:26.83#ibcon#*after write, iclass 13, count 0 2006.257.21:31:26.83#ibcon#*before return 0, iclass 13, count 0 2006.257.21:31:26.83#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:31:26.83#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:31:26.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.21:31:26.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.21:31:26.83$vck44/valo=8,884.99 2006.257.21:31:26.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.21:31:26.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.21:31:26.83#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:26.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:26.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:26.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:26.83#ibcon#enter wrdev, iclass 15, count 0 2006.257.21:31:26.83#ibcon#first serial, iclass 15, count 0 2006.257.21:31:26.83#ibcon#enter sib2, iclass 15, count 0 2006.257.21:31:26.83#ibcon#flushed, iclass 15, count 0 2006.257.21:31:26.83#ibcon#about to write, iclass 15, count 0 2006.257.21:31:26.83#ibcon#wrote, iclass 15, count 0 2006.257.21:31:26.83#ibcon#about to read 3, iclass 15, count 0 2006.257.21:31:26.85#ibcon#read 3, iclass 15, count 0 2006.257.21:31:26.85#ibcon#about to read 4, iclass 15, count 0 2006.257.21:31:26.85#ibcon#read 4, iclass 15, count 0 2006.257.21:31:26.85#ibcon#about to read 5, iclass 15, count 0 2006.257.21:31:26.85#ibcon#read 5, iclass 15, count 0 2006.257.21:31:26.85#ibcon#about to read 6, iclass 15, count 0 2006.257.21:31:26.85#ibcon#read 6, iclass 15, count 0 2006.257.21:31:26.85#ibcon#end of sib2, iclass 15, count 0 2006.257.21:31:26.85#ibcon#*mode == 0, iclass 15, count 0 2006.257.21:31:26.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.21:31:26.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.21:31:26.85#ibcon#*before write, iclass 15, count 0 2006.257.21:31:26.85#ibcon#enter sib2, iclass 15, count 0 2006.257.21:31:26.85#ibcon#flushed, iclass 15, count 0 2006.257.21:31:26.85#ibcon#about to write, iclass 15, count 0 2006.257.21:31:26.85#ibcon#wrote, iclass 15, count 0 2006.257.21:31:26.85#ibcon#about to read 3, iclass 15, count 0 2006.257.21:31:26.89#ibcon#read 3, iclass 15, count 0 2006.257.21:31:26.89#ibcon#about to read 4, iclass 15, count 0 2006.257.21:31:26.89#ibcon#read 4, iclass 15, count 0 2006.257.21:31:26.89#ibcon#about to read 5, iclass 15, count 0 2006.257.21:31:26.89#ibcon#read 5, iclass 15, count 0 2006.257.21:31:26.89#ibcon#about to read 6, iclass 15, count 0 2006.257.21:31:26.89#ibcon#read 6, iclass 15, count 0 2006.257.21:31:26.89#ibcon#end of sib2, iclass 15, count 0 2006.257.21:31:26.89#ibcon#*after write, iclass 15, count 0 2006.257.21:31:26.89#ibcon#*before return 0, iclass 15, count 0 2006.257.21:31:26.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:26.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:26.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.21:31:26.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.21:31:26.89$vck44/va=8,4 2006.257.21:31:26.89#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.21:31:26.89#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.21:31:26.89#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:26.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:26.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:26.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:26.95#ibcon#enter wrdev, iclass 17, count 2 2006.257.21:31:26.95#ibcon#first serial, iclass 17, count 2 2006.257.21:31:26.95#ibcon#enter sib2, iclass 17, count 2 2006.257.21:31:26.95#ibcon#flushed, iclass 17, count 2 2006.257.21:31:26.95#ibcon#about to write, iclass 17, count 2 2006.257.21:31:26.95#ibcon#wrote, iclass 17, count 2 2006.257.21:31:26.95#ibcon#about to read 3, iclass 17, count 2 2006.257.21:31:26.97#ibcon#read 3, iclass 17, count 2 2006.257.21:31:26.97#ibcon#about to read 4, iclass 17, count 2 2006.257.21:31:26.97#ibcon#read 4, iclass 17, count 2 2006.257.21:31:26.97#ibcon#about to read 5, iclass 17, count 2 2006.257.21:31:26.97#ibcon#read 5, iclass 17, count 2 2006.257.21:31:26.97#ibcon#about to read 6, iclass 17, count 2 2006.257.21:31:26.97#ibcon#read 6, iclass 17, count 2 2006.257.21:31:26.97#ibcon#end of sib2, iclass 17, count 2 2006.257.21:31:26.97#ibcon#*mode == 0, iclass 17, count 2 2006.257.21:31:26.97#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.21:31:26.97#ibcon#[25=AT08-04\r\n] 2006.257.21:31:26.97#ibcon#*before write, iclass 17, count 2 2006.257.21:31:26.97#ibcon#enter sib2, iclass 17, count 2 2006.257.21:31:26.97#ibcon#flushed, iclass 17, count 2 2006.257.21:31:26.97#ibcon#about to write, iclass 17, count 2 2006.257.21:31:26.97#ibcon#wrote, iclass 17, count 2 2006.257.21:31:26.97#ibcon#about to read 3, iclass 17, count 2 2006.257.21:31:27.00#ibcon#read 3, iclass 17, count 2 2006.257.21:31:27.00#ibcon#about to read 4, iclass 17, count 2 2006.257.21:31:27.00#ibcon#read 4, iclass 17, count 2 2006.257.21:31:27.00#ibcon#about to read 5, iclass 17, count 2 2006.257.21:31:27.00#ibcon#read 5, iclass 17, count 2 2006.257.21:31:27.00#ibcon#about to read 6, iclass 17, count 2 2006.257.21:31:27.00#ibcon#read 6, iclass 17, count 2 2006.257.21:31:27.00#ibcon#end of sib2, iclass 17, count 2 2006.257.21:31:27.00#ibcon#*after write, iclass 17, count 2 2006.257.21:31:27.00#ibcon#*before return 0, iclass 17, count 2 2006.257.21:31:27.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:27.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:27.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.21:31:27.00#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:27.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:27.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:27.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:27.12#ibcon#enter wrdev, iclass 17, count 0 2006.257.21:31:27.12#ibcon#first serial, iclass 17, count 0 2006.257.21:31:27.12#ibcon#enter sib2, iclass 17, count 0 2006.257.21:31:27.12#ibcon#flushed, iclass 17, count 0 2006.257.21:31:27.12#ibcon#about to write, iclass 17, count 0 2006.257.21:31:27.12#ibcon#wrote, iclass 17, count 0 2006.257.21:31:27.12#ibcon#about to read 3, iclass 17, count 0 2006.257.21:31:27.14#ibcon#read 3, iclass 17, count 0 2006.257.21:31:27.14#ibcon#about to read 4, iclass 17, count 0 2006.257.21:31:27.14#ibcon#read 4, iclass 17, count 0 2006.257.21:31:27.14#ibcon#about to read 5, iclass 17, count 0 2006.257.21:31:27.14#ibcon#read 5, iclass 17, count 0 2006.257.21:31:27.14#ibcon#about to read 6, iclass 17, count 0 2006.257.21:31:27.14#ibcon#read 6, iclass 17, count 0 2006.257.21:31:27.14#ibcon#end of sib2, iclass 17, count 0 2006.257.21:31:27.14#ibcon#*mode == 0, iclass 17, count 0 2006.257.21:31:27.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.21:31:27.14#ibcon#[25=USB\r\n] 2006.257.21:31:27.14#ibcon#*before write, iclass 17, count 0 2006.257.21:31:27.14#ibcon#enter sib2, iclass 17, count 0 2006.257.21:31:27.14#ibcon#flushed, iclass 17, count 0 2006.257.21:31:27.14#ibcon#about to write, iclass 17, count 0 2006.257.21:31:27.14#ibcon#wrote, iclass 17, count 0 2006.257.21:31:27.14#ibcon#about to read 3, iclass 17, count 0 2006.257.21:31:27.17#ibcon#read 3, iclass 17, count 0 2006.257.21:31:27.17#ibcon#about to read 4, iclass 17, count 0 2006.257.21:31:27.17#ibcon#read 4, iclass 17, count 0 2006.257.21:31:27.17#ibcon#about to read 5, iclass 17, count 0 2006.257.21:31:27.17#ibcon#read 5, iclass 17, count 0 2006.257.21:31:27.17#ibcon#about to read 6, iclass 17, count 0 2006.257.21:31:27.17#ibcon#read 6, iclass 17, count 0 2006.257.21:31:27.17#ibcon#end of sib2, iclass 17, count 0 2006.257.21:31:27.17#ibcon#*after write, iclass 17, count 0 2006.257.21:31:27.17#ibcon#*before return 0, iclass 17, count 0 2006.257.21:31:27.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:27.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:27.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.21:31:27.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.21:31:27.17$vck44/vblo=1,629.99 2006.257.21:31:27.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.21:31:27.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.21:31:27.17#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:27.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:27.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:27.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:27.17#ibcon#enter wrdev, iclass 19, count 0 2006.257.21:31:27.17#ibcon#first serial, iclass 19, count 0 2006.257.21:31:27.17#ibcon#enter sib2, iclass 19, count 0 2006.257.21:31:27.17#ibcon#flushed, iclass 19, count 0 2006.257.21:31:27.17#ibcon#about to write, iclass 19, count 0 2006.257.21:31:27.17#ibcon#wrote, iclass 19, count 0 2006.257.21:31:27.17#ibcon#about to read 3, iclass 19, count 0 2006.257.21:31:27.19#ibcon#read 3, iclass 19, count 0 2006.257.21:31:27.19#ibcon#about to read 4, iclass 19, count 0 2006.257.21:31:27.19#ibcon#read 4, iclass 19, count 0 2006.257.21:31:27.19#ibcon#about to read 5, iclass 19, count 0 2006.257.21:31:27.19#ibcon#read 5, iclass 19, count 0 2006.257.21:31:27.19#ibcon#about to read 6, iclass 19, count 0 2006.257.21:31:27.19#ibcon#read 6, iclass 19, count 0 2006.257.21:31:27.19#ibcon#end of sib2, iclass 19, count 0 2006.257.21:31:27.19#ibcon#*mode == 0, iclass 19, count 0 2006.257.21:31:27.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.21:31:27.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.21:31:27.19#ibcon#*before write, iclass 19, count 0 2006.257.21:31:27.19#ibcon#enter sib2, iclass 19, count 0 2006.257.21:31:27.19#ibcon#flushed, iclass 19, count 0 2006.257.21:31:27.19#ibcon#about to write, iclass 19, count 0 2006.257.21:31:27.19#ibcon#wrote, iclass 19, count 0 2006.257.21:31:27.19#ibcon#about to read 3, iclass 19, count 0 2006.257.21:31:27.23#ibcon#read 3, iclass 19, count 0 2006.257.21:31:27.23#ibcon#about to read 4, iclass 19, count 0 2006.257.21:31:27.23#ibcon#read 4, iclass 19, count 0 2006.257.21:31:27.23#ibcon#about to read 5, iclass 19, count 0 2006.257.21:31:27.23#ibcon#read 5, iclass 19, count 0 2006.257.21:31:27.23#ibcon#about to read 6, iclass 19, count 0 2006.257.21:31:27.23#ibcon#read 6, iclass 19, count 0 2006.257.21:31:27.23#ibcon#end of sib2, iclass 19, count 0 2006.257.21:31:27.23#ibcon#*after write, iclass 19, count 0 2006.257.21:31:27.23#ibcon#*before return 0, iclass 19, count 0 2006.257.21:31:27.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:27.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:27.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.21:31:27.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.21:31:27.23$vck44/vb=1,4 2006.257.21:31:27.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.21:31:27.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.21:31:27.23#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:27.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:31:27.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:31:27.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:31:27.23#ibcon#enter wrdev, iclass 21, count 2 2006.257.21:31:27.23#ibcon#first serial, iclass 21, count 2 2006.257.21:31:27.23#ibcon#enter sib2, iclass 21, count 2 2006.257.21:31:27.23#ibcon#flushed, iclass 21, count 2 2006.257.21:31:27.23#ibcon#about to write, iclass 21, count 2 2006.257.21:31:27.23#ibcon#wrote, iclass 21, count 2 2006.257.21:31:27.23#ibcon#about to read 3, iclass 21, count 2 2006.257.21:31:27.25#ibcon#read 3, iclass 21, count 2 2006.257.21:31:27.25#ibcon#about to read 4, iclass 21, count 2 2006.257.21:31:27.25#ibcon#read 4, iclass 21, count 2 2006.257.21:31:27.25#ibcon#about to read 5, iclass 21, count 2 2006.257.21:31:27.25#ibcon#read 5, iclass 21, count 2 2006.257.21:31:27.25#ibcon#about to read 6, iclass 21, count 2 2006.257.21:31:27.25#ibcon#read 6, iclass 21, count 2 2006.257.21:31:27.25#ibcon#end of sib2, iclass 21, count 2 2006.257.21:31:27.25#ibcon#*mode == 0, iclass 21, count 2 2006.257.21:31:27.25#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.21:31:27.25#ibcon#[27=AT01-04\r\n] 2006.257.21:31:27.25#ibcon#*before write, iclass 21, count 2 2006.257.21:31:27.25#ibcon#enter sib2, iclass 21, count 2 2006.257.21:31:27.25#ibcon#flushed, iclass 21, count 2 2006.257.21:31:27.25#ibcon#about to write, iclass 21, count 2 2006.257.21:31:27.25#ibcon#wrote, iclass 21, count 2 2006.257.21:31:27.25#ibcon#about to read 3, iclass 21, count 2 2006.257.21:31:27.28#ibcon#read 3, iclass 21, count 2 2006.257.21:31:27.28#ibcon#about to read 4, iclass 21, count 2 2006.257.21:31:27.28#ibcon#read 4, iclass 21, count 2 2006.257.21:31:27.28#ibcon#about to read 5, iclass 21, count 2 2006.257.21:31:27.28#ibcon#read 5, iclass 21, count 2 2006.257.21:31:27.28#ibcon#about to read 6, iclass 21, count 2 2006.257.21:31:27.28#ibcon#read 6, iclass 21, count 2 2006.257.21:31:27.28#ibcon#end of sib2, iclass 21, count 2 2006.257.21:31:27.28#ibcon#*after write, iclass 21, count 2 2006.257.21:31:27.28#ibcon#*before return 0, iclass 21, count 2 2006.257.21:31:27.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:31:27.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:31:27.28#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.21:31:27.28#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:27.28#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:31:27.40#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:31:27.40#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:31:27.40#ibcon#enter wrdev, iclass 21, count 0 2006.257.21:31:27.40#ibcon#first serial, iclass 21, count 0 2006.257.21:31:27.40#ibcon#enter sib2, iclass 21, count 0 2006.257.21:31:27.40#ibcon#flushed, iclass 21, count 0 2006.257.21:31:27.40#ibcon#about to write, iclass 21, count 0 2006.257.21:31:27.40#ibcon#wrote, iclass 21, count 0 2006.257.21:31:27.40#ibcon#about to read 3, iclass 21, count 0 2006.257.21:31:27.42#ibcon#read 3, iclass 21, count 0 2006.257.21:31:27.42#ibcon#about to read 4, iclass 21, count 0 2006.257.21:31:27.42#ibcon#read 4, iclass 21, count 0 2006.257.21:31:27.42#ibcon#about to read 5, iclass 21, count 0 2006.257.21:31:27.42#ibcon#read 5, iclass 21, count 0 2006.257.21:31:27.42#ibcon#about to read 6, iclass 21, count 0 2006.257.21:31:27.42#ibcon#read 6, iclass 21, count 0 2006.257.21:31:27.42#ibcon#end of sib2, iclass 21, count 0 2006.257.21:31:27.42#ibcon#*mode == 0, iclass 21, count 0 2006.257.21:31:27.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.21:31:27.42#ibcon#[27=USB\r\n] 2006.257.21:31:27.42#ibcon#*before write, iclass 21, count 0 2006.257.21:31:27.42#ibcon#enter sib2, iclass 21, count 0 2006.257.21:31:27.42#ibcon#flushed, iclass 21, count 0 2006.257.21:31:27.42#ibcon#about to write, iclass 21, count 0 2006.257.21:31:27.42#ibcon#wrote, iclass 21, count 0 2006.257.21:31:27.42#ibcon#about to read 3, iclass 21, count 0 2006.257.21:31:27.45#ibcon#read 3, iclass 21, count 0 2006.257.21:31:27.45#ibcon#about to read 4, iclass 21, count 0 2006.257.21:31:27.45#ibcon#read 4, iclass 21, count 0 2006.257.21:31:27.45#ibcon#about to read 5, iclass 21, count 0 2006.257.21:31:27.45#ibcon#read 5, iclass 21, count 0 2006.257.21:31:27.45#ibcon#about to read 6, iclass 21, count 0 2006.257.21:31:27.45#ibcon#read 6, iclass 21, count 0 2006.257.21:31:27.45#ibcon#end of sib2, iclass 21, count 0 2006.257.21:31:27.45#ibcon#*after write, iclass 21, count 0 2006.257.21:31:27.45#ibcon#*before return 0, iclass 21, count 0 2006.257.21:31:27.45#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:31:27.45#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:31:27.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.21:31:27.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.21:31:27.45$vck44/vblo=2,634.99 2006.257.21:31:27.45#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.21:31:27.45#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.21:31:27.45#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:27.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:27.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:27.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:27.45#ibcon#enter wrdev, iclass 23, count 0 2006.257.21:31:27.45#ibcon#first serial, iclass 23, count 0 2006.257.21:31:27.45#ibcon#enter sib2, iclass 23, count 0 2006.257.21:31:27.45#ibcon#flushed, iclass 23, count 0 2006.257.21:31:27.45#ibcon#about to write, iclass 23, count 0 2006.257.21:31:27.45#ibcon#wrote, iclass 23, count 0 2006.257.21:31:27.45#ibcon#about to read 3, iclass 23, count 0 2006.257.21:31:27.47#ibcon#read 3, iclass 23, count 0 2006.257.21:31:27.47#ibcon#about to read 4, iclass 23, count 0 2006.257.21:31:27.47#ibcon#read 4, iclass 23, count 0 2006.257.21:31:27.47#ibcon#about to read 5, iclass 23, count 0 2006.257.21:31:27.47#ibcon#read 5, iclass 23, count 0 2006.257.21:31:27.47#ibcon#about to read 6, iclass 23, count 0 2006.257.21:31:27.47#ibcon#read 6, iclass 23, count 0 2006.257.21:31:27.47#ibcon#end of sib2, iclass 23, count 0 2006.257.21:31:27.47#ibcon#*mode == 0, iclass 23, count 0 2006.257.21:31:27.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.21:31:27.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.21:31:27.47#ibcon#*before write, iclass 23, count 0 2006.257.21:31:27.47#ibcon#enter sib2, iclass 23, count 0 2006.257.21:31:27.47#ibcon#flushed, iclass 23, count 0 2006.257.21:31:27.47#ibcon#about to write, iclass 23, count 0 2006.257.21:31:27.47#ibcon#wrote, iclass 23, count 0 2006.257.21:31:27.47#ibcon#about to read 3, iclass 23, count 0 2006.257.21:31:27.51#ibcon#read 3, iclass 23, count 0 2006.257.21:31:27.51#ibcon#about to read 4, iclass 23, count 0 2006.257.21:31:27.51#ibcon#read 4, iclass 23, count 0 2006.257.21:31:27.51#ibcon#about to read 5, iclass 23, count 0 2006.257.21:31:27.51#ibcon#read 5, iclass 23, count 0 2006.257.21:31:27.51#ibcon#about to read 6, iclass 23, count 0 2006.257.21:31:27.51#ibcon#read 6, iclass 23, count 0 2006.257.21:31:27.51#ibcon#end of sib2, iclass 23, count 0 2006.257.21:31:27.51#ibcon#*after write, iclass 23, count 0 2006.257.21:31:27.51#ibcon#*before return 0, iclass 23, count 0 2006.257.21:31:27.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:27.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:31:27.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.21:31:27.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.21:31:27.51$vck44/vb=2,5 2006.257.21:31:27.51#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.21:31:27.51#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.21:31:27.51#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:27.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:27.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:27.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:27.57#ibcon#enter wrdev, iclass 25, count 2 2006.257.21:31:27.57#ibcon#first serial, iclass 25, count 2 2006.257.21:31:27.57#ibcon#enter sib2, iclass 25, count 2 2006.257.21:31:27.57#ibcon#flushed, iclass 25, count 2 2006.257.21:31:27.57#ibcon#about to write, iclass 25, count 2 2006.257.21:31:27.57#ibcon#wrote, iclass 25, count 2 2006.257.21:31:27.57#ibcon#about to read 3, iclass 25, count 2 2006.257.21:31:27.59#ibcon#read 3, iclass 25, count 2 2006.257.21:31:27.59#ibcon#about to read 4, iclass 25, count 2 2006.257.21:31:27.59#ibcon#read 4, iclass 25, count 2 2006.257.21:31:27.59#ibcon#about to read 5, iclass 25, count 2 2006.257.21:31:27.59#ibcon#read 5, iclass 25, count 2 2006.257.21:31:27.59#ibcon#about to read 6, iclass 25, count 2 2006.257.21:31:27.59#ibcon#read 6, iclass 25, count 2 2006.257.21:31:27.59#ibcon#end of sib2, iclass 25, count 2 2006.257.21:31:27.59#ibcon#*mode == 0, iclass 25, count 2 2006.257.21:31:27.59#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.21:31:27.59#ibcon#[27=AT02-05\r\n] 2006.257.21:31:27.59#ibcon#*before write, iclass 25, count 2 2006.257.21:31:27.59#ibcon#enter sib2, iclass 25, count 2 2006.257.21:31:27.59#ibcon#flushed, iclass 25, count 2 2006.257.21:31:27.59#ibcon#about to write, iclass 25, count 2 2006.257.21:31:27.59#ibcon#wrote, iclass 25, count 2 2006.257.21:31:27.59#ibcon#about to read 3, iclass 25, count 2 2006.257.21:31:27.62#ibcon#read 3, iclass 25, count 2 2006.257.21:31:27.62#ibcon#about to read 4, iclass 25, count 2 2006.257.21:31:27.62#ibcon#read 4, iclass 25, count 2 2006.257.21:31:27.62#ibcon#about to read 5, iclass 25, count 2 2006.257.21:31:27.62#ibcon#read 5, iclass 25, count 2 2006.257.21:31:27.62#ibcon#about to read 6, iclass 25, count 2 2006.257.21:31:27.62#ibcon#read 6, iclass 25, count 2 2006.257.21:31:27.62#ibcon#end of sib2, iclass 25, count 2 2006.257.21:31:27.62#ibcon#*after write, iclass 25, count 2 2006.257.21:31:27.62#ibcon#*before return 0, iclass 25, count 2 2006.257.21:31:27.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:27.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:31:27.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.21:31:27.62#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:27.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:27.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:27.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:27.74#ibcon#enter wrdev, iclass 25, count 0 2006.257.21:31:27.74#ibcon#first serial, iclass 25, count 0 2006.257.21:31:27.74#ibcon#enter sib2, iclass 25, count 0 2006.257.21:31:27.74#ibcon#flushed, iclass 25, count 0 2006.257.21:31:27.74#ibcon#about to write, iclass 25, count 0 2006.257.21:31:27.74#ibcon#wrote, iclass 25, count 0 2006.257.21:31:27.74#ibcon#about to read 3, iclass 25, count 0 2006.257.21:31:27.76#ibcon#read 3, iclass 25, count 0 2006.257.21:31:27.76#ibcon#about to read 4, iclass 25, count 0 2006.257.21:31:27.76#ibcon#read 4, iclass 25, count 0 2006.257.21:31:27.76#ibcon#about to read 5, iclass 25, count 0 2006.257.21:31:27.76#ibcon#read 5, iclass 25, count 0 2006.257.21:31:27.76#ibcon#about to read 6, iclass 25, count 0 2006.257.21:31:27.76#ibcon#read 6, iclass 25, count 0 2006.257.21:31:27.76#ibcon#end of sib2, iclass 25, count 0 2006.257.21:31:27.76#ibcon#*mode == 0, iclass 25, count 0 2006.257.21:31:27.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.21:31:27.76#ibcon#[27=USB\r\n] 2006.257.21:31:27.76#ibcon#*before write, iclass 25, count 0 2006.257.21:31:27.76#ibcon#enter sib2, iclass 25, count 0 2006.257.21:31:27.76#ibcon#flushed, iclass 25, count 0 2006.257.21:31:27.76#ibcon#about to write, iclass 25, count 0 2006.257.21:31:27.76#ibcon#wrote, iclass 25, count 0 2006.257.21:31:27.76#ibcon#about to read 3, iclass 25, count 0 2006.257.21:31:27.79#ibcon#read 3, iclass 25, count 0 2006.257.21:31:27.79#ibcon#about to read 4, iclass 25, count 0 2006.257.21:31:27.79#ibcon#read 4, iclass 25, count 0 2006.257.21:31:27.79#ibcon#about to read 5, iclass 25, count 0 2006.257.21:31:27.79#ibcon#read 5, iclass 25, count 0 2006.257.21:31:27.79#ibcon#about to read 6, iclass 25, count 0 2006.257.21:31:27.79#ibcon#read 6, iclass 25, count 0 2006.257.21:31:27.79#ibcon#end of sib2, iclass 25, count 0 2006.257.21:31:27.79#ibcon#*after write, iclass 25, count 0 2006.257.21:31:27.79#ibcon#*before return 0, iclass 25, count 0 2006.257.21:31:27.79#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:27.79#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:31:27.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.21:31:27.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.21:31:27.79$vck44/vblo=3,649.99 2006.257.21:31:27.79#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.21:31:27.79#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.21:31:27.79#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:27.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:27.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:27.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:27.79#ibcon#enter wrdev, iclass 27, count 0 2006.257.21:31:27.79#ibcon#first serial, iclass 27, count 0 2006.257.21:31:27.79#ibcon#enter sib2, iclass 27, count 0 2006.257.21:31:27.79#ibcon#flushed, iclass 27, count 0 2006.257.21:31:27.79#ibcon#about to write, iclass 27, count 0 2006.257.21:31:27.79#ibcon#wrote, iclass 27, count 0 2006.257.21:31:27.79#ibcon#about to read 3, iclass 27, count 0 2006.257.21:31:27.81#ibcon#read 3, iclass 27, count 0 2006.257.21:31:27.81#ibcon#about to read 4, iclass 27, count 0 2006.257.21:31:27.81#ibcon#read 4, iclass 27, count 0 2006.257.21:31:27.81#ibcon#about to read 5, iclass 27, count 0 2006.257.21:31:27.81#ibcon#read 5, iclass 27, count 0 2006.257.21:31:27.81#ibcon#about to read 6, iclass 27, count 0 2006.257.21:31:27.81#ibcon#read 6, iclass 27, count 0 2006.257.21:31:27.81#ibcon#end of sib2, iclass 27, count 0 2006.257.21:31:27.81#ibcon#*mode == 0, iclass 27, count 0 2006.257.21:31:27.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.21:31:27.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.21:31:27.81#ibcon#*before write, iclass 27, count 0 2006.257.21:31:27.81#ibcon#enter sib2, iclass 27, count 0 2006.257.21:31:27.81#ibcon#flushed, iclass 27, count 0 2006.257.21:31:27.81#ibcon#about to write, iclass 27, count 0 2006.257.21:31:27.81#ibcon#wrote, iclass 27, count 0 2006.257.21:31:27.81#ibcon#about to read 3, iclass 27, count 0 2006.257.21:31:27.85#ibcon#read 3, iclass 27, count 0 2006.257.21:31:27.85#ibcon#about to read 4, iclass 27, count 0 2006.257.21:31:27.85#ibcon#read 4, iclass 27, count 0 2006.257.21:31:27.85#ibcon#about to read 5, iclass 27, count 0 2006.257.21:31:27.85#ibcon#read 5, iclass 27, count 0 2006.257.21:31:27.85#ibcon#about to read 6, iclass 27, count 0 2006.257.21:31:27.85#ibcon#read 6, iclass 27, count 0 2006.257.21:31:27.85#ibcon#end of sib2, iclass 27, count 0 2006.257.21:31:27.85#ibcon#*after write, iclass 27, count 0 2006.257.21:31:27.85#ibcon#*before return 0, iclass 27, count 0 2006.257.21:31:27.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:27.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:31:27.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.21:31:27.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.21:31:27.85$vck44/vb=3,4 2006.257.21:31:27.85#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.21:31:27.85#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.21:31:27.85#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:27.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:27.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:27.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:27.91#ibcon#enter wrdev, iclass 29, count 2 2006.257.21:31:27.91#ibcon#first serial, iclass 29, count 2 2006.257.21:31:27.91#ibcon#enter sib2, iclass 29, count 2 2006.257.21:31:27.91#ibcon#flushed, iclass 29, count 2 2006.257.21:31:27.91#ibcon#about to write, iclass 29, count 2 2006.257.21:31:27.91#ibcon#wrote, iclass 29, count 2 2006.257.21:31:27.91#ibcon#about to read 3, iclass 29, count 2 2006.257.21:31:27.93#ibcon#read 3, iclass 29, count 2 2006.257.21:31:27.93#ibcon#about to read 4, iclass 29, count 2 2006.257.21:31:27.93#ibcon#read 4, iclass 29, count 2 2006.257.21:31:27.93#ibcon#about to read 5, iclass 29, count 2 2006.257.21:31:27.93#ibcon#read 5, iclass 29, count 2 2006.257.21:31:27.93#ibcon#about to read 6, iclass 29, count 2 2006.257.21:31:27.93#ibcon#read 6, iclass 29, count 2 2006.257.21:31:27.93#ibcon#end of sib2, iclass 29, count 2 2006.257.21:31:27.93#ibcon#*mode == 0, iclass 29, count 2 2006.257.21:31:27.93#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.21:31:27.93#ibcon#[27=AT03-04\r\n] 2006.257.21:31:27.93#ibcon#*before write, iclass 29, count 2 2006.257.21:31:27.93#ibcon#enter sib2, iclass 29, count 2 2006.257.21:31:27.93#ibcon#flushed, iclass 29, count 2 2006.257.21:31:27.93#ibcon#about to write, iclass 29, count 2 2006.257.21:31:27.93#ibcon#wrote, iclass 29, count 2 2006.257.21:31:27.93#ibcon#about to read 3, iclass 29, count 2 2006.257.21:31:27.96#ibcon#read 3, iclass 29, count 2 2006.257.21:31:27.96#ibcon#about to read 4, iclass 29, count 2 2006.257.21:31:27.96#ibcon#read 4, iclass 29, count 2 2006.257.21:31:27.96#ibcon#about to read 5, iclass 29, count 2 2006.257.21:31:27.96#ibcon#read 5, iclass 29, count 2 2006.257.21:31:27.96#ibcon#about to read 6, iclass 29, count 2 2006.257.21:31:27.96#ibcon#read 6, iclass 29, count 2 2006.257.21:31:27.96#ibcon#end of sib2, iclass 29, count 2 2006.257.21:31:27.96#ibcon#*after write, iclass 29, count 2 2006.257.21:31:27.96#ibcon#*before return 0, iclass 29, count 2 2006.257.21:31:27.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:27.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:31:27.96#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.21:31:27.96#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:27.96#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:28.08#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:28.08#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:28.08#ibcon#enter wrdev, iclass 29, count 0 2006.257.21:31:28.08#ibcon#first serial, iclass 29, count 0 2006.257.21:31:28.08#ibcon#enter sib2, iclass 29, count 0 2006.257.21:31:28.08#ibcon#flushed, iclass 29, count 0 2006.257.21:31:28.08#ibcon#about to write, iclass 29, count 0 2006.257.21:31:28.08#ibcon#wrote, iclass 29, count 0 2006.257.21:31:28.08#ibcon#about to read 3, iclass 29, count 0 2006.257.21:31:28.10#ibcon#read 3, iclass 29, count 0 2006.257.21:31:28.10#ibcon#about to read 4, iclass 29, count 0 2006.257.21:31:28.10#ibcon#read 4, iclass 29, count 0 2006.257.21:31:28.10#ibcon#about to read 5, iclass 29, count 0 2006.257.21:31:28.10#ibcon#read 5, iclass 29, count 0 2006.257.21:31:28.10#ibcon#about to read 6, iclass 29, count 0 2006.257.21:31:28.10#ibcon#read 6, iclass 29, count 0 2006.257.21:31:28.10#ibcon#end of sib2, iclass 29, count 0 2006.257.21:31:28.10#ibcon#*mode == 0, iclass 29, count 0 2006.257.21:31:28.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.21:31:28.10#ibcon#[27=USB\r\n] 2006.257.21:31:28.10#ibcon#*before write, iclass 29, count 0 2006.257.21:31:28.10#ibcon#enter sib2, iclass 29, count 0 2006.257.21:31:28.10#ibcon#flushed, iclass 29, count 0 2006.257.21:31:28.10#ibcon#about to write, iclass 29, count 0 2006.257.21:31:28.10#ibcon#wrote, iclass 29, count 0 2006.257.21:31:28.10#ibcon#about to read 3, iclass 29, count 0 2006.257.21:31:28.13#ibcon#read 3, iclass 29, count 0 2006.257.21:31:28.13#ibcon#about to read 4, iclass 29, count 0 2006.257.21:31:28.13#ibcon#read 4, iclass 29, count 0 2006.257.21:31:28.13#ibcon#about to read 5, iclass 29, count 0 2006.257.21:31:28.13#ibcon#read 5, iclass 29, count 0 2006.257.21:31:28.13#ibcon#about to read 6, iclass 29, count 0 2006.257.21:31:28.13#ibcon#read 6, iclass 29, count 0 2006.257.21:31:28.13#ibcon#end of sib2, iclass 29, count 0 2006.257.21:31:28.13#ibcon#*after write, iclass 29, count 0 2006.257.21:31:28.13#ibcon#*before return 0, iclass 29, count 0 2006.257.21:31:28.13#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:28.13#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:31:28.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.21:31:28.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.21:31:28.13$vck44/vblo=4,679.99 2006.257.21:31:28.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.21:31:28.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.21:31:28.13#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:28.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:28.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:28.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:28.13#ibcon#enter wrdev, iclass 31, count 0 2006.257.21:31:28.13#ibcon#first serial, iclass 31, count 0 2006.257.21:31:28.13#ibcon#enter sib2, iclass 31, count 0 2006.257.21:31:28.13#ibcon#flushed, iclass 31, count 0 2006.257.21:31:28.13#ibcon#about to write, iclass 31, count 0 2006.257.21:31:28.13#ibcon#wrote, iclass 31, count 0 2006.257.21:31:28.13#ibcon#about to read 3, iclass 31, count 0 2006.257.21:31:28.15#ibcon#read 3, iclass 31, count 0 2006.257.21:31:28.15#ibcon#about to read 4, iclass 31, count 0 2006.257.21:31:28.15#ibcon#read 4, iclass 31, count 0 2006.257.21:31:28.15#ibcon#about to read 5, iclass 31, count 0 2006.257.21:31:28.15#ibcon#read 5, iclass 31, count 0 2006.257.21:31:28.15#ibcon#about to read 6, iclass 31, count 0 2006.257.21:31:28.15#ibcon#read 6, iclass 31, count 0 2006.257.21:31:28.15#ibcon#end of sib2, iclass 31, count 0 2006.257.21:31:28.15#ibcon#*mode == 0, iclass 31, count 0 2006.257.21:31:28.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.21:31:28.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.21:31:28.15#ibcon#*before write, iclass 31, count 0 2006.257.21:31:28.15#ibcon#enter sib2, iclass 31, count 0 2006.257.21:31:28.15#ibcon#flushed, iclass 31, count 0 2006.257.21:31:28.15#ibcon#about to write, iclass 31, count 0 2006.257.21:31:28.15#ibcon#wrote, iclass 31, count 0 2006.257.21:31:28.15#ibcon#about to read 3, iclass 31, count 0 2006.257.21:31:28.19#ibcon#read 3, iclass 31, count 0 2006.257.21:31:28.19#ibcon#about to read 4, iclass 31, count 0 2006.257.21:31:28.19#ibcon#read 4, iclass 31, count 0 2006.257.21:31:28.19#ibcon#about to read 5, iclass 31, count 0 2006.257.21:31:28.19#ibcon#read 5, iclass 31, count 0 2006.257.21:31:28.19#ibcon#about to read 6, iclass 31, count 0 2006.257.21:31:28.19#ibcon#read 6, iclass 31, count 0 2006.257.21:31:28.19#ibcon#end of sib2, iclass 31, count 0 2006.257.21:31:28.19#ibcon#*after write, iclass 31, count 0 2006.257.21:31:28.19#ibcon#*before return 0, iclass 31, count 0 2006.257.21:31:28.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:28.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:31:28.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.21:31:28.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.21:31:28.19$vck44/vb=4,5 2006.257.21:31:28.19#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.21:31:28.19#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.21:31:28.19#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:28.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:28.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:28.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:28.25#ibcon#enter wrdev, iclass 33, count 2 2006.257.21:31:28.25#ibcon#first serial, iclass 33, count 2 2006.257.21:31:28.25#ibcon#enter sib2, iclass 33, count 2 2006.257.21:31:28.25#ibcon#flushed, iclass 33, count 2 2006.257.21:31:28.25#ibcon#about to write, iclass 33, count 2 2006.257.21:31:28.25#ibcon#wrote, iclass 33, count 2 2006.257.21:31:28.25#ibcon#about to read 3, iclass 33, count 2 2006.257.21:31:28.27#ibcon#read 3, iclass 33, count 2 2006.257.21:31:28.27#ibcon#about to read 4, iclass 33, count 2 2006.257.21:31:28.27#ibcon#read 4, iclass 33, count 2 2006.257.21:31:28.27#ibcon#about to read 5, iclass 33, count 2 2006.257.21:31:28.27#ibcon#read 5, iclass 33, count 2 2006.257.21:31:28.27#ibcon#about to read 6, iclass 33, count 2 2006.257.21:31:28.27#ibcon#read 6, iclass 33, count 2 2006.257.21:31:28.27#ibcon#end of sib2, iclass 33, count 2 2006.257.21:31:28.27#ibcon#*mode == 0, iclass 33, count 2 2006.257.21:31:28.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.21:31:28.27#ibcon#[27=AT04-05\r\n] 2006.257.21:31:28.27#ibcon#*before write, iclass 33, count 2 2006.257.21:31:28.27#ibcon#enter sib2, iclass 33, count 2 2006.257.21:31:28.27#ibcon#flushed, iclass 33, count 2 2006.257.21:31:28.27#ibcon#about to write, iclass 33, count 2 2006.257.21:31:28.27#ibcon#wrote, iclass 33, count 2 2006.257.21:31:28.27#ibcon#about to read 3, iclass 33, count 2 2006.257.21:31:28.30#ibcon#read 3, iclass 33, count 2 2006.257.21:31:28.30#ibcon#about to read 4, iclass 33, count 2 2006.257.21:31:28.30#ibcon#read 4, iclass 33, count 2 2006.257.21:31:28.30#ibcon#about to read 5, iclass 33, count 2 2006.257.21:31:28.30#ibcon#read 5, iclass 33, count 2 2006.257.21:31:28.30#ibcon#about to read 6, iclass 33, count 2 2006.257.21:31:28.30#ibcon#read 6, iclass 33, count 2 2006.257.21:31:28.30#ibcon#end of sib2, iclass 33, count 2 2006.257.21:31:28.30#ibcon#*after write, iclass 33, count 2 2006.257.21:31:28.30#ibcon#*before return 0, iclass 33, count 2 2006.257.21:31:28.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:28.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:31:28.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.21:31:28.30#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:28.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:28.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:28.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:28.42#ibcon#enter wrdev, iclass 33, count 0 2006.257.21:31:28.42#ibcon#first serial, iclass 33, count 0 2006.257.21:31:28.42#ibcon#enter sib2, iclass 33, count 0 2006.257.21:31:28.42#ibcon#flushed, iclass 33, count 0 2006.257.21:31:28.42#ibcon#about to write, iclass 33, count 0 2006.257.21:31:28.42#ibcon#wrote, iclass 33, count 0 2006.257.21:31:28.42#ibcon#about to read 3, iclass 33, count 0 2006.257.21:31:28.44#ibcon#read 3, iclass 33, count 0 2006.257.21:31:28.44#ibcon#about to read 4, iclass 33, count 0 2006.257.21:31:28.44#ibcon#read 4, iclass 33, count 0 2006.257.21:31:28.44#ibcon#about to read 5, iclass 33, count 0 2006.257.21:31:28.44#ibcon#read 5, iclass 33, count 0 2006.257.21:31:28.44#ibcon#about to read 6, iclass 33, count 0 2006.257.21:31:28.44#ibcon#read 6, iclass 33, count 0 2006.257.21:31:28.44#ibcon#end of sib2, iclass 33, count 0 2006.257.21:31:28.44#ibcon#*mode == 0, iclass 33, count 0 2006.257.21:31:28.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.21:31:28.44#ibcon#[27=USB\r\n] 2006.257.21:31:28.44#ibcon#*before write, iclass 33, count 0 2006.257.21:31:28.44#ibcon#enter sib2, iclass 33, count 0 2006.257.21:31:28.44#ibcon#flushed, iclass 33, count 0 2006.257.21:31:28.44#ibcon#about to write, iclass 33, count 0 2006.257.21:31:28.44#ibcon#wrote, iclass 33, count 0 2006.257.21:31:28.44#ibcon#about to read 3, iclass 33, count 0 2006.257.21:31:28.47#ibcon#read 3, iclass 33, count 0 2006.257.21:31:28.47#ibcon#about to read 4, iclass 33, count 0 2006.257.21:31:28.47#ibcon#read 4, iclass 33, count 0 2006.257.21:31:28.47#ibcon#about to read 5, iclass 33, count 0 2006.257.21:31:28.47#ibcon#read 5, iclass 33, count 0 2006.257.21:31:28.47#ibcon#about to read 6, iclass 33, count 0 2006.257.21:31:28.47#ibcon#read 6, iclass 33, count 0 2006.257.21:31:28.47#ibcon#end of sib2, iclass 33, count 0 2006.257.21:31:28.47#ibcon#*after write, iclass 33, count 0 2006.257.21:31:28.47#ibcon#*before return 0, iclass 33, count 0 2006.257.21:31:28.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:28.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:31:28.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.21:31:28.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.21:31:28.47$vck44/vblo=5,709.99 2006.257.21:31:28.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.21:31:28.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.21:31:28.47#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:28.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:28.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:28.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:28.47#ibcon#enter wrdev, iclass 35, count 0 2006.257.21:31:28.47#ibcon#first serial, iclass 35, count 0 2006.257.21:31:28.47#ibcon#enter sib2, iclass 35, count 0 2006.257.21:31:28.47#ibcon#flushed, iclass 35, count 0 2006.257.21:31:28.47#ibcon#about to write, iclass 35, count 0 2006.257.21:31:28.47#ibcon#wrote, iclass 35, count 0 2006.257.21:31:28.47#ibcon#about to read 3, iclass 35, count 0 2006.257.21:31:28.49#ibcon#read 3, iclass 35, count 0 2006.257.21:31:28.49#ibcon#about to read 4, iclass 35, count 0 2006.257.21:31:28.49#ibcon#read 4, iclass 35, count 0 2006.257.21:31:28.49#ibcon#about to read 5, iclass 35, count 0 2006.257.21:31:28.49#ibcon#read 5, iclass 35, count 0 2006.257.21:31:28.49#ibcon#about to read 6, iclass 35, count 0 2006.257.21:31:28.49#ibcon#read 6, iclass 35, count 0 2006.257.21:31:28.49#ibcon#end of sib2, iclass 35, count 0 2006.257.21:31:28.49#ibcon#*mode == 0, iclass 35, count 0 2006.257.21:31:28.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.21:31:28.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.21:31:28.49#ibcon#*before write, iclass 35, count 0 2006.257.21:31:28.49#ibcon#enter sib2, iclass 35, count 0 2006.257.21:31:28.49#ibcon#flushed, iclass 35, count 0 2006.257.21:31:28.49#ibcon#about to write, iclass 35, count 0 2006.257.21:31:28.49#ibcon#wrote, iclass 35, count 0 2006.257.21:31:28.49#ibcon#about to read 3, iclass 35, count 0 2006.257.21:31:28.53#ibcon#read 3, iclass 35, count 0 2006.257.21:31:28.53#ibcon#about to read 4, iclass 35, count 0 2006.257.21:31:28.53#ibcon#read 4, iclass 35, count 0 2006.257.21:31:28.53#ibcon#about to read 5, iclass 35, count 0 2006.257.21:31:28.53#ibcon#read 5, iclass 35, count 0 2006.257.21:31:28.53#ibcon#about to read 6, iclass 35, count 0 2006.257.21:31:28.53#ibcon#read 6, iclass 35, count 0 2006.257.21:31:28.53#ibcon#end of sib2, iclass 35, count 0 2006.257.21:31:28.53#ibcon#*after write, iclass 35, count 0 2006.257.21:31:28.53#ibcon#*before return 0, iclass 35, count 0 2006.257.21:31:28.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:28.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:31:28.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.21:31:28.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.21:31:28.53$vck44/vb=5,4 2006.257.21:31:28.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.21:31:28.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.21:31:28.53#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:28.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:28.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:28.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:28.59#ibcon#enter wrdev, iclass 37, count 2 2006.257.21:31:28.59#ibcon#first serial, iclass 37, count 2 2006.257.21:31:28.59#ibcon#enter sib2, iclass 37, count 2 2006.257.21:31:28.59#ibcon#flushed, iclass 37, count 2 2006.257.21:31:28.59#ibcon#about to write, iclass 37, count 2 2006.257.21:31:28.59#ibcon#wrote, iclass 37, count 2 2006.257.21:31:28.59#ibcon#about to read 3, iclass 37, count 2 2006.257.21:31:28.61#ibcon#read 3, iclass 37, count 2 2006.257.21:31:28.61#ibcon#about to read 4, iclass 37, count 2 2006.257.21:31:28.61#ibcon#read 4, iclass 37, count 2 2006.257.21:31:28.61#ibcon#about to read 5, iclass 37, count 2 2006.257.21:31:28.61#ibcon#read 5, iclass 37, count 2 2006.257.21:31:28.61#ibcon#about to read 6, iclass 37, count 2 2006.257.21:31:28.61#ibcon#read 6, iclass 37, count 2 2006.257.21:31:28.61#ibcon#end of sib2, iclass 37, count 2 2006.257.21:31:28.61#ibcon#*mode == 0, iclass 37, count 2 2006.257.21:31:28.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.21:31:28.61#ibcon#[27=AT05-04\r\n] 2006.257.21:31:28.61#ibcon#*before write, iclass 37, count 2 2006.257.21:31:28.61#ibcon#enter sib2, iclass 37, count 2 2006.257.21:31:28.61#ibcon#flushed, iclass 37, count 2 2006.257.21:31:28.61#ibcon#about to write, iclass 37, count 2 2006.257.21:31:28.61#ibcon#wrote, iclass 37, count 2 2006.257.21:31:28.61#ibcon#about to read 3, iclass 37, count 2 2006.257.21:31:28.64#ibcon#read 3, iclass 37, count 2 2006.257.21:31:28.64#ibcon#about to read 4, iclass 37, count 2 2006.257.21:31:28.64#ibcon#read 4, iclass 37, count 2 2006.257.21:31:28.64#ibcon#about to read 5, iclass 37, count 2 2006.257.21:31:28.64#ibcon#read 5, iclass 37, count 2 2006.257.21:31:28.64#ibcon#about to read 6, iclass 37, count 2 2006.257.21:31:28.64#ibcon#read 6, iclass 37, count 2 2006.257.21:31:28.64#ibcon#end of sib2, iclass 37, count 2 2006.257.21:31:28.64#ibcon#*after write, iclass 37, count 2 2006.257.21:31:28.64#ibcon#*before return 0, iclass 37, count 2 2006.257.21:31:28.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:28.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:31:28.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.21:31:28.64#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:28.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:28.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:28.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:28.76#ibcon#enter wrdev, iclass 37, count 0 2006.257.21:31:28.76#ibcon#first serial, iclass 37, count 0 2006.257.21:31:28.76#ibcon#enter sib2, iclass 37, count 0 2006.257.21:31:28.76#ibcon#flushed, iclass 37, count 0 2006.257.21:31:28.76#ibcon#about to write, iclass 37, count 0 2006.257.21:31:28.76#ibcon#wrote, iclass 37, count 0 2006.257.21:31:28.76#ibcon#about to read 3, iclass 37, count 0 2006.257.21:31:28.78#ibcon#read 3, iclass 37, count 0 2006.257.21:31:28.78#ibcon#about to read 4, iclass 37, count 0 2006.257.21:31:28.78#ibcon#read 4, iclass 37, count 0 2006.257.21:31:28.78#ibcon#about to read 5, iclass 37, count 0 2006.257.21:31:28.78#ibcon#read 5, iclass 37, count 0 2006.257.21:31:28.78#ibcon#about to read 6, iclass 37, count 0 2006.257.21:31:28.78#ibcon#read 6, iclass 37, count 0 2006.257.21:31:28.78#ibcon#end of sib2, iclass 37, count 0 2006.257.21:31:28.78#ibcon#*mode == 0, iclass 37, count 0 2006.257.21:31:28.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.21:31:28.78#ibcon#[27=USB\r\n] 2006.257.21:31:28.78#ibcon#*before write, iclass 37, count 0 2006.257.21:31:28.78#ibcon#enter sib2, iclass 37, count 0 2006.257.21:31:28.78#ibcon#flushed, iclass 37, count 0 2006.257.21:31:28.78#ibcon#about to write, iclass 37, count 0 2006.257.21:31:28.78#ibcon#wrote, iclass 37, count 0 2006.257.21:31:28.78#ibcon#about to read 3, iclass 37, count 0 2006.257.21:31:28.81#ibcon#read 3, iclass 37, count 0 2006.257.21:31:28.81#ibcon#about to read 4, iclass 37, count 0 2006.257.21:31:28.81#ibcon#read 4, iclass 37, count 0 2006.257.21:31:28.81#ibcon#about to read 5, iclass 37, count 0 2006.257.21:31:28.81#ibcon#read 5, iclass 37, count 0 2006.257.21:31:28.81#ibcon#about to read 6, iclass 37, count 0 2006.257.21:31:28.81#ibcon#read 6, iclass 37, count 0 2006.257.21:31:28.81#ibcon#end of sib2, iclass 37, count 0 2006.257.21:31:28.81#ibcon#*after write, iclass 37, count 0 2006.257.21:31:28.81#ibcon#*before return 0, iclass 37, count 0 2006.257.21:31:28.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:28.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:31:28.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.21:31:28.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.21:31:28.81$vck44/vblo=6,719.99 2006.257.21:31:28.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.21:31:28.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.21:31:28.81#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:28.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:28.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:28.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:28.81#ibcon#enter wrdev, iclass 39, count 0 2006.257.21:31:28.81#ibcon#first serial, iclass 39, count 0 2006.257.21:31:28.81#ibcon#enter sib2, iclass 39, count 0 2006.257.21:31:28.81#ibcon#flushed, iclass 39, count 0 2006.257.21:31:28.81#ibcon#about to write, iclass 39, count 0 2006.257.21:31:28.81#ibcon#wrote, iclass 39, count 0 2006.257.21:31:28.81#ibcon#about to read 3, iclass 39, count 0 2006.257.21:31:28.83#ibcon#read 3, iclass 39, count 0 2006.257.21:31:28.83#ibcon#about to read 4, iclass 39, count 0 2006.257.21:31:28.83#ibcon#read 4, iclass 39, count 0 2006.257.21:31:28.83#ibcon#about to read 5, iclass 39, count 0 2006.257.21:31:28.83#ibcon#read 5, iclass 39, count 0 2006.257.21:31:28.83#ibcon#about to read 6, iclass 39, count 0 2006.257.21:31:28.83#ibcon#read 6, iclass 39, count 0 2006.257.21:31:28.83#ibcon#end of sib2, iclass 39, count 0 2006.257.21:31:28.83#ibcon#*mode == 0, iclass 39, count 0 2006.257.21:31:28.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.21:31:28.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.21:31:28.83#ibcon#*before write, iclass 39, count 0 2006.257.21:31:28.83#ibcon#enter sib2, iclass 39, count 0 2006.257.21:31:28.83#ibcon#flushed, iclass 39, count 0 2006.257.21:31:28.83#ibcon#about to write, iclass 39, count 0 2006.257.21:31:28.83#ibcon#wrote, iclass 39, count 0 2006.257.21:31:28.83#ibcon#about to read 3, iclass 39, count 0 2006.257.21:31:28.87#ibcon#read 3, iclass 39, count 0 2006.257.21:31:28.87#ibcon#about to read 4, iclass 39, count 0 2006.257.21:31:28.87#ibcon#read 4, iclass 39, count 0 2006.257.21:31:28.87#ibcon#about to read 5, iclass 39, count 0 2006.257.21:31:28.87#ibcon#read 5, iclass 39, count 0 2006.257.21:31:28.87#ibcon#about to read 6, iclass 39, count 0 2006.257.21:31:28.87#ibcon#read 6, iclass 39, count 0 2006.257.21:31:28.87#ibcon#end of sib2, iclass 39, count 0 2006.257.21:31:28.87#ibcon#*after write, iclass 39, count 0 2006.257.21:31:28.87#ibcon#*before return 0, iclass 39, count 0 2006.257.21:31:28.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:28.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:31:28.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.21:31:28.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.21:31:28.87$vck44/vb=6,4 2006.257.21:31:28.87#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.21:31:28.87#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.21:31:28.87#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:28.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:28.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:28.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:28.93#ibcon#enter wrdev, iclass 3, count 2 2006.257.21:31:28.93#ibcon#first serial, iclass 3, count 2 2006.257.21:31:28.93#ibcon#enter sib2, iclass 3, count 2 2006.257.21:31:28.93#ibcon#flushed, iclass 3, count 2 2006.257.21:31:28.93#ibcon#about to write, iclass 3, count 2 2006.257.21:31:28.93#ibcon#wrote, iclass 3, count 2 2006.257.21:31:28.93#ibcon#about to read 3, iclass 3, count 2 2006.257.21:31:28.95#ibcon#read 3, iclass 3, count 2 2006.257.21:31:28.95#ibcon#about to read 4, iclass 3, count 2 2006.257.21:31:28.95#ibcon#read 4, iclass 3, count 2 2006.257.21:31:28.95#ibcon#about to read 5, iclass 3, count 2 2006.257.21:31:28.95#ibcon#read 5, iclass 3, count 2 2006.257.21:31:28.95#ibcon#about to read 6, iclass 3, count 2 2006.257.21:31:28.95#ibcon#read 6, iclass 3, count 2 2006.257.21:31:28.95#ibcon#end of sib2, iclass 3, count 2 2006.257.21:31:28.95#ibcon#*mode == 0, iclass 3, count 2 2006.257.21:31:28.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.21:31:28.95#ibcon#[27=AT06-04\r\n] 2006.257.21:31:28.95#ibcon#*before write, iclass 3, count 2 2006.257.21:31:28.95#ibcon#enter sib2, iclass 3, count 2 2006.257.21:31:28.95#ibcon#flushed, iclass 3, count 2 2006.257.21:31:28.95#ibcon#about to write, iclass 3, count 2 2006.257.21:31:28.95#ibcon#wrote, iclass 3, count 2 2006.257.21:31:28.95#ibcon#about to read 3, iclass 3, count 2 2006.257.21:31:28.98#ibcon#read 3, iclass 3, count 2 2006.257.21:31:28.98#ibcon#about to read 4, iclass 3, count 2 2006.257.21:31:28.98#ibcon#read 4, iclass 3, count 2 2006.257.21:31:28.98#ibcon#about to read 5, iclass 3, count 2 2006.257.21:31:28.98#ibcon#read 5, iclass 3, count 2 2006.257.21:31:28.98#ibcon#about to read 6, iclass 3, count 2 2006.257.21:31:28.98#ibcon#read 6, iclass 3, count 2 2006.257.21:31:28.98#ibcon#end of sib2, iclass 3, count 2 2006.257.21:31:28.98#ibcon#*after write, iclass 3, count 2 2006.257.21:31:28.98#ibcon#*before return 0, iclass 3, count 2 2006.257.21:31:28.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:28.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:31:28.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.21:31:28.98#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:28.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:29.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:29.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:29.10#ibcon#enter wrdev, iclass 3, count 0 2006.257.21:31:29.10#ibcon#first serial, iclass 3, count 0 2006.257.21:31:29.10#ibcon#enter sib2, iclass 3, count 0 2006.257.21:31:29.10#ibcon#flushed, iclass 3, count 0 2006.257.21:31:29.10#ibcon#about to write, iclass 3, count 0 2006.257.21:31:29.10#ibcon#wrote, iclass 3, count 0 2006.257.21:31:29.10#ibcon#about to read 3, iclass 3, count 0 2006.257.21:31:29.12#ibcon#read 3, iclass 3, count 0 2006.257.21:31:29.12#ibcon#about to read 4, iclass 3, count 0 2006.257.21:31:29.12#ibcon#read 4, iclass 3, count 0 2006.257.21:31:29.12#ibcon#about to read 5, iclass 3, count 0 2006.257.21:31:29.12#ibcon#read 5, iclass 3, count 0 2006.257.21:31:29.12#ibcon#about to read 6, iclass 3, count 0 2006.257.21:31:29.12#ibcon#read 6, iclass 3, count 0 2006.257.21:31:29.12#ibcon#end of sib2, iclass 3, count 0 2006.257.21:31:29.12#ibcon#*mode == 0, iclass 3, count 0 2006.257.21:31:29.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.21:31:29.12#ibcon#[27=USB\r\n] 2006.257.21:31:29.12#ibcon#*before write, iclass 3, count 0 2006.257.21:31:29.12#ibcon#enter sib2, iclass 3, count 0 2006.257.21:31:29.12#ibcon#flushed, iclass 3, count 0 2006.257.21:31:29.12#ibcon#about to write, iclass 3, count 0 2006.257.21:31:29.12#ibcon#wrote, iclass 3, count 0 2006.257.21:31:29.12#ibcon#about to read 3, iclass 3, count 0 2006.257.21:31:29.15#ibcon#read 3, iclass 3, count 0 2006.257.21:31:29.15#ibcon#about to read 4, iclass 3, count 0 2006.257.21:31:29.15#ibcon#read 4, iclass 3, count 0 2006.257.21:31:29.15#ibcon#about to read 5, iclass 3, count 0 2006.257.21:31:29.15#ibcon#read 5, iclass 3, count 0 2006.257.21:31:29.15#ibcon#about to read 6, iclass 3, count 0 2006.257.21:31:29.15#ibcon#read 6, iclass 3, count 0 2006.257.21:31:29.15#ibcon#end of sib2, iclass 3, count 0 2006.257.21:31:29.15#ibcon#*after write, iclass 3, count 0 2006.257.21:31:29.15#ibcon#*before return 0, iclass 3, count 0 2006.257.21:31:29.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:29.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:31:29.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.21:31:29.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.21:31:29.15$vck44/vblo=7,734.99 2006.257.21:31:29.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.21:31:29.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.21:31:29.15#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:29.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:29.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:29.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:29.15#ibcon#enter wrdev, iclass 5, count 0 2006.257.21:31:29.15#ibcon#first serial, iclass 5, count 0 2006.257.21:31:29.15#ibcon#enter sib2, iclass 5, count 0 2006.257.21:31:29.15#ibcon#flushed, iclass 5, count 0 2006.257.21:31:29.15#ibcon#about to write, iclass 5, count 0 2006.257.21:31:29.15#ibcon#wrote, iclass 5, count 0 2006.257.21:31:29.15#ibcon#about to read 3, iclass 5, count 0 2006.257.21:31:29.17#ibcon#read 3, iclass 5, count 0 2006.257.21:31:29.17#ibcon#about to read 4, iclass 5, count 0 2006.257.21:31:29.17#ibcon#read 4, iclass 5, count 0 2006.257.21:31:29.17#ibcon#about to read 5, iclass 5, count 0 2006.257.21:31:29.17#ibcon#read 5, iclass 5, count 0 2006.257.21:31:29.17#ibcon#about to read 6, iclass 5, count 0 2006.257.21:31:29.17#ibcon#read 6, iclass 5, count 0 2006.257.21:31:29.17#ibcon#end of sib2, iclass 5, count 0 2006.257.21:31:29.17#ibcon#*mode == 0, iclass 5, count 0 2006.257.21:31:29.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.21:31:29.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.21:31:29.17#ibcon#*before write, iclass 5, count 0 2006.257.21:31:29.17#ibcon#enter sib2, iclass 5, count 0 2006.257.21:31:29.17#ibcon#flushed, iclass 5, count 0 2006.257.21:31:29.17#ibcon#about to write, iclass 5, count 0 2006.257.21:31:29.17#ibcon#wrote, iclass 5, count 0 2006.257.21:31:29.17#ibcon#about to read 3, iclass 5, count 0 2006.257.21:31:29.21#ibcon#read 3, iclass 5, count 0 2006.257.21:31:29.21#ibcon#about to read 4, iclass 5, count 0 2006.257.21:31:29.21#ibcon#read 4, iclass 5, count 0 2006.257.21:31:29.21#ibcon#about to read 5, iclass 5, count 0 2006.257.21:31:29.21#ibcon#read 5, iclass 5, count 0 2006.257.21:31:29.21#ibcon#about to read 6, iclass 5, count 0 2006.257.21:31:29.21#ibcon#read 6, iclass 5, count 0 2006.257.21:31:29.21#ibcon#end of sib2, iclass 5, count 0 2006.257.21:31:29.21#ibcon#*after write, iclass 5, count 0 2006.257.21:31:29.21#ibcon#*before return 0, iclass 5, count 0 2006.257.21:31:29.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:29.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:31:29.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.21:31:29.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.21:31:29.21$vck44/vb=7,4 2006.257.21:31:29.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.21:31:29.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.21:31:29.21#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:29.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:29.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:29.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:29.27#ibcon#enter wrdev, iclass 7, count 2 2006.257.21:31:29.27#ibcon#first serial, iclass 7, count 2 2006.257.21:31:29.27#ibcon#enter sib2, iclass 7, count 2 2006.257.21:31:29.27#ibcon#flushed, iclass 7, count 2 2006.257.21:31:29.27#ibcon#about to write, iclass 7, count 2 2006.257.21:31:29.27#ibcon#wrote, iclass 7, count 2 2006.257.21:31:29.27#ibcon#about to read 3, iclass 7, count 2 2006.257.21:31:29.28#abcon#<5=/14 1.0 2.9 17.83 951015.5\r\n> 2006.257.21:31:29.29#ibcon#read 3, iclass 7, count 2 2006.257.21:31:29.29#ibcon#about to read 4, iclass 7, count 2 2006.257.21:31:29.29#ibcon#read 4, iclass 7, count 2 2006.257.21:31:29.29#ibcon#about to read 5, iclass 7, count 2 2006.257.21:31:29.29#ibcon#read 5, iclass 7, count 2 2006.257.21:31:29.29#ibcon#about to read 6, iclass 7, count 2 2006.257.21:31:29.29#ibcon#read 6, iclass 7, count 2 2006.257.21:31:29.29#ibcon#end of sib2, iclass 7, count 2 2006.257.21:31:29.29#ibcon#*mode == 0, iclass 7, count 2 2006.257.21:31:29.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.21:31:29.29#ibcon#[27=AT07-04\r\n] 2006.257.21:31:29.29#ibcon#*before write, iclass 7, count 2 2006.257.21:31:29.29#ibcon#enter sib2, iclass 7, count 2 2006.257.21:31:29.29#ibcon#flushed, iclass 7, count 2 2006.257.21:31:29.29#ibcon#about to write, iclass 7, count 2 2006.257.21:31:29.29#ibcon#wrote, iclass 7, count 2 2006.257.21:31:29.29#ibcon#about to read 3, iclass 7, count 2 2006.257.21:31:29.30#abcon#{5=INTERFACE CLEAR} 2006.257.21:31:29.32#ibcon#read 3, iclass 7, count 2 2006.257.21:31:29.32#ibcon#about to read 4, iclass 7, count 2 2006.257.21:31:29.32#ibcon#read 4, iclass 7, count 2 2006.257.21:31:29.32#ibcon#about to read 5, iclass 7, count 2 2006.257.21:31:29.32#ibcon#read 5, iclass 7, count 2 2006.257.21:31:29.32#ibcon#about to read 6, iclass 7, count 2 2006.257.21:31:29.32#ibcon#read 6, iclass 7, count 2 2006.257.21:31:29.32#ibcon#end of sib2, iclass 7, count 2 2006.257.21:31:29.32#ibcon#*after write, iclass 7, count 2 2006.257.21:31:29.32#ibcon#*before return 0, iclass 7, count 2 2006.257.21:31:29.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:29.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:31:29.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.21:31:29.32#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:29.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:29.36#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:31:29.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:29.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:29.44#ibcon#enter wrdev, iclass 7, count 0 2006.257.21:31:29.44#ibcon#first serial, iclass 7, count 0 2006.257.21:31:29.44#ibcon#enter sib2, iclass 7, count 0 2006.257.21:31:29.44#ibcon#flushed, iclass 7, count 0 2006.257.21:31:29.44#ibcon#about to write, iclass 7, count 0 2006.257.21:31:29.44#ibcon#wrote, iclass 7, count 0 2006.257.21:31:29.44#ibcon#about to read 3, iclass 7, count 0 2006.257.21:31:29.46#ibcon#read 3, iclass 7, count 0 2006.257.21:31:29.46#ibcon#about to read 4, iclass 7, count 0 2006.257.21:31:29.46#ibcon#read 4, iclass 7, count 0 2006.257.21:31:29.46#ibcon#about to read 5, iclass 7, count 0 2006.257.21:31:29.46#ibcon#read 5, iclass 7, count 0 2006.257.21:31:29.46#ibcon#about to read 6, iclass 7, count 0 2006.257.21:31:29.46#ibcon#read 6, iclass 7, count 0 2006.257.21:31:29.46#ibcon#end of sib2, iclass 7, count 0 2006.257.21:31:29.46#ibcon#*mode == 0, iclass 7, count 0 2006.257.21:31:29.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.21:31:29.46#ibcon#[27=USB\r\n] 2006.257.21:31:29.46#ibcon#*before write, iclass 7, count 0 2006.257.21:31:29.46#ibcon#enter sib2, iclass 7, count 0 2006.257.21:31:29.46#ibcon#flushed, iclass 7, count 0 2006.257.21:31:29.46#ibcon#about to write, iclass 7, count 0 2006.257.21:31:29.46#ibcon#wrote, iclass 7, count 0 2006.257.21:31:29.46#ibcon#about to read 3, iclass 7, count 0 2006.257.21:31:29.49#ibcon#read 3, iclass 7, count 0 2006.257.21:31:29.49#ibcon#about to read 4, iclass 7, count 0 2006.257.21:31:29.49#ibcon#read 4, iclass 7, count 0 2006.257.21:31:29.49#ibcon#about to read 5, iclass 7, count 0 2006.257.21:31:29.49#ibcon#read 5, iclass 7, count 0 2006.257.21:31:29.49#ibcon#about to read 6, iclass 7, count 0 2006.257.21:31:29.49#ibcon#read 6, iclass 7, count 0 2006.257.21:31:29.49#ibcon#end of sib2, iclass 7, count 0 2006.257.21:31:29.49#ibcon#*after write, iclass 7, count 0 2006.257.21:31:29.49#ibcon#*before return 0, iclass 7, count 0 2006.257.21:31:29.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:29.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:31:29.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.21:31:29.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.21:31:29.49$vck44/vblo=8,744.99 2006.257.21:31:29.49#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.21:31:29.49#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.21:31:29.49#ibcon#ireg 17 cls_cnt 0 2006.257.21:31:29.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:29.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:29.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:29.49#ibcon#enter wrdev, iclass 15, count 0 2006.257.21:31:29.49#ibcon#first serial, iclass 15, count 0 2006.257.21:31:29.49#ibcon#enter sib2, iclass 15, count 0 2006.257.21:31:29.49#ibcon#flushed, iclass 15, count 0 2006.257.21:31:29.49#ibcon#about to write, iclass 15, count 0 2006.257.21:31:29.49#ibcon#wrote, iclass 15, count 0 2006.257.21:31:29.49#ibcon#about to read 3, iclass 15, count 0 2006.257.21:31:29.51#ibcon#read 3, iclass 15, count 0 2006.257.21:31:29.51#ibcon#about to read 4, iclass 15, count 0 2006.257.21:31:29.51#ibcon#read 4, iclass 15, count 0 2006.257.21:31:29.51#ibcon#about to read 5, iclass 15, count 0 2006.257.21:31:29.51#ibcon#read 5, iclass 15, count 0 2006.257.21:31:29.51#ibcon#about to read 6, iclass 15, count 0 2006.257.21:31:29.51#ibcon#read 6, iclass 15, count 0 2006.257.21:31:29.51#ibcon#end of sib2, iclass 15, count 0 2006.257.21:31:29.51#ibcon#*mode == 0, iclass 15, count 0 2006.257.21:31:29.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.21:31:29.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.21:31:29.51#ibcon#*before write, iclass 15, count 0 2006.257.21:31:29.51#ibcon#enter sib2, iclass 15, count 0 2006.257.21:31:29.51#ibcon#flushed, iclass 15, count 0 2006.257.21:31:29.51#ibcon#about to write, iclass 15, count 0 2006.257.21:31:29.51#ibcon#wrote, iclass 15, count 0 2006.257.21:31:29.51#ibcon#about to read 3, iclass 15, count 0 2006.257.21:31:29.55#ibcon#read 3, iclass 15, count 0 2006.257.21:31:29.55#ibcon#about to read 4, iclass 15, count 0 2006.257.21:31:29.55#ibcon#read 4, iclass 15, count 0 2006.257.21:31:29.55#ibcon#about to read 5, iclass 15, count 0 2006.257.21:31:29.55#ibcon#read 5, iclass 15, count 0 2006.257.21:31:29.55#ibcon#about to read 6, iclass 15, count 0 2006.257.21:31:29.55#ibcon#read 6, iclass 15, count 0 2006.257.21:31:29.55#ibcon#end of sib2, iclass 15, count 0 2006.257.21:31:29.55#ibcon#*after write, iclass 15, count 0 2006.257.21:31:29.55#ibcon#*before return 0, iclass 15, count 0 2006.257.21:31:29.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:29.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:31:29.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.21:31:29.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.21:31:29.55$vck44/vb=8,4 2006.257.21:31:29.55#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.21:31:29.55#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.21:31:29.55#ibcon#ireg 11 cls_cnt 2 2006.257.21:31:29.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:29.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:29.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:29.61#ibcon#enter wrdev, iclass 17, count 2 2006.257.21:31:29.61#ibcon#first serial, iclass 17, count 2 2006.257.21:31:29.61#ibcon#enter sib2, iclass 17, count 2 2006.257.21:31:29.61#ibcon#flushed, iclass 17, count 2 2006.257.21:31:29.61#ibcon#about to write, iclass 17, count 2 2006.257.21:31:29.61#ibcon#wrote, iclass 17, count 2 2006.257.21:31:29.61#ibcon#about to read 3, iclass 17, count 2 2006.257.21:31:29.63#ibcon#read 3, iclass 17, count 2 2006.257.21:31:29.63#ibcon#about to read 4, iclass 17, count 2 2006.257.21:31:29.63#ibcon#read 4, iclass 17, count 2 2006.257.21:31:29.63#ibcon#about to read 5, iclass 17, count 2 2006.257.21:31:29.63#ibcon#read 5, iclass 17, count 2 2006.257.21:31:29.63#ibcon#about to read 6, iclass 17, count 2 2006.257.21:31:29.63#ibcon#read 6, iclass 17, count 2 2006.257.21:31:29.63#ibcon#end of sib2, iclass 17, count 2 2006.257.21:31:29.63#ibcon#*mode == 0, iclass 17, count 2 2006.257.21:31:29.63#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.21:31:29.63#ibcon#[27=AT08-04\r\n] 2006.257.21:31:29.63#ibcon#*before write, iclass 17, count 2 2006.257.21:31:29.63#ibcon#enter sib2, iclass 17, count 2 2006.257.21:31:29.63#ibcon#flushed, iclass 17, count 2 2006.257.21:31:29.63#ibcon#about to write, iclass 17, count 2 2006.257.21:31:29.63#ibcon#wrote, iclass 17, count 2 2006.257.21:31:29.63#ibcon#about to read 3, iclass 17, count 2 2006.257.21:31:29.66#ibcon#read 3, iclass 17, count 2 2006.257.21:31:29.66#ibcon#about to read 4, iclass 17, count 2 2006.257.21:31:29.66#ibcon#read 4, iclass 17, count 2 2006.257.21:31:29.66#ibcon#about to read 5, iclass 17, count 2 2006.257.21:31:29.66#ibcon#read 5, iclass 17, count 2 2006.257.21:31:29.66#ibcon#about to read 6, iclass 17, count 2 2006.257.21:31:29.66#ibcon#read 6, iclass 17, count 2 2006.257.21:31:29.66#ibcon#end of sib2, iclass 17, count 2 2006.257.21:31:29.66#ibcon#*after write, iclass 17, count 2 2006.257.21:31:29.66#ibcon#*before return 0, iclass 17, count 2 2006.257.21:31:29.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:29.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:31:29.66#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.21:31:29.66#ibcon#ireg 7 cls_cnt 0 2006.257.21:31:29.66#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:29.78#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:29.78#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:29.78#ibcon#enter wrdev, iclass 17, count 0 2006.257.21:31:29.78#ibcon#first serial, iclass 17, count 0 2006.257.21:31:29.78#ibcon#enter sib2, iclass 17, count 0 2006.257.21:31:29.78#ibcon#flushed, iclass 17, count 0 2006.257.21:31:29.78#ibcon#about to write, iclass 17, count 0 2006.257.21:31:29.78#ibcon#wrote, iclass 17, count 0 2006.257.21:31:29.78#ibcon#about to read 3, iclass 17, count 0 2006.257.21:31:29.80#ibcon#read 3, iclass 17, count 0 2006.257.21:31:29.80#ibcon#about to read 4, iclass 17, count 0 2006.257.21:31:29.80#ibcon#read 4, iclass 17, count 0 2006.257.21:31:29.80#ibcon#about to read 5, iclass 17, count 0 2006.257.21:31:29.80#ibcon#read 5, iclass 17, count 0 2006.257.21:31:29.80#ibcon#about to read 6, iclass 17, count 0 2006.257.21:31:29.80#ibcon#read 6, iclass 17, count 0 2006.257.21:31:29.80#ibcon#end of sib2, iclass 17, count 0 2006.257.21:31:29.80#ibcon#*mode == 0, iclass 17, count 0 2006.257.21:31:29.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.21:31:29.80#ibcon#[27=USB\r\n] 2006.257.21:31:29.80#ibcon#*before write, iclass 17, count 0 2006.257.21:31:29.80#ibcon#enter sib2, iclass 17, count 0 2006.257.21:31:29.80#ibcon#flushed, iclass 17, count 0 2006.257.21:31:29.80#ibcon#about to write, iclass 17, count 0 2006.257.21:31:29.80#ibcon#wrote, iclass 17, count 0 2006.257.21:31:29.80#ibcon#about to read 3, iclass 17, count 0 2006.257.21:31:29.83#ibcon#read 3, iclass 17, count 0 2006.257.21:31:29.83#ibcon#about to read 4, iclass 17, count 0 2006.257.21:31:29.83#ibcon#read 4, iclass 17, count 0 2006.257.21:31:29.83#ibcon#about to read 5, iclass 17, count 0 2006.257.21:31:29.83#ibcon#read 5, iclass 17, count 0 2006.257.21:31:29.83#ibcon#about to read 6, iclass 17, count 0 2006.257.21:31:29.83#ibcon#read 6, iclass 17, count 0 2006.257.21:31:29.83#ibcon#end of sib2, iclass 17, count 0 2006.257.21:31:29.83#ibcon#*after write, iclass 17, count 0 2006.257.21:31:29.83#ibcon#*before return 0, iclass 17, count 0 2006.257.21:31:29.83#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:29.83#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:31:29.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.21:31:29.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.21:31:29.83$vck44/vabw=wide 2006.257.21:31:29.83#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.21:31:29.83#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.21:31:29.83#ibcon#ireg 8 cls_cnt 0 2006.257.21:31:29.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:29.83#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:29.83#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:29.83#ibcon#enter wrdev, iclass 19, count 0 2006.257.21:31:29.83#ibcon#first serial, iclass 19, count 0 2006.257.21:31:29.83#ibcon#enter sib2, iclass 19, count 0 2006.257.21:31:29.83#ibcon#flushed, iclass 19, count 0 2006.257.21:31:29.83#ibcon#about to write, iclass 19, count 0 2006.257.21:31:29.83#ibcon#wrote, iclass 19, count 0 2006.257.21:31:29.83#ibcon#about to read 3, iclass 19, count 0 2006.257.21:31:29.85#ibcon#read 3, iclass 19, count 0 2006.257.21:31:29.85#ibcon#about to read 4, iclass 19, count 0 2006.257.21:31:29.85#ibcon#read 4, iclass 19, count 0 2006.257.21:31:29.85#ibcon#about to read 5, iclass 19, count 0 2006.257.21:31:29.85#ibcon#read 5, iclass 19, count 0 2006.257.21:31:29.85#ibcon#about to read 6, iclass 19, count 0 2006.257.21:31:29.85#ibcon#read 6, iclass 19, count 0 2006.257.21:31:29.85#ibcon#end of sib2, iclass 19, count 0 2006.257.21:31:29.85#ibcon#*mode == 0, iclass 19, count 0 2006.257.21:31:29.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.21:31:29.85#ibcon#[25=BW32\r\n] 2006.257.21:31:29.85#ibcon#*before write, iclass 19, count 0 2006.257.21:31:29.85#ibcon#enter sib2, iclass 19, count 0 2006.257.21:31:29.85#ibcon#flushed, iclass 19, count 0 2006.257.21:31:29.85#ibcon#about to write, iclass 19, count 0 2006.257.21:31:29.85#ibcon#wrote, iclass 19, count 0 2006.257.21:31:29.85#ibcon#about to read 3, iclass 19, count 0 2006.257.21:31:29.88#ibcon#read 3, iclass 19, count 0 2006.257.21:31:29.88#ibcon#about to read 4, iclass 19, count 0 2006.257.21:31:29.88#ibcon#read 4, iclass 19, count 0 2006.257.21:31:29.88#ibcon#about to read 5, iclass 19, count 0 2006.257.21:31:29.88#ibcon#read 5, iclass 19, count 0 2006.257.21:31:29.88#ibcon#about to read 6, iclass 19, count 0 2006.257.21:31:29.88#ibcon#read 6, iclass 19, count 0 2006.257.21:31:29.88#ibcon#end of sib2, iclass 19, count 0 2006.257.21:31:29.88#ibcon#*after write, iclass 19, count 0 2006.257.21:31:29.88#ibcon#*before return 0, iclass 19, count 0 2006.257.21:31:29.88#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:29.88#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:31:29.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.21:31:29.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.21:31:29.88$vck44/vbbw=wide 2006.257.21:31:29.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.21:31:29.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.21:31:29.88#ibcon#ireg 8 cls_cnt 0 2006.257.21:31:29.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:31:29.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:31:29.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:31:29.95#ibcon#enter wrdev, iclass 21, count 0 2006.257.21:31:29.95#ibcon#first serial, iclass 21, count 0 2006.257.21:31:29.95#ibcon#enter sib2, iclass 21, count 0 2006.257.21:31:29.95#ibcon#flushed, iclass 21, count 0 2006.257.21:31:29.95#ibcon#about to write, iclass 21, count 0 2006.257.21:31:29.95#ibcon#wrote, iclass 21, count 0 2006.257.21:31:29.95#ibcon#about to read 3, iclass 21, count 0 2006.257.21:31:29.97#ibcon#read 3, iclass 21, count 0 2006.257.21:31:29.97#ibcon#about to read 4, iclass 21, count 0 2006.257.21:31:29.97#ibcon#read 4, iclass 21, count 0 2006.257.21:31:29.97#ibcon#about to read 5, iclass 21, count 0 2006.257.21:31:29.97#ibcon#read 5, iclass 21, count 0 2006.257.21:31:29.97#ibcon#about to read 6, iclass 21, count 0 2006.257.21:31:29.97#ibcon#read 6, iclass 21, count 0 2006.257.21:31:29.97#ibcon#end of sib2, iclass 21, count 0 2006.257.21:31:29.97#ibcon#*mode == 0, iclass 21, count 0 2006.257.21:31:29.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.21:31:29.97#ibcon#[27=BW32\r\n] 2006.257.21:31:29.97#ibcon#*before write, iclass 21, count 0 2006.257.21:31:29.97#ibcon#enter sib2, iclass 21, count 0 2006.257.21:31:29.97#ibcon#flushed, iclass 21, count 0 2006.257.21:31:29.97#ibcon#about to write, iclass 21, count 0 2006.257.21:31:29.97#ibcon#wrote, iclass 21, count 0 2006.257.21:31:29.97#ibcon#about to read 3, iclass 21, count 0 2006.257.21:31:30.00#ibcon#read 3, iclass 21, count 0 2006.257.21:31:30.00#ibcon#about to read 4, iclass 21, count 0 2006.257.21:31:30.00#ibcon#read 4, iclass 21, count 0 2006.257.21:31:30.00#ibcon#about to read 5, iclass 21, count 0 2006.257.21:31:30.00#ibcon#read 5, iclass 21, count 0 2006.257.21:31:30.00#ibcon#about to read 6, iclass 21, count 0 2006.257.21:31:30.00#ibcon#read 6, iclass 21, count 0 2006.257.21:31:30.00#ibcon#end of sib2, iclass 21, count 0 2006.257.21:31:30.00#ibcon#*after write, iclass 21, count 0 2006.257.21:31:30.00#ibcon#*before return 0, iclass 21, count 0 2006.257.21:31:30.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:31:30.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:31:30.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.21:31:30.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.21:31:30.00$setupk4/ifdk4 2006.257.21:31:30.00$ifdk4/lo= 2006.257.21:31:30.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.21:31:30.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.21:31:30.00$ifdk4/patch= 2006.257.21:31:30.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.21:31:30.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.21:31:30.00$setupk4/!*+20s 2006.257.21:31:39.45#abcon#<5=/14 1.1 2.9 17.83 951015.5\r\n> 2006.257.21:31:39.47#abcon#{5=INTERFACE CLEAR} 2006.257.21:31:39.53#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:31:44.51$setupk4/"tpicd 2006.257.21:31:44.51$setupk4/echo=off 2006.257.21:31:44.51$setupk4/xlog=off 2006.257.21:31:44.51:!2006.257.21:34:04 2006.257.21:32:13.14#trakl#Source acquired 2006.257.21:32:15.14#flagr#flagr/antenna,acquired 2006.257.21:34:04.00:preob 2006.257.21:34:04.13/onsource/TRACKING 2006.257.21:34:04.13:!2006.257.21:34:14 2006.257.21:34:14.00:"tape 2006.257.21:34:14.00:"st=record 2006.257.21:34:14.00:data_valid=on 2006.257.21:34:14.00:midob 2006.257.21:34:15.13/onsource/TRACKING 2006.257.21:34:15.13/wx/17.85,1015.4,95 2006.257.21:34:15.28/cable/+6.4850E-03 2006.257.21:34:16.37/va/01,08,usb,yes,32,34 2006.257.21:34:16.37/va/02,07,usb,yes,34,35 2006.257.21:34:16.37/va/03,08,usb,yes,31,33 2006.257.21:34:16.37/va/04,07,usb,yes,35,37 2006.257.21:34:16.37/va/05,04,usb,yes,32,32 2006.257.21:34:16.37/va/06,04,usb,yes,35,35 2006.257.21:34:16.37/va/07,04,usb,yes,36,36 2006.257.21:34:16.37/va/08,04,usb,yes,30,37 2006.257.21:34:16.60/valo/01,524.99,yes,locked 2006.257.21:34:16.60/valo/02,534.99,yes,locked 2006.257.21:34:16.60/valo/03,564.99,yes,locked 2006.257.21:34:16.60/valo/04,624.99,yes,locked 2006.257.21:34:16.60/valo/05,734.99,yes,locked 2006.257.21:34:16.60/valo/06,814.99,yes,locked 2006.257.21:34:16.60/valo/07,864.99,yes,locked 2006.257.21:34:16.60/valo/08,884.99,yes,locked 2006.257.21:34:17.69/vb/01,04,usb,yes,30,28 2006.257.21:34:17.69/vb/02,05,usb,yes,29,29 2006.257.21:34:17.69/vb/03,04,usb,yes,30,33 2006.257.21:34:17.69/vb/04,05,usb,yes,30,29 2006.257.21:34:17.69/vb/05,04,usb,yes,26,29 2006.257.21:34:17.69/vb/06,04,usb,yes,31,27 2006.257.21:34:17.69/vb/07,04,usb,yes,31,30 2006.257.21:34:17.69/vb/08,04,usb,yes,28,31 2006.257.21:34:17.92/vblo/01,629.99,yes,locked 2006.257.21:34:17.92/vblo/02,634.99,yes,locked 2006.257.21:34:17.92/vblo/03,649.99,yes,locked 2006.257.21:34:17.92/vblo/04,679.99,yes,locked 2006.257.21:34:17.92/vblo/05,709.99,yes,locked 2006.257.21:34:17.92/vblo/06,719.99,yes,locked 2006.257.21:34:17.92/vblo/07,734.99,yes,locked 2006.257.21:34:17.92/vblo/08,744.99,yes,locked 2006.257.21:34:18.07/vabw/8 2006.257.21:34:18.22/vbbw/8 2006.257.21:34:18.31/xfe/off,on,15.2 2006.257.21:34:18.69/ifatt/23,28,28,28 2006.257.21:34:19.08/fmout-gps/S +4.57E-07 2006.257.21:34:19.11:!2006.257.21:35:04 2006.257.21:35:04.00:data_valid=off 2006.257.21:35:04.00:"et 2006.257.21:35:04.00:!+3s 2006.257.21:35:07.01:"tape 2006.257.21:35:07.01:postob 2006.257.21:35:07.16/cable/+6.4830E-03 2006.257.21:35:07.16/wx/17.86,1015.4,95 2006.257.21:35:08.07/fmout-gps/S +4.57E-07 2006.257.21:35:08.07:scan_name=257-2137,jd0609,120 2006.257.21:35:08.07:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.257.21:35:09.13#flagr#flagr/antenna,new-source 2006.257.21:35:09.13:checkk5 2006.257.21:35:09.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.21:35:09.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.21:35:10.15/chk_autoobs//k5ts3/ autoobs is running! 2006.257.21:35:10.49/chk_autoobs//k5ts4/ autoobs is running! 2006.257.21:35:10.82/chk_obsdata//k5ts1/T2572134??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.21:35:11.15/chk_obsdata//k5ts2/T2572134??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.21:35:11.48/chk_obsdata//k5ts3/T2572134??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.21:35:11.81/chk_obsdata//k5ts4/T2572134??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.21:35:12.49/k5log//k5ts1_log_newline 2006.257.21:35:13.14/k5log//k5ts2_log_newline 2006.257.21:35:13.80/k5log//k5ts3_log_newline 2006.257.21:35:14.45/k5log//k5ts4_log_newline 2006.257.21:35:14.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.21:35:14.48:setupk4=1 2006.257.21:35:14.48$setupk4/echo=on 2006.257.21:35:14.48$setupk4/pcalon 2006.257.21:35:14.48$pcalon/"no phase cal control is implemented here 2006.257.21:35:14.48$setupk4/"tpicd=stop 2006.257.21:35:14.48$setupk4/"rec=synch_on 2006.257.21:35:14.48$setupk4/"rec_mode=128 2006.257.21:35:14.48$setupk4/!* 2006.257.21:35:14.48$setupk4/recpk4 2006.257.21:35:14.48$recpk4/recpatch= 2006.257.21:35:14.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.21:35:14.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.21:35:14.48$setupk4/vck44 2006.257.21:35:14.48$vck44/valo=1,524.99 2006.257.21:35:14.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.21:35:14.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.21:35:14.48#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:14.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:14.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:14.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:14.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:35:14.49#ibcon#first serial, iclass 4, count 0 2006.257.21:35:14.49#ibcon#enter sib2, iclass 4, count 0 2006.257.21:35:14.49#ibcon#flushed, iclass 4, count 0 2006.257.21:35:14.49#ibcon#about to write, iclass 4, count 0 2006.257.21:35:14.49#ibcon#wrote, iclass 4, count 0 2006.257.21:35:14.49#ibcon#about to read 3, iclass 4, count 0 2006.257.21:35:14.50#ibcon#read 3, iclass 4, count 0 2006.257.21:35:14.50#ibcon#about to read 4, iclass 4, count 0 2006.257.21:35:14.50#ibcon#read 4, iclass 4, count 0 2006.257.21:35:14.50#ibcon#about to read 5, iclass 4, count 0 2006.257.21:35:14.50#ibcon#read 5, iclass 4, count 0 2006.257.21:35:14.50#ibcon#about to read 6, iclass 4, count 0 2006.257.21:35:14.50#ibcon#read 6, iclass 4, count 0 2006.257.21:35:14.50#ibcon#end of sib2, iclass 4, count 0 2006.257.21:35:14.50#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:35:14.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:35:14.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.21:35:14.50#ibcon#*before write, iclass 4, count 0 2006.257.21:35:14.50#ibcon#enter sib2, iclass 4, count 0 2006.257.21:35:14.50#ibcon#flushed, iclass 4, count 0 2006.257.21:35:14.50#ibcon#about to write, iclass 4, count 0 2006.257.21:35:14.50#ibcon#wrote, iclass 4, count 0 2006.257.21:35:14.50#ibcon#about to read 3, iclass 4, count 0 2006.257.21:35:14.55#ibcon#read 3, iclass 4, count 0 2006.257.21:35:14.55#ibcon#about to read 4, iclass 4, count 0 2006.257.21:35:14.55#ibcon#read 4, iclass 4, count 0 2006.257.21:35:14.55#ibcon#about to read 5, iclass 4, count 0 2006.257.21:35:14.55#ibcon#read 5, iclass 4, count 0 2006.257.21:35:14.55#ibcon#about to read 6, iclass 4, count 0 2006.257.21:35:14.55#ibcon#read 6, iclass 4, count 0 2006.257.21:35:14.55#ibcon#end of sib2, iclass 4, count 0 2006.257.21:35:14.55#ibcon#*after write, iclass 4, count 0 2006.257.21:35:14.55#ibcon#*before return 0, iclass 4, count 0 2006.257.21:35:14.55#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:14.55#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:14.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:35:14.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:35:14.55$vck44/va=1,8 2006.257.21:35:14.55#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.21:35:14.55#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.21:35:14.55#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:14.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:14.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:14.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:14.55#ibcon#enter wrdev, iclass 6, count 2 2006.257.21:35:14.55#ibcon#first serial, iclass 6, count 2 2006.257.21:35:14.55#ibcon#enter sib2, iclass 6, count 2 2006.257.21:35:14.55#ibcon#flushed, iclass 6, count 2 2006.257.21:35:14.55#ibcon#about to write, iclass 6, count 2 2006.257.21:35:14.55#ibcon#wrote, iclass 6, count 2 2006.257.21:35:14.55#ibcon#about to read 3, iclass 6, count 2 2006.257.21:35:14.57#ibcon#read 3, iclass 6, count 2 2006.257.21:35:14.57#ibcon#about to read 4, iclass 6, count 2 2006.257.21:35:14.57#ibcon#read 4, iclass 6, count 2 2006.257.21:35:14.57#ibcon#about to read 5, iclass 6, count 2 2006.257.21:35:14.57#ibcon#read 5, iclass 6, count 2 2006.257.21:35:14.57#ibcon#about to read 6, iclass 6, count 2 2006.257.21:35:14.57#ibcon#read 6, iclass 6, count 2 2006.257.21:35:14.57#ibcon#end of sib2, iclass 6, count 2 2006.257.21:35:14.57#ibcon#*mode == 0, iclass 6, count 2 2006.257.21:35:14.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.21:35:14.57#ibcon#[25=AT01-08\r\n] 2006.257.21:35:14.57#ibcon#*before write, iclass 6, count 2 2006.257.21:35:14.57#ibcon#enter sib2, iclass 6, count 2 2006.257.21:35:14.57#ibcon#flushed, iclass 6, count 2 2006.257.21:35:14.57#ibcon#about to write, iclass 6, count 2 2006.257.21:35:14.57#ibcon#wrote, iclass 6, count 2 2006.257.21:35:14.57#ibcon#about to read 3, iclass 6, count 2 2006.257.21:35:14.60#ibcon#read 3, iclass 6, count 2 2006.257.21:35:14.60#ibcon#about to read 4, iclass 6, count 2 2006.257.21:35:14.60#ibcon#read 4, iclass 6, count 2 2006.257.21:35:14.60#ibcon#about to read 5, iclass 6, count 2 2006.257.21:35:14.60#ibcon#read 5, iclass 6, count 2 2006.257.21:35:14.60#ibcon#about to read 6, iclass 6, count 2 2006.257.21:35:14.60#ibcon#read 6, iclass 6, count 2 2006.257.21:35:14.60#ibcon#end of sib2, iclass 6, count 2 2006.257.21:35:14.60#ibcon#*after write, iclass 6, count 2 2006.257.21:35:14.60#ibcon#*before return 0, iclass 6, count 2 2006.257.21:35:14.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:14.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:14.60#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.21:35:14.60#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:14.60#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:14.72#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:14.72#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:14.72#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:35:14.72#ibcon#first serial, iclass 6, count 0 2006.257.21:35:14.72#ibcon#enter sib2, iclass 6, count 0 2006.257.21:35:14.72#ibcon#flushed, iclass 6, count 0 2006.257.21:35:14.72#ibcon#about to write, iclass 6, count 0 2006.257.21:35:14.72#ibcon#wrote, iclass 6, count 0 2006.257.21:35:14.72#ibcon#about to read 3, iclass 6, count 0 2006.257.21:35:14.74#ibcon#read 3, iclass 6, count 0 2006.257.21:35:14.74#ibcon#about to read 4, iclass 6, count 0 2006.257.21:35:14.74#ibcon#read 4, iclass 6, count 0 2006.257.21:35:14.74#ibcon#about to read 5, iclass 6, count 0 2006.257.21:35:14.74#ibcon#read 5, iclass 6, count 0 2006.257.21:35:14.74#ibcon#about to read 6, iclass 6, count 0 2006.257.21:35:14.74#ibcon#read 6, iclass 6, count 0 2006.257.21:35:14.74#ibcon#end of sib2, iclass 6, count 0 2006.257.21:35:14.74#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:35:14.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:35:14.74#ibcon#[25=USB\r\n] 2006.257.21:35:14.74#ibcon#*before write, iclass 6, count 0 2006.257.21:35:14.74#ibcon#enter sib2, iclass 6, count 0 2006.257.21:35:14.74#ibcon#flushed, iclass 6, count 0 2006.257.21:35:14.74#ibcon#about to write, iclass 6, count 0 2006.257.21:35:14.74#ibcon#wrote, iclass 6, count 0 2006.257.21:35:14.74#ibcon#about to read 3, iclass 6, count 0 2006.257.21:35:14.77#ibcon#read 3, iclass 6, count 0 2006.257.21:35:14.77#ibcon#about to read 4, iclass 6, count 0 2006.257.21:35:14.77#ibcon#read 4, iclass 6, count 0 2006.257.21:35:14.77#ibcon#about to read 5, iclass 6, count 0 2006.257.21:35:14.77#ibcon#read 5, iclass 6, count 0 2006.257.21:35:14.77#ibcon#about to read 6, iclass 6, count 0 2006.257.21:35:14.77#ibcon#read 6, iclass 6, count 0 2006.257.21:35:14.77#ibcon#end of sib2, iclass 6, count 0 2006.257.21:35:14.77#ibcon#*after write, iclass 6, count 0 2006.257.21:35:14.77#ibcon#*before return 0, iclass 6, count 0 2006.257.21:35:14.77#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:14.77#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:14.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:35:14.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:35:14.77$vck44/valo=2,534.99 2006.257.21:35:14.77#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.21:35:14.77#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.21:35:14.77#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:14.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:14.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:14.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:14.77#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:35:14.77#ibcon#first serial, iclass 10, count 0 2006.257.21:35:14.77#ibcon#enter sib2, iclass 10, count 0 2006.257.21:35:14.77#ibcon#flushed, iclass 10, count 0 2006.257.21:35:14.77#ibcon#about to write, iclass 10, count 0 2006.257.21:35:14.77#ibcon#wrote, iclass 10, count 0 2006.257.21:35:14.77#ibcon#about to read 3, iclass 10, count 0 2006.257.21:35:14.79#ibcon#read 3, iclass 10, count 0 2006.257.21:35:14.79#ibcon#about to read 4, iclass 10, count 0 2006.257.21:35:14.79#ibcon#read 4, iclass 10, count 0 2006.257.21:35:14.79#ibcon#about to read 5, iclass 10, count 0 2006.257.21:35:14.79#ibcon#read 5, iclass 10, count 0 2006.257.21:35:14.79#ibcon#about to read 6, iclass 10, count 0 2006.257.21:35:14.79#ibcon#read 6, iclass 10, count 0 2006.257.21:35:14.79#ibcon#end of sib2, iclass 10, count 0 2006.257.21:35:14.79#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:35:14.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:35:14.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.21:35:14.79#ibcon#*before write, iclass 10, count 0 2006.257.21:35:14.79#ibcon#enter sib2, iclass 10, count 0 2006.257.21:35:14.79#ibcon#flushed, iclass 10, count 0 2006.257.21:35:14.79#ibcon#about to write, iclass 10, count 0 2006.257.21:35:14.79#ibcon#wrote, iclass 10, count 0 2006.257.21:35:14.79#ibcon#about to read 3, iclass 10, count 0 2006.257.21:35:14.83#ibcon#read 3, iclass 10, count 0 2006.257.21:35:14.83#ibcon#about to read 4, iclass 10, count 0 2006.257.21:35:14.83#ibcon#read 4, iclass 10, count 0 2006.257.21:35:14.83#ibcon#about to read 5, iclass 10, count 0 2006.257.21:35:14.83#ibcon#read 5, iclass 10, count 0 2006.257.21:35:14.83#ibcon#about to read 6, iclass 10, count 0 2006.257.21:35:14.83#ibcon#read 6, iclass 10, count 0 2006.257.21:35:14.83#ibcon#end of sib2, iclass 10, count 0 2006.257.21:35:14.83#ibcon#*after write, iclass 10, count 0 2006.257.21:35:14.83#ibcon#*before return 0, iclass 10, count 0 2006.257.21:35:14.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:14.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:14.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:35:14.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:35:14.83$vck44/va=2,7 2006.257.21:35:14.83#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.21:35:14.83#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.21:35:14.83#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:14.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:14.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:14.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:14.89#ibcon#enter wrdev, iclass 12, count 2 2006.257.21:35:14.89#ibcon#first serial, iclass 12, count 2 2006.257.21:35:14.89#ibcon#enter sib2, iclass 12, count 2 2006.257.21:35:14.89#ibcon#flushed, iclass 12, count 2 2006.257.21:35:14.89#ibcon#about to write, iclass 12, count 2 2006.257.21:35:14.89#ibcon#wrote, iclass 12, count 2 2006.257.21:35:14.89#ibcon#about to read 3, iclass 12, count 2 2006.257.21:35:14.91#ibcon#read 3, iclass 12, count 2 2006.257.21:35:14.91#ibcon#about to read 4, iclass 12, count 2 2006.257.21:35:14.91#ibcon#read 4, iclass 12, count 2 2006.257.21:35:14.91#ibcon#about to read 5, iclass 12, count 2 2006.257.21:35:14.91#ibcon#read 5, iclass 12, count 2 2006.257.21:35:14.91#ibcon#about to read 6, iclass 12, count 2 2006.257.21:35:14.91#ibcon#read 6, iclass 12, count 2 2006.257.21:35:14.91#ibcon#end of sib2, iclass 12, count 2 2006.257.21:35:14.91#ibcon#*mode == 0, iclass 12, count 2 2006.257.21:35:14.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.21:35:14.91#ibcon#[25=AT02-07\r\n] 2006.257.21:35:14.91#ibcon#*before write, iclass 12, count 2 2006.257.21:35:14.91#ibcon#enter sib2, iclass 12, count 2 2006.257.21:35:14.91#ibcon#flushed, iclass 12, count 2 2006.257.21:35:14.91#ibcon#about to write, iclass 12, count 2 2006.257.21:35:14.91#ibcon#wrote, iclass 12, count 2 2006.257.21:35:14.91#ibcon#about to read 3, iclass 12, count 2 2006.257.21:35:14.94#ibcon#read 3, iclass 12, count 2 2006.257.21:35:14.94#ibcon#about to read 4, iclass 12, count 2 2006.257.21:35:14.94#ibcon#read 4, iclass 12, count 2 2006.257.21:35:14.94#ibcon#about to read 5, iclass 12, count 2 2006.257.21:35:14.94#ibcon#read 5, iclass 12, count 2 2006.257.21:35:14.94#ibcon#about to read 6, iclass 12, count 2 2006.257.21:35:14.94#ibcon#read 6, iclass 12, count 2 2006.257.21:35:14.94#ibcon#end of sib2, iclass 12, count 2 2006.257.21:35:14.94#ibcon#*after write, iclass 12, count 2 2006.257.21:35:14.94#ibcon#*before return 0, iclass 12, count 2 2006.257.21:35:14.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:14.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:14.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.21:35:14.94#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:14.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:15.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:15.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:15.06#ibcon#enter wrdev, iclass 12, count 0 2006.257.21:35:15.06#ibcon#first serial, iclass 12, count 0 2006.257.21:35:15.06#ibcon#enter sib2, iclass 12, count 0 2006.257.21:35:15.06#ibcon#flushed, iclass 12, count 0 2006.257.21:35:15.06#ibcon#about to write, iclass 12, count 0 2006.257.21:35:15.06#ibcon#wrote, iclass 12, count 0 2006.257.21:35:15.06#ibcon#about to read 3, iclass 12, count 0 2006.257.21:35:15.08#ibcon#read 3, iclass 12, count 0 2006.257.21:35:15.08#ibcon#about to read 4, iclass 12, count 0 2006.257.21:35:15.08#ibcon#read 4, iclass 12, count 0 2006.257.21:35:15.08#ibcon#about to read 5, iclass 12, count 0 2006.257.21:35:15.08#ibcon#read 5, iclass 12, count 0 2006.257.21:35:15.08#ibcon#about to read 6, iclass 12, count 0 2006.257.21:35:15.08#ibcon#read 6, iclass 12, count 0 2006.257.21:35:15.08#ibcon#end of sib2, iclass 12, count 0 2006.257.21:35:15.08#ibcon#*mode == 0, iclass 12, count 0 2006.257.21:35:15.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.21:35:15.08#ibcon#[25=USB\r\n] 2006.257.21:35:15.08#ibcon#*before write, iclass 12, count 0 2006.257.21:35:15.08#ibcon#enter sib2, iclass 12, count 0 2006.257.21:35:15.08#ibcon#flushed, iclass 12, count 0 2006.257.21:35:15.08#ibcon#about to write, iclass 12, count 0 2006.257.21:35:15.08#ibcon#wrote, iclass 12, count 0 2006.257.21:35:15.08#ibcon#about to read 3, iclass 12, count 0 2006.257.21:35:15.11#ibcon#read 3, iclass 12, count 0 2006.257.21:35:15.11#ibcon#about to read 4, iclass 12, count 0 2006.257.21:35:15.11#ibcon#read 4, iclass 12, count 0 2006.257.21:35:15.11#ibcon#about to read 5, iclass 12, count 0 2006.257.21:35:15.11#ibcon#read 5, iclass 12, count 0 2006.257.21:35:15.11#ibcon#about to read 6, iclass 12, count 0 2006.257.21:35:15.11#ibcon#read 6, iclass 12, count 0 2006.257.21:35:15.11#ibcon#end of sib2, iclass 12, count 0 2006.257.21:35:15.11#ibcon#*after write, iclass 12, count 0 2006.257.21:35:15.11#ibcon#*before return 0, iclass 12, count 0 2006.257.21:35:15.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:15.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:15.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.21:35:15.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.21:35:15.11$vck44/valo=3,564.99 2006.257.21:35:15.11#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.21:35:15.11#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.21:35:15.11#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:15.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:15.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:15.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:15.11#ibcon#enter wrdev, iclass 14, count 0 2006.257.21:35:15.11#ibcon#first serial, iclass 14, count 0 2006.257.21:35:15.11#ibcon#enter sib2, iclass 14, count 0 2006.257.21:35:15.11#ibcon#flushed, iclass 14, count 0 2006.257.21:35:15.11#ibcon#about to write, iclass 14, count 0 2006.257.21:35:15.11#ibcon#wrote, iclass 14, count 0 2006.257.21:35:15.11#ibcon#about to read 3, iclass 14, count 0 2006.257.21:35:15.13#ibcon#read 3, iclass 14, count 0 2006.257.21:35:15.13#ibcon#about to read 4, iclass 14, count 0 2006.257.21:35:15.13#ibcon#read 4, iclass 14, count 0 2006.257.21:35:15.13#ibcon#about to read 5, iclass 14, count 0 2006.257.21:35:15.13#ibcon#read 5, iclass 14, count 0 2006.257.21:35:15.13#ibcon#about to read 6, iclass 14, count 0 2006.257.21:35:15.13#ibcon#read 6, iclass 14, count 0 2006.257.21:35:15.13#ibcon#end of sib2, iclass 14, count 0 2006.257.21:35:15.13#ibcon#*mode == 0, iclass 14, count 0 2006.257.21:35:15.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.21:35:15.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.21:35:15.13#ibcon#*before write, iclass 14, count 0 2006.257.21:35:15.13#ibcon#enter sib2, iclass 14, count 0 2006.257.21:35:15.13#ibcon#flushed, iclass 14, count 0 2006.257.21:35:15.13#ibcon#about to write, iclass 14, count 0 2006.257.21:35:15.13#ibcon#wrote, iclass 14, count 0 2006.257.21:35:15.13#ibcon#about to read 3, iclass 14, count 0 2006.257.21:35:15.17#ibcon#read 3, iclass 14, count 0 2006.257.21:35:15.17#ibcon#about to read 4, iclass 14, count 0 2006.257.21:35:15.17#ibcon#read 4, iclass 14, count 0 2006.257.21:35:15.17#ibcon#about to read 5, iclass 14, count 0 2006.257.21:35:15.17#ibcon#read 5, iclass 14, count 0 2006.257.21:35:15.17#ibcon#about to read 6, iclass 14, count 0 2006.257.21:35:15.17#ibcon#read 6, iclass 14, count 0 2006.257.21:35:15.17#ibcon#end of sib2, iclass 14, count 0 2006.257.21:35:15.17#ibcon#*after write, iclass 14, count 0 2006.257.21:35:15.17#ibcon#*before return 0, iclass 14, count 0 2006.257.21:35:15.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:15.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:15.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.21:35:15.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.21:35:15.17$vck44/va=3,8 2006.257.21:35:15.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.21:35:15.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.21:35:15.17#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:15.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:15.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:15.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:15.23#ibcon#enter wrdev, iclass 16, count 2 2006.257.21:35:15.23#ibcon#first serial, iclass 16, count 2 2006.257.21:35:15.23#ibcon#enter sib2, iclass 16, count 2 2006.257.21:35:15.23#ibcon#flushed, iclass 16, count 2 2006.257.21:35:15.23#ibcon#about to write, iclass 16, count 2 2006.257.21:35:15.23#ibcon#wrote, iclass 16, count 2 2006.257.21:35:15.23#ibcon#about to read 3, iclass 16, count 2 2006.257.21:35:15.25#ibcon#read 3, iclass 16, count 2 2006.257.21:35:15.25#ibcon#about to read 4, iclass 16, count 2 2006.257.21:35:15.25#ibcon#read 4, iclass 16, count 2 2006.257.21:35:15.25#ibcon#about to read 5, iclass 16, count 2 2006.257.21:35:15.25#ibcon#read 5, iclass 16, count 2 2006.257.21:35:15.25#ibcon#about to read 6, iclass 16, count 2 2006.257.21:35:15.25#ibcon#read 6, iclass 16, count 2 2006.257.21:35:15.25#ibcon#end of sib2, iclass 16, count 2 2006.257.21:35:15.25#ibcon#*mode == 0, iclass 16, count 2 2006.257.21:35:15.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.21:35:15.25#ibcon#[25=AT03-08\r\n] 2006.257.21:35:15.25#ibcon#*before write, iclass 16, count 2 2006.257.21:35:15.25#ibcon#enter sib2, iclass 16, count 2 2006.257.21:35:15.25#ibcon#flushed, iclass 16, count 2 2006.257.21:35:15.25#ibcon#about to write, iclass 16, count 2 2006.257.21:35:15.25#ibcon#wrote, iclass 16, count 2 2006.257.21:35:15.25#ibcon#about to read 3, iclass 16, count 2 2006.257.21:35:15.28#ibcon#read 3, iclass 16, count 2 2006.257.21:35:15.28#ibcon#about to read 4, iclass 16, count 2 2006.257.21:35:15.28#ibcon#read 4, iclass 16, count 2 2006.257.21:35:15.28#ibcon#about to read 5, iclass 16, count 2 2006.257.21:35:15.28#ibcon#read 5, iclass 16, count 2 2006.257.21:35:15.28#ibcon#about to read 6, iclass 16, count 2 2006.257.21:35:15.28#ibcon#read 6, iclass 16, count 2 2006.257.21:35:15.28#ibcon#end of sib2, iclass 16, count 2 2006.257.21:35:15.28#ibcon#*after write, iclass 16, count 2 2006.257.21:35:15.28#ibcon#*before return 0, iclass 16, count 2 2006.257.21:35:15.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:15.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:15.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.21:35:15.28#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:15.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:15.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:15.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:15.40#ibcon#enter wrdev, iclass 16, count 0 2006.257.21:35:15.40#ibcon#first serial, iclass 16, count 0 2006.257.21:35:15.40#ibcon#enter sib2, iclass 16, count 0 2006.257.21:35:15.40#ibcon#flushed, iclass 16, count 0 2006.257.21:35:15.40#ibcon#about to write, iclass 16, count 0 2006.257.21:35:15.40#ibcon#wrote, iclass 16, count 0 2006.257.21:35:15.40#ibcon#about to read 3, iclass 16, count 0 2006.257.21:35:15.42#ibcon#read 3, iclass 16, count 0 2006.257.21:35:15.42#ibcon#about to read 4, iclass 16, count 0 2006.257.21:35:15.42#ibcon#read 4, iclass 16, count 0 2006.257.21:35:15.42#ibcon#about to read 5, iclass 16, count 0 2006.257.21:35:15.42#ibcon#read 5, iclass 16, count 0 2006.257.21:35:15.42#ibcon#about to read 6, iclass 16, count 0 2006.257.21:35:15.42#ibcon#read 6, iclass 16, count 0 2006.257.21:35:15.42#ibcon#end of sib2, iclass 16, count 0 2006.257.21:35:15.42#ibcon#*mode == 0, iclass 16, count 0 2006.257.21:35:15.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.21:35:15.42#ibcon#[25=USB\r\n] 2006.257.21:35:15.42#ibcon#*before write, iclass 16, count 0 2006.257.21:35:15.42#ibcon#enter sib2, iclass 16, count 0 2006.257.21:35:15.42#ibcon#flushed, iclass 16, count 0 2006.257.21:35:15.42#ibcon#about to write, iclass 16, count 0 2006.257.21:35:15.42#ibcon#wrote, iclass 16, count 0 2006.257.21:35:15.42#ibcon#about to read 3, iclass 16, count 0 2006.257.21:35:15.45#ibcon#read 3, iclass 16, count 0 2006.257.21:35:15.45#ibcon#about to read 4, iclass 16, count 0 2006.257.21:35:15.45#ibcon#read 4, iclass 16, count 0 2006.257.21:35:15.45#ibcon#about to read 5, iclass 16, count 0 2006.257.21:35:15.45#ibcon#read 5, iclass 16, count 0 2006.257.21:35:15.45#ibcon#about to read 6, iclass 16, count 0 2006.257.21:35:15.45#ibcon#read 6, iclass 16, count 0 2006.257.21:35:15.45#ibcon#end of sib2, iclass 16, count 0 2006.257.21:35:15.45#ibcon#*after write, iclass 16, count 0 2006.257.21:35:15.45#ibcon#*before return 0, iclass 16, count 0 2006.257.21:35:15.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:15.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:15.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.21:35:15.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.21:35:15.45$vck44/valo=4,624.99 2006.257.21:35:15.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.21:35:15.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.21:35:15.45#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:15.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:15.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:15.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:15.45#ibcon#enter wrdev, iclass 18, count 0 2006.257.21:35:15.45#ibcon#first serial, iclass 18, count 0 2006.257.21:35:15.45#ibcon#enter sib2, iclass 18, count 0 2006.257.21:35:15.45#ibcon#flushed, iclass 18, count 0 2006.257.21:35:15.45#ibcon#about to write, iclass 18, count 0 2006.257.21:35:15.45#ibcon#wrote, iclass 18, count 0 2006.257.21:35:15.45#ibcon#about to read 3, iclass 18, count 0 2006.257.21:35:15.47#ibcon#read 3, iclass 18, count 0 2006.257.21:35:15.47#ibcon#about to read 4, iclass 18, count 0 2006.257.21:35:15.47#ibcon#read 4, iclass 18, count 0 2006.257.21:35:15.47#ibcon#about to read 5, iclass 18, count 0 2006.257.21:35:15.47#ibcon#read 5, iclass 18, count 0 2006.257.21:35:15.47#ibcon#about to read 6, iclass 18, count 0 2006.257.21:35:15.47#ibcon#read 6, iclass 18, count 0 2006.257.21:35:15.47#ibcon#end of sib2, iclass 18, count 0 2006.257.21:35:15.47#ibcon#*mode == 0, iclass 18, count 0 2006.257.21:35:15.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.21:35:15.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.21:35:15.47#ibcon#*before write, iclass 18, count 0 2006.257.21:35:15.47#ibcon#enter sib2, iclass 18, count 0 2006.257.21:35:15.47#ibcon#flushed, iclass 18, count 0 2006.257.21:35:15.47#ibcon#about to write, iclass 18, count 0 2006.257.21:35:15.47#ibcon#wrote, iclass 18, count 0 2006.257.21:35:15.47#ibcon#about to read 3, iclass 18, count 0 2006.257.21:35:15.51#ibcon#read 3, iclass 18, count 0 2006.257.21:35:15.51#ibcon#about to read 4, iclass 18, count 0 2006.257.21:35:15.51#ibcon#read 4, iclass 18, count 0 2006.257.21:35:15.51#ibcon#about to read 5, iclass 18, count 0 2006.257.21:35:15.51#ibcon#read 5, iclass 18, count 0 2006.257.21:35:15.51#ibcon#about to read 6, iclass 18, count 0 2006.257.21:35:15.51#ibcon#read 6, iclass 18, count 0 2006.257.21:35:15.51#ibcon#end of sib2, iclass 18, count 0 2006.257.21:35:15.51#ibcon#*after write, iclass 18, count 0 2006.257.21:35:15.51#ibcon#*before return 0, iclass 18, count 0 2006.257.21:35:15.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:15.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:15.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.21:35:15.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.21:35:15.51$vck44/va=4,7 2006.257.21:35:15.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.21:35:15.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.21:35:15.51#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:15.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:15.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:15.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:15.57#ibcon#enter wrdev, iclass 20, count 2 2006.257.21:35:15.57#ibcon#first serial, iclass 20, count 2 2006.257.21:35:15.57#ibcon#enter sib2, iclass 20, count 2 2006.257.21:35:15.57#ibcon#flushed, iclass 20, count 2 2006.257.21:35:15.57#ibcon#about to write, iclass 20, count 2 2006.257.21:35:15.57#ibcon#wrote, iclass 20, count 2 2006.257.21:35:15.57#ibcon#about to read 3, iclass 20, count 2 2006.257.21:35:15.59#ibcon#read 3, iclass 20, count 2 2006.257.21:35:15.59#ibcon#about to read 4, iclass 20, count 2 2006.257.21:35:15.59#ibcon#read 4, iclass 20, count 2 2006.257.21:35:15.59#ibcon#about to read 5, iclass 20, count 2 2006.257.21:35:15.59#ibcon#read 5, iclass 20, count 2 2006.257.21:35:15.59#ibcon#about to read 6, iclass 20, count 2 2006.257.21:35:15.59#ibcon#read 6, iclass 20, count 2 2006.257.21:35:15.59#ibcon#end of sib2, iclass 20, count 2 2006.257.21:35:15.59#ibcon#*mode == 0, iclass 20, count 2 2006.257.21:35:15.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.21:35:15.59#ibcon#[25=AT04-07\r\n] 2006.257.21:35:15.59#ibcon#*before write, iclass 20, count 2 2006.257.21:35:15.59#ibcon#enter sib2, iclass 20, count 2 2006.257.21:35:15.59#ibcon#flushed, iclass 20, count 2 2006.257.21:35:15.59#ibcon#about to write, iclass 20, count 2 2006.257.21:35:15.59#ibcon#wrote, iclass 20, count 2 2006.257.21:35:15.59#ibcon#about to read 3, iclass 20, count 2 2006.257.21:35:15.62#ibcon#read 3, iclass 20, count 2 2006.257.21:35:15.62#ibcon#about to read 4, iclass 20, count 2 2006.257.21:35:15.62#ibcon#read 4, iclass 20, count 2 2006.257.21:35:15.62#ibcon#about to read 5, iclass 20, count 2 2006.257.21:35:15.62#ibcon#read 5, iclass 20, count 2 2006.257.21:35:15.62#ibcon#about to read 6, iclass 20, count 2 2006.257.21:35:15.62#ibcon#read 6, iclass 20, count 2 2006.257.21:35:15.62#ibcon#end of sib2, iclass 20, count 2 2006.257.21:35:15.62#ibcon#*after write, iclass 20, count 2 2006.257.21:35:15.62#ibcon#*before return 0, iclass 20, count 2 2006.257.21:35:15.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:15.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:15.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.21:35:15.62#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:15.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:15.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:15.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:15.74#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:35:15.74#ibcon#first serial, iclass 20, count 0 2006.257.21:35:15.74#ibcon#enter sib2, iclass 20, count 0 2006.257.21:35:15.74#ibcon#flushed, iclass 20, count 0 2006.257.21:35:15.74#ibcon#about to write, iclass 20, count 0 2006.257.21:35:15.74#ibcon#wrote, iclass 20, count 0 2006.257.21:35:15.74#ibcon#about to read 3, iclass 20, count 0 2006.257.21:35:15.76#ibcon#read 3, iclass 20, count 0 2006.257.21:35:15.76#ibcon#about to read 4, iclass 20, count 0 2006.257.21:35:15.76#ibcon#read 4, iclass 20, count 0 2006.257.21:35:15.76#ibcon#about to read 5, iclass 20, count 0 2006.257.21:35:15.76#ibcon#read 5, iclass 20, count 0 2006.257.21:35:15.76#ibcon#about to read 6, iclass 20, count 0 2006.257.21:35:15.76#ibcon#read 6, iclass 20, count 0 2006.257.21:35:15.76#ibcon#end of sib2, iclass 20, count 0 2006.257.21:35:15.76#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:35:15.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:35:15.76#ibcon#[25=USB\r\n] 2006.257.21:35:15.76#ibcon#*before write, iclass 20, count 0 2006.257.21:35:15.76#ibcon#enter sib2, iclass 20, count 0 2006.257.21:35:15.76#ibcon#flushed, iclass 20, count 0 2006.257.21:35:15.76#ibcon#about to write, iclass 20, count 0 2006.257.21:35:15.76#ibcon#wrote, iclass 20, count 0 2006.257.21:35:15.76#ibcon#about to read 3, iclass 20, count 0 2006.257.21:35:15.79#ibcon#read 3, iclass 20, count 0 2006.257.21:35:15.79#ibcon#about to read 4, iclass 20, count 0 2006.257.21:35:15.79#ibcon#read 4, iclass 20, count 0 2006.257.21:35:15.79#ibcon#about to read 5, iclass 20, count 0 2006.257.21:35:15.79#ibcon#read 5, iclass 20, count 0 2006.257.21:35:15.79#ibcon#about to read 6, iclass 20, count 0 2006.257.21:35:15.79#ibcon#read 6, iclass 20, count 0 2006.257.21:35:15.79#ibcon#end of sib2, iclass 20, count 0 2006.257.21:35:15.79#ibcon#*after write, iclass 20, count 0 2006.257.21:35:15.79#ibcon#*before return 0, iclass 20, count 0 2006.257.21:35:15.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:15.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:15.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:35:15.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:35:15.79$vck44/valo=5,734.99 2006.257.21:35:15.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.21:35:15.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.21:35:15.79#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:15.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:15.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:15.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:15.79#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:35:15.79#ibcon#first serial, iclass 22, count 0 2006.257.21:35:15.79#ibcon#enter sib2, iclass 22, count 0 2006.257.21:35:15.79#ibcon#flushed, iclass 22, count 0 2006.257.21:35:15.79#ibcon#about to write, iclass 22, count 0 2006.257.21:35:15.79#ibcon#wrote, iclass 22, count 0 2006.257.21:35:15.79#ibcon#about to read 3, iclass 22, count 0 2006.257.21:35:15.81#ibcon#read 3, iclass 22, count 0 2006.257.21:35:15.81#ibcon#about to read 4, iclass 22, count 0 2006.257.21:35:15.81#ibcon#read 4, iclass 22, count 0 2006.257.21:35:15.81#ibcon#about to read 5, iclass 22, count 0 2006.257.21:35:15.81#ibcon#read 5, iclass 22, count 0 2006.257.21:35:15.81#ibcon#about to read 6, iclass 22, count 0 2006.257.21:35:15.81#ibcon#read 6, iclass 22, count 0 2006.257.21:35:15.81#ibcon#end of sib2, iclass 22, count 0 2006.257.21:35:15.81#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:35:15.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:35:15.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.21:35:15.81#ibcon#*before write, iclass 22, count 0 2006.257.21:35:15.81#ibcon#enter sib2, iclass 22, count 0 2006.257.21:35:15.81#ibcon#flushed, iclass 22, count 0 2006.257.21:35:15.81#ibcon#about to write, iclass 22, count 0 2006.257.21:35:15.81#ibcon#wrote, iclass 22, count 0 2006.257.21:35:15.81#ibcon#about to read 3, iclass 22, count 0 2006.257.21:35:15.85#ibcon#read 3, iclass 22, count 0 2006.257.21:35:15.85#ibcon#about to read 4, iclass 22, count 0 2006.257.21:35:15.85#ibcon#read 4, iclass 22, count 0 2006.257.21:35:15.85#ibcon#about to read 5, iclass 22, count 0 2006.257.21:35:15.85#ibcon#read 5, iclass 22, count 0 2006.257.21:35:15.85#ibcon#about to read 6, iclass 22, count 0 2006.257.21:35:15.85#ibcon#read 6, iclass 22, count 0 2006.257.21:35:15.85#ibcon#end of sib2, iclass 22, count 0 2006.257.21:35:15.85#ibcon#*after write, iclass 22, count 0 2006.257.21:35:15.85#ibcon#*before return 0, iclass 22, count 0 2006.257.21:35:15.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:15.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:15.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:35:15.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:35:15.85$vck44/va=5,4 2006.257.21:35:15.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.21:35:15.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.21:35:15.85#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:15.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:15.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:15.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:15.91#ibcon#enter wrdev, iclass 24, count 2 2006.257.21:35:15.91#ibcon#first serial, iclass 24, count 2 2006.257.21:35:15.91#ibcon#enter sib2, iclass 24, count 2 2006.257.21:35:15.91#ibcon#flushed, iclass 24, count 2 2006.257.21:35:15.91#ibcon#about to write, iclass 24, count 2 2006.257.21:35:15.91#ibcon#wrote, iclass 24, count 2 2006.257.21:35:15.91#ibcon#about to read 3, iclass 24, count 2 2006.257.21:35:15.93#ibcon#read 3, iclass 24, count 2 2006.257.21:35:15.93#ibcon#about to read 4, iclass 24, count 2 2006.257.21:35:15.93#ibcon#read 4, iclass 24, count 2 2006.257.21:35:15.93#ibcon#about to read 5, iclass 24, count 2 2006.257.21:35:15.93#ibcon#read 5, iclass 24, count 2 2006.257.21:35:15.93#ibcon#about to read 6, iclass 24, count 2 2006.257.21:35:15.93#ibcon#read 6, iclass 24, count 2 2006.257.21:35:15.93#ibcon#end of sib2, iclass 24, count 2 2006.257.21:35:15.93#ibcon#*mode == 0, iclass 24, count 2 2006.257.21:35:15.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.21:35:15.93#ibcon#[25=AT05-04\r\n] 2006.257.21:35:15.93#ibcon#*before write, iclass 24, count 2 2006.257.21:35:15.93#ibcon#enter sib2, iclass 24, count 2 2006.257.21:35:15.93#ibcon#flushed, iclass 24, count 2 2006.257.21:35:15.93#ibcon#about to write, iclass 24, count 2 2006.257.21:35:15.93#ibcon#wrote, iclass 24, count 2 2006.257.21:35:15.93#ibcon#about to read 3, iclass 24, count 2 2006.257.21:35:15.96#ibcon#read 3, iclass 24, count 2 2006.257.21:35:15.96#ibcon#about to read 4, iclass 24, count 2 2006.257.21:35:15.96#ibcon#read 4, iclass 24, count 2 2006.257.21:35:15.96#ibcon#about to read 5, iclass 24, count 2 2006.257.21:35:15.96#ibcon#read 5, iclass 24, count 2 2006.257.21:35:15.96#ibcon#about to read 6, iclass 24, count 2 2006.257.21:35:15.96#ibcon#read 6, iclass 24, count 2 2006.257.21:35:15.96#ibcon#end of sib2, iclass 24, count 2 2006.257.21:35:15.96#ibcon#*after write, iclass 24, count 2 2006.257.21:35:15.96#ibcon#*before return 0, iclass 24, count 2 2006.257.21:35:15.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:15.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:15.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.21:35:15.96#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:15.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:16.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:16.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:16.08#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:35:16.08#ibcon#first serial, iclass 24, count 0 2006.257.21:35:16.08#ibcon#enter sib2, iclass 24, count 0 2006.257.21:35:16.08#ibcon#flushed, iclass 24, count 0 2006.257.21:35:16.08#ibcon#about to write, iclass 24, count 0 2006.257.21:35:16.08#ibcon#wrote, iclass 24, count 0 2006.257.21:35:16.08#ibcon#about to read 3, iclass 24, count 0 2006.257.21:35:16.10#ibcon#read 3, iclass 24, count 0 2006.257.21:35:16.10#ibcon#about to read 4, iclass 24, count 0 2006.257.21:35:16.10#ibcon#read 4, iclass 24, count 0 2006.257.21:35:16.10#ibcon#about to read 5, iclass 24, count 0 2006.257.21:35:16.10#ibcon#read 5, iclass 24, count 0 2006.257.21:35:16.10#ibcon#about to read 6, iclass 24, count 0 2006.257.21:35:16.10#ibcon#read 6, iclass 24, count 0 2006.257.21:35:16.10#ibcon#end of sib2, iclass 24, count 0 2006.257.21:35:16.10#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:35:16.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:35:16.10#ibcon#[25=USB\r\n] 2006.257.21:35:16.10#ibcon#*before write, iclass 24, count 0 2006.257.21:35:16.10#ibcon#enter sib2, iclass 24, count 0 2006.257.21:35:16.10#ibcon#flushed, iclass 24, count 0 2006.257.21:35:16.10#ibcon#about to write, iclass 24, count 0 2006.257.21:35:16.10#ibcon#wrote, iclass 24, count 0 2006.257.21:35:16.10#ibcon#about to read 3, iclass 24, count 0 2006.257.21:35:16.13#ibcon#read 3, iclass 24, count 0 2006.257.21:35:16.13#ibcon#about to read 4, iclass 24, count 0 2006.257.21:35:16.13#ibcon#read 4, iclass 24, count 0 2006.257.21:35:16.13#ibcon#about to read 5, iclass 24, count 0 2006.257.21:35:16.13#ibcon#read 5, iclass 24, count 0 2006.257.21:35:16.13#ibcon#about to read 6, iclass 24, count 0 2006.257.21:35:16.13#ibcon#read 6, iclass 24, count 0 2006.257.21:35:16.13#ibcon#end of sib2, iclass 24, count 0 2006.257.21:35:16.13#ibcon#*after write, iclass 24, count 0 2006.257.21:35:16.13#ibcon#*before return 0, iclass 24, count 0 2006.257.21:35:16.13#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:16.13#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:16.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:35:16.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:35:16.13$vck44/valo=6,814.99 2006.257.21:35:16.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.21:35:16.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.21:35:16.13#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:16.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:16.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:16.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:16.13#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:35:16.13#ibcon#first serial, iclass 26, count 0 2006.257.21:35:16.13#ibcon#enter sib2, iclass 26, count 0 2006.257.21:35:16.13#ibcon#flushed, iclass 26, count 0 2006.257.21:35:16.13#ibcon#about to write, iclass 26, count 0 2006.257.21:35:16.13#ibcon#wrote, iclass 26, count 0 2006.257.21:35:16.13#ibcon#about to read 3, iclass 26, count 0 2006.257.21:35:16.15#ibcon#read 3, iclass 26, count 0 2006.257.21:35:16.15#ibcon#about to read 4, iclass 26, count 0 2006.257.21:35:16.15#ibcon#read 4, iclass 26, count 0 2006.257.21:35:16.15#ibcon#about to read 5, iclass 26, count 0 2006.257.21:35:16.15#ibcon#read 5, iclass 26, count 0 2006.257.21:35:16.15#ibcon#about to read 6, iclass 26, count 0 2006.257.21:35:16.15#ibcon#read 6, iclass 26, count 0 2006.257.21:35:16.15#ibcon#end of sib2, iclass 26, count 0 2006.257.21:35:16.15#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:35:16.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:35:16.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.21:35:16.15#ibcon#*before write, iclass 26, count 0 2006.257.21:35:16.15#ibcon#enter sib2, iclass 26, count 0 2006.257.21:35:16.15#ibcon#flushed, iclass 26, count 0 2006.257.21:35:16.15#ibcon#about to write, iclass 26, count 0 2006.257.21:35:16.15#ibcon#wrote, iclass 26, count 0 2006.257.21:35:16.15#ibcon#about to read 3, iclass 26, count 0 2006.257.21:35:16.19#ibcon#read 3, iclass 26, count 0 2006.257.21:35:16.19#ibcon#about to read 4, iclass 26, count 0 2006.257.21:35:16.19#ibcon#read 4, iclass 26, count 0 2006.257.21:35:16.19#ibcon#about to read 5, iclass 26, count 0 2006.257.21:35:16.19#ibcon#read 5, iclass 26, count 0 2006.257.21:35:16.19#ibcon#about to read 6, iclass 26, count 0 2006.257.21:35:16.19#ibcon#read 6, iclass 26, count 0 2006.257.21:35:16.19#ibcon#end of sib2, iclass 26, count 0 2006.257.21:35:16.19#ibcon#*after write, iclass 26, count 0 2006.257.21:35:16.19#ibcon#*before return 0, iclass 26, count 0 2006.257.21:35:16.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:16.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:16.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:35:16.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:35:16.19$vck44/va=6,4 2006.257.21:35:16.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.21:35:16.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.21:35:16.19#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:16.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:16.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:16.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:16.25#ibcon#enter wrdev, iclass 28, count 2 2006.257.21:35:16.25#ibcon#first serial, iclass 28, count 2 2006.257.21:35:16.25#ibcon#enter sib2, iclass 28, count 2 2006.257.21:35:16.25#ibcon#flushed, iclass 28, count 2 2006.257.21:35:16.25#ibcon#about to write, iclass 28, count 2 2006.257.21:35:16.25#ibcon#wrote, iclass 28, count 2 2006.257.21:35:16.25#ibcon#about to read 3, iclass 28, count 2 2006.257.21:35:16.27#ibcon#read 3, iclass 28, count 2 2006.257.21:35:16.27#ibcon#about to read 4, iclass 28, count 2 2006.257.21:35:16.27#ibcon#read 4, iclass 28, count 2 2006.257.21:35:16.27#ibcon#about to read 5, iclass 28, count 2 2006.257.21:35:16.27#ibcon#read 5, iclass 28, count 2 2006.257.21:35:16.27#ibcon#about to read 6, iclass 28, count 2 2006.257.21:35:16.27#ibcon#read 6, iclass 28, count 2 2006.257.21:35:16.27#ibcon#end of sib2, iclass 28, count 2 2006.257.21:35:16.27#ibcon#*mode == 0, iclass 28, count 2 2006.257.21:35:16.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.21:35:16.27#ibcon#[25=AT06-04\r\n] 2006.257.21:35:16.27#ibcon#*before write, iclass 28, count 2 2006.257.21:35:16.27#ibcon#enter sib2, iclass 28, count 2 2006.257.21:35:16.27#ibcon#flushed, iclass 28, count 2 2006.257.21:35:16.27#ibcon#about to write, iclass 28, count 2 2006.257.21:35:16.27#ibcon#wrote, iclass 28, count 2 2006.257.21:35:16.27#ibcon#about to read 3, iclass 28, count 2 2006.257.21:35:16.30#ibcon#read 3, iclass 28, count 2 2006.257.21:35:16.30#ibcon#about to read 4, iclass 28, count 2 2006.257.21:35:16.30#ibcon#read 4, iclass 28, count 2 2006.257.21:35:16.30#ibcon#about to read 5, iclass 28, count 2 2006.257.21:35:16.30#ibcon#read 5, iclass 28, count 2 2006.257.21:35:16.30#ibcon#about to read 6, iclass 28, count 2 2006.257.21:35:16.30#ibcon#read 6, iclass 28, count 2 2006.257.21:35:16.30#ibcon#end of sib2, iclass 28, count 2 2006.257.21:35:16.30#ibcon#*after write, iclass 28, count 2 2006.257.21:35:16.30#ibcon#*before return 0, iclass 28, count 2 2006.257.21:35:16.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:16.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:16.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.21:35:16.30#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:16.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:16.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:16.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:16.42#ibcon#enter wrdev, iclass 28, count 0 2006.257.21:35:16.42#ibcon#first serial, iclass 28, count 0 2006.257.21:35:16.42#ibcon#enter sib2, iclass 28, count 0 2006.257.21:35:16.42#ibcon#flushed, iclass 28, count 0 2006.257.21:35:16.42#ibcon#about to write, iclass 28, count 0 2006.257.21:35:16.42#ibcon#wrote, iclass 28, count 0 2006.257.21:35:16.42#ibcon#about to read 3, iclass 28, count 0 2006.257.21:35:16.44#ibcon#read 3, iclass 28, count 0 2006.257.21:35:16.44#ibcon#about to read 4, iclass 28, count 0 2006.257.21:35:16.44#ibcon#read 4, iclass 28, count 0 2006.257.21:35:16.44#ibcon#about to read 5, iclass 28, count 0 2006.257.21:35:16.44#ibcon#read 5, iclass 28, count 0 2006.257.21:35:16.44#ibcon#about to read 6, iclass 28, count 0 2006.257.21:35:16.44#ibcon#read 6, iclass 28, count 0 2006.257.21:35:16.44#ibcon#end of sib2, iclass 28, count 0 2006.257.21:35:16.44#ibcon#*mode == 0, iclass 28, count 0 2006.257.21:35:16.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.21:35:16.44#ibcon#[25=USB\r\n] 2006.257.21:35:16.44#ibcon#*before write, iclass 28, count 0 2006.257.21:35:16.44#ibcon#enter sib2, iclass 28, count 0 2006.257.21:35:16.44#ibcon#flushed, iclass 28, count 0 2006.257.21:35:16.44#ibcon#about to write, iclass 28, count 0 2006.257.21:35:16.44#ibcon#wrote, iclass 28, count 0 2006.257.21:35:16.44#ibcon#about to read 3, iclass 28, count 0 2006.257.21:35:16.47#ibcon#read 3, iclass 28, count 0 2006.257.21:35:16.47#ibcon#about to read 4, iclass 28, count 0 2006.257.21:35:16.47#ibcon#read 4, iclass 28, count 0 2006.257.21:35:16.47#ibcon#about to read 5, iclass 28, count 0 2006.257.21:35:16.47#ibcon#read 5, iclass 28, count 0 2006.257.21:35:16.47#ibcon#about to read 6, iclass 28, count 0 2006.257.21:35:16.47#ibcon#read 6, iclass 28, count 0 2006.257.21:35:16.47#ibcon#end of sib2, iclass 28, count 0 2006.257.21:35:16.47#ibcon#*after write, iclass 28, count 0 2006.257.21:35:16.47#ibcon#*before return 0, iclass 28, count 0 2006.257.21:35:16.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:16.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:16.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.21:35:16.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.21:35:16.47$vck44/valo=7,864.99 2006.257.21:35:16.47#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.21:35:16.47#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.21:35:16.47#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:16.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:16.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:16.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:16.47#ibcon#enter wrdev, iclass 30, count 0 2006.257.21:35:16.47#ibcon#first serial, iclass 30, count 0 2006.257.21:35:16.47#ibcon#enter sib2, iclass 30, count 0 2006.257.21:35:16.47#ibcon#flushed, iclass 30, count 0 2006.257.21:35:16.47#ibcon#about to write, iclass 30, count 0 2006.257.21:35:16.47#ibcon#wrote, iclass 30, count 0 2006.257.21:35:16.47#ibcon#about to read 3, iclass 30, count 0 2006.257.21:35:16.49#ibcon#read 3, iclass 30, count 0 2006.257.21:35:16.49#ibcon#about to read 4, iclass 30, count 0 2006.257.21:35:16.49#ibcon#read 4, iclass 30, count 0 2006.257.21:35:16.49#ibcon#about to read 5, iclass 30, count 0 2006.257.21:35:16.49#ibcon#read 5, iclass 30, count 0 2006.257.21:35:16.49#ibcon#about to read 6, iclass 30, count 0 2006.257.21:35:16.49#ibcon#read 6, iclass 30, count 0 2006.257.21:35:16.49#ibcon#end of sib2, iclass 30, count 0 2006.257.21:35:16.49#ibcon#*mode == 0, iclass 30, count 0 2006.257.21:35:16.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.21:35:16.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.21:35:16.49#ibcon#*before write, iclass 30, count 0 2006.257.21:35:16.49#ibcon#enter sib2, iclass 30, count 0 2006.257.21:35:16.49#ibcon#flushed, iclass 30, count 0 2006.257.21:35:16.49#ibcon#about to write, iclass 30, count 0 2006.257.21:35:16.49#ibcon#wrote, iclass 30, count 0 2006.257.21:35:16.49#ibcon#about to read 3, iclass 30, count 0 2006.257.21:35:16.53#ibcon#read 3, iclass 30, count 0 2006.257.21:35:16.53#ibcon#about to read 4, iclass 30, count 0 2006.257.21:35:16.53#ibcon#read 4, iclass 30, count 0 2006.257.21:35:16.53#ibcon#about to read 5, iclass 30, count 0 2006.257.21:35:16.53#ibcon#read 5, iclass 30, count 0 2006.257.21:35:16.53#ibcon#about to read 6, iclass 30, count 0 2006.257.21:35:16.53#ibcon#read 6, iclass 30, count 0 2006.257.21:35:16.53#ibcon#end of sib2, iclass 30, count 0 2006.257.21:35:16.53#ibcon#*after write, iclass 30, count 0 2006.257.21:35:16.53#ibcon#*before return 0, iclass 30, count 0 2006.257.21:35:16.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:16.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:16.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.21:35:16.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.21:35:16.53$vck44/va=7,4 2006.257.21:35:16.53#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.21:35:16.53#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.21:35:16.53#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:16.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:16.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:16.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:16.59#ibcon#enter wrdev, iclass 32, count 2 2006.257.21:35:16.59#ibcon#first serial, iclass 32, count 2 2006.257.21:35:16.59#ibcon#enter sib2, iclass 32, count 2 2006.257.21:35:16.59#ibcon#flushed, iclass 32, count 2 2006.257.21:35:16.59#ibcon#about to write, iclass 32, count 2 2006.257.21:35:16.59#ibcon#wrote, iclass 32, count 2 2006.257.21:35:16.59#ibcon#about to read 3, iclass 32, count 2 2006.257.21:35:16.61#ibcon#read 3, iclass 32, count 2 2006.257.21:35:16.61#ibcon#about to read 4, iclass 32, count 2 2006.257.21:35:16.61#ibcon#read 4, iclass 32, count 2 2006.257.21:35:16.61#ibcon#about to read 5, iclass 32, count 2 2006.257.21:35:16.61#ibcon#read 5, iclass 32, count 2 2006.257.21:35:16.61#ibcon#about to read 6, iclass 32, count 2 2006.257.21:35:16.61#ibcon#read 6, iclass 32, count 2 2006.257.21:35:16.61#ibcon#end of sib2, iclass 32, count 2 2006.257.21:35:16.61#ibcon#*mode == 0, iclass 32, count 2 2006.257.21:35:16.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.21:35:16.61#ibcon#[25=AT07-04\r\n] 2006.257.21:35:16.61#ibcon#*before write, iclass 32, count 2 2006.257.21:35:16.61#ibcon#enter sib2, iclass 32, count 2 2006.257.21:35:16.61#ibcon#flushed, iclass 32, count 2 2006.257.21:35:16.61#ibcon#about to write, iclass 32, count 2 2006.257.21:35:16.61#ibcon#wrote, iclass 32, count 2 2006.257.21:35:16.61#ibcon#about to read 3, iclass 32, count 2 2006.257.21:35:16.64#ibcon#read 3, iclass 32, count 2 2006.257.21:35:16.64#ibcon#about to read 4, iclass 32, count 2 2006.257.21:35:16.64#ibcon#read 4, iclass 32, count 2 2006.257.21:35:16.64#ibcon#about to read 5, iclass 32, count 2 2006.257.21:35:16.64#ibcon#read 5, iclass 32, count 2 2006.257.21:35:16.64#ibcon#about to read 6, iclass 32, count 2 2006.257.21:35:16.64#ibcon#read 6, iclass 32, count 2 2006.257.21:35:16.64#ibcon#end of sib2, iclass 32, count 2 2006.257.21:35:16.64#ibcon#*after write, iclass 32, count 2 2006.257.21:35:16.64#ibcon#*before return 0, iclass 32, count 2 2006.257.21:35:16.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:16.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:16.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.21:35:16.64#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:16.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:16.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:16.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:16.76#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:35:16.76#ibcon#first serial, iclass 32, count 0 2006.257.21:35:16.76#ibcon#enter sib2, iclass 32, count 0 2006.257.21:35:16.76#ibcon#flushed, iclass 32, count 0 2006.257.21:35:16.76#ibcon#about to write, iclass 32, count 0 2006.257.21:35:16.76#ibcon#wrote, iclass 32, count 0 2006.257.21:35:16.76#ibcon#about to read 3, iclass 32, count 0 2006.257.21:35:16.78#ibcon#read 3, iclass 32, count 0 2006.257.21:35:16.78#ibcon#about to read 4, iclass 32, count 0 2006.257.21:35:16.78#ibcon#read 4, iclass 32, count 0 2006.257.21:35:16.78#ibcon#about to read 5, iclass 32, count 0 2006.257.21:35:16.78#ibcon#read 5, iclass 32, count 0 2006.257.21:35:16.78#ibcon#about to read 6, iclass 32, count 0 2006.257.21:35:16.78#ibcon#read 6, iclass 32, count 0 2006.257.21:35:16.78#ibcon#end of sib2, iclass 32, count 0 2006.257.21:35:16.78#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:35:16.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:35:16.78#ibcon#[25=USB\r\n] 2006.257.21:35:16.78#ibcon#*before write, iclass 32, count 0 2006.257.21:35:16.78#ibcon#enter sib2, iclass 32, count 0 2006.257.21:35:16.78#ibcon#flushed, iclass 32, count 0 2006.257.21:35:16.78#ibcon#about to write, iclass 32, count 0 2006.257.21:35:16.78#ibcon#wrote, iclass 32, count 0 2006.257.21:35:16.78#ibcon#about to read 3, iclass 32, count 0 2006.257.21:35:16.81#ibcon#read 3, iclass 32, count 0 2006.257.21:35:16.81#ibcon#about to read 4, iclass 32, count 0 2006.257.21:35:16.81#ibcon#read 4, iclass 32, count 0 2006.257.21:35:16.81#ibcon#about to read 5, iclass 32, count 0 2006.257.21:35:16.81#ibcon#read 5, iclass 32, count 0 2006.257.21:35:16.81#ibcon#about to read 6, iclass 32, count 0 2006.257.21:35:16.81#ibcon#read 6, iclass 32, count 0 2006.257.21:35:16.81#ibcon#end of sib2, iclass 32, count 0 2006.257.21:35:16.81#ibcon#*after write, iclass 32, count 0 2006.257.21:35:16.81#ibcon#*before return 0, iclass 32, count 0 2006.257.21:35:16.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:16.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:16.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:35:16.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:35:16.81$vck44/valo=8,884.99 2006.257.21:35:16.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.21:35:16.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.21:35:16.81#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:16.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:16.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:16.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:16.81#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:35:16.81#ibcon#first serial, iclass 34, count 0 2006.257.21:35:16.81#ibcon#enter sib2, iclass 34, count 0 2006.257.21:35:16.81#ibcon#flushed, iclass 34, count 0 2006.257.21:35:16.81#ibcon#about to write, iclass 34, count 0 2006.257.21:35:16.81#ibcon#wrote, iclass 34, count 0 2006.257.21:35:16.81#ibcon#about to read 3, iclass 34, count 0 2006.257.21:35:16.83#ibcon#read 3, iclass 34, count 0 2006.257.21:35:16.83#ibcon#about to read 4, iclass 34, count 0 2006.257.21:35:16.83#ibcon#read 4, iclass 34, count 0 2006.257.21:35:16.83#ibcon#about to read 5, iclass 34, count 0 2006.257.21:35:16.83#ibcon#read 5, iclass 34, count 0 2006.257.21:35:16.83#ibcon#about to read 6, iclass 34, count 0 2006.257.21:35:16.83#ibcon#read 6, iclass 34, count 0 2006.257.21:35:16.83#ibcon#end of sib2, iclass 34, count 0 2006.257.21:35:16.83#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:35:16.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:35:16.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.21:35:16.83#ibcon#*before write, iclass 34, count 0 2006.257.21:35:16.83#ibcon#enter sib2, iclass 34, count 0 2006.257.21:35:16.83#ibcon#flushed, iclass 34, count 0 2006.257.21:35:16.83#ibcon#about to write, iclass 34, count 0 2006.257.21:35:16.83#ibcon#wrote, iclass 34, count 0 2006.257.21:35:16.83#ibcon#about to read 3, iclass 34, count 0 2006.257.21:35:16.87#ibcon#read 3, iclass 34, count 0 2006.257.21:35:16.87#ibcon#about to read 4, iclass 34, count 0 2006.257.21:35:16.87#ibcon#read 4, iclass 34, count 0 2006.257.21:35:16.87#ibcon#about to read 5, iclass 34, count 0 2006.257.21:35:16.87#ibcon#read 5, iclass 34, count 0 2006.257.21:35:16.87#ibcon#about to read 6, iclass 34, count 0 2006.257.21:35:16.87#ibcon#read 6, iclass 34, count 0 2006.257.21:35:16.87#ibcon#end of sib2, iclass 34, count 0 2006.257.21:35:16.87#ibcon#*after write, iclass 34, count 0 2006.257.21:35:16.87#ibcon#*before return 0, iclass 34, count 0 2006.257.21:35:16.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:16.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:16.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:35:16.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:35:16.87$vck44/va=8,4 2006.257.21:35:16.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.21:35:16.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.21:35:16.87#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:16.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:35:16.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:35:16.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:35:16.93#ibcon#enter wrdev, iclass 36, count 2 2006.257.21:35:16.93#ibcon#first serial, iclass 36, count 2 2006.257.21:35:16.93#ibcon#enter sib2, iclass 36, count 2 2006.257.21:35:16.93#ibcon#flushed, iclass 36, count 2 2006.257.21:35:16.93#ibcon#about to write, iclass 36, count 2 2006.257.21:35:16.93#ibcon#wrote, iclass 36, count 2 2006.257.21:35:16.93#ibcon#about to read 3, iclass 36, count 2 2006.257.21:35:16.95#ibcon#read 3, iclass 36, count 2 2006.257.21:35:16.95#ibcon#about to read 4, iclass 36, count 2 2006.257.21:35:16.95#ibcon#read 4, iclass 36, count 2 2006.257.21:35:16.95#ibcon#about to read 5, iclass 36, count 2 2006.257.21:35:16.95#ibcon#read 5, iclass 36, count 2 2006.257.21:35:16.95#ibcon#about to read 6, iclass 36, count 2 2006.257.21:35:16.95#ibcon#read 6, iclass 36, count 2 2006.257.21:35:16.95#ibcon#end of sib2, iclass 36, count 2 2006.257.21:35:16.95#ibcon#*mode == 0, iclass 36, count 2 2006.257.21:35:16.95#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.21:35:16.95#ibcon#[25=AT08-04\r\n] 2006.257.21:35:16.95#ibcon#*before write, iclass 36, count 2 2006.257.21:35:16.95#ibcon#enter sib2, iclass 36, count 2 2006.257.21:35:16.95#ibcon#flushed, iclass 36, count 2 2006.257.21:35:16.95#ibcon#about to write, iclass 36, count 2 2006.257.21:35:16.95#ibcon#wrote, iclass 36, count 2 2006.257.21:35:16.95#ibcon#about to read 3, iclass 36, count 2 2006.257.21:35:16.98#ibcon#read 3, iclass 36, count 2 2006.257.21:35:16.98#ibcon#about to read 4, iclass 36, count 2 2006.257.21:35:16.98#ibcon#read 4, iclass 36, count 2 2006.257.21:35:16.98#ibcon#about to read 5, iclass 36, count 2 2006.257.21:35:16.98#ibcon#read 5, iclass 36, count 2 2006.257.21:35:16.98#ibcon#about to read 6, iclass 36, count 2 2006.257.21:35:16.98#ibcon#read 6, iclass 36, count 2 2006.257.21:35:16.98#ibcon#end of sib2, iclass 36, count 2 2006.257.21:35:16.98#ibcon#*after write, iclass 36, count 2 2006.257.21:35:16.98#ibcon#*before return 0, iclass 36, count 2 2006.257.21:35:16.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:35:16.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:35:16.98#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.21:35:16.98#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:16.98#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:35:17.10#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:35:17.10#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:35:17.10#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:35:17.10#ibcon#first serial, iclass 36, count 0 2006.257.21:35:17.10#ibcon#enter sib2, iclass 36, count 0 2006.257.21:35:17.10#ibcon#flushed, iclass 36, count 0 2006.257.21:35:17.10#ibcon#about to write, iclass 36, count 0 2006.257.21:35:17.10#ibcon#wrote, iclass 36, count 0 2006.257.21:35:17.10#ibcon#about to read 3, iclass 36, count 0 2006.257.21:35:17.12#ibcon#read 3, iclass 36, count 0 2006.257.21:35:17.12#ibcon#about to read 4, iclass 36, count 0 2006.257.21:35:17.12#ibcon#read 4, iclass 36, count 0 2006.257.21:35:17.12#ibcon#about to read 5, iclass 36, count 0 2006.257.21:35:17.12#ibcon#read 5, iclass 36, count 0 2006.257.21:35:17.12#ibcon#about to read 6, iclass 36, count 0 2006.257.21:35:17.12#ibcon#read 6, iclass 36, count 0 2006.257.21:35:17.12#ibcon#end of sib2, iclass 36, count 0 2006.257.21:35:17.12#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:35:17.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:35:17.12#ibcon#[25=USB\r\n] 2006.257.21:35:17.12#ibcon#*before write, iclass 36, count 0 2006.257.21:35:17.12#ibcon#enter sib2, iclass 36, count 0 2006.257.21:35:17.12#ibcon#flushed, iclass 36, count 0 2006.257.21:35:17.12#ibcon#about to write, iclass 36, count 0 2006.257.21:35:17.12#ibcon#wrote, iclass 36, count 0 2006.257.21:35:17.12#ibcon#about to read 3, iclass 36, count 0 2006.257.21:35:17.15#ibcon#read 3, iclass 36, count 0 2006.257.21:35:17.15#ibcon#about to read 4, iclass 36, count 0 2006.257.21:35:17.15#ibcon#read 4, iclass 36, count 0 2006.257.21:35:17.15#ibcon#about to read 5, iclass 36, count 0 2006.257.21:35:17.15#ibcon#read 5, iclass 36, count 0 2006.257.21:35:17.15#ibcon#about to read 6, iclass 36, count 0 2006.257.21:35:17.15#ibcon#read 6, iclass 36, count 0 2006.257.21:35:17.15#ibcon#end of sib2, iclass 36, count 0 2006.257.21:35:17.15#ibcon#*after write, iclass 36, count 0 2006.257.21:35:17.15#ibcon#*before return 0, iclass 36, count 0 2006.257.21:35:17.15#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:35:17.15#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:35:17.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:35:17.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:35:17.15$vck44/vblo=1,629.99 2006.257.21:35:17.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.21:35:17.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.21:35:17.15#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:17.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:35:17.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:35:17.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:35:17.15#ibcon#enter wrdev, iclass 38, count 0 2006.257.21:35:17.15#ibcon#first serial, iclass 38, count 0 2006.257.21:35:17.15#ibcon#enter sib2, iclass 38, count 0 2006.257.21:35:17.15#ibcon#flushed, iclass 38, count 0 2006.257.21:35:17.15#ibcon#about to write, iclass 38, count 0 2006.257.21:35:17.15#ibcon#wrote, iclass 38, count 0 2006.257.21:35:17.15#ibcon#about to read 3, iclass 38, count 0 2006.257.21:35:17.17#ibcon#read 3, iclass 38, count 0 2006.257.21:35:17.17#ibcon#about to read 4, iclass 38, count 0 2006.257.21:35:17.17#ibcon#read 4, iclass 38, count 0 2006.257.21:35:17.17#ibcon#about to read 5, iclass 38, count 0 2006.257.21:35:17.17#ibcon#read 5, iclass 38, count 0 2006.257.21:35:17.17#ibcon#about to read 6, iclass 38, count 0 2006.257.21:35:17.17#ibcon#read 6, iclass 38, count 0 2006.257.21:35:17.17#ibcon#end of sib2, iclass 38, count 0 2006.257.21:35:17.17#ibcon#*mode == 0, iclass 38, count 0 2006.257.21:35:17.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.21:35:17.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.21:35:17.17#ibcon#*before write, iclass 38, count 0 2006.257.21:35:17.17#ibcon#enter sib2, iclass 38, count 0 2006.257.21:35:17.17#ibcon#flushed, iclass 38, count 0 2006.257.21:35:17.17#ibcon#about to write, iclass 38, count 0 2006.257.21:35:17.17#ibcon#wrote, iclass 38, count 0 2006.257.21:35:17.17#ibcon#about to read 3, iclass 38, count 0 2006.257.21:35:17.21#ibcon#read 3, iclass 38, count 0 2006.257.21:35:17.21#ibcon#about to read 4, iclass 38, count 0 2006.257.21:35:17.21#ibcon#read 4, iclass 38, count 0 2006.257.21:35:17.21#ibcon#about to read 5, iclass 38, count 0 2006.257.21:35:17.21#ibcon#read 5, iclass 38, count 0 2006.257.21:35:17.21#ibcon#about to read 6, iclass 38, count 0 2006.257.21:35:17.21#ibcon#read 6, iclass 38, count 0 2006.257.21:35:17.21#ibcon#end of sib2, iclass 38, count 0 2006.257.21:35:17.21#ibcon#*after write, iclass 38, count 0 2006.257.21:35:17.21#ibcon#*before return 0, iclass 38, count 0 2006.257.21:35:17.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:35:17.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:35:17.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.21:35:17.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.21:35:17.21$vck44/vb=1,4 2006.257.21:35:17.21#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.21:35:17.21#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.21:35:17.21#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:17.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:35:17.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:35:17.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:35:17.21#ibcon#enter wrdev, iclass 40, count 2 2006.257.21:35:17.21#ibcon#first serial, iclass 40, count 2 2006.257.21:35:17.21#ibcon#enter sib2, iclass 40, count 2 2006.257.21:35:17.21#ibcon#flushed, iclass 40, count 2 2006.257.21:35:17.21#ibcon#about to write, iclass 40, count 2 2006.257.21:35:17.21#ibcon#wrote, iclass 40, count 2 2006.257.21:35:17.21#ibcon#about to read 3, iclass 40, count 2 2006.257.21:35:17.23#ibcon#read 3, iclass 40, count 2 2006.257.21:35:17.23#ibcon#about to read 4, iclass 40, count 2 2006.257.21:35:17.23#ibcon#read 4, iclass 40, count 2 2006.257.21:35:17.23#ibcon#about to read 5, iclass 40, count 2 2006.257.21:35:17.23#ibcon#read 5, iclass 40, count 2 2006.257.21:35:17.23#ibcon#about to read 6, iclass 40, count 2 2006.257.21:35:17.23#ibcon#read 6, iclass 40, count 2 2006.257.21:35:17.23#ibcon#end of sib2, iclass 40, count 2 2006.257.21:35:17.23#ibcon#*mode == 0, iclass 40, count 2 2006.257.21:35:17.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.21:35:17.23#ibcon#[27=AT01-04\r\n] 2006.257.21:35:17.23#ibcon#*before write, iclass 40, count 2 2006.257.21:35:17.23#ibcon#enter sib2, iclass 40, count 2 2006.257.21:35:17.23#ibcon#flushed, iclass 40, count 2 2006.257.21:35:17.23#ibcon#about to write, iclass 40, count 2 2006.257.21:35:17.23#ibcon#wrote, iclass 40, count 2 2006.257.21:35:17.23#ibcon#about to read 3, iclass 40, count 2 2006.257.21:35:17.26#ibcon#read 3, iclass 40, count 2 2006.257.21:35:17.26#ibcon#about to read 4, iclass 40, count 2 2006.257.21:35:17.26#ibcon#read 4, iclass 40, count 2 2006.257.21:35:17.26#ibcon#about to read 5, iclass 40, count 2 2006.257.21:35:17.26#ibcon#read 5, iclass 40, count 2 2006.257.21:35:17.26#ibcon#about to read 6, iclass 40, count 2 2006.257.21:35:17.26#ibcon#read 6, iclass 40, count 2 2006.257.21:35:17.26#ibcon#end of sib2, iclass 40, count 2 2006.257.21:35:17.26#ibcon#*after write, iclass 40, count 2 2006.257.21:35:17.26#ibcon#*before return 0, iclass 40, count 2 2006.257.21:35:17.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:35:17.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:35:17.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.21:35:17.26#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:17.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:35:17.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:35:17.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:35:17.38#ibcon#enter wrdev, iclass 40, count 0 2006.257.21:35:17.38#ibcon#first serial, iclass 40, count 0 2006.257.21:35:17.38#ibcon#enter sib2, iclass 40, count 0 2006.257.21:35:17.38#ibcon#flushed, iclass 40, count 0 2006.257.21:35:17.38#ibcon#about to write, iclass 40, count 0 2006.257.21:35:17.38#ibcon#wrote, iclass 40, count 0 2006.257.21:35:17.38#ibcon#about to read 3, iclass 40, count 0 2006.257.21:35:17.40#ibcon#read 3, iclass 40, count 0 2006.257.21:35:17.40#ibcon#about to read 4, iclass 40, count 0 2006.257.21:35:17.40#ibcon#read 4, iclass 40, count 0 2006.257.21:35:17.40#ibcon#about to read 5, iclass 40, count 0 2006.257.21:35:17.40#ibcon#read 5, iclass 40, count 0 2006.257.21:35:17.40#ibcon#about to read 6, iclass 40, count 0 2006.257.21:35:17.40#ibcon#read 6, iclass 40, count 0 2006.257.21:35:17.40#ibcon#end of sib2, iclass 40, count 0 2006.257.21:35:17.40#ibcon#*mode == 0, iclass 40, count 0 2006.257.21:35:17.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.21:35:17.40#ibcon#[27=USB\r\n] 2006.257.21:35:17.40#ibcon#*before write, iclass 40, count 0 2006.257.21:35:17.40#ibcon#enter sib2, iclass 40, count 0 2006.257.21:35:17.40#ibcon#flushed, iclass 40, count 0 2006.257.21:35:17.40#ibcon#about to write, iclass 40, count 0 2006.257.21:35:17.40#ibcon#wrote, iclass 40, count 0 2006.257.21:35:17.40#ibcon#about to read 3, iclass 40, count 0 2006.257.21:35:17.43#ibcon#read 3, iclass 40, count 0 2006.257.21:35:17.43#ibcon#about to read 4, iclass 40, count 0 2006.257.21:35:17.43#ibcon#read 4, iclass 40, count 0 2006.257.21:35:17.43#ibcon#about to read 5, iclass 40, count 0 2006.257.21:35:17.43#ibcon#read 5, iclass 40, count 0 2006.257.21:35:17.43#ibcon#about to read 6, iclass 40, count 0 2006.257.21:35:17.43#ibcon#read 6, iclass 40, count 0 2006.257.21:35:17.43#ibcon#end of sib2, iclass 40, count 0 2006.257.21:35:17.43#ibcon#*after write, iclass 40, count 0 2006.257.21:35:17.43#ibcon#*before return 0, iclass 40, count 0 2006.257.21:35:17.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:35:17.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:35:17.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.21:35:17.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.21:35:17.43$vck44/vblo=2,634.99 2006.257.21:35:17.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.21:35:17.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.21:35:17.43#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:17.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:17.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:17.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:17.43#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:35:17.43#ibcon#first serial, iclass 4, count 0 2006.257.21:35:17.43#ibcon#enter sib2, iclass 4, count 0 2006.257.21:35:17.43#ibcon#flushed, iclass 4, count 0 2006.257.21:35:17.43#ibcon#about to write, iclass 4, count 0 2006.257.21:35:17.43#ibcon#wrote, iclass 4, count 0 2006.257.21:35:17.43#ibcon#about to read 3, iclass 4, count 0 2006.257.21:35:17.45#ibcon#read 3, iclass 4, count 0 2006.257.21:35:17.45#ibcon#about to read 4, iclass 4, count 0 2006.257.21:35:17.45#ibcon#read 4, iclass 4, count 0 2006.257.21:35:17.45#ibcon#about to read 5, iclass 4, count 0 2006.257.21:35:17.45#ibcon#read 5, iclass 4, count 0 2006.257.21:35:17.45#ibcon#about to read 6, iclass 4, count 0 2006.257.21:35:17.45#ibcon#read 6, iclass 4, count 0 2006.257.21:35:17.45#ibcon#end of sib2, iclass 4, count 0 2006.257.21:35:17.45#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:35:17.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:35:17.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.21:35:17.45#ibcon#*before write, iclass 4, count 0 2006.257.21:35:17.45#ibcon#enter sib2, iclass 4, count 0 2006.257.21:35:17.45#ibcon#flushed, iclass 4, count 0 2006.257.21:35:17.45#ibcon#about to write, iclass 4, count 0 2006.257.21:35:17.45#ibcon#wrote, iclass 4, count 0 2006.257.21:35:17.45#ibcon#about to read 3, iclass 4, count 0 2006.257.21:35:17.49#ibcon#read 3, iclass 4, count 0 2006.257.21:35:17.49#ibcon#about to read 4, iclass 4, count 0 2006.257.21:35:17.49#ibcon#read 4, iclass 4, count 0 2006.257.21:35:17.49#ibcon#about to read 5, iclass 4, count 0 2006.257.21:35:17.49#ibcon#read 5, iclass 4, count 0 2006.257.21:35:17.49#ibcon#about to read 6, iclass 4, count 0 2006.257.21:35:17.49#ibcon#read 6, iclass 4, count 0 2006.257.21:35:17.49#ibcon#end of sib2, iclass 4, count 0 2006.257.21:35:17.49#ibcon#*after write, iclass 4, count 0 2006.257.21:35:17.49#ibcon#*before return 0, iclass 4, count 0 2006.257.21:35:17.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:17.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:35:17.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:35:17.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:35:17.49$vck44/vb=2,5 2006.257.21:35:17.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.21:35:17.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.21:35:17.49#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:17.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:17.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:17.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:17.55#ibcon#enter wrdev, iclass 6, count 2 2006.257.21:35:17.55#ibcon#first serial, iclass 6, count 2 2006.257.21:35:17.55#ibcon#enter sib2, iclass 6, count 2 2006.257.21:35:17.55#ibcon#flushed, iclass 6, count 2 2006.257.21:35:17.55#ibcon#about to write, iclass 6, count 2 2006.257.21:35:17.55#ibcon#wrote, iclass 6, count 2 2006.257.21:35:17.55#ibcon#about to read 3, iclass 6, count 2 2006.257.21:35:17.57#ibcon#read 3, iclass 6, count 2 2006.257.21:35:17.57#ibcon#about to read 4, iclass 6, count 2 2006.257.21:35:17.57#ibcon#read 4, iclass 6, count 2 2006.257.21:35:17.57#ibcon#about to read 5, iclass 6, count 2 2006.257.21:35:17.57#ibcon#read 5, iclass 6, count 2 2006.257.21:35:17.57#ibcon#about to read 6, iclass 6, count 2 2006.257.21:35:17.57#ibcon#read 6, iclass 6, count 2 2006.257.21:35:17.57#ibcon#end of sib2, iclass 6, count 2 2006.257.21:35:17.57#ibcon#*mode == 0, iclass 6, count 2 2006.257.21:35:17.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.21:35:17.57#ibcon#[27=AT02-05\r\n] 2006.257.21:35:17.57#ibcon#*before write, iclass 6, count 2 2006.257.21:35:17.57#ibcon#enter sib2, iclass 6, count 2 2006.257.21:35:17.57#ibcon#flushed, iclass 6, count 2 2006.257.21:35:17.57#ibcon#about to write, iclass 6, count 2 2006.257.21:35:17.57#ibcon#wrote, iclass 6, count 2 2006.257.21:35:17.57#ibcon#about to read 3, iclass 6, count 2 2006.257.21:35:17.60#ibcon#read 3, iclass 6, count 2 2006.257.21:35:17.60#ibcon#about to read 4, iclass 6, count 2 2006.257.21:35:17.60#ibcon#read 4, iclass 6, count 2 2006.257.21:35:17.60#ibcon#about to read 5, iclass 6, count 2 2006.257.21:35:17.60#ibcon#read 5, iclass 6, count 2 2006.257.21:35:17.60#ibcon#about to read 6, iclass 6, count 2 2006.257.21:35:17.60#ibcon#read 6, iclass 6, count 2 2006.257.21:35:17.60#ibcon#end of sib2, iclass 6, count 2 2006.257.21:35:17.60#ibcon#*after write, iclass 6, count 2 2006.257.21:35:17.60#ibcon#*before return 0, iclass 6, count 2 2006.257.21:35:17.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:17.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:35:17.60#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.21:35:17.60#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:17.60#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:17.72#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:17.72#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:17.72#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:35:17.72#ibcon#first serial, iclass 6, count 0 2006.257.21:35:17.72#ibcon#enter sib2, iclass 6, count 0 2006.257.21:35:17.72#ibcon#flushed, iclass 6, count 0 2006.257.21:35:17.72#ibcon#about to write, iclass 6, count 0 2006.257.21:35:17.72#ibcon#wrote, iclass 6, count 0 2006.257.21:35:17.72#ibcon#about to read 3, iclass 6, count 0 2006.257.21:35:17.74#ibcon#read 3, iclass 6, count 0 2006.257.21:35:17.74#ibcon#about to read 4, iclass 6, count 0 2006.257.21:35:17.74#ibcon#read 4, iclass 6, count 0 2006.257.21:35:17.74#ibcon#about to read 5, iclass 6, count 0 2006.257.21:35:17.74#ibcon#read 5, iclass 6, count 0 2006.257.21:35:17.74#ibcon#about to read 6, iclass 6, count 0 2006.257.21:35:17.74#ibcon#read 6, iclass 6, count 0 2006.257.21:35:17.74#ibcon#end of sib2, iclass 6, count 0 2006.257.21:35:17.74#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:35:17.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:35:17.74#ibcon#[27=USB\r\n] 2006.257.21:35:17.74#ibcon#*before write, iclass 6, count 0 2006.257.21:35:17.74#ibcon#enter sib2, iclass 6, count 0 2006.257.21:35:17.74#ibcon#flushed, iclass 6, count 0 2006.257.21:35:17.74#ibcon#about to write, iclass 6, count 0 2006.257.21:35:17.74#ibcon#wrote, iclass 6, count 0 2006.257.21:35:17.74#ibcon#about to read 3, iclass 6, count 0 2006.257.21:35:17.77#ibcon#read 3, iclass 6, count 0 2006.257.21:35:17.77#ibcon#about to read 4, iclass 6, count 0 2006.257.21:35:17.77#ibcon#read 4, iclass 6, count 0 2006.257.21:35:17.77#ibcon#about to read 5, iclass 6, count 0 2006.257.21:35:17.77#ibcon#read 5, iclass 6, count 0 2006.257.21:35:17.77#ibcon#about to read 6, iclass 6, count 0 2006.257.21:35:17.77#ibcon#read 6, iclass 6, count 0 2006.257.21:35:17.77#ibcon#end of sib2, iclass 6, count 0 2006.257.21:35:17.77#ibcon#*after write, iclass 6, count 0 2006.257.21:35:17.77#ibcon#*before return 0, iclass 6, count 0 2006.257.21:35:17.77#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:17.77#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:35:17.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:35:17.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:35:17.77$vck44/vblo=3,649.99 2006.257.21:35:17.77#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.21:35:17.77#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.21:35:17.77#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:17.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:17.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:17.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:17.77#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:35:17.77#ibcon#first serial, iclass 10, count 0 2006.257.21:35:17.77#ibcon#enter sib2, iclass 10, count 0 2006.257.21:35:17.77#ibcon#flushed, iclass 10, count 0 2006.257.21:35:17.77#ibcon#about to write, iclass 10, count 0 2006.257.21:35:17.77#ibcon#wrote, iclass 10, count 0 2006.257.21:35:17.77#ibcon#about to read 3, iclass 10, count 0 2006.257.21:35:17.79#ibcon#read 3, iclass 10, count 0 2006.257.21:35:17.79#ibcon#about to read 4, iclass 10, count 0 2006.257.21:35:17.79#ibcon#read 4, iclass 10, count 0 2006.257.21:35:17.79#ibcon#about to read 5, iclass 10, count 0 2006.257.21:35:17.79#ibcon#read 5, iclass 10, count 0 2006.257.21:35:17.79#ibcon#about to read 6, iclass 10, count 0 2006.257.21:35:17.79#ibcon#read 6, iclass 10, count 0 2006.257.21:35:17.79#ibcon#end of sib2, iclass 10, count 0 2006.257.21:35:17.79#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:35:17.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:35:17.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.21:35:17.79#ibcon#*before write, iclass 10, count 0 2006.257.21:35:17.79#ibcon#enter sib2, iclass 10, count 0 2006.257.21:35:17.79#ibcon#flushed, iclass 10, count 0 2006.257.21:35:17.79#ibcon#about to write, iclass 10, count 0 2006.257.21:35:17.79#ibcon#wrote, iclass 10, count 0 2006.257.21:35:17.79#ibcon#about to read 3, iclass 10, count 0 2006.257.21:35:17.83#ibcon#read 3, iclass 10, count 0 2006.257.21:35:17.83#ibcon#about to read 4, iclass 10, count 0 2006.257.21:35:17.83#ibcon#read 4, iclass 10, count 0 2006.257.21:35:17.83#ibcon#about to read 5, iclass 10, count 0 2006.257.21:35:17.83#ibcon#read 5, iclass 10, count 0 2006.257.21:35:17.83#ibcon#about to read 6, iclass 10, count 0 2006.257.21:35:17.83#ibcon#read 6, iclass 10, count 0 2006.257.21:35:17.83#ibcon#end of sib2, iclass 10, count 0 2006.257.21:35:17.83#ibcon#*after write, iclass 10, count 0 2006.257.21:35:17.83#ibcon#*before return 0, iclass 10, count 0 2006.257.21:35:17.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:17.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:35:17.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:35:17.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:35:17.83$vck44/vb=3,4 2006.257.21:35:17.83#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.21:35:17.83#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.21:35:17.83#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:17.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:17.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:17.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:17.89#ibcon#enter wrdev, iclass 12, count 2 2006.257.21:35:17.89#ibcon#first serial, iclass 12, count 2 2006.257.21:35:17.89#ibcon#enter sib2, iclass 12, count 2 2006.257.21:35:17.89#ibcon#flushed, iclass 12, count 2 2006.257.21:35:17.89#ibcon#about to write, iclass 12, count 2 2006.257.21:35:17.89#ibcon#wrote, iclass 12, count 2 2006.257.21:35:17.89#ibcon#about to read 3, iclass 12, count 2 2006.257.21:35:17.91#ibcon#read 3, iclass 12, count 2 2006.257.21:35:17.91#ibcon#about to read 4, iclass 12, count 2 2006.257.21:35:17.91#ibcon#read 4, iclass 12, count 2 2006.257.21:35:17.91#ibcon#about to read 5, iclass 12, count 2 2006.257.21:35:17.91#ibcon#read 5, iclass 12, count 2 2006.257.21:35:17.91#ibcon#about to read 6, iclass 12, count 2 2006.257.21:35:17.91#ibcon#read 6, iclass 12, count 2 2006.257.21:35:17.91#ibcon#end of sib2, iclass 12, count 2 2006.257.21:35:17.91#ibcon#*mode == 0, iclass 12, count 2 2006.257.21:35:17.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.21:35:17.91#ibcon#[27=AT03-04\r\n] 2006.257.21:35:17.91#ibcon#*before write, iclass 12, count 2 2006.257.21:35:17.91#ibcon#enter sib2, iclass 12, count 2 2006.257.21:35:17.91#ibcon#flushed, iclass 12, count 2 2006.257.21:35:17.91#ibcon#about to write, iclass 12, count 2 2006.257.21:35:17.91#ibcon#wrote, iclass 12, count 2 2006.257.21:35:17.91#ibcon#about to read 3, iclass 12, count 2 2006.257.21:35:17.94#ibcon#read 3, iclass 12, count 2 2006.257.21:35:17.94#ibcon#about to read 4, iclass 12, count 2 2006.257.21:35:17.94#ibcon#read 4, iclass 12, count 2 2006.257.21:35:17.94#ibcon#about to read 5, iclass 12, count 2 2006.257.21:35:17.94#ibcon#read 5, iclass 12, count 2 2006.257.21:35:17.94#ibcon#about to read 6, iclass 12, count 2 2006.257.21:35:17.94#ibcon#read 6, iclass 12, count 2 2006.257.21:35:17.94#ibcon#end of sib2, iclass 12, count 2 2006.257.21:35:17.94#ibcon#*after write, iclass 12, count 2 2006.257.21:35:17.94#ibcon#*before return 0, iclass 12, count 2 2006.257.21:35:17.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:17.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:35:17.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.21:35:17.94#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:17.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:18.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:18.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:18.06#ibcon#enter wrdev, iclass 12, count 0 2006.257.21:35:18.06#ibcon#first serial, iclass 12, count 0 2006.257.21:35:18.06#ibcon#enter sib2, iclass 12, count 0 2006.257.21:35:18.06#ibcon#flushed, iclass 12, count 0 2006.257.21:35:18.06#ibcon#about to write, iclass 12, count 0 2006.257.21:35:18.06#ibcon#wrote, iclass 12, count 0 2006.257.21:35:18.06#ibcon#about to read 3, iclass 12, count 0 2006.257.21:35:18.08#ibcon#read 3, iclass 12, count 0 2006.257.21:35:18.08#ibcon#about to read 4, iclass 12, count 0 2006.257.21:35:18.08#ibcon#read 4, iclass 12, count 0 2006.257.21:35:18.08#ibcon#about to read 5, iclass 12, count 0 2006.257.21:35:18.08#ibcon#read 5, iclass 12, count 0 2006.257.21:35:18.08#ibcon#about to read 6, iclass 12, count 0 2006.257.21:35:18.08#ibcon#read 6, iclass 12, count 0 2006.257.21:35:18.08#ibcon#end of sib2, iclass 12, count 0 2006.257.21:35:18.08#ibcon#*mode == 0, iclass 12, count 0 2006.257.21:35:18.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.21:35:18.08#ibcon#[27=USB\r\n] 2006.257.21:35:18.08#ibcon#*before write, iclass 12, count 0 2006.257.21:35:18.08#ibcon#enter sib2, iclass 12, count 0 2006.257.21:35:18.08#ibcon#flushed, iclass 12, count 0 2006.257.21:35:18.08#ibcon#about to write, iclass 12, count 0 2006.257.21:35:18.08#ibcon#wrote, iclass 12, count 0 2006.257.21:35:18.08#ibcon#about to read 3, iclass 12, count 0 2006.257.21:35:18.11#ibcon#read 3, iclass 12, count 0 2006.257.21:35:18.11#ibcon#about to read 4, iclass 12, count 0 2006.257.21:35:18.11#ibcon#read 4, iclass 12, count 0 2006.257.21:35:18.11#ibcon#about to read 5, iclass 12, count 0 2006.257.21:35:18.11#ibcon#read 5, iclass 12, count 0 2006.257.21:35:18.11#ibcon#about to read 6, iclass 12, count 0 2006.257.21:35:18.11#ibcon#read 6, iclass 12, count 0 2006.257.21:35:18.11#ibcon#end of sib2, iclass 12, count 0 2006.257.21:35:18.11#ibcon#*after write, iclass 12, count 0 2006.257.21:35:18.11#ibcon#*before return 0, iclass 12, count 0 2006.257.21:35:18.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:18.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:35:18.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.21:35:18.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.21:35:18.11$vck44/vblo=4,679.99 2006.257.21:35:18.11#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.21:35:18.11#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.21:35:18.11#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:18.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:18.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:18.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:18.11#ibcon#enter wrdev, iclass 14, count 0 2006.257.21:35:18.11#ibcon#first serial, iclass 14, count 0 2006.257.21:35:18.11#ibcon#enter sib2, iclass 14, count 0 2006.257.21:35:18.11#ibcon#flushed, iclass 14, count 0 2006.257.21:35:18.11#ibcon#about to write, iclass 14, count 0 2006.257.21:35:18.11#ibcon#wrote, iclass 14, count 0 2006.257.21:35:18.11#ibcon#about to read 3, iclass 14, count 0 2006.257.21:35:18.13#ibcon#read 3, iclass 14, count 0 2006.257.21:35:18.13#ibcon#about to read 4, iclass 14, count 0 2006.257.21:35:18.13#ibcon#read 4, iclass 14, count 0 2006.257.21:35:18.13#ibcon#about to read 5, iclass 14, count 0 2006.257.21:35:18.13#ibcon#read 5, iclass 14, count 0 2006.257.21:35:18.13#ibcon#about to read 6, iclass 14, count 0 2006.257.21:35:18.13#ibcon#read 6, iclass 14, count 0 2006.257.21:35:18.13#ibcon#end of sib2, iclass 14, count 0 2006.257.21:35:18.13#ibcon#*mode == 0, iclass 14, count 0 2006.257.21:35:18.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.21:35:18.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.21:35:18.13#ibcon#*before write, iclass 14, count 0 2006.257.21:35:18.13#ibcon#enter sib2, iclass 14, count 0 2006.257.21:35:18.13#ibcon#flushed, iclass 14, count 0 2006.257.21:35:18.13#ibcon#about to write, iclass 14, count 0 2006.257.21:35:18.13#ibcon#wrote, iclass 14, count 0 2006.257.21:35:18.13#ibcon#about to read 3, iclass 14, count 0 2006.257.21:35:18.17#ibcon#read 3, iclass 14, count 0 2006.257.21:35:18.17#ibcon#about to read 4, iclass 14, count 0 2006.257.21:35:18.17#ibcon#read 4, iclass 14, count 0 2006.257.21:35:18.17#ibcon#about to read 5, iclass 14, count 0 2006.257.21:35:18.17#ibcon#read 5, iclass 14, count 0 2006.257.21:35:18.17#ibcon#about to read 6, iclass 14, count 0 2006.257.21:35:18.17#ibcon#read 6, iclass 14, count 0 2006.257.21:35:18.17#ibcon#end of sib2, iclass 14, count 0 2006.257.21:35:18.17#ibcon#*after write, iclass 14, count 0 2006.257.21:35:18.17#ibcon#*before return 0, iclass 14, count 0 2006.257.21:35:18.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:18.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:35:18.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.21:35:18.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.21:35:18.17$vck44/vb=4,5 2006.257.21:35:18.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.21:35:18.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.21:35:18.17#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:18.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:18.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:18.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:18.23#ibcon#enter wrdev, iclass 16, count 2 2006.257.21:35:18.23#ibcon#first serial, iclass 16, count 2 2006.257.21:35:18.23#ibcon#enter sib2, iclass 16, count 2 2006.257.21:35:18.23#ibcon#flushed, iclass 16, count 2 2006.257.21:35:18.23#ibcon#about to write, iclass 16, count 2 2006.257.21:35:18.23#ibcon#wrote, iclass 16, count 2 2006.257.21:35:18.23#ibcon#about to read 3, iclass 16, count 2 2006.257.21:35:18.25#ibcon#read 3, iclass 16, count 2 2006.257.21:35:18.25#ibcon#about to read 4, iclass 16, count 2 2006.257.21:35:18.25#ibcon#read 4, iclass 16, count 2 2006.257.21:35:18.25#ibcon#about to read 5, iclass 16, count 2 2006.257.21:35:18.25#ibcon#read 5, iclass 16, count 2 2006.257.21:35:18.25#ibcon#about to read 6, iclass 16, count 2 2006.257.21:35:18.25#ibcon#read 6, iclass 16, count 2 2006.257.21:35:18.25#ibcon#end of sib2, iclass 16, count 2 2006.257.21:35:18.25#ibcon#*mode == 0, iclass 16, count 2 2006.257.21:35:18.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.21:35:18.25#ibcon#[27=AT04-05\r\n] 2006.257.21:35:18.25#ibcon#*before write, iclass 16, count 2 2006.257.21:35:18.25#ibcon#enter sib2, iclass 16, count 2 2006.257.21:35:18.25#ibcon#flushed, iclass 16, count 2 2006.257.21:35:18.25#ibcon#about to write, iclass 16, count 2 2006.257.21:35:18.25#ibcon#wrote, iclass 16, count 2 2006.257.21:35:18.25#ibcon#about to read 3, iclass 16, count 2 2006.257.21:35:18.28#ibcon#read 3, iclass 16, count 2 2006.257.21:35:18.28#ibcon#about to read 4, iclass 16, count 2 2006.257.21:35:18.28#ibcon#read 4, iclass 16, count 2 2006.257.21:35:18.28#ibcon#about to read 5, iclass 16, count 2 2006.257.21:35:18.28#ibcon#read 5, iclass 16, count 2 2006.257.21:35:18.28#ibcon#about to read 6, iclass 16, count 2 2006.257.21:35:18.28#ibcon#read 6, iclass 16, count 2 2006.257.21:35:18.28#ibcon#end of sib2, iclass 16, count 2 2006.257.21:35:18.28#ibcon#*after write, iclass 16, count 2 2006.257.21:35:18.28#ibcon#*before return 0, iclass 16, count 2 2006.257.21:35:18.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:18.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:35:18.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.21:35:18.28#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:18.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:18.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:18.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:18.40#ibcon#enter wrdev, iclass 16, count 0 2006.257.21:35:18.40#ibcon#first serial, iclass 16, count 0 2006.257.21:35:18.40#ibcon#enter sib2, iclass 16, count 0 2006.257.21:35:18.40#ibcon#flushed, iclass 16, count 0 2006.257.21:35:18.40#ibcon#about to write, iclass 16, count 0 2006.257.21:35:18.40#ibcon#wrote, iclass 16, count 0 2006.257.21:35:18.40#ibcon#about to read 3, iclass 16, count 0 2006.257.21:35:18.42#ibcon#read 3, iclass 16, count 0 2006.257.21:35:18.42#ibcon#about to read 4, iclass 16, count 0 2006.257.21:35:18.42#ibcon#read 4, iclass 16, count 0 2006.257.21:35:18.42#ibcon#about to read 5, iclass 16, count 0 2006.257.21:35:18.42#ibcon#read 5, iclass 16, count 0 2006.257.21:35:18.42#ibcon#about to read 6, iclass 16, count 0 2006.257.21:35:18.42#ibcon#read 6, iclass 16, count 0 2006.257.21:35:18.42#ibcon#end of sib2, iclass 16, count 0 2006.257.21:35:18.42#ibcon#*mode == 0, iclass 16, count 0 2006.257.21:35:18.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.21:35:18.42#ibcon#[27=USB\r\n] 2006.257.21:35:18.42#ibcon#*before write, iclass 16, count 0 2006.257.21:35:18.42#ibcon#enter sib2, iclass 16, count 0 2006.257.21:35:18.42#ibcon#flushed, iclass 16, count 0 2006.257.21:35:18.42#ibcon#about to write, iclass 16, count 0 2006.257.21:35:18.42#ibcon#wrote, iclass 16, count 0 2006.257.21:35:18.42#ibcon#about to read 3, iclass 16, count 0 2006.257.21:35:18.45#ibcon#read 3, iclass 16, count 0 2006.257.21:35:18.45#ibcon#about to read 4, iclass 16, count 0 2006.257.21:35:18.45#ibcon#read 4, iclass 16, count 0 2006.257.21:35:18.45#ibcon#about to read 5, iclass 16, count 0 2006.257.21:35:18.45#ibcon#read 5, iclass 16, count 0 2006.257.21:35:18.45#ibcon#about to read 6, iclass 16, count 0 2006.257.21:35:18.45#ibcon#read 6, iclass 16, count 0 2006.257.21:35:18.45#ibcon#end of sib2, iclass 16, count 0 2006.257.21:35:18.45#ibcon#*after write, iclass 16, count 0 2006.257.21:35:18.45#ibcon#*before return 0, iclass 16, count 0 2006.257.21:35:18.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:18.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:35:18.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.21:35:18.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.21:35:18.45$vck44/vblo=5,709.99 2006.257.21:35:18.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.21:35:18.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.21:35:18.45#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:18.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:18.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:18.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:18.45#ibcon#enter wrdev, iclass 18, count 0 2006.257.21:35:18.45#ibcon#first serial, iclass 18, count 0 2006.257.21:35:18.45#ibcon#enter sib2, iclass 18, count 0 2006.257.21:35:18.45#ibcon#flushed, iclass 18, count 0 2006.257.21:35:18.45#ibcon#about to write, iclass 18, count 0 2006.257.21:35:18.45#ibcon#wrote, iclass 18, count 0 2006.257.21:35:18.45#ibcon#about to read 3, iclass 18, count 0 2006.257.21:35:18.47#ibcon#read 3, iclass 18, count 0 2006.257.21:35:18.47#ibcon#about to read 4, iclass 18, count 0 2006.257.21:35:18.47#ibcon#read 4, iclass 18, count 0 2006.257.21:35:18.47#ibcon#about to read 5, iclass 18, count 0 2006.257.21:35:18.47#ibcon#read 5, iclass 18, count 0 2006.257.21:35:18.47#ibcon#about to read 6, iclass 18, count 0 2006.257.21:35:18.47#ibcon#read 6, iclass 18, count 0 2006.257.21:35:18.47#ibcon#end of sib2, iclass 18, count 0 2006.257.21:35:18.47#ibcon#*mode == 0, iclass 18, count 0 2006.257.21:35:18.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.21:35:18.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.21:35:18.47#ibcon#*before write, iclass 18, count 0 2006.257.21:35:18.47#ibcon#enter sib2, iclass 18, count 0 2006.257.21:35:18.47#ibcon#flushed, iclass 18, count 0 2006.257.21:35:18.47#ibcon#about to write, iclass 18, count 0 2006.257.21:35:18.47#ibcon#wrote, iclass 18, count 0 2006.257.21:35:18.47#ibcon#about to read 3, iclass 18, count 0 2006.257.21:35:18.51#ibcon#read 3, iclass 18, count 0 2006.257.21:35:18.51#ibcon#about to read 4, iclass 18, count 0 2006.257.21:35:18.51#ibcon#read 4, iclass 18, count 0 2006.257.21:35:18.51#ibcon#about to read 5, iclass 18, count 0 2006.257.21:35:18.51#ibcon#read 5, iclass 18, count 0 2006.257.21:35:18.51#ibcon#about to read 6, iclass 18, count 0 2006.257.21:35:18.51#ibcon#read 6, iclass 18, count 0 2006.257.21:35:18.51#ibcon#end of sib2, iclass 18, count 0 2006.257.21:35:18.51#ibcon#*after write, iclass 18, count 0 2006.257.21:35:18.51#ibcon#*before return 0, iclass 18, count 0 2006.257.21:35:18.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:18.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:35:18.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.21:35:18.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.21:35:18.51$vck44/vb=5,4 2006.257.21:35:18.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.21:35:18.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.21:35:18.51#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:18.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:18.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:18.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:18.57#ibcon#enter wrdev, iclass 20, count 2 2006.257.21:35:18.57#ibcon#first serial, iclass 20, count 2 2006.257.21:35:18.57#ibcon#enter sib2, iclass 20, count 2 2006.257.21:35:18.57#ibcon#flushed, iclass 20, count 2 2006.257.21:35:18.57#ibcon#about to write, iclass 20, count 2 2006.257.21:35:18.57#ibcon#wrote, iclass 20, count 2 2006.257.21:35:18.57#ibcon#about to read 3, iclass 20, count 2 2006.257.21:35:18.59#ibcon#read 3, iclass 20, count 2 2006.257.21:35:18.59#ibcon#about to read 4, iclass 20, count 2 2006.257.21:35:18.59#ibcon#read 4, iclass 20, count 2 2006.257.21:35:18.59#ibcon#about to read 5, iclass 20, count 2 2006.257.21:35:18.59#ibcon#read 5, iclass 20, count 2 2006.257.21:35:18.59#ibcon#about to read 6, iclass 20, count 2 2006.257.21:35:18.59#ibcon#read 6, iclass 20, count 2 2006.257.21:35:18.59#ibcon#end of sib2, iclass 20, count 2 2006.257.21:35:18.59#ibcon#*mode == 0, iclass 20, count 2 2006.257.21:35:18.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.21:35:18.59#ibcon#[27=AT05-04\r\n] 2006.257.21:35:18.59#ibcon#*before write, iclass 20, count 2 2006.257.21:35:18.59#ibcon#enter sib2, iclass 20, count 2 2006.257.21:35:18.59#ibcon#flushed, iclass 20, count 2 2006.257.21:35:18.59#ibcon#about to write, iclass 20, count 2 2006.257.21:35:18.59#ibcon#wrote, iclass 20, count 2 2006.257.21:35:18.59#ibcon#about to read 3, iclass 20, count 2 2006.257.21:35:18.62#ibcon#read 3, iclass 20, count 2 2006.257.21:35:18.62#ibcon#about to read 4, iclass 20, count 2 2006.257.21:35:18.62#ibcon#read 4, iclass 20, count 2 2006.257.21:35:18.62#ibcon#about to read 5, iclass 20, count 2 2006.257.21:35:18.62#ibcon#read 5, iclass 20, count 2 2006.257.21:35:18.62#ibcon#about to read 6, iclass 20, count 2 2006.257.21:35:18.62#ibcon#read 6, iclass 20, count 2 2006.257.21:35:18.62#ibcon#end of sib2, iclass 20, count 2 2006.257.21:35:18.62#ibcon#*after write, iclass 20, count 2 2006.257.21:35:18.62#ibcon#*before return 0, iclass 20, count 2 2006.257.21:35:18.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:18.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:35:18.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.21:35:18.62#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:18.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:18.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:18.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:18.74#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:35:18.74#ibcon#first serial, iclass 20, count 0 2006.257.21:35:18.74#ibcon#enter sib2, iclass 20, count 0 2006.257.21:35:18.74#ibcon#flushed, iclass 20, count 0 2006.257.21:35:18.74#ibcon#about to write, iclass 20, count 0 2006.257.21:35:18.74#ibcon#wrote, iclass 20, count 0 2006.257.21:35:18.74#ibcon#about to read 3, iclass 20, count 0 2006.257.21:35:18.76#ibcon#read 3, iclass 20, count 0 2006.257.21:35:18.76#ibcon#about to read 4, iclass 20, count 0 2006.257.21:35:18.76#ibcon#read 4, iclass 20, count 0 2006.257.21:35:18.76#ibcon#about to read 5, iclass 20, count 0 2006.257.21:35:18.76#ibcon#read 5, iclass 20, count 0 2006.257.21:35:18.76#ibcon#about to read 6, iclass 20, count 0 2006.257.21:35:18.76#ibcon#read 6, iclass 20, count 0 2006.257.21:35:18.76#ibcon#end of sib2, iclass 20, count 0 2006.257.21:35:18.76#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:35:18.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:35:18.76#ibcon#[27=USB\r\n] 2006.257.21:35:18.76#ibcon#*before write, iclass 20, count 0 2006.257.21:35:18.76#ibcon#enter sib2, iclass 20, count 0 2006.257.21:35:18.76#ibcon#flushed, iclass 20, count 0 2006.257.21:35:18.76#ibcon#about to write, iclass 20, count 0 2006.257.21:35:18.76#ibcon#wrote, iclass 20, count 0 2006.257.21:35:18.76#ibcon#about to read 3, iclass 20, count 0 2006.257.21:35:18.79#ibcon#read 3, iclass 20, count 0 2006.257.21:35:18.79#ibcon#about to read 4, iclass 20, count 0 2006.257.21:35:18.79#ibcon#read 4, iclass 20, count 0 2006.257.21:35:18.79#ibcon#about to read 5, iclass 20, count 0 2006.257.21:35:18.79#ibcon#read 5, iclass 20, count 0 2006.257.21:35:18.79#ibcon#about to read 6, iclass 20, count 0 2006.257.21:35:18.79#ibcon#read 6, iclass 20, count 0 2006.257.21:35:18.79#ibcon#end of sib2, iclass 20, count 0 2006.257.21:35:18.79#ibcon#*after write, iclass 20, count 0 2006.257.21:35:18.79#ibcon#*before return 0, iclass 20, count 0 2006.257.21:35:18.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:18.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:35:18.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:35:18.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:35:18.79$vck44/vblo=6,719.99 2006.257.21:35:18.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.21:35:18.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.21:35:18.79#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:18.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:18.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:18.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:18.79#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:35:18.79#ibcon#first serial, iclass 22, count 0 2006.257.21:35:18.79#ibcon#enter sib2, iclass 22, count 0 2006.257.21:35:18.79#ibcon#flushed, iclass 22, count 0 2006.257.21:35:18.79#ibcon#about to write, iclass 22, count 0 2006.257.21:35:18.79#ibcon#wrote, iclass 22, count 0 2006.257.21:35:18.79#ibcon#about to read 3, iclass 22, count 0 2006.257.21:35:18.81#ibcon#read 3, iclass 22, count 0 2006.257.21:35:18.81#ibcon#about to read 4, iclass 22, count 0 2006.257.21:35:18.81#ibcon#read 4, iclass 22, count 0 2006.257.21:35:18.81#ibcon#about to read 5, iclass 22, count 0 2006.257.21:35:18.81#ibcon#read 5, iclass 22, count 0 2006.257.21:35:18.81#ibcon#about to read 6, iclass 22, count 0 2006.257.21:35:18.81#ibcon#read 6, iclass 22, count 0 2006.257.21:35:18.81#ibcon#end of sib2, iclass 22, count 0 2006.257.21:35:18.81#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:35:18.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:35:18.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.21:35:18.81#ibcon#*before write, iclass 22, count 0 2006.257.21:35:18.81#ibcon#enter sib2, iclass 22, count 0 2006.257.21:35:18.81#ibcon#flushed, iclass 22, count 0 2006.257.21:35:18.81#ibcon#about to write, iclass 22, count 0 2006.257.21:35:18.81#ibcon#wrote, iclass 22, count 0 2006.257.21:35:18.81#ibcon#about to read 3, iclass 22, count 0 2006.257.21:35:18.85#ibcon#read 3, iclass 22, count 0 2006.257.21:35:18.85#ibcon#about to read 4, iclass 22, count 0 2006.257.21:35:18.85#ibcon#read 4, iclass 22, count 0 2006.257.21:35:18.85#ibcon#about to read 5, iclass 22, count 0 2006.257.21:35:18.85#ibcon#read 5, iclass 22, count 0 2006.257.21:35:18.85#ibcon#about to read 6, iclass 22, count 0 2006.257.21:35:18.85#ibcon#read 6, iclass 22, count 0 2006.257.21:35:18.85#ibcon#end of sib2, iclass 22, count 0 2006.257.21:35:18.85#ibcon#*after write, iclass 22, count 0 2006.257.21:35:18.85#ibcon#*before return 0, iclass 22, count 0 2006.257.21:35:18.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:18.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:35:18.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:35:18.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:35:18.85$vck44/vb=6,4 2006.257.21:35:18.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.21:35:18.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.21:35:18.85#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:18.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:18.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:18.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:18.91#ibcon#enter wrdev, iclass 24, count 2 2006.257.21:35:18.91#ibcon#first serial, iclass 24, count 2 2006.257.21:35:18.91#ibcon#enter sib2, iclass 24, count 2 2006.257.21:35:18.91#ibcon#flushed, iclass 24, count 2 2006.257.21:35:18.91#ibcon#about to write, iclass 24, count 2 2006.257.21:35:18.91#ibcon#wrote, iclass 24, count 2 2006.257.21:35:18.91#ibcon#about to read 3, iclass 24, count 2 2006.257.21:35:18.93#ibcon#read 3, iclass 24, count 2 2006.257.21:35:18.93#ibcon#about to read 4, iclass 24, count 2 2006.257.21:35:18.93#ibcon#read 4, iclass 24, count 2 2006.257.21:35:18.93#ibcon#about to read 5, iclass 24, count 2 2006.257.21:35:18.93#ibcon#read 5, iclass 24, count 2 2006.257.21:35:18.93#ibcon#about to read 6, iclass 24, count 2 2006.257.21:35:18.93#ibcon#read 6, iclass 24, count 2 2006.257.21:35:18.93#ibcon#end of sib2, iclass 24, count 2 2006.257.21:35:18.93#ibcon#*mode == 0, iclass 24, count 2 2006.257.21:35:18.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.21:35:18.93#ibcon#[27=AT06-04\r\n] 2006.257.21:35:18.93#ibcon#*before write, iclass 24, count 2 2006.257.21:35:18.93#ibcon#enter sib2, iclass 24, count 2 2006.257.21:35:18.93#ibcon#flushed, iclass 24, count 2 2006.257.21:35:18.93#ibcon#about to write, iclass 24, count 2 2006.257.21:35:18.93#ibcon#wrote, iclass 24, count 2 2006.257.21:35:18.93#ibcon#about to read 3, iclass 24, count 2 2006.257.21:35:18.96#ibcon#read 3, iclass 24, count 2 2006.257.21:35:18.96#ibcon#about to read 4, iclass 24, count 2 2006.257.21:35:18.96#ibcon#read 4, iclass 24, count 2 2006.257.21:35:18.96#ibcon#about to read 5, iclass 24, count 2 2006.257.21:35:18.96#ibcon#read 5, iclass 24, count 2 2006.257.21:35:18.96#ibcon#about to read 6, iclass 24, count 2 2006.257.21:35:18.96#ibcon#read 6, iclass 24, count 2 2006.257.21:35:18.96#ibcon#end of sib2, iclass 24, count 2 2006.257.21:35:18.96#ibcon#*after write, iclass 24, count 2 2006.257.21:35:18.96#ibcon#*before return 0, iclass 24, count 2 2006.257.21:35:18.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:18.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:35:18.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.21:35:18.96#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:18.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:19.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:19.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:19.08#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:35:19.08#ibcon#first serial, iclass 24, count 0 2006.257.21:35:19.08#ibcon#enter sib2, iclass 24, count 0 2006.257.21:35:19.08#ibcon#flushed, iclass 24, count 0 2006.257.21:35:19.08#ibcon#about to write, iclass 24, count 0 2006.257.21:35:19.08#ibcon#wrote, iclass 24, count 0 2006.257.21:35:19.08#ibcon#about to read 3, iclass 24, count 0 2006.257.21:35:19.10#ibcon#read 3, iclass 24, count 0 2006.257.21:35:19.10#ibcon#about to read 4, iclass 24, count 0 2006.257.21:35:19.10#ibcon#read 4, iclass 24, count 0 2006.257.21:35:19.10#ibcon#about to read 5, iclass 24, count 0 2006.257.21:35:19.10#ibcon#read 5, iclass 24, count 0 2006.257.21:35:19.10#ibcon#about to read 6, iclass 24, count 0 2006.257.21:35:19.10#ibcon#read 6, iclass 24, count 0 2006.257.21:35:19.10#ibcon#end of sib2, iclass 24, count 0 2006.257.21:35:19.10#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:35:19.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:35:19.10#ibcon#[27=USB\r\n] 2006.257.21:35:19.10#ibcon#*before write, iclass 24, count 0 2006.257.21:35:19.10#ibcon#enter sib2, iclass 24, count 0 2006.257.21:35:19.10#ibcon#flushed, iclass 24, count 0 2006.257.21:35:19.10#ibcon#about to write, iclass 24, count 0 2006.257.21:35:19.10#ibcon#wrote, iclass 24, count 0 2006.257.21:35:19.10#ibcon#about to read 3, iclass 24, count 0 2006.257.21:35:19.13#ibcon#read 3, iclass 24, count 0 2006.257.21:35:19.13#ibcon#about to read 4, iclass 24, count 0 2006.257.21:35:19.13#ibcon#read 4, iclass 24, count 0 2006.257.21:35:19.13#ibcon#about to read 5, iclass 24, count 0 2006.257.21:35:19.13#ibcon#read 5, iclass 24, count 0 2006.257.21:35:19.13#ibcon#about to read 6, iclass 24, count 0 2006.257.21:35:19.13#ibcon#read 6, iclass 24, count 0 2006.257.21:35:19.13#ibcon#end of sib2, iclass 24, count 0 2006.257.21:35:19.13#ibcon#*after write, iclass 24, count 0 2006.257.21:35:19.13#ibcon#*before return 0, iclass 24, count 0 2006.257.21:35:19.13#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:19.13#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:35:19.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:35:19.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:35:19.13$vck44/vblo=7,734.99 2006.257.21:35:19.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.21:35:19.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.21:35:19.13#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:19.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:19.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:19.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:19.13#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:35:19.13#ibcon#first serial, iclass 26, count 0 2006.257.21:35:19.13#ibcon#enter sib2, iclass 26, count 0 2006.257.21:35:19.13#ibcon#flushed, iclass 26, count 0 2006.257.21:35:19.13#ibcon#about to write, iclass 26, count 0 2006.257.21:35:19.13#ibcon#wrote, iclass 26, count 0 2006.257.21:35:19.13#ibcon#about to read 3, iclass 26, count 0 2006.257.21:35:19.15#ibcon#read 3, iclass 26, count 0 2006.257.21:35:19.15#ibcon#about to read 4, iclass 26, count 0 2006.257.21:35:19.15#ibcon#read 4, iclass 26, count 0 2006.257.21:35:19.15#ibcon#about to read 5, iclass 26, count 0 2006.257.21:35:19.15#ibcon#read 5, iclass 26, count 0 2006.257.21:35:19.15#ibcon#about to read 6, iclass 26, count 0 2006.257.21:35:19.15#ibcon#read 6, iclass 26, count 0 2006.257.21:35:19.15#ibcon#end of sib2, iclass 26, count 0 2006.257.21:35:19.15#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:35:19.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:35:19.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.21:35:19.15#ibcon#*before write, iclass 26, count 0 2006.257.21:35:19.15#ibcon#enter sib2, iclass 26, count 0 2006.257.21:35:19.15#ibcon#flushed, iclass 26, count 0 2006.257.21:35:19.15#ibcon#about to write, iclass 26, count 0 2006.257.21:35:19.15#ibcon#wrote, iclass 26, count 0 2006.257.21:35:19.15#ibcon#about to read 3, iclass 26, count 0 2006.257.21:35:19.19#ibcon#read 3, iclass 26, count 0 2006.257.21:35:19.19#ibcon#about to read 4, iclass 26, count 0 2006.257.21:35:19.19#ibcon#read 4, iclass 26, count 0 2006.257.21:35:19.19#ibcon#about to read 5, iclass 26, count 0 2006.257.21:35:19.19#ibcon#read 5, iclass 26, count 0 2006.257.21:35:19.19#ibcon#about to read 6, iclass 26, count 0 2006.257.21:35:19.19#ibcon#read 6, iclass 26, count 0 2006.257.21:35:19.19#ibcon#end of sib2, iclass 26, count 0 2006.257.21:35:19.19#ibcon#*after write, iclass 26, count 0 2006.257.21:35:19.19#ibcon#*before return 0, iclass 26, count 0 2006.257.21:35:19.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:19.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:35:19.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:35:19.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:35:19.19$vck44/vb=7,4 2006.257.21:35:19.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.21:35:19.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.21:35:19.19#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:19.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:19.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:19.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:19.25#ibcon#enter wrdev, iclass 28, count 2 2006.257.21:35:19.25#ibcon#first serial, iclass 28, count 2 2006.257.21:35:19.25#ibcon#enter sib2, iclass 28, count 2 2006.257.21:35:19.25#ibcon#flushed, iclass 28, count 2 2006.257.21:35:19.25#ibcon#about to write, iclass 28, count 2 2006.257.21:35:19.25#ibcon#wrote, iclass 28, count 2 2006.257.21:35:19.25#ibcon#about to read 3, iclass 28, count 2 2006.257.21:35:19.27#ibcon#read 3, iclass 28, count 2 2006.257.21:35:19.27#ibcon#about to read 4, iclass 28, count 2 2006.257.21:35:19.27#ibcon#read 4, iclass 28, count 2 2006.257.21:35:19.27#ibcon#about to read 5, iclass 28, count 2 2006.257.21:35:19.27#ibcon#read 5, iclass 28, count 2 2006.257.21:35:19.27#ibcon#about to read 6, iclass 28, count 2 2006.257.21:35:19.27#ibcon#read 6, iclass 28, count 2 2006.257.21:35:19.27#ibcon#end of sib2, iclass 28, count 2 2006.257.21:35:19.27#ibcon#*mode == 0, iclass 28, count 2 2006.257.21:35:19.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.21:35:19.27#ibcon#[27=AT07-04\r\n] 2006.257.21:35:19.27#ibcon#*before write, iclass 28, count 2 2006.257.21:35:19.27#ibcon#enter sib2, iclass 28, count 2 2006.257.21:35:19.27#ibcon#flushed, iclass 28, count 2 2006.257.21:35:19.27#ibcon#about to write, iclass 28, count 2 2006.257.21:35:19.27#ibcon#wrote, iclass 28, count 2 2006.257.21:35:19.27#ibcon#about to read 3, iclass 28, count 2 2006.257.21:35:19.30#ibcon#read 3, iclass 28, count 2 2006.257.21:35:19.30#ibcon#about to read 4, iclass 28, count 2 2006.257.21:35:19.30#ibcon#read 4, iclass 28, count 2 2006.257.21:35:19.30#ibcon#about to read 5, iclass 28, count 2 2006.257.21:35:19.30#ibcon#read 5, iclass 28, count 2 2006.257.21:35:19.30#ibcon#about to read 6, iclass 28, count 2 2006.257.21:35:19.30#ibcon#read 6, iclass 28, count 2 2006.257.21:35:19.30#ibcon#end of sib2, iclass 28, count 2 2006.257.21:35:19.30#ibcon#*after write, iclass 28, count 2 2006.257.21:35:19.30#ibcon#*before return 0, iclass 28, count 2 2006.257.21:35:19.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:19.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:35:19.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.21:35:19.30#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:19.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:19.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:19.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:19.42#ibcon#enter wrdev, iclass 28, count 0 2006.257.21:35:19.42#ibcon#first serial, iclass 28, count 0 2006.257.21:35:19.42#ibcon#enter sib2, iclass 28, count 0 2006.257.21:35:19.42#ibcon#flushed, iclass 28, count 0 2006.257.21:35:19.42#ibcon#about to write, iclass 28, count 0 2006.257.21:35:19.42#ibcon#wrote, iclass 28, count 0 2006.257.21:35:19.42#ibcon#about to read 3, iclass 28, count 0 2006.257.21:35:19.44#ibcon#read 3, iclass 28, count 0 2006.257.21:35:19.44#ibcon#about to read 4, iclass 28, count 0 2006.257.21:35:19.44#ibcon#read 4, iclass 28, count 0 2006.257.21:35:19.44#ibcon#about to read 5, iclass 28, count 0 2006.257.21:35:19.44#ibcon#read 5, iclass 28, count 0 2006.257.21:35:19.44#ibcon#about to read 6, iclass 28, count 0 2006.257.21:35:19.44#ibcon#read 6, iclass 28, count 0 2006.257.21:35:19.44#ibcon#end of sib2, iclass 28, count 0 2006.257.21:35:19.44#ibcon#*mode == 0, iclass 28, count 0 2006.257.21:35:19.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.21:35:19.44#ibcon#[27=USB\r\n] 2006.257.21:35:19.44#ibcon#*before write, iclass 28, count 0 2006.257.21:35:19.44#ibcon#enter sib2, iclass 28, count 0 2006.257.21:35:19.44#ibcon#flushed, iclass 28, count 0 2006.257.21:35:19.44#ibcon#about to write, iclass 28, count 0 2006.257.21:35:19.44#ibcon#wrote, iclass 28, count 0 2006.257.21:35:19.44#ibcon#about to read 3, iclass 28, count 0 2006.257.21:35:19.47#ibcon#read 3, iclass 28, count 0 2006.257.21:35:19.47#ibcon#about to read 4, iclass 28, count 0 2006.257.21:35:19.47#ibcon#read 4, iclass 28, count 0 2006.257.21:35:19.47#ibcon#about to read 5, iclass 28, count 0 2006.257.21:35:19.47#ibcon#read 5, iclass 28, count 0 2006.257.21:35:19.47#ibcon#about to read 6, iclass 28, count 0 2006.257.21:35:19.47#ibcon#read 6, iclass 28, count 0 2006.257.21:35:19.47#ibcon#end of sib2, iclass 28, count 0 2006.257.21:35:19.47#ibcon#*after write, iclass 28, count 0 2006.257.21:35:19.47#ibcon#*before return 0, iclass 28, count 0 2006.257.21:35:19.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:19.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:35:19.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.21:35:19.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.21:35:19.47$vck44/vblo=8,744.99 2006.257.21:35:19.47#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.21:35:19.47#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.21:35:19.47#ibcon#ireg 17 cls_cnt 0 2006.257.21:35:19.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:19.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:19.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:19.47#ibcon#enter wrdev, iclass 30, count 0 2006.257.21:35:19.47#ibcon#first serial, iclass 30, count 0 2006.257.21:35:19.47#ibcon#enter sib2, iclass 30, count 0 2006.257.21:35:19.47#ibcon#flushed, iclass 30, count 0 2006.257.21:35:19.47#ibcon#about to write, iclass 30, count 0 2006.257.21:35:19.47#ibcon#wrote, iclass 30, count 0 2006.257.21:35:19.47#ibcon#about to read 3, iclass 30, count 0 2006.257.21:35:19.49#ibcon#read 3, iclass 30, count 0 2006.257.21:35:19.49#ibcon#about to read 4, iclass 30, count 0 2006.257.21:35:19.49#ibcon#read 4, iclass 30, count 0 2006.257.21:35:19.49#ibcon#about to read 5, iclass 30, count 0 2006.257.21:35:19.49#ibcon#read 5, iclass 30, count 0 2006.257.21:35:19.49#ibcon#about to read 6, iclass 30, count 0 2006.257.21:35:19.49#ibcon#read 6, iclass 30, count 0 2006.257.21:35:19.49#ibcon#end of sib2, iclass 30, count 0 2006.257.21:35:19.49#ibcon#*mode == 0, iclass 30, count 0 2006.257.21:35:19.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.21:35:19.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.21:35:19.49#ibcon#*before write, iclass 30, count 0 2006.257.21:35:19.49#ibcon#enter sib2, iclass 30, count 0 2006.257.21:35:19.49#ibcon#flushed, iclass 30, count 0 2006.257.21:35:19.49#ibcon#about to write, iclass 30, count 0 2006.257.21:35:19.49#ibcon#wrote, iclass 30, count 0 2006.257.21:35:19.49#ibcon#about to read 3, iclass 30, count 0 2006.257.21:35:19.53#ibcon#read 3, iclass 30, count 0 2006.257.21:35:19.53#ibcon#about to read 4, iclass 30, count 0 2006.257.21:35:19.53#ibcon#read 4, iclass 30, count 0 2006.257.21:35:19.53#ibcon#about to read 5, iclass 30, count 0 2006.257.21:35:19.53#ibcon#read 5, iclass 30, count 0 2006.257.21:35:19.53#ibcon#about to read 6, iclass 30, count 0 2006.257.21:35:19.53#ibcon#read 6, iclass 30, count 0 2006.257.21:35:19.53#ibcon#end of sib2, iclass 30, count 0 2006.257.21:35:19.53#ibcon#*after write, iclass 30, count 0 2006.257.21:35:19.53#ibcon#*before return 0, iclass 30, count 0 2006.257.21:35:19.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:19.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:35:19.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.21:35:19.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.21:35:19.53$vck44/vb=8,4 2006.257.21:35:19.53#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.21:35:19.53#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.21:35:19.53#ibcon#ireg 11 cls_cnt 2 2006.257.21:35:19.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:19.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:19.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:19.59#ibcon#enter wrdev, iclass 32, count 2 2006.257.21:35:19.59#ibcon#first serial, iclass 32, count 2 2006.257.21:35:19.59#ibcon#enter sib2, iclass 32, count 2 2006.257.21:35:19.59#ibcon#flushed, iclass 32, count 2 2006.257.21:35:19.59#ibcon#about to write, iclass 32, count 2 2006.257.21:35:19.59#ibcon#wrote, iclass 32, count 2 2006.257.21:35:19.59#ibcon#about to read 3, iclass 32, count 2 2006.257.21:35:19.61#ibcon#read 3, iclass 32, count 2 2006.257.21:35:19.61#ibcon#about to read 4, iclass 32, count 2 2006.257.21:35:19.61#ibcon#read 4, iclass 32, count 2 2006.257.21:35:19.61#ibcon#about to read 5, iclass 32, count 2 2006.257.21:35:19.61#ibcon#read 5, iclass 32, count 2 2006.257.21:35:19.61#ibcon#about to read 6, iclass 32, count 2 2006.257.21:35:19.61#ibcon#read 6, iclass 32, count 2 2006.257.21:35:19.61#ibcon#end of sib2, iclass 32, count 2 2006.257.21:35:19.61#ibcon#*mode == 0, iclass 32, count 2 2006.257.21:35:19.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.21:35:19.61#ibcon#[27=AT08-04\r\n] 2006.257.21:35:19.61#ibcon#*before write, iclass 32, count 2 2006.257.21:35:19.61#ibcon#enter sib2, iclass 32, count 2 2006.257.21:35:19.61#ibcon#flushed, iclass 32, count 2 2006.257.21:35:19.61#ibcon#about to write, iclass 32, count 2 2006.257.21:35:19.61#ibcon#wrote, iclass 32, count 2 2006.257.21:35:19.61#ibcon#about to read 3, iclass 32, count 2 2006.257.21:35:19.64#ibcon#read 3, iclass 32, count 2 2006.257.21:35:19.64#ibcon#about to read 4, iclass 32, count 2 2006.257.21:35:19.64#ibcon#read 4, iclass 32, count 2 2006.257.21:35:19.64#ibcon#about to read 5, iclass 32, count 2 2006.257.21:35:19.64#ibcon#read 5, iclass 32, count 2 2006.257.21:35:19.64#ibcon#about to read 6, iclass 32, count 2 2006.257.21:35:19.64#ibcon#read 6, iclass 32, count 2 2006.257.21:35:19.64#ibcon#end of sib2, iclass 32, count 2 2006.257.21:35:19.64#ibcon#*after write, iclass 32, count 2 2006.257.21:35:19.64#ibcon#*before return 0, iclass 32, count 2 2006.257.21:35:19.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:19.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:35:19.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.21:35:19.64#ibcon#ireg 7 cls_cnt 0 2006.257.21:35:19.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:19.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:19.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:19.76#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:35:19.76#ibcon#first serial, iclass 32, count 0 2006.257.21:35:19.76#ibcon#enter sib2, iclass 32, count 0 2006.257.21:35:19.76#ibcon#flushed, iclass 32, count 0 2006.257.21:35:19.76#ibcon#about to write, iclass 32, count 0 2006.257.21:35:19.76#ibcon#wrote, iclass 32, count 0 2006.257.21:35:19.76#ibcon#about to read 3, iclass 32, count 0 2006.257.21:35:19.78#ibcon#read 3, iclass 32, count 0 2006.257.21:35:19.78#ibcon#about to read 4, iclass 32, count 0 2006.257.21:35:19.78#ibcon#read 4, iclass 32, count 0 2006.257.21:35:19.78#ibcon#about to read 5, iclass 32, count 0 2006.257.21:35:19.78#ibcon#read 5, iclass 32, count 0 2006.257.21:35:19.78#ibcon#about to read 6, iclass 32, count 0 2006.257.21:35:19.78#ibcon#read 6, iclass 32, count 0 2006.257.21:35:19.78#ibcon#end of sib2, iclass 32, count 0 2006.257.21:35:19.78#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:35:19.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:35:19.78#ibcon#[27=USB\r\n] 2006.257.21:35:19.78#ibcon#*before write, iclass 32, count 0 2006.257.21:35:19.78#ibcon#enter sib2, iclass 32, count 0 2006.257.21:35:19.78#ibcon#flushed, iclass 32, count 0 2006.257.21:35:19.78#ibcon#about to write, iclass 32, count 0 2006.257.21:35:19.78#ibcon#wrote, iclass 32, count 0 2006.257.21:35:19.78#ibcon#about to read 3, iclass 32, count 0 2006.257.21:35:19.81#ibcon#read 3, iclass 32, count 0 2006.257.21:35:19.81#ibcon#about to read 4, iclass 32, count 0 2006.257.21:35:19.81#ibcon#read 4, iclass 32, count 0 2006.257.21:35:19.81#ibcon#about to read 5, iclass 32, count 0 2006.257.21:35:19.81#ibcon#read 5, iclass 32, count 0 2006.257.21:35:19.81#ibcon#about to read 6, iclass 32, count 0 2006.257.21:35:19.81#ibcon#read 6, iclass 32, count 0 2006.257.21:35:19.81#ibcon#end of sib2, iclass 32, count 0 2006.257.21:35:19.81#ibcon#*after write, iclass 32, count 0 2006.257.21:35:19.81#ibcon#*before return 0, iclass 32, count 0 2006.257.21:35:19.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:19.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:35:19.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:35:19.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:35:19.81$vck44/vabw=wide 2006.257.21:35:19.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.21:35:19.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.21:35:19.81#ibcon#ireg 8 cls_cnt 0 2006.257.21:35:19.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:19.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:19.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:19.81#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:35:19.81#ibcon#first serial, iclass 34, count 0 2006.257.21:35:19.81#ibcon#enter sib2, iclass 34, count 0 2006.257.21:35:19.81#ibcon#flushed, iclass 34, count 0 2006.257.21:35:19.81#ibcon#about to write, iclass 34, count 0 2006.257.21:35:19.81#ibcon#wrote, iclass 34, count 0 2006.257.21:35:19.81#ibcon#about to read 3, iclass 34, count 0 2006.257.21:35:19.83#ibcon#read 3, iclass 34, count 0 2006.257.21:35:19.83#ibcon#about to read 4, iclass 34, count 0 2006.257.21:35:19.83#ibcon#read 4, iclass 34, count 0 2006.257.21:35:19.83#ibcon#about to read 5, iclass 34, count 0 2006.257.21:35:19.83#ibcon#read 5, iclass 34, count 0 2006.257.21:35:19.83#ibcon#about to read 6, iclass 34, count 0 2006.257.21:35:19.83#ibcon#read 6, iclass 34, count 0 2006.257.21:35:19.83#ibcon#end of sib2, iclass 34, count 0 2006.257.21:35:19.83#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:35:19.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:35:19.83#ibcon#[25=BW32\r\n] 2006.257.21:35:19.83#ibcon#*before write, iclass 34, count 0 2006.257.21:35:19.83#ibcon#enter sib2, iclass 34, count 0 2006.257.21:35:19.83#ibcon#flushed, iclass 34, count 0 2006.257.21:35:19.83#ibcon#about to write, iclass 34, count 0 2006.257.21:35:19.83#ibcon#wrote, iclass 34, count 0 2006.257.21:35:19.83#ibcon#about to read 3, iclass 34, count 0 2006.257.21:35:19.86#ibcon#read 3, iclass 34, count 0 2006.257.21:35:19.86#ibcon#about to read 4, iclass 34, count 0 2006.257.21:35:19.86#ibcon#read 4, iclass 34, count 0 2006.257.21:35:19.86#ibcon#about to read 5, iclass 34, count 0 2006.257.21:35:19.86#ibcon#read 5, iclass 34, count 0 2006.257.21:35:19.86#ibcon#about to read 6, iclass 34, count 0 2006.257.21:35:19.86#ibcon#read 6, iclass 34, count 0 2006.257.21:35:19.86#ibcon#end of sib2, iclass 34, count 0 2006.257.21:35:19.86#ibcon#*after write, iclass 34, count 0 2006.257.21:35:19.86#ibcon#*before return 0, iclass 34, count 0 2006.257.21:35:19.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:19.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:35:19.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:35:19.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:35:19.86$vck44/vbbw=wide 2006.257.21:35:19.86#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.21:35:19.86#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.21:35:19.86#ibcon#ireg 8 cls_cnt 0 2006.257.21:35:19.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:35:19.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:35:19.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:35:19.93#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:35:19.93#ibcon#first serial, iclass 36, count 0 2006.257.21:35:19.93#ibcon#enter sib2, iclass 36, count 0 2006.257.21:35:19.93#ibcon#flushed, iclass 36, count 0 2006.257.21:35:19.93#ibcon#about to write, iclass 36, count 0 2006.257.21:35:19.93#ibcon#wrote, iclass 36, count 0 2006.257.21:35:19.93#ibcon#about to read 3, iclass 36, count 0 2006.257.21:35:19.95#ibcon#read 3, iclass 36, count 0 2006.257.21:35:19.95#ibcon#about to read 4, iclass 36, count 0 2006.257.21:35:19.95#ibcon#read 4, iclass 36, count 0 2006.257.21:35:19.95#ibcon#about to read 5, iclass 36, count 0 2006.257.21:35:19.95#ibcon#read 5, iclass 36, count 0 2006.257.21:35:19.95#ibcon#about to read 6, iclass 36, count 0 2006.257.21:35:19.95#ibcon#read 6, iclass 36, count 0 2006.257.21:35:19.95#ibcon#end of sib2, iclass 36, count 0 2006.257.21:35:19.95#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:35:19.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:35:19.95#ibcon#[27=BW32\r\n] 2006.257.21:35:19.95#ibcon#*before write, iclass 36, count 0 2006.257.21:35:19.95#ibcon#enter sib2, iclass 36, count 0 2006.257.21:35:19.95#ibcon#flushed, iclass 36, count 0 2006.257.21:35:19.95#ibcon#about to write, iclass 36, count 0 2006.257.21:35:19.95#ibcon#wrote, iclass 36, count 0 2006.257.21:35:19.95#ibcon#about to read 3, iclass 36, count 0 2006.257.21:35:19.98#ibcon#read 3, iclass 36, count 0 2006.257.21:35:19.98#ibcon#about to read 4, iclass 36, count 0 2006.257.21:35:19.98#ibcon#read 4, iclass 36, count 0 2006.257.21:35:19.98#ibcon#about to read 5, iclass 36, count 0 2006.257.21:35:19.98#ibcon#read 5, iclass 36, count 0 2006.257.21:35:19.98#ibcon#about to read 6, iclass 36, count 0 2006.257.21:35:19.98#ibcon#read 6, iclass 36, count 0 2006.257.21:35:19.98#ibcon#end of sib2, iclass 36, count 0 2006.257.21:35:19.98#ibcon#*after write, iclass 36, count 0 2006.257.21:35:19.98#ibcon#*before return 0, iclass 36, count 0 2006.257.21:35:19.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:35:19.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:35:19.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:35:19.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:35:19.98$setupk4/ifdk4 2006.257.21:35:19.98$ifdk4/lo= 2006.257.21:35:19.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.21:35:19.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.21:35:19.98$ifdk4/patch= 2006.257.21:35:19.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.21:35:19.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.21:35:19.98$setupk4/!*+20s 2006.257.21:35:23.19#abcon#<5=/14 1.1 2.9 17.86 951015.4\r\n> 2006.257.21:35:23.21#abcon#{5=INTERFACE CLEAR} 2006.257.21:35:23.27#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:35:33.36#abcon#<5=/14 1.1 2.9 17.86 951015.4\r\n> 2006.257.21:35:33.38#abcon#{5=INTERFACE CLEAR} 2006.257.21:35:33.44#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:35:34.49$setupk4/"tpicd 2006.257.21:35:34.49$setupk4/echo=off 2006.257.21:35:34.49$setupk4/xlog=off 2006.257.21:35:34.49:!2006.257.21:37:21 2006.257.21:35:36.14#trakl#Source acquired 2006.257.21:35:38.14#flagr#flagr/antenna,acquired 2006.257.21:37:21.00:preob 2006.257.21:37:21.14/onsource/TRACKING 2006.257.21:37:21.14:!2006.257.21:37:31 2006.257.21:37:31.00:"tape 2006.257.21:37:31.00:"st=record 2006.257.21:37:31.00:data_valid=on 2006.257.21:37:31.00:midob 2006.257.21:37:32.14/onsource/TRACKING 2006.257.21:37:32.14/wx/17.88,1015.4,95 2006.257.21:37:32.28/cable/+6.4846E-03 2006.257.21:37:33.37/va/01,08,usb,yes,32,34 2006.257.21:37:33.37/va/02,07,usb,yes,35,35 2006.257.21:37:33.37/va/03,08,usb,yes,31,33 2006.257.21:37:33.37/va/04,07,usb,yes,36,37 2006.257.21:37:33.37/va/05,04,usb,yes,32,32 2006.257.21:37:33.37/va/06,04,usb,yes,36,35 2006.257.21:37:33.37/va/07,04,usb,yes,36,37 2006.257.21:37:33.37/va/08,04,usb,yes,30,37 2006.257.21:37:33.60/valo/01,524.99,yes,locked 2006.257.21:37:33.60/valo/02,534.99,yes,locked 2006.257.21:37:33.60/valo/03,564.99,yes,locked 2006.257.21:37:33.60/valo/04,624.99,yes,locked 2006.257.21:37:33.60/valo/05,734.99,yes,locked 2006.257.21:37:33.60/valo/06,814.99,yes,locked 2006.257.21:37:33.60/valo/07,864.99,yes,locked 2006.257.21:37:33.60/valo/08,884.99,yes,locked 2006.257.21:37:34.69/vb/01,04,usb,yes,31,29 2006.257.21:37:34.69/vb/02,05,usb,yes,29,29 2006.257.21:37:34.69/vb/03,04,usb,yes,30,33 2006.257.21:37:34.69/vb/04,05,usb,yes,30,29 2006.257.21:37:34.69/vb/05,04,usb,yes,27,29 2006.257.21:37:34.69/vb/06,04,usb,yes,31,27 2006.257.21:37:34.69/vb/07,04,usb,yes,31,31 2006.257.21:37:34.69/vb/08,04,usb,yes,28,32 2006.257.21:37:34.93/vblo/01,629.99,yes,locked 2006.257.21:37:34.93/vblo/02,634.99,yes,locked 2006.257.21:37:34.93/vblo/03,649.99,yes,locked 2006.257.21:37:34.93/vblo/04,679.99,yes,locked 2006.257.21:37:34.93/vblo/05,709.99,yes,locked 2006.257.21:37:34.93/vblo/06,719.99,yes,locked 2006.257.21:37:34.93/vblo/07,734.99,yes,locked 2006.257.21:37:34.93/vblo/08,744.99,yes,locked 2006.257.21:37:35.08/vabw/8 2006.257.21:37:35.23/vbbw/8 2006.257.21:37:35.32/xfe/off,on,15.2 2006.257.21:37:35.70/ifatt/23,28,28,28 2006.257.21:37:36.08/fmout-gps/S +4.58E-07 2006.257.21:37:36.11:!2006.257.21:39:31 2006.257.21:39:31.02:data_valid=off 2006.257.21:39:31.02:"et 2006.257.21:39:31.02:!+3s 2006.257.21:39:34.04:"tape 2006.257.21:39:34.05:postob 2006.257.21:39:34.24/cable/+6.4842E-03 2006.257.21:39:34.25/wx/17.91,1015.4,95 2006.257.21:39:34.30/fmout-gps/S +4.55E-07 2006.257.21:39:34.31:scan_name=257-2143,jd0609,140 2006.257.21:39:34.31:source=3c274,123049.42,122328.0,2000.0,cw 2006.257.21:39:35.15#flagr#flagr/antenna,new-source 2006.257.21:39:35.15:checkk5 2006.257.21:39:35.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.21:39:35.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.21:39:36.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.21:39:36.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.21:39:36.83/chk_obsdata//k5ts1/T2572137??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.257.21:39:37.16/chk_obsdata//k5ts2/T2572137??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.257.21:39:37.49/chk_obsdata//k5ts3/T2572137??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.257.21:39:37.82/chk_obsdata//k5ts4/T2572137??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.257.21:39:38.47/k5log//k5ts1_log_newline 2006.257.21:39:39.14/k5log//k5ts2_log_newline 2006.257.21:39:39.79/k5log//k5ts3_log_newline 2006.257.21:39:40.44/k5log//k5ts4_log_newline 2006.257.21:39:40.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.21:39:40.47:setupk4=1 2006.257.21:39:40.47$setupk4/echo=on 2006.257.21:39:40.47$setupk4/pcalon 2006.257.21:39:40.47$pcalon/"no phase cal control is implemented here 2006.257.21:39:40.47$setupk4/"tpicd=stop 2006.257.21:39:40.47$setupk4/"rec=synch_on 2006.257.21:39:40.47$setupk4/"rec_mode=128 2006.257.21:39:40.47$setupk4/!* 2006.257.21:39:40.47$setupk4/recpk4 2006.257.21:39:40.47$recpk4/recpatch= 2006.257.21:39:40.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.21:39:40.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.21:39:40.47$setupk4/vck44 2006.257.21:39:40.47$vck44/valo=1,524.99 2006.257.21:39:40.47#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.21:39:40.47#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.21:39:40.47#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:40.47#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:40.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:40.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:40.47#ibcon#enter wrdev, iclass 37, count 0 2006.257.21:39:40.47#ibcon#first serial, iclass 37, count 0 2006.257.21:39:40.47#ibcon#enter sib2, iclass 37, count 0 2006.257.21:39:40.47#ibcon#flushed, iclass 37, count 0 2006.257.21:39:40.47#ibcon#about to write, iclass 37, count 0 2006.257.21:39:40.47#ibcon#wrote, iclass 37, count 0 2006.257.21:39:40.47#ibcon#about to read 3, iclass 37, count 0 2006.257.21:39:40.49#ibcon#read 3, iclass 37, count 0 2006.257.21:39:40.49#ibcon#about to read 4, iclass 37, count 0 2006.257.21:39:40.49#ibcon#read 4, iclass 37, count 0 2006.257.21:39:40.49#ibcon#about to read 5, iclass 37, count 0 2006.257.21:39:40.49#ibcon#read 5, iclass 37, count 0 2006.257.21:39:40.49#ibcon#about to read 6, iclass 37, count 0 2006.257.21:39:40.49#ibcon#read 6, iclass 37, count 0 2006.257.21:39:40.49#ibcon#end of sib2, iclass 37, count 0 2006.257.21:39:40.49#ibcon#*mode == 0, iclass 37, count 0 2006.257.21:39:40.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.21:39:40.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.21:39:40.49#ibcon#*before write, iclass 37, count 0 2006.257.21:39:40.49#ibcon#enter sib2, iclass 37, count 0 2006.257.21:39:40.49#ibcon#flushed, iclass 37, count 0 2006.257.21:39:40.49#ibcon#about to write, iclass 37, count 0 2006.257.21:39:40.49#ibcon#wrote, iclass 37, count 0 2006.257.21:39:40.49#ibcon#about to read 3, iclass 37, count 0 2006.257.21:39:40.53#ibcon#read 3, iclass 37, count 0 2006.257.21:39:40.53#ibcon#about to read 4, iclass 37, count 0 2006.257.21:39:40.53#ibcon#read 4, iclass 37, count 0 2006.257.21:39:40.53#ibcon#about to read 5, iclass 37, count 0 2006.257.21:39:40.53#ibcon#read 5, iclass 37, count 0 2006.257.21:39:40.53#ibcon#about to read 6, iclass 37, count 0 2006.257.21:39:40.53#ibcon#read 6, iclass 37, count 0 2006.257.21:39:40.53#ibcon#end of sib2, iclass 37, count 0 2006.257.21:39:40.53#ibcon#*after write, iclass 37, count 0 2006.257.21:39:40.53#ibcon#*before return 0, iclass 37, count 0 2006.257.21:39:40.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:40.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:40.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.21:39:40.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.21:39:40.54$vck44/va=1,8 2006.257.21:39:40.54#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.21:39:40.54#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.21:39:40.54#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:40.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:40.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:40.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:40.54#ibcon#enter wrdev, iclass 39, count 2 2006.257.21:39:40.54#ibcon#first serial, iclass 39, count 2 2006.257.21:39:40.54#ibcon#enter sib2, iclass 39, count 2 2006.257.21:39:40.54#ibcon#flushed, iclass 39, count 2 2006.257.21:39:40.54#ibcon#about to write, iclass 39, count 2 2006.257.21:39:40.54#ibcon#wrote, iclass 39, count 2 2006.257.21:39:40.54#ibcon#about to read 3, iclass 39, count 2 2006.257.21:39:40.55#ibcon#read 3, iclass 39, count 2 2006.257.21:39:40.55#ibcon#about to read 4, iclass 39, count 2 2006.257.21:39:40.55#ibcon#read 4, iclass 39, count 2 2006.257.21:39:40.55#ibcon#about to read 5, iclass 39, count 2 2006.257.21:39:40.55#ibcon#read 5, iclass 39, count 2 2006.257.21:39:40.55#ibcon#about to read 6, iclass 39, count 2 2006.257.21:39:40.55#ibcon#read 6, iclass 39, count 2 2006.257.21:39:40.55#ibcon#end of sib2, iclass 39, count 2 2006.257.21:39:40.55#ibcon#*mode == 0, iclass 39, count 2 2006.257.21:39:40.55#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.21:39:40.55#ibcon#[25=AT01-08\r\n] 2006.257.21:39:40.55#ibcon#*before write, iclass 39, count 2 2006.257.21:39:40.55#ibcon#enter sib2, iclass 39, count 2 2006.257.21:39:40.55#ibcon#flushed, iclass 39, count 2 2006.257.21:39:40.55#ibcon#about to write, iclass 39, count 2 2006.257.21:39:40.56#ibcon#wrote, iclass 39, count 2 2006.257.21:39:40.56#ibcon#about to read 3, iclass 39, count 2 2006.257.21:39:40.58#ibcon#read 3, iclass 39, count 2 2006.257.21:39:40.58#ibcon#about to read 4, iclass 39, count 2 2006.257.21:39:40.58#ibcon#read 4, iclass 39, count 2 2006.257.21:39:40.58#ibcon#about to read 5, iclass 39, count 2 2006.257.21:39:40.58#ibcon#read 5, iclass 39, count 2 2006.257.21:39:40.58#ibcon#about to read 6, iclass 39, count 2 2006.257.21:39:40.58#ibcon#read 6, iclass 39, count 2 2006.257.21:39:40.58#ibcon#end of sib2, iclass 39, count 2 2006.257.21:39:40.58#ibcon#*after write, iclass 39, count 2 2006.257.21:39:40.58#ibcon#*before return 0, iclass 39, count 2 2006.257.21:39:40.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:40.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:40.58#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.21:39:40.58#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:40.59#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:40.69#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:40.69#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:40.69#ibcon#enter wrdev, iclass 39, count 0 2006.257.21:39:40.69#ibcon#first serial, iclass 39, count 0 2006.257.21:39:40.69#ibcon#enter sib2, iclass 39, count 0 2006.257.21:39:40.69#ibcon#flushed, iclass 39, count 0 2006.257.21:39:40.69#ibcon#about to write, iclass 39, count 0 2006.257.21:39:40.69#ibcon#wrote, iclass 39, count 0 2006.257.21:39:40.69#ibcon#about to read 3, iclass 39, count 0 2006.257.21:39:40.71#ibcon#read 3, iclass 39, count 0 2006.257.21:39:40.71#ibcon#about to read 4, iclass 39, count 0 2006.257.21:39:40.71#ibcon#read 4, iclass 39, count 0 2006.257.21:39:40.71#ibcon#about to read 5, iclass 39, count 0 2006.257.21:39:40.71#ibcon#read 5, iclass 39, count 0 2006.257.21:39:40.71#ibcon#about to read 6, iclass 39, count 0 2006.257.21:39:40.71#ibcon#read 6, iclass 39, count 0 2006.257.21:39:40.71#ibcon#end of sib2, iclass 39, count 0 2006.257.21:39:40.71#ibcon#*mode == 0, iclass 39, count 0 2006.257.21:39:40.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.21:39:40.71#ibcon#[25=USB\r\n] 2006.257.21:39:40.71#ibcon#*before write, iclass 39, count 0 2006.257.21:39:40.71#ibcon#enter sib2, iclass 39, count 0 2006.257.21:39:40.71#ibcon#flushed, iclass 39, count 0 2006.257.21:39:40.71#ibcon#about to write, iclass 39, count 0 2006.257.21:39:40.72#ibcon#wrote, iclass 39, count 0 2006.257.21:39:40.72#ibcon#about to read 3, iclass 39, count 0 2006.257.21:39:40.74#ibcon#read 3, iclass 39, count 0 2006.257.21:39:40.74#ibcon#about to read 4, iclass 39, count 0 2006.257.21:39:40.74#ibcon#read 4, iclass 39, count 0 2006.257.21:39:40.74#ibcon#about to read 5, iclass 39, count 0 2006.257.21:39:40.74#ibcon#read 5, iclass 39, count 0 2006.257.21:39:40.74#ibcon#about to read 6, iclass 39, count 0 2006.257.21:39:40.74#ibcon#read 6, iclass 39, count 0 2006.257.21:39:40.74#ibcon#end of sib2, iclass 39, count 0 2006.257.21:39:40.74#ibcon#*after write, iclass 39, count 0 2006.257.21:39:40.74#ibcon#*before return 0, iclass 39, count 0 2006.257.21:39:40.74#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:40.74#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:40.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.21:39:40.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.21:39:40.75$vck44/valo=2,534.99 2006.257.21:39:40.75#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.21:39:40.75#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.21:39:40.75#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:40.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:40.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:40.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:40.75#ibcon#enter wrdev, iclass 3, count 0 2006.257.21:39:40.75#ibcon#first serial, iclass 3, count 0 2006.257.21:39:40.75#ibcon#enter sib2, iclass 3, count 0 2006.257.21:39:40.75#ibcon#flushed, iclass 3, count 0 2006.257.21:39:40.75#ibcon#about to write, iclass 3, count 0 2006.257.21:39:40.75#ibcon#wrote, iclass 3, count 0 2006.257.21:39:40.75#ibcon#about to read 3, iclass 3, count 0 2006.257.21:39:40.76#ibcon#read 3, iclass 3, count 0 2006.257.21:39:40.76#ibcon#about to read 4, iclass 3, count 0 2006.257.21:39:40.76#ibcon#read 4, iclass 3, count 0 2006.257.21:39:40.76#ibcon#about to read 5, iclass 3, count 0 2006.257.21:39:40.76#ibcon#read 5, iclass 3, count 0 2006.257.21:39:40.76#ibcon#about to read 6, iclass 3, count 0 2006.257.21:39:40.76#ibcon#read 6, iclass 3, count 0 2006.257.21:39:40.76#ibcon#end of sib2, iclass 3, count 0 2006.257.21:39:40.76#ibcon#*mode == 0, iclass 3, count 0 2006.257.21:39:40.76#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.21:39:40.76#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.21:39:40.76#ibcon#*before write, iclass 3, count 0 2006.257.21:39:40.76#ibcon#enter sib2, iclass 3, count 0 2006.257.21:39:40.76#ibcon#flushed, iclass 3, count 0 2006.257.21:39:40.76#ibcon#about to write, iclass 3, count 0 2006.257.21:39:40.77#ibcon#wrote, iclass 3, count 0 2006.257.21:39:40.77#ibcon#about to read 3, iclass 3, count 0 2006.257.21:39:40.80#ibcon#read 3, iclass 3, count 0 2006.257.21:39:40.80#ibcon#about to read 4, iclass 3, count 0 2006.257.21:39:40.80#ibcon#read 4, iclass 3, count 0 2006.257.21:39:40.80#ibcon#about to read 5, iclass 3, count 0 2006.257.21:39:40.80#ibcon#read 5, iclass 3, count 0 2006.257.21:39:40.80#ibcon#about to read 6, iclass 3, count 0 2006.257.21:39:40.80#ibcon#read 6, iclass 3, count 0 2006.257.21:39:40.80#ibcon#end of sib2, iclass 3, count 0 2006.257.21:39:40.80#ibcon#*after write, iclass 3, count 0 2006.257.21:39:40.80#ibcon#*before return 0, iclass 3, count 0 2006.257.21:39:40.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:40.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:40.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.21:39:40.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.21:39:40.81$vck44/va=2,7 2006.257.21:39:40.81#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.21:39:40.81#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.21:39:40.81#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:40.81#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:40.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:40.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:40.85#ibcon#enter wrdev, iclass 5, count 2 2006.257.21:39:40.85#ibcon#first serial, iclass 5, count 2 2006.257.21:39:40.85#ibcon#enter sib2, iclass 5, count 2 2006.257.21:39:40.85#ibcon#flushed, iclass 5, count 2 2006.257.21:39:40.85#ibcon#about to write, iclass 5, count 2 2006.257.21:39:40.85#ibcon#wrote, iclass 5, count 2 2006.257.21:39:40.85#ibcon#about to read 3, iclass 5, count 2 2006.257.21:39:40.87#ibcon#read 3, iclass 5, count 2 2006.257.21:39:40.87#ibcon#about to read 4, iclass 5, count 2 2006.257.21:39:40.87#ibcon#read 4, iclass 5, count 2 2006.257.21:39:40.87#ibcon#about to read 5, iclass 5, count 2 2006.257.21:39:40.87#ibcon#read 5, iclass 5, count 2 2006.257.21:39:40.87#ibcon#about to read 6, iclass 5, count 2 2006.257.21:39:40.87#ibcon#read 6, iclass 5, count 2 2006.257.21:39:40.87#ibcon#end of sib2, iclass 5, count 2 2006.257.21:39:40.87#ibcon#*mode == 0, iclass 5, count 2 2006.257.21:39:40.87#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.21:39:40.87#ibcon#[25=AT02-07\r\n] 2006.257.21:39:40.87#ibcon#*before write, iclass 5, count 2 2006.257.21:39:40.87#ibcon#enter sib2, iclass 5, count 2 2006.257.21:39:40.87#ibcon#flushed, iclass 5, count 2 2006.257.21:39:40.87#ibcon#about to write, iclass 5, count 2 2006.257.21:39:40.88#ibcon#wrote, iclass 5, count 2 2006.257.21:39:40.88#ibcon#about to read 3, iclass 5, count 2 2006.257.21:39:40.90#ibcon#read 3, iclass 5, count 2 2006.257.21:39:40.90#ibcon#about to read 4, iclass 5, count 2 2006.257.21:39:40.90#ibcon#read 4, iclass 5, count 2 2006.257.21:39:40.90#ibcon#about to read 5, iclass 5, count 2 2006.257.21:39:40.90#ibcon#read 5, iclass 5, count 2 2006.257.21:39:40.90#ibcon#about to read 6, iclass 5, count 2 2006.257.21:39:40.90#ibcon#read 6, iclass 5, count 2 2006.257.21:39:40.90#ibcon#end of sib2, iclass 5, count 2 2006.257.21:39:40.90#ibcon#*after write, iclass 5, count 2 2006.257.21:39:40.90#ibcon#*before return 0, iclass 5, count 2 2006.257.21:39:40.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:40.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:40.90#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.21:39:40.90#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:40.91#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:41.02#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:41.02#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:41.02#ibcon#enter wrdev, iclass 5, count 0 2006.257.21:39:41.02#ibcon#first serial, iclass 5, count 0 2006.257.21:39:41.02#ibcon#enter sib2, iclass 5, count 0 2006.257.21:39:41.02#ibcon#flushed, iclass 5, count 0 2006.257.21:39:41.02#ibcon#about to write, iclass 5, count 0 2006.257.21:39:41.02#ibcon#wrote, iclass 5, count 0 2006.257.21:39:41.02#ibcon#about to read 3, iclass 5, count 0 2006.257.21:39:41.03#ibcon#read 3, iclass 5, count 0 2006.257.21:39:41.03#ibcon#about to read 4, iclass 5, count 0 2006.257.21:39:41.03#ibcon#read 4, iclass 5, count 0 2006.257.21:39:41.03#ibcon#about to read 5, iclass 5, count 0 2006.257.21:39:41.03#ibcon#read 5, iclass 5, count 0 2006.257.21:39:41.03#ibcon#about to read 6, iclass 5, count 0 2006.257.21:39:41.03#ibcon#read 6, iclass 5, count 0 2006.257.21:39:41.03#ibcon#end of sib2, iclass 5, count 0 2006.257.21:39:41.03#ibcon#*mode == 0, iclass 5, count 0 2006.257.21:39:41.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.21:39:41.03#ibcon#[25=USB\r\n] 2006.257.21:39:41.03#ibcon#*before write, iclass 5, count 0 2006.257.21:39:41.03#ibcon#enter sib2, iclass 5, count 0 2006.257.21:39:41.03#ibcon#flushed, iclass 5, count 0 2006.257.21:39:41.03#ibcon#about to write, iclass 5, count 0 2006.257.21:39:41.04#ibcon#wrote, iclass 5, count 0 2006.257.21:39:41.04#ibcon#about to read 3, iclass 5, count 0 2006.257.21:39:41.06#ibcon#read 3, iclass 5, count 0 2006.257.21:39:41.06#ibcon#about to read 4, iclass 5, count 0 2006.257.21:39:41.06#ibcon#read 4, iclass 5, count 0 2006.257.21:39:41.06#ibcon#about to read 5, iclass 5, count 0 2006.257.21:39:41.06#ibcon#read 5, iclass 5, count 0 2006.257.21:39:41.06#ibcon#about to read 6, iclass 5, count 0 2006.257.21:39:41.06#ibcon#read 6, iclass 5, count 0 2006.257.21:39:41.06#ibcon#end of sib2, iclass 5, count 0 2006.257.21:39:41.06#ibcon#*after write, iclass 5, count 0 2006.257.21:39:41.06#ibcon#*before return 0, iclass 5, count 0 2006.257.21:39:41.06#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:41.06#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:41.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.21:39:41.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.21:39:41.07$vck44/valo=3,564.99 2006.257.21:39:41.07#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.21:39:41.07#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.21:39:41.07#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:41.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:41.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:41.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:41.07#ibcon#enter wrdev, iclass 7, count 0 2006.257.21:39:41.07#ibcon#first serial, iclass 7, count 0 2006.257.21:39:41.07#ibcon#enter sib2, iclass 7, count 0 2006.257.21:39:41.07#ibcon#flushed, iclass 7, count 0 2006.257.21:39:41.07#ibcon#about to write, iclass 7, count 0 2006.257.21:39:41.07#ibcon#wrote, iclass 7, count 0 2006.257.21:39:41.07#ibcon#about to read 3, iclass 7, count 0 2006.257.21:39:41.08#ibcon#read 3, iclass 7, count 0 2006.257.21:39:41.08#ibcon#about to read 4, iclass 7, count 0 2006.257.21:39:41.08#ibcon#read 4, iclass 7, count 0 2006.257.21:39:41.08#ibcon#about to read 5, iclass 7, count 0 2006.257.21:39:41.08#ibcon#read 5, iclass 7, count 0 2006.257.21:39:41.08#ibcon#about to read 6, iclass 7, count 0 2006.257.21:39:41.08#ibcon#read 6, iclass 7, count 0 2006.257.21:39:41.08#ibcon#end of sib2, iclass 7, count 0 2006.257.21:39:41.08#ibcon#*mode == 0, iclass 7, count 0 2006.257.21:39:41.08#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.21:39:41.08#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.21:39:41.08#ibcon#*before write, iclass 7, count 0 2006.257.21:39:41.08#ibcon#enter sib2, iclass 7, count 0 2006.257.21:39:41.08#ibcon#flushed, iclass 7, count 0 2006.257.21:39:41.08#ibcon#about to write, iclass 7, count 0 2006.257.21:39:41.09#ibcon#wrote, iclass 7, count 0 2006.257.21:39:41.09#ibcon#about to read 3, iclass 7, count 0 2006.257.21:39:41.12#ibcon#read 3, iclass 7, count 0 2006.257.21:39:41.12#ibcon#about to read 4, iclass 7, count 0 2006.257.21:39:41.12#ibcon#read 4, iclass 7, count 0 2006.257.21:39:41.12#ibcon#about to read 5, iclass 7, count 0 2006.257.21:39:41.12#ibcon#read 5, iclass 7, count 0 2006.257.21:39:41.12#ibcon#about to read 6, iclass 7, count 0 2006.257.21:39:41.12#ibcon#read 6, iclass 7, count 0 2006.257.21:39:41.12#ibcon#end of sib2, iclass 7, count 0 2006.257.21:39:41.12#ibcon#*after write, iclass 7, count 0 2006.257.21:39:41.12#ibcon#*before return 0, iclass 7, count 0 2006.257.21:39:41.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:41.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:41.12#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.21:39:41.12#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.21:39:41.13$vck44/va=3,8 2006.257.21:39:41.13#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.21:39:41.13#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.21:39:41.13#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:41.13#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:41.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:41.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:41.17#ibcon#enter wrdev, iclass 11, count 2 2006.257.21:39:41.17#ibcon#first serial, iclass 11, count 2 2006.257.21:39:41.17#ibcon#enter sib2, iclass 11, count 2 2006.257.21:39:41.17#ibcon#flushed, iclass 11, count 2 2006.257.21:39:41.17#ibcon#about to write, iclass 11, count 2 2006.257.21:39:41.17#ibcon#wrote, iclass 11, count 2 2006.257.21:39:41.17#ibcon#about to read 3, iclass 11, count 2 2006.257.21:39:41.19#ibcon#read 3, iclass 11, count 2 2006.257.21:39:41.19#ibcon#about to read 4, iclass 11, count 2 2006.257.21:39:41.19#ibcon#read 4, iclass 11, count 2 2006.257.21:39:41.19#ibcon#about to read 5, iclass 11, count 2 2006.257.21:39:41.19#ibcon#read 5, iclass 11, count 2 2006.257.21:39:41.19#ibcon#about to read 6, iclass 11, count 2 2006.257.21:39:41.19#ibcon#read 6, iclass 11, count 2 2006.257.21:39:41.19#ibcon#end of sib2, iclass 11, count 2 2006.257.21:39:41.19#ibcon#*mode == 0, iclass 11, count 2 2006.257.21:39:41.19#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.21:39:41.19#ibcon#[25=AT03-08\r\n] 2006.257.21:39:41.19#ibcon#*before write, iclass 11, count 2 2006.257.21:39:41.19#ibcon#enter sib2, iclass 11, count 2 2006.257.21:39:41.19#ibcon#flushed, iclass 11, count 2 2006.257.21:39:41.19#ibcon#about to write, iclass 11, count 2 2006.257.21:39:41.20#ibcon#wrote, iclass 11, count 2 2006.257.21:39:41.20#ibcon#about to read 3, iclass 11, count 2 2006.257.21:39:41.22#ibcon#read 3, iclass 11, count 2 2006.257.21:39:41.22#ibcon#about to read 4, iclass 11, count 2 2006.257.21:39:41.22#ibcon#read 4, iclass 11, count 2 2006.257.21:39:41.22#ibcon#about to read 5, iclass 11, count 2 2006.257.21:39:41.22#ibcon#read 5, iclass 11, count 2 2006.257.21:39:41.22#ibcon#about to read 6, iclass 11, count 2 2006.257.21:39:41.22#ibcon#read 6, iclass 11, count 2 2006.257.21:39:41.22#ibcon#end of sib2, iclass 11, count 2 2006.257.21:39:41.22#ibcon#*after write, iclass 11, count 2 2006.257.21:39:41.22#ibcon#*before return 0, iclass 11, count 2 2006.257.21:39:41.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:41.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:41.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.21:39:41.22#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:41.23#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:41.33#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:41.33#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:41.33#ibcon#enter wrdev, iclass 11, count 0 2006.257.21:39:41.33#ibcon#first serial, iclass 11, count 0 2006.257.21:39:41.33#ibcon#enter sib2, iclass 11, count 0 2006.257.21:39:41.33#ibcon#flushed, iclass 11, count 0 2006.257.21:39:41.33#ibcon#about to write, iclass 11, count 0 2006.257.21:39:41.33#ibcon#wrote, iclass 11, count 0 2006.257.21:39:41.33#ibcon#about to read 3, iclass 11, count 0 2006.257.21:39:41.35#ibcon#read 3, iclass 11, count 0 2006.257.21:39:41.35#ibcon#about to read 4, iclass 11, count 0 2006.257.21:39:41.35#ibcon#read 4, iclass 11, count 0 2006.257.21:39:41.35#ibcon#about to read 5, iclass 11, count 0 2006.257.21:39:41.35#ibcon#read 5, iclass 11, count 0 2006.257.21:39:41.35#ibcon#about to read 6, iclass 11, count 0 2006.257.21:39:41.35#ibcon#read 6, iclass 11, count 0 2006.257.21:39:41.35#ibcon#end of sib2, iclass 11, count 0 2006.257.21:39:41.35#ibcon#*mode == 0, iclass 11, count 0 2006.257.21:39:41.35#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.21:39:41.35#ibcon#[25=USB\r\n] 2006.257.21:39:41.35#ibcon#*before write, iclass 11, count 0 2006.257.21:39:41.35#ibcon#enter sib2, iclass 11, count 0 2006.257.21:39:41.35#ibcon#flushed, iclass 11, count 0 2006.257.21:39:41.35#ibcon#about to write, iclass 11, count 0 2006.257.21:39:41.36#ibcon#wrote, iclass 11, count 0 2006.257.21:39:41.36#ibcon#about to read 3, iclass 11, count 0 2006.257.21:39:41.38#ibcon#read 3, iclass 11, count 0 2006.257.21:39:41.38#ibcon#about to read 4, iclass 11, count 0 2006.257.21:39:41.38#ibcon#read 4, iclass 11, count 0 2006.257.21:39:41.38#ibcon#about to read 5, iclass 11, count 0 2006.257.21:39:41.38#ibcon#read 5, iclass 11, count 0 2006.257.21:39:41.38#ibcon#about to read 6, iclass 11, count 0 2006.257.21:39:41.38#ibcon#read 6, iclass 11, count 0 2006.257.21:39:41.38#ibcon#end of sib2, iclass 11, count 0 2006.257.21:39:41.38#ibcon#*after write, iclass 11, count 0 2006.257.21:39:41.38#ibcon#*before return 0, iclass 11, count 0 2006.257.21:39:41.38#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:41.38#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:41.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.21:39:41.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.21:39:41.39$vck44/valo=4,624.99 2006.257.21:39:41.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.21:39:41.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.21:39:41.39#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:41.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:41.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:41.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:41.39#ibcon#enter wrdev, iclass 13, count 0 2006.257.21:39:41.39#ibcon#first serial, iclass 13, count 0 2006.257.21:39:41.39#ibcon#enter sib2, iclass 13, count 0 2006.257.21:39:41.39#ibcon#flushed, iclass 13, count 0 2006.257.21:39:41.39#ibcon#about to write, iclass 13, count 0 2006.257.21:39:41.39#ibcon#wrote, iclass 13, count 0 2006.257.21:39:41.39#ibcon#about to read 3, iclass 13, count 0 2006.257.21:39:41.40#ibcon#read 3, iclass 13, count 0 2006.257.21:39:41.40#ibcon#about to read 4, iclass 13, count 0 2006.257.21:39:41.40#ibcon#read 4, iclass 13, count 0 2006.257.21:39:41.40#ibcon#about to read 5, iclass 13, count 0 2006.257.21:39:41.40#ibcon#read 5, iclass 13, count 0 2006.257.21:39:41.40#ibcon#about to read 6, iclass 13, count 0 2006.257.21:39:41.40#ibcon#read 6, iclass 13, count 0 2006.257.21:39:41.40#ibcon#end of sib2, iclass 13, count 0 2006.257.21:39:41.40#ibcon#*mode == 0, iclass 13, count 0 2006.257.21:39:41.40#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.21:39:41.40#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.21:39:41.40#ibcon#*before write, iclass 13, count 0 2006.257.21:39:41.40#ibcon#enter sib2, iclass 13, count 0 2006.257.21:39:41.40#ibcon#flushed, iclass 13, count 0 2006.257.21:39:41.40#ibcon#about to write, iclass 13, count 0 2006.257.21:39:41.41#ibcon#wrote, iclass 13, count 0 2006.257.21:39:41.41#ibcon#about to read 3, iclass 13, count 0 2006.257.21:39:41.44#ibcon#read 3, iclass 13, count 0 2006.257.21:39:41.44#ibcon#about to read 4, iclass 13, count 0 2006.257.21:39:41.44#ibcon#read 4, iclass 13, count 0 2006.257.21:39:41.44#ibcon#about to read 5, iclass 13, count 0 2006.257.21:39:41.44#ibcon#read 5, iclass 13, count 0 2006.257.21:39:41.44#ibcon#about to read 6, iclass 13, count 0 2006.257.21:39:41.44#ibcon#read 6, iclass 13, count 0 2006.257.21:39:41.44#ibcon#end of sib2, iclass 13, count 0 2006.257.21:39:41.44#ibcon#*after write, iclass 13, count 0 2006.257.21:39:41.44#ibcon#*before return 0, iclass 13, count 0 2006.257.21:39:41.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:41.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:41.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.21:39:41.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.21:39:41.45$vck44/va=4,7 2006.257.21:39:41.45#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.21:39:41.45#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.21:39:41.45#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:41.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:41.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:41.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:41.49#ibcon#enter wrdev, iclass 15, count 2 2006.257.21:39:41.49#ibcon#first serial, iclass 15, count 2 2006.257.21:39:41.49#ibcon#enter sib2, iclass 15, count 2 2006.257.21:39:41.49#ibcon#flushed, iclass 15, count 2 2006.257.21:39:41.49#ibcon#about to write, iclass 15, count 2 2006.257.21:39:41.49#ibcon#wrote, iclass 15, count 2 2006.257.21:39:41.49#ibcon#about to read 3, iclass 15, count 2 2006.257.21:39:41.51#ibcon#read 3, iclass 15, count 2 2006.257.21:39:41.51#ibcon#about to read 4, iclass 15, count 2 2006.257.21:39:41.51#ibcon#read 4, iclass 15, count 2 2006.257.21:39:41.51#ibcon#about to read 5, iclass 15, count 2 2006.257.21:39:41.51#ibcon#read 5, iclass 15, count 2 2006.257.21:39:41.51#ibcon#about to read 6, iclass 15, count 2 2006.257.21:39:41.51#ibcon#read 6, iclass 15, count 2 2006.257.21:39:41.51#ibcon#end of sib2, iclass 15, count 2 2006.257.21:39:41.51#ibcon#*mode == 0, iclass 15, count 2 2006.257.21:39:41.51#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.21:39:41.51#ibcon#[25=AT04-07\r\n] 2006.257.21:39:41.51#ibcon#*before write, iclass 15, count 2 2006.257.21:39:41.51#ibcon#enter sib2, iclass 15, count 2 2006.257.21:39:41.51#ibcon#flushed, iclass 15, count 2 2006.257.21:39:41.51#ibcon#about to write, iclass 15, count 2 2006.257.21:39:41.52#ibcon#wrote, iclass 15, count 2 2006.257.21:39:41.52#ibcon#about to read 3, iclass 15, count 2 2006.257.21:39:41.54#ibcon#read 3, iclass 15, count 2 2006.257.21:39:41.54#ibcon#about to read 4, iclass 15, count 2 2006.257.21:39:41.54#ibcon#read 4, iclass 15, count 2 2006.257.21:39:41.54#ibcon#about to read 5, iclass 15, count 2 2006.257.21:39:41.54#ibcon#read 5, iclass 15, count 2 2006.257.21:39:41.54#ibcon#about to read 6, iclass 15, count 2 2006.257.21:39:41.54#ibcon#read 6, iclass 15, count 2 2006.257.21:39:41.54#ibcon#end of sib2, iclass 15, count 2 2006.257.21:39:41.54#ibcon#*after write, iclass 15, count 2 2006.257.21:39:41.54#ibcon#*before return 0, iclass 15, count 2 2006.257.21:39:41.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:41.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:41.54#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.21:39:41.54#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:41.55#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:41.65#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:41.65#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:41.65#ibcon#enter wrdev, iclass 15, count 0 2006.257.21:39:41.65#ibcon#first serial, iclass 15, count 0 2006.257.21:39:41.65#ibcon#enter sib2, iclass 15, count 0 2006.257.21:39:41.65#ibcon#flushed, iclass 15, count 0 2006.257.21:39:41.65#ibcon#about to write, iclass 15, count 0 2006.257.21:39:41.65#ibcon#wrote, iclass 15, count 0 2006.257.21:39:41.65#ibcon#about to read 3, iclass 15, count 0 2006.257.21:39:41.67#ibcon#read 3, iclass 15, count 0 2006.257.21:39:41.67#ibcon#about to read 4, iclass 15, count 0 2006.257.21:39:41.67#ibcon#read 4, iclass 15, count 0 2006.257.21:39:41.67#ibcon#about to read 5, iclass 15, count 0 2006.257.21:39:41.67#ibcon#read 5, iclass 15, count 0 2006.257.21:39:41.67#ibcon#about to read 6, iclass 15, count 0 2006.257.21:39:41.67#ibcon#read 6, iclass 15, count 0 2006.257.21:39:41.67#ibcon#end of sib2, iclass 15, count 0 2006.257.21:39:41.67#ibcon#*mode == 0, iclass 15, count 0 2006.257.21:39:41.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.21:39:41.67#ibcon#[25=USB\r\n] 2006.257.21:39:41.67#ibcon#*before write, iclass 15, count 0 2006.257.21:39:41.67#ibcon#enter sib2, iclass 15, count 0 2006.257.21:39:41.67#ibcon#flushed, iclass 15, count 0 2006.257.21:39:41.67#ibcon#about to write, iclass 15, count 0 2006.257.21:39:41.68#ibcon#wrote, iclass 15, count 0 2006.257.21:39:41.68#ibcon#about to read 3, iclass 15, count 0 2006.257.21:39:41.70#ibcon#read 3, iclass 15, count 0 2006.257.21:39:41.70#ibcon#about to read 4, iclass 15, count 0 2006.257.21:39:41.70#ibcon#read 4, iclass 15, count 0 2006.257.21:39:41.70#ibcon#about to read 5, iclass 15, count 0 2006.257.21:39:41.70#ibcon#read 5, iclass 15, count 0 2006.257.21:39:41.70#ibcon#about to read 6, iclass 15, count 0 2006.257.21:39:41.70#ibcon#read 6, iclass 15, count 0 2006.257.21:39:41.70#ibcon#end of sib2, iclass 15, count 0 2006.257.21:39:41.70#ibcon#*after write, iclass 15, count 0 2006.257.21:39:41.70#ibcon#*before return 0, iclass 15, count 0 2006.257.21:39:41.70#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:41.70#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:41.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.21:39:41.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.21:39:41.71$vck44/valo=5,734.99 2006.257.21:39:41.71#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.21:39:41.71#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.21:39:41.71#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:41.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:41.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:41.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:41.71#ibcon#enter wrdev, iclass 17, count 0 2006.257.21:39:41.71#ibcon#first serial, iclass 17, count 0 2006.257.21:39:41.71#ibcon#enter sib2, iclass 17, count 0 2006.257.21:39:41.71#ibcon#flushed, iclass 17, count 0 2006.257.21:39:41.71#ibcon#about to write, iclass 17, count 0 2006.257.21:39:41.71#ibcon#wrote, iclass 17, count 0 2006.257.21:39:41.71#ibcon#about to read 3, iclass 17, count 0 2006.257.21:39:41.72#ibcon#read 3, iclass 17, count 0 2006.257.21:39:41.72#ibcon#about to read 4, iclass 17, count 0 2006.257.21:39:41.72#ibcon#read 4, iclass 17, count 0 2006.257.21:39:41.72#ibcon#about to read 5, iclass 17, count 0 2006.257.21:39:41.72#ibcon#read 5, iclass 17, count 0 2006.257.21:39:41.72#ibcon#about to read 6, iclass 17, count 0 2006.257.21:39:41.72#ibcon#read 6, iclass 17, count 0 2006.257.21:39:41.72#ibcon#end of sib2, iclass 17, count 0 2006.257.21:39:41.72#ibcon#*mode == 0, iclass 17, count 0 2006.257.21:39:41.72#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.21:39:41.72#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.21:39:41.72#ibcon#*before write, iclass 17, count 0 2006.257.21:39:41.72#ibcon#enter sib2, iclass 17, count 0 2006.257.21:39:41.72#ibcon#flushed, iclass 17, count 0 2006.257.21:39:41.72#ibcon#about to write, iclass 17, count 0 2006.257.21:39:41.73#ibcon#wrote, iclass 17, count 0 2006.257.21:39:41.73#ibcon#about to read 3, iclass 17, count 0 2006.257.21:39:41.76#ibcon#read 3, iclass 17, count 0 2006.257.21:39:41.76#ibcon#about to read 4, iclass 17, count 0 2006.257.21:39:41.76#ibcon#read 4, iclass 17, count 0 2006.257.21:39:41.76#ibcon#about to read 5, iclass 17, count 0 2006.257.21:39:41.76#ibcon#read 5, iclass 17, count 0 2006.257.21:39:41.76#ibcon#about to read 6, iclass 17, count 0 2006.257.21:39:41.76#ibcon#read 6, iclass 17, count 0 2006.257.21:39:41.76#ibcon#end of sib2, iclass 17, count 0 2006.257.21:39:41.76#ibcon#*after write, iclass 17, count 0 2006.257.21:39:41.76#ibcon#*before return 0, iclass 17, count 0 2006.257.21:39:41.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:41.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:41.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.21:39:41.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.21:39:41.77$vck44/va=5,4 2006.257.21:39:41.77#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.21:39:41.77#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.21:39:41.77#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:41.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:41.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:41.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:41.81#ibcon#enter wrdev, iclass 19, count 2 2006.257.21:39:41.81#ibcon#first serial, iclass 19, count 2 2006.257.21:39:41.81#ibcon#enter sib2, iclass 19, count 2 2006.257.21:39:41.81#ibcon#flushed, iclass 19, count 2 2006.257.21:39:41.81#ibcon#about to write, iclass 19, count 2 2006.257.21:39:41.81#ibcon#wrote, iclass 19, count 2 2006.257.21:39:41.81#ibcon#about to read 3, iclass 19, count 2 2006.257.21:39:41.83#ibcon#read 3, iclass 19, count 2 2006.257.21:39:41.83#ibcon#about to read 4, iclass 19, count 2 2006.257.21:39:41.83#ibcon#read 4, iclass 19, count 2 2006.257.21:39:41.83#ibcon#about to read 5, iclass 19, count 2 2006.257.21:39:41.83#ibcon#read 5, iclass 19, count 2 2006.257.21:39:41.83#ibcon#about to read 6, iclass 19, count 2 2006.257.21:39:41.83#ibcon#read 6, iclass 19, count 2 2006.257.21:39:41.83#ibcon#end of sib2, iclass 19, count 2 2006.257.21:39:41.83#ibcon#*mode == 0, iclass 19, count 2 2006.257.21:39:41.83#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.21:39:41.83#ibcon#[25=AT05-04\r\n] 2006.257.21:39:41.83#ibcon#*before write, iclass 19, count 2 2006.257.21:39:41.83#ibcon#enter sib2, iclass 19, count 2 2006.257.21:39:41.83#ibcon#flushed, iclass 19, count 2 2006.257.21:39:41.83#ibcon#about to write, iclass 19, count 2 2006.257.21:39:41.84#ibcon#wrote, iclass 19, count 2 2006.257.21:39:41.84#ibcon#about to read 3, iclass 19, count 2 2006.257.21:39:41.86#ibcon#read 3, iclass 19, count 2 2006.257.21:39:41.86#ibcon#about to read 4, iclass 19, count 2 2006.257.21:39:41.86#ibcon#read 4, iclass 19, count 2 2006.257.21:39:41.86#ibcon#about to read 5, iclass 19, count 2 2006.257.21:39:41.86#ibcon#read 5, iclass 19, count 2 2006.257.21:39:41.86#ibcon#about to read 6, iclass 19, count 2 2006.257.21:39:41.86#ibcon#read 6, iclass 19, count 2 2006.257.21:39:41.86#ibcon#end of sib2, iclass 19, count 2 2006.257.21:39:41.86#ibcon#*after write, iclass 19, count 2 2006.257.21:39:41.86#ibcon#*before return 0, iclass 19, count 2 2006.257.21:39:41.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:41.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:41.86#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.21:39:41.86#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:41.87#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:41.97#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:41.97#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:41.97#ibcon#enter wrdev, iclass 19, count 0 2006.257.21:39:41.97#ibcon#first serial, iclass 19, count 0 2006.257.21:39:41.97#ibcon#enter sib2, iclass 19, count 0 2006.257.21:39:41.97#ibcon#flushed, iclass 19, count 0 2006.257.21:39:41.97#ibcon#about to write, iclass 19, count 0 2006.257.21:39:41.97#ibcon#wrote, iclass 19, count 0 2006.257.21:39:41.97#ibcon#about to read 3, iclass 19, count 0 2006.257.21:39:41.99#ibcon#read 3, iclass 19, count 0 2006.257.21:39:41.99#ibcon#about to read 4, iclass 19, count 0 2006.257.21:39:41.99#ibcon#read 4, iclass 19, count 0 2006.257.21:39:41.99#ibcon#about to read 5, iclass 19, count 0 2006.257.21:39:41.99#ibcon#read 5, iclass 19, count 0 2006.257.21:39:41.99#ibcon#about to read 6, iclass 19, count 0 2006.257.21:39:41.99#ibcon#read 6, iclass 19, count 0 2006.257.21:39:41.99#ibcon#end of sib2, iclass 19, count 0 2006.257.21:39:41.99#ibcon#*mode == 0, iclass 19, count 0 2006.257.21:39:41.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.21:39:41.99#ibcon#[25=USB\r\n] 2006.257.21:39:41.99#ibcon#*before write, iclass 19, count 0 2006.257.21:39:41.99#ibcon#enter sib2, iclass 19, count 0 2006.257.21:39:41.99#ibcon#flushed, iclass 19, count 0 2006.257.21:39:41.99#ibcon#about to write, iclass 19, count 0 2006.257.21:39:42.00#ibcon#wrote, iclass 19, count 0 2006.257.21:39:42.00#ibcon#about to read 3, iclass 19, count 0 2006.257.21:39:42.02#ibcon#read 3, iclass 19, count 0 2006.257.21:39:42.02#ibcon#about to read 4, iclass 19, count 0 2006.257.21:39:42.02#ibcon#read 4, iclass 19, count 0 2006.257.21:39:42.02#ibcon#about to read 5, iclass 19, count 0 2006.257.21:39:42.02#ibcon#read 5, iclass 19, count 0 2006.257.21:39:42.02#ibcon#about to read 6, iclass 19, count 0 2006.257.21:39:42.02#ibcon#read 6, iclass 19, count 0 2006.257.21:39:42.02#ibcon#end of sib2, iclass 19, count 0 2006.257.21:39:42.02#ibcon#*after write, iclass 19, count 0 2006.257.21:39:42.02#ibcon#*before return 0, iclass 19, count 0 2006.257.21:39:42.02#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:42.02#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:42.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.21:39:42.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.21:39:42.03$vck44/valo=6,814.99 2006.257.21:39:42.03#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.21:39:42.03#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.21:39:42.03#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:42.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:42.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:42.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:42.03#ibcon#enter wrdev, iclass 21, count 0 2006.257.21:39:42.03#ibcon#first serial, iclass 21, count 0 2006.257.21:39:42.03#ibcon#enter sib2, iclass 21, count 0 2006.257.21:39:42.03#ibcon#flushed, iclass 21, count 0 2006.257.21:39:42.03#ibcon#about to write, iclass 21, count 0 2006.257.21:39:42.03#ibcon#wrote, iclass 21, count 0 2006.257.21:39:42.03#ibcon#about to read 3, iclass 21, count 0 2006.257.21:39:42.04#ibcon#read 3, iclass 21, count 0 2006.257.21:39:42.04#ibcon#about to read 4, iclass 21, count 0 2006.257.21:39:42.04#ibcon#read 4, iclass 21, count 0 2006.257.21:39:42.04#ibcon#about to read 5, iclass 21, count 0 2006.257.21:39:42.04#ibcon#read 5, iclass 21, count 0 2006.257.21:39:42.04#ibcon#about to read 6, iclass 21, count 0 2006.257.21:39:42.04#ibcon#read 6, iclass 21, count 0 2006.257.21:39:42.04#ibcon#end of sib2, iclass 21, count 0 2006.257.21:39:42.04#ibcon#*mode == 0, iclass 21, count 0 2006.257.21:39:42.04#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.21:39:42.04#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.21:39:42.04#ibcon#*before write, iclass 21, count 0 2006.257.21:39:42.04#ibcon#enter sib2, iclass 21, count 0 2006.257.21:39:42.04#ibcon#flushed, iclass 21, count 0 2006.257.21:39:42.04#ibcon#about to write, iclass 21, count 0 2006.257.21:39:42.05#ibcon#wrote, iclass 21, count 0 2006.257.21:39:42.05#ibcon#about to read 3, iclass 21, count 0 2006.257.21:39:42.08#ibcon#read 3, iclass 21, count 0 2006.257.21:39:42.08#ibcon#about to read 4, iclass 21, count 0 2006.257.21:39:42.08#ibcon#read 4, iclass 21, count 0 2006.257.21:39:42.08#ibcon#about to read 5, iclass 21, count 0 2006.257.21:39:42.08#ibcon#read 5, iclass 21, count 0 2006.257.21:39:42.08#ibcon#about to read 6, iclass 21, count 0 2006.257.21:39:42.08#ibcon#read 6, iclass 21, count 0 2006.257.21:39:42.08#ibcon#end of sib2, iclass 21, count 0 2006.257.21:39:42.08#ibcon#*after write, iclass 21, count 0 2006.257.21:39:42.08#ibcon#*before return 0, iclass 21, count 0 2006.257.21:39:42.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:42.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:42.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.21:39:42.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.21:39:42.09$vck44/va=6,4 2006.257.21:39:42.09#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.21:39:42.09#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.21:39:42.09#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:42.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:42.13#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:42.13#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:42.13#ibcon#enter wrdev, iclass 23, count 2 2006.257.21:39:42.13#ibcon#first serial, iclass 23, count 2 2006.257.21:39:42.13#ibcon#enter sib2, iclass 23, count 2 2006.257.21:39:42.14#ibcon#flushed, iclass 23, count 2 2006.257.21:39:42.14#ibcon#about to write, iclass 23, count 2 2006.257.21:39:42.14#ibcon#wrote, iclass 23, count 2 2006.257.21:39:42.14#ibcon#about to read 3, iclass 23, count 2 2006.257.21:39:42.15#ibcon#read 3, iclass 23, count 2 2006.257.21:39:42.15#ibcon#about to read 4, iclass 23, count 2 2006.257.21:39:42.15#ibcon#read 4, iclass 23, count 2 2006.257.21:39:42.15#ibcon#about to read 5, iclass 23, count 2 2006.257.21:39:42.15#ibcon#read 5, iclass 23, count 2 2006.257.21:39:42.15#ibcon#about to read 6, iclass 23, count 2 2006.257.21:39:42.15#ibcon#read 6, iclass 23, count 2 2006.257.21:39:42.15#ibcon#end of sib2, iclass 23, count 2 2006.257.21:39:42.15#ibcon#*mode == 0, iclass 23, count 2 2006.257.21:39:42.15#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.21:39:42.15#ibcon#[25=AT06-04\r\n] 2006.257.21:39:42.15#ibcon#*before write, iclass 23, count 2 2006.257.21:39:42.15#ibcon#enter sib2, iclass 23, count 2 2006.257.21:39:42.15#ibcon#flushed, iclass 23, count 2 2006.257.21:39:42.15#ibcon#about to write, iclass 23, count 2 2006.257.21:39:42.16#ibcon#wrote, iclass 23, count 2 2006.257.21:39:42.16#ibcon#about to read 3, iclass 23, count 2 2006.257.21:39:42.18#ibcon#read 3, iclass 23, count 2 2006.257.21:39:42.18#ibcon#about to read 4, iclass 23, count 2 2006.257.21:39:42.18#ibcon#read 4, iclass 23, count 2 2006.257.21:39:42.18#ibcon#about to read 5, iclass 23, count 2 2006.257.21:39:42.18#ibcon#read 5, iclass 23, count 2 2006.257.21:39:42.18#ibcon#about to read 6, iclass 23, count 2 2006.257.21:39:42.18#ibcon#read 6, iclass 23, count 2 2006.257.21:39:42.18#ibcon#end of sib2, iclass 23, count 2 2006.257.21:39:42.18#ibcon#*after write, iclass 23, count 2 2006.257.21:39:42.18#ibcon#*before return 0, iclass 23, count 2 2006.257.21:39:42.18#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:42.18#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:42.18#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.21:39:42.18#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:42.19#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:42.29#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:42.29#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:42.29#ibcon#enter wrdev, iclass 23, count 0 2006.257.21:39:42.29#ibcon#first serial, iclass 23, count 0 2006.257.21:39:42.29#ibcon#enter sib2, iclass 23, count 0 2006.257.21:39:42.29#ibcon#flushed, iclass 23, count 0 2006.257.21:39:42.29#ibcon#about to write, iclass 23, count 0 2006.257.21:39:42.29#ibcon#wrote, iclass 23, count 0 2006.257.21:39:42.29#ibcon#about to read 3, iclass 23, count 0 2006.257.21:39:42.31#ibcon#read 3, iclass 23, count 0 2006.257.21:39:42.31#ibcon#about to read 4, iclass 23, count 0 2006.257.21:39:42.31#ibcon#read 4, iclass 23, count 0 2006.257.21:39:42.31#ibcon#about to read 5, iclass 23, count 0 2006.257.21:39:42.31#ibcon#read 5, iclass 23, count 0 2006.257.21:39:42.31#ibcon#about to read 6, iclass 23, count 0 2006.257.21:39:42.31#ibcon#read 6, iclass 23, count 0 2006.257.21:39:42.31#ibcon#end of sib2, iclass 23, count 0 2006.257.21:39:42.31#ibcon#*mode == 0, iclass 23, count 0 2006.257.21:39:42.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.21:39:42.31#ibcon#[25=USB\r\n] 2006.257.21:39:42.31#ibcon#*before write, iclass 23, count 0 2006.257.21:39:42.31#ibcon#enter sib2, iclass 23, count 0 2006.257.21:39:42.31#ibcon#flushed, iclass 23, count 0 2006.257.21:39:42.31#ibcon#about to write, iclass 23, count 0 2006.257.21:39:42.32#ibcon#wrote, iclass 23, count 0 2006.257.21:39:42.32#ibcon#about to read 3, iclass 23, count 0 2006.257.21:39:42.34#ibcon#read 3, iclass 23, count 0 2006.257.21:39:42.34#ibcon#about to read 4, iclass 23, count 0 2006.257.21:39:42.34#ibcon#read 4, iclass 23, count 0 2006.257.21:39:42.34#ibcon#about to read 5, iclass 23, count 0 2006.257.21:39:42.34#ibcon#read 5, iclass 23, count 0 2006.257.21:39:42.34#ibcon#about to read 6, iclass 23, count 0 2006.257.21:39:42.34#ibcon#read 6, iclass 23, count 0 2006.257.21:39:42.34#ibcon#end of sib2, iclass 23, count 0 2006.257.21:39:42.34#ibcon#*after write, iclass 23, count 0 2006.257.21:39:42.34#ibcon#*before return 0, iclass 23, count 0 2006.257.21:39:42.34#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:42.34#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:42.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.21:39:42.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.21:39:42.35$vck44/valo=7,864.99 2006.257.21:39:42.35#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.21:39:42.35#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.21:39:42.35#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:42.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:42.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:42.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:42.35#ibcon#enter wrdev, iclass 25, count 0 2006.257.21:39:42.35#ibcon#first serial, iclass 25, count 0 2006.257.21:39:42.35#ibcon#enter sib2, iclass 25, count 0 2006.257.21:39:42.35#ibcon#flushed, iclass 25, count 0 2006.257.21:39:42.35#ibcon#about to write, iclass 25, count 0 2006.257.21:39:42.35#ibcon#wrote, iclass 25, count 0 2006.257.21:39:42.35#ibcon#about to read 3, iclass 25, count 0 2006.257.21:39:42.36#ibcon#read 3, iclass 25, count 0 2006.257.21:39:42.36#ibcon#about to read 4, iclass 25, count 0 2006.257.21:39:42.36#ibcon#read 4, iclass 25, count 0 2006.257.21:39:42.36#ibcon#about to read 5, iclass 25, count 0 2006.257.21:39:42.36#ibcon#read 5, iclass 25, count 0 2006.257.21:39:42.36#ibcon#about to read 6, iclass 25, count 0 2006.257.21:39:42.36#ibcon#read 6, iclass 25, count 0 2006.257.21:39:42.36#ibcon#end of sib2, iclass 25, count 0 2006.257.21:39:42.36#ibcon#*mode == 0, iclass 25, count 0 2006.257.21:39:42.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.21:39:42.36#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.21:39:42.36#ibcon#*before write, iclass 25, count 0 2006.257.21:39:42.36#ibcon#enter sib2, iclass 25, count 0 2006.257.21:39:42.36#ibcon#flushed, iclass 25, count 0 2006.257.21:39:42.36#ibcon#about to write, iclass 25, count 0 2006.257.21:39:42.37#ibcon#wrote, iclass 25, count 0 2006.257.21:39:42.37#ibcon#about to read 3, iclass 25, count 0 2006.257.21:39:42.40#ibcon#read 3, iclass 25, count 0 2006.257.21:39:42.40#ibcon#about to read 4, iclass 25, count 0 2006.257.21:39:42.40#ibcon#read 4, iclass 25, count 0 2006.257.21:39:42.40#ibcon#about to read 5, iclass 25, count 0 2006.257.21:39:42.40#ibcon#read 5, iclass 25, count 0 2006.257.21:39:42.40#ibcon#about to read 6, iclass 25, count 0 2006.257.21:39:42.40#ibcon#read 6, iclass 25, count 0 2006.257.21:39:42.40#ibcon#end of sib2, iclass 25, count 0 2006.257.21:39:42.40#ibcon#*after write, iclass 25, count 0 2006.257.21:39:42.40#ibcon#*before return 0, iclass 25, count 0 2006.257.21:39:42.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:42.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:42.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.21:39:42.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.21:39:42.41$vck44/va=7,4 2006.257.21:39:42.41#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.21:39:42.41#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.21:39:42.41#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:42.41#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:42.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:42.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:42.45#ibcon#enter wrdev, iclass 27, count 2 2006.257.21:39:42.45#ibcon#first serial, iclass 27, count 2 2006.257.21:39:42.45#ibcon#enter sib2, iclass 27, count 2 2006.257.21:39:42.45#ibcon#flushed, iclass 27, count 2 2006.257.21:39:42.45#ibcon#about to write, iclass 27, count 2 2006.257.21:39:42.45#ibcon#wrote, iclass 27, count 2 2006.257.21:39:42.45#ibcon#about to read 3, iclass 27, count 2 2006.257.21:39:42.47#ibcon#read 3, iclass 27, count 2 2006.257.21:39:42.47#ibcon#about to read 4, iclass 27, count 2 2006.257.21:39:42.47#ibcon#read 4, iclass 27, count 2 2006.257.21:39:42.47#ibcon#about to read 5, iclass 27, count 2 2006.257.21:39:42.47#ibcon#read 5, iclass 27, count 2 2006.257.21:39:42.47#ibcon#about to read 6, iclass 27, count 2 2006.257.21:39:42.47#ibcon#read 6, iclass 27, count 2 2006.257.21:39:42.47#ibcon#end of sib2, iclass 27, count 2 2006.257.21:39:42.47#ibcon#*mode == 0, iclass 27, count 2 2006.257.21:39:42.47#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.21:39:42.47#ibcon#[25=AT07-04\r\n] 2006.257.21:39:42.47#ibcon#*before write, iclass 27, count 2 2006.257.21:39:42.47#ibcon#enter sib2, iclass 27, count 2 2006.257.21:39:42.47#ibcon#flushed, iclass 27, count 2 2006.257.21:39:42.47#ibcon#about to write, iclass 27, count 2 2006.257.21:39:42.48#ibcon#wrote, iclass 27, count 2 2006.257.21:39:42.48#ibcon#about to read 3, iclass 27, count 2 2006.257.21:39:42.50#ibcon#read 3, iclass 27, count 2 2006.257.21:39:42.50#ibcon#about to read 4, iclass 27, count 2 2006.257.21:39:42.50#ibcon#read 4, iclass 27, count 2 2006.257.21:39:42.50#ibcon#about to read 5, iclass 27, count 2 2006.257.21:39:42.50#ibcon#read 5, iclass 27, count 2 2006.257.21:39:42.50#ibcon#about to read 6, iclass 27, count 2 2006.257.21:39:42.50#ibcon#read 6, iclass 27, count 2 2006.257.21:39:42.50#ibcon#end of sib2, iclass 27, count 2 2006.257.21:39:42.50#ibcon#*after write, iclass 27, count 2 2006.257.21:39:42.50#ibcon#*before return 0, iclass 27, count 2 2006.257.21:39:42.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:42.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:42.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.21:39:42.50#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:42.51#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:42.61#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:42.61#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:42.61#ibcon#enter wrdev, iclass 27, count 0 2006.257.21:39:42.61#ibcon#first serial, iclass 27, count 0 2006.257.21:39:42.61#ibcon#enter sib2, iclass 27, count 0 2006.257.21:39:42.61#ibcon#flushed, iclass 27, count 0 2006.257.21:39:42.61#ibcon#about to write, iclass 27, count 0 2006.257.21:39:42.61#ibcon#wrote, iclass 27, count 0 2006.257.21:39:42.61#ibcon#about to read 3, iclass 27, count 0 2006.257.21:39:42.63#ibcon#read 3, iclass 27, count 0 2006.257.21:39:42.63#ibcon#about to read 4, iclass 27, count 0 2006.257.21:39:42.63#ibcon#read 4, iclass 27, count 0 2006.257.21:39:42.63#ibcon#about to read 5, iclass 27, count 0 2006.257.21:39:42.63#ibcon#read 5, iclass 27, count 0 2006.257.21:39:42.63#ibcon#about to read 6, iclass 27, count 0 2006.257.21:39:42.63#ibcon#read 6, iclass 27, count 0 2006.257.21:39:42.63#ibcon#end of sib2, iclass 27, count 0 2006.257.21:39:42.63#ibcon#*mode == 0, iclass 27, count 0 2006.257.21:39:42.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.21:39:42.63#ibcon#[25=USB\r\n] 2006.257.21:39:42.63#ibcon#*before write, iclass 27, count 0 2006.257.21:39:42.63#ibcon#enter sib2, iclass 27, count 0 2006.257.21:39:42.63#ibcon#flushed, iclass 27, count 0 2006.257.21:39:42.63#ibcon#about to write, iclass 27, count 0 2006.257.21:39:42.64#ibcon#wrote, iclass 27, count 0 2006.257.21:39:42.64#ibcon#about to read 3, iclass 27, count 0 2006.257.21:39:42.66#ibcon#read 3, iclass 27, count 0 2006.257.21:39:42.66#ibcon#about to read 4, iclass 27, count 0 2006.257.21:39:42.66#ibcon#read 4, iclass 27, count 0 2006.257.21:39:42.66#ibcon#about to read 5, iclass 27, count 0 2006.257.21:39:42.66#ibcon#read 5, iclass 27, count 0 2006.257.21:39:42.66#ibcon#about to read 6, iclass 27, count 0 2006.257.21:39:42.66#ibcon#read 6, iclass 27, count 0 2006.257.21:39:42.66#ibcon#end of sib2, iclass 27, count 0 2006.257.21:39:42.66#ibcon#*after write, iclass 27, count 0 2006.257.21:39:42.66#ibcon#*before return 0, iclass 27, count 0 2006.257.21:39:42.66#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:42.66#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:42.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.21:39:42.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.21:39:42.67$vck44/valo=8,884.99 2006.257.21:39:42.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.21:39:42.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.21:39:42.67#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:42.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:42.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:42.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:42.67#ibcon#enter wrdev, iclass 29, count 0 2006.257.21:39:42.67#ibcon#first serial, iclass 29, count 0 2006.257.21:39:42.67#ibcon#enter sib2, iclass 29, count 0 2006.257.21:39:42.67#ibcon#flushed, iclass 29, count 0 2006.257.21:39:42.67#ibcon#about to write, iclass 29, count 0 2006.257.21:39:42.67#ibcon#wrote, iclass 29, count 0 2006.257.21:39:42.67#ibcon#about to read 3, iclass 29, count 0 2006.257.21:39:42.68#ibcon#read 3, iclass 29, count 0 2006.257.21:39:42.68#ibcon#about to read 4, iclass 29, count 0 2006.257.21:39:42.68#ibcon#read 4, iclass 29, count 0 2006.257.21:39:42.68#ibcon#about to read 5, iclass 29, count 0 2006.257.21:39:42.68#ibcon#read 5, iclass 29, count 0 2006.257.21:39:42.68#ibcon#about to read 6, iclass 29, count 0 2006.257.21:39:42.68#ibcon#read 6, iclass 29, count 0 2006.257.21:39:42.68#ibcon#end of sib2, iclass 29, count 0 2006.257.21:39:42.68#ibcon#*mode == 0, iclass 29, count 0 2006.257.21:39:42.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.21:39:42.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.21:39:42.68#ibcon#*before write, iclass 29, count 0 2006.257.21:39:42.68#ibcon#enter sib2, iclass 29, count 0 2006.257.21:39:42.68#ibcon#flushed, iclass 29, count 0 2006.257.21:39:42.68#ibcon#about to write, iclass 29, count 0 2006.257.21:39:42.69#ibcon#wrote, iclass 29, count 0 2006.257.21:39:42.69#ibcon#about to read 3, iclass 29, count 0 2006.257.21:39:42.72#ibcon#read 3, iclass 29, count 0 2006.257.21:39:42.72#ibcon#about to read 4, iclass 29, count 0 2006.257.21:39:42.72#ibcon#read 4, iclass 29, count 0 2006.257.21:39:42.72#ibcon#about to read 5, iclass 29, count 0 2006.257.21:39:42.72#ibcon#read 5, iclass 29, count 0 2006.257.21:39:42.72#ibcon#about to read 6, iclass 29, count 0 2006.257.21:39:42.72#ibcon#read 6, iclass 29, count 0 2006.257.21:39:42.72#ibcon#end of sib2, iclass 29, count 0 2006.257.21:39:42.72#ibcon#*after write, iclass 29, count 0 2006.257.21:39:42.72#ibcon#*before return 0, iclass 29, count 0 2006.257.21:39:42.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:42.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:42.72#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.21:39:42.72#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.21:39:42.73$vck44/va=8,4 2006.257.21:39:42.73#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.21:39:42.73#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.21:39:42.73#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:42.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:39:42.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:39:42.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:39:42.77#ibcon#enter wrdev, iclass 31, count 2 2006.257.21:39:42.77#ibcon#first serial, iclass 31, count 2 2006.257.21:39:42.77#ibcon#enter sib2, iclass 31, count 2 2006.257.21:39:42.77#ibcon#flushed, iclass 31, count 2 2006.257.21:39:42.77#ibcon#about to write, iclass 31, count 2 2006.257.21:39:42.77#ibcon#wrote, iclass 31, count 2 2006.257.21:39:42.77#ibcon#about to read 3, iclass 31, count 2 2006.257.21:39:42.79#ibcon#read 3, iclass 31, count 2 2006.257.21:39:42.79#ibcon#about to read 4, iclass 31, count 2 2006.257.21:39:42.79#ibcon#read 4, iclass 31, count 2 2006.257.21:39:42.79#ibcon#about to read 5, iclass 31, count 2 2006.257.21:39:42.79#ibcon#read 5, iclass 31, count 2 2006.257.21:39:42.79#ibcon#about to read 6, iclass 31, count 2 2006.257.21:39:42.79#ibcon#read 6, iclass 31, count 2 2006.257.21:39:42.79#ibcon#end of sib2, iclass 31, count 2 2006.257.21:39:42.79#ibcon#*mode == 0, iclass 31, count 2 2006.257.21:39:42.79#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.21:39:42.79#ibcon#[25=AT08-04\r\n] 2006.257.21:39:42.79#ibcon#*before write, iclass 31, count 2 2006.257.21:39:42.79#ibcon#enter sib2, iclass 31, count 2 2006.257.21:39:42.79#ibcon#flushed, iclass 31, count 2 2006.257.21:39:42.79#ibcon#about to write, iclass 31, count 2 2006.257.21:39:42.80#ibcon#wrote, iclass 31, count 2 2006.257.21:39:42.80#ibcon#about to read 3, iclass 31, count 2 2006.257.21:39:42.82#ibcon#read 3, iclass 31, count 2 2006.257.21:39:42.82#ibcon#about to read 4, iclass 31, count 2 2006.257.21:39:42.82#ibcon#read 4, iclass 31, count 2 2006.257.21:39:42.82#ibcon#about to read 5, iclass 31, count 2 2006.257.21:39:42.82#ibcon#read 5, iclass 31, count 2 2006.257.21:39:42.82#ibcon#about to read 6, iclass 31, count 2 2006.257.21:39:42.82#ibcon#read 6, iclass 31, count 2 2006.257.21:39:42.82#ibcon#end of sib2, iclass 31, count 2 2006.257.21:39:42.82#ibcon#*after write, iclass 31, count 2 2006.257.21:39:42.82#ibcon#*before return 0, iclass 31, count 2 2006.257.21:39:42.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:39:42.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.21:39:42.82#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.21:39:42.82#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:42.83#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:39:42.93#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:39:42.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:39:42.93#ibcon#enter wrdev, iclass 31, count 0 2006.257.21:39:42.93#ibcon#first serial, iclass 31, count 0 2006.257.21:39:42.93#ibcon#enter sib2, iclass 31, count 0 2006.257.21:39:42.93#ibcon#flushed, iclass 31, count 0 2006.257.21:39:42.93#ibcon#about to write, iclass 31, count 0 2006.257.21:39:42.93#ibcon#wrote, iclass 31, count 0 2006.257.21:39:42.93#ibcon#about to read 3, iclass 31, count 0 2006.257.21:39:42.95#ibcon#read 3, iclass 31, count 0 2006.257.21:39:42.95#ibcon#about to read 4, iclass 31, count 0 2006.257.21:39:42.95#ibcon#read 4, iclass 31, count 0 2006.257.21:39:42.95#ibcon#about to read 5, iclass 31, count 0 2006.257.21:39:42.95#ibcon#read 5, iclass 31, count 0 2006.257.21:39:42.95#ibcon#about to read 6, iclass 31, count 0 2006.257.21:39:42.95#ibcon#read 6, iclass 31, count 0 2006.257.21:39:42.95#ibcon#end of sib2, iclass 31, count 0 2006.257.21:39:42.95#ibcon#*mode == 0, iclass 31, count 0 2006.257.21:39:42.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.21:39:42.95#ibcon#[25=USB\r\n] 2006.257.21:39:42.95#ibcon#*before write, iclass 31, count 0 2006.257.21:39:42.95#ibcon#enter sib2, iclass 31, count 0 2006.257.21:39:42.95#ibcon#flushed, iclass 31, count 0 2006.257.21:39:42.95#ibcon#about to write, iclass 31, count 0 2006.257.21:39:42.96#ibcon#wrote, iclass 31, count 0 2006.257.21:39:42.96#ibcon#about to read 3, iclass 31, count 0 2006.257.21:39:42.98#ibcon#read 3, iclass 31, count 0 2006.257.21:39:42.98#ibcon#about to read 4, iclass 31, count 0 2006.257.21:39:42.98#ibcon#read 4, iclass 31, count 0 2006.257.21:39:42.98#ibcon#about to read 5, iclass 31, count 0 2006.257.21:39:42.98#ibcon#read 5, iclass 31, count 0 2006.257.21:39:42.98#ibcon#about to read 6, iclass 31, count 0 2006.257.21:39:42.98#ibcon#read 6, iclass 31, count 0 2006.257.21:39:42.98#ibcon#end of sib2, iclass 31, count 0 2006.257.21:39:42.98#ibcon#*after write, iclass 31, count 0 2006.257.21:39:42.98#ibcon#*before return 0, iclass 31, count 0 2006.257.21:39:42.98#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:39:42.98#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.21:39:42.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.21:39:42.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.21:39:42.99$vck44/vblo=1,629.99 2006.257.21:39:42.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.21:39:42.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.21:39:42.99#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:42.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:39:42.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:39:42.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:39:42.99#ibcon#enter wrdev, iclass 33, count 0 2006.257.21:39:42.99#ibcon#first serial, iclass 33, count 0 2006.257.21:39:42.99#ibcon#enter sib2, iclass 33, count 0 2006.257.21:39:42.99#ibcon#flushed, iclass 33, count 0 2006.257.21:39:42.99#ibcon#about to write, iclass 33, count 0 2006.257.21:39:42.99#ibcon#wrote, iclass 33, count 0 2006.257.21:39:42.99#ibcon#about to read 3, iclass 33, count 0 2006.257.21:39:43.00#ibcon#read 3, iclass 33, count 0 2006.257.21:39:43.00#ibcon#about to read 4, iclass 33, count 0 2006.257.21:39:43.00#ibcon#read 4, iclass 33, count 0 2006.257.21:39:43.00#ibcon#about to read 5, iclass 33, count 0 2006.257.21:39:43.00#ibcon#read 5, iclass 33, count 0 2006.257.21:39:43.00#ibcon#about to read 6, iclass 33, count 0 2006.257.21:39:43.00#ibcon#read 6, iclass 33, count 0 2006.257.21:39:43.00#ibcon#end of sib2, iclass 33, count 0 2006.257.21:39:43.00#ibcon#*mode == 0, iclass 33, count 0 2006.257.21:39:43.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.21:39:43.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.21:39:43.00#ibcon#*before write, iclass 33, count 0 2006.257.21:39:43.00#ibcon#enter sib2, iclass 33, count 0 2006.257.21:39:43.00#ibcon#flushed, iclass 33, count 0 2006.257.21:39:43.00#ibcon#about to write, iclass 33, count 0 2006.257.21:39:43.01#ibcon#wrote, iclass 33, count 0 2006.257.21:39:43.01#ibcon#about to read 3, iclass 33, count 0 2006.257.21:39:43.04#ibcon#read 3, iclass 33, count 0 2006.257.21:39:43.04#ibcon#about to read 4, iclass 33, count 0 2006.257.21:39:43.04#ibcon#read 4, iclass 33, count 0 2006.257.21:39:43.04#ibcon#about to read 5, iclass 33, count 0 2006.257.21:39:43.04#ibcon#read 5, iclass 33, count 0 2006.257.21:39:43.04#ibcon#about to read 6, iclass 33, count 0 2006.257.21:39:43.04#ibcon#read 6, iclass 33, count 0 2006.257.21:39:43.04#ibcon#end of sib2, iclass 33, count 0 2006.257.21:39:43.04#ibcon#*after write, iclass 33, count 0 2006.257.21:39:43.04#ibcon#*before return 0, iclass 33, count 0 2006.257.21:39:43.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:39:43.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.21:39:43.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.21:39:43.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.21:39:43.05$vck44/vb=1,4 2006.257.21:39:43.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.21:39:43.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.21:39:43.05#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:43.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:39:43.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:39:43.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:39:43.05#ibcon#enter wrdev, iclass 35, count 2 2006.257.21:39:43.05#ibcon#first serial, iclass 35, count 2 2006.257.21:39:43.05#ibcon#enter sib2, iclass 35, count 2 2006.257.21:39:43.05#ibcon#flushed, iclass 35, count 2 2006.257.21:39:43.05#ibcon#about to write, iclass 35, count 2 2006.257.21:39:43.05#ibcon#wrote, iclass 35, count 2 2006.257.21:39:43.05#ibcon#about to read 3, iclass 35, count 2 2006.257.21:39:43.06#ibcon#read 3, iclass 35, count 2 2006.257.21:39:43.06#ibcon#about to read 4, iclass 35, count 2 2006.257.21:39:43.06#ibcon#read 4, iclass 35, count 2 2006.257.21:39:43.06#ibcon#about to read 5, iclass 35, count 2 2006.257.21:39:43.06#ibcon#read 5, iclass 35, count 2 2006.257.21:39:43.06#ibcon#about to read 6, iclass 35, count 2 2006.257.21:39:43.06#ibcon#read 6, iclass 35, count 2 2006.257.21:39:43.06#ibcon#end of sib2, iclass 35, count 2 2006.257.21:39:43.06#ibcon#*mode == 0, iclass 35, count 2 2006.257.21:39:43.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.21:39:43.06#ibcon#[27=AT01-04\r\n] 2006.257.21:39:43.06#ibcon#*before write, iclass 35, count 2 2006.257.21:39:43.06#ibcon#enter sib2, iclass 35, count 2 2006.257.21:39:43.06#ibcon#flushed, iclass 35, count 2 2006.257.21:39:43.06#ibcon#about to write, iclass 35, count 2 2006.257.21:39:43.07#ibcon#wrote, iclass 35, count 2 2006.257.21:39:43.07#ibcon#about to read 3, iclass 35, count 2 2006.257.21:39:43.09#ibcon#read 3, iclass 35, count 2 2006.257.21:39:43.09#ibcon#about to read 4, iclass 35, count 2 2006.257.21:39:43.09#ibcon#read 4, iclass 35, count 2 2006.257.21:39:43.09#ibcon#about to read 5, iclass 35, count 2 2006.257.21:39:43.09#ibcon#read 5, iclass 35, count 2 2006.257.21:39:43.09#ibcon#about to read 6, iclass 35, count 2 2006.257.21:39:43.09#ibcon#read 6, iclass 35, count 2 2006.257.21:39:43.09#ibcon#end of sib2, iclass 35, count 2 2006.257.21:39:43.09#ibcon#*after write, iclass 35, count 2 2006.257.21:39:43.09#ibcon#*before return 0, iclass 35, count 2 2006.257.21:39:43.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:39:43.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.21:39:43.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.21:39:43.09#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:43.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:39:43.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:39:43.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:39:43.20#ibcon#enter wrdev, iclass 35, count 0 2006.257.21:39:43.20#ibcon#first serial, iclass 35, count 0 2006.257.21:39:43.20#ibcon#enter sib2, iclass 35, count 0 2006.257.21:39:43.20#ibcon#flushed, iclass 35, count 0 2006.257.21:39:43.20#ibcon#about to write, iclass 35, count 0 2006.257.21:39:43.20#ibcon#wrote, iclass 35, count 0 2006.257.21:39:43.20#ibcon#about to read 3, iclass 35, count 0 2006.257.21:39:43.22#ibcon#read 3, iclass 35, count 0 2006.257.21:39:43.22#ibcon#about to read 4, iclass 35, count 0 2006.257.21:39:43.22#ibcon#read 4, iclass 35, count 0 2006.257.21:39:43.22#ibcon#about to read 5, iclass 35, count 0 2006.257.21:39:43.22#ibcon#read 5, iclass 35, count 0 2006.257.21:39:43.22#ibcon#about to read 6, iclass 35, count 0 2006.257.21:39:43.22#ibcon#read 6, iclass 35, count 0 2006.257.21:39:43.22#ibcon#end of sib2, iclass 35, count 0 2006.257.21:39:43.22#ibcon#*mode == 0, iclass 35, count 0 2006.257.21:39:43.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.21:39:43.22#ibcon#[27=USB\r\n] 2006.257.21:39:43.22#ibcon#*before write, iclass 35, count 0 2006.257.21:39:43.22#ibcon#enter sib2, iclass 35, count 0 2006.257.21:39:43.22#ibcon#flushed, iclass 35, count 0 2006.257.21:39:43.22#ibcon#about to write, iclass 35, count 0 2006.257.21:39:43.23#ibcon#wrote, iclass 35, count 0 2006.257.21:39:43.23#ibcon#about to read 3, iclass 35, count 0 2006.257.21:39:43.25#ibcon#read 3, iclass 35, count 0 2006.257.21:39:43.25#ibcon#about to read 4, iclass 35, count 0 2006.257.21:39:43.25#ibcon#read 4, iclass 35, count 0 2006.257.21:39:43.25#ibcon#about to read 5, iclass 35, count 0 2006.257.21:39:43.25#ibcon#read 5, iclass 35, count 0 2006.257.21:39:43.25#ibcon#about to read 6, iclass 35, count 0 2006.257.21:39:43.25#ibcon#read 6, iclass 35, count 0 2006.257.21:39:43.25#ibcon#end of sib2, iclass 35, count 0 2006.257.21:39:43.25#ibcon#*after write, iclass 35, count 0 2006.257.21:39:43.25#ibcon#*before return 0, iclass 35, count 0 2006.257.21:39:43.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:39:43.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.21:39:43.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.21:39:43.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.21:39:43.26$vck44/vblo=2,634.99 2006.257.21:39:43.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.21:39:43.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.21:39:43.26#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:43.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:43.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:43.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:43.26#ibcon#enter wrdev, iclass 37, count 0 2006.257.21:39:43.26#ibcon#first serial, iclass 37, count 0 2006.257.21:39:43.26#ibcon#enter sib2, iclass 37, count 0 2006.257.21:39:43.26#ibcon#flushed, iclass 37, count 0 2006.257.21:39:43.26#ibcon#about to write, iclass 37, count 0 2006.257.21:39:43.26#ibcon#wrote, iclass 37, count 0 2006.257.21:39:43.26#ibcon#about to read 3, iclass 37, count 0 2006.257.21:39:43.27#ibcon#read 3, iclass 37, count 0 2006.257.21:39:43.27#ibcon#about to read 4, iclass 37, count 0 2006.257.21:39:43.27#ibcon#read 4, iclass 37, count 0 2006.257.21:39:43.27#ibcon#about to read 5, iclass 37, count 0 2006.257.21:39:43.27#ibcon#read 5, iclass 37, count 0 2006.257.21:39:43.27#ibcon#about to read 6, iclass 37, count 0 2006.257.21:39:43.27#ibcon#read 6, iclass 37, count 0 2006.257.21:39:43.27#ibcon#end of sib2, iclass 37, count 0 2006.257.21:39:43.27#ibcon#*mode == 0, iclass 37, count 0 2006.257.21:39:43.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.21:39:43.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.21:39:43.27#ibcon#*before write, iclass 37, count 0 2006.257.21:39:43.27#ibcon#enter sib2, iclass 37, count 0 2006.257.21:39:43.27#ibcon#flushed, iclass 37, count 0 2006.257.21:39:43.27#ibcon#about to write, iclass 37, count 0 2006.257.21:39:43.28#ibcon#wrote, iclass 37, count 0 2006.257.21:39:43.28#ibcon#about to read 3, iclass 37, count 0 2006.257.21:39:43.31#ibcon#read 3, iclass 37, count 0 2006.257.21:39:43.31#ibcon#about to read 4, iclass 37, count 0 2006.257.21:39:43.31#ibcon#read 4, iclass 37, count 0 2006.257.21:39:43.31#ibcon#about to read 5, iclass 37, count 0 2006.257.21:39:43.31#ibcon#read 5, iclass 37, count 0 2006.257.21:39:43.31#ibcon#about to read 6, iclass 37, count 0 2006.257.21:39:43.31#ibcon#read 6, iclass 37, count 0 2006.257.21:39:43.31#ibcon#end of sib2, iclass 37, count 0 2006.257.21:39:43.31#ibcon#*after write, iclass 37, count 0 2006.257.21:39:43.31#ibcon#*before return 0, iclass 37, count 0 2006.257.21:39:43.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:43.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.21:39:43.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.21:39:43.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.21:39:43.32$vck44/vb=2,5 2006.257.21:39:43.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.21:39:43.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.21:39:43.32#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:43.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:43.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:43.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:43.36#ibcon#enter wrdev, iclass 39, count 2 2006.257.21:39:43.36#ibcon#first serial, iclass 39, count 2 2006.257.21:39:43.36#ibcon#enter sib2, iclass 39, count 2 2006.257.21:39:43.36#ibcon#flushed, iclass 39, count 2 2006.257.21:39:43.36#ibcon#about to write, iclass 39, count 2 2006.257.21:39:43.36#ibcon#wrote, iclass 39, count 2 2006.257.21:39:43.36#ibcon#about to read 3, iclass 39, count 2 2006.257.21:39:43.38#ibcon#read 3, iclass 39, count 2 2006.257.21:39:43.38#ibcon#about to read 4, iclass 39, count 2 2006.257.21:39:43.38#ibcon#read 4, iclass 39, count 2 2006.257.21:39:43.38#ibcon#about to read 5, iclass 39, count 2 2006.257.21:39:43.38#ibcon#read 5, iclass 39, count 2 2006.257.21:39:43.38#ibcon#about to read 6, iclass 39, count 2 2006.257.21:39:43.38#ibcon#read 6, iclass 39, count 2 2006.257.21:39:43.38#ibcon#end of sib2, iclass 39, count 2 2006.257.21:39:43.38#ibcon#*mode == 0, iclass 39, count 2 2006.257.21:39:43.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.21:39:43.38#ibcon#[27=AT02-05\r\n] 2006.257.21:39:43.38#ibcon#*before write, iclass 39, count 2 2006.257.21:39:43.38#ibcon#enter sib2, iclass 39, count 2 2006.257.21:39:43.38#ibcon#flushed, iclass 39, count 2 2006.257.21:39:43.38#ibcon#about to write, iclass 39, count 2 2006.257.21:39:43.39#ibcon#wrote, iclass 39, count 2 2006.257.21:39:43.39#ibcon#about to read 3, iclass 39, count 2 2006.257.21:39:43.41#ibcon#read 3, iclass 39, count 2 2006.257.21:39:43.41#ibcon#about to read 4, iclass 39, count 2 2006.257.21:39:43.41#ibcon#read 4, iclass 39, count 2 2006.257.21:39:43.41#ibcon#about to read 5, iclass 39, count 2 2006.257.21:39:43.41#ibcon#read 5, iclass 39, count 2 2006.257.21:39:43.41#ibcon#about to read 6, iclass 39, count 2 2006.257.21:39:43.41#ibcon#read 6, iclass 39, count 2 2006.257.21:39:43.41#ibcon#end of sib2, iclass 39, count 2 2006.257.21:39:43.41#ibcon#*after write, iclass 39, count 2 2006.257.21:39:43.41#ibcon#*before return 0, iclass 39, count 2 2006.257.21:39:43.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:43.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.21:39:43.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.21:39:43.41#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:43.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:43.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:43.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:43.53#ibcon#enter wrdev, iclass 39, count 0 2006.257.21:39:43.53#ibcon#first serial, iclass 39, count 0 2006.257.21:39:43.53#ibcon#enter sib2, iclass 39, count 0 2006.257.21:39:43.53#ibcon#flushed, iclass 39, count 0 2006.257.21:39:43.53#ibcon#about to write, iclass 39, count 0 2006.257.21:39:43.53#ibcon#wrote, iclass 39, count 0 2006.257.21:39:43.53#ibcon#about to read 3, iclass 39, count 0 2006.257.21:39:43.55#ibcon#read 3, iclass 39, count 0 2006.257.21:39:43.55#ibcon#about to read 4, iclass 39, count 0 2006.257.21:39:43.55#ibcon#read 4, iclass 39, count 0 2006.257.21:39:43.55#ibcon#about to read 5, iclass 39, count 0 2006.257.21:39:43.55#ibcon#read 5, iclass 39, count 0 2006.257.21:39:43.55#ibcon#about to read 6, iclass 39, count 0 2006.257.21:39:43.55#ibcon#read 6, iclass 39, count 0 2006.257.21:39:43.55#ibcon#end of sib2, iclass 39, count 0 2006.257.21:39:43.55#ibcon#*mode == 0, iclass 39, count 0 2006.257.21:39:43.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.21:39:43.55#ibcon#[27=USB\r\n] 2006.257.21:39:43.55#ibcon#*before write, iclass 39, count 0 2006.257.21:39:43.55#ibcon#enter sib2, iclass 39, count 0 2006.257.21:39:43.55#ibcon#flushed, iclass 39, count 0 2006.257.21:39:43.55#ibcon#about to write, iclass 39, count 0 2006.257.21:39:43.56#ibcon#wrote, iclass 39, count 0 2006.257.21:39:43.56#ibcon#about to read 3, iclass 39, count 0 2006.257.21:39:43.58#ibcon#read 3, iclass 39, count 0 2006.257.21:39:43.58#ibcon#about to read 4, iclass 39, count 0 2006.257.21:39:43.58#ibcon#read 4, iclass 39, count 0 2006.257.21:39:43.58#ibcon#about to read 5, iclass 39, count 0 2006.257.21:39:43.58#ibcon#read 5, iclass 39, count 0 2006.257.21:39:43.58#ibcon#about to read 6, iclass 39, count 0 2006.257.21:39:43.58#ibcon#read 6, iclass 39, count 0 2006.257.21:39:43.58#ibcon#end of sib2, iclass 39, count 0 2006.257.21:39:43.58#ibcon#*after write, iclass 39, count 0 2006.257.21:39:43.58#ibcon#*before return 0, iclass 39, count 0 2006.257.21:39:43.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:43.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.21:39:43.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.21:39:43.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.21:39:43.59$vck44/vblo=3,649.99 2006.257.21:39:43.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.21:39:43.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.21:39:43.59#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:43.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:43.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:43.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:43.59#ibcon#enter wrdev, iclass 3, count 0 2006.257.21:39:43.59#ibcon#first serial, iclass 3, count 0 2006.257.21:39:43.59#ibcon#enter sib2, iclass 3, count 0 2006.257.21:39:43.59#ibcon#flushed, iclass 3, count 0 2006.257.21:39:43.59#ibcon#about to write, iclass 3, count 0 2006.257.21:39:43.59#ibcon#wrote, iclass 3, count 0 2006.257.21:39:43.59#ibcon#about to read 3, iclass 3, count 0 2006.257.21:39:43.60#ibcon#read 3, iclass 3, count 0 2006.257.21:39:43.60#ibcon#about to read 4, iclass 3, count 0 2006.257.21:39:43.60#ibcon#read 4, iclass 3, count 0 2006.257.21:39:43.60#ibcon#about to read 5, iclass 3, count 0 2006.257.21:39:43.60#ibcon#read 5, iclass 3, count 0 2006.257.21:39:43.60#ibcon#about to read 6, iclass 3, count 0 2006.257.21:39:43.60#ibcon#read 6, iclass 3, count 0 2006.257.21:39:43.60#ibcon#end of sib2, iclass 3, count 0 2006.257.21:39:43.60#ibcon#*mode == 0, iclass 3, count 0 2006.257.21:39:43.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.21:39:43.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.21:39:43.60#ibcon#*before write, iclass 3, count 0 2006.257.21:39:43.60#ibcon#enter sib2, iclass 3, count 0 2006.257.21:39:43.60#ibcon#flushed, iclass 3, count 0 2006.257.21:39:43.60#ibcon#about to write, iclass 3, count 0 2006.257.21:39:43.61#ibcon#wrote, iclass 3, count 0 2006.257.21:39:43.61#ibcon#about to read 3, iclass 3, count 0 2006.257.21:39:43.64#ibcon#read 3, iclass 3, count 0 2006.257.21:39:43.64#ibcon#about to read 4, iclass 3, count 0 2006.257.21:39:43.64#ibcon#read 4, iclass 3, count 0 2006.257.21:39:43.64#ibcon#about to read 5, iclass 3, count 0 2006.257.21:39:43.64#ibcon#read 5, iclass 3, count 0 2006.257.21:39:43.64#ibcon#about to read 6, iclass 3, count 0 2006.257.21:39:43.64#ibcon#read 6, iclass 3, count 0 2006.257.21:39:43.64#ibcon#end of sib2, iclass 3, count 0 2006.257.21:39:43.64#ibcon#*after write, iclass 3, count 0 2006.257.21:39:43.64#ibcon#*before return 0, iclass 3, count 0 2006.257.21:39:43.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:43.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.21:39:43.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.21:39:43.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.21:39:43.65$vck44/vb=3,4 2006.257.21:39:43.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.21:39:43.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.21:39:43.65#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:43.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:43.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:43.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:43.69#ibcon#enter wrdev, iclass 5, count 2 2006.257.21:39:43.69#ibcon#first serial, iclass 5, count 2 2006.257.21:39:43.69#ibcon#enter sib2, iclass 5, count 2 2006.257.21:39:43.69#ibcon#flushed, iclass 5, count 2 2006.257.21:39:43.69#ibcon#about to write, iclass 5, count 2 2006.257.21:39:43.69#ibcon#wrote, iclass 5, count 2 2006.257.21:39:43.69#ibcon#about to read 3, iclass 5, count 2 2006.257.21:39:43.71#ibcon#read 3, iclass 5, count 2 2006.257.21:39:43.71#ibcon#about to read 4, iclass 5, count 2 2006.257.21:39:43.71#ibcon#read 4, iclass 5, count 2 2006.257.21:39:43.71#ibcon#about to read 5, iclass 5, count 2 2006.257.21:39:43.71#ibcon#read 5, iclass 5, count 2 2006.257.21:39:43.71#ibcon#about to read 6, iclass 5, count 2 2006.257.21:39:43.71#ibcon#read 6, iclass 5, count 2 2006.257.21:39:43.71#ibcon#end of sib2, iclass 5, count 2 2006.257.21:39:43.71#ibcon#*mode == 0, iclass 5, count 2 2006.257.21:39:43.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.21:39:43.71#ibcon#[27=AT03-04\r\n] 2006.257.21:39:43.71#ibcon#*before write, iclass 5, count 2 2006.257.21:39:43.71#ibcon#enter sib2, iclass 5, count 2 2006.257.21:39:43.71#ibcon#flushed, iclass 5, count 2 2006.257.21:39:43.71#ibcon#about to write, iclass 5, count 2 2006.257.21:39:43.72#ibcon#wrote, iclass 5, count 2 2006.257.21:39:43.72#ibcon#about to read 3, iclass 5, count 2 2006.257.21:39:43.74#ibcon#read 3, iclass 5, count 2 2006.257.21:39:43.74#ibcon#about to read 4, iclass 5, count 2 2006.257.21:39:43.74#ibcon#read 4, iclass 5, count 2 2006.257.21:39:43.74#ibcon#about to read 5, iclass 5, count 2 2006.257.21:39:43.74#ibcon#read 5, iclass 5, count 2 2006.257.21:39:43.74#ibcon#about to read 6, iclass 5, count 2 2006.257.21:39:43.74#ibcon#read 6, iclass 5, count 2 2006.257.21:39:43.74#ibcon#end of sib2, iclass 5, count 2 2006.257.21:39:43.74#ibcon#*after write, iclass 5, count 2 2006.257.21:39:43.74#ibcon#*before return 0, iclass 5, count 2 2006.257.21:39:43.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:43.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.21:39:43.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.21:39:43.74#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:43.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:43.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:43.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:43.86#ibcon#enter wrdev, iclass 5, count 0 2006.257.21:39:43.86#ibcon#first serial, iclass 5, count 0 2006.257.21:39:43.86#ibcon#enter sib2, iclass 5, count 0 2006.257.21:39:43.86#ibcon#flushed, iclass 5, count 0 2006.257.21:39:43.86#ibcon#about to write, iclass 5, count 0 2006.257.21:39:43.86#ibcon#wrote, iclass 5, count 0 2006.257.21:39:43.86#ibcon#about to read 3, iclass 5, count 0 2006.257.21:39:43.88#ibcon#read 3, iclass 5, count 0 2006.257.21:39:43.88#ibcon#about to read 4, iclass 5, count 0 2006.257.21:39:43.88#ibcon#read 4, iclass 5, count 0 2006.257.21:39:43.88#ibcon#about to read 5, iclass 5, count 0 2006.257.21:39:43.88#ibcon#read 5, iclass 5, count 0 2006.257.21:39:43.88#ibcon#about to read 6, iclass 5, count 0 2006.257.21:39:43.88#ibcon#read 6, iclass 5, count 0 2006.257.21:39:43.88#ibcon#end of sib2, iclass 5, count 0 2006.257.21:39:43.88#ibcon#*mode == 0, iclass 5, count 0 2006.257.21:39:43.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.21:39:43.88#ibcon#[27=USB\r\n] 2006.257.21:39:43.88#ibcon#*before write, iclass 5, count 0 2006.257.21:39:43.88#ibcon#enter sib2, iclass 5, count 0 2006.257.21:39:43.88#ibcon#flushed, iclass 5, count 0 2006.257.21:39:43.88#ibcon#about to write, iclass 5, count 0 2006.257.21:39:43.89#ibcon#wrote, iclass 5, count 0 2006.257.21:39:43.89#ibcon#about to read 3, iclass 5, count 0 2006.257.21:39:43.91#ibcon#read 3, iclass 5, count 0 2006.257.21:39:43.91#ibcon#about to read 4, iclass 5, count 0 2006.257.21:39:43.91#ibcon#read 4, iclass 5, count 0 2006.257.21:39:43.91#ibcon#about to read 5, iclass 5, count 0 2006.257.21:39:43.91#ibcon#read 5, iclass 5, count 0 2006.257.21:39:43.91#ibcon#about to read 6, iclass 5, count 0 2006.257.21:39:43.91#ibcon#read 6, iclass 5, count 0 2006.257.21:39:43.91#ibcon#end of sib2, iclass 5, count 0 2006.257.21:39:43.91#ibcon#*after write, iclass 5, count 0 2006.257.21:39:43.91#ibcon#*before return 0, iclass 5, count 0 2006.257.21:39:43.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:43.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.21:39:43.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.21:39:43.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.21:39:43.92$vck44/vblo=4,679.99 2006.257.21:39:43.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.21:39:43.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.21:39:43.92#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:43.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:43.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:43.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:43.92#ibcon#enter wrdev, iclass 7, count 0 2006.257.21:39:43.92#ibcon#first serial, iclass 7, count 0 2006.257.21:39:43.92#ibcon#enter sib2, iclass 7, count 0 2006.257.21:39:43.92#ibcon#flushed, iclass 7, count 0 2006.257.21:39:43.92#ibcon#about to write, iclass 7, count 0 2006.257.21:39:43.92#ibcon#wrote, iclass 7, count 0 2006.257.21:39:43.92#ibcon#about to read 3, iclass 7, count 0 2006.257.21:39:43.93#ibcon#read 3, iclass 7, count 0 2006.257.21:39:43.93#ibcon#about to read 4, iclass 7, count 0 2006.257.21:39:43.93#ibcon#read 4, iclass 7, count 0 2006.257.21:39:43.93#ibcon#about to read 5, iclass 7, count 0 2006.257.21:39:43.93#ibcon#read 5, iclass 7, count 0 2006.257.21:39:43.93#ibcon#about to read 6, iclass 7, count 0 2006.257.21:39:43.93#ibcon#read 6, iclass 7, count 0 2006.257.21:39:43.93#ibcon#end of sib2, iclass 7, count 0 2006.257.21:39:43.93#ibcon#*mode == 0, iclass 7, count 0 2006.257.21:39:43.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.21:39:43.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.21:39:43.93#ibcon#*before write, iclass 7, count 0 2006.257.21:39:43.93#ibcon#enter sib2, iclass 7, count 0 2006.257.21:39:43.93#ibcon#flushed, iclass 7, count 0 2006.257.21:39:43.93#ibcon#about to write, iclass 7, count 0 2006.257.21:39:43.94#ibcon#wrote, iclass 7, count 0 2006.257.21:39:43.94#ibcon#about to read 3, iclass 7, count 0 2006.257.21:39:43.97#ibcon#read 3, iclass 7, count 0 2006.257.21:39:43.97#ibcon#about to read 4, iclass 7, count 0 2006.257.21:39:43.97#ibcon#read 4, iclass 7, count 0 2006.257.21:39:43.97#ibcon#about to read 5, iclass 7, count 0 2006.257.21:39:43.97#ibcon#read 5, iclass 7, count 0 2006.257.21:39:43.97#ibcon#about to read 6, iclass 7, count 0 2006.257.21:39:43.97#ibcon#read 6, iclass 7, count 0 2006.257.21:39:43.97#ibcon#end of sib2, iclass 7, count 0 2006.257.21:39:43.97#ibcon#*after write, iclass 7, count 0 2006.257.21:39:43.97#ibcon#*before return 0, iclass 7, count 0 2006.257.21:39:43.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:43.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.21:39:43.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.21:39:43.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.21:39:43.98$vck44/vb=4,5 2006.257.21:39:43.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.21:39:43.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.21:39:43.98#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:43.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:44.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:44.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:44.02#ibcon#enter wrdev, iclass 11, count 2 2006.257.21:39:44.02#ibcon#first serial, iclass 11, count 2 2006.257.21:39:44.02#ibcon#enter sib2, iclass 11, count 2 2006.257.21:39:44.02#ibcon#flushed, iclass 11, count 2 2006.257.21:39:44.02#ibcon#about to write, iclass 11, count 2 2006.257.21:39:44.02#ibcon#wrote, iclass 11, count 2 2006.257.21:39:44.02#ibcon#about to read 3, iclass 11, count 2 2006.257.21:39:44.04#ibcon#read 3, iclass 11, count 2 2006.257.21:39:44.04#ibcon#about to read 4, iclass 11, count 2 2006.257.21:39:44.04#ibcon#read 4, iclass 11, count 2 2006.257.21:39:44.04#ibcon#about to read 5, iclass 11, count 2 2006.257.21:39:44.04#ibcon#read 5, iclass 11, count 2 2006.257.21:39:44.04#ibcon#about to read 6, iclass 11, count 2 2006.257.21:39:44.04#ibcon#read 6, iclass 11, count 2 2006.257.21:39:44.04#ibcon#end of sib2, iclass 11, count 2 2006.257.21:39:44.04#ibcon#*mode == 0, iclass 11, count 2 2006.257.21:39:44.04#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.21:39:44.04#ibcon#[27=AT04-05\r\n] 2006.257.21:39:44.04#ibcon#*before write, iclass 11, count 2 2006.257.21:39:44.04#ibcon#enter sib2, iclass 11, count 2 2006.257.21:39:44.04#ibcon#flushed, iclass 11, count 2 2006.257.21:39:44.04#ibcon#about to write, iclass 11, count 2 2006.257.21:39:44.05#ibcon#wrote, iclass 11, count 2 2006.257.21:39:44.05#ibcon#about to read 3, iclass 11, count 2 2006.257.21:39:44.07#ibcon#read 3, iclass 11, count 2 2006.257.21:39:44.07#ibcon#about to read 4, iclass 11, count 2 2006.257.21:39:44.07#ibcon#read 4, iclass 11, count 2 2006.257.21:39:44.07#ibcon#about to read 5, iclass 11, count 2 2006.257.21:39:44.07#ibcon#read 5, iclass 11, count 2 2006.257.21:39:44.07#ibcon#about to read 6, iclass 11, count 2 2006.257.21:39:44.07#ibcon#read 6, iclass 11, count 2 2006.257.21:39:44.07#ibcon#end of sib2, iclass 11, count 2 2006.257.21:39:44.07#ibcon#*after write, iclass 11, count 2 2006.257.21:39:44.07#ibcon#*before return 0, iclass 11, count 2 2006.257.21:39:44.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:44.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.21:39:44.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.21:39:44.07#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:44.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:44.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:44.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:44.19#ibcon#enter wrdev, iclass 11, count 0 2006.257.21:39:44.19#ibcon#first serial, iclass 11, count 0 2006.257.21:39:44.19#ibcon#enter sib2, iclass 11, count 0 2006.257.21:39:44.19#ibcon#flushed, iclass 11, count 0 2006.257.21:39:44.19#ibcon#about to write, iclass 11, count 0 2006.257.21:39:44.19#ibcon#wrote, iclass 11, count 0 2006.257.21:39:44.19#ibcon#about to read 3, iclass 11, count 0 2006.257.21:39:44.21#ibcon#read 3, iclass 11, count 0 2006.257.21:39:44.21#ibcon#about to read 4, iclass 11, count 0 2006.257.21:39:44.21#ibcon#read 4, iclass 11, count 0 2006.257.21:39:44.21#ibcon#about to read 5, iclass 11, count 0 2006.257.21:39:44.21#ibcon#read 5, iclass 11, count 0 2006.257.21:39:44.21#ibcon#about to read 6, iclass 11, count 0 2006.257.21:39:44.21#ibcon#read 6, iclass 11, count 0 2006.257.21:39:44.21#ibcon#end of sib2, iclass 11, count 0 2006.257.21:39:44.21#ibcon#*mode == 0, iclass 11, count 0 2006.257.21:39:44.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.21:39:44.21#ibcon#[27=USB\r\n] 2006.257.21:39:44.21#ibcon#*before write, iclass 11, count 0 2006.257.21:39:44.21#ibcon#enter sib2, iclass 11, count 0 2006.257.21:39:44.21#ibcon#flushed, iclass 11, count 0 2006.257.21:39:44.21#ibcon#about to write, iclass 11, count 0 2006.257.21:39:44.22#ibcon#wrote, iclass 11, count 0 2006.257.21:39:44.22#ibcon#about to read 3, iclass 11, count 0 2006.257.21:39:44.24#ibcon#read 3, iclass 11, count 0 2006.257.21:39:44.24#ibcon#about to read 4, iclass 11, count 0 2006.257.21:39:44.24#ibcon#read 4, iclass 11, count 0 2006.257.21:39:44.24#ibcon#about to read 5, iclass 11, count 0 2006.257.21:39:44.24#ibcon#read 5, iclass 11, count 0 2006.257.21:39:44.24#ibcon#about to read 6, iclass 11, count 0 2006.257.21:39:44.24#ibcon#read 6, iclass 11, count 0 2006.257.21:39:44.24#ibcon#end of sib2, iclass 11, count 0 2006.257.21:39:44.24#ibcon#*after write, iclass 11, count 0 2006.257.21:39:44.24#ibcon#*before return 0, iclass 11, count 0 2006.257.21:39:44.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:44.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.21:39:44.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.21:39:44.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.21:39:44.25$vck44/vblo=5,709.99 2006.257.21:39:44.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.21:39:44.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.21:39:44.25#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:44.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:44.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:44.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:44.25#ibcon#enter wrdev, iclass 13, count 0 2006.257.21:39:44.25#ibcon#first serial, iclass 13, count 0 2006.257.21:39:44.25#ibcon#enter sib2, iclass 13, count 0 2006.257.21:39:44.25#ibcon#flushed, iclass 13, count 0 2006.257.21:39:44.25#ibcon#about to write, iclass 13, count 0 2006.257.21:39:44.25#ibcon#wrote, iclass 13, count 0 2006.257.21:39:44.25#ibcon#about to read 3, iclass 13, count 0 2006.257.21:39:44.26#ibcon#read 3, iclass 13, count 0 2006.257.21:39:44.26#ibcon#about to read 4, iclass 13, count 0 2006.257.21:39:44.26#ibcon#read 4, iclass 13, count 0 2006.257.21:39:44.26#ibcon#about to read 5, iclass 13, count 0 2006.257.21:39:44.26#ibcon#read 5, iclass 13, count 0 2006.257.21:39:44.26#ibcon#about to read 6, iclass 13, count 0 2006.257.21:39:44.26#ibcon#read 6, iclass 13, count 0 2006.257.21:39:44.26#ibcon#end of sib2, iclass 13, count 0 2006.257.21:39:44.26#ibcon#*mode == 0, iclass 13, count 0 2006.257.21:39:44.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.21:39:44.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.21:39:44.26#ibcon#*before write, iclass 13, count 0 2006.257.21:39:44.26#ibcon#enter sib2, iclass 13, count 0 2006.257.21:39:44.26#ibcon#flushed, iclass 13, count 0 2006.257.21:39:44.26#ibcon#about to write, iclass 13, count 0 2006.257.21:39:44.27#ibcon#wrote, iclass 13, count 0 2006.257.21:39:44.27#ibcon#about to read 3, iclass 13, count 0 2006.257.21:39:44.30#ibcon#read 3, iclass 13, count 0 2006.257.21:39:44.30#ibcon#about to read 4, iclass 13, count 0 2006.257.21:39:44.30#ibcon#read 4, iclass 13, count 0 2006.257.21:39:44.30#ibcon#about to read 5, iclass 13, count 0 2006.257.21:39:44.30#ibcon#read 5, iclass 13, count 0 2006.257.21:39:44.30#ibcon#about to read 6, iclass 13, count 0 2006.257.21:39:44.30#ibcon#read 6, iclass 13, count 0 2006.257.21:39:44.30#ibcon#end of sib2, iclass 13, count 0 2006.257.21:39:44.30#ibcon#*after write, iclass 13, count 0 2006.257.21:39:44.30#ibcon#*before return 0, iclass 13, count 0 2006.257.21:39:44.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:44.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.21:39:44.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.21:39:44.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.21:39:44.31$vck44/vb=5,4 2006.257.21:39:44.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.21:39:44.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.21:39:44.31#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:44.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:44.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:44.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:44.35#ibcon#enter wrdev, iclass 15, count 2 2006.257.21:39:44.35#ibcon#first serial, iclass 15, count 2 2006.257.21:39:44.35#ibcon#enter sib2, iclass 15, count 2 2006.257.21:39:44.35#ibcon#flushed, iclass 15, count 2 2006.257.21:39:44.35#ibcon#about to write, iclass 15, count 2 2006.257.21:39:44.35#ibcon#wrote, iclass 15, count 2 2006.257.21:39:44.35#ibcon#about to read 3, iclass 15, count 2 2006.257.21:39:44.37#ibcon#read 3, iclass 15, count 2 2006.257.21:39:44.37#ibcon#about to read 4, iclass 15, count 2 2006.257.21:39:44.37#ibcon#read 4, iclass 15, count 2 2006.257.21:39:44.37#ibcon#about to read 5, iclass 15, count 2 2006.257.21:39:44.37#ibcon#read 5, iclass 15, count 2 2006.257.21:39:44.37#ibcon#about to read 6, iclass 15, count 2 2006.257.21:39:44.37#ibcon#read 6, iclass 15, count 2 2006.257.21:39:44.37#ibcon#end of sib2, iclass 15, count 2 2006.257.21:39:44.37#ibcon#*mode == 0, iclass 15, count 2 2006.257.21:39:44.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.21:39:44.37#ibcon#[27=AT05-04\r\n] 2006.257.21:39:44.37#ibcon#*before write, iclass 15, count 2 2006.257.21:39:44.37#ibcon#enter sib2, iclass 15, count 2 2006.257.21:39:44.37#ibcon#flushed, iclass 15, count 2 2006.257.21:39:44.37#ibcon#about to write, iclass 15, count 2 2006.257.21:39:44.38#ibcon#wrote, iclass 15, count 2 2006.257.21:39:44.38#ibcon#about to read 3, iclass 15, count 2 2006.257.21:39:44.40#ibcon#read 3, iclass 15, count 2 2006.257.21:39:44.40#ibcon#about to read 4, iclass 15, count 2 2006.257.21:39:44.40#ibcon#read 4, iclass 15, count 2 2006.257.21:39:44.40#ibcon#about to read 5, iclass 15, count 2 2006.257.21:39:44.40#ibcon#read 5, iclass 15, count 2 2006.257.21:39:44.40#ibcon#about to read 6, iclass 15, count 2 2006.257.21:39:44.40#ibcon#read 6, iclass 15, count 2 2006.257.21:39:44.40#ibcon#end of sib2, iclass 15, count 2 2006.257.21:39:44.40#ibcon#*after write, iclass 15, count 2 2006.257.21:39:44.40#ibcon#*before return 0, iclass 15, count 2 2006.257.21:39:44.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:44.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.21:39:44.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.21:39:44.40#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:44.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:44.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:44.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:44.52#ibcon#enter wrdev, iclass 15, count 0 2006.257.21:39:44.52#ibcon#first serial, iclass 15, count 0 2006.257.21:39:44.52#ibcon#enter sib2, iclass 15, count 0 2006.257.21:39:44.52#ibcon#flushed, iclass 15, count 0 2006.257.21:39:44.52#ibcon#about to write, iclass 15, count 0 2006.257.21:39:44.52#ibcon#wrote, iclass 15, count 0 2006.257.21:39:44.52#ibcon#about to read 3, iclass 15, count 0 2006.257.21:39:44.54#ibcon#read 3, iclass 15, count 0 2006.257.21:39:44.54#ibcon#about to read 4, iclass 15, count 0 2006.257.21:39:44.54#ibcon#read 4, iclass 15, count 0 2006.257.21:39:44.54#ibcon#about to read 5, iclass 15, count 0 2006.257.21:39:44.54#ibcon#read 5, iclass 15, count 0 2006.257.21:39:44.54#ibcon#about to read 6, iclass 15, count 0 2006.257.21:39:44.54#ibcon#read 6, iclass 15, count 0 2006.257.21:39:44.54#ibcon#end of sib2, iclass 15, count 0 2006.257.21:39:44.54#ibcon#*mode == 0, iclass 15, count 0 2006.257.21:39:44.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.21:39:44.54#ibcon#[27=USB\r\n] 2006.257.21:39:44.54#ibcon#*before write, iclass 15, count 0 2006.257.21:39:44.54#ibcon#enter sib2, iclass 15, count 0 2006.257.21:39:44.54#ibcon#flushed, iclass 15, count 0 2006.257.21:39:44.54#ibcon#about to write, iclass 15, count 0 2006.257.21:39:44.55#ibcon#wrote, iclass 15, count 0 2006.257.21:39:44.55#ibcon#about to read 3, iclass 15, count 0 2006.257.21:39:44.57#ibcon#read 3, iclass 15, count 0 2006.257.21:39:44.57#ibcon#about to read 4, iclass 15, count 0 2006.257.21:39:44.57#ibcon#read 4, iclass 15, count 0 2006.257.21:39:44.57#ibcon#about to read 5, iclass 15, count 0 2006.257.21:39:44.57#ibcon#read 5, iclass 15, count 0 2006.257.21:39:44.57#ibcon#about to read 6, iclass 15, count 0 2006.257.21:39:44.57#ibcon#read 6, iclass 15, count 0 2006.257.21:39:44.57#ibcon#end of sib2, iclass 15, count 0 2006.257.21:39:44.57#ibcon#*after write, iclass 15, count 0 2006.257.21:39:44.57#ibcon#*before return 0, iclass 15, count 0 2006.257.21:39:44.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:44.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.21:39:44.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.21:39:44.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.21:39:44.58$vck44/vblo=6,719.99 2006.257.21:39:44.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.21:39:44.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.21:39:44.58#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:44.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:44.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:44.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:44.58#ibcon#enter wrdev, iclass 17, count 0 2006.257.21:39:44.58#ibcon#first serial, iclass 17, count 0 2006.257.21:39:44.58#ibcon#enter sib2, iclass 17, count 0 2006.257.21:39:44.58#ibcon#flushed, iclass 17, count 0 2006.257.21:39:44.58#ibcon#about to write, iclass 17, count 0 2006.257.21:39:44.58#ibcon#wrote, iclass 17, count 0 2006.257.21:39:44.58#ibcon#about to read 3, iclass 17, count 0 2006.257.21:39:44.59#ibcon#read 3, iclass 17, count 0 2006.257.21:39:44.59#ibcon#about to read 4, iclass 17, count 0 2006.257.21:39:44.59#ibcon#read 4, iclass 17, count 0 2006.257.21:39:44.59#ibcon#about to read 5, iclass 17, count 0 2006.257.21:39:44.59#ibcon#read 5, iclass 17, count 0 2006.257.21:39:44.59#ibcon#about to read 6, iclass 17, count 0 2006.257.21:39:44.59#ibcon#read 6, iclass 17, count 0 2006.257.21:39:44.59#ibcon#end of sib2, iclass 17, count 0 2006.257.21:39:44.59#ibcon#*mode == 0, iclass 17, count 0 2006.257.21:39:44.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.21:39:44.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.21:39:44.59#ibcon#*before write, iclass 17, count 0 2006.257.21:39:44.59#ibcon#enter sib2, iclass 17, count 0 2006.257.21:39:44.59#ibcon#flushed, iclass 17, count 0 2006.257.21:39:44.59#ibcon#about to write, iclass 17, count 0 2006.257.21:39:44.60#ibcon#wrote, iclass 17, count 0 2006.257.21:39:44.60#ibcon#about to read 3, iclass 17, count 0 2006.257.21:39:44.63#ibcon#read 3, iclass 17, count 0 2006.257.21:39:44.63#ibcon#about to read 4, iclass 17, count 0 2006.257.21:39:44.63#ibcon#read 4, iclass 17, count 0 2006.257.21:39:44.63#ibcon#about to read 5, iclass 17, count 0 2006.257.21:39:44.63#ibcon#read 5, iclass 17, count 0 2006.257.21:39:44.63#ibcon#about to read 6, iclass 17, count 0 2006.257.21:39:44.63#ibcon#read 6, iclass 17, count 0 2006.257.21:39:44.63#ibcon#end of sib2, iclass 17, count 0 2006.257.21:39:44.63#ibcon#*after write, iclass 17, count 0 2006.257.21:39:44.63#ibcon#*before return 0, iclass 17, count 0 2006.257.21:39:44.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:44.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.21:39:44.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.21:39:44.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.21:39:44.64$vck44/vb=6,4 2006.257.21:39:44.64#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.21:39:44.64#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.21:39:44.64#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:44.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:44.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:44.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:44.68#ibcon#enter wrdev, iclass 19, count 2 2006.257.21:39:44.68#ibcon#first serial, iclass 19, count 2 2006.257.21:39:44.68#ibcon#enter sib2, iclass 19, count 2 2006.257.21:39:44.68#ibcon#flushed, iclass 19, count 2 2006.257.21:39:44.68#ibcon#about to write, iclass 19, count 2 2006.257.21:39:44.68#ibcon#wrote, iclass 19, count 2 2006.257.21:39:44.68#ibcon#about to read 3, iclass 19, count 2 2006.257.21:39:44.70#ibcon#read 3, iclass 19, count 2 2006.257.21:39:44.70#ibcon#about to read 4, iclass 19, count 2 2006.257.21:39:44.70#ibcon#read 4, iclass 19, count 2 2006.257.21:39:44.70#ibcon#about to read 5, iclass 19, count 2 2006.257.21:39:44.70#ibcon#read 5, iclass 19, count 2 2006.257.21:39:44.70#ibcon#about to read 6, iclass 19, count 2 2006.257.21:39:44.70#ibcon#read 6, iclass 19, count 2 2006.257.21:39:44.70#ibcon#end of sib2, iclass 19, count 2 2006.257.21:39:44.70#ibcon#*mode == 0, iclass 19, count 2 2006.257.21:39:44.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.21:39:44.70#ibcon#[27=AT06-04\r\n] 2006.257.21:39:44.70#ibcon#*before write, iclass 19, count 2 2006.257.21:39:44.70#ibcon#enter sib2, iclass 19, count 2 2006.257.21:39:44.70#ibcon#flushed, iclass 19, count 2 2006.257.21:39:44.70#ibcon#about to write, iclass 19, count 2 2006.257.21:39:44.71#ibcon#wrote, iclass 19, count 2 2006.257.21:39:44.71#ibcon#about to read 3, iclass 19, count 2 2006.257.21:39:44.73#ibcon#read 3, iclass 19, count 2 2006.257.21:39:44.73#ibcon#about to read 4, iclass 19, count 2 2006.257.21:39:44.73#ibcon#read 4, iclass 19, count 2 2006.257.21:39:44.73#ibcon#about to read 5, iclass 19, count 2 2006.257.21:39:44.73#ibcon#read 5, iclass 19, count 2 2006.257.21:39:44.73#ibcon#about to read 6, iclass 19, count 2 2006.257.21:39:44.73#ibcon#read 6, iclass 19, count 2 2006.257.21:39:44.73#ibcon#end of sib2, iclass 19, count 2 2006.257.21:39:44.73#ibcon#*after write, iclass 19, count 2 2006.257.21:39:44.73#ibcon#*before return 0, iclass 19, count 2 2006.257.21:39:44.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:44.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.21:39:44.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.21:39:44.73#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:44.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:44.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:44.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:44.85#ibcon#enter wrdev, iclass 19, count 0 2006.257.21:39:44.85#ibcon#first serial, iclass 19, count 0 2006.257.21:39:44.85#ibcon#enter sib2, iclass 19, count 0 2006.257.21:39:44.85#ibcon#flushed, iclass 19, count 0 2006.257.21:39:44.85#ibcon#about to write, iclass 19, count 0 2006.257.21:39:44.85#ibcon#wrote, iclass 19, count 0 2006.257.21:39:44.85#ibcon#about to read 3, iclass 19, count 0 2006.257.21:39:44.87#ibcon#read 3, iclass 19, count 0 2006.257.21:39:44.87#ibcon#about to read 4, iclass 19, count 0 2006.257.21:39:44.87#ibcon#read 4, iclass 19, count 0 2006.257.21:39:44.87#ibcon#about to read 5, iclass 19, count 0 2006.257.21:39:44.87#ibcon#read 5, iclass 19, count 0 2006.257.21:39:44.87#ibcon#about to read 6, iclass 19, count 0 2006.257.21:39:44.87#ibcon#read 6, iclass 19, count 0 2006.257.21:39:44.87#ibcon#end of sib2, iclass 19, count 0 2006.257.21:39:44.87#ibcon#*mode == 0, iclass 19, count 0 2006.257.21:39:44.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.21:39:44.87#ibcon#[27=USB\r\n] 2006.257.21:39:44.87#ibcon#*before write, iclass 19, count 0 2006.257.21:39:44.87#ibcon#enter sib2, iclass 19, count 0 2006.257.21:39:44.87#ibcon#flushed, iclass 19, count 0 2006.257.21:39:44.87#ibcon#about to write, iclass 19, count 0 2006.257.21:39:44.88#ibcon#wrote, iclass 19, count 0 2006.257.21:39:44.88#ibcon#about to read 3, iclass 19, count 0 2006.257.21:39:44.90#ibcon#read 3, iclass 19, count 0 2006.257.21:39:44.90#ibcon#about to read 4, iclass 19, count 0 2006.257.21:39:44.90#ibcon#read 4, iclass 19, count 0 2006.257.21:39:44.90#ibcon#about to read 5, iclass 19, count 0 2006.257.21:39:44.90#ibcon#read 5, iclass 19, count 0 2006.257.21:39:44.90#ibcon#about to read 6, iclass 19, count 0 2006.257.21:39:44.90#ibcon#read 6, iclass 19, count 0 2006.257.21:39:44.90#ibcon#end of sib2, iclass 19, count 0 2006.257.21:39:44.90#ibcon#*after write, iclass 19, count 0 2006.257.21:39:44.90#ibcon#*before return 0, iclass 19, count 0 2006.257.21:39:44.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:44.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.21:39:44.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.21:39:44.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.21:39:44.91$vck44/vblo=7,734.99 2006.257.21:39:44.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.21:39:44.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.21:39:44.91#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:44.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:44.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:44.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:44.91#ibcon#enter wrdev, iclass 21, count 0 2006.257.21:39:44.91#ibcon#first serial, iclass 21, count 0 2006.257.21:39:44.91#ibcon#enter sib2, iclass 21, count 0 2006.257.21:39:44.91#ibcon#flushed, iclass 21, count 0 2006.257.21:39:44.91#ibcon#about to write, iclass 21, count 0 2006.257.21:39:44.91#ibcon#wrote, iclass 21, count 0 2006.257.21:39:44.91#ibcon#about to read 3, iclass 21, count 0 2006.257.21:39:44.92#ibcon#read 3, iclass 21, count 0 2006.257.21:39:44.92#ibcon#about to read 4, iclass 21, count 0 2006.257.21:39:44.92#ibcon#read 4, iclass 21, count 0 2006.257.21:39:44.92#ibcon#about to read 5, iclass 21, count 0 2006.257.21:39:44.92#ibcon#read 5, iclass 21, count 0 2006.257.21:39:44.92#ibcon#about to read 6, iclass 21, count 0 2006.257.21:39:44.92#ibcon#read 6, iclass 21, count 0 2006.257.21:39:44.92#ibcon#end of sib2, iclass 21, count 0 2006.257.21:39:44.92#ibcon#*mode == 0, iclass 21, count 0 2006.257.21:39:44.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.21:39:44.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.21:39:44.92#ibcon#*before write, iclass 21, count 0 2006.257.21:39:44.92#ibcon#enter sib2, iclass 21, count 0 2006.257.21:39:44.92#ibcon#flushed, iclass 21, count 0 2006.257.21:39:44.92#ibcon#about to write, iclass 21, count 0 2006.257.21:39:44.93#ibcon#wrote, iclass 21, count 0 2006.257.21:39:44.93#ibcon#about to read 3, iclass 21, count 0 2006.257.21:39:44.96#ibcon#read 3, iclass 21, count 0 2006.257.21:39:44.96#ibcon#about to read 4, iclass 21, count 0 2006.257.21:39:44.96#ibcon#read 4, iclass 21, count 0 2006.257.21:39:44.96#ibcon#about to read 5, iclass 21, count 0 2006.257.21:39:44.96#ibcon#read 5, iclass 21, count 0 2006.257.21:39:44.96#ibcon#about to read 6, iclass 21, count 0 2006.257.21:39:44.96#ibcon#read 6, iclass 21, count 0 2006.257.21:39:44.96#ibcon#end of sib2, iclass 21, count 0 2006.257.21:39:44.96#ibcon#*after write, iclass 21, count 0 2006.257.21:39:44.96#ibcon#*before return 0, iclass 21, count 0 2006.257.21:39:44.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:44.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.21:39:44.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.21:39:44.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.21:39:44.97$vck44/vb=7,4 2006.257.21:39:44.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.21:39:44.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.21:39:44.97#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:44.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:45.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:45.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:45.02#ibcon#enter wrdev, iclass 23, count 2 2006.257.21:39:45.02#ibcon#first serial, iclass 23, count 2 2006.257.21:39:45.02#ibcon#enter sib2, iclass 23, count 2 2006.257.21:39:45.02#ibcon#flushed, iclass 23, count 2 2006.257.21:39:45.02#ibcon#about to write, iclass 23, count 2 2006.257.21:39:45.02#ibcon#wrote, iclass 23, count 2 2006.257.21:39:45.02#ibcon#about to read 3, iclass 23, count 2 2006.257.21:39:45.03#ibcon#read 3, iclass 23, count 2 2006.257.21:39:45.03#ibcon#about to read 4, iclass 23, count 2 2006.257.21:39:45.03#ibcon#read 4, iclass 23, count 2 2006.257.21:39:45.03#ibcon#about to read 5, iclass 23, count 2 2006.257.21:39:45.03#ibcon#read 5, iclass 23, count 2 2006.257.21:39:45.03#ibcon#about to read 6, iclass 23, count 2 2006.257.21:39:45.03#ibcon#read 6, iclass 23, count 2 2006.257.21:39:45.03#ibcon#end of sib2, iclass 23, count 2 2006.257.21:39:45.03#ibcon#*mode == 0, iclass 23, count 2 2006.257.21:39:45.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.21:39:45.03#ibcon#[27=AT07-04\r\n] 2006.257.21:39:45.03#ibcon#*before write, iclass 23, count 2 2006.257.21:39:45.03#ibcon#enter sib2, iclass 23, count 2 2006.257.21:39:45.03#ibcon#flushed, iclass 23, count 2 2006.257.21:39:45.03#ibcon#about to write, iclass 23, count 2 2006.257.21:39:45.04#ibcon#wrote, iclass 23, count 2 2006.257.21:39:45.04#ibcon#about to read 3, iclass 23, count 2 2006.257.21:39:45.06#ibcon#read 3, iclass 23, count 2 2006.257.21:39:45.06#ibcon#about to read 4, iclass 23, count 2 2006.257.21:39:45.06#ibcon#read 4, iclass 23, count 2 2006.257.21:39:45.06#ibcon#about to read 5, iclass 23, count 2 2006.257.21:39:45.06#ibcon#read 5, iclass 23, count 2 2006.257.21:39:45.06#ibcon#about to read 6, iclass 23, count 2 2006.257.21:39:45.06#ibcon#read 6, iclass 23, count 2 2006.257.21:39:45.06#ibcon#end of sib2, iclass 23, count 2 2006.257.21:39:45.06#ibcon#*after write, iclass 23, count 2 2006.257.21:39:45.06#ibcon#*before return 0, iclass 23, count 2 2006.257.21:39:45.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:45.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.21:39:45.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.21:39:45.06#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:45.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:45.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:45.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:45.18#ibcon#enter wrdev, iclass 23, count 0 2006.257.21:39:45.18#ibcon#first serial, iclass 23, count 0 2006.257.21:39:45.18#ibcon#enter sib2, iclass 23, count 0 2006.257.21:39:45.18#ibcon#flushed, iclass 23, count 0 2006.257.21:39:45.18#ibcon#about to write, iclass 23, count 0 2006.257.21:39:45.18#ibcon#wrote, iclass 23, count 0 2006.257.21:39:45.18#ibcon#about to read 3, iclass 23, count 0 2006.257.21:39:45.20#ibcon#read 3, iclass 23, count 0 2006.257.21:39:45.20#ibcon#about to read 4, iclass 23, count 0 2006.257.21:39:45.20#ibcon#read 4, iclass 23, count 0 2006.257.21:39:45.20#ibcon#about to read 5, iclass 23, count 0 2006.257.21:39:45.20#ibcon#read 5, iclass 23, count 0 2006.257.21:39:45.20#ibcon#about to read 6, iclass 23, count 0 2006.257.21:39:45.20#ibcon#read 6, iclass 23, count 0 2006.257.21:39:45.20#ibcon#end of sib2, iclass 23, count 0 2006.257.21:39:45.20#ibcon#*mode == 0, iclass 23, count 0 2006.257.21:39:45.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.21:39:45.20#ibcon#[27=USB\r\n] 2006.257.21:39:45.20#ibcon#*before write, iclass 23, count 0 2006.257.21:39:45.20#ibcon#enter sib2, iclass 23, count 0 2006.257.21:39:45.20#ibcon#flushed, iclass 23, count 0 2006.257.21:39:45.20#ibcon#about to write, iclass 23, count 0 2006.257.21:39:45.21#ibcon#wrote, iclass 23, count 0 2006.257.21:39:45.21#ibcon#about to read 3, iclass 23, count 0 2006.257.21:39:45.23#ibcon#read 3, iclass 23, count 0 2006.257.21:39:45.23#ibcon#about to read 4, iclass 23, count 0 2006.257.21:39:45.23#ibcon#read 4, iclass 23, count 0 2006.257.21:39:45.23#ibcon#about to read 5, iclass 23, count 0 2006.257.21:39:45.23#ibcon#read 5, iclass 23, count 0 2006.257.21:39:45.23#ibcon#about to read 6, iclass 23, count 0 2006.257.21:39:45.23#ibcon#read 6, iclass 23, count 0 2006.257.21:39:45.23#ibcon#end of sib2, iclass 23, count 0 2006.257.21:39:45.23#ibcon#*after write, iclass 23, count 0 2006.257.21:39:45.23#ibcon#*before return 0, iclass 23, count 0 2006.257.21:39:45.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:45.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.21:39:45.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.21:39:45.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.21:39:45.24$vck44/vblo=8,744.99 2006.257.21:39:45.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.21:39:45.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.21:39:45.24#ibcon#ireg 17 cls_cnt 0 2006.257.21:39:45.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:45.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:45.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:45.24#ibcon#enter wrdev, iclass 25, count 0 2006.257.21:39:45.24#ibcon#first serial, iclass 25, count 0 2006.257.21:39:45.24#ibcon#enter sib2, iclass 25, count 0 2006.257.21:39:45.24#ibcon#flushed, iclass 25, count 0 2006.257.21:39:45.24#ibcon#about to write, iclass 25, count 0 2006.257.21:39:45.24#ibcon#wrote, iclass 25, count 0 2006.257.21:39:45.24#ibcon#about to read 3, iclass 25, count 0 2006.257.21:39:45.25#ibcon#read 3, iclass 25, count 0 2006.257.21:39:45.25#ibcon#about to read 4, iclass 25, count 0 2006.257.21:39:45.25#ibcon#read 4, iclass 25, count 0 2006.257.21:39:45.25#ibcon#about to read 5, iclass 25, count 0 2006.257.21:39:45.25#ibcon#read 5, iclass 25, count 0 2006.257.21:39:45.25#ibcon#about to read 6, iclass 25, count 0 2006.257.21:39:45.25#ibcon#read 6, iclass 25, count 0 2006.257.21:39:45.25#ibcon#end of sib2, iclass 25, count 0 2006.257.21:39:45.25#ibcon#*mode == 0, iclass 25, count 0 2006.257.21:39:45.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.21:39:45.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.21:39:45.25#ibcon#*before write, iclass 25, count 0 2006.257.21:39:45.25#ibcon#enter sib2, iclass 25, count 0 2006.257.21:39:45.25#ibcon#flushed, iclass 25, count 0 2006.257.21:39:45.25#ibcon#about to write, iclass 25, count 0 2006.257.21:39:45.26#ibcon#wrote, iclass 25, count 0 2006.257.21:39:45.26#ibcon#about to read 3, iclass 25, count 0 2006.257.21:39:45.29#ibcon#read 3, iclass 25, count 0 2006.257.21:39:45.29#ibcon#about to read 4, iclass 25, count 0 2006.257.21:39:45.29#ibcon#read 4, iclass 25, count 0 2006.257.21:39:45.29#ibcon#about to read 5, iclass 25, count 0 2006.257.21:39:45.29#ibcon#read 5, iclass 25, count 0 2006.257.21:39:45.29#ibcon#about to read 6, iclass 25, count 0 2006.257.21:39:45.29#ibcon#read 6, iclass 25, count 0 2006.257.21:39:45.29#ibcon#end of sib2, iclass 25, count 0 2006.257.21:39:45.29#ibcon#*after write, iclass 25, count 0 2006.257.21:39:45.29#ibcon#*before return 0, iclass 25, count 0 2006.257.21:39:45.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:45.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:39:45.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.21:39:45.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.21:39:45.30$vck44/vb=8,4 2006.257.21:39:45.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.21:39:45.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.21:39:45.30#ibcon#ireg 11 cls_cnt 2 2006.257.21:39:45.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:45.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:45.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:45.34#ibcon#enter wrdev, iclass 27, count 2 2006.257.21:39:45.34#ibcon#first serial, iclass 27, count 2 2006.257.21:39:45.34#ibcon#enter sib2, iclass 27, count 2 2006.257.21:39:45.34#ibcon#flushed, iclass 27, count 2 2006.257.21:39:45.34#ibcon#about to write, iclass 27, count 2 2006.257.21:39:45.34#ibcon#wrote, iclass 27, count 2 2006.257.21:39:45.34#ibcon#about to read 3, iclass 27, count 2 2006.257.21:39:45.36#ibcon#read 3, iclass 27, count 2 2006.257.21:39:45.36#ibcon#about to read 4, iclass 27, count 2 2006.257.21:39:45.36#ibcon#read 4, iclass 27, count 2 2006.257.21:39:45.36#ibcon#about to read 5, iclass 27, count 2 2006.257.21:39:45.36#ibcon#read 5, iclass 27, count 2 2006.257.21:39:45.36#ibcon#about to read 6, iclass 27, count 2 2006.257.21:39:45.36#ibcon#read 6, iclass 27, count 2 2006.257.21:39:45.36#ibcon#end of sib2, iclass 27, count 2 2006.257.21:39:45.36#ibcon#*mode == 0, iclass 27, count 2 2006.257.21:39:45.36#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.21:39:45.36#ibcon#[27=AT08-04\r\n] 2006.257.21:39:45.36#ibcon#*before write, iclass 27, count 2 2006.257.21:39:45.36#ibcon#enter sib2, iclass 27, count 2 2006.257.21:39:45.36#ibcon#flushed, iclass 27, count 2 2006.257.21:39:45.36#ibcon#about to write, iclass 27, count 2 2006.257.21:39:45.37#ibcon#wrote, iclass 27, count 2 2006.257.21:39:45.37#ibcon#about to read 3, iclass 27, count 2 2006.257.21:39:45.39#ibcon#read 3, iclass 27, count 2 2006.257.21:39:45.39#ibcon#about to read 4, iclass 27, count 2 2006.257.21:39:45.39#ibcon#read 4, iclass 27, count 2 2006.257.21:39:45.39#ibcon#about to read 5, iclass 27, count 2 2006.257.21:39:45.39#ibcon#read 5, iclass 27, count 2 2006.257.21:39:45.39#ibcon#about to read 6, iclass 27, count 2 2006.257.21:39:45.39#ibcon#read 6, iclass 27, count 2 2006.257.21:39:45.39#ibcon#end of sib2, iclass 27, count 2 2006.257.21:39:45.39#ibcon#*after write, iclass 27, count 2 2006.257.21:39:45.39#ibcon#*before return 0, iclass 27, count 2 2006.257.21:39:45.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:45.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.21:39:45.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.21:39:45.39#ibcon#ireg 7 cls_cnt 0 2006.257.21:39:45.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:45.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:45.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:45.51#ibcon#enter wrdev, iclass 27, count 0 2006.257.21:39:45.51#ibcon#first serial, iclass 27, count 0 2006.257.21:39:45.51#ibcon#enter sib2, iclass 27, count 0 2006.257.21:39:45.51#ibcon#flushed, iclass 27, count 0 2006.257.21:39:45.51#ibcon#about to write, iclass 27, count 0 2006.257.21:39:45.51#ibcon#wrote, iclass 27, count 0 2006.257.21:39:45.51#ibcon#about to read 3, iclass 27, count 0 2006.257.21:39:45.53#ibcon#read 3, iclass 27, count 0 2006.257.21:39:45.53#ibcon#about to read 4, iclass 27, count 0 2006.257.21:39:45.53#ibcon#read 4, iclass 27, count 0 2006.257.21:39:45.53#ibcon#about to read 5, iclass 27, count 0 2006.257.21:39:45.53#ibcon#read 5, iclass 27, count 0 2006.257.21:39:45.53#ibcon#about to read 6, iclass 27, count 0 2006.257.21:39:45.53#ibcon#read 6, iclass 27, count 0 2006.257.21:39:45.53#ibcon#end of sib2, iclass 27, count 0 2006.257.21:39:45.53#ibcon#*mode == 0, iclass 27, count 0 2006.257.21:39:45.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.21:39:45.53#ibcon#[27=USB\r\n] 2006.257.21:39:45.53#ibcon#*before write, iclass 27, count 0 2006.257.21:39:45.53#ibcon#enter sib2, iclass 27, count 0 2006.257.21:39:45.53#ibcon#flushed, iclass 27, count 0 2006.257.21:39:45.53#ibcon#about to write, iclass 27, count 0 2006.257.21:39:45.54#ibcon#wrote, iclass 27, count 0 2006.257.21:39:45.54#ibcon#about to read 3, iclass 27, count 0 2006.257.21:39:45.56#ibcon#read 3, iclass 27, count 0 2006.257.21:39:45.56#ibcon#about to read 4, iclass 27, count 0 2006.257.21:39:45.56#ibcon#read 4, iclass 27, count 0 2006.257.21:39:45.56#ibcon#about to read 5, iclass 27, count 0 2006.257.21:39:45.56#ibcon#read 5, iclass 27, count 0 2006.257.21:39:45.56#ibcon#about to read 6, iclass 27, count 0 2006.257.21:39:45.56#ibcon#read 6, iclass 27, count 0 2006.257.21:39:45.56#ibcon#end of sib2, iclass 27, count 0 2006.257.21:39:45.56#ibcon#*after write, iclass 27, count 0 2006.257.21:39:45.56#ibcon#*before return 0, iclass 27, count 0 2006.257.21:39:45.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:45.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.21:39:45.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.21:39:45.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.21:39:45.57$vck44/vabw=wide 2006.257.21:39:45.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.21:39:45.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.21:39:45.57#ibcon#ireg 8 cls_cnt 0 2006.257.21:39:45.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:45.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:45.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:45.57#ibcon#enter wrdev, iclass 29, count 0 2006.257.21:39:45.57#ibcon#first serial, iclass 29, count 0 2006.257.21:39:45.57#ibcon#enter sib2, iclass 29, count 0 2006.257.21:39:45.57#ibcon#flushed, iclass 29, count 0 2006.257.21:39:45.57#ibcon#about to write, iclass 29, count 0 2006.257.21:39:45.57#ibcon#wrote, iclass 29, count 0 2006.257.21:39:45.57#ibcon#about to read 3, iclass 29, count 0 2006.257.21:39:45.58#ibcon#read 3, iclass 29, count 0 2006.257.21:39:45.58#ibcon#about to read 4, iclass 29, count 0 2006.257.21:39:45.58#ibcon#read 4, iclass 29, count 0 2006.257.21:39:45.58#ibcon#about to read 5, iclass 29, count 0 2006.257.21:39:45.58#ibcon#read 5, iclass 29, count 0 2006.257.21:39:45.58#ibcon#about to read 6, iclass 29, count 0 2006.257.21:39:45.58#ibcon#read 6, iclass 29, count 0 2006.257.21:39:45.58#ibcon#end of sib2, iclass 29, count 0 2006.257.21:39:45.58#ibcon#*mode == 0, iclass 29, count 0 2006.257.21:39:45.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.21:39:45.58#ibcon#[25=BW32\r\n] 2006.257.21:39:45.58#ibcon#*before write, iclass 29, count 0 2006.257.21:39:45.58#ibcon#enter sib2, iclass 29, count 0 2006.257.21:39:45.58#ibcon#flushed, iclass 29, count 0 2006.257.21:39:45.58#ibcon#about to write, iclass 29, count 0 2006.257.21:39:45.59#ibcon#wrote, iclass 29, count 0 2006.257.21:39:45.59#ibcon#about to read 3, iclass 29, count 0 2006.257.21:39:45.61#ibcon#read 3, iclass 29, count 0 2006.257.21:39:45.61#ibcon#about to read 4, iclass 29, count 0 2006.257.21:39:45.61#ibcon#read 4, iclass 29, count 0 2006.257.21:39:45.61#ibcon#about to read 5, iclass 29, count 0 2006.257.21:39:45.61#ibcon#read 5, iclass 29, count 0 2006.257.21:39:45.61#ibcon#about to read 6, iclass 29, count 0 2006.257.21:39:45.61#ibcon#read 6, iclass 29, count 0 2006.257.21:39:45.61#ibcon#end of sib2, iclass 29, count 0 2006.257.21:39:45.61#ibcon#*after write, iclass 29, count 0 2006.257.21:39:45.61#ibcon#*before return 0, iclass 29, count 0 2006.257.21:39:45.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:45.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.21:39:45.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.21:39:45.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.21:39:45.62$vck44/vbbw=wide 2006.257.21:39:45.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.21:39:45.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.21:39:45.62#ibcon#ireg 8 cls_cnt 0 2006.257.21:39:45.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:39:45.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:39:45.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:39:45.67#ibcon#enter wrdev, iclass 31, count 0 2006.257.21:39:45.67#ibcon#first serial, iclass 31, count 0 2006.257.21:39:45.67#ibcon#enter sib2, iclass 31, count 0 2006.257.21:39:45.67#ibcon#flushed, iclass 31, count 0 2006.257.21:39:45.67#ibcon#about to write, iclass 31, count 0 2006.257.21:39:45.67#ibcon#wrote, iclass 31, count 0 2006.257.21:39:45.67#ibcon#about to read 3, iclass 31, count 0 2006.257.21:39:45.69#ibcon#read 3, iclass 31, count 0 2006.257.21:39:45.69#ibcon#about to read 4, iclass 31, count 0 2006.257.21:39:45.69#ibcon#read 4, iclass 31, count 0 2006.257.21:39:45.69#ibcon#about to read 5, iclass 31, count 0 2006.257.21:39:45.69#ibcon#read 5, iclass 31, count 0 2006.257.21:39:45.69#ibcon#about to read 6, iclass 31, count 0 2006.257.21:39:45.69#ibcon#read 6, iclass 31, count 0 2006.257.21:39:45.69#ibcon#end of sib2, iclass 31, count 0 2006.257.21:39:45.69#ibcon#*mode == 0, iclass 31, count 0 2006.257.21:39:45.69#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.21:39:45.69#ibcon#[27=BW32\r\n] 2006.257.21:39:45.69#ibcon#*before write, iclass 31, count 0 2006.257.21:39:45.69#ibcon#enter sib2, iclass 31, count 0 2006.257.21:39:45.69#ibcon#flushed, iclass 31, count 0 2006.257.21:39:45.69#ibcon#about to write, iclass 31, count 0 2006.257.21:39:45.70#ibcon#wrote, iclass 31, count 0 2006.257.21:39:45.70#ibcon#about to read 3, iclass 31, count 0 2006.257.21:39:45.72#ibcon#read 3, iclass 31, count 0 2006.257.21:39:45.72#ibcon#about to read 4, iclass 31, count 0 2006.257.21:39:45.72#ibcon#read 4, iclass 31, count 0 2006.257.21:39:45.72#ibcon#about to read 5, iclass 31, count 0 2006.257.21:39:45.72#ibcon#read 5, iclass 31, count 0 2006.257.21:39:45.72#ibcon#about to read 6, iclass 31, count 0 2006.257.21:39:45.72#ibcon#read 6, iclass 31, count 0 2006.257.21:39:45.72#ibcon#end of sib2, iclass 31, count 0 2006.257.21:39:45.72#ibcon#*after write, iclass 31, count 0 2006.257.21:39:45.72#ibcon#*before return 0, iclass 31, count 0 2006.257.21:39:45.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:39:45.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:39:45.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.21:39:45.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.21:39:45.73$setupk4/ifdk4 2006.257.21:39:45.73$ifdk4/lo= 2006.257.21:39:45.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.21:39:45.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.21:39:45.73$ifdk4/patch= 2006.257.21:39:45.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.21:39:45.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.21:39:45.73$setupk4/!*+20s 2006.257.21:39:47.95#abcon#<5=/14 1.0 2.5 17.92 951015.4\r\n> 2006.257.21:39:47.97#abcon#{5=INTERFACE CLEAR} 2006.257.21:39:48.03#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:39:58.12#abcon#<5=/14 1.0 2.5 17.92 951015.4\r\n> 2006.257.21:39:58.14#abcon#{5=INTERFACE CLEAR} 2006.257.21:39:58.20#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:40:00.49$setupk4/"tpicd 2006.257.21:40:00.49$setupk4/echo=off 2006.257.21:40:00.49$setupk4/xlog=off 2006.257.21:40:00.50:!2006.257.21:42:56 2006.257.21:40:21.14#trakl#Source acquired 2006.257.21:40:22.15#flagr#flagr/antenna,acquired 2006.257.21:42:56.01:preob 2006.257.21:42:57.13/onsource/TRACKING 2006.257.21:42:57.13:!2006.257.21:43:06 2006.257.21:43:06.00:"tape 2006.257.21:43:06.00:"st=record 2006.257.21:43:06.00:data_valid=on 2006.257.21:43:06.00:midob 2006.257.21:43:06.13/onsource/TRACKING 2006.257.21:43:06.13/wx/17.97,1015.4,94 2006.257.21:43:06.19/cable/+6.4845E-03 2006.257.21:43:07.28/va/01,08,usb,yes,38,41 2006.257.21:43:07.28/va/02,07,usb,yes,41,42 2006.257.21:43:07.28/va/03,08,usb,yes,37,39 2006.257.21:43:07.28/va/04,07,usb,yes,42,44 2006.257.21:43:07.28/va/05,04,usb,yes,38,38 2006.257.21:43:07.28/va/06,04,usb,yes,42,42 2006.257.21:43:07.28/va/07,04,usb,yes,43,44 2006.257.21:43:07.28/va/08,04,usb,yes,36,44 2006.257.21:43:07.51/valo/01,524.99,yes,locked 2006.257.21:43:07.51/valo/02,534.99,yes,locked 2006.257.21:43:07.51/valo/03,564.99,yes,locked 2006.257.21:43:07.51/valo/04,624.99,yes,locked 2006.257.21:43:07.51/valo/05,734.99,yes,locked 2006.257.21:43:07.51/valo/06,814.99,yes,locked 2006.257.21:43:07.51/valo/07,864.99,yes,locked 2006.257.21:43:07.51/valo/08,884.99,yes,locked 2006.257.21:43:08.60/vb/01,04,usb,yes,40,38 2006.257.21:43:08.60/vb/02,05,usb,yes,38,38 2006.257.21:43:08.60/vb/03,04,usb,yes,39,44 2006.257.21:43:08.60/vb/04,05,usb,yes,40,38 2006.257.21:43:08.60/vb/05,04,usb,yes,36,39 2006.257.21:43:08.60/vb/06,04,usb,yes,42,37 2006.257.21:43:08.60/vb/07,04,usb,yes,41,41 2006.257.21:43:08.60/vb/08,04,usb,yes,37,42 2006.257.21:43:08.83/vblo/01,629.99,yes,locked 2006.257.21:43:08.83/vblo/02,634.99,yes,locked 2006.257.21:43:08.83/vblo/03,649.99,yes,locked 2006.257.21:43:08.83/vblo/04,679.99,yes,locked 2006.257.21:43:08.83/vblo/05,709.99,yes,locked 2006.257.21:43:08.83/vblo/06,719.99,yes,locked 2006.257.21:43:08.83/vblo/07,734.99,yes,locked 2006.257.21:43:08.83/vblo/08,744.99,yes,locked 2006.257.21:43:08.98/vabw/8 2006.257.21:43:09.13/vbbw/8 2006.257.21:43:09.22/xfe/off,on,15.2 2006.257.21:43:09.62/ifatt/23,28,28,28 2006.257.21:43:10.07/fmout-gps/S +4.50E-07 2006.257.21:43:10.11:!2006.257.21:45:26 2006.257.21:45:26.01:data_valid=off 2006.257.21:45:26.01:"et 2006.257.21:45:26.01:!+3s 2006.257.21:45:29.02:"tape 2006.257.21:45:29.02:postob 2006.257.21:45:29.16/cable/+6.4856E-03 2006.257.21:45:29.16/wx/18.02,1015.4,94 2006.257.21:45:29.22/fmout-gps/S +4.47E-07 2006.257.21:45:29.22:scan_name=257-2146,jd0609,290 2006.257.21:45:29.22:source=oj287,085448.87,200630.6,2000.0,cw 2006.257.21:45:30.14#flagr#flagr/antenna,new-source 2006.257.21:45:30.14:checkk5 2006.257.21:45:30.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.21:45:30.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.21:45:31.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.21:45:31.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.21:45:31.83/chk_obsdata//k5ts1/T2572143??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.21:45:32.16/chk_obsdata//k5ts2/T2572143??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.21:45:32.50/chk_obsdata//k5ts3/T2572143??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.21:45:32.84/chk_obsdata//k5ts4/T2572143??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.257.21:45:33.50/k5log//k5ts1_log_newline 2006.257.21:45:34.15/k5log//k5ts2_log_newline 2006.257.21:45:34.81/k5log//k5ts3_log_newline 2006.257.21:45:35.47/k5log//k5ts4_log_newline 2006.257.21:45:35.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.21:45:35.49:setupk4=1 2006.257.21:45:35.49$setupk4/echo=on 2006.257.21:45:35.49$setupk4/pcalon 2006.257.21:45:35.49$pcalon/"no phase cal control is implemented here 2006.257.21:45:35.49$setupk4/"tpicd=stop 2006.257.21:45:35.49$setupk4/"rec=synch_on 2006.257.21:45:35.49$setupk4/"rec_mode=128 2006.257.21:45:35.49$setupk4/!* 2006.257.21:45:35.49$setupk4/recpk4 2006.257.21:45:35.50$recpk4/recpatch= 2006.257.21:45:35.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.21:45:35.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.21:45:35.50$setupk4/vck44 2006.257.21:45:35.50$vck44/valo=1,524.99 2006.257.21:45:35.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.21:45:35.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.21:45:35.50#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:35.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:35.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:35.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:35.50#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:45:35.50#ibcon#first serial, iclass 32, count 0 2006.257.21:45:35.50#ibcon#enter sib2, iclass 32, count 0 2006.257.21:45:35.50#ibcon#flushed, iclass 32, count 0 2006.257.21:45:35.50#ibcon#about to write, iclass 32, count 0 2006.257.21:45:35.50#ibcon#wrote, iclass 32, count 0 2006.257.21:45:35.50#ibcon#about to read 3, iclass 32, count 0 2006.257.21:45:35.51#ibcon#read 3, iclass 32, count 0 2006.257.21:45:35.51#ibcon#about to read 4, iclass 32, count 0 2006.257.21:45:35.51#ibcon#read 4, iclass 32, count 0 2006.257.21:45:35.51#ibcon#about to read 5, iclass 32, count 0 2006.257.21:45:35.51#ibcon#read 5, iclass 32, count 0 2006.257.21:45:35.51#ibcon#about to read 6, iclass 32, count 0 2006.257.21:45:35.51#ibcon#read 6, iclass 32, count 0 2006.257.21:45:35.51#ibcon#end of sib2, iclass 32, count 0 2006.257.21:45:35.51#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:45:35.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:45:35.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.21:45:35.51#ibcon#*before write, iclass 32, count 0 2006.257.21:45:35.51#ibcon#enter sib2, iclass 32, count 0 2006.257.21:45:35.51#ibcon#flushed, iclass 32, count 0 2006.257.21:45:35.51#ibcon#about to write, iclass 32, count 0 2006.257.21:45:35.51#ibcon#wrote, iclass 32, count 0 2006.257.21:45:35.51#ibcon#about to read 3, iclass 32, count 0 2006.257.21:45:35.56#ibcon#read 3, iclass 32, count 0 2006.257.21:45:35.56#ibcon#about to read 4, iclass 32, count 0 2006.257.21:45:35.56#ibcon#read 4, iclass 32, count 0 2006.257.21:45:35.56#ibcon#about to read 5, iclass 32, count 0 2006.257.21:45:35.56#ibcon#read 5, iclass 32, count 0 2006.257.21:45:35.56#ibcon#about to read 6, iclass 32, count 0 2006.257.21:45:35.56#ibcon#read 6, iclass 32, count 0 2006.257.21:45:35.56#ibcon#end of sib2, iclass 32, count 0 2006.257.21:45:35.56#ibcon#*after write, iclass 32, count 0 2006.257.21:45:35.56#ibcon#*before return 0, iclass 32, count 0 2006.257.21:45:35.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:35.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:35.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:45:35.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:45:35.56$vck44/va=1,8 2006.257.21:45:35.56#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.21:45:35.56#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.21:45:35.56#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:35.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:35.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:35.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:35.56#ibcon#enter wrdev, iclass 34, count 2 2006.257.21:45:35.56#ibcon#first serial, iclass 34, count 2 2006.257.21:45:35.56#ibcon#enter sib2, iclass 34, count 2 2006.257.21:45:35.56#ibcon#flushed, iclass 34, count 2 2006.257.21:45:35.56#ibcon#about to write, iclass 34, count 2 2006.257.21:45:35.56#ibcon#wrote, iclass 34, count 2 2006.257.21:45:35.56#ibcon#about to read 3, iclass 34, count 2 2006.257.21:45:35.58#ibcon#read 3, iclass 34, count 2 2006.257.21:45:35.58#ibcon#about to read 4, iclass 34, count 2 2006.257.21:45:35.58#ibcon#read 4, iclass 34, count 2 2006.257.21:45:35.58#ibcon#about to read 5, iclass 34, count 2 2006.257.21:45:35.58#ibcon#read 5, iclass 34, count 2 2006.257.21:45:35.58#ibcon#about to read 6, iclass 34, count 2 2006.257.21:45:35.58#ibcon#read 6, iclass 34, count 2 2006.257.21:45:35.58#ibcon#end of sib2, iclass 34, count 2 2006.257.21:45:35.58#ibcon#*mode == 0, iclass 34, count 2 2006.257.21:45:35.58#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.21:45:35.58#ibcon#[25=AT01-08\r\n] 2006.257.21:45:35.58#ibcon#*before write, iclass 34, count 2 2006.257.21:45:35.58#ibcon#enter sib2, iclass 34, count 2 2006.257.21:45:35.58#ibcon#flushed, iclass 34, count 2 2006.257.21:45:35.58#ibcon#about to write, iclass 34, count 2 2006.257.21:45:35.58#ibcon#wrote, iclass 34, count 2 2006.257.21:45:35.58#ibcon#about to read 3, iclass 34, count 2 2006.257.21:45:35.61#ibcon#read 3, iclass 34, count 2 2006.257.21:45:35.61#ibcon#about to read 4, iclass 34, count 2 2006.257.21:45:35.61#ibcon#read 4, iclass 34, count 2 2006.257.21:45:35.61#ibcon#about to read 5, iclass 34, count 2 2006.257.21:45:35.61#ibcon#read 5, iclass 34, count 2 2006.257.21:45:35.61#ibcon#about to read 6, iclass 34, count 2 2006.257.21:45:35.61#ibcon#read 6, iclass 34, count 2 2006.257.21:45:35.61#ibcon#end of sib2, iclass 34, count 2 2006.257.21:45:35.61#ibcon#*after write, iclass 34, count 2 2006.257.21:45:35.61#ibcon#*before return 0, iclass 34, count 2 2006.257.21:45:35.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:35.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:35.61#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.21:45:35.61#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:35.61#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:35.73#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:35.73#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:35.73#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:45:35.73#ibcon#first serial, iclass 34, count 0 2006.257.21:45:35.73#ibcon#enter sib2, iclass 34, count 0 2006.257.21:45:35.73#ibcon#flushed, iclass 34, count 0 2006.257.21:45:35.73#ibcon#about to write, iclass 34, count 0 2006.257.21:45:35.73#ibcon#wrote, iclass 34, count 0 2006.257.21:45:35.73#ibcon#about to read 3, iclass 34, count 0 2006.257.21:45:35.75#ibcon#read 3, iclass 34, count 0 2006.257.21:45:35.75#ibcon#about to read 4, iclass 34, count 0 2006.257.21:45:35.75#ibcon#read 4, iclass 34, count 0 2006.257.21:45:35.75#ibcon#about to read 5, iclass 34, count 0 2006.257.21:45:35.75#ibcon#read 5, iclass 34, count 0 2006.257.21:45:35.75#ibcon#about to read 6, iclass 34, count 0 2006.257.21:45:35.75#ibcon#read 6, iclass 34, count 0 2006.257.21:45:35.75#ibcon#end of sib2, iclass 34, count 0 2006.257.21:45:35.75#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:45:35.75#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:45:35.75#ibcon#[25=USB\r\n] 2006.257.21:45:35.75#ibcon#*before write, iclass 34, count 0 2006.257.21:45:35.75#ibcon#enter sib2, iclass 34, count 0 2006.257.21:45:35.75#ibcon#flushed, iclass 34, count 0 2006.257.21:45:35.75#ibcon#about to write, iclass 34, count 0 2006.257.21:45:35.75#ibcon#wrote, iclass 34, count 0 2006.257.21:45:35.75#ibcon#about to read 3, iclass 34, count 0 2006.257.21:45:35.78#ibcon#read 3, iclass 34, count 0 2006.257.21:45:35.78#ibcon#about to read 4, iclass 34, count 0 2006.257.21:45:35.78#ibcon#read 4, iclass 34, count 0 2006.257.21:45:35.78#ibcon#about to read 5, iclass 34, count 0 2006.257.21:45:35.78#ibcon#read 5, iclass 34, count 0 2006.257.21:45:35.78#ibcon#about to read 6, iclass 34, count 0 2006.257.21:45:35.78#ibcon#read 6, iclass 34, count 0 2006.257.21:45:35.78#ibcon#end of sib2, iclass 34, count 0 2006.257.21:45:35.78#ibcon#*after write, iclass 34, count 0 2006.257.21:45:35.78#ibcon#*before return 0, iclass 34, count 0 2006.257.21:45:35.78#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:35.78#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:35.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:45:35.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:45:35.78$vck44/valo=2,534.99 2006.257.21:45:35.78#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.21:45:35.78#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.21:45:35.78#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:35.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:35.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:35.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:35.78#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:45:35.78#ibcon#first serial, iclass 36, count 0 2006.257.21:45:35.78#ibcon#enter sib2, iclass 36, count 0 2006.257.21:45:35.78#ibcon#flushed, iclass 36, count 0 2006.257.21:45:35.78#ibcon#about to write, iclass 36, count 0 2006.257.21:45:35.78#ibcon#wrote, iclass 36, count 0 2006.257.21:45:35.78#ibcon#about to read 3, iclass 36, count 0 2006.257.21:45:35.80#ibcon#read 3, iclass 36, count 0 2006.257.21:45:35.80#ibcon#about to read 4, iclass 36, count 0 2006.257.21:45:35.80#ibcon#read 4, iclass 36, count 0 2006.257.21:45:35.80#ibcon#about to read 5, iclass 36, count 0 2006.257.21:45:35.80#ibcon#read 5, iclass 36, count 0 2006.257.21:45:35.80#ibcon#about to read 6, iclass 36, count 0 2006.257.21:45:35.80#ibcon#read 6, iclass 36, count 0 2006.257.21:45:35.80#ibcon#end of sib2, iclass 36, count 0 2006.257.21:45:35.80#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:45:35.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:45:35.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.21:45:35.80#ibcon#*before write, iclass 36, count 0 2006.257.21:45:35.80#ibcon#enter sib2, iclass 36, count 0 2006.257.21:45:35.80#ibcon#flushed, iclass 36, count 0 2006.257.21:45:35.80#ibcon#about to write, iclass 36, count 0 2006.257.21:45:35.80#ibcon#wrote, iclass 36, count 0 2006.257.21:45:35.80#ibcon#about to read 3, iclass 36, count 0 2006.257.21:45:35.84#ibcon#read 3, iclass 36, count 0 2006.257.21:45:35.84#ibcon#about to read 4, iclass 36, count 0 2006.257.21:45:35.84#ibcon#read 4, iclass 36, count 0 2006.257.21:45:35.84#ibcon#about to read 5, iclass 36, count 0 2006.257.21:45:35.84#ibcon#read 5, iclass 36, count 0 2006.257.21:45:35.84#ibcon#about to read 6, iclass 36, count 0 2006.257.21:45:35.84#ibcon#read 6, iclass 36, count 0 2006.257.21:45:35.84#ibcon#end of sib2, iclass 36, count 0 2006.257.21:45:35.84#ibcon#*after write, iclass 36, count 0 2006.257.21:45:35.84#ibcon#*before return 0, iclass 36, count 0 2006.257.21:45:35.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:35.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:35.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:45:35.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:45:35.84$vck44/va=2,7 2006.257.21:45:35.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.21:45:35.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.21:45:35.84#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:35.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:35.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:35.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:35.90#ibcon#enter wrdev, iclass 38, count 2 2006.257.21:45:35.90#ibcon#first serial, iclass 38, count 2 2006.257.21:45:35.90#ibcon#enter sib2, iclass 38, count 2 2006.257.21:45:35.90#ibcon#flushed, iclass 38, count 2 2006.257.21:45:35.90#ibcon#about to write, iclass 38, count 2 2006.257.21:45:35.90#ibcon#wrote, iclass 38, count 2 2006.257.21:45:35.90#ibcon#about to read 3, iclass 38, count 2 2006.257.21:45:35.92#ibcon#read 3, iclass 38, count 2 2006.257.21:45:35.92#ibcon#about to read 4, iclass 38, count 2 2006.257.21:45:35.92#ibcon#read 4, iclass 38, count 2 2006.257.21:45:35.92#ibcon#about to read 5, iclass 38, count 2 2006.257.21:45:35.92#ibcon#read 5, iclass 38, count 2 2006.257.21:45:35.92#ibcon#about to read 6, iclass 38, count 2 2006.257.21:45:35.92#ibcon#read 6, iclass 38, count 2 2006.257.21:45:35.92#ibcon#end of sib2, iclass 38, count 2 2006.257.21:45:35.92#ibcon#*mode == 0, iclass 38, count 2 2006.257.21:45:35.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.21:45:35.92#ibcon#[25=AT02-07\r\n] 2006.257.21:45:35.92#ibcon#*before write, iclass 38, count 2 2006.257.21:45:35.92#ibcon#enter sib2, iclass 38, count 2 2006.257.21:45:35.92#ibcon#flushed, iclass 38, count 2 2006.257.21:45:35.92#ibcon#about to write, iclass 38, count 2 2006.257.21:45:35.92#ibcon#wrote, iclass 38, count 2 2006.257.21:45:35.92#ibcon#about to read 3, iclass 38, count 2 2006.257.21:45:35.95#ibcon#read 3, iclass 38, count 2 2006.257.21:45:35.95#ibcon#about to read 4, iclass 38, count 2 2006.257.21:45:35.95#ibcon#read 4, iclass 38, count 2 2006.257.21:45:35.95#ibcon#about to read 5, iclass 38, count 2 2006.257.21:45:35.95#ibcon#read 5, iclass 38, count 2 2006.257.21:45:35.95#ibcon#about to read 6, iclass 38, count 2 2006.257.21:45:35.95#ibcon#read 6, iclass 38, count 2 2006.257.21:45:35.95#ibcon#end of sib2, iclass 38, count 2 2006.257.21:45:35.95#ibcon#*after write, iclass 38, count 2 2006.257.21:45:35.95#ibcon#*before return 0, iclass 38, count 2 2006.257.21:45:35.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:35.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:35.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.21:45:35.95#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:35.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:36.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:36.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:36.07#ibcon#enter wrdev, iclass 38, count 0 2006.257.21:45:36.07#ibcon#first serial, iclass 38, count 0 2006.257.21:45:36.07#ibcon#enter sib2, iclass 38, count 0 2006.257.21:45:36.07#ibcon#flushed, iclass 38, count 0 2006.257.21:45:36.07#ibcon#about to write, iclass 38, count 0 2006.257.21:45:36.07#ibcon#wrote, iclass 38, count 0 2006.257.21:45:36.07#ibcon#about to read 3, iclass 38, count 0 2006.257.21:45:36.09#ibcon#read 3, iclass 38, count 0 2006.257.21:45:36.09#ibcon#about to read 4, iclass 38, count 0 2006.257.21:45:36.09#ibcon#read 4, iclass 38, count 0 2006.257.21:45:36.09#ibcon#about to read 5, iclass 38, count 0 2006.257.21:45:36.09#ibcon#read 5, iclass 38, count 0 2006.257.21:45:36.09#ibcon#about to read 6, iclass 38, count 0 2006.257.21:45:36.09#ibcon#read 6, iclass 38, count 0 2006.257.21:45:36.09#ibcon#end of sib2, iclass 38, count 0 2006.257.21:45:36.09#ibcon#*mode == 0, iclass 38, count 0 2006.257.21:45:36.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.21:45:36.09#ibcon#[25=USB\r\n] 2006.257.21:45:36.09#ibcon#*before write, iclass 38, count 0 2006.257.21:45:36.09#ibcon#enter sib2, iclass 38, count 0 2006.257.21:45:36.09#ibcon#flushed, iclass 38, count 0 2006.257.21:45:36.09#ibcon#about to write, iclass 38, count 0 2006.257.21:45:36.09#ibcon#wrote, iclass 38, count 0 2006.257.21:45:36.09#ibcon#about to read 3, iclass 38, count 0 2006.257.21:45:36.12#ibcon#read 3, iclass 38, count 0 2006.257.21:45:36.12#ibcon#about to read 4, iclass 38, count 0 2006.257.21:45:36.12#ibcon#read 4, iclass 38, count 0 2006.257.21:45:36.12#ibcon#about to read 5, iclass 38, count 0 2006.257.21:45:36.12#ibcon#read 5, iclass 38, count 0 2006.257.21:45:36.12#ibcon#about to read 6, iclass 38, count 0 2006.257.21:45:36.12#ibcon#read 6, iclass 38, count 0 2006.257.21:45:36.12#ibcon#end of sib2, iclass 38, count 0 2006.257.21:45:36.12#ibcon#*after write, iclass 38, count 0 2006.257.21:45:36.12#ibcon#*before return 0, iclass 38, count 0 2006.257.21:45:36.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:36.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:36.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.21:45:36.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.21:45:36.12$vck44/valo=3,564.99 2006.257.21:45:36.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.21:45:36.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.21:45:36.12#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:36.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:36.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:36.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:36.12#ibcon#enter wrdev, iclass 40, count 0 2006.257.21:45:36.12#ibcon#first serial, iclass 40, count 0 2006.257.21:45:36.12#ibcon#enter sib2, iclass 40, count 0 2006.257.21:45:36.12#ibcon#flushed, iclass 40, count 0 2006.257.21:45:36.12#ibcon#about to write, iclass 40, count 0 2006.257.21:45:36.12#ibcon#wrote, iclass 40, count 0 2006.257.21:45:36.12#ibcon#about to read 3, iclass 40, count 0 2006.257.21:45:36.14#ibcon#read 3, iclass 40, count 0 2006.257.21:45:36.14#ibcon#about to read 4, iclass 40, count 0 2006.257.21:45:36.14#ibcon#read 4, iclass 40, count 0 2006.257.21:45:36.14#ibcon#about to read 5, iclass 40, count 0 2006.257.21:45:36.14#ibcon#read 5, iclass 40, count 0 2006.257.21:45:36.14#ibcon#about to read 6, iclass 40, count 0 2006.257.21:45:36.14#ibcon#read 6, iclass 40, count 0 2006.257.21:45:36.14#ibcon#end of sib2, iclass 40, count 0 2006.257.21:45:36.14#ibcon#*mode == 0, iclass 40, count 0 2006.257.21:45:36.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.21:45:36.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.21:45:36.14#ibcon#*before write, iclass 40, count 0 2006.257.21:45:36.14#ibcon#enter sib2, iclass 40, count 0 2006.257.21:45:36.14#ibcon#flushed, iclass 40, count 0 2006.257.21:45:36.14#ibcon#about to write, iclass 40, count 0 2006.257.21:45:36.14#ibcon#wrote, iclass 40, count 0 2006.257.21:45:36.14#ibcon#about to read 3, iclass 40, count 0 2006.257.21:45:36.18#ibcon#read 3, iclass 40, count 0 2006.257.21:45:36.18#ibcon#about to read 4, iclass 40, count 0 2006.257.21:45:36.18#ibcon#read 4, iclass 40, count 0 2006.257.21:45:36.18#ibcon#about to read 5, iclass 40, count 0 2006.257.21:45:36.18#ibcon#read 5, iclass 40, count 0 2006.257.21:45:36.18#ibcon#about to read 6, iclass 40, count 0 2006.257.21:45:36.18#ibcon#read 6, iclass 40, count 0 2006.257.21:45:36.18#ibcon#end of sib2, iclass 40, count 0 2006.257.21:45:36.18#ibcon#*after write, iclass 40, count 0 2006.257.21:45:36.18#ibcon#*before return 0, iclass 40, count 0 2006.257.21:45:36.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:36.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:36.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.21:45:36.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.21:45:36.18$vck44/va=3,8 2006.257.21:45:36.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.21:45:36.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.21:45:36.18#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:36.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:36.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:36.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:36.24#ibcon#enter wrdev, iclass 4, count 2 2006.257.21:45:36.24#ibcon#first serial, iclass 4, count 2 2006.257.21:45:36.24#ibcon#enter sib2, iclass 4, count 2 2006.257.21:45:36.24#ibcon#flushed, iclass 4, count 2 2006.257.21:45:36.24#ibcon#about to write, iclass 4, count 2 2006.257.21:45:36.24#ibcon#wrote, iclass 4, count 2 2006.257.21:45:36.24#ibcon#about to read 3, iclass 4, count 2 2006.257.21:45:36.26#ibcon#read 3, iclass 4, count 2 2006.257.21:45:36.26#ibcon#about to read 4, iclass 4, count 2 2006.257.21:45:36.26#ibcon#read 4, iclass 4, count 2 2006.257.21:45:36.26#ibcon#about to read 5, iclass 4, count 2 2006.257.21:45:36.26#ibcon#read 5, iclass 4, count 2 2006.257.21:45:36.26#ibcon#about to read 6, iclass 4, count 2 2006.257.21:45:36.26#ibcon#read 6, iclass 4, count 2 2006.257.21:45:36.26#ibcon#end of sib2, iclass 4, count 2 2006.257.21:45:36.26#ibcon#*mode == 0, iclass 4, count 2 2006.257.21:45:36.26#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.21:45:36.26#ibcon#[25=AT03-08\r\n] 2006.257.21:45:36.26#ibcon#*before write, iclass 4, count 2 2006.257.21:45:36.26#ibcon#enter sib2, iclass 4, count 2 2006.257.21:45:36.26#ibcon#flushed, iclass 4, count 2 2006.257.21:45:36.26#ibcon#about to write, iclass 4, count 2 2006.257.21:45:36.26#ibcon#wrote, iclass 4, count 2 2006.257.21:45:36.26#ibcon#about to read 3, iclass 4, count 2 2006.257.21:45:36.29#ibcon#read 3, iclass 4, count 2 2006.257.21:45:36.29#ibcon#about to read 4, iclass 4, count 2 2006.257.21:45:36.29#ibcon#read 4, iclass 4, count 2 2006.257.21:45:36.29#ibcon#about to read 5, iclass 4, count 2 2006.257.21:45:36.29#ibcon#read 5, iclass 4, count 2 2006.257.21:45:36.29#ibcon#about to read 6, iclass 4, count 2 2006.257.21:45:36.29#ibcon#read 6, iclass 4, count 2 2006.257.21:45:36.29#ibcon#end of sib2, iclass 4, count 2 2006.257.21:45:36.29#ibcon#*after write, iclass 4, count 2 2006.257.21:45:36.29#ibcon#*before return 0, iclass 4, count 2 2006.257.21:45:36.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:36.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:36.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.21:45:36.29#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:36.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:36.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:36.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:36.41#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:45:36.41#ibcon#first serial, iclass 4, count 0 2006.257.21:45:36.41#ibcon#enter sib2, iclass 4, count 0 2006.257.21:45:36.41#ibcon#flushed, iclass 4, count 0 2006.257.21:45:36.41#ibcon#about to write, iclass 4, count 0 2006.257.21:45:36.41#ibcon#wrote, iclass 4, count 0 2006.257.21:45:36.41#ibcon#about to read 3, iclass 4, count 0 2006.257.21:45:36.43#ibcon#read 3, iclass 4, count 0 2006.257.21:45:36.43#ibcon#about to read 4, iclass 4, count 0 2006.257.21:45:36.43#ibcon#read 4, iclass 4, count 0 2006.257.21:45:36.43#ibcon#about to read 5, iclass 4, count 0 2006.257.21:45:36.43#ibcon#read 5, iclass 4, count 0 2006.257.21:45:36.43#ibcon#about to read 6, iclass 4, count 0 2006.257.21:45:36.43#ibcon#read 6, iclass 4, count 0 2006.257.21:45:36.43#ibcon#end of sib2, iclass 4, count 0 2006.257.21:45:36.43#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:45:36.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:45:36.43#ibcon#[25=USB\r\n] 2006.257.21:45:36.43#ibcon#*before write, iclass 4, count 0 2006.257.21:45:36.43#ibcon#enter sib2, iclass 4, count 0 2006.257.21:45:36.43#ibcon#flushed, iclass 4, count 0 2006.257.21:45:36.43#ibcon#about to write, iclass 4, count 0 2006.257.21:45:36.43#ibcon#wrote, iclass 4, count 0 2006.257.21:45:36.43#ibcon#about to read 3, iclass 4, count 0 2006.257.21:45:36.46#ibcon#read 3, iclass 4, count 0 2006.257.21:45:36.46#ibcon#about to read 4, iclass 4, count 0 2006.257.21:45:36.46#ibcon#read 4, iclass 4, count 0 2006.257.21:45:36.46#ibcon#about to read 5, iclass 4, count 0 2006.257.21:45:36.46#ibcon#read 5, iclass 4, count 0 2006.257.21:45:36.46#ibcon#about to read 6, iclass 4, count 0 2006.257.21:45:36.46#ibcon#read 6, iclass 4, count 0 2006.257.21:45:36.46#ibcon#end of sib2, iclass 4, count 0 2006.257.21:45:36.46#ibcon#*after write, iclass 4, count 0 2006.257.21:45:36.46#ibcon#*before return 0, iclass 4, count 0 2006.257.21:45:36.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:36.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:36.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:45:36.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:45:36.46$vck44/valo=4,624.99 2006.257.21:45:36.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.21:45:36.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.21:45:36.46#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:36.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:36.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:36.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:36.46#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:45:36.46#ibcon#first serial, iclass 6, count 0 2006.257.21:45:36.46#ibcon#enter sib2, iclass 6, count 0 2006.257.21:45:36.46#ibcon#flushed, iclass 6, count 0 2006.257.21:45:36.46#ibcon#about to write, iclass 6, count 0 2006.257.21:45:36.46#ibcon#wrote, iclass 6, count 0 2006.257.21:45:36.46#ibcon#about to read 3, iclass 6, count 0 2006.257.21:45:36.48#ibcon#read 3, iclass 6, count 0 2006.257.21:45:36.48#ibcon#about to read 4, iclass 6, count 0 2006.257.21:45:36.48#ibcon#read 4, iclass 6, count 0 2006.257.21:45:36.48#ibcon#about to read 5, iclass 6, count 0 2006.257.21:45:36.48#ibcon#read 5, iclass 6, count 0 2006.257.21:45:36.48#ibcon#about to read 6, iclass 6, count 0 2006.257.21:45:36.48#ibcon#read 6, iclass 6, count 0 2006.257.21:45:36.48#ibcon#end of sib2, iclass 6, count 0 2006.257.21:45:36.48#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:45:36.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:45:36.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.21:45:36.48#ibcon#*before write, iclass 6, count 0 2006.257.21:45:36.48#ibcon#enter sib2, iclass 6, count 0 2006.257.21:45:36.48#ibcon#flushed, iclass 6, count 0 2006.257.21:45:36.48#ibcon#about to write, iclass 6, count 0 2006.257.21:45:36.48#ibcon#wrote, iclass 6, count 0 2006.257.21:45:36.48#ibcon#about to read 3, iclass 6, count 0 2006.257.21:45:36.52#ibcon#read 3, iclass 6, count 0 2006.257.21:45:36.52#ibcon#about to read 4, iclass 6, count 0 2006.257.21:45:36.52#ibcon#read 4, iclass 6, count 0 2006.257.21:45:36.52#ibcon#about to read 5, iclass 6, count 0 2006.257.21:45:36.52#ibcon#read 5, iclass 6, count 0 2006.257.21:45:36.52#ibcon#about to read 6, iclass 6, count 0 2006.257.21:45:36.52#ibcon#read 6, iclass 6, count 0 2006.257.21:45:36.52#ibcon#end of sib2, iclass 6, count 0 2006.257.21:45:36.52#ibcon#*after write, iclass 6, count 0 2006.257.21:45:36.52#ibcon#*before return 0, iclass 6, count 0 2006.257.21:45:36.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:36.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:36.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:45:36.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:45:36.52$vck44/va=4,7 2006.257.21:45:36.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.21:45:36.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.21:45:36.52#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:36.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:36.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:36.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:36.58#ibcon#enter wrdev, iclass 10, count 2 2006.257.21:45:36.58#ibcon#first serial, iclass 10, count 2 2006.257.21:45:36.58#ibcon#enter sib2, iclass 10, count 2 2006.257.21:45:36.58#ibcon#flushed, iclass 10, count 2 2006.257.21:45:36.58#ibcon#about to write, iclass 10, count 2 2006.257.21:45:36.58#ibcon#wrote, iclass 10, count 2 2006.257.21:45:36.58#ibcon#about to read 3, iclass 10, count 2 2006.257.21:45:36.60#ibcon#read 3, iclass 10, count 2 2006.257.21:45:36.60#ibcon#about to read 4, iclass 10, count 2 2006.257.21:45:36.60#ibcon#read 4, iclass 10, count 2 2006.257.21:45:36.60#ibcon#about to read 5, iclass 10, count 2 2006.257.21:45:36.60#ibcon#read 5, iclass 10, count 2 2006.257.21:45:36.60#ibcon#about to read 6, iclass 10, count 2 2006.257.21:45:36.60#ibcon#read 6, iclass 10, count 2 2006.257.21:45:36.60#ibcon#end of sib2, iclass 10, count 2 2006.257.21:45:36.60#ibcon#*mode == 0, iclass 10, count 2 2006.257.21:45:36.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.21:45:36.60#ibcon#[25=AT04-07\r\n] 2006.257.21:45:36.60#ibcon#*before write, iclass 10, count 2 2006.257.21:45:36.60#ibcon#enter sib2, iclass 10, count 2 2006.257.21:45:36.60#ibcon#flushed, iclass 10, count 2 2006.257.21:45:36.60#ibcon#about to write, iclass 10, count 2 2006.257.21:45:36.60#ibcon#wrote, iclass 10, count 2 2006.257.21:45:36.60#ibcon#about to read 3, iclass 10, count 2 2006.257.21:45:36.63#ibcon#read 3, iclass 10, count 2 2006.257.21:45:36.63#ibcon#about to read 4, iclass 10, count 2 2006.257.21:45:36.63#ibcon#read 4, iclass 10, count 2 2006.257.21:45:36.63#ibcon#about to read 5, iclass 10, count 2 2006.257.21:45:36.63#ibcon#read 5, iclass 10, count 2 2006.257.21:45:36.63#ibcon#about to read 6, iclass 10, count 2 2006.257.21:45:36.63#ibcon#read 6, iclass 10, count 2 2006.257.21:45:36.63#ibcon#end of sib2, iclass 10, count 2 2006.257.21:45:36.63#ibcon#*after write, iclass 10, count 2 2006.257.21:45:36.63#ibcon#*before return 0, iclass 10, count 2 2006.257.21:45:36.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:36.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:36.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.21:45:36.63#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:36.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:36.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:36.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:36.75#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:45:36.75#ibcon#first serial, iclass 10, count 0 2006.257.21:45:36.75#ibcon#enter sib2, iclass 10, count 0 2006.257.21:45:36.75#ibcon#flushed, iclass 10, count 0 2006.257.21:45:36.75#ibcon#about to write, iclass 10, count 0 2006.257.21:45:36.75#ibcon#wrote, iclass 10, count 0 2006.257.21:45:36.75#ibcon#about to read 3, iclass 10, count 0 2006.257.21:45:36.77#ibcon#read 3, iclass 10, count 0 2006.257.21:45:36.77#ibcon#about to read 4, iclass 10, count 0 2006.257.21:45:36.77#ibcon#read 4, iclass 10, count 0 2006.257.21:45:36.77#ibcon#about to read 5, iclass 10, count 0 2006.257.21:45:36.77#ibcon#read 5, iclass 10, count 0 2006.257.21:45:36.77#ibcon#about to read 6, iclass 10, count 0 2006.257.21:45:36.77#ibcon#read 6, iclass 10, count 0 2006.257.21:45:36.77#ibcon#end of sib2, iclass 10, count 0 2006.257.21:45:36.77#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:45:36.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:45:36.77#ibcon#[25=USB\r\n] 2006.257.21:45:36.77#ibcon#*before write, iclass 10, count 0 2006.257.21:45:36.77#ibcon#enter sib2, iclass 10, count 0 2006.257.21:45:36.77#ibcon#flushed, iclass 10, count 0 2006.257.21:45:36.77#ibcon#about to write, iclass 10, count 0 2006.257.21:45:36.77#ibcon#wrote, iclass 10, count 0 2006.257.21:45:36.77#ibcon#about to read 3, iclass 10, count 0 2006.257.21:45:36.80#ibcon#read 3, iclass 10, count 0 2006.257.21:45:36.80#ibcon#about to read 4, iclass 10, count 0 2006.257.21:45:36.80#ibcon#read 4, iclass 10, count 0 2006.257.21:45:36.80#ibcon#about to read 5, iclass 10, count 0 2006.257.21:45:36.80#ibcon#read 5, iclass 10, count 0 2006.257.21:45:36.80#ibcon#about to read 6, iclass 10, count 0 2006.257.21:45:36.80#ibcon#read 6, iclass 10, count 0 2006.257.21:45:36.80#ibcon#end of sib2, iclass 10, count 0 2006.257.21:45:36.80#ibcon#*after write, iclass 10, count 0 2006.257.21:45:36.80#ibcon#*before return 0, iclass 10, count 0 2006.257.21:45:36.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:36.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:36.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:45:36.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:45:36.80$vck44/valo=5,734.99 2006.257.21:45:36.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.21:45:36.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.21:45:36.80#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:36.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:36.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:36.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:36.80#ibcon#enter wrdev, iclass 12, count 0 2006.257.21:45:36.80#ibcon#first serial, iclass 12, count 0 2006.257.21:45:36.80#ibcon#enter sib2, iclass 12, count 0 2006.257.21:45:36.80#ibcon#flushed, iclass 12, count 0 2006.257.21:45:36.80#ibcon#about to write, iclass 12, count 0 2006.257.21:45:36.80#ibcon#wrote, iclass 12, count 0 2006.257.21:45:36.80#ibcon#about to read 3, iclass 12, count 0 2006.257.21:45:36.82#ibcon#read 3, iclass 12, count 0 2006.257.21:45:36.82#ibcon#about to read 4, iclass 12, count 0 2006.257.21:45:36.82#ibcon#read 4, iclass 12, count 0 2006.257.21:45:36.82#ibcon#about to read 5, iclass 12, count 0 2006.257.21:45:36.82#ibcon#read 5, iclass 12, count 0 2006.257.21:45:36.82#ibcon#about to read 6, iclass 12, count 0 2006.257.21:45:36.82#ibcon#read 6, iclass 12, count 0 2006.257.21:45:36.82#ibcon#end of sib2, iclass 12, count 0 2006.257.21:45:36.82#ibcon#*mode == 0, iclass 12, count 0 2006.257.21:45:36.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.21:45:36.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.21:45:36.82#ibcon#*before write, iclass 12, count 0 2006.257.21:45:36.82#ibcon#enter sib2, iclass 12, count 0 2006.257.21:45:36.82#ibcon#flushed, iclass 12, count 0 2006.257.21:45:36.82#ibcon#about to write, iclass 12, count 0 2006.257.21:45:36.82#ibcon#wrote, iclass 12, count 0 2006.257.21:45:36.82#ibcon#about to read 3, iclass 12, count 0 2006.257.21:45:36.86#ibcon#read 3, iclass 12, count 0 2006.257.21:45:36.86#ibcon#about to read 4, iclass 12, count 0 2006.257.21:45:36.86#ibcon#read 4, iclass 12, count 0 2006.257.21:45:36.86#ibcon#about to read 5, iclass 12, count 0 2006.257.21:45:36.86#ibcon#read 5, iclass 12, count 0 2006.257.21:45:36.86#ibcon#about to read 6, iclass 12, count 0 2006.257.21:45:36.86#ibcon#read 6, iclass 12, count 0 2006.257.21:45:36.86#ibcon#end of sib2, iclass 12, count 0 2006.257.21:45:36.86#ibcon#*after write, iclass 12, count 0 2006.257.21:45:36.86#ibcon#*before return 0, iclass 12, count 0 2006.257.21:45:36.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:36.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:36.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.21:45:36.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.21:45:36.86$vck44/va=5,4 2006.257.21:45:36.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.21:45:36.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.21:45:36.86#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:36.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:36.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:36.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:36.92#ibcon#enter wrdev, iclass 14, count 2 2006.257.21:45:36.92#ibcon#first serial, iclass 14, count 2 2006.257.21:45:36.92#ibcon#enter sib2, iclass 14, count 2 2006.257.21:45:36.92#ibcon#flushed, iclass 14, count 2 2006.257.21:45:36.92#ibcon#about to write, iclass 14, count 2 2006.257.21:45:36.92#ibcon#wrote, iclass 14, count 2 2006.257.21:45:36.92#ibcon#about to read 3, iclass 14, count 2 2006.257.21:45:36.94#ibcon#read 3, iclass 14, count 2 2006.257.21:45:36.94#ibcon#about to read 4, iclass 14, count 2 2006.257.21:45:36.94#ibcon#read 4, iclass 14, count 2 2006.257.21:45:36.94#ibcon#about to read 5, iclass 14, count 2 2006.257.21:45:36.94#ibcon#read 5, iclass 14, count 2 2006.257.21:45:36.94#ibcon#about to read 6, iclass 14, count 2 2006.257.21:45:36.94#ibcon#read 6, iclass 14, count 2 2006.257.21:45:36.94#ibcon#end of sib2, iclass 14, count 2 2006.257.21:45:36.94#ibcon#*mode == 0, iclass 14, count 2 2006.257.21:45:36.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.21:45:36.94#ibcon#[25=AT05-04\r\n] 2006.257.21:45:36.94#ibcon#*before write, iclass 14, count 2 2006.257.21:45:36.94#ibcon#enter sib2, iclass 14, count 2 2006.257.21:45:36.94#ibcon#flushed, iclass 14, count 2 2006.257.21:45:36.94#ibcon#about to write, iclass 14, count 2 2006.257.21:45:36.94#ibcon#wrote, iclass 14, count 2 2006.257.21:45:36.94#ibcon#about to read 3, iclass 14, count 2 2006.257.21:45:36.97#ibcon#read 3, iclass 14, count 2 2006.257.21:45:36.97#ibcon#about to read 4, iclass 14, count 2 2006.257.21:45:36.97#ibcon#read 4, iclass 14, count 2 2006.257.21:45:36.97#ibcon#about to read 5, iclass 14, count 2 2006.257.21:45:36.97#ibcon#read 5, iclass 14, count 2 2006.257.21:45:36.97#ibcon#about to read 6, iclass 14, count 2 2006.257.21:45:36.97#ibcon#read 6, iclass 14, count 2 2006.257.21:45:36.97#ibcon#end of sib2, iclass 14, count 2 2006.257.21:45:36.97#ibcon#*after write, iclass 14, count 2 2006.257.21:45:36.97#ibcon#*before return 0, iclass 14, count 2 2006.257.21:45:36.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:36.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:36.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.21:45:36.97#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:36.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:37.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:37.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:37.09#ibcon#enter wrdev, iclass 14, count 0 2006.257.21:45:37.09#ibcon#first serial, iclass 14, count 0 2006.257.21:45:37.09#ibcon#enter sib2, iclass 14, count 0 2006.257.21:45:37.09#ibcon#flushed, iclass 14, count 0 2006.257.21:45:37.09#ibcon#about to write, iclass 14, count 0 2006.257.21:45:37.09#ibcon#wrote, iclass 14, count 0 2006.257.21:45:37.09#ibcon#about to read 3, iclass 14, count 0 2006.257.21:45:37.11#ibcon#read 3, iclass 14, count 0 2006.257.21:45:37.11#ibcon#about to read 4, iclass 14, count 0 2006.257.21:45:37.11#ibcon#read 4, iclass 14, count 0 2006.257.21:45:37.11#ibcon#about to read 5, iclass 14, count 0 2006.257.21:45:37.11#ibcon#read 5, iclass 14, count 0 2006.257.21:45:37.11#ibcon#about to read 6, iclass 14, count 0 2006.257.21:45:37.11#ibcon#read 6, iclass 14, count 0 2006.257.21:45:37.11#ibcon#end of sib2, iclass 14, count 0 2006.257.21:45:37.11#ibcon#*mode == 0, iclass 14, count 0 2006.257.21:45:37.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.21:45:37.11#ibcon#[25=USB\r\n] 2006.257.21:45:37.11#ibcon#*before write, iclass 14, count 0 2006.257.21:45:37.11#ibcon#enter sib2, iclass 14, count 0 2006.257.21:45:37.11#ibcon#flushed, iclass 14, count 0 2006.257.21:45:37.11#ibcon#about to write, iclass 14, count 0 2006.257.21:45:37.11#ibcon#wrote, iclass 14, count 0 2006.257.21:45:37.11#ibcon#about to read 3, iclass 14, count 0 2006.257.21:45:37.14#ibcon#read 3, iclass 14, count 0 2006.257.21:45:37.14#ibcon#about to read 4, iclass 14, count 0 2006.257.21:45:37.14#ibcon#read 4, iclass 14, count 0 2006.257.21:45:37.14#ibcon#about to read 5, iclass 14, count 0 2006.257.21:45:37.14#ibcon#read 5, iclass 14, count 0 2006.257.21:45:37.14#ibcon#about to read 6, iclass 14, count 0 2006.257.21:45:37.14#ibcon#read 6, iclass 14, count 0 2006.257.21:45:37.14#ibcon#end of sib2, iclass 14, count 0 2006.257.21:45:37.14#ibcon#*after write, iclass 14, count 0 2006.257.21:45:37.14#ibcon#*before return 0, iclass 14, count 0 2006.257.21:45:37.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:37.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:37.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.21:45:37.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.21:45:37.14$vck44/valo=6,814.99 2006.257.21:45:37.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.21:45:37.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.21:45:37.14#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:37.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:37.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:37.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:37.14#ibcon#enter wrdev, iclass 16, count 0 2006.257.21:45:37.14#ibcon#first serial, iclass 16, count 0 2006.257.21:45:37.14#ibcon#enter sib2, iclass 16, count 0 2006.257.21:45:37.14#ibcon#flushed, iclass 16, count 0 2006.257.21:45:37.14#ibcon#about to write, iclass 16, count 0 2006.257.21:45:37.14#ibcon#wrote, iclass 16, count 0 2006.257.21:45:37.14#ibcon#about to read 3, iclass 16, count 0 2006.257.21:45:37.16#ibcon#read 3, iclass 16, count 0 2006.257.21:45:37.16#ibcon#about to read 4, iclass 16, count 0 2006.257.21:45:37.16#ibcon#read 4, iclass 16, count 0 2006.257.21:45:37.16#ibcon#about to read 5, iclass 16, count 0 2006.257.21:45:37.16#ibcon#read 5, iclass 16, count 0 2006.257.21:45:37.16#ibcon#about to read 6, iclass 16, count 0 2006.257.21:45:37.16#ibcon#read 6, iclass 16, count 0 2006.257.21:45:37.16#ibcon#end of sib2, iclass 16, count 0 2006.257.21:45:37.16#ibcon#*mode == 0, iclass 16, count 0 2006.257.21:45:37.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.21:45:37.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.21:45:37.16#ibcon#*before write, iclass 16, count 0 2006.257.21:45:37.16#ibcon#enter sib2, iclass 16, count 0 2006.257.21:45:37.16#ibcon#flushed, iclass 16, count 0 2006.257.21:45:37.16#ibcon#about to write, iclass 16, count 0 2006.257.21:45:37.16#ibcon#wrote, iclass 16, count 0 2006.257.21:45:37.16#ibcon#about to read 3, iclass 16, count 0 2006.257.21:45:37.20#ibcon#read 3, iclass 16, count 0 2006.257.21:45:37.20#ibcon#about to read 4, iclass 16, count 0 2006.257.21:45:37.20#ibcon#read 4, iclass 16, count 0 2006.257.21:45:37.20#ibcon#about to read 5, iclass 16, count 0 2006.257.21:45:37.20#ibcon#read 5, iclass 16, count 0 2006.257.21:45:37.20#ibcon#about to read 6, iclass 16, count 0 2006.257.21:45:37.20#ibcon#read 6, iclass 16, count 0 2006.257.21:45:37.20#ibcon#end of sib2, iclass 16, count 0 2006.257.21:45:37.20#ibcon#*after write, iclass 16, count 0 2006.257.21:45:37.20#ibcon#*before return 0, iclass 16, count 0 2006.257.21:45:37.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:37.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:37.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.21:45:37.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.21:45:37.20$vck44/va=6,4 2006.257.21:45:37.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.21:45:37.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.21:45:37.20#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:37.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:37.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:37.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:37.26#ibcon#enter wrdev, iclass 18, count 2 2006.257.21:45:37.26#ibcon#first serial, iclass 18, count 2 2006.257.21:45:37.26#ibcon#enter sib2, iclass 18, count 2 2006.257.21:45:37.26#ibcon#flushed, iclass 18, count 2 2006.257.21:45:37.26#ibcon#about to write, iclass 18, count 2 2006.257.21:45:37.26#ibcon#wrote, iclass 18, count 2 2006.257.21:45:37.26#ibcon#about to read 3, iclass 18, count 2 2006.257.21:45:37.28#ibcon#read 3, iclass 18, count 2 2006.257.21:45:37.28#ibcon#about to read 4, iclass 18, count 2 2006.257.21:45:37.28#ibcon#read 4, iclass 18, count 2 2006.257.21:45:37.28#ibcon#about to read 5, iclass 18, count 2 2006.257.21:45:37.28#ibcon#read 5, iclass 18, count 2 2006.257.21:45:37.28#ibcon#about to read 6, iclass 18, count 2 2006.257.21:45:37.28#ibcon#read 6, iclass 18, count 2 2006.257.21:45:37.28#ibcon#end of sib2, iclass 18, count 2 2006.257.21:45:37.28#ibcon#*mode == 0, iclass 18, count 2 2006.257.21:45:37.28#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.21:45:37.28#ibcon#[25=AT06-04\r\n] 2006.257.21:45:37.28#ibcon#*before write, iclass 18, count 2 2006.257.21:45:37.28#ibcon#enter sib2, iclass 18, count 2 2006.257.21:45:37.28#ibcon#flushed, iclass 18, count 2 2006.257.21:45:37.28#ibcon#about to write, iclass 18, count 2 2006.257.21:45:37.28#ibcon#wrote, iclass 18, count 2 2006.257.21:45:37.28#ibcon#about to read 3, iclass 18, count 2 2006.257.21:45:37.31#ibcon#read 3, iclass 18, count 2 2006.257.21:45:37.31#ibcon#about to read 4, iclass 18, count 2 2006.257.21:45:37.31#ibcon#read 4, iclass 18, count 2 2006.257.21:45:37.31#ibcon#about to read 5, iclass 18, count 2 2006.257.21:45:37.31#ibcon#read 5, iclass 18, count 2 2006.257.21:45:37.31#ibcon#about to read 6, iclass 18, count 2 2006.257.21:45:37.31#ibcon#read 6, iclass 18, count 2 2006.257.21:45:37.31#ibcon#end of sib2, iclass 18, count 2 2006.257.21:45:37.31#ibcon#*after write, iclass 18, count 2 2006.257.21:45:37.31#ibcon#*before return 0, iclass 18, count 2 2006.257.21:45:37.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:37.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:37.31#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.21:45:37.31#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:37.31#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:37.43#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:37.43#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:37.43#ibcon#enter wrdev, iclass 18, count 0 2006.257.21:45:37.43#ibcon#first serial, iclass 18, count 0 2006.257.21:45:37.43#ibcon#enter sib2, iclass 18, count 0 2006.257.21:45:37.43#ibcon#flushed, iclass 18, count 0 2006.257.21:45:37.43#ibcon#about to write, iclass 18, count 0 2006.257.21:45:37.43#ibcon#wrote, iclass 18, count 0 2006.257.21:45:37.43#ibcon#about to read 3, iclass 18, count 0 2006.257.21:45:37.45#ibcon#read 3, iclass 18, count 0 2006.257.21:45:37.45#ibcon#about to read 4, iclass 18, count 0 2006.257.21:45:37.45#ibcon#read 4, iclass 18, count 0 2006.257.21:45:37.45#ibcon#about to read 5, iclass 18, count 0 2006.257.21:45:37.45#ibcon#read 5, iclass 18, count 0 2006.257.21:45:37.45#ibcon#about to read 6, iclass 18, count 0 2006.257.21:45:37.45#ibcon#read 6, iclass 18, count 0 2006.257.21:45:37.45#ibcon#end of sib2, iclass 18, count 0 2006.257.21:45:37.45#ibcon#*mode == 0, iclass 18, count 0 2006.257.21:45:37.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.21:45:37.45#ibcon#[25=USB\r\n] 2006.257.21:45:37.45#ibcon#*before write, iclass 18, count 0 2006.257.21:45:37.45#ibcon#enter sib2, iclass 18, count 0 2006.257.21:45:37.45#ibcon#flushed, iclass 18, count 0 2006.257.21:45:37.45#ibcon#about to write, iclass 18, count 0 2006.257.21:45:37.45#ibcon#wrote, iclass 18, count 0 2006.257.21:45:37.45#ibcon#about to read 3, iclass 18, count 0 2006.257.21:45:37.48#ibcon#read 3, iclass 18, count 0 2006.257.21:45:37.48#ibcon#about to read 4, iclass 18, count 0 2006.257.21:45:37.48#ibcon#read 4, iclass 18, count 0 2006.257.21:45:37.48#ibcon#about to read 5, iclass 18, count 0 2006.257.21:45:37.48#ibcon#read 5, iclass 18, count 0 2006.257.21:45:37.48#ibcon#about to read 6, iclass 18, count 0 2006.257.21:45:37.48#ibcon#read 6, iclass 18, count 0 2006.257.21:45:37.48#ibcon#end of sib2, iclass 18, count 0 2006.257.21:45:37.48#ibcon#*after write, iclass 18, count 0 2006.257.21:45:37.48#ibcon#*before return 0, iclass 18, count 0 2006.257.21:45:37.48#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:37.48#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:37.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.21:45:37.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.21:45:37.48$vck44/valo=7,864.99 2006.257.21:45:37.48#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.21:45:37.48#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.21:45:37.48#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:37.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:37.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:37.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:37.48#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:45:37.48#ibcon#first serial, iclass 20, count 0 2006.257.21:45:37.48#ibcon#enter sib2, iclass 20, count 0 2006.257.21:45:37.48#ibcon#flushed, iclass 20, count 0 2006.257.21:45:37.48#ibcon#about to write, iclass 20, count 0 2006.257.21:45:37.48#ibcon#wrote, iclass 20, count 0 2006.257.21:45:37.48#ibcon#about to read 3, iclass 20, count 0 2006.257.21:45:37.50#ibcon#read 3, iclass 20, count 0 2006.257.21:45:37.50#ibcon#about to read 4, iclass 20, count 0 2006.257.21:45:37.50#ibcon#read 4, iclass 20, count 0 2006.257.21:45:37.50#ibcon#about to read 5, iclass 20, count 0 2006.257.21:45:37.50#ibcon#read 5, iclass 20, count 0 2006.257.21:45:37.50#ibcon#about to read 6, iclass 20, count 0 2006.257.21:45:37.50#ibcon#read 6, iclass 20, count 0 2006.257.21:45:37.50#ibcon#end of sib2, iclass 20, count 0 2006.257.21:45:37.50#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:45:37.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:45:37.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.21:45:37.50#ibcon#*before write, iclass 20, count 0 2006.257.21:45:37.50#ibcon#enter sib2, iclass 20, count 0 2006.257.21:45:37.50#ibcon#flushed, iclass 20, count 0 2006.257.21:45:37.50#ibcon#about to write, iclass 20, count 0 2006.257.21:45:37.50#ibcon#wrote, iclass 20, count 0 2006.257.21:45:37.50#ibcon#about to read 3, iclass 20, count 0 2006.257.21:45:37.54#ibcon#read 3, iclass 20, count 0 2006.257.21:45:37.54#ibcon#about to read 4, iclass 20, count 0 2006.257.21:45:37.54#ibcon#read 4, iclass 20, count 0 2006.257.21:45:37.54#ibcon#about to read 5, iclass 20, count 0 2006.257.21:45:37.54#ibcon#read 5, iclass 20, count 0 2006.257.21:45:37.54#ibcon#about to read 6, iclass 20, count 0 2006.257.21:45:37.54#ibcon#read 6, iclass 20, count 0 2006.257.21:45:37.54#ibcon#end of sib2, iclass 20, count 0 2006.257.21:45:37.54#ibcon#*after write, iclass 20, count 0 2006.257.21:45:37.54#ibcon#*before return 0, iclass 20, count 0 2006.257.21:45:37.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:37.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:37.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:45:37.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:45:37.54$vck44/va=7,4 2006.257.21:45:37.54#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.21:45:37.54#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.21:45:37.54#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:37.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:37.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:37.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:37.60#ibcon#enter wrdev, iclass 22, count 2 2006.257.21:45:37.60#ibcon#first serial, iclass 22, count 2 2006.257.21:45:37.60#ibcon#enter sib2, iclass 22, count 2 2006.257.21:45:37.60#ibcon#flushed, iclass 22, count 2 2006.257.21:45:37.60#ibcon#about to write, iclass 22, count 2 2006.257.21:45:37.60#ibcon#wrote, iclass 22, count 2 2006.257.21:45:37.60#ibcon#about to read 3, iclass 22, count 2 2006.257.21:45:37.62#ibcon#read 3, iclass 22, count 2 2006.257.21:45:37.62#ibcon#about to read 4, iclass 22, count 2 2006.257.21:45:37.62#ibcon#read 4, iclass 22, count 2 2006.257.21:45:37.62#ibcon#about to read 5, iclass 22, count 2 2006.257.21:45:37.62#ibcon#read 5, iclass 22, count 2 2006.257.21:45:37.62#ibcon#about to read 6, iclass 22, count 2 2006.257.21:45:37.62#ibcon#read 6, iclass 22, count 2 2006.257.21:45:37.62#ibcon#end of sib2, iclass 22, count 2 2006.257.21:45:37.62#ibcon#*mode == 0, iclass 22, count 2 2006.257.21:45:37.62#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.21:45:37.62#ibcon#[25=AT07-04\r\n] 2006.257.21:45:37.62#ibcon#*before write, iclass 22, count 2 2006.257.21:45:37.62#ibcon#enter sib2, iclass 22, count 2 2006.257.21:45:37.62#ibcon#flushed, iclass 22, count 2 2006.257.21:45:37.62#ibcon#about to write, iclass 22, count 2 2006.257.21:45:37.62#ibcon#wrote, iclass 22, count 2 2006.257.21:45:37.62#ibcon#about to read 3, iclass 22, count 2 2006.257.21:45:37.65#ibcon#read 3, iclass 22, count 2 2006.257.21:45:37.65#ibcon#about to read 4, iclass 22, count 2 2006.257.21:45:37.65#ibcon#read 4, iclass 22, count 2 2006.257.21:45:37.65#ibcon#about to read 5, iclass 22, count 2 2006.257.21:45:37.65#ibcon#read 5, iclass 22, count 2 2006.257.21:45:37.65#ibcon#about to read 6, iclass 22, count 2 2006.257.21:45:37.65#ibcon#read 6, iclass 22, count 2 2006.257.21:45:37.65#ibcon#end of sib2, iclass 22, count 2 2006.257.21:45:37.65#ibcon#*after write, iclass 22, count 2 2006.257.21:45:37.65#ibcon#*before return 0, iclass 22, count 2 2006.257.21:45:37.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:37.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:37.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.21:45:37.65#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:37.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:37.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:37.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:37.77#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:45:37.77#ibcon#first serial, iclass 22, count 0 2006.257.21:45:37.77#ibcon#enter sib2, iclass 22, count 0 2006.257.21:45:37.77#ibcon#flushed, iclass 22, count 0 2006.257.21:45:37.77#ibcon#about to write, iclass 22, count 0 2006.257.21:45:37.77#ibcon#wrote, iclass 22, count 0 2006.257.21:45:37.77#ibcon#about to read 3, iclass 22, count 0 2006.257.21:45:37.79#ibcon#read 3, iclass 22, count 0 2006.257.21:45:37.79#ibcon#about to read 4, iclass 22, count 0 2006.257.21:45:37.79#ibcon#read 4, iclass 22, count 0 2006.257.21:45:37.79#ibcon#about to read 5, iclass 22, count 0 2006.257.21:45:37.79#ibcon#read 5, iclass 22, count 0 2006.257.21:45:37.79#ibcon#about to read 6, iclass 22, count 0 2006.257.21:45:37.79#ibcon#read 6, iclass 22, count 0 2006.257.21:45:37.79#ibcon#end of sib2, iclass 22, count 0 2006.257.21:45:37.79#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:45:37.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:45:37.79#ibcon#[25=USB\r\n] 2006.257.21:45:37.79#ibcon#*before write, iclass 22, count 0 2006.257.21:45:37.79#ibcon#enter sib2, iclass 22, count 0 2006.257.21:45:37.79#ibcon#flushed, iclass 22, count 0 2006.257.21:45:37.79#ibcon#about to write, iclass 22, count 0 2006.257.21:45:37.79#ibcon#wrote, iclass 22, count 0 2006.257.21:45:37.79#ibcon#about to read 3, iclass 22, count 0 2006.257.21:45:37.82#ibcon#read 3, iclass 22, count 0 2006.257.21:45:37.82#ibcon#about to read 4, iclass 22, count 0 2006.257.21:45:37.82#ibcon#read 4, iclass 22, count 0 2006.257.21:45:37.82#ibcon#about to read 5, iclass 22, count 0 2006.257.21:45:37.82#ibcon#read 5, iclass 22, count 0 2006.257.21:45:37.82#ibcon#about to read 6, iclass 22, count 0 2006.257.21:45:37.82#ibcon#read 6, iclass 22, count 0 2006.257.21:45:37.82#ibcon#end of sib2, iclass 22, count 0 2006.257.21:45:37.82#ibcon#*after write, iclass 22, count 0 2006.257.21:45:37.82#ibcon#*before return 0, iclass 22, count 0 2006.257.21:45:37.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:37.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:37.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:45:37.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:45:37.82$vck44/valo=8,884.99 2006.257.21:45:37.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.21:45:37.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.21:45:37.82#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:37.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:37.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:37.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:37.82#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:45:37.82#ibcon#first serial, iclass 24, count 0 2006.257.21:45:37.82#ibcon#enter sib2, iclass 24, count 0 2006.257.21:45:37.82#ibcon#flushed, iclass 24, count 0 2006.257.21:45:37.82#ibcon#about to write, iclass 24, count 0 2006.257.21:45:37.82#ibcon#wrote, iclass 24, count 0 2006.257.21:45:37.82#ibcon#about to read 3, iclass 24, count 0 2006.257.21:45:37.84#ibcon#read 3, iclass 24, count 0 2006.257.21:45:37.84#ibcon#about to read 4, iclass 24, count 0 2006.257.21:45:37.84#ibcon#read 4, iclass 24, count 0 2006.257.21:45:37.84#ibcon#about to read 5, iclass 24, count 0 2006.257.21:45:37.84#ibcon#read 5, iclass 24, count 0 2006.257.21:45:37.84#ibcon#about to read 6, iclass 24, count 0 2006.257.21:45:37.84#ibcon#read 6, iclass 24, count 0 2006.257.21:45:37.84#ibcon#end of sib2, iclass 24, count 0 2006.257.21:45:37.84#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:45:37.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:45:37.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.21:45:37.84#ibcon#*before write, iclass 24, count 0 2006.257.21:45:37.84#ibcon#enter sib2, iclass 24, count 0 2006.257.21:45:37.84#ibcon#flushed, iclass 24, count 0 2006.257.21:45:37.84#ibcon#about to write, iclass 24, count 0 2006.257.21:45:37.84#ibcon#wrote, iclass 24, count 0 2006.257.21:45:37.84#ibcon#about to read 3, iclass 24, count 0 2006.257.21:45:37.88#ibcon#read 3, iclass 24, count 0 2006.257.21:45:37.88#ibcon#about to read 4, iclass 24, count 0 2006.257.21:45:37.88#ibcon#read 4, iclass 24, count 0 2006.257.21:45:37.88#ibcon#about to read 5, iclass 24, count 0 2006.257.21:45:37.88#ibcon#read 5, iclass 24, count 0 2006.257.21:45:37.88#ibcon#about to read 6, iclass 24, count 0 2006.257.21:45:37.88#ibcon#read 6, iclass 24, count 0 2006.257.21:45:37.88#ibcon#end of sib2, iclass 24, count 0 2006.257.21:45:37.88#ibcon#*after write, iclass 24, count 0 2006.257.21:45:37.88#ibcon#*before return 0, iclass 24, count 0 2006.257.21:45:37.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:37.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:37.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:45:37.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:45:37.88$vck44/va=8,4 2006.257.21:45:37.88#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.21:45:37.88#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.21:45:37.88#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:37.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:45:37.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:45:37.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:45:37.94#ibcon#enter wrdev, iclass 26, count 2 2006.257.21:45:37.94#ibcon#first serial, iclass 26, count 2 2006.257.21:45:37.94#ibcon#enter sib2, iclass 26, count 2 2006.257.21:45:37.94#ibcon#flushed, iclass 26, count 2 2006.257.21:45:37.94#ibcon#about to write, iclass 26, count 2 2006.257.21:45:37.94#ibcon#wrote, iclass 26, count 2 2006.257.21:45:37.94#ibcon#about to read 3, iclass 26, count 2 2006.257.21:45:37.96#ibcon#read 3, iclass 26, count 2 2006.257.21:45:37.96#ibcon#about to read 4, iclass 26, count 2 2006.257.21:45:37.96#ibcon#read 4, iclass 26, count 2 2006.257.21:45:37.96#ibcon#about to read 5, iclass 26, count 2 2006.257.21:45:37.96#ibcon#read 5, iclass 26, count 2 2006.257.21:45:37.96#ibcon#about to read 6, iclass 26, count 2 2006.257.21:45:37.96#ibcon#read 6, iclass 26, count 2 2006.257.21:45:37.96#ibcon#end of sib2, iclass 26, count 2 2006.257.21:45:37.96#ibcon#*mode == 0, iclass 26, count 2 2006.257.21:45:37.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.21:45:37.96#ibcon#[25=AT08-04\r\n] 2006.257.21:45:37.96#ibcon#*before write, iclass 26, count 2 2006.257.21:45:37.96#ibcon#enter sib2, iclass 26, count 2 2006.257.21:45:37.96#ibcon#flushed, iclass 26, count 2 2006.257.21:45:37.96#ibcon#about to write, iclass 26, count 2 2006.257.21:45:37.96#ibcon#wrote, iclass 26, count 2 2006.257.21:45:37.96#ibcon#about to read 3, iclass 26, count 2 2006.257.21:45:37.99#ibcon#read 3, iclass 26, count 2 2006.257.21:45:37.99#ibcon#about to read 4, iclass 26, count 2 2006.257.21:45:37.99#ibcon#read 4, iclass 26, count 2 2006.257.21:45:37.99#ibcon#about to read 5, iclass 26, count 2 2006.257.21:45:37.99#ibcon#read 5, iclass 26, count 2 2006.257.21:45:37.99#ibcon#about to read 6, iclass 26, count 2 2006.257.21:45:37.99#ibcon#read 6, iclass 26, count 2 2006.257.21:45:37.99#ibcon#end of sib2, iclass 26, count 2 2006.257.21:45:37.99#ibcon#*after write, iclass 26, count 2 2006.257.21:45:37.99#ibcon#*before return 0, iclass 26, count 2 2006.257.21:45:37.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:45:37.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.21:45:37.99#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.21:45:37.99#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:37.99#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:45:38.11#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:45:38.11#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:45:38.11#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:45:38.11#ibcon#first serial, iclass 26, count 0 2006.257.21:45:38.11#ibcon#enter sib2, iclass 26, count 0 2006.257.21:45:38.11#ibcon#flushed, iclass 26, count 0 2006.257.21:45:38.11#ibcon#about to write, iclass 26, count 0 2006.257.21:45:38.11#ibcon#wrote, iclass 26, count 0 2006.257.21:45:38.11#ibcon#about to read 3, iclass 26, count 0 2006.257.21:45:38.13#ibcon#read 3, iclass 26, count 0 2006.257.21:45:38.13#ibcon#about to read 4, iclass 26, count 0 2006.257.21:45:38.13#ibcon#read 4, iclass 26, count 0 2006.257.21:45:38.13#ibcon#about to read 5, iclass 26, count 0 2006.257.21:45:38.13#ibcon#read 5, iclass 26, count 0 2006.257.21:45:38.13#ibcon#about to read 6, iclass 26, count 0 2006.257.21:45:38.13#ibcon#read 6, iclass 26, count 0 2006.257.21:45:38.13#ibcon#end of sib2, iclass 26, count 0 2006.257.21:45:38.13#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:45:38.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:45:38.13#ibcon#[25=USB\r\n] 2006.257.21:45:38.13#ibcon#*before write, iclass 26, count 0 2006.257.21:45:38.13#ibcon#enter sib2, iclass 26, count 0 2006.257.21:45:38.13#ibcon#flushed, iclass 26, count 0 2006.257.21:45:38.13#ibcon#about to write, iclass 26, count 0 2006.257.21:45:38.13#ibcon#wrote, iclass 26, count 0 2006.257.21:45:38.13#ibcon#about to read 3, iclass 26, count 0 2006.257.21:45:38.16#ibcon#read 3, iclass 26, count 0 2006.257.21:45:38.16#ibcon#about to read 4, iclass 26, count 0 2006.257.21:45:38.16#ibcon#read 4, iclass 26, count 0 2006.257.21:45:38.16#ibcon#about to read 5, iclass 26, count 0 2006.257.21:45:38.16#ibcon#read 5, iclass 26, count 0 2006.257.21:45:38.16#ibcon#about to read 6, iclass 26, count 0 2006.257.21:45:38.16#ibcon#read 6, iclass 26, count 0 2006.257.21:45:38.16#ibcon#end of sib2, iclass 26, count 0 2006.257.21:45:38.16#ibcon#*after write, iclass 26, count 0 2006.257.21:45:38.16#ibcon#*before return 0, iclass 26, count 0 2006.257.21:45:38.16#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:45:38.16#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.21:45:38.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:45:38.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:45:38.16$vck44/vblo=1,629.99 2006.257.21:45:38.16#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.21:45:38.16#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.21:45:38.16#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:38.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:45:38.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:45:38.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:45:38.16#ibcon#enter wrdev, iclass 28, count 0 2006.257.21:45:38.16#ibcon#first serial, iclass 28, count 0 2006.257.21:45:38.16#ibcon#enter sib2, iclass 28, count 0 2006.257.21:45:38.16#ibcon#flushed, iclass 28, count 0 2006.257.21:45:38.16#ibcon#about to write, iclass 28, count 0 2006.257.21:45:38.16#ibcon#wrote, iclass 28, count 0 2006.257.21:45:38.16#ibcon#about to read 3, iclass 28, count 0 2006.257.21:45:38.18#ibcon#read 3, iclass 28, count 0 2006.257.21:45:38.18#ibcon#about to read 4, iclass 28, count 0 2006.257.21:45:38.18#ibcon#read 4, iclass 28, count 0 2006.257.21:45:38.18#ibcon#about to read 5, iclass 28, count 0 2006.257.21:45:38.18#ibcon#read 5, iclass 28, count 0 2006.257.21:45:38.18#ibcon#about to read 6, iclass 28, count 0 2006.257.21:45:38.18#ibcon#read 6, iclass 28, count 0 2006.257.21:45:38.18#ibcon#end of sib2, iclass 28, count 0 2006.257.21:45:38.18#ibcon#*mode == 0, iclass 28, count 0 2006.257.21:45:38.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.21:45:38.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.21:45:38.18#ibcon#*before write, iclass 28, count 0 2006.257.21:45:38.18#ibcon#enter sib2, iclass 28, count 0 2006.257.21:45:38.18#ibcon#flushed, iclass 28, count 0 2006.257.21:45:38.18#ibcon#about to write, iclass 28, count 0 2006.257.21:45:38.18#ibcon#wrote, iclass 28, count 0 2006.257.21:45:38.18#ibcon#about to read 3, iclass 28, count 0 2006.257.21:45:38.22#ibcon#read 3, iclass 28, count 0 2006.257.21:45:38.22#ibcon#about to read 4, iclass 28, count 0 2006.257.21:45:38.22#ibcon#read 4, iclass 28, count 0 2006.257.21:45:38.22#ibcon#about to read 5, iclass 28, count 0 2006.257.21:45:38.22#ibcon#read 5, iclass 28, count 0 2006.257.21:45:38.22#ibcon#about to read 6, iclass 28, count 0 2006.257.21:45:38.22#ibcon#read 6, iclass 28, count 0 2006.257.21:45:38.22#ibcon#end of sib2, iclass 28, count 0 2006.257.21:45:38.22#ibcon#*after write, iclass 28, count 0 2006.257.21:45:38.22#ibcon#*before return 0, iclass 28, count 0 2006.257.21:45:38.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:45:38.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.21:45:38.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.21:45:38.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.21:45:38.22$vck44/vb=1,4 2006.257.21:45:38.22#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.21:45:38.22#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.21:45:38.22#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:38.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:45:38.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:45:38.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:45:38.22#ibcon#enter wrdev, iclass 30, count 2 2006.257.21:45:38.22#ibcon#first serial, iclass 30, count 2 2006.257.21:45:38.22#ibcon#enter sib2, iclass 30, count 2 2006.257.21:45:38.22#ibcon#flushed, iclass 30, count 2 2006.257.21:45:38.22#ibcon#about to write, iclass 30, count 2 2006.257.21:45:38.22#ibcon#wrote, iclass 30, count 2 2006.257.21:45:38.22#ibcon#about to read 3, iclass 30, count 2 2006.257.21:45:38.24#ibcon#read 3, iclass 30, count 2 2006.257.21:45:38.24#ibcon#about to read 4, iclass 30, count 2 2006.257.21:45:38.24#ibcon#read 4, iclass 30, count 2 2006.257.21:45:38.24#ibcon#about to read 5, iclass 30, count 2 2006.257.21:45:38.24#ibcon#read 5, iclass 30, count 2 2006.257.21:45:38.24#ibcon#about to read 6, iclass 30, count 2 2006.257.21:45:38.24#ibcon#read 6, iclass 30, count 2 2006.257.21:45:38.24#ibcon#end of sib2, iclass 30, count 2 2006.257.21:45:38.24#ibcon#*mode == 0, iclass 30, count 2 2006.257.21:45:38.24#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.21:45:38.24#ibcon#[27=AT01-04\r\n] 2006.257.21:45:38.24#ibcon#*before write, iclass 30, count 2 2006.257.21:45:38.24#ibcon#enter sib2, iclass 30, count 2 2006.257.21:45:38.24#ibcon#flushed, iclass 30, count 2 2006.257.21:45:38.24#ibcon#about to write, iclass 30, count 2 2006.257.21:45:38.24#ibcon#wrote, iclass 30, count 2 2006.257.21:45:38.24#ibcon#about to read 3, iclass 30, count 2 2006.257.21:45:38.27#ibcon#read 3, iclass 30, count 2 2006.257.21:45:38.27#ibcon#about to read 4, iclass 30, count 2 2006.257.21:45:38.27#ibcon#read 4, iclass 30, count 2 2006.257.21:45:38.27#ibcon#about to read 5, iclass 30, count 2 2006.257.21:45:38.27#ibcon#read 5, iclass 30, count 2 2006.257.21:45:38.27#ibcon#about to read 6, iclass 30, count 2 2006.257.21:45:38.27#ibcon#read 6, iclass 30, count 2 2006.257.21:45:38.27#ibcon#end of sib2, iclass 30, count 2 2006.257.21:45:38.27#ibcon#*after write, iclass 30, count 2 2006.257.21:45:38.27#ibcon#*before return 0, iclass 30, count 2 2006.257.21:45:38.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:45:38.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.21:45:38.27#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.21:45:38.27#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:38.27#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:45:38.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:45:38.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:45:38.39#ibcon#enter wrdev, iclass 30, count 0 2006.257.21:45:38.39#ibcon#first serial, iclass 30, count 0 2006.257.21:45:38.39#ibcon#enter sib2, iclass 30, count 0 2006.257.21:45:38.39#ibcon#flushed, iclass 30, count 0 2006.257.21:45:38.39#ibcon#about to write, iclass 30, count 0 2006.257.21:45:38.39#ibcon#wrote, iclass 30, count 0 2006.257.21:45:38.39#ibcon#about to read 3, iclass 30, count 0 2006.257.21:45:38.41#ibcon#read 3, iclass 30, count 0 2006.257.21:45:38.41#ibcon#about to read 4, iclass 30, count 0 2006.257.21:45:38.41#ibcon#read 4, iclass 30, count 0 2006.257.21:45:38.41#ibcon#about to read 5, iclass 30, count 0 2006.257.21:45:38.41#ibcon#read 5, iclass 30, count 0 2006.257.21:45:38.41#ibcon#about to read 6, iclass 30, count 0 2006.257.21:45:38.41#ibcon#read 6, iclass 30, count 0 2006.257.21:45:38.41#ibcon#end of sib2, iclass 30, count 0 2006.257.21:45:38.41#ibcon#*mode == 0, iclass 30, count 0 2006.257.21:45:38.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.21:45:38.41#ibcon#[27=USB\r\n] 2006.257.21:45:38.41#ibcon#*before write, iclass 30, count 0 2006.257.21:45:38.41#ibcon#enter sib2, iclass 30, count 0 2006.257.21:45:38.41#ibcon#flushed, iclass 30, count 0 2006.257.21:45:38.41#ibcon#about to write, iclass 30, count 0 2006.257.21:45:38.41#ibcon#wrote, iclass 30, count 0 2006.257.21:45:38.41#ibcon#about to read 3, iclass 30, count 0 2006.257.21:45:38.44#ibcon#read 3, iclass 30, count 0 2006.257.21:45:38.44#ibcon#about to read 4, iclass 30, count 0 2006.257.21:45:38.44#ibcon#read 4, iclass 30, count 0 2006.257.21:45:38.44#ibcon#about to read 5, iclass 30, count 0 2006.257.21:45:38.44#ibcon#read 5, iclass 30, count 0 2006.257.21:45:38.44#ibcon#about to read 6, iclass 30, count 0 2006.257.21:45:38.44#ibcon#read 6, iclass 30, count 0 2006.257.21:45:38.44#ibcon#end of sib2, iclass 30, count 0 2006.257.21:45:38.44#ibcon#*after write, iclass 30, count 0 2006.257.21:45:38.44#ibcon#*before return 0, iclass 30, count 0 2006.257.21:45:38.44#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:45:38.44#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.21:45:38.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.21:45:38.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.21:45:38.44$vck44/vblo=2,634.99 2006.257.21:45:38.44#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.21:45:38.44#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.21:45:38.44#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:38.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:38.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:38.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:38.44#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:45:38.44#ibcon#first serial, iclass 32, count 0 2006.257.21:45:38.44#ibcon#enter sib2, iclass 32, count 0 2006.257.21:45:38.44#ibcon#flushed, iclass 32, count 0 2006.257.21:45:38.44#ibcon#about to write, iclass 32, count 0 2006.257.21:45:38.44#ibcon#wrote, iclass 32, count 0 2006.257.21:45:38.44#ibcon#about to read 3, iclass 32, count 0 2006.257.21:45:38.46#ibcon#read 3, iclass 32, count 0 2006.257.21:45:38.46#ibcon#about to read 4, iclass 32, count 0 2006.257.21:45:38.46#ibcon#read 4, iclass 32, count 0 2006.257.21:45:38.46#ibcon#about to read 5, iclass 32, count 0 2006.257.21:45:38.46#ibcon#read 5, iclass 32, count 0 2006.257.21:45:38.46#ibcon#about to read 6, iclass 32, count 0 2006.257.21:45:38.46#ibcon#read 6, iclass 32, count 0 2006.257.21:45:38.46#ibcon#end of sib2, iclass 32, count 0 2006.257.21:45:38.46#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:45:38.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:45:38.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.21:45:38.46#ibcon#*before write, iclass 32, count 0 2006.257.21:45:38.46#ibcon#enter sib2, iclass 32, count 0 2006.257.21:45:38.46#ibcon#flushed, iclass 32, count 0 2006.257.21:45:38.46#ibcon#about to write, iclass 32, count 0 2006.257.21:45:38.46#ibcon#wrote, iclass 32, count 0 2006.257.21:45:38.46#ibcon#about to read 3, iclass 32, count 0 2006.257.21:45:38.50#ibcon#read 3, iclass 32, count 0 2006.257.21:45:38.50#ibcon#about to read 4, iclass 32, count 0 2006.257.21:45:38.50#ibcon#read 4, iclass 32, count 0 2006.257.21:45:38.50#ibcon#about to read 5, iclass 32, count 0 2006.257.21:45:38.50#ibcon#read 5, iclass 32, count 0 2006.257.21:45:38.50#ibcon#about to read 6, iclass 32, count 0 2006.257.21:45:38.50#ibcon#read 6, iclass 32, count 0 2006.257.21:45:38.50#ibcon#end of sib2, iclass 32, count 0 2006.257.21:45:38.50#ibcon#*after write, iclass 32, count 0 2006.257.21:45:38.50#ibcon#*before return 0, iclass 32, count 0 2006.257.21:45:38.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:38.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.21:45:38.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:45:38.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:45:38.50$vck44/vb=2,5 2006.257.21:45:38.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.21:45:38.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.21:45:38.50#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:38.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:38.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:38.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:38.56#ibcon#enter wrdev, iclass 34, count 2 2006.257.21:45:38.56#ibcon#first serial, iclass 34, count 2 2006.257.21:45:38.56#ibcon#enter sib2, iclass 34, count 2 2006.257.21:45:38.56#ibcon#flushed, iclass 34, count 2 2006.257.21:45:38.56#ibcon#about to write, iclass 34, count 2 2006.257.21:45:38.56#ibcon#wrote, iclass 34, count 2 2006.257.21:45:38.56#ibcon#about to read 3, iclass 34, count 2 2006.257.21:45:38.58#ibcon#read 3, iclass 34, count 2 2006.257.21:45:38.58#ibcon#about to read 4, iclass 34, count 2 2006.257.21:45:38.58#ibcon#read 4, iclass 34, count 2 2006.257.21:45:38.58#ibcon#about to read 5, iclass 34, count 2 2006.257.21:45:38.58#ibcon#read 5, iclass 34, count 2 2006.257.21:45:38.58#ibcon#about to read 6, iclass 34, count 2 2006.257.21:45:38.58#ibcon#read 6, iclass 34, count 2 2006.257.21:45:38.58#ibcon#end of sib2, iclass 34, count 2 2006.257.21:45:38.58#ibcon#*mode == 0, iclass 34, count 2 2006.257.21:45:38.58#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.21:45:38.58#ibcon#[27=AT02-05\r\n] 2006.257.21:45:38.58#ibcon#*before write, iclass 34, count 2 2006.257.21:45:38.58#ibcon#enter sib2, iclass 34, count 2 2006.257.21:45:38.58#ibcon#flushed, iclass 34, count 2 2006.257.21:45:38.58#ibcon#about to write, iclass 34, count 2 2006.257.21:45:38.58#ibcon#wrote, iclass 34, count 2 2006.257.21:45:38.58#ibcon#about to read 3, iclass 34, count 2 2006.257.21:45:38.61#ibcon#read 3, iclass 34, count 2 2006.257.21:45:38.61#ibcon#about to read 4, iclass 34, count 2 2006.257.21:45:38.61#ibcon#read 4, iclass 34, count 2 2006.257.21:45:38.61#ibcon#about to read 5, iclass 34, count 2 2006.257.21:45:38.61#ibcon#read 5, iclass 34, count 2 2006.257.21:45:38.61#ibcon#about to read 6, iclass 34, count 2 2006.257.21:45:38.61#ibcon#read 6, iclass 34, count 2 2006.257.21:45:38.61#ibcon#end of sib2, iclass 34, count 2 2006.257.21:45:38.61#ibcon#*after write, iclass 34, count 2 2006.257.21:45:38.61#ibcon#*before return 0, iclass 34, count 2 2006.257.21:45:38.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:38.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.21:45:38.61#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.21:45:38.61#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:38.61#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:38.73#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:38.73#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:38.73#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:45:38.73#ibcon#first serial, iclass 34, count 0 2006.257.21:45:38.73#ibcon#enter sib2, iclass 34, count 0 2006.257.21:45:38.73#ibcon#flushed, iclass 34, count 0 2006.257.21:45:38.73#ibcon#about to write, iclass 34, count 0 2006.257.21:45:38.73#ibcon#wrote, iclass 34, count 0 2006.257.21:45:38.73#ibcon#about to read 3, iclass 34, count 0 2006.257.21:45:38.75#ibcon#read 3, iclass 34, count 0 2006.257.21:45:38.75#ibcon#about to read 4, iclass 34, count 0 2006.257.21:45:38.75#ibcon#read 4, iclass 34, count 0 2006.257.21:45:38.75#ibcon#about to read 5, iclass 34, count 0 2006.257.21:45:38.75#ibcon#read 5, iclass 34, count 0 2006.257.21:45:38.75#ibcon#about to read 6, iclass 34, count 0 2006.257.21:45:38.75#ibcon#read 6, iclass 34, count 0 2006.257.21:45:38.75#ibcon#end of sib2, iclass 34, count 0 2006.257.21:45:38.75#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:45:38.75#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:45:38.75#ibcon#[27=USB\r\n] 2006.257.21:45:38.75#ibcon#*before write, iclass 34, count 0 2006.257.21:45:38.75#ibcon#enter sib2, iclass 34, count 0 2006.257.21:45:38.75#ibcon#flushed, iclass 34, count 0 2006.257.21:45:38.75#ibcon#about to write, iclass 34, count 0 2006.257.21:45:38.75#ibcon#wrote, iclass 34, count 0 2006.257.21:45:38.75#ibcon#about to read 3, iclass 34, count 0 2006.257.21:45:38.78#ibcon#read 3, iclass 34, count 0 2006.257.21:45:38.78#ibcon#about to read 4, iclass 34, count 0 2006.257.21:45:38.78#ibcon#read 4, iclass 34, count 0 2006.257.21:45:38.78#ibcon#about to read 5, iclass 34, count 0 2006.257.21:45:38.78#ibcon#read 5, iclass 34, count 0 2006.257.21:45:38.78#ibcon#about to read 6, iclass 34, count 0 2006.257.21:45:38.78#ibcon#read 6, iclass 34, count 0 2006.257.21:45:38.78#ibcon#end of sib2, iclass 34, count 0 2006.257.21:45:38.78#ibcon#*after write, iclass 34, count 0 2006.257.21:45:38.78#ibcon#*before return 0, iclass 34, count 0 2006.257.21:45:38.78#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:38.78#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.21:45:38.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:45:38.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:45:38.78$vck44/vblo=3,649.99 2006.257.21:45:38.78#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.21:45:38.78#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.21:45:38.78#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:38.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:38.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:38.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:38.78#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:45:38.78#ibcon#first serial, iclass 36, count 0 2006.257.21:45:38.78#ibcon#enter sib2, iclass 36, count 0 2006.257.21:45:38.78#ibcon#flushed, iclass 36, count 0 2006.257.21:45:38.78#ibcon#about to write, iclass 36, count 0 2006.257.21:45:38.78#ibcon#wrote, iclass 36, count 0 2006.257.21:45:38.78#ibcon#about to read 3, iclass 36, count 0 2006.257.21:45:38.80#ibcon#read 3, iclass 36, count 0 2006.257.21:45:38.80#ibcon#about to read 4, iclass 36, count 0 2006.257.21:45:38.80#ibcon#read 4, iclass 36, count 0 2006.257.21:45:38.80#ibcon#about to read 5, iclass 36, count 0 2006.257.21:45:38.80#ibcon#read 5, iclass 36, count 0 2006.257.21:45:38.80#ibcon#about to read 6, iclass 36, count 0 2006.257.21:45:38.80#ibcon#read 6, iclass 36, count 0 2006.257.21:45:38.80#ibcon#end of sib2, iclass 36, count 0 2006.257.21:45:38.80#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:45:38.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:45:38.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.21:45:38.80#ibcon#*before write, iclass 36, count 0 2006.257.21:45:38.80#ibcon#enter sib2, iclass 36, count 0 2006.257.21:45:38.80#ibcon#flushed, iclass 36, count 0 2006.257.21:45:38.80#ibcon#about to write, iclass 36, count 0 2006.257.21:45:38.80#ibcon#wrote, iclass 36, count 0 2006.257.21:45:38.80#ibcon#about to read 3, iclass 36, count 0 2006.257.21:45:38.84#ibcon#read 3, iclass 36, count 0 2006.257.21:45:38.84#ibcon#about to read 4, iclass 36, count 0 2006.257.21:45:38.84#ibcon#read 4, iclass 36, count 0 2006.257.21:45:38.84#ibcon#about to read 5, iclass 36, count 0 2006.257.21:45:38.84#ibcon#read 5, iclass 36, count 0 2006.257.21:45:38.84#ibcon#about to read 6, iclass 36, count 0 2006.257.21:45:38.84#ibcon#read 6, iclass 36, count 0 2006.257.21:45:38.84#ibcon#end of sib2, iclass 36, count 0 2006.257.21:45:38.84#ibcon#*after write, iclass 36, count 0 2006.257.21:45:38.84#ibcon#*before return 0, iclass 36, count 0 2006.257.21:45:38.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:38.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:45:38.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:45:38.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:45:38.84$vck44/vb=3,4 2006.257.21:45:38.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.21:45:38.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.21:45:38.84#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:38.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:38.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:38.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:38.90#ibcon#enter wrdev, iclass 38, count 2 2006.257.21:45:38.90#ibcon#first serial, iclass 38, count 2 2006.257.21:45:38.90#ibcon#enter sib2, iclass 38, count 2 2006.257.21:45:38.90#ibcon#flushed, iclass 38, count 2 2006.257.21:45:38.90#ibcon#about to write, iclass 38, count 2 2006.257.21:45:38.90#ibcon#wrote, iclass 38, count 2 2006.257.21:45:38.90#ibcon#about to read 3, iclass 38, count 2 2006.257.21:45:38.92#ibcon#read 3, iclass 38, count 2 2006.257.21:45:38.92#ibcon#about to read 4, iclass 38, count 2 2006.257.21:45:38.92#ibcon#read 4, iclass 38, count 2 2006.257.21:45:38.92#ibcon#about to read 5, iclass 38, count 2 2006.257.21:45:38.92#ibcon#read 5, iclass 38, count 2 2006.257.21:45:38.92#ibcon#about to read 6, iclass 38, count 2 2006.257.21:45:38.92#ibcon#read 6, iclass 38, count 2 2006.257.21:45:38.92#ibcon#end of sib2, iclass 38, count 2 2006.257.21:45:38.92#ibcon#*mode == 0, iclass 38, count 2 2006.257.21:45:38.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.21:45:38.92#ibcon#[27=AT03-04\r\n] 2006.257.21:45:38.92#ibcon#*before write, iclass 38, count 2 2006.257.21:45:38.92#ibcon#enter sib2, iclass 38, count 2 2006.257.21:45:38.92#ibcon#flushed, iclass 38, count 2 2006.257.21:45:38.92#ibcon#about to write, iclass 38, count 2 2006.257.21:45:38.92#ibcon#wrote, iclass 38, count 2 2006.257.21:45:38.92#ibcon#about to read 3, iclass 38, count 2 2006.257.21:45:38.95#ibcon#read 3, iclass 38, count 2 2006.257.21:45:38.95#ibcon#about to read 4, iclass 38, count 2 2006.257.21:45:38.95#ibcon#read 4, iclass 38, count 2 2006.257.21:45:38.95#ibcon#about to read 5, iclass 38, count 2 2006.257.21:45:38.95#ibcon#read 5, iclass 38, count 2 2006.257.21:45:38.95#ibcon#about to read 6, iclass 38, count 2 2006.257.21:45:38.95#ibcon#read 6, iclass 38, count 2 2006.257.21:45:38.95#ibcon#end of sib2, iclass 38, count 2 2006.257.21:45:38.95#ibcon#*after write, iclass 38, count 2 2006.257.21:45:38.95#ibcon#*before return 0, iclass 38, count 2 2006.257.21:45:38.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:38.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.21:45:38.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.21:45:38.95#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:38.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:39.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:39.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:39.07#ibcon#enter wrdev, iclass 38, count 0 2006.257.21:45:39.07#ibcon#first serial, iclass 38, count 0 2006.257.21:45:39.07#ibcon#enter sib2, iclass 38, count 0 2006.257.21:45:39.07#ibcon#flushed, iclass 38, count 0 2006.257.21:45:39.07#ibcon#about to write, iclass 38, count 0 2006.257.21:45:39.07#ibcon#wrote, iclass 38, count 0 2006.257.21:45:39.07#ibcon#about to read 3, iclass 38, count 0 2006.257.21:45:39.09#ibcon#read 3, iclass 38, count 0 2006.257.21:45:39.09#ibcon#about to read 4, iclass 38, count 0 2006.257.21:45:39.09#ibcon#read 4, iclass 38, count 0 2006.257.21:45:39.09#ibcon#about to read 5, iclass 38, count 0 2006.257.21:45:39.09#ibcon#read 5, iclass 38, count 0 2006.257.21:45:39.09#ibcon#about to read 6, iclass 38, count 0 2006.257.21:45:39.09#ibcon#read 6, iclass 38, count 0 2006.257.21:45:39.09#ibcon#end of sib2, iclass 38, count 0 2006.257.21:45:39.09#ibcon#*mode == 0, iclass 38, count 0 2006.257.21:45:39.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.21:45:39.09#ibcon#[27=USB\r\n] 2006.257.21:45:39.09#ibcon#*before write, iclass 38, count 0 2006.257.21:45:39.09#ibcon#enter sib2, iclass 38, count 0 2006.257.21:45:39.09#ibcon#flushed, iclass 38, count 0 2006.257.21:45:39.09#ibcon#about to write, iclass 38, count 0 2006.257.21:45:39.09#ibcon#wrote, iclass 38, count 0 2006.257.21:45:39.09#ibcon#about to read 3, iclass 38, count 0 2006.257.21:45:39.12#ibcon#read 3, iclass 38, count 0 2006.257.21:45:39.12#ibcon#about to read 4, iclass 38, count 0 2006.257.21:45:39.12#ibcon#read 4, iclass 38, count 0 2006.257.21:45:39.12#ibcon#about to read 5, iclass 38, count 0 2006.257.21:45:39.12#ibcon#read 5, iclass 38, count 0 2006.257.21:45:39.12#ibcon#about to read 6, iclass 38, count 0 2006.257.21:45:39.12#ibcon#read 6, iclass 38, count 0 2006.257.21:45:39.12#ibcon#end of sib2, iclass 38, count 0 2006.257.21:45:39.12#ibcon#*after write, iclass 38, count 0 2006.257.21:45:39.12#ibcon#*before return 0, iclass 38, count 0 2006.257.21:45:39.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:39.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.21:45:39.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.21:45:39.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.21:45:39.12$vck44/vblo=4,679.99 2006.257.21:45:39.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.21:45:39.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.21:45:39.12#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:39.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:39.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:39.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:39.12#ibcon#enter wrdev, iclass 40, count 0 2006.257.21:45:39.12#ibcon#first serial, iclass 40, count 0 2006.257.21:45:39.12#ibcon#enter sib2, iclass 40, count 0 2006.257.21:45:39.12#ibcon#flushed, iclass 40, count 0 2006.257.21:45:39.12#ibcon#about to write, iclass 40, count 0 2006.257.21:45:39.12#ibcon#wrote, iclass 40, count 0 2006.257.21:45:39.12#ibcon#about to read 3, iclass 40, count 0 2006.257.21:45:39.14#ibcon#read 3, iclass 40, count 0 2006.257.21:45:39.14#ibcon#about to read 4, iclass 40, count 0 2006.257.21:45:39.14#ibcon#read 4, iclass 40, count 0 2006.257.21:45:39.14#ibcon#about to read 5, iclass 40, count 0 2006.257.21:45:39.14#ibcon#read 5, iclass 40, count 0 2006.257.21:45:39.14#ibcon#about to read 6, iclass 40, count 0 2006.257.21:45:39.14#ibcon#read 6, iclass 40, count 0 2006.257.21:45:39.14#ibcon#end of sib2, iclass 40, count 0 2006.257.21:45:39.14#ibcon#*mode == 0, iclass 40, count 0 2006.257.21:45:39.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.21:45:39.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.21:45:39.14#ibcon#*before write, iclass 40, count 0 2006.257.21:45:39.14#ibcon#enter sib2, iclass 40, count 0 2006.257.21:45:39.14#ibcon#flushed, iclass 40, count 0 2006.257.21:45:39.14#ibcon#about to write, iclass 40, count 0 2006.257.21:45:39.14#ibcon#wrote, iclass 40, count 0 2006.257.21:45:39.14#ibcon#about to read 3, iclass 40, count 0 2006.257.21:45:39.18#ibcon#read 3, iclass 40, count 0 2006.257.21:45:39.18#ibcon#about to read 4, iclass 40, count 0 2006.257.21:45:39.18#ibcon#read 4, iclass 40, count 0 2006.257.21:45:39.18#ibcon#about to read 5, iclass 40, count 0 2006.257.21:45:39.18#ibcon#read 5, iclass 40, count 0 2006.257.21:45:39.18#ibcon#about to read 6, iclass 40, count 0 2006.257.21:45:39.18#ibcon#read 6, iclass 40, count 0 2006.257.21:45:39.18#ibcon#end of sib2, iclass 40, count 0 2006.257.21:45:39.18#ibcon#*after write, iclass 40, count 0 2006.257.21:45:39.18#ibcon#*before return 0, iclass 40, count 0 2006.257.21:45:39.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:39.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.21:45:39.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.21:45:39.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.21:45:39.18$vck44/vb=4,5 2006.257.21:45:39.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.21:45:39.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.21:45:39.18#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:39.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:39.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:39.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:39.24#ibcon#enter wrdev, iclass 4, count 2 2006.257.21:45:39.24#ibcon#first serial, iclass 4, count 2 2006.257.21:45:39.24#ibcon#enter sib2, iclass 4, count 2 2006.257.21:45:39.24#ibcon#flushed, iclass 4, count 2 2006.257.21:45:39.24#ibcon#about to write, iclass 4, count 2 2006.257.21:45:39.24#ibcon#wrote, iclass 4, count 2 2006.257.21:45:39.24#ibcon#about to read 3, iclass 4, count 2 2006.257.21:45:39.26#ibcon#read 3, iclass 4, count 2 2006.257.21:45:39.26#ibcon#about to read 4, iclass 4, count 2 2006.257.21:45:39.26#ibcon#read 4, iclass 4, count 2 2006.257.21:45:39.26#ibcon#about to read 5, iclass 4, count 2 2006.257.21:45:39.26#ibcon#read 5, iclass 4, count 2 2006.257.21:45:39.26#ibcon#about to read 6, iclass 4, count 2 2006.257.21:45:39.26#ibcon#read 6, iclass 4, count 2 2006.257.21:45:39.26#ibcon#end of sib2, iclass 4, count 2 2006.257.21:45:39.26#ibcon#*mode == 0, iclass 4, count 2 2006.257.21:45:39.26#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.21:45:39.26#ibcon#[27=AT04-05\r\n] 2006.257.21:45:39.26#ibcon#*before write, iclass 4, count 2 2006.257.21:45:39.26#ibcon#enter sib2, iclass 4, count 2 2006.257.21:45:39.26#ibcon#flushed, iclass 4, count 2 2006.257.21:45:39.26#ibcon#about to write, iclass 4, count 2 2006.257.21:45:39.26#ibcon#wrote, iclass 4, count 2 2006.257.21:45:39.26#ibcon#about to read 3, iclass 4, count 2 2006.257.21:45:39.29#ibcon#read 3, iclass 4, count 2 2006.257.21:45:39.29#ibcon#about to read 4, iclass 4, count 2 2006.257.21:45:39.29#ibcon#read 4, iclass 4, count 2 2006.257.21:45:39.29#ibcon#about to read 5, iclass 4, count 2 2006.257.21:45:39.29#ibcon#read 5, iclass 4, count 2 2006.257.21:45:39.29#ibcon#about to read 6, iclass 4, count 2 2006.257.21:45:39.29#ibcon#read 6, iclass 4, count 2 2006.257.21:45:39.29#ibcon#end of sib2, iclass 4, count 2 2006.257.21:45:39.29#ibcon#*after write, iclass 4, count 2 2006.257.21:45:39.29#ibcon#*before return 0, iclass 4, count 2 2006.257.21:45:39.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:39.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.21:45:39.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.21:45:39.29#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:39.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:39.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:39.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:39.41#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:45:39.41#ibcon#first serial, iclass 4, count 0 2006.257.21:45:39.41#ibcon#enter sib2, iclass 4, count 0 2006.257.21:45:39.41#ibcon#flushed, iclass 4, count 0 2006.257.21:45:39.41#ibcon#about to write, iclass 4, count 0 2006.257.21:45:39.41#ibcon#wrote, iclass 4, count 0 2006.257.21:45:39.41#ibcon#about to read 3, iclass 4, count 0 2006.257.21:45:39.43#ibcon#read 3, iclass 4, count 0 2006.257.21:45:39.43#ibcon#about to read 4, iclass 4, count 0 2006.257.21:45:39.43#ibcon#read 4, iclass 4, count 0 2006.257.21:45:39.43#ibcon#about to read 5, iclass 4, count 0 2006.257.21:45:39.43#ibcon#read 5, iclass 4, count 0 2006.257.21:45:39.43#ibcon#about to read 6, iclass 4, count 0 2006.257.21:45:39.43#ibcon#read 6, iclass 4, count 0 2006.257.21:45:39.43#ibcon#end of sib2, iclass 4, count 0 2006.257.21:45:39.43#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:45:39.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:45:39.43#ibcon#[27=USB\r\n] 2006.257.21:45:39.43#ibcon#*before write, iclass 4, count 0 2006.257.21:45:39.43#ibcon#enter sib2, iclass 4, count 0 2006.257.21:45:39.43#ibcon#flushed, iclass 4, count 0 2006.257.21:45:39.43#ibcon#about to write, iclass 4, count 0 2006.257.21:45:39.43#ibcon#wrote, iclass 4, count 0 2006.257.21:45:39.43#ibcon#about to read 3, iclass 4, count 0 2006.257.21:45:39.46#ibcon#read 3, iclass 4, count 0 2006.257.21:45:39.46#ibcon#about to read 4, iclass 4, count 0 2006.257.21:45:39.46#ibcon#read 4, iclass 4, count 0 2006.257.21:45:39.46#ibcon#about to read 5, iclass 4, count 0 2006.257.21:45:39.46#ibcon#read 5, iclass 4, count 0 2006.257.21:45:39.46#ibcon#about to read 6, iclass 4, count 0 2006.257.21:45:39.46#ibcon#read 6, iclass 4, count 0 2006.257.21:45:39.46#ibcon#end of sib2, iclass 4, count 0 2006.257.21:45:39.46#ibcon#*after write, iclass 4, count 0 2006.257.21:45:39.46#ibcon#*before return 0, iclass 4, count 0 2006.257.21:45:39.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:39.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.21:45:39.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:45:39.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:45:39.46$vck44/vblo=5,709.99 2006.257.21:45:39.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.21:45:39.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.21:45:39.46#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:39.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:39.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:39.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:39.46#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:45:39.46#ibcon#first serial, iclass 6, count 0 2006.257.21:45:39.46#ibcon#enter sib2, iclass 6, count 0 2006.257.21:45:39.46#ibcon#flushed, iclass 6, count 0 2006.257.21:45:39.46#ibcon#about to write, iclass 6, count 0 2006.257.21:45:39.46#ibcon#wrote, iclass 6, count 0 2006.257.21:45:39.46#ibcon#about to read 3, iclass 6, count 0 2006.257.21:45:39.48#ibcon#read 3, iclass 6, count 0 2006.257.21:45:39.48#ibcon#about to read 4, iclass 6, count 0 2006.257.21:45:39.48#ibcon#read 4, iclass 6, count 0 2006.257.21:45:39.48#ibcon#about to read 5, iclass 6, count 0 2006.257.21:45:39.48#ibcon#read 5, iclass 6, count 0 2006.257.21:45:39.48#ibcon#about to read 6, iclass 6, count 0 2006.257.21:45:39.48#ibcon#read 6, iclass 6, count 0 2006.257.21:45:39.48#ibcon#end of sib2, iclass 6, count 0 2006.257.21:45:39.48#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:45:39.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:45:39.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.21:45:39.48#ibcon#*before write, iclass 6, count 0 2006.257.21:45:39.48#ibcon#enter sib2, iclass 6, count 0 2006.257.21:45:39.48#ibcon#flushed, iclass 6, count 0 2006.257.21:45:39.48#ibcon#about to write, iclass 6, count 0 2006.257.21:45:39.48#ibcon#wrote, iclass 6, count 0 2006.257.21:45:39.48#ibcon#about to read 3, iclass 6, count 0 2006.257.21:45:39.52#ibcon#read 3, iclass 6, count 0 2006.257.21:45:39.52#ibcon#about to read 4, iclass 6, count 0 2006.257.21:45:39.52#ibcon#read 4, iclass 6, count 0 2006.257.21:45:39.52#ibcon#about to read 5, iclass 6, count 0 2006.257.21:45:39.52#ibcon#read 5, iclass 6, count 0 2006.257.21:45:39.52#ibcon#about to read 6, iclass 6, count 0 2006.257.21:45:39.52#ibcon#read 6, iclass 6, count 0 2006.257.21:45:39.52#ibcon#end of sib2, iclass 6, count 0 2006.257.21:45:39.52#ibcon#*after write, iclass 6, count 0 2006.257.21:45:39.52#ibcon#*before return 0, iclass 6, count 0 2006.257.21:45:39.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:39.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.21:45:39.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:45:39.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:45:39.52$vck44/vb=5,4 2006.257.21:45:39.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.21:45:39.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.21:45:39.52#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:39.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:39.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:39.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:39.58#ibcon#enter wrdev, iclass 10, count 2 2006.257.21:45:39.58#ibcon#first serial, iclass 10, count 2 2006.257.21:45:39.58#ibcon#enter sib2, iclass 10, count 2 2006.257.21:45:39.58#ibcon#flushed, iclass 10, count 2 2006.257.21:45:39.58#ibcon#about to write, iclass 10, count 2 2006.257.21:45:39.58#ibcon#wrote, iclass 10, count 2 2006.257.21:45:39.58#ibcon#about to read 3, iclass 10, count 2 2006.257.21:45:39.60#ibcon#read 3, iclass 10, count 2 2006.257.21:45:39.60#ibcon#about to read 4, iclass 10, count 2 2006.257.21:45:39.60#ibcon#read 4, iclass 10, count 2 2006.257.21:45:39.60#ibcon#about to read 5, iclass 10, count 2 2006.257.21:45:39.60#ibcon#read 5, iclass 10, count 2 2006.257.21:45:39.60#ibcon#about to read 6, iclass 10, count 2 2006.257.21:45:39.60#ibcon#read 6, iclass 10, count 2 2006.257.21:45:39.60#ibcon#end of sib2, iclass 10, count 2 2006.257.21:45:39.60#ibcon#*mode == 0, iclass 10, count 2 2006.257.21:45:39.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.21:45:39.60#ibcon#[27=AT05-04\r\n] 2006.257.21:45:39.60#ibcon#*before write, iclass 10, count 2 2006.257.21:45:39.60#ibcon#enter sib2, iclass 10, count 2 2006.257.21:45:39.60#ibcon#flushed, iclass 10, count 2 2006.257.21:45:39.60#ibcon#about to write, iclass 10, count 2 2006.257.21:45:39.60#ibcon#wrote, iclass 10, count 2 2006.257.21:45:39.60#ibcon#about to read 3, iclass 10, count 2 2006.257.21:45:39.63#ibcon#read 3, iclass 10, count 2 2006.257.21:45:39.63#ibcon#about to read 4, iclass 10, count 2 2006.257.21:45:39.63#ibcon#read 4, iclass 10, count 2 2006.257.21:45:39.63#ibcon#about to read 5, iclass 10, count 2 2006.257.21:45:39.63#ibcon#read 5, iclass 10, count 2 2006.257.21:45:39.63#ibcon#about to read 6, iclass 10, count 2 2006.257.21:45:39.63#ibcon#read 6, iclass 10, count 2 2006.257.21:45:39.63#ibcon#end of sib2, iclass 10, count 2 2006.257.21:45:39.63#ibcon#*after write, iclass 10, count 2 2006.257.21:45:39.63#ibcon#*before return 0, iclass 10, count 2 2006.257.21:45:39.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:39.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.21:45:39.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.21:45:39.63#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:39.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:39.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:39.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:39.75#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:45:39.75#ibcon#first serial, iclass 10, count 0 2006.257.21:45:39.75#ibcon#enter sib2, iclass 10, count 0 2006.257.21:45:39.75#ibcon#flushed, iclass 10, count 0 2006.257.21:45:39.75#ibcon#about to write, iclass 10, count 0 2006.257.21:45:39.75#ibcon#wrote, iclass 10, count 0 2006.257.21:45:39.75#ibcon#about to read 3, iclass 10, count 0 2006.257.21:45:39.77#ibcon#read 3, iclass 10, count 0 2006.257.21:45:39.77#ibcon#about to read 4, iclass 10, count 0 2006.257.21:45:39.77#ibcon#read 4, iclass 10, count 0 2006.257.21:45:39.77#ibcon#about to read 5, iclass 10, count 0 2006.257.21:45:39.77#ibcon#read 5, iclass 10, count 0 2006.257.21:45:39.77#ibcon#about to read 6, iclass 10, count 0 2006.257.21:45:39.77#ibcon#read 6, iclass 10, count 0 2006.257.21:45:39.77#ibcon#end of sib2, iclass 10, count 0 2006.257.21:45:39.77#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:45:39.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:45:39.77#ibcon#[27=USB\r\n] 2006.257.21:45:39.77#ibcon#*before write, iclass 10, count 0 2006.257.21:45:39.77#ibcon#enter sib2, iclass 10, count 0 2006.257.21:45:39.77#ibcon#flushed, iclass 10, count 0 2006.257.21:45:39.77#ibcon#about to write, iclass 10, count 0 2006.257.21:45:39.77#ibcon#wrote, iclass 10, count 0 2006.257.21:45:39.77#ibcon#about to read 3, iclass 10, count 0 2006.257.21:45:39.80#ibcon#read 3, iclass 10, count 0 2006.257.21:45:39.80#ibcon#about to read 4, iclass 10, count 0 2006.257.21:45:39.80#ibcon#read 4, iclass 10, count 0 2006.257.21:45:39.80#ibcon#about to read 5, iclass 10, count 0 2006.257.21:45:39.80#ibcon#read 5, iclass 10, count 0 2006.257.21:45:39.80#ibcon#about to read 6, iclass 10, count 0 2006.257.21:45:39.80#ibcon#read 6, iclass 10, count 0 2006.257.21:45:39.80#ibcon#end of sib2, iclass 10, count 0 2006.257.21:45:39.80#ibcon#*after write, iclass 10, count 0 2006.257.21:45:39.80#ibcon#*before return 0, iclass 10, count 0 2006.257.21:45:39.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:39.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.21:45:39.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:45:39.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:45:39.80$vck44/vblo=6,719.99 2006.257.21:45:39.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.21:45:39.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.21:45:39.80#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:39.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:39.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:39.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:39.80#ibcon#enter wrdev, iclass 12, count 0 2006.257.21:45:39.80#ibcon#first serial, iclass 12, count 0 2006.257.21:45:39.80#ibcon#enter sib2, iclass 12, count 0 2006.257.21:45:39.80#ibcon#flushed, iclass 12, count 0 2006.257.21:45:39.80#ibcon#about to write, iclass 12, count 0 2006.257.21:45:39.80#ibcon#wrote, iclass 12, count 0 2006.257.21:45:39.80#ibcon#about to read 3, iclass 12, count 0 2006.257.21:45:39.82#ibcon#read 3, iclass 12, count 0 2006.257.21:45:39.82#ibcon#about to read 4, iclass 12, count 0 2006.257.21:45:39.82#ibcon#read 4, iclass 12, count 0 2006.257.21:45:39.82#ibcon#about to read 5, iclass 12, count 0 2006.257.21:45:39.82#ibcon#read 5, iclass 12, count 0 2006.257.21:45:39.82#ibcon#about to read 6, iclass 12, count 0 2006.257.21:45:39.82#ibcon#read 6, iclass 12, count 0 2006.257.21:45:39.82#ibcon#end of sib2, iclass 12, count 0 2006.257.21:45:39.82#ibcon#*mode == 0, iclass 12, count 0 2006.257.21:45:39.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.21:45:39.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.21:45:39.82#ibcon#*before write, iclass 12, count 0 2006.257.21:45:39.82#ibcon#enter sib2, iclass 12, count 0 2006.257.21:45:39.82#ibcon#flushed, iclass 12, count 0 2006.257.21:45:39.82#ibcon#about to write, iclass 12, count 0 2006.257.21:45:39.82#ibcon#wrote, iclass 12, count 0 2006.257.21:45:39.82#ibcon#about to read 3, iclass 12, count 0 2006.257.21:45:39.86#ibcon#read 3, iclass 12, count 0 2006.257.21:45:39.86#ibcon#about to read 4, iclass 12, count 0 2006.257.21:45:39.86#ibcon#read 4, iclass 12, count 0 2006.257.21:45:39.86#ibcon#about to read 5, iclass 12, count 0 2006.257.21:45:39.86#ibcon#read 5, iclass 12, count 0 2006.257.21:45:39.86#ibcon#about to read 6, iclass 12, count 0 2006.257.21:45:39.86#ibcon#read 6, iclass 12, count 0 2006.257.21:45:39.86#ibcon#end of sib2, iclass 12, count 0 2006.257.21:45:39.86#ibcon#*after write, iclass 12, count 0 2006.257.21:45:39.86#ibcon#*before return 0, iclass 12, count 0 2006.257.21:45:39.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:39.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.21:45:39.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.21:45:39.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.21:45:39.86$vck44/vb=6,4 2006.257.21:45:39.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.21:45:39.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.21:45:39.86#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:39.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:39.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:39.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:39.92#ibcon#enter wrdev, iclass 14, count 2 2006.257.21:45:39.92#ibcon#first serial, iclass 14, count 2 2006.257.21:45:39.92#ibcon#enter sib2, iclass 14, count 2 2006.257.21:45:39.92#ibcon#flushed, iclass 14, count 2 2006.257.21:45:39.92#ibcon#about to write, iclass 14, count 2 2006.257.21:45:39.92#ibcon#wrote, iclass 14, count 2 2006.257.21:45:39.92#ibcon#about to read 3, iclass 14, count 2 2006.257.21:45:39.94#ibcon#read 3, iclass 14, count 2 2006.257.21:45:39.94#ibcon#about to read 4, iclass 14, count 2 2006.257.21:45:39.94#ibcon#read 4, iclass 14, count 2 2006.257.21:45:39.94#ibcon#about to read 5, iclass 14, count 2 2006.257.21:45:39.94#ibcon#read 5, iclass 14, count 2 2006.257.21:45:39.94#ibcon#about to read 6, iclass 14, count 2 2006.257.21:45:39.94#ibcon#read 6, iclass 14, count 2 2006.257.21:45:39.94#ibcon#end of sib2, iclass 14, count 2 2006.257.21:45:39.94#ibcon#*mode == 0, iclass 14, count 2 2006.257.21:45:39.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.21:45:39.94#ibcon#[27=AT06-04\r\n] 2006.257.21:45:39.94#ibcon#*before write, iclass 14, count 2 2006.257.21:45:39.94#ibcon#enter sib2, iclass 14, count 2 2006.257.21:45:39.94#ibcon#flushed, iclass 14, count 2 2006.257.21:45:39.94#ibcon#about to write, iclass 14, count 2 2006.257.21:45:39.94#ibcon#wrote, iclass 14, count 2 2006.257.21:45:39.94#ibcon#about to read 3, iclass 14, count 2 2006.257.21:45:39.97#ibcon#read 3, iclass 14, count 2 2006.257.21:45:39.97#ibcon#about to read 4, iclass 14, count 2 2006.257.21:45:39.97#ibcon#read 4, iclass 14, count 2 2006.257.21:45:39.97#ibcon#about to read 5, iclass 14, count 2 2006.257.21:45:39.97#ibcon#read 5, iclass 14, count 2 2006.257.21:45:39.97#ibcon#about to read 6, iclass 14, count 2 2006.257.21:45:39.97#ibcon#read 6, iclass 14, count 2 2006.257.21:45:39.97#ibcon#end of sib2, iclass 14, count 2 2006.257.21:45:39.97#ibcon#*after write, iclass 14, count 2 2006.257.21:45:39.97#ibcon#*before return 0, iclass 14, count 2 2006.257.21:45:39.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:39.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.21:45:39.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.21:45:39.97#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:39.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:40.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:40.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:40.09#ibcon#enter wrdev, iclass 14, count 0 2006.257.21:45:40.09#ibcon#first serial, iclass 14, count 0 2006.257.21:45:40.09#ibcon#enter sib2, iclass 14, count 0 2006.257.21:45:40.09#ibcon#flushed, iclass 14, count 0 2006.257.21:45:40.09#ibcon#about to write, iclass 14, count 0 2006.257.21:45:40.09#ibcon#wrote, iclass 14, count 0 2006.257.21:45:40.09#ibcon#about to read 3, iclass 14, count 0 2006.257.21:45:40.11#ibcon#read 3, iclass 14, count 0 2006.257.21:45:40.11#ibcon#about to read 4, iclass 14, count 0 2006.257.21:45:40.11#ibcon#read 4, iclass 14, count 0 2006.257.21:45:40.11#ibcon#about to read 5, iclass 14, count 0 2006.257.21:45:40.11#ibcon#read 5, iclass 14, count 0 2006.257.21:45:40.11#ibcon#about to read 6, iclass 14, count 0 2006.257.21:45:40.11#ibcon#read 6, iclass 14, count 0 2006.257.21:45:40.11#ibcon#end of sib2, iclass 14, count 0 2006.257.21:45:40.11#ibcon#*mode == 0, iclass 14, count 0 2006.257.21:45:40.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.21:45:40.11#ibcon#[27=USB\r\n] 2006.257.21:45:40.11#ibcon#*before write, iclass 14, count 0 2006.257.21:45:40.11#ibcon#enter sib2, iclass 14, count 0 2006.257.21:45:40.11#ibcon#flushed, iclass 14, count 0 2006.257.21:45:40.11#ibcon#about to write, iclass 14, count 0 2006.257.21:45:40.11#ibcon#wrote, iclass 14, count 0 2006.257.21:45:40.11#ibcon#about to read 3, iclass 14, count 0 2006.257.21:45:40.14#ibcon#read 3, iclass 14, count 0 2006.257.21:45:40.14#ibcon#about to read 4, iclass 14, count 0 2006.257.21:45:40.14#ibcon#read 4, iclass 14, count 0 2006.257.21:45:40.14#ibcon#about to read 5, iclass 14, count 0 2006.257.21:45:40.14#ibcon#read 5, iclass 14, count 0 2006.257.21:45:40.14#ibcon#about to read 6, iclass 14, count 0 2006.257.21:45:40.14#ibcon#read 6, iclass 14, count 0 2006.257.21:45:40.14#ibcon#end of sib2, iclass 14, count 0 2006.257.21:45:40.14#ibcon#*after write, iclass 14, count 0 2006.257.21:45:40.14#ibcon#*before return 0, iclass 14, count 0 2006.257.21:45:40.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:40.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.21:45:40.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.21:45:40.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.21:45:40.14$vck44/vblo=7,734.99 2006.257.21:45:40.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.21:45:40.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.21:45:40.14#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:40.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:40.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:40.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:40.14#ibcon#enter wrdev, iclass 16, count 0 2006.257.21:45:40.14#ibcon#first serial, iclass 16, count 0 2006.257.21:45:40.14#ibcon#enter sib2, iclass 16, count 0 2006.257.21:45:40.14#ibcon#flushed, iclass 16, count 0 2006.257.21:45:40.14#ibcon#about to write, iclass 16, count 0 2006.257.21:45:40.14#ibcon#wrote, iclass 16, count 0 2006.257.21:45:40.14#ibcon#about to read 3, iclass 16, count 0 2006.257.21:45:40.16#ibcon#read 3, iclass 16, count 0 2006.257.21:45:40.16#ibcon#about to read 4, iclass 16, count 0 2006.257.21:45:40.16#ibcon#read 4, iclass 16, count 0 2006.257.21:45:40.16#ibcon#about to read 5, iclass 16, count 0 2006.257.21:45:40.16#ibcon#read 5, iclass 16, count 0 2006.257.21:45:40.16#ibcon#about to read 6, iclass 16, count 0 2006.257.21:45:40.16#ibcon#read 6, iclass 16, count 0 2006.257.21:45:40.16#ibcon#end of sib2, iclass 16, count 0 2006.257.21:45:40.16#ibcon#*mode == 0, iclass 16, count 0 2006.257.21:45:40.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.21:45:40.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.21:45:40.16#ibcon#*before write, iclass 16, count 0 2006.257.21:45:40.16#ibcon#enter sib2, iclass 16, count 0 2006.257.21:45:40.16#ibcon#flushed, iclass 16, count 0 2006.257.21:45:40.16#ibcon#about to write, iclass 16, count 0 2006.257.21:45:40.16#ibcon#wrote, iclass 16, count 0 2006.257.21:45:40.16#ibcon#about to read 3, iclass 16, count 0 2006.257.21:45:40.20#ibcon#read 3, iclass 16, count 0 2006.257.21:45:40.20#ibcon#about to read 4, iclass 16, count 0 2006.257.21:45:40.20#ibcon#read 4, iclass 16, count 0 2006.257.21:45:40.20#ibcon#about to read 5, iclass 16, count 0 2006.257.21:45:40.20#ibcon#read 5, iclass 16, count 0 2006.257.21:45:40.20#ibcon#about to read 6, iclass 16, count 0 2006.257.21:45:40.20#ibcon#read 6, iclass 16, count 0 2006.257.21:45:40.20#ibcon#end of sib2, iclass 16, count 0 2006.257.21:45:40.20#ibcon#*after write, iclass 16, count 0 2006.257.21:45:40.20#ibcon#*before return 0, iclass 16, count 0 2006.257.21:45:40.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:40.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.21:45:40.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.21:45:40.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.21:45:40.20$vck44/vb=7,4 2006.257.21:45:40.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.21:45:40.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.21:45:40.20#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:40.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:40.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:40.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:40.26#ibcon#enter wrdev, iclass 18, count 2 2006.257.21:45:40.26#ibcon#first serial, iclass 18, count 2 2006.257.21:45:40.26#ibcon#enter sib2, iclass 18, count 2 2006.257.21:45:40.26#ibcon#flushed, iclass 18, count 2 2006.257.21:45:40.26#ibcon#about to write, iclass 18, count 2 2006.257.21:45:40.26#ibcon#wrote, iclass 18, count 2 2006.257.21:45:40.26#ibcon#about to read 3, iclass 18, count 2 2006.257.21:45:40.28#ibcon#read 3, iclass 18, count 2 2006.257.21:45:40.28#ibcon#about to read 4, iclass 18, count 2 2006.257.21:45:40.28#ibcon#read 4, iclass 18, count 2 2006.257.21:45:40.28#ibcon#about to read 5, iclass 18, count 2 2006.257.21:45:40.28#ibcon#read 5, iclass 18, count 2 2006.257.21:45:40.28#ibcon#about to read 6, iclass 18, count 2 2006.257.21:45:40.28#ibcon#read 6, iclass 18, count 2 2006.257.21:45:40.28#ibcon#end of sib2, iclass 18, count 2 2006.257.21:45:40.28#ibcon#*mode == 0, iclass 18, count 2 2006.257.21:45:40.28#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.21:45:40.28#ibcon#[27=AT07-04\r\n] 2006.257.21:45:40.28#ibcon#*before write, iclass 18, count 2 2006.257.21:45:40.28#ibcon#enter sib2, iclass 18, count 2 2006.257.21:45:40.28#ibcon#flushed, iclass 18, count 2 2006.257.21:45:40.28#ibcon#about to write, iclass 18, count 2 2006.257.21:45:40.28#ibcon#wrote, iclass 18, count 2 2006.257.21:45:40.28#ibcon#about to read 3, iclass 18, count 2 2006.257.21:45:40.31#ibcon#read 3, iclass 18, count 2 2006.257.21:45:40.31#ibcon#about to read 4, iclass 18, count 2 2006.257.21:45:40.31#ibcon#read 4, iclass 18, count 2 2006.257.21:45:40.31#ibcon#about to read 5, iclass 18, count 2 2006.257.21:45:40.31#ibcon#read 5, iclass 18, count 2 2006.257.21:45:40.31#ibcon#about to read 6, iclass 18, count 2 2006.257.21:45:40.31#ibcon#read 6, iclass 18, count 2 2006.257.21:45:40.31#ibcon#end of sib2, iclass 18, count 2 2006.257.21:45:40.31#ibcon#*after write, iclass 18, count 2 2006.257.21:45:40.31#ibcon#*before return 0, iclass 18, count 2 2006.257.21:45:40.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:40.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.21:45:40.31#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.21:45:40.31#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:40.31#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:40.43#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:40.43#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:40.43#ibcon#enter wrdev, iclass 18, count 0 2006.257.21:45:40.43#ibcon#first serial, iclass 18, count 0 2006.257.21:45:40.43#ibcon#enter sib2, iclass 18, count 0 2006.257.21:45:40.43#ibcon#flushed, iclass 18, count 0 2006.257.21:45:40.43#ibcon#about to write, iclass 18, count 0 2006.257.21:45:40.43#ibcon#wrote, iclass 18, count 0 2006.257.21:45:40.43#ibcon#about to read 3, iclass 18, count 0 2006.257.21:45:40.45#ibcon#read 3, iclass 18, count 0 2006.257.21:45:40.45#ibcon#about to read 4, iclass 18, count 0 2006.257.21:45:40.45#ibcon#read 4, iclass 18, count 0 2006.257.21:45:40.45#ibcon#about to read 5, iclass 18, count 0 2006.257.21:45:40.45#ibcon#read 5, iclass 18, count 0 2006.257.21:45:40.45#ibcon#about to read 6, iclass 18, count 0 2006.257.21:45:40.45#ibcon#read 6, iclass 18, count 0 2006.257.21:45:40.45#ibcon#end of sib2, iclass 18, count 0 2006.257.21:45:40.45#ibcon#*mode == 0, iclass 18, count 0 2006.257.21:45:40.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.21:45:40.45#ibcon#[27=USB\r\n] 2006.257.21:45:40.45#ibcon#*before write, iclass 18, count 0 2006.257.21:45:40.45#ibcon#enter sib2, iclass 18, count 0 2006.257.21:45:40.45#ibcon#flushed, iclass 18, count 0 2006.257.21:45:40.45#ibcon#about to write, iclass 18, count 0 2006.257.21:45:40.45#ibcon#wrote, iclass 18, count 0 2006.257.21:45:40.45#ibcon#about to read 3, iclass 18, count 0 2006.257.21:45:40.48#ibcon#read 3, iclass 18, count 0 2006.257.21:45:40.48#ibcon#about to read 4, iclass 18, count 0 2006.257.21:45:40.48#ibcon#read 4, iclass 18, count 0 2006.257.21:45:40.48#ibcon#about to read 5, iclass 18, count 0 2006.257.21:45:40.48#ibcon#read 5, iclass 18, count 0 2006.257.21:45:40.48#ibcon#about to read 6, iclass 18, count 0 2006.257.21:45:40.48#ibcon#read 6, iclass 18, count 0 2006.257.21:45:40.48#ibcon#end of sib2, iclass 18, count 0 2006.257.21:45:40.48#ibcon#*after write, iclass 18, count 0 2006.257.21:45:40.48#ibcon#*before return 0, iclass 18, count 0 2006.257.21:45:40.48#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:40.48#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.21:45:40.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.21:45:40.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.21:45:40.48$vck44/vblo=8,744.99 2006.257.21:45:40.48#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.21:45:40.48#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.21:45:40.48#ibcon#ireg 17 cls_cnt 0 2006.257.21:45:40.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:40.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:40.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:40.48#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:45:40.48#ibcon#first serial, iclass 20, count 0 2006.257.21:45:40.48#ibcon#enter sib2, iclass 20, count 0 2006.257.21:45:40.48#ibcon#flushed, iclass 20, count 0 2006.257.21:45:40.48#ibcon#about to write, iclass 20, count 0 2006.257.21:45:40.48#ibcon#wrote, iclass 20, count 0 2006.257.21:45:40.48#ibcon#about to read 3, iclass 20, count 0 2006.257.21:45:40.50#ibcon#read 3, iclass 20, count 0 2006.257.21:45:40.50#ibcon#about to read 4, iclass 20, count 0 2006.257.21:45:40.50#ibcon#read 4, iclass 20, count 0 2006.257.21:45:40.50#ibcon#about to read 5, iclass 20, count 0 2006.257.21:45:40.50#ibcon#read 5, iclass 20, count 0 2006.257.21:45:40.50#ibcon#about to read 6, iclass 20, count 0 2006.257.21:45:40.50#ibcon#read 6, iclass 20, count 0 2006.257.21:45:40.50#ibcon#end of sib2, iclass 20, count 0 2006.257.21:45:40.50#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:45:40.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:45:40.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.21:45:40.50#ibcon#*before write, iclass 20, count 0 2006.257.21:45:40.50#ibcon#enter sib2, iclass 20, count 0 2006.257.21:45:40.50#ibcon#flushed, iclass 20, count 0 2006.257.21:45:40.50#ibcon#about to write, iclass 20, count 0 2006.257.21:45:40.50#ibcon#wrote, iclass 20, count 0 2006.257.21:45:40.50#ibcon#about to read 3, iclass 20, count 0 2006.257.21:45:40.54#ibcon#read 3, iclass 20, count 0 2006.257.21:45:40.54#ibcon#about to read 4, iclass 20, count 0 2006.257.21:45:40.54#ibcon#read 4, iclass 20, count 0 2006.257.21:45:40.54#ibcon#about to read 5, iclass 20, count 0 2006.257.21:45:40.54#ibcon#read 5, iclass 20, count 0 2006.257.21:45:40.54#ibcon#about to read 6, iclass 20, count 0 2006.257.21:45:40.54#ibcon#read 6, iclass 20, count 0 2006.257.21:45:40.54#ibcon#end of sib2, iclass 20, count 0 2006.257.21:45:40.54#ibcon#*after write, iclass 20, count 0 2006.257.21:45:40.54#ibcon#*before return 0, iclass 20, count 0 2006.257.21:45:40.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:40.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.21:45:40.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:45:40.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:45:40.54$vck44/vb=8,4 2006.257.21:45:40.54#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.21:45:40.54#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.21:45:40.54#ibcon#ireg 11 cls_cnt 2 2006.257.21:45:40.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:40.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:40.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:40.60#ibcon#enter wrdev, iclass 22, count 2 2006.257.21:45:40.60#ibcon#first serial, iclass 22, count 2 2006.257.21:45:40.60#ibcon#enter sib2, iclass 22, count 2 2006.257.21:45:40.60#ibcon#flushed, iclass 22, count 2 2006.257.21:45:40.60#ibcon#about to write, iclass 22, count 2 2006.257.21:45:40.60#ibcon#wrote, iclass 22, count 2 2006.257.21:45:40.60#ibcon#about to read 3, iclass 22, count 2 2006.257.21:45:40.62#ibcon#read 3, iclass 22, count 2 2006.257.21:45:40.62#ibcon#about to read 4, iclass 22, count 2 2006.257.21:45:40.62#ibcon#read 4, iclass 22, count 2 2006.257.21:45:40.62#ibcon#about to read 5, iclass 22, count 2 2006.257.21:45:40.62#ibcon#read 5, iclass 22, count 2 2006.257.21:45:40.62#ibcon#about to read 6, iclass 22, count 2 2006.257.21:45:40.62#ibcon#read 6, iclass 22, count 2 2006.257.21:45:40.62#ibcon#end of sib2, iclass 22, count 2 2006.257.21:45:40.62#ibcon#*mode == 0, iclass 22, count 2 2006.257.21:45:40.62#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.21:45:40.62#ibcon#[27=AT08-04\r\n] 2006.257.21:45:40.62#ibcon#*before write, iclass 22, count 2 2006.257.21:45:40.62#ibcon#enter sib2, iclass 22, count 2 2006.257.21:45:40.62#ibcon#flushed, iclass 22, count 2 2006.257.21:45:40.62#ibcon#about to write, iclass 22, count 2 2006.257.21:45:40.62#ibcon#wrote, iclass 22, count 2 2006.257.21:45:40.62#ibcon#about to read 3, iclass 22, count 2 2006.257.21:45:40.65#ibcon#read 3, iclass 22, count 2 2006.257.21:45:40.65#ibcon#about to read 4, iclass 22, count 2 2006.257.21:45:40.65#ibcon#read 4, iclass 22, count 2 2006.257.21:45:40.65#ibcon#about to read 5, iclass 22, count 2 2006.257.21:45:40.65#ibcon#read 5, iclass 22, count 2 2006.257.21:45:40.65#ibcon#about to read 6, iclass 22, count 2 2006.257.21:45:40.65#ibcon#read 6, iclass 22, count 2 2006.257.21:45:40.65#ibcon#end of sib2, iclass 22, count 2 2006.257.21:45:40.65#ibcon#*after write, iclass 22, count 2 2006.257.21:45:40.65#ibcon#*before return 0, iclass 22, count 2 2006.257.21:45:40.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:40.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.21:45:40.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.21:45:40.65#ibcon#ireg 7 cls_cnt 0 2006.257.21:45:40.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:40.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:40.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:40.77#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:45:40.77#ibcon#first serial, iclass 22, count 0 2006.257.21:45:40.77#ibcon#enter sib2, iclass 22, count 0 2006.257.21:45:40.77#ibcon#flushed, iclass 22, count 0 2006.257.21:45:40.77#ibcon#about to write, iclass 22, count 0 2006.257.21:45:40.77#ibcon#wrote, iclass 22, count 0 2006.257.21:45:40.77#ibcon#about to read 3, iclass 22, count 0 2006.257.21:45:40.79#ibcon#read 3, iclass 22, count 0 2006.257.21:45:40.79#ibcon#about to read 4, iclass 22, count 0 2006.257.21:45:40.79#ibcon#read 4, iclass 22, count 0 2006.257.21:45:40.79#ibcon#about to read 5, iclass 22, count 0 2006.257.21:45:40.79#ibcon#read 5, iclass 22, count 0 2006.257.21:45:40.79#ibcon#about to read 6, iclass 22, count 0 2006.257.21:45:40.79#ibcon#read 6, iclass 22, count 0 2006.257.21:45:40.79#ibcon#end of sib2, iclass 22, count 0 2006.257.21:45:40.79#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:45:40.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:45:40.79#ibcon#[27=USB\r\n] 2006.257.21:45:40.79#ibcon#*before write, iclass 22, count 0 2006.257.21:45:40.79#ibcon#enter sib2, iclass 22, count 0 2006.257.21:45:40.79#ibcon#flushed, iclass 22, count 0 2006.257.21:45:40.79#ibcon#about to write, iclass 22, count 0 2006.257.21:45:40.79#ibcon#wrote, iclass 22, count 0 2006.257.21:45:40.79#ibcon#about to read 3, iclass 22, count 0 2006.257.21:45:40.82#ibcon#read 3, iclass 22, count 0 2006.257.21:45:40.82#ibcon#about to read 4, iclass 22, count 0 2006.257.21:45:40.82#ibcon#read 4, iclass 22, count 0 2006.257.21:45:40.82#ibcon#about to read 5, iclass 22, count 0 2006.257.21:45:40.82#ibcon#read 5, iclass 22, count 0 2006.257.21:45:40.82#ibcon#about to read 6, iclass 22, count 0 2006.257.21:45:40.82#ibcon#read 6, iclass 22, count 0 2006.257.21:45:40.82#ibcon#end of sib2, iclass 22, count 0 2006.257.21:45:40.82#ibcon#*after write, iclass 22, count 0 2006.257.21:45:40.82#ibcon#*before return 0, iclass 22, count 0 2006.257.21:45:40.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:40.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.21:45:40.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:45:40.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:45:40.82$vck44/vabw=wide 2006.257.21:45:40.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.21:45:40.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.21:45:40.82#ibcon#ireg 8 cls_cnt 0 2006.257.21:45:40.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:40.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:40.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:40.82#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:45:40.82#ibcon#first serial, iclass 24, count 0 2006.257.21:45:40.82#ibcon#enter sib2, iclass 24, count 0 2006.257.21:45:40.82#ibcon#flushed, iclass 24, count 0 2006.257.21:45:40.82#ibcon#about to write, iclass 24, count 0 2006.257.21:45:40.82#ibcon#wrote, iclass 24, count 0 2006.257.21:45:40.82#ibcon#about to read 3, iclass 24, count 0 2006.257.21:45:40.84#ibcon#read 3, iclass 24, count 0 2006.257.21:45:40.84#ibcon#about to read 4, iclass 24, count 0 2006.257.21:45:40.84#ibcon#read 4, iclass 24, count 0 2006.257.21:45:40.84#ibcon#about to read 5, iclass 24, count 0 2006.257.21:45:40.84#ibcon#read 5, iclass 24, count 0 2006.257.21:45:40.84#ibcon#about to read 6, iclass 24, count 0 2006.257.21:45:40.84#ibcon#read 6, iclass 24, count 0 2006.257.21:45:40.84#ibcon#end of sib2, iclass 24, count 0 2006.257.21:45:40.84#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:45:40.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:45:40.84#ibcon#[25=BW32\r\n] 2006.257.21:45:40.84#ibcon#*before write, iclass 24, count 0 2006.257.21:45:40.84#ibcon#enter sib2, iclass 24, count 0 2006.257.21:45:40.84#ibcon#flushed, iclass 24, count 0 2006.257.21:45:40.84#ibcon#about to write, iclass 24, count 0 2006.257.21:45:40.84#ibcon#wrote, iclass 24, count 0 2006.257.21:45:40.84#ibcon#about to read 3, iclass 24, count 0 2006.257.21:45:40.87#ibcon#read 3, iclass 24, count 0 2006.257.21:45:40.87#ibcon#about to read 4, iclass 24, count 0 2006.257.21:45:40.87#ibcon#read 4, iclass 24, count 0 2006.257.21:45:40.87#ibcon#about to read 5, iclass 24, count 0 2006.257.21:45:40.87#ibcon#read 5, iclass 24, count 0 2006.257.21:45:40.87#ibcon#about to read 6, iclass 24, count 0 2006.257.21:45:40.87#ibcon#read 6, iclass 24, count 0 2006.257.21:45:40.87#ibcon#end of sib2, iclass 24, count 0 2006.257.21:45:40.87#ibcon#*after write, iclass 24, count 0 2006.257.21:45:40.87#ibcon#*before return 0, iclass 24, count 0 2006.257.21:45:40.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:40.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.21:45:40.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:45:40.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:45:40.87$vck44/vbbw=wide 2006.257.21:45:40.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.21:45:40.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.21:45:40.87#ibcon#ireg 8 cls_cnt 0 2006.257.21:45:40.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:45:40.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:45:40.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:45:40.94#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:45:40.94#ibcon#first serial, iclass 26, count 0 2006.257.21:45:40.94#ibcon#enter sib2, iclass 26, count 0 2006.257.21:45:40.94#ibcon#flushed, iclass 26, count 0 2006.257.21:45:40.94#ibcon#about to write, iclass 26, count 0 2006.257.21:45:40.94#ibcon#wrote, iclass 26, count 0 2006.257.21:45:40.94#ibcon#about to read 3, iclass 26, count 0 2006.257.21:45:40.96#ibcon#read 3, iclass 26, count 0 2006.257.21:45:40.96#ibcon#about to read 4, iclass 26, count 0 2006.257.21:45:40.96#ibcon#read 4, iclass 26, count 0 2006.257.21:45:40.96#ibcon#about to read 5, iclass 26, count 0 2006.257.21:45:40.96#ibcon#read 5, iclass 26, count 0 2006.257.21:45:40.96#ibcon#about to read 6, iclass 26, count 0 2006.257.21:45:40.96#ibcon#read 6, iclass 26, count 0 2006.257.21:45:40.96#ibcon#end of sib2, iclass 26, count 0 2006.257.21:45:40.96#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:45:40.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:45:40.96#ibcon#[27=BW32\r\n] 2006.257.21:45:40.96#ibcon#*before write, iclass 26, count 0 2006.257.21:45:40.96#ibcon#enter sib2, iclass 26, count 0 2006.257.21:45:40.96#ibcon#flushed, iclass 26, count 0 2006.257.21:45:40.96#ibcon#about to write, iclass 26, count 0 2006.257.21:45:40.96#ibcon#wrote, iclass 26, count 0 2006.257.21:45:40.96#ibcon#about to read 3, iclass 26, count 0 2006.257.21:45:40.99#ibcon#read 3, iclass 26, count 0 2006.257.21:45:40.99#ibcon#about to read 4, iclass 26, count 0 2006.257.21:45:40.99#ibcon#read 4, iclass 26, count 0 2006.257.21:45:40.99#ibcon#about to read 5, iclass 26, count 0 2006.257.21:45:40.99#ibcon#read 5, iclass 26, count 0 2006.257.21:45:40.99#ibcon#about to read 6, iclass 26, count 0 2006.257.21:45:40.99#ibcon#read 6, iclass 26, count 0 2006.257.21:45:40.99#ibcon#end of sib2, iclass 26, count 0 2006.257.21:45:40.99#ibcon#*after write, iclass 26, count 0 2006.257.21:45:40.99#ibcon#*before return 0, iclass 26, count 0 2006.257.21:45:40.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:45:40.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:45:40.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:45:40.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:45:40.99$setupk4/ifdk4 2006.257.21:45:40.99$ifdk4/lo= 2006.257.21:45:40.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.21:45:40.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.21:45:40.99$ifdk4/patch= 2006.257.21:45:40.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.21:45:40.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.21:45:40.99$setupk4/!*+20s 2006.257.21:45:44.03#abcon#<5=/13 0.8 2.0 18.03 941015.4\r\n> 2006.257.21:45:44.05#abcon#{5=INTERFACE CLEAR} 2006.257.21:45:44.11#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:45:54.20#abcon#<5=/13 0.8 2.0 18.03 941015.4\r\n> 2006.257.21:45:54.22#abcon#{5=INTERFACE CLEAR} 2006.257.21:45:54.28#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:45:55.50$setupk4/"tpicd 2006.257.21:45:55.50$setupk4/echo=off 2006.257.21:45:55.50$setupk4/xlog=off 2006.257.21:45:55.50:!2006.257.21:46:26 2006.257.21:45:56.14#trakl#Source acquired 2006.257.21:45:56.14#flagr#flagr/antenna,acquired 2006.257.21:46:26.00:preob 2006.257.21:46:27.14/onsource/TRACKING 2006.257.21:46:27.14:!2006.257.21:46:36 2006.257.21:46:36.00:"tape 2006.257.21:46:36.00:"st=record 2006.257.21:46:36.00:data_valid=on 2006.257.21:46:36.00:midob 2006.257.21:46:36.14/onsource/TRACKING 2006.257.21:46:36.14/wx/18.05,1015.4,94 2006.257.21:46:36.31/cable/+6.4848E-03 2006.257.21:46:37.40/va/01,08,usb,yes,31,33 2006.257.21:46:37.40/va/02,07,usb,yes,34,34 2006.257.21:46:37.40/va/03,08,usb,yes,30,32 2006.257.21:46:37.40/va/04,07,usb,yes,35,36 2006.257.21:46:37.40/va/05,04,usb,yes,31,31 2006.257.21:46:37.40/va/06,04,usb,yes,34,34 2006.257.21:46:37.40/va/07,04,usb,yes,35,36 2006.257.21:46:37.40/va/08,04,usb,yes,29,36 2006.257.21:46:37.63/valo/01,524.99,yes,locked 2006.257.21:46:37.63/valo/02,534.99,yes,locked 2006.257.21:46:37.63/valo/03,564.99,yes,locked 2006.257.21:46:37.63/valo/04,624.99,yes,locked 2006.257.21:46:37.63/valo/05,734.99,yes,locked 2006.257.21:46:37.63/valo/06,814.99,yes,locked 2006.257.21:46:37.63/valo/07,864.99,yes,locked 2006.257.21:46:37.63/valo/08,884.99,yes,locked 2006.257.21:46:38.72/vb/01,04,usb,yes,30,28 2006.257.21:46:38.72/vb/02,05,usb,yes,28,28 2006.257.21:46:38.72/vb/03,04,usb,yes,29,32 2006.257.21:46:38.72/vb/04,05,usb,yes,29,28 2006.257.21:46:38.72/vb/05,04,usb,yes,26,28 2006.257.21:46:38.72/vb/06,04,usb,yes,30,27 2006.257.21:46:38.72/vb/07,04,usb,yes,30,30 2006.257.21:46:38.72/vb/08,04,usb,yes,28,31 2006.257.21:46:38.96/vblo/01,629.99,yes,locked 2006.257.21:46:38.96/vblo/02,634.99,yes,locked 2006.257.21:46:38.96/vblo/03,649.99,yes,locked 2006.257.21:46:38.96/vblo/04,679.99,yes,locked 2006.257.21:46:38.96/vblo/05,709.99,yes,locked 2006.257.21:46:38.96/vblo/06,719.99,yes,locked 2006.257.21:46:38.96/vblo/07,734.99,yes,locked 2006.257.21:46:38.96/vblo/08,744.99,yes,locked 2006.257.21:46:39.11/vabw/8 2006.257.21:46:39.26/vbbw/8 2006.257.21:46:39.35/xfe/off,on,15.2 2006.257.21:46:39.72/ifatt/23,28,28,28 2006.257.21:46:40.07/fmout-gps/S +4.48E-07 2006.257.21:46:40.11:!2006.257.21:51:26 2006.257.21:51:26.01:data_valid=off 2006.257.21:51:26.01:"et 2006.257.21:51:26.01:!+3s 2006.257.21:51:29.02:"tape 2006.257.21:51:29.02:postob 2006.257.21:51:29.18/cable/+6.4837E-03 2006.257.21:51:29.18/wx/18.19,1015.4,94 2006.257.21:51:29.24/fmout-gps/S +4.47E-07 2006.257.21:51:29.24:scan_name=257-2155,jd0609,40 2006.257.21:51:29.24:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.257.21:51:30.13#flagr#flagr/antenna,new-source 2006.257.21:51:30.13:checkk5 2006.257.21:51:30.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.21:51:30.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.21:51:31.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.21:51:31.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.21:51:31.87/chk_obsdata//k5ts1/T2572146??a.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.257.21:51:32.19/chk_obsdata//k5ts2/T2572146??b.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.257.21:51:32.53/chk_obsdata//k5ts3/T2572146??c.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.257.21:51:32.86/chk_obsdata//k5ts4/T2572146??d.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.257.21:51:33.52/k5log//k5ts1_log_newline 2006.257.21:51:34.17/k5log//k5ts2_log_newline 2006.257.21:51:34.83/k5log//k5ts3_log_newline 2006.257.21:51:35.48/k5log//k5ts4_log_newline 2006.257.21:51:35.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.21:51:35.51:setupk4=1 2006.257.21:51:35.51$setupk4/echo=on 2006.257.21:51:35.51$setupk4/pcalon 2006.257.21:51:35.51$pcalon/"no phase cal control is implemented here 2006.257.21:51:35.51$setupk4/"tpicd=stop 2006.257.21:51:35.51$setupk4/"rec=synch_on 2006.257.21:51:35.51$setupk4/"rec_mode=128 2006.257.21:51:35.51$setupk4/!* 2006.257.21:51:35.51$setupk4/recpk4 2006.257.21:51:35.51$recpk4/recpatch= 2006.257.21:51:35.51$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.21:51:35.51$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.21:51:35.52$setupk4/vck44 2006.257.21:51:35.52$vck44/valo=1,524.99 2006.257.21:51:35.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.21:51:35.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.21:51:35.52#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:35.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:35.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:35.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:35.52#ibcon#enter wrdev, iclass 27, count 0 2006.257.21:51:35.52#ibcon#first serial, iclass 27, count 0 2006.257.21:51:35.52#ibcon#enter sib2, iclass 27, count 0 2006.257.21:51:35.52#ibcon#flushed, iclass 27, count 0 2006.257.21:51:35.52#ibcon#about to write, iclass 27, count 0 2006.257.21:51:35.52#ibcon#wrote, iclass 27, count 0 2006.257.21:51:35.52#ibcon#about to read 3, iclass 27, count 0 2006.257.21:51:35.53#ibcon#read 3, iclass 27, count 0 2006.257.21:51:35.53#ibcon#about to read 4, iclass 27, count 0 2006.257.21:51:35.53#ibcon#read 4, iclass 27, count 0 2006.257.21:51:35.53#ibcon#about to read 5, iclass 27, count 0 2006.257.21:51:35.53#ibcon#read 5, iclass 27, count 0 2006.257.21:51:35.53#ibcon#about to read 6, iclass 27, count 0 2006.257.21:51:35.53#ibcon#read 6, iclass 27, count 0 2006.257.21:51:35.53#ibcon#end of sib2, iclass 27, count 0 2006.257.21:51:35.53#ibcon#*mode == 0, iclass 27, count 0 2006.257.21:51:35.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.21:51:35.53#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.21:51:35.53#ibcon#*before write, iclass 27, count 0 2006.257.21:51:35.53#ibcon#enter sib2, iclass 27, count 0 2006.257.21:51:35.53#ibcon#flushed, iclass 27, count 0 2006.257.21:51:35.53#ibcon#about to write, iclass 27, count 0 2006.257.21:51:35.53#ibcon#wrote, iclass 27, count 0 2006.257.21:51:35.53#ibcon#about to read 3, iclass 27, count 0 2006.257.21:51:35.58#ibcon#read 3, iclass 27, count 0 2006.257.21:51:35.58#ibcon#about to read 4, iclass 27, count 0 2006.257.21:51:35.58#ibcon#read 4, iclass 27, count 0 2006.257.21:51:35.58#ibcon#about to read 5, iclass 27, count 0 2006.257.21:51:35.58#ibcon#read 5, iclass 27, count 0 2006.257.21:51:35.58#ibcon#about to read 6, iclass 27, count 0 2006.257.21:51:35.58#ibcon#read 6, iclass 27, count 0 2006.257.21:51:35.58#ibcon#end of sib2, iclass 27, count 0 2006.257.21:51:35.58#ibcon#*after write, iclass 27, count 0 2006.257.21:51:35.58#ibcon#*before return 0, iclass 27, count 0 2006.257.21:51:35.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:35.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:35.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.21:51:35.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.21:51:35.58$vck44/va=1,8 2006.257.21:51:35.58#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.21:51:35.58#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.21:51:35.58#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:35.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:35.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:35.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:35.58#ibcon#enter wrdev, iclass 29, count 2 2006.257.21:51:35.58#ibcon#first serial, iclass 29, count 2 2006.257.21:51:35.58#ibcon#enter sib2, iclass 29, count 2 2006.257.21:51:35.58#ibcon#flushed, iclass 29, count 2 2006.257.21:51:35.58#ibcon#about to write, iclass 29, count 2 2006.257.21:51:35.58#ibcon#wrote, iclass 29, count 2 2006.257.21:51:35.58#ibcon#about to read 3, iclass 29, count 2 2006.257.21:51:35.60#ibcon#read 3, iclass 29, count 2 2006.257.21:51:35.60#ibcon#about to read 4, iclass 29, count 2 2006.257.21:51:35.60#ibcon#read 4, iclass 29, count 2 2006.257.21:51:35.60#ibcon#about to read 5, iclass 29, count 2 2006.257.21:51:35.60#ibcon#read 5, iclass 29, count 2 2006.257.21:51:35.60#ibcon#about to read 6, iclass 29, count 2 2006.257.21:51:35.60#ibcon#read 6, iclass 29, count 2 2006.257.21:51:35.60#ibcon#end of sib2, iclass 29, count 2 2006.257.21:51:35.60#ibcon#*mode == 0, iclass 29, count 2 2006.257.21:51:35.60#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.21:51:35.60#ibcon#[25=AT01-08\r\n] 2006.257.21:51:35.60#ibcon#*before write, iclass 29, count 2 2006.257.21:51:35.60#ibcon#enter sib2, iclass 29, count 2 2006.257.21:51:35.60#ibcon#flushed, iclass 29, count 2 2006.257.21:51:35.60#ibcon#about to write, iclass 29, count 2 2006.257.21:51:35.60#ibcon#wrote, iclass 29, count 2 2006.257.21:51:35.60#ibcon#about to read 3, iclass 29, count 2 2006.257.21:51:35.63#ibcon#read 3, iclass 29, count 2 2006.257.21:51:35.63#ibcon#about to read 4, iclass 29, count 2 2006.257.21:51:35.63#ibcon#read 4, iclass 29, count 2 2006.257.21:51:35.63#ibcon#about to read 5, iclass 29, count 2 2006.257.21:51:35.63#ibcon#read 5, iclass 29, count 2 2006.257.21:51:35.63#ibcon#about to read 6, iclass 29, count 2 2006.257.21:51:35.63#ibcon#read 6, iclass 29, count 2 2006.257.21:51:35.63#ibcon#end of sib2, iclass 29, count 2 2006.257.21:51:35.63#ibcon#*after write, iclass 29, count 2 2006.257.21:51:35.63#ibcon#*before return 0, iclass 29, count 2 2006.257.21:51:35.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:35.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:35.63#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.21:51:35.63#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:35.63#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:35.75#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:35.75#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:35.75#ibcon#enter wrdev, iclass 29, count 0 2006.257.21:51:35.75#ibcon#first serial, iclass 29, count 0 2006.257.21:51:35.75#ibcon#enter sib2, iclass 29, count 0 2006.257.21:51:35.75#ibcon#flushed, iclass 29, count 0 2006.257.21:51:35.75#ibcon#about to write, iclass 29, count 0 2006.257.21:51:35.75#ibcon#wrote, iclass 29, count 0 2006.257.21:51:35.75#ibcon#about to read 3, iclass 29, count 0 2006.257.21:51:35.77#ibcon#read 3, iclass 29, count 0 2006.257.21:51:35.77#ibcon#about to read 4, iclass 29, count 0 2006.257.21:51:35.77#ibcon#read 4, iclass 29, count 0 2006.257.21:51:35.77#ibcon#about to read 5, iclass 29, count 0 2006.257.21:51:35.77#ibcon#read 5, iclass 29, count 0 2006.257.21:51:35.77#ibcon#about to read 6, iclass 29, count 0 2006.257.21:51:35.77#ibcon#read 6, iclass 29, count 0 2006.257.21:51:35.77#ibcon#end of sib2, iclass 29, count 0 2006.257.21:51:35.77#ibcon#*mode == 0, iclass 29, count 0 2006.257.21:51:35.77#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.21:51:35.77#ibcon#[25=USB\r\n] 2006.257.21:51:35.77#ibcon#*before write, iclass 29, count 0 2006.257.21:51:35.77#ibcon#enter sib2, iclass 29, count 0 2006.257.21:51:35.77#ibcon#flushed, iclass 29, count 0 2006.257.21:51:35.77#ibcon#about to write, iclass 29, count 0 2006.257.21:51:35.77#ibcon#wrote, iclass 29, count 0 2006.257.21:51:35.77#ibcon#about to read 3, iclass 29, count 0 2006.257.21:51:35.80#ibcon#read 3, iclass 29, count 0 2006.257.21:51:35.80#ibcon#about to read 4, iclass 29, count 0 2006.257.21:51:35.80#ibcon#read 4, iclass 29, count 0 2006.257.21:51:35.80#ibcon#about to read 5, iclass 29, count 0 2006.257.21:51:35.80#ibcon#read 5, iclass 29, count 0 2006.257.21:51:35.80#ibcon#about to read 6, iclass 29, count 0 2006.257.21:51:35.80#ibcon#read 6, iclass 29, count 0 2006.257.21:51:35.80#ibcon#end of sib2, iclass 29, count 0 2006.257.21:51:35.80#ibcon#*after write, iclass 29, count 0 2006.257.21:51:35.80#ibcon#*before return 0, iclass 29, count 0 2006.257.21:51:35.80#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:35.80#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:35.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.21:51:35.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.21:51:35.80$vck44/valo=2,534.99 2006.257.21:51:35.80#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.21:51:35.80#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.21:51:35.80#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:35.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:35.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:35.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:35.80#ibcon#enter wrdev, iclass 31, count 0 2006.257.21:51:35.80#ibcon#first serial, iclass 31, count 0 2006.257.21:51:35.80#ibcon#enter sib2, iclass 31, count 0 2006.257.21:51:35.80#ibcon#flushed, iclass 31, count 0 2006.257.21:51:35.80#ibcon#about to write, iclass 31, count 0 2006.257.21:51:35.80#ibcon#wrote, iclass 31, count 0 2006.257.21:51:35.80#ibcon#about to read 3, iclass 31, count 0 2006.257.21:51:35.82#ibcon#read 3, iclass 31, count 0 2006.257.21:51:35.82#ibcon#about to read 4, iclass 31, count 0 2006.257.21:51:35.82#ibcon#read 4, iclass 31, count 0 2006.257.21:51:35.82#ibcon#about to read 5, iclass 31, count 0 2006.257.21:51:35.82#ibcon#read 5, iclass 31, count 0 2006.257.21:51:35.82#ibcon#about to read 6, iclass 31, count 0 2006.257.21:51:35.82#ibcon#read 6, iclass 31, count 0 2006.257.21:51:35.82#ibcon#end of sib2, iclass 31, count 0 2006.257.21:51:35.82#ibcon#*mode == 0, iclass 31, count 0 2006.257.21:51:35.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.21:51:35.82#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.21:51:35.82#ibcon#*before write, iclass 31, count 0 2006.257.21:51:35.82#ibcon#enter sib2, iclass 31, count 0 2006.257.21:51:35.82#ibcon#flushed, iclass 31, count 0 2006.257.21:51:35.82#ibcon#about to write, iclass 31, count 0 2006.257.21:51:35.82#ibcon#wrote, iclass 31, count 0 2006.257.21:51:35.82#ibcon#about to read 3, iclass 31, count 0 2006.257.21:51:35.86#ibcon#read 3, iclass 31, count 0 2006.257.21:51:35.86#ibcon#about to read 4, iclass 31, count 0 2006.257.21:51:35.86#ibcon#read 4, iclass 31, count 0 2006.257.21:51:35.86#ibcon#about to read 5, iclass 31, count 0 2006.257.21:51:35.86#ibcon#read 5, iclass 31, count 0 2006.257.21:51:35.86#ibcon#about to read 6, iclass 31, count 0 2006.257.21:51:35.86#ibcon#read 6, iclass 31, count 0 2006.257.21:51:35.86#ibcon#end of sib2, iclass 31, count 0 2006.257.21:51:35.86#ibcon#*after write, iclass 31, count 0 2006.257.21:51:35.86#ibcon#*before return 0, iclass 31, count 0 2006.257.21:51:35.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:35.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:35.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.21:51:35.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.21:51:35.86$vck44/va=2,7 2006.257.21:51:35.86#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.21:51:35.86#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.21:51:35.86#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:35.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:35.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:35.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:35.92#ibcon#enter wrdev, iclass 33, count 2 2006.257.21:51:35.92#ibcon#first serial, iclass 33, count 2 2006.257.21:51:35.92#ibcon#enter sib2, iclass 33, count 2 2006.257.21:51:35.92#ibcon#flushed, iclass 33, count 2 2006.257.21:51:35.92#ibcon#about to write, iclass 33, count 2 2006.257.21:51:35.92#ibcon#wrote, iclass 33, count 2 2006.257.21:51:35.92#ibcon#about to read 3, iclass 33, count 2 2006.257.21:51:35.94#ibcon#read 3, iclass 33, count 2 2006.257.21:51:35.94#ibcon#about to read 4, iclass 33, count 2 2006.257.21:51:35.94#ibcon#read 4, iclass 33, count 2 2006.257.21:51:35.94#ibcon#about to read 5, iclass 33, count 2 2006.257.21:51:35.94#ibcon#read 5, iclass 33, count 2 2006.257.21:51:35.94#ibcon#about to read 6, iclass 33, count 2 2006.257.21:51:35.94#ibcon#read 6, iclass 33, count 2 2006.257.21:51:35.94#ibcon#end of sib2, iclass 33, count 2 2006.257.21:51:35.94#ibcon#*mode == 0, iclass 33, count 2 2006.257.21:51:35.94#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.21:51:35.94#ibcon#[25=AT02-07\r\n] 2006.257.21:51:35.94#ibcon#*before write, iclass 33, count 2 2006.257.21:51:35.94#ibcon#enter sib2, iclass 33, count 2 2006.257.21:51:35.94#ibcon#flushed, iclass 33, count 2 2006.257.21:51:35.94#ibcon#about to write, iclass 33, count 2 2006.257.21:51:35.94#ibcon#wrote, iclass 33, count 2 2006.257.21:51:35.94#ibcon#about to read 3, iclass 33, count 2 2006.257.21:51:35.97#ibcon#read 3, iclass 33, count 2 2006.257.21:51:35.97#ibcon#about to read 4, iclass 33, count 2 2006.257.21:51:35.97#ibcon#read 4, iclass 33, count 2 2006.257.21:51:35.97#ibcon#about to read 5, iclass 33, count 2 2006.257.21:51:35.97#ibcon#read 5, iclass 33, count 2 2006.257.21:51:35.97#ibcon#about to read 6, iclass 33, count 2 2006.257.21:51:35.97#ibcon#read 6, iclass 33, count 2 2006.257.21:51:35.97#ibcon#end of sib2, iclass 33, count 2 2006.257.21:51:35.97#ibcon#*after write, iclass 33, count 2 2006.257.21:51:35.97#ibcon#*before return 0, iclass 33, count 2 2006.257.21:51:35.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:35.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:35.97#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.21:51:35.97#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:35.97#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:36.09#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:36.09#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:36.09#ibcon#enter wrdev, iclass 33, count 0 2006.257.21:51:36.09#ibcon#first serial, iclass 33, count 0 2006.257.21:51:36.09#ibcon#enter sib2, iclass 33, count 0 2006.257.21:51:36.09#ibcon#flushed, iclass 33, count 0 2006.257.21:51:36.09#ibcon#about to write, iclass 33, count 0 2006.257.21:51:36.09#ibcon#wrote, iclass 33, count 0 2006.257.21:51:36.09#ibcon#about to read 3, iclass 33, count 0 2006.257.21:51:36.11#ibcon#read 3, iclass 33, count 0 2006.257.21:51:36.11#ibcon#about to read 4, iclass 33, count 0 2006.257.21:51:36.11#ibcon#read 4, iclass 33, count 0 2006.257.21:51:36.11#ibcon#about to read 5, iclass 33, count 0 2006.257.21:51:36.11#ibcon#read 5, iclass 33, count 0 2006.257.21:51:36.11#ibcon#about to read 6, iclass 33, count 0 2006.257.21:51:36.11#ibcon#read 6, iclass 33, count 0 2006.257.21:51:36.11#ibcon#end of sib2, iclass 33, count 0 2006.257.21:51:36.11#ibcon#*mode == 0, iclass 33, count 0 2006.257.21:51:36.11#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.21:51:36.11#ibcon#[25=USB\r\n] 2006.257.21:51:36.11#ibcon#*before write, iclass 33, count 0 2006.257.21:51:36.11#ibcon#enter sib2, iclass 33, count 0 2006.257.21:51:36.11#ibcon#flushed, iclass 33, count 0 2006.257.21:51:36.11#ibcon#about to write, iclass 33, count 0 2006.257.21:51:36.11#ibcon#wrote, iclass 33, count 0 2006.257.21:51:36.11#ibcon#about to read 3, iclass 33, count 0 2006.257.21:51:36.14#ibcon#read 3, iclass 33, count 0 2006.257.21:51:36.14#ibcon#about to read 4, iclass 33, count 0 2006.257.21:51:36.14#ibcon#read 4, iclass 33, count 0 2006.257.21:51:36.14#ibcon#about to read 5, iclass 33, count 0 2006.257.21:51:36.14#ibcon#read 5, iclass 33, count 0 2006.257.21:51:36.14#ibcon#about to read 6, iclass 33, count 0 2006.257.21:51:36.14#ibcon#read 6, iclass 33, count 0 2006.257.21:51:36.14#ibcon#end of sib2, iclass 33, count 0 2006.257.21:51:36.14#ibcon#*after write, iclass 33, count 0 2006.257.21:51:36.14#ibcon#*before return 0, iclass 33, count 0 2006.257.21:51:36.14#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:36.14#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:36.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.21:51:36.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.21:51:36.14$vck44/valo=3,564.99 2006.257.21:51:36.14#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.21:51:36.14#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.21:51:36.14#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:36.14#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:36.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:36.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:36.14#ibcon#enter wrdev, iclass 35, count 0 2006.257.21:51:36.14#ibcon#first serial, iclass 35, count 0 2006.257.21:51:36.14#ibcon#enter sib2, iclass 35, count 0 2006.257.21:51:36.14#ibcon#flushed, iclass 35, count 0 2006.257.21:51:36.14#ibcon#about to write, iclass 35, count 0 2006.257.21:51:36.14#ibcon#wrote, iclass 35, count 0 2006.257.21:51:36.14#ibcon#about to read 3, iclass 35, count 0 2006.257.21:51:36.16#ibcon#read 3, iclass 35, count 0 2006.257.21:51:36.16#ibcon#about to read 4, iclass 35, count 0 2006.257.21:51:36.16#ibcon#read 4, iclass 35, count 0 2006.257.21:51:36.16#ibcon#about to read 5, iclass 35, count 0 2006.257.21:51:36.16#ibcon#read 5, iclass 35, count 0 2006.257.21:51:36.16#ibcon#about to read 6, iclass 35, count 0 2006.257.21:51:36.16#ibcon#read 6, iclass 35, count 0 2006.257.21:51:36.16#ibcon#end of sib2, iclass 35, count 0 2006.257.21:51:36.16#ibcon#*mode == 0, iclass 35, count 0 2006.257.21:51:36.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.21:51:36.16#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.21:51:36.16#ibcon#*before write, iclass 35, count 0 2006.257.21:51:36.16#ibcon#enter sib2, iclass 35, count 0 2006.257.21:51:36.16#ibcon#flushed, iclass 35, count 0 2006.257.21:51:36.16#ibcon#about to write, iclass 35, count 0 2006.257.21:51:36.16#ibcon#wrote, iclass 35, count 0 2006.257.21:51:36.16#ibcon#about to read 3, iclass 35, count 0 2006.257.21:51:36.20#ibcon#read 3, iclass 35, count 0 2006.257.21:51:36.20#ibcon#about to read 4, iclass 35, count 0 2006.257.21:51:36.20#ibcon#read 4, iclass 35, count 0 2006.257.21:51:36.20#ibcon#about to read 5, iclass 35, count 0 2006.257.21:51:36.20#ibcon#read 5, iclass 35, count 0 2006.257.21:51:36.20#ibcon#about to read 6, iclass 35, count 0 2006.257.21:51:36.20#ibcon#read 6, iclass 35, count 0 2006.257.21:51:36.20#ibcon#end of sib2, iclass 35, count 0 2006.257.21:51:36.20#ibcon#*after write, iclass 35, count 0 2006.257.21:51:36.20#ibcon#*before return 0, iclass 35, count 0 2006.257.21:51:36.20#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:36.20#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:36.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.21:51:36.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.21:51:36.20$vck44/va=3,8 2006.257.21:51:36.20#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.21:51:36.20#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.21:51:36.20#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:36.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:36.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:36.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:36.26#ibcon#enter wrdev, iclass 37, count 2 2006.257.21:51:36.26#ibcon#first serial, iclass 37, count 2 2006.257.21:51:36.26#ibcon#enter sib2, iclass 37, count 2 2006.257.21:51:36.26#ibcon#flushed, iclass 37, count 2 2006.257.21:51:36.26#ibcon#about to write, iclass 37, count 2 2006.257.21:51:36.26#ibcon#wrote, iclass 37, count 2 2006.257.21:51:36.26#ibcon#about to read 3, iclass 37, count 2 2006.257.21:51:36.28#ibcon#read 3, iclass 37, count 2 2006.257.21:51:36.28#ibcon#about to read 4, iclass 37, count 2 2006.257.21:51:36.28#ibcon#read 4, iclass 37, count 2 2006.257.21:51:36.28#ibcon#about to read 5, iclass 37, count 2 2006.257.21:51:36.28#ibcon#read 5, iclass 37, count 2 2006.257.21:51:36.28#ibcon#about to read 6, iclass 37, count 2 2006.257.21:51:36.28#ibcon#read 6, iclass 37, count 2 2006.257.21:51:36.28#ibcon#end of sib2, iclass 37, count 2 2006.257.21:51:36.28#ibcon#*mode == 0, iclass 37, count 2 2006.257.21:51:36.28#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.21:51:36.28#ibcon#[25=AT03-08\r\n] 2006.257.21:51:36.28#ibcon#*before write, iclass 37, count 2 2006.257.21:51:36.28#ibcon#enter sib2, iclass 37, count 2 2006.257.21:51:36.28#ibcon#flushed, iclass 37, count 2 2006.257.21:51:36.28#ibcon#about to write, iclass 37, count 2 2006.257.21:51:36.28#ibcon#wrote, iclass 37, count 2 2006.257.21:51:36.28#ibcon#about to read 3, iclass 37, count 2 2006.257.21:51:36.31#ibcon#read 3, iclass 37, count 2 2006.257.21:51:36.31#ibcon#about to read 4, iclass 37, count 2 2006.257.21:51:36.31#ibcon#read 4, iclass 37, count 2 2006.257.21:51:36.31#ibcon#about to read 5, iclass 37, count 2 2006.257.21:51:36.31#ibcon#read 5, iclass 37, count 2 2006.257.21:51:36.31#ibcon#about to read 6, iclass 37, count 2 2006.257.21:51:36.31#ibcon#read 6, iclass 37, count 2 2006.257.21:51:36.31#ibcon#end of sib2, iclass 37, count 2 2006.257.21:51:36.31#ibcon#*after write, iclass 37, count 2 2006.257.21:51:36.31#ibcon#*before return 0, iclass 37, count 2 2006.257.21:51:36.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:36.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:36.31#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.21:51:36.31#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:36.31#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:36.43#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:36.43#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:36.43#ibcon#enter wrdev, iclass 37, count 0 2006.257.21:51:36.43#ibcon#first serial, iclass 37, count 0 2006.257.21:51:36.43#ibcon#enter sib2, iclass 37, count 0 2006.257.21:51:36.43#ibcon#flushed, iclass 37, count 0 2006.257.21:51:36.43#ibcon#about to write, iclass 37, count 0 2006.257.21:51:36.43#ibcon#wrote, iclass 37, count 0 2006.257.21:51:36.43#ibcon#about to read 3, iclass 37, count 0 2006.257.21:51:36.45#ibcon#read 3, iclass 37, count 0 2006.257.21:51:36.45#ibcon#about to read 4, iclass 37, count 0 2006.257.21:51:36.45#ibcon#read 4, iclass 37, count 0 2006.257.21:51:36.45#ibcon#about to read 5, iclass 37, count 0 2006.257.21:51:36.45#ibcon#read 5, iclass 37, count 0 2006.257.21:51:36.45#ibcon#about to read 6, iclass 37, count 0 2006.257.21:51:36.45#ibcon#read 6, iclass 37, count 0 2006.257.21:51:36.45#ibcon#end of sib2, iclass 37, count 0 2006.257.21:51:36.45#ibcon#*mode == 0, iclass 37, count 0 2006.257.21:51:36.45#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.21:51:36.45#ibcon#[25=USB\r\n] 2006.257.21:51:36.45#ibcon#*before write, iclass 37, count 0 2006.257.21:51:36.45#ibcon#enter sib2, iclass 37, count 0 2006.257.21:51:36.45#ibcon#flushed, iclass 37, count 0 2006.257.21:51:36.45#ibcon#about to write, iclass 37, count 0 2006.257.21:51:36.45#ibcon#wrote, iclass 37, count 0 2006.257.21:51:36.45#ibcon#about to read 3, iclass 37, count 0 2006.257.21:51:36.48#ibcon#read 3, iclass 37, count 0 2006.257.21:51:36.48#ibcon#about to read 4, iclass 37, count 0 2006.257.21:51:36.48#ibcon#read 4, iclass 37, count 0 2006.257.21:51:36.48#ibcon#about to read 5, iclass 37, count 0 2006.257.21:51:36.48#ibcon#read 5, iclass 37, count 0 2006.257.21:51:36.48#ibcon#about to read 6, iclass 37, count 0 2006.257.21:51:36.48#ibcon#read 6, iclass 37, count 0 2006.257.21:51:36.48#ibcon#end of sib2, iclass 37, count 0 2006.257.21:51:36.48#ibcon#*after write, iclass 37, count 0 2006.257.21:51:36.48#ibcon#*before return 0, iclass 37, count 0 2006.257.21:51:36.48#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:36.48#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:36.48#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.21:51:36.48#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.21:51:36.48$vck44/valo=4,624.99 2006.257.21:51:36.48#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.21:51:36.48#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.21:51:36.48#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:36.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:36.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:36.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:36.48#ibcon#enter wrdev, iclass 39, count 0 2006.257.21:51:36.48#ibcon#first serial, iclass 39, count 0 2006.257.21:51:36.48#ibcon#enter sib2, iclass 39, count 0 2006.257.21:51:36.48#ibcon#flushed, iclass 39, count 0 2006.257.21:51:36.48#ibcon#about to write, iclass 39, count 0 2006.257.21:51:36.48#ibcon#wrote, iclass 39, count 0 2006.257.21:51:36.48#ibcon#about to read 3, iclass 39, count 0 2006.257.21:51:36.50#ibcon#read 3, iclass 39, count 0 2006.257.21:51:36.50#ibcon#about to read 4, iclass 39, count 0 2006.257.21:51:36.50#ibcon#read 4, iclass 39, count 0 2006.257.21:51:36.50#ibcon#about to read 5, iclass 39, count 0 2006.257.21:51:36.50#ibcon#read 5, iclass 39, count 0 2006.257.21:51:36.50#ibcon#about to read 6, iclass 39, count 0 2006.257.21:51:36.50#ibcon#read 6, iclass 39, count 0 2006.257.21:51:36.50#ibcon#end of sib2, iclass 39, count 0 2006.257.21:51:36.50#ibcon#*mode == 0, iclass 39, count 0 2006.257.21:51:36.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.21:51:36.50#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.21:51:36.50#ibcon#*before write, iclass 39, count 0 2006.257.21:51:36.50#ibcon#enter sib2, iclass 39, count 0 2006.257.21:51:36.50#ibcon#flushed, iclass 39, count 0 2006.257.21:51:36.50#ibcon#about to write, iclass 39, count 0 2006.257.21:51:36.50#ibcon#wrote, iclass 39, count 0 2006.257.21:51:36.50#ibcon#about to read 3, iclass 39, count 0 2006.257.21:51:36.54#ibcon#read 3, iclass 39, count 0 2006.257.21:51:36.54#ibcon#about to read 4, iclass 39, count 0 2006.257.21:51:36.54#ibcon#read 4, iclass 39, count 0 2006.257.21:51:36.54#ibcon#about to read 5, iclass 39, count 0 2006.257.21:51:36.54#ibcon#read 5, iclass 39, count 0 2006.257.21:51:36.54#ibcon#about to read 6, iclass 39, count 0 2006.257.21:51:36.54#ibcon#read 6, iclass 39, count 0 2006.257.21:51:36.54#ibcon#end of sib2, iclass 39, count 0 2006.257.21:51:36.54#ibcon#*after write, iclass 39, count 0 2006.257.21:51:36.54#ibcon#*before return 0, iclass 39, count 0 2006.257.21:51:36.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:36.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:36.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.21:51:36.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.21:51:36.54$vck44/va=4,7 2006.257.21:51:36.54#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.21:51:36.54#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.21:51:36.54#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:36.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:36.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:36.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:36.60#ibcon#enter wrdev, iclass 3, count 2 2006.257.21:51:36.60#ibcon#first serial, iclass 3, count 2 2006.257.21:51:36.60#ibcon#enter sib2, iclass 3, count 2 2006.257.21:51:36.60#ibcon#flushed, iclass 3, count 2 2006.257.21:51:36.60#ibcon#about to write, iclass 3, count 2 2006.257.21:51:36.60#ibcon#wrote, iclass 3, count 2 2006.257.21:51:36.60#ibcon#about to read 3, iclass 3, count 2 2006.257.21:51:36.62#ibcon#read 3, iclass 3, count 2 2006.257.21:51:36.62#ibcon#about to read 4, iclass 3, count 2 2006.257.21:51:36.62#ibcon#read 4, iclass 3, count 2 2006.257.21:51:36.62#ibcon#about to read 5, iclass 3, count 2 2006.257.21:51:36.62#ibcon#read 5, iclass 3, count 2 2006.257.21:51:36.62#ibcon#about to read 6, iclass 3, count 2 2006.257.21:51:36.62#ibcon#read 6, iclass 3, count 2 2006.257.21:51:36.62#ibcon#end of sib2, iclass 3, count 2 2006.257.21:51:36.62#ibcon#*mode == 0, iclass 3, count 2 2006.257.21:51:36.62#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.21:51:36.62#ibcon#[25=AT04-07\r\n] 2006.257.21:51:36.62#ibcon#*before write, iclass 3, count 2 2006.257.21:51:36.62#ibcon#enter sib2, iclass 3, count 2 2006.257.21:51:36.62#ibcon#flushed, iclass 3, count 2 2006.257.21:51:36.62#ibcon#about to write, iclass 3, count 2 2006.257.21:51:36.62#ibcon#wrote, iclass 3, count 2 2006.257.21:51:36.62#ibcon#about to read 3, iclass 3, count 2 2006.257.21:51:36.65#ibcon#read 3, iclass 3, count 2 2006.257.21:51:36.65#ibcon#about to read 4, iclass 3, count 2 2006.257.21:51:36.65#ibcon#read 4, iclass 3, count 2 2006.257.21:51:36.65#ibcon#about to read 5, iclass 3, count 2 2006.257.21:51:36.65#ibcon#read 5, iclass 3, count 2 2006.257.21:51:36.65#ibcon#about to read 6, iclass 3, count 2 2006.257.21:51:36.65#ibcon#read 6, iclass 3, count 2 2006.257.21:51:36.65#ibcon#end of sib2, iclass 3, count 2 2006.257.21:51:36.65#ibcon#*after write, iclass 3, count 2 2006.257.21:51:36.65#ibcon#*before return 0, iclass 3, count 2 2006.257.21:51:36.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:36.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:36.65#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.21:51:36.65#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:36.65#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:36.77#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:36.77#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:36.77#ibcon#enter wrdev, iclass 3, count 0 2006.257.21:51:36.77#ibcon#first serial, iclass 3, count 0 2006.257.21:51:36.77#ibcon#enter sib2, iclass 3, count 0 2006.257.21:51:36.77#ibcon#flushed, iclass 3, count 0 2006.257.21:51:36.77#ibcon#about to write, iclass 3, count 0 2006.257.21:51:36.77#ibcon#wrote, iclass 3, count 0 2006.257.21:51:36.77#ibcon#about to read 3, iclass 3, count 0 2006.257.21:51:36.79#ibcon#read 3, iclass 3, count 0 2006.257.21:51:36.79#ibcon#about to read 4, iclass 3, count 0 2006.257.21:51:36.79#ibcon#read 4, iclass 3, count 0 2006.257.21:51:36.79#ibcon#about to read 5, iclass 3, count 0 2006.257.21:51:36.79#ibcon#read 5, iclass 3, count 0 2006.257.21:51:36.79#ibcon#about to read 6, iclass 3, count 0 2006.257.21:51:36.79#ibcon#read 6, iclass 3, count 0 2006.257.21:51:36.79#ibcon#end of sib2, iclass 3, count 0 2006.257.21:51:36.79#ibcon#*mode == 0, iclass 3, count 0 2006.257.21:51:36.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.21:51:36.79#ibcon#[25=USB\r\n] 2006.257.21:51:36.79#ibcon#*before write, iclass 3, count 0 2006.257.21:51:36.79#ibcon#enter sib2, iclass 3, count 0 2006.257.21:51:36.79#ibcon#flushed, iclass 3, count 0 2006.257.21:51:36.79#ibcon#about to write, iclass 3, count 0 2006.257.21:51:36.79#ibcon#wrote, iclass 3, count 0 2006.257.21:51:36.79#ibcon#about to read 3, iclass 3, count 0 2006.257.21:51:36.82#ibcon#read 3, iclass 3, count 0 2006.257.21:51:36.82#ibcon#about to read 4, iclass 3, count 0 2006.257.21:51:36.82#ibcon#read 4, iclass 3, count 0 2006.257.21:51:36.82#ibcon#about to read 5, iclass 3, count 0 2006.257.21:51:36.82#ibcon#read 5, iclass 3, count 0 2006.257.21:51:36.82#ibcon#about to read 6, iclass 3, count 0 2006.257.21:51:36.82#ibcon#read 6, iclass 3, count 0 2006.257.21:51:36.82#ibcon#end of sib2, iclass 3, count 0 2006.257.21:51:36.82#ibcon#*after write, iclass 3, count 0 2006.257.21:51:36.82#ibcon#*before return 0, iclass 3, count 0 2006.257.21:51:36.82#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:36.82#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:36.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.21:51:36.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.21:51:36.82$vck44/valo=5,734.99 2006.257.21:51:36.82#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.21:51:36.82#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.21:51:36.82#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:36.82#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:36.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:36.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:36.82#ibcon#enter wrdev, iclass 5, count 0 2006.257.21:51:36.82#ibcon#first serial, iclass 5, count 0 2006.257.21:51:36.82#ibcon#enter sib2, iclass 5, count 0 2006.257.21:51:36.82#ibcon#flushed, iclass 5, count 0 2006.257.21:51:36.82#ibcon#about to write, iclass 5, count 0 2006.257.21:51:36.82#ibcon#wrote, iclass 5, count 0 2006.257.21:51:36.82#ibcon#about to read 3, iclass 5, count 0 2006.257.21:51:36.84#ibcon#read 3, iclass 5, count 0 2006.257.21:51:36.84#ibcon#about to read 4, iclass 5, count 0 2006.257.21:51:36.84#ibcon#read 4, iclass 5, count 0 2006.257.21:51:36.84#ibcon#about to read 5, iclass 5, count 0 2006.257.21:51:36.84#ibcon#read 5, iclass 5, count 0 2006.257.21:51:36.84#ibcon#about to read 6, iclass 5, count 0 2006.257.21:51:36.84#ibcon#read 6, iclass 5, count 0 2006.257.21:51:36.84#ibcon#end of sib2, iclass 5, count 0 2006.257.21:51:36.84#ibcon#*mode == 0, iclass 5, count 0 2006.257.21:51:36.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.21:51:36.84#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.21:51:36.84#ibcon#*before write, iclass 5, count 0 2006.257.21:51:36.84#ibcon#enter sib2, iclass 5, count 0 2006.257.21:51:36.84#ibcon#flushed, iclass 5, count 0 2006.257.21:51:36.84#ibcon#about to write, iclass 5, count 0 2006.257.21:51:36.84#ibcon#wrote, iclass 5, count 0 2006.257.21:51:36.84#ibcon#about to read 3, iclass 5, count 0 2006.257.21:51:36.88#ibcon#read 3, iclass 5, count 0 2006.257.21:51:36.88#ibcon#about to read 4, iclass 5, count 0 2006.257.21:51:36.88#ibcon#read 4, iclass 5, count 0 2006.257.21:51:36.88#ibcon#about to read 5, iclass 5, count 0 2006.257.21:51:36.88#ibcon#read 5, iclass 5, count 0 2006.257.21:51:36.88#ibcon#about to read 6, iclass 5, count 0 2006.257.21:51:36.88#ibcon#read 6, iclass 5, count 0 2006.257.21:51:36.88#ibcon#end of sib2, iclass 5, count 0 2006.257.21:51:36.88#ibcon#*after write, iclass 5, count 0 2006.257.21:51:36.88#ibcon#*before return 0, iclass 5, count 0 2006.257.21:51:36.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:36.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:36.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.21:51:36.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.21:51:36.88$vck44/va=5,4 2006.257.21:51:36.88#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.21:51:36.88#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.21:51:36.88#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:36.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:36.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:36.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:36.94#ibcon#enter wrdev, iclass 7, count 2 2006.257.21:51:36.94#ibcon#first serial, iclass 7, count 2 2006.257.21:51:36.94#ibcon#enter sib2, iclass 7, count 2 2006.257.21:51:36.94#ibcon#flushed, iclass 7, count 2 2006.257.21:51:36.94#ibcon#about to write, iclass 7, count 2 2006.257.21:51:36.94#ibcon#wrote, iclass 7, count 2 2006.257.21:51:36.94#ibcon#about to read 3, iclass 7, count 2 2006.257.21:51:36.96#ibcon#read 3, iclass 7, count 2 2006.257.21:51:36.96#ibcon#about to read 4, iclass 7, count 2 2006.257.21:51:36.96#ibcon#read 4, iclass 7, count 2 2006.257.21:51:36.96#ibcon#about to read 5, iclass 7, count 2 2006.257.21:51:36.96#ibcon#read 5, iclass 7, count 2 2006.257.21:51:36.96#ibcon#about to read 6, iclass 7, count 2 2006.257.21:51:36.96#ibcon#read 6, iclass 7, count 2 2006.257.21:51:36.96#ibcon#end of sib2, iclass 7, count 2 2006.257.21:51:36.96#ibcon#*mode == 0, iclass 7, count 2 2006.257.21:51:36.96#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.21:51:36.96#ibcon#[25=AT05-04\r\n] 2006.257.21:51:36.96#ibcon#*before write, iclass 7, count 2 2006.257.21:51:36.96#ibcon#enter sib2, iclass 7, count 2 2006.257.21:51:36.96#ibcon#flushed, iclass 7, count 2 2006.257.21:51:36.96#ibcon#about to write, iclass 7, count 2 2006.257.21:51:36.96#ibcon#wrote, iclass 7, count 2 2006.257.21:51:36.96#ibcon#about to read 3, iclass 7, count 2 2006.257.21:51:36.99#ibcon#read 3, iclass 7, count 2 2006.257.21:51:36.99#ibcon#about to read 4, iclass 7, count 2 2006.257.21:51:36.99#ibcon#read 4, iclass 7, count 2 2006.257.21:51:36.99#ibcon#about to read 5, iclass 7, count 2 2006.257.21:51:36.99#ibcon#read 5, iclass 7, count 2 2006.257.21:51:36.99#ibcon#about to read 6, iclass 7, count 2 2006.257.21:51:36.99#ibcon#read 6, iclass 7, count 2 2006.257.21:51:36.99#ibcon#end of sib2, iclass 7, count 2 2006.257.21:51:36.99#ibcon#*after write, iclass 7, count 2 2006.257.21:51:36.99#ibcon#*before return 0, iclass 7, count 2 2006.257.21:51:36.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:36.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:36.99#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.21:51:36.99#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:36.99#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:37.11#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:37.11#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:37.11#ibcon#enter wrdev, iclass 7, count 0 2006.257.21:51:37.11#ibcon#first serial, iclass 7, count 0 2006.257.21:51:37.11#ibcon#enter sib2, iclass 7, count 0 2006.257.21:51:37.11#ibcon#flushed, iclass 7, count 0 2006.257.21:51:37.11#ibcon#about to write, iclass 7, count 0 2006.257.21:51:37.11#ibcon#wrote, iclass 7, count 0 2006.257.21:51:37.11#ibcon#about to read 3, iclass 7, count 0 2006.257.21:51:37.13#ibcon#read 3, iclass 7, count 0 2006.257.21:51:37.13#ibcon#about to read 4, iclass 7, count 0 2006.257.21:51:37.13#ibcon#read 4, iclass 7, count 0 2006.257.21:51:37.13#ibcon#about to read 5, iclass 7, count 0 2006.257.21:51:37.13#ibcon#read 5, iclass 7, count 0 2006.257.21:51:37.13#ibcon#about to read 6, iclass 7, count 0 2006.257.21:51:37.13#ibcon#read 6, iclass 7, count 0 2006.257.21:51:37.13#ibcon#end of sib2, iclass 7, count 0 2006.257.21:51:37.13#ibcon#*mode == 0, iclass 7, count 0 2006.257.21:51:37.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.21:51:37.13#ibcon#[25=USB\r\n] 2006.257.21:51:37.13#ibcon#*before write, iclass 7, count 0 2006.257.21:51:37.13#ibcon#enter sib2, iclass 7, count 0 2006.257.21:51:37.13#ibcon#flushed, iclass 7, count 0 2006.257.21:51:37.13#ibcon#about to write, iclass 7, count 0 2006.257.21:51:37.13#ibcon#wrote, iclass 7, count 0 2006.257.21:51:37.13#ibcon#about to read 3, iclass 7, count 0 2006.257.21:51:37.16#ibcon#read 3, iclass 7, count 0 2006.257.21:51:37.16#ibcon#about to read 4, iclass 7, count 0 2006.257.21:51:37.16#ibcon#read 4, iclass 7, count 0 2006.257.21:51:37.16#ibcon#about to read 5, iclass 7, count 0 2006.257.21:51:37.16#ibcon#read 5, iclass 7, count 0 2006.257.21:51:37.16#ibcon#about to read 6, iclass 7, count 0 2006.257.21:51:37.16#ibcon#read 6, iclass 7, count 0 2006.257.21:51:37.16#ibcon#end of sib2, iclass 7, count 0 2006.257.21:51:37.16#ibcon#*after write, iclass 7, count 0 2006.257.21:51:37.16#ibcon#*before return 0, iclass 7, count 0 2006.257.21:51:37.16#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:37.16#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:37.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.21:51:37.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.21:51:37.16$vck44/valo=6,814.99 2006.257.21:51:37.16#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.21:51:37.16#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.21:51:37.16#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:37.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:51:37.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:51:37.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:51:37.16#ibcon#enter wrdev, iclass 11, count 0 2006.257.21:51:37.16#ibcon#first serial, iclass 11, count 0 2006.257.21:51:37.16#ibcon#enter sib2, iclass 11, count 0 2006.257.21:51:37.16#ibcon#flushed, iclass 11, count 0 2006.257.21:51:37.16#ibcon#about to write, iclass 11, count 0 2006.257.21:51:37.16#ibcon#wrote, iclass 11, count 0 2006.257.21:51:37.16#ibcon#about to read 3, iclass 11, count 0 2006.257.21:51:37.18#ibcon#read 3, iclass 11, count 0 2006.257.21:51:37.18#ibcon#about to read 4, iclass 11, count 0 2006.257.21:51:37.18#ibcon#read 4, iclass 11, count 0 2006.257.21:51:37.18#ibcon#about to read 5, iclass 11, count 0 2006.257.21:51:37.18#ibcon#read 5, iclass 11, count 0 2006.257.21:51:37.18#ibcon#about to read 6, iclass 11, count 0 2006.257.21:51:37.18#ibcon#read 6, iclass 11, count 0 2006.257.21:51:37.18#ibcon#end of sib2, iclass 11, count 0 2006.257.21:51:37.18#ibcon#*mode == 0, iclass 11, count 0 2006.257.21:51:37.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.21:51:37.18#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.21:51:37.18#ibcon#*before write, iclass 11, count 0 2006.257.21:51:37.18#ibcon#enter sib2, iclass 11, count 0 2006.257.21:51:37.18#ibcon#flushed, iclass 11, count 0 2006.257.21:51:37.18#ibcon#about to write, iclass 11, count 0 2006.257.21:51:37.18#ibcon#wrote, iclass 11, count 0 2006.257.21:51:37.18#ibcon#about to read 3, iclass 11, count 0 2006.257.21:51:37.22#ibcon#read 3, iclass 11, count 0 2006.257.21:51:37.22#ibcon#about to read 4, iclass 11, count 0 2006.257.21:51:37.22#ibcon#read 4, iclass 11, count 0 2006.257.21:51:37.22#ibcon#about to read 5, iclass 11, count 0 2006.257.21:51:37.22#ibcon#read 5, iclass 11, count 0 2006.257.21:51:37.22#ibcon#about to read 6, iclass 11, count 0 2006.257.21:51:37.22#ibcon#read 6, iclass 11, count 0 2006.257.21:51:37.22#ibcon#end of sib2, iclass 11, count 0 2006.257.21:51:37.22#ibcon#*after write, iclass 11, count 0 2006.257.21:51:37.22#ibcon#*before return 0, iclass 11, count 0 2006.257.21:51:37.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:51:37.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.21:51:37.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.21:51:37.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.21:51:37.22$vck44/va=6,4 2006.257.21:51:37.22#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.21:51:37.22#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.21:51:37.22#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:37.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:51:37.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:51:37.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:51:37.28#ibcon#enter wrdev, iclass 13, count 2 2006.257.21:51:37.28#ibcon#first serial, iclass 13, count 2 2006.257.21:51:37.28#ibcon#enter sib2, iclass 13, count 2 2006.257.21:51:37.28#ibcon#flushed, iclass 13, count 2 2006.257.21:51:37.28#ibcon#about to write, iclass 13, count 2 2006.257.21:51:37.28#ibcon#wrote, iclass 13, count 2 2006.257.21:51:37.28#ibcon#about to read 3, iclass 13, count 2 2006.257.21:51:37.30#ibcon#read 3, iclass 13, count 2 2006.257.21:51:37.30#ibcon#about to read 4, iclass 13, count 2 2006.257.21:51:37.30#ibcon#read 4, iclass 13, count 2 2006.257.21:51:37.30#ibcon#about to read 5, iclass 13, count 2 2006.257.21:51:37.30#ibcon#read 5, iclass 13, count 2 2006.257.21:51:37.30#ibcon#about to read 6, iclass 13, count 2 2006.257.21:51:37.30#ibcon#read 6, iclass 13, count 2 2006.257.21:51:37.30#ibcon#end of sib2, iclass 13, count 2 2006.257.21:51:37.30#ibcon#*mode == 0, iclass 13, count 2 2006.257.21:51:37.30#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.21:51:37.30#ibcon#[25=AT06-04\r\n] 2006.257.21:51:37.30#ibcon#*before write, iclass 13, count 2 2006.257.21:51:37.30#ibcon#enter sib2, iclass 13, count 2 2006.257.21:51:37.30#ibcon#flushed, iclass 13, count 2 2006.257.21:51:37.30#ibcon#about to write, iclass 13, count 2 2006.257.21:51:37.30#ibcon#wrote, iclass 13, count 2 2006.257.21:51:37.30#ibcon#about to read 3, iclass 13, count 2 2006.257.21:51:37.33#ibcon#read 3, iclass 13, count 2 2006.257.21:51:37.33#ibcon#about to read 4, iclass 13, count 2 2006.257.21:51:37.33#ibcon#read 4, iclass 13, count 2 2006.257.21:51:37.33#ibcon#about to read 5, iclass 13, count 2 2006.257.21:51:37.33#ibcon#read 5, iclass 13, count 2 2006.257.21:51:37.33#ibcon#about to read 6, iclass 13, count 2 2006.257.21:51:37.33#ibcon#read 6, iclass 13, count 2 2006.257.21:51:37.33#ibcon#end of sib2, iclass 13, count 2 2006.257.21:51:37.33#ibcon#*after write, iclass 13, count 2 2006.257.21:51:37.33#ibcon#*before return 0, iclass 13, count 2 2006.257.21:51:37.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:51:37.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.21:51:37.33#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.21:51:37.33#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:37.33#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:51:37.45#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:51:37.45#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:51:37.45#ibcon#enter wrdev, iclass 13, count 0 2006.257.21:51:37.45#ibcon#first serial, iclass 13, count 0 2006.257.21:51:37.45#ibcon#enter sib2, iclass 13, count 0 2006.257.21:51:37.45#ibcon#flushed, iclass 13, count 0 2006.257.21:51:37.45#ibcon#about to write, iclass 13, count 0 2006.257.21:51:37.45#ibcon#wrote, iclass 13, count 0 2006.257.21:51:37.45#ibcon#about to read 3, iclass 13, count 0 2006.257.21:51:37.47#ibcon#read 3, iclass 13, count 0 2006.257.21:51:37.47#ibcon#about to read 4, iclass 13, count 0 2006.257.21:51:37.47#ibcon#read 4, iclass 13, count 0 2006.257.21:51:37.47#ibcon#about to read 5, iclass 13, count 0 2006.257.21:51:37.47#ibcon#read 5, iclass 13, count 0 2006.257.21:51:37.47#ibcon#about to read 6, iclass 13, count 0 2006.257.21:51:37.47#ibcon#read 6, iclass 13, count 0 2006.257.21:51:37.47#ibcon#end of sib2, iclass 13, count 0 2006.257.21:51:37.47#ibcon#*mode == 0, iclass 13, count 0 2006.257.21:51:37.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.21:51:37.47#ibcon#[25=USB\r\n] 2006.257.21:51:37.47#ibcon#*before write, iclass 13, count 0 2006.257.21:51:37.47#ibcon#enter sib2, iclass 13, count 0 2006.257.21:51:37.47#ibcon#flushed, iclass 13, count 0 2006.257.21:51:37.47#ibcon#about to write, iclass 13, count 0 2006.257.21:51:37.47#ibcon#wrote, iclass 13, count 0 2006.257.21:51:37.47#ibcon#about to read 3, iclass 13, count 0 2006.257.21:51:37.50#ibcon#read 3, iclass 13, count 0 2006.257.21:51:37.50#ibcon#about to read 4, iclass 13, count 0 2006.257.21:51:37.50#ibcon#read 4, iclass 13, count 0 2006.257.21:51:37.50#ibcon#about to read 5, iclass 13, count 0 2006.257.21:51:37.50#ibcon#read 5, iclass 13, count 0 2006.257.21:51:37.50#ibcon#about to read 6, iclass 13, count 0 2006.257.21:51:37.50#ibcon#read 6, iclass 13, count 0 2006.257.21:51:37.50#ibcon#end of sib2, iclass 13, count 0 2006.257.21:51:37.50#ibcon#*after write, iclass 13, count 0 2006.257.21:51:37.50#ibcon#*before return 0, iclass 13, count 0 2006.257.21:51:37.50#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:51:37.50#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.21:51:37.50#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.21:51:37.50#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.21:51:37.50$vck44/valo=7,864.99 2006.257.21:51:37.50#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.21:51:37.50#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.21:51:37.50#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:37.50#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:51:37.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:51:37.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:51:37.50#ibcon#enter wrdev, iclass 15, count 0 2006.257.21:51:37.50#ibcon#first serial, iclass 15, count 0 2006.257.21:51:37.50#ibcon#enter sib2, iclass 15, count 0 2006.257.21:51:37.50#ibcon#flushed, iclass 15, count 0 2006.257.21:51:37.50#ibcon#about to write, iclass 15, count 0 2006.257.21:51:37.50#ibcon#wrote, iclass 15, count 0 2006.257.21:51:37.50#ibcon#about to read 3, iclass 15, count 0 2006.257.21:51:37.52#ibcon#read 3, iclass 15, count 0 2006.257.21:51:37.52#ibcon#about to read 4, iclass 15, count 0 2006.257.21:51:37.52#ibcon#read 4, iclass 15, count 0 2006.257.21:51:37.52#ibcon#about to read 5, iclass 15, count 0 2006.257.21:51:37.52#ibcon#read 5, iclass 15, count 0 2006.257.21:51:37.52#ibcon#about to read 6, iclass 15, count 0 2006.257.21:51:37.52#ibcon#read 6, iclass 15, count 0 2006.257.21:51:37.52#ibcon#end of sib2, iclass 15, count 0 2006.257.21:51:37.52#ibcon#*mode == 0, iclass 15, count 0 2006.257.21:51:37.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.21:51:37.52#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.21:51:37.52#ibcon#*before write, iclass 15, count 0 2006.257.21:51:37.52#ibcon#enter sib2, iclass 15, count 0 2006.257.21:51:37.52#ibcon#flushed, iclass 15, count 0 2006.257.21:51:37.52#ibcon#about to write, iclass 15, count 0 2006.257.21:51:37.52#ibcon#wrote, iclass 15, count 0 2006.257.21:51:37.52#ibcon#about to read 3, iclass 15, count 0 2006.257.21:51:37.56#ibcon#read 3, iclass 15, count 0 2006.257.21:51:37.56#ibcon#about to read 4, iclass 15, count 0 2006.257.21:51:37.56#ibcon#read 4, iclass 15, count 0 2006.257.21:51:37.56#ibcon#about to read 5, iclass 15, count 0 2006.257.21:51:37.56#ibcon#read 5, iclass 15, count 0 2006.257.21:51:37.56#ibcon#about to read 6, iclass 15, count 0 2006.257.21:51:37.56#ibcon#read 6, iclass 15, count 0 2006.257.21:51:37.56#ibcon#end of sib2, iclass 15, count 0 2006.257.21:51:37.56#ibcon#*after write, iclass 15, count 0 2006.257.21:51:37.56#ibcon#*before return 0, iclass 15, count 0 2006.257.21:51:37.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:51:37.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.21:51:37.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.21:51:37.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.21:51:37.56$vck44/va=7,4 2006.257.21:51:37.56#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.21:51:37.56#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.21:51:37.56#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:37.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:37.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:37.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:37.62#ibcon#enter wrdev, iclass 17, count 2 2006.257.21:51:37.62#ibcon#first serial, iclass 17, count 2 2006.257.21:51:37.62#ibcon#enter sib2, iclass 17, count 2 2006.257.21:51:37.62#ibcon#flushed, iclass 17, count 2 2006.257.21:51:37.62#ibcon#about to write, iclass 17, count 2 2006.257.21:51:37.62#ibcon#wrote, iclass 17, count 2 2006.257.21:51:37.62#ibcon#about to read 3, iclass 17, count 2 2006.257.21:51:37.64#ibcon#read 3, iclass 17, count 2 2006.257.21:51:37.64#ibcon#about to read 4, iclass 17, count 2 2006.257.21:51:37.64#ibcon#read 4, iclass 17, count 2 2006.257.21:51:37.64#ibcon#about to read 5, iclass 17, count 2 2006.257.21:51:37.64#ibcon#read 5, iclass 17, count 2 2006.257.21:51:37.64#ibcon#about to read 6, iclass 17, count 2 2006.257.21:51:37.64#ibcon#read 6, iclass 17, count 2 2006.257.21:51:37.64#ibcon#end of sib2, iclass 17, count 2 2006.257.21:51:37.64#ibcon#*mode == 0, iclass 17, count 2 2006.257.21:51:37.64#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.21:51:37.64#ibcon#[25=AT07-04\r\n] 2006.257.21:51:37.64#ibcon#*before write, iclass 17, count 2 2006.257.21:51:37.64#ibcon#enter sib2, iclass 17, count 2 2006.257.21:51:37.64#ibcon#flushed, iclass 17, count 2 2006.257.21:51:37.64#ibcon#about to write, iclass 17, count 2 2006.257.21:51:37.64#ibcon#wrote, iclass 17, count 2 2006.257.21:51:37.64#ibcon#about to read 3, iclass 17, count 2 2006.257.21:51:37.67#ibcon#read 3, iclass 17, count 2 2006.257.21:51:37.67#ibcon#about to read 4, iclass 17, count 2 2006.257.21:51:37.67#ibcon#read 4, iclass 17, count 2 2006.257.21:51:37.67#ibcon#about to read 5, iclass 17, count 2 2006.257.21:51:37.67#ibcon#read 5, iclass 17, count 2 2006.257.21:51:37.67#ibcon#about to read 6, iclass 17, count 2 2006.257.21:51:37.67#ibcon#read 6, iclass 17, count 2 2006.257.21:51:37.67#ibcon#end of sib2, iclass 17, count 2 2006.257.21:51:37.67#ibcon#*after write, iclass 17, count 2 2006.257.21:51:37.67#ibcon#*before return 0, iclass 17, count 2 2006.257.21:51:37.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:37.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:37.67#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.21:51:37.67#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:37.67#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:37.79#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:37.79#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:37.79#ibcon#enter wrdev, iclass 17, count 0 2006.257.21:51:37.79#ibcon#first serial, iclass 17, count 0 2006.257.21:51:37.79#ibcon#enter sib2, iclass 17, count 0 2006.257.21:51:37.79#ibcon#flushed, iclass 17, count 0 2006.257.21:51:37.79#ibcon#about to write, iclass 17, count 0 2006.257.21:51:37.79#ibcon#wrote, iclass 17, count 0 2006.257.21:51:37.79#ibcon#about to read 3, iclass 17, count 0 2006.257.21:51:37.81#ibcon#read 3, iclass 17, count 0 2006.257.21:51:37.81#ibcon#about to read 4, iclass 17, count 0 2006.257.21:51:37.81#ibcon#read 4, iclass 17, count 0 2006.257.21:51:37.81#ibcon#about to read 5, iclass 17, count 0 2006.257.21:51:37.81#ibcon#read 5, iclass 17, count 0 2006.257.21:51:37.81#ibcon#about to read 6, iclass 17, count 0 2006.257.21:51:37.81#ibcon#read 6, iclass 17, count 0 2006.257.21:51:37.81#ibcon#end of sib2, iclass 17, count 0 2006.257.21:51:37.81#ibcon#*mode == 0, iclass 17, count 0 2006.257.21:51:37.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.21:51:37.81#ibcon#[25=USB\r\n] 2006.257.21:51:37.81#ibcon#*before write, iclass 17, count 0 2006.257.21:51:37.81#ibcon#enter sib2, iclass 17, count 0 2006.257.21:51:37.81#ibcon#flushed, iclass 17, count 0 2006.257.21:51:37.81#ibcon#about to write, iclass 17, count 0 2006.257.21:51:37.81#ibcon#wrote, iclass 17, count 0 2006.257.21:51:37.81#ibcon#about to read 3, iclass 17, count 0 2006.257.21:51:37.84#ibcon#read 3, iclass 17, count 0 2006.257.21:51:37.84#ibcon#about to read 4, iclass 17, count 0 2006.257.21:51:37.84#ibcon#read 4, iclass 17, count 0 2006.257.21:51:37.84#ibcon#about to read 5, iclass 17, count 0 2006.257.21:51:37.84#ibcon#read 5, iclass 17, count 0 2006.257.21:51:37.84#ibcon#about to read 6, iclass 17, count 0 2006.257.21:51:37.84#ibcon#read 6, iclass 17, count 0 2006.257.21:51:37.84#ibcon#end of sib2, iclass 17, count 0 2006.257.21:51:37.84#ibcon#*after write, iclass 17, count 0 2006.257.21:51:37.84#ibcon#*before return 0, iclass 17, count 0 2006.257.21:51:37.84#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:37.84#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:37.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.21:51:37.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.21:51:37.84$vck44/valo=8,884.99 2006.257.21:51:37.84#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.21:51:37.84#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.21:51:37.84#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:37.84#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:37.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:37.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:37.84#ibcon#enter wrdev, iclass 19, count 0 2006.257.21:51:37.84#ibcon#first serial, iclass 19, count 0 2006.257.21:51:37.84#ibcon#enter sib2, iclass 19, count 0 2006.257.21:51:37.84#ibcon#flushed, iclass 19, count 0 2006.257.21:51:37.84#ibcon#about to write, iclass 19, count 0 2006.257.21:51:37.84#ibcon#wrote, iclass 19, count 0 2006.257.21:51:37.84#ibcon#about to read 3, iclass 19, count 0 2006.257.21:51:37.86#ibcon#read 3, iclass 19, count 0 2006.257.21:51:37.86#ibcon#about to read 4, iclass 19, count 0 2006.257.21:51:37.86#ibcon#read 4, iclass 19, count 0 2006.257.21:51:37.86#ibcon#about to read 5, iclass 19, count 0 2006.257.21:51:37.86#ibcon#read 5, iclass 19, count 0 2006.257.21:51:37.86#ibcon#about to read 6, iclass 19, count 0 2006.257.21:51:37.86#ibcon#read 6, iclass 19, count 0 2006.257.21:51:37.86#ibcon#end of sib2, iclass 19, count 0 2006.257.21:51:37.86#ibcon#*mode == 0, iclass 19, count 0 2006.257.21:51:37.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.21:51:37.86#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.21:51:37.86#ibcon#*before write, iclass 19, count 0 2006.257.21:51:37.86#ibcon#enter sib2, iclass 19, count 0 2006.257.21:51:37.86#ibcon#flushed, iclass 19, count 0 2006.257.21:51:37.86#ibcon#about to write, iclass 19, count 0 2006.257.21:51:37.86#ibcon#wrote, iclass 19, count 0 2006.257.21:51:37.86#ibcon#about to read 3, iclass 19, count 0 2006.257.21:51:37.90#ibcon#read 3, iclass 19, count 0 2006.257.21:51:37.90#ibcon#about to read 4, iclass 19, count 0 2006.257.21:51:37.90#ibcon#read 4, iclass 19, count 0 2006.257.21:51:37.90#ibcon#about to read 5, iclass 19, count 0 2006.257.21:51:37.90#ibcon#read 5, iclass 19, count 0 2006.257.21:51:37.90#ibcon#about to read 6, iclass 19, count 0 2006.257.21:51:37.90#ibcon#read 6, iclass 19, count 0 2006.257.21:51:37.90#ibcon#end of sib2, iclass 19, count 0 2006.257.21:51:37.90#ibcon#*after write, iclass 19, count 0 2006.257.21:51:37.90#ibcon#*before return 0, iclass 19, count 0 2006.257.21:51:37.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:37.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:37.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.21:51:37.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.21:51:37.90$vck44/va=8,4 2006.257.21:51:37.90#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.21:51:37.90#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.21:51:37.90#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:37.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:37.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:37.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:37.96#ibcon#enter wrdev, iclass 21, count 2 2006.257.21:51:37.96#ibcon#first serial, iclass 21, count 2 2006.257.21:51:37.96#ibcon#enter sib2, iclass 21, count 2 2006.257.21:51:37.96#ibcon#flushed, iclass 21, count 2 2006.257.21:51:37.96#ibcon#about to write, iclass 21, count 2 2006.257.21:51:37.96#ibcon#wrote, iclass 21, count 2 2006.257.21:51:37.96#ibcon#about to read 3, iclass 21, count 2 2006.257.21:51:37.98#ibcon#read 3, iclass 21, count 2 2006.257.21:51:37.98#ibcon#about to read 4, iclass 21, count 2 2006.257.21:51:37.98#ibcon#read 4, iclass 21, count 2 2006.257.21:51:37.98#ibcon#about to read 5, iclass 21, count 2 2006.257.21:51:37.98#ibcon#read 5, iclass 21, count 2 2006.257.21:51:37.98#ibcon#about to read 6, iclass 21, count 2 2006.257.21:51:37.98#ibcon#read 6, iclass 21, count 2 2006.257.21:51:37.98#ibcon#end of sib2, iclass 21, count 2 2006.257.21:51:37.98#ibcon#*mode == 0, iclass 21, count 2 2006.257.21:51:37.98#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.21:51:37.98#ibcon#[25=AT08-04\r\n] 2006.257.21:51:37.98#ibcon#*before write, iclass 21, count 2 2006.257.21:51:37.98#ibcon#enter sib2, iclass 21, count 2 2006.257.21:51:37.98#ibcon#flushed, iclass 21, count 2 2006.257.21:51:37.98#ibcon#about to write, iclass 21, count 2 2006.257.21:51:37.98#ibcon#wrote, iclass 21, count 2 2006.257.21:51:37.98#ibcon#about to read 3, iclass 21, count 2 2006.257.21:51:38.01#ibcon#read 3, iclass 21, count 2 2006.257.21:51:38.01#ibcon#about to read 4, iclass 21, count 2 2006.257.21:51:38.01#ibcon#read 4, iclass 21, count 2 2006.257.21:51:38.01#ibcon#about to read 5, iclass 21, count 2 2006.257.21:51:38.01#ibcon#read 5, iclass 21, count 2 2006.257.21:51:38.01#ibcon#about to read 6, iclass 21, count 2 2006.257.21:51:38.01#ibcon#read 6, iclass 21, count 2 2006.257.21:51:38.01#ibcon#end of sib2, iclass 21, count 2 2006.257.21:51:38.01#ibcon#*after write, iclass 21, count 2 2006.257.21:51:38.01#ibcon#*before return 0, iclass 21, count 2 2006.257.21:51:38.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:38.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:38.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.21:51:38.01#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:38.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:38.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:38.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:38.13#ibcon#enter wrdev, iclass 21, count 0 2006.257.21:51:38.13#ibcon#first serial, iclass 21, count 0 2006.257.21:51:38.13#ibcon#enter sib2, iclass 21, count 0 2006.257.21:51:38.13#ibcon#flushed, iclass 21, count 0 2006.257.21:51:38.13#ibcon#about to write, iclass 21, count 0 2006.257.21:51:38.13#ibcon#wrote, iclass 21, count 0 2006.257.21:51:38.13#ibcon#about to read 3, iclass 21, count 0 2006.257.21:51:38.15#ibcon#read 3, iclass 21, count 0 2006.257.21:51:38.15#ibcon#about to read 4, iclass 21, count 0 2006.257.21:51:38.15#ibcon#read 4, iclass 21, count 0 2006.257.21:51:38.15#ibcon#about to read 5, iclass 21, count 0 2006.257.21:51:38.15#ibcon#read 5, iclass 21, count 0 2006.257.21:51:38.15#ibcon#about to read 6, iclass 21, count 0 2006.257.21:51:38.15#ibcon#read 6, iclass 21, count 0 2006.257.21:51:38.15#ibcon#end of sib2, iclass 21, count 0 2006.257.21:51:38.15#ibcon#*mode == 0, iclass 21, count 0 2006.257.21:51:38.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.21:51:38.15#ibcon#[25=USB\r\n] 2006.257.21:51:38.15#ibcon#*before write, iclass 21, count 0 2006.257.21:51:38.15#ibcon#enter sib2, iclass 21, count 0 2006.257.21:51:38.15#ibcon#flushed, iclass 21, count 0 2006.257.21:51:38.15#ibcon#about to write, iclass 21, count 0 2006.257.21:51:38.15#ibcon#wrote, iclass 21, count 0 2006.257.21:51:38.15#ibcon#about to read 3, iclass 21, count 0 2006.257.21:51:38.18#ibcon#read 3, iclass 21, count 0 2006.257.21:51:38.18#ibcon#about to read 4, iclass 21, count 0 2006.257.21:51:38.18#ibcon#read 4, iclass 21, count 0 2006.257.21:51:38.18#ibcon#about to read 5, iclass 21, count 0 2006.257.21:51:38.18#ibcon#read 5, iclass 21, count 0 2006.257.21:51:38.18#ibcon#about to read 6, iclass 21, count 0 2006.257.21:51:38.18#ibcon#read 6, iclass 21, count 0 2006.257.21:51:38.18#ibcon#end of sib2, iclass 21, count 0 2006.257.21:51:38.18#ibcon#*after write, iclass 21, count 0 2006.257.21:51:38.18#ibcon#*before return 0, iclass 21, count 0 2006.257.21:51:38.18#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:38.18#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:38.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.21:51:38.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.21:51:38.18$vck44/vblo=1,629.99 2006.257.21:51:38.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.21:51:38.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.21:51:38.18#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:38.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:38.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:38.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:38.18#ibcon#enter wrdev, iclass 23, count 0 2006.257.21:51:38.18#ibcon#first serial, iclass 23, count 0 2006.257.21:51:38.18#ibcon#enter sib2, iclass 23, count 0 2006.257.21:51:38.18#ibcon#flushed, iclass 23, count 0 2006.257.21:51:38.18#ibcon#about to write, iclass 23, count 0 2006.257.21:51:38.18#ibcon#wrote, iclass 23, count 0 2006.257.21:51:38.18#ibcon#about to read 3, iclass 23, count 0 2006.257.21:51:38.20#ibcon#read 3, iclass 23, count 0 2006.257.21:51:38.20#ibcon#about to read 4, iclass 23, count 0 2006.257.21:51:38.20#ibcon#read 4, iclass 23, count 0 2006.257.21:51:38.20#ibcon#about to read 5, iclass 23, count 0 2006.257.21:51:38.20#ibcon#read 5, iclass 23, count 0 2006.257.21:51:38.20#ibcon#about to read 6, iclass 23, count 0 2006.257.21:51:38.20#ibcon#read 6, iclass 23, count 0 2006.257.21:51:38.20#ibcon#end of sib2, iclass 23, count 0 2006.257.21:51:38.20#ibcon#*mode == 0, iclass 23, count 0 2006.257.21:51:38.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.21:51:38.20#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.21:51:38.20#ibcon#*before write, iclass 23, count 0 2006.257.21:51:38.20#ibcon#enter sib2, iclass 23, count 0 2006.257.21:51:38.20#ibcon#flushed, iclass 23, count 0 2006.257.21:51:38.20#ibcon#about to write, iclass 23, count 0 2006.257.21:51:38.20#ibcon#wrote, iclass 23, count 0 2006.257.21:51:38.20#ibcon#about to read 3, iclass 23, count 0 2006.257.21:51:38.24#ibcon#read 3, iclass 23, count 0 2006.257.21:51:38.24#ibcon#about to read 4, iclass 23, count 0 2006.257.21:51:38.24#ibcon#read 4, iclass 23, count 0 2006.257.21:51:38.24#ibcon#about to read 5, iclass 23, count 0 2006.257.21:51:38.24#ibcon#read 5, iclass 23, count 0 2006.257.21:51:38.24#ibcon#about to read 6, iclass 23, count 0 2006.257.21:51:38.24#ibcon#read 6, iclass 23, count 0 2006.257.21:51:38.24#ibcon#end of sib2, iclass 23, count 0 2006.257.21:51:38.24#ibcon#*after write, iclass 23, count 0 2006.257.21:51:38.24#ibcon#*before return 0, iclass 23, count 0 2006.257.21:51:38.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:38.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:38.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.21:51:38.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.21:51:38.24$vck44/vb=1,4 2006.257.21:51:38.24#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.21:51:38.24#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.21:51:38.24#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:38.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:51:38.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:51:38.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:51:38.24#ibcon#enter wrdev, iclass 25, count 2 2006.257.21:51:38.24#ibcon#first serial, iclass 25, count 2 2006.257.21:51:38.24#ibcon#enter sib2, iclass 25, count 2 2006.257.21:51:38.24#ibcon#flushed, iclass 25, count 2 2006.257.21:51:38.24#ibcon#about to write, iclass 25, count 2 2006.257.21:51:38.24#ibcon#wrote, iclass 25, count 2 2006.257.21:51:38.24#ibcon#about to read 3, iclass 25, count 2 2006.257.21:51:38.26#ibcon#read 3, iclass 25, count 2 2006.257.21:51:38.26#ibcon#about to read 4, iclass 25, count 2 2006.257.21:51:38.26#ibcon#read 4, iclass 25, count 2 2006.257.21:51:38.26#ibcon#about to read 5, iclass 25, count 2 2006.257.21:51:38.26#ibcon#read 5, iclass 25, count 2 2006.257.21:51:38.26#ibcon#about to read 6, iclass 25, count 2 2006.257.21:51:38.26#ibcon#read 6, iclass 25, count 2 2006.257.21:51:38.26#ibcon#end of sib2, iclass 25, count 2 2006.257.21:51:38.26#ibcon#*mode == 0, iclass 25, count 2 2006.257.21:51:38.26#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.21:51:38.26#ibcon#[27=AT01-04\r\n] 2006.257.21:51:38.26#ibcon#*before write, iclass 25, count 2 2006.257.21:51:38.26#ibcon#enter sib2, iclass 25, count 2 2006.257.21:51:38.26#ibcon#flushed, iclass 25, count 2 2006.257.21:51:38.26#ibcon#about to write, iclass 25, count 2 2006.257.21:51:38.26#ibcon#wrote, iclass 25, count 2 2006.257.21:51:38.26#ibcon#about to read 3, iclass 25, count 2 2006.257.21:51:38.29#ibcon#read 3, iclass 25, count 2 2006.257.21:51:38.29#ibcon#about to read 4, iclass 25, count 2 2006.257.21:51:38.29#ibcon#read 4, iclass 25, count 2 2006.257.21:51:38.29#ibcon#about to read 5, iclass 25, count 2 2006.257.21:51:38.29#ibcon#read 5, iclass 25, count 2 2006.257.21:51:38.29#ibcon#about to read 6, iclass 25, count 2 2006.257.21:51:38.29#ibcon#read 6, iclass 25, count 2 2006.257.21:51:38.29#ibcon#end of sib2, iclass 25, count 2 2006.257.21:51:38.29#ibcon#*after write, iclass 25, count 2 2006.257.21:51:38.29#ibcon#*before return 0, iclass 25, count 2 2006.257.21:51:38.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:51:38.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.21:51:38.29#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.21:51:38.29#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:38.29#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:51:38.41#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:51:38.41#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:51:38.41#ibcon#enter wrdev, iclass 25, count 0 2006.257.21:51:38.41#ibcon#first serial, iclass 25, count 0 2006.257.21:51:38.41#ibcon#enter sib2, iclass 25, count 0 2006.257.21:51:38.41#ibcon#flushed, iclass 25, count 0 2006.257.21:51:38.41#ibcon#about to write, iclass 25, count 0 2006.257.21:51:38.41#ibcon#wrote, iclass 25, count 0 2006.257.21:51:38.41#ibcon#about to read 3, iclass 25, count 0 2006.257.21:51:38.43#ibcon#read 3, iclass 25, count 0 2006.257.21:51:38.43#ibcon#about to read 4, iclass 25, count 0 2006.257.21:51:38.43#ibcon#read 4, iclass 25, count 0 2006.257.21:51:38.43#ibcon#about to read 5, iclass 25, count 0 2006.257.21:51:38.43#ibcon#read 5, iclass 25, count 0 2006.257.21:51:38.43#ibcon#about to read 6, iclass 25, count 0 2006.257.21:51:38.43#ibcon#read 6, iclass 25, count 0 2006.257.21:51:38.43#ibcon#end of sib2, iclass 25, count 0 2006.257.21:51:38.43#ibcon#*mode == 0, iclass 25, count 0 2006.257.21:51:38.43#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.21:51:38.43#ibcon#[27=USB\r\n] 2006.257.21:51:38.43#ibcon#*before write, iclass 25, count 0 2006.257.21:51:38.43#ibcon#enter sib2, iclass 25, count 0 2006.257.21:51:38.43#ibcon#flushed, iclass 25, count 0 2006.257.21:51:38.43#ibcon#about to write, iclass 25, count 0 2006.257.21:51:38.43#ibcon#wrote, iclass 25, count 0 2006.257.21:51:38.43#ibcon#about to read 3, iclass 25, count 0 2006.257.21:51:38.46#ibcon#read 3, iclass 25, count 0 2006.257.21:51:38.46#ibcon#about to read 4, iclass 25, count 0 2006.257.21:51:38.46#ibcon#read 4, iclass 25, count 0 2006.257.21:51:38.46#ibcon#about to read 5, iclass 25, count 0 2006.257.21:51:38.46#ibcon#read 5, iclass 25, count 0 2006.257.21:51:38.46#ibcon#about to read 6, iclass 25, count 0 2006.257.21:51:38.46#ibcon#read 6, iclass 25, count 0 2006.257.21:51:38.46#ibcon#end of sib2, iclass 25, count 0 2006.257.21:51:38.46#ibcon#*after write, iclass 25, count 0 2006.257.21:51:38.46#ibcon#*before return 0, iclass 25, count 0 2006.257.21:51:38.46#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:51:38.46#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.21:51:38.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.21:51:38.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.21:51:38.46$vck44/vblo=2,634.99 2006.257.21:51:38.46#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.21:51:38.46#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.21:51:38.46#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:38.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:38.46#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:38.46#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:38.46#ibcon#enter wrdev, iclass 27, count 0 2006.257.21:51:38.46#ibcon#first serial, iclass 27, count 0 2006.257.21:51:38.46#ibcon#enter sib2, iclass 27, count 0 2006.257.21:51:38.46#ibcon#flushed, iclass 27, count 0 2006.257.21:51:38.46#ibcon#about to write, iclass 27, count 0 2006.257.21:51:38.46#ibcon#wrote, iclass 27, count 0 2006.257.21:51:38.46#ibcon#about to read 3, iclass 27, count 0 2006.257.21:51:38.48#ibcon#read 3, iclass 27, count 0 2006.257.21:51:38.48#ibcon#about to read 4, iclass 27, count 0 2006.257.21:51:38.48#ibcon#read 4, iclass 27, count 0 2006.257.21:51:38.48#ibcon#about to read 5, iclass 27, count 0 2006.257.21:51:38.48#ibcon#read 5, iclass 27, count 0 2006.257.21:51:38.48#ibcon#about to read 6, iclass 27, count 0 2006.257.21:51:38.48#ibcon#read 6, iclass 27, count 0 2006.257.21:51:38.48#ibcon#end of sib2, iclass 27, count 0 2006.257.21:51:38.48#ibcon#*mode == 0, iclass 27, count 0 2006.257.21:51:38.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.21:51:38.48#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.21:51:38.48#ibcon#*before write, iclass 27, count 0 2006.257.21:51:38.48#ibcon#enter sib2, iclass 27, count 0 2006.257.21:51:38.48#ibcon#flushed, iclass 27, count 0 2006.257.21:51:38.48#ibcon#about to write, iclass 27, count 0 2006.257.21:51:38.48#ibcon#wrote, iclass 27, count 0 2006.257.21:51:38.48#ibcon#about to read 3, iclass 27, count 0 2006.257.21:51:38.52#ibcon#read 3, iclass 27, count 0 2006.257.21:51:38.52#ibcon#about to read 4, iclass 27, count 0 2006.257.21:51:38.52#ibcon#read 4, iclass 27, count 0 2006.257.21:51:38.52#ibcon#about to read 5, iclass 27, count 0 2006.257.21:51:38.52#ibcon#read 5, iclass 27, count 0 2006.257.21:51:38.52#ibcon#about to read 6, iclass 27, count 0 2006.257.21:51:38.52#ibcon#read 6, iclass 27, count 0 2006.257.21:51:38.52#ibcon#end of sib2, iclass 27, count 0 2006.257.21:51:38.52#ibcon#*after write, iclass 27, count 0 2006.257.21:51:38.52#ibcon#*before return 0, iclass 27, count 0 2006.257.21:51:38.52#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:38.52#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.21:51:38.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.21:51:38.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.21:51:38.52$vck44/vb=2,5 2006.257.21:51:38.52#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.21:51:38.52#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.21:51:38.52#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:38.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:38.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:38.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:38.58#ibcon#enter wrdev, iclass 29, count 2 2006.257.21:51:38.58#ibcon#first serial, iclass 29, count 2 2006.257.21:51:38.58#ibcon#enter sib2, iclass 29, count 2 2006.257.21:51:38.58#ibcon#flushed, iclass 29, count 2 2006.257.21:51:38.58#ibcon#about to write, iclass 29, count 2 2006.257.21:51:38.58#ibcon#wrote, iclass 29, count 2 2006.257.21:51:38.58#ibcon#about to read 3, iclass 29, count 2 2006.257.21:51:38.60#ibcon#read 3, iclass 29, count 2 2006.257.21:51:38.60#ibcon#about to read 4, iclass 29, count 2 2006.257.21:51:38.60#ibcon#read 4, iclass 29, count 2 2006.257.21:51:38.60#ibcon#about to read 5, iclass 29, count 2 2006.257.21:51:38.60#ibcon#read 5, iclass 29, count 2 2006.257.21:51:38.60#ibcon#about to read 6, iclass 29, count 2 2006.257.21:51:38.60#ibcon#read 6, iclass 29, count 2 2006.257.21:51:38.60#ibcon#end of sib2, iclass 29, count 2 2006.257.21:51:38.60#ibcon#*mode == 0, iclass 29, count 2 2006.257.21:51:38.60#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.21:51:38.60#ibcon#[27=AT02-05\r\n] 2006.257.21:51:38.60#ibcon#*before write, iclass 29, count 2 2006.257.21:51:38.60#ibcon#enter sib2, iclass 29, count 2 2006.257.21:51:38.60#ibcon#flushed, iclass 29, count 2 2006.257.21:51:38.60#ibcon#about to write, iclass 29, count 2 2006.257.21:51:38.60#ibcon#wrote, iclass 29, count 2 2006.257.21:51:38.60#ibcon#about to read 3, iclass 29, count 2 2006.257.21:51:38.63#ibcon#read 3, iclass 29, count 2 2006.257.21:51:38.63#ibcon#about to read 4, iclass 29, count 2 2006.257.21:51:38.63#ibcon#read 4, iclass 29, count 2 2006.257.21:51:38.63#ibcon#about to read 5, iclass 29, count 2 2006.257.21:51:38.63#ibcon#read 5, iclass 29, count 2 2006.257.21:51:38.63#ibcon#about to read 6, iclass 29, count 2 2006.257.21:51:38.63#ibcon#read 6, iclass 29, count 2 2006.257.21:51:38.63#ibcon#end of sib2, iclass 29, count 2 2006.257.21:51:38.63#ibcon#*after write, iclass 29, count 2 2006.257.21:51:38.63#ibcon#*before return 0, iclass 29, count 2 2006.257.21:51:38.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:38.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.21:51:38.63#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.21:51:38.63#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:38.63#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:38.75#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:38.75#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:38.75#ibcon#enter wrdev, iclass 29, count 0 2006.257.21:51:38.75#ibcon#first serial, iclass 29, count 0 2006.257.21:51:38.75#ibcon#enter sib2, iclass 29, count 0 2006.257.21:51:38.75#ibcon#flushed, iclass 29, count 0 2006.257.21:51:38.75#ibcon#about to write, iclass 29, count 0 2006.257.21:51:38.75#ibcon#wrote, iclass 29, count 0 2006.257.21:51:38.75#ibcon#about to read 3, iclass 29, count 0 2006.257.21:51:38.77#ibcon#read 3, iclass 29, count 0 2006.257.21:51:38.77#ibcon#about to read 4, iclass 29, count 0 2006.257.21:51:38.77#ibcon#read 4, iclass 29, count 0 2006.257.21:51:38.77#ibcon#about to read 5, iclass 29, count 0 2006.257.21:51:38.77#ibcon#read 5, iclass 29, count 0 2006.257.21:51:38.77#ibcon#about to read 6, iclass 29, count 0 2006.257.21:51:38.77#ibcon#read 6, iclass 29, count 0 2006.257.21:51:38.77#ibcon#end of sib2, iclass 29, count 0 2006.257.21:51:38.77#ibcon#*mode == 0, iclass 29, count 0 2006.257.21:51:38.77#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.21:51:38.77#ibcon#[27=USB\r\n] 2006.257.21:51:38.77#ibcon#*before write, iclass 29, count 0 2006.257.21:51:38.77#ibcon#enter sib2, iclass 29, count 0 2006.257.21:51:38.77#ibcon#flushed, iclass 29, count 0 2006.257.21:51:38.77#ibcon#about to write, iclass 29, count 0 2006.257.21:51:38.77#ibcon#wrote, iclass 29, count 0 2006.257.21:51:38.77#ibcon#about to read 3, iclass 29, count 0 2006.257.21:51:38.80#ibcon#read 3, iclass 29, count 0 2006.257.21:51:38.80#ibcon#about to read 4, iclass 29, count 0 2006.257.21:51:38.80#ibcon#read 4, iclass 29, count 0 2006.257.21:51:38.80#ibcon#about to read 5, iclass 29, count 0 2006.257.21:51:38.80#ibcon#read 5, iclass 29, count 0 2006.257.21:51:38.80#ibcon#about to read 6, iclass 29, count 0 2006.257.21:51:38.80#ibcon#read 6, iclass 29, count 0 2006.257.21:51:38.80#ibcon#end of sib2, iclass 29, count 0 2006.257.21:51:38.80#ibcon#*after write, iclass 29, count 0 2006.257.21:51:38.80#ibcon#*before return 0, iclass 29, count 0 2006.257.21:51:38.80#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:38.80#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.21:51:38.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.21:51:38.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.21:51:38.80$vck44/vblo=3,649.99 2006.257.21:51:38.80#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.21:51:38.80#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.21:51:38.80#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:38.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:38.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:38.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:38.80#ibcon#enter wrdev, iclass 31, count 0 2006.257.21:51:38.80#ibcon#first serial, iclass 31, count 0 2006.257.21:51:38.80#ibcon#enter sib2, iclass 31, count 0 2006.257.21:51:38.80#ibcon#flushed, iclass 31, count 0 2006.257.21:51:38.80#ibcon#about to write, iclass 31, count 0 2006.257.21:51:38.80#ibcon#wrote, iclass 31, count 0 2006.257.21:51:38.80#ibcon#about to read 3, iclass 31, count 0 2006.257.21:51:38.82#ibcon#read 3, iclass 31, count 0 2006.257.21:51:38.82#ibcon#about to read 4, iclass 31, count 0 2006.257.21:51:38.82#ibcon#read 4, iclass 31, count 0 2006.257.21:51:38.82#ibcon#about to read 5, iclass 31, count 0 2006.257.21:51:38.82#ibcon#read 5, iclass 31, count 0 2006.257.21:51:38.82#ibcon#about to read 6, iclass 31, count 0 2006.257.21:51:38.82#ibcon#read 6, iclass 31, count 0 2006.257.21:51:38.82#ibcon#end of sib2, iclass 31, count 0 2006.257.21:51:38.82#ibcon#*mode == 0, iclass 31, count 0 2006.257.21:51:38.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.21:51:38.82#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.21:51:38.82#ibcon#*before write, iclass 31, count 0 2006.257.21:51:38.82#ibcon#enter sib2, iclass 31, count 0 2006.257.21:51:38.82#ibcon#flushed, iclass 31, count 0 2006.257.21:51:38.82#ibcon#about to write, iclass 31, count 0 2006.257.21:51:38.82#ibcon#wrote, iclass 31, count 0 2006.257.21:51:38.82#ibcon#about to read 3, iclass 31, count 0 2006.257.21:51:38.86#ibcon#read 3, iclass 31, count 0 2006.257.21:51:38.86#ibcon#about to read 4, iclass 31, count 0 2006.257.21:51:38.86#ibcon#read 4, iclass 31, count 0 2006.257.21:51:38.86#ibcon#about to read 5, iclass 31, count 0 2006.257.21:51:38.86#ibcon#read 5, iclass 31, count 0 2006.257.21:51:38.86#ibcon#about to read 6, iclass 31, count 0 2006.257.21:51:38.86#ibcon#read 6, iclass 31, count 0 2006.257.21:51:38.86#ibcon#end of sib2, iclass 31, count 0 2006.257.21:51:38.86#ibcon#*after write, iclass 31, count 0 2006.257.21:51:38.86#ibcon#*before return 0, iclass 31, count 0 2006.257.21:51:38.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:38.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.21:51:38.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.21:51:38.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.21:51:38.86$vck44/vb=3,4 2006.257.21:51:38.86#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.21:51:38.86#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.21:51:38.86#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:38.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:38.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:38.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:38.92#ibcon#enter wrdev, iclass 33, count 2 2006.257.21:51:38.92#ibcon#first serial, iclass 33, count 2 2006.257.21:51:38.92#ibcon#enter sib2, iclass 33, count 2 2006.257.21:51:38.92#ibcon#flushed, iclass 33, count 2 2006.257.21:51:38.92#ibcon#about to write, iclass 33, count 2 2006.257.21:51:38.92#ibcon#wrote, iclass 33, count 2 2006.257.21:51:38.92#ibcon#about to read 3, iclass 33, count 2 2006.257.21:51:38.94#ibcon#read 3, iclass 33, count 2 2006.257.21:51:38.94#ibcon#about to read 4, iclass 33, count 2 2006.257.21:51:38.94#ibcon#read 4, iclass 33, count 2 2006.257.21:51:38.94#ibcon#about to read 5, iclass 33, count 2 2006.257.21:51:38.94#ibcon#read 5, iclass 33, count 2 2006.257.21:51:38.94#ibcon#about to read 6, iclass 33, count 2 2006.257.21:51:38.94#ibcon#read 6, iclass 33, count 2 2006.257.21:51:38.94#ibcon#end of sib2, iclass 33, count 2 2006.257.21:51:38.94#ibcon#*mode == 0, iclass 33, count 2 2006.257.21:51:38.94#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.21:51:38.94#ibcon#[27=AT03-04\r\n] 2006.257.21:51:38.94#ibcon#*before write, iclass 33, count 2 2006.257.21:51:38.94#ibcon#enter sib2, iclass 33, count 2 2006.257.21:51:38.94#ibcon#flushed, iclass 33, count 2 2006.257.21:51:38.94#ibcon#about to write, iclass 33, count 2 2006.257.21:51:38.94#ibcon#wrote, iclass 33, count 2 2006.257.21:51:38.94#ibcon#about to read 3, iclass 33, count 2 2006.257.21:51:38.97#ibcon#read 3, iclass 33, count 2 2006.257.21:51:38.97#ibcon#about to read 4, iclass 33, count 2 2006.257.21:51:38.97#ibcon#read 4, iclass 33, count 2 2006.257.21:51:38.97#ibcon#about to read 5, iclass 33, count 2 2006.257.21:51:38.97#ibcon#read 5, iclass 33, count 2 2006.257.21:51:38.97#ibcon#about to read 6, iclass 33, count 2 2006.257.21:51:38.97#ibcon#read 6, iclass 33, count 2 2006.257.21:51:38.97#ibcon#end of sib2, iclass 33, count 2 2006.257.21:51:38.97#ibcon#*after write, iclass 33, count 2 2006.257.21:51:38.97#ibcon#*before return 0, iclass 33, count 2 2006.257.21:51:38.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:38.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.21:51:38.97#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.21:51:38.97#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:38.97#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:39.09#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:39.09#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:39.09#ibcon#enter wrdev, iclass 33, count 0 2006.257.21:51:39.09#ibcon#first serial, iclass 33, count 0 2006.257.21:51:39.09#ibcon#enter sib2, iclass 33, count 0 2006.257.21:51:39.09#ibcon#flushed, iclass 33, count 0 2006.257.21:51:39.09#ibcon#about to write, iclass 33, count 0 2006.257.21:51:39.09#ibcon#wrote, iclass 33, count 0 2006.257.21:51:39.09#ibcon#about to read 3, iclass 33, count 0 2006.257.21:51:39.11#ibcon#read 3, iclass 33, count 0 2006.257.21:51:39.11#ibcon#about to read 4, iclass 33, count 0 2006.257.21:51:39.11#ibcon#read 4, iclass 33, count 0 2006.257.21:51:39.11#ibcon#about to read 5, iclass 33, count 0 2006.257.21:51:39.11#ibcon#read 5, iclass 33, count 0 2006.257.21:51:39.11#ibcon#about to read 6, iclass 33, count 0 2006.257.21:51:39.11#ibcon#read 6, iclass 33, count 0 2006.257.21:51:39.11#ibcon#end of sib2, iclass 33, count 0 2006.257.21:51:39.11#ibcon#*mode == 0, iclass 33, count 0 2006.257.21:51:39.11#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.21:51:39.11#ibcon#[27=USB\r\n] 2006.257.21:51:39.11#ibcon#*before write, iclass 33, count 0 2006.257.21:51:39.11#ibcon#enter sib2, iclass 33, count 0 2006.257.21:51:39.11#ibcon#flushed, iclass 33, count 0 2006.257.21:51:39.11#ibcon#about to write, iclass 33, count 0 2006.257.21:51:39.11#ibcon#wrote, iclass 33, count 0 2006.257.21:51:39.11#ibcon#about to read 3, iclass 33, count 0 2006.257.21:51:39.14#ibcon#read 3, iclass 33, count 0 2006.257.21:51:39.14#ibcon#about to read 4, iclass 33, count 0 2006.257.21:51:39.14#ibcon#read 4, iclass 33, count 0 2006.257.21:51:39.14#ibcon#about to read 5, iclass 33, count 0 2006.257.21:51:39.14#ibcon#read 5, iclass 33, count 0 2006.257.21:51:39.14#ibcon#about to read 6, iclass 33, count 0 2006.257.21:51:39.14#ibcon#read 6, iclass 33, count 0 2006.257.21:51:39.14#ibcon#end of sib2, iclass 33, count 0 2006.257.21:51:39.14#ibcon#*after write, iclass 33, count 0 2006.257.21:51:39.14#ibcon#*before return 0, iclass 33, count 0 2006.257.21:51:39.14#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:39.14#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.21:51:39.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.21:51:39.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.21:51:39.14$vck44/vblo=4,679.99 2006.257.21:51:39.14#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.21:51:39.14#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.21:51:39.14#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:39.14#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:39.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:39.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:39.14#ibcon#enter wrdev, iclass 35, count 0 2006.257.21:51:39.14#ibcon#first serial, iclass 35, count 0 2006.257.21:51:39.14#ibcon#enter sib2, iclass 35, count 0 2006.257.21:51:39.14#ibcon#flushed, iclass 35, count 0 2006.257.21:51:39.14#ibcon#about to write, iclass 35, count 0 2006.257.21:51:39.14#ibcon#wrote, iclass 35, count 0 2006.257.21:51:39.14#ibcon#about to read 3, iclass 35, count 0 2006.257.21:51:39.16#ibcon#read 3, iclass 35, count 0 2006.257.21:51:39.16#ibcon#about to read 4, iclass 35, count 0 2006.257.21:51:39.16#ibcon#read 4, iclass 35, count 0 2006.257.21:51:39.16#ibcon#about to read 5, iclass 35, count 0 2006.257.21:51:39.16#ibcon#read 5, iclass 35, count 0 2006.257.21:51:39.16#ibcon#about to read 6, iclass 35, count 0 2006.257.21:51:39.16#ibcon#read 6, iclass 35, count 0 2006.257.21:51:39.16#ibcon#end of sib2, iclass 35, count 0 2006.257.21:51:39.16#ibcon#*mode == 0, iclass 35, count 0 2006.257.21:51:39.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.21:51:39.16#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.21:51:39.16#ibcon#*before write, iclass 35, count 0 2006.257.21:51:39.16#ibcon#enter sib2, iclass 35, count 0 2006.257.21:51:39.16#ibcon#flushed, iclass 35, count 0 2006.257.21:51:39.16#ibcon#about to write, iclass 35, count 0 2006.257.21:51:39.16#ibcon#wrote, iclass 35, count 0 2006.257.21:51:39.16#ibcon#about to read 3, iclass 35, count 0 2006.257.21:51:39.20#ibcon#read 3, iclass 35, count 0 2006.257.21:51:39.20#ibcon#about to read 4, iclass 35, count 0 2006.257.21:51:39.20#ibcon#read 4, iclass 35, count 0 2006.257.21:51:39.20#ibcon#about to read 5, iclass 35, count 0 2006.257.21:51:39.20#ibcon#read 5, iclass 35, count 0 2006.257.21:51:39.20#ibcon#about to read 6, iclass 35, count 0 2006.257.21:51:39.20#ibcon#read 6, iclass 35, count 0 2006.257.21:51:39.20#ibcon#end of sib2, iclass 35, count 0 2006.257.21:51:39.20#ibcon#*after write, iclass 35, count 0 2006.257.21:51:39.20#ibcon#*before return 0, iclass 35, count 0 2006.257.21:51:39.20#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:39.20#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.21:51:39.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.21:51:39.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.21:51:39.20$vck44/vb=4,5 2006.257.21:51:39.20#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.21:51:39.20#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.21:51:39.20#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:39.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:39.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:39.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:39.26#ibcon#enter wrdev, iclass 37, count 2 2006.257.21:51:39.26#ibcon#first serial, iclass 37, count 2 2006.257.21:51:39.26#ibcon#enter sib2, iclass 37, count 2 2006.257.21:51:39.26#ibcon#flushed, iclass 37, count 2 2006.257.21:51:39.26#ibcon#about to write, iclass 37, count 2 2006.257.21:51:39.26#ibcon#wrote, iclass 37, count 2 2006.257.21:51:39.26#ibcon#about to read 3, iclass 37, count 2 2006.257.21:51:39.28#ibcon#read 3, iclass 37, count 2 2006.257.21:51:39.28#ibcon#about to read 4, iclass 37, count 2 2006.257.21:51:39.28#ibcon#read 4, iclass 37, count 2 2006.257.21:51:39.28#ibcon#about to read 5, iclass 37, count 2 2006.257.21:51:39.28#ibcon#read 5, iclass 37, count 2 2006.257.21:51:39.28#ibcon#about to read 6, iclass 37, count 2 2006.257.21:51:39.28#ibcon#read 6, iclass 37, count 2 2006.257.21:51:39.28#ibcon#end of sib2, iclass 37, count 2 2006.257.21:51:39.28#ibcon#*mode == 0, iclass 37, count 2 2006.257.21:51:39.28#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.21:51:39.28#ibcon#[27=AT04-05\r\n] 2006.257.21:51:39.28#ibcon#*before write, iclass 37, count 2 2006.257.21:51:39.28#ibcon#enter sib2, iclass 37, count 2 2006.257.21:51:39.28#ibcon#flushed, iclass 37, count 2 2006.257.21:51:39.28#ibcon#about to write, iclass 37, count 2 2006.257.21:51:39.28#ibcon#wrote, iclass 37, count 2 2006.257.21:51:39.28#ibcon#about to read 3, iclass 37, count 2 2006.257.21:51:39.31#ibcon#read 3, iclass 37, count 2 2006.257.21:51:39.31#ibcon#about to read 4, iclass 37, count 2 2006.257.21:51:39.31#ibcon#read 4, iclass 37, count 2 2006.257.21:51:39.31#ibcon#about to read 5, iclass 37, count 2 2006.257.21:51:39.31#ibcon#read 5, iclass 37, count 2 2006.257.21:51:39.31#ibcon#about to read 6, iclass 37, count 2 2006.257.21:51:39.31#ibcon#read 6, iclass 37, count 2 2006.257.21:51:39.31#ibcon#end of sib2, iclass 37, count 2 2006.257.21:51:39.31#ibcon#*after write, iclass 37, count 2 2006.257.21:51:39.31#ibcon#*before return 0, iclass 37, count 2 2006.257.21:51:39.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:39.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.21:51:39.31#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.21:51:39.31#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:39.31#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:39.43#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:39.43#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:39.43#ibcon#enter wrdev, iclass 37, count 0 2006.257.21:51:39.43#ibcon#first serial, iclass 37, count 0 2006.257.21:51:39.43#ibcon#enter sib2, iclass 37, count 0 2006.257.21:51:39.43#ibcon#flushed, iclass 37, count 0 2006.257.21:51:39.43#ibcon#about to write, iclass 37, count 0 2006.257.21:51:39.43#ibcon#wrote, iclass 37, count 0 2006.257.21:51:39.43#ibcon#about to read 3, iclass 37, count 0 2006.257.21:51:39.45#ibcon#read 3, iclass 37, count 0 2006.257.21:51:39.45#ibcon#about to read 4, iclass 37, count 0 2006.257.21:51:39.45#ibcon#read 4, iclass 37, count 0 2006.257.21:51:39.45#ibcon#about to read 5, iclass 37, count 0 2006.257.21:51:39.45#ibcon#read 5, iclass 37, count 0 2006.257.21:51:39.45#ibcon#about to read 6, iclass 37, count 0 2006.257.21:51:39.45#ibcon#read 6, iclass 37, count 0 2006.257.21:51:39.45#ibcon#end of sib2, iclass 37, count 0 2006.257.21:51:39.45#ibcon#*mode == 0, iclass 37, count 0 2006.257.21:51:39.45#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.21:51:39.45#ibcon#[27=USB\r\n] 2006.257.21:51:39.45#ibcon#*before write, iclass 37, count 0 2006.257.21:51:39.45#ibcon#enter sib2, iclass 37, count 0 2006.257.21:51:39.45#ibcon#flushed, iclass 37, count 0 2006.257.21:51:39.45#ibcon#about to write, iclass 37, count 0 2006.257.21:51:39.45#ibcon#wrote, iclass 37, count 0 2006.257.21:51:39.45#ibcon#about to read 3, iclass 37, count 0 2006.257.21:51:39.48#ibcon#read 3, iclass 37, count 0 2006.257.21:51:39.48#ibcon#about to read 4, iclass 37, count 0 2006.257.21:51:39.48#ibcon#read 4, iclass 37, count 0 2006.257.21:51:39.48#ibcon#about to read 5, iclass 37, count 0 2006.257.21:51:39.48#ibcon#read 5, iclass 37, count 0 2006.257.21:51:39.48#ibcon#about to read 6, iclass 37, count 0 2006.257.21:51:39.48#ibcon#read 6, iclass 37, count 0 2006.257.21:51:39.48#ibcon#end of sib2, iclass 37, count 0 2006.257.21:51:39.48#ibcon#*after write, iclass 37, count 0 2006.257.21:51:39.48#ibcon#*before return 0, iclass 37, count 0 2006.257.21:51:39.48#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:39.48#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.21:51:39.48#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.21:51:39.48#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.21:51:39.48$vck44/vblo=5,709.99 2006.257.21:51:39.48#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.21:51:39.48#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.21:51:39.48#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:39.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:39.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:39.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:39.48#ibcon#enter wrdev, iclass 39, count 0 2006.257.21:51:39.48#ibcon#first serial, iclass 39, count 0 2006.257.21:51:39.48#ibcon#enter sib2, iclass 39, count 0 2006.257.21:51:39.48#ibcon#flushed, iclass 39, count 0 2006.257.21:51:39.48#ibcon#about to write, iclass 39, count 0 2006.257.21:51:39.48#ibcon#wrote, iclass 39, count 0 2006.257.21:51:39.48#ibcon#about to read 3, iclass 39, count 0 2006.257.21:51:39.50#ibcon#read 3, iclass 39, count 0 2006.257.21:51:39.50#ibcon#about to read 4, iclass 39, count 0 2006.257.21:51:39.50#ibcon#read 4, iclass 39, count 0 2006.257.21:51:39.50#ibcon#about to read 5, iclass 39, count 0 2006.257.21:51:39.50#ibcon#read 5, iclass 39, count 0 2006.257.21:51:39.50#ibcon#about to read 6, iclass 39, count 0 2006.257.21:51:39.50#ibcon#read 6, iclass 39, count 0 2006.257.21:51:39.50#ibcon#end of sib2, iclass 39, count 0 2006.257.21:51:39.50#ibcon#*mode == 0, iclass 39, count 0 2006.257.21:51:39.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.21:51:39.50#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.21:51:39.50#ibcon#*before write, iclass 39, count 0 2006.257.21:51:39.50#ibcon#enter sib2, iclass 39, count 0 2006.257.21:51:39.50#ibcon#flushed, iclass 39, count 0 2006.257.21:51:39.50#ibcon#about to write, iclass 39, count 0 2006.257.21:51:39.50#ibcon#wrote, iclass 39, count 0 2006.257.21:51:39.50#ibcon#about to read 3, iclass 39, count 0 2006.257.21:51:39.54#ibcon#read 3, iclass 39, count 0 2006.257.21:51:39.54#ibcon#about to read 4, iclass 39, count 0 2006.257.21:51:39.54#ibcon#read 4, iclass 39, count 0 2006.257.21:51:39.54#ibcon#about to read 5, iclass 39, count 0 2006.257.21:51:39.54#ibcon#read 5, iclass 39, count 0 2006.257.21:51:39.54#ibcon#about to read 6, iclass 39, count 0 2006.257.21:51:39.54#ibcon#read 6, iclass 39, count 0 2006.257.21:51:39.54#ibcon#end of sib2, iclass 39, count 0 2006.257.21:51:39.54#ibcon#*after write, iclass 39, count 0 2006.257.21:51:39.54#ibcon#*before return 0, iclass 39, count 0 2006.257.21:51:39.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:39.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.21:51:39.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.21:51:39.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.21:51:39.54$vck44/vb=5,4 2006.257.21:51:39.54#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.21:51:39.54#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.21:51:39.54#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:39.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:39.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:39.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:39.60#ibcon#enter wrdev, iclass 3, count 2 2006.257.21:51:39.60#ibcon#first serial, iclass 3, count 2 2006.257.21:51:39.60#ibcon#enter sib2, iclass 3, count 2 2006.257.21:51:39.60#ibcon#flushed, iclass 3, count 2 2006.257.21:51:39.60#ibcon#about to write, iclass 3, count 2 2006.257.21:51:39.60#ibcon#wrote, iclass 3, count 2 2006.257.21:51:39.60#ibcon#about to read 3, iclass 3, count 2 2006.257.21:51:39.62#ibcon#read 3, iclass 3, count 2 2006.257.21:51:39.62#ibcon#about to read 4, iclass 3, count 2 2006.257.21:51:39.62#ibcon#read 4, iclass 3, count 2 2006.257.21:51:39.62#ibcon#about to read 5, iclass 3, count 2 2006.257.21:51:39.62#ibcon#read 5, iclass 3, count 2 2006.257.21:51:39.62#ibcon#about to read 6, iclass 3, count 2 2006.257.21:51:39.62#ibcon#read 6, iclass 3, count 2 2006.257.21:51:39.62#ibcon#end of sib2, iclass 3, count 2 2006.257.21:51:39.62#ibcon#*mode == 0, iclass 3, count 2 2006.257.21:51:39.62#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.21:51:39.62#ibcon#[27=AT05-04\r\n] 2006.257.21:51:39.62#ibcon#*before write, iclass 3, count 2 2006.257.21:51:39.62#ibcon#enter sib2, iclass 3, count 2 2006.257.21:51:39.62#ibcon#flushed, iclass 3, count 2 2006.257.21:51:39.62#ibcon#about to write, iclass 3, count 2 2006.257.21:51:39.62#ibcon#wrote, iclass 3, count 2 2006.257.21:51:39.62#ibcon#about to read 3, iclass 3, count 2 2006.257.21:51:39.65#ibcon#read 3, iclass 3, count 2 2006.257.21:51:39.65#ibcon#about to read 4, iclass 3, count 2 2006.257.21:51:39.65#ibcon#read 4, iclass 3, count 2 2006.257.21:51:39.65#ibcon#about to read 5, iclass 3, count 2 2006.257.21:51:39.65#ibcon#read 5, iclass 3, count 2 2006.257.21:51:39.65#ibcon#about to read 6, iclass 3, count 2 2006.257.21:51:39.65#ibcon#read 6, iclass 3, count 2 2006.257.21:51:39.65#ibcon#end of sib2, iclass 3, count 2 2006.257.21:51:39.65#ibcon#*after write, iclass 3, count 2 2006.257.21:51:39.65#ibcon#*before return 0, iclass 3, count 2 2006.257.21:51:39.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:39.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.21:51:39.65#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.21:51:39.65#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:39.65#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:39.77#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:39.77#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:39.77#ibcon#enter wrdev, iclass 3, count 0 2006.257.21:51:39.77#ibcon#first serial, iclass 3, count 0 2006.257.21:51:39.77#ibcon#enter sib2, iclass 3, count 0 2006.257.21:51:39.77#ibcon#flushed, iclass 3, count 0 2006.257.21:51:39.77#ibcon#about to write, iclass 3, count 0 2006.257.21:51:39.77#ibcon#wrote, iclass 3, count 0 2006.257.21:51:39.77#ibcon#about to read 3, iclass 3, count 0 2006.257.21:51:39.79#ibcon#read 3, iclass 3, count 0 2006.257.21:51:39.79#ibcon#about to read 4, iclass 3, count 0 2006.257.21:51:39.79#ibcon#read 4, iclass 3, count 0 2006.257.21:51:39.79#ibcon#about to read 5, iclass 3, count 0 2006.257.21:51:39.79#ibcon#read 5, iclass 3, count 0 2006.257.21:51:39.79#ibcon#about to read 6, iclass 3, count 0 2006.257.21:51:39.79#ibcon#read 6, iclass 3, count 0 2006.257.21:51:39.79#ibcon#end of sib2, iclass 3, count 0 2006.257.21:51:39.79#ibcon#*mode == 0, iclass 3, count 0 2006.257.21:51:39.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.21:51:39.79#ibcon#[27=USB\r\n] 2006.257.21:51:39.79#ibcon#*before write, iclass 3, count 0 2006.257.21:51:39.79#ibcon#enter sib2, iclass 3, count 0 2006.257.21:51:39.79#ibcon#flushed, iclass 3, count 0 2006.257.21:51:39.79#ibcon#about to write, iclass 3, count 0 2006.257.21:51:39.79#ibcon#wrote, iclass 3, count 0 2006.257.21:51:39.79#ibcon#about to read 3, iclass 3, count 0 2006.257.21:51:39.82#ibcon#read 3, iclass 3, count 0 2006.257.21:51:39.82#ibcon#about to read 4, iclass 3, count 0 2006.257.21:51:39.82#ibcon#read 4, iclass 3, count 0 2006.257.21:51:39.82#ibcon#about to read 5, iclass 3, count 0 2006.257.21:51:39.82#ibcon#read 5, iclass 3, count 0 2006.257.21:51:39.82#ibcon#about to read 6, iclass 3, count 0 2006.257.21:51:39.82#ibcon#read 6, iclass 3, count 0 2006.257.21:51:39.82#ibcon#end of sib2, iclass 3, count 0 2006.257.21:51:39.82#ibcon#*after write, iclass 3, count 0 2006.257.21:51:39.82#ibcon#*before return 0, iclass 3, count 0 2006.257.21:51:39.82#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:39.82#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.21:51:39.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.21:51:39.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.21:51:39.82$vck44/vblo=6,719.99 2006.257.21:51:39.82#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.21:51:39.82#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.21:51:39.82#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:39.82#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:39.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:39.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:39.82#ibcon#enter wrdev, iclass 5, count 0 2006.257.21:51:39.82#ibcon#first serial, iclass 5, count 0 2006.257.21:51:39.82#ibcon#enter sib2, iclass 5, count 0 2006.257.21:51:39.82#ibcon#flushed, iclass 5, count 0 2006.257.21:51:39.82#ibcon#about to write, iclass 5, count 0 2006.257.21:51:39.82#ibcon#wrote, iclass 5, count 0 2006.257.21:51:39.82#ibcon#about to read 3, iclass 5, count 0 2006.257.21:51:39.84#ibcon#read 3, iclass 5, count 0 2006.257.21:51:39.84#ibcon#about to read 4, iclass 5, count 0 2006.257.21:51:39.84#ibcon#read 4, iclass 5, count 0 2006.257.21:51:39.84#ibcon#about to read 5, iclass 5, count 0 2006.257.21:51:39.84#ibcon#read 5, iclass 5, count 0 2006.257.21:51:39.84#ibcon#about to read 6, iclass 5, count 0 2006.257.21:51:39.84#ibcon#read 6, iclass 5, count 0 2006.257.21:51:39.84#ibcon#end of sib2, iclass 5, count 0 2006.257.21:51:39.84#ibcon#*mode == 0, iclass 5, count 0 2006.257.21:51:39.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.21:51:39.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.21:51:39.84#ibcon#*before write, iclass 5, count 0 2006.257.21:51:39.84#ibcon#enter sib2, iclass 5, count 0 2006.257.21:51:39.84#ibcon#flushed, iclass 5, count 0 2006.257.21:51:39.84#ibcon#about to write, iclass 5, count 0 2006.257.21:51:39.84#ibcon#wrote, iclass 5, count 0 2006.257.21:51:39.84#ibcon#about to read 3, iclass 5, count 0 2006.257.21:51:39.88#ibcon#read 3, iclass 5, count 0 2006.257.21:51:39.88#ibcon#about to read 4, iclass 5, count 0 2006.257.21:51:39.88#ibcon#read 4, iclass 5, count 0 2006.257.21:51:39.88#ibcon#about to read 5, iclass 5, count 0 2006.257.21:51:39.88#ibcon#read 5, iclass 5, count 0 2006.257.21:51:39.88#ibcon#about to read 6, iclass 5, count 0 2006.257.21:51:39.88#ibcon#read 6, iclass 5, count 0 2006.257.21:51:39.88#ibcon#end of sib2, iclass 5, count 0 2006.257.21:51:39.88#ibcon#*after write, iclass 5, count 0 2006.257.21:51:39.88#ibcon#*before return 0, iclass 5, count 0 2006.257.21:51:39.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:39.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.21:51:39.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.21:51:39.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.21:51:39.88$vck44/vb=6,4 2006.257.21:51:39.88#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.21:51:39.88#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.21:51:39.88#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:39.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:39.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:39.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:39.94#ibcon#enter wrdev, iclass 7, count 2 2006.257.21:51:39.94#ibcon#first serial, iclass 7, count 2 2006.257.21:51:39.94#ibcon#enter sib2, iclass 7, count 2 2006.257.21:51:39.94#ibcon#flushed, iclass 7, count 2 2006.257.21:51:39.94#ibcon#about to write, iclass 7, count 2 2006.257.21:51:39.94#ibcon#wrote, iclass 7, count 2 2006.257.21:51:39.94#ibcon#about to read 3, iclass 7, count 2 2006.257.21:51:39.96#ibcon#read 3, iclass 7, count 2 2006.257.21:51:39.96#ibcon#about to read 4, iclass 7, count 2 2006.257.21:51:39.96#ibcon#read 4, iclass 7, count 2 2006.257.21:51:39.96#ibcon#about to read 5, iclass 7, count 2 2006.257.21:51:39.96#ibcon#read 5, iclass 7, count 2 2006.257.21:51:39.96#ibcon#about to read 6, iclass 7, count 2 2006.257.21:51:39.96#ibcon#read 6, iclass 7, count 2 2006.257.21:51:39.96#ibcon#end of sib2, iclass 7, count 2 2006.257.21:51:39.96#ibcon#*mode == 0, iclass 7, count 2 2006.257.21:51:39.96#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.21:51:39.96#ibcon#[27=AT06-04\r\n] 2006.257.21:51:39.96#ibcon#*before write, iclass 7, count 2 2006.257.21:51:39.96#ibcon#enter sib2, iclass 7, count 2 2006.257.21:51:39.96#ibcon#flushed, iclass 7, count 2 2006.257.21:51:39.96#ibcon#about to write, iclass 7, count 2 2006.257.21:51:39.96#ibcon#wrote, iclass 7, count 2 2006.257.21:51:39.96#ibcon#about to read 3, iclass 7, count 2 2006.257.21:51:39.99#ibcon#read 3, iclass 7, count 2 2006.257.21:51:39.99#ibcon#about to read 4, iclass 7, count 2 2006.257.21:51:39.99#ibcon#read 4, iclass 7, count 2 2006.257.21:51:39.99#ibcon#about to read 5, iclass 7, count 2 2006.257.21:51:39.99#ibcon#read 5, iclass 7, count 2 2006.257.21:51:39.99#ibcon#about to read 6, iclass 7, count 2 2006.257.21:51:39.99#ibcon#read 6, iclass 7, count 2 2006.257.21:51:39.99#ibcon#end of sib2, iclass 7, count 2 2006.257.21:51:39.99#ibcon#*after write, iclass 7, count 2 2006.257.21:51:39.99#ibcon#*before return 0, iclass 7, count 2 2006.257.21:51:39.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:39.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.21:51:39.99#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.21:51:39.99#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:39.99#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:40.11#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:40.11#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:40.11#ibcon#enter wrdev, iclass 7, count 0 2006.257.21:51:40.11#ibcon#first serial, iclass 7, count 0 2006.257.21:51:40.11#ibcon#enter sib2, iclass 7, count 0 2006.257.21:51:40.11#ibcon#flushed, iclass 7, count 0 2006.257.21:51:40.11#ibcon#about to write, iclass 7, count 0 2006.257.21:51:40.11#ibcon#wrote, iclass 7, count 0 2006.257.21:51:40.11#ibcon#about to read 3, iclass 7, count 0 2006.257.21:51:40.12#abcon#<5=/13 0.8 2.0 18.20 931015.5\r\n> 2006.257.21:51:40.13#ibcon#read 3, iclass 7, count 0 2006.257.21:51:40.13#ibcon#about to read 4, iclass 7, count 0 2006.257.21:51:40.13#ibcon#read 4, iclass 7, count 0 2006.257.21:51:40.13#ibcon#about to read 5, iclass 7, count 0 2006.257.21:51:40.13#ibcon#read 5, iclass 7, count 0 2006.257.21:51:40.13#ibcon#about to read 6, iclass 7, count 0 2006.257.21:51:40.13#ibcon#read 6, iclass 7, count 0 2006.257.21:51:40.13#ibcon#end of sib2, iclass 7, count 0 2006.257.21:51:40.13#ibcon#*mode == 0, iclass 7, count 0 2006.257.21:51:40.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.21:51:40.13#ibcon#[27=USB\r\n] 2006.257.21:51:40.13#ibcon#*before write, iclass 7, count 0 2006.257.21:51:40.13#ibcon#enter sib2, iclass 7, count 0 2006.257.21:51:40.13#ibcon#flushed, iclass 7, count 0 2006.257.21:51:40.13#ibcon#about to write, iclass 7, count 0 2006.257.21:51:40.13#ibcon#wrote, iclass 7, count 0 2006.257.21:51:40.13#ibcon#about to read 3, iclass 7, count 0 2006.257.21:51:40.14#abcon#{5=INTERFACE CLEAR} 2006.257.21:51:40.16#ibcon#read 3, iclass 7, count 0 2006.257.21:51:40.16#ibcon#about to read 4, iclass 7, count 0 2006.257.21:51:40.16#ibcon#read 4, iclass 7, count 0 2006.257.21:51:40.16#ibcon#about to read 5, iclass 7, count 0 2006.257.21:51:40.16#ibcon#read 5, iclass 7, count 0 2006.257.21:51:40.16#ibcon#about to read 6, iclass 7, count 0 2006.257.21:51:40.16#ibcon#read 6, iclass 7, count 0 2006.257.21:51:40.16#ibcon#end of sib2, iclass 7, count 0 2006.257.21:51:40.16#ibcon#*after write, iclass 7, count 0 2006.257.21:51:40.16#ibcon#*before return 0, iclass 7, count 0 2006.257.21:51:40.16#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:40.16#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.21:51:40.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.21:51:40.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.21:51:40.16$vck44/vblo=7,734.99 2006.257.21:51:40.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.21:51:40.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.21:51:40.16#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:40.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:51:40.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:51:40.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:51:40.16#ibcon#enter wrdev, iclass 14, count 0 2006.257.21:51:40.16#ibcon#first serial, iclass 14, count 0 2006.257.21:51:40.16#ibcon#enter sib2, iclass 14, count 0 2006.257.21:51:40.16#ibcon#flushed, iclass 14, count 0 2006.257.21:51:40.16#ibcon#about to write, iclass 14, count 0 2006.257.21:51:40.16#ibcon#wrote, iclass 14, count 0 2006.257.21:51:40.16#ibcon#about to read 3, iclass 14, count 0 2006.257.21:51:40.18#ibcon#read 3, iclass 14, count 0 2006.257.21:51:40.18#ibcon#about to read 4, iclass 14, count 0 2006.257.21:51:40.18#ibcon#read 4, iclass 14, count 0 2006.257.21:51:40.18#ibcon#about to read 5, iclass 14, count 0 2006.257.21:51:40.18#ibcon#read 5, iclass 14, count 0 2006.257.21:51:40.18#ibcon#about to read 6, iclass 14, count 0 2006.257.21:51:40.18#ibcon#read 6, iclass 14, count 0 2006.257.21:51:40.18#ibcon#end of sib2, iclass 14, count 0 2006.257.21:51:40.18#ibcon#*mode == 0, iclass 14, count 0 2006.257.21:51:40.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.21:51:40.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.21:51:40.18#ibcon#*before write, iclass 14, count 0 2006.257.21:51:40.18#ibcon#enter sib2, iclass 14, count 0 2006.257.21:51:40.18#ibcon#flushed, iclass 14, count 0 2006.257.21:51:40.18#ibcon#about to write, iclass 14, count 0 2006.257.21:51:40.18#ibcon#wrote, iclass 14, count 0 2006.257.21:51:40.18#ibcon#about to read 3, iclass 14, count 0 2006.257.21:51:40.20#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:51:40.22#ibcon#read 3, iclass 14, count 0 2006.257.21:51:40.22#ibcon#about to read 4, iclass 14, count 0 2006.257.21:51:40.22#ibcon#read 4, iclass 14, count 0 2006.257.21:51:40.22#ibcon#about to read 5, iclass 14, count 0 2006.257.21:51:40.22#ibcon#read 5, iclass 14, count 0 2006.257.21:51:40.22#ibcon#about to read 6, iclass 14, count 0 2006.257.21:51:40.22#ibcon#read 6, iclass 14, count 0 2006.257.21:51:40.22#ibcon#end of sib2, iclass 14, count 0 2006.257.21:51:40.22#ibcon#*after write, iclass 14, count 0 2006.257.21:51:40.22#ibcon#*before return 0, iclass 14, count 0 2006.257.21:51:40.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:51:40.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:51:40.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.21:51:40.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.21:51:40.22$vck44/vb=7,4 2006.257.21:51:40.22#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.21:51:40.22#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.21:51:40.22#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:40.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:40.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:40.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:40.28#ibcon#enter wrdev, iclass 17, count 2 2006.257.21:51:40.28#ibcon#first serial, iclass 17, count 2 2006.257.21:51:40.28#ibcon#enter sib2, iclass 17, count 2 2006.257.21:51:40.28#ibcon#flushed, iclass 17, count 2 2006.257.21:51:40.28#ibcon#about to write, iclass 17, count 2 2006.257.21:51:40.28#ibcon#wrote, iclass 17, count 2 2006.257.21:51:40.28#ibcon#about to read 3, iclass 17, count 2 2006.257.21:51:40.30#ibcon#read 3, iclass 17, count 2 2006.257.21:51:40.30#ibcon#about to read 4, iclass 17, count 2 2006.257.21:51:40.30#ibcon#read 4, iclass 17, count 2 2006.257.21:51:40.30#ibcon#about to read 5, iclass 17, count 2 2006.257.21:51:40.30#ibcon#read 5, iclass 17, count 2 2006.257.21:51:40.30#ibcon#about to read 6, iclass 17, count 2 2006.257.21:51:40.30#ibcon#read 6, iclass 17, count 2 2006.257.21:51:40.30#ibcon#end of sib2, iclass 17, count 2 2006.257.21:51:40.30#ibcon#*mode == 0, iclass 17, count 2 2006.257.21:51:40.30#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.21:51:40.30#ibcon#[27=AT07-04\r\n] 2006.257.21:51:40.30#ibcon#*before write, iclass 17, count 2 2006.257.21:51:40.30#ibcon#enter sib2, iclass 17, count 2 2006.257.21:51:40.30#ibcon#flushed, iclass 17, count 2 2006.257.21:51:40.30#ibcon#about to write, iclass 17, count 2 2006.257.21:51:40.30#ibcon#wrote, iclass 17, count 2 2006.257.21:51:40.30#ibcon#about to read 3, iclass 17, count 2 2006.257.21:51:40.33#ibcon#read 3, iclass 17, count 2 2006.257.21:51:40.33#ibcon#about to read 4, iclass 17, count 2 2006.257.21:51:40.33#ibcon#read 4, iclass 17, count 2 2006.257.21:51:40.33#ibcon#about to read 5, iclass 17, count 2 2006.257.21:51:40.33#ibcon#read 5, iclass 17, count 2 2006.257.21:51:40.33#ibcon#about to read 6, iclass 17, count 2 2006.257.21:51:40.33#ibcon#read 6, iclass 17, count 2 2006.257.21:51:40.33#ibcon#end of sib2, iclass 17, count 2 2006.257.21:51:40.33#ibcon#*after write, iclass 17, count 2 2006.257.21:51:40.33#ibcon#*before return 0, iclass 17, count 2 2006.257.21:51:40.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:40.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.21:51:40.33#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.21:51:40.33#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:40.33#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:40.45#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:40.45#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:40.45#ibcon#enter wrdev, iclass 17, count 0 2006.257.21:51:40.45#ibcon#first serial, iclass 17, count 0 2006.257.21:51:40.45#ibcon#enter sib2, iclass 17, count 0 2006.257.21:51:40.45#ibcon#flushed, iclass 17, count 0 2006.257.21:51:40.45#ibcon#about to write, iclass 17, count 0 2006.257.21:51:40.45#ibcon#wrote, iclass 17, count 0 2006.257.21:51:40.45#ibcon#about to read 3, iclass 17, count 0 2006.257.21:51:40.47#ibcon#read 3, iclass 17, count 0 2006.257.21:51:40.47#ibcon#about to read 4, iclass 17, count 0 2006.257.21:51:40.47#ibcon#read 4, iclass 17, count 0 2006.257.21:51:40.47#ibcon#about to read 5, iclass 17, count 0 2006.257.21:51:40.47#ibcon#read 5, iclass 17, count 0 2006.257.21:51:40.47#ibcon#about to read 6, iclass 17, count 0 2006.257.21:51:40.47#ibcon#read 6, iclass 17, count 0 2006.257.21:51:40.47#ibcon#end of sib2, iclass 17, count 0 2006.257.21:51:40.47#ibcon#*mode == 0, iclass 17, count 0 2006.257.21:51:40.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.21:51:40.47#ibcon#[27=USB\r\n] 2006.257.21:51:40.47#ibcon#*before write, iclass 17, count 0 2006.257.21:51:40.47#ibcon#enter sib2, iclass 17, count 0 2006.257.21:51:40.47#ibcon#flushed, iclass 17, count 0 2006.257.21:51:40.47#ibcon#about to write, iclass 17, count 0 2006.257.21:51:40.47#ibcon#wrote, iclass 17, count 0 2006.257.21:51:40.47#ibcon#about to read 3, iclass 17, count 0 2006.257.21:51:40.50#ibcon#read 3, iclass 17, count 0 2006.257.21:51:40.50#ibcon#about to read 4, iclass 17, count 0 2006.257.21:51:40.50#ibcon#read 4, iclass 17, count 0 2006.257.21:51:40.50#ibcon#about to read 5, iclass 17, count 0 2006.257.21:51:40.50#ibcon#read 5, iclass 17, count 0 2006.257.21:51:40.50#ibcon#about to read 6, iclass 17, count 0 2006.257.21:51:40.50#ibcon#read 6, iclass 17, count 0 2006.257.21:51:40.50#ibcon#end of sib2, iclass 17, count 0 2006.257.21:51:40.50#ibcon#*after write, iclass 17, count 0 2006.257.21:51:40.50#ibcon#*before return 0, iclass 17, count 0 2006.257.21:51:40.50#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:40.50#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.21:51:40.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.21:51:40.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.21:51:40.50$vck44/vblo=8,744.99 2006.257.21:51:40.50#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.21:51:40.50#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.21:51:40.50#ibcon#ireg 17 cls_cnt 0 2006.257.21:51:40.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:40.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:40.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:40.50#ibcon#enter wrdev, iclass 19, count 0 2006.257.21:51:40.50#ibcon#first serial, iclass 19, count 0 2006.257.21:51:40.50#ibcon#enter sib2, iclass 19, count 0 2006.257.21:51:40.50#ibcon#flushed, iclass 19, count 0 2006.257.21:51:40.50#ibcon#about to write, iclass 19, count 0 2006.257.21:51:40.50#ibcon#wrote, iclass 19, count 0 2006.257.21:51:40.50#ibcon#about to read 3, iclass 19, count 0 2006.257.21:51:40.52#ibcon#read 3, iclass 19, count 0 2006.257.21:51:40.52#ibcon#about to read 4, iclass 19, count 0 2006.257.21:51:40.52#ibcon#read 4, iclass 19, count 0 2006.257.21:51:40.52#ibcon#about to read 5, iclass 19, count 0 2006.257.21:51:40.52#ibcon#read 5, iclass 19, count 0 2006.257.21:51:40.52#ibcon#about to read 6, iclass 19, count 0 2006.257.21:51:40.52#ibcon#read 6, iclass 19, count 0 2006.257.21:51:40.52#ibcon#end of sib2, iclass 19, count 0 2006.257.21:51:40.52#ibcon#*mode == 0, iclass 19, count 0 2006.257.21:51:40.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.21:51:40.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.21:51:40.52#ibcon#*before write, iclass 19, count 0 2006.257.21:51:40.52#ibcon#enter sib2, iclass 19, count 0 2006.257.21:51:40.52#ibcon#flushed, iclass 19, count 0 2006.257.21:51:40.52#ibcon#about to write, iclass 19, count 0 2006.257.21:51:40.52#ibcon#wrote, iclass 19, count 0 2006.257.21:51:40.52#ibcon#about to read 3, iclass 19, count 0 2006.257.21:51:40.56#ibcon#read 3, iclass 19, count 0 2006.257.21:51:40.56#ibcon#about to read 4, iclass 19, count 0 2006.257.21:51:40.56#ibcon#read 4, iclass 19, count 0 2006.257.21:51:40.56#ibcon#about to read 5, iclass 19, count 0 2006.257.21:51:40.56#ibcon#read 5, iclass 19, count 0 2006.257.21:51:40.56#ibcon#about to read 6, iclass 19, count 0 2006.257.21:51:40.56#ibcon#read 6, iclass 19, count 0 2006.257.21:51:40.56#ibcon#end of sib2, iclass 19, count 0 2006.257.21:51:40.56#ibcon#*after write, iclass 19, count 0 2006.257.21:51:40.56#ibcon#*before return 0, iclass 19, count 0 2006.257.21:51:40.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:40.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.21:51:40.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.21:51:40.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.21:51:40.56$vck44/vb=8,4 2006.257.21:51:40.56#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.21:51:40.56#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.21:51:40.56#ibcon#ireg 11 cls_cnt 2 2006.257.21:51:40.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:40.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:40.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:40.62#ibcon#enter wrdev, iclass 21, count 2 2006.257.21:51:40.62#ibcon#first serial, iclass 21, count 2 2006.257.21:51:40.62#ibcon#enter sib2, iclass 21, count 2 2006.257.21:51:40.62#ibcon#flushed, iclass 21, count 2 2006.257.21:51:40.62#ibcon#about to write, iclass 21, count 2 2006.257.21:51:40.62#ibcon#wrote, iclass 21, count 2 2006.257.21:51:40.62#ibcon#about to read 3, iclass 21, count 2 2006.257.21:51:40.64#ibcon#read 3, iclass 21, count 2 2006.257.21:51:40.64#ibcon#about to read 4, iclass 21, count 2 2006.257.21:51:40.64#ibcon#read 4, iclass 21, count 2 2006.257.21:51:40.64#ibcon#about to read 5, iclass 21, count 2 2006.257.21:51:40.64#ibcon#read 5, iclass 21, count 2 2006.257.21:51:40.64#ibcon#about to read 6, iclass 21, count 2 2006.257.21:51:40.64#ibcon#read 6, iclass 21, count 2 2006.257.21:51:40.64#ibcon#end of sib2, iclass 21, count 2 2006.257.21:51:40.64#ibcon#*mode == 0, iclass 21, count 2 2006.257.21:51:40.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.21:51:40.64#ibcon#[27=AT08-04\r\n] 2006.257.21:51:40.64#ibcon#*before write, iclass 21, count 2 2006.257.21:51:40.64#ibcon#enter sib2, iclass 21, count 2 2006.257.21:51:40.64#ibcon#flushed, iclass 21, count 2 2006.257.21:51:40.64#ibcon#about to write, iclass 21, count 2 2006.257.21:51:40.64#ibcon#wrote, iclass 21, count 2 2006.257.21:51:40.64#ibcon#about to read 3, iclass 21, count 2 2006.257.21:51:40.67#ibcon#read 3, iclass 21, count 2 2006.257.21:51:40.67#ibcon#about to read 4, iclass 21, count 2 2006.257.21:51:40.67#ibcon#read 4, iclass 21, count 2 2006.257.21:51:40.67#ibcon#about to read 5, iclass 21, count 2 2006.257.21:51:40.67#ibcon#read 5, iclass 21, count 2 2006.257.21:51:40.67#ibcon#about to read 6, iclass 21, count 2 2006.257.21:51:40.67#ibcon#read 6, iclass 21, count 2 2006.257.21:51:40.67#ibcon#end of sib2, iclass 21, count 2 2006.257.21:51:40.67#ibcon#*after write, iclass 21, count 2 2006.257.21:51:40.67#ibcon#*before return 0, iclass 21, count 2 2006.257.21:51:40.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:40.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.21:51:40.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.21:51:40.67#ibcon#ireg 7 cls_cnt 0 2006.257.21:51:40.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:40.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:40.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:40.79#ibcon#enter wrdev, iclass 21, count 0 2006.257.21:51:40.79#ibcon#first serial, iclass 21, count 0 2006.257.21:51:40.79#ibcon#enter sib2, iclass 21, count 0 2006.257.21:51:40.79#ibcon#flushed, iclass 21, count 0 2006.257.21:51:40.79#ibcon#about to write, iclass 21, count 0 2006.257.21:51:40.79#ibcon#wrote, iclass 21, count 0 2006.257.21:51:40.79#ibcon#about to read 3, iclass 21, count 0 2006.257.21:51:40.81#ibcon#read 3, iclass 21, count 0 2006.257.21:51:40.81#ibcon#about to read 4, iclass 21, count 0 2006.257.21:51:40.81#ibcon#read 4, iclass 21, count 0 2006.257.21:51:40.81#ibcon#about to read 5, iclass 21, count 0 2006.257.21:51:40.81#ibcon#read 5, iclass 21, count 0 2006.257.21:51:40.81#ibcon#about to read 6, iclass 21, count 0 2006.257.21:51:40.81#ibcon#read 6, iclass 21, count 0 2006.257.21:51:40.81#ibcon#end of sib2, iclass 21, count 0 2006.257.21:51:40.81#ibcon#*mode == 0, iclass 21, count 0 2006.257.21:51:40.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.21:51:40.81#ibcon#[27=USB\r\n] 2006.257.21:51:40.81#ibcon#*before write, iclass 21, count 0 2006.257.21:51:40.81#ibcon#enter sib2, iclass 21, count 0 2006.257.21:51:40.81#ibcon#flushed, iclass 21, count 0 2006.257.21:51:40.81#ibcon#about to write, iclass 21, count 0 2006.257.21:51:40.81#ibcon#wrote, iclass 21, count 0 2006.257.21:51:40.81#ibcon#about to read 3, iclass 21, count 0 2006.257.21:51:40.84#ibcon#read 3, iclass 21, count 0 2006.257.21:51:40.84#ibcon#about to read 4, iclass 21, count 0 2006.257.21:51:40.84#ibcon#read 4, iclass 21, count 0 2006.257.21:51:40.84#ibcon#about to read 5, iclass 21, count 0 2006.257.21:51:40.84#ibcon#read 5, iclass 21, count 0 2006.257.21:51:40.84#ibcon#about to read 6, iclass 21, count 0 2006.257.21:51:40.84#ibcon#read 6, iclass 21, count 0 2006.257.21:51:40.84#ibcon#end of sib2, iclass 21, count 0 2006.257.21:51:40.84#ibcon#*after write, iclass 21, count 0 2006.257.21:51:40.84#ibcon#*before return 0, iclass 21, count 0 2006.257.21:51:40.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:40.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.21:51:40.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.21:51:40.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.21:51:40.84$vck44/vabw=wide 2006.257.21:51:40.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.21:51:40.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.21:51:40.84#ibcon#ireg 8 cls_cnt 0 2006.257.21:51:40.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:40.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:40.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:40.84#ibcon#enter wrdev, iclass 23, count 0 2006.257.21:51:40.84#ibcon#first serial, iclass 23, count 0 2006.257.21:51:40.84#ibcon#enter sib2, iclass 23, count 0 2006.257.21:51:40.84#ibcon#flushed, iclass 23, count 0 2006.257.21:51:40.84#ibcon#about to write, iclass 23, count 0 2006.257.21:51:40.84#ibcon#wrote, iclass 23, count 0 2006.257.21:51:40.84#ibcon#about to read 3, iclass 23, count 0 2006.257.21:51:40.86#ibcon#read 3, iclass 23, count 0 2006.257.21:51:40.86#ibcon#about to read 4, iclass 23, count 0 2006.257.21:51:40.86#ibcon#read 4, iclass 23, count 0 2006.257.21:51:40.86#ibcon#about to read 5, iclass 23, count 0 2006.257.21:51:40.86#ibcon#read 5, iclass 23, count 0 2006.257.21:51:40.86#ibcon#about to read 6, iclass 23, count 0 2006.257.21:51:40.86#ibcon#read 6, iclass 23, count 0 2006.257.21:51:40.86#ibcon#end of sib2, iclass 23, count 0 2006.257.21:51:40.86#ibcon#*mode == 0, iclass 23, count 0 2006.257.21:51:40.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.21:51:40.86#ibcon#[25=BW32\r\n] 2006.257.21:51:40.86#ibcon#*before write, iclass 23, count 0 2006.257.21:51:40.86#ibcon#enter sib2, iclass 23, count 0 2006.257.21:51:40.86#ibcon#flushed, iclass 23, count 0 2006.257.21:51:40.86#ibcon#about to write, iclass 23, count 0 2006.257.21:51:40.86#ibcon#wrote, iclass 23, count 0 2006.257.21:51:40.86#ibcon#about to read 3, iclass 23, count 0 2006.257.21:51:40.89#ibcon#read 3, iclass 23, count 0 2006.257.21:51:40.89#ibcon#about to read 4, iclass 23, count 0 2006.257.21:51:40.89#ibcon#read 4, iclass 23, count 0 2006.257.21:51:40.89#ibcon#about to read 5, iclass 23, count 0 2006.257.21:51:40.89#ibcon#read 5, iclass 23, count 0 2006.257.21:51:40.89#ibcon#about to read 6, iclass 23, count 0 2006.257.21:51:40.89#ibcon#read 6, iclass 23, count 0 2006.257.21:51:40.89#ibcon#end of sib2, iclass 23, count 0 2006.257.21:51:40.89#ibcon#*after write, iclass 23, count 0 2006.257.21:51:40.89#ibcon#*before return 0, iclass 23, count 0 2006.257.21:51:40.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:40.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.21:51:40.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.21:51:40.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.21:51:40.89$vck44/vbbw=wide 2006.257.21:51:40.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.21:51:40.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.21:51:40.89#ibcon#ireg 8 cls_cnt 0 2006.257.21:51:40.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:51:40.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:51:40.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:51:40.96#ibcon#enter wrdev, iclass 25, count 0 2006.257.21:51:40.96#ibcon#first serial, iclass 25, count 0 2006.257.21:51:40.96#ibcon#enter sib2, iclass 25, count 0 2006.257.21:51:40.96#ibcon#flushed, iclass 25, count 0 2006.257.21:51:40.96#ibcon#about to write, iclass 25, count 0 2006.257.21:51:40.96#ibcon#wrote, iclass 25, count 0 2006.257.21:51:40.96#ibcon#about to read 3, iclass 25, count 0 2006.257.21:51:40.98#ibcon#read 3, iclass 25, count 0 2006.257.21:51:40.98#ibcon#about to read 4, iclass 25, count 0 2006.257.21:51:40.98#ibcon#read 4, iclass 25, count 0 2006.257.21:51:40.98#ibcon#about to read 5, iclass 25, count 0 2006.257.21:51:40.98#ibcon#read 5, iclass 25, count 0 2006.257.21:51:40.98#ibcon#about to read 6, iclass 25, count 0 2006.257.21:51:40.98#ibcon#read 6, iclass 25, count 0 2006.257.21:51:40.98#ibcon#end of sib2, iclass 25, count 0 2006.257.21:51:40.98#ibcon#*mode == 0, iclass 25, count 0 2006.257.21:51:40.98#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.21:51:40.98#ibcon#[27=BW32\r\n] 2006.257.21:51:40.98#ibcon#*before write, iclass 25, count 0 2006.257.21:51:40.98#ibcon#enter sib2, iclass 25, count 0 2006.257.21:51:40.98#ibcon#flushed, iclass 25, count 0 2006.257.21:51:40.98#ibcon#about to write, iclass 25, count 0 2006.257.21:51:40.98#ibcon#wrote, iclass 25, count 0 2006.257.21:51:40.98#ibcon#about to read 3, iclass 25, count 0 2006.257.21:51:41.01#ibcon#read 3, iclass 25, count 0 2006.257.21:51:41.01#ibcon#about to read 4, iclass 25, count 0 2006.257.21:51:41.01#ibcon#read 4, iclass 25, count 0 2006.257.21:51:41.01#ibcon#about to read 5, iclass 25, count 0 2006.257.21:51:41.01#ibcon#read 5, iclass 25, count 0 2006.257.21:51:41.01#ibcon#about to read 6, iclass 25, count 0 2006.257.21:51:41.01#ibcon#read 6, iclass 25, count 0 2006.257.21:51:41.01#ibcon#end of sib2, iclass 25, count 0 2006.257.21:51:41.01#ibcon#*after write, iclass 25, count 0 2006.257.21:51:41.01#ibcon#*before return 0, iclass 25, count 0 2006.257.21:51:41.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:51:41.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.21:51:41.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.21:51:41.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.21:51:41.01$setupk4/ifdk4 2006.257.21:51:41.01$ifdk4/lo= 2006.257.21:51:41.01$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.21:51:41.01$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.21:51:41.01$ifdk4/patch= 2006.257.21:51:41.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.21:51:41.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.21:51:41.01$setupk4/!*+20s 2006.257.21:51:50.29#abcon#<5=/13 0.8 2.0 18.21 931015.4\r\n> 2006.257.21:51:50.31#abcon#{5=INTERFACE CLEAR} 2006.257.21:51:50.37#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:51:55.52$setupk4/"tpicd 2006.257.21:51:55.52$setupk4/echo=off 2006.257.21:51:55.52$setupk4/xlog=off 2006.257.21:51:55.52:!2006.257.21:55:45 2006.257.21:52:05.13#trakl#Source acquired 2006.257.21:52:07.13#flagr#flagr/antenna,acquired 2006.257.21:55:45.00:preob 2006.257.21:55:45.14/onsource/TRACKING 2006.257.21:55:45.14:!2006.257.21:55:55 2006.257.21:55:55.00:"tape 2006.257.21:55:55.00:"st=record 2006.257.21:55:55.00:data_valid=on 2006.257.21:55:55.00:midob 2006.257.21:55:55.14/onsource/TRACKING 2006.257.21:55:55.14/wx/18.42,1015.5,92 2006.257.21:55:55.36/cable/+6.4852E-03 2006.257.21:55:56.45/va/01,08,usb,yes,37,40 2006.257.21:55:56.45/va/02,07,usb,yes,40,41 2006.257.21:55:56.45/va/03,08,usb,yes,36,38 2006.257.21:55:56.45/va/04,07,usb,yes,41,43 2006.257.21:55:56.45/va/05,04,usb,yes,37,38 2006.257.21:55:56.45/va/06,04,usb,yes,41,41 2006.257.21:55:56.45/va/07,04,usb,yes,42,43 2006.257.21:55:56.45/va/08,04,usb,yes,35,43 2006.257.21:55:56.68/valo/01,524.99,yes,locked 2006.257.21:55:56.68/valo/02,534.99,yes,locked 2006.257.21:55:56.68/valo/03,564.99,yes,locked 2006.257.21:55:56.68/valo/04,624.99,yes,locked 2006.257.21:55:56.68/valo/05,734.99,yes,locked 2006.257.21:55:56.68/valo/06,814.99,yes,locked 2006.257.21:55:56.68/valo/07,864.99,yes,locked 2006.257.21:55:56.68/valo/08,884.99,yes,locked 2006.257.21:55:57.77/vb/01,04,usb,yes,35,32 2006.257.21:55:57.77/vb/02,05,usb,yes,33,33 2006.257.21:55:57.77/vb/03,04,usb,yes,34,37 2006.257.21:55:57.77/vb/04,05,usb,yes,34,33 2006.257.21:55:57.77/vb/05,04,usb,yes,30,33 2006.257.21:55:57.77/vb/06,04,usb,yes,36,31 2006.257.21:55:57.77/vb/07,04,usb,yes,35,35 2006.257.21:55:57.77/vb/08,04,usb,yes,32,36 2006.257.21:55:58.01/vblo/01,629.99,yes,locked 2006.257.21:55:58.01/vblo/02,634.99,yes,locked 2006.257.21:55:58.01/vblo/03,649.99,yes,locked 2006.257.21:55:58.01/vblo/04,679.99,yes,locked 2006.257.21:55:58.01/vblo/05,709.99,yes,locked 2006.257.21:55:58.01/vblo/06,719.99,yes,locked 2006.257.21:55:58.01/vblo/07,734.99,yes,locked 2006.257.21:55:58.01/vblo/08,744.99,yes,locked 2006.257.21:55:58.16/vabw/8 2006.257.21:55:58.31/vbbw/8 2006.257.21:55:58.40/xfe/off,on,15.2 2006.257.21:55:58.77/ifatt/23,28,28,28 2006.257.21:55:59.07/fmout-gps/S +4.46E-07 2006.257.21:55:59.11:!2006.257.21:56:35 2006.257.21:56:35.00:data_valid=off 2006.257.21:56:35.00:"et 2006.257.21:56:35.00:!+3s 2006.257.21:56:38.01:"tape 2006.257.21:56:38.01:postob 2006.257.21:56:38.23/cable/+6.4868E-03 2006.257.21:56:38.23/wx/18.44,1015.5,91 2006.257.21:56:39.07/fmout-gps/S +4.47E-07 2006.257.21:56:39.07:scan_name=257-2204,jd0609,320 2006.257.21:56:39.07:source=nrao150,035929.75,505750.2,2000.0,cw 2006.257.21:56:40.14#flagr#flagr/antenna,new-source 2006.257.21:56:40.14:checkk5 2006.257.21:56:40.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.21:56:40.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.21:56:41.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.21:56:41.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.21:56:41.84/chk_obsdata//k5ts1/T2572155??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.21:56:42.18/chk_obsdata//k5ts2/T2572155??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.21:56:42.52/chk_obsdata//k5ts3/T2572155??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.21:56:42.85/chk_obsdata//k5ts4/T2572155??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.257.21:56:43.52/k5log//k5ts1_log_newline 2006.257.21:56:44.19/k5log//k5ts2_log_newline 2006.257.21:56:44.84/k5log//k5ts3_log_newline 2006.257.21:56:45.50/k5log//k5ts4_log_newline 2006.257.21:56:45.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.21:56:45.52:setupk4=1 2006.257.21:56:45.52$setupk4/echo=on 2006.257.21:56:45.52$setupk4/pcalon 2006.257.21:56:45.52$pcalon/"no phase cal control is implemented here 2006.257.21:56:45.52$setupk4/"tpicd=stop 2006.257.21:56:45.52$setupk4/"rec=synch_on 2006.257.21:56:45.52$setupk4/"rec_mode=128 2006.257.21:56:45.52$setupk4/!* 2006.257.21:56:45.52$setupk4/recpk4 2006.257.21:56:45.52$recpk4/recpatch= 2006.257.21:56:45.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.21:56:45.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.21:56:45.53$setupk4/vck44 2006.257.21:56:45.53$vck44/valo=1,524.99 2006.257.21:56:45.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.21:56:45.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.21:56:45.53#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:45.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:45.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:45.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:45.53#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:56:45.53#ibcon#first serial, iclass 4, count 0 2006.257.21:56:45.53#ibcon#enter sib2, iclass 4, count 0 2006.257.21:56:45.53#ibcon#flushed, iclass 4, count 0 2006.257.21:56:45.53#ibcon#about to write, iclass 4, count 0 2006.257.21:56:45.53#ibcon#wrote, iclass 4, count 0 2006.257.21:56:45.53#ibcon#about to read 3, iclass 4, count 0 2006.257.21:56:45.54#ibcon#read 3, iclass 4, count 0 2006.257.21:56:45.54#ibcon#about to read 4, iclass 4, count 0 2006.257.21:56:45.54#ibcon#read 4, iclass 4, count 0 2006.257.21:56:45.54#ibcon#about to read 5, iclass 4, count 0 2006.257.21:56:45.54#ibcon#read 5, iclass 4, count 0 2006.257.21:56:45.54#ibcon#about to read 6, iclass 4, count 0 2006.257.21:56:45.54#ibcon#read 6, iclass 4, count 0 2006.257.21:56:45.54#ibcon#end of sib2, iclass 4, count 0 2006.257.21:56:45.54#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:56:45.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:56:45.54#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.21:56:45.54#ibcon#*before write, iclass 4, count 0 2006.257.21:56:45.54#ibcon#enter sib2, iclass 4, count 0 2006.257.21:56:45.54#ibcon#flushed, iclass 4, count 0 2006.257.21:56:45.54#ibcon#about to write, iclass 4, count 0 2006.257.21:56:45.54#ibcon#wrote, iclass 4, count 0 2006.257.21:56:45.54#ibcon#about to read 3, iclass 4, count 0 2006.257.21:56:45.59#ibcon#read 3, iclass 4, count 0 2006.257.21:56:45.59#ibcon#about to read 4, iclass 4, count 0 2006.257.21:56:45.59#ibcon#read 4, iclass 4, count 0 2006.257.21:56:45.59#ibcon#about to read 5, iclass 4, count 0 2006.257.21:56:45.59#ibcon#read 5, iclass 4, count 0 2006.257.21:56:45.59#ibcon#about to read 6, iclass 4, count 0 2006.257.21:56:45.59#ibcon#read 6, iclass 4, count 0 2006.257.21:56:45.59#ibcon#end of sib2, iclass 4, count 0 2006.257.21:56:45.59#ibcon#*after write, iclass 4, count 0 2006.257.21:56:45.59#ibcon#*before return 0, iclass 4, count 0 2006.257.21:56:45.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:45.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:45.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:56:45.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:56:45.59$vck44/va=1,8 2006.257.21:56:45.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.21:56:45.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.21:56:45.59#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:45.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:45.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:45.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:45.59#ibcon#enter wrdev, iclass 6, count 2 2006.257.21:56:45.59#ibcon#first serial, iclass 6, count 2 2006.257.21:56:45.59#ibcon#enter sib2, iclass 6, count 2 2006.257.21:56:45.59#ibcon#flushed, iclass 6, count 2 2006.257.21:56:45.59#ibcon#about to write, iclass 6, count 2 2006.257.21:56:45.59#ibcon#wrote, iclass 6, count 2 2006.257.21:56:45.59#ibcon#about to read 3, iclass 6, count 2 2006.257.21:56:45.61#ibcon#read 3, iclass 6, count 2 2006.257.21:56:45.61#ibcon#about to read 4, iclass 6, count 2 2006.257.21:56:45.61#ibcon#read 4, iclass 6, count 2 2006.257.21:56:45.61#ibcon#about to read 5, iclass 6, count 2 2006.257.21:56:45.61#ibcon#read 5, iclass 6, count 2 2006.257.21:56:45.61#ibcon#about to read 6, iclass 6, count 2 2006.257.21:56:45.61#ibcon#read 6, iclass 6, count 2 2006.257.21:56:45.61#ibcon#end of sib2, iclass 6, count 2 2006.257.21:56:45.61#ibcon#*mode == 0, iclass 6, count 2 2006.257.21:56:45.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.21:56:45.61#ibcon#[25=AT01-08\r\n] 2006.257.21:56:45.61#ibcon#*before write, iclass 6, count 2 2006.257.21:56:45.61#ibcon#enter sib2, iclass 6, count 2 2006.257.21:56:45.61#ibcon#flushed, iclass 6, count 2 2006.257.21:56:45.61#ibcon#about to write, iclass 6, count 2 2006.257.21:56:45.61#ibcon#wrote, iclass 6, count 2 2006.257.21:56:45.61#ibcon#about to read 3, iclass 6, count 2 2006.257.21:56:45.64#ibcon#read 3, iclass 6, count 2 2006.257.21:56:45.64#ibcon#about to read 4, iclass 6, count 2 2006.257.21:56:45.64#ibcon#read 4, iclass 6, count 2 2006.257.21:56:45.64#ibcon#about to read 5, iclass 6, count 2 2006.257.21:56:45.64#ibcon#read 5, iclass 6, count 2 2006.257.21:56:45.64#ibcon#about to read 6, iclass 6, count 2 2006.257.21:56:45.64#ibcon#read 6, iclass 6, count 2 2006.257.21:56:45.64#ibcon#end of sib2, iclass 6, count 2 2006.257.21:56:45.64#ibcon#*after write, iclass 6, count 2 2006.257.21:56:45.64#ibcon#*before return 0, iclass 6, count 2 2006.257.21:56:45.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:45.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:45.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.21:56:45.64#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:45.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:45.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:45.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:45.76#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:56:45.76#ibcon#first serial, iclass 6, count 0 2006.257.21:56:45.76#ibcon#enter sib2, iclass 6, count 0 2006.257.21:56:45.76#ibcon#flushed, iclass 6, count 0 2006.257.21:56:45.76#ibcon#about to write, iclass 6, count 0 2006.257.21:56:45.76#ibcon#wrote, iclass 6, count 0 2006.257.21:56:45.76#ibcon#about to read 3, iclass 6, count 0 2006.257.21:56:45.78#ibcon#read 3, iclass 6, count 0 2006.257.21:56:45.78#ibcon#about to read 4, iclass 6, count 0 2006.257.21:56:45.78#ibcon#read 4, iclass 6, count 0 2006.257.21:56:45.78#ibcon#about to read 5, iclass 6, count 0 2006.257.21:56:45.78#ibcon#read 5, iclass 6, count 0 2006.257.21:56:45.78#ibcon#about to read 6, iclass 6, count 0 2006.257.21:56:45.78#ibcon#read 6, iclass 6, count 0 2006.257.21:56:45.78#ibcon#end of sib2, iclass 6, count 0 2006.257.21:56:45.78#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:56:45.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:56:45.78#ibcon#[25=USB\r\n] 2006.257.21:56:45.78#ibcon#*before write, iclass 6, count 0 2006.257.21:56:45.78#ibcon#enter sib2, iclass 6, count 0 2006.257.21:56:45.78#ibcon#flushed, iclass 6, count 0 2006.257.21:56:45.78#ibcon#about to write, iclass 6, count 0 2006.257.21:56:45.78#ibcon#wrote, iclass 6, count 0 2006.257.21:56:45.78#ibcon#about to read 3, iclass 6, count 0 2006.257.21:56:45.81#ibcon#read 3, iclass 6, count 0 2006.257.21:56:45.81#ibcon#about to read 4, iclass 6, count 0 2006.257.21:56:45.81#ibcon#read 4, iclass 6, count 0 2006.257.21:56:45.81#ibcon#about to read 5, iclass 6, count 0 2006.257.21:56:45.81#ibcon#read 5, iclass 6, count 0 2006.257.21:56:45.81#ibcon#about to read 6, iclass 6, count 0 2006.257.21:56:45.81#ibcon#read 6, iclass 6, count 0 2006.257.21:56:45.81#ibcon#end of sib2, iclass 6, count 0 2006.257.21:56:45.81#ibcon#*after write, iclass 6, count 0 2006.257.21:56:45.81#ibcon#*before return 0, iclass 6, count 0 2006.257.21:56:45.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:45.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:45.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:56:45.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:56:45.81$vck44/valo=2,534.99 2006.257.21:56:45.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.21:56:45.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.21:56:45.81#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:45.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:45.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:45.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:45.81#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:56:45.81#ibcon#first serial, iclass 10, count 0 2006.257.21:56:45.81#ibcon#enter sib2, iclass 10, count 0 2006.257.21:56:45.81#ibcon#flushed, iclass 10, count 0 2006.257.21:56:45.81#ibcon#about to write, iclass 10, count 0 2006.257.21:56:45.81#ibcon#wrote, iclass 10, count 0 2006.257.21:56:45.81#ibcon#about to read 3, iclass 10, count 0 2006.257.21:56:45.83#ibcon#read 3, iclass 10, count 0 2006.257.21:56:45.83#ibcon#about to read 4, iclass 10, count 0 2006.257.21:56:45.83#ibcon#read 4, iclass 10, count 0 2006.257.21:56:45.83#ibcon#about to read 5, iclass 10, count 0 2006.257.21:56:45.83#ibcon#read 5, iclass 10, count 0 2006.257.21:56:45.83#ibcon#about to read 6, iclass 10, count 0 2006.257.21:56:45.83#ibcon#read 6, iclass 10, count 0 2006.257.21:56:45.83#ibcon#end of sib2, iclass 10, count 0 2006.257.21:56:45.83#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:56:45.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:56:45.83#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.21:56:45.83#ibcon#*before write, iclass 10, count 0 2006.257.21:56:45.83#ibcon#enter sib2, iclass 10, count 0 2006.257.21:56:45.83#ibcon#flushed, iclass 10, count 0 2006.257.21:56:45.83#ibcon#about to write, iclass 10, count 0 2006.257.21:56:45.83#ibcon#wrote, iclass 10, count 0 2006.257.21:56:45.83#ibcon#about to read 3, iclass 10, count 0 2006.257.21:56:45.87#ibcon#read 3, iclass 10, count 0 2006.257.21:56:45.87#ibcon#about to read 4, iclass 10, count 0 2006.257.21:56:45.87#ibcon#read 4, iclass 10, count 0 2006.257.21:56:45.87#ibcon#about to read 5, iclass 10, count 0 2006.257.21:56:45.87#ibcon#read 5, iclass 10, count 0 2006.257.21:56:45.87#ibcon#about to read 6, iclass 10, count 0 2006.257.21:56:45.87#ibcon#read 6, iclass 10, count 0 2006.257.21:56:45.87#ibcon#end of sib2, iclass 10, count 0 2006.257.21:56:45.87#ibcon#*after write, iclass 10, count 0 2006.257.21:56:45.87#ibcon#*before return 0, iclass 10, count 0 2006.257.21:56:45.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:45.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:45.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:56:45.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:56:45.87$vck44/va=2,7 2006.257.21:56:45.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.21:56:45.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.21:56:45.87#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:45.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:45.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:45.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:45.93#ibcon#enter wrdev, iclass 12, count 2 2006.257.21:56:45.93#ibcon#first serial, iclass 12, count 2 2006.257.21:56:45.93#ibcon#enter sib2, iclass 12, count 2 2006.257.21:56:45.93#ibcon#flushed, iclass 12, count 2 2006.257.21:56:45.93#ibcon#about to write, iclass 12, count 2 2006.257.21:56:45.93#ibcon#wrote, iclass 12, count 2 2006.257.21:56:45.93#ibcon#about to read 3, iclass 12, count 2 2006.257.21:56:45.95#ibcon#read 3, iclass 12, count 2 2006.257.21:56:45.95#ibcon#about to read 4, iclass 12, count 2 2006.257.21:56:45.95#ibcon#read 4, iclass 12, count 2 2006.257.21:56:45.95#ibcon#about to read 5, iclass 12, count 2 2006.257.21:56:45.95#ibcon#read 5, iclass 12, count 2 2006.257.21:56:45.95#ibcon#about to read 6, iclass 12, count 2 2006.257.21:56:45.95#ibcon#read 6, iclass 12, count 2 2006.257.21:56:45.95#ibcon#end of sib2, iclass 12, count 2 2006.257.21:56:45.95#ibcon#*mode == 0, iclass 12, count 2 2006.257.21:56:45.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.21:56:45.95#ibcon#[25=AT02-07\r\n] 2006.257.21:56:45.95#ibcon#*before write, iclass 12, count 2 2006.257.21:56:45.95#ibcon#enter sib2, iclass 12, count 2 2006.257.21:56:45.95#ibcon#flushed, iclass 12, count 2 2006.257.21:56:45.95#ibcon#about to write, iclass 12, count 2 2006.257.21:56:45.95#ibcon#wrote, iclass 12, count 2 2006.257.21:56:45.95#ibcon#about to read 3, iclass 12, count 2 2006.257.21:56:45.98#ibcon#read 3, iclass 12, count 2 2006.257.21:56:45.98#ibcon#about to read 4, iclass 12, count 2 2006.257.21:56:45.98#ibcon#read 4, iclass 12, count 2 2006.257.21:56:45.98#ibcon#about to read 5, iclass 12, count 2 2006.257.21:56:45.98#ibcon#read 5, iclass 12, count 2 2006.257.21:56:45.98#ibcon#about to read 6, iclass 12, count 2 2006.257.21:56:45.98#ibcon#read 6, iclass 12, count 2 2006.257.21:56:45.98#ibcon#end of sib2, iclass 12, count 2 2006.257.21:56:45.98#ibcon#*after write, iclass 12, count 2 2006.257.21:56:45.98#ibcon#*before return 0, iclass 12, count 2 2006.257.21:56:45.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:45.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:45.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.21:56:45.98#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:45.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:46.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:46.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:46.10#ibcon#enter wrdev, iclass 12, count 0 2006.257.21:56:46.10#ibcon#first serial, iclass 12, count 0 2006.257.21:56:46.10#ibcon#enter sib2, iclass 12, count 0 2006.257.21:56:46.10#ibcon#flushed, iclass 12, count 0 2006.257.21:56:46.10#ibcon#about to write, iclass 12, count 0 2006.257.21:56:46.10#ibcon#wrote, iclass 12, count 0 2006.257.21:56:46.10#ibcon#about to read 3, iclass 12, count 0 2006.257.21:56:46.12#ibcon#read 3, iclass 12, count 0 2006.257.21:56:46.12#ibcon#about to read 4, iclass 12, count 0 2006.257.21:56:46.12#ibcon#read 4, iclass 12, count 0 2006.257.21:56:46.12#ibcon#about to read 5, iclass 12, count 0 2006.257.21:56:46.12#ibcon#read 5, iclass 12, count 0 2006.257.21:56:46.12#ibcon#about to read 6, iclass 12, count 0 2006.257.21:56:46.12#ibcon#read 6, iclass 12, count 0 2006.257.21:56:46.12#ibcon#end of sib2, iclass 12, count 0 2006.257.21:56:46.12#ibcon#*mode == 0, iclass 12, count 0 2006.257.21:56:46.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.21:56:46.12#ibcon#[25=USB\r\n] 2006.257.21:56:46.12#ibcon#*before write, iclass 12, count 0 2006.257.21:56:46.12#ibcon#enter sib2, iclass 12, count 0 2006.257.21:56:46.12#ibcon#flushed, iclass 12, count 0 2006.257.21:56:46.12#ibcon#about to write, iclass 12, count 0 2006.257.21:56:46.12#ibcon#wrote, iclass 12, count 0 2006.257.21:56:46.12#ibcon#about to read 3, iclass 12, count 0 2006.257.21:56:46.15#ibcon#read 3, iclass 12, count 0 2006.257.21:56:46.15#ibcon#about to read 4, iclass 12, count 0 2006.257.21:56:46.15#ibcon#read 4, iclass 12, count 0 2006.257.21:56:46.15#ibcon#about to read 5, iclass 12, count 0 2006.257.21:56:46.15#ibcon#read 5, iclass 12, count 0 2006.257.21:56:46.15#ibcon#about to read 6, iclass 12, count 0 2006.257.21:56:46.15#ibcon#read 6, iclass 12, count 0 2006.257.21:56:46.15#ibcon#end of sib2, iclass 12, count 0 2006.257.21:56:46.15#ibcon#*after write, iclass 12, count 0 2006.257.21:56:46.15#ibcon#*before return 0, iclass 12, count 0 2006.257.21:56:46.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:46.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:46.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.21:56:46.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.21:56:46.15$vck44/valo=3,564.99 2006.257.21:56:46.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.21:56:46.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.21:56:46.15#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:46.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:46.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:46.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:46.15#ibcon#enter wrdev, iclass 14, count 0 2006.257.21:56:46.15#ibcon#first serial, iclass 14, count 0 2006.257.21:56:46.15#ibcon#enter sib2, iclass 14, count 0 2006.257.21:56:46.15#ibcon#flushed, iclass 14, count 0 2006.257.21:56:46.15#ibcon#about to write, iclass 14, count 0 2006.257.21:56:46.15#ibcon#wrote, iclass 14, count 0 2006.257.21:56:46.15#ibcon#about to read 3, iclass 14, count 0 2006.257.21:56:46.17#ibcon#read 3, iclass 14, count 0 2006.257.21:56:46.17#ibcon#about to read 4, iclass 14, count 0 2006.257.21:56:46.17#ibcon#read 4, iclass 14, count 0 2006.257.21:56:46.17#ibcon#about to read 5, iclass 14, count 0 2006.257.21:56:46.17#ibcon#read 5, iclass 14, count 0 2006.257.21:56:46.17#ibcon#about to read 6, iclass 14, count 0 2006.257.21:56:46.17#ibcon#read 6, iclass 14, count 0 2006.257.21:56:46.17#ibcon#end of sib2, iclass 14, count 0 2006.257.21:56:46.17#ibcon#*mode == 0, iclass 14, count 0 2006.257.21:56:46.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.21:56:46.17#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.21:56:46.17#ibcon#*before write, iclass 14, count 0 2006.257.21:56:46.17#ibcon#enter sib2, iclass 14, count 0 2006.257.21:56:46.17#ibcon#flushed, iclass 14, count 0 2006.257.21:56:46.17#ibcon#about to write, iclass 14, count 0 2006.257.21:56:46.17#ibcon#wrote, iclass 14, count 0 2006.257.21:56:46.17#ibcon#about to read 3, iclass 14, count 0 2006.257.21:56:46.21#ibcon#read 3, iclass 14, count 0 2006.257.21:56:46.21#ibcon#about to read 4, iclass 14, count 0 2006.257.21:56:46.21#ibcon#read 4, iclass 14, count 0 2006.257.21:56:46.21#ibcon#about to read 5, iclass 14, count 0 2006.257.21:56:46.21#ibcon#read 5, iclass 14, count 0 2006.257.21:56:46.21#ibcon#about to read 6, iclass 14, count 0 2006.257.21:56:46.21#ibcon#read 6, iclass 14, count 0 2006.257.21:56:46.21#ibcon#end of sib2, iclass 14, count 0 2006.257.21:56:46.21#ibcon#*after write, iclass 14, count 0 2006.257.21:56:46.21#ibcon#*before return 0, iclass 14, count 0 2006.257.21:56:46.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:46.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:46.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.21:56:46.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.21:56:46.21$vck44/va=3,8 2006.257.21:56:46.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.21:56:46.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.21:56:46.21#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:46.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:46.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:46.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:46.27#ibcon#enter wrdev, iclass 16, count 2 2006.257.21:56:46.27#ibcon#first serial, iclass 16, count 2 2006.257.21:56:46.27#ibcon#enter sib2, iclass 16, count 2 2006.257.21:56:46.27#ibcon#flushed, iclass 16, count 2 2006.257.21:56:46.27#ibcon#about to write, iclass 16, count 2 2006.257.21:56:46.27#ibcon#wrote, iclass 16, count 2 2006.257.21:56:46.27#ibcon#about to read 3, iclass 16, count 2 2006.257.21:56:46.29#ibcon#read 3, iclass 16, count 2 2006.257.21:56:46.29#ibcon#about to read 4, iclass 16, count 2 2006.257.21:56:46.29#ibcon#read 4, iclass 16, count 2 2006.257.21:56:46.29#ibcon#about to read 5, iclass 16, count 2 2006.257.21:56:46.29#ibcon#read 5, iclass 16, count 2 2006.257.21:56:46.29#ibcon#about to read 6, iclass 16, count 2 2006.257.21:56:46.29#ibcon#read 6, iclass 16, count 2 2006.257.21:56:46.29#ibcon#end of sib2, iclass 16, count 2 2006.257.21:56:46.29#ibcon#*mode == 0, iclass 16, count 2 2006.257.21:56:46.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.21:56:46.29#ibcon#[25=AT03-08\r\n] 2006.257.21:56:46.29#ibcon#*before write, iclass 16, count 2 2006.257.21:56:46.29#ibcon#enter sib2, iclass 16, count 2 2006.257.21:56:46.29#ibcon#flushed, iclass 16, count 2 2006.257.21:56:46.29#ibcon#about to write, iclass 16, count 2 2006.257.21:56:46.29#ibcon#wrote, iclass 16, count 2 2006.257.21:56:46.29#ibcon#about to read 3, iclass 16, count 2 2006.257.21:56:46.32#ibcon#read 3, iclass 16, count 2 2006.257.21:56:46.32#ibcon#about to read 4, iclass 16, count 2 2006.257.21:56:46.32#ibcon#read 4, iclass 16, count 2 2006.257.21:56:46.32#ibcon#about to read 5, iclass 16, count 2 2006.257.21:56:46.32#ibcon#read 5, iclass 16, count 2 2006.257.21:56:46.32#ibcon#about to read 6, iclass 16, count 2 2006.257.21:56:46.32#ibcon#read 6, iclass 16, count 2 2006.257.21:56:46.32#ibcon#end of sib2, iclass 16, count 2 2006.257.21:56:46.32#ibcon#*after write, iclass 16, count 2 2006.257.21:56:46.32#ibcon#*before return 0, iclass 16, count 2 2006.257.21:56:46.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:46.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:46.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.21:56:46.32#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:46.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:46.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:46.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:46.44#ibcon#enter wrdev, iclass 16, count 0 2006.257.21:56:46.44#ibcon#first serial, iclass 16, count 0 2006.257.21:56:46.44#ibcon#enter sib2, iclass 16, count 0 2006.257.21:56:46.44#ibcon#flushed, iclass 16, count 0 2006.257.21:56:46.44#ibcon#about to write, iclass 16, count 0 2006.257.21:56:46.44#ibcon#wrote, iclass 16, count 0 2006.257.21:56:46.44#ibcon#about to read 3, iclass 16, count 0 2006.257.21:56:46.46#ibcon#read 3, iclass 16, count 0 2006.257.21:56:46.46#ibcon#about to read 4, iclass 16, count 0 2006.257.21:56:46.46#ibcon#read 4, iclass 16, count 0 2006.257.21:56:46.46#ibcon#about to read 5, iclass 16, count 0 2006.257.21:56:46.46#ibcon#read 5, iclass 16, count 0 2006.257.21:56:46.46#ibcon#about to read 6, iclass 16, count 0 2006.257.21:56:46.46#ibcon#read 6, iclass 16, count 0 2006.257.21:56:46.46#ibcon#end of sib2, iclass 16, count 0 2006.257.21:56:46.46#ibcon#*mode == 0, iclass 16, count 0 2006.257.21:56:46.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.21:56:46.46#ibcon#[25=USB\r\n] 2006.257.21:56:46.46#ibcon#*before write, iclass 16, count 0 2006.257.21:56:46.46#ibcon#enter sib2, iclass 16, count 0 2006.257.21:56:46.46#ibcon#flushed, iclass 16, count 0 2006.257.21:56:46.46#ibcon#about to write, iclass 16, count 0 2006.257.21:56:46.46#ibcon#wrote, iclass 16, count 0 2006.257.21:56:46.46#ibcon#about to read 3, iclass 16, count 0 2006.257.21:56:46.49#ibcon#read 3, iclass 16, count 0 2006.257.21:56:46.49#ibcon#about to read 4, iclass 16, count 0 2006.257.21:56:46.49#ibcon#read 4, iclass 16, count 0 2006.257.21:56:46.49#ibcon#about to read 5, iclass 16, count 0 2006.257.21:56:46.49#ibcon#read 5, iclass 16, count 0 2006.257.21:56:46.49#ibcon#about to read 6, iclass 16, count 0 2006.257.21:56:46.49#ibcon#read 6, iclass 16, count 0 2006.257.21:56:46.49#ibcon#end of sib2, iclass 16, count 0 2006.257.21:56:46.49#ibcon#*after write, iclass 16, count 0 2006.257.21:56:46.49#ibcon#*before return 0, iclass 16, count 0 2006.257.21:56:46.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:46.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:46.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.21:56:46.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.21:56:46.49$vck44/valo=4,624.99 2006.257.21:56:46.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.21:56:46.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.21:56:46.49#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:46.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:46.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:46.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:46.49#ibcon#enter wrdev, iclass 18, count 0 2006.257.21:56:46.49#ibcon#first serial, iclass 18, count 0 2006.257.21:56:46.49#ibcon#enter sib2, iclass 18, count 0 2006.257.21:56:46.49#ibcon#flushed, iclass 18, count 0 2006.257.21:56:46.49#ibcon#about to write, iclass 18, count 0 2006.257.21:56:46.49#ibcon#wrote, iclass 18, count 0 2006.257.21:56:46.49#ibcon#about to read 3, iclass 18, count 0 2006.257.21:56:46.51#ibcon#read 3, iclass 18, count 0 2006.257.21:56:46.51#ibcon#about to read 4, iclass 18, count 0 2006.257.21:56:46.51#ibcon#read 4, iclass 18, count 0 2006.257.21:56:46.51#ibcon#about to read 5, iclass 18, count 0 2006.257.21:56:46.51#ibcon#read 5, iclass 18, count 0 2006.257.21:56:46.51#ibcon#about to read 6, iclass 18, count 0 2006.257.21:56:46.51#ibcon#read 6, iclass 18, count 0 2006.257.21:56:46.51#ibcon#end of sib2, iclass 18, count 0 2006.257.21:56:46.51#ibcon#*mode == 0, iclass 18, count 0 2006.257.21:56:46.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.21:56:46.51#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.21:56:46.51#ibcon#*before write, iclass 18, count 0 2006.257.21:56:46.51#ibcon#enter sib2, iclass 18, count 0 2006.257.21:56:46.51#ibcon#flushed, iclass 18, count 0 2006.257.21:56:46.51#ibcon#about to write, iclass 18, count 0 2006.257.21:56:46.51#ibcon#wrote, iclass 18, count 0 2006.257.21:56:46.51#ibcon#about to read 3, iclass 18, count 0 2006.257.21:56:46.55#ibcon#read 3, iclass 18, count 0 2006.257.21:56:46.55#ibcon#about to read 4, iclass 18, count 0 2006.257.21:56:46.55#ibcon#read 4, iclass 18, count 0 2006.257.21:56:46.55#ibcon#about to read 5, iclass 18, count 0 2006.257.21:56:46.55#ibcon#read 5, iclass 18, count 0 2006.257.21:56:46.55#ibcon#about to read 6, iclass 18, count 0 2006.257.21:56:46.55#ibcon#read 6, iclass 18, count 0 2006.257.21:56:46.55#ibcon#end of sib2, iclass 18, count 0 2006.257.21:56:46.55#ibcon#*after write, iclass 18, count 0 2006.257.21:56:46.55#ibcon#*before return 0, iclass 18, count 0 2006.257.21:56:46.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:46.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:46.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.21:56:46.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.21:56:46.55$vck44/va=4,7 2006.257.21:56:46.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.21:56:46.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.21:56:46.55#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:46.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:46.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:46.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:46.61#ibcon#enter wrdev, iclass 20, count 2 2006.257.21:56:46.61#ibcon#first serial, iclass 20, count 2 2006.257.21:56:46.61#ibcon#enter sib2, iclass 20, count 2 2006.257.21:56:46.61#ibcon#flushed, iclass 20, count 2 2006.257.21:56:46.61#ibcon#about to write, iclass 20, count 2 2006.257.21:56:46.61#ibcon#wrote, iclass 20, count 2 2006.257.21:56:46.61#ibcon#about to read 3, iclass 20, count 2 2006.257.21:56:46.63#ibcon#read 3, iclass 20, count 2 2006.257.21:56:46.63#ibcon#about to read 4, iclass 20, count 2 2006.257.21:56:46.63#ibcon#read 4, iclass 20, count 2 2006.257.21:56:46.63#ibcon#about to read 5, iclass 20, count 2 2006.257.21:56:46.63#ibcon#read 5, iclass 20, count 2 2006.257.21:56:46.63#ibcon#about to read 6, iclass 20, count 2 2006.257.21:56:46.63#ibcon#read 6, iclass 20, count 2 2006.257.21:56:46.63#ibcon#end of sib2, iclass 20, count 2 2006.257.21:56:46.63#ibcon#*mode == 0, iclass 20, count 2 2006.257.21:56:46.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.21:56:46.63#ibcon#[25=AT04-07\r\n] 2006.257.21:56:46.63#ibcon#*before write, iclass 20, count 2 2006.257.21:56:46.63#ibcon#enter sib2, iclass 20, count 2 2006.257.21:56:46.63#ibcon#flushed, iclass 20, count 2 2006.257.21:56:46.63#ibcon#about to write, iclass 20, count 2 2006.257.21:56:46.63#ibcon#wrote, iclass 20, count 2 2006.257.21:56:46.63#ibcon#about to read 3, iclass 20, count 2 2006.257.21:56:46.66#ibcon#read 3, iclass 20, count 2 2006.257.21:56:46.66#ibcon#about to read 4, iclass 20, count 2 2006.257.21:56:46.66#ibcon#read 4, iclass 20, count 2 2006.257.21:56:46.66#ibcon#about to read 5, iclass 20, count 2 2006.257.21:56:46.66#ibcon#read 5, iclass 20, count 2 2006.257.21:56:46.66#ibcon#about to read 6, iclass 20, count 2 2006.257.21:56:46.66#ibcon#read 6, iclass 20, count 2 2006.257.21:56:46.66#ibcon#end of sib2, iclass 20, count 2 2006.257.21:56:46.66#ibcon#*after write, iclass 20, count 2 2006.257.21:56:46.66#ibcon#*before return 0, iclass 20, count 2 2006.257.21:56:46.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:46.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:46.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.21:56:46.66#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:46.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:46.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:46.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:46.78#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:56:46.78#ibcon#first serial, iclass 20, count 0 2006.257.21:56:46.78#ibcon#enter sib2, iclass 20, count 0 2006.257.21:56:46.78#ibcon#flushed, iclass 20, count 0 2006.257.21:56:46.78#ibcon#about to write, iclass 20, count 0 2006.257.21:56:46.78#ibcon#wrote, iclass 20, count 0 2006.257.21:56:46.78#ibcon#about to read 3, iclass 20, count 0 2006.257.21:56:46.80#ibcon#read 3, iclass 20, count 0 2006.257.21:56:46.80#ibcon#about to read 4, iclass 20, count 0 2006.257.21:56:46.80#ibcon#read 4, iclass 20, count 0 2006.257.21:56:46.80#ibcon#about to read 5, iclass 20, count 0 2006.257.21:56:46.80#ibcon#read 5, iclass 20, count 0 2006.257.21:56:46.80#ibcon#about to read 6, iclass 20, count 0 2006.257.21:56:46.80#ibcon#read 6, iclass 20, count 0 2006.257.21:56:46.80#ibcon#end of sib2, iclass 20, count 0 2006.257.21:56:46.80#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:56:46.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:56:46.80#ibcon#[25=USB\r\n] 2006.257.21:56:46.80#ibcon#*before write, iclass 20, count 0 2006.257.21:56:46.80#ibcon#enter sib2, iclass 20, count 0 2006.257.21:56:46.80#ibcon#flushed, iclass 20, count 0 2006.257.21:56:46.80#ibcon#about to write, iclass 20, count 0 2006.257.21:56:46.80#ibcon#wrote, iclass 20, count 0 2006.257.21:56:46.80#ibcon#about to read 3, iclass 20, count 0 2006.257.21:56:46.83#ibcon#read 3, iclass 20, count 0 2006.257.21:56:46.83#ibcon#about to read 4, iclass 20, count 0 2006.257.21:56:46.83#ibcon#read 4, iclass 20, count 0 2006.257.21:56:46.83#ibcon#about to read 5, iclass 20, count 0 2006.257.21:56:46.83#ibcon#read 5, iclass 20, count 0 2006.257.21:56:46.83#ibcon#about to read 6, iclass 20, count 0 2006.257.21:56:46.83#ibcon#read 6, iclass 20, count 0 2006.257.21:56:46.83#ibcon#end of sib2, iclass 20, count 0 2006.257.21:56:46.83#ibcon#*after write, iclass 20, count 0 2006.257.21:56:46.83#ibcon#*before return 0, iclass 20, count 0 2006.257.21:56:46.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:46.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:46.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:56:46.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:56:46.83$vck44/valo=5,734.99 2006.257.21:56:46.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.21:56:46.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.21:56:46.83#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:46.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:46.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:46.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:46.83#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:56:46.83#ibcon#first serial, iclass 22, count 0 2006.257.21:56:46.83#ibcon#enter sib2, iclass 22, count 0 2006.257.21:56:46.83#ibcon#flushed, iclass 22, count 0 2006.257.21:56:46.83#ibcon#about to write, iclass 22, count 0 2006.257.21:56:46.83#ibcon#wrote, iclass 22, count 0 2006.257.21:56:46.83#ibcon#about to read 3, iclass 22, count 0 2006.257.21:56:46.85#ibcon#read 3, iclass 22, count 0 2006.257.21:56:46.85#ibcon#about to read 4, iclass 22, count 0 2006.257.21:56:46.85#ibcon#read 4, iclass 22, count 0 2006.257.21:56:46.85#ibcon#about to read 5, iclass 22, count 0 2006.257.21:56:46.85#ibcon#read 5, iclass 22, count 0 2006.257.21:56:46.85#ibcon#about to read 6, iclass 22, count 0 2006.257.21:56:46.85#ibcon#read 6, iclass 22, count 0 2006.257.21:56:46.85#ibcon#end of sib2, iclass 22, count 0 2006.257.21:56:46.85#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:56:46.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:56:46.85#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.21:56:46.85#ibcon#*before write, iclass 22, count 0 2006.257.21:56:46.85#ibcon#enter sib2, iclass 22, count 0 2006.257.21:56:46.85#ibcon#flushed, iclass 22, count 0 2006.257.21:56:46.85#ibcon#about to write, iclass 22, count 0 2006.257.21:56:46.85#ibcon#wrote, iclass 22, count 0 2006.257.21:56:46.85#ibcon#about to read 3, iclass 22, count 0 2006.257.21:56:46.89#ibcon#read 3, iclass 22, count 0 2006.257.21:56:46.89#ibcon#about to read 4, iclass 22, count 0 2006.257.21:56:46.89#ibcon#read 4, iclass 22, count 0 2006.257.21:56:46.89#ibcon#about to read 5, iclass 22, count 0 2006.257.21:56:46.89#ibcon#read 5, iclass 22, count 0 2006.257.21:56:46.89#ibcon#about to read 6, iclass 22, count 0 2006.257.21:56:46.89#ibcon#read 6, iclass 22, count 0 2006.257.21:56:46.89#ibcon#end of sib2, iclass 22, count 0 2006.257.21:56:46.89#ibcon#*after write, iclass 22, count 0 2006.257.21:56:46.89#ibcon#*before return 0, iclass 22, count 0 2006.257.21:56:46.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:46.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:46.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:56:46.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:56:46.89$vck44/va=5,4 2006.257.21:56:46.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.21:56:46.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.21:56:46.89#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:46.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:46.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:46.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:46.95#ibcon#enter wrdev, iclass 24, count 2 2006.257.21:56:46.95#ibcon#first serial, iclass 24, count 2 2006.257.21:56:46.95#ibcon#enter sib2, iclass 24, count 2 2006.257.21:56:46.95#ibcon#flushed, iclass 24, count 2 2006.257.21:56:46.95#ibcon#about to write, iclass 24, count 2 2006.257.21:56:46.95#ibcon#wrote, iclass 24, count 2 2006.257.21:56:46.95#ibcon#about to read 3, iclass 24, count 2 2006.257.21:56:46.97#ibcon#read 3, iclass 24, count 2 2006.257.21:56:46.97#ibcon#about to read 4, iclass 24, count 2 2006.257.21:56:46.97#ibcon#read 4, iclass 24, count 2 2006.257.21:56:46.97#ibcon#about to read 5, iclass 24, count 2 2006.257.21:56:46.97#ibcon#read 5, iclass 24, count 2 2006.257.21:56:46.97#ibcon#about to read 6, iclass 24, count 2 2006.257.21:56:46.97#ibcon#read 6, iclass 24, count 2 2006.257.21:56:46.97#ibcon#end of sib2, iclass 24, count 2 2006.257.21:56:46.97#ibcon#*mode == 0, iclass 24, count 2 2006.257.21:56:46.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.21:56:46.97#ibcon#[25=AT05-04\r\n] 2006.257.21:56:46.97#ibcon#*before write, iclass 24, count 2 2006.257.21:56:46.97#ibcon#enter sib2, iclass 24, count 2 2006.257.21:56:46.97#ibcon#flushed, iclass 24, count 2 2006.257.21:56:46.97#ibcon#about to write, iclass 24, count 2 2006.257.21:56:46.97#ibcon#wrote, iclass 24, count 2 2006.257.21:56:46.97#ibcon#about to read 3, iclass 24, count 2 2006.257.21:56:47.00#ibcon#read 3, iclass 24, count 2 2006.257.21:56:47.00#ibcon#about to read 4, iclass 24, count 2 2006.257.21:56:47.00#ibcon#read 4, iclass 24, count 2 2006.257.21:56:47.00#ibcon#about to read 5, iclass 24, count 2 2006.257.21:56:47.00#ibcon#read 5, iclass 24, count 2 2006.257.21:56:47.00#ibcon#about to read 6, iclass 24, count 2 2006.257.21:56:47.00#ibcon#read 6, iclass 24, count 2 2006.257.21:56:47.00#ibcon#end of sib2, iclass 24, count 2 2006.257.21:56:47.00#ibcon#*after write, iclass 24, count 2 2006.257.21:56:47.00#ibcon#*before return 0, iclass 24, count 2 2006.257.21:56:47.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:47.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:47.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.21:56:47.00#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:47.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:47.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:47.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:47.12#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:56:47.12#ibcon#first serial, iclass 24, count 0 2006.257.21:56:47.12#ibcon#enter sib2, iclass 24, count 0 2006.257.21:56:47.12#ibcon#flushed, iclass 24, count 0 2006.257.21:56:47.12#ibcon#about to write, iclass 24, count 0 2006.257.21:56:47.12#ibcon#wrote, iclass 24, count 0 2006.257.21:56:47.12#ibcon#about to read 3, iclass 24, count 0 2006.257.21:56:47.14#ibcon#read 3, iclass 24, count 0 2006.257.21:56:47.14#ibcon#about to read 4, iclass 24, count 0 2006.257.21:56:47.14#ibcon#read 4, iclass 24, count 0 2006.257.21:56:47.14#ibcon#about to read 5, iclass 24, count 0 2006.257.21:56:47.14#ibcon#read 5, iclass 24, count 0 2006.257.21:56:47.14#ibcon#about to read 6, iclass 24, count 0 2006.257.21:56:47.14#ibcon#read 6, iclass 24, count 0 2006.257.21:56:47.14#ibcon#end of sib2, iclass 24, count 0 2006.257.21:56:47.14#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:56:47.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:56:47.14#ibcon#[25=USB\r\n] 2006.257.21:56:47.14#ibcon#*before write, iclass 24, count 0 2006.257.21:56:47.14#ibcon#enter sib2, iclass 24, count 0 2006.257.21:56:47.14#ibcon#flushed, iclass 24, count 0 2006.257.21:56:47.14#ibcon#about to write, iclass 24, count 0 2006.257.21:56:47.14#ibcon#wrote, iclass 24, count 0 2006.257.21:56:47.14#ibcon#about to read 3, iclass 24, count 0 2006.257.21:56:47.17#ibcon#read 3, iclass 24, count 0 2006.257.21:56:47.17#ibcon#about to read 4, iclass 24, count 0 2006.257.21:56:47.17#ibcon#read 4, iclass 24, count 0 2006.257.21:56:47.17#ibcon#about to read 5, iclass 24, count 0 2006.257.21:56:47.17#ibcon#read 5, iclass 24, count 0 2006.257.21:56:47.17#ibcon#about to read 6, iclass 24, count 0 2006.257.21:56:47.17#ibcon#read 6, iclass 24, count 0 2006.257.21:56:47.17#ibcon#end of sib2, iclass 24, count 0 2006.257.21:56:47.17#ibcon#*after write, iclass 24, count 0 2006.257.21:56:47.17#ibcon#*before return 0, iclass 24, count 0 2006.257.21:56:47.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:47.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:47.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:56:47.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:56:47.17$vck44/valo=6,814.99 2006.257.21:56:47.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.21:56:47.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.21:56:47.17#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:47.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:47.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:47.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:47.17#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:56:47.17#ibcon#first serial, iclass 26, count 0 2006.257.21:56:47.17#ibcon#enter sib2, iclass 26, count 0 2006.257.21:56:47.17#ibcon#flushed, iclass 26, count 0 2006.257.21:56:47.17#ibcon#about to write, iclass 26, count 0 2006.257.21:56:47.17#ibcon#wrote, iclass 26, count 0 2006.257.21:56:47.17#ibcon#about to read 3, iclass 26, count 0 2006.257.21:56:47.19#ibcon#read 3, iclass 26, count 0 2006.257.21:56:47.19#ibcon#about to read 4, iclass 26, count 0 2006.257.21:56:47.19#ibcon#read 4, iclass 26, count 0 2006.257.21:56:47.19#ibcon#about to read 5, iclass 26, count 0 2006.257.21:56:47.19#ibcon#read 5, iclass 26, count 0 2006.257.21:56:47.19#ibcon#about to read 6, iclass 26, count 0 2006.257.21:56:47.19#ibcon#read 6, iclass 26, count 0 2006.257.21:56:47.19#ibcon#end of sib2, iclass 26, count 0 2006.257.21:56:47.19#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:56:47.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:56:47.19#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.21:56:47.19#ibcon#*before write, iclass 26, count 0 2006.257.21:56:47.19#ibcon#enter sib2, iclass 26, count 0 2006.257.21:56:47.19#ibcon#flushed, iclass 26, count 0 2006.257.21:56:47.19#ibcon#about to write, iclass 26, count 0 2006.257.21:56:47.19#ibcon#wrote, iclass 26, count 0 2006.257.21:56:47.19#ibcon#about to read 3, iclass 26, count 0 2006.257.21:56:47.23#ibcon#read 3, iclass 26, count 0 2006.257.21:56:47.23#ibcon#about to read 4, iclass 26, count 0 2006.257.21:56:47.23#ibcon#read 4, iclass 26, count 0 2006.257.21:56:47.23#ibcon#about to read 5, iclass 26, count 0 2006.257.21:56:47.23#ibcon#read 5, iclass 26, count 0 2006.257.21:56:47.23#ibcon#about to read 6, iclass 26, count 0 2006.257.21:56:47.23#ibcon#read 6, iclass 26, count 0 2006.257.21:56:47.23#ibcon#end of sib2, iclass 26, count 0 2006.257.21:56:47.23#ibcon#*after write, iclass 26, count 0 2006.257.21:56:47.23#ibcon#*before return 0, iclass 26, count 0 2006.257.21:56:47.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:47.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:47.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:56:47.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:56:47.23$vck44/va=6,4 2006.257.21:56:47.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.21:56:47.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.21:56:47.23#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:47.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:47.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:47.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:47.29#ibcon#enter wrdev, iclass 28, count 2 2006.257.21:56:47.29#ibcon#first serial, iclass 28, count 2 2006.257.21:56:47.29#ibcon#enter sib2, iclass 28, count 2 2006.257.21:56:47.29#ibcon#flushed, iclass 28, count 2 2006.257.21:56:47.29#ibcon#about to write, iclass 28, count 2 2006.257.21:56:47.29#ibcon#wrote, iclass 28, count 2 2006.257.21:56:47.29#ibcon#about to read 3, iclass 28, count 2 2006.257.21:56:47.31#ibcon#read 3, iclass 28, count 2 2006.257.21:56:47.31#ibcon#about to read 4, iclass 28, count 2 2006.257.21:56:47.31#ibcon#read 4, iclass 28, count 2 2006.257.21:56:47.31#ibcon#about to read 5, iclass 28, count 2 2006.257.21:56:47.31#ibcon#read 5, iclass 28, count 2 2006.257.21:56:47.31#ibcon#about to read 6, iclass 28, count 2 2006.257.21:56:47.31#ibcon#read 6, iclass 28, count 2 2006.257.21:56:47.31#ibcon#end of sib2, iclass 28, count 2 2006.257.21:56:47.31#ibcon#*mode == 0, iclass 28, count 2 2006.257.21:56:47.31#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.21:56:47.31#ibcon#[25=AT06-04\r\n] 2006.257.21:56:47.31#ibcon#*before write, iclass 28, count 2 2006.257.21:56:47.31#ibcon#enter sib2, iclass 28, count 2 2006.257.21:56:47.31#ibcon#flushed, iclass 28, count 2 2006.257.21:56:47.31#ibcon#about to write, iclass 28, count 2 2006.257.21:56:47.31#ibcon#wrote, iclass 28, count 2 2006.257.21:56:47.31#ibcon#about to read 3, iclass 28, count 2 2006.257.21:56:47.34#ibcon#read 3, iclass 28, count 2 2006.257.21:56:47.34#ibcon#about to read 4, iclass 28, count 2 2006.257.21:56:47.34#ibcon#read 4, iclass 28, count 2 2006.257.21:56:47.34#ibcon#about to read 5, iclass 28, count 2 2006.257.21:56:47.34#ibcon#read 5, iclass 28, count 2 2006.257.21:56:47.34#ibcon#about to read 6, iclass 28, count 2 2006.257.21:56:47.34#ibcon#read 6, iclass 28, count 2 2006.257.21:56:47.34#ibcon#end of sib2, iclass 28, count 2 2006.257.21:56:47.34#ibcon#*after write, iclass 28, count 2 2006.257.21:56:47.34#ibcon#*before return 0, iclass 28, count 2 2006.257.21:56:47.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:47.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:47.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.21:56:47.34#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:47.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:47.46#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:47.46#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:47.46#ibcon#enter wrdev, iclass 28, count 0 2006.257.21:56:47.46#ibcon#first serial, iclass 28, count 0 2006.257.21:56:47.46#ibcon#enter sib2, iclass 28, count 0 2006.257.21:56:47.46#ibcon#flushed, iclass 28, count 0 2006.257.21:56:47.46#ibcon#about to write, iclass 28, count 0 2006.257.21:56:47.46#ibcon#wrote, iclass 28, count 0 2006.257.21:56:47.46#ibcon#about to read 3, iclass 28, count 0 2006.257.21:56:47.48#ibcon#read 3, iclass 28, count 0 2006.257.21:56:47.48#ibcon#about to read 4, iclass 28, count 0 2006.257.21:56:47.48#ibcon#read 4, iclass 28, count 0 2006.257.21:56:47.48#ibcon#about to read 5, iclass 28, count 0 2006.257.21:56:47.48#ibcon#read 5, iclass 28, count 0 2006.257.21:56:47.48#ibcon#about to read 6, iclass 28, count 0 2006.257.21:56:47.48#ibcon#read 6, iclass 28, count 0 2006.257.21:56:47.48#ibcon#end of sib2, iclass 28, count 0 2006.257.21:56:47.48#ibcon#*mode == 0, iclass 28, count 0 2006.257.21:56:47.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.21:56:47.48#ibcon#[25=USB\r\n] 2006.257.21:56:47.48#ibcon#*before write, iclass 28, count 0 2006.257.21:56:47.48#ibcon#enter sib2, iclass 28, count 0 2006.257.21:56:47.48#ibcon#flushed, iclass 28, count 0 2006.257.21:56:47.48#ibcon#about to write, iclass 28, count 0 2006.257.21:56:47.48#ibcon#wrote, iclass 28, count 0 2006.257.21:56:47.48#ibcon#about to read 3, iclass 28, count 0 2006.257.21:56:47.51#ibcon#read 3, iclass 28, count 0 2006.257.21:56:47.51#ibcon#about to read 4, iclass 28, count 0 2006.257.21:56:47.51#ibcon#read 4, iclass 28, count 0 2006.257.21:56:47.51#ibcon#about to read 5, iclass 28, count 0 2006.257.21:56:47.51#ibcon#read 5, iclass 28, count 0 2006.257.21:56:47.51#ibcon#about to read 6, iclass 28, count 0 2006.257.21:56:47.51#ibcon#read 6, iclass 28, count 0 2006.257.21:56:47.51#ibcon#end of sib2, iclass 28, count 0 2006.257.21:56:47.51#ibcon#*after write, iclass 28, count 0 2006.257.21:56:47.51#ibcon#*before return 0, iclass 28, count 0 2006.257.21:56:47.51#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:47.51#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:47.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.21:56:47.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.21:56:47.51$vck44/valo=7,864.99 2006.257.21:56:47.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.21:56:47.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.21:56:47.51#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:47.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:47.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:47.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:47.51#ibcon#enter wrdev, iclass 30, count 0 2006.257.21:56:47.51#ibcon#first serial, iclass 30, count 0 2006.257.21:56:47.51#ibcon#enter sib2, iclass 30, count 0 2006.257.21:56:47.51#ibcon#flushed, iclass 30, count 0 2006.257.21:56:47.51#ibcon#about to write, iclass 30, count 0 2006.257.21:56:47.51#ibcon#wrote, iclass 30, count 0 2006.257.21:56:47.51#ibcon#about to read 3, iclass 30, count 0 2006.257.21:56:47.53#ibcon#read 3, iclass 30, count 0 2006.257.21:56:47.53#ibcon#about to read 4, iclass 30, count 0 2006.257.21:56:47.53#ibcon#read 4, iclass 30, count 0 2006.257.21:56:47.53#ibcon#about to read 5, iclass 30, count 0 2006.257.21:56:47.53#ibcon#read 5, iclass 30, count 0 2006.257.21:56:47.53#ibcon#about to read 6, iclass 30, count 0 2006.257.21:56:47.53#ibcon#read 6, iclass 30, count 0 2006.257.21:56:47.53#ibcon#end of sib2, iclass 30, count 0 2006.257.21:56:47.53#ibcon#*mode == 0, iclass 30, count 0 2006.257.21:56:47.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.21:56:47.53#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.21:56:47.53#ibcon#*before write, iclass 30, count 0 2006.257.21:56:47.53#ibcon#enter sib2, iclass 30, count 0 2006.257.21:56:47.53#ibcon#flushed, iclass 30, count 0 2006.257.21:56:47.53#ibcon#about to write, iclass 30, count 0 2006.257.21:56:47.53#ibcon#wrote, iclass 30, count 0 2006.257.21:56:47.53#ibcon#about to read 3, iclass 30, count 0 2006.257.21:56:47.57#ibcon#read 3, iclass 30, count 0 2006.257.21:56:47.57#ibcon#about to read 4, iclass 30, count 0 2006.257.21:56:47.57#ibcon#read 4, iclass 30, count 0 2006.257.21:56:47.57#ibcon#about to read 5, iclass 30, count 0 2006.257.21:56:47.57#ibcon#read 5, iclass 30, count 0 2006.257.21:56:47.57#ibcon#about to read 6, iclass 30, count 0 2006.257.21:56:47.57#ibcon#read 6, iclass 30, count 0 2006.257.21:56:47.57#ibcon#end of sib2, iclass 30, count 0 2006.257.21:56:47.57#ibcon#*after write, iclass 30, count 0 2006.257.21:56:47.57#ibcon#*before return 0, iclass 30, count 0 2006.257.21:56:47.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:47.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:47.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.21:56:47.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.21:56:47.57$vck44/va=7,4 2006.257.21:56:47.57#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.21:56:47.57#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.21:56:47.57#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:47.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:47.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:47.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:47.63#ibcon#enter wrdev, iclass 32, count 2 2006.257.21:56:47.63#ibcon#first serial, iclass 32, count 2 2006.257.21:56:47.63#ibcon#enter sib2, iclass 32, count 2 2006.257.21:56:47.63#ibcon#flushed, iclass 32, count 2 2006.257.21:56:47.63#ibcon#about to write, iclass 32, count 2 2006.257.21:56:47.63#ibcon#wrote, iclass 32, count 2 2006.257.21:56:47.63#ibcon#about to read 3, iclass 32, count 2 2006.257.21:56:47.65#ibcon#read 3, iclass 32, count 2 2006.257.21:56:47.65#ibcon#about to read 4, iclass 32, count 2 2006.257.21:56:47.65#ibcon#read 4, iclass 32, count 2 2006.257.21:56:47.65#ibcon#about to read 5, iclass 32, count 2 2006.257.21:56:47.65#ibcon#read 5, iclass 32, count 2 2006.257.21:56:47.65#ibcon#about to read 6, iclass 32, count 2 2006.257.21:56:47.65#ibcon#read 6, iclass 32, count 2 2006.257.21:56:47.65#ibcon#end of sib2, iclass 32, count 2 2006.257.21:56:47.65#ibcon#*mode == 0, iclass 32, count 2 2006.257.21:56:47.65#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.21:56:47.65#ibcon#[25=AT07-04\r\n] 2006.257.21:56:47.65#ibcon#*before write, iclass 32, count 2 2006.257.21:56:47.65#ibcon#enter sib2, iclass 32, count 2 2006.257.21:56:47.65#ibcon#flushed, iclass 32, count 2 2006.257.21:56:47.65#ibcon#about to write, iclass 32, count 2 2006.257.21:56:47.65#ibcon#wrote, iclass 32, count 2 2006.257.21:56:47.65#ibcon#about to read 3, iclass 32, count 2 2006.257.21:56:47.68#ibcon#read 3, iclass 32, count 2 2006.257.21:56:47.68#ibcon#about to read 4, iclass 32, count 2 2006.257.21:56:47.68#ibcon#read 4, iclass 32, count 2 2006.257.21:56:47.68#ibcon#about to read 5, iclass 32, count 2 2006.257.21:56:47.68#ibcon#read 5, iclass 32, count 2 2006.257.21:56:47.68#ibcon#about to read 6, iclass 32, count 2 2006.257.21:56:47.68#ibcon#read 6, iclass 32, count 2 2006.257.21:56:47.68#ibcon#end of sib2, iclass 32, count 2 2006.257.21:56:47.68#ibcon#*after write, iclass 32, count 2 2006.257.21:56:47.68#ibcon#*before return 0, iclass 32, count 2 2006.257.21:56:47.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:47.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:47.68#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.21:56:47.68#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:47.68#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:47.80#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:47.80#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:47.80#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:56:47.80#ibcon#first serial, iclass 32, count 0 2006.257.21:56:47.80#ibcon#enter sib2, iclass 32, count 0 2006.257.21:56:47.80#ibcon#flushed, iclass 32, count 0 2006.257.21:56:47.80#ibcon#about to write, iclass 32, count 0 2006.257.21:56:47.80#ibcon#wrote, iclass 32, count 0 2006.257.21:56:47.80#ibcon#about to read 3, iclass 32, count 0 2006.257.21:56:47.82#ibcon#read 3, iclass 32, count 0 2006.257.21:56:47.82#ibcon#about to read 4, iclass 32, count 0 2006.257.21:56:47.82#ibcon#read 4, iclass 32, count 0 2006.257.21:56:47.82#ibcon#about to read 5, iclass 32, count 0 2006.257.21:56:47.82#ibcon#read 5, iclass 32, count 0 2006.257.21:56:47.82#ibcon#about to read 6, iclass 32, count 0 2006.257.21:56:47.82#ibcon#read 6, iclass 32, count 0 2006.257.21:56:47.82#ibcon#end of sib2, iclass 32, count 0 2006.257.21:56:47.82#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:56:47.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:56:47.82#ibcon#[25=USB\r\n] 2006.257.21:56:47.82#ibcon#*before write, iclass 32, count 0 2006.257.21:56:47.82#ibcon#enter sib2, iclass 32, count 0 2006.257.21:56:47.82#ibcon#flushed, iclass 32, count 0 2006.257.21:56:47.82#ibcon#about to write, iclass 32, count 0 2006.257.21:56:47.82#ibcon#wrote, iclass 32, count 0 2006.257.21:56:47.82#ibcon#about to read 3, iclass 32, count 0 2006.257.21:56:47.85#ibcon#read 3, iclass 32, count 0 2006.257.21:56:47.85#ibcon#about to read 4, iclass 32, count 0 2006.257.21:56:47.85#ibcon#read 4, iclass 32, count 0 2006.257.21:56:47.85#ibcon#about to read 5, iclass 32, count 0 2006.257.21:56:47.85#ibcon#read 5, iclass 32, count 0 2006.257.21:56:47.85#ibcon#about to read 6, iclass 32, count 0 2006.257.21:56:47.85#ibcon#read 6, iclass 32, count 0 2006.257.21:56:47.85#ibcon#end of sib2, iclass 32, count 0 2006.257.21:56:47.85#ibcon#*after write, iclass 32, count 0 2006.257.21:56:47.85#ibcon#*before return 0, iclass 32, count 0 2006.257.21:56:47.85#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:47.85#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:47.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:56:47.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:56:47.85$vck44/valo=8,884.99 2006.257.21:56:47.85#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.21:56:47.85#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.21:56:47.85#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:47.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:47.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:47.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:47.85#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:56:47.85#ibcon#first serial, iclass 34, count 0 2006.257.21:56:47.85#ibcon#enter sib2, iclass 34, count 0 2006.257.21:56:47.85#ibcon#flushed, iclass 34, count 0 2006.257.21:56:47.85#ibcon#about to write, iclass 34, count 0 2006.257.21:56:47.85#ibcon#wrote, iclass 34, count 0 2006.257.21:56:47.85#ibcon#about to read 3, iclass 34, count 0 2006.257.21:56:47.87#ibcon#read 3, iclass 34, count 0 2006.257.21:56:47.87#ibcon#about to read 4, iclass 34, count 0 2006.257.21:56:47.87#ibcon#read 4, iclass 34, count 0 2006.257.21:56:47.87#ibcon#about to read 5, iclass 34, count 0 2006.257.21:56:47.87#ibcon#read 5, iclass 34, count 0 2006.257.21:56:47.87#ibcon#about to read 6, iclass 34, count 0 2006.257.21:56:47.87#ibcon#read 6, iclass 34, count 0 2006.257.21:56:47.87#ibcon#end of sib2, iclass 34, count 0 2006.257.21:56:47.87#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:56:47.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:56:47.87#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.21:56:47.87#ibcon#*before write, iclass 34, count 0 2006.257.21:56:47.87#ibcon#enter sib2, iclass 34, count 0 2006.257.21:56:47.87#ibcon#flushed, iclass 34, count 0 2006.257.21:56:47.87#ibcon#about to write, iclass 34, count 0 2006.257.21:56:47.87#ibcon#wrote, iclass 34, count 0 2006.257.21:56:47.87#ibcon#about to read 3, iclass 34, count 0 2006.257.21:56:47.91#ibcon#read 3, iclass 34, count 0 2006.257.21:56:47.91#ibcon#about to read 4, iclass 34, count 0 2006.257.21:56:47.91#ibcon#read 4, iclass 34, count 0 2006.257.21:56:47.91#ibcon#about to read 5, iclass 34, count 0 2006.257.21:56:47.91#ibcon#read 5, iclass 34, count 0 2006.257.21:56:47.91#ibcon#about to read 6, iclass 34, count 0 2006.257.21:56:47.91#ibcon#read 6, iclass 34, count 0 2006.257.21:56:47.91#ibcon#end of sib2, iclass 34, count 0 2006.257.21:56:47.91#ibcon#*after write, iclass 34, count 0 2006.257.21:56:47.91#ibcon#*before return 0, iclass 34, count 0 2006.257.21:56:47.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:47.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:47.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:56:47.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:56:47.91$vck44/va=8,4 2006.257.21:56:47.91#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.21:56:47.91#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.21:56:47.91#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:47.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:56:47.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:56:47.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:56:47.97#ibcon#enter wrdev, iclass 36, count 2 2006.257.21:56:47.97#ibcon#first serial, iclass 36, count 2 2006.257.21:56:47.97#ibcon#enter sib2, iclass 36, count 2 2006.257.21:56:47.97#ibcon#flushed, iclass 36, count 2 2006.257.21:56:47.97#ibcon#about to write, iclass 36, count 2 2006.257.21:56:47.97#ibcon#wrote, iclass 36, count 2 2006.257.21:56:47.97#ibcon#about to read 3, iclass 36, count 2 2006.257.21:56:47.99#ibcon#read 3, iclass 36, count 2 2006.257.21:56:47.99#ibcon#about to read 4, iclass 36, count 2 2006.257.21:56:47.99#ibcon#read 4, iclass 36, count 2 2006.257.21:56:47.99#ibcon#about to read 5, iclass 36, count 2 2006.257.21:56:47.99#ibcon#read 5, iclass 36, count 2 2006.257.21:56:47.99#ibcon#about to read 6, iclass 36, count 2 2006.257.21:56:47.99#ibcon#read 6, iclass 36, count 2 2006.257.21:56:47.99#ibcon#end of sib2, iclass 36, count 2 2006.257.21:56:47.99#ibcon#*mode == 0, iclass 36, count 2 2006.257.21:56:47.99#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.21:56:47.99#ibcon#[25=AT08-04\r\n] 2006.257.21:56:47.99#ibcon#*before write, iclass 36, count 2 2006.257.21:56:47.99#ibcon#enter sib2, iclass 36, count 2 2006.257.21:56:47.99#ibcon#flushed, iclass 36, count 2 2006.257.21:56:47.99#ibcon#about to write, iclass 36, count 2 2006.257.21:56:47.99#ibcon#wrote, iclass 36, count 2 2006.257.21:56:47.99#ibcon#about to read 3, iclass 36, count 2 2006.257.21:56:48.02#ibcon#read 3, iclass 36, count 2 2006.257.21:56:48.02#ibcon#about to read 4, iclass 36, count 2 2006.257.21:56:48.02#ibcon#read 4, iclass 36, count 2 2006.257.21:56:48.02#ibcon#about to read 5, iclass 36, count 2 2006.257.21:56:48.02#ibcon#read 5, iclass 36, count 2 2006.257.21:56:48.02#ibcon#about to read 6, iclass 36, count 2 2006.257.21:56:48.02#ibcon#read 6, iclass 36, count 2 2006.257.21:56:48.02#ibcon#end of sib2, iclass 36, count 2 2006.257.21:56:48.02#ibcon#*after write, iclass 36, count 2 2006.257.21:56:48.02#ibcon#*before return 0, iclass 36, count 2 2006.257.21:56:48.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:56:48.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.21:56:48.02#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.21:56:48.02#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:48.02#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:56:48.14#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:56:48.14#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:56:48.14#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:56:48.14#ibcon#first serial, iclass 36, count 0 2006.257.21:56:48.14#ibcon#enter sib2, iclass 36, count 0 2006.257.21:56:48.14#ibcon#flushed, iclass 36, count 0 2006.257.21:56:48.14#ibcon#about to write, iclass 36, count 0 2006.257.21:56:48.14#ibcon#wrote, iclass 36, count 0 2006.257.21:56:48.14#ibcon#about to read 3, iclass 36, count 0 2006.257.21:56:48.16#ibcon#read 3, iclass 36, count 0 2006.257.21:56:48.16#ibcon#about to read 4, iclass 36, count 0 2006.257.21:56:48.16#ibcon#read 4, iclass 36, count 0 2006.257.21:56:48.16#ibcon#about to read 5, iclass 36, count 0 2006.257.21:56:48.16#ibcon#read 5, iclass 36, count 0 2006.257.21:56:48.16#ibcon#about to read 6, iclass 36, count 0 2006.257.21:56:48.16#ibcon#read 6, iclass 36, count 0 2006.257.21:56:48.16#ibcon#end of sib2, iclass 36, count 0 2006.257.21:56:48.16#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:56:48.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:56:48.16#ibcon#[25=USB\r\n] 2006.257.21:56:48.16#ibcon#*before write, iclass 36, count 0 2006.257.21:56:48.16#ibcon#enter sib2, iclass 36, count 0 2006.257.21:56:48.16#ibcon#flushed, iclass 36, count 0 2006.257.21:56:48.16#ibcon#about to write, iclass 36, count 0 2006.257.21:56:48.16#ibcon#wrote, iclass 36, count 0 2006.257.21:56:48.16#ibcon#about to read 3, iclass 36, count 0 2006.257.21:56:48.19#ibcon#read 3, iclass 36, count 0 2006.257.21:56:48.19#ibcon#about to read 4, iclass 36, count 0 2006.257.21:56:48.19#ibcon#read 4, iclass 36, count 0 2006.257.21:56:48.19#ibcon#about to read 5, iclass 36, count 0 2006.257.21:56:48.19#ibcon#read 5, iclass 36, count 0 2006.257.21:56:48.19#ibcon#about to read 6, iclass 36, count 0 2006.257.21:56:48.19#ibcon#read 6, iclass 36, count 0 2006.257.21:56:48.19#ibcon#end of sib2, iclass 36, count 0 2006.257.21:56:48.19#ibcon#*after write, iclass 36, count 0 2006.257.21:56:48.19#ibcon#*before return 0, iclass 36, count 0 2006.257.21:56:48.19#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:56:48.19#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.21:56:48.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:56:48.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:56:48.19$vck44/vblo=1,629.99 2006.257.21:56:48.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.21:56:48.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.21:56:48.19#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:48.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:56:48.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:56:48.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:56:48.19#ibcon#enter wrdev, iclass 38, count 0 2006.257.21:56:48.19#ibcon#first serial, iclass 38, count 0 2006.257.21:56:48.19#ibcon#enter sib2, iclass 38, count 0 2006.257.21:56:48.19#ibcon#flushed, iclass 38, count 0 2006.257.21:56:48.19#ibcon#about to write, iclass 38, count 0 2006.257.21:56:48.19#ibcon#wrote, iclass 38, count 0 2006.257.21:56:48.19#ibcon#about to read 3, iclass 38, count 0 2006.257.21:56:48.21#ibcon#read 3, iclass 38, count 0 2006.257.21:56:48.21#ibcon#about to read 4, iclass 38, count 0 2006.257.21:56:48.21#ibcon#read 4, iclass 38, count 0 2006.257.21:56:48.21#ibcon#about to read 5, iclass 38, count 0 2006.257.21:56:48.21#ibcon#read 5, iclass 38, count 0 2006.257.21:56:48.21#ibcon#about to read 6, iclass 38, count 0 2006.257.21:56:48.21#ibcon#read 6, iclass 38, count 0 2006.257.21:56:48.21#ibcon#end of sib2, iclass 38, count 0 2006.257.21:56:48.21#ibcon#*mode == 0, iclass 38, count 0 2006.257.21:56:48.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.21:56:48.21#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.21:56:48.21#ibcon#*before write, iclass 38, count 0 2006.257.21:56:48.21#ibcon#enter sib2, iclass 38, count 0 2006.257.21:56:48.21#ibcon#flushed, iclass 38, count 0 2006.257.21:56:48.21#ibcon#about to write, iclass 38, count 0 2006.257.21:56:48.21#ibcon#wrote, iclass 38, count 0 2006.257.21:56:48.21#ibcon#about to read 3, iclass 38, count 0 2006.257.21:56:48.25#ibcon#read 3, iclass 38, count 0 2006.257.21:56:48.25#ibcon#about to read 4, iclass 38, count 0 2006.257.21:56:48.25#ibcon#read 4, iclass 38, count 0 2006.257.21:56:48.25#ibcon#about to read 5, iclass 38, count 0 2006.257.21:56:48.25#ibcon#read 5, iclass 38, count 0 2006.257.21:56:48.25#ibcon#about to read 6, iclass 38, count 0 2006.257.21:56:48.25#ibcon#read 6, iclass 38, count 0 2006.257.21:56:48.25#ibcon#end of sib2, iclass 38, count 0 2006.257.21:56:48.25#ibcon#*after write, iclass 38, count 0 2006.257.21:56:48.25#ibcon#*before return 0, iclass 38, count 0 2006.257.21:56:48.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:56:48.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.21:56:48.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.21:56:48.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.21:56:48.25$vck44/vb=1,4 2006.257.21:56:48.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.21:56:48.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.21:56:48.25#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:48.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:56:48.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:56:48.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:56:48.25#ibcon#enter wrdev, iclass 40, count 2 2006.257.21:56:48.25#ibcon#first serial, iclass 40, count 2 2006.257.21:56:48.25#ibcon#enter sib2, iclass 40, count 2 2006.257.21:56:48.25#ibcon#flushed, iclass 40, count 2 2006.257.21:56:48.25#ibcon#about to write, iclass 40, count 2 2006.257.21:56:48.25#ibcon#wrote, iclass 40, count 2 2006.257.21:56:48.25#ibcon#about to read 3, iclass 40, count 2 2006.257.21:56:48.27#ibcon#read 3, iclass 40, count 2 2006.257.21:56:48.27#ibcon#about to read 4, iclass 40, count 2 2006.257.21:56:48.27#ibcon#read 4, iclass 40, count 2 2006.257.21:56:48.27#ibcon#about to read 5, iclass 40, count 2 2006.257.21:56:48.27#ibcon#read 5, iclass 40, count 2 2006.257.21:56:48.27#ibcon#about to read 6, iclass 40, count 2 2006.257.21:56:48.27#ibcon#read 6, iclass 40, count 2 2006.257.21:56:48.27#ibcon#end of sib2, iclass 40, count 2 2006.257.21:56:48.27#ibcon#*mode == 0, iclass 40, count 2 2006.257.21:56:48.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.21:56:48.27#ibcon#[27=AT01-04\r\n] 2006.257.21:56:48.27#ibcon#*before write, iclass 40, count 2 2006.257.21:56:48.27#ibcon#enter sib2, iclass 40, count 2 2006.257.21:56:48.27#ibcon#flushed, iclass 40, count 2 2006.257.21:56:48.27#ibcon#about to write, iclass 40, count 2 2006.257.21:56:48.27#ibcon#wrote, iclass 40, count 2 2006.257.21:56:48.27#ibcon#about to read 3, iclass 40, count 2 2006.257.21:56:48.30#ibcon#read 3, iclass 40, count 2 2006.257.21:56:48.30#ibcon#about to read 4, iclass 40, count 2 2006.257.21:56:48.30#ibcon#read 4, iclass 40, count 2 2006.257.21:56:48.30#ibcon#about to read 5, iclass 40, count 2 2006.257.21:56:48.30#ibcon#read 5, iclass 40, count 2 2006.257.21:56:48.30#ibcon#about to read 6, iclass 40, count 2 2006.257.21:56:48.30#ibcon#read 6, iclass 40, count 2 2006.257.21:56:48.30#ibcon#end of sib2, iclass 40, count 2 2006.257.21:56:48.30#ibcon#*after write, iclass 40, count 2 2006.257.21:56:48.30#ibcon#*before return 0, iclass 40, count 2 2006.257.21:56:48.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:56:48.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.21:56:48.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.21:56:48.30#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:48.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:56:48.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:56:48.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:56:48.42#ibcon#enter wrdev, iclass 40, count 0 2006.257.21:56:48.42#ibcon#first serial, iclass 40, count 0 2006.257.21:56:48.42#ibcon#enter sib2, iclass 40, count 0 2006.257.21:56:48.42#ibcon#flushed, iclass 40, count 0 2006.257.21:56:48.42#ibcon#about to write, iclass 40, count 0 2006.257.21:56:48.42#ibcon#wrote, iclass 40, count 0 2006.257.21:56:48.42#ibcon#about to read 3, iclass 40, count 0 2006.257.21:56:48.44#ibcon#read 3, iclass 40, count 0 2006.257.21:56:48.44#ibcon#about to read 4, iclass 40, count 0 2006.257.21:56:48.44#ibcon#read 4, iclass 40, count 0 2006.257.21:56:48.44#ibcon#about to read 5, iclass 40, count 0 2006.257.21:56:48.44#ibcon#read 5, iclass 40, count 0 2006.257.21:56:48.44#ibcon#about to read 6, iclass 40, count 0 2006.257.21:56:48.44#ibcon#read 6, iclass 40, count 0 2006.257.21:56:48.44#ibcon#end of sib2, iclass 40, count 0 2006.257.21:56:48.44#ibcon#*mode == 0, iclass 40, count 0 2006.257.21:56:48.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.21:56:48.44#ibcon#[27=USB\r\n] 2006.257.21:56:48.44#ibcon#*before write, iclass 40, count 0 2006.257.21:56:48.44#ibcon#enter sib2, iclass 40, count 0 2006.257.21:56:48.44#ibcon#flushed, iclass 40, count 0 2006.257.21:56:48.44#ibcon#about to write, iclass 40, count 0 2006.257.21:56:48.44#ibcon#wrote, iclass 40, count 0 2006.257.21:56:48.44#ibcon#about to read 3, iclass 40, count 0 2006.257.21:56:48.47#ibcon#read 3, iclass 40, count 0 2006.257.21:56:48.47#ibcon#about to read 4, iclass 40, count 0 2006.257.21:56:48.47#ibcon#read 4, iclass 40, count 0 2006.257.21:56:48.47#ibcon#about to read 5, iclass 40, count 0 2006.257.21:56:48.47#ibcon#read 5, iclass 40, count 0 2006.257.21:56:48.47#ibcon#about to read 6, iclass 40, count 0 2006.257.21:56:48.47#ibcon#read 6, iclass 40, count 0 2006.257.21:56:48.47#ibcon#end of sib2, iclass 40, count 0 2006.257.21:56:48.47#ibcon#*after write, iclass 40, count 0 2006.257.21:56:48.47#ibcon#*before return 0, iclass 40, count 0 2006.257.21:56:48.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:56:48.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.21:56:48.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.21:56:48.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.21:56:48.47$vck44/vblo=2,634.99 2006.257.21:56:48.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.21:56:48.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.21:56:48.47#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:48.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:48.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:48.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:48.47#ibcon#enter wrdev, iclass 4, count 0 2006.257.21:56:48.47#ibcon#first serial, iclass 4, count 0 2006.257.21:56:48.47#ibcon#enter sib2, iclass 4, count 0 2006.257.21:56:48.47#ibcon#flushed, iclass 4, count 0 2006.257.21:56:48.47#ibcon#about to write, iclass 4, count 0 2006.257.21:56:48.47#ibcon#wrote, iclass 4, count 0 2006.257.21:56:48.47#ibcon#about to read 3, iclass 4, count 0 2006.257.21:56:48.49#ibcon#read 3, iclass 4, count 0 2006.257.21:56:48.49#ibcon#about to read 4, iclass 4, count 0 2006.257.21:56:48.49#ibcon#read 4, iclass 4, count 0 2006.257.21:56:48.49#ibcon#about to read 5, iclass 4, count 0 2006.257.21:56:48.49#ibcon#read 5, iclass 4, count 0 2006.257.21:56:48.49#ibcon#about to read 6, iclass 4, count 0 2006.257.21:56:48.49#ibcon#read 6, iclass 4, count 0 2006.257.21:56:48.49#ibcon#end of sib2, iclass 4, count 0 2006.257.21:56:48.49#ibcon#*mode == 0, iclass 4, count 0 2006.257.21:56:48.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.21:56:48.49#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.21:56:48.49#ibcon#*before write, iclass 4, count 0 2006.257.21:56:48.49#ibcon#enter sib2, iclass 4, count 0 2006.257.21:56:48.49#ibcon#flushed, iclass 4, count 0 2006.257.21:56:48.49#ibcon#about to write, iclass 4, count 0 2006.257.21:56:48.49#ibcon#wrote, iclass 4, count 0 2006.257.21:56:48.49#ibcon#about to read 3, iclass 4, count 0 2006.257.21:56:48.53#ibcon#read 3, iclass 4, count 0 2006.257.21:56:48.53#ibcon#about to read 4, iclass 4, count 0 2006.257.21:56:48.53#ibcon#read 4, iclass 4, count 0 2006.257.21:56:48.53#ibcon#about to read 5, iclass 4, count 0 2006.257.21:56:48.53#ibcon#read 5, iclass 4, count 0 2006.257.21:56:48.53#ibcon#about to read 6, iclass 4, count 0 2006.257.21:56:48.53#ibcon#read 6, iclass 4, count 0 2006.257.21:56:48.53#ibcon#end of sib2, iclass 4, count 0 2006.257.21:56:48.53#ibcon#*after write, iclass 4, count 0 2006.257.21:56:48.53#ibcon#*before return 0, iclass 4, count 0 2006.257.21:56:48.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:48.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.21:56:48.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.21:56:48.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.21:56:48.53$vck44/vb=2,5 2006.257.21:56:48.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.21:56:48.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.21:56:48.53#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:48.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:48.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:48.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:48.59#ibcon#enter wrdev, iclass 6, count 2 2006.257.21:56:48.59#ibcon#first serial, iclass 6, count 2 2006.257.21:56:48.59#ibcon#enter sib2, iclass 6, count 2 2006.257.21:56:48.59#ibcon#flushed, iclass 6, count 2 2006.257.21:56:48.59#ibcon#about to write, iclass 6, count 2 2006.257.21:56:48.59#ibcon#wrote, iclass 6, count 2 2006.257.21:56:48.59#ibcon#about to read 3, iclass 6, count 2 2006.257.21:56:48.61#ibcon#read 3, iclass 6, count 2 2006.257.21:56:48.61#ibcon#about to read 4, iclass 6, count 2 2006.257.21:56:48.61#ibcon#read 4, iclass 6, count 2 2006.257.21:56:48.61#ibcon#about to read 5, iclass 6, count 2 2006.257.21:56:48.61#ibcon#read 5, iclass 6, count 2 2006.257.21:56:48.61#ibcon#about to read 6, iclass 6, count 2 2006.257.21:56:48.61#ibcon#read 6, iclass 6, count 2 2006.257.21:56:48.61#ibcon#end of sib2, iclass 6, count 2 2006.257.21:56:48.61#ibcon#*mode == 0, iclass 6, count 2 2006.257.21:56:48.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.21:56:48.61#ibcon#[27=AT02-05\r\n] 2006.257.21:56:48.61#ibcon#*before write, iclass 6, count 2 2006.257.21:56:48.61#ibcon#enter sib2, iclass 6, count 2 2006.257.21:56:48.61#ibcon#flushed, iclass 6, count 2 2006.257.21:56:48.61#ibcon#about to write, iclass 6, count 2 2006.257.21:56:48.61#ibcon#wrote, iclass 6, count 2 2006.257.21:56:48.61#ibcon#about to read 3, iclass 6, count 2 2006.257.21:56:48.64#ibcon#read 3, iclass 6, count 2 2006.257.21:56:48.64#ibcon#about to read 4, iclass 6, count 2 2006.257.21:56:48.64#ibcon#read 4, iclass 6, count 2 2006.257.21:56:48.64#ibcon#about to read 5, iclass 6, count 2 2006.257.21:56:48.64#ibcon#read 5, iclass 6, count 2 2006.257.21:56:48.64#ibcon#about to read 6, iclass 6, count 2 2006.257.21:56:48.64#ibcon#read 6, iclass 6, count 2 2006.257.21:56:48.64#ibcon#end of sib2, iclass 6, count 2 2006.257.21:56:48.64#ibcon#*after write, iclass 6, count 2 2006.257.21:56:48.64#ibcon#*before return 0, iclass 6, count 2 2006.257.21:56:48.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:48.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.21:56:48.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.21:56:48.64#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:48.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:48.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:48.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:48.76#ibcon#enter wrdev, iclass 6, count 0 2006.257.21:56:48.76#ibcon#first serial, iclass 6, count 0 2006.257.21:56:48.76#ibcon#enter sib2, iclass 6, count 0 2006.257.21:56:48.76#ibcon#flushed, iclass 6, count 0 2006.257.21:56:48.76#ibcon#about to write, iclass 6, count 0 2006.257.21:56:48.76#ibcon#wrote, iclass 6, count 0 2006.257.21:56:48.76#ibcon#about to read 3, iclass 6, count 0 2006.257.21:56:48.78#ibcon#read 3, iclass 6, count 0 2006.257.21:56:48.78#ibcon#about to read 4, iclass 6, count 0 2006.257.21:56:48.78#ibcon#read 4, iclass 6, count 0 2006.257.21:56:48.78#ibcon#about to read 5, iclass 6, count 0 2006.257.21:56:48.78#ibcon#read 5, iclass 6, count 0 2006.257.21:56:48.78#ibcon#about to read 6, iclass 6, count 0 2006.257.21:56:48.78#ibcon#read 6, iclass 6, count 0 2006.257.21:56:48.78#ibcon#end of sib2, iclass 6, count 0 2006.257.21:56:48.78#ibcon#*mode == 0, iclass 6, count 0 2006.257.21:56:48.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.21:56:48.78#ibcon#[27=USB\r\n] 2006.257.21:56:48.78#ibcon#*before write, iclass 6, count 0 2006.257.21:56:48.78#ibcon#enter sib2, iclass 6, count 0 2006.257.21:56:48.78#ibcon#flushed, iclass 6, count 0 2006.257.21:56:48.78#ibcon#about to write, iclass 6, count 0 2006.257.21:56:48.78#ibcon#wrote, iclass 6, count 0 2006.257.21:56:48.78#ibcon#about to read 3, iclass 6, count 0 2006.257.21:56:48.81#ibcon#read 3, iclass 6, count 0 2006.257.21:56:48.81#ibcon#about to read 4, iclass 6, count 0 2006.257.21:56:48.81#ibcon#read 4, iclass 6, count 0 2006.257.21:56:48.81#ibcon#about to read 5, iclass 6, count 0 2006.257.21:56:48.81#ibcon#read 5, iclass 6, count 0 2006.257.21:56:48.81#ibcon#about to read 6, iclass 6, count 0 2006.257.21:56:48.81#ibcon#read 6, iclass 6, count 0 2006.257.21:56:48.81#ibcon#end of sib2, iclass 6, count 0 2006.257.21:56:48.81#ibcon#*after write, iclass 6, count 0 2006.257.21:56:48.81#ibcon#*before return 0, iclass 6, count 0 2006.257.21:56:48.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:48.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.21:56:48.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.21:56:48.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.21:56:48.81$vck44/vblo=3,649.99 2006.257.21:56:48.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.21:56:48.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.21:56:48.81#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:48.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:48.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:48.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:48.81#ibcon#enter wrdev, iclass 10, count 0 2006.257.21:56:48.81#ibcon#first serial, iclass 10, count 0 2006.257.21:56:48.81#ibcon#enter sib2, iclass 10, count 0 2006.257.21:56:48.81#ibcon#flushed, iclass 10, count 0 2006.257.21:56:48.81#ibcon#about to write, iclass 10, count 0 2006.257.21:56:48.81#ibcon#wrote, iclass 10, count 0 2006.257.21:56:48.81#ibcon#about to read 3, iclass 10, count 0 2006.257.21:56:48.83#ibcon#read 3, iclass 10, count 0 2006.257.21:56:48.83#ibcon#about to read 4, iclass 10, count 0 2006.257.21:56:48.83#ibcon#read 4, iclass 10, count 0 2006.257.21:56:48.83#ibcon#about to read 5, iclass 10, count 0 2006.257.21:56:48.83#ibcon#read 5, iclass 10, count 0 2006.257.21:56:48.83#ibcon#about to read 6, iclass 10, count 0 2006.257.21:56:48.83#ibcon#read 6, iclass 10, count 0 2006.257.21:56:48.83#ibcon#end of sib2, iclass 10, count 0 2006.257.21:56:48.83#ibcon#*mode == 0, iclass 10, count 0 2006.257.21:56:48.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.21:56:48.83#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.21:56:48.83#ibcon#*before write, iclass 10, count 0 2006.257.21:56:48.83#ibcon#enter sib2, iclass 10, count 0 2006.257.21:56:48.83#ibcon#flushed, iclass 10, count 0 2006.257.21:56:48.83#ibcon#about to write, iclass 10, count 0 2006.257.21:56:48.83#ibcon#wrote, iclass 10, count 0 2006.257.21:56:48.83#ibcon#about to read 3, iclass 10, count 0 2006.257.21:56:48.87#ibcon#read 3, iclass 10, count 0 2006.257.21:56:48.87#ibcon#about to read 4, iclass 10, count 0 2006.257.21:56:48.87#ibcon#read 4, iclass 10, count 0 2006.257.21:56:48.87#ibcon#about to read 5, iclass 10, count 0 2006.257.21:56:48.87#ibcon#read 5, iclass 10, count 0 2006.257.21:56:48.87#ibcon#about to read 6, iclass 10, count 0 2006.257.21:56:48.87#ibcon#read 6, iclass 10, count 0 2006.257.21:56:48.87#ibcon#end of sib2, iclass 10, count 0 2006.257.21:56:48.87#ibcon#*after write, iclass 10, count 0 2006.257.21:56:48.87#ibcon#*before return 0, iclass 10, count 0 2006.257.21:56:48.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:48.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.21:56:48.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.21:56:48.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.21:56:48.87$vck44/vb=3,4 2006.257.21:56:48.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.21:56:48.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.21:56:48.87#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:48.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:48.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:48.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:48.93#ibcon#enter wrdev, iclass 12, count 2 2006.257.21:56:48.93#ibcon#first serial, iclass 12, count 2 2006.257.21:56:48.93#ibcon#enter sib2, iclass 12, count 2 2006.257.21:56:48.93#ibcon#flushed, iclass 12, count 2 2006.257.21:56:48.93#ibcon#about to write, iclass 12, count 2 2006.257.21:56:48.93#ibcon#wrote, iclass 12, count 2 2006.257.21:56:48.93#ibcon#about to read 3, iclass 12, count 2 2006.257.21:56:48.95#ibcon#read 3, iclass 12, count 2 2006.257.21:56:48.95#ibcon#about to read 4, iclass 12, count 2 2006.257.21:56:48.95#ibcon#read 4, iclass 12, count 2 2006.257.21:56:48.95#ibcon#about to read 5, iclass 12, count 2 2006.257.21:56:48.95#ibcon#read 5, iclass 12, count 2 2006.257.21:56:48.95#ibcon#about to read 6, iclass 12, count 2 2006.257.21:56:48.95#ibcon#read 6, iclass 12, count 2 2006.257.21:56:48.95#ibcon#end of sib2, iclass 12, count 2 2006.257.21:56:48.95#ibcon#*mode == 0, iclass 12, count 2 2006.257.21:56:48.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.21:56:48.95#ibcon#[27=AT03-04\r\n] 2006.257.21:56:48.95#ibcon#*before write, iclass 12, count 2 2006.257.21:56:48.95#ibcon#enter sib2, iclass 12, count 2 2006.257.21:56:48.95#ibcon#flushed, iclass 12, count 2 2006.257.21:56:48.95#ibcon#about to write, iclass 12, count 2 2006.257.21:56:48.95#ibcon#wrote, iclass 12, count 2 2006.257.21:56:48.95#ibcon#about to read 3, iclass 12, count 2 2006.257.21:56:48.98#ibcon#read 3, iclass 12, count 2 2006.257.21:56:48.98#ibcon#about to read 4, iclass 12, count 2 2006.257.21:56:48.98#ibcon#read 4, iclass 12, count 2 2006.257.21:56:48.98#ibcon#about to read 5, iclass 12, count 2 2006.257.21:56:48.98#ibcon#read 5, iclass 12, count 2 2006.257.21:56:48.98#ibcon#about to read 6, iclass 12, count 2 2006.257.21:56:48.98#ibcon#read 6, iclass 12, count 2 2006.257.21:56:48.98#ibcon#end of sib2, iclass 12, count 2 2006.257.21:56:48.98#ibcon#*after write, iclass 12, count 2 2006.257.21:56:48.98#ibcon#*before return 0, iclass 12, count 2 2006.257.21:56:48.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:48.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.21:56:48.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.21:56:48.98#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:48.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:49.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:49.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:49.10#ibcon#enter wrdev, iclass 12, count 0 2006.257.21:56:49.10#ibcon#first serial, iclass 12, count 0 2006.257.21:56:49.10#ibcon#enter sib2, iclass 12, count 0 2006.257.21:56:49.10#ibcon#flushed, iclass 12, count 0 2006.257.21:56:49.10#ibcon#about to write, iclass 12, count 0 2006.257.21:56:49.10#ibcon#wrote, iclass 12, count 0 2006.257.21:56:49.10#ibcon#about to read 3, iclass 12, count 0 2006.257.21:56:49.12#ibcon#read 3, iclass 12, count 0 2006.257.21:56:49.12#ibcon#about to read 4, iclass 12, count 0 2006.257.21:56:49.12#ibcon#read 4, iclass 12, count 0 2006.257.21:56:49.12#ibcon#about to read 5, iclass 12, count 0 2006.257.21:56:49.12#ibcon#read 5, iclass 12, count 0 2006.257.21:56:49.12#ibcon#about to read 6, iclass 12, count 0 2006.257.21:56:49.12#ibcon#read 6, iclass 12, count 0 2006.257.21:56:49.12#ibcon#end of sib2, iclass 12, count 0 2006.257.21:56:49.12#ibcon#*mode == 0, iclass 12, count 0 2006.257.21:56:49.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.21:56:49.12#ibcon#[27=USB\r\n] 2006.257.21:56:49.12#ibcon#*before write, iclass 12, count 0 2006.257.21:56:49.12#ibcon#enter sib2, iclass 12, count 0 2006.257.21:56:49.12#ibcon#flushed, iclass 12, count 0 2006.257.21:56:49.12#ibcon#about to write, iclass 12, count 0 2006.257.21:56:49.12#ibcon#wrote, iclass 12, count 0 2006.257.21:56:49.12#ibcon#about to read 3, iclass 12, count 0 2006.257.21:56:49.15#ibcon#read 3, iclass 12, count 0 2006.257.21:56:49.15#ibcon#about to read 4, iclass 12, count 0 2006.257.21:56:49.15#ibcon#read 4, iclass 12, count 0 2006.257.21:56:49.15#ibcon#about to read 5, iclass 12, count 0 2006.257.21:56:49.15#ibcon#read 5, iclass 12, count 0 2006.257.21:56:49.15#ibcon#about to read 6, iclass 12, count 0 2006.257.21:56:49.15#ibcon#read 6, iclass 12, count 0 2006.257.21:56:49.15#ibcon#end of sib2, iclass 12, count 0 2006.257.21:56:49.15#ibcon#*after write, iclass 12, count 0 2006.257.21:56:49.15#ibcon#*before return 0, iclass 12, count 0 2006.257.21:56:49.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:49.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.21:56:49.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.21:56:49.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.21:56:49.15$vck44/vblo=4,679.99 2006.257.21:56:49.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.21:56:49.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.21:56:49.15#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:49.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:49.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:49.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:49.15#ibcon#enter wrdev, iclass 14, count 0 2006.257.21:56:49.15#ibcon#first serial, iclass 14, count 0 2006.257.21:56:49.15#ibcon#enter sib2, iclass 14, count 0 2006.257.21:56:49.15#ibcon#flushed, iclass 14, count 0 2006.257.21:56:49.15#ibcon#about to write, iclass 14, count 0 2006.257.21:56:49.15#ibcon#wrote, iclass 14, count 0 2006.257.21:56:49.15#ibcon#about to read 3, iclass 14, count 0 2006.257.21:56:49.17#ibcon#read 3, iclass 14, count 0 2006.257.21:56:49.17#ibcon#about to read 4, iclass 14, count 0 2006.257.21:56:49.17#ibcon#read 4, iclass 14, count 0 2006.257.21:56:49.17#ibcon#about to read 5, iclass 14, count 0 2006.257.21:56:49.17#ibcon#read 5, iclass 14, count 0 2006.257.21:56:49.17#ibcon#about to read 6, iclass 14, count 0 2006.257.21:56:49.17#ibcon#read 6, iclass 14, count 0 2006.257.21:56:49.17#ibcon#end of sib2, iclass 14, count 0 2006.257.21:56:49.17#ibcon#*mode == 0, iclass 14, count 0 2006.257.21:56:49.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.21:56:49.17#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.21:56:49.17#ibcon#*before write, iclass 14, count 0 2006.257.21:56:49.17#ibcon#enter sib2, iclass 14, count 0 2006.257.21:56:49.17#ibcon#flushed, iclass 14, count 0 2006.257.21:56:49.17#ibcon#about to write, iclass 14, count 0 2006.257.21:56:49.17#ibcon#wrote, iclass 14, count 0 2006.257.21:56:49.17#ibcon#about to read 3, iclass 14, count 0 2006.257.21:56:49.21#ibcon#read 3, iclass 14, count 0 2006.257.21:56:49.21#ibcon#about to read 4, iclass 14, count 0 2006.257.21:56:49.21#ibcon#read 4, iclass 14, count 0 2006.257.21:56:49.21#ibcon#about to read 5, iclass 14, count 0 2006.257.21:56:49.21#ibcon#read 5, iclass 14, count 0 2006.257.21:56:49.21#ibcon#about to read 6, iclass 14, count 0 2006.257.21:56:49.21#ibcon#read 6, iclass 14, count 0 2006.257.21:56:49.21#ibcon#end of sib2, iclass 14, count 0 2006.257.21:56:49.21#ibcon#*after write, iclass 14, count 0 2006.257.21:56:49.21#ibcon#*before return 0, iclass 14, count 0 2006.257.21:56:49.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:49.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.21:56:49.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.21:56:49.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.21:56:49.21$vck44/vb=4,5 2006.257.21:56:49.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.21:56:49.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.21:56:49.21#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:49.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:49.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:49.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:49.27#ibcon#enter wrdev, iclass 16, count 2 2006.257.21:56:49.27#ibcon#first serial, iclass 16, count 2 2006.257.21:56:49.27#ibcon#enter sib2, iclass 16, count 2 2006.257.21:56:49.27#ibcon#flushed, iclass 16, count 2 2006.257.21:56:49.27#ibcon#about to write, iclass 16, count 2 2006.257.21:56:49.27#ibcon#wrote, iclass 16, count 2 2006.257.21:56:49.27#ibcon#about to read 3, iclass 16, count 2 2006.257.21:56:49.29#ibcon#read 3, iclass 16, count 2 2006.257.21:56:49.29#ibcon#about to read 4, iclass 16, count 2 2006.257.21:56:49.29#ibcon#read 4, iclass 16, count 2 2006.257.21:56:49.29#ibcon#about to read 5, iclass 16, count 2 2006.257.21:56:49.29#ibcon#read 5, iclass 16, count 2 2006.257.21:56:49.29#ibcon#about to read 6, iclass 16, count 2 2006.257.21:56:49.29#ibcon#read 6, iclass 16, count 2 2006.257.21:56:49.29#ibcon#end of sib2, iclass 16, count 2 2006.257.21:56:49.29#ibcon#*mode == 0, iclass 16, count 2 2006.257.21:56:49.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.21:56:49.29#ibcon#[27=AT04-05\r\n] 2006.257.21:56:49.29#ibcon#*before write, iclass 16, count 2 2006.257.21:56:49.29#ibcon#enter sib2, iclass 16, count 2 2006.257.21:56:49.29#ibcon#flushed, iclass 16, count 2 2006.257.21:56:49.29#ibcon#about to write, iclass 16, count 2 2006.257.21:56:49.29#ibcon#wrote, iclass 16, count 2 2006.257.21:56:49.29#ibcon#about to read 3, iclass 16, count 2 2006.257.21:56:49.32#ibcon#read 3, iclass 16, count 2 2006.257.21:56:49.32#ibcon#about to read 4, iclass 16, count 2 2006.257.21:56:49.32#ibcon#read 4, iclass 16, count 2 2006.257.21:56:49.32#ibcon#about to read 5, iclass 16, count 2 2006.257.21:56:49.32#ibcon#read 5, iclass 16, count 2 2006.257.21:56:49.32#ibcon#about to read 6, iclass 16, count 2 2006.257.21:56:49.32#ibcon#read 6, iclass 16, count 2 2006.257.21:56:49.32#ibcon#end of sib2, iclass 16, count 2 2006.257.21:56:49.32#ibcon#*after write, iclass 16, count 2 2006.257.21:56:49.32#ibcon#*before return 0, iclass 16, count 2 2006.257.21:56:49.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:49.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.21:56:49.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.21:56:49.32#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:49.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:49.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:49.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:49.44#ibcon#enter wrdev, iclass 16, count 0 2006.257.21:56:49.44#ibcon#first serial, iclass 16, count 0 2006.257.21:56:49.44#ibcon#enter sib2, iclass 16, count 0 2006.257.21:56:49.44#ibcon#flushed, iclass 16, count 0 2006.257.21:56:49.44#ibcon#about to write, iclass 16, count 0 2006.257.21:56:49.44#ibcon#wrote, iclass 16, count 0 2006.257.21:56:49.44#ibcon#about to read 3, iclass 16, count 0 2006.257.21:56:49.46#ibcon#read 3, iclass 16, count 0 2006.257.21:56:49.46#ibcon#about to read 4, iclass 16, count 0 2006.257.21:56:49.46#ibcon#read 4, iclass 16, count 0 2006.257.21:56:49.46#ibcon#about to read 5, iclass 16, count 0 2006.257.21:56:49.46#ibcon#read 5, iclass 16, count 0 2006.257.21:56:49.46#ibcon#about to read 6, iclass 16, count 0 2006.257.21:56:49.46#ibcon#read 6, iclass 16, count 0 2006.257.21:56:49.46#ibcon#end of sib2, iclass 16, count 0 2006.257.21:56:49.46#ibcon#*mode == 0, iclass 16, count 0 2006.257.21:56:49.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.21:56:49.46#ibcon#[27=USB\r\n] 2006.257.21:56:49.46#ibcon#*before write, iclass 16, count 0 2006.257.21:56:49.46#ibcon#enter sib2, iclass 16, count 0 2006.257.21:56:49.46#ibcon#flushed, iclass 16, count 0 2006.257.21:56:49.46#ibcon#about to write, iclass 16, count 0 2006.257.21:56:49.46#ibcon#wrote, iclass 16, count 0 2006.257.21:56:49.46#ibcon#about to read 3, iclass 16, count 0 2006.257.21:56:49.49#ibcon#read 3, iclass 16, count 0 2006.257.21:56:49.49#ibcon#about to read 4, iclass 16, count 0 2006.257.21:56:49.49#ibcon#read 4, iclass 16, count 0 2006.257.21:56:49.49#ibcon#about to read 5, iclass 16, count 0 2006.257.21:56:49.49#ibcon#read 5, iclass 16, count 0 2006.257.21:56:49.49#ibcon#about to read 6, iclass 16, count 0 2006.257.21:56:49.49#ibcon#read 6, iclass 16, count 0 2006.257.21:56:49.49#ibcon#end of sib2, iclass 16, count 0 2006.257.21:56:49.49#ibcon#*after write, iclass 16, count 0 2006.257.21:56:49.49#ibcon#*before return 0, iclass 16, count 0 2006.257.21:56:49.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:49.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.21:56:49.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.21:56:49.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.21:56:49.49$vck44/vblo=5,709.99 2006.257.21:56:49.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.21:56:49.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.21:56:49.49#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:49.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:49.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:49.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:49.49#ibcon#enter wrdev, iclass 18, count 0 2006.257.21:56:49.49#ibcon#first serial, iclass 18, count 0 2006.257.21:56:49.49#ibcon#enter sib2, iclass 18, count 0 2006.257.21:56:49.49#ibcon#flushed, iclass 18, count 0 2006.257.21:56:49.49#ibcon#about to write, iclass 18, count 0 2006.257.21:56:49.49#ibcon#wrote, iclass 18, count 0 2006.257.21:56:49.49#ibcon#about to read 3, iclass 18, count 0 2006.257.21:56:49.51#ibcon#read 3, iclass 18, count 0 2006.257.21:56:49.51#ibcon#about to read 4, iclass 18, count 0 2006.257.21:56:49.51#ibcon#read 4, iclass 18, count 0 2006.257.21:56:49.51#ibcon#about to read 5, iclass 18, count 0 2006.257.21:56:49.51#ibcon#read 5, iclass 18, count 0 2006.257.21:56:49.51#ibcon#about to read 6, iclass 18, count 0 2006.257.21:56:49.51#ibcon#read 6, iclass 18, count 0 2006.257.21:56:49.51#ibcon#end of sib2, iclass 18, count 0 2006.257.21:56:49.51#ibcon#*mode == 0, iclass 18, count 0 2006.257.21:56:49.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.21:56:49.51#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.21:56:49.51#ibcon#*before write, iclass 18, count 0 2006.257.21:56:49.51#ibcon#enter sib2, iclass 18, count 0 2006.257.21:56:49.51#ibcon#flushed, iclass 18, count 0 2006.257.21:56:49.51#ibcon#about to write, iclass 18, count 0 2006.257.21:56:49.51#ibcon#wrote, iclass 18, count 0 2006.257.21:56:49.51#ibcon#about to read 3, iclass 18, count 0 2006.257.21:56:49.55#ibcon#read 3, iclass 18, count 0 2006.257.21:56:49.55#ibcon#about to read 4, iclass 18, count 0 2006.257.21:56:49.55#ibcon#read 4, iclass 18, count 0 2006.257.21:56:49.55#ibcon#about to read 5, iclass 18, count 0 2006.257.21:56:49.55#ibcon#read 5, iclass 18, count 0 2006.257.21:56:49.55#ibcon#about to read 6, iclass 18, count 0 2006.257.21:56:49.55#ibcon#read 6, iclass 18, count 0 2006.257.21:56:49.55#ibcon#end of sib2, iclass 18, count 0 2006.257.21:56:49.55#ibcon#*after write, iclass 18, count 0 2006.257.21:56:49.55#ibcon#*before return 0, iclass 18, count 0 2006.257.21:56:49.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:49.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.21:56:49.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.21:56:49.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.21:56:49.55$vck44/vb=5,4 2006.257.21:56:49.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.21:56:49.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.21:56:49.55#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:49.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:49.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:49.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:49.61#ibcon#enter wrdev, iclass 20, count 2 2006.257.21:56:49.61#ibcon#first serial, iclass 20, count 2 2006.257.21:56:49.61#ibcon#enter sib2, iclass 20, count 2 2006.257.21:56:49.61#ibcon#flushed, iclass 20, count 2 2006.257.21:56:49.61#ibcon#about to write, iclass 20, count 2 2006.257.21:56:49.61#ibcon#wrote, iclass 20, count 2 2006.257.21:56:49.61#ibcon#about to read 3, iclass 20, count 2 2006.257.21:56:49.63#ibcon#read 3, iclass 20, count 2 2006.257.21:56:49.63#ibcon#about to read 4, iclass 20, count 2 2006.257.21:56:49.63#ibcon#read 4, iclass 20, count 2 2006.257.21:56:49.63#ibcon#about to read 5, iclass 20, count 2 2006.257.21:56:49.63#ibcon#read 5, iclass 20, count 2 2006.257.21:56:49.63#ibcon#about to read 6, iclass 20, count 2 2006.257.21:56:49.63#ibcon#read 6, iclass 20, count 2 2006.257.21:56:49.63#ibcon#end of sib2, iclass 20, count 2 2006.257.21:56:49.63#ibcon#*mode == 0, iclass 20, count 2 2006.257.21:56:49.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.21:56:49.63#ibcon#[27=AT05-04\r\n] 2006.257.21:56:49.63#ibcon#*before write, iclass 20, count 2 2006.257.21:56:49.63#ibcon#enter sib2, iclass 20, count 2 2006.257.21:56:49.63#ibcon#flushed, iclass 20, count 2 2006.257.21:56:49.63#ibcon#about to write, iclass 20, count 2 2006.257.21:56:49.63#ibcon#wrote, iclass 20, count 2 2006.257.21:56:49.63#ibcon#about to read 3, iclass 20, count 2 2006.257.21:56:49.66#ibcon#read 3, iclass 20, count 2 2006.257.21:56:49.66#ibcon#about to read 4, iclass 20, count 2 2006.257.21:56:49.66#ibcon#read 4, iclass 20, count 2 2006.257.21:56:49.66#ibcon#about to read 5, iclass 20, count 2 2006.257.21:56:49.66#ibcon#read 5, iclass 20, count 2 2006.257.21:56:49.66#ibcon#about to read 6, iclass 20, count 2 2006.257.21:56:49.66#ibcon#read 6, iclass 20, count 2 2006.257.21:56:49.66#ibcon#end of sib2, iclass 20, count 2 2006.257.21:56:49.66#ibcon#*after write, iclass 20, count 2 2006.257.21:56:49.66#ibcon#*before return 0, iclass 20, count 2 2006.257.21:56:49.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:49.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.21:56:49.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.21:56:49.66#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:49.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:49.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:49.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:49.78#ibcon#enter wrdev, iclass 20, count 0 2006.257.21:56:49.78#ibcon#first serial, iclass 20, count 0 2006.257.21:56:49.78#ibcon#enter sib2, iclass 20, count 0 2006.257.21:56:49.78#ibcon#flushed, iclass 20, count 0 2006.257.21:56:49.78#ibcon#about to write, iclass 20, count 0 2006.257.21:56:49.78#ibcon#wrote, iclass 20, count 0 2006.257.21:56:49.78#ibcon#about to read 3, iclass 20, count 0 2006.257.21:56:49.80#ibcon#read 3, iclass 20, count 0 2006.257.21:56:49.80#ibcon#about to read 4, iclass 20, count 0 2006.257.21:56:49.80#ibcon#read 4, iclass 20, count 0 2006.257.21:56:49.80#ibcon#about to read 5, iclass 20, count 0 2006.257.21:56:49.80#ibcon#read 5, iclass 20, count 0 2006.257.21:56:49.80#ibcon#about to read 6, iclass 20, count 0 2006.257.21:56:49.80#ibcon#read 6, iclass 20, count 0 2006.257.21:56:49.80#ibcon#end of sib2, iclass 20, count 0 2006.257.21:56:49.80#ibcon#*mode == 0, iclass 20, count 0 2006.257.21:56:49.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.21:56:49.80#ibcon#[27=USB\r\n] 2006.257.21:56:49.80#ibcon#*before write, iclass 20, count 0 2006.257.21:56:49.80#ibcon#enter sib2, iclass 20, count 0 2006.257.21:56:49.80#ibcon#flushed, iclass 20, count 0 2006.257.21:56:49.80#ibcon#about to write, iclass 20, count 0 2006.257.21:56:49.80#ibcon#wrote, iclass 20, count 0 2006.257.21:56:49.80#ibcon#about to read 3, iclass 20, count 0 2006.257.21:56:49.83#ibcon#read 3, iclass 20, count 0 2006.257.21:56:49.83#ibcon#about to read 4, iclass 20, count 0 2006.257.21:56:49.83#ibcon#read 4, iclass 20, count 0 2006.257.21:56:49.83#ibcon#about to read 5, iclass 20, count 0 2006.257.21:56:49.83#ibcon#read 5, iclass 20, count 0 2006.257.21:56:49.83#ibcon#about to read 6, iclass 20, count 0 2006.257.21:56:49.83#ibcon#read 6, iclass 20, count 0 2006.257.21:56:49.83#ibcon#end of sib2, iclass 20, count 0 2006.257.21:56:49.83#ibcon#*after write, iclass 20, count 0 2006.257.21:56:49.83#ibcon#*before return 0, iclass 20, count 0 2006.257.21:56:49.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:49.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.21:56:49.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.21:56:49.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.21:56:49.83$vck44/vblo=6,719.99 2006.257.21:56:49.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.21:56:49.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.21:56:49.83#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:49.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:49.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:49.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:49.83#ibcon#enter wrdev, iclass 22, count 0 2006.257.21:56:49.83#ibcon#first serial, iclass 22, count 0 2006.257.21:56:49.83#ibcon#enter sib2, iclass 22, count 0 2006.257.21:56:49.83#ibcon#flushed, iclass 22, count 0 2006.257.21:56:49.83#ibcon#about to write, iclass 22, count 0 2006.257.21:56:49.83#ibcon#wrote, iclass 22, count 0 2006.257.21:56:49.83#ibcon#about to read 3, iclass 22, count 0 2006.257.21:56:49.85#ibcon#read 3, iclass 22, count 0 2006.257.21:56:49.85#ibcon#about to read 4, iclass 22, count 0 2006.257.21:56:49.85#ibcon#read 4, iclass 22, count 0 2006.257.21:56:49.85#ibcon#about to read 5, iclass 22, count 0 2006.257.21:56:49.85#ibcon#read 5, iclass 22, count 0 2006.257.21:56:49.85#ibcon#about to read 6, iclass 22, count 0 2006.257.21:56:49.85#ibcon#read 6, iclass 22, count 0 2006.257.21:56:49.85#ibcon#end of sib2, iclass 22, count 0 2006.257.21:56:49.85#ibcon#*mode == 0, iclass 22, count 0 2006.257.21:56:49.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.21:56:49.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.21:56:49.85#ibcon#*before write, iclass 22, count 0 2006.257.21:56:49.85#ibcon#enter sib2, iclass 22, count 0 2006.257.21:56:49.85#ibcon#flushed, iclass 22, count 0 2006.257.21:56:49.85#ibcon#about to write, iclass 22, count 0 2006.257.21:56:49.85#ibcon#wrote, iclass 22, count 0 2006.257.21:56:49.85#ibcon#about to read 3, iclass 22, count 0 2006.257.21:56:49.89#ibcon#read 3, iclass 22, count 0 2006.257.21:56:49.89#ibcon#about to read 4, iclass 22, count 0 2006.257.21:56:49.89#ibcon#read 4, iclass 22, count 0 2006.257.21:56:49.89#ibcon#about to read 5, iclass 22, count 0 2006.257.21:56:49.89#ibcon#read 5, iclass 22, count 0 2006.257.21:56:49.89#ibcon#about to read 6, iclass 22, count 0 2006.257.21:56:49.89#ibcon#read 6, iclass 22, count 0 2006.257.21:56:49.89#ibcon#end of sib2, iclass 22, count 0 2006.257.21:56:49.89#ibcon#*after write, iclass 22, count 0 2006.257.21:56:49.89#ibcon#*before return 0, iclass 22, count 0 2006.257.21:56:49.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:49.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.21:56:49.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.21:56:49.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.21:56:49.89$vck44/vb=6,4 2006.257.21:56:49.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.21:56:49.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.21:56:49.89#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:49.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:49.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:49.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:49.95#ibcon#enter wrdev, iclass 24, count 2 2006.257.21:56:49.95#ibcon#first serial, iclass 24, count 2 2006.257.21:56:49.95#ibcon#enter sib2, iclass 24, count 2 2006.257.21:56:49.95#ibcon#flushed, iclass 24, count 2 2006.257.21:56:49.95#ibcon#about to write, iclass 24, count 2 2006.257.21:56:49.95#ibcon#wrote, iclass 24, count 2 2006.257.21:56:49.95#ibcon#about to read 3, iclass 24, count 2 2006.257.21:56:49.97#ibcon#read 3, iclass 24, count 2 2006.257.21:56:49.97#ibcon#about to read 4, iclass 24, count 2 2006.257.21:56:49.97#ibcon#read 4, iclass 24, count 2 2006.257.21:56:49.97#ibcon#about to read 5, iclass 24, count 2 2006.257.21:56:49.97#ibcon#read 5, iclass 24, count 2 2006.257.21:56:49.97#ibcon#about to read 6, iclass 24, count 2 2006.257.21:56:49.97#ibcon#read 6, iclass 24, count 2 2006.257.21:56:49.97#ibcon#end of sib2, iclass 24, count 2 2006.257.21:56:49.97#ibcon#*mode == 0, iclass 24, count 2 2006.257.21:56:49.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.21:56:49.97#ibcon#[27=AT06-04\r\n] 2006.257.21:56:49.97#ibcon#*before write, iclass 24, count 2 2006.257.21:56:49.97#ibcon#enter sib2, iclass 24, count 2 2006.257.21:56:49.97#ibcon#flushed, iclass 24, count 2 2006.257.21:56:49.97#ibcon#about to write, iclass 24, count 2 2006.257.21:56:49.97#ibcon#wrote, iclass 24, count 2 2006.257.21:56:49.97#ibcon#about to read 3, iclass 24, count 2 2006.257.21:56:50.00#ibcon#read 3, iclass 24, count 2 2006.257.21:56:50.00#ibcon#about to read 4, iclass 24, count 2 2006.257.21:56:50.00#ibcon#read 4, iclass 24, count 2 2006.257.21:56:50.00#ibcon#about to read 5, iclass 24, count 2 2006.257.21:56:50.00#ibcon#read 5, iclass 24, count 2 2006.257.21:56:50.00#ibcon#about to read 6, iclass 24, count 2 2006.257.21:56:50.00#ibcon#read 6, iclass 24, count 2 2006.257.21:56:50.00#ibcon#end of sib2, iclass 24, count 2 2006.257.21:56:50.00#ibcon#*after write, iclass 24, count 2 2006.257.21:56:50.00#ibcon#*before return 0, iclass 24, count 2 2006.257.21:56:50.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:50.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.21:56:50.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.21:56:50.00#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:50.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:50.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:50.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:50.12#ibcon#enter wrdev, iclass 24, count 0 2006.257.21:56:50.12#ibcon#first serial, iclass 24, count 0 2006.257.21:56:50.12#ibcon#enter sib2, iclass 24, count 0 2006.257.21:56:50.12#ibcon#flushed, iclass 24, count 0 2006.257.21:56:50.12#ibcon#about to write, iclass 24, count 0 2006.257.21:56:50.12#ibcon#wrote, iclass 24, count 0 2006.257.21:56:50.12#ibcon#about to read 3, iclass 24, count 0 2006.257.21:56:50.14#ibcon#read 3, iclass 24, count 0 2006.257.21:56:50.14#ibcon#about to read 4, iclass 24, count 0 2006.257.21:56:50.14#ibcon#read 4, iclass 24, count 0 2006.257.21:56:50.14#ibcon#about to read 5, iclass 24, count 0 2006.257.21:56:50.14#ibcon#read 5, iclass 24, count 0 2006.257.21:56:50.14#ibcon#about to read 6, iclass 24, count 0 2006.257.21:56:50.14#ibcon#read 6, iclass 24, count 0 2006.257.21:56:50.14#ibcon#end of sib2, iclass 24, count 0 2006.257.21:56:50.14#ibcon#*mode == 0, iclass 24, count 0 2006.257.21:56:50.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.21:56:50.14#ibcon#[27=USB\r\n] 2006.257.21:56:50.14#ibcon#*before write, iclass 24, count 0 2006.257.21:56:50.14#ibcon#enter sib2, iclass 24, count 0 2006.257.21:56:50.14#ibcon#flushed, iclass 24, count 0 2006.257.21:56:50.14#ibcon#about to write, iclass 24, count 0 2006.257.21:56:50.14#ibcon#wrote, iclass 24, count 0 2006.257.21:56:50.14#ibcon#about to read 3, iclass 24, count 0 2006.257.21:56:50.17#ibcon#read 3, iclass 24, count 0 2006.257.21:56:50.17#ibcon#about to read 4, iclass 24, count 0 2006.257.21:56:50.17#ibcon#read 4, iclass 24, count 0 2006.257.21:56:50.17#ibcon#about to read 5, iclass 24, count 0 2006.257.21:56:50.17#ibcon#read 5, iclass 24, count 0 2006.257.21:56:50.17#ibcon#about to read 6, iclass 24, count 0 2006.257.21:56:50.17#ibcon#read 6, iclass 24, count 0 2006.257.21:56:50.17#ibcon#end of sib2, iclass 24, count 0 2006.257.21:56:50.17#ibcon#*after write, iclass 24, count 0 2006.257.21:56:50.17#ibcon#*before return 0, iclass 24, count 0 2006.257.21:56:50.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:50.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.21:56:50.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.21:56:50.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.21:56:50.17$vck44/vblo=7,734.99 2006.257.21:56:50.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.21:56:50.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.21:56:50.17#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:50.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:50.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:50.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:50.17#ibcon#enter wrdev, iclass 26, count 0 2006.257.21:56:50.17#ibcon#first serial, iclass 26, count 0 2006.257.21:56:50.17#ibcon#enter sib2, iclass 26, count 0 2006.257.21:56:50.17#ibcon#flushed, iclass 26, count 0 2006.257.21:56:50.17#ibcon#about to write, iclass 26, count 0 2006.257.21:56:50.17#ibcon#wrote, iclass 26, count 0 2006.257.21:56:50.17#ibcon#about to read 3, iclass 26, count 0 2006.257.21:56:50.19#ibcon#read 3, iclass 26, count 0 2006.257.21:56:50.19#ibcon#about to read 4, iclass 26, count 0 2006.257.21:56:50.19#ibcon#read 4, iclass 26, count 0 2006.257.21:56:50.19#ibcon#about to read 5, iclass 26, count 0 2006.257.21:56:50.19#ibcon#read 5, iclass 26, count 0 2006.257.21:56:50.19#ibcon#about to read 6, iclass 26, count 0 2006.257.21:56:50.19#ibcon#read 6, iclass 26, count 0 2006.257.21:56:50.19#ibcon#end of sib2, iclass 26, count 0 2006.257.21:56:50.19#ibcon#*mode == 0, iclass 26, count 0 2006.257.21:56:50.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.21:56:50.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.21:56:50.19#ibcon#*before write, iclass 26, count 0 2006.257.21:56:50.19#ibcon#enter sib2, iclass 26, count 0 2006.257.21:56:50.19#ibcon#flushed, iclass 26, count 0 2006.257.21:56:50.19#ibcon#about to write, iclass 26, count 0 2006.257.21:56:50.19#ibcon#wrote, iclass 26, count 0 2006.257.21:56:50.19#ibcon#about to read 3, iclass 26, count 0 2006.257.21:56:50.23#ibcon#read 3, iclass 26, count 0 2006.257.21:56:50.23#ibcon#about to read 4, iclass 26, count 0 2006.257.21:56:50.23#ibcon#read 4, iclass 26, count 0 2006.257.21:56:50.23#ibcon#about to read 5, iclass 26, count 0 2006.257.21:56:50.23#ibcon#read 5, iclass 26, count 0 2006.257.21:56:50.23#ibcon#about to read 6, iclass 26, count 0 2006.257.21:56:50.23#ibcon#read 6, iclass 26, count 0 2006.257.21:56:50.23#ibcon#end of sib2, iclass 26, count 0 2006.257.21:56:50.23#ibcon#*after write, iclass 26, count 0 2006.257.21:56:50.23#ibcon#*before return 0, iclass 26, count 0 2006.257.21:56:50.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:50.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.21:56:50.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.21:56:50.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.21:56:50.23$vck44/vb=7,4 2006.257.21:56:50.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.21:56:50.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.21:56:50.23#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:50.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:50.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:50.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:50.29#ibcon#enter wrdev, iclass 28, count 2 2006.257.21:56:50.29#ibcon#first serial, iclass 28, count 2 2006.257.21:56:50.29#ibcon#enter sib2, iclass 28, count 2 2006.257.21:56:50.29#ibcon#flushed, iclass 28, count 2 2006.257.21:56:50.29#ibcon#about to write, iclass 28, count 2 2006.257.21:56:50.29#ibcon#wrote, iclass 28, count 2 2006.257.21:56:50.29#ibcon#about to read 3, iclass 28, count 2 2006.257.21:56:50.31#ibcon#read 3, iclass 28, count 2 2006.257.21:56:50.31#ibcon#about to read 4, iclass 28, count 2 2006.257.21:56:50.31#ibcon#read 4, iclass 28, count 2 2006.257.21:56:50.31#ibcon#about to read 5, iclass 28, count 2 2006.257.21:56:50.31#ibcon#read 5, iclass 28, count 2 2006.257.21:56:50.31#ibcon#about to read 6, iclass 28, count 2 2006.257.21:56:50.31#ibcon#read 6, iclass 28, count 2 2006.257.21:56:50.31#ibcon#end of sib2, iclass 28, count 2 2006.257.21:56:50.31#ibcon#*mode == 0, iclass 28, count 2 2006.257.21:56:50.31#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.21:56:50.31#ibcon#[27=AT07-04\r\n] 2006.257.21:56:50.31#ibcon#*before write, iclass 28, count 2 2006.257.21:56:50.31#ibcon#enter sib2, iclass 28, count 2 2006.257.21:56:50.31#ibcon#flushed, iclass 28, count 2 2006.257.21:56:50.31#ibcon#about to write, iclass 28, count 2 2006.257.21:56:50.31#ibcon#wrote, iclass 28, count 2 2006.257.21:56:50.31#ibcon#about to read 3, iclass 28, count 2 2006.257.21:56:50.34#ibcon#read 3, iclass 28, count 2 2006.257.21:56:50.34#ibcon#about to read 4, iclass 28, count 2 2006.257.21:56:50.34#ibcon#read 4, iclass 28, count 2 2006.257.21:56:50.34#ibcon#about to read 5, iclass 28, count 2 2006.257.21:56:50.34#ibcon#read 5, iclass 28, count 2 2006.257.21:56:50.34#ibcon#about to read 6, iclass 28, count 2 2006.257.21:56:50.34#ibcon#read 6, iclass 28, count 2 2006.257.21:56:50.34#ibcon#end of sib2, iclass 28, count 2 2006.257.21:56:50.34#ibcon#*after write, iclass 28, count 2 2006.257.21:56:50.34#ibcon#*before return 0, iclass 28, count 2 2006.257.21:56:50.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:50.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.21:56:50.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.21:56:50.34#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:50.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:50.46#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:50.46#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:50.46#ibcon#enter wrdev, iclass 28, count 0 2006.257.21:56:50.46#ibcon#first serial, iclass 28, count 0 2006.257.21:56:50.46#ibcon#enter sib2, iclass 28, count 0 2006.257.21:56:50.46#ibcon#flushed, iclass 28, count 0 2006.257.21:56:50.46#ibcon#about to write, iclass 28, count 0 2006.257.21:56:50.46#ibcon#wrote, iclass 28, count 0 2006.257.21:56:50.46#ibcon#about to read 3, iclass 28, count 0 2006.257.21:56:50.48#ibcon#read 3, iclass 28, count 0 2006.257.21:56:50.48#ibcon#about to read 4, iclass 28, count 0 2006.257.21:56:50.48#ibcon#read 4, iclass 28, count 0 2006.257.21:56:50.48#ibcon#about to read 5, iclass 28, count 0 2006.257.21:56:50.48#ibcon#read 5, iclass 28, count 0 2006.257.21:56:50.48#ibcon#about to read 6, iclass 28, count 0 2006.257.21:56:50.48#ibcon#read 6, iclass 28, count 0 2006.257.21:56:50.48#ibcon#end of sib2, iclass 28, count 0 2006.257.21:56:50.48#ibcon#*mode == 0, iclass 28, count 0 2006.257.21:56:50.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.21:56:50.48#ibcon#[27=USB\r\n] 2006.257.21:56:50.48#ibcon#*before write, iclass 28, count 0 2006.257.21:56:50.48#ibcon#enter sib2, iclass 28, count 0 2006.257.21:56:50.48#ibcon#flushed, iclass 28, count 0 2006.257.21:56:50.48#ibcon#about to write, iclass 28, count 0 2006.257.21:56:50.48#ibcon#wrote, iclass 28, count 0 2006.257.21:56:50.48#ibcon#about to read 3, iclass 28, count 0 2006.257.21:56:50.51#ibcon#read 3, iclass 28, count 0 2006.257.21:56:50.51#ibcon#about to read 4, iclass 28, count 0 2006.257.21:56:50.51#ibcon#read 4, iclass 28, count 0 2006.257.21:56:50.51#ibcon#about to read 5, iclass 28, count 0 2006.257.21:56:50.51#ibcon#read 5, iclass 28, count 0 2006.257.21:56:50.51#ibcon#about to read 6, iclass 28, count 0 2006.257.21:56:50.51#ibcon#read 6, iclass 28, count 0 2006.257.21:56:50.51#ibcon#end of sib2, iclass 28, count 0 2006.257.21:56:50.51#ibcon#*after write, iclass 28, count 0 2006.257.21:56:50.51#ibcon#*before return 0, iclass 28, count 0 2006.257.21:56:50.51#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:50.51#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.21:56:50.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.21:56:50.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.21:56:50.51$vck44/vblo=8,744.99 2006.257.21:56:50.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.21:56:50.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.21:56:50.51#ibcon#ireg 17 cls_cnt 0 2006.257.21:56:50.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:50.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:50.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:50.51#ibcon#enter wrdev, iclass 30, count 0 2006.257.21:56:50.51#ibcon#first serial, iclass 30, count 0 2006.257.21:56:50.51#ibcon#enter sib2, iclass 30, count 0 2006.257.21:56:50.51#ibcon#flushed, iclass 30, count 0 2006.257.21:56:50.51#ibcon#about to write, iclass 30, count 0 2006.257.21:56:50.51#ibcon#wrote, iclass 30, count 0 2006.257.21:56:50.51#ibcon#about to read 3, iclass 30, count 0 2006.257.21:56:50.53#ibcon#read 3, iclass 30, count 0 2006.257.21:56:50.53#ibcon#about to read 4, iclass 30, count 0 2006.257.21:56:50.53#ibcon#read 4, iclass 30, count 0 2006.257.21:56:50.53#ibcon#about to read 5, iclass 30, count 0 2006.257.21:56:50.53#ibcon#read 5, iclass 30, count 0 2006.257.21:56:50.53#ibcon#about to read 6, iclass 30, count 0 2006.257.21:56:50.53#ibcon#read 6, iclass 30, count 0 2006.257.21:56:50.53#ibcon#end of sib2, iclass 30, count 0 2006.257.21:56:50.53#ibcon#*mode == 0, iclass 30, count 0 2006.257.21:56:50.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.21:56:50.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.21:56:50.53#ibcon#*before write, iclass 30, count 0 2006.257.21:56:50.53#ibcon#enter sib2, iclass 30, count 0 2006.257.21:56:50.53#ibcon#flushed, iclass 30, count 0 2006.257.21:56:50.53#ibcon#about to write, iclass 30, count 0 2006.257.21:56:50.53#ibcon#wrote, iclass 30, count 0 2006.257.21:56:50.53#ibcon#about to read 3, iclass 30, count 0 2006.257.21:56:50.57#ibcon#read 3, iclass 30, count 0 2006.257.21:56:50.57#ibcon#about to read 4, iclass 30, count 0 2006.257.21:56:50.57#ibcon#read 4, iclass 30, count 0 2006.257.21:56:50.57#ibcon#about to read 5, iclass 30, count 0 2006.257.21:56:50.57#ibcon#read 5, iclass 30, count 0 2006.257.21:56:50.57#ibcon#about to read 6, iclass 30, count 0 2006.257.21:56:50.57#ibcon#read 6, iclass 30, count 0 2006.257.21:56:50.57#ibcon#end of sib2, iclass 30, count 0 2006.257.21:56:50.57#ibcon#*after write, iclass 30, count 0 2006.257.21:56:50.57#ibcon#*before return 0, iclass 30, count 0 2006.257.21:56:50.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:50.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.21:56:50.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.21:56:50.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.21:56:50.57$vck44/vb=8,4 2006.257.21:56:50.57#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.21:56:50.57#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.21:56:50.57#ibcon#ireg 11 cls_cnt 2 2006.257.21:56:50.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:50.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:50.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:50.63#ibcon#enter wrdev, iclass 32, count 2 2006.257.21:56:50.63#ibcon#first serial, iclass 32, count 2 2006.257.21:56:50.63#ibcon#enter sib2, iclass 32, count 2 2006.257.21:56:50.63#ibcon#flushed, iclass 32, count 2 2006.257.21:56:50.63#ibcon#about to write, iclass 32, count 2 2006.257.21:56:50.63#ibcon#wrote, iclass 32, count 2 2006.257.21:56:50.63#ibcon#about to read 3, iclass 32, count 2 2006.257.21:56:50.65#ibcon#read 3, iclass 32, count 2 2006.257.21:56:50.65#ibcon#about to read 4, iclass 32, count 2 2006.257.21:56:50.65#ibcon#read 4, iclass 32, count 2 2006.257.21:56:50.65#ibcon#about to read 5, iclass 32, count 2 2006.257.21:56:50.65#ibcon#read 5, iclass 32, count 2 2006.257.21:56:50.65#ibcon#about to read 6, iclass 32, count 2 2006.257.21:56:50.65#ibcon#read 6, iclass 32, count 2 2006.257.21:56:50.65#ibcon#end of sib2, iclass 32, count 2 2006.257.21:56:50.65#ibcon#*mode == 0, iclass 32, count 2 2006.257.21:56:50.65#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.21:56:50.65#ibcon#[27=AT08-04\r\n] 2006.257.21:56:50.65#ibcon#*before write, iclass 32, count 2 2006.257.21:56:50.65#ibcon#enter sib2, iclass 32, count 2 2006.257.21:56:50.65#ibcon#flushed, iclass 32, count 2 2006.257.21:56:50.65#ibcon#about to write, iclass 32, count 2 2006.257.21:56:50.65#ibcon#wrote, iclass 32, count 2 2006.257.21:56:50.65#ibcon#about to read 3, iclass 32, count 2 2006.257.21:56:50.68#ibcon#read 3, iclass 32, count 2 2006.257.21:56:50.68#ibcon#about to read 4, iclass 32, count 2 2006.257.21:56:50.68#ibcon#read 4, iclass 32, count 2 2006.257.21:56:50.68#ibcon#about to read 5, iclass 32, count 2 2006.257.21:56:50.68#ibcon#read 5, iclass 32, count 2 2006.257.21:56:50.68#ibcon#about to read 6, iclass 32, count 2 2006.257.21:56:50.68#ibcon#read 6, iclass 32, count 2 2006.257.21:56:50.68#ibcon#end of sib2, iclass 32, count 2 2006.257.21:56:50.68#ibcon#*after write, iclass 32, count 2 2006.257.21:56:50.68#ibcon#*before return 0, iclass 32, count 2 2006.257.21:56:50.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:50.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.21:56:50.68#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.21:56:50.68#ibcon#ireg 7 cls_cnt 0 2006.257.21:56:50.68#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:50.80#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:50.80#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:50.80#ibcon#enter wrdev, iclass 32, count 0 2006.257.21:56:50.80#ibcon#first serial, iclass 32, count 0 2006.257.21:56:50.80#ibcon#enter sib2, iclass 32, count 0 2006.257.21:56:50.80#ibcon#flushed, iclass 32, count 0 2006.257.21:56:50.80#ibcon#about to write, iclass 32, count 0 2006.257.21:56:50.80#ibcon#wrote, iclass 32, count 0 2006.257.21:56:50.80#ibcon#about to read 3, iclass 32, count 0 2006.257.21:56:50.82#ibcon#read 3, iclass 32, count 0 2006.257.21:56:50.82#ibcon#about to read 4, iclass 32, count 0 2006.257.21:56:50.82#ibcon#read 4, iclass 32, count 0 2006.257.21:56:50.82#ibcon#about to read 5, iclass 32, count 0 2006.257.21:56:50.82#ibcon#read 5, iclass 32, count 0 2006.257.21:56:50.82#ibcon#about to read 6, iclass 32, count 0 2006.257.21:56:50.82#ibcon#read 6, iclass 32, count 0 2006.257.21:56:50.82#ibcon#end of sib2, iclass 32, count 0 2006.257.21:56:50.82#ibcon#*mode == 0, iclass 32, count 0 2006.257.21:56:50.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.21:56:50.82#ibcon#[27=USB\r\n] 2006.257.21:56:50.82#ibcon#*before write, iclass 32, count 0 2006.257.21:56:50.82#ibcon#enter sib2, iclass 32, count 0 2006.257.21:56:50.82#ibcon#flushed, iclass 32, count 0 2006.257.21:56:50.82#ibcon#about to write, iclass 32, count 0 2006.257.21:56:50.82#ibcon#wrote, iclass 32, count 0 2006.257.21:56:50.82#ibcon#about to read 3, iclass 32, count 0 2006.257.21:56:50.85#ibcon#read 3, iclass 32, count 0 2006.257.21:56:50.85#ibcon#about to read 4, iclass 32, count 0 2006.257.21:56:50.85#ibcon#read 4, iclass 32, count 0 2006.257.21:56:50.85#ibcon#about to read 5, iclass 32, count 0 2006.257.21:56:50.85#ibcon#read 5, iclass 32, count 0 2006.257.21:56:50.85#ibcon#about to read 6, iclass 32, count 0 2006.257.21:56:50.85#ibcon#read 6, iclass 32, count 0 2006.257.21:56:50.85#ibcon#end of sib2, iclass 32, count 0 2006.257.21:56:50.85#ibcon#*after write, iclass 32, count 0 2006.257.21:56:50.85#ibcon#*before return 0, iclass 32, count 0 2006.257.21:56:50.85#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:50.85#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.21:56:50.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.21:56:50.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.21:56:50.85$vck44/vabw=wide 2006.257.21:56:50.85#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.21:56:50.85#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.21:56:50.85#ibcon#ireg 8 cls_cnt 0 2006.257.21:56:50.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:50.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:50.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:50.85#ibcon#enter wrdev, iclass 34, count 0 2006.257.21:56:50.85#ibcon#first serial, iclass 34, count 0 2006.257.21:56:50.85#ibcon#enter sib2, iclass 34, count 0 2006.257.21:56:50.85#ibcon#flushed, iclass 34, count 0 2006.257.21:56:50.85#ibcon#about to write, iclass 34, count 0 2006.257.21:56:50.85#ibcon#wrote, iclass 34, count 0 2006.257.21:56:50.85#ibcon#about to read 3, iclass 34, count 0 2006.257.21:56:50.87#ibcon#read 3, iclass 34, count 0 2006.257.21:56:50.87#ibcon#about to read 4, iclass 34, count 0 2006.257.21:56:50.87#ibcon#read 4, iclass 34, count 0 2006.257.21:56:50.87#ibcon#about to read 5, iclass 34, count 0 2006.257.21:56:50.87#ibcon#read 5, iclass 34, count 0 2006.257.21:56:50.87#ibcon#about to read 6, iclass 34, count 0 2006.257.21:56:50.87#ibcon#read 6, iclass 34, count 0 2006.257.21:56:50.87#ibcon#end of sib2, iclass 34, count 0 2006.257.21:56:50.87#ibcon#*mode == 0, iclass 34, count 0 2006.257.21:56:50.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.21:56:50.87#ibcon#[25=BW32\r\n] 2006.257.21:56:50.87#ibcon#*before write, iclass 34, count 0 2006.257.21:56:50.87#ibcon#enter sib2, iclass 34, count 0 2006.257.21:56:50.87#ibcon#flushed, iclass 34, count 0 2006.257.21:56:50.87#ibcon#about to write, iclass 34, count 0 2006.257.21:56:50.87#ibcon#wrote, iclass 34, count 0 2006.257.21:56:50.87#ibcon#about to read 3, iclass 34, count 0 2006.257.21:56:50.90#ibcon#read 3, iclass 34, count 0 2006.257.21:56:50.90#ibcon#about to read 4, iclass 34, count 0 2006.257.21:56:50.90#ibcon#read 4, iclass 34, count 0 2006.257.21:56:50.90#ibcon#about to read 5, iclass 34, count 0 2006.257.21:56:50.90#ibcon#read 5, iclass 34, count 0 2006.257.21:56:50.90#ibcon#about to read 6, iclass 34, count 0 2006.257.21:56:50.90#ibcon#read 6, iclass 34, count 0 2006.257.21:56:50.90#ibcon#end of sib2, iclass 34, count 0 2006.257.21:56:50.90#ibcon#*after write, iclass 34, count 0 2006.257.21:56:50.90#ibcon#*before return 0, iclass 34, count 0 2006.257.21:56:50.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:50.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.21:56:50.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.21:56:50.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.21:56:50.90$vck44/vbbw=wide 2006.257.21:56:50.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.21:56:50.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.21:56:50.90#ibcon#ireg 8 cls_cnt 0 2006.257.21:56:50.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:56:50.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:56:50.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:56:50.97#ibcon#enter wrdev, iclass 36, count 0 2006.257.21:56:50.97#ibcon#first serial, iclass 36, count 0 2006.257.21:56:50.97#ibcon#enter sib2, iclass 36, count 0 2006.257.21:56:50.97#ibcon#flushed, iclass 36, count 0 2006.257.21:56:50.97#ibcon#about to write, iclass 36, count 0 2006.257.21:56:50.97#ibcon#wrote, iclass 36, count 0 2006.257.21:56:50.97#ibcon#about to read 3, iclass 36, count 0 2006.257.21:56:50.99#ibcon#read 3, iclass 36, count 0 2006.257.21:56:50.99#ibcon#about to read 4, iclass 36, count 0 2006.257.21:56:50.99#ibcon#read 4, iclass 36, count 0 2006.257.21:56:50.99#ibcon#about to read 5, iclass 36, count 0 2006.257.21:56:50.99#ibcon#read 5, iclass 36, count 0 2006.257.21:56:50.99#ibcon#about to read 6, iclass 36, count 0 2006.257.21:56:50.99#ibcon#read 6, iclass 36, count 0 2006.257.21:56:50.99#ibcon#end of sib2, iclass 36, count 0 2006.257.21:56:50.99#ibcon#*mode == 0, iclass 36, count 0 2006.257.21:56:50.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.21:56:50.99#ibcon#[27=BW32\r\n] 2006.257.21:56:50.99#ibcon#*before write, iclass 36, count 0 2006.257.21:56:50.99#ibcon#enter sib2, iclass 36, count 0 2006.257.21:56:50.99#ibcon#flushed, iclass 36, count 0 2006.257.21:56:50.99#ibcon#about to write, iclass 36, count 0 2006.257.21:56:50.99#ibcon#wrote, iclass 36, count 0 2006.257.21:56:50.99#ibcon#about to read 3, iclass 36, count 0 2006.257.21:56:51.02#ibcon#read 3, iclass 36, count 0 2006.257.21:56:51.02#ibcon#about to read 4, iclass 36, count 0 2006.257.21:56:51.02#ibcon#read 4, iclass 36, count 0 2006.257.21:56:51.02#ibcon#about to read 5, iclass 36, count 0 2006.257.21:56:51.02#ibcon#read 5, iclass 36, count 0 2006.257.21:56:51.02#ibcon#about to read 6, iclass 36, count 0 2006.257.21:56:51.02#ibcon#read 6, iclass 36, count 0 2006.257.21:56:51.02#ibcon#end of sib2, iclass 36, count 0 2006.257.21:56:51.02#ibcon#*after write, iclass 36, count 0 2006.257.21:56:51.02#ibcon#*before return 0, iclass 36, count 0 2006.257.21:56:51.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:56:51.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.21:56:51.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.21:56:51.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.21:56:51.02$setupk4/ifdk4 2006.257.21:56:51.02$ifdk4/lo= 2006.257.21:56:51.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.21:56:51.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.21:56:51.02$ifdk4/patch= 2006.257.21:56:51.02$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.21:56:51.02$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.21:56:51.02$setupk4/!*+20s 2006.257.21:56:55.48#abcon#<5=/14 1.0 2.5 18.45 921015.5\r\n> 2006.257.21:56:55.50#abcon#{5=INTERFACE CLEAR} 2006.257.21:56:55.56#abcon#[5=S1D000X0/0*\r\n] 2006.257.21:57:05.53$setupk4/"tpicd 2006.257.21:57:05.53$setupk4/echo=off 2006.257.21:57:05.53$setupk4/xlog=off 2006.257.21:57:05.53:!2006.257.22:03:55 2006.257.21:57:25.14#trakl#Source acquired 2006.257.21:57:26.14#flagr#flagr/antenna,acquired 2006.257.22:03:55.00:preob 2006.257.22:03:55.14/onsource/TRACKING 2006.257.22:03:55.14:!2006.257.22:04:05 2006.257.22:04:05.00:"tape 2006.257.22:04:05.00:"st=record 2006.257.22:04:05.00:data_valid=on 2006.257.22:04:05.00:midob 2006.257.22:04:05.14/onsource/TRACKING 2006.257.22:04:05.14/wx/18.78,1015.7,91 2006.257.22:04:05.27/cable/+6.4852E-03 2006.257.22:04:06.36/va/01,08,usb,yes,31,33 2006.257.22:04:06.36/va/02,07,usb,yes,34,34 2006.257.22:04:06.36/va/03,08,usb,yes,30,32 2006.257.22:04:06.36/va/04,07,usb,yes,35,36 2006.257.22:04:06.36/va/05,04,usb,yes,31,32 2006.257.22:04:06.36/va/06,04,usb,yes,35,34 2006.257.22:04:06.36/va/07,04,usb,yes,36,36 2006.257.22:04:06.36/va/08,04,usb,yes,30,36 2006.257.22:04:06.59/valo/01,524.99,yes,locked 2006.257.22:04:06.59/valo/02,534.99,yes,locked 2006.257.22:04:06.59/valo/03,564.99,yes,locked 2006.257.22:04:06.59/valo/04,624.99,yes,locked 2006.257.22:04:06.59/valo/05,734.99,yes,locked 2006.257.22:04:06.59/valo/06,814.99,yes,locked 2006.257.22:04:06.59/valo/07,864.99,yes,locked 2006.257.22:04:06.59/valo/08,884.99,yes,locked 2006.257.22:04:07.68/vb/01,04,usb,yes,30,28 2006.257.22:04:07.68/vb/02,05,usb,yes,29,29 2006.257.22:04:07.68/vb/03,04,usb,yes,30,33 2006.257.22:04:07.68/vb/04,05,usb,yes,30,29 2006.257.22:04:07.68/vb/05,04,usb,yes,26,29 2006.257.22:04:07.68/vb/06,04,usb,yes,31,27 2006.257.22:04:07.68/vb/07,04,usb,yes,31,30 2006.257.22:04:07.68/vb/08,04,usb,yes,28,31 2006.257.22:04:07.91/vblo/01,629.99,yes,locked 2006.257.22:04:07.91/vblo/02,634.99,yes,locked 2006.257.22:04:07.91/vblo/03,649.99,yes,locked 2006.257.22:04:07.91/vblo/04,679.99,yes,locked 2006.257.22:04:07.91/vblo/05,709.99,yes,locked 2006.257.22:04:07.91/vblo/06,719.99,yes,locked 2006.257.22:04:07.91/vblo/07,734.99,yes,locked 2006.257.22:04:07.91/vblo/08,744.99,yes,locked 2006.257.22:04:08.06/vabw/8 2006.257.22:04:08.21/vbbw/8 2006.257.22:04:08.30/xfe/off,on,15.2 2006.257.22:04:08.68/ifatt/23,28,28,28 2006.257.22:04:09.07/fmout-gps/S +4.50E-07 2006.257.22:04:09.11:!2006.257.22:09:25 2006.257.22:09:25.00:data_valid=off 2006.257.22:09:25.00:"et 2006.257.22:09:25.00:!+3s 2006.257.22:09:28.02:"tape 2006.257.22:09:28.02:postob 2006.257.22:09:28.13/cable/+6.4847E-03 2006.257.22:09:28.13/wx/18.96,1015.7,89 2006.257.22:09:29.08/fmout-gps/S +4.52E-07 2006.257.22:09:29.08:scan_name=257-2214,jd0609,100 2006.257.22:09:29.08:source=0528+134,053056.42,133155.1,2000.0,cw 2006.257.22:09:30.13#flagr#flagr/antenna,new-source 2006.257.22:09:30.14:checkk5 2006.257.22:09:30.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.22:09:30.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.22:09:31.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.22:09:31.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.22:09:31.85/chk_obsdata//k5ts1/T2572204??a.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.257.22:09:32.18/chk_obsdata//k5ts2/T2572204??b.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.257.22:09:32.51/chk_obsdata//k5ts3/T2572204??c.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.257.22:09:32.84/chk_obsdata//k5ts4/T2572204??d.dat file size is correct (nominal:1280MB, actual:1280MB). 2006.257.22:09:33.49/k5log//k5ts1_log_newline 2006.257.22:09:34.14/k5log//k5ts2_log_newline 2006.257.22:09:34.79/k5log//k5ts3_log_newline 2006.257.22:09:35.45/k5log//k5ts4_log_newline 2006.257.22:09:35.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.22:09:35.47:setupk4=1 2006.257.22:09:35.47$setupk4/echo=on 2006.257.22:09:35.47$setupk4/pcalon 2006.257.22:09:35.47$pcalon/"no phase cal control is implemented here 2006.257.22:09:35.47$setupk4/"tpicd=stop 2006.257.22:09:35.47$setupk4/"rec=synch_on 2006.257.22:09:35.47$setupk4/"rec_mode=128 2006.257.22:09:35.47$setupk4/!* 2006.257.22:09:35.47$setupk4/recpk4 2006.257.22:09:35.47$recpk4/recpatch= 2006.257.22:09:35.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.22:09:35.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.22:09:35.48$setupk4/vck44 2006.257.22:09:35.48$vck44/valo=1,524.99 2006.257.22:09:35.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.22:09:35.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.22:09:35.48#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:35.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:35.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:35.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:35.48#ibcon#enter wrdev, iclass 12, count 0 2006.257.22:09:35.48#ibcon#first serial, iclass 12, count 0 2006.257.22:09:35.48#ibcon#enter sib2, iclass 12, count 0 2006.257.22:09:35.48#ibcon#flushed, iclass 12, count 0 2006.257.22:09:35.48#ibcon#about to write, iclass 12, count 0 2006.257.22:09:35.48#ibcon#wrote, iclass 12, count 0 2006.257.22:09:35.48#ibcon#about to read 3, iclass 12, count 0 2006.257.22:09:35.50#ibcon#read 3, iclass 12, count 0 2006.257.22:09:35.50#ibcon#about to read 4, iclass 12, count 0 2006.257.22:09:35.50#ibcon#read 4, iclass 12, count 0 2006.257.22:09:35.50#ibcon#about to read 5, iclass 12, count 0 2006.257.22:09:35.50#ibcon#read 5, iclass 12, count 0 2006.257.22:09:35.50#ibcon#about to read 6, iclass 12, count 0 2006.257.22:09:35.50#ibcon#read 6, iclass 12, count 0 2006.257.22:09:35.50#ibcon#end of sib2, iclass 12, count 0 2006.257.22:09:35.50#ibcon#*mode == 0, iclass 12, count 0 2006.257.22:09:35.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.22:09:35.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.22:09:35.50#ibcon#*before write, iclass 12, count 0 2006.257.22:09:35.50#ibcon#enter sib2, iclass 12, count 0 2006.257.22:09:35.50#ibcon#flushed, iclass 12, count 0 2006.257.22:09:35.50#ibcon#about to write, iclass 12, count 0 2006.257.22:09:35.50#ibcon#wrote, iclass 12, count 0 2006.257.22:09:35.50#ibcon#about to read 3, iclass 12, count 0 2006.257.22:09:35.55#ibcon#read 3, iclass 12, count 0 2006.257.22:09:35.55#ibcon#about to read 4, iclass 12, count 0 2006.257.22:09:35.55#ibcon#read 4, iclass 12, count 0 2006.257.22:09:35.55#ibcon#about to read 5, iclass 12, count 0 2006.257.22:09:35.55#ibcon#read 5, iclass 12, count 0 2006.257.22:09:35.55#ibcon#about to read 6, iclass 12, count 0 2006.257.22:09:35.55#ibcon#read 6, iclass 12, count 0 2006.257.22:09:35.55#ibcon#end of sib2, iclass 12, count 0 2006.257.22:09:35.55#ibcon#*after write, iclass 12, count 0 2006.257.22:09:35.55#ibcon#*before return 0, iclass 12, count 0 2006.257.22:09:35.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:35.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:35.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.22:09:35.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.22:09:35.55$vck44/va=1,8 2006.257.22:09:35.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.22:09:35.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.22:09:35.55#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:35.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:35.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:35.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:35.55#ibcon#enter wrdev, iclass 14, count 2 2006.257.22:09:35.55#ibcon#first serial, iclass 14, count 2 2006.257.22:09:35.55#ibcon#enter sib2, iclass 14, count 2 2006.257.22:09:35.55#ibcon#flushed, iclass 14, count 2 2006.257.22:09:35.55#ibcon#about to write, iclass 14, count 2 2006.257.22:09:35.55#ibcon#wrote, iclass 14, count 2 2006.257.22:09:35.55#ibcon#about to read 3, iclass 14, count 2 2006.257.22:09:35.57#ibcon#read 3, iclass 14, count 2 2006.257.22:09:35.57#ibcon#about to read 4, iclass 14, count 2 2006.257.22:09:35.57#ibcon#read 4, iclass 14, count 2 2006.257.22:09:35.57#ibcon#about to read 5, iclass 14, count 2 2006.257.22:09:35.57#ibcon#read 5, iclass 14, count 2 2006.257.22:09:35.57#ibcon#about to read 6, iclass 14, count 2 2006.257.22:09:35.57#ibcon#read 6, iclass 14, count 2 2006.257.22:09:35.57#ibcon#end of sib2, iclass 14, count 2 2006.257.22:09:35.57#ibcon#*mode == 0, iclass 14, count 2 2006.257.22:09:35.57#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.22:09:35.57#ibcon#[25=AT01-08\r\n] 2006.257.22:09:35.57#ibcon#*before write, iclass 14, count 2 2006.257.22:09:35.57#ibcon#enter sib2, iclass 14, count 2 2006.257.22:09:35.57#ibcon#flushed, iclass 14, count 2 2006.257.22:09:35.57#ibcon#about to write, iclass 14, count 2 2006.257.22:09:35.57#ibcon#wrote, iclass 14, count 2 2006.257.22:09:35.57#ibcon#about to read 3, iclass 14, count 2 2006.257.22:09:35.60#ibcon#read 3, iclass 14, count 2 2006.257.22:09:35.60#ibcon#about to read 4, iclass 14, count 2 2006.257.22:09:35.60#ibcon#read 4, iclass 14, count 2 2006.257.22:09:35.60#ibcon#about to read 5, iclass 14, count 2 2006.257.22:09:35.60#ibcon#read 5, iclass 14, count 2 2006.257.22:09:35.60#ibcon#about to read 6, iclass 14, count 2 2006.257.22:09:35.60#ibcon#read 6, iclass 14, count 2 2006.257.22:09:35.60#ibcon#end of sib2, iclass 14, count 2 2006.257.22:09:35.60#ibcon#*after write, iclass 14, count 2 2006.257.22:09:35.60#ibcon#*before return 0, iclass 14, count 2 2006.257.22:09:35.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:35.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:35.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.22:09:35.60#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:35.60#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:35.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:35.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:35.72#ibcon#enter wrdev, iclass 14, count 0 2006.257.22:09:35.72#ibcon#first serial, iclass 14, count 0 2006.257.22:09:35.72#ibcon#enter sib2, iclass 14, count 0 2006.257.22:09:35.72#ibcon#flushed, iclass 14, count 0 2006.257.22:09:35.72#ibcon#about to write, iclass 14, count 0 2006.257.22:09:35.72#ibcon#wrote, iclass 14, count 0 2006.257.22:09:35.72#ibcon#about to read 3, iclass 14, count 0 2006.257.22:09:35.74#ibcon#read 3, iclass 14, count 0 2006.257.22:09:35.74#ibcon#about to read 4, iclass 14, count 0 2006.257.22:09:35.74#ibcon#read 4, iclass 14, count 0 2006.257.22:09:35.74#ibcon#about to read 5, iclass 14, count 0 2006.257.22:09:35.74#ibcon#read 5, iclass 14, count 0 2006.257.22:09:35.74#ibcon#about to read 6, iclass 14, count 0 2006.257.22:09:35.74#ibcon#read 6, iclass 14, count 0 2006.257.22:09:35.74#ibcon#end of sib2, iclass 14, count 0 2006.257.22:09:35.74#ibcon#*mode == 0, iclass 14, count 0 2006.257.22:09:35.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.22:09:35.74#ibcon#[25=USB\r\n] 2006.257.22:09:35.74#ibcon#*before write, iclass 14, count 0 2006.257.22:09:35.74#ibcon#enter sib2, iclass 14, count 0 2006.257.22:09:35.74#ibcon#flushed, iclass 14, count 0 2006.257.22:09:35.74#ibcon#about to write, iclass 14, count 0 2006.257.22:09:35.74#ibcon#wrote, iclass 14, count 0 2006.257.22:09:35.74#ibcon#about to read 3, iclass 14, count 0 2006.257.22:09:35.77#ibcon#read 3, iclass 14, count 0 2006.257.22:09:35.77#ibcon#about to read 4, iclass 14, count 0 2006.257.22:09:35.77#ibcon#read 4, iclass 14, count 0 2006.257.22:09:35.77#ibcon#about to read 5, iclass 14, count 0 2006.257.22:09:35.77#ibcon#read 5, iclass 14, count 0 2006.257.22:09:35.77#ibcon#about to read 6, iclass 14, count 0 2006.257.22:09:35.77#ibcon#read 6, iclass 14, count 0 2006.257.22:09:35.77#ibcon#end of sib2, iclass 14, count 0 2006.257.22:09:35.77#ibcon#*after write, iclass 14, count 0 2006.257.22:09:35.77#ibcon#*before return 0, iclass 14, count 0 2006.257.22:09:35.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:35.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:35.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.22:09:35.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.22:09:35.77$vck44/valo=2,534.99 2006.257.22:09:35.77#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.22:09:35.77#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.22:09:35.77#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:35.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:35.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:35.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:35.77#ibcon#enter wrdev, iclass 16, count 0 2006.257.22:09:35.77#ibcon#first serial, iclass 16, count 0 2006.257.22:09:35.77#ibcon#enter sib2, iclass 16, count 0 2006.257.22:09:35.77#ibcon#flushed, iclass 16, count 0 2006.257.22:09:35.77#ibcon#about to write, iclass 16, count 0 2006.257.22:09:35.77#ibcon#wrote, iclass 16, count 0 2006.257.22:09:35.77#ibcon#about to read 3, iclass 16, count 0 2006.257.22:09:35.79#ibcon#read 3, iclass 16, count 0 2006.257.22:09:35.79#ibcon#about to read 4, iclass 16, count 0 2006.257.22:09:35.79#ibcon#read 4, iclass 16, count 0 2006.257.22:09:35.79#ibcon#about to read 5, iclass 16, count 0 2006.257.22:09:35.79#ibcon#read 5, iclass 16, count 0 2006.257.22:09:35.79#ibcon#about to read 6, iclass 16, count 0 2006.257.22:09:35.79#ibcon#read 6, iclass 16, count 0 2006.257.22:09:35.79#ibcon#end of sib2, iclass 16, count 0 2006.257.22:09:35.79#ibcon#*mode == 0, iclass 16, count 0 2006.257.22:09:35.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.22:09:35.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.22:09:35.79#ibcon#*before write, iclass 16, count 0 2006.257.22:09:35.79#ibcon#enter sib2, iclass 16, count 0 2006.257.22:09:35.79#ibcon#flushed, iclass 16, count 0 2006.257.22:09:35.79#ibcon#about to write, iclass 16, count 0 2006.257.22:09:35.79#ibcon#wrote, iclass 16, count 0 2006.257.22:09:35.79#ibcon#about to read 3, iclass 16, count 0 2006.257.22:09:35.83#ibcon#read 3, iclass 16, count 0 2006.257.22:09:35.83#ibcon#about to read 4, iclass 16, count 0 2006.257.22:09:35.83#ibcon#read 4, iclass 16, count 0 2006.257.22:09:35.83#ibcon#about to read 5, iclass 16, count 0 2006.257.22:09:35.83#ibcon#read 5, iclass 16, count 0 2006.257.22:09:35.83#ibcon#about to read 6, iclass 16, count 0 2006.257.22:09:35.83#ibcon#read 6, iclass 16, count 0 2006.257.22:09:35.83#ibcon#end of sib2, iclass 16, count 0 2006.257.22:09:35.83#ibcon#*after write, iclass 16, count 0 2006.257.22:09:35.83#ibcon#*before return 0, iclass 16, count 0 2006.257.22:09:35.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:35.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:35.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.22:09:35.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.22:09:35.83$vck44/va=2,7 2006.257.22:09:35.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.22:09:35.83#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.22:09:35.83#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:35.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:35.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:35.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:35.89#ibcon#enter wrdev, iclass 18, count 2 2006.257.22:09:35.89#ibcon#first serial, iclass 18, count 2 2006.257.22:09:35.89#ibcon#enter sib2, iclass 18, count 2 2006.257.22:09:35.89#ibcon#flushed, iclass 18, count 2 2006.257.22:09:35.89#ibcon#about to write, iclass 18, count 2 2006.257.22:09:35.89#ibcon#wrote, iclass 18, count 2 2006.257.22:09:35.89#ibcon#about to read 3, iclass 18, count 2 2006.257.22:09:35.91#ibcon#read 3, iclass 18, count 2 2006.257.22:09:35.91#ibcon#about to read 4, iclass 18, count 2 2006.257.22:09:35.91#ibcon#read 4, iclass 18, count 2 2006.257.22:09:35.91#ibcon#about to read 5, iclass 18, count 2 2006.257.22:09:35.91#ibcon#read 5, iclass 18, count 2 2006.257.22:09:35.91#ibcon#about to read 6, iclass 18, count 2 2006.257.22:09:35.91#ibcon#read 6, iclass 18, count 2 2006.257.22:09:35.91#ibcon#end of sib2, iclass 18, count 2 2006.257.22:09:35.91#ibcon#*mode == 0, iclass 18, count 2 2006.257.22:09:35.91#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.22:09:35.91#ibcon#[25=AT02-07\r\n] 2006.257.22:09:35.91#ibcon#*before write, iclass 18, count 2 2006.257.22:09:35.91#ibcon#enter sib2, iclass 18, count 2 2006.257.22:09:35.91#ibcon#flushed, iclass 18, count 2 2006.257.22:09:35.91#ibcon#about to write, iclass 18, count 2 2006.257.22:09:35.91#ibcon#wrote, iclass 18, count 2 2006.257.22:09:35.91#ibcon#about to read 3, iclass 18, count 2 2006.257.22:09:35.94#ibcon#read 3, iclass 18, count 2 2006.257.22:09:35.94#ibcon#about to read 4, iclass 18, count 2 2006.257.22:09:35.94#ibcon#read 4, iclass 18, count 2 2006.257.22:09:35.94#ibcon#about to read 5, iclass 18, count 2 2006.257.22:09:35.94#ibcon#read 5, iclass 18, count 2 2006.257.22:09:35.94#ibcon#about to read 6, iclass 18, count 2 2006.257.22:09:35.94#ibcon#read 6, iclass 18, count 2 2006.257.22:09:35.94#ibcon#end of sib2, iclass 18, count 2 2006.257.22:09:35.94#ibcon#*after write, iclass 18, count 2 2006.257.22:09:35.94#ibcon#*before return 0, iclass 18, count 2 2006.257.22:09:35.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:35.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:35.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.22:09:35.94#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:35.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:36.06#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:36.06#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:36.06#ibcon#enter wrdev, iclass 18, count 0 2006.257.22:09:36.06#ibcon#first serial, iclass 18, count 0 2006.257.22:09:36.06#ibcon#enter sib2, iclass 18, count 0 2006.257.22:09:36.06#ibcon#flushed, iclass 18, count 0 2006.257.22:09:36.06#ibcon#about to write, iclass 18, count 0 2006.257.22:09:36.06#ibcon#wrote, iclass 18, count 0 2006.257.22:09:36.06#ibcon#about to read 3, iclass 18, count 0 2006.257.22:09:36.08#ibcon#read 3, iclass 18, count 0 2006.257.22:09:36.08#ibcon#about to read 4, iclass 18, count 0 2006.257.22:09:36.08#ibcon#read 4, iclass 18, count 0 2006.257.22:09:36.08#ibcon#about to read 5, iclass 18, count 0 2006.257.22:09:36.08#ibcon#read 5, iclass 18, count 0 2006.257.22:09:36.08#ibcon#about to read 6, iclass 18, count 0 2006.257.22:09:36.08#ibcon#read 6, iclass 18, count 0 2006.257.22:09:36.08#ibcon#end of sib2, iclass 18, count 0 2006.257.22:09:36.08#ibcon#*mode == 0, iclass 18, count 0 2006.257.22:09:36.08#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.22:09:36.08#ibcon#[25=USB\r\n] 2006.257.22:09:36.08#ibcon#*before write, iclass 18, count 0 2006.257.22:09:36.08#ibcon#enter sib2, iclass 18, count 0 2006.257.22:09:36.08#ibcon#flushed, iclass 18, count 0 2006.257.22:09:36.08#ibcon#about to write, iclass 18, count 0 2006.257.22:09:36.08#ibcon#wrote, iclass 18, count 0 2006.257.22:09:36.08#ibcon#about to read 3, iclass 18, count 0 2006.257.22:09:36.11#ibcon#read 3, iclass 18, count 0 2006.257.22:09:36.11#ibcon#about to read 4, iclass 18, count 0 2006.257.22:09:36.11#ibcon#read 4, iclass 18, count 0 2006.257.22:09:36.11#ibcon#about to read 5, iclass 18, count 0 2006.257.22:09:36.11#ibcon#read 5, iclass 18, count 0 2006.257.22:09:36.11#ibcon#about to read 6, iclass 18, count 0 2006.257.22:09:36.11#ibcon#read 6, iclass 18, count 0 2006.257.22:09:36.11#ibcon#end of sib2, iclass 18, count 0 2006.257.22:09:36.11#ibcon#*after write, iclass 18, count 0 2006.257.22:09:36.11#ibcon#*before return 0, iclass 18, count 0 2006.257.22:09:36.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:36.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:36.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.22:09:36.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.22:09:36.11$vck44/valo=3,564.99 2006.257.22:09:36.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.22:09:36.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.22:09:36.11#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:36.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:36.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:36.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:36.11#ibcon#enter wrdev, iclass 20, count 0 2006.257.22:09:36.11#ibcon#first serial, iclass 20, count 0 2006.257.22:09:36.11#ibcon#enter sib2, iclass 20, count 0 2006.257.22:09:36.11#ibcon#flushed, iclass 20, count 0 2006.257.22:09:36.11#ibcon#about to write, iclass 20, count 0 2006.257.22:09:36.11#ibcon#wrote, iclass 20, count 0 2006.257.22:09:36.11#ibcon#about to read 3, iclass 20, count 0 2006.257.22:09:36.13#ibcon#read 3, iclass 20, count 0 2006.257.22:09:36.13#ibcon#about to read 4, iclass 20, count 0 2006.257.22:09:36.13#ibcon#read 4, iclass 20, count 0 2006.257.22:09:36.13#ibcon#about to read 5, iclass 20, count 0 2006.257.22:09:36.13#ibcon#read 5, iclass 20, count 0 2006.257.22:09:36.13#ibcon#about to read 6, iclass 20, count 0 2006.257.22:09:36.13#ibcon#read 6, iclass 20, count 0 2006.257.22:09:36.13#ibcon#end of sib2, iclass 20, count 0 2006.257.22:09:36.13#ibcon#*mode == 0, iclass 20, count 0 2006.257.22:09:36.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.22:09:36.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.22:09:36.13#ibcon#*before write, iclass 20, count 0 2006.257.22:09:36.13#ibcon#enter sib2, iclass 20, count 0 2006.257.22:09:36.13#ibcon#flushed, iclass 20, count 0 2006.257.22:09:36.13#ibcon#about to write, iclass 20, count 0 2006.257.22:09:36.13#ibcon#wrote, iclass 20, count 0 2006.257.22:09:36.13#ibcon#about to read 3, iclass 20, count 0 2006.257.22:09:36.17#ibcon#read 3, iclass 20, count 0 2006.257.22:09:36.17#ibcon#about to read 4, iclass 20, count 0 2006.257.22:09:36.17#ibcon#read 4, iclass 20, count 0 2006.257.22:09:36.17#ibcon#about to read 5, iclass 20, count 0 2006.257.22:09:36.17#ibcon#read 5, iclass 20, count 0 2006.257.22:09:36.17#ibcon#about to read 6, iclass 20, count 0 2006.257.22:09:36.17#ibcon#read 6, iclass 20, count 0 2006.257.22:09:36.17#ibcon#end of sib2, iclass 20, count 0 2006.257.22:09:36.17#ibcon#*after write, iclass 20, count 0 2006.257.22:09:36.17#ibcon#*before return 0, iclass 20, count 0 2006.257.22:09:36.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:36.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:36.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.22:09:36.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.22:09:36.17$vck44/va=3,8 2006.257.22:09:36.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.22:09:36.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.22:09:36.17#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:36.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:36.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:36.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:36.23#ibcon#enter wrdev, iclass 22, count 2 2006.257.22:09:36.23#ibcon#first serial, iclass 22, count 2 2006.257.22:09:36.23#ibcon#enter sib2, iclass 22, count 2 2006.257.22:09:36.23#ibcon#flushed, iclass 22, count 2 2006.257.22:09:36.23#ibcon#about to write, iclass 22, count 2 2006.257.22:09:36.23#ibcon#wrote, iclass 22, count 2 2006.257.22:09:36.23#ibcon#about to read 3, iclass 22, count 2 2006.257.22:09:36.25#ibcon#read 3, iclass 22, count 2 2006.257.22:09:36.25#ibcon#about to read 4, iclass 22, count 2 2006.257.22:09:36.25#ibcon#read 4, iclass 22, count 2 2006.257.22:09:36.25#ibcon#about to read 5, iclass 22, count 2 2006.257.22:09:36.25#ibcon#read 5, iclass 22, count 2 2006.257.22:09:36.25#ibcon#about to read 6, iclass 22, count 2 2006.257.22:09:36.25#ibcon#read 6, iclass 22, count 2 2006.257.22:09:36.25#ibcon#end of sib2, iclass 22, count 2 2006.257.22:09:36.25#ibcon#*mode == 0, iclass 22, count 2 2006.257.22:09:36.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.22:09:36.25#ibcon#[25=AT03-08\r\n] 2006.257.22:09:36.25#ibcon#*before write, iclass 22, count 2 2006.257.22:09:36.25#ibcon#enter sib2, iclass 22, count 2 2006.257.22:09:36.25#ibcon#flushed, iclass 22, count 2 2006.257.22:09:36.25#ibcon#about to write, iclass 22, count 2 2006.257.22:09:36.25#ibcon#wrote, iclass 22, count 2 2006.257.22:09:36.25#ibcon#about to read 3, iclass 22, count 2 2006.257.22:09:36.28#ibcon#read 3, iclass 22, count 2 2006.257.22:09:36.28#ibcon#about to read 4, iclass 22, count 2 2006.257.22:09:36.28#ibcon#read 4, iclass 22, count 2 2006.257.22:09:36.28#ibcon#about to read 5, iclass 22, count 2 2006.257.22:09:36.28#ibcon#read 5, iclass 22, count 2 2006.257.22:09:36.28#ibcon#about to read 6, iclass 22, count 2 2006.257.22:09:36.28#ibcon#read 6, iclass 22, count 2 2006.257.22:09:36.28#ibcon#end of sib2, iclass 22, count 2 2006.257.22:09:36.28#ibcon#*after write, iclass 22, count 2 2006.257.22:09:36.28#ibcon#*before return 0, iclass 22, count 2 2006.257.22:09:36.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:36.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:36.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.22:09:36.28#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:36.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:36.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:36.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:36.40#ibcon#enter wrdev, iclass 22, count 0 2006.257.22:09:36.40#ibcon#first serial, iclass 22, count 0 2006.257.22:09:36.40#ibcon#enter sib2, iclass 22, count 0 2006.257.22:09:36.40#ibcon#flushed, iclass 22, count 0 2006.257.22:09:36.40#ibcon#about to write, iclass 22, count 0 2006.257.22:09:36.40#ibcon#wrote, iclass 22, count 0 2006.257.22:09:36.40#ibcon#about to read 3, iclass 22, count 0 2006.257.22:09:36.42#ibcon#read 3, iclass 22, count 0 2006.257.22:09:36.42#ibcon#about to read 4, iclass 22, count 0 2006.257.22:09:36.42#ibcon#read 4, iclass 22, count 0 2006.257.22:09:36.42#ibcon#about to read 5, iclass 22, count 0 2006.257.22:09:36.42#ibcon#read 5, iclass 22, count 0 2006.257.22:09:36.42#ibcon#about to read 6, iclass 22, count 0 2006.257.22:09:36.42#ibcon#read 6, iclass 22, count 0 2006.257.22:09:36.42#ibcon#end of sib2, iclass 22, count 0 2006.257.22:09:36.42#ibcon#*mode == 0, iclass 22, count 0 2006.257.22:09:36.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.22:09:36.42#ibcon#[25=USB\r\n] 2006.257.22:09:36.42#ibcon#*before write, iclass 22, count 0 2006.257.22:09:36.42#ibcon#enter sib2, iclass 22, count 0 2006.257.22:09:36.42#ibcon#flushed, iclass 22, count 0 2006.257.22:09:36.42#ibcon#about to write, iclass 22, count 0 2006.257.22:09:36.42#ibcon#wrote, iclass 22, count 0 2006.257.22:09:36.42#ibcon#about to read 3, iclass 22, count 0 2006.257.22:09:36.45#ibcon#read 3, iclass 22, count 0 2006.257.22:09:36.45#ibcon#about to read 4, iclass 22, count 0 2006.257.22:09:36.45#ibcon#read 4, iclass 22, count 0 2006.257.22:09:36.45#ibcon#about to read 5, iclass 22, count 0 2006.257.22:09:36.45#ibcon#read 5, iclass 22, count 0 2006.257.22:09:36.45#ibcon#about to read 6, iclass 22, count 0 2006.257.22:09:36.45#ibcon#read 6, iclass 22, count 0 2006.257.22:09:36.45#ibcon#end of sib2, iclass 22, count 0 2006.257.22:09:36.45#ibcon#*after write, iclass 22, count 0 2006.257.22:09:36.45#ibcon#*before return 0, iclass 22, count 0 2006.257.22:09:36.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:36.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:36.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.22:09:36.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.22:09:36.45$vck44/valo=4,624.99 2006.257.22:09:36.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.22:09:36.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.22:09:36.45#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:36.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:36.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:36.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:36.45#ibcon#enter wrdev, iclass 24, count 0 2006.257.22:09:36.45#ibcon#first serial, iclass 24, count 0 2006.257.22:09:36.45#ibcon#enter sib2, iclass 24, count 0 2006.257.22:09:36.45#ibcon#flushed, iclass 24, count 0 2006.257.22:09:36.45#ibcon#about to write, iclass 24, count 0 2006.257.22:09:36.45#ibcon#wrote, iclass 24, count 0 2006.257.22:09:36.45#ibcon#about to read 3, iclass 24, count 0 2006.257.22:09:36.47#ibcon#read 3, iclass 24, count 0 2006.257.22:09:36.47#ibcon#about to read 4, iclass 24, count 0 2006.257.22:09:36.47#ibcon#read 4, iclass 24, count 0 2006.257.22:09:36.47#ibcon#about to read 5, iclass 24, count 0 2006.257.22:09:36.47#ibcon#read 5, iclass 24, count 0 2006.257.22:09:36.47#ibcon#about to read 6, iclass 24, count 0 2006.257.22:09:36.47#ibcon#read 6, iclass 24, count 0 2006.257.22:09:36.47#ibcon#end of sib2, iclass 24, count 0 2006.257.22:09:36.47#ibcon#*mode == 0, iclass 24, count 0 2006.257.22:09:36.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.22:09:36.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.22:09:36.47#ibcon#*before write, iclass 24, count 0 2006.257.22:09:36.47#ibcon#enter sib2, iclass 24, count 0 2006.257.22:09:36.47#ibcon#flushed, iclass 24, count 0 2006.257.22:09:36.47#ibcon#about to write, iclass 24, count 0 2006.257.22:09:36.47#ibcon#wrote, iclass 24, count 0 2006.257.22:09:36.47#ibcon#about to read 3, iclass 24, count 0 2006.257.22:09:36.51#ibcon#read 3, iclass 24, count 0 2006.257.22:09:36.51#ibcon#about to read 4, iclass 24, count 0 2006.257.22:09:36.51#ibcon#read 4, iclass 24, count 0 2006.257.22:09:36.51#ibcon#about to read 5, iclass 24, count 0 2006.257.22:09:36.51#ibcon#read 5, iclass 24, count 0 2006.257.22:09:36.51#ibcon#about to read 6, iclass 24, count 0 2006.257.22:09:36.51#ibcon#read 6, iclass 24, count 0 2006.257.22:09:36.51#ibcon#end of sib2, iclass 24, count 0 2006.257.22:09:36.51#ibcon#*after write, iclass 24, count 0 2006.257.22:09:36.51#ibcon#*before return 0, iclass 24, count 0 2006.257.22:09:36.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:36.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:36.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.22:09:36.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.22:09:36.51$vck44/va=4,7 2006.257.22:09:36.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.22:09:36.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.22:09:36.51#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:36.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:36.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:36.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:36.57#ibcon#enter wrdev, iclass 26, count 2 2006.257.22:09:36.57#ibcon#first serial, iclass 26, count 2 2006.257.22:09:36.57#ibcon#enter sib2, iclass 26, count 2 2006.257.22:09:36.57#ibcon#flushed, iclass 26, count 2 2006.257.22:09:36.57#ibcon#about to write, iclass 26, count 2 2006.257.22:09:36.57#ibcon#wrote, iclass 26, count 2 2006.257.22:09:36.57#ibcon#about to read 3, iclass 26, count 2 2006.257.22:09:36.59#ibcon#read 3, iclass 26, count 2 2006.257.22:09:36.59#ibcon#about to read 4, iclass 26, count 2 2006.257.22:09:36.59#ibcon#read 4, iclass 26, count 2 2006.257.22:09:36.59#ibcon#about to read 5, iclass 26, count 2 2006.257.22:09:36.59#ibcon#read 5, iclass 26, count 2 2006.257.22:09:36.59#ibcon#about to read 6, iclass 26, count 2 2006.257.22:09:36.59#ibcon#read 6, iclass 26, count 2 2006.257.22:09:36.59#ibcon#end of sib2, iclass 26, count 2 2006.257.22:09:36.59#ibcon#*mode == 0, iclass 26, count 2 2006.257.22:09:36.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.22:09:36.59#ibcon#[25=AT04-07\r\n] 2006.257.22:09:36.59#ibcon#*before write, iclass 26, count 2 2006.257.22:09:36.59#ibcon#enter sib2, iclass 26, count 2 2006.257.22:09:36.59#ibcon#flushed, iclass 26, count 2 2006.257.22:09:36.59#ibcon#about to write, iclass 26, count 2 2006.257.22:09:36.59#ibcon#wrote, iclass 26, count 2 2006.257.22:09:36.59#ibcon#about to read 3, iclass 26, count 2 2006.257.22:09:36.62#ibcon#read 3, iclass 26, count 2 2006.257.22:09:36.62#ibcon#about to read 4, iclass 26, count 2 2006.257.22:09:36.62#ibcon#read 4, iclass 26, count 2 2006.257.22:09:36.62#ibcon#about to read 5, iclass 26, count 2 2006.257.22:09:36.62#ibcon#read 5, iclass 26, count 2 2006.257.22:09:36.62#ibcon#about to read 6, iclass 26, count 2 2006.257.22:09:36.62#ibcon#read 6, iclass 26, count 2 2006.257.22:09:36.62#ibcon#end of sib2, iclass 26, count 2 2006.257.22:09:36.62#ibcon#*after write, iclass 26, count 2 2006.257.22:09:36.62#ibcon#*before return 0, iclass 26, count 2 2006.257.22:09:36.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:36.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:36.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.22:09:36.62#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:36.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:36.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:36.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:36.74#ibcon#enter wrdev, iclass 26, count 0 2006.257.22:09:36.74#ibcon#first serial, iclass 26, count 0 2006.257.22:09:36.74#ibcon#enter sib2, iclass 26, count 0 2006.257.22:09:36.74#ibcon#flushed, iclass 26, count 0 2006.257.22:09:36.74#ibcon#about to write, iclass 26, count 0 2006.257.22:09:36.74#ibcon#wrote, iclass 26, count 0 2006.257.22:09:36.74#ibcon#about to read 3, iclass 26, count 0 2006.257.22:09:36.76#ibcon#read 3, iclass 26, count 0 2006.257.22:09:36.76#ibcon#about to read 4, iclass 26, count 0 2006.257.22:09:36.76#ibcon#read 4, iclass 26, count 0 2006.257.22:09:36.76#ibcon#about to read 5, iclass 26, count 0 2006.257.22:09:36.76#ibcon#read 5, iclass 26, count 0 2006.257.22:09:36.76#ibcon#about to read 6, iclass 26, count 0 2006.257.22:09:36.76#ibcon#read 6, iclass 26, count 0 2006.257.22:09:36.76#ibcon#end of sib2, iclass 26, count 0 2006.257.22:09:36.76#ibcon#*mode == 0, iclass 26, count 0 2006.257.22:09:36.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.22:09:36.76#ibcon#[25=USB\r\n] 2006.257.22:09:36.76#ibcon#*before write, iclass 26, count 0 2006.257.22:09:36.76#ibcon#enter sib2, iclass 26, count 0 2006.257.22:09:36.76#ibcon#flushed, iclass 26, count 0 2006.257.22:09:36.76#ibcon#about to write, iclass 26, count 0 2006.257.22:09:36.76#ibcon#wrote, iclass 26, count 0 2006.257.22:09:36.76#ibcon#about to read 3, iclass 26, count 0 2006.257.22:09:36.79#ibcon#read 3, iclass 26, count 0 2006.257.22:09:36.79#ibcon#about to read 4, iclass 26, count 0 2006.257.22:09:36.79#ibcon#read 4, iclass 26, count 0 2006.257.22:09:36.79#ibcon#about to read 5, iclass 26, count 0 2006.257.22:09:36.79#ibcon#read 5, iclass 26, count 0 2006.257.22:09:36.79#ibcon#about to read 6, iclass 26, count 0 2006.257.22:09:36.79#ibcon#read 6, iclass 26, count 0 2006.257.22:09:36.79#ibcon#end of sib2, iclass 26, count 0 2006.257.22:09:36.79#ibcon#*after write, iclass 26, count 0 2006.257.22:09:36.79#ibcon#*before return 0, iclass 26, count 0 2006.257.22:09:36.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:36.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:36.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.22:09:36.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.22:09:36.79$vck44/valo=5,734.99 2006.257.22:09:36.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.22:09:36.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.22:09:36.79#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:36.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:36.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:36.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:36.79#ibcon#enter wrdev, iclass 28, count 0 2006.257.22:09:36.79#ibcon#first serial, iclass 28, count 0 2006.257.22:09:36.79#ibcon#enter sib2, iclass 28, count 0 2006.257.22:09:36.79#ibcon#flushed, iclass 28, count 0 2006.257.22:09:36.79#ibcon#about to write, iclass 28, count 0 2006.257.22:09:36.79#ibcon#wrote, iclass 28, count 0 2006.257.22:09:36.79#ibcon#about to read 3, iclass 28, count 0 2006.257.22:09:36.81#ibcon#read 3, iclass 28, count 0 2006.257.22:09:36.81#ibcon#about to read 4, iclass 28, count 0 2006.257.22:09:36.81#ibcon#read 4, iclass 28, count 0 2006.257.22:09:36.81#ibcon#about to read 5, iclass 28, count 0 2006.257.22:09:36.81#ibcon#read 5, iclass 28, count 0 2006.257.22:09:36.81#ibcon#about to read 6, iclass 28, count 0 2006.257.22:09:36.81#ibcon#read 6, iclass 28, count 0 2006.257.22:09:36.81#ibcon#end of sib2, iclass 28, count 0 2006.257.22:09:36.81#ibcon#*mode == 0, iclass 28, count 0 2006.257.22:09:36.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.22:09:36.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.22:09:36.81#ibcon#*before write, iclass 28, count 0 2006.257.22:09:36.81#ibcon#enter sib2, iclass 28, count 0 2006.257.22:09:36.81#ibcon#flushed, iclass 28, count 0 2006.257.22:09:36.81#ibcon#about to write, iclass 28, count 0 2006.257.22:09:36.81#ibcon#wrote, iclass 28, count 0 2006.257.22:09:36.81#ibcon#about to read 3, iclass 28, count 0 2006.257.22:09:36.85#ibcon#read 3, iclass 28, count 0 2006.257.22:09:36.85#ibcon#about to read 4, iclass 28, count 0 2006.257.22:09:36.85#ibcon#read 4, iclass 28, count 0 2006.257.22:09:36.85#ibcon#about to read 5, iclass 28, count 0 2006.257.22:09:36.85#ibcon#read 5, iclass 28, count 0 2006.257.22:09:36.85#ibcon#about to read 6, iclass 28, count 0 2006.257.22:09:36.85#ibcon#read 6, iclass 28, count 0 2006.257.22:09:36.85#ibcon#end of sib2, iclass 28, count 0 2006.257.22:09:36.85#ibcon#*after write, iclass 28, count 0 2006.257.22:09:36.85#ibcon#*before return 0, iclass 28, count 0 2006.257.22:09:36.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:36.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:36.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.22:09:36.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.22:09:36.85$vck44/va=5,4 2006.257.22:09:36.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.22:09:36.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.22:09:36.85#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:36.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:36.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:36.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:36.91#ibcon#enter wrdev, iclass 30, count 2 2006.257.22:09:36.91#ibcon#first serial, iclass 30, count 2 2006.257.22:09:36.91#ibcon#enter sib2, iclass 30, count 2 2006.257.22:09:36.91#ibcon#flushed, iclass 30, count 2 2006.257.22:09:36.91#ibcon#about to write, iclass 30, count 2 2006.257.22:09:36.91#ibcon#wrote, iclass 30, count 2 2006.257.22:09:36.91#ibcon#about to read 3, iclass 30, count 2 2006.257.22:09:36.93#ibcon#read 3, iclass 30, count 2 2006.257.22:09:36.93#ibcon#about to read 4, iclass 30, count 2 2006.257.22:09:36.93#ibcon#read 4, iclass 30, count 2 2006.257.22:09:36.93#ibcon#about to read 5, iclass 30, count 2 2006.257.22:09:36.93#ibcon#read 5, iclass 30, count 2 2006.257.22:09:36.93#ibcon#about to read 6, iclass 30, count 2 2006.257.22:09:36.93#ibcon#read 6, iclass 30, count 2 2006.257.22:09:36.93#ibcon#end of sib2, iclass 30, count 2 2006.257.22:09:36.93#ibcon#*mode == 0, iclass 30, count 2 2006.257.22:09:36.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.22:09:36.93#ibcon#[25=AT05-04\r\n] 2006.257.22:09:36.93#ibcon#*before write, iclass 30, count 2 2006.257.22:09:36.93#ibcon#enter sib2, iclass 30, count 2 2006.257.22:09:36.93#ibcon#flushed, iclass 30, count 2 2006.257.22:09:36.93#ibcon#about to write, iclass 30, count 2 2006.257.22:09:36.93#ibcon#wrote, iclass 30, count 2 2006.257.22:09:36.93#ibcon#about to read 3, iclass 30, count 2 2006.257.22:09:36.96#ibcon#read 3, iclass 30, count 2 2006.257.22:09:36.96#ibcon#about to read 4, iclass 30, count 2 2006.257.22:09:36.96#ibcon#read 4, iclass 30, count 2 2006.257.22:09:36.96#ibcon#about to read 5, iclass 30, count 2 2006.257.22:09:36.96#ibcon#read 5, iclass 30, count 2 2006.257.22:09:36.96#ibcon#about to read 6, iclass 30, count 2 2006.257.22:09:36.96#ibcon#read 6, iclass 30, count 2 2006.257.22:09:36.96#ibcon#end of sib2, iclass 30, count 2 2006.257.22:09:36.96#ibcon#*after write, iclass 30, count 2 2006.257.22:09:36.96#ibcon#*before return 0, iclass 30, count 2 2006.257.22:09:36.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:36.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:36.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.22:09:36.96#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:36.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:37.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:37.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:37.08#ibcon#enter wrdev, iclass 30, count 0 2006.257.22:09:37.08#ibcon#first serial, iclass 30, count 0 2006.257.22:09:37.08#ibcon#enter sib2, iclass 30, count 0 2006.257.22:09:37.08#ibcon#flushed, iclass 30, count 0 2006.257.22:09:37.08#ibcon#about to write, iclass 30, count 0 2006.257.22:09:37.08#ibcon#wrote, iclass 30, count 0 2006.257.22:09:37.08#ibcon#about to read 3, iclass 30, count 0 2006.257.22:09:37.10#ibcon#read 3, iclass 30, count 0 2006.257.22:09:37.10#ibcon#about to read 4, iclass 30, count 0 2006.257.22:09:37.10#ibcon#read 4, iclass 30, count 0 2006.257.22:09:37.10#ibcon#about to read 5, iclass 30, count 0 2006.257.22:09:37.10#ibcon#read 5, iclass 30, count 0 2006.257.22:09:37.10#ibcon#about to read 6, iclass 30, count 0 2006.257.22:09:37.10#ibcon#read 6, iclass 30, count 0 2006.257.22:09:37.10#ibcon#end of sib2, iclass 30, count 0 2006.257.22:09:37.10#ibcon#*mode == 0, iclass 30, count 0 2006.257.22:09:37.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.22:09:37.10#ibcon#[25=USB\r\n] 2006.257.22:09:37.10#ibcon#*before write, iclass 30, count 0 2006.257.22:09:37.10#ibcon#enter sib2, iclass 30, count 0 2006.257.22:09:37.10#ibcon#flushed, iclass 30, count 0 2006.257.22:09:37.10#ibcon#about to write, iclass 30, count 0 2006.257.22:09:37.10#ibcon#wrote, iclass 30, count 0 2006.257.22:09:37.10#ibcon#about to read 3, iclass 30, count 0 2006.257.22:09:37.13#ibcon#read 3, iclass 30, count 0 2006.257.22:09:37.13#ibcon#about to read 4, iclass 30, count 0 2006.257.22:09:37.13#ibcon#read 4, iclass 30, count 0 2006.257.22:09:37.13#ibcon#about to read 5, iclass 30, count 0 2006.257.22:09:37.13#ibcon#read 5, iclass 30, count 0 2006.257.22:09:37.13#ibcon#about to read 6, iclass 30, count 0 2006.257.22:09:37.13#ibcon#read 6, iclass 30, count 0 2006.257.22:09:37.13#ibcon#end of sib2, iclass 30, count 0 2006.257.22:09:37.13#ibcon#*after write, iclass 30, count 0 2006.257.22:09:37.13#ibcon#*before return 0, iclass 30, count 0 2006.257.22:09:37.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:37.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:37.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.22:09:37.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.22:09:37.13$vck44/valo=6,814.99 2006.257.22:09:37.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.22:09:37.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.22:09:37.13#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:37.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:37.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:37.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:37.13#ibcon#enter wrdev, iclass 32, count 0 2006.257.22:09:37.13#ibcon#first serial, iclass 32, count 0 2006.257.22:09:37.13#ibcon#enter sib2, iclass 32, count 0 2006.257.22:09:37.13#ibcon#flushed, iclass 32, count 0 2006.257.22:09:37.13#ibcon#about to write, iclass 32, count 0 2006.257.22:09:37.13#ibcon#wrote, iclass 32, count 0 2006.257.22:09:37.13#ibcon#about to read 3, iclass 32, count 0 2006.257.22:09:37.15#ibcon#read 3, iclass 32, count 0 2006.257.22:09:37.15#ibcon#about to read 4, iclass 32, count 0 2006.257.22:09:37.15#ibcon#read 4, iclass 32, count 0 2006.257.22:09:37.15#ibcon#about to read 5, iclass 32, count 0 2006.257.22:09:37.15#ibcon#read 5, iclass 32, count 0 2006.257.22:09:37.15#ibcon#about to read 6, iclass 32, count 0 2006.257.22:09:37.15#ibcon#read 6, iclass 32, count 0 2006.257.22:09:37.15#ibcon#end of sib2, iclass 32, count 0 2006.257.22:09:37.15#ibcon#*mode == 0, iclass 32, count 0 2006.257.22:09:37.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.22:09:37.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.22:09:37.15#ibcon#*before write, iclass 32, count 0 2006.257.22:09:37.15#ibcon#enter sib2, iclass 32, count 0 2006.257.22:09:37.15#ibcon#flushed, iclass 32, count 0 2006.257.22:09:37.15#ibcon#about to write, iclass 32, count 0 2006.257.22:09:37.15#ibcon#wrote, iclass 32, count 0 2006.257.22:09:37.15#ibcon#about to read 3, iclass 32, count 0 2006.257.22:09:37.19#ibcon#read 3, iclass 32, count 0 2006.257.22:09:37.19#ibcon#about to read 4, iclass 32, count 0 2006.257.22:09:37.19#ibcon#read 4, iclass 32, count 0 2006.257.22:09:37.19#ibcon#about to read 5, iclass 32, count 0 2006.257.22:09:37.19#ibcon#read 5, iclass 32, count 0 2006.257.22:09:37.19#ibcon#about to read 6, iclass 32, count 0 2006.257.22:09:37.19#ibcon#read 6, iclass 32, count 0 2006.257.22:09:37.19#ibcon#end of sib2, iclass 32, count 0 2006.257.22:09:37.19#ibcon#*after write, iclass 32, count 0 2006.257.22:09:37.19#ibcon#*before return 0, iclass 32, count 0 2006.257.22:09:37.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:37.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:37.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.22:09:37.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.22:09:37.19$vck44/va=6,4 2006.257.22:09:37.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.22:09:37.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.22:09:37.19#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:37.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:37.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:37.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:37.25#ibcon#enter wrdev, iclass 34, count 2 2006.257.22:09:37.25#ibcon#first serial, iclass 34, count 2 2006.257.22:09:37.25#ibcon#enter sib2, iclass 34, count 2 2006.257.22:09:37.25#ibcon#flushed, iclass 34, count 2 2006.257.22:09:37.25#ibcon#about to write, iclass 34, count 2 2006.257.22:09:37.25#ibcon#wrote, iclass 34, count 2 2006.257.22:09:37.25#ibcon#about to read 3, iclass 34, count 2 2006.257.22:09:37.27#ibcon#read 3, iclass 34, count 2 2006.257.22:09:37.27#ibcon#about to read 4, iclass 34, count 2 2006.257.22:09:37.27#ibcon#read 4, iclass 34, count 2 2006.257.22:09:37.27#ibcon#about to read 5, iclass 34, count 2 2006.257.22:09:37.27#ibcon#read 5, iclass 34, count 2 2006.257.22:09:37.27#ibcon#about to read 6, iclass 34, count 2 2006.257.22:09:37.27#ibcon#read 6, iclass 34, count 2 2006.257.22:09:37.27#ibcon#end of sib2, iclass 34, count 2 2006.257.22:09:37.27#ibcon#*mode == 0, iclass 34, count 2 2006.257.22:09:37.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.22:09:37.27#ibcon#[25=AT06-04\r\n] 2006.257.22:09:37.27#ibcon#*before write, iclass 34, count 2 2006.257.22:09:37.27#ibcon#enter sib2, iclass 34, count 2 2006.257.22:09:37.27#ibcon#flushed, iclass 34, count 2 2006.257.22:09:37.27#ibcon#about to write, iclass 34, count 2 2006.257.22:09:37.27#ibcon#wrote, iclass 34, count 2 2006.257.22:09:37.27#ibcon#about to read 3, iclass 34, count 2 2006.257.22:09:37.30#ibcon#read 3, iclass 34, count 2 2006.257.22:09:37.30#ibcon#about to read 4, iclass 34, count 2 2006.257.22:09:37.30#ibcon#read 4, iclass 34, count 2 2006.257.22:09:37.30#ibcon#about to read 5, iclass 34, count 2 2006.257.22:09:37.30#ibcon#read 5, iclass 34, count 2 2006.257.22:09:37.30#ibcon#about to read 6, iclass 34, count 2 2006.257.22:09:37.30#ibcon#read 6, iclass 34, count 2 2006.257.22:09:37.30#ibcon#end of sib2, iclass 34, count 2 2006.257.22:09:37.30#ibcon#*after write, iclass 34, count 2 2006.257.22:09:37.30#ibcon#*before return 0, iclass 34, count 2 2006.257.22:09:37.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:37.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:37.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.22:09:37.30#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:37.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:37.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:37.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:37.42#ibcon#enter wrdev, iclass 34, count 0 2006.257.22:09:37.42#ibcon#first serial, iclass 34, count 0 2006.257.22:09:37.42#ibcon#enter sib2, iclass 34, count 0 2006.257.22:09:37.42#ibcon#flushed, iclass 34, count 0 2006.257.22:09:37.42#ibcon#about to write, iclass 34, count 0 2006.257.22:09:37.42#ibcon#wrote, iclass 34, count 0 2006.257.22:09:37.42#ibcon#about to read 3, iclass 34, count 0 2006.257.22:09:37.44#ibcon#read 3, iclass 34, count 0 2006.257.22:09:37.44#ibcon#about to read 4, iclass 34, count 0 2006.257.22:09:37.44#ibcon#read 4, iclass 34, count 0 2006.257.22:09:37.44#ibcon#about to read 5, iclass 34, count 0 2006.257.22:09:37.44#ibcon#read 5, iclass 34, count 0 2006.257.22:09:37.44#ibcon#about to read 6, iclass 34, count 0 2006.257.22:09:37.44#ibcon#read 6, iclass 34, count 0 2006.257.22:09:37.44#ibcon#end of sib2, iclass 34, count 0 2006.257.22:09:37.44#ibcon#*mode == 0, iclass 34, count 0 2006.257.22:09:37.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.22:09:37.44#ibcon#[25=USB\r\n] 2006.257.22:09:37.44#ibcon#*before write, iclass 34, count 0 2006.257.22:09:37.44#ibcon#enter sib2, iclass 34, count 0 2006.257.22:09:37.44#ibcon#flushed, iclass 34, count 0 2006.257.22:09:37.44#ibcon#about to write, iclass 34, count 0 2006.257.22:09:37.44#ibcon#wrote, iclass 34, count 0 2006.257.22:09:37.44#ibcon#about to read 3, iclass 34, count 0 2006.257.22:09:37.47#ibcon#read 3, iclass 34, count 0 2006.257.22:09:37.47#ibcon#about to read 4, iclass 34, count 0 2006.257.22:09:37.47#ibcon#read 4, iclass 34, count 0 2006.257.22:09:37.47#ibcon#about to read 5, iclass 34, count 0 2006.257.22:09:37.47#ibcon#read 5, iclass 34, count 0 2006.257.22:09:37.47#ibcon#about to read 6, iclass 34, count 0 2006.257.22:09:37.47#ibcon#read 6, iclass 34, count 0 2006.257.22:09:37.47#ibcon#end of sib2, iclass 34, count 0 2006.257.22:09:37.47#ibcon#*after write, iclass 34, count 0 2006.257.22:09:37.47#ibcon#*before return 0, iclass 34, count 0 2006.257.22:09:37.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:37.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:37.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.22:09:37.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.22:09:37.47$vck44/valo=7,864.99 2006.257.22:09:37.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.22:09:37.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.22:09:37.47#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:37.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:37.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:37.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:37.47#ibcon#enter wrdev, iclass 36, count 0 2006.257.22:09:37.47#ibcon#first serial, iclass 36, count 0 2006.257.22:09:37.47#ibcon#enter sib2, iclass 36, count 0 2006.257.22:09:37.47#ibcon#flushed, iclass 36, count 0 2006.257.22:09:37.47#ibcon#about to write, iclass 36, count 0 2006.257.22:09:37.47#ibcon#wrote, iclass 36, count 0 2006.257.22:09:37.47#ibcon#about to read 3, iclass 36, count 0 2006.257.22:09:37.49#ibcon#read 3, iclass 36, count 0 2006.257.22:09:37.49#ibcon#about to read 4, iclass 36, count 0 2006.257.22:09:37.49#ibcon#read 4, iclass 36, count 0 2006.257.22:09:37.49#ibcon#about to read 5, iclass 36, count 0 2006.257.22:09:37.49#ibcon#read 5, iclass 36, count 0 2006.257.22:09:37.49#ibcon#about to read 6, iclass 36, count 0 2006.257.22:09:37.49#ibcon#read 6, iclass 36, count 0 2006.257.22:09:37.49#ibcon#end of sib2, iclass 36, count 0 2006.257.22:09:37.49#ibcon#*mode == 0, iclass 36, count 0 2006.257.22:09:37.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.22:09:37.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.22:09:37.49#ibcon#*before write, iclass 36, count 0 2006.257.22:09:37.49#ibcon#enter sib2, iclass 36, count 0 2006.257.22:09:37.49#ibcon#flushed, iclass 36, count 0 2006.257.22:09:37.49#ibcon#about to write, iclass 36, count 0 2006.257.22:09:37.49#ibcon#wrote, iclass 36, count 0 2006.257.22:09:37.49#ibcon#about to read 3, iclass 36, count 0 2006.257.22:09:37.53#ibcon#read 3, iclass 36, count 0 2006.257.22:09:37.53#ibcon#about to read 4, iclass 36, count 0 2006.257.22:09:37.53#ibcon#read 4, iclass 36, count 0 2006.257.22:09:37.53#ibcon#about to read 5, iclass 36, count 0 2006.257.22:09:37.53#ibcon#read 5, iclass 36, count 0 2006.257.22:09:37.53#ibcon#about to read 6, iclass 36, count 0 2006.257.22:09:37.53#ibcon#read 6, iclass 36, count 0 2006.257.22:09:37.53#ibcon#end of sib2, iclass 36, count 0 2006.257.22:09:37.53#ibcon#*after write, iclass 36, count 0 2006.257.22:09:37.53#ibcon#*before return 0, iclass 36, count 0 2006.257.22:09:37.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:37.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:37.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.22:09:37.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.22:09:37.53$vck44/va=7,4 2006.257.22:09:37.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.22:09:37.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.22:09:37.53#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:37.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:37.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:37.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:37.59#ibcon#enter wrdev, iclass 38, count 2 2006.257.22:09:37.59#ibcon#first serial, iclass 38, count 2 2006.257.22:09:37.59#ibcon#enter sib2, iclass 38, count 2 2006.257.22:09:37.59#ibcon#flushed, iclass 38, count 2 2006.257.22:09:37.59#ibcon#about to write, iclass 38, count 2 2006.257.22:09:37.59#ibcon#wrote, iclass 38, count 2 2006.257.22:09:37.59#ibcon#about to read 3, iclass 38, count 2 2006.257.22:09:37.61#ibcon#read 3, iclass 38, count 2 2006.257.22:09:37.61#ibcon#about to read 4, iclass 38, count 2 2006.257.22:09:37.61#ibcon#read 4, iclass 38, count 2 2006.257.22:09:37.61#ibcon#about to read 5, iclass 38, count 2 2006.257.22:09:37.61#ibcon#read 5, iclass 38, count 2 2006.257.22:09:37.61#ibcon#about to read 6, iclass 38, count 2 2006.257.22:09:37.61#ibcon#read 6, iclass 38, count 2 2006.257.22:09:37.61#ibcon#end of sib2, iclass 38, count 2 2006.257.22:09:37.61#ibcon#*mode == 0, iclass 38, count 2 2006.257.22:09:37.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.22:09:37.61#ibcon#[25=AT07-04\r\n] 2006.257.22:09:37.61#ibcon#*before write, iclass 38, count 2 2006.257.22:09:37.61#ibcon#enter sib2, iclass 38, count 2 2006.257.22:09:37.61#ibcon#flushed, iclass 38, count 2 2006.257.22:09:37.61#ibcon#about to write, iclass 38, count 2 2006.257.22:09:37.61#ibcon#wrote, iclass 38, count 2 2006.257.22:09:37.61#ibcon#about to read 3, iclass 38, count 2 2006.257.22:09:37.64#ibcon#read 3, iclass 38, count 2 2006.257.22:09:37.64#ibcon#about to read 4, iclass 38, count 2 2006.257.22:09:37.64#ibcon#read 4, iclass 38, count 2 2006.257.22:09:37.64#ibcon#about to read 5, iclass 38, count 2 2006.257.22:09:37.64#ibcon#read 5, iclass 38, count 2 2006.257.22:09:37.64#ibcon#about to read 6, iclass 38, count 2 2006.257.22:09:37.64#ibcon#read 6, iclass 38, count 2 2006.257.22:09:37.64#ibcon#end of sib2, iclass 38, count 2 2006.257.22:09:37.64#ibcon#*after write, iclass 38, count 2 2006.257.22:09:37.64#ibcon#*before return 0, iclass 38, count 2 2006.257.22:09:37.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:37.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:37.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.22:09:37.64#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:37.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:37.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:37.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:37.76#ibcon#enter wrdev, iclass 38, count 0 2006.257.22:09:37.76#ibcon#first serial, iclass 38, count 0 2006.257.22:09:37.76#ibcon#enter sib2, iclass 38, count 0 2006.257.22:09:37.76#ibcon#flushed, iclass 38, count 0 2006.257.22:09:37.76#ibcon#about to write, iclass 38, count 0 2006.257.22:09:37.76#ibcon#wrote, iclass 38, count 0 2006.257.22:09:37.76#ibcon#about to read 3, iclass 38, count 0 2006.257.22:09:37.78#ibcon#read 3, iclass 38, count 0 2006.257.22:09:37.78#ibcon#about to read 4, iclass 38, count 0 2006.257.22:09:37.78#ibcon#read 4, iclass 38, count 0 2006.257.22:09:37.78#ibcon#about to read 5, iclass 38, count 0 2006.257.22:09:37.78#ibcon#read 5, iclass 38, count 0 2006.257.22:09:37.78#ibcon#about to read 6, iclass 38, count 0 2006.257.22:09:37.78#ibcon#read 6, iclass 38, count 0 2006.257.22:09:37.78#ibcon#end of sib2, iclass 38, count 0 2006.257.22:09:37.78#ibcon#*mode == 0, iclass 38, count 0 2006.257.22:09:37.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.22:09:37.78#ibcon#[25=USB\r\n] 2006.257.22:09:37.78#ibcon#*before write, iclass 38, count 0 2006.257.22:09:37.78#ibcon#enter sib2, iclass 38, count 0 2006.257.22:09:37.78#ibcon#flushed, iclass 38, count 0 2006.257.22:09:37.78#ibcon#about to write, iclass 38, count 0 2006.257.22:09:37.78#ibcon#wrote, iclass 38, count 0 2006.257.22:09:37.78#ibcon#about to read 3, iclass 38, count 0 2006.257.22:09:37.81#ibcon#read 3, iclass 38, count 0 2006.257.22:09:37.81#ibcon#about to read 4, iclass 38, count 0 2006.257.22:09:37.81#ibcon#read 4, iclass 38, count 0 2006.257.22:09:37.81#ibcon#about to read 5, iclass 38, count 0 2006.257.22:09:37.81#ibcon#read 5, iclass 38, count 0 2006.257.22:09:37.81#ibcon#about to read 6, iclass 38, count 0 2006.257.22:09:37.81#ibcon#read 6, iclass 38, count 0 2006.257.22:09:37.81#ibcon#end of sib2, iclass 38, count 0 2006.257.22:09:37.81#ibcon#*after write, iclass 38, count 0 2006.257.22:09:37.81#ibcon#*before return 0, iclass 38, count 0 2006.257.22:09:37.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:37.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:37.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.22:09:37.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.22:09:37.81$vck44/valo=8,884.99 2006.257.22:09:37.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.22:09:37.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.22:09:37.81#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:37.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:37.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:37.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:37.81#ibcon#enter wrdev, iclass 40, count 0 2006.257.22:09:37.81#ibcon#first serial, iclass 40, count 0 2006.257.22:09:37.81#ibcon#enter sib2, iclass 40, count 0 2006.257.22:09:37.81#ibcon#flushed, iclass 40, count 0 2006.257.22:09:37.81#ibcon#about to write, iclass 40, count 0 2006.257.22:09:37.81#ibcon#wrote, iclass 40, count 0 2006.257.22:09:37.81#ibcon#about to read 3, iclass 40, count 0 2006.257.22:09:37.83#ibcon#read 3, iclass 40, count 0 2006.257.22:09:37.83#ibcon#about to read 4, iclass 40, count 0 2006.257.22:09:37.83#ibcon#read 4, iclass 40, count 0 2006.257.22:09:37.83#ibcon#about to read 5, iclass 40, count 0 2006.257.22:09:37.83#ibcon#read 5, iclass 40, count 0 2006.257.22:09:37.83#ibcon#about to read 6, iclass 40, count 0 2006.257.22:09:37.83#ibcon#read 6, iclass 40, count 0 2006.257.22:09:37.83#ibcon#end of sib2, iclass 40, count 0 2006.257.22:09:37.83#ibcon#*mode == 0, iclass 40, count 0 2006.257.22:09:37.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.22:09:37.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.22:09:37.83#ibcon#*before write, iclass 40, count 0 2006.257.22:09:37.83#ibcon#enter sib2, iclass 40, count 0 2006.257.22:09:37.83#ibcon#flushed, iclass 40, count 0 2006.257.22:09:37.83#ibcon#about to write, iclass 40, count 0 2006.257.22:09:37.83#ibcon#wrote, iclass 40, count 0 2006.257.22:09:37.83#ibcon#about to read 3, iclass 40, count 0 2006.257.22:09:37.87#ibcon#read 3, iclass 40, count 0 2006.257.22:09:37.87#ibcon#about to read 4, iclass 40, count 0 2006.257.22:09:37.87#ibcon#read 4, iclass 40, count 0 2006.257.22:09:37.87#ibcon#about to read 5, iclass 40, count 0 2006.257.22:09:37.87#ibcon#read 5, iclass 40, count 0 2006.257.22:09:37.87#ibcon#about to read 6, iclass 40, count 0 2006.257.22:09:37.87#ibcon#read 6, iclass 40, count 0 2006.257.22:09:37.87#ibcon#end of sib2, iclass 40, count 0 2006.257.22:09:37.87#ibcon#*after write, iclass 40, count 0 2006.257.22:09:37.87#ibcon#*before return 0, iclass 40, count 0 2006.257.22:09:37.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:37.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:37.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.22:09:37.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.22:09:37.87$vck44/va=8,4 2006.257.22:09:37.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.22:09:37.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.22:09:37.87#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:37.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:09:37.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:09:37.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:09:37.93#ibcon#enter wrdev, iclass 4, count 2 2006.257.22:09:37.93#ibcon#first serial, iclass 4, count 2 2006.257.22:09:37.93#ibcon#enter sib2, iclass 4, count 2 2006.257.22:09:37.93#ibcon#flushed, iclass 4, count 2 2006.257.22:09:37.93#ibcon#about to write, iclass 4, count 2 2006.257.22:09:37.93#ibcon#wrote, iclass 4, count 2 2006.257.22:09:37.93#ibcon#about to read 3, iclass 4, count 2 2006.257.22:09:37.95#ibcon#read 3, iclass 4, count 2 2006.257.22:09:37.95#ibcon#about to read 4, iclass 4, count 2 2006.257.22:09:37.95#ibcon#read 4, iclass 4, count 2 2006.257.22:09:37.95#ibcon#about to read 5, iclass 4, count 2 2006.257.22:09:37.95#ibcon#read 5, iclass 4, count 2 2006.257.22:09:37.95#ibcon#about to read 6, iclass 4, count 2 2006.257.22:09:37.95#ibcon#read 6, iclass 4, count 2 2006.257.22:09:37.95#ibcon#end of sib2, iclass 4, count 2 2006.257.22:09:37.95#ibcon#*mode == 0, iclass 4, count 2 2006.257.22:09:37.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.22:09:37.95#ibcon#[25=AT08-04\r\n] 2006.257.22:09:37.95#ibcon#*before write, iclass 4, count 2 2006.257.22:09:37.95#ibcon#enter sib2, iclass 4, count 2 2006.257.22:09:37.95#ibcon#flushed, iclass 4, count 2 2006.257.22:09:37.95#ibcon#about to write, iclass 4, count 2 2006.257.22:09:37.95#ibcon#wrote, iclass 4, count 2 2006.257.22:09:37.95#ibcon#about to read 3, iclass 4, count 2 2006.257.22:09:37.98#ibcon#read 3, iclass 4, count 2 2006.257.22:09:37.98#ibcon#about to read 4, iclass 4, count 2 2006.257.22:09:37.98#ibcon#read 4, iclass 4, count 2 2006.257.22:09:37.98#ibcon#about to read 5, iclass 4, count 2 2006.257.22:09:37.98#ibcon#read 5, iclass 4, count 2 2006.257.22:09:37.98#ibcon#about to read 6, iclass 4, count 2 2006.257.22:09:37.98#ibcon#read 6, iclass 4, count 2 2006.257.22:09:37.98#ibcon#end of sib2, iclass 4, count 2 2006.257.22:09:37.98#ibcon#*after write, iclass 4, count 2 2006.257.22:09:37.98#ibcon#*before return 0, iclass 4, count 2 2006.257.22:09:37.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:09:37.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:09:37.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.22:09:37.98#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:37.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:09:38.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:09:38.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:09:38.10#ibcon#enter wrdev, iclass 4, count 0 2006.257.22:09:38.10#ibcon#first serial, iclass 4, count 0 2006.257.22:09:38.10#ibcon#enter sib2, iclass 4, count 0 2006.257.22:09:38.10#ibcon#flushed, iclass 4, count 0 2006.257.22:09:38.10#ibcon#about to write, iclass 4, count 0 2006.257.22:09:38.10#ibcon#wrote, iclass 4, count 0 2006.257.22:09:38.10#ibcon#about to read 3, iclass 4, count 0 2006.257.22:09:38.12#ibcon#read 3, iclass 4, count 0 2006.257.22:09:38.12#ibcon#about to read 4, iclass 4, count 0 2006.257.22:09:38.12#ibcon#read 4, iclass 4, count 0 2006.257.22:09:38.12#ibcon#about to read 5, iclass 4, count 0 2006.257.22:09:38.12#ibcon#read 5, iclass 4, count 0 2006.257.22:09:38.12#ibcon#about to read 6, iclass 4, count 0 2006.257.22:09:38.12#ibcon#read 6, iclass 4, count 0 2006.257.22:09:38.12#ibcon#end of sib2, iclass 4, count 0 2006.257.22:09:38.12#ibcon#*mode == 0, iclass 4, count 0 2006.257.22:09:38.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.22:09:38.12#ibcon#[25=USB\r\n] 2006.257.22:09:38.12#ibcon#*before write, iclass 4, count 0 2006.257.22:09:38.12#ibcon#enter sib2, iclass 4, count 0 2006.257.22:09:38.12#ibcon#flushed, iclass 4, count 0 2006.257.22:09:38.12#ibcon#about to write, iclass 4, count 0 2006.257.22:09:38.12#ibcon#wrote, iclass 4, count 0 2006.257.22:09:38.12#ibcon#about to read 3, iclass 4, count 0 2006.257.22:09:38.15#ibcon#read 3, iclass 4, count 0 2006.257.22:09:38.15#ibcon#about to read 4, iclass 4, count 0 2006.257.22:09:38.15#ibcon#read 4, iclass 4, count 0 2006.257.22:09:38.15#ibcon#about to read 5, iclass 4, count 0 2006.257.22:09:38.15#ibcon#read 5, iclass 4, count 0 2006.257.22:09:38.15#ibcon#about to read 6, iclass 4, count 0 2006.257.22:09:38.15#ibcon#read 6, iclass 4, count 0 2006.257.22:09:38.15#ibcon#end of sib2, iclass 4, count 0 2006.257.22:09:38.15#ibcon#*after write, iclass 4, count 0 2006.257.22:09:38.15#ibcon#*before return 0, iclass 4, count 0 2006.257.22:09:38.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:09:38.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:09:38.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.22:09:38.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.22:09:38.15$vck44/vblo=1,629.99 2006.257.22:09:38.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.22:09:38.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.22:09:38.15#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:38.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:09:38.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:09:38.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:09:38.15#ibcon#enter wrdev, iclass 6, count 0 2006.257.22:09:38.15#ibcon#first serial, iclass 6, count 0 2006.257.22:09:38.15#ibcon#enter sib2, iclass 6, count 0 2006.257.22:09:38.15#ibcon#flushed, iclass 6, count 0 2006.257.22:09:38.15#ibcon#about to write, iclass 6, count 0 2006.257.22:09:38.15#ibcon#wrote, iclass 6, count 0 2006.257.22:09:38.15#ibcon#about to read 3, iclass 6, count 0 2006.257.22:09:38.17#ibcon#read 3, iclass 6, count 0 2006.257.22:09:38.17#ibcon#about to read 4, iclass 6, count 0 2006.257.22:09:38.17#ibcon#read 4, iclass 6, count 0 2006.257.22:09:38.17#ibcon#about to read 5, iclass 6, count 0 2006.257.22:09:38.17#ibcon#read 5, iclass 6, count 0 2006.257.22:09:38.17#ibcon#about to read 6, iclass 6, count 0 2006.257.22:09:38.17#ibcon#read 6, iclass 6, count 0 2006.257.22:09:38.17#ibcon#end of sib2, iclass 6, count 0 2006.257.22:09:38.17#ibcon#*mode == 0, iclass 6, count 0 2006.257.22:09:38.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.22:09:38.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.22:09:38.17#ibcon#*before write, iclass 6, count 0 2006.257.22:09:38.17#ibcon#enter sib2, iclass 6, count 0 2006.257.22:09:38.17#ibcon#flushed, iclass 6, count 0 2006.257.22:09:38.17#ibcon#about to write, iclass 6, count 0 2006.257.22:09:38.17#ibcon#wrote, iclass 6, count 0 2006.257.22:09:38.17#ibcon#about to read 3, iclass 6, count 0 2006.257.22:09:38.21#ibcon#read 3, iclass 6, count 0 2006.257.22:09:38.21#ibcon#about to read 4, iclass 6, count 0 2006.257.22:09:38.21#ibcon#read 4, iclass 6, count 0 2006.257.22:09:38.21#ibcon#about to read 5, iclass 6, count 0 2006.257.22:09:38.21#ibcon#read 5, iclass 6, count 0 2006.257.22:09:38.21#ibcon#about to read 6, iclass 6, count 0 2006.257.22:09:38.21#ibcon#read 6, iclass 6, count 0 2006.257.22:09:38.21#ibcon#end of sib2, iclass 6, count 0 2006.257.22:09:38.21#ibcon#*after write, iclass 6, count 0 2006.257.22:09:38.21#ibcon#*before return 0, iclass 6, count 0 2006.257.22:09:38.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:09:38.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:09:38.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.22:09:38.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.22:09:38.21$vck44/vb=1,4 2006.257.22:09:38.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.22:09:38.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.22:09:38.21#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:38.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:09:38.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:09:38.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:09:38.21#ibcon#enter wrdev, iclass 10, count 2 2006.257.22:09:38.21#ibcon#first serial, iclass 10, count 2 2006.257.22:09:38.21#ibcon#enter sib2, iclass 10, count 2 2006.257.22:09:38.21#ibcon#flushed, iclass 10, count 2 2006.257.22:09:38.21#ibcon#about to write, iclass 10, count 2 2006.257.22:09:38.21#ibcon#wrote, iclass 10, count 2 2006.257.22:09:38.21#ibcon#about to read 3, iclass 10, count 2 2006.257.22:09:38.23#ibcon#read 3, iclass 10, count 2 2006.257.22:09:38.23#ibcon#about to read 4, iclass 10, count 2 2006.257.22:09:38.23#ibcon#read 4, iclass 10, count 2 2006.257.22:09:38.23#ibcon#about to read 5, iclass 10, count 2 2006.257.22:09:38.23#ibcon#read 5, iclass 10, count 2 2006.257.22:09:38.23#ibcon#about to read 6, iclass 10, count 2 2006.257.22:09:38.23#ibcon#read 6, iclass 10, count 2 2006.257.22:09:38.23#ibcon#end of sib2, iclass 10, count 2 2006.257.22:09:38.23#ibcon#*mode == 0, iclass 10, count 2 2006.257.22:09:38.23#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.22:09:38.23#ibcon#[27=AT01-04\r\n] 2006.257.22:09:38.23#ibcon#*before write, iclass 10, count 2 2006.257.22:09:38.23#ibcon#enter sib2, iclass 10, count 2 2006.257.22:09:38.23#ibcon#flushed, iclass 10, count 2 2006.257.22:09:38.23#ibcon#about to write, iclass 10, count 2 2006.257.22:09:38.23#ibcon#wrote, iclass 10, count 2 2006.257.22:09:38.23#ibcon#about to read 3, iclass 10, count 2 2006.257.22:09:38.26#ibcon#read 3, iclass 10, count 2 2006.257.22:09:38.26#ibcon#about to read 4, iclass 10, count 2 2006.257.22:09:38.26#ibcon#read 4, iclass 10, count 2 2006.257.22:09:38.26#ibcon#about to read 5, iclass 10, count 2 2006.257.22:09:38.26#ibcon#read 5, iclass 10, count 2 2006.257.22:09:38.26#ibcon#about to read 6, iclass 10, count 2 2006.257.22:09:38.26#ibcon#read 6, iclass 10, count 2 2006.257.22:09:38.26#ibcon#end of sib2, iclass 10, count 2 2006.257.22:09:38.26#ibcon#*after write, iclass 10, count 2 2006.257.22:09:38.26#ibcon#*before return 0, iclass 10, count 2 2006.257.22:09:38.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:09:38.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:09:38.26#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.22:09:38.26#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:38.26#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:09:38.38#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:09:38.38#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:09:38.38#ibcon#enter wrdev, iclass 10, count 0 2006.257.22:09:38.38#ibcon#first serial, iclass 10, count 0 2006.257.22:09:38.38#ibcon#enter sib2, iclass 10, count 0 2006.257.22:09:38.38#ibcon#flushed, iclass 10, count 0 2006.257.22:09:38.38#ibcon#about to write, iclass 10, count 0 2006.257.22:09:38.38#ibcon#wrote, iclass 10, count 0 2006.257.22:09:38.38#ibcon#about to read 3, iclass 10, count 0 2006.257.22:09:38.40#ibcon#read 3, iclass 10, count 0 2006.257.22:09:38.40#ibcon#about to read 4, iclass 10, count 0 2006.257.22:09:38.40#ibcon#read 4, iclass 10, count 0 2006.257.22:09:38.40#ibcon#about to read 5, iclass 10, count 0 2006.257.22:09:38.40#ibcon#read 5, iclass 10, count 0 2006.257.22:09:38.40#ibcon#about to read 6, iclass 10, count 0 2006.257.22:09:38.40#ibcon#read 6, iclass 10, count 0 2006.257.22:09:38.40#ibcon#end of sib2, iclass 10, count 0 2006.257.22:09:38.40#ibcon#*mode == 0, iclass 10, count 0 2006.257.22:09:38.40#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.22:09:38.40#ibcon#[27=USB\r\n] 2006.257.22:09:38.40#ibcon#*before write, iclass 10, count 0 2006.257.22:09:38.40#ibcon#enter sib2, iclass 10, count 0 2006.257.22:09:38.40#ibcon#flushed, iclass 10, count 0 2006.257.22:09:38.40#ibcon#about to write, iclass 10, count 0 2006.257.22:09:38.40#ibcon#wrote, iclass 10, count 0 2006.257.22:09:38.40#ibcon#about to read 3, iclass 10, count 0 2006.257.22:09:38.43#ibcon#read 3, iclass 10, count 0 2006.257.22:09:38.43#ibcon#about to read 4, iclass 10, count 0 2006.257.22:09:38.43#ibcon#read 4, iclass 10, count 0 2006.257.22:09:38.43#ibcon#about to read 5, iclass 10, count 0 2006.257.22:09:38.43#ibcon#read 5, iclass 10, count 0 2006.257.22:09:38.43#ibcon#about to read 6, iclass 10, count 0 2006.257.22:09:38.43#ibcon#read 6, iclass 10, count 0 2006.257.22:09:38.43#ibcon#end of sib2, iclass 10, count 0 2006.257.22:09:38.43#ibcon#*after write, iclass 10, count 0 2006.257.22:09:38.43#ibcon#*before return 0, iclass 10, count 0 2006.257.22:09:38.43#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:09:38.43#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:09:38.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.22:09:38.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.22:09:38.43$vck44/vblo=2,634.99 2006.257.22:09:38.43#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.22:09:38.43#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.22:09:38.43#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:38.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:38.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:38.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:38.43#ibcon#enter wrdev, iclass 12, count 0 2006.257.22:09:38.43#ibcon#first serial, iclass 12, count 0 2006.257.22:09:38.43#ibcon#enter sib2, iclass 12, count 0 2006.257.22:09:38.43#ibcon#flushed, iclass 12, count 0 2006.257.22:09:38.43#ibcon#about to write, iclass 12, count 0 2006.257.22:09:38.43#ibcon#wrote, iclass 12, count 0 2006.257.22:09:38.43#ibcon#about to read 3, iclass 12, count 0 2006.257.22:09:38.45#ibcon#read 3, iclass 12, count 0 2006.257.22:09:38.45#ibcon#about to read 4, iclass 12, count 0 2006.257.22:09:38.45#ibcon#read 4, iclass 12, count 0 2006.257.22:09:38.45#ibcon#about to read 5, iclass 12, count 0 2006.257.22:09:38.45#ibcon#read 5, iclass 12, count 0 2006.257.22:09:38.45#ibcon#about to read 6, iclass 12, count 0 2006.257.22:09:38.45#ibcon#read 6, iclass 12, count 0 2006.257.22:09:38.45#ibcon#end of sib2, iclass 12, count 0 2006.257.22:09:38.45#ibcon#*mode == 0, iclass 12, count 0 2006.257.22:09:38.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.22:09:38.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.22:09:38.45#ibcon#*before write, iclass 12, count 0 2006.257.22:09:38.45#ibcon#enter sib2, iclass 12, count 0 2006.257.22:09:38.45#ibcon#flushed, iclass 12, count 0 2006.257.22:09:38.45#ibcon#about to write, iclass 12, count 0 2006.257.22:09:38.45#ibcon#wrote, iclass 12, count 0 2006.257.22:09:38.45#ibcon#about to read 3, iclass 12, count 0 2006.257.22:09:38.49#ibcon#read 3, iclass 12, count 0 2006.257.22:09:38.49#ibcon#about to read 4, iclass 12, count 0 2006.257.22:09:38.49#ibcon#read 4, iclass 12, count 0 2006.257.22:09:38.49#ibcon#about to read 5, iclass 12, count 0 2006.257.22:09:38.49#ibcon#read 5, iclass 12, count 0 2006.257.22:09:38.49#ibcon#about to read 6, iclass 12, count 0 2006.257.22:09:38.49#ibcon#read 6, iclass 12, count 0 2006.257.22:09:38.49#ibcon#end of sib2, iclass 12, count 0 2006.257.22:09:38.49#ibcon#*after write, iclass 12, count 0 2006.257.22:09:38.49#ibcon#*before return 0, iclass 12, count 0 2006.257.22:09:38.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:38.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:09:38.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.22:09:38.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.22:09:38.49$vck44/vb=2,5 2006.257.22:09:38.49#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.22:09:38.49#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.22:09:38.49#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:38.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:38.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:38.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:38.55#ibcon#enter wrdev, iclass 14, count 2 2006.257.22:09:38.55#ibcon#first serial, iclass 14, count 2 2006.257.22:09:38.55#ibcon#enter sib2, iclass 14, count 2 2006.257.22:09:38.55#ibcon#flushed, iclass 14, count 2 2006.257.22:09:38.55#ibcon#about to write, iclass 14, count 2 2006.257.22:09:38.55#ibcon#wrote, iclass 14, count 2 2006.257.22:09:38.55#ibcon#about to read 3, iclass 14, count 2 2006.257.22:09:38.57#ibcon#read 3, iclass 14, count 2 2006.257.22:09:38.57#ibcon#about to read 4, iclass 14, count 2 2006.257.22:09:38.57#ibcon#read 4, iclass 14, count 2 2006.257.22:09:38.57#ibcon#about to read 5, iclass 14, count 2 2006.257.22:09:38.57#ibcon#read 5, iclass 14, count 2 2006.257.22:09:38.57#ibcon#about to read 6, iclass 14, count 2 2006.257.22:09:38.57#ibcon#read 6, iclass 14, count 2 2006.257.22:09:38.57#ibcon#end of sib2, iclass 14, count 2 2006.257.22:09:38.57#ibcon#*mode == 0, iclass 14, count 2 2006.257.22:09:38.57#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.22:09:38.57#ibcon#[27=AT02-05\r\n] 2006.257.22:09:38.57#ibcon#*before write, iclass 14, count 2 2006.257.22:09:38.57#ibcon#enter sib2, iclass 14, count 2 2006.257.22:09:38.57#ibcon#flushed, iclass 14, count 2 2006.257.22:09:38.57#ibcon#about to write, iclass 14, count 2 2006.257.22:09:38.57#ibcon#wrote, iclass 14, count 2 2006.257.22:09:38.57#ibcon#about to read 3, iclass 14, count 2 2006.257.22:09:38.60#ibcon#read 3, iclass 14, count 2 2006.257.22:09:38.60#ibcon#about to read 4, iclass 14, count 2 2006.257.22:09:38.60#ibcon#read 4, iclass 14, count 2 2006.257.22:09:38.60#ibcon#about to read 5, iclass 14, count 2 2006.257.22:09:38.60#ibcon#read 5, iclass 14, count 2 2006.257.22:09:38.60#ibcon#about to read 6, iclass 14, count 2 2006.257.22:09:38.60#ibcon#read 6, iclass 14, count 2 2006.257.22:09:38.60#ibcon#end of sib2, iclass 14, count 2 2006.257.22:09:38.60#ibcon#*after write, iclass 14, count 2 2006.257.22:09:38.60#ibcon#*before return 0, iclass 14, count 2 2006.257.22:09:38.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:38.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:09:38.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.22:09:38.60#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:38.60#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:38.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:38.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:38.72#ibcon#enter wrdev, iclass 14, count 0 2006.257.22:09:38.72#ibcon#first serial, iclass 14, count 0 2006.257.22:09:38.72#ibcon#enter sib2, iclass 14, count 0 2006.257.22:09:38.72#ibcon#flushed, iclass 14, count 0 2006.257.22:09:38.72#ibcon#about to write, iclass 14, count 0 2006.257.22:09:38.72#ibcon#wrote, iclass 14, count 0 2006.257.22:09:38.72#ibcon#about to read 3, iclass 14, count 0 2006.257.22:09:38.74#ibcon#read 3, iclass 14, count 0 2006.257.22:09:38.74#ibcon#about to read 4, iclass 14, count 0 2006.257.22:09:38.74#ibcon#read 4, iclass 14, count 0 2006.257.22:09:38.74#ibcon#about to read 5, iclass 14, count 0 2006.257.22:09:38.74#ibcon#read 5, iclass 14, count 0 2006.257.22:09:38.74#ibcon#about to read 6, iclass 14, count 0 2006.257.22:09:38.74#ibcon#read 6, iclass 14, count 0 2006.257.22:09:38.74#ibcon#end of sib2, iclass 14, count 0 2006.257.22:09:38.74#ibcon#*mode == 0, iclass 14, count 0 2006.257.22:09:38.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.22:09:38.74#ibcon#[27=USB\r\n] 2006.257.22:09:38.74#ibcon#*before write, iclass 14, count 0 2006.257.22:09:38.74#ibcon#enter sib2, iclass 14, count 0 2006.257.22:09:38.74#ibcon#flushed, iclass 14, count 0 2006.257.22:09:38.74#ibcon#about to write, iclass 14, count 0 2006.257.22:09:38.74#ibcon#wrote, iclass 14, count 0 2006.257.22:09:38.74#ibcon#about to read 3, iclass 14, count 0 2006.257.22:09:38.77#ibcon#read 3, iclass 14, count 0 2006.257.22:09:38.77#ibcon#about to read 4, iclass 14, count 0 2006.257.22:09:38.77#ibcon#read 4, iclass 14, count 0 2006.257.22:09:38.77#ibcon#about to read 5, iclass 14, count 0 2006.257.22:09:38.77#ibcon#read 5, iclass 14, count 0 2006.257.22:09:38.77#ibcon#about to read 6, iclass 14, count 0 2006.257.22:09:38.77#ibcon#read 6, iclass 14, count 0 2006.257.22:09:38.77#ibcon#end of sib2, iclass 14, count 0 2006.257.22:09:38.77#ibcon#*after write, iclass 14, count 0 2006.257.22:09:38.77#ibcon#*before return 0, iclass 14, count 0 2006.257.22:09:38.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:38.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:09:38.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.22:09:38.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.22:09:38.77$vck44/vblo=3,649.99 2006.257.22:09:38.77#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.22:09:38.77#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.22:09:38.77#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:38.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:38.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:38.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:38.77#ibcon#enter wrdev, iclass 16, count 0 2006.257.22:09:38.77#ibcon#first serial, iclass 16, count 0 2006.257.22:09:38.77#ibcon#enter sib2, iclass 16, count 0 2006.257.22:09:38.77#ibcon#flushed, iclass 16, count 0 2006.257.22:09:38.77#ibcon#about to write, iclass 16, count 0 2006.257.22:09:38.77#ibcon#wrote, iclass 16, count 0 2006.257.22:09:38.77#ibcon#about to read 3, iclass 16, count 0 2006.257.22:09:38.79#ibcon#read 3, iclass 16, count 0 2006.257.22:09:38.79#ibcon#about to read 4, iclass 16, count 0 2006.257.22:09:38.79#ibcon#read 4, iclass 16, count 0 2006.257.22:09:38.79#ibcon#about to read 5, iclass 16, count 0 2006.257.22:09:38.79#ibcon#read 5, iclass 16, count 0 2006.257.22:09:38.79#ibcon#about to read 6, iclass 16, count 0 2006.257.22:09:38.79#ibcon#read 6, iclass 16, count 0 2006.257.22:09:38.79#ibcon#end of sib2, iclass 16, count 0 2006.257.22:09:38.79#ibcon#*mode == 0, iclass 16, count 0 2006.257.22:09:38.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.22:09:38.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.22:09:38.79#ibcon#*before write, iclass 16, count 0 2006.257.22:09:38.79#ibcon#enter sib2, iclass 16, count 0 2006.257.22:09:38.79#ibcon#flushed, iclass 16, count 0 2006.257.22:09:38.79#ibcon#about to write, iclass 16, count 0 2006.257.22:09:38.79#ibcon#wrote, iclass 16, count 0 2006.257.22:09:38.79#ibcon#about to read 3, iclass 16, count 0 2006.257.22:09:38.83#ibcon#read 3, iclass 16, count 0 2006.257.22:09:38.83#ibcon#about to read 4, iclass 16, count 0 2006.257.22:09:38.83#ibcon#read 4, iclass 16, count 0 2006.257.22:09:38.83#ibcon#about to read 5, iclass 16, count 0 2006.257.22:09:38.83#ibcon#read 5, iclass 16, count 0 2006.257.22:09:38.83#ibcon#about to read 6, iclass 16, count 0 2006.257.22:09:38.83#ibcon#read 6, iclass 16, count 0 2006.257.22:09:38.83#ibcon#end of sib2, iclass 16, count 0 2006.257.22:09:38.83#ibcon#*after write, iclass 16, count 0 2006.257.22:09:38.83#ibcon#*before return 0, iclass 16, count 0 2006.257.22:09:38.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:38.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:09:38.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.22:09:38.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.22:09:38.83$vck44/vb=3,4 2006.257.22:09:38.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.22:09:38.83#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.22:09:38.83#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:38.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:38.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:38.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:38.89#ibcon#enter wrdev, iclass 18, count 2 2006.257.22:09:38.89#ibcon#first serial, iclass 18, count 2 2006.257.22:09:38.89#ibcon#enter sib2, iclass 18, count 2 2006.257.22:09:38.89#ibcon#flushed, iclass 18, count 2 2006.257.22:09:38.89#ibcon#about to write, iclass 18, count 2 2006.257.22:09:38.89#ibcon#wrote, iclass 18, count 2 2006.257.22:09:38.89#ibcon#about to read 3, iclass 18, count 2 2006.257.22:09:38.91#ibcon#read 3, iclass 18, count 2 2006.257.22:09:38.91#ibcon#about to read 4, iclass 18, count 2 2006.257.22:09:38.91#ibcon#read 4, iclass 18, count 2 2006.257.22:09:38.91#ibcon#about to read 5, iclass 18, count 2 2006.257.22:09:38.91#ibcon#read 5, iclass 18, count 2 2006.257.22:09:38.91#ibcon#about to read 6, iclass 18, count 2 2006.257.22:09:38.91#ibcon#read 6, iclass 18, count 2 2006.257.22:09:38.91#ibcon#end of sib2, iclass 18, count 2 2006.257.22:09:38.91#ibcon#*mode == 0, iclass 18, count 2 2006.257.22:09:38.91#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.22:09:38.91#ibcon#[27=AT03-04\r\n] 2006.257.22:09:38.91#ibcon#*before write, iclass 18, count 2 2006.257.22:09:38.91#ibcon#enter sib2, iclass 18, count 2 2006.257.22:09:38.91#ibcon#flushed, iclass 18, count 2 2006.257.22:09:38.91#ibcon#about to write, iclass 18, count 2 2006.257.22:09:38.91#ibcon#wrote, iclass 18, count 2 2006.257.22:09:38.91#ibcon#about to read 3, iclass 18, count 2 2006.257.22:09:38.94#ibcon#read 3, iclass 18, count 2 2006.257.22:09:38.94#ibcon#about to read 4, iclass 18, count 2 2006.257.22:09:38.94#ibcon#read 4, iclass 18, count 2 2006.257.22:09:38.94#ibcon#about to read 5, iclass 18, count 2 2006.257.22:09:38.94#ibcon#read 5, iclass 18, count 2 2006.257.22:09:38.94#ibcon#about to read 6, iclass 18, count 2 2006.257.22:09:38.94#ibcon#read 6, iclass 18, count 2 2006.257.22:09:38.94#ibcon#end of sib2, iclass 18, count 2 2006.257.22:09:38.94#ibcon#*after write, iclass 18, count 2 2006.257.22:09:38.94#ibcon#*before return 0, iclass 18, count 2 2006.257.22:09:38.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:38.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:09:38.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.22:09:38.94#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:38.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:39.06#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:39.06#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:39.06#ibcon#enter wrdev, iclass 18, count 0 2006.257.22:09:39.06#ibcon#first serial, iclass 18, count 0 2006.257.22:09:39.06#ibcon#enter sib2, iclass 18, count 0 2006.257.22:09:39.06#ibcon#flushed, iclass 18, count 0 2006.257.22:09:39.06#ibcon#about to write, iclass 18, count 0 2006.257.22:09:39.06#ibcon#wrote, iclass 18, count 0 2006.257.22:09:39.06#ibcon#about to read 3, iclass 18, count 0 2006.257.22:09:39.08#ibcon#read 3, iclass 18, count 0 2006.257.22:09:39.08#ibcon#about to read 4, iclass 18, count 0 2006.257.22:09:39.08#ibcon#read 4, iclass 18, count 0 2006.257.22:09:39.08#ibcon#about to read 5, iclass 18, count 0 2006.257.22:09:39.08#ibcon#read 5, iclass 18, count 0 2006.257.22:09:39.08#ibcon#about to read 6, iclass 18, count 0 2006.257.22:09:39.08#ibcon#read 6, iclass 18, count 0 2006.257.22:09:39.08#ibcon#end of sib2, iclass 18, count 0 2006.257.22:09:39.08#ibcon#*mode == 0, iclass 18, count 0 2006.257.22:09:39.08#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.22:09:39.08#ibcon#[27=USB\r\n] 2006.257.22:09:39.08#ibcon#*before write, iclass 18, count 0 2006.257.22:09:39.08#ibcon#enter sib2, iclass 18, count 0 2006.257.22:09:39.08#ibcon#flushed, iclass 18, count 0 2006.257.22:09:39.08#ibcon#about to write, iclass 18, count 0 2006.257.22:09:39.08#ibcon#wrote, iclass 18, count 0 2006.257.22:09:39.08#ibcon#about to read 3, iclass 18, count 0 2006.257.22:09:39.11#ibcon#read 3, iclass 18, count 0 2006.257.22:09:39.11#ibcon#about to read 4, iclass 18, count 0 2006.257.22:09:39.11#ibcon#read 4, iclass 18, count 0 2006.257.22:09:39.11#ibcon#about to read 5, iclass 18, count 0 2006.257.22:09:39.11#ibcon#read 5, iclass 18, count 0 2006.257.22:09:39.11#ibcon#about to read 6, iclass 18, count 0 2006.257.22:09:39.11#ibcon#read 6, iclass 18, count 0 2006.257.22:09:39.11#ibcon#end of sib2, iclass 18, count 0 2006.257.22:09:39.11#ibcon#*after write, iclass 18, count 0 2006.257.22:09:39.11#ibcon#*before return 0, iclass 18, count 0 2006.257.22:09:39.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:39.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:09:39.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.22:09:39.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.22:09:39.11$vck44/vblo=4,679.99 2006.257.22:09:39.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.22:09:39.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.22:09:39.11#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:39.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:39.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:39.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:39.11#ibcon#enter wrdev, iclass 20, count 0 2006.257.22:09:39.11#ibcon#first serial, iclass 20, count 0 2006.257.22:09:39.11#ibcon#enter sib2, iclass 20, count 0 2006.257.22:09:39.11#ibcon#flushed, iclass 20, count 0 2006.257.22:09:39.11#ibcon#about to write, iclass 20, count 0 2006.257.22:09:39.11#ibcon#wrote, iclass 20, count 0 2006.257.22:09:39.11#ibcon#about to read 3, iclass 20, count 0 2006.257.22:09:39.13#ibcon#read 3, iclass 20, count 0 2006.257.22:09:39.13#ibcon#about to read 4, iclass 20, count 0 2006.257.22:09:39.13#ibcon#read 4, iclass 20, count 0 2006.257.22:09:39.13#ibcon#about to read 5, iclass 20, count 0 2006.257.22:09:39.13#ibcon#read 5, iclass 20, count 0 2006.257.22:09:39.13#ibcon#about to read 6, iclass 20, count 0 2006.257.22:09:39.13#ibcon#read 6, iclass 20, count 0 2006.257.22:09:39.13#ibcon#end of sib2, iclass 20, count 0 2006.257.22:09:39.13#ibcon#*mode == 0, iclass 20, count 0 2006.257.22:09:39.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.22:09:39.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.22:09:39.13#ibcon#*before write, iclass 20, count 0 2006.257.22:09:39.13#ibcon#enter sib2, iclass 20, count 0 2006.257.22:09:39.13#ibcon#flushed, iclass 20, count 0 2006.257.22:09:39.13#ibcon#about to write, iclass 20, count 0 2006.257.22:09:39.13#ibcon#wrote, iclass 20, count 0 2006.257.22:09:39.13#ibcon#about to read 3, iclass 20, count 0 2006.257.22:09:39.17#ibcon#read 3, iclass 20, count 0 2006.257.22:09:39.17#ibcon#about to read 4, iclass 20, count 0 2006.257.22:09:39.17#ibcon#read 4, iclass 20, count 0 2006.257.22:09:39.17#ibcon#about to read 5, iclass 20, count 0 2006.257.22:09:39.17#ibcon#read 5, iclass 20, count 0 2006.257.22:09:39.17#ibcon#about to read 6, iclass 20, count 0 2006.257.22:09:39.17#ibcon#read 6, iclass 20, count 0 2006.257.22:09:39.17#ibcon#end of sib2, iclass 20, count 0 2006.257.22:09:39.17#ibcon#*after write, iclass 20, count 0 2006.257.22:09:39.17#ibcon#*before return 0, iclass 20, count 0 2006.257.22:09:39.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:39.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:09:39.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.22:09:39.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.22:09:39.17$vck44/vb=4,5 2006.257.22:09:39.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.22:09:39.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.22:09:39.17#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:39.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:39.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:39.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:39.23#ibcon#enter wrdev, iclass 22, count 2 2006.257.22:09:39.23#ibcon#first serial, iclass 22, count 2 2006.257.22:09:39.23#ibcon#enter sib2, iclass 22, count 2 2006.257.22:09:39.23#ibcon#flushed, iclass 22, count 2 2006.257.22:09:39.23#ibcon#about to write, iclass 22, count 2 2006.257.22:09:39.23#ibcon#wrote, iclass 22, count 2 2006.257.22:09:39.23#ibcon#about to read 3, iclass 22, count 2 2006.257.22:09:39.25#ibcon#read 3, iclass 22, count 2 2006.257.22:09:39.25#ibcon#about to read 4, iclass 22, count 2 2006.257.22:09:39.25#ibcon#read 4, iclass 22, count 2 2006.257.22:09:39.25#ibcon#about to read 5, iclass 22, count 2 2006.257.22:09:39.25#ibcon#read 5, iclass 22, count 2 2006.257.22:09:39.25#ibcon#about to read 6, iclass 22, count 2 2006.257.22:09:39.25#ibcon#read 6, iclass 22, count 2 2006.257.22:09:39.25#ibcon#end of sib2, iclass 22, count 2 2006.257.22:09:39.25#ibcon#*mode == 0, iclass 22, count 2 2006.257.22:09:39.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.22:09:39.25#ibcon#[27=AT04-05\r\n] 2006.257.22:09:39.25#ibcon#*before write, iclass 22, count 2 2006.257.22:09:39.25#ibcon#enter sib2, iclass 22, count 2 2006.257.22:09:39.25#ibcon#flushed, iclass 22, count 2 2006.257.22:09:39.25#ibcon#about to write, iclass 22, count 2 2006.257.22:09:39.25#ibcon#wrote, iclass 22, count 2 2006.257.22:09:39.25#ibcon#about to read 3, iclass 22, count 2 2006.257.22:09:39.28#ibcon#read 3, iclass 22, count 2 2006.257.22:09:39.28#ibcon#about to read 4, iclass 22, count 2 2006.257.22:09:39.28#ibcon#read 4, iclass 22, count 2 2006.257.22:09:39.28#ibcon#about to read 5, iclass 22, count 2 2006.257.22:09:39.28#ibcon#read 5, iclass 22, count 2 2006.257.22:09:39.28#ibcon#about to read 6, iclass 22, count 2 2006.257.22:09:39.28#ibcon#read 6, iclass 22, count 2 2006.257.22:09:39.28#ibcon#end of sib2, iclass 22, count 2 2006.257.22:09:39.28#ibcon#*after write, iclass 22, count 2 2006.257.22:09:39.28#ibcon#*before return 0, iclass 22, count 2 2006.257.22:09:39.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:39.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:09:39.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.22:09:39.28#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:39.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:39.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:39.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:39.40#ibcon#enter wrdev, iclass 22, count 0 2006.257.22:09:39.40#ibcon#first serial, iclass 22, count 0 2006.257.22:09:39.40#ibcon#enter sib2, iclass 22, count 0 2006.257.22:09:39.40#ibcon#flushed, iclass 22, count 0 2006.257.22:09:39.40#ibcon#about to write, iclass 22, count 0 2006.257.22:09:39.40#ibcon#wrote, iclass 22, count 0 2006.257.22:09:39.40#ibcon#about to read 3, iclass 22, count 0 2006.257.22:09:39.42#ibcon#read 3, iclass 22, count 0 2006.257.22:09:39.42#ibcon#about to read 4, iclass 22, count 0 2006.257.22:09:39.42#ibcon#read 4, iclass 22, count 0 2006.257.22:09:39.42#ibcon#about to read 5, iclass 22, count 0 2006.257.22:09:39.42#ibcon#read 5, iclass 22, count 0 2006.257.22:09:39.42#ibcon#about to read 6, iclass 22, count 0 2006.257.22:09:39.42#ibcon#read 6, iclass 22, count 0 2006.257.22:09:39.42#ibcon#end of sib2, iclass 22, count 0 2006.257.22:09:39.42#ibcon#*mode == 0, iclass 22, count 0 2006.257.22:09:39.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.22:09:39.42#ibcon#[27=USB\r\n] 2006.257.22:09:39.42#ibcon#*before write, iclass 22, count 0 2006.257.22:09:39.42#ibcon#enter sib2, iclass 22, count 0 2006.257.22:09:39.42#ibcon#flushed, iclass 22, count 0 2006.257.22:09:39.42#ibcon#about to write, iclass 22, count 0 2006.257.22:09:39.42#ibcon#wrote, iclass 22, count 0 2006.257.22:09:39.42#ibcon#about to read 3, iclass 22, count 0 2006.257.22:09:39.45#ibcon#read 3, iclass 22, count 0 2006.257.22:09:39.45#ibcon#about to read 4, iclass 22, count 0 2006.257.22:09:39.45#ibcon#read 4, iclass 22, count 0 2006.257.22:09:39.45#ibcon#about to read 5, iclass 22, count 0 2006.257.22:09:39.45#ibcon#read 5, iclass 22, count 0 2006.257.22:09:39.45#ibcon#about to read 6, iclass 22, count 0 2006.257.22:09:39.45#ibcon#read 6, iclass 22, count 0 2006.257.22:09:39.45#ibcon#end of sib2, iclass 22, count 0 2006.257.22:09:39.45#ibcon#*after write, iclass 22, count 0 2006.257.22:09:39.45#ibcon#*before return 0, iclass 22, count 0 2006.257.22:09:39.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:39.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:09:39.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.22:09:39.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.22:09:39.45$vck44/vblo=5,709.99 2006.257.22:09:39.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.22:09:39.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.22:09:39.45#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:39.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:39.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:39.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:39.45#ibcon#enter wrdev, iclass 24, count 0 2006.257.22:09:39.45#ibcon#first serial, iclass 24, count 0 2006.257.22:09:39.45#ibcon#enter sib2, iclass 24, count 0 2006.257.22:09:39.45#ibcon#flushed, iclass 24, count 0 2006.257.22:09:39.45#ibcon#about to write, iclass 24, count 0 2006.257.22:09:39.45#ibcon#wrote, iclass 24, count 0 2006.257.22:09:39.45#ibcon#about to read 3, iclass 24, count 0 2006.257.22:09:39.47#ibcon#read 3, iclass 24, count 0 2006.257.22:09:39.47#ibcon#about to read 4, iclass 24, count 0 2006.257.22:09:39.47#ibcon#read 4, iclass 24, count 0 2006.257.22:09:39.47#ibcon#about to read 5, iclass 24, count 0 2006.257.22:09:39.47#ibcon#read 5, iclass 24, count 0 2006.257.22:09:39.47#ibcon#about to read 6, iclass 24, count 0 2006.257.22:09:39.47#ibcon#read 6, iclass 24, count 0 2006.257.22:09:39.47#ibcon#end of sib2, iclass 24, count 0 2006.257.22:09:39.47#ibcon#*mode == 0, iclass 24, count 0 2006.257.22:09:39.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.22:09:39.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.22:09:39.47#ibcon#*before write, iclass 24, count 0 2006.257.22:09:39.47#ibcon#enter sib2, iclass 24, count 0 2006.257.22:09:39.47#ibcon#flushed, iclass 24, count 0 2006.257.22:09:39.47#ibcon#about to write, iclass 24, count 0 2006.257.22:09:39.47#ibcon#wrote, iclass 24, count 0 2006.257.22:09:39.47#ibcon#about to read 3, iclass 24, count 0 2006.257.22:09:39.51#ibcon#read 3, iclass 24, count 0 2006.257.22:09:39.51#ibcon#about to read 4, iclass 24, count 0 2006.257.22:09:39.51#ibcon#read 4, iclass 24, count 0 2006.257.22:09:39.51#ibcon#about to read 5, iclass 24, count 0 2006.257.22:09:39.51#ibcon#read 5, iclass 24, count 0 2006.257.22:09:39.51#ibcon#about to read 6, iclass 24, count 0 2006.257.22:09:39.51#ibcon#read 6, iclass 24, count 0 2006.257.22:09:39.51#ibcon#end of sib2, iclass 24, count 0 2006.257.22:09:39.51#ibcon#*after write, iclass 24, count 0 2006.257.22:09:39.51#ibcon#*before return 0, iclass 24, count 0 2006.257.22:09:39.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:39.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:09:39.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.22:09:39.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.22:09:39.51$vck44/vb=5,4 2006.257.22:09:39.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.22:09:39.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.22:09:39.51#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:39.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:39.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:39.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:39.57#ibcon#enter wrdev, iclass 26, count 2 2006.257.22:09:39.57#ibcon#first serial, iclass 26, count 2 2006.257.22:09:39.57#ibcon#enter sib2, iclass 26, count 2 2006.257.22:09:39.57#ibcon#flushed, iclass 26, count 2 2006.257.22:09:39.57#ibcon#about to write, iclass 26, count 2 2006.257.22:09:39.57#ibcon#wrote, iclass 26, count 2 2006.257.22:09:39.57#ibcon#about to read 3, iclass 26, count 2 2006.257.22:09:39.59#ibcon#read 3, iclass 26, count 2 2006.257.22:09:39.59#ibcon#about to read 4, iclass 26, count 2 2006.257.22:09:39.59#ibcon#read 4, iclass 26, count 2 2006.257.22:09:39.59#ibcon#about to read 5, iclass 26, count 2 2006.257.22:09:39.59#ibcon#read 5, iclass 26, count 2 2006.257.22:09:39.59#ibcon#about to read 6, iclass 26, count 2 2006.257.22:09:39.59#ibcon#read 6, iclass 26, count 2 2006.257.22:09:39.59#ibcon#end of sib2, iclass 26, count 2 2006.257.22:09:39.59#ibcon#*mode == 0, iclass 26, count 2 2006.257.22:09:39.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.22:09:39.59#ibcon#[27=AT05-04\r\n] 2006.257.22:09:39.59#ibcon#*before write, iclass 26, count 2 2006.257.22:09:39.59#ibcon#enter sib2, iclass 26, count 2 2006.257.22:09:39.59#ibcon#flushed, iclass 26, count 2 2006.257.22:09:39.59#ibcon#about to write, iclass 26, count 2 2006.257.22:09:39.59#ibcon#wrote, iclass 26, count 2 2006.257.22:09:39.59#ibcon#about to read 3, iclass 26, count 2 2006.257.22:09:39.62#ibcon#read 3, iclass 26, count 2 2006.257.22:09:39.62#ibcon#about to read 4, iclass 26, count 2 2006.257.22:09:39.62#ibcon#read 4, iclass 26, count 2 2006.257.22:09:39.62#ibcon#about to read 5, iclass 26, count 2 2006.257.22:09:39.62#ibcon#read 5, iclass 26, count 2 2006.257.22:09:39.62#ibcon#about to read 6, iclass 26, count 2 2006.257.22:09:39.62#ibcon#read 6, iclass 26, count 2 2006.257.22:09:39.62#ibcon#end of sib2, iclass 26, count 2 2006.257.22:09:39.62#ibcon#*after write, iclass 26, count 2 2006.257.22:09:39.62#ibcon#*before return 0, iclass 26, count 2 2006.257.22:09:39.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:39.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:09:39.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.22:09:39.62#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:39.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:39.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:39.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:39.74#ibcon#enter wrdev, iclass 26, count 0 2006.257.22:09:39.74#ibcon#first serial, iclass 26, count 0 2006.257.22:09:39.74#ibcon#enter sib2, iclass 26, count 0 2006.257.22:09:39.74#ibcon#flushed, iclass 26, count 0 2006.257.22:09:39.74#ibcon#about to write, iclass 26, count 0 2006.257.22:09:39.74#ibcon#wrote, iclass 26, count 0 2006.257.22:09:39.74#ibcon#about to read 3, iclass 26, count 0 2006.257.22:09:39.76#ibcon#read 3, iclass 26, count 0 2006.257.22:09:39.76#ibcon#about to read 4, iclass 26, count 0 2006.257.22:09:39.76#ibcon#read 4, iclass 26, count 0 2006.257.22:09:39.76#ibcon#about to read 5, iclass 26, count 0 2006.257.22:09:39.76#ibcon#read 5, iclass 26, count 0 2006.257.22:09:39.76#ibcon#about to read 6, iclass 26, count 0 2006.257.22:09:39.76#ibcon#read 6, iclass 26, count 0 2006.257.22:09:39.76#ibcon#end of sib2, iclass 26, count 0 2006.257.22:09:39.76#ibcon#*mode == 0, iclass 26, count 0 2006.257.22:09:39.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.22:09:39.76#ibcon#[27=USB\r\n] 2006.257.22:09:39.76#ibcon#*before write, iclass 26, count 0 2006.257.22:09:39.76#ibcon#enter sib2, iclass 26, count 0 2006.257.22:09:39.76#ibcon#flushed, iclass 26, count 0 2006.257.22:09:39.76#ibcon#about to write, iclass 26, count 0 2006.257.22:09:39.76#ibcon#wrote, iclass 26, count 0 2006.257.22:09:39.76#ibcon#about to read 3, iclass 26, count 0 2006.257.22:09:39.79#ibcon#read 3, iclass 26, count 0 2006.257.22:09:39.79#ibcon#about to read 4, iclass 26, count 0 2006.257.22:09:39.79#ibcon#read 4, iclass 26, count 0 2006.257.22:09:39.79#ibcon#about to read 5, iclass 26, count 0 2006.257.22:09:39.79#ibcon#read 5, iclass 26, count 0 2006.257.22:09:39.79#ibcon#about to read 6, iclass 26, count 0 2006.257.22:09:39.79#ibcon#read 6, iclass 26, count 0 2006.257.22:09:39.79#ibcon#end of sib2, iclass 26, count 0 2006.257.22:09:39.79#ibcon#*after write, iclass 26, count 0 2006.257.22:09:39.79#ibcon#*before return 0, iclass 26, count 0 2006.257.22:09:39.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:39.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:09:39.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.22:09:39.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.22:09:39.79$vck44/vblo=6,719.99 2006.257.22:09:39.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.22:09:39.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.22:09:39.79#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:39.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:39.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:39.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:39.79#ibcon#enter wrdev, iclass 28, count 0 2006.257.22:09:39.79#ibcon#first serial, iclass 28, count 0 2006.257.22:09:39.79#ibcon#enter sib2, iclass 28, count 0 2006.257.22:09:39.79#ibcon#flushed, iclass 28, count 0 2006.257.22:09:39.79#ibcon#about to write, iclass 28, count 0 2006.257.22:09:39.79#ibcon#wrote, iclass 28, count 0 2006.257.22:09:39.79#ibcon#about to read 3, iclass 28, count 0 2006.257.22:09:39.81#ibcon#read 3, iclass 28, count 0 2006.257.22:09:39.81#ibcon#about to read 4, iclass 28, count 0 2006.257.22:09:39.81#ibcon#read 4, iclass 28, count 0 2006.257.22:09:39.81#ibcon#about to read 5, iclass 28, count 0 2006.257.22:09:39.81#ibcon#read 5, iclass 28, count 0 2006.257.22:09:39.81#ibcon#about to read 6, iclass 28, count 0 2006.257.22:09:39.81#ibcon#read 6, iclass 28, count 0 2006.257.22:09:39.81#ibcon#end of sib2, iclass 28, count 0 2006.257.22:09:39.81#ibcon#*mode == 0, iclass 28, count 0 2006.257.22:09:39.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.22:09:39.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.22:09:39.81#ibcon#*before write, iclass 28, count 0 2006.257.22:09:39.81#ibcon#enter sib2, iclass 28, count 0 2006.257.22:09:39.81#ibcon#flushed, iclass 28, count 0 2006.257.22:09:39.81#ibcon#about to write, iclass 28, count 0 2006.257.22:09:39.81#ibcon#wrote, iclass 28, count 0 2006.257.22:09:39.81#ibcon#about to read 3, iclass 28, count 0 2006.257.22:09:39.85#ibcon#read 3, iclass 28, count 0 2006.257.22:09:39.85#ibcon#about to read 4, iclass 28, count 0 2006.257.22:09:39.85#ibcon#read 4, iclass 28, count 0 2006.257.22:09:39.85#ibcon#about to read 5, iclass 28, count 0 2006.257.22:09:39.85#ibcon#read 5, iclass 28, count 0 2006.257.22:09:39.85#ibcon#about to read 6, iclass 28, count 0 2006.257.22:09:39.85#ibcon#read 6, iclass 28, count 0 2006.257.22:09:39.85#ibcon#end of sib2, iclass 28, count 0 2006.257.22:09:39.85#ibcon#*after write, iclass 28, count 0 2006.257.22:09:39.85#ibcon#*before return 0, iclass 28, count 0 2006.257.22:09:39.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:39.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:09:39.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.22:09:39.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.22:09:39.85$vck44/vb=6,4 2006.257.22:09:39.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.22:09:39.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.22:09:39.85#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:39.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:39.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:39.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:39.91#ibcon#enter wrdev, iclass 30, count 2 2006.257.22:09:39.91#ibcon#first serial, iclass 30, count 2 2006.257.22:09:39.91#ibcon#enter sib2, iclass 30, count 2 2006.257.22:09:39.91#ibcon#flushed, iclass 30, count 2 2006.257.22:09:39.91#ibcon#about to write, iclass 30, count 2 2006.257.22:09:39.91#ibcon#wrote, iclass 30, count 2 2006.257.22:09:39.91#ibcon#about to read 3, iclass 30, count 2 2006.257.22:09:39.93#ibcon#read 3, iclass 30, count 2 2006.257.22:09:39.93#ibcon#about to read 4, iclass 30, count 2 2006.257.22:09:39.93#ibcon#read 4, iclass 30, count 2 2006.257.22:09:39.93#ibcon#about to read 5, iclass 30, count 2 2006.257.22:09:39.93#ibcon#read 5, iclass 30, count 2 2006.257.22:09:39.93#ibcon#about to read 6, iclass 30, count 2 2006.257.22:09:39.93#ibcon#read 6, iclass 30, count 2 2006.257.22:09:39.93#ibcon#end of sib2, iclass 30, count 2 2006.257.22:09:39.93#ibcon#*mode == 0, iclass 30, count 2 2006.257.22:09:39.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.22:09:39.93#ibcon#[27=AT06-04\r\n] 2006.257.22:09:39.93#ibcon#*before write, iclass 30, count 2 2006.257.22:09:39.93#ibcon#enter sib2, iclass 30, count 2 2006.257.22:09:39.93#ibcon#flushed, iclass 30, count 2 2006.257.22:09:39.93#ibcon#about to write, iclass 30, count 2 2006.257.22:09:39.93#ibcon#wrote, iclass 30, count 2 2006.257.22:09:39.93#ibcon#about to read 3, iclass 30, count 2 2006.257.22:09:39.96#ibcon#read 3, iclass 30, count 2 2006.257.22:09:39.96#ibcon#about to read 4, iclass 30, count 2 2006.257.22:09:39.96#ibcon#read 4, iclass 30, count 2 2006.257.22:09:39.96#ibcon#about to read 5, iclass 30, count 2 2006.257.22:09:39.96#ibcon#read 5, iclass 30, count 2 2006.257.22:09:39.96#ibcon#about to read 6, iclass 30, count 2 2006.257.22:09:39.96#ibcon#read 6, iclass 30, count 2 2006.257.22:09:39.96#ibcon#end of sib2, iclass 30, count 2 2006.257.22:09:39.96#ibcon#*after write, iclass 30, count 2 2006.257.22:09:39.96#ibcon#*before return 0, iclass 30, count 2 2006.257.22:09:39.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:39.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:09:39.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.22:09:39.96#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:39.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:40.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:40.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:40.08#ibcon#enter wrdev, iclass 30, count 0 2006.257.22:09:40.08#ibcon#first serial, iclass 30, count 0 2006.257.22:09:40.08#ibcon#enter sib2, iclass 30, count 0 2006.257.22:09:40.08#ibcon#flushed, iclass 30, count 0 2006.257.22:09:40.08#ibcon#about to write, iclass 30, count 0 2006.257.22:09:40.08#ibcon#wrote, iclass 30, count 0 2006.257.22:09:40.08#ibcon#about to read 3, iclass 30, count 0 2006.257.22:09:40.10#ibcon#read 3, iclass 30, count 0 2006.257.22:09:40.10#ibcon#about to read 4, iclass 30, count 0 2006.257.22:09:40.10#ibcon#read 4, iclass 30, count 0 2006.257.22:09:40.10#ibcon#about to read 5, iclass 30, count 0 2006.257.22:09:40.10#ibcon#read 5, iclass 30, count 0 2006.257.22:09:40.10#ibcon#about to read 6, iclass 30, count 0 2006.257.22:09:40.10#ibcon#read 6, iclass 30, count 0 2006.257.22:09:40.10#ibcon#end of sib2, iclass 30, count 0 2006.257.22:09:40.10#ibcon#*mode == 0, iclass 30, count 0 2006.257.22:09:40.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.22:09:40.10#ibcon#[27=USB\r\n] 2006.257.22:09:40.10#ibcon#*before write, iclass 30, count 0 2006.257.22:09:40.10#ibcon#enter sib2, iclass 30, count 0 2006.257.22:09:40.10#ibcon#flushed, iclass 30, count 0 2006.257.22:09:40.10#ibcon#about to write, iclass 30, count 0 2006.257.22:09:40.10#ibcon#wrote, iclass 30, count 0 2006.257.22:09:40.10#ibcon#about to read 3, iclass 30, count 0 2006.257.22:09:40.13#ibcon#read 3, iclass 30, count 0 2006.257.22:09:40.13#ibcon#about to read 4, iclass 30, count 0 2006.257.22:09:40.13#ibcon#read 4, iclass 30, count 0 2006.257.22:09:40.13#ibcon#about to read 5, iclass 30, count 0 2006.257.22:09:40.13#ibcon#read 5, iclass 30, count 0 2006.257.22:09:40.13#ibcon#about to read 6, iclass 30, count 0 2006.257.22:09:40.13#ibcon#read 6, iclass 30, count 0 2006.257.22:09:40.13#ibcon#end of sib2, iclass 30, count 0 2006.257.22:09:40.13#ibcon#*after write, iclass 30, count 0 2006.257.22:09:40.13#ibcon#*before return 0, iclass 30, count 0 2006.257.22:09:40.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:40.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:09:40.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.22:09:40.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.22:09:40.13$vck44/vblo=7,734.99 2006.257.22:09:40.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.22:09:40.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.22:09:40.13#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:40.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:40.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:40.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:40.13#ibcon#enter wrdev, iclass 32, count 0 2006.257.22:09:40.13#ibcon#first serial, iclass 32, count 0 2006.257.22:09:40.13#ibcon#enter sib2, iclass 32, count 0 2006.257.22:09:40.13#ibcon#flushed, iclass 32, count 0 2006.257.22:09:40.13#ibcon#about to write, iclass 32, count 0 2006.257.22:09:40.13#ibcon#wrote, iclass 32, count 0 2006.257.22:09:40.13#ibcon#about to read 3, iclass 32, count 0 2006.257.22:09:40.15#ibcon#read 3, iclass 32, count 0 2006.257.22:09:40.15#ibcon#about to read 4, iclass 32, count 0 2006.257.22:09:40.15#ibcon#read 4, iclass 32, count 0 2006.257.22:09:40.15#ibcon#about to read 5, iclass 32, count 0 2006.257.22:09:40.15#ibcon#read 5, iclass 32, count 0 2006.257.22:09:40.15#ibcon#about to read 6, iclass 32, count 0 2006.257.22:09:40.15#ibcon#read 6, iclass 32, count 0 2006.257.22:09:40.15#ibcon#end of sib2, iclass 32, count 0 2006.257.22:09:40.15#ibcon#*mode == 0, iclass 32, count 0 2006.257.22:09:40.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.22:09:40.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.22:09:40.15#ibcon#*before write, iclass 32, count 0 2006.257.22:09:40.15#ibcon#enter sib2, iclass 32, count 0 2006.257.22:09:40.15#ibcon#flushed, iclass 32, count 0 2006.257.22:09:40.15#ibcon#about to write, iclass 32, count 0 2006.257.22:09:40.15#ibcon#wrote, iclass 32, count 0 2006.257.22:09:40.15#ibcon#about to read 3, iclass 32, count 0 2006.257.22:09:40.19#ibcon#read 3, iclass 32, count 0 2006.257.22:09:40.19#ibcon#about to read 4, iclass 32, count 0 2006.257.22:09:40.19#ibcon#read 4, iclass 32, count 0 2006.257.22:09:40.19#ibcon#about to read 5, iclass 32, count 0 2006.257.22:09:40.19#ibcon#read 5, iclass 32, count 0 2006.257.22:09:40.19#ibcon#about to read 6, iclass 32, count 0 2006.257.22:09:40.19#ibcon#read 6, iclass 32, count 0 2006.257.22:09:40.19#ibcon#end of sib2, iclass 32, count 0 2006.257.22:09:40.19#ibcon#*after write, iclass 32, count 0 2006.257.22:09:40.19#ibcon#*before return 0, iclass 32, count 0 2006.257.22:09:40.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:40.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:09:40.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.22:09:40.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.22:09:40.19$vck44/vb=7,4 2006.257.22:09:40.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.22:09:40.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.22:09:40.19#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:40.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:40.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:40.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:40.25#ibcon#enter wrdev, iclass 34, count 2 2006.257.22:09:40.25#ibcon#first serial, iclass 34, count 2 2006.257.22:09:40.25#ibcon#enter sib2, iclass 34, count 2 2006.257.22:09:40.25#ibcon#flushed, iclass 34, count 2 2006.257.22:09:40.25#ibcon#about to write, iclass 34, count 2 2006.257.22:09:40.25#ibcon#wrote, iclass 34, count 2 2006.257.22:09:40.25#ibcon#about to read 3, iclass 34, count 2 2006.257.22:09:40.27#ibcon#read 3, iclass 34, count 2 2006.257.22:09:40.27#ibcon#about to read 4, iclass 34, count 2 2006.257.22:09:40.27#ibcon#read 4, iclass 34, count 2 2006.257.22:09:40.27#ibcon#about to read 5, iclass 34, count 2 2006.257.22:09:40.27#ibcon#read 5, iclass 34, count 2 2006.257.22:09:40.27#ibcon#about to read 6, iclass 34, count 2 2006.257.22:09:40.27#ibcon#read 6, iclass 34, count 2 2006.257.22:09:40.27#ibcon#end of sib2, iclass 34, count 2 2006.257.22:09:40.27#ibcon#*mode == 0, iclass 34, count 2 2006.257.22:09:40.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.22:09:40.27#ibcon#[27=AT07-04\r\n] 2006.257.22:09:40.27#ibcon#*before write, iclass 34, count 2 2006.257.22:09:40.27#ibcon#enter sib2, iclass 34, count 2 2006.257.22:09:40.27#ibcon#flushed, iclass 34, count 2 2006.257.22:09:40.27#ibcon#about to write, iclass 34, count 2 2006.257.22:09:40.27#ibcon#wrote, iclass 34, count 2 2006.257.22:09:40.27#ibcon#about to read 3, iclass 34, count 2 2006.257.22:09:40.30#ibcon#read 3, iclass 34, count 2 2006.257.22:09:40.30#ibcon#about to read 4, iclass 34, count 2 2006.257.22:09:40.30#ibcon#read 4, iclass 34, count 2 2006.257.22:09:40.30#ibcon#about to read 5, iclass 34, count 2 2006.257.22:09:40.30#ibcon#read 5, iclass 34, count 2 2006.257.22:09:40.30#ibcon#about to read 6, iclass 34, count 2 2006.257.22:09:40.30#ibcon#read 6, iclass 34, count 2 2006.257.22:09:40.30#ibcon#end of sib2, iclass 34, count 2 2006.257.22:09:40.30#ibcon#*after write, iclass 34, count 2 2006.257.22:09:40.30#ibcon#*before return 0, iclass 34, count 2 2006.257.22:09:40.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:40.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:09:40.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.22:09:40.30#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:40.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:40.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:40.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:40.42#ibcon#enter wrdev, iclass 34, count 0 2006.257.22:09:40.42#ibcon#first serial, iclass 34, count 0 2006.257.22:09:40.42#ibcon#enter sib2, iclass 34, count 0 2006.257.22:09:40.42#ibcon#flushed, iclass 34, count 0 2006.257.22:09:40.42#ibcon#about to write, iclass 34, count 0 2006.257.22:09:40.42#ibcon#wrote, iclass 34, count 0 2006.257.22:09:40.42#ibcon#about to read 3, iclass 34, count 0 2006.257.22:09:40.44#ibcon#read 3, iclass 34, count 0 2006.257.22:09:40.44#ibcon#about to read 4, iclass 34, count 0 2006.257.22:09:40.44#ibcon#read 4, iclass 34, count 0 2006.257.22:09:40.44#ibcon#about to read 5, iclass 34, count 0 2006.257.22:09:40.44#ibcon#read 5, iclass 34, count 0 2006.257.22:09:40.44#ibcon#about to read 6, iclass 34, count 0 2006.257.22:09:40.44#ibcon#read 6, iclass 34, count 0 2006.257.22:09:40.44#ibcon#end of sib2, iclass 34, count 0 2006.257.22:09:40.44#ibcon#*mode == 0, iclass 34, count 0 2006.257.22:09:40.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.22:09:40.44#ibcon#[27=USB\r\n] 2006.257.22:09:40.44#ibcon#*before write, iclass 34, count 0 2006.257.22:09:40.44#ibcon#enter sib2, iclass 34, count 0 2006.257.22:09:40.44#ibcon#flushed, iclass 34, count 0 2006.257.22:09:40.44#ibcon#about to write, iclass 34, count 0 2006.257.22:09:40.44#ibcon#wrote, iclass 34, count 0 2006.257.22:09:40.44#ibcon#about to read 3, iclass 34, count 0 2006.257.22:09:40.47#ibcon#read 3, iclass 34, count 0 2006.257.22:09:40.47#ibcon#about to read 4, iclass 34, count 0 2006.257.22:09:40.47#ibcon#read 4, iclass 34, count 0 2006.257.22:09:40.47#ibcon#about to read 5, iclass 34, count 0 2006.257.22:09:40.47#ibcon#read 5, iclass 34, count 0 2006.257.22:09:40.47#ibcon#about to read 6, iclass 34, count 0 2006.257.22:09:40.47#ibcon#read 6, iclass 34, count 0 2006.257.22:09:40.47#ibcon#end of sib2, iclass 34, count 0 2006.257.22:09:40.47#ibcon#*after write, iclass 34, count 0 2006.257.22:09:40.47#ibcon#*before return 0, iclass 34, count 0 2006.257.22:09:40.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:40.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:09:40.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.22:09:40.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.22:09:40.47$vck44/vblo=8,744.99 2006.257.22:09:40.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.22:09:40.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.22:09:40.47#ibcon#ireg 17 cls_cnt 0 2006.257.22:09:40.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:40.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:40.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:40.47#ibcon#enter wrdev, iclass 36, count 0 2006.257.22:09:40.47#ibcon#first serial, iclass 36, count 0 2006.257.22:09:40.47#ibcon#enter sib2, iclass 36, count 0 2006.257.22:09:40.47#ibcon#flushed, iclass 36, count 0 2006.257.22:09:40.47#ibcon#about to write, iclass 36, count 0 2006.257.22:09:40.47#ibcon#wrote, iclass 36, count 0 2006.257.22:09:40.47#ibcon#about to read 3, iclass 36, count 0 2006.257.22:09:40.49#ibcon#read 3, iclass 36, count 0 2006.257.22:09:40.49#ibcon#about to read 4, iclass 36, count 0 2006.257.22:09:40.49#ibcon#read 4, iclass 36, count 0 2006.257.22:09:40.49#ibcon#about to read 5, iclass 36, count 0 2006.257.22:09:40.49#ibcon#read 5, iclass 36, count 0 2006.257.22:09:40.49#ibcon#about to read 6, iclass 36, count 0 2006.257.22:09:40.49#ibcon#read 6, iclass 36, count 0 2006.257.22:09:40.49#ibcon#end of sib2, iclass 36, count 0 2006.257.22:09:40.49#ibcon#*mode == 0, iclass 36, count 0 2006.257.22:09:40.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.22:09:40.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.22:09:40.49#ibcon#*before write, iclass 36, count 0 2006.257.22:09:40.49#ibcon#enter sib2, iclass 36, count 0 2006.257.22:09:40.49#ibcon#flushed, iclass 36, count 0 2006.257.22:09:40.49#ibcon#about to write, iclass 36, count 0 2006.257.22:09:40.49#ibcon#wrote, iclass 36, count 0 2006.257.22:09:40.49#ibcon#about to read 3, iclass 36, count 0 2006.257.22:09:40.53#ibcon#read 3, iclass 36, count 0 2006.257.22:09:40.53#ibcon#about to read 4, iclass 36, count 0 2006.257.22:09:40.53#ibcon#read 4, iclass 36, count 0 2006.257.22:09:40.53#ibcon#about to read 5, iclass 36, count 0 2006.257.22:09:40.53#ibcon#read 5, iclass 36, count 0 2006.257.22:09:40.53#ibcon#about to read 6, iclass 36, count 0 2006.257.22:09:40.53#ibcon#read 6, iclass 36, count 0 2006.257.22:09:40.53#ibcon#end of sib2, iclass 36, count 0 2006.257.22:09:40.53#ibcon#*after write, iclass 36, count 0 2006.257.22:09:40.53#ibcon#*before return 0, iclass 36, count 0 2006.257.22:09:40.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:40.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:09:40.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.22:09:40.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.22:09:40.53$vck44/vb=8,4 2006.257.22:09:40.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.22:09:40.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.22:09:40.53#ibcon#ireg 11 cls_cnt 2 2006.257.22:09:40.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:40.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:40.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:40.59#ibcon#enter wrdev, iclass 38, count 2 2006.257.22:09:40.59#ibcon#first serial, iclass 38, count 2 2006.257.22:09:40.59#ibcon#enter sib2, iclass 38, count 2 2006.257.22:09:40.59#ibcon#flushed, iclass 38, count 2 2006.257.22:09:40.59#ibcon#about to write, iclass 38, count 2 2006.257.22:09:40.59#ibcon#wrote, iclass 38, count 2 2006.257.22:09:40.59#ibcon#about to read 3, iclass 38, count 2 2006.257.22:09:40.61#ibcon#read 3, iclass 38, count 2 2006.257.22:09:40.61#ibcon#about to read 4, iclass 38, count 2 2006.257.22:09:40.61#ibcon#read 4, iclass 38, count 2 2006.257.22:09:40.61#ibcon#about to read 5, iclass 38, count 2 2006.257.22:09:40.61#ibcon#read 5, iclass 38, count 2 2006.257.22:09:40.61#ibcon#about to read 6, iclass 38, count 2 2006.257.22:09:40.61#ibcon#read 6, iclass 38, count 2 2006.257.22:09:40.61#ibcon#end of sib2, iclass 38, count 2 2006.257.22:09:40.61#ibcon#*mode == 0, iclass 38, count 2 2006.257.22:09:40.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.22:09:40.61#ibcon#[27=AT08-04\r\n] 2006.257.22:09:40.61#ibcon#*before write, iclass 38, count 2 2006.257.22:09:40.61#ibcon#enter sib2, iclass 38, count 2 2006.257.22:09:40.61#ibcon#flushed, iclass 38, count 2 2006.257.22:09:40.61#ibcon#about to write, iclass 38, count 2 2006.257.22:09:40.61#ibcon#wrote, iclass 38, count 2 2006.257.22:09:40.61#ibcon#about to read 3, iclass 38, count 2 2006.257.22:09:40.64#ibcon#read 3, iclass 38, count 2 2006.257.22:09:40.64#ibcon#about to read 4, iclass 38, count 2 2006.257.22:09:40.64#ibcon#read 4, iclass 38, count 2 2006.257.22:09:40.64#ibcon#about to read 5, iclass 38, count 2 2006.257.22:09:40.64#ibcon#read 5, iclass 38, count 2 2006.257.22:09:40.64#ibcon#about to read 6, iclass 38, count 2 2006.257.22:09:40.64#ibcon#read 6, iclass 38, count 2 2006.257.22:09:40.64#ibcon#end of sib2, iclass 38, count 2 2006.257.22:09:40.64#ibcon#*after write, iclass 38, count 2 2006.257.22:09:40.64#ibcon#*before return 0, iclass 38, count 2 2006.257.22:09:40.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:40.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:09:40.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.22:09:40.64#ibcon#ireg 7 cls_cnt 0 2006.257.22:09:40.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:40.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:40.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:40.76#ibcon#enter wrdev, iclass 38, count 0 2006.257.22:09:40.76#ibcon#first serial, iclass 38, count 0 2006.257.22:09:40.76#ibcon#enter sib2, iclass 38, count 0 2006.257.22:09:40.76#ibcon#flushed, iclass 38, count 0 2006.257.22:09:40.76#ibcon#about to write, iclass 38, count 0 2006.257.22:09:40.76#ibcon#wrote, iclass 38, count 0 2006.257.22:09:40.76#ibcon#about to read 3, iclass 38, count 0 2006.257.22:09:40.78#ibcon#read 3, iclass 38, count 0 2006.257.22:09:40.78#ibcon#about to read 4, iclass 38, count 0 2006.257.22:09:40.78#ibcon#read 4, iclass 38, count 0 2006.257.22:09:40.78#ibcon#about to read 5, iclass 38, count 0 2006.257.22:09:40.78#ibcon#read 5, iclass 38, count 0 2006.257.22:09:40.78#ibcon#about to read 6, iclass 38, count 0 2006.257.22:09:40.78#ibcon#read 6, iclass 38, count 0 2006.257.22:09:40.78#ibcon#end of sib2, iclass 38, count 0 2006.257.22:09:40.78#ibcon#*mode == 0, iclass 38, count 0 2006.257.22:09:40.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.22:09:40.78#ibcon#[27=USB\r\n] 2006.257.22:09:40.78#ibcon#*before write, iclass 38, count 0 2006.257.22:09:40.78#ibcon#enter sib2, iclass 38, count 0 2006.257.22:09:40.78#ibcon#flushed, iclass 38, count 0 2006.257.22:09:40.78#ibcon#about to write, iclass 38, count 0 2006.257.22:09:40.78#ibcon#wrote, iclass 38, count 0 2006.257.22:09:40.78#ibcon#about to read 3, iclass 38, count 0 2006.257.22:09:40.81#ibcon#read 3, iclass 38, count 0 2006.257.22:09:40.81#ibcon#about to read 4, iclass 38, count 0 2006.257.22:09:40.81#ibcon#read 4, iclass 38, count 0 2006.257.22:09:40.81#ibcon#about to read 5, iclass 38, count 0 2006.257.22:09:40.81#ibcon#read 5, iclass 38, count 0 2006.257.22:09:40.81#ibcon#about to read 6, iclass 38, count 0 2006.257.22:09:40.81#ibcon#read 6, iclass 38, count 0 2006.257.22:09:40.81#ibcon#end of sib2, iclass 38, count 0 2006.257.22:09:40.81#ibcon#*after write, iclass 38, count 0 2006.257.22:09:40.81#ibcon#*before return 0, iclass 38, count 0 2006.257.22:09:40.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:40.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:09:40.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.22:09:40.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.22:09:40.81$vck44/vabw=wide 2006.257.22:09:40.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.22:09:40.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.22:09:40.81#ibcon#ireg 8 cls_cnt 0 2006.257.22:09:40.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:40.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:40.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:40.81#ibcon#enter wrdev, iclass 40, count 0 2006.257.22:09:40.81#ibcon#first serial, iclass 40, count 0 2006.257.22:09:40.81#ibcon#enter sib2, iclass 40, count 0 2006.257.22:09:40.81#ibcon#flushed, iclass 40, count 0 2006.257.22:09:40.81#ibcon#about to write, iclass 40, count 0 2006.257.22:09:40.81#ibcon#wrote, iclass 40, count 0 2006.257.22:09:40.81#ibcon#about to read 3, iclass 40, count 0 2006.257.22:09:40.83#ibcon#read 3, iclass 40, count 0 2006.257.22:09:40.83#ibcon#about to read 4, iclass 40, count 0 2006.257.22:09:40.83#ibcon#read 4, iclass 40, count 0 2006.257.22:09:40.83#ibcon#about to read 5, iclass 40, count 0 2006.257.22:09:40.83#ibcon#read 5, iclass 40, count 0 2006.257.22:09:40.83#ibcon#about to read 6, iclass 40, count 0 2006.257.22:09:40.83#ibcon#read 6, iclass 40, count 0 2006.257.22:09:40.83#ibcon#end of sib2, iclass 40, count 0 2006.257.22:09:40.83#ibcon#*mode == 0, iclass 40, count 0 2006.257.22:09:40.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.22:09:40.83#ibcon#[25=BW32\r\n] 2006.257.22:09:40.83#ibcon#*before write, iclass 40, count 0 2006.257.22:09:40.83#ibcon#enter sib2, iclass 40, count 0 2006.257.22:09:40.83#ibcon#flushed, iclass 40, count 0 2006.257.22:09:40.83#ibcon#about to write, iclass 40, count 0 2006.257.22:09:40.83#ibcon#wrote, iclass 40, count 0 2006.257.22:09:40.83#ibcon#about to read 3, iclass 40, count 0 2006.257.22:09:40.86#ibcon#read 3, iclass 40, count 0 2006.257.22:09:40.86#ibcon#about to read 4, iclass 40, count 0 2006.257.22:09:40.86#ibcon#read 4, iclass 40, count 0 2006.257.22:09:40.86#ibcon#about to read 5, iclass 40, count 0 2006.257.22:09:40.86#ibcon#read 5, iclass 40, count 0 2006.257.22:09:40.86#ibcon#about to read 6, iclass 40, count 0 2006.257.22:09:40.86#ibcon#read 6, iclass 40, count 0 2006.257.22:09:40.86#ibcon#end of sib2, iclass 40, count 0 2006.257.22:09:40.86#ibcon#*after write, iclass 40, count 0 2006.257.22:09:40.86#ibcon#*before return 0, iclass 40, count 0 2006.257.22:09:40.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:40.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:09:40.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.22:09:40.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.22:09:40.86$vck44/vbbw=wide 2006.257.22:09:40.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.22:09:40.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.22:09:40.86#ibcon#ireg 8 cls_cnt 0 2006.257.22:09:40.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:09:40.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:09:40.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:09:40.93#ibcon#enter wrdev, iclass 4, count 0 2006.257.22:09:40.93#ibcon#first serial, iclass 4, count 0 2006.257.22:09:40.93#ibcon#enter sib2, iclass 4, count 0 2006.257.22:09:40.93#ibcon#flushed, iclass 4, count 0 2006.257.22:09:40.93#ibcon#about to write, iclass 4, count 0 2006.257.22:09:40.93#ibcon#wrote, iclass 4, count 0 2006.257.22:09:40.93#ibcon#about to read 3, iclass 4, count 0 2006.257.22:09:40.95#ibcon#read 3, iclass 4, count 0 2006.257.22:09:40.95#ibcon#about to read 4, iclass 4, count 0 2006.257.22:09:40.95#ibcon#read 4, iclass 4, count 0 2006.257.22:09:40.95#ibcon#about to read 5, iclass 4, count 0 2006.257.22:09:40.95#ibcon#read 5, iclass 4, count 0 2006.257.22:09:40.95#ibcon#about to read 6, iclass 4, count 0 2006.257.22:09:40.95#ibcon#read 6, iclass 4, count 0 2006.257.22:09:40.95#ibcon#end of sib2, iclass 4, count 0 2006.257.22:09:40.95#ibcon#*mode == 0, iclass 4, count 0 2006.257.22:09:40.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.22:09:40.95#ibcon#[27=BW32\r\n] 2006.257.22:09:40.95#ibcon#*before write, iclass 4, count 0 2006.257.22:09:40.95#ibcon#enter sib2, iclass 4, count 0 2006.257.22:09:40.95#ibcon#flushed, iclass 4, count 0 2006.257.22:09:40.95#ibcon#about to write, iclass 4, count 0 2006.257.22:09:40.95#ibcon#wrote, iclass 4, count 0 2006.257.22:09:40.95#ibcon#about to read 3, iclass 4, count 0 2006.257.22:09:40.98#ibcon#read 3, iclass 4, count 0 2006.257.22:09:40.98#ibcon#about to read 4, iclass 4, count 0 2006.257.22:09:40.98#ibcon#read 4, iclass 4, count 0 2006.257.22:09:40.98#ibcon#about to read 5, iclass 4, count 0 2006.257.22:09:40.98#ibcon#read 5, iclass 4, count 0 2006.257.22:09:40.98#ibcon#about to read 6, iclass 4, count 0 2006.257.22:09:40.98#ibcon#read 6, iclass 4, count 0 2006.257.22:09:40.98#ibcon#end of sib2, iclass 4, count 0 2006.257.22:09:40.98#ibcon#*after write, iclass 4, count 0 2006.257.22:09:40.98#ibcon#*before return 0, iclass 4, count 0 2006.257.22:09:40.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:09:40.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:09:40.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.22:09:40.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.22:09:40.98$setupk4/ifdk4 2006.257.22:09:40.98$ifdk4/lo= 2006.257.22:09:40.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.22:09:40.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.22:09:40.98$ifdk4/patch= 2006.257.22:09:40.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.22:09:40.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.22:09:40.98$setupk4/!*+20s 2006.257.22:09:41.15#abcon#<5=/14 0.7 1.9 18.97 891015.7\r\n> 2006.257.22:09:41.17#abcon#{5=INTERFACE CLEAR} 2006.257.22:09:41.23#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:09:51.32#abcon#<5=/14 0.7 1.9 18.97 891015.8\r\n> 2006.257.22:09:51.34#abcon#{5=INTERFACE CLEAR} 2006.257.22:09:51.40#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:09:55.48$setupk4/"tpicd 2006.257.22:09:55.48$setupk4/echo=off 2006.257.22:09:55.48$setupk4/xlog=off 2006.257.22:09:55.48:!2006.257.22:14:03 2006.257.22:10:04.14#trakl#Source acquired 2006.257.22:10:05.14#flagr#flagr/antenna,acquired 2006.257.22:14:03.00:preob 2006.257.22:14:03.14/onsource/TRACKING 2006.257.22:14:03.14:!2006.257.22:14:13 2006.257.22:14:13.00:"tape 2006.257.22:14:13.00:"st=record 2006.257.22:14:13.00:data_valid=on 2006.257.22:14:13.00:midob 2006.257.22:14:14.14/onsource/TRACKING 2006.257.22:14:14.14/wx/19.02,1015.8,89 2006.257.22:14:14.32/cable/+6.4838E-03 2006.257.22:14:15.41/va/01,08,usb,yes,31,33 2006.257.22:14:15.41/va/02,07,usb,yes,33,34 2006.257.22:14:15.41/va/03,08,usb,yes,30,31 2006.257.22:14:15.41/va/04,07,usb,yes,34,36 2006.257.22:14:15.41/va/05,04,usb,yes,31,31 2006.257.22:14:15.41/va/06,04,usb,yes,34,34 2006.257.22:14:15.41/va/07,04,usb,yes,35,35 2006.257.22:14:15.41/va/08,04,usb,yes,29,36 2006.257.22:14:15.64/valo/01,524.99,yes,locked 2006.257.22:14:15.64/valo/02,534.99,yes,locked 2006.257.22:14:15.64/valo/03,564.99,yes,locked 2006.257.22:14:15.64/valo/04,624.99,yes,locked 2006.257.22:14:15.64/valo/05,734.99,yes,locked 2006.257.22:14:15.64/valo/06,814.99,yes,locked 2006.257.22:14:15.64/valo/07,864.99,yes,locked 2006.257.22:14:15.64/valo/08,884.99,yes,locked 2006.257.22:14:16.73/vb/01,04,usb,yes,30,28 2006.257.22:14:16.73/vb/02,05,usb,yes,28,28 2006.257.22:14:16.73/vb/03,04,usb,yes,29,32 2006.257.22:14:16.73/vb/04,05,usb,yes,30,29 2006.257.22:14:16.73/vb/05,04,usb,yes,26,28 2006.257.22:14:16.73/vb/06,04,usb,yes,30,27 2006.257.22:14:16.73/vb/07,04,usb,yes,30,30 2006.257.22:14:16.73/vb/08,04,usb,yes,28,31 2006.257.22:14:16.96/vblo/01,629.99,yes,locked 2006.257.22:14:16.96/vblo/02,634.99,yes,locked 2006.257.22:14:16.96/vblo/03,649.99,yes,locked 2006.257.22:14:16.96/vblo/04,679.99,yes,locked 2006.257.22:14:16.96/vblo/05,709.99,yes,locked 2006.257.22:14:16.96/vblo/06,719.99,yes,locked 2006.257.22:14:16.96/vblo/07,734.99,yes,locked 2006.257.22:14:16.96/vblo/08,744.99,yes,locked 2006.257.22:14:17.11/vabw/8 2006.257.22:14:17.26/vbbw/8 2006.257.22:14:17.35/xfe/off,on,15.2 2006.257.22:14:17.75/ifatt/23,28,28,28 2006.257.22:14:18.08/fmout-gps/S +4.49E-07 2006.257.22:14:18.11:!2006.257.22:15:53 2006.257.22:15:53.02:data_valid=off 2006.257.22:15:53.02:"et 2006.257.22:15:53.02:!+3s 2006.257.22:15:56.04:"tape 2006.257.22:15:56.05:postob 2006.257.22:15:56.24/cable/+6.4863E-03 2006.257.22:15:56.25/wx/19.06,1015.8,88 2006.257.22:15:56.30/fmout-gps/S +4.49E-07 2006.257.22:15:56.31:scan_name=257-2217,jd0609,60 2006.257.22:15:56.31:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.257.22:15:58.14#flagr#flagr/antenna,new-source 2006.257.22:15:58.14:checkk5 2006.257.22:15:58.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.22:15:58.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.22:15:59.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.22:15:59.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.22:15:59.85/chk_obsdata//k5ts1/T2572214??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.22:16:00.18/chk_obsdata//k5ts2/T2572214??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.22:16:00.52/chk_obsdata//k5ts3/T2572214??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.22:16:00.85/chk_obsdata//k5ts4/T2572214??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.22:16:01.50/k5log//k5ts1_log_newline 2006.257.22:16:02.16/k5log//k5ts2_log_newline 2006.257.22:16:02.81/k5log//k5ts3_log_newline 2006.257.22:16:03.47/k5log//k5ts4_log_newline 2006.257.22:16:03.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.22:16:03.49:setupk4=1 2006.257.22:16:03.49$setupk4/echo=on 2006.257.22:16:03.49$setupk4/pcalon 2006.257.22:16:03.49$pcalon/"no phase cal control is implemented here 2006.257.22:16:03.49$setupk4/"tpicd=stop 2006.257.22:16:03.49$setupk4/"rec=synch_on 2006.257.22:16:03.49$setupk4/"rec_mode=128 2006.257.22:16:03.49$setupk4/!* 2006.257.22:16:03.49$setupk4/recpk4 2006.257.22:16:03.49$recpk4/recpatch= 2006.257.22:16:03.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.22:16:03.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.22:16:03.50$setupk4/vck44 2006.257.22:16:03.50$vck44/valo=1,524.99 2006.257.22:16:03.50#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.22:16:03.50#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.22:16:03.50#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:03.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:03.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:03.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:03.50#ibcon#enter wrdev, iclass 19, count 0 2006.257.22:16:03.50#ibcon#first serial, iclass 19, count 0 2006.257.22:16:03.50#ibcon#enter sib2, iclass 19, count 0 2006.257.22:16:03.50#ibcon#flushed, iclass 19, count 0 2006.257.22:16:03.50#ibcon#about to write, iclass 19, count 0 2006.257.22:16:03.50#ibcon#wrote, iclass 19, count 0 2006.257.22:16:03.50#ibcon#about to read 3, iclass 19, count 0 2006.257.22:16:03.51#ibcon#read 3, iclass 19, count 0 2006.257.22:16:03.51#ibcon#about to read 4, iclass 19, count 0 2006.257.22:16:03.51#ibcon#read 4, iclass 19, count 0 2006.257.22:16:03.51#ibcon#about to read 5, iclass 19, count 0 2006.257.22:16:03.51#ibcon#read 5, iclass 19, count 0 2006.257.22:16:03.51#ibcon#about to read 6, iclass 19, count 0 2006.257.22:16:03.51#ibcon#read 6, iclass 19, count 0 2006.257.22:16:03.51#ibcon#end of sib2, iclass 19, count 0 2006.257.22:16:03.51#ibcon#*mode == 0, iclass 19, count 0 2006.257.22:16:03.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.22:16:03.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.22:16:03.51#ibcon#*before write, iclass 19, count 0 2006.257.22:16:03.51#ibcon#enter sib2, iclass 19, count 0 2006.257.22:16:03.51#ibcon#flushed, iclass 19, count 0 2006.257.22:16:03.51#ibcon#about to write, iclass 19, count 0 2006.257.22:16:03.51#ibcon#wrote, iclass 19, count 0 2006.257.22:16:03.51#ibcon#about to read 3, iclass 19, count 0 2006.257.22:16:03.56#ibcon#read 3, iclass 19, count 0 2006.257.22:16:03.56#ibcon#about to read 4, iclass 19, count 0 2006.257.22:16:03.56#ibcon#read 4, iclass 19, count 0 2006.257.22:16:03.56#ibcon#about to read 5, iclass 19, count 0 2006.257.22:16:03.56#ibcon#read 5, iclass 19, count 0 2006.257.22:16:03.56#ibcon#about to read 6, iclass 19, count 0 2006.257.22:16:03.56#ibcon#read 6, iclass 19, count 0 2006.257.22:16:03.56#ibcon#end of sib2, iclass 19, count 0 2006.257.22:16:03.56#ibcon#*after write, iclass 19, count 0 2006.257.22:16:03.56#ibcon#*before return 0, iclass 19, count 0 2006.257.22:16:03.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:03.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:03.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.22:16:03.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.22:16:03.57$vck44/va=1,8 2006.257.22:16:03.57#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.22:16:03.57#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.22:16:03.57#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:03.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:03.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:03.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:03.57#ibcon#enter wrdev, iclass 21, count 2 2006.257.22:16:03.57#ibcon#first serial, iclass 21, count 2 2006.257.22:16:03.57#ibcon#enter sib2, iclass 21, count 2 2006.257.22:16:03.57#ibcon#flushed, iclass 21, count 2 2006.257.22:16:03.57#ibcon#about to write, iclass 21, count 2 2006.257.22:16:03.57#ibcon#wrote, iclass 21, count 2 2006.257.22:16:03.57#ibcon#about to read 3, iclass 21, count 2 2006.257.22:16:03.58#ibcon#read 3, iclass 21, count 2 2006.257.22:16:03.58#ibcon#about to read 4, iclass 21, count 2 2006.257.22:16:03.58#ibcon#read 4, iclass 21, count 2 2006.257.22:16:03.58#ibcon#about to read 5, iclass 21, count 2 2006.257.22:16:03.58#ibcon#read 5, iclass 21, count 2 2006.257.22:16:03.58#ibcon#about to read 6, iclass 21, count 2 2006.257.22:16:03.58#ibcon#read 6, iclass 21, count 2 2006.257.22:16:03.58#ibcon#end of sib2, iclass 21, count 2 2006.257.22:16:03.58#ibcon#*mode == 0, iclass 21, count 2 2006.257.22:16:03.58#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.22:16:03.58#ibcon#[25=AT01-08\r\n] 2006.257.22:16:03.58#ibcon#*before write, iclass 21, count 2 2006.257.22:16:03.58#ibcon#enter sib2, iclass 21, count 2 2006.257.22:16:03.58#ibcon#flushed, iclass 21, count 2 2006.257.22:16:03.58#ibcon#about to write, iclass 21, count 2 2006.257.22:16:03.58#ibcon#wrote, iclass 21, count 2 2006.257.22:16:03.58#ibcon#about to read 3, iclass 21, count 2 2006.257.22:16:03.61#ibcon#read 3, iclass 21, count 2 2006.257.22:16:03.61#ibcon#about to read 4, iclass 21, count 2 2006.257.22:16:03.61#ibcon#read 4, iclass 21, count 2 2006.257.22:16:03.61#ibcon#about to read 5, iclass 21, count 2 2006.257.22:16:03.61#ibcon#read 5, iclass 21, count 2 2006.257.22:16:03.61#ibcon#about to read 6, iclass 21, count 2 2006.257.22:16:03.61#ibcon#read 6, iclass 21, count 2 2006.257.22:16:03.61#ibcon#end of sib2, iclass 21, count 2 2006.257.22:16:03.61#ibcon#*after write, iclass 21, count 2 2006.257.22:16:03.61#ibcon#*before return 0, iclass 21, count 2 2006.257.22:16:03.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:03.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:03.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.22:16:03.61#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:03.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:03.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:03.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:03.73#ibcon#enter wrdev, iclass 21, count 0 2006.257.22:16:03.73#ibcon#first serial, iclass 21, count 0 2006.257.22:16:03.73#ibcon#enter sib2, iclass 21, count 0 2006.257.22:16:03.73#ibcon#flushed, iclass 21, count 0 2006.257.22:16:03.73#ibcon#about to write, iclass 21, count 0 2006.257.22:16:03.73#ibcon#wrote, iclass 21, count 0 2006.257.22:16:03.73#ibcon#about to read 3, iclass 21, count 0 2006.257.22:16:03.75#ibcon#read 3, iclass 21, count 0 2006.257.22:16:03.75#ibcon#about to read 4, iclass 21, count 0 2006.257.22:16:03.75#ibcon#read 4, iclass 21, count 0 2006.257.22:16:03.75#ibcon#about to read 5, iclass 21, count 0 2006.257.22:16:03.75#ibcon#read 5, iclass 21, count 0 2006.257.22:16:03.75#ibcon#about to read 6, iclass 21, count 0 2006.257.22:16:03.75#ibcon#read 6, iclass 21, count 0 2006.257.22:16:03.75#ibcon#end of sib2, iclass 21, count 0 2006.257.22:16:03.75#ibcon#*mode == 0, iclass 21, count 0 2006.257.22:16:03.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.22:16:03.75#ibcon#[25=USB\r\n] 2006.257.22:16:03.75#ibcon#*before write, iclass 21, count 0 2006.257.22:16:03.75#ibcon#enter sib2, iclass 21, count 0 2006.257.22:16:03.75#ibcon#flushed, iclass 21, count 0 2006.257.22:16:03.75#ibcon#about to write, iclass 21, count 0 2006.257.22:16:03.75#ibcon#wrote, iclass 21, count 0 2006.257.22:16:03.75#ibcon#about to read 3, iclass 21, count 0 2006.257.22:16:03.78#ibcon#read 3, iclass 21, count 0 2006.257.22:16:03.78#ibcon#about to read 4, iclass 21, count 0 2006.257.22:16:03.78#ibcon#read 4, iclass 21, count 0 2006.257.22:16:03.78#ibcon#about to read 5, iclass 21, count 0 2006.257.22:16:03.78#ibcon#read 5, iclass 21, count 0 2006.257.22:16:03.78#ibcon#about to read 6, iclass 21, count 0 2006.257.22:16:03.78#ibcon#read 6, iclass 21, count 0 2006.257.22:16:03.78#ibcon#end of sib2, iclass 21, count 0 2006.257.22:16:03.78#ibcon#*after write, iclass 21, count 0 2006.257.22:16:03.78#ibcon#*before return 0, iclass 21, count 0 2006.257.22:16:03.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:03.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:03.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.22:16:03.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.22:16:03.79$vck44/valo=2,534.99 2006.257.22:16:03.79#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.22:16:03.79#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.22:16:03.79#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:03.79#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:03.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:03.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:03.79#ibcon#enter wrdev, iclass 23, count 0 2006.257.22:16:03.79#ibcon#first serial, iclass 23, count 0 2006.257.22:16:03.79#ibcon#enter sib2, iclass 23, count 0 2006.257.22:16:03.79#ibcon#flushed, iclass 23, count 0 2006.257.22:16:03.79#ibcon#about to write, iclass 23, count 0 2006.257.22:16:03.79#ibcon#wrote, iclass 23, count 0 2006.257.22:16:03.79#ibcon#about to read 3, iclass 23, count 0 2006.257.22:16:03.80#ibcon#read 3, iclass 23, count 0 2006.257.22:16:03.80#ibcon#about to read 4, iclass 23, count 0 2006.257.22:16:03.80#ibcon#read 4, iclass 23, count 0 2006.257.22:16:03.80#ibcon#about to read 5, iclass 23, count 0 2006.257.22:16:03.80#ibcon#read 5, iclass 23, count 0 2006.257.22:16:03.80#ibcon#about to read 6, iclass 23, count 0 2006.257.22:16:03.80#ibcon#read 6, iclass 23, count 0 2006.257.22:16:03.80#ibcon#end of sib2, iclass 23, count 0 2006.257.22:16:03.80#ibcon#*mode == 0, iclass 23, count 0 2006.257.22:16:03.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.22:16:03.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.22:16:03.80#ibcon#*before write, iclass 23, count 0 2006.257.22:16:03.80#ibcon#enter sib2, iclass 23, count 0 2006.257.22:16:03.80#ibcon#flushed, iclass 23, count 0 2006.257.22:16:03.80#ibcon#about to write, iclass 23, count 0 2006.257.22:16:03.80#ibcon#wrote, iclass 23, count 0 2006.257.22:16:03.80#ibcon#about to read 3, iclass 23, count 0 2006.257.22:16:03.84#ibcon#read 3, iclass 23, count 0 2006.257.22:16:03.84#ibcon#about to read 4, iclass 23, count 0 2006.257.22:16:03.84#ibcon#read 4, iclass 23, count 0 2006.257.22:16:03.84#ibcon#about to read 5, iclass 23, count 0 2006.257.22:16:03.84#ibcon#read 5, iclass 23, count 0 2006.257.22:16:03.84#ibcon#about to read 6, iclass 23, count 0 2006.257.22:16:03.84#ibcon#read 6, iclass 23, count 0 2006.257.22:16:03.84#ibcon#end of sib2, iclass 23, count 0 2006.257.22:16:03.84#ibcon#*after write, iclass 23, count 0 2006.257.22:16:03.84#ibcon#*before return 0, iclass 23, count 0 2006.257.22:16:03.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:03.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:03.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.22:16:03.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.22:16:03.85$vck44/va=2,7 2006.257.22:16:03.85#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.22:16:03.85#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.22:16:03.85#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:03.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:03.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:03.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:03.89#ibcon#enter wrdev, iclass 25, count 2 2006.257.22:16:03.89#ibcon#first serial, iclass 25, count 2 2006.257.22:16:03.89#ibcon#enter sib2, iclass 25, count 2 2006.257.22:16:03.89#ibcon#flushed, iclass 25, count 2 2006.257.22:16:03.89#ibcon#about to write, iclass 25, count 2 2006.257.22:16:03.89#ibcon#wrote, iclass 25, count 2 2006.257.22:16:03.89#ibcon#about to read 3, iclass 25, count 2 2006.257.22:16:03.91#ibcon#read 3, iclass 25, count 2 2006.257.22:16:03.91#ibcon#about to read 4, iclass 25, count 2 2006.257.22:16:03.91#ibcon#read 4, iclass 25, count 2 2006.257.22:16:03.91#ibcon#about to read 5, iclass 25, count 2 2006.257.22:16:03.91#ibcon#read 5, iclass 25, count 2 2006.257.22:16:03.91#ibcon#about to read 6, iclass 25, count 2 2006.257.22:16:03.91#ibcon#read 6, iclass 25, count 2 2006.257.22:16:03.91#ibcon#end of sib2, iclass 25, count 2 2006.257.22:16:03.91#ibcon#*mode == 0, iclass 25, count 2 2006.257.22:16:03.91#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.22:16:03.91#ibcon#[25=AT02-07\r\n] 2006.257.22:16:03.91#ibcon#*before write, iclass 25, count 2 2006.257.22:16:03.91#ibcon#enter sib2, iclass 25, count 2 2006.257.22:16:03.91#ibcon#flushed, iclass 25, count 2 2006.257.22:16:03.91#ibcon#about to write, iclass 25, count 2 2006.257.22:16:03.91#ibcon#wrote, iclass 25, count 2 2006.257.22:16:03.91#ibcon#about to read 3, iclass 25, count 2 2006.257.22:16:03.94#ibcon#read 3, iclass 25, count 2 2006.257.22:16:03.94#ibcon#about to read 4, iclass 25, count 2 2006.257.22:16:03.94#ibcon#read 4, iclass 25, count 2 2006.257.22:16:03.94#ibcon#about to read 5, iclass 25, count 2 2006.257.22:16:03.94#ibcon#read 5, iclass 25, count 2 2006.257.22:16:03.94#ibcon#about to read 6, iclass 25, count 2 2006.257.22:16:03.94#ibcon#read 6, iclass 25, count 2 2006.257.22:16:03.94#ibcon#end of sib2, iclass 25, count 2 2006.257.22:16:03.94#ibcon#*after write, iclass 25, count 2 2006.257.22:16:03.94#ibcon#*before return 0, iclass 25, count 2 2006.257.22:16:03.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:03.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:03.94#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.22:16:03.94#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:03.94#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:04.06#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:04.06#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:04.06#ibcon#enter wrdev, iclass 25, count 0 2006.257.22:16:04.06#ibcon#first serial, iclass 25, count 0 2006.257.22:16:04.06#ibcon#enter sib2, iclass 25, count 0 2006.257.22:16:04.06#ibcon#flushed, iclass 25, count 0 2006.257.22:16:04.06#ibcon#about to write, iclass 25, count 0 2006.257.22:16:04.06#ibcon#wrote, iclass 25, count 0 2006.257.22:16:04.06#ibcon#about to read 3, iclass 25, count 0 2006.257.22:16:04.08#ibcon#read 3, iclass 25, count 0 2006.257.22:16:04.08#ibcon#about to read 4, iclass 25, count 0 2006.257.22:16:04.08#ibcon#read 4, iclass 25, count 0 2006.257.22:16:04.08#ibcon#about to read 5, iclass 25, count 0 2006.257.22:16:04.08#ibcon#read 5, iclass 25, count 0 2006.257.22:16:04.08#ibcon#about to read 6, iclass 25, count 0 2006.257.22:16:04.08#ibcon#read 6, iclass 25, count 0 2006.257.22:16:04.08#ibcon#end of sib2, iclass 25, count 0 2006.257.22:16:04.08#ibcon#*mode == 0, iclass 25, count 0 2006.257.22:16:04.08#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.22:16:04.08#ibcon#[25=USB\r\n] 2006.257.22:16:04.08#ibcon#*before write, iclass 25, count 0 2006.257.22:16:04.08#ibcon#enter sib2, iclass 25, count 0 2006.257.22:16:04.08#ibcon#flushed, iclass 25, count 0 2006.257.22:16:04.08#ibcon#about to write, iclass 25, count 0 2006.257.22:16:04.08#ibcon#wrote, iclass 25, count 0 2006.257.22:16:04.08#ibcon#about to read 3, iclass 25, count 0 2006.257.22:16:04.11#ibcon#read 3, iclass 25, count 0 2006.257.22:16:04.11#ibcon#about to read 4, iclass 25, count 0 2006.257.22:16:04.11#ibcon#read 4, iclass 25, count 0 2006.257.22:16:04.11#ibcon#about to read 5, iclass 25, count 0 2006.257.22:16:04.11#ibcon#read 5, iclass 25, count 0 2006.257.22:16:04.11#ibcon#about to read 6, iclass 25, count 0 2006.257.22:16:04.11#ibcon#read 6, iclass 25, count 0 2006.257.22:16:04.11#ibcon#end of sib2, iclass 25, count 0 2006.257.22:16:04.11#ibcon#*after write, iclass 25, count 0 2006.257.22:16:04.11#ibcon#*before return 0, iclass 25, count 0 2006.257.22:16:04.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:04.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:04.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.22:16:04.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.22:16:04.12$vck44/valo=3,564.99 2006.257.22:16:04.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.22:16:04.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.22:16:04.12#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:04.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:04.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:04.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:04.12#ibcon#enter wrdev, iclass 27, count 0 2006.257.22:16:04.12#ibcon#first serial, iclass 27, count 0 2006.257.22:16:04.12#ibcon#enter sib2, iclass 27, count 0 2006.257.22:16:04.12#ibcon#flushed, iclass 27, count 0 2006.257.22:16:04.12#ibcon#about to write, iclass 27, count 0 2006.257.22:16:04.12#ibcon#wrote, iclass 27, count 0 2006.257.22:16:04.12#ibcon#about to read 3, iclass 27, count 0 2006.257.22:16:04.13#ibcon#read 3, iclass 27, count 0 2006.257.22:16:04.13#ibcon#about to read 4, iclass 27, count 0 2006.257.22:16:04.13#ibcon#read 4, iclass 27, count 0 2006.257.22:16:04.13#ibcon#about to read 5, iclass 27, count 0 2006.257.22:16:04.13#ibcon#read 5, iclass 27, count 0 2006.257.22:16:04.13#ibcon#about to read 6, iclass 27, count 0 2006.257.22:16:04.13#ibcon#read 6, iclass 27, count 0 2006.257.22:16:04.13#ibcon#end of sib2, iclass 27, count 0 2006.257.22:16:04.13#ibcon#*mode == 0, iclass 27, count 0 2006.257.22:16:04.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.22:16:04.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.22:16:04.13#ibcon#*before write, iclass 27, count 0 2006.257.22:16:04.13#ibcon#enter sib2, iclass 27, count 0 2006.257.22:16:04.13#ibcon#flushed, iclass 27, count 0 2006.257.22:16:04.13#ibcon#about to write, iclass 27, count 0 2006.257.22:16:04.13#ibcon#wrote, iclass 27, count 0 2006.257.22:16:04.13#ibcon#about to read 3, iclass 27, count 0 2006.257.22:16:04.17#ibcon#read 3, iclass 27, count 0 2006.257.22:16:04.17#ibcon#about to read 4, iclass 27, count 0 2006.257.22:16:04.17#ibcon#read 4, iclass 27, count 0 2006.257.22:16:04.17#ibcon#about to read 5, iclass 27, count 0 2006.257.22:16:04.17#ibcon#read 5, iclass 27, count 0 2006.257.22:16:04.17#ibcon#about to read 6, iclass 27, count 0 2006.257.22:16:04.17#ibcon#read 6, iclass 27, count 0 2006.257.22:16:04.17#ibcon#end of sib2, iclass 27, count 0 2006.257.22:16:04.17#ibcon#*after write, iclass 27, count 0 2006.257.22:16:04.17#ibcon#*before return 0, iclass 27, count 0 2006.257.22:16:04.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:04.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:04.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.22:16:04.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.22:16:04.18$vck44/va=3,8 2006.257.22:16:04.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.22:16:04.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.22:16:04.18#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:04.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:04.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:04.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:04.22#ibcon#enter wrdev, iclass 29, count 2 2006.257.22:16:04.22#ibcon#first serial, iclass 29, count 2 2006.257.22:16:04.22#ibcon#enter sib2, iclass 29, count 2 2006.257.22:16:04.22#ibcon#flushed, iclass 29, count 2 2006.257.22:16:04.22#ibcon#about to write, iclass 29, count 2 2006.257.22:16:04.22#ibcon#wrote, iclass 29, count 2 2006.257.22:16:04.22#ibcon#about to read 3, iclass 29, count 2 2006.257.22:16:04.24#ibcon#read 3, iclass 29, count 2 2006.257.22:16:04.24#ibcon#about to read 4, iclass 29, count 2 2006.257.22:16:04.24#ibcon#read 4, iclass 29, count 2 2006.257.22:16:04.24#ibcon#about to read 5, iclass 29, count 2 2006.257.22:16:04.24#ibcon#read 5, iclass 29, count 2 2006.257.22:16:04.24#ibcon#about to read 6, iclass 29, count 2 2006.257.22:16:04.24#ibcon#read 6, iclass 29, count 2 2006.257.22:16:04.24#ibcon#end of sib2, iclass 29, count 2 2006.257.22:16:04.24#ibcon#*mode == 0, iclass 29, count 2 2006.257.22:16:04.24#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.22:16:04.24#ibcon#[25=AT03-08\r\n] 2006.257.22:16:04.24#ibcon#*before write, iclass 29, count 2 2006.257.22:16:04.24#ibcon#enter sib2, iclass 29, count 2 2006.257.22:16:04.24#ibcon#flushed, iclass 29, count 2 2006.257.22:16:04.24#ibcon#about to write, iclass 29, count 2 2006.257.22:16:04.24#ibcon#wrote, iclass 29, count 2 2006.257.22:16:04.24#ibcon#about to read 3, iclass 29, count 2 2006.257.22:16:04.27#ibcon#read 3, iclass 29, count 2 2006.257.22:16:04.27#ibcon#about to read 4, iclass 29, count 2 2006.257.22:16:04.27#ibcon#read 4, iclass 29, count 2 2006.257.22:16:04.27#ibcon#about to read 5, iclass 29, count 2 2006.257.22:16:04.27#ibcon#read 5, iclass 29, count 2 2006.257.22:16:04.27#ibcon#about to read 6, iclass 29, count 2 2006.257.22:16:04.27#ibcon#read 6, iclass 29, count 2 2006.257.22:16:04.27#ibcon#end of sib2, iclass 29, count 2 2006.257.22:16:04.27#ibcon#*after write, iclass 29, count 2 2006.257.22:16:04.27#ibcon#*before return 0, iclass 29, count 2 2006.257.22:16:04.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:04.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:04.27#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.22:16:04.27#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:04.27#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:04.39#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:04.39#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:04.39#ibcon#enter wrdev, iclass 29, count 0 2006.257.22:16:04.39#ibcon#first serial, iclass 29, count 0 2006.257.22:16:04.39#ibcon#enter sib2, iclass 29, count 0 2006.257.22:16:04.39#ibcon#flushed, iclass 29, count 0 2006.257.22:16:04.39#ibcon#about to write, iclass 29, count 0 2006.257.22:16:04.39#ibcon#wrote, iclass 29, count 0 2006.257.22:16:04.39#ibcon#about to read 3, iclass 29, count 0 2006.257.22:16:04.41#ibcon#read 3, iclass 29, count 0 2006.257.22:16:04.41#ibcon#about to read 4, iclass 29, count 0 2006.257.22:16:04.41#ibcon#read 4, iclass 29, count 0 2006.257.22:16:04.41#ibcon#about to read 5, iclass 29, count 0 2006.257.22:16:04.41#ibcon#read 5, iclass 29, count 0 2006.257.22:16:04.41#ibcon#about to read 6, iclass 29, count 0 2006.257.22:16:04.41#ibcon#read 6, iclass 29, count 0 2006.257.22:16:04.41#ibcon#end of sib2, iclass 29, count 0 2006.257.22:16:04.41#ibcon#*mode == 0, iclass 29, count 0 2006.257.22:16:04.41#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.22:16:04.41#ibcon#[25=USB\r\n] 2006.257.22:16:04.41#ibcon#*before write, iclass 29, count 0 2006.257.22:16:04.41#ibcon#enter sib2, iclass 29, count 0 2006.257.22:16:04.41#ibcon#flushed, iclass 29, count 0 2006.257.22:16:04.41#ibcon#about to write, iclass 29, count 0 2006.257.22:16:04.41#ibcon#wrote, iclass 29, count 0 2006.257.22:16:04.41#ibcon#about to read 3, iclass 29, count 0 2006.257.22:16:04.44#ibcon#read 3, iclass 29, count 0 2006.257.22:16:04.44#ibcon#about to read 4, iclass 29, count 0 2006.257.22:16:04.44#ibcon#read 4, iclass 29, count 0 2006.257.22:16:04.44#ibcon#about to read 5, iclass 29, count 0 2006.257.22:16:04.44#ibcon#read 5, iclass 29, count 0 2006.257.22:16:04.44#ibcon#about to read 6, iclass 29, count 0 2006.257.22:16:04.44#ibcon#read 6, iclass 29, count 0 2006.257.22:16:04.44#ibcon#end of sib2, iclass 29, count 0 2006.257.22:16:04.44#ibcon#*after write, iclass 29, count 0 2006.257.22:16:04.44#ibcon#*before return 0, iclass 29, count 0 2006.257.22:16:04.44#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:04.44#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:04.44#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.22:16:04.44#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.22:16:04.45$vck44/valo=4,624.99 2006.257.22:16:04.45#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.22:16:04.45#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.22:16:04.45#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:04.45#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:04.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:04.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:04.45#ibcon#enter wrdev, iclass 31, count 0 2006.257.22:16:04.45#ibcon#first serial, iclass 31, count 0 2006.257.22:16:04.45#ibcon#enter sib2, iclass 31, count 0 2006.257.22:16:04.45#ibcon#flushed, iclass 31, count 0 2006.257.22:16:04.45#ibcon#about to write, iclass 31, count 0 2006.257.22:16:04.45#ibcon#wrote, iclass 31, count 0 2006.257.22:16:04.45#ibcon#about to read 3, iclass 31, count 0 2006.257.22:16:04.46#ibcon#read 3, iclass 31, count 0 2006.257.22:16:04.46#ibcon#about to read 4, iclass 31, count 0 2006.257.22:16:04.46#ibcon#read 4, iclass 31, count 0 2006.257.22:16:04.46#ibcon#about to read 5, iclass 31, count 0 2006.257.22:16:04.46#ibcon#read 5, iclass 31, count 0 2006.257.22:16:04.46#ibcon#about to read 6, iclass 31, count 0 2006.257.22:16:04.46#ibcon#read 6, iclass 31, count 0 2006.257.22:16:04.46#ibcon#end of sib2, iclass 31, count 0 2006.257.22:16:04.46#ibcon#*mode == 0, iclass 31, count 0 2006.257.22:16:04.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.22:16:04.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.22:16:04.46#ibcon#*before write, iclass 31, count 0 2006.257.22:16:04.46#ibcon#enter sib2, iclass 31, count 0 2006.257.22:16:04.46#ibcon#flushed, iclass 31, count 0 2006.257.22:16:04.46#ibcon#about to write, iclass 31, count 0 2006.257.22:16:04.46#ibcon#wrote, iclass 31, count 0 2006.257.22:16:04.46#ibcon#about to read 3, iclass 31, count 0 2006.257.22:16:04.50#ibcon#read 3, iclass 31, count 0 2006.257.22:16:04.50#ibcon#about to read 4, iclass 31, count 0 2006.257.22:16:04.50#ibcon#read 4, iclass 31, count 0 2006.257.22:16:04.50#ibcon#about to read 5, iclass 31, count 0 2006.257.22:16:04.50#ibcon#read 5, iclass 31, count 0 2006.257.22:16:04.50#ibcon#about to read 6, iclass 31, count 0 2006.257.22:16:04.50#ibcon#read 6, iclass 31, count 0 2006.257.22:16:04.51#ibcon#end of sib2, iclass 31, count 0 2006.257.22:16:04.51#ibcon#*after write, iclass 31, count 0 2006.257.22:16:04.51#ibcon#*before return 0, iclass 31, count 0 2006.257.22:16:04.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:04.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:04.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.22:16:04.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.22:16:04.51$vck44/va=4,7 2006.257.22:16:04.51#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.22:16:04.51#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.22:16:04.51#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:04.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:04.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:04.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:04.55#ibcon#enter wrdev, iclass 33, count 2 2006.257.22:16:04.55#ibcon#first serial, iclass 33, count 2 2006.257.22:16:04.55#ibcon#enter sib2, iclass 33, count 2 2006.257.22:16:04.55#ibcon#flushed, iclass 33, count 2 2006.257.22:16:04.55#ibcon#about to write, iclass 33, count 2 2006.257.22:16:04.55#ibcon#wrote, iclass 33, count 2 2006.257.22:16:04.55#ibcon#about to read 3, iclass 33, count 2 2006.257.22:16:04.57#ibcon#read 3, iclass 33, count 2 2006.257.22:16:04.57#ibcon#about to read 4, iclass 33, count 2 2006.257.22:16:04.57#ibcon#read 4, iclass 33, count 2 2006.257.22:16:04.57#ibcon#about to read 5, iclass 33, count 2 2006.257.22:16:04.57#ibcon#read 5, iclass 33, count 2 2006.257.22:16:04.57#ibcon#about to read 6, iclass 33, count 2 2006.257.22:16:04.57#ibcon#read 6, iclass 33, count 2 2006.257.22:16:04.57#ibcon#end of sib2, iclass 33, count 2 2006.257.22:16:04.57#ibcon#*mode == 0, iclass 33, count 2 2006.257.22:16:04.57#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.22:16:04.57#ibcon#[25=AT04-07\r\n] 2006.257.22:16:04.57#ibcon#*before write, iclass 33, count 2 2006.257.22:16:04.57#ibcon#enter sib2, iclass 33, count 2 2006.257.22:16:04.57#ibcon#flushed, iclass 33, count 2 2006.257.22:16:04.57#ibcon#about to write, iclass 33, count 2 2006.257.22:16:04.57#ibcon#wrote, iclass 33, count 2 2006.257.22:16:04.57#ibcon#about to read 3, iclass 33, count 2 2006.257.22:16:04.60#ibcon#read 3, iclass 33, count 2 2006.257.22:16:04.60#ibcon#about to read 4, iclass 33, count 2 2006.257.22:16:04.60#ibcon#read 4, iclass 33, count 2 2006.257.22:16:04.60#ibcon#about to read 5, iclass 33, count 2 2006.257.22:16:04.60#ibcon#read 5, iclass 33, count 2 2006.257.22:16:04.60#ibcon#about to read 6, iclass 33, count 2 2006.257.22:16:04.60#ibcon#read 6, iclass 33, count 2 2006.257.22:16:04.60#ibcon#end of sib2, iclass 33, count 2 2006.257.22:16:04.60#ibcon#*after write, iclass 33, count 2 2006.257.22:16:04.60#ibcon#*before return 0, iclass 33, count 2 2006.257.22:16:04.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:04.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:04.60#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.22:16:04.60#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:04.60#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:04.72#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:04.72#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:04.72#ibcon#enter wrdev, iclass 33, count 0 2006.257.22:16:04.72#ibcon#first serial, iclass 33, count 0 2006.257.22:16:04.72#ibcon#enter sib2, iclass 33, count 0 2006.257.22:16:04.72#ibcon#flushed, iclass 33, count 0 2006.257.22:16:04.72#ibcon#about to write, iclass 33, count 0 2006.257.22:16:04.72#ibcon#wrote, iclass 33, count 0 2006.257.22:16:04.72#ibcon#about to read 3, iclass 33, count 0 2006.257.22:16:04.74#ibcon#read 3, iclass 33, count 0 2006.257.22:16:04.74#ibcon#about to read 4, iclass 33, count 0 2006.257.22:16:04.74#ibcon#read 4, iclass 33, count 0 2006.257.22:16:04.74#ibcon#about to read 5, iclass 33, count 0 2006.257.22:16:04.74#ibcon#read 5, iclass 33, count 0 2006.257.22:16:04.74#ibcon#about to read 6, iclass 33, count 0 2006.257.22:16:04.74#ibcon#read 6, iclass 33, count 0 2006.257.22:16:04.74#ibcon#end of sib2, iclass 33, count 0 2006.257.22:16:04.74#ibcon#*mode == 0, iclass 33, count 0 2006.257.22:16:04.74#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.22:16:04.74#ibcon#[25=USB\r\n] 2006.257.22:16:04.74#ibcon#*before write, iclass 33, count 0 2006.257.22:16:04.74#ibcon#enter sib2, iclass 33, count 0 2006.257.22:16:04.74#ibcon#flushed, iclass 33, count 0 2006.257.22:16:04.74#ibcon#about to write, iclass 33, count 0 2006.257.22:16:04.74#ibcon#wrote, iclass 33, count 0 2006.257.22:16:04.74#ibcon#about to read 3, iclass 33, count 0 2006.257.22:16:04.77#ibcon#read 3, iclass 33, count 0 2006.257.22:16:04.77#ibcon#about to read 4, iclass 33, count 0 2006.257.22:16:04.77#ibcon#read 4, iclass 33, count 0 2006.257.22:16:04.77#ibcon#about to read 5, iclass 33, count 0 2006.257.22:16:04.77#ibcon#read 5, iclass 33, count 0 2006.257.22:16:04.77#ibcon#about to read 6, iclass 33, count 0 2006.257.22:16:04.77#ibcon#read 6, iclass 33, count 0 2006.257.22:16:04.77#ibcon#end of sib2, iclass 33, count 0 2006.257.22:16:04.77#ibcon#*after write, iclass 33, count 0 2006.257.22:16:04.77#ibcon#*before return 0, iclass 33, count 0 2006.257.22:16:04.77#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:04.77#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:04.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.22:16:04.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.22:16:04.78$vck44/valo=5,734.99 2006.257.22:16:04.78#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.22:16:04.78#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.22:16:04.78#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:04.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:04.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:04.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:04.78#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:16:04.78#ibcon#first serial, iclass 35, count 0 2006.257.22:16:04.78#ibcon#enter sib2, iclass 35, count 0 2006.257.22:16:04.78#ibcon#flushed, iclass 35, count 0 2006.257.22:16:04.78#ibcon#about to write, iclass 35, count 0 2006.257.22:16:04.78#ibcon#wrote, iclass 35, count 0 2006.257.22:16:04.78#ibcon#about to read 3, iclass 35, count 0 2006.257.22:16:04.79#ibcon#read 3, iclass 35, count 0 2006.257.22:16:04.79#ibcon#about to read 4, iclass 35, count 0 2006.257.22:16:04.79#ibcon#read 4, iclass 35, count 0 2006.257.22:16:04.79#ibcon#about to read 5, iclass 35, count 0 2006.257.22:16:04.79#ibcon#read 5, iclass 35, count 0 2006.257.22:16:04.79#ibcon#about to read 6, iclass 35, count 0 2006.257.22:16:04.79#ibcon#read 6, iclass 35, count 0 2006.257.22:16:04.79#ibcon#end of sib2, iclass 35, count 0 2006.257.22:16:04.79#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:16:04.79#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:16:04.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.22:16:04.79#ibcon#*before write, iclass 35, count 0 2006.257.22:16:04.79#ibcon#enter sib2, iclass 35, count 0 2006.257.22:16:04.79#ibcon#flushed, iclass 35, count 0 2006.257.22:16:04.79#ibcon#about to write, iclass 35, count 0 2006.257.22:16:04.79#ibcon#wrote, iclass 35, count 0 2006.257.22:16:04.79#ibcon#about to read 3, iclass 35, count 0 2006.257.22:16:04.83#ibcon#read 3, iclass 35, count 0 2006.257.22:16:04.83#ibcon#about to read 4, iclass 35, count 0 2006.257.22:16:04.83#ibcon#read 4, iclass 35, count 0 2006.257.22:16:04.83#ibcon#about to read 5, iclass 35, count 0 2006.257.22:16:04.83#ibcon#read 5, iclass 35, count 0 2006.257.22:16:04.83#ibcon#about to read 6, iclass 35, count 0 2006.257.22:16:04.83#ibcon#read 6, iclass 35, count 0 2006.257.22:16:04.83#ibcon#end of sib2, iclass 35, count 0 2006.257.22:16:04.83#ibcon#*after write, iclass 35, count 0 2006.257.22:16:04.83#ibcon#*before return 0, iclass 35, count 0 2006.257.22:16:04.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:04.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:04.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:16:04.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:16:04.84$vck44/va=5,4 2006.257.22:16:04.84#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.22:16:04.84#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.22:16:04.84#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:04.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:16:04.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:16:04.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:16:04.88#ibcon#enter wrdev, iclass 37, count 2 2006.257.22:16:04.88#ibcon#first serial, iclass 37, count 2 2006.257.22:16:04.88#ibcon#enter sib2, iclass 37, count 2 2006.257.22:16:04.88#ibcon#flushed, iclass 37, count 2 2006.257.22:16:04.88#ibcon#about to write, iclass 37, count 2 2006.257.22:16:04.88#ibcon#wrote, iclass 37, count 2 2006.257.22:16:04.88#ibcon#about to read 3, iclass 37, count 2 2006.257.22:16:04.90#ibcon#read 3, iclass 37, count 2 2006.257.22:16:04.90#ibcon#about to read 4, iclass 37, count 2 2006.257.22:16:04.90#ibcon#read 4, iclass 37, count 2 2006.257.22:16:04.90#ibcon#about to read 5, iclass 37, count 2 2006.257.22:16:04.90#ibcon#read 5, iclass 37, count 2 2006.257.22:16:04.90#ibcon#about to read 6, iclass 37, count 2 2006.257.22:16:04.90#ibcon#read 6, iclass 37, count 2 2006.257.22:16:04.90#ibcon#end of sib2, iclass 37, count 2 2006.257.22:16:04.90#ibcon#*mode == 0, iclass 37, count 2 2006.257.22:16:04.90#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.22:16:04.90#ibcon#[25=AT05-04\r\n] 2006.257.22:16:04.90#ibcon#*before write, iclass 37, count 2 2006.257.22:16:04.90#ibcon#enter sib2, iclass 37, count 2 2006.257.22:16:04.90#ibcon#flushed, iclass 37, count 2 2006.257.22:16:04.90#ibcon#about to write, iclass 37, count 2 2006.257.22:16:04.90#ibcon#wrote, iclass 37, count 2 2006.257.22:16:04.90#ibcon#about to read 3, iclass 37, count 2 2006.257.22:16:04.93#ibcon#read 3, iclass 37, count 2 2006.257.22:16:04.93#ibcon#about to read 4, iclass 37, count 2 2006.257.22:16:04.93#ibcon#read 4, iclass 37, count 2 2006.257.22:16:04.93#ibcon#about to read 5, iclass 37, count 2 2006.257.22:16:04.93#ibcon#read 5, iclass 37, count 2 2006.257.22:16:04.93#ibcon#about to read 6, iclass 37, count 2 2006.257.22:16:04.93#ibcon#read 6, iclass 37, count 2 2006.257.22:16:04.93#ibcon#end of sib2, iclass 37, count 2 2006.257.22:16:04.93#ibcon#*after write, iclass 37, count 2 2006.257.22:16:04.93#ibcon#*before return 0, iclass 37, count 2 2006.257.22:16:04.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:16:04.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:16:04.93#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.22:16:04.93#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:04.93#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:16:05.05#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:16:05.05#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:16:05.05#ibcon#enter wrdev, iclass 37, count 0 2006.257.22:16:05.05#ibcon#first serial, iclass 37, count 0 2006.257.22:16:05.05#ibcon#enter sib2, iclass 37, count 0 2006.257.22:16:05.05#ibcon#flushed, iclass 37, count 0 2006.257.22:16:05.05#ibcon#about to write, iclass 37, count 0 2006.257.22:16:05.05#ibcon#wrote, iclass 37, count 0 2006.257.22:16:05.05#ibcon#about to read 3, iclass 37, count 0 2006.257.22:16:05.07#ibcon#read 3, iclass 37, count 0 2006.257.22:16:05.07#ibcon#about to read 4, iclass 37, count 0 2006.257.22:16:05.07#ibcon#read 4, iclass 37, count 0 2006.257.22:16:05.07#ibcon#about to read 5, iclass 37, count 0 2006.257.22:16:05.07#ibcon#read 5, iclass 37, count 0 2006.257.22:16:05.07#ibcon#about to read 6, iclass 37, count 0 2006.257.22:16:05.07#ibcon#read 6, iclass 37, count 0 2006.257.22:16:05.07#ibcon#end of sib2, iclass 37, count 0 2006.257.22:16:05.07#ibcon#*mode == 0, iclass 37, count 0 2006.257.22:16:05.07#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.22:16:05.07#ibcon#[25=USB\r\n] 2006.257.22:16:05.07#ibcon#*before write, iclass 37, count 0 2006.257.22:16:05.07#ibcon#enter sib2, iclass 37, count 0 2006.257.22:16:05.07#ibcon#flushed, iclass 37, count 0 2006.257.22:16:05.07#ibcon#about to write, iclass 37, count 0 2006.257.22:16:05.07#ibcon#wrote, iclass 37, count 0 2006.257.22:16:05.07#ibcon#about to read 3, iclass 37, count 0 2006.257.22:16:05.10#ibcon#read 3, iclass 37, count 0 2006.257.22:16:05.10#ibcon#about to read 4, iclass 37, count 0 2006.257.22:16:05.10#ibcon#read 4, iclass 37, count 0 2006.257.22:16:05.10#ibcon#about to read 5, iclass 37, count 0 2006.257.22:16:05.10#ibcon#read 5, iclass 37, count 0 2006.257.22:16:05.10#ibcon#about to read 6, iclass 37, count 0 2006.257.22:16:05.10#ibcon#read 6, iclass 37, count 0 2006.257.22:16:05.10#ibcon#end of sib2, iclass 37, count 0 2006.257.22:16:05.10#ibcon#*after write, iclass 37, count 0 2006.257.22:16:05.10#ibcon#*before return 0, iclass 37, count 0 2006.257.22:16:05.10#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:16:05.10#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:16:05.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.22:16:05.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.22:16:05.11$vck44/valo=6,814.99 2006.257.22:16:05.11#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.22:16:05.11#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.22:16:05.11#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:05.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:16:05.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:16:05.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:16:05.11#ibcon#enter wrdev, iclass 39, count 0 2006.257.22:16:05.11#ibcon#first serial, iclass 39, count 0 2006.257.22:16:05.11#ibcon#enter sib2, iclass 39, count 0 2006.257.22:16:05.11#ibcon#flushed, iclass 39, count 0 2006.257.22:16:05.11#ibcon#about to write, iclass 39, count 0 2006.257.22:16:05.11#ibcon#wrote, iclass 39, count 0 2006.257.22:16:05.11#ibcon#about to read 3, iclass 39, count 0 2006.257.22:16:05.12#ibcon#read 3, iclass 39, count 0 2006.257.22:16:05.12#ibcon#about to read 4, iclass 39, count 0 2006.257.22:16:05.12#ibcon#read 4, iclass 39, count 0 2006.257.22:16:05.12#ibcon#about to read 5, iclass 39, count 0 2006.257.22:16:05.12#ibcon#read 5, iclass 39, count 0 2006.257.22:16:05.12#ibcon#about to read 6, iclass 39, count 0 2006.257.22:16:05.12#ibcon#read 6, iclass 39, count 0 2006.257.22:16:05.12#ibcon#end of sib2, iclass 39, count 0 2006.257.22:16:05.12#ibcon#*mode == 0, iclass 39, count 0 2006.257.22:16:05.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.22:16:05.12#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.22:16:05.12#ibcon#*before write, iclass 39, count 0 2006.257.22:16:05.12#ibcon#enter sib2, iclass 39, count 0 2006.257.22:16:05.12#ibcon#flushed, iclass 39, count 0 2006.257.22:16:05.12#ibcon#about to write, iclass 39, count 0 2006.257.22:16:05.12#ibcon#wrote, iclass 39, count 0 2006.257.22:16:05.12#ibcon#about to read 3, iclass 39, count 0 2006.257.22:16:05.16#ibcon#read 3, iclass 39, count 0 2006.257.22:16:05.16#ibcon#about to read 4, iclass 39, count 0 2006.257.22:16:05.16#ibcon#read 4, iclass 39, count 0 2006.257.22:16:05.16#ibcon#about to read 5, iclass 39, count 0 2006.257.22:16:05.16#ibcon#read 5, iclass 39, count 0 2006.257.22:16:05.16#ibcon#about to read 6, iclass 39, count 0 2006.257.22:16:05.16#ibcon#read 6, iclass 39, count 0 2006.257.22:16:05.16#ibcon#end of sib2, iclass 39, count 0 2006.257.22:16:05.16#ibcon#*after write, iclass 39, count 0 2006.257.22:16:05.16#ibcon#*before return 0, iclass 39, count 0 2006.257.22:16:05.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:16:05.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:16:05.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.22:16:05.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.22:16:05.17$vck44/va=6,4 2006.257.22:16:05.17#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.22:16:05.17#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.22:16:05.17#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:05.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:16:05.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:16:05.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:16:05.21#ibcon#enter wrdev, iclass 3, count 2 2006.257.22:16:05.21#ibcon#first serial, iclass 3, count 2 2006.257.22:16:05.21#ibcon#enter sib2, iclass 3, count 2 2006.257.22:16:05.21#ibcon#flushed, iclass 3, count 2 2006.257.22:16:05.21#ibcon#about to write, iclass 3, count 2 2006.257.22:16:05.21#ibcon#wrote, iclass 3, count 2 2006.257.22:16:05.21#ibcon#about to read 3, iclass 3, count 2 2006.257.22:16:05.23#ibcon#read 3, iclass 3, count 2 2006.257.22:16:05.23#ibcon#about to read 4, iclass 3, count 2 2006.257.22:16:05.23#ibcon#read 4, iclass 3, count 2 2006.257.22:16:05.23#ibcon#about to read 5, iclass 3, count 2 2006.257.22:16:05.23#ibcon#read 5, iclass 3, count 2 2006.257.22:16:05.23#ibcon#about to read 6, iclass 3, count 2 2006.257.22:16:05.23#ibcon#read 6, iclass 3, count 2 2006.257.22:16:05.23#ibcon#end of sib2, iclass 3, count 2 2006.257.22:16:05.23#ibcon#*mode == 0, iclass 3, count 2 2006.257.22:16:05.23#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.22:16:05.23#ibcon#[25=AT06-04\r\n] 2006.257.22:16:05.23#ibcon#*before write, iclass 3, count 2 2006.257.22:16:05.23#ibcon#enter sib2, iclass 3, count 2 2006.257.22:16:05.23#ibcon#flushed, iclass 3, count 2 2006.257.22:16:05.23#ibcon#about to write, iclass 3, count 2 2006.257.22:16:05.23#ibcon#wrote, iclass 3, count 2 2006.257.22:16:05.23#ibcon#about to read 3, iclass 3, count 2 2006.257.22:16:05.26#ibcon#read 3, iclass 3, count 2 2006.257.22:16:05.26#ibcon#about to read 4, iclass 3, count 2 2006.257.22:16:05.26#ibcon#read 4, iclass 3, count 2 2006.257.22:16:05.26#ibcon#about to read 5, iclass 3, count 2 2006.257.22:16:05.26#ibcon#read 5, iclass 3, count 2 2006.257.22:16:05.26#ibcon#about to read 6, iclass 3, count 2 2006.257.22:16:05.26#ibcon#read 6, iclass 3, count 2 2006.257.22:16:05.26#ibcon#end of sib2, iclass 3, count 2 2006.257.22:16:05.26#ibcon#*after write, iclass 3, count 2 2006.257.22:16:05.26#ibcon#*before return 0, iclass 3, count 2 2006.257.22:16:05.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:16:05.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:16:05.26#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.22:16:05.26#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:05.26#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:16:05.38#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:16:05.38#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:16:05.38#ibcon#enter wrdev, iclass 3, count 0 2006.257.22:16:05.38#ibcon#first serial, iclass 3, count 0 2006.257.22:16:05.38#ibcon#enter sib2, iclass 3, count 0 2006.257.22:16:05.38#ibcon#flushed, iclass 3, count 0 2006.257.22:16:05.38#ibcon#about to write, iclass 3, count 0 2006.257.22:16:05.38#ibcon#wrote, iclass 3, count 0 2006.257.22:16:05.38#ibcon#about to read 3, iclass 3, count 0 2006.257.22:16:05.40#ibcon#read 3, iclass 3, count 0 2006.257.22:16:05.40#ibcon#about to read 4, iclass 3, count 0 2006.257.22:16:05.40#ibcon#read 4, iclass 3, count 0 2006.257.22:16:05.40#ibcon#about to read 5, iclass 3, count 0 2006.257.22:16:05.40#ibcon#read 5, iclass 3, count 0 2006.257.22:16:05.40#ibcon#about to read 6, iclass 3, count 0 2006.257.22:16:05.40#ibcon#read 6, iclass 3, count 0 2006.257.22:16:05.40#ibcon#end of sib2, iclass 3, count 0 2006.257.22:16:05.40#ibcon#*mode == 0, iclass 3, count 0 2006.257.22:16:05.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.22:16:05.40#ibcon#[25=USB\r\n] 2006.257.22:16:05.40#ibcon#*before write, iclass 3, count 0 2006.257.22:16:05.40#ibcon#enter sib2, iclass 3, count 0 2006.257.22:16:05.40#ibcon#flushed, iclass 3, count 0 2006.257.22:16:05.40#ibcon#about to write, iclass 3, count 0 2006.257.22:16:05.40#ibcon#wrote, iclass 3, count 0 2006.257.22:16:05.40#ibcon#about to read 3, iclass 3, count 0 2006.257.22:16:05.43#ibcon#read 3, iclass 3, count 0 2006.257.22:16:05.43#ibcon#about to read 4, iclass 3, count 0 2006.257.22:16:05.43#ibcon#read 4, iclass 3, count 0 2006.257.22:16:05.43#ibcon#about to read 5, iclass 3, count 0 2006.257.22:16:05.43#ibcon#read 5, iclass 3, count 0 2006.257.22:16:05.43#ibcon#about to read 6, iclass 3, count 0 2006.257.22:16:05.43#ibcon#read 6, iclass 3, count 0 2006.257.22:16:05.43#ibcon#end of sib2, iclass 3, count 0 2006.257.22:16:05.43#ibcon#*after write, iclass 3, count 0 2006.257.22:16:05.43#ibcon#*before return 0, iclass 3, count 0 2006.257.22:16:05.43#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:16:05.43#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:16:05.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.22:16:05.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.22:16:05.44$vck44/valo=7,864.99 2006.257.22:16:05.44#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.22:16:05.44#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.22:16:05.44#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:05.44#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:05.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:05.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:05.44#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:16:05.44#ibcon#first serial, iclass 5, count 0 2006.257.22:16:05.44#ibcon#enter sib2, iclass 5, count 0 2006.257.22:16:05.44#ibcon#flushed, iclass 5, count 0 2006.257.22:16:05.44#ibcon#about to write, iclass 5, count 0 2006.257.22:16:05.44#ibcon#wrote, iclass 5, count 0 2006.257.22:16:05.44#ibcon#about to read 3, iclass 5, count 0 2006.257.22:16:05.45#ibcon#read 3, iclass 5, count 0 2006.257.22:16:05.45#ibcon#about to read 4, iclass 5, count 0 2006.257.22:16:05.45#ibcon#read 4, iclass 5, count 0 2006.257.22:16:05.45#ibcon#about to read 5, iclass 5, count 0 2006.257.22:16:05.45#ibcon#read 5, iclass 5, count 0 2006.257.22:16:05.45#ibcon#about to read 6, iclass 5, count 0 2006.257.22:16:05.45#ibcon#read 6, iclass 5, count 0 2006.257.22:16:05.45#ibcon#end of sib2, iclass 5, count 0 2006.257.22:16:05.45#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:16:05.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:16:05.45#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.22:16:05.45#ibcon#*before write, iclass 5, count 0 2006.257.22:16:05.45#ibcon#enter sib2, iclass 5, count 0 2006.257.22:16:05.45#ibcon#flushed, iclass 5, count 0 2006.257.22:16:05.45#ibcon#about to write, iclass 5, count 0 2006.257.22:16:05.45#ibcon#wrote, iclass 5, count 0 2006.257.22:16:05.45#ibcon#about to read 3, iclass 5, count 0 2006.257.22:16:05.49#ibcon#read 3, iclass 5, count 0 2006.257.22:16:05.49#ibcon#about to read 4, iclass 5, count 0 2006.257.22:16:05.49#ibcon#read 4, iclass 5, count 0 2006.257.22:16:05.49#ibcon#about to read 5, iclass 5, count 0 2006.257.22:16:05.49#ibcon#read 5, iclass 5, count 0 2006.257.22:16:05.49#ibcon#about to read 6, iclass 5, count 0 2006.257.22:16:05.49#ibcon#read 6, iclass 5, count 0 2006.257.22:16:05.49#ibcon#end of sib2, iclass 5, count 0 2006.257.22:16:05.49#ibcon#*after write, iclass 5, count 0 2006.257.22:16:05.49#ibcon#*before return 0, iclass 5, count 0 2006.257.22:16:05.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:05.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:05.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:16:05.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:16:05.50$vck44/va=7,4 2006.257.22:16:05.50#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.22:16:05.50#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.22:16:05.50#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:05.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:05.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:05.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:05.54#ibcon#enter wrdev, iclass 7, count 2 2006.257.22:16:05.54#ibcon#first serial, iclass 7, count 2 2006.257.22:16:05.54#ibcon#enter sib2, iclass 7, count 2 2006.257.22:16:05.54#ibcon#flushed, iclass 7, count 2 2006.257.22:16:05.54#ibcon#about to write, iclass 7, count 2 2006.257.22:16:05.54#ibcon#wrote, iclass 7, count 2 2006.257.22:16:05.54#ibcon#about to read 3, iclass 7, count 2 2006.257.22:16:05.56#ibcon#read 3, iclass 7, count 2 2006.257.22:16:05.56#ibcon#about to read 4, iclass 7, count 2 2006.257.22:16:05.56#ibcon#read 4, iclass 7, count 2 2006.257.22:16:05.56#ibcon#about to read 5, iclass 7, count 2 2006.257.22:16:05.56#ibcon#read 5, iclass 7, count 2 2006.257.22:16:05.56#ibcon#about to read 6, iclass 7, count 2 2006.257.22:16:05.56#ibcon#read 6, iclass 7, count 2 2006.257.22:16:05.56#ibcon#end of sib2, iclass 7, count 2 2006.257.22:16:05.56#ibcon#*mode == 0, iclass 7, count 2 2006.257.22:16:05.56#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.22:16:05.56#ibcon#[25=AT07-04\r\n] 2006.257.22:16:05.56#ibcon#*before write, iclass 7, count 2 2006.257.22:16:05.56#ibcon#enter sib2, iclass 7, count 2 2006.257.22:16:05.56#ibcon#flushed, iclass 7, count 2 2006.257.22:16:05.56#ibcon#about to write, iclass 7, count 2 2006.257.22:16:05.56#ibcon#wrote, iclass 7, count 2 2006.257.22:16:05.56#ibcon#about to read 3, iclass 7, count 2 2006.257.22:16:05.59#ibcon#read 3, iclass 7, count 2 2006.257.22:16:05.59#ibcon#about to read 4, iclass 7, count 2 2006.257.22:16:05.59#ibcon#read 4, iclass 7, count 2 2006.257.22:16:05.59#ibcon#about to read 5, iclass 7, count 2 2006.257.22:16:05.59#ibcon#read 5, iclass 7, count 2 2006.257.22:16:05.59#ibcon#about to read 6, iclass 7, count 2 2006.257.22:16:05.59#ibcon#read 6, iclass 7, count 2 2006.257.22:16:05.59#ibcon#end of sib2, iclass 7, count 2 2006.257.22:16:05.59#ibcon#*after write, iclass 7, count 2 2006.257.22:16:05.59#ibcon#*before return 0, iclass 7, count 2 2006.257.22:16:05.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:05.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:05.59#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.22:16:05.59#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:05.59#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:05.71#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:05.71#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:05.71#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:16:05.71#ibcon#first serial, iclass 7, count 0 2006.257.22:16:05.71#ibcon#enter sib2, iclass 7, count 0 2006.257.22:16:05.71#ibcon#flushed, iclass 7, count 0 2006.257.22:16:05.71#ibcon#about to write, iclass 7, count 0 2006.257.22:16:05.71#ibcon#wrote, iclass 7, count 0 2006.257.22:16:05.71#ibcon#about to read 3, iclass 7, count 0 2006.257.22:16:05.73#ibcon#read 3, iclass 7, count 0 2006.257.22:16:05.73#ibcon#about to read 4, iclass 7, count 0 2006.257.22:16:05.73#ibcon#read 4, iclass 7, count 0 2006.257.22:16:05.73#ibcon#about to read 5, iclass 7, count 0 2006.257.22:16:05.73#ibcon#read 5, iclass 7, count 0 2006.257.22:16:05.73#ibcon#about to read 6, iclass 7, count 0 2006.257.22:16:05.73#ibcon#read 6, iclass 7, count 0 2006.257.22:16:05.73#ibcon#end of sib2, iclass 7, count 0 2006.257.22:16:05.73#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:16:05.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:16:05.73#ibcon#[25=USB\r\n] 2006.257.22:16:05.73#ibcon#*before write, iclass 7, count 0 2006.257.22:16:05.73#ibcon#enter sib2, iclass 7, count 0 2006.257.22:16:05.73#ibcon#flushed, iclass 7, count 0 2006.257.22:16:05.73#ibcon#about to write, iclass 7, count 0 2006.257.22:16:05.73#ibcon#wrote, iclass 7, count 0 2006.257.22:16:05.73#ibcon#about to read 3, iclass 7, count 0 2006.257.22:16:05.76#ibcon#read 3, iclass 7, count 0 2006.257.22:16:05.76#ibcon#about to read 4, iclass 7, count 0 2006.257.22:16:05.76#ibcon#read 4, iclass 7, count 0 2006.257.22:16:05.76#ibcon#about to read 5, iclass 7, count 0 2006.257.22:16:05.76#ibcon#read 5, iclass 7, count 0 2006.257.22:16:05.76#ibcon#about to read 6, iclass 7, count 0 2006.257.22:16:05.76#ibcon#read 6, iclass 7, count 0 2006.257.22:16:05.76#ibcon#end of sib2, iclass 7, count 0 2006.257.22:16:05.76#ibcon#*after write, iclass 7, count 0 2006.257.22:16:05.76#ibcon#*before return 0, iclass 7, count 0 2006.257.22:16:05.76#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:05.76#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:05.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:16:05.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:16:05.77$vck44/valo=8,884.99 2006.257.22:16:05.77#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.22:16:05.77#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.22:16:05.77#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:05.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:05.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:05.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:05.77#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:16:05.77#ibcon#first serial, iclass 11, count 0 2006.257.22:16:05.77#ibcon#enter sib2, iclass 11, count 0 2006.257.22:16:05.77#ibcon#flushed, iclass 11, count 0 2006.257.22:16:05.77#ibcon#about to write, iclass 11, count 0 2006.257.22:16:05.77#ibcon#wrote, iclass 11, count 0 2006.257.22:16:05.77#ibcon#about to read 3, iclass 11, count 0 2006.257.22:16:05.78#ibcon#read 3, iclass 11, count 0 2006.257.22:16:05.78#ibcon#about to read 4, iclass 11, count 0 2006.257.22:16:05.78#ibcon#read 4, iclass 11, count 0 2006.257.22:16:05.78#ibcon#about to read 5, iclass 11, count 0 2006.257.22:16:05.78#ibcon#read 5, iclass 11, count 0 2006.257.22:16:05.78#ibcon#about to read 6, iclass 11, count 0 2006.257.22:16:05.78#ibcon#read 6, iclass 11, count 0 2006.257.22:16:05.78#ibcon#end of sib2, iclass 11, count 0 2006.257.22:16:05.78#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:16:05.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:16:05.78#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.22:16:05.78#ibcon#*before write, iclass 11, count 0 2006.257.22:16:05.78#ibcon#enter sib2, iclass 11, count 0 2006.257.22:16:05.78#ibcon#flushed, iclass 11, count 0 2006.257.22:16:05.78#ibcon#about to write, iclass 11, count 0 2006.257.22:16:05.78#ibcon#wrote, iclass 11, count 0 2006.257.22:16:05.78#ibcon#about to read 3, iclass 11, count 0 2006.257.22:16:05.82#ibcon#read 3, iclass 11, count 0 2006.257.22:16:05.82#ibcon#about to read 4, iclass 11, count 0 2006.257.22:16:05.82#ibcon#read 4, iclass 11, count 0 2006.257.22:16:05.82#ibcon#about to read 5, iclass 11, count 0 2006.257.22:16:05.82#ibcon#read 5, iclass 11, count 0 2006.257.22:16:05.82#ibcon#about to read 6, iclass 11, count 0 2006.257.22:16:05.82#ibcon#read 6, iclass 11, count 0 2006.257.22:16:05.82#ibcon#end of sib2, iclass 11, count 0 2006.257.22:16:05.82#ibcon#*after write, iclass 11, count 0 2006.257.22:16:05.82#ibcon#*before return 0, iclass 11, count 0 2006.257.22:16:05.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:05.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:05.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:16:05.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:16:05.83$vck44/va=8,4 2006.257.22:16:05.83#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.22:16:05.83#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.22:16:05.83#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:05.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:05.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:05.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:05.87#ibcon#enter wrdev, iclass 13, count 2 2006.257.22:16:05.87#ibcon#first serial, iclass 13, count 2 2006.257.22:16:05.87#ibcon#enter sib2, iclass 13, count 2 2006.257.22:16:05.87#ibcon#flushed, iclass 13, count 2 2006.257.22:16:05.87#ibcon#about to write, iclass 13, count 2 2006.257.22:16:05.87#ibcon#wrote, iclass 13, count 2 2006.257.22:16:05.87#ibcon#about to read 3, iclass 13, count 2 2006.257.22:16:05.89#ibcon#read 3, iclass 13, count 2 2006.257.22:16:05.89#ibcon#about to read 4, iclass 13, count 2 2006.257.22:16:05.89#ibcon#read 4, iclass 13, count 2 2006.257.22:16:05.89#ibcon#about to read 5, iclass 13, count 2 2006.257.22:16:05.89#ibcon#read 5, iclass 13, count 2 2006.257.22:16:05.89#ibcon#about to read 6, iclass 13, count 2 2006.257.22:16:05.89#ibcon#read 6, iclass 13, count 2 2006.257.22:16:05.89#ibcon#end of sib2, iclass 13, count 2 2006.257.22:16:05.89#ibcon#*mode == 0, iclass 13, count 2 2006.257.22:16:05.89#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.22:16:05.89#ibcon#[25=AT08-04\r\n] 2006.257.22:16:05.89#ibcon#*before write, iclass 13, count 2 2006.257.22:16:05.89#ibcon#enter sib2, iclass 13, count 2 2006.257.22:16:05.89#ibcon#flushed, iclass 13, count 2 2006.257.22:16:05.89#ibcon#about to write, iclass 13, count 2 2006.257.22:16:05.89#ibcon#wrote, iclass 13, count 2 2006.257.22:16:05.89#ibcon#about to read 3, iclass 13, count 2 2006.257.22:16:05.92#ibcon#read 3, iclass 13, count 2 2006.257.22:16:05.92#ibcon#about to read 4, iclass 13, count 2 2006.257.22:16:05.92#ibcon#read 4, iclass 13, count 2 2006.257.22:16:05.92#ibcon#about to read 5, iclass 13, count 2 2006.257.22:16:05.92#ibcon#read 5, iclass 13, count 2 2006.257.22:16:05.92#ibcon#about to read 6, iclass 13, count 2 2006.257.22:16:05.92#ibcon#read 6, iclass 13, count 2 2006.257.22:16:05.92#ibcon#end of sib2, iclass 13, count 2 2006.257.22:16:05.92#ibcon#*after write, iclass 13, count 2 2006.257.22:16:05.92#ibcon#*before return 0, iclass 13, count 2 2006.257.22:16:05.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:05.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:05.92#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.22:16:05.92#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:05.92#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:06.04#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:06.04#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:06.04#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:16:06.04#ibcon#first serial, iclass 13, count 0 2006.257.22:16:06.04#ibcon#enter sib2, iclass 13, count 0 2006.257.22:16:06.04#ibcon#flushed, iclass 13, count 0 2006.257.22:16:06.04#ibcon#about to write, iclass 13, count 0 2006.257.22:16:06.04#ibcon#wrote, iclass 13, count 0 2006.257.22:16:06.04#ibcon#about to read 3, iclass 13, count 0 2006.257.22:16:06.06#ibcon#read 3, iclass 13, count 0 2006.257.22:16:06.06#ibcon#about to read 4, iclass 13, count 0 2006.257.22:16:06.06#ibcon#read 4, iclass 13, count 0 2006.257.22:16:06.06#ibcon#about to read 5, iclass 13, count 0 2006.257.22:16:06.06#ibcon#read 5, iclass 13, count 0 2006.257.22:16:06.06#ibcon#about to read 6, iclass 13, count 0 2006.257.22:16:06.06#ibcon#read 6, iclass 13, count 0 2006.257.22:16:06.06#ibcon#end of sib2, iclass 13, count 0 2006.257.22:16:06.06#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:16:06.06#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:16:06.06#ibcon#[25=USB\r\n] 2006.257.22:16:06.06#ibcon#*before write, iclass 13, count 0 2006.257.22:16:06.06#ibcon#enter sib2, iclass 13, count 0 2006.257.22:16:06.06#ibcon#flushed, iclass 13, count 0 2006.257.22:16:06.06#ibcon#about to write, iclass 13, count 0 2006.257.22:16:06.06#ibcon#wrote, iclass 13, count 0 2006.257.22:16:06.06#ibcon#about to read 3, iclass 13, count 0 2006.257.22:16:06.09#ibcon#read 3, iclass 13, count 0 2006.257.22:16:06.09#ibcon#about to read 4, iclass 13, count 0 2006.257.22:16:06.09#ibcon#read 4, iclass 13, count 0 2006.257.22:16:06.09#ibcon#about to read 5, iclass 13, count 0 2006.257.22:16:06.09#ibcon#read 5, iclass 13, count 0 2006.257.22:16:06.09#ibcon#about to read 6, iclass 13, count 0 2006.257.22:16:06.09#ibcon#read 6, iclass 13, count 0 2006.257.22:16:06.09#ibcon#end of sib2, iclass 13, count 0 2006.257.22:16:06.09#ibcon#*after write, iclass 13, count 0 2006.257.22:16:06.09#ibcon#*before return 0, iclass 13, count 0 2006.257.22:16:06.09#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:06.09#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:06.09#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:16:06.09#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:16:06.10$vck44/vblo=1,629.99 2006.257.22:16:06.10#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.22:16:06.10#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.22:16:06.10#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:06.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:06.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:06.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:06.10#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:16:06.10#ibcon#first serial, iclass 15, count 0 2006.257.22:16:06.10#ibcon#enter sib2, iclass 15, count 0 2006.257.22:16:06.10#ibcon#flushed, iclass 15, count 0 2006.257.22:16:06.10#ibcon#about to write, iclass 15, count 0 2006.257.22:16:06.10#ibcon#wrote, iclass 15, count 0 2006.257.22:16:06.10#ibcon#about to read 3, iclass 15, count 0 2006.257.22:16:06.11#ibcon#read 3, iclass 15, count 0 2006.257.22:16:06.11#ibcon#about to read 4, iclass 15, count 0 2006.257.22:16:06.11#ibcon#read 4, iclass 15, count 0 2006.257.22:16:06.11#ibcon#about to read 5, iclass 15, count 0 2006.257.22:16:06.11#ibcon#read 5, iclass 15, count 0 2006.257.22:16:06.11#ibcon#about to read 6, iclass 15, count 0 2006.257.22:16:06.11#ibcon#read 6, iclass 15, count 0 2006.257.22:16:06.11#ibcon#end of sib2, iclass 15, count 0 2006.257.22:16:06.11#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:16:06.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:16:06.11#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.22:16:06.11#ibcon#*before write, iclass 15, count 0 2006.257.22:16:06.11#ibcon#enter sib2, iclass 15, count 0 2006.257.22:16:06.11#ibcon#flushed, iclass 15, count 0 2006.257.22:16:06.11#ibcon#about to write, iclass 15, count 0 2006.257.22:16:06.11#ibcon#wrote, iclass 15, count 0 2006.257.22:16:06.11#ibcon#about to read 3, iclass 15, count 0 2006.257.22:16:06.15#ibcon#read 3, iclass 15, count 0 2006.257.22:16:06.15#ibcon#about to read 4, iclass 15, count 0 2006.257.22:16:06.15#ibcon#read 4, iclass 15, count 0 2006.257.22:16:06.15#ibcon#about to read 5, iclass 15, count 0 2006.257.22:16:06.15#ibcon#read 5, iclass 15, count 0 2006.257.22:16:06.15#ibcon#about to read 6, iclass 15, count 0 2006.257.22:16:06.15#ibcon#read 6, iclass 15, count 0 2006.257.22:16:06.15#ibcon#end of sib2, iclass 15, count 0 2006.257.22:16:06.15#ibcon#*after write, iclass 15, count 0 2006.257.22:16:06.15#ibcon#*before return 0, iclass 15, count 0 2006.257.22:16:06.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:06.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:06.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:16:06.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:16:06.16$vck44/vb=1,4 2006.257.22:16:06.16#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.22:16:06.16#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.22:16:06.16#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:06.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:16:06.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:16:06.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:16:06.16#ibcon#enter wrdev, iclass 17, count 2 2006.257.22:16:06.16#ibcon#first serial, iclass 17, count 2 2006.257.22:16:06.16#ibcon#enter sib2, iclass 17, count 2 2006.257.22:16:06.16#ibcon#flushed, iclass 17, count 2 2006.257.22:16:06.16#ibcon#about to write, iclass 17, count 2 2006.257.22:16:06.16#ibcon#wrote, iclass 17, count 2 2006.257.22:16:06.16#ibcon#about to read 3, iclass 17, count 2 2006.257.22:16:06.17#ibcon#read 3, iclass 17, count 2 2006.257.22:16:06.17#ibcon#about to read 4, iclass 17, count 2 2006.257.22:16:06.17#ibcon#read 4, iclass 17, count 2 2006.257.22:16:06.17#ibcon#about to read 5, iclass 17, count 2 2006.257.22:16:06.17#ibcon#read 5, iclass 17, count 2 2006.257.22:16:06.17#ibcon#about to read 6, iclass 17, count 2 2006.257.22:16:06.17#ibcon#read 6, iclass 17, count 2 2006.257.22:16:06.17#ibcon#end of sib2, iclass 17, count 2 2006.257.22:16:06.17#ibcon#*mode == 0, iclass 17, count 2 2006.257.22:16:06.17#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.22:16:06.17#ibcon#[27=AT01-04\r\n] 2006.257.22:16:06.17#ibcon#*before write, iclass 17, count 2 2006.257.22:16:06.17#ibcon#enter sib2, iclass 17, count 2 2006.257.22:16:06.17#ibcon#flushed, iclass 17, count 2 2006.257.22:16:06.17#ibcon#about to write, iclass 17, count 2 2006.257.22:16:06.17#ibcon#wrote, iclass 17, count 2 2006.257.22:16:06.17#ibcon#about to read 3, iclass 17, count 2 2006.257.22:16:06.20#ibcon#read 3, iclass 17, count 2 2006.257.22:16:06.20#ibcon#about to read 4, iclass 17, count 2 2006.257.22:16:06.20#ibcon#read 4, iclass 17, count 2 2006.257.22:16:06.20#ibcon#about to read 5, iclass 17, count 2 2006.257.22:16:06.20#ibcon#read 5, iclass 17, count 2 2006.257.22:16:06.20#ibcon#about to read 6, iclass 17, count 2 2006.257.22:16:06.20#ibcon#read 6, iclass 17, count 2 2006.257.22:16:06.20#ibcon#end of sib2, iclass 17, count 2 2006.257.22:16:06.20#ibcon#*after write, iclass 17, count 2 2006.257.22:16:06.20#ibcon#*before return 0, iclass 17, count 2 2006.257.22:16:06.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:16:06.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:16:06.20#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.22:16:06.20#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:06.20#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:16:06.32#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:16:06.32#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:16:06.32#ibcon#enter wrdev, iclass 17, count 0 2006.257.22:16:06.32#ibcon#first serial, iclass 17, count 0 2006.257.22:16:06.32#ibcon#enter sib2, iclass 17, count 0 2006.257.22:16:06.32#ibcon#flushed, iclass 17, count 0 2006.257.22:16:06.32#ibcon#about to write, iclass 17, count 0 2006.257.22:16:06.32#ibcon#wrote, iclass 17, count 0 2006.257.22:16:06.32#ibcon#about to read 3, iclass 17, count 0 2006.257.22:16:06.34#ibcon#read 3, iclass 17, count 0 2006.257.22:16:06.34#ibcon#about to read 4, iclass 17, count 0 2006.257.22:16:06.34#ibcon#read 4, iclass 17, count 0 2006.257.22:16:06.34#ibcon#about to read 5, iclass 17, count 0 2006.257.22:16:06.34#ibcon#read 5, iclass 17, count 0 2006.257.22:16:06.34#ibcon#about to read 6, iclass 17, count 0 2006.257.22:16:06.34#ibcon#read 6, iclass 17, count 0 2006.257.22:16:06.34#ibcon#end of sib2, iclass 17, count 0 2006.257.22:16:06.34#ibcon#*mode == 0, iclass 17, count 0 2006.257.22:16:06.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.22:16:06.34#ibcon#[27=USB\r\n] 2006.257.22:16:06.34#ibcon#*before write, iclass 17, count 0 2006.257.22:16:06.34#ibcon#enter sib2, iclass 17, count 0 2006.257.22:16:06.34#ibcon#flushed, iclass 17, count 0 2006.257.22:16:06.34#ibcon#about to write, iclass 17, count 0 2006.257.22:16:06.34#ibcon#wrote, iclass 17, count 0 2006.257.22:16:06.34#ibcon#about to read 3, iclass 17, count 0 2006.257.22:16:06.37#ibcon#read 3, iclass 17, count 0 2006.257.22:16:06.37#ibcon#about to read 4, iclass 17, count 0 2006.257.22:16:06.37#ibcon#read 4, iclass 17, count 0 2006.257.22:16:06.37#ibcon#about to read 5, iclass 17, count 0 2006.257.22:16:06.37#ibcon#read 5, iclass 17, count 0 2006.257.22:16:06.37#ibcon#about to read 6, iclass 17, count 0 2006.257.22:16:06.37#ibcon#read 6, iclass 17, count 0 2006.257.22:16:06.37#ibcon#end of sib2, iclass 17, count 0 2006.257.22:16:06.37#ibcon#*after write, iclass 17, count 0 2006.257.22:16:06.37#ibcon#*before return 0, iclass 17, count 0 2006.257.22:16:06.37#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:16:06.37#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:16:06.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.22:16:06.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.22:16:06.38$vck44/vblo=2,634.99 2006.257.22:16:06.38#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.22:16:06.38#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.22:16:06.38#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:06.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:06.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:06.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:06.38#ibcon#enter wrdev, iclass 19, count 0 2006.257.22:16:06.38#ibcon#first serial, iclass 19, count 0 2006.257.22:16:06.38#ibcon#enter sib2, iclass 19, count 0 2006.257.22:16:06.38#ibcon#flushed, iclass 19, count 0 2006.257.22:16:06.38#ibcon#about to write, iclass 19, count 0 2006.257.22:16:06.38#ibcon#wrote, iclass 19, count 0 2006.257.22:16:06.38#ibcon#about to read 3, iclass 19, count 0 2006.257.22:16:06.39#ibcon#read 3, iclass 19, count 0 2006.257.22:16:06.39#ibcon#about to read 4, iclass 19, count 0 2006.257.22:16:06.39#ibcon#read 4, iclass 19, count 0 2006.257.22:16:06.39#ibcon#about to read 5, iclass 19, count 0 2006.257.22:16:06.39#ibcon#read 5, iclass 19, count 0 2006.257.22:16:06.39#ibcon#about to read 6, iclass 19, count 0 2006.257.22:16:06.39#ibcon#read 6, iclass 19, count 0 2006.257.22:16:06.39#ibcon#end of sib2, iclass 19, count 0 2006.257.22:16:06.39#ibcon#*mode == 0, iclass 19, count 0 2006.257.22:16:06.39#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.22:16:06.39#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.22:16:06.39#ibcon#*before write, iclass 19, count 0 2006.257.22:16:06.39#ibcon#enter sib2, iclass 19, count 0 2006.257.22:16:06.39#ibcon#flushed, iclass 19, count 0 2006.257.22:16:06.39#ibcon#about to write, iclass 19, count 0 2006.257.22:16:06.39#ibcon#wrote, iclass 19, count 0 2006.257.22:16:06.39#ibcon#about to read 3, iclass 19, count 0 2006.257.22:16:06.43#ibcon#read 3, iclass 19, count 0 2006.257.22:16:06.43#ibcon#about to read 4, iclass 19, count 0 2006.257.22:16:06.43#ibcon#read 4, iclass 19, count 0 2006.257.22:16:06.43#ibcon#about to read 5, iclass 19, count 0 2006.257.22:16:06.43#ibcon#read 5, iclass 19, count 0 2006.257.22:16:06.43#ibcon#about to read 6, iclass 19, count 0 2006.257.22:16:06.43#ibcon#read 6, iclass 19, count 0 2006.257.22:16:06.43#ibcon#end of sib2, iclass 19, count 0 2006.257.22:16:06.43#ibcon#*after write, iclass 19, count 0 2006.257.22:16:06.43#ibcon#*before return 0, iclass 19, count 0 2006.257.22:16:06.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:06.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:16:06.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.22:16:06.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.22:16:06.44$vck44/vb=2,5 2006.257.22:16:06.44#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.22:16:06.44#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.22:16:06.44#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:06.44#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:06.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:06.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:06.48#ibcon#enter wrdev, iclass 21, count 2 2006.257.22:16:06.48#ibcon#first serial, iclass 21, count 2 2006.257.22:16:06.48#ibcon#enter sib2, iclass 21, count 2 2006.257.22:16:06.48#ibcon#flushed, iclass 21, count 2 2006.257.22:16:06.48#ibcon#about to write, iclass 21, count 2 2006.257.22:16:06.48#ibcon#wrote, iclass 21, count 2 2006.257.22:16:06.48#ibcon#about to read 3, iclass 21, count 2 2006.257.22:16:06.50#ibcon#read 3, iclass 21, count 2 2006.257.22:16:06.50#ibcon#about to read 4, iclass 21, count 2 2006.257.22:16:06.50#ibcon#read 4, iclass 21, count 2 2006.257.22:16:06.50#ibcon#about to read 5, iclass 21, count 2 2006.257.22:16:06.50#ibcon#read 5, iclass 21, count 2 2006.257.22:16:06.50#ibcon#about to read 6, iclass 21, count 2 2006.257.22:16:06.50#ibcon#read 6, iclass 21, count 2 2006.257.22:16:06.50#ibcon#end of sib2, iclass 21, count 2 2006.257.22:16:06.50#ibcon#*mode == 0, iclass 21, count 2 2006.257.22:16:06.50#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.22:16:06.50#ibcon#[27=AT02-05\r\n] 2006.257.22:16:06.50#ibcon#*before write, iclass 21, count 2 2006.257.22:16:06.50#ibcon#enter sib2, iclass 21, count 2 2006.257.22:16:06.50#ibcon#flushed, iclass 21, count 2 2006.257.22:16:06.50#ibcon#about to write, iclass 21, count 2 2006.257.22:16:06.50#ibcon#wrote, iclass 21, count 2 2006.257.22:16:06.50#ibcon#about to read 3, iclass 21, count 2 2006.257.22:16:06.53#ibcon#read 3, iclass 21, count 2 2006.257.22:16:06.53#ibcon#about to read 4, iclass 21, count 2 2006.257.22:16:06.53#ibcon#read 4, iclass 21, count 2 2006.257.22:16:06.53#ibcon#about to read 5, iclass 21, count 2 2006.257.22:16:06.53#ibcon#read 5, iclass 21, count 2 2006.257.22:16:06.53#ibcon#about to read 6, iclass 21, count 2 2006.257.22:16:06.53#ibcon#read 6, iclass 21, count 2 2006.257.22:16:06.53#ibcon#end of sib2, iclass 21, count 2 2006.257.22:16:06.53#ibcon#*after write, iclass 21, count 2 2006.257.22:16:06.53#ibcon#*before return 0, iclass 21, count 2 2006.257.22:16:06.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:06.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:16:06.53#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.22:16:06.53#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:06.53#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:06.65#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:06.65#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:06.65#ibcon#enter wrdev, iclass 21, count 0 2006.257.22:16:06.65#ibcon#first serial, iclass 21, count 0 2006.257.22:16:06.65#ibcon#enter sib2, iclass 21, count 0 2006.257.22:16:06.65#ibcon#flushed, iclass 21, count 0 2006.257.22:16:06.65#ibcon#about to write, iclass 21, count 0 2006.257.22:16:06.65#ibcon#wrote, iclass 21, count 0 2006.257.22:16:06.65#ibcon#about to read 3, iclass 21, count 0 2006.257.22:16:06.67#ibcon#read 3, iclass 21, count 0 2006.257.22:16:06.67#ibcon#about to read 4, iclass 21, count 0 2006.257.22:16:06.67#ibcon#read 4, iclass 21, count 0 2006.257.22:16:06.67#ibcon#about to read 5, iclass 21, count 0 2006.257.22:16:06.67#ibcon#read 5, iclass 21, count 0 2006.257.22:16:06.67#ibcon#about to read 6, iclass 21, count 0 2006.257.22:16:06.67#ibcon#read 6, iclass 21, count 0 2006.257.22:16:06.67#ibcon#end of sib2, iclass 21, count 0 2006.257.22:16:06.67#ibcon#*mode == 0, iclass 21, count 0 2006.257.22:16:06.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.22:16:06.67#ibcon#[27=USB\r\n] 2006.257.22:16:06.67#ibcon#*before write, iclass 21, count 0 2006.257.22:16:06.67#ibcon#enter sib2, iclass 21, count 0 2006.257.22:16:06.67#ibcon#flushed, iclass 21, count 0 2006.257.22:16:06.67#ibcon#about to write, iclass 21, count 0 2006.257.22:16:06.67#ibcon#wrote, iclass 21, count 0 2006.257.22:16:06.67#ibcon#about to read 3, iclass 21, count 0 2006.257.22:16:06.70#ibcon#read 3, iclass 21, count 0 2006.257.22:16:06.70#ibcon#about to read 4, iclass 21, count 0 2006.257.22:16:06.70#ibcon#read 4, iclass 21, count 0 2006.257.22:16:06.70#ibcon#about to read 5, iclass 21, count 0 2006.257.22:16:06.70#ibcon#read 5, iclass 21, count 0 2006.257.22:16:06.70#ibcon#about to read 6, iclass 21, count 0 2006.257.22:16:06.70#ibcon#read 6, iclass 21, count 0 2006.257.22:16:06.70#ibcon#end of sib2, iclass 21, count 0 2006.257.22:16:06.70#ibcon#*after write, iclass 21, count 0 2006.257.22:16:06.70#ibcon#*before return 0, iclass 21, count 0 2006.257.22:16:06.70#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:06.70#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:16:06.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.22:16:06.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.22:16:06.71$vck44/vblo=3,649.99 2006.257.22:16:06.71#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.22:16:06.71#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.22:16:06.71#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:06.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:06.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:06.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:06.71#ibcon#enter wrdev, iclass 23, count 0 2006.257.22:16:06.71#ibcon#first serial, iclass 23, count 0 2006.257.22:16:06.71#ibcon#enter sib2, iclass 23, count 0 2006.257.22:16:06.71#ibcon#flushed, iclass 23, count 0 2006.257.22:16:06.71#ibcon#about to write, iclass 23, count 0 2006.257.22:16:06.71#ibcon#wrote, iclass 23, count 0 2006.257.22:16:06.71#ibcon#about to read 3, iclass 23, count 0 2006.257.22:16:06.72#ibcon#read 3, iclass 23, count 0 2006.257.22:16:06.72#ibcon#about to read 4, iclass 23, count 0 2006.257.22:16:06.72#ibcon#read 4, iclass 23, count 0 2006.257.22:16:06.72#ibcon#about to read 5, iclass 23, count 0 2006.257.22:16:06.72#ibcon#read 5, iclass 23, count 0 2006.257.22:16:06.72#ibcon#about to read 6, iclass 23, count 0 2006.257.22:16:06.72#ibcon#read 6, iclass 23, count 0 2006.257.22:16:06.72#ibcon#end of sib2, iclass 23, count 0 2006.257.22:16:06.72#ibcon#*mode == 0, iclass 23, count 0 2006.257.22:16:06.72#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.22:16:06.72#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.22:16:06.72#ibcon#*before write, iclass 23, count 0 2006.257.22:16:06.72#ibcon#enter sib2, iclass 23, count 0 2006.257.22:16:06.72#ibcon#flushed, iclass 23, count 0 2006.257.22:16:06.72#ibcon#about to write, iclass 23, count 0 2006.257.22:16:06.72#ibcon#wrote, iclass 23, count 0 2006.257.22:16:06.72#ibcon#about to read 3, iclass 23, count 0 2006.257.22:16:06.76#ibcon#read 3, iclass 23, count 0 2006.257.22:16:06.76#ibcon#about to read 4, iclass 23, count 0 2006.257.22:16:06.76#ibcon#read 4, iclass 23, count 0 2006.257.22:16:06.76#ibcon#about to read 5, iclass 23, count 0 2006.257.22:16:06.76#ibcon#read 5, iclass 23, count 0 2006.257.22:16:06.76#ibcon#about to read 6, iclass 23, count 0 2006.257.22:16:06.76#ibcon#read 6, iclass 23, count 0 2006.257.22:16:06.76#ibcon#end of sib2, iclass 23, count 0 2006.257.22:16:06.76#ibcon#*after write, iclass 23, count 0 2006.257.22:16:06.76#ibcon#*before return 0, iclass 23, count 0 2006.257.22:16:06.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:06.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:16:06.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.22:16:06.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.22:16:06.77$vck44/vb=3,4 2006.257.22:16:06.77#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.22:16:06.77#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.22:16:06.77#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:06.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:06.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:06.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:06.81#ibcon#enter wrdev, iclass 25, count 2 2006.257.22:16:06.81#ibcon#first serial, iclass 25, count 2 2006.257.22:16:06.81#ibcon#enter sib2, iclass 25, count 2 2006.257.22:16:06.81#ibcon#flushed, iclass 25, count 2 2006.257.22:16:06.81#ibcon#about to write, iclass 25, count 2 2006.257.22:16:06.81#ibcon#wrote, iclass 25, count 2 2006.257.22:16:06.81#ibcon#about to read 3, iclass 25, count 2 2006.257.22:16:06.83#ibcon#read 3, iclass 25, count 2 2006.257.22:16:06.83#ibcon#about to read 4, iclass 25, count 2 2006.257.22:16:06.83#ibcon#read 4, iclass 25, count 2 2006.257.22:16:06.83#ibcon#about to read 5, iclass 25, count 2 2006.257.22:16:06.83#ibcon#read 5, iclass 25, count 2 2006.257.22:16:06.83#ibcon#about to read 6, iclass 25, count 2 2006.257.22:16:06.83#ibcon#read 6, iclass 25, count 2 2006.257.22:16:06.83#ibcon#end of sib2, iclass 25, count 2 2006.257.22:16:06.83#ibcon#*mode == 0, iclass 25, count 2 2006.257.22:16:06.83#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.22:16:06.83#ibcon#[27=AT03-04\r\n] 2006.257.22:16:06.83#ibcon#*before write, iclass 25, count 2 2006.257.22:16:06.83#ibcon#enter sib2, iclass 25, count 2 2006.257.22:16:06.83#ibcon#flushed, iclass 25, count 2 2006.257.22:16:06.83#ibcon#about to write, iclass 25, count 2 2006.257.22:16:06.83#ibcon#wrote, iclass 25, count 2 2006.257.22:16:06.83#ibcon#about to read 3, iclass 25, count 2 2006.257.22:16:06.86#ibcon#read 3, iclass 25, count 2 2006.257.22:16:06.86#ibcon#about to read 4, iclass 25, count 2 2006.257.22:16:06.86#ibcon#read 4, iclass 25, count 2 2006.257.22:16:06.86#ibcon#about to read 5, iclass 25, count 2 2006.257.22:16:06.86#ibcon#read 5, iclass 25, count 2 2006.257.22:16:06.86#ibcon#about to read 6, iclass 25, count 2 2006.257.22:16:06.86#ibcon#read 6, iclass 25, count 2 2006.257.22:16:06.86#ibcon#end of sib2, iclass 25, count 2 2006.257.22:16:06.86#ibcon#*after write, iclass 25, count 2 2006.257.22:16:06.86#ibcon#*before return 0, iclass 25, count 2 2006.257.22:16:06.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:06.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:16:06.86#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.22:16:06.86#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:06.86#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:06.98#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:06.98#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:06.98#ibcon#enter wrdev, iclass 25, count 0 2006.257.22:16:06.98#ibcon#first serial, iclass 25, count 0 2006.257.22:16:06.98#ibcon#enter sib2, iclass 25, count 0 2006.257.22:16:06.98#ibcon#flushed, iclass 25, count 0 2006.257.22:16:06.98#ibcon#about to write, iclass 25, count 0 2006.257.22:16:06.98#ibcon#wrote, iclass 25, count 0 2006.257.22:16:06.98#ibcon#about to read 3, iclass 25, count 0 2006.257.22:16:07.00#ibcon#read 3, iclass 25, count 0 2006.257.22:16:07.00#ibcon#about to read 4, iclass 25, count 0 2006.257.22:16:07.00#ibcon#read 4, iclass 25, count 0 2006.257.22:16:07.00#ibcon#about to read 5, iclass 25, count 0 2006.257.22:16:07.00#ibcon#read 5, iclass 25, count 0 2006.257.22:16:07.00#ibcon#about to read 6, iclass 25, count 0 2006.257.22:16:07.00#ibcon#read 6, iclass 25, count 0 2006.257.22:16:07.00#ibcon#end of sib2, iclass 25, count 0 2006.257.22:16:07.00#ibcon#*mode == 0, iclass 25, count 0 2006.257.22:16:07.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.22:16:07.00#ibcon#[27=USB\r\n] 2006.257.22:16:07.00#ibcon#*before write, iclass 25, count 0 2006.257.22:16:07.00#ibcon#enter sib2, iclass 25, count 0 2006.257.22:16:07.00#ibcon#flushed, iclass 25, count 0 2006.257.22:16:07.00#ibcon#about to write, iclass 25, count 0 2006.257.22:16:07.00#ibcon#wrote, iclass 25, count 0 2006.257.22:16:07.00#ibcon#about to read 3, iclass 25, count 0 2006.257.22:16:07.03#ibcon#read 3, iclass 25, count 0 2006.257.22:16:07.03#ibcon#about to read 4, iclass 25, count 0 2006.257.22:16:07.03#ibcon#read 4, iclass 25, count 0 2006.257.22:16:07.03#ibcon#about to read 5, iclass 25, count 0 2006.257.22:16:07.03#ibcon#read 5, iclass 25, count 0 2006.257.22:16:07.03#ibcon#about to read 6, iclass 25, count 0 2006.257.22:16:07.03#ibcon#read 6, iclass 25, count 0 2006.257.22:16:07.03#ibcon#end of sib2, iclass 25, count 0 2006.257.22:16:07.03#ibcon#*after write, iclass 25, count 0 2006.257.22:16:07.03#ibcon#*before return 0, iclass 25, count 0 2006.257.22:16:07.03#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:07.03#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:16:07.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.22:16:07.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.22:16:07.04$vck44/vblo=4,679.99 2006.257.22:16:07.04#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.22:16:07.04#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.22:16:07.04#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:07.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:07.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:07.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:07.04#ibcon#enter wrdev, iclass 27, count 0 2006.257.22:16:07.04#ibcon#first serial, iclass 27, count 0 2006.257.22:16:07.04#ibcon#enter sib2, iclass 27, count 0 2006.257.22:16:07.04#ibcon#flushed, iclass 27, count 0 2006.257.22:16:07.04#ibcon#about to write, iclass 27, count 0 2006.257.22:16:07.04#ibcon#wrote, iclass 27, count 0 2006.257.22:16:07.04#ibcon#about to read 3, iclass 27, count 0 2006.257.22:16:07.05#ibcon#read 3, iclass 27, count 0 2006.257.22:16:07.05#ibcon#about to read 4, iclass 27, count 0 2006.257.22:16:07.05#ibcon#read 4, iclass 27, count 0 2006.257.22:16:07.05#ibcon#about to read 5, iclass 27, count 0 2006.257.22:16:07.05#ibcon#read 5, iclass 27, count 0 2006.257.22:16:07.05#ibcon#about to read 6, iclass 27, count 0 2006.257.22:16:07.05#ibcon#read 6, iclass 27, count 0 2006.257.22:16:07.05#ibcon#end of sib2, iclass 27, count 0 2006.257.22:16:07.05#ibcon#*mode == 0, iclass 27, count 0 2006.257.22:16:07.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.22:16:07.05#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.22:16:07.05#ibcon#*before write, iclass 27, count 0 2006.257.22:16:07.05#ibcon#enter sib2, iclass 27, count 0 2006.257.22:16:07.05#ibcon#flushed, iclass 27, count 0 2006.257.22:16:07.05#ibcon#about to write, iclass 27, count 0 2006.257.22:16:07.05#ibcon#wrote, iclass 27, count 0 2006.257.22:16:07.05#ibcon#about to read 3, iclass 27, count 0 2006.257.22:16:07.09#ibcon#read 3, iclass 27, count 0 2006.257.22:16:07.09#ibcon#about to read 4, iclass 27, count 0 2006.257.22:16:07.09#ibcon#read 4, iclass 27, count 0 2006.257.22:16:07.09#ibcon#about to read 5, iclass 27, count 0 2006.257.22:16:07.09#ibcon#read 5, iclass 27, count 0 2006.257.22:16:07.09#ibcon#about to read 6, iclass 27, count 0 2006.257.22:16:07.09#ibcon#read 6, iclass 27, count 0 2006.257.22:16:07.09#ibcon#end of sib2, iclass 27, count 0 2006.257.22:16:07.09#ibcon#*after write, iclass 27, count 0 2006.257.22:16:07.09#ibcon#*before return 0, iclass 27, count 0 2006.257.22:16:07.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:07.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:16:07.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.22:16:07.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.22:16:07.10$vck44/vb=4,5 2006.257.22:16:07.10#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.22:16:07.10#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.22:16:07.10#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:07.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:07.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:07.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:07.14#ibcon#enter wrdev, iclass 29, count 2 2006.257.22:16:07.14#ibcon#first serial, iclass 29, count 2 2006.257.22:16:07.14#ibcon#enter sib2, iclass 29, count 2 2006.257.22:16:07.14#ibcon#flushed, iclass 29, count 2 2006.257.22:16:07.14#ibcon#about to write, iclass 29, count 2 2006.257.22:16:07.14#ibcon#wrote, iclass 29, count 2 2006.257.22:16:07.14#ibcon#about to read 3, iclass 29, count 2 2006.257.22:16:07.16#ibcon#read 3, iclass 29, count 2 2006.257.22:16:07.16#ibcon#about to read 4, iclass 29, count 2 2006.257.22:16:07.16#ibcon#read 4, iclass 29, count 2 2006.257.22:16:07.16#ibcon#about to read 5, iclass 29, count 2 2006.257.22:16:07.16#ibcon#read 5, iclass 29, count 2 2006.257.22:16:07.16#ibcon#about to read 6, iclass 29, count 2 2006.257.22:16:07.16#ibcon#read 6, iclass 29, count 2 2006.257.22:16:07.16#ibcon#end of sib2, iclass 29, count 2 2006.257.22:16:07.16#ibcon#*mode == 0, iclass 29, count 2 2006.257.22:16:07.16#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.22:16:07.16#ibcon#[27=AT04-05\r\n] 2006.257.22:16:07.16#ibcon#*before write, iclass 29, count 2 2006.257.22:16:07.16#ibcon#enter sib2, iclass 29, count 2 2006.257.22:16:07.16#ibcon#flushed, iclass 29, count 2 2006.257.22:16:07.16#ibcon#about to write, iclass 29, count 2 2006.257.22:16:07.16#ibcon#wrote, iclass 29, count 2 2006.257.22:16:07.16#ibcon#about to read 3, iclass 29, count 2 2006.257.22:16:07.19#ibcon#read 3, iclass 29, count 2 2006.257.22:16:07.19#ibcon#about to read 4, iclass 29, count 2 2006.257.22:16:07.19#ibcon#read 4, iclass 29, count 2 2006.257.22:16:07.19#ibcon#about to read 5, iclass 29, count 2 2006.257.22:16:07.19#ibcon#read 5, iclass 29, count 2 2006.257.22:16:07.19#ibcon#about to read 6, iclass 29, count 2 2006.257.22:16:07.19#ibcon#read 6, iclass 29, count 2 2006.257.22:16:07.19#ibcon#end of sib2, iclass 29, count 2 2006.257.22:16:07.19#ibcon#*after write, iclass 29, count 2 2006.257.22:16:07.19#ibcon#*before return 0, iclass 29, count 2 2006.257.22:16:07.19#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:07.19#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:16:07.19#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.22:16:07.19#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:07.19#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:07.31#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:07.31#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:07.31#ibcon#enter wrdev, iclass 29, count 0 2006.257.22:16:07.31#ibcon#first serial, iclass 29, count 0 2006.257.22:16:07.31#ibcon#enter sib2, iclass 29, count 0 2006.257.22:16:07.31#ibcon#flushed, iclass 29, count 0 2006.257.22:16:07.31#ibcon#about to write, iclass 29, count 0 2006.257.22:16:07.31#ibcon#wrote, iclass 29, count 0 2006.257.22:16:07.31#ibcon#about to read 3, iclass 29, count 0 2006.257.22:16:07.33#ibcon#read 3, iclass 29, count 0 2006.257.22:16:07.33#ibcon#about to read 4, iclass 29, count 0 2006.257.22:16:07.33#ibcon#read 4, iclass 29, count 0 2006.257.22:16:07.33#ibcon#about to read 5, iclass 29, count 0 2006.257.22:16:07.33#ibcon#read 5, iclass 29, count 0 2006.257.22:16:07.33#ibcon#about to read 6, iclass 29, count 0 2006.257.22:16:07.33#ibcon#read 6, iclass 29, count 0 2006.257.22:16:07.33#ibcon#end of sib2, iclass 29, count 0 2006.257.22:16:07.33#ibcon#*mode == 0, iclass 29, count 0 2006.257.22:16:07.33#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.22:16:07.33#ibcon#[27=USB\r\n] 2006.257.22:16:07.33#ibcon#*before write, iclass 29, count 0 2006.257.22:16:07.33#ibcon#enter sib2, iclass 29, count 0 2006.257.22:16:07.33#ibcon#flushed, iclass 29, count 0 2006.257.22:16:07.33#ibcon#about to write, iclass 29, count 0 2006.257.22:16:07.33#ibcon#wrote, iclass 29, count 0 2006.257.22:16:07.33#ibcon#about to read 3, iclass 29, count 0 2006.257.22:16:07.36#ibcon#read 3, iclass 29, count 0 2006.257.22:16:07.36#ibcon#about to read 4, iclass 29, count 0 2006.257.22:16:07.36#ibcon#read 4, iclass 29, count 0 2006.257.22:16:07.36#ibcon#about to read 5, iclass 29, count 0 2006.257.22:16:07.36#ibcon#read 5, iclass 29, count 0 2006.257.22:16:07.36#ibcon#about to read 6, iclass 29, count 0 2006.257.22:16:07.36#ibcon#read 6, iclass 29, count 0 2006.257.22:16:07.36#ibcon#end of sib2, iclass 29, count 0 2006.257.22:16:07.36#ibcon#*after write, iclass 29, count 0 2006.257.22:16:07.36#ibcon#*before return 0, iclass 29, count 0 2006.257.22:16:07.36#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:07.36#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:16:07.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.22:16:07.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.22:16:07.37$vck44/vblo=5,709.99 2006.257.22:16:07.37#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.22:16:07.37#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.22:16:07.37#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:07.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:07.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:07.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:07.37#ibcon#enter wrdev, iclass 31, count 0 2006.257.22:16:07.37#ibcon#first serial, iclass 31, count 0 2006.257.22:16:07.37#ibcon#enter sib2, iclass 31, count 0 2006.257.22:16:07.37#ibcon#flushed, iclass 31, count 0 2006.257.22:16:07.37#ibcon#about to write, iclass 31, count 0 2006.257.22:16:07.37#ibcon#wrote, iclass 31, count 0 2006.257.22:16:07.37#ibcon#about to read 3, iclass 31, count 0 2006.257.22:16:07.38#ibcon#read 3, iclass 31, count 0 2006.257.22:16:07.38#ibcon#about to read 4, iclass 31, count 0 2006.257.22:16:07.38#ibcon#read 4, iclass 31, count 0 2006.257.22:16:07.38#ibcon#about to read 5, iclass 31, count 0 2006.257.22:16:07.38#ibcon#read 5, iclass 31, count 0 2006.257.22:16:07.38#ibcon#about to read 6, iclass 31, count 0 2006.257.22:16:07.38#ibcon#read 6, iclass 31, count 0 2006.257.22:16:07.38#ibcon#end of sib2, iclass 31, count 0 2006.257.22:16:07.38#ibcon#*mode == 0, iclass 31, count 0 2006.257.22:16:07.38#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.22:16:07.38#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.22:16:07.38#ibcon#*before write, iclass 31, count 0 2006.257.22:16:07.38#ibcon#enter sib2, iclass 31, count 0 2006.257.22:16:07.38#ibcon#flushed, iclass 31, count 0 2006.257.22:16:07.38#ibcon#about to write, iclass 31, count 0 2006.257.22:16:07.38#ibcon#wrote, iclass 31, count 0 2006.257.22:16:07.38#ibcon#about to read 3, iclass 31, count 0 2006.257.22:16:07.42#ibcon#read 3, iclass 31, count 0 2006.257.22:16:07.42#ibcon#about to read 4, iclass 31, count 0 2006.257.22:16:07.42#ibcon#read 4, iclass 31, count 0 2006.257.22:16:07.42#ibcon#about to read 5, iclass 31, count 0 2006.257.22:16:07.42#ibcon#read 5, iclass 31, count 0 2006.257.22:16:07.42#ibcon#about to read 6, iclass 31, count 0 2006.257.22:16:07.42#ibcon#read 6, iclass 31, count 0 2006.257.22:16:07.42#ibcon#end of sib2, iclass 31, count 0 2006.257.22:16:07.42#ibcon#*after write, iclass 31, count 0 2006.257.22:16:07.42#ibcon#*before return 0, iclass 31, count 0 2006.257.22:16:07.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:07.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:16:07.42#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.22:16:07.42#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.22:16:07.43$vck44/vb=5,4 2006.257.22:16:07.43#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.22:16:07.43#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.22:16:07.43#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:07.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:07.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:07.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:07.47#ibcon#enter wrdev, iclass 33, count 2 2006.257.22:16:07.47#ibcon#first serial, iclass 33, count 2 2006.257.22:16:07.47#ibcon#enter sib2, iclass 33, count 2 2006.257.22:16:07.47#ibcon#flushed, iclass 33, count 2 2006.257.22:16:07.47#ibcon#about to write, iclass 33, count 2 2006.257.22:16:07.47#ibcon#wrote, iclass 33, count 2 2006.257.22:16:07.47#ibcon#about to read 3, iclass 33, count 2 2006.257.22:16:07.49#ibcon#read 3, iclass 33, count 2 2006.257.22:16:07.49#ibcon#about to read 4, iclass 33, count 2 2006.257.22:16:07.49#ibcon#read 4, iclass 33, count 2 2006.257.22:16:07.49#ibcon#about to read 5, iclass 33, count 2 2006.257.22:16:07.49#ibcon#read 5, iclass 33, count 2 2006.257.22:16:07.49#ibcon#about to read 6, iclass 33, count 2 2006.257.22:16:07.49#ibcon#read 6, iclass 33, count 2 2006.257.22:16:07.49#ibcon#end of sib2, iclass 33, count 2 2006.257.22:16:07.49#ibcon#*mode == 0, iclass 33, count 2 2006.257.22:16:07.49#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.22:16:07.49#ibcon#[27=AT05-04\r\n] 2006.257.22:16:07.49#ibcon#*before write, iclass 33, count 2 2006.257.22:16:07.49#ibcon#enter sib2, iclass 33, count 2 2006.257.22:16:07.49#ibcon#flushed, iclass 33, count 2 2006.257.22:16:07.49#ibcon#about to write, iclass 33, count 2 2006.257.22:16:07.49#ibcon#wrote, iclass 33, count 2 2006.257.22:16:07.49#ibcon#about to read 3, iclass 33, count 2 2006.257.22:16:07.52#ibcon#read 3, iclass 33, count 2 2006.257.22:16:07.52#ibcon#about to read 4, iclass 33, count 2 2006.257.22:16:07.52#ibcon#read 4, iclass 33, count 2 2006.257.22:16:07.52#ibcon#about to read 5, iclass 33, count 2 2006.257.22:16:07.52#ibcon#read 5, iclass 33, count 2 2006.257.22:16:07.52#ibcon#about to read 6, iclass 33, count 2 2006.257.22:16:07.52#ibcon#read 6, iclass 33, count 2 2006.257.22:16:07.52#ibcon#end of sib2, iclass 33, count 2 2006.257.22:16:07.52#ibcon#*after write, iclass 33, count 2 2006.257.22:16:07.52#ibcon#*before return 0, iclass 33, count 2 2006.257.22:16:07.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:07.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:16:07.52#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.22:16:07.52#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:07.52#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:07.64#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:07.64#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:07.64#ibcon#enter wrdev, iclass 33, count 0 2006.257.22:16:07.64#ibcon#first serial, iclass 33, count 0 2006.257.22:16:07.64#ibcon#enter sib2, iclass 33, count 0 2006.257.22:16:07.64#ibcon#flushed, iclass 33, count 0 2006.257.22:16:07.64#ibcon#about to write, iclass 33, count 0 2006.257.22:16:07.64#ibcon#wrote, iclass 33, count 0 2006.257.22:16:07.64#ibcon#about to read 3, iclass 33, count 0 2006.257.22:16:07.66#ibcon#read 3, iclass 33, count 0 2006.257.22:16:07.66#ibcon#about to read 4, iclass 33, count 0 2006.257.22:16:07.66#ibcon#read 4, iclass 33, count 0 2006.257.22:16:07.66#ibcon#about to read 5, iclass 33, count 0 2006.257.22:16:07.66#ibcon#read 5, iclass 33, count 0 2006.257.22:16:07.66#ibcon#about to read 6, iclass 33, count 0 2006.257.22:16:07.66#ibcon#read 6, iclass 33, count 0 2006.257.22:16:07.66#ibcon#end of sib2, iclass 33, count 0 2006.257.22:16:07.66#ibcon#*mode == 0, iclass 33, count 0 2006.257.22:16:07.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.22:16:07.66#ibcon#[27=USB\r\n] 2006.257.22:16:07.66#ibcon#*before write, iclass 33, count 0 2006.257.22:16:07.66#ibcon#enter sib2, iclass 33, count 0 2006.257.22:16:07.66#ibcon#flushed, iclass 33, count 0 2006.257.22:16:07.66#ibcon#about to write, iclass 33, count 0 2006.257.22:16:07.66#ibcon#wrote, iclass 33, count 0 2006.257.22:16:07.66#ibcon#about to read 3, iclass 33, count 0 2006.257.22:16:07.69#ibcon#read 3, iclass 33, count 0 2006.257.22:16:07.69#ibcon#about to read 4, iclass 33, count 0 2006.257.22:16:07.69#ibcon#read 4, iclass 33, count 0 2006.257.22:16:07.69#ibcon#about to read 5, iclass 33, count 0 2006.257.22:16:07.69#ibcon#read 5, iclass 33, count 0 2006.257.22:16:07.69#ibcon#about to read 6, iclass 33, count 0 2006.257.22:16:07.69#ibcon#read 6, iclass 33, count 0 2006.257.22:16:07.69#ibcon#end of sib2, iclass 33, count 0 2006.257.22:16:07.69#ibcon#*after write, iclass 33, count 0 2006.257.22:16:07.69#ibcon#*before return 0, iclass 33, count 0 2006.257.22:16:07.69#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:07.69#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:16:07.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.22:16:07.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.22:16:07.70$vck44/vblo=6,719.99 2006.257.22:16:07.70#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.22:16:07.70#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.22:16:07.70#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:07.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:07.70#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:07.70#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:07.70#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:16:07.70#ibcon#first serial, iclass 35, count 0 2006.257.22:16:07.70#ibcon#enter sib2, iclass 35, count 0 2006.257.22:16:07.70#ibcon#flushed, iclass 35, count 0 2006.257.22:16:07.70#ibcon#about to write, iclass 35, count 0 2006.257.22:16:07.70#ibcon#wrote, iclass 35, count 0 2006.257.22:16:07.70#ibcon#about to read 3, iclass 35, count 0 2006.257.22:16:07.71#ibcon#read 3, iclass 35, count 0 2006.257.22:16:07.71#ibcon#about to read 4, iclass 35, count 0 2006.257.22:16:07.71#ibcon#read 4, iclass 35, count 0 2006.257.22:16:07.71#ibcon#about to read 5, iclass 35, count 0 2006.257.22:16:07.71#ibcon#read 5, iclass 35, count 0 2006.257.22:16:07.71#ibcon#about to read 6, iclass 35, count 0 2006.257.22:16:07.71#ibcon#read 6, iclass 35, count 0 2006.257.22:16:07.71#ibcon#end of sib2, iclass 35, count 0 2006.257.22:16:07.71#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:16:07.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:16:07.71#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.22:16:07.71#ibcon#*before write, iclass 35, count 0 2006.257.22:16:07.71#ibcon#enter sib2, iclass 35, count 0 2006.257.22:16:07.71#ibcon#flushed, iclass 35, count 0 2006.257.22:16:07.71#ibcon#about to write, iclass 35, count 0 2006.257.22:16:07.71#ibcon#wrote, iclass 35, count 0 2006.257.22:16:07.71#ibcon#about to read 3, iclass 35, count 0 2006.257.22:16:07.75#ibcon#read 3, iclass 35, count 0 2006.257.22:16:07.75#ibcon#about to read 4, iclass 35, count 0 2006.257.22:16:07.75#ibcon#read 4, iclass 35, count 0 2006.257.22:16:07.75#ibcon#about to read 5, iclass 35, count 0 2006.257.22:16:07.75#ibcon#read 5, iclass 35, count 0 2006.257.22:16:07.75#ibcon#about to read 6, iclass 35, count 0 2006.257.22:16:07.75#ibcon#read 6, iclass 35, count 0 2006.257.22:16:07.75#ibcon#end of sib2, iclass 35, count 0 2006.257.22:16:07.75#ibcon#*after write, iclass 35, count 0 2006.257.22:16:07.75#ibcon#*before return 0, iclass 35, count 0 2006.257.22:16:07.75#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:07.75#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:16:07.75#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:16:07.75#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:16:07.76$vck44/vb=6,4 2006.257.22:16:07.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.22:16:07.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.22:16:07.76#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:07.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:16:07.78#abcon#<5=/14 0.5 1.5 19.06 881015.8\r\n> 2006.257.22:16:07.80#abcon#{5=INTERFACE CLEAR} 2006.257.22:16:07.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:16:07.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:16:07.81#ibcon#enter wrdev, iclass 38, count 2 2006.257.22:16:07.81#ibcon#first serial, iclass 38, count 2 2006.257.22:16:07.81#ibcon#enter sib2, iclass 38, count 2 2006.257.22:16:07.81#ibcon#flushed, iclass 38, count 2 2006.257.22:16:07.81#ibcon#about to write, iclass 38, count 2 2006.257.22:16:07.81#ibcon#wrote, iclass 38, count 2 2006.257.22:16:07.81#ibcon#about to read 3, iclass 38, count 2 2006.257.22:16:07.82#ibcon#read 3, iclass 38, count 2 2006.257.22:16:07.82#ibcon#about to read 4, iclass 38, count 2 2006.257.22:16:07.82#ibcon#read 4, iclass 38, count 2 2006.257.22:16:07.82#ibcon#about to read 5, iclass 38, count 2 2006.257.22:16:07.82#ibcon#read 5, iclass 38, count 2 2006.257.22:16:07.82#ibcon#about to read 6, iclass 38, count 2 2006.257.22:16:07.82#ibcon#read 6, iclass 38, count 2 2006.257.22:16:07.82#ibcon#end of sib2, iclass 38, count 2 2006.257.22:16:07.82#ibcon#*mode == 0, iclass 38, count 2 2006.257.22:16:07.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.22:16:07.82#ibcon#[27=AT06-04\r\n] 2006.257.22:16:07.82#ibcon#*before write, iclass 38, count 2 2006.257.22:16:07.82#ibcon#enter sib2, iclass 38, count 2 2006.257.22:16:07.82#ibcon#flushed, iclass 38, count 2 2006.257.22:16:07.82#ibcon#about to write, iclass 38, count 2 2006.257.22:16:07.82#ibcon#wrote, iclass 38, count 2 2006.257.22:16:07.82#ibcon#about to read 3, iclass 38, count 2 2006.257.22:16:07.85#ibcon#read 3, iclass 38, count 2 2006.257.22:16:07.85#ibcon#about to read 4, iclass 38, count 2 2006.257.22:16:07.85#ibcon#read 4, iclass 38, count 2 2006.257.22:16:07.85#ibcon#about to read 5, iclass 38, count 2 2006.257.22:16:07.85#ibcon#read 5, iclass 38, count 2 2006.257.22:16:07.85#ibcon#about to read 6, iclass 38, count 2 2006.257.22:16:07.85#ibcon#read 6, iclass 38, count 2 2006.257.22:16:07.85#ibcon#end of sib2, iclass 38, count 2 2006.257.22:16:07.85#ibcon#*after write, iclass 38, count 2 2006.257.22:16:07.85#ibcon#*before return 0, iclass 38, count 2 2006.257.22:16:07.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:16:07.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:16:07.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.22:16:07.85#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:07.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:16:07.86#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:16:07.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:16:07.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:16:07.97#ibcon#enter wrdev, iclass 38, count 0 2006.257.22:16:07.97#ibcon#first serial, iclass 38, count 0 2006.257.22:16:07.97#ibcon#enter sib2, iclass 38, count 0 2006.257.22:16:07.97#ibcon#flushed, iclass 38, count 0 2006.257.22:16:07.97#ibcon#about to write, iclass 38, count 0 2006.257.22:16:07.97#ibcon#wrote, iclass 38, count 0 2006.257.22:16:07.97#ibcon#about to read 3, iclass 38, count 0 2006.257.22:16:07.99#ibcon#read 3, iclass 38, count 0 2006.257.22:16:07.99#ibcon#about to read 4, iclass 38, count 0 2006.257.22:16:07.99#ibcon#read 4, iclass 38, count 0 2006.257.22:16:07.99#ibcon#about to read 5, iclass 38, count 0 2006.257.22:16:07.99#ibcon#read 5, iclass 38, count 0 2006.257.22:16:07.99#ibcon#about to read 6, iclass 38, count 0 2006.257.22:16:07.99#ibcon#read 6, iclass 38, count 0 2006.257.22:16:07.99#ibcon#end of sib2, iclass 38, count 0 2006.257.22:16:07.99#ibcon#*mode == 0, iclass 38, count 0 2006.257.22:16:07.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.22:16:07.99#ibcon#[27=USB\r\n] 2006.257.22:16:07.99#ibcon#*before write, iclass 38, count 0 2006.257.22:16:07.99#ibcon#enter sib2, iclass 38, count 0 2006.257.22:16:07.99#ibcon#flushed, iclass 38, count 0 2006.257.22:16:07.99#ibcon#about to write, iclass 38, count 0 2006.257.22:16:07.99#ibcon#wrote, iclass 38, count 0 2006.257.22:16:07.99#ibcon#about to read 3, iclass 38, count 0 2006.257.22:16:08.02#ibcon#read 3, iclass 38, count 0 2006.257.22:16:08.02#ibcon#about to read 4, iclass 38, count 0 2006.257.22:16:08.02#ibcon#read 4, iclass 38, count 0 2006.257.22:16:08.02#ibcon#about to read 5, iclass 38, count 0 2006.257.22:16:08.02#ibcon#read 5, iclass 38, count 0 2006.257.22:16:08.02#ibcon#about to read 6, iclass 38, count 0 2006.257.22:16:08.02#ibcon#read 6, iclass 38, count 0 2006.257.22:16:08.02#ibcon#end of sib2, iclass 38, count 0 2006.257.22:16:08.02#ibcon#*after write, iclass 38, count 0 2006.257.22:16:08.02#ibcon#*before return 0, iclass 38, count 0 2006.257.22:16:08.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:16:08.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:16:08.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.22:16:08.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.22:16:08.03$vck44/vblo=7,734.99 2006.257.22:16:08.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.22:16:08.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.22:16:08.03#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:08.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:08.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:08.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:08.03#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:16:08.03#ibcon#first serial, iclass 5, count 0 2006.257.22:16:08.03#ibcon#enter sib2, iclass 5, count 0 2006.257.22:16:08.03#ibcon#flushed, iclass 5, count 0 2006.257.22:16:08.03#ibcon#about to write, iclass 5, count 0 2006.257.22:16:08.03#ibcon#wrote, iclass 5, count 0 2006.257.22:16:08.03#ibcon#about to read 3, iclass 5, count 0 2006.257.22:16:08.04#ibcon#read 3, iclass 5, count 0 2006.257.22:16:08.04#ibcon#about to read 4, iclass 5, count 0 2006.257.22:16:08.04#ibcon#read 4, iclass 5, count 0 2006.257.22:16:08.04#ibcon#about to read 5, iclass 5, count 0 2006.257.22:16:08.04#ibcon#read 5, iclass 5, count 0 2006.257.22:16:08.04#ibcon#about to read 6, iclass 5, count 0 2006.257.22:16:08.04#ibcon#read 6, iclass 5, count 0 2006.257.22:16:08.04#ibcon#end of sib2, iclass 5, count 0 2006.257.22:16:08.04#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:16:08.04#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:16:08.04#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.22:16:08.04#ibcon#*before write, iclass 5, count 0 2006.257.22:16:08.04#ibcon#enter sib2, iclass 5, count 0 2006.257.22:16:08.04#ibcon#flushed, iclass 5, count 0 2006.257.22:16:08.04#ibcon#about to write, iclass 5, count 0 2006.257.22:16:08.04#ibcon#wrote, iclass 5, count 0 2006.257.22:16:08.04#ibcon#about to read 3, iclass 5, count 0 2006.257.22:16:08.08#ibcon#read 3, iclass 5, count 0 2006.257.22:16:08.08#ibcon#about to read 4, iclass 5, count 0 2006.257.22:16:08.08#ibcon#read 4, iclass 5, count 0 2006.257.22:16:08.08#ibcon#about to read 5, iclass 5, count 0 2006.257.22:16:08.08#ibcon#read 5, iclass 5, count 0 2006.257.22:16:08.08#ibcon#about to read 6, iclass 5, count 0 2006.257.22:16:08.08#ibcon#read 6, iclass 5, count 0 2006.257.22:16:08.08#ibcon#end of sib2, iclass 5, count 0 2006.257.22:16:08.08#ibcon#*after write, iclass 5, count 0 2006.257.22:16:08.08#ibcon#*before return 0, iclass 5, count 0 2006.257.22:16:08.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:08.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:16:08.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:16:08.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:16:08.09$vck44/vb=7,4 2006.257.22:16:08.09#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.22:16:08.09#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.22:16:08.09#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:08.09#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:08.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:08.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:08.14#ibcon#enter wrdev, iclass 7, count 2 2006.257.22:16:08.14#ibcon#first serial, iclass 7, count 2 2006.257.22:16:08.14#ibcon#enter sib2, iclass 7, count 2 2006.257.22:16:08.14#ibcon#flushed, iclass 7, count 2 2006.257.22:16:08.14#ibcon#about to write, iclass 7, count 2 2006.257.22:16:08.14#ibcon#wrote, iclass 7, count 2 2006.257.22:16:08.14#ibcon#about to read 3, iclass 7, count 2 2006.257.22:16:08.15#ibcon#read 3, iclass 7, count 2 2006.257.22:16:08.15#ibcon#about to read 4, iclass 7, count 2 2006.257.22:16:08.15#ibcon#read 4, iclass 7, count 2 2006.257.22:16:08.15#ibcon#about to read 5, iclass 7, count 2 2006.257.22:16:08.15#ibcon#read 5, iclass 7, count 2 2006.257.22:16:08.15#ibcon#about to read 6, iclass 7, count 2 2006.257.22:16:08.15#ibcon#read 6, iclass 7, count 2 2006.257.22:16:08.15#ibcon#end of sib2, iclass 7, count 2 2006.257.22:16:08.15#ibcon#*mode == 0, iclass 7, count 2 2006.257.22:16:08.15#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.22:16:08.15#ibcon#[27=AT07-04\r\n] 2006.257.22:16:08.15#ibcon#*before write, iclass 7, count 2 2006.257.22:16:08.15#ibcon#enter sib2, iclass 7, count 2 2006.257.22:16:08.15#ibcon#flushed, iclass 7, count 2 2006.257.22:16:08.15#ibcon#about to write, iclass 7, count 2 2006.257.22:16:08.15#ibcon#wrote, iclass 7, count 2 2006.257.22:16:08.15#ibcon#about to read 3, iclass 7, count 2 2006.257.22:16:08.18#ibcon#read 3, iclass 7, count 2 2006.257.22:16:08.18#ibcon#about to read 4, iclass 7, count 2 2006.257.22:16:08.18#ibcon#read 4, iclass 7, count 2 2006.257.22:16:08.18#ibcon#about to read 5, iclass 7, count 2 2006.257.22:16:08.18#ibcon#read 5, iclass 7, count 2 2006.257.22:16:08.18#ibcon#about to read 6, iclass 7, count 2 2006.257.22:16:08.18#ibcon#read 6, iclass 7, count 2 2006.257.22:16:08.18#ibcon#end of sib2, iclass 7, count 2 2006.257.22:16:08.18#ibcon#*after write, iclass 7, count 2 2006.257.22:16:08.18#ibcon#*before return 0, iclass 7, count 2 2006.257.22:16:08.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:08.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:16:08.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.22:16:08.18#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:08.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:08.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:08.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:08.30#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:16:08.30#ibcon#first serial, iclass 7, count 0 2006.257.22:16:08.30#ibcon#enter sib2, iclass 7, count 0 2006.257.22:16:08.30#ibcon#flushed, iclass 7, count 0 2006.257.22:16:08.30#ibcon#about to write, iclass 7, count 0 2006.257.22:16:08.30#ibcon#wrote, iclass 7, count 0 2006.257.22:16:08.30#ibcon#about to read 3, iclass 7, count 0 2006.257.22:16:08.32#ibcon#read 3, iclass 7, count 0 2006.257.22:16:08.32#ibcon#about to read 4, iclass 7, count 0 2006.257.22:16:08.32#ibcon#read 4, iclass 7, count 0 2006.257.22:16:08.32#ibcon#about to read 5, iclass 7, count 0 2006.257.22:16:08.32#ibcon#read 5, iclass 7, count 0 2006.257.22:16:08.32#ibcon#about to read 6, iclass 7, count 0 2006.257.22:16:08.32#ibcon#read 6, iclass 7, count 0 2006.257.22:16:08.32#ibcon#end of sib2, iclass 7, count 0 2006.257.22:16:08.32#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:16:08.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:16:08.32#ibcon#[27=USB\r\n] 2006.257.22:16:08.32#ibcon#*before write, iclass 7, count 0 2006.257.22:16:08.32#ibcon#enter sib2, iclass 7, count 0 2006.257.22:16:08.32#ibcon#flushed, iclass 7, count 0 2006.257.22:16:08.32#ibcon#about to write, iclass 7, count 0 2006.257.22:16:08.32#ibcon#wrote, iclass 7, count 0 2006.257.22:16:08.32#ibcon#about to read 3, iclass 7, count 0 2006.257.22:16:08.35#ibcon#read 3, iclass 7, count 0 2006.257.22:16:08.35#ibcon#about to read 4, iclass 7, count 0 2006.257.22:16:08.35#ibcon#read 4, iclass 7, count 0 2006.257.22:16:08.35#ibcon#about to read 5, iclass 7, count 0 2006.257.22:16:08.35#ibcon#read 5, iclass 7, count 0 2006.257.22:16:08.35#ibcon#about to read 6, iclass 7, count 0 2006.257.22:16:08.35#ibcon#read 6, iclass 7, count 0 2006.257.22:16:08.35#ibcon#end of sib2, iclass 7, count 0 2006.257.22:16:08.35#ibcon#*after write, iclass 7, count 0 2006.257.22:16:08.35#ibcon#*before return 0, iclass 7, count 0 2006.257.22:16:08.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:08.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:16:08.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:16:08.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:16:08.36$vck44/vblo=8,744.99 2006.257.22:16:08.36#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.22:16:08.36#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.22:16:08.36#ibcon#ireg 17 cls_cnt 0 2006.257.22:16:08.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:08.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:08.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:08.36#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:16:08.36#ibcon#first serial, iclass 11, count 0 2006.257.22:16:08.36#ibcon#enter sib2, iclass 11, count 0 2006.257.22:16:08.36#ibcon#flushed, iclass 11, count 0 2006.257.22:16:08.36#ibcon#about to write, iclass 11, count 0 2006.257.22:16:08.36#ibcon#wrote, iclass 11, count 0 2006.257.22:16:08.36#ibcon#about to read 3, iclass 11, count 0 2006.257.22:16:08.37#ibcon#read 3, iclass 11, count 0 2006.257.22:16:08.37#ibcon#about to read 4, iclass 11, count 0 2006.257.22:16:08.37#ibcon#read 4, iclass 11, count 0 2006.257.22:16:08.37#ibcon#about to read 5, iclass 11, count 0 2006.257.22:16:08.37#ibcon#read 5, iclass 11, count 0 2006.257.22:16:08.37#ibcon#about to read 6, iclass 11, count 0 2006.257.22:16:08.37#ibcon#read 6, iclass 11, count 0 2006.257.22:16:08.37#ibcon#end of sib2, iclass 11, count 0 2006.257.22:16:08.37#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:16:08.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:16:08.37#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.22:16:08.37#ibcon#*before write, iclass 11, count 0 2006.257.22:16:08.37#ibcon#enter sib2, iclass 11, count 0 2006.257.22:16:08.37#ibcon#flushed, iclass 11, count 0 2006.257.22:16:08.37#ibcon#about to write, iclass 11, count 0 2006.257.22:16:08.37#ibcon#wrote, iclass 11, count 0 2006.257.22:16:08.37#ibcon#about to read 3, iclass 11, count 0 2006.257.22:16:08.41#ibcon#read 3, iclass 11, count 0 2006.257.22:16:08.41#ibcon#about to read 4, iclass 11, count 0 2006.257.22:16:08.41#ibcon#read 4, iclass 11, count 0 2006.257.22:16:08.41#ibcon#about to read 5, iclass 11, count 0 2006.257.22:16:08.41#ibcon#read 5, iclass 11, count 0 2006.257.22:16:08.41#ibcon#about to read 6, iclass 11, count 0 2006.257.22:16:08.41#ibcon#read 6, iclass 11, count 0 2006.257.22:16:08.41#ibcon#end of sib2, iclass 11, count 0 2006.257.22:16:08.41#ibcon#*after write, iclass 11, count 0 2006.257.22:16:08.41#ibcon#*before return 0, iclass 11, count 0 2006.257.22:16:08.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:08.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:16:08.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:16:08.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:16:08.42$vck44/vb=8,4 2006.257.22:16:08.42#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.22:16:08.42#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.22:16:08.42#ibcon#ireg 11 cls_cnt 2 2006.257.22:16:08.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:08.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:08.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:08.46#ibcon#enter wrdev, iclass 13, count 2 2006.257.22:16:08.46#ibcon#first serial, iclass 13, count 2 2006.257.22:16:08.46#ibcon#enter sib2, iclass 13, count 2 2006.257.22:16:08.46#ibcon#flushed, iclass 13, count 2 2006.257.22:16:08.46#ibcon#about to write, iclass 13, count 2 2006.257.22:16:08.46#ibcon#wrote, iclass 13, count 2 2006.257.22:16:08.46#ibcon#about to read 3, iclass 13, count 2 2006.257.22:16:08.48#ibcon#read 3, iclass 13, count 2 2006.257.22:16:08.48#ibcon#about to read 4, iclass 13, count 2 2006.257.22:16:08.48#ibcon#read 4, iclass 13, count 2 2006.257.22:16:08.48#ibcon#about to read 5, iclass 13, count 2 2006.257.22:16:08.48#ibcon#read 5, iclass 13, count 2 2006.257.22:16:08.48#ibcon#about to read 6, iclass 13, count 2 2006.257.22:16:08.48#ibcon#read 6, iclass 13, count 2 2006.257.22:16:08.48#ibcon#end of sib2, iclass 13, count 2 2006.257.22:16:08.48#ibcon#*mode == 0, iclass 13, count 2 2006.257.22:16:08.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.22:16:08.48#ibcon#[27=AT08-04\r\n] 2006.257.22:16:08.48#ibcon#*before write, iclass 13, count 2 2006.257.22:16:08.48#ibcon#enter sib2, iclass 13, count 2 2006.257.22:16:08.48#ibcon#flushed, iclass 13, count 2 2006.257.22:16:08.48#ibcon#about to write, iclass 13, count 2 2006.257.22:16:08.48#ibcon#wrote, iclass 13, count 2 2006.257.22:16:08.48#ibcon#about to read 3, iclass 13, count 2 2006.257.22:16:08.51#ibcon#read 3, iclass 13, count 2 2006.257.22:16:08.51#ibcon#about to read 4, iclass 13, count 2 2006.257.22:16:08.51#ibcon#read 4, iclass 13, count 2 2006.257.22:16:08.51#ibcon#about to read 5, iclass 13, count 2 2006.257.22:16:08.51#ibcon#read 5, iclass 13, count 2 2006.257.22:16:08.51#ibcon#about to read 6, iclass 13, count 2 2006.257.22:16:08.51#ibcon#read 6, iclass 13, count 2 2006.257.22:16:08.51#ibcon#end of sib2, iclass 13, count 2 2006.257.22:16:08.51#ibcon#*after write, iclass 13, count 2 2006.257.22:16:08.51#ibcon#*before return 0, iclass 13, count 2 2006.257.22:16:08.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:08.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:16:08.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.22:16:08.51#ibcon#ireg 7 cls_cnt 0 2006.257.22:16:08.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:08.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:08.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:08.63#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:16:08.63#ibcon#first serial, iclass 13, count 0 2006.257.22:16:08.63#ibcon#enter sib2, iclass 13, count 0 2006.257.22:16:08.63#ibcon#flushed, iclass 13, count 0 2006.257.22:16:08.63#ibcon#about to write, iclass 13, count 0 2006.257.22:16:08.63#ibcon#wrote, iclass 13, count 0 2006.257.22:16:08.63#ibcon#about to read 3, iclass 13, count 0 2006.257.22:16:08.65#ibcon#read 3, iclass 13, count 0 2006.257.22:16:08.65#ibcon#about to read 4, iclass 13, count 0 2006.257.22:16:08.65#ibcon#read 4, iclass 13, count 0 2006.257.22:16:08.65#ibcon#about to read 5, iclass 13, count 0 2006.257.22:16:08.65#ibcon#read 5, iclass 13, count 0 2006.257.22:16:08.65#ibcon#about to read 6, iclass 13, count 0 2006.257.22:16:08.65#ibcon#read 6, iclass 13, count 0 2006.257.22:16:08.65#ibcon#end of sib2, iclass 13, count 0 2006.257.22:16:08.65#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:16:08.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:16:08.65#ibcon#[27=USB\r\n] 2006.257.22:16:08.65#ibcon#*before write, iclass 13, count 0 2006.257.22:16:08.65#ibcon#enter sib2, iclass 13, count 0 2006.257.22:16:08.65#ibcon#flushed, iclass 13, count 0 2006.257.22:16:08.65#ibcon#about to write, iclass 13, count 0 2006.257.22:16:08.65#ibcon#wrote, iclass 13, count 0 2006.257.22:16:08.65#ibcon#about to read 3, iclass 13, count 0 2006.257.22:16:08.68#ibcon#read 3, iclass 13, count 0 2006.257.22:16:08.68#ibcon#about to read 4, iclass 13, count 0 2006.257.22:16:08.68#ibcon#read 4, iclass 13, count 0 2006.257.22:16:08.68#ibcon#about to read 5, iclass 13, count 0 2006.257.22:16:08.68#ibcon#read 5, iclass 13, count 0 2006.257.22:16:08.68#ibcon#about to read 6, iclass 13, count 0 2006.257.22:16:08.68#ibcon#read 6, iclass 13, count 0 2006.257.22:16:08.68#ibcon#end of sib2, iclass 13, count 0 2006.257.22:16:08.68#ibcon#*after write, iclass 13, count 0 2006.257.22:16:08.68#ibcon#*before return 0, iclass 13, count 0 2006.257.22:16:08.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:08.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:16:08.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:16:08.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:16:08.69$vck44/vabw=wide 2006.257.22:16:08.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.22:16:08.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.22:16:08.69#ibcon#ireg 8 cls_cnt 0 2006.257.22:16:08.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:08.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:08.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:08.69#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:16:08.69#ibcon#first serial, iclass 15, count 0 2006.257.22:16:08.69#ibcon#enter sib2, iclass 15, count 0 2006.257.22:16:08.69#ibcon#flushed, iclass 15, count 0 2006.257.22:16:08.69#ibcon#about to write, iclass 15, count 0 2006.257.22:16:08.69#ibcon#wrote, iclass 15, count 0 2006.257.22:16:08.69#ibcon#about to read 3, iclass 15, count 0 2006.257.22:16:08.70#ibcon#read 3, iclass 15, count 0 2006.257.22:16:08.70#ibcon#about to read 4, iclass 15, count 0 2006.257.22:16:08.70#ibcon#read 4, iclass 15, count 0 2006.257.22:16:08.70#ibcon#about to read 5, iclass 15, count 0 2006.257.22:16:08.70#ibcon#read 5, iclass 15, count 0 2006.257.22:16:08.70#ibcon#about to read 6, iclass 15, count 0 2006.257.22:16:08.70#ibcon#read 6, iclass 15, count 0 2006.257.22:16:08.70#ibcon#end of sib2, iclass 15, count 0 2006.257.22:16:08.70#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:16:08.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:16:08.70#ibcon#[25=BW32\r\n] 2006.257.22:16:08.70#ibcon#*before write, iclass 15, count 0 2006.257.22:16:08.70#ibcon#enter sib2, iclass 15, count 0 2006.257.22:16:08.70#ibcon#flushed, iclass 15, count 0 2006.257.22:16:08.70#ibcon#about to write, iclass 15, count 0 2006.257.22:16:08.70#ibcon#wrote, iclass 15, count 0 2006.257.22:16:08.70#ibcon#about to read 3, iclass 15, count 0 2006.257.22:16:08.73#ibcon#read 3, iclass 15, count 0 2006.257.22:16:08.73#ibcon#about to read 4, iclass 15, count 0 2006.257.22:16:08.73#ibcon#read 4, iclass 15, count 0 2006.257.22:16:08.73#ibcon#about to read 5, iclass 15, count 0 2006.257.22:16:08.73#ibcon#read 5, iclass 15, count 0 2006.257.22:16:08.73#ibcon#about to read 6, iclass 15, count 0 2006.257.22:16:08.73#ibcon#read 6, iclass 15, count 0 2006.257.22:16:08.73#ibcon#end of sib2, iclass 15, count 0 2006.257.22:16:08.73#ibcon#*after write, iclass 15, count 0 2006.257.22:16:08.73#ibcon#*before return 0, iclass 15, count 0 2006.257.22:16:08.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:08.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:16:08.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:16:08.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:16:08.74$vck44/vbbw=wide 2006.257.22:16:08.74#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.22:16:08.74#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.22:16:08.74#ibcon#ireg 8 cls_cnt 0 2006.257.22:16:08.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:16:08.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:16:08.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:16:08.79#ibcon#enter wrdev, iclass 17, count 0 2006.257.22:16:08.79#ibcon#first serial, iclass 17, count 0 2006.257.22:16:08.79#ibcon#enter sib2, iclass 17, count 0 2006.257.22:16:08.79#ibcon#flushed, iclass 17, count 0 2006.257.22:16:08.79#ibcon#about to write, iclass 17, count 0 2006.257.22:16:08.79#ibcon#wrote, iclass 17, count 0 2006.257.22:16:08.79#ibcon#about to read 3, iclass 17, count 0 2006.257.22:16:08.81#ibcon#read 3, iclass 17, count 0 2006.257.22:16:08.81#ibcon#about to read 4, iclass 17, count 0 2006.257.22:16:08.81#ibcon#read 4, iclass 17, count 0 2006.257.22:16:08.81#ibcon#about to read 5, iclass 17, count 0 2006.257.22:16:08.81#ibcon#read 5, iclass 17, count 0 2006.257.22:16:08.81#ibcon#about to read 6, iclass 17, count 0 2006.257.22:16:08.81#ibcon#read 6, iclass 17, count 0 2006.257.22:16:08.81#ibcon#end of sib2, iclass 17, count 0 2006.257.22:16:08.81#ibcon#*mode == 0, iclass 17, count 0 2006.257.22:16:08.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.22:16:08.81#ibcon#[27=BW32\r\n] 2006.257.22:16:08.81#ibcon#*before write, iclass 17, count 0 2006.257.22:16:08.81#ibcon#enter sib2, iclass 17, count 0 2006.257.22:16:08.81#ibcon#flushed, iclass 17, count 0 2006.257.22:16:08.81#ibcon#about to write, iclass 17, count 0 2006.257.22:16:08.81#ibcon#wrote, iclass 17, count 0 2006.257.22:16:08.81#ibcon#about to read 3, iclass 17, count 0 2006.257.22:16:08.84#ibcon#read 3, iclass 17, count 0 2006.257.22:16:08.84#ibcon#about to read 4, iclass 17, count 0 2006.257.22:16:08.84#ibcon#read 4, iclass 17, count 0 2006.257.22:16:08.84#ibcon#about to read 5, iclass 17, count 0 2006.257.22:16:08.84#ibcon#read 5, iclass 17, count 0 2006.257.22:16:08.84#ibcon#about to read 6, iclass 17, count 0 2006.257.22:16:08.84#ibcon#read 6, iclass 17, count 0 2006.257.22:16:08.84#ibcon#end of sib2, iclass 17, count 0 2006.257.22:16:08.84#ibcon#*after write, iclass 17, count 0 2006.257.22:16:08.84#ibcon#*before return 0, iclass 17, count 0 2006.257.22:16:08.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:16:08.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:16:08.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.22:16:08.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.22:16:08.85$setupk4/ifdk4 2006.257.22:16:08.85$ifdk4/lo= 2006.257.22:16:08.85$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.22:16:08.85$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.22:16:08.85$ifdk4/patch= 2006.257.22:16:08.85$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.22:16:08.85$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.22:16:08.85$setupk4/!*+20s 2006.257.22:16:17.95#abcon#<5=/14 0.5 1.5 19.07 881015.9\r\n> 2006.257.22:16:17.97#abcon#{5=INTERFACE CLEAR} 2006.257.22:16:18.03#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:16:23.51$setupk4/"tpicd 2006.257.22:16:23.51$setupk4/echo=off 2006.257.22:16:23.51$setupk4/xlog=off 2006.257.22:16:23.52:!2006.257.22:17:33 2006.257.22:16:25.13#trakl#Source acquired 2006.257.22:16:26.14#flagr#flagr/antenna,acquired 2006.257.22:17:33.01:preob 2006.257.22:17:34.13/onsource/TRACKING 2006.257.22:17:34.14:!2006.257.22:17:43 2006.257.22:17:43.01:"tape 2006.257.22:17:43.01:"st=record 2006.257.22:17:43.02:data_valid=on 2006.257.22:17:43.02:midob 2006.257.22:17:44.13/onsource/TRACKING 2006.257.22:17:44.14/wx/19.12,1015.9,88 2006.257.22:17:44.26/cable/+6.4843E-03 2006.257.22:17:45.35/va/01,08,usb,yes,31,33 2006.257.22:17:45.35/va/02,07,usb,yes,34,34 2006.257.22:17:45.35/va/03,08,usb,yes,30,32 2006.257.22:17:45.35/va/04,07,usb,yes,35,36 2006.257.22:17:45.35/va/05,04,usb,yes,31,31 2006.257.22:17:45.35/va/06,04,usb,yes,34,34 2006.257.22:17:45.35/va/07,04,usb,yes,35,36 2006.257.22:17:45.35/va/08,04,usb,yes,30,36 2006.257.22:17:45.58/valo/01,524.99,yes,locked 2006.257.22:17:45.58/valo/02,534.99,yes,locked 2006.257.22:17:45.58/valo/03,564.99,yes,locked 2006.257.22:17:45.58/valo/04,624.99,yes,locked 2006.257.22:17:45.58/valo/05,734.99,yes,locked 2006.257.22:17:45.58/valo/06,814.99,yes,locked 2006.257.22:17:45.58/valo/07,864.99,yes,locked 2006.257.22:17:45.58/valo/08,884.99,yes,locked 2006.257.22:17:46.67/vb/01,04,usb,yes,31,28 2006.257.22:17:46.67/vb/02,05,usb,yes,29,29 2006.257.22:17:46.67/vb/03,04,usb,yes,30,33 2006.257.22:17:46.67/vb/04,05,usb,yes,30,29 2006.257.22:17:46.67/vb/05,04,usb,yes,26,29 2006.257.22:17:46.67/vb/06,04,usb,yes,31,27 2006.257.22:17:46.67/vb/07,04,usb,yes,31,31 2006.257.22:17:46.67/vb/08,04,usb,yes,28,32 2006.257.22:17:46.90/vblo/01,629.99,yes,locked 2006.257.22:17:46.90/vblo/02,634.99,yes,locked 2006.257.22:17:46.90/vblo/03,649.99,yes,locked 2006.257.22:17:46.90/vblo/04,679.99,yes,locked 2006.257.22:17:46.90/vblo/05,709.99,yes,locked 2006.257.22:17:46.90/vblo/06,719.99,yes,locked 2006.257.22:17:46.90/vblo/07,734.99,yes,locked 2006.257.22:17:46.90/vblo/08,744.99,yes,locked 2006.257.22:17:47.05/vabw/8 2006.257.22:17:47.20/vbbw/8 2006.257.22:17:47.38/xfe/off,on,15.2 2006.257.22:17:47.75/ifatt/23,28,28,28 2006.257.22:17:48.07/fmout-gps/S +4.49E-07 2006.257.22:17:48.11:!2006.257.22:18:43 2006.257.22:18:43.01:data_valid=off 2006.257.22:18:43.02:"et 2006.257.22:18:43.02:!+3s 2006.257.22:18:46.04:"tape 2006.257.22:18:46.04:postob 2006.257.22:18:46.12/cable/+6.4854E-03 2006.257.22:18:46.12/wx/19.16,1015.9,89 2006.257.22:18:46.18/fmout-gps/S +4.49E-07 2006.257.22:18:46.18:scan_name=257-2221,jd0609,110 2006.257.22:18:46.18:source=3c274,123049.42,122328.0,2000.0,cw 2006.257.22:18:47.14#flagr#flagr/antenna,new-source 2006.257.22:18:47.15:checkk5 2006.257.22:18:47.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.22:18:47.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.22:18:48.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.22:18:48.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.22:18:48.86/chk_obsdata//k5ts1/T2572217??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.22:18:49.20/chk_obsdata//k5ts2/T2572217??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.22:18:49.53/chk_obsdata//k5ts3/T2572217??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.22:18:49.86/chk_obsdata//k5ts4/T2572217??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.257.22:18:50.52/k5log//k5ts1_log_newline 2006.257.22:18:51.18/k5log//k5ts2_log_newline 2006.257.22:18:51.84/k5log//k5ts3_log_newline 2006.257.22:18:52.50/k5log//k5ts4_log_newline 2006.257.22:18:52.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.22:18:52.52:setupk4=1 2006.257.22:18:52.52$setupk4/echo=on 2006.257.22:18:52.52$setupk4/pcalon 2006.257.22:18:52.52$pcalon/"no phase cal control is implemented here 2006.257.22:18:52.52$setupk4/"tpicd=stop 2006.257.22:18:52.52$setupk4/"rec=synch_on 2006.257.22:18:52.52$setupk4/"rec_mode=128 2006.257.22:18:52.52$setupk4/!* 2006.257.22:18:52.52$setupk4/recpk4 2006.257.22:18:52.52$recpk4/recpatch= 2006.257.22:18:52.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.22:18:52.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.22:18:52.53$setupk4/vck44 2006.257.22:18:52.53$vck44/valo=1,524.99 2006.257.22:18:52.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.22:18:52.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.22:18:52.53#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:52.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:52.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:52.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:52.53#ibcon#enter wrdev, iclass 3, count 0 2006.257.22:18:52.53#ibcon#first serial, iclass 3, count 0 2006.257.22:18:52.53#ibcon#enter sib2, iclass 3, count 0 2006.257.22:18:52.53#ibcon#flushed, iclass 3, count 0 2006.257.22:18:52.53#ibcon#about to write, iclass 3, count 0 2006.257.22:18:52.53#ibcon#wrote, iclass 3, count 0 2006.257.22:18:52.53#ibcon#about to read 3, iclass 3, count 0 2006.257.22:18:52.54#ibcon#read 3, iclass 3, count 0 2006.257.22:18:52.54#ibcon#about to read 4, iclass 3, count 0 2006.257.22:18:52.54#ibcon#read 4, iclass 3, count 0 2006.257.22:18:52.54#ibcon#about to read 5, iclass 3, count 0 2006.257.22:18:52.54#ibcon#read 5, iclass 3, count 0 2006.257.22:18:52.54#ibcon#about to read 6, iclass 3, count 0 2006.257.22:18:52.54#ibcon#read 6, iclass 3, count 0 2006.257.22:18:52.54#ibcon#end of sib2, iclass 3, count 0 2006.257.22:18:52.54#ibcon#*mode == 0, iclass 3, count 0 2006.257.22:18:52.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.22:18:52.54#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.22:18:52.54#ibcon#*before write, iclass 3, count 0 2006.257.22:18:52.54#ibcon#enter sib2, iclass 3, count 0 2006.257.22:18:52.54#ibcon#flushed, iclass 3, count 0 2006.257.22:18:52.54#ibcon#about to write, iclass 3, count 0 2006.257.22:18:52.54#ibcon#wrote, iclass 3, count 0 2006.257.22:18:52.54#ibcon#about to read 3, iclass 3, count 0 2006.257.22:18:52.59#ibcon#read 3, iclass 3, count 0 2006.257.22:18:52.59#ibcon#about to read 4, iclass 3, count 0 2006.257.22:18:52.59#ibcon#read 4, iclass 3, count 0 2006.257.22:18:52.59#ibcon#about to read 5, iclass 3, count 0 2006.257.22:18:52.59#ibcon#read 5, iclass 3, count 0 2006.257.22:18:52.59#ibcon#about to read 6, iclass 3, count 0 2006.257.22:18:52.59#ibcon#read 6, iclass 3, count 0 2006.257.22:18:52.59#ibcon#end of sib2, iclass 3, count 0 2006.257.22:18:52.59#ibcon#*after write, iclass 3, count 0 2006.257.22:18:52.59#ibcon#*before return 0, iclass 3, count 0 2006.257.22:18:52.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:52.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:52.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.22:18:52.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.22:18:52.59$vck44/va=1,8 2006.257.22:18:52.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.22:18:52.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.22:18:52.59#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:52.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:52.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:52.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:52.59#ibcon#enter wrdev, iclass 5, count 2 2006.257.22:18:52.59#ibcon#first serial, iclass 5, count 2 2006.257.22:18:52.59#ibcon#enter sib2, iclass 5, count 2 2006.257.22:18:52.59#ibcon#flushed, iclass 5, count 2 2006.257.22:18:52.59#ibcon#about to write, iclass 5, count 2 2006.257.22:18:52.59#ibcon#wrote, iclass 5, count 2 2006.257.22:18:52.59#ibcon#about to read 3, iclass 5, count 2 2006.257.22:18:52.61#ibcon#read 3, iclass 5, count 2 2006.257.22:18:52.61#ibcon#about to read 4, iclass 5, count 2 2006.257.22:18:52.61#ibcon#read 4, iclass 5, count 2 2006.257.22:18:52.61#ibcon#about to read 5, iclass 5, count 2 2006.257.22:18:52.61#ibcon#read 5, iclass 5, count 2 2006.257.22:18:52.61#ibcon#about to read 6, iclass 5, count 2 2006.257.22:18:52.61#ibcon#read 6, iclass 5, count 2 2006.257.22:18:52.61#ibcon#end of sib2, iclass 5, count 2 2006.257.22:18:52.61#ibcon#*mode == 0, iclass 5, count 2 2006.257.22:18:52.61#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.22:18:52.61#ibcon#[25=AT01-08\r\n] 2006.257.22:18:52.61#ibcon#*before write, iclass 5, count 2 2006.257.22:18:52.61#ibcon#enter sib2, iclass 5, count 2 2006.257.22:18:52.61#ibcon#flushed, iclass 5, count 2 2006.257.22:18:52.61#ibcon#about to write, iclass 5, count 2 2006.257.22:18:52.61#ibcon#wrote, iclass 5, count 2 2006.257.22:18:52.61#ibcon#about to read 3, iclass 5, count 2 2006.257.22:18:52.64#ibcon#read 3, iclass 5, count 2 2006.257.22:18:52.64#ibcon#about to read 4, iclass 5, count 2 2006.257.22:18:52.64#ibcon#read 4, iclass 5, count 2 2006.257.22:18:52.64#ibcon#about to read 5, iclass 5, count 2 2006.257.22:18:52.64#ibcon#read 5, iclass 5, count 2 2006.257.22:18:52.64#ibcon#about to read 6, iclass 5, count 2 2006.257.22:18:52.64#ibcon#read 6, iclass 5, count 2 2006.257.22:18:52.64#ibcon#end of sib2, iclass 5, count 2 2006.257.22:18:52.64#ibcon#*after write, iclass 5, count 2 2006.257.22:18:52.64#ibcon#*before return 0, iclass 5, count 2 2006.257.22:18:52.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:52.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:52.64#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.22:18:52.64#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:52.64#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:52.76#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:52.76#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:52.76#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:18:52.76#ibcon#first serial, iclass 5, count 0 2006.257.22:18:52.76#ibcon#enter sib2, iclass 5, count 0 2006.257.22:18:52.76#ibcon#flushed, iclass 5, count 0 2006.257.22:18:52.76#ibcon#about to write, iclass 5, count 0 2006.257.22:18:52.76#ibcon#wrote, iclass 5, count 0 2006.257.22:18:52.76#ibcon#about to read 3, iclass 5, count 0 2006.257.22:18:52.78#ibcon#read 3, iclass 5, count 0 2006.257.22:18:52.78#ibcon#about to read 4, iclass 5, count 0 2006.257.22:18:52.78#ibcon#read 4, iclass 5, count 0 2006.257.22:18:52.78#ibcon#about to read 5, iclass 5, count 0 2006.257.22:18:52.78#ibcon#read 5, iclass 5, count 0 2006.257.22:18:52.78#ibcon#about to read 6, iclass 5, count 0 2006.257.22:18:52.78#ibcon#read 6, iclass 5, count 0 2006.257.22:18:52.78#ibcon#end of sib2, iclass 5, count 0 2006.257.22:18:52.78#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:18:52.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:18:52.78#ibcon#[25=USB\r\n] 2006.257.22:18:52.78#ibcon#*before write, iclass 5, count 0 2006.257.22:18:52.78#ibcon#enter sib2, iclass 5, count 0 2006.257.22:18:52.78#ibcon#flushed, iclass 5, count 0 2006.257.22:18:52.78#ibcon#about to write, iclass 5, count 0 2006.257.22:18:52.78#ibcon#wrote, iclass 5, count 0 2006.257.22:18:52.78#ibcon#about to read 3, iclass 5, count 0 2006.257.22:18:52.81#ibcon#read 3, iclass 5, count 0 2006.257.22:18:52.81#ibcon#about to read 4, iclass 5, count 0 2006.257.22:18:52.81#ibcon#read 4, iclass 5, count 0 2006.257.22:18:52.81#ibcon#about to read 5, iclass 5, count 0 2006.257.22:18:52.81#ibcon#read 5, iclass 5, count 0 2006.257.22:18:52.81#ibcon#about to read 6, iclass 5, count 0 2006.257.22:18:52.81#ibcon#read 6, iclass 5, count 0 2006.257.22:18:52.81#ibcon#end of sib2, iclass 5, count 0 2006.257.22:18:52.81#ibcon#*after write, iclass 5, count 0 2006.257.22:18:52.81#ibcon#*before return 0, iclass 5, count 0 2006.257.22:18:52.81#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:52.81#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:52.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:18:52.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:18:52.81$vck44/valo=2,534.99 2006.257.22:18:52.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.22:18:52.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.22:18:52.81#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:52.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:52.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:52.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:52.81#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:18:52.81#ibcon#first serial, iclass 7, count 0 2006.257.22:18:52.81#ibcon#enter sib2, iclass 7, count 0 2006.257.22:18:52.81#ibcon#flushed, iclass 7, count 0 2006.257.22:18:52.81#ibcon#about to write, iclass 7, count 0 2006.257.22:18:52.81#ibcon#wrote, iclass 7, count 0 2006.257.22:18:52.81#ibcon#about to read 3, iclass 7, count 0 2006.257.22:18:52.83#ibcon#read 3, iclass 7, count 0 2006.257.22:18:52.83#ibcon#about to read 4, iclass 7, count 0 2006.257.22:18:52.83#ibcon#read 4, iclass 7, count 0 2006.257.22:18:52.83#ibcon#about to read 5, iclass 7, count 0 2006.257.22:18:52.83#ibcon#read 5, iclass 7, count 0 2006.257.22:18:52.83#ibcon#about to read 6, iclass 7, count 0 2006.257.22:18:52.83#ibcon#read 6, iclass 7, count 0 2006.257.22:18:52.83#ibcon#end of sib2, iclass 7, count 0 2006.257.22:18:52.83#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:18:52.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:18:52.83#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.22:18:52.83#ibcon#*before write, iclass 7, count 0 2006.257.22:18:52.83#ibcon#enter sib2, iclass 7, count 0 2006.257.22:18:52.83#ibcon#flushed, iclass 7, count 0 2006.257.22:18:52.83#ibcon#about to write, iclass 7, count 0 2006.257.22:18:52.83#ibcon#wrote, iclass 7, count 0 2006.257.22:18:52.83#ibcon#about to read 3, iclass 7, count 0 2006.257.22:18:52.87#ibcon#read 3, iclass 7, count 0 2006.257.22:18:52.87#ibcon#about to read 4, iclass 7, count 0 2006.257.22:18:52.87#ibcon#read 4, iclass 7, count 0 2006.257.22:18:52.87#ibcon#about to read 5, iclass 7, count 0 2006.257.22:18:52.87#ibcon#read 5, iclass 7, count 0 2006.257.22:18:52.87#ibcon#about to read 6, iclass 7, count 0 2006.257.22:18:52.87#ibcon#read 6, iclass 7, count 0 2006.257.22:18:52.87#ibcon#end of sib2, iclass 7, count 0 2006.257.22:18:52.87#ibcon#*after write, iclass 7, count 0 2006.257.22:18:52.87#ibcon#*before return 0, iclass 7, count 0 2006.257.22:18:52.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:52.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:52.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:18:52.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:18:52.87$vck44/va=2,7 2006.257.22:18:52.87#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.22:18:52.87#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.22:18:52.87#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:52.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:52.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:52.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:52.93#ibcon#enter wrdev, iclass 11, count 2 2006.257.22:18:52.93#ibcon#first serial, iclass 11, count 2 2006.257.22:18:52.93#ibcon#enter sib2, iclass 11, count 2 2006.257.22:18:52.93#ibcon#flushed, iclass 11, count 2 2006.257.22:18:52.93#ibcon#about to write, iclass 11, count 2 2006.257.22:18:52.93#ibcon#wrote, iclass 11, count 2 2006.257.22:18:52.93#ibcon#about to read 3, iclass 11, count 2 2006.257.22:18:52.95#ibcon#read 3, iclass 11, count 2 2006.257.22:18:52.95#ibcon#about to read 4, iclass 11, count 2 2006.257.22:18:52.95#ibcon#read 4, iclass 11, count 2 2006.257.22:18:52.95#ibcon#about to read 5, iclass 11, count 2 2006.257.22:18:52.95#ibcon#read 5, iclass 11, count 2 2006.257.22:18:52.95#ibcon#about to read 6, iclass 11, count 2 2006.257.22:18:52.95#ibcon#read 6, iclass 11, count 2 2006.257.22:18:52.95#ibcon#end of sib2, iclass 11, count 2 2006.257.22:18:52.95#ibcon#*mode == 0, iclass 11, count 2 2006.257.22:18:52.95#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.22:18:52.95#ibcon#[25=AT02-07\r\n] 2006.257.22:18:52.95#ibcon#*before write, iclass 11, count 2 2006.257.22:18:52.95#ibcon#enter sib2, iclass 11, count 2 2006.257.22:18:52.95#ibcon#flushed, iclass 11, count 2 2006.257.22:18:52.95#ibcon#about to write, iclass 11, count 2 2006.257.22:18:52.95#ibcon#wrote, iclass 11, count 2 2006.257.22:18:52.95#ibcon#about to read 3, iclass 11, count 2 2006.257.22:18:52.98#ibcon#read 3, iclass 11, count 2 2006.257.22:18:52.98#ibcon#about to read 4, iclass 11, count 2 2006.257.22:18:52.98#ibcon#read 4, iclass 11, count 2 2006.257.22:18:52.98#ibcon#about to read 5, iclass 11, count 2 2006.257.22:18:52.98#ibcon#read 5, iclass 11, count 2 2006.257.22:18:52.98#ibcon#about to read 6, iclass 11, count 2 2006.257.22:18:52.98#ibcon#read 6, iclass 11, count 2 2006.257.22:18:52.98#ibcon#end of sib2, iclass 11, count 2 2006.257.22:18:52.98#ibcon#*after write, iclass 11, count 2 2006.257.22:18:52.98#ibcon#*before return 0, iclass 11, count 2 2006.257.22:18:52.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:52.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:52.98#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.22:18:52.98#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:52.98#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:53.10#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:53.10#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:53.10#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:18:53.10#ibcon#first serial, iclass 11, count 0 2006.257.22:18:53.10#ibcon#enter sib2, iclass 11, count 0 2006.257.22:18:53.10#ibcon#flushed, iclass 11, count 0 2006.257.22:18:53.10#ibcon#about to write, iclass 11, count 0 2006.257.22:18:53.10#ibcon#wrote, iclass 11, count 0 2006.257.22:18:53.10#ibcon#about to read 3, iclass 11, count 0 2006.257.22:18:53.12#ibcon#read 3, iclass 11, count 0 2006.257.22:18:53.12#ibcon#about to read 4, iclass 11, count 0 2006.257.22:18:53.12#ibcon#read 4, iclass 11, count 0 2006.257.22:18:53.12#ibcon#about to read 5, iclass 11, count 0 2006.257.22:18:53.12#ibcon#read 5, iclass 11, count 0 2006.257.22:18:53.12#ibcon#about to read 6, iclass 11, count 0 2006.257.22:18:53.12#ibcon#read 6, iclass 11, count 0 2006.257.22:18:53.12#ibcon#end of sib2, iclass 11, count 0 2006.257.22:18:53.12#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:18:53.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:18:53.12#ibcon#[25=USB\r\n] 2006.257.22:18:53.12#ibcon#*before write, iclass 11, count 0 2006.257.22:18:53.12#ibcon#enter sib2, iclass 11, count 0 2006.257.22:18:53.12#ibcon#flushed, iclass 11, count 0 2006.257.22:18:53.12#ibcon#about to write, iclass 11, count 0 2006.257.22:18:53.12#ibcon#wrote, iclass 11, count 0 2006.257.22:18:53.12#ibcon#about to read 3, iclass 11, count 0 2006.257.22:18:53.15#ibcon#read 3, iclass 11, count 0 2006.257.22:18:53.15#ibcon#about to read 4, iclass 11, count 0 2006.257.22:18:53.15#ibcon#read 4, iclass 11, count 0 2006.257.22:18:53.15#ibcon#about to read 5, iclass 11, count 0 2006.257.22:18:53.15#ibcon#read 5, iclass 11, count 0 2006.257.22:18:53.15#ibcon#about to read 6, iclass 11, count 0 2006.257.22:18:53.15#ibcon#read 6, iclass 11, count 0 2006.257.22:18:53.15#ibcon#end of sib2, iclass 11, count 0 2006.257.22:18:53.15#ibcon#*after write, iclass 11, count 0 2006.257.22:18:53.15#ibcon#*before return 0, iclass 11, count 0 2006.257.22:18:53.15#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:53.15#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:53.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:18:53.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:18:53.15$vck44/valo=3,564.99 2006.257.22:18:53.15#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.22:18:53.15#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.22:18:53.15#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:53.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:53.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:53.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:53.15#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:18:53.15#ibcon#first serial, iclass 13, count 0 2006.257.22:18:53.15#ibcon#enter sib2, iclass 13, count 0 2006.257.22:18:53.15#ibcon#flushed, iclass 13, count 0 2006.257.22:18:53.15#ibcon#about to write, iclass 13, count 0 2006.257.22:18:53.15#ibcon#wrote, iclass 13, count 0 2006.257.22:18:53.15#ibcon#about to read 3, iclass 13, count 0 2006.257.22:18:53.17#ibcon#read 3, iclass 13, count 0 2006.257.22:18:53.17#ibcon#about to read 4, iclass 13, count 0 2006.257.22:18:53.17#ibcon#read 4, iclass 13, count 0 2006.257.22:18:53.17#ibcon#about to read 5, iclass 13, count 0 2006.257.22:18:53.17#ibcon#read 5, iclass 13, count 0 2006.257.22:18:53.17#ibcon#about to read 6, iclass 13, count 0 2006.257.22:18:53.17#ibcon#read 6, iclass 13, count 0 2006.257.22:18:53.17#ibcon#end of sib2, iclass 13, count 0 2006.257.22:18:53.17#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:18:53.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:18:53.17#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.22:18:53.17#ibcon#*before write, iclass 13, count 0 2006.257.22:18:53.17#ibcon#enter sib2, iclass 13, count 0 2006.257.22:18:53.17#ibcon#flushed, iclass 13, count 0 2006.257.22:18:53.17#ibcon#about to write, iclass 13, count 0 2006.257.22:18:53.17#ibcon#wrote, iclass 13, count 0 2006.257.22:18:53.17#ibcon#about to read 3, iclass 13, count 0 2006.257.22:18:53.21#ibcon#read 3, iclass 13, count 0 2006.257.22:18:53.21#ibcon#about to read 4, iclass 13, count 0 2006.257.22:18:53.21#ibcon#read 4, iclass 13, count 0 2006.257.22:18:53.21#ibcon#about to read 5, iclass 13, count 0 2006.257.22:18:53.21#ibcon#read 5, iclass 13, count 0 2006.257.22:18:53.21#ibcon#about to read 6, iclass 13, count 0 2006.257.22:18:53.21#ibcon#read 6, iclass 13, count 0 2006.257.22:18:53.21#ibcon#end of sib2, iclass 13, count 0 2006.257.22:18:53.21#ibcon#*after write, iclass 13, count 0 2006.257.22:18:53.21#ibcon#*before return 0, iclass 13, count 0 2006.257.22:18:53.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:53.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:53.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:18:53.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:18:53.21$vck44/va=3,8 2006.257.22:18:53.21#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.22:18:53.21#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.22:18:53.21#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:53.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:53.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:53.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:53.27#ibcon#enter wrdev, iclass 15, count 2 2006.257.22:18:53.27#ibcon#first serial, iclass 15, count 2 2006.257.22:18:53.27#ibcon#enter sib2, iclass 15, count 2 2006.257.22:18:53.27#ibcon#flushed, iclass 15, count 2 2006.257.22:18:53.27#ibcon#about to write, iclass 15, count 2 2006.257.22:18:53.27#ibcon#wrote, iclass 15, count 2 2006.257.22:18:53.27#ibcon#about to read 3, iclass 15, count 2 2006.257.22:18:53.29#ibcon#read 3, iclass 15, count 2 2006.257.22:18:53.29#ibcon#about to read 4, iclass 15, count 2 2006.257.22:18:53.29#ibcon#read 4, iclass 15, count 2 2006.257.22:18:53.29#ibcon#about to read 5, iclass 15, count 2 2006.257.22:18:53.29#ibcon#read 5, iclass 15, count 2 2006.257.22:18:53.29#ibcon#about to read 6, iclass 15, count 2 2006.257.22:18:53.29#ibcon#read 6, iclass 15, count 2 2006.257.22:18:53.29#ibcon#end of sib2, iclass 15, count 2 2006.257.22:18:53.29#ibcon#*mode == 0, iclass 15, count 2 2006.257.22:18:53.29#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.22:18:53.29#ibcon#[25=AT03-08\r\n] 2006.257.22:18:53.29#ibcon#*before write, iclass 15, count 2 2006.257.22:18:53.29#ibcon#enter sib2, iclass 15, count 2 2006.257.22:18:53.29#ibcon#flushed, iclass 15, count 2 2006.257.22:18:53.29#ibcon#about to write, iclass 15, count 2 2006.257.22:18:53.29#ibcon#wrote, iclass 15, count 2 2006.257.22:18:53.29#ibcon#about to read 3, iclass 15, count 2 2006.257.22:18:53.32#ibcon#read 3, iclass 15, count 2 2006.257.22:18:53.32#ibcon#about to read 4, iclass 15, count 2 2006.257.22:18:53.32#ibcon#read 4, iclass 15, count 2 2006.257.22:18:53.32#ibcon#about to read 5, iclass 15, count 2 2006.257.22:18:53.32#ibcon#read 5, iclass 15, count 2 2006.257.22:18:53.32#ibcon#about to read 6, iclass 15, count 2 2006.257.22:18:53.32#ibcon#read 6, iclass 15, count 2 2006.257.22:18:53.32#ibcon#end of sib2, iclass 15, count 2 2006.257.22:18:53.32#ibcon#*after write, iclass 15, count 2 2006.257.22:18:53.32#ibcon#*before return 0, iclass 15, count 2 2006.257.22:18:53.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:53.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:53.32#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.22:18:53.32#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:53.32#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:53.33#abcon#<5=/15 0.5 1.8 19.17 891015.9\r\n> 2006.257.22:18:53.35#abcon#{5=INTERFACE CLEAR} 2006.257.22:18:53.41#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:18:53.44#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:53.44#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:53.44#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:18:53.44#ibcon#first serial, iclass 15, count 0 2006.257.22:18:53.44#ibcon#enter sib2, iclass 15, count 0 2006.257.22:18:53.44#ibcon#flushed, iclass 15, count 0 2006.257.22:18:53.44#ibcon#about to write, iclass 15, count 0 2006.257.22:18:53.44#ibcon#wrote, iclass 15, count 0 2006.257.22:18:53.44#ibcon#about to read 3, iclass 15, count 0 2006.257.22:18:53.46#ibcon#read 3, iclass 15, count 0 2006.257.22:18:53.46#ibcon#about to read 4, iclass 15, count 0 2006.257.22:18:53.46#ibcon#read 4, iclass 15, count 0 2006.257.22:18:53.46#ibcon#about to read 5, iclass 15, count 0 2006.257.22:18:53.46#ibcon#read 5, iclass 15, count 0 2006.257.22:18:53.46#ibcon#about to read 6, iclass 15, count 0 2006.257.22:18:53.46#ibcon#read 6, iclass 15, count 0 2006.257.22:18:53.46#ibcon#end of sib2, iclass 15, count 0 2006.257.22:18:53.46#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:18:53.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:18:53.46#ibcon#[25=USB\r\n] 2006.257.22:18:53.46#ibcon#*before write, iclass 15, count 0 2006.257.22:18:53.46#ibcon#enter sib2, iclass 15, count 0 2006.257.22:18:53.46#ibcon#flushed, iclass 15, count 0 2006.257.22:18:53.46#ibcon#about to write, iclass 15, count 0 2006.257.22:18:53.46#ibcon#wrote, iclass 15, count 0 2006.257.22:18:53.46#ibcon#about to read 3, iclass 15, count 0 2006.257.22:18:53.49#ibcon#read 3, iclass 15, count 0 2006.257.22:18:53.49#ibcon#about to read 4, iclass 15, count 0 2006.257.22:18:53.49#ibcon#read 4, iclass 15, count 0 2006.257.22:18:53.49#ibcon#about to read 5, iclass 15, count 0 2006.257.22:18:53.49#ibcon#read 5, iclass 15, count 0 2006.257.22:18:53.49#ibcon#about to read 6, iclass 15, count 0 2006.257.22:18:53.49#ibcon#read 6, iclass 15, count 0 2006.257.22:18:53.49#ibcon#end of sib2, iclass 15, count 0 2006.257.22:18:53.49#ibcon#*after write, iclass 15, count 0 2006.257.22:18:53.49#ibcon#*before return 0, iclass 15, count 0 2006.257.22:18:53.49#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:53.49#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:53.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:18:53.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:18:53.49$vck44/valo=4,624.99 2006.257.22:18:53.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.22:18:53.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.22:18:53.49#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:53.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:53.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:53.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:53.49#ibcon#enter wrdev, iclass 21, count 0 2006.257.22:18:53.49#ibcon#first serial, iclass 21, count 0 2006.257.22:18:53.49#ibcon#enter sib2, iclass 21, count 0 2006.257.22:18:53.49#ibcon#flushed, iclass 21, count 0 2006.257.22:18:53.49#ibcon#about to write, iclass 21, count 0 2006.257.22:18:53.49#ibcon#wrote, iclass 21, count 0 2006.257.22:18:53.49#ibcon#about to read 3, iclass 21, count 0 2006.257.22:18:53.51#ibcon#read 3, iclass 21, count 0 2006.257.22:18:53.51#ibcon#about to read 4, iclass 21, count 0 2006.257.22:18:53.51#ibcon#read 4, iclass 21, count 0 2006.257.22:18:53.51#ibcon#about to read 5, iclass 21, count 0 2006.257.22:18:53.51#ibcon#read 5, iclass 21, count 0 2006.257.22:18:53.51#ibcon#about to read 6, iclass 21, count 0 2006.257.22:18:53.51#ibcon#read 6, iclass 21, count 0 2006.257.22:18:53.51#ibcon#end of sib2, iclass 21, count 0 2006.257.22:18:53.51#ibcon#*mode == 0, iclass 21, count 0 2006.257.22:18:53.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.22:18:53.51#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.22:18:53.51#ibcon#*before write, iclass 21, count 0 2006.257.22:18:53.51#ibcon#enter sib2, iclass 21, count 0 2006.257.22:18:53.51#ibcon#flushed, iclass 21, count 0 2006.257.22:18:53.51#ibcon#about to write, iclass 21, count 0 2006.257.22:18:53.51#ibcon#wrote, iclass 21, count 0 2006.257.22:18:53.51#ibcon#about to read 3, iclass 21, count 0 2006.257.22:18:53.55#ibcon#read 3, iclass 21, count 0 2006.257.22:18:53.55#ibcon#about to read 4, iclass 21, count 0 2006.257.22:18:53.55#ibcon#read 4, iclass 21, count 0 2006.257.22:18:53.55#ibcon#about to read 5, iclass 21, count 0 2006.257.22:18:53.55#ibcon#read 5, iclass 21, count 0 2006.257.22:18:53.55#ibcon#about to read 6, iclass 21, count 0 2006.257.22:18:53.55#ibcon#read 6, iclass 21, count 0 2006.257.22:18:53.55#ibcon#end of sib2, iclass 21, count 0 2006.257.22:18:53.55#ibcon#*after write, iclass 21, count 0 2006.257.22:18:53.55#ibcon#*before return 0, iclass 21, count 0 2006.257.22:18:53.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:53.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:53.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.22:18:53.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.22:18:53.55$vck44/va=4,7 2006.257.22:18:53.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.22:18:53.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.22:18:53.55#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:53.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:53.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:53.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:53.61#ibcon#enter wrdev, iclass 23, count 2 2006.257.22:18:53.61#ibcon#first serial, iclass 23, count 2 2006.257.22:18:53.61#ibcon#enter sib2, iclass 23, count 2 2006.257.22:18:53.61#ibcon#flushed, iclass 23, count 2 2006.257.22:18:53.61#ibcon#about to write, iclass 23, count 2 2006.257.22:18:53.61#ibcon#wrote, iclass 23, count 2 2006.257.22:18:53.61#ibcon#about to read 3, iclass 23, count 2 2006.257.22:18:53.63#ibcon#read 3, iclass 23, count 2 2006.257.22:18:53.63#ibcon#about to read 4, iclass 23, count 2 2006.257.22:18:53.63#ibcon#read 4, iclass 23, count 2 2006.257.22:18:53.63#ibcon#about to read 5, iclass 23, count 2 2006.257.22:18:53.63#ibcon#read 5, iclass 23, count 2 2006.257.22:18:53.63#ibcon#about to read 6, iclass 23, count 2 2006.257.22:18:53.63#ibcon#read 6, iclass 23, count 2 2006.257.22:18:53.63#ibcon#end of sib2, iclass 23, count 2 2006.257.22:18:53.63#ibcon#*mode == 0, iclass 23, count 2 2006.257.22:18:53.63#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.22:18:53.63#ibcon#[25=AT04-07\r\n] 2006.257.22:18:53.63#ibcon#*before write, iclass 23, count 2 2006.257.22:18:53.63#ibcon#enter sib2, iclass 23, count 2 2006.257.22:18:53.63#ibcon#flushed, iclass 23, count 2 2006.257.22:18:53.63#ibcon#about to write, iclass 23, count 2 2006.257.22:18:53.63#ibcon#wrote, iclass 23, count 2 2006.257.22:18:53.63#ibcon#about to read 3, iclass 23, count 2 2006.257.22:18:53.66#ibcon#read 3, iclass 23, count 2 2006.257.22:18:53.66#ibcon#about to read 4, iclass 23, count 2 2006.257.22:18:53.66#ibcon#read 4, iclass 23, count 2 2006.257.22:18:53.66#ibcon#about to read 5, iclass 23, count 2 2006.257.22:18:53.66#ibcon#read 5, iclass 23, count 2 2006.257.22:18:53.66#ibcon#about to read 6, iclass 23, count 2 2006.257.22:18:53.66#ibcon#read 6, iclass 23, count 2 2006.257.22:18:53.66#ibcon#end of sib2, iclass 23, count 2 2006.257.22:18:53.66#ibcon#*after write, iclass 23, count 2 2006.257.22:18:53.66#ibcon#*before return 0, iclass 23, count 2 2006.257.22:18:53.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:53.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:53.66#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.22:18:53.66#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:53.66#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:53.78#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:53.78#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:53.78#ibcon#enter wrdev, iclass 23, count 0 2006.257.22:18:53.78#ibcon#first serial, iclass 23, count 0 2006.257.22:18:53.78#ibcon#enter sib2, iclass 23, count 0 2006.257.22:18:53.78#ibcon#flushed, iclass 23, count 0 2006.257.22:18:53.78#ibcon#about to write, iclass 23, count 0 2006.257.22:18:53.78#ibcon#wrote, iclass 23, count 0 2006.257.22:18:53.78#ibcon#about to read 3, iclass 23, count 0 2006.257.22:18:53.80#ibcon#read 3, iclass 23, count 0 2006.257.22:18:53.80#ibcon#about to read 4, iclass 23, count 0 2006.257.22:18:53.80#ibcon#read 4, iclass 23, count 0 2006.257.22:18:53.80#ibcon#about to read 5, iclass 23, count 0 2006.257.22:18:53.80#ibcon#read 5, iclass 23, count 0 2006.257.22:18:53.80#ibcon#about to read 6, iclass 23, count 0 2006.257.22:18:53.80#ibcon#read 6, iclass 23, count 0 2006.257.22:18:53.80#ibcon#end of sib2, iclass 23, count 0 2006.257.22:18:53.80#ibcon#*mode == 0, iclass 23, count 0 2006.257.22:18:53.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.22:18:53.80#ibcon#[25=USB\r\n] 2006.257.22:18:53.80#ibcon#*before write, iclass 23, count 0 2006.257.22:18:53.80#ibcon#enter sib2, iclass 23, count 0 2006.257.22:18:53.80#ibcon#flushed, iclass 23, count 0 2006.257.22:18:53.80#ibcon#about to write, iclass 23, count 0 2006.257.22:18:53.80#ibcon#wrote, iclass 23, count 0 2006.257.22:18:53.80#ibcon#about to read 3, iclass 23, count 0 2006.257.22:18:53.83#ibcon#read 3, iclass 23, count 0 2006.257.22:18:53.83#ibcon#about to read 4, iclass 23, count 0 2006.257.22:18:53.83#ibcon#read 4, iclass 23, count 0 2006.257.22:18:53.83#ibcon#about to read 5, iclass 23, count 0 2006.257.22:18:53.83#ibcon#read 5, iclass 23, count 0 2006.257.22:18:53.83#ibcon#about to read 6, iclass 23, count 0 2006.257.22:18:53.83#ibcon#read 6, iclass 23, count 0 2006.257.22:18:53.83#ibcon#end of sib2, iclass 23, count 0 2006.257.22:18:53.83#ibcon#*after write, iclass 23, count 0 2006.257.22:18:53.83#ibcon#*before return 0, iclass 23, count 0 2006.257.22:18:53.83#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:53.83#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:53.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.22:18:53.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.22:18:53.83$vck44/valo=5,734.99 2006.257.22:18:53.83#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.22:18:53.83#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.22:18:53.83#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:53.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:53.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:53.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:53.83#ibcon#enter wrdev, iclass 25, count 0 2006.257.22:18:53.83#ibcon#first serial, iclass 25, count 0 2006.257.22:18:53.83#ibcon#enter sib2, iclass 25, count 0 2006.257.22:18:53.83#ibcon#flushed, iclass 25, count 0 2006.257.22:18:53.83#ibcon#about to write, iclass 25, count 0 2006.257.22:18:53.83#ibcon#wrote, iclass 25, count 0 2006.257.22:18:53.83#ibcon#about to read 3, iclass 25, count 0 2006.257.22:18:53.85#ibcon#read 3, iclass 25, count 0 2006.257.22:18:53.85#ibcon#about to read 4, iclass 25, count 0 2006.257.22:18:53.85#ibcon#read 4, iclass 25, count 0 2006.257.22:18:53.85#ibcon#about to read 5, iclass 25, count 0 2006.257.22:18:53.85#ibcon#read 5, iclass 25, count 0 2006.257.22:18:53.85#ibcon#about to read 6, iclass 25, count 0 2006.257.22:18:53.85#ibcon#read 6, iclass 25, count 0 2006.257.22:18:53.85#ibcon#end of sib2, iclass 25, count 0 2006.257.22:18:53.85#ibcon#*mode == 0, iclass 25, count 0 2006.257.22:18:53.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.22:18:53.85#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.22:18:53.85#ibcon#*before write, iclass 25, count 0 2006.257.22:18:53.85#ibcon#enter sib2, iclass 25, count 0 2006.257.22:18:53.85#ibcon#flushed, iclass 25, count 0 2006.257.22:18:53.85#ibcon#about to write, iclass 25, count 0 2006.257.22:18:53.85#ibcon#wrote, iclass 25, count 0 2006.257.22:18:53.85#ibcon#about to read 3, iclass 25, count 0 2006.257.22:18:53.89#ibcon#read 3, iclass 25, count 0 2006.257.22:18:53.89#ibcon#about to read 4, iclass 25, count 0 2006.257.22:18:53.89#ibcon#read 4, iclass 25, count 0 2006.257.22:18:53.89#ibcon#about to read 5, iclass 25, count 0 2006.257.22:18:53.89#ibcon#read 5, iclass 25, count 0 2006.257.22:18:53.89#ibcon#about to read 6, iclass 25, count 0 2006.257.22:18:53.89#ibcon#read 6, iclass 25, count 0 2006.257.22:18:53.89#ibcon#end of sib2, iclass 25, count 0 2006.257.22:18:53.89#ibcon#*after write, iclass 25, count 0 2006.257.22:18:53.89#ibcon#*before return 0, iclass 25, count 0 2006.257.22:18:53.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:53.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:53.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.22:18:53.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.22:18:53.89$vck44/va=5,4 2006.257.22:18:53.89#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.22:18:53.89#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.22:18:53.89#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:53.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:53.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:53.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:53.95#ibcon#enter wrdev, iclass 27, count 2 2006.257.22:18:53.95#ibcon#first serial, iclass 27, count 2 2006.257.22:18:53.95#ibcon#enter sib2, iclass 27, count 2 2006.257.22:18:53.95#ibcon#flushed, iclass 27, count 2 2006.257.22:18:53.95#ibcon#about to write, iclass 27, count 2 2006.257.22:18:53.95#ibcon#wrote, iclass 27, count 2 2006.257.22:18:53.95#ibcon#about to read 3, iclass 27, count 2 2006.257.22:18:53.97#ibcon#read 3, iclass 27, count 2 2006.257.22:18:53.97#ibcon#about to read 4, iclass 27, count 2 2006.257.22:18:53.97#ibcon#read 4, iclass 27, count 2 2006.257.22:18:53.97#ibcon#about to read 5, iclass 27, count 2 2006.257.22:18:53.97#ibcon#read 5, iclass 27, count 2 2006.257.22:18:53.97#ibcon#about to read 6, iclass 27, count 2 2006.257.22:18:53.97#ibcon#read 6, iclass 27, count 2 2006.257.22:18:53.97#ibcon#end of sib2, iclass 27, count 2 2006.257.22:18:53.97#ibcon#*mode == 0, iclass 27, count 2 2006.257.22:18:53.97#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.22:18:53.97#ibcon#[25=AT05-04\r\n] 2006.257.22:18:53.97#ibcon#*before write, iclass 27, count 2 2006.257.22:18:53.97#ibcon#enter sib2, iclass 27, count 2 2006.257.22:18:53.97#ibcon#flushed, iclass 27, count 2 2006.257.22:18:53.97#ibcon#about to write, iclass 27, count 2 2006.257.22:18:53.97#ibcon#wrote, iclass 27, count 2 2006.257.22:18:53.97#ibcon#about to read 3, iclass 27, count 2 2006.257.22:18:54.00#ibcon#read 3, iclass 27, count 2 2006.257.22:18:54.00#ibcon#about to read 4, iclass 27, count 2 2006.257.22:18:54.00#ibcon#read 4, iclass 27, count 2 2006.257.22:18:54.00#ibcon#about to read 5, iclass 27, count 2 2006.257.22:18:54.00#ibcon#read 5, iclass 27, count 2 2006.257.22:18:54.00#ibcon#about to read 6, iclass 27, count 2 2006.257.22:18:54.00#ibcon#read 6, iclass 27, count 2 2006.257.22:18:54.00#ibcon#end of sib2, iclass 27, count 2 2006.257.22:18:54.00#ibcon#*after write, iclass 27, count 2 2006.257.22:18:54.00#ibcon#*before return 0, iclass 27, count 2 2006.257.22:18:54.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:54.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:54.00#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.22:18:54.00#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:54.00#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:54.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:54.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:54.12#ibcon#enter wrdev, iclass 27, count 0 2006.257.22:18:54.12#ibcon#first serial, iclass 27, count 0 2006.257.22:18:54.12#ibcon#enter sib2, iclass 27, count 0 2006.257.22:18:54.12#ibcon#flushed, iclass 27, count 0 2006.257.22:18:54.12#ibcon#about to write, iclass 27, count 0 2006.257.22:18:54.12#ibcon#wrote, iclass 27, count 0 2006.257.22:18:54.12#ibcon#about to read 3, iclass 27, count 0 2006.257.22:18:54.14#ibcon#read 3, iclass 27, count 0 2006.257.22:18:54.14#ibcon#about to read 4, iclass 27, count 0 2006.257.22:18:54.14#ibcon#read 4, iclass 27, count 0 2006.257.22:18:54.14#ibcon#about to read 5, iclass 27, count 0 2006.257.22:18:54.14#ibcon#read 5, iclass 27, count 0 2006.257.22:18:54.14#ibcon#about to read 6, iclass 27, count 0 2006.257.22:18:54.14#ibcon#read 6, iclass 27, count 0 2006.257.22:18:54.14#ibcon#end of sib2, iclass 27, count 0 2006.257.22:18:54.14#ibcon#*mode == 0, iclass 27, count 0 2006.257.22:18:54.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.22:18:54.14#ibcon#[25=USB\r\n] 2006.257.22:18:54.14#ibcon#*before write, iclass 27, count 0 2006.257.22:18:54.14#ibcon#enter sib2, iclass 27, count 0 2006.257.22:18:54.14#ibcon#flushed, iclass 27, count 0 2006.257.22:18:54.14#ibcon#about to write, iclass 27, count 0 2006.257.22:18:54.14#ibcon#wrote, iclass 27, count 0 2006.257.22:18:54.14#ibcon#about to read 3, iclass 27, count 0 2006.257.22:18:54.17#ibcon#read 3, iclass 27, count 0 2006.257.22:18:54.17#ibcon#about to read 4, iclass 27, count 0 2006.257.22:18:54.17#ibcon#read 4, iclass 27, count 0 2006.257.22:18:54.17#ibcon#about to read 5, iclass 27, count 0 2006.257.22:18:54.17#ibcon#read 5, iclass 27, count 0 2006.257.22:18:54.17#ibcon#about to read 6, iclass 27, count 0 2006.257.22:18:54.17#ibcon#read 6, iclass 27, count 0 2006.257.22:18:54.17#ibcon#end of sib2, iclass 27, count 0 2006.257.22:18:54.17#ibcon#*after write, iclass 27, count 0 2006.257.22:18:54.17#ibcon#*before return 0, iclass 27, count 0 2006.257.22:18:54.17#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:54.17#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:54.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.22:18:54.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.22:18:54.17$vck44/valo=6,814.99 2006.257.22:18:54.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.22:18:54.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.22:18:54.17#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:54.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:54.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:54.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:54.17#ibcon#enter wrdev, iclass 29, count 0 2006.257.22:18:54.17#ibcon#first serial, iclass 29, count 0 2006.257.22:18:54.17#ibcon#enter sib2, iclass 29, count 0 2006.257.22:18:54.17#ibcon#flushed, iclass 29, count 0 2006.257.22:18:54.17#ibcon#about to write, iclass 29, count 0 2006.257.22:18:54.17#ibcon#wrote, iclass 29, count 0 2006.257.22:18:54.17#ibcon#about to read 3, iclass 29, count 0 2006.257.22:18:54.19#ibcon#read 3, iclass 29, count 0 2006.257.22:18:54.19#ibcon#about to read 4, iclass 29, count 0 2006.257.22:18:54.19#ibcon#read 4, iclass 29, count 0 2006.257.22:18:54.19#ibcon#about to read 5, iclass 29, count 0 2006.257.22:18:54.19#ibcon#read 5, iclass 29, count 0 2006.257.22:18:54.19#ibcon#about to read 6, iclass 29, count 0 2006.257.22:18:54.19#ibcon#read 6, iclass 29, count 0 2006.257.22:18:54.19#ibcon#end of sib2, iclass 29, count 0 2006.257.22:18:54.19#ibcon#*mode == 0, iclass 29, count 0 2006.257.22:18:54.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.22:18:54.19#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.22:18:54.19#ibcon#*before write, iclass 29, count 0 2006.257.22:18:54.19#ibcon#enter sib2, iclass 29, count 0 2006.257.22:18:54.19#ibcon#flushed, iclass 29, count 0 2006.257.22:18:54.19#ibcon#about to write, iclass 29, count 0 2006.257.22:18:54.19#ibcon#wrote, iclass 29, count 0 2006.257.22:18:54.19#ibcon#about to read 3, iclass 29, count 0 2006.257.22:18:54.23#ibcon#read 3, iclass 29, count 0 2006.257.22:18:54.23#ibcon#about to read 4, iclass 29, count 0 2006.257.22:18:54.23#ibcon#read 4, iclass 29, count 0 2006.257.22:18:54.23#ibcon#about to read 5, iclass 29, count 0 2006.257.22:18:54.23#ibcon#read 5, iclass 29, count 0 2006.257.22:18:54.23#ibcon#about to read 6, iclass 29, count 0 2006.257.22:18:54.23#ibcon#read 6, iclass 29, count 0 2006.257.22:18:54.23#ibcon#end of sib2, iclass 29, count 0 2006.257.22:18:54.23#ibcon#*after write, iclass 29, count 0 2006.257.22:18:54.23#ibcon#*before return 0, iclass 29, count 0 2006.257.22:18:54.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:54.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:54.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.22:18:54.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.22:18:54.23$vck44/va=6,4 2006.257.22:18:54.23#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.22:18:54.23#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.22:18:54.23#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:54.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:54.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:54.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:54.29#ibcon#enter wrdev, iclass 31, count 2 2006.257.22:18:54.29#ibcon#first serial, iclass 31, count 2 2006.257.22:18:54.29#ibcon#enter sib2, iclass 31, count 2 2006.257.22:18:54.29#ibcon#flushed, iclass 31, count 2 2006.257.22:18:54.29#ibcon#about to write, iclass 31, count 2 2006.257.22:18:54.29#ibcon#wrote, iclass 31, count 2 2006.257.22:18:54.29#ibcon#about to read 3, iclass 31, count 2 2006.257.22:18:54.31#ibcon#read 3, iclass 31, count 2 2006.257.22:18:54.31#ibcon#about to read 4, iclass 31, count 2 2006.257.22:18:54.31#ibcon#read 4, iclass 31, count 2 2006.257.22:18:54.31#ibcon#about to read 5, iclass 31, count 2 2006.257.22:18:54.31#ibcon#read 5, iclass 31, count 2 2006.257.22:18:54.31#ibcon#about to read 6, iclass 31, count 2 2006.257.22:18:54.31#ibcon#read 6, iclass 31, count 2 2006.257.22:18:54.31#ibcon#end of sib2, iclass 31, count 2 2006.257.22:18:54.31#ibcon#*mode == 0, iclass 31, count 2 2006.257.22:18:54.31#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.22:18:54.31#ibcon#[25=AT06-04\r\n] 2006.257.22:18:54.31#ibcon#*before write, iclass 31, count 2 2006.257.22:18:54.31#ibcon#enter sib2, iclass 31, count 2 2006.257.22:18:54.31#ibcon#flushed, iclass 31, count 2 2006.257.22:18:54.31#ibcon#about to write, iclass 31, count 2 2006.257.22:18:54.31#ibcon#wrote, iclass 31, count 2 2006.257.22:18:54.31#ibcon#about to read 3, iclass 31, count 2 2006.257.22:18:54.34#ibcon#read 3, iclass 31, count 2 2006.257.22:18:54.34#ibcon#about to read 4, iclass 31, count 2 2006.257.22:18:54.34#ibcon#read 4, iclass 31, count 2 2006.257.22:18:54.34#ibcon#about to read 5, iclass 31, count 2 2006.257.22:18:54.34#ibcon#read 5, iclass 31, count 2 2006.257.22:18:54.34#ibcon#about to read 6, iclass 31, count 2 2006.257.22:18:54.34#ibcon#read 6, iclass 31, count 2 2006.257.22:18:54.34#ibcon#end of sib2, iclass 31, count 2 2006.257.22:18:54.34#ibcon#*after write, iclass 31, count 2 2006.257.22:18:54.34#ibcon#*before return 0, iclass 31, count 2 2006.257.22:18:54.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:54.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:54.34#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.22:18:54.34#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:54.34#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:54.46#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:54.46#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:54.46#ibcon#enter wrdev, iclass 31, count 0 2006.257.22:18:54.46#ibcon#first serial, iclass 31, count 0 2006.257.22:18:54.46#ibcon#enter sib2, iclass 31, count 0 2006.257.22:18:54.46#ibcon#flushed, iclass 31, count 0 2006.257.22:18:54.46#ibcon#about to write, iclass 31, count 0 2006.257.22:18:54.46#ibcon#wrote, iclass 31, count 0 2006.257.22:18:54.46#ibcon#about to read 3, iclass 31, count 0 2006.257.22:18:54.48#ibcon#read 3, iclass 31, count 0 2006.257.22:18:54.48#ibcon#about to read 4, iclass 31, count 0 2006.257.22:18:54.48#ibcon#read 4, iclass 31, count 0 2006.257.22:18:54.48#ibcon#about to read 5, iclass 31, count 0 2006.257.22:18:54.48#ibcon#read 5, iclass 31, count 0 2006.257.22:18:54.48#ibcon#about to read 6, iclass 31, count 0 2006.257.22:18:54.48#ibcon#read 6, iclass 31, count 0 2006.257.22:18:54.48#ibcon#end of sib2, iclass 31, count 0 2006.257.22:18:54.48#ibcon#*mode == 0, iclass 31, count 0 2006.257.22:18:54.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.22:18:54.48#ibcon#[25=USB\r\n] 2006.257.22:18:54.48#ibcon#*before write, iclass 31, count 0 2006.257.22:18:54.48#ibcon#enter sib2, iclass 31, count 0 2006.257.22:18:54.48#ibcon#flushed, iclass 31, count 0 2006.257.22:18:54.48#ibcon#about to write, iclass 31, count 0 2006.257.22:18:54.48#ibcon#wrote, iclass 31, count 0 2006.257.22:18:54.48#ibcon#about to read 3, iclass 31, count 0 2006.257.22:18:54.51#ibcon#read 3, iclass 31, count 0 2006.257.22:18:54.51#ibcon#about to read 4, iclass 31, count 0 2006.257.22:18:54.51#ibcon#read 4, iclass 31, count 0 2006.257.22:18:54.51#ibcon#about to read 5, iclass 31, count 0 2006.257.22:18:54.51#ibcon#read 5, iclass 31, count 0 2006.257.22:18:54.51#ibcon#about to read 6, iclass 31, count 0 2006.257.22:18:54.51#ibcon#read 6, iclass 31, count 0 2006.257.22:18:54.51#ibcon#end of sib2, iclass 31, count 0 2006.257.22:18:54.51#ibcon#*after write, iclass 31, count 0 2006.257.22:18:54.51#ibcon#*before return 0, iclass 31, count 0 2006.257.22:18:54.51#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:54.51#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:54.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.22:18:54.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.22:18:54.51$vck44/valo=7,864.99 2006.257.22:18:54.51#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.22:18:54.51#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.22:18:54.51#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:54.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:54.51#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:54.51#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:54.51#ibcon#enter wrdev, iclass 33, count 0 2006.257.22:18:54.51#ibcon#first serial, iclass 33, count 0 2006.257.22:18:54.51#ibcon#enter sib2, iclass 33, count 0 2006.257.22:18:54.51#ibcon#flushed, iclass 33, count 0 2006.257.22:18:54.51#ibcon#about to write, iclass 33, count 0 2006.257.22:18:54.51#ibcon#wrote, iclass 33, count 0 2006.257.22:18:54.51#ibcon#about to read 3, iclass 33, count 0 2006.257.22:18:54.53#ibcon#read 3, iclass 33, count 0 2006.257.22:18:54.53#ibcon#about to read 4, iclass 33, count 0 2006.257.22:18:54.53#ibcon#read 4, iclass 33, count 0 2006.257.22:18:54.53#ibcon#about to read 5, iclass 33, count 0 2006.257.22:18:54.53#ibcon#read 5, iclass 33, count 0 2006.257.22:18:54.53#ibcon#about to read 6, iclass 33, count 0 2006.257.22:18:54.53#ibcon#read 6, iclass 33, count 0 2006.257.22:18:54.53#ibcon#end of sib2, iclass 33, count 0 2006.257.22:18:54.53#ibcon#*mode == 0, iclass 33, count 0 2006.257.22:18:54.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.22:18:54.53#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.22:18:54.53#ibcon#*before write, iclass 33, count 0 2006.257.22:18:54.53#ibcon#enter sib2, iclass 33, count 0 2006.257.22:18:54.53#ibcon#flushed, iclass 33, count 0 2006.257.22:18:54.53#ibcon#about to write, iclass 33, count 0 2006.257.22:18:54.53#ibcon#wrote, iclass 33, count 0 2006.257.22:18:54.53#ibcon#about to read 3, iclass 33, count 0 2006.257.22:18:54.57#ibcon#read 3, iclass 33, count 0 2006.257.22:18:54.57#ibcon#about to read 4, iclass 33, count 0 2006.257.22:18:54.57#ibcon#read 4, iclass 33, count 0 2006.257.22:18:54.57#ibcon#about to read 5, iclass 33, count 0 2006.257.22:18:54.57#ibcon#read 5, iclass 33, count 0 2006.257.22:18:54.57#ibcon#about to read 6, iclass 33, count 0 2006.257.22:18:54.57#ibcon#read 6, iclass 33, count 0 2006.257.22:18:54.57#ibcon#end of sib2, iclass 33, count 0 2006.257.22:18:54.57#ibcon#*after write, iclass 33, count 0 2006.257.22:18:54.57#ibcon#*before return 0, iclass 33, count 0 2006.257.22:18:54.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:54.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:54.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.22:18:54.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.22:18:54.57$vck44/va=7,4 2006.257.22:18:54.57#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.22:18:54.57#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.22:18:54.57#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:54.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:54.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:54.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:54.63#ibcon#enter wrdev, iclass 35, count 2 2006.257.22:18:54.63#ibcon#first serial, iclass 35, count 2 2006.257.22:18:54.63#ibcon#enter sib2, iclass 35, count 2 2006.257.22:18:54.63#ibcon#flushed, iclass 35, count 2 2006.257.22:18:54.63#ibcon#about to write, iclass 35, count 2 2006.257.22:18:54.63#ibcon#wrote, iclass 35, count 2 2006.257.22:18:54.63#ibcon#about to read 3, iclass 35, count 2 2006.257.22:18:54.65#ibcon#read 3, iclass 35, count 2 2006.257.22:18:54.65#ibcon#about to read 4, iclass 35, count 2 2006.257.22:18:54.65#ibcon#read 4, iclass 35, count 2 2006.257.22:18:54.65#ibcon#about to read 5, iclass 35, count 2 2006.257.22:18:54.65#ibcon#read 5, iclass 35, count 2 2006.257.22:18:54.65#ibcon#about to read 6, iclass 35, count 2 2006.257.22:18:54.65#ibcon#read 6, iclass 35, count 2 2006.257.22:18:54.65#ibcon#end of sib2, iclass 35, count 2 2006.257.22:18:54.65#ibcon#*mode == 0, iclass 35, count 2 2006.257.22:18:54.65#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.22:18:54.65#ibcon#[25=AT07-04\r\n] 2006.257.22:18:54.65#ibcon#*before write, iclass 35, count 2 2006.257.22:18:54.65#ibcon#enter sib2, iclass 35, count 2 2006.257.22:18:54.65#ibcon#flushed, iclass 35, count 2 2006.257.22:18:54.65#ibcon#about to write, iclass 35, count 2 2006.257.22:18:54.65#ibcon#wrote, iclass 35, count 2 2006.257.22:18:54.65#ibcon#about to read 3, iclass 35, count 2 2006.257.22:18:54.68#ibcon#read 3, iclass 35, count 2 2006.257.22:18:54.68#ibcon#about to read 4, iclass 35, count 2 2006.257.22:18:54.68#ibcon#read 4, iclass 35, count 2 2006.257.22:18:54.68#ibcon#about to read 5, iclass 35, count 2 2006.257.22:18:54.68#ibcon#read 5, iclass 35, count 2 2006.257.22:18:54.68#ibcon#about to read 6, iclass 35, count 2 2006.257.22:18:54.68#ibcon#read 6, iclass 35, count 2 2006.257.22:18:54.68#ibcon#end of sib2, iclass 35, count 2 2006.257.22:18:54.68#ibcon#*after write, iclass 35, count 2 2006.257.22:18:54.68#ibcon#*before return 0, iclass 35, count 2 2006.257.22:18:54.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:54.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:54.68#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.22:18:54.68#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:54.68#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:54.80#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:54.80#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:54.80#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:18:54.80#ibcon#first serial, iclass 35, count 0 2006.257.22:18:54.80#ibcon#enter sib2, iclass 35, count 0 2006.257.22:18:54.80#ibcon#flushed, iclass 35, count 0 2006.257.22:18:54.80#ibcon#about to write, iclass 35, count 0 2006.257.22:18:54.80#ibcon#wrote, iclass 35, count 0 2006.257.22:18:54.80#ibcon#about to read 3, iclass 35, count 0 2006.257.22:18:54.82#ibcon#read 3, iclass 35, count 0 2006.257.22:18:54.82#ibcon#about to read 4, iclass 35, count 0 2006.257.22:18:54.82#ibcon#read 4, iclass 35, count 0 2006.257.22:18:54.82#ibcon#about to read 5, iclass 35, count 0 2006.257.22:18:54.82#ibcon#read 5, iclass 35, count 0 2006.257.22:18:54.82#ibcon#about to read 6, iclass 35, count 0 2006.257.22:18:54.82#ibcon#read 6, iclass 35, count 0 2006.257.22:18:54.82#ibcon#end of sib2, iclass 35, count 0 2006.257.22:18:54.82#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:18:54.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:18:54.82#ibcon#[25=USB\r\n] 2006.257.22:18:54.82#ibcon#*before write, iclass 35, count 0 2006.257.22:18:54.82#ibcon#enter sib2, iclass 35, count 0 2006.257.22:18:54.82#ibcon#flushed, iclass 35, count 0 2006.257.22:18:54.82#ibcon#about to write, iclass 35, count 0 2006.257.22:18:54.82#ibcon#wrote, iclass 35, count 0 2006.257.22:18:54.82#ibcon#about to read 3, iclass 35, count 0 2006.257.22:18:54.85#ibcon#read 3, iclass 35, count 0 2006.257.22:18:54.85#ibcon#about to read 4, iclass 35, count 0 2006.257.22:18:54.85#ibcon#read 4, iclass 35, count 0 2006.257.22:18:54.85#ibcon#about to read 5, iclass 35, count 0 2006.257.22:18:54.85#ibcon#read 5, iclass 35, count 0 2006.257.22:18:54.85#ibcon#about to read 6, iclass 35, count 0 2006.257.22:18:54.85#ibcon#read 6, iclass 35, count 0 2006.257.22:18:54.85#ibcon#end of sib2, iclass 35, count 0 2006.257.22:18:54.85#ibcon#*after write, iclass 35, count 0 2006.257.22:18:54.85#ibcon#*before return 0, iclass 35, count 0 2006.257.22:18:54.85#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:54.85#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:54.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:18:54.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:18:54.85$vck44/valo=8,884.99 2006.257.22:18:54.85#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.22:18:54.85#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.22:18:54.85#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:54.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:54.85#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:54.85#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:54.85#ibcon#enter wrdev, iclass 37, count 0 2006.257.22:18:54.85#ibcon#first serial, iclass 37, count 0 2006.257.22:18:54.85#ibcon#enter sib2, iclass 37, count 0 2006.257.22:18:54.85#ibcon#flushed, iclass 37, count 0 2006.257.22:18:54.85#ibcon#about to write, iclass 37, count 0 2006.257.22:18:54.85#ibcon#wrote, iclass 37, count 0 2006.257.22:18:54.85#ibcon#about to read 3, iclass 37, count 0 2006.257.22:18:54.87#ibcon#read 3, iclass 37, count 0 2006.257.22:18:54.87#ibcon#about to read 4, iclass 37, count 0 2006.257.22:18:54.87#ibcon#read 4, iclass 37, count 0 2006.257.22:18:54.87#ibcon#about to read 5, iclass 37, count 0 2006.257.22:18:54.87#ibcon#read 5, iclass 37, count 0 2006.257.22:18:54.87#ibcon#about to read 6, iclass 37, count 0 2006.257.22:18:54.87#ibcon#read 6, iclass 37, count 0 2006.257.22:18:54.87#ibcon#end of sib2, iclass 37, count 0 2006.257.22:18:54.87#ibcon#*mode == 0, iclass 37, count 0 2006.257.22:18:54.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.22:18:54.87#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.22:18:54.87#ibcon#*before write, iclass 37, count 0 2006.257.22:18:54.87#ibcon#enter sib2, iclass 37, count 0 2006.257.22:18:54.87#ibcon#flushed, iclass 37, count 0 2006.257.22:18:54.87#ibcon#about to write, iclass 37, count 0 2006.257.22:18:54.87#ibcon#wrote, iclass 37, count 0 2006.257.22:18:54.87#ibcon#about to read 3, iclass 37, count 0 2006.257.22:18:54.91#ibcon#read 3, iclass 37, count 0 2006.257.22:18:54.91#ibcon#about to read 4, iclass 37, count 0 2006.257.22:18:54.91#ibcon#read 4, iclass 37, count 0 2006.257.22:18:54.91#ibcon#about to read 5, iclass 37, count 0 2006.257.22:18:54.91#ibcon#read 5, iclass 37, count 0 2006.257.22:18:54.91#ibcon#about to read 6, iclass 37, count 0 2006.257.22:18:54.91#ibcon#read 6, iclass 37, count 0 2006.257.22:18:54.91#ibcon#end of sib2, iclass 37, count 0 2006.257.22:18:54.91#ibcon#*after write, iclass 37, count 0 2006.257.22:18:54.91#ibcon#*before return 0, iclass 37, count 0 2006.257.22:18:54.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:54.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:54.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.22:18:54.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.22:18:54.91$vck44/va=8,4 2006.257.22:18:54.91#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.22:18:54.91#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.22:18:54.91#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:54.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:18:54.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:18:54.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:18:54.97#ibcon#enter wrdev, iclass 39, count 2 2006.257.22:18:54.97#ibcon#first serial, iclass 39, count 2 2006.257.22:18:54.97#ibcon#enter sib2, iclass 39, count 2 2006.257.22:18:54.97#ibcon#flushed, iclass 39, count 2 2006.257.22:18:54.97#ibcon#about to write, iclass 39, count 2 2006.257.22:18:54.97#ibcon#wrote, iclass 39, count 2 2006.257.22:18:54.97#ibcon#about to read 3, iclass 39, count 2 2006.257.22:18:54.99#ibcon#read 3, iclass 39, count 2 2006.257.22:18:54.99#ibcon#about to read 4, iclass 39, count 2 2006.257.22:18:54.99#ibcon#read 4, iclass 39, count 2 2006.257.22:18:54.99#ibcon#about to read 5, iclass 39, count 2 2006.257.22:18:54.99#ibcon#read 5, iclass 39, count 2 2006.257.22:18:54.99#ibcon#about to read 6, iclass 39, count 2 2006.257.22:18:54.99#ibcon#read 6, iclass 39, count 2 2006.257.22:18:54.99#ibcon#end of sib2, iclass 39, count 2 2006.257.22:18:54.99#ibcon#*mode == 0, iclass 39, count 2 2006.257.22:18:54.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.22:18:54.99#ibcon#[25=AT08-04\r\n] 2006.257.22:18:54.99#ibcon#*before write, iclass 39, count 2 2006.257.22:18:54.99#ibcon#enter sib2, iclass 39, count 2 2006.257.22:18:54.99#ibcon#flushed, iclass 39, count 2 2006.257.22:18:54.99#ibcon#about to write, iclass 39, count 2 2006.257.22:18:54.99#ibcon#wrote, iclass 39, count 2 2006.257.22:18:54.99#ibcon#about to read 3, iclass 39, count 2 2006.257.22:18:55.02#ibcon#read 3, iclass 39, count 2 2006.257.22:18:55.02#ibcon#about to read 4, iclass 39, count 2 2006.257.22:18:55.02#ibcon#read 4, iclass 39, count 2 2006.257.22:18:55.02#ibcon#about to read 5, iclass 39, count 2 2006.257.22:18:55.02#ibcon#read 5, iclass 39, count 2 2006.257.22:18:55.02#ibcon#about to read 6, iclass 39, count 2 2006.257.22:18:55.02#ibcon#read 6, iclass 39, count 2 2006.257.22:18:55.02#ibcon#end of sib2, iclass 39, count 2 2006.257.22:18:55.02#ibcon#*after write, iclass 39, count 2 2006.257.22:18:55.02#ibcon#*before return 0, iclass 39, count 2 2006.257.22:18:55.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:18:55.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:18:55.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.22:18:55.02#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:55.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:18:55.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:18:55.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:18:55.14#ibcon#enter wrdev, iclass 39, count 0 2006.257.22:18:55.14#ibcon#first serial, iclass 39, count 0 2006.257.22:18:55.14#ibcon#enter sib2, iclass 39, count 0 2006.257.22:18:55.14#ibcon#flushed, iclass 39, count 0 2006.257.22:18:55.14#ibcon#about to write, iclass 39, count 0 2006.257.22:18:55.14#ibcon#wrote, iclass 39, count 0 2006.257.22:18:55.14#ibcon#about to read 3, iclass 39, count 0 2006.257.22:18:55.16#ibcon#read 3, iclass 39, count 0 2006.257.22:18:55.16#ibcon#about to read 4, iclass 39, count 0 2006.257.22:18:55.16#ibcon#read 4, iclass 39, count 0 2006.257.22:18:55.16#ibcon#about to read 5, iclass 39, count 0 2006.257.22:18:55.16#ibcon#read 5, iclass 39, count 0 2006.257.22:18:55.16#ibcon#about to read 6, iclass 39, count 0 2006.257.22:18:55.16#ibcon#read 6, iclass 39, count 0 2006.257.22:18:55.16#ibcon#end of sib2, iclass 39, count 0 2006.257.22:18:55.16#ibcon#*mode == 0, iclass 39, count 0 2006.257.22:18:55.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.22:18:55.16#ibcon#[25=USB\r\n] 2006.257.22:18:55.16#ibcon#*before write, iclass 39, count 0 2006.257.22:18:55.16#ibcon#enter sib2, iclass 39, count 0 2006.257.22:18:55.16#ibcon#flushed, iclass 39, count 0 2006.257.22:18:55.16#ibcon#about to write, iclass 39, count 0 2006.257.22:18:55.16#ibcon#wrote, iclass 39, count 0 2006.257.22:18:55.16#ibcon#about to read 3, iclass 39, count 0 2006.257.22:18:55.19#ibcon#read 3, iclass 39, count 0 2006.257.22:18:55.19#ibcon#about to read 4, iclass 39, count 0 2006.257.22:18:55.19#ibcon#read 4, iclass 39, count 0 2006.257.22:18:55.19#ibcon#about to read 5, iclass 39, count 0 2006.257.22:18:55.19#ibcon#read 5, iclass 39, count 0 2006.257.22:18:55.19#ibcon#about to read 6, iclass 39, count 0 2006.257.22:18:55.19#ibcon#read 6, iclass 39, count 0 2006.257.22:18:55.19#ibcon#end of sib2, iclass 39, count 0 2006.257.22:18:55.19#ibcon#*after write, iclass 39, count 0 2006.257.22:18:55.19#ibcon#*before return 0, iclass 39, count 0 2006.257.22:18:55.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:18:55.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:18:55.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.22:18:55.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.22:18:55.19$vck44/vblo=1,629.99 2006.257.22:18:55.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.22:18:55.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.22:18:55.19#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:55.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:55.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:55.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:55.19#ibcon#enter wrdev, iclass 3, count 0 2006.257.22:18:55.19#ibcon#first serial, iclass 3, count 0 2006.257.22:18:55.19#ibcon#enter sib2, iclass 3, count 0 2006.257.22:18:55.19#ibcon#flushed, iclass 3, count 0 2006.257.22:18:55.19#ibcon#about to write, iclass 3, count 0 2006.257.22:18:55.19#ibcon#wrote, iclass 3, count 0 2006.257.22:18:55.19#ibcon#about to read 3, iclass 3, count 0 2006.257.22:18:55.21#ibcon#read 3, iclass 3, count 0 2006.257.22:18:55.21#ibcon#about to read 4, iclass 3, count 0 2006.257.22:18:55.21#ibcon#read 4, iclass 3, count 0 2006.257.22:18:55.21#ibcon#about to read 5, iclass 3, count 0 2006.257.22:18:55.21#ibcon#read 5, iclass 3, count 0 2006.257.22:18:55.21#ibcon#about to read 6, iclass 3, count 0 2006.257.22:18:55.21#ibcon#read 6, iclass 3, count 0 2006.257.22:18:55.21#ibcon#end of sib2, iclass 3, count 0 2006.257.22:18:55.21#ibcon#*mode == 0, iclass 3, count 0 2006.257.22:18:55.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.22:18:55.21#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.22:18:55.21#ibcon#*before write, iclass 3, count 0 2006.257.22:18:55.21#ibcon#enter sib2, iclass 3, count 0 2006.257.22:18:55.21#ibcon#flushed, iclass 3, count 0 2006.257.22:18:55.21#ibcon#about to write, iclass 3, count 0 2006.257.22:18:55.21#ibcon#wrote, iclass 3, count 0 2006.257.22:18:55.21#ibcon#about to read 3, iclass 3, count 0 2006.257.22:18:55.25#ibcon#read 3, iclass 3, count 0 2006.257.22:18:55.25#ibcon#about to read 4, iclass 3, count 0 2006.257.22:18:55.25#ibcon#read 4, iclass 3, count 0 2006.257.22:18:55.25#ibcon#about to read 5, iclass 3, count 0 2006.257.22:18:55.25#ibcon#read 5, iclass 3, count 0 2006.257.22:18:55.25#ibcon#about to read 6, iclass 3, count 0 2006.257.22:18:55.25#ibcon#read 6, iclass 3, count 0 2006.257.22:18:55.25#ibcon#end of sib2, iclass 3, count 0 2006.257.22:18:55.25#ibcon#*after write, iclass 3, count 0 2006.257.22:18:55.25#ibcon#*before return 0, iclass 3, count 0 2006.257.22:18:55.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:55.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:18:55.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.22:18:55.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.22:18:55.25$vck44/vb=1,4 2006.257.22:18:55.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.22:18:55.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.22:18:55.25#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:55.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:55.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:55.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:55.25#ibcon#enter wrdev, iclass 5, count 2 2006.257.22:18:55.25#ibcon#first serial, iclass 5, count 2 2006.257.22:18:55.25#ibcon#enter sib2, iclass 5, count 2 2006.257.22:18:55.25#ibcon#flushed, iclass 5, count 2 2006.257.22:18:55.25#ibcon#about to write, iclass 5, count 2 2006.257.22:18:55.25#ibcon#wrote, iclass 5, count 2 2006.257.22:18:55.25#ibcon#about to read 3, iclass 5, count 2 2006.257.22:18:55.27#ibcon#read 3, iclass 5, count 2 2006.257.22:18:55.27#ibcon#about to read 4, iclass 5, count 2 2006.257.22:18:55.27#ibcon#read 4, iclass 5, count 2 2006.257.22:18:55.27#ibcon#about to read 5, iclass 5, count 2 2006.257.22:18:55.27#ibcon#read 5, iclass 5, count 2 2006.257.22:18:55.27#ibcon#about to read 6, iclass 5, count 2 2006.257.22:18:55.27#ibcon#read 6, iclass 5, count 2 2006.257.22:18:55.27#ibcon#end of sib2, iclass 5, count 2 2006.257.22:18:55.27#ibcon#*mode == 0, iclass 5, count 2 2006.257.22:18:55.27#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.22:18:55.27#ibcon#[27=AT01-04\r\n] 2006.257.22:18:55.27#ibcon#*before write, iclass 5, count 2 2006.257.22:18:55.27#ibcon#enter sib2, iclass 5, count 2 2006.257.22:18:55.27#ibcon#flushed, iclass 5, count 2 2006.257.22:18:55.27#ibcon#about to write, iclass 5, count 2 2006.257.22:18:55.27#ibcon#wrote, iclass 5, count 2 2006.257.22:18:55.27#ibcon#about to read 3, iclass 5, count 2 2006.257.22:18:55.30#ibcon#read 3, iclass 5, count 2 2006.257.22:18:55.30#ibcon#about to read 4, iclass 5, count 2 2006.257.22:18:55.30#ibcon#read 4, iclass 5, count 2 2006.257.22:18:55.30#ibcon#about to read 5, iclass 5, count 2 2006.257.22:18:55.30#ibcon#read 5, iclass 5, count 2 2006.257.22:18:55.30#ibcon#about to read 6, iclass 5, count 2 2006.257.22:18:55.30#ibcon#read 6, iclass 5, count 2 2006.257.22:18:55.30#ibcon#end of sib2, iclass 5, count 2 2006.257.22:18:55.30#ibcon#*after write, iclass 5, count 2 2006.257.22:18:55.30#ibcon#*before return 0, iclass 5, count 2 2006.257.22:18:55.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:55.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:18:55.30#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.22:18:55.30#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:55.30#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:55.42#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:55.42#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:55.42#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:18:55.42#ibcon#first serial, iclass 5, count 0 2006.257.22:18:55.42#ibcon#enter sib2, iclass 5, count 0 2006.257.22:18:55.42#ibcon#flushed, iclass 5, count 0 2006.257.22:18:55.42#ibcon#about to write, iclass 5, count 0 2006.257.22:18:55.42#ibcon#wrote, iclass 5, count 0 2006.257.22:18:55.42#ibcon#about to read 3, iclass 5, count 0 2006.257.22:18:55.44#ibcon#read 3, iclass 5, count 0 2006.257.22:18:55.44#ibcon#about to read 4, iclass 5, count 0 2006.257.22:18:55.44#ibcon#read 4, iclass 5, count 0 2006.257.22:18:55.44#ibcon#about to read 5, iclass 5, count 0 2006.257.22:18:55.44#ibcon#read 5, iclass 5, count 0 2006.257.22:18:55.44#ibcon#about to read 6, iclass 5, count 0 2006.257.22:18:55.44#ibcon#read 6, iclass 5, count 0 2006.257.22:18:55.44#ibcon#end of sib2, iclass 5, count 0 2006.257.22:18:55.44#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:18:55.44#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:18:55.44#ibcon#[27=USB\r\n] 2006.257.22:18:55.44#ibcon#*before write, iclass 5, count 0 2006.257.22:18:55.44#ibcon#enter sib2, iclass 5, count 0 2006.257.22:18:55.44#ibcon#flushed, iclass 5, count 0 2006.257.22:18:55.44#ibcon#about to write, iclass 5, count 0 2006.257.22:18:55.44#ibcon#wrote, iclass 5, count 0 2006.257.22:18:55.44#ibcon#about to read 3, iclass 5, count 0 2006.257.22:18:55.47#ibcon#read 3, iclass 5, count 0 2006.257.22:18:55.47#ibcon#about to read 4, iclass 5, count 0 2006.257.22:18:55.47#ibcon#read 4, iclass 5, count 0 2006.257.22:18:55.47#ibcon#about to read 5, iclass 5, count 0 2006.257.22:18:55.47#ibcon#read 5, iclass 5, count 0 2006.257.22:18:55.47#ibcon#about to read 6, iclass 5, count 0 2006.257.22:18:55.47#ibcon#read 6, iclass 5, count 0 2006.257.22:18:55.47#ibcon#end of sib2, iclass 5, count 0 2006.257.22:18:55.47#ibcon#*after write, iclass 5, count 0 2006.257.22:18:55.47#ibcon#*before return 0, iclass 5, count 0 2006.257.22:18:55.47#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:55.47#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:18:55.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:18:55.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:18:55.47$vck44/vblo=2,634.99 2006.257.22:18:55.47#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.22:18:55.47#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.22:18:55.47#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:55.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:55.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:55.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:55.47#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:18:55.47#ibcon#first serial, iclass 7, count 0 2006.257.22:18:55.47#ibcon#enter sib2, iclass 7, count 0 2006.257.22:18:55.47#ibcon#flushed, iclass 7, count 0 2006.257.22:18:55.47#ibcon#about to write, iclass 7, count 0 2006.257.22:18:55.47#ibcon#wrote, iclass 7, count 0 2006.257.22:18:55.47#ibcon#about to read 3, iclass 7, count 0 2006.257.22:18:55.49#ibcon#read 3, iclass 7, count 0 2006.257.22:18:55.49#ibcon#about to read 4, iclass 7, count 0 2006.257.22:18:55.49#ibcon#read 4, iclass 7, count 0 2006.257.22:18:55.49#ibcon#about to read 5, iclass 7, count 0 2006.257.22:18:55.49#ibcon#read 5, iclass 7, count 0 2006.257.22:18:55.49#ibcon#about to read 6, iclass 7, count 0 2006.257.22:18:55.49#ibcon#read 6, iclass 7, count 0 2006.257.22:18:55.49#ibcon#end of sib2, iclass 7, count 0 2006.257.22:18:55.49#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:18:55.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:18:55.49#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.22:18:55.49#ibcon#*before write, iclass 7, count 0 2006.257.22:18:55.49#ibcon#enter sib2, iclass 7, count 0 2006.257.22:18:55.49#ibcon#flushed, iclass 7, count 0 2006.257.22:18:55.49#ibcon#about to write, iclass 7, count 0 2006.257.22:18:55.49#ibcon#wrote, iclass 7, count 0 2006.257.22:18:55.49#ibcon#about to read 3, iclass 7, count 0 2006.257.22:18:55.53#ibcon#read 3, iclass 7, count 0 2006.257.22:18:55.53#ibcon#about to read 4, iclass 7, count 0 2006.257.22:18:55.53#ibcon#read 4, iclass 7, count 0 2006.257.22:18:55.53#ibcon#about to read 5, iclass 7, count 0 2006.257.22:18:55.53#ibcon#read 5, iclass 7, count 0 2006.257.22:18:55.53#ibcon#about to read 6, iclass 7, count 0 2006.257.22:18:55.53#ibcon#read 6, iclass 7, count 0 2006.257.22:18:55.53#ibcon#end of sib2, iclass 7, count 0 2006.257.22:18:55.53#ibcon#*after write, iclass 7, count 0 2006.257.22:18:55.53#ibcon#*before return 0, iclass 7, count 0 2006.257.22:18:55.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:55.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:18:55.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:18:55.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:18:55.53$vck44/vb=2,5 2006.257.22:18:55.53#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.22:18:55.53#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.22:18:55.53#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:55.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:55.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:55.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:55.59#ibcon#enter wrdev, iclass 11, count 2 2006.257.22:18:55.59#ibcon#first serial, iclass 11, count 2 2006.257.22:18:55.59#ibcon#enter sib2, iclass 11, count 2 2006.257.22:18:55.59#ibcon#flushed, iclass 11, count 2 2006.257.22:18:55.59#ibcon#about to write, iclass 11, count 2 2006.257.22:18:55.59#ibcon#wrote, iclass 11, count 2 2006.257.22:18:55.59#ibcon#about to read 3, iclass 11, count 2 2006.257.22:18:55.61#ibcon#read 3, iclass 11, count 2 2006.257.22:18:55.61#ibcon#about to read 4, iclass 11, count 2 2006.257.22:18:55.61#ibcon#read 4, iclass 11, count 2 2006.257.22:18:55.61#ibcon#about to read 5, iclass 11, count 2 2006.257.22:18:55.61#ibcon#read 5, iclass 11, count 2 2006.257.22:18:55.61#ibcon#about to read 6, iclass 11, count 2 2006.257.22:18:55.61#ibcon#read 6, iclass 11, count 2 2006.257.22:18:55.61#ibcon#end of sib2, iclass 11, count 2 2006.257.22:18:55.61#ibcon#*mode == 0, iclass 11, count 2 2006.257.22:18:55.61#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.22:18:55.61#ibcon#[27=AT02-05\r\n] 2006.257.22:18:55.61#ibcon#*before write, iclass 11, count 2 2006.257.22:18:55.61#ibcon#enter sib2, iclass 11, count 2 2006.257.22:18:55.61#ibcon#flushed, iclass 11, count 2 2006.257.22:18:55.61#ibcon#about to write, iclass 11, count 2 2006.257.22:18:55.61#ibcon#wrote, iclass 11, count 2 2006.257.22:18:55.61#ibcon#about to read 3, iclass 11, count 2 2006.257.22:18:55.64#ibcon#read 3, iclass 11, count 2 2006.257.22:18:55.64#ibcon#about to read 4, iclass 11, count 2 2006.257.22:18:55.64#ibcon#read 4, iclass 11, count 2 2006.257.22:18:55.64#ibcon#about to read 5, iclass 11, count 2 2006.257.22:18:55.64#ibcon#read 5, iclass 11, count 2 2006.257.22:18:55.64#ibcon#about to read 6, iclass 11, count 2 2006.257.22:18:55.64#ibcon#read 6, iclass 11, count 2 2006.257.22:18:55.64#ibcon#end of sib2, iclass 11, count 2 2006.257.22:18:55.64#ibcon#*after write, iclass 11, count 2 2006.257.22:18:55.64#ibcon#*before return 0, iclass 11, count 2 2006.257.22:18:55.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:55.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:18:55.64#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.22:18:55.64#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:55.64#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:55.76#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:55.76#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:55.76#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:18:55.76#ibcon#first serial, iclass 11, count 0 2006.257.22:18:55.76#ibcon#enter sib2, iclass 11, count 0 2006.257.22:18:55.76#ibcon#flushed, iclass 11, count 0 2006.257.22:18:55.76#ibcon#about to write, iclass 11, count 0 2006.257.22:18:55.76#ibcon#wrote, iclass 11, count 0 2006.257.22:18:55.76#ibcon#about to read 3, iclass 11, count 0 2006.257.22:18:55.78#ibcon#read 3, iclass 11, count 0 2006.257.22:18:55.78#ibcon#about to read 4, iclass 11, count 0 2006.257.22:18:55.78#ibcon#read 4, iclass 11, count 0 2006.257.22:18:55.78#ibcon#about to read 5, iclass 11, count 0 2006.257.22:18:55.78#ibcon#read 5, iclass 11, count 0 2006.257.22:18:55.78#ibcon#about to read 6, iclass 11, count 0 2006.257.22:18:55.78#ibcon#read 6, iclass 11, count 0 2006.257.22:18:55.78#ibcon#end of sib2, iclass 11, count 0 2006.257.22:18:55.78#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:18:55.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:18:55.78#ibcon#[27=USB\r\n] 2006.257.22:18:55.78#ibcon#*before write, iclass 11, count 0 2006.257.22:18:55.78#ibcon#enter sib2, iclass 11, count 0 2006.257.22:18:55.78#ibcon#flushed, iclass 11, count 0 2006.257.22:18:55.78#ibcon#about to write, iclass 11, count 0 2006.257.22:18:55.78#ibcon#wrote, iclass 11, count 0 2006.257.22:18:55.78#ibcon#about to read 3, iclass 11, count 0 2006.257.22:18:55.81#ibcon#read 3, iclass 11, count 0 2006.257.22:18:55.81#ibcon#about to read 4, iclass 11, count 0 2006.257.22:18:55.81#ibcon#read 4, iclass 11, count 0 2006.257.22:18:55.81#ibcon#about to read 5, iclass 11, count 0 2006.257.22:18:55.81#ibcon#read 5, iclass 11, count 0 2006.257.22:18:55.81#ibcon#about to read 6, iclass 11, count 0 2006.257.22:18:55.81#ibcon#read 6, iclass 11, count 0 2006.257.22:18:55.81#ibcon#end of sib2, iclass 11, count 0 2006.257.22:18:55.81#ibcon#*after write, iclass 11, count 0 2006.257.22:18:55.81#ibcon#*before return 0, iclass 11, count 0 2006.257.22:18:55.81#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:55.81#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:18:55.81#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:18:55.81#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:18:55.81$vck44/vblo=3,649.99 2006.257.22:18:55.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.22:18:55.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.22:18:55.81#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:55.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:55.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:55.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:55.81#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:18:55.81#ibcon#first serial, iclass 13, count 0 2006.257.22:18:55.81#ibcon#enter sib2, iclass 13, count 0 2006.257.22:18:55.81#ibcon#flushed, iclass 13, count 0 2006.257.22:18:55.81#ibcon#about to write, iclass 13, count 0 2006.257.22:18:55.81#ibcon#wrote, iclass 13, count 0 2006.257.22:18:55.81#ibcon#about to read 3, iclass 13, count 0 2006.257.22:18:55.83#ibcon#read 3, iclass 13, count 0 2006.257.22:18:55.83#ibcon#about to read 4, iclass 13, count 0 2006.257.22:18:55.83#ibcon#read 4, iclass 13, count 0 2006.257.22:18:55.83#ibcon#about to read 5, iclass 13, count 0 2006.257.22:18:55.83#ibcon#read 5, iclass 13, count 0 2006.257.22:18:55.83#ibcon#about to read 6, iclass 13, count 0 2006.257.22:18:55.83#ibcon#read 6, iclass 13, count 0 2006.257.22:18:55.83#ibcon#end of sib2, iclass 13, count 0 2006.257.22:18:55.83#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:18:55.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:18:55.83#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.22:18:55.83#ibcon#*before write, iclass 13, count 0 2006.257.22:18:55.83#ibcon#enter sib2, iclass 13, count 0 2006.257.22:18:55.83#ibcon#flushed, iclass 13, count 0 2006.257.22:18:55.83#ibcon#about to write, iclass 13, count 0 2006.257.22:18:55.83#ibcon#wrote, iclass 13, count 0 2006.257.22:18:55.83#ibcon#about to read 3, iclass 13, count 0 2006.257.22:18:55.87#ibcon#read 3, iclass 13, count 0 2006.257.22:18:55.87#ibcon#about to read 4, iclass 13, count 0 2006.257.22:18:55.87#ibcon#read 4, iclass 13, count 0 2006.257.22:18:55.87#ibcon#about to read 5, iclass 13, count 0 2006.257.22:18:55.87#ibcon#read 5, iclass 13, count 0 2006.257.22:18:55.87#ibcon#about to read 6, iclass 13, count 0 2006.257.22:18:55.87#ibcon#read 6, iclass 13, count 0 2006.257.22:18:55.87#ibcon#end of sib2, iclass 13, count 0 2006.257.22:18:55.87#ibcon#*after write, iclass 13, count 0 2006.257.22:18:55.87#ibcon#*before return 0, iclass 13, count 0 2006.257.22:18:55.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:55.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:18:55.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:18:55.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:18:55.87$vck44/vb=3,4 2006.257.22:18:55.87#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.22:18:55.87#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.22:18:55.87#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:55.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:55.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:55.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:55.93#ibcon#enter wrdev, iclass 15, count 2 2006.257.22:18:55.93#ibcon#first serial, iclass 15, count 2 2006.257.22:18:55.93#ibcon#enter sib2, iclass 15, count 2 2006.257.22:18:55.93#ibcon#flushed, iclass 15, count 2 2006.257.22:18:55.93#ibcon#about to write, iclass 15, count 2 2006.257.22:18:55.93#ibcon#wrote, iclass 15, count 2 2006.257.22:18:55.93#ibcon#about to read 3, iclass 15, count 2 2006.257.22:18:55.95#ibcon#read 3, iclass 15, count 2 2006.257.22:18:55.95#ibcon#about to read 4, iclass 15, count 2 2006.257.22:18:55.95#ibcon#read 4, iclass 15, count 2 2006.257.22:18:55.95#ibcon#about to read 5, iclass 15, count 2 2006.257.22:18:55.95#ibcon#read 5, iclass 15, count 2 2006.257.22:18:55.95#ibcon#about to read 6, iclass 15, count 2 2006.257.22:18:55.95#ibcon#read 6, iclass 15, count 2 2006.257.22:18:55.95#ibcon#end of sib2, iclass 15, count 2 2006.257.22:18:55.95#ibcon#*mode == 0, iclass 15, count 2 2006.257.22:18:55.95#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.22:18:55.95#ibcon#[27=AT03-04\r\n] 2006.257.22:18:55.95#ibcon#*before write, iclass 15, count 2 2006.257.22:18:55.95#ibcon#enter sib2, iclass 15, count 2 2006.257.22:18:55.95#ibcon#flushed, iclass 15, count 2 2006.257.22:18:55.95#ibcon#about to write, iclass 15, count 2 2006.257.22:18:55.95#ibcon#wrote, iclass 15, count 2 2006.257.22:18:55.95#ibcon#about to read 3, iclass 15, count 2 2006.257.22:18:55.98#ibcon#read 3, iclass 15, count 2 2006.257.22:18:55.98#ibcon#about to read 4, iclass 15, count 2 2006.257.22:18:55.98#ibcon#read 4, iclass 15, count 2 2006.257.22:18:55.98#ibcon#about to read 5, iclass 15, count 2 2006.257.22:18:55.98#ibcon#read 5, iclass 15, count 2 2006.257.22:18:55.98#ibcon#about to read 6, iclass 15, count 2 2006.257.22:18:55.98#ibcon#read 6, iclass 15, count 2 2006.257.22:18:55.98#ibcon#end of sib2, iclass 15, count 2 2006.257.22:18:55.98#ibcon#*after write, iclass 15, count 2 2006.257.22:18:55.98#ibcon#*before return 0, iclass 15, count 2 2006.257.22:18:55.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:55.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:18:55.98#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.22:18:55.98#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:55.98#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:56.10#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:56.10#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:56.10#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:18:56.10#ibcon#first serial, iclass 15, count 0 2006.257.22:18:56.10#ibcon#enter sib2, iclass 15, count 0 2006.257.22:18:56.10#ibcon#flushed, iclass 15, count 0 2006.257.22:18:56.10#ibcon#about to write, iclass 15, count 0 2006.257.22:18:56.10#ibcon#wrote, iclass 15, count 0 2006.257.22:18:56.10#ibcon#about to read 3, iclass 15, count 0 2006.257.22:18:56.12#ibcon#read 3, iclass 15, count 0 2006.257.22:18:56.12#ibcon#about to read 4, iclass 15, count 0 2006.257.22:18:56.12#ibcon#read 4, iclass 15, count 0 2006.257.22:18:56.12#ibcon#about to read 5, iclass 15, count 0 2006.257.22:18:56.12#ibcon#read 5, iclass 15, count 0 2006.257.22:18:56.12#ibcon#about to read 6, iclass 15, count 0 2006.257.22:18:56.12#ibcon#read 6, iclass 15, count 0 2006.257.22:18:56.12#ibcon#end of sib2, iclass 15, count 0 2006.257.22:18:56.12#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:18:56.12#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:18:56.12#ibcon#[27=USB\r\n] 2006.257.22:18:56.12#ibcon#*before write, iclass 15, count 0 2006.257.22:18:56.12#ibcon#enter sib2, iclass 15, count 0 2006.257.22:18:56.12#ibcon#flushed, iclass 15, count 0 2006.257.22:18:56.12#ibcon#about to write, iclass 15, count 0 2006.257.22:18:56.12#ibcon#wrote, iclass 15, count 0 2006.257.22:18:56.12#ibcon#about to read 3, iclass 15, count 0 2006.257.22:18:56.15#ibcon#read 3, iclass 15, count 0 2006.257.22:18:56.15#ibcon#about to read 4, iclass 15, count 0 2006.257.22:18:56.15#ibcon#read 4, iclass 15, count 0 2006.257.22:18:56.15#ibcon#about to read 5, iclass 15, count 0 2006.257.22:18:56.15#ibcon#read 5, iclass 15, count 0 2006.257.22:18:56.15#ibcon#about to read 6, iclass 15, count 0 2006.257.22:18:56.15#ibcon#read 6, iclass 15, count 0 2006.257.22:18:56.15#ibcon#end of sib2, iclass 15, count 0 2006.257.22:18:56.15#ibcon#*after write, iclass 15, count 0 2006.257.22:18:56.15#ibcon#*before return 0, iclass 15, count 0 2006.257.22:18:56.15#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:56.15#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:18:56.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:18:56.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:18:56.15$vck44/vblo=4,679.99 2006.257.22:18:56.15#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.22:18:56.15#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.22:18:56.15#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:56.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:18:56.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:18:56.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:18:56.15#ibcon#enter wrdev, iclass 17, count 0 2006.257.22:18:56.15#ibcon#first serial, iclass 17, count 0 2006.257.22:18:56.15#ibcon#enter sib2, iclass 17, count 0 2006.257.22:18:56.15#ibcon#flushed, iclass 17, count 0 2006.257.22:18:56.15#ibcon#about to write, iclass 17, count 0 2006.257.22:18:56.15#ibcon#wrote, iclass 17, count 0 2006.257.22:18:56.15#ibcon#about to read 3, iclass 17, count 0 2006.257.22:18:56.17#ibcon#read 3, iclass 17, count 0 2006.257.22:18:56.17#ibcon#about to read 4, iclass 17, count 0 2006.257.22:18:56.17#ibcon#read 4, iclass 17, count 0 2006.257.22:18:56.17#ibcon#about to read 5, iclass 17, count 0 2006.257.22:18:56.17#ibcon#read 5, iclass 17, count 0 2006.257.22:18:56.17#ibcon#about to read 6, iclass 17, count 0 2006.257.22:18:56.17#ibcon#read 6, iclass 17, count 0 2006.257.22:18:56.17#ibcon#end of sib2, iclass 17, count 0 2006.257.22:18:56.17#ibcon#*mode == 0, iclass 17, count 0 2006.257.22:18:56.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.22:18:56.17#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.22:18:56.17#ibcon#*before write, iclass 17, count 0 2006.257.22:18:56.17#ibcon#enter sib2, iclass 17, count 0 2006.257.22:18:56.17#ibcon#flushed, iclass 17, count 0 2006.257.22:18:56.17#ibcon#about to write, iclass 17, count 0 2006.257.22:18:56.17#ibcon#wrote, iclass 17, count 0 2006.257.22:18:56.17#ibcon#about to read 3, iclass 17, count 0 2006.257.22:18:56.21#ibcon#read 3, iclass 17, count 0 2006.257.22:18:56.21#ibcon#about to read 4, iclass 17, count 0 2006.257.22:18:56.21#ibcon#read 4, iclass 17, count 0 2006.257.22:18:56.21#ibcon#about to read 5, iclass 17, count 0 2006.257.22:18:56.21#ibcon#read 5, iclass 17, count 0 2006.257.22:18:56.21#ibcon#about to read 6, iclass 17, count 0 2006.257.22:18:56.21#ibcon#read 6, iclass 17, count 0 2006.257.22:18:56.21#ibcon#end of sib2, iclass 17, count 0 2006.257.22:18:56.21#ibcon#*after write, iclass 17, count 0 2006.257.22:18:56.21#ibcon#*before return 0, iclass 17, count 0 2006.257.22:18:56.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:18:56.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:18:56.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.22:18:56.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.22:18:56.21$vck44/vb=4,5 2006.257.22:18:56.21#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.22:18:56.21#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.22:18:56.21#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:56.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:18:56.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:18:56.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:18:56.27#ibcon#enter wrdev, iclass 19, count 2 2006.257.22:18:56.27#ibcon#first serial, iclass 19, count 2 2006.257.22:18:56.27#ibcon#enter sib2, iclass 19, count 2 2006.257.22:18:56.27#ibcon#flushed, iclass 19, count 2 2006.257.22:18:56.27#ibcon#about to write, iclass 19, count 2 2006.257.22:18:56.27#ibcon#wrote, iclass 19, count 2 2006.257.22:18:56.27#ibcon#about to read 3, iclass 19, count 2 2006.257.22:18:56.29#ibcon#read 3, iclass 19, count 2 2006.257.22:18:56.29#ibcon#about to read 4, iclass 19, count 2 2006.257.22:18:56.29#ibcon#read 4, iclass 19, count 2 2006.257.22:18:56.29#ibcon#about to read 5, iclass 19, count 2 2006.257.22:18:56.29#ibcon#read 5, iclass 19, count 2 2006.257.22:18:56.29#ibcon#about to read 6, iclass 19, count 2 2006.257.22:18:56.29#ibcon#read 6, iclass 19, count 2 2006.257.22:18:56.29#ibcon#end of sib2, iclass 19, count 2 2006.257.22:18:56.29#ibcon#*mode == 0, iclass 19, count 2 2006.257.22:18:56.29#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.22:18:56.29#ibcon#[27=AT04-05\r\n] 2006.257.22:18:56.29#ibcon#*before write, iclass 19, count 2 2006.257.22:18:56.29#ibcon#enter sib2, iclass 19, count 2 2006.257.22:18:56.29#ibcon#flushed, iclass 19, count 2 2006.257.22:18:56.29#ibcon#about to write, iclass 19, count 2 2006.257.22:18:56.29#ibcon#wrote, iclass 19, count 2 2006.257.22:18:56.29#ibcon#about to read 3, iclass 19, count 2 2006.257.22:18:56.32#ibcon#read 3, iclass 19, count 2 2006.257.22:18:56.32#ibcon#about to read 4, iclass 19, count 2 2006.257.22:18:56.32#ibcon#read 4, iclass 19, count 2 2006.257.22:18:56.32#ibcon#about to read 5, iclass 19, count 2 2006.257.22:18:56.32#ibcon#read 5, iclass 19, count 2 2006.257.22:18:56.32#ibcon#about to read 6, iclass 19, count 2 2006.257.22:18:56.32#ibcon#read 6, iclass 19, count 2 2006.257.22:18:56.32#ibcon#end of sib2, iclass 19, count 2 2006.257.22:18:56.32#ibcon#*after write, iclass 19, count 2 2006.257.22:18:56.32#ibcon#*before return 0, iclass 19, count 2 2006.257.22:18:56.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:18:56.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:18:56.32#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.22:18:56.32#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:56.32#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:18:56.44#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:18:56.44#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:18:56.44#ibcon#enter wrdev, iclass 19, count 0 2006.257.22:18:56.44#ibcon#first serial, iclass 19, count 0 2006.257.22:18:56.44#ibcon#enter sib2, iclass 19, count 0 2006.257.22:18:56.44#ibcon#flushed, iclass 19, count 0 2006.257.22:18:56.44#ibcon#about to write, iclass 19, count 0 2006.257.22:18:56.44#ibcon#wrote, iclass 19, count 0 2006.257.22:18:56.44#ibcon#about to read 3, iclass 19, count 0 2006.257.22:18:56.46#ibcon#read 3, iclass 19, count 0 2006.257.22:18:56.46#ibcon#about to read 4, iclass 19, count 0 2006.257.22:18:56.46#ibcon#read 4, iclass 19, count 0 2006.257.22:18:56.46#ibcon#about to read 5, iclass 19, count 0 2006.257.22:18:56.46#ibcon#read 5, iclass 19, count 0 2006.257.22:18:56.46#ibcon#about to read 6, iclass 19, count 0 2006.257.22:18:56.46#ibcon#read 6, iclass 19, count 0 2006.257.22:18:56.46#ibcon#end of sib2, iclass 19, count 0 2006.257.22:18:56.46#ibcon#*mode == 0, iclass 19, count 0 2006.257.22:18:56.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.22:18:56.46#ibcon#[27=USB\r\n] 2006.257.22:18:56.46#ibcon#*before write, iclass 19, count 0 2006.257.22:18:56.46#ibcon#enter sib2, iclass 19, count 0 2006.257.22:18:56.46#ibcon#flushed, iclass 19, count 0 2006.257.22:18:56.46#ibcon#about to write, iclass 19, count 0 2006.257.22:18:56.46#ibcon#wrote, iclass 19, count 0 2006.257.22:18:56.46#ibcon#about to read 3, iclass 19, count 0 2006.257.22:18:56.49#ibcon#read 3, iclass 19, count 0 2006.257.22:18:56.49#ibcon#about to read 4, iclass 19, count 0 2006.257.22:18:56.49#ibcon#read 4, iclass 19, count 0 2006.257.22:18:56.49#ibcon#about to read 5, iclass 19, count 0 2006.257.22:18:56.49#ibcon#read 5, iclass 19, count 0 2006.257.22:18:56.49#ibcon#about to read 6, iclass 19, count 0 2006.257.22:18:56.49#ibcon#read 6, iclass 19, count 0 2006.257.22:18:56.49#ibcon#end of sib2, iclass 19, count 0 2006.257.22:18:56.49#ibcon#*after write, iclass 19, count 0 2006.257.22:18:56.49#ibcon#*before return 0, iclass 19, count 0 2006.257.22:18:56.49#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:18:56.49#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:18:56.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.22:18:56.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.22:18:56.49$vck44/vblo=5,709.99 2006.257.22:18:56.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.22:18:56.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.22:18:56.49#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:56.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:56.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:56.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:56.49#ibcon#enter wrdev, iclass 21, count 0 2006.257.22:18:56.49#ibcon#first serial, iclass 21, count 0 2006.257.22:18:56.49#ibcon#enter sib2, iclass 21, count 0 2006.257.22:18:56.49#ibcon#flushed, iclass 21, count 0 2006.257.22:18:56.49#ibcon#about to write, iclass 21, count 0 2006.257.22:18:56.49#ibcon#wrote, iclass 21, count 0 2006.257.22:18:56.49#ibcon#about to read 3, iclass 21, count 0 2006.257.22:18:56.51#ibcon#read 3, iclass 21, count 0 2006.257.22:18:56.51#ibcon#about to read 4, iclass 21, count 0 2006.257.22:18:56.51#ibcon#read 4, iclass 21, count 0 2006.257.22:18:56.51#ibcon#about to read 5, iclass 21, count 0 2006.257.22:18:56.51#ibcon#read 5, iclass 21, count 0 2006.257.22:18:56.51#ibcon#about to read 6, iclass 21, count 0 2006.257.22:18:56.51#ibcon#read 6, iclass 21, count 0 2006.257.22:18:56.51#ibcon#end of sib2, iclass 21, count 0 2006.257.22:18:56.51#ibcon#*mode == 0, iclass 21, count 0 2006.257.22:18:56.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.22:18:56.51#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.22:18:56.51#ibcon#*before write, iclass 21, count 0 2006.257.22:18:56.51#ibcon#enter sib2, iclass 21, count 0 2006.257.22:18:56.51#ibcon#flushed, iclass 21, count 0 2006.257.22:18:56.51#ibcon#about to write, iclass 21, count 0 2006.257.22:18:56.51#ibcon#wrote, iclass 21, count 0 2006.257.22:18:56.51#ibcon#about to read 3, iclass 21, count 0 2006.257.22:18:56.55#ibcon#read 3, iclass 21, count 0 2006.257.22:18:56.55#ibcon#about to read 4, iclass 21, count 0 2006.257.22:18:56.55#ibcon#read 4, iclass 21, count 0 2006.257.22:18:56.55#ibcon#about to read 5, iclass 21, count 0 2006.257.22:18:56.55#ibcon#read 5, iclass 21, count 0 2006.257.22:18:56.55#ibcon#about to read 6, iclass 21, count 0 2006.257.22:18:56.55#ibcon#read 6, iclass 21, count 0 2006.257.22:18:56.55#ibcon#end of sib2, iclass 21, count 0 2006.257.22:18:56.55#ibcon#*after write, iclass 21, count 0 2006.257.22:18:56.55#ibcon#*before return 0, iclass 21, count 0 2006.257.22:18:56.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:56.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:18:56.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.22:18:56.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.22:18:56.55$vck44/vb=5,4 2006.257.22:18:56.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.22:18:56.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.22:18:56.55#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:56.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:56.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:56.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:56.61#ibcon#enter wrdev, iclass 23, count 2 2006.257.22:18:56.61#ibcon#first serial, iclass 23, count 2 2006.257.22:18:56.61#ibcon#enter sib2, iclass 23, count 2 2006.257.22:18:56.61#ibcon#flushed, iclass 23, count 2 2006.257.22:18:56.61#ibcon#about to write, iclass 23, count 2 2006.257.22:18:56.61#ibcon#wrote, iclass 23, count 2 2006.257.22:18:56.61#ibcon#about to read 3, iclass 23, count 2 2006.257.22:18:56.63#ibcon#read 3, iclass 23, count 2 2006.257.22:18:56.63#ibcon#about to read 4, iclass 23, count 2 2006.257.22:18:56.63#ibcon#read 4, iclass 23, count 2 2006.257.22:18:56.63#ibcon#about to read 5, iclass 23, count 2 2006.257.22:18:56.63#ibcon#read 5, iclass 23, count 2 2006.257.22:18:56.63#ibcon#about to read 6, iclass 23, count 2 2006.257.22:18:56.63#ibcon#read 6, iclass 23, count 2 2006.257.22:18:56.63#ibcon#end of sib2, iclass 23, count 2 2006.257.22:18:56.63#ibcon#*mode == 0, iclass 23, count 2 2006.257.22:18:56.63#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.22:18:56.63#ibcon#[27=AT05-04\r\n] 2006.257.22:18:56.63#ibcon#*before write, iclass 23, count 2 2006.257.22:18:56.63#ibcon#enter sib2, iclass 23, count 2 2006.257.22:18:56.63#ibcon#flushed, iclass 23, count 2 2006.257.22:18:56.63#ibcon#about to write, iclass 23, count 2 2006.257.22:18:56.63#ibcon#wrote, iclass 23, count 2 2006.257.22:18:56.63#ibcon#about to read 3, iclass 23, count 2 2006.257.22:18:56.66#ibcon#read 3, iclass 23, count 2 2006.257.22:18:56.66#ibcon#about to read 4, iclass 23, count 2 2006.257.22:18:56.66#ibcon#read 4, iclass 23, count 2 2006.257.22:18:56.66#ibcon#about to read 5, iclass 23, count 2 2006.257.22:18:56.66#ibcon#read 5, iclass 23, count 2 2006.257.22:18:56.66#ibcon#about to read 6, iclass 23, count 2 2006.257.22:18:56.66#ibcon#read 6, iclass 23, count 2 2006.257.22:18:56.66#ibcon#end of sib2, iclass 23, count 2 2006.257.22:18:56.66#ibcon#*after write, iclass 23, count 2 2006.257.22:18:56.66#ibcon#*before return 0, iclass 23, count 2 2006.257.22:18:56.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:56.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:18:56.66#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.22:18:56.66#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:56.66#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:56.78#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:56.78#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:56.78#ibcon#enter wrdev, iclass 23, count 0 2006.257.22:18:56.78#ibcon#first serial, iclass 23, count 0 2006.257.22:18:56.78#ibcon#enter sib2, iclass 23, count 0 2006.257.22:18:56.78#ibcon#flushed, iclass 23, count 0 2006.257.22:18:56.78#ibcon#about to write, iclass 23, count 0 2006.257.22:18:56.78#ibcon#wrote, iclass 23, count 0 2006.257.22:18:56.78#ibcon#about to read 3, iclass 23, count 0 2006.257.22:18:56.80#ibcon#read 3, iclass 23, count 0 2006.257.22:18:56.80#ibcon#about to read 4, iclass 23, count 0 2006.257.22:18:56.80#ibcon#read 4, iclass 23, count 0 2006.257.22:18:56.80#ibcon#about to read 5, iclass 23, count 0 2006.257.22:18:56.80#ibcon#read 5, iclass 23, count 0 2006.257.22:18:56.80#ibcon#about to read 6, iclass 23, count 0 2006.257.22:18:56.80#ibcon#read 6, iclass 23, count 0 2006.257.22:18:56.80#ibcon#end of sib2, iclass 23, count 0 2006.257.22:18:56.80#ibcon#*mode == 0, iclass 23, count 0 2006.257.22:18:56.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.22:18:56.80#ibcon#[27=USB\r\n] 2006.257.22:18:56.80#ibcon#*before write, iclass 23, count 0 2006.257.22:18:56.80#ibcon#enter sib2, iclass 23, count 0 2006.257.22:18:56.80#ibcon#flushed, iclass 23, count 0 2006.257.22:18:56.80#ibcon#about to write, iclass 23, count 0 2006.257.22:18:56.80#ibcon#wrote, iclass 23, count 0 2006.257.22:18:56.80#ibcon#about to read 3, iclass 23, count 0 2006.257.22:18:56.83#ibcon#read 3, iclass 23, count 0 2006.257.22:18:56.83#ibcon#about to read 4, iclass 23, count 0 2006.257.22:18:56.83#ibcon#read 4, iclass 23, count 0 2006.257.22:18:56.83#ibcon#about to read 5, iclass 23, count 0 2006.257.22:18:56.83#ibcon#read 5, iclass 23, count 0 2006.257.22:18:56.83#ibcon#about to read 6, iclass 23, count 0 2006.257.22:18:56.83#ibcon#read 6, iclass 23, count 0 2006.257.22:18:56.83#ibcon#end of sib2, iclass 23, count 0 2006.257.22:18:56.83#ibcon#*after write, iclass 23, count 0 2006.257.22:18:56.83#ibcon#*before return 0, iclass 23, count 0 2006.257.22:18:56.83#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:56.83#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:18:56.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.22:18:56.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.22:18:56.83$vck44/vblo=6,719.99 2006.257.22:18:56.83#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.22:18:56.83#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.22:18:56.83#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:56.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:56.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:56.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:56.83#ibcon#enter wrdev, iclass 25, count 0 2006.257.22:18:56.83#ibcon#first serial, iclass 25, count 0 2006.257.22:18:56.83#ibcon#enter sib2, iclass 25, count 0 2006.257.22:18:56.83#ibcon#flushed, iclass 25, count 0 2006.257.22:18:56.83#ibcon#about to write, iclass 25, count 0 2006.257.22:18:56.83#ibcon#wrote, iclass 25, count 0 2006.257.22:18:56.83#ibcon#about to read 3, iclass 25, count 0 2006.257.22:18:56.85#ibcon#read 3, iclass 25, count 0 2006.257.22:18:56.85#ibcon#about to read 4, iclass 25, count 0 2006.257.22:18:56.85#ibcon#read 4, iclass 25, count 0 2006.257.22:18:56.85#ibcon#about to read 5, iclass 25, count 0 2006.257.22:18:56.85#ibcon#read 5, iclass 25, count 0 2006.257.22:18:56.85#ibcon#about to read 6, iclass 25, count 0 2006.257.22:18:56.85#ibcon#read 6, iclass 25, count 0 2006.257.22:18:56.85#ibcon#end of sib2, iclass 25, count 0 2006.257.22:18:56.85#ibcon#*mode == 0, iclass 25, count 0 2006.257.22:18:56.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.22:18:56.85#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.22:18:56.85#ibcon#*before write, iclass 25, count 0 2006.257.22:18:56.85#ibcon#enter sib2, iclass 25, count 0 2006.257.22:18:56.85#ibcon#flushed, iclass 25, count 0 2006.257.22:18:56.85#ibcon#about to write, iclass 25, count 0 2006.257.22:18:56.85#ibcon#wrote, iclass 25, count 0 2006.257.22:18:56.85#ibcon#about to read 3, iclass 25, count 0 2006.257.22:18:56.89#ibcon#read 3, iclass 25, count 0 2006.257.22:18:56.89#ibcon#about to read 4, iclass 25, count 0 2006.257.22:18:56.89#ibcon#read 4, iclass 25, count 0 2006.257.22:18:56.89#ibcon#about to read 5, iclass 25, count 0 2006.257.22:18:56.89#ibcon#read 5, iclass 25, count 0 2006.257.22:18:56.89#ibcon#about to read 6, iclass 25, count 0 2006.257.22:18:56.89#ibcon#read 6, iclass 25, count 0 2006.257.22:18:56.89#ibcon#end of sib2, iclass 25, count 0 2006.257.22:18:56.89#ibcon#*after write, iclass 25, count 0 2006.257.22:18:56.89#ibcon#*before return 0, iclass 25, count 0 2006.257.22:18:56.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:56.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:18:56.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.22:18:56.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.22:18:56.89$vck44/vb=6,4 2006.257.22:18:56.89#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.22:18:56.89#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.22:18:56.89#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:56.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:56.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:56.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:56.95#ibcon#enter wrdev, iclass 27, count 2 2006.257.22:18:56.95#ibcon#first serial, iclass 27, count 2 2006.257.22:18:56.95#ibcon#enter sib2, iclass 27, count 2 2006.257.22:18:56.95#ibcon#flushed, iclass 27, count 2 2006.257.22:18:56.95#ibcon#about to write, iclass 27, count 2 2006.257.22:18:56.95#ibcon#wrote, iclass 27, count 2 2006.257.22:18:56.95#ibcon#about to read 3, iclass 27, count 2 2006.257.22:18:56.97#ibcon#read 3, iclass 27, count 2 2006.257.22:18:56.97#ibcon#about to read 4, iclass 27, count 2 2006.257.22:18:56.97#ibcon#read 4, iclass 27, count 2 2006.257.22:18:56.97#ibcon#about to read 5, iclass 27, count 2 2006.257.22:18:56.97#ibcon#read 5, iclass 27, count 2 2006.257.22:18:56.97#ibcon#about to read 6, iclass 27, count 2 2006.257.22:18:56.97#ibcon#read 6, iclass 27, count 2 2006.257.22:18:56.97#ibcon#end of sib2, iclass 27, count 2 2006.257.22:18:56.97#ibcon#*mode == 0, iclass 27, count 2 2006.257.22:18:56.97#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.22:18:56.97#ibcon#[27=AT06-04\r\n] 2006.257.22:18:56.97#ibcon#*before write, iclass 27, count 2 2006.257.22:18:56.97#ibcon#enter sib2, iclass 27, count 2 2006.257.22:18:56.97#ibcon#flushed, iclass 27, count 2 2006.257.22:18:56.97#ibcon#about to write, iclass 27, count 2 2006.257.22:18:56.97#ibcon#wrote, iclass 27, count 2 2006.257.22:18:56.97#ibcon#about to read 3, iclass 27, count 2 2006.257.22:18:57.00#ibcon#read 3, iclass 27, count 2 2006.257.22:18:57.00#ibcon#about to read 4, iclass 27, count 2 2006.257.22:18:57.00#ibcon#read 4, iclass 27, count 2 2006.257.22:18:57.00#ibcon#about to read 5, iclass 27, count 2 2006.257.22:18:57.00#ibcon#read 5, iclass 27, count 2 2006.257.22:18:57.00#ibcon#about to read 6, iclass 27, count 2 2006.257.22:18:57.00#ibcon#read 6, iclass 27, count 2 2006.257.22:18:57.00#ibcon#end of sib2, iclass 27, count 2 2006.257.22:18:57.00#ibcon#*after write, iclass 27, count 2 2006.257.22:18:57.00#ibcon#*before return 0, iclass 27, count 2 2006.257.22:18:57.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:57.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:18:57.00#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.22:18:57.00#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:57.00#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:57.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:57.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:57.12#ibcon#enter wrdev, iclass 27, count 0 2006.257.22:18:57.12#ibcon#first serial, iclass 27, count 0 2006.257.22:18:57.12#ibcon#enter sib2, iclass 27, count 0 2006.257.22:18:57.12#ibcon#flushed, iclass 27, count 0 2006.257.22:18:57.12#ibcon#about to write, iclass 27, count 0 2006.257.22:18:57.12#ibcon#wrote, iclass 27, count 0 2006.257.22:18:57.12#ibcon#about to read 3, iclass 27, count 0 2006.257.22:18:57.14#ibcon#read 3, iclass 27, count 0 2006.257.22:18:57.14#ibcon#about to read 4, iclass 27, count 0 2006.257.22:18:57.14#ibcon#read 4, iclass 27, count 0 2006.257.22:18:57.14#ibcon#about to read 5, iclass 27, count 0 2006.257.22:18:57.14#ibcon#read 5, iclass 27, count 0 2006.257.22:18:57.14#ibcon#about to read 6, iclass 27, count 0 2006.257.22:18:57.14#ibcon#read 6, iclass 27, count 0 2006.257.22:18:57.14#ibcon#end of sib2, iclass 27, count 0 2006.257.22:18:57.14#ibcon#*mode == 0, iclass 27, count 0 2006.257.22:18:57.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.22:18:57.14#ibcon#[27=USB\r\n] 2006.257.22:18:57.14#ibcon#*before write, iclass 27, count 0 2006.257.22:18:57.14#ibcon#enter sib2, iclass 27, count 0 2006.257.22:18:57.14#ibcon#flushed, iclass 27, count 0 2006.257.22:18:57.14#ibcon#about to write, iclass 27, count 0 2006.257.22:18:57.14#ibcon#wrote, iclass 27, count 0 2006.257.22:18:57.14#ibcon#about to read 3, iclass 27, count 0 2006.257.22:18:57.17#ibcon#read 3, iclass 27, count 0 2006.257.22:18:57.17#ibcon#about to read 4, iclass 27, count 0 2006.257.22:18:57.17#ibcon#read 4, iclass 27, count 0 2006.257.22:18:57.17#ibcon#about to read 5, iclass 27, count 0 2006.257.22:18:57.17#ibcon#read 5, iclass 27, count 0 2006.257.22:18:57.17#ibcon#about to read 6, iclass 27, count 0 2006.257.22:18:57.17#ibcon#read 6, iclass 27, count 0 2006.257.22:18:57.17#ibcon#end of sib2, iclass 27, count 0 2006.257.22:18:57.17#ibcon#*after write, iclass 27, count 0 2006.257.22:18:57.17#ibcon#*before return 0, iclass 27, count 0 2006.257.22:18:57.17#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:57.17#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:18:57.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.22:18:57.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.22:18:57.17$vck44/vblo=7,734.99 2006.257.22:18:57.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.22:18:57.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.22:18:57.17#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:57.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:57.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:57.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:57.17#ibcon#enter wrdev, iclass 29, count 0 2006.257.22:18:57.17#ibcon#first serial, iclass 29, count 0 2006.257.22:18:57.17#ibcon#enter sib2, iclass 29, count 0 2006.257.22:18:57.17#ibcon#flushed, iclass 29, count 0 2006.257.22:18:57.17#ibcon#about to write, iclass 29, count 0 2006.257.22:18:57.17#ibcon#wrote, iclass 29, count 0 2006.257.22:18:57.17#ibcon#about to read 3, iclass 29, count 0 2006.257.22:18:57.19#ibcon#read 3, iclass 29, count 0 2006.257.22:18:57.19#ibcon#about to read 4, iclass 29, count 0 2006.257.22:18:57.19#ibcon#read 4, iclass 29, count 0 2006.257.22:18:57.19#ibcon#about to read 5, iclass 29, count 0 2006.257.22:18:57.19#ibcon#read 5, iclass 29, count 0 2006.257.22:18:57.19#ibcon#about to read 6, iclass 29, count 0 2006.257.22:18:57.19#ibcon#read 6, iclass 29, count 0 2006.257.22:18:57.19#ibcon#end of sib2, iclass 29, count 0 2006.257.22:18:57.19#ibcon#*mode == 0, iclass 29, count 0 2006.257.22:18:57.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.22:18:57.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.22:18:57.19#ibcon#*before write, iclass 29, count 0 2006.257.22:18:57.19#ibcon#enter sib2, iclass 29, count 0 2006.257.22:18:57.19#ibcon#flushed, iclass 29, count 0 2006.257.22:18:57.19#ibcon#about to write, iclass 29, count 0 2006.257.22:18:57.19#ibcon#wrote, iclass 29, count 0 2006.257.22:18:57.19#ibcon#about to read 3, iclass 29, count 0 2006.257.22:18:57.23#ibcon#read 3, iclass 29, count 0 2006.257.22:18:57.23#ibcon#about to read 4, iclass 29, count 0 2006.257.22:18:57.23#ibcon#read 4, iclass 29, count 0 2006.257.22:18:57.23#ibcon#about to read 5, iclass 29, count 0 2006.257.22:18:57.23#ibcon#read 5, iclass 29, count 0 2006.257.22:18:57.23#ibcon#about to read 6, iclass 29, count 0 2006.257.22:18:57.23#ibcon#read 6, iclass 29, count 0 2006.257.22:18:57.23#ibcon#end of sib2, iclass 29, count 0 2006.257.22:18:57.23#ibcon#*after write, iclass 29, count 0 2006.257.22:18:57.23#ibcon#*before return 0, iclass 29, count 0 2006.257.22:18:57.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:57.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:18:57.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.22:18:57.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.22:18:57.23$vck44/vb=7,4 2006.257.22:18:57.23#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.22:18:57.23#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.22:18:57.23#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:57.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:57.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:57.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:57.29#ibcon#enter wrdev, iclass 31, count 2 2006.257.22:18:57.29#ibcon#first serial, iclass 31, count 2 2006.257.22:18:57.29#ibcon#enter sib2, iclass 31, count 2 2006.257.22:18:57.29#ibcon#flushed, iclass 31, count 2 2006.257.22:18:57.29#ibcon#about to write, iclass 31, count 2 2006.257.22:18:57.29#ibcon#wrote, iclass 31, count 2 2006.257.22:18:57.29#ibcon#about to read 3, iclass 31, count 2 2006.257.22:18:57.31#ibcon#read 3, iclass 31, count 2 2006.257.22:18:57.31#ibcon#about to read 4, iclass 31, count 2 2006.257.22:18:57.31#ibcon#read 4, iclass 31, count 2 2006.257.22:18:57.31#ibcon#about to read 5, iclass 31, count 2 2006.257.22:18:57.31#ibcon#read 5, iclass 31, count 2 2006.257.22:18:57.31#ibcon#about to read 6, iclass 31, count 2 2006.257.22:18:57.31#ibcon#read 6, iclass 31, count 2 2006.257.22:18:57.31#ibcon#end of sib2, iclass 31, count 2 2006.257.22:18:57.31#ibcon#*mode == 0, iclass 31, count 2 2006.257.22:18:57.31#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.22:18:57.31#ibcon#[27=AT07-04\r\n] 2006.257.22:18:57.31#ibcon#*before write, iclass 31, count 2 2006.257.22:18:57.31#ibcon#enter sib2, iclass 31, count 2 2006.257.22:18:57.31#ibcon#flushed, iclass 31, count 2 2006.257.22:18:57.31#ibcon#about to write, iclass 31, count 2 2006.257.22:18:57.31#ibcon#wrote, iclass 31, count 2 2006.257.22:18:57.31#ibcon#about to read 3, iclass 31, count 2 2006.257.22:18:57.34#ibcon#read 3, iclass 31, count 2 2006.257.22:18:57.34#ibcon#about to read 4, iclass 31, count 2 2006.257.22:18:57.34#ibcon#read 4, iclass 31, count 2 2006.257.22:18:57.34#ibcon#about to read 5, iclass 31, count 2 2006.257.22:18:57.34#ibcon#read 5, iclass 31, count 2 2006.257.22:18:57.34#ibcon#about to read 6, iclass 31, count 2 2006.257.22:18:57.34#ibcon#read 6, iclass 31, count 2 2006.257.22:18:57.34#ibcon#end of sib2, iclass 31, count 2 2006.257.22:18:57.34#ibcon#*after write, iclass 31, count 2 2006.257.22:18:57.34#ibcon#*before return 0, iclass 31, count 2 2006.257.22:18:57.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:57.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:18:57.34#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.22:18:57.34#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:57.34#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:57.46#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:57.46#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:57.46#ibcon#enter wrdev, iclass 31, count 0 2006.257.22:18:57.46#ibcon#first serial, iclass 31, count 0 2006.257.22:18:57.46#ibcon#enter sib2, iclass 31, count 0 2006.257.22:18:57.46#ibcon#flushed, iclass 31, count 0 2006.257.22:18:57.46#ibcon#about to write, iclass 31, count 0 2006.257.22:18:57.46#ibcon#wrote, iclass 31, count 0 2006.257.22:18:57.46#ibcon#about to read 3, iclass 31, count 0 2006.257.22:18:57.48#ibcon#read 3, iclass 31, count 0 2006.257.22:18:57.48#ibcon#about to read 4, iclass 31, count 0 2006.257.22:18:57.48#ibcon#read 4, iclass 31, count 0 2006.257.22:18:57.48#ibcon#about to read 5, iclass 31, count 0 2006.257.22:18:57.48#ibcon#read 5, iclass 31, count 0 2006.257.22:18:57.48#ibcon#about to read 6, iclass 31, count 0 2006.257.22:18:57.48#ibcon#read 6, iclass 31, count 0 2006.257.22:18:57.48#ibcon#end of sib2, iclass 31, count 0 2006.257.22:18:57.48#ibcon#*mode == 0, iclass 31, count 0 2006.257.22:18:57.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.22:18:57.48#ibcon#[27=USB\r\n] 2006.257.22:18:57.48#ibcon#*before write, iclass 31, count 0 2006.257.22:18:57.48#ibcon#enter sib2, iclass 31, count 0 2006.257.22:18:57.48#ibcon#flushed, iclass 31, count 0 2006.257.22:18:57.48#ibcon#about to write, iclass 31, count 0 2006.257.22:18:57.48#ibcon#wrote, iclass 31, count 0 2006.257.22:18:57.48#ibcon#about to read 3, iclass 31, count 0 2006.257.22:18:57.51#ibcon#read 3, iclass 31, count 0 2006.257.22:18:57.51#ibcon#about to read 4, iclass 31, count 0 2006.257.22:18:57.51#ibcon#read 4, iclass 31, count 0 2006.257.22:18:57.51#ibcon#about to read 5, iclass 31, count 0 2006.257.22:18:57.51#ibcon#read 5, iclass 31, count 0 2006.257.22:18:57.51#ibcon#about to read 6, iclass 31, count 0 2006.257.22:18:57.51#ibcon#read 6, iclass 31, count 0 2006.257.22:18:57.51#ibcon#end of sib2, iclass 31, count 0 2006.257.22:18:57.51#ibcon#*after write, iclass 31, count 0 2006.257.22:18:57.51#ibcon#*before return 0, iclass 31, count 0 2006.257.22:18:57.51#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:57.51#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:18:57.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.22:18:57.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.22:18:57.51$vck44/vblo=8,744.99 2006.257.22:18:57.51#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.22:18:57.51#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.22:18:57.51#ibcon#ireg 17 cls_cnt 0 2006.257.22:18:57.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:57.51#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:57.51#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:57.51#ibcon#enter wrdev, iclass 33, count 0 2006.257.22:18:57.51#ibcon#first serial, iclass 33, count 0 2006.257.22:18:57.51#ibcon#enter sib2, iclass 33, count 0 2006.257.22:18:57.51#ibcon#flushed, iclass 33, count 0 2006.257.22:18:57.51#ibcon#about to write, iclass 33, count 0 2006.257.22:18:57.51#ibcon#wrote, iclass 33, count 0 2006.257.22:18:57.51#ibcon#about to read 3, iclass 33, count 0 2006.257.22:18:57.53#ibcon#read 3, iclass 33, count 0 2006.257.22:18:57.53#ibcon#about to read 4, iclass 33, count 0 2006.257.22:18:57.53#ibcon#read 4, iclass 33, count 0 2006.257.22:18:57.53#ibcon#about to read 5, iclass 33, count 0 2006.257.22:18:57.53#ibcon#read 5, iclass 33, count 0 2006.257.22:18:57.53#ibcon#about to read 6, iclass 33, count 0 2006.257.22:18:57.53#ibcon#read 6, iclass 33, count 0 2006.257.22:18:57.53#ibcon#end of sib2, iclass 33, count 0 2006.257.22:18:57.53#ibcon#*mode == 0, iclass 33, count 0 2006.257.22:18:57.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.22:18:57.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.22:18:57.53#ibcon#*before write, iclass 33, count 0 2006.257.22:18:57.53#ibcon#enter sib2, iclass 33, count 0 2006.257.22:18:57.53#ibcon#flushed, iclass 33, count 0 2006.257.22:18:57.53#ibcon#about to write, iclass 33, count 0 2006.257.22:18:57.53#ibcon#wrote, iclass 33, count 0 2006.257.22:18:57.53#ibcon#about to read 3, iclass 33, count 0 2006.257.22:18:57.57#ibcon#read 3, iclass 33, count 0 2006.257.22:18:57.57#ibcon#about to read 4, iclass 33, count 0 2006.257.22:18:57.57#ibcon#read 4, iclass 33, count 0 2006.257.22:18:57.57#ibcon#about to read 5, iclass 33, count 0 2006.257.22:18:57.57#ibcon#read 5, iclass 33, count 0 2006.257.22:18:57.57#ibcon#about to read 6, iclass 33, count 0 2006.257.22:18:57.57#ibcon#read 6, iclass 33, count 0 2006.257.22:18:57.57#ibcon#end of sib2, iclass 33, count 0 2006.257.22:18:57.57#ibcon#*after write, iclass 33, count 0 2006.257.22:18:57.57#ibcon#*before return 0, iclass 33, count 0 2006.257.22:18:57.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:57.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:18:57.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.22:18:57.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.22:18:57.57$vck44/vb=8,4 2006.257.22:18:57.57#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.22:18:57.57#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.22:18:57.57#ibcon#ireg 11 cls_cnt 2 2006.257.22:18:57.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:57.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:57.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:57.63#ibcon#enter wrdev, iclass 35, count 2 2006.257.22:18:57.63#ibcon#first serial, iclass 35, count 2 2006.257.22:18:57.63#ibcon#enter sib2, iclass 35, count 2 2006.257.22:18:57.63#ibcon#flushed, iclass 35, count 2 2006.257.22:18:57.63#ibcon#about to write, iclass 35, count 2 2006.257.22:18:57.63#ibcon#wrote, iclass 35, count 2 2006.257.22:18:57.63#ibcon#about to read 3, iclass 35, count 2 2006.257.22:18:57.65#ibcon#read 3, iclass 35, count 2 2006.257.22:18:57.65#ibcon#about to read 4, iclass 35, count 2 2006.257.22:18:57.65#ibcon#read 4, iclass 35, count 2 2006.257.22:18:57.65#ibcon#about to read 5, iclass 35, count 2 2006.257.22:18:57.65#ibcon#read 5, iclass 35, count 2 2006.257.22:18:57.65#ibcon#about to read 6, iclass 35, count 2 2006.257.22:18:57.65#ibcon#read 6, iclass 35, count 2 2006.257.22:18:57.65#ibcon#end of sib2, iclass 35, count 2 2006.257.22:18:57.65#ibcon#*mode == 0, iclass 35, count 2 2006.257.22:18:57.65#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.22:18:57.65#ibcon#[27=AT08-04\r\n] 2006.257.22:18:57.65#ibcon#*before write, iclass 35, count 2 2006.257.22:18:57.65#ibcon#enter sib2, iclass 35, count 2 2006.257.22:18:57.65#ibcon#flushed, iclass 35, count 2 2006.257.22:18:57.65#ibcon#about to write, iclass 35, count 2 2006.257.22:18:57.65#ibcon#wrote, iclass 35, count 2 2006.257.22:18:57.65#ibcon#about to read 3, iclass 35, count 2 2006.257.22:18:57.68#ibcon#read 3, iclass 35, count 2 2006.257.22:18:57.68#ibcon#about to read 4, iclass 35, count 2 2006.257.22:18:57.68#ibcon#read 4, iclass 35, count 2 2006.257.22:18:57.68#ibcon#about to read 5, iclass 35, count 2 2006.257.22:18:57.68#ibcon#read 5, iclass 35, count 2 2006.257.22:18:57.68#ibcon#about to read 6, iclass 35, count 2 2006.257.22:18:57.68#ibcon#read 6, iclass 35, count 2 2006.257.22:18:57.68#ibcon#end of sib2, iclass 35, count 2 2006.257.22:18:57.68#ibcon#*after write, iclass 35, count 2 2006.257.22:18:57.68#ibcon#*before return 0, iclass 35, count 2 2006.257.22:18:57.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:57.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:18:57.68#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.22:18:57.68#ibcon#ireg 7 cls_cnt 0 2006.257.22:18:57.68#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:57.80#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:57.80#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:57.80#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:18:57.80#ibcon#first serial, iclass 35, count 0 2006.257.22:18:57.80#ibcon#enter sib2, iclass 35, count 0 2006.257.22:18:57.80#ibcon#flushed, iclass 35, count 0 2006.257.22:18:57.80#ibcon#about to write, iclass 35, count 0 2006.257.22:18:57.80#ibcon#wrote, iclass 35, count 0 2006.257.22:18:57.80#ibcon#about to read 3, iclass 35, count 0 2006.257.22:18:57.82#ibcon#read 3, iclass 35, count 0 2006.257.22:18:57.82#ibcon#about to read 4, iclass 35, count 0 2006.257.22:18:57.82#ibcon#read 4, iclass 35, count 0 2006.257.22:18:57.82#ibcon#about to read 5, iclass 35, count 0 2006.257.22:18:57.82#ibcon#read 5, iclass 35, count 0 2006.257.22:18:57.82#ibcon#about to read 6, iclass 35, count 0 2006.257.22:18:57.82#ibcon#read 6, iclass 35, count 0 2006.257.22:18:57.82#ibcon#end of sib2, iclass 35, count 0 2006.257.22:18:57.82#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:18:57.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:18:57.82#ibcon#[27=USB\r\n] 2006.257.22:18:57.82#ibcon#*before write, iclass 35, count 0 2006.257.22:18:57.82#ibcon#enter sib2, iclass 35, count 0 2006.257.22:18:57.82#ibcon#flushed, iclass 35, count 0 2006.257.22:18:57.82#ibcon#about to write, iclass 35, count 0 2006.257.22:18:57.82#ibcon#wrote, iclass 35, count 0 2006.257.22:18:57.82#ibcon#about to read 3, iclass 35, count 0 2006.257.22:18:57.85#ibcon#read 3, iclass 35, count 0 2006.257.22:18:57.85#ibcon#about to read 4, iclass 35, count 0 2006.257.22:18:57.85#ibcon#read 4, iclass 35, count 0 2006.257.22:18:57.85#ibcon#about to read 5, iclass 35, count 0 2006.257.22:18:57.85#ibcon#read 5, iclass 35, count 0 2006.257.22:18:57.85#ibcon#about to read 6, iclass 35, count 0 2006.257.22:18:57.85#ibcon#read 6, iclass 35, count 0 2006.257.22:18:57.85#ibcon#end of sib2, iclass 35, count 0 2006.257.22:18:57.85#ibcon#*after write, iclass 35, count 0 2006.257.22:18:57.85#ibcon#*before return 0, iclass 35, count 0 2006.257.22:18:57.85#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:57.85#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:18:57.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:18:57.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:18:57.85$vck44/vabw=wide 2006.257.22:18:57.85#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.22:18:57.85#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.22:18:57.85#ibcon#ireg 8 cls_cnt 0 2006.257.22:18:57.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:57.85#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:57.85#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:57.85#ibcon#enter wrdev, iclass 37, count 0 2006.257.22:18:57.85#ibcon#first serial, iclass 37, count 0 2006.257.22:18:57.85#ibcon#enter sib2, iclass 37, count 0 2006.257.22:18:57.85#ibcon#flushed, iclass 37, count 0 2006.257.22:18:57.85#ibcon#about to write, iclass 37, count 0 2006.257.22:18:57.85#ibcon#wrote, iclass 37, count 0 2006.257.22:18:57.85#ibcon#about to read 3, iclass 37, count 0 2006.257.22:18:57.87#ibcon#read 3, iclass 37, count 0 2006.257.22:18:57.87#ibcon#about to read 4, iclass 37, count 0 2006.257.22:18:57.87#ibcon#read 4, iclass 37, count 0 2006.257.22:18:57.87#ibcon#about to read 5, iclass 37, count 0 2006.257.22:18:57.87#ibcon#read 5, iclass 37, count 0 2006.257.22:18:57.87#ibcon#about to read 6, iclass 37, count 0 2006.257.22:18:57.87#ibcon#read 6, iclass 37, count 0 2006.257.22:18:57.87#ibcon#end of sib2, iclass 37, count 0 2006.257.22:18:57.87#ibcon#*mode == 0, iclass 37, count 0 2006.257.22:18:57.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.22:18:57.87#ibcon#[25=BW32\r\n] 2006.257.22:18:57.87#ibcon#*before write, iclass 37, count 0 2006.257.22:18:57.87#ibcon#enter sib2, iclass 37, count 0 2006.257.22:18:57.87#ibcon#flushed, iclass 37, count 0 2006.257.22:18:57.87#ibcon#about to write, iclass 37, count 0 2006.257.22:18:57.87#ibcon#wrote, iclass 37, count 0 2006.257.22:18:57.87#ibcon#about to read 3, iclass 37, count 0 2006.257.22:18:57.90#ibcon#read 3, iclass 37, count 0 2006.257.22:18:57.90#ibcon#about to read 4, iclass 37, count 0 2006.257.22:18:57.90#ibcon#read 4, iclass 37, count 0 2006.257.22:18:57.90#ibcon#about to read 5, iclass 37, count 0 2006.257.22:18:57.90#ibcon#read 5, iclass 37, count 0 2006.257.22:18:57.90#ibcon#about to read 6, iclass 37, count 0 2006.257.22:18:57.90#ibcon#read 6, iclass 37, count 0 2006.257.22:18:57.90#ibcon#end of sib2, iclass 37, count 0 2006.257.22:18:57.90#ibcon#*after write, iclass 37, count 0 2006.257.22:18:57.90#ibcon#*before return 0, iclass 37, count 0 2006.257.22:18:57.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:57.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:18:57.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.22:18:57.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.22:18:57.90$vck44/vbbw=wide 2006.257.22:18:57.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.22:18:57.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.22:18:57.90#ibcon#ireg 8 cls_cnt 0 2006.257.22:18:57.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:18:57.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:18:57.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:18:57.97#ibcon#enter wrdev, iclass 39, count 0 2006.257.22:18:57.97#ibcon#first serial, iclass 39, count 0 2006.257.22:18:57.97#ibcon#enter sib2, iclass 39, count 0 2006.257.22:18:57.97#ibcon#flushed, iclass 39, count 0 2006.257.22:18:57.97#ibcon#about to write, iclass 39, count 0 2006.257.22:18:57.97#ibcon#wrote, iclass 39, count 0 2006.257.22:18:57.97#ibcon#about to read 3, iclass 39, count 0 2006.257.22:18:57.99#ibcon#read 3, iclass 39, count 0 2006.257.22:18:57.99#ibcon#about to read 4, iclass 39, count 0 2006.257.22:18:57.99#ibcon#read 4, iclass 39, count 0 2006.257.22:18:57.99#ibcon#about to read 5, iclass 39, count 0 2006.257.22:18:57.99#ibcon#read 5, iclass 39, count 0 2006.257.22:18:57.99#ibcon#about to read 6, iclass 39, count 0 2006.257.22:18:57.99#ibcon#read 6, iclass 39, count 0 2006.257.22:18:57.99#ibcon#end of sib2, iclass 39, count 0 2006.257.22:18:57.99#ibcon#*mode == 0, iclass 39, count 0 2006.257.22:18:57.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.22:18:57.99#ibcon#[27=BW32\r\n] 2006.257.22:18:57.99#ibcon#*before write, iclass 39, count 0 2006.257.22:18:57.99#ibcon#enter sib2, iclass 39, count 0 2006.257.22:18:57.99#ibcon#flushed, iclass 39, count 0 2006.257.22:18:57.99#ibcon#about to write, iclass 39, count 0 2006.257.22:18:57.99#ibcon#wrote, iclass 39, count 0 2006.257.22:18:57.99#ibcon#about to read 3, iclass 39, count 0 2006.257.22:18:58.02#ibcon#read 3, iclass 39, count 0 2006.257.22:18:58.02#ibcon#about to read 4, iclass 39, count 0 2006.257.22:18:58.02#ibcon#read 4, iclass 39, count 0 2006.257.22:18:58.02#ibcon#about to read 5, iclass 39, count 0 2006.257.22:18:58.02#ibcon#read 5, iclass 39, count 0 2006.257.22:18:58.02#ibcon#about to read 6, iclass 39, count 0 2006.257.22:18:58.02#ibcon#read 6, iclass 39, count 0 2006.257.22:18:58.02#ibcon#end of sib2, iclass 39, count 0 2006.257.22:18:58.02#ibcon#*after write, iclass 39, count 0 2006.257.22:18:58.02#ibcon#*before return 0, iclass 39, count 0 2006.257.22:18:58.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:18:58.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:18:58.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.22:18:58.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.22:18:58.02$setupk4/ifdk4 2006.257.22:18:58.02$ifdk4/lo= 2006.257.22:18:58.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.22:18:58.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.22:18:58.02$ifdk4/patch= 2006.257.22:18:58.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.22:18:58.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.22:18:58.03$setupk4/!*+20s 2006.257.22:19:03.50#abcon#<5=/15 0.5 1.8 19.17 881015.9\r\n> 2006.257.22:19:03.52#abcon#{5=INTERFACE CLEAR} 2006.257.22:19:03.58#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:19:12.54$setupk4/"tpicd 2006.257.22:19:12.54$setupk4/echo=off 2006.257.22:19:12.54$setupk4/xlog=off 2006.257.22:19:12.54:!2006.257.22:20:50 2006.257.22:19:24.14#trakl#Source acquired 2006.257.22:19:24.14#flagr#flagr/antenna,acquired 2006.257.22:20:50.00:preob 2006.257.22:20:50.14/onsource/TRACKING 2006.257.22:20:50.14:!2006.257.22:21:00 2006.257.22:21:00.00:"tape 2006.257.22:21:00.00:"st=record 2006.257.22:21:00.00:data_valid=on 2006.257.22:21:00.00:midob 2006.257.22:21:00.14/onsource/TRACKING 2006.257.22:21:00.14/wx/19.23,1015.9,89 2006.257.22:21:00.35/cable/+6.4839E-03 2006.257.22:21:01.44/va/01,08,usb,yes,35,38 2006.257.22:21:01.44/va/02,07,usb,yes,38,38 2006.257.22:21:01.44/va/03,08,usb,yes,34,36 2006.257.22:21:01.44/va/04,07,usb,yes,39,41 2006.257.22:21:01.44/va/05,04,usb,yes,35,35 2006.257.22:21:01.44/va/06,04,usb,yes,39,38 2006.257.22:21:01.44/va/07,04,usb,yes,40,40 2006.257.22:21:01.44/va/08,04,usb,yes,33,40 2006.257.22:21:01.67/valo/01,524.99,yes,locked 2006.257.22:21:01.67/valo/02,534.99,yes,locked 2006.257.22:21:01.67/valo/03,564.99,yes,locked 2006.257.22:21:01.67/valo/04,624.99,yes,locked 2006.257.22:21:01.67/valo/05,734.99,yes,locked 2006.257.22:21:01.67/valo/06,814.99,yes,locked 2006.257.22:21:01.67/valo/07,864.99,yes,locked 2006.257.22:21:01.67/valo/08,884.99,yes,locked 2006.257.22:21:02.76/vb/01,04,usb,yes,39,36 2006.257.22:21:02.76/vb/02,05,usb,yes,37,37 2006.257.22:21:02.76/vb/03,04,usb,yes,38,42 2006.257.22:21:02.76/vb/04,05,usb,yes,38,37 2006.257.22:21:02.76/vb/05,04,usb,yes,34,37 2006.257.22:21:02.76/vb/06,04,usb,yes,40,35 2006.257.22:21:02.76/vb/07,04,usb,yes,39,39 2006.257.22:21:02.76/vb/08,04,usb,yes,36,40 2006.257.22:21:03.00/vblo/01,629.99,yes,locked 2006.257.22:21:03.00/vblo/02,634.99,yes,locked 2006.257.22:21:03.00/vblo/03,649.99,yes,locked 2006.257.22:21:03.00/vblo/04,679.99,yes,locked 2006.257.22:21:03.00/vblo/05,709.99,yes,locked 2006.257.22:21:03.00/vblo/06,719.99,yes,locked 2006.257.22:21:03.00/vblo/07,734.99,yes,locked 2006.257.22:21:03.00/vblo/08,744.99,yes,locked 2006.257.22:21:03.15/vabw/8 2006.257.22:21:03.30/vbbw/8 2006.257.22:21:03.46/xfe/off,on,15.5 2006.257.22:21:03.84/ifatt/23,28,28,28 2006.257.22:21:04.07/fmout-gps/S +4.53E-07 2006.257.22:21:04.11:!2006.257.22:22:50 2006.257.22:22:50.01:data_valid=off 2006.257.22:22:50.01:"et 2006.257.22:22:50.01:!+3s 2006.257.22:22:53.02:"tape 2006.257.22:22:53.02:postob 2006.257.22:22:53.27/cable/+6.4841E-03 2006.257.22:22:53.27/wx/19.26,1015.9,87 2006.257.22:22:53.33/fmout-gps/S +4.54E-07 2006.257.22:22:53.33:scan_name=257-2227,jd0609,200 2006.257.22:22:53.33:source=1044+719,104827.62,714335.9,2000.0,cw 2006.257.22:22:54.14#flagr#flagr/antenna,new-source 2006.257.22:22:54.14:checkk5 2006.257.22:22:54.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.22:22:54.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.22:22:55.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.22:22:55.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.22:22:55.83/chk_obsdata//k5ts1/T2572221??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.22:22:56.17/chk_obsdata//k5ts2/T2572221??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.22:22:56.50/chk_obsdata//k5ts3/T2572221??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.22:22:56.83/chk_obsdata//k5ts4/T2572221??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.257.22:22:57.49/k5log//k5ts1_log_newline 2006.257.22:22:58.15/k5log//k5ts2_log_newline 2006.257.22:22:58.80/k5log//k5ts3_log_newline 2006.257.22:22:59.45/k5log//k5ts4_log_newline 2006.257.22:22:59.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.22:22:59.47:setupk4=1 2006.257.22:22:59.47$setupk4/echo=on 2006.257.22:22:59.47$setupk4/pcalon 2006.257.22:22:59.47$pcalon/"no phase cal control is implemented here 2006.257.22:22:59.47$setupk4/"tpicd=stop 2006.257.22:22:59.47$setupk4/"rec=synch_on 2006.257.22:22:59.48$setupk4/"rec_mode=128 2006.257.22:22:59.48$setupk4/!* 2006.257.22:22:59.48$setupk4/recpk4 2006.257.22:22:59.48$recpk4/recpatch= 2006.257.22:22:59.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.22:22:59.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.22:22:59.48$setupk4/vck44 2006.257.22:22:59.48$vck44/valo=1,524.99 2006.257.22:22:59.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.22:22:59.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.22:22:59.48#ibcon#ireg 17 cls_cnt 0 2006.257.22:22:59.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:22:59.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:22:59.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:22:59.48#ibcon#enter wrdev, iclass 32, count 0 2006.257.22:22:59.48#ibcon#first serial, iclass 32, count 0 2006.257.22:22:59.48#ibcon#enter sib2, iclass 32, count 0 2006.257.22:22:59.48#ibcon#flushed, iclass 32, count 0 2006.257.22:22:59.48#ibcon#about to write, iclass 32, count 0 2006.257.22:22:59.48#ibcon#wrote, iclass 32, count 0 2006.257.22:22:59.48#ibcon#about to read 3, iclass 32, count 0 2006.257.22:22:59.49#ibcon#read 3, iclass 32, count 0 2006.257.22:22:59.49#ibcon#about to read 4, iclass 32, count 0 2006.257.22:22:59.49#ibcon#read 4, iclass 32, count 0 2006.257.22:22:59.49#ibcon#about to read 5, iclass 32, count 0 2006.257.22:22:59.49#ibcon#read 5, iclass 32, count 0 2006.257.22:22:59.49#ibcon#about to read 6, iclass 32, count 0 2006.257.22:22:59.49#ibcon#read 6, iclass 32, count 0 2006.257.22:22:59.49#ibcon#end of sib2, iclass 32, count 0 2006.257.22:22:59.49#ibcon#*mode == 0, iclass 32, count 0 2006.257.22:22:59.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.22:22:59.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.22:22:59.49#ibcon#*before write, iclass 32, count 0 2006.257.22:22:59.49#ibcon#enter sib2, iclass 32, count 0 2006.257.22:22:59.49#ibcon#flushed, iclass 32, count 0 2006.257.22:22:59.49#ibcon#about to write, iclass 32, count 0 2006.257.22:22:59.49#ibcon#wrote, iclass 32, count 0 2006.257.22:22:59.49#ibcon#about to read 3, iclass 32, count 0 2006.257.22:22:59.54#ibcon#read 3, iclass 32, count 0 2006.257.22:22:59.54#ibcon#about to read 4, iclass 32, count 0 2006.257.22:22:59.54#ibcon#read 4, iclass 32, count 0 2006.257.22:22:59.54#ibcon#about to read 5, iclass 32, count 0 2006.257.22:22:59.54#ibcon#read 5, iclass 32, count 0 2006.257.22:22:59.54#ibcon#about to read 6, iclass 32, count 0 2006.257.22:22:59.54#ibcon#read 6, iclass 32, count 0 2006.257.22:22:59.54#ibcon#end of sib2, iclass 32, count 0 2006.257.22:22:59.54#ibcon#*after write, iclass 32, count 0 2006.257.22:22:59.54#ibcon#*before return 0, iclass 32, count 0 2006.257.22:22:59.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:22:59.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:22:59.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.22:22:59.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.22:22:59.54$vck44/va=1,8 2006.257.22:22:59.54#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.22:22:59.54#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.22:22:59.54#ibcon#ireg 11 cls_cnt 2 2006.257.22:22:59.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:22:59.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:22:59.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:22:59.54#ibcon#enter wrdev, iclass 34, count 2 2006.257.22:22:59.54#ibcon#first serial, iclass 34, count 2 2006.257.22:22:59.54#ibcon#enter sib2, iclass 34, count 2 2006.257.22:22:59.54#ibcon#flushed, iclass 34, count 2 2006.257.22:22:59.54#ibcon#about to write, iclass 34, count 2 2006.257.22:22:59.54#ibcon#wrote, iclass 34, count 2 2006.257.22:22:59.54#ibcon#about to read 3, iclass 34, count 2 2006.257.22:22:59.56#ibcon#read 3, iclass 34, count 2 2006.257.22:22:59.56#ibcon#about to read 4, iclass 34, count 2 2006.257.22:22:59.56#ibcon#read 4, iclass 34, count 2 2006.257.22:22:59.56#ibcon#about to read 5, iclass 34, count 2 2006.257.22:22:59.56#ibcon#read 5, iclass 34, count 2 2006.257.22:22:59.56#ibcon#about to read 6, iclass 34, count 2 2006.257.22:22:59.56#ibcon#read 6, iclass 34, count 2 2006.257.22:22:59.56#ibcon#end of sib2, iclass 34, count 2 2006.257.22:22:59.56#ibcon#*mode == 0, iclass 34, count 2 2006.257.22:22:59.56#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.22:22:59.56#ibcon#[25=AT01-08\r\n] 2006.257.22:22:59.56#ibcon#*before write, iclass 34, count 2 2006.257.22:22:59.56#ibcon#enter sib2, iclass 34, count 2 2006.257.22:22:59.56#ibcon#flushed, iclass 34, count 2 2006.257.22:22:59.56#ibcon#about to write, iclass 34, count 2 2006.257.22:22:59.56#ibcon#wrote, iclass 34, count 2 2006.257.22:22:59.56#ibcon#about to read 3, iclass 34, count 2 2006.257.22:22:59.59#ibcon#read 3, iclass 34, count 2 2006.257.22:22:59.59#ibcon#about to read 4, iclass 34, count 2 2006.257.22:22:59.59#ibcon#read 4, iclass 34, count 2 2006.257.22:22:59.59#ibcon#about to read 5, iclass 34, count 2 2006.257.22:22:59.59#ibcon#read 5, iclass 34, count 2 2006.257.22:22:59.59#ibcon#about to read 6, iclass 34, count 2 2006.257.22:22:59.59#ibcon#read 6, iclass 34, count 2 2006.257.22:22:59.59#ibcon#end of sib2, iclass 34, count 2 2006.257.22:22:59.59#ibcon#*after write, iclass 34, count 2 2006.257.22:22:59.59#ibcon#*before return 0, iclass 34, count 2 2006.257.22:22:59.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:22:59.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:22:59.59#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.22:22:59.59#ibcon#ireg 7 cls_cnt 0 2006.257.22:22:59.59#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:22:59.71#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:22:59.71#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:22:59.71#ibcon#enter wrdev, iclass 34, count 0 2006.257.22:22:59.71#ibcon#first serial, iclass 34, count 0 2006.257.22:22:59.71#ibcon#enter sib2, iclass 34, count 0 2006.257.22:22:59.71#ibcon#flushed, iclass 34, count 0 2006.257.22:22:59.71#ibcon#about to write, iclass 34, count 0 2006.257.22:22:59.71#ibcon#wrote, iclass 34, count 0 2006.257.22:22:59.71#ibcon#about to read 3, iclass 34, count 0 2006.257.22:22:59.73#ibcon#read 3, iclass 34, count 0 2006.257.22:22:59.73#ibcon#about to read 4, iclass 34, count 0 2006.257.22:22:59.73#ibcon#read 4, iclass 34, count 0 2006.257.22:22:59.73#ibcon#about to read 5, iclass 34, count 0 2006.257.22:22:59.73#ibcon#read 5, iclass 34, count 0 2006.257.22:22:59.73#ibcon#about to read 6, iclass 34, count 0 2006.257.22:22:59.73#ibcon#read 6, iclass 34, count 0 2006.257.22:22:59.73#ibcon#end of sib2, iclass 34, count 0 2006.257.22:22:59.73#ibcon#*mode == 0, iclass 34, count 0 2006.257.22:22:59.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.22:22:59.73#ibcon#[25=USB\r\n] 2006.257.22:22:59.73#ibcon#*before write, iclass 34, count 0 2006.257.22:22:59.73#ibcon#enter sib2, iclass 34, count 0 2006.257.22:22:59.73#ibcon#flushed, iclass 34, count 0 2006.257.22:22:59.73#ibcon#about to write, iclass 34, count 0 2006.257.22:22:59.73#ibcon#wrote, iclass 34, count 0 2006.257.22:22:59.73#ibcon#about to read 3, iclass 34, count 0 2006.257.22:22:59.76#ibcon#read 3, iclass 34, count 0 2006.257.22:22:59.76#ibcon#about to read 4, iclass 34, count 0 2006.257.22:22:59.76#ibcon#read 4, iclass 34, count 0 2006.257.22:22:59.76#ibcon#about to read 5, iclass 34, count 0 2006.257.22:22:59.76#ibcon#read 5, iclass 34, count 0 2006.257.22:22:59.76#ibcon#about to read 6, iclass 34, count 0 2006.257.22:22:59.76#ibcon#read 6, iclass 34, count 0 2006.257.22:22:59.76#ibcon#end of sib2, iclass 34, count 0 2006.257.22:22:59.76#ibcon#*after write, iclass 34, count 0 2006.257.22:22:59.76#ibcon#*before return 0, iclass 34, count 0 2006.257.22:22:59.76#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:22:59.76#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:22:59.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.22:22:59.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.22:22:59.76$vck44/valo=2,534.99 2006.257.22:22:59.76#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.22:22:59.76#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.22:22:59.76#ibcon#ireg 17 cls_cnt 0 2006.257.22:22:59.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:22:59.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:22:59.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:22:59.76#ibcon#enter wrdev, iclass 36, count 0 2006.257.22:22:59.76#ibcon#first serial, iclass 36, count 0 2006.257.22:22:59.76#ibcon#enter sib2, iclass 36, count 0 2006.257.22:22:59.76#ibcon#flushed, iclass 36, count 0 2006.257.22:22:59.76#ibcon#about to write, iclass 36, count 0 2006.257.22:22:59.76#ibcon#wrote, iclass 36, count 0 2006.257.22:22:59.76#ibcon#about to read 3, iclass 36, count 0 2006.257.22:22:59.78#ibcon#read 3, iclass 36, count 0 2006.257.22:22:59.78#ibcon#about to read 4, iclass 36, count 0 2006.257.22:22:59.78#ibcon#read 4, iclass 36, count 0 2006.257.22:22:59.78#ibcon#about to read 5, iclass 36, count 0 2006.257.22:22:59.78#ibcon#read 5, iclass 36, count 0 2006.257.22:22:59.78#ibcon#about to read 6, iclass 36, count 0 2006.257.22:22:59.78#ibcon#read 6, iclass 36, count 0 2006.257.22:22:59.78#ibcon#end of sib2, iclass 36, count 0 2006.257.22:22:59.78#ibcon#*mode == 0, iclass 36, count 0 2006.257.22:22:59.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.22:22:59.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.22:22:59.78#ibcon#*before write, iclass 36, count 0 2006.257.22:22:59.78#ibcon#enter sib2, iclass 36, count 0 2006.257.22:22:59.78#ibcon#flushed, iclass 36, count 0 2006.257.22:22:59.78#ibcon#about to write, iclass 36, count 0 2006.257.22:22:59.78#ibcon#wrote, iclass 36, count 0 2006.257.22:22:59.78#ibcon#about to read 3, iclass 36, count 0 2006.257.22:22:59.82#ibcon#read 3, iclass 36, count 0 2006.257.22:22:59.82#ibcon#about to read 4, iclass 36, count 0 2006.257.22:22:59.82#ibcon#read 4, iclass 36, count 0 2006.257.22:22:59.82#ibcon#about to read 5, iclass 36, count 0 2006.257.22:22:59.82#ibcon#read 5, iclass 36, count 0 2006.257.22:22:59.82#ibcon#about to read 6, iclass 36, count 0 2006.257.22:22:59.82#ibcon#read 6, iclass 36, count 0 2006.257.22:22:59.82#ibcon#end of sib2, iclass 36, count 0 2006.257.22:22:59.82#ibcon#*after write, iclass 36, count 0 2006.257.22:22:59.82#ibcon#*before return 0, iclass 36, count 0 2006.257.22:22:59.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:22:59.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:22:59.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.22:22:59.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.22:22:59.82$vck44/va=2,7 2006.257.22:22:59.82#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.22:22:59.82#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.22:22:59.82#ibcon#ireg 11 cls_cnt 2 2006.257.22:22:59.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:22:59.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:22:59.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:22:59.88#ibcon#enter wrdev, iclass 38, count 2 2006.257.22:22:59.88#ibcon#first serial, iclass 38, count 2 2006.257.22:22:59.88#ibcon#enter sib2, iclass 38, count 2 2006.257.22:22:59.88#ibcon#flushed, iclass 38, count 2 2006.257.22:22:59.88#ibcon#about to write, iclass 38, count 2 2006.257.22:22:59.88#ibcon#wrote, iclass 38, count 2 2006.257.22:22:59.88#ibcon#about to read 3, iclass 38, count 2 2006.257.22:22:59.90#ibcon#read 3, iclass 38, count 2 2006.257.22:22:59.90#ibcon#about to read 4, iclass 38, count 2 2006.257.22:22:59.90#ibcon#read 4, iclass 38, count 2 2006.257.22:22:59.90#ibcon#about to read 5, iclass 38, count 2 2006.257.22:22:59.90#ibcon#read 5, iclass 38, count 2 2006.257.22:22:59.90#ibcon#about to read 6, iclass 38, count 2 2006.257.22:22:59.90#ibcon#read 6, iclass 38, count 2 2006.257.22:22:59.90#ibcon#end of sib2, iclass 38, count 2 2006.257.22:22:59.90#ibcon#*mode == 0, iclass 38, count 2 2006.257.22:22:59.90#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.22:22:59.90#ibcon#[25=AT02-07\r\n] 2006.257.22:22:59.90#ibcon#*before write, iclass 38, count 2 2006.257.22:22:59.90#ibcon#enter sib2, iclass 38, count 2 2006.257.22:22:59.90#ibcon#flushed, iclass 38, count 2 2006.257.22:22:59.90#ibcon#about to write, iclass 38, count 2 2006.257.22:22:59.90#ibcon#wrote, iclass 38, count 2 2006.257.22:22:59.90#ibcon#about to read 3, iclass 38, count 2 2006.257.22:22:59.93#ibcon#read 3, iclass 38, count 2 2006.257.22:22:59.93#ibcon#about to read 4, iclass 38, count 2 2006.257.22:22:59.93#ibcon#read 4, iclass 38, count 2 2006.257.22:22:59.93#ibcon#about to read 5, iclass 38, count 2 2006.257.22:22:59.93#ibcon#read 5, iclass 38, count 2 2006.257.22:22:59.93#ibcon#about to read 6, iclass 38, count 2 2006.257.22:22:59.93#ibcon#read 6, iclass 38, count 2 2006.257.22:22:59.93#ibcon#end of sib2, iclass 38, count 2 2006.257.22:22:59.93#ibcon#*after write, iclass 38, count 2 2006.257.22:22:59.93#ibcon#*before return 0, iclass 38, count 2 2006.257.22:22:59.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:22:59.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:22:59.93#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.22:22:59.93#ibcon#ireg 7 cls_cnt 0 2006.257.22:22:59.93#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:00.05#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:00.05#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:00.05#ibcon#enter wrdev, iclass 38, count 0 2006.257.22:23:00.05#ibcon#first serial, iclass 38, count 0 2006.257.22:23:00.05#ibcon#enter sib2, iclass 38, count 0 2006.257.22:23:00.05#ibcon#flushed, iclass 38, count 0 2006.257.22:23:00.05#ibcon#about to write, iclass 38, count 0 2006.257.22:23:00.05#ibcon#wrote, iclass 38, count 0 2006.257.22:23:00.05#ibcon#about to read 3, iclass 38, count 0 2006.257.22:23:00.07#ibcon#read 3, iclass 38, count 0 2006.257.22:23:00.07#ibcon#about to read 4, iclass 38, count 0 2006.257.22:23:00.07#ibcon#read 4, iclass 38, count 0 2006.257.22:23:00.07#ibcon#about to read 5, iclass 38, count 0 2006.257.22:23:00.07#ibcon#read 5, iclass 38, count 0 2006.257.22:23:00.07#ibcon#about to read 6, iclass 38, count 0 2006.257.22:23:00.07#ibcon#read 6, iclass 38, count 0 2006.257.22:23:00.07#ibcon#end of sib2, iclass 38, count 0 2006.257.22:23:00.07#ibcon#*mode == 0, iclass 38, count 0 2006.257.22:23:00.07#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.22:23:00.07#ibcon#[25=USB\r\n] 2006.257.22:23:00.07#ibcon#*before write, iclass 38, count 0 2006.257.22:23:00.07#ibcon#enter sib2, iclass 38, count 0 2006.257.22:23:00.07#ibcon#flushed, iclass 38, count 0 2006.257.22:23:00.07#ibcon#about to write, iclass 38, count 0 2006.257.22:23:00.07#ibcon#wrote, iclass 38, count 0 2006.257.22:23:00.07#ibcon#about to read 3, iclass 38, count 0 2006.257.22:23:00.10#ibcon#read 3, iclass 38, count 0 2006.257.22:23:00.10#ibcon#about to read 4, iclass 38, count 0 2006.257.22:23:00.10#ibcon#read 4, iclass 38, count 0 2006.257.22:23:00.10#ibcon#about to read 5, iclass 38, count 0 2006.257.22:23:00.10#ibcon#read 5, iclass 38, count 0 2006.257.22:23:00.10#ibcon#about to read 6, iclass 38, count 0 2006.257.22:23:00.10#ibcon#read 6, iclass 38, count 0 2006.257.22:23:00.10#ibcon#end of sib2, iclass 38, count 0 2006.257.22:23:00.10#ibcon#*after write, iclass 38, count 0 2006.257.22:23:00.10#ibcon#*before return 0, iclass 38, count 0 2006.257.22:23:00.10#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:00.10#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:00.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.22:23:00.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.22:23:00.10$vck44/valo=3,564.99 2006.257.22:23:00.10#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.22:23:00.10#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.22:23:00.10#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:00.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:00.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:00.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:00.10#ibcon#enter wrdev, iclass 40, count 0 2006.257.22:23:00.10#ibcon#first serial, iclass 40, count 0 2006.257.22:23:00.10#ibcon#enter sib2, iclass 40, count 0 2006.257.22:23:00.10#ibcon#flushed, iclass 40, count 0 2006.257.22:23:00.10#ibcon#about to write, iclass 40, count 0 2006.257.22:23:00.10#ibcon#wrote, iclass 40, count 0 2006.257.22:23:00.10#ibcon#about to read 3, iclass 40, count 0 2006.257.22:23:00.12#ibcon#read 3, iclass 40, count 0 2006.257.22:23:00.12#ibcon#about to read 4, iclass 40, count 0 2006.257.22:23:00.12#ibcon#read 4, iclass 40, count 0 2006.257.22:23:00.12#ibcon#about to read 5, iclass 40, count 0 2006.257.22:23:00.12#ibcon#read 5, iclass 40, count 0 2006.257.22:23:00.12#ibcon#about to read 6, iclass 40, count 0 2006.257.22:23:00.12#ibcon#read 6, iclass 40, count 0 2006.257.22:23:00.12#ibcon#end of sib2, iclass 40, count 0 2006.257.22:23:00.12#ibcon#*mode == 0, iclass 40, count 0 2006.257.22:23:00.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.22:23:00.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.22:23:00.12#ibcon#*before write, iclass 40, count 0 2006.257.22:23:00.12#ibcon#enter sib2, iclass 40, count 0 2006.257.22:23:00.12#ibcon#flushed, iclass 40, count 0 2006.257.22:23:00.12#ibcon#about to write, iclass 40, count 0 2006.257.22:23:00.12#ibcon#wrote, iclass 40, count 0 2006.257.22:23:00.12#ibcon#about to read 3, iclass 40, count 0 2006.257.22:23:00.16#ibcon#read 3, iclass 40, count 0 2006.257.22:23:00.16#ibcon#about to read 4, iclass 40, count 0 2006.257.22:23:00.16#ibcon#read 4, iclass 40, count 0 2006.257.22:23:00.16#ibcon#about to read 5, iclass 40, count 0 2006.257.22:23:00.16#ibcon#read 5, iclass 40, count 0 2006.257.22:23:00.16#ibcon#about to read 6, iclass 40, count 0 2006.257.22:23:00.16#ibcon#read 6, iclass 40, count 0 2006.257.22:23:00.16#ibcon#end of sib2, iclass 40, count 0 2006.257.22:23:00.16#ibcon#*after write, iclass 40, count 0 2006.257.22:23:00.16#ibcon#*before return 0, iclass 40, count 0 2006.257.22:23:00.16#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:00.16#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:00.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.22:23:00.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.22:23:00.16$vck44/va=3,8 2006.257.22:23:00.16#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.22:23:00.16#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.22:23:00.16#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:00.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:00.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:00.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:00.22#ibcon#enter wrdev, iclass 4, count 2 2006.257.22:23:00.22#ibcon#first serial, iclass 4, count 2 2006.257.22:23:00.22#ibcon#enter sib2, iclass 4, count 2 2006.257.22:23:00.22#ibcon#flushed, iclass 4, count 2 2006.257.22:23:00.22#ibcon#about to write, iclass 4, count 2 2006.257.22:23:00.22#ibcon#wrote, iclass 4, count 2 2006.257.22:23:00.22#ibcon#about to read 3, iclass 4, count 2 2006.257.22:23:00.24#ibcon#read 3, iclass 4, count 2 2006.257.22:23:00.24#ibcon#about to read 4, iclass 4, count 2 2006.257.22:23:00.24#ibcon#read 4, iclass 4, count 2 2006.257.22:23:00.24#ibcon#about to read 5, iclass 4, count 2 2006.257.22:23:00.24#ibcon#read 5, iclass 4, count 2 2006.257.22:23:00.24#ibcon#about to read 6, iclass 4, count 2 2006.257.22:23:00.24#ibcon#read 6, iclass 4, count 2 2006.257.22:23:00.24#ibcon#end of sib2, iclass 4, count 2 2006.257.22:23:00.24#ibcon#*mode == 0, iclass 4, count 2 2006.257.22:23:00.24#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.22:23:00.24#ibcon#[25=AT03-08\r\n] 2006.257.22:23:00.24#ibcon#*before write, iclass 4, count 2 2006.257.22:23:00.24#ibcon#enter sib2, iclass 4, count 2 2006.257.22:23:00.24#ibcon#flushed, iclass 4, count 2 2006.257.22:23:00.24#ibcon#about to write, iclass 4, count 2 2006.257.22:23:00.24#ibcon#wrote, iclass 4, count 2 2006.257.22:23:00.24#ibcon#about to read 3, iclass 4, count 2 2006.257.22:23:00.27#ibcon#read 3, iclass 4, count 2 2006.257.22:23:00.27#ibcon#about to read 4, iclass 4, count 2 2006.257.22:23:00.27#ibcon#read 4, iclass 4, count 2 2006.257.22:23:00.27#ibcon#about to read 5, iclass 4, count 2 2006.257.22:23:00.27#ibcon#read 5, iclass 4, count 2 2006.257.22:23:00.27#ibcon#about to read 6, iclass 4, count 2 2006.257.22:23:00.27#ibcon#read 6, iclass 4, count 2 2006.257.22:23:00.27#ibcon#end of sib2, iclass 4, count 2 2006.257.22:23:00.27#ibcon#*after write, iclass 4, count 2 2006.257.22:23:00.27#ibcon#*before return 0, iclass 4, count 2 2006.257.22:23:00.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:00.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:00.27#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.22:23:00.27#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:00.27#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:00.39#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:00.39#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:00.39#ibcon#enter wrdev, iclass 4, count 0 2006.257.22:23:00.39#ibcon#first serial, iclass 4, count 0 2006.257.22:23:00.39#ibcon#enter sib2, iclass 4, count 0 2006.257.22:23:00.39#ibcon#flushed, iclass 4, count 0 2006.257.22:23:00.39#ibcon#about to write, iclass 4, count 0 2006.257.22:23:00.39#ibcon#wrote, iclass 4, count 0 2006.257.22:23:00.39#ibcon#about to read 3, iclass 4, count 0 2006.257.22:23:00.41#ibcon#read 3, iclass 4, count 0 2006.257.22:23:00.41#ibcon#about to read 4, iclass 4, count 0 2006.257.22:23:00.41#ibcon#read 4, iclass 4, count 0 2006.257.22:23:00.41#ibcon#about to read 5, iclass 4, count 0 2006.257.22:23:00.41#ibcon#read 5, iclass 4, count 0 2006.257.22:23:00.41#ibcon#about to read 6, iclass 4, count 0 2006.257.22:23:00.41#ibcon#read 6, iclass 4, count 0 2006.257.22:23:00.41#ibcon#end of sib2, iclass 4, count 0 2006.257.22:23:00.41#ibcon#*mode == 0, iclass 4, count 0 2006.257.22:23:00.41#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.22:23:00.41#ibcon#[25=USB\r\n] 2006.257.22:23:00.41#ibcon#*before write, iclass 4, count 0 2006.257.22:23:00.41#ibcon#enter sib2, iclass 4, count 0 2006.257.22:23:00.41#ibcon#flushed, iclass 4, count 0 2006.257.22:23:00.41#ibcon#about to write, iclass 4, count 0 2006.257.22:23:00.41#ibcon#wrote, iclass 4, count 0 2006.257.22:23:00.41#ibcon#about to read 3, iclass 4, count 0 2006.257.22:23:00.44#ibcon#read 3, iclass 4, count 0 2006.257.22:23:00.44#ibcon#about to read 4, iclass 4, count 0 2006.257.22:23:00.44#ibcon#read 4, iclass 4, count 0 2006.257.22:23:00.44#ibcon#about to read 5, iclass 4, count 0 2006.257.22:23:00.44#ibcon#read 5, iclass 4, count 0 2006.257.22:23:00.44#ibcon#about to read 6, iclass 4, count 0 2006.257.22:23:00.44#ibcon#read 6, iclass 4, count 0 2006.257.22:23:00.44#ibcon#end of sib2, iclass 4, count 0 2006.257.22:23:00.44#ibcon#*after write, iclass 4, count 0 2006.257.22:23:00.44#ibcon#*before return 0, iclass 4, count 0 2006.257.22:23:00.44#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:00.44#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:00.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.22:23:00.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.22:23:00.44$vck44/valo=4,624.99 2006.257.22:23:00.44#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.22:23:00.44#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.22:23:00.44#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:00.44#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:00.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:00.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:00.44#ibcon#enter wrdev, iclass 6, count 0 2006.257.22:23:00.44#ibcon#first serial, iclass 6, count 0 2006.257.22:23:00.44#ibcon#enter sib2, iclass 6, count 0 2006.257.22:23:00.44#ibcon#flushed, iclass 6, count 0 2006.257.22:23:00.44#ibcon#about to write, iclass 6, count 0 2006.257.22:23:00.44#ibcon#wrote, iclass 6, count 0 2006.257.22:23:00.44#ibcon#about to read 3, iclass 6, count 0 2006.257.22:23:00.46#ibcon#read 3, iclass 6, count 0 2006.257.22:23:00.46#ibcon#about to read 4, iclass 6, count 0 2006.257.22:23:00.46#ibcon#read 4, iclass 6, count 0 2006.257.22:23:00.46#ibcon#about to read 5, iclass 6, count 0 2006.257.22:23:00.46#ibcon#read 5, iclass 6, count 0 2006.257.22:23:00.46#ibcon#about to read 6, iclass 6, count 0 2006.257.22:23:00.46#ibcon#read 6, iclass 6, count 0 2006.257.22:23:00.46#ibcon#end of sib2, iclass 6, count 0 2006.257.22:23:00.46#ibcon#*mode == 0, iclass 6, count 0 2006.257.22:23:00.46#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.22:23:00.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.22:23:00.46#ibcon#*before write, iclass 6, count 0 2006.257.22:23:00.46#ibcon#enter sib2, iclass 6, count 0 2006.257.22:23:00.46#ibcon#flushed, iclass 6, count 0 2006.257.22:23:00.46#ibcon#about to write, iclass 6, count 0 2006.257.22:23:00.46#ibcon#wrote, iclass 6, count 0 2006.257.22:23:00.46#ibcon#about to read 3, iclass 6, count 0 2006.257.22:23:00.50#ibcon#read 3, iclass 6, count 0 2006.257.22:23:00.50#ibcon#about to read 4, iclass 6, count 0 2006.257.22:23:00.50#ibcon#read 4, iclass 6, count 0 2006.257.22:23:00.50#ibcon#about to read 5, iclass 6, count 0 2006.257.22:23:00.50#ibcon#read 5, iclass 6, count 0 2006.257.22:23:00.50#ibcon#about to read 6, iclass 6, count 0 2006.257.22:23:00.50#ibcon#read 6, iclass 6, count 0 2006.257.22:23:00.50#ibcon#end of sib2, iclass 6, count 0 2006.257.22:23:00.50#ibcon#*after write, iclass 6, count 0 2006.257.22:23:00.50#ibcon#*before return 0, iclass 6, count 0 2006.257.22:23:00.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:00.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:00.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.22:23:00.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.22:23:00.50$vck44/va=4,7 2006.257.22:23:00.50#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.22:23:00.50#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.22:23:00.50#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:00.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:00.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:00.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:00.56#ibcon#enter wrdev, iclass 10, count 2 2006.257.22:23:00.56#ibcon#first serial, iclass 10, count 2 2006.257.22:23:00.56#ibcon#enter sib2, iclass 10, count 2 2006.257.22:23:00.56#ibcon#flushed, iclass 10, count 2 2006.257.22:23:00.56#ibcon#about to write, iclass 10, count 2 2006.257.22:23:00.56#ibcon#wrote, iclass 10, count 2 2006.257.22:23:00.56#ibcon#about to read 3, iclass 10, count 2 2006.257.22:23:00.58#ibcon#read 3, iclass 10, count 2 2006.257.22:23:00.58#ibcon#about to read 4, iclass 10, count 2 2006.257.22:23:00.58#ibcon#read 4, iclass 10, count 2 2006.257.22:23:00.58#ibcon#about to read 5, iclass 10, count 2 2006.257.22:23:00.58#ibcon#read 5, iclass 10, count 2 2006.257.22:23:00.58#ibcon#about to read 6, iclass 10, count 2 2006.257.22:23:00.58#ibcon#read 6, iclass 10, count 2 2006.257.22:23:00.58#ibcon#end of sib2, iclass 10, count 2 2006.257.22:23:00.58#ibcon#*mode == 0, iclass 10, count 2 2006.257.22:23:00.58#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.22:23:00.58#ibcon#[25=AT04-07\r\n] 2006.257.22:23:00.58#ibcon#*before write, iclass 10, count 2 2006.257.22:23:00.58#ibcon#enter sib2, iclass 10, count 2 2006.257.22:23:00.58#ibcon#flushed, iclass 10, count 2 2006.257.22:23:00.58#ibcon#about to write, iclass 10, count 2 2006.257.22:23:00.58#ibcon#wrote, iclass 10, count 2 2006.257.22:23:00.58#ibcon#about to read 3, iclass 10, count 2 2006.257.22:23:00.61#ibcon#read 3, iclass 10, count 2 2006.257.22:23:00.61#ibcon#about to read 4, iclass 10, count 2 2006.257.22:23:00.61#ibcon#read 4, iclass 10, count 2 2006.257.22:23:00.61#ibcon#about to read 5, iclass 10, count 2 2006.257.22:23:00.61#ibcon#read 5, iclass 10, count 2 2006.257.22:23:00.61#ibcon#about to read 6, iclass 10, count 2 2006.257.22:23:00.61#ibcon#read 6, iclass 10, count 2 2006.257.22:23:00.61#ibcon#end of sib2, iclass 10, count 2 2006.257.22:23:00.61#ibcon#*after write, iclass 10, count 2 2006.257.22:23:00.61#ibcon#*before return 0, iclass 10, count 2 2006.257.22:23:00.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:00.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:00.61#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.22:23:00.61#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:00.61#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:00.73#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:00.73#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:00.73#ibcon#enter wrdev, iclass 10, count 0 2006.257.22:23:00.73#ibcon#first serial, iclass 10, count 0 2006.257.22:23:00.73#ibcon#enter sib2, iclass 10, count 0 2006.257.22:23:00.73#ibcon#flushed, iclass 10, count 0 2006.257.22:23:00.73#ibcon#about to write, iclass 10, count 0 2006.257.22:23:00.73#ibcon#wrote, iclass 10, count 0 2006.257.22:23:00.73#ibcon#about to read 3, iclass 10, count 0 2006.257.22:23:00.75#ibcon#read 3, iclass 10, count 0 2006.257.22:23:00.75#ibcon#about to read 4, iclass 10, count 0 2006.257.22:23:00.75#ibcon#read 4, iclass 10, count 0 2006.257.22:23:00.75#ibcon#about to read 5, iclass 10, count 0 2006.257.22:23:00.75#ibcon#read 5, iclass 10, count 0 2006.257.22:23:00.75#ibcon#about to read 6, iclass 10, count 0 2006.257.22:23:00.75#ibcon#read 6, iclass 10, count 0 2006.257.22:23:00.75#ibcon#end of sib2, iclass 10, count 0 2006.257.22:23:00.75#ibcon#*mode == 0, iclass 10, count 0 2006.257.22:23:00.75#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.22:23:00.75#ibcon#[25=USB\r\n] 2006.257.22:23:00.75#ibcon#*before write, iclass 10, count 0 2006.257.22:23:00.75#ibcon#enter sib2, iclass 10, count 0 2006.257.22:23:00.75#ibcon#flushed, iclass 10, count 0 2006.257.22:23:00.75#ibcon#about to write, iclass 10, count 0 2006.257.22:23:00.75#ibcon#wrote, iclass 10, count 0 2006.257.22:23:00.75#ibcon#about to read 3, iclass 10, count 0 2006.257.22:23:00.78#ibcon#read 3, iclass 10, count 0 2006.257.22:23:00.78#ibcon#about to read 4, iclass 10, count 0 2006.257.22:23:00.78#ibcon#read 4, iclass 10, count 0 2006.257.22:23:00.78#ibcon#about to read 5, iclass 10, count 0 2006.257.22:23:00.78#ibcon#read 5, iclass 10, count 0 2006.257.22:23:00.78#ibcon#about to read 6, iclass 10, count 0 2006.257.22:23:00.78#ibcon#read 6, iclass 10, count 0 2006.257.22:23:00.78#ibcon#end of sib2, iclass 10, count 0 2006.257.22:23:00.78#ibcon#*after write, iclass 10, count 0 2006.257.22:23:00.78#ibcon#*before return 0, iclass 10, count 0 2006.257.22:23:00.78#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:00.78#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:00.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.22:23:00.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.22:23:00.78$vck44/valo=5,734.99 2006.257.22:23:00.78#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.22:23:00.78#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.22:23:00.78#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:00.78#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:00.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:00.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:00.78#ibcon#enter wrdev, iclass 12, count 0 2006.257.22:23:00.78#ibcon#first serial, iclass 12, count 0 2006.257.22:23:00.78#ibcon#enter sib2, iclass 12, count 0 2006.257.22:23:00.78#ibcon#flushed, iclass 12, count 0 2006.257.22:23:00.78#ibcon#about to write, iclass 12, count 0 2006.257.22:23:00.78#ibcon#wrote, iclass 12, count 0 2006.257.22:23:00.78#ibcon#about to read 3, iclass 12, count 0 2006.257.22:23:00.80#ibcon#read 3, iclass 12, count 0 2006.257.22:23:00.80#ibcon#about to read 4, iclass 12, count 0 2006.257.22:23:00.80#ibcon#read 4, iclass 12, count 0 2006.257.22:23:00.80#ibcon#about to read 5, iclass 12, count 0 2006.257.22:23:00.80#ibcon#read 5, iclass 12, count 0 2006.257.22:23:00.80#ibcon#about to read 6, iclass 12, count 0 2006.257.22:23:00.80#ibcon#read 6, iclass 12, count 0 2006.257.22:23:00.80#ibcon#end of sib2, iclass 12, count 0 2006.257.22:23:00.80#ibcon#*mode == 0, iclass 12, count 0 2006.257.22:23:00.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.22:23:00.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.22:23:00.80#ibcon#*before write, iclass 12, count 0 2006.257.22:23:00.80#ibcon#enter sib2, iclass 12, count 0 2006.257.22:23:00.80#ibcon#flushed, iclass 12, count 0 2006.257.22:23:00.80#ibcon#about to write, iclass 12, count 0 2006.257.22:23:00.80#ibcon#wrote, iclass 12, count 0 2006.257.22:23:00.80#ibcon#about to read 3, iclass 12, count 0 2006.257.22:23:00.84#ibcon#read 3, iclass 12, count 0 2006.257.22:23:00.84#ibcon#about to read 4, iclass 12, count 0 2006.257.22:23:00.84#ibcon#read 4, iclass 12, count 0 2006.257.22:23:00.84#ibcon#about to read 5, iclass 12, count 0 2006.257.22:23:00.84#ibcon#read 5, iclass 12, count 0 2006.257.22:23:00.84#ibcon#about to read 6, iclass 12, count 0 2006.257.22:23:00.84#ibcon#read 6, iclass 12, count 0 2006.257.22:23:00.84#ibcon#end of sib2, iclass 12, count 0 2006.257.22:23:00.84#ibcon#*after write, iclass 12, count 0 2006.257.22:23:00.84#ibcon#*before return 0, iclass 12, count 0 2006.257.22:23:00.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:00.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:00.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.22:23:00.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.22:23:00.84$vck44/va=5,4 2006.257.22:23:00.84#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.22:23:00.84#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.22:23:00.84#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:00.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:00.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:00.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:00.90#ibcon#enter wrdev, iclass 14, count 2 2006.257.22:23:00.90#ibcon#first serial, iclass 14, count 2 2006.257.22:23:00.90#ibcon#enter sib2, iclass 14, count 2 2006.257.22:23:00.90#ibcon#flushed, iclass 14, count 2 2006.257.22:23:00.90#ibcon#about to write, iclass 14, count 2 2006.257.22:23:00.90#ibcon#wrote, iclass 14, count 2 2006.257.22:23:00.90#ibcon#about to read 3, iclass 14, count 2 2006.257.22:23:00.92#ibcon#read 3, iclass 14, count 2 2006.257.22:23:00.92#ibcon#about to read 4, iclass 14, count 2 2006.257.22:23:00.92#ibcon#read 4, iclass 14, count 2 2006.257.22:23:00.92#ibcon#about to read 5, iclass 14, count 2 2006.257.22:23:00.92#ibcon#read 5, iclass 14, count 2 2006.257.22:23:00.92#ibcon#about to read 6, iclass 14, count 2 2006.257.22:23:00.92#ibcon#read 6, iclass 14, count 2 2006.257.22:23:00.92#ibcon#end of sib2, iclass 14, count 2 2006.257.22:23:00.92#ibcon#*mode == 0, iclass 14, count 2 2006.257.22:23:00.92#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.22:23:00.92#ibcon#[25=AT05-04\r\n] 2006.257.22:23:00.92#ibcon#*before write, iclass 14, count 2 2006.257.22:23:00.92#ibcon#enter sib2, iclass 14, count 2 2006.257.22:23:00.92#ibcon#flushed, iclass 14, count 2 2006.257.22:23:00.92#ibcon#about to write, iclass 14, count 2 2006.257.22:23:00.92#ibcon#wrote, iclass 14, count 2 2006.257.22:23:00.92#ibcon#about to read 3, iclass 14, count 2 2006.257.22:23:00.95#ibcon#read 3, iclass 14, count 2 2006.257.22:23:00.95#ibcon#about to read 4, iclass 14, count 2 2006.257.22:23:00.95#ibcon#read 4, iclass 14, count 2 2006.257.22:23:00.95#ibcon#about to read 5, iclass 14, count 2 2006.257.22:23:00.95#ibcon#read 5, iclass 14, count 2 2006.257.22:23:00.95#ibcon#about to read 6, iclass 14, count 2 2006.257.22:23:00.95#ibcon#read 6, iclass 14, count 2 2006.257.22:23:00.95#ibcon#end of sib2, iclass 14, count 2 2006.257.22:23:00.95#ibcon#*after write, iclass 14, count 2 2006.257.22:23:00.95#ibcon#*before return 0, iclass 14, count 2 2006.257.22:23:00.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:00.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:00.95#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.22:23:00.95#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:00.95#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:01.07#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:01.07#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:01.07#ibcon#enter wrdev, iclass 14, count 0 2006.257.22:23:01.07#ibcon#first serial, iclass 14, count 0 2006.257.22:23:01.07#ibcon#enter sib2, iclass 14, count 0 2006.257.22:23:01.07#ibcon#flushed, iclass 14, count 0 2006.257.22:23:01.07#ibcon#about to write, iclass 14, count 0 2006.257.22:23:01.07#ibcon#wrote, iclass 14, count 0 2006.257.22:23:01.07#ibcon#about to read 3, iclass 14, count 0 2006.257.22:23:01.09#ibcon#read 3, iclass 14, count 0 2006.257.22:23:01.09#ibcon#about to read 4, iclass 14, count 0 2006.257.22:23:01.09#ibcon#read 4, iclass 14, count 0 2006.257.22:23:01.09#ibcon#about to read 5, iclass 14, count 0 2006.257.22:23:01.09#ibcon#read 5, iclass 14, count 0 2006.257.22:23:01.09#ibcon#about to read 6, iclass 14, count 0 2006.257.22:23:01.09#ibcon#read 6, iclass 14, count 0 2006.257.22:23:01.09#ibcon#end of sib2, iclass 14, count 0 2006.257.22:23:01.09#ibcon#*mode == 0, iclass 14, count 0 2006.257.22:23:01.09#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.22:23:01.09#ibcon#[25=USB\r\n] 2006.257.22:23:01.09#ibcon#*before write, iclass 14, count 0 2006.257.22:23:01.09#ibcon#enter sib2, iclass 14, count 0 2006.257.22:23:01.09#ibcon#flushed, iclass 14, count 0 2006.257.22:23:01.09#ibcon#about to write, iclass 14, count 0 2006.257.22:23:01.09#ibcon#wrote, iclass 14, count 0 2006.257.22:23:01.09#ibcon#about to read 3, iclass 14, count 0 2006.257.22:23:01.12#ibcon#read 3, iclass 14, count 0 2006.257.22:23:01.12#ibcon#about to read 4, iclass 14, count 0 2006.257.22:23:01.12#ibcon#read 4, iclass 14, count 0 2006.257.22:23:01.12#ibcon#about to read 5, iclass 14, count 0 2006.257.22:23:01.12#ibcon#read 5, iclass 14, count 0 2006.257.22:23:01.12#ibcon#about to read 6, iclass 14, count 0 2006.257.22:23:01.12#ibcon#read 6, iclass 14, count 0 2006.257.22:23:01.12#ibcon#end of sib2, iclass 14, count 0 2006.257.22:23:01.12#ibcon#*after write, iclass 14, count 0 2006.257.22:23:01.12#ibcon#*before return 0, iclass 14, count 0 2006.257.22:23:01.12#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:01.12#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:01.12#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.22:23:01.12#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.22:23:01.12$vck44/valo=6,814.99 2006.257.22:23:01.12#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.22:23:01.12#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.22:23:01.12#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:01.12#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:01.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:01.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:01.12#ibcon#enter wrdev, iclass 16, count 0 2006.257.22:23:01.12#ibcon#first serial, iclass 16, count 0 2006.257.22:23:01.12#ibcon#enter sib2, iclass 16, count 0 2006.257.22:23:01.12#ibcon#flushed, iclass 16, count 0 2006.257.22:23:01.12#ibcon#about to write, iclass 16, count 0 2006.257.22:23:01.12#ibcon#wrote, iclass 16, count 0 2006.257.22:23:01.12#ibcon#about to read 3, iclass 16, count 0 2006.257.22:23:01.14#ibcon#read 3, iclass 16, count 0 2006.257.22:23:01.14#ibcon#about to read 4, iclass 16, count 0 2006.257.22:23:01.14#ibcon#read 4, iclass 16, count 0 2006.257.22:23:01.14#ibcon#about to read 5, iclass 16, count 0 2006.257.22:23:01.14#ibcon#read 5, iclass 16, count 0 2006.257.22:23:01.14#ibcon#about to read 6, iclass 16, count 0 2006.257.22:23:01.14#ibcon#read 6, iclass 16, count 0 2006.257.22:23:01.14#ibcon#end of sib2, iclass 16, count 0 2006.257.22:23:01.14#ibcon#*mode == 0, iclass 16, count 0 2006.257.22:23:01.14#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.22:23:01.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.22:23:01.14#ibcon#*before write, iclass 16, count 0 2006.257.22:23:01.14#ibcon#enter sib2, iclass 16, count 0 2006.257.22:23:01.14#ibcon#flushed, iclass 16, count 0 2006.257.22:23:01.14#ibcon#about to write, iclass 16, count 0 2006.257.22:23:01.14#ibcon#wrote, iclass 16, count 0 2006.257.22:23:01.14#ibcon#about to read 3, iclass 16, count 0 2006.257.22:23:01.18#ibcon#read 3, iclass 16, count 0 2006.257.22:23:01.18#ibcon#about to read 4, iclass 16, count 0 2006.257.22:23:01.18#ibcon#read 4, iclass 16, count 0 2006.257.22:23:01.18#ibcon#about to read 5, iclass 16, count 0 2006.257.22:23:01.18#ibcon#read 5, iclass 16, count 0 2006.257.22:23:01.18#ibcon#about to read 6, iclass 16, count 0 2006.257.22:23:01.18#ibcon#read 6, iclass 16, count 0 2006.257.22:23:01.18#ibcon#end of sib2, iclass 16, count 0 2006.257.22:23:01.18#ibcon#*after write, iclass 16, count 0 2006.257.22:23:01.18#ibcon#*before return 0, iclass 16, count 0 2006.257.22:23:01.18#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:01.18#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:01.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.22:23:01.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.22:23:01.18$vck44/va=6,4 2006.257.22:23:01.18#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.22:23:01.18#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.22:23:01.18#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:01.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:01.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:01.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:01.24#ibcon#enter wrdev, iclass 18, count 2 2006.257.22:23:01.24#ibcon#first serial, iclass 18, count 2 2006.257.22:23:01.24#ibcon#enter sib2, iclass 18, count 2 2006.257.22:23:01.24#ibcon#flushed, iclass 18, count 2 2006.257.22:23:01.24#ibcon#about to write, iclass 18, count 2 2006.257.22:23:01.24#ibcon#wrote, iclass 18, count 2 2006.257.22:23:01.24#ibcon#about to read 3, iclass 18, count 2 2006.257.22:23:01.26#ibcon#read 3, iclass 18, count 2 2006.257.22:23:01.26#ibcon#about to read 4, iclass 18, count 2 2006.257.22:23:01.26#ibcon#read 4, iclass 18, count 2 2006.257.22:23:01.26#ibcon#about to read 5, iclass 18, count 2 2006.257.22:23:01.26#ibcon#read 5, iclass 18, count 2 2006.257.22:23:01.26#ibcon#about to read 6, iclass 18, count 2 2006.257.22:23:01.26#ibcon#read 6, iclass 18, count 2 2006.257.22:23:01.26#ibcon#end of sib2, iclass 18, count 2 2006.257.22:23:01.26#ibcon#*mode == 0, iclass 18, count 2 2006.257.22:23:01.26#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.22:23:01.26#ibcon#[25=AT06-04\r\n] 2006.257.22:23:01.26#ibcon#*before write, iclass 18, count 2 2006.257.22:23:01.26#ibcon#enter sib2, iclass 18, count 2 2006.257.22:23:01.26#ibcon#flushed, iclass 18, count 2 2006.257.22:23:01.26#ibcon#about to write, iclass 18, count 2 2006.257.22:23:01.26#ibcon#wrote, iclass 18, count 2 2006.257.22:23:01.26#ibcon#about to read 3, iclass 18, count 2 2006.257.22:23:01.29#ibcon#read 3, iclass 18, count 2 2006.257.22:23:01.29#ibcon#about to read 4, iclass 18, count 2 2006.257.22:23:01.29#ibcon#read 4, iclass 18, count 2 2006.257.22:23:01.29#ibcon#about to read 5, iclass 18, count 2 2006.257.22:23:01.29#ibcon#read 5, iclass 18, count 2 2006.257.22:23:01.29#ibcon#about to read 6, iclass 18, count 2 2006.257.22:23:01.29#ibcon#read 6, iclass 18, count 2 2006.257.22:23:01.29#ibcon#end of sib2, iclass 18, count 2 2006.257.22:23:01.29#ibcon#*after write, iclass 18, count 2 2006.257.22:23:01.29#ibcon#*before return 0, iclass 18, count 2 2006.257.22:23:01.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:01.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:01.29#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.22:23:01.29#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:01.29#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:01.41#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:01.41#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:01.41#ibcon#enter wrdev, iclass 18, count 0 2006.257.22:23:01.41#ibcon#first serial, iclass 18, count 0 2006.257.22:23:01.41#ibcon#enter sib2, iclass 18, count 0 2006.257.22:23:01.41#ibcon#flushed, iclass 18, count 0 2006.257.22:23:01.41#ibcon#about to write, iclass 18, count 0 2006.257.22:23:01.41#ibcon#wrote, iclass 18, count 0 2006.257.22:23:01.41#ibcon#about to read 3, iclass 18, count 0 2006.257.22:23:01.43#ibcon#read 3, iclass 18, count 0 2006.257.22:23:01.43#ibcon#about to read 4, iclass 18, count 0 2006.257.22:23:01.43#ibcon#read 4, iclass 18, count 0 2006.257.22:23:01.43#ibcon#about to read 5, iclass 18, count 0 2006.257.22:23:01.43#ibcon#read 5, iclass 18, count 0 2006.257.22:23:01.43#ibcon#about to read 6, iclass 18, count 0 2006.257.22:23:01.43#ibcon#read 6, iclass 18, count 0 2006.257.22:23:01.43#ibcon#end of sib2, iclass 18, count 0 2006.257.22:23:01.43#ibcon#*mode == 0, iclass 18, count 0 2006.257.22:23:01.43#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.22:23:01.43#ibcon#[25=USB\r\n] 2006.257.22:23:01.43#ibcon#*before write, iclass 18, count 0 2006.257.22:23:01.43#ibcon#enter sib2, iclass 18, count 0 2006.257.22:23:01.43#ibcon#flushed, iclass 18, count 0 2006.257.22:23:01.43#ibcon#about to write, iclass 18, count 0 2006.257.22:23:01.43#ibcon#wrote, iclass 18, count 0 2006.257.22:23:01.43#ibcon#about to read 3, iclass 18, count 0 2006.257.22:23:01.46#ibcon#read 3, iclass 18, count 0 2006.257.22:23:01.46#ibcon#about to read 4, iclass 18, count 0 2006.257.22:23:01.46#ibcon#read 4, iclass 18, count 0 2006.257.22:23:01.46#ibcon#about to read 5, iclass 18, count 0 2006.257.22:23:01.46#ibcon#read 5, iclass 18, count 0 2006.257.22:23:01.46#ibcon#about to read 6, iclass 18, count 0 2006.257.22:23:01.46#ibcon#read 6, iclass 18, count 0 2006.257.22:23:01.46#ibcon#end of sib2, iclass 18, count 0 2006.257.22:23:01.46#ibcon#*after write, iclass 18, count 0 2006.257.22:23:01.46#ibcon#*before return 0, iclass 18, count 0 2006.257.22:23:01.46#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:01.46#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:01.46#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.22:23:01.46#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.22:23:01.46$vck44/valo=7,864.99 2006.257.22:23:01.46#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.22:23:01.46#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.22:23:01.46#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:01.46#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:01.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:01.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:01.46#ibcon#enter wrdev, iclass 20, count 0 2006.257.22:23:01.46#ibcon#first serial, iclass 20, count 0 2006.257.22:23:01.46#ibcon#enter sib2, iclass 20, count 0 2006.257.22:23:01.46#ibcon#flushed, iclass 20, count 0 2006.257.22:23:01.46#ibcon#about to write, iclass 20, count 0 2006.257.22:23:01.46#ibcon#wrote, iclass 20, count 0 2006.257.22:23:01.46#ibcon#about to read 3, iclass 20, count 0 2006.257.22:23:01.48#ibcon#read 3, iclass 20, count 0 2006.257.22:23:01.48#ibcon#about to read 4, iclass 20, count 0 2006.257.22:23:01.48#ibcon#read 4, iclass 20, count 0 2006.257.22:23:01.48#ibcon#about to read 5, iclass 20, count 0 2006.257.22:23:01.48#ibcon#read 5, iclass 20, count 0 2006.257.22:23:01.48#ibcon#about to read 6, iclass 20, count 0 2006.257.22:23:01.48#ibcon#read 6, iclass 20, count 0 2006.257.22:23:01.48#ibcon#end of sib2, iclass 20, count 0 2006.257.22:23:01.48#ibcon#*mode == 0, iclass 20, count 0 2006.257.22:23:01.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.22:23:01.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.22:23:01.48#ibcon#*before write, iclass 20, count 0 2006.257.22:23:01.48#ibcon#enter sib2, iclass 20, count 0 2006.257.22:23:01.48#ibcon#flushed, iclass 20, count 0 2006.257.22:23:01.48#ibcon#about to write, iclass 20, count 0 2006.257.22:23:01.48#ibcon#wrote, iclass 20, count 0 2006.257.22:23:01.48#ibcon#about to read 3, iclass 20, count 0 2006.257.22:23:01.52#ibcon#read 3, iclass 20, count 0 2006.257.22:23:01.52#ibcon#about to read 4, iclass 20, count 0 2006.257.22:23:01.52#ibcon#read 4, iclass 20, count 0 2006.257.22:23:01.52#ibcon#about to read 5, iclass 20, count 0 2006.257.22:23:01.52#ibcon#read 5, iclass 20, count 0 2006.257.22:23:01.52#ibcon#about to read 6, iclass 20, count 0 2006.257.22:23:01.52#ibcon#read 6, iclass 20, count 0 2006.257.22:23:01.52#ibcon#end of sib2, iclass 20, count 0 2006.257.22:23:01.52#ibcon#*after write, iclass 20, count 0 2006.257.22:23:01.52#ibcon#*before return 0, iclass 20, count 0 2006.257.22:23:01.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:01.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:01.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.22:23:01.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.22:23:01.52$vck44/va=7,4 2006.257.22:23:01.52#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.22:23:01.52#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.22:23:01.52#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:01.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:01.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:01.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:01.58#ibcon#enter wrdev, iclass 22, count 2 2006.257.22:23:01.58#ibcon#first serial, iclass 22, count 2 2006.257.22:23:01.58#ibcon#enter sib2, iclass 22, count 2 2006.257.22:23:01.58#ibcon#flushed, iclass 22, count 2 2006.257.22:23:01.58#ibcon#about to write, iclass 22, count 2 2006.257.22:23:01.58#ibcon#wrote, iclass 22, count 2 2006.257.22:23:01.58#ibcon#about to read 3, iclass 22, count 2 2006.257.22:23:01.60#ibcon#read 3, iclass 22, count 2 2006.257.22:23:01.60#ibcon#about to read 4, iclass 22, count 2 2006.257.22:23:01.60#ibcon#read 4, iclass 22, count 2 2006.257.22:23:01.60#ibcon#about to read 5, iclass 22, count 2 2006.257.22:23:01.60#ibcon#read 5, iclass 22, count 2 2006.257.22:23:01.60#ibcon#about to read 6, iclass 22, count 2 2006.257.22:23:01.60#ibcon#read 6, iclass 22, count 2 2006.257.22:23:01.60#ibcon#end of sib2, iclass 22, count 2 2006.257.22:23:01.60#ibcon#*mode == 0, iclass 22, count 2 2006.257.22:23:01.60#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.22:23:01.60#ibcon#[25=AT07-04\r\n] 2006.257.22:23:01.60#ibcon#*before write, iclass 22, count 2 2006.257.22:23:01.60#ibcon#enter sib2, iclass 22, count 2 2006.257.22:23:01.60#ibcon#flushed, iclass 22, count 2 2006.257.22:23:01.60#ibcon#about to write, iclass 22, count 2 2006.257.22:23:01.60#ibcon#wrote, iclass 22, count 2 2006.257.22:23:01.60#ibcon#about to read 3, iclass 22, count 2 2006.257.22:23:01.63#ibcon#read 3, iclass 22, count 2 2006.257.22:23:01.63#ibcon#about to read 4, iclass 22, count 2 2006.257.22:23:01.63#ibcon#read 4, iclass 22, count 2 2006.257.22:23:01.63#ibcon#about to read 5, iclass 22, count 2 2006.257.22:23:01.63#ibcon#read 5, iclass 22, count 2 2006.257.22:23:01.63#ibcon#about to read 6, iclass 22, count 2 2006.257.22:23:01.63#ibcon#read 6, iclass 22, count 2 2006.257.22:23:01.63#ibcon#end of sib2, iclass 22, count 2 2006.257.22:23:01.63#ibcon#*after write, iclass 22, count 2 2006.257.22:23:01.63#ibcon#*before return 0, iclass 22, count 2 2006.257.22:23:01.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:01.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:01.63#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.22:23:01.63#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:01.63#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:01.75#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:01.75#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:01.75#ibcon#enter wrdev, iclass 22, count 0 2006.257.22:23:01.75#ibcon#first serial, iclass 22, count 0 2006.257.22:23:01.75#ibcon#enter sib2, iclass 22, count 0 2006.257.22:23:01.75#ibcon#flushed, iclass 22, count 0 2006.257.22:23:01.75#ibcon#about to write, iclass 22, count 0 2006.257.22:23:01.75#ibcon#wrote, iclass 22, count 0 2006.257.22:23:01.75#ibcon#about to read 3, iclass 22, count 0 2006.257.22:23:01.77#ibcon#read 3, iclass 22, count 0 2006.257.22:23:01.77#ibcon#about to read 4, iclass 22, count 0 2006.257.22:23:01.77#ibcon#read 4, iclass 22, count 0 2006.257.22:23:01.77#ibcon#about to read 5, iclass 22, count 0 2006.257.22:23:01.77#ibcon#read 5, iclass 22, count 0 2006.257.22:23:01.77#ibcon#about to read 6, iclass 22, count 0 2006.257.22:23:01.77#ibcon#read 6, iclass 22, count 0 2006.257.22:23:01.77#ibcon#end of sib2, iclass 22, count 0 2006.257.22:23:01.77#ibcon#*mode == 0, iclass 22, count 0 2006.257.22:23:01.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.22:23:01.77#ibcon#[25=USB\r\n] 2006.257.22:23:01.77#ibcon#*before write, iclass 22, count 0 2006.257.22:23:01.77#ibcon#enter sib2, iclass 22, count 0 2006.257.22:23:01.77#ibcon#flushed, iclass 22, count 0 2006.257.22:23:01.77#ibcon#about to write, iclass 22, count 0 2006.257.22:23:01.77#ibcon#wrote, iclass 22, count 0 2006.257.22:23:01.77#ibcon#about to read 3, iclass 22, count 0 2006.257.22:23:01.80#ibcon#read 3, iclass 22, count 0 2006.257.22:23:01.80#ibcon#about to read 4, iclass 22, count 0 2006.257.22:23:01.80#ibcon#read 4, iclass 22, count 0 2006.257.22:23:01.80#ibcon#about to read 5, iclass 22, count 0 2006.257.22:23:01.80#ibcon#read 5, iclass 22, count 0 2006.257.22:23:01.80#ibcon#about to read 6, iclass 22, count 0 2006.257.22:23:01.80#ibcon#read 6, iclass 22, count 0 2006.257.22:23:01.80#ibcon#end of sib2, iclass 22, count 0 2006.257.22:23:01.80#ibcon#*after write, iclass 22, count 0 2006.257.22:23:01.80#ibcon#*before return 0, iclass 22, count 0 2006.257.22:23:01.80#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:01.80#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:01.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.22:23:01.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.22:23:01.80$vck44/valo=8,884.99 2006.257.22:23:01.80#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.22:23:01.80#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.22:23:01.80#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:01.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:01.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:01.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:01.80#ibcon#enter wrdev, iclass 24, count 0 2006.257.22:23:01.80#ibcon#first serial, iclass 24, count 0 2006.257.22:23:01.80#ibcon#enter sib2, iclass 24, count 0 2006.257.22:23:01.80#ibcon#flushed, iclass 24, count 0 2006.257.22:23:01.80#ibcon#about to write, iclass 24, count 0 2006.257.22:23:01.80#ibcon#wrote, iclass 24, count 0 2006.257.22:23:01.80#ibcon#about to read 3, iclass 24, count 0 2006.257.22:23:01.82#ibcon#read 3, iclass 24, count 0 2006.257.22:23:01.82#ibcon#about to read 4, iclass 24, count 0 2006.257.22:23:01.82#ibcon#read 4, iclass 24, count 0 2006.257.22:23:01.82#ibcon#about to read 5, iclass 24, count 0 2006.257.22:23:01.82#ibcon#read 5, iclass 24, count 0 2006.257.22:23:01.82#ibcon#about to read 6, iclass 24, count 0 2006.257.22:23:01.82#ibcon#read 6, iclass 24, count 0 2006.257.22:23:01.82#ibcon#end of sib2, iclass 24, count 0 2006.257.22:23:01.82#ibcon#*mode == 0, iclass 24, count 0 2006.257.22:23:01.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.22:23:01.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.22:23:01.82#ibcon#*before write, iclass 24, count 0 2006.257.22:23:01.82#ibcon#enter sib2, iclass 24, count 0 2006.257.22:23:01.82#ibcon#flushed, iclass 24, count 0 2006.257.22:23:01.82#ibcon#about to write, iclass 24, count 0 2006.257.22:23:01.82#ibcon#wrote, iclass 24, count 0 2006.257.22:23:01.82#ibcon#about to read 3, iclass 24, count 0 2006.257.22:23:01.86#ibcon#read 3, iclass 24, count 0 2006.257.22:23:01.86#ibcon#about to read 4, iclass 24, count 0 2006.257.22:23:01.86#ibcon#read 4, iclass 24, count 0 2006.257.22:23:01.86#ibcon#about to read 5, iclass 24, count 0 2006.257.22:23:01.86#ibcon#read 5, iclass 24, count 0 2006.257.22:23:01.86#ibcon#about to read 6, iclass 24, count 0 2006.257.22:23:01.86#ibcon#read 6, iclass 24, count 0 2006.257.22:23:01.86#ibcon#end of sib2, iclass 24, count 0 2006.257.22:23:01.86#ibcon#*after write, iclass 24, count 0 2006.257.22:23:01.86#ibcon#*before return 0, iclass 24, count 0 2006.257.22:23:01.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:01.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:01.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.22:23:01.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.22:23:01.86$vck44/va=8,4 2006.257.22:23:01.86#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.22:23:01.86#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.22:23:01.86#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:01.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:23:01.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:23:01.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:23:01.92#ibcon#enter wrdev, iclass 26, count 2 2006.257.22:23:01.92#ibcon#first serial, iclass 26, count 2 2006.257.22:23:01.92#ibcon#enter sib2, iclass 26, count 2 2006.257.22:23:01.92#ibcon#flushed, iclass 26, count 2 2006.257.22:23:01.92#ibcon#about to write, iclass 26, count 2 2006.257.22:23:01.92#ibcon#wrote, iclass 26, count 2 2006.257.22:23:01.92#ibcon#about to read 3, iclass 26, count 2 2006.257.22:23:01.94#ibcon#read 3, iclass 26, count 2 2006.257.22:23:01.94#ibcon#about to read 4, iclass 26, count 2 2006.257.22:23:01.94#ibcon#read 4, iclass 26, count 2 2006.257.22:23:01.94#ibcon#about to read 5, iclass 26, count 2 2006.257.22:23:01.94#ibcon#read 5, iclass 26, count 2 2006.257.22:23:01.94#ibcon#about to read 6, iclass 26, count 2 2006.257.22:23:01.94#ibcon#read 6, iclass 26, count 2 2006.257.22:23:01.94#ibcon#end of sib2, iclass 26, count 2 2006.257.22:23:01.94#ibcon#*mode == 0, iclass 26, count 2 2006.257.22:23:01.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.22:23:01.94#ibcon#[25=AT08-04\r\n] 2006.257.22:23:01.94#ibcon#*before write, iclass 26, count 2 2006.257.22:23:01.94#ibcon#enter sib2, iclass 26, count 2 2006.257.22:23:01.94#ibcon#flushed, iclass 26, count 2 2006.257.22:23:01.94#ibcon#about to write, iclass 26, count 2 2006.257.22:23:01.94#ibcon#wrote, iclass 26, count 2 2006.257.22:23:01.94#ibcon#about to read 3, iclass 26, count 2 2006.257.22:23:01.97#ibcon#read 3, iclass 26, count 2 2006.257.22:23:01.97#ibcon#about to read 4, iclass 26, count 2 2006.257.22:23:01.97#ibcon#read 4, iclass 26, count 2 2006.257.22:23:01.97#ibcon#about to read 5, iclass 26, count 2 2006.257.22:23:01.97#ibcon#read 5, iclass 26, count 2 2006.257.22:23:01.97#ibcon#about to read 6, iclass 26, count 2 2006.257.22:23:01.97#ibcon#read 6, iclass 26, count 2 2006.257.22:23:01.97#ibcon#end of sib2, iclass 26, count 2 2006.257.22:23:01.97#ibcon#*after write, iclass 26, count 2 2006.257.22:23:01.97#ibcon#*before return 0, iclass 26, count 2 2006.257.22:23:01.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:23:01.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:23:01.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.22:23:01.97#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:01.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:23:02.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:23:02.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:23:02.09#ibcon#enter wrdev, iclass 26, count 0 2006.257.22:23:02.09#ibcon#first serial, iclass 26, count 0 2006.257.22:23:02.09#ibcon#enter sib2, iclass 26, count 0 2006.257.22:23:02.09#ibcon#flushed, iclass 26, count 0 2006.257.22:23:02.09#ibcon#about to write, iclass 26, count 0 2006.257.22:23:02.09#ibcon#wrote, iclass 26, count 0 2006.257.22:23:02.09#ibcon#about to read 3, iclass 26, count 0 2006.257.22:23:02.11#ibcon#read 3, iclass 26, count 0 2006.257.22:23:02.11#ibcon#about to read 4, iclass 26, count 0 2006.257.22:23:02.11#ibcon#read 4, iclass 26, count 0 2006.257.22:23:02.11#ibcon#about to read 5, iclass 26, count 0 2006.257.22:23:02.11#ibcon#read 5, iclass 26, count 0 2006.257.22:23:02.11#ibcon#about to read 6, iclass 26, count 0 2006.257.22:23:02.11#ibcon#read 6, iclass 26, count 0 2006.257.22:23:02.11#ibcon#end of sib2, iclass 26, count 0 2006.257.22:23:02.11#ibcon#*mode == 0, iclass 26, count 0 2006.257.22:23:02.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.22:23:02.11#ibcon#[25=USB\r\n] 2006.257.22:23:02.11#ibcon#*before write, iclass 26, count 0 2006.257.22:23:02.11#ibcon#enter sib2, iclass 26, count 0 2006.257.22:23:02.11#ibcon#flushed, iclass 26, count 0 2006.257.22:23:02.11#ibcon#about to write, iclass 26, count 0 2006.257.22:23:02.11#ibcon#wrote, iclass 26, count 0 2006.257.22:23:02.11#ibcon#about to read 3, iclass 26, count 0 2006.257.22:23:02.14#ibcon#read 3, iclass 26, count 0 2006.257.22:23:02.14#ibcon#about to read 4, iclass 26, count 0 2006.257.22:23:02.14#ibcon#read 4, iclass 26, count 0 2006.257.22:23:02.14#ibcon#about to read 5, iclass 26, count 0 2006.257.22:23:02.14#ibcon#read 5, iclass 26, count 0 2006.257.22:23:02.14#ibcon#about to read 6, iclass 26, count 0 2006.257.22:23:02.14#ibcon#read 6, iclass 26, count 0 2006.257.22:23:02.14#ibcon#end of sib2, iclass 26, count 0 2006.257.22:23:02.14#ibcon#*after write, iclass 26, count 0 2006.257.22:23:02.14#ibcon#*before return 0, iclass 26, count 0 2006.257.22:23:02.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:23:02.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:23:02.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.22:23:02.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.22:23:02.14$vck44/vblo=1,629.99 2006.257.22:23:02.14#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.22:23:02.14#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.22:23:02.14#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:02.14#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:23:02.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:23:02.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:23:02.14#ibcon#enter wrdev, iclass 28, count 0 2006.257.22:23:02.14#ibcon#first serial, iclass 28, count 0 2006.257.22:23:02.14#ibcon#enter sib2, iclass 28, count 0 2006.257.22:23:02.14#ibcon#flushed, iclass 28, count 0 2006.257.22:23:02.14#ibcon#about to write, iclass 28, count 0 2006.257.22:23:02.14#ibcon#wrote, iclass 28, count 0 2006.257.22:23:02.14#ibcon#about to read 3, iclass 28, count 0 2006.257.22:23:02.16#ibcon#read 3, iclass 28, count 0 2006.257.22:23:02.16#ibcon#about to read 4, iclass 28, count 0 2006.257.22:23:02.16#ibcon#read 4, iclass 28, count 0 2006.257.22:23:02.16#ibcon#about to read 5, iclass 28, count 0 2006.257.22:23:02.16#ibcon#read 5, iclass 28, count 0 2006.257.22:23:02.16#ibcon#about to read 6, iclass 28, count 0 2006.257.22:23:02.16#ibcon#read 6, iclass 28, count 0 2006.257.22:23:02.16#ibcon#end of sib2, iclass 28, count 0 2006.257.22:23:02.16#ibcon#*mode == 0, iclass 28, count 0 2006.257.22:23:02.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.22:23:02.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.22:23:02.16#ibcon#*before write, iclass 28, count 0 2006.257.22:23:02.16#ibcon#enter sib2, iclass 28, count 0 2006.257.22:23:02.16#ibcon#flushed, iclass 28, count 0 2006.257.22:23:02.16#ibcon#about to write, iclass 28, count 0 2006.257.22:23:02.16#ibcon#wrote, iclass 28, count 0 2006.257.22:23:02.16#ibcon#about to read 3, iclass 28, count 0 2006.257.22:23:02.20#ibcon#read 3, iclass 28, count 0 2006.257.22:23:02.20#ibcon#about to read 4, iclass 28, count 0 2006.257.22:23:02.20#ibcon#read 4, iclass 28, count 0 2006.257.22:23:02.20#ibcon#about to read 5, iclass 28, count 0 2006.257.22:23:02.20#ibcon#read 5, iclass 28, count 0 2006.257.22:23:02.20#ibcon#about to read 6, iclass 28, count 0 2006.257.22:23:02.20#ibcon#read 6, iclass 28, count 0 2006.257.22:23:02.20#ibcon#end of sib2, iclass 28, count 0 2006.257.22:23:02.20#ibcon#*after write, iclass 28, count 0 2006.257.22:23:02.20#ibcon#*before return 0, iclass 28, count 0 2006.257.22:23:02.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:23:02.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.22:23:02.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.22:23:02.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.22:23:02.20$vck44/vb=1,4 2006.257.22:23:02.20#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.22:23:02.20#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.22:23:02.20#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:02.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:23:02.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:23:02.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:23:02.20#ibcon#enter wrdev, iclass 30, count 2 2006.257.22:23:02.20#ibcon#first serial, iclass 30, count 2 2006.257.22:23:02.20#ibcon#enter sib2, iclass 30, count 2 2006.257.22:23:02.20#ibcon#flushed, iclass 30, count 2 2006.257.22:23:02.20#ibcon#about to write, iclass 30, count 2 2006.257.22:23:02.20#ibcon#wrote, iclass 30, count 2 2006.257.22:23:02.20#ibcon#about to read 3, iclass 30, count 2 2006.257.22:23:02.22#ibcon#read 3, iclass 30, count 2 2006.257.22:23:02.22#ibcon#about to read 4, iclass 30, count 2 2006.257.22:23:02.22#ibcon#read 4, iclass 30, count 2 2006.257.22:23:02.22#ibcon#about to read 5, iclass 30, count 2 2006.257.22:23:02.22#ibcon#read 5, iclass 30, count 2 2006.257.22:23:02.22#ibcon#about to read 6, iclass 30, count 2 2006.257.22:23:02.22#ibcon#read 6, iclass 30, count 2 2006.257.22:23:02.22#ibcon#end of sib2, iclass 30, count 2 2006.257.22:23:02.22#ibcon#*mode == 0, iclass 30, count 2 2006.257.22:23:02.22#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.22:23:02.22#ibcon#[27=AT01-04\r\n] 2006.257.22:23:02.22#ibcon#*before write, iclass 30, count 2 2006.257.22:23:02.22#ibcon#enter sib2, iclass 30, count 2 2006.257.22:23:02.22#ibcon#flushed, iclass 30, count 2 2006.257.22:23:02.22#ibcon#about to write, iclass 30, count 2 2006.257.22:23:02.22#ibcon#wrote, iclass 30, count 2 2006.257.22:23:02.22#ibcon#about to read 3, iclass 30, count 2 2006.257.22:23:02.25#ibcon#read 3, iclass 30, count 2 2006.257.22:23:02.25#ibcon#about to read 4, iclass 30, count 2 2006.257.22:23:02.25#ibcon#read 4, iclass 30, count 2 2006.257.22:23:02.25#ibcon#about to read 5, iclass 30, count 2 2006.257.22:23:02.25#ibcon#read 5, iclass 30, count 2 2006.257.22:23:02.25#ibcon#about to read 6, iclass 30, count 2 2006.257.22:23:02.25#ibcon#read 6, iclass 30, count 2 2006.257.22:23:02.25#ibcon#end of sib2, iclass 30, count 2 2006.257.22:23:02.25#ibcon#*after write, iclass 30, count 2 2006.257.22:23:02.25#ibcon#*before return 0, iclass 30, count 2 2006.257.22:23:02.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:23:02.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.22:23:02.25#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.22:23:02.25#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:02.25#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:23:02.37#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:23:02.37#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:23:02.37#ibcon#enter wrdev, iclass 30, count 0 2006.257.22:23:02.37#ibcon#first serial, iclass 30, count 0 2006.257.22:23:02.37#ibcon#enter sib2, iclass 30, count 0 2006.257.22:23:02.37#ibcon#flushed, iclass 30, count 0 2006.257.22:23:02.37#ibcon#about to write, iclass 30, count 0 2006.257.22:23:02.37#ibcon#wrote, iclass 30, count 0 2006.257.22:23:02.37#ibcon#about to read 3, iclass 30, count 0 2006.257.22:23:02.39#ibcon#read 3, iclass 30, count 0 2006.257.22:23:02.39#ibcon#about to read 4, iclass 30, count 0 2006.257.22:23:02.39#ibcon#read 4, iclass 30, count 0 2006.257.22:23:02.39#ibcon#about to read 5, iclass 30, count 0 2006.257.22:23:02.39#ibcon#read 5, iclass 30, count 0 2006.257.22:23:02.39#ibcon#about to read 6, iclass 30, count 0 2006.257.22:23:02.39#ibcon#read 6, iclass 30, count 0 2006.257.22:23:02.39#ibcon#end of sib2, iclass 30, count 0 2006.257.22:23:02.39#ibcon#*mode == 0, iclass 30, count 0 2006.257.22:23:02.39#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.22:23:02.39#ibcon#[27=USB\r\n] 2006.257.22:23:02.39#ibcon#*before write, iclass 30, count 0 2006.257.22:23:02.39#ibcon#enter sib2, iclass 30, count 0 2006.257.22:23:02.39#ibcon#flushed, iclass 30, count 0 2006.257.22:23:02.39#ibcon#about to write, iclass 30, count 0 2006.257.22:23:02.39#ibcon#wrote, iclass 30, count 0 2006.257.22:23:02.39#ibcon#about to read 3, iclass 30, count 0 2006.257.22:23:02.42#ibcon#read 3, iclass 30, count 0 2006.257.22:23:02.42#ibcon#about to read 4, iclass 30, count 0 2006.257.22:23:02.42#ibcon#read 4, iclass 30, count 0 2006.257.22:23:02.42#ibcon#about to read 5, iclass 30, count 0 2006.257.22:23:02.42#ibcon#read 5, iclass 30, count 0 2006.257.22:23:02.42#ibcon#about to read 6, iclass 30, count 0 2006.257.22:23:02.42#ibcon#read 6, iclass 30, count 0 2006.257.22:23:02.42#ibcon#end of sib2, iclass 30, count 0 2006.257.22:23:02.42#ibcon#*after write, iclass 30, count 0 2006.257.22:23:02.42#ibcon#*before return 0, iclass 30, count 0 2006.257.22:23:02.42#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:23:02.42#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.22:23:02.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.22:23:02.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.22:23:02.42$vck44/vblo=2,634.99 2006.257.22:23:02.42#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.22:23:02.42#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.22:23:02.42#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:02.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:23:02.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:23:02.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:23:02.42#ibcon#enter wrdev, iclass 32, count 0 2006.257.22:23:02.42#ibcon#first serial, iclass 32, count 0 2006.257.22:23:02.42#ibcon#enter sib2, iclass 32, count 0 2006.257.22:23:02.42#ibcon#flushed, iclass 32, count 0 2006.257.22:23:02.42#ibcon#about to write, iclass 32, count 0 2006.257.22:23:02.42#ibcon#wrote, iclass 32, count 0 2006.257.22:23:02.42#ibcon#about to read 3, iclass 32, count 0 2006.257.22:23:02.44#ibcon#read 3, iclass 32, count 0 2006.257.22:23:02.44#ibcon#about to read 4, iclass 32, count 0 2006.257.22:23:02.44#ibcon#read 4, iclass 32, count 0 2006.257.22:23:02.44#ibcon#about to read 5, iclass 32, count 0 2006.257.22:23:02.44#ibcon#read 5, iclass 32, count 0 2006.257.22:23:02.44#ibcon#about to read 6, iclass 32, count 0 2006.257.22:23:02.44#ibcon#read 6, iclass 32, count 0 2006.257.22:23:02.44#ibcon#end of sib2, iclass 32, count 0 2006.257.22:23:02.44#ibcon#*mode == 0, iclass 32, count 0 2006.257.22:23:02.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.22:23:02.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.22:23:02.44#ibcon#*before write, iclass 32, count 0 2006.257.22:23:02.44#ibcon#enter sib2, iclass 32, count 0 2006.257.22:23:02.44#ibcon#flushed, iclass 32, count 0 2006.257.22:23:02.44#ibcon#about to write, iclass 32, count 0 2006.257.22:23:02.44#ibcon#wrote, iclass 32, count 0 2006.257.22:23:02.44#ibcon#about to read 3, iclass 32, count 0 2006.257.22:23:02.48#ibcon#read 3, iclass 32, count 0 2006.257.22:23:02.48#ibcon#about to read 4, iclass 32, count 0 2006.257.22:23:02.48#ibcon#read 4, iclass 32, count 0 2006.257.22:23:02.48#ibcon#about to read 5, iclass 32, count 0 2006.257.22:23:02.48#ibcon#read 5, iclass 32, count 0 2006.257.22:23:02.48#ibcon#about to read 6, iclass 32, count 0 2006.257.22:23:02.48#ibcon#read 6, iclass 32, count 0 2006.257.22:23:02.48#ibcon#end of sib2, iclass 32, count 0 2006.257.22:23:02.48#ibcon#*after write, iclass 32, count 0 2006.257.22:23:02.48#ibcon#*before return 0, iclass 32, count 0 2006.257.22:23:02.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:23:02.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.22:23:02.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.22:23:02.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.22:23:02.48$vck44/vb=2,5 2006.257.22:23:02.48#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.22:23:02.48#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.22:23:02.48#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:02.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:23:02.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:23:02.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:23:02.54#ibcon#enter wrdev, iclass 34, count 2 2006.257.22:23:02.54#ibcon#first serial, iclass 34, count 2 2006.257.22:23:02.54#ibcon#enter sib2, iclass 34, count 2 2006.257.22:23:02.54#ibcon#flushed, iclass 34, count 2 2006.257.22:23:02.54#ibcon#about to write, iclass 34, count 2 2006.257.22:23:02.54#ibcon#wrote, iclass 34, count 2 2006.257.22:23:02.54#ibcon#about to read 3, iclass 34, count 2 2006.257.22:23:02.56#ibcon#read 3, iclass 34, count 2 2006.257.22:23:02.56#ibcon#about to read 4, iclass 34, count 2 2006.257.22:23:02.56#ibcon#read 4, iclass 34, count 2 2006.257.22:23:02.56#ibcon#about to read 5, iclass 34, count 2 2006.257.22:23:02.56#ibcon#read 5, iclass 34, count 2 2006.257.22:23:02.56#ibcon#about to read 6, iclass 34, count 2 2006.257.22:23:02.56#ibcon#read 6, iclass 34, count 2 2006.257.22:23:02.56#ibcon#end of sib2, iclass 34, count 2 2006.257.22:23:02.56#ibcon#*mode == 0, iclass 34, count 2 2006.257.22:23:02.56#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.22:23:02.56#ibcon#[27=AT02-05\r\n] 2006.257.22:23:02.56#ibcon#*before write, iclass 34, count 2 2006.257.22:23:02.56#ibcon#enter sib2, iclass 34, count 2 2006.257.22:23:02.56#ibcon#flushed, iclass 34, count 2 2006.257.22:23:02.56#ibcon#about to write, iclass 34, count 2 2006.257.22:23:02.56#ibcon#wrote, iclass 34, count 2 2006.257.22:23:02.56#ibcon#about to read 3, iclass 34, count 2 2006.257.22:23:02.59#ibcon#read 3, iclass 34, count 2 2006.257.22:23:02.59#ibcon#about to read 4, iclass 34, count 2 2006.257.22:23:02.59#ibcon#read 4, iclass 34, count 2 2006.257.22:23:02.59#ibcon#about to read 5, iclass 34, count 2 2006.257.22:23:02.59#ibcon#read 5, iclass 34, count 2 2006.257.22:23:02.59#ibcon#about to read 6, iclass 34, count 2 2006.257.22:23:02.59#ibcon#read 6, iclass 34, count 2 2006.257.22:23:02.59#ibcon#end of sib2, iclass 34, count 2 2006.257.22:23:02.59#ibcon#*after write, iclass 34, count 2 2006.257.22:23:02.59#ibcon#*before return 0, iclass 34, count 2 2006.257.22:23:02.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:23:02.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.22:23:02.59#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.22:23:02.59#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:02.59#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:23:02.71#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:23:02.71#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:23:02.71#ibcon#enter wrdev, iclass 34, count 0 2006.257.22:23:02.71#ibcon#first serial, iclass 34, count 0 2006.257.22:23:02.71#ibcon#enter sib2, iclass 34, count 0 2006.257.22:23:02.71#ibcon#flushed, iclass 34, count 0 2006.257.22:23:02.71#ibcon#about to write, iclass 34, count 0 2006.257.22:23:02.71#ibcon#wrote, iclass 34, count 0 2006.257.22:23:02.71#ibcon#about to read 3, iclass 34, count 0 2006.257.22:23:02.73#ibcon#read 3, iclass 34, count 0 2006.257.22:23:02.73#ibcon#about to read 4, iclass 34, count 0 2006.257.22:23:02.73#ibcon#read 4, iclass 34, count 0 2006.257.22:23:02.73#ibcon#about to read 5, iclass 34, count 0 2006.257.22:23:02.73#ibcon#read 5, iclass 34, count 0 2006.257.22:23:02.73#ibcon#about to read 6, iclass 34, count 0 2006.257.22:23:02.73#ibcon#read 6, iclass 34, count 0 2006.257.22:23:02.73#ibcon#end of sib2, iclass 34, count 0 2006.257.22:23:02.73#ibcon#*mode == 0, iclass 34, count 0 2006.257.22:23:02.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.22:23:02.73#ibcon#[27=USB\r\n] 2006.257.22:23:02.73#ibcon#*before write, iclass 34, count 0 2006.257.22:23:02.73#ibcon#enter sib2, iclass 34, count 0 2006.257.22:23:02.73#ibcon#flushed, iclass 34, count 0 2006.257.22:23:02.73#ibcon#about to write, iclass 34, count 0 2006.257.22:23:02.73#ibcon#wrote, iclass 34, count 0 2006.257.22:23:02.73#ibcon#about to read 3, iclass 34, count 0 2006.257.22:23:02.76#ibcon#read 3, iclass 34, count 0 2006.257.22:23:02.76#ibcon#about to read 4, iclass 34, count 0 2006.257.22:23:02.76#ibcon#read 4, iclass 34, count 0 2006.257.22:23:02.76#ibcon#about to read 5, iclass 34, count 0 2006.257.22:23:02.76#ibcon#read 5, iclass 34, count 0 2006.257.22:23:02.76#ibcon#about to read 6, iclass 34, count 0 2006.257.22:23:02.76#ibcon#read 6, iclass 34, count 0 2006.257.22:23:02.76#ibcon#end of sib2, iclass 34, count 0 2006.257.22:23:02.76#ibcon#*after write, iclass 34, count 0 2006.257.22:23:02.76#ibcon#*before return 0, iclass 34, count 0 2006.257.22:23:02.76#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:23:02.76#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.22:23:02.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.22:23:02.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.22:23:02.76$vck44/vblo=3,649.99 2006.257.22:23:02.76#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.22:23:02.76#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.22:23:02.76#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:02.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:23:02.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:23:02.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:23:02.76#ibcon#enter wrdev, iclass 36, count 0 2006.257.22:23:02.76#ibcon#first serial, iclass 36, count 0 2006.257.22:23:02.76#ibcon#enter sib2, iclass 36, count 0 2006.257.22:23:02.76#ibcon#flushed, iclass 36, count 0 2006.257.22:23:02.76#ibcon#about to write, iclass 36, count 0 2006.257.22:23:02.76#ibcon#wrote, iclass 36, count 0 2006.257.22:23:02.76#ibcon#about to read 3, iclass 36, count 0 2006.257.22:23:02.78#ibcon#read 3, iclass 36, count 0 2006.257.22:23:02.78#ibcon#about to read 4, iclass 36, count 0 2006.257.22:23:02.78#ibcon#read 4, iclass 36, count 0 2006.257.22:23:02.78#ibcon#about to read 5, iclass 36, count 0 2006.257.22:23:02.78#ibcon#read 5, iclass 36, count 0 2006.257.22:23:02.78#ibcon#about to read 6, iclass 36, count 0 2006.257.22:23:02.78#ibcon#read 6, iclass 36, count 0 2006.257.22:23:02.78#ibcon#end of sib2, iclass 36, count 0 2006.257.22:23:02.78#ibcon#*mode == 0, iclass 36, count 0 2006.257.22:23:02.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.22:23:02.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.22:23:02.78#ibcon#*before write, iclass 36, count 0 2006.257.22:23:02.78#ibcon#enter sib2, iclass 36, count 0 2006.257.22:23:02.78#ibcon#flushed, iclass 36, count 0 2006.257.22:23:02.78#ibcon#about to write, iclass 36, count 0 2006.257.22:23:02.78#ibcon#wrote, iclass 36, count 0 2006.257.22:23:02.78#ibcon#about to read 3, iclass 36, count 0 2006.257.22:23:02.82#ibcon#read 3, iclass 36, count 0 2006.257.22:23:02.82#ibcon#about to read 4, iclass 36, count 0 2006.257.22:23:02.82#ibcon#read 4, iclass 36, count 0 2006.257.22:23:02.82#ibcon#about to read 5, iclass 36, count 0 2006.257.22:23:02.82#ibcon#read 5, iclass 36, count 0 2006.257.22:23:02.82#ibcon#about to read 6, iclass 36, count 0 2006.257.22:23:02.82#ibcon#read 6, iclass 36, count 0 2006.257.22:23:02.82#ibcon#end of sib2, iclass 36, count 0 2006.257.22:23:02.82#ibcon#*after write, iclass 36, count 0 2006.257.22:23:02.82#ibcon#*before return 0, iclass 36, count 0 2006.257.22:23:02.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:23:02.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.22:23:02.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.22:23:02.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.22:23:02.82$vck44/vb=3,4 2006.257.22:23:02.82#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.22:23:02.82#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.22:23:02.82#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:02.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:23:02.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:23:02.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:23:02.88#ibcon#enter wrdev, iclass 38, count 2 2006.257.22:23:02.88#ibcon#first serial, iclass 38, count 2 2006.257.22:23:02.88#ibcon#enter sib2, iclass 38, count 2 2006.257.22:23:02.88#ibcon#flushed, iclass 38, count 2 2006.257.22:23:02.88#ibcon#about to write, iclass 38, count 2 2006.257.22:23:02.88#ibcon#wrote, iclass 38, count 2 2006.257.22:23:02.88#ibcon#about to read 3, iclass 38, count 2 2006.257.22:23:02.90#ibcon#read 3, iclass 38, count 2 2006.257.22:23:02.90#ibcon#about to read 4, iclass 38, count 2 2006.257.22:23:02.90#ibcon#read 4, iclass 38, count 2 2006.257.22:23:02.90#ibcon#about to read 5, iclass 38, count 2 2006.257.22:23:02.90#ibcon#read 5, iclass 38, count 2 2006.257.22:23:02.90#ibcon#about to read 6, iclass 38, count 2 2006.257.22:23:02.90#ibcon#read 6, iclass 38, count 2 2006.257.22:23:02.90#ibcon#end of sib2, iclass 38, count 2 2006.257.22:23:02.90#ibcon#*mode == 0, iclass 38, count 2 2006.257.22:23:02.90#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.22:23:02.90#ibcon#[27=AT03-04\r\n] 2006.257.22:23:02.90#ibcon#*before write, iclass 38, count 2 2006.257.22:23:02.90#ibcon#enter sib2, iclass 38, count 2 2006.257.22:23:02.90#ibcon#flushed, iclass 38, count 2 2006.257.22:23:02.90#ibcon#about to write, iclass 38, count 2 2006.257.22:23:02.90#ibcon#wrote, iclass 38, count 2 2006.257.22:23:02.90#ibcon#about to read 3, iclass 38, count 2 2006.257.22:23:02.93#ibcon#read 3, iclass 38, count 2 2006.257.22:23:02.93#ibcon#about to read 4, iclass 38, count 2 2006.257.22:23:02.93#ibcon#read 4, iclass 38, count 2 2006.257.22:23:02.93#ibcon#about to read 5, iclass 38, count 2 2006.257.22:23:02.93#ibcon#read 5, iclass 38, count 2 2006.257.22:23:02.93#ibcon#about to read 6, iclass 38, count 2 2006.257.22:23:02.93#ibcon#read 6, iclass 38, count 2 2006.257.22:23:02.93#ibcon#end of sib2, iclass 38, count 2 2006.257.22:23:02.93#ibcon#*after write, iclass 38, count 2 2006.257.22:23:02.93#ibcon#*before return 0, iclass 38, count 2 2006.257.22:23:02.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:23:02.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.22:23:02.93#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.22:23:02.93#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:02.93#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:03.05#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:03.05#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:03.05#ibcon#enter wrdev, iclass 38, count 0 2006.257.22:23:03.05#ibcon#first serial, iclass 38, count 0 2006.257.22:23:03.05#ibcon#enter sib2, iclass 38, count 0 2006.257.22:23:03.05#ibcon#flushed, iclass 38, count 0 2006.257.22:23:03.05#ibcon#about to write, iclass 38, count 0 2006.257.22:23:03.05#ibcon#wrote, iclass 38, count 0 2006.257.22:23:03.05#ibcon#about to read 3, iclass 38, count 0 2006.257.22:23:03.07#ibcon#read 3, iclass 38, count 0 2006.257.22:23:03.07#ibcon#about to read 4, iclass 38, count 0 2006.257.22:23:03.07#ibcon#read 4, iclass 38, count 0 2006.257.22:23:03.07#ibcon#about to read 5, iclass 38, count 0 2006.257.22:23:03.07#ibcon#read 5, iclass 38, count 0 2006.257.22:23:03.07#ibcon#about to read 6, iclass 38, count 0 2006.257.22:23:03.07#ibcon#read 6, iclass 38, count 0 2006.257.22:23:03.07#ibcon#end of sib2, iclass 38, count 0 2006.257.22:23:03.07#ibcon#*mode == 0, iclass 38, count 0 2006.257.22:23:03.07#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.22:23:03.07#ibcon#[27=USB\r\n] 2006.257.22:23:03.07#ibcon#*before write, iclass 38, count 0 2006.257.22:23:03.07#ibcon#enter sib2, iclass 38, count 0 2006.257.22:23:03.07#ibcon#flushed, iclass 38, count 0 2006.257.22:23:03.07#ibcon#about to write, iclass 38, count 0 2006.257.22:23:03.07#ibcon#wrote, iclass 38, count 0 2006.257.22:23:03.07#ibcon#about to read 3, iclass 38, count 0 2006.257.22:23:03.10#ibcon#read 3, iclass 38, count 0 2006.257.22:23:03.10#ibcon#about to read 4, iclass 38, count 0 2006.257.22:23:03.10#ibcon#read 4, iclass 38, count 0 2006.257.22:23:03.10#ibcon#about to read 5, iclass 38, count 0 2006.257.22:23:03.10#ibcon#read 5, iclass 38, count 0 2006.257.22:23:03.10#ibcon#about to read 6, iclass 38, count 0 2006.257.22:23:03.10#ibcon#read 6, iclass 38, count 0 2006.257.22:23:03.10#ibcon#end of sib2, iclass 38, count 0 2006.257.22:23:03.10#ibcon#*after write, iclass 38, count 0 2006.257.22:23:03.10#ibcon#*before return 0, iclass 38, count 0 2006.257.22:23:03.10#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:03.10#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.22:23:03.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.22:23:03.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.22:23:03.10$vck44/vblo=4,679.99 2006.257.22:23:03.10#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.22:23:03.10#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.22:23:03.10#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:03.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:03.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:03.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:03.10#ibcon#enter wrdev, iclass 40, count 0 2006.257.22:23:03.10#ibcon#first serial, iclass 40, count 0 2006.257.22:23:03.10#ibcon#enter sib2, iclass 40, count 0 2006.257.22:23:03.10#ibcon#flushed, iclass 40, count 0 2006.257.22:23:03.10#ibcon#about to write, iclass 40, count 0 2006.257.22:23:03.10#ibcon#wrote, iclass 40, count 0 2006.257.22:23:03.10#ibcon#about to read 3, iclass 40, count 0 2006.257.22:23:03.12#ibcon#read 3, iclass 40, count 0 2006.257.22:23:03.12#ibcon#about to read 4, iclass 40, count 0 2006.257.22:23:03.12#ibcon#read 4, iclass 40, count 0 2006.257.22:23:03.12#ibcon#about to read 5, iclass 40, count 0 2006.257.22:23:03.12#ibcon#read 5, iclass 40, count 0 2006.257.22:23:03.12#ibcon#about to read 6, iclass 40, count 0 2006.257.22:23:03.12#ibcon#read 6, iclass 40, count 0 2006.257.22:23:03.12#ibcon#end of sib2, iclass 40, count 0 2006.257.22:23:03.12#ibcon#*mode == 0, iclass 40, count 0 2006.257.22:23:03.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.22:23:03.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.22:23:03.12#ibcon#*before write, iclass 40, count 0 2006.257.22:23:03.12#ibcon#enter sib2, iclass 40, count 0 2006.257.22:23:03.12#ibcon#flushed, iclass 40, count 0 2006.257.22:23:03.12#ibcon#about to write, iclass 40, count 0 2006.257.22:23:03.12#ibcon#wrote, iclass 40, count 0 2006.257.22:23:03.12#ibcon#about to read 3, iclass 40, count 0 2006.257.22:23:03.16#ibcon#read 3, iclass 40, count 0 2006.257.22:23:03.16#ibcon#about to read 4, iclass 40, count 0 2006.257.22:23:03.16#ibcon#read 4, iclass 40, count 0 2006.257.22:23:03.16#ibcon#about to read 5, iclass 40, count 0 2006.257.22:23:03.16#ibcon#read 5, iclass 40, count 0 2006.257.22:23:03.16#ibcon#about to read 6, iclass 40, count 0 2006.257.22:23:03.16#ibcon#read 6, iclass 40, count 0 2006.257.22:23:03.16#ibcon#end of sib2, iclass 40, count 0 2006.257.22:23:03.16#ibcon#*after write, iclass 40, count 0 2006.257.22:23:03.16#ibcon#*before return 0, iclass 40, count 0 2006.257.22:23:03.16#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:03.16#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.22:23:03.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.22:23:03.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.22:23:03.16$vck44/vb=4,5 2006.257.22:23:03.16#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.22:23:03.16#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.22:23:03.16#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:03.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:03.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:03.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:03.22#ibcon#enter wrdev, iclass 4, count 2 2006.257.22:23:03.22#ibcon#first serial, iclass 4, count 2 2006.257.22:23:03.22#ibcon#enter sib2, iclass 4, count 2 2006.257.22:23:03.22#ibcon#flushed, iclass 4, count 2 2006.257.22:23:03.22#ibcon#about to write, iclass 4, count 2 2006.257.22:23:03.22#ibcon#wrote, iclass 4, count 2 2006.257.22:23:03.22#ibcon#about to read 3, iclass 4, count 2 2006.257.22:23:03.24#ibcon#read 3, iclass 4, count 2 2006.257.22:23:03.24#ibcon#about to read 4, iclass 4, count 2 2006.257.22:23:03.24#ibcon#read 4, iclass 4, count 2 2006.257.22:23:03.24#ibcon#about to read 5, iclass 4, count 2 2006.257.22:23:03.24#ibcon#read 5, iclass 4, count 2 2006.257.22:23:03.24#ibcon#about to read 6, iclass 4, count 2 2006.257.22:23:03.24#ibcon#read 6, iclass 4, count 2 2006.257.22:23:03.24#ibcon#end of sib2, iclass 4, count 2 2006.257.22:23:03.24#ibcon#*mode == 0, iclass 4, count 2 2006.257.22:23:03.24#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.22:23:03.24#ibcon#[27=AT04-05\r\n] 2006.257.22:23:03.24#ibcon#*before write, iclass 4, count 2 2006.257.22:23:03.24#ibcon#enter sib2, iclass 4, count 2 2006.257.22:23:03.24#ibcon#flushed, iclass 4, count 2 2006.257.22:23:03.24#ibcon#about to write, iclass 4, count 2 2006.257.22:23:03.24#ibcon#wrote, iclass 4, count 2 2006.257.22:23:03.24#ibcon#about to read 3, iclass 4, count 2 2006.257.22:23:03.27#ibcon#read 3, iclass 4, count 2 2006.257.22:23:03.27#ibcon#about to read 4, iclass 4, count 2 2006.257.22:23:03.27#ibcon#read 4, iclass 4, count 2 2006.257.22:23:03.27#ibcon#about to read 5, iclass 4, count 2 2006.257.22:23:03.27#ibcon#read 5, iclass 4, count 2 2006.257.22:23:03.27#ibcon#about to read 6, iclass 4, count 2 2006.257.22:23:03.27#ibcon#read 6, iclass 4, count 2 2006.257.22:23:03.27#ibcon#end of sib2, iclass 4, count 2 2006.257.22:23:03.27#ibcon#*after write, iclass 4, count 2 2006.257.22:23:03.27#ibcon#*before return 0, iclass 4, count 2 2006.257.22:23:03.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:03.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.22:23:03.27#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.22:23:03.27#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:03.27#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:03.39#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:03.39#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:03.39#ibcon#enter wrdev, iclass 4, count 0 2006.257.22:23:03.39#ibcon#first serial, iclass 4, count 0 2006.257.22:23:03.39#ibcon#enter sib2, iclass 4, count 0 2006.257.22:23:03.39#ibcon#flushed, iclass 4, count 0 2006.257.22:23:03.39#ibcon#about to write, iclass 4, count 0 2006.257.22:23:03.39#ibcon#wrote, iclass 4, count 0 2006.257.22:23:03.39#ibcon#about to read 3, iclass 4, count 0 2006.257.22:23:03.41#ibcon#read 3, iclass 4, count 0 2006.257.22:23:03.41#ibcon#about to read 4, iclass 4, count 0 2006.257.22:23:03.41#ibcon#read 4, iclass 4, count 0 2006.257.22:23:03.41#ibcon#about to read 5, iclass 4, count 0 2006.257.22:23:03.41#ibcon#read 5, iclass 4, count 0 2006.257.22:23:03.41#ibcon#about to read 6, iclass 4, count 0 2006.257.22:23:03.41#ibcon#read 6, iclass 4, count 0 2006.257.22:23:03.41#ibcon#end of sib2, iclass 4, count 0 2006.257.22:23:03.41#ibcon#*mode == 0, iclass 4, count 0 2006.257.22:23:03.41#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.22:23:03.41#ibcon#[27=USB\r\n] 2006.257.22:23:03.41#ibcon#*before write, iclass 4, count 0 2006.257.22:23:03.41#ibcon#enter sib2, iclass 4, count 0 2006.257.22:23:03.41#ibcon#flushed, iclass 4, count 0 2006.257.22:23:03.41#ibcon#about to write, iclass 4, count 0 2006.257.22:23:03.41#ibcon#wrote, iclass 4, count 0 2006.257.22:23:03.41#ibcon#about to read 3, iclass 4, count 0 2006.257.22:23:03.44#ibcon#read 3, iclass 4, count 0 2006.257.22:23:03.44#ibcon#about to read 4, iclass 4, count 0 2006.257.22:23:03.44#ibcon#read 4, iclass 4, count 0 2006.257.22:23:03.44#ibcon#about to read 5, iclass 4, count 0 2006.257.22:23:03.44#ibcon#read 5, iclass 4, count 0 2006.257.22:23:03.44#ibcon#about to read 6, iclass 4, count 0 2006.257.22:23:03.44#ibcon#read 6, iclass 4, count 0 2006.257.22:23:03.44#ibcon#end of sib2, iclass 4, count 0 2006.257.22:23:03.44#ibcon#*after write, iclass 4, count 0 2006.257.22:23:03.44#ibcon#*before return 0, iclass 4, count 0 2006.257.22:23:03.44#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:03.44#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.22:23:03.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.22:23:03.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.22:23:03.44$vck44/vblo=5,709.99 2006.257.22:23:03.44#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.22:23:03.44#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.22:23:03.44#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:03.44#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:03.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:03.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:03.44#ibcon#enter wrdev, iclass 6, count 0 2006.257.22:23:03.44#ibcon#first serial, iclass 6, count 0 2006.257.22:23:03.44#ibcon#enter sib2, iclass 6, count 0 2006.257.22:23:03.44#ibcon#flushed, iclass 6, count 0 2006.257.22:23:03.44#ibcon#about to write, iclass 6, count 0 2006.257.22:23:03.44#ibcon#wrote, iclass 6, count 0 2006.257.22:23:03.44#ibcon#about to read 3, iclass 6, count 0 2006.257.22:23:03.46#ibcon#read 3, iclass 6, count 0 2006.257.22:23:03.46#ibcon#about to read 4, iclass 6, count 0 2006.257.22:23:03.46#ibcon#read 4, iclass 6, count 0 2006.257.22:23:03.46#ibcon#about to read 5, iclass 6, count 0 2006.257.22:23:03.46#ibcon#read 5, iclass 6, count 0 2006.257.22:23:03.46#ibcon#about to read 6, iclass 6, count 0 2006.257.22:23:03.46#ibcon#read 6, iclass 6, count 0 2006.257.22:23:03.46#ibcon#end of sib2, iclass 6, count 0 2006.257.22:23:03.46#ibcon#*mode == 0, iclass 6, count 0 2006.257.22:23:03.46#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.22:23:03.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.22:23:03.46#ibcon#*before write, iclass 6, count 0 2006.257.22:23:03.46#ibcon#enter sib2, iclass 6, count 0 2006.257.22:23:03.46#ibcon#flushed, iclass 6, count 0 2006.257.22:23:03.46#ibcon#about to write, iclass 6, count 0 2006.257.22:23:03.46#ibcon#wrote, iclass 6, count 0 2006.257.22:23:03.46#ibcon#about to read 3, iclass 6, count 0 2006.257.22:23:03.50#ibcon#read 3, iclass 6, count 0 2006.257.22:23:03.50#ibcon#about to read 4, iclass 6, count 0 2006.257.22:23:03.50#ibcon#read 4, iclass 6, count 0 2006.257.22:23:03.50#ibcon#about to read 5, iclass 6, count 0 2006.257.22:23:03.50#ibcon#read 5, iclass 6, count 0 2006.257.22:23:03.50#ibcon#about to read 6, iclass 6, count 0 2006.257.22:23:03.50#ibcon#read 6, iclass 6, count 0 2006.257.22:23:03.50#ibcon#end of sib2, iclass 6, count 0 2006.257.22:23:03.50#ibcon#*after write, iclass 6, count 0 2006.257.22:23:03.50#ibcon#*before return 0, iclass 6, count 0 2006.257.22:23:03.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:03.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.22:23:03.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.22:23:03.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.22:23:03.50$vck44/vb=5,4 2006.257.22:23:03.50#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.22:23:03.50#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.22:23:03.50#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:03.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:03.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:03.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:03.56#ibcon#enter wrdev, iclass 10, count 2 2006.257.22:23:03.56#ibcon#first serial, iclass 10, count 2 2006.257.22:23:03.56#ibcon#enter sib2, iclass 10, count 2 2006.257.22:23:03.56#ibcon#flushed, iclass 10, count 2 2006.257.22:23:03.56#ibcon#about to write, iclass 10, count 2 2006.257.22:23:03.56#ibcon#wrote, iclass 10, count 2 2006.257.22:23:03.56#ibcon#about to read 3, iclass 10, count 2 2006.257.22:23:03.58#ibcon#read 3, iclass 10, count 2 2006.257.22:23:03.58#ibcon#about to read 4, iclass 10, count 2 2006.257.22:23:03.58#ibcon#read 4, iclass 10, count 2 2006.257.22:23:03.58#ibcon#about to read 5, iclass 10, count 2 2006.257.22:23:03.58#ibcon#read 5, iclass 10, count 2 2006.257.22:23:03.58#ibcon#about to read 6, iclass 10, count 2 2006.257.22:23:03.58#ibcon#read 6, iclass 10, count 2 2006.257.22:23:03.58#ibcon#end of sib2, iclass 10, count 2 2006.257.22:23:03.58#ibcon#*mode == 0, iclass 10, count 2 2006.257.22:23:03.58#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.22:23:03.58#ibcon#[27=AT05-04\r\n] 2006.257.22:23:03.58#ibcon#*before write, iclass 10, count 2 2006.257.22:23:03.58#ibcon#enter sib2, iclass 10, count 2 2006.257.22:23:03.58#ibcon#flushed, iclass 10, count 2 2006.257.22:23:03.58#ibcon#about to write, iclass 10, count 2 2006.257.22:23:03.58#ibcon#wrote, iclass 10, count 2 2006.257.22:23:03.58#ibcon#about to read 3, iclass 10, count 2 2006.257.22:23:03.61#ibcon#read 3, iclass 10, count 2 2006.257.22:23:03.61#ibcon#about to read 4, iclass 10, count 2 2006.257.22:23:03.61#ibcon#read 4, iclass 10, count 2 2006.257.22:23:03.61#ibcon#about to read 5, iclass 10, count 2 2006.257.22:23:03.61#ibcon#read 5, iclass 10, count 2 2006.257.22:23:03.61#ibcon#about to read 6, iclass 10, count 2 2006.257.22:23:03.61#ibcon#read 6, iclass 10, count 2 2006.257.22:23:03.61#ibcon#end of sib2, iclass 10, count 2 2006.257.22:23:03.61#ibcon#*after write, iclass 10, count 2 2006.257.22:23:03.61#ibcon#*before return 0, iclass 10, count 2 2006.257.22:23:03.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:03.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.22:23:03.61#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.22:23:03.61#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:03.61#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:03.73#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:03.73#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:03.73#ibcon#enter wrdev, iclass 10, count 0 2006.257.22:23:03.73#ibcon#first serial, iclass 10, count 0 2006.257.22:23:03.73#ibcon#enter sib2, iclass 10, count 0 2006.257.22:23:03.73#ibcon#flushed, iclass 10, count 0 2006.257.22:23:03.73#ibcon#about to write, iclass 10, count 0 2006.257.22:23:03.73#ibcon#wrote, iclass 10, count 0 2006.257.22:23:03.73#ibcon#about to read 3, iclass 10, count 0 2006.257.22:23:03.75#ibcon#read 3, iclass 10, count 0 2006.257.22:23:03.75#ibcon#about to read 4, iclass 10, count 0 2006.257.22:23:03.75#ibcon#read 4, iclass 10, count 0 2006.257.22:23:03.75#ibcon#about to read 5, iclass 10, count 0 2006.257.22:23:03.75#ibcon#read 5, iclass 10, count 0 2006.257.22:23:03.75#ibcon#about to read 6, iclass 10, count 0 2006.257.22:23:03.75#ibcon#read 6, iclass 10, count 0 2006.257.22:23:03.75#ibcon#end of sib2, iclass 10, count 0 2006.257.22:23:03.75#ibcon#*mode == 0, iclass 10, count 0 2006.257.22:23:03.75#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.22:23:03.75#ibcon#[27=USB\r\n] 2006.257.22:23:03.75#ibcon#*before write, iclass 10, count 0 2006.257.22:23:03.75#ibcon#enter sib2, iclass 10, count 0 2006.257.22:23:03.75#ibcon#flushed, iclass 10, count 0 2006.257.22:23:03.75#ibcon#about to write, iclass 10, count 0 2006.257.22:23:03.75#ibcon#wrote, iclass 10, count 0 2006.257.22:23:03.75#ibcon#about to read 3, iclass 10, count 0 2006.257.22:23:03.78#ibcon#read 3, iclass 10, count 0 2006.257.22:23:03.78#ibcon#about to read 4, iclass 10, count 0 2006.257.22:23:03.78#ibcon#read 4, iclass 10, count 0 2006.257.22:23:03.78#ibcon#about to read 5, iclass 10, count 0 2006.257.22:23:03.78#ibcon#read 5, iclass 10, count 0 2006.257.22:23:03.78#ibcon#about to read 6, iclass 10, count 0 2006.257.22:23:03.78#ibcon#read 6, iclass 10, count 0 2006.257.22:23:03.78#ibcon#end of sib2, iclass 10, count 0 2006.257.22:23:03.78#ibcon#*after write, iclass 10, count 0 2006.257.22:23:03.78#ibcon#*before return 0, iclass 10, count 0 2006.257.22:23:03.78#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:03.78#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.22:23:03.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.22:23:03.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.22:23:03.78$vck44/vblo=6,719.99 2006.257.22:23:03.78#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.22:23:03.78#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.22:23:03.78#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:03.78#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:03.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:03.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:03.78#ibcon#enter wrdev, iclass 12, count 0 2006.257.22:23:03.78#ibcon#first serial, iclass 12, count 0 2006.257.22:23:03.78#ibcon#enter sib2, iclass 12, count 0 2006.257.22:23:03.78#ibcon#flushed, iclass 12, count 0 2006.257.22:23:03.78#ibcon#about to write, iclass 12, count 0 2006.257.22:23:03.78#ibcon#wrote, iclass 12, count 0 2006.257.22:23:03.78#ibcon#about to read 3, iclass 12, count 0 2006.257.22:23:03.80#ibcon#read 3, iclass 12, count 0 2006.257.22:23:03.80#ibcon#about to read 4, iclass 12, count 0 2006.257.22:23:03.80#ibcon#read 4, iclass 12, count 0 2006.257.22:23:03.80#ibcon#about to read 5, iclass 12, count 0 2006.257.22:23:03.80#ibcon#read 5, iclass 12, count 0 2006.257.22:23:03.80#ibcon#about to read 6, iclass 12, count 0 2006.257.22:23:03.80#ibcon#read 6, iclass 12, count 0 2006.257.22:23:03.80#ibcon#end of sib2, iclass 12, count 0 2006.257.22:23:03.80#ibcon#*mode == 0, iclass 12, count 0 2006.257.22:23:03.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.22:23:03.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.22:23:03.80#ibcon#*before write, iclass 12, count 0 2006.257.22:23:03.80#ibcon#enter sib2, iclass 12, count 0 2006.257.22:23:03.80#ibcon#flushed, iclass 12, count 0 2006.257.22:23:03.80#ibcon#about to write, iclass 12, count 0 2006.257.22:23:03.80#ibcon#wrote, iclass 12, count 0 2006.257.22:23:03.80#ibcon#about to read 3, iclass 12, count 0 2006.257.22:23:03.84#ibcon#read 3, iclass 12, count 0 2006.257.22:23:03.84#ibcon#about to read 4, iclass 12, count 0 2006.257.22:23:03.84#ibcon#read 4, iclass 12, count 0 2006.257.22:23:03.84#ibcon#about to read 5, iclass 12, count 0 2006.257.22:23:03.84#ibcon#read 5, iclass 12, count 0 2006.257.22:23:03.84#ibcon#about to read 6, iclass 12, count 0 2006.257.22:23:03.84#ibcon#read 6, iclass 12, count 0 2006.257.22:23:03.84#ibcon#end of sib2, iclass 12, count 0 2006.257.22:23:03.84#ibcon#*after write, iclass 12, count 0 2006.257.22:23:03.84#ibcon#*before return 0, iclass 12, count 0 2006.257.22:23:03.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:03.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.22:23:03.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.22:23:03.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.22:23:03.84$vck44/vb=6,4 2006.257.22:23:03.84#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.22:23:03.84#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.22:23:03.84#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:03.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:03.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:03.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:03.90#ibcon#enter wrdev, iclass 14, count 2 2006.257.22:23:03.90#ibcon#first serial, iclass 14, count 2 2006.257.22:23:03.90#ibcon#enter sib2, iclass 14, count 2 2006.257.22:23:03.90#ibcon#flushed, iclass 14, count 2 2006.257.22:23:03.90#ibcon#about to write, iclass 14, count 2 2006.257.22:23:03.90#ibcon#wrote, iclass 14, count 2 2006.257.22:23:03.90#ibcon#about to read 3, iclass 14, count 2 2006.257.22:23:03.92#ibcon#read 3, iclass 14, count 2 2006.257.22:23:03.92#ibcon#about to read 4, iclass 14, count 2 2006.257.22:23:03.92#ibcon#read 4, iclass 14, count 2 2006.257.22:23:03.92#ibcon#about to read 5, iclass 14, count 2 2006.257.22:23:03.92#ibcon#read 5, iclass 14, count 2 2006.257.22:23:03.92#ibcon#about to read 6, iclass 14, count 2 2006.257.22:23:03.92#ibcon#read 6, iclass 14, count 2 2006.257.22:23:03.92#ibcon#end of sib2, iclass 14, count 2 2006.257.22:23:03.92#ibcon#*mode == 0, iclass 14, count 2 2006.257.22:23:03.92#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.22:23:03.92#ibcon#[27=AT06-04\r\n] 2006.257.22:23:03.92#ibcon#*before write, iclass 14, count 2 2006.257.22:23:03.92#ibcon#enter sib2, iclass 14, count 2 2006.257.22:23:03.92#ibcon#flushed, iclass 14, count 2 2006.257.22:23:03.92#ibcon#about to write, iclass 14, count 2 2006.257.22:23:03.92#ibcon#wrote, iclass 14, count 2 2006.257.22:23:03.92#ibcon#about to read 3, iclass 14, count 2 2006.257.22:23:03.95#ibcon#read 3, iclass 14, count 2 2006.257.22:23:03.95#ibcon#about to read 4, iclass 14, count 2 2006.257.22:23:03.95#ibcon#read 4, iclass 14, count 2 2006.257.22:23:03.95#ibcon#about to read 5, iclass 14, count 2 2006.257.22:23:03.95#ibcon#read 5, iclass 14, count 2 2006.257.22:23:03.95#ibcon#about to read 6, iclass 14, count 2 2006.257.22:23:03.95#ibcon#read 6, iclass 14, count 2 2006.257.22:23:03.95#ibcon#end of sib2, iclass 14, count 2 2006.257.22:23:03.95#ibcon#*after write, iclass 14, count 2 2006.257.22:23:03.95#ibcon#*before return 0, iclass 14, count 2 2006.257.22:23:03.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:03.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.22:23:03.95#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.22:23:03.95#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:03.95#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:04.07#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:04.07#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:04.07#ibcon#enter wrdev, iclass 14, count 0 2006.257.22:23:04.07#ibcon#first serial, iclass 14, count 0 2006.257.22:23:04.07#ibcon#enter sib2, iclass 14, count 0 2006.257.22:23:04.07#ibcon#flushed, iclass 14, count 0 2006.257.22:23:04.07#ibcon#about to write, iclass 14, count 0 2006.257.22:23:04.07#ibcon#wrote, iclass 14, count 0 2006.257.22:23:04.07#ibcon#about to read 3, iclass 14, count 0 2006.257.22:23:04.09#ibcon#read 3, iclass 14, count 0 2006.257.22:23:04.09#ibcon#about to read 4, iclass 14, count 0 2006.257.22:23:04.09#ibcon#read 4, iclass 14, count 0 2006.257.22:23:04.09#ibcon#about to read 5, iclass 14, count 0 2006.257.22:23:04.09#ibcon#read 5, iclass 14, count 0 2006.257.22:23:04.09#ibcon#about to read 6, iclass 14, count 0 2006.257.22:23:04.09#ibcon#read 6, iclass 14, count 0 2006.257.22:23:04.09#ibcon#end of sib2, iclass 14, count 0 2006.257.22:23:04.09#ibcon#*mode == 0, iclass 14, count 0 2006.257.22:23:04.09#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.22:23:04.09#ibcon#[27=USB\r\n] 2006.257.22:23:04.09#ibcon#*before write, iclass 14, count 0 2006.257.22:23:04.09#ibcon#enter sib2, iclass 14, count 0 2006.257.22:23:04.09#ibcon#flushed, iclass 14, count 0 2006.257.22:23:04.09#ibcon#about to write, iclass 14, count 0 2006.257.22:23:04.09#ibcon#wrote, iclass 14, count 0 2006.257.22:23:04.09#ibcon#about to read 3, iclass 14, count 0 2006.257.22:23:04.12#ibcon#read 3, iclass 14, count 0 2006.257.22:23:04.12#ibcon#about to read 4, iclass 14, count 0 2006.257.22:23:04.12#ibcon#read 4, iclass 14, count 0 2006.257.22:23:04.12#ibcon#about to read 5, iclass 14, count 0 2006.257.22:23:04.12#ibcon#read 5, iclass 14, count 0 2006.257.22:23:04.12#ibcon#about to read 6, iclass 14, count 0 2006.257.22:23:04.12#ibcon#read 6, iclass 14, count 0 2006.257.22:23:04.12#ibcon#end of sib2, iclass 14, count 0 2006.257.22:23:04.12#ibcon#*after write, iclass 14, count 0 2006.257.22:23:04.12#ibcon#*before return 0, iclass 14, count 0 2006.257.22:23:04.12#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:04.12#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.22:23:04.12#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.22:23:04.12#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.22:23:04.12$vck44/vblo=7,734.99 2006.257.22:23:04.12#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.22:23:04.12#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.22:23:04.12#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:04.12#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:04.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:04.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:04.12#ibcon#enter wrdev, iclass 16, count 0 2006.257.22:23:04.12#ibcon#first serial, iclass 16, count 0 2006.257.22:23:04.12#ibcon#enter sib2, iclass 16, count 0 2006.257.22:23:04.12#ibcon#flushed, iclass 16, count 0 2006.257.22:23:04.12#ibcon#about to write, iclass 16, count 0 2006.257.22:23:04.12#ibcon#wrote, iclass 16, count 0 2006.257.22:23:04.12#ibcon#about to read 3, iclass 16, count 0 2006.257.22:23:04.14#ibcon#read 3, iclass 16, count 0 2006.257.22:23:04.14#ibcon#about to read 4, iclass 16, count 0 2006.257.22:23:04.14#ibcon#read 4, iclass 16, count 0 2006.257.22:23:04.14#ibcon#about to read 5, iclass 16, count 0 2006.257.22:23:04.14#ibcon#read 5, iclass 16, count 0 2006.257.22:23:04.14#ibcon#about to read 6, iclass 16, count 0 2006.257.22:23:04.14#ibcon#read 6, iclass 16, count 0 2006.257.22:23:04.14#ibcon#end of sib2, iclass 16, count 0 2006.257.22:23:04.14#ibcon#*mode == 0, iclass 16, count 0 2006.257.22:23:04.14#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.22:23:04.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.22:23:04.14#ibcon#*before write, iclass 16, count 0 2006.257.22:23:04.14#ibcon#enter sib2, iclass 16, count 0 2006.257.22:23:04.14#ibcon#flushed, iclass 16, count 0 2006.257.22:23:04.14#ibcon#about to write, iclass 16, count 0 2006.257.22:23:04.14#ibcon#wrote, iclass 16, count 0 2006.257.22:23:04.14#ibcon#about to read 3, iclass 16, count 0 2006.257.22:23:04.18#ibcon#read 3, iclass 16, count 0 2006.257.22:23:04.18#ibcon#about to read 4, iclass 16, count 0 2006.257.22:23:04.18#ibcon#read 4, iclass 16, count 0 2006.257.22:23:04.18#ibcon#about to read 5, iclass 16, count 0 2006.257.22:23:04.18#ibcon#read 5, iclass 16, count 0 2006.257.22:23:04.18#ibcon#about to read 6, iclass 16, count 0 2006.257.22:23:04.18#ibcon#read 6, iclass 16, count 0 2006.257.22:23:04.18#ibcon#end of sib2, iclass 16, count 0 2006.257.22:23:04.18#ibcon#*after write, iclass 16, count 0 2006.257.22:23:04.18#ibcon#*before return 0, iclass 16, count 0 2006.257.22:23:04.18#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:04.18#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.22:23:04.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.22:23:04.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.22:23:04.18$vck44/vb=7,4 2006.257.22:23:04.18#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.22:23:04.18#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.22:23:04.18#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:04.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:04.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:04.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:04.24#ibcon#enter wrdev, iclass 18, count 2 2006.257.22:23:04.24#ibcon#first serial, iclass 18, count 2 2006.257.22:23:04.24#ibcon#enter sib2, iclass 18, count 2 2006.257.22:23:04.24#ibcon#flushed, iclass 18, count 2 2006.257.22:23:04.24#ibcon#about to write, iclass 18, count 2 2006.257.22:23:04.24#ibcon#wrote, iclass 18, count 2 2006.257.22:23:04.24#ibcon#about to read 3, iclass 18, count 2 2006.257.22:23:04.26#ibcon#read 3, iclass 18, count 2 2006.257.22:23:04.26#ibcon#about to read 4, iclass 18, count 2 2006.257.22:23:04.26#ibcon#read 4, iclass 18, count 2 2006.257.22:23:04.26#ibcon#about to read 5, iclass 18, count 2 2006.257.22:23:04.26#ibcon#read 5, iclass 18, count 2 2006.257.22:23:04.26#ibcon#about to read 6, iclass 18, count 2 2006.257.22:23:04.26#ibcon#read 6, iclass 18, count 2 2006.257.22:23:04.26#ibcon#end of sib2, iclass 18, count 2 2006.257.22:23:04.26#ibcon#*mode == 0, iclass 18, count 2 2006.257.22:23:04.26#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.22:23:04.26#ibcon#[27=AT07-04\r\n] 2006.257.22:23:04.26#ibcon#*before write, iclass 18, count 2 2006.257.22:23:04.26#ibcon#enter sib2, iclass 18, count 2 2006.257.22:23:04.26#ibcon#flushed, iclass 18, count 2 2006.257.22:23:04.26#ibcon#about to write, iclass 18, count 2 2006.257.22:23:04.26#ibcon#wrote, iclass 18, count 2 2006.257.22:23:04.26#ibcon#about to read 3, iclass 18, count 2 2006.257.22:23:04.29#ibcon#read 3, iclass 18, count 2 2006.257.22:23:04.29#ibcon#about to read 4, iclass 18, count 2 2006.257.22:23:04.29#ibcon#read 4, iclass 18, count 2 2006.257.22:23:04.29#ibcon#about to read 5, iclass 18, count 2 2006.257.22:23:04.29#ibcon#read 5, iclass 18, count 2 2006.257.22:23:04.29#ibcon#about to read 6, iclass 18, count 2 2006.257.22:23:04.29#ibcon#read 6, iclass 18, count 2 2006.257.22:23:04.29#ibcon#end of sib2, iclass 18, count 2 2006.257.22:23:04.29#ibcon#*after write, iclass 18, count 2 2006.257.22:23:04.29#ibcon#*before return 0, iclass 18, count 2 2006.257.22:23:04.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:04.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.22:23:04.29#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.22:23:04.29#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:04.29#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:04.41#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:04.41#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:04.41#ibcon#enter wrdev, iclass 18, count 0 2006.257.22:23:04.41#ibcon#first serial, iclass 18, count 0 2006.257.22:23:04.41#ibcon#enter sib2, iclass 18, count 0 2006.257.22:23:04.41#ibcon#flushed, iclass 18, count 0 2006.257.22:23:04.41#ibcon#about to write, iclass 18, count 0 2006.257.22:23:04.41#ibcon#wrote, iclass 18, count 0 2006.257.22:23:04.41#ibcon#about to read 3, iclass 18, count 0 2006.257.22:23:04.43#ibcon#read 3, iclass 18, count 0 2006.257.22:23:04.43#ibcon#about to read 4, iclass 18, count 0 2006.257.22:23:04.43#ibcon#read 4, iclass 18, count 0 2006.257.22:23:04.43#ibcon#about to read 5, iclass 18, count 0 2006.257.22:23:04.43#ibcon#read 5, iclass 18, count 0 2006.257.22:23:04.43#ibcon#about to read 6, iclass 18, count 0 2006.257.22:23:04.43#ibcon#read 6, iclass 18, count 0 2006.257.22:23:04.43#ibcon#end of sib2, iclass 18, count 0 2006.257.22:23:04.43#ibcon#*mode == 0, iclass 18, count 0 2006.257.22:23:04.43#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.22:23:04.43#ibcon#[27=USB\r\n] 2006.257.22:23:04.43#ibcon#*before write, iclass 18, count 0 2006.257.22:23:04.43#ibcon#enter sib2, iclass 18, count 0 2006.257.22:23:04.43#ibcon#flushed, iclass 18, count 0 2006.257.22:23:04.43#ibcon#about to write, iclass 18, count 0 2006.257.22:23:04.43#ibcon#wrote, iclass 18, count 0 2006.257.22:23:04.43#ibcon#about to read 3, iclass 18, count 0 2006.257.22:23:04.46#ibcon#read 3, iclass 18, count 0 2006.257.22:23:04.46#ibcon#about to read 4, iclass 18, count 0 2006.257.22:23:04.46#ibcon#read 4, iclass 18, count 0 2006.257.22:23:04.46#ibcon#about to read 5, iclass 18, count 0 2006.257.22:23:04.46#ibcon#read 5, iclass 18, count 0 2006.257.22:23:04.46#ibcon#about to read 6, iclass 18, count 0 2006.257.22:23:04.46#ibcon#read 6, iclass 18, count 0 2006.257.22:23:04.46#ibcon#end of sib2, iclass 18, count 0 2006.257.22:23:04.46#ibcon#*after write, iclass 18, count 0 2006.257.22:23:04.46#ibcon#*before return 0, iclass 18, count 0 2006.257.22:23:04.46#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:04.46#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.22:23:04.46#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.22:23:04.46#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.22:23:04.46$vck44/vblo=8,744.99 2006.257.22:23:04.46#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.22:23:04.46#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.22:23:04.46#ibcon#ireg 17 cls_cnt 0 2006.257.22:23:04.46#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:04.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:04.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:04.46#ibcon#enter wrdev, iclass 20, count 0 2006.257.22:23:04.46#ibcon#first serial, iclass 20, count 0 2006.257.22:23:04.46#ibcon#enter sib2, iclass 20, count 0 2006.257.22:23:04.46#ibcon#flushed, iclass 20, count 0 2006.257.22:23:04.46#ibcon#about to write, iclass 20, count 0 2006.257.22:23:04.46#ibcon#wrote, iclass 20, count 0 2006.257.22:23:04.46#ibcon#about to read 3, iclass 20, count 0 2006.257.22:23:04.48#ibcon#read 3, iclass 20, count 0 2006.257.22:23:04.48#ibcon#about to read 4, iclass 20, count 0 2006.257.22:23:04.48#ibcon#read 4, iclass 20, count 0 2006.257.22:23:04.48#ibcon#about to read 5, iclass 20, count 0 2006.257.22:23:04.48#ibcon#read 5, iclass 20, count 0 2006.257.22:23:04.48#ibcon#about to read 6, iclass 20, count 0 2006.257.22:23:04.48#ibcon#read 6, iclass 20, count 0 2006.257.22:23:04.48#ibcon#end of sib2, iclass 20, count 0 2006.257.22:23:04.48#ibcon#*mode == 0, iclass 20, count 0 2006.257.22:23:04.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.22:23:04.48#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.22:23:04.48#ibcon#*before write, iclass 20, count 0 2006.257.22:23:04.48#ibcon#enter sib2, iclass 20, count 0 2006.257.22:23:04.48#ibcon#flushed, iclass 20, count 0 2006.257.22:23:04.48#ibcon#about to write, iclass 20, count 0 2006.257.22:23:04.48#ibcon#wrote, iclass 20, count 0 2006.257.22:23:04.48#ibcon#about to read 3, iclass 20, count 0 2006.257.22:23:04.52#ibcon#read 3, iclass 20, count 0 2006.257.22:23:04.52#ibcon#about to read 4, iclass 20, count 0 2006.257.22:23:04.52#ibcon#read 4, iclass 20, count 0 2006.257.22:23:04.52#ibcon#about to read 5, iclass 20, count 0 2006.257.22:23:04.52#ibcon#read 5, iclass 20, count 0 2006.257.22:23:04.52#ibcon#about to read 6, iclass 20, count 0 2006.257.22:23:04.52#ibcon#read 6, iclass 20, count 0 2006.257.22:23:04.52#ibcon#end of sib2, iclass 20, count 0 2006.257.22:23:04.52#ibcon#*after write, iclass 20, count 0 2006.257.22:23:04.52#ibcon#*before return 0, iclass 20, count 0 2006.257.22:23:04.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:04.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.22:23:04.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.22:23:04.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.22:23:04.52$vck44/vb=8,4 2006.257.22:23:04.52#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.22:23:04.52#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.22:23:04.52#ibcon#ireg 11 cls_cnt 2 2006.257.22:23:04.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:04.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:04.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:04.58#ibcon#enter wrdev, iclass 22, count 2 2006.257.22:23:04.58#ibcon#first serial, iclass 22, count 2 2006.257.22:23:04.58#ibcon#enter sib2, iclass 22, count 2 2006.257.22:23:04.58#ibcon#flushed, iclass 22, count 2 2006.257.22:23:04.58#ibcon#about to write, iclass 22, count 2 2006.257.22:23:04.58#ibcon#wrote, iclass 22, count 2 2006.257.22:23:04.58#ibcon#about to read 3, iclass 22, count 2 2006.257.22:23:04.60#ibcon#read 3, iclass 22, count 2 2006.257.22:23:04.60#ibcon#about to read 4, iclass 22, count 2 2006.257.22:23:04.60#ibcon#read 4, iclass 22, count 2 2006.257.22:23:04.60#ibcon#about to read 5, iclass 22, count 2 2006.257.22:23:04.60#ibcon#read 5, iclass 22, count 2 2006.257.22:23:04.60#ibcon#about to read 6, iclass 22, count 2 2006.257.22:23:04.60#ibcon#read 6, iclass 22, count 2 2006.257.22:23:04.60#ibcon#end of sib2, iclass 22, count 2 2006.257.22:23:04.60#ibcon#*mode == 0, iclass 22, count 2 2006.257.22:23:04.60#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.22:23:04.60#ibcon#[27=AT08-04\r\n] 2006.257.22:23:04.60#ibcon#*before write, iclass 22, count 2 2006.257.22:23:04.60#ibcon#enter sib2, iclass 22, count 2 2006.257.22:23:04.60#ibcon#flushed, iclass 22, count 2 2006.257.22:23:04.60#ibcon#about to write, iclass 22, count 2 2006.257.22:23:04.60#ibcon#wrote, iclass 22, count 2 2006.257.22:23:04.60#ibcon#about to read 3, iclass 22, count 2 2006.257.22:23:04.63#ibcon#read 3, iclass 22, count 2 2006.257.22:23:04.63#ibcon#about to read 4, iclass 22, count 2 2006.257.22:23:04.63#ibcon#read 4, iclass 22, count 2 2006.257.22:23:04.63#ibcon#about to read 5, iclass 22, count 2 2006.257.22:23:04.63#ibcon#read 5, iclass 22, count 2 2006.257.22:23:04.63#ibcon#about to read 6, iclass 22, count 2 2006.257.22:23:04.63#ibcon#read 6, iclass 22, count 2 2006.257.22:23:04.63#ibcon#end of sib2, iclass 22, count 2 2006.257.22:23:04.63#ibcon#*after write, iclass 22, count 2 2006.257.22:23:04.63#ibcon#*before return 0, iclass 22, count 2 2006.257.22:23:04.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:04.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.22:23:04.63#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.22:23:04.63#ibcon#ireg 7 cls_cnt 0 2006.257.22:23:04.63#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:04.75#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:04.75#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:04.75#ibcon#enter wrdev, iclass 22, count 0 2006.257.22:23:04.75#ibcon#first serial, iclass 22, count 0 2006.257.22:23:04.75#ibcon#enter sib2, iclass 22, count 0 2006.257.22:23:04.75#ibcon#flushed, iclass 22, count 0 2006.257.22:23:04.75#ibcon#about to write, iclass 22, count 0 2006.257.22:23:04.75#ibcon#wrote, iclass 22, count 0 2006.257.22:23:04.75#ibcon#about to read 3, iclass 22, count 0 2006.257.22:23:04.77#ibcon#read 3, iclass 22, count 0 2006.257.22:23:04.77#ibcon#about to read 4, iclass 22, count 0 2006.257.22:23:04.77#ibcon#read 4, iclass 22, count 0 2006.257.22:23:04.77#ibcon#about to read 5, iclass 22, count 0 2006.257.22:23:04.77#ibcon#read 5, iclass 22, count 0 2006.257.22:23:04.77#ibcon#about to read 6, iclass 22, count 0 2006.257.22:23:04.77#ibcon#read 6, iclass 22, count 0 2006.257.22:23:04.77#ibcon#end of sib2, iclass 22, count 0 2006.257.22:23:04.77#ibcon#*mode == 0, iclass 22, count 0 2006.257.22:23:04.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.22:23:04.77#ibcon#[27=USB\r\n] 2006.257.22:23:04.77#ibcon#*before write, iclass 22, count 0 2006.257.22:23:04.77#ibcon#enter sib2, iclass 22, count 0 2006.257.22:23:04.77#ibcon#flushed, iclass 22, count 0 2006.257.22:23:04.77#ibcon#about to write, iclass 22, count 0 2006.257.22:23:04.77#ibcon#wrote, iclass 22, count 0 2006.257.22:23:04.77#ibcon#about to read 3, iclass 22, count 0 2006.257.22:23:04.80#ibcon#read 3, iclass 22, count 0 2006.257.22:23:04.80#ibcon#about to read 4, iclass 22, count 0 2006.257.22:23:04.80#ibcon#read 4, iclass 22, count 0 2006.257.22:23:04.80#ibcon#about to read 5, iclass 22, count 0 2006.257.22:23:04.80#ibcon#read 5, iclass 22, count 0 2006.257.22:23:04.80#ibcon#about to read 6, iclass 22, count 0 2006.257.22:23:04.80#ibcon#read 6, iclass 22, count 0 2006.257.22:23:04.80#ibcon#end of sib2, iclass 22, count 0 2006.257.22:23:04.80#ibcon#*after write, iclass 22, count 0 2006.257.22:23:04.80#ibcon#*before return 0, iclass 22, count 0 2006.257.22:23:04.80#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:04.80#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.22:23:04.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.22:23:04.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.22:23:04.80$vck44/vabw=wide 2006.257.22:23:04.80#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.22:23:04.80#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.22:23:04.80#ibcon#ireg 8 cls_cnt 0 2006.257.22:23:04.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:04.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:04.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:04.80#ibcon#enter wrdev, iclass 24, count 0 2006.257.22:23:04.80#ibcon#first serial, iclass 24, count 0 2006.257.22:23:04.80#ibcon#enter sib2, iclass 24, count 0 2006.257.22:23:04.80#ibcon#flushed, iclass 24, count 0 2006.257.22:23:04.80#ibcon#about to write, iclass 24, count 0 2006.257.22:23:04.80#ibcon#wrote, iclass 24, count 0 2006.257.22:23:04.80#ibcon#about to read 3, iclass 24, count 0 2006.257.22:23:04.82#ibcon#read 3, iclass 24, count 0 2006.257.22:23:04.82#ibcon#about to read 4, iclass 24, count 0 2006.257.22:23:04.82#ibcon#read 4, iclass 24, count 0 2006.257.22:23:04.82#ibcon#about to read 5, iclass 24, count 0 2006.257.22:23:04.82#ibcon#read 5, iclass 24, count 0 2006.257.22:23:04.82#ibcon#about to read 6, iclass 24, count 0 2006.257.22:23:04.82#ibcon#read 6, iclass 24, count 0 2006.257.22:23:04.82#ibcon#end of sib2, iclass 24, count 0 2006.257.22:23:04.82#ibcon#*mode == 0, iclass 24, count 0 2006.257.22:23:04.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.22:23:04.82#ibcon#[25=BW32\r\n] 2006.257.22:23:04.82#ibcon#*before write, iclass 24, count 0 2006.257.22:23:04.82#ibcon#enter sib2, iclass 24, count 0 2006.257.22:23:04.82#ibcon#flushed, iclass 24, count 0 2006.257.22:23:04.82#ibcon#about to write, iclass 24, count 0 2006.257.22:23:04.82#ibcon#wrote, iclass 24, count 0 2006.257.22:23:04.82#ibcon#about to read 3, iclass 24, count 0 2006.257.22:23:04.85#ibcon#read 3, iclass 24, count 0 2006.257.22:23:04.85#ibcon#about to read 4, iclass 24, count 0 2006.257.22:23:04.85#ibcon#read 4, iclass 24, count 0 2006.257.22:23:04.85#ibcon#about to read 5, iclass 24, count 0 2006.257.22:23:04.85#ibcon#read 5, iclass 24, count 0 2006.257.22:23:04.85#ibcon#about to read 6, iclass 24, count 0 2006.257.22:23:04.85#ibcon#read 6, iclass 24, count 0 2006.257.22:23:04.85#ibcon#end of sib2, iclass 24, count 0 2006.257.22:23:04.85#ibcon#*after write, iclass 24, count 0 2006.257.22:23:04.85#ibcon#*before return 0, iclass 24, count 0 2006.257.22:23:04.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:04.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:23:04.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.22:23:04.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.22:23:04.85$vck44/vbbw=wide 2006.257.22:23:04.85#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.22:23:04.85#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.22:23:04.85#ibcon#ireg 8 cls_cnt 0 2006.257.22:23:04.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:23:04.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:23:04.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:23:04.92#ibcon#enter wrdev, iclass 26, count 0 2006.257.22:23:04.92#ibcon#first serial, iclass 26, count 0 2006.257.22:23:04.92#ibcon#enter sib2, iclass 26, count 0 2006.257.22:23:04.92#ibcon#flushed, iclass 26, count 0 2006.257.22:23:04.92#ibcon#about to write, iclass 26, count 0 2006.257.22:23:04.92#ibcon#wrote, iclass 26, count 0 2006.257.22:23:04.92#ibcon#about to read 3, iclass 26, count 0 2006.257.22:23:04.94#ibcon#read 3, iclass 26, count 0 2006.257.22:23:04.94#ibcon#about to read 4, iclass 26, count 0 2006.257.22:23:04.94#ibcon#read 4, iclass 26, count 0 2006.257.22:23:04.94#ibcon#about to read 5, iclass 26, count 0 2006.257.22:23:04.94#ibcon#read 5, iclass 26, count 0 2006.257.22:23:04.94#ibcon#about to read 6, iclass 26, count 0 2006.257.22:23:04.94#ibcon#read 6, iclass 26, count 0 2006.257.22:23:04.94#ibcon#end of sib2, iclass 26, count 0 2006.257.22:23:04.94#ibcon#*mode == 0, iclass 26, count 0 2006.257.22:23:04.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.22:23:04.94#ibcon#[27=BW32\r\n] 2006.257.22:23:04.94#ibcon#*before write, iclass 26, count 0 2006.257.22:23:04.94#ibcon#enter sib2, iclass 26, count 0 2006.257.22:23:04.94#ibcon#flushed, iclass 26, count 0 2006.257.22:23:04.94#ibcon#about to write, iclass 26, count 0 2006.257.22:23:04.94#ibcon#wrote, iclass 26, count 0 2006.257.22:23:04.94#ibcon#about to read 3, iclass 26, count 0 2006.257.22:23:04.97#ibcon#read 3, iclass 26, count 0 2006.257.22:23:04.97#ibcon#about to read 4, iclass 26, count 0 2006.257.22:23:04.97#ibcon#read 4, iclass 26, count 0 2006.257.22:23:04.97#ibcon#about to read 5, iclass 26, count 0 2006.257.22:23:04.97#ibcon#read 5, iclass 26, count 0 2006.257.22:23:04.97#ibcon#about to read 6, iclass 26, count 0 2006.257.22:23:04.97#ibcon#read 6, iclass 26, count 0 2006.257.22:23:04.97#ibcon#end of sib2, iclass 26, count 0 2006.257.22:23:04.97#ibcon#*after write, iclass 26, count 0 2006.257.22:23:04.97#ibcon#*before return 0, iclass 26, count 0 2006.257.22:23:04.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:23:04.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:23:04.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.22:23:04.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.22:23:04.97$setupk4/ifdk4 2006.257.22:23:04.97$ifdk4/lo= 2006.257.22:23:04.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.22:23:04.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.22:23:04.97$ifdk4/patch= 2006.257.22:23:04.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.22:23:04.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.22:23:04.97$setupk4/!*+20s 2006.257.22:23:07.58#abcon#<5=/13 0.5 1.8 19.27 871015.9\r\n> 2006.257.22:23:07.60#abcon#{5=INTERFACE CLEAR} 2006.257.22:23:07.66#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:23:17.75#abcon#<5=/13 0.5 1.8 19.27 871015.9\r\n> 2006.257.22:23:17.77#abcon#{5=INTERFACE CLEAR} 2006.257.22:23:17.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:23:19.49$setupk4/"tpicd 2006.257.22:23:19.49$setupk4/echo=off 2006.257.22:23:19.49$setupk4/xlog=off 2006.257.22:23:19.49:!2006.257.22:27:09 2006.257.22:23:24.14#trakl#Source acquired 2006.257.22:23:25.14#flagr#flagr/antenna,acquired 2006.257.22:27:09.00:preob 2006.257.22:27:09.14/onsource/TRACKING 2006.257.22:27:09.14:!2006.257.22:27:19 2006.257.22:27:19.00:"tape 2006.257.22:27:19.00:"st=record 2006.257.22:27:19.00:data_valid=on 2006.257.22:27:19.00:midob 2006.257.22:27:19.14/onsource/TRACKING 2006.257.22:27:19.14/wx/19.34,1016.0,89 2006.257.22:27:19.32/cable/+6.4829E-03 2006.257.22:27:20.41/va/01,08,usb,yes,30,33 2006.257.22:27:20.41/va/02,07,usb,yes,33,34 2006.257.22:27:20.41/va/03,08,usb,yes,30,31 2006.257.22:27:20.41/va/04,07,usb,yes,34,36 2006.257.22:27:20.41/va/05,04,usb,yes,30,31 2006.257.22:27:20.41/va/06,04,usb,yes,34,34 2006.257.22:27:20.41/va/07,04,usb,yes,35,35 2006.257.22:27:20.41/va/08,04,usb,yes,29,36 2006.257.22:27:20.64/valo/01,524.99,yes,locked 2006.257.22:27:20.64/valo/02,534.99,yes,locked 2006.257.22:27:20.64/valo/03,564.99,yes,locked 2006.257.22:27:20.64/valo/04,624.99,yes,locked 2006.257.22:27:20.64/valo/05,734.99,yes,locked 2006.257.22:27:20.64/valo/06,814.99,yes,locked 2006.257.22:27:20.64/valo/07,864.99,yes,locked 2006.257.22:27:20.64/valo/08,884.99,yes,locked 2006.257.22:27:21.73/vb/01,04,usb,yes,30,28 2006.257.22:27:21.73/vb/02,05,usb,yes,29,29 2006.257.22:27:21.73/vb/03,04,usb,yes,30,33 2006.257.22:27:21.73/vb/04,05,usb,yes,30,29 2006.257.22:27:21.73/vb/05,04,usb,yes,26,29 2006.257.22:27:21.73/vb/06,04,usb,yes,31,27 2006.257.22:27:21.73/vb/07,04,usb,yes,31,31 2006.257.22:27:21.73/vb/08,04,usb,yes,28,32 2006.257.22:27:21.97/vblo/01,629.99,yes,locked 2006.257.22:27:21.97/vblo/02,634.99,yes,locked 2006.257.22:27:21.97/vblo/03,649.99,yes,locked 2006.257.22:27:21.97/vblo/04,679.99,yes,locked 2006.257.22:27:21.97/vblo/05,709.99,yes,locked 2006.257.22:27:21.97/vblo/06,719.99,yes,locked 2006.257.22:27:21.97/vblo/07,734.99,yes,locked 2006.257.22:27:21.97/vblo/08,744.99,yes,locked 2006.257.22:27:22.12/vabw/8 2006.257.22:27:22.27/vbbw/8 2006.257.22:27:22.36/xfe/off,on,15.5 2006.257.22:27:22.73/ifatt/23,28,28,28 2006.257.22:27:23.07/fmout-gps/S +4.59E-07 2006.257.22:27:23.11:!2006.257.22:30:39 2006.257.22:30:39.00:data_valid=off 2006.257.22:30:39.00:"et 2006.257.22:30:39.00:!+3s 2006.257.22:30:42.01:"tape 2006.257.22:30:42.01:postob 2006.257.22:30:42.07/cable/+6.4845E-03 2006.257.22:30:42.07/wx/19.36,1016.0,87 2006.257.22:30:43.07/fmout-gps/S +4.59E-07 2006.257.22:30:43.07:scan_name=257-2234,jd0609,50 2006.257.22:30:43.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.22:30:44.14#flagr#flagr/antenna,new-source 2006.257.22:30:44.14:checkk5 2006.257.22:30:44.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.22:30:44.85/chk_autoobs//k5ts2/ autoobs is running! 2006.257.22:30:45.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.22:30:45.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.22:30:45.86/chk_obsdata//k5ts1/T2572227??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.22:30:46.20/chk_obsdata//k5ts2/T2572227??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.22:30:46.53/chk_obsdata//k5ts3/T2572227??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.22:30:46.87/chk_obsdata//k5ts4/T2572227??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.257.22:30:47.53/k5log//k5ts1_log_newline 2006.257.22:30:48.20/k5log//k5ts2_log_newline 2006.257.22:30:48.85/k5log//k5ts3_log_newline 2006.257.22:30:49.52/k5log//k5ts4_log_newline 2006.257.22:30:49.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.22:30:49.54:setupk4=1 2006.257.22:30:49.55$setupk4/echo=on 2006.257.22:30:49.55$setupk4/pcalon 2006.257.22:30:49.55$pcalon/"no phase cal control is implemented here 2006.257.22:30:49.55$setupk4/"tpicd=stop 2006.257.22:30:49.55$setupk4/"rec=synch_on 2006.257.22:30:49.55$setupk4/"rec_mode=128 2006.257.22:30:49.55$setupk4/!* 2006.257.22:30:49.55$setupk4/recpk4 2006.257.22:30:49.55$recpk4/recpatch= 2006.257.22:30:49.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.22:30:49.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.22:30:49.55$setupk4/vck44 2006.257.22:30:49.55$vck44/valo=1,524.99 2006.257.22:30:49.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.22:30:49.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.22:30:49.55#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:49.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:49.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:49.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:49.55#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:30:49.55#ibcon#first serial, iclass 35, count 0 2006.257.22:30:49.55#ibcon#enter sib2, iclass 35, count 0 2006.257.22:30:49.55#ibcon#flushed, iclass 35, count 0 2006.257.22:30:49.55#ibcon#about to write, iclass 35, count 0 2006.257.22:30:49.55#ibcon#wrote, iclass 35, count 0 2006.257.22:30:49.55#ibcon#about to read 3, iclass 35, count 0 2006.257.22:30:49.57#ibcon#read 3, iclass 35, count 0 2006.257.22:30:49.57#ibcon#about to read 4, iclass 35, count 0 2006.257.22:30:49.57#ibcon#read 4, iclass 35, count 0 2006.257.22:30:49.57#ibcon#about to read 5, iclass 35, count 0 2006.257.22:30:49.57#ibcon#read 5, iclass 35, count 0 2006.257.22:30:49.57#ibcon#about to read 6, iclass 35, count 0 2006.257.22:30:49.57#ibcon#read 6, iclass 35, count 0 2006.257.22:30:49.57#ibcon#end of sib2, iclass 35, count 0 2006.257.22:30:49.57#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:30:49.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:30:49.57#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.22:30:49.57#ibcon#*before write, iclass 35, count 0 2006.257.22:30:49.57#ibcon#enter sib2, iclass 35, count 0 2006.257.22:30:49.57#ibcon#flushed, iclass 35, count 0 2006.257.22:30:49.57#ibcon#about to write, iclass 35, count 0 2006.257.22:30:49.57#ibcon#wrote, iclass 35, count 0 2006.257.22:30:49.57#ibcon#about to read 3, iclass 35, count 0 2006.257.22:30:49.62#ibcon#read 3, iclass 35, count 0 2006.257.22:30:49.62#ibcon#about to read 4, iclass 35, count 0 2006.257.22:30:49.62#ibcon#read 4, iclass 35, count 0 2006.257.22:30:49.62#ibcon#about to read 5, iclass 35, count 0 2006.257.22:30:49.62#ibcon#read 5, iclass 35, count 0 2006.257.22:30:49.62#ibcon#about to read 6, iclass 35, count 0 2006.257.22:30:49.62#ibcon#read 6, iclass 35, count 0 2006.257.22:30:49.62#ibcon#end of sib2, iclass 35, count 0 2006.257.22:30:49.62#ibcon#*after write, iclass 35, count 0 2006.257.22:30:49.62#ibcon#*before return 0, iclass 35, count 0 2006.257.22:30:49.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:49.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:49.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:30:49.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:30:49.62$vck44/va=1,8 2006.257.22:30:49.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.22:30:49.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.22:30:49.62#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:49.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:49.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:49.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:49.62#ibcon#enter wrdev, iclass 37, count 2 2006.257.22:30:49.62#ibcon#first serial, iclass 37, count 2 2006.257.22:30:49.62#ibcon#enter sib2, iclass 37, count 2 2006.257.22:30:49.62#ibcon#flushed, iclass 37, count 2 2006.257.22:30:49.62#ibcon#about to write, iclass 37, count 2 2006.257.22:30:49.62#ibcon#wrote, iclass 37, count 2 2006.257.22:30:49.62#ibcon#about to read 3, iclass 37, count 2 2006.257.22:30:49.64#ibcon#read 3, iclass 37, count 2 2006.257.22:30:49.64#ibcon#about to read 4, iclass 37, count 2 2006.257.22:30:49.64#ibcon#read 4, iclass 37, count 2 2006.257.22:30:49.64#ibcon#about to read 5, iclass 37, count 2 2006.257.22:30:49.64#ibcon#read 5, iclass 37, count 2 2006.257.22:30:49.64#ibcon#about to read 6, iclass 37, count 2 2006.257.22:30:49.64#ibcon#read 6, iclass 37, count 2 2006.257.22:30:49.64#ibcon#end of sib2, iclass 37, count 2 2006.257.22:30:49.64#ibcon#*mode == 0, iclass 37, count 2 2006.257.22:30:49.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.22:30:49.64#ibcon#[25=AT01-08\r\n] 2006.257.22:30:49.64#ibcon#*before write, iclass 37, count 2 2006.257.22:30:49.64#ibcon#enter sib2, iclass 37, count 2 2006.257.22:30:49.64#ibcon#flushed, iclass 37, count 2 2006.257.22:30:49.64#ibcon#about to write, iclass 37, count 2 2006.257.22:30:49.64#ibcon#wrote, iclass 37, count 2 2006.257.22:30:49.64#ibcon#about to read 3, iclass 37, count 2 2006.257.22:30:49.67#ibcon#read 3, iclass 37, count 2 2006.257.22:30:49.67#ibcon#about to read 4, iclass 37, count 2 2006.257.22:30:49.67#ibcon#read 4, iclass 37, count 2 2006.257.22:30:49.67#ibcon#about to read 5, iclass 37, count 2 2006.257.22:30:49.67#ibcon#read 5, iclass 37, count 2 2006.257.22:30:49.67#ibcon#about to read 6, iclass 37, count 2 2006.257.22:30:49.67#ibcon#read 6, iclass 37, count 2 2006.257.22:30:49.67#ibcon#end of sib2, iclass 37, count 2 2006.257.22:30:49.67#ibcon#*after write, iclass 37, count 2 2006.257.22:30:49.67#ibcon#*before return 0, iclass 37, count 2 2006.257.22:30:49.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:49.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:49.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.22:30:49.67#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:49.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:49.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:49.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:49.79#ibcon#enter wrdev, iclass 37, count 0 2006.257.22:30:49.79#ibcon#first serial, iclass 37, count 0 2006.257.22:30:49.79#ibcon#enter sib2, iclass 37, count 0 2006.257.22:30:49.79#ibcon#flushed, iclass 37, count 0 2006.257.22:30:49.79#ibcon#about to write, iclass 37, count 0 2006.257.22:30:49.79#ibcon#wrote, iclass 37, count 0 2006.257.22:30:49.79#ibcon#about to read 3, iclass 37, count 0 2006.257.22:30:49.81#ibcon#read 3, iclass 37, count 0 2006.257.22:30:49.81#ibcon#about to read 4, iclass 37, count 0 2006.257.22:30:49.81#ibcon#read 4, iclass 37, count 0 2006.257.22:30:49.81#ibcon#about to read 5, iclass 37, count 0 2006.257.22:30:49.81#ibcon#read 5, iclass 37, count 0 2006.257.22:30:49.81#ibcon#about to read 6, iclass 37, count 0 2006.257.22:30:49.81#ibcon#read 6, iclass 37, count 0 2006.257.22:30:49.81#ibcon#end of sib2, iclass 37, count 0 2006.257.22:30:49.81#ibcon#*mode == 0, iclass 37, count 0 2006.257.22:30:49.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.22:30:49.81#ibcon#[25=USB\r\n] 2006.257.22:30:49.81#ibcon#*before write, iclass 37, count 0 2006.257.22:30:49.81#ibcon#enter sib2, iclass 37, count 0 2006.257.22:30:49.81#ibcon#flushed, iclass 37, count 0 2006.257.22:30:49.81#ibcon#about to write, iclass 37, count 0 2006.257.22:30:49.81#ibcon#wrote, iclass 37, count 0 2006.257.22:30:49.81#ibcon#about to read 3, iclass 37, count 0 2006.257.22:30:49.84#ibcon#read 3, iclass 37, count 0 2006.257.22:30:49.84#ibcon#about to read 4, iclass 37, count 0 2006.257.22:30:49.84#ibcon#read 4, iclass 37, count 0 2006.257.22:30:49.84#ibcon#about to read 5, iclass 37, count 0 2006.257.22:30:49.84#ibcon#read 5, iclass 37, count 0 2006.257.22:30:49.84#ibcon#about to read 6, iclass 37, count 0 2006.257.22:30:49.84#ibcon#read 6, iclass 37, count 0 2006.257.22:30:49.84#ibcon#end of sib2, iclass 37, count 0 2006.257.22:30:49.84#ibcon#*after write, iclass 37, count 0 2006.257.22:30:49.84#ibcon#*before return 0, iclass 37, count 0 2006.257.22:30:49.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:49.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:49.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.22:30:49.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.22:30:49.84$vck44/valo=2,534.99 2006.257.22:30:49.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.22:30:49.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.22:30:49.84#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:49.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:49.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:49.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:49.84#ibcon#enter wrdev, iclass 39, count 0 2006.257.22:30:49.84#ibcon#first serial, iclass 39, count 0 2006.257.22:30:49.84#ibcon#enter sib2, iclass 39, count 0 2006.257.22:30:49.84#ibcon#flushed, iclass 39, count 0 2006.257.22:30:49.84#ibcon#about to write, iclass 39, count 0 2006.257.22:30:49.84#ibcon#wrote, iclass 39, count 0 2006.257.22:30:49.84#ibcon#about to read 3, iclass 39, count 0 2006.257.22:30:49.86#ibcon#read 3, iclass 39, count 0 2006.257.22:30:49.86#ibcon#about to read 4, iclass 39, count 0 2006.257.22:30:49.86#ibcon#read 4, iclass 39, count 0 2006.257.22:30:49.86#ibcon#about to read 5, iclass 39, count 0 2006.257.22:30:49.86#ibcon#read 5, iclass 39, count 0 2006.257.22:30:49.86#ibcon#about to read 6, iclass 39, count 0 2006.257.22:30:49.86#ibcon#read 6, iclass 39, count 0 2006.257.22:30:49.86#ibcon#end of sib2, iclass 39, count 0 2006.257.22:30:49.86#ibcon#*mode == 0, iclass 39, count 0 2006.257.22:30:49.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.22:30:49.86#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.22:30:49.86#ibcon#*before write, iclass 39, count 0 2006.257.22:30:49.86#ibcon#enter sib2, iclass 39, count 0 2006.257.22:30:49.86#ibcon#flushed, iclass 39, count 0 2006.257.22:30:49.86#ibcon#about to write, iclass 39, count 0 2006.257.22:30:49.86#ibcon#wrote, iclass 39, count 0 2006.257.22:30:49.86#ibcon#about to read 3, iclass 39, count 0 2006.257.22:30:49.90#ibcon#read 3, iclass 39, count 0 2006.257.22:30:49.90#ibcon#about to read 4, iclass 39, count 0 2006.257.22:30:49.90#ibcon#read 4, iclass 39, count 0 2006.257.22:30:49.90#ibcon#about to read 5, iclass 39, count 0 2006.257.22:30:49.90#ibcon#read 5, iclass 39, count 0 2006.257.22:30:49.90#ibcon#about to read 6, iclass 39, count 0 2006.257.22:30:49.90#ibcon#read 6, iclass 39, count 0 2006.257.22:30:49.90#ibcon#end of sib2, iclass 39, count 0 2006.257.22:30:49.90#ibcon#*after write, iclass 39, count 0 2006.257.22:30:49.90#ibcon#*before return 0, iclass 39, count 0 2006.257.22:30:49.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:49.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:49.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.22:30:49.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.22:30:49.90$vck44/va=2,7 2006.257.22:30:49.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.22:30:49.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.22:30:49.90#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:49.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:49.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:49.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:49.96#ibcon#enter wrdev, iclass 3, count 2 2006.257.22:30:49.96#ibcon#first serial, iclass 3, count 2 2006.257.22:30:49.96#ibcon#enter sib2, iclass 3, count 2 2006.257.22:30:49.96#ibcon#flushed, iclass 3, count 2 2006.257.22:30:49.96#ibcon#about to write, iclass 3, count 2 2006.257.22:30:49.96#ibcon#wrote, iclass 3, count 2 2006.257.22:30:49.96#ibcon#about to read 3, iclass 3, count 2 2006.257.22:30:49.98#ibcon#read 3, iclass 3, count 2 2006.257.22:30:49.98#ibcon#about to read 4, iclass 3, count 2 2006.257.22:30:49.98#ibcon#read 4, iclass 3, count 2 2006.257.22:30:49.98#ibcon#about to read 5, iclass 3, count 2 2006.257.22:30:49.98#ibcon#read 5, iclass 3, count 2 2006.257.22:30:49.98#ibcon#about to read 6, iclass 3, count 2 2006.257.22:30:49.98#ibcon#read 6, iclass 3, count 2 2006.257.22:30:49.98#ibcon#end of sib2, iclass 3, count 2 2006.257.22:30:49.98#ibcon#*mode == 0, iclass 3, count 2 2006.257.22:30:49.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.22:30:49.98#ibcon#[25=AT02-07\r\n] 2006.257.22:30:49.98#ibcon#*before write, iclass 3, count 2 2006.257.22:30:49.98#ibcon#enter sib2, iclass 3, count 2 2006.257.22:30:49.98#ibcon#flushed, iclass 3, count 2 2006.257.22:30:49.98#ibcon#about to write, iclass 3, count 2 2006.257.22:30:49.98#ibcon#wrote, iclass 3, count 2 2006.257.22:30:49.98#ibcon#about to read 3, iclass 3, count 2 2006.257.22:30:50.01#ibcon#read 3, iclass 3, count 2 2006.257.22:30:50.01#ibcon#about to read 4, iclass 3, count 2 2006.257.22:30:50.01#ibcon#read 4, iclass 3, count 2 2006.257.22:30:50.01#ibcon#about to read 5, iclass 3, count 2 2006.257.22:30:50.01#ibcon#read 5, iclass 3, count 2 2006.257.22:30:50.01#ibcon#about to read 6, iclass 3, count 2 2006.257.22:30:50.01#ibcon#read 6, iclass 3, count 2 2006.257.22:30:50.01#ibcon#end of sib2, iclass 3, count 2 2006.257.22:30:50.01#ibcon#*after write, iclass 3, count 2 2006.257.22:30:50.01#ibcon#*before return 0, iclass 3, count 2 2006.257.22:30:50.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:50.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:50.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.22:30:50.01#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:50.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:50.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:50.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:50.13#ibcon#enter wrdev, iclass 3, count 0 2006.257.22:30:50.13#ibcon#first serial, iclass 3, count 0 2006.257.22:30:50.13#ibcon#enter sib2, iclass 3, count 0 2006.257.22:30:50.13#ibcon#flushed, iclass 3, count 0 2006.257.22:30:50.13#ibcon#about to write, iclass 3, count 0 2006.257.22:30:50.13#ibcon#wrote, iclass 3, count 0 2006.257.22:30:50.13#ibcon#about to read 3, iclass 3, count 0 2006.257.22:30:50.15#ibcon#read 3, iclass 3, count 0 2006.257.22:30:50.15#ibcon#about to read 4, iclass 3, count 0 2006.257.22:30:50.15#ibcon#read 4, iclass 3, count 0 2006.257.22:30:50.15#ibcon#about to read 5, iclass 3, count 0 2006.257.22:30:50.15#ibcon#read 5, iclass 3, count 0 2006.257.22:30:50.15#ibcon#about to read 6, iclass 3, count 0 2006.257.22:30:50.15#ibcon#read 6, iclass 3, count 0 2006.257.22:30:50.15#ibcon#end of sib2, iclass 3, count 0 2006.257.22:30:50.15#ibcon#*mode == 0, iclass 3, count 0 2006.257.22:30:50.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.22:30:50.15#ibcon#[25=USB\r\n] 2006.257.22:30:50.15#ibcon#*before write, iclass 3, count 0 2006.257.22:30:50.15#ibcon#enter sib2, iclass 3, count 0 2006.257.22:30:50.15#ibcon#flushed, iclass 3, count 0 2006.257.22:30:50.15#ibcon#about to write, iclass 3, count 0 2006.257.22:30:50.15#ibcon#wrote, iclass 3, count 0 2006.257.22:30:50.15#ibcon#about to read 3, iclass 3, count 0 2006.257.22:30:50.18#ibcon#read 3, iclass 3, count 0 2006.257.22:30:50.18#ibcon#about to read 4, iclass 3, count 0 2006.257.22:30:50.18#ibcon#read 4, iclass 3, count 0 2006.257.22:30:50.18#ibcon#about to read 5, iclass 3, count 0 2006.257.22:30:50.18#ibcon#read 5, iclass 3, count 0 2006.257.22:30:50.18#ibcon#about to read 6, iclass 3, count 0 2006.257.22:30:50.18#ibcon#read 6, iclass 3, count 0 2006.257.22:30:50.18#ibcon#end of sib2, iclass 3, count 0 2006.257.22:30:50.18#ibcon#*after write, iclass 3, count 0 2006.257.22:30:50.18#ibcon#*before return 0, iclass 3, count 0 2006.257.22:30:50.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:50.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:50.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.22:30:50.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.22:30:50.18$vck44/valo=3,564.99 2006.257.22:30:50.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.22:30:50.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.22:30:50.18#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:50.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:50.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:50.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:50.18#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:30:50.18#ibcon#first serial, iclass 5, count 0 2006.257.22:30:50.18#ibcon#enter sib2, iclass 5, count 0 2006.257.22:30:50.18#ibcon#flushed, iclass 5, count 0 2006.257.22:30:50.18#ibcon#about to write, iclass 5, count 0 2006.257.22:30:50.18#ibcon#wrote, iclass 5, count 0 2006.257.22:30:50.18#ibcon#about to read 3, iclass 5, count 0 2006.257.22:30:50.20#ibcon#read 3, iclass 5, count 0 2006.257.22:30:50.20#ibcon#about to read 4, iclass 5, count 0 2006.257.22:30:50.20#ibcon#read 4, iclass 5, count 0 2006.257.22:30:50.20#ibcon#about to read 5, iclass 5, count 0 2006.257.22:30:50.20#ibcon#read 5, iclass 5, count 0 2006.257.22:30:50.20#ibcon#about to read 6, iclass 5, count 0 2006.257.22:30:50.20#ibcon#read 6, iclass 5, count 0 2006.257.22:30:50.20#ibcon#end of sib2, iclass 5, count 0 2006.257.22:30:50.20#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:30:50.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:30:50.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.22:30:50.20#ibcon#*before write, iclass 5, count 0 2006.257.22:30:50.20#ibcon#enter sib2, iclass 5, count 0 2006.257.22:30:50.20#ibcon#flushed, iclass 5, count 0 2006.257.22:30:50.20#ibcon#about to write, iclass 5, count 0 2006.257.22:30:50.20#ibcon#wrote, iclass 5, count 0 2006.257.22:30:50.20#ibcon#about to read 3, iclass 5, count 0 2006.257.22:30:50.24#ibcon#read 3, iclass 5, count 0 2006.257.22:30:50.24#ibcon#about to read 4, iclass 5, count 0 2006.257.22:30:50.24#ibcon#read 4, iclass 5, count 0 2006.257.22:30:50.24#ibcon#about to read 5, iclass 5, count 0 2006.257.22:30:50.24#ibcon#read 5, iclass 5, count 0 2006.257.22:30:50.24#ibcon#about to read 6, iclass 5, count 0 2006.257.22:30:50.24#ibcon#read 6, iclass 5, count 0 2006.257.22:30:50.24#ibcon#end of sib2, iclass 5, count 0 2006.257.22:30:50.24#ibcon#*after write, iclass 5, count 0 2006.257.22:30:50.24#ibcon#*before return 0, iclass 5, count 0 2006.257.22:30:50.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:50.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:50.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:30:50.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:30:50.24$vck44/va=3,8 2006.257.22:30:50.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.22:30:50.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.22:30:50.24#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:50.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:50.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:50.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:50.30#ibcon#enter wrdev, iclass 7, count 2 2006.257.22:30:50.30#ibcon#first serial, iclass 7, count 2 2006.257.22:30:50.30#ibcon#enter sib2, iclass 7, count 2 2006.257.22:30:50.30#ibcon#flushed, iclass 7, count 2 2006.257.22:30:50.30#ibcon#about to write, iclass 7, count 2 2006.257.22:30:50.30#ibcon#wrote, iclass 7, count 2 2006.257.22:30:50.30#ibcon#about to read 3, iclass 7, count 2 2006.257.22:30:50.32#ibcon#read 3, iclass 7, count 2 2006.257.22:30:50.32#ibcon#about to read 4, iclass 7, count 2 2006.257.22:30:50.32#ibcon#read 4, iclass 7, count 2 2006.257.22:30:50.32#ibcon#about to read 5, iclass 7, count 2 2006.257.22:30:50.32#ibcon#read 5, iclass 7, count 2 2006.257.22:30:50.32#ibcon#about to read 6, iclass 7, count 2 2006.257.22:30:50.32#ibcon#read 6, iclass 7, count 2 2006.257.22:30:50.32#ibcon#end of sib2, iclass 7, count 2 2006.257.22:30:50.32#ibcon#*mode == 0, iclass 7, count 2 2006.257.22:30:50.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.22:30:50.32#ibcon#[25=AT03-08\r\n] 2006.257.22:30:50.32#ibcon#*before write, iclass 7, count 2 2006.257.22:30:50.32#ibcon#enter sib2, iclass 7, count 2 2006.257.22:30:50.32#ibcon#flushed, iclass 7, count 2 2006.257.22:30:50.32#ibcon#about to write, iclass 7, count 2 2006.257.22:30:50.32#ibcon#wrote, iclass 7, count 2 2006.257.22:30:50.32#ibcon#about to read 3, iclass 7, count 2 2006.257.22:30:50.35#ibcon#read 3, iclass 7, count 2 2006.257.22:30:50.35#ibcon#about to read 4, iclass 7, count 2 2006.257.22:30:50.35#ibcon#read 4, iclass 7, count 2 2006.257.22:30:50.35#ibcon#about to read 5, iclass 7, count 2 2006.257.22:30:50.35#ibcon#read 5, iclass 7, count 2 2006.257.22:30:50.35#ibcon#about to read 6, iclass 7, count 2 2006.257.22:30:50.35#ibcon#read 6, iclass 7, count 2 2006.257.22:30:50.35#ibcon#end of sib2, iclass 7, count 2 2006.257.22:30:50.35#ibcon#*after write, iclass 7, count 2 2006.257.22:30:50.35#ibcon#*before return 0, iclass 7, count 2 2006.257.22:30:50.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:50.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:50.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.22:30:50.35#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:50.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:50.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:50.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:50.47#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:30:50.47#ibcon#first serial, iclass 7, count 0 2006.257.22:30:50.47#ibcon#enter sib2, iclass 7, count 0 2006.257.22:30:50.47#ibcon#flushed, iclass 7, count 0 2006.257.22:30:50.47#ibcon#about to write, iclass 7, count 0 2006.257.22:30:50.47#ibcon#wrote, iclass 7, count 0 2006.257.22:30:50.47#ibcon#about to read 3, iclass 7, count 0 2006.257.22:30:50.49#ibcon#read 3, iclass 7, count 0 2006.257.22:30:50.49#ibcon#about to read 4, iclass 7, count 0 2006.257.22:30:50.49#ibcon#read 4, iclass 7, count 0 2006.257.22:30:50.49#ibcon#about to read 5, iclass 7, count 0 2006.257.22:30:50.49#ibcon#read 5, iclass 7, count 0 2006.257.22:30:50.49#ibcon#about to read 6, iclass 7, count 0 2006.257.22:30:50.49#ibcon#read 6, iclass 7, count 0 2006.257.22:30:50.49#ibcon#end of sib2, iclass 7, count 0 2006.257.22:30:50.49#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:30:50.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:30:50.49#ibcon#[25=USB\r\n] 2006.257.22:30:50.49#ibcon#*before write, iclass 7, count 0 2006.257.22:30:50.49#ibcon#enter sib2, iclass 7, count 0 2006.257.22:30:50.49#ibcon#flushed, iclass 7, count 0 2006.257.22:30:50.49#ibcon#about to write, iclass 7, count 0 2006.257.22:30:50.49#ibcon#wrote, iclass 7, count 0 2006.257.22:30:50.49#ibcon#about to read 3, iclass 7, count 0 2006.257.22:30:50.52#ibcon#read 3, iclass 7, count 0 2006.257.22:30:50.52#ibcon#about to read 4, iclass 7, count 0 2006.257.22:30:50.52#ibcon#read 4, iclass 7, count 0 2006.257.22:30:50.52#ibcon#about to read 5, iclass 7, count 0 2006.257.22:30:50.52#ibcon#read 5, iclass 7, count 0 2006.257.22:30:50.52#ibcon#about to read 6, iclass 7, count 0 2006.257.22:30:50.52#ibcon#read 6, iclass 7, count 0 2006.257.22:30:50.52#ibcon#end of sib2, iclass 7, count 0 2006.257.22:30:50.52#ibcon#*after write, iclass 7, count 0 2006.257.22:30:50.52#ibcon#*before return 0, iclass 7, count 0 2006.257.22:30:50.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:50.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:50.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:30:50.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:30:50.52$vck44/valo=4,624.99 2006.257.22:30:50.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.22:30:50.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.22:30:50.52#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:50.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:50.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:50.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:50.52#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:30:50.52#ibcon#first serial, iclass 11, count 0 2006.257.22:30:50.52#ibcon#enter sib2, iclass 11, count 0 2006.257.22:30:50.52#ibcon#flushed, iclass 11, count 0 2006.257.22:30:50.52#ibcon#about to write, iclass 11, count 0 2006.257.22:30:50.52#ibcon#wrote, iclass 11, count 0 2006.257.22:30:50.52#ibcon#about to read 3, iclass 11, count 0 2006.257.22:30:50.54#ibcon#read 3, iclass 11, count 0 2006.257.22:30:50.54#ibcon#about to read 4, iclass 11, count 0 2006.257.22:30:50.54#ibcon#read 4, iclass 11, count 0 2006.257.22:30:50.54#ibcon#about to read 5, iclass 11, count 0 2006.257.22:30:50.54#ibcon#read 5, iclass 11, count 0 2006.257.22:30:50.54#ibcon#about to read 6, iclass 11, count 0 2006.257.22:30:50.54#ibcon#read 6, iclass 11, count 0 2006.257.22:30:50.54#ibcon#end of sib2, iclass 11, count 0 2006.257.22:30:50.54#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:30:50.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:30:50.54#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.22:30:50.54#ibcon#*before write, iclass 11, count 0 2006.257.22:30:50.54#ibcon#enter sib2, iclass 11, count 0 2006.257.22:30:50.54#ibcon#flushed, iclass 11, count 0 2006.257.22:30:50.54#ibcon#about to write, iclass 11, count 0 2006.257.22:30:50.54#ibcon#wrote, iclass 11, count 0 2006.257.22:30:50.54#ibcon#about to read 3, iclass 11, count 0 2006.257.22:30:50.58#ibcon#read 3, iclass 11, count 0 2006.257.22:30:50.58#ibcon#about to read 4, iclass 11, count 0 2006.257.22:30:50.58#ibcon#read 4, iclass 11, count 0 2006.257.22:30:50.58#ibcon#about to read 5, iclass 11, count 0 2006.257.22:30:50.58#ibcon#read 5, iclass 11, count 0 2006.257.22:30:50.58#ibcon#about to read 6, iclass 11, count 0 2006.257.22:30:50.58#ibcon#read 6, iclass 11, count 0 2006.257.22:30:50.58#ibcon#end of sib2, iclass 11, count 0 2006.257.22:30:50.58#ibcon#*after write, iclass 11, count 0 2006.257.22:30:50.58#ibcon#*before return 0, iclass 11, count 0 2006.257.22:30:50.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:50.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:50.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:30:50.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:30:50.58$vck44/va=4,7 2006.257.22:30:50.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.22:30:50.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.22:30:50.58#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:50.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:50.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:50.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:50.64#ibcon#enter wrdev, iclass 13, count 2 2006.257.22:30:50.64#ibcon#first serial, iclass 13, count 2 2006.257.22:30:50.64#ibcon#enter sib2, iclass 13, count 2 2006.257.22:30:50.64#ibcon#flushed, iclass 13, count 2 2006.257.22:30:50.64#ibcon#about to write, iclass 13, count 2 2006.257.22:30:50.64#ibcon#wrote, iclass 13, count 2 2006.257.22:30:50.64#ibcon#about to read 3, iclass 13, count 2 2006.257.22:30:50.66#ibcon#read 3, iclass 13, count 2 2006.257.22:30:50.66#ibcon#about to read 4, iclass 13, count 2 2006.257.22:30:50.66#ibcon#read 4, iclass 13, count 2 2006.257.22:30:50.66#ibcon#about to read 5, iclass 13, count 2 2006.257.22:30:50.66#ibcon#read 5, iclass 13, count 2 2006.257.22:30:50.66#ibcon#about to read 6, iclass 13, count 2 2006.257.22:30:50.66#ibcon#read 6, iclass 13, count 2 2006.257.22:30:50.66#ibcon#end of sib2, iclass 13, count 2 2006.257.22:30:50.66#ibcon#*mode == 0, iclass 13, count 2 2006.257.22:30:50.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.22:30:50.66#ibcon#[25=AT04-07\r\n] 2006.257.22:30:50.66#ibcon#*before write, iclass 13, count 2 2006.257.22:30:50.66#ibcon#enter sib2, iclass 13, count 2 2006.257.22:30:50.66#ibcon#flushed, iclass 13, count 2 2006.257.22:30:50.66#ibcon#about to write, iclass 13, count 2 2006.257.22:30:50.66#ibcon#wrote, iclass 13, count 2 2006.257.22:30:50.66#ibcon#about to read 3, iclass 13, count 2 2006.257.22:30:50.69#ibcon#read 3, iclass 13, count 2 2006.257.22:30:50.69#ibcon#about to read 4, iclass 13, count 2 2006.257.22:30:50.69#ibcon#read 4, iclass 13, count 2 2006.257.22:30:50.69#ibcon#about to read 5, iclass 13, count 2 2006.257.22:30:50.69#ibcon#read 5, iclass 13, count 2 2006.257.22:30:50.69#ibcon#about to read 6, iclass 13, count 2 2006.257.22:30:50.69#ibcon#read 6, iclass 13, count 2 2006.257.22:30:50.69#ibcon#end of sib2, iclass 13, count 2 2006.257.22:30:50.69#ibcon#*after write, iclass 13, count 2 2006.257.22:30:50.69#ibcon#*before return 0, iclass 13, count 2 2006.257.22:30:50.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:50.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:50.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.22:30:50.69#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:50.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:50.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:50.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:50.81#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:30:50.81#ibcon#first serial, iclass 13, count 0 2006.257.22:30:50.81#ibcon#enter sib2, iclass 13, count 0 2006.257.22:30:50.81#ibcon#flushed, iclass 13, count 0 2006.257.22:30:50.81#ibcon#about to write, iclass 13, count 0 2006.257.22:30:50.81#ibcon#wrote, iclass 13, count 0 2006.257.22:30:50.81#ibcon#about to read 3, iclass 13, count 0 2006.257.22:30:50.83#ibcon#read 3, iclass 13, count 0 2006.257.22:30:50.83#ibcon#about to read 4, iclass 13, count 0 2006.257.22:30:50.83#ibcon#read 4, iclass 13, count 0 2006.257.22:30:50.83#ibcon#about to read 5, iclass 13, count 0 2006.257.22:30:50.83#ibcon#read 5, iclass 13, count 0 2006.257.22:30:50.83#ibcon#about to read 6, iclass 13, count 0 2006.257.22:30:50.83#ibcon#read 6, iclass 13, count 0 2006.257.22:30:50.83#ibcon#end of sib2, iclass 13, count 0 2006.257.22:30:50.83#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:30:50.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:30:50.83#ibcon#[25=USB\r\n] 2006.257.22:30:50.83#ibcon#*before write, iclass 13, count 0 2006.257.22:30:50.83#ibcon#enter sib2, iclass 13, count 0 2006.257.22:30:50.83#ibcon#flushed, iclass 13, count 0 2006.257.22:30:50.83#ibcon#about to write, iclass 13, count 0 2006.257.22:30:50.83#ibcon#wrote, iclass 13, count 0 2006.257.22:30:50.83#ibcon#about to read 3, iclass 13, count 0 2006.257.22:30:50.86#ibcon#read 3, iclass 13, count 0 2006.257.22:30:50.86#ibcon#about to read 4, iclass 13, count 0 2006.257.22:30:50.86#ibcon#read 4, iclass 13, count 0 2006.257.22:30:50.86#ibcon#about to read 5, iclass 13, count 0 2006.257.22:30:50.86#ibcon#read 5, iclass 13, count 0 2006.257.22:30:50.86#ibcon#about to read 6, iclass 13, count 0 2006.257.22:30:50.86#ibcon#read 6, iclass 13, count 0 2006.257.22:30:50.86#ibcon#end of sib2, iclass 13, count 0 2006.257.22:30:50.86#ibcon#*after write, iclass 13, count 0 2006.257.22:30:50.86#ibcon#*before return 0, iclass 13, count 0 2006.257.22:30:50.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:50.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:50.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:30:50.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:30:50.86$vck44/valo=5,734.99 2006.257.22:30:50.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.22:30:50.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.22:30:50.86#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:50.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:50.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:50.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:50.86#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:30:50.86#ibcon#first serial, iclass 15, count 0 2006.257.22:30:50.86#ibcon#enter sib2, iclass 15, count 0 2006.257.22:30:50.86#ibcon#flushed, iclass 15, count 0 2006.257.22:30:50.86#ibcon#about to write, iclass 15, count 0 2006.257.22:30:50.86#ibcon#wrote, iclass 15, count 0 2006.257.22:30:50.86#ibcon#about to read 3, iclass 15, count 0 2006.257.22:30:50.88#ibcon#read 3, iclass 15, count 0 2006.257.22:30:50.88#ibcon#about to read 4, iclass 15, count 0 2006.257.22:30:50.88#ibcon#read 4, iclass 15, count 0 2006.257.22:30:50.88#ibcon#about to read 5, iclass 15, count 0 2006.257.22:30:50.88#ibcon#read 5, iclass 15, count 0 2006.257.22:30:50.88#ibcon#about to read 6, iclass 15, count 0 2006.257.22:30:50.88#ibcon#read 6, iclass 15, count 0 2006.257.22:30:50.88#ibcon#end of sib2, iclass 15, count 0 2006.257.22:30:50.88#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:30:50.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:30:50.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.22:30:50.88#ibcon#*before write, iclass 15, count 0 2006.257.22:30:50.88#ibcon#enter sib2, iclass 15, count 0 2006.257.22:30:50.88#ibcon#flushed, iclass 15, count 0 2006.257.22:30:50.88#ibcon#about to write, iclass 15, count 0 2006.257.22:30:50.88#ibcon#wrote, iclass 15, count 0 2006.257.22:30:50.88#ibcon#about to read 3, iclass 15, count 0 2006.257.22:30:50.92#ibcon#read 3, iclass 15, count 0 2006.257.22:30:50.92#ibcon#about to read 4, iclass 15, count 0 2006.257.22:30:50.92#ibcon#read 4, iclass 15, count 0 2006.257.22:30:50.92#ibcon#about to read 5, iclass 15, count 0 2006.257.22:30:50.92#ibcon#read 5, iclass 15, count 0 2006.257.22:30:50.92#ibcon#about to read 6, iclass 15, count 0 2006.257.22:30:50.92#ibcon#read 6, iclass 15, count 0 2006.257.22:30:50.92#ibcon#end of sib2, iclass 15, count 0 2006.257.22:30:50.92#ibcon#*after write, iclass 15, count 0 2006.257.22:30:50.92#ibcon#*before return 0, iclass 15, count 0 2006.257.22:30:50.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:50.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:50.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:30:50.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:30:50.92$vck44/va=5,4 2006.257.22:30:50.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.22:30:50.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.22:30:50.92#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:50.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:50.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:50.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:50.98#ibcon#enter wrdev, iclass 17, count 2 2006.257.22:30:50.98#ibcon#first serial, iclass 17, count 2 2006.257.22:30:50.98#ibcon#enter sib2, iclass 17, count 2 2006.257.22:30:50.98#ibcon#flushed, iclass 17, count 2 2006.257.22:30:50.98#ibcon#about to write, iclass 17, count 2 2006.257.22:30:50.98#ibcon#wrote, iclass 17, count 2 2006.257.22:30:50.98#ibcon#about to read 3, iclass 17, count 2 2006.257.22:30:51.00#ibcon#read 3, iclass 17, count 2 2006.257.22:30:51.00#ibcon#about to read 4, iclass 17, count 2 2006.257.22:30:51.00#ibcon#read 4, iclass 17, count 2 2006.257.22:30:51.00#ibcon#about to read 5, iclass 17, count 2 2006.257.22:30:51.00#ibcon#read 5, iclass 17, count 2 2006.257.22:30:51.00#ibcon#about to read 6, iclass 17, count 2 2006.257.22:30:51.00#ibcon#read 6, iclass 17, count 2 2006.257.22:30:51.00#ibcon#end of sib2, iclass 17, count 2 2006.257.22:30:51.00#ibcon#*mode == 0, iclass 17, count 2 2006.257.22:30:51.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.22:30:51.00#ibcon#[25=AT05-04\r\n] 2006.257.22:30:51.00#ibcon#*before write, iclass 17, count 2 2006.257.22:30:51.00#ibcon#enter sib2, iclass 17, count 2 2006.257.22:30:51.00#ibcon#flushed, iclass 17, count 2 2006.257.22:30:51.00#ibcon#about to write, iclass 17, count 2 2006.257.22:30:51.00#ibcon#wrote, iclass 17, count 2 2006.257.22:30:51.00#ibcon#about to read 3, iclass 17, count 2 2006.257.22:30:51.03#ibcon#read 3, iclass 17, count 2 2006.257.22:30:51.03#ibcon#about to read 4, iclass 17, count 2 2006.257.22:30:51.03#ibcon#read 4, iclass 17, count 2 2006.257.22:30:51.03#ibcon#about to read 5, iclass 17, count 2 2006.257.22:30:51.03#ibcon#read 5, iclass 17, count 2 2006.257.22:30:51.03#ibcon#about to read 6, iclass 17, count 2 2006.257.22:30:51.03#ibcon#read 6, iclass 17, count 2 2006.257.22:30:51.03#ibcon#end of sib2, iclass 17, count 2 2006.257.22:30:51.03#ibcon#*after write, iclass 17, count 2 2006.257.22:30:51.03#ibcon#*before return 0, iclass 17, count 2 2006.257.22:30:51.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:51.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:51.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.22:30:51.03#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:51.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:51.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:51.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:51.15#ibcon#enter wrdev, iclass 17, count 0 2006.257.22:30:51.15#ibcon#first serial, iclass 17, count 0 2006.257.22:30:51.15#ibcon#enter sib2, iclass 17, count 0 2006.257.22:30:51.15#ibcon#flushed, iclass 17, count 0 2006.257.22:30:51.15#ibcon#about to write, iclass 17, count 0 2006.257.22:30:51.15#ibcon#wrote, iclass 17, count 0 2006.257.22:30:51.15#ibcon#about to read 3, iclass 17, count 0 2006.257.22:30:51.17#ibcon#read 3, iclass 17, count 0 2006.257.22:30:51.17#ibcon#about to read 4, iclass 17, count 0 2006.257.22:30:51.17#ibcon#read 4, iclass 17, count 0 2006.257.22:30:51.17#ibcon#about to read 5, iclass 17, count 0 2006.257.22:30:51.17#ibcon#read 5, iclass 17, count 0 2006.257.22:30:51.17#ibcon#about to read 6, iclass 17, count 0 2006.257.22:30:51.17#ibcon#read 6, iclass 17, count 0 2006.257.22:30:51.17#ibcon#end of sib2, iclass 17, count 0 2006.257.22:30:51.17#ibcon#*mode == 0, iclass 17, count 0 2006.257.22:30:51.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.22:30:51.17#ibcon#[25=USB\r\n] 2006.257.22:30:51.17#ibcon#*before write, iclass 17, count 0 2006.257.22:30:51.17#ibcon#enter sib2, iclass 17, count 0 2006.257.22:30:51.17#ibcon#flushed, iclass 17, count 0 2006.257.22:30:51.17#ibcon#about to write, iclass 17, count 0 2006.257.22:30:51.17#ibcon#wrote, iclass 17, count 0 2006.257.22:30:51.17#ibcon#about to read 3, iclass 17, count 0 2006.257.22:30:51.20#ibcon#read 3, iclass 17, count 0 2006.257.22:30:51.20#ibcon#about to read 4, iclass 17, count 0 2006.257.22:30:51.20#ibcon#read 4, iclass 17, count 0 2006.257.22:30:51.20#ibcon#about to read 5, iclass 17, count 0 2006.257.22:30:51.20#ibcon#read 5, iclass 17, count 0 2006.257.22:30:51.20#ibcon#about to read 6, iclass 17, count 0 2006.257.22:30:51.20#ibcon#read 6, iclass 17, count 0 2006.257.22:30:51.20#ibcon#end of sib2, iclass 17, count 0 2006.257.22:30:51.20#ibcon#*after write, iclass 17, count 0 2006.257.22:30:51.20#ibcon#*before return 0, iclass 17, count 0 2006.257.22:30:51.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:51.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:51.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.22:30:51.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.22:30:51.20$vck44/valo=6,814.99 2006.257.22:30:51.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.22:30:51.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.22:30:51.20#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:51.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:51.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:51.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:51.20#ibcon#enter wrdev, iclass 19, count 0 2006.257.22:30:51.20#ibcon#first serial, iclass 19, count 0 2006.257.22:30:51.20#ibcon#enter sib2, iclass 19, count 0 2006.257.22:30:51.20#ibcon#flushed, iclass 19, count 0 2006.257.22:30:51.20#ibcon#about to write, iclass 19, count 0 2006.257.22:30:51.20#ibcon#wrote, iclass 19, count 0 2006.257.22:30:51.20#ibcon#about to read 3, iclass 19, count 0 2006.257.22:30:51.22#ibcon#read 3, iclass 19, count 0 2006.257.22:30:51.22#ibcon#about to read 4, iclass 19, count 0 2006.257.22:30:51.22#ibcon#read 4, iclass 19, count 0 2006.257.22:30:51.22#ibcon#about to read 5, iclass 19, count 0 2006.257.22:30:51.22#ibcon#read 5, iclass 19, count 0 2006.257.22:30:51.22#ibcon#about to read 6, iclass 19, count 0 2006.257.22:30:51.22#ibcon#read 6, iclass 19, count 0 2006.257.22:30:51.22#ibcon#end of sib2, iclass 19, count 0 2006.257.22:30:51.22#ibcon#*mode == 0, iclass 19, count 0 2006.257.22:30:51.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.22:30:51.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.22:30:51.22#ibcon#*before write, iclass 19, count 0 2006.257.22:30:51.22#ibcon#enter sib2, iclass 19, count 0 2006.257.22:30:51.22#ibcon#flushed, iclass 19, count 0 2006.257.22:30:51.22#ibcon#about to write, iclass 19, count 0 2006.257.22:30:51.22#ibcon#wrote, iclass 19, count 0 2006.257.22:30:51.22#ibcon#about to read 3, iclass 19, count 0 2006.257.22:30:51.26#ibcon#read 3, iclass 19, count 0 2006.257.22:30:51.26#ibcon#about to read 4, iclass 19, count 0 2006.257.22:30:51.26#ibcon#read 4, iclass 19, count 0 2006.257.22:30:51.26#ibcon#about to read 5, iclass 19, count 0 2006.257.22:30:51.26#ibcon#read 5, iclass 19, count 0 2006.257.22:30:51.26#ibcon#about to read 6, iclass 19, count 0 2006.257.22:30:51.26#ibcon#read 6, iclass 19, count 0 2006.257.22:30:51.26#ibcon#end of sib2, iclass 19, count 0 2006.257.22:30:51.26#ibcon#*after write, iclass 19, count 0 2006.257.22:30:51.26#ibcon#*before return 0, iclass 19, count 0 2006.257.22:30:51.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:51.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:51.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.22:30:51.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.22:30:51.26$vck44/va=6,4 2006.257.22:30:51.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.22:30:51.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.22:30:51.26#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:51.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:51.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:51.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:51.32#ibcon#enter wrdev, iclass 21, count 2 2006.257.22:30:51.32#ibcon#first serial, iclass 21, count 2 2006.257.22:30:51.32#ibcon#enter sib2, iclass 21, count 2 2006.257.22:30:51.32#ibcon#flushed, iclass 21, count 2 2006.257.22:30:51.32#ibcon#about to write, iclass 21, count 2 2006.257.22:30:51.32#ibcon#wrote, iclass 21, count 2 2006.257.22:30:51.32#ibcon#about to read 3, iclass 21, count 2 2006.257.22:30:51.34#ibcon#read 3, iclass 21, count 2 2006.257.22:30:51.34#ibcon#about to read 4, iclass 21, count 2 2006.257.22:30:51.34#ibcon#read 4, iclass 21, count 2 2006.257.22:30:51.34#ibcon#about to read 5, iclass 21, count 2 2006.257.22:30:51.34#ibcon#read 5, iclass 21, count 2 2006.257.22:30:51.34#ibcon#about to read 6, iclass 21, count 2 2006.257.22:30:51.34#ibcon#read 6, iclass 21, count 2 2006.257.22:30:51.34#ibcon#end of sib2, iclass 21, count 2 2006.257.22:30:51.34#ibcon#*mode == 0, iclass 21, count 2 2006.257.22:30:51.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.22:30:51.34#ibcon#[25=AT06-04\r\n] 2006.257.22:30:51.34#ibcon#*before write, iclass 21, count 2 2006.257.22:30:51.34#ibcon#enter sib2, iclass 21, count 2 2006.257.22:30:51.34#ibcon#flushed, iclass 21, count 2 2006.257.22:30:51.34#ibcon#about to write, iclass 21, count 2 2006.257.22:30:51.34#ibcon#wrote, iclass 21, count 2 2006.257.22:30:51.34#ibcon#about to read 3, iclass 21, count 2 2006.257.22:30:51.37#ibcon#read 3, iclass 21, count 2 2006.257.22:30:51.37#ibcon#about to read 4, iclass 21, count 2 2006.257.22:30:51.37#ibcon#read 4, iclass 21, count 2 2006.257.22:30:51.37#ibcon#about to read 5, iclass 21, count 2 2006.257.22:30:51.37#ibcon#read 5, iclass 21, count 2 2006.257.22:30:51.37#ibcon#about to read 6, iclass 21, count 2 2006.257.22:30:51.37#ibcon#read 6, iclass 21, count 2 2006.257.22:30:51.37#ibcon#end of sib2, iclass 21, count 2 2006.257.22:30:51.37#ibcon#*after write, iclass 21, count 2 2006.257.22:30:51.37#ibcon#*before return 0, iclass 21, count 2 2006.257.22:30:51.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:51.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:51.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.22:30:51.37#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:51.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:51.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:51.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:51.49#ibcon#enter wrdev, iclass 21, count 0 2006.257.22:30:51.49#ibcon#first serial, iclass 21, count 0 2006.257.22:30:51.49#ibcon#enter sib2, iclass 21, count 0 2006.257.22:30:51.49#ibcon#flushed, iclass 21, count 0 2006.257.22:30:51.49#ibcon#about to write, iclass 21, count 0 2006.257.22:30:51.49#ibcon#wrote, iclass 21, count 0 2006.257.22:30:51.49#ibcon#about to read 3, iclass 21, count 0 2006.257.22:30:51.51#ibcon#read 3, iclass 21, count 0 2006.257.22:30:51.51#ibcon#about to read 4, iclass 21, count 0 2006.257.22:30:51.51#ibcon#read 4, iclass 21, count 0 2006.257.22:30:51.51#ibcon#about to read 5, iclass 21, count 0 2006.257.22:30:51.51#ibcon#read 5, iclass 21, count 0 2006.257.22:30:51.51#ibcon#about to read 6, iclass 21, count 0 2006.257.22:30:51.51#ibcon#read 6, iclass 21, count 0 2006.257.22:30:51.51#ibcon#end of sib2, iclass 21, count 0 2006.257.22:30:51.51#ibcon#*mode == 0, iclass 21, count 0 2006.257.22:30:51.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.22:30:51.51#ibcon#[25=USB\r\n] 2006.257.22:30:51.51#ibcon#*before write, iclass 21, count 0 2006.257.22:30:51.51#ibcon#enter sib2, iclass 21, count 0 2006.257.22:30:51.51#ibcon#flushed, iclass 21, count 0 2006.257.22:30:51.51#ibcon#about to write, iclass 21, count 0 2006.257.22:30:51.51#ibcon#wrote, iclass 21, count 0 2006.257.22:30:51.51#ibcon#about to read 3, iclass 21, count 0 2006.257.22:30:51.54#ibcon#read 3, iclass 21, count 0 2006.257.22:30:51.54#ibcon#about to read 4, iclass 21, count 0 2006.257.22:30:51.54#ibcon#read 4, iclass 21, count 0 2006.257.22:30:51.54#ibcon#about to read 5, iclass 21, count 0 2006.257.22:30:51.54#ibcon#read 5, iclass 21, count 0 2006.257.22:30:51.54#ibcon#about to read 6, iclass 21, count 0 2006.257.22:30:51.54#ibcon#read 6, iclass 21, count 0 2006.257.22:30:51.54#ibcon#end of sib2, iclass 21, count 0 2006.257.22:30:51.54#ibcon#*after write, iclass 21, count 0 2006.257.22:30:51.54#ibcon#*before return 0, iclass 21, count 0 2006.257.22:30:51.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:51.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:51.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.22:30:51.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.22:30:51.54$vck44/valo=7,864.99 2006.257.22:30:51.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.22:30:51.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.22:30:51.54#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:51.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:51.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:51.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:51.54#ibcon#enter wrdev, iclass 23, count 0 2006.257.22:30:51.54#ibcon#first serial, iclass 23, count 0 2006.257.22:30:51.54#ibcon#enter sib2, iclass 23, count 0 2006.257.22:30:51.54#ibcon#flushed, iclass 23, count 0 2006.257.22:30:51.54#ibcon#about to write, iclass 23, count 0 2006.257.22:30:51.54#ibcon#wrote, iclass 23, count 0 2006.257.22:30:51.54#ibcon#about to read 3, iclass 23, count 0 2006.257.22:30:51.56#ibcon#read 3, iclass 23, count 0 2006.257.22:30:51.56#ibcon#about to read 4, iclass 23, count 0 2006.257.22:30:51.56#ibcon#read 4, iclass 23, count 0 2006.257.22:30:51.56#ibcon#about to read 5, iclass 23, count 0 2006.257.22:30:51.56#ibcon#read 5, iclass 23, count 0 2006.257.22:30:51.56#ibcon#about to read 6, iclass 23, count 0 2006.257.22:30:51.56#ibcon#read 6, iclass 23, count 0 2006.257.22:30:51.56#ibcon#end of sib2, iclass 23, count 0 2006.257.22:30:51.56#ibcon#*mode == 0, iclass 23, count 0 2006.257.22:30:51.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.22:30:51.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.22:30:51.56#ibcon#*before write, iclass 23, count 0 2006.257.22:30:51.56#ibcon#enter sib2, iclass 23, count 0 2006.257.22:30:51.56#ibcon#flushed, iclass 23, count 0 2006.257.22:30:51.56#ibcon#about to write, iclass 23, count 0 2006.257.22:30:51.56#ibcon#wrote, iclass 23, count 0 2006.257.22:30:51.56#ibcon#about to read 3, iclass 23, count 0 2006.257.22:30:51.60#ibcon#read 3, iclass 23, count 0 2006.257.22:30:51.60#ibcon#about to read 4, iclass 23, count 0 2006.257.22:30:51.60#ibcon#read 4, iclass 23, count 0 2006.257.22:30:51.60#ibcon#about to read 5, iclass 23, count 0 2006.257.22:30:51.60#ibcon#read 5, iclass 23, count 0 2006.257.22:30:51.60#ibcon#about to read 6, iclass 23, count 0 2006.257.22:30:51.60#ibcon#read 6, iclass 23, count 0 2006.257.22:30:51.60#ibcon#end of sib2, iclass 23, count 0 2006.257.22:30:51.60#ibcon#*after write, iclass 23, count 0 2006.257.22:30:51.60#ibcon#*before return 0, iclass 23, count 0 2006.257.22:30:51.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:51.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:51.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.22:30:51.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.22:30:51.60$vck44/va=7,4 2006.257.22:30:51.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.22:30:51.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.22:30:51.60#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:51.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:51.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:51.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:51.66#ibcon#enter wrdev, iclass 25, count 2 2006.257.22:30:51.66#ibcon#first serial, iclass 25, count 2 2006.257.22:30:51.66#ibcon#enter sib2, iclass 25, count 2 2006.257.22:30:51.66#ibcon#flushed, iclass 25, count 2 2006.257.22:30:51.66#ibcon#about to write, iclass 25, count 2 2006.257.22:30:51.66#ibcon#wrote, iclass 25, count 2 2006.257.22:30:51.66#ibcon#about to read 3, iclass 25, count 2 2006.257.22:30:51.68#ibcon#read 3, iclass 25, count 2 2006.257.22:30:51.68#ibcon#about to read 4, iclass 25, count 2 2006.257.22:30:51.68#ibcon#read 4, iclass 25, count 2 2006.257.22:30:51.68#ibcon#about to read 5, iclass 25, count 2 2006.257.22:30:51.68#ibcon#read 5, iclass 25, count 2 2006.257.22:30:51.68#ibcon#about to read 6, iclass 25, count 2 2006.257.22:30:51.68#ibcon#read 6, iclass 25, count 2 2006.257.22:30:51.68#ibcon#end of sib2, iclass 25, count 2 2006.257.22:30:51.68#ibcon#*mode == 0, iclass 25, count 2 2006.257.22:30:51.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.22:30:51.68#ibcon#[25=AT07-04\r\n] 2006.257.22:30:51.68#ibcon#*before write, iclass 25, count 2 2006.257.22:30:51.68#ibcon#enter sib2, iclass 25, count 2 2006.257.22:30:51.68#ibcon#flushed, iclass 25, count 2 2006.257.22:30:51.68#ibcon#about to write, iclass 25, count 2 2006.257.22:30:51.68#ibcon#wrote, iclass 25, count 2 2006.257.22:30:51.68#ibcon#about to read 3, iclass 25, count 2 2006.257.22:30:51.71#ibcon#read 3, iclass 25, count 2 2006.257.22:30:51.71#ibcon#about to read 4, iclass 25, count 2 2006.257.22:30:51.71#ibcon#read 4, iclass 25, count 2 2006.257.22:30:51.71#ibcon#about to read 5, iclass 25, count 2 2006.257.22:30:51.71#ibcon#read 5, iclass 25, count 2 2006.257.22:30:51.71#ibcon#about to read 6, iclass 25, count 2 2006.257.22:30:51.71#ibcon#read 6, iclass 25, count 2 2006.257.22:30:51.71#ibcon#end of sib2, iclass 25, count 2 2006.257.22:30:51.71#ibcon#*after write, iclass 25, count 2 2006.257.22:30:51.71#ibcon#*before return 0, iclass 25, count 2 2006.257.22:30:51.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:51.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:51.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.22:30:51.71#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:51.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:51.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:51.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:51.83#ibcon#enter wrdev, iclass 25, count 0 2006.257.22:30:51.83#ibcon#first serial, iclass 25, count 0 2006.257.22:30:51.83#ibcon#enter sib2, iclass 25, count 0 2006.257.22:30:51.83#ibcon#flushed, iclass 25, count 0 2006.257.22:30:51.83#ibcon#about to write, iclass 25, count 0 2006.257.22:30:51.83#ibcon#wrote, iclass 25, count 0 2006.257.22:30:51.83#ibcon#about to read 3, iclass 25, count 0 2006.257.22:30:51.85#ibcon#read 3, iclass 25, count 0 2006.257.22:30:51.85#ibcon#about to read 4, iclass 25, count 0 2006.257.22:30:51.85#ibcon#read 4, iclass 25, count 0 2006.257.22:30:51.85#ibcon#about to read 5, iclass 25, count 0 2006.257.22:30:51.85#ibcon#read 5, iclass 25, count 0 2006.257.22:30:51.85#ibcon#about to read 6, iclass 25, count 0 2006.257.22:30:51.85#ibcon#read 6, iclass 25, count 0 2006.257.22:30:51.85#ibcon#end of sib2, iclass 25, count 0 2006.257.22:30:51.85#ibcon#*mode == 0, iclass 25, count 0 2006.257.22:30:51.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.22:30:51.85#ibcon#[25=USB\r\n] 2006.257.22:30:51.85#ibcon#*before write, iclass 25, count 0 2006.257.22:30:51.85#ibcon#enter sib2, iclass 25, count 0 2006.257.22:30:51.85#ibcon#flushed, iclass 25, count 0 2006.257.22:30:51.85#ibcon#about to write, iclass 25, count 0 2006.257.22:30:51.85#ibcon#wrote, iclass 25, count 0 2006.257.22:30:51.85#ibcon#about to read 3, iclass 25, count 0 2006.257.22:30:51.88#ibcon#read 3, iclass 25, count 0 2006.257.22:30:51.88#ibcon#about to read 4, iclass 25, count 0 2006.257.22:30:51.88#ibcon#read 4, iclass 25, count 0 2006.257.22:30:51.88#ibcon#about to read 5, iclass 25, count 0 2006.257.22:30:51.88#ibcon#read 5, iclass 25, count 0 2006.257.22:30:51.88#ibcon#about to read 6, iclass 25, count 0 2006.257.22:30:51.88#ibcon#read 6, iclass 25, count 0 2006.257.22:30:51.88#ibcon#end of sib2, iclass 25, count 0 2006.257.22:30:51.88#ibcon#*after write, iclass 25, count 0 2006.257.22:30:51.88#ibcon#*before return 0, iclass 25, count 0 2006.257.22:30:51.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:51.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:51.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.22:30:51.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.22:30:51.88$vck44/valo=8,884.99 2006.257.22:30:51.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.22:30:51.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.22:30:51.88#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:51.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:51.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:51.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:51.88#ibcon#enter wrdev, iclass 27, count 0 2006.257.22:30:51.88#ibcon#first serial, iclass 27, count 0 2006.257.22:30:51.88#ibcon#enter sib2, iclass 27, count 0 2006.257.22:30:51.88#ibcon#flushed, iclass 27, count 0 2006.257.22:30:51.88#ibcon#about to write, iclass 27, count 0 2006.257.22:30:51.88#ibcon#wrote, iclass 27, count 0 2006.257.22:30:51.88#ibcon#about to read 3, iclass 27, count 0 2006.257.22:30:51.90#ibcon#read 3, iclass 27, count 0 2006.257.22:30:51.90#ibcon#about to read 4, iclass 27, count 0 2006.257.22:30:51.90#ibcon#read 4, iclass 27, count 0 2006.257.22:30:51.90#ibcon#about to read 5, iclass 27, count 0 2006.257.22:30:51.90#ibcon#read 5, iclass 27, count 0 2006.257.22:30:51.90#ibcon#about to read 6, iclass 27, count 0 2006.257.22:30:51.90#ibcon#read 6, iclass 27, count 0 2006.257.22:30:51.90#ibcon#end of sib2, iclass 27, count 0 2006.257.22:30:51.90#ibcon#*mode == 0, iclass 27, count 0 2006.257.22:30:51.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.22:30:51.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.22:30:51.90#ibcon#*before write, iclass 27, count 0 2006.257.22:30:51.90#ibcon#enter sib2, iclass 27, count 0 2006.257.22:30:51.90#ibcon#flushed, iclass 27, count 0 2006.257.22:30:51.90#ibcon#about to write, iclass 27, count 0 2006.257.22:30:51.90#ibcon#wrote, iclass 27, count 0 2006.257.22:30:51.90#ibcon#about to read 3, iclass 27, count 0 2006.257.22:30:51.94#ibcon#read 3, iclass 27, count 0 2006.257.22:30:51.94#ibcon#about to read 4, iclass 27, count 0 2006.257.22:30:51.94#ibcon#read 4, iclass 27, count 0 2006.257.22:30:51.94#ibcon#about to read 5, iclass 27, count 0 2006.257.22:30:51.94#ibcon#read 5, iclass 27, count 0 2006.257.22:30:51.94#ibcon#about to read 6, iclass 27, count 0 2006.257.22:30:51.94#ibcon#read 6, iclass 27, count 0 2006.257.22:30:51.94#ibcon#end of sib2, iclass 27, count 0 2006.257.22:30:51.94#ibcon#*after write, iclass 27, count 0 2006.257.22:30:51.94#ibcon#*before return 0, iclass 27, count 0 2006.257.22:30:51.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:51.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:51.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.22:30:51.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.22:30:51.94$vck44/va=8,4 2006.257.22:30:51.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.22:30:51.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.22:30:51.94#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:51.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:30:52.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:30:52.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:30:52.00#ibcon#enter wrdev, iclass 29, count 2 2006.257.22:30:52.00#ibcon#first serial, iclass 29, count 2 2006.257.22:30:52.00#ibcon#enter sib2, iclass 29, count 2 2006.257.22:30:52.00#ibcon#flushed, iclass 29, count 2 2006.257.22:30:52.00#ibcon#about to write, iclass 29, count 2 2006.257.22:30:52.00#ibcon#wrote, iclass 29, count 2 2006.257.22:30:52.00#ibcon#about to read 3, iclass 29, count 2 2006.257.22:30:52.02#ibcon#read 3, iclass 29, count 2 2006.257.22:30:52.02#ibcon#about to read 4, iclass 29, count 2 2006.257.22:30:52.02#ibcon#read 4, iclass 29, count 2 2006.257.22:30:52.02#ibcon#about to read 5, iclass 29, count 2 2006.257.22:30:52.02#ibcon#read 5, iclass 29, count 2 2006.257.22:30:52.02#ibcon#about to read 6, iclass 29, count 2 2006.257.22:30:52.02#ibcon#read 6, iclass 29, count 2 2006.257.22:30:52.02#ibcon#end of sib2, iclass 29, count 2 2006.257.22:30:52.02#ibcon#*mode == 0, iclass 29, count 2 2006.257.22:30:52.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.22:30:52.02#ibcon#[25=AT08-04\r\n] 2006.257.22:30:52.02#ibcon#*before write, iclass 29, count 2 2006.257.22:30:52.02#ibcon#enter sib2, iclass 29, count 2 2006.257.22:30:52.02#ibcon#flushed, iclass 29, count 2 2006.257.22:30:52.02#ibcon#about to write, iclass 29, count 2 2006.257.22:30:52.02#ibcon#wrote, iclass 29, count 2 2006.257.22:30:52.02#ibcon#about to read 3, iclass 29, count 2 2006.257.22:30:52.05#ibcon#read 3, iclass 29, count 2 2006.257.22:30:52.05#ibcon#about to read 4, iclass 29, count 2 2006.257.22:30:52.05#ibcon#read 4, iclass 29, count 2 2006.257.22:30:52.05#ibcon#about to read 5, iclass 29, count 2 2006.257.22:30:52.05#ibcon#read 5, iclass 29, count 2 2006.257.22:30:52.05#ibcon#about to read 6, iclass 29, count 2 2006.257.22:30:52.05#ibcon#read 6, iclass 29, count 2 2006.257.22:30:52.05#ibcon#end of sib2, iclass 29, count 2 2006.257.22:30:52.05#ibcon#*after write, iclass 29, count 2 2006.257.22:30:52.05#ibcon#*before return 0, iclass 29, count 2 2006.257.22:30:52.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:30:52.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:30:52.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.22:30:52.05#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:52.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:30:52.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:30:52.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:30:52.17#ibcon#enter wrdev, iclass 29, count 0 2006.257.22:30:52.17#ibcon#first serial, iclass 29, count 0 2006.257.22:30:52.17#ibcon#enter sib2, iclass 29, count 0 2006.257.22:30:52.17#ibcon#flushed, iclass 29, count 0 2006.257.22:30:52.17#ibcon#about to write, iclass 29, count 0 2006.257.22:30:52.17#ibcon#wrote, iclass 29, count 0 2006.257.22:30:52.17#ibcon#about to read 3, iclass 29, count 0 2006.257.22:30:52.19#ibcon#read 3, iclass 29, count 0 2006.257.22:30:52.19#ibcon#about to read 4, iclass 29, count 0 2006.257.22:30:52.19#ibcon#read 4, iclass 29, count 0 2006.257.22:30:52.19#ibcon#about to read 5, iclass 29, count 0 2006.257.22:30:52.19#ibcon#read 5, iclass 29, count 0 2006.257.22:30:52.19#ibcon#about to read 6, iclass 29, count 0 2006.257.22:30:52.19#ibcon#read 6, iclass 29, count 0 2006.257.22:30:52.19#ibcon#end of sib2, iclass 29, count 0 2006.257.22:30:52.19#ibcon#*mode == 0, iclass 29, count 0 2006.257.22:30:52.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.22:30:52.19#ibcon#[25=USB\r\n] 2006.257.22:30:52.19#ibcon#*before write, iclass 29, count 0 2006.257.22:30:52.19#ibcon#enter sib2, iclass 29, count 0 2006.257.22:30:52.19#ibcon#flushed, iclass 29, count 0 2006.257.22:30:52.19#ibcon#about to write, iclass 29, count 0 2006.257.22:30:52.19#ibcon#wrote, iclass 29, count 0 2006.257.22:30:52.19#ibcon#about to read 3, iclass 29, count 0 2006.257.22:30:52.22#ibcon#read 3, iclass 29, count 0 2006.257.22:30:52.22#ibcon#about to read 4, iclass 29, count 0 2006.257.22:30:52.22#ibcon#read 4, iclass 29, count 0 2006.257.22:30:52.22#ibcon#about to read 5, iclass 29, count 0 2006.257.22:30:52.22#ibcon#read 5, iclass 29, count 0 2006.257.22:30:52.22#ibcon#about to read 6, iclass 29, count 0 2006.257.22:30:52.22#ibcon#read 6, iclass 29, count 0 2006.257.22:30:52.22#ibcon#end of sib2, iclass 29, count 0 2006.257.22:30:52.22#ibcon#*after write, iclass 29, count 0 2006.257.22:30:52.22#ibcon#*before return 0, iclass 29, count 0 2006.257.22:30:52.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:30:52.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:30:52.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.22:30:52.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.22:30:52.22$vck44/vblo=1,629.99 2006.257.22:30:52.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.22:30:52.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.22:30:52.22#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:52.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:30:52.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:30:52.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:30:52.22#ibcon#enter wrdev, iclass 31, count 0 2006.257.22:30:52.22#ibcon#first serial, iclass 31, count 0 2006.257.22:30:52.22#ibcon#enter sib2, iclass 31, count 0 2006.257.22:30:52.22#ibcon#flushed, iclass 31, count 0 2006.257.22:30:52.22#ibcon#about to write, iclass 31, count 0 2006.257.22:30:52.22#ibcon#wrote, iclass 31, count 0 2006.257.22:30:52.22#ibcon#about to read 3, iclass 31, count 0 2006.257.22:30:52.24#ibcon#read 3, iclass 31, count 0 2006.257.22:30:52.24#ibcon#about to read 4, iclass 31, count 0 2006.257.22:30:52.24#ibcon#read 4, iclass 31, count 0 2006.257.22:30:52.24#ibcon#about to read 5, iclass 31, count 0 2006.257.22:30:52.24#ibcon#read 5, iclass 31, count 0 2006.257.22:30:52.24#ibcon#about to read 6, iclass 31, count 0 2006.257.22:30:52.24#ibcon#read 6, iclass 31, count 0 2006.257.22:30:52.24#ibcon#end of sib2, iclass 31, count 0 2006.257.22:30:52.24#ibcon#*mode == 0, iclass 31, count 0 2006.257.22:30:52.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.22:30:52.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.22:30:52.24#ibcon#*before write, iclass 31, count 0 2006.257.22:30:52.24#ibcon#enter sib2, iclass 31, count 0 2006.257.22:30:52.24#ibcon#flushed, iclass 31, count 0 2006.257.22:30:52.24#ibcon#about to write, iclass 31, count 0 2006.257.22:30:52.24#ibcon#wrote, iclass 31, count 0 2006.257.22:30:52.24#ibcon#about to read 3, iclass 31, count 0 2006.257.22:30:52.28#ibcon#read 3, iclass 31, count 0 2006.257.22:30:52.28#ibcon#about to read 4, iclass 31, count 0 2006.257.22:30:52.28#ibcon#read 4, iclass 31, count 0 2006.257.22:30:52.28#ibcon#about to read 5, iclass 31, count 0 2006.257.22:30:52.28#ibcon#read 5, iclass 31, count 0 2006.257.22:30:52.28#ibcon#about to read 6, iclass 31, count 0 2006.257.22:30:52.28#ibcon#read 6, iclass 31, count 0 2006.257.22:30:52.28#ibcon#end of sib2, iclass 31, count 0 2006.257.22:30:52.28#ibcon#*after write, iclass 31, count 0 2006.257.22:30:52.28#ibcon#*before return 0, iclass 31, count 0 2006.257.22:30:52.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:30:52.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:30:52.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.22:30:52.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.22:30:52.28$vck44/vb=1,4 2006.257.22:30:52.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.22:30:52.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.22:30:52.28#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:52.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:30:52.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:30:52.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:30:52.28#ibcon#enter wrdev, iclass 33, count 2 2006.257.22:30:52.28#ibcon#first serial, iclass 33, count 2 2006.257.22:30:52.28#ibcon#enter sib2, iclass 33, count 2 2006.257.22:30:52.28#ibcon#flushed, iclass 33, count 2 2006.257.22:30:52.28#ibcon#about to write, iclass 33, count 2 2006.257.22:30:52.28#ibcon#wrote, iclass 33, count 2 2006.257.22:30:52.28#ibcon#about to read 3, iclass 33, count 2 2006.257.22:30:52.30#ibcon#read 3, iclass 33, count 2 2006.257.22:30:52.30#ibcon#about to read 4, iclass 33, count 2 2006.257.22:30:52.30#ibcon#read 4, iclass 33, count 2 2006.257.22:30:52.30#ibcon#about to read 5, iclass 33, count 2 2006.257.22:30:52.30#ibcon#read 5, iclass 33, count 2 2006.257.22:30:52.30#ibcon#about to read 6, iclass 33, count 2 2006.257.22:30:52.30#ibcon#read 6, iclass 33, count 2 2006.257.22:30:52.30#ibcon#end of sib2, iclass 33, count 2 2006.257.22:30:52.30#ibcon#*mode == 0, iclass 33, count 2 2006.257.22:30:52.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.22:30:52.30#ibcon#[27=AT01-04\r\n] 2006.257.22:30:52.30#ibcon#*before write, iclass 33, count 2 2006.257.22:30:52.30#ibcon#enter sib2, iclass 33, count 2 2006.257.22:30:52.30#ibcon#flushed, iclass 33, count 2 2006.257.22:30:52.30#ibcon#about to write, iclass 33, count 2 2006.257.22:30:52.30#ibcon#wrote, iclass 33, count 2 2006.257.22:30:52.30#ibcon#about to read 3, iclass 33, count 2 2006.257.22:30:52.33#ibcon#read 3, iclass 33, count 2 2006.257.22:30:52.33#ibcon#about to read 4, iclass 33, count 2 2006.257.22:30:52.33#ibcon#read 4, iclass 33, count 2 2006.257.22:30:52.33#ibcon#about to read 5, iclass 33, count 2 2006.257.22:30:52.33#ibcon#read 5, iclass 33, count 2 2006.257.22:30:52.33#ibcon#about to read 6, iclass 33, count 2 2006.257.22:30:52.33#ibcon#read 6, iclass 33, count 2 2006.257.22:30:52.33#ibcon#end of sib2, iclass 33, count 2 2006.257.22:30:52.33#ibcon#*after write, iclass 33, count 2 2006.257.22:30:52.33#ibcon#*before return 0, iclass 33, count 2 2006.257.22:30:52.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:30:52.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:30:52.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.22:30:52.33#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:52.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:30:52.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:30:52.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:30:52.45#ibcon#enter wrdev, iclass 33, count 0 2006.257.22:30:52.45#ibcon#first serial, iclass 33, count 0 2006.257.22:30:52.45#ibcon#enter sib2, iclass 33, count 0 2006.257.22:30:52.45#ibcon#flushed, iclass 33, count 0 2006.257.22:30:52.45#ibcon#about to write, iclass 33, count 0 2006.257.22:30:52.45#ibcon#wrote, iclass 33, count 0 2006.257.22:30:52.45#ibcon#about to read 3, iclass 33, count 0 2006.257.22:30:52.47#ibcon#read 3, iclass 33, count 0 2006.257.22:30:52.47#ibcon#about to read 4, iclass 33, count 0 2006.257.22:30:52.47#ibcon#read 4, iclass 33, count 0 2006.257.22:30:52.47#ibcon#about to read 5, iclass 33, count 0 2006.257.22:30:52.47#ibcon#read 5, iclass 33, count 0 2006.257.22:30:52.47#ibcon#about to read 6, iclass 33, count 0 2006.257.22:30:52.47#ibcon#read 6, iclass 33, count 0 2006.257.22:30:52.47#ibcon#end of sib2, iclass 33, count 0 2006.257.22:30:52.47#ibcon#*mode == 0, iclass 33, count 0 2006.257.22:30:52.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.22:30:52.47#ibcon#[27=USB\r\n] 2006.257.22:30:52.47#ibcon#*before write, iclass 33, count 0 2006.257.22:30:52.47#ibcon#enter sib2, iclass 33, count 0 2006.257.22:30:52.47#ibcon#flushed, iclass 33, count 0 2006.257.22:30:52.47#ibcon#about to write, iclass 33, count 0 2006.257.22:30:52.47#ibcon#wrote, iclass 33, count 0 2006.257.22:30:52.47#ibcon#about to read 3, iclass 33, count 0 2006.257.22:30:52.50#ibcon#read 3, iclass 33, count 0 2006.257.22:30:52.50#ibcon#about to read 4, iclass 33, count 0 2006.257.22:30:52.50#ibcon#read 4, iclass 33, count 0 2006.257.22:30:52.50#ibcon#about to read 5, iclass 33, count 0 2006.257.22:30:52.50#ibcon#read 5, iclass 33, count 0 2006.257.22:30:52.50#ibcon#about to read 6, iclass 33, count 0 2006.257.22:30:52.50#ibcon#read 6, iclass 33, count 0 2006.257.22:30:52.50#ibcon#end of sib2, iclass 33, count 0 2006.257.22:30:52.50#ibcon#*after write, iclass 33, count 0 2006.257.22:30:52.50#ibcon#*before return 0, iclass 33, count 0 2006.257.22:30:52.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:30:52.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:30:52.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.22:30:52.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.22:30:52.50$vck44/vblo=2,634.99 2006.257.22:30:52.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.22:30:52.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.22:30:52.50#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:52.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:52.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:52.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:52.50#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:30:52.50#ibcon#first serial, iclass 35, count 0 2006.257.22:30:52.50#ibcon#enter sib2, iclass 35, count 0 2006.257.22:30:52.50#ibcon#flushed, iclass 35, count 0 2006.257.22:30:52.50#ibcon#about to write, iclass 35, count 0 2006.257.22:30:52.50#ibcon#wrote, iclass 35, count 0 2006.257.22:30:52.50#ibcon#about to read 3, iclass 35, count 0 2006.257.22:30:52.52#ibcon#read 3, iclass 35, count 0 2006.257.22:30:52.52#ibcon#about to read 4, iclass 35, count 0 2006.257.22:30:52.52#ibcon#read 4, iclass 35, count 0 2006.257.22:30:52.52#ibcon#about to read 5, iclass 35, count 0 2006.257.22:30:52.52#ibcon#read 5, iclass 35, count 0 2006.257.22:30:52.52#ibcon#about to read 6, iclass 35, count 0 2006.257.22:30:52.52#ibcon#read 6, iclass 35, count 0 2006.257.22:30:52.52#ibcon#end of sib2, iclass 35, count 0 2006.257.22:30:52.52#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:30:52.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:30:52.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.22:30:52.52#ibcon#*before write, iclass 35, count 0 2006.257.22:30:52.52#ibcon#enter sib2, iclass 35, count 0 2006.257.22:30:52.52#ibcon#flushed, iclass 35, count 0 2006.257.22:30:52.52#ibcon#about to write, iclass 35, count 0 2006.257.22:30:52.52#ibcon#wrote, iclass 35, count 0 2006.257.22:30:52.52#ibcon#about to read 3, iclass 35, count 0 2006.257.22:30:52.56#ibcon#read 3, iclass 35, count 0 2006.257.22:30:52.56#ibcon#about to read 4, iclass 35, count 0 2006.257.22:30:52.56#ibcon#read 4, iclass 35, count 0 2006.257.22:30:52.56#ibcon#about to read 5, iclass 35, count 0 2006.257.22:30:52.56#ibcon#read 5, iclass 35, count 0 2006.257.22:30:52.56#ibcon#about to read 6, iclass 35, count 0 2006.257.22:30:52.56#ibcon#read 6, iclass 35, count 0 2006.257.22:30:52.56#ibcon#end of sib2, iclass 35, count 0 2006.257.22:30:52.56#ibcon#*after write, iclass 35, count 0 2006.257.22:30:52.56#ibcon#*before return 0, iclass 35, count 0 2006.257.22:30:52.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:52.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:30:52.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:30:52.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:30:52.56$vck44/vb=2,5 2006.257.22:30:52.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.22:30:52.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.22:30:52.56#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:52.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:52.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:52.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:52.62#ibcon#enter wrdev, iclass 37, count 2 2006.257.22:30:52.62#ibcon#first serial, iclass 37, count 2 2006.257.22:30:52.62#ibcon#enter sib2, iclass 37, count 2 2006.257.22:30:52.62#ibcon#flushed, iclass 37, count 2 2006.257.22:30:52.62#ibcon#about to write, iclass 37, count 2 2006.257.22:30:52.62#ibcon#wrote, iclass 37, count 2 2006.257.22:30:52.62#ibcon#about to read 3, iclass 37, count 2 2006.257.22:30:52.64#ibcon#read 3, iclass 37, count 2 2006.257.22:30:52.64#ibcon#about to read 4, iclass 37, count 2 2006.257.22:30:52.64#ibcon#read 4, iclass 37, count 2 2006.257.22:30:52.64#ibcon#about to read 5, iclass 37, count 2 2006.257.22:30:52.64#ibcon#read 5, iclass 37, count 2 2006.257.22:30:52.64#ibcon#about to read 6, iclass 37, count 2 2006.257.22:30:52.64#ibcon#read 6, iclass 37, count 2 2006.257.22:30:52.64#ibcon#end of sib2, iclass 37, count 2 2006.257.22:30:52.64#ibcon#*mode == 0, iclass 37, count 2 2006.257.22:30:52.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.22:30:52.64#ibcon#[27=AT02-05\r\n] 2006.257.22:30:52.64#ibcon#*before write, iclass 37, count 2 2006.257.22:30:52.64#ibcon#enter sib2, iclass 37, count 2 2006.257.22:30:52.64#ibcon#flushed, iclass 37, count 2 2006.257.22:30:52.64#ibcon#about to write, iclass 37, count 2 2006.257.22:30:52.64#ibcon#wrote, iclass 37, count 2 2006.257.22:30:52.64#ibcon#about to read 3, iclass 37, count 2 2006.257.22:30:52.67#ibcon#read 3, iclass 37, count 2 2006.257.22:30:52.67#ibcon#about to read 4, iclass 37, count 2 2006.257.22:30:52.67#ibcon#read 4, iclass 37, count 2 2006.257.22:30:52.67#ibcon#about to read 5, iclass 37, count 2 2006.257.22:30:52.67#ibcon#read 5, iclass 37, count 2 2006.257.22:30:52.67#ibcon#about to read 6, iclass 37, count 2 2006.257.22:30:52.67#ibcon#read 6, iclass 37, count 2 2006.257.22:30:52.67#ibcon#end of sib2, iclass 37, count 2 2006.257.22:30:52.67#ibcon#*after write, iclass 37, count 2 2006.257.22:30:52.67#ibcon#*before return 0, iclass 37, count 2 2006.257.22:30:52.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:52.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:30:52.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.22:30:52.67#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:52.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:52.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:52.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:52.79#ibcon#enter wrdev, iclass 37, count 0 2006.257.22:30:52.79#ibcon#first serial, iclass 37, count 0 2006.257.22:30:52.79#ibcon#enter sib2, iclass 37, count 0 2006.257.22:30:52.79#ibcon#flushed, iclass 37, count 0 2006.257.22:30:52.79#ibcon#about to write, iclass 37, count 0 2006.257.22:30:52.79#ibcon#wrote, iclass 37, count 0 2006.257.22:30:52.79#ibcon#about to read 3, iclass 37, count 0 2006.257.22:30:52.81#ibcon#read 3, iclass 37, count 0 2006.257.22:30:52.81#ibcon#about to read 4, iclass 37, count 0 2006.257.22:30:52.81#ibcon#read 4, iclass 37, count 0 2006.257.22:30:52.81#ibcon#about to read 5, iclass 37, count 0 2006.257.22:30:52.81#ibcon#read 5, iclass 37, count 0 2006.257.22:30:52.81#ibcon#about to read 6, iclass 37, count 0 2006.257.22:30:52.81#ibcon#read 6, iclass 37, count 0 2006.257.22:30:52.81#ibcon#end of sib2, iclass 37, count 0 2006.257.22:30:52.81#ibcon#*mode == 0, iclass 37, count 0 2006.257.22:30:52.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.22:30:52.81#ibcon#[27=USB\r\n] 2006.257.22:30:52.81#ibcon#*before write, iclass 37, count 0 2006.257.22:30:52.81#ibcon#enter sib2, iclass 37, count 0 2006.257.22:30:52.81#ibcon#flushed, iclass 37, count 0 2006.257.22:30:52.81#ibcon#about to write, iclass 37, count 0 2006.257.22:30:52.81#ibcon#wrote, iclass 37, count 0 2006.257.22:30:52.81#ibcon#about to read 3, iclass 37, count 0 2006.257.22:30:52.84#ibcon#read 3, iclass 37, count 0 2006.257.22:30:52.84#ibcon#about to read 4, iclass 37, count 0 2006.257.22:30:52.84#ibcon#read 4, iclass 37, count 0 2006.257.22:30:52.84#ibcon#about to read 5, iclass 37, count 0 2006.257.22:30:52.84#ibcon#read 5, iclass 37, count 0 2006.257.22:30:52.84#ibcon#about to read 6, iclass 37, count 0 2006.257.22:30:52.84#ibcon#read 6, iclass 37, count 0 2006.257.22:30:52.84#ibcon#end of sib2, iclass 37, count 0 2006.257.22:30:52.84#ibcon#*after write, iclass 37, count 0 2006.257.22:30:52.84#ibcon#*before return 0, iclass 37, count 0 2006.257.22:30:52.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:52.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:30:52.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.22:30:52.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.22:30:52.84$vck44/vblo=3,649.99 2006.257.22:30:52.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.22:30:52.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.22:30:52.84#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:52.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:52.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:52.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:52.84#ibcon#enter wrdev, iclass 39, count 0 2006.257.22:30:52.84#ibcon#first serial, iclass 39, count 0 2006.257.22:30:52.84#ibcon#enter sib2, iclass 39, count 0 2006.257.22:30:52.84#ibcon#flushed, iclass 39, count 0 2006.257.22:30:52.84#ibcon#about to write, iclass 39, count 0 2006.257.22:30:52.84#ibcon#wrote, iclass 39, count 0 2006.257.22:30:52.84#ibcon#about to read 3, iclass 39, count 0 2006.257.22:30:52.86#ibcon#read 3, iclass 39, count 0 2006.257.22:30:52.86#ibcon#about to read 4, iclass 39, count 0 2006.257.22:30:52.86#ibcon#read 4, iclass 39, count 0 2006.257.22:30:52.86#ibcon#about to read 5, iclass 39, count 0 2006.257.22:30:52.86#ibcon#read 5, iclass 39, count 0 2006.257.22:30:52.86#ibcon#about to read 6, iclass 39, count 0 2006.257.22:30:52.86#ibcon#read 6, iclass 39, count 0 2006.257.22:30:52.86#ibcon#end of sib2, iclass 39, count 0 2006.257.22:30:52.86#ibcon#*mode == 0, iclass 39, count 0 2006.257.22:30:52.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.22:30:52.86#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.22:30:52.86#ibcon#*before write, iclass 39, count 0 2006.257.22:30:52.86#ibcon#enter sib2, iclass 39, count 0 2006.257.22:30:52.86#ibcon#flushed, iclass 39, count 0 2006.257.22:30:52.86#ibcon#about to write, iclass 39, count 0 2006.257.22:30:52.86#ibcon#wrote, iclass 39, count 0 2006.257.22:30:52.86#ibcon#about to read 3, iclass 39, count 0 2006.257.22:30:52.90#ibcon#read 3, iclass 39, count 0 2006.257.22:30:52.90#ibcon#about to read 4, iclass 39, count 0 2006.257.22:30:52.90#ibcon#read 4, iclass 39, count 0 2006.257.22:30:52.90#ibcon#about to read 5, iclass 39, count 0 2006.257.22:30:52.90#ibcon#read 5, iclass 39, count 0 2006.257.22:30:52.90#ibcon#about to read 6, iclass 39, count 0 2006.257.22:30:52.90#ibcon#read 6, iclass 39, count 0 2006.257.22:30:52.90#ibcon#end of sib2, iclass 39, count 0 2006.257.22:30:52.90#ibcon#*after write, iclass 39, count 0 2006.257.22:30:52.90#ibcon#*before return 0, iclass 39, count 0 2006.257.22:30:52.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:52.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:30:52.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.22:30:52.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.22:30:52.90$vck44/vb=3,4 2006.257.22:30:52.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.22:30:52.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.22:30:52.90#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:52.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:52.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:52.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:52.96#ibcon#enter wrdev, iclass 3, count 2 2006.257.22:30:52.96#ibcon#first serial, iclass 3, count 2 2006.257.22:30:52.96#ibcon#enter sib2, iclass 3, count 2 2006.257.22:30:52.96#ibcon#flushed, iclass 3, count 2 2006.257.22:30:52.96#ibcon#about to write, iclass 3, count 2 2006.257.22:30:52.96#ibcon#wrote, iclass 3, count 2 2006.257.22:30:52.96#ibcon#about to read 3, iclass 3, count 2 2006.257.22:30:52.98#ibcon#read 3, iclass 3, count 2 2006.257.22:30:52.98#ibcon#about to read 4, iclass 3, count 2 2006.257.22:30:52.98#ibcon#read 4, iclass 3, count 2 2006.257.22:30:52.98#ibcon#about to read 5, iclass 3, count 2 2006.257.22:30:52.98#ibcon#read 5, iclass 3, count 2 2006.257.22:30:52.98#ibcon#about to read 6, iclass 3, count 2 2006.257.22:30:52.98#ibcon#read 6, iclass 3, count 2 2006.257.22:30:52.98#ibcon#end of sib2, iclass 3, count 2 2006.257.22:30:52.98#ibcon#*mode == 0, iclass 3, count 2 2006.257.22:30:52.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.22:30:52.98#ibcon#[27=AT03-04\r\n] 2006.257.22:30:52.98#ibcon#*before write, iclass 3, count 2 2006.257.22:30:52.98#ibcon#enter sib2, iclass 3, count 2 2006.257.22:30:52.98#ibcon#flushed, iclass 3, count 2 2006.257.22:30:52.98#ibcon#about to write, iclass 3, count 2 2006.257.22:30:52.98#ibcon#wrote, iclass 3, count 2 2006.257.22:30:52.98#ibcon#about to read 3, iclass 3, count 2 2006.257.22:30:53.01#ibcon#read 3, iclass 3, count 2 2006.257.22:30:53.01#ibcon#about to read 4, iclass 3, count 2 2006.257.22:30:53.01#ibcon#read 4, iclass 3, count 2 2006.257.22:30:53.01#ibcon#about to read 5, iclass 3, count 2 2006.257.22:30:53.01#ibcon#read 5, iclass 3, count 2 2006.257.22:30:53.01#ibcon#about to read 6, iclass 3, count 2 2006.257.22:30:53.01#ibcon#read 6, iclass 3, count 2 2006.257.22:30:53.01#ibcon#end of sib2, iclass 3, count 2 2006.257.22:30:53.01#ibcon#*after write, iclass 3, count 2 2006.257.22:30:53.01#ibcon#*before return 0, iclass 3, count 2 2006.257.22:30:53.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:53.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:30:53.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.22:30:53.01#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:53.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:53.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:53.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:53.13#ibcon#enter wrdev, iclass 3, count 0 2006.257.22:30:53.13#ibcon#first serial, iclass 3, count 0 2006.257.22:30:53.13#ibcon#enter sib2, iclass 3, count 0 2006.257.22:30:53.13#ibcon#flushed, iclass 3, count 0 2006.257.22:30:53.13#ibcon#about to write, iclass 3, count 0 2006.257.22:30:53.13#ibcon#wrote, iclass 3, count 0 2006.257.22:30:53.13#ibcon#about to read 3, iclass 3, count 0 2006.257.22:30:53.15#ibcon#read 3, iclass 3, count 0 2006.257.22:30:53.15#ibcon#about to read 4, iclass 3, count 0 2006.257.22:30:53.15#ibcon#read 4, iclass 3, count 0 2006.257.22:30:53.15#ibcon#about to read 5, iclass 3, count 0 2006.257.22:30:53.15#ibcon#read 5, iclass 3, count 0 2006.257.22:30:53.15#ibcon#about to read 6, iclass 3, count 0 2006.257.22:30:53.15#ibcon#read 6, iclass 3, count 0 2006.257.22:30:53.15#ibcon#end of sib2, iclass 3, count 0 2006.257.22:30:53.15#ibcon#*mode == 0, iclass 3, count 0 2006.257.22:30:53.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.22:30:53.15#ibcon#[27=USB\r\n] 2006.257.22:30:53.15#ibcon#*before write, iclass 3, count 0 2006.257.22:30:53.15#ibcon#enter sib2, iclass 3, count 0 2006.257.22:30:53.15#ibcon#flushed, iclass 3, count 0 2006.257.22:30:53.15#ibcon#about to write, iclass 3, count 0 2006.257.22:30:53.15#ibcon#wrote, iclass 3, count 0 2006.257.22:30:53.15#ibcon#about to read 3, iclass 3, count 0 2006.257.22:30:53.18#ibcon#read 3, iclass 3, count 0 2006.257.22:30:53.18#ibcon#about to read 4, iclass 3, count 0 2006.257.22:30:53.18#ibcon#read 4, iclass 3, count 0 2006.257.22:30:53.18#ibcon#about to read 5, iclass 3, count 0 2006.257.22:30:53.18#ibcon#read 5, iclass 3, count 0 2006.257.22:30:53.18#ibcon#about to read 6, iclass 3, count 0 2006.257.22:30:53.18#ibcon#read 6, iclass 3, count 0 2006.257.22:30:53.18#ibcon#end of sib2, iclass 3, count 0 2006.257.22:30:53.18#ibcon#*after write, iclass 3, count 0 2006.257.22:30:53.18#ibcon#*before return 0, iclass 3, count 0 2006.257.22:30:53.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:53.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:30:53.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.22:30:53.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.22:30:53.18$vck44/vblo=4,679.99 2006.257.22:30:53.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.22:30:53.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.22:30:53.18#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:53.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:53.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:53.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:53.18#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:30:53.18#ibcon#first serial, iclass 5, count 0 2006.257.22:30:53.18#ibcon#enter sib2, iclass 5, count 0 2006.257.22:30:53.18#ibcon#flushed, iclass 5, count 0 2006.257.22:30:53.18#ibcon#about to write, iclass 5, count 0 2006.257.22:30:53.18#ibcon#wrote, iclass 5, count 0 2006.257.22:30:53.18#ibcon#about to read 3, iclass 5, count 0 2006.257.22:30:53.20#ibcon#read 3, iclass 5, count 0 2006.257.22:30:53.20#ibcon#about to read 4, iclass 5, count 0 2006.257.22:30:53.20#ibcon#read 4, iclass 5, count 0 2006.257.22:30:53.20#ibcon#about to read 5, iclass 5, count 0 2006.257.22:30:53.20#ibcon#read 5, iclass 5, count 0 2006.257.22:30:53.20#ibcon#about to read 6, iclass 5, count 0 2006.257.22:30:53.20#ibcon#read 6, iclass 5, count 0 2006.257.22:30:53.20#ibcon#end of sib2, iclass 5, count 0 2006.257.22:30:53.20#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:30:53.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:30:53.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.22:30:53.20#ibcon#*before write, iclass 5, count 0 2006.257.22:30:53.20#ibcon#enter sib2, iclass 5, count 0 2006.257.22:30:53.20#ibcon#flushed, iclass 5, count 0 2006.257.22:30:53.20#ibcon#about to write, iclass 5, count 0 2006.257.22:30:53.20#ibcon#wrote, iclass 5, count 0 2006.257.22:30:53.20#ibcon#about to read 3, iclass 5, count 0 2006.257.22:30:53.24#ibcon#read 3, iclass 5, count 0 2006.257.22:30:53.24#ibcon#about to read 4, iclass 5, count 0 2006.257.22:30:53.24#ibcon#read 4, iclass 5, count 0 2006.257.22:30:53.24#ibcon#about to read 5, iclass 5, count 0 2006.257.22:30:53.24#ibcon#read 5, iclass 5, count 0 2006.257.22:30:53.24#ibcon#about to read 6, iclass 5, count 0 2006.257.22:30:53.24#ibcon#read 6, iclass 5, count 0 2006.257.22:30:53.24#ibcon#end of sib2, iclass 5, count 0 2006.257.22:30:53.24#ibcon#*after write, iclass 5, count 0 2006.257.22:30:53.24#ibcon#*before return 0, iclass 5, count 0 2006.257.22:30:53.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:53.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:30:53.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:30:53.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:30:53.24$vck44/vb=4,5 2006.257.22:30:53.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.22:30:53.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.22:30:53.24#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:53.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:53.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:53.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:53.30#ibcon#enter wrdev, iclass 7, count 2 2006.257.22:30:53.30#ibcon#first serial, iclass 7, count 2 2006.257.22:30:53.30#ibcon#enter sib2, iclass 7, count 2 2006.257.22:30:53.30#ibcon#flushed, iclass 7, count 2 2006.257.22:30:53.30#ibcon#about to write, iclass 7, count 2 2006.257.22:30:53.30#ibcon#wrote, iclass 7, count 2 2006.257.22:30:53.30#ibcon#about to read 3, iclass 7, count 2 2006.257.22:30:53.32#ibcon#read 3, iclass 7, count 2 2006.257.22:30:53.32#ibcon#about to read 4, iclass 7, count 2 2006.257.22:30:53.32#ibcon#read 4, iclass 7, count 2 2006.257.22:30:53.32#ibcon#about to read 5, iclass 7, count 2 2006.257.22:30:53.32#ibcon#read 5, iclass 7, count 2 2006.257.22:30:53.32#ibcon#about to read 6, iclass 7, count 2 2006.257.22:30:53.32#ibcon#read 6, iclass 7, count 2 2006.257.22:30:53.32#ibcon#end of sib2, iclass 7, count 2 2006.257.22:30:53.32#ibcon#*mode == 0, iclass 7, count 2 2006.257.22:30:53.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.22:30:53.32#ibcon#[27=AT04-05\r\n] 2006.257.22:30:53.32#ibcon#*before write, iclass 7, count 2 2006.257.22:30:53.32#ibcon#enter sib2, iclass 7, count 2 2006.257.22:30:53.32#ibcon#flushed, iclass 7, count 2 2006.257.22:30:53.32#ibcon#about to write, iclass 7, count 2 2006.257.22:30:53.32#ibcon#wrote, iclass 7, count 2 2006.257.22:30:53.32#ibcon#about to read 3, iclass 7, count 2 2006.257.22:30:53.35#ibcon#read 3, iclass 7, count 2 2006.257.22:30:53.35#ibcon#about to read 4, iclass 7, count 2 2006.257.22:30:53.35#ibcon#read 4, iclass 7, count 2 2006.257.22:30:53.35#ibcon#about to read 5, iclass 7, count 2 2006.257.22:30:53.35#ibcon#read 5, iclass 7, count 2 2006.257.22:30:53.35#ibcon#about to read 6, iclass 7, count 2 2006.257.22:30:53.35#ibcon#read 6, iclass 7, count 2 2006.257.22:30:53.35#ibcon#end of sib2, iclass 7, count 2 2006.257.22:30:53.35#ibcon#*after write, iclass 7, count 2 2006.257.22:30:53.35#ibcon#*before return 0, iclass 7, count 2 2006.257.22:30:53.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:53.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:30:53.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.22:30:53.35#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:53.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:53.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:53.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:53.47#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:30:53.47#ibcon#first serial, iclass 7, count 0 2006.257.22:30:53.47#ibcon#enter sib2, iclass 7, count 0 2006.257.22:30:53.47#ibcon#flushed, iclass 7, count 0 2006.257.22:30:53.47#ibcon#about to write, iclass 7, count 0 2006.257.22:30:53.47#ibcon#wrote, iclass 7, count 0 2006.257.22:30:53.47#ibcon#about to read 3, iclass 7, count 0 2006.257.22:30:53.49#ibcon#read 3, iclass 7, count 0 2006.257.22:30:53.49#ibcon#about to read 4, iclass 7, count 0 2006.257.22:30:53.49#ibcon#read 4, iclass 7, count 0 2006.257.22:30:53.49#ibcon#about to read 5, iclass 7, count 0 2006.257.22:30:53.49#ibcon#read 5, iclass 7, count 0 2006.257.22:30:53.49#ibcon#about to read 6, iclass 7, count 0 2006.257.22:30:53.49#ibcon#read 6, iclass 7, count 0 2006.257.22:30:53.49#ibcon#end of sib2, iclass 7, count 0 2006.257.22:30:53.49#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:30:53.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:30:53.49#ibcon#[27=USB\r\n] 2006.257.22:30:53.49#ibcon#*before write, iclass 7, count 0 2006.257.22:30:53.49#ibcon#enter sib2, iclass 7, count 0 2006.257.22:30:53.49#ibcon#flushed, iclass 7, count 0 2006.257.22:30:53.49#ibcon#about to write, iclass 7, count 0 2006.257.22:30:53.49#ibcon#wrote, iclass 7, count 0 2006.257.22:30:53.49#ibcon#about to read 3, iclass 7, count 0 2006.257.22:30:53.52#ibcon#read 3, iclass 7, count 0 2006.257.22:30:53.52#ibcon#about to read 4, iclass 7, count 0 2006.257.22:30:53.52#ibcon#read 4, iclass 7, count 0 2006.257.22:30:53.52#ibcon#about to read 5, iclass 7, count 0 2006.257.22:30:53.52#ibcon#read 5, iclass 7, count 0 2006.257.22:30:53.52#ibcon#about to read 6, iclass 7, count 0 2006.257.22:30:53.52#ibcon#read 6, iclass 7, count 0 2006.257.22:30:53.52#ibcon#end of sib2, iclass 7, count 0 2006.257.22:30:53.52#ibcon#*after write, iclass 7, count 0 2006.257.22:30:53.52#ibcon#*before return 0, iclass 7, count 0 2006.257.22:30:53.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:53.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:30:53.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:30:53.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:30:53.52$vck44/vblo=5,709.99 2006.257.22:30:53.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.22:30:53.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.22:30:53.52#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:53.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:53.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:53.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:53.52#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:30:53.52#ibcon#first serial, iclass 11, count 0 2006.257.22:30:53.52#ibcon#enter sib2, iclass 11, count 0 2006.257.22:30:53.52#ibcon#flushed, iclass 11, count 0 2006.257.22:30:53.52#ibcon#about to write, iclass 11, count 0 2006.257.22:30:53.52#ibcon#wrote, iclass 11, count 0 2006.257.22:30:53.52#ibcon#about to read 3, iclass 11, count 0 2006.257.22:30:53.54#ibcon#read 3, iclass 11, count 0 2006.257.22:30:53.54#ibcon#about to read 4, iclass 11, count 0 2006.257.22:30:53.54#ibcon#read 4, iclass 11, count 0 2006.257.22:30:53.54#ibcon#about to read 5, iclass 11, count 0 2006.257.22:30:53.54#ibcon#read 5, iclass 11, count 0 2006.257.22:30:53.54#ibcon#about to read 6, iclass 11, count 0 2006.257.22:30:53.54#ibcon#read 6, iclass 11, count 0 2006.257.22:30:53.54#ibcon#end of sib2, iclass 11, count 0 2006.257.22:30:53.54#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:30:53.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:30:53.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.22:30:53.54#ibcon#*before write, iclass 11, count 0 2006.257.22:30:53.54#ibcon#enter sib2, iclass 11, count 0 2006.257.22:30:53.54#ibcon#flushed, iclass 11, count 0 2006.257.22:30:53.54#ibcon#about to write, iclass 11, count 0 2006.257.22:30:53.54#ibcon#wrote, iclass 11, count 0 2006.257.22:30:53.54#ibcon#about to read 3, iclass 11, count 0 2006.257.22:30:53.58#ibcon#read 3, iclass 11, count 0 2006.257.22:30:53.58#ibcon#about to read 4, iclass 11, count 0 2006.257.22:30:53.58#ibcon#read 4, iclass 11, count 0 2006.257.22:30:53.58#ibcon#about to read 5, iclass 11, count 0 2006.257.22:30:53.58#ibcon#read 5, iclass 11, count 0 2006.257.22:30:53.58#ibcon#about to read 6, iclass 11, count 0 2006.257.22:30:53.58#ibcon#read 6, iclass 11, count 0 2006.257.22:30:53.58#ibcon#end of sib2, iclass 11, count 0 2006.257.22:30:53.58#ibcon#*after write, iclass 11, count 0 2006.257.22:30:53.58#ibcon#*before return 0, iclass 11, count 0 2006.257.22:30:53.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:53.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:30:53.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:30:53.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:30:53.58$vck44/vb=5,4 2006.257.22:30:53.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.22:30:53.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.22:30:53.58#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:53.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:53.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:53.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:53.64#ibcon#enter wrdev, iclass 13, count 2 2006.257.22:30:53.64#ibcon#first serial, iclass 13, count 2 2006.257.22:30:53.64#ibcon#enter sib2, iclass 13, count 2 2006.257.22:30:53.64#ibcon#flushed, iclass 13, count 2 2006.257.22:30:53.64#ibcon#about to write, iclass 13, count 2 2006.257.22:30:53.64#ibcon#wrote, iclass 13, count 2 2006.257.22:30:53.64#ibcon#about to read 3, iclass 13, count 2 2006.257.22:30:53.66#ibcon#read 3, iclass 13, count 2 2006.257.22:30:53.66#ibcon#about to read 4, iclass 13, count 2 2006.257.22:30:53.66#ibcon#read 4, iclass 13, count 2 2006.257.22:30:53.66#ibcon#about to read 5, iclass 13, count 2 2006.257.22:30:53.66#ibcon#read 5, iclass 13, count 2 2006.257.22:30:53.66#ibcon#about to read 6, iclass 13, count 2 2006.257.22:30:53.66#ibcon#read 6, iclass 13, count 2 2006.257.22:30:53.66#ibcon#end of sib2, iclass 13, count 2 2006.257.22:30:53.66#ibcon#*mode == 0, iclass 13, count 2 2006.257.22:30:53.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.22:30:53.66#ibcon#[27=AT05-04\r\n] 2006.257.22:30:53.66#ibcon#*before write, iclass 13, count 2 2006.257.22:30:53.66#ibcon#enter sib2, iclass 13, count 2 2006.257.22:30:53.66#ibcon#flushed, iclass 13, count 2 2006.257.22:30:53.66#ibcon#about to write, iclass 13, count 2 2006.257.22:30:53.66#ibcon#wrote, iclass 13, count 2 2006.257.22:30:53.66#ibcon#about to read 3, iclass 13, count 2 2006.257.22:30:53.69#ibcon#read 3, iclass 13, count 2 2006.257.22:30:53.69#ibcon#about to read 4, iclass 13, count 2 2006.257.22:30:53.69#ibcon#read 4, iclass 13, count 2 2006.257.22:30:53.69#ibcon#about to read 5, iclass 13, count 2 2006.257.22:30:53.69#ibcon#read 5, iclass 13, count 2 2006.257.22:30:53.69#ibcon#about to read 6, iclass 13, count 2 2006.257.22:30:53.69#ibcon#read 6, iclass 13, count 2 2006.257.22:30:53.69#ibcon#end of sib2, iclass 13, count 2 2006.257.22:30:53.69#ibcon#*after write, iclass 13, count 2 2006.257.22:30:53.69#ibcon#*before return 0, iclass 13, count 2 2006.257.22:30:53.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:53.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:30:53.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.22:30:53.69#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:53.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:53.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:53.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:53.81#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:30:53.81#ibcon#first serial, iclass 13, count 0 2006.257.22:30:53.81#ibcon#enter sib2, iclass 13, count 0 2006.257.22:30:53.81#ibcon#flushed, iclass 13, count 0 2006.257.22:30:53.81#ibcon#about to write, iclass 13, count 0 2006.257.22:30:53.81#ibcon#wrote, iclass 13, count 0 2006.257.22:30:53.81#ibcon#about to read 3, iclass 13, count 0 2006.257.22:30:53.83#ibcon#read 3, iclass 13, count 0 2006.257.22:30:53.83#ibcon#about to read 4, iclass 13, count 0 2006.257.22:30:53.83#ibcon#read 4, iclass 13, count 0 2006.257.22:30:53.83#ibcon#about to read 5, iclass 13, count 0 2006.257.22:30:53.83#ibcon#read 5, iclass 13, count 0 2006.257.22:30:53.83#ibcon#about to read 6, iclass 13, count 0 2006.257.22:30:53.83#ibcon#read 6, iclass 13, count 0 2006.257.22:30:53.83#ibcon#end of sib2, iclass 13, count 0 2006.257.22:30:53.83#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:30:53.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:30:53.83#ibcon#[27=USB\r\n] 2006.257.22:30:53.83#ibcon#*before write, iclass 13, count 0 2006.257.22:30:53.83#ibcon#enter sib2, iclass 13, count 0 2006.257.22:30:53.83#ibcon#flushed, iclass 13, count 0 2006.257.22:30:53.83#ibcon#about to write, iclass 13, count 0 2006.257.22:30:53.83#ibcon#wrote, iclass 13, count 0 2006.257.22:30:53.83#ibcon#about to read 3, iclass 13, count 0 2006.257.22:30:53.86#ibcon#read 3, iclass 13, count 0 2006.257.22:30:53.86#ibcon#about to read 4, iclass 13, count 0 2006.257.22:30:53.86#ibcon#read 4, iclass 13, count 0 2006.257.22:30:53.86#ibcon#about to read 5, iclass 13, count 0 2006.257.22:30:53.86#ibcon#read 5, iclass 13, count 0 2006.257.22:30:53.86#ibcon#about to read 6, iclass 13, count 0 2006.257.22:30:53.86#ibcon#read 6, iclass 13, count 0 2006.257.22:30:53.86#ibcon#end of sib2, iclass 13, count 0 2006.257.22:30:53.86#ibcon#*after write, iclass 13, count 0 2006.257.22:30:53.86#ibcon#*before return 0, iclass 13, count 0 2006.257.22:30:53.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:53.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:30:53.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:30:53.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:30:53.86$vck44/vblo=6,719.99 2006.257.22:30:53.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.22:30:53.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.22:30:53.86#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:53.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:53.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:53.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:53.86#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:30:53.86#ibcon#first serial, iclass 15, count 0 2006.257.22:30:53.86#ibcon#enter sib2, iclass 15, count 0 2006.257.22:30:53.86#ibcon#flushed, iclass 15, count 0 2006.257.22:30:53.86#ibcon#about to write, iclass 15, count 0 2006.257.22:30:53.86#ibcon#wrote, iclass 15, count 0 2006.257.22:30:53.86#ibcon#about to read 3, iclass 15, count 0 2006.257.22:30:53.88#ibcon#read 3, iclass 15, count 0 2006.257.22:30:53.88#ibcon#about to read 4, iclass 15, count 0 2006.257.22:30:53.88#ibcon#read 4, iclass 15, count 0 2006.257.22:30:53.88#ibcon#about to read 5, iclass 15, count 0 2006.257.22:30:53.88#ibcon#read 5, iclass 15, count 0 2006.257.22:30:53.88#ibcon#about to read 6, iclass 15, count 0 2006.257.22:30:53.88#ibcon#read 6, iclass 15, count 0 2006.257.22:30:53.88#ibcon#end of sib2, iclass 15, count 0 2006.257.22:30:53.88#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:30:53.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:30:53.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.22:30:53.88#ibcon#*before write, iclass 15, count 0 2006.257.22:30:53.88#ibcon#enter sib2, iclass 15, count 0 2006.257.22:30:53.88#ibcon#flushed, iclass 15, count 0 2006.257.22:30:53.88#ibcon#about to write, iclass 15, count 0 2006.257.22:30:53.88#ibcon#wrote, iclass 15, count 0 2006.257.22:30:53.88#ibcon#about to read 3, iclass 15, count 0 2006.257.22:30:53.92#ibcon#read 3, iclass 15, count 0 2006.257.22:30:53.92#ibcon#about to read 4, iclass 15, count 0 2006.257.22:30:53.92#ibcon#read 4, iclass 15, count 0 2006.257.22:30:53.92#ibcon#about to read 5, iclass 15, count 0 2006.257.22:30:53.92#ibcon#read 5, iclass 15, count 0 2006.257.22:30:53.92#ibcon#about to read 6, iclass 15, count 0 2006.257.22:30:53.92#ibcon#read 6, iclass 15, count 0 2006.257.22:30:53.92#ibcon#end of sib2, iclass 15, count 0 2006.257.22:30:53.92#ibcon#*after write, iclass 15, count 0 2006.257.22:30:53.92#ibcon#*before return 0, iclass 15, count 0 2006.257.22:30:53.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:53.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:30:53.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:30:53.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:30:53.92$vck44/vb=6,4 2006.257.22:30:53.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.22:30:53.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.22:30:53.92#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:53.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:53.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:53.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:53.98#ibcon#enter wrdev, iclass 17, count 2 2006.257.22:30:53.98#ibcon#first serial, iclass 17, count 2 2006.257.22:30:53.98#ibcon#enter sib2, iclass 17, count 2 2006.257.22:30:53.98#ibcon#flushed, iclass 17, count 2 2006.257.22:30:53.98#ibcon#about to write, iclass 17, count 2 2006.257.22:30:53.98#ibcon#wrote, iclass 17, count 2 2006.257.22:30:53.98#ibcon#about to read 3, iclass 17, count 2 2006.257.22:30:54.00#ibcon#read 3, iclass 17, count 2 2006.257.22:30:54.00#ibcon#about to read 4, iclass 17, count 2 2006.257.22:30:54.00#ibcon#read 4, iclass 17, count 2 2006.257.22:30:54.00#ibcon#about to read 5, iclass 17, count 2 2006.257.22:30:54.00#ibcon#read 5, iclass 17, count 2 2006.257.22:30:54.00#ibcon#about to read 6, iclass 17, count 2 2006.257.22:30:54.00#ibcon#read 6, iclass 17, count 2 2006.257.22:30:54.00#ibcon#end of sib2, iclass 17, count 2 2006.257.22:30:54.00#ibcon#*mode == 0, iclass 17, count 2 2006.257.22:30:54.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.22:30:54.00#ibcon#[27=AT06-04\r\n] 2006.257.22:30:54.00#ibcon#*before write, iclass 17, count 2 2006.257.22:30:54.00#ibcon#enter sib2, iclass 17, count 2 2006.257.22:30:54.00#ibcon#flushed, iclass 17, count 2 2006.257.22:30:54.00#ibcon#about to write, iclass 17, count 2 2006.257.22:30:54.00#ibcon#wrote, iclass 17, count 2 2006.257.22:30:54.00#ibcon#about to read 3, iclass 17, count 2 2006.257.22:30:54.03#ibcon#read 3, iclass 17, count 2 2006.257.22:30:54.03#ibcon#about to read 4, iclass 17, count 2 2006.257.22:30:54.03#ibcon#read 4, iclass 17, count 2 2006.257.22:30:54.03#ibcon#about to read 5, iclass 17, count 2 2006.257.22:30:54.03#ibcon#read 5, iclass 17, count 2 2006.257.22:30:54.03#ibcon#about to read 6, iclass 17, count 2 2006.257.22:30:54.03#ibcon#read 6, iclass 17, count 2 2006.257.22:30:54.03#ibcon#end of sib2, iclass 17, count 2 2006.257.22:30:54.03#ibcon#*after write, iclass 17, count 2 2006.257.22:30:54.03#ibcon#*before return 0, iclass 17, count 2 2006.257.22:30:54.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:54.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:30:54.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.22:30:54.03#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:54.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:54.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:54.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:54.15#ibcon#enter wrdev, iclass 17, count 0 2006.257.22:30:54.15#ibcon#first serial, iclass 17, count 0 2006.257.22:30:54.15#ibcon#enter sib2, iclass 17, count 0 2006.257.22:30:54.15#ibcon#flushed, iclass 17, count 0 2006.257.22:30:54.15#ibcon#about to write, iclass 17, count 0 2006.257.22:30:54.15#ibcon#wrote, iclass 17, count 0 2006.257.22:30:54.15#ibcon#about to read 3, iclass 17, count 0 2006.257.22:30:54.17#ibcon#read 3, iclass 17, count 0 2006.257.22:30:54.17#ibcon#about to read 4, iclass 17, count 0 2006.257.22:30:54.17#ibcon#read 4, iclass 17, count 0 2006.257.22:30:54.17#ibcon#about to read 5, iclass 17, count 0 2006.257.22:30:54.17#ibcon#read 5, iclass 17, count 0 2006.257.22:30:54.17#ibcon#about to read 6, iclass 17, count 0 2006.257.22:30:54.17#ibcon#read 6, iclass 17, count 0 2006.257.22:30:54.17#ibcon#end of sib2, iclass 17, count 0 2006.257.22:30:54.17#ibcon#*mode == 0, iclass 17, count 0 2006.257.22:30:54.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.22:30:54.17#ibcon#[27=USB\r\n] 2006.257.22:30:54.17#ibcon#*before write, iclass 17, count 0 2006.257.22:30:54.17#ibcon#enter sib2, iclass 17, count 0 2006.257.22:30:54.17#ibcon#flushed, iclass 17, count 0 2006.257.22:30:54.17#ibcon#about to write, iclass 17, count 0 2006.257.22:30:54.17#ibcon#wrote, iclass 17, count 0 2006.257.22:30:54.17#ibcon#about to read 3, iclass 17, count 0 2006.257.22:30:54.20#ibcon#read 3, iclass 17, count 0 2006.257.22:30:54.20#ibcon#about to read 4, iclass 17, count 0 2006.257.22:30:54.20#ibcon#read 4, iclass 17, count 0 2006.257.22:30:54.20#ibcon#about to read 5, iclass 17, count 0 2006.257.22:30:54.20#ibcon#read 5, iclass 17, count 0 2006.257.22:30:54.20#ibcon#about to read 6, iclass 17, count 0 2006.257.22:30:54.20#ibcon#read 6, iclass 17, count 0 2006.257.22:30:54.20#ibcon#end of sib2, iclass 17, count 0 2006.257.22:30:54.20#ibcon#*after write, iclass 17, count 0 2006.257.22:30:54.20#ibcon#*before return 0, iclass 17, count 0 2006.257.22:30:54.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:54.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:30:54.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.22:30:54.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.22:30:54.20$vck44/vblo=7,734.99 2006.257.22:30:54.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.22:30:54.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.22:30:54.20#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:54.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:54.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:54.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:54.20#ibcon#enter wrdev, iclass 19, count 0 2006.257.22:30:54.20#ibcon#first serial, iclass 19, count 0 2006.257.22:30:54.20#ibcon#enter sib2, iclass 19, count 0 2006.257.22:30:54.20#ibcon#flushed, iclass 19, count 0 2006.257.22:30:54.20#ibcon#about to write, iclass 19, count 0 2006.257.22:30:54.20#ibcon#wrote, iclass 19, count 0 2006.257.22:30:54.20#ibcon#about to read 3, iclass 19, count 0 2006.257.22:30:54.22#ibcon#read 3, iclass 19, count 0 2006.257.22:30:54.22#ibcon#about to read 4, iclass 19, count 0 2006.257.22:30:54.22#ibcon#read 4, iclass 19, count 0 2006.257.22:30:54.22#ibcon#about to read 5, iclass 19, count 0 2006.257.22:30:54.22#ibcon#read 5, iclass 19, count 0 2006.257.22:30:54.22#ibcon#about to read 6, iclass 19, count 0 2006.257.22:30:54.22#ibcon#read 6, iclass 19, count 0 2006.257.22:30:54.22#ibcon#end of sib2, iclass 19, count 0 2006.257.22:30:54.22#ibcon#*mode == 0, iclass 19, count 0 2006.257.22:30:54.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.22:30:54.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.22:30:54.22#ibcon#*before write, iclass 19, count 0 2006.257.22:30:54.22#ibcon#enter sib2, iclass 19, count 0 2006.257.22:30:54.22#ibcon#flushed, iclass 19, count 0 2006.257.22:30:54.22#ibcon#about to write, iclass 19, count 0 2006.257.22:30:54.22#ibcon#wrote, iclass 19, count 0 2006.257.22:30:54.22#ibcon#about to read 3, iclass 19, count 0 2006.257.22:30:54.26#ibcon#read 3, iclass 19, count 0 2006.257.22:30:54.26#ibcon#about to read 4, iclass 19, count 0 2006.257.22:30:54.26#ibcon#read 4, iclass 19, count 0 2006.257.22:30:54.26#ibcon#about to read 5, iclass 19, count 0 2006.257.22:30:54.26#ibcon#read 5, iclass 19, count 0 2006.257.22:30:54.26#ibcon#about to read 6, iclass 19, count 0 2006.257.22:30:54.26#ibcon#read 6, iclass 19, count 0 2006.257.22:30:54.26#ibcon#end of sib2, iclass 19, count 0 2006.257.22:30:54.26#ibcon#*after write, iclass 19, count 0 2006.257.22:30:54.26#ibcon#*before return 0, iclass 19, count 0 2006.257.22:30:54.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:54.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:30:54.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.22:30:54.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.22:30:54.26$vck44/vb=7,4 2006.257.22:30:54.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.22:30:54.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.22:30:54.26#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:54.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:54.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:54.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:54.32#ibcon#enter wrdev, iclass 21, count 2 2006.257.22:30:54.32#ibcon#first serial, iclass 21, count 2 2006.257.22:30:54.32#ibcon#enter sib2, iclass 21, count 2 2006.257.22:30:54.32#ibcon#flushed, iclass 21, count 2 2006.257.22:30:54.32#ibcon#about to write, iclass 21, count 2 2006.257.22:30:54.32#ibcon#wrote, iclass 21, count 2 2006.257.22:30:54.32#ibcon#about to read 3, iclass 21, count 2 2006.257.22:30:54.34#ibcon#read 3, iclass 21, count 2 2006.257.22:30:54.34#ibcon#about to read 4, iclass 21, count 2 2006.257.22:30:54.34#ibcon#read 4, iclass 21, count 2 2006.257.22:30:54.34#ibcon#about to read 5, iclass 21, count 2 2006.257.22:30:54.34#ibcon#read 5, iclass 21, count 2 2006.257.22:30:54.34#ibcon#about to read 6, iclass 21, count 2 2006.257.22:30:54.34#ibcon#read 6, iclass 21, count 2 2006.257.22:30:54.34#ibcon#end of sib2, iclass 21, count 2 2006.257.22:30:54.34#ibcon#*mode == 0, iclass 21, count 2 2006.257.22:30:54.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.22:30:54.34#ibcon#[27=AT07-04\r\n] 2006.257.22:30:54.34#ibcon#*before write, iclass 21, count 2 2006.257.22:30:54.34#ibcon#enter sib2, iclass 21, count 2 2006.257.22:30:54.34#ibcon#flushed, iclass 21, count 2 2006.257.22:30:54.34#ibcon#about to write, iclass 21, count 2 2006.257.22:30:54.34#ibcon#wrote, iclass 21, count 2 2006.257.22:30:54.34#ibcon#about to read 3, iclass 21, count 2 2006.257.22:30:54.37#ibcon#read 3, iclass 21, count 2 2006.257.22:30:54.37#ibcon#about to read 4, iclass 21, count 2 2006.257.22:30:54.37#ibcon#read 4, iclass 21, count 2 2006.257.22:30:54.37#ibcon#about to read 5, iclass 21, count 2 2006.257.22:30:54.37#ibcon#read 5, iclass 21, count 2 2006.257.22:30:54.37#ibcon#about to read 6, iclass 21, count 2 2006.257.22:30:54.37#ibcon#read 6, iclass 21, count 2 2006.257.22:30:54.37#ibcon#end of sib2, iclass 21, count 2 2006.257.22:30:54.37#ibcon#*after write, iclass 21, count 2 2006.257.22:30:54.37#ibcon#*before return 0, iclass 21, count 2 2006.257.22:30:54.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:54.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:30:54.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.22:30:54.37#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:54.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:54.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:54.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:54.49#ibcon#enter wrdev, iclass 21, count 0 2006.257.22:30:54.49#ibcon#first serial, iclass 21, count 0 2006.257.22:30:54.49#ibcon#enter sib2, iclass 21, count 0 2006.257.22:30:54.49#ibcon#flushed, iclass 21, count 0 2006.257.22:30:54.49#ibcon#about to write, iclass 21, count 0 2006.257.22:30:54.49#ibcon#wrote, iclass 21, count 0 2006.257.22:30:54.49#ibcon#about to read 3, iclass 21, count 0 2006.257.22:30:54.51#ibcon#read 3, iclass 21, count 0 2006.257.22:30:54.51#ibcon#about to read 4, iclass 21, count 0 2006.257.22:30:54.51#ibcon#read 4, iclass 21, count 0 2006.257.22:30:54.51#ibcon#about to read 5, iclass 21, count 0 2006.257.22:30:54.51#ibcon#read 5, iclass 21, count 0 2006.257.22:30:54.51#ibcon#about to read 6, iclass 21, count 0 2006.257.22:30:54.51#ibcon#read 6, iclass 21, count 0 2006.257.22:30:54.51#ibcon#end of sib2, iclass 21, count 0 2006.257.22:30:54.51#ibcon#*mode == 0, iclass 21, count 0 2006.257.22:30:54.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.22:30:54.51#ibcon#[27=USB\r\n] 2006.257.22:30:54.51#ibcon#*before write, iclass 21, count 0 2006.257.22:30:54.51#ibcon#enter sib2, iclass 21, count 0 2006.257.22:30:54.51#ibcon#flushed, iclass 21, count 0 2006.257.22:30:54.51#ibcon#about to write, iclass 21, count 0 2006.257.22:30:54.51#ibcon#wrote, iclass 21, count 0 2006.257.22:30:54.51#ibcon#about to read 3, iclass 21, count 0 2006.257.22:30:54.54#ibcon#read 3, iclass 21, count 0 2006.257.22:30:54.54#ibcon#about to read 4, iclass 21, count 0 2006.257.22:30:54.54#ibcon#read 4, iclass 21, count 0 2006.257.22:30:54.54#ibcon#about to read 5, iclass 21, count 0 2006.257.22:30:54.54#ibcon#read 5, iclass 21, count 0 2006.257.22:30:54.54#ibcon#about to read 6, iclass 21, count 0 2006.257.22:30:54.54#ibcon#read 6, iclass 21, count 0 2006.257.22:30:54.54#ibcon#end of sib2, iclass 21, count 0 2006.257.22:30:54.54#ibcon#*after write, iclass 21, count 0 2006.257.22:30:54.54#ibcon#*before return 0, iclass 21, count 0 2006.257.22:30:54.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:54.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:30:54.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.22:30:54.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.22:30:54.54$vck44/vblo=8,744.99 2006.257.22:30:54.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.22:30:54.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.22:30:54.54#ibcon#ireg 17 cls_cnt 0 2006.257.22:30:54.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:54.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:54.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:54.54#ibcon#enter wrdev, iclass 23, count 0 2006.257.22:30:54.54#ibcon#first serial, iclass 23, count 0 2006.257.22:30:54.54#ibcon#enter sib2, iclass 23, count 0 2006.257.22:30:54.54#ibcon#flushed, iclass 23, count 0 2006.257.22:30:54.54#ibcon#about to write, iclass 23, count 0 2006.257.22:30:54.54#ibcon#wrote, iclass 23, count 0 2006.257.22:30:54.54#ibcon#about to read 3, iclass 23, count 0 2006.257.22:30:54.56#ibcon#read 3, iclass 23, count 0 2006.257.22:30:54.56#ibcon#about to read 4, iclass 23, count 0 2006.257.22:30:54.56#ibcon#read 4, iclass 23, count 0 2006.257.22:30:54.56#ibcon#about to read 5, iclass 23, count 0 2006.257.22:30:54.56#ibcon#read 5, iclass 23, count 0 2006.257.22:30:54.56#ibcon#about to read 6, iclass 23, count 0 2006.257.22:30:54.56#ibcon#read 6, iclass 23, count 0 2006.257.22:30:54.56#ibcon#end of sib2, iclass 23, count 0 2006.257.22:30:54.56#ibcon#*mode == 0, iclass 23, count 0 2006.257.22:30:54.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.22:30:54.56#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.22:30:54.56#ibcon#*before write, iclass 23, count 0 2006.257.22:30:54.56#ibcon#enter sib2, iclass 23, count 0 2006.257.22:30:54.56#ibcon#flushed, iclass 23, count 0 2006.257.22:30:54.56#ibcon#about to write, iclass 23, count 0 2006.257.22:30:54.56#ibcon#wrote, iclass 23, count 0 2006.257.22:30:54.56#ibcon#about to read 3, iclass 23, count 0 2006.257.22:30:54.60#ibcon#read 3, iclass 23, count 0 2006.257.22:30:54.60#ibcon#about to read 4, iclass 23, count 0 2006.257.22:30:54.60#ibcon#read 4, iclass 23, count 0 2006.257.22:30:54.60#ibcon#about to read 5, iclass 23, count 0 2006.257.22:30:54.60#ibcon#read 5, iclass 23, count 0 2006.257.22:30:54.60#ibcon#about to read 6, iclass 23, count 0 2006.257.22:30:54.60#ibcon#read 6, iclass 23, count 0 2006.257.22:30:54.60#ibcon#end of sib2, iclass 23, count 0 2006.257.22:30:54.60#ibcon#*after write, iclass 23, count 0 2006.257.22:30:54.60#ibcon#*before return 0, iclass 23, count 0 2006.257.22:30:54.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:54.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:30:54.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.22:30:54.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.22:30:54.60$vck44/vb=8,4 2006.257.22:30:54.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.22:30:54.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.22:30:54.60#ibcon#ireg 11 cls_cnt 2 2006.257.22:30:54.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:54.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:54.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:54.66#ibcon#enter wrdev, iclass 25, count 2 2006.257.22:30:54.66#ibcon#first serial, iclass 25, count 2 2006.257.22:30:54.66#ibcon#enter sib2, iclass 25, count 2 2006.257.22:30:54.66#ibcon#flushed, iclass 25, count 2 2006.257.22:30:54.66#ibcon#about to write, iclass 25, count 2 2006.257.22:30:54.66#ibcon#wrote, iclass 25, count 2 2006.257.22:30:54.66#ibcon#about to read 3, iclass 25, count 2 2006.257.22:30:54.68#ibcon#read 3, iclass 25, count 2 2006.257.22:30:54.68#ibcon#about to read 4, iclass 25, count 2 2006.257.22:30:54.68#ibcon#read 4, iclass 25, count 2 2006.257.22:30:54.68#ibcon#about to read 5, iclass 25, count 2 2006.257.22:30:54.68#ibcon#read 5, iclass 25, count 2 2006.257.22:30:54.68#ibcon#about to read 6, iclass 25, count 2 2006.257.22:30:54.68#ibcon#read 6, iclass 25, count 2 2006.257.22:30:54.68#ibcon#end of sib2, iclass 25, count 2 2006.257.22:30:54.68#ibcon#*mode == 0, iclass 25, count 2 2006.257.22:30:54.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.22:30:54.68#ibcon#[27=AT08-04\r\n] 2006.257.22:30:54.68#ibcon#*before write, iclass 25, count 2 2006.257.22:30:54.68#ibcon#enter sib2, iclass 25, count 2 2006.257.22:30:54.68#ibcon#flushed, iclass 25, count 2 2006.257.22:30:54.68#ibcon#about to write, iclass 25, count 2 2006.257.22:30:54.68#ibcon#wrote, iclass 25, count 2 2006.257.22:30:54.68#ibcon#about to read 3, iclass 25, count 2 2006.257.22:30:54.71#ibcon#read 3, iclass 25, count 2 2006.257.22:30:54.71#ibcon#about to read 4, iclass 25, count 2 2006.257.22:30:54.71#ibcon#read 4, iclass 25, count 2 2006.257.22:30:54.71#ibcon#about to read 5, iclass 25, count 2 2006.257.22:30:54.71#ibcon#read 5, iclass 25, count 2 2006.257.22:30:54.71#ibcon#about to read 6, iclass 25, count 2 2006.257.22:30:54.71#ibcon#read 6, iclass 25, count 2 2006.257.22:30:54.71#ibcon#end of sib2, iclass 25, count 2 2006.257.22:30:54.71#ibcon#*after write, iclass 25, count 2 2006.257.22:30:54.71#ibcon#*before return 0, iclass 25, count 2 2006.257.22:30:54.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:54.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:30:54.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.22:30:54.71#ibcon#ireg 7 cls_cnt 0 2006.257.22:30:54.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:54.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:54.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:54.83#ibcon#enter wrdev, iclass 25, count 0 2006.257.22:30:54.83#ibcon#first serial, iclass 25, count 0 2006.257.22:30:54.83#ibcon#enter sib2, iclass 25, count 0 2006.257.22:30:54.83#ibcon#flushed, iclass 25, count 0 2006.257.22:30:54.83#ibcon#about to write, iclass 25, count 0 2006.257.22:30:54.83#ibcon#wrote, iclass 25, count 0 2006.257.22:30:54.83#ibcon#about to read 3, iclass 25, count 0 2006.257.22:30:54.85#ibcon#read 3, iclass 25, count 0 2006.257.22:30:54.85#ibcon#about to read 4, iclass 25, count 0 2006.257.22:30:54.85#ibcon#read 4, iclass 25, count 0 2006.257.22:30:54.85#ibcon#about to read 5, iclass 25, count 0 2006.257.22:30:54.85#ibcon#read 5, iclass 25, count 0 2006.257.22:30:54.85#ibcon#about to read 6, iclass 25, count 0 2006.257.22:30:54.85#ibcon#read 6, iclass 25, count 0 2006.257.22:30:54.85#ibcon#end of sib2, iclass 25, count 0 2006.257.22:30:54.85#ibcon#*mode == 0, iclass 25, count 0 2006.257.22:30:54.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.22:30:54.85#ibcon#[27=USB\r\n] 2006.257.22:30:54.85#ibcon#*before write, iclass 25, count 0 2006.257.22:30:54.85#ibcon#enter sib2, iclass 25, count 0 2006.257.22:30:54.85#ibcon#flushed, iclass 25, count 0 2006.257.22:30:54.85#ibcon#about to write, iclass 25, count 0 2006.257.22:30:54.85#ibcon#wrote, iclass 25, count 0 2006.257.22:30:54.85#ibcon#about to read 3, iclass 25, count 0 2006.257.22:30:54.88#ibcon#read 3, iclass 25, count 0 2006.257.22:30:54.88#ibcon#about to read 4, iclass 25, count 0 2006.257.22:30:54.88#ibcon#read 4, iclass 25, count 0 2006.257.22:30:54.88#ibcon#about to read 5, iclass 25, count 0 2006.257.22:30:54.88#ibcon#read 5, iclass 25, count 0 2006.257.22:30:54.88#ibcon#about to read 6, iclass 25, count 0 2006.257.22:30:54.88#ibcon#read 6, iclass 25, count 0 2006.257.22:30:54.88#ibcon#end of sib2, iclass 25, count 0 2006.257.22:30:54.88#ibcon#*after write, iclass 25, count 0 2006.257.22:30:54.88#ibcon#*before return 0, iclass 25, count 0 2006.257.22:30:54.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:54.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:30:54.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.22:30:54.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.22:30:54.88$vck44/vabw=wide 2006.257.22:30:54.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.22:30:54.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.22:30:54.88#ibcon#ireg 8 cls_cnt 0 2006.257.22:30:54.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:54.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:54.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:54.88#ibcon#enter wrdev, iclass 27, count 0 2006.257.22:30:54.88#ibcon#first serial, iclass 27, count 0 2006.257.22:30:54.88#ibcon#enter sib2, iclass 27, count 0 2006.257.22:30:54.88#ibcon#flushed, iclass 27, count 0 2006.257.22:30:54.88#ibcon#about to write, iclass 27, count 0 2006.257.22:30:54.88#ibcon#wrote, iclass 27, count 0 2006.257.22:30:54.88#ibcon#about to read 3, iclass 27, count 0 2006.257.22:30:54.90#ibcon#read 3, iclass 27, count 0 2006.257.22:30:54.90#ibcon#about to read 4, iclass 27, count 0 2006.257.22:30:54.90#ibcon#read 4, iclass 27, count 0 2006.257.22:30:54.90#ibcon#about to read 5, iclass 27, count 0 2006.257.22:30:54.90#ibcon#read 5, iclass 27, count 0 2006.257.22:30:54.90#ibcon#about to read 6, iclass 27, count 0 2006.257.22:30:54.90#ibcon#read 6, iclass 27, count 0 2006.257.22:30:54.90#ibcon#end of sib2, iclass 27, count 0 2006.257.22:30:54.90#ibcon#*mode == 0, iclass 27, count 0 2006.257.22:30:54.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.22:30:54.90#ibcon#[25=BW32\r\n] 2006.257.22:30:54.90#ibcon#*before write, iclass 27, count 0 2006.257.22:30:54.90#ibcon#enter sib2, iclass 27, count 0 2006.257.22:30:54.90#ibcon#flushed, iclass 27, count 0 2006.257.22:30:54.90#ibcon#about to write, iclass 27, count 0 2006.257.22:30:54.90#ibcon#wrote, iclass 27, count 0 2006.257.22:30:54.90#ibcon#about to read 3, iclass 27, count 0 2006.257.22:30:54.93#ibcon#read 3, iclass 27, count 0 2006.257.22:30:54.93#ibcon#about to read 4, iclass 27, count 0 2006.257.22:30:54.93#ibcon#read 4, iclass 27, count 0 2006.257.22:30:54.93#ibcon#about to read 5, iclass 27, count 0 2006.257.22:30:54.93#ibcon#read 5, iclass 27, count 0 2006.257.22:30:54.93#ibcon#about to read 6, iclass 27, count 0 2006.257.22:30:54.93#ibcon#read 6, iclass 27, count 0 2006.257.22:30:54.93#ibcon#end of sib2, iclass 27, count 0 2006.257.22:30:54.93#ibcon#*after write, iclass 27, count 0 2006.257.22:30:54.93#ibcon#*before return 0, iclass 27, count 0 2006.257.22:30:54.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:54.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:30:54.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.22:30:54.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.22:30:54.93$vck44/vbbw=wide 2006.257.22:30:54.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.22:30:54.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.22:30:54.93#ibcon#ireg 8 cls_cnt 0 2006.257.22:30:54.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:30:55.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:30:55.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:30:55.00#ibcon#enter wrdev, iclass 29, count 0 2006.257.22:30:55.00#ibcon#first serial, iclass 29, count 0 2006.257.22:30:55.00#ibcon#enter sib2, iclass 29, count 0 2006.257.22:30:55.00#ibcon#flushed, iclass 29, count 0 2006.257.22:30:55.00#ibcon#about to write, iclass 29, count 0 2006.257.22:30:55.00#ibcon#wrote, iclass 29, count 0 2006.257.22:30:55.00#ibcon#about to read 3, iclass 29, count 0 2006.257.22:30:55.02#ibcon#read 3, iclass 29, count 0 2006.257.22:30:55.02#ibcon#about to read 4, iclass 29, count 0 2006.257.22:30:55.02#ibcon#read 4, iclass 29, count 0 2006.257.22:30:55.02#ibcon#about to read 5, iclass 29, count 0 2006.257.22:30:55.02#ibcon#read 5, iclass 29, count 0 2006.257.22:30:55.02#ibcon#about to read 6, iclass 29, count 0 2006.257.22:30:55.02#ibcon#read 6, iclass 29, count 0 2006.257.22:30:55.02#ibcon#end of sib2, iclass 29, count 0 2006.257.22:30:55.02#ibcon#*mode == 0, iclass 29, count 0 2006.257.22:30:55.02#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.22:30:55.02#ibcon#[27=BW32\r\n] 2006.257.22:30:55.02#ibcon#*before write, iclass 29, count 0 2006.257.22:30:55.02#ibcon#enter sib2, iclass 29, count 0 2006.257.22:30:55.02#ibcon#flushed, iclass 29, count 0 2006.257.22:30:55.02#ibcon#about to write, iclass 29, count 0 2006.257.22:30:55.02#ibcon#wrote, iclass 29, count 0 2006.257.22:30:55.02#ibcon#about to read 3, iclass 29, count 0 2006.257.22:30:55.05#ibcon#read 3, iclass 29, count 0 2006.257.22:30:55.05#ibcon#about to read 4, iclass 29, count 0 2006.257.22:30:55.05#ibcon#read 4, iclass 29, count 0 2006.257.22:30:55.05#ibcon#about to read 5, iclass 29, count 0 2006.257.22:30:55.05#ibcon#read 5, iclass 29, count 0 2006.257.22:30:55.05#ibcon#about to read 6, iclass 29, count 0 2006.257.22:30:55.05#ibcon#read 6, iclass 29, count 0 2006.257.22:30:55.05#ibcon#end of sib2, iclass 29, count 0 2006.257.22:30:55.05#ibcon#*after write, iclass 29, count 0 2006.257.22:30:55.05#ibcon#*before return 0, iclass 29, count 0 2006.257.22:30:55.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:30:55.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:30:55.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.22:30:55.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.22:30:55.05$setupk4/ifdk4 2006.257.22:30:55.05$ifdk4/lo= 2006.257.22:30:55.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.22:30:55.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.22:30:55.05$ifdk4/patch= 2006.257.22:30:55.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.22:30:55.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.22:30:55.05$setupk4/!*+20s 2006.257.22:30:55.56#abcon#<5=/13 0.9 2.6 19.36 871016.0\r\n> 2006.257.22:30:55.58#abcon#{5=INTERFACE CLEAR} 2006.257.22:30:55.64#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:31:05.73#abcon#<5=/13 0.9 2.6 19.36 871016.0\r\n> 2006.257.22:31:05.75#abcon#{5=INTERFACE CLEAR} 2006.257.22:31:05.81#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:31:09.56$setupk4/"tpicd 2006.257.22:31:09.56$setupk4/echo=off 2006.257.22:31:09.56$setupk4/xlog=off 2006.257.22:31:09.56:!2006.257.22:33:59 2006.257.22:31:22.14#trakl#Source acquired 2006.257.22:31:22.14#flagr#flagr/antenna,acquired 2006.257.22:33:59.00:preob 2006.257.22:33:59.13/onsource/TRACKING 2006.257.22:33:59.13:!2006.257.22:34:09 2006.257.22:34:09.00:"tape 2006.257.22:34:09.00:"st=record 2006.257.22:34:09.00:data_valid=on 2006.257.22:34:09.00:midob 2006.257.22:34:10.13/onsource/TRACKING 2006.257.22:34:10.13/wx/19.42,1016.0,87 2006.257.22:34:10.27/cable/+6.4843E-03 2006.257.22:34:11.36/va/01,08,usb,yes,30,32 2006.257.22:34:11.36/va/02,07,usb,yes,33,33 2006.257.22:34:11.36/va/03,08,usb,yes,29,31 2006.257.22:34:11.36/va/04,07,usb,yes,34,35 2006.257.22:34:11.36/va/05,04,usb,yes,30,31 2006.257.22:34:11.36/va/06,04,usb,yes,34,33 2006.257.22:34:11.36/va/07,04,usb,yes,35,35 2006.257.22:34:11.36/va/08,04,usb,yes,29,35 2006.257.22:34:11.59/valo/01,524.99,yes,locked 2006.257.22:34:11.59/valo/02,534.99,yes,locked 2006.257.22:34:11.59/valo/03,564.99,yes,locked 2006.257.22:34:11.59/valo/04,624.99,yes,locked 2006.257.22:34:11.59/valo/05,734.99,yes,locked 2006.257.22:34:11.59/valo/06,814.99,yes,locked 2006.257.22:34:11.59/valo/07,864.99,yes,locked 2006.257.22:34:11.59/valo/08,884.99,yes,locked 2006.257.22:34:12.68/vb/01,04,usb,yes,30,28 2006.257.22:34:12.68/vb/02,05,usb,yes,29,29 2006.257.22:34:12.68/vb/03,04,usb,yes,30,33 2006.257.22:34:12.68/vb/04,05,usb,yes,30,29 2006.257.22:34:12.68/vb/05,04,usb,yes,26,29 2006.257.22:34:12.68/vb/06,04,usb,yes,31,27 2006.257.22:34:12.68/vb/07,04,usb,yes,31,31 2006.257.22:34:12.68/vb/08,04,usb,yes,28,32 2006.257.22:34:12.91/vblo/01,629.99,yes,locked 2006.257.22:34:12.91/vblo/02,634.99,yes,locked 2006.257.22:34:12.91/vblo/03,649.99,yes,locked 2006.257.22:34:12.91/vblo/04,679.99,yes,locked 2006.257.22:34:12.91/vblo/05,709.99,yes,locked 2006.257.22:34:12.91/vblo/06,719.99,yes,locked 2006.257.22:34:12.91/vblo/07,734.99,yes,locked 2006.257.22:34:12.91/vblo/08,744.99,yes,locked 2006.257.22:34:13.06/vabw/8 2006.257.22:34:13.21/vbbw/8 2006.257.22:34:13.30/xfe/off,on,15.2 2006.257.22:34:13.67/ifatt/23,28,28,28 2006.257.22:34:14.08/fmout-gps/S +4.59E-07 2006.257.22:34:14.12:!2006.257.22:34:59 2006.257.22:34:59.01:data_valid=off 2006.257.22:34:59.01:"et 2006.257.22:34:59.01:!+3s 2006.257.22:35:02.02:"tape 2006.257.22:35:02.02:postob 2006.257.22:35:02.09/cable/+6.4858E-03 2006.257.22:35:02.09/wx/19.43,1016.0,87 2006.257.22:35:02.15/fmout-gps/S +4.62E-07 2006.257.22:35:02.15:scan_name=257-2237,jd0609,120 2006.257.22:35:02.15:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.257.22:35:03.14#flagr#flagr/antenna,new-source 2006.257.22:35:03.14:checkk5 2006.257.22:35:03.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.22:35:03.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.22:35:04.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.22:35:04.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.22:35:04.83/chk_obsdata//k5ts1/T2572234??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.22:35:05.16/chk_obsdata//k5ts2/T2572234??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.22:35:05.50/chk_obsdata//k5ts3/T2572234??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.22:35:05.83/chk_obsdata//k5ts4/T2572234??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.257.22:35:06.49/k5log//k5ts1_log_newline 2006.257.22:35:07.14/k5log//k5ts2_log_newline 2006.257.22:35:07.82/k5log//k5ts3_log_newline 2006.257.22:35:08.47/k5log//k5ts4_log_newline 2006.257.22:35:08.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.22:35:08.49:setupk4=1 2006.257.22:35:08.49$setupk4/echo=on 2006.257.22:35:08.49$setupk4/pcalon 2006.257.22:35:08.49$pcalon/"no phase cal control is implemented here 2006.257.22:35:08.49$setupk4/"tpicd=stop 2006.257.22:35:08.49$setupk4/"rec=synch_on 2006.257.22:35:08.49$setupk4/"rec_mode=128 2006.257.22:35:08.49$setupk4/!* 2006.257.22:35:08.49$setupk4/recpk4 2006.257.22:35:08.50$recpk4/recpatch= 2006.257.22:35:08.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.22:35:08.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.22:35:08.50$setupk4/vck44 2006.257.22:35:08.50$vck44/valo=1,524.99 2006.257.22:35:08.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.22:35:08.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.22:35:08.50#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:08.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:08.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:08.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:08.50#ibcon#enter wrdev, iclass 26, count 0 2006.257.22:35:08.50#ibcon#first serial, iclass 26, count 0 2006.257.22:35:08.50#ibcon#enter sib2, iclass 26, count 0 2006.257.22:35:08.50#ibcon#flushed, iclass 26, count 0 2006.257.22:35:08.50#ibcon#about to write, iclass 26, count 0 2006.257.22:35:08.50#ibcon#wrote, iclass 26, count 0 2006.257.22:35:08.50#ibcon#about to read 3, iclass 26, count 0 2006.257.22:35:08.52#ibcon#read 3, iclass 26, count 0 2006.257.22:35:08.52#ibcon#about to read 4, iclass 26, count 0 2006.257.22:35:08.52#ibcon#read 4, iclass 26, count 0 2006.257.22:35:08.52#ibcon#about to read 5, iclass 26, count 0 2006.257.22:35:08.52#ibcon#read 5, iclass 26, count 0 2006.257.22:35:08.52#ibcon#about to read 6, iclass 26, count 0 2006.257.22:35:08.52#ibcon#read 6, iclass 26, count 0 2006.257.22:35:08.52#ibcon#end of sib2, iclass 26, count 0 2006.257.22:35:08.52#ibcon#*mode == 0, iclass 26, count 0 2006.257.22:35:08.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.22:35:08.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.22:35:08.52#ibcon#*before write, iclass 26, count 0 2006.257.22:35:08.52#ibcon#enter sib2, iclass 26, count 0 2006.257.22:35:08.52#ibcon#flushed, iclass 26, count 0 2006.257.22:35:08.52#ibcon#about to write, iclass 26, count 0 2006.257.22:35:08.52#ibcon#wrote, iclass 26, count 0 2006.257.22:35:08.52#ibcon#about to read 3, iclass 26, count 0 2006.257.22:35:08.57#ibcon#read 3, iclass 26, count 0 2006.257.22:35:08.57#ibcon#about to read 4, iclass 26, count 0 2006.257.22:35:08.57#ibcon#read 4, iclass 26, count 0 2006.257.22:35:08.57#ibcon#about to read 5, iclass 26, count 0 2006.257.22:35:08.57#ibcon#read 5, iclass 26, count 0 2006.257.22:35:08.57#ibcon#about to read 6, iclass 26, count 0 2006.257.22:35:08.57#ibcon#read 6, iclass 26, count 0 2006.257.22:35:08.57#ibcon#end of sib2, iclass 26, count 0 2006.257.22:35:08.57#ibcon#*after write, iclass 26, count 0 2006.257.22:35:08.57#ibcon#*before return 0, iclass 26, count 0 2006.257.22:35:08.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:08.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:08.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.22:35:08.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.22:35:08.57$vck44/va=1,8 2006.257.22:35:08.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.22:35:08.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.22:35:08.57#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:08.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:08.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:08.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:08.57#ibcon#enter wrdev, iclass 28, count 2 2006.257.22:35:08.57#ibcon#first serial, iclass 28, count 2 2006.257.22:35:08.57#ibcon#enter sib2, iclass 28, count 2 2006.257.22:35:08.57#ibcon#flushed, iclass 28, count 2 2006.257.22:35:08.57#ibcon#about to write, iclass 28, count 2 2006.257.22:35:08.57#ibcon#wrote, iclass 28, count 2 2006.257.22:35:08.57#ibcon#about to read 3, iclass 28, count 2 2006.257.22:35:08.59#ibcon#read 3, iclass 28, count 2 2006.257.22:35:08.59#ibcon#about to read 4, iclass 28, count 2 2006.257.22:35:08.59#ibcon#read 4, iclass 28, count 2 2006.257.22:35:08.59#ibcon#about to read 5, iclass 28, count 2 2006.257.22:35:08.59#ibcon#read 5, iclass 28, count 2 2006.257.22:35:08.59#ibcon#about to read 6, iclass 28, count 2 2006.257.22:35:08.59#ibcon#read 6, iclass 28, count 2 2006.257.22:35:08.59#ibcon#end of sib2, iclass 28, count 2 2006.257.22:35:08.59#ibcon#*mode == 0, iclass 28, count 2 2006.257.22:35:08.59#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.22:35:08.59#ibcon#[25=AT01-08\r\n] 2006.257.22:35:08.59#ibcon#*before write, iclass 28, count 2 2006.257.22:35:08.59#ibcon#enter sib2, iclass 28, count 2 2006.257.22:35:08.59#ibcon#flushed, iclass 28, count 2 2006.257.22:35:08.59#ibcon#about to write, iclass 28, count 2 2006.257.22:35:08.59#ibcon#wrote, iclass 28, count 2 2006.257.22:35:08.59#ibcon#about to read 3, iclass 28, count 2 2006.257.22:35:08.62#ibcon#read 3, iclass 28, count 2 2006.257.22:35:08.62#ibcon#about to read 4, iclass 28, count 2 2006.257.22:35:08.62#ibcon#read 4, iclass 28, count 2 2006.257.22:35:08.62#ibcon#about to read 5, iclass 28, count 2 2006.257.22:35:08.62#ibcon#read 5, iclass 28, count 2 2006.257.22:35:08.62#ibcon#about to read 6, iclass 28, count 2 2006.257.22:35:08.62#ibcon#read 6, iclass 28, count 2 2006.257.22:35:08.62#ibcon#end of sib2, iclass 28, count 2 2006.257.22:35:08.62#ibcon#*after write, iclass 28, count 2 2006.257.22:35:08.62#ibcon#*before return 0, iclass 28, count 2 2006.257.22:35:08.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:08.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:08.62#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.22:35:08.62#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:08.62#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:08.74#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:08.74#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:08.74#ibcon#enter wrdev, iclass 28, count 0 2006.257.22:35:08.74#ibcon#first serial, iclass 28, count 0 2006.257.22:35:08.74#ibcon#enter sib2, iclass 28, count 0 2006.257.22:35:08.74#ibcon#flushed, iclass 28, count 0 2006.257.22:35:08.74#ibcon#about to write, iclass 28, count 0 2006.257.22:35:08.74#ibcon#wrote, iclass 28, count 0 2006.257.22:35:08.74#ibcon#about to read 3, iclass 28, count 0 2006.257.22:35:08.76#ibcon#read 3, iclass 28, count 0 2006.257.22:35:08.76#ibcon#about to read 4, iclass 28, count 0 2006.257.22:35:08.76#ibcon#read 4, iclass 28, count 0 2006.257.22:35:08.76#ibcon#about to read 5, iclass 28, count 0 2006.257.22:35:08.76#ibcon#read 5, iclass 28, count 0 2006.257.22:35:08.76#ibcon#about to read 6, iclass 28, count 0 2006.257.22:35:08.76#ibcon#read 6, iclass 28, count 0 2006.257.22:35:08.76#ibcon#end of sib2, iclass 28, count 0 2006.257.22:35:08.76#ibcon#*mode == 0, iclass 28, count 0 2006.257.22:35:08.76#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.22:35:08.76#ibcon#[25=USB\r\n] 2006.257.22:35:08.76#ibcon#*before write, iclass 28, count 0 2006.257.22:35:08.76#ibcon#enter sib2, iclass 28, count 0 2006.257.22:35:08.76#ibcon#flushed, iclass 28, count 0 2006.257.22:35:08.76#ibcon#about to write, iclass 28, count 0 2006.257.22:35:08.76#ibcon#wrote, iclass 28, count 0 2006.257.22:35:08.76#ibcon#about to read 3, iclass 28, count 0 2006.257.22:35:08.79#ibcon#read 3, iclass 28, count 0 2006.257.22:35:08.79#ibcon#about to read 4, iclass 28, count 0 2006.257.22:35:08.79#ibcon#read 4, iclass 28, count 0 2006.257.22:35:08.79#ibcon#about to read 5, iclass 28, count 0 2006.257.22:35:08.79#ibcon#read 5, iclass 28, count 0 2006.257.22:35:08.79#ibcon#about to read 6, iclass 28, count 0 2006.257.22:35:08.79#ibcon#read 6, iclass 28, count 0 2006.257.22:35:08.79#ibcon#end of sib2, iclass 28, count 0 2006.257.22:35:08.79#ibcon#*after write, iclass 28, count 0 2006.257.22:35:08.79#ibcon#*before return 0, iclass 28, count 0 2006.257.22:35:08.79#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:08.79#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:08.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.22:35:08.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.22:35:08.79$vck44/valo=2,534.99 2006.257.22:35:08.79#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.22:35:08.79#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.22:35:08.79#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:08.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:08.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:08.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:08.79#ibcon#enter wrdev, iclass 30, count 0 2006.257.22:35:08.79#ibcon#first serial, iclass 30, count 0 2006.257.22:35:08.79#ibcon#enter sib2, iclass 30, count 0 2006.257.22:35:08.79#ibcon#flushed, iclass 30, count 0 2006.257.22:35:08.79#ibcon#about to write, iclass 30, count 0 2006.257.22:35:08.79#ibcon#wrote, iclass 30, count 0 2006.257.22:35:08.79#ibcon#about to read 3, iclass 30, count 0 2006.257.22:35:08.81#ibcon#read 3, iclass 30, count 0 2006.257.22:35:08.81#ibcon#about to read 4, iclass 30, count 0 2006.257.22:35:08.81#ibcon#read 4, iclass 30, count 0 2006.257.22:35:08.81#ibcon#about to read 5, iclass 30, count 0 2006.257.22:35:08.81#ibcon#read 5, iclass 30, count 0 2006.257.22:35:08.81#ibcon#about to read 6, iclass 30, count 0 2006.257.22:35:08.81#ibcon#read 6, iclass 30, count 0 2006.257.22:35:08.81#ibcon#end of sib2, iclass 30, count 0 2006.257.22:35:08.81#ibcon#*mode == 0, iclass 30, count 0 2006.257.22:35:08.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.22:35:08.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.22:35:08.81#ibcon#*before write, iclass 30, count 0 2006.257.22:35:08.81#ibcon#enter sib2, iclass 30, count 0 2006.257.22:35:08.81#ibcon#flushed, iclass 30, count 0 2006.257.22:35:08.81#ibcon#about to write, iclass 30, count 0 2006.257.22:35:08.81#ibcon#wrote, iclass 30, count 0 2006.257.22:35:08.81#ibcon#about to read 3, iclass 30, count 0 2006.257.22:35:08.85#ibcon#read 3, iclass 30, count 0 2006.257.22:35:08.85#ibcon#about to read 4, iclass 30, count 0 2006.257.22:35:08.85#ibcon#read 4, iclass 30, count 0 2006.257.22:35:08.85#ibcon#about to read 5, iclass 30, count 0 2006.257.22:35:08.85#ibcon#read 5, iclass 30, count 0 2006.257.22:35:08.85#ibcon#about to read 6, iclass 30, count 0 2006.257.22:35:08.85#ibcon#read 6, iclass 30, count 0 2006.257.22:35:08.85#ibcon#end of sib2, iclass 30, count 0 2006.257.22:35:08.85#ibcon#*after write, iclass 30, count 0 2006.257.22:35:08.85#ibcon#*before return 0, iclass 30, count 0 2006.257.22:35:08.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:08.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:08.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.22:35:08.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.22:35:08.85$vck44/va=2,7 2006.257.22:35:08.85#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.22:35:08.85#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.22:35:08.85#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:08.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:08.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:08.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:08.91#ibcon#enter wrdev, iclass 32, count 2 2006.257.22:35:08.91#ibcon#first serial, iclass 32, count 2 2006.257.22:35:08.91#ibcon#enter sib2, iclass 32, count 2 2006.257.22:35:08.91#ibcon#flushed, iclass 32, count 2 2006.257.22:35:08.91#ibcon#about to write, iclass 32, count 2 2006.257.22:35:08.91#ibcon#wrote, iclass 32, count 2 2006.257.22:35:08.91#ibcon#about to read 3, iclass 32, count 2 2006.257.22:35:08.93#ibcon#read 3, iclass 32, count 2 2006.257.22:35:08.93#ibcon#about to read 4, iclass 32, count 2 2006.257.22:35:08.93#ibcon#read 4, iclass 32, count 2 2006.257.22:35:08.93#ibcon#about to read 5, iclass 32, count 2 2006.257.22:35:08.93#ibcon#read 5, iclass 32, count 2 2006.257.22:35:08.93#ibcon#about to read 6, iclass 32, count 2 2006.257.22:35:08.93#ibcon#read 6, iclass 32, count 2 2006.257.22:35:08.93#ibcon#end of sib2, iclass 32, count 2 2006.257.22:35:08.93#ibcon#*mode == 0, iclass 32, count 2 2006.257.22:35:08.93#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.22:35:08.93#ibcon#[25=AT02-07\r\n] 2006.257.22:35:08.93#ibcon#*before write, iclass 32, count 2 2006.257.22:35:08.93#ibcon#enter sib2, iclass 32, count 2 2006.257.22:35:08.93#ibcon#flushed, iclass 32, count 2 2006.257.22:35:08.93#ibcon#about to write, iclass 32, count 2 2006.257.22:35:08.93#ibcon#wrote, iclass 32, count 2 2006.257.22:35:08.93#ibcon#about to read 3, iclass 32, count 2 2006.257.22:35:08.96#ibcon#read 3, iclass 32, count 2 2006.257.22:35:08.96#ibcon#about to read 4, iclass 32, count 2 2006.257.22:35:08.96#ibcon#read 4, iclass 32, count 2 2006.257.22:35:08.96#ibcon#about to read 5, iclass 32, count 2 2006.257.22:35:08.96#ibcon#read 5, iclass 32, count 2 2006.257.22:35:08.96#ibcon#about to read 6, iclass 32, count 2 2006.257.22:35:08.96#ibcon#read 6, iclass 32, count 2 2006.257.22:35:08.96#ibcon#end of sib2, iclass 32, count 2 2006.257.22:35:08.96#ibcon#*after write, iclass 32, count 2 2006.257.22:35:08.96#ibcon#*before return 0, iclass 32, count 2 2006.257.22:35:08.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:08.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:08.96#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.22:35:08.96#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:08.96#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:09.08#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:09.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:09.08#ibcon#enter wrdev, iclass 32, count 0 2006.257.22:35:09.08#ibcon#first serial, iclass 32, count 0 2006.257.22:35:09.08#ibcon#enter sib2, iclass 32, count 0 2006.257.22:35:09.08#ibcon#flushed, iclass 32, count 0 2006.257.22:35:09.08#ibcon#about to write, iclass 32, count 0 2006.257.22:35:09.08#ibcon#wrote, iclass 32, count 0 2006.257.22:35:09.08#ibcon#about to read 3, iclass 32, count 0 2006.257.22:35:09.10#ibcon#read 3, iclass 32, count 0 2006.257.22:35:09.10#ibcon#about to read 4, iclass 32, count 0 2006.257.22:35:09.10#ibcon#read 4, iclass 32, count 0 2006.257.22:35:09.10#ibcon#about to read 5, iclass 32, count 0 2006.257.22:35:09.10#ibcon#read 5, iclass 32, count 0 2006.257.22:35:09.10#ibcon#about to read 6, iclass 32, count 0 2006.257.22:35:09.10#ibcon#read 6, iclass 32, count 0 2006.257.22:35:09.10#ibcon#end of sib2, iclass 32, count 0 2006.257.22:35:09.10#ibcon#*mode == 0, iclass 32, count 0 2006.257.22:35:09.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.22:35:09.10#ibcon#[25=USB\r\n] 2006.257.22:35:09.10#ibcon#*before write, iclass 32, count 0 2006.257.22:35:09.10#ibcon#enter sib2, iclass 32, count 0 2006.257.22:35:09.10#ibcon#flushed, iclass 32, count 0 2006.257.22:35:09.10#ibcon#about to write, iclass 32, count 0 2006.257.22:35:09.10#ibcon#wrote, iclass 32, count 0 2006.257.22:35:09.10#ibcon#about to read 3, iclass 32, count 0 2006.257.22:35:09.13#ibcon#read 3, iclass 32, count 0 2006.257.22:35:09.13#ibcon#about to read 4, iclass 32, count 0 2006.257.22:35:09.13#ibcon#read 4, iclass 32, count 0 2006.257.22:35:09.13#ibcon#about to read 5, iclass 32, count 0 2006.257.22:35:09.13#ibcon#read 5, iclass 32, count 0 2006.257.22:35:09.13#ibcon#about to read 6, iclass 32, count 0 2006.257.22:35:09.13#ibcon#read 6, iclass 32, count 0 2006.257.22:35:09.13#ibcon#end of sib2, iclass 32, count 0 2006.257.22:35:09.13#ibcon#*after write, iclass 32, count 0 2006.257.22:35:09.13#ibcon#*before return 0, iclass 32, count 0 2006.257.22:35:09.13#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:09.13#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:09.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.22:35:09.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.22:35:09.13$vck44/valo=3,564.99 2006.257.22:35:09.13#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.22:35:09.13#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.22:35:09.13#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:09.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:09.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:09.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:09.13#ibcon#enter wrdev, iclass 34, count 0 2006.257.22:35:09.13#ibcon#first serial, iclass 34, count 0 2006.257.22:35:09.13#ibcon#enter sib2, iclass 34, count 0 2006.257.22:35:09.13#ibcon#flushed, iclass 34, count 0 2006.257.22:35:09.13#ibcon#about to write, iclass 34, count 0 2006.257.22:35:09.13#ibcon#wrote, iclass 34, count 0 2006.257.22:35:09.13#ibcon#about to read 3, iclass 34, count 0 2006.257.22:35:09.15#ibcon#read 3, iclass 34, count 0 2006.257.22:35:09.15#ibcon#about to read 4, iclass 34, count 0 2006.257.22:35:09.15#ibcon#read 4, iclass 34, count 0 2006.257.22:35:09.15#ibcon#about to read 5, iclass 34, count 0 2006.257.22:35:09.15#ibcon#read 5, iclass 34, count 0 2006.257.22:35:09.15#ibcon#about to read 6, iclass 34, count 0 2006.257.22:35:09.15#ibcon#read 6, iclass 34, count 0 2006.257.22:35:09.15#ibcon#end of sib2, iclass 34, count 0 2006.257.22:35:09.15#ibcon#*mode == 0, iclass 34, count 0 2006.257.22:35:09.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.22:35:09.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.22:35:09.15#ibcon#*before write, iclass 34, count 0 2006.257.22:35:09.15#ibcon#enter sib2, iclass 34, count 0 2006.257.22:35:09.15#ibcon#flushed, iclass 34, count 0 2006.257.22:35:09.15#ibcon#about to write, iclass 34, count 0 2006.257.22:35:09.15#ibcon#wrote, iclass 34, count 0 2006.257.22:35:09.15#ibcon#about to read 3, iclass 34, count 0 2006.257.22:35:09.19#ibcon#read 3, iclass 34, count 0 2006.257.22:35:09.19#ibcon#about to read 4, iclass 34, count 0 2006.257.22:35:09.19#ibcon#read 4, iclass 34, count 0 2006.257.22:35:09.19#ibcon#about to read 5, iclass 34, count 0 2006.257.22:35:09.19#ibcon#read 5, iclass 34, count 0 2006.257.22:35:09.19#ibcon#about to read 6, iclass 34, count 0 2006.257.22:35:09.19#ibcon#read 6, iclass 34, count 0 2006.257.22:35:09.19#ibcon#end of sib2, iclass 34, count 0 2006.257.22:35:09.19#ibcon#*after write, iclass 34, count 0 2006.257.22:35:09.19#ibcon#*before return 0, iclass 34, count 0 2006.257.22:35:09.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:09.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:09.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.22:35:09.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.22:35:09.19$vck44/va=3,8 2006.257.22:35:09.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.22:35:09.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.22:35:09.19#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:09.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:09.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:09.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:09.25#ibcon#enter wrdev, iclass 36, count 2 2006.257.22:35:09.25#ibcon#first serial, iclass 36, count 2 2006.257.22:35:09.25#ibcon#enter sib2, iclass 36, count 2 2006.257.22:35:09.25#ibcon#flushed, iclass 36, count 2 2006.257.22:35:09.25#ibcon#about to write, iclass 36, count 2 2006.257.22:35:09.25#ibcon#wrote, iclass 36, count 2 2006.257.22:35:09.25#ibcon#about to read 3, iclass 36, count 2 2006.257.22:35:09.27#ibcon#read 3, iclass 36, count 2 2006.257.22:35:09.27#ibcon#about to read 4, iclass 36, count 2 2006.257.22:35:09.27#ibcon#read 4, iclass 36, count 2 2006.257.22:35:09.27#ibcon#about to read 5, iclass 36, count 2 2006.257.22:35:09.27#ibcon#read 5, iclass 36, count 2 2006.257.22:35:09.27#ibcon#about to read 6, iclass 36, count 2 2006.257.22:35:09.27#ibcon#read 6, iclass 36, count 2 2006.257.22:35:09.27#ibcon#end of sib2, iclass 36, count 2 2006.257.22:35:09.27#ibcon#*mode == 0, iclass 36, count 2 2006.257.22:35:09.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.22:35:09.27#ibcon#[25=AT03-08\r\n] 2006.257.22:35:09.27#ibcon#*before write, iclass 36, count 2 2006.257.22:35:09.27#ibcon#enter sib2, iclass 36, count 2 2006.257.22:35:09.27#ibcon#flushed, iclass 36, count 2 2006.257.22:35:09.27#ibcon#about to write, iclass 36, count 2 2006.257.22:35:09.27#ibcon#wrote, iclass 36, count 2 2006.257.22:35:09.27#ibcon#about to read 3, iclass 36, count 2 2006.257.22:35:09.30#ibcon#read 3, iclass 36, count 2 2006.257.22:35:09.30#ibcon#about to read 4, iclass 36, count 2 2006.257.22:35:09.30#ibcon#read 4, iclass 36, count 2 2006.257.22:35:09.30#ibcon#about to read 5, iclass 36, count 2 2006.257.22:35:09.30#ibcon#read 5, iclass 36, count 2 2006.257.22:35:09.30#ibcon#about to read 6, iclass 36, count 2 2006.257.22:35:09.30#ibcon#read 6, iclass 36, count 2 2006.257.22:35:09.30#ibcon#end of sib2, iclass 36, count 2 2006.257.22:35:09.30#ibcon#*after write, iclass 36, count 2 2006.257.22:35:09.30#ibcon#*before return 0, iclass 36, count 2 2006.257.22:35:09.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:09.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:09.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.22:35:09.30#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:09.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:09.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:09.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:09.42#ibcon#enter wrdev, iclass 36, count 0 2006.257.22:35:09.42#ibcon#first serial, iclass 36, count 0 2006.257.22:35:09.42#ibcon#enter sib2, iclass 36, count 0 2006.257.22:35:09.42#ibcon#flushed, iclass 36, count 0 2006.257.22:35:09.42#ibcon#about to write, iclass 36, count 0 2006.257.22:35:09.42#ibcon#wrote, iclass 36, count 0 2006.257.22:35:09.42#ibcon#about to read 3, iclass 36, count 0 2006.257.22:35:09.44#ibcon#read 3, iclass 36, count 0 2006.257.22:35:09.44#ibcon#about to read 4, iclass 36, count 0 2006.257.22:35:09.44#ibcon#read 4, iclass 36, count 0 2006.257.22:35:09.44#ibcon#about to read 5, iclass 36, count 0 2006.257.22:35:09.44#ibcon#read 5, iclass 36, count 0 2006.257.22:35:09.44#ibcon#about to read 6, iclass 36, count 0 2006.257.22:35:09.44#ibcon#read 6, iclass 36, count 0 2006.257.22:35:09.44#ibcon#end of sib2, iclass 36, count 0 2006.257.22:35:09.44#ibcon#*mode == 0, iclass 36, count 0 2006.257.22:35:09.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.22:35:09.44#ibcon#[25=USB\r\n] 2006.257.22:35:09.44#ibcon#*before write, iclass 36, count 0 2006.257.22:35:09.44#ibcon#enter sib2, iclass 36, count 0 2006.257.22:35:09.44#ibcon#flushed, iclass 36, count 0 2006.257.22:35:09.44#ibcon#about to write, iclass 36, count 0 2006.257.22:35:09.44#ibcon#wrote, iclass 36, count 0 2006.257.22:35:09.44#ibcon#about to read 3, iclass 36, count 0 2006.257.22:35:09.47#ibcon#read 3, iclass 36, count 0 2006.257.22:35:09.47#ibcon#about to read 4, iclass 36, count 0 2006.257.22:35:09.47#ibcon#read 4, iclass 36, count 0 2006.257.22:35:09.47#ibcon#about to read 5, iclass 36, count 0 2006.257.22:35:09.47#ibcon#read 5, iclass 36, count 0 2006.257.22:35:09.47#ibcon#about to read 6, iclass 36, count 0 2006.257.22:35:09.47#ibcon#read 6, iclass 36, count 0 2006.257.22:35:09.47#ibcon#end of sib2, iclass 36, count 0 2006.257.22:35:09.47#ibcon#*after write, iclass 36, count 0 2006.257.22:35:09.47#ibcon#*before return 0, iclass 36, count 0 2006.257.22:35:09.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:09.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:09.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.22:35:09.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.22:35:09.47$vck44/valo=4,624.99 2006.257.22:35:09.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.22:35:09.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.22:35:09.47#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:09.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:09.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:09.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:09.47#ibcon#enter wrdev, iclass 38, count 0 2006.257.22:35:09.47#ibcon#first serial, iclass 38, count 0 2006.257.22:35:09.47#ibcon#enter sib2, iclass 38, count 0 2006.257.22:35:09.47#ibcon#flushed, iclass 38, count 0 2006.257.22:35:09.47#ibcon#about to write, iclass 38, count 0 2006.257.22:35:09.47#ibcon#wrote, iclass 38, count 0 2006.257.22:35:09.47#ibcon#about to read 3, iclass 38, count 0 2006.257.22:35:09.49#ibcon#read 3, iclass 38, count 0 2006.257.22:35:09.49#ibcon#about to read 4, iclass 38, count 0 2006.257.22:35:09.49#ibcon#read 4, iclass 38, count 0 2006.257.22:35:09.49#ibcon#about to read 5, iclass 38, count 0 2006.257.22:35:09.49#ibcon#read 5, iclass 38, count 0 2006.257.22:35:09.49#ibcon#about to read 6, iclass 38, count 0 2006.257.22:35:09.49#ibcon#read 6, iclass 38, count 0 2006.257.22:35:09.49#ibcon#end of sib2, iclass 38, count 0 2006.257.22:35:09.49#ibcon#*mode == 0, iclass 38, count 0 2006.257.22:35:09.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.22:35:09.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.22:35:09.49#ibcon#*before write, iclass 38, count 0 2006.257.22:35:09.49#ibcon#enter sib2, iclass 38, count 0 2006.257.22:35:09.49#ibcon#flushed, iclass 38, count 0 2006.257.22:35:09.49#ibcon#about to write, iclass 38, count 0 2006.257.22:35:09.49#ibcon#wrote, iclass 38, count 0 2006.257.22:35:09.49#ibcon#about to read 3, iclass 38, count 0 2006.257.22:35:09.53#ibcon#read 3, iclass 38, count 0 2006.257.22:35:09.53#ibcon#about to read 4, iclass 38, count 0 2006.257.22:35:09.53#ibcon#read 4, iclass 38, count 0 2006.257.22:35:09.53#ibcon#about to read 5, iclass 38, count 0 2006.257.22:35:09.53#ibcon#read 5, iclass 38, count 0 2006.257.22:35:09.53#ibcon#about to read 6, iclass 38, count 0 2006.257.22:35:09.53#ibcon#read 6, iclass 38, count 0 2006.257.22:35:09.53#ibcon#end of sib2, iclass 38, count 0 2006.257.22:35:09.53#ibcon#*after write, iclass 38, count 0 2006.257.22:35:09.53#ibcon#*before return 0, iclass 38, count 0 2006.257.22:35:09.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:09.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:09.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.22:35:09.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.22:35:09.53$vck44/va=4,7 2006.257.22:35:09.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.22:35:09.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.22:35:09.53#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:09.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:09.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:09.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:09.59#ibcon#enter wrdev, iclass 40, count 2 2006.257.22:35:09.59#ibcon#first serial, iclass 40, count 2 2006.257.22:35:09.59#ibcon#enter sib2, iclass 40, count 2 2006.257.22:35:09.59#ibcon#flushed, iclass 40, count 2 2006.257.22:35:09.59#ibcon#about to write, iclass 40, count 2 2006.257.22:35:09.59#ibcon#wrote, iclass 40, count 2 2006.257.22:35:09.59#ibcon#about to read 3, iclass 40, count 2 2006.257.22:35:09.61#ibcon#read 3, iclass 40, count 2 2006.257.22:35:09.61#ibcon#about to read 4, iclass 40, count 2 2006.257.22:35:09.61#ibcon#read 4, iclass 40, count 2 2006.257.22:35:09.61#ibcon#about to read 5, iclass 40, count 2 2006.257.22:35:09.61#ibcon#read 5, iclass 40, count 2 2006.257.22:35:09.61#ibcon#about to read 6, iclass 40, count 2 2006.257.22:35:09.61#ibcon#read 6, iclass 40, count 2 2006.257.22:35:09.61#ibcon#end of sib2, iclass 40, count 2 2006.257.22:35:09.61#ibcon#*mode == 0, iclass 40, count 2 2006.257.22:35:09.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.22:35:09.61#ibcon#[25=AT04-07\r\n] 2006.257.22:35:09.61#ibcon#*before write, iclass 40, count 2 2006.257.22:35:09.61#ibcon#enter sib2, iclass 40, count 2 2006.257.22:35:09.61#ibcon#flushed, iclass 40, count 2 2006.257.22:35:09.61#ibcon#about to write, iclass 40, count 2 2006.257.22:35:09.61#ibcon#wrote, iclass 40, count 2 2006.257.22:35:09.61#ibcon#about to read 3, iclass 40, count 2 2006.257.22:35:09.64#ibcon#read 3, iclass 40, count 2 2006.257.22:35:09.64#ibcon#about to read 4, iclass 40, count 2 2006.257.22:35:09.64#ibcon#read 4, iclass 40, count 2 2006.257.22:35:09.64#ibcon#about to read 5, iclass 40, count 2 2006.257.22:35:09.64#ibcon#read 5, iclass 40, count 2 2006.257.22:35:09.64#ibcon#about to read 6, iclass 40, count 2 2006.257.22:35:09.64#ibcon#read 6, iclass 40, count 2 2006.257.22:35:09.64#ibcon#end of sib2, iclass 40, count 2 2006.257.22:35:09.64#ibcon#*after write, iclass 40, count 2 2006.257.22:35:09.64#ibcon#*before return 0, iclass 40, count 2 2006.257.22:35:09.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:09.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:09.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.22:35:09.64#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:09.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:09.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:09.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:09.76#ibcon#enter wrdev, iclass 40, count 0 2006.257.22:35:09.76#ibcon#first serial, iclass 40, count 0 2006.257.22:35:09.76#ibcon#enter sib2, iclass 40, count 0 2006.257.22:35:09.76#ibcon#flushed, iclass 40, count 0 2006.257.22:35:09.76#ibcon#about to write, iclass 40, count 0 2006.257.22:35:09.76#ibcon#wrote, iclass 40, count 0 2006.257.22:35:09.76#ibcon#about to read 3, iclass 40, count 0 2006.257.22:35:09.78#ibcon#read 3, iclass 40, count 0 2006.257.22:35:09.78#ibcon#about to read 4, iclass 40, count 0 2006.257.22:35:09.78#ibcon#read 4, iclass 40, count 0 2006.257.22:35:09.78#ibcon#about to read 5, iclass 40, count 0 2006.257.22:35:09.78#ibcon#read 5, iclass 40, count 0 2006.257.22:35:09.78#ibcon#about to read 6, iclass 40, count 0 2006.257.22:35:09.78#ibcon#read 6, iclass 40, count 0 2006.257.22:35:09.78#ibcon#end of sib2, iclass 40, count 0 2006.257.22:35:09.78#ibcon#*mode == 0, iclass 40, count 0 2006.257.22:35:09.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.22:35:09.78#ibcon#[25=USB\r\n] 2006.257.22:35:09.78#ibcon#*before write, iclass 40, count 0 2006.257.22:35:09.78#ibcon#enter sib2, iclass 40, count 0 2006.257.22:35:09.78#ibcon#flushed, iclass 40, count 0 2006.257.22:35:09.78#ibcon#about to write, iclass 40, count 0 2006.257.22:35:09.78#ibcon#wrote, iclass 40, count 0 2006.257.22:35:09.78#ibcon#about to read 3, iclass 40, count 0 2006.257.22:35:09.81#ibcon#read 3, iclass 40, count 0 2006.257.22:35:09.81#ibcon#about to read 4, iclass 40, count 0 2006.257.22:35:09.81#ibcon#read 4, iclass 40, count 0 2006.257.22:35:09.81#ibcon#about to read 5, iclass 40, count 0 2006.257.22:35:09.81#ibcon#read 5, iclass 40, count 0 2006.257.22:35:09.81#ibcon#about to read 6, iclass 40, count 0 2006.257.22:35:09.81#ibcon#read 6, iclass 40, count 0 2006.257.22:35:09.81#ibcon#end of sib2, iclass 40, count 0 2006.257.22:35:09.81#ibcon#*after write, iclass 40, count 0 2006.257.22:35:09.81#ibcon#*before return 0, iclass 40, count 0 2006.257.22:35:09.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:09.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:09.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.22:35:09.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.22:35:09.81$vck44/valo=5,734.99 2006.257.22:35:09.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.22:35:09.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.22:35:09.81#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:09.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:09.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:09.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:09.81#ibcon#enter wrdev, iclass 4, count 0 2006.257.22:35:09.81#ibcon#first serial, iclass 4, count 0 2006.257.22:35:09.81#ibcon#enter sib2, iclass 4, count 0 2006.257.22:35:09.81#ibcon#flushed, iclass 4, count 0 2006.257.22:35:09.81#ibcon#about to write, iclass 4, count 0 2006.257.22:35:09.81#ibcon#wrote, iclass 4, count 0 2006.257.22:35:09.81#ibcon#about to read 3, iclass 4, count 0 2006.257.22:35:09.83#ibcon#read 3, iclass 4, count 0 2006.257.22:35:09.83#ibcon#about to read 4, iclass 4, count 0 2006.257.22:35:09.83#ibcon#read 4, iclass 4, count 0 2006.257.22:35:09.83#ibcon#about to read 5, iclass 4, count 0 2006.257.22:35:09.83#ibcon#read 5, iclass 4, count 0 2006.257.22:35:09.83#ibcon#about to read 6, iclass 4, count 0 2006.257.22:35:09.83#ibcon#read 6, iclass 4, count 0 2006.257.22:35:09.83#ibcon#end of sib2, iclass 4, count 0 2006.257.22:35:09.83#ibcon#*mode == 0, iclass 4, count 0 2006.257.22:35:09.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.22:35:09.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.22:35:09.83#ibcon#*before write, iclass 4, count 0 2006.257.22:35:09.83#ibcon#enter sib2, iclass 4, count 0 2006.257.22:35:09.83#ibcon#flushed, iclass 4, count 0 2006.257.22:35:09.83#ibcon#about to write, iclass 4, count 0 2006.257.22:35:09.83#ibcon#wrote, iclass 4, count 0 2006.257.22:35:09.83#ibcon#about to read 3, iclass 4, count 0 2006.257.22:35:09.87#ibcon#read 3, iclass 4, count 0 2006.257.22:35:09.87#ibcon#about to read 4, iclass 4, count 0 2006.257.22:35:09.87#ibcon#read 4, iclass 4, count 0 2006.257.22:35:09.87#ibcon#about to read 5, iclass 4, count 0 2006.257.22:35:09.87#ibcon#read 5, iclass 4, count 0 2006.257.22:35:09.87#ibcon#about to read 6, iclass 4, count 0 2006.257.22:35:09.87#ibcon#read 6, iclass 4, count 0 2006.257.22:35:09.87#ibcon#end of sib2, iclass 4, count 0 2006.257.22:35:09.87#ibcon#*after write, iclass 4, count 0 2006.257.22:35:09.87#ibcon#*before return 0, iclass 4, count 0 2006.257.22:35:09.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:09.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:09.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.22:35:09.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.22:35:09.87$vck44/va=5,4 2006.257.22:35:09.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.22:35:09.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.22:35:09.87#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:09.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:09.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:09.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:09.93#ibcon#enter wrdev, iclass 6, count 2 2006.257.22:35:09.93#ibcon#first serial, iclass 6, count 2 2006.257.22:35:09.93#ibcon#enter sib2, iclass 6, count 2 2006.257.22:35:09.93#ibcon#flushed, iclass 6, count 2 2006.257.22:35:09.93#ibcon#about to write, iclass 6, count 2 2006.257.22:35:09.93#ibcon#wrote, iclass 6, count 2 2006.257.22:35:09.93#ibcon#about to read 3, iclass 6, count 2 2006.257.22:35:09.95#ibcon#read 3, iclass 6, count 2 2006.257.22:35:09.95#ibcon#about to read 4, iclass 6, count 2 2006.257.22:35:09.95#ibcon#read 4, iclass 6, count 2 2006.257.22:35:09.95#ibcon#about to read 5, iclass 6, count 2 2006.257.22:35:09.95#ibcon#read 5, iclass 6, count 2 2006.257.22:35:09.95#ibcon#about to read 6, iclass 6, count 2 2006.257.22:35:09.95#ibcon#read 6, iclass 6, count 2 2006.257.22:35:09.95#ibcon#end of sib2, iclass 6, count 2 2006.257.22:35:09.95#ibcon#*mode == 0, iclass 6, count 2 2006.257.22:35:09.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.22:35:09.95#ibcon#[25=AT05-04\r\n] 2006.257.22:35:09.95#ibcon#*before write, iclass 6, count 2 2006.257.22:35:09.95#ibcon#enter sib2, iclass 6, count 2 2006.257.22:35:09.95#ibcon#flushed, iclass 6, count 2 2006.257.22:35:09.95#ibcon#about to write, iclass 6, count 2 2006.257.22:35:09.95#ibcon#wrote, iclass 6, count 2 2006.257.22:35:09.95#ibcon#about to read 3, iclass 6, count 2 2006.257.22:35:09.95#abcon#<5=/13 0.9 2.6 19.44 871016.0\r\n> 2006.257.22:35:09.97#abcon#{5=INTERFACE CLEAR} 2006.257.22:35:09.98#ibcon#read 3, iclass 6, count 2 2006.257.22:35:09.98#ibcon#about to read 4, iclass 6, count 2 2006.257.22:35:09.98#ibcon#read 4, iclass 6, count 2 2006.257.22:35:09.98#ibcon#about to read 5, iclass 6, count 2 2006.257.22:35:09.98#ibcon#read 5, iclass 6, count 2 2006.257.22:35:09.98#ibcon#about to read 6, iclass 6, count 2 2006.257.22:35:09.98#ibcon#read 6, iclass 6, count 2 2006.257.22:35:09.98#ibcon#end of sib2, iclass 6, count 2 2006.257.22:35:09.98#ibcon#*after write, iclass 6, count 2 2006.257.22:35:09.98#ibcon#*before return 0, iclass 6, count 2 2006.257.22:35:09.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:09.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:09.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.22:35:09.98#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:09.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:10.03#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:35:10.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:10.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:10.10#ibcon#enter wrdev, iclass 6, count 0 2006.257.22:35:10.10#ibcon#first serial, iclass 6, count 0 2006.257.22:35:10.10#ibcon#enter sib2, iclass 6, count 0 2006.257.22:35:10.10#ibcon#flushed, iclass 6, count 0 2006.257.22:35:10.10#ibcon#about to write, iclass 6, count 0 2006.257.22:35:10.10#ibcon#wrote, iclass 6, count 0 2006.257.22:35:10.10#ibcon#about to read 3, iclass 6, count 0 2006.257.22:35:10.12#ibcon#read 3, iclass 6, count 0 2006.257.22:35:10.12#ibcon#about to read 4, iclass 6, count 0 2006.257.22:35:10.12#ibcon#read 4, iclass 6, count 0 2006.257.22:35:10.12#ibcon#about to read 5, iclass 6, count 0 2006.257.22:35:10.12#ibcon#read 5, iclass 6, count 0 2006.257.22:35:10.12#ibcon#about to read 6, iclass 6, count 0 2006.257.22:35:10.12#ibcon#read 6, iclass 6, count 0 2006.257.22:35:10.12#ibcon#end of sib2, iclass 6, count 0 2006.257.22:35:10.12#ibcon#*mode == 0, iclass 6, count 0 2006.257.22:35:10.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.22:35:10.12#ibcon#[25=USB\r\n] 2006.257.22:35:10.12#ibcon#*before write, iclass 6, count 0 2006.257.22:35:10.12#ibcon#enter sib2, iclass 6, count 0 2006.257.22:35:10.12#ibcon#flushed, iclass 6, count 0 2006.257.22:35:10.12#ibcon#about to write, iclass 6, count 0 2006.257.22:35:10.12#ibcon#wrote, iclass 6, count 0 2006.257.22:35:10.12#ibcon#about to read 3, iclass 6, count 0 2006.257.22:35:10.15#ibcon#read 3, iclass 6, count 0 2006.257.22:35:10.15#ibcon#about to read 4, iclass 6, count 0 2006.257.22:35:10.15#ibcon#read 4, iclass 6, count 0 2006.257.22:35:10.15#ibcon#about to read 5, iclass 6, count 0 2006.257.22:35:10.15#ibcon#read 5, iclass 6, count 0 2006.257.22:35:10.15#ibcon#about to read 6, iclass 6, count 0 2006.257.22:35:10.15#ibcon#read 6, iclass 6, count 0 2006.257.22:35:10.15#ibcon#end of sib2, iclass 6, count 0 2006.257.22:35:10.15#ibcon#*after write, iclass 6, count 0 2006.257.22:35:10.15#ibcon#*before return 0, iclass 6, count 0 2006.257.22:35:10.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:10.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:10.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.22:35:10.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.22:35:10.15$vck44/valo=6,814.99 2006.257.22:35:10.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.22:35:10.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.22:35:10.15#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:10.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:10.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:10.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:10.15#ibcon#enter wrdev, iclass 14, count 0 2006.257.22:35:10.15#ibcon#first serial, iclass 14, count 0 2006.257.22:35:10.15#ibcon#enter sib2, iclass 14, count 0 2006.257.22:35:10.15#ibcon#flushed, iclass 14, count 0 2006.257.22:35:10.15#ibcon#about to write, iclass 14, count 0 2006.257.22:35:10.15#ibcon#wrote, iclass 14, count 0 2006.257.22:35:10.15#ibcon#about to read 3, iclass 14, count 0 2006.257.22:35:10.17#ibcon#read 3, iclass 14, count 0 2006.257.22:35:10.17#ibcon#about to read 4, iclass 14, count 0 2006.257.22:35:10.17#ibcon#read 4, iclass 14, count 0 2006.257.22:35:10.17#ibcon#about to read 5, iclass 14, count 0 2006.257.22:35:10.17#ibcon#read 5, iclass 14, count 0 2006.257.22:35:10.17#ibcon#about to read 6, iclass 14, count 0 2006.257.22:35:10.17#ibcon#read 6, iclass 14, count 0 2006.257.22:35:10.17#ibcon#end of sib2, iclass 14, count 0 2006.257.22:35:10.17#ibcon#*mode == 0, iclass 14, count 0 2006.257.22:35:10.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.22:35:10.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.22:35:10.17#ibcon#*before write, iclass 14, count 0 2006.257.22:35:10.17#ibcon#enter sib2, iclass 14, count 0 2006.257.22:35:10.17#ibcon#flushed, iclass 14, count 0 2006.257.22:35:10.17#ibcon#about to write, iclass 14, count 0 2006.257.22:35:10.17#ibcon#wrote, iclass 14, count 0 2006.257.22:35:10.17#ibcon#about to read 3, iclass 14, count 0 2006.257.22:35:10.21#ibcon#read 3, iclass 14, count 0 2006.257.22:35:10.21#ibcon#about to read 4, iclass 14, count 0 2006.257.22:35:10.21#ibcon#read 4, iclass 14, count 0 2006.257.22:35:10.21#ibcon#about to read 5, iclass 14, count 0 2006.257.22:35:10.21#ibcon#read 5, iclass 14, count 0 2006.257.22:35:10.21#ibcon#about to read 6, iclass 14, count 0 2006.257.22:35:10.21#ibcon#read 6, iclass 14, count 0 2006.257.22:35:10.21#ibcon#end of sib2, iclass 14, count 0 2006.257.22:35:10.21#ibcon#*after write, iclass 14, count 0 2006.257.22:35:10.21#ibcon#*before return 0, iclass 14, count 0 2006.257.22:35:10.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:10.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:10.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.22:35:10.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.22:35:10.21$vck44/va=6,4 2006.257.22:35:10.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.22:35:10.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.22:35:10.21#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:10.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:10.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:10.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:10.27#ibcon#enter wrdev, iclass 16, count 2 2006.257.22:35:10.27#ibcon#first serial, iclass 16, count 2 2006.257.22:35:10.27#ibcon#enter sib2, iclass 16, count 2 2006.257.22:35:10.27#ibcon#flushed, iclass 16, count 2 2006.257.22:35:10.27#ibcon#about to write, iclass 16, count 2 2006.257.22:35:10.27#ibcon#wrote, iclass 16, count 2 2006.257.22:35:10.27#ibcon#about to read 3, iclass 16, count 2 2006.257.22:35:10.29#ibcon#read 3, iclass 16, count 2 2006.257.22:35:10.29#ibcon#about to read 4, iclass 16, count 2 2006.257.22:35:10.29#ibcon#read 4, iclass 16, count 2 2006.257.22:35:10.29#ibcon#about to read 5, iclass 16, count 2 2006.257.22:35:10.29#ibcon#read 5, iclass 16, count 2 2006.257.22:35:10.29#ibcon#about to read 6, iclass 16, count 2 2006.257.22:35:10.29#ibcon#read 6, iclass 16, count 2 2006.257.22:35:10.29#ibcon#end of sib2, iclass 16, count 2 2006.257.22:35:10.29#ibcon#*mode == 0, iclass 16, count 2 2006.257.22:35:10.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.22:35:10.29#ibcon#[25=AT06-04\r\n] 2006.257.22:35:10.29#ibcon#*before write, iclass 16, count 2 2006.257.22:35:10.29#ibcon#enter sib2, iclass 16, count 2 2006.257.22:35:10.29#ibcon#flushed, iclass 16, count 2 2006.257.22:35:10.29#ibcon#about to write, iclass 16, count 2 2006.257.22:35:10.29#ibcon#wrote, iclass 16, count 2 2006.257.22:35:10.29#ibcon#about to read 3, iclass 16, count 2 2006.257.22:35:10.32#ibcon#read 3, iclass 16, count 2 2006.257.22:35:10.32#ibcon#about to read 4, iclass 16, count 2 2006.257.22:35:10.32#ibcon#read 4, iclass 16, count 2 2006.257.22:35:10.32#ibcon#about to read 5, iclass 16, count 2 2006.257.22:35:10.32#ibcon#read 5, iclass 16, count 2 2006.257.22:35:10.32#ibcon#about to read 6, iclass 16, count 2 2006.257.22:35:10.32#ibcon#read 6, iclass 16, count 2 2006.257.22:35:10.32#ibcon#end of sib2, iclass 16, count 2 2006.257.22:35:10.32#ibcon#*after write, iclass 16, count 2 2006.257.22:35:10.32#ibcon#*before return 0, iclass 16, count 2 2006.257.22:35:10.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:10.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:10.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.22:35:10.32#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:10.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:10.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:10.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:10.44#ibcon#enter wrdev, iclass 16, count 0 2006.257.22:35:10.44#ibcon#first serial, iclass 16, count 0 2006.257.22:35:10.44#ibcon#enter sib2, iclass 16, count 0 2006.257.22:35:10.44#ibcon#flushed, iclass 16, count 0 2006.257.22:35:10.44#ibcon#about to write, iclass 16, count 0 2006.257.22:35:10.44#ibcon#wrote, iclass 16, count 0 2006.257.22:35:10.44#ibcon#about to read 3, iclass 16, count 0 2006.257.22:35:10.46#ibcon#read 3, iclass 16, count 0 2006.257.22:35:10.46#ibcon#about to read 4, iclass 16, count 0 2006.257.22:35:10.46#ibcon#read 4, iclass 16, count 0 2006.257.22:35:10.46#ibcon#about to read 5, iclass 16, count 0 2006.257.22:35:10.46#ibcon#read 5, iclass 16, count 0 2006.257.22:35:10.46#ibcon#about to read 6, iclass 16, count 0 2006.257.22:35:10.46#ibcon#read 6, iclass 16, count 0 2006.257.22:35:10.46#ibcon#end of sib2, iclass 16, count 0 2006.257.22:35:10.46#ibcon#*mode == 0, iclass 16, count 0 2006.257.22:35:10.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.22:35:10.46#ibcon#[25=USB\r\n] 2006.257.22:35:10.46#ibcon#*before write, iclass 16, count 0 2006.257.22:35:10.46#ibcon#enter sib2, iclass 16, count 0 2006.257.22:35:10.46#ibcon#flushed, iclass 16, count 0 2006.257.22:35:10.46#ibcon#about to write, iclass 16, count 0 2006.257.22:35:10.46#ibcon#wrote, iclass 16, count 0 2006.257.22:35:10.46#ibcon#about to read 3, iclass 16, count 0 2006.257.22:35:10.49#ibcon#read 3, iclass 16, count 0 2006.257.22:35:10.49#ibcon#about to read 4, iclass 16, count 0 2006.257.22:35:10.49#ibcon#read 4, iclass 16, count 0 2006.257.22:35:10.49#ibcon#about to read 5, iclass 16, count 0 2006.257.22:35:10.49#ibcon#read 5, iclass 16, count 0 2006.257.22:35:10.49#ibcon#about to read 6, iclass 16, count 0 2006.257.22:35:10.49#ibcon#read 6, iclass 16, count 0 2006.257.22:35:10.49#ibcon#end of sib2, iclass 16, count 0 2006.257.22:35:10.49#ibcon#*after write, iclass 16, count 0 2006.257.22:35:10.49#ibcon#*before return 0, iclass 16, count 0 2006.257.22:35:10.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:10.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:10.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.22:35:10.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.22:35:10.49$vck44/valo=7,864.99 2006.257.22:35:10.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.22:35:10.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.22:35:10.49#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:10.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:10.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:10.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:10.49#ibcon#enter wrdev, iclass 18, count 0 2006.257.22:35:10.49#ibcon#first serial, iclass 18, count 0 2006.257.22:35:10.49#ibcon#enter sib2, iclass 18, count 0 2006.257.22:35:10.49#ibcon#flushed, iclass 18, count 0 2006.257.22:35:10.49#ibcon#about to write, iclass 18, count 0 2006.257.22:35:10.49#ibcon#wrote, iclass 18, count 0 2006.257.22:35:10.49#ibcon#about to read 3, iclass 18, count 0 2006.257.22:35:10.51#ibcon#read 3, iclass 18, count 0 2006.257.22:35:10.51#ibcon#about to read 4, iclass 18, count 0 2006.257.22:35:10.51#ibcon#read 4, iclass 18, count 0 2006.257.22:35:10.51#ibcon#about to read 5, iclass 18, count 0 2006.257.22:35:10.51#ibcon#read 5, iclass 18, count 0 2006.257.22:35:10.51#ibcon#about to read 6, iclass 18, count 0 2006.257.22:35:10.51#ibcon#read 6, iclass 18, count 0 2006.257.22:35:10.51#ibcon#end of sib2, iclass 18, count 0 2006.257.22:35:10.51#ibcon#*mode == 0, iclass 18, count 0 2006.257.22:35:10.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.22:35:10.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.22:35:10.51#ibcon#*before write, iclass 18, count 0 2006.257.22:35:10.51#ibcon#enter sib2, iclass 18, count 0 2006.257.22:35:10.51#ibcon#flushed, iclass 18, count 0 2006.257.22:35:10.51#ibcon#about to write, iclass 18, count 0 2006.257.22:35:10.51#ibcon#wrote, iclass 18, count 0 2006.257.22:35:10.51#ibcon#about to read 3, iclass 18, count 0 2006.257.22:35:10.55#ibcon#read 3, iclass 18, count 0 2006.257.22:35:10.55#ibcon#about to read 4, iclass 18, count 0 2006.257.22:35:10.55#ibcon#read 4, iclass 18, count 0 2006.257.22:35:10.55#ibcon#about to read 5, iclass 18, count 0 2006.257.22:35:10.55#ibcon#read 5, iclass 18, count 0 2006.257.22:35:10.55#ibcon#about to read 6, iclass 18, count 0 2006.257.22:35:10.55#ibcon#read 6, iclass 18, count 0 2006.257.22:35:10.55#ibcon#end of sib2, iclass 18, count 0 2006.257.22:35:10.55#ibcon#*after write, iclass 18, count 0 2006.257.22:35:10.55#ibcon#*before return 0, iclass 18, count 0 2006.257.22:35:10.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:10.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:10.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.22:35:10.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.22:35:10.55$vck44/va=7,4 2006.257.22:35:10.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.22:35:10.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.22:35:10.55#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:10.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:10.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:10.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:10.61#ibcon#enter wrdev, iclass 20, count 2 2006.257.22:35:10.61#ibcon#first serial, iclass 20, count 2 2006.257.22:35:10.61#ibcon#enter sib2, iclass 20, count 2 2006.257.22:35:10.61#ibcon#flushed, iclass 20, count 2 2006.257.22:35:10.61#ibcon#about to write, iclass 20, count 2 2006.257.22:35:10.61#ibcon#wrote, iclass 20, count 2 2006.257.22:35:10.61#ibcon#about to read 3, iclass 20, count 2 2006.257.22:35:10.63#ibcon#read 3, iclass 20, count 2 2006.257.22:35:10.63#ibcon#about to read 4, iclass 20, count 2 2006.257.22:35:10.63#ibcon#read 4, iclass 20, count 2 2006.257.22:35:10.63#ibcon#about to read 5, iclass 20, count 2 2006.257.22:35:10.63#ibcon#read 5, iclass 20, count 2 2006.257.22:35:10.63#ibcon#about to read 6, iclass 20, count 2 2006.257.22:35:10.63#ibcon#read 6, iclass 20, count 2 2006.257.22:35:10.63#ibcon#end of sib2, iclass 20, count 2 2006.257.22:35:10.63#ibcon#*mode == 0, iclass 20, count 2 2006.257.22:35:10.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.22:35:10.63#ibcon#[25=AT07-04\r\n] 2006.257.22:35:10.63#ibcon#*before write, iclass 20, count 2 2006.257.22:35:10.63#ibcon#enter sib2, iclass 20, count 2 2006.257.22:35:10.63#ibcon#flushed, iclass 20, count 2 2006.257.22:35:10.63#ibcon#about to write, iclass 20, count 2 2006.257.22:35:10.63#ibcon#wrote, iclass 20, count 2 2006.257.22:35:10.63#ibcon#about to read 3, iclass 20, count 2 2006.257.22:35:10.66#ibcon#read 3, iclass 20, count 2 2006.257.22:35:10.66#ibcon#about to read 4, iclass 20, count 2 2006.257.22:35:10.66#ibcon#read 4, iclass 20, count 2 2006.257.22:35:10.66#ibcon#about to read 5, iclass 20, count 2 2006.257.22:35:10.66#ibcon#read 5, iclass 20, count 2 2006.257.22:35:10.66#ibcon#about to read 6, iclass 20, count 2 2006.257.22:35:10.66#ibcon#read 6, iclass 20, count 2 2006.257.22:35:10.66#ibcon#end of sib2, iclass 20, count 2 2006.257.22:35:10.66#ibcon#*after write, iclass 20, count 2 2006.257.22:35:10.66#ibcon#*before return 0, iclass 20, count 2 2006.257.22:35:10.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:10.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:10.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.22:35:10.66#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:10.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:10.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:10.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:10.78#ibcon#enter wrdev, iclass 20, count 0 2006.257.22:35:10.78#ibcon#first serial, iclass 20, count 0 2006.257.22:35:10.78#ibcon#enter sib2, iclass 20, count 0 2006.257.22:35:10.78#ibcon#flushed, iclass 20, count 0 2006.257.22:35:10.78#ibcon#about to write, iclass 20, count 0 2006.257.22:35:10.78#ibcon#wrote, iclass 20, count 0 2006.257.22:35:10.78#ibcon#about to read 3, iclass 20, count 0 2006.257.22:35:10.80#ibcon#read 3, iclass 20, count 0 2006.257.22:35:10.80#ibcon#about to read 4, iclass 20, count 0 2006.257.22:35:10.80#ibcon#read 4, iclass 20, count 0 2006.257.22:35:10.80#ibcon#about to read 5, iclass 20, count 0 2006.257.22:35:10.80#ibcon#read 5, iclass 20, count 0 2006.257.22:35:10.80#ibcon#about to read 6, iclass 20, count 0 2006.257.22:35:10.80#ibcon#read 6, iclass 20, count 0 2006.257.22:35:10.80#ibcon#end of sib2, iclass 20, count 0 2006.257.22:35:10.80#ibcon#*mode == 0, iclass 20, count 0 2006.257.22:35:10.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.22:35:10.80#ibcon#[25=USB\r\n] 2006.257.22:35:10.80#ibcon#*before write, iclass 20, count 0 2006.257.22:35:10.80#ibcon#enter sib2, iclass 20, count 0 2006.257.22:35:10.80#ibcon#flushed, iclass 20, count 0 2006.257.22:35:10.80#ibcon#about to write, iclass 20, count 0 2006.257.22:35:10.80#ibcon#wrote, iclass 20, count 0 2006.257.22:35:10.80#ibcon#about to read 3, iclass 20, count 0 2006.257.22:35:10.83#ibcon#read 3, iclass 20, count 0 2006.257.22:35:10.83#ibcon#about to read 4, iclass 20, count 0 2006.257.22:35:10.83#ibcon#read 4, iclass 20, count 0 2006.257.22:35:10.83#ibcon#about to read 5, iclass 20, count 0 2006.257.22:35:10.83#ibcon#read 5, iclass 20, count 0 2006.257.22:35:10.83#ibcon#about to read 6, iclass 20, count 0 2006.257.22:35:10.83#ibcon#read 6, iclass 20, count 0 2006.257.22:35:10.83#ibcon#end of sib2, iclass 20, count 0 2006.257.22:35:10.83#ibcon#*after write, iclass 20, count 0 2006.257.22:35:10.83#ibcon#*before return 0, iclass 20, count 0 2006.257.22:35:10.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:10.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:10.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.22:35:10.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.22:35:10.83$vck44/valo=8,884.99 2006.257.22:35:10.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.22:35:10.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.22:35:10.83#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:10.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:10.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:10.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:10.83#ibcon#enter wrdev, iclass 22, count 0 2006.257.22:35:10.83#ibcon#first serial, iclass 22, count 0 2006.257.22:35:10.83#ibcon#enter sib2, iclass 22, count 0 2006.257.22:35:10.83#ibcon#flushed, iclass 22, count 0 2006.257.22:35:10.83#ibcon#about to write, iclass 22, count 0 2006.257.22:35:10.83#ibcon#wrote, iclass 22, count 0 2006.257.22:35:10.83#ibcon#about to read 3, iclass 22, count 0 2006.257.22:35:10.85#ibcon#read 3, iclass 22, count 0 2006.257.22:35:10.85#ibcon#about to read 4, iclass 22, count 0 2006.257.22:35:10.85#ibcon#read 4, iclass 22, count 0 2006.257.22:35:10.85#ibcon#about to read 5, iclass 22, count 0 2006.257.22:35:10.85#ibcon#read 5, iclass 22, count 0 2006.257.22:35:10.85#ibcon#about to read 6, iclass 22, count 0 2006.257.22:35:10.85#ibcon#read 6, iclass 22, count 0 2006.257.22:35:10.85#ibcon#end of sib2, iclass 22, count 0 2006.257.22:35:10.85#ibcon#*mode == 0, iclass 22, count 0 2006.257.22:35:10.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.22:35:10.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.22:35:10.85#ibcon#*before write, iclass 22, count 0 2006.257.22:35:10.85#ibcon#enter sib2, iclass 22, count 0 2006.257.22:35:10.85#ibcon#flushed, iclass 22, count 0 2006.257.22:35:10.85#ibcon#about to write, iclass 22, count 0 2006.257.22:35:10.85#ibcon#wrote, iclass 22, count 0 2006.257.22:35:10.85#ibcon#about to read 3, iclass 22, count 0 2006.257.22:35:10.89#ibcon#read 3, iclass 22, count 0 2006.257.22:35:10.89#ibcon#about to read 4, iclass 22, count 0 2006.257.22:35:10.89#ibcon#read 4, iclass 22, count 0 2006.257.22:35:10.89#ibcon#about to read 5, iclass 22, count 0 2006.257.22:35:10.89#ibcon#read 5, iclass 22, count 0 2006.257.22:35:10.89#ibcon#about to read 6, iclass 22, count 0 2006.257.22:35:10.89#ibcon#read 6, iclass 22, count 0 2006.257.22:35:10.89#ibcon#end of sib2, iclass 22, count 0 2006.257.22:35:10.89#ibcon#*after write, iclass 22, count 0 2006.257.22:35:10.89#ibcon#*before return 0, iclass 22, count 0 2006.257.22:35:10.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:10.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:10.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.22:35:10.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.22:35:10.89$vck44/va=8,4 2006.257.22:35:10.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.22:35:10.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.22:35:10.89#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:10.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.22:35:10.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.22:35:10.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.22:35:10.95#ibcon#enter wrdev, iclass 24, count 2 2006.257.22:35:10.95#ibcon#first serial, iclass 24, count 2 2006.257.22:35:10.95#ibcon#enter sib2, iclass 24, count 2 2006.257.22:35:10.95#ibcon#flushed, iclass 24, count 2 2006.257.22:35:10.95#ibcon#about to write, iclass 24, count 2 2006.257.22:35:10.95#ibcon#wrote, iclass 24, count 2 2006.257.22:35:10.95#ibcon#about to read 3, iclass 24, count 2 2006.257.22:35:10.97#ibcon#read 3, iclass 24, count 2 2006.257.22:35:10.97#ibcon#about to read 4, iclass 24, count 2 2006.257.22:35:10.97#ibcon#read 4, iclass 24, count 2 2006.257.22:35:10.97#ibcon#about to read 5, iclass 24, count 2 2006.257.22:35:10.97#ibcon#read 5, iclass 24, count 2 2006.257.22:35:10.97#ibcon#about to read 6, iclass 24, count 2 2006.257.22:35:10.97#ibcon#read 6, iclass 24, count 2 2006.257.22:35:10.97#ibcon#end of sib2, iclass 24, count 2 2006.257.22:35:10.97#ibcon#*mode == 0, iclass 24, count 2 2006.257.22:35:10.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.22:35:10.97#ibcon#[25=AT08-04\r\n] 2006.257.22:35:10.97#ibcon#*before write, iclass 24, count 2 2006.257.22:35:10.97#ibcon#enter sib2, iclass 24, count 2 2006.257.22:35:10.97#ibcon#flushed, iclass 24, count 2 2006.257.22:35:10.97#ibcon#about to write, iclass 24, count 2 2006.257.22:35:10.97#ibcon#wrote, iclass 24, count 2 2006.257.22:35:10.97#ibcon#about to read 3, iclass 24, count 2 2006.257.22:35:11.00#ibcon#read 3, iclass 24, count 2 2006.257.22:35:11.00#ibcon#about to read 4, iclass 24, count 2 2006.257.22:35:11.00#ibcon#read 4, iclass 24, count 2 2006.257.22:35:11.00#ibcon#about to read 5, iclass 24, count 2 2006.257.22:35:11.00#ibcon#read 5, iclass 24, count 2 2006.257.22:35:11.00#ibcon#about to read 6, iclass 24, count 2 2006.257.22:35:11.00#ibcon#read 6, iclass 24, count 2 2006.257.22:35:11.00#ibcon#end of sib2, iclass 24, count 2 2006.257.22:35:11.00#ibcon#*after write, iclass 24, count 2 2006.257.22:35:11.00#ibcon#*before return 0, iclass 24, count 2 2006.257.22:35:11.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.22:35:11.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.22:35:11.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.22:35:11.00#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:11.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.22:35:11.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.22:35:11.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.22:35:11.12#ibcon#enter wrdev, iclass 24, count 0 2006.257.22:35:11.12#ibcon#first serial, iclass 24, count 0 2006.257.22:35:11.12#ibcon#enter sib2, iclass 24, count 0 2006.257.22:35:11.12#ibcon#flushed, iclass 24, count 0 2006.257.22:35:11.12#ibcon#about to write, iclass 24, count 0 2006.257.22:35:11.12#ibcon#wrote, iclass 24, count 0 2006.257.22:35:11.12#ibcon#about to read 3, iclass 24, count 0 2006.257.22:35:11.14#ibcon#read 3, iclass 24, count 0 2006.257.22:35:11.14#ibcon#about to read 4, iclass 24, count 0 2006.257.22:35:11.14#ibcon#read 4, iclass 24, count 0 2006.257.22:35:11.14#ibcon#about to read 5, iclass 24, count 0 2006.257.22:35:11.14#ibcon#read 5, iclass 24, count 0 2006.257.22:35:11.14#ibcon#about to read 6, iclass 24, count 0 2006.257.22:35:11.14#ibcon#read 6, iclass 24, count 0 2006.257.22:35:11.14#ibcon#end of sib2, iclass 24, count 0 2006.257.22:35:11.14#ibcon#*mode == 0, iclass 24, count 0 2006.257.22:35:11.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.22:35:11.14#ibcon#[25=USB\r\n] 2006.257.22:35:11.14#ibcon#*before write, iclass 24, count 0 2006.257.22:35:11.14#ibcon#enter sib2, iclass 24, count 0 2006.257.22:35:11.14#ibcon#flushed, iclass 24, count 0 2006.257.22:35:11.14#ibcon#about to write, iclass 24, count 0 2006.257.22:35:11.14#ibcon#wrote, iclass 24, count 0 2006.257.22:35:11.14#ibcon#about to read 3, iclass 24, count 0 2006.257.22:35:11.17#ibcon#read 3, iclass 24, count 0 2006.257.22:35:11.17#ibcon#about to read 4, iclass 24, count 0 2006.257.22:35:11.17#ibcon#read 4, iclass 24, count 0 2006.257.22:35:11.17#ibcon#about to read 5, iclass 24, count 0 2006.257.22:35:11.17#ibcon#read 5, iclass 24, count 0 2006.257.22:35:11.17#ibcon#about to read 6, iclass 24, count 0 2006.257.22:35:11.17#ibcon#read 6, iclass 24, count 0 2006.257.22:35:11.17#ibcon#end of sib2, iclass 24, count 0 2006.257.22:35:11.17#ibcon#*after write, iclass 24, count 0 2006.257.22:35:11.17#ibcon#*before return 0, iclass 24, count 0 2006.257.22:35:11.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.22:35:11.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.22:35:11.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.22:35:11.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.22:35:11.17$vck44/vblo=1,629.99 2006.257.22:35:11.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.22:35:11.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.22:35:11.17#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:11.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:11.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:11.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:11.17#ibcon#enter wrdev, iclass 26, count 0 2006.257.22:35:11.17#ibcon#first serial, iclass 26, count 0 2006.257.22:35:11.17#ibcon#enter sib2, iclass 26, count 0 2006.257.22:35:11.17#ibcon#flushed, iclass 26, count 0 2006.257.22:35:11.17#ibcon#about to write, iclass 26, count 0 2006.257.22:35:11.17#ibcon#wrote, iclass 26, count 0 2006.257.22:35:11.17#ibcon#about to read 3, iclass 26, count 0 2006.257.22:35:11.19#ibcon#read 3, iclass 26, count 0 2006.257.22:35:11.19#ibcon#about to read 4, iclass 26, count 0 2006.257.22:35:11.19#ibcon#read 4, iclass 26, count 0 2006.257.22:35:11.19#ibcon#about to read 5, iclass 26, count 0 2006.257.22:35:11.19#ibcon#read 5, iclass 26, count 0 2006.257.22:35:11.19#ibcon#about to read 6, iclass 26, count 0 2006.257.22:35:11.19#ibcon#read 6, iclass 26, count 0 2006.257.22:35:11.19#ibcon#end of sib2, iclass 26, count 0 2006.257.22:35:11.19#ibcon#*mode == 0, iclass 26, count 0 2006.257.22:35:11.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.22:35:11.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.22:35:11.19#ibcon#*before write, iclass 26, count 0 2006.257.22:35:11.19#ibcon#enter sib2, iclass 26, count 0 2006.257.22:35:11.19#ibcon#flushed, iclass 26, count 0 2006.257.22:35:11.19#ibcon#about to write, iclass 26, count 0 2006.257.22:35:11.19#ibcon#wrote, iclass 26, count 0 2006.257.22:35:11.19#ibcon#about to read 3, iclass 26, count 0 2006.257.22:35:11.23#ibcon#read 3, iclass 26, count 0 2006.257.22:35:11.23#ibcon#about to read 4, iclass 26, count 0 2006.257.22:35:11.23#ibcon#read 4, iclass 26, count 0 2006.257.22:35:11.23#ibcon#about to read 5, iclass 26, count 0 2006.257.22:35:11.23#ibcon#read 5, iclass 26, count 0 2006.257.22:35:11.23#ibcon#about to read 6, iclass 26, count 0 2006.257.22:35:11.23#ibcon#read 6, iclass 26, count 0 2006.257.22:35:11.23#ibcon#end of sib2, iclass 26, count 0 2006.257.22:35:11.23#ibcon#*after write, iclass 26, count 0 2006.257.22:35:11.23#ibcon#*before return 0, iclass 26, count 0 2006.257.22:35:11.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:11.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.22:35:11.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.22:35:11.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.22:35:11.23$vck44/vb=1,4 2006.257.22:35:11.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.22:35:11.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.22:35:11.23#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:11.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:11.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:11.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:11.23#ibcon#enter wrdev, iclass 28, count 2 2006.257.22:35:11.23#ibcon#first serial, iclass 28, count 2 2006.257.22:35:11.23#ibcon#enter sib2, iclass 28, count 2 2006.257.22:35:11.23#ibcon#flushed, iclass 28, count 2 2006.257.22:35:11.23#ibcon#about to write, iclass 28, count 2 2006.257.22:35:11.23#ibcon#wrote, iclass 28, count 2 2006.257.22:35:11.23#ibcon#about to read 3, iclass 28, count 2 2006.257.22:35:11.25#ibcon#read 3, iclass 28, count 2 2006.257.22:35:11.25#ibcon#about to read 4, iclass 28, count 2 2006.257.22:35:11.25#ibcon#read 4, iclass 28, count 2 2006.257.22:35:11.25#ibcon#about to read 5, iclass 28, count 2 2006.257.22:35:11.25#ibcon#read 5, iclass 28, count 2 2006.257.22:35:11.25#ibcon#about to read 6, iclass 28, count 2 2006.257.22:35:11.25#ibcon#read 6, iclass 28, count 2 2006.257.22:35:11.25#ibcon#end of sib2, iclass 28, count 2 2006.257.22:35:11.25#ibcon#*mode == 0, iclass 28, count 2 2006.257.22:35:11.25#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.22:35:11.25#ibcon#[27=AT01-04\r\n] 2006.257.22:35:11.25#ibcon#*before write, iclass 28, count 2 2006.257.22:35:11.25#ibcon#enter sib2, iclass 28, count 2 2006.257.22:35:11.25#ibcon#flushed, iclass 28, count 2 2006.257.22:35:11.25#ibcon#about to write, iclass 28, count 2 2006.257.22:35:11.25#ibcon#wrote, iclass 28, count 2 2006.257.22:35:11.25#ibcon#about to read 3, iclass 28, count 2 2006.257.22:35:11.28#ibcon#read 3, iclass 28, count 2 2006.257.22:35:11.28#ibcon#about to read 4, iclass 28, count 2 2006.257.22:35:11.28#ibcon#read 4, iclass 28, count 2 2006.257.22:35:11.28#ibcon#about to read 5, iclass 28, count 2 2006.257.22:35:11.28#ibcon#read 5, iclass 28, count 2 2006.257.22:35:11.28#ibcon#about to read 6, iclass 28, count 2 2006.257.22:35:11.28#ibcon#read 6, iclass 28, count 2 2006.257.22:35:11.28#ibcon#end of sib2, iclass 28, count 2 2006.257.22:35:11.28#ibcon#*after write, iclass 28, count 2 2006.257.22:35:11.28#ibcon#*before return 0, iclass 28, count 2 2006.257.22:35:11.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:11.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.22:35:11.28#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.22:35:11.28#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:11.28#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:11.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:11.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:11.40#ibcon#enter wrdev, iclass 28, count 0 2006.257.22:35:11.40#ibcon#first serial, iclass 28, count 0 2006.257.22:35:11.40#ibcon#enter sib2, iclass 28, count 0 2006.257.22:35:11.40#ibcon#flushed, iclass 28, count 0 2006.257.22:35:11.40#ibcon#about to write, iclass 28, count 0 2006.257.22:35:11.40#ibcon#wrote, iclass 28, count 0 2006.257.22:35:11.40#ibcon#about to read 3, iclass 28, count 0 2006.257.22:35:11.42#ibcon#read 3, iclass 28, count 0 2006.257.22:35:11.42#ibcon#about to read 4, iclass 28, count 0 2006.257.22:35:11.42#ibcon#read 4, iclass 28, count 0 2006.257.22:35:11.42#ibcon#about to read 5, iclass 28, count 0 2006.257.22:35:11.42#ibcon#read 5, iclass 28, count 0 2006.257.22:35:11.42#ibcon#about to read 6, iclass 28, count 0 2006.257.22:35:11.42#ibcon#read 6, iclass 28, count 0 2006.257.22:35:11.42#ibcon#end of sib2, iclass 28, count 0 2006.257.22:35:11.42#ibcon#*mode == 0, iclass 28, count 0 2006.257.22:35:11.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.22:35:11.42#ibcon#[27=USB\r\n] 2006.257.22:35:11.42#ibcon#*before write, iclass 28, count 0 2006.257.22:35:11.42#ibcon#enter sib2, iclass 28, count 0 2006.257.22:35:11.42#ibcon#flushed, iclass 28, count 0 2006.257.22:35:11.42#ibcon#about to write, iclass 28, count 0 2006.257.22:35:11.42#ibcon#wrote, iclass 28, count 0 2006.257.22:35:11.42#ibcon#about to read 3, iclass 28, count 0 2006.257.22:35:11.45#ibcon#read 3, iclass 28, count 0 2006.257.22:35:11.45#ibcon#about to read 4, iclass 28, count 0 2006.257.22:35:11.45#ibcon#read 4, iclass 28, count 0 2006.257.22:35:11.45#ibcon#about to read 5, iclass 28, count 0 2006.257.22:35:11.45#ibcon#read 5, iclass 28, count 0 2006.257.22:35:11.45#ibcon#about to read 6, iclass 28, count 0 2006.257.22:35:11.45#ibcon#read 6, iclass 28, count 0 2006.257.22:35:11.45#ibcon#end of sib2, iclass 28, count 0 2006.257.22:35:11.45#ibcon#*after write, iclass 28, count 0 2006.257.22:35:11.45#ibcon#*before return 0, iclass 28, count 0 2006.257.22:35:11.45#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:11.45#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.22:35:11.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.22:35:11.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.22:35:11.45$vck44/vblo=2,634.99 2006.257.22:35:11.45#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.22:35:11.45#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.22:35:11.45#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:11.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:11.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:11.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:11.45#ibcon#enter wrdev, iclass 30, count 0 2006.257.22:35:11.45#ibcon#first serial, iclass 30, count 0 2006.257.22:35:11.45#ibcon#enter sib2, iclass 30, count 0 2006.257.22:35:11.45#ibcon#flushed, iclass 30, count 0 2006.257.22:35:11.45#ibcon#about to write, iclass 30, count 0 2006.257.22:35:11.45#ibcon#wrote, iclass 30, count 0 2006.257.22:35:11.45#ibcon#about to read 3, iclass 30, count 0 2006.257.22:35:11.47#ibcon#read 3, iclass 30, count 0 2006.257.22:35:11.47#ibcon#about to read 4, iclass 30, count 0 2006.257.22:35:11.47#ibcon#read 4, iclass 30, count 0 2006.257.22:35:11.47#ibcon#about to read 5, iclass 30, count 0 2006.257.22:35:11.47#ibcon#read 5, iclass 30, count 0 2006.257.22:35:11.47#ibcon#about to read 6, iclass 30, count 0 2006.257.22:35:11.47#ibcon#read 6, iclass 30, count 0 2006.257.22:35:11.47#ibcon#end of sib2, iclass 30, count 0 2006.257.22:35:11.47#ibcon#*mode == 0, iclass 30, count 0 2006.257.22:35:11.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.22:35:11.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.22:35:11.47#ibcon#*before write, iclass 30, count 0 2006.257.22:35:11.47#ibcon#enter sib2, iclass 30, count 0 2006.257.22:35:11.47#ibcon#flushed, iclass 30, count 0 2006.257.22:35:11.47#ibcon#about to write, iclass 30, count 0 2006.257.22:35:11.47#ibcon#wrote, iclass 30, count 0 2006.257.22:35:11.47#ibcon#about to read 3, iclass 30, count 0 2006.257.22:35:11.51#ibcon#read 3, iclass 30, count 0 2006.257.22:35:11.51#ibcon#about to read 4, iclass 30, count 0 2006.257.22:35:11.51#ibcon#read 4, iclass 30, count 0 2006.257.22:35:11.51#ibcon#about to read 5, iclass 30, count 0 2006.257.22:35:11.51#ibcon#read 5, iclass 30, count 0 2006.257.22:35:11.51#ibcon#about to read 6, iclass 30, count 0 2006.257.22:35:11.51#ibcon#read 6, iclass 30, count 0 2006.257.22:35:11.51#ibcon#end of sib2, iclass 30, count 0 2006.257.22:35:11.51#ibcon#*after write, iclass 30, count 0 2006.257.22:35:11.51#ibcon#*before return 0, iclass 30, count 0 2006.257.22:35:11.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:11.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.22:35:11.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.22:35:11.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.22:35:11.51$vck44/vb=2,5 2006.257.22:35:11.51#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.22:35:11.51#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.22:35:11.51#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:11.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:11.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:11.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:11.57#ibcon#enter wrdev, iclass 32, count 2 2006.257.22:35:11.57#ibcon#first serial, iclass 32, count 2 2006.257.22:35:11.57#ibcon#enter sib2, iclass 32, count 2 2006.257.22:35:11.57#ibcon#flushed, iclass 32, count 2 2006.257.22:35:11.57#ibcon#about to write, iclass 32, count 2 2006.257.22:35:11.57#ibcon#wrote, iclass 32, count 2 2006.257.22:35:11.57#ibcon#about to read 3, iclass 32, count 2 2006.257.22:35:11.59#ibcon#read 3, iclass 32, count 2 2006.257.22:35:11.59#ibcon#about to read 4, iclass 32, count 2 2006.257.22:35:11.59#ibcon#read 4, iclass 32, count 2 2006.257.22:35:11.59#ibcon#about to read 5, iclass 32, count 2 2006.257.22:35:11.59#ibcon#read 5, iclass 32, count 2 2006.257.22:35:11.59#ibcon#about to read 6, iclass 32, count 2 2006.257.22:35:11.59#ibcon#read 6, iclass 32, count 2 2006.257.22:35:11.59#ibcon#end of sib2, iclass 32, count 2 2006.257.22:35:11.59#ibcon#*mode == 0, iclass 32, count 2 2006.257.22:35:11.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.22:35:11.59#ibcon#[27=AT02-05\r\n] 2006.257.22:35:11.59#ibcon#*before write, iclass 32, count 2 2006.257.22:35:11.59#ibcon#enter sib2, iclass 32, count 2 2006.257.22:35:11.59#ibcon#flushed, iclass 32, count 2 2006.257.22:35:11.59#ibcon#about to write, iclass 32, count 2 2006.257.22:35:11.59#ibcon#wrote, iclass 32, count 2 2006.257.22:35:11.59#ibcon#about to read 3, iclass 32, count 2 2006.257.22:35:11.62#ibcon#read 3, iclass 32, count 2 2006.257.22:35:11.62#ibcon#about to read 4, iclass 32, count 2 2006.257.22:35:11.62#ibcon#read 4, iclass 32, count 2 2006.257.22:35:11.62#ibcon#about to read 5, iclass 32, count 2 2006.257.22:35:11.62#ibcon#read 5, iclass 32, count 2 2006.257.22:35:11.62#ibcon#about to read 6, iclass 32, count 2 2006.257.22:35:11.62#ibcon#read 6, iclass 32, count 2 2006.257.22:35:11.62#ibcon#end of sib2, iclass 32, count 2 2006.257.22:35:11.62#ibcon#*after write, iclass 32, count 2 2006.257.22:35:11.62#ibcon#*before return 0, iclass 32, count 2 2006.257.22:35:11.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:11.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.22:35:11.62#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.22:35:11.62#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:11.62#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:11.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:11.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:11.74#ibcon#enter wrdev, iclass 32, count 0 2006.257.22:35:11.74#ibcon#first serial, iclass 32, count 0 2006.257.22:35:11.74#ibcon#enter sib2, iclass 32, count 0 2006.257.22:35:11.74#ibcon#flushed, iclass 32, count 0 2006.257.22:35:11.74#ibcon#about to write, iclass 32, count 0 2006.257.22:35:11.74#ibcon#wrote, iclass 32, count 0 2006.257.22:35:11.74#ibcon#about to read 3, iclass 32, count 0 2006.257.22:35:11.76#ibcon#read 3, iclass 32, count 0 2006.257.22:35:11.76#ibcon#about to read 4, iclass 32, count 0 2006.257.22:35:11.76#ibcon#read 4, iclass 32, count 0 2006.257.22:35:11.76#ibcon#about to read 5, iclass 32, count 0 2006.257.22:35:11.76#ibcon#read 5, iclass 32, count 0 2006.257.22:35:11.76#ibcon#about to read 6, iclass 32, count 0 2006.257.22:35:11.76#ibcon#read 6, iclass 32, count 0 2006.257.22:35:11.76#ibcon#end of sib2, iclass 32, count 0 2006.257.22:35:11.76#ibcon#*mode == 0, iclass 32, count 0 2006.257.22:35:11.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.22:35:11.76#ibcon#[27=USB\r\n] 2006.257.22:35:11.76#ibcon#*before write, iclass 32, count 0 2006.257.22:35:11.76#ibcon#enter sib2, iclass 32, count 0 2006.257.22:35:11.76#ibcon#flushed, iclass 32, count 0 2006.257.22:35:11.76#ibcon#about to write, iclass 32, count 0 2006.257.22:35:11.76#ibcon#wrote, iclass 32, count 0 2006.257.22:35:11.76#ibcon#about to read 3, iclass 32, count 0 2006.257.22:35:11.79#ibcon#read 3, iclass 32, count 0 2006.257.22:35:11.79#ibcon#about to read 4, iclass 32, count 0 2006.257.22:35:11.79#ibcon#read 4, iclass 32, count 0 2006.257.22:35:11.79#ibcon#about to read 5, iclass 32, count 0 2006.257.22:35:11.79#ibcon#read 5, iclass 32, count 0 2006.257.22:35:11.79#ibcon#about to read 6, iclass 32, count 0 2006.257.22:35:11.79#ibcon#read 6, iclass 32, count 0 2006.257.22:35:11.79#ibcon#end of sib2, iclass 32, count 0 2006.257.22:35:11.79#ibcon#*after write, iclass 32, count 0 2006.257.22:35:11.79#ibcon#*before return 0, iclass 32, count 0 2006.257.22:35:11.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:11.79#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.22:35:11.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.22:35:11.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.22:35:11.79$vck44/vblo=3,649.99 2006.257.22:35:11.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.22:35:11.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.22:35:11.79#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:11.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:11.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:11.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:11.79#ibcon#enter wrdev, iclass 34, count 0 2006.257.22:35:11.79#ibcon#first serial, iclass 34, count 0 2006.257.22:35:11.79#ibcon#enter sib2, iclass 34, count 0 2006.257.22:35:11.79#ibcon#flushed, iclass 34, count 0 2006.257.22:35:11.79#ibcon#about to write, iclass 34, count 0 2006.257.22:35:11.79#ibcon#wrote, iclass 34, count 0 2006.257.22:35:11.79#ibcon#about to read 3, iclass 34, count 0 2006.257.22:35:11.81#ibcon#read 3, iclass 34, count 0 2006.257.22:35:11.81#ibcon#about to read 4, iclass 34, count 0 2006.257.22:35:11.81#ibcon#read 4, iclass 34, count 0 2006.257.22:35:11.81#ibcon#about to read 5, iclass 34, count 0 2006.257.22:35:11.81#ibcon#read 5, iclass 34, count 0 2006.257.22:35:11.81#ibcon#about to read 6, iclass 34, count 0 2006.257.22:35:11.81#ibcon#read 6, iclass 34, count 0 2006.257.22:35:11.81#ibcon#end of sib2, iclass 34, count 0 2006.257.22:35:11.81#ibcon#*mode == 0, iclass 34, count 0 2006.257.22:35:11.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.22:35:11.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.22:35:11.81#ibcon#*before write, iclass 34, count 0 2006.257.22:35:11.81#ibcon#enter sib2, iclass 34, count 0 2006.257.22:35:11.81#ibcon#flushed, iclass 34, count 0 2006.257.22:35:11.81#ibcon#about to write, iclass 34, count 0 2006.257.22:35:11.81#ibcon#wrote, iclass 34, count 0 2006.257.22:35:11.81#ibcon#about to read 3, iclass 34, count 0 2006.257.22:35:11.85#ibcon#read 3, iclass 34, count 0 2006.257.22:35:11.85#ibcon#about to read 4, iclass 34, count 0 2006.257.22:35:11.85#ibcon#read 4, iclass 34, count 0 2006.257.22:35:11.85#ibcon#about to read 5, iclass 34, count 0 2006.257.22:35:11.85#ibcon#read 5, iclass 34, count 0 2006.257.22:35:11.85#ibcon#about to read 6, iclass 34, count 0 2006.257.22:35:11.85#ibcon#read 6, iclass 34, count 0 2006.257.22:35:11.85#ibcon#end of sib2, iclass 34, count 0 2006.257.22:35:11.85#ibcon#*after write, iclass 34, count 0 2006.257.22:35:11.85#ibcon#*before return 0, iclass 34, count 0 2006.257.22:35:11.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:11.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.22:35:11.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.22:35:11.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.22:35:11.85$vck44/vb=3,4 2006.257.22:35:11.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.22:35:11.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.22:35:11.85#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:11.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:11.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:11.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:11.91#ibcon#enter wrdev, iclass 36, count 2 2006.257.22:35:11.91#ibcon#first serial, iclass 36, count 2 2006.257.22:35:11.91#ibcon#enter sib2, iclass 36, count 2 2006.257.22:35:11.91#ibcon#flushed, iclass 36, count 2 2006.257.22:35:11.91#ibcon#about to write, iclass 36, count 2 2006.257.22:35:11.91#ibcon#wrote, iclass 36, count 2 2006.257.22:35:11.91#ibcon#about to read 3, iclass 36, count 2 2006.257.22:35:11.93#ibcon#read 3, iclass 36, count 2 2006.257.22:35:11.93#ibcon#about to read 4, iclass 36, count 2 2006.257.22:35:11.93#ibcon#read 4, iclass 36, count 2 2006.257.22:35:11.93#ibcon#about to read 5, iclass 36, count 2 2006.257.22:35:11.93#ibcon#read 5, iclass 36, count 2 2006.257.22:35:11.93#ibcon#about to read 6, iclass 36, count 2 2006.257.22:35:11.93#ibcon#read 6, iclass 36, count 2 2006.257.22:35:11.93#ibcon#end of sib2, iclass 36, count 2 2006.257.22:35:11.93#ibcon#*mode == 0, iclass 36, count 2 2006.257.22:35:11.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.22:35:11.93#ibcon#[27=AT03-04\r\n] 2006.257.22:35:11.93#ibcon#*before write, iclass 36, count 2 2006.257.22:35:11.93#ibcon#enter sib2, iclass 36, count 2 2006.257.22:35:11.93#ibcon#flushed, iclass 36, count 2 2006.257.22:35:11.93#ibcon#about to write, iclass 36, count 2 2006.257.22:35:11.93#ibcon#wrote, iclass 36, count 2 2006.257.22:35:11.93#ibcon#about to read 3, iclass 36, count 2 2006.257.22:35:11.96#ibcon#read 3, iclass 36, count 2 2006.257.22:35:11.96#ibcon#about to read 4, iclass 36, count 2 2006.257.22:35:11.96#ibcon#read 4, iclass 36, count 2 2006.257.22:35:11.96#ibcon#about to read 5, iclass 36, count 2 2006.257.22:35:11.96#ibcon#read 5, iclass 36, count 2 2006.257.22:35:11.96#ibcon#about to read 6, iclass 36, count 2 2006.257.22:35:11.96#ibcon#read 6, iclass 36, count 2 2006.257.22:35:11.96#ibcon#end of sib2, iclass 36, count 2 2006.257.22:35:11.96#ibcon#*after write, iclass 36, count 2 2006.257.22:35:11.96#ibcon#*before return 0, iclass 36, count 2 2006.257.22:35:11.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:11.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.22:35:11.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.22:35:11.96#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:11.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:12.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:12.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:12.08#ibcon#enter wrdev, iclass 36, count 0 2006.257.22:35:12.08#ibcon#first serial, iclass 36, count 0 2006.257.22:35:12.08#ibcon#enter sib2, iclass 36, count 0 2006.257.22:35:12.08#ibcon#flushed, iclass 36, count 0 2006.257.22:35:12.08#ibcon#about to write, iclass 36, count 0 2006.257.22:35:12.08#ibcon#wrote, iclass 36, count 0 2006.257.22:35:12.08#ibcon#about to read 3, iclass 36, count 0 2006.257.22:35:12.10#ibcon#read 3, iclass 36, count 0 2006.257.22:35:12.10#ibcon#about to read 4, iclass 36, count 0 2006.257.22:35:12.10#ibcon#read 4, iclass 36, count 0 2006.257.22:35:12.10#ibcon#about to read 5, iclass 36, count 0 2006.257.22:35:12.10#ibcon#read 5, iclass 36, count 0 2006.257.22:35:12.10#ibcon#about to read 6, iclass 36, count 0 2006.257.22:35:12.10#ibcon#read 6, iclass 36, count 0 2006.257.22:35:12.10#ibcon#end of sib2, iclass 36, count 0 2006.257.22:35:12.10#ibcon#*mode == 0, iclass 36, count 0 2006.257.22:35:12.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.22:35:12.10#ibcon#[27=USB\r\n] 2006.257.22:35:12.10#ibcon#*before write, iclass 36, count 0 2006.257.22:35:12.10#ibcon#enter sib2, iclass 36, count 0 2006.257.22:35:12.10#ibcon#flushed, iclass 36, count 0 2006.257.22:35:12.10#ibcon#about to write, iclass 36, count 0 2006.257.22:35:12.10#ibcon#wrote, iclass 36, count 0 2006.257.22:35:12.10#ibcon#about to read 3, iclass 36, count 0 2006.257.22:35:12.13#ibcon#read 3, iclass 36, count 0 2006.257.22:35:12.13#ibcon#about to read 4, iclass 36, count 0 2006.257.22:35:12.13#ibcon#read 4, iclass 36, count 0 2006.257.22:35:12.13#ibcon#about to read 5, iclass 36, count 0 2006.257.22:35:12.13#ibcon#read 5, iclass 36, count 0 2006.257.22:35:12.13#ibcon#about to read 6, iclass 36, count 0 2006.257.22:35:12.13#ibcon#read 6, iclass 36, count 0 2006.257.22:35:12.13#ibcon#end of sib2, iclass 36, count 0 2006.257.22:35:12.13#ibcon#*after write, iclass 36, count 0 2006.257.22:35:12.13#ibcon#*before return 0, iclass 36, count 0 2006.257.22:35:12.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:12.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.22:35:12.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.22:35:12.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.22:35:12.13$vck44/vblo=4,679.99 2006.257.22:35:12.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.22:35:12.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.22:35:12.13#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:12.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:12.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:12.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:12.13#ibcon#enter wrdev, iclass 38, count 0 2006.257.22:35:12.13#ibcon#first serial, iclass 38, count 0 2006.257.22:35:12.13#ibcon#enter sib2, iclass 38, count 0 2006.257.22:35:12.13#ibcon#flushed, iclass 38, count 0 2006.257.22:35:12.13#ibcon#about to write, iclass 38, count 0 2006.257.22:35:12.13#ibcon#wrote, iclass 38, count 0 2006.257.22:35:12.13#ibcon#about to read 3, iclass 38, count 0 2006.257.22:35:12.15#ibcon#read 3, iclass 38, count 0 2006.257.22:35:12.15#ibcon#about to read 4, iclass 38, count 0 2006.257.22:35:12.15#ibcon#read 4, iclass 38, count 0 2006.257.22:35:12.15#ibcon#about to read 5, iclass 38, count 0 2006.257.22:35:12.15#ibcon#read 5, iclass 38, count 0 2006.257.22:35:12.15#ibcon#about to read 6, iclass 38, count 0 2006.257.22:35:12.15#ibcon#read 6, iclass 38, count 0 2006.257.22:35:12.15#ibcon#end of sib2, iclass 38, count 0 2006.257.22:35:12.15#ibcon#*mode == 0, iclass 38, count 0 2006.257.22:35:12.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.22:35:12.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.22:35:12.15#ibcon#*before write, iclass 38, count 0 2006.257.22:35:12.15#ibcon#enter sib2, iclass 38, count 0 2006.257.22:35:12.15#ibcon#flushed, iclass 38, count 0 2006.257.22:35:12.15#ibcon#about to write, iclass 38, count 0 2006.257.22:35:12.15#ibcon#wrote, iclass 38, count 0 2006.257.22:35:12.15#ibcon#about to read 3, iclass 38, count 0 2006.257.22:35:12.19#ibcon#read 3, iclass 38, count 0 2006.257.22:35:12.19#ibcon#about to read 4, iclass 38, count 0 2006.257.22:35:12.19#ibcon#read 4, iclass 38, count 0 2006.257.22:35:12.19#ibcon#about to read 5, iclass 38, count 0 2006.257.22:35:12.19#ibcon#read 5, iclass 38, count 0 2006.257.22:35:12.19#ibcon#about to read 6, iclass 38, count 0 2006.257.22:35:12.19#ibcon#read 6, iclass 38, count 0 2006.257.22:35:12.19#ibcon#end of sib2, iclass 38, count 0 2006.257.22:35:12.19#ibcon#*after write, iclass 38, count 0 2006.257.22:35:12.19#ibcon#*before return 0, iclass 38, count 0 2006.257.22:35:12.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:12.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.22:35:12.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.22:35:12.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.22:35:12.19$vck44/vb=4,5 2006.257.22:35:12.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.22:35:12.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.22:35:12.19#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:12.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:12.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:12.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:12.25#ibcon#enter wrdev, iclass 40, count 2 2006.257.22:35:12.25#ibcon#first serial, iclass 40, count 2 2006.257.22:35:12.25#ibcon#enter sib2, iclass 40, count 2 2006.257.22:35:12.25#ibcon#flushed, iclass 40, count 2 2006.257.22:35:12.25#ibcon#about to write, iclass 40, count 2 2006.257.22:35:12.25#ibcon#wrote, iclass 40, count 2 2006.257.22:35:12.25#ibcon#about to read 3, iclass 40, count 2 2006.257.22:35:12.27#ibcon#read 3, iclass 40, count 2 2006.257.22:35:12.27#ibcon#about to read 4, iclass 40, count 2 2006.257.22:35:12.27#ibcon#read 4, iclass 40, count 2 2006.257.22:35:12.27#ibcon#about to read 5, iclass 40, count 2 2006.257.22:35:12.27#ibcon#read 5, iclass 40, count 2 2006.257.22:35:12.27#ibcon#about to read 6, iclass 40, count 2 2006.257.22:35:12.27#ibcon#read 6, iclass 40, count 2 2006.257.22:35:12.27#ibcon#end of sib2, iclass 40, count 2 2006.257.22:35:12.27#ibcon#*mode == 0, iclass 40, count 2 2006.257.22:35:12.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.22:35:12.27#ibcon#[27=AT04-05\r\n] 2006.257.22:35:12.27#ibcon#*before write, iclass 40, count 2 2006.257.22:35:12.27#ibcon#enter sib2, iclass 40, count 2 2006.257.22:35:12.27#ibcon#flushed, iclass 40, count 2 2006.257.22:35:12.27#ibcon#about to write, iclass 40, count 2 2006.257.22:35:12.27#ibcon#wrote, iclass 40, count 2 2006.257.22:35:12.27#ibcon#about to read 3, iclass 40, count 2 2006.257.22:35:12.30#ibcon#read 3, iclass 40, count 2 2006.257.22:35:12.30#ibcon#about to read 4, iclass 40, count 2 2006.257.22:35:12.30#ibcon#read 4, iclass 40, count 2 2006.257.22:35:12.30#ibcon#about to read 5, iclass 40, count 2 2006.257.22:35:12.30#ibcon#read 5, iclass 40, count 2 2006.257.22:35:12.30#ibcon#about to read 6, iclass 40, count 2 2006.257.22:35:12.30#ibcon#read 6, iclass 40, count 2 2006.257.22:35:12.30#ibcon#end of sib2, iclass 40, count 2 2006.257.22:35:12.30#ibcon#*after write, iclass 40, count 2 2006.257.22:35:12.30#ibcon#*before return 0, iclass 40, count 2 2006.257.22:35:12.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:12.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.22:35:12.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.22:35:12.30#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:12.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:12.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:12.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:12.42#ibcon#enter wrdev, iclass 40, count 0 2006.257.22:35:12.42#ibcon#first serial, iclass 40, count 0 2006.257.22:35:12.42#ibcon#enter sib2, iclass 40, count 0 2006.257.22:35:12.42#ibcon#flushed, iclass 40, count 0 2006.257.22:35:12.42#ibcon#about to write, iclass 40, count 0 2006.257.22:35:12.42#ibcon#wrote, iclass 40, count 0 2006.257.22:35:12.42#ibcon#about to read 3, iclass 40, count 0 2006.257.22:35:12.44#ibcon#read 3, iclass 40, count 0 2006.257.22:35:12.44#ibcon#about to read 4, iclass 40, count 0 2006.257.22:35:12.44#ibcon#read 4, iclass 40, count 0 2006.257.22:35:12.44#ibcon#about to read 5, iclass 40, count 0 2006.257.22:35:12.44#ibcon#read 5, iclass 40, count 0 2006.257.22:35:12.44#ibcon#about to read 6, iclass 40, count 0 2006.257.22:35:12.44#ibcon#read 6, iclass 40, count 0 2006.257.22:35:12.44#ibcon#end of sib2, iclass 40, count 0 2006.257.22:35:12.44#ibcon#*mode == 0, iclass 40, count 0 2006.257.22:35:12.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.22:35:12.44#ibcon#[27=USB\r\n] 2006.257.22:35:12.44#ibcon#*before write, iclass 40, count 0 2006.257.22:35:12.44#ibcon#enter sib2, iclass 40, count 0 2006.257.22:35:12.44#ibcon#flushed, iclass 40, count 0 2006.257.22:35:12.44#ibcon#about to write, iclass 40, count 0 2006.257.22:35:12.44#ibcon#wrote, iclass 40, count 0 2006.257.22:35:12.44#ibcon#about to read 3, iclass 40, count 0 2006.257.22:35:12.47#ibcon#read 3, iclass 40, count 0 2006.257.22:35:12.47#ibcon#about to read 4, iclass 40, count 0 2006.257.22:35:12.47#ibcon#read 4, iclass 40, count 0 2006.257.22:35:12.47#ibcon#about to read 5, iclass 40, count 0 2006.257.22:35:12.47#ibcon#read 5, iclass 40, count 0 2006.257.22:35:12.47#ibcon#about to read 6, iclass 40, count 0 2006.257.22:35:12.47#ibcon#read 6, iclass 40, count 0 2006.257.22:35:12.47#ibcon#end of sib2, iclass 40, count 0 2006.257.22:35:12.47#ibcon#*after write, iclass 40, count 0 2006.257.22:35:12.47#ibcon#*before return 0, iclass 40, count 0 2006.257.22:35:12.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:12.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.22:35:12.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.22:35:12.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.22:35:12.47$vck44/vblo=5,709.99 2006.257.22:35:12.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.22:35:12.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.22:35:12.47#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:12.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:12.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:12.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:12.47#ibcon#enter wrdev, iclass 4, count 0 2006.257.22:35:12.47#ibcon#first serial, iclass 4, count 0 2006.257.22:35:12.47#ibcon#enter sib2, iclass 4, count 0 2006.257.22:35:12.47#ibcon#flushed, iclass 4, count 0 2006.257.22:35:12.47#ibcon#about to write, iclass 4, count 0 2006.257.22:35:12.47#ibcon#wrote, iclass 4, count 0 2006.257.22:35:12.47#ibcon#about to read 3, iclass 4, count 0 2006.257.22:35:12.49#ibcon#read 3, iclass 4, count 0 2006.257.22:35:12.49#ibcon#about to read 4, iclass 4, count 0 2006.257.22:35:12.49#ibcon#read 4, iclass 4, count 0 2006.257.22:35:12.49#ibcon#about to read 5, iclass 4, count 0 2006.257.22:35:12.49#ibcon#read 5, iclass 4, count 0 2006.257.22:35:12.49#ibcon#about to read 6, iclass 4, count 0 2006.257.22:35:12.49#ibcon#read 6, iclass 4, count 0 2006.257.22:35:12.49#ibcon#end of sib2, iclass 4, count 0 2006.257.22:35:12.49#ibcon#*mode == 0, iclass 4, count 0 2006.257.22:35:12.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.22:35:12.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.22:35:12.49#ibcon#*before write, iclass 4, count 0 2006.257.22:35:12.49#ibcon#enter sib2, iclass 4, count 0 2006.257.22:35:12.49#ibcon#flushed, iclass 4, count 0 2006.257.22:35:12.49#ibcon#about to write, iclass 4, count 0 2006.257.22:35:12.49#ibcon#wrote, iclass 4, count 0 2006.257.22:35:12.49#ibcon#about to read 3, iclass 4, count 0 2006.257.22:35:12.53#ibcon#read 3, iclass 4, count 0 2006.257.22:35:12.53#ibcon#about to read 4, iclass 4, count 0 2006.257.22:35:12.53#ibcon#read 4, iclass 4, count 0 2006.257.22:35:12.53#ibcon#about to read 5, iclass 4, count 0 2006.257.22:35:12.53#ibcon#read 5, iclass 4, count 0 2006.257.22:35:12.53#ibcon#about to read 6, iclass 4, count 0 2006.257.22:35:12.53#ibcon#read 6, iclass 4, count 0 2006.257.22:35:12.53#ibcon#end of sib2, iclass 4, count 0 2006.257.22:35:12.53#ibcon#*after write, iclass 4, count 0 2006.257.22:35:12.53#ibcon#*before return 0, iclass 4, count 0 2006.257.22:35:12.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:12.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.22:35:12.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.22:35:12.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.22:35:12.53$vck44/vb=5,4 2006.257.22:35:12.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.22:35:12.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.22:35:12.53#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:12.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:12.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:12.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:12.59#ibcon#enter wrdev, iclass 6, count 2 2006.257.22:35:12.59#ibcon#first serial, iclass 6, count 2 2006.257.22:35:12.59#ibcon#enter sib2, iclass 6, count 2 2006.257.22:35:12.59#ibcon#flushed, iclass 6, count 2 2006.257.22:35:12.59#ibcon#about to write, iclass 6, count 2 2006.257.22:35:12.59#ibcon#wrote, iclass 6, count 2 2006.257.22:35:12.59#ibcon#about to read 3, iclass 6, count 2 2006.257.22:35:12.61#ibcon#read 3, iclass 6, count 2 2006.257.22:35:12.61#ibcon#about to read 4, iclass 6, count 2 2006.257.22:35:12.61#ibcon#read 4, iclass 6, count 2 2006.257.22:35:12.61#ibcon#about to read 5, iclass 6, count 2 2006.257.22:35:12.61#ibcon#read 5, iclass 6, count 2 2006.257.22:35:12.61#ibcon#about to read 6, iclass 6, count 2 2006.257.22:35:12.61#ibcon#read 6, iclass 6, count 2 2006.257.22:35:12.61#ibcon#end of sib2, iclass 6, count 2 2006.257.22:35:12.61#ibcon#*mode == 0, iclass 6, count 2 2006.257.22:35:12.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.22:35:12.61#ibcon#[27=AT05-04\r\n] 2006.257.22:35:12.61#ibcon#*before write, iclass 6, count 2 2006.257.22:35:12.61#ibcon#enter sib2, iclass 6, count 2 2006.257.22:35:12.61#ibcon#flushed, iclass 6, count 2 2006.257.22:35:12.61#ibcon#about to write, iclass 6, count 2 2006.257.22:35:12.61#ibcon#wrote, iclass 6, count 2 2006.257.22:35:12.61#ibcon#about to read 3, iclass 6, count 2 2006.257.22:35:12.64#ibcon#read 3, iclass 6, count 2 2006.257.22:35:12.64#ibcon#about to read 4, iclass 6, count 2 2006.257.22:35:12.64#ibcon#read 4, iclass 6, count 2 2006.257.22:35:12.64#ibcon#about to read 5, iclass 6, count 2 2006.257.22:35:12.64#ibcon#read 5, iclass 6, count 2 2006.257.22:35:12.64#ibcon#about to read 6, iclass 6, count 2 2006.257.22:35:12.64#ibcon#read 6, iclass 6, count 2 2006.257.22:35:12.64#ibcon#end of sib2, iclass 6, count 2 2006.257.22:35:12.64#ibcon#*after write, iclass 6, count 2 2006.257.22:35:12.64#ibcon#*before return 0, iclass 6, count 2 2006.257.22:35:12.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:12.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.22:35:12.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.22:35:12.64#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:12.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:12.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:12.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:12.76#ibcon#enter wrdev, iclass 6, count 0 2006.257.22:35:12.76#ibcon#first serial, iclass 6, count 0 2006.257.22:35:12.76#ibcon#enter sib2, iclass 6, count 0 2006.257.22:35:12.76#ibcon#flushed, iclass 6, count 0 2006.257.22:35:12.76#ibcon#about to write, iclass 6, count 0 2006.257.22:35:12.76#ibcon#wrote, iclass 6, count 0 2006.257.22:35:12.76#ibcon#about to read 3, iclass 6, count 0 2006.257.22:35:12.78#ibcon#read 3, iclass 6, count 0 2006.257.22:35:12.78#ibcon#about to read 4, iclass 6, count 0 2006.257.22:35:12.78#ibcon#read 4, iclass 6, count 0 2006.257.22:35:12.78#ibcon#about to read 5, iclass 6, count 0 2006.257.22:35:12.78#ibcon#read 5, iclass 6, count 0 2006.257.22:35:12.78#ibcon#about to read 6, iclass 6, count 0 2006.257.22:35:12.78#ibcon#read 6, iclass 6, count 0 2006.257.22:35:12.78#ibcon#end of sib2, iclass 6, count 0 2006.257.22:35:12.78#ibcon#*mode == 0, iclass 6, count 0 2006.257.22:35:12.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.22:35:12.78#ibcon#[27=USB\r\n] 2006.257.22:35:12.78#ibcon#*before write, iclass 6, count 0 2006.257.22:35:12.78#ibcon#enter sib2, iclass 6, count 0 2006.257.22:35:12.78#ibcon#flushed, iclass 6, count 0 2006.257.22:35:12.78#ibcon#about to write, iclass 6, count 0 2006.257.22:35:12.78#ibcon#wrote, iclass 6, count 0 2006.257.22:35:12.78#ibcon#about to read 3, iclass 6, count 0 2006.257.22:35:12.81#ibcon#read 3, iclass 6, count 0 2006.257.22:35:12.81#ibcon#about to read 4, iclass 6, count 0 2006.257.22:35:12.81#ibcon#read 4, iclass 6, count 0 2006.257.22:35:12.81#ibcon#about to read 5, iclass 6, count 0 2006.257.22:35:12.81#ibcon#read 5, iclass 6, count 0 2006.257.22:35:12.81#ibcon#about to read 6, iclass 6, count 0 2006.257.22:35:12.81#ibcon#read 6, iclass 6, count 0 2006.257.22:35:12.81#ibcon#end of sib2, iclass 6, count 0 2006.257.22:35:12.81#ibcon#*after write, iclass 6, count 0 2006.257.22:35:12.81#ibcon#*before return 0, iclass 6, count 0 2006.257.22:35:12.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:12.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.22:35:12.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.22:35:12.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.22:35:12.81$vck44/vblo=6,719.99 2006.257.22:35:12.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.22:35:12.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.22:35:12.81#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:12.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.22:35:12.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.22:35:12.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.22:35:12.81#ibcon#enter wrdev, iclass 10, count 0 2006.257.22:35:12.81#ibcon#first serial, iclass 10, count 0 2006.257.22:35:12.81#ibcon#enter sib2, iclass 10, count 0 2006.257.22:35:12.81#ibcon#flushed, iclass 10, count 0 2006.257.22:35:12.81#ibcon#about to write, iclass 10, count 0 2006.257.22:35:12.81#ibcon#wrote, iclass 10, count 0 2006.257.22:35:12.81#ibcon#about to read 3, iclass 10, count 0 2006.257.22:35:12.83#ibcon#read 3, iclass 10, count 0 2006.257.22:35:12.83#ibcon#about to read 4, iclass 10, count 0 2006.257.22:35:12.83#ibcon#read 4, iclass 10, count 0 2006.257.22:35:12.83#ibcon#about to read 5, iclass 10, count 0 2006.257.22:35:12.83#ibcon#read 5, iclass 10, count 0 2006.257.22:35:12.83#ibcon#about to read 6, iclass 10, count 0 2006.257.22:35:12.83#ibcon#read 6, iclass 10, count 0 2006.257.22:35:12.83#ibcon#end of sib2, iclass 10, count 0 2006.257.22:35:12.83#ibcon#*mode == 0, iclass 10, count 0 2006.257.22:35:12.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.22:35:12.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.22:35:12.83#ibcon#*before write, iclass 10, count 0 2006.257.22:35:12.83#ibcon#enter sib2, iclass 10, count 0 2006.257.22:35:12.83#ibcon#flushed, iclass 10, count 0 2006.257.22:35:12.83#ibcon#about to write, iclass 10, count 0 2006.257.22:35:12.83#ibcon#wrote, iclass 10, count 0 2006.257.22:35:12.83#ibcon#about to read 3, iclass 10, count 0 2006.257.22:35:12.87#ibcon#read 3, iclass 10, count 0 2006.257.22:35:12.87#ibcon#about to read 4, iclass 10, count 0 2006.257.22:35:12.87#ibcon#read 4, iclass 10, count 0 2006.257.22:35:12.87#ibcon#about to read 5, iclass 10, count 0 2006.257.22:35:12.87#ibcon#read 5, iclass 10, count 0 2006.257.22:35:12.87#ibcon#about to read 6, iclass 10, count 0 2006.257.22:35:12.87#ibcon#read 6, iclass 10, count 0 2006.257.22:35:12.87#ibcon#end of sib2, iclass 10, count 0 2006.257.22:35:12.87#ibcon#*after write, iclass 10, count 0 2006.257.22:35:12.87#ibcon#*before return 0, iclass 10, count 0 2006.257.22:35:12.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.22:35:12.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.22:35:12.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.22:35:12.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.22:35:12.87$vck44/vb=6,4 2006.257.22:35:12.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.22:35:12.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.22:35:12.87#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:12.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.22:35:12.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.22:35:12.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.22:35:12.93#ibcon#enter wrdev, iclass 12, count 2 2006.257.22:35:12.93#ibcon#first serial, iclass 12, count 2 2006.257.22:35:12.93#ibcon#enter sib2, iclass 12, count 2 2006.257.22:35:12.93#ibcon#flushed, iclass 12, count 2 2006.257.22:35:12.93#ibcon#about to write, iclass 12, count 2 2006.257.22:35:12.93#ibcon#wrote, iclass 12, count 2 2006.257.22:35:12.93#ibcon#about to read 3, iclass 12, count 2 2006.257.22:35:12.95#ibcon#read 3, iclass 12, count 2 2006.257.22:35:12.95#ibcon#about to read 4, iclass 12, count 2 2006.257.22:35:12.95#ibcon#read 4, iclass 12, count 2 2006.257.22:35:12.95#ibcon#about to read 5, iclass 12, count 2 2006.257.22:35:12.95#ibcon#read 5, iclass 12, count 2 2006.257.22:35:12.95#ibcon#about to read 6, iclass 12, count 2 2006.257.22:35:12.95#ibcon#read 6, iclass 12, count 2 2006.257.22:35:12.95#ibcon#end of sib2, iclass 12, count 2 2006.257.22:35:12.95#ibcon#*mode == 0, iclass 12, count 2 2006.257.22:35:12.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.22:35:12.95#ibcon#[27=AT06-04\r\n] 2006.257.22:35:12.95#ibcon#*before write, iclass 12, count 2 2006.257.22:35:12.95#ibcon#enter sib2, iclass 12, count 2 2006.257.22:35:12.95#ibcon#flushed, iclass 12, count 2 2006.257.22:35:12.95#ibcon#about to write, iclass 12, count 2 2006.257.22:35:12.95#ibcon#wrote, iclass 12, count 2 2006.257.22:35:12.95#ibcon#about to read 3, iclass 12, count 2 2006.257.22:35:12.98#ibcon#read 3, iclass 12, count 2 2006.257.22:35:12.98#ibcon#about to read 4, iclass 12, count 2 2006.257.22:35:12.98#ibcon#read 4, iclass 12, count 2 2006.257.22:35:12.98#ibcon#about to read 5, iclass 12, count 2 2006.257.22:35:12.98#ibcon#read 5, iclass 12, count 2 2006.257.22:35:12.98#ibcon#about to read 6, iclass 12, count 2 2006.257.22:35:12.98#ibcon#read 6, iclass 12, count 2 2006.257.22:35:12.98#ibcon#end of sib2, iclass 12, count 2 2006.257.22:35:12.98#ibcon#*after write, iclass 12, count 2 2006.257.22:35:12.98#ibcon#*before return 0, iclass 12, count 2 2006.257.22:35:12.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.22:35:12.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.22:35:12.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.22:35:12.98#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:12.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.22:35:13.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.22:35:13.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.22:35:13.10#ibcon#enter wrdev, iclass 12, count 0 2006.257.22:35:13.10#ibcon#first serial, iclass 12, count 0 2006.257.22:35:13.10#ibcon#enter sib2, iclass 12, count 0 2006.257.22:35:13.10#ibcon#flushed, iclass 12, count 0 2006.257.22:35:13.10#ibcon#about to write, iclass 12, count 0 2006.257.22:35:13.10#ibcon#wrote, iclass 12, count 0 2006.257.22:35:13.10#ibcon#about to read 3, iclass 12, count 0 2006.257.22:35:13.12#ibcon#read 3, iclass 12, count 0 2006.257.22:35:13.12#ibcon#about to read 4, iclass 12, count 0 2006.257.22:35:13.12#ibcon#read 4, iclass 12, count 0 2006.257.22:35:13.12#ibcon#about to read 5, iclass 12, count 0 2006.257.22:35:13.12#ibcon#read 5, iclass 12, count 0 2006.257.22:35:13.12#ibcon#about to read 6, iclass 12, count 0 2006.257.22:35:13.12#ibcon#read 6, iclass 12, count 0 2006.257.22:35:13.12#ibcon#end of sib2, iclass 12, count 0 2006.257.22:35:13.12#ibcon#*mode == 0, iclass 12, count 0 2006.257.22:35:13.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.22:35:13.12#ibcon#[27=USB\r\n] 2006.257.22:35:13.12#ibcon#*before write, iclass 12, count 0 2006.257.22:35:13.12#ibcon#enter sib2, iclass 12, count 0 2006.257.22:35:13.12#ibcon#flushed, iclass 12, count 0 2006.257.22:35:13.12#ibcon#about to write, iclass 12, count 0 2006.257.22:35:13.12#ibcon#wrote, iclass 12, count 0 2006.257.22:35:13.12#ibcon#about to read 3, iclass 12, count 0 2006.257.22:35:13.15#ibcon#read 3, iclass 12, count 0 2006.257.22:35:13.15#ibcon#about to read 4, iclass 12, count 0 2006.257.22:35:13.15#ibcon#read 4, iclass 12, count 0 2006.257.22:35:13.15#ibcon#about to read 5, iclass 12, count 0 2006.257.22:35:13.15#ibcon#read 5, iclass 12, count 0 2006.257.22:35:13.15#ibcon#about to read 6, iclass 12, count 0 2006.257.22:35:13.15#ibcon#read 6, iclass 12, count 0 2006.257.22:35:13.15#ibcon#end of sib2, iclass 12, count 0 2006.257.22:35:13.15#ibcon#*after write, iclass 12, count 0 2006.257.22:35:13.15#ibcon#*before return 0, iclass 12, count 0 2006.257.22:35:13.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.22:35:13.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.22:35:13.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.22:35:13.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.22:35:13.15$vck44/vblo=7,734.99 2006.257.22:35:13.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.22:35:13.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.22:35:13.15#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:13.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:13.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:13.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:13.15#ibcon#enter wrdev, iclass 14, count 0 2006.257.22:35:13.15#ibcon#first serial, iclass 14, count 0 2006.257.22:35:13.15#ibcon#enter sib2, iclass 14, count 0 2006.257.22:35:13.15#ibcon#flushed, iclass 14, count 0 2006.257.22:35:13.15#ibcon#about to write, iclass 14, count 0 2006.257.22:35:13.15#ibcon#wrote, iclass 14, count 0 2006.257.22:35:13.15#ibcon#about to read 3, iclass 14, count 0 2006.257.22:35:13.17#ibcon#read 3, iclass 14, count 0 2006.257.22:35:13.17#ibcon#about to read 4, iclass 14, count 0 2006.257.22:35:13.17#ibcon#read 4, iclass 14, count 0 2006.257.22:35:13.17#ibcon#about to read 5, iclass 14, count 0 2006.257.22:35:13.17#ibcon#read 5, iclass 14, count 0 2006.257.22:35:13.17#ibcon#about to read 6, iclass 14, count 0 2006.257.22:35:13.17#ibcon#read 6, iclass 14, count 0 2006.257.22:35:13.17#ibcon#end of sib2, iclass 14, count 0 2006.257.22:35:13.17#ibcon#*mode == 0, iclass 14, count 0 2006.257.22:35:13.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.22:35:13.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.22:35:13.17#ibcon#*before write, iclass 14, count 0 2006.257.22:35:13.17#ibcon#enter sib2, iclass 14, count 0 2006.257.22:35:13.17#ibcon#flushed, iclass 14, count 0 2006.257.22:35:13.17#ibcon#about to write, iclass 14, count 0 2006.257.22:35:13.17#ibcon#wrote, iclass 14, count 0 2006.257.22:35:13.17#ibcon#about to read 3, iclass 14, count 0 2006.257.22:35:13.21#ibcon#read 3, iclass 14, count 0 2006.257.22:35:13.21#ibcon#about to read 4, iclass 14, count 0 2006.257.22:35:13.21#ibcon#read 4, iclass 14, count 0 2006.257.22:35:13.21#ibcon#about to read 5, iclass 14, count 0 2006.257.22:35:13.21#ibcon#read 5, iclass 14, count 0 2006.257.22:35:13.21#ibcon#about to read 6, iclass 14, count 0 2006.257.22:35:13.21#ibcon#read 6, iclass 14, count 0 2006.257.22:35:13.21#ibcon#end of sib2, iclass 14, count 0 2006.257.22:35:13.21#ibcon#*after write, iclass 14, count 0 2006.257.22:35:13.21#ibcon#*before return 0, iclass 14, count 0 2006.257.22:35:13.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:13.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.22:35:13.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.22:35:13.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.22:35:13.21$vck44/vb=7,4 2006.257.22:35:13.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.22:35:13.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.22:35:13.21#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:13.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:13.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:13.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:13.27#ibcon#enter wrdev, iclass 16, count 2 2006.257.22:35:13.27#ibcon#first serial, iclass 16, count 2 2006.257.22:35:13.27#ibcon#enter sib2, iclass 16, count 2 2006.257.22:35:13.27#ibcon#flushed, iclass 16, count 2 2006.257.22:35:13.27#ibcon#about to write, iclass 16, count 2 2006.257.22:35:13.27#ibcon#wrote, iclass 16, count 2 2006.257.22:35:13.27#ibcon#about to read 3, iclass 16, count 2 2006.257.22:35:13.29#ibcon#read 3, iclass 16, count 2 2006.257.22:35:13.29#ibcon#about to read 4, iclass 16, count 2 2006.257.22:35:13.29#ibcon#read 4, iclass 16, count 2 2006.257.22:35:13.29#ibcon#about to read 5, iclass 16, count 2 2006.257.22:35:13.29#ibcon#read 5, iclass 16, count 2 2006.257.22:35:13.29#ibcon#about to read 6, iclass 16, count 2 2006.257.22:35:13.29#ibcon#read 6, iclass 16, count 2 2006.257.22:35:13.29#ibcon#end of sib2, iclass 16, count 2 2006.257.22:35:13.29#ibcon#*mode == 0, iclass 16, count 2 2006.257.22:35:13.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.22:35:13.29#ibcon#[27=AT07-04\r\n] 2006.257.22:35:13.29#ibcon#*before write, iclass 16, count 2 2006.257.22:35:13.29#ibcon#enter sib2, iclass 16, count 2 2006.257.22:35:13.29#ibcon#flushed, iclass 16, count 2 2006.257.22:35:13.29#ibcon#about to write, iclass 16, count 2 2006.257.22:35:13.29#ibcon#wrote, iclass 16, count 2 2006.257.22:35:13.29#ibcon#about to read 3, iclass 16, count 2 2006.257.22:35:13.32#ibcon#read 3, iclass 16, count 2 2006.257.22:35:13.32#ibcon#about to read 4, iclass 16, count 2 2006.257.22:35:13.32#ibcon#read 4, iclass 16, count 2 2006.257.22:35:13.32#ibcon#about to read 5, iclass 16, count 2 2006.257.22:35:13.32#ibcon#read 5, iclass 16, count 2 2006.257.22:35:13.32#ibcon#about to read 6, iclass 16, count 2 2006.257.22:35:13.32#ibcon#read 6, iclass 16, count 2 2006.257.22:35:13.32#ibcon#end of sib2, iclass 16, count 2 2006.257.22:35:13.32#ibcon#*after write, iclass 16, count 2 2006.257.22:35:13.32#ibcon#*before return 0, iclass 16, count 2 2006.257.22:35:13.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:13.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.22:35:13.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.22:35:13.32#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:13.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:13.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:13.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:13.44#ibcon#enter wrdev, iclass 16, count 0 2006.257.22:35:13.44#ibcon#first serial, iclass 16, count 0 2006.257.22:35:13.44#ibcon#enter sib2, iclass 16, count 0 2006.257.22:35:13.44#ibcon#flushed, iclass 16, count 0 2006.257.22:35:13.44#ibcon#about to write, iclass 16, count 0 2006.257.22:35:13.44#ibcon#wrote, iclass 16, count 0 2006.257.22:35:13.44#ibcon#about to read 3, iclass 16, count 0 2006.257.22:35:13.46#ibcon#read 3, iclass 16, count 0 2006.257.22:35:13.46#ibcon#about to read 4, iclass 16, count 0 2006.257.22:35:13.46#ibcon#read 4, iclass 16, count 0 2006.257.22:35:13.46#ibcon#about to read 5, iclass 16, count 0 2006.257.22:35:13.46#ibcon#read 5, iclass 16, count 0 2006.257.22:35:13.46#ibcon#about to read 6, iclass 16, count 0 2006.257.22:35:13.46#ibcon#read 6, iclass 16, count 0 2006.257.22:35:13.46#ibcon#end of sib2, iclass 16, count 0 2006.257.22:35:13.46#ibcon#*mode == 0, iclass 16, count 0 2006.257.22:35:13.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.22:35:13.46#ibcon#[27=USB\r\n] 2006.257.22:35:13.46#ibcon#*before write, iclass 16, count 0 2006.257.22:35:13.46#ibcon#enter sib2, iclass 16, count 0 2006.257.22:35:13.46#ibcon#flushed, iclass 16, count 0 2006.257.22:35:13.46#ibcon#about to write, iclass 16, count 0 2006.257.22:35:13.46#ibcon#wrote, iclass 16, count 0 2006.257.22:35:13.46#ibcon#about to read 3, iclass 16, count 0 2006.257.22:35:13.49#ibcon#read 3, iclass 16, count 0 2006.257.22:35:13.49#ibcon#about to read 4, iclass 16, count 0 2006.257.22:35:13.49#ibcon#read 4, iclass 16, count 0 2006.257.22:35:13.49#ibcon#about to read 5, iclass 16, count 0 2006.257.22:35:13.49#ibcon#read 5, iclass 16, count 0 2006.257.22:35:13.49#ibcon#about to read 6, iclass 16, count 0 2006.257.22:35:13.49#ibcon#read 6, iclass 16, count 0 2006.257.22:35:13.49#ibcon#end of sib2, iclass 16, count 0 2006.257.22:35:13.49#ibcon#*after write, iclass 16, count 0 2006.257.22:35:13.49#ibcon#*before return 0, iclass 16, count 0 2006.257.22:35:13.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:13.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.22:35:13.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.22:35:13.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.22:35:13.49$vck44/vblo=8,744.99 2006.257.22:35:13.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.22:35:13.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.22:35:13.49#ibcon#ireg 17 cls_cnt 0 2006.257.22:35:13.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:13.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:13.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:13.49#ibcon#enter wrdev, iclass 18, count 0 2006.257.22:35:13.49#ibcon#first serial, iclass 18, count 0 2006.257.22:35:13.49#ibcon#enter sib2, iclass 18, count 0 2006.257.22:35:13.49#ibcon#flushed, iclass 18, count 0 2006.257.22:35:13.49#ibcon#about to write, iclass 18, count 0 2006.257.22:35:13.49#ibcon#wrote, iclass 18, count 0 2006.257.22:35:13.49#ibcon#about to read 3, iclass 18, count 0 2006.257.22:35:13.51#ibcon#read 3, iclass 18, count 0 2006.257.22:35:13.51#ibcon#about to read 4, iclass 18, count 0 2006.257.22:35:13.51#ibcon#read 4, iclass 18, count 0 2006.257.22:35:13.51#ibcon#about to read 5, iclass 18, count 0 2006.257.22:35:13.51#ibcon#read 5, iclass 18, count 0 2006.257.22:35:13.51#ibcon#about to read 6, iclass 18, count 0 2006.257.22:35:13.51#ibcon#read 6, iclass 18, count 0 2006.257.22:35:13.51#ibcon#end of sib2, iclass 18, count 0 2006.257.22:35:13.51#ibcon#*mode == 0, iclass 18, count 0 2006.257.22:35:13.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.22:35:13.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.22:35:13.51#ibcon#*before write, iclass 18, count 0 2006.257.22:35:13.51#ibcon#enter sib2, iclass 18, count 0 2006.257.22:35:13.51#ibcon#flushed, iclass 18, count 0 2006.257.22:35:13.51#ibcon#about to write, iclass 18, count 0 2006.257.22:35:13.51#ibcon#wrote, iclass 18, count 0 2006.257.22:35:13.51#ibcon#about to read 3, iclass 18, count 0 2006.257.22:35:13.55#ibcon#read 3, iclass 18, count 0 2006.257.22:35:13.55#ibcon#about to read 4, iclass 18, count 0 2006.257.22:35:13.55#ibcon#read 4, iclass 18, count 0 2006.257.22:35:13.55#ibcon#about to read 5, iclass 18, count 0 2006.257.22:35:13.55#ibcon#read 5, iclass 18, count 0 2006.257.22:35:13.55#ibcon#about to read 6, iclass 18, count 0 2006.257.22:35:13.55#ibcon#read 6, iclass 18, count 0 2006.257.22:35:13.55#ibcon#end of sib2, iclass 18, count 0 2006.257.22:35:13.55#ibcon#*after write, iclass 18, count 0 2006.257.22:35:13.55#ibcon#*before return 0, iclass 18, count 0 2006.257.22:35:13.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:13.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.22:35:13.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.22:35:13.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.22:35:13.55$vck44/vb=8,4 2006.257.22:35:13.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.22:35:13.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.22:35:13.55#ibcon#ireg 11 cls_cnt 2 2006.257.22:35:13.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:13.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:13.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:13.61#ibcon#enter wrdev, iclass 20, count 2 2006.257.22:35:13.61#ibcon#first serial, iclass 20, count 2 2006.257.22:35:13.61#ibcon#enter sib2, iclass 20, count 2 2006.257.22:35:13.61#ibcon#flushed, iclass 20, count 2 2006.257.22:35:13.61#ibcon#about to write, iclass 20, count 2 2006.257.22:35:13.61#ibcon#wrote, iclass 20, count 2 2006.257.22:35:13.61#ibcon#about to read 3, iclass 20, count 2 2006.257.22:35:13.63#ibcon#read 3, iclass 20, count 2 2006.257.22:35:13.63#ibcon#about to read 4, iclass 20, count 2 2006.257.22:35:13.63#ibcon#read 4, iclass 20, count 2 2006.257.22:35:13.63#ibcon#about to read 5, iclass 20, count 2 2006.257.22:35:13.63#ibcon#read 5, iclass 20, count 2 2006.257.22:35:13.63#ibcon#about to read 6, iclass 20, count 2 2006.257.22:35:13.63#ibcon#read 6, iclass 20, count 2 2006.257.22:35:13.63#ibcon#end of sib2, iclass 20, count 2 2006.257.22:35:13.63#ibcon#*mode == 0, iclass 20, count 2 2006.257.22:35:13.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.22:35:13.63#ibcon#[27=AT08-04\r\n] 2006.257.22:35:13.63#ibcon#*before write, iclass 20, count 2 2006.257.22:35:13.63#ibcon#enter sib2, iclass 20, count 2 2006.257.22:35:13.63#ibcon#flushed, iclass 20, count 2 2006.257.22:35:13.63#ibcon#about to write, iclass 20, count 2 2006.257.22:35:13.63#ibcon#wrote, iclass 20, count 2 2006.257.22:35:13.63#ibcon#about to read 3, iclass 20, count 2 2006.257.22:35:13.66#ibcon#read 3, iclass 20, count 2 2006.257.22:35:13.66#ibcon#about to read 4, iclass 20, count 2 2006.257.22:35:13.66#ibcon#read 4, iclass 20, count 2 2006.257.22:35:13.66#ibcon#about to read 5, iclass 20, count 2 2006.257.22:35:13.66#ibcon#read 5, iclass 20, count 2 2006.257.22:35:13.66#ibcon#about to read 6, iclass 20, count 2 2006.257.22:35:13.66#ibcon#read 6, iclass 20, count 2 2006.257.22:35:13.66#ibcon#end of sib2, iclass 20, count 2 2006.257.22:35:13.66#ibcon#*after write, iclass 20, count 2 2006.257.22:35:13.66#ibcon#*before return 0, iclass 20, count 2 2006.257.22:35:13.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:13.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.22:35:13.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.22:35:13.66#ibcon#ireg 7 cls_cnt 0 2006.257.22:35:13.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:13.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:13.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:13.78#ibcon#enter wrdev, iclass 20, count 0 2006.257.22:35:13.78#ibcon#first serial, iclass 20, count 0 2006.257.22:35:13.78#ibcon#enter sib2, iclass 20, count 0 2006.257.22:35:13.78#ibcon#flushed, iclass 20, count 0 2006.257.22:35:13.78#ibcon#about to write, iclass 20, count 0 2006.257.22:35:13.78#ibcon#wrote, iclass 20, count 0 2006.257.22:35:13.78#ibcon#about to read 3, iclass 20, count 0 2006.257.22:35:13.80#ibcon#read 3, iclass 20, count 0 2006.257.22:35:13.80#ibcon#about to read 4, iclass 20, count 0 2006.257.22:35:13.80#ibcon#read 4, iclass 20, count 0 2006.257.22:35:13.80#ibcon#about to read 5, iclass 20, count 0 2006.257.22:35:13.80#ibcon#read 5, iclass 20, count 0 2006.257.22:35:13.80#ibcon#about to read 6, iclass 20, count 0 2006.257.22:35:13.80#ibcon#read 6, iclass 20, count 0 2006.257.22:35:13.80#ibcon#end of sib2, iclass 20, count 0 2006.257.22:35:13.80#ibcon#*mode == 0, iclass 20, count 0 2006.257.22:35:13.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.22:35:13.80#ibcon#[27=USB\r\n] 2006.257.22:35:13.80#ibcon#*before write, iclass 20, count 0 2006.257.22:35:13.80#ibcon#enter sib2, iclass 20, count 0 2006.257.22:35:13.80#ibcon#flushed, iclass 20, count 0 2006.257.22:35:13.80#ibcon#about to write, iclass 20, count 0 2006.257.22:35:13.80#ibcon#wrote, iclass 20, count 0 2006.257.22:35:13.80#ibcon#about to read 3, iclass 20, count 0 2006.257.22:35:13.83#ibcon#read 3, iclass 20, count 0 2006.257.22:35:13.83#ibcon#about to read 4, iclass 20, count 0 2006.257.22:35:13.83#ibcon#read 4, iclass 20, count 0 2006.257.22:35:13.83#ibcon#about to read 5, iclass 20, count 0 2006.257.22:35:13.83#ibcon#read 5, iclass 20, count 0 2006.257.22:35:13.83#ibcon#about to read 6, iclass 20, count 0 2006.257.22:35:13.83#ibcon#read 6, iclass 20, count 0 2006.257.22:35:13.83#ibcon#end of sib2, iclass 20, count 0 2006.257.22:35:13.83#ibcon#*after write, iclass 20, count 0 2006.257.22:35:13.83#ibcon#*before return 0, iclass 20, count 0 2006.257.22:35:13.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:13.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.22:35:13.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.22:35:13.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.22:35:13.83$vck44/vabw=wide 2006.257.22:35:13.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.22:35:13.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.22:35:13.83#ibcon#ireg 8 cls_cnt 0 2006.257.22:35:13.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:13.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:13.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:13.83#ibcon#enter wrdev, iclass 22, count 0 2006.257.22:35:13.83#ibcon#first serial, iclass 22, count 0 2006.257.22:35:13.83#ibcon#enter sib2, iclass 22, count 0 2006.257.22:35:13.83#ibcon#flushed, iclass 22, count 0 2006.257.22:35:13.83#ibcon#about to write, iclass 22, count 0 2006.257.22:35:13.83#ibcon#wrote, iclass 22, count 0 2006.257.22:35:13.83#ibcon#about to read 3, iclass 22, count 0 2006.257.22:35:13.85#ibcon#read 3, iclass 22, count 0 2006.257.22:35:13.85#ibcon#about to read 4, iclass 22, count 0 2006.257.22:35:13.85#ibcon#read 4, iclass 22, count 0 2006.257.22:35:13.85#ibcon#about to read 5, iclass 22, count 0 2006.257.22:35:13.85#ibcon#read 5, iclass 22, count 0 2006.257.22:35:13.85#ibcon#about to read 6, iclass 22, count 0 2006.257.22:35:13.85#ibcon#read 6, iclass 22, count 0 2006.257.22:35:13.85#ibcon#end of sib2, iclass 22, count 0 2006.257.22:35:13.85#ibcon#*mode == 0, iclass 22, count 0 2006.257.22:35:13.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.22:35:13.85#ibcon#[25=BW32\r\n] 2006.257.22:35:13.85#ibcon#*before write, iclass 22, count 0 2006.257.22:35:13.85#ibcon#enter sib2, iclass 22, count 0 2006.257.22:35:13.85#ibcon#flushed, iclass 22, count 0 2006.257.22:35:13.85#ibcon#about to write, iclass 22, count 0 2006.257.22:35:13.85#ibcon#wrote, iclass 22, count 0 2006.257.22:35:13.85#ibcon#about to read 3, iclass 22, count 0 2006.257.22:35:13.88#ibcon#read 3, iclass 22, count 0 2006.257.22:35:13.88#ibcon#about to read 4, iclass 22, count 0 2006.257.22:35:13.88#ibcon#read 4, iclass 22, count 0 2006.257.22:35:13.88#ibcon#about to read 5, iclass 22, count 0 2006.257.22:35:13.88#ibcon#read 5, iclass 22, count 0 2006.257.22:35:13.88#ibcon#about to read 6, iclass 22, count 0 2006.257.22:35:13.88#ibcon#read 6, iclass 22, count 0 2006.257.22:35:13.88#ibcon#end of sib2, iclass 22, count 0 2006.257.22:35:13.88#ibcon#*after write, iclass 22, count 0 2006.257.22:35:13.88#ibcon#*before return 0, iclass 22, count 0 2006.257.22:35:13.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:13.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.22:35:13.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.22:35:13.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.22:35:13.88$vck44/vbbw=wide 2006.257.22:35:13.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.22:35:13.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.22:35:13.88#ibcon#ireg 8 cls_cnt 0 2006.257.22:35:13.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:35:13.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:35:13.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:35:13.95#ibcon#enter wrdev, iclass 24, count 0 2006.257.22:35:13.95#ibcon#first serial, iclass 24, count 0 2006.257.22:35:13.95#ibcon#enter sib2, iclass 24, count 0 2006.257.22:35:13.95#ibcon#flushed, iclass 24, count 0 2006.257.22:35:13.95#ibcon#about to write, iclass 24, count 0 2006.257.22:35:13.95#ibcon#wrote, iclass 24, count 0 2006.257.22:35:13.95#ibcon#about to read 3, iclass 24, count 0 2006.257.22:35:13.97#ibcon#read 3, iclass 24, count 0 2006.257.22:35:13.97#ibcon#about to read 4, iclass 24, count 0 2006.257.22:35:13.97#ibcon#read 4, iclass 24, count 0 2006.257.22:35:13.97#ibcon#about to read 5, iclass 24, count 0 2006.257.22:35:13.97#ibcon#read 5, iclass 24, count 0 2006.257.22:35:13.97#ibcon#about to read 6, iclass 24, count 0 2006.257.22:35:13.97#ibcon#read 6, iclass 24, count 0 2006.257.22:35:13.97#ibcon#end of sib2, iclass 24, count 0 2006.257.22:35:13.97#ibcon#*mode == 0, iclass 24, count 0 2006.257.22:35:13.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.22:35:13.97#ibcon#[27=BW32\r\n] 2006.257.22:35:13.97#ibcon#*before write, iclass 24, count 0 2006.257.22:35:13.97#ibcon#enter sib2, iclass 24, count 0 2006.257.22:35:13.97#ibcon#flushed, iclass 24, count 0 2006.257.22:35:13.97#ibcon#about to write, iclass 24, count 0 2006.257.22:35:13.97#ibcon#wrote, iclass 24, count 0 2006.257.22:35:13.97#ibcon#about to read 3, iclass 24, count 0 2006.257.22:35:14.00#ibcon#read 3, iclass 24, count 0 2006.257.22:35:14.00#ibcon#about to read 4, iclass 24, count 0 2006.257.22:35:14.00#ibcon#read 4, iclass 24, count 0 2006.257.22:35:14.00#ibcon#about to read 5, iclass 24, count 0 2006.257.22:35:14.00#ibcon#read 5, iclass 24, count 0 2006.257.22:35:14.00#ibcon#about to read 6, iclass 24, count 0 2006.257.22:35:14.00#ibcon#read 6, iclass 24, count 0 2006.257.22:35:14.00#ibcon#end of sib2, iclass 24, count 0 2006.257.22:35:14.00#ibcon#*after write, iclass 24, count 0 2006.257.22:35:14.00#ibcon#*before return 0, iclass 24, count 0 2006.257.22:35:14.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:35:14.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:35:14.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.22:35:14.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.22:35:14.00$setupk4/ifdk4 2006.257.22:35:14.00$ifdk4/lo= 2006.257.22:35:14.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.22:35:14.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.22:35:14.00$ifdk4/patch= 2006.257.22:35:14.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.22:35:14.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.22:35:14.00$setupk4/!*+20s 2006.257.22:35:20.12#abcon#<5=/13 0.9 2.6 19.44 861016.0\r\n> 2006.257.22:35:20.14#abcon#{5=INTERFACE CLEAR} 2006.257.22:35:20.20#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:35:28.50$setupk4/"tpicd 2006.257.22:35:28.50$setupk4/echo=off 2006.257.22:35:28.50$setupk4/xlog=off 2006.257.22:35:28.50:!2006.257.22:37:16 2006.257.22:35:30.14#trakl#Source acquired 2006.257.22:35:31.14#flagr#flagr/antenna,acquired 2006.257.22:37:16.00:preob 2006.257.22:37:17.14/onsource/TRACKING 2006.257.22:37:17.14:!2006.257.22:37:26 2006.257.22:37:26.00:"tape 2006.257.22:37:26.00:"st=record 2006.257.22:37:26.00:data_valid=on 2006.257.22:37:26.00:midob 2006.257.22:37:26.14/onsource/TRACKING 2006.257.22:37:26.14/wx/19.48,1016.0,87 2006.257.22:37:26.32/cable/+6.4842E-03 2006.257.22:37:27.41/va/01,08,usb,yes,31,34 2006.257.22:37:27.41/va/02,07,usb,yes,34,35 2006.257.22:37:27.41/va/03,08,usb,yes,30,32 2006.257.22:37:27.41/va/04,07,usb,yes,35,37 2006.257.22:37:27.41/va/05,04,usb,yes,31,32 2006.257.22:37:27.41/va/06,04,usb,yes,35,35 2006.257.22:37:27.41/va/07,04,usb,yes,36,36 2006.257.22:37:27.41/va/08,04,usb,yes,30,37 2006.257.22:37:27.64/valo/01,524.99,yes,locked 2006.257.22:37:27.64/valo/02,534.99,yes,locked 2006.257.22:37:27.64/valo/03,564.99,yes,locked 2006.257.22:37:27.64/valo/04,624.99,yes,locked 2006.257.22:37:27.64/valo/05,734.99,yes,locked 2006.257.22:37:27.64/valo/06,814.99,yes,locked 2006.257.22:37:27.64/valo/07,864.99,yes,locked 2006.257.22:37:27.64/valo/08,884.99,yes,locked 2006.257.22:37:28.73/vb/01,04,usb,yes,31,29 2006.257.22:37:28.73/vb/02,05,usb,yes,29,29 2006.257.22:37:28.73/vb/03,04,usb,yes,30,33 2006.257.22:37:28.73/vb/04,05,usb,yes,30,29 2006.257.22:37:28.73/vb/05,04,usb,yes,27,29 2006.257.22:37:28.73/vb/06,04,usb,yes,31,28 2006.257.22:37:28.73/vb/07,04,usb,yes,31,31 2006.257.22:37:28.73/vb/08,04,usb,yes,28,32 2006.257.22:37:28.96/vblo/01,629.99,yes,locked 2006.257.22:37:28.96/vblo/02,634.99,yes,locked 2006.257.22:37:28.96/vblo/03,649.99,yes,locked 2006.257.22:37:28.96/vblo/04,679.99,yes,locked 2006.257.22:37:28.96/vblo/05,709.99,yes,locked 2006.257.22:37:28.96/vblo/06,719.99,yes,locked 2006.257.22:37:28.96/vblo/07,734.99,yes,locked 2006.257.22:37:28.96/vblo/08,744.99,yes,locked 2006.257.22:37:29.11/vabw/8 2006.257.22:37:29.26/vbbw/8 2006.257.22:37:29.35/xfe/off,on,15.5 2006.257.22:37:29.72/ifatt/23,28,28,28 2006.257.22:37:30.07/fmout-gps/S +4.60E-07 2006.257.22:37:30.11:!2006.257.22:39:26 2006.257.22:39:26.01:data_valid=off 2006.257.22:39:26.01:"et 2006.257.22:39:26.01:!+3s 2006.257.22:39:29.02:"tape 2006.257.22:39:29.02:postob 2006.257.22:39:29.17/cable/+6.4841E-03 2006.257.22:39:29.17/wx/19.51,1016.0,87 2006.257.22:39:29.23/fmout-gps/S +4.59E-07 2006.257.22:39:29.23:scan_name=257-2243,jd0609,420 2006.257.22:39:29.23:source=0804+499,080839.67,495036.5,2000.0,cw 2006.257.22:39:30.14#flagr#flagr/antenna,new-source 2006.257.22:39:30.14:checkk5 2006.257.22:39:30.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.22:39:30.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.22:39:31.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.22:39:31.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.22:39:31.84/chk_obsdata//k5ts1/T2572237??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.22:39:32.17/chk_obsdata//k5ts2/T2572237??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.22:39:32.51/chk_obsdata//k5ts3/T2572237??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.22:39:32.84/chk_obsdata//k5ts4/T2572237??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.257.22:39:33.52/k5log//k5ts1_log_newline 2006.257.22:39:34.19/k5log//k5ts2_log_newline 2006.257.22:39:34.85/k5log//k5ts3_log_newline 2006.257.22:39:35.51/k5log//k5ts4_log_newline 2006.257.22:39:35.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.22:39:35.54:setupk4=1 2006.257.22:39:35.54$setupk4/echo=on 2006.257.22:39:35.54$setupk4/pcalon 2006.257.22:39:35.54$pcalon/"no phase cal control is implemented here 2006.257.22:39:35.54$setupk4/"tpicd=stop 2006.257.22:39:35.54$setupk4/"rec=synch_on 2006.257.22:39:35.54$setupk4/"rec_mode=128 2006.257.22:39:35.54$setupk4/!* 2006.257.22:39:35.54$setupk4/recpk4 2006.257.22:39:35.54$recpk4/recpatch= 2006.257.22:39:35.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.22:39:35.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.22:39:35.55$setupk4/vck44 2006.257.22:39:35.55$vck44/valo=1,524.99 2006.257.22:39:35.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.22:39:35.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.22:39:35.55#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:35.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:35.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:35.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:35.55#ibcon#enter wrdev, iclass 25, count 0 2006.257.22:39:35.55#ibcon#first serial, iclass 25, count 0 2006.257.22:39:35.55#ibcon#enter sib2, iclass 25, count 0 2006.257.22:39:35.55#ibcon#flushed, iclass 25, count 0 2006.257.22:39:35.55#ibcon#about to write, iclass 25, count 0 2006.257.22:39:35.55#ibcon#wrote, iclass 25, count 0 2006.257.22:39:35.55#ibcon#about to read 3, iclass 25, count 0 2006.257.22:39:35.56#ibcon#read 3, iclass 25, count 0 2006.257.22:39:35.56#ibcon#about to read 4, iclass 25, count 0 2006.257.22:39:35.56#ibcon#read 4, iclass 25, count 0 2006.257.22:39:35.56#ibcon#about to read 5, iclass 25, count 0 2006.257.22:39:35.56#ibcon#read 5, iclass 25, count 0 2006.257.22:39:35.56#ibcon#about to read 6, iclass 25, count 0 2006.257.22:39:35.56#ibcon#read 6, iclass 25, count 0 2006.257.22:39:35.56#ibcon#end of sib2, iclass 25, count 0 2006.257.22:39:35.56#ibcon#*mode == 0, iclass 25, count 0 2006.257.22:39:35.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.22:39:35.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.22:39:35.56#ibcon#*before write, iclass 25, count 0 2006.257.22:39:35.56#ibcon#enter sib2, iclass 25, count 0 2006.257.22:39:35.56#ibcon#flushed, iclass 25, count 0 2006.257.22:39:35.56#ibcon#about to write, iclass 25, count 0 2006.257.22:39:35.56#ibcon#wrote, iclass 25, count 0 2006.257.22:39:35.56#ibcon#about to read 3, iclass 25, count 0 2006.257.22:39:35.61#ibcon#read 3, iclass 25, count 0 2006.257.22:39:35.61#ibcon#about to read 4, iclass 25, count 0 2006.257.22:39:35.61#ibcon#read 4, iclass 25, count 0 2006.257.22:39:35.61#ibcon#about to read 5, iclass 25, count 0 2006.257.22:39:35.61#ibcon#read 5, iclass 25, count 0 2006.257.22:39:35.61#ibcon#about to read 6, iclass 25, count 0 2006.257.22:39:35.61#ibcon#read 6, iclass 25, count 0 2006.257.22:39:35.61#ibcon#end of sib2, iclass 25, count 0 2006.257.22:39:35.61#ibcon#*after write, iclass 25, count 0 2006.257.22:39:35.61#ibcon#*before return 0, iclass 25, count 0 2006.257.22:39:35.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:35.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:35.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.22:39:35.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.22:39:35.61$vck44/va=1,8 2006.257.22:39:35.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.22:39:35.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.22:39:35.61#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:35.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:35.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:35.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:35.61#ibcon#enter wrdev, iclass 27, count 2 2006.257.22:39:35.61#ibcon#first serial, iclass 27, count 2 2006.257.22:39:35.61#ibcon#enter sib2, iclass 27, count 2 2006.257.22:39:35.61#ibcon#flushed, iclass 27, count 2 2006.257.22:39:35.61#ibcon#about to write, iclass 27, count 2 2006.257.22:39:35.61#ibcon#wrote, iclass 27, count 2 2006.257.22:39:35.61#ibcon#about to read 3, iclass 27, count 2 2006.257.22:39:35.63#ibcon#read 3, iclass 27, count 2 2006.257.22:39:35.63#ibcon#about to read 4, iclass 27, count 2 2006.257.22:39:35.63#ibcon#read 4, iclass 27, count 2 2006.257.22:39:35.63#ibcon#about to read 5, iclass 27, count 2 2006.257.22:39:35.63#ibcon#read 5, iclass 27, count 2 2006.257.22:39:35.63#ibcon#about to read 6, iclass 27, count 2 2006.257.22:39:35.63#ibcon#read 6, iclass 27, count 2 2006.257.22:39:35.63#ibcon#end of sib2, iclass 27, count 2 2006.257.22:39:35.63#ibcon#*mode == 0, iclass 27, count 2 2006.257.22:39:35.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.22:39:35.63#ibcon#[25=AT01-08\r\n] 2006.257.22:39:35.63#ibcon#*before write, iclass 27, count 2 2006.257.22:39:35.63#ibcon#enter sib2, iclass 27, count 2 2006.257.22:39:35.63#ibcon#flushed, iclass 27, count 2 2006.257.22:39:35.63#ibcon#about to write, iclass 27, count 2 2006.257.22:39:35.63#ibcon#wrote, iclass 27, count 2 2006.257.22:39:35.63#ibcon#about to read 3, iclass 27, count 2 2006.257.22:39:35.66#ibcon#read 3, iclass 27, count 2 2006.257.22:39:35.66#ibcon#about to read 4, iclass 27, count 2 2006.257.22:39:35.66#ibcon#read 4, iclass 27, count 2 2006.257.22:39:35.66#ibcon#about to read 5, iclass 27, count 2 2006.257.22:39:35.66#ibcon#read 5, iclass 27, count 2 2006.257.22:39:35.66#ibcon#about to read 6, iclass 27, count 2 2006.257.22:39:35.66#ibcon#read 6, iclass 27, count 2 2006.257.22:39:35.66#ibcon#end of sib2, iclass 27, count 2 2006.257.22:39:35.66#ibcon#*after write, iclass 27, count 2 2006.257.22:39:35.66#ibcon#*before return 0, iclass 27, count 2 2006.257.22:39:35.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:35.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:35.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.22:39:35.66#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:35.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:35.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:35.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:35.78#ibcon#enter wrdev, iclass 27, count 0 2006.257.22:39:35.78#ibcon#first serial, iclass 27, count 0 2006.257.22:39:35.78#ibcon#enter sib2, iclass 27, count 0 2006.257.22:39:35.78#ibcon#flushed, iclass 27, count 0 2006.257.22:39:35.78#ibcon#about to write, iclass 27, count 0 2006.257.22:39:35.78#ibcon#wrote, iclass 27, count 0 2006.257.22:39:35.78#ibcon#about to read 3, iclass 27, count 0 2006.257.22:39:35.80#ibcon#read 3, iclass 27, count 0 2006.257.22:39:35.80#ibcon#about to read 4, iclass 27, count 0 2006.257.22:39:35.80#ibcon#read 4, iclass 27, count 0 2006.257.22:39:35.80#ibcon#about to read 5, iclass 27, count 0 2006.257.22:39:35.80#ibcon#read 5, iclass 27, count 0 2006.257.22:39:35.80#ibcon#about to read 6, iclass 27, count 0 2006.257.22:39:35.80#ibcon#read 6, iclass 27, count 0 2006.257.22:39:35.80#ibcon#end of sib2, iclass 27, count 0 2006.257.22:39:35.80#ibcon#*mode == 0, iclass 27, count 0 2006.257.22:39:35.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.22:39:35.80#ibcon#[25=USB\r\n] 2006.257.22:39:35.80#ibcon#*before write, iclass 27, count 0 2006.257.22:39:35.80#ibcon#enter sib2, iclass 27, count 0 2006.257.22:39:35.80#ibcon#flushed, iclass 27, count 0 2006.257.22:39:35.80#ibcon#about to write, iclass 27, count 0 2006.257.22:39:35.80#ibcon#wrote, iclass 27, count 0 2006.257.22:39:35.80#ibcon#about to read 3, iclass 27, count 0 2006.257.22:39:35.83#ibcon#read 3, iclass 27, count 0 2006.257.22:39:35.83#ibcon#about to read 4, iclass 27, count 0 2006.257.22:39:35.83#ibcon#read 4, iclass 27, count 0 2006.257.22:39:35.83#ibcon#about to read 5, iclass 27, count 0 2006.257.22:39:35.83#ibcon#read 5, iclass 27, count 0 2006.257.22:39:35.83#ibcon#about to read 6, iclass 27, count 0 2006.257.22:39:35.83#ibcon#read 6, iclass 27, count 0 2006.257.22:39:35.83#ibcon#end of sib2, iclass 27, count 0 2006.257.22:39:35.83#ibcon#*after write, iclass 27, count 0 2006.257.22:39:35.83#ibcon#*before return 0, iclass 27, count 0 2006.257.22:39:35.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:35.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:35.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.22:39:35.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.22:39:35.83$vck44/valo=2,534.99 2006.257.22:39:35.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.22:39:35.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.22:39:35.83#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:35.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:35.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:35.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:35.83#ibcon#enter wrdev, iclass 29, count 0 2006.257.22:39:35.83#ibcon#first serial, iclass 29, count 0 2006.257.22:39:35.83#ibcon#enter sib2, iclass 29, count 0 2006.257.22:39:35.83#ibcon#flushed, iclass 29, count 0 2006.257.22:39:35.83#ibcon#about to write, iclass 29, count 0 2006.257.22:39:35.83#ibcon#wrote, iclass 29, count 0 2006.257.22:39:35.83#ibcon#about to read 3, iclass 29, count 0 2006.257.22:39:35.85#ibcon#read 3, iclass 29, count 0 2006.257.22:39:35.85#ibcon#about to read 4, iclass 29, count 0 2006.257.22:39:35.85#ibcon#read 4, iclass 29, count 0 2006.257.22:39:35.85#ibcon#about to read 5, iclass 29, count 0 2006.257.22:39:35.85#ibcon#read 5, iclass 29, count 0 2006.257.22:39:35.85#ibcon#about to read 6, iclass 29, count 0 2006.257.22:39:35.85#ibcon#read 6, iclass 29, count 0 2006.257.22:39:35.85#ibcon#end of sib2, iclass 29, count 0 2006.257.22:39:35.85#ibcon#*mode == 0, iclass 29, count 0 2006.257.22:39:35.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.22:39:35.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.22:39:35.85#ibcon#*before write, iclass 29, count 0 2006.257.22:39:35.85#ibcon#enter sib2, iclass 29, count 0 2006.257.22:39:35.85#ibcon#flushed, iclass 29, count 0 2006.257.22:39:35.85#ibcon#about to write, iclass 29, count 0 2006.257.22:39:35.85#ibcon#wrote, iclass 29, count 0 2006.257.22:39:35.85#ibcon#about to read 3, iclass 29, count 0 2006.257.22:39:35.89#ibcon#read 3, iclass 29, count 0 2006.257.22:39:35.89#ibcon#about to read 4, iclass 29, count 0 2006.257.22:39:35.89#ibcon#read 4, iclass 29, count 0 2006.257.22:39:35.89#ibcon#about to read 5, iclass 29, count 0 2006.257.22:39:35.89#ibcon#read 5, iclass 29, count 0 2006.257.22:39:35.89#ibcon#about to read 6, iclass 29, count 0 2006.257.22:39:35.89#ibcon#read 6, iclass 29, count 0 2006.257.22:39:35.89#ibcon#end of sib2, iclass 29, count 0 2006.257.22:39:35.89#ibcon#*after write, iclass 29, count 0 2006.257.22:39:35.89#ibcon#*before return 0, iclass 29, count 0 2006.257.22:39:35.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:35.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:35.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.22:39:35.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.22:39:35.89$vck44/va=2,7 2006.257.22:39:35.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.22:39:35.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.22:39:35.89#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:35.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:35.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:35.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:35.95#ibcon#enter wrdev, iclass 31, count 2 2006.257.22:39:35.95#ibcon#first serial, iclass 31, count 2 2006.257.22:39:35.95#ibcon#enter sib2, iclass 31, count 2 2006.257.22:39:35.95#ibcon#flushed, iclass 31, count 2 2006.257.22:39:35.95#ibcon#about to write, iclass 31, count 2 2006.257.22:39:35.95#ibcon#wrote, iclass 31, count 2 2006.257.22:39:35.95#ibcon#about to read 3, iclass 31, count 2 2006.257.22:39:35.97#ibcon#read 3, iclass 31, count 2 2006.257.22:39:35.97#ibcon#about to read 4, iclass 31, count 2 2006.257.22:39:35.97#ibcon#read 4, iclass 31, count 2 2006.257.22:39:35.97#ibcon#about to read 5, iclass 31, count 2 2006.257.22:39:35.97#ibcon#read 5, iclass 31, count 2 2006.257.22:39:35.97#ibcon#about to read 6, iclass 31, count 2 2006.257.22:39:35.97#ibcon#read 6, iclass 31, count 2 2006.257.22:39:35.97#ibcon#end of sib2, iclass 31, count 2 2006.257.22:39:35.97#ibcon#*mode == 0, iclass 31, count 2 2006.257.22:39:35.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.22:39:35.97#ibcon#[25=AT02-07\r\n] 2006.257.22:39:35.97#ibcon#*before write, iclass 31, count 2 2006.257.22:39:35.97#ibcon#enter sib2, iclass 31, count 2 2006.257.22:39:35.97#ibcon#flushed, iclass 31, count 2 2006.257.22:39:35.97#ibcon#about to write, iclass 31, count 2 2006.257.22:39:35.97#ibcon#wrote, iclass 31, count 2 2006.257.22:39:35.97#ibcon#about to read 3, iclass 31, count 2 2006.257.22:39:36.00#ibcon#read 3, iclass 31, count 2 2006.257.22:39:36.00#ibcon#about to read 4, iclass 31, count 2 2006.257.22:39:36.00#ibcon#read 4, iclass 31, count 2 2006.257.22:39:36.00#ibcon#about to read 5, iclass 31, count 2 2006.257.22:39:36.00#ibcon#read 5, iclass 31, count 2 2006.257.22:39:36.00#ibcon#about to read 6, iclass 31, count 2 2006.257.22:39:36.00#ibcon#read 6, iclass 31, count 2 2006.257.22:39:36.00#ibcon#end of sib2, iclass 31, count 2 2006.257.22:39:36.00#ibcon#*after write, iclass 31, count 2 2006.257.22:39:36.00#ibcon#*before return 0, iclass 31, count 2 2006.257.22:39:36.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:36.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:36.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.22:39:36.00#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:36.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:36.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:36.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:36.12#ibcon#enter wrdev, iclass 31, count 0 2006.257.22:39:36.12#ibcon#first serial, iclass 31, count 0 2006.257.22:39:36.12#ibcon#enter sib2, iclass 31, count 0 2006.257.22:39:36.12#ibcon#flushed, iclass 31, count 0 2006.257.22:39:36.12#ibcon#about to write, iclass 31, count 0 2006.257.22:39:36.12#ibcon#wrote, iclass 31, count 0 2006.257.22:39:36.12#ibcon#about to read 3, iclass 31, count 0 2006.257.22:39:36.14#ibcon#read 3, iclass 31, count 0 2006.257.22:39:36.14#ibcon#about to read 4, iclass 31, count 0 2006.257.22:39:36.14#ibcon#read 4, iclass 31, count 0 2006.257.22:39:36.14#ibcon#about to read 5, iclass 31, count 0 2006.257.22:39:36.14#ibcon#read 5, iclass 31, count 0 2006.257.22:39:36.14#ibcon#about to read 6, iclass 31, count 0 2006.257.22:39:36.14#ibcon#read 6, iclass 31, count 0 2006.257.22:39:36.14#ibcon#end of sib2, iclass 31, count 0 2006.257.22:39:36.14#ibcon#*mode == 0, iclass 31, count 0 2006.257.22:39:36.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.22:39:36.14#ibcon#[25=USB\r\n] 2006.257.22:39:36.14#ibcon#*before write, iclass 31, count 0 2006.257.22:39:36.14#ibcon#enter sib2, iclass 31, count 0 2006.257.22:39:36.14#ibcon#flushed, iclass 31, count 0 2006.257.22:39:36.14#ibcon#about to write, iclass 31, count 0 2006.257.22:39:36.14#ibcon#wrote, iclass 31, count 0 2006.257.22:39:36.14#ibcon#about to read 3, iclass 31, count 0 2006.257.22:39:36.17#ibcon#read 3, iclass 31, count 0 2006.257.22:39:36.17#ibcon#about to read 4, iclass 31, count 0 2006.257.22:39:36.17#ibcon#read 4, iclass 31, count 0 2006.257.22:39:36.17#ibcon#about to read 5, iclass 31, count 0 2006.257.22:39:36.17#ibcon#read 5, iclass 31, count 0 2006.257.22:39:36.17#ibcon#about to read 6, iclass 31, count 0 2006.257.22:39:36.17#ibcon#read 6, iclass 31, count 0 2006.257.22:39:36.17#ibcon#end of sib2, iclass 31, count 0 2006.257.22:39:36.17#ibcon#*after write, iclass 31, count 0 2006.257.22:39:36.17#ibcon#*before return 0, iclass 31, count 0 2006.257.22:39:36.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:36.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:36.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.22:39:36.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.22:39:36.17$vck44/valo=3,564.99 2006.257.22:39:36.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.22:39:36.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.22:39:36.17#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:36.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:36.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:36.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:36.17#ibcon#enter wrdev, iclass 33, count 0 2006.257.22:39:36.17#ibcon#first serial, iclass 33, count 0 2006.257.22:39:36.17#ibcon#enter sib2, iclass 33, count 0 2006.257.22:39:36.17#ibcon#flushed, iclass 33, count 0 2006.257.22:39:36.17#ibcon#about to write, iclass 33, count 0 2006.257.22:39:36.17#ibcon#wrote, iclass 33, count 0 2006.257.22:39:36.17#ibcon#about to read 3, iclass 33, count 0 2006.257.22:39:36.19#ibcon#read 3, iclass 33, count 0 2006.257.22:39:36.19#ibcon#about to read 4, iclass 33, count 0 2006.257.22:39:36.19#ibcon#read 4, iclass 33, count 0 2006.257.22:39:36.19#ibcon#about to read 5, iclass 33, count 0 2006.257.22:39:36.19#ibcon#read 5, iclass 33, count 0 2006.257.22:39:36.19#ibcon#about to read 6, iclass 33, count 0 2006.257.22:39:36.19#ibcon#read 6, iclass 33, count 0 2006.257.22:39:36.19#ibcon#end of sib2, iclass 33, count 0 2006.257.22:39:36.19#ibcon#*mode == 0, iclass 33, count 0 2006.257.22:39:36.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.22:39:36.19#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.22:39:36.19#ibcon#*before write, iclass 33, count 0 2006.257.22:39:36.19#ibcon#enter sib2, iclass 33, count 0 2006.257.22:39:36.19#ibcon#flushed, iclass 33, count 0 2006.257.22:39:36.19#ibcon#about to write, iclass 33, count 0 2006.257.22:39:36.19#ibcon#wrote, iclass 33, count 0 2006.257.22:39:36.19#ibcon#about to read 3, iclass 33, count 0 2006.257.22:39:36.23#ibcon#read 3, iclass 33, count 0 2006.257.22:39:36.23#ibcon#about to read 4, iclass 33, count 0 2006.257.22:39:36.23#ibcon#read 4, iclass 33, count 0 2006.257.22:39:36.23#ibcon#about to read 5, iclass 33, count 0 2006.257.22:39:36.23#ibcon#read 5, iclass 33, count 0 2006.257.22:39:36.23#ibcon#about to read 6, iclass 33, count 0 2006.257.22:39:36.23#ibcon#read 6, iclass 33, count 0 2006.257.22:39:36.23#ibcon#end of sib2, iclass 33, count 0 2006.257.22:39:36.23#ibcon#*after write, iclass 33, count 0 2006.257.22:39:36.23#ibcon#*before return 0, iclass 33, count 0 2006.257.22:39:36.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:36.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:36.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.22:39:36.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.22:39:36.23$vck44/va=3,8 2006.257.22:39:36.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.22:39:36.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.22:39:36.23#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:36.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:36.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:36.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:36.29#ibcon#enter wrdev, iclass 35, count 2 2006.257.22:39:36.29#ibcon#first serial, iclass 35, count 2 2006.257.22:39:36.29#ibcon#enter sib2, iclass 35, count 2 2006.257.22:39:36.29#ibcon#flushed, iclass 35, count 2 2006.257.22:39:36.29#ibcon#about to write, iclass 35, count 2 2006.257.22:39:36.29#ibcon#wrote, iclass 35, count 2 2006.257.22:39:36.29#ibcon#about to read 3, iclass 35, count 2 2006.257.22:39:36.31#ibcon#read 3, iclass 35, count 2 2006.257.22:39:36.31#ibcon#about to read 4, iclass 35, count 2 2006.257.22:39:36.31#ibcon#read 4, iclass 35, count 2 2006.257.22:39:36.31#ibcon#about to read 5, iclass 35, count 2 2006.257.22:39:36.31#ibcon#read 5, iclass 35, count 2 2006.257.22:39:36.31#ibcon#about to read 6, iclass 35, count 2 2006.257.22:39:36.31#ibcon#read 6, iclass 35, count 2 2006.257.22:39:36.31#ibcon#end of sib2, iclass 35, count 2 2006.257.22:39:36.31#ibcon#*mode == 0, iclass 35, count 2 2006.257.22:39:36.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.22:39:36.31#ibcon#[25=AT03-08\r\n] 2006.257.22:39:36.31#ibcon#*before write, iclass 35, count 2 2006.257.22:39:36.31#ibcon#enter sib2, iclass 35, count 2 2006.257.22:39:36.31#ibcon#flushed, iclass 35, count 2 2006.257.22:39:36.31#ibcon#about to write, iclass 35, count 2 2006.257.22:39:36.31#ibcon#wrote, iclass 35, count 2 2006.257.22:39:36.31#ibcon#about to read 3, iclass 35, count 2 2006.257.22:39:36.34#ibcon#read 3, iclass 35, count 2 2006.257.22:39:36.34#ibcon#about to read 4, iclass 35, count 2 2006.257.22:39:36.34#ibcon#read 4, iclass 35, count 2 2006.257.22:39:36.34#ibcon#about to read 5, iclass 35, count 2 2006.257.22:39:36.34#ibcon#read 5, iclass 35, count 2 2006.257.22:39:36.34#ibcon#about to read 6, iclass 35, count 2 2006.257.22:39:36.34#ibcon#read 6, iclass 35, count 2 2006.257.22:39:36.34#ibcon#end of sib2, iclass 35, count 2 2006.257.22:39:36.34#ibcon#*after write, iclass 35, count 2 2006.257.22:39:36.34#ibcon#*before return 0, iclass 35, count 2 2006.257.22:39:36.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:36.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:36.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.22:39:36.34#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:36.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:36.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:36.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:36.46#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:39:36.46#ibcon#first serial, iclass 35, count 0 2006.257.22:39:36.46#ibcon#enter sib2, iclass 35, count 0 2006.257.22:39:36.46#ibcon#flushed, iclass 35, count 0 2006.257.22:39:36.46#ibcon#about to write, iclass 35, count 0 2006.257.22:39:36.46#ibcon#wrote, iclass 35, count 0 2006.257.22:39:36.46#ibcon#about to read 3, iclass 35, count 0 2006.257.22:39:36.48#ibcon#read 3, iclass 35, count 0 2006.257.22:39:36.48#ibcon#about to read 4, iclass 35, count 0 2006.257.22:39:36.48#ibcon#read 4, iclass 35, count 0 2006.257.22:39:36.48#ibcon#about to read 5, iclass 35, count 0 2006.257.22:39:36.48#ibcon#read 5, iclass 35, count 0 2006.257.22:39:36.48#ibcon#about to read 6, iclass 35, count 0 2006.257.22:39:36.48#ibcon#read 6, iclass 35, count 0 2006.257.22:39:36.48#ibcon#end of sib2, iclass 35, count 0 2006.257.22:39:36.48#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:39:36.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:39:36.48#ibcon#[25=USB\r\n] 2006.257.22:39:36.48#ibcon#*before write, iclass 35, count 0 2006.257.22:39:36.48#ibcon#enter sib2, iclass 35, count 0 2006.257.22:39:36.48#ibcon#flushed, iclass 35, count 0 2006.257.22:39:36.48#ibcon#about to write, iclass 35, count 0 2006.257.22:39:36.48#ibcon#wrote, iclass 35, count 0 2006.257.22:39:36.48#ibcon#about to read 3, iclass 35, count 0 2006.257.22:39:36.51#ibcon#read 3, iclass 35, count 0 2006.257.22:39:36.51#ibcon#about to read 4, iclass 35, count 0 2006.257.22:39:36.51#ibcon#read 4, iclass 35, count 0 2006.257.22:39:36.51#ibcon#about to read 5, iclass 35, count 0 2006.257.22:39:36.51#ibcon#read 5, iclass 35, count 0 2006.257.22:39:36.51#ibcon#about to read 6, iclass 35, count 0 2006.257.22:39:36.51#ibcon#read 6, iclass 35, count 0 2006.257.22:39:36.51#ibcon#end of sib2, iclass 35, count 0 2006.257.22:39:36.51#ibcon#*after write, iclass 35, count 0 2006.257.22:39:36.51#ibcon#*before return 0, iclass 35, count 0 2006.257.22:39:36.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:36.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:36.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:39:36.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:39:36.51$vck44/valo=4,624.99 2006.257.22:39:36.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.22:39:36.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.22:39:36.51#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:36.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:36.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:36.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:36.51#ibcon#enter wrdev, iclass 37, count 0 2006.257.22:39:36.51#ibcon#first serial, iclass 37, count 0 2006.257.22:39:36.51#ibcon#enter sib2, iclass 37, count 0 2006.257.22:39:36.51#ibcon#flushed, iclass 37, count 0 2006.257.22:39:36.51#ibcon#about to write, iclass 37, count 0 2006.257.22:39:36.51#ibcon#wrote, iclass 37, count 0 2006.257.22:39:36.51#ibcon#about to read 3, iclass 37, count 0 2006.257.22:39:36.53#ibcon#read 3, iclass 37, count 0 2006.257.22:39:36.53#ibcon#about to read 4, iclass 37, count 0 2006.257.22:39:36.53#ibcon#read 4, iclass 37, count 0 2006.257.22:39:36.53#ibcon#about to read 5, iclass 37, count 0 2006.257.22:39:36.53#ibcon#read 5, iclass 37, count 0 2006.257.22:39:36.53#ibcon#about to read 6, iclass 37, count 0 2006.257.22:39:36.53#ibcon#read 6, iclass 37, count 0 2006.257.22:39:36.53#ibcon#end of sib2, iclass 37, count 0 2006.257.22:39:36.53#ibcon#*mode == 0, iclass 37, count 0 2006.257.22:39:36.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.22:39:36.53#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.22:39:36.53#ibcon#*before write, iclass 37, count 0 2006.257.22:39:36.53#ibcon#enter sib2, iclass 37, count 0 2006.257.22:39:36.53#ibcon#flushed, iclass 37, count 0 2006.257.22:39:36.53#ibcon#about to write, iclass 37, count 0 2006.257.22:39:36.53#ibcon#wrote, iclass 37, count 0 2006.257.22:39:36.53#ibcon#about to read 3, iclass 37, count 0 2006.257.22:39:36.57#ibcon#read 3, iclass 37, count 0 2006.257.22:39:36.57#ibcon#about to read 4, iclass 37, count 0 2006.257.22:39:36.57#ibcon#read 4, iclass 37, count 0 2006.257.22:39:36.57#ibcon#about to read 5, iclass 37, count 0 2006.257.22:39:36.57#ibcon#read 5, iclass 37, count 0 2006.257.22:39:36.57#ibcon#about to read 6, iclass 37, count 0 2006.257.22:39:36.57#ibcon#read 6, iclass 37, count 0 2006.257.22:39:36.57#ibcon#end of sib2, iclass 37, count 0 2006.257.22:39:36.57#ibcon#*after write, iclass 37, count 0 2006.257.22:39:36.57#ibcon#*before return 0, iclass 37, count 0 2006.257.22:39:36.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:36.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:36.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.22:39:36.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.22:39:36.57$vck44/va=4,7 2006.257.22:39:36.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.22:39:36.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.22:39:36.57#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:36.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:36.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:36.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:36.63#ibcon#enter wrdev, iclass 39, count 2 2006.257.22:39:36.63#ibcon#first serial, iclass 39, count 2 2006.257.22:39:36.63#ibcon#enter sib2, iclass 39, count 2 2006.257.22:39:36.63#ibcon#flushed, iclass 39, count 2 2006.257.22:39:36.63#ibcon#about to write, iclass 39, count 2 2006.257.22:39:36.63#ibcon#wrote, iclass 39, count 2 2006.257.22:39:36.63#ibcon#about to read 3, iclass 39, count 2 2006.257.22:39:36.65#ibcon#read 3, iclass 39, count 2 2006.257.22:39:36.65#ibcon#about to read 4, iclass 39, count 2 2006.257.22:39:36.65#ibcon#read 4, iclass 39, count 2 2006.257.22:39:36.65#ibcon#about to read 5, iclass 39, count 2 2006.257.22:39:36.65#ibcon#read 5, iclass 39, count 2 2006.257.22:39:36.65#ibcon#about to read 6, iclass 39, count 2 2006.257.22:39:36.65#ibcon#read 6, iclass 39, count 2 2006.257.22:39:36.65#ibcon#end of sib2, iclass 39, count 2 2006.257.22:39:36.65#ibcon#*mode == 0, iclass 39, count 2 2006.257.22:39:36.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.22:39:36.65#ibcon#[25=AT04-07\r\n] 2006.257.22:39:36.65#ibcon#*before write, iclass 39, count 2 2006.257.22:39:36.65#ibcon#enter sib2, iclass 39, count 2 2006.257.22:39:36.65#ibcon#flushed, iclass 39, count 2 2006.257.22:39:36.65#ibcon#about to write, iclass 39, count 2 2006.257.22:39:36.65#ibcon#wrote, iclass 39, count 2 2006.257.22:39:36.65#ibcon#about to read 3, iclass 39, count 2 2006.257.22:39:36.68#ibcon#read 3, iclass 39, count 2 2006.257.22:39:36.68#ibcon#about to read 4, iclass 39, count 2 2006.257.22:39:36.68#ibcon#read 4, iclass 39, count 2 2006.257.22:39:36.68#ibcon#about to read 5, iclass 39, count 2 2006.257.22:39:36.68#ibcon#read 5, iclass 39, count 2 2006.257.22:39:36.68#ibcon#about to read 6, iclass 39, count 2 2006.257.22:39:36.68#ibcon#read 6, iclass 39, count 2 2006.257.22:39:36.68#ibcon#end of sib2, iclass 39, count 2 2006.257.22:39:36.68#ibcon#*after write, iclass 39, count 2 2006.257.22:39:36.68#ibcon#*before return 0, iclass 39, count 2 2006.257.22:39:36.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:36.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:36.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.22:39:36.68#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:36.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:36.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:36.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:36.80#ibcon#enter wrdev, iclass 39, count 0 2006.257.22:39:36.80#ibcon#first serial, iclass 39, count 0 2006.257.22:39:36.80#ibcon#enter sib2, iclass 39, count 0 2006.257.22:39:36.80#ibcon#flushed, iclass 39, count 0 2006.257.22:39:36.80#ibcon#about to write, iclass 39, count 0 2006.257.22:39:36.80#ibcon#wrote, iclass 39, count 0 2006.257.22:39:36.80#ibcon#about to read 3, iclass 39, count 0 2006.257.22:39:36.82#ibcon#read 3, iclass 39, count 0 2006.257.22:39:36.82#ibcon#about to read 4, iclass 39, count 0 2006.257.22:39:36.82#ibcon#read 4, iclass 39, count 0 2006.257.22:39:36.82#ibcon#about to read 5, iclass 39, count 0 2006.257.22:39:36.82#ibcon#read 5, iclass 39, count 0 2006.257.22:39:36.82#ibcon#about to read 6, iclass 39, count 0 2006.257.22:39:36.82#ibcon#read 6, iclass 39, count 0 2006.257.22:39:36.82#ibcon#end of sib2, iclass 39, count 0 2006.257.22:39:36.82#ibcon#*mode == 0, iclass 39, count 0 2006.257.22:39:36.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.22:39:36.82#ibcon#[25=USB\r\n] 2006.257.22:39:36.82#ibcon#*before write, iclass 39, count 0 2006.257.22:39:36.82#ibcon#enter sib2, iclass 39, count 0 2006.257.22:39:36.82#ibcon#flushed, iclass 39, count 0 2006.257.22:39:36.82#ibcon#about to write, iclass 39, count 0 2006.257.22:39:36.82#ibcon#wrote, iclass 39, count 0 2006.257.22:39:36.82#ibcon#about to read 3, iclass 39, count 0 2006.257.22:39:36.85#ibcon#read 3, iclass 39, count 0 2006.257.22:39:36.85#ibcon#about to read 4, iclass 39, count 0 2006.257.22:39:36.85#ibcon#read 4, iclass 39, count 0 2006.257.22:39:36.85#ibcon#about to read 5, iclass 39, count 0 2006.257.22:39:36.85#ibcon#read 5, iclass 39, count 0 2006.257.22:39:36.85#ibcon#about to read 6, iclass 39, count 0 2006.257.22:39:36.85#ibcon#read 6, iclass 39, count 0 2006.257.22:39:36.85#ibcon#end of sib2, iclass 39, count 0 2006.257.22:39:36.85#ibcon#*after write, iclass 39, count 0 2006.257.22:39:36.85#ibcon#*before return 0, iclass 39, count 0 2006.257.22:39:36.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:36.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:36.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.22:39:36.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.22:39:36.85$vck44/valo=5,734.99 2006.257.22:39:36.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.22:39:36.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.22:39:36.85#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:36.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:36.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:36.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:36.85#ibcon#enter wrdev, iclass 3, count 0 2006.257.22:39:36.85#ibcon#first serial, iclass 3, count 0 2006.257.22:39:36.85#ibcon#enter sib2, iclass 3, count 0 2006.257.22:39:36.85#ibcon#flushed, iclass 3, count 0 2006.257.22:39:36.85#ibcon#about to write, iclass 3, count 0 2006.257.22:39:36.85#ibcon#wrote, iclass 3, count 0 2006.257.22:39:36.85#ibcon#about to read 3, iclass 3, count 0 2006.257.22:39:36.87#ibcon#read 3, iclass 3, count 0 2006.257.22:39:36.87#ibcon#about to read 4, iclass 3, count 0 2006.257.22:39:36.87#ibcon#read 4, iclass 3, count 0 2006.257.22:39:36.87#ibcon#about to read 5, iclass 3, count 0 2006.257.22:39:36.87#ibcon#read 5, iclass 3, count 0 2006.257.22:39:36.87#ibcon#about to read 6, iclass 3, count 0 2006.257.22:39:36.87#ibcon#read 6, iclass 3, count 0 2006.257.22:39:36.87#ibcon#end of sib2, iclass 3, count 0 2006.257.22:39:36.87#ibcon#*mode == 0, iclass 3, count 0 2006.257.22:39:36.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.22:39:36.87#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.22:39:36.87#ibcon#*before write, iclass 3, count 0 2006.257.22:39:36.87#ibcon#enter sib2, iclass 3, count 0 2006.257.22:39:36.87#ibcon#flushed, iclass 3, count 0 2006.257.22:39:36.87#ibcon#about to write, iclass 3, count 0 2006.257.22:39:36.87#ibcon#wrote, iclass 3, count 0 2006.257.22:39:36.87#ibcon#about to read 3, iclass 3, count 0 2006.257.22:39:36.91#ibcon#read 3, iclass 3, count 0 2006.257.22:39:36.91#ibcon#about to read 4, iclass 3, count 0 2006.257.22:39:36.91#ibcon#read 4, iclass 3, count 0 2006.257.22:39:36.91#ibcon#about to read 5, iclass 3, count 0 2006.257.22:39:36.91#ibcon#read 5, iclass 3, count 0 2006.257.22:39:36.91#ibcon#about to read 6, iclass 3, count 0 2006.257.22:39:36.91#ibcon#read 6, iclass 3, count 0 2006.257.22:39:36.91#ibcon#end of sib2, iclass 3, count 0 2006.257.22:39:36.91#ibcon#*after write, iclass 3, count 0 2006.257.22:39:36.91#ibcon#*before return 0, iclass 3, count 0 2006.257.22:39:36.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:36.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:36.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.22:39:36.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.22:39:36.91$vck44/va=5,4 2006.257.22:39:36.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.22:39:36.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.22:39:36.91#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:36.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:36.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:36.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:36.97#ibcon#enter wrdev, iclass 5, count 2 2006.257.22:39:36.97#ibcon#first serial, iclass 5, count 2 2006.257.22:39:36.97#ibcon#enter sib2, iclass 5, count 2 2006.257.22:39:36.97#ibcon#flushed, iclass 5, count 2 2006.257.22:39:36.97#ibcon#about to write, iclass 5, count 2 2006.257.22:39:36.97#ibcon#wrote, iclass 5, count 2 2006.257.22:39:36.97#ibcon#about to read 3, iclass 5, count 2 2006.257.22:39:36.99#ibcon#read 3, iclass 5, count 2 2006.257.22:39:36.99#ibcon#about to read 4, iclass 5, count 2 2006.257.22:39:36.99#ibcon#read 4, iclass 5, count 2 2006.257.22:39:36.99#ibcon#about to read 5, iclass 5, count 2 2006.257.22:39:36.99#ibcon#read 5, iclass 5, count 2 2006.257.22:39:36.99#ibcon#about to read 6, iclass 5, count 2 2006.257.22:39:36.99#ibcon#read 6, iclass 5, count 2 2006.257.22:39:36.99#ibcon#end of sib2, iclass 5, count 2 2006.257.22:39:36.99#ibcon#*mode == 0, iclass 5, count 2 2006.257.22:39:36.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.22:39:36.99#ibcon#[25=AT05-04\r\n] 2006.257.22:39:36.99#ibcon#*before write, iclass 5, count 2 2006.257.22:39:36.99#ibcon#enter sib2, iclass 5, count 2 2006.257.22:39:36.99#ibcon#flushed, iclass 5, count 2 2006.257.22:39:36.99#ibcon#about to write, iclass 5, count 2 2006.257.22:39:36.99#ibcon#wrote, iclass 5, count 2 2006.257.22:39:36.99#ibcon#about to read 3, iclass 5, count 2 2006.257.22:39:37.02#ibcon#read 3, iclass 5, count 2 2006.257.22:39:37.02#ibcon#about to read 4, iclass 5, count 2 2006.257.22:39:37.02#ibcon#read 4, iclass 5, count 2 2006.257.22:39:37.02#ibcon#about to read 5, iclass 5, count 2 2006.257.22:39:37.02#ibcon#read 5, iclass 5, count 2 2006.257.22:39:37.02#ibcon#about to read 6, iclass 5, count 2 2006.257.22:39:37.02#ibcon#read 6, iclass 5, count 2 2006.257.22:39:37.02#ibcon#end of sib2, iclass 5, count 2 2006.257.22:39:37.02#ibcon#*after write, iclass 5, count 2 2006.257.22:39:37.02#ibcon#*before return 0, iclass 5, count 2 2006.257.22:39:37.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:37.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:37.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.22:39:37.02#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:37.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:37.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:37.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:37.14#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:39:37.14#ibcon#first serial, iclass 5, count 0 2006.257.22:39:37.14#ibcon#enter sib2, iclass 5, count 0 2006.257.22:39:37.14#ibcon#flushed, iclass 5, count 0 2006.257.22:39:37.14#ibcon#about to write, iclass 5, count 0 2006.257.22:39:37.14#ibcon#wrote, iclass 5, count 0 2006.257.22:39:37.14#ibcon#about to read 3, iclass 5, count 0 2006.257.22:39:37.16#ibcon#read 3, iclass 5, count 0 2006.257.22:39:37.16#ibcon#about to read 4, iclass 5, count 0 2006.257.22:39:37.16#ibcon#read 4, iclass 5, count 0 2006.257.22:39:37.16#ibcon#about to read 5, iclass 5, count 0 2006.257.22:39:37.16#ibcon#read 5, iclass 5, count 0 2006.257.22:39:37.16#ibcon#about to read 6, iclass 5, count 0 2006.257.22:39:37.16#ibcon#read 6, iclass 5, count 0 2006.257.22:39:37.16#ibcon#end of sib2, iclass 5, count 0 2006.257.22:39:37.16#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:39:37.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:39:37.16#ibcon#[25=USB\r\n] 2006.257.22:39:37.16#ibcon#*before write, iclass 5, count 0 2006.257.22:39:37.16#ibcon#enter sib2, iclass 5, count 0 2006.257.22:39:37.16#ibcon#flushed, iclass 5, count 0 2006.257.22:39:37.16#ibcon#about to write, iclass 5, count 0 2006.257.22:39:37.16#ibcon#wrote, iclass 5, count 0 2006.257.22:39:37.16#ibcon#about to read 3, iclass 5, count 0 2006.257.22:39:37.19#ibcon#read 3, iclass 5, count 0 2006.257.22:39:37.19#ibcon#about to read 4, iclass 5, count 0 2006.257.22:39:37.19#ibcon#read 4, iclass 5, count 0 2006.257.22:39:37.19#ibcon#about to read 5, iclass 5, count 0 2006.257.22:39:37.19#ibcon#read 5, iclass 5, count 0 2006.257.22:39:37.19#ibcon#about to read 6, iclass 5, count 0 2006.257.22:39:37.19#ibcon#read 6, iclass 5, count 0 2006.257.22:39:37.19#ibcon#end of sib2, iclass 5, count 0 2006.257.22:39:37.19#ibcon#*after write, iclass 5, count 0 2006.257.22:39:37.19#ibcon#*before return 0, iclass 5, count 0 2006.257.22:39:37.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:37.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:37.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:39:37.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:39:37.19$vck44/valo=6,814.99 2006.257.22:39:37.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.22:39:37.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.22:39:37.19#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:37.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:37.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:37.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:37.19#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:39:37.19#ibcon#first serial, iclass 7, count 0 2006.257.22:39:37.19#ibcon#enter sib2, iclass 7, count 0 2006.257.22:39:37.19#ibcon#flushed, iclass 7, count 0 2006.257.22:39:37.19#ibcon#about to write, iclass 7, count 0 2006.257.22:39:37.19#ibcon#wrote, iclass 7, count 0 2006.257.22:39:37.19#ibcon#about to read 3, iclass 7, count 0 2006.257.22:39:37.21#ibcon#read 3, iclass 7, count 0 2006.257.22:39:37.21#ibcon#about to read 4, iclass 7, count 0 2006.257.22:39:37.21#ibcon#read 4, iclass 7, count 0 2006.257.22:39:37.21#ibcon#about to read 5, iclass 7, count 0 2006.257.22:39:37.21#ibcon#read 5, iclass 7, count 0 2006.257.22:39:37.21#ibcon#about to read 6, iclass 7, count 0 2006.257.22:39:37.21#ibcon#read 6, iclass 7, count 0 2006.257.22:39:37.21#ibcon#end of sib2, iclass 7, count 0 2006.257.22:39:37.21#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:39:37.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:39:37.21#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.22:39:37.21#ibcon#*before write, iclass 7, count 0 2006.257.22:39:37.21#ibcon#enter sib2, iclass 7, count 0 2006.257.22:39:37.21#ibcon#flushed, iclass 7, count 0 2006.257.22:39:37.21#ibcon#about to write, iclass 7, count 0 2006.257.22:39:37.21#ibcon#wrote, iclass 7, count 0 2006.257.22:39:37.21#ibcon#about to read 3, iclass 7, count 0 2006.257.22:39:37.25#ibcon#read 3, iclass 7, count 0 2006.257.22:39:37.25#ibcon#about to read 4, iclass 7, count 0 2006.257.22:39:37.25#ibcon#read 4, iclass 7, count 0 2006.257.22:39:37.25#ibcon#about to read 5, iclass 7, count 0 2006.257.22:39:37.25#ibcon#read 5, iclass 7, count 0 2006.257.22:39:37.25#ibcon#about to read 6, iclass 7, count 0 2006.257.22:39:37.25#ibcon#read 6, iclass 7, count 0 2006.257.22:39:37.25#ibcon#end of sib2, iclass 7, count 0 2006.257.22:39:37.25#ibcon#*after write, iclass 7, count 0 2006.257.22:39:37.25#ibcon#*before return 0, iclass 7, count 0 2006.257.22:39:37.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:37.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:37.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:39:37.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:39:37.25$vck44/va=6,4 2006.257.22:39:37.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.22:39:37.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.22:39:37.25#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:37.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:37.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:37.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:37.31#ibcon#enter wrdev, iclass 11, count 2 2006.257.22:39:37.31#ibcon#first serial, iclass 11, count 2 2006.257.22:39:37.31#ibcon#enter sib2, iclass 11, count 2 2006.257.22:39:37.31#ibcon#flushed, iclass 11, count 2 2006.257.22:39:37.31#ibcon#about to write, iclass 11, count 2 2006.257.22:39:37.31#ibcon#wrote, iclass 11, count 2 2006.257.22:39:37.31#ibcon#about to read 3, iclass 11, count 2 2006.257.22:39:37.33#ibcon#read 3, iclass 11, count 2 2006.257.22:39:37.33#ibcon#about to read 4, iclass 11, count 2 2006.257.22:39:37.33#ibcon#read 4, iclass 11, count 2 2006.257.22:39:37.33#ibcon#about to read 5, iclass 11, count 2 2006.257.22:39:37.33#ibcon#read 5, iclass 11, count 2 2006.257.22:39:37.33#ibcon#about to read 6, iclass 11, count 2 2006.257.22:39:37.33#ibcon#read 6, iclass 11, count 2 2006.257.22:39:37.33#ibcon#end of sib2, iclass 11, count 2 2006.257.22:39:37.33#ibcon#*mode == 0, iclass 11, count 2 2006.257.22:39:37.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.22:39:37.33#ibcon#[25=AT06-04\r\n] 2006.257.22:39:37.33#ibcon#*before write, iclass 11, count 2 2006.257.22:39:37.33#ibcon#enter sib2, iclass 11, count 2 2006.257.22:39:37.33#ibcon#flushed, iclass 11, count 2 2006.257.22:39:37.33#ibcon#about to write, iclass 11, count 2 2006.257.22:39:37.33#ibcon#wrote, iclass 11, count 2 2006.257.22:39:37.33#ibcon#about to read 3, iclass 11, count 2 2006.257.22:39:37.36#ibcon#read 3, iclass 11, count 2 2006.257.22:39:37.36#ibcon#about to read 4, iclass 11, count 2 2006.257.22:39:37.36#ibcon#read 4, iclass 11, count 2 2006.257.22:39:37.36#ibcon#about to read 5, iclass 11, count 2 2006.257.22:39:37.36#ibcon#read 5, iclass 11, count 2 2006.257.22:39:37.36#ibcon#about to read 6, iclass 11, count 2 2006.257.22:39:37.36#ibcon#read 6, iclass 11, count 2 2006.257.22:39:37.36#ibcon#end of sib2, iclass 11, count 2 2006.257.22:39:37.36#ibcon#*after write, iclass 11, count 2 2006.257.22:39:37.36#ibcon#*before return 0, iclass 11, count 2 2006.257.22:39:37.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:37.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:37.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.22:39:37.36#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:37.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:37.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:37.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:37.48#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:39:37.48#ibcon#first serial, iclass 11, count 0 2006.257.22:39:37.48#ibcon#enter sib2, iclass 11, count 0 2006.257.22:39:37.48#ibcon#flushed, iclass 11, count 0 2006.257.22:39:37.48#ibcon#about to write, iclass 11, count 0 2006.257.22:39:37.48#ibcon#wrote, iclass 11, count 0 2006.257.22:39:37.48#ibcon#about to read 3, iclass 11, count 0 2006.257.22:39:37.50#ibcon#read 3, iclass 11, count 0 2006.257.22:39:37.50#ibcon#about to read 4, iclass 11, count 0 2006.257.22:39:37.50#ibcon#read 4, iclass 11, count 0 2006.257.22:39:37.50#ibcon#about to read 5, iclass 11, count 0 2006.257.22:39:37.50#ibcon#read 5, iclass 11, count 0 2006.257.22:39:37.50#ibcon#about to read 6, iclass 11, count 0 2006.257.22:39:37.50#ibcon#read 6, iclass 11, count 0 2006.257.22:39:37.50#ibcon#end of sib2, iclass 11, count 0 2006.257.22:39:37.50#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:39:37.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:39:37.50#ibcon#[25=USB\r\n] 2006.257.22:39:37.50#ibcon#*before write, iclass 11, count 0 2006.257.22:39:37.50#ibcon#enter sib2, iclass 11, count 0 2006.257.22:39:37.50#ibcon#flushed, iclass 11, count 0 2006.257.22:39:37.50#ibcon#about to write, iclass 11, count 0 2006.257.22:39:37.50#ibcon#wrote, iclass 11, count 0 2006.257.22:39:37.50#ibcon#about to read 3, iclass 11, count 0 2006.257.22:39:37.53#ibcon#read 3, iclass 11, count 0 2006.257.22:39:37.53#ibcon#about to read 4, iclass 11, count 0 2006.257.22:39:37.53#ibcon#read 4, iclass 11, count 0 2006.257.22:39:37.53#ibcon#about to read 5, iclass 11, count 0 2006.257.22:39:37.53#ibcon#read 5, iclass 11, count 0 2006.257.22:39:37.53#ibcon#about to read 6, iclass 11, count 0 2006.257.22:39:37.53#ibcon#read 6, iclass 11, count 0 2006.257.22:39:37.53#ibcon#end of sib2, iclass 11, count 0 2006.257.22:39:37.53#ibcon#*after write, iclass 11, count 0 2006.257.22:39:37.53#ibcon#*before return 0, iclass 11, count 0 2006.257.22:39:37.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:37.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:37.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:39:37.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:39:37.53$vck44/valo=7,864.99 2006.257.22:39:37.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.22:39:37.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.22:39:37.53#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:37.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:37.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:37.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:37.53#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:39:37.53#ibcon#first serial, iclass 13, count 0 2006.257.22:39:37.53#ibcon#enter sib2, iclass 13, count 0 2006.257.22:39:37.53#ibcon#flushed, iclass 13, count 0 2006.257.22:39:37.53#ibcon#about to write, iclass 13, count 0 2006.257.22:39:37.53#ibcon#wrote, iclass 13, count 0 2006.257.22:39:37.53#ibcon#about to read 3, iclass 13, count 0 2006.257.22:39:37.55#ibcon#read 3, iclass 13, count 0 2006.257.22:39:37.55#ibcon#about to read 4, iclass 13, count 0 2006.257.22:39:37.55#ibcon#read 4, iclass 13, count 0 2006.257.22:39:37.55#ibcon#about to read 5, iclass 13, count 0 2006.257.22:39:37.55#ibcon#read 5, iclass 13, count 0 2006.257.22:39:37.55#ibcon#about to read 6, iclass 13, count 0 2006.257.22:39:37.55#ibcon#read 6, iclass 13, count 0 2006.257.22:39:37.55#ibcon#end of sib2, iclass 13, count 0 2006.257.22:39:37.55#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:39:37.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:39:37.55#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.22:39:37.55#ibcon#*before write, iclass 13, count 0 2006.257.22:39:37.55#ibcon#enter sib2, iclass 13, count 0 2006.257.22:39:37.55#ibcon#flushed, iclass 13, count 0 2006.257.22:39:37.55#ibcon#about to write, iclass 13, count 0 2006.257.22:39:37.55#ibcon#wrote, iclass 13, count 0 2006.257.22:39:37.55#ibcon#about to read 3, iclass 13, count 0 2006.257.22:39:37.59#ibcon#read 3, iclass 13, count 0 2006.257.22:39:37.59#ibcon#about to read 4, iclass 13, count 0 2006.257.22:39:37.59#ibcon#read 4, iclass 13, count 0 2006.257.22:39:37.59#ibcon#about to read 5, iclass 13, count 0 2006.257.22:39:37.59#ibcon#read 5, iclass 13, count 0 2006.257.22:39:37.59#ibcon#about to read 6, iclass 13, count 0 2006.257.22:39:37.59#ibcon#read 6, iclass 13, count 0 2006.257.22:39:37.59#ibcon#end of sib2, iclass 13, count 0 2006.257.22:39:37.59#ibcon#*after write, iclass 13, count 0 2006.257.22:39:37.59#ibcon#*before return 0, iclass 13, count 0 2006.257.22:39:37.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:37.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:37.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:39:37.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:39:37.59$vck44/va=7,4 2006.257.22:39:37.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.22:39:37.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.22:39:37.59#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:37.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:37.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:37.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:37.65#ibcon#enter wrdev, iclass 15, count 2 2006.257.22:39:37.65#ibcon#first serial, iclass 15, count 2 2006.257.22:39:37.65#ibcon#enter sib2, iclass 15, count 2 2006.257.22:39:37.65#ibcon#flushed, iclass 15, count 2 2006.257.22:39:37.65#ibcon#about to write, iclass 15, count 2 2006.257.22:39:37.65#ibcon#wrote, iclass 15, count 2 2006.257.22:39:37.65#ibcon#about to read 3, iclass 15, count 2 2006.257.22:39:37.67#ibcon#read 3, iclass 15, count 2 2006.257.22:39:37.67#ibcon#about to read 4, iclass 15, count 2 2006.257.22:39:37.67#ibcon#read 4, iclass 15, count 2 2006.257.22:39:37.67#ibcon#about to read 5, iclass 15, count 2 2006.257.22:39:37.67#ibcon#read 5, iclass 15, count 2 2006.257.22:39:37.67#ibcon#about to read 6, iclass 15, count 2 2006.257.22:39:37.67#ibcon#read 6, iclass 15, count 2 2006.257.22:39:37.67#ibcon#end of sib2, iclass 15, count 2 2006.257.22:39:37.67#ibcon#*mode == 0, iclass 15, count 2 2006.257.22:39:37.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.22:39:37.67#ibcon#[25=AT07-04\r\n] 2006.257.22:39:37.67#ibcon#*before write, iclass 15, count 2 2006.257.22:39:37.67#ibcon#enter sib2, iclass 15, count 2 2006.257.22:39:37.67#ibcon#flushed, iclass 15, count 2 2006.257.22:39:37.67#ibcon#about to write, iclass 15, count 2 2006.257.22:39:37.67#ibcon#wrote, iclass 15, count 2 2006.257.22:39:37.67#ibcon#about to read 3, iclass 15, count 2 2006.257.22:39:37.70#ibcon#read 3, iclass 15, count 2 2006.257.22:39:37.70#ibcon#about to read 4, iclass 15, count 2 2006.257.22:39:37.70#ibcon#read 4, iclass 15, count 2 2006.257.22:39:37.70#ibcon#about to read 5, iclass 15, count 2 2006.257.22:39:37.70#ibcon#read 5, iclass 15, count 2 2006.257.22:39:37.70#ibcon#about to read 6, iclass 15, count 2 2006.257.22:39:37.70#ibcon#read 6, iclass 15, count 2 2006.257.22:39:37.70#ibcon#end of sib2, iclass 15, count 2 2006.257.22:39:37.70#ibcon#*after write, iclass 15, count 2 2006.257.22:39:37.70#ibcon#*before return 0, iclass 15, count 2 2006.257.22:39:37.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:37.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:37.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.22:39:37.70#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:37.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:37.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:37.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:37.82#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:39:37.82#ibcon#first serial, iclass 15, count 0 2006.257.22:39:37.82#ibcon#enter sib2, iclass 15, count 0 2006.257.22:39:37.82#ibcon#flushed, iclass 15, count 0 2006.257.22:39:37.82#ibcon#about to write, iclass 15, count 0 2006.257.22:39:37.82#ibcon#wrote, iclass 15, count 0 2006.257.22:39:37.82#ibcon#about to read 3, iclass 15, count 0 2006.257.22:39:37.84#ibcon#read 3, iclass 15, count 0 2006.257.22:39:37.84#ibcon#about to read 4, iclass 15, count 0 2006.257.22:39:37.84#ibcon#read 4, iclass 15, count 0 2006.257.22:39:37.84#ibcon#about to read 5, iclass 15, count 0 2006.257.22:39:37.84#ibcon#read 5, iclass 15, count 0 2006.257.22:39:37.84#ibcon#about to read 6, iclass 15, count 0 2006.257.22:39:37.84#ibcon#read 6, iclass 15, count 0 2006.257.22:39:37.84#ibcon#end of sib2, iclass 15, count 0 2006.257.22:39:37.84#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:39:37.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:39:37.84#ibcon#[25=USB\r\n] 2006.257.22:39:37.84#ibcon#*before write, iclass 15, count 0 2006.257.22:39:37.84#ibcon#enter sib2, iclass 15, count 0 2006.257.22:39:37.84#ibcon#flushed, iclass 15, count 0 2006.257.22:39:37.84#ibcon#about to write, iclass 15, count 0 2006.257.22:39:37.84#ibcon#wrote, iclass 15, count 0 2006.257.22:39:37.84#ibcon#about to read 3, iclass 15, count 0 2006.257.22:39:37.87#ibcon#read 3, iclass 15, count 0 2006.257.22:39:37.87#ibcon#about to read 4, iclass 15, count 0 2006.257.22:39:37.87#ibcon#read 4, iclass 15, count 0 2006.257.22:39:37.87#ibcon#about to read 5, iclass 15, count 0 2006.257.22:39:37.87#ibcon#read 5, iclass 15, count 0 2006.257.22:39:37.87#ibcon#about to read 6, iclass 15, count 0 2006.257.22:39:37.87#ibcon#read 6, iclass 15, count 0 2006.257.22:39:37.87#ibcon#end of sib2, iclass 15, count 0 2006.257.22:39:37.87#ibcon#*after write, iclass 15, count 0 2006.257.22:39:37.87#ibcon#*before return 0, iclass 15, count 0 2006.257.22:39:37.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:37.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:37.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:39:37.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:39:37.87$vck44/valo=8,884.99 2006.257.22:39:37.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.22:39:37.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.22:39:37.87#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:37.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:37.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:37.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:37.87#ibcon#enter wrdev, iclass 17, count 0 2006.257.22:39:37.87#ibcon#first serial, iclass 17, count 0 2006.257.22:39:37.87#ibcon#enter sib2, iclass 17, count 0 2006.257.22:39:37.87#ibcon#flushed, iclass 17, count 0 2006.257.22:39:37.87#ibcon#about to write, iclass 17, count 0 2006.257.22:39:37.87#ibcon#wrote, iclass 17, count 0 2006.257.22:39:37.87#ibcon#about to read 3, iclass 17, count 0 2006.257.22:39:37.89#ibcon#read 3, iclass 17, count 0 2006.257.22:39:37.89#ibcon#about to read 4, iclass 17, count 0 2006.257.22:39:37.89#ibcon#read 4, iclass 17, count 0 2006.257.22:39:37.89#ibcon#about to read 5, iclass 17, count 0 2006.257.22:39:37.89#ibcon#read 5, iclass 17, count 0 2006.257.22:39:37.89#ibcon#about to read 6, iclass 17, count 0 2006.257.22:39:37.89#ibcon#read 6, iclass 17, count 0 2006.257.22:39:37.89#ibcon#end of sib2, iclass 17, count 0 2006.257.22:39:37.89#ibcon#*mode == 0, iclass 17, count 0 2006.257.22:39:37.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.22:39:37.89#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.22:39:37.89#ibcon#*before write, iclass 17, count 0 2006.257.22:39:37.89#ibcon#enter sib2, iclass 17, count 0 2006.257.22:39:37.89#ibcon#flushed, iclass 17, count 0 2006.257.22:39:37.89#ibcon#about to write, iclass 17, count 0 2006.257.22:39:37.89#ibcon#wrote, iclass 17, count 0 2006.257.22:39:37.89#ibcon#about to read 3, iclass 17, count 0 2006.257.22:39:37.93#ibcon#read 3, iclass 17, count 0 2006.257.22:39:37.93#ibcon#about to read 4, iclass 17, count 0 2006.257.22:39:37.93#ibcon#read 4, iclass 17, count 0 2006.257.22:39:37.93#ibcon#about to read 5, iclass 17, count 0 2006.257.22:39:37.93#ibcon#read 5, iclass 17, count 0 2006.257.22:39:37.93#ibcon#about to read 6, iclass 17, count 0 2006.257.22:39:37.93#ibcon#read 6, iclass 17, count 0 2006.257.22:39:37.93#ibcon#end of sib2, iclass 17, count 0 2006.257.22:39:37.93#ibcon#*after write, iclass 17, count 0 2006.257.22:39:37.93#ibcon#*before return 0, iclass 17, count 0 2006.257.22:39:37.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:37.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:37.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.22:39:37.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.22:39:37.93$vck44/va=8,4 2006.257.22:39:37.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.22:39:37.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.22:39:37.93#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:37.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:39:37.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:39:37.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:39:37.99#ibcon#enter wrdev, iclass 19, count 2 2006.257.22:39:37.99#ibcon#first serial, iclass 19, count 2 2006.257.22:39:37.99#ibcon#enter sib2, iclass 19, count 2 2006.257.22:39:37.99#ibcon#flushed, iclass 19, count 2 2006.257.22:39:37.99#ibcon#about to write, iclass 19, count 2 2006.257.22:39:37.99#ibcon#wrote, iclass 19, count 2 2006.257.22:39:37.99#ibcon#about to read 3, iclass 19, count 2 2006.257.22:39:38.01#ibcon#read 3, iclass 19, count 2 2006.257.22:39:38.01#ibcon#about to read 4, iclass 19, count 2 2006.257.22:39:38.01#ibcon#read 4, iclass 19, count 2 2006.257.22:39:38.01#ibcon#about to read 5, iclass 19, count 2 2006.257.22:39:38.01#ibcon#read 5, iclass 19, count 2 2006.257.22:39:38.01#ibcon#about to read 6, iclass 19, count 2 2006.257.22:39:38.01#ibcon#read 6, iclass 19, count 2 2006.257.22:39:38.01#ibcon#end of sib2, iclass 19, count 2 2006.257.22:39:38.01#ibcon#*mode == 0, iclass 19, count 2 2006.257.22:39:38.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.22:39:38.01#ibcon#[25=AT08-04\r\n] 2006.257.22:39:38.01#ibcon#*before write, iclass 19, count 2 2006.257.22:39:38.01#ibcon#enter sib2, iclass 19, count 2 2006.257.22:39:38.01#ibcon#flushed, iclass 19, count 2 2006.257.22:39:38.01#ibcon#about to write, iclass 19, count 2 2006.257.22:39:38.01#ibcon#wrote, iclass 19, count 2 2006.257.22:39:38.01#ibcon#about to read 3, iclass 19, count 2 2006.257.22:39:38.04#ibcon#read 3, iclass 19, count 2 2006.257.22:39:38.04#ibcon#about to read 4, iclass 19, count 2 2006.257.22:39:38.04#ibcon#read 4, iclass 19, count 2 2006.257.22:39:38.04#ibcon#about to read 5, iclass 19, count 2 2006.257.22:39:38.04#ibcon#read 5, iclass 19, count 2 2006.257.22:39:38.04#ibcon#about to read 6, iclass 19, count 2 2006.257.22:39:38.04#ibcon#read 6, iclass 19, count 2 2006.257.22:39:38.04#ibcon#end of sib2, iclass 19, count 2 2006.257.22:39:38.04#ibcon#*after write, iclass 19, count 2 2006.257.22:39:38.04#ibcon#*before return 0, iclass 19, count 2 2006.257.22:39:38.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:39:38.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.22:39:38.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.22:39:38.04#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:38.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:39:38.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:39:38.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:39:38.16#ibcon#enter wrdev, iclass 19, count 0 2006.257.22:39:38.16#ibcon#first serial, iclass 19, count 0 2006.257.22:39:38.16#ibcon#enter sib2, iclass 19, count 0 2006.257.22:39:38.16#ibcon#flushed, iclass 19, count 0 2006.257.22:39:38.16#ibcon#about to write, iclass 19, count 0 2006.257.22:39:38.16#ibcon#wrote, iclass 19, count 0 2006.257.22:39:38.16#ibcon#about to read 3, iclass 19, count 0 2006.257.22:39:38.18#ibcon#read 3, iclass 19, count 0 2006.257.22:39:38.18#ibcon#about to read 4, iclass 19, count 0 2006.257.22:39:38.18#ibcon#read 4, iclass 19, count 0 2006.257.22:39:38.18#ibcon#about to read 5, iclass 19, count 0 2006.257.22:39:38.18#ibcon#read 5, iclass 19, count 0 2006.257.22:39:38.18#ibcon#about to read 6, iclass 19, count 0 2006.257.22:39:38.18#ibcon#read 6, iclass 19, count 0 2006.257.22:39:38.18#ibcon#end of sib2, iclass 19, count 0 2006.257.22:39:38.18#ibcon#*mode == 0, iclass 19, count 0 2006.257.22:39:38.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.22:39:38.18#ibcon#[25=USB\r\n] 2006.257.22:39:38.18#ibcon#*before write, iclass 19, count 0 2006.257.22:39:38.18#ibcon#enter sib2, iclass 19, count 0 2006.257.22:39:38.18#ibcon#flushed, iclass 19, count 0 2006.257.22:39:38.18#ibcon#about to write, iclass 19, count 0 2006.257.22:39:38.18#ibcon#wrote, iclass 19, count 0 2006.257.22:39:38.18#ibcon#about to read 3, iclass 19, count 0 2006.257.22:39:38.21#ibcon#read 3, iclass 19, count 0 2006.257.22:39:38.21#ibcon#about to read 4, iclass 19, count 0 2006.257.22:39:38.21#ibcon#read 4, iclass 19, count 0 2006.257.22:39:38.21#ibcon#about to read 5, iclass 19, count 0 2006.257.22:39:38.21#ibcon#read 5, iclass 19, count 0 2006.257.22:39:38.21#ibcon#about to read 6, iclass 19, count 0 2006.257.22:39:38.21#ibcon#read 6, iclass 19, count 0 2006.257.22:39:38.21#ibcon#end of sib2, iclass 19, count 0 2006.257.22:39:38.21#ibcon#*after write, iclass 19, count 0 2006.257.22:39:38.21#ibcon#*before return 0, iclass 19, count 0 2006.257.22:39:38.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:39:38.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.22:39:38.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.22:39:38.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.22:39:38.21$vck44/vblo=1,629.99 2006.257.22:39:38.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.22:39:38.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.22:39:38.21#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:38.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:39:38.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:39:38.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:39:38.21#ibcon#enter wrdev, iclass 21, count 0 2006.257.22:39:38.21#ibcon#first serial, iclass 21, count 0 2006.257.22:39:38.21#ibcon#enter sib2, iclass 21, count 0 2006.257.22:39:38.21#ibcon#flushed, iclass 21, count 0 2006.257.22:39:38.21#ibcon#about to write, iclass 21, count 0 2006.257.22:39:38.21#ibcon#wrote, iclass 21, count 0 2006.257.22:39:38.21#ibcon#about to read 3, iclass 21, count 0 2006.257.22:39:38.23#ibcon#read 3, iclass 21, count 0 2006.257.22:39:38.23#ibcon#about to read 4, iclass 21, count 0 2006.257.22:39:38.23#ibcon#read 4, iclass 21, count 0 2006.257.22:39:38.23#ibcon#about to read 5, iclass 21, count 0 2006.257.22:39:38.23#ibcon#read 5, iclass 21, count 0 2006.257.22:39:38.23#ibcon#about to read 6, iclass 21, count 0 2006.257.22:39:38.23#ibcon#read 6, iclass 21, count 0 2006.257.22:39:38.23#ibcon#end of sib2, iclass 21, count 0 2006.257.22:39:38.23#ibcon#*mode == 0, iclass 21, count 0 2006.257.22:39:38.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.22:39:38.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.22:39:38.23#ibcon#*before write, iclass 21, count 0 2006.257.22:39:38.23#ibcon#enter sib2, iclass 21, count 0 2006.257.22:39:38.23#ibcon#flushed, iclass 21, count 0 2006.257.22:39:38.23#ibcon#about to write, iclass 21, count 0 2006.257.22:39:38.23#ibcon#wrote, iclass 21, count 0 2006.257.22:39:38.23#ibcon#about to read 3, iclass 21, count 0 2006.257.22:39:38.27#ibcon#read 3, iclass 21, count 0 2006.257.22:39:38.27#ibcon#about to read 4, iclass 21, count 0 2006.257.22:39:38.27#ibcon#read 4, iclass 21, count 0 2006.257.22:39:38.27#ibcon#about to read 5, iclass 21, count 0 2006.257.22:39:38.27#ibcon#read 5, iclass 21, count 0 2006.257.22:39:38.27#ibcon#about to read 6, iclass 21, count 0 2006.257.22:39:38.27#ibcon#read 6, iclass 21, count 0 2006.257.22:39:38.27#ibcon#end of sib2, iclass 21, count 0 2006.257.22:39:38.27#ibcon#*after write, iclass 21, count 0 2006.257.22:39:38.27#ibcon#*before return 0, iclass 21, count 0 2006.257.22:39:38.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:39:38.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:39:38.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.22:39:38.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.22:39:38.27$vck44/vb=1,4 2006.257.22:39:38.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.22:39:38.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.22:39:38.27#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:38.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:39:38.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:39:38.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:39:38.27#ibcon#enter wrdev, iclass 23, count 2 2006.257.22:39:38.27#ibcon#first serial, iclass 23, count 2 2006.257.22:39:38.27#ibcon#enter sib2, iclass 23, count 2 2006.257.22:39:38.27#ibcon#flushed, iclass 23, count 2 2006.257.22:39:38.27#ibcon#about to write, iclass 23, count 2 2006.257.22:39:38.27#ibcon#wrote, iclass 23, count 2 2006.257.22:39:38.27#ibcon#about to read 3, iclass 23, count 2 2006.257.22:39:38.29#ibcon#read 3, iclass 23, count 2 2006.257.22:39:38.29#ibcon#about to read 4, iclass 23, count 2 2006.257.22:39:38.29#ibcon#read 4, iclass 23, count 2 2006.257.22:39:38.29#ibcon#about to read 5, iclass 23, count 2 2006.257.22:39:38.29#ibcon#read 5, iclass 23, count 2 2006.257.22:39:38.29#ibcon#about to read 6, iclass 23, count 2 2006.257.22:39:38.29#ibcon#read 6, iclass 23, count 2 2006.257.22:39:38.29#ibcon#end of sib2, iclass 23, count 2 2006.257.22:39:38.29#ibcon#*mode == 0, iclass 23, count 2 2006.257.22:39:38.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.22:39:38.29#ibcon#[27=AT01-04\r\n] 2006.257.22:39:38.29#ibcon#*before write, iclass 23, count 2 2006.257.22:39:38.29#ibcon#enter sib2, iclass 23, count 2 2006.257.22:39:38.29#ibcon#flushed, iclass 23, count 2 2006.257.22:39:38.29#ibcon#about to write, iclass 23, count 2 2006.257.22:39:38.29#ibcon#wrote, iclass 23, count 2 2006.257.22:39:38.29#ibcon#about to read 3, iclass 23, count 2 2006.257.22:39:38.32#ibcon#read 3, iclass 23, count 2 2006.257.22:39:38.32#ibcon#about to read 4, iclass 23, count 2 2006.257.22:39:38.32#ibcon#read 4, iclass 23, count 2 2006.257.22:39:38.32#ibcon#about to read 5, iclass 23, count 2 2006.257.22:39:38.32#ibcon#read 5, iclass 23, count 2 2006.257.22:39:38.32#ibcon#about to read 6, iclass 23, count 2 2006.257.22:39:38.32#ibcon#read 6, iclass 23, count 2 2006.257.22:39:38.32#ibcon#end of sib2, iclass 23, count 2 2006.257.22:39:38.32#ibcon#*after write, iclass 23, count 2 2006.257.22:39:38.32#ibcon#*before return 0, iclass 23, count 2 2006.257.22:39:38.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:39:38.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.22:39:38.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.22:39:38.32#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:38.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:39:38.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:39:38.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:39:38.44#ibcon#enter wrdev, iclass 23, count 0 2006.257.22:39:38.44#ibcon#first serial, iclass 23, count 0 2006.257.22:39:38.44#ibcon#enter sib2, iclass 23, count 0 2006.257.22:39:38.44#ibcon#flushed, iclass 23, count 0 2006.257.22:39:38.44#ibcon#about to write, iclass 23, count 0 2006.257.22:39:38.44#ibcon#wrote, iclass 23, count 0 2006.257.22:39:38.44#ibcon#about to read 3, iclass 23, count 0 2006.257.22:39:38.46#ibcon#read 3, iclass 23, count 0 2006.257.22:39:38.46#ibcon#about to read 4, iclass 23, count 0 2006.257.22:39:38.46#ibcon#read 4, iclass 23, count 0 2006.257.22:39:38.46#ibcon#about to read 5, iclass 23, count 0 2006.257.22:39:38.46#ibcon#read 5, iclass 23, count 0 2006.257.22:39:38.46#ibcon#about to read 6, iclass 23, count 0 2006.257.22:39:38.46#ibcon#read 6, iclass 23, count 0 2006.257.22:39:38.46#ibcon#end of sib2, iclass 23, count 0 2006.257.22:39:38.46#ibcon#*mode == 0, iclass 23, count 0 2006.257.22:39:38.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.22:39:38.46#ibcon#[27=USB\r\n] 2006.257.22:39:38.46#ibcon#*before write, iclass 23, count 0 2006.257.22:39:38.46#ibcon#enter sib2, iclass 23, count 0 2006.257.22:39:38.46#ibcon#flushed, iclass 23, count 0 2006.257.22:39:38.46#ibcon#about to write, iclass 23, count 0 2006.257.22:39:38.46#ibcon#wrote, iclass 23, count 0 2006.257.22:39:38.46#ibcon#about to read 3, iclass 23, count 0 2006.257.22:39:38.49#ibcon#read 3, iclass 23, count 0 2006.257.22:39:38.49#ibcon#about to read 4, iclass 23, count 0 2006.257.22:39:38.49#ibcon#read 4, iclass 23, count 0 2006.257.22:39:38.49#ibcon#about to read 5, iclass 23, count 0 2006.257.22:39:38.49#ibcon#read 5, iclass 23, count 0 2006.257.22:39:38.49#ibcon#about to read 6, iclass 23, count 0 2006.257.22:39:38.49#ibcon#read 6, iclass 23, count 0 2006.257.22:39:38.49#ibcon#end of sib2, iclass 23, count 0 2006.257.22:39:38.49#ibcon#*after write, iclass 23, count 0 2006.257.22:39:38.49#ibcon#*before return 0, iclass 23, count 0 2006.257.22:39:38.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:39:38.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.22:39:38.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.22:39:38.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.22:39:38.49$vck44/vblo=2,634.99 2006.257.22:39:38.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.22:39:38.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.22:39:38.49#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:38.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:38.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:38.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:38.49#ibcon#enter wrdev, iclass 25, count 0 2006.257.22:39:38.49#ibcon#first serial, iclass 25, count 0 2006.257.22:39:38.49#ibcon#enter sib2, iclass 25, count 0 2006.257.22:39:38.49#ibcon#flushed, iclass 25, count 0 2006.257.22:39:38.49#ibcon#about to write, iclass 25, count 0 2006.257.22:39:38.49#ibcon#wrote, iclass 25, count 0 2006.257.22:39:38.49#ibcon#about to read 3, iclass 25, count 0 2006.257.22:39:38.51#ibcon#read 3, iclass 25, count 0 2006.257.22:39:38.51#ibcon#about to read 4, iclass 25, count 0 2006.257.22:39:38.51#ibcon#read 4, iclass 25, count 0 2006.257.22:39:38.51#ibcon#about to read 5, iclass 25, count 0 2006.257.22:39:38.51#ibcon#read 5, iclass 25, count 0 2006.257.22:39:38.51#ibcon#about to read 6, iclass 25, count 0 2006.257.22:39:38.51#ibcon#read 6, iclass 25, count 0 2006.257.22:39:38.51#ibcon#end of sib2, iclass 25, count 0 2006.257.22:39:38.51#ibcon#*mode == 0, iclass 25, count 0 2006.257.22:39:38.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.22:39:38.51#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.22:39:38.51#ibcon#*before write, iclass 25, count 0 2006.257.22:39:38.51#ibcon#enter sib2, iclass 25, count 0 2006.257.22:39:38.51#ibcon#flushed, iclass 25, count 0 2006.257.22:39:38.51#ibcon#about to write, iclass 25, count 0 2006.257.22:39:38.51#ibcon#wrote, iclass 25, count 0 2006.257.22:39:38.51#ibcon#about to read 3, iclass 25, count 0 2006.257.22:39:38.55#ibcon#read 3, iclass 25, count 0 2006.257.22:39:38.55#ibcon#about to read 4, iclass 25, count 0 2006.257.22:39:38.55#ibcon#read 4, iclass 25, count 0 2006.257.22:39:38.55#ibcon#about to read 5, iclass 25, count 0 2006.257.22:39:38.55#ibcon#read 5, iclass 25, count 0 2006.257.22:39:38.55#ibcon#about to read 6, iclass 25, count 0 2006.257.22:39:38.55#ibcon#read 6, iclass 25, count 0 2006.257.22:39:38.55#ibcon#end of sib2, iclass 25, count 0 2006.257.22:39:38.55#ibcon#*after write, iclass 25, count 0 2006.257.22:39:38.55#ibcon#*before return 0, iclass 25, count 0 2006.257.22:39:38.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:38.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.22:39:38.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.22:39:38.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.22:39:38.55$vck44/vb=2,5 2006.257.22:39:38.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.22:39:38.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.22:39:38.55#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:38.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:38.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:38.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:38.61#ibcon#enter wrdev, iclass 27, count 2 2006.257.22:39:38.61#ibcon#first serial, iclass 27, count 2 2006.257.22:39:38.61#ibcon#enter sib2, iclass 27, count 2 2006.257.22:39:38.61#ibcon#flushed, iclass 27, count 2 2006.257.22:39:38.61#ibcon#about to write, iclass 27, count 2 2006.257.22:39:38.61#ibcon#wrote, iclass 27, count 2 2006.257.22:39:38.61#ibcon#about to read 3, iclass 27, count 2 2006.257.22:39:38.63#ibcon#read 3, iclass 27, count 2 2006.257.22:39:38.63#ibcon#about to read 4, iclass 27, count 2 2006.257.22:39:38.63#ibcon#read 4, iclass 27, count 2 2006.257.22:39:38.63#ibcon#about to read 5, iclass 27, count 2 2006.257.22:39:38.63#ibcon#read 5, iclass 27, count 2 2006.257.22:39:38.63#ibcon#about to read 6, iclass 27, count 2 2006.257.22:39:38.63#ibcon#read 6, iclass 27, count 2 2006.257.22:39:38.63#ibcon#end of sib2, iclass 27, count 2 2006.257.22:39:38.63#ibcon#*mode == 0, iclass 27, count 2 2006.257.22:39:38.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.22:39:38.63#ibcon#[27=AT02-05\r\n] 2006.257.22:39:38.63#ibcon#*before write, iclass 27, count 2 2006.257.22:39:38.63#ibcon#enter sib2, iclass 27, count 2 2006.257.22:39:38.63#ibcon#flushed, iclass 27, count 2 2006.257.22:39:38.63#ibcon#about to write, iclass 27, count 2 2006.257.22:39:38.63#ibcon#wrote, iclass 27, count 2 2006.257.22:39:38.63#ibcon#about to read 3, iclass 27, count 2 2006.257.22:39:38.66#ibcon#read 3, iclass 27, count 2 2006.257.22:39:38.66#ibcon#about to read 4, iclass 27, count 2 2006.257.22:39:38.66#ibcon#read 4, iclass 27, count 2 2006.257.22:39:38.66#ibcon#about to read 5, iclass 27, count 2 2006.257.22:39:38.66#ibcon#read 5, iclass 27, count 2 2006.257.22:39:38.66#ibcon#about to read 6, iclass 27, count 2 2006.257.22:39:38.66#ibcon#read 6, iclass 27, count 2 2006.257.22:39:38.66#ibcon#end of sib2, iclass 27, count 2 2006.257.22:39:38.66#ibcon#*after write, iclass 27, count 2 2006.257.22:39:38.66#ibcon#*before return 0, iclass 27, count 2 2006.257.22:39:38.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:38.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.22:39:38.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.22:39:38.66#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:38.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:38.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:38.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:38.78#ibcon#enter wrdev, iclass 27, count 0 2006.257.22:39:38.78#ibcon#first serial, iclass 27, count 0 2006.257.22:39:38.78#ibcon#enter sib2, iclass 27, count 0 2006.257.22:39:38.78#ibcon#flushed, iclass 27, count 0 2006.257.22:39:38.78#ibcon#about to write, iclass 27, count 0 2006.257.22:39:38.78#ibcon#wrote, iclass 27, count 0 2006.257.22:39:38.78#ibcon#about to read 3, iclass 27, count 0 2006.257.22:39:38.80#ibcon#read 3, iclass 27, count 0 2006.257.22:39:38.80#ibcon#about to read 4, iclass 27, count 0 2006.257.22:39:38.80#ibcon#read 4, iclass 27, count 0 2006.257.22:39:38.80#ibcon#about to read 5, iclass 27, count 0 2006.257.22:39:38.80#ibcon#read 5, iclass 27, count 0 2006.257.22:39:38.80#ibcon#about to read 6, iclass 27, count 0 2006.257.22:39:38.80#ibcon#read 6, iclass 27, count 0 2006.257.22:39:38.80#ibcon#end of sib2, iclass 27, count 0 2006.257.22:39:38.80#ibcon#*mode == 0, iclass 27, count 0 2006.257.22:39:38.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.22:39:38.80#ibcon#[27=USB\r\n] 2006.257.22:39:38.80#ibcon#*before write, iclass 27, count 0 2006.257.22:39:38.80#ibcon#enter sib2, iclass 27, count 0 2006.257.22:39:38.80#ibcon#flushed, iclass 27, count 0 2006.257.22:39:38.80#ibcon#about to write, iclass 27, count 0 2006.257.22:39:38.80#ibcon#wrote, iclass 27, count 0 2006.257.22:39:38.80#ibcon#about to read 3, iclass 27, count 0 2006.257.22:39:38.83#ibcon#read 3, iclass 27, count 0 2006.257.22:39:38.83#ibcon#about to read 4, iclass 27, count 0 2006.257.22:39:38.83#ibcon#read 4, iclass 27, count 0 2006.257.22:39:38.83#ibcon#about to read 5, iclass 27, count 0 2006.257.22:39:38.83#ibcon#read 5, iclass 27, count 0 2006.257.22:39:38.83#ibcon#about to read 6, iclass 27, count 0 2006.257.22:39:38.83#ibcon#read 6, iclass 27, count 0 2006.257.22:39:38.83#ibcon#end of sib2, iclass 27, count 0 2006.257.22:39:38.83#ibcon#*after write, iclass 27, count 0 2006.257.22:39:38.83#ibcon#*before return 0, iclass 27, count 0 2006.257.22:39:38.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:38.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.22:39:38.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.22:39:38.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.22:39:38.83$vck44/vblo=3,649.99 2006.257.22:39:38.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.22:39:38.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.22:39:38.83#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:38.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:38.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:38.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:38.83#ibcon#enter wrdev, iclass 29, count 0 2006.257.22:39:38.83#ibcon#first serial, iclass 29, count 0 2006.257.22:39:38.83#ibcon#enter sib2, iclass 29, count 0 2006.257.22:39:38.83#ibcon#flushed, iclass 29, count 0 2006.257.22:39:38.83#ibcon#about to write, iclass 29, count 0 2006.257.22:39:38.83#ibcon#wrote, iclass 29, count 0 2006.257.22:39:38.83#ibcon#about to read 3, iclass 29, count 0 2006.257.22:39:38.85#ibcon#read 3, iclass 29, count 0 2006.257.22:39:38.85#ibcon#about to read 4, iclass 29, count 0 2006.257.22:39:38.85#ibcon#read 4, iclass 29, count 0 2006.257.22:39:38.85#ibcon#about to read 5, iclass 29, count 0 2006.257.22:39:38.85#ibcon#read 5, iclass 29, count 0 2006.257.22:39:38.85#ibcon#about to read 6, iclass 29, count 0 2006.257.22:39:38.85#ibcon#read 6, iclass 29, count 0 2006.257.22:39:38.85#ibcon#end of sib2, iclass 29, count 0 2006.257.22:39:38.85#ibcon#*mode == 0, iclass 29, count 0 2006.257.22:39:38.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.22:39:38.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.22:39:38.85#ibcon#*before write, iclass 29, count 0 2006.257.22:39:38.85#ibcon#enter sib2, iclass 29, count 0 2006.257.22:39:38.85#ibcon#flushed, iclass 29, count 0 2006.257.22:39:38.85#ibcon#about to write, iclass 29, count 0 2006.257.22:39:38.85#ibcon#wrote, iclass 29, count 0 2006.257.22:39:38.85#ibcon#about to read 3, iclass 29, count 0 2006.257.22:39:38.89#ibcon#read 3, iclass 29, count 0 2006.257.22:39:38.89#ibcon#about to read 4, iclass 29, count 0 2006.257.22:39:38.89#ibcon#read 4, iclass 29, count 0 2006.257.22:39:38.89#ibcon#about to read 5, iclass 29, count 0 2006.257.22:39:38.89#ibcon#read 5, iclass 29, count 0 2006.257.22:39:38.89#ibcon#about to read 6, iclass 29, count 0 2006.257.22:39:38.89#ibcon#read 6, iclass 29, count 0 2006.257.22:39:38.89#ibcon#end of sib2, iclass 29, count 0 2006.257.22:39:38.89#ibcon#*after write, iclass 29, count 0 2006.257.22:39:38.89#ibcon#*before return 0, iclass 29, count 0 2006.257.22:39:38.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:38.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.22:39:38.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.22:39:38.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.22:39:38.89$vck44/vb=3,4 2006.257.22:39:38.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.22:39:38.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.22:39:38.89#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:38.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:38.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:38.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:38.95#ibcon#enter wrdev, iclass 31, count 2 2006.257.22:39:38.95#ibcon#first serial, iclass 31, count 2 2006.257.22:39:38.95#ibcon#enter sib2, iclass 31, count 2 2006.257.22:39:38.95#ibcon#flushed, iclass 31, count 2 2006.257.22:39:38.95#ibcon#about to write, iclass 31, count 2 2006.257.22:39:38.95#ibcon#wrote, iclass 31, count 2 2006.257.22:39:38.95#ibcon#about to read 3, iclass 31, count 2 2006.257.22:39:38.97#ibcon#read 3, iclass 31, count 2 2006.257.22:39:38.97#ibcon#about to read 4, iclass 31, count 2 2006.257.22:39:38.97#ibcon#read 4, iclass 31, count 2 2006.257.22:39:38.97#ibcon#about to read 5, iclass 31, count 2 2006.257.22:39:38.97#ibcon#read 5, iclass 31, count 2 2006.257.22:39:38.97#ibcon#about to read 6, iclass 31, count 2 2006.257.22:39:38.97#ibcon#read 6, iclass 31, count 2 2006.257.22:39:38.97#ibcon#end of sib2, iclass 31, count 2 2006.257.22:39:38.97#ibcon#*mode == 0, iclass 31, count 2 2006.257.22:39:38.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.22:39:38.97#ibcon#[27=AT03-04\r\n] 2006.257.22:39:38.97#ibcon#*before write, iclass 31, count 2 2006.257.22:39:38.97#ibcon#enter sib2, iclass 31, count 2 2006.257.22:39:38.97#ibcon#flushed, iclass 31, count 2 2006.257.22:39:38.97#ibcon#about to write, iclass 31, count 2 2006.257.22:39:38.97#ibcon#wrote, iclass 31, count 2 2006.257.22:39:38.97#ibcon#about to read 3, iclass 31, count 2 2006.257.22:39:39.00#ibcon#read 3, iclass 31, count 2 2006.257.22:39:39.00#ibcon#about to read 4, iclass 31, count 2 2006.257.22:39:39.00#ibcon#read 4, iclass 31, count 2 2006.257.22:39:39.00#ibcon#about to read 5, iclass 31, count 2 2006.257.22:39:39.00#ibcon#read 5, iclass 31, count 2 2006.257.22:39:39.00#ibcon#about to read 6, iclass 31, count 2 2006.257.22:39:39.00#ibcon#read 6, iclass 31, count 2 2006.257.22:39:39.00#ibcon#end of sib2, iclass 31, count 2 2006.257.22:39:39.00#ibcon#*after write, iclass 31, count 2 2006.257.22:39:39.00#ibcon#*before return 0, iclass 31, count 2 2006.257.22:39:39.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:39.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.22:39:39.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.22:39:39.00#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:39.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:39.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:39.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:39.12#ibcon#enter wrdev, iclass 31, count 0 2006.257.22:39:39.12#ibcon#first serial, iclass 31, count 0 2006.257.22:39:39.12#ibcon#enter sib2, iclass 31, count 0 2006.257.22:39:39.12#ibcon#flushed, iclass 31, count 0 2006.257.22:39:39.12#ibcon#about to write, iclass 31, count 0 2006.257.22:39:39.12#ibcon#wrote, iclass 31, count 0 2006.257.22:39:39.12#ibcon#about to read 3, iclass 31, count 0 2006.257.22:39:39.14#ibcon#read 3, iclass 31, count 0 2006.257.22:39:39.14#ibcon#about to read 4, iclass 31, count 0 2006.257.22:39:39.14#ibcon#read 4, iclass 31, count 0 2006.257.22:39:39.14#ibcon#about to read 5, iclass 31, count 0 2006.257.22:39:39.14#ibcon#read 5, iclass 31, count 0 2006.257.22:39:39.14#ibcon#about to read 6, iclass 31, count 0 2006.257.22:39:39.14#ibcon#read 6, iclass 31, count 0 2006.257.22:39:39.14#ibcon#end of sib2, iclass 31, count 0 2006.257.22:39:39.14#ibcon#*mode == 0, iclass 31, count 0 2006.257.22:39:39.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.22:39:39.14#ibcon#[27=USB\r\n] 2006.257.22:39:39.14#ibcon#*before write, iclass 31, count 0 2006.257.22:39:39.14#ibcon#enter sib2, iclass 31, count 0 2006.257.22:39:39.14#ibcon#flushed, iclass 31, count 0 2006.257.22:39:39.14#ibcon#about to write, iclass 31, count 0 2006.257.22:39:39.14#ibcon#wrote, iclass 31, count 0 2006.257.22:39:39.14#ibcon#about to read 3, iclass 31, count 0 2006.257.22:39:39.17#ibcon#read 3, iclass 31, count 0 2006.257.22:39:39.17#ibcon#about to read 4, iclass 31, count 0 2006.257.22:39:39.17#ibcon#read 4, iclass 31, count 0 2006.257.22:39:39.17#ibcon#about to read 5, iclass 31, count 0 2006.257.22:39:39.17#ibcon#read 5, iclass 31, count 0 2006.257.22:39:39.17#ibcon#about to read 6, iclass 31, count 0 2006.257.22:39:39.17#ibcon#read 6, iclass 31, count 0 2006.257.22:39:39.17#ibcon#end of sib2, iclass 31, count 0 2006.257.22:39:39.17#ibcon#*after write, iclass 31, count 0 2006.257.22:39:39.17#ibcon#*before return 0, iclass 31, count 0 2006.257.22:39:39.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:39.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.22:39:39.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.22:39:39.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.22:39:39.17$vck44/vblo=4,679.99 2006.257.22:39:39.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.22:39:39.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.22:39:39.17#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:39.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:39.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:39.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:39.17#ibcon#enter wrdev, iclass 33, count 0 2006.257.22:39:39.17#ibcon#first serial, iclass 33, count 0 2006.257.22:39:39.17#ibcon#enter sib2, iclass 33, count 0 2006.257.22:39:39.17#ibcon#flushed, iclass 33, count 0 2006.257.22:39:39.17#ibcon#about to write, iclass 33, count 0 2006.257.22:39:39.17#ibcon#wrote, iclass 33, count 0 2006.257.22:39:39.17#ibcon#about to read 3, iclass 33, count 0 2006.257.22:39:39.19#ibcon#read 3, iclass 33, count 0 2006.257.22:39:39.19#ibcon#about to read 4, iclass 33, count 0 2006.257.22:39:39.19#ibcon#read 4, iclass 33, count 0 2006.257.22:39:39.19#ibcon#about to read 5, iclass 33, count 0 2006.257.22:39:39.19#ibcon#read 5, iclass 33, count 0 2006.257.22:39:39.19#ibcon#about to read 6, iclass 33, count 0 2006.257.22:39:39.19#ibcon#read 6, iclass 33, count 0 2006.257.22:39:39.19#ibcon#end of sib2, iclass 33, count 0 2006.257.22:39:39.19#ibcon#*mode == 0, iclass 33, count 0 2006.257.22:39:39.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.22:39:39.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.22:39:39.19#ibcon#*before write, iclass 33, count 0 2006.257.22:39:39.19#ibcon#enter sib2, iclass 33, count 0 2006.257.22:39:39.19#ibcon#flushed, iclass 33, count 0 2006.257.22:39:39.19#ibcon#about to write, iclass 33, count 0 2006.257.22:39:39.19#ibcon#wrote, iclass 33, count 0 2006.257.22:39:39.19#ibcon#about to read 3, iclass 33, count 0 2006.257.22:39:39.23#ibcon#read 3, iclass 33, count 0 2006.257.22:39:39.23#ibcon#about to read 4, iclass 33, count 0 2006.257.22:39:39.23#ibcon#read 4, iclass 33, count 0 2006.257.22:39:39.23#ibcon#about to read 5, iclass 33, count 0 2006.257.22:39:39.23#ibcon#read 5, iclass 33, count 0 2006.257.22:39:39.23#ibcon#about to read 6, iclass 33, count 0 2006.257.22:39:39.23#ibcon#read 6, iclass 33, count 0 2006.257.22:39:39.23#ibcon#end of sib2, iclass 33, count 0 2006.257.22:39:39.23#ibcon#*after write, iclass 33, count 0 2006.257.22:39:39.23#ibcon#*before return 0, iclass 33, count 0 2006.257.22:39:39.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:39.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.22:39:39.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.22:39:39.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.22:39:39.23$vck44/vb=4,5 2006.257.22:39:39.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.22:39:39.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.22:39:39.23#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:39.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:39.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:39.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:39.29#ibcon#enter wrdev, iclass 35, count 2 2006.257.22:39:39.29#ibcon#first serial, iclass 35, count 2 2006.257.22:39:39.29#ibcon#enter sib2, iclass 35, count 2 2006.257.22:39:39.29#ibcon#flushed, iclass 35, count 2 2006.257.22:39:39.29#ibcon#about to write, iclass 35, count 2 2006.257.22:39:39.29#ibcon#wrote, iclass 35, count 2 2006.257.22:39:39.29#ibcon#about to read 3, iclass 35, count 2 2006.257.22:39:39.31#ibcon#read 3, iclass 35, count 2 2006.257.22:39:39.31#ibcon#about to read 4, iclass 35, count 2 2006.257.22:39:39.31#ibcon#read 4, iclass 35, count 2 2006.257.22:39:39.31#ibcon#about to read 5, iclass 35, count 2 2006.257.22:39:39.31#ibcon#read 5, iclass 35, count 2 2006.257.22:39:39.31#ibcon#about to read 6, iclass 35, count 2 2006.257.22:39:39.31#ibcon#read 6, iclass 35, count 2 2006.257.22:39:39.31#ibcon#end of sib2, iclass 35, count 2 2006.257.22:39:39.31#ibcon#*mode == 0, iclass 35, count 2 2006.257.22:39:39.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.22:39:39.31#ibcon#[27=AT04-05\r\n] 2006.257.22:39:39.31#ibcon#*before write, iclass 35, count 2 2006.257.22:39:39.31#ibcon#enter sib2, iclass 35, count 2 2006.257.22:39:39.31#ibcon#flushed, iclass 35, count 2 2006.257.22:39:39.31#ibcon#about to write, iclass 35, count 2 2006.257.22:39:39.31#ibcon#wrote, iclass 35, count 2 2006.257.22:39:39.31#ibcon#about to read 3, iclass 35, count 2 2006.257.22:39:39.34#ibcon#read 3, iclass 35, count 2 2006.257.22:39:39.34#ibcon#about to read 4, iclass 35, count 2 2006.257.22:39:39.34#ibcon#read 4, iclass 35, count 2 2006.257.22:39:39.34#ibcon#about to read 5, iclass 35, count 2 2006.257.22:39:39.34#ibcon#read 5, iclass 35, count 2 2006.257.22:39:39.34#ibcon#about to read 6, iclass 35, count 2 2006.257.22:39:39.34#ibcon#read 6, iclass 35, count 2 2006.257.22:39:39.34#ibcon#end of sib2, iclass 35, count 2 2006.257.22:39:39.34#ibcon#*after write, iclass 35, count 2 2006.257.22:39:39.34#ibcon#*before return 0, iclass 35, count 2 2006.257.22:39:39.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:39.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.22:39:39.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.22:39:39.34#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:39.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:39.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:39.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:39.46#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:39:39.46#ibcon#first serial, iclass 35, count 0 2006.257.22:39:39.46#ibcon#enter sib2, iclass 35, count 0 2006.257.22:39:39.46#ibcon#flushed, iclass 35, count 0 2006.257.22:39:39.46#ibcon#about to write, iclass 35, count 0 2006.257.22:39:39.46#ibcon#wrote, iclass 35, count 0 2006.257.22:39:39.46#ibcon#about to read 3, iclass 35, count 0 2006.257.22:39:39.48#ibcon#read 3, iclass 35, count 0 2006.257.22:39:39.48#ibcon#about to read 4, iclass 35, count 0 2006.257.22:39:39.48#ibcon#read 4, iclass 35, count 0 2006.257.22:39:39.48#ibcon#about to read 5, iclass 35, count 0 2006.257.22:39:39.48#ibcon#read 5, iclass 35, count 0 2006.257.22:39:39.48#ibcon#about to read 6, iclass 35, count 0 2006.257.22:39:39.48#ibcon#read 6, iclass 35, count 0 2006.257.22:39:39.48#ibcon#end of sib2, iclass 35, count 0 2006.257.22:39:39.48#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:39:39.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:39:39.48#ibcon#[27=USB\r\n] 2006.257.22:39:39.48#ibcon#*before write, iclass 35, count 0 2006.257.22:39:39.48#ibcon#enter sib2, iclass 35, count 0 2006.257.22:39:39.48#ibcon#flushed, iclass 35, count 0 2006.257.22:39:39.48#ibcon#about to write, iclass 35, count 0 2006.257.22:39:39.48#ibcon#wrote, iclass 35, count 0 2006.257.22:39:39.48#ibcon#about to read 3, iclass 35, count 0 2006.257.22:39:39.51#ibcon#read 3, iclass 35, count 0 2006.257.22:39:39.51#ibcon#about to read 4, iclass 35, count 0 2006.257.22:39:39.51#ibcon#read 4, iclass 35, count 0 2006.257.22:39:39.51#ibcon#about to read 5, iclass 35, count 0 2006.257.22:39:39.51#ibcon#read 5, iclass 35, count 0 2006.257.22:39:39.51#ibcon#about to read 6, iclass 35, count 0 2006.257.22:39:39.51#ibcon#read 6, iclass 35, count 0 2006.257.22:39:39.51#ibcon#end of sib2, iclass 35, count 0 2006.257.22:39:39.51#ibcon#*after write, iclass 35, count 0 2006.257.22:39:39.51#ibcon#*before return 0, iclass 35, count 0 2006.257.22:39:39.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:39.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.22:39:39.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:39:39.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:39:39.51$vck44/vblo=5,709.99 2006.257.22:39:39.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.22:39:39.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.22:39:39.51#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:39.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:39.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:39.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:39.51#ibcon#enter wrdev, iclass 37, count 0 2006.257.22:39:39.51#ibcon#first serial, iclass 37, count 0 2006.257.22:39:39.51#ibcon#enter sib2, iclass 37, count 0 2006.257.22:39:39.51#ibcon#flushed, iclass 37, count 0 2006.257.22:39:39.51#ibcon#about to write, iclass 37, count 0 2006.257.22:39:39.51#ibcon#wrote, iclass 37, count 0 2006.257.22:39:39.51#ibcon#about to read 3, iclass 37, count 0 2006.257.22:39:39.53#ibcon#read 3, iclass 37, count 0 2006.257.22:39:39.53#ibcon#about to read 4, iclass 37, count 0 2006.257.22:39:39.53#ibcon#read 4, iclass 37, count 0 2006.257.22:39:39.53#ibcon#about to read 5, iclass 37, count 0 2006.257.22:39:39.53#ibcon#read 5, iclass 37, count 0 2006.257.22:39:39.53#ibcon#about to read 6, iclass 37, count 0 2006.257.22:39:39.53#ibcon#read 6, iclass 37, count 0 2006.257.22:39:39.53#ibcon#end of sib2, iclass 37, count 0 2006.257.22:39:39.53#ibcon#*mode == 0, iclass 37, count 0 2006.257.22:39:39.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.22:39:39.53#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.22:39:39.53#ibcon#*before write, iclass 37, count 0 2006.257.22:39:39.53#ibcon#enter sib2, iclass 37, count 0 2006.257.22:39:39.53#ibcon#flushed, iclass 37, count 0 2006.257.22:39:39.53#ibcon#about to write, iclass 37, count 0 2006.257.22:39:39.53#ibcon#wrote, iclass 37, count 0 2006.257.22:39:39.53#ibcon#about to read 3, iclass 37, count 0 2006.257.22:39:39.57#ibcon#read 3, iclass 37, count 0 2006.257.22:39:39.57#ibcon#about to read 4, iclass 37, count 0 2006.257.22:39:39.57#ibcon#read 4, iclass 37, count 0 2006.257.22:39:39.57#ibcon#about to read 5, iclass 37, count 0 2006.257.22:39:39.57#ibcon#read 5, iclass 37, count 0 2006.257.22:39:39.57#ibcon#about to read 6, iclass 37, count 0 2006.257.22:39:39.57#ibcon#read 6, iclass 37, count 0 2006.257.22:39:39.57#ibcon#end of sib2, iclass 37, count 0 2006.257.22:39:39.57#ibcon#*after write, iclass 37, count 0 2006.257.22:39:39.57#ibcon#*before return 0, iclass 37, count 0 2006.257.22:39:39.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:39.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.22:39:39.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.22:39:39.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.22:39:39.57$vck44/vb=5,4 2006.257.22:39:39.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.22:39:39.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.22:39:39.57#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:39.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:39.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:39.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:39.63#ibcon#enter wrdev, iclass 39, count 2 2006.257.22:39:39.63#ibcon#first serial, iclass 39, count 2 2006.257.22:39:39.63#ibcon#enter sib2, iclass 39, count 2 2006.257.22:39:39.63#ibcon#flushed, iclass 39, count 2 2006.257.22:39:39.63#ibcon#about to write, iclass 39, count 2 2006.257.22:39:39.63#ibcon#wrote, iclass 39, count 2 2006.257.22:39:39.63#ibcon#about to read 3, iclass 39, count 2 2006.257.22:39:39.65#ibcon#read 3, iclass 39, count 2 2006.257.22:39:39.65#ibcon#about to read 4, iclass 39, count 2 2006.257.22:39:39.65#ibcon#read 4, iclass 39, count 2 2006.257.22:39:39.65#ibcon#about to read 5, iclass 39, count 2 2006.257.22:39:39.65#ibcon#read 5, iclass 39, count 2 2006.257.22:39:39.65#ibcon#about to read 6, iclass 39, count 2 2006.257.22:39:39.65#ibcon#read 6, iclass 39, count 2 2006.257.22:39:39.65#ibcon#end of sib2, iclass 39, count 2 2006.257.22:39:39.65#ibcon#*mode == 0, iclass 39, count 2 2006.257.22:39:39.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.22:39:39.65#ibcon#[27=AT05-04\r\n] 2006.257.22:39:39.65#ibcon#*before write, iclass 39, count 2 2006.257.22:39:39.65#ibcon#enter sib2, iclass 39, count 2 2006.257.22:39:39.65#ibcon#flushed, iclass 39, count 2 2006.257.22:39:39.65#ibcon#about to write, iclass 39, count 2 2006.257.22:39:39.65#ibcon#wrote, iclass 39, count 2 2006.257.22:39:39.65#ibcon#about to read 3, iclass 39, count 2 2006.257.22:39:39.68#ibcon#read 3, iclass 39, count 2 2006.257.22:39:39.68#ibcon#about to read 4, iclass 39, count 2 2006.257.22:39:39.68#ibcon#read 4, iclass 39, count 2 2006.257.22:39:39.68#ibcon#about to read 5, iclass 39, count 2 2006.257.22:39:39.68#ibcon#read 5, iclass 39, count 2 2006.257.22:39:39.68#ibcon#about to read 6, iclass 39, count 2 2006.257.22:39:39.68#ibcon#read 6, iclass 39, count 2 2006.257.22:39:39.68#ibcon#end of sib2, iclass 39, count 2 2006.257.22:39:39.68#ibcon#*after write, iclass 39, count 2 2006.257.22:39:39.68#ibcon#*before return 0, iclass 39, count 2 2006.257.22:39:39.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:39.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.22:39:39.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.22:39:39.68#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:39.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:39.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:39.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:39.80#ibcon#enter wrdev, iclass 39, count 0 2006.257.22:39:39.80#ibcon#first serial, iclass 39, count 0 2006.257.22:39:39.80#ibcon#enter sib2, iclass 39, count 0 2006.257.22:39:39.80#ibcon#flushed, iclass 39, count 0 2006.257.22:39:39.80#ibcon#about to write, iclass 39, count 0 2006.257.22:39:39.80#ibcon#wrote, iclass 39, count 0 2006.257.22:39:39.80#ibcon#about to read 3, iclass 39, count 0 2006.257.22:39:39.82#ibcon#read 3, iclass 39, count 0 2006.257.22:39:39.82#ibcon#about to read 4, iclass 39, count 0 2006.257.22:39:39.82#ibcon#read 4, iclass 39, count 0 2006.257.22:39:39.82#ibcon#about to read 5, iclass 39, count 0 2006.257.22:39:39.82#ibcon#read 5, iclass 39, count 0 2006.257.22:39:39.82#ibcon#about to read 6, iclass 39, count 0 2006.257.22:39:39.82#ibcon#read 6, iclass 39, count 0 2006.257.22:39:39.82#ibcon#end of sib2, iclass 39, count 0 2006.257.22:39:39.82#ibcon#*mode == 0, iclass 39, count 0 2006.257.22:39:39.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.22:39:39.82#ibcon#[27=USB\r\n] 2006.257.22:39:39.82#ibcon#*before write, iclass 39, count 0 2006.257.22:39:39.82#ibcon#enter sib2, iclass 39, count 0 2006.257.22:39:39.82#ibcon#flushed, iclass 39, count 0 2006.257.22:39:39.82#ibcon#about to write, iclass 39, count 0 2006.257.22:39:39.82#ibcon#wrote, iclass 39, count 0 2006.257.22:39:39.82#ibcon#about to read 3, iclass 39, count 0 2006.257.22:39:39.85#ibcon#read 3, iclass 39, count 0 2006.257.22:39:39.85#ibcon#about to read 4, iclass 39, count 0 2006.257.22:39:39.85#ibcon#read 4, iclass 39, count 0 2006.257.22:39:39.85#ibcon#about to read 5, iclass 39, count 0 2006.257.22:39:39.85#ibcon#read 5, iclass 39, count 0 2006.257.22:39:39.85#ibcon#about to read 6, iclass 39, count 0 2006.257.22:39:39.85#ibcon#read 6, iclass 39, count 0 2006.257.22:39:39.85#ibcon#end of sib2, iclass 39, count 0 2006.257.22:39:39.85#ibcon#*after write, iclass 39, count 0 2006.257.22:39:39.85#ibcon#*before return 0, iclass 39, count 0 2006.257.22:39:39.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:39.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.22:39:39.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.22:39:39.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.22:39:39.85$vck44/vblo=6,719.99 2006.257.22:39:39.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.22:39:39.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.22:39:39.85#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:39.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:39.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:39.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:39.85#ibcon#enter wrdev, iclass 3, count 0 2006.257.22:39:39.85#ibcon#first serial, iclass 3, count 0 2006.257.22:39:39.85#ibcon#enter sib2, iclass 3, count 0 2006.257.22:39:39.85#ibcon#flushed, iclass 3, count 0 2006.257.22:39:39.85#ibcon#about to write, iclass 3, count 0 2006.257.22:39:39.85#ibcon#wrote, iclass 3, count 0 2006.257.22:39:39.85#ibcon#about to read 3, iclass 3, count 0 2006.257.22:39:39.87#ibcon#read 3, iclass 3, count 0 2006.257.22:39:39.87#ibcon#about to read 4, iclass 3, count 0 2006.257.22:39:39.87#ibcon#read 4, iclass 3, count 0 2006.257.22:39:39.87#ibcon#about to read 5, iclass 3, count 0 2006.257.22:39:39.87#ibcon#read 5, iclass 3, count 0 2006.257.22:39:39.87#ibcon#about to read 6, iclass 3, count 0 2006.257.22:39:39.87#ibcon#read 6, iclass 3, count 0 2006.257.22:39:39.87#ibcon#end of sib2, iclass 3, count 0 2006.257.22:39:39.87#ibcon#*mode == 0, iclass 3, count 0 2006.257.22:39:39.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.22:39:39.87#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.22:39:39.87#ibcon#*before write, iclass 3, count 0 2006.257.22:39:39.87#ibcon#enter sib2, iclass 3, count 0 2006.257.22:39:39.87#ibcon#flushed, iclass 3, count 0 2006.257.22:39:39.87#ibcon#about to write, iclass 3, count 0 2006.257.22:39:39.87#ibcon#wrote, iclass 3, count 0 2006.257.22:39:39.87#ibcon#about to read 3, iclass 3, count 0 2006.257.22:39:39.91#ibcon#read 3, iclass 3, count 0 2006.257.22:39:39.91#ibcon#about to read 4, iclass 3, count 0 2006.257.22:39:39.91#ibcon#read 4, iclass 3, count 0 2006.257.22:39:39.91#ibcon#about to read 5, iclass 3, count 0 2006.257.22:39:39.91#ibcon#read 5, iclass 3, count 0 2006.257.22:39:39.91#ibcon#about to read 6, iclass 3, count 0 2006.257.22:39:39.91#ibcon#read 6, iclass 3, count 0 2006.257.22:39:39.91#ibcon#end of sib2, iclass 3, count 0 2006.257.22:39:39.91#ibcon#*after write, iclass 3, count 0 2006.257.22:39:39.91#ibcon#*before return 0, iclass 3, count 0 2006.257.22:39:39.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:39.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.22:39:39.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.22:39:39.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.22:39:39.91$vck44/vb=6,4 2006.257.22:39:39.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.22:39:39.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.22:39:39.91#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:39.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:39.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:39.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:39.97#ibcon#enter wrdev, iclass 5, count 2 2006.257.22:39:39.97#ibcon#first serial, iclass 5, count 2 2006.257.22:39:39.97#ibcon#enter sib2, iclass 5, count 2 2006.257.22:39:39.97#ibcon#flushed, iclass 5, count 2 2006.257.22:39:39.97#ibcon#about to write, iclass 5, count 2 2006.257.22:39:39.97#ibcon#wrote, iclass 5, count 2 2006.257.22:39:39.97#ibcon#about to read 3, iclass 5, count 2 2006.257.22:39:39.99#ibcon#read 3, iclass 5, count 2 2006.257.22:39:39.99#ibcon#about to read 4, iclass 5, count 2 2006.257.22:39:39.99#ibcon#read 4, iclass 5, count 2 2006.257.22:39:39.99#ibcon#about to read 5, iclass 5, count 2 2006.257.22:39:39.99#ibcon#read 5, iclass 5, count 2 2006.257.22:39:39.99#ibcon#about to read 6, iclass 5, count 2 2006.257.22:39:39.99#ibcon#read 6, iclass 5, count 2 2006.257.22:39:39.99#ibcon#end of sib2, iclass 5, count 2 2006.257.22:39:39.99#ibcon#*mode == 0, iclass 5, count 2 2006.257.22:39:39.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.22:39:39.99#ibcon#[27=AT06-04\r\n] 2006.257.22:39:39.99#ibcon#*before write, iclass 5, count 2 2006.257.22:39:39.99#ibcon#enter sib2, iclass 5, count 2 2006.257.22:39:39.99#ibcon#flushed, iclass 5, count 2 2006.257.22:39:39.99#ibcon#about to write, iclass 5, count 2 2006.257.22:39:39.99#ibcon#wrote, iclass 5, count 2 2006.257.22:39:39.99#ibcon#about to read 3, iclass 5, count 2 2006.257.22:39:40.02#ibcon#read 3, iclass 5, count 2 2006.257.22:39:40.02#ibcon#about to read 4, iclass 5, count 2 2006.257.22:39:40.02#ibcon#read 4, iclass 5, count 2 2006.257.22:39:40.02#ibcon#about to read 5, iclass 5, count 2 2006.257.22:39:40.02#ibcon#read 5, iclass 5, count 2 2006.257.22:39:40.02#ibcon#about to read 6, iclass 5, count 2 2006.257.22:39:40.02#ibcon#read 6, iclass 5, count 2 2006.257.22:39:40.02#ibcon#end of sib2, iclass 5, count 2 2006.257.22:39:40.02#ibcon#*after write, iclass 5, count 2 2006.257.22:39:40.02#ibcon#*before return 0, iclass 5, count 2 2006.257.22:39:40.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:40.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.22:39:40.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.22:39:40.02#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:40.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:40.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:40.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:40.14#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:39:40.14#ibcon#first serial, iclass 5, count 0 2006.257.22:39:40.14#ibcon#enter sib2, iclass 5, count 0 2006.257.22:39:40.14#ibcon#flushed, iclass 5, count 0 2006.257.22:39:40.14#ibcon#about to write, iclass 5, count 0 2006.257.22:39:40.14#ibcon#wrote, iclass 5, count 0 2006.257.22:39:40.14#ibcon#about to read 3, iclass 5, count 0 2006.257.22:39:40.16#ibcon#read 3, iclass 5, count 0 2006.257.22:39:40.16#ibcon#about to read 4, iclass 5, count 0 2006.257.22:39:40.16#ibcon#read 4, iclass 5, count 0 2006.257.22:39:40.16#ibcon#about to read 5, iclass 5, count 0 2006.257.22:39:40.16#ibcon#read 5, iclass 5, count 0 2006.257.22:39:40.16#ibcon#about to read 6, iclass 5, count 0 2006.257.22:39:40.16#ibcon#read 6, iclass 5, count 0 2006.257.22:39:40.16#ibcon#end of sib2, iclass 5, count 0 2006.257.22:39:40.16#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:39:40.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:39:40.16#ibcon#[27=USB\r\n] 2006.257.22:39:40.16#ibcon#*before write, iclass 5, count 0 2006.257.22:39:40.16#ibcon#enter sib2, iclass 5, count 0 2006.257.22:39:40.16#ibcon#flushed, iclass 5, count 0 2006.257.22:39:40.16#ibcon#about to write, iclass 5, count 0 2006.257.22:39:40.16#ibcon#wrote, iclass 5, count 0 2006.257.22:39:40.16#ibcon#about to read 3, iclass 5, count 0 2006.257.22:39:40.19#ibcon#read 3, iclass 5, count 0 2006.257.22:39:40.19#ibcon#about to read 4, iclass 5, count 0 2006.257.22:39:40.19#ibcon#read 4, iclass 5, count 0 2006.257.22:39:40.19#ibcon#about to read 5, iclass 5, count 0 2006.257.22:39:40.19#ibcon#read 5, iclass 5, count 0 2006.257.22:39:40.19#ibcon#about to read 6, iclass 5, count 0 2006.257.22:39:40.19#ibcon#read 6, iclass 5, count 0 2006.257.22:39:40.19#ibcon#end of sib2, iclass 5, count 0 2006.257.22:39:40.19#ibcon#*after write, iclass 5, count 0 2006.257.22:39:40.19#ibcon#*before return 0, iclass 5, count 0 2006.257.22:39:40.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:40.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.22:39:40.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:39:40.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:39:40.19$vck44/vblo=7,734.99 2006.257.22:39:40.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.22:39:40.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.22:39:40.19#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:40.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:40.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:40.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:40.19#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:39:40.19#ibcon#first serial, iclass 7, count 0 2006.257.22:39:40.19#ibcon#enter sib2, iclass 7, count 0 2006.257.22:39:40.19#ibcon#flushed, iclass 7, count 0 2006.257.22:39:40.19#ibcon#about to write, iclass 7, count 0 2006.257.22:39:40.19#ibcon#wrote, iclass 7, count 0 2006.257.22:39:40.19#ibcon#about to read 3, iclass 7, count 0 2006.257.22:39:40.21#ibcon#read 3, iclass 7, count 0 2006.257.22:39:40.21#ibcon#about to read 4, iclass 7, count 0 2006.257.22:39:40.21#ibcon#read 4, iclass 7, count 0 2006.257.22:39:40.21#ibcon#about to read 5, iclass 7, count 0 2006.257.22:39:40.21#ibcon#read 5, iclass 7, count 0 2006.257.22:39:40.21#ibcon#about to read 6, iclass 7, count 0 2006.257.22:39:40.21#ibcon#read 6, iclass 7, count 0 2006.257.22:39:40.21#ibcon#end of sib2, iclass 7, count 0 2006.257.22:39:40.21#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:39:40.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:39:40.21#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.22:39:40.21#ibcon#*before write, iclass 7, count 0 2006.257.22:39:40.21#ibcon#enter sib2, iclass 7, count 0 2006.257.22:39:40.21#ibcon#flushed, iclass 7, count 0 2006.257.22:39:40.21#ibcon#about to write, iclass 7, count 0 2006.257.22:39:40.21#ibcon#wrote, iclass 7, count 0 2006.257.22:39:40.21#ibcon#about to read 3, iclass 7, count 0 2006.257.22:39:40.25#ibcon#read 3, iclass 7, count 0 2006.257.22:39:40.25#ibcon#about to read 4, iclass 7, count 0 2006.257.22:39:40.25#ibcon#read 4, iclass 7, count 0 2006.257.22:39:40.25#ibcon#about to read 5, iclass 7, count 0 2006.257.22:39:40.25#ibcon#read 5, iclass 7, count 0 2006.257.22:39:40.25#ibcon#about to read 6, iclass 7, count 0 2006.257.22:39:40.25#ibcon#read 6, iclass 7, count 0 2006.257.22:39:40.25#ibcon#end of sib2, iclass 7, count 0 2006.257.22:39:40.25#ibcon#*after write, iclass 7, count 0 2006.257.22:39:40.25#ibcon#*before return 0, iclass 7, count 0 2006.257.22:39:40.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:40.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.22:39:40.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:39:40.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:39:40.25$vck44/vb=7,4 2006.257.22:39:40.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.22:39:40.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.22:39:40.25#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:40.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:40.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:40.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:40.31#ibcon#enter wrdev, iclass 11, count 2 2006.257.22:39:40.31#ibcon#first serial, iclass 11, count 2 2006.257.22:39:40.31#ibcon#enter sib2, iclass 11, count 2 2006.257.22:39:40.31#ibcon#flushed, iclass 11, count 2 2006.257.22:39:40.31#ibcon#about to write, iclass 11, count 2 2006.257.22:39:40.31#ibcon#wrote, iclass 11, count 2 2006.257.22:39:40.31#ibcon#about to read 3, iclass 11, count 2 2006.257.22:39:40.33#ibcon#read 3, iclass 11, count 2 2006.257.22:39:40.33#ibcon#about to read 4, iclass 11, count 2 2006.257.22:39:40.33#ibcon#read 4, iclass 11, count 2 2006.257.22:39:40.33#ibcon#about to read 5, iclass 11, count 2 2006.257.22:39:40.33#ibcon#read 5, iclass 11, count 2 2006.257.22:39:40.33#ibcon#about to read 6, iclass 11, count 2 2006.257.22:39:40.33#ibcon#read 6, iclass 11, count 2 2006.257.22:39:40.33#ibcon#end of sib2, iclass 11, count 2 2006.257.22:39:40.33#ibcon#*mode == 0, iclass 11, count 2 2006.257.22:39:40.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.22:39:40.33#ibcon#[27=AT07-04\r\n] 2006.257.22:39:40.33#ibcon#*before write, iclass 11, count 2 2006.257.22:39:40.33#ibcon#enter sib2, iclass 11, count 2 2006.257.22:39:40.33#ibcon#flushed, iclass 11, count 2 2006.257.22:39:40.33#ibcon#about to write, iclass 11, count 2 2006.257.22:39:40.33#ibcon#wrote, iclass 11, count 2 2006.257.22:39:40.33#ibcon#about to read 3, iclass 11, count 2 2006.257.22:39:40.36#ibcon#read 3, iclass 11, count 2 2006.257.22:39:40.36#ibcon#about to read 4, iclass 11, count 2 2006.257.22:39:40.36#ibcon#read 4, iclass 11, count 2 2006.257.22:39:40.36#ibcon#about to read 5, iclass 11, count 2 2006.257.22:39:40.36#ibcon#read 5, iclass 11, count 2 2006.257.22:39:40.36#ibcon#about to read 6, iclass 11, count 2 2006.257.22:39:40.36#ibcon#read 6, iclass 11, count 2 2006.257.22:39:40.36#ibcon#end of sib2, iclass 11, count 2 2006.257.22:39:40.36#ibcon#*after write, iclass 11, count 2 2006.257.22:39:40.36#ibcon#*before return 0, iclass 11, count 2 2006.257.22:39:40.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:40.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.22:39:40.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.22:39:40.36#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:40.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:40.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:40.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:40.48#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:39:40.48#ibcon#first serial, iclass 11, count 0 2006.257.22:39:40.48#ibcon#enter sib2, iclass 11, count 0 2006.257.22:39:40.48#ibcon#flushed, iclass 11, count 0 2006.257.22:39:40.48#ibcon#about to write, iclass 11, count 0 2006.257.22:39:40.48#ibcon#wrote, iclass 11, count 0 2006.257.22:39:40.48#ibcon#about to read 3, iclass 11, count 0 2006.257.22:39:40.50#ibcon#read 3, iclass 11, count 0 2006.257.22:39:40.50#ibcon#about to read 4, iclass 11, count 0 2006.257.22:39:40.50#ibcon#read 4, iclass 11, count 0 2006.257.22:39:40.50#ibcon#about to read 5, iclass 11, count 0 2006.257.22:39:40.50#ibcon#read 5, iclass 11, count 0 2006.257.22:39:40.50#ibcon#about to read 6, iclass 11, count 0 2006.257.22:39:40.50#ibcon#read 6, iclass 11, count 0 2006.257.22:39:40.50#ibcon#end of sib2, iclass 11, count 0 2006.257.22:39:40.50#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:39:40.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:39:40.50#ibcon#[27=USB\r\n] 2006.257.22:39:40.50#ibcon#*before write, iclass 11, count 0 2006.257.22:39:40.50#ibcon#enter sib2, iclass 11, count 0 2006.257.22:39:40.50#ibcon#flushed, iclass 11, count 0 2006.257.22:39:40.50#ibcon#about to write, iclass 11, count 0 2006.257.22:39:40.50#ibcon#wrote, iclass 11, count 0 2006.257.22:39:40.50#ibcon#about to read 3, iclass 11, count 0 2006.257.22:39:40.53#ibcon#read 3, iclass 11, count 0 2006.257.22:39:40.53#ibcon#about to read 4, iclass 11, count 0 2006.257.22:39:40.53#ibcon#read 4, iclass 11, count 0 2006.257.22:39:40.53#ibcon#about to read 5, iclass 11, count 0 2006.257.22:39:40.53#ibcon#read 5, iclass 11, count 0 2006.257.22:39:40.53#ibcon#about to read 6, iclass 11, count 0 2006.257.22:39:40.53#ibcon#read 6, iclass 11, count 0 2006.257.22:39:40.53#ibcon#end of sib2, iclass 11, count 0 2006.257.22:39:40.53#ibcon#*after write, iclass 11, count 0 2006.257.22:39:40.53#ibcon#*before return 0, iclass 11, count 0 2006.257.22:39:40.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:40.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.22:39:40.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:39:40.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:39:40.53$vck44/vblo=8,744.99 2006.257.22:39:40.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.22:39:40.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.22:39:40.53#ibcon#ireg 17 cls_cnt 0 2006.257.22:39:40.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:40.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:40.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:40.53#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:39:40.53#ibcon#first serial, iclass 13, count 0 2006.257.22:39:40.53#ibcon#enter sib2, iclass 13, count 0 2006.257.22:39:40.53#ibcon#flushed, iclass 13, count 0 2006.257.22:39:40.53#ibcon#about to write, iclass 13, count 0 2006.257.22:39:40.53#ibcon#wrote, iclass 13, count 0 2006.257.22:39:40.53#ibcon#about to read 3, iclass 13, count 0 2006.257.22:39:40.55#ibcon#read 3, iclass 13, count 0 2006.257.22:39:40.55#ibcon#about to read 4, iclass 13, count 0 2006.257.22:39:40.55#ibcon#read 4, iclass 13, count 0 2006.257.22:39:40.55#ibcon#about to read 5, iclass 13, count 0 2006.257.22:39:40.55#ibcon#read 5, iclass 13, count 0 2006.257.22:39:40.55#ibcon#about to read 6, iclass 13, count 0 2006.257.22:39:40.55#ibcon#read 6, iclass 13, count 0 2006.257.22:39:40.55#ibcon#end of sib2, iclass 13, count 0 2006.257.22:39:40.55#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:39:40.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:39:40.55#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.22:39:40.55#ibcon#*before write, iclass 13, count 0 2006.257.22:39:40.55#ibcon#enter sib2, iclass 13, count 0 2006.257.22:39:40.55#ibcon#flushed, iclass 13, count 0 2006.257.22:39:40.55#ibcon#about to write, iclass 13, count 0 2006.257.22:39:40.55#ibcon#wrote, iclass 13, count 0 2006.257.22:39:40.55#ibcon#about to read 3, iclass 13, count 0 2006.257.22:39:40.59#ibcon#read 3, iclass 13, count 0 2006.257.22:39:40.59#ibcon#about to read 4, iclass 13, count 0 2006.257.22:39:40.59#ibcon#read 4, iclass 13, count 0 2006.257.22:39:40.59#ibcon#about to read 5, iclass 13, count 0 2006.257.22:39:40.59#ibcon#read 5, iclass 13, count 0 2006.257.22:39:40.59#ibcon#about to read 6, iclass 13, count 0 2006.257.22:39:40.59#ibcon#read 6, iclass 13, count 0 2006.257.22:39:40.59#ibcon#end of sib2, iclass 13, count 0 2006.257.22:39:40.59#ibcon#*after write, iclass 13, count 0 2006.257.22:39:40.59#ibcon#*before return 0, iclass 13, count 0 2006.257.22:39:40.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:40.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.22:39:40.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:39:40.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:39:40.59$vck44/vb=8,4 2006.257.22:39:40.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.22:39:40.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.22:39:40.59#ibcon#ireg 11 cls_cnt 2 2006.257.22:39:40.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:40.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:40.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:40.65#ibcon#enter wrdev, iclass 15, count 2 2006.257.22:39:40.65#ibcon#first serial, iclass 15, count 2 2006.257.22:39:40.65#ibcon#enter sib2, iclass 15, count 2 2006.257.22:39:40.65#ibcon#flushed, iclass 15, count 2 2006.257.22:39:40.65#ibcon#about to write, iclass 15, count 2 2006.257.22:39:40.65#ibcon#wrote, iclass 15, count 2 2006.257.22:39:40.65#ibcon#about to read 3, iclass 15, count 2 2006.257.22:39:40.67#ibcon#read 3, iclass 15, count 2 2006.257.22:39:40.67#ibcon#about to read 4, iclass 15, count 2 2006.257.22:39:40.67#ibcon#read 4, iclass 15, count 2 2006.257.22:39:40.67#ibcon#about to read 5, iclass 15, count 2 2006.257.22:39:40.67#ibcon#read 5, iclass 15, count 2 2006.257.22:39:40.67#ibcon#about to read 6, iclass 15, count 2 2006.257.22:39:40.67#ibcon#read 6, iclass 15, count 2 2006.257.22:39:40.67#ibcon#end of sib2, iclass 15, count 2 2006.257.22:39:40.67#ibcon#*mode == 0, iclass 15, count 2 2006.257.22:39:40.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.22:39:40.67#ibcon#[27=AT08-04\r\n] 2006.257.22:39:40.67#ibcon#*before write, iclass 15, count 2 2006.257.22:39:40.67#ibcon#enter sib2, iclass 15, count 2 2006.257.22:39:40.67#ibcon#flushed, iclass 15, count 2 2006.257.22:39:40.67#ibcon#about to write, iclass 15, count 2 2006.257.22:39:40.67#ibcon#wrote, iclass 15, count 2 2006.257.22:39:40.67#ibcon#about to read 3, iclass 15, count 2 2006.257.22:39:40.70#ibcon#read 3, iclass 15, count 2 2006.257.22:39:40.70#ibcon#about to read 4, iclass 15, count 2 2006.257.22:39:40.70#ibcon#read 4, iclass 15, count 2 2006.257.22:39:40.70#ibcon#about to read 5, iclass 15, count 2 2006.257.22:39:40.70#ibcon#read 5, iclass 15, count 2 2006.257.22:39:40.70#ibcon#about to read 6, iclass 15, count 2 2006.257.22:39:40.70#ibcon#read 6, iclass 15, count 2 2006.257.22:39:40.70#ibcon#end of sib2, iclass 15, count 2 2006.257.22:39:40.70#ibcon#*after write, iclass 15, count 2 2006.257.22:39:40.70#ibcon#*before return 0, iclass 15, count 2 2006.257.22:39:40.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:40.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.22:39:40.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.22:39:40.70#ibcon#ireg 7 cls_cnt 0 2006.257.22:39:40.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:40.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:40.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:40.82#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:39:40.82#ibcon#first serial, iclass 15, count 0 2006.257.22:39:40.82#ibcon#enter sib2, iclass 15, count 0 2006.257.22:39:40.82#ibcon#flushed, iclass 15, count 0 2006.257.22:39:40.82#ibcon#about to write, iclass 15, count 0 2006.257.22:39:40.82#ibcon#wrote, iclass 15, count 0 2006.257.22:39:40.82#ibcon#about to read 3, iclass 15, count 0 2006.257.22:39:40.84#ibcon#read 3, iclass 15, count 0 2006.257.22:39:40.84#ibcon#about to read 4, iclass 15, count 0 2006.257.22:39:40.84#ibcon#read 4, iclass 15, count 0 2006.257.22:39:40.84#ibcon#about to read 5, iclass 15, count 0 2006.257.22:39:40.84#ibcon#read 5, iclass 15, count 0 2006.257.22:39:40.84#ibcon#about to read 6, iclass 15, count 0 2006.257.22:39:40.84#ibcon#read 6, iclass 15, count 0 2006.257.22:39:40.84#ibcon#end of sib2, iclass 15, count 0 2006.257.22:39:40.84#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:39:40.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:39:40.84#ibcon#[27=USB\r\n] 2006.257.22:39:40.84#ibcon#*before write, iclass 15, count 0 2006.257.22:39:40.84#ibcon#enter sib2, iclass 15, count 0 2006.257.22:39:40.84#ibcon#flushed, iclass 15, count 0 2006.257.22:39:40.84#ibcon#about to write, iclass 15, count 0 2006.257.22:39:40.84#ibcon#wrote, iclass 15, count 0 2006.257.22:39:40.84#ibcon#about to read 3, iclass 15, count 0 2006.257.22:39:40.87#ibcon#read 3, iclass 15, count 0 2006.257.22:39:40.87#ibcon#about to read 4, iclass 15, count 0 2006.257.22:39:40.87#ibcon#read 4, iclass 15, count 0 2006.257.22:39:40.87#ibcon#about to read 5, iclass 15, count 0 2006.257.22:39:40.87#ibcon#read 5, iclass 15, count 0 2006.257.22:39:40.87#ibcon#about to read 6, iclass 15, count 0 2006.257.22:39:40.87#ibcon#read 6, iclass 15, count 0 2006.257.22:39:40.87#ibcon#end of sib2, iclass 15, count 0 2006.257.22:39:40.87#ibcon#*after write, iclass 15, count 0 2006.257.22:39:40.87#ibcon#*before return 0, iclass 15, count 0 2006.257.22:39:40.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:40.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.22:39:40.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:39:40.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:39:40.87$vck44/vabw=wide 2006.257.22:39:40.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.22:39:40.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.22:39:40.87#ibcon#ireg 8 cls_cnt 0 2006.257.22:39:40.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:40.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:40.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:40.87#ibcon#enter wrdev, iclass 17, count 0 2006.257.22:39:40.87#ibcon#first serial, iclass 17, count 0 2006.257.22:39:40.87#ibcon#enter sib2, iclass 17, count 0 2006.257.22:39:40.87#ibcon#flushed, iclass 17, count 0 2006.257.22:39:40.87#ibcon#about to write, iclass 17, count 0 2006.257.22:39:40.87#ibcon#wrote, iclass 17, count 0 2006.257.22:39:40.87#ibcon#about to read 3, iclass 17, count 0 2006.257.22:39:40.89#ibcon#read 3, iclass 17, count 0 2006.257.22:39:40.89#ibcon#about to read 4, iclass 17, count 0 2006.257.22:39:40.89#ibcon#read 4, iclass 17, count 0 2006.257.22:39:40.89#ibcon#about to read 5, iclass 17, count 0 2006.257.22:39:40.89#ibcon#read 5, iclass 17, count 0 2006.257.22:39:40.89#ibcon#about to read 6, iclass 17, count 0 2006.257.22:39:40.89#ibcon#read 6, iclass 17, count 0 2006.257.22:39:40.89#ibcon#end of sib2, iclass 17, count 0 2006.257.22:39:40.89#ibcon#*mode == 0, iclass 17, count 0 2006.257.22:39:40.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.22:39:40.89#ibcon#[25=BW32\r\n] 2006.257.22:39:40.89#ibcon#*before write, iclass 17, count 0 2006.257.22:39:40.89#ibcon#enter sib2, iclass 17, count 0 2006.257.22:39:40.89#ibcon#flushed, iclass 17, count 0 2006.257.22:39:40.89#ibcon#about to write, iclass 17, count 0 2006.257.22:39:40.89#ibcon#wrote, iclass 17, count 0 2006.257.22:39:40.89#ibcon#about to read 3, iclass 17, count 0 2006.257.22:39:40.92#ibcon#read 3, iclass 17, count 0 2006.257.22:39:40.92#ibcon#about to read 4, iclass 17, count 0 2006.257.22:39:40.92#ibcon#read 4, iclass 17, count 0 2006.257.22:39:40.92#ibcon#about to read 5, iclass 17, count 0 2006.257.22:39:40.92#ibcon#read 5, iclass 17, count 0 2006.257.22:39:40.92#ibcon#about to read 6, iclass 17, count 0 2006.257.22:39:40.92#ibcon#read 6, iclass 17, count 0 2006.257.22:39:40.92#ibcon#end of sib2, iclass 17, count 0 2006.257.22:39:40.92#ibcon#*after write, iclass 17, count 0 2006.257.22:39:40.92#ibcon#*before return 0, iclass 17, count 0 2006.257.22:39:40.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:40.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.22:39:40.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.22:39:40.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.22:39:40.92$vck44/vbbw=wide 2006.257.22:39:40.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.22:39:40.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.22:39:40.92#ibcon#ireg 8 cls_cnt 0 2006.257.22:39:40.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:39:40.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:39:40.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:39:40.99#ibcon#enter wrdev, iclass 19, count 0 2006.257.22:39:40.99#ibcon#first serial, iclass 19, count 0 2006.257.22:39:40.99#ibcon#enter sib2, iclass 19, count 0 2006.257.22:39:40.99#ibcon#flushed, iclass 19, count 0 2006.257.22:39:40.99#ibcon#about to write, iclass 19, count 0 2006.257.22:39:40.99#ibcon#wrote, iclass 19, count 0 2006.257.22:39:40.99#ibcon#about to read 3, iclass 19, count 0 2006.257.22:39:41.01#ibcon#read 3, iclass 19, count 0 2006.257.22:39:41.01#ibcon#about to read 4, iclass 19, count 0 2006.257.22:39:41.01#ibcon#read 4, iclass 19, count 0 2006.257.22:39:41.01#ibcon#about to read 5, iclass 19, count 0 2006.257.22:39:41.01#ibcon#read 5, iclass 19, count 0 2006.257.22:39:41.01#ibcon#about to read 6, iclass 19, count 0 2006.257.22:39:41.01#ibcon#read 6, iclass 19, count 0 2006.257.22:39:41.01#ibcon#end of sib2, iclass 19, count 0 2006.257.22:39:41.01#ibcon#*mode == 0, iclass 19, count 0 2006.257.22:39:41.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.22:39:41.01#ibcon#[27=BW32\r\n] 2006.257.22:39:41.01#ibcon#*before write, iclass 19, count 0 2006.257.22:39:41.01#ibcon#enter sib2, iclass 19, count 0 2006.257.22:39:41.01#ibcon#flushed, iclass 19, count 0 2006.257.22:39:41.01#ibcon#about to write, iclass 19, count 0 2006.257.22:39:41.01#ibcon#wrote, iclass 19, count 0 2006.257.22:39:41.01#ibcon#about to read 3, iclass 19, count 0 2006.257.22:39:41.04#ibcon#read 3, iclass 19, count 0 2006.257.22:39:41.04#ibcon#about to read 4, iclass 19, count 0 2006.257.22:39:41.04#ibcon#read 4, iclass 19, count 0 2006.257.22:39:41.04#ibcon#about to read 5, iclass 19, count 0 2006.257.22:39:41.04#ibcon#read 5, iclass 19, count 0 2006.257.22:39:41.04#ibcon#about to read 6, iclass 19, count 0 2006.257.22:39:41.04#ibcon#read 6, iclass 19, count 0 2006.257.22:39:41.04#ibcon#end of sib2, iclass 19, count 0 2006.257.22:39:41.04#ibcon#*after write, iclass 19, count 0 2006.257.22:39:41.04#ibcon#*before return 0, iclass 19, count 0 2006.257.22:39:41.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:39:41.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:39:41.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.22:39:41.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.22:39:41.04$setupk4/ifdk4 2006.257.22:39:41.04$ifdk4/lo= 2006.257.22:39:41.04$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.22:39:41.04$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.22:39:41.04$ifdk4/patch= 2006.257.22:39:41.04$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.22:39:41.04$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.22:39:41.04$setupk4/!*+20s 2006.257.22:39:44.55#abcon#<5=/14 1.0 3.4 19.52 871016.0\r\n> 2006.257.22:39:44.57#abcon#{5=INTERFACE CLEAR} 2006.257.22:39:44.63#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:39:54.72#abcon#<5=/14 1.0 3.4 19.53 871016.0\r\n> 2006.257.22:39:54.74#abcon#{5=INTERFACE CLEAR} 2006.257.22:39:54.80#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:39:55.55$setupk4/"tpicd 2006.257.22:39:55.55$setupk4/echo=off 2006.257.22:39:55.55$setupk4/xlog=off 2006.257.22:39:55.55:!2006.257.22:43:15 2006.257.22:39:59.14#trakl#Source acquired 2006.257.22:39:59.14#flagr#flagr/antenna,acquired 2006.257.22:43:15.00:preob 2006.257.22:43:15.13/onsource/TRACKING 2006.257.22:43:15.13:!2006.257.22:43:25 2006.257.22:43:25.00:"tape 2006.257.22:43:25.00:"st=record 2006.257.22:43:25.00:data_valid=on 2006.257.22:43:25.00:midob 2006.257.22:43:26.13/onsource/TRACKING 2006.257.22:43:26.13/wx/19.59,1016.0,86 2006.257.22:43:26.25/cable/+6.4828E-03 2006.257.22:43:27.34/va/01,08,usb,yes,30,32 2006.257.22:43:27.34/va/02,07,usb,yes,32,33 2006.257.22:43:27.34/va/03,08,usb,yes,29,31 2006.257.22:43:27.34/va/04,07,usb,yes,33,35 2006.257.22:43:27.34/va/05,04,usb,yes,30,30 2006.257.22:43:27.34/va/06,04,usb,yes,33,33 2006.257.22:43:27.34/va/07,04,usb,yes,34,35 2006.257.22:43:27.34/va/08,04,usb,yes,28,35 2006.257.22:43:27.57/valo/01,524.99,yes,locked 2006.257.22:43:27.57/valo/02,534.99,yes,locked 2006.257.22:43:27.57/valo/03,564.99,yes,locked 2006.257.22:43:27.57/valo/04,624.99,yes,locked 2006.257.22:43:27.57/valo/05,734.99,yes,locked 2006.257.22:43:27.57/valo/06,814.99,yes,locked 2006.257.22:43:27.57/valo/07,864.99,yes,locked 2006.257.22:43:27.57/valo/08,884.99,yes,locked 2006.257.22:43:28.66/vb/01,04,usb,yes,30,28 2006.257.22:43:28.66/vb/02,05,usb,yes,28,28 2006.257.22:43:28.66/vb/03,04,usb,yes,29,32 2006.257.22:43:28.66/vb/04,05,usb,yes,29,28 2006.257.22:43:28.66/vb/05,04,usb,yes,26,28 2006.257.22:43:28.66/vb/06,04,usb,yes,30,27 2006.257.22:43:28.66/vb/07,04,usb,yes,30,30 2006.257.22:43:28.66/vb/08,04,usb,yes,28,31 2006.257.22:43:28.90/vblo/01,629.99,yes,locked 2006.257.22:43:28.90/vblo/02,634.99,yes,locked 2006.257.22:43:28.90/vblo/03,649.99,yes,locked 2006.257.22:43:28.90/vblo/04,679.99,yes,locked 2006.257.22:43:28.90/vblo/05,709.99,yes,locked 2006.257.22:43:28.90/vblo/06,719.99,yes,locked 2006.257.22:43:28.90/vblo/07,734.99,yes,locked 2006.257.22:43:28.90/vblo/08,744.99,yes,locked 2006.257.22:43:29.05/vabw/8 2006.257.22:43:29.20/vbbw/8 2006.257.22:43:29.29/xfe/off,on,15.2 2006.257.22:43:29.67/ifatt/23,28,28,28 2006.257.22:43:30.08/fmout-gps/S +4.60E-07 2006.257.22:43:30.12:!2006.257.22:50:25 2006.257.22:50:25.00:data_valid=off 2006.257.22:50:25.00:"et 2006.257.22:50:25.00:!+3s 2006.257.22:50:28.01:"tape 2006.257.22:50:28.01:postob 2006.257.22:50:28.20/cable/+6.4846E-03 2006.257.22:50:28.20/wx/19.77,1016.0,85 2006.257.22:50:29.08/fmout-gps/S +4.58E-07 2006.257.22:50:29.08:scan_name=257-2257,jd0609,320 2006.257.22:50:29.08:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.257.22:50:29.13#flagr#flagr/antenna,new-source 2006.257.22:50:30.13:checkk5 2006.257.22:50:30.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.22:50:30.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.22:50:31.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.22:50:31.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.22:50:31.85/chk_obsdata//k5ts1/T2572243??a.dat file size is correct (nominal:1680MB, actual:1680MB). 2006.257.22:50:32.18/chk_obsdata//k5ts2/T2572243??b.dat file size is correct (nominal:1680MB, actual:1680MB). 2006.257.22:50:32.51/chk_obsdata//k5ts3/T2572243??c.dat file size is correct (nominal:1680MB, actual:1680MB). 2006.257.22:50:32.84/chk_obsdata//k5ts4/T2572243??d.dat file size is correct (nominal:1680MB, actual:1680MB). 2006.257.22:50:33.51/k5log//k5ts1_log_newline 2006.257.22:50:34.18/k5log//k5ts2_log_newline 2006.257.22:50:34.86/k5log//k5ts3_log_newline 2006.257.22:50:35.53/k5log//k5ts4_log_newline 2006.257.22:50:35.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.22:50:35.56:setupk4=1 2006.257.22:50:35.56$setupk4/echo=on 2006.257.22:50:35.56$setupk4/pcalon 2006.257.22:50:35.56$pcalon/"no phase cal control is implemented here 2006.257.22:50:35.56$setupk4/"tpicd=stop 2006.257.22:50:35.56$setupk4/"rec=synch_on 2006.257.22:50:35.56$setupk4/"rec_mode=128 2006.257.22:50:35.56$setupk4/!* 2006.257.22:50:35.56$setupk4/recpk4 2006.257.22:50:35.56$recpk4/recpatch= 2006.257.22:50:35.56$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.22:50:35.56$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.22:50:35.56$setupk4/vck44 2006.257.22:50:35.56$vck44/valo=1,524.99 2006.257.22:50:35.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.22:50:35.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.22:50:35.56#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:35.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:50:35.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:50:35.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:50:35.56#ibcon#enter wrdev, iclass 23, count 0 2006.257.22:50:35.56#ibcon#first serial, iclass 23, count 0 2006.257.22:50:35.56#ibcon#enter sib2, iclass 23, count 0 2006.257.22:50:35.56#ibcon#flushed, iclass 23, count 0 2006.257.22:50:35.56#ibcon#about to write, iclass 23, count 0 2006.257.22:50:35.56#ibcon#wrote, iclass 23, count 0 2006.257.22:50:35.56#ibcon#about to read 3, iclass 23, count 0 2006.257.22:50:35.58#ibcon#read 3, iclass 23, count 0 2006.257.22:50:35.58#ibcon#about to read 4, iclass 23, count 0 2006.257.22:50:35.58#ibcon#read 4, iclass 23, count 0 2006.257.22:50:35.58#ibcon#about to read 5, iclass 23, count 0 2006.257.22:50:35.58#ibcon#read 5, iclass 23, count 0 2006.257.22:50:35.58#ibcon#about to read 6, iclass 23, count 0 2006.257.22:50:35.58#ibcon#read 6, iclass 23, count 0 2006.257.22:50:35.58#ibcon#end of sib2, iclass 23, count 0 2006.257.22:50:35.58#ibcon#*mode == 0, iclass 23, count 0 2006.257.22:50:35.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.22:50:35.58#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.22:50:35.58#ibcon#*before write, iclass 23, count 0 2006.257.22:50:35.58#ibcon#enter sib2, iclass 23, count 0 2006.257.22:50:35.58#ibcon#flushed, iclass 23, count 0 2006.257.22:50:35.58#ibcon#about to write, iclass 23, count 0 2006.257.22:50:35.58#ibcon#wrote, iclass 23, count 0 2006.257.22:50:35.58#ibcon#about to read 3, iclass 23, count 0 2006.257.22:50:35.62#ibcon#read 3, iclass 23, count 0 2006.257.22:50:35.63#ibcon#about to read 4, iclass 23, count 0 2006.257.22:50:35.63#ibcon#read 4, iclass 23, count 0 2006.257.22:50:35.63#ibcon#about to read 5, iclass 23, count 0 2006.257.22:50:35.63#ibcon#read 5, iclass 23, count 0 2006.257.22:50:35.63#ibcon#about to read 6, iclass 23, count 0 2006.257.22:50:35.63#ibcon#read 6, iclass 23, count 0 2006.257.22:50:35.63#ibcon#end of sib2, iclass 23, count 0 2006.257.22:50:35.63#ibcon#*after write, iclass 23, count 0 2006.257.22:50:35.63#ibcon#*before return 0, iclass 23, count 0 2006.257.22:50:35.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:50:35.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.22:50:35.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.22:50:35.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.22:50:35.63$vck44/va=1,8 2006.257.22:50:35.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.22:50:35.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.22:50:35.63#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:35.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:50:35.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:50:35.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:50:35.63#ibcon#enter wrdev, iclass 25, count 2 2006.257.22:50:35.63#ibcon#first serial, iclass 25, count 2 2006.257.22:50:35.63#ibcon#enter sib2, iclass 25, count 2 2006.257.22:50:35.63#ibcon#flushed, iclass 25, count 2 2006.257.22:50:35.63#ibcon#about to write, iclass 25, count 2 2006.257.22:50:35.63#ibcon#wrote, iclass 25, count 2 2006.257.22:50:35.63#ibcon#about to read 3, iclass 25, count 2 2006.257.22:50:35.65#ibcon#read 3, iclass 25, count 2 2006.257.22:50:35.65#ibcon#about to read 4, iclass 25, count 2 2006.257.22:50:35.65#ibcon#read 4, iclass 25, count 2 2006.257.22:50:35.65#ibcon#about to read 5, iclass 25, count 2 2006.257.22:50:35.65#ibcon#read 5, iclass 25, count 2 2006.257.22:50:35.65#ibcon#about to read 6, iclass 25, count 2 2006.257.22:50:35.65#ibcon#read 6, iclass 25, count 2 2006.257.22:50:35.65#ibcon#end of sib2, iclass 25, count 2 2006.257.22:50:35.65#ibcon#*mode == 0, iclass 25, count 2 2006.257.22:50:35.65#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.22:50:35.65#ibcon#[25=AT01-08\r\n] 2006.257.22:50:35.65#ibcon#*before write, iclass 25, count 2 2006.257.22:50:35.65#ibcon#enter sib2, iclass 25, count 2 2006.257.22:50:35.65#ibcon#flushed, iclass 25, count 2 2006.257.22:50:35.65#ibcon#about to write, iclass 25, count 2 2006.257.22:50:35.65#ibcon#wrote, iclass 25, count 2 2006.257.22:50:35.65#ibcon#about to read 3, iclass 25, count 2 2006.257.22:50:35.67#ibcon#read 3, iclass 25, count 2 2006.257.22:50:35.68#ibcon#about to read 4, iclass 25, count 2 2006.257.22:50:35.68#ibcon#read 4, iclass 25, count 2 2006.257.22:50:35.68#ibcon#about to read 5, iclass 25, count 2 2006.257.22:50:35.68#ibcon#read 5, iclass 25, count 2 2006.257.22:50:35.68#ibcon#about to read 6, iclass 25, count 2 2006.257.22:50:35.68#ibcon#read 6, iclass 25, count 2 2006.257.22:50:35.68#ibcon#end of sib2, iclass 25, count 2 2006.257.22:50:35.68#ibcon#*after write, iclass 25, count 2 2006.257.22:50:35.68#ibcon#*before return 0, iclass 25, count 2 2006.257.22:50:35.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:50:35.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.22:50:35.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.22:50:35.68#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:35.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:50:35.79#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:50:35.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:50:35.80#ibcon#enter wrdev, iclass 25, count 0 2006.257.22:50:35.80#ibcon#first serial, iclass 25, count 0 2006.257.22:50:35.80#ibcon#enter sib2, iclass 25, count 0 2006.257.22:50:35.80#ibcon#flushed, iclass 25, count 0 2006.257.22:50:35.80#ibcon#about to write, iclass 25, count 0 2006.257.22:50:35.80#ibcon#wrote, iclass 25, count 0 2006.257.22:50:35.80#ibcon#about to read 3, iclass 25, count 0 2006.257.22:50:35.81#ibcon#read 3, iclass 25, count 0 2006.257.22:50:35.82#ibcon#about to read 4, iclass 25, count 0 2006.257.22:50:35.82#ibcon#read 4, iclass 25, count 0 2006.257.22:50:35.82#ibcon#about to read 5, iclass 25, count 0 2006.257.22:50:35.82#ibcon#read 5, iclass 25, count 0 2006.257.22:50:35.82#ibcon#about to read 6, iclass 25, count 0 2006.257.22:50:35.82#ibcon#read 6, iclass 25, count 0 2006.257.22:50:35.82#ibcon#end of sib2, iclass 25, count 0 2006.257.22:50:35.82#ibcon#*mode == 0, iclass 25, count 0 2006.257.22:50:35.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.22:50:35.82#ibcon#[25=USB\r\n] 2006.257.22:50:35.82#ibcon#*before write, iclass 25, count 0 2006.257.22:50:35.82#ibcon#enter sib2, iclass 25, count 0 2006.257.22:50:35.82#ibcon#flushed, iclass 25, count 0 2006.257.22:50:35.82#ibcon#about to write, iclass 25, count 0 2006.257.22:50:35.82#ibcon#wrote, iclass 25, count 0 2006.257.22:50:35.82#ibcon#about to read 3, iclass 25, count 0 2006.257.22:50:35.84#ibcon#read 3, iclass 25, count 0 2006.257.22:50:35.85#ibcon#about to read 4, iclass 25, count 0 2006.257.22:50:35.85#ibcon#read 4, iclass 25, count 0 2006.257.22:50:35.85#ibcon#about to read 5, iclass 25, count 0 2006.257.22:50:35.85#ibcon#read 5, iclass 25, count 0 2006.257.22:50:35.85#ibcon#about to read 6, iclass 25, count 0 2006.257.22:50:35.85#ibcon#read 6, iclass 25, count 0 2006.257.22:50:35.85#ibcon#end of sib2, iclass 25, count 0 2006.257.22:50:35.85#ibcon#*after write, iclass 25, count 0 2006.257.22:50:35.85#ibcon#*before return 0, iclass 25, count 0 2006.257.22:50:35.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:50:35.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.22:50:35.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.22:50:35.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.22:50:35.85$vck44/valo=2,534.99 2006.257.22:50:35.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.22:50:35.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.22:50:35.85#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:35.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:50:35.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:50:35.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:50:35.85#ibcon#enter wrdev, iclass 27, count 0 2006.257.22:50:35.85#ibcon#first serial, iclass 27, count 0 2006.257.22:50:35.85#ibcon#enter sib2, iclass 27, count 0 2006.257.22:50:35.85#ibcon#flushed, iclass 27, count 0 2006.257.22:50:35.85#ibcon#about to write, iclass 27, count 0 2006.257.22:50:35.85#ibcon#wrote, iclass 27, count 0 2006.257.22:50:35.85#ibcon#about to read 3, iclass 27, count 0 2006.257.22:50:35.87#ibcon#read 3, iclass 27, count 0 2006.257.22:50:35.87#ibcon#about to read 4, iclass 27, count 0 2006.257.22:50:35.87#ibcon#read 4, iclass 27, count 0 2006.257.22:50:35.87#ibcon#about to read 5, iclass 27, count 0 2006.257.22:50:35.87#ibcon#read 5, iclass 27, count 0 2006.257.22:50:35.87#ibcon#about to read 6, iclass 27, count 0 2006.257.22:50:35.87#ibcon#read 6, iclass 27, count 0 2006.257.22:50:35.87#ibcon#end of sib2, iclass 27, count 0 2006.257.22:50:35.87#ibcon#*mode == 0, iclass 27, count 0 2006.257.22:50:35.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.22:50:35.87#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.22:50:35.87#ibcon#*before write, iclass 27, count 0 2006.257.22:50:35.87#ibcon#enter sib2, iclass 27, count 0 2006.257.22:50:35.87#ibcon#flushed, iclass 27, count 0 2006.257.22:50:35.87#ibcon#about to write, iclass 27, count 0 2006.257.22:50:35.87#ibcon#wrote, iclass 27, count 0 2006.257.22:50:35.87#ibcon#about to read 3, iclass 27, count 0 2006.257.22:50:35.90#ibcon#read 3, iclass 27, count 0 2006.257.22:50:35.91#ibcon#about to read 4, iclass 27, count 0 2006.257.22:50:35.91#ibcon#read 4, iclass 27, count 0 2006.257.22:50:35.91#ibcon#about to read 5, iclass 27, count 0 2006.257.22:50:35.91#ibcon#read 5, iclass 27, count 0 2006.257.22:50:35.91#ibcon#about to read 6, iclass 27, count 0 2006.257.22:50:35.91#ibcon#read 6, iclass 27, count 0 2006.257.22:50:35.91#ibcon#end of sib2, iclass 27, count 0 2006.257.22:50:35.91#ibcon#*after write, iclass 27, count 0 2006.257.22:50:35.91#ibcon#*before return 0, iclass 27, count 0 2006.257.22:50:35.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:50:35.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.22:50:35.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.22:50:35.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.22:50:35.91$vck44/va=2,7 2006.257.22:50:35.91#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.22:50:35.91#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.22:50:35.91#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:35.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:50:35.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:50:35.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:50:35.97#ibcon#enter wrdev, iclass 29, count 2 2006.257.22:50:35.97#ibcon#first serial, iclass 29, count 2 2006.257.22:50:35.97#ibcon#enter sib2, iclass 29, count 2 2006.257.22:50:35.97#ibcon#flushed, iclass 29, count 2 2006.257.22:50:35.97#ibcon#about to write, iclass 29, count 2 2006.257.22:50:35.97#ibcon#wrote, iclass 29, count 2 2006.257.22:50:35.97#ibcon#about to read 3, iclass 29, count 2 2006.257.22:50:35.98#ibcon#read 3, iclass 29, count 2 2006.257.22:50:35.99#ibcon#about to read 4, iclass 29, count 2 2006.257.22:50:35.99#ibcon#read 4, iclass 29, count 2 2006.257.22:50:35.99#ibcon#about to read 5, iclass 29, count 2 2006.257.22:50:35.99#ibcon#read 5, iclass 29, count 2 2006.257.22:50:35.99#ibcon#about to read 6, iclass 29, count 2 2006.257.22:50:35.99#ibcon#read 6, iclass 29, count 2 2006.257.22:50:35.99#ibcon#end of sib2, iclass 29, count 2 2006.257.22:50:35.99#ibcon#*mode == 0, iclass 29, count 2 2006.257.22:50:35.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.22:50:35.99#ibcon#[25=AT02-07\r\n] 2006.257.22:50:35.99#ibcon#*before write, iclass 29, count 2 2006.257.22:50:35.99#ibcon#enter sib2, iclass 29, count 2 2006.257.22:50:35.99#ibcon#flushed, iclass 29, count 2 2006.257.22:50:35.99#ibcon#about to write, iclass 29, count 2 2006.257.22:50:35.99#ibcon#wrote, iclass 29, count 2 2006.257.22:50:35.99#ibcon#about to read 3, iclass 29, count 2 2006.257.22:50:36.01#ibcon#read 3, iclass 29, count 2 2006.257.22:50:36.02#ibcon#about to read 4, iclass 29, count 2 2006.257.22:50:36.02#ibcon#read 4, iclass 29, count 2 2006.257.22:50:36.02#ibcon#about to read 5, iclass 29, count 2 2006.257.22:50:36.02#ibcon#read 5, iclass 29, count 2 2006.257.22:50:36.02#ibcon#about to read 6, iclass 29, count 2 2006.257.22:50:36.02#ibcon#read 6, iclass 29, count 2 2006.257.22:50:36.02#ibcon#end of sib2, iclass 29, count 2 2006.257.22:50:36.02#ibcon#*after write, iclass 29, count 2 2006.257.22:50:36.02#ibcon#*before return 0, iclass 29, count 2 2006.257.22:50:36.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:50:36.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.22:50:36.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.22:50:36.02#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:36.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:50:36.13#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:50:36.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:50:36.14#ibcon#enter wrdev, iclass 29, count 0 2006.257.22:50:36.14#ibcon#first serial, iclass 29, count 0 2006.257.22:50:36.14#ibcon#enter sib2, iclass 29, count 0 2006.257.22:50:36.14#ibcon#flushed, iclass 29, count 0 2006.257.22:50:36.14#ibcon#about to write, iclass 29, count 0 2006.257.22:50:36.14#ibcon#wrote, iclass 29, count 0 2006.257.22:50:36.14#ibcon#about to read 3, iclass 29, count 0 2006.257.22:50:36.15#ibcon#read 3, iclass 29, count 0 2006.257.22:50:36.16#ibcon#about to read 4, iclass 29, count 0 2006.257.22:50:36.16#ibcon#read 4, iclass 29, count 0 2006.257.22:50:36.16#ibcon#about to read 5, iclass 29, count 0 2006.257.22:50:36.16#ibcon#read 5, iclass 29, count 0 2006.257.22:50:36.16#ibcon#about to read 6, iclass 29, count 0 2006.257.22:50:36.16#ibcon#read 6, iclass 29, count 0 2006.257.22:50:36.16#ibcon#end of sib2, iclass 29, count 0 2006.257.22:50:36.16#ibcon#*mode == 0, iclass 29, count 0 2006.257.22:50:36.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.22:50:36.16#ibcon#[25=USB\r\n] 2006.257.22:50:36.16#ibcon#*before write, iclass 29, count 0 2006.257.22:50:36.16#ibcon#enter sib2, iclass 29, count 0 2006.257.22:50:36.16#ibcon#flushed, iclass 29, count 0 2006.257.22:50:36.16#ibcon#about to write, iclass 29, count 0 2006.257.22:50:36.16#ibcon#wrote, iclass 29, count 0 2006.257.22:50:36.16#ibcon#about to read 3, iclass 29, count 0 2006.257.22:50:36.18#ibcon#read 3, iclass 29, count 0 2006.257.22:50:36.19#ibcon#about to read 4, iclass 29, count 0 2006.257.22:50:36.19#ibcon#read 4, iclass 29, count 0 2006.257.22:50:36.19#ibcon#about to read 5, iclass 29, count 0 2006.257.22:50:36.19#ibcon#read 5, iclass 29, count 0 2006.257.22:50:36.19#ibcon#about to read 6, iclass 29, count 0 2006.257.22:50:36.19#ibcon#read 6, iclass 29, count 0 2006.257.22:50:36.19#ibcon#end of sib2, iclass 29, count 0 2006.257.22:50:36.19#ibcon#*after write, iclass 29, count 0 2006.257.22:50:36.19#ibcon#*before return 0, iclass 29, count 0 2006.257.22:50:36.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:50:36.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.22:50:36.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.22:50:36.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.22:50:36.19$vck44/valo=3,564.99 2006.257.22:50:36.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.22:50:36.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.22:50:36.19#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:36.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:36.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:36.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:36.19#ibcon#enter wrdev, iclass 31, count 0 2006.257.22:50:36.19#ibcon#first serial, iclass 31, count 0 2006.257.22:50:36.19#ibcon#enter sib2, iclass 31, count 0 2006.257.22:50:36.19#ibcon#flushed, iclass 31, count 0 2006.257.22:50:36.19#ibcon#about to write, iclass 31, count 0 2006.257.22:50:36.19#ibcon#wrote, iclass 31, count 0 2006.257.22:50:36.19#ibcon#about to read 3, iclass 31, count 0 2006.257.22:50:36.20#ibcon#read 3, iclass 31, count 0 2006.257.22:50:36.21#ibcon#about to read 4, iclass 31, count 0 2006.257.22:50:36.21#ibcon#read 4, iclass 31, count 0 2006.257.22:50:36.21#ibcon#about to read 5, iclass 31, count 0 2006.257.22:50:36.21#ibcon#read 5, iclass 31, count 0 2006.257.22:50:36.21#ibcon#about to read 6, iclass 31, count 0 2006.257.22:50:36.21#ibcon#read 6, iclass 31, count 0 2006.257.22:50:36.21#ibcon#end of sib2, iclass 31, count 0 2006.257.22:50:36.21#ibcon#*mode == 0, iclass 31, count 0 2006.257.22:50:36.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.22:50:36.21#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.22:50:36.21#ibcon#*before write, iclass 31, count 0 2006.257.22:50:36.21#ibcon#enter sib2, iclass 31, count 0 2006.257.22:50:36.21#ibcon#flushed, iclass 31, count 0 2006.257.22:50:36.21#ibcon#about to write, iclass 31, count 0 2006.257.22:50:36.21#ibcon#wrote, iclass 31, count 0 2006.257.22:50:36.21#ibcon#about to read 3, iclass 31, count 0 2006.257.22:50:36.24#ibcon#read 3, iclass 31, count 0 2006.257.22:50:36.25#ibcon#about to read 4, iclass 31, count 0 2006.257.22:50:36.25#ibcon#read 4, iclass 31, count 0 2006.257.22:50:36.25#ibcon#about to read 5, iclass 31, count 0 2006.257.22:50:36.25#ibcon#read 5, iclass 31, count 0 2006.257.22:50:36.25#ibcon#about to read 6, iclass 31, count 0 2006.257.22:50:36.25#ibcon#read 6, iclass 31, count 0 2006.257.22:50:36.25#ibcon#end of sib2, iclass 31, count 0 2006.257.22:50:36.25#ibcon#*after write, iclass 31, count 0 2006.257.22:50:36.25#ibcon#*before return 0, iclass 31, count 0 2006.257.22:50:36.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:36.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:36.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.22:50:36.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.22:50:36.25$vck44/va=3,8 2006.257.22:50:36.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.22:50:36.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.22:50:36.25#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:36.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:36.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:36.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:36.31#ibcon#enter wrdev, iclass 33, count 2 2006.257.22:50:36.31#ibcon#first serial, iclass 33, count 2 2006.257.22:50:36.31#ibcon#enter sib2, iclass 33, count 2 2006.257.22:50:36.31#ibcon#flushed, iclass 33, count 2 2006.257.22:50:36.31#ibcon#about to write, iclass 33, count 2 2006.257.22:50:36.31#ibcon#wrote, iclass 33, count 2 2006.257.22:50:36.31#ibcon#about to read 3, iclass 33, count 2 2006.257.22:50:36.32#ibcon#read 3, iclass 33, count 2 2006.257.22:50:36.33#ibcon#about to read 4, iclass 33, count 2 2006.257.22:50:36.33#ibcon#read 4, iclass 33, count 2 2006.257.22:50:36.33#ibcon#about to read 5, iclass 33, count 2 2006.257.22:50:36.33#ibcon#read 5, iclass 33, count 2 2006.257.22:50:36.33#ibcon#about to read 6, iclass 33, count 2 2006.257.22:50:36.33#ibcon#read 6, iclass 33, count 2 2006.257.22:50:36.33#ibcon#end of sib2, iclass 33, count 2 2006.257.22:50:36.33#ibcon#*mode == 0, iclass 33, count 2 2006.257.22:50:36.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.22:50:36.33#ibcon#[25=AT03-08\r\n] 2006.257.22:50:36.33#ibcon#*before write, iclass 33, count 2 2006.257.22:50:36.33#ibcon#enter sib2, iclass 33, count 2 2006.257.22:50:36.33#ibcon#flushed, iclass 33, count 2 2006.257.22:50:36.33#ibcon#about to write, iclass 33, count 2 2006.257.22:50:36.33#ibcon#wrote, iclass 33, count 2 2006.257.22:50:36.33#ibcon#about to read 3, iclass 33, count 2 2006.257.22:50:36.35#ibcon#read 3, iclass 33, count 2 2006.257.22:50:36.36#ibcon#about to read 4, iclass 33, count 2 2006.257.22:50:36.36#ibcon#read 4, iclass 33, count 2 2006.257.22:50:36.36#ibcon#about to read 5, iclass 33, count 2 2006.257.22:50:36.36#ibcon#read 5, iclass 33, count 2 2006.257.22:50:36.36#ibcon#about to read 6, iclass 33, count 2 2006.257.22:50:36.36#ibcon#read 6, iclass 33, count 2 2006.257.22:50:36.36#ibcon#end of sib2, iclass 33, count 2 2006.257.22:50:36.36#ibcon#*after write, iclass 33, count 2 2006.257.22:50:36.36#ibcon#*before return 0, iclass 33, count 2 2006.257.22:50:36.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:36.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:36.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.22:50:36.36#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:36.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:36.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:36.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:36.48#ibcon#enter wrdev, iclass 33, count 0 2006.257.22:50:36.48#ibcon#first serial, iclass 33, count 0 2006.257.22:50:36.48#ibcon#enter sib2, iclass 33, count 0 2006.257.22:50:36.48#ibcon#flushed, iclass 33, count 0 2006.257.22:50:36.48#ibcon#about to write, iclass 33, count 0 2006.257.22:50:36.48#ibcon#wrote, iclass 33, count 0 2006.257.22:50:36.48#ibcon#about to read 3, iclass 33, count 0 2006.257.22:50:36.49#ibcon#read 3, iclass 33, count 0 2006.257.22:50:36.50#ibcon#about to read 4, iclass 33, count 0 2006.257.22:50:36.50#ibcon#read 4, iclass 33, count 0 2006.257.22:50:36.50#ibcon#about to read 5, iclass 33, count 0 2006.257.22:50:36.50#ibcon#read 5, iclass 33, count 0 2006.257.22:50:36.50#ibcon#about to read 6, iclass 33, count 0 2006.257.22:50:36.50#ibcon#read 6, iclass 33, count 0 2006.257.22:50:36.50#ibcon#end of sib2, iclass 33, count 0 2006.257.22:50:36.50#ibcon#*mode == 0, iclass 33, count 0 2006.257.22:50:36.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.22:50:36.50#ibcon#[25=USB\r\n] 2006.257.22:50:36.50#ibcon#*before write, iclass 33, count 0 2006.257.22:50:36.50#ibcon#enter sib2, iclass 33, count 0 2006.257.22:50:36.50#ibcon#flushed, iclass 33, count 0 2006.257.22:50:36.50#ibcon#about to write, iclass 33, count 0 2006.257.22:50:36.50#ibcon#wrote, iclass 33, count 0 2006.257.22:50:36.50#ibcon#about to read 3, iclass 33, count 0 2006.257.22:50:36.52#ibcon#read 3, iclass 33, count 0 2006.257.22:50:36.53#ibcon#about to read 4, iclass 33, count 0 2006.257.22:50:36.53#ibcon#read 4, iclass 33, count 0 2006.257.22:50:36.53#ibcon#about to read 5, iclass 33, count 0 2006.257.22:50:36.53#ibcon#read 5, iclass 33, count 0 2006.257.22:50:36.53#ibcon#about to read 6, iclass 33, count 0 2006.257.22:50:36.53#ibcon#read 6, iclass 33, count 0 2006.257.22:50:36.53#ibcon#end of sib2, iclass 33, count 0 2006.257.22:50:36.53#ibcon#*after write, iclass 33, count 0 2006.257.22:50:36.53#ibcon#*before return 0, iclass 33, count 0 2006.257.22:50:36.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:36.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:36.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.22:50:36.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.22:50:36.53$vck44/valo=4,624.99 2006.257.22:50:36.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.22:50:36.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.22:50:36.53#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:36.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:36.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:36.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:36.53#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:50:36.53#ibcon#first serial, iclass 35, count 0 2006.257.22:50:36.53#ibcon#enter sib2, iclass 35, count 0 2006.257.22:50:36.53#ibcon#flushed, iclass 35, count 0 2006.257.22:50:36.53#ibcon#about to write, iclass 35, count 0 2006.257.22:50:36.53#ibcon#wrote, iclass 35, count 0 2006.257.22:50:36.53#ibcon#about to read 3, iclass 35, count 0 2006.257.22:50:36.54#ibcon#read 3, iclass 35, count 0 2006.257.22:50:36.55#ibcon#about to read 4, iclass 35, count 0 2006.257.22:50:36.55#ibcon#read 4, iclass 35, count 0 2006.257.22:50:36.55#ibcon#about to read 5, iclass 35, count 0 2006.257.22:50:36.55#ibcon#read 5, iclass 35, count 0 2006.257.22:50:36.55#ibcon#about to read 6, iclass 35, count 0 2006.257.22:50:36.55#ibcon#read 6, iclass 35, count 0 2006.257.22:50:36.55#ibcon#end of sib2, iclass 35, count 0 2006.257.22:50:36.55#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:50:36.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:50:36.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.22:50:36.55#ibcon#*before write, iclass 35, count 0 2006.257.22:50:36.55#ibcon#enter sib2, iclass 35, count 0 2006.257.22:50:36.55#ibcon#flushed, iclass 35, count 0 2006.257.22:50:36.55#ibcon#about to write, iclass 35, count 0 2006.257.22:50:36.55#ibcon#wrote, iclass 35, count 0 2006.257.22:50:36.55#ibcon#about to read 3, iclass 35, count 0 2006.257.22:50:36.58#ibcon#read 3, iclass 35, count 0 2006.257.22:50:36.59#ibcon#about to read 4, iclass 35, count 0 2006.257.22:50:36.59#ibcon#read 4, iclass 35, count 0 2006.257.22:50:36.59#ibcon#about to read 5, iclass 35, count 0 2006.257.22:50:36.59#ibcon#read 5, iclass 35, count 0 2006.257.22:50:36.59#ibcon#about to read 6, iclass 35, count 0 2006.257.22:50:36.59#ibcon#read 6, iclass 35, count 0 2006.257.22:50:36.59#ibcon#end of sib2, iclass 35, count 0 2006.257.22:50:36.59#ibcon#*after write, iclass 35, count 0 2006.257.22:50:36.59#ibcon#*before return 0, iclass 35, count 0 2006.257.22:50:36.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:36.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:36.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:50:36.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:50:36.59$vck44/va=4,7 2006.257.22:50:36.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.22:50:36.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.22:50:36.59#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:36.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:36.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:36.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:36.65#ibcon#enter wrdev, iclass 37, count 2 2006.257.22:50:36.65#ibcon#first serial, iclass 37, count 2 2006.257.22:50:36.65#ibcon#enter sib2, iclass 37, count 2 2006.257.22:50:36.65#ibcon#flushed, iclass 37, count 2 2006.257.22:50:36.65#ibcon#about to write, iclass 37, count 2 2006.257.22:50:36.65#ibcon#wrote, iclass 37, count 2 2006.257.22:50:36.65#ibcon#about to read 3, iclass 37, count 2 2006.257.22:50:36.66#ibcon#read 3, iclass 37, count 2 2006.257.22:50:36.67#ibcon#about to read 4, iclass 37, count 2 2006.257.22:50:36.67#ibcon#read 4, iclass 37, count 2 2006.257.22:50:36.67#ibcon#about to read 5, iclass 37, count 2 2006.257.22:50:36.67#ibcon#read 5, iclass 37, count 2 2006.257.22:50:36.67#ibcon#about to read 6, iclass 37, count 2 2006.257.22:50:36.67#ibcon#read 6, iclass 37, count 2 2006.257.22:50:36.67#ibcon#end of sib2, iclass 37, count 2 2006.257.22:50:36.67#ibcon#*mode == 0, iclass 37, count 2 2006.257.22:50:36.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.22:50:36.67#ibcon#[25=AT04-07\r\n] 2006.257.22:50:36.67#ibcon#*before write, iclass 37, count 2 2006.257.22:50:36.67#ibcon#enter sib2, iclass 37, count 2 2006.257.22:50:36.67#ibcon#flushed, iclass 37, count 2 2006.257.22:50:36.67#ibcon#about to write, iclass 37, count 2 2006.257.22:50:36.67#ibcon#wrote, iclass 37, count 2 2006.257.22:50:36.67#ibcon#about to read 3, iclass 37, count 2 2006.257.22:50:36.69#ibcon#read 3, iclass 37, count 2 2006.257.22:50:36.70#ibcon#about to read 4, iclass 37, count 2 2006.257.22:50:36.70#ibcon#read 4, iclass 37, count 2 2006.257.22:50:36.70#ibcon#about to read 5, iclass 37, count 2 2006.257.22:50:36.70#ibcon#read 5, iclass 37, count 2 2006.257.22:50:36.70#ibcon#about to read 6, iclass 37, count 2 2006.257.22:50:36.70#ibcon#read 6, iclass 37, count 2 2006.257.22:50:36.70#ibcon#end of sib2, iclass 37, count 2 2006.257.22:50:36.70#ibcon#*after write, iclass 37, count 2 2006.257.22:50:36.70#ibcon#*before return 0, iclass 37, count 2 2006.257.22:50:36.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:36.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:36.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.22:50:36.70#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:36.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:36.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:36.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:36.82#ibcon#enter wrdev, iclass 37, count 0 2006.257.22:50:36.82#ibcon#first serial, iclass 37, count 0 2006.257.22:50:36.82#ibcon#enter sib2, iclass 37, count 0 2006.257.22:50:36.82#ibcon#flushed, iclass 37, count 0 2006.257.22:50:36.82#ibcon#about to write, iclass 37, count 0 2006.257.22:50:36.82#ibcon#wrote, iclass 37, count 0 2006.257.22:50:36.82#ibcon#about to read 3, iclass 37, count 0 2006.257.22:50:36.83#ibcon#read 3, iclass 37, count 0 2006.257.22:50:36.84#ibcon#about to read 4, iclass 37, count 0 2006.257.22:50:36.84#ibcon#read 4, iclass 37, count 0 2006.257.22:50:36.84#ibcon#about to read 5, iclass 37, count 0 2006.257.22:50:36.84#ibcon#read 5, iclass 37, count 0 2006.257.22:50:36.84#ibcon#about to read 6, iclass 37, count 0 2006.257.22:50:36.84#ibcon#read 6, iclass 37, count 0 2006.257.22:50:36.84#ibcon#end of sib2, iclass 37, count 0 2006.257.22:50:36.84#ibcon#*mode == 0, iclass 37, count 0 2006.257.22:50:36.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.22:50:36.84#ibcon#[25=USB\r\n] 2006.257.22:50:36.84#ibcon#*before write, iclass 37, count 0 2006.257.22:50:36.84#ibcon#enter sib2, iclass 37, count 0 2006.257.22:50:36.84#ibcon#flushed, iclass 37, count 0 2006.257.22:50:36.84#ibcon#about to write, iclass 37, count 0 2006.257.22:50:36.84#ibcon#wrote, iclass 37, count 0 2006.257.22:50:36.84#ibcon#about to read 3, iclass 37, count 0 2006.257.22:50:36.86#ibcon#read 3, iclass 37, count 0 2006.257.22:50:36.87#ibcon#about to read 4, iclass 37, count 0 2006.257.22:50:36.87#ibcon#read 4, iclass 37, count 0 2006.257.22:50:36.87#ibcon#about to read 5, iclass 37, count 0 2006.257.22:50:36.87#ibcon#read 5, iclass 37, count 0 2006.257.22:50:36.87#ibcon#about to read 6, iclass 37, count 0 2006.257.22:50:36.87#ibcon#read 6, iclass 37, count 0 2006.257.22:50:36.87#ibcon#end of sib2, iclass 37, count 0 2006.257.22:50:36.87#ibcon#*after write, iclass 37, count 0 2006.257.22:50:36.87#ibcon#*before return 0, iclass 37, count 0 2006.257.22:50:36.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:36.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:36.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.22:50:36.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.22:50:36.87$vck44/valo=5,734.99 2006.257.22:50:36.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.22:50:36.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.22:50:36.87#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:36.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:36.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:36.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:36.87#ibcon#enter wrdev, iclass 39, count 0 2006.257.22:50:36.87#ibcon#first serial, iclass 39, count 0 2006.257.22:50:36.87#ibcon#enter sib2, iclass 39, count 0 2006.257.22:50:36.87#ibcon#flushed, iclass 39, count 0 2006.257.22:50:36.87#ibcon#about to write, iclass 39, count 0 2006.257.22:50:36.87#ibcon#wrote, iclass 39, count 0 2006.257.22:50:36.87#ibcon#about to read 3, iclass 39, count 0 2006.257.22:50:36.88#ibcon#read 3, iclass 39, count 0 2006.257.22:50:36.89#ibcon#about to read 4, iclass 39, count 0 2006.257.22:50:36.89#ibcon#read 4, iclass 39, count 0 2006.257.22:50:36.89#ibcon#about to read 5, iclass 39, count 0 2006.257.22:50:36.89#ibcon#read 5, iclass 39, count 0 2006.257.22:50:36.89#ibcon#about to read 6, iclass 39, count 0 2006.257.22:50:36.89#ibcon#read 6, iclass 39, count 0 2006.257.22:50:36.89#ibcon#end of sib2, iclass 39, count 0 2006.257.22:50:36.89#ibcon#*mode == 0, iclass 39, count 0 2006.257.22:50:36.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.22:50:36.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.22:50:36.89#ibcon#*before write, iclass 39, count 0 2006.257.22:50:36.89#ibcon#enter sib2, iclass 39, count 0 2006.257.22:50:36.89#ibcon#flushed, iclass 39, count 0 2006.257.22:50:36.89#ibcon#about to write, iclass 39, count 0 2006.257.22:50:36.89#ibcon#wrote, iclass 39, count 0 2006.257.22:50:36.89#ibcon#about to read 3, iclass 39, count 0 2006.257.22:50:36.92#ibcon#read 3, iclass 39, count 0 2006.257.22:50:36.93#ibcon#about to read 4, iclass 39, count 0 2006.257.22:50:36.93#ibcon#read 4, iclass 39, count 0 2006.257.22:50:36.93#ibcon#about to read 5, iclass 39, count 0 2006.257.22:50:36.93#ibcon#read 5, iclass 39, count 0 2006.257.22:50:36.93#ibcon#about to read 6, iclass 39, count 0 2006.257.22:50:36.93#ibcon#read 6, iclass 39, count 0 2006.257.22:50:36.93#ibcon#end of sib2, iclass 39, count 0 2006.257.22:50:36.93#ibcon#*after write, iclass 39, count 0 2006.257.22:50:36.93#ibcon#*before return 0, iclass 39, count 0 2006.257.22:50:36.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:36.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:36.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.22:50:36.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.22:50:36.93$vck44/va=5,4 2006.257.22:50:36.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.22:50:36.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.22:50:36.93#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:36.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:36.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:36.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:36.99#ibcon#enter wrdev, iclass 3, count 2 2006.257.22:50:36.99#ibcon#first serial, iclass 3, count 2 2006.257.22:50:36.99#ibcon#enter sib2, iclass 3, count 2 2006.257.22:50:36.99#ibcon#flushed, iclass 3, count 2 2006.257.22:50:36.99#ibcon#about to write, iclass 3, count 2 2006.257.22:50:36.99#ibcon#wrote, iclass 3, count 2 2006.257.22:50:36.99#ibcon#about to read 3, iclass 3, count 2 2006.257.22:50:37.00#ibcon#read 3, iclass 3, count 2 2006.257.22:50:37.01#ibcon#about to read 4, iclass 3, count 2 2006.257.22:50:37.01#ibcon#read 4, iclass 3, count 2 2006.257.22:50:37.01#ibcon#about to read 5, iclass 3, count 2 2006.257.22:50:37.01#ibcon#read 5, iclass 3, count 2 2006.257.22:50:37.01#ibcon#about to read 6, iclass 3, count 2 2006.257.22:50:37.01#ibcon#read 6, iclass 3, count 2 2006.257.22:50:37.01#ibcon#end of sib2, iclass 3, count 2 2006.257.22:50:37.01#ibcon#*mode == 0, iclass 3, count 2 2006.257.22:50:37.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.22:50:37.01#ibcon#[25=AT05-04\r\n] 2006.257.22:50:37.01#ibcon#*before write, iclass 3, count 2 2006.257.22:50:37.01#ibcon#enter sib2, iclass 3, count 2 2006.257.22:50:37.01#ibcon#flushed, iclass 3, count 2 2006.257.22:50:37.01#ibcon#about to write, iclass 3, count 2 2006.257.22:50:37.01#ibcon#wrote, iclass 3, count 2 2006.257.22:50:37.01#ibcon#about to read 3, iclass 3, count 2 2006.257.22:50:37.03#ibcon#read 3, iclass 3, count 2 2006.257.22:50:37.04#ibcon#about to read 4, iclass 3, count 2 2006.257.22:50:37.04#ibcon#read 4, iclass 3, count 2 2006.257.22:50:37.04#ibcon#about to read 5, iclass 3, count 2 2006.257.22:50:37.04#ibcon#read 5, iclass 3, count 2 2006.257.22:50:37.04#ibcon#about to read 6, iclass 3, count 2 2006.257.22:50:37.04#ibcon#read 6, iclass 3, count 2 2006.257.22:50:37.04#ibcon#end of sib2, iclass 3, count 2 2006.257.22:50:37.04#ibcon#*after write, iclass 3, count 2 2006.257.22:50:37.04#ibcon#*before return 0, iclass 3, count 2 2006.257.22:50:37.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:37.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:37.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.22:50:37.04#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:37.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:37.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:37.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:37.16#ibcon#enter wrdev, iclass 3, count 0 2006.257.22:50:37.16#ibcon#first serial, iclass 3, count 0 2006.257.22:50:37.16#ibcon#enter sib2, iclass 3, count 0 2006.257.22:50:37.16#ibcon#flushed, iclass 3, count 0 2006.257.22:50:37.16#ibcon#about to write, iclass 3, count 0 2006.257.22:50:37.16#ibcon#wrote, iclass 3, count 0 2006.257.22:50:37.16#ibcon#about to read 3, iclass 3, count 0 2006.257.22:50:37.17#ibcon#read 3, iclass 3, count 0 2006.257.22:50:37.18#ibcon#about to read 4, iclass 3, count 0 2006.257.22:50:37.18#ibcon#read 4, iclass 3, count 0 2006.257.22:50:37.18#ibcon#about to read 5, iclass 3, count 0 2006.257.22:50:37.18#ibcon#read 5, iclass 3, count 0 2006.257.22:50:37.18#ibcon#about to read 6, iclass 3, count 0 2006.257.22:50:37.18#ibcon#read 6, iclass 3, count 0 2006.257.22:50:37.18#ibcon#end of sib2, iclass 3, count 0 2006.257.22:50:37.18#ibcon#*mode == 0, iclass 3, count 0 2006.257.22:50:37.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.22:50:37.18#ibcon#[25=USB\r\n] 2006.257.22:50:37.18#ibcon#*before write, iclass 3, count 0 2006.257.22:50:37.18#ibcon#enter sib2, iclass 3, count 0 2006.257.22:50:37.18#ibcon#flushed, iclass 3, count 0 2006.257.22:50:37.18#ibcon#about to write, iclass 3, count 0 2006.257.22:50:37.18#ibcon#wrote, iclass 3, count 0 2006.257.22:50:37.18#ibcon#about to read 3, iclass 3, count 0 2006.257.22:50:37.20#ibcon#read 3, iclass 3, count 0 2006.257.22:50:37.21#ibcon#about to read 4, iclass 3, count 0 2006.257.22:50:37.21#ibcon#read 4, iclass 3, count 0 2006.257.22:50:37.21#ibcon#about to read 5, iclass 3, count 0 2006.257.22:50:37.21#ibcon#read 5, iclass 3, count 0 2006.257.22:50:37.21#ibcon#about to read 6, iclass 3, count 0 2006.257.22:50:37.21#ibcon#read 6, iclass 3, count 0 2006.257.22:50:37.21#ibcon#end of sib2, iclass 3, count 0 2006.257.22:50:37.21#ibcon#*after write, iclass 3, count 0 2006.257.22:50:37.21#ibcon#*before return 0, iclass 3, count 0 2006.257.22:50:37.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:37.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:37.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.22:50:37.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.22:50:37.21$vck44/valo=6,814.99 2006.257.22:50:37.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.22:50:37.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.22:50:37.21#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:37.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:37.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:37.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:37.21#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:50:37.21#ibcon#first serial, iclass 5, count 0 2006.257.22:50:37.21#ibcon#enter sib2, iclass 5, count 0 2006.257.22:50:37.21#ibcon#flushed, iclass 5, count 0 2006.257.22:50:37.21#ibcon#about to write, iclass 5, count 0 2006.257.22:50:37.21#ibcon#wrote, iclass 5, count 0 2006.257.22:50:37.21#ibcon#about to read 3, iclass 5, count 0 2006.257.22:50:37.22#ibcon#read 3, iclass 5, count 0 2006.257.22:50:37.23#ibcon#about to read 4, iclass 5, count 0 2006.257.22:50:37.23#ibcon#read 4, iclass 5, count 0 2006.257.22:50:37.23#ibcon#about to read 5, iclass 5, count 0 2006.257.22:50:37.23#ibcon#read 5, iclass 5, count 0 2006.257.22:50:37.23#ibcon#about to read 6, iclass 5, count 0 2006.257.22:50:37.23#ibcon#read 6, iclass 5, count 0 2006.257.22:50:37.23#ibcon#end of sib2, iclass 5, count 0 2006.257.22:50:37.23#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:50:37.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:50:37.23#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.22:50:37.23#ibcon#*before write, iclass 5, count 0 2006.257.22:50:37.23#ibcon#enter sib2, iclass 5, count 0 2006.257.22:50:37.23#ibcon#flushed, iclass 5, count 0 2006.257.22:50:37.23#ibcon#about to write, iclass 5, count 0 2006.257.22:50:37.23#ibcon#wrote, iclass 5, count 0 2006.257.22:50:37.23#ibcon#about to read 3, iclass 5, count 0 2006.257.22:50:37.26#ibcon#read 3, iclass 5, count 0 2006.257.22:50:37.27#ibcon#about to read 4, iclass 5, count 0 2006.257.22:50:37.27#ibcon#read 4, iclass 5, count 0 2006.257.22:50:37.27#ibcon#about to read 5, iclass 5, count 0 2006.257.22:50:37.27#ibcon#read 5, iclass 5, count 0 2006.257.22:50:37.27#ibcon#about to read 6, iclass 5, count 0 2006.257.22:50:37.27#ibcon#read 6, iclass 5, count 0 2006.257.22:50:37.27#ibcon#end of sib2, iclass 5, count 0 2006.257.22:50:37.27#ibcon#*after write, iclass 5, count 0 2006.257.22:50:37.27#ibcon#*before return 0, iclass 5, count 0 2006.257.22:50:37.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:37.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:37.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:50:37.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:50:37.27$vck44/va=6,4 2006.257.22:50:37.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.22:50:37.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.22:50:37.27#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:37.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:37.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:37.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:37.33#ibcon#enter wrdev, iclass 7, count 2 2006.257.22:50:37.33#ibcon#first serial, iclass 7, count 2 2006.257.22:50:37.33#ibcon#enter sib2, iclass 7, count 2 2006.257.22:50:37.33#ibcon#flushed, iclass 7, count 2 2006.257.22:50:37.33#ibcon#about to write, iclass 7, count 2 2006.257.22:50:37.33#ibcon#wrote, iclass 7, count 2 2006.257.22:50:37.33#ibcon#about to read 3, iclass 7, count 2 2006.257.22:50:37.34#ibcon#read 3, iclass 7, count 2 2006.257.22:50:37.35#ibcon#about to read 4, iclass 7, count 2 2006.257.22:50:37.35#ibcon#read 4, iclass 7, count 2 2006.257.22:50:37.35#ibcon#about to read 5, iclass 7, count 2 2006.257.22:50:37.35#ibcon#read 5, iclass 7, count 2 2006.257.22:50:37.35#ibcon#about to read 6, iclass 7, count 2 2006.257.22:50:37.35#ibcon#read 6, iclass 7, count 2 2006.257.22:50:37.35#ibcon#end of sib2, iclass 7, count 2 2006.257.22:50:37.35#ibcon#*mode == 0, iclass 7, count 2 2006.257.22:50:37.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.22:50:37.35#ibcon#[25=AT06-04\r\n] 2006.257.22:50:37.35#ibcon#*before write, iclass 7, count 2 2006.257.22:50:37.35#ibcon#enter sib2, iclass 7, count 2 2006.257.22:50:37.35#ibcon#flushed, iclass 7, count 2 2006.257.22:50:37.35#ibcon#about to write, iclass 7, count 2 2006.257.22:50:37.35#ibcon#wrote, iclass 7, count 2 2006.257.22:50:37.35#ibcon#about to read 3, iclass 7, count 2 2006.257.22:50:37.37#ibcon#read 3, iclass 7, count 2 2006.257.22:50:37.38#ibcon#about to read 4, iclass 7, count 2 2006.257.22:50:37.38#ibcon#read 4, iclass 7, count 2 2006.257.22:50:37.38#ibcon#about to read 5, iclass 7, count 2 2006.257.22:50:37.38#ibcon#read 5, iclass 7, count 2 2006.257.22:50:37.38#ibcon#about to read 6, iclass 7, count 2 2006.257.22:50:37.38#ibcon#read 6, iclass 7, count 2 2006.257.22:50:37.38#ibcon#end of sib2, iclass 7, count 2 2006.257.22:50:37.38#ibcon#*after write, iclass 7, count 2 2006.257.22:50:37.38#ibcon#*before return 0, iclass 7, count 2 2006.257.22:50:37.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:37.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:37.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.22:50:37.38#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:37.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:37.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:37.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:37.50#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:50:37.50#ibcon#first serial, iclass 7, count 0 2006.257.22:50:37.50#ibcon#enter sib2, iclass 7, count 0 2006.257.22:50:37.50#ibcon#flushed, iclass 7, count 0 2006.257.22:50:37.50#ibcon#about to write, iclass 7, count 0 2006.257.22:50:37.50#ibcon#wrote, iclass 7, count 0 2006.257.22:50:37.50#ibcon#about to read 3, iclass 7, count 0 2006.257.22:50:37.51#ibcon#read 3, iclass 7, count 0 2006.257.22:50:37.52#ibcon#about to read 4, iclass 7, count 0 2006.257.22:50:37.52#ibcon#read 4, iclass 7, count 0 2006.257.22:50:37.52#ibcon#about to read 5, iclass 7, count 0 2006.257.22:50:37.52#ibcon#read 5, iclass 7, count 0 2006.257.22:50:37.52#ibcon#about to read 6, iclass 7, count 0 2006.257.22:50:37.52#ibcon#read 6, iclass 7, count 0 2006.257.22:50:37.52#ibcon#end of sib2, iclass 7, count 0 2006.257.22:50:37.52#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:50:37.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:50:37.52#ibcon#[25=USB\r\n] 2006.257.22:50:37.52#ibcon#*before write, iclass 7, count 0 2006.257.22:50:37.52#ibcon#enter sib2, iclass 7, count 0 2006.257.22:50:37.52#ibcon#flushed, iclass 7, count 0 2006.257.22:50:37.52#ibcon#about to write, iclass 7, count 0 2006.257.22:50:37.52#ibcon#wrote, iclass 7, count 0 2006.257.22:50:37.52#ibcon#about to read 3, iclass 7, count 0 2006.257.22:50:37.54#ibcon#read 3, iclass 7, count 0 2006.257.22:50:37.55#ibcon#about to read 4, iclass 7, count 0 2006.257.22:50:37.55#ibcon#read 4, iclass 7, count 0 2006.257.22:50:37.55#ibcon#about to read 5, iclass 7, count 0 2006.257.22:50:37.55#ibcon#read 5, iclass 7, count 0 2006.257.22:50:37.55#ibcon#about to read 6, iclass 7, count 0 2006.257.22:50:37.55#ibcon#read 6, iclass 7, count 0 2006.257.22:50:37.55#ibcon#end of sib2, iclass 7, count 0 2006.257.22:50:37.55#ibcon#*after write, iclass 7, count 0 2006.257.22:50:37.55#ibcon#*before return 0, iclass 7, count 0 2006.257.22:50:37.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:37.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:37.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:50:37.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:50:37.55$vck44/valo=7,864.99 2006.257.22:50:37.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.22:50:37.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.22:50:37.55#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:37.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:37.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:37.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:37.55#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:50:37.55#ibcon#first serial, iclass 11, count 0 2006.257.22:50:37.55#ibcon#enter sib2, iclass 11, count 0 2006.257.22:50:37.55#ibcon#flushed, iclass 11, count 0 2006.257.22:50:37.55#ibcon#about to write, iclass 11, count 0 2006.257.22:50:37.55#ibcon#wrote, iclass 11, count 0 2006.257.22:50:37.55#ibcon#about to read 3, iclass 11, count 0 2006.257.22:50:37.56#ibcon#read 3, iclass 11, count 0 2006.257.22:50:37.57#ibcon#about to read 4, iclass 11, count 0 2006.257.22:50:37.57#ibcon#read 4, iclass 11, count 0 2006.257.22:50:37.57#ibcon#about to read 5, iclass 11, count 0 2006.257.22:50:37.57#ibcon#read 5, iclass 11, count 0 2006.257.22:50:37.57#ibcon#about to read 6, iclass 11, count 0 2006.257.22:50:37.57#ibcon#read 6, iclass 11, count 0 2006.257.22:50:37.57#ibcon#end of sib2, iclass 11, count 0 2006.257.22:50:37.57#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:50:37.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:50:37.57#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.22:50:37.57#ibcon#*before write, iclass 11, count 0 2006.257.22:50:37.57#ibcon#enter sib2, iclass 11, count 0 2006.257.22:50:37.57#ibcon#flushed, iclass 11, count 0 2006.257.22:50:37.57#ibcon#about to write, iclass 11, count 0 2006.257.22:50:37.57#ibcon#wrote, iclass 11, count 0 2006.257.22:50:37.57#ibcon#about to read 3, iclass 11, count 0 2006.257.22:50:37.60#ibcon#read 3, iclass 11, count 0 2006.257.22:50:37.61#ibcon#about to read 4, iclass 11, count 0 2006.257.22:50:37.61#ibcon#read 4, iclass 11, count 0 2006.257.22:50:37.61#ibcon#about to read 5, iclass 11, count 0 2006.257.22:50:37.61#ibcon#read 5, iclass 11, count 0 2006.257.22:50:37.61#ibcon#about to read 6, iclass 11, count 0 2006.257.22:50:37.61#ibcon#read 6, iclass 11, count 0 2006.257.22:50:37.61#ibcon#end of sib2, iclass 11, count 0 2006.257.22:50:37.61#ibcon#*after write, iclass 11, count 0 2006.257.22:50:37.61#ibcon#*before return 0, iclass 11, count 0 2006.257.22:50:37.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:37.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:37.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:50:37.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:50:37.61$vck44/va=7,4 2006.257.22:50:37.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.22:50:37.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.22:50:37.61#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:37.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:37.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:37.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:37.67#ibcon#enter wrdev, iclass 13, count 2 2006.257.22:50:37.67#ibcon#first serial, iclass 13, count 2 2006.257.22:50:37.67#ibcon#enter sib2, iclass 13, count 2 2006.257.22:50:37.67#ibcon#flushed, iclass 13, count 2 2006.257.22:50:37.67#ibcon#about to write, iclass 13, count 2 2006.257.22:50:37.67#ibcon#wrote, iclass 13, count 2 2006.257.22:50:37.67#ibcon#about to read 3, iclass 13, count 2 2006.257.22:50:37.68#ibcon#read 3, iclass 13, count 2 2006.257.22:50:37.69#ibcon#about to read 4, iclass 13, count 2 2006.257.22:50:37.69#ibcon#read 4, iclass 13, count 2 2006.257.22:50:37.69#ibcon#about to read 5, iclass 13, count 2 2006.257.22:50:37.69#ibcon#read 5, iclass 13, count 2 2006.257.22:50:37.69#ibcon#about to read 6, iclass 13, count 2 2006.257.22:50:37.69#ibcon#read 6, iclass 13, count 2 2006.257.22:50:37.69#ibcon#end of sib2, iclass 13, count 2 2006.257.22:50:37.69#ibcon#*mode == 0, iclass 13, count 2 2006.257.22:50:37.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.22:50:37.69#ibcon#[25=AT07-04\r\n] 2006.257.22:50:37.69#ibcon#*before write, iclass 13, count 2 2006.257.22:50:37.69#ibcon#enter sib2, iclass 13, count 2 2006.257.22:50:37.69#ibcon#flushed, iclass 13, count 2 2006.257.22:50:37.69#ibcon#about to write, iclass 13, count 2 2006.257.22:50:37.69#ibcon#wrote, iclass 13, count 2 2006.257.22:50:37.69#ibcon#about to read 3, iclass 13, count 2 2006.257.22:50:37.71#ibcon#read 3, iclass 13, count 2 2006.257.22:50:37.72#ibcon#about to read 4, iclass 13, count 2 2006.257.22:50:37.72#ibcon#read 4, iclass 13, count 2 2006.257.22:50:37.72#ibcon#about to read 5, iclass 13, count 2 2006.257.22:50:37.72#ibcon#read 5, iclass 13, count 2 2006.257.22:50:37.72#ibcon#about to read 6, iclass 13, count 2 2006.257.22:50:37.72#ibcon#read 6, iclass 13, count 2 2006.257.22:50:37.72#ibcon#end of sib2, iclass 13, count 2 2006.257.22:50:37.72#ibcon#*after write, iclass 13, count 2 2006.257.22:50:37.72#ibcon#*before return 0, iclass 13, count 2 2006.257.22:50:37.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:37.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:37.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.22:50:37.72#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:37.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:37.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:37.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:37.84#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:50:37.84#ibcon#first serial, iclass 13, count 0 2006.257.22:50:37.84#ibcon#enter sib2, iclass 13, count 0 2006.257.22:50:37.84#ibcon#flushed, iclass 13, count 0 2006.257.22:50:37.84#ibcon#about to write, iclass 13, count 0 2006.257.22:50:37.84#ibcon#wrote, iclass 13, count 0 2006.257.22:50:37.84#ibcon#about to read 3, iclass 13, count 0 2006.257.22:50:37.85#ibcon#read 3, iclass 13, count 0 2006.257.22:50:37.86#ibcon#about to read 4, iclass 13, count 0 2006.257.22:50:37.86#ibcon#read 4, iclass 13, count 0 2006.257.22:50:37.86#ibcon#about to read 5, iclass 13, count 0 2006.257.22:50:37.86#ibcon#read 5, iclass 13, count 0 2006.257.22:50:37.86#ibcon#about to read 6, iclass 13, count 0 2006.257.22:50:37.86#ibcon#read 6, iclass 13, count 0 2006.257.22:50:37.86#ibcon#end of sib2, iclass 13, count 0 2006.257.22:50:37.86#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:50:37.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:50:37.86#ibcon#[25=USB\r\n] 2006.257.22:50:37.86#ibcon#*before write, iclass 13, count 0 2006.257.22:50:37.86#ibcon#enter sib2, iclass 13, count 0 2006.257.22:50:37.86#ibcon#flushed, iclass 13, count 0 2006.257.22:50:37.86#ibcon#about to write, iclass 13, count 0 2006.257.22:50:37.86#ibcon#wrote, iclass 13, count 0 2006.257.22:50:37.86#ibcon#about to read 3, iclass 13, count 0 2006.257.22:50:37.88#ibcon#read 3, iclass 13, count 0 2006.257.22:50:37.89#ibcon#about to read 4, iclass 13, count 0 2006.257.22:50:37.89#ibcon#read 4, iclass 13, count 0 2006.257.22:50:37.89#ibcon#about to read 5, iclass 13, count 0 2006.257.22:50:37.89#ibcon#read 5, iclass 13, count 0 2006.257.22:50:37.89#ibcon#about to read 6, iclass 13, count 0 2006.257.22:50:37.89#ibcon#read 6, iclass 13, count 0 2006.257.22:50:37.89#ibcon#end of sib2, iclass 13, count 0 2006.257.22:50:37.89#ibcon#*after write, iclass 13, count 0 2006.257.22:50:37.89#ibcon#*before return 0, iclass 13, count 0 2006.257.22:50:37.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:37.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:37.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:50:37.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:50:37.89$vck44/valo=8,884.99 2006.257.22:50:37.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.22:50:37.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.22:50:37.89#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:37.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:37.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:37.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:37.89#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:50:37.89#ibcon#first serial, iclass 15, count 0 2006.257.22:50:37.89#ibcon#enter sib2, iclass 15, count 0 2006.257.22:50:37.89#ibcon#flushed, iclass 15, count 0 2006.257.22:50:37.89#ibcon#about to write, iclass 15, count 0 2006.257.22:50:37.89#ibcon#wrote, iclass 15, count 0 2006.257.22:50:37.89#ibcon#about to read 3, iclass 15, count 0 2006.257.22:50:37.90#ibcon#read 3, iclass 15, count 0 2006.257.22:50:37.91#ibcon#about to read 4, iclass 15, count 0 2006.257.22:50:37.91#ibcon#read 4, iclass 15, count 0 2006.257.22:50:37.91#ibcon#about to read 5, iclass 15, count 0 2006.257.22:50:37.91#ibcon#read 5, iclass 15, count 0 2006.257.22:50:37.91#ibcon#about to read 6, iclass 15, count 0 2006.257.22:50:37.91#ibcon#read 6, iclass 15, count 0 2006.257.22:50:37.91#ibcon#end of sib2, iclass 15, count 0 2006.257.22:50:37.91#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:50:37.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:50:37.91#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.22:50:37.91#ibcon#*before write, iclass 15, count 0 2006.257.22:50:37.91#ibcon#enter sib2, iclass 15, count 0 2006.257.22:50:37.91#ibcon#flushed, iclass 15, count 0 2006.257.22:50:37.91#ibcon#about to write, iclass 15, count 0 2006.257.22:50:37.91#ibcon#wrote, iclass 15, count 0 2006.257.22:50:37.91#ibcon#about to read 3, iclass 15, count 0 2006.257.22:50:37.94#ibcon#read 3, iclass 15, count 0 2006.257.22:50:37.95#ibcon#about to read 4, iclass 15, count 0 2006.257.22:50:37.95#ibcon#read 4, iclass 15, count 0 2006.257.22:50:37.95#ibcon#about to read 5, iclass 15, count 0 2006.257.22:50:37.95#ibcon#read 5, iclass 15, count 0 2006.257.22:50:37.95#ibcon#about to read 6, iclass 15, count 0 2006.257.22:50:37.95#ibcon#read 6, iclass 15, count 0 2006.257.22:50:37.95#ibcon#end of sib2, iclass 15, count 0 2006.257.22:50:37.95#ibcon#*after write, iclass 15, count 0 2006.257.22:50:37.95#ibcon#*before return 0, iclass 15, count 0 2006.257.22:50:37.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:37.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:37.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:50:37.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:50:37.95$vck44/va=8,4 2006.257.22:50:37.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.22:50:37.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.22:50:37.95#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:37.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:38.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:38.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:38.01#ibcon#enter wrdev, iclass 17, count 2 2006.257.22:50:38.01#ibcon#first serial, iclass 17, count 2 2006.257.22:50:38.01#ibcon#enter sib2, iclass 17, count 2 2006.257.22:50:38.01#ibcon#flushed, iclass 17, count 2 2006.257.22:50:38.01#ibcon#about to write, iclass 17, count 2 2006.257.22:50:38.01#ibcon#wrote, iclass 17, count 2 2006.257.22:50:38.01#ibcon#about to read 3, iclass 17, count 2 2006.257.22:50:38.02#ibcon#read 3, iclass 17, count 2 2006.257.22:50:38.03#ibcon#about to read 4, iclass 17, count 2 2006.257.22:50:38.03#ibcon#read 4, iclass 17, count 2 2006.257.22:50:38.03#ibcon#about to read 5, iclass 17, count 2 2006.257.22:50:38.03#ibcon#read 5, iclass 17, count 2 2006.257.22:50:38.03#ibcon#about to read 6, iclass 17, count 2 2006.257.22:50:38.03#ibcon#read 6, iclass 17, count 2 2006.257.22:50:38.03#ibcon#end of sib2, iclass 17, count 2 2006.257.22:50:38.03#ibcon#*mode == 0, iclass 17, count 2 2006.257.22:50:38.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.22:50:38.03#ibcon#[25=AT08-04\r\n] 2006.257.22:50:38.03#ibcon#*before write, iclass 17, count 2 2006.257.22:50:38.03#ibcon#enter sib2, iclass 17, count 2 2006.257.22:50:38.03#ibcon#flushed, iclass 17, count 2 2006.257.22:50:38.03#ibcon#about to write, iclass 17, count 2 2006.257.22:50:38.03#ibcon#wrote, iclass 17, count 2 2006.257.22:50:38.03#ibcon#about to read 3, iclass 17, count 2 2006.257.22:50:38.05#ibcon#read 3, iclass 17, count 2 2006.257.22:50:38.06#ibcon#about to read 4, iclass 17, count 2 2006.257.22:50:38.06#ibcon#read 4, iclass 17, count 2 2006.257.22:50:38.06#ibcon#about to read 5, iclass 17, count 2 2006.257.22:50:38.06#ibcon#read 5, iclass 17, count 2 2006.257.22:50:38.06#ibcon#about to read 6, iclass 17, count 2 2006.257.22:50:38.06#ibcon#read 6, iclass 17, count 2 2006.257.22:50:38.06#ibcon#end of sib2, iclass 17, count 2 2006.257.22:50:38.06#ibcon#*after write, iclass 17, count 2 2006.257.22:50:38.06#ibcon#*before return 0, iclass 17, count 2 2006.257.22:50:38.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:38.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:38.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.22:50:38.06#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:38.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:38.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:38.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:38.18#ibcon#enter wrdev, iclass 17, count 0 2006.257.22:50:38.18#ibcon#first serial, iclass 17, count 0 2006.257.22:50:38.18#ibcon#enter sib2, iclass 17, count 0 2006.257.22:50:38.18#ibcon#flushed, iclass 17, count 0 2006.257.22:50:38.18#ibcon#about to write, iclass 17, count 0 2006.257.22:50:38.18#ibcon#wrote, iclass 17, count 0 2006.257.22:50:38.18#ibcon#about to read 3, iclass 17, count 0 2006.257.22:50:38.19#ibcon#read 3, iclass 17, count 0 2006.257.22:50:38.20#ibcon#about to read 4, iclass 17, count 0 2006.257.22:50:38.20#ibcon#read 4, iclass 17, count 0 2006.257.22:50:38.20#ibcon#about to read 5, iclass 17, count 0 2006.257.22:50:38.20#ibcon#read 5, iclass 17, count 0 2006.257.22:50:38.20#ibcon#about to read 6, iclass 17, count 0 2006.257.22:50:38.20#ibcon#read 6, iclass 17, count 0 2006.257.22:50:38.20#ibcon#end of sib2, iclass 17, count 0 2006.257.22:50:38.20#ibcon#*mode == 0, iclass 17, count 0 2006.257.22:50:38.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.22:50:38.20#ibcon#[25=USB\r\n] 2006.257.22:50:38.20#ibcon#*before write, iclass 17, count 0 2006.257.22:50:38.20#ibcon#enter sib2, iclass 17, count 0 2006.257.22:50:38.20#ibcon#flushed, iclass 17, count 0 2006.257.22:50:38.20#ibcon#about to write, iclass 17, count 0 2006.257.22:50:38.20#ibcon#wrote, iclass 17, count 0 2006.257.22:50:38.20#ibcon#about to read 3, iclass 17, count 0 2006.257.22:50:38.22#ibcon#read 3, iclass 17, count 0 2006.257.22:50:38.23#ibcon#about to read 4, iclass 17, count 0 2006.257.22:50:38.23#ibcon#read 4, iclass 17, count 0 2006.257.22:50:38.23#ibcon#about to read 5, iclass 17, count 0 2006.257.22:50:38.23#ibcon#read 5, iclass 17, count 0 2006.257.22:50:38.23#ibcon#about to read 6, iclass 17, count 0 2006.257.22:50:38.23#ibcon#read 6, iclass 17, count 0 2006.257.22:50:38.23#ibcon#end of sib2, iclass 17, count 0 2006.257.22:50:38.23#ibcon#*after write, iclass 17, count 0 2006.257.22:50:38.23#ibcon#*before return 0, iclass 17, count 0 2006.257.22:50:38.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:38.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:38.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.22:50:38.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.22:50:38.23$vck44/vblo=1,629.99 2006.257.22:50:38.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.22:50:38.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.22:50:38.23#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:38.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:38.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:38.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:38.23#ibcon#enter wrdev, iclass 19, count 0 2006.257.22:50:38.23#ibcon#first serial, iclass 19, count 0 2006.257.22:50:38.23#ibcon#enter sib2, iclass 19, count 0 2006.257.22:50:38.23#ibcon#flushed, iclass 19, count 0 2006.257.22:50:38.23#ibcon#about to write, iclass 19, count 0 2006.257.22:50:38.23#ibcon#wrote, iclass 19, count 0 2006.257.22:50:38.23#ibcon#about to read 3, iclass 19, count 0 2006.257.22:50:38.24#ibcon#read 3, iclass 19, count 0 2006.257.22:50:38.25#ibcon#about to read 4, iclass 19, count 0 2006.257.22:50:38.25#ibcon#read 4, iclass 19, count 0 2006.257.22:50:38.25#ibcon#about to read 5, iclass 19, count 0 2006.257.22:50:38.25#ibcon#read 5, iclass 19, count 0 2006.257.22:50:38.25#ibcon#about to read 6, iclass 19, count 0 2006.257.22:50:38.25#ibcon#read 6, iclass 19, count 0 2006.257.22:50:38.25#ibcon#end of sib2, iclass 19, count 0 2006.257.22:50:38.25#ibcon#*mode == 0, iclass 19, count 0 2006.257.22:50:38.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.22:50:38.25#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.22:50:38.25#ibcon#*before write, iclass 19, count 0 2006.257.22:50:38.25#ibcon#enter sib2, iclass 19, count 0 2006.257.22:50:38.25#ibcon#flushed, iclass 19, count 0 2006.257.22:50:38.25#ibcon#about to write, iclass 19, count 0 2006.257.22:50:38.25#ibcon#wrote, iclass 19, count 0 2006.257.22:50:38.25#ibcon#about to read 3, iclass 19, count 0 2006.257.22:50:38.28#ibcon#read 3, iclass 19, count 0 2006.257.22:50:38.29#ibcon#about to read 4, iclass 19, count 0 2006.257.22:50:38.29#ibcon#read 4, iclass 19, count 0 2006.257.22:50:38.29#ibcon#about to read 5, iclass 19, count 0 2006.257.22:50:38.29#ibcon#read 5, iclass 19, count 0 2006.257.22:50:38.29#ibcon#about to read 6, iclass 19, count 0 2006.257.22:50:38.29#ibcon#read 6, iclass 19, count 0 2006.257.22:50:38.29#ibcon#end of sib2, iclass 19, count 0 2006.257.22:50:38.29#ibcon#*after write, iclass 19, count 0 2006.257.22:50:38.29#ibcon#*before return 0, iclass 19, count 0 2006.257.22:50:38.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:38.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:38.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.22:50:38.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.22:50:38.29$vck44/vb=1,4 2006.257.22:50:38.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.22:50:38.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.22:50:38.29#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:38.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:50:38.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:50:38.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:50:38.29#ibcon#enter wrdev, iclass 21, count 2 2006.257.22:50:38.29#ibcon#first serial, iclass 21, count 2 2006.257.22:50:38.29#ibcon#enter sib2, iclass 21, count 2 2006.257.22:50:38.29#ibcon#flushed, iclass 21, count 2 2006.257.22:50:38.29#ibcon#about to write, iclass 21, count 2 2006.257.22:50:38.29#ibcon#wrote, iclass 21, count 2 2006.257.22:50:38.29#ibcon#about to read 3, iclass 21, count 2 2006.257.22:50:38.30#ibcon#read 3, iclass 21, count 2 2006.257.22:50:38.31#ibcon#about to read 4, iclass 21, count 2 2006.257.22:50:38.31#ibcon#read 4, iclass 21, count 2 2006.257.22:50:38.31#ibcon#about to read 5, iclass 21, count 2 2006.257.22:50:38.31#ibcon#read 5, iclass 21, count 2 2006.257.22:50:38.31#ibcon#about to read 6, iclass 21, count 2 2006.257.22:50:38.31#ibcon#read 6, iclass 21, count 2 2006.257.22:50:38.31#ibcon#end of sib2, iclass 21, count 2 2006.257.22:50:38.31#ibcon#*mode == 0, iclass 21, count 2 2006.257.22:50:38.31#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.22:50:38.31#ibcon#[27=AT01-04\r\n] 2006.257.22:50:38.31#ibcon#*before write, iclass 21, count 2 2006.257.22:50:38.31#ibcon#enter sib2, iclass 21, count 2 2006.257.22:50:38.31#ibcon#flushed, iclass 21, count 2 2006.257.22:50:38.31#ibcon#about to write, iclass 21, count 2 2006.257.22:50:38.31#ibcon#wrote, iclass 21, count 2 2006.257.22:50:38.31#ibcon#about to read 3, iclass 21, count 2 2006.257.22:50:38.33#ibcon#read 3, iclass 21, count 2 2006.257.22:50:38.34#ibcon#about to read 4, iclass 21, count 2 2006.257.22:50:38.34#ibcon#read 4, iclass 21, count 2 2006.257.22:50:38.34#ibcon#about to read 5, iclass 21, count 2 2006.257.22:50:38.34#ibcon#read 5, iclass 21, count 2 2006.257.22:50:38.34#ibcon#about to read 6, iclass 21, count 2 2006.257.22:50:38.34#ibcon#read 6, iclass 21, count 2 2006.257.22:50:38.34#ibcon#end of sib2, iclass 21, count 2 2006.257.22:50:38.34#ibcon#*after write, iclass 21, count 2 2006.257.22:50:38.34#ibcon#*before return 0, iclass 21, count 2 2006.257.22:50:38.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:50:38.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.22:50:38.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.22:50:38.34#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:38.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:50:38.45#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:50:38.45#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:50:38.46#ibcon#enter wrdev, iclass 21, count 0 2006.257.22:50:38.46#ibcon#first serial, iclass 21, count 0 2006.257.22:50:38.46#ibcon#enter sib2, iclass 21, count 0 2006.257.22:50:38.46#ibcon#flushed, iclass 21, count 0 2006.257.22:50:38.46#ibcon#about to write, iclass 21, count 0 2006.257.22:50:38.46#ibcon#wrote, iclass 21, count 0 2006.257.22:50:38.46#ibcon#about to read 3, iclass 21, count 0 2006.257.22:50:38.47#ibcon#read 3, iclass 21, count 0 2006.257.22:50:38.48#ibcon#about to read 4, iclass 21, count 0 2006.257.22:50:38.48#ibcon#read 4, iclass 21, count 0 2006.257.22:50:38.48#ibcon#about to read 5, iclass 21, count 0 2006.257.22:50:38.48#ibcon#read 5, iclass 21, count 0 2006.257.22:50:38.48#ibcon#about to read 6, iclass 21, count 0 2006.257.22:50:38.48#ibcon#read 6, iclass 21, count 0 2006.257.22:50:38.48#ibcon#end of sib2, iclass 21, count 0 2006.257.22:50:38.48#ibcon#*mode == 0, iclass 21, count 0 2006.257.22:50:38.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.22:50:38.48#ibcon#[27=USB\r\n] 2006.257.22:50:38.48#ibcon#*before write, iclass 21, count 0 2006.257.22:50:38.48#ibcon#enter sib2, iclass 21, count 0 2006.257.22:50:38.48#ibcon#flushed, iclass 21, count 0 2006.257.22:50:38.48#ibcon#about to write, iclass 21, count 0 2006.257.22:50:38.48#ibcon#wrote, iclass 21, count 0 2006.257.22:50:38.48#ibcon#about to read 3, iclass 21, count 0 2006.257.22:50:38.50#ibcon#read 3, iclass 21, count 0 2006.257.22:50:38.51#ibcon#about to read 4, iclass 21, count 0 2006.257.22:50:38.51#ibcon#read 4, iclass 21, count 0 2006.257.22:50:38.51#ibcon#about to read 5, iclass 21, count 0 2006.257.22:50:38.51#ibcon#read 5, iclass 21, count 0 2006.257.22:50:38.51#ibcon#about to read 6, iclass 21, count 0 2006.257.22:50:38.51#ibcon#read 6, iclass 21, count 0 2006.257.22:50:38.51#ibcon#end of sib2, iclass 21, count 0 2006.257.22:50:38.51#ibcon#*after write, iclass 21, count 0 2006.257.22:50:38.51#ibcon#*before return 0, iclass 21, count 0 2006.257.22:50:38.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:50:38.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.22:50:38.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.22:50:38.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.22:50:38.51$vck44/vblo=2,634.99 2006.257.22:50:38.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.22:50:38.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.22:50:38.51#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:38.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:50:38.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:50:38.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:50:38.51#ibcon#enter wrdev, iclass 24, count 0 2006.257.22:50:38.51#ibcon#first serial, iclass 24, count 0 2006.257.22:50:38.51#ibcon#enter sib2, iclass 24, count 0 2006.257.22:50:38.51#ibcon#flushed, iclass 24, count 0 2006.257.22:50:38.51#ibcon#about to write, iclass 24, count 0 2006.257.22:50:38.51#ibcon#wrote, iclass 24, count 0 2006.257.22:50:38.51#ibcon#about to read 3, iclass 24, count 0 2006.257.22:50:38.52#ibcon#read 3, iclass 24, count 0 2006.257.22:50:38.53#ibcon#about to read 4, iclass 24, count 0 2006.257.22:50:38.53#ibcon#read 4, iclass 24, count 0 2006.257.22:50:38.53#ibcon#about to read 5, iclass 24, count 0 2006.257.22:50:38.53#ibcon#read 5, iclass 24, count 0 2006.257.22:50:38.53#ibcon#about to read 6, iclass 24, count 0 2006.257.22:50:38.53#ibcon#read 6, iclass 24, count 0 2006.257.22:50:38.53#ibcon#end of sib2, iclass 24, count 0 2006.257.22:50:38.53#ibcon#*mode == 0, iclass 24, count 0 2006.257.22:50:38.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.22:50:38.53#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.22:50:38.53#ibcon#*before write, iclass 24, count 0 2006.257.22:50:38.53#ibcon#enter sib2, iclass 24, count 0 2006.257.22:50:38.53#ibcon#flushed, iclass 24, count 0 2006.257.22:50:38.53#ibcon#about to write, iclass 24, count 0 2006.257.22:50:38.53#ibcon#wrote, iclass 24, count 0 2006.257.22:50:38.53#ibcon#about to read 3, iclass 24, count 0 2006.257.22:50:38.56#ibcon#read 3, iclass 24, count 0 2006.257.22:50:38.57#ibcon#about to read 4, iclass 24, count 0 2006.257.22:50:38.57#ibcon#read 4, iclass 24, count 0 2006.257.22:50:38.57#ibcon#about to read 5, iclass 24, count 0 2006.257.22:50:38.57#ibcon#read 5, iclass 24, count 0 2006.257.22:50:38.57#ibcon#about to read 6, iclass 24, count 0 2006.257.22:50:38.57#ibcon#read 6, iclass 24, count 0 2006.257.22:50:38.57#ibcon#end of sib2, iclass 24, count 0 2006.257.22:50:38.57#ibcon#*after write, iclass 24, count 0 2006.257.22:50:38.57#ibcon#*before return 0, iclass 24, count 0 2006.257.22:50:38.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:50:38.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.22:50:38.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.22:50:38.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.22:50:38.57$vck44/vb=2,5 2006.257.22:50:38.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.22:50:38.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.22:50:38.57#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:38.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:50:38.59#abcon#<5=/14 1.2 3.3 19.78 851015.9\r\n> 2006.257.22:50:38.61#abcon#{5=INTERFACE CLEAR} 2006.257.22:50:38.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:50:38.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:50:38.63#ibcon#enter wrdev, iclass 26, count 2 2006.257.22:50:38.63#ibcon#first serial, iclass 26, count 2 2006.257.22:50:38.63#ibcon#enter sib2, iclass 26, count 2 2006.257.22:50:38.63#ibcon#flushed, iclass 26, count 2 2006.257.22:50:38.63#ibcon#about to write, iclass 26, count 2 2006.257.22:50:38.63#ibcon#wrote, iclass 26, count 2 2006.257.22:50:38.63#ibcon#about to read 3, iclass 26, count 2 2006.257.22:50:38.64#ibcon#read 3, iclass 26, count 2 2006.257.22:50:38.65#ibcon#about to read 4, iclass 26, count 2 2006.257.22:50:38.65#ibcon#read 4, iclass 26, count 2 2006.257.22:50:38.65#ibcon#about to read 5, iclass 26, count 2 2006.257.22:50:38.65#ibcon#read 5, iclass 26, count 2 2006.257.22:50:38.65#ibcon#about to read 6, iclass 26, count 2 2006.257.22:50:38.65#ibcon#read 6, iclass 26, count 2 2006.257.22:50:38.65#ibcon#end of sib2, iclass 26, count 2 2006.257.22:50:38.65#ibcon#*mode == 0, iclass 26, count 2 2006.257.22:50:38.65#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.22:50:38.65#ibcon#[27=AT02-05\r\n] 2006.257.22:50:38.65#ibcon#*before write, iclass 26, count 2 2006.257.22:50:38.65#ibcon#enter sib2, iclass 26, count 2 2006.257.22:50:38.65#ibcon#flushed, iclass 26, count 2 2006.257.22:50:38.65#ibcon#about to write, iclass 26, count 2 2006.257.22:50:38.65#ibcon#wrote, iclass 26, count 2 2006.257.22:50:38.65#ibcon#about to read 3, iclass 26, count 2 2006.257.22:50:38.67#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:50:38.67#ibcon#read 3, iclass 26, count 2 2006.257.22:50:38.68#ibcon#about to read 4, iclass 26, count 2 2006.257.22:50:38.68#ibcon#read 4, iclass 26, count 2 2006.257.22:50:38.68#ibcon#about to read 5, iclass 26, count 2 2006.257.22:50:38.68#ibcon#read 5, iclass 26, count 2 2006.257.22:50:38.68#ibcon#about to read 6, iclass 26, count 2 2006.257.22:50:38.68#ibcon#read 6, iclass 26, count 2 2006.257.22:50:38.68#ibcon#end of sib2, iclass 26, count 2 2006.257.22:50:38.68#ibcon#*after write, iclass 26, count 2 2006.257.22:50:38.68#ibcon#*before return 0, iclass 26, count 2 2006.257.22:50:38.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:50:38.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.22:50:38.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.22:50:38.68#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:38.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:50:38.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:50:38.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:50:38.80#ibcon#enter wrdev, iclass 26, count 0 2006.257.22:50:38.80#ibcon#first serial, iclass 26, count 0 2006.257.22:50:38.80#ibcon#enter sib2, iclass 26, count 0 2006.257.22:50:38.80#ibcon#flushed, iclass 26, count 0 2006.257.22:50:38.80#ibcon#about to write, iclass 26, count 0 2006.257.22:50:38.80#ibcon#wrote, iclass 26, count 0 2006.257.22:50:38.80#ibcon#about to read 3, iclass 26, count 0 2006.257.22:50:38.81#ibcon#read 3, iclass 26, count 0 2006.257.22:50:38.82#ibcon#about to read 4, iclass 26, count 0 2006.257.22:50:38.82#ibcon#read 4, iclass 26, count 0 2006.257.22:50:38.82#ibcon#about to read 5, iclass 26, count 0 2006.257.22:50:38.82#ibcon#read 5, iclass 26, count 0 2006.257.22:50:38.82#ibcon#about to read 6, iclass 26, count 0 2006.257.22:50:38.82#ibcon#read 6, iclass 26, count 0 2006.257.22:50:38.82#ibcon#end of sib2, iclass 26, count 0 2006.257.22:50:38.82#ibcon#*mode == 0, iclass 26, count 0 2006.257.22:50:38.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.22:50:38.82#ibcon#[27=USB\r\n] 2006.257.22:50:38.82#ibcon#*before write, iclass 26, count 0 2006.257.22:50:38.82#ibcon#enter sib2, iclass 26, count 0 2006.257.22:50:38.82#ibcon#flushed, iclass 26, count 0 2006.257.22:50:38.82#ibcon#about to write, iclass 26, count 0 2006.257.22:50:38.82#ibcon#wrote, iclass 26, count 0 2006.257.22:50:38.82#ibcon#about to read 3, iclass 26, count 0 2006.257.22:50:38.84#ibcon#read 3, iclass 26, count 0 2006.257.22:50:38.85#ibcon#about to read 4, iclass 26, count 0 2006.257.22:50:38.85#ibcon#read 4, iclass 26, count 0 2006.257.22:50:38.85#ibcon#about to read 5, iclass 26, count 0 2006.257.22:50:38.85#ibcon#read 5, iclass 26, count 0 2006.257.22:50:38.85#ibcon#about to read 6, iclass 26, count 0 2006.257.22:50:38.85#ibcon#read 6, iclass 26, count 0 2006.257.22:50:38.85#ibcon#end of sib2, iclass 26, count 0 2006.257.22:50:38.85#ibcon#*after write, iclass 26, count 0 2006.257.22:50:38.85#ibcon#*before return 0, iclass 26, count 0 2006.257.22:50:38.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:50:38.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.22:50:38.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.22:50:38.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.22:50:38.85$vck44/vblo=3,649.99 2006.257.22:50:38.85#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.22:50:38.85#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.22:50:38.85#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:38.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:38.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:38.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:38.85#ibcon#enter wrdev, iclass 31, count 0 2006.257.22:50:38.85#ibcon#first serial, iclass 31, count 0 2006.257.22:50:38.85#ibcon#enter sib2, iclass 31, count 0 2006.257.22:50:38.85#ibcon#flushed, iclass 31, count 0 2006.257.22:50:38.85#ibcon#about to write, iclass 31, count 0 2006.257.22:50:38.85#ibcon#wrote, iclass 31, count 0 2006.257.22:50:38.85#ibcon#about to read 3, iclass 31, count 0 2006.257.22:50:38.86#ibcon#read 3, iclass 31, count 0 2006.257.22:50:38.87#ibcon#about to read 4, iclass 31, count 0 2006.257.22:50:38.87#ibcon#read 4, iclass 31, count 0 2006.257.22:50:38.87#ibcon#about to read 5, iclass 31, count 0 2006.257.22:50:38.87#ibcon#read 5, iclass 31, count 0 2006.257.22:50:38.87#ibcon#about to read 6, iclass 31, count 0 2006.257.22:50:38.87#ibcon#read 6, iclass 31, count 0 2006.257.22:50:38.87#ibcon#end of sib2, iclass 31, count 0 2006.257.22:50:38.87#ibcon#*mode == 0, iclass 31, count 0 2006.257.22:50:38.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.22:50:38.87#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.22:50:38.87#ibcon#*before write, iclass 31, count 0 2006.257.22:50:38.87#ibcon#enter sib2, iclass 31, count 0 2006.257.22:50:38.87#ibcon#flushed, iclass 31, count 0 2006.257.22:50:38.87#ibcon#about to write, iclass 31, count 0 2006.257.22:50:38.87#ibcon#wrote, iclass 31, count 0 2006.257.22:50:38.87#ibcon#about to read 3, iclass 31, count 0 2006.257.22:50:38.90#ibcon#read 3, iclass 31, count 0 2006.257.22:50:38.91#ibcon#about to read 4, iclass 31, count 0 2006.257.22:50:38.91#ibcon#read 4, iclass 31, count 0 2006.257.22:50:38.91#ibcon#about to read 5, iclass 31, count 0 2006.257.22:50:38.91#ibcon#read 5, iclass 31, count 0 2006.257.22:50:38.91#ibcon#about to read 6, iclass 31, count 0 2006.257.22:50:38.91#ibcon#read 6, iclass 31, count 0 2006.257.22:50:38.91#ibcon#end of sib2, iclass 31, count 0 2006.257.22:50:38.91#ibcon#*after write, iclass 31, count 0 2006.257.22:50:38.91#ibcon#*before return 0, iclass 31, count 0 2006.257.22:50:38.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:38.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.22:50:38.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.22:50:38.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.22:50:38.91$vck44/vb=3,4 2006.257.22:50:38.91#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.22:50:38.91#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.22:50:38.91#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:38.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:38.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:38.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:38.97#ibcon#enter wrdev, iclass 33, count 2 2006.257.22:50:38.97#ibcon#first serial, iclass 33, count 2 2006.257.22:50:38.97#ibcon#enter sib2, iclass 33, count 2 2006.257.22:50:38.97#ibcon#flushed, iclass 33, count 2 2006.257.22:50:38.97#ibcon#about to write, iclass 33, count 2 2006.257.22:50:38.97#ibcon#wrote, iclass 33, count 2 2006.257.22:50:38.97#ibcon#about to read 3, iclass 33, count 2 2006.257.22:50:38.98#ibcon#read 3, iclass 33, count 2 2006.257.22:50:38.99#ibcon#about to read 4, iclass 33, count 2 2006.257.22:50:38.99#ibcon#read 4, iclass 33, count 2 2006.257.22:50:38.99#ibcon#about to read 5, iclass 33, count 2 2006.257.22:50:38.99#ibcon#read 5, iclass 33, count 2 2006.257.22:50:38.99#ibcon#about to read 6, iclass 33, count 2 2006.257.22:50:38.99#ibcon#read 6, iclass 33, count 2 2006.257.22:50:38.99#ibcon#end of sib2, iclass 33, count 2 2006.257.22:50:38.99#ibcon#*mode == 0, iclass 33, count 2 2006.257.22:50:38.99#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.22:50:38.99#ibcon#[27=AT03-04\r\n] 2006.257.22:50:38.99#ibcon#*before write, iclass 33, count 2 2006.257.22:50:38.99#ibcon#enter sib2, iclass 33, count 2 2006.257.22:50:38.99#ibcon#flushed, iclass 33, count 2 2006.257.22:50:38.99#ibcon#about to write, iclass 33, count 2 2006.257.22:50:38.99#ibcon#wrote, iclass 33, count 2 2006.257.22:50:38.99#ibcon#about to read 3, iclass 33, count 2 2006.257.22:50:39.01#ibcon#read 3, iclass 33, count 2 2006.257.22:50:39.02#ibcon#about to read 4, iclass 33, count 2 2006.257.22:50:39.02#ibcon#read 4, iclass 33, count 2 2006.257.22:50:39.02#ibcon#about to read 5, iclass 33, count 2 2006.257.22:50:39.02#ibcon#read 5, iclass 33, count 2 2006.257.22:50:39.02#ibcon#about to read 6, iclass 33, count 2 2006.257.22:50:39.02#ibcon#read 6, iclass 33, count 2 2006.257.22:50:39.02#ibcon#end of sib2, iclass 33, count 2 2006.257.22:50:39.02#ibcon#*after write, iclass 33, count 2 2006.257.22:50:39.02#ibcon#*before return 0, iclass 33, count 2 2006.257.22:50:39.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:39.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.22:50:39.02#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.22:50:39.02#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:39.02#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:39.13#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:39.13#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:39.14#ibcon#enter wrdev, iclass 33, count 0 2006.257.22:50:39.14#ibcon#first serial, iclass 33, count 0 2006.257.22:50:39.14#ibcon#enter sib2, iclass 33, count 0 2006.257.22:50:39.14#ibcon#flushed, iclass 33, count 0 2006.257.22:50:39.14#ibcon#about to write, iclass 33, count 0 2006.257.22:50:39.14#ibcon#wrote, iclass 33, count 0 2006.257.22:50:39.14#ibcon#about to read 3, iclass 33, count 0 2006.257.22:50:39.15#ibcon#read 3, iclass 33, count 0 2006.257.22:50:39.16#ibcon#about to read 4, iclass 33, count 0 2006.257.22:50:39.16#ibcon#read 4, iclass 33, count 0 2006.257.22:50:39.16#ibcon#about to read 5, iclass 33, count 0 2006.257.22:50:39.16#ibcon#read 5, iclass 33, count 0 2006.257.22:50:39.16#ibcon#about to read 6, iclass 33, count 0 2006.257.22:50:39.16#ibcon#read 6, iclass 33, count 0 2006.257.22:50:39.16#ibcon#end of sib2, iclass 33, count 0 2006.257.22:50:39.16#ibcon#*mode == 0, iclass 33, count 0 2006.257.22:50:39.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.22:50:39.16#ibcon#[27=USB\r\n] 2006.257.22:50:39.16#ibcon#*before write, iclass 33, count 0 2006.257.22:50:39.16#ibcon#enter sib2, iclass 33, count 0 2006.257.22:50:39.16#ibcon#flushed, iclass 33, count 0 2006.257.22:50:39.16#ibcon#about to write, iclass 33, count 0 2006.257.22:50:39.16#ibcon#wrote, iclass 33, count 0 2006.257.22:50:39.16#ibcon#about to read 3, iclass 33, count 0 2006.257.22:50:39.18#ibcon#read 3, iclass 33, count 0 2006.257.22:50:39.19#ibcon#about to read 4, iclass 33, count 0 2006.257.22:50:39.19#ibcon#read 4, iclass 33, count 0 2006.257.22:50:39.19#ibcon#about to read 5, iclass 33, count 0 2006.257.22:50:39.19#ibcon#read 5, iclass 33, count 0 2006.257.22:50:39.19#ibcon#about to read 6, iclass 33, count 0 2006.257.22:50:39.19#ibcon#read 6, iclass 33, count 0 2006.257.22:50:39.19#ibcon#end of sib2, iclass 33, count 0 2006.257.22:50:39.19#ibcon#*after write, iclass 33, count 0 2006.257.22:50:39.19#ibcon#*before return 0, iclass 33, count 0 2006.257.22:50:39.19#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:39.19#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.22:50:39.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.22:50:39.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.22:50:39.19$vck44/vblo=4,679.99 2006.257.22:50:39.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.22:50:39.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.22:50:39.19#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:39.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:39.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:39.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:39.19#ibcon#enter wrdev, iclass 35, count 0 2006.257.22:50:39.19#ibcon#first serial, iclass 35, count 0 2006.257.22:50:39.19#ibcon#enter sib2, iclass 35, count 0 2006.257.22:50:39.19#ibcon#flushed, iclass 35, count 0 2006.257.22:50:39.19#ibcon#about to write, iclass 35, count 0 2006.257.22:50:39.19#ibcon#wrote, iclass 35, count 0 2006.257.22:50:39.19#ibcon#about to read 3, iclass 35, count 0 2006.257.22:50:39.20#ibcon#read 3, iclass 35, count 0 2006.257.22:50:39.21#ibcon#about to read 4, iclass 35, count 0 2006.257.22:50:39.21#ibcon#read 4, iclass 35, count 0 2006.257.22:50:39.21#ibcon#about to read 5, iclass 35, count 0 2006.257.22:50:39.21#ibcon#read 5, iclass 35, count 0 2006.257.22:50:39.21#ibcon#about to read 6, iclass 35, count 0 2006.257.22:50:39.21#ibcon#read 6, iclass 35, count 0 2006.257.22:50:39.21#ibcon#end of sib2, iclass 35, count 0 2006.257.22:50:39.21#ibcon#*mode == 0, iclass 35, count 0 2006.257.22:50:39.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.22:50:39.21#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.22:50:39.21#ibcon#*before write, iclass 35, count 0 2006.257.22:50:39.21#ibcon#enter sib2, iclass 35, count 0 2006.257.22:50:39.21#ibcon#flushed, iclass 35, count 0 2006.257.22:50:39.21#ibcon#about to write, iclass 35, count 0 2006.257.22:50:39.21#ibcon#wrote, iclass 35, count 0 2006.257.22:50:39.21#ibcon#about to read 3, iclass 35, count 0 2006.257.22:50:39.24#ibcon#read 3, iclass 35, count 0 2006.257.22:50:39.25#ibcon#about to read 4, iclass 35, count 0 2006.257.22:50:39.25#ibcon#read 4, iclass 35, count 0 2006.257.22:50:39.25#ibcon#about to read 5, iclass 35, count 0 2006.257.22:50:39.25#ibcon#read 5, iclass 35, count 0 2006.257.22:50:39.25#ibcon#about to read 6, iclass 35, count 0 2006.257.22:50:39.25#ibcon#read 6, iclass 35, count 0 2006.257.22:50:39.25#ibcon#end of sib2, iclass 35, count 0 2006.257.22:50:39.25#ibcon#*after write, iclass 35, count 0 2006.257.22:50:39.25#ibcon#*before return 0, iclass 35, count 0 2006.257.22:50:39.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:39.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.22:50:39.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.22:50:39.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.22:50:39.25$vck44/vb=4,5 2006.257.22:50:39.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.22:50:39.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.22:50:39.25#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:39.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:39.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:39.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:39.31#ibcon#enter wrdev, iclass 37, count 2 2006.257.22:50:39.31#ibcon#first serial, iclass 37, count 2 2006.257.22:50:39.31#ibcon#enter sib2, iclass 37, count 2 2006.257.22:50:39.31#ibcon#flushed, iclass 37, count 2 2006.257.22:50:39.31#ibcon#about to write, iclass 37, count 2 2006.257.22:50:39.31#ibcon#wrote, iclass 37, count 2 2006.257.22:50:39.31#ibcon#about to read 3, iclass 37, count 2 2006.257.22:50:39.32#ibcon#read 3, iclass 37, count 2 2006.257.22:50:39.33#ibcon#about to read 4, iclass 37, count 2 2006.257.22:50:39.33#ibcon#read 4, iclass 37, count 2 2006.257.22:50:39.33#ibcon#about to read 5, iclass 37, count 2 2006.257.22:50:39.33#ibcon#read 5, iclass 37, count 2 2006.257.22:50:39.33#ibcon#about to read 6, iclass 37, count 2 2006.257.22:50:39.33#ibcon#read 6, iclass 37, count 2 2006.257.22:50:39.33#ibcon#end of sib2, iclass 37, count 2 2006.257.22:50:39.33#ibcon#*mode == 0, iclass 37, count 2 2006.257.22:50:39.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.22:50:39.33#ibcon#[27=AT04-05\r\n] 2006.257.22:50:39.33#ibcon#*before write, iclass 37, count 2 2006.257.22:50:39.33#ibcon#enter sib2, iclass 37, count 2 2006.257.22:50:39.33#ibcon#flushed, iclass 37, count 2 2006.257.22:50:39.33#ibcon#about to write, iclass 37, count 2 2006.257.22:50:39.33#ibcon#wrote, iclass 37, count 2 2006.257.22:50:39.33#ibcon#about to read 3, iclass 37, count 2 2006.257.22:50:39.35#ibcon#read 3, iclass 37, count 2 2006.257.22:50:39.36#ibcon#about to read 4, iclass 37, count 2 2006.257.22:50:39.36#ibcon#read 4, iclass 37, count 2 2006.257.22:50:39.36#ibcon#about to read 5, iclass 37, count 2 2006.257.22:50:39.36#ibcon#read 5, iclass 37, count 2 2006.257.22:50:39.36#ibcon#about to read 6, iclass 37, count 2 2006.257.22:50:39.36#ibcon#read 6, iclass 37, count 2 2006.257.22:50:39.36#ibcon#end of sib2, iclass 37, count 2 2006.257.22:50:39.36#ibcon#*after write, iclass 37, count 2 2006.257.22:50:39.36#ibcon#*before return 0, iclass 37, count 2 2006.257.22:50:39.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:39.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.22:50:39.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.22:50:39.36#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:39.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:39.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:39.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:39.48#ibcon#enter wrdev, iclass 37, count 0 2006.257.22:50:39.48#ibcon#first serial, iclass 37, count 0 2006.257.22:50:39.48#ibcon#enter sib2, iclass 37, count 0 2006.257.22:50:39.48#ibcon#flushed, iclass 37, count 0 2006.257.22:50:39.48#ibcon#about to write, iclass 37, count 0 2006.257.22:50:39.48#ibcon#wrote, iclass 37, count 0 2006.257.22:50:39.48#ibcon#about to read 3, iclass 37, count 0 2006.257.22:50:39.49#ibcon#read 3, iclass 37, count 0 2006.257.22:50:39.50#ibcon#about to read 4, iclass 37, count 0 2006.257.22:50:39.50#ibcon#read 4, iclass 37, count 0 2006.257.22:50:39.50#ibcon#about to read 5, iclass 37, count 0 2006.257.22:50:39.50#ibcon#read 5, iclass 37, count 0 2006.257.22:50:39.50#ibcon#about to read 6, iclass 37, count 0 2006.257.22:50:39.50#ibcon#read 6, iclass 37, count 0 2006.257.22:50:39.50#ibcon#end of sib2, iclass 37, count 0 2006.257.22:50:39.50#ibcon#*mode == 0, iclass 37, count 0 2006.257.22:50:39.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.22:50:39.50#ibcon#[27=USB\r\n] 2006.257.22:50:39.50#ibcon#*before write, iclass 37, count 0 2006.257.22:50:39.50#ibcon#enter sib2, iclass 37, count 0 2006.257.22:50:39.50#ibcon#flushed, iclass 37, count 0 2006.257.22:50:39.50#ibcon#about to write, iclass 37, count 0 2006.257.22:50:39.50#ibcon#wrote, iclass 37, count 0 2006.257.22:50:39.50#ibcon#about to read 3, iclass 37, count 0 2006.257.22:50:39.52#ibcon#read 3, iclass 37, count 0 2006.257.22:50:39.53#ibcon#about to read 4, iclass 37, count 0 2006.257.22:50:39.53#ibcon#read 4, iclass 37, count 0 2006.257.22:50:39.53#ibcon#about to read 5, iclass 37, count 0 2006.257.22:50:39.53#ibcon#read 5, iclass 37, count 0 2006.257.22:50:39.53#ibcon#about to read 6, iclass 37, count 0 2006.257.22:50:39.53#ibcon#read 6, iclass 37, count 0 2006.257.22:50:39.53#ibcon#end of sib2, iclass 37, count 0 2006.257.22:50:39.53#ibcon#*after write, iclass 37, count 0 2006.257.22:50:39.53#ibcon#*before return 0, iclass 37, count 0 2006.257.22:50:39.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:39.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.22:50:39.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.22:50:39.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.22:50:39.53$vck44/vblo=5,709.99 2006.257.22:50:39.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.22:50:39.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.22:50:39.53#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:39.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:39.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:39.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:39.53#ibcon#enter wrdev, iclass 39, count 0 2006.257.22:50:39.53#ibcon#first serial, iclass 39, count 0 2006.257.22:50:39.53#ibcon#enter sib2, iclass 39, count 0 2006.257.22:50:39.53#ibcon#flushed, iclass 39, count 0 2006.257.22:50:39.53#ibcon#about to write, iclass 39, count 0 2006.257.22:50:39.53#ibcon#wrote, iclass 39, count 0 2006.257.22:50:39.53#ibcon#about to read 3, iclass 39, count 0 2006.257.22:50:39.54#ibcon#read 3, iclass 39, count 0 2006.257.22:50:39.55#ibcon#about to read 4, iclass 39, count 0 2006.257.22:50:39.55#ibcon#read 4, iclass 39, count 0 2006.257.22:50:39.55#ibcon#about to read 5, iclass 39, count 0 2006.257.22:50:39.55#ibcon#read 5, iclass 39, count 0 2006.257.22:50:39.55#ibcon#about to read 6, iclass 39, count 0 2006.257.22:50:39.55#ibcon#read 6, iclass 39, count 0 2006.257.22:50:39.55#ibcon#end of sib2, iclass 39, count 0 2006.257.22:50:39.55#ibcon#*mode == 0, iclass 39, count 0 2006.257.22:50:39.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.22:50:39.55#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.22:50:39.55#ibcon#*before write, iclass 39, count 0 2006.257.22:50:39.55#ibcon#enter sib2, iclass 39, count 0 2006.257.22:50:39.55#ibcon#flushed, iclass 39, count 0 2006.257.22:50:39.55#ibcon#about to write, iclass 39, count 0 2006.257.22:50:39.55#ibcon#wrote, iclass 39, count 0 2006.257.22:50:39.55#ibcon#about to read 3, iclass 39, count 0 2006.257.22:50:39.58#ibcon#read 3, iclass 39, count 0 2006.257.22:50:39.59#ibcon#about to read 4, iclass 39, count 0 2006.257.22:50:39.59#ibcon#read 4, iclass 39, count 0 2006.257.22:50:39.59#ibcon#about to read 5, iclass 39, count 0 2006.257.22:50:39.59#ibcon#read 5, iclass 39, count 0 2006.257.22:50:39.59#ibcon#about to read 6, iclass 39, count 0 2006.257.22:50:39.59#ibcon#read 6, iclass 39, count 0 2006.257.22:50:39.59#ibcon#end of sib2, iclass 39, count 0 2006.257.22:50:39.59#ibcon#*after write, iclass 39, count 0 2006.257.22:50:39.59#ibcon#*before return 0, iclass 39, count 0 2006.257.22:50:39.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:39.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.22:50:39.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.22:50:39.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.22:50:39.59$vck44/vb=5,4 2006.257.22:50:39.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.22:50:39.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.22:50:39.59#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:39.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:39.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:39.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:39.65#ibcon#enter wrdev, iclass 3, count 2 2006.257.22:50:39.65#ibcon#first serial, iclass 3, count 2 2006.257.22:50:39.65#ibcon#enter sib2, iclass 3, count 2 2006.257.22:50:39.65#ibcon#flushed, iclass 3, count 2 2006.257.22:50:39.65#ibcon#about to write, iclass 3, count 2 2006.257.22:50:39.65#ibcon#wrote, iclass 3, count 2 2006.257.22:50:39.65#ibcon#about to read 3, iclass 3, count 2 2006.257.22:50:39.66#ibcon#read 3, iclass 3, count 2 2006.257.22:50:39.67#ibcon#about to read 4, iclass 3, count 2 2006.257.22:50:39.67#ibcon#read 4, iclass 3, count 2 2006.257.22:50:39.67#ibcon#about to read 5, iclass 3, count 2 2006.257.22:50:39.67#ibcon#read 5, iclass 3, count 2 2006.257.22:50:39.67#ibcon#about to read 6, iclass 3, count 2 2006.257.22:50:39.67#ibcon#read 6, iclass 3, count 2 2006.257.22:50:39.67#ibcon#end of sib2, iclass 3, count 2 2006.257.22:50:39.67#ibcon#*mode == 0, iclass 3, count 2 2006.257.22:50:39.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.22:50:39.67#ibcon#[27=AT05-04\r\n] 2006.257.22:50:39.67#ibcon#*before write, iclass 3, count 2 2006.257.22:50:39.67#ibcon#enter sib2, iclass 3, count 2 2006.257.22:50:39.67#ibcon#flushed, iclass 3, count 2 2006.257.22:50:39.67#ibcon#about to write, iclass 3, count 2 2006.257.22:50:39.67#ibcon#wrote, iclass 3, count 2 2006.257.22:50:39.67#ibcon#about to read 3, iclass 3, count 2 2006.257.22:50:39.69#ibcon#read 3, iclass 3, count 2 2006.257.22:50:39.70#ibcon#about to read 4, iclass 3, count 2 2006.257.22:50:39.70#ibcon#read 4, iclass 3, count 2 2006.257.22:50:39.70#ibcon#about to read 5, iclass 3, count 2 2006.257.22:50:39.70#ibcon#read 5, iclass 3, count 2 2006.257.22:50:39.70#ibcon#about to read 6, iclass 3, count 2 2006.257.22:50:39.70#ibcon#read 6, iclass 3, count 2 2006.257.22:50:39.70#ibcon#end of sib2, iclass 3, count 2 2006.257.22:50:39.70#ibcon#*after write, iclass 3, count 2 2006.257.22:50:39.70#ibcon#*before return 0, iclass 3, count 2 2006.257.22:50:39.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:39.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.22:50:39.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.22:50:39.70#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:39.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:39.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:39.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:39.82#ibcon#enter wrdev, iclass 3, count 0 2006.257.22:50:39.82#ibcon#first serial, iclass 3, count 0 2006.257.22:50:39.82#ibcon#enter sib2, iclass 3, count 0 2006.257.22:50:39.82#ibcon#flushed, iclass 3, count 0 2006.257.22:50:39.82#ibcon#about to write, iclass 3, count 0 2006.257.22:50:39.82#ibcon#wrote, iclass 3, count 0 2006.257.22:50:39.82#ibcon#about to read 3, iclass 3, count 0 2006.257.22:50:39.83#ibcon#read 3, iclass 3, count 0 2006.257.22:50:39.84#ibcon#about to read 4, iclass 3, count 0 2006.257.22:50:39.84#ibcon#read 4, iclass 3, count 0 2006.257.22:50:39.84#ibcon#about to read 5, iclass 3, count 0 2006.257.22:50:39.84#ibcon#read 5, iclass 3, count 0 2006.257.22:50:39.84#ibcon#about to read 6, iclass 3, count 0 2006.257.22:50:39.84#ibcon#read 6, iclass 3, count 0 2006.257.22:50:39.84#ibcon#end of sib2, iclass 3, count 0 2006.257.22:50:39.84#ibcon#*mode == 0, iclass 3, count 0 2006.257.22:50:39.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.22:50:39.84#ibcon#[27=USB\r\n] 2006.257.22:50:39.84#ibcon#*before write, iclass 3, count 0 2006.257.22:50:39.84#ibcon#enter sib2, iclass 3, count 0 2006.257.22:50:39.84#ibcon#flushed, iclass 3, count 0 2006.257.22:50:39.84#ibcon#about to write, iclass 3, count 0 2006.257.22:50:39.84#ibcon#wrote, iclass 3, count 0 2006.257.22:50:39.84#ibcon#about to read 3, iclass 3, count 0 2006.257.22:50:39.86#ibcon#read 3, iclass 3, count 0 2006.257.22:50:39.87#ibcon#about to read 4, iclass 3, count 0 2006.257.22:50:39.87#ibcon#read 4, iclass 3, count 0 2006.257.22:50:39.87#ibcon#about to read 5, iclass 3, count 0 2006.257.22:50:39.87#ibcon#read 5, iclass 3, count 0 2006.257.22:50:39.87#ibcon#about to read 6, iclass 3, count 0 2006.257.22:50:39.87#ibcon#read 6, iclass 3, count 0 2006.257.22:50:39.87#ibcon#end of sib2, iclass 3, count 0 2006.257.22:50:39.87#ibcon#*after write, iclass 3, count 0 2006.257.22:50:39.87#ibcon#*before return 0, iclass 3, count 0 2006.257.22:50:39.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:39.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.22:50:39.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.22:50:39.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.22:50:39.87$vck44/vblo=6,719.99 2006.257.22:50:39.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.22:50:39.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.22:50:39.87#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:39.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:39.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:39.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:39.87#ibcon#enter wrdev, iclass 5, count 0 2006.257.22:50:39.87#ibcon#first serial, iclass 5, count 0 2006.257.22:50:39.87#ibcon#enter sib2, iclass 5, count 0 2006.257.22:50:39.87#ibcon#flushed, iclass 5, count 0 2006.257.22:50:39.87#ibcon#about to write, iclass 5, count 0 2006.257.22:50:39.87#ibcon#wrote, iclass 5, count 0 2006.257.22:50:39.87#ibcon#about to read 3, iclass 5, count 0 2006.257.22:50:39.88#ibcon#read 3, iclass 5, count 0 2006.257.22:50:39.89#ibcon#about to read 4, iclass 5, count 0 2006.257.22:50:39.89#ibcon#read 4, iclass 5, count 0 2006.257.22:50:39.89#ibcon#about to read 5, iclass 5, count 0 2006.257.22:50:39.89#ibcon#read 5, iclass 5, count 0 2006.257.22:50:39.89#ibcon#about to read 6, iclass 5, count 0 2006.257.22:50:39.89#ibcon#read 6, iclass 5, count 0 2006.257.22:50:39.89#ibcon#end of sib2, iclass 5, count 0 2006.257.22:50:39.89#ibcon#*mode == 0, iclass 5, count 0 2006.257.22:50:39.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.22:50:39.89#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.22:50:39.89#ibcon#*before write, iclass 5, count 0 2006.257.22:50:39.89#ibcon#enter sib2, iclass 5, count 0 2006.257.22:50:39.89#ibcon#flushed, iclass 5, count 0 2006.257.22:50:39.89#ibcon#about to write, iclass 5, count 0 2006.257.22:50:39.89#ibcon#wrote, iclass 5, count 0 2006.257.22:50:39.89#ibcon#about to read 3, iclass 5, count 0 2006.257.22:50:39.92#ibcon#read 3, iclass 5, count 0 2006.257.22:50:39.93#ibcon#about to read 4, iclass 5, count 0 2006.257.22:50:39.93#ibcon#read 4, iclass 5, count 0 2006.257.22:50:39.93#ibcon#about to read 5, iclass 5, count 0 2006.257.22:50:39.93#ibcon#read 5, iclass 5, count 0 2006.257.22:50:39.93#ibcon#about to read 6, iclass 5, count 0 2006.257.22:50:39.93#ibcon#read 6, iclass 5, count 0 2006.257.22:50:39.93#ibcon#end of sib2, iclass 5, count 0 2006.257.22:50:39.93#ibcon#*after write, iclass 5, count 0 2006.257.22:50:39.93#ibcon#*before return 0, iclass 5, count 0 2006.257.22:50:39.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:39.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.22:50:39.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.22:50:39.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.22:50:39.93$vck44/vb=6,4 2006.257.22:50:39.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.22:50:39.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.22:50:39.93#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:39.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:39.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:39.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:39.99#ibcon#enter wrdev, iclass 7, count 2 2006.257.22:50:39.99#ibcon#first serial, iclass 7, count 2 2006.257.22:50:39.99#ibcon#enter sib2, iclass 7, count 2 2006.257.22:50:39.99#ibcon#flushed, iclass 7, count 2 2006.257.22:50:39.99#ibcon#about to write, iclass 7, count 2 2006.257.22:50:39.99#ibcon#wrote, iclass 7, count 2 2006.257.22:50:39.99#ibcon#about to read 3, iclass 7, count 2 2006.257.22:50:40.00#ibcon#read 3, iclass 7, count 2 2006.257.22:50:40.01#ibcon#about to read 4, iclass 7, count 2 2006.257.22:50:40.01#ibcon#read 4, iclass 7, count 2 2006.257.22:50:40.01#ibcon#about to read 5, iclass 7, count 2 2006.257.22:50:40.01#ibcon#read 5, iclass 7, count 2 2006.257.22:50:40.01#ibcon#about to read 6, iclass 7, count 2 2006.257.22:50:40.01#ibcon#read 6, iclass 7, count 2 2006.257.22:50:40.01#ibcon#end of sib2, iclass 7, count 2 2006.257.22:50:40.01#ibcon#*mode == 0, iclass 7, count 2 2006.257.22:50:40.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.22:50:40.01#ibcon#[27=AT06-04\r\n] 2006.257.22:50:40.01#ibcon#*before write, iclass 7, count 2 2006.257.22:50:40.01#ibcon#enter sib2, iclass 7, count 2 2006.257.22:50:40.01#ibcon#flushed, iclass 7, count 2 2006.257.22:50:40.01#ibcon#about to write, iclass 7, count 2 2006.257.22:50:40.01#ibcon#wrote, iclass 7, count 2 2006.257.22:50:40.01#ibcon#about to read 3, iclass 7, count 2 2006.257.22:50:40.03#ibcon#read 3, iclass 7, count 2 2006.257.22:50:40.04#ibcon#about to read 4, iclass 7, count 2 2006.257.22:50:40.04#ibcon#read 4, iclass 7, count 2 2006.257.22:50:40.04#ibcon#about to read 5, iclass 7, count 2 2006.257.22:50:40.04#ibcon#read 5, iclass 7, count 2 2006.257.22:50:40.04#ibcon#about to read 6, iclass 7, count 2 2006.257.22:50:40.04#ibcon#read 6, iclass 7, count 2 2006.257.22:50:40.04#ibcon#end of sib2, iclass 7, count 2 2006.257.22:50:40.04#ibcon#*after write, iclass 7, count 2 2006.257.22:50:40.04#ibcon#*before return 0, iclass 7, count 2 2006.257.22:50:40.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:40.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.22:50:40.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.22:50:40.04#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:40.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:40.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:40.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:40.16#ibcon#enter wrdev, iclass 7, count 0 2006.257.22:50:40.16#ibcon#first serial, iclass 7, count 0 2006.257.22:50:40.16#ibcon#enter sib2, iclass 7, count 0 2006.257.22:50:40.16#ibcon#flushed, iclass 7, count 0 2006.257.22:50:40.16#ibcon#about to write, iclass 7, count 0 2006.257.22:50:40.16#ibcon#wrote, iclass 7, count 0 2006.257.22:50:40.16#ibcon#about to read 3, iclass 7, count 0 2006.257.22:50:40.17#ibcon#read 3, iclass 7, count 0 2006.257.22:50:40.18#ibcon#about to read 4, iclass 7, count 0 2006.257.22:50:40.18#ibcon#read 4, iclass 7, count 0 2006.257.22:50:40.18#ibcon#about to read 5, iclass 7, count 0 2006.257.22:50:40.18#ibcon#read 5, iclass 7, count 0 2006.257.22:50:40.18#ibcon#about to read 6, iclass 7, count 0 2006.257.22:50:40.18#ibcon#read 6, iclass 7, count 0 2006.257.22:50:40.18#ibcon#end of sib2, iclass 7, count 0 2006.257.22:50:40.18#ibcon#*mode == 0, iclass 7, count 0 2006.257.22:50:40.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.22:50:40.18#ibcon#[27=USB\r\n] 2006.257.22:50:40.18#ibcon#*before write, iclass 7, count 0 2006.257.22:50:40.18#ibcon#enter sib2, iclass 7, count 0 2006.257.22:50:40.18#ibcon#flushed, iclass 7, count 0 2006.257.22:50:40.18#ibcon#about to write, iclass 7, count 0 2006.257.22:50:40.18#ibcon#wrote, iclass 7, count 0 2006.257.22:50:40.18#ibcon#about to read 3, iclass 7, count 0 2006.257.22:50:40.20#ibcon#read 3, iclass 7, count 0 2006.257.22:50:40.21#ibcon#about to read 4, iclass 7, count 0 2006.257.22:50:40.21#ibcon#read 4, iclass 7, count 0 2006.257.22:50:40.21#ibcon#about to read 5, iclass 7, count 0 2006.257.22:50:40.21#ibcon#read 5, iclass 7, count 0 2006.257.22:50:40.21#ibcon#about to read 6, iclass 7, count 0 2006.257.22:50:40.21#ibcon#read 6, iclass 7, count 0 2006.257.22:50:40.21#ibcon#end of sib2, iclass 7, count 0 2006.257.22:50:40.21#ibcon#*after write, iclass 7, count 0 2006.257.22:50:40.21#ibcon#*before return 0, iclass 7, count 0 2006.257.22:50:40.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:40.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.22:50:40.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.22:50:40.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.22:50:40.21$vck44/vblo=7,734.99 2006.257.22:50:40.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.22:50:40.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.22:50:40.21#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:40.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:40.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:40.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:40.21#ibcon#enter wrdev, iclass 11, count 0 2006.257.22:50:40.21#ibcon#first serial, iclass 11, count 0 2006.257.22:50:40.21#ibcon#enter sib2, iclass 11, count 0 2006.257.22:50:40.21#ibcon#flushed, iclass 11, count 0 2006.257.22:50:40.21#ibcon#about to write, iclass 11, count 0 2006.257.22:50:40.21#ibcon#wrote, iclass 11, count 0 2006.257.22:50:40.21#ibcon#about to read 3, iclass 11, count 0 2006.257.22:50:40.22#ibcon#read 3, iclass 11, count 0 2006.257.22:50:40.23#ibcon#about to read 4, iclass 11, count 0 2006.257.22:50:40.23#ibcon#read 4, iclass 11, count 0 2006.257.22:50:40.23#ibcon#about to read 5, iclass 11, count 0 2006.257.22:50:40.23#ibcon#read 5, iclass 11, count 0 2006.257.22:50:40.23#ibcon#about to read 6, iclass 11, count 0 2006.257.22:50:40.23#ibcon#read 6, iclass 11, count 0 2006.257.22:50:40.23#ibcon#end of sib2, iclass 11, count 0 2006.257.22:50:40.23#ibcon#*mode == 0, iclass 11, count 0 2006.257.22:50:40.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.22:50:40.23#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.22:50:40.23#ibcon#*before write, iclass 11, count 0 2006.257.22:50:40.23#ibcon#enter sib2, iclass 11, count 0 2006.257.22:50:40.23#ibcon#flushed, iclass 11, count 0 2006.257.22:50:40.23#ibcon#about to write, iclass 11, count 0 2006.257.22:50:40.23#ibcon#wrote, iclass 11, count 0 2006.257.22:50:40.23#ibcon#about to read 3, iclass 11, count 0 2006.257.22:50:40.26#ibcon#read 3, iclass 11, count 0 2006.257.22:50:40.27#ibcon#about to read 4, iclass 11, count 0 2006.257.22:50:40.27#ibcon#read 4, iclass 11, count 0 2006.257.22:50:40.27#ibcon#about to read 5, iclass 11, count 0 2006.257.22:50:40.27#ibcon#read 5, iclass 11, count 0 2006.257.22:50:40.27#ibcon#about to read 6, iclass 11, count 0 2006.257.22:50:40.27#ibcon#read 6, iclass 11, count 0 2006.257.22:50:40.27#ibcon#end of sib2, iclass 11, count 0 2006.257.22:50:40.27#ibcon#*after write, iclass 11, count 0 2006.257.22:50:40.27#ibcon#*before return 0, iclass 11, count 0 2006.257.22:50:40.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:40.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.22:50:40.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.22:50:40.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.22:50:40.27$vck44/vb=7,4 2006.257.22:50:40.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.22:50:40.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.22:50:40.27#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:40.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:40.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:40.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:40.33#ibcon#enter wrdev, iclass 13, count 2 2006.257.22:50:40.33#ibcon#first serial, iclass 13, count 2 2006.257.22:50:40.33#ibcon#enter sib2, iclass 13, count 2 2006.257.22:50:40.33#ibcon#flushed, iclass 13, count 2 2006.257.22:50:40.33#ibcon#about to write, iclass 13, count 2 2006.257.22:50:40.33#ibcon#wrote, iclass 13, count 2 2006.257.22:50:40.33#ibcon#about to read 3, iclass 13, count 2 2006.257.22:50:40.34#ibcon#read 3, iclass 13, count 2 2006.257.22:50:40.35#ibcon#about to read 4, iclass 13, count 2 2006.257.22:50:40.35#ibcon#read 4, iclass 13, count 2 2006.257.22:50:40.35#ibcon#about to read 5, iclass 13, count 2 2006.257.22:50:40.35#ibcon#read 5, iclass 13, count 2 2006.257.22:50:40.35#ibcon#about to read 6, iclass 13, count 2 2006.257.22:50:40.35#ibcon#read 6, iclass 13, count 2 2006.257.22:50:40.35#ibcon#end of sib2, iclass 13, count 2 2006.257.22:50:40.35#ibcon#*mode == 0, iclass 13, count 2 2006.257.22:50:40.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.22:50:40.35#ibcon#[27=AT07-04\r\n] 2006.257.22:50:40.35#ibcon#*before write, iclass 13, count 2 2006.257.22:50:40.35#ibcon#enter sib2, iclass 13, count 2 2006.257.22:50:40.35#ibcon#flushed, iclass 13, count 2 2006.257.22:50:40.35#ibcon#about to write, iclass 13, count 2 2006.257.22:50:40.35#ibcon#wrote, iclass 13, count 2 2006.257.22:50:40.35#ibcon#about to read 3, iclass 13, count 2 2006.257.22:50:40.37#ibcon#read 3, iclass 13, count 2 2006.257.22:50:40.38#ibcon#about to read 4, iclass 13, count 2 2006.257.22:50:40.38#ibcon#read 4, iclass 13, count 2 2006.257.22:50:40.38#ibcon#about to read 5, iclass 13, count 2 2006.257.22:50:40.38#ibcon#read 5, iclass 13, count 2 2006.257.22:50:40.38#ibcon#about to read 6, iclass 13, count 2 2006.257.22:50:40.38#ibcon#read 6, iclass 13, count 2 2006.257.22:50:40.38#ibcon#end of sib2, iclass 13, count 2 2006.257.22:50:40.38#ibcon#*after write, iclass 13, count 2 2006.257.22:50:40.38#ibcon#*before return 0, iclass 13, count 2 2006.257.22:50:40.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:40.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.22:50:40.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.22:50:40.38#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:40.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:40.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:40.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:40.50#ibcon#enter wrdev, iclass 13, count 0 2006.257.22:50:40.50#ibcon#first serial, iclass 13, count 0 2006.257.22:50:40.50#ibcon#enter sib2, iclass 13, count 0 2006.257.22:50:40.50#ibcon#flushed, iclass 13, count 0 2006.257.22:50:40.50#ibcon#about to write, iclass 13, count 0 2006.257.22:50:40.50#ibcon#wrote, iclass 13, count 0 2006.257.22:50:40.50#ibcon#about to read 3, iclass 13, count 0 2006.257.22:50:40.51#ibcon#read 3, iclass 13, count 0 2006.257.22:50:40.52#ibcon#about to read 4, iclass 13, count 0 2006.257.22:50:40.52#ibcon#read 4, iclass 13, count 0 2006.257.22:50:40.52#ibcon#about to read 5, iclass 13, count 0 2006.257.22:50:40.52#ibcon#read 5, iclass 13, count 0 2006.257.22:50:40.52#ibcon#about to read 6, iclass 13, count 0 2006.257.22:50:40.52#ibcon#read 6, iclass 13, count 0 2006.257.22:50:40.52#ibcon#end of sib2, iclass 13, count 0 2006.257.22:50:40.52#ibcon#*mode == 0, iclass 13, count 0 2006.257.22:50:40.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.22:50:40.52#ibcon#[27=USB\r\n] 2006.257.22:50:40.52#ibcon#*before write, iclass 13, count 0 2006.257.22:50:40.52#ibcon#enter sib2, iclass 13, count 0 2006.257.22:50:40.52#ibcon#flushed, iclass 13, count 0 2006.257.22:50:40.52#ibcon#about to write, iclass 13, count 0 2006.257.22:50:40.52#ibcon#wrote, iclass 13, count 0 2006.257.22:50:40.52#ibcon#about to read 3, iclass 13, count 0 2006.257.22:50:40.54#ibcon#read 3, iclass 13, count 0 2006.257.22:50:40.55#ibcon#about to read 4, iclass 13, count 0 2006.257.22:50:40.55#ibcon#read 4, iclass 13, count 0 2006.257.22:50:40.55#ibcon#about to read 5, iclass 13, count 0 2006.257.22:50:40.55#ibcon#read 5, iclass 13, count 0 2006.257.22:50:40.55#ibcon#about to read 6, iclass 13, count 0 2006.257.22:50:40.55#ibcon#read 6, iclass 13, count 0 2006.257.22:50:40.55#ibcon#end of sib2, iclass 13, count 0 2006.257.22:50:40.55#ibcon#*after write, iclass 13, count 0 2006.257.22:50:40.55#ibcon#*before return 0, iclass 13, count 0 2006.257.22:50:40.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:40.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.22:50:40.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.22:50:40.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.22:50:40.55$vck44/vblo=8,744.99 2006.257.22:50:40.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.22:50:40.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.22:50:40.55#ibcon#ireg 17 cls_cnt 0 2006.257.22:50:40.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:40.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:40.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:40.55#ibcon#enter wrdev, iclass 15, count 0 2006.257.22:50:40.55#ibcon#first serial, iclass 15, count 0 2006.257.22:50:40.55#ibcon#enter sib2, iclass 15, count 0 2006.257.22:50:40.55#ibcon#flushed, iclass 15, count 0 2006.257.22:50:40.55#ibcon#about to write, iclass 15, count 0 2006.257.22:50:40.55#ibcon#wrote, iclass 15, count 0 2006.257.22:50:40.55#ibcon#about to read 3, iclass 15, count 0 2006.257.22:50:40.56#ibcon#read 3, iclass 15, count 0 2006.257.22:50:40.57#ibcon#about to read 4, iclass 15, count 0 2006.257.22:50:40.57#ibcon#read 4, iclass 15, count 0 2006.257.22:50:40.57#ibcon#about to read 5, iclass 15, count 0 2006.257.22:50:40.57#ibcon#read 5, iclass 15, count 0 2006.257.22:50:40.57#ibcon#about to read 6, iclass 15, count 0 2006.257.22:50:40.57#ibcon#read 6, iclass 15, count 0 2006.257.22:50:40.57#ibcon#end of sib2, iclass 15, count 0 2006.257.22:50:40.57#ibcon#*mode == 0, iclass 15, count 0 2006.257.22:50:40.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.22:50:40.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.22:50:40.57#ibcon#*before write, iclass 15, count 0 2006.257.22:50:40.57#ibcon#enter sib2, iclass 15, count 0 2006.257.22:50:40.57#ibcon#flushed, iclass 15, count 0 2006.257.22:50:40.57#ibcon#about to write, iclass 15, count 0 2006.257.22:50:40.57#ibcon#wrote, iclass 15, count 0 2006.257.22:50:40.57#ibcon#about to read 3, iclass 15, count 0 2006.257.22:50:40.60#ibcon#read 3, iclass 15, count 0 2006.257.22:50:40.61#ibcon#about to read 4, iclass 15, count 0 2006.257.22:50:40.61#ibcon#read 4, iclass 15, count 0 2006.257.22:50:40.61#ibcon#about to read 5, iclass 15, count 0 2006.257.22:50:40.61#ibcon#read 5, iclass 15, count 0 2006.257.22:50:40.61#ibcon#about to read 6, iclass 15, count 0 2006.257.22:50:40.61#ibcon#read 6, iclass 15, count 0 2006.257.22:50:40.61#ibcon#end of sib2, iclass 15, count 0 2006.257.22:50:40.61#ibcon#*after write, iclass 15, count 0 2006.257.22:50:40.61#ibcon#*before return 0, iclass 15, count 0 2006.257.22:50:40.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:40.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.22:50:40.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.22:50:40.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.22:50:40.61$vck44/vb=8,4 2006.257.22:50:40.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.22:50:40.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.22:50:40.61#ibcon#ireg 11 cls_cnt 2 2006.257.22:50:40.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:40.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:40.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:40.67#ibcon#enter wrdev, iclass 17, count 2 2006.257.22:50:40.67#ibcon#first serial, iclass 17, count 2 2006.257.22:50:40.67#ibcon#enter sib2, iclass 17, count 2 2006.257.22:50:40.67#ibcon#flushed, iclass 17, count 2 2006.257.22:50:40.67#ibcon#about to write, iclass 17, count 2 2006.257.22:50:40.67#ibcon#wrote, iclass 17, count 2 2006.257.22:50:40.67#ibcon#about to read 3, iclass 17, count 2 2006.257.22:50:40.68#ibcon#read 3, iclass 17, count 2 2006.257.22:50:40.69#ibcon#about to read 4, iclass 17, count 2 2006.257.22:50:40.69#ibcon#read 4, iclass 17, count 2 2006.257.22:50:40.69#ibcon#about to read 5, iclass 17, count 2 2006.257.22:50:40.69#ibcon#read 5, iclass 17, count 2 2006.257.22:50:40.69#ibcon#about to read 6, iclass 17, count 2 2006.257.22:50:40.69#ibcon#read 6, iclass 17, count 2 2006.257.22:50:40.69#ibcon#end of sib2, iclass 17, count 2 2006.257.22:50:40.69#ibcon#*mode == 0, iclass 17, count 2 2006.257.22:50:40.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.22:50:40.69#ibcon#[27=AT08-04\r\n] 2006.257.22:50:40.69#ibcon#*before write, iclass 17, count 2 2006.257.22:50:40.69#ibcon#enter sib2, iclass 17, count 2 2006.257.22:50:40.69#ibcon#flushed, iclass 17, count 2 2006.257.22:50:40.69#ibcon#about to write, iclass 17, count 2 2006.257.22:50:40.69#ibcon#wrote, iclass 17, count 2 2006.257.22:50:40.69#ibcon#about to read 3, iclass 17, count 2 2006.257.22:50:40.71#ibcon#read 3, iclass 17, count 2 2006.257.22:50:40.72#ibcon#about to read 4, iclass 17, count 2 2006.257.22:50:40.72#ibcon#read 4, iclass 17, count 2 2006.257.22:50:40.72#ibcon#about to read 5, iclass 17, count 2 2006.257.22:50:40.72#ibcon#read 5, iclass 17, count 2 2006.257.22:50:40.72#ibcon#about to read 6, iclass 17, count 2 2006.257.22:50:40.72#ibcon#read 6, iclass 17, count 2 2006.257.22:50:40.72#ibcon#end of sib2, iclass 17, count 2 2006.257.22:50:40.72#ibcon#*after write, iclass 17, count 2 2006.257.22:50:40.72#ibcon#*before return 0, iclass 17, count 2 2006.257.22:50:40.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:40.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.22:50:40.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.22:50:40.72#ibcon#ireg 7 cls_cnt 0 2006.257.22:50:40.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:40.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:40.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:40.84#ibcon#enter wrdev, iclass 17, count 0 2006.257.22:50:40.84#ibcon#first serial, iclass 17, count 0 2006.257.22:50:40.84#ibcon#enter sib2, iclass 17, count 0 2006.257.22:50:40.84#ibcon#flushed, iclass 17, count 0 2006.257.22:50:40.84#ibcon#about to write, iclass 17, count 0 2006.257.22:50:40.84#ibcon#wrote, iclass 17, count 0 2006.257.22:50:40.84#ibcon#about to read 3, iclass 17, count 0 2006.257.22:50:40.85#ibcon#read 3, iclass 17, count 0 2006.257.22:50:40.86#ibcon#about to read 4, iclass 17, count 0 2006.257.22:50:40.86#ibcon#read 4, iclass 17, count 0 2006.257.22:50:40.86#ibcon#about to read 5, iclass 17, count 0 2006.257.22:50:40.86#ibcon#read 5, iclass 17, count 0 2006.257.22:50:40.86#ibcon#about to read 6, iclass 17, count 0 2006.257.22:50:40.86#ibcon#read 6, iclass 17, count 0 2006.257.22:50:40.86#ibcon#end of sib2, iclass 17, count 0 2006.257.22:50:40.86#ibcon#*mode == 0, iclass 17, count 0 2006.257.22:50:40.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.22:50:40.86#ibcon#[27=USB\r\n] 2006.257.22:50:40.86#ibcon#*before write, iclass 17, count 0 2006.257.22:50:40.86#ibcon#enter sib2, iclass 17, count 0 2006.257.22:50:40.86#ibcon#flushed, iclass 17, count 0 2006.257.22:50:40.86#ibcon#about to write, iclass 17, count 0 2006.257.22:50:40.86#ibcon#wrote, iclass 17, count 0 2006.257.22:50:40.86#ibcon#about to read 3, iclass 17, count 0 2006.257.22:50:40.88#ibcon#read 3, iclass 17, count 0 2006.257.22:50:40.89#ibcon#about to read 4, iclass 17, count 0 2006.257.22:50:40.89#ibcon#read 4, iclass 17, count 0 2006.257.22:50:40.89#ibcon#about to read 5, iclass 17, count 0 2006.257.22:50:40.89#ibcon#read 5, iclass 17, count 0 2006.257.22:50:40.89#ibcon#about to read 6, iclass 17, count 0 2006.257.22:50:40.89#ibcon#read 6, iclass 17, count 0 2006.257.22:50:40.89#ibcon#end of sib2, iclass 17, count 0 2006.257.22:50:40.89#ibcon#*after write, iclass 17, count 0 2006.257.22:50:40.89#ibcon#*before return 0, iclass 17, count 0 2006.257.22:50:40.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:40.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.22:50:40.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.22:50:40.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.22:50:40.89$vck44/vabw=wide 2006.257.22:50:40.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.22:50:40.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.22:50:40.89#ibcon#ireg 8 cls_cnt 0 2006.257.22:50:40.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:40.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:40.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:40.89#ibcon#enter wrdev, iclass 19, count 0 2006.257.22:50:40.89#ibcon#first serial, iclass 19, count 0 2006.257.22:50:40.89#ibcon#enter sib2, iclass 19, count 0 2006.257.22:50:40.89#ibcon#flushed, iclass 19, count 0 2006.257.22:50:40.89#ibcon#about to write, iclass 19, count 0 2006.257.22:50:40.89#ibcon#wrote, iclass 19, count 0 2006.257.22:50:40.89#ibcon#about to read 3, iclass 19, count 0 2006.257.22:50:40.90#ibcon#read 3, iclass 19, count 0 2006.257.22:50:40.91#ibcon#about to read 4, iclass 19, count 0 2006.257.22:50:40.91#ibcon#read 4, iclass 19, count 0 2006.257.22:50:40.91#ibcon#about to read 5, iclass 19, count 0 2006.257.22:50:40.91#ibcon#read 5, iclass 19, count 0 2006.257.22:50:40.91#ibcon#about to read 6, iclass 19, count 0 2006.257.22:50:40.91#ibcon#read 6, iclass 19, count 0 2006.257.22:50:40.91#ibcon#end of sib2, iclass 19, count 0 2006.257.22:50:40.91#ibcon#*mode == 0, iclass 19, count 0 2006.257.22:50:40.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.22:50:40.91#ibcon#[25=BW32\r\n] 2006.257.22:50:40.91#ibcon#*before write, iclass 19, count 0 2006.257.22:50:40.91#ibcon#enter sib2, iclass 19, count 0 2006.257.22:50:40.91#ibcon#flushed, iclass 19, count 0 2006.257.22:50:40.91#ibcon#about to write, iclass 19, count 0 2006.257.22:50:40.91#ibcon#wrote, iclass 19, count 0 2006.257.22:50:40.91#ibcon#about to read 3, iclass 19, count 0 2006.257.22:50:40.93#ibcon#read 3, iclass 19, count 0 2006.257.22:50:40.94#ibcon#about to read 4, iclass 19, count 0 2006.257.22:50:40.94#ibcon#read 4, iclass 19, count 0 2006.257.22:50:40.94#ibcon#about to read 5, iclass 19, count 0 2006.257.22:50:40.94#ibcon#read 5, iclass 19, count 0 2006.257.22:50:40.94#ibcon#about to read 6, iclass 19, count 0 2006.257.22:50:40.94#ibcon#read 6, iclass 19, count 0 2006.257.22:50:40.94#ibcon#end of sib2, iclass 19, count 0 2006.257.22:50:40.94#ibcon#*after write, iclass 19, count 0 2006.257.22:50:40.94#ibcon#*before return 0, iclass 19, count 0 2006.257.22:50:40.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:40.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.22:50:40.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.22:50:40.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.22:50:40.94$vck44/vbbw=wide 2006.257.22:50:40.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.22:50:40.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.22:50:40.94#ibcon#ireg 8 cls_cnt 0 2006.257.22:50:40.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:50:41.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:50:41.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:50:41.01#ibcon#enter wrdev, iclass 21, count 0 2006.257.22:50:41.01#ibcon#first serial, iclass 21, count 0 2006.257.22:50:41.01#ibcon#enter sib2, iclass 21, count 0 2006.257.22:50:41.01#ibcon#flushed, iclass 21, count 0 2006.257.22:50:41.01#ibcon#about to write, iclass 21, count 0 2006.257.22:50:41.01#ibcon#wrote, iclass 21, count 0 2006.257.22:50:41.01#ibcon#about to read 3, iclass 21, count 0 2006.257.22:50:41.02#ibcon#read 3, iclass 21, count 0 2006.257.22:50:41.03#ibcon#about to read 4, iclass 21, count 0 2006.257.22:50:41.03#ibcon#read 4, iclass 21, count 0 2006.257.22:50:41.03#ibcon#about to read 5, iclass 21, count 0 2006.257.22:50:41.03#ibcon#read 5, iclass 21, count 0 2006.257.22:50:41.03#ibcon#about to read 6, iclass 21, count 0 2006.257.22:50:41.03#ibcon#read 6, iclass 21, count 0 2006.257.22:50:41.03#ibcon#end of sib2, iclass 21, count 0 2006.257.22:50:41.03#ibcon#*mode == 0, iclass 21, count 0 2006.257.22:50:41.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.22:50:41.03#ibcon#[27=BW32\r\n] 2006.257.22:50:41.03#ibcon#*before write, iclass 21, count 0 2006.257.22:50:41.03#ibcon#enter sib2, iclass 21, count 0 2006.257.22:50:41.03#ibcon#flushed, iclass 21, count 0 2006.257.22:50:41.03#ibcon#about to write, iclass 21, count 0 2006.257.22:50:41.03#ibcon#wrote, iclass 21, count 0 2006.257.22:50:41.03#ibcon#about to read 3, iclass 21, count 0 2006.257.22:50:41.05#ibcon#read 3, iclass 21, count 0 2006.257.22:50:41.06#ibcon#about to read 4, iclass 21, count 0 2006.257.22:50:41.06#ibcon#read 4, iclass 21, count 0 2006.257.22:50:41.06#ibcon#about to read 5, iclass 21, count 0 2006.257.22:50:41.06#ibcon#read 5, iclass 21, count 0 2006.257.22:50:41.06#ibcon#about to read 6, iclass 21, count 0 2006.257.22:50:41.06#ibcon#read 6, iclass 21, count 0 2006.257.22:50:41.06#ibcon#end of sib2, iclass 21, count 0 2006.257.22:50:41.06#ibcon#*after write, iclass 21, count 0 2006.257.22:50:41.06#ibcon#*before return 0, iclass 21, count 0 2006.257.22:50:41.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:50:41.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.22:50:41.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.22:50:41.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.22:50:41.06$setupk4/ifdk4 2006.257.22:50:41.06$ifdk4/lo= 2006.257.22:50:41.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.22:50:41.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.22:50:41.06$ifdk4/patch= 2006.257.22:50:41.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.22:50:41.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.22:50:41.06$setupk4/!*+20s 2006.257.22:50:48.75#abcon#<5=/14 1.2 3.3 19.79 851016.0\r\n> 2006.257.22:50:48.77#abcon#{5=INTERFACE CLEAR} 2006.257.22:50:48.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.22:50:55.59$setupk4/"tpicd 2006.257.22:50:55.59$setupk4/echo=off 2006.257.22:50:55.59$setupk4/xlog=off 2006.257.22:50:55.59:!2006.257.22:57:10 2006.257.22:51:00.13#trakl#Source acquired 2006.257.22:51:02.14#flagr#flagr/antenna,acquired 2006.257.22:57:10.00:preob 2006.257.22:57:10.14/onsource/TRACKING 2006.257.22:57:10.14:!2006.257.22:57:20 2006.257.22:57:20.00:"tape 2006.257.22:57:20.00:"st=record 2006.257.22:57:20.00:data_valid=on 2006.257.22:57:20.00:midob 2006.257.22:57:20.14/onsource/TRACKING 2006.257.22:57:20.14/wx/19.92,1016.0,84 2006.257.22:57:20.22/cable/+6.4845E-03 2006.257.22:57:21.31/va/01,08,usb,yes,31,33 2006.257.22:57:21.31/va/02,07,usb,yes,33,34 2006.257.22:57:21.31/va/03,08,usb,yes,30,31 2006.257.22:57:21.31/va/04,07,usb,yes,34,36 2006.257.22:57:21.31/va/05,04,usb,yes,30,31 2006.257.22:57:21.31/va/06,04,usb,yes,34,34 2006.257.22:57:21.31/va/07,04,usb,yes,35,35 2006.257.22:57:21.31/va/08,04,usb,yes,29,36 2006.257.22:57:21.54/valo/01,524.99,yes,locked 2006.257.22:57:21.54/valo/02,534.99,yes,locked 2006.257.22:57:21.54/valo/03,564.99,yes,locked 2006.257.22:57:21.54/valo/04,624.99,yes,locked 2006.257.22:57:21.54/valo/05,734.99,yes,locked 2006.257.22:57:21.54/valo/06,814.99,yes,locked 2006.257.22:57:21.54/valo/07,864.99,yes,locked 2006.257.22:57:21.54/valo/08,884.99,yes,locked 2006.257.22:57:22.63/vb/01,04,usb,yes,31,30 2006.257.22:57:22.63/vb/02,05,usb,yes,29,30 2006.257.22:57:22.63/vb/03,04,usb,yes,30,33 2006.257.22:57:22.63/vb/04,05,usb,yes,30,29 2006.257.22:57:22.63/vb/05,04,usb,yes,27,29 2006.257.22:57:22.63/vb/06,04,usb,yes,31,27 2006.257.22:57:22.63/vb/07,04,usb,yes,31,31 2006.257.22:57:22.63/vb/08,04,usb,yes,28,32 2006.257.22:57:22.86/vblo/01,629.99,yes,locked 2006.257.22:57:22.86/vblo/02,634.99,yes,locked 2006.257.22:57:22.86/vblo/03,649.99,yes,locked 2006.257.22:57:22.86/vblo/04,679.99,yes,locked 2006.257.22:57:22.86/vblo/05,709.99,yes,locked 2006.257.22:57:22.86/vblo/06,719.99,yes,locked 2006.257.22:57:22.86/vblo/07,734.99,yes,locked 2006.257.22:57:22.86/vblo/08,744.99,yes,locked 2006.257.22:57:23.01/vabw/8 2006.257.22:57:23.16/vbbw/8 2006.257.22:57:23.25/xfe/off,on,15.2 2006.257.22:57:23.63/ifatt/23,28,28,28 2006.257.22:57:24.07/fmout-gps/S +4.58E-07 2006.257.22:57:24.11:!2006.257.23:02:40 2006.257.23:02:40.00:data_valid=off 2006.257.23:02:40.01:"et 2006.257.23:02:40.01:!+3s 2006.257.23:02:43.02:"tape 2006.257.23:02:43.03:postob 2006.257.23:02:43.12/cable/+6.4841E-03 2006.257.23:02:43.13/wx/20.01,1016.0,83 2006.257.23:02:43.18/fmout-gps/S +4.58E-07 2006.257.23:02:43.19:scan_name=257-2307,jd0609,100 2006.257.23:02:43.19:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.257.23:02:44.14#flagr#flagr/antenna,new-source 2006.257.23:02:44.15:checkk5 2006.257.23:02:44.50/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:02:44.85/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:02:45.20/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:02:45.56/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:02:45.90/chk_obsdata//k5ts1/T2572257??a.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.257.23:02:46.24/chk_obsdata//k5ts2/T2572257??b.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.257.23:02:46.58/chk_obsdata//k5ts3/T2572257??c.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.257.23:02:46.91/chk_obsdata//k5ts4/T2572257??d.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.257.23:02:47.56/k5log//k5ts1_log_newline 2006.257.23:02:48.21/k5log//k5ts2_log_newline 2006.257.23:02:48.86/k5log//k5ts3_log_newline 2006.257.23:02:49.53/k5log//k5ts4_log_newline 2006.257.23:02:49.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:02:49.55:setupk4=1 2006.257.23:02:49.55$setupk4/echo=on 2006.257.23:02:49.55$setupk4/pcalon 2006.257.23:02:49.55$pcalon/"no phase cal control is implemented here 2006.257.23:02:49.55$setupk4/"tpicd=stop 2006.257.23:02:49.55$setupk4/"rec=synch_on 2006.257.23:02:49.55$setupk4/"rec_mode=128 2006.257.23:02:49.55$setupk4/!* 2006.257.23:02:49.55$setupk4/recpk4 2006.257.23:02:49.55$recpk4/recpatch= 2006.257.23:02:49.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:02:49.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:02:49.55$setupk4/vck44 2006.257.23:02:49.55$vck44/valo=1,524.99 2006.257.23:02:49.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.23:02:49.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.23:02:49.56#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:49.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:49.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:49.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:49.56#ibcon#enter wrdev, iclass 17, count 0 2006.257.23:02:49.56#ibcon#first serial, iclass 17, count 0 2006.257.23:02:49.56#ibcon#enter sib2, iclass 17, count 0 2006.257.23:02:49.56#ibcon#flushed, iclass 17, count 0 2006.257.23:02:49.56#ibcon#about to write, iclass 17, count 0 2006.257.23:02:49.56#ibcon#wrote, iclass 17, count 0 2006.257.23:02:49.56#ibcon#about to read 3, iclass 17, count 0 2006.257.23:02:49.57#ibcon#read 3, iclass 17, count 0 2006.257.23:02:49.57#ibcon#about to read 4, iclass 17, count 0 2006.257.23:02:49.57#ibcon#read 4, iclass 17, count 0 2006.257.23:02:49.57#ibcon#about to read 5, iclass 17, count 0 2006.257.23:02:49.57#ibcon#read 5, iclass 17, count 0 2006.257.23:02:49.57#ibcon#about to read 6, iclass 17, count 0 2006.257.23:02:49.57#ibcon#read 6, iclass 17, count 0 2006.257.23:02:49.57#ibcon#end of sib2, iclass 17, count 0 2006.257.23:02:49.57#ibcon#*mode == 0, iclass 17, count 0 2006.257.23:02:49.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.23:02:49.57#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:02:49.57#ibcon#*before write, iclass 17, count 0 2006.257.23:02:49.57#ibcon#enter sib2, iclass 17, count 0 2006.257.23:02:49.57#ibcon#flushed, iclass 17, count 0 2006.257.23:02:49.57#ibcon#about to write, iclass 17, count 0 2006.257.23:02:49.57#ibcon#wrote, iclass 17, count 0 2006.257.23:02:49.57#ibcon#about to read 3, iclass 17, count 0 2006.257.23:02:49.62#ibcon#read 3, iclass 17, count 0 2006.257.23:02:49.62#ibcon#about to read 4, iclass 17, count 0 2006.257.23:02:49.62#ibcon#read 4, iclass 17, count 0 2006.257.23:02:49.62#ibcon#about to read 5, iclass 17, count 0 2006.257.23:02:49.62#ibcon#read 5, iclass 17, count 0 2006.257.23:02:49.62#ibcon#about to read 6, iclass 17, count 0 2006.257.23:02:49.62#ibcon#read 6, iclass 17, count 0 2006.257.23:02:49.62#ibcon#end of sib2, iclass 17, count 0 2006.257.23:02:49.62#ibcon#*after write, iclass 17, count 0 2006.257.23:02:49.62#ibcon#*before return 0, iclass 17, count 0 2006.257.23:02:49.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:49.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:49.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.23:02:49.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.23:02:49.62$vck44/va=1,8 2006.257.23:02:49.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.23:02:49.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.23:02:49.62#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:49.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:49.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:49.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:49.62#ibcon#enter wrdev, iclass 19, count 2 2006.257.23:02:49.62#ibcon#first serial, iclass 19, count 2 2006.257.23:02:49.62#ibcon#enter sib2, iclass 19, count 2 2006.257.23:02:49.62#ibcon#flushed, iclass 19, count 2 2006.257.23:02:49.62#ibcon#about to write, iclass 19, count 2 2006.257.23:02:49.62#ibcon#wrote, iclass 19, count 2 2006.257.23:02:49.62#ibcon#about to read 3, iclass 19, count 2 2006.257.23:02:49.64#ibcon#read 3, iclass 19, count 2 2006.257.23:02:49.64#ibcon#about to read 4, iclass 19, count 2 2006.257.23:02:49.64#ibcon#read 4, iclass 19, count 2 2006.257.23:02:49.64#ibcon#about to read 5, iclass 19, count 2 2006.257.23:02:49.64#ibcon#read 5, iclass 19, count 2 2006.257.23:02:49.64#ibcon#about to read 6, iclass 19, count 2 2006.257.23:02:49.64#ibcon#read 6, iclass 19, count 2 2006.257.23:02:49.64#ibcon#end of sib2, iclass 19, count 2 2006.257.23:02:49.64#ibcon#*mode == 0, iclass 19, count 2 2006.257.23:02:49.64#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.23:02:49.64#ibcon#[25=AT01-08\r\n] 2006.257.23:02:49.64#ibcon#*before write, iclass 19, count 2 2006.257.23:02:49.64#ibcon#enter sib2, iclass 19, count 2 2006.257.23:02:49.64#ibcon#flushed, iclass 19, count 2 2006.257.23:02:49.64#ibcon#about to write, iclass 19, count 2 2006.257.23:02:49.64#ibcon#wrote, iclass 19, count 2 2006.257.23:02:49.64#ibcon#about to read 3, iclass 19, count 2 2006.257.23:02:49.67#ibcon#read 3, iclass 19, count 2 2006.257.23:02:49.67#ibcon#about to read 4, iclass 19, count 2 2006.257.23:02:49.67#ibcon#read 4, iclass 19, count 2 2006.257.23:02:49.67#ibcon#about to read 5, iclass 19, count 2 2006.257.23:02:49.67#ibcon#read 5, iclass 19, count 2 2006.257.23:02:49.67#ibcon#about to read 6, iclass 19, count 2 2006.257.23:02:49.67#ibcon#read 6, iclass 19, count 2 2006.257.23:02:49.67#ibcon#end of sib2, iclass 19, count 2 2006.257.23:02:49.67#ibcon#*after write, iclass 19, count 2 2006.257.23:02:49.67#ibcon#*before return 0, iclass 19, count 2 2006.257.23:02:49.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:49.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:49.67#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.23:02:49.67#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:49.67#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:49.79#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:49.79#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:49.79#ibcon#enter wrdev, iclass 19, count 0 2006.257.23:02:49.79#ibcon#first serial, iclass 19, count 0 2006.257.23:02:49.79#ibcon#enter sib2, iclass 19, count 0 2006.257.23:02:49.79#ibcon#flushed, iclass 19, count 0 2006.257.23:02:49.79#ibcon#about to write, iclass 19, count 0 2006.257.23:02:49.79#ibcon#wrote, iclass 19, count 0 2006.257.23:02:49.79#ibcon#about to read 3, iclass 19, count 0 2006.257.23:02:49.81#ibcon#read 3, iclass 19, count 0 2006.257.23:02:49.81#ibcon#about to read 4, iclass 19, count 0 2006.257.23:02:49.81#ibcon#read 4, iclass 19, count 0 2006.257.23:02:49.81#ibcon#about to read 5, iclass 19, count 0 2006.257.23:02:49.81#ibcon#read 5, iclass 19, count 0 2006.257.23:02:49.81#ibcon#about to read 6, iclass 19, count 0 2006.257.23:02:49.81#ibcon#read 6, iclass 19, count 0 2006.257.23:02:49.81#ibcon#end of sib2, iclass 19, count 0 2006.257.23:02:49.81#ibcon#*mode == 0, iclass 19, count 0 2006.257.23:02:49.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.23:02:49.81#ibcon#[25=USB\r\n] 2006.257.23:02:49.81#ibcon#*before write, iclass 19, count 0 2006.257.23:02:49.81#ibcon#enter sib2, iclass 19, count 0 2006.257.23:02:49.81#ibcon#flushed, iclass 19, count 0 2006.257.23:02:49.81#ibcon#about to write, iclass 19, count 0 2006.257.23:02:49.81#ibcon#wrote, iclass 19, count 0 2006.257.23:02:49.81#ibcon#about to read 3, iclass 19, count 0 2006.257.23:02:49.84#ibcon#read 3, iclass 19, count 0 2006.257.23:02:49.84#ibcon#about to read 4, iclass 19, count 0 2006.257.23:02:49.84#ibcon#read 4, iclass 19, count 0 2006.257.23:02:49.84#ibcon#about to read 5, iclass 19, count 0 2006.257.23:02:49.84#ibcon#read 5, iclass 19, count 0 2006.257.23:02:49.84#ibcon#about to read 6, iclass 19, count 0 2006.257.23:02:49.84#ibcon#read 6, iclass 19, count 0 2006.257.23:02:49.84#ibcon#end of sib2, iclass 19, count 0 2006.257.23:02:49.84#ibcon#*after write, iclass 19, count 0 2006.257.23:02:49.84#ibcon#*before return 0, iclass 19, count 0 2006.257.23:02:49.84#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:49.84#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:49.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.23:02:49.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.23:02:49.84$vck44/valo=2,534.99 2006.257.23:02:49.84#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.23:02:49.84#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.23:02:49.84#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:49.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:49.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:49.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:49.84#ibcon#enter wrdev, iclass 21, count 0 2006.257.23:02:49.84#ibcon#first serial, iclass 21, count 0 2006.257.23:02:49.84#ibcon#enter sib2, iclass 21, count 0 2006.257.23:02:49.84#ibcon#flushed, iclass 21, count 0 2006.257.23:02:49.84#ibcon#about to write, iclass 21, count 0 2006.257.23:02:49.84#ibcon#wrote, iclass 21, count 0 2006.257.23:02:49.84#ibcon#about to read 3, iclass 21, count 0 2006.257.23:02:49.86#ibcon#read 3, iclass 21, count 0 2006.257.23:02:49.86#ibcon#about to read 4, iclass 21, count 0 2006.257.23:02:49.86#ibcon#read 4, iclass 21, count 0 2006.257.23:02:49.86#ibcon#about to read 5, iclass 21, count 0 2006.257.23:02:49.86#ibcon#read 5, iclass 21, count 0 2006.257.23:02:49.86#ibcon#about to read 6, iclass 21, count 0 2006.257.23:02:49.86#ibcon#read 6, iclass 21, count 0 2006.257.23:02:49.86#ibcon#end of sib2, iclass 21, count 0 2006.257.23:02:49.86#ibcon#*mode == 0, iclass 21, count 0 2006.257.23:02:49.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.23:02:49.86#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:02:49.86#ibcon#*before write, iclass 21, count 0 2006.257.23:02:49.86#ibcon#enter sib2, iclass 21, count 0 2006.257.23:02:49.86#ibcon#flushed, iclass 21, count 0 2006.257.23:02:49.86#ibcon#about to write, iclass 21, count 0 2006.257.23:02:49.86#ibcon#wrote, iclass 21, count 0 2006.257.23:02:49.86#ibcon#about to read 3, iclass 21, count 0 2006.257.23:02:49.90#ibcon#read 3, iclass 21, count 0 2006.257.23:02:49.90#ibcon#about to read 4, iclass 21, count 0 2006.257.23:02:49.90#ibcon#read 4, iclass 21, count 0 2006.257.23:02:49.90#ibcon#about to read 5, iclass 21, count 0 2006.257.23:02:49.90#ibcon#read 5, iclass 21, count 0 2006.257.23:02:49.90#ibcon#about to read 6, iclass 21, count 0 2006.257.23:02:49.90#ibcon#read 6, iclass 21, count 0 2006.257.23:02:49.90#ibcon#end of sib2, iclass 21, count 0 2006.257.23:02:49.90#ibcon#*after write, iclass 21, count 0 2006.257.23:02:49.90#ibcon#*before return 0, iclass 21, count 0 2006.257.23:02:49.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:49.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:49.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.23:02:49.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.23:02:49.90$vck44/va=2,7 2006.257.23:02:49.90#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.23:02:49.90#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.23:02:49.90#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:49.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:49.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:49.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:49.96#ibcon#enter wrdev, iclass 23, count 2 2006.257.23:02:49.96#ibcon#first serial, iclass 23, count 2 2006.257.23:02:49.96#ibcon#enter sib2, iclass 23, count 2 2006.257.23:02:49.96#ibcon#flushed, iclass 23, count 2 2006.257.23:02:49.96#ibcon#about to write, iclass 23, count 2 2006.257.23:02:49.96#ibcon#wrote, iclass 23, count 2 2006.257.23:02:49.96#ibcon#about to read 3, iclass 23, count 2 2006.257.23:02:49.98#ibcon#read 3, iclass 23, count 2 2006.257.23:02:49.98#ibcon#about to read 4, iclass 23, count 2 2006.257.23:02:49.98#ibcon#read 4, iclass 23, count 2 2006.257.23:02:49.98#ibcon#about to read 5, iclass 23, count 2 2006.257.23:02:49.98#ibcon#read 5, iclass 23, count 2 2006.257.23:02:49.98#ibcon#about to read 6, iclass 23, count 2 2006.257.23:02:49.98#ibcon#read 6, iclass 23, count 2 2006.257.23:02:49.98#ibcon#end of sib2, iclass 23, count 2 2006.257.23:02:49.98#ibcon#*mode == 0, iclass 23, count 2 2006.257.23:02:49.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.23:02:49.98#ibcon#[25=AT02-07\r\n] 2006.257.23:02:49.98#ibcon#*before write, iclass 23, count 2 2006.257.23:02:49.98#ibcon#enter sib2, iclass 23, count 2 2006.257.23:02:49.98#ibcon#flushed, iclass 23, count 2 2006.257.23:02:49.98#ibcon#about to write, iclass 23, count 2 2006.257.23:02:49.98#ibcon#wrote, iclass 23, count 2 2006.257.23:02:49.98#ibcon#about to read 3, iclass 23, count 2 2006.257.23:02:50.01#ibcon#read 3, iclass 23, count 2 2006.257.23:02:50.01#ibcon#about to read 4, iclass 23, count 2 2006.257.23:02:50.01#ibcon#read 4, iclass 23, count 2 2006.257.23:02:50.01#ibcon#about to read 5, iclass 23, count 2 2006.257.23:02:50.01#ibcon#read 5, iclass 23, count 2 2006.257.23:02:50.01#ibcon#about to read 6, iclass 23, count 2 2006.257.23:02:50.01#ibcon#read 6, iclass 23, count 2 2006.257.23:02:50.01#ibcon#end of sib2, iclass 23, count 2 2006.257.23:02:50.01#ibcon#*after write, iclass 23, count 2 2006.257.23:02:50.01#ibcon#*before return 0, iclass 23, count 2 2006.257.23:02:50.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:50.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:50.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.23:02:50.01#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:50.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:50.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:50.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:50.13#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:02:50.13#ibcon#first serial, iclass 23, count 0 2006.257.23:02:50.13#ibcon#enter sib2, iclass 23, count 0 2006.257.23:02:50.13#ibcon#flushed, iclass 23, count 0 2006.257.23:02:50.13#ibcon#about to write, iclass 23, count 0 2006.257.23:02:50.13#ibcon#wrote, iclass 23, count 0 2006.257.23:02:50.13#ibcon#about to read 3, iclass 23, count 0 2006.257.23:02:50.15#ibcon#read 3, iclass 23, count 0 2006.257.23:02:50.15#ibcon#about to read 4, iclass 23, count 0 2006.257.23:02:50.15#ibcon#read 4, iclass 23, count 0 2006.257.23:02:50.15#ibcon#about to read 5, iclass 23, count 0 2006.257.23:02:50.15#ibcon#read 5, iclass 23, count 0 2006.257.23:02:50.15#ibcon#about to read 6, iclass 23, count 0 2006.257.23:02:50.15#ibcon#read 6, iclass 23, count 0 2006.257.23:02:50.15#ibcon#end of sib2, iclass 23, count 0 2006.257.23:02:50.15#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:02:50.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:02:50.15#ibcon#[25=USB\r\n] 2006.257.23:02:50.15#ibcon#*before write, iclass 23, count 0 2006.257.23:02:50.15#ibcon#enter sib2, iclass 23, count 0 2006.257.23:02:50.15#ibcon#flushed, iclass 23, count 0 2006.257.23:02:50.15#ibcon#about to write, iclass 23, count 0 2006.257.23:02:50.15#ibcon#wrote, iclass 23, count 0 2006.257.23:02:50.15#ibcon#about to read 3, iclass 23, count 0 2006.257.23:02:50.18#ibcon#read 3, iclass 23, count 0 2006.257.23:02:50.18#ibcon#about to read 4, iclass 23, count 0 2006.257.23:02:50.18#ibcon#read 4, iclass 23, count 0 2006.257.23:02:50.18#ibcon#about to read 5, iclass 23, count 0 2006.257.23:02:50.18#ibcon#read 5, iclass 23, count 0 2006.257.23:02:50.18#ibcon#about to read 6, iclass 23, count 0 2006.257.23:02:50.18#ibcon#read 6, iclass 23, count 0 2006.257.23:02:50.18#ibcon#end of sib2, iclass 23, count 0 2006.257.23:02:50.18#ibcon#*after write, iclass 23, count 0 2006.257.23:02:50.18#ibcon#*before return 0, iclass 23, count 0 2006.257.23:02:50.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:50.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:50.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:02:50.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:02:50.18$vck44/valo=3,564.99 2006.257.23:02:50.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.23:02:50.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.23:02:50.18#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:50.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:50.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:50.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:50.18#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:02:50.18#ibcon#first serial, iclass 25, count 0 2006.257.23:02:50.18#ibcon#enter sib2, iclass 25, count 0 2006.257.23:02:50.18#ibcon#flushed, iclass 25, count 0 2006.257.23:02:50.18#ibcon#about to write, iclass 25, count 0 2006.257.23:02:50.18#ibcon#wrote, iclass 25, count 0 2006.257.23:02:50.18#ibcon#about to read 3, iclass 25, count 0 2006.257.23:02:50.20#ibcon#read 3, iclass 25, count 0 2006.257.23:02:50.20#ibcon#about to read 4, iclass 25, count 0 2006.257.23:02:50.20#ibcon#read 4, iclass 25, count 0 2006.257.23:02:50.20#ibcon#about to read 5, iclass 25, count 0 2006.257.23:02:50.20#ibcon#read 5, iclass 25, count 0 2006.257.23:02:50.20#ibcon#about to read 6, iclass 25, count 0 2006.257.23:02:50.20#ibcon#read 6, iclass 25, count 0 2006.257.23:02:50.20#ibcon#end of sib2, iclass 25, count 0 2006.257.23:02:50.20#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:02:50.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:02:50.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:02:50.20#ibcon#*before write, iclass 25, count 0 2006.257.23:02:50.20#ibcon#enter sib2, iclass 25, count 0 2006.257.23:02:50.20#ibcon#flushed, iclass 25, count 0 2006.257.23:02:50.20#ibcon#about to write, iclass 25, count 0 2006.257.23:02:50.20#ibcon#wrote, iclass 25, count 0 2006.257.23:02:50.20#ibcon#about to read 3, iclass 25, count 0 2006.257.23:02:50.24#ibcon#read 3, iclass 25, count 0 2006.257.23:02:50.24#ibcon#about to read 4, iclass 25, count 0 2006.257.23:02:50.24#ibcon#read 4, iclass 25, count 0 2006.257.23:02:50.24#ibcon#about to read 5, iclass 25, count 0 2006.257.23:02:50.24#ibcon#read 5, iclass 25, count 0 2006.257.23:02:50.24#ibcon#about to read 6, iclass 25, count 0 2006.257.23:02:50.24#ibcon#read 6, iclass 25, count 0 2006.257.23:02:50.24#ibcon#end of sib2, iclass 25, count 0 2006.257.23:02:50.24#ibcon#*after write, iclass 25, count 0 2006.257.23:02:50.24#ibcon#*before return 0, iclass 25, count 0 2006.257.23:02:50.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:50.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:50.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:02:50.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:02:50.24$vck44/va=3,8 2006.257.23:02:50.24#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.23:02:50.24#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.23:02:50.24#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:50.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:50.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:50.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:50.30#ibcon#enter wrdev, iclass 27, count 2 2006.257.23:02:50.30#ibcon#first serial, iclass 27, count 2 2006.257.23:02:50.30#ibcon#enter sib2, iclass 27, count 2 2006.257.23:02:50.30#ibcon#flushed, iclass 27, count 2 2006.257.23:02:50.30#ibcon#about to write, iclass 27, count 2 2006.257.23:02:50.30#ibcon#wrote, iclass 27, count 2 2006.257.23:02:50.30#ibcon#about to read 3, iclass 27, count 2 2006.257.23:02:50.32#ibcon#read 3, iclass 27, count 2 2006.257.23:02:50.32#ibcon#about to read 4, iclass 27, count 2 2006.257.23:02:50.32#ibcon#read 4, iclass 27, count 2 2006.257.23:02:50.32#ibcon#about to read 5, iclass 27, count 2 2006.257.23:02:50.32#ibcon#read 5, iclass 27, count 2 2006.257.23:02:50.32#ibcon#about to read 6, iclass 27, count 2 2006.257.23:02:50.32#ibcon#read 6, iclass 27, count 2 2006.257.23:02:50.32#ibcon#end of sib2, iclass 27, count 2 2006.257.23:02:50.32#ibcon#*mode == 0, iclass 27, count 2 2006.257.23:02:50.32#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.23:02:50.32#ibcon#[25=AT03-08\r\n] 2006.257.23:02:50.32#ibcon#*before write, iclass 27, count 2 2006.257.23:02:50.32#ibcon#enter sib2, iclass 27, count 2 2006.257.23:02:50.32#ibcon#flushed, iclass 27, count 2 2006.257.23:02:50.32#ibcon#about to write, iclass 27, count 2 2006.257.23:02:50.32#ibcon#wrote, iclass 27, count 2 2006.257.23:02:50.32#ibcon#about to read 3, iclass 27, count 2 2006.257.23:02:50.35#ibcon#read 3, iclass 27, count 2 2006.257.23:02:50.35#ibcon#about to read 4, iclass 27, count 2 2006.257.23:02:50.35#ibcon#read 4, iclass 27, count 2 2006.257.23:02:50.35#ibcon#about to read 5, iclass 27, count 2 2006.257.23:02:50.35#ibcon#read 5, iclass 27, count 2 2006.257.23:02:50.35#ibcon#about to read 6, iclass 27, count 2 2006.257.23:02:50.35#ibcon#read 6, iclass 27, count 2 2006.257.23:02:50.35#ibcon#end of sib2, iclass 27, count 2 2006.257.23:02:50.35#ibcon#*after write, iclass 27, count 2 2006.257.23:02:50.35#ibcon#*before return 0, iclass 27, count 2 2006.257.23:02:50.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:50.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:50.35#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.23:02:50.35#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:50.35#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:50.47#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:50.47#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:50.47#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:02:50.47#ibcon#first serial, iclass 27, count 0 2006.257.23:02:50.47#ibcon#enter sib2, iclass 27, count 0 2006.257.23:02:50.47#ibcon#flushed, iclass 27, count 0 2006.257.23:02:50.47#ibcon#about to write, iclass 27, count 0 2006.257.23:02:50.47#ibcon#wrote, iclass 27, count 0 2006.257.23:02:50.47#ibcon#about to read 3, iclass 27, count 0 2006.257.23:02:50.49#ibcon#read 3, iclass 27, count 0 2006.257.23:02:50.49#ibcon#about to read 4, iclass 27, count 0 2006.257.23:02:50.49#ibcon#read 4, iclass 27, count 0 2006.257.23:02:50.49#ibcon#about to read 5, iclass 27, count 0 2006.257.23:02:50.49#ibcon#read 5, iclass 27, count 0 2006.257.23:02:50.49#ibcon#about to read 6, iclass 27, count 0 2006.257.23:02:50.49#ibcon#read 6, iclass 27, count 0 2006.257.23:02:50.49#ibcon#end of sib2, iclass 27, count 0 2006.257.23:02:50.49#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:02:50.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:02:50.49#ibcon#[25=USB\r\n] 2006.257.23:02:50.49#ibcon#*before write, iclass 27, count 0 2006.257.23:02:50.49#ibcon#enter sib2, iclass 27, count 0 2006.257.23:02:50.49#ibcon#flushed, iclass 27, count 0 2006.257.23:02:50.49#ibcon#about to write, iclass 27, count 0 2006.257.23:02:50.49#ibcon#wrote, iclass 27, count 0 2006.257.23:02:50.49#ibcon#about to read 3, iclass 27, count 0 2006.257.23:02:50.52#ibcon#read 3, iclass 27, count 0 2006.257.23:02:50.52#ibcon#about to read 4, iclass 27, count 0 2006.257.23:02:50.52#ibcon#read 4, iclass 27, count 0 2006.257.23:02:50.52#ibcon#about to read 5, iclass 27, count 0 2006.257.23:02:50.52#ibcon#read 5, iclass 27, count 0 2006.257.23:02:50.52#ibcon#about to read 6, iclass 27, count 0 2006.257.23:02:50.52#ibcon#read 6, iclass 27, count 0 2006.257.23:02:50.52#ibcon#end of sib2, iclass 27, count 0 2006.257.23:02:50.52#ibcon#*after write, iclass 27, count 0 2006.257.23:02:50.52#ibcon#*before return 0, iclass 27, count 0 2006.257.23:02:50.52#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:50.52#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:50.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:02:50.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:02:50.52$vck44/valo=4,624.99 2006.257.23:02:50.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.23:02:50.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.23:02:50.52#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:50.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:50.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:50.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:50.52#ibcon#enter wrdev, iclass 29, count 0 2006.257.23:02:50.52#ibcon#first serial, iclass 29, count 0 2006.257.23:02:50.52#ibcon#enter sib2, iclass 29, count 0 2006.257.23:02:50.52#ibcon#flushed, iclass 29, count 0 2006.257.23:02:50.52#ibcon#about to write, iclass 29, count 0 2006.257.23:02:50.52#ibcon#wrote, iclass 29, count 0 2006.257.23:02:50.52#ibcon#about to read 3, iclass 29, count 0 2006.257.23:02:50.54#ibcon#read 3, iclass 29, count 0 2006.257.23:02:50.54#ibcon#about to read 4, iclass 29, count 0 2006.257.23:02:50.54#ibcon#read 4, iclass 29, count 0 2006.257.23:02:50.54#ibcon#about to read 5, iclass 29, count 0 2006.257.23:02:50.54#ibcon#read 5, iclass 29, count 0 2006.257.23:02:50.54#ibcon#about to read 6, iclass 29, count 0 2006.257.23:02:50.54#ibcon#read 6, iclass 29, count 0 2006.257.23:02:50.54#ibcon#end of sib2, iclass 29, count 0 2006.257.23:02:50.54#ibcon#*mode == 0, iclass 29, count 0 2006.257.23:02:50.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.23:02:50.54#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:02:50.54#ibcon#*before write, iclass 29, count 0 2006.257.23:02:50.54#ibcon#enter sib2, iclass 29, count 0 2006.257.23:02:50.54#ibcon#flushed, iclass 29, count 0 2006.257.23:02:50.54#ibcon#about to write, iclass 29, count 0 2006.257.23:02:50.54#ibcon#wrote, iclass 29, count 0 2006.257.23:02:50.54#ibcon#about to read 3, iclass 29, count 0 2006.257.23:02:50.58#ibcon#read 3, iclass 29, count 0 2006.257.23:02:50.58#ibcon#about to read 4, iclass 29, count 0 2006.257.23:02:50.58#ibcon#read 4, iclass 29, count 0 2006.257.23:02:50.58#ibcon#about to read 5, iclass 29, count 0 2006.257.23:02:50.58#ibcon#read 5, iclass 29, count 0 2006.257.23:02:50.58#ibcon#about to read 6, iclass 29, count 0 2006.257.23:02:50.58#ibcon#read 6, iclass 29, count 0 2006.257.23:02:50.58#ibcon#end of sib2, iclass 29, count 0 2006.257.23:02:50.58#ibcon#*after write, iclass 29, count 0 2006.257.23:02:50.58#ibcon#*before return 0, iclass 29, count 0 2006.257.23:02:50.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:50.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:50.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.23:02:50.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.23:02:50.58$vck44/va=4,7 2006.257.23:02:50.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.23:02:50.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.23:02:50.58#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:50.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:50.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:50.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:50.64#ibcon#enter wrdev, iclass 31, count 2 2006.257.23:02:50.64#ibcon#first serial, iclass 31, count 2 2006.257.23:02:50.64#ibcon#enter sib2, iclass 31, count 2 2006.257.23:02:50.64#ibcon#flushed, iclass 31, count 2 2006.257.23:02:50.64#ibcon#about to write, iclass 31, count 2 2006.257.23:02:50.64#ibcon#wrote, iclass 31, count 2 2006.257.23:02:50.64#ibcon#about to read 3, iclass 31, count 2 2006.257.23:02:50.66#ibcon#read 3, iclass 31, count 2 2006.257.23:02:50.66#ibcon#about to read 4, iclass 31, count 2 2006.257.23:02:50.66#ibcon#read 4, iclass 31, count 2 2006.257.23:02:50.66#ibcon#about to read 5, iclass 31, count 2 2006.257.23:02:50.66#ibcon#read 5, iclass 31, count 2 2006.257.23:02:50.66#ibcon#about to read 6, iclass 31, count 2 2006.257.23:02:50.66#ibcon#read 6, iclass 31, count 2 2006.257.23:02:50.66#ibcon#end of sib2, iclass 31, count 2 2006.257.23:02:50.66#ibcon#*mode == 0, iclass 31, count 2 2006.257.23:02:50.66#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.23:02:50.66#ibcon#[25=AT04-07\r\n] 2006.257.23:02:50.66#ibcon#*before write, iclass 31, count 2 2006.257.23:02:50.66#ibcon#enter sib2, iclass 31, count 2 2006.257.23:02:50.66#ibcon#flushed, iclass 31, count 2 2006.257.23:02:50.66#ibcon#about to write, iclass 31, count 2 2006.257.23:02:50.66#ibcon#wrote, iclass 31, count 2 2006.257.23:02:50.66#ibcon#about to read 3, iclass 31, count 2 2006.257.23:02:50.69#ibcon#read 3, iclass 31, count 2 2006.257.23:02:50.69#ibcon#about to read 4, iclass 31, count 2 2006.257.23:02:50.69#ibcon#read 4, iclass 31, count 2 2006.257.23:02:50.69#ibcon#about to read 5, iclass 31, count 2 2006.257.23:02:50.69#ibcon#read 5, iclass 31, count 2 2006.257.23:02:50.69#ibcon#about to read 6, iclass 31, count 2 2006.257.23:02:50.69#ibcon#read 6, iclass 31, count 2 2006.257.23:02:50.69#ibcon#end of sib2, iclass 31, count 2 2006.257.23:02:50.69#ibcon#*after write, iclass 31, count 2 2006.257.23:02:50.69#ibcon#*before return 0, iclass 31, count 2 2006.257.23:02:50.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:50.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:50.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.23:02:50.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:50.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:50.81#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:50.81#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:50.81#ibcon#enter wrdev, iclass 31, count 0 2006.257.23:02:50.81#ibcon#first serial, iclass 31, count 0 2006.257.23:02:50.81#ibcon#enter sib2, iclass 31, count 0 2006.257.23:02:50.81#ibcon#flushed, iclass 31, count 0 2006.257.23:02:50.81#ibcon#about to write, iclass 31, count 0 2006.257.23:02:50.81#ibcon#wrote, iclass 31, count 0 2006.257.23:02:50.81#ibcon#about to read 3, iclass 31, count 0 2006.257.23:02:50.83#ibcon#read 3, iclass 31, count 0 2006.257.23:02:50.83#ibcon#about to read 4, iclass 31, count 0 2006.257.23:02:50.83#ibcon#read 4, iclass 31, count 0 2006.257.23:02:50.83#ibcon#about to read 5, iclass 31, count 0 2006.257.23:02:50.83#ibcon#read 5, iclass 31, count 0 2006.257.23:02:50.83#ibcon#about to read 6, iclass 31, count 0 2006.257.23:02:50.83#ibcon#read 6, iclass 31, count 0 2006.257.23:02:50.83#ibcon#end of sib2, iclass 31, count 0 2006.257.23:02:50.83#ibcon#*mode == 0, iclass 31, count 0 2006.257.23:02:50.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.23:02:50.83#ibcon#[25=USB\r\n] 2006.257.23:02:50.83#ibcon#*before write, iclass 31, count 0 2006.257.23:02:50.83#ibcon#enter sib2, iclass 31, count 0 2006.257.23:02:50.83#ibcon#flushed, iclass 31, count 0 2006.257.23:02:50.83#ibcon#about to write, iclass 31, count 0 2006.257.23:02:50.83#ibcon#wrote, iclass 31, count 0 2006.257.23:02:50.83#ibcon#about to read 3, iclass 31, count 0 2006.257.23:02:50.86#ibcon#read 3, iclass 31, count 0 2006.257.23:02:50.86#ibcon#about to read 4, iclass 31, count 0 2006.257.23:02:50.86#ibcon#read 4, iclass 31, count 0 2006.257.23:02:50.86#ibcon#about to read 5, iclass 31, count 0 2006.257.23:02:50.86#ibcon#read 5, iclass 31, count 0 2006.257.23:02:50.86#ibcon#about to read 6, iclass 31, count 0 2006.257.23:02:50.86#ibcon#read 6, iclass 31, count 0 2006.257.23:02:50.86#ibcon#end of sib2, iclass 31, count 0 2006.257.23:02:50.86#ibcon#*after write, iclass 31, count 0 2006.257.23:02:50.86#ibcon#*before return 0, iclass 31, count 0 2006.257.23:02:50.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:50.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:50.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.23:02:50.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.23:02:50.86$vck44/valo=5,734.99 2006.257.23:02:50.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.23:02:50.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.23:02:50.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:50.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:50.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:50.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:50.86#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:02:50.86#ibcon#first serial, iclass 33, count 0 2006.257.23:02:50.86#ibcon#enter sib2, iclass 33, count 0 2006.257.23:02:50.86#ibcon#flushed, iclass 33, count 0 2006.257.23:02:50.86#ibcon#about to write, iclass 33, count 0 2006.257.23:02:50.86#ibcon#wrote, iclass 33, count 0 2006.257.23:02:50.86#ibcon#about to read 3, iclass 33, count 0 2006.257.23:02:50.88#ibcon#read 3, iclass 33, count 0 2006.257.23:02:50.88#ibcon#about to read 4, iclass 33, count 0 2006.257.23:02:50.88#ibcon#read 4, iclass 33, count 0 2006.257.23:02:50.88#ibcon#about to read 5, iclass 33, count 0 2006.257.23:02:50.88#ibcon#read 5, iclass 33, count 0 2006.257.23:02:50.88#ibcon#about to read 6, iclass 33, count 0 2006.257.23:02:50.88#ibcon#read 6, iclass 33, count 0 2006.257.23:02:50.88#ibcon#end of sib2, iclass 33, count 0 2006.257.23:02:50.88#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:02:50.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:02:50.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:02:50.88#ibcon#*before write, iclass 33, count 0 2006.257.23:02:50.88#ibcon#enter sib2, iclass 33, count 0 2006.257.23:02:50.88#ibcon#flushed, iclass 33, count 0 2006.257.23:02:50.88#ibcon#about to write, iclass 33, count 0 2006.257.23:02:50.88#ibcon#wrote, iclass 33, count 0 2006.257.23:02:50.88#ibcon#about to read 3, iclass 33, count 0 2006.257.23:02:50.92#ibcon#read 3, iclass 33, count 0 2006.257.23:02:50.92#ibcon#about to read 4, iclass 33, count 0 2006.257.23:02:50.92#ibcon#read 4, iclass 33, count 0 2006.257.23:02:50.92#ibcon#about to read 5, iclass 33, count 0 2006.257.23:02:50.92#ibcon#read 5, iclass 33, count 0 2006.257.23:02:50.92#ibcon#about to read 6, iclass 33, count 0 2006.257.23:02:50.92#ibcon#read 6, iclass 33, count 0 2006.257.23:02:50.92#ibcon#end of sib2, iclass 33, count 0 2006.257.23:02:50.92#ibcon#*after write, iclass 33, count 0 2006.257.23:02:50.92#ibcon#*before return 0, iclass 33, count 0 2006.257.23:02:50.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:50.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:50.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:02:50.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:02:50.92$vck44/va=5,4 2006.257.23:02:50.92#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.23:02:50.92#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.23:02:50.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:50.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:02:50.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:02:50.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:02:50.98#ibcon#enter wrdev, iclass 35, count 2 2006.257.23:02:50.98#ibcon#first serial, iclass 35, count 2 2006.257.23:02:50.98#ibcon#enter sib2, iclass 35, count 2 2006.257.23:02:50.98#ibcon#flushed, iclass 35, count 2 2006.257.23:02:50.98#ibcon#about to write, iclass 35, count 2 2006.257.23:02:50.98#ibcon#wrote, iclass 35, count 2 2006.257.23:02:50.98#ibcon#about to read 3, iclass 35, count 2 2006.257.23:02:51.00#ibcon#read 3, iclass 35, count 2 2006.257.23:02:51.00#ibcon#about to read 4, iclass 35, count 2 2006.257.23:02:51.00#ibcon#read 4, iclass 35, count 2 2006.257.23:02:51.00#ibcon#about to read 5, iclass 35, count 2 2006.257.23:02:51.00#ibcon#read 5, iclass 35, count 2 2006.257.23:02:51.00#ibcon#about to read 6, iclass 35, count 2 2006.257.23:02:51.00#ibcon#read 6, iclass 35, count 2 2006.257.23:02:51.00#ibcon#end of sib2, iclass 35, count 2 2006.257.23:02:51.00#ibcon#*mode == 0, iclass 35, count 2 2006.257.23:02:51.00#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.23:02:51.00#ibcon#[25=AT05-04\r\n] 2006.257.23:02:51.00#ibcon#*before write, iclass 35, count 2 2006.257.23:02:51.00#ibcon#enter sib2, iclass 35, count 2 2006.257.23:02:51.00#ibcon#flushed, iclass 35, count 2 2006.257.23:02:51.00#ibcon#about to write, iclass 35, count 2 2006.257.23:02:51.00#ibcon#wrote, iclass 35, count 2 2006.257.23:02:51.00#ibcon#about to read 3, iclass 35, count 2 2006.257.23:02:51.03#ibcon#read 3, iclass 35, count 2 2006.257.23:02:51.03#ibcon#about to read 4, iclass 35, count 2 2006.257.23:02:51.03#ibcon#read 4, iclass 35, count 2 2006.257.23:02:51.03#ibcon#about to read 5, iclass 35, count 2 2006.257.23:02:51.03#ibcon#read 5, iclass 35, count 2 2006.257.23:02:51.03#ibcon#about to read 6, iclass 35, count 2 2006.257.23:02:51.03#ibcon#read 6, iclass 35, count 2 2006.257.23:02:51.03#ibcon#end of sib2, iclass 35, count 2 2006.257.23:02:51.03#ibcon#*after write, iclass 35, count 2 2006.257.23:02:51.03#ibcon#*before return 0, iclass 35, count 2 2006.257.23:02:51.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:02:51.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:02:51.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.23:02:51.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:51.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:02:51.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:02:51.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:02:51.15#ibcon#enter wrdev, iclass 35, count 0 2006.257.23:02:51.15#ibcon#first serial, iclass 35, count 0 2006.257.23:02:51.15#ibcon#enter sib2, iclass 35, count 0 2006.257.23:02:51.15#ibcon#flushed, iclass 35, count 0 2006.257.23:02:51.15#ibcon#about to write, iclass 35, count 0 2006.257.23:02:51.15#ibcon#wrote, iclass 35, count 0 2006.257.23:02:51.15#ibcon#about to read 3, iclass 35, count 0 2006.257.23:02:51.17#ibcon#read 3, iclass 35, count 0 2006.257.23:02:51.17#ibcon#about to read 4, iclass 35, count 0 2006.257.23:02:51.17#ibcon#read 4, iclass 35, count 0 2006.257.23:02:51.17#ibcon#about to read 5, iclass 35, count 0 2006.257.23:02:51.17#ibcon#read 5, iclass 35, count 0 2006.257.23:02:51.17#ibcon#about to read 6, iclass 35, count 0 2006.257.23:02:51.17#ibcon#read 6, iclass 35, count 0 2006.257.23:02:51.17#ibcon#end of sib2, iclass 35, count 0 2006.257.23:02:51.17#ibcon#*mode == 0, iclass 35, count 0 2006.257.23:02:51.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.23:02:51.17#ibcon#[25=USB\r\n] 2006.257.23:02:51.17#ibcon#*before write, iclass 35, count 0 2006.257.23:02:51.17#ibcon#enter sib2, iclass 35, count 0 2006.257.23:02:51.17#ibcon#flushed, iclass 35, count 0 2006.257.23:02:51.17#ibcon#about to write, iclass 35, count 0 2006.257.23:02:51.17#ibcon#wrote, iclass 35, count 0 2006.257.23:02:51.17#ibcon#about to read 3, iclass 35, count 0 2006.257.23:02:51.20#ibcon#read 3, iclass 35, count 0 2006.257.23:02:51.20#ibcon#about to read 4, iclass 35, count 0 2006.257.23:02:51.20#ibcon#read 4, iclass 35, count 0 2006.257.23:02:51.20#ibcon#about to read 5, iclass 35, count 0 2006.257.23:02:51.20#ibcon#read 5, iclass 35, count 0 2006.257.23:02:51.20#ibcon#about to read 6, iclass 35, count 0 2006.257.23:02:51.20#ibcon#read 6, iclass 35, count 0 2006.257.23:02:51.20#ibcon#end of sib2, iclass 35, count 0 2006.257.23:02:51.20#ibcon#*after write, iclass 35, count 0 2006.257.23:02:51.20#ibcon#*before return 0, iclass 35, count 0 2006.257.23:02:51.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:02:51.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:02:51.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.23:02:51.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.23:02:51.20$vck44/valo=6,814.99 2006.257.23:02:51.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.23:02:51.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.23:02:51.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:51.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:02:51.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:02:51.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:02:51.20#ibcon#enter wrdev, iclass 37, count 0 2006.257.23:02:51.20#ibcon#first serial, iclass 37, count 0 2006.257.23:02:51.20#ibcon#enter sib2, iclass 37, count 0 2006.257.23:02:51.20#ibcon#flushed, iclass 37, count 0 2006.257.23:02:51.20#ibcon#about to write, iclass 37, count 0 2006.257.23:02:51.20#ibcon#wrote, iclass 37, count 0 2006.257.23:02:51.20#ibcon#about to read 3, iclass 37, count 0 2006.257.23:02:51.22#ibcon#read 3, iclass 37, count 0 2006.257.23:02:51.22#ibcon#about to read 4, iclass 37, count 0 2006.257.23:02:51.22#ibcon#read 4, iclass 37, count 0 2006.257.23:02:51.22#ibcon#about to read 5, iclass 37, count 0 2006.257.23:02:51.22#ibcon#read 5, iclass 37, count 0 2006.257.23:02:51.22#ibcon#about to read 6, iclass 37, count 0 2006.257.23:02:51.22#ibcon#read 6, iclass 37, count 0 2006.257.23:02:51.22#ibcon#end of sib2, iclass 37, count 0 2006.257.23:02:51.22#ibcon#*mode == 0, iclass 37, count 0 2006.257.23:02:51.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.23:02:51.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:02:51.22#ibcon#*before write, iclass 37, count 0 2006.257.23:02:51.22#ibcon#enter sib2, iclass 37, count 0 2006.257.23:02:51.22#ibcon#flushed, iclass 37, count 0 2006.257.23:02:51.22#ibcon#about to write, iclass 37, count 0 2006.257.23:02:51.22#ibcon#wrote, iclass 37, count 0 2006.257.23:02:51.22#ibcon#about to read 3, iclass 37, count 0 2006.257.23:02:51.26#ibcon#read 3, iclass 37, count 0 2006.257.23:02:51.26#ibcon#about to read 4, iclass 37, count 0 2006.257.23:02:51.26#ibcon#read 4, iclass 37, count 0 2006.257.23:02:51.26#ibcon#about to read 5, iclass 37, count 0 2006.257.23:02:51.26#ibcon#read 5, iclass 37, count 0 2006.257.23:02:51.26#ibcon#about to read 6, iclass 37, count 0 2006.257.23:02:51.26#ibcon#read 6, iclass 37, count 0 2006.257.23:02:51.26#ibcon#end of sib2, iclass 37, count 0 2006.257.23:02:51.26#ibcon#*after write, iclass 37, count 0 2006.257.23:02:51.26#ibcon#*before return 0, iclass 37, count 0 2006.257.23:02:51.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:02:51.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:02:51.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.23:02:51.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.23:02:51.26$vck44/va=6,4 2006.257.23:02:51.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.23:02:51.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.23:02:51.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:51.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:02:51.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:02:51.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:02:51.32#ibcon#enter wrdev, iclass 39, count 2 2006.257.23:02:51.32#ibcon#first serial, iclass 39, count 2 2006.257.23:02:51.32#ibcon#enter sib2, iclass 39, count 2 2006.257.23:02:51.32#ibcon#flushed, iclass 39, count 2 2006.257.23:02:51.32#ibcon#about to write, iclass 39, count 2 2006.257.23:02:51.32#ibcon#wrote, iclass 39, count 2 2006.257.23:02:51.32#ibcon#about to read 3, iclass 39, count 2 2006.257.23:02:51.34#ibcon#read 3, iclass 39, count 2 2006.257.23:02:51.34#ibcon#about to read 4, iclass 39, count 2 2006.257.23:02:51.34#ibcon#read 4, iclass 39, count 2 2006.257.23:02:51.34#ibcon#about to read 5, iclass 39, count 2 2006.257.23:02:51.34#ibcon#read 5, iclass 39, count 2 2006.257.23:02:51.34#ibcon#about to read 6, iclass 39, count 2 2006.257.23:02:51.34#ibcon#read 6, iclass 39, count 2 2006.257.23:02:51.34#ibcon#end of sib2, iclass 39, count 2 2006.257.23:02:51.34#ibcon#*mode == 0, iclass 39, count 2 2006.257.23:02:51.34#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.23:02:51.34#ibcon#[25=AT06-04\r\n] 2006.257.23:02:51.34#ibcon#*before write, iclass 39, count 2 2006.257.23:02:51.34#ibcon#enter sib2, iclass 39, count 2 2006.257.23:02:51.34#ibcon#flushed, iclass 39, count 2 2006.257.23:02:51.34#ibcon#about to write, iclass 39, count 2 2006.257.23:02:51.34#ibcon#wrote, iclass 39, count 2 2006.257.23:02:51.34#ibcon#about to read 3, iclass 39, count 2 2006.257.23:02:51.37#ibcon#read 3, iclass 39, count 2 2006.257.23:02:51.37#ibcon#about to read 4, iclass 39, count 2 2006.257.23:02:51.37#ibcon#read 4, iclass 39, count 2 2006.257.23:02:51.37#ibcon#about to read 5, iclass 39, count 2 2006.257.23:02:51.37#ibcon#read 5, iclass 39, count 2 2006.257.23:02:51.37#ibcon#about to read 6, iclass 39, count 2 2006.257.23:02:51.37#ibcon#read 6, iclass 39, count 2 2006.257.23:02:51.37#ibcon#end of sib2, iclass 39, count 2 2006.257.23:02:51.37#ibcon#*after write, iclass 39, count 2 2006.257.23:02:51.37#ibcon#*before return 0, iclass 39, count 2 2006.257.23:02:51.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:02:51.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:02:51.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.23:02:51.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:51.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:02:51.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:02:51.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:02:51.49#ibcon#enter wrdev, iclass 39, count 0 2006.257.23:02:51.49#ibcon#first serial, iclass 39, count 0 2006.257.23:02:51.49#ibcon#enter sib2, iclass 39, count 0 2006.257.23:02:51.49#ibcon#flushed, iclass 39, count 0 2006.257.23:02:51.49#ibcon#about to write, iclass 39, count 0 2006.257.23:02:51.49#ibcon#wrote, iclass 39, count 0 2006.257.23:02:51.49#ibcon#about to read 3, iclass 39, count 0 2006.257.23:02:51.51#ibcon#read 3, iclass 39, count 0 2006.257.23:02:51.51#ibcon#about to read 4, iclass 39, count 0 2006.257.23:02:51.51#ibcon#read 4, iclass 39, count 0 2006.257.23:02:51.51#ibcon#about to read 5, iclass 39, count 0 2006.257.23:02:51.51#ibcon#read 5, iclass 39, count 0 2006.257.23:02:51.51#ibcon#about to read 6, iclass 39, count 0 2006.257.23:02:51.51#ibcon#read 6, iclass 39, count 0 2006.257.23:02:51.51#ibcon#end of sib2, iclass 39, count 0 2006.257.23:02:51.51#ibcon#*mode == 0, iclass 39, count 0 2006.257.23:02:51.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.23:02:51.51#ibcon#[25=USB\r\n] 2006.257.23:02:51.51#ibcon#*before write, iclass 39, count 0 2006.257.23:02:51.51#ibcon#enter sib2, iclass 39, count 0 2006.257.23:02:51.51#ibcon#flushed, iclass 39, count 0 2006.257.23:02:51.51#ibcon#about to write, iclass 39, count 0 2006.257.23:02:51.51#ibcon#wrote, iclass 39, count 0 2006.257.23:02:51.51#ibcon#about to read 3, iclass 39, count 0 2006.257.23:02:51.54#ibcon#read 3, iclass 39, count 0 2006.257.23:02:51.54#ibcon#about to read 4, iclass 39, count 0 2006.257.23:02:51.54#ibcon#read 4, iclass 39, count 0 2006.257.23:02:51.54#ibcon#about to read 5, iclass 39, count 0 2006.257.23:02:51.54#ibcon#read 5, iclass 39, count 0 2006.257.23:02:51.54#ibcon#about to read 6, iclass 39, count 0 2006.257.23:02:51.54#ibcon#read 6, iclass 39, count 0 2006.257.23:02:51.54#ibcon#end of sib2, iclass 39, count 0 2006.257.23:02:51.54#ibcon#*after write, iclass 39, count 0 2006.257.23:02:51.54#ibcon#*before return 0, iclass 39, count 0 2006.257.23:02:51.54#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:02:51.54#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:02:51.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.23:02:51.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.23:02:51.54$vck44/valo=7,864.99 2006.257.23:02:51.54#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.23:02:51.54#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.23:02:51.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:51.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:51.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:51.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:51.54#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:02:51.54#ibcon#first serial, iclass 3, count 0 2006.257.23:02:51.54#ibcon#enter sib2, iclass 3, count 0 2006.257.23:02:51.54#ibcon#flushed, iclass 3, count 0 2006.257.23:02:51.54#ibcon#about to write, iclass 3, count 0 2006.257.23:02:51.54#ibcon#wrote, iclass 3, count 0 2006.257.23:02:51.54#ibcon#about to read 3, iclass 3, count 0 2006.257.23:02:51.56#ibcon#read 3, iclass 3, count 0 2006.257.23:02:51.56#ibcon#about to read 4, iclass 3, count 0 2006.257.23:02:51.56#ibcon#read 4, iclass 3, count 0 2006.257.23:02:51.56#ibcon#about to read 5, iclass 3, count 0 2006.257.23:02:51.56#ibcon#read 5, iclass 3, count 0 2006.257.23:02:51.56#ibcon#about to read 6, iclass 3, count 0 2006.257.23:02:51.56#ibcon#read 6, iclass 3, count 0 2006.257.23:02:51.56#ibcon#end of sib2, iclass 3, count 0 2006.257.23:02:51.56#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:02:51.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:02:51.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:02:51.56#ibcon#*before write, iclass 3, count 0 2006.257.23:02:51.56#ibcon#enter sib2, iclass 3, count 0 2006.257.23:02:51.56#ibcon#flushed, iclass 3, count 0 2006.257.23:02:51.56#ibcon#about to write, iclass 3, count 0 2006.257.23:02:51.56#ibcon#wrote, iclass 3, count 0 2006.257.23:02:51.56#ibcon#about to read 3, iclass 3, count 0 2006.257.23:02:51.60#ibcon#read 3, iclass 3, count 0 2006.257.23:02:51.60#ibcon#about to read 4, iclass 3, count 0 2006.257.23:02:51.60#ibcon#read 4, iclass 3, count 0 2006.257.23:02:51.60#ibcon#about to read 5, iclass 3, count 0 2006.257.23:02:51.60#ibcon#read 5, iclass 3, count 0 2006.257.23:02:51.60#ibcon#about to read 6, iclass 3, count 0 2006.257.23:02:51.60#ibcon#read 6, iclass 3, count 0 2006.257.23:02:51.60#ibcon#end of sib2, iclass 3, count 0 2006.257.23:02:51.60#ibcon#*after write, iclass 3, count 0 2006.257.23:02:51.60#ibcon#*before return 0, iclass 3, count 0 2006.257.23:02:51.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:51.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:51.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:02:51.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:02:51.60$vck44/va=7,4 2006.257.23:02:51.60#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.23:02:51.60#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.23:02:51.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:51.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:51.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:51.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:51.66#ibcon#enter wrdev, iclass 5, count 2 2006.257.23:02:51.66#ibcon#first serial, iclass 5, count 2 2006.257.23:02:51.66#ibcon#enter sib2, iclass 5, count 2 2006.257.23:02:51.66#ibcon#flushed, iclass 5, count 2 2006.257.23:02:51.66#ibcon#about to write, iclass 5, count 2 2006.257.23:02:51.66#ibcon#wrote, iclass 5, count 2 2006.257.23:02:51.66#ibcon#about to read 3, iclass 5, count 2 2006.257.23:02:51.68#ibcon#read 3, iclass 5, count 2 2006.257.23:02:51.68#ibcon#about to read 4, iclass 5, count 2 2006.257.23:02:51.68#ibcon#read 4, iclass 5, count 2 2006.257.23:02:51.68#ibcon#about to read 5, iclass 5, count 2 2006.257.23:02:51.68#ibcon#read 5, iclass 5, count 2 2006.257.23:02:51.68#ibcon#about to read 6, iclass 5, count 2 2006.257.23:02:51.68#ibcon#read 6, iclass 5, count 2 2006.257.23:02:51.68#ibcon#end of sib2, iclass 5, count 2 2006.257.23:02:51.68#ibcon#*mode == 0, iclass 5, count 2 2006.257.23:02:51.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.23:02:51.68#ibcon#[25=AT07-04\r\n] 2006.257.23:02:51.68#ibcon#*before write, iclass 5, count 2 2006.257.23:02:51.68#ibcon#enter sib2, iclass 5, count 2 2006.257.23:02:51.68#ibcon#flushed, iclass 5, count 2 2006.257.23:02:51.68#ibcon#about to write, iclass 5, count 2 2006.257.23:02:51.68#ibcon#wrote, iclass 5, count 2 2006.257.23:02:51.68#ibcon#about to read 3, iclass 5, count 2 2006.257.23:02:51.71#ibcon#read 3, iclass 5, count 2 2006.257.23:02:51.71#ibcon#about to read 4, iclass 5, count 2 2006.257.23:02:51.71#ibcon#read 4, iclass 5, count 2 2006.257.23:02:51.71#ibcon#about to read 5, iclass 5, count 2 2006.257.23:02:51.71#ibcon#read 5, iclass 5, count 2 2006.257.23:02:51.71#ibcon#about to read 6, iclass 5, count 2 2006.257.23:02:51.71#ibcon#read 6, iclass 5, count 2 2006.257.23:02:51.71#ibcon#end of sib2, iclass 5, count 2 2006.257.23:02:51.71#ibcon#*after write, iclass 5, count 2 2006.257.23:02:51.71#ibcon#*before return 0, iclass 5, count 2 2006.257.23:02:51.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:51.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:51.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.23:02:51.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:51.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:51.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:51.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:51.83#ibcon#enter wrdev, iclass 5, count 0 2006.257.23:02:51.83#ibcon#first serial, iclass 5, count 0 2006.257.23:02:51.83#ibcon#enter sib2, iclass 5, count 0 2006.257.23:02:51.83#ibcon#flushed, iclass 5, count 0 2006.257.23:02:51.83#ibcon#about to write, iclass 5, count 0 2006.257.23:02:51.83#ibcon#wrote, iclass 5, count 0 2006.257.23:02:51.83#ibcon#about to read 3, iclass 5, count 0 2006.257.23:02:51.85#ibcon#read 3, iclass 5, count 0 2006.257.23:02:51.85#ibcon#about to read 4, iclass 5, count 0 2006.257.23:02:51.85#ibcon#read 4, iclass 5, count 0 2006.257.23:02:51.85#ibcon#about to read 5, iclass 5, count 0 2006.257.23:02:51.85#ibcon#read 5, iclass 5, count 0 2006.257.23:02:51.85#ibcon#about to read 6, iclass 5, count 0 2006.257.23:02:51.85#ibcon#read 6, iclass 5, count 0 2006.257.23:02:51.85#ibcon#end of sib2, iclass 5, count 0 2006.257.23:02:51.85#ibcon#*mode == 0, iclass 5, count 0 2006.257.23:02:51.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.23:02:51.85#ibcon#[25=USB\r\n] 2006.257.23:02:51.85#ibcon#*before write, iclass 5, count 0 2006.257.23:02:51.85#ibcon#enter sib2, iclass 5, count 0 2006.257.23:02:51.85#ibcon#flushed, iclass 5, count 0 2006.257.23:02:51.85#ibcon#about to write, iclass 5, count 0 2006.257.23:02:51.85#ibcon#wrote, iclass 5, count 0 2006.257.23:02:51.85#ibcon#about to read 3, iclass 5, count 0 2006.257.23:02:51.88#ibcon#read 3, iclass 5, count 0 2006.257.23:02:51.88#ibcon#about to read 4, iclass 5, count 0 2006.257.23:02:51.88#ibcon#read 4, iclass 5, count 0 2006.257.23:02:51.88#ibcon#about to read 5, iclass 5, count 0 2006.257.23:02:51.88#ibcon#read 5, iclass 5, count 0 2006.257.23:02:51.88#ibcon#about to read 6, iclass 5, count 0 2006.257.23:02:51.88#ibcon#read 6, iclass 5, count 0 2006.257.23:02:51.88#ibcon#end of sib2, iclass 5, count 0 2006.257.23:02:51.88#ibcon#*after write, iclass 5, count 0 2006.257.23:02:51.88#ibcon#*before return 0, iclass 5, count 0 2006.257.23:02:51.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:51.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:51.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.23:02:51.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.23:02:51.88$vck44/valo=8,884.99 2006.257.23:02:51.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.23:02:51.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.23:02:51.88#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:51.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:51.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:51.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:51.88#ibcon#enter wrdev, iclass 7, count 0 2006.257.23:02:51.88#ibcon#first serial, iclass 7, count 0 2006.257.23:02:51.88#ibcon#enter sib2, iclass 7, count 0 2006.257.23:02:51.88#ibcon#flushed, iclass 7, count 0 2006.257.23:02:51.88#ibcon#about to write, iclass 7, count 0 2006.257.23:02:51.88#ibcon#wrote, iclass 7, count 0 2006.257.23:02:51.88#ibcon#about to read 3, iclass 7, count 0 2006.257.23:02:51.90#ibcon#read 3, iclass 7, count 0 2006.257.23:02:51.90#ibcon#about to read 4, iclass 7, count 0 2006.257.23:02:51.90#ibcon#read 4, iclass 7, count 0 2006.257.23:02:51.90#ibcon#about to read 5, iclass 7, count 0 2006.257.23:02:51.90#ibcon#read 5, iclass 7, count 0 2006.257.23:02:51.90#ibcon#about to read 6, iclass 7, count 0 2006.257.23:02:51.90#ibcon#read 6, iclass 7, count 0 2006.257.23:02:51.90#ibcon#end of sib2, iclass 7, count 0 2006.257.23:02:51.90#ibcon#*mode == 0, iclass 7, count 0 2006.257.23:02:51.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.23:02:51.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:02:51.90#ibcon#*before write, iclass 7, count 0 2006.257.23:02:51.90#ibcon#enter sib2, iclass 7, count 0 2006.257.23:02:51.90#ibcon#flushed, iclass 7, count 0 2006.257.23:02:51.90#ibcon#about to write, iclass 7, count 0 2006.257.23:02:51.90#ibcon#wrote, iclass 7, count 0 2006.257.23:02:51.90#ibcon#about to read 3, iclass 7, count 0 2006.257.23:02:51.94#ibcon#read 3, iclass 7, count 0 2006.257.23:02:51.94#ibcon#about to read 4, iclass 7, count 0 2006.257.23:02:51.94#ibcon#read 4, iclass 7, count 0 2006.257.23:02:51.94#ibcon#about to read 5, iclass 7, count 0 2006.257.23:02:51.94#ibcon#read 5, iclass 7, count 0 2006.257.23:02:51.94#ibcon#about to read 6, iclass 7, count 0 2006.257.23:02:51.94#ibcon#read 6, iclass 7, count 0 2006.257.23:02:51.94#ibcon#end of sib2, iclass 7, count 0 2006.257.23:02:51.94#ibcon#*after write, iclass 7, count 0 2006.257.23:02:51.94#ibcon#*before return 0, iclass 7, count 0 2006.257.23:02:51.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:51.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:51.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.23:02:51.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.23:02:51.94$vck44/va=8,4 2006.257.23:02:51.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.23:02:51.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.23:02:51.94#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:51.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:52.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:52.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:52.00#ibcon#enter wrdev, iclass 11, count 2 2006.257.23:02:52.00#ibcon#first serial, iclass 11, count 2 2006.257.23:02:52.00#ibcon#enter sib2, iclass 11, count 2 2006.257.23:02:52.00#ibcon#flushed, iclass 11, count 2 2006.257.23:02:52.00#ibcon#about to write, iclass 11, count 2 2006.257.23:02:52.00#ibcon#wrote, iclass 11, count 2 2006.257.23:02:52.00#ibcon#about to read 3, iclass 11, count 2 2006.257.23:02:52.02#ibcon#read 3, iclass 11, count 2 2006.257.23:02:52.02#ibcon#about to read 4, iclass 11, count 2 2006.257.23:02:52.02#ibcon#read 4, iclass 11, count 2 2006.257.23:02:52.02#ibcon#about to read 5, iclass 11, count 2 2006.257.23:02:52.02#ibcon#read 5, iclass 11, count 2 2006.257.23:02:52.02#ibcon#about to read 6, iclass 11, count 2 2006.257.23:02:52.02#ibcon#read 6, iclass 11, count 2 2006.257.23:02:52.02#ibcon#end of sib2, iclass 11, count 2 2006.257.23:02:52.02#ibcon#*mode == 0, iclass 11, count 2 2006.257.23:02:52.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.23:02:52.02#ibcon#[25=AT08-04\r\n] 2006.257.23:02:52.02#ibcon#*before write, iclass 11, count 2 2006.257.23:02:52.02#ibcon#enter sib2, iclass 11, count 2 2006.257.23:02:52.02#ibcon#flushed, iclass 11, count 2 2006.257.23:02:52.02#ibcon#about to write, iclass 11, count 2 2006.257.23:02:52.02#ibcon#wrote, iclass 11, count 2 2006.257.23:02:52.02#ibcon#about to read 3, iclass 11, count 2 2006.257.23:02:52.05#ibcon#read 3, iclass 11, count 2 2006.257.23:02:52.05#ibcon#about to read 4, iclass 11, count 2 2006.257.23:02:52.05#ibcon#read 4, iclass 11, count 2 2006.257.23:02:52.05#ibcon#about to read 5, iclass 11, count 2 2006.257.23:02:52.05#ibcon#read 5, iclass 11, count 2 2006.257.23:02:52.05#ibcon#about to read 6, iclass 11, count 2 2006.257.23:02:52.05#ibcon#read 6, iclass 11, count 2 2006.257.23:02:52.05#ibcon#end of sib2, iclass 11, count 2 2006.257.23:02:52.05#ibcon#*after write, iclass 11, count 2 2006.257.23:02:52.05#ibcon#*before return 0, iclass 11, count 2 2006.257.23:02:52.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:52.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:52.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.23:02:52.05#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:52.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:52.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:52.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:52.17#ibcon#enter wrdev, iclass 11, count 0 2006.257.23:02:52.17#ibcon#first serial, iclass 11, count 0 2006.257.23:02:52.17#ibcon#enter sib2, iclass 11, count 0 2006.257.23:02:52.17#ibcon#flushed, iclass 11, count 0 2006.257.23:02:52.17#ibcon#about to write, iclass 11, count 0 2006.257.23:02:52.17#ibcon#wrote, iclass 11, count 0 2006.257.23:02:52.17#ibcon#about to read 3, iclass 11, count 0 2006.257.23:02:52.19#ibcon#read 3, iclass 11, count 0 2006.257.23:02:52.19#ibcon#about to read 4, iclass 11, count 0 2006.257.23:02:52.19#ibcon#read 4, iclass 11, count 0 2006.257.23:02:52.19#ibcon#about to read 5, iclass 11, count 0 2006.257.23:02:52.19#ibcon#read 5, iclass 11, count 0 2006.257.23:02:52.19#ibcon#about to read 6, iclass 11, count 0 2006.257.23:02:52.19#ibcon#read 6, iclass 11, count 0 2006.257.23:02:52.19#ibcon#end of sib2, iclass 11, count 0 2006.257.23:02:52.19#ibcon#*mode == 0, iclass 11, count 0 2006.257.23:02:52.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.23:02:52.19#ibcon#[25=USB\r\n] 2006.257.23:02:52.19#ibcon#*before write, iclass 11, count 0 2006.257.23:02:52.19#ibcon#enter sib2, iclass 11, count 0 2006.257.23:02:52.19#ibcon#flushed, iclass 11, count 0 2006.257.23:02:52.19#ibcon#about to write, iclass 11, count 0 2006.257.23:02:52.19#ibcon#wrote, iclass 11, count 0 2006.257.23:02:52.19#ibcon#about to read 3, iclass 11, count 0 2006.257.23:02:52.22#ibcon#read 3, iclass 11, count 0 2006.257.23:02:52.22#ibcon#about to read 4, iclass 11, count 0 2006.257.23:02:52.22#ibcon#read 4, iclass 11, count 0 2006.257.23:02:52.22#ibcon#about to read 5, iclass 11, count 0 2006.257.23:02:52.22#ibcon#read 5, iclass 11, count 0 2006.257.23:02:52.22#ibcon#about to read 6, iclass 11, count 0 2006.257.23:02:52.22#ibcon#read 6, iclass 11, count 0 2006.257.23:02:52.22#ibcon#end of sib2, iclass 11, count 0 2006.257.23:02:52.22#ibcon#*after write, iclass 11, count 0 2006.257.23:02:52.22#ibcon#*before return 0, iclass 11, count 0 2006.257.23:02:52.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:52.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:52.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.23:02:52.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.23:02:52.22$vck44/vblo=1,629.99 2006.257.23:02:52.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.23:02:52.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.23:02:52.22#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:52.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:52.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:52.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:52.22#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:02:52.22#ibcon#first serial, iclass 13, count 0 2006.257.23:02:52.22#ibcon#enter sib2, iclass 13, count 0 2006.257.23:02:52.22#ibcon#flushed, iclass 13, count 0 2006.257.23:02:52.22#ibcon#about to write, iclass 13, count 0 2006.257.23:02:52.22#ibcon#wrote, iclass 13, count 0 2006.257.23:02:52.22#ibcon#about to read 3, iclass 13, count 0 2006.257.23:02:52.24#ibcon#read 3, iclass 13, count 0 2006.257.23:02:52.24#ibcon#about to read 4, iclass 13, count 0 2006.257.23:02:52.24#ibcon#read 4, iclass 13, count 0 2006.257.23:02:52.24#ibcon#about to read 5, iclass 13, count 0 2006.257.23:02:52.24#ibcon#read 5, iclass 13, count 0 2006.257.23:02:52.24#ibcon#about to read 6, iclass 13, count 0 2006.257.23:02:52.24#ibcon#read 6, iclass 13, count 0 2006.257.23:02:52.24#ibcon#end of sib2, iclass 13, count 0 2006.257.23:02:52.24#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:02:52.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:02:52.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:02:52.24#ibcon#*before write, iclass 13, count 0 2006.257.23:02:52.24#ibcon#enter sib2, iclass 13, count 0 2006.257.23:02:52.24#ibcon#flushed, iclass 13, count 0 2006.257.23:02:52.24#ibcon#about to write, iclass 13, count 0 2006.257.23:02:52.24#ibcon#wrote, iclass 13, count 0 2006.257.23:02:52.24#ibcon#about to read 3, iclass 13, count 0 2006.257.23:02:52.28#ibcon#read 3, iclass 13, count 0 2006.257.23:02:52.28#ibcon#about to read 4, iclass 13, count 0 2006.257.23:02:52.28#ibcon#read 4, iclass 13, count 0 2006.257.23:02:52.28#ibcon#about to read 5, iclass 13, count 0 2006.257.23:02:52.28#ibcon#read 5, iclass 13, count 0 2006.257.23:02:52.28#ibcon#about to read 6, iclass 13, count 0 2006.257.23:02:52.28#ibcon#read 6, iclass 13, count 0 2006.257.23:02:52.28#ibcon#end of sib2, iclass 13, count 0 2006.257.23:02:52.28#ibcon#*after write, iclass 13, count 0 2006.257.23:02:52.28#ibcon#*before return 0, iclass 13, count 0 2006.257.23:02:52.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:52.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:52.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:02:52.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:02:52.28$vck44/vb=1,4 2006.257.23:02:52.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.23:02:52.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.23:02:52.28#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:52.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:02:52.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:02:52.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:02:52.28#ibcon#enter wrdev, iclass 15, count 2 2006.257.23:02:52.28#ibcon#first serial, iclass 15, count 2 2006.257.23:02:52.28#ibcon#enter sib2, iclass 15, count 2 2006.257.23:02:52.28#ibcon#flushed, iclass 15, count 2 2006.257.23:02:52.28#ibcon#about to write, iclass 15, count 2 2006.257.23:02:52.28#ibcon#wrote, iclass 15, count 2 2006.257.23:02:52.28#ibcon#about to read 3, iclass 15, count 2 2006.257.23:02:52.30#ibcon#read 3, iclass 15, count 2 2006.257.23:02:52.30#ibcon#about to read 4, iclass 15, count 2 2006.257.23:02:52.30#ibcon#read 4, iclass 15, count 2 2006.257.23:02:52.30#ibcon#about to read 5, iclass 15, count 2 2006.257.23:02:52.30#ibcon#read 5, iclass 15, count 2 2006.257.23:02:52.30#ibcon#about to read 6, iclass 15, count 2 2006.257.23:02:52.30#ibcon#read 6, iclass 15, count 2 2006.257.23:02:52.30#ibcon#end of sib2, iclass 15, count 2 2006.257.23:02:52.30#ibcon#*mode == 0, iclass 15, count 2 2006.257.23:02:52.30#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.23:02:52.30#ibcon#[27=AT01-04\r\n] 2006.257.23:02:52.30#ibcon#*before write, iclass 15, count 2 2006.257.23:02:52.30#ibcon#enter sib2, iclass 15, count 2 2006.257.23:02:52.30#ibcon#flushed, iclass 15, count 2 2006.257.23:02:52.30#ibcon#about to write, iclass 15, count 2 2006.257.23:02:52.30#ibcon#wrote, iclass 15, count 2 2006.257.23:02:52.30#ibcon#about to read 3, iclass 15, count 2 2006.257.23:02:52.33#ibcon#read 3, iclass 15, count 2 2006.257.23:02:52.33#ibcon#about to read 4, iclass 15, count 2 2006.257.23:02:52.33#ibcon#read 4, iclass 15, count 2 2006.257.23:02:52.33#ibcon#about to read 5, iclass 15, count 2 2006.257.23:02:52.33#ibcon#read 5, iclass 15, count 2 2006.257.23:02:52.33#ibcon#about to read 6, iclass 15, count 2 2006.257.23:02:52.33#ibcon#read 6, iclass 15, count 2 2006.257.23:02:52.33#ibcon#end of sib2, iclass 15, count 2 2006.257.23:02:52.33#ibcon#*after write, iclass 15, count 2 2006.257.23:02:52.33#ibcon#*before return 0, iclass 15, count 2 2006.257.23:02:52.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:02:52.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:02:52.33#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.23:02:52.33#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:52.33#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:02:52.45#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:02:52.45#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:02:52.45#ibcon#enter wrdev, iclass 15, count 0 2006.257.23:02:52.45#ibcon#first serial, iclass 15, count 0 2006.257.23:02:52.45#ibcon#enter sib2, iclass 15, count 0 2006.257.23:02:52.45#ibcon#flushed, iclass 15, count 0 2006.257.23:02:52.45#ibcon#about to write, iclass 15, count 0 2006.257.23:02:52.45#ibcon#wrote, iclass 15, count 0 2006.257.23:02:52.45#ibcon#about to read 3, iclass 15, count 0 2006.257.23:02:52.47#ibcon#read 3, iclass 15, count 0 2006.257.23:02:52.47#ibcon#about to read 4, iclass 15, count 0 2006.257.23:02:52.47#ibcon#read 4, iclass 15, count 0 2006.257.23:02:52.47#ibcon#about to read 5, iclass 15, count 0 2006.257.23:02:52.47#ibcon#read 5, iclass 15, count 0 2006.257.23:02:52.47#ibcon#about to read 6, iclass 15, count 0 2006.257.23:02:52.47#ibcon#read 6, iclass 15, count 0 2006.257.23:02:52.47#ibcon#end of sib2, iclass 15, count 0 2006.257.23:02:52.47#ibcon#*mode == 0, iclass 15, count 0 2006.257.23:02:52.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.23:02:52.47#ibcon#[27=USB\r\n] 2006.257.23:02:52.47#ibcon#*before write, iclass 15, count 0 2006.257.23:02:52.47#ibcon#enter sib2, iclass 15, count 0 2006.257.23:02:52.47#ibcon#flushed, iclass 15, count 0 2006.257.23:02:52.47#ibcon#about to write, iclass 15, count 0 2006.257.23:02:52.47#ibcon#wrote, iclass 15, count 0 2006.257.23:02:52.47#ibcon#about to read 3, iclass 15, count 0 2006.257.23:02:52.50#ibcon#read 3, iclass 15, count 0 2006.257.23:02:52.50#ibcon#about to read 4, iclass 15, count 0 2006.257.23:02:52.50#ibcon#read 4, iclass 15, count 0 2006.257.23:02:52.50#ibcon#about to read 5, iclass 15, count 0 2006.257.23:02:52.50#ibcon#read 5, iclass 15, count 0 2006.257.23:02:52.50#ibcon#about to read 6, iclass 15, count 0 2006.257.23:02:52.50#ibcon#read 6, iclass 15, count 0 2006.257.23:02:52.50#ibcon#end of sib2, iclass 15, count 0 2006.257.23:02:52.50#ibcon#*after write, iclass 15, count 0 2006.257.23:02:52.50#ibcon#*before return 0, iclass 15, count 0 2006.257.23:02:52.50#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:02:52.50#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:02:52.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.23:02:52.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.23:02:52.50$vck44/vblo=2,634.99 2006.257.23:02:52.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.23:02:52.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.23:02:52.50#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:52.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:52.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:52.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:52.50#ibcon#enter wrdev, iclass 17, count 0 2006.257.23:02:52.50#ibcon#first serial, iclass 17, count 0 2006.257.23:02:52.50#ibcon#enter sib2, iclass 17, count 0 2006.257.23:02:52.50#ibcon#flushed, iclass 17, count 0 2006.257.23:02:52.50#ibcon#about to write, iclass 17, count 0 2006.257.23:02:52.50#ibcon#wrote, iclass 17, count 0 2006.257.23:02:52.50#ibcon#about to read 3, iclass 17, count 0 2006.257.23:02:52.52#ibcon#read 3, iclass 17, count 0 2006.257.23:02:52.52#ibcon#about to read 4, iclass 17, count 0 2006.257.23:02:52.52#ibcon#read 4, iclass 17, count 0 2006.257.23:02:52.52#ibcon#about to read 5, iclass 17, count 0 2006.257.23:02:52.52#ibcon#read 5, iclass 17, count 0 2006.257.23:02:52.52#ibcon#about to read 6, iclass 17, count 0 2006.257.23:02:52.52#ibcon#read 6, iclass 17, count 0 2006.257.23:02:52.52#ibcon#end of sib2, iclass 17, count 0 2006.257.23:02:52.52#ibcon#*mode == 0, iclass 17, count 0 2006.257.23:02:52.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.23:02:52.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:02:52.52#ibcon#*before write, iclass 17, count 0 2006.257.23:02:52.52#ibcon#enter sib2, iclass 17, count 0 2006.257.23:02:52.52#ibcon#flushed, iclass 17, count 0 2006.257.23:02:52.52#ibcon#about to write, iclass 17, count 0 2006.257.23:02:52.52#ibcon#wrote, iclass 17, count 0 2006.257.23:02:52.52#ibcon#about to read 3, iclass 17, count 0 2006.257.23:02:52.56#ibcon#read 3, iclass 17, count 0 2006.257.23:02:52.56#ibcon#about to read 4, iclass 17, count 0 2006.257.23:02:52.56#ibcon#read 4, iclass 17, count 0 2006.257.23:02:52.56#ibcon#about to read 5, iclass 17, count 0 2006.257.23:02:52.56#ibcon#read 5, iclass 17, count 0 2006.257.23:02:52.56#ibcon#about to read 6, iclass 17, count 0 2006.257.23:02:52.56#ibcon#read 6, iclass 17, count 0 2006.257.23:02:52.56#ibcon#end of sib2, iclass 17, count 0 2006.257.23:02:52.56#ibcon#*after write, iclass 17, count 0 2006.257.23:02:52.56#ibcon#*before return 0, iclass 17, count 0 2006.257.23:02:52.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:52.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:02:52.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.23:02:52.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.23:02:52.56$vck44/vb=2,5 2006.257.23:02:52.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.23:02:52.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.23:02:52.56#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:52.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:52.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:52.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:52.62#ibcon#enter wrdev, iclass 19, count 2 2006.257.23:02:52.62#ibcon#first serial, iclass 19, count 2 2006.257.23:02:52.62#ibcon#enter sib2, iclass 19, count 2 2006.257.23:02:52.62#ibcon#flushed, iclass 19, count 2 2006.257.23:02:52.62#ibcon#about to write, iclass 19, count 2 2006.257.23:02:52.62#ibcon#wrote, iclass 19, count 2 2006.257.23:02:52.62#ibcon#about to read 3, iclass 19, count 2 2006.257.23:02:52.64#ibcon#read 3, iclass 19, count 2 2006.257.23:02:52.64#ibcon#about to read 4, iclass 19, count 2 2006.257.23:02:52.64#ibcon#read 4, iclass 19, count 2 2006.257.23:02:52.64#ibcon#about to read 5, iclass 19, count 2 2006.257.23:02:52.64#ibcon#read 5, iclass 19, count 2 2006.257.23:02:52.64#ibcon#about to read 6, iclass 19, count 2 2006.257.23:02:52.64#ibcon#read 6, iclass 19, count 2 2006.257.23:02:52.64#ibcon#end of sib2, iclass 19, count 2 2006.257.23:02:52.64#ibcon#*mode == 0, iclass 19, count 2 2006.257.23:02:52.64#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.23:02:52.64#ibcon#[27=AT02-05\r\n] 2006.257.23:02:52.64#ibcon#*before write, iclass 19, count 2 2006.257.23:02:52.64#ibcon#enter sib2, iclass 19, count 2 2006.257.23:02:52.64#ibcon#flushed, iclass 19, count 2 2006.257.23:02:52.64#ibcon#about to write, iclass 19, count 2 2006.257.23:02:52.64#ibcon#wrote, iclass 19, count 2 2006.257.23:02:52.64#ibcon#about to read 3, iclass 19, count 2 2006.257.23:02:52.67#ibcon#read 3, iclass 19, count 2 2006.257.23:02:52.67#ibcon#about to read 4, iclass 19, count 2 2006.257.23:02:52.67#ibcon#read 4, iclass 19, count 2 2006.257.23:02:52.67#ibcon#about to read 5, iclass 19, count 2 2006.257.23:02:52.67#ibcon#read 5, iclass 19, count 2 2006.257.23:02:52.67#ibcon#about to read 6, iclass 19, count 2 2006.257.23:02:52.67#ibcon#read 6, iclass 19, count 2 2006.257.23:02:52.67#ibcon#end of sib2, iclass 19, count 2 2006.257.23:02:52.67#ibcon#*after write, iclass 19, count 2 2006.257.23:02:52.67#ibcon#*before return 0, iclass 19, count 2 2006.257.23:02:52.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:52.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:02:52.67#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.23:02:52.67#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:52.67#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:52.79#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:52.79#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:52.79#ibcon#enter wrdev, iclass 19, count 0 2006.257.23:02:52.79#ibcon#first serial, iclass 19, count 0 2006.257.23:02:52.79#ibcon#enter sib2, iclass 19, count 0 2006.257.23:02:52.79#ibcon#flushed, iclass 19, count 0 2006.257.23:02:52.79#ibcon#about to write, iclass 19, count 0 2006.257.23:02:52.79#ibcon#wrote, iclass 19, count 0 2006.257.23:02:52.79#ibcon#about to read 3, iclass 19, count 0 2006.257.23:02:52.81#ibcon#read 3, iclass 19, count 0 2006.257.23:02:52.81#ibcon#about to read 4, iclass 19, count 0 2006.257.23:02:52.81#ibcon#read 4, iclass 19, count 0 2006.257.23:02:52.81#ibcon#about to read 5, iclass 19, count 0 2006.257.23:02:52.81#ibcon#read 5, iclass 19, count 0 2006.257.23:02:52.81#ibcon#about to read 6, iclass 19, count 0 2006.257.23:02:52.81#ibcon#read 6, iclass 19, count 0 2006.257.23:02:52.81#ibcon#end of sib2, iclass 19, count 0 2006.257.23:02:52.81#ibcon#*mode == 0, iclass 19, count 0 2006.257.23:02:52.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.23:02:52.81#ibcon#[27=USB\r\n] 2006.257.23:02:52.81#ibcon#*before write, iclass 19, count 0 2006.257.23:02:52.81#ibcon#enter sib2, iclass 19, count 0 2006.257.23:02:52.81#ibcon#flushed, iclass 19, count 0 2006.257.23:02:52.81#ibcon#about to write, iclass 19, count 0 2006.257.23:02:52.81#ibcon#wrote, iclass 19, count 0 2006.257.23:02:52.81#ibcon#about to read 3, iclass 19, count 0 2006.257.23:02:52.84#ibcon#read 3, iclass 19, count 0 2006.257.23:02:52.84#ibcon#about to read 4, iclass 19, count 0 2006.257.23:02:52.84#ibcon#read 4, iclass 19, count 0 2006.257.23:02:52.84#ibcon#about to read 5, iclass 19, count 0 2006.257.23:02:52.84#ibcon#read 5, iclass 19, count 0 2006.257.23:02:52.84#ibcon#about to read 6, iclass 19, count 0 2006.257.23:02:52.84#ibcon#read 6, iclass 19, count 0 2006.257.23:02:52.84#ibcon#end of sib2, iclass 19, count 0 2006.257.23:02:52.84#ibcon#*after write, iclass 19, count 0 2006.257.23:02:52.84#ibcon#*before return 0, iclass 19, count 0 2006.257.23:02:52.84#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:52.84#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:02:52.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.23:02:52.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.23:02:52.84$vck44/vblo=3,649.99 2006.257.23:02:52.84#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.23:02:52.84#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.23:02:52.84#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:52.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:52.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:52.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:52.84#ibcon#enter wrdev, iclass 21, count 0 2006.257.23:02:52.84#ibcon#first serial, iclass 21, count 0 2006.257.23:02:52.84#ibcon#enter sib2, iclass 21, count 0 2006.257.23:02:52.84#ibcon#flushed, iclass 21, count 0 2006.257.23:02:52.84#ibcon#about to write, iclass 21, count 0 2006.257.23:02:52.84#ibcon#wrote, iclass 21, count 0 2006.257.23:02:52.84#ibcon#about to read 3, iclass 21, count 0 2006.257.23:02:52.86#ibcon#read 3, iclass 21, count 0 2006.257.23:02:52.86#ibcon#about to read 4, iclass 21, count 0 2006.257.23:02:52.86#ibcon#read 4, iclass 21, count 0 2006.257.23:02:52.86#ibcon#about to read 5, iclass 21, count 0 2006.257.23:02:52.86#ibcon#read 5, iclass 21, count 0 2006.257.23:02:52.86#ibcon#about to read 6, iclass 21, count 0 2006.257.23:02:52.86#ibcon#read 6, iclass 21, count 0 2006.257.23:02:52.86#ibcon#end of sib2, iclass 21, count 0 2006.257.23:02:52.86#ibcon#*mode == 0, iclass 21, count 0 2006.257.23:02:52.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.23:02:52.86#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:02:52.86#ibcon#*before write, iclass 21, count 0 2006.257.23:02:52.86#ibcon#enter sib2, iclass 21, count 0 2006.257.23:02:52.86#ibcon#flushed, iclass 21, count 0 2006.257.23:02:52.86#ibcon#about to write, iclass 21, count 0 2006.257.23:02:52.86#ibcon#wrote, iclass 21, count 0 2006.257.23:02:52.86#ibcon#about to read 3, iclass 21, count 0 2006.257.23:02:52.90#ibcon#read 3, iclass 21, count 0 2006.257.23:02:52.90#ibcon#about to read 4, iclass 21, count 0 2006.257.23:02:52.90#ibcon#read 4, iclass 21, count 0 2006.257.23:02:52.90#ibcon#about to read 5, iclass 21, count 0 2006.257.23:02:52.90#ibcon#read 5, iclass 21, count 0 2006.257.23:02:52.90#ibcon#about to read 6, iclass 21, count 0 2006.257.23:02:52.90#ibcon#read 6, iclass 21, count 0 2006.257.23:02:52.90#ibcon#end of sib2, iclass 21, count 0 2006.257.23:02:52.90#ibcon#*after write, iclass 21, count 0 2006.257.23:02:52.90#ibcon#*before return 0, iclass 21, count 0 2006.257.23:02:52.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:52.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:02:52.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.23:02:52.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.23:02:52.90$vck44/vb=3,4 2006.257.23:02:52.90#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.23:02:52.90#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.23:02:52.90#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:52.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:52.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:52.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:52.96#ibcon#enter wrdev, iclass 23, count 2 2006.257.23:02:52.96#ibcon#first serial, iclass 23, count 2 2006.257.23:02:52.96#ibcon#enter sib2, iclass 23, count 2 2006.257.23:02:52.96#ibcon#flushed, iclass 23, count 2 2006.257.23:02:52.96#ibcon#about to write, iclass 23, count 2 2006.257.23:02:52.96#ibcon#wrote, iclass 23, count 2 2006.257.23:02:52.96#ibcon#about to read 3, iclass 23, count 2 2006.257.23:02:52.98#ibcon#read 3, iclass 23, count 2 2006.257.23:02:52.98#ibcon#about to read 4, iclass 23, count 2 2006.257.23:02:52.98#ibcon#read 4, iclass 23, count 2 2006.257.23:02:52.98#ibcon#about to read 5, iclass 23, count 2 2006.257.23:02:52.98#ibcon#read 5, iclass 23, count 2 2006.257.23:02:52.98#ibcon#about to read 6, iclass 23, count 2 2006.257.23:02:52.98#ibcon#read 6, iclass 23, count 2 2006.257.23:02:52.98#ibcon#end of sib2, iclass 23, count 2 2006.257.23:02:52.98#ibcon#*mode == 0, iclass 23, count 2 2006.257.23:02:52.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.23:02:52.98#ibcon#[27=AT03-04\r\n] 2006.257.23:02:52.98#ibcon#*before write, iclass 23, count 2 2006.257.23:02:52.98#ibcon#enter sib2, iclass 23, count 2 2006.257.23:02:52.98#ibcon#flushed, iclass 23, count 2 2006.257.23:02:52.98#ibcon#about to write, iclass 23, count 2 2006.257.23:02:52.98#ibcon#wrote, iclass 23, count 2 2006.257.23:02:52.98#ibcon#about to read 3, iclass 23, count 2 2006.257.23:02:53.01#ibcon#read 3, iclass 23, count 2 2006.257.23:02:53.01#ibcon#about to read 4, iclass 23, count 2 2006.257.23:02:53.01#ibcon#read 4, iclass 23, count 2 2006.257.23:02:53.01#ibcon#about to read 5, iclass 23, count 2 2006.257.23:02:53.01#ibcon#read 5, iclass 23, count 2 2006.257.23:02:53.01#ibcon#about to read 6, iclass 23, count 2 2006.257.23:02:53.01#ibcon#read 6, iclass 23, count 2 2006.257.23:02:53.01#ibcon#end of sib2, iclass 23, count 2 2006.257.23:02:53.01#ibcon#*after write, iclass 23, count 2 2006.257.23:02:53.01#ibcon#*before return 0, iclass 23, count 2 2006.257.23:02:53.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:53.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:02:53.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.23:02:53.01#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:53.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:53.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:53.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:53.13#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:02:53.13#ibcon#first serial, iclass 23, count 0 2006.257.23:02:53.13#ibcon#enter sib2, iclass 23, count 0 2006.257.23:02:53.13#ibcon#flushed, iclass 23, count 0 2006.257.23:02:53.13#ibcon#about to write, iclass 23, count 0 2006.257.23:02:53.13#ibcon#wrote, iclass 23, count 0 2006.257.23:02:53.13#ibcon#about to read 3, iclass 23, count 0 2006.257.23:02:53.15#ibcon#read 3, iclass 23, count 0 2006.257.23:02:53.15#ibcon#about to read 4, iclass 23, count 0 2006.257.23:02:53.15#ibcon#read 4, iclass 23, count 0 2006.257.23:02:53.15#ibcon#about to read 5, iclass 23, count 0 2006.257.23:02:53.15#ibcon#read 5, iclass 23, count 0 2006.257.23:02:53.15#ibcon#about to read 6, iclass 23, count 0 2006.257.23:02:53.15#ibcon#read 6, iclass 23, count 0 2006.257.23:02:53.15#ibcon#end of sib2, iclass 23, count 0 2006.257.23:02:53.15#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:02:53.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:02:53.15#ibcon#[27=USB\r\n] 2006.257.23:02:53.15#ibcon#*before write, iclass 23, count 0 2006.257.23:02:53.15#ibcon#enter sib2, iclass 23, count 0 2006.257.23:02:53.15#ibcon#flushed, iclass 23, count 0 2006.257.23:02:53.15#ibcon#about to write, iclass 23, count 0 2006.257.23:02:53.15#ibcon#wrote, iclass 23, count 0 2006.257.23:02:53.15#ibcon#about to read 3, iclass 23, count 0 2006.257.23:02:53.18#ibcon#read 3, iclass 23, count 0 2006.257.23:02:53.18#ibcon#about to read 4, iclass 23, count 0 2006.257.23:02:53.18#ibcon#read 4, iclass 23, count 0 2006.257.23:02:53.18#ibcon#about to read 5, iclass 23, count 0 2006.257.23:02:53.18#ibcon#read 5, iclass 23, count 0 2006.257.23:02:53.18#ibcon#about to read 6, iclass 23, count 0 2006.257.23:02:53.18#ibcon#read 6, iclass 23, count 0 2006.257.23:02:53.18#ibcon#end of sib2, iclass 23, count 0 2006.257.23:02:53.18#ibcon#*after write, iclass 23, count 0 2006.257.23:02:53.18#ibcon#*before return 0, iclass 23, count 0 2006.257.23:02:53.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:53.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:02:53.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:02:53.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:02:53.18$vck44/vblo=4,679.99 2006.257.23:02:53.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.23:02:53.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.23:02:53.18#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:53.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:53.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:53.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:53.18#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:02:53.18#ibcon#first serial, iclass 25, count 0 2006.257.23:02:53.18#ibcon#enter sib2, iclass 25, count 0 2006.257.23:02:53.18#ibcon#flushed, iclass 25, count 0 2006.257.23:02:53.18#ibcon#about to write, iclass 25, count 0 2006.257.23:02:53.18#ibcon#wrote, iclass 25, count 0 2006.257.23:02:53.18#ibcon#about to read 3, iclass 25, count 0 2006.257.23:02:53.20#ibcon#read 3, iclass 25, count 0 2006.257.23:02:53.20#ibcon#about to read 4, iclass 25, count 0 2006.257.23:02:53.20#ibcon#read 4, iclass 25, count 0 2006.257.23:02:53.20#ibcon#about to read 5, iclass 25, count 0 2006.257.23:02:53.20#ibcon#read 5, iclass 25, count 0 2006.257.23:02:53.20#ibcon#about to read 6, iclass 25, count 0 2006.257.23:02:53.20#ibcon#read 6, iclass 25, count 0 2006.257.23:02:53.20#ibcon#end of sib2, iclass 25, count 0 2006.257.23:02:53.20#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:02:53.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:02:53.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:02:53.20#ibcon#*before write, iclass 25, count 0 2006.257.23:02:53.20#ibcon#enter sib2, iclass 25, count 0 2006.257.23:02:53.20#ibcon#flushed, iclass 25, count 0 2006.257.23:02:53.20#ibcon#about to write, iclass 25, count 0 2006.257.23:02:53.20#ibcon#wrote, iclass 25, count 0 2006.257.23:02:53.20#ibcon#about to read 3, iclass 25, count 0 2006.257.23:02:53.24#ibcon#read 3, iclass 25, count 0 2006.257.23:02:53.24#ibcon#about to read 4, iclass 25, count 0 2006.257.23:02:53.24#ibcon#read 4, iclass 25, count 0 2006.257.23:02:53.24#ibcon#about to read 5, iclass 25, count 0 2006.257.23:02:53.24#ibcon#read 5, iclass 25, count 0 2006.257.23:02:53.24#ibcon#about to read 6, iclass 25, count 0 2006.257.23:02:53.24#ibcon#read 6, iclass 25, count 0 2006.257.23:02:53.24#ibcon#end of sib2, iclass 25, count 0 2006.257.23:02:53.24#ibcon#*after write, iclass 25, count 0 2006.257.23:02:53.24#ibcon#*before return 0, iclass 25, count 0 2006.257.23:02:53.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:53.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:02:53.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:02:53.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:02:53.24$vck44/vb=4,5 2006.257.23:02:53.24#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.23:02:53.24#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.23:02:53.24#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:53.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:53.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:53.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:53.30#ibcon#enter wrdev, iclass 27, count 2 2006.257.23:02:53.30#ibcon#first serial, iclass 27, count 2 2006.257.23:02:53.30#ibcon#enter sib2, iclass 27, count 2 2006.257.23:02:53.30#ibcon#flushed, iclass 27, count 2 2006.257.23:02:53.30#ibcon#about to write, iclass 27, count 2 2006.257.23:02:53.30#ibcon#wrote, iclass 27, count 2 2006.257.23:02:53.30#ibcon#about to read 3, iclass 27, count 2 2006.257.23:02:53.32#ibcon#read 3, iclass 27, count 2 2006.257.23:02:53.32#ibcon#about to read 4, iclass 27, count 2 2006.257.23:02:53.32#ibcon#read 4, iclass 27, count 2 2006.257.23:02:53.32#ibcon#about to read 5, iclass 27, count 2 2006.257.23:02:53.32#ibcon#read 5, iclass 27, count 2 2006.257.23:02:53.32#ibcon#about to read 6, iclass 27, count 2 2006.257.23:02:53.32#ibcon#read 6, iclass 27, count 2 2006.257.23:02:53.32#ibcon#end of sib2, iclass 27, count 2 2006.257.23:02:53.32#ibcon#*mode == 0, iclass 27, count 2 2006.257.23:02:53.32#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.23:02:53.32#ibcon#[27=AT04-05\r\n] 2006.257.23:02:53.32#ibcon#*before write, iclass 27, count 2 2006.257.23:02:53.32#ibcon#enter sib2, iclass 27, count 2 2006.257.23:02:53.32#ibcon#flushed, iclass 27, count 2 2006.257.23:02:53.32#ibcon#about to write, iclass 27, count 2 2006.257.23:02:53.32#ibcon#wrote, iclass 27, count 2 2006.257.23:02:53.32#ibcon#about to read 3, iclass 27, count 2 2006.257.23:02:53.35#ibcon#read 3, iclass 27, count 2 2006.257.23:02:53.35#ibcon#about to read 4, iclass 27, count 2 2006.257.23:02:53.35#ibcon#read 4, iclass 27, count 2 2006.257.23:02:53.35#ibcon#about to read 5, iclass 27, count 2 2006.257.23:02:53.35#ibcon#read 5, iclass 27, count 2 2006.257.23:02:53.35#ibcon#about to read 6, iclass 27, count 2 2006.257.23:02:53.35#ibcon#read 6, iclass 27, count 2 2006.257.23:02:53.35#ibcon#end of sib2, iclass 27, count 2 2006.257.23:02:53.35#ibcon#*after write, iclass 27, count 2 2006.257.23:02:53.35#ibcon#*before return 0, iclass 27, count 2 2006.257.23:02:53.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:53.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:02:53.35#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.23:02:53.35#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:53.35#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:53.47#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:53.47#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:53.47#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:02:53.47#ibcon#first serial, iclass 27, count 0 2006.257.23:02:53.47#ibcon#enter sib2, iclass 27, count 0 2006.257.23:02:53.47#ibcon#flushed, iclass 27, count 0 2006.257.23:02:53.47#ibcon#about to write, iclass 27, count 0 2006.257.23:02:53.47#ibcon#wrote, iclass 27, count 0 2006.257.23:02:53.47#ibcon#about to read 3, iclass 27, count 0 2006.257.23:02:53.49#ibcon#read 3, iclass 27, count 0 2006.257.23:02:53.49#ibcon#about to read 4, iclass 27, count 0 2006.257.23:02:53.49#ibcon#read 4, iclass 27, count 0 2006.257.23:02:53.49#ibcon#about to read 5, iclass 27, count 0 2006.257.23:02:53.49#ibcon#read 5, iclass 27, count 0 2006.257.23:02:53.49#ibcon#about to read 6, iclass 27, count 0 2006.257.23:02:53.49#ibcon#read 6, iclass 27, count 0 2006.257.23:02:53.49#ibcon#end of sib2, iclass 27, count 0 2006.257.23:02:53.49#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:02:53.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:02:53.49#ibcon#[27=USB\r\n] 2006.257.23:02:53.49#ibcon#*before write, iclass 27, count 0 2006.257.23:02:53.49#ibcon#enter sib2, iclass 27, count 0 2006.257.23:02:53.49#ibcon#flushed, iclass 27, count 0 2006.257.23:02:53.49#ibcon#about to write, iclass 27, count 0 2006.257.23:02:53.49#ibcon#wrote, iclass 27, count 0 2006.257.23:02:53.49#ibcon#about to read 3, iclass 27, count 0 2006.257.23:02:53.52#ibcon#read 3, iclass 27, count 0 2006.257.23:02:53.52#ibcon#about to read 4, iclass 27, count 0 2006.257.23:02:53.52#ibcon#read 4, iclass 27, count 0 2006.257.23:02:53.52#ibcon#about to read 5, iclass 27, count 0 2006.257.23:02:53.52#ibcon#read 5, iclass 27, count 0 2006.257.23:02:53.52#ibcon#about to read 6, iclass 27, count 0 2006.257.23:02:53.52#ibcon#read 6, iclass 27, count 0 2006.257.23:02:53.52#ibcon#end of sib2, iclass 27, count 0 2006.257.23:02:53.52#ibcon#*after write, iclass 27, count 0 2006.257.23:02:53.52#ibcon#*before return 0, iclass 27, count 0 2006.257.23:02:53.52#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:53.52#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:02:53.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:02:53.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:02:53.52$vck44/vblo=5,709.99 2006.257.23:02:53.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.23:02:53.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.23:02:53.52#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:53.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:53.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:53.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:53.52#ibcon#enter wrdev, iclass 29, count 0 2006.257.23:02:53.52#ibcon#first serial, iclass 29, count 0 2006.257.23:02:53.52#ibcon#enter sib2, iclass 29, count 0 2006.257.23:02:53.52#ibcon#flushed, iclass 29, count 0 2006.257.23:02:53.52#ibcon#about to write, iclass 29, count 0 2006.257.23:02:53.52#ibcon#wrote, iclass 29, count 0 2006.257.23:02:53.52#ibcon#about to read 3, iclass 29, count 0 2006.257.23:02:53.54#ibcon#read 3, iclass 29, count 0 2006.257.23:02:53.54#ibcon#about to read 4, iclass 29, count 0 2006.257.23:02:53.54#ibcon#read 4, iclass 29, count 0 2006.257.23:02:53.54#ibcon#about to read 5, iclass 29, count 0 2006.257.23:02:53.54#ibcon#read 5, iclass 29, count 0 2006.257.23:02:53.54#ibcon#about to read 6, iclass 29, count 0 2006.257.23:02:53.54#ibcon#read 6, iclass 29, count 0 2006.257.23:02:53.54#ibcon#end of sib2, iclass 29, count 0 2006.257.23:02:53.54#ibcon#*mode == 0, iclass 29, count 0 2006.257.23:02:53.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.23:02:53.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:02:53.54#ibcon#*before write, iclass 29, count 0 2006.257.23:02:53.54#ibcon#enter sib2, iclass 29, count 0 2006.257.23:02:53.54#ibcon#flushed, iclass 29, count 0 2006.257.23:02:53.54#ibcon#about to write, iclass 29, count 0 2006.257.23:02:53.54#ibcon#wrote, iclass 29, count 0 2006.257.23:02:53.54#ibcon#about to read 3, iclass 29, count 0 2006.257.23:02:53.58#ibcon#read 3, iclass 29, count 0 2006.257.23:02:53.58#ibcon#about to read 4, iclass 29, count 0 2006.257.23:02:53.58#ibcon#read 4, iclass 29, count 0 2006.257.23:02:53.58#ibcon#about to read 5, iclass 29, count 0 2006.257.23:02:53.58#ibcon#read 5, iclass 29, count 0 2006.257.23:02:53.58#ibcon#about to read 6, iclass 29, count 0 2006.257.23:02:53.58#ibcon#read 6, iclass 29, count 0 2006.257.23:02:53.58#ibcon#end of sib2, iclass 29, count 0 2006.257.23:02:53.58#ibcon#*after write, iclass 29, count 0 2006.257.23:02:53.58#ibcon#*before return 0, iclass 29, count 0 2006.257.23:02:53.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:53.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:02:53.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.23:02:53.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.23:02:53.58$vck44/vb=5,4 2006.257.23:02:53.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.23:02:53.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.23:02:53.58#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:53.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:53.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:53.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:53.64#ibcon#enter wrdev, iclass 31, count 2 2006.257.23:02:53.64#ibcon#first serial, iclass 31, count 2 2006.257.23:02:53.64#ibcon#enter sib2, iclass 31, count 2 2006.257.23:02:53.64#ibcon#flushed, iclass 31, count 2 2006.257.23:02:53.64#ibcon#about to write, iclass 31, count 2 2006.257.23:02:53.64#ibcon#wrote, iclass 31, count 2 2006.257.23:02:53.64#ibcon#about to read 3, iclass 31, count 2 2006.257.23:02:53.66#ibcon#read 3, iclass 31, count 2 2006.257.23:02:53.66#ibcon#about to read 4, iclass 31, count 2 2006.257.23:02:53.66#ibcon#read 4, iclass 31, count 2 2006.257.23:02:53.66#ibcon#about to read 5, iclass 31, count 2 2006.257.23:02:53.66#ibcon#read 5, iclass 31, count 2 2006.257.23:02:53.66#ibcon#about to read 6, iclass 31, count 2 2006.257.23:02:53.66#ibcon#read 6, iclass 31, count 2 2006.257.23:02:53.66#ibcon#end of sib2, iclass 31, count 2 2006.257.23:02:53.66#ibcon#*mode == 0, iclass 31, count 2 2006.257.23:02:53.66#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.23:02:53.66#ibcon#[27=AT05-04\r\n] 2006.257.23:02:53.66#ibcon#*before write, iclass 31, count 2 2006.257.23:02:53.66#ibcon#enter sib2, iclass 31, count 2 2006.257.23:02:53.66#ibcon#flushed, iclass 31, count 2 2006.257.23:02:53.66#ibcon#about to write, iclass 31, count 2 2006.257.23:02:53.66#ibcon#wrote, iclass 31, count 2 2006.257.23:02:53.66#ibcon#about to read 3, iclass 31, count 2 2006.257.23:02:53.69#ibcon#read 3, iclass 31, count 2 2006.257.23:02:53.69#ibcon#about to read 4, iclass 31, count 2 2006.257.23:02:53.69#ibcon#read 4, iclass 31, count 2 2006.257.23:02:53.69#ibcon#about to read 5, iclass 31, count 2 2006.257.23:02:53.69#ibcon#read 5, iclass 31, count 2 2006.257.23:02:53.69#ibcon#about to read 6, iclass 31, count 2 2006.257.23:02:53.69#ibcon#read 6, iclass 31, count 2 2006.257.23:02:53.69#ibcon#end of sib2, iclass 31, count 2 2006.257.23:02:53.69#ibcon#*after write, iclass 31, count 2 2006.257.23:02:53.69#ibcon#*before return 0, iclass 31, count 2 2006.257.23:02:53.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:53.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:02:53.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.23:02:53.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:53.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:53.81#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:53.81#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:53.81#ibcon#enter wrdev, iclass 31, count 0 2006.257.23:02:53.81#ibcon#first serial, iclass 31, count 0 2006.257.23:02:53.81#ibcon#enter sib2, iclass 31, count 0 2006.257.23:02:53.81#ibcon#flushed, iclass 31, count 0 2006.257.23:02:53.81#ibcon#about to write, iclass 31, count 0 2006.257.23:02:53.81#ibcon#wrote, iclass 31, count 0 2006.257.23:02:53.81#ibcon#about to read 3, iclass 31, count 0 2006.257.23:02:53.83#ibcon#read 3, iclass 31, count 0 2006.257.23:02:53.83#ibcon#about to read 4, iclass 31, count 0 2006.257.23:02:53.83#ibcon#read 4, iclass 31, count 0 2006.257.23:02:53.83#ibcon#about to read 5, iclass 31, count 0 2006.257.23:02:53.83#ibcon#read 5, iclass 31, count 0 2006.257.23:02:53.83#ibcon#about to read 6, iclass 31, count 0 2006.257.23:02:53.83#ibcon#read 6, iclass 31, count 0 2006.257.23:02:53.83#ibcon#end of sib2, iclass 31, count 0 2006.257.23:02:53.83#ibcon#*mode == 0, iclass 31, count 0 2006.257.23:02:53.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.23:02:53.83#ibcon#[27=USB\r\n] 2006.257.23:02:53.83#ibcon#*before write, iclass 31, count 0 2006.257.23:02:53.83#ibcon#enter sib2, iclass 31, count 0 2006.257.23:02:53.83#ibcon#flushed, iclass 31, count 0 2006.257.23:02:53.83#ibcon#about to write, iclass 31, count 0 2006.257.23:02:53.83#ibcon#wrote, iclass 31, count 0 2006.257.23:02:53.83#ibcon#about to read 3, iclass 31, count 0 2006.257.23:02:53.86#ibcon#read 3, iclass 31, count 0 2006.257.23:02:53.86#ibcon#about to read 4, iclass 31, count 0 2006.257.23:02:53.86#ibcon#read 4, iclass 31, count 0 2006.257.23:02:53.86#ibcon#about to read 5, iclass 31, count 0 2006.257.23:02:53.86#ibcon#read 5, iclass 31, count 0 2006.257.23:02:53.86#ibcon#about to read 6, iclass 31, count 0 2006.257.23:02:53.86#ibcon#read 6, iclass 31, count 0 2006.257.23:02:53.86#ibcon#end of sib2, iclass 31, count 0 2006.257.23:02:53.86#ibcon#*after write, iclass 31, count 0 2006.257.23:02:53.86#ibcon#*before return 0, iclass 31, count 0 2006.257.23:02:53.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:53.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:02:53.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.23:02:53.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.23:02:53.86$vck44/vblo=6,719.99 2006.257.23:02:53.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.23:02:53.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.23:02:53.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:53.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:53.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:53.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:53.86#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:02:53.86#ibcon#first serial, iclass 33, count 0 2006.257.23:02:53.86#ibcon#enter sib2, iclass 33, count 0 2006.257.23:02:53.86#ibcon#flushed, iclass 33, count 0 2006.257.23:02:53.86#ibcon#about to write, iclass 33, count 0 2006.257.23:02:53.86#ibcon#wrote, iclass 33, count 0 2006.257.23:02:53.86#ibcon#about to read 3, iclass 33, count 0 2006.257.23:02:53.88#ibcon#read 3, iclass 33, count 0 2006.257.23:02:53.88#ibcon#about to read 4, iclass 33, count 0 2006.257.23:02:53.88#ibcon#read 4, iclass 33, count 0 2006.257.23:02:53.88#ibcon#about to read 5, iclass 33, count 0 2006.257.23:02:53.88#ibcon#read 5, iclass 33, count 0 2006.257.23:02:53.88#ibcon#about to read 6, iclass 33, count 0 2006.257.23:02:53.88#ibcon#read 6, iclass 33, count 0 2006.257.23:02:53.88#ibcon#end of sib2, iclass 33, count 0 2006.257.23:02:53.88#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:02:53.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:02:53.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:02:53.88#ibcon#*before write, iclass 33, count 0 2006.257.23:02:53.88#ibcon#enter sib2, iclass 33, count 0 2006.257.23:02:53.88#ibcon#flushed, iclass 33, count 0 2006.257.23:02:53.88#ibcon#about to write, iclass 33, count 0 2006.257.23:02:53.88#ibcon#wrote, iclass 33, count 0 2006.257.23:02:53.88#ibcon#about to read 3, iclass 33, count 0 2006.257.23:02:53.92#abcon#<5=/15 1.5 3.7 20.02 831016.0\r\n> 2006.257.23:02:53.92#ibcon#read 3, iclass 33, count 0 2006.257.23:02:53.92#ibcon#about to read 4, iclass 33, count 0 2006.257.23:02:53.92#ibcon#read 4, iclass 33, count 0 2006.257.23:02:53.92#ibcon#about to read 5, iclass 33, count 0 2006.257.23:02:53.92#ibcon#read 5, iclass 33, count 0 2006.257.23:02:53.92#ibcon#about to read 6, iclass 33, count 0 2006.257.23:02:53.92#ibcon#read 6, iclass 33, count 0 2006.257.23:02:53.92#ibcon#end of sib2, iclass 33, count 0 2006.257.23:02:53.92#ibcon#*after write, iclass 33, count 0 2006.257.23:02:53.92#ibcon#*before return 0, iclass 33, count 0 2006.257.23:02:53.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:53.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:02:53.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:02:53.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:02:53.92$vck44/vb=6,4 2006.257.23:02:53.92#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.23:02:53.92#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.23:02:53.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:53.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:02:53.94#abcon#{5=INTERFACE CLEAR} 2006.257.23:02:53.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:02:53.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:02:53.98#ibcon#enter wrdev, iclass 38, count 2 2006.257.23:02:53.98#ibcon#first serial, iclass 38, count 2 2006.257.23:02:53.98#ibcon#enter sib2, iclass 38, count 2 2006.257.23:02:53.98#ibcon#flushed, iclass 38, count 2 2006.257.23:02:53.98#ibcon#about to write, iclass 38, count 2 2006.257.23:02:53.98#ibcon#wrote, iclass 38, count 2 2006.257.23:02:53.98#ibcon#about to read 3, iclass 38, count 2 2006.257.23:02:54.00#ibcon#read 3, iclass 38, count 2 2006.257.23:02:54.00#ibcon#about to read 4, iclass 38, count 2 2006.257.23:02:54.00#ibcon#read 4, iclass 38, count 2 2006.257.23:02:54.00#ibcon#about to read 5, iclass 38, count 2 2006.257.23:02:54.00#ibcon#read 5, iclass 38, count 2 2006.257.23:02:54.00#ibcon#about to read 6, iclass 38, count 2 2006.257.23:02:54.00#ibcon#read 6, iclass 38, count 2 2006.257.23:02:54.00#ibcon#end of sib2, iclass 38, count 2 2006.257.23:02:54.00#ibcon#*mode == 0, iclass 38, count 2 2006.257.23:02:54.00#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.23:02:54.00#ibcon#[27=AT06-04\r\n] 2006.257.23:02:54.00#ibcon#*before write, iclass 38, count 2 2006.257.23:02:54.00#ibcon#enter sib2, iclass 38, count 2 2006.257.23:02:54.00#ibcon#flushed, iclass 38, count 2 2006.257.23:02:54.00#ibcon#about to write, iclass 38, count 2 2006.257.23:02:54.00#ibcon#wrote, iclass 38, count 2 2006.257.23:02:54.00#ibcon#about to read 3, iclass 38, count 2 2006.257.23:02:54.00#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:02:54.03#ibcon#read 3, iclass 38, count 2 2006.257.23:02:54.03#ibcon#about to read 4, iclass 38, count 2 2006.257.23:02:54.03#ibcon#read 4, iclass 38, count 2 2006.257.23:02:54.03#ibcon#about to read 5, iclass 38, count 2 2006.257.23:02:54.03#ibcon#read 5, iclass 38, count 2 2006.257.23:02:54.03#ibcon#about to read 6, iclass 38, count 2 2006.257.23:02:54.03#ibcon#read 6, iclass 38, count 2 2006.257.23:02:54.03#ibcon#end of sib2, iclass 38, count 2 2006.257.23:02:54.03#ibcon#*after write, iclass 38, count 2 2006.257.23:02:54.03#ibcon#*before return 0, iclass 38, count 2 2006.257.23:02:54.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:02:54.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:02:54.03#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.23:02:54.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:54.03#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:02:54.15#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:02:54.15#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:02:54.15#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:02:54.15#ibcon#first serial, iclass 38, count 0 2006.257.23:02:54.15#ibcon#enter sib2, iclass 38, count 0 2006.257.23:02:54.15#ibcon#flushed, iclass 38, count 0 2006.257.23:02:54.15#ibcon#about to write, iclass 38, count 0 2006.257.23:02:54.15#ibcon#wrote, iclass 38, count 0 2006.257.23:02:54.15#ibcon#about to read 3, iclass 38, count 0 2006.257.23:02:54.17#ibcon#read 3, iclass 38, count 0 2006.257.23:02:54.17#ibcon#about to read 4, iclass 38, count 0 2006.257.23:02:54.17#ibcon#read 4, iclass 38, count 0 2006.257.23:02:54.17#ibcon#about to read 5, iclass 38, count 0 2006.257.23:02:54.17#ibcon#read 5, iclass 38, count 0 2006.257.23:02:54.17#ibcon#about to read 6, iclass 38, count 0 2006.257.23:02:54.17#ibcon#read 6, iclass 38, count 0 2006.257.23:02:54.17#ibcon#end of sib2, iclass 38, count 0 2006.257.23:02:54.17#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:02:54.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:02:54.17#ibcon#[27=USB\r\n] 2006.257.23:02:54.17#ibcon#*before write, iclass 38, count 0 2006.257.23:02:54.17#ibcon#enter sib2, iclass 38, count 0 2006.257.23:02:54.17#ibcon#flushed, iclass 38, count 0 2006.257.23:02:54.17#ibcon#about to write, iclass 38, count 0 2006.257.23:02:54.17#ibcon#wrote, iclass 38, count 0 2006.257.23:02:54.17#ibcon#about to read 3, iclass 38, count 0 2006.257.23:02:54.20#ibcon#read 3, iclass 38, count 0 2006.257.23:02:54.20#ibcon#about to read 4, iclass 38, count 0 2006.257.23:02:54.20#ibcon#read 4, iclass 38, count 0 2006.257.23:02:54.20#ibcon#about to read 5, iclass 38, count 0 2006.257.23:02:54.20#ibcon#read 5, iclass 38, count 0 2006.257.23:02:54.20#ibcon#about to read 6, iclass 38, count 0 2006.257.23:02:54.20#ibcon#read 6, iclass 38, count 0 2006.257.23:02:54.20#ibcon#end of sib2, iclass 38, count 0 2006.257.23:02:54.20#ibcon#*after write, iclass 38, count 0 2006.257.23:02:54.20#ibcon#*before return 0, iclass 38, count 0 2006.257.23:02:54.20#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:02:54.20#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:02:54.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:02:54.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:02:54.20$vck44/vblo=7,734.99 2006.257.23:02:54.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.23:02:54.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.23:02:54.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:54.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:54.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:54.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:54.20#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:02:54.20#ibcon#first serial, iclass 3, count 0 2006.257.23:02:54.20#ibcon#enter sib2, iclass 3, count 0 2006.257.23:02:54.20#ibcon#flushed, iclass 3, count 0 2006.257.23:02:54.20#ibcon#about to write, iclass 3, count 0 2006.257.23:02:54.20#ibcon#wrote, iclass 3, count 0 2006.257.23:02:54.20#ibcon#about to read 3, iclass 3, count 0 2006.257.23:02:54.22#ibcon#read 3, iclass 3, count 0 2006.257.23:02:54.22#ibcon#about to read 4, iclass 3, count 0 2006.257.23:02:54.22#ibcon#read 4, iclass 3, count 0 2006.257.23:02:54.22#ibcon#about to read 5, iclass 3, count 0 2006.257.23:02:54.22#ibcon#read 5, iclass 3, count 0 2006.257.23:02:54.22#ibcon#about to read 6, iclass 3, count 0 2006.257.23:02:54.22#ibcon#read 6, iclass 3, count 0 2006.257.23:02:54.22#ibcon#end of sib2, iclass 3, count 0 2006.257.23:02:54.22#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:02:54.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:02:54.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:02:54.22#ibcon#*before write, iclass 3, count 0 2006.257.23:02:54.22#ibcon#enter sib2, iclass 3, count 0 2006.257.23:02:54.22#ibcon#flushed, iclass 3, count 0 2006.257.23:02:54.22#ibcon#about to write, iclass 3, count 0 2006.257.23:02:54.22#ibcon#wrote, iclass 3, count 0 2006.257.23:02:54.22#ibcon#about to read 3, iclass 3, count 0 2006.257.23:02:54.26#ibcon#read 3, iclass 3, count 0 2006.257.23:02:54.26#ibcon#about to read 4, iclass 3, count 0 2006.257.23:02:54.26#ibcon#read 4, iclass 3, count 0 2006.257.23:02:54.26#ibcon#about to read 5, iclass 3, count 0 2006.257.23:02:54.26#ibcon#read 5, iclass 3, count 0 2006.257.23:02:54.26#ibcon#about to read 6, iclass 3, count 0 2006.257.23:02:54.26#ibcon#read 6, iclass 3, count 0 2006.257.23:02:54.26#ibcon#end of sib2, iclass 3, count 0 2006.257.23:02:54.26#ibcon#*after write, iclass 3, count 0 2006.257.23:02:54.26#ibcon#*before return 0, iclass 3, count 0 2006.257.23:02:54.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:54.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:02:54.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:02:54.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:02:54.26$vck44/vb=7,4 2006.257.23:02:54.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.23:02:54.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.23:02:54.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:54.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:54.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:54.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:54.32#ibcon#enter wrdev, iclass 5, count 2 2006.257.23:02:54.32#ibcon#first serial, iclass 5, count 2 2006.257.23:02:54.32#ibcon#enter sib2, iclass 5, count 2 2006.257.23:02:54.32#ibcon#flushed, iclass 5, count 2 2006.257.23:02:54.32#ibcon#about to write, iclass 5, count 2 2006.257.23:02:54.32#ibcon#wrote, iclass 5, count 2 2006.257.23:02:54.32#ibcon#about to read 3, iclass 5, count 2 2006.257.23:02:54.34#ibcon#read 3, iclass 5, count 2 2006.257.23:02:54.34#ibcon#about to read 4, iclass 5, count 2 2006.257.23:02:54.34#ibcon#read 4, iclass 5, count 2 2006.257.23:02:54.34#ibcon#about to read 5, iclass 5, count 2 2006.257.23:02:54.34#ibcon#read 5, iclass 5, count 2 2006.257.23:02:54.34#ibcon#about to read 6, iclass 5, count 2 2006.257.23:02:54.34#ibcon#read 6, iclass 5, count 2 2006.257.23:02:54.34#ibcon#end of sib2, iclass 5, count 2 2006.257.23:02:54.34#ibcon#*mode == 0, iclass 5, count 2 2006.257.23:02:54.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.23:02:54.34#ibcon#[27=AT07-04\r\n] 2006.257.23:02:54.34#ibcon#*before write, iclass 5, count 2 2006.257.23:02:54.34#ibcon#enter sib2, iclass 5, count 2 2006.257.23:02:54.34#ibcon#flushed, iclass 5, count 2 2006.257.23:02:54.34#ibcon#about to write, iclass 5, count 2 2006.257.23:02:54.34#ibcon#wrote, iclass 5, count 2 2006.257.23:02:54.34#ibcon#about to read 3, iclass 5, count 2 2006.257.23:02:54.37#ibcon#read 3, iclass 5, count 2 2006.257.23:02:54.37#ibcon#about to read 4, iclass 5, count 2 2006.257.23:02:54.37#ibcon#read 4, iclass 5, count 2 2006.257.23:02:54.37#ibcon#about to read 5, iclass 5, count 2 2006.257.23:02:54.37#ibcon#read 5, iclass 5, count 2 2006.257.23:02:54.37#ibcon#about to read 6, iclass 5, count 2 2006.257.23:02:54.37#ibcon#read 6, iclass 5, count 2 2006.257.23:02:54.37#ibcon#end of sib2, iclass 5, count 2 2006.257.23:02:54.37#ibcon#*after write, iclass 5, count 2 2006.257.23:02:54.37#ibcon#*before return 0, iclass 5, count 2 2006.257.23:02:54.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:54.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:02:54.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.23:02:54.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:54.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:54.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:54.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:54.49#ibcon#enter wrdev, iclass 5, count 0 2006.257.23:02:54.49#ibcon#first serial, iclass 5, count 0 2006.257.23:02:54.49#ibcon#enter sib2, iclass 5, count 0 2006.257.23:02:54.49#ibcon#flushed, iclass 5, count 0 2006.257.23:02:54.49#ibcon#about to write, iclass 5, count 0 2006.257.23:02:54.49#ibcon#wrote, iclass 5, count 0 2006.257.23:02:54.49#ibcon#about to read 3, iclass 5, count 0 2006.257.23:02:54.51#ibcon#read 3, iclass 5, count 0 2006.257.23:02:54.51#ibcon#about to read 4, iclass 5, count 0 2006.257.23:02:54.51#ibcon#read 4, iclass 5, count 0 2006.257.23:02:54.51#ibcon#about to read 5, iclass 5, count 0 2006.257.23:02:54.51#ibcon#read 5, iclass 5, count 0 2006.257.23:02:54.51#ibcon#about to read 6, iclass 5, count 0 2006.257.23:02:54.51#ibcon#read 6, iclass 5, count 0 2006.257.23:02:54.51#ibcon#end of sib2, iclass 5, count 0 2006.257.23:02:54.51#ibcon#*mode == 0, iclass 5, count 0 2006.257.23:02:54.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.23:02:54.51#ibcon#[27=USB\r\n] 2006.257.23:02:54.51#ibcon#*before write, iclass 5, count 0 2006.257.23:02:54.51#ibcon#enter sib2, iclass 5, count 0 2006.257.23:02:54.51#ibcon#flushed, iclass 5, count 0 2006.257.23:02:54.51#ibcon#about to write, iclass 5, count 0 2006.257.23:02:54.51#ibcon#wrote, iclass 5, count 0 2006.257.23:02:54.51#ibcon#about to read 3, iclass 5, count 0 2006.257.23:02:54.54#ibcon#read 3, iclass 5, count 0 2006.257.23:02:54.54#ibcon#about to read 4, iclass 5, count 0 2006.257.23:02:54.54#ibcon#read 4, iclass 5, count 0 2006.257.23:02:54.54#ibcon#about to read 5, iclass 5, count 0 2006.257.23:02:54.54#ibcon#read 5, iclass 5, count 0 2006.257.23:02:54.54#ibcon#about to read 6, iclass 5, count 0 2006.257.23:02:54.54#ibcon#read 6, iclass 5, count 0 2006.257.23:02:54.54#ibcon#end of sib2, iclass 5, count 0 2006.257.23:02:54.54#ibcon#*after write, iclass 5, count 0 2006.257.23:02:54.54#ibcon#*before return 0, iclass 5, count 0 2006.257.23:02:54.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:54.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:02:54.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.23:02:54.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.23:02:54.54$vck44/vblo=8,744.99 2006.257.23:02:54.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.23:02:54.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.23:02:54.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:02:54.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:54.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:54.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:54.54#ibcon#enter wrdev, iclass 7, count 0 2006.257.23:02:54.54#ibcon#first serial, iclass 7, count 0 2006.257.23:02:54.54#ibcon#enter sib2, iclass 7, count 0 2006.257.23:02:54.54#ibcon#flushed, iclass 7, count 0 2006.257.23:02:54.54#ibcon#about to write, iclass 7, count 0 2006.257.23:02:54.54#ibcon#wrote, iclass 7, count 0 2006.257.23:02:54.54#ibcon#about to read 3, iclass 7, count 0 2006.257.23:02:54.56#ibcon#read 3, iclass 7, count 0 2006.257.23:02:54.56#ibcon#about to read 4, iclass 7, count 0 2006.257.23:02:54.56#ibcon#read 4, iclass 7, count 0 2006.257.23:02:54.56#ibcon#about to read 5, iclass 7, count 0 2006.257.23:02:54.56#ibcon#read 5, iclass 7, count 0 2006.257.23:02:54.56#ibcon#about to read 6, iclass 7, count 0 2006.257.23:02:54.56#ibcon#read 6, iclass 7, count 0 2006.257.23:02:54.56#ibcon#end of sib2, iclass 7, count 0 2006.257.23:02:54.56#ibcon#*mode == 0, iclass 7, count 0 2006.257.23:02:54.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.23:02:54.56#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:02:54.56#ibcon#*before write, iclass 7, count 0 2006.257.23:02:54.56#ibcon#enter sib2, iclass 7, count 0 2006.257.23:02:54.56#ibcon#flushed, iclass 7, count 0 2006.257.23:02:54.56#ibcon#about to write, iclass 7, count 0 2006.257.23:02:54.56#ibcon#wrote, iclass 7, count 0 2006.257.23:02:54.56#ibcon#about to read 3, iclass 7, count 0 2006.257.23:02:54.60#ibcon#read 3, iclass 7, count 0 2006.257.23:02:54.60#ibcon#about to read 4, iclass 7, count 0 2006.257.23:02:54.60#ibcon#read 4, iclass 7, count 0 2006.257.23:02:54.60#ibcon#about to read 5, iclass 7, count 0 2006.257.23:02:54.60#ibcon#read 5, iclass 7, count 0 2006.257.23:02:54.60#ibcon#about to read 6, iclass 7, count 0 2006.257.23:02:54.60#ibcon#read 6, iclass 7, count 0 2006.257.23:02:54.60#ibcon#end of sib2, iclass 7, count 0 2006.257.23:02:54.60#ibcon#*after write, iclass 7, count 0 2006.257.23:02:54.60#ibcon#*before return 0, iclass 7, count 0 2006.257.23:02:54.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:54.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:02:54.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.23:02:54.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.23:02:54.60$vck44/vb=8,4 2006.257.23:02:54.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.23:02:54.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.23:02:54.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:02:54.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:54.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:54.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:54.66#ibcon#enter wrdev, iclass 11, count 2 2006.257.23:02:54.66#ibcon#first serial, iclass 11, count 2 2006.257.23:02:54.66#ibcon#enter sib2, iclass 11, count 2 2006.257.23:02:54.66#ibcon#flushed, iclass 11, count 2 2006.257.23:02:54.66#ibcon#about to write, iclass 11, count 2 2006.257.23:02:54.66#ibcon#wrote, iclass 11, count 2 2006.257.23:02:54.66#ibcon#about to read 3, iclass 11, count 2 2006.257.23:02:54.68#ibcon#read 3, iclass 11, count 2 2006.257.23:02:54.68#ibcon#about to read 4, iclass 11, count 2 2006.257.23:02:54.68#ibcon#read 4, iclass 11, count 2 2006.257.23:02:54.68#ibcon#about to read 5, iclass 11, count 2 2006.257.23:02:54.68#ibcon#read 5, iclass 11, count 2 2006.257.23:02:54.68#ibcon#about to read 6, iclass 11, count 2 2006.257.23:02:54.68#ibcon#read 6, iclass 11, count 2 2006.257.23:02:54.68#ibcon#end of sib2, iclass 11, count 2 2006.257.23:02:54.68#ibcon#*mode == 0, iclass 11, count 2 2006.257.23:02:54.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.23:02:54.68#ibcon#[27=AT08-04\r\n] 2006.257.23:02:54.68#ibcon#*before write, iclass 11, count 2 2006.257.23:02:54.68#ibcon#enter sib2, iclass 11, count 2 2006.257.23:02:54.68#ibcon#flushed, iclass 11, count 2 2006.257.23:02:54.68#ibcon#about to write, iclass 11, count 2 2006.257.23:02:54.68#ibcon#wrote, iclass 11, count 2 2006.257.23:02:54.68#ibcon#about to read 3, iclass 11, count 2 2006.257.23:02:54.71#ibcon#read 3, iclass 11, count 2 2006.257.23:02:54.71#ibcon#about to read 4, iclass 11, count 2 2006.257.23:02:54.71#ibcon#read 4, iclass 11, count 2 2006.257.23:02:54.71#ibcon#about to read 5, iclass 11, count 2 2006.257.23:02:54.71#ibcon#read 5, iclass 11, count 2 2006.257.23:02:54.71#ibcon#about to read 6, iclass 11, count 2 2006.257.23:02:54.71#ibcon#read 6, iclass 11, count 2 2006.257.23:02:54.71#ibcon#end of sib2, iclass 11, count 2 2006.257.23:02:54.71#ibcon#*after write, iclass 11, count 2 2006.257.23:02:54.71#ibcon#*before return 0, iclass 11, count 2 2006.257.23:02:54.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:54.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:02:54.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.23:02:54.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:02:54.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:54.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:54.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:54.83#ibcon#enter wrdev, iclass 11, count 0 2006.257.23:02:54.83#ibcon#first serial, iclass 11, count 0 2006.257.23:02:54.83#ibcon#enter sib2, iclass 11, count 0 2006.257.23:02:54.83#ibcon#flushed, iclass 11, count 0 2006.257.23:02:54.83#ibcon#about to write, iclass 11, count 0 2006.257.23:02:54.83#ibcon#wrote, iclass 11, count 0 2006.257.23:02:54.83#ibcon#about to read 3, iclass 11, count 0 2006.257.23:02:54.85#ibcon#read 3, iclass 11, count 0 2006.257.23:02:54.85#ibcon#about to read 4, iclass 11, count 0 2006.257.23:02:54.85#ibcon#read 4, iclass 11, count 0 2006.257.23:02:54.85#ibcon#about to read 5, iclass 11, count 0 2006.257.23:02:54.85#ibcon#read 5, iclass 11, count 0 2006.257.23:02:54.85#ibcon#about to read 6, iclass 11, count 0 2006.257.23:02:54.85#ibcon#read 6, iclass 11, count 0 2006.257.23:02:54.85#ibcon#end of sib2, iclass 11, count 0 2006.257.23:02:54.85#ibcon#*mode == 0, iclass 11, count 0 2006.257.23:02:54.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.23:02:54.85#ibcon#[27=USB\r\n] 2006.257.23:02:54.85#ibcon#*before write, iclass 11, count 0 2006.257.23:02:54.85#ibcon#enter sib2, iclass 11, count 0 2006.257.23:02:54.85#ibcon#flushed, iclass 11, count 0 2006.257.23:02:54.85#ibcon#about to write, iclass 11, count 0 2006.257.23:02:54.85#ibcon#wrote, iclass 11, count 0 2006.257.23:02:54.85#ibcon#about to read 3, iclass 11, count 0 2006.257.23:02:54.88#ibcon#read 3, iclass 11, count 0 2006.257.23:02:54.88#ibcon#about to read 4, iclass 11, count 0 2006.257.23:02:54.88#ibcon#read 4, iclass 11, count 0 2006.257.23:02:54.88#ibcon#about to read 5, iclass 11, count 0 2006.257.23:02:54.88#ibcon#read 5, iclass 11, count 0 2006.257.23:02:54.88#ibcon#about to read 6, iclass 11, count 0 2006.257.23:02:54.88#ibcon#read 6, iclass 11, count 0 2006.257.23:02:54.88#ibcon#end of sib2, iclass 11, count 0 2006.257.23:02:54.88#ibcon#*after write, iclass 11, count 0 2006.257.23:02:54.88#ibcon#*before return 0, iclass 11, count 0 2006.257.23:02:54.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:54.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:02:54.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.23:02:54.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.23:02:54.88$vck44/vabw=wide 2006.257.23:02:54.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.23:02:54.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.23:02:54.88#ibcon#ireg 8 cls_cnt 0 2006.257.23:02:54.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:54.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:54.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:54.88#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:02:54.88#ibcon#first serial, iclass 13, count 0 2006.257.23:02:54.88#ibcon#enter sib2, iclass 13, count 0 2006.257.23:02:54.88#ibcon#flushed, iclass 13, count 0 2006.257.23:02:54.88#ibcon#about to write, iclass 13, count 0 2006.257.23:02:54.88#ibcon#wrote, iclass 13, count 0 2006.257.23:02:54.88#ibcon#about to read 3, iclass 13, count 0 2006.257.23:02:54.90#ibcon#read 3, iclass 13, count 0 2006.257.23:02:54.90#ibcon#about to read 4, iclass 13, count 0 2006.257.23:02:54.90#ibcon#read 4, iclass 13, count 0 2006.257.23:02:54.90#ibcon#about to read 5, iclass 13, count 0 2006.257.23:02:54.90#ibcon#read 5, iclass 13, count 0 2006.257.23:02:54.90#ibcon#about to read 6, iclass 13, count 0 2006.257.23:02:54.90#ibcon#read 6, iclass 13, count 0 2006.257.23:02:54.90#ibcon#end of sib2, iclass 13, count 0 2006.257.23:02:54.90#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:02:54.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:02:54.90#ibcon#[25=BW32\r\n] 2006.257.23:02:54.90#ibcon#*before write, iclass 13, count 0 2006.257.23:02:54.90#ibcon#enter sib2, iclass 13, count 0 2006.257.23:02:54.90#ibcon#flushed, iclass 13, count 0 2006.257.23:02:54.90#ibcon#about to write, iclass 13, count 0 2006.257.23:02:54.90#ibcon#wrote, iclass 13, count 0 2006.257.23:02:54.90#ibcon#about to read 3, iclass 13, count 0 2006.257.23:02:54.93#ibcon#read 3, iclass 13, count 0 2006.257.23:02:54.93#ibcon#about to read 4, iclass 13, count 0 2006.257.23:02:54.93#ibcon#read 4, iclass 13, count 0 2006.257.23:02:54.93#ibcon#about to read 5, iclass 13, count 0 2006.257.23:02:54.93#ibcon#read 5, iclass 13, count 0 2006.257.23:02:54.93#ibcon#about to read 6, iclass 13, count 0 2006.257.23:02:54.93#ibcon#read 6, iclass 13, count 0 2006.257.23:02:54.93#ibcon#end of sib2, iclass 13, count 0 2006.257.23:02:54.93#ibcon#*after write, iclass 13, count 0 2006.257.23:02:54.93#ibcon#*before return 0, iclass 13, count 0 2006.257.23:02:54.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:54.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:02:54.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:02:54.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:02:54.93$vck44/vbbw=wide 2006.257.23:02:54.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.23:02:54.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.23:02:54.93#ibcon#ireg 8 cls_cnt 0 2006.257.23:02:54.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:02:55.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:02:55.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:02:55.00#ibcon#enter wrdev, iclass 15, count 0 2006.257.23:02:55.00#ibcon#first serial, iclass 15, count 0 2006.257.23:02:55.00#ibcon#enter sib2, iclass 15, count 0 2006.257.23:02:55.00#ibcon#flushed, iclass 15, count 0 2006.257.23:02:55.00#ibcon#about to write, iclass 15, count 0 2006.257.23:02:55.00#ibcon#wrote, iclass 15, count 0 2006.257.23:02:55.00#ibcon#about to read 3, iclass 15, count 0 2006.257.23:02:55.02#ibcon#read 3, iclass 15, count 0 2006.257.23:02:55.02#ibcon#about to read 4, iclass 15, count 0 2006.257.23:02:55.02#ibcon#read 4, iclass 15, count 0 2006.257.23:02:55.02#ibcon#about to read 5, iclass 15, count 0 2006.257.23:02:55.02#ibcon#read 5, iclass 15, count 0 2006.257.23:02:55.02#ibcon#about to read 6, iclass 15, count 0 2006.257.23:02:55.02#ibcon#read 6, iclass 15, count 0 2006.257.23:02:55.02#ibcon#end of sib2, iclass 15, count 0 2006.257.23:02:55.02#ibcon#*mode == 0, iclass 15, count 0 2006.257.23:02:55.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.23:02:55.02#ibcon#[27=BW32\r\n] 2006.257.23:02:55.02#ibcon#*before write, iclass 15, count 0 2006.257.23:02:55.02#ibcon#enter sib2, iclass 15, count 0 2006.257.23:02:55.02#ibcon#flushed, iclass 15, count 0 2006.257.23:02:55.02#ibcon#about to write, iclass 15, count 0 2006.257.23:02:55.02#ibcon#wrote, iclass 15, count 0 2006.257.23:02:55.02#ibcon#about to read 3, iclass 15, count 0 2006.257.23:02:55.05#ibcon#read 3, iclass 15, count 0 2006.257.23:02:55.05#ibcon#about to read 4, iclass 15, count 0 2006.257.23:02:55.05#ibcon#read 4, iclass 15, count 0 2006.257.23:02:55.05#ibcon#about to read 5, iclass 15, count 0 2006.257.23:02:55.05#ibcon#read 5, iclass 15, count 0 2006.257.23:02:55.05#ibcon#about to read 6, iclass 15, count 0 2006.257.23:02:55.05#ibcon#read 6, iclass 15, count 0 2006.257.23:02:55.05#ibcon#end of sib2, iclass 15, count 0 2006.257.23:02:55.05#ibcon#*after write, iclass 15, count 0 2006.257.23:02:55.05#ibcon#*before return 0, iclass 15, count 0 2006.257.23:02:55.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:02:55.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:02:55.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.23:02:55.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.23:02:55.05$setupk4/ifdk4 2006.257.23:02:55.05$ifdk4/lo= 2006.257.23:02:55.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:02:55.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:02:55.05$ifdk4/patch= 2006.257.23:02:55.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:02:55.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:02:55.05$setupk4/!*+20s 2006.257.23:03:04.09#abcon#<5=/15 1.5 3.4 20.02 831016.0\r\n> 2006.257.23:03:04.11#abcon#{5=INTERFACE CLEAR} 2006.257.23:03:04.17#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:03:09.56$setupk4/"tpicd 2006.257.23:03:09.56$setupk4/echo=off 2006.257.23:03:09.56$setupk4/xlog=off 2006.257.23:03:09.56:!2006.257.23:07:20 2006.257.23:03:13.14#trakl#Source acquired 2006.257.23:03:15.14#flagr#flagr/antenna,acquired 2006.257.23:07:20.00:preob 2006.257.23:07:20.13/onsource/TRACKING 2006.257.23:07:20.13:!2006.257.23:07:30 2006.257.23:07:30.00:"tape 2006.257.23:07:30.00:"st=record 2006.257.23:07:30.00:data_valid=on 2006.257.23:07:30.00:midob 2006.257.23:07:30.13/onsource/TRACKING 2006.257.23:07:30.13/wx/20.17,1016.0,83 2006.257.23:07:30.24/cable/+6.4844E-03 2006.257.23:07:31.33/va/01,08,usb,yes,30,33 2006.257.23:07:31.33/va/02,07,usb,yes,33,33 2006.257.23:07:31.33/va/03,08,usb,yes,29,31 2006.257.23:07:31.33/va/04,07,usb,yes,34,35 2006.257.23:07:31.33/va/05,04,usb,yes,30,31 2006.257.23:07:31.33/va/06,04,usb,yes,34,33 2006.257.23:07:31.33/va/07,04,usb,yes,34,35 2006.257.23:07:31.33/va/08,04,usb,yes,29,35 2006.257.23:07:31.56/valo/01,524.99,yes,locked 2006.257.23:07:31.56/valo/02,534.99,yes,locked 2006.257.23:07:31.56/valo/03,564.99,yes,locked 2006.257.23:07:31.56/valo/04,624.99,yes,locked 2006.257.23:07:31.56/valo/05,734.99,yes,locked 2006.257.23:07:31.56/valo/06,814.99,yes,locked 2006.257.23:07:31.56/valo/07,864.99,yes,locked 2006.257.23:07:31.56/valo/08,884.99,yes,locked 2006.257.23:07:32.65/vb/01,04,usb,yes,30,28 2006.257.23:07:32.65/vb/02,05,usb,yes,28,28 2006.257.23:07:32.65/vb/03,04,usb,yes,29,32 2006.257.23:07:32.65/vb/04,05,usb,yes,29,28 2006.257.23:07:32.65/vb/05,04,usb,yes,26,28 2006.257.23:07:32.65/vb/06,04,usb,yes,30,27 2006.257.23:07:32.65/vb/07,04,usb,yes,30,30 2006.257.23:07:32.65/vb/08,04,usb,yes,28,31 2006.257.23:07:32.89/vblo/01,629.99,yes,locked 2006.257.23:07:32.89/vblo/02,634.99,yes,locked 2006.257.23:07:32.89/vblo/03,649.99,yes,locked 2006.257.23:07:32.89/vblo/04,679.99,yes,locked 2006.257.23:07:32.89/vblo/05,709.99,yes,locked 2006.257.23:07:32.89/vblo/06,719.99,yes,locked 2006.257.23:07:32.89/vblo/07,734.99,yes,locked 2006.257.23:07:32.89/vblo/08,744.99,yes,locked 2006.257.23:07:33.04/vabw/8 2006.257.23:07:33.19/vbbw/8 2006.257.23:07:33.28/xfe/off,on,15.2 2006.257.23:07:33.67/ifatt/23,28,28,28 2006.257.23:07:34.08/fmout-gps/S +4.55E-07 2006.257.23:07:34.12:!2006.257.23:09:10 2006.257.23:09:10.01:data_valid=off 2006.257.23:09:10.01:"et 2006.257.23:09:10.01:!+3s 2006.257.23:09:13.02:"tape 2006.257.23:09:13.02:postob 2006.257.23:09:13.11/cable/+6.4832E-03 2006.257.23:09:13.11/wx/20.24,1016.0,83 2006.257.23:09:14.07/fmout-gps/S +4.54E-07 2006.257.23:09:14.07:scan_name=257-2311,jd0609,60 2006.257.23:09:14.07:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.257.23:09:15.14#flagr#flagr/antenna,new-source 2006.257.23:09:15.14:checkk5 2006.257.23:09:15.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:09:15.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:09:16.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:09:16.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:09:16.83/chk_obsdata//k5ts1/T2572307??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.23:09:17.16/chk_obsdata//k5ts2/T2572307??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.23:09:17.50/chk_obsdata//k5ts3/T2572307??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.23:09:17.83/chk_obsdata//k5ts4/T2572307??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.257.23:09:18.49/k5log//k5ts1_log_newline 2006.257.23:09:19.14/k5log//k5ts2_log_newline 2006.257.23:09:19.82/k5log//k5ts3_log_newline 2006.257.23:09:20.47/k5log//k5ts4_log_newline 2006.257.23:09:20.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:09:20.49:setupk4=1 2006.257.23:09:20.49$setupk4/echo=on 2006.257.23:09:20.49$setupk4/pcalon 2006.257.23:09:20.49$pcalon/"no phase cal control is implemented here 2006.257.23:09:20.49$setupk4/"tpicd=stop 2006.257.23:09:20.49$setupk4/"rec=synch_on 2006.257.23:09:20.49$setupk4/"rec_mode=128 2006.257.23:09:20.49$setupk4/!* 2006.257.23:09:20.49$setupk4/recpk4 2006.257.23:09:20.49$recpk4/recpatch= 2006.257.23:09:20.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:09:20.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:09:20.50$setupk4/vck44 2006.257.23:09:20.50$vck44/valo=1,524.99 2006.257.23:09:20.50#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.23:09:20.50#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.23:09:20.50#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:20.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:09:20.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:09:20.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:09:20.50#ibcon#enter wrdev, iclass 19, count 0 2006.257.23:09:20.50#ibcon#first serial, iclass 19, count 0 2006.257.23:09:20.50#ibcon#enter sib2, iclass 19, count 0 2006.257.23:09:20.50#ibcon#flushed, iclass 19, count 0 2006.257.23:09:20.50#ibcon#about to write, iclass 19, count 0 2006.257.23:09:20.50#ibcon#wrote, iclass 19, count 0 2006.257.23:09:20.50#ibcon#about to read 3, iclass 19, count 0 2006.257.23:09:20.51#ibcon#read 3, iclass 19, count 0 2006.257.23:09:20.51#ibcon#about to read 4, iclass 19, count 0 2006.257.23:09:20.51#ibcon#read 4, iclass 19, count 0 2006.257.23:09:20.51#ibcon#about to read 5, iclass 19, count 0 2006.257.23:09:20.51#ibcon#read 5, iclass 19, count 0 2006.257.23:09:20.51#ibcon#about to read 6, iclass 19, count 0 2006.257.23:09:20.51#ibcon#read 6, iclass 19, count 0 2006.257.23:09:20.51#ibcon#end of sib2, iclass 19, count 0 2006.257.23:09:20.51#ibcon#*mode == 0, iclass 19, count 0 2006.257.23:09:20.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.23:09:20.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:09:20.51#ibcon#*before write, iclass 19, count 0 2006.257.23:09:20.51#ibcon#enter sib2, iclass 19, count 0 2006.257.23:09:20.51#ibcon#flushed, iclass 19, count 0 2006.257.23:09:20.51#ibcon#about to write, iclass 19, count 0 2006.257.23:09:20.51#ibcon#wrote, iclass 19, count 0 2006.257.23:09:20.51#ibcon#about to read 3, iclass 19, count 0 2006.257.23:09:20.56#ibcon#read 3, iclass 19, count 0 2006.257.23:09:20.56#ibcon#about to read 4, iclass 19, count 0 2006.257.23:09:20.56#ibcon#read 4, iclass 19, count 0 2006.257.23:09:20.56#ibcon#about to read 5, iclass 19, count 0 2006.257.23:09:20.56#ibcon#read 5, iclass 19, count 0 2006.257.23:09:20.56#ibcon#about to read 6, iclass 19, count 0 2006.257.23:09:20.56#ibcon#read 6, iclass 19, count 0 2006.257.23:09:20.56#ibcon#end of sib2, iclass 19, count 0 2006.257.23:09:20.56#ibcon#*after write, iclass 19, count 0 2006.257.23:09:20.56#ibcon#*before return 0, iclass 19, count 0 2006.257.23:09:20.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:09:20.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:09:20.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.23:09:20.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.23:09:20.56$vck44/va=1,8 2006.257.23:09:20.56#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.23:09:20.56#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.23:09:20.56#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:20.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:09:20.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:09:20.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:09:20.56#ibcon#enter wrdev, iclass 21, count 2 2006.257.23:09:20.56#ibcon#first serial, iclass 21, count 2 2006.257.23:09:20.56#ibcon#enter sib2, iclass 21, count 2 2006.257.23:09:20.56#ibcon#flushed, iclass 21, count 2 2006.257.23:09:20.56#ibcon#about to write, iclass 21, count 2 2006.257.23:09:20.56#ibcon#wrote, iclass 21, count 2 2006.257.23:09:20.56#ibcon#about to read 3, iclass 21, count 2 2006.257.23:09:20.58#ibcon#read 3, iclass 21, count 2 2006.257.23:09:20.58#ibcon#about to read 4, iclass 21, count 2 2006.257.23:09:20.58#ibcon#read 4, iclass 21, count 2 2006.257.23:09:20.58#ibcon#about to read 5, iclass 21, count 2 2006.257.23:09:20.58#ibcon#read 5, iclass 21, count 2 2006.257.23:09:20.58#ibcon#about to read 6, iclass 21, count 2 2006.257.23:09:20.58#ibcon#read 6, iclass 21, count 2 2006.257.23:09:20.58#ibcon#end of sib2, iclass 21, count 2 2006.257.23:09:20.58#ibcon#*mode == 0, iclass 21, count 2 2006.257.23:09:20.58#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.23:09:20.58#ibcon#[25=AT01-08\r\n] 2006.257.23:09:20.58#ibcon#*before write, iclass 21, count 2 2006.257.23:09:20.58#ibcon#enter sib2, iclass 21, count 2 2006.257.23:09:20.58#ibcon#flushed, iclass 21, count 2 2006.257.23:09:20.58#ibcon#about to write, iclass 21, count 2 2006.257.23:09:20.58#ibcon#wrote, iclass 21, count 2 2006.257.23:09:20.58#ibcon#about to read 3, iclass 21, count 2 2006.257.23:09:20.61#ibcon#read 3, iclass 21, count 2 2006.257.23:09:20.61#ibcon#about to read 4, iclass 21, count 2 2006.257.23:09:20.61#ibcon#read 4, iclass 21, count 2 2006.257.23:09:20.61#ibcon#about to read 5, iclass 21, count 2 2006.257.23:09:20.61#ibcon#read 5, iclass 21, count 2 2006.257.23:09:20.61#ibcon#about to read 6, iclass 21, count 2 2006.257.23:09:20.61#ibcon#read 6, iclass 21, count 2 2006.257.23:09:20.61#ibcon#end of sib2, iclass 21, count 2 2006.257.23:09:20.61#ibcon#*after write, iclass 21, count 2 2006.257.23:09:20.61#ibcon#*before return 0, iclass 21, count 2 2006.257.23:09:20.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:09:20.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:09:20.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.23:09:20.61#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:20.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:09:20.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:09:20.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:09:20.73#ibcon#enter wrdev, iclass 21, count 0 2006.257.23:09:20.73#ibcon#first serial, iclass 21, count 0 2006.257.23:09:20.73#ibcon#enter sib2, iclass 21, count 0 2006.257.23:09:20.73#ibcon#flushed, iclass 21, count 0 2006.257.23:09:20.73#ibcon#about to write, iclass 21, count 0 2006.257.23:09:20.73#ibcon#wrote, iclass 21, count 0 2006.257.23:09:20.73#ibcon#about to read 3, iclass 21, count 0 2006.257.23:09:20.75#ibcon#read 3, iclass 21, count 0 2006.257.23:09:20.75#ibcon#about to read 4, iclass 21, count 0 2006.257.23:09:20.75#ibcon#read 4, iclass 21, count 0 2006.257.23:09:20.75#ibcon#about to read 5, iclass 21, count 0 2006.257.23:09:20.75#ibcon#read 5, iclass 21, count 0 2006.257.23:09:20.75#ibcon#about to read 6, iclass 21, count 0 2006.257.23:09:20.75#ibcon#read 6, iclass 21, count 0 2006.257.23:09:20.75#ibcon#end of sib2, iclass 21, count 0 2006.257.23:09:20.75#ibcon#*mode == 0, iclass 21, count 0 2006.257.23:09:20.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.23:09:20.75#ibcon#[25=USB\r\n] 2006.257.23:09:20.75#ibcon#*before write, iclass 21, count 0 2006.257.23:09:20.75#ibcon#enter sib2, iclass 21, count 0 2006.257.23:09:20.75#ibcon#flushed, iclass 21, count 0 2006.257.23:09:20.75#ibcon#about to write, iclass 21, count 0 2006.257.23:09:20.75#ibcon#wrote, iclass 21, count 0 2006.257.23:09:20.75#ibcon#about to read 3, iclass 21, count 0 2006.257.23:09:20.78#ibcon#read 3, iclass 21, count 0 2006.257.23:09:20.78#ibcon#about to read 4, iclass 21, count 0 2006.257.23:09:20.78#ibcon#read 4, iclass 21, count 0 2006.257.23:09:20.78#ibcon#about to read 5, iclass 21, count 0 2006.257.23:09:20.78#ibcon#read 5, iclass 21, count 0 2006.257.23:09:20.78#ibcon#about to read 6, iclass 21, count 0 2006.257.23:09:20.78#ibcon#read 6, iclass 21, count 0 2006.257.23:09:20.78#ibcon#end of sib2, iclass 21, count 0 2006.257.23:09:20.78#ibcon#*after write, iclass 21, count 0 2006.257.23:09:20.78#ibcon#*before return 0, iclass 21, count 0 2006.257.23:09:20.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:09:20.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:09:20.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.23:09:20.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.23:09:20.78$vck44/valo=2,534.99 2006.257.23:09:20.78#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.23:09:20.78#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.23:09:20.78#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:20.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:20.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:20.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:20.78#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:09:20.78#ibcon#first serial, iclass 23, count 0 2006.257.23:09:20.78#ibcon#enter sib2, iclass 23, count 0 2006.257.23:09:20.78#ibcon#flushed, iclass 23, count 0 2006.257.23:09:20.78#ibcon#about to write, iclass 23, count 0 2006.257.23:09:20.78#ibcon#wrote, iclass 23, count 0 2006.257.23:09:20.78#ibcon#about to read 3, iclass 23, count 0 2006.257.23:09:20.80#ibcon#read 3, iclass 23, count 0 2006.257.23:09:20.80#ibcon#about to read 4, iclass 23, count 0 2006.257.23:09:20.80#ibcon#read 4, iclass 23, count 0 2006.257.23:09:20.80#ibcon#about to read 5, iclass 23, count 0 2006.257.23:09:20.80#ibcon#read 5, iclass 23, count 0 2006.257.23:09:20.80#ibcon#about to read 6, iclass 23, count 0 2006.257.23:09:20.80#ibcon#read 6, iclass 23, count 0 2006.257.23:09:20.80#ibcon#end of sib2, iclass 23, count 0 2006.257.23:09:20.80#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:09:20.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:09:20.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:09:20.80#ibcon#*before write, iclass 23, count 0 2006.257.23:09:20.80#ibcon#enter sib2, iclass 23, count 0 2006.257.23:09:20.80#ibcon#flushed, iclass 23, count 0 2006.257.23:09:20.80#ibcon#about to write, iclass 23, count 0 2006.257.23:09:20.80#ibcon#wrote, iclass 23, count 0 2006.257.23:09:20.80#ibcon#about to read 3, iclass 23, count 0 2006.257.23:09:20.84#ibcon#read 3, iclass 23, count 0 2006.257.23:09:20.84#ibcon#about to read 4, iclass 23, count 0 2006.257.23:09:20.84#ibcon#read 4, iclass 23, count 0 2006.257.23:09:20.84#ibcon#about to read 5, iclass 23, count 0 2006.257.23:09:20.84#ibcon#read 5, iclass 23, count 0 2006.257.23:09:20.84#ibcon#about to read 6, iclass 23, count 0 2006.257.23:09:20.84#ibcon#read 6, iclass 23, count 0 2006.257.23:09:20.84#ibcon#end of sib2, iclass 23, count 0 2006.257.23:09:20.84#ibcon#*after write, iclass 23, count 0 2006.257.23:09:20.84#ibcon#*before return 0, iclass 23, count 0 2006.257.23:09:20.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:20.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:20.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:09:20.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:09:20.84$vck44/va=2,7 2006.257.23:09:20.84#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.23:09:20.84#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.23:09:20.84#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:20.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:20.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:20.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:20.90#ibcon#enter wrdev, iclass 25, count 2 2006.257.23:09:20.90#ibcon#first serial, iclass 25, count 2 2006.257.23:09:20.90#ibcon#enter sib2, iclass 25, count 2 2006.257.23:09:20.90#ibcon#flushed, iclass 25, count 2 2006.257.23:09:20.90#ibcon#about to write, iclass 25, count 2 2006.257.23:09:20.90#ibcon#wrote, iclass 25, count 2 2006.257.23:09:20.90#ibcon#about to read 3, iclass 25, count 2 2006.257.23:09:20.92#ibcon#read 3, iclass 25, count 2 2006.257.23:09:20.92#ibcon#about to read 4, iclass 25, count 2 2006.257.23:09:20.92#ibcon#read 4, iclass 25, count 2 2006.257.23:09:20.92#ibcon#about to read 5, iclass 25, count 2 2006.257.23:09:20.92#ibcon#read 5, iclass 25, count 2 2006.257.23:09:20.92#ibcon#about to read 6, iclass 25, count 2 2006.257.23:09:20.92#ibcon#read 6, iclass 25, count 2 2006.257.23:09:20.92#ibcon#end of sib2, iclass 25, count 2 2006.257.23:09:20.92#ibcon#*mode == 0, iclass 25, count 2 2006.257.23:09:20.92#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.23:09:20.92#ibcon#[25=AT02-07\r\n] 2006.257.23:09:20.92#ibcon#*before write, iclass 25, count 2 2006.257.23:09:20.92#ibcon#enter sib2, iclass 25, count 2 2006.257.23:09:20.92#ibcon#flushed, iclass 25, count 2 2006.257.23:09:20.92#ibcon#about to write, iclass 25, count 2 2006.257.23:09:20.92#ibcon#wrote, iclass 25, count 2 2006.257.23:09:20.92#ibcon#about to read 3, iclass 25, count 2 2006.257.23:09:20.95#ibcon#read 3, iclass 25, count 2 2006.257.23:09:20.95#ibcon#about to read 4, iclass 25, count 2 2006.257.23:09:20.95#ibcon#read 4, iclass 25, count 2 2006.257.23:09:20.95#ibcon#about to read 5, iclass 25, count 2 2006.257.23:09:20.95#ibcon#read 5, iclass 25, count 2 2006.257.23:09:20.95#ibcon#about to read 6, iclass 25, count 2 2006.257.23:09:20.95#ibcon#read 6, iclass 25, count 2 2006.257.23:09:20.95#ibcon#end of sib2, iclass 25, count 2 2006.257.23:09:20.95#ibcon#*after write, iclass 25, count 2 2006.257.23:09:20.95#ibcon#*before return 0, iclass 25, count 2 2006.257.23:09:20.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:20.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:20.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.23:09:20.95#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:20.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:21.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:21.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:21.07#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:09:21.07#ibcon#first serial, iclass 25, count 0 2006.257.23:09:21.07#ibcon#enter sib2, iclass 25, count 0 2006.257.23:09:21.07#ibcon#flushed, iclass 25, count 0 2006.257.23:09:21.07#ibcon#about to write, iclass 25, count 0 2006.257.23:09:21.07#ibcon#wrote, iclass 25, count 0 2006.257.23:09:21.07#ibcon#about to read 3, iclass 25, count 0 2006.257.23:09:21.09#ibcon#read 3, iclass 25, count 0 2006.257.23:09:21.09#ibcon#about to read 4, iclass 25, count 0 2006.257.23:09:21.09#ibcon#read 4, iclass 25, count 0 2006.257.23:09:21.09#ibcon#about to read 5, iclass 25, count 0 2006.257.23:09:21.09#ibcon#read 5, iclass 25, count 0 2006.257.23:09:21.09#ibcon#about to read 6, iclass 25, count 0 2006.257.23:09:21.09#ibcon#read 6, iclass 25, count 0 2006.257.23:09:21.09#ibcon#end of sib2, iclass 25, count 0 2006.257.23:09:21.09#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:09:21.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:09:21.09#ibcon#[25=USB\r\n] 2006.257.23:09:21.09#ibcon#*before write, iclass 25, count 0 2006.257.23:09:21.09#ibcon#enter sib2, iclass 25, count 0 2006.257.23:09:21.09#ibcon#flushed, iclass 25, count 0 2006.257.23:09:21.09#ibcon#about to write, iclass 25, count 0 2006.257.23:09:21.09#ibcon#wrote, iclass 25, count 0 2006.257.23:09:21.09#ibcon#about to read 3, iclass 25, count 0 2006.257.23:09:21.12#ibcon#read 3, iclass 25, count 0 2006.257.23:09:21.12#ibcon#about to read 4, iclass 25, count 0 2006.257.23:09:21.12#ibcon#read 4, iclass 25, count 0 2006.257.23:09:21.12#ibcon#about to read 5, iclass 25, count 0 2006.257.23:09:21.12#ibcon#read 5, iclass 25, count 0 2006.257.23:09:21.12#ibcon#about to read 6, iclass 25, count 0 2006.257.23:09:21.12#ibcon#read 6, iclass 25, count 0 2006.257.23:09:21.12#ibcon#end of sib2, iclass 25, count 0 2006.257.23:09:21.12#ibcon#*after write, iclass 25, count 0 2006.257.23:09:21.12#ibcon#*before return 0, iclass 25, count 0 2006.257.23:09:21.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:21.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:21.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:09:21.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:09:21.12$vck44/valo=3,564.99 2006.257.23:09:21.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.23:09:21.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.23:09:21.12#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:21.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:21.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:21.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:21.12#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:09:21.12#ibcon#first serial, iclass 27, count 0 2006.257.23:09:21.12#ibcon#enter sib2, iclass 27, count 0 2006.257.23:09:21.12#ibcon#flushed, iclass 27, count 0 2006.257.23:09:21.12#ibcon#about to write, iclass 27, count 0 2006.257.23:09:21.12#ibcon#wrote, iclass 27, count 0 2006.257.23:09:21.12#ibcon#about to read 3, iclass 27, count 0 2006.257.23:09:21.14#ibcon#read 3, iclass 27, count 0 2006.257.23:09:21.14#ibcon#about to read 4, iclass 27, count 0 2006.257.23:09:21.14#ibcon#read 4, iclass 27, count 0 2006.257.23:09:21.14#ibcon#about to read 5, iclass 27, count 0 2006.257.23:09:21.14#ibcon#read 5, iclass 27, count 0 2006.257.23:09:21.14#ibcon#about to read 6, iclass 27, count 0 2006.257.23:09:21.14#ibcon#read 6, iclass 27, count 0 2006.257.23:09:21.14#ibcon#end of sib2, iclass 27, count 0 2006.257.23:09:21.14#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:09:21.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:09:21.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:09:21.14#ibcon#*before write, iclass 27, count 0 2006.257.23:09:21.14#ibcon#enter sib2, iclass 27, count 0 2006.257.23:09:21.14#ibcon#flushed, iclass 27, count 0 2006.257.23:09:21.14#ibcon#about to write, iclass 27, count 0 2006.257.23:09:21.14#ibcon#wrote, iclass 27, count 0 2006.257.23:09:21.14#ibcon#about to read 3, iclass 27, count 0 2006.257.23:09:21.18#ibcon#read 3, iclass 27, count 0 2006.257.23:09:21.18#ibcon#about to read 4, iclass 27, count 0 2006.257.23:09:21.18#ibcon#read 4, iclass 27, count 0 2006.257.23:09:21.18#ibcon#about to read 5, iclass 27, count 0 2006.257.23:09:21.18#ibcon#read 5, iclass 27, count 0 2006.257.23:09:21.18#ibcon#about to read 6, iclass 27, count 0 2006.257.23:09:21.18#ibcon#read 6, iclass 27, count 0 2006.257.23:09:21.18#ibcon#end of sib2, iclass 27, count 0 2006.257.23:09:21.18#ibcon#*after write, iclass 27, count 0 2006.257.23:09:21.18#ibcon#*before return 0, iclass 27, count 0 2006.257.23:09:21.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:21.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:21.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:09:21.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:09:21.18$vck44/va=3,8 2006.257.23:09:21.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.23:09:21.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.23:09:21.18#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:21.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:21.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:21.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:21.24#ibcon#enter wrdev, iclass 29, count 2 2006.257.23:09:21.24#ibcon#first serial, iclass 29, count 2 2006.257.23:09:21.24#ibcon#enter sib2, iclass 29, count 2 2006.257.23:09:21.24#ibcon#flushed, iclass 29, count 2 2006.257.23:09:21.24#ibcon#about to write, iclass 29, count 2 2006.257.23:09:21.24#ibcon#wrote, iclass 29, count 2 2006.257.23:09:21.24#ibcon#about to read 3, iclass 29, count 2 2006.257.23:09:21.26#ibcon#read 3, iclass 29, count 2 2006.257.23:09:21.26#ibcon#about to read 4, iclass 29, count 2 2006.257.23:09:21.26#ibcon#read 4, iclass 29, count 2 2006.257.23:09:21.26#ibcon#about to read 5, iclass 29, count 2 2006.257.23:09:21.26#ibcon#read 5, iclass 29, count 2 2006.257.23:09:21.26#ibcon#about to read 6, iclass 29, count 2 2006.257.23:09:21.26#ibcon#read 6, iclass 29, count 2 2006.257.23:09:21.26#ibcon#end of sib2, iclass 29, count 2 2006.257.23:09:21.26#ibcon#*mode == 0, iclass 29, count 2 2006.257.23:09:21.26#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.23:09:21.26#ibcon#[25=AT03-08\r\n] 2006.257.23:09:21.26#ibcon#*before write, iclass 29, count 2 2006.257.23:09:21.26#ibcon#enter sib2, iclass 29, count 2 2006.257.23:09:21.26#ibcon#flushed, iclass 29, count 2 2006.257.23:09:21.26#ibcon#about to write, iclass 29, count 2 2006.257.23:09:21.26#ibcon#wrote, iclass 29, count 2 2006.257.23:09:21.26#ibcon#about to read 3, iclass 29, count 2 2006.257.23:09:21.29#ibcon#read 3, iclass 29, count 2 2006.257.23:09:21.29#ibcon#about to read 4, iclass 29, count 2 2006.257.23:09:21.29#ibcon#read 4, iclass 29, count 2 2006.257.23:09:21.29#ibcon#about to read 5, iclass 29, count 2 2006.257.23:09:21.29#ibcon#read 5, iclass 29, count 2 2006.257.23:09:21.29#ibcon#about to read 6, iclass 29, count 2 2006.257.23:09:21.29#ibcon#read 6, iclass 29, count 2 2006.257.23:09:21.29#ibcon#end of sib2, iclass 29, count 2 2006.257.23:09:21.29#ibcon#*after write, iclass 29, count 2 2006.257.23:09:21.29#ibcon#*before return 0, iclass 29, count 2 2006.257.23:09:21.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:21.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:21.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.23:09:21.29#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:21.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:21.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:21.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:21.41#ibcon#enter wrdev, iclass 29, count 0 2006.257.23:09:21.41#ibcon#first serial, iclass 29, count 0 2006.257.23:09:21.41#ibcon#enter sib2, iclass 29, count 0 2006.257.23:09:21.41#ibcon#flushed, iclass 29, count 0 2006.257.23:09:21.41#ibcon#about to write, iclass 29, count 0 2006.257.23:09:21.41#ibcon#wrote, iclass 29, count 0 2006.257.23:09:21.41#ibcon#about to read 3, iclass 29, count 0 2006.257.23:09:21.43#ibcon#read 3, iclass 29, count 0 2006.257.23:09:21.43#ibcon#about to read 4, iclass 29, count 0 2006.257.23:09:21.43#ibcon#read 4, iclass 29, count 0 2006.257.23:09:21.43#ibcon#about to read 5, iclass 29, count 0 2006.257.23:09:21.43#ibcon#read 5, iclass 29, count 0 2006.257.23:09:21.43#ibcon#about to read 6, iclass 29, count 0 2006.257.23:09:21.43#ibcon#read 6, iclass 29, count 0 2006.257.23:09:21.43#ibcon#end of sib2, iclass 29, count 0 2006.257.23:09:21.43#ibcon#*mode == 0, iclass 29, count 0 2006.257.23:09:21.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.23:09:21.43#ibcon#[25=USB\r\n] 2006.257.23:09:21.43#ibcon#*before write, iclass 29, count 0 2006.257.23:09:21.43#ibcon#enter sib2, iclass 29, count 0 2006.257.23:09:21.43#ibcon#flushed, iclass 29, count 0 2006.257.23:09:21.43#ibcon#about to write, iclass 29, count 0 2006.257.23:09:21.43#ibcon#wrote, iclass 29, count 0 2006.257.23:09:21.43#ibcon#about to read 3, iclass 29, count 0 2006.257.23:09:21.46#ibcon#read 3, iclass 29, count 0 2006.257.23:09:21.46#ibcon#about to read 4, iclass 29, count 0 2006.257.23:09:21.46#ibcon#read 4, iclass 29, count 0 2006.257.23:09:21.46#ibcon#about to read 5, iclass 29, count 0 2006.257.23:09:21.46#ibcon#read 5, iclass 29, count 0 2006.257.23:09:21.46#ibcon#about to read 6, iclass 29, count 0 2006.257.23:09:21.46#ibcon#read 6, iclass 29, count 0 2006.257.23:09:21.46#ibcon#end of sib2, iclass 29, count 0 2006.257.23:09:21.46#ibcon#*after write, iclass 29, count 0 2006.257.23:09:21.46#ibcon#*before return 0, iclass 29, count 0 2006.257.23:09:21.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:21.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:21.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.23:09:21.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.23:09:21.46$vck44/valo=4,624.99 2006.257.23:09:21.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.23:09:21.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.23:09:21.46#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:21.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:21.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:21.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:21.46#ibcon#enter wrdev, iclass 31, count 0 2006.257.23:09:21.46#ibcon#first serial, iclass 31, count 0 2006.257.23:09:21.46#ibcon#enter sib2, iclass 31, count 0 2006.257.23:09:21.46#ibcon#flushed, iclass 31, count 0 2006.257.23:09:21.46#ibcon#about to write, iclass 31, count 0 2006.257.23:09:21.46#ibcon#wrote, iclass 31, count 0 2006.257.23:09:21.46#ibcon#about to read 3, iclass 31, count 0 2006.257.23:09:21.48#ibcon#read 3, iclass 31, count 0 2006.257.23:09:21.48#ibcon#about to read 4, iclass 31, count 0 2006.257.23:09:21.48#ibcon#read 4, iclass 31, count 0 2006.257.23:09:21.48#ibcon#about to read 5, iclass 31, count 0 2006.257.23:09:21.48#ibcon#read 5, iclass 31, count 0 2006.257.23:09:21.48#ibcon#about to read 6, iclass 31, count 0 2006.257.23:09:21.48#ibcon#read 6, iclass 31, count 0 2006.257.23:09:21.48#ibcon#end of sib2, iclass 31, count 0 2006.257.23:09:21.48#ibcon#*mode == 0, iclass 31, count 0 2006.257.23:09:21.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.23:09:21.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:09:21.48#ibcon#*before write, iclass 31, count 0 2006.257.23:09:21.48#ibcon#enter sib2, iclass 31, count 0 2006.257.23:09:21.48#ibcon#flushed, iclass 31, count 0 2006.257.23:09:21.48#ibcon#about to write, iclass 31, count 0 2006.257.23:09:21.48#ibcon#wrote, iclass 31, count 0 2006.257.23:09:21.48#ibcon#about to read 3, iclass 31, count 0 2006.257.23:09:21.52#ibcon#read 3, iclass 31, count 0 2006.257.23:09:21.52#ibcon#about to read 4, iclass 31, count 0 2006.257.23:09:21.52#ibcon#read 4, iclass 31, count 0 2006.257.23:09:21.52#ibcon#about to read 5, iclass 31, count 0 2006.257.23:09:21.52#ibcon#read 5, iclass 31, count 0 2006.257.23:09:21.52#ibcon#about to read 6, iclass 31, count 0 2006.257.23:09:21.52#ibcon#read 6, iclass 31, count 0 2006.257.23:09:21.52#ibcon#end of sib2, iclass 31, count 0 2006.257.23:09:21.52#ibcon#*after write, iclass 31, count 0 2006.257.23:09:21.52#ibcon#*before return 0, iclass 31, count 0 2006.257.23:09:21.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:21.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:21.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.23:09:21.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.23:09:21.52$vck44/va=4,7 2006.257.23:09:21.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.23:09:21.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.23:09:21.52#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:21.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:21.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:21.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:21.58#ibcon#enter wrdev, iclass 33, count 2 2006.257.23:09:21.58#ibcon#first serial, iclass 33, count 2 2006.257.23:09:21.58#ibcon#enter sib2, iclass 33, count 2 2006.257.23:09:21.58#ibcon#flushed, iclass 33, count 2 2006.257.23:09:21.58#ibcon#about to write, iclass 33, count 2 2006.257.23:09:21.58#ibcon#wrote, iclass 33, count 2 2006.257.23:09:21.58#ibcon#about to read 3, iclass 33, count 2 2006.257.23:09:21.60#ibcon#read 3, iclass 33, count 2 2006.257.23:09:21.60#ibcon#about to read 4, iclass 33, count 2 2006.257.23:09:21.60#ibcon#read 4, iclass 33, count 2 2006.257.23:09:21.60#ibcon#about to read 5, iclass 33, count 2 2006.257.23:09:21.60#ibcon#read 5, iclass 33, count 2 2006.257.23:09:21.60#ibcon#about to read 6, iclass 33, count 2 2006.257.23:09:21.60#ibcon#read 6, iclass 33, count 2 2006.257.23:09:21.60#ibcon#end of sib2, iclass 33, count 2 2006.257.23:09:21.60#ibcon#*mode == 0, iclass 33, count 2 2006.257.23:09:21.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.23:09:21.60#ibcon#[25=AT04-07\r\n] 2006.257.23:09:21.60#ibcon#*before write, iclass 33, count 2 2006.257.23:09:21.60#ibcon#enter sib2, iclass 33, count 2 2006.257.23:09:21.60#ibcon#flushed, iclass 33, count 2 2006.257.23:09:21.60#ibcon#about to write, iclass 33, count 2 2006.257.23:09:21.60#ibcon#wrote, iclass 33, count 2 2006.257.23:09:21.60#ibcon#about to read 3, iclass 33, count 2 2006.257.23:09:21.63#ibcon#read 3, iclass 33, count 2 2006.257.23:09:21.63#ibcon#about to read 4, iclass 33, count 2 2006.257.23:09:21.63#ibcon#read 4, iclass 33, count 2 2006.257.23:09:21.63#ibcon#about to read 5, iclass 33, count 2 2006.257.23:09:21.63#ibcon#read 5, iclass 33, count 2 2006.257.23:09:21.63#ibcon#about to read 6, iclass 33, count 2 2006.257.23:09:21.63#ibcon#read 6, iclass 33, count 2 2006.257.23:09:21.63#ibcon#end of sib2, iclass 33, count 2 2006.257.23:09:21.63#ibcon#*after write, iclass 33, count 2 2006.257.23:09:21.63#ibcon#*before return 0, iclass 33, count 2 2006.257.23:09:21.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:21.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:21.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.23:09:21.63#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:21.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:21.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:21.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:21.75#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:09:21.75#ibcon#first serial, iclass 33, count 0 2006.257.23:09:21.75#ibcon#enter sib2, iclass 33, count 0 2006.257.23:09:21.75#ibcon#flushed, iclass 33, count 0 2006.257.23:09:21.75#ibcon#about to write, iclass 33, count 0 2006.257.23:09:21.75#ibcon#wrote, iclass 33, count 0 2006.257.23:09:21.75#ibcon#about to read 3, iclass 33, count 0 2006.257.23:09:21.77#ibcon#read 3, iclass 33, count 0 2006.257.23:09:21.77#ibcon#about to read 4, iclass 33, count 0 2006.257.23:09:21.77#ibcon#read 4, iclass 33, count 0 2006.257.23:09:21.77#ibcon#about to read 5, iclass 33, count 0 2006.257.23:09:21.77#ibcon#read 5, iclass 33, count 0 2006.257.23:09:21.77#ibcon#about to read 6, iclass 33, count 0 2006.257.23:09:21.77#ibcon#read 6, iclass 33, count 0 2006.257.23:09:21.77#ibcon#end of sib2, iclass 33, count 0 2006.257.23:09:21.77#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:09:21.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:09:21.77#ibcon#[25=USB\r\n] 2006.257.23:09:21.77#ibcon#*before write, iclass 33, count 0 2006.257.23:09:21.77#ibcon#enter sib2, iclass 33, count 0 2006.257.23:09:21.77#ibcon#flushed, iclass 33, count 0 2006.257.23:09:21.77#ibcon#about to write, iclass 33, count 0 2006.257.23:09:21.77#ibcon#wrote, iclass 33, count 0 2006.257.23:09:21.77#ibcon#about to read 3, iclass 33, count 0 2006.257.23:09:21.80#ibcon#read 3, iclass 33, count 0 2006.257.23:09:21.80#ibcon#about to read 4, iclass 33, count 0 2006.257.23:09:21.80#ibcon#read 4, iclass 33, count 0 2006.257.23:09:21.80#ibcon#about to read 5, iclass 33, count 0 2006.257.23:09:21.80#ibcon#read 5, iclass 33, count 0 2006.257.23:09:21.80#ibcon#about to read 6, iclass 33, count 0 2006.257.23:09:21.80#ibcon#read 6, iclass 33, count 0 2006.257.23:09:21.80#ibcon#end of sib2, iclass 33, count 0 2006.257.23:09:21.80#ibcon#*after write, iclass 33, count 0 2006.257.23:09:21.80#ibcon#*before return 0, iclass 33, count 0 2006.257.23:09:21.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:21.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:21.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:09:21.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:09:21.80$vck44/valo=5,734.99 2006.257.23:09:21.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.23:09:21.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.23:09:21.80#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:21.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:21.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:21.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:21.80#ibcon#enter wrdev, iclass 35, count 0 2006.257.23:09:21.80#ibcon#first serial, iclass 35, count 0 2006.257.23:09:21.80#ibcon#enter sib2, iclass 35, count 0 2006.257.23:09:21.80#ibcon#flushed, iclass 35, count 0 2006.257.23:09:21.80#ibcon#about to write, iclass 35, count 0 2006.257.23:09:21.80#ibcon#wrote, iclass 35, count 0 2006.257.23:09:21.80#ibcon#about to read 3, iclass 35, count 0 2006.257.23:09:21.82#ibcon#read 3, iclass 35, count 0 2006.257.23:09:21.82#ibcon#about to read 4, iclass 35, count 0 2006.257.23:09:21.82#ibcon#read 4, iclass 35, count 0 2006.257.23:09:21.82#ibcon#about to read 5, iclass 35, count 0 2006.257.23:09:21.82#ibcon#read 5, iclass 35, count 0 2006.257.23:09:21.82#ibcon#about to read 6, iclass 35, count 0 2006.257.23:09:21.82#ibcon#read 6, iclass 35, count 0 2006.257.23:09:21.82#ibcon#end of sib2, iclass 35, count 0 2006.257.23:09:21.82#ibcon#*mode == 0, iclass 35, count 0 2006.257.23:09:21.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.23:09:21.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:09:21.82#ibcon#*before write, iclass 35, count 0 2006.257.23:09:21.82#ibcon#enter sib2, iclass 35, count 0 2006.257.23:09:21.82#ibcon#flushed, iclass 35, count 0 2006.257.23:09:21.82#ibcon#about to write, iclass 35, count 0 2006.257.23:09:21.82#ibcon#wrote, iclass 35, count 0 2006.257.23:09:21.82#ibcon#about to read 3, iclass 35, count 0 2006.257.23:09:21.86#ibcon#read 3, iclass 35, count 0 2006.257.23:09:21.86#ibcon#about to read 4, iclass 35, count 0 2006.257.23:09:21.86#ibcon#read 4, iclass 35, count 0 2006.257.23:09:21.86#ibcon#about to read 5, iclass 35, count 0 2006.257.23:09:21.86#ibcon#read 5, iclass 35, count 0 2006.257.23:09:21.86#ibcon#about to read 6, iclass 35, count 0 2006.257.23:09:21.86#ibcon#read 6, iclass 35, count 0 2006.257.23:09:21.86#ibcon#end of sib2, iclass 35, count 0 2006.257.23:09:21.86#ibcon#*after write, iclass 35, count 0 2006.257.23:09:21.86#ibcon#*before return 0, iclass 35, count 0 2006.257.23:09:21.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:21.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:21.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.23:09:21.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.23:09:21.86$vck44/va=5,4 2006.257.23:09:21.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.23:09:21.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.23:09:21.86#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:21.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:21.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:21.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:21.92#ibcon#enter wrdev, iclass 37, count 2 2006.257.23:09:21.92#ibcon#first serial, iclass 37, count 2 2006.257.23:09:21.92#ibcon#enter sib2, iclass 37, count 2 2006.257.23:09:21.92#ibcon#flushed, iclass 37, count 2 2006.257.23:09:21.92#ibcon#about to write, iclass 37, count 2 2006.257.23:09:21.92#ibcon#wrote, iclass 37, count 2 2006.257.23:09:21.92#ibcon#about to read 3, iclass 37, count 2 2006.257.23:09:21.94#ibcon#read 3, iclass 37, count 2 2006.257.23:09:21.94#ibcon#about to read 4, iclass 37, count 2 2006.257.23:09:21.94#ibcon#read 4, iclass 37, count 2 2006.257.23:09:21.94#ibcon#about to read 5, iclass 37, count 2 2006.257.23:09:21.94#ibcon#read 5, iclass 37, count 2 2006.257.23:09:21.94#ibcon#about to read 6, iclass 37, count 2 2006.257.23:09:21.94#ibcon#read 6, iclass 37, count 2 2006.257.23:09:21.94#ibcon#end of sib2, iclass 37, count 2 2006.257.23:09:21.94#ibcon#*mode == 0, iclass 37, count 2 2006.257.23:09:21.94#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.23:09:21.94#ibcon#[25=AT05-04\r\n] 2006.257.23:09:21.94#ibcon#*before write, iclass 37, count 2 2006.257.23:09:21.94#ibcon#enter sib2, iclass 37, count 2 2006.257.23:09:21.94#ibcon#flushed, iclass 37, count 2 2006.257.23:09:21.94#ibcon#about to write, iclass 37, count 2 2006.257.23:09:21.94#ibcon#wrote, iclass 37, count 2 2006.257.23:09:21.94#ibcon#about to read 3, iclass 37, count 2 2006.257.23:09:21.97#ibcon#read 3, iclass 37, count 2 2006.257.23:09:21.97#ibcon#about to read 4, iclass 37, count 2 2006.257.23:09:21.97#ibcon#read 4, iclass 37, count 2 2006.257.23:09:21.97#ibcon#about to read 5, iclass 37, count 2 2006.257.23:09:21.97#ibcon#read 5, iclass 37, count 2 2006.257.23:09:21.97#ibcon#about to read 6, iclass 37, count 2 2006.257.23:09:21.97#ibcon#read 6, iclass 37, count 2 2006.257.23:09:21.97#ibcon#end of sib2, iclass 37, count 2 2006.257.23:09:21.97#ibcon#*after write, iclass 37, count 2 2006.257.23:09:21.97#ibcon#*before return 0, iclass 37, count 2 2006.257.23:09:21.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:21.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:21.97#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.23:09:21.97#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:21.97#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:22.09#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:22.09#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:22.09#ibcon#enter wrdev, iclass 37, count 0 2006.257.23:09:22.09#ibcon#first serial, iclass 37, count 0 2006.257.23:09:22.09#ibcon#enter sib2, iclass 37, count 0 2006.257.23:09:22.09#ibcon#flushed, iclass 37, count 0 2006.257.23:09:22.09#ibcon#about to write, iclass 37, count 0 2006.257.23:09:22.09#ibcon#wrote, iclass 37, count 0 2006.257.23:09:22.09#ibcon#about to read 3, iclass 37, count 0 2006.257.23:09:22.11#ibcon#read 3, iclass 37, count 0 2006.257.23:09:22.11#ibcon#about to read 4, iclass 37, count 0 2006.257.23:09:22.11#ibcon#read 4, iclass 37, count 0 2006.257.23:09:22.11#ibcon#about to read 5, iclass 37, count 0 2006.257.23:09:22.11#ibcon#read 5, iclass 37, count 0 2006.257.23:09:22.11#ibcon#about to read 6, iclass 37, count 0 2006.257.23:09:22.11#ibcon#read 6, iclass 37, count 0 2006.257.23:09:22.11#ibcon#end of sib2, iclass 37, count 0 2006.257.23:09:22.11#ibcon#*mode == 0, iclass 37, count 0 2006.257.23:09:22.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.23:09:22.11#ibcon#[25=USB\r\n] 2006.257.23:09:22.11#ibcon#*before write, iclass 37, count 0 2006.257.23:09:22.11#ibcon#enter sib2, iclass 37, count 0 2006.257.23:09:22.11#ibcon#flushed, iclass 37, count 0 2006.257.23:09:22.11#ibcon#about to write, iclass 37, count 0 2006.257.23:09:22.11#ibcon#wrote, iclass 37, count 0 2006.257.23:09:22.11#ibcon#about to read 3, iclass 37, count 0 2006.257.23:09:22.14#ibcon#read 3, iclass 37, count 0 2006.257.23:09:22.14#ibcon#about to read 4, iclass 37, count 0 2006.257.23:09:22.14#ibcon#read 4, iclass 37, count 0 2006.257.23:09:22.14#ibcon#about to read 5, iclass 37, count 0 2006.257.23:09:22.14#ibcon#read 5, iclass 37, count 0 2006.257.23:09:22.14#ibcon#about to read 6, iclass 37, count 0 2006.257.23:09:22.14#ibcon#read 6, iclass 37, count 0 2006.257.23:09:22.14#ibcon#end of sib2, iclass 37, count 0 2006.257.23:09:22.14#ibcon#*after write, iclass 37, count 0 2006.257.23:09:22.14#ibcon#*before return 0, iclass 37, count 0 2006.257.23:09:22.14#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:22.14#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:22.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.23:09:22.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.23:09:22.14$vck44/valo=6,814.99 2006.257.23:09:22.14#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.23:09:22.14#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.23:09:22.14#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:22.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:22.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:22.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:22.14#ibcon#enter wrdev, iclass 39, count 0 2006.257.23:09:22.14#ibcon#first serial, iclass 39, count 0 2006.257.23:09:22.14#ibcon#enter sib2, iclass 39, count 0 2006.257.23:09:22.14#ibcon#flushed, iclass 39, count 0 2006.257.23:09:22.14#ibcon#about to write, iclass 39, count 0 2006.257.23:09:22.14#ibcon#wrote, iclass 39, count 0 2006.257.23:09:22.14#ibcon#about to read 3, iclass 39, count 0 2006.257.23:09:22.16#ibcon#read 3, iclass 39, count 0 2006.257.23:09:22.16#ibcon#about to read 4, iclass 39, count 0 2006.257.23:09:22.16#ibcon#read 4, iclass 39, count 0 2006.257.23:09:22.16#ibcon#about to read 5, iclass 39, count 0 2006.257.23:09:22.16#ibcon#read 5, iclass 39, count 0 2006.257.23:09:22.16#ibcon#about to read 6, iclass 39, count 0 2006.257.23:09:22.16#ibcon#read 6, iclass 39, count 0 2006.257.23:09:22.16#ibcon#end of sib2, iclass 39, count 0 2006.257.23:09:22.16#ibcon#*mode == 0, iclass 39, count 0 2006.257.23:09:22.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.23:09:22.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:09:22.16#ibcon#*before write, iclass 39, count 0 2006.257.23:09:22.16#ibcon#enter sib2, iclass 39, count 0 2006.257.23:09:22.16#ibcon#flushed, iclass 39, count 0 2006.257.23:09:22.16#ibcon#about to write, iclass 39, count 0 2006.257.23:09:22.16#ibcon#wrote, iclass 39, count 0 2006.257.23:09:22.16#ibcon#about to read 3, iclass 39, count 0 2006.257.23:09:22.20#ibcon#read 3, iclass 39, count 0 2006.257.23:09:22.20#ibcon#about to read 4, iclass 39, count 0 2006.257.23:09:22.20#ibcon#read 4, iclass 39, count 0 2006.257.23:09:22.20#ibcon#about to read 5, iclass 39, count 0 2006.257.23:09:22.20#ibcon#read 5, iclass 39, count 0 2006.257.23:09:22.20#ibcon#about to read 6, iclass 39, count 0 2006.257.23:09:22.20#ibcon#read 6, iclass 39, count 0 2006.257.23:09:22.20#ibcon#end of sib2, iclass 39, count 0 2006.257.23:09:22.20#ibcon#*after write, iclass 39, count 0 2006.257.23:09:22.20#ibcon#*before return 0, iclass 39, count 0 2006.257.23:09:22.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:22.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:22.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.23:09:22.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.23:09:22.20$vck44/va=6,4 2006.257.23:09:22.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.23:09:22.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.23:09:22.20#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:22.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:22.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:22.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:22.26#ibcon#enter wrdev, iclass 3, count 2 2006.257.23:09:22.26#ibcon#first serial, iclass 3, count 2 2006.257.23:09:22.26#ibcon#enter sib2, iclass 3, count 2 2006.257.23:09:22.26#ibcon#flushed, iclass 3, count 2 2006.257.23:09:22.26#ibcon#about to write, iclass 3, count 2 2006.257.23:09:22.26#ibcon#wrote, iclass 3, count 2 2006.257.23:09:22.26#ibcon#about to read 3, iclass 3, count 2 2006.257.23:09:22.28#ibcon#read 3, iclass 3, count 2 2006.257.23:09:22.28#ibcon#about to read 4, iclass 3, count 2 2006.257.23:09:22.28#ibcon#read 4, iclass 3, count 2 2006.257.23:09:22.28#ibcon#about to read 5, iclass 3, count 2 2006.257.23:09:22.28#ibcon#read 5, iclass 3, count 2 2006.257.23:09:22.28#ibcon#about to read 6, iclass 3, count 2 2006.257.23:09:22.28#ibcon#read 6, iclass 3, count 2 2006.257.23:09:22.28#ibcon#end of sib2, iclass 3, count 2 2006.257.23:09:22.28#ibcon#*mode == 0, iclass 3, count 2 2006.257.23:09:22.28#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.23:09:22.28#ibcon#[25=AT06-04\r\n] 2006.257.23:09:22.28#ibcon#*before write, iclass 3, count 2 2006.257.23:09:22.28#ibcon#enter sib2, iclass 3, count 2 2006.257.23:09:22.28#ibcon#flushed, iclass 3, count 2 2006.257.23:09:22.28#ibcon#about to write, iclass 3, count 2 2006.257.23:09:22.28#ibcon#wrote, iclass 3, count 2 2006.257.23:09:22.28#ibcon#about to read 3, iclass 3, count 2 2006.257.23:09:22.31#ibcon#read 3, iclass 3, count 2 2006.257.23:09:22.31#ibcon#about to read 4, iclass 3, count 2 2006.257.23:09:22.31#ibcon#read 4, iclass 3, count 2 2006.257.23:09:22.31#ibcon#about to read 5, iclass 3, count 2 2006.257.23:09:22.31#ibcon#read 5, iclass 3, count 2 2006.257.23:09:22.31#ibcon#about to read 6, iclass 3, count 2 2006.257.23:09:22.31#ibcon#read 6, iclass 3, count 2 2006.257.23:09:22.31#ibcon#end of sib2, iclass 3, count 2 2006.257.23:09:22.31#ibcon#*after write, iclass 3, count 2 2006.257.23:09:22.31#ibcon#*before return 0, iclass 3, count 2 2006.257.23:09:22.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:22.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:22.31#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.23:09:22.31#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:22.31#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:22.43#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:22.43#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:22.43#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:09:22.43#ibcon#first serial, iclass 3, count 0 2006.257.23:09:22.43#ibcon#enter sib2, iclass 3, count 0 2006.257.23:09:22.43#ibcon#flushed, iclass 3, count 0 2006.257.23:09:22.43#ibcon#about to write, iclass 3, count 0 2006.257.23:09:22.43#ibcon#wrote, iclass 3, count 0 2006.257.23:09:22.43#ibcon#about to read 3, iclass 3, count 0 2006.257.23:09:22.45#ibcon#read 3, iclass 3, count 0 2006.257.23:09:22.45#ibcon#about to read 4, iclass 3, count 0 2006.257.23:09:22.45#ibcon#read 4, iclass 3, count 0 2006.257.23:09:22.45#ibcon#about to read 5, iclass 3, count 0 2006.257.23:09:22.45#ibcon#read 5, iclass 3, count 0 2006.257.23:09:22.45#ibcon#about to read 6, iclass 3, count 0 2006.257.23:09:22.45#ibcon#read 6, iclass 3, count 0 2006.257.23:09:22.45#ibcon#end of sib2, iclass 3, count 0 2006.257.23:09:22.45#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:09:22.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:09:22.45#ibcon#[25=USB\r\n] 2006.257.23:09:22.45#ibcon#*before write, iclass 3, count 0 2006.257.23:09:22.45#ibcon#enter sib2, iclass 3, count 0 2006.257.23:09:22.45#ibcon#flushed, iclass 3, count 0 2006.257.23:09:22.45#ibcon#about to write, iclass 3, count 0 2006.257.23:09:22.45#ibcon#wrote, iclass 3, count 0 2006.257.23:09:22.45#ibcon#about to read 3, iclass 3, count 0 2006.257.23:09:22.48#ibcon#read 3, iclass 3, count 0 2006.257.23:09:22.48#ibcon#about to read 4, iclass 3, count 0 2006.257.23:09:22.48#ibcon#read 4, iclass 3, count 0 2006.257.23:09:22.48#ibcon#about to read 5, iclass 3, count 0 2006.257.23:09:22.48#ibcon#read 5, iclass 3, count 0 2006.257.23:09:22.48#ibcon#about to read 6, iclass 3, count 0 2006.257.23:09:22.48#ibcon#read 6, iclass 3, count 0 2006.257.23:09:22.48#ibcon#end of sib2, iclass 3, count 0 2006.257.23:09:22.48#ibcon#*after write, iclass 3, count 0 2006.257.23:09:22.48#ibcon#*before return 0, iclass 3, count 0 2006.257.23:09:22.48#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:22.48#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:22.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:09:22.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:09:22.48$vck44/valo=7,864.99 2006.257.23:09:22.48#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.23:09:22.48#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.23:09:22.48#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:22.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:22.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:22.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:22.48#ibcon#enter wrdev, iclass 5, count 0 2006.257.23:09:22.48#ibcon#first serial, iclass 5, count 0 2006.257.23:09:22.48#ibcon#enter sib2, iclass 5, count 0 2006.257.23:09:22.48#ibcon#flushed, iclass 5, count 0 2006.257.23:09:22.48#ibcon#about to write, iclass 5, count 0 2006.257.23:09:22.48#ibcon#wrote, iclass 5, count 0 2006.257.23:09:22.48#ibcon#about to read 3, iclass 5, count 0 2006.257.23:09:22.50#ibcon#read 3, iclass 5, count 0 2006.257.23:09:22.50#ibcon#about to read 4, iclass 5, count 0 2006.257.23:09:22.50#ibcon#read 4, iclass 5, count 0 2006.257.23:09:22.50#ibcon#about to read 5, iclass 5, count 0 2006.257.23:09:22.50#ibcon#read 5, iclass 5, count 0 2006.257.23:09:22.50#ibcon#about to read 6, iclass 5, count 0 2006.257.23:09:22.50#ibcon#read 6, iclass 5, count 0 2006.257.23:09:22.50#ibcon#end of sib2, iclass 5, count 0 2006.257.23:09:22.50#ibcon#*mode == 0, iclass 5, count 0 2006.257.23:09:22.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.23:09:22.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:09:22.50#ibcon#*before write, iclass 5, count 0 2006.257.23:09:22.50#ibcon#enter sib2, iclass 5, count 0 2006.257.23:09:22.50#ibcon#flushed, iclass 5, count 0 2006.257.23:09:22.50#ibcon#about to write, iclass 5, count 0 2006.257.23:09:22.50#ibcon#wrote, iclass 5, count 0 2006.257.23:09:22.50#ibcon#about to read 3, iclass 5, count 0 2006.257.23:09:22.54#ibcon#read 3, iclass 5, count 0 2006.257.23:09:22.54#ibcon#about to read 4, iclass 5, count 0 2006.257.23:09:22.54#ibcon#read 4, iclass 5, count 0 2006.257.23:09:22.54#ibcon#about to read 5, iclass 5, count 0 2006.257.23:09:22.54#ibcon#read 5, iclass 5, count 0 2006.257.23:09:22.54#ibcon#about to read 6, iclass 5, count 0 2006.257.23:09:22.54#ibcon#read 6, iclass 5, count 0 2006.257.23:09:22.54#ibcon#end of sib2, iclass 5, count 0 2006.257.23:09:22.54#ibcon#*after write, iclass 5, count 0 2006.257.23:09:22.54#ibcon#*before return 0, iclass 5, count 0 2006.257.23:09:22.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:22.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:22.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.23:09:22.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.23:09:22.54$vck44/va=7,4 2006.257.23:09:22.54#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.23:09:22.54#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.23:09:22.54#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:22.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:22.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:22.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:22.60#ibcon#enter wrdev, iclass 7, count 2 2006.257.23:09:22.60#ibcon#first serial, iclass 7, count 2 2006.257.23:09:22.60#ibcon#enter sib2, iclass 7, count 2 2006.257.23:09:22.60#ibcon#flushed, iclass 7, count 2 2006.257.23:09:22.60#ibcon#about to write, iclass 7, count 2 2006.257.23:09:22.60#ibcon#wrote, iclass 7, count 2 2006.257.23:09:22.60#ibcon#about to read 3, iclass 7, count 2 2006.257.23:09:22.62#ibcon#read 3, iclass 7, count 2 2006.257.23:09:22.62#ibcon#about to read 4, iclass 7, count 2 2006.257.23:09:22.62#ibcon#read 4, iclass 7, count 2 2006.257.23:09:22.62#ibcon#about to read 5, iclass 7, count 2 2006.257.23:09:22.62#ibcon#read 5, iclass 7, count 2 2006.257.23:09:22.62#ibcon#about to read 6, iclass 7, count 2 2006.257.23:09:22.62#ibcon#read 6, iclass 7, count 2 2006.257.23:09:22.62#ibcon#end of sib2, iclass 7, count 2 2006.257.23:09:22.62#ibcon#*mode == 0, iclass 7, count 2 2006.257.23:09:22.62#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.23:09:22.62#ibcon#[25=AT07-04\r\n] 2006.257.23:09:22.62#ibcon#*before write, iclass 7, count 2 2006.257.23:09:22.62#ibcon#enter sib2, iclass 7, count 2 2006.257.23:09:22.62#ibcon#flushed, iclass 7, count 2 2006.257.23:09:22.62#ibcon#about to write, iclass 7, count 2 2006.257.23:09:22.62#ibcon#wrote, iclass 7, count 2 2006.257.23:09:22.62#ibcon#about to read 3, iclass 7, count 2 2006.257.23:09:22.65#ibcon#read 3, iclass 7, count 2 2006.257.23:09:22.65#ibcon#about to read 4, iclass 7, count 2 2006.257.23:09:22.65#ibcon#read 4, iclass 7, count 2 2006.257.23:09:22.65#ibcon#about to read 5, iclass 7, count 2 2006.257.23:09:22.65#ibcon#read 5, iclass 7, count 2 2006.257.23:09:22.65#ibcon#about to read 6, iclass 7, count 2 2006.257.23:09:22.65#ibcon#read 6, iclass 7, count 2 2006.257.23:09:22.65#ibcon#end of sib2, iclass 7, count 2 2006.257.23:09:22.65#ibcon#*after write, iclass 7, count 2 2006.257.23:09:22.65#ibcon#*before return 0, iclass 7, count 2 2006.257.23:09:22.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:22.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:22.65#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.23:09:22.65#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:22.65#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:22.77#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:22.77#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:22.77#ibcon#enter wrdev, iclass 7, count 0 2006.257.23:09:22.77#ibcon#first serial, iclass 7, count 0 2006.257.23:09:22.77#ibcon#enter sib2, iclass 7, count 0 2006.257.23:09:22.77#ibcon#flushed, iclass 7, count 0 2006.257.23:09:22.77#ibcon#about to write, iclass 7, count 0 2006.257.23:09:22.77#ibcon#wrote, iclass 7, count 0 2006.257.23:09:22.77#ibcon#about to read 3, iclass 7, count 0 2006.257.23:09:22.79#ibcon#read 3, iclass 7, count 0 2006.257.23:09:22.79#ibcon#about to read 4, iclass 7, count 0 2006.257.23:09:22.79#ibcon#read 4, iclass 7, count 0 2006.257.23:09:22.79#ibcon#about to read 5, iclass 7, count 0 2006.257.23:09:22.79#ibcon#read 5, iclass 7, count 0 2006.257.23:09:22.79#ibcon#about to read 6, iclass 7, count 0 2006.257.23:09:22.79#ibcon#read 6, iclass 7, count 0 2006.257.23:09:22.79#ibcon#end of sib2, iclass 7, count 0 2006.257.23:09:22.79#ibcon#*mode == 0, iclass 7, count 0 2006.257.23:09:22.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.23:09:22.79#ibcon#[25=USB\r\n] 2006.257.23:09:22.79#ibcon#*before write, iclass 7, count 0 2006.257.23:09:22.79#ibcon#enter sib2, iclass 7, count 0 2006.257.23:09:22.79#ibcon#flushed, iclass 7, count 0 2006.257.23:09:22.79#ibcon#about to write, iclass 7, count 0 2006.257.23:09:22.79#ibcon#wrote, iclass 7, count 0 2006.257.23:09:22.79#ibcon#about to read 3, iclass 7, count 0 2006.257.23:09:22.82#ibcon#read 3, iclass 7, count 0 2006.257.23:09:22.82#ibcon#about to read 4, iclass 7, count 0 2006.257.23:09:22.82#ibcon#read 4, iclass 7, count 0 2006.257.23:09:22.82#ibcon#about to read 5, iclass 7, count 0 2006.257.23:09:22.82#ibcon#read 5, iclass 7, count 0 2006.257.23:09:22.82#ibcon#about to read 6, iclass 7, count 0 2006.257.23:09:22.82#ibcon#read 6, iclass 7, count 0 2006.257.23:09:22.82#ibcon#end of sib2, iclass 7, count 0 2006.257.23:09:22.82#ibcon#*after write, iclass 7, count 0 2006.257.23:09:22.82#ibcon#*before return 0, iclass 7, count 0 2006.257.23:09:22.82#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:22.82#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:22.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.23:09:22.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.23:09:22.82$vck44/valo=8,884.99 2006.257.23:09:22.82#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.23:09:22.82#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.23:09:22.82#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:22.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:22.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:22.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:22.82#ibcon#enter wrdev, iclass 11, count 0 2006.257.23:09:22.82#ibcon#first serial, iclass 11, count 0 2006.257.23:09:22.82#ibcon#enter sib2, iclass 11, count 0 2006.257.23:09:22.82#ibcon#flushed, iclass 11, count 0 2006.257.23:09:22.82#ibcon#about to write, iclass 11, count 0 2006.257.23:09:22.82#ibcon#wrote, iclass 11, count 0 2006.257.23:09:22.82#ibcon#about to read 3, iclass 11, count 0 2006.257.23:09:22.84#ibcon#read 3, iclass 11, count 0 2006.257.23:09:22.84#ibcon#about to read 4, iclass 11, count 0 2006.257.23:09:22.84#ibcon#read 4, iclass 11, count 0 2006.257.23:09:22.84#ibcon#about to read 5, iclass 11, count 0 2006.257.23:09:22.84#ibcon#read 5, iclass 11, count 0 2006.257.23:09:22.84#ibcon#about to read 6, iclass 11, count 0 2006.257.23:09:22.84#ibcon#read 6, iclass 11, count 0 2006.257.23:09:22.84#ibcon#end of sib2, iclass 11, count 0 2006.257.23:09:22.84#ibcon#*mode == 0, iclass 11, count 0 2006.257.23:09:22.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.23:09:22.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:09:22.84#ibcon#*before write, iclass 11, count 0 2006.257.23:09:22.84#ibcon#enter sib2, iclass 11, count 0 2006.257.23:09:22.84#ibcon#flushed, iclass 11, count 0 2006.257.23:09:22.84#ibcon#about to write, iclass 11, count 0 2006.257.23:09:22.84#ibcon#wrote, iclass 11, count 0 2006.257.23:09:22.84#ibcon#about to read 3, iclass 11, count 0 2006.257.23:09:22.88#ibcon#read 3, iclass 11, count 0 2006.257.23:09:22.88#ibcon#about to read 4, iclass 11, count 0 2006.257.23:09:22.88#ibcon#read 4, iclass 11, count 0 2006.257.23:09:22.88#ibcon#about to read 5, iclass 11, count 0 2006.257.23:09:22.88#ibcon#read 5, iclass 11, count 0 2006.257.23:09:22.88#ibcon#about to read 6, iclass 11, count 0 2006.257.23:09:22.88#ibcon#read 6, iclass 11, count 0 2006.257.23:09:22.88#ibcon#end of sib2, iclass 11, count 0 2006.257.23:09:22.88#ibcon#*after write, iclass 11, count 0 2006.257.23:09:22.88#ibcon#*before return 0, iclass 11, count 0 2006.257.23:09:22.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:22.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:22.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.23:09:22.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.23:09:22.88$vck44/va=8,4 2006.257.23:09:22.88#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.23:09:22.88#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.23:09:22.88#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:22.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:22.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:22.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:22.94#ibcon#enter wrdev, iclass 13, count 2 2006.257.23:09:22.94#ibcon#first serial, iclass 13, count 2 2006.257.23:09:22.94#ibcon#enter sib2, iclass 13, count 2 2006.257.23:09:22.94#ibcon#flushed, iclass 13, count 2 2006.257.23:09:22.94#ibcon#about to write, iclass 13, count 2 2006.257.23:09:22.94#ibcon#wrote, iclass 13, count 2 2006.257.23:09:22.94#ibcon#about to read 3, iclass 13, count 2 2006.257.23:09:22.96#ibcon#read 3, iclass 13, count 2 2006.257.23:09:22.96#ibcon#about to read 4, iclass 13, count 2 2006.257.23:09:22.96#ibcon#read 4, iclass 13, count 2 2006.257.23:09:22.96#ibcon#about to read 5, iclass 13, count 2 2006.257.23:09:22.96#ibcon#read 5, iclass 13, count 2 2006.257.23:09:22.96#ibcon#about to read 6, iclass 13, count 2 2006.257.23:09:22.96#ibcon#read 6, iclass 13, count 2 2006.257.23:09:22.96#ibcon#end of sib2, iclass 13, count 2 2006.257.23:09:22.96#ibcon#*mode == 0, iclass 13, count 2 2006.257.23:09:22.96#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.23:09:22.96#ibcon#[25=AT08-04\r\n] 2006.257.23:09:22.96#ibcon#*before write, iclass 13, count 2 2006.257.23:09:22.96#ibcon#enter sib2, iclass 13, count 2 2006.257.23:09:22.96#ibcon#flushed, iclass 13, count 2 2006.257.23:09:22.96#ibcon#about to write, iclass 13, count 2 2006.257.23:09:22.96#ibcon#wrote, iclass 13, count 2 2006.257.23:09:22.96#ibcon#about to read 3, iclass 13, count 2 2006.257.23:09:22.99#ibcon#read 3, iclass 13, count 2 2006.257.23:09:22.99#ibcon#about to read 4, iclass 13, count 2 2006.257.23:09:22.99#ibcon#read 4, iclass 13, count 2 2006.257.23:09:22.99#ibcon#about to read 5, iclass 13, count 2 2006.257.23:09:22.99#ibcon#read 5, iclass 13, count 2 2006.257.23:09:22.99#ibcon#about to read 6, iclass 13, count 2 2006.257.23:09:22.99#ibcon#read 6, iclass 13, count 2 2006.257.23:09:22.99#ibcon#end of sib2, iclass 13, count 2 2006.257.23:09:22.99#ibcon#*after write, iclass 13, count 2 2006.257.23:09:22.99#ibcon#*before return 0, iclass 13, count 2 2006.257.23:09:22.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:22.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:22.99#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.23:09:22.99#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:22.99#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:23.11#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:23.11#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:23.11#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:09:23.11#ibcon#first serial, iclass 13, count 0 2006.257.23:09:23.11#ibcon#enter sib2, iclass 13, count 0 2006.257.23:09:23.11#ibcon#flushed, iclass 13, count 0 2006.257.23:09:23.11#ibcon#about to write, iclass 13, count 0 2006.257.23:09:23.11#ibcon#wrote, iclass 13, count 0 2006.257.23:09:23.11#ibcon#about to read 3, iclass 13, count 0 2006.257.23:09:23.13#ibcon#read 3, iclass 13, count 0 2006.257.23:09:23.13#ibcon#about to read 4, iclass 13, count 0 2006.257.23:09:23.13#ibcon#read 4, iclass 13, count 0 2006.257.23:09:23.13#ibcon#about to read 5, iclass 13, count 0 2006.257.23:09:23.13#ibcon#read 5, iclass 13, count 0 2006.257.23:09:23.13#ibcon#about to read 6, iclass 13, count 0 2006.257.23:09:23.13#ibcon#read 6, iclass 13, count 0 2006.257.23:09:23.13#ibcon#end of sib2, iclass 13, count 0 2006.257.23:09:23.13#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:09:23.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:09:23.13#ibcon#[25=USB\r\n] 2006.257.23:09:23.13#ibcon#*before write, iclass 13, count 0 2006.257.23:09:23.13#ibcon#enter sib2, iclass 13, count 0 2006.257.23:09:23.13#ibcon#flushed, iclass 13, count 0 2006.257.23:09:23.13#ibcon#about to write, iclass 13, count 0 2006.257.23:09:23.13#ibcon#wrote, iclass 13, count 0 2006.257.23:09:23.13#ibcon#about to read 3, iclass 13, count 0 2006.257.23:09:23.16#ibcon#read 3, iclass 13, count 0 2006.257.23:09:23.16#ibcon#about to read 4, iclass 13, count 0 2006.257.23:09:23.16#ibcon#read 4, iclass 13, count 0 2006.257.23:09:23.16#ibcon#about to read 5, iclass 13, count 0 2006.257.23:09:23.16#ibcon#read 5, iclass 13, count 0 2006.257.23:09:23.16#ibcon#about to read 6, iclass 13, count 0 2006.257.23:09:23.16#ibcon#read 6, iclass 13, count 0 2006.257.23:09:23.16#ibcon#end of sib2, iclass 13, count 0 2006.257.23:09:23.16#ibcon#*after write, iclass 13, count 0 2006.257.23:09:23.16#ibcon#*before return 0, iclass 13, count 0 2006.257.23:09:23.16#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:23.16#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:23.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:09:23.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:09:23.16$vck44/vblo=1,629.99 2006.257.23:09:23.16#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.23:09:23.16#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.23:09:23.16#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:23.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:23.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:23.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:23.16#ibcon#enter wrdev, iclass 15, count 0 2006.257.23:09:23.16#ibcon#first serial, iclass 15, count 0 2006.257.23:09:23.16#ibcon#enter sib2, iclass 15, count 0 2006.257.23:09:23.16#ibcon#flushed, iclass 15, count 0 2006.257.23:09:23.16#ibcon#about to write, iclass 15, count 0 2006.257.23:09:23.16#ibcon#wrote, iclass 15, count 0 2006.257.23:09:23.16#ibcon#about to read 3, iclass 15, count 0 2006.257.23:09:23.18#ibcon#read 3, iclass 15, count 0 2006.257.23:09:23.18#ibcon#about to read 4, iclass 15, count 0 2006.257.23:09:23.18#ibcon#read 4, iclass 15, count 0 2006.257.23:09:23.18#ibcon#about to read 5, iclass 15, count 0 2006.257.23:09:23.18#ibcon#read 5, iclass 15, count 0 2006.257.23:09:23.18#ibcon#about to read 6, iclass 15, count 0 2006.257.23:09:23.18#ibcon#read 6, iclass 15, count 0 2006.257.23:09:23.18#ibcon#end of sib2, iclass 15, count 0 2006.257.23:09:23.18#ibcon#*mode == 0, iclass 15, count 0 2006.257.23:09:23.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.23:09:23.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:09:23.18#ibcon#*before write, iclass 15, count 0 2006.257.23:09:23.18#ibcon#enter sib2, iclass 15, count 0 2006.257.23:09:23.18#ibcon#flushed, iclass 15, count 0 2006.257.23:09:23.18#ibcon#about to write, iclass 15, count 0 2006.257.23:09:23.18#ibcon#wrote, iclass 15, count 0 2006.257.23:09:23.18#ibcon#about to read 3, iclass 15, count 0 2006.257.23:09:23.21#abcon#<5=/14 1.0 3.4 20.25 831016.0\r\n> 2006.257.23:09:23.22#ibcon#read 3, iclass 15, count 0 2006.257.23:09:23.22#ibcon#about to read 4, iclass 15, count 0 2006.257.23:09:23.22#ibcon#read 4, iclass 15, count 0 2006.257.23:09:23.22#ibcon#about to read 5, iclass 15, count 0 2006.257.23:09:23.22#ibcon#read 5, iclass 15, count 0 2006.257.23:09:23.22#ibcon#about to read 6, iclass 15, count 0 2006.257.23:09:23.22#ibcon#read 6, iclass 15, count 0 2006.257.23:09:23.22#ibcon#end of sib2, iclass 15, count 0 2006.257.23:09:23.22#ibcon#*after write, iclass 15, count 0 2006.257.23:09:23.22#ibcon#*before return 0, iclass 15, count 0 2006.257.23:09:23.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:23.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:23.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.23:09:23.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.23:09:23.22$vck44/vb=1,4 2006.257.23:09:23.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.23:09:23.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.23:09:23.22#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:23.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:09:23.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:09:23.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:09:23.22#ibcon#enter wrdev, iclass 20, count 2 2006.257.23:09:23.22#ibcon#first serial, iclass 20, count 2 2006.257.23:09:23.22#ibcon#enter sib2, iclass 20, count 2 2006.257.23:09:23.22#ibcon#flushed, iclass 20, count 2 2006.257.23:09:23.22#ibcon#about to write, iclass 20, count 2 2006.257.23:09:23.22#ibcon#wrote, iclass 20, count 2 2006.257.23:09:23.22#ibcon#about to read 3, iclass 20, count 2 2006.257.23:09:23.23#abcon#{5=INTERFACE CLEAR} 2006.257.23:09:23.24#ibcon#read 3, iclass 20, count 2 2006.257.23:09:23.24#ibcon#about to read 4, iclass 20, count 2 2006.257.23:09:23.24#ibcon#read 4, iclass 20, count 2 2006.257.23:09:23.24#ibcon#about to read 5, iclass 20, count 2 2006.257.23:09:23.24#ibcon#read 5, iclass 20, count 2 2006.257.23:09:23.24#ibcon#about to read 6, iclass 20, count 2 2006.257.23:09:23.24#ibcon#read 6, iclass 20, count 2 2006.257.23:09:23.24#ibcon#end of sib2, iclass 20, count 2 2006.257.23:09:23.24#ibcon#*mode == 0, iclass 20, count 2 2006.257.23:09:23.24#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.23:09:23.24#ibcon#[27=AT01-04\r\n] 2006.257.23:09:23.24#ibcon#*before write, iclass 20, count 2 2006.257.23:09:23.24#ibcon#enter sib2, iclass 20, count 2 2006.257.23:09:23.24#ibcon#flushed, iclass 20, count 2 2006.257.23:09:23.24#ibcon#about to write, iclass 20, count 2 2006.257.23:09:23.24#ibcon#wrote, iclass 20, count 2 2006.257.23:09:23.24#ibcon#about to read 3, iclass 20, count 2 2006.257.23:09:23.27#ibcon#read 3, iclass 20, count 2 2006.257.23:09:23.27#ibcon#about to read 4, iclass 20, count 2 2006.257.23:09:23.27#ibcon#read 4, iclass 20, count 2 2006.257.23:09:23.27#ibcon#about to read 5, iclass 20, count 2 2006.257.23:09:23.27#ibcon#read 5, iclass 20, count 2 2006.257.23:09:23.27#ibcon#about to read 6, iclass 20, count 2 2006.257.23:09:23.27#ibcon#read 6, iclass 20, count 2 2006.257.23:09:23.27#ibcon#end of sib2, iclass 20, count 2 2006.257.23:09:23.27#ibcon#*after write, iclass 20, count 2 2006.257.23:09:23.27#ibcon#*before return 0, iclass 20, count 2 2006.257.23:09:23.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:09:23.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:09:23.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.23:09:23.27#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:23.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:09:23.29#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:09:23.39#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:09:23.39#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:09:23.39#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:09:23.39#ibcon#first serial, iclass 20, count 0 2006.257.23:09:23.39#ibcon#enter sib2, iclass 20, count 0 2006.257.23:09:23.39#ibcon#flushed, iclass 20, count 0 2006.257.23:09:23.39#ibcon#about to write, iclass 20, count 0 2006.257.23:09:23.39#ibcon#wrote, iclass 20, count 0 2006.257.23:09:23.39#ibcon#about to read 3, iclass 20, count 0 2006.257.23:09:23.41#ibcon#read 3, iclass 20, count 0 2006.257.23:09:23.41#ibcon#about to read 4, iclass 20, count 0 2006.257.23:09:23.41#ibcon#read 4, iclass 20, count 0 2006.257.23:09:23.41#ibcon#about to read 5, iclass 20, count 0 2006.257.23:09:23.41#ibcon#read 5, iclass 20, count 0 2006.257.23:09:23.41#ibcon#about to read 6, iclass 20, count 0 2006.257.23:09:23.41#ibcon#read 6, iclass 20, count 0 2006.257.23:09:23.41#ibcon#end of sib2, iclass 20, count 0 2006.257.23:09:23.41#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:09:23.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:09:23.41#ibcon#[27=USB\r\n] 2006.257.23:09:23.41#ibcon#*before write, iclass 20, count 0 2006.257.23:09:23.41#ibcon#enter sib2, iclass 20, count 0 2006.257.23:09:23.41#ibcon#flushed, iclass 20, count 0 2006.257.23:09:23.41#ibcon#about to write, iclass 20, count 0 2006.257.23:09:23.41#ibcon#wrote, iclass 20, count 0 2006.257.23:09:23.41#ibcon#about to read 3, iclass 20, count 0 2006.257.23:09:23.44#ibcon#read 3, iclass 20, count 0 2006.257.23:09:23.44#ibcon#about to read 4, iclass 20, count 0 2006.257.23:09:23.44#ibcon#read 4, iclass 20, count 0 2006.257.23:09:23.44#ibcon#about to read 5, iclass 20, count 0 2006.257.23:09:23.44#ibcon#read 5, iclass 20, count 0 2006.257.23:09:23.44#ibcon#about to read 6, iclass 20, count 0 2006.257.23:09:23.44#ibcon#read 6, iclass 20, count 0 2006.257.23:09:23.44#ibcon#end of sib2, iclass 20, count 0 2006.257.23:09:23.44#ibcon#*after write, iclass 20, count 0 2006.257.23:09:23.44#ibcon#*before return 0, iclass 20, count 0 2006.257.23:09:23.44#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:09:23.44#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:09:23.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:09:23.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:09:23.44$vck44/vblo=2,634.99 2006.257.23:09:23.44#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.23:09:23.44#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.23:09:23.44#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:23.44#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:23.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:23.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:23.44#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:09:23.44#ibcon#first serial, iclass 23, count 0 2006.257.23:09:23.44#ibcon#enter sib2, iclass 23, count 0 2006.257.23:09:23.44#ibcon#flushed, iclass 23, count 0 2006.257.23:09:23.44#ibcon#about to write, iclass 23, count 0 2006.257.23:09:23.44#ibcon#wrote, iclass 23, count 0 2006.257.23:09:23.44#ibcon#about to read 3, iclass 23, count 0 2006.257.23:09:23.46#ibcon#read 3, iclass 23, count 0 2006.257.23:09:23.46#ibcon#about to read 4, iclass 23, count 0 2006.257.23:09:23.46#ibcon#read 4, iclass 23, count 0 2006.257.23:09:23.46#ibcon#about to read 5, iclass 23, count 0 2006.257.23:09:23.46#ibcon#read 5, iclass 23, count 0 2006.257.23:09:23.46#ibcon#about to read 6, iclass 23, count 0 2006.257.23:09:23.46#ibcon#read 6, iclass 23, count 0 2006.257.23:09:23.46#ibcon#end of sib2, iclass 23, count 0 2006.257.23:09:23.46#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:09:23.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:09:23.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:09:23.46#ibcon#*before write, iclass 23, count 0 2006.257.23:09:23.46#ibcon#enter sib2, iclass 23, count 0 2006.257.23:09:23.46#ibcon#flushed, iclass 23, count 0 2006.257.23:09:23.46#ibcon#about to write, iclass 23, count 0 2006.257.23:09:23.46#ibcon#wrote, iclass 23, count 0 2006.257.23:09:23.46#ibcon#about to read 3, iclass 23, count 0 2006.257.23:09:23.50#ibcon#read 3, iclass 23, count 0 2006.257.23:09:23.50#ibcon#about to read 4, iclass 23, count 0 2006.257.23:09:23.50#ibcon#read 4, iclass 23, count 0 2006.257.23:09:23.50#ibcon#about to read 5, iclass 23, count 0 2006.257.23:09:23.50#ibcon#read 5, iclass 23, count 0 2006.257.23:09:23.50#ibcon#about to read 6, iclass 23, count 0 2006.257.23:09:23.50#ibcon#read 6, iclass 23, count 0 2006.257.23:09:23.50#ibcon#end of sib2, iclass 23, count 0 2006.257.23:09:23.50#ibcon#*after write, iclass 23, count 0 2006.257.23:09:23.50#ibcon#*before return 0, iclass 23, count 0 2006.257.23:09:23.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:23.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:09:23.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:09:23.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:09:23.50$vck44/vb=2,5 2006.257.23:09:23.50#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.23:09:23.50#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.23:09:23.50#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:23.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:23.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:23.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:23.56#ibcon#enter wrdev, iclass 25, count 2 2006.257.23:09:23.56#ibcon#first serial, iclass 25, count 2 2006.257.23:09:23.56#ibcon#enter sib2, iclass 25, count 2 2006.257.23:09:23.56#ibcon#flushed, iclass 25, count 2 2006.257.23:09:23.56#ibcon#about to write, iclass 25, count 2 2006.257.23:09:23.56#ibcon#wrote, iclass 25, count 2 2006.257.23:09:23.56#ibcon#about to read 3, iclass 25, count 2 2006.257.23:09:23.58#ibcon#read 3, iclass 25, count 2 2006.257.23:09:23.58#ibcon#about to read 4, iclass 25, count 2 2006.257.23:09:23.58#ibcon#read 4, iclass 25, count 2 2006.257.23:09:23.58#ibcon#about to read 5, iclass 25, count 2 2006.257.23:09:23.58#ibcon#read 5, iclass 25, count 2 2006.257.23:09:23.58#ibcon#about to read 6, iclass 25, count 2 2006.257.23:09:23.58#ibcon#read 6, iclass 25, count 2 2006.257.23:09:23.58#ibcon#end of sib2, iclass 25, count 2 2006.257.23:09:23.58#ibcon#*mode == 0, iclass 25, count 2 2006.257.23:09:23.58#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.23:09:23.58#ibcon#[27=AT02-05\r\n] 2006.257.23:09:23.58#ibcon#*before write, iclass 25, count 2 2006.257.23:09:23.58#ibcon#enter sib2, iclass 25, count 2 2006.257.23:09:23.58#ibcon#flushed, iclass 25, count 2 2006.257.23:09:23.58#ibcon#about to write, iclass 25, count 2 2006.257.23:09:23.58#ibcon#wrote, iclass 25, count 2 2006.257.23:09:23.58#ibcon#about to read 3, iclass 25, count 2 2006.257.23:09:23.61#ibcon#read 3, iclass 25, count 2 2006.257.23:09:23.61#ibcon#about to read 4, iclass 25, count 2 2006.257.23:09:23.61#ibcon#read 4, iclass 25, count 2 2006.257.23:09:23.61#ibcon#about to read 5, iclass 25, count 2 2006.257.23:09:23.61#ibcon#read 5, iclass 25, count 2 2006.257.23:09:23.61#ibcon#about to read 6, iclass 25, count 2 2006.257.23:09:23.61#ibcon#read 6, iclass 25, count 2 2006.257.23:09:23.61#ibcon#end of sib2, iclass 25, count 2 2006.257.23:09:23.61#ibcon#*after write, iclass 25, count 2 2006.257.23:09:23.61#ibcon#*before return 0, iclass 25, count 2 2006.257.23:09:23.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:23.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:09:23.61#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.23:09:23.61#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:23.61#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:23.73#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:23.73#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:23.73#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:09:23.73#ibcon#first serial, iclass 25, count 0 2006.257.23:09:23.73#ibcon#enter sib2, iclass 25, count 0 2006.257.23:09:23.73#ibcon#flushed, iclass 25, count 0 2006.257.23:09:23.73#ibcon#about to write, iclass 25, count 0 2006.257.23:09:23.73#ibcon#wrote, iclass 25, count 0 2006.257.23:09:23.73#ibcon#about to read 3, iclass 25, count 0 2006.257.23:09:23.75#ibcon#read 3, iclass 25, count 0 2006.257.23:09:23.75#ibcon#about to read 4, iclass 25, count 0 2006.257.23:09:23.75#ibcon#read 4, iclass 25, count 0 2006.257.23:09:23.75#ibcon#about to read 5, iclass 25, count 0 2006.257.23:09:23.75#ibcon#read 5, iclass 25, count 0 2006.257.23:09:23.75#ibcon#about to read 6, iclass 25, count 0 2006.257.23:09:23.75#ibcon#read 6, iclass 25, count 0 2006.257.23:09:23.75#ibcon#end of sib2, iclass 25, count 0 2006.257.23:09:23.75#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:09:23.75#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:09:23.75#ibcon#[27=USB\r\n] 2006.257.23:09:23.75#ibcon#*before write, iclass 25, count 0 2006.257.23:09:23.75#ibcon#enter sib2, iclass 25, count 0 2006.257.23:09:23.75#ibcon#flushed, iclass 25, count 0 2006.257.23:09:23.75#ibcon#about to write, iclass 25, count 0 2006.257.23:09:23.75#ibcon#wrote, iclass 25, count 0 2006.257.23:09:23.75#ibcon#about to read 3, iclass 25, count 0 2006.257.23:09:23.78#ibcon#read 3, iclass 25, count 0 2006.257.23:09:23.78#ibcon#about to read 4, iclass 25, count 0 2006.257.23:09:23.78#ibcon#read 4, iclass 25, count 0 2006.257.23:09:23.78#ibcon#about to read 5, iclass 25, count 0 2006.257.23:09:23.78#ibcon#read 5, iclass 25, count 0 2006.257.23:09:23.78#ibcon#about to read 6, iclass 25, count 0 2006.257.23:09:23.78#ibcon#read 6, iclass 25, count 0 2006.257.23:09:23.78#ibcon#end of sib2, iclass 25, count 0 2006.257.23:09:23.78#ibcon#*after write, iclass 25, count 0 2006.257.23:09:23.78#ibcon#*before return 0, iclass 25, count 0 2006.257.23:09:23.78#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:23.78#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:09:23.78#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:09:23.78#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:09:23.78$vck44/vblo=3,649.99 2006.257.23:09:23.78#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.23:09:23.78#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.23:09:23.78#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:23.78#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:23.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:23.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:23.78#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:09:23.78#ibcon#first serial, iclass 27, count 0 2006.257.23:09:23.78#ibcon#enter sib2, iclass 27, count 0 2006.257.23:09:23.78#ibcon#flushed, iclass 27, count 0 2006.257.23:09:23.78#ibcon#about to write, iclass 27, count 0 2006.257.23:09:23.78#ibcon#wrote, iclass 27, count 0 2006.257.23:09:23.78#ibcon#about to read 3, iclass 27, count 0 2006.257.23:09:23.80#ibcon#read 3, iclass 27, count 0 2006.257.23:09:23.80#ibcon#about to read 4, iclass 27, count 0 2006.257.23:09:23.80#ibcon#read 4, iclass 27, count 0 2006.257.23:09:23.80#ibcon#about to read 5, iclass 27, count 0 2006.257.23:09:23.80#ibcon#read 5, iclass 27, count 0 2006.257.23:09:23.80#ibcon#about to read 6, iclass 27, count 0 2006.257.23:09:23.80#ibcon#read 6, iclass 27, count 0 2006.257.23:09:23.80#ibcon#end of sib2, iclass 27, count 0 2006.257.23:09:23.80#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:09:23.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:09:23.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:09:23.80#ibcon#*before write, iclass 27, count 0 2006.257.23:09:23.80#ibcon#enter sib2, iclass 27, count 0 2006.257.23:09:23.80#ibcon#flushed, iclass 27, count 0 2006.257.23:09:23.80#ibcon#about to write, iclass 27, count 0 2006.257.23:09:23.80#ibcon#wrote, iclass 27, count 0 2006.257.23:09:23.80#ibcon#about to read 3, iclass 27, count 0 2006.257.23:09:23.84#ibcon#read 3, iclass 27, count 0 2006.257.23:09:23.84#ibcon#about to read 4, iclass 27, count 0 2006.257.23:09:23.84#ibcon#read 4, iclass 27, count 0 2006.257.23:09:23.84#ibcon#about to read 5, iclass 27, count 0 2006.257.23:09:23.84#ibcon#read 5, iclass 27, count 0 2006.257.23:09:23.84#ibcon#about to read 6, iclass 27, count 0 2006.257.23:09:23.84#ibcon#read 6, iclass 27, count 0 2006.257.23:09:23.84#ibcon#end of sib2, iclass 27, count 0 2006.257.23:09:23.84#ibcon#*after write, iclass 27, count 0 2006.257.23:09:23.84#ibcon#*before return 0, iclass 27, count 0 2006.257.23:09:23.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:23.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:09:23.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:09:23.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:09:23.84$vck44/vb=3,4 2006.257.23:09:23.84#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.23:09:23.84#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.23:09:23.84#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:23.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:23.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:23.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:23.90#ibcon#enter wrdev, iclass 29, count 2 2006.257.23:09:23.90#ibcon#first serial, iclass 29, count 2 2006.257.23:09:23.90#ibcon#enter sib2, iclass 29, count 2 2006.257.23:09:23.90#ibcon#flushed, iclass 29, count 2 2006.257.23:09:23.90#ibcon#about to write, iclass 29, count 2 2006.257.23:09:23.90#ibcon#wrote, iclass 29, count 2 2006.257.23:09:23.90#ibcon#about to read 3, iclass 29, count 2 2006.257.23:09:23.92#ibcon#read 3, iclass 29, count 2 2006.257.23:09:23.92#ibcon#about to read 4, iclass 29, count 2 2006.257.23:09:23.92#ibcon#read 4, iclass 29, count 2 2006.257.23:09:23.92#ibcon#about to read 5, iclass 29, count 2 2006.257.23:09:23.92#ibcon#read 5, iclass 29, count 2 2006.257.23:09:23.92#ibcon#about to read 6, iclass 29, count 2 2006.257.23:09:23.92#ibcon#read 6, iclass 29, count 2 2006.257.23:09:23.92#ibcon#end of sib2, iclass 29, count 2 2006.257.23:09:23.92#ibcon#*mode == 0, iclass 29, count 2 2006.257.23:09:23.92#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.23:09:23.92#ibcon#[27=AT03-04\r\n] 2006.257.23:09:23.92#ibcon#*before write, iclass 29, count 2 2006.257.23:09:23.92#ibcon#enter sib2, iclass 29, count 2 2006.257.23:09:23.92#ibcon#flushed, iclass 29, count 2 2006.257.23:09:23.92#ibcon#about to write, iclass 29, count 2 2006.257.23:09:23.92#ibcon#wrote, iclass 29, count 2 2006.257.23:09:23.92#ibcon#about to read 3, iclass 29, count 2 2006.257.23:09:23.95#ibcon#read 3, iclass 29, count 2 2006.257.23:09:23.95#ibcon#about to read 4, iclass 29, count 2 2006.257.23:09:23.95#ibcon#read 4, iclass 29, count 2 2006.257.23:09:23.95#ibcon#about to read 5, iclass 29, count 2 2006.257.23:09:23.95#ibcon#read 5, iclass 29, count 2 2006.257.23:09:23.95#ibcon#about to read 6, iclass 29, count 2 2006.257.23:09:23.95#ibcon#read 6, iclass 29, count 2 2006.257.23:09:23.95#ibcon#end of sib2, iclass 29, count 2 2006.257.23:09:23.95#ibcon#*after write, iclass 29, count 2 2006.257.23:09:23.95#ibcon#*before return 0, iclass 29, count 2 2006.257.23:09:23.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:23.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:09:23.95#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.23:09:23.95#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:23.95#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:24.07#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:24.07#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:24.07#ibcon#enter wrdev, iclass 29, count 0 2006.257.23:09:24.07#ibcon#first serial, iclass 29, count 0 2006.257.23:09:24.07#ibcon#enter sib2, iclass 29, count 0 2006.257.23:09:24.07#ibcon#flushed, iclass 29, count 0 2006.257.23:09:24.07#ibcon#about to write, iclass 29, count 0 2006.257.23:09:24.07#ibcon#wrote, iclass 29, count 0 2006.257.23:09:24.07#ibcon#about to read 3, iclass 29, count 0 2006.257.23:09:24.09#ibcon#read 3, iclass 29, count 0 2006.257.23:09:24.09#ibcon#about to read 4, iclass 29, count 0 2006.257.23:09:24.09#ibcon#read 4, iclass 29, count 0 2006.257.23:09:24.09#ibcon#about to read 5, iclass 29, count 0 2006.257.23:09:24.09#ibcon#read 5, iclass 29, count 0 2006.257.23:09:24.09#ibcon#about to read 6, iclass 29, count 0 2006.257.23:09:24.09#ibcon#read 6, iclass 29, count 0 2006.257.23:09:24.09#ibcon#end of sib2, iclass 29, count 0 2006.257.23:09:24.09#ibcon#*mode == 0, iclass 29, count 0 2006.257.23:09:24.09#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.23:09:24.09#ibcon#[27=USB\r\n] 2006.257.23:09:24.09#ibcon#*before write, iclass 29, count 0 2006.257.23:09:24.09#ibcon#enter sib2, iclass 29, count 0 2006.257.23:09:24.09#ibcon#flushed, iclass 29, count 0 2006.257.23:09:24.09#ibcon#about to write, iclass 29, count 0 2006.257.23:09:24.09#ibcon#wrote, iclass 29, count 0 2006.257.23:09:24.09#ibcon#about to read 3, iclass 29, count 0 2006.257.23:09:24.12#ibcon#read 3, iclass 29, count 0 2006.257.23:09:24.12#ibcon#about to read 4, iclass 29, count 0 2006.257.23:09:24.12#ibcon#read 4, iclass 29, count 0 2006.257.23:09:24.12#ibcon#about to read 5, iclass 29, count 0 2006.257.23:09:24.12#ibcon#read 5, iclass 29, count 0 2006.257.23:09:24.12#ibcon#about to read 6, iclass 29, count 0 2006.257.23:09:24.12#ibcon#read 6, iclass 29, count 0 2006.257.23:09:24.12#ibcon#end of sib2, iclass 29, count 0 2006.257.23:09:24.12#ibcon#*after write, iclass 29, count 0 2006.257.23:09:24.12#ibcon#*before return 0, iclass 29, count 0 2006.257.23:09:24.12#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:24.12#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:09:24.12#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.23:09:24.12#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.23:09:24.12$vck44/vblo=4,679.99 2006.257.23:09:24.12#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.23:09:24.12#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.23:09:24.12#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:24.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:24.12#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:24.12#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:24.12#ibcon#enter wrdev, iclass 31, count 0 2006.257.23:09:24.12#ibcon#first serial, iclass 31, count 0 2006.257.23:09:24.12#ibcon#enter sib2, iclass 31, count 0 2006.257.23:09:24.12#ibcon#flushed, iclass 31, count 0 2006.257.23:09:24.12#ibcon#about to write, iclass 31, count 0 2006.257.23:09:24.12#ibcon#wrote, iclass 31, count 0 2006.257.23:09:24.12#ibcon#about to read 3, iclass 31, count 0 2006.257.23:09:24.14#ibcon#read 3, iclass 31, count 0 2006.257.23:09:24.14#ibcon#about to read 4, iclass 31, count 0 2006.257.23:09:24.14#ibcon#read 4, iclass 31, count 0 2006.257.23:09:24.14#ibcon#about to read 5, iclass 31, count 0 2006.257.23:09:24.14#ibcon#read 5, iclass 31, count 0 2006.257.23:09:24.14#ibcon#about to read 6, iclass 31, count 0 2006.257.23:09:24.14#ibcon#read 6, iclass 31, count 0 2006.257.23:09:24.14#ibcon#end of sib2, iclass 31, count 0 2006.257.23:09:24.14#ibcon#*mode == 0, iclass 31, count 0 2006.257.23:09:24.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.23:09:24.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:09:24.14#ibcon#*before write, iclass 31, count 0 2006.257.23:09:24.14#ibcon#enter sib2, iclass 31, count 0 2006.257.23:09:24.14#ibcon#flushed, iclass 31, count 0 2006.257.23:09:24.14#ibcon#about to write, iclass 31, count 0 2006.257.23:09:24.14#ibcon#wrote, iclass 31, count 0 2006.257.23:09:24.14#ibcon#about to read 3, iclass 31, count 0 2006.257.23:09:24.18#ibcon#read 3, iclass 31, count 0 2006.257.23:09:24.18#ibcon#about to read 4, iclass 31, count 0 2006.257.23:09:24.18#ibcon#read 4, iclass 31, count 0 2006.257.23:09:24.18#ibcon#about to read 5, iclass 31, count 0 2006.257.23:09:24.18#ibcon#read 5, iclass 31, count 0 2006.257.23:09:24.18#ibcon#about to read 6, iclass 31, count 0 2006.257.23:09:24.18#ibcon#read 6, iclass 31, count 0 2006.257.23:09:24.18#ibcon#end of sib2, iclass 31, count 0 2006.257.23:09:24.18#ibcon#*after write, iclass 31, count 0 2006.257.23:09:24.18#ibcon#*before return 0, iclass 31, count 0 2006.257.23:09:24.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:24.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:09:24.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.23:09:24.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.23:09:24.18$vck44/vb=4,5 2006.257.23:09:24.18#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.23:09:24.18#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.23:09:24.18#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:24.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:24.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:24.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:24.24#ibcon#enter wrdev, iclass 33, count 2 2006.257.23:09:24.24#ibcon#first serial, iclass 33, count 2 2006.257.23:09:24.24#ibcon#enter sib2, iclass 33, count 2 2006.257.23:09:24.24#ibcon#flushed, iclass 33, count 2 2006.257.23:09:24.24#ibcon#about to write, iclass 33, count 2 2006.257.23:09:24.24#ibcon#wrote, iclass 33, count 2 2006.257.23:09:24.24#ibcon#about to read 3, iclass 33, count 2 2006.257.23:09:24.26#ibcon#read 3, iclass 33, count 2 2006.257.23:09:24.26#ibcon#about to read 4, iclass 33, count 2 2006.257.23:09:24.26#ibcon#read 4, iclass 33, count 2 2006.257.23:09:24.26#ibcon#about to read 5, iclass 33, count 2 2006.257.23:09:24.26#ibcon#read 5, iclass 33, count 2 2006.257.23:09:24.26#ibcon#about to read 6, iclass 33, count 2 2006.257.23:09:24.26#ibcon#read 6, iclass 33, count 2 2006.257.23:09:24.26#ibcon#end of sib2, iclass 33, count 2 2006.257.23:09:24.26#ibcon#*mode == 0, iclass 33, count 2 2006.257.23:09:24.26#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.23:09:24.26#ibcon#[27=AT04-05\r\n] 2006.257.23:09:24.26#ibcon#*before write, iclass 33, count 2 2006.257.23:09:24.26#ibcon#enter sib2, iclass 33, count 2 2006.257.23:09:24.26#ibcon#flushed, iclass 33, count 2 2006.257.23:09:24.26#ibcon#about to write, iclass 33, count 2 2006.257.23:09:24.26#ibcon#wrote, iclass 33, count 2 2006.257.23:09:24.26#ibcon#about to read 3, iclass 33, count 2 2006.257.23:09:24.29#ibcon#read 3, iclass 33, count 2 2006.257.23:09:24.29#ibcon#about to read 4, iclass 33, count 2 2006.257.23:09:24.29#ibcon#read 4, iclass 33, count 2 2006.257.23:09:24.29#ibcon#about to read 5, iclass 33, count 2 2006.257.23:09:24.29#ibcon#read 5, iclass 33, count 2 2006.257.23:09:24.29#ibcon#about to read 6, iclass 33, count 2 2006.257.23:09:24.29#ibcon#read 6, iclass 33, count 2 2006.257.23:09:24.29#ibcon#end of sib2, iclass 33, count 2 2006.257.23:09:24.29#ibcon#*after write, iclass 33, count 2 2006.257.23:09:24.29#ibcon#*before return 0, iclass 33, count 2 2006.257.23:09:24.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:24.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:09:24.29#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.23:09:24.29#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:24.29#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:24.41#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:24.41#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:24.41#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:09:24.41#ibcon#first serial, iclass 33, count 0 2006.257.23:09:24.41#ibcon#enter sib2, iclass 33, count 0 2006.257.23:09:24.41#ibcon#flushed, iclass 33, count 0 2006.257.23:09:24.41#ibcon#about to write, iclass 33, count 0 2006.257.23:09:24.41#ibcon#wrote, iclass 33, count 0 2006.257.23:09:24.41#ibcon#about to read 3, iclass 33, count 0 2006.257.23:09:24.43#ibcon#read 3, iclass 33, count 0 2006.257.23:09:24.43#ibcon#about to read 4, iclass 33, count 0 2006.257.23:09:24.43#ibcon#read 4, iclass 33, count 0 2006.257.23:09:24.43#ibcon#about to read 5, iclass 33, count 0 2006.257.23:09:24.43#ibcon#read 5, iclass 33, count 0 2006.257.23:09:24.43#ibcon#about to read 6, iclass 33, count 0 2006.257.23:09:24.43#ibcon#read 6, iclass 33, count 0 2006.257.23:09:24.43#ibcon#end of sib2, iclass 33, count 0 2006.257.23:09:24.43#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:09:24.43#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:09:24.43#ibcon#[27=USB\r\n] 2006.257.23:09:24.43#ibcon#*before write, iclass 33, count 0 2006.257.23:09:24.43#ibcon#enter sib2, iclass 33, count 0 2006.257.23:09:24.43#ibcon#flushed, iclass 33, count 0 2006.257.23:09:24.43#ibcon#about to write, iclass 33, count 0 2006.257.23:09:24.43#ibcon#wrote, iclass 33, count 0 2006.257.23:09:24.43#ibcon#about to read 3, iclass 33, count 0 2006.257.23:09:24.46#ibcon#read 3, iclass 33, count 0 2006.257.23:09:24.46#ibcon#about to read 4, iclass 33, count 0 2006.257.23:09:24.46#ibcon#read 4, iclass 33, count 0 2006.257.23:09:24.46#ibcon#about to read 5, iclass 33, count 0 2006.257.23:09:24.46#ibcon#read 5, iclass 33, count 0 2006.257.23:09:24.46#ibcon#about to read 6, iclass 33, count 0 2006.257.23:09:24.46#ibcon#read 6, iclass 33, count 0 2006.257.23:09:24.46#ibcon#end of sib2, iclass 33, count 0 2006.257.23:09:24.46#ibcon#*after write, iclass 33, count 0 2006.257.23:09:24.46#ibcon#*before return 0, iclass 33, count 0 2006.257.23:09:24.46#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:24.46#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:09:24.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:09:24.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:09:24.46$vck44/vblo=5,709.99 2006.257.23:09:24.46#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.23:09:24.46#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.23:09:24.46#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:24.46#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:24.46#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:24.46#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:24.46#ibcon#enter wrdev, iclass 35, count 0 2006.257.23:09:24.46#ibcon#first serial, iclass 35, count 0 2006.257.23:09:24.46#ibcon#enter sib2, iclass 35, count 0 2006.257.23:09:24.46#ibcon#flushed, iclass 35, count 0 2006.257.23:09:24.46#ibcon#about to write, iclass 35, count 0 2006.257.23:09:24.46#ibcon#wrote, iclass 35, count 0 2006.257.23:09:24.46#ibcon#about to read 3, iclass 35, count 0 2006.257.23:09:24.48#ibcon#read 3, iclass 35, count 0 2006.257.23:09:24.48#ibcon#about to read 4, iclass 35, count 0 2006.257.23:09:24.48#ibcon#read 4, iclass 35, count 0 2006.257.23:09:24.48#ibcon#about to read 5, iclass 35, count 0 2006.257.23:09:24.48#ibcon#read 5, iclass 35, count 0 2006.257.23:09:24.48#ibcon#about to read 6, iclass 35, count 0 2006.257.23:09:24.48#ibcon#read 6, iclass 35, count 0 2006.257.23:09:24.48#ibcon#end of sib2, iclass 35, count 0 2006.257.23:09:24.48#ibcon#*mode == 0, iclass 35, count 0 2006.257.23:09:24.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.23:09:24.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:09:24.48#ibcon#*before write, iclass 35, count 0 2006.257.23:09:24.48#ibcon#enter sib2, iclass 35, count 0 2006.257.23:09:24.48#ibcon#flushed, iclass 35, count 0 2006.257.23:09:24.48#ibcon#about to write, iclass 35, count 0 2006.257.23:09:24.48#ibcon#wrote, iclass 35, count 0 2006.257.23:09:24.48#ibcon#about to read 3, iclass 35, count 0 2006.257.23:09:24.52#ibcon#read 3, iclass 35, count 0 2006.257.23:09:24.52#ibcon#about to read 4, iclass 35, count 0 2006.257.23:09:24.52#ibcon#read 4, iclass 35, count 0 2006.257.23:09:24.52#ibcon#about to read 5, iclass 35, count 0 2006.257.23:09:24.52#ibcon#read 5, iclass 35, count 0 2006.257.23:09:24.52#ibcon#about to read 6, iclass 35, count 0 2006.257.23:09:24.52#ibcon#read 6, iclass 35, count 0 2006.257.23:09:24.52#ibcon#end of sib2, iclass 35, count 0 2006.257.23:09:24.52#ibcon#*after write, iclass 35, count 0 2006.257.23:09:24.52#ibcon#*before return 0, iclass 35, count 0 2006.257.23:09:24.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:24.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:09:24.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.23:09:24.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.23:09:24.52$vck44/vb=5,4 2006.257.23:09:24.52#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.23:09:24.52#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.23:09:24.52#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:24.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:24.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:24.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:24.58#ibcon#enter wrdev, iclass 37, count 2 2006.257.23:09:24.58#ibcon#first serial, iclass 37, count 2 2006.257.23:09:24.58#ibcon#enter sib2, iclass 37, count 2 2006.257.23:09:24.58#ibcon#flushed, iclass 37, count 2 2006.257.23:09:24.58#ibcon#about to write, iclass 37, count 2 2006.257.23:09:24.58#ibcon#wrote, iclass 37, count 2 2006.257.23:09:24.58#ibcon#about to read 3, iclass 37, count 2 2006.257.23:09:24.60#ibcon#read 3, iclass 37, count 2 2006.257.23:09:24.60#ibcon#about to read 4, iclass 37, count 2 2006.257.23:09:24.60#ibcon#read 4, iclass 37, count 2 2006.257.23:09:24.60#ibcon#about to read 5, iclass 37, count 2 2006.257.23:09:24.60#ibcon#read 5, iclass 37, count 2 2006.257.23:09:24.60#ibcon#about to read 6, iclass 37, count 2 2006.257.23:09:24.60#ibcon#read 6, iclass 37, count 2 2006.257.23:09:24.60#ibcon#end of sib2, iclass 37, count 2 2006.257.23:09:24.60#ibcon#*mode == 0, iclass 37, count 2 2006.257.23:09:24.60#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.23:09:24.60#ibcon#[27=AT05-04\r\n] 2006.257.23:09:24.60#ibcon#*before write, iclass 37, count 2 2006.257.23:09:24.60#ibcon#enter sib2, iclass 37, count 2 2006.257.23:09:24.60#ibcon#flushed, iclass 37, count 2 2006.257.23:09:24.60#ibcon#about to write, iclass 37, count 2 2006.257.23:09:24.60#ibcon#wrote, iclass 37, count 2 2006.257.23:09:24.60#ibcon#about to read 3, iclass 37, count 2 2006.257.23:09:24.63#ibcon#read 3, iclass 37, count 2 2006.257.23:09:24.63#ibcon#about to read 4, iclass 37, count 2 2006.257.23:09:24.63#ibcon#read 4, iclass 37, count 2 2006.257.23:09:24.63#ibcon#about to read 5, iclass 37, count 2 2006.257.23:09:24.63#ibcon#read 5, iclass 37, count 2 2006.257.23:09:24.63#ibcon#about to read 6, iclass 37, count 2 2006.257.23:09:24.63#ibcon#read 6, iclass 37, count 2 2006.257.23:09:24.63#ibcon#end of sib2, iclass 37, count 2 2006.257.23:09:24.63#ibcon#*after write, iclass 37, count 2 2006.257.23:09:24.63#ibcon#*before return 0, iclass 37, count 2 2006.257.23:09:24.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:24.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:09:24.63#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.23:09:24.63#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:24.63#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:24.75#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:24.75#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:24.75#ibcon#enter wrdev, iclass 37, count 0 2006.257.23:09:24.75#ibcon#first serial, iclass 37, count 0 2006.257.23:09:24.75#ibcon#enter sib2, iclass 37, count 0 2006.257.23:09:24.75#ibcon#flushed, iclass 37, count 0 2006.257.23:09:24.75#ibcon#about to write, iclass 37, count 0 2006.257.23:09:24.75#ibcon#wrote, iclass 37, count 0 2006.257.23:09:24.75#ibcon#about to read 3, iclass 37, count 0 2006.257.23:09:24.77#ibcon#read 3, iclass 37, count 0 2006.257.23:09:24.77#ibcon#about to read 4, iclass 37, count 0 2006.257.23:09:24.77#ibcon#read 4, iclass 37, count 0 2006.257.23:09:24.77#ibcon#about to read 5, iclass 37, count 0 2006.257.23:09:24.77#ibcon#read 5, iclass 37, count 0 2006.257.23:09:24.77#ibcon#about to read 6, iclass 37, count 0 2006.257.23:09:24.77#ibcon#read 6, iclass 37, count 0 2006.257.23:09:24.77#ibcon#end of sib2, iclass 37, count 0 2006.257.23:09:24.77#ibcon#*mode == 0, iclass 37, count 0 2006.257.23:09:24.77#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.23:09:24.77#ibcon#[27=USB\r\n] 2006.257.23:09:24.77#ibcon#*before write, iclass 37, count 0 2006.257.23:09:24.77#ibcon#enter sib2, iclass 37, count 0 2006.257.23:09:24.77#ibcon#flushed, iclass 37, count 0 2006.257.23:09:24.77#ibcon#about to write, iclass 37, count 0 2006.257.23:09:24.77#ibcon#wrote, iclass 37, count 0 2006.257.23:09:24.77#ibcon#about to read 3, iclass 37, count 0 2006.257.23:09:24.80#ibcon#read 3, iclass 37, count 0 2006.257.23:09:24.80#ibcon#about to read 4, iclass 37, count 0 2006.257.23:09:24.80#ibcon#read 4, iclass 37, count 0 2006.257.23:09:24.80#ibcon#about to read 5, iclass 37, count 0 2006.257.23:09:24.80#ibcon#read 5, iclass 37, count 0 2006.257.23:09:24.80#ibcon#about to read 6, iclass 37, count 0 2006.257.23:09:24.80#ibcon#read 6, iclass 37, count 0 2006.257.23:09:24.80#ibcon#end of sib2, iclass 37, count 0 2006.257.23:09:24.80#ibcon#*after write, iclass 37, count 0 2006.257.23:09:24.80#ibcon#*before return 0, iclass 37, count 0 2006.257.23:09:24.80#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:24.80#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:09:24.80#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.23:09:24.80#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.23:09:24.80$vck44/vblo=6,719.99 2006.257.23:09:24.80#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.23:09:24.80#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.23:09:24.80#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:24.80#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:24.80#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:24.80#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:24.80#ibcon#enter wrdev, iclass 39, count 0 2006.257.23:09:24.80#ibcon#first serial, iclass 39, count 0 2006.257.23:09:24.80#ibcon#enter sib2, iclass 39, count 0 2006.257.23:09:24.80#ibcon#flushed, iclass 39, count 0 2006.257.23:09:24.80#ibcon#about to write, iclass 39, count 0 2006.257.23:09:24.80#ibcon#wrote, iclass 39, count 0 2006.257.23:09:24.80#ibcon#about to read 3, iclass 39, count 0 2006.257.23:09:24.82#ibcon#read 3, iclass 39, count 0 2006.257.23:09:24.82#ibcon#about to read 4, iclass 39, count 0 2006.257.23:09:24.82#ibcon#read 4, iclass 39, count 0 2006.257.23:09:24.82#ibcon#about to read 5, iclass 39, count 0 2006.257.23:09:24.82#ibcon#read 5, iclass 39, count 0 2006.257.23:09:24.82#ibcon#about to read 6, iclass 39, count 0 2006.257.23:09:24.82#ibcon#read 6, iclass 39, count 0 2006.257.23:09:24.82#ibcon#end of sib2, iclass 39, count 0 2006.257.23:09:24.82#ibcon#*mode == 0, iclass 39, count 0 2006.257.23:09:24.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.23:09:24.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:09:24.82#ibcon#*before write, iclass 39, count 0 2006.257.23:09:24.82#ibcon#enter sib2, iclass 39, count 0 2006.257.23:09:24.82#ibcon#flushed, iclass 39, count 0 2006.257.23:09:24.82#ibcon#about to write, iclass 39, count 0 2006.257.23:09:24.82#ibcon#wrote, iclass 39, count 0 2006.257.23:09:24.82#ibcon#about to read 3, iclass 39, count 0 2006.257.23:09:24.86#ibcon#read 3, iclass 39, count 0 2006.257.23:09:24.86#ibcon#about to read 4, iclass 39, count 0 2006.257.23:09:24.86#ibcon#read 4, iclass 39, count 0 2006.257.23:09:24.86#ibcon#about to read 5, iclass 39, count 0 2006.257.23:09:24.86#ibcon#read 5, iclass 39, count 0 2006.257.23:09:24.86#ibcon#about to read 6, iclass 39, count 0 2006.257.23:09:24.86#ibcon#read 6, iclass 39, count 0 2006.257.23:09:24.86#ibcon#end of sib2, iclass 39, count 0 2006.257.23:09:24.86#ibcon#*after write, iclass 39, count 0 2006.257.23:09:24.86#ibcon#*before return 0, iclass 39, count 0 2006.257.23:09:24.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:24.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:09:24.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.23:09:24.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.23:09:24.86$vck44/vb=6,4 2006.257.23:09:24.86#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.23:09:24.86#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.23:09:24.86#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:24.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:24.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:24.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:24.92#ibcon#enter wrdev, iclass 3, count 2 2006.257.23:09:24.92#ibcon#first serial, iclass 3, count 2 2006.257.23:09:24.92#ibcon#enter sib2, iclass 3, count 2 2006.257.23:09:24.92#ibcon#flushed, iclass 3, count 2 2006.257.23:09:24.92#ibcon#about to write, iclass 3, count 2 2006.257.23:09:24.92#ibcon#wrote, iclass 3, count 2 2006.257.23:09:24.92#ibcon#about to read 3, iclass 3, count 2 2006.257.23:09:24.94#ibcon#read 3, iclass 3, count 2 2006.257.23:09:24.94#ibcon#about to read 4, iclass 3, count 2 2006.257.23:09:24.94#ibcon#read 4, iclass 3, count 2 2006.257.23:09:24.94#ibcon#about to read 5, iclass 3, count 2 2006.257.23:09:24.94#ibcon#read 5, iclass 3, count 2 2006.257.23:09:24.94#ibcon#about to read 6, iclass 3, count 2 2006.257.23:09:24.94#ibcon#read 6, iclass 3, count 2 2006.257.23:09:24.94#ibcon#end of sib2, iclass 3, count 2 2006.257.23:09:24.94#ibcon#*mode == 0, iclass 3, count 2 2006.257.23:09:24.94#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.23:09:24.94#ibcon#[27=AT06-04\r\n] 2006.257.23:09:24.94#ibcon#*before write, iclass 3, count 2 2006.257.23:09:24.94#ibcon#enter sib2, iclass 3, count 2 2006.257.23:09:24.94#ibcon#flushed, iclass 3, count 2 2006.257.23:09:24.94#ibcon#about to write, iclass 3, count 2 2006.257.23:09:24.94#ibcon#wrote, iclass 3, count 2 2006.257.23:09:24.94#ibcon#about to read 3, iclass 3, count 2 2006.257.23:09:24.97#ibcon#read 3, iclass 3, count 2 2006.257.23:09:24.97#ibcon#about to read 4, iclass 3, count 2 2006.257.23:09:24.97#ibcon#read 4, iclass 3, count 2 2006.257.23:09:24.97#ibcon#about to read 5, iclass 3, count 2 2006.257.23:09:24.97#ibcon#read 5, iclass 3, count 2 2006.257.23:09:24.97#ibcon#about to read 6, iclass 3, count 2 2006.257.23:09:24.97#ibcon#read 6, iclass 3, count 2 2006.257.23:09:24.97#ibcon#end of sib2, iclass 3, count 2 2006.257.23:09:24.97#ibcon#*after write, iclass 3, count 2 2006.257.23:09:24.97#ibcon#*before return 0, iclass 3, count 2 2006.257.23:09:24.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:24.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:09:24.97#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.23:09:24.97#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:24.97#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:25.09#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:25.09#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:25.09#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:09:25.09#ibcon#first serial, iclass 3, count 0 2006.257.23:09:25.09#ibcon#enter sib2, iclass 3, count 0 2006.257.23:09:25.09#ibcon#flushed, iclass 3, count 0 2006.257.23:09:25.09#ibcon#about to write, iclass 3, count 0 2006.257.23:09:25.09#ibcon#wrote, iclass 3, count 0 2006.257.23:09:25.09#ibcon#about to read 3, iclass 3, count 0 2006.257.23:09:25.11#ibcon#read 3, iclass 3, count 0 2006.257.23:09:25.11#ibcon#about to read 4, iclass 3, count 0 2006.257.23:09:25.11#ibcon#read 4, iclass 3, count 0 2006.257.23:09:25.11#ibcon#about to read 5, iclass 3, count 0 2006.257.23:09:25.11#ibcon#read 5, iclass 3, count 0 2006.257.23:09:25.11#ibcon#about to read 6, iclass 3, count 0 2006.257.23:09:25.11#ibcon#read 6, iclass 3, count 0 2006.257.23:09:25.11#ibcon#end of sib2, iclass 3, count 0 2006.257.23:09:25.11#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:09:25.11#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:09:25.11#ibcon#[27=USB\r\n] 2006.257.23:09:25.11#ibcon#*before write, iclass 3, count 0 2006.257.23:09:25.11#ibcon#enter sib2, iclass 3, count 0 2006.257.23:09:25.11#ibcon#flushed, iclass 3, count 0 2006.257.23:09:25.11#ibcon#about to write, iclass 3, count 0 2006.257.23:09:25.11#ibcon#wrote, iclass 3, count 0 2006.257.23:09:25.11#ibcon#about to read 3, iclass 3, count 0 2006.257.23:09:25.14#ibcon#read 3, iclass 3, count 0 2006.257.23:09:25.14#ibcon#about to read 4, iclass 3, count 0 2006.257.23:09:25.14#ibcon#read 4, iclass 3, count 0 2006.257.23:09:25.14#ibcon#about to read 5, iclass 3, count 0 2006.257.23:09:25.14#ibcon#read 5, iclass 3, count 0 2006.257.23:09:25.14#ibcon#about to read 6, iclass 3, count 0 2006.257.23:09:25.14#ibcon#read 6, iclass 3, count 0 2006.257.23:09:25.14#ibcon#end of sib2, iclass 3, count 0 2006.257.23:09:25.14#ibcon#*after write, iclass 3, count 0 2006.257.23:09:25.14#ibcon#*before return 0, iclass 3, count 0 2006.257.23:09:25.14#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:25.14#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:09:25.14#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:09:25.14#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:09:25.14$vck44/vblo=7,734.99 2006.257.23:09:25.14#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.23:09:25.14#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.23:09:25.14#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:25.14#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:25.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:25.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:25.14#ibcon#enter wrdev, iclass 5, count 0 2006.257.23:09:25.14#ibcon#first serial, iclass 5, count 0 2006.257.23:09:25.14#ibcon#enter sib2, iclass 5, count 0 2006.257.23:09:25.14#ibcon#flushed, iclass 5, count 0 2006.257.23:09:25.14#ibcon#about to write, iclass 5, count 0 2006.257.23:09:25.14#ibcon#wrote, iclass 5, count 0 2006.257.23:09:25.14#ibcon#about to read 3, iclass 5, count 0 2006.257.23:09:25.16#ibcon#read 3, iclass 5, count 0 2006.257.23:09:25.16#ibcon#about to read 4, iclass 5, count 0 2006.257.23:09:25.16#ibcon#read 4, iclass 5, count 0 2006.257.23:09:25.16#ibcon#about to read 5, iclass 5, count 0 2006.257.23:09:25.16#ibcon#read 5, iclass 5, count 0 2006.257.23:09:25.16#ibcon#about to read 6, iclass 5, count 0 2006.257.23:09:25.16#ibcon#read 6, iclass 5, count 0 2006.257.23:09:25.16#ibcon#end of sib2, iclass 5, count 0 2006.257.23:09:25.16#ibcon#*mode == 0, iclass 5, count 0 2006.257.23:09:25.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.23:09:25.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:09:25.16#ibcon#*before write, iclass 5, count 0 2006.257.23:09:25.16#ibcon#enter sib2, iclass 5, count 0 2006.257.23:09:25.16#ibcon#flushed, iclass 5, count 0 2006.257.23:09:25.16#ibcon#about to write, iclass 5, count 0 2006.257.23:09:25.16#ibcon#wrote, iclass 5, count 0 2006.257.23:09:25.16#ibcon#about to read 3, iclass 5, count 0 2006.257.23:09:25.20#ibcon#read 3, iclass 5, count 0 2006.257.23:09:25.20#ibcon#about to read 4, iclass 5, count 0 2006.257.23:09:25.20#ibcon#read 4, iclass 5, count 0 2006.257.23:09:25.20#ibcon#about to read 5, iclass 5, count 0 2006.257.23:09:25.20#ibcon#read 5, iclass 5, count 0 2006.257.23:09:25.20#ibcon#about to read 6, iclass 5, count 0 2006.257.23:09:25.20#ibcon#read 6, iclass 5, count 0 2006.257.23:09:25.20#ibcon#end of sib2, iclass 5, count 0 2006.257.23:09:25.20#ibcon#*after write, iclass 5, count 0 2006.257.23:09:25.20#ibcon#*before return 0, iclass 5, count 0 2006.257.23:09:25.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:25.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:09:25.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.23:09:25.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.23:09:25.20$vck44/vb=7,4 2006.257.23:09:25.20#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.23:09:25.20#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.23:09:25.20#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:25.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:25.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:25.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:25.26#ibcon#enter wrdev, iclass 7, count 2 2006.257.23:09:25.26#ibcon#first serial, iclass 7, count 2 2006.257.23:09:25.26#ibcon#enter sib2, iclass 7, count 2 2006.257.23:09:25.26#ibcon#flushed, iclass 7, count 2 2006.257.23:09:25.26#ibcon#about to write, iclass 7, count 2 2006.257.23:09:25.26#ibcon#wrote, iclass 7, count 2 2006.257.23:09:25.26#ibcon#about to read 3, iclass 7, count 2 2006.257.23:09:25.28#ibcon#read 3, iclass 7, count 2 2006.257.23:09:25.28#ibcon#about to read 4, iclass 7, count 2 2006.257.23:09:25.28#ibcon#read 4, iclass 7, count 2 2006.257.23:09:25.28#ibcon#about to read 5, iclass 7, count 2 2006.257.23:09:25.28#ibcon#read 5, iclass 7, count 2 2006.257.23:09:25.28#ibcon#about to read 6, iclass 7, count 2 2006.257.23:09:25.28#ibcon#read 6, iclass 7, count 2 2006.257.23:09:25.28#ibcon#end of sib2, iclass 7, count 2 2006.257.23:09:25.28#ibcon#*mode == 0, iclass 7, count 2 2006.257.23:09:25.28#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.23:09:25.28#ibcon#[27=AT07-04\r\n] 2006.257.23:09:25.28#ibcon#*before write, iclass 7, count 2 2006.257.23:09:25.28#ibcon#enter sib2, iclass 7, count 2 2006.257.23:09:25.28#ibcon#flushed, iclass 7, count 2 2006.257.23:09:25.28#ibcon#about to write, iclass 7, count 2 2006.257.23:09:25.28#ibcon#wrote, iclass 7, count 2 2006.257.23:09:25.28#ibcon#about to read 3, iclass 7, count 2 2006.257.23:09:25.31#ibcon#read 3, iclass 7, count 2 2006.257.23:09:25.31#ibcon#about to read 4, iclass 7, count 2 2006.257.23:09:25.31#ibcon#read 4, iclass 7, count 2 2006.257.23:09:25.31#ibcon#about to read 5, iclass 7, count 2 2006.257.23:09:25.31#ibcon#read 5, iclass 7, count 2 2006.257.23:09:25.31#ibcon#about to read 6, iclass 7, count 2 2006.257.23:09:25.31#ibcon#read 6, iclass 7, count 2 2006.257.23:09:25.31#ibcon#end of sib2, iclass 7, count 2 2006.257.23:09:25.31#ibcon#*after write, iclass 7, count 2 2006.257.23:09:25.31#ibcon#*before return 0, iclass 7, count 2 2006.257.23:09:25.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:25.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:09:25.31#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.23:09:25.31#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:25.31#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:25.43#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:25.43#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:25.43#ibcon#enter wrdev, iclass 7, count 0 2006.257.23:09:25.43#ibcon#first serial, iclass 7, count 0 2006.257.23:09:25.43#ibcon#enter sib2, iclass 7, count 0 2006.257.23:09:25.43#ibcon#flushed, iclass 7, count 0 2006.257.23:09:25.43#ibcon#about to write, iclass 7, count 0 2006.257.23:09:25.43#ibcon#wrote, iclass 7, count 0 2006.257.23:09:25.43#ibcon#about to read 3, iclass 7, count 0 2006.257.23:09:25.45#ibcon#read 3, iclass 7, count 0 2006.257.23:09:25.45#ibcon#about to read 4, iclass 7, count 0 2006.257.23:09:25.45#ibcon#read 4, iclass 7, count 0 2006.257.23:09:25.45#ibcon#about to read 5, iclass 7, count 0 2006.257.23:09:25.45#ibcon#read 5, iclass 7, count 0 2006.257.23:09:25.45#ibcon#about to read 6, iclass 7, count 0 2006.257.23:09:25.45#ibcon#read 6, iclass 7, count 0 2006.257.23:09:25.45#ibcon#end of sib2, iclass 7, count 0 2006.257.23:09:25.45#ibcon#*mode == 0, iclass 7, count 0 2006.257.23:09:25.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.23:09:25.45#ibcon#[27=USB\r\n] 2006.257.23:09:25.45#ibcon#*before write, iclass 7, count 0 2006.257.23:09:25.45#ibcon#enter sib2, iclass 7, count 0 2006.257.23:09:25.45#ibcon#flushed, iclass 7, count 0 2006.257.23:09:25.45#ibcon#about to write, iclass 7, count 0 2006.257.23:09:25.45#ibcon#wrote, iclass 7, count 0 2006.257.23:09:25.45#ibcon#about to read 3, iclass 7, count 0 2006.257.23:09:25.48#ibcon#read 3, iclass 7, count 0 2006.257.23:09:25.48#ibcon#about to read 4, iclass 7, count 0 2006.257.23:09:25.48#ibcon#read 4, iclass 7, count 0 2006.257.23:09:25.48#ibcon#about to read 5, iclass 7, count 0 2006.257.23:09:25.48#ibcon#read 5, iclass 7, count 0 2006.257.23:09:25.48#ibcon#about to read 6, iclass 7, count 0 2006.257.23:09:25.48#ibcon#read 6, iclass 7, count 0 2006.257.23:09:25.48#ibcon#end of sib2, iclass 7, count 0 2006.257.23:09:25.48#ibcon#*after write, iclass 7, count 0 2006.257.23:09:25.48#ibcon#*before return 0, iclass 7, count 0 2006.257.23:09:25.48#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:25.48#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:09:25.48#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.23:09:25.48#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.23:09:25.48$vck44/vblo=8,744.99 2006.257.23:09:25.48#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.23:09:25.48#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.23:09:25.48#ibcon#ireg 17 cls_cnt 0 2006.257.23:09:25.48#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:25.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:25.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:25.48#ibcon#enter wrdev, iclass 11, count 0 2006.257.23:09:25.48#ibcon#first serial, iclass 11, count 0 2006.257.23:09:25.48#ibcon#enter sib2, iclass 11, count 0 2006.257.23:09:25.48#ibcon#flushed, iclass 11, count 0 2006.257.23:09:25.48#ibcon#about to write, iclass 11, count 0 2006.257.23:09:25.48#ibcon#wrote, iclass 11, count 0 2006.257.23:09:25.48#ibcon#about to read 3, iclass 11, count 0 2006.257.23:09:25.50#ibcon#read 3, iclass 11, count 0 2006.257.23:09:25.50#ibcon#about to read 4, iclass 11, count 0 2006.257.23:09:25.50#ibcon#read 4, iclass 11, count 0 2006.257.23:09:25.50#ibcon#about to read 5, iclass 11, count 0 2006.257.23:09:25.50#ibcon#read 5, iclass 11, count 0 2006.257.23:09:25.50#ibcon#about to read 6, iclass 11, count 0 2006.257.23:09:25.50#ibcon#read 6, iclass 11, count 0 2006.257.23:09:25.50#ibcon#end of sib2, iclass 11, count 0 2006.257.23:09:25.50#ibcon#*mode == 0, iclass 11, count 0 2006.257.23:09:25.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.23:09:25.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:09:25.50#ibcon#*before write, iclass 11, count 0 2006.257.23:09:25.50#ibcon#enter sib2, iclass 11, count 0 2006.257.23:09:25.50#ibcon#flushed, iclass 11, count 0 2006.257.23:09:25.50#ibcon#about to write, iclass 11, count 0 2006.257.23:09:25.50#ibcon#wrote, iclass 11, count 0 2006.257.23:09:25.50#ibcon#about to read 3, iclass 11, count 0 2006.257.23:09:25.54#ibcon#read 3, iclass 11, count 0 2006.257.23:09:25.54#ibcon#about to read 4, iclass 11, count 0 2006.257.23:09:25.54#ibcon#read 4, iclass 11, count 0 2006.257.23:09:25.54#ibcon#about to read 5, iclass 11, count 0 2006.257.23:09:25.54#ibcon#read 5, iclass 11, count 0 2006.257.23:09:25.54#ibcon#about to read 6, iclass 11, count 0 2006.257.23:09:25.54#ibcon#read 6, iclass 11, count 0 2006.257.23:09:25.54#ibcon#end of sib2, iclass 11, count 0 2006.257.23:09:25.54#ibcon#*after write, iclass 11, count 0 2006.257.23:09:25.54#ibcon#*before return 0, iclass 11, count 0 2006.257.23:09:25.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:25.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:09:25.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.23:09:25.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.23:09:25.54$vck44/vb=8,4 2006.257.23:09:25.54#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.23:09:25.54#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.23:09:25.54#ibcon#ireg 11 cls_cnt 2 2006.257.23:09:25.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:25.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:25.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:25.60#ibcon#enter wrdev, iclass 13, count 2 2006.257.23:09:25.60#ibcon#first serial, iclass 13, count 2 2006.257.23:09:25.60#ibcon#enter sib2, iclass 13, count 2 2006.257.23:09:25.60#ibcon#flushed, iclass 13, count 2 2006.257.23:09:25.60#ibcon#about to write, iclass 13, count 2 2006.257.23:09:25.60#ibcon#wrote, iclass 13, count 2 2006.257.23:09:25.60#ibcon#about to read 3, iclass 13, count 2 2006.257.23:09:25.62#ibcon#read 3, iclass 13, count 2 2006.257.23:09:25.62#ibcon#about to read 4, iclass 13, count 2 2006.257.23:09:25.62#ibcon#read 4, iclass 13, count 2 2006.257.23:09:25.62#ibcon#about to read 5, iclass 13, count 2 2006.257.23:09:25.62#ibcon#read 5, iclass 13, count 2 2006.257.23:09:25.62#ibcon#about to read 6, iclass 13, count 2 2006.257.23:09:25.62#ibcon#read 6, iclass 13, count 2 2006.257.23:09:25.62#ibcon#end of sib2, iclass 13, count 2 2006.257.23:09:25.62#ibcon#*mode == 0, iclass 13, count 2 2006.257.23:09:25.62#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.23:09:25.62#ibcon#[27=AT08-04\r\n] 2006.257.23:09:25.62#ibcon#*before write, iclass 13, count 2 2006.257.23:09:25.62#ibcon#enter sib2, iclass 13, count 2 2006.257.23:09:25.62#ibcon#flushed, iclass 13, count 2 2006.257.23:09:25.62#ibcon#about to write, iclass 13, count 2 2006.257.23:09:25.62#ibcon#wrote, iclass 13, count 2 2006.257.23:09:25.62#ibcon#about to read 3, iclass 13, count 2 2006.257.23:09:25.65#ibcon#read 3, iclass 13, count 2 2006.257.23:09:25.65#ibcon#about to read 4, iclass 13, count 2 2006.257.23:09:25.65#ibcon#read 4, iclass 13, count 2 2006.257.23:09:25.65#ibcon#about to read 5, iclass 13, count 2 2006.257.23:09:25.65#ibcon#read 5, iclass 13, count 2 2006.257.23:09:25.65#ibcon#about to read 6, iclass 13, count 2 2006.257.23:09:25.65#ibcon#read 6, iclass 13, count 2 2006.257.23:09:25.65#ibcon#end of sib2, iclass 13, count 2 2006.257.23:09:25.65#ibcon#*after write, iclass 13, count 2 2006.257.23:09:25.65#ibcon#*before return 0, iclass 13, count 2 2006.257.23:09:25.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:25.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:09:25.65#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.23:09:25.65#ibcon#ireg 7 cls_cnt 0 2006.257.23:09:25.65#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:25.77#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:25.77#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:25.77#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:09:25.77#ibcon#first serial, iclass 13, count 0 2006.257.23:09:25.77#ibcon#enter sib2, iclass 13, count 0 2006.257.23:09:25.77#ibcon#flushed, iclass 13, count 0 2006.257.23:09:25.77#ibcon#about to write, iclass 13, count 0 2006.257.23:09:25.77#ibcon#wrote, iclass 13, count 0 2006.257.23:09:25.77#ibcon#about to read 3, iclass 13, count 0 2006.257.23:09:25.79#ibcon#read 3, iclass 13, count 0 2006.257.23:09:25.79#ibcon#about to read 4, iclass 13, count 0 2006.257.23:09:25.79#ibcon#read 4, iclass 13, count 0 2006.257.23:09:25.79#ibcon#about to read 5, iclass 13, count 0 2006.257.23:09:25.79#ibcon#read 5, iclass 13, count 0 2006.257.23:09:25.79#ibcon#about to read 6, iclass 13, count 0 2006.257.23:09:25.79#ibcon#read 6, iclass 13, count 0 2006.257.23:09:25.79#ibcon#end of sib2, iclass 13, count 0 2006.257.23:09:25.79#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:09:25.79#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:09:25.79#ibcon#[27=USB\r\n] 2006.257.23:09:25.79#ibcon#*before write, iclass 13, count 0 2006.257.23:09:25.79#ibcon#enter sib2, iclass 13, count 0 2006.257.23:09:25.79#ibcon#flushed, iclass 13, count 0 2006.257.23:09:25.79#ibcon#about to write, iclass 13, count 0 2006.257.23:09:25.79#ibcon#wrote, iclass 13, count 0 2006.257.23:09:25.79#ibcon#about to read 3, iclass 13, count 0 2006.257.23:09:25.82#ibcon#read 3, iclass 13, count 0 2006.257.23:09:25.82#ibcon#about to read 4, iclass 13, count 0 2006.257.23:09:25.82#ibcon#read 4, iclass 13, count 0 2006.257.23:09:25.82#ibcon#about to read 5, iclass 13, count 0 2006.257.23:09:25.82#ibcon#read 5, iclass 13, count 0 2006.257.23:09:25.82#ibcon#about to read 6, iclass 13, count 0 2006.257.23:09:25.82#ibcon#read 6, iclass 13, count 0 2006.257.23:09:25.82#ibcon#end of sib2, iclass 13, count 0 2006.257.23:09:25.82#ibcon#*after write, iclass 13, count 0 2006.257.23:09:25.82#ibcon#*before return 0, iclass 13, count 0 2006.257.23:09:25.82#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:25.82#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:09:25.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:09:25.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:09:25.82$vck44/vabw=wide 2006.257.23:09:25.82#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.23:09:25.82#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.23:09:25.82#ibcon#ireg 8 cls_cnt 0 2006.257.23:09:25.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:25.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:25.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:25.82#ibcon#enter wrdev, iclass 15, count 0 2006.257.23:09:25.82#ibcon#first serial, iclass 15, count 0 2006.257.23:09:25.82#ibcon#enter sib2, iclass 15, count 0 2006.257.23:09:25.82#ibcon#flushed, iclass 15, count 0 2006.257.23:09:25.82#ibcon#about to write, iclass 15, count 0 2006.257.23:09:25.82#ibcon#wrote, iclass 15, count 0 2006.257.23:09:25.82#ibcon#about to read 3, iclass 15, count 0 2006.257.23:09:25.84#ibcon#read 3, iclass 15, count 0 2006.257.23:09:25.84#ibcon#about to read 4, iclass 15, count 0 2006.257.23:09:25.84#ibcon#read 4, iclass 15, count 0 2006.257.23:09:25.84#ibcon#about to read 5, iclass 15, count 0 2006.257.23:09:25.84#ibcon#read 5, iclass 15, count 0 2006.257.23:09:25.84#ibcon#about to read 6, iclass 15, count 0 2006.257.23:09:25.84#ibcon#read 6, iclass 15, count 0 2006.257.23:09:25.84#ibcon#end of sib2, iclass 15, count 0 2006.257.23:09:25.84#ibcon#*mode == 0, iclass 15, count 0 2006.257.23:09:25.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.23:09:25.84#ibcon#[25=BW32\r\n] 2006.257.23:09:25.84#ibcon#*before write, iclass 15, count 0 2006.257.23:09:25.84#ibcon#enter sib2, iclass 15, count 0 2006.257.23:09:25.84#ibcon#flushed, iclass 15, count 0 2006.257.23:09:25.84#ibcon#about to write, iclass 15, count 0 2006.257.23:09:25.84#ibcon#wrote, iclass 15, count 0 2006.257.23:09:25.84#ibcon#about to read 3, iclass 15, count 0 2006.257.23:09:25.87#ibcon#read 3, iclass 15, count 0 2006.257.23:09:25.87#ibcon#about to read 4, iclass 15, count 0 2006.257.23:09:25.87#ibcon#read 4, iclass 15, count 0 2006.257.23:09:25.87#ibcon#about to read 5, iclass 15, count 0 2006.257.23:09:25.87#ibcon#read 5, iclass 15, count 0 2006.257.23:09:25.87#ibcon#about to read 6, iclass 15, count 0 2006.257.23:09:25.87#ibcon#read 6, iclass 15, count 0 2006.257.23:09:25.87#ibcon#end of sib2, iclass 15, count 0 2006.257.23:09:25.87#ibcon#*after write, iclass 15, count 0 2006.257.23:09:25.87#ibcon#*before return 0, iclass 15, count 0 2006.257.23:09:25.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:25.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:09:25.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.23:09:25.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.23:09:25.87$vck44/vbbw=wide 2006.257.23:09:25.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.23:09:25.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.23:09:25.87#ibcon#ireg 8 cls_cnt 0 2006.257.23:09:25.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:09:25.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:09:25.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:09:25.94#ibcon#enter wrdev, iclass 17, count 0 2006.257.23:09:25.94#ibcon#first serial, iclass 17, count 0 2006.257.23:09:25.94#ibcon#enter sib2, iclass 17, count 0 2006.257.23:09:25.94#ibcon#flushed, iclass 17, count 0 2006.257.23:09:25.94#ibcon#about to write, iclass 17, count 0 2006.257.23:09:25.94#ibcon#wrote, iclass 17, count 0 2006.257.23:09:25.94#ibcon#about to read 3, iclass 17, count 0 2006.257.23:09:25.96#ibcon#read 3, iclass 17, count 0 2006.257.23:09:25.96#ibcon#about to read 4, iclass 17, count 0 2006.257.23:09:25.96#ibcon#read 4, iclass 17, count 0 2006.257.23:09:25.96#ibcon#about to read 5, iclass 17, count 0 2006.257.23:09:25.96#ibcon#read 5, iclass 17, count 0 2006.257.23:09:25.96#ibcon#about to read 6, iclass 17, count 0 2006.257.23:09:25.96#ibcon#read 6, iclass 17, count 0 2006.257.23:09:25.96#ibcon#end of sib2, iclass 17, count 0 2006.257.23:09:25.96#ibcon#*mode == 0, iclass 17, count 0 2006.257.23:09:25.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.23:09:25.96#ibcon#[27=BW32\r\n] 2006.257.23:09:25.96#ibcon#*before write, iclass 17, count 0 2006.257.23:09:25.96#ibcon#enter sib2, iclass 17, count 0 2006.257.23:09:25.96#ibcon#flushed, iclass 17, count 0 2006.257.23:09:25.96#ibcon#about to write, iclass 17, count 0 2006.257.23:09:25.96#ibcon#wrote, iclass 17, count 0 2006.257.23:09:25.96#ibcon#about to read 3, iclass 17, count 0 2006.257.23:09:25.99#ibcon#read 3, iclass 17, count 0 2006.257.23:09:25.99#ibcon#about to read 4, iclass 17, count 0 2006.257.23:09:25.99#ibcon#read 4, iclass 17, count 0 2006.257.23:09:25.99#ibcon#about to read 5, iclass 17, count 0 2006.257.23:09:25.99#ibcon#read 5, iclass 17, count 0 2006.257.23:09:25.99#ibcon#about to read 6, iclass 17, count 0 2006.257.23:09:25.99#ibcon#read 6, iclass 17, count 0 2006.257.23:09:25.99#ibcon#end of sib2, iclass 17, count 0 2006.257.23:09:25.99#ibcon#*after write, iclass 17, count 0 2006.257.23:09:25.99#ibcon#*before return 0, iclass 17, count 0 2006.257.23:09:25.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:09:25.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:09:25.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.23:09:25.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.23:09:25.99$setupk4/ifdk4 2006.257.23:09:25.99$ifdk4/lo= 2006.257.23:09:25.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:09:25.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:09:25.99$ifdk4/patch= 2006.257.23:09:25.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:09:25.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:09:25.99$setupk4/!*+20s 2006.257.23:09:33.38#abcon#<5=/14 1.0 2.8 20.25 831016.0\r\n> 2006.257.23:09:33.40#abcon#{5=INTERFACE CLEAR} 2006.257.23:09:33.46#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:09:40.50$setupk4/"tpicd 2006.257.23:09:40.50$setupk4/echo=off 2006.257.23:09:40.50$setupk4/xlog=off 2006.257.23:09:40.50:!2006.257.23:10:58 2006.257.23:09:42.14#trakl#Source acquired 2006.257.23:09:43.14#flagr#flagr/antenna,acquired 2006.257.23:10:58.00:preob 2006.257.23:10:59.14/onsource/TRACKING 2006.257.23:10:59.14:!2006.257.23:11:08 2006.257.23:11:08.00:"tape 2006.257.23:11:08.00:"st=record 2006.257.23:11:08.00:data_valid=on 2006.257.23:11:08.00:midob 2006.257.23:11:08.14/onsource/TRACKING 2006.257.23:11:08.14/wx/20.30,1016.0,81 2006.257.23:11:08.20/cable/+6.4826E-03 2006.257.23:11:09.29/va/01,08,usb,yes,31,33 2006.257.23:11:09.29/va/02,07,usb,yes,33,34 2006.257.23:11:09.29/va/03,08,usb,yes,30,31 2006.257.23:11:09.29/va/04,07,usb,yes,34,36 2006.257.23:11:09.29/va/05,04,usb,yes,30,31 2006.257.23:11:09.29/va/06,04,usb,yes,34,34 2006.257.23:11:09.29/va/07,04,usb,yes,35,35 2006.257.23:11:09.29/va/08,04,usb,yes,29,36 2006.257.23:11:09.52/valo/01,524.99,yes,locked 2006.257.23:11:09.52/valo/02,534.99,yes,locked 2006.257.23:11:09.52/valo/03,564.99,yes,locked 2006.257.23:11:09.52/valo/04,624.99,yes,locked 2006.257.23:11:09.52/valo/05,734.99,yes,locked 2006.257.23:11:09.52/valo/06,814.99,yes,locked 2006.257.23:11:09.52/valo/07,864.99,yes,locked 2006.257.23:11:09.52/valo/08,884.99,yes,locked 2006.257.23:11:10.61/vb/01,04,usb,yes,30,28 2006.257.23:11:10.61/vb/02,05,usb,yes,29,29 2006.257.23:11:10.61/vb/03,04,usb,yes,30,33 2006.257.23:11:10.61/vb/04,05,usb,yes,30,29 2006.257.23:11:10.61/vb/05,04,usb,yes,26,29 2006.257.23:11:10.61/vb/06,04,usb,yes,31,27 2006.257.23:11:10.61/vb/07,04,usb,yes,31,31 2006.257.23:11:10.61/vb/08,04,usb,yes,28,31 2006.257.23:11:10.84/vblo/01,629.99,yes,locked 2006.257.23:11:10.84/vblo/02,634.99,yes,locked 2006.257.23:11:10.84/vblo/03,649.99,yes,locked 2006.257.23:11:10.84/vblo/04,679.99,yes,locked 2006.257.23:11:10.84/vblo/05,709.99,yes,locked 2006.257.23:11:10.84/vblo/06,719.99,yes,locked 2006.257.23:11:10.84/vblo/07,734.99,yes,locked 2006.257.23:11:10.84/vblo/08,744.99,yes,locked 2006.257.23:11:10.99/vabw/8 2006.257.23:11:11.14/vbbw/8 2006.257.23:11:11.23/xfe/off,on,15.2 2006.257.23:11:11.60/ifatt/23,28,28,28 2006.257.23:11:12.07/fmout-gps/S +4.52E-07 2006.257.23:11:12.11:!2006.257.23:12:08 2006.257.23:12:08.01:data_valid=off 2006.257.23:12:08.01:"et 2006.257.23:12:08.01:!+3s 2006.257.23:12:11.02:"tape 2006.257.23:12:11.02:postob 2006.257.23:12:11.16/cable/+6.4842E-03 2006.257.23:12:11.16/wx/20.33,1016.0,83 2006.257.23:12:12.07/fmout-gps/S +4.51E-07 2006.257.23:12:12.07:scan_name=257-2314,jd0609,90 2006.257.23:12:12.07:source=3c274,123049.42,122328.0,2000.0,ccw 2006.257.23:12:12.14#flagr#flagr/antenna,new-source 2006.257.23:12:13.14:checkk5 2006.257.23:12:13.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:12:13.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:12:14.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:12:14.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:12:14.84/chk_obsdata//k5ts1/T2572311??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.23:12:15.17/chk_obsdata//k5ts2/T2572311??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.23:12:15.51/chk_obsdata//k5ts3/T2572311??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.23:12:15.85/chk_obsdata//k5ts4/T2572311??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.23:12:16.51/k5log//k5ts1_log_newline 2006.257.23:12:17.17/k5log//k5ts2_log_newline 2006.257.23:12:17.82/k5log//k5ts3_log_newline 2006.257.23:12:18.47/k5log//k5ts4_log_newline 2006.257.23:12:18.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:12:18.49:setupk4=1 2006.257.23:12:18.49$setupk4/echo=on 2006.257.23:12:18.49$setupk4/pcalon 2006.257.23:12:18.49$pcalon/"no phase cal control is implemented here 2006.257.23:12:18.49$setupk4/"tpicd=stop 2006.257.23:12:18.49$setupk4/"rec=synch_on 2006.257.23:12:18.49$setupk4/"rec_mode=128 2006.257.23:12:18.49$setupk4/!* 2006.257.23:12:18.49$setupk4/recpk4 2006.257.23:12:18.49$recpk4/recpatch= 2006.257.23:12:18.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:12:18.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:12:18.49$setupk4/vck44 2006.257.23:12:18.49$vck44/valo=1,524.99 2006.257.23:12:18.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.23:12:18.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.23:12:18.49#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:18.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:18.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:18.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:18.49#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:12:18.49#ibcon#first serial, iclass 18, count 0 2006.257.23:12:18.49#ibcon#enter sib2, iclass 18, count 0 2006.257.23:12:18.49#ibcon#flushed, iclass 18, count 0 2006.257.23:12:18.49#ibcon#about to write, iclass 18, count 0 2006.257.23:12:18.49#ibcon#wrote, iclass 18, count 0 2006.257.23:12:18.49#ibcon#about to read 3, iclass 18, count 0 2006.257.23:12:18.51#ibcon#read 3, iclass 18, count 0 2006.257.23:12:18.51#ibcon#about to read 4, iclass 18, count 0 2006.257.23:12:18.51#ibcon#read 4, iclass 18, count 0 2006.257.23:12:18.51#ibcon#about to read 5, iclass 18, count 0 2006.257.23:12:18.51#ibcon#read 5, iclass 18, count 0 2006.257.23:12:18.51#ibcon#about to read 6, iclass 18, count 0 2006.257.23:12:18.51#ibcon#read 6, iclass 18, count 0 2006.257.23:12:18.51#ibcon#end of sib2, iclass 18, count 0 2006.257.23:12:18.51#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:12:18.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:12:18.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:12:18.51#ibcon#*before write, iclass 18, count 0 2006.257.23:12:18.51#ibcon#enter sib2, iclass 18, count 0 2006.257.23:12:18.51#ibcon#flushed, iclass 18, count 0 2006.257.23:12:18.51#ibcon#about to write, iclass 18, count 0 2006.257.23:12:18.51#ibcon#wrote, iclass 18, count 0 2006.257.23:12:18.51#ibcon#about to read 3, iclass 18, count 0 2006.257.23:12:18.56#ibcon#read 3, iclass 18, count 0 2006.257.23:12:18.56#ibcon#about to read 4, iclass 18, count 0 2006.257.23:12:18.56#ibcon#read 4, iclass 18, count 0 2006.257.23:12:18.56#ibcon#about to read 5, iclass 18, count 0 2006.257.23:12:18.56#ibcon#read 5, iclass 18, count 0 2006.257.23:12:18.56#ibcon#about to read 6, iclass 18, count 0 2006.257.23:12:18.56#ibcon#read 6, iclass 18, count 0 2006.257.23:12:18.56#ibcon#end of sib2, iclass 18, count 0 2006.257.23:12:18.56#ibcon#*after write, iclass 18, count 0 2006.257.23:12:18.56#ibcon#*before return 0, iclass 18, count 0 2006.257.23:12:18.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:18.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:18.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:12:18.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:12:18.56$vck44/va=1,8 2006.257.23:12:18.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.23:12:18.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.23:12:18.56#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:18.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:18.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:18.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:18.56#ibcon#enter wrdev, iclass 20, count 2 2006.257.23:12:18.56#ibcon#first serial, iclass 20, count 2 2006.257.23:12:18.56#ibcon#enter sib2, iclass 20, count 2 2006.257.23:12:18.56#ibcon#flushed, iclass 20, count 2 2006.257.23:12:18.56#ibcon#about to write, iclass 20, count 2 2006.257.23:12:18.56#ibcon#wrote, iclass 20, count 2 2006.257.23:12:18.56#ibcon#about to read 3, iclass 20, count 2 2006.257.23:12:18.58#ibcon#read 3, iclass 20, count 2 2006.257.23:12:18.58#ibcon#about to read 4, iclass 20, count 2 2006.257.23:12:18.58#ibcon#read 4, iclass 20, count 2 2006.257.23:12:18.58#ibcon#about to read 5, iclass 20, count 2 2006.257.23:12:18.58#ibcon#read 5, iclass 20, count 2 2006.257.23:12:18.58#ibcon#about to read 6, iclass 20, count 2 2006.257.23:12:18.58#ibcon#read 6, iclass 20, count 2 2006.257.23:12:18.58#ibcon#end of sib2, iclass 20, count 2 2006.257.23:12:18.58#ibcon#*mode == 0, iclass 20, count 2 2006.257.23:12:18.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.23:12:18.58#ibcon#[25=AT01-08\r\n] 2006.257.23:12:18.58#ibcon#*before write, iclass 20, count 2 2006.257.23:12:18.58#ibcon#enter sib2, iclass 20, count 2 2006.257.23:12:18.58#ibcon#flushed, iclass 20, count 2 2006.257.23:12:18.58#ibcon#about to write, iclass 20, count 2 2006.257.23:12:18.58#ibcon#wrote, iclass 20, count 2 2006.257.23:12:18.58#ibcon#about to read 3, iclass 20, count 2 2006.257.23:12:18.61#ibcon#read 3, iclass 20, count 2 2006.257.23:12:18.61#ibcon#about to read 4, iclass 20, count 2 2006.257.23:12:18.61#ibcon#read 4, iclass 20, count 2 2006.257.23:12:18.61#ibcon#about to read 5, iclass 20, count 2 2006.257.23:12:18.61#ibcon#read 5, iclass 20, count 2 2006.257.23:12:18.61#ibcon#about to read 6, iclass 20, count 2 2006.257.23:12:18.61#ibcon#read 6, iclass 20, count 2 2006.257.23:12:18.61#ibcon#end of sib2, iclass 20, count 2 2006.257.23:12:18.61#ibcon#*after write, iclass 20, count 2 2006.257.23:12:18.61#ibcon#*before return 0, iclass 20, count 2 2006.257.23:12:18.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:18.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:18.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.23:12:18.61#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:18.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:18.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:18.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:18.73#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:12:18.73#ibcon#first serial, iclass 20, count 0 2006.257.23:12:18.73#ibcon#enter sib2, iclass 20, count 0 2006.257.23:12:18.73#ibcon#flushed, iclass 20, count 0 2006.257.23:12:18.73#ibcon#about to write, iclass 20, count 0 2006.257.23:12:18.73#ibcon#wrote, iclass 20, count 0 2006.257.23:12:18.73#ibcon#about to read 3, iclass 20, count 0 2006.257.23:12:18.75#ibcon#read 3, iclass 20, count 0 2006.257.23:12:18.75#ibcon#about to read 4, iclass 20, count 0 2006.257.23:12:18.75#ibcon#read 4, iclass 20, count 0 2006.257.23:12:18.75#ibcon#about to read 5, iclass 20, count 0 2006.257.23:12:18.75#ibcon#read 5, iclass 20, count 0 2006.257.23:12:18.75#ibcon#about to read 6, iclass 20, count 0 2006.257.23:12:18.75#ibcon#read 6, iclass 20, count 0 2006.257.23:12:18.75#ibcon#end of sib2, iclass 20, count 0 2006.257.23:12:18.75#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:12:18.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:12:18.75#ibcon#[25=USB\r\n] 2006.257.23:12:18.75#ibcon#*before write, iclass 20, count 0 2006.257.23:12:18.75#ibcon#enter sib2, iclass 20, count 0 2006.257.23:12:18.75#ibcon#flushed, iclass 20, count 0 2006.257.23:12:18.75#ibcon#about to write, iclass 20, count 0 2006.257.23:12:18.75#ibcon#wrote, iclass 20, count 0 2006.257.23:12:18.75#ibcon#about to read 3, iclass 20, count 0 2006.257.23:12:18.78#ibcon#read 3, iclass 20, count 0 2006.257.23:12:18.78#ibcon#about to read 4, iclass 20, count 0 2006.257.23:12:18.78#ibcon#read 4, iclass 20, count 0 2006.257.23:12:18.78#ibcon#about to read 5, iclass 20, count 0 2006.257.23:12:18.78#ibcon#read 5, iclass 20, count 0 2006.257.23:12:18.78#ibcon#about to read 6, iclass 20, count 0 2006.257.23:12:18.78#ibcon#read 6, iclass 20, count 0 2006.257.23:12:18.78#ibcon#end of sib2, iclass 20, count 0 2006.257.23:12:18.78#ibcon#*after write, iclass 20, count 0 2006.257.23:12:18.78#ibcon#*before return 0, iclass 20, count 0 2006.257.23:12:18.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:18.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:18.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:12:18.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:12:18.78$vck44/valo=2,534.99 2006.257.23:12:18.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.23:12:18.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.23:12:18.78#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:18.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:18.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:18.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:18.78#ibcon#enter wrdev, iclass 22, count 0 2006.257.23:12:18.78#ibcon#first serial, iclass 22, count 0 2006.257.23:12:18.78#ibcon#enter sib2, iclass 22, count 0 2006.257.23:12:18.78#ibcon#flushed, iclass 22, count 0 2006.257.23:12:18.78#ibcon#about to write, iclass 22, count 0 2006.257.23:12:18.78#ibcon#wrote, iclass 22, count 0 2006.257.23:12:18.78#ibcon#about to read 3, iclass 22, count 0 2006.257.23:12:18.80#ibcon#read 3, iclass 22, count 0 2006.257.23:12:18.80#ibcon#about to read 4, iclass 22, count 0 2006.257.23:12:18.80#ibcon#read 4, iclass 22, count 0 2006.257.23:12:18.80#ibcon#about to read 5, iclass 22, count 0 2006.257.23:12:18.80#ibcon#read 5, iclass 22, count 0 2006.257.23:12:18.80#ibcon#about to read 6, iclass 22, count 0 2006.257.23:12:18.80#ibcon#read 6, iclass 22, count 0 2006.257.23:12:18.80#ibcon#end of sib2, iclass 22, count 0 2006.257.23:12:18.80#ibcon#*mode == 0, iclass 22, count 0 2006.257.23:12:18.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.23:12:18.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:12:18.80#ibcon#*before write, iclass 22, count 0 2006.257.23:12:18.80#ibcon#enter sib2, iclass 22, count 0 2006.257.23:12:18.80#ibcon#flushed, iclass 22, count 0 2006.257.23:12:18.80#ibcon#about to write, iclass 22, count 0 2006.257.23:12:18.80#ibcon#wrote, iclass 22, count 0 2006.257.23:12:18.80#ibcon#about to read 3, iclass 22, count 0 2006.257.23:12:18.84#ibcon#read 3, iclass 22, count 0 2006.257.23:12:18.84#ibcon#about to read 4, iclass 22, count 0 2006.257.23:12:18.84#ibcon#read 4, iclass 22, count 0 2006.257.23:12:18.84#ibcon#about to read 5, iclass 22, count 0 2006.257.23:12:18.84#ibcon#read 5, iclass 22, count 0 2006.257.23:12:18.84#ibcon#about to read 6, iclass 22, count 0 2006.257.23:12:18.84#ibcon#read 6, iclass 22, count 0 2006.257.23:12:18.84#ibcon#end of sib2, iclass 22, count 0 2006.257.23:12:18.84#ibcon#*after write, iclass 22, count 0 2006.257.23:12:18.84#ibcon#*before return 0, iclass 22, count 0 2006.257.23:12:18.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:18.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:18.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.23:12:18.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.23:12:18.84$vck44/va=2,7 2006.257.23:12:18.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.23:12:18.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.23:12:18.84#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:18.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:18.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:18.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:18.90#ibcon#enter wrdev, iclass 24, count 2 2006.257.23:12:18.90#ibcon#first serial, iclass 24, count 2 2006.257.23:12:18.90#ibcon#enter sib2, iclass 24, count 2 2006.257.23:12:18.90#ibcon#flushed, iclass 24, count 2 2006.257.23:12:18.90#ibcon#about to write, iclass 24, count 2 2006.257.23:12:18.90#ibcon#wrote, iclass 24, count 2 2006.257.23:12:18.90#ibcon#about to read 3, iclass 24, count 2 2006.257.23:12:18.92#ibcon#read 3, iclass 24, count 2 2006.257.23:12:18.92#ibcon#about to read 4, iclass 24, count 2 2006.257.23:12:18.92#ibcon#read 4, iclass 24, count 2 2006.257.23:12:18.92#ibcon#about to read 5, iclass 24, count 2 2006.257.23:12:18.92#ibcon#read 5, iclass 24, count 2 2006.257.23:12:18.92#ibcon#about to read 6, iclass 24, count 2 2006.257.23:12:18.92#ibcon#read 6, iclass 24, count 2 2006.257.23:12:18.92#ibcon#end of sib2, iclass 24, count 2 2006.257.23:12:18.92#ibcon#*mode == 0, iclass 24, count 2 2006.257.23:12:18.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.23:12:18.92#ibcon#[25=AT02-07\r\n] 2006.257.23:12:18.92#ibcon#*before write, iclass 24, count 2 2006.257.23:12:18.92#ibcon#enter sib2, iclass 24, count 2 2006.257.23:12:18.92#ibcon#flushed, iclass 24, count 2 2006.257.23:12:18.92#ibcon#about to write, iclass 24, count 2 2006.257.23:12:18.92#ibcon#wrote, iclass 24, count 2 2006.257.23:12:18.92#ibcon#about to read 3, iclass 24, count 2 2006.257.23:12:18.95#ibcon#read 3, iclass 24, count 2 2006.257.23:12:18.95#ibcon#about to read 4, iclass 24, count 2 2006.257.23:12:18.95#ibcon#read 4, iclass 24, count 2 2006.257.23:12:18.95#ibcon#about to read 5, iclass 24, count 2 2006.257.23:12:18.95#ibcon#read 5, iclass 24, count 2 2006.257.23:12:18.95#ibcon#about to read 6, iclass 24, count 2 2006.257.23:12:18.95#ibcon#read 6, iclass 24, count 2 2006.257.23:12:18.95#ibcon#end of sib2, iclass 24, count 2 2006.257.23:12:18.95#ibcon#*after write, iclass 24, count 2 2006.257.23:12:18.95#ibcon#*before return 0, iclass 24, count 2 2006.257.23:12:18.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:18.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:18.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.23:12:18.95#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:18.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:19.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:19.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:19.07#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:12:19.07#ibcon#first serial, iclass 24, count 0 2006.257.23:12:19.07#ibcon#enter sib2, iclass 24, count 0 2006.257.23:12:19.07#ibcon#flushed, iclass 24, count 0 2006.257.23:12:19.07#ibcon#about to write, iclass 24, count 0 2006.257.23:12:19.07#ibcon#wrote, iclass 24, count 0 2006.257.23:12:19.07#ibcon#about to read 3, iclass 24, count 0 2006.257.23:12:19.09#ibcon#read 3, iclass 24, count 0 2006.257.23:12:19.09#ibcon#about to read 4, iclass 24, count 0 2006.257.23:12:19.09#ibcon#read 4, iclass 24, count 0 2006.257.23:12:19.09#ibcon#about to read 5, iclass 24, count 0 2006.257.23:12:19.09#ibcon#read 5, iclass 24, count 0 2006.257.23:12:19.09#ibcon#about to read 6, iclass 24, count 0 2006.257.23:12:19.09#ibcon#read 6, iclass 24, count 0 2006.257.23:12:19.09#ibcon#end of sib2, iclass 24, count 0 2006.257.23:12:19.09#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:12:19.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:12:19.09#ibcon#[25=USB\r\n] 2006.257.23:12:19.09#ibcon#*before write, iclass 24, count 0 2006.257.23:12:19.09#ibcon#enter sib2, iclass 24, count 0 2006.257.23:12:19.09#ibcon#flushed, iclass 24, count 0 2006.257.23:12:19.09#ibcon#about to write, iclass 24, count 0 2006.257.23:12:19.09#ibcon#wrote, iclass 24, count 0 2006.257.23:12:19.09#ibcon#about to read 3, iclass 24, count 0 2006.257.23:12:19.12#ibcon#read 3, iclass 24, count 0 2006.257.23:12:19.12#ibcon#about to read 4, iclass 24, count 0 2006.257.23:12:19.12#ibcon#read 4, iclass 24, count 0 2006.257.23:12:19.12#ibcon#about to read 5, iclass 24, count 0 2006.257.23:12:19.12#ibcon#read 5, iclass 24, count 0 2006.257.23:12:19.12#ibcon#about to read 6, iclass 24, count 0 2006.257.23:12:19.12#ibcon#read 6, iclass 24, count 0 2006.257.23:12:19.12#ibcon#end of sib2, iclass 24, count 0 2006.257.23:12:19.12#ibcon#*after write, iclass 24, count 0 2006.257.23:12:19.12#ibcon#*before return 0, iclass 24, count 0 2006.257.23:12:19.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:19.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:19.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:12:19.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:12:19.12$vck44/valo=3,564.99 2006.257.23:12:19.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.23:12:19.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.23:12:19.12#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:19.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:19.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:19.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:19.12#ibcon#enter wrdev, iclass 26, count 0 2006.257.23:12:19.12#ibcon#first serial, iclass 26, count 0 2006.257.23:12:19.12#ibcon#enter sib2, iclass 26, count 0 2006.257.23:12:19.12#ibcon#flushed, iclass 26, count 0 2006.257.23:12:19.12#ibcon#about to write, iclass 26, count 0 2006.257.23:12:19.12#ibcon#wrote, iclass 26, count 0 2006.257.23:12:19.12#ibcon#about to read 3, iclass 26, count 0 2006.257.23:12:19.14#ibcon#read 3, iclass 26, count 0 2006.257.23:12:19.14#ibcon#about to read 4, iclass 26, count 0 2006.257.23:12:19.14#ibcon#read 4, iclass 26, count 0 2006.257.23:12:19.14#ibcon#about to read 5, iclass 26, count 0 2006.257.23:12:19.14#ibcon#read 5, iclass 26, count 0 2006.257.23:12:19.14#ibcon#about to read 6, iclass 26, count 0 2006.257.23:12:19.14#ibcon#read 6, iclass 26, count 0 2006.257.23:12:19.14#ibcon#end of sib2, iclass 26, count 0 2006.257.23:12:19.14#ibcon#*mode == 0, iclass 26, count 0 2006.257.23:12:19.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.23:12:19.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:12:19.14#ibcon#*before write, iclass 26, count 0 2006.257.23:12:19.14#ibcon#enter sib2, iclass 26, count 0 2006.257.23:12:19.14#ibcon#flushed, iclass 26, count 0 2006.257.23:12:19.14#ibcon#about to write, iclass 26, count 0 2006.257.23:12:19.14#ibcon#wrote, iclass 26, count 0 2006.257.23:12:19.14#ibcon#about to read 3, iclass 26, count 0 2006.257.23:12:19.18#ibcon#read 3, iclass 26, count 0 2006.257.23:12:19.18#ibcon#about to read 4, iclass 26, count 0 2006.257.23:12:19.18#ibcon#read 4, iclass 26, count 0 2006.257.23:12:19.18#ibcon#about to read 5, iclass 26, count 0 2006.257.23:12:19.18#ibcon#read 5, iclass 26, count 0 2006.257.23:12:19.18#ibcon#about to read 6, iclass 26, count 0 2006.257.23:12:19.18#ibcon#read 6, iclass 26, count 0 2006.257.23:12:19.18#ibcon#end of sib2, iclass 26, count 0 2006.257.23:12:19.18#ibcon#*after write, iclass 26, count 0 2006.257.23:12:19.18#ibcon#*before return 0, iclass 26, count 0 2006.257.23:12:19.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:19.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:19.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.23:12:19.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.23:12:19.18$vck44/va=3,8 2006.257.23:12:19.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.23:12:19.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.23:12:19.18#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:19.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:19.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:19.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:19.24#ibcon#enter wrdev, iclass 28, count 2 2006.257.23:12:19.24#ibcon#first serial, iclass 28, count 2 2006.257.23:12:19.24#ibcon#enter sib2, iclass 28, count 2 2006.257.23:12:19.24#ibcon#flushed, iclass 28, count 2 2006.257.23:12:19.24#ibcon#about to write, iclass 28, count 2 2006.257.23:12:19.24#ibcon#wrote, iclass 28, count 2 2006.257.23:12:19.24#ibcon#about to read 3, iclass 28, count 2 2006.257.23:12:19.26#ibcon#read 3, iclass 28, count 2 2006.257.23:12:19.26#ibcon#about to read 4, iclass 28, count 2 2006.257.23:12:19.26#ibcon#read 4, iclass 28, count 2 2006.257.23:12:19.26#ibcon#about to read 5, iclass 28, count 2 2006.257.23:12:19.26#ibcon#read 5, iclass 28, count 2 2006.257.23:12:19.26#ibcon#about to read 6, iclass 28, count 2 2006.257.23:12:19.26#ibcon#read 6, iclass 28, count 2 2006.257.23:12:19.26#ibcon#end of sib2, iclass 28, count 2 2006.257.23:12:19.26#ibcon#*mode == 0, iclass 28, count 2 2006.257.23:12:19.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.23:12:19.26#ibcon#[25=AT03-08\r\n] 2006.257.23:12:19.26#ibcon#*before write, iclass 28, count 2 2006.257.23:12:19.26#ibcon#enter sib2, iclass 28, count 2 2006.257.23:12:19.26#ibcon#flushed, iclass 28, count 2 2006.257.23:12:19.26#ibcon#about to write, iclass 28, count 2 2006.257.23:12:19.26#ibcon#wrote, iclass 28, count 2 2006.257.23:12:19.26#ibcon#about to read 3, iclass 28, count 2 2006.257.23:12:19.29#ibcon#read 3, iclass 28, count 2 2006.257.23:12:19.29#ibcon#about to read 4, iclass 28, count 2 2006.257.23:12:19.29#ibcon#read 4, iclass 28, count 2 2006.257.23:12:19.29#ibcon#about to read 5, iclass 28, count 2 2006.257.23:12:19.29#ibcon#read 5, iclass 28, count 2 2006.257.23:12:19.29#ibcon#about to read 6, iclass 28, count 2 2006.257.23:12:19.29#ibcon#read 6, iclass 28, count 2 2006.257.23:12:19.29#ibcon#end of sib2, iclass 28, count 2 2006.257.23:12:19.29#ibcon#*after write, iclass 28, count 2 2006.257.23:12:19.29#ibcon#*before return 0, iclass 28, count 2 2006.257.23:12:19.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:19.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:19.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.23:12:19.29#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:19.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:19.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:19.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:19.41#ibcon#enter wrdev, iclass 28, count 0 2006.257.23:12:19.41#ibcon#first serial, iclass 28, count 0 2006.257.23:12:19.41#ibcon#enter sib2, iclass 28, count 0 2006.257.23:12:19.41#ibcon#flushed, iclass 28, count 0 2006.257.23:12:19.41#ibcon#about to write, iclass 28, count 0 2006.257.23:12:19.41#ibcon#wrote, iclass 28, count 0 2006.257.23:12:19.41#ibcon#about to read 3, iclass 28, count 0 2006.257.23:12:19.43#ibcon#read 3, iclass 28, count 0 2006.257.23:12:19.43#ibcon#about to read 4, iclass 28, count 0 2006.257.23:12:19.43#ibcon#read 4, iclass 28, count 0 2006.257.23:12:19.43#ibcon#about to read 5, iclass 28, count 0 2006.257.23:12:19.43#ibcon#read 5, iclass 28, count 0 2006.257.23:12:19.43#ibcon#about to read 6, iclass 28, count 0 2006.257.23:12:19.43#ibcon#read 6, iclass 28, count 0 2006.257.23:12:19.43#ibcon#end of sib2, iclass 28, count 0 2006.257.23:12:19.43#ibcon#*mode == 0, iclass 28, count 0 2006.257.23:12:19.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.23:12:19.43#ibcon#[25=USB\r\n] 2006.257.23:12:19.43#ibcon#*before write, iclass 28, count 0 2006.257.23:12:19.43#ibcon#enter sib2, iclass 28, count 0 2006.257.23:12:19.43#ibcon#flushed, iclass 28, count 0 2006.257.23:12:19.43#ibcon#about to write, iclass 28, count 0 2006.257.23:12:19.43#ibcon#wrote, iclass 28, count 0 2006.257.23:12:19.43#ibcon#about to read 3, iclass 28, count 0 2006.257.23:12:19.46#ibcon#read 3, iclass 28, count 0 2006.257.23:12:19.46#ibcon#about to read 4, iclass 28, count 0 2006.257.23:12:19.46#ibcon#read 4, iclass 28, count 0 2006.257.23:12:19.46#ibcon#about to read 5, iclass 28, count 0 2006.257.23:12:19.46#ibcon#read 5, iclass 28, count 0 2006.257.23:12:19.46#ibcon#about to read 6, iclass 28, count 0 2006.257.23:12:19.46#ibcon#read 6, iclass 28, count 0 2006.257.23:12:19.46#ibcon#end of sib2, iclass 28, count 0 2006.257.23:12:19.46#ibcon#*after write, iclass 28, count 0 2006.257.23:12:19.46#ibcon#*before return 0, iclass 28, count 0 2006.257.23:12:19.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:19.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:19.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.23:12:19.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.23:12:19.46$vck44/valo=4,624.99 2006.257.23:12:19.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.23:12:19.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.23:12:19.46#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:19.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:19.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:19.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:19.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:12:19.46#ibcon#first serial, iclass 30, count 0 2006.257.23:12:19.46#ibcon#enter sib2, iclass 30, count 0 2006.257.23:12:19.46#ibcon#flushed, iclass 30, count 0 2006.257.23:12:19.46#ibcon#about to write, iclass 30, count 0 2006.257.23:12:19.46#ibcon#wrote, iclass 30, count 0 2006.257.23:12:19.46#ibcon#about to read 3, iclass 30, count 0 2006.257.23:12:19.48#ibcon#read 3, iclass 30, count 0 2006.257.23:12:19.48#ibcon#about to read 4, iclass 30, count 0 2006.257.23:12:19.48#ibcon#read 4, iclass 30, count 0 2006.257.23:12:19.48#ibcon#about to read 5, iclass 30, count 0 2006.257.23:12:19.48#ibcon#read 5, iclass 30, count 0 2006.257.23:12:19.48#ibcon#about to read 6, iclass 30, count 0 2006.257.23:12:19.48#ibcon#read 6, iclass 30, count 0 2006.257.23:12:19.48#ibcon#end of sib2, iclass 30, count 0 2006.257.23:12:19.48#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:12:19.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:12:19.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:12:19.48#ibcon#*before write, iclass 30, count 0 2006.257.23:12:19.48#ibcon#enter sib2, iclass 30, count 0 2006.257.23:12:19.48#ibcon#flushed, iclass 30, count 0 2006.257.23:12:19.48#ibcon#about to write, iclass 30, count 0 2006.257.23:12:19.48#ibcon#wrote, iclass 30, count 0 2006.257.23:12:19.48#ibcon#about to read 3, iclass 30, count 0 2006.257.23:12:19.52#ibcon#read 3, iclass 30, count 0 2006.257.23:12:19.52#ibcon#about to read 4, iclass 30, count 0 2006.257.23:12:19.52#ibcon#read 4, iclass 30, count 0 2006.257.23:12:19.52#ibcon#about to read 5, iclass 30, count 0 2006.257.23:12:19.52#ibcon#read 5, iclass 30, count 0 2006.257.23:12:19.52#ibcon#about to read 6, iclass 30, count 0 2006.257.23:12:19.52#ibcon#read 6, iclass 30, count 0 2006.257.23:12:19.52#ibcon#end of sib2, iclass 30, count 0 2006.257.23:12:19.52#ibcon#*after write, iclass 30, count 0 2006.257.23:12:19.52#ibcon#*before return 0, iclass 30, count 0 2006.257.23:12:19.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:19.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:19.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:12:19.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:12:19.52$vck44/va=4,7 2006.257.23:12:19.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.23:12:19.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.23:12:19.52#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:19.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:19.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:19.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:19.58#ibcon#enter wrdev, iclass 32, count 2 2006.257.23:12:19.58#ibcon#first serial, iclass 32, count 2 2006.257.23:12:19.58#ibcon#enter sib2, iclass 32, count 2 2006.257.23:12:19.58#ibcon#flushed, iclass 32, count 2 2006.257.23:12:19.58#ibcon#about to write, iclass 32, count 2 2006.257.23:12:19.58#ibcon#wrote, iclass 32, count 2 2006.257.23:12:19.58#ibcon#about to read 3, iclass 32, count 2 2006.257.23:12:19.60#ibcon#read 3, iclass 32, count 2 2006.257.23:12:19.60#ibcon#about to read 4, iclass 32, count 2 2006.257.23:12:19.60#ibcon#read 4, iclass 32, count 2 2006.257.23:12:19.60#ibcon#about to read 5, iclass 32, count 2 2006.257.23:12:19.60#ibcon#read 5, iclass 32, count 2 2006.257.23:12:19.60#ibcon#about to read 6, iclass 32, count 2 2006.257.23:12:19.60#ibcon#read 6, iclass 32, count 2 2006.257.23:12:19.60#ibcon#end of sib2, iclass 32, count 2 2006.257.23:12:19.60#ibcon#*mode == 0, iclass 32, count 2 2006.257.23:12:19.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.23:12:19.60#ibcon#[25=AT04-07\r\n] 2006.257.23:12:19.60#ibcon#*before write, iclass 32, count 2 2006.257.23:12:19.60#ibcon#enter sib2, iclass 32, count 2 2006.257.23:12:19.60#ibcon#flushed, iclass 32, count 2 2006.257.23:12:19.60#ibcon#about to write, iclass 32, count 2 2006.257.23:12:19.60#ibcon#wrote, iclass 32, count 2 2006.257.23:12:19.60#ibcon#about to read 3, iclass 32, count 2 2006.257.23:12:19.63#ibcon#read 3, iclass 32, count 2 2006.257.23:12:19.63#ibcon#about to read 4, iclass 32, count 2 2006.257.23:12:19.63#ibcon#read 4, iclass 32, count 2 2006.257.23:12:19.63#ibcon#about to read 5, iclass 32, count 2 2006.257.23:12:19.63#ibcon#read 5, iclass 32, count 2 2006.257.23:12:19.63#ibcon#about to read 6, iclass 32, count 2 2006.257.23:12:19.63#ibcon#read 6, iclass 32, count 2 2006.257.23:12:19.63#ibcon#end of sib2, iclass 32, count 2 2006.257.23:12:19.63#ibcon#*after write, iclass 32, count 2 2006.257.23:12:19.63#ibcon#*before return 0, iclass 32, count 2 2006.257.23:12:19.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:19.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:19.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.23:12:19.63#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:19.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:19.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:19.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:19.75#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:12:19.75#ibcon#first serial, iclass 32, count 0 2006.257.23:12:19.75#ibcon#enter sib2, iclass 32, count 0 2006.257.23:12:19.75#ibcon#flushed, iclass 32, count 0 2006.257.23:12:19.75#ibcon#about to write, iclass 32, count 0 2006.257.23:12:19.75#ibcon#wrote, iclass 32, count 0 2006.257.23:12:19.75#ibcon#about to read 3, iclass 32, count 0 2006.257.23:12:19.77#ibcon#read 3, iclass 32, count 0 2006.257.23:12:19.77#ibcon#about to read 4, iclass 32, count 0 2006.257.23:12:19.77#ibcon#read 4, iclass 32, count 0 2006.257.23:12:19.77#ibcon#about to read 5, iclass 32, count 0 2006.257.23:12:19.77#ibcon#read 5, iclass 32, count 0 2006.257.23:12:19.77#ibcon#about to read 6, iclass 32, count 0 2006.257.23:12:19.77#ibcon#read 6, iclass 32, count 0 2006.257.23:12:19.77#ibcon#end of sib2, iclass 32, count 0 2006.257.23:12:19.77#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:12:19.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:12:19.77#ibcon#[25=USB\r\n] 2006.257.23:12:19.77#ibcon#*before write, iclass 32, count 0 2006.257.23:12:19.77#ibcon#enter sib2, iclass 32, count 0 2006.257.23:12:19.77#ibcon#flushed, iclass 32, count 0 2006.257.23:12:19.77#ibcon#about to write, iclass 32, count 0 2006.257.23:12:19.77#ibcon#wrote, iclass 32, count 0 2006.257.23:12:19.77#ibcon#about to read 3, iclass 32, count 0 2006.257.23:12:19.80#ibcon#read 3, iclass 32, count 0 2006.257.23:12:19.80#ibcon#about to read 4, iclass 32, count 0 2006.257.23:12:19.80#ibcon#read 4, iclass 32, count 0 2006.257.23:12:19.80#ibcon#about to read 5, iclass 32, count 0 2006.257.23:12:19.80#ibcon#read 5, iclass 32, count 0 2006.257.23:12:19.80#ibcon#about to read 6, iclass 32, count 0 2006.257.23:12:19.80#ibcon#read 6, iclass 32, count 0 2006.257.23:12:19.80#ibcon#end of sib2, iclass 32, count 0 2006.257.23:12:19.80#ibcon#*after write, iclass 32, count 0 2006.257.23:12:19.80#ibcon#*before return 0, iclass 32, count 0 2006.257.23:12:19.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:19.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:19.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:12:19.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:12:19.80$vck44/valo=5,734.99 2006.257.23:12:19.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.23:12:19.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.23:12:19.80#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:19.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:19.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:19.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:19.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:12:19.80#ibcon#first serial, iclass 34, count 0 2006.257.23:12:19.80#ibcon#enter sib2, iclass 34, count 0 2006.257.23:12:19.80#ibcon#flushed, iclass 34, count 0 2006.257.23:12:19.80#ibcon#about to write, iclass 34, count 0 2006.257.23:12:19.80#ibcon#wrote, iclass 34, count 0 2006.257.23:12:19.80#ibcon#about to read 3, iclass 34, count 0 2006.257.23:12:19.82#ibcon#read 3, iclass 34, count 0 2006.257.23:12:19.82#ibcon#about to read 4, iclass 34, count 0 2006.257.23:12:19.82#ibcon#read 4, iclass 34, count 0 2006.257.23:12:19.82#ibcon#about to read 5, iclass 34, count 0 2006.257.23:12:19.82#ibcon#read 5, iclass 34, count 0 2006.257.23:12:19.82#ibcon#about to read 6, iclass 34, count 0 2006.257.23:12:19.82#ibcon#read 6, iclass 34, count 0 2006.257.23:12:19.82#ibcon#end of sib2, iclass 34, count 0 2006.257.23:12:19.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:12:19.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:12:19.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:12:19.82#ibcon#*before write, iclass 34, count 0 2006.257.23:12:19.82#ibcon#enter sib2, iclass 34, count 0 2006.257.23:12:19.82#ibcon#flushed, iclass 34, count 0 2006.257.23:12:19.82#ibcon#about to write, iclass 34, count 0 2006.257.23:12:19.82#ibcon#wrote, iclass 34, count 0 2006.257.23:12:19.82#ibcon#about to read 3, iclass 34, count 0 2006.257.23:12:19.86#ibcon#read 3, iclass 34, count 0 2006.257.23:12:19.86#ibcon#about to read 4, iclass 34, count 0 2006.257.23:12:19.86#ibcon#read 4, iclass 34, count 0 2006.257.23:12:19.86#ibcon#about to read 5, iclass 34, count 0 2006.257.23:12:19.86#ibcon#read 5, iclass 34, count 0 2006.257.23:12:19.86#ibcon#about to read 6, iclass 34, count 0 2006.257.23:12:19.86#ibcon#read 6, iclass 34, count 0 2006.257.23:12:19.86#ibcon#end of sib2, iclass 34, count 0 2006.257.23:12:19.86#ibcon#*after write, iclass 34, count 0 2006.257.23:12:19.86#ibcon#*before return 0, iclass 34, count 0 2006.257.23:12:19.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:19.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:19.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:12:19.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:12:19.86$vck44/va=5,4 2006.257.23:12:19.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.23:12:19.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.23:12:19.86#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:19.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:19.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:19.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:19.92#ibcon#enter wrdev, iclass 36, count 2 2006.257.23:12:19.92#ibcon#first serial, iclass 36, count 2 2006.257.23:12:19.92#ibcon#enter sib2, iclass 36, count 2 2006.257.23:12:19.92#ibcon#flushed, iclass 36, count 2 2006.257.23:12:19.92#ibcon#about to write, iclass 36, count 2 2006.257.23:12:19.92#ibcon#wrote, iclass 36, count 2 2006.257.23:12:19.92#ibcon#about to read 3, iclass 36, count 2 2006.257.23:12:19.94#ibcon#read 3, iclass 36, count 2 2006.257.23:12:19.94#ibcon#about to read 4, iclass 36, count 2 2006.257.23:12:19.94#ibcon#read 4, iclass 36, count 2 2006.257.23:12:19.94#ibcon#about to read 5, iclass 36, count 2 2006.257.23:12:19.94#ibcon#read 5, iclass 36, count 2 2006.257.23:12:19.94#ibcon#about to read 6, iclass 36, count 2 2006.257.23:12:19.94#ibcon#read 6, iclass 36, count 2 2006.257.23:12:19.94#ibcon#end of sib2, iclass 36, count 2 2006.257.23:12:19.94#ibcon#*mode == 0, iclass 36, count 2 2006.257.23:12:19.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.23:12:19.94#ibcon#[25=AT05-04\r\n] 2006.257.23:12:19.94#ibcon#*before write, iclass 36, count 2 2006.257.23:12:19.94#ibcon#enter sib2, iclass 36, count 2 2006.257.23:12:19.94#ibcon#flushed, iclass 36, count 2 2006.257.23:12:19.94#ibcon#about to write, iclass 36, count 2 2006.257.23:12:19.94#ibcon#wrote, iclass 36, count 2 2006.257.23:12:19.94#ibcon#about to read 3, iclass 36, count 2 2006.257.23:12:19.97#ibcon#read 3, iclass 36, count 2 2006.257.23:12:19.97#ibcon#about to read 4, iclass 36, count 2 2006.257.23:12:19.97#ibcon#read 4, iclass 36, count 2 2006.257.23:12:19.97#ibcon#about to read 5, iclass 36, count 2 2006.257.23:12:19.97#ibcon#read 5, iclass 36, count 2 2006.257.23:12:19.97#ibcon#about to read 6, iclass 36, count 2 2006.257.23:12:19.97#ibcon#read 6, iclass 36, count 2 2006.257.23:12:19.97#ibcon#end of sib2, iclass 36, count 2 2006.257.23:12:19.97#ibcon#*after write, iclass 36, count 2 2006.257.23:12:19.97#ibcon#*before return 0, iclass 36, count 2 2006.257.23:12:19.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:19.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:19.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.23:12:19.97#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:19.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:20.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:20.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:20.09#ibcon#enter wrdev, iclass 36, count 0 2006.257.23:12:20.09#ibcon#first serial, iclass 36, count 0 2006.257.23:12:20.09#ibcon#enter sib2, iclass 36, count 0 2006.257.23:12:20.09#ibcon#flushed, iclass 36, count 0 2006.257.23:12:20.09#ibcon#about to write, iclass 36, count 0 2006.257.23:12:20.09#ibcon#wrote, iclass 36, count 0 2006.257.23:12:20.09#ibcon#about to read 3, iclass 36, count 0 2006.257.23:12:20.11#ibcon#read 3, iclass 36, count 0 2006.257.23:12:20.11#ibcon#about to read 4, iclass 36, count 0 2006.257.23:12:20.11#ibcon#read 4, iclass 36, count 0 2006.257.23:12:20.11#ibcon#about to read 5, iclass 36, count 0 2006.257.23:12:20.11#ibcon#read 5, iclass 36, count 0 2006.257.23:12:20.11#ibcon#about to read 6, iclass 36, count 0 2006.257.23:12:20.11#ibcon#read 6, iclass 36, count 0 2006.257.23:12:20.11#ibcon#end of sib2, iclass 36, count 0 2006.257.23:12:20.11#ibcon#*mode == 0, iclass 36, count 0 2006.257.23:12:20.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.23:12:20.11#ibcon#[25=USB\r\n] 2006.257.23:12:20.11#ibcon#*before write, iclass 36, count 0 2006.257.23:12:20.11#ibcon#enter sib2, iclass 36, count 0 2006.257.23:12:20.11#ibcon#flushed, iclass 36, count 0 2006.257.23:12:20.11#ibcon#about to write, iclass 36, count 0 2006.257.23:12:20.11#ibcon#wrote, iclass 36, count 0 2006.257.23:12:20.11#ibcon#about to read 3, iclass 36, count 0 2006.257.23:12:20.14#ibcon#read 3, iclass 36, count 0 2006.257.23:12:20.14#ibcon#about to read 4, iclass 36, count 0 2006.257.23:12:20.14#ibcon#read 4, iclass 36, count 0 2006.257.23:12:20.14#ibcon#about to read 5, iclass 36, count 0 2006.257.23:12:20.14#ibcon#read 5, iclass 36, count 0 2006.257.23:12:20.14#ibcon#about to read 6, iclass 36, count 0 2006.257.23:12:20.14#ibcon#read 6, iclass 36, count 0 2006.257.23:12:20.14#ibcon#end of sib2, iclass 36, count 0 2006.257.23:12:20.14#ibcon#*after write, iclass 36, count 0 2006.257.23:12:20.14#ibcon#*before return 0, iclass 36, count 0 2006.257.23:12:20.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:20.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:20.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.23:12:20.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.23:12:20.14$vck44/valo=6,814.99 2006.257.23:12:20.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.23:12:20.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.23:12:20.14#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:20.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:20.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:20.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:20.14#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:12:20.14#ibcon#first serial, iclass 38, count 0 2006.257.23:12:20.14#ibcon#enter sib2, iclass 38, count 0 2006.257.23:12:20.14#ibcon#flushed, iclass 38, count 0 2006.257.23:12:20.14#ibcon#about to write, iclass 38, count 0 2006.257.23:12:20.14#ibcon#wrote, iclass 38, count 0 2006.257.23:12:20.14#ibcon#about to read 3, iclass 38, count 0 2006.257.23:12:20.16#ibcon#read 3, iclass 38, count 0 2006.257.23:12:20.16#ibcon#about to read 4, iclass 38, count 0 2006.257.23:12:20.16#ibcon#read 4, iclass 38, count 0 2006.257.23:12:20.16#ibcon#about to read 5, iclass 38, count 0 2006.257.23:12:20.16#ibcon#read 5, iclass 38, count 0 2006.257.23:12:20.16#ibcon#about to read 6, iclass 38, count 0 2006.257.23:12:20.16#ibcon#read 6, iclass 38, count 0 2006.257.23:12:20.16#ibcon#end of sib2, iclass 38, count 0 2006.257.23:12:20.16#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:12:20.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:12:20.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:12:20.16#ibcon#*before write, iclass 38, count 0 2006.257.23:12:20.16#ibcon#enter sib2, iclass 38, count 0 2006.257.23:12:20.16#ibcon#flushed, iclass 38, count 0 2006.257.23:12:20.16#ibcon#about to write, iclass 38, count 0 2006.257.23:12:20.16#ibcon#wrote, iclass 38, count 0 2006.257.23:12:20.16#ibcon#about to read 3, iclass 38, count 0 2006.257.23:12:20.20#ibcon#read 3, iclass 38, count 0 2006.257.23:12:20.20#ibcon#about to read 4, iclass 38, count 0 2006.257.23:12:20.20#ibcon#read 4, iclass 38, count 0 2006.257.23:12:20.20#ibcon#about to read 5, iclass 38, count 0 2006.257.23:12:20.20#ibcon#read 5, iclass 38, count 0 2006.257.23:12:20.20#ibcon#about to read 6, iclass 38, count 0 2006.257.23:12:20.20#ibcon#read 6, iclass 38, count 0 2006.257.23:12:20.20#ibcon#end of sib2, iclass 38, count 0 2006.257.23:12:20.20#ibcon#*after write, iclass 38, count 0 2006.257.23:12:20.20#ibcon#*before return 0, iclass 38, count 0 2006.257.23:12:20.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:20.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:20.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:12:20.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:12:20.20$vck44/va=6,4 2006.257.23:12:20.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.23:12:20.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.23:12:20.20#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:20.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:20.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:20.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:20.26#ibcon#enter wrdev, iclass 40, count 2 2006.257.23:12:20.26#ibcon#first serial, iclass 40, count 2 2006.257.23:12:20.26#ibcon#enter sib2, iclass 40, count 2 2006.257.23:12:20.26#ibcon#flushed, iclass 40, count 2 2006.257.23:12:20.26#ibcon#about to write, iclass 40, count 2 2006.257.23:12:20.26#ibcon#wrote, iclass 40, count 2 2006.257.23:12:20.26#ibcon#about to read 3, iclass 40, count 2 2006.257.23:12:20.28#ibcon#read 3, iclass 40, count 2 2006.257.23:12:20.28#ibcon#about to read 4, iclass 40, count 2 2006.257.23:12:20.28#ibcon#read 4, iclass 40, count 2 2006.257.23:12:20.28#ibcon#about to read 5, iclass 40, count 2 2006.257.23:12:20.28#ibcon#read 5, iclass 40, count 2 2006.257.23:12:20.28#ibcon#about to read 6, iclass 40, count 2 2006.257.23:12:20.28#ibcon#read 6, iclass 40, count 2 2006.257.23:12:20.28#ibcon#end of sib2, iclass 40, count 2 2006.257.23:12:20.28#ibcon#*mode == 0, iclass 40, count 2 2006.257.23:12:20.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.23:12:20.28#ibcon#[25=AT06-04\r\n] 2006.257.23:12:20.28#ibcon#*before write, iclass 40, count 2 2006.257.23:12:20.28#ibcon#enter sib2, iclass 40, count 2 2006.257.23:12:20.28#ibcon#flushed, iclass 40, count 2 2006.257.23:12:20.28#ibcon#about to write, iclass 40, count 2 2006.257.23:12:20.28#ibcon#wrote, iclass 40, count 2 2006.257.23:12:20.28#ibcon#about to read 3, iclass 40, count 2 2006.257.23:12:20.31#ibcon#read 3, iclass 40, count 2 2006.257.23:12:20.31#ibcon#about to read 4, iclass 40, count 2 2006.257.23:12:20.31#ibcon#read 4, iclass 40, count 2 2006.257.23:12:20.31#ibcon#about to read 5, iclass 40, count 2 2006.257.23:12:20.31#ibcon#read 5, iclass 40, count 2 2006.257.23:12:20.31#ibcon#about to read 6, iclass 40, count 2 2006.257.23:12:20.31#ibcon#read 6, iclass 40, count 2 2006.257.23:12:20.31#ibcon#end of sib2, iclass 40, count 2 2006.257.23:12:20.31#ibcon#*after write, iclass 40, count 2 2006.257.23:12:20.31#ibcon#*before return 0, iclass 40, count 2 2006.257.23:12:20.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:20.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:20.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.23:12:20.31#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:20.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:20.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:20.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:20.43#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:12:20.43#ibcon#first serial, iclass 40, count 0 2006.257.23:12:20.43#ibcon#enter sib2, iclass 40, count 0 2006.257.23:12:20.43#ibcon#flushed, iclass 40, count 0 2006.257.23:12:20.43#ibcon#about to write, iclass 40, count 0 2006.257.23:12:20.43#ibcon#wrote, iclass 40, count 0 2006.257.23:12:20.43#ibcon#about to read 3, iclass 40, count 0 2006.257.23:12:20.45#ibcon#read 3, iclass 40, count 0 2006.257.23:12:20.45#ibcon#about to read 4, iclass 40, count 0 2006.257.23:12:20.45#ibcon#read 4, iclass 40, count 0 2006.257.23:12:20.45#ibcon#about to read 5, iclass 40, count 0 2006.257.23:12:20.45#ibcon#read 5, iclass 40, count 0 2006.257.23:12:20.45#ibcon#about to read 6, iclass 40, count 0 2006.257.23:12:20.45#ibcon#read 6, iclass 40, count 0 2006.257.23:12:20.45#ibcon#end of sib2, iclass 40, count 0 2006.257.23:12:20.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:12:20.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:12:20.45#ibcon#[25=USB\r\n] 2006.257.23:12:20.45#ibcon#*before write, iclass 40, count 0 2006.257.23:12:20.45#ibcon#enter sib2, iclass 40, count 0 2006.257.23:12:20.45#ibcon#flushed, iclass 40, count 0 2006.257.23:12:20.45#ibcon#about to write, iclass 40, count 0 2006.257.23:12:20.45#ibcon#wrote, iclass 40, count 0 2006.257.23:12:20.45#ibcon#about to read 3, iclass 40, count 0 2006.257.23:12:20.48#ibcon#read 3, iclass 40, count 0 2006.257.23:12:20.48#ibcon#about to read 4, iclass 40, count 0 2006.257.23:12:20.48#ibcon#read 4, iclass 40, count 0 2006.257.23:12:20.48#ibcon#about to read 5, iclass 40, count 0 2006.257.23:12:20.48#ibcon#read 5, iclass 40, count 0 2006.257.23:12:20.48#ibcon#about to read 6, iclass 40, count 0 2006.257.23:12:20.48#ibcon#read 6, iclass 40, count 0 2006.257.23:12:20.48#ibcon#end of sib2, iclass 40, count 0 2006.257.23:12:20.48#ibcon#*after write, iclass 40, count 0 2006.257.23:12:20.48#ibcon#*before return 0, iclass 40, count 0 2006.257.23:12:20.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:20.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:20.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:12:20.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:12:20.48$vck44/valo=7,864.99 2006.257.23:12:20.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.23:12:20.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.23:12:20.48#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:20.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:20.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:20.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:20.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:12:20.48#ibcon#first serial, iclass 4, count 0 2006.257.23:12:20.48#ibcon#enter sib2, iclass 4, count 0 2006.257.23:12:20.48#ibcon#flushed, iclass 4, count 0 2006.257.23:12:20.48#ibcon#about to write, iclass 4, count 0 2006.257.23:12:20.48#ibcon#wrote, iclass 4, count 0 2006.257.23:12:20.48#ibcon#about to read 3, iclass 4, count 0 2006.257.23:12:20.50#ibcon#read 3, iclass 4, count 0 2006.257.23:12:20.50#ibcon#about to read 4, iclass 4, count 0 2006.257.23:12:20.50#ibcon#read 4, iclass 4, count 0 2006.257.23:12:20.50#ibcon#about to read 5, iclass 4, count 0 2006.257.23:12:20.50#ibcon#read 5, iclass 4, count 0 2006.257.23:12:20.50#ibcon#about to read 6, iclass 4, count 0 2006.257.23:12:20.50#ibcon#read 6, iclass 4, count 0 2006.257.23:12:20.50#ibcon#end of sib2, iclass 4, count 0 2006.257.23:12:20.50#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:12:20.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:12:20.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:12:20.50#ibcon#*before write, iclass 4, count 0 2006.257.23:12:20.50#ibcon#enter sib2, iclass 4, count 0 2006.257.23:12:20.50#ibcon#flushed, iclass 4, count 0 2006.257.23:12:20.50#ibcon#about to write, iclass 4, count 0 2006.257.23:12:20.50#ibcon#wrote, iclass 4, count 0 2006.257.23:12:20.50#ibcon#about to read 3, iclass 4, count 0 2006.257.23:12:20.54#ibcon#read 3, iclass 4, count 0 2006.257.23:12:20.54#ibcon#about to read 4, iclass 4, count 0 2006.257.23:12:20.54#ibcon#read 4, iclass 4, count 0 2006.257.23:12:20.54#ibcon#about to read 5, iclass 4, count 0 2006.257.23:12:20.54#ibcon#read 5, iclass 4, count 0 2006.257.23:12:20.54#ibcon#about to read 6, iclass 4, count 0 2006.257.23:12:20.54#ibcon#read 6, iclass 4, count 0 2006.257.23:12:20.54#ibcon#end of sib2, iclass 4, count 0 2006.257.23:12:20.54#ibcon#*after write, iclass 4, count 0 2006.257.23:12:20.54#ibcon#*before return 0, iclass 4, count 0 2006.257.23:12:20.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:20.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:20.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:12:20.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:12:20.54$vck44/va=7,4 2006.257.23:12:20.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.23:12:20.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.23:12:20.54#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:20.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:20.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:20.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:20.60#ibcon#enter wrdev, iclass 6, count 2 2006.257.23:12:20.60#ibcon#first serial, iclass 6, count 2 2006.257.23:12:20.60#ibcon#enter sib2, iclass 6, count 2 2006.257.23:12:20.60#ibcon#flushed, iclass 6, count 2 2006.257.23:12:20.60#ibcon#about to write, iclass 6, count 2 2006.257.23:12:20.60#ibcon#wrote, iclass 6, count 2 2006.257.23:12:20.60#ibcon#about to read 3, iclass 6, count 2 2006.257.23:12:20.62#ibcon#read 3, iclass 6, count 2 2006.257.23:12:20.62#ibcon#about to read 4, iclass 6, count 2 2006.257.23:12:20.62#ibcon#read 4, iclass 6, count 2 2006.257.23:12:20.62#ibcon#about to read 5, iclass 6, count 2 2006.257.23:12:20.62#ibcon#read 5, iclass 6, count 2 2006.257.23:12:20.62#ibcon#about to read 6, iclass 6, count 2 2006.257.23:12:20.62#ibcon#read 6, iclass 6, count 2 2006.257.23:12:20.62#ibcon#end of sib2, iclass 6, count 2 2006.257.23:12:20.62#ibcon#*mode == 0, iclass 6, count 2 2006.257.23:12:20.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.23:12:20.62#ibcon#[25=AT07-04\r\n] 2006.257.23:12:20.62#ibcon#*before write, iclass 6, count 2 2006.257.23:12:20.62#ibcon#enter sib2, iclass 6, count 2 2006.257.23:12:20.62#ibcon#flushed, iclass 6, count 2 2006.257.23:12:20.62#ibcon#about to write, iclass 6, count 2 2006.257.23:12:20.62#ibcon#wrote, iclass 6, count 2 2006.257.23:12:20.62#ibcon#about to read 3, iclass 6, count 2 2006.257.23:12:20.65#ibcon#read 3, iclass 6, count 2 2006.257.23:12:20.65#ibcon#about to read 4, iclass 6, count 2 2006.257.23:12:20.65#ibcon#read 4, iclass 6, count 2 2006.257.23:12:20.65#ibcon#about to read 5, iclass 6, count 2 2006.257.23:12:20.65#ibcon#read 5, iclass 6, count 2 2006.257.23:12:20.65#ibcon#about to read 6, iclass 6, count 2 2006.257.23:12:20.65#ibcon#read 6, iclass 6, count 2 2006.257.23:12:20.65#ibcon#end of sib2, iclass 6, count 2 2006.257.23:12:20.65#ibcon#*after write, iclass 6, count 2 2006.257.23:12:20.65#ibcon#*before return 0, iclass 6, count 2 2006.257.23:12:20.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:20.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:20.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.23:12:20.65#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:20.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:20.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:20.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:20.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:12:20.77#ibcon#first serial, iclass 6, count 0 2006.257.23:12:20.77#ibcon#enter sib2, iclass 6, count 0 2006.257.23:12:20.77#ibcon#flushed, iclass 6, count 0 2006.257.23:12:20.77#ibcon#about to write, iclass 6, count 0 2006.257.23:12:20.77#ibcon#wrote, iclass 6, count 0 2006.257.23:12:20.77#ibcon#about to read 3, iclass 6, count 0 2006.257.23:12:20.79#ibcon#read 3, iclass 6, count 0 2006.257.23:12:20.79#ibcon#about to read 4, iclass 6, count 0 2006.257.23:12:20.79#ibcon#read 4, iclass 6, count 0 2006.257.23:12:20.79#ibcon#about to read 5, iclass 6, count 0 2006.257.23:12:20.79#ibcon#read 5, iclass 6, count 0 2006.257.23:12:20.79#ibcon#about to read 6, iclass 6, count 0 2006.257.23:12:20.79#ibcon#read 6, iclass 6, count 0 2006.257.23:12:20.79#ibcon#end of sib2, iclass 6, count 0 2006.257.23:12:20.79#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:12:20.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:12:20.79#ibcon#[25=USB\r\n] 2006.257.23:12:20.79#ibcon#*before write, iclass 6, count 0 2006.257.23:12:20.79#ibcon#enter sib2, iclass 6, count 0 2006.257.23:12:20.79#ibcon#flushed, iclass 6, count 0 2006.257.23:12:20.79#ibcon#about to write, iclass 6, count 0 2006.257.23:12:20.79#ibcon#wrote, iclass 6, count 0 2006.257.23:12:20.79#ibcon#about to read 3, iclass 6, count 0 2006.257.23:12:20.82#ibcon#read 3, iclass 6, count 0 2006.257.23:12:20.82#ibcon#about to read 4, iclass 6, count 0 2006.257.23:12:20.82#ibcon#read 4, iclass 6, count 0 2006.257.23:12:20.82#ibcon#about to read 5, iclass 6, count 0 2006.257.23:12:20.82#ibcon#read 5, iclass 6, count 0 2006.257.23:12:20.82#ibcon#about to read 6, iclass 6, count 0 2006.257.23:12:20.82#ibcon#read 6, iclass 6, count 0 2006.257.23:12:20.82#ibcon#end of sib2, iclass 6, count 0 2006.257.23:12:20.82#ibcon#*after write, iclass 6, count 0 2006.257.23:12:20.82#ibcon#*before return 0, iclass 6, count 0 2006.257.23:12:20.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:20.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:20.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:12:20.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:12:20.82$vck44/valo=8,884.99 2006.257.23:12:20.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.23:12:20.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.23:12:20.82#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:20.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:20.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:20.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:20.82#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:12:20.82#ibcon#first serial, iclass 10, count 0 2006.257.23:12:20.82#ibcon#enter sib2, iclass 10, count 0 2006.257.23:12:20.82#ibcon#flushed, iclass 10, count 0 2006.257.23:12:20.82#ibcon#about to write, iclass 10, count 0 2006.257.23:12:20.82#ibcon#wrote, iclass 10, count 0 2006.257.23:12:20.82#ibcon#about to read 3, iclass 10, count 0 2006.257.23:12:20.84#ibcon#read 3, iclass 10, count 0 2006.257.23:12:20.84#ibcon#about to read 4, iclass 10, count 0 2006.257.23:12:20.84#ibcon#read 4, iclass 10, count 0 2006.257.23:12:20.84#ibcon#about to read 5, iclass 10, count 0 2006.257.23:12:20.84#ibcon#read 5, iclass 10, count 0 2006.257.23:12:20.84#ibcon#about to read 6, iclass 10, count 0 2006.257.23:12:20.84#ibcon#read 6, iclass 10, count 0 2006.257.23:12:20.84#ibcon#end of sib2, iclass 10, count 0 2006.257.23:12:20.84#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:12:20.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:12:20.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:12:20.84#ibcon#*before write, iclass 10, count 0 2006.257.23:12:20.84#ibcon#enter sib2, iclass 10, count 0 2006.257.23:12:20.84#ibcon#flushed, iclass 10, count 0 2006.257.23:12:20.84#ibcon#about to write, iclass 10, count 0 2006.257.23:12:20.84#ibcon#wrote, iclass 10, count 0 2006.257.23:12:20.84#ibcon#about to read 3, iclass 10, count 0 2006.257.23:12:20.88#ibcon#read 3, iclass 10, count 0 2006.257.23:12:20.88#ibcon#about to read 4, iclass 10, count 0 2006.257.23:12:20.88#ibcon#read 4, iclass 10, count 0 2006.257.23:12:20.88#ibcon#about to read 5, iclass 10, count 0 2006.257.23:12:20.88#ibcon#read 5, iclass 10, count 0 2006.257.23:12:20.88#ibcon#about to read 6, iclass 10, count 0 2006.257.23:12:20.88#ibcon#read 6, iclass 10, count 0 2006.257.23:12:20.88#ibcon#end of sib2, iclass 10, count 0 2006.257.23:12:20.88#ibcon#*after write, iclass 10, count 0 2006.257.23:12:20.88#ibcon#*before return 0, iclass 10, count 0 2006.257.23:12:20.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:20.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:20.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:12:20.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:12:20.88$vck44/va=8,4 2006.257.23:12:20.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.23:12:20.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.23:12:20.88#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:20.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:12:20.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:12:20.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:12:20.94#ibcon#enter wrdev, iclass 12, count 2 2006.257.23:12:20.94#ibcon#first serial, iclass 12, count 2 2006.257.23:12:20.94#ibcon#enter sib2, iclass 12, count 2 2006.257.23:12:20.94#ibcon#flushed, iclass 12, count 2 2006.257.23:12:20.94#ibcon#about to write, iclass 12, count 2 2006.257.23:12:20.94#ibcon#wrote, iclass 12, count 2 2006.257.23:12:20.94#ibcon#about to read 3, iclass 12, count 2 2006.257.23:12:20.96#ibcon#read 3, iclass 12, count 2 2006.257.23:12:20.96#ibcon#about to read 4, iclass 12, count 2 2006.257.23:12:20.96#ibcon#read 4, iclass 12, count 2 2006.257.23:12:20.96#ibcon#about to read 5, iclass 12, count 2 2006.257.23:12:20.96#ibcon#read 5, iclass 12, count 2 2006.257.23:12:20.96#ibcon#about to read 6, iclass 12, count 2 2006.257.23:12:20.96#ibcon#read 6, iclass 12, count 2 2006.257.23:12:20.96#ibcon#end of sib2, iclass 12, count 2 2006.257.23:12:20.96#ibcon#*mode == 0, iclass 12, count 2 2006.257.23:12:20.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.23:12:20.96#ibcon#[25=AT08-04\r\n] 2006.257.23:12:20.96#ibcon#*before write, iclass 12, count 2 2006.257.23:12:20.96#ibcon#enter sib2, iclass 12, count 2 2006.257.23:12:20.96#ibcon#flushed, iclass 12, count 2 2006.257.23:12:20.96#ibcon#about to write, iclass 12, count 2 2006.257.23:12:20.96#ibcon#wrote, iclass 12, count 2 2006.257.23:12:20.96#ibcon#about to read 3, iclass 12, count 2 2006.257.23:12:20.99#ibcon#read 3, iclass 12, count 2 2006.257.23:12:20.99#ibcon#about to read 4, iclass 12, count 2 2006.257.23:12:20.99#ibcon#read 4, iclass 12, count 2 2006.257.23:12:20.99#ibcon#about to read 5, iclass 12, count 2 2006.257.23:12:20.99#ibcon#read 5, iclass 12, count 2 2006.257.23:12:20.99#ibcon#about to read 6, iclass 12, count 2 2006.257.23:12:20.99#ibcon#read 6, iclass 12, count 2 2006.257.23:12:20.99#ibcon#end of sib2, iclass 12, count 2 2006.257.23:12:20.99#ibcon#*after write, iclass 12, count 2 2006.257.23:12:20.99#ibcon#*before return 0, iclass 12, count 2 2006.257.23:12:20.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:12:20.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:12:20.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.23:12:20.99#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:20.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:12:21.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:12:21.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:12:21.11#ibcon#enter wrdev, iclass 12, count 0 2006.257.23:12:21.11#ibcon#first serial, iclass 12, count 0 2006.257.23:12:21.11#ibcon#enter sib2, iclass 12, count 0 2006.257.23:12:21.11#ibcon#flushed, iclass 12, count 0 2006.257.23:12:21.11#ibcon#about to write, iclass 12, count 0 2006.257.23:12:21.11#ibcon#wrote, iclass 12, count 0 2006.257.23:12:21.11#ibcon#about to read 3, iclass 12, count 0 2006.257.23:12:21.13#ibcon#read 3, iclass 12, count 0 2006.257.23:12:21.13#ibcon#about to read 4, iclass 12, count 0 2006.257.23:12:21.13#ibcon#read 4, iclass 12, count 0 2006.257.23:12:21.13#ibcon#about to read 5, iclass 12, count 0 2006.257.23:12:21.13#ibcon#read 5, iclass 12, count 0 2006.257.23:12:21.13#ibcon#about to read 6, iclass 12, count 0 2006.257.23:12:21.13#ibcon#read 6, iclass 12, count 0 2006.257.23:12:21.13#ibcon#end of sib2, iclass 12, count 0 2006.257.23:12:21.13#ibcon#*mode == 0, iclass 12, count 0 2006.257.23:12:21.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.23:12:21.13#ibcon#[25=USB\r\n] 2006.257.23:12:21.13#ibcon#*before write, iclass 12, count 0 2006.257.23:12:21.13#ibcon#enter sib2, iclass 12, count 0 2006.257.23:12:21.13#ibcon#flushed, iclass 12, count 0 2006.257.23:12:21.13#ibcon#about to write, iclass 12, count 0 2006.257.23:12:21.13#ibcon#wrote, iclass 12, count 0 2006.257.23:12:21.13#ibcon#about to read 3, iclass 12, count 0 2006.257.23:12:21.16#ibcon#read 3, iclass 12, count 0 2006.257.23:12:21.16#ibcon#about to read 4, iclass 12, count 0 2006.257.23:12:21.16#ibcon#read 4, iclass 12, count 0 2006.257.23:12:21.16#ibcon#about to read 5, iclass 12, count 0 2006.257.23:12:21.16#ibcon#read 5, iclass 12, count 0 2006.257.23:12:21.16#ibcon#about to read 6, iclass 12, count 0 2006.257.23:12:21.16#ibcon#read 6, iclass 12, count 0 2006.257.23:12:21.16#ibcon#end of sib2, iclass 12, count 0 2006.257.23:12:21.16#ibcon#*after write, iclass 12, count 0 2006.257.23:12:21.16#ibcon#*before return 0, iclass 12, count 0 2006.257.23:12:21.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:12:21.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:12:21.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.23:12:21.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.23:12:21.16$vck44/vblo=1,629.99 2006.257.23:12:21.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.23:12:21.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.23:12:21.16#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:21.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:12:21.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:12:21.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:12:21.16#ibcon#enter wrdev, iclass 14, count 0 2006.257.23:12:21.16#ibcon#first serial, iclass 14, count 0 2006.257.23:12:21.16#ibcon#enter sib2, iclass 14, count 0 2006.257.23:12:21.16#ibcon#flushed, iclass 14, count 0 2006.257.23:12:21.16#ibcon#about to write, iclass 14, count 0 2006.257.23:12:21.16#ibcon#wrote, iclass 14, count 0 2006.257.23:12:21.16#ibcon#about to read 3, iclass 14, count 0 2006.257.23:12:21.18#ibcon#read 3, iclass 14, count 0 2006.257.23:12:21.18#ibcon#about to read 4, iclass 14, count 0 2006.257.23:12:21.18#ibcon#read 4, iclass 14, count 0 2006.257.23:12:21.18#ibcon#about to read 5, iclass 14, count 0 2006.257.23:12:21.18#ibcon#read 5, iclass 14, count 0 2006.257.23:12:21.18#ibcon#about to read 6, iclass 14, count 0 2006.257.23:12:21.18#ibcon#read 6, iclass 14, count 0 2006.257.23:12:21.18#ibcon#end of sib2, iclass 14, count 0 2006.257.23:12:21.18#ibcon#*mode == 0, iclass 14, count 0 2006.257.23:12:21.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.23:12:21.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:12:21.18#ibcon#*before write, iclass 14, count 0 2006.257.23:12:21.18#ibcon#enter sib2, iclass 14, count 0 2006.257.23:12:21.18#ibcon#flushed, iclass 14, count 0 2006.257.23:12:21.18#ibcon#about to write, iclass 14, count 0 2006.257.23:12:21.18#ibcon#wrote, iclass 14, count 0 2006.257.23:12:21.18#ibcon#about to read 3, iclass 14, count 0 2006.257.23:12:21.22#ibcon#read 3, iclass 14, count 0 2006.257.23:12:21.22#ibcon#about to read 4, iclass 14, count 0 2006.257.23:12:21.22#ibcon#read 4, iclass 14, count 0 2006.257.23:12:21.22#ibcon#about to read 5, iclass 14, count 0 2006.257.23:12:21.22#ibcon#read 5, iclass 14, count 0 2006.257.23:12:21.22#ibcon#about to read 6, iclass 14, count 0 2006.257.23:12:21.22#ibcon#read 6, iclass 14, count 0 2006.257.23:12:21.22#ibcon#end of sib2, iclass 14, count 0 2006.257.23:12:21.22#ibcon#*after write, iclass 14, count 0 2006.257.23:12:21.22#ibcon#*before return 0, iclass 14, count 0 2006.257.23:12:21.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:12:21.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:12:21.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.23:12:21.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.23:12:21.22$vck44/vb=1,4 2006.257.23:12:21.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.23:12:21.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.23:12:21.22#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:21.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:12:21.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:12:21.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:12:21.22#ibcon#enter wrdev, iclass 16, count 2 2006.257.23:12:21.22#ibcon#first serial, iclass 16, count 2 2006.257.23:12:21.22#ibcon#enter sib2, iclass 16, count 2 2006.257.23:12:21.22#ibcon#flushed, iclass 16, count 2 2006.257.23:12:21.22#ibcon#about to write, iclass 16, count 2 2006.257.23:12:21.22#ibcon#wrote, iclass 16, count 2 2006.257.23:12:21.22#ibcon#about to read 3, iclass 16, count 2 2006.257.23:12:21.24#ibcon#read 3, iclass 16, count 2 2006.257.23:12:21.24#ibcon#about to read 4, iclass 16, count 2 2006.257.23:12:21.24#ibcon#read 4, iclass 16, count 2 2006.257.23:12:21.24#ibcon#about to read 5, iclass 16, count 2 2006.257.23:12:21.24#ibcon#read 5, iclass 16, count 2 2006.257.23:12:21.24#ibcon#about to read 6, iclass 16, count 2 2006.257.23:12:21.24#ibcon#read 6, iclass 16, count 2 2006.257.23:12:21.24#ibcon#end of sib2, iclass 16, count 2 2006.257.23:12:21.24#ibcon#*mode == 0, iclass 16, count 2 2006.257.23:12:21.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.23:12:21.24#ibcon#[27=AT01-04\r\n] 2006.257.23:12:21.24#ibcon#*before write, iclass 16, count 2 2006.257.23:12:21.24#ibcon#enter sib2, iclass 16, count 2 2006.257.23:12:21.24#ibcon#flushed, iclass 16, count 2 2006.257.23:12:21.24#ibcon#about to write, iclass 16, count 2 2006.257.23:12:21.24#ibcon#wrote, iclass 16, count 2 2006.257.23:12:21.24#ibcon#about to read 3, iclass 16, count 2 2006.257.23:12:21.27#ibcon#read 3, iclass 16, count 2 2006.257.23:12:21.27#ibcon#about to read 4, iclass 16, count 2 2006.257.23:12:21.27#ibcon#read 4, iclass 16, count 2 2006.257.23:12:21.27#ibcon#about to read 5, iclass 16, count 2 2006.257.23:12:21.27#ibcon#read 5, iclass 16, count 2 2006.257.23:12:21.27#ibcon#about to read 6, iclass 16, count 2 2006.257.23:12:21.27#ibcon#read 6, iclass 16, count 2 2006.257.23:12:21.27#ibcon#end of sib2, iclass 16, count 2 2006.257.23:12:21.27#ibcon#*after write, iclass 16, count 2 2006.257.23:12:21.27#ibcon#*before return 0, iclass 16, count 2 2006.257.23:12:21.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:12:21.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:12:21.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.23:12:21.27#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:21.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:12:21.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:12:21.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:12:21.39#ibcon#enter wrdev, iclass 16, count 0 2006.257.23:12:21.39#ibcon#first serial, iclass 16, count 0 2006.257.23:12:21.39#ibcon#enter sib2, iclass 16, count 0 2006.257.23:12:21.39#ibcon#flushed, iclass 16, count 0 2006.257.23:12:21.39#ibcon#about to write, iclass 16, count 0 2006.257.23:12:21.39#ibcon#wrote, iclass 16, count 0 2006.257.23:12:21.39#ibcon#about to read 3, iclass 16, count 0 2006.257.23:12:21.41#ibcon#read 3, iclass 16, count 0 2006.257.23:12:21.41#ibcon#about to read 4, iclass 16, count 0 2006.257.23:12:21.41#ibcon#read 4, iclass 16, count 0 2006.257.23:12:21.41#ibcon#about to read 5, iclass 16, count 0 2006.257.23:12:21.41#ibcon#read 5, iclass 16, count 0 2006.257.23:12:21.41#ibcon#about to read 6, iclass 16, count 0 2006.257.23:12:21.41#ibcon#read 6, iclass 16, count 0 2006.257.23:12:21.41#ibcon#end of sib2, iclass 16, count 0 2006.257.23:12:21.41#ibcon#*mode == 0, iclass 16, count 0 2006.257.23:12:21.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.23:12:21.41#ibcon#[27=USB\r\n] 2006.257.23:12:21.41#ibcon#*before write, iclass 16, count 0 2006.257.23:12:21.41#ibcon#enter sib2, iclass 16, count 0 2006.257.23:12:21.41#ibcon#flushed, iclass 16, count 0 2006.257.23:12:21.41#ibcon#about to write, iclass 16, count 0 2006.257.23:12:21.41#ibcon#wrote, iclass 16, count 0 2006.257.23:12:21.41#ibcon#about to read 3, iclass 16, count 0 2006.257.23:12:21.44#ibcon#read 3, iclass 16, count 0 2006.257.23:12:21.44#ibcon#about to read 4, iclass 16, count 0 2006.257.23:12:21.44#ibcon#read 4, iclass 16, count 0 2006.257.23:12:21.44#ibcon#about to read 5, iclass 16, count 0 2006.257.23:12:21.44#ibcon#read 5, iclass 16, count 0 2006.257.23:12:21.44#ibcon#about to read 6, iclass 16, count 0 2006.257.23:12:21.44#ibcon#read 6, iclass 16, count 0 2006.257.23:12:21.44#ibcon#end of sib2, iclass 16, count 0 2006.257.23:12:21.44#ibcon#*after write, iclass 16, count 0 2006.257.23:12:21.44#ibcon#*before return 0, iclass 16, count 0 2006.257.23:12:21.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:12:21.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:12:21.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.23:12:21.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.23:12:21.44$vck44/vblo=2,634.99 2006.257.23:12:21.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.23:12:21.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.23:12:21.44#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:21.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:21.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:21.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:21.44#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:12:21.44#ibcon#first serial, iclass 18, count 0 2006.257.23:12:21.44#ibcon#enter sib2, iclass 18, count 0 2006.257.23:12:21.44#ibcon#flushed, iclass 18, count 0 2006.257.23:12:21.44#ibcon#about to write, iclass 18, count 0 2006.257.23:12:21.44#ibcon#wrote, iclass 18, count 0 2006.257.23:12:21.44#ibcon#about to read 3, iclass 18, count 0 2006.257.23:12:21.46#ibcon#read 3, iclass 18, count 0 2006.257.23:12:21.46#ibcon#about to read 4, iclass 18, count 0 2006.257.23:12:21.46#ibcon#read 4, iclass 18, count 0 2006.257.23:12:21.46#ibcon#about to read 5, iclass 18, count 0 2006.257.23:12:21.46#ibcon#read 5, iclass 18, count 0 2006.257.23:12:21.46#ibcon#about to read 6, iclass 18, count 0 2006.257.23:12:21.46#ibcon#read 6, iclass 18, count 0 2006.257.23:12:21.46#ibcon#end of sib2, iclass 18, count 0 2006.257.23:12:21.46#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:12:21.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:12:21.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:12:21.46#ibcon#*before write, iclass 18, count 0 2006.257.23:12:21.46#ibcon#enter sib2, iclass 18, count 0 2006.257.23:12:21.46#ibcon#flushed, iclass 18, count 0 2006.257.23:12:21.46#ibcon#about to write, iclass 18, count 0 2006.257.23:12:21.46#ibcon#wrote, iclass 18, count 0 2006.257.23:12:21.46#ibcon#about to read 3, iclass 18, count 0 2006.257.23:12:21.50#ibcon#read 3, iclass 18, count 0 2006.257.23:12:21.50#ibcon#about to read 4, iclass 18, count 0 2006.257.23:12:21.50#ibcon#read 4, iclass 18, count 0 2006.257.23:12:21.50#ibcon#about to read 5, iclass 18, count 0 2006.257.23:12:21.50#ibcon#read 5, iclass 18, count 0 2006.257.23:12:21.50#ibcon#about to read 6, iclass 18, count 0 2006.257.23:12:21.50#ibcon#read 6, iclass 18, count 0 2006.257.23:12:21.50#ibcon#end of sib2, iclass 18, count 0 2006.257.23:12:21.50#ibcon#*after write, iclass 18, count 0 2006.257.23:12:21.50#ibcon#*before return 0, iclass 18, count 0 2006.257.23:12:21.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:21.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:12:21.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:12:21.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:12:21.50$vck44/vb=2,5 2006.257.23:12:21.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.23:12:21.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.23:12:21.50#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:21.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:21.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:21.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:21.56#ibcon#enter wrdev, iclass 20, count 2 2006.257.23:12:21.56#ibcon#first serial, iclass 20, count 2 2006.257.23:12:21.56#ibcon#enter sib2, iclass 20, count 2 2006.257.23:12:21.56#ibcon#flushed, iclass 20, count 2 2006.257.23:12:21.56#ibcon#about to write, iclass 20, count 2 2006.257.23:12:21.56#ibcon#wrote, iclass 20, count 2 2006.257.23:12:21.56#ibcon#about to read 3, iclass 20, count 2 2006.257.23:12:21.58#ibcon#read 3, iclass 20, count 2 2006.257.23:12:21.58#ibcon#about to read 4, iclass 20, count 2 2006.257.23:12:21.58#ibcon#read 4, iclass 20, count 2 2006.257.23:12:21.58#ibcon#about to read 5, iclass 20, count 2 2006.257.23:12:21.58#ibcon#read 5, iclass 20, count 2 2006.257.23:12:21.58#ibcon#about to read 6, iclass 20, count 2 2006.257.23:12:21.58#ibcon#read 6, iclass 20, count 2 2006.257.23:12:21.58#ibcon#end of sib2, iclass 20, count 2 2006.257.23:12:21.58#ibcon#*mode == 0, iclass 20, count 2 2006.257.23:12:21.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.23:12:21.58#ibcon#[27=AT02-05\r\n] 2006.257.23:12:21.58#ibcon#*before write, iclass 20, count 2 2006.257.23:12:21.58#ibcon#enter sib2, iclass 20, count 2 2006.257.23:12:21.58#ibcon#flushed, iclass 20, count 2 2006.257.23:12:21.58#ibcon#about to write, iclass 20, count 2 2006.257.23:12:21.58#ibcon#wrote, iclass 20, count 2 2006.257.23:12:21.58#ibcon#about to read 3, iclass 20, count 2 2006.257.23:12:21.61#ibcon#read 3, iclass 20, count 2 2006.257.23:12:21.61#ibcon#about to read 4, iclass 20, count 2 2006.257.23:12:21.61#ibcon#read 4, iclass 20, count 2 2006.257.23:12:21.61#ibcon#about to read 5, iclass 20, count 2 2006.257.23:12:21.61#ibcon#read 5, iclass 20, count 2 2006.257.23:12:21.61#ibcon#about to read 6, iclass 20, count 2 2006.257.23:12:21.61#ibcon#read 6, iclass 20, count 2 2006.257.23:12:21.61#ibcon#end of sib2, iclass 20, count 2 2006.257.23:12:21.61#ibcon#*after write, iclass 20, count 2 2006.257.23:12:21.61#ibcon#*before return 0, iclass 20, count 2 2006.257.23:12:21.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:21.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:12:21.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.23:12:21.61#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:21.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:21.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:21.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:21.73#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:12:21.73#ibcon#first serial, iclass 20, count 0 2006.257.23:12:21.73#ibcon#enter sib2, iclass 20, count 0 2006.257.23:12:21.73#ibcon#flushed, iclass 20, count 0 2006.257.23:12:21.73#ibcon#about to write, iclass 20, count 0 2006.257.23:12:21.73#ibcon#wrote, iclass 20, count 0 2006.257.23:12:21.73#ibcon#about to read 3, iclass 20, count 0 2006.257.23:12:21.75#ibcon#read 3, iclass 20, count 0 2006.257.23:12:21.75#ibcon#about to read 4, iclass 20, count 0 2006.257.23:12:21.75#ibcon#read 4, iclass 20, count 0 2006.257.23:12:21.75#ibcon#about to read 5, iclass 20, count 0 2006.257.23:12:21.75#ibcon#read 5, iclass 20, count 0 2006.257.23:12:21.75#ibcon#about to read 6, iclass 20, count 0 2006.257.23:12:21.75#ibcon#read 6, iclass 20, count 0 2006.257.23:12:21.75#ibcon#end of sib2, iclass 20, count 0 2006.257.23:12:21.75#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:12:21.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:12:21.75#ibcon#[27=USB\r\n] 2006.257.23:12:21.75#ibcon#*before write, iclass 20, count 0 2006.257.23:12:21.75#ibcon#enter sib2, iclass 20, count 0 2006.257.23:12:21.75#ibcon#flushed, iclass 20, count 0 2006.257.23:12:21.75#ibcon#about to write, iclass 20, count 0 2006.257.23:12:21.75#ibcon#wrote, iclass 20, count 0 2006.257.23:12:21.75#ibcon#about to read 3, iclass 20, count 0 2006.257.23:12:21.78#ibcon#read 3, iclass 20, count 0 2006.257.23:12:21.78#ibcon#about to read 4, iclass 20, count 0 2006.257.23:12:21.78#ibcon#read 4, iclass 20, count 0 2006.257.23:12:21.78#ibcon#about to read 5, iclass 20, count 0 2006.257.23:12:21.78#ibcon#read 5, iclass 20, count 0 2006.257.23:12:21.78#ibcon#about to read 6, iclass 20, count 0 2006.257.23:12:21.78#ibcon#read 6, iclass 20, count 0 2006.257.23:12:21.78#ibcon#end of sib2, iclass 20, count 0 2006.257.23:12:21.78#ibcon#*after write, iclass 20, count 0 2006.257.23:12:21.78#ibcon#*before return 0, iclass 20, count 0 2006.257.23:12:21.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:21.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:12:21.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:12:21.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:12:21.78$vck44/vblo=3,649.99 2006.257.23:12:21.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.23:12:21.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.23:12:21.78#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:21.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:21.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:21.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:21.78#ibcon#enter wrdev, iclass 22, count 0 2006.257.23:12:21.78#ibcon#first serial, iclass 22, count 0 2006.257.23:12:21.78#ibcon#enter sib2, iclass 22, count 0 2006.257.23:12:21.78#ibcon#flushed, iclass 22, count 0 2006.257.23:12:21.78#ibcon#about to write, iclass 22, count 0 2006.257.23:12:21.78#ibcon#wrote, iclass 22, count 0 2006.257.23:12:21.78#ibcon#about to read 3, iclass 22, count 0 2006.257.23:12:21.80#ibcon#read 3, iclass 22, count 0 2006.257.23:12:21.80#ibcon#about to read 4, iclass 22, count 0 2006.257.23:12:21.80#ibcon#read 4, iclass 22, count 0 2006.257.23:12:21.80#ibcon#about to read 5, iclass 22, count 0 2006.257.23:12:21.80#ibcon#read 5, iclass 22, count 0 2006.257.23:12:21.80#ibcon#about to read 6, iclass 22, count 0 2006.257.23:12:21.80#ibcon#read 6, iclass 22, count 0 2006.257.23:12:21.80#ibcon#end of sib2, iclass 22, count 0 2006.257.23:12:21.80#ibcon#*mode == 0, iclass 22, count 0 2006.257.23:12:21.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.23:12:21.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:12:21.80#ibcon#*before write, iclass 22, count 0 2006.257.23:12:21.80#ibcon#enter sib2, iclass 22, count 0 2006.257.23:12:21.80#ibcon#flushed, iclass 22, count 0 2006.257.23:12:21.80#ibcon#about to write, iclass 22, count 0 2006.257.23:12:21.80#ibcon#wrote, iclass 22, count 0 2006.257.23:12:21.80#ibcon#about to read 3, iclass 22, count 0 2006.257.23:12:21.84#ibcon#read 3, iclass 22, count 0 2006.257.23:12:21.84#ibcon#about to read 4, iclass 22, count 0 2006.257.23:12:21.84#ibcon#read 4, iclass 22, count 0 2006.257.23:12:21.84#ibcon#about to read 5, iclass 22, count 0 2006.257.23:12:21.84#ibcon#read 5, iclass 22, count 0 2006.257.23:12:21.84#ibcon#about to read 6, iclass 22, count 0 2006.257.23:12:21.84#ibcon#read 6, iclass 22, count 0 2006.257.23:12:21.84#ibcon#end of sib2, iclass 22, count 0 2006.257.23:12:21.84#ibcon#*after write, iclass 22, count 0 2006.257.23:12:21.84#ibcon#*before return 0, iclass 22, count 0 2006.257.23:12:21.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:21.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:12:21.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.23:12:21.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.23:12:21.84$vck44/vb=3,4 2006.257.23:12:21.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.23:12:21.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.23:12:21.84#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:21.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:21.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:21.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:21.90#ibcon#enter wrdev, iclass 24, count 2 2006.257.23:12:21.90#ibcon#first serial, iclass 24, count 2 2006.257.23:12:21.90#ibcon#enter sib2, iclass 24, count 2 2006.257.23:12:21.90#ibcon#flushed, iclass 24, count 2 2006.257.23:12:21.90#ibcon#about to write, iclass 24, count 2 2006.257.23:12:21.90#ibcon#wrote, iclass 24, count 2 2006.257.23:12:21.90#ibcon#about to read 3, iclass 24, count 2 2006.257.23:12:21.92#ibcon#read 3, iclass 24, count 2 2006.257.23:12:21.92#ibcon#about to read 4, iclass 24, count 2 2006.257.23:12:21.92#ibcon#read 4, iclass 24, count 2 2006.257.23:12:21.92#ibcon#about to read 5, iclass 24, count 2 2006.257.23:12:21.92#ibcon#read 5, iclass 24, count 2 2006.257.23:12:21.92#ibcon#about to read 6, iclass 24, count 2 2006.257.23:12:21.92#ibcon#read 6, iclass 24, count 2 2006.257.23:12:21.92#ibcon#end of sib2, iclass 24, count 2 2006.257.23:12:21.92#ibcon#*mode == 0, iclass 24, count 2 2006.257.23:12:21.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.23:12:21.92#ibcon#[27=AT03-04\r\n] 2006.257.23:12:21.92#ibcon#*before write, iclass 24, count 2 2006.257.23:12:21.92#ibcon#enter sib2, iclass 24, count 2 2006.257.23:12:21.92#ibcon#flushed, iclass 24, count 2 2006.257.23:12:21.92#ibcon#about to write, iclass 24, count 2 2006.257.23:12:21.92#ibcon#wrote, iclass 24, count 2 2006.257.23:12:21.92#ibcon#about to read 3, iclass 24, count 2 2006.257.23:12:21.95#ibcon#read 3, iclass 24, count 2 2006.257.23:12:21.95#ibcon#about to read 4, iclass 24, count 2 2006.257.23:12:21.95#ibcon#read 4, iclass 24, count 2 2006.257.23:12:21.95#ibcon#about to read 5, iclass 24, count 2 2006.257.23:12:21.95#ibcon#read 5, iclass 24, count 2 2006.257.23:12:21.95#ibcon#about to read 6, iclass 24, count 2 2006.257.23:12:21.95#ibcon#read 6, iclass 24, count 2 2006.257.23:12:21.95#ibcon#end of sib2, iclass 24, count 2 2006.257.23:12:21.95#ibcon#*after write, iclass 24, count 2 2006.257.23:12:21.95#ibcon#*before return 0, iclass 24, count 2 2006.257.23:12:21.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:21.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:12:21.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.23:12:21.95#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:21.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:22.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:22.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:22.07#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:12:22.07#ibcon#first serial, iclass 24, count 0 2006.257.23:12:22.07#ibcon#enter sib2, iclass 24, count 0 2006.257.23:12:22.07#ibcon#flushed, iclass 24, count 0 2006.257.23:12:22.07#ibcon#about to write, iclass 24, count 0 2006.257.23:12:22.07#ibcon#wrote, iclass 24, count 0 2006.257.23:12:22.07#ibcon#about to read 3, iclass 24, count 0 2006.257.23:12:22.09#ibcon#read 3, iclass 24, count 0 2006.257.23:12:22.09#ibcon#about to read 4, iclass 24, count 0 2006.257.23:12:22.09#ibcon#read 4, iclass 24, count 0 2006.257.23:12:22.09#ibcon#about to read 5, iclass 24, count 0 2006.257.23:12:22.09#ibcon#read 5, iclass 24, count 0 2006.257.23:12:22.09#ibcon#about to read 6, iclass 24, count 0 2006.257.23:12:22.09#ibcon#read 6, iclass 24, count 0 2006.257.23:12:22.09#ibcon#end of sib2, iclass 24, count 0 2006.257.23:12:22.09#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:12:22.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:12:22.09#ibcon#[27=USB\r\n] 2006.257.23:12:22.09#ibcon#*before write, iclass 24, count 0 2006.257.23:12:22.09#ibcon#enter sib2, iclass 24, count 0 2006.257.23:12:22.09#ibcon#flushed, iclass 24, count 0 2006.257.23:12:22.09#ibcon#about to write, iclass 24, count 0 2006.257.23:12:22.09#ibcon#wrote, iclass 24, count 0 2006.257.23:12:22.09#ibcon#about to read 3, iclass 24, count 0 2006.257.23:12:22.12#ibcon#read 3, iclass 24, count 0 2006.257.23:12:22.12#ibcon#about to read 4, iclass 24, count 0 2006.257.23:12:22.12#ibcon#read 4, iclass 24, count 0 2006.257.23:12:22.12#ibcon#about to read 5, iclass 24, count 0 2006.257.23:12:22.12#ibcon#read 5, iclass 24, count 0 2006.257.23:12:22.12#ibcon#about to read 6, iclass 24, count 0 2006.257.23:12:22.12#ibcon#read 6, iclass 24, count 0 2006.257.23:12:22.12#ibcon#end of sib2, iclass 24, count 0 2006.257.23:12:22.12#ibcon#*after write, iclass 24, count 0 2006.257.23:12:22.12#ibcon#*before return 0, iclass 24, count 0 2006.257.23:12:22.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:22.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:12:22.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:12:22.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:12:22.12$vck44/vblo=4,679.99 2006.257.23:12:22.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.23:12:22.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.23:12:22.12#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:22.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:22.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:22.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:22.12#ibcon#enter wrdev, iclass 26, count 0 2006.257.23:12:22.12#ibcon#first serial, iclass 26, count 0 2006.257.23:12:22.12#ibcon#enter sib2, iclass 26, count 0 2006.257.23:12:22.12#ibcon#flushed, iclass 26, count 0 2006.257.23:12:22.12#ibcon#about to write, iclass 26, count 0 2006.257.23:12:22.12#ibcon#wrote, iclass 26, count 0 2006.257.23:12:22.12#ibcon#about to read 3, iclass 26, count 0 2006.257.23:12:22.14#ibcon#read 3, iclass 26, count 0 2006.257.23:12:22.14#ibcon#about to read 4, iclass 26, count 0 2006.257.23:12:22.14#ibcon#read 4, iclass 26, count 0 2006.257.23:12:22.14#ibcon#about to read 5, iclass 26, count 0 2006.257.23:12:22.14#ibcon#read 5, iclass 26, count 0 2006.257.23:12:22.14#ibcon#about to read 6, iclass 26, count 0 2006.257.23:12:22.14#ibcon#read 6, iclass 26, count 0 2006.257.23:12:22.14#ibcon#end of sib2, iclass 26, count 0 2006.257.23:12:22.14#ibcon#*mode == 0, iclass 26, count 0 2006.257.23:12:22.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.23:12:22.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:12:22.14#ibcon#*before write, iclass 26, count 0 2006.257.23:12:22.14#ibcon#enter sib2, iclass 26, count 0 2006.257.23:12:22.14#ibcon#flushed, iclass 26, count 0 2006.257.23:12:22.14#ibcon#about to write, iclass 26, count 0 2006.257.23:12:22.14#ibcon#wrote, iclass 26, count 0 2006.257.23:12:22.14#ibcon#about to read 3, iclass 26, count 0 2006.257.23:12:22.18#ibcon#read 3, iclass 26, count 0 2006.257.23:12:22.18#ibcon#about to read 4, iclass 26, count 0 2006.257.23:12:22.18#ibcon#read 4, iclass 26, count 0 2006.257.23:12:22.18#ibcon#about to read 5, iclass 26, count 0 2006.257.23:12:22.18#ibcon#read 5, iclass 26, count 0 2006.257.23:12:22.18#ibcon#about to read 6, iclass 26, count 0 2006.257.23:12:22.18#ibcon#read 6, iclass 26, count 0 2006.257.23:12:22.18#ibcon#end of sib2, iclass 26, count 0 2006.257.23:12:22.18#ibcon#*after write, iclass 26, count 0 2006.257.23:12:22.18#ibcon#*before return 0, iclass 26, count 0 2006.257.23:12:22.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:22.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:12:22.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.23:12:22.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.23:12:22.18$vck44/vb=4,5 2006.257.23:12:22.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.23:12:22.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.23:12:22.18#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:22.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:22.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:22.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:22.24#ibcon#enter wrdev, iclass 28, count 2 2006.257.23:12:22.24#ibcon#first serial, iclass 28, count 2 2006.257.23:12:22.24#ibcon#enter sib2, iclass 28, count 2 2006.257.23:12:22.24#ibcon#flushed, iclass 28, count 2 2006.257.23:12:22.24#ibcon#about to write, iclass 28, count 2 2006.257.23:12:22.24#ibcon#wrote, iclass 28, count 2 2006.257.23:12:22.24#ibcon#about to read 3, iclass 28, count 2 2006.257.23:12:22.26#ibcon#read 3, iclass 28, count 2 2006.257.23:12:22.26#ibcon#about to read 4, iclass 28, count 2 2006.257.23:12:22.26#ibcon#read 4, iclass 28, count 2 2006.257.23:12:22.26#ibcon#about to read 5, iclass 28, count 2 2006.257.23:12:22.26#ibcon#read 5, iclass 28, count 2 2006.257.23:12:22.26#ibcon#about to read 6, iclass 28, count 2 2006.257.23:12:22.26#ibcon#read 6, iclass 28, count 2 2006.257.23:12:22.26#ibcon#end of sib2, iclass 28, count 2 2006.257.23:12:22.26#ibcon#*mode == 0, iclass 28, count 2 2006.257.23:12:22.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.23:12:22.26#ibcon#[27=AT04-05\r\n] 2006.257.23:12:22.26#ibcon#*before write, iclass 28, count 2 2006.257.23:12:22.26#ibcon#enter sib2, iclass 28, count 2 2006.257.23:12:22.26#ibcon#flushed, iclass 28, count 2 2006.257.23:12:22.26#ibcon#about to write, iclass 28, count 2 2006.257.23:12:22.26#ibcon#wrote, iclass 28, count 2 2006.257.23:12:22.26#ibcon#about to read 3, iclass 28, count 2 2006.257.23:12:22.29#ibcon#read 3, iclass 28, count 2 2006.257.23:12:22.29#ibcon#about to read 4, iclass 28, count 2 2006.257.23:12:22.29#ibcon#read 4, iclass 28, count 2 2006.257.23:12:22.29#ibcon#about to read 5, iclass 28, count 2 2006.257.23:12:22.29#ibcon#read 5, iclass 28, count 2 2006.257.23:12:22.29#ibcon#about to read 6, iclass 28, count 2 2006.257.23:12:22.29#ibcon#read 6, iclass 28, count 2 2006.257.23:12:22.29#ibcon#end of sib2, iclass 28, count 2 2006.257.23:12:22.29#ibcon#*after write, iclass 28, count 2 2006.257.23:12:22.29#ibcon#*before return 0, iclass 28, count 2 2006.257.23:12:22.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:22.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:12:22.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.23:12:22.29#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:22.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:22.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:22.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:22.41#ibcon#enter wrdev, iclass 28, count 0 2006.257.23:12:22.41#ibcon#first serial, iclass 28, count 0 2006.257.23:12:22.41#ibcon#enter sib2, iclass 28, count 0 2006.257.23:12:22.41#ibcon#flushed, iclass 28, count 0 2006.257.23:12:22.41#ibcon#about to write, iclass 28, count 0 2006.257.23:12:22.41#ibcon#wrote, iclass 28, count 0 2006.257.23:12:22.41#ibcon#about to read 3, iclass 28, count 0 2006.257.23:12:22.43#ibcon#read 3, iclass 28, count 0 2006.257.23:12:22.43#ibcon#about to read 4, iclass 28, count 0 2006.257.23:12:22.43#ibcon#read 4, iclass 28, count 0 2006.257.23:12:22.43#ibcon#about to read 5, iclass 28, count 0 2006.257.23:12:22.43#ibcon#read 5, iclass 28, count 0 2006.257.23:12:22.43#ibcon#about to read 6, iclass 28, count 0 2006.257.23:12:22.43#ibcon#read 6, iclass 28, count 0 2006.257.23:12:22.43#ibcon#end of sib2, iclass 28, count 0 2006.257.23:12:22.43#ibcon#*mode == 0, iclass 28, count 0 2006.257.23:12:22.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.23:12:22.43#ibcon#[27=USB\r\n] 2006.257.23:12:22.43#ibcon#*before write, iclass 28, count 0 2006.257.23:12:22.43#ibcon#enter sib2, iclass 28, count 0 2006.257.23:12:22.43#ibcon#flushed, iclass 28, count 0 2006.257.23:12:22.43#ibcon#about to write, iclass 28, count 0 2006.257.23:12:22.43#ibcon#wrote, iclass 28, count 0 2006.257.23:12:22.43#ibcon#about to read 3, iclass 28, count 0 2006.257.23:12:22.46#ibcon#read 3, iclass 28, count 0 2006.257.23:12:22.46#ibcon#about to read 4, iclass 28, count 0 2006.257.23:12:22.46#ibcon#read 4, iclass 28, count 0 2006.257.23:12:22.46#ibcon#about to read 5, iclass 28, count 0 2006.257.23:12:22.46#ibcon#read 5, iclass 28, count 0 2006.257.23:12:22.46#ibcon#about to read 6, iclass 28, count 0 2006.257.23:12:22.46#ibcon#read 6, iclass 28, count 0 2006.257.23:12:22.46#ibcon#end of sib2, iclass 28, count 0 2006.257.23:12:22.46#ibcon#*after write, iclass 28, count 0 2006.257.23:12:22.46#ibcon#*before return 0, iclass 28, count 0 2006.257.23:12:22.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:22.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:12:22.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.23:12:22.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.23:12:22.46$vck44/vblo=5,709.99 2006.257.23:12:22.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.23:12:22.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.23:12:22.46#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:22.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:22.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:22.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:22.46#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:12:22.46#ibcon#first serial, iclass 30, count 0 2006.257.23:12:22.46#ibcon#enter sib2, iclass 30, count 0 2006.257.23:12:22.46#ibcon#flushed, iclass 30, count 0 2006.257.23:12:22.46#ibcon#about to write, iclass 30, count 0 2006.257.23:12:22.46#ibcon#wrote, iclass 30, count 0 2006.257.23:12:22.46#ibcon#about to read 3, iclass 30, count 0 2006.257.23:12:22.48#ibcon#read 3, iclass 30, count 0 2006.257.23:12:22.48#ibcon#about to read 4, iclass 30, count 0 2006.257.23:12:22.48#ibcon#read 4, iclass 30, count 0 2006.257.23:12:22.48#ibcon#about to read 5, iclass 30, count 0 2006.257.23:12:22.48#ibcon#read 5, iclass 30, count 0 2006.257.23:12:22.48#ibcon#about to read 6, iclass 30, count 0 2006.257.23:12:22.48#ibcon#read 6, iclass 30, count 0 2006.257.23:12:22.48#ibcon#end of sib2, iclass 30, count 0 2006.257.23:12:22.48#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:12:22.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:12:22.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:12:22.48#ibcon#*before write, iclass 30, count 0 2006.257.23:12:22.48#ibcon#enter sib2, iclass 30, count 0 2006.257.23:12:22.48#ibcon#flushed, iclass 30, count 0 2006.257.23:12:22.48#ibcon#about to write, iclass 30, count 0 2006.257.23:12:22.48#ibcon#wrote, iclass 30, count 0 2006.257.23:12:22.48#ibcon#about to read 3, iclass 30, count 0 2006.257.23:12:22.52#ibcon#read 3, iclass 30, count 0 2006.257.23:12:22.52#ibcon#about to read 4, iclass 30, count 0 2006.257.23:12:22.52#ibcon#read 4, iclass 30, count 0 2006.257.23:12:22.52#ibcon#about to read 5, iclass 30, count 0 2006.257.23:12:22.52#ibcon#read 5, iclass 30, count 0 2006.257.23:12:22.52#ibcon#about to read 6, iclass 30, count 0 2006.257.23:12:22.52#ibcon#read 6, iclass 30, count 0 2006.257.23:12:22.52#ibcon#end of sib2, iclass 30, count 0 2006.257.23:12:22.52#ibcon#*after write, iclass 30, count 0 2006.257.23:12:22.52#ibcon#*before return 0, iclass 30, count 0 2006.257.23:12:22.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:22.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:12:22.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:12:22.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:12:22.52$vck44/vb=5,4 2006.257.23:12:22.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.23:12:22.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.23:12:22.52#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:22.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:22.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:22.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:22.58#ibcon#enter wrdev, iclass 32, count 2 2006.257.23:12:22.58#ibcon#first serial, iclass 32, count 2 2006.257.23:12:22.58#ibcon#enter sib2, iclass 32, count 2 2006.257.23:12:22.58#ibcon#flushed, iclass 32, count 2 2006.257.23:12:22.58#ibcon#about to write, iclass 32, count 2 2006.257.23:12:22.58#ibcon#wrote, iclass 32, count 2 2006.257.23:12:22.58#ibcon#about to read 3, iclass 32, count 2 2006.257.23:12:22.60#ibcon#read 3, iclass 32, count 2 2006.257.23:12:22.60#ibcon#about to read 4, iclass 32, count 2 2006.257.23:12:22.60#ibcon#read 4, iclass 32, count 2 2006.257.23:12:22.60#ibcon#about to read 5, iclass 32, count 2 2006.257.23:12:22.60#ibcon#read 5, iclass 32, count 2 2006.257.23:12:22.60#ibcon#about to read 6, iclass 32, count 2 2006.257.23:12:22.60#ibcon#read 6, iclass 32, count 2 2006.257.23:12:22.60#ibcon#end of sib2, iclass 32, count 2 2006.257.23:12:22.60#ibcon#*mode == 0, iclass 32, count 2 2006.257.23:12:22.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.23:12:22.60#ibcon#[27=AT05-04\r\n] 2006.257.23:12:22.60#ibcon#*before write, iclass 32, count 2 2006.257.23:12:22.60#ibcon#enter sib2, iclass 32, count 2 2006.257.23:12:22.60#ibcon#flushed, iclass 32, count 2 2006.257.23:12:22.60#ibcon#about to write, iclass 32, count 2 2006.257.23:12:22.60#ibcon#wrote, iclass 32, count 2 2006.257.23:12:22.60#ibcon#about to read 3, iclass 32, count 2 2006.257.23:12:22.63#ibcon#read 3, iclass 32, count 2 2006.257.23:12:22.63#ibcon#about to read 4, iclass 32, count 2 2006.257.23:12:22.63#ibcon#read 4, iclass 32, count 2 2006.257.23:12:22.63#ibcon#about to read 5, iclass 32, count 2 2006.257.23:12:22.63#ibcon#read 5, iclass 32, count 2 2006.257.23:12:22.63#ibcon#about to read 6, iclass 32, count 2 2006.257.23:12:22.63#ibcon#read 6, iclass 32, count 2 2006.257.23:12:22.63#ibcon#end of sib2, iclass 32, count 2 2006.257.23:12:22.63#ibcon#*after write, iclass 32, count 2 2006.257.23:12:22.63#ibcon#*before return 0, iclass 32, count 2 2006.257.23:12:22.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:22.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:12:22.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.23:12:22.63#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:22.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:22.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:22.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:22.75#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:12:22.75#ibcon#first serial, iclass 32, count 0 2006.257.23:12:22.75#ibcon#enter sib2, iclass 32, count 0 2006.257.23:12:22.75#ibcon#flushed, iclass 32, count 0 2006.257.23:12:22.75#ibcon#about to write, iclass 32, count 0 2006.257.23:12:22.75#ibcon#wrote, iclass 32, count 0 2006.257.23:12:22.75#ibcon#about to read 3, iclass 32, count 0 2006.257.23:12:22.77#ibcon#read 3, iclass 32, count 0 2006.257.23:12:22.77#ibcon#about to read 4, iclass 32, count 0 2006.257.23:12:22.77#ibcon#read 4, iclass 32, count 0 2006.257.23:12:22.77#ibcon#about to read 5, iclass 32, count 0 2006.257.23:12:22.77#ibcon#read 5, iclass 32, count 0 2006.257.23:12:22.77#ibcon#about to read 6, iclass 32, count 0 2006.257.23:12:22.77#ibcon#read 6, iclass 32, count 0 2006.257.23:12:22.77#ibcon#end of sib2, iclass 32, count 0 2006.257.23:12:22.77#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:12:22.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:12:22.77#ibcon#[27=USB\r\n] 2006.257.23:12:22.77#ibcon#*before write, iclass 32, count 0 2006.257.23:12:22.77#ibcon#enter sib2, iclass 32, count 0 2006.257.23:12:22.77#ibcon#flushed, iclass 32, count 0 2006.257.23:12:22.77#ibcon#about to write, iclass 32, count 0 2006.257.23:12:22.77#ibcon#wrote, iclass 32, count 0 2006.257.23:12:22.77#ibcon#about to read 3, iclass 32, count 0 2006.257.23:12:22.80#ibcon#read 3, iclass 32, count 0 2006.257.23:12:22.80#ibcon#about to read 4, iclass 32, count 0 2006.257.23:12:22.80#ibcon#read 4, iclass 32, count 0 2006.257.23:12:22.80#ibcon#about to read 5, iclass 32, count 0 2006.257.23:12:22.80#ibcon#read 5, iclass 32, count 0 2006.257.23:12:22.80#ibcon#about to read 6, iclass 32, count 0 2006.257.23:12:22.80#ibcon#read 6, iclass 32, count 0 2006.257.23:12:22.80#ibcon#end of sib2, iclass 32, count 0 2006.257.23:12:22.80#ibcon#*after write, iclass 32, count 0 2006.257.23:12:22.80#ibcon#*before return 0, iclass 32, count 0 2006.257.23:12:22.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:22.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:12:22.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:12:22.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:12:22.80$vck44/vblo=6,719.99 2006.257.23:12:22.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.23:12:22.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.23:12:22.80#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:22.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:22.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:22.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:22.80#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:12:22.80#ibcon#first serial, iclass 34, count 0 2006.257.23:12:22.80#ibcon#enter sib2, iclass 34, count 0 2006.257.23:12:22.80#ibcon#flushed, iclass 34, count 0 2006.257.23:12:22.80#ibcon#about to write, iclass 34, count 0 2006.257.23:12:22.80#ibcon#wrote, iclass 34, count 0 2006.257.23:12:22.80#ibcon#about to read 3, iclass 34, count 0 2006.257.23:12:22.82#ibcon#read 3, iclass 34, count 0 2006.257.23:12:22.82#ibcon#about to read 4, iclass 34, count 0 2006.257.23:12:22.82#ibcon#read 4, iclass 34, count 0 2006.257.23:12:22.82#ibcon#about to read 5, iclass 34, count 0 2006.257.23:12:22.82#ibcon#read 5, iclass 34, count 0 2006.257.23:12:22.82#ibcon#about to read 6, iclass 34, count 0 2006.257.23:12:22.82#ibcon#read 6, iclass 34, count 0 2006.257.23:12:22.82#ibcon#end of sib2, iclass 34, count 0 2006.257.23:12:22.82#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:12:22.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:12:22.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:12:22.82#ibcon#*before write, iclass 34, count 0 2006.257.23:12:22.82#ibcon#enter sib2, iclass 34, count 0 2006.257.23:12:22.82#ibcon#flushed, iclass 34, count 0 2006.257.23:12:22.82#ibcon#about to write, iclass 34, count 0 2006.257.23:12:22.82#ibcon#wrote, iclass 34, count 0 2006.257.23:12:22.82#ibcon#about to read 3, iclass 34, count 0 2006.257.23:12:22.86#ibcon#read 3, iclass 34, count 0 2006.257.23:12:22.86#ibcon#about to read 4, iclass 34, count 0 2006.257.23:12:22.86#ibcon#read 4, iclass 34, count 0 2006.257.23:12:22.86#ibcon#about to read 5, iclass 34, count 0 2006.257.23:12:22.86#ibcon#read 5, iclass 34, count 0 2006.257.23:12:22.86#ibcon#about to read 6, iclass 34, count 0 2006.257.23:12:22.86#ibcon#read 6, iclass 34, count 0 2006.257.23:12:22.86#ibcon#end of sib2, iclass 34, count 0 2006.257.23:12:22.86#ibcon#*after write, iclass 34, count 0 2006.257.23:12:22.86#ibcon#*before return 0, iclass 34, count 0 2006.257.23:12:22.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:22.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:12:22.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:12:22.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:12:22.86$vck44/vb=6,4 2006.257.23:12:22.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.23:12:22.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.23:12:22.86#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:22.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:22.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:22.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:22.92#ibcon#enter wrdev, iclass 36, count 2 2006.257.23:12:22.92#ibcon#first serial, iclass 36, count 2 2006.257.23:12:22.92#ibcon#enter sib2, iclass 36, count 2 2006.257.23:12:22.92#ibcon#flushed, iclass 36, count 2 2006.257.23:12:22.92#ibcon#about to write, iclass 36, count 2 2006.257.23:12:22.92#ibcon#wrote, iclass 36, count 2 2006.257.23:12:22.92#ibcon#about to read 3, iclass 36, count 2 2006.257.23:12:22.94#ibcon#read 3, iclass 36, count 2 2006.257.23:12:22.94#ibcon#about to read 4, iclass 36, count 2 2006.257.23:12:22.94#ibcon#read 4, iclass 36, count 2 2006.257.23:12:22.94#ibcon#about to read 5, iclass 36, count 2 2006.257.23:12:22.94#ibcon#read 5, iclass 36, count 2 2006.257.23:12:22.94#ibcon#about to read 6, iclass 36, count 2 2006.257.23:12:22.94#ibcon#read 6, iclass 36, count 2 2006.257.23:12:22.94#ibcon#end of sib2, iclass 36, count 2 2006.257.23:12:22.94#ibcon#*mode == 0, iclass 36, count 2 2006.257.23:12:22.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.23:12:22.94#ibcon#[27=AT06-04\r\n] 2006.257.23:12:22.94#ibcon#*before write, iclass 36, count 2 2006.257.23:12:22.94#ibcon#enter sib2, iclass 36, count 2 2006.257.23:12:22.94#ibcon#flushed, iclass 36, count 2 2006.257.23:12:22.94#ibcon#about to write, iclass 36, count 2 2006.257.23:12:22.94#ibcon#wrote, iclass 36, count 2 2006.257.23:12:22.94#ibcon#about to read 3, iclass 36, count 2 2006.257.23:12:22.97#ibcon#read 3, iclass 36, count 2 2006.257.23:12:22.97#ibcon#about to read 4, iclass 36, count 2 2006.257.23:12:22.97#ibcon#read 4, iclass 36, count 2 2006.257.23:12:22.97#ibcon#about to read 5, iclass 36, count 2 2006.257.23:12:22.97#ibcon#read 5, iclass 36, count 2 2006.257.23:12:22.97#ibcon#about to read 6, iclass 36, count 2 2006.257.23:12:22.97#ibcon#read 6, iclass 36, count 2 2006.257.23:12:22.97#ibcon#end of sib2, iclass 36, count 2 2006.257.23:12:22.97#ibcon#*after write, iclass 36, count 2 2006.257.23:12:22.97#ibcon#*before return 0, iclass 36, count 2 2006.257.23:12:22.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:22.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:12:22.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.23:12:22.97#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:22.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:23.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:23.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:23.09#ibcon#enter wrdev, iclass 36, count 0 2006.257.23:12:23.09#ibcon#first serial, iclass 36, count 0 2006.257.23:12:23.09#ibcon#enter sib2, iclass 36, count 0 2006.257.23:12:23.09#ibcon#flushed, iclass 36, count 0 2006.257.23:12:23.09#ibcon#about to write, iclass 36, count 0 2006.257.23:12:23.09#ibcon#wrote, iclass 36, count 0 2006.257.23:12:23.09#ibcon#about to read 3, iclass 36, count 0 2006.257.23:12:23.11#ibcon#read 3, iclass 36, count 0 2006.257.23:12:23.11#ibcon#about to read 4, iclass 36, count 0 2006.257.23:12:23.11#ibcon#read 4, iclass 36, count 0 2006.257.23:12:23.11#ibcon#about to read 5, iclass 36, count 0 2006.257.23:12:23.11#ibcon#read 5, iclass 36, count 0 2006.257.23:12:23.11#ibcon#about to read 6, iclass 36, count 0 2006.257.23:12:23.11#ibcon#read 6, iclass 36, count 0 2006.257.23:12:23.11#ibcon#end of sib2, iclass 36, count 0 2006.257.23:12:23.11#ibcon#*mode == 0, iclass 36, count 0 2006.257.23:12:23.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.23:12:23.11#ibcon#[27=USB\r\n] 2006.257.23:12:23.11#ibcon#*before write, iclass 36, count 0 2006.257.23:12:23.11#ibcon#enter sib2, iclass 36, count 0 2006.257.23:12:23.11#ibcon#flushed, iclass 36, count 0 2006.257.23:12:23.11#ibcon#about to write, iclass 36, count 0 2006.257.23:12:23.11#ibcon#wrote, iclass 36, count 0 2006.257.23:12:23.11#ibcon#about to read 3, iclass 36, count 0 2006.257.23:12:23.14#ibcon#read 3, iclass 36, count 0 2006.257.23:12:23.14#ibcon#about to read 4, iclass 36, count 0 2006.257.23:12:23.14#ibcon#read 4, iclass 36, count 0 2006.257.23:12:23.14#ibcon#about to read 5, iclass 36, count 0 2006.257.23:12:23.14#ibcon#read 5, iclass 36, count 0 2006.257.23:12:23.14#ibcon#about to read 6, iclass 36, count 0 2006.257.23:12:23.14#ibcon#read 6, iclass 36, count 0 2006.257.23:12:23.14#ibcon#end of sib2, iclass 36, count 0 2006.257.23:12:23.14#ibcon#*after write, iclass 36, count 0 2006.257.23:12:23.14#ibcon#*before return 0, iclass 36, count 0 2006.257.23:12:23.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:23.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:12:23.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.23:12:23.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.23:12:23.14$vck44/vblo=7,734.99 2006.257.23:12:23.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.23:12:23.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.23:12:23.14#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:23.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:23.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:23.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:23.14#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:12:23.14#ibcon#first serial, iclass 38, count 0 2006.257.23:12:23.14#ibcon#enter sib2, iclass 38, count 0 2006.257.23:12:23.14#ibcon#flushed, iclass 38, count 0 2006.257.23:12:23.14#ibcon#about to write, iclass 38, count 0 2006.257.23:12:23.14#ibcon#wrote, iclass 38, count 0 2006.257.23:12:23.14#ibcon#about to read 3, iclass 38, count 0 2006.257.23:12:23.16#ibcon#read 3, iclass 38, count 0 2006.257.23:12:23.16#ibcon#about to read 4, iclass 38, count 0 2006.257.23:12:23.16#ibcon#read 4, iclass 38, count 0 2006.257.23:12:23.16#ibcon#about to read 5, iclass 38, count 0 2006.257.23:12:23.16#ibcon#read 5, iclass 38, count 0 2006.257.23:12:23.16#ibcon#about to read 6, iclass 38, count 0 2006.257.23:12:23.16#ibcon#read 6, iclass 38, count 0 2006.257.23:12:23.16#ibcon#end of sib2, iclass 38, count 0 2006.257.23:12:23.16#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:12:23.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:12:23.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:12:23.16#ibcon#*before write, iclass 38, count 0 2006.257.23:12:23.16#ibcon#enter sib2, iclass 38, count 0 2006.257.23:12:23.16#ibcon#flushed, iclass 38, count 0 2006.257.23:12:23.16#ibcon#about to write, iclass 38, count 0 2006.257.23:12:23.16#ibcon#wrote, iclass 38, count 0 2006.257.23:12:23.16#ibcon#about to read 3, iclass 38, count 0 2006.257.23:12:23.20#ibcon#read 3, iclass 38, count 0 2006.257.23:12:23.20#ibcon#about to read 4, iclass 38, count 0 2006.257.23:12:23.20#ibcon#read 4, iclass 38, count 0 2006.257.23:12:23.20#ibcon#about to read 5, iclass 38, count 0 2006.257.23:12:23.20#ibcon#read 5, iclass 38, count 0 2006.257.23:12:23.20#ibcon#about to read 6, iclass 38, count 0 2006.257.23:12:23.20#ibcon#read 6, iclass 38, count 0 2006.257.23:12:23.20#ibcon#end of sib2, iclass 38, count 0 2006.257.23:12:23.20#ibcon#*after write, iclass 38, count 0 2006.257.23:12:23.20#ibcon#*before return 0, iclass 38, count 0 2006.257.23:12:23.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:23.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:12:23.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:12:23.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:12:23.20$vck44/vb=7,4 2006.257.23:12:23.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.23:12:23.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.23:12:23.20#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:23.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:23.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:23.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:23.26#ibcon#enter wrdev, iclass 40, count 2 2006.257.23:12:23.26#ibcon#first serial, iclass 40, count 2 2006.257.23:12:23.26#ibcon#enter sib2, iclass 40, count 2 2006.257.23:12:23.26#ibcon#flushed, iclass 40, count 2 2006.257.23:12:23.26#ibcon#about to write, iclass 40, count 2 2006.257.23:12:23.26#ibcon#wrote, iclass 40, count 2 2006.257.23:12:23.26#ibcon#about to read 3, iclass 40, count 2 2006.257.23:12:23.28#ibcon#read 3, iclass 40, count 2 2006.257.23:12:23.28#ibcon#about to read 4, iclass 40, count 2 2006.257.23:12:23.28#ibcon#read 4, iclass 40, count 2 2006.257.23:12:23.28#ibcon#about to read 5, iclass 40, count 2 2006.257.23:12:23.28#ibcon#read 5, iclass 40, count 2 2006.257.23:12:23.28#ibcon#about to read 6, iclass 40, count 2 2006.257.23:12:23.28#ibcon#read 6, iclass 40, count 2 2006.257.23:12:23.28#ibcon#end of sib2, iclass 40, count 2 2006.257.23:12:23.28#ibcon#*mode == 0, iclass 40, count 2 2006.257.23:12:23.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.23:12:23.28#ibcon#[27=AT07-04\r\n] 2006.257.23:12:23.28#ibcon#*before write, iclass 40, count 2 2006.257.23:12:23.28#ibcon#enter sib2, iclass 40, count 2 2006.257.23:12:23.28#ibcon#flushed, iclass 40, count 2 2006.257.23:12:23.28#ibcon#about to write, iclass 40, count 2 2006.257.23:12:23.28#ibcon#wrote, iclass 40, count 2 2006.257.23:12:23.28#ibcon#about to read 3, iclass 40, count 2 2006.257.23:12:23.31#ibcon#read 3, iclass 40, count 2 2006.257.23:12:23.31#ibcon#about to read 4, iclass 40, count 2 2006.257.23:12:23.31#ibcon#read 4, iclass 40, count 2 2006.257.23:12:23.31#ibcon#about to read 5, iclass 40, count 2 2006.257.23:12:23.31#ibcon#read 5, iclass 40, count 2 2006.257.23:12:23.31#ibcon#about to read 6, iclass 40, count 2 2006.257.23:12:23.31#ibcon#read 6, iclass 40, count 2 2006.257.23:12:23.31#ibcon#end of sib2, iclass 40, count 2 2006.257.23:12:23.31#ibcon#*after write, iclass 40, count 2 2006.257.23:12:23.31#ibcon#*before return 0, iclass 40, count 2 2006.257.23:12:23.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:23.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:12:23.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.23:12:23.31#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:23.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:23.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:23.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:23.43#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:12:23.43#ibcon#first serial, iclass 40, count 0 2006.257.23:12:23.43#ibcon#enter sib2, iclass 40, count 0 2006.257.23:12:23.43#ibcon#flushed, iclass 40, count 0 2006.257.23:12:23.43#ibcon#about to write, iclass 40, count 0 2006.257.23:12:23.43#ibcon#wrote, iclass 40, count 0 2006.257.23:12:23.43#ibcon#about to read 3, iclass 40, count 0 2006.257.23:12:23.45#ibcon#read 3, iclass 40, count 0 2006.257.23:12:23.45#ibcon#about to read 4, iclass 40, count 0 2006.257.23:12:23.45#ibcon#read 4, iclass 40, count 0 2006.257.23:12:23.45#ibcon#about to read 5, iclass 40, count 0 2006.257.23:12:23.45#ibcon#read 5, iclass 40, count 0 2006.257.23:12:23.45#ibcon#about to read 6, iclass 40, count 0 2006.257.23:12:23.45#ibcon#read 6, iclass 40, count 0 2006.257.23:12:23.45#ibcon#end of sib2, iclass 40, count 0 2006.257.23:12:23.45#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:12:23.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:12:23.45#ibcon#[27=USB\r\n] 2006.257.23:12:23.45#ibcon#*before write, iclass 40, count 0 2006.257.23:12:23.45#ibcon#enter sib2, iclass 40, count 0 2006.257.23:12:23.45#ibcon#flushed, iclass 40, count 0 2006.257.23:12:23.45#ibcon#about to write, iclass 40, count 0 2006.257.23:12:23.45#ibcon#wrote, iclass 40, count 0 2006.257.23:12:23.45#ibcon#about to read 3, iclass 40, count 0 2006.257.23:12:23.48#ibcon#read 3, iclass 40, count 0 2006.257.23:12:23.48#ibcon#about to read 4, iclass 40, count 0 2006.257.23:12:23.48#ibcon#read 4, iclass 40, count 0 2006.257.23:12:23.48#ibcon#about to read 5, iclass 40, count 0 2006.257.23:12:23.48#ibcon#read 5, iclass 40, count 0 2006.257.23:12:23.48#ibcon#about to read 6, iclass 40, count 0 2006.257.23:12:23.48#ibcon#read 6, iclass 40, count 0 2006.257.23:12:23.48#ibcon#end of sib2, iclass 40, count 0 2006.257.23:12:23.48#ibcon#*after write, iclass 40, count 0 2006.257.23:12:23.48#ibcon#*before return 0, iclass 40, count 0 2006.257.23:12:23.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:23.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:12:23.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:12:23.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:12:23.48$vck44/vblo=8,744.99 2006.257.23:12:23.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.23:12:23.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.23:12:23.48#ibcon#ireg 17 cls_cnt 0 2006.257.23:12:23.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:23.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:23.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:23.48#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:12:23.48#ibcon#first serial, iclass 4, count 0 2006.257.23:12:23.48#ibcon#enter sib2, iclass 4, count 0 2006.257.23:12:23.48#ibcon#flushed, iclass 4, count 0 2006.257.23:12:23.48#ibcon#about to write, iclass 4, count 0 2006.257.23:12:23.48#ibcon#wrote, iclass 4, count 0 2006.257.23:12:23.48#ibcon#about to read 3, iclass 4, count 0 2006.257.23:12:23.50#ibcon#read 3, iclass 4, count 0 2006.257.23:12:23.50#ibcon#about to read 4, iclass 4, count 0 2006.257.23:12:23.50#ibcon#read 4, iclass 4, count 0 2006.257.23:12:23.50#ibcon#about to read 5, iclass 4, count 0 2006.257.23:12:23.50#ibcon#read 5, iclass 4, count 0 2006.257.23:12:23.50#ibcon#about to read 6, iclass 4, count 0 2006.257.23:12:23.50#ibcon#read 6, iclass 4, count 0 2006.257.23:12:23.50#ibcon#end of sib2, iclass 4, count 0 2006.257.23:12:23.50#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:12:23.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:12:23.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:12:23.50#ibcon#*before write, iclass 4, count 0 2006.257.23:12:23.50#ibcon#enter sib2, iclass 4, count 0 2006.257.23:12:23.50#ibcon#flushed, iclass 4, count 0 2006.257.23:12:23.50#ibcon#about to write, iclass 4, count 0 2006.257.23:12:23.50#ibcon#wrote, iclass 4, count 0 2006.257.23:12:23.50#ibcon#about to read 3, iclass 4, count 0 2006.257.23:12:23.54#ibcon#read 3, iclass 4, count 0 2006.257.23:12:23.54#ibcon#about to read 4, iclass 4, count 0 2006.257.23:12:23.54#ibcon#read 4, iclass 4, count 0 2006.257.23:12:23.54#ibcon#about to read 5, iclass 4, count 0 2006.257.23:12:23.54#ibcon#read 5, iclass 4, count 0 2006.257.23:12:23.54#ibcon#about to read 6, iclass 4, count 0 2006.257.23:12:23.54#ibcon#read 6, iclass 4, count 0 2006.257.23:12:23.54#ibcon#end of sib2, iclass 4, count 0 2006.257.23:12:23.54#ibcon#*after write, iclass 4, count 0 2006.257.23:12:23.54#ibcon#*before return 0, iclass 4, count 0 2006.257.23:12:23.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:23.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:12:23.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:12:23.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:12:23.54$vck44/vb=8,4 2006.257.23:12:23.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.23:12:23.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.23:12:23.54#ibcon#ireg 11 cls_cnt 2 2006.257.23:12:23.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:23.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:23.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:23.60#ibcon#enter wrdev, iclass 6, count 2 2006.257.23:12:23.60#ibcon#first serial, iclass 6, count 2 2006.257.23:12:23.60#ibcon#enter sib2, iclass 6, count 2 2006.257.23:12:23.60#ibcon#flushed, iclass 6, count 2 2006.257.23:12:23.60#ibcon#about to write, iclass 6, count 2 2006.257.23:12:23.60#ibcon#wrote, iclass 6, count 2 2006.257.23:12:23.60#ibcon#about to read 3, iclass 6, count 2 2006.257.23:12:23.62#ibcon#read 3, iclass 6, count 2 2006.257.23:12:23.62#ibcon#about to read 4, iclass 6, count 2 2006.257.23:12:23.62#ibcon#read 4, iclass 6, count 2 2006.257.23:12:23.62#ibcon#about to read 5, iclass 6, count 2 2006.257.23:12:23.62#ibcon#read 5, iclass 6, count 2 2006.257.23:12:23.62#ibcon#about to read 6, iclass 6, count 2 2006.257.23:12:23.62#ibcon#read 6, iclass 6, count 2 2006.257.23:12:23.62#ibcon#end of sib2, iclass 6, count 2 2006.257.23:12:23.62#ibcon#*mode == 0, iclass 6, count 2 2006.257.23:12:23.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.23:12:23.62#ibcon#[27=AT08-04\r\n] 2006.257.23:12:23.62#ibcon#*before write, iclass 6, count 2 2006.257.23:12:23.62#ibcon#enter sib2, iclass 6, count 2 2006.257.23:12:23.62#ibcon#flushed, iclass 6, count 2 2006.257.23:12:23.62#ibcon#about to write, iclass 6, count 2 2006.257.23:12:23.62#ibcon#wrote, iclass 6, count 2 2006.257.23:12:23.62#ibcon#about to read 3, iclass 6, count 2 2006.257.23:12:23.65#ibcon#read 3, iclass 6, count 2 2006.257.23:12:23.65#ibcon#about to read 4, iclass 6, count 2 2006.257.23:12:23.65#ibcon#read 4, iclass 6, count 2 2006.257.23:12:23.65#ibcon#about to read 5, iclass 6, count 2 2006.257.23:12:23.65#ibcon#read 5, iclass 6, count 2 2006.257.23:12:23.65#ibcon#about to read 6, iclass 6, count 2 2006.257.23:12:23.65#ibcon#read 6, iclass 6, count 2 2006.257.23:12:23.65#ibcon#end of sib2, iclass 6, count 2 2006.257.23:12:23.65#ibcon#*after write, iclass 6, count 2 2006.257.23:12:23.65#ibcon#*before return 0, iclass 6, count 2 2006.257.23:12:23.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:23.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:12:23.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.23:12:23.65#ibcon#ireg 7 cls_cnt 0 2006.257.23:12:23.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:23.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:23.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:23.77#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:12:23.77#ibcon#first serial, iclass 6, count 0 2006.257.23:12:23.77#ibcon#enter sib2, iclass 6, count 0 2006.257.23:12:23.77#ibcon#flushed, iclass 6, count 0 2006.257.23:12:23.77#ibcon#about to write, iclass 6, count 0 2006.257.23:12:23.77#ibcon#wrote, iclass 6, count 0 2006.257.23:12:23.77#ibcon#about to read 3, iclass 6, count 0 2006.257.23:12:23.79#ibcon#read 3, iclass 6, count 0 2006.257.23:12:23.79#ibcon#about to read 4, iclass 6, count 0 2006.257.23:12:23.79#ibcon#read 4, iclass 6, count 0 2006.257.23:12:23.79#ibcon#about to read 5, iclass 6, count 0 2006.257.23:12:23.79#ibcon#read 5, iclass 6, count 0 2006.257.23:12:23.79#ibcon#about to read 6, iclass 6, count 0 2006.257.23:12:23.79#ibcon#read 6, iclass 6, count 0 2006.257.23:12:23.79#ibcon#end of sib2, iclass 6, count 0 2006.257.23:12:23.79#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:12:23.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:12:23.79#ibcon#[27=USB\r\n] 2006.257.23:12:23.79#ibcon#*before write, iclass 6, count 0 2006.257.23:12:23.79#ibcon#enter sib2, iclass 6, count 0 2006.257.23:12:23.79#ibcon#flushed, iclass 6, count 0 2006.257.23:12:23.79#ibcon#about to write, iclass 6, count 0 2006.257.23:12:23.79#ibcon#wrote, iclass 6, count 0 2006.257.23:12:23.79#ibcon#about to read 3, iclass 6, count 0 2006.257.23:12:23.82#ibcon#read 3, iclass 6, count 0 2006.257.23:12:23.82#ibcon#about to read 4, iclass 6, count 0 2006.257.23:12:23.82#ibcon#read 4, iclass 6, count 0 2006.257.23:12:23.82#ibcon#about to read 5, iclass 6, count 0 2006.257.23:12:23.82#ibcon#read 5, iclass 6, count 0 2006.257.23:12:23.82#ibcon#about to read 6, iclass 6, count 0 2006.257.23:12:23.82#ibcon#read 6, iclass 6, count 0 2006.257.23:12:23.82#ibcon#end of sib2, iclass 6, count 0 2006.257.23:12:23.82#ibcon#*after write, iclass 6, count 0 2006.257.23:12:23.82#ibcon#*before return 0, iclass 6, count 0 2006.257.23:12:23.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:23.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:12:23.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:12:23.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:12:23.82$vck44/vabw=wide 2006.257.23:12:23.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.23:12:23.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.23:12:23.82#ibcon#ireg 8 cls_cnt 0 2006.257.23:12:23.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:23.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:23.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:23.82#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:12:23.82#ibcon#first serial, iclass 10, count 0 2006.257.23:12:23.82#ibcon#enter sib2, iclass 10, count 0 2006.257.23:12:23.82#ibcon#flushed, iclass 10, count 0 2006.257.23:12:23.82#ibcon#about to write, iclass 10, count 0 2006.257.23:12:23.82#ibcon#wrote, iclass 10, count 0 2006.257.23:12:23.82#ibcon#about to read 3, iclass 10, count 0 2006.257.23:12:23.84#ibcon#read 3, iclass 10, count 0 2006.257.23:12:23.84#ibcon#about to read 4, iclass 10, count 0 2006.257.23:12:23.84#ibcon#read 4, iclass 10, count 0 2006.257.23:12:23.84#ibcon#about to read 5, iclass 10, count 0 2006.257.23:12:23.84#ibcon#read 5, iclass 10, count 0 2006.257.23:12:23.84#ibcon#about to read 6, iclass 10, count 0 2006.257.23:12:23.84#ibcon#read 6, iclass 10, count 0 2006.257.23:12:23.84#ibcon#end of sib2, iclass 10, count 0 2006.257.23:12:23.84#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:12:23.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:12:23.84#ibcon#[25=BW32\r\n] 2006.257.23:12:23.84#ibcon#*before write, iclass 10, count 0 2006.257.23:12:23.84#ibcon#enter sib2, iclass 10, count 0 2006.257.23:12:23.84#ibcon#flushed, iclass 10, count 0 2006.257.23:12:23.84#ibcon#about to write, iclass 10, count 0 2006.257.23:12:23.84#ibcon#wrote, iclass 10, count 0 2006.257.23:12:23.84#ibcon#about to read 3, iclass 10, count 0 2006.257.23:12:23.87#ibcon#read 3, iclass 10, count 0 2006.257.23:12:23.87#ibcon#about to read 4, iclass 10, count 0 2006.257.23:12:23.87#ibcon#read 4, iclass 10, count 0 2006.257.23:12:23.87#ibcon#about to read 5, iclass 10, count 0 2006.257.23:12:23.87#ibcon#read 5, iclass 10, count 0 2006.257.23:12:23.87#ibcon#about to read 6, iclass 10, count 0 2006.257.23:12:23.87#ibcon#read 6, iclass 10, count 0 2006.257.23:12:23.87#ibcon#end of sib2, iclass 10, count 0 2006.257.23:12:23.87#ibcon#*after write, iclass 10, count 0 2006.257.23:12:23.87#ibcon#*before return 0, iclass 10, count 0 2006.257.23:12:23.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:23.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:12:23.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:12:23.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:12:23.87$vck44/vbbw=wide 2006.257.23:12:23.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.23:12:23.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.23:12:23.87#ibcon#ireg 8 cls_cnt 0 2006.257.23:12:23.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:12:23.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:12:23.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:12:23.94#ibcon#enter wrdev, iclass 12, count 0 2006.257.23:12:23.94#ibcon#first serial, iclass 12, count 0 2006.257.23:12:23.94#ibcon#enter sib2, iclass 12, count 0 2006.257.23:12:23.94#ibcon#flushed, iclass 12, count 0 2006.257.23:12:23.94#ibcon#about to write, iclass 12, count 0 2006.257.23:12:23.94#ibcon#wrote, iclass 12, count 0 2006.257.23:12:23.94#ibcon#about to read 3, iclass 12, count 0 2006.257.23:12:23.96#ibcon#read 3, iclass 12, count 0 2006.257.23:12:23.96#ibcon#about to read 4, iclass 12, count 0 2006.257.23:12:23.96#ibcon#read 4, iclass 12, count 0 2006.257.23:12:23.96#ibcon#about to read 5, iclass 12, count 0 2006.257.23:12:23.96#ibcon#read 5, iclass 12, count 0 2006.257.23:12:23.96#ibcon#about to read 6, iclass 12, count 0 2006.257.23:12:23.96#ibcon#read 6, iclass 12, count 0 2006.257.23:12:23.96#ibcon#end of sib2, iclass 12, count 0 2006.257.23:12:23.96#ibcon#*mode == 0, iclass 12, count 0 2006.257.23:12:23.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.23:12:23.96#ibcon#[27=BW32\r\n] 2006.257.23:12:23.96#ibcon#*before write, iclass 12, count 0 2006.257.23:12:23.96#ibcon#enter sib2, iclass 12, count 0 2006.257.23:12:23.96#ibcon#flushed, iclass 12, count 0 2006.257.23:12:23.96#ibcon#about to write, iclass 12, count 0 2006.257.23:12:23.96#ibcon#wrote, iclass 12, count 0 2006.257.23:12:23.96#ibcon#about to read 3, iclass 12, count 0 2006.257.23:12:23.99#ibcon#read 3, iclass 12, count 0 2006.257.23:12:23.99#ibcon#about to read 4, iclass 12, count 0 2006.257.23:12:23.99#ibcon#read 4, iclass 12, count 0 2006.257.23:12:23.99#ibcon#about to read 5, iclass 12, count 0 2006.257.23:12:23.99#ibcon#read 5, iclass 12, count 0 2006.257.23:12:23.99#ibcon#about to read 6, iclass 12, count 0 2006.257.23:12:23.99#ibcon#read 6, iclass 12, count 0 2006.257.23:12:23.99#ibcon#end of sib2, iclass 12, count 0 2006.257.23:12:23.99#ibcon#*after write, iclass 12, count 0 2006.257.23:12:23.99#ibcon#*before return 0, iclass 12, count 0 2006.257.23:12:23.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:12:23.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:12:23.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.23:12:23.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.23:12:23.99$setupk4/ifdk4 2006.257.23:12:23.99$ifdk4/lo= 2006.257.23:12:23.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:12:23.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:12:23.99$ifdk4/patch= 2006.257.23:12:23.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:12:23.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:12:23.99$setupk4/!*+20s 2006.257.23:12:26.36#abcon#<5=/14 0.8 2.8 20.35 841016.0\r\n> 2006.257.23:12:26.38#abcon#{5=INTERFACE CLEAR} 2006.257.23:12:26.44#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:12:36.53#abcon#<5=/14 0.8 2.8 20.36 841016.0\r\n> 2006.257.23:12:36.55#abcon#{5=INTERFACE CLEAR} 2006.257.23:12:36.61#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:12:38.50$setupk4/"tpicd 2006.257.23:12:38.50$setupk4/echo=off 2006.257.23:12:38.50$setupk4/xlog=off 2006.257.23:12:38.50:!2006.257.23:14:10 2006.257.23:12:53.14#trakl#Source acquired 2006.257.23:12:54.14#flagr#flagr/antenna,acquired 2006.257.23:14:10.00:preob 2006.257.23:14:10.14/onsource/TRACKING 2006.257.23:14:10.14:!2006.257.23:14:20 2006.257.23:14:20.00:"tape 2006.257.23:14:20.00:"st=record 2006.257.23:14:20.00:data_valid=on 2006.257.23:14:20.00:midob 2006.257.23:14:21.14/onsource/TRACKING 2006.257.23:14:21.14/wx/20.44,1016.1,84 2006.257.23:14:21.23/cable/+6.4824E-03 2006.257.23:14:22.32/va/01,08,usb,yes,33,36 2006.257.23:14:22.32/va/02,07,usb,yes,36,37 2006.257.23:14:22.32/va/03,08,usb,yes,32,34 2006.257.23:14:22.32/va/04,07,usb,yes,37,39 2006.257.23:14:22.32/va/05,04,usb,yes,33,34 2006.257.23:14:22.32/va/06,04,usb,yes,37,36 2006.257.23:14:22.32/va/07,04,usb,yes,38,38 2006.257.23:14:22.32/va/08,04,usb,yes,31,39 2006.257.23:14:22.55/valo/01,524.99,yes,locked 2006.257.23:14:22.55/valo/02,534.99,yes,locked 2006.257.23:14:22.55/valo/03,564.99,yes,locked 2006.257.23:14:22.55/valo/04,624.99,yes,locked 2006.257.23:14:22.55/valo/05,734.99,yes,locked 2006.257.23:14:22.55/valo/06,814.99,yes,locked 2006.257.23:14:22.55/valo/07,864.99,yes,locked 2006.257.23:14:22.55/valo/08,884.99,yes,locked 2006.257.23:14:23.64/vb/01,04,usb,yes,39,36 2006.257.23:14:23.64/vb/02,05,usb,yes,37,36 2006.257.23:14:23.64/vb/03,04,usb,yes,38,42 2006.257.23:14:23.64/vb/04,05,usb,yes,38,37 2006.257.23:14:23.64/vb/05,04,usb,yes,34,37 2006.257.23:14:23.64/vb/06,04,usb,yes,39,35 2006.257.23:14:23.64/vb/07,04,usb,yes,39,39 2006.257.23:14:23.64/vb/08,04,usb,yes,35,39 2006.257.23:14:23.87/vblo/01,629.99,yes,locked 2006.257.23:14:23.87/vblo/02,634.99,yes,locked 2006.257.23:14:23.87/vblo/03,649.99,yes,locked 2006.257.23:14:23.87/vblo/04,679.99,yes,locked 2006.257.23:14:23.87/vblo/05,709.99,yes,locked 2006.257.23:14:23.87/vblo/06,719.99,yes,locked 2006.257.23:14:23.87/vblo/07,734.99,yes,locked 2006.257.23:14:23.87/vblo/08,744.99,yes,locked 2006.257.23:14:24.02/vabw/8 2006.257.23:14:24.17/vbbw/8 2006.257.23:14:24.34/xfe/off,on,15.2 2006.257.23:14:24.71/ifatt/23,28,28,28 2006.257.23:14:25.07/fmout-gps/S +4.53E-07 2006.257.23:14:25.11:!2006.257.23:15:50 2006.257.23:15:50.01:data_valid=off 2006.257.23:15:50.01:"et 2006.257.23:15:50.01:!+3s 2006.257.23:15:53.02:"tape 2006.257.23:15:53.02:postob 2006.257.23:15:53.08/cable/+6.4814E-03 2006.257.23:15:53.08/wx/20.50,1016.1,80 2006.257.23:15:54.08/fmout-gps/S +4.52E-07 2006.257.23:15:54.08:scan_name=257-2319,jd0609,50 2006.257.23:15:54.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.257.23:15:54.13#flagr#flagr/antenna,new-source 2006.257.23:15:55.13:checkk5 2006.257.23:15:55.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:15:55.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:15:56.15/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:15:56.49/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:15:56.82/chk_obsdata//k5ts1/T2572314??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.23:15:57.15/chk_obsdata//k5ts2/T2572314??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.23:15:57.48/chk_obsdata//k5ts3/T2572314??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.23:15:57.82/chk_obsdata//k5ts4/T2572314??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.257.23:15:58.49/k5log//k5ts1_log_newline 2006.257.23:15:59.15/k5log//k5ts2_log_newline 2006.257.23:15:59.80/k5log//k5ts3_log_newline 2006.257.23:16:00.47/k5log//k5ts4_log_newline 2006.257.23:16:00.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:16:00.49:setupk4=1 2006.257.23:16:00.49$setupk4/echo=on 2006.257.23:16:00.49$setupk4/pcalon 2006.257.23:16:00.49$pcalon/"no phase cal control is implemented here 2006.257.23:16:00.49$setupk4/"tpicd=stop 2006.257.23:16:00.49$setupk4/"rec=synch_on 2006.257.23:16:00.49$setupk4/"rec_mode=128 2006.257.23:16:00.49$setupk4/!* 2006.257.23:16:00.49$setupk4/recpk4 2006.257.23:16:00.49$recpk4/recpatch= 2006.257.23:16:00.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:16:00.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:16:00.49$setupk4/vck44 2006.257.23:16:00.49$vck44/valo=1,524.99 2006.257.23:16:00.49#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.23:16:00.49#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.23:16:00.49#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:00.49#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:00.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:00.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:00.49#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:16:00.49#ibcon#first serial, iclass 33, count 0 2006.257.23:16:00.49#ibcon#enter sib2, iclass 33, count 0 2006.257.23:16:00.49#ibcon#flushed, iclass 33, count 0 2006.257.23:16:00.49#ibcon#about to write, iclass 33, count 0 2006.257.23:16:00.49#ibcon#wrote, iclass 33, count 0 2006.257.23:16:00.49#ibcon#about to read 3, iclass 33, count 0 2006.257.23:16:00.51#ibcon#read 3, iclass 33, count 0 2006.257.23:16:00.51#ibcon#about to read 4, iclass 33, count 0 2006.257.23:16:00.51#ibcon#read 4, iclass 33, count 0 2006.257.23:16:00.51#ibcon#about to read 5, iclass 33, count 0 2006.257.23:16:00.51#ibcon#read 5, iclass 33, count 0 2006.257.23:16:00.51#ibcon#about to read 6, iclass 33, count 0 2006.257.23:16:00.51#ibcon#read 6, iclass 33, count 0 2006.257.23:16:00.51#ibcon#end of sib2, iclass 33, count 0 2006.257.23:16:00.51#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:16:00.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:16:00.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:16:00.51#ibcon#*before write, iclass 33, count 0 2006.257.23:16:00.51#ibcon#enter sib2, iclass 33, count 0 2006.257.23:16:00.51#ibcon#flushed, iclass 33, count 0 2006.257.23:16:00.51#ibcon#about to write, iclass 33, count 0 2006.257.23:16:00.51#ibcon#wrote, iclass 33, count 0 2006.257.23:16:00.51#ibcon#about to read 3, iclass 33, count 0 2006.257.23:16:00.56#ibcon#read 3, iclass 33, count 0 2006.257.23:16:00.56#ibcon#about to read 4, iclass 33, count 0 2006.257.23:16:00.56#ibcon#read 4, iclass 33, count 0 2006.257.23:16:00.56#ibcon#about to read 5, iclass 33, count 0 2006.257.23:16:00.56#ibcon#read 5, iclass 33, count 0 2006.257.23:16:00.56#ibcon#about to read 6, iclass 33, count 0 2006.257.23:16:00.56#ibcon#read 6, iclass 33, count 0 2006.257.23:16:00.56#ibcon#end of sib2, iclass 33, count 0 2006.257.23:16:00.56#ibcon#*after write, iclass 33, count 0 2006.257.23:16:00.56#ibcon#*before return 0, iclass 33, count 0 2006.257.23:16:00.56#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:00.56#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:00.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:16:00.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:16:00.56$vck44/va=1,8 2006.257.23:16:00.56#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.23:16:00.56#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.23:16:00.56#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:00.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:00.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:00.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:00.56#ibcon#enter wrdev, iclass 35, count 2 2006.257.23:16:00.56#ibcon#first serial, iclass 35, count 2 2006.257.23:16:00.56#ibcon#enter sib2, iclass 35, count 2 2006.257.23:16:00.56#ibcon#flushed, iclass 35, count 2 2006.257.23:16:00.56#ibcon#about to write, iclass 35, count 2 2006.257.23:16:00.56#ibcon#wrote, iclass 35, count 2 2006.257.23:16:00.56#ibcon#about to read 3, iclass 35, count 2 2006.257.23:16:00.58#ibcon#read 3, iclass 35, count 2 2006.257.23:16:00.58#ibcon#about to read 4, iclass 35, count 2 2006.257.23:16:00.58#ibcon#read 4, iclass 35, count 2 2006.257.23:16:00.58#ibcon#about to read 5, iclass 35, count 2 2006.257.23:16:00.58#ibcon#read 5, iclass 35, count 2 2006.257.23:16:00.58#ibcon#about to read 6, iclass 35, count 2 2006.257.23:16:00.58#ibcon#read 6, iclass 35, count 2 2006.257.23:16:00.58#ibcon#end of sib2, iclass 35, count 2 2006.257.23:16:00.58#ibcon#*mode == 0, iclass 35, count 2 2006.257.23:16:00.58#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.23:16:00.58#ibcon#[25=AT01-08\r\n] 2006.257.23:16:00.58#ibcon#*before write, iclass 35, count 2 2006.257.23:16:00.58#ibcon#enter sib2, iclass 35, count 2 2006.257.23:16:00.58#ibcon#flushed, iclass 35, count 2 2006.257.23:16:00.58#ibcon#about to write, iclass 35, count 2 2006.257.23:16:00.58#ibcon#wrote, iclass 35, count 2 2006.257.23:16:00.58#ibcon#about to read 3, iclass 35, count 2 2006.257.23:16:00.61#ibcon#read 3, iclass 35, count 2 2006.257.23:16:00.61#ibcon#about to read 4, iclass 35, count 2 2006.257.23:16:00.61#ibcon#read 4, iclass 35, count 2 2006.257.23:16:00.61#ibcon#about to read 5, iclass 35, count 2 2006.257.23:16:00.61#ibcon#read 5, iclass 35, count 2 2006.257.23:16:00.61#ibcon#about to read 6, iclass 35, count 2 2006.257.23:16:00.61#ibcon#read 6, iclass 35, count 2 2006.257.23:16:00.61#ibcon#end of sib2, iclass 35, count 2 2006.257.23:16:00.61#ibcon#*after write, iclass 35, count 2 2006.257.23:16:00.61#ibcon#*before return 0, iclass 35, count 2 2006.257.23:16:00.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:00.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:00.61#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.23:16:00.61#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:00.61#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:00.73#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:00.73#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:00.73#ibcon#enter wrdev, iclass 35, count 0 2006.257.23:16:00.73#ibcon#first serial, iclass 35, count 0 2006.257.23:16:00.73#ibcon#enter sib2, iclass 35, count 0 2006.257.23:16:00.73#ibcon#flushed, iclass 35, count 0 2006.257.23:16:00.73#ibcon#about to write, iclass 35, count 0 2006.257.23:16:00.73#ibcon#wrote, iclass 35, count 0 2006.257.23:16:00.73#ibcon#about to read 3, iclass 35, count 0 2006.257.23:16:00.75#ibcon#read 3, iclass 35, count 0 2006.257.23:16:00.75#ibcon#about to read 4, iclass 35, count 0 2006.257.23:16:00.75#ibcon#read 4, iclass 35, count 0 2006.257.23:16:00.75#ibcon#about to read 5, iclass 35, count 0 2006.257.23:16:00.75#ibcon#read 5, iclass 35, count 0 2006.257.23:16:00.75#ibcon#about to read 6, iclass 35, count 0 2006.257.23:16:00.75#ibcon#read 6, iclass 35, count 0 2006.257.23:16:00.75#ibcon#end of sib2, iclass 35, count 0 2006.257.23:16:00.75#ibcon#*mode == 0, iclass 35, count 0 2006.257.23:16:00.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.23:16:00.75#ibcon#[25=USB\r\n] 2006.257.23:16:00.75#ibcon#*before write, iclass 35, count 0 2006.257.23:16:00.75#ibcon#enter sib2, iclass 35, count 0 2006.257.23:16:00.75#ibcon#flushed, iclass 35, count 0 2006.257.23:16:00.75#ibcon#about to write, iclass 35, count 0 2006.257.23:16:00.75#ibcon#wrote, iclass 35, count 0 2006.257.23:16:00.75#ibcon#about to read 3, iclass 35, count 0 2006.257.23:16:00.78#ibcon#read 3, iclass 35, count 0 2006.257.23:16:00.78#ibcon#about to read 4, iclass 35, count 0 2006.257.23:16:00.78#ibcon#read 4, iclass 35, count 0 2006.257.23:16:00.78#ibcon#about to read 5, iclass 35, count 0 2006.257.23:16:00.78#ibcon#read 5, iclass 35, count 0 2006.257.23:16:00.78#ibcon#about to read 6, iclass 35, count 0 2006.257.23:16:00.78#ibcon#read 6, iclass 35, count 0 2006.257.23:16:00.78#ibcon#end of sib2, iclass 35, count 0 2006.257.23:16:00.78#ibcon#*after write, iclass 35, count 0 2006.257.23:16:00.78#ibcon#*before return 0, iclass 35, count 0 2006.257.23:16:00.78#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:00.78#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:00.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.23:16:00.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.23:16:00.78$vck44/valo=2,534.99 2006.257.23:16:00.78#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.23:16:00.78#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.23:16:00.78#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:00.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:00.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:00.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:00.78#ibcon#enter wrdev, iclass 37, count 0 2006.257.23:16:00.78#ibcon#first serial, iclass 37, count 0 2006.257.23:16:00.78#ibcon#enter sib2, iclass 37, count 0 2006.257.23:16:00.78#ibcon#flushed, iclass 37, count 0 2006.257.23:16:00.78#ibcon#about to write, iclass 37, count 0 2006.257.23:16:00.78#ibcon#wrote, iclass 37, count 0 2006.257.23:16:00.78#ibcon#about to read 3, iclass 37, count 0 2006.257.23:16:00.80#ibcon#read 3, iclass 37, count 0 2006.257.23:16:00.80#ibcon#about to read 4, iclass 37, count 0 2006.257.23:16:00.80#ibcon#read 4, iclass 37, count 0 2006.257.23:16:00.80#ibcon#about to read 5, iclass 37, count 0 2006.257.23:16:00.80#ibcon#read 5, iclass 37, count 0 2006.257.23:16:00.80#ibcon#about to read 6, iclass 37, count 0 2006.257.23:16:00.80#ibcon#read 6, iclass 37, count 0 2006.257.23:16:00.80#ibcon#end of sib2, iclass 37, count 0 2006.257.23:16:00.80#ibcon#*mode == 0, iclass 37, count 0 2006.257.23:16:00.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.23:16:00.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:16:00.80#ibcon#*before write, iclass 37, count 0 2006.257.23:16:00.80#ibcon#enter sib2, iclass 37, count 0 2006.257.23:16:00.80#ibcon#flushed, iclass 37, count 0 2006.257.23:16:00.80#ibcon#about to write, iclass 37, count 0 2006.257.23:16:00.80#ibcon#wrote, iclass 37, count 0 2006.257.23:16:00.80#ibcon#about to read 3, iclass 37, count 0 2006.257.23:16:00.84#ibcon#read 3, iclass 37, count 0 2006.257.23:16:00.84#ibcon#about to read 4, iclass 37, count 0 2006.257.23:16:00.84#ibcon#read 4, iclass 37, count 0 2006.257.23:16:00.84#ibcon#about to read 5, iclass 37, count 0 2006.257.23:16:00.84#ibcon#read 5, iclass 37, count 0 2006.257.23:16:00.84#ibcon#about to read 6, iclass 37, count 0 2006.257.23:16:00.84#ibcon#read 6, iclass 37, count 0 2006.257.23:16:00.84#ibcon#end of sib2, iclass 37, count 0 2006.257.23:16:00.84#ibcon#*after write, iclass 37, count 0 2006.257.23:16:00.84#ibcon#*before return 0, iclass 37, count 0 2006.257.23:16:00.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:00.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:00.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.23:16:00.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.23:16:00.84$vck44/va=2,7 2006.257.23:16:00.84#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.23:16:00.84#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.23:16:00.84#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:00.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:00.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:00.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:00.90#ibcon#enter wrdev, iclass 39, count 2 2006.257.23:16:00.90#ibcon#first serial, iclass 39, count 2 2006.257.23:16:00.90#ibcon#enter sib2, iclass 39, count 2 2006.257.23:16:00.90#ibcon#flushed, iclass 39, count 2 2006.257.23:16:00.90#ibcon#about to write, iclass 39, count 2 2006.257.23:16:00.90#ibcon#wrote, iclass 39, count 2 2006.257.23:16:00.90#ibcon#about to read 3, iclass 39, count 2 2006.257.23:16:00.92#ibcon#read 3, iclass 39, count 2 2006.257.23:16:00.92#ibcon#about to read 4, iclass 39, count 2 2006.257.23:16:00.92#ibcon#read 4, iclass 39, count 2 2006.257.23:16:00.92#ibcon#about to read 5, iclass 39, count 2 2006.257.23:16:00.92#ibcon#read 5, iclass 39, count 2 2006.257.23:16:00.92#ibcon#about to read 6, iclass 39, count 2 2006.257.23:16:00.92#ibcon#read 6, iclass 39, count 2 2006.257.23:16:00.92#ibcon#end of sib2, iclass 39, count 2 2006.257.23:16:00.92#ibcon#*mode == 0, iclass 39, count 2 2006.257.23:16:00.92#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.23:16:00.92#ibcon#[25=AT02-07\r\n] 2006.257.23:16:00.92#ibcon#*before write, iclass 39, count 2 2006.257.23:16:00.92#ibcon#enter sib2, iclass 39, count 2 2006.257.23:16:00.92#ibcon#flushed, iclass 39, count 2 2006.257.23:16:00.92#ibcon#about to write, iclass 39, count 2 2006.257.23:16:00.92#ibcon#wrote, iclass 39, count 2 2006.257.23:16:00.92#ibcon#about to read 3, iclass 39, count 2 2006.257.23:16:00.95#ibcon#read 3, iclass 39, count 2 2006.257.23:16:00.95#ibcon#about to read 4, iclass 39, count 2 2006.257.23:16:00.95#ibcon#read 4, iclass 39, count 2 2006.257.23:16:00.95#ibcon#about to read 5, iclass 39, count 2 2006.257.23:16:00.95#ibcon#read 5, iclass 39, count 2 2006.257.23:16:00.95#ibcon#about to read 6, iclass 39, count 2 2006.257.23:16:00.95#ibcon#read 6, iclass 39, count 2 2006.257.23:16:00.95#ibcon#end of sib2, iclass 39, count 2 2006.257.23:16:00.95#ibcon#*after write, iclass 39, count 2 2006.257.23:16:00.95#ibcon#*before return 0, iclass 39, count 2 2006.257.23:16:00.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:00.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:00.95#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.23:16:00.95#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:00.95#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:01.07#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:01.07#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:01.07#ibcon#enter wrdev, iclass 39, count 0 2006.257.23:16:01.07#ibcon#first serial, iclass 39, count 0 2006.257.23:16:01.07#ibcon#enter sib2, iclass 39, count 0 2006.257.23:16:01.07#ibcon#flushed, iclass 39, count 0 2006.257.23:16:01.07#ibcon#about to write, iclass 39, count 0 2006.257.23:16:01.07#ibcon#wrote, iclass 39, count 0 2006.257.23:16:01.07#ibcon#about to read 3, iclass 39, count 0 2006.257.23:16:01.09#ibcon#read 3, iclass 39, count 0 2006.257.23:16:01.09#ibcon#about to read 4, iclass 39, count 0 2006.257.23:16:01.09#ibcon#read 4, iclass 39, count 0 2006.257.23:16:01.09#ibcon#about to read 5, iclass 39, count 0 2006.257.23:16:01.09#ibcon#read 5, iclass 39, count 0 2006.257.23:16:01.09#ibcon#about to read 6, iclass 39, count 0 2006.257.23:16:01.09#ibcon#read 6, iclass 39, count 0 2006.257.23:16:01.09#ibcon#end of sib2, iclass 39, count 0 2006.257.23:16:01.09#ibcon#*mode == 0, iclass 39, count 0 2006.257.23:16:01.09#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.23:16:01.09#ibcon#[25=USB\r\n] 2006.257.23:16:01.09#ibcon#*before write, iclass 39, count 0 2006.257.23:16:01.09#ibcon#enter sib2, iclass 39, count 0 2006.257.23:16:01.09#ibcon#flushed, iclass 39, count 0 2006.257.23:16:01.09#ibcon#about to write, iclass 39, count 0 2006.257.23:16:01.09#ibcon#wrote, iclass 39, count 0 2006.257.23:16:01.09#ibcon#about to read 3, iclass 39, count 0 2006.257.23:16:01.12#ibcon#read 3, iclass 39, count 0 2006.257.23:16:01.12#ibcon#about to read 4, iclass 39, count 0 2006.257.23:16:01.12#ibcon#read 4, iclass 39, count 0 2006.257.23:16:01.12#ibcon#about to read 5, iclass 39, count 0 2006.257.23:16:01.12#ibcon#read 5, iclass 39, count 0 2006.257.23:16:01.12#ibcon#about to read 6, iclass 39, count 0 2006.257.23:16:01.12#ibcon#read 6, iclass 39, count 0 2006.257.23:16:01.12#ibcon#end of sib2, iclass 39, count 0 2006.257.23:16:01.12#ibcon#*after write, iclass 39, count 0 2006.257.23:16:01.12#ibcon#*before return 0, iclass 39, count 0 2006.257.23:16:01.12#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:01.12#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:01.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.23:16:01.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.23:16:01.12$vck44/valo=3,564.99 2006.257.23:16:01.12#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.23:16:01.12#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.23:16:01.12#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:01.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:01.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:01.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:01.12#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:16:01.12#ibcon#first serial, iclass 3, count 0 2006.257.23:16:01.12#ibcon#enter sib2, iclass 3, count 0 2006.257.23:16:01.12#ibcon#flushed, iclass 3, count 0 2006.257.23:16:01.12#ibcon#about to write, iclass 3, count 0 2006.257.23:16:01.12#ibcon#wrote, iclass 3, count 0 2006.257.23:16:01.12#ibcon#about to read 3, iclass 3, count 0 2006.257.23:16:01.14#ibcon#read 3, iclass 3, count 0 2006.257.23:16:01.14#ibcon#about to read 4, iclass 3, count 0 2006.257.23:16:01.14#ibcon#read 4, iclass 3, count 0 2006.257.23:16:01.14#ibcon#about to read 5, iclass 3, count 0 2006.257.23:16:01.14#ibcon#read 5, iclass 3, count 0 2006.257.23:16:01.14#ibcon#about to read 6, iclass 3, count 0 2006.257.23:16:01.14#ibcon#read 6, iclass 3, count 0 2006.257.23:16:01.14#ibcon#end of sib2, iclass 3, count 0 2006.257.23:16:01.14#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:16:01.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:16:01.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:16:01.14#ibcon#*before write, iclass 3, count 0 2006.257.23:16:01.14#ibcon#enter sib2, iclass 3, count 0 2006.257.23:16:01.14#ibcon#flushed, iclass 3, count 0 2006.257.23:16:01.14#ibcon#about to write, iclass 3, count 0 2006.257.23:16:01.14#ibcon#wrote, iclass 3, count 0 2006.257.23:16:01.14#ibcon#about to read 3, iclass 3, count 0 2006.257.23:16:01.18#ibcon#read 3, iclass 3, count 0 2006.257.23:16:01.18#ibcon#about to read 4, iclass 3, count 0 2006.257.23:16:01.18#ibcon#read 4, iclass 3, count 0 2006.257.23:16:01.18#ibcon#about to read 5, iclass 3, count 0 2006.257.23:16:01.18#ibcon#read 5, iclass 3, count 0 2006.257.23:16:01.18#ibcon#about to read 6, iclass 3, count 0 2006.257.23:16:01.18#ibcon#read 6, iclass 3, count 0 2006.257.23:16:01.18#ibcon#end of sib2, iclass 3, count 0 2006.257.23:16:01.18#ibcon#*after write, iclass 3, count 0 2006.257.23:16:01.18#ibcon#*before return 0, iclass 3, count 0 2006.257.23:16:01.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:01.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:01.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:16:01.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:16:01.18$vck44/va=3,8 2006.257.23:16:01.18#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.23:16:01.18#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.23:16:01.18#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:01.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:01.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:01.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:01.24#ibcon#enter wrdev, iclass 5, count 2 2006.257.23:16:01.24#ibcon#first serial, iclass 5, count 2 2006.257.23:16:01.24#ibcon#enter sib2, iclass 5, count 2 2006.257.23:16:01.24#ibcon#flushed, iclass 5, count 2 2006.257.23:16:01.24#ibcon#about to write, iclass 5, count 2 2006.257.23:16:01.24#ibcon#wrote, iclass 5, count 2 2006.257.23:16:01.24#ibcon#about to read 3, iclass 5, count 2 2006.257.23:16:01.26#ibcon#read 3, iclass 5, count 2 2006.257.23:16:01.26#ibcon#about to read 4, iclass 5, count 2 2006.257.23:16:01.26#ibcon#read 4, iclass 5, count 2 2006.257.23:16:01.26#ibcon#about to read 5, iclass 5, count 2 2006.257.23:16:01.26#ibcon#read 5, iclass 5, count 2 2006.257.23:16:01.26#ibcon#about to read 6, iclass 5, count 2 2006.257.23:16:01.26#ibcon#read 6, iclass 5, count 2 2006.257.23:16:01.26#ibcon#end of sib2, iclass 5, count 2 2006.257.23:16:01.26#ibcon#*mode == 0, iclass 5, count 2 2006.257.23:16:01.26#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.23:16:01.26#ibcon#[25=AT03-08\r\n] 2006.257.23:16:01.26#ibcon#*before write, iclass 5, count 2 2006.257.23:16:01.26#ibcon#enter sib2, iclass 5, count 2 2006.257.23:16:01.26#ibcon#flushed, iclass 5, count 2 2006.257.23:16:01.26#ibcon#about to write, iclass 5, count 2 2006.257.23:16:01.26#ibcon#wrote, iclass 5, count 2 2006.257.23:16:01.26#ibcon#about to read 3, iclass 5, count 2 2006.257.23:16:01.29#ibcon#read 3, iclass 5, count 2 2006.257.23:16:01.29#ibcon#about to read 4, iclass 5, count 2 2006.257.23:16:01.29#ibcon#read 4, iclass 5, count 2 2006.257.23:16:01.29#ibcon#about to read 5, iclass 5, count 2 2006.257.23:16:01.29#ibcon#read 5, iclass 5, count 2 2006.257.23:16:01.29#ibcon#about to read 6, iclass 5, count 2 2006.257.23:16:01.29#ibcon#read 6, iclass 5, count 2 2006.257.23:16:01.29#ibcon#end of sib2, iclass 5, count 2 2006.257.23:16:01.29#ibcon#*after write, iclass 5, count 2 2006.257.23:16:01.29#ibcon#*before return 0, iclass 5, count 2 2006.257.23:16:01.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:01.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:01.29#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.23:16:01.29#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:01.29#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:01.41#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:01.41#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:01.41#ibcon#enter wrdev, iclass 5, count 0 2006.257.23:16:01.41#ibcon#first serial, iclass 5, count 0 2006.257.23:16:01.41#ibcon#enter sib2, iclass 5, count 0 2006.257.23:16:01.41#ibcon#flushed, iclass 5, count 0 2006.257.23:16:01.41#ibcon#about to write, iclass 5, count 0 2006.257.23:16:01.41#ibcon#wrote, iclass 5, count 0 2006.257.23:16:01.41#ibcon#about to read 3, iclass 5, count 0 2006.257.23:16:01.43#ibcon#read 3, iclass 5, count 0 2006.257.23:16:01.43#ibcon#about to read 4, iclass 5, count 0 2006.257.23:16:01.43#ibcon#read 4, iclass 5, count 0 2006.257.23:16:01.43#ibcon#about to read 5, iclass 5, count 0 2006.257.23:16:01.43#ibcon#read 5, iclass 5, count 0 2006.257.23:16:01.43#ibcon#about to read 6, iclass 5, count 0 2006.257.23:16:01.43#ibcon#read 6, iclass 5, count 0 2006.257.23:16:01.43#ibcon#end of sib2, iclass 5, count 0 2006.257.23:16:01.43#ibcon#*mode == 0, iclass 5, count 0 2006.257.23:16:01.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.23:16:01.43#ibcon#[25=USB\r\n] 2006.257.23:16:01.43#ibcon#*before write, iclass 5, count 0 2006.257.23:16:01.43#ibcon#enter sib2, iclass 5, count 0 2006.257.23:16:01.43#ibcon#flushed, iclass 5, count 0 2006.257.23:16:01.43#ibcon#about to write, iclass 5, count 0 2006.257.23:16:01.43#ibcon#wrote, iclass 5, count 0 2006.257.23:16:01.43#ibcon#about to read 3, iclass 5, count 0 2006.257.23:16:01.46#ibcon#read 3, iclass 5, count 0 2006.257.23:16:01.46#ibcon#about to read 4, iclass 5, count 0 2006.257.23:16:01.46#ibcon#read 4, iclass 5, count 0 2006.257.23:16:01.46#ibcon#about to read 5, iclass 5, count 0 2006.257.23:16:01.46#ibcon#read 5, iclass 5, count 0 2006.257.23:16:01.46#ibcon#about to read 6, iclass 5, count 0 2006.257.23:16:01.46#ibcon#read 6, iclass 5, count 0 2006.257.23:16:01.46#ibcon#end of sib2, iclass 5, count 0 2006.257.23:16:01.46#ibcon#*after write, iclass 5, count 0 2006.257.23:16:01.46#ibcon#*before return 0, iclass 5, count 0 2006.257.23:16:01.46#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:01.46#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:01.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.23:16:01.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.23:16:01.46$vck44/valo=4,624.99 2006.257.23:16:01.46#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.23:16:01.46#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.23:16:01.46#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:01.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:01.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:01.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:01.46#ibcon#enter wrdev, iclass 7, count 0 2006.257.23:16:01.46#ibcon#first serial, iclass 7, count 0 2006.257.23:16:01.46#ibcon#enter sib2, iclass 7, count 0 2006.257.23:16:01.46#ibcon#flushed, iclass 7, count 0 2006.257.23:16:01.46#ibcon#about to write, iclass 7, count 0 2006.257.23:16:01.46#ibcon#wrote, iclass 7, count 0 2006.257.23:16:01.46#ibcon#about to read 3, iclass 7, count 0 2006.257.23:16:01.48#ibcon#read 3, iclass 7, count 0 2006.257.23:16:01.48#ibcon#about to read 4, iclass 7, count 0 2006.257.23:16:01.48#ibcon#read 4, iclass 7, count 0 2006.257.23:16:01.48#ibcon#about to read 5, iclass 7, count 0 2006.257.23:16:01.48#ibcon#read 5, iclass 7, count 0 2006.257.23:16:01.48#ibcon#about to read 6, iclass 7, count 0 2006.257.23:16:01.48#ibcon#read 6, iclass 7, count 0 2006.257.23:16:01.48#ibcon#end of sib2, iclass 7, count 0 2006.257.23:16:01.48#ibcon#*mode == 0, iclass 7, count 0 2006.257.23:16:01.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.23:16:01.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:16:01.48#ibcon#*before write, iclass 7, count 0 2006.257.23:16:01.48#ibcon#enter sib2, iclass 7, count 0 2006.257.23:16:01.48#ibcon#flushed, iclass 7, count 0 2006.257.23:16:01.48#ibcon#about to write, iclass 7, count 0 2006.257.23:16:01.48#ibcon#wrote, iclass 7, count 0 2006.257.23:16:01.48#ibcon#about to read 3, iclass 7, count 0 2006.257.23:16:01.52#ibcon#read 3, iclass 7, count 0 2006.257.23:16:01.52#ibcon#about to read 4, iclass 7, count 0 2006.257.23:16:01.52#ibcon#read 4, iclass 7, count 0 2006.257.23:16:01.52#ibcon#about to read 5, iclass 7, count 0 2006.257.23:16:01.52#ibcon#read 5, iclass 7, count 0 2006.257.23:16:01.52#ibcon#about to read 6, iclass 7, count 0 2006.257.23:16:01.52#ibcon#read 6, iclass 7, count 0 2006.257.23:16:01.52#ibcon#end of sib2, iclass 7, count 0 2006.257.23:16:01.52#ibcon#*after write, iclass 7, count 0 2006.257.23:16:01.52#ibcon#*before return 0, iclass 7, count 0 2006.257.23:16:01.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:01.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:01.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.23:16:01.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.23:16:01.52$vck44/va=4,7 2006.257.23:16:01.52#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.23:16:01.52#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.23:16:01.52#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:01.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:01.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:01.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:01.58#ibcon#enter wrdev, iclass 11, count 2 2006.257.23:16:01.58#ibcon#first serial, iclass 11, count 2 2006.257.23:16:01.58#ibcon#enter sib2, iclass 11, count 2 2006.257.23:16:01.58#ibcon#flushed, iclass 11, count 2 2006.257.23:16:01.58#ibcon#about to write, iclass 11, count 2 2006.257.23:16:01.58#ibcon#wrote, iclass 11, count 2 2006.257.23:16:01.58#ibcon#about to read 3, iclass 11, count 2 2006.257.23:16:01.60#ibcon#read 3, iclass 11, count 2 2006.257.23:16:01.60#ibcon#about to read 4, iclass 11, count 2 2006.257.23:16:01.60#ibcon#read 4, iclass 11, count 2 2006.257.23:16:01.60#ibcon#about to read 5, iclass 11, count 2 2006.257.23:16:01.60#ibcon#read 5, iclass 11, count 2 2006.257.23:16:01.60#ibcon#about to read 6, iclass 11, count 2 2006.257.23:16:01.60#ibcon#read 6, iclass 11, count 2 2006.257.23:16:01.60#ibcon#end of sib2, iclass 11, count 2 2006.257.23:16:01.60#ibcon#*mode == 0, iclass 11, count 2 2006.257.23:16:01.60#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.23:16:01.60#ibcon#[25=AT04-07\r\n] 2006.257.23:16:01.60#ibcon#*before write, iclass 11, count 2 2006.257.23:16:01.60#ibcon#enter sib2, iclass 11, count 2 2006.257.23:16:01.60#ibcon#flushed, iclass 11, count 2 2006.257.23:16:01.60#ibcon#about to write, iclass 11, count 2 2006.257.23:16:01.60#ibcon#wrote, iclass 11, count 2 2006.257.23:16:01.60#ibcon#about to read 3, iclass 11, count 2 2006.257.23:16:01.63#ibcon#read 3, iclass 11, count 2 2006.257.23:16:01.63#ibcon#about to read 4, iclass 11, count 2 2006.257.23:16:01.63#ibcon#read 4, iclass 11, count 2 2006.257.23:16:01.63#ibcon#about to read 5, iclass 11, count 2 2006.257.23:16:01.63#ibcon#read 5, iclass 11, count 2 2006.257.23:16:01.63#ibcon#about to read 6, iclass 11, count 2 2006.257.23:16:01.63#ibcon#read 6, iclass 11, count 2 2006.257.23:16:01.63#ibcon#end of sib2, iclass 11, count 2 2006.257.23:16:01.63#ibcon#*after write, iclass 11, count 2 2006.257.23:16:01.63#ibcon#*before return 0, iclass 11, count 2 2006.257.23:16:01.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:01.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:01.63#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.23:16:01.63#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:01.63#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:01.75#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:01.75#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:01.75#ibcon#enter wrdev, iclass 11, count 0 2006.257.23:16:01.75#ibcon#first serial, iclass 11, count 0 2006.257.23:16:01.75#ibcon#enter sib2, iclass 11, count 0 2006.257.23:16:01.75#ibcon#flushed, iclass 11, count 0 2006.257.23:16:01.75#ibcon#about to write, iclass 11, count 0 2006.257.23:16:01.75#ibcon#wrote, iclass 11, count 0 2006.257.23:16:01.75#ibcon#about to read 3, iclass 11, count 0 2006.257.23:16:01.77#ibcon#read 3, iclass 11, count 0 2006.257.23:16:01.77#ibcon#about to read 4, iclass 11, count 0 2006.257.23:16:01.77#ibcon#read 4, iclass 11, count 0 2006.257.23:16:01.77#ibcon#about to read 5, iclass 11, count 0 2006.257.23:16:01.77#ibcon#read 5, iclass 11, count 0 2006.257.23:16:01.77#ibcon#about to read 6, iclass 11, count 0 2006.257.23:16:01.77#ibcon#read 6, iclass 11, count 0 2006.257.23:16:01.77#ibcon#end of sib2, iclass 11, count 0 2006.257.23:16:01.77#ibcon#*mode == 0, iclass 11, count 0 2006.257.23:16:01.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.23:16:01.77#ibcon#[25=USB\r\n] 2006.257.23:16:01.77#ibcon#*before write, iclass 11, count 0 2006.257.23:16:01.77#ibcon#enter sib2, iclass 11, count 0 2006.257.23:16:01.77#ibcon#flushed, iclass 11, count 0 2006.257.23:16:01.77#ibcon#about to write, iclass 11, count 0 2006.257.23:16:01.77#ibcon#wrote, iclass 11, count 0 2006.257.23:16:01.77#ibcon#about to read 3, iclass 11, count 0 2006.257.23:16:01.80#ibcon#read 3, iclass 11, count 0 2006.257.23:16:01.80#ibcon#about to read 4, iclass 11, count 0 2006.257.23:16:01.80#ibcon#read 4, iclass 11, count 0 2006.257.23:16:01.80#ibcon#about to read 5, iclass 11, count 0 2006.257.23:16:01.80#ibcon#read 5, iclass 11, count 0 2006.257.23:16:01.80#ibcon#about to read 6, iclass 11, count 0 2006.257.23:16:01.80#ibcon#read 6, iclass 11, count 0 2006.257.23:16:01.80#ibcon#end of sib2, iclass 11, count 0 2006.257.23:16:01.80#ibcon#*after write, iclass 11, count 0 2006.257.23:16:01.80#ibcon#*before return 0, iclass 11, count 0 2006.257.23:16:01.80#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:01.80#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:01.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.23:16:01.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.23:16:01.80$vck44/valo=5,734.99 2006.257.23:16:01.80#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.23:16:01.80#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.23:16:01.80#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:01.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:01.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:01.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:01.80#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:16:01.80#ibcon#first serial, iclass 13, count 0 2006.257.23:16:01.80#ibcon#enter sib2, iclass 13, count 0 2006.257.23:16:01.80#ibcon#flushed, iclass 13, count 0 2006.257.23:16:01.80#ibcon#about to write, iclass 13, count 0 2006.257.23:16:01.80#ibcon#wrote, iclass 13, count 0 2006.257.23:16:01.80#ibcon#about to read 3, iclass 13, count 0 2006.257.23:16:01.82#ibcon#read 3, iclass 13, count 0 2006.257.23:16:01.82#ibcon#about to read 4, iclass 13, count 0 2006.257.23:16:01.82#ibcon#read 4, iclass 13, count 0 2006.257.23:16:01.82#ibcon#about to read 5, iclass 13, count 0 2006.257.23:16:01.82#ibcon#read 5, iclass 13, count 0 2006.257.23:16:01.82#ibcon#about to read 6, iclass 13, count 0 2006.257.23:16:01.82#ibcon#read 6, iclass 13, count 0 2006.257.23:16:01.82#ibcon#end of sib2, iclass 13, count 0 2006.257.23:16:01.82#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:16:01.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:16:01.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:16:01.82#ibcon#*before write, iclass 13, count 0 2006.257.23:16:01.82#ibcon#enter sib2, iclass 13, count 0 2006.257.23:16:01.82#ibcon#flushed, iclass 13, count 0 2006.257.23:16:01.82#ibcon#about to write, iclass 13, count 0 2006.257.23:16:01.82#ibcon#wrote, iclass 13, count 0 2006.257.23:16:01.82#ibcon#about to read 3, iclass 13, count 0 2006.257.23:16:01.86#ibcon#read 3, iclass 13, count 0 2006.257.23:16:01.86#ibcon#about to read 4, iclass 13, count 0 2006.257.23:16:01.86#ibcon#read 4, iclass 13, count 0 2006.257.23:16:01.86#ibcon#about to read 5, iclass 13, count 0 2006.257.23:16:01.86#ibcon#read 5, iclass 13, count 0 2006.257.23:16:01.86#ibcon#about to read 6, iclass 13, count 0 2006.257.23:16:01.86#ibcon#read 6, iclass 13, count 0 2006.257.23:16:01.86#ibcon#end of sib2, iclass 13, count 0 2006.257.23:16:01.86#ibcon#*after write, iclass 13, count 0 2006.257.23:16:01.86#ibcon#*before return 0, iclass 13, count 0 2006.257.23:16:01.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:01.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:01.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:16:01.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:16:01.86$vck44/va=5,4 2006.257.23:16:01.86#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.23:16:01.86#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.23:16:01.86#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:01.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:01.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:01.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:01.92#ibcon#enter wrdev, iclass 15, count 2 2006.257.23:16:01.92#ibcon#first serial, iclass 15, count 2 2006.257.23:16:01.92#ibcon#enter sib2, iclass 15, count 2 2006.257.23:16:01.92#ibcon#flushed, iclass 15, count 2 2006.257.23:16:01.92#ibcon#about to write, iclass 15, count 2 2006.257.23:16:01.92#ibcon#wrote, iclass 15, count 2 2006.257.23:16:01.92#ibcon#about to read 3, iclass 15, count 2 2006.257.23:16:01.94#ibcon#read 3, iclass 15, count 2 2006.257.23:16:01.94#ibcon#about to read 4, iclass 15, count 2 2006.257.23:16:01.94#ibcon#read 4, iclass 15, count 2 2006.257.23:16:01.94#ibcon#about to read 5, iclass 15, count 2 2006.257.23:16:01.94#ibcon#read 5, iclass 15, count 2 2006.257.23:16:01.94#ibcon#about to read 6, iclass 15, count 2 2006.257.23:16:01.94#ibcon#read 6, iclass 15, count 2 2006.257.23:16:01.94#ibcon#end of sib2, iclass 15, count 2 2006.257.23:16:01.94#ibcon#*mode == 0, iclass 15, count 2 2006.257.23:16:01.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.23:16:01.94#ibcon#[25=AT05-04\r\n] 2006.257.23:16:01.94#ibcon#*before write, iclass 15, count 2 2006.257.23:16:01.94#ibcon#enter sib2, iclass 15, count 2 2006.257.23:16:01.94#ibcon#flushed, iclass 15, count 2 2006.257.23:16:01.94#ibcon#about to write, iclass 15, count 2 2006.257.23:16:01.94#ibcon#wrote, iclass 15, count 2 2006.257.23:16:01.94#ibcon#about to read 3, iclass 15, count 2 2006.257.23:16:01.97#ibcon#read 3, iclass 15, count 2 2006.257.23:16:01.97#ibcon#about to read 4, iclass 15, count 2 2006.257.23:16:01.97#ibcon#read 4, iclass 15, count 2 2006.257.23:16:01.97#ibcon#about to read 5, iclass 15, count 2 2006.257.23:16:01.97#ibcon#read 5, iclass 15, count 2 2006.257.23:16:01.97#ibcon#about to read 6, iclass 15, count 2 2006.257.23:16:01.97#ibcon#read 6, iclass 15, count 2 2006.257.23:16:01.97#ibcon#end of sib2, iclass 15, count 2 2006.257.23:16:01.97#ibcon#*after write, iclass 15, count 2 2006.257.23:16:01.97#ibcon#*before return 0, iclass 15, count 2 2006.257.23:16:01.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:01.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:01.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.23:16:01.97#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:01.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:02.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:02.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:02.09#ibcon#enter wrdev, iclass 15, count 0 2006.257.23:16:02.09#ibcon#first serial, iclass 15, count 0 2006.257.23:16:02.09#ibcon#enter sib2, iclass 15, count 0 2006.257.23:16:02.09#ibcon#flushed, iclass 15, count 0 2006.257.23:16:02.09#ibcon#about to write, iclass 15, count 0 2006.257.23:16:02.09#ibcon#wrote, iclass 15, count 0 2006.257.23:16:02.09#ibcon#about to read 3, iclass 15, count 0 2006.257.23:16:02.11#ibcon#read 3, iclass 15, count 0 2006.257.23:16:02.11#ibcon#about to read 4, iclass 15, count 0 2006.257.23:16:02.11#ibcon#read 4, iclass 15, count 0 2006.257.23:16:02.11#ibcon#about to read 5, iclass 15, count 0 2006.257.23:16:02.11#ibcon#read 5, iclass 15, count 0 2006.257.23:16:02.11#ibcon#about to read 6, iclass 15, count 0 2006.257.23:16:02.11#ibcon#read 6, iclass 15, count 0 2006.257.23:16:02.11#ibcon#end of sib2, iclass 15, count 0 2006.257.23:16:02.11#ibcon#*mode == 0, iclass 15, count 0 2006.257.23:16:02.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.23:16:02.11#ibcon#[25=USB\r\n] 2006.257.23:16:02.11#ibcon#*before write, iclass 15, count 0 2006.257.23:16:02.11#ibcon#enter sib2, iclass 15, count 0 2006.257.23:16:02.11#ibcon#flushed, iclass 15, count 0 2006.257.23:16:02.11#ibcon#about to write, iclass 15, count 0 2006.257.23:16:02.11#ibcon#wrote, iclass 15, count 0 2006.257.23:16:02.11#ibcon#about to read 3, iclass 15, count 0 2006.257.23:16:02.14#ibcon#read 3, iclass 15, count 0 2006.257.23:16:02.14#ibcon#about to read 4, iclass 15, count 0 2006.257.23:16:02.14#ibcon#read 4, iclass 15, count 0 2006.257.23:16:02.14#ibcon#about to read 5, iclass 15, count 0 2006.257.23:16:02.14#ibcon#read 5, iclass 15, count 0 2006.257.23:16:02.14#ibcon#about to read 6, iclass 15, count 0 2006.257.23:16:02.14#ibcon#read 6, iclass 15, count 0 2006.257.23:16:02.14#ibcon#end of sib2, iclass 15, count 0 2006.257.23:16:02.14#ibcon#*after write, iclass 15, count 0 2006.257.23:16:02.14#ibcon#*before return 0, iclass 15, count 0 2006.257.23:16:02.14#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:02.14#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:02.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.23:16:02.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.23:16:02.14$vck44/valo=6,814.99 2006.257.23:16:02.14#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.23:16:02.14#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.23:16:02.14#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:02.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:02.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:02.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:02.14#ibcon#enter wrdev, iclass 17, count 0 2006.257.23:16:02.14#ibcon#first serial, iclass 17, count 0 2006.257.23:16:02.14#ibcon#enter sib2, iclass 17, count 0 2006.257.23:16:02.14#ibcon#flushed, iclass 17, count 0 2006.257.23:16:02.14#ibcon#about to write, iclass 17, count 0 2006.257.23:16:02.14#ibcon#wrote, iclass 17, count 0 2006.257.23:16:02.14#ibcon#about to read 3, iclass 17, count 0 2006.257.23:16:02.16#ibcon#read 3, iclass 17, count 0 2006.257.23:16:02.16#ibcon#about to read 4, iclass 17, count 0 2006.257.23:16:02.16#ibcon#read 4, iclass 17, count 0 2006.257.23:16:02.16#ibcon#about to read 5, iclass 17, count 0 2006.257.23:16:02.16#ibcon#read 5, iclass 17, count 0 2006.257.23:16:02.16#ibcon#about to read 6, iclass 17, count 0 2006.257.23:16:02.16#ibcon#read 6, iclass 17, count 0 2006.257.23:16:02.16#ibcon#end of sib2, iclass 17, count 0 2006.257.23:16:02.16#ibcon#*mode == 0, iclass 17, count 0 2006.257.23:16:02.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.23:16:02.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:16:02.16#ibcon#*before write, iclass 17, count 0 2006.257.23:16:02.16#ibcon#enter sib2, iclass 17, count 0 2006.257.23:16:02.16#ibcon#flushed, iclass 17, count 0 2006.257.23:16:02.16#ibcon#about to write, iclass 17, count 0 2006.257.23:16:02.16#ibcon#wrote, iclass 17, count 0 2006.257.23:16:02.16#ibcon#about to read 3, iclass 17, count 0 2006.257.23:16:02.20#ibcon#read 3, iclass 17, count 0 2006.257.23:16:02.20#ibcon#about to read 4, iclass 17, count 0 2006.257.23:16:02.20#ibcon#read 4, iclass 17, count 0 2006.257.23:16:02.20#ibcon#about to read 5, iclass 17, count 0 2006.257.23:16:02.20#ibcon#read 5, iclass 17, count 0 2006.257.23:16:02.20#ibcon#about to read 6, iclass 17, count 0 2006.257.23:16:02.20#ibcon#read 6, iclass 17, count 0 2006.257.23:16:02.20#ibcon#end of sib2, iclass 17, count 0 2006.257.23:16:02.20#ibcon#*after write, iclass 17, count 0 2006.257.23:16:02.20#ibcon#*before return 0, iclass 17, count 0 2006.257.23:16:02.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:02.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:02.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.23:16:02.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.23:16:02.20$vck44/va=6,4 2006.257.23:16:02.20#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.23:16:02.20#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.23:16:02.20#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:02.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:02.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:02.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:02.26#ibcon#enter wrdev, iclass 19, count 2 2006.257.23:16:02.26#ibcon#first serial, iclass 19, count 2 2006.257.23:16:02.26#ibcon#enter sib2, iclass 19, count 2 2006.257.23:16:02.26#ibcon#flushed, iclass 19, count 2 2006.257.23:16:02.26#ibcon#about to write, iclass 19, count 2 2006.257.23:16:02.26#ibcon#wrote, iclass 19, count 2 2006.257.23:16:02.26#ibcon#about to read 3, iclass 19, count 2 2006.257.23:16:02.28#ibcon#read 3, iclass 19, count 2 2006.257.23:16:02.28#ibcon#about to read 4, iclass 19, count 2 2006.257.23:16:02.28#ibcon#read 4, iclass 19, count 2 2006.257.23:16:02.28#ibcon#about to read 5, iclass 19, count 2 2006.257.23:16:02.28#ibcon#read 5, iclass 19, count 2 2006.257.23:16:02.28#ibcon#about to read 6, iclass 19, count 2 2006.257.23:16:02.28#ibcon#read 6, iclass 19, count 2 2006.257.23:16:02.28#ibcon#end of sib2, iclass 19, count 2 2006.257.23:16:02.28#ibcon#*mode == 0, iclass 19, count 2 2006.257.23:16:02.28#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.23:16:02.28#ibcon#[25=AT06-04\r\n] 2006.257.23:16:02.28#ibcon#*before write, iclass 19, count 2 2006.257.23:16:02.28#ibcon#enter sib2, iclass 19, count 2 2006.257.23:16:02.28#ibcon#flushed, iclass 19, count 2 2006.257.23:16:02.28#ibcon#about to write, iclass 19, count 2 2006.257.23:16:02.28#ibcon#wrote, iclass 19, count 2 2006.257.23:16:02.28#ibcon#about to read 3, iclass 19, count 2 2006.257.23:16:02.31#ibcon#read 3, iclass 19, count 2 2006.257.23:16:02.31#ibcon#about to read 4, iclass 19, count 2 2006.257.23:16:02.31#ibcon#read 4, iclass 19, count 2 2006.257.23:16:02.31#ibcon#about to read 5, iclass 19, count 2 2006.257.23:16:02.31#ibcon#read 5, iclass 19, count 2 2006.257.23:16:02.31#ibcon#about to read 6, iclass 19, count 2 2006.257.23:16:02.31#ibcon#read 6, iclass 19, count 2 2006.257.23:16:02.31#ibcon#end of sib2, iclass 19, count 2 2006.257.23:16:02.31#ibcon#*after write, iclass 19, count 2 2006.257.23:16:02.31#ibcon#*before return 0, iclass 19, count 2 2006.257.23:16:02.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:02.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:02.31#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.23:16:02.31#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:02.31#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:02.43#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:02.43#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:02.43#ibcon#enter wrdev, iclass 19, count 0 2006.257.23:16:02.43#ibcon#first serial, iclass 19, count 0 2006.257.23:16:02.43#ibcon#enter sib2, iclass 19, count 0 2006.257.23:16:02.43#ibcon#flushed, iclass 19, count 0 2006.257.23:16:02.43#ibcon#about to write, iclass 19, count 0 2006.257.23:16:02.43#ibcon#wrote, iclass 19, count 0 2006.257.23:16:02.43#ibcon#about to read 3, iclass 19, count 0 2006.257.23:16:02.45#ibcon#read 3, iclass 19, count 0 2006.257.23:16:02.45#ibcon#about to read 4, iclass 19, count 0 2006.257.23:16:02.45#ibcon#read 4, iclass 19, count 0 2006.257.23:16:02.45#ibcon#about to read 5, iclass 19, count 0 2006.257.23:16:02.45#ibcon#read 5, iclass 19, count 0 2006.257.23:16:02.45#ibcon#about to read 6, iclass 19, count 0 2006.257.23:16:02.45#ibcon#read 6, iclass 19, count 0 2006.257.23:16:02.45#ibcon#end of sib2, iclass 19, count 0 2006.257.23:16:02.45#ibcon#*mode == 0, iclass 19, count 0 2006.257.23:16:02.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.23:16:02.45#ibcon#[25=USB\r\n] 2006.257.23:16:02.45#ibcon#*before write, iclass 19, count 0 2006.257.23:16:02.45#ibcon#enter sib2, iclass 19, count 0 2006.257.23:16:02.45#ibcon#flushed, iclass 19, count 0 2006.257.23:16:02.45#ibcon#about to write, iclass 19, count 0 2006.257.23:16:02.45#ibcon#wrote, iclass 19, count 0 2006.257.23:16:02.45#ibcon#about to read 3, iclass 19, count 0 2006.257.23:16:02.48#ibcon#read 3, iclass 19, count 0 2006.257.23:16:02.48#ibcon#about to read 4, iclass 19, count 0 2006.257.23:16:02.48#ibcon#read 4, iclass 19, count 0 2006.257.23:16:02.48#ibcon#about to read 5, iclass 19, count 0 2006.257.23:16:02.48#ibcon#read 5, iclass 19, count 0 2006.257.23:16:02.48#ibcon#about to read 6, iclass 19, count 0 2006.257.23:16:02.48#ibcon#read 6, iclass 19, count 0 2006.257.23:16:02.48#ibcon#end of sib2, iclass 19, count 0 2006.257.23:16:02.48#ibcon#*after write, iclass 19, count 0 2006.257.23:16:02.48#ibcon#*before return 0, iclass 19, count 0 2006.257.23:16:02.48#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:02.48#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:02.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.23:16:02.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.23:16:02.48$vck44/valo=7,864.99 2006.257.23:16:02.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.23:16:02.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.23:16:02.48#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:02.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:02.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:02.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:02.48#ibcon#enter wrdev, iclass 21, count 0 2006.257.23:16:02.48#ibcon#first serial, iclass 21, count 0 2006.257.23:16:02.48#ibcon#enter sib2, iclass 21, count 0 2006.257.23:16:02.48#ibcon#flushed, iclass 21, count 0 2006.257.23:16:02.48#ibcon#about to write, iclass 21, count 0 2006.257.23:16:02.48#ibcon#wrote, iclass 21, count 0 2006.257.23:16:02.48#ibcon#about to read 3, iclass 21, count 0 2006.257.23:16:02.50#ibcon#read 3, iclass 21, count 0 2006.257.23:16:02.50#ibcon#about to read 4, iclass 21, count 0 2006.257.23:16:02.50#ibcon#read 4, iclass 21, count 0 2006.257.23:16:02.50#ibcon#about to read 5, iclass 21, count 0 2006.257.23:16:02.50#ibcon#read 5, iclass 21, count 0 2006.257.23:16:02.50#ibcon#about to read 6, iclass 21, count 0 2006.257.23:16:02.50#ibcon#read 6, iclass 21, count 0 2006.257.23:16:02.50#ibcon#end of sib2, iclass 21, count 0 2006.257.23:16:02.50#ibcon#*mode == 0, iclass 21, count 0 2006.257.23:16:02.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.23:16:02.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:16:02.50#ibcon#*before write, iclass 21, count 0 2006.257.23:16:02.50#ibcon#enter sib2, iclass 21, count 0 2006.257.23:16:02.50#ibcon#flushed, iclass 21, count 0 2006.257.23:16:02.50#ibcon#about to write, iclass 21, count 0 2006.257.23:16:02.50#ibcon#wrote, iclass 21, count 0 2006.257.23:16:02.50#ibcon#about to read 3, iclass 21, count 0 2006.257.23:16:02.54#ibcon#read 3, iclass 21, count 0 2006.257.23:16:02.54#ibcon#about to read 4, iclass 21, count 0 2006.257.23:16:02.54#ibcon#read 4, iclass 21, count 0 2006.257.23:16:02.54#ibcon#about to read 5, iclass 21, count 0 2006.257.23:16:02.54#ibcon#read 5, iclass 21, count 0 2006.257.23:16:02.54#ibcon#about to read 6, iclass 21, count 0 2006.257.23:16:02.54#ibcon#read 6, iclass 21, count 0 2006.257.23:16:02.54#ibcon#end of sib2, iclass 21, count 0 2006.257.23:16:02.54#ibcon#*after write, iclass 21, count 0 2006.257.23:16:02.54#ibcon#*before return 0, iclass 21, count 0 2006.257.23:16:02.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:02.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:02.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.23:16:02.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.23:16:02.54$vck44/va=7,4 2006.257.23:16:02.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.23:16:02.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.23:16:02.54#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:02.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:02.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:02.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:02.60#ibcon#enter wrdev, iclass 23, count 2 2006.257.23:16:02.60#ibcon#first serial, iclass 23, count 2 2006.257.23:16:02.60#ibcon#enter sib2, iclass 23, count 2 2006.257.23:16:02.60#ibcon#flushed, iclass 23, count 2 2006.257.23:16:02.60#ibcon#about to write, iclass 23, count 2 2006.257.23:16:02.60#ibcon#wrote, iclass 23, count 2 2006.257.23:16:02.60#ibcon#about to read 3, iclass 23, count 2 2006.257.23:16:02.62#ibcon#read 3, iclass 23, count 2 2006.257.23:16:02.62#ibcon#about to read 4, iclass 23, count 2 2006.257.23:16:02.62#ibcon#read 4, iclass 23, count 2 2006.257.23:16:02.62#ibcon#about to read 5, iclass 23, count 2 2006.257.23:16:02.62#ibcon#read 5, iclass 23, count 2 2006.257.23:16:02.62#ibcon#about to read 6, iclass 23, count 2 2006.257.23:16:02.62#ibcon#read 6, iclass 23, count 2 2006.257.23:16:02.62#ibcon#end of sib2, iclass 23, count 2 2006.257.23:16:02.62#ibcon#*mode == 0, iclass 23, count 2 2006.257.23:16:02.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.23:16:02.62#ibcon#[25=AT07-04\r\n] 2006.257.23:16:02.62#ibcon#*before write, iclass 23, count 2 2006.257.23:16:02.62#ibcon#enter sib2, iclass 23, count 2 2006.257.23:16:02.62#ibcon#flushed, iclass 23, count 2 2006.257.23:16:02.62#ibcon#about to write, iclass 23, count 2 2006.257.23:16:02.62#ibcon#wrote, iclass 23, count 2 2006.257.23:16:02.62#ibcon#about to read 3, iclass 23, count 2 2006.257.23:16:02.65#ibcon#read 3, iclass 23, count 2 2006.257.23:16:02.65#ibcon#about to read 4, iclass 23, count 2 2006.257.23:16:02.65#ibcon#read 4, iclass 23, count 2 2006.257.23:16:02.65#ibcon#about to read 5, iclass 23, count 2 2006.257.23:16:02.65#ibcon#read 5, iclass 23, count 2 2006.257.23:16:02.65#ibcon#about to read 6, iclass 23, count 2 2006.257.23:16:02.65#ibcon#read 6, iclass 23, count 2 2006.257.23:16:02.65#ibcon#end of sib2, iclass 23, count 2 2006.257.23:16:02.65#ibcon#*after write, iclass 23, count 2 2006.257.23:16:02.65#ibcon#*before return 0, iclass 23, count 2 2006.257.23:16:02.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:02.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:02.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.23:16:02.65#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:02.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:02.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:02.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:02.77#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:16:02.77#ibcon#first serial, iclass 23, count 0 2006.257.23:16:02.77#ibcon#enter sib2, iclass 23, count 0 2006.257.23:16:02.77#ibcon#flushed, iclass 23, count 0 2006.257.23:16:02.77#ibcon#about to write, iclass 23, count 0 2006.257.23:16:02.77#ibcon#wrote, iclass 23, count 0 2006.257.23:16:02.77#ibcon#about to read 3, iclass 23, count 0 2006.257.23:16:02.79#ibcon#read 3, iclass 23, count 0 2006.257.23:16:02.79#ibcon#about to read 4, iclass 23, count 0 2006.257.23:16:02.79#ibcon#read 4, iclass 23, count 0 2006.257.23:16:02.79#ibcon#about to read 5, iclass 23, count 0 2006.257.23:16:02.79#ibcon#read 5, iclass 23, count 0 2006.257.23:16:02.79#ibcon#about to read 6, iclass 23, count 0 2006.257.23:16:02.79#ibcon#read 6, iclass 23, count 0 2006.257.23:16:02.79#ibcon#end of sib2, iclass 23, count 0 2006.257.23:16:02.79#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:16:02.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:16:02.79#ibcon#[25=USB\r\n] 2006.257.23:16:02.79#ibcon#*before write, iclass 23, count 0 2006.257.23:16:02.79#ibcon#enter sib2, iclass 23, count 0 2006.257.23:16:02.79#ibcon#flushed, iclass 23, count 0 2006.257.23:16:02.79#ibcon#about to write, iclass 23, count 0 2006.257.23:16:02.79#ibcon#wrote, iclass 23, count 0 2006.257.23:16:02.79#ibcon#about to read 3, iclass 23, count 0 2006.257.23:16:02.82#ibcon#read 3, iclass 23, count 0 2006.257.23:16:02.82#ibcon#about to read 4, iclass 23, count 0 2006.257.23:16:02.82#ibcon#read 4, iclass 23, count 0 2006.257.23:16:02.82#ibcon#about to read 5, iclass 23, count 0 2006.257.23:16:02.82#ibcon#read 5, iclass 23, count 0 2006.257.23:16:02.82#ibcon#about to read 6, iclass 23, count 0 2006.257.23:16:02.82#ibcon#read 6, iclass 23, count 0 2006.257.23:16:02.82#ibcon#end of sib2, iclass 23, count 0 2006.257.23:16:02.82#ibcon#*after write, iclass 23, count 0 2006.257.23:16:02.82#ibcon#*before return 0, iclass 23, count 0 2006.257.23:16:02.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:02.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:02.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:16:02.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:16:02.82$vck44/valo=8,884.99 2006.257.23:16:02.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.23:16:02.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.23:16:02.82#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:02.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:02.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:02.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:02.82#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:16:02.82#ibcon#first serial, iclass 25, count 0 2006.257.23:16:02.82#ibcon#enter sib2, iclass 25, count 0 2006.257.23:16:02.82#ibcon#flushed, iclass 25, count 0 2006.257.23:16:02.82#ibcon#about to write, iclass 25, count 0 2006.257.23:16:02.82#ibcon#wrote, iclass 25, count 0 2006.257.23:16:02.82#ibcon#about to read 3, iclass 25, count 0 2006.257.23:16:02.84#ibcon#read 3, iclass 25, count 0 2006.257.23:16:02.84#ibcon#about to read 4, iclass 25, count 0 2006.257.23:16:02.84#ibcon#read 4, iclass 25, count 0 2006.257.23:16:02.84#ibcon#about to read 5, iclass 25, count 0 2006.257.23:16:02.84#ibcon#read 5, iclass 25, count 0 2006.257.23:16:02.84#ibcon#about to read 6, iclass 25, count 0 2006.257.23:16:02.84#ibcon#read 6, iclass 25, count 0 2006.257.23:16:02.84#ibcon#end of sib2, iclass 25, count 0 2006.257.23:16:02.84#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:16:02.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:16:02.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:16:02.84#ibcon#*before write, iclass 25, count 0 2006.257.23:16:02.84#ibcon#enter sib2, iclass 25, count 0 2006.257.23:16:02.84#ibcon#flushed, iclass 25, count 0 2006.257.23:16:02.84#ibcon#about to write, iclass 25, count 0 2006.257.23:16:02.84#ibcon#wrote, iclass 25, count 0 2006.257.23:16:02.84#ibcon#about to read 3, iclass 25, count 0 2006.257.23:16:02.88#ibcon#read 3, iclass 25, count 0 2006.257.23:16:02.88#ibcon#about to read 4, iclass 25, count 0 2006.257.23:16:02.88#ibcon#read 4, iclass 25, count 0 2006.257.23:16:02.88#ibcon#about to read 5, iclass 25, count 0 2006.257.23:16:02.88#ibcon#read 5, iclass 25, count 0 2006.257.23:16:02.88#ibcon#about to read 6, iclass 25, count 0 2006.257.23:16:02.88#ibcon#read 6, iclass 25, count 0 2006.257.23:16:02.88#ibcon#end of sib2, iclass 25, count 0 2006.257.23:16:02.88#ibcon#*after write, iclass 25, count 0 2006.257.23:16:02.88#ibcon#*before return 0, iclass 25, count 0 2006.257.23:16:02.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:02.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:02.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:16:02.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:16:02.88$vck44/va=8,4 2006.257.23:16:02.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.23:16:02.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.23:16:02.88#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:02.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:16:02.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:16:02.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:16:02.94#ibcon#enter wrdev, iclass 27, count 2 2006.257.23:16:02.94#ibcon#first serial, iclass 27, count 2 2006.257.23:16:02.94#ibcon#enter sib2, iclass 27, count 2 2006.257.23:16:02.94#ibcon#flushed, iclass 27, count 2 2006.257.23:16:02.94#ibcon#about to write, iclass 27, count 2 2006.257.23:16:02.94#ibcon#wrote, iclass 27, count 2 2006.257.23:16:02.94#ibcon#about to read 3, iclass 27, count 2 2006.257.23:16:02.96#ibcon#read 3, iclass 27, count 2 2006.257.23:16:02.96#ibcon#about to read 4, iclass 27, count 2 2006.257.23:16:02.96#ibcon#read 4, iclass 27, count 2 2006.257.23:16:02.96#ibcon#about to read 5, iclass 27, count 2 2006.257.23:16:02.96#ibcon#read 5, iclass 27, count 2 2006.257.23:16:02.96#ibcon#about to read 6, iclass 27, count 2 2006.257.23:16:02.96#ibcon#read 6, iclass 27, count 2 2006.257.23:16:02.96#ibcon#end of sib2, iclass 27, count 2 2006.257.23:16:02.96#ibcon#*mode == 0, iclass 27, count 2 2006.257.23:16:02.96#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.23:16:02.96#ibcon#[25=AT08-04\r\n] 2006.257.23:16:02.96#ibcon#*before write, iclass 27, count 2 2006.257.23:16:02.96#ibcon#enter sib2, iclass 27, count 2 2006.257.23:16:02.96#ibcon#flushed, iclass 27, count 2 2006.257.23:16:02.96#ibcon#about to write, iclass 27, count 2 2006.257.23:16:02.96#ibcon#wrote, iclass 27, count 2 2006.257.23:16:02.96#ibcon#about to read 3, iclass 27, count 2 2006.257.23:16:02.99#ibcon#read 3, iclass 27, count 2 2006.257.23:16:02.99#ibcon#about to read 4, iclass 27, count 2 2006.257.23:16:02.99#ibcon#read 4, iclass 27, count 2 2006.257.23:16:02.99#ibcon#about to read 5, iclass 27, count 2 2006.257.23:16:02.99#ibcon#read 5, iclass 27, count 2 2006.257.23:16:02.99#ibcon#about to read 6, iclass 27, count 2 2006.257.23:16:02.99#ibcon#read 6, iclass 27, count 2 2006.257.23:16:02.99#ibcon#end of sib2, iclass 27, count 2 2006.257.23:16:02.99#ibcon#*after write, iclass 27, count 2 2006.257.23:16:02.99#ibcon#*before return 0, iclass 27, count 2 2006.257.23:16:02.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:16:02.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:16:02.99#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.23:16:02.99#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:02.99#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:16:03.11#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:16:03.11#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:16:03.11#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:16:03.11#ibcon#first serial, iclass 27, count 0 2006.257.23:16:03.11#ibcon#enter sib2, iclass 27, count 0 2006.257.23:16:03.11#ibcon#flushed, iclass 27, count 0 2006.257.23:16:03.11#ibcon#about to write, iclass 27, count 0 2006.257.23:16:03.11#ibcon#wrote, iclass 27, count 0 2006.257.23:16:03.11#ibcon#about to read 3, iclass 27, count 0 2006.257.23:16:03.13#ibcon#read 3, iclass 27, count 0 2006.257.23:16:03.13#ibcon#about to read 4, iclass 27, count 0 2006.257.23:16:03.13#ibcon#read 4, iclass 27, count 0 2006.257.23:16:03.13#ibcon#about to read 5, iclass 27, count 0 2006.257.23:16:03.13#ibcon#read 5, iclass 27, count 0 2006.257.23:16:03.13#ibcon#about to read 6, iclass 27, count 0 2006.257.23:16:03.13#ibcon#read 6, iclass 27, count 0 2006.257.23:16:03.13#ibcon#end of sib2, iclass 27, count 0 2006.257.23:16:03.13#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:16:03.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:16:03.13#ibcon#[25=USB\r\n] 2006.257.23:16:03.13#ibcon#*before write, iclass 27, count 0 2006.257.23:16:03.13#ibcon#enter sib2, iclass 27, count 0 2006.257.23:16:03.13#ibcon#flushed, iclass 27, count 0 2006.257.23:16:03.13#ibcon#about to write, iclass 27, count 0 2006.257.23:16:03.13#ibcon#wrote, iclass 27, count 0 2006.257.23:16:03.13#ibcon#about to read 3, iclass 27, count 0 2006.257.23:16:03.16#ibcon#read 3, iclass 27, count 0 2006.257.23:16:03.16#ibcon#about to read 4, iclass 27, count 0 2006.257.23:16:03.16#ibcon#read 4, iclass 27, count 0 2006.257.23:16:03.16#ibcon#about to read 5, iclass 27, count 0 2006.257.23:16:03.16#ibcon#read 5, iclass 27, count 0 2006.257.23:16:03.16#ibcon#about to read 6, iclass 27, count 0 2006.257.23:16:03.16#ibcon#read 6, iclass 27, count 0 2006.257.23:16:03.16#ibcon#end of sib2, iclass 27, count 0 2006.257.23:16:03.16#ibcon#*after write, iclass 27, count 0 2006.257.23:16:03.16#ibcon#*before return 0, iclass 27, count 0 2006.257.23:16:03.16#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:16:03.16#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:16:03.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:16:03.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:16:03.16$vck44/vblo=1,629.99 2006.257.23:16:03.16#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.23:16:03.16#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.23:16:03.16#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:03.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:16:03.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:16:03.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:16:03.16#ibcon#enter wrdev, iclass 29, count 0 2006.257.23:16:03.16#ibcon#first serial, iclass 29, count 0 2006.257.23:16:03.16#ibcon#enter sib2, iclass 29, count 0 2006.257.23:16:03.16#ibcon#flushed, iclass 29, count 0 2006.257.23:16:03.16#ibcon#about to write, iclass 29, count 0 2006.257.23:16:03.16#ibcon#wrote, iclass 29, count 0 2006.257.23:16:03.16#ibcon#about to read 3, iclass 29, count 0 2006.257.23:16:03.18#ibcon#read 3, iclass 29, count 0 2006.257.23:16:03.18#ibcon#about to read 4, iclass 29, count 0 2006.257.23:16:03.18#ibcon#read 4, iclass 29, count 0 2006.257.23:16:03.18#ibcon#about to read 5, iclass 29, count 0 2006.257.23:16:03.18#ibcon#read 5, iclass 29, count 0 2006.257.23:16:03.18#ibcon#about to read 6, iclass 29, count 0 2006.257.23:16:03.18#ibcon#read 6, iclass 29, count 0 2006.257.23:16:03.18#ibcon#end of sib2, iclass 29, count 0 2006.257.23:16:03.18#ibcon#*mode == 0, iclass 29, count 0 2006.257.23:16:03.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.23:16:03.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:16:03.18#ibcon#*before write, iclass 29, count 0 2006.257.23:16:03.18#ibcon#enter sib2, iclass 29, count 0 2006.257.23:16:03.18#ibcon#flushed, iclass 29, count 0 2006.257.23:16:03.18#ibcon#about to write, iclass 29, count 0 2006.257.23:16:03.18#ibcon#wrote, iclass 29, count 0 2006.257.23:16:03.18#ibcon#about to read 3, iclass 29, count 0 2006.257.23:16:03.22#ibcon#read 3, iclass 29, count 0 2006.257.23:16:03.22#ibcon#about to read 4, iclass 29, count 0 2006.257.23:16:03.22#ibcon#read 4, iclass 29, count 0 2006.257.23:16:03.22#ibcon#about to read 5, iclass 29, count 0 2006.257.23:16:03.22#ibcon#read 5, iclass 29, count 0 2006.257.23:16:03.22#ibcon#about to read 6, iclass 29, count 0 2006.257.23:16:03.22#ibcon#read 6, iclass 29, count 0 2006.257.23:16:03.22#ibcon#end of sib2, iclass 29, count 0 2006.257.23:16:03.22#ibcon#*after write, iclass 29, count 0 2006.257.23:16:03.22#ibcon#*before return 0, iclass 29, count 0 2006.257.23:16:03.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:16:03.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:16:03.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.23:16:03.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.23:16:03.22$vck44/vb=1,4 2006.257.23:16:03.22#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.23:16:03.22#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.23:16:03.22#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:03.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:16:03.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:16:03.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:16:03.22#ibcon#enter wrdev, iclass 31, count 2 2006.257.23:16:03.22#ibcon#first serial, iclass 31, count 2 2006.257.23:16:03.22#ibcon#enter sib2, iclass 31, count 2 2006.257.23:16:03.22#ibcon#flushed, iclass 31, count 2 2006.257.23:16:03.22#ibcon#about to write, iclass 31, count 2 2006.257.23:16:03.22#ibcon#wrote, iclass 31, count 2 2006.257.23:16:03.22#ibcon#about to read 3, iclass 31, count 2 2006.257.23:16:03.24#ibcon#read 3, iclass 31, count 2 2006.257.23:16:03.24#ibcon#about to read 4, iclass 31, count 2 2006.257.23:16:03.24#ibcon#read 4, iclass 31, count 2 2006.257.23:16:03.24#ibcon#about to read 5, iclass 31, count 2 2006.257.23:16:03.24#ibcon#read 5, iclass 31, count 2 2006.257.23:16:03.24#ibcon#about to read 6, iclass 31, count 2 2006.257.23:16:03.24#ibcon#read 6, iclass 31, count 2 2006.257.23:16:03.24#ibcon#end of sib2, iclass 31, count 2 2006.257.23:16:03.24#ibcon#*mode == 0, iclass 31, count 2 2006.257.23:16:03.24#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.23:16:03.24#ibcon#[27=AT01-04\r\n] 2006.257.23:16:03.24#ibcon#*before write, iclass 31, count 2 2006.257.23:16:03.24#ibcon#enter sib2, iclass 31, count 2 2006.257.23:16:03.24#ibcon#flushed, iclass 31, count 2 2006.257.23:16:03.24#ibcon#about to write, iclass 31, count 2 2006.257.23:16:03.24#ibcon#wrote, iclass 31, count 2 2006.257.23:16:03.24#ibcon#about to read 3, iclass 31, count 2 2006.257.23:16:03.27#ibcon#read 3, iclass 31, count 2 2006.257.23:16:03.27#ibcon#about to read 4, iclass 31, count 2 2006.257.23:16:03.27#ibcon#read 4, iclass 31, count 2 2006.257.23:16:03.27#ibcon#about to read 5, iclass 31, count 2 2006.257.23:16:03.27#ibcon#read 5, iclass 31, count 2 2006.257.23:16:03.27#ibcon#about to read 6, iclass 31, count 2 2006.257.23:16:03.27#ibcon#read 6, iclass 31, count 2 2006.257.23:16:03.27#ibcon#end of sib2, iclass 31, count 2 2006.257.23:16:03.27#ibcon#*after write, iclass 31, count 2 2006.257.23:16:03.27#ibcon#*before return 0, iclass 31, count 2 2006.257.23:16:03.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:16:03.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:16:03.27#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.23:16:03.27#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:03.27#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:16:03.39#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:16:03.39#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:16:03.39#ibcon#enter wrdev, iclass 31, count 0 2006.257.23:16:03.39#ibcon#first serial, iclass 31, count 0 2006.257.23:16:03.39#ibcon#enter sib2, iclass 31, count 0 2006.257.23:16:03.39#ibcon#flushed, iclass 31, count 0 2006.257.23:16:03.39#ibcon#about to write, iclass 31, count 0 2006.257.23:16:03.39#ibcon#wrote, iclass 31, count 0 2006.257.23:16:03.39#ibcon#about to read 3, iclass 31, count 0 2006.257.23:16:03.41#ibcon#read 3, iclass 31, count 0 2006.257.23:16:03.41#ibcon#about to read 4, iclass 31, count 0 2006.257.23:16:03.41#ibcon#read 4, iclass 31, count 0 2006.257.23:16:03.41#ibcon#about to read 5, iclass 31, count 0 2006.257.23:16:03.41#ibcon#read 5, iclass 31, count 0 2006.257.23:16:03.41#ibcon#about to read 6, iclass 31, count 0 2006.257.23:16:03.41#ibcon#read 6, iclass 31, count 0 2006.257.23:16:03.41#ibcon#end of sib2, iclass 31, count 0 2006.257.23:16:03.41#ibcon#*mode == 0, iclass 31, count 0 2006.257.23:16:03.41#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.23:16:03.41#ibcon#[27=USB\r\n] 2006.257.23:16:03.41#ibcon#*before write, iclass 31, count 0 2006.257.23:16:03.41#ibcon#enter sib2, iclass 31, count 0 2006.257.23:16:03.41#ibcon#flushed, iclass 31, count 0 2006.257.23:16:03.41#ibcon#about to write, iclass 31, count 0 2006.257.23:16:03.41#ibcon#wrote, iclass 31, count 0 2006.257.23:16:03.41#ibcon#about to read 3, iclass 31, count 0 2006.257.23:16:03.44#ibcon#read 3, iclass 31, count 0 2006.257.23:16:03.44#ibcon#about to read 4, iclass 31, count 0 2006.257.23:16:03.44#ibcon#read 4, iclass 31, count 0 2006.257.23:16:03.44#ibcon#about to read 5, iclass 31, count 0 2006.257.23:16:03.44#ibcon#read 5, iclass 31, count 0 2006.257.23:16:03.44#ibcon#about to read 6, iclass 31, count 0 2006.257.23:16:03.44#ibcon#read 6, iclass 31, count 0 2006.257.23:16:03.44#ibcon#end of sib2, iclass 31, count 0 2006.257.23:16:03.44#ibcon#*after write, iclass 31, count 0 2006.257.23:16:03.44#ibcon#*before return 0, iclass 31, count 0 2006.257.23:16:03.44#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:16:03.44#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:16:03.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.23:16:03.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.23:16:03.44$vck44/vblo=2,634.99 2006.257.23:16:03.44#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.23:16:03.44#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.23:16:03.44#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:03.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:03.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:03.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:03.44#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:16:03.44#ibcon#first serial, iclass 33, count 0 2006.257.23:16:03.44#ibcon#enter sib2, iclass 33, count 0 2006.257.23:16:03.44#ibcon#flushed, iclass 33, count 0 2006.257.23:16:03.44#ibcon#about to write, iclass 33, count 0 2006.257.23:16:03.44#ibcon#wrote, iclass 33, count 0 2006.257.23:16:03.44#ibcon#about to read 3, iclass 33, count 0 2006.257.23:16:03.46#ibcon#read 3, iclass 33, count 0 2006.257.23:16:03.46#ibcon#about to read 4, iclass 33, count 0 2006.257.23:16:03.46#ibcon#read 4, iclass 33, count 0 2006.257.23:16:03.46#ibcon#about to read 5, iclass 33, count 0 2006.257.23:16:03.46#ibcon#read 5, iclass 33, count 0 2006.257.23:16:03.46#ibcon#about to read 6, iclass 33, count 0 2006.257.23:16:03.46#ibcon#read 6, iclass 33, count 0 2006.257.23:16:03.46#ibcon#end of sib2, iclass 33, count 0 2006.257.23:16:03.46#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:16:03.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:16:03.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:16:03.46#ibcon#*before write, iclass 33, count 0 2006.257.23:16:03.46#ibcon#enter sib2, iclass 33, count 0 2006.257.23:16:03.46#ibcon#flushed, iclass 33, count 0 2006.257.23:16:03.46#ibcon#about to write, iclass 33, count 0 2006.257.23:16:03.46#ibcon#wrote, iclass 33, count 0 2006.257.23:16:03.46#ibcon#about to read 3, iclass 33, count 0 2006.257.23:16:03.50#ibcon#read 3, iclass 33, count 0 2006.257.23:16:03.50#ibcon#about to read 4, iclass 33, count 0 2006.257.23:16:03.50#ibcon#read 4, iclass 33, count 0 2006.257.23:16:03.50#ibcon#about to read 5, iclass 33, count 0 2006.257.23:16:03.50#ibcon#read 5, iclass 33, count 0 2006.257.23:16:03.50#ibcon#about to read 6, iclass 33, count 0 2006.257.23:16:03.50#ibcon#read 6, iclass 33, count 0 2006.257.23:16:03.50#ibcon#end of sib2, iclass 33, count 0 2006.257.23:16:03.50#ibcon#*after write, iclass 33, count 0 2006.257.23:16:03.50#ibcon#*before return 0, iclass 33, count 0 2006.257.23:16:03.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:03.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:16:03.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:16:03.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:16:03.50$vck44/vb=2,5 2006.257.23:16:03.50#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.23:16:03.50#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.23:16:03.50#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:03.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:03.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:03.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:03.56#ibcon#enter wrdev, iclass 35, count 2 2006.257.23:16:03.56#ibcon#first serial, iclass 35, count 2 2006.257.23:16:03.56#ibcon#enter sib2, iclass 35, count 2 2006.257.23:16:03.56#ibcon#flushed, iclass 35, count 2 2006.257.23:16:03.56#ibcon#about to write, iclass 35, count 2 2006.257.23:16:03.56#ibcon#wrote, iclass 35, count 2 2006.257.23:16:03.56#ibcon#about to read 3, iclass 35, count 2 2006.257.23:16:03.58#ibcon#read 3, iclass 35, count 2 2006.257.23:16:03.58#ibcon#about to read 4, iclass 35, count 2 2006.257.23:16:03.58#ibcon#read 4, iclass 35, count 2 2006.257.23:16:03.58#ibcon#about to read 5, iclass 35, count 2 2006.257.23:16:03.58#ibcon#read 5, iclass 35, count 2 2006.257.23:16:03.58#ibcon#about to read 6, iclass 35, count 2 2006.257.23:16:03.58#ibcon#read 6, iclass 35, count 2 2006.257.23:16:03.58#ibcon#end of sib2, iclass 35, count 2 2006.257.23:16:03.58#ibcon#*mode == 0, iclass 35, count 2 2006.257.23:16:03.58#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.23:16:03.58#ibcon#[27=AT02-05\r\n] 2006.257.23:16:03.58#ibcon#*before write, iclass 35, count 2 2006.257.23:16:03.58#ibcon#enter sib2, iclass 35, count 2 2006.257.23:16:03.58#ibcon#flushed, iclass 35, count 2 2006.257.23:16:03.58#ibcon#about to write, iclass 35, count 2 2006.257.23:16:03.58#ibcon#wrote, iclass 35, count 2 2006.257.23:16:03.58#ibcon#about to read 3, iclass 35, count 2 2006.257.23:16:03.61#ibcon#read 3, iclass 35, count 2 2006.257.23:16:03.61#ibcon#about to read 4, iclass 35, count 2 2006.257.23:16:03.61#ibcon#read 4, iclass 35, count 2 2006.257.23:16:03.61#ibcon#about to read 5, iclass 35, count 2 2006.257.23:16:03.61#ibcon#read 5, iclass 35, count 2 2006.257.23:16:03.61#ibcon#about to read 6, iclass 35, count 2 2006.257.23:16:03.61#ibcon#read 6, iclass 35, count 2 2006.257.23:16:03.61#ibcon#end of sib2, iclass 35, count 2 2006.257.23:16:03.61#ibcon#*after write, iclass 35, count 2 2006.257.23:16:03.61#ibcon#*before return 0, iclass 35, count 2 2006.257.23:16:03.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:03.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:16:03.61#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.23:16:03.61#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:03.61#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:03.73#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:03.73#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:03.73#ibcon#enter wrdev, iclass 35, count 0 2006.257.23:16:03.73#ibcon#first serial, iclass 35, count 0 2006.257.23:16:03.73#ibcon#enter sib2, iclass 35, count 0 2006.257.23:16:03.73#ibcon#flushed, iclass 35, count 0 2006.257.23:16:03.73#ibcon#about to write, iclass 35, count 0 2006.257.23:16:03.73#ibcon#wrote, iclass 35, count 0 2006.257.23:16:03.73#ibcon#about to read 3, iclass 35, count 0 2006.257.23:16:03.75#ibcon#read 3, iclass 35, count 0 2006.257.23:16:03.75#ibcon#about to read 4, iclass 35, count 0 2006.257.23:16:03.75#ibcon#read 4, iclass 35, count 0 2006.257.23:16:03.75#ibcon#about to read 5, iclass 35, count 0 2006.257.23:16:03.75#ibcon#read 5, iclass 35, count 0 2006.257.23:16:03.75#ibcon#about to read 6, iclass 35, count 0 2006.257.23:16:03.75#ibcon#read 6, iclass 35, count 0 2006.257.23:16:03.75#ibcon#end of sib2, iclass 35, count 0 2006.257.23:16:03.75#ibcon#*mode == 0, iclass 35, count 0 2006.257.23:16:03.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.23:16:03.75#ibcon#[27=USB\r\n] 2006.257.23:16:03.75#ibcon#*before write, iclass 35, count 0 2006.257.23:16:03.75#ibcon#enter sib2, iclass 35, count 0 2006.257.23:16:03.75#ibcon#flushed, iclass 35, count 0 2006.257.23:16:03.75#ibcon#about to write, iclass 35, count 0 2006.257.23:16:03.75#ibcon#wrote, iclass 35, count 0 2006.257.23:16:03.75#ibcon#about to read 3, iclass 35, count 0 2006.257.23:16:03.78#ibcon#read 3, iclass 35, count 0 2006.257.23:16:03.78#ibcon#about to read 4, iclass 35, count 0 2006.257.23:16:03.78#ibcon#read 4, iclass 35, count 0 2006.257.23:16:03.78#ibcon#about to read 5, iclass 35, count 0 2006.257.23:16:03.78#ibcon#read 5, iclass 35, count 0 2006.257.23:16:03.78#ibcon#about to read 6, iclass 35, count 0 2006.257.23:16:03.78#ibcon#read 6, iclass 35, count 0 2006.257.23:16:03.78#ibcon#end of sib2, iclass 35, count 0 2006.257.23:16:03.78#ibcon#*after write, iclass 35, count 0 2006.257.23:16:03.78#ibcon#*before return 0, iclass 35, count 0 2006.257.23:16:03.78#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:03.78#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:16:03.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.23:16:03.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.23:16:03.78$vck44/vblo=3,649.99 2006.257.23:16:03.78#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.23:16:03.78#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.23:16:03.78#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:03.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:03.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:03.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:03.78#ibcon#enter wrdev, iclass 37, count 0 2006.257.23:16:03.78#ibcon#first serial, iclass 37, count 0 2006.257.23:16:03.78#ibcon#enter sib2, iclass 37, count 0 2006.257.23:16:03.78#ibcon#flushed, iclass 37, count 0 2006.257.23:16:03.78#ibcon#about to write, iclass 37, count 0 2006.257.23:16:03.78#ibcon#wrote, iclass 37, count 0 2006.257.23:16:03.78#ibcon#about to read 3, iclass 37, count 0 2006.257.23:16:03.80#ibcon#read 3, iclass 37, count 0 2006.257.23:16:03.80#ibcon#about to read 4, iclass 37, count 0 2006.257.23:16:03.80#ibcon#read 4, iclass 37, count 0 2006.257.23:16:03.80#ibcon#about to read 5, iclass 37, count 0 2006.257.23:16:03.80#ibcon#read 5, iclass 37, count 0 2006.257.23:16:03.80#ibcon#about to read 6, iclass 37, count 0 2006.257.23:16:03.80#ibcon#read 6, iclass 37, count 0 2006.257.23:16:03.80#ibcon#end of sib2, iclass 37, count 0 2006.257.23:16:03.80#ibcon#*mode == 0, iclass 37, count 0 2006.257.23:16:03.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.23:16:03.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:16:03.80#ibcon#*before write, iclass 37, count 0 2006.257.23:16:03.80#ibcon#enter sib2, iclass 37, count 0 2006.257.23:16:03.80#ibcon#flushed, iclass 37, count 0 2006.257.23:16:03.80#ibcon#about to write, iclass 37, count 0 2006.257.23:16:03.80#ibcon#wrote, iclass 37, count 0 2006.257.23:16:03.80#ibcon#about to read 3, iclass 37, count 0 2006.257.23:16:03.84#ibcon#read 3, iclass 37, count 0 2006.257.23:16:03.84#ibcon#about to read 4, iclass 37, count 0 2006.257.23:16:03.84#ibcon#read 4, iclass 37, count 0 2006.257.23:16:03.84#ibcon#about to read 5, iclass 37, count 0 2006.257.23:16:03.84#ibcon#read 5, iclass 37, count 0 2006.257.23:16:03.84#ibcon#about to read 6, iclass 37, count 0 2006.257.23:16:03.84#ibcon#read 6, iclass 37, count 0 2006.257.23:16:03.84#ibcon#end of sib2, iclass 37, count 0 2006.257.23:16:03.84#ibcon#*after write, iclass 37, count 0 2006.257.23:16:03.84#ibcon#*before return 0, iclass 37, count 0 2006.257.23:16:03.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:03.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:16:03.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.23:16:03.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.23:16:03.84$vck44/vb=3,4 2006.257.23:16:03.84#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.23:16:03.84#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.23:16:03.84#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:03.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:03.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:03.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:03.90#ibcon#enter wrdev, iclass 39, count 2 2006.257.23:16:03.90#ibcon#first serial, iclass 39, count 2 2006.257.23:16:03.90#ibcon#enter sib2, iclass 39, count 2 2006.257.23:16:03.90#ibcon#flushed, iclass 39, count 2 2006.257.23:16:03.90#ibcon#about to write, iclass 39, count 2 2006.257.23:16:03.90#ibcon#wrote, iclass 39, count 2 2006.257.23:16:03.90#ibcon#about to read 3, iclass 39, count 2 2006.257.23:16:03.92#ibcon#read 3, iclass 39, count 2 2006.257.23:16:03.92#ibcon#about to read 4, iclass 39, count 2 2006.257.23:16:03.92#ibcon#read 4, iclass 39, count 2 2006.257.23:16:03.92#ibcon#about to read 5, iclass 39, count 2 2006.257.23:16:03.92#ibcon#read 5, iclass 39, count 2 2006.257.23:16:03.92#ibcon#about to read 6, iclass 39, count 2 2006.257.23:16:03.92#ibcon#read 6, iclass 39, count 2 2006.257.23:16:03.92#ibcon#end of sib2, iclass 39, count 2 2006.257.23:16:03.92#ibcon#*mode == 0, iclass 39, count 2 2006.257.23:16:03.92#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.23:16:03.92#ibcon#[27=AT03-04\r\n] 2006.257.23:16:03.92#ibcon#*before write, iclass 39, count 2 2006.257.23:16:03.92#ibcon#enter sib2, iclass 39, count 2 2006.257.23:16:03.92#ibcon#flushed, iclass 39, count 2 2006.257.23:16:03.92#ibcon#about to write, iclass 39, count 2 2006.257.23:16:03.92#ibcon#wrote, iclass 39, count 2 2006.257.23:16:03.92#ibcon#about to read 3, iclass 39, count 2 2006.257.23:16:03.95#ibcon#read 3, iclass 39, count 2 2006.257.23:16:03.95#ibcon#about to read 4, iclass 39, count 2 2006.257.23:16:03.95#ibcon#read 4, iclass 39, count 2 2006.257.23:16:03.95#ibcon#about to read 5, iclass 39, count 2 2006.257.23:16:03.95#ibcon#read 5, iclass 39, count 2 2006.257.23:16:03.95#ibcon#about to read 6, iclass 39, count 2 2006.257.23:16:03.95#ibcon#read 6, iclass 39, count 2 2006.257.23:16:03.95#ibcon#end of sib2, iclass 39, count 2 2006.257.23:16:03.95#ibcon#*after write, iclass 39, count 2 2006.257.23:16:03.95#ibcon#*before return 0, iclass 39, count 2 2006.257.23:16:03.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:03.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:16:03.95#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.23:16:03.95#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:03.95#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:04.07#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:04.07#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:04.07#ibcon#enter wrdev, iclass 39, count 0 2006.257.23:16:04.07#ibcon#first serial, iclass 39, count 0 2006.257.23:16:04.07#ibcon#enter sib2, iclass 39, count 0 2006.257.23:16:04.07#ibcon#flushed, iclass 39, count 0 2006.257.23:16:04.07#ibcon#about to write, iclass 39, count 0 2006.257.23:16:04.07#ibcon#wrote, iclass 39, count 0 2006.257.23:16:04.07#ibcon#about to read 3, iclass 39, count 0 2006.257.23:16:04.09#ibcon#read 3, iclass 39, count 0 2006.257.23:16:04.09#ibcon#about to read 4, iclass 39, count 0 2006.257.23:16:04.09#ibcon#read 4, iclass 39, count 0 2006.257.23:16:04.09#ibcon#about to read 5, iclass 39, count 0 2006.257.23:16:04.09#ibcon#read 5, iclass 39, count 0 2006.257.23:16:04.09#ibcon#about to read 6, iclass 39, count 0 2006.257.23:16:04.09#ibcon#read 6, iclass 39, count 0 2006.257.23:16:04.09#ibcon#end of sib2, iclass 39, count 0 2006.257.23:16:04.09#ibcon#*mode == 0, iclass 39, count 0 2006.257.23:16:04.09#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.23:16:04.09#ibcon#[27=USB\r\n] 2006.257.23:16:04.09#ibcon#*before write, iclass 39, count 0 2006.257.23:16:04.09#ibcon#enter sib2, iclass 39, count 0 2006.257.23:16:04.09#ibcon#flushed, iclass 39, count 0 2006.257.23:16:04.09#ibcon#about to write, iclass 39, count 0 2006.257.23:16:04.09#ibcon#wrote, iclass 39, count 0 2006.257.23:16:04.09#ibcon#about to read 3, iclass 39, count 0 2006.257.23:16:04.12#ibcon#read 3, iclass 39, count 0 2006.257.23:16:04.12#ibcon#about to read 4, iclass 39, count 0 2006.257.23:16:04.12#ibcon#read 4, iclass 39, count 0 2006.257.23:16:04.12#ibcon#about to read 5, iclass 39, count 0 2006.257.23:16:04.12#ibcon#read 5, iclass 39, count 0 2006.257.23:16:04.12#ibcon#about to read 6, iclass 39, count 0 2006.257.23:16:04.12#ibcon#read 6, iclass 39, count 0 2006.257.23:16:04.12#ibcon#end of sib2, iclass 39, count 0 2006.257.23:16:04.12#ibcon#*after write, iclass 39, count 0 2006.257.23:16:04.12#ibcon#*before return 0, iclass 39, count 0 2006.257.23:16:04.12#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:04.12#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:16:04.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.23:16:04.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.23:16:04.12$vck44/vblo=4,679.99 2006.257.23:16:04.12#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.23:16:04.12#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.23:16:04.12#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:04.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:04.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:04.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:04.12#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:16:04.12#ibcon#first serial, iclass 3, count 0 2006.257.23:16:04.12#ibcon#enter sib2, iclass 3, count 0 2006.257.23:16:04.12#ibcon#flushed, iclass 3, count 0 2006.257.23:16:04.12#ibcon#about to write, iclass 3, count 0 2006.257.23:16:04.12#ibcon#wrote, iclass 3, count 0 2006.257.23:16:04.12#ibcon#about to read 3, iclass 3, count 0 2006.257.23:16:04.14#ibcon#read 3, iclass 3, count 0 2006.257.23:16:04.14#ibcon#about to read 4, iclass 3, count 0 2006.257.23:16:04.14#ibcon#read 4, iclass 3, count 0 2006.257.23:16:04.14#ibcon#about to read 5, iclass 3, count 0 2006.257.23:16:04.14#ibcon#read 5, iclass 3, count 0 2006.257.23:16:04.14#ibcon#about to read 6, iclass 3, count 0 2006.257.23:16:04.14#ibcon#read 6, iclass 3, count 0 2006.257.23:16:04.14#ibcon#end of sib2, iclass 3, count 0 2006.257.23:16:04.14#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:16:04.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:16:04.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:16:04.14#ibcon#*before write, iclass 3, count 0 2006.257.23:16:04.14#ibcon#enter sib2, iclass 3, count 0 2006.257.23:16:04.14#ibcon#flushed, iclass 3, count 0 2006.257.23:16:04.14#ibcon#about to write, iclass 3, count 0 2006.257.23:16:04.14#ibcon#wrote, iclass 3, count 0 2006.257.23:16:04.14#ibcon#about to read 3, iclass 3, count 0 2006.257.23:16:04.18#ibcon#read 3, iclass 3, count 0 2006.257.23:16:04.18#ibcon#about to read 4, iclass 3, count 0 2006.257.23:16:04.18#ibcon#read 4, iclass 3, count 0 2006.257.23:16:04.18#ibcon#about to read 5, iclass 3, count 0 2006.257.23:16:04.18#ibcon#read 5, iclass 3, count 0 2006.257.23:16:04.18#ibcon#about to read 6, iclass 3, count 0 2006.257.23:16:04.18#ibcon#read 6, iclass 3, count 0 2006.257.23:16:04.18#ibcon#end of sib2, iclass 3, count 0 2006.257.23:16:04.18#ibcon#*after write, iclass 3, count 0 2006.257.23:16:04.18#ibcon#*before return 0, iclass 3, count 0 2006.257.23:16:04.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:04.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:16:04.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:16:04.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:16:04.18$vck44/vb=4,5 2006.257.23:16:04.18#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.23:16:04.18#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.23:16:04.18#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:04.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:04.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:04.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:04.24#ibcon#enter wrdev, iclass 5, count 2 2006.257.23:16:04.24#ibcon#first serial, iclass 5, count 2 2006.257.23:16:04.24#ibcon#enter sib2, iclass 5, count 2 2006.257.23:16:04.24#ibcon#flushed, iclass 5, count 2 2006.257.23:16:04.24#ibcon#about to write, iclass 5, count 2 2006.257.23:16:04.24#ibcon#wrote, iclass 5, count 2 2006.257.23:16:04.24#ibcon#about to read 3, iclass 5, count 2 2006.257.23:16:04.26#ibcon#read 3, iclass 5, count 2 2006.257.23:16:04.26#ibcon#about to read 4, iclass 5, count 2 2006.257.23:16:04.26#ibcon#read 4, iclass 5, count 2 2006.257.23:16:04.26#ibcon#about to read 5, iclass 5, count 2 2006.257.23:16:04.26#ibcon#read 5, iclass 5, count 2 2006.257.23:16:04.26#ibcon#about to read 6, iclass 5, count 2 2006.257.23:16:04.26#ibcon#read 6, iclass 5, count 2 2006.257.23:16:04.26#ibcon#end of sib2, iclass 5, count 2 2006.257.23:16:04.26#ibcon#*mode == 0, iclass 5, count 2 2006.257.23:16:04.26#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.23:16:04.26#ibcon#[27=AT04-05\r\n] 2006.257.23:16:04.26#ibcon#*before write, iclass 5, count 2 2006.257.23:16:04.26#ibcon#enter sib2, iclass 5, count 2 2006.257.23:16:04.26#ibcon#flushed, iclass 5, count 2 2006.257.23:16:04.26#ibcon#about to write, iclass 5, count 2 2006.257.23:16:04.26#ibcon#wrote, iclass 5, count 2 2006.257.23:16:04.26#ibcon#about to read 3, iclass 5, count 2 2006.257.23:16:04.29#ibcon#read 3, iclass 5, count 2 2006.257.23:16:04.29#ibcon#about to read 4, iclass 5, count 2 2006.257.23:16:04.29#ibcon#read 4, iclass 5, count 2 2006.257.23:16:04.29#ibcon#about to read 5, iclass 5, count 2 2006.257.23:16:04.29#ibcon#read 5, iclass 5, count 2 2006.257.23:16:04.29#ibcon#about to read 6, iclass 5, count 2 2006.257.23:16:04.29#ibcon#read 6, iclass 5, count 2 2006.257.23:16:04.29#ibcon#end of sib2, iclass 5, count 2 2006.257.23:16:04.29#ibcon#*after write, iclass 5, count 2 2006.257.23:16:04.29#ibcon#*before return 0, iclass 5, count 2 2006.257.23:16:04.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:04.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:16:04.29#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.23:16:04.29#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:04.29#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:04.41#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:04.41#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:04.41#ibcon#enter wrdev, iclass 5, count 0 2006.257.23:16:04.41#ibcon#first serial, iclass 5, count 0 2006.257.23:16:04.41#ibcon#enter sib2, iclass 5, count 0 2006.257.23:16:04.41#ibcon#flushed, iclass 5, count 0 2006.257.23:16:04.41#ibcon#about to write, iclass 5, count 0 2006.257.23:16:04.41#ibcon#wrote, iclass 5, count 0 2006.257.23:16:04.41#ibcon#about to read 3, iclass 5, count 0 2006.257.23:16:04.43#ibcon#read 3, iclass 5, count 0 2006.257.23:16:04.43#ibcon#about to read 4, iclass 5, count 0 2006.257.23:16:04.43#ibcon#read 4, iclass 5, count 0 2006.257.23:16:04.43#ibcon#about to read 5, iclass 5, count 0 2006.257.23:16:04.43#ibcon#read 5, iclass 5, count 0 2006.257.23:16:04.43#ibcon#about to read 6, iclass 5, count 0 2006.257.23:16:04.43#ibcon#read 6, iclass 5, count 0 2006.257.23:16:04.43#ibcon#end of sib2, iclass 5, count 0 2006.257.23:16:04.43#ibcon#*mode == 0, iclass 5, count 0 2006.257.23:16:04.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.23:16:04.43#ibcon#[27=USB\r\n] 2006.257.23:16:04.43#ibcon#*before write, iclass 5, count 0 2006.257.23:16:04.43#ibcon#enter sib2, iclass 5, count 0 2006.257.23:16:04.43#ibcon#flushed, iclass 5, count 0 2006.257.23:16:04.43#ibcon#about to write, iclass 5, count 0 2006.257.23:16:04.43#ibcon#wrote, iclass 5, count 0 2006.257.23:16:04.43#ibcon#about to read 3, iclass 5, count 0 2006.257.23:16:04.46#ibcon#read 3, iclass 5, count 0 2006.257.23:16:04.46#ibcon#about to read 4, iclass 5, count 0 2006.257.23:16:04.46#ibcon#read 4, iclass 5, count 0 2006.257.23:16:04.46#ibcon#about to read 5, iclass 5, count 0 2006.257.23:16:04.46#ibcon#read 5, iclass 5, count 0 2006.257.23:16:04.46#ibcon#about to read 6, iclass 5, count 0 2006.257.23:16:04.46#ibcon#read 6, iclass 5, count 0 2006.257.23:16:04.46#ibcon#end of sib2, iclass 5, count 0 2006.257.23:16:04.46#ibcon#*after write, iclass 5, count 0 2006.257.23:16:04.46#ibcon#*before return 0, iclass 5, count 0 2006.257.23:16:04.46#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:04.46#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:16:04.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.23:16:04.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.23:16:04.46$vck44/vblo=5,709.99 2006.257.23:16:04.46#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.23:16:04.46#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.23:16:04.46#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:04.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:04.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:04.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:04.46#ibcon#enter wrdev, iclass 7, count 0 2006.257.23:16:04.46#ibcon#first serial, iclass 7, count 0 2006.257.23:16:04.46#ibcon#enter sib2, iclass 7, count 0 2006.257.23:16:04.46#ibcon#flushed, iclass 7, count 0 2006.257.23:16:04.46#ibcon#about to write, iclass 7, count 0 2006.257.23:16:04.46#ibcon#wrote, iclass 7, count 0 2006.257.23:16:04.46#ibcon#about to read 3, iclass 7, count 0 2006.257.23:16:04.48#ibcon#read 3, iclass 7, count 0 2006.257.23:16:04.48#ibcon#about to read 4, iclass 7, count 0 2006.257.23:16:04.48#ibcon#read 4, iclass 7, count 0 2006.257.23:16:04.48#ibcon#about to read 5, iclass 7, count 0 2006.257.23:16:04.48#ibcon#read 5, iclass 7, count 0 2006.257.23:16:04.48#ibcon#about to read 6, iclass 7, count 0 2006.257.23:16:04.48#ibcon#read 6, iclass 7, count 0 2006.257.23:16:04.48#ibcon#end of sib2, iclass 7, count 0 2006.257.23:16:04.48#ibcon#*mode == 0, iclass 7, count 0 2006.257.23:16:04.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.23:16:04.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:16:04.48#ibcon#*before write, iclass 7, count 0 2006.257.23:16:04.48#ibcon#enter sib2, iclass 7, count 0 2006.257.23:16:04.48#ibcon#flushed, iclass 7, count 0 2006.257.23:16:04.48#ibcon#about to write, iclass 7, count 0 2006.257.23:16:04.48#ibcon#wrote, iclass 7, count 0 2006.257.23:16:04.48#ibcon#about to read 3, iclass 7, count 0 2006.257.23:16:04.52#ibcon#read 3, iclass 7, count 0 2006.257.23:16:04.52#ibcon#about to read 4, iclass 7, count 0 2006.257.23:16:04.52#ibcon#read 4, iclass 7, count 0 2006.257.23:16:04.52#ibcon#about to read 5, iclass 7, count 0 2006.257.23:16:04.52#ibcon#read 5, iclass 7, count 0 2006.257.23:16:04.52#ibcon#about to read 6, iclass 7, count 0 2006.257.23:16:04.52#ibcon#read 6, iclass 7, count 0 2006.257.23:16:04.52#ibcon#end of sib2, iclass 7, count 0 2006.257.23:16:04.52#ibcon#*after write, iclass 7, count 0 2006.257.23:16:04.52#ibcon#*before return 0, iclass 7, count 0 2006.257.23:16:04.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:04.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:16:04.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.23:16:04.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.23:16:04.52$vck44/vb=5,4 2006.257.23:16:04.52#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.23:16:04.52#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.23:16:04.52#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:04.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:04.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:04.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:04.58#ibcon#enter wrdev, iclass 11, count 2 2006.257.23:16:04.58#ibcon#first serial, iclass 11, count 2 2006.257.23:16:04.58#ibcon#enter sib2, iclass 11, count 2 2006.257.23:16:04.58#ibcon#flushed, iclass 11, count 2 2006.257.23:16:04.58#ibcon#about to write, iclass 11, count 2 2006.257.23:16:04.58#ibcon#wrote, iclass 11, count 2 2006.257.23:16:04.58#ibcon#about to read 3, iclass 11, count 2 2006.257.23:16:04.60#ibcon#read 3, iclass 11, count 2 2006.257.23:16:04.60#ibcon#about to read 4, iclass 11, count 2 2006.257.23:16:04.60#ibcon#read 4, iclass 11, count 2 2006.257.23:16:04.60#ibcon#about to read 5, iclass 11, count 2 2006.257.23:16:04.60#ibcon#read 5, iclass 11, count 2 2006.257.23:16:04.60#ibcon#about to read 6, iclass 11, count 2 2006.257.23:16:04.60#ibcon#read 6, iclass 11, count 2 2006.257.23:16:04.60#ibcon#end of sib2, iclass 11, count 2 2006.257.23:16:04.60#ibcon#*mode == 0, iclass 11, count 2 2006.257.23:16:04.60#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.23:16:04.60#ibcon#[27=AT05-04\r\n] 2006.257.23:16:04.60#ibcon#*before write, iclass 11, count 2 2006.257.23:16:04.60#ibcon#enter sib2, iclass 11, count 2 2006.257.23:16:04.60#ibcon#flushed, iclass 11, count 2 2006.257.23:16:04.60#ibcon#about to write, iclass 11, count 2 2006.257.23:16:04.60#ibcon#wrote, iclass 11, count 2 2006.257.23:16:04.60#ibcon#about to read 3, iclass 11, count 2 2006.257.23:16:04.63#ibcon#read 3, iclass 11, count 2 2006.257.23:16:04.63#ibcon#about to read 4, iclass 11, count 2 2006.257.23:16:04.63#ibcon#read 4, iclass 11, count 2 2006.257.23:16:04.63#ibcon#about to read 5, iclass 11, count 2 2006.257.23:16:04.63#ibcon#read 5, iclass 11, count 2 2006.257.23:16:04.63#ibcon#about to read 6, iclass 11, count 2 2006.257.23:16:04.63#ibcon#read 6, iclass 11, count 2 2006.257.23:16:04.63#ibcon#end of sib2, iclass 11, count 2 2006.257.23:16:04.63#ibcon#*after write, iclass 11, count 2 2006.257.23:16:04.63#ibcon#*before return 0, iclass 11, count 2 2006.257.23:16:04.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:04.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:16:04.63#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.23:16:04.63#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:04.63#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:04.75#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:04.75#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:04.75#ibcon#enter wrdev, iclass 11, count 0 2006.257.23:16:04.75#ibcon#first serial, iclass 11, count 0 2006.257.23:16:04.75#ibcon#enter sib2, iclass 11, count 0 2006.257.23:16:04.75#ibcon#flushed, iclass 11, count 0 2006.257.23:16:04.75#ibcon#about to write, iclass 11, count 0 2006.257.23:16:04.75#ibcon#wrote, iclass 11, count 0 2006.257.23:16:04.75#ibcon#about to read 3, iclass 11, count 0 2006.257.23:16:04.77#ibcon#read 3, iclass 11, count 0 2006.257.23:16:04.77#ibcon#about to read 4, iclass 11, count 0 2006.257.23:16:04.77#ibcon#read 4, iclass 11, count 0 2006.257.23:16:04.77#ibcon#about to read 5, iclass 11, count 0 2006.257.23:16:04.77#ibcon#read 5, iclass 11, count 0 2006.257.23:16:04.77#ibcon#about to read 6, iclass 11, count 0 2006.257.23:16:04.77#ibcon#read 6, iclass 11, count 0 2006.257.23:16:04.77#ibcon#end of sib2, iclass 11, count 0 2006.257.23:16:04.77#ibcon#*mode == 0, iclass 11, count 0 2006.257.23:16:04.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.23:16:04.77#ibcon#[27=USB\r\n] 2006.257.23:16:04.77#ibcon#*before write, iclass 11, count 0 2006.257.23:16:04.77#ibcon#enter sib2, iclass 11, count 0 2006.257.23:16:04.77#ibcon#flushed, iclass 11, count 0 2006.257.23:16:04.77#ibcon#about to write, iclass 11, count 0 2006.257.23:16:04.77#ibcon#wrote, iclass 11, count 0 2006.257.23:16:04.77#ibcon#about to read 3, iclass 11, count 0 2006.257.23:16:04.80#ibcon#read 3, iclass 11, count 0 2006.257.23:16:04.80#ibcon#about to read 4, iclass 11, count 0 2006.257.23:16:04.80#ibcon#read 4, iclass 11, count 0 2006.257.23:16:04.80#ibcon#about to read 5, iclass 11, count 0 2006.257.23:16:04.80#ibcon#read 5, iclass 11, count 0 2006.257.23:16:04.80#ibcon#about to read 6, iclass 11, count 0 2006.257.23:16:04.80#ibcon#read 6, iclass 11, count 0 2006.257.23:16:04.80#ibcon#end of sib2, iclass 11, count 0 2006.257.23:16:04.80#ibcon#*after write, iclass 11, count 0 2006.257.23:16:04.80#ibcon#*before return 0, iclass 11, count 0 2006.257.23:16:04.80#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:04.80#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:16:04.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.23:16:04.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.23:16:04.80$vck44/vblo=6,719.99 2006.257.23:16:04.80#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.23:16:04.80#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.23:16:04.80#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:04.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:04.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:04.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:04.80#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:16:04.80#ibcon#first serial, iclass 13, count 0 2006.257.23:16:04.80#ibcon#enter sib2, iclass 13, count 0 2006.257.23:16:04.80#ibcon#flushed, iclass 13, count 0 2006.257.23:16:04.80#ibcon#about to write, iclass 13, count 0 2006.257.23:16:04.80#ibcon#wrote, iclass 13, count 0 2006.257.23:16:04.80#ibcon#about to read 3, iclass 13, count 0 2006.257.23:16:04.82#ibcon#read 3, iclass 13, count 0 2006.257.23:16:04.82#ibcon#about to read 4, iclass 13, count 0 2006.257.23:16:04.82#ibcon#read 4, iclass 13, count 0 2006.257.23:16:04.82#ibcon#about to read 5, iclass 13, count 0 2006.257.23:16:04.82#ibcon#read 5, iclass 13, count 0 2006.257.23:16:04.82#ibcon#about to read 6, iclass 13, count 0 2006.257.23:16:04.82#ibcon#read 6, iclass 13, count 0 2006.257.23:16:04.82#ibcon#end of sib2, iclass 13, count 0 2006.257.23:16:04.82#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:16:04.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:16:04.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:16:04.82#ibcon#*before write, iclass 13, count 0 2006.257.23:16:04.82#ibcon#enter sib2, iclass 13, count 0 2006.257.23:16:04.82#ibcon#flushed, iclass 13, count 0 2006.257.23:16:04.82#ibcon#about to write, iclass 13, count 0 2006.257.23:16:04.82#ibcon#wrote, iclass 13, count 0 2006.257.23:16:04.82#ibcon#about to read 3, iclass 13, count 0 2006.257.23:16:04.86#ibcon#read 3, iclass 13, count 0 2006.257.23:16:04.86#ibcon#about to read 4, iclass 13, count 0 2006.257.23:16:04.86#ibcon#read 4, iclass 13, count 0 2006.257.23:16:04.86#ibcon#about to read 5, iclass 13, count 0 2006.257.23:16:04.86#ibcon#read 5, iclass 13, count 0 2006.257.23:16:04.86#ibcon#about to read 6, iclass 13, count 0 2006.257.23:16:04.86#ibcon#read 6, iclass 13, count 0 2006.257.23:16:04.86#ibcon#end of sib2, iclass 13, count 0 2006.257.23:16:04.86#ibcon#*after write, iclass 13, count 0 2006.257.23:16:04.86#ibcon#*before return 0, iclass 13, count 0 2006.257.23:16:04.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:04.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:16:04.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:16:04.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:16:04.86$vck44/vb=6,4 2006.257.23:16:04.86#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.23:16:04.86#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.23:16:04.86#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:04.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:04.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:04.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:04.92#ibcon#enter wrdev, iclass 15, count 2 2006.257.23:16:04.92#ibcon#first serial, iclass 15, count 2 2006.257.23:16:04.92#ibcon#enter sib2, iclass 15, count 2 2006.257.23:16:04.92#ibcon#flushed, iclass 15, count 2 2006.257.23:16:04.92#ibcon#about to write, iclass 15, count 2 2006.257.23:16:04.92#ibcon#wrote, iclass 15, count 2 2006.257.23:16:04.92#ibcon#about to read 3, iclass 15, count 2 2006.257.23:16:04.94#ibcon#read 3, iclass 15, count 2 2006.257.23:16:04.94#ibcon#about to read 4, iclass 15, count 2 2006.257.23:16:04.94#ibcon#read 4, iclass 15, count 2 2006.257.23:16:04.94#ibcon#about to read 5, iclass 15, count 2 2006.257.23:16:04.94#ibcon#read 5, iclass 15, count 2 2006.257.23:16:04.94#ibcon#about to read 6, iclass 15, count 2 2006.257.23:16:04.94#ibcon#read 6, iclass 15, count 2 2006.257.23:16:04.94#ibcon#end of sib2, iclass 15, count 2 2006.257.23:16:04.94#ibcon#*mode == 0, iclass 15, count 2 2006.257.23:16:04.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.23:16:04.94#ibcon#[27=AT06-04\r\n] 2006.257.23:16:04.94#ibcon#*before write, iclass 15, count 2 2006.257.23:16:04.94#ibcon#enter sib2, iclass 15, count 2 2006.257.23:16:04.94#ibcon#flushed, iclass 15, count 2 2006.257.23:16:04.94#ibcon#about to write, iclass 15, count 2 2006.257.23:16:04.94#ibcon#wrote, iclass 15, count 2 2006.257.23:16:04.94#ibcon#about to read 3, iclass 15, count 2 2006.257.23:16:04.97#ibcon#read 3, iclass 15, count 2 2006.257.23:16:04.97#ibcon#about to read 4, iclass 15, count 2 2006.257.23:16:04.97#ibcon#read 4, iclass 15, count 2 2006.257.23:16:04.97#ibcon#about to read 5, iclass 15, count 2 2006.257.23:16:04.97#ibcon#read 5, iclass 15, count 2 2006.257.23:16:04.97#ibcon#about to read 6, iclass 15, count 2 2006.257.23:16:04.97#ibcon#read 6, iclass 15, count 2 2006.257.23:16:04.97#ibcon#end of sib2, iclass 15, count 2 2006.257.23:16:04.97#ibcon#*after write, iclass 15, count 2 2006.257.23:16:04.97#ibcon#*before return 0, iclass 15, count 2 2006.257.23:16:04.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:04.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:16:04.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.23:16:04.97#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:04.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:05.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:05.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:05.09#ibcon#enter wrdev, iclass 15, count 0 2006.257.23:16:05.09#ibcon#first serial, iclass 15, count 0 2006.257.23:16:05.09#ibcon#enter sib2, iclass 15, count 0 2006.257.23:16:05.09#ibcon#flushed, iclass 15, count 0 2006.257.23:16:05.09#ibcon#about to write, iclass 15, count 0 2006.257.23:16:05.09#ibcon#wrote, iclass 15, count 0 2006.257.23:16:05.09#ibcon#about to read 3, iclass 15, count 0 2006.257.23:16:05.11#ibcon#read 3, iclass 15, count 0 2006.257.23:16:05.11#ibcon#about to read 4, iclass 15, count 0 2006.257.23:16:05.11#ibcon#read 4, iclass 15, count 0 2006.257.23:16:05.11#ibcon#about to read 5, iclass 15, count 0 2006.257.23:16:05.11#ibcon#read 5, iclass 15, count 0 2006.257.23:16:05.11#ibcon#about to read 6, iclass 15, count 0 2006.257.23:16:05.11#ibcon#read 6, iclass 15, count 0 2006.257.23:16:05.11#ibcon#end of sib2, iclass 15, count 0 2006.257.23:16:05.11#ibcon#*mode == 0, iclass 15, count 0 2006.257.23:16:05.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.23:16:05.11#ibcon#[27=USB\r\n] 2006.257.23:16:05.11#ibcon#*before write, iclass 15, count 0 2006.257.23:16:05.11#ibcon#enter sib2, iclass 15, count 0 2006.257.23:16:05.11#ibcon#flushed, iclass 15, count 0 2006.257.23:16:05.11#ibcon#about to write, iclass 15, count 0 2006.257.23:16:05.11#ibcon#wrote, iclass 15, count 0 2006.257.23:16:05.11#ibcon#about to read 3, iclass 15, count 0 2006.257.23:16:05.14#ibcon#read 3, iclass 15, count 0 2006.257.23:16:05.14#ibcon#about to read 4, iclass 15, count 0 2006.257.23:16:05.14#ibcon#read 4, iclass 15, count 0 2006.257.23:16:05.14#ibcon#about to read 5, iclass 15, count 0 2006.257.23:16:05.14#ibcon#read 5, iclass 15, count 0 2006.257.23:16:05.14#ibcon#about to read 6, iclass 15, count 0 2006.257.23:16:05.14#ibcon#read 6, iclass 15, count 0 2006.257.23:16:05.14#ibcon#end of sib2, iclass 15, count 0 2006.257.23:16:05.14#ibcon#*after write, iclass 15, count 0 2006.257.23:16:05.14#ibcon#*before return 0, iclass 15, count 0 2006.257.23:16:05.14#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:05.14#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:16:05.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.23:16:05.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.23:16:05.14$vck44/vblo=7,734.99 2006.257.23:16:05.14#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.23:16:05.14#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.23:16:05.14#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:05.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:05.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:05.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:05.14#ibcon#enter wrdev, iclass 17, count 0 2006.257.23:16:05.14#ibcon#first serial, iclass 17, count 0 2006.257.23:16:05.14#ibcon#enter sib2, iclass 17, count 0 2006.257.23:16:05.14#ibcon#flushed, iclass 17, count 0 2006.257.23:16:05.14#ibcon#about to write, iclass 17, count 0 2006.257.23:16:05.14#ibcon#wrote, iclass 17, count 0 2006.257.23:16:05.14#ibcon#about to read 3, iclass 17, count 0 2006.257.23:16:05.16#ibcon#read 3, iclass 17, count 0 2006.257.23:16:05.16#ibcon#about to read 4, iclass 17, count 0 2006.257.23:16:05.16#ibcon#read 4, iclass 17, count 0 2006.257.23:16:05.16#ibcon#about to read 5, iclass 17, count 0 2006.257.23:16:05.16#ibcon#read 5, iclass 17, count 0 2006.257.23:16:05.16#ibcon#about to read 6, iclass 17, count 0 2006.257.23:16:05.16#ibcon#read 6, iclass 17, count 0 2006.257.23:16:05.16#ibcon#end of sib2, iclass 17, count 0 2006.257.23:16:05.16#ibcon#*mode == 0, iclass 17, count 0 2006.257.23:16:05.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.23:16:05.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:16:05.16#ibcon#*before write, iclass 17, count 0 2006.257.23:16:05.16#ibcon#enter sib2, iclass 17, count 0 2006.257.23:16:05.16#ibcon#flushed, iclass 17, count 0 2006.257.23:16:05.16#ibcon#about to write, iclass 17, count 0 2006.257.23:16:05.16#ibcon#wrote, iclass 17, count 0 2006.257.23:16:05.16#ibcon#about to read 3, iclass 17, count 0 2006.257.23:16:05.20#ibcon#read 3, iclass 17, count 0 2006.257.23:16:05.20#ibcon#about to read 4, iclass 17, count 0 2006.257.23:16:05.20#ibcon#read 4, iclass 17, count 0 2006.257.23:16:05.20#ibcon#about to read 5, iclass 17, count 0 2006.257.23:16:05.20#ibcon#read 5, iclass 17, count 0 2006.257.23:16:05.20#ibcon#about to read 6, iclass 17, count 0 2006.257.23:16:05.20#ibcon#read 6, iclass 17, count 0 2006.257.23:16:05.20#ibcon#end of sib2, iclass 17, count 0 2006.257.23:16:05.20#ibcon#*after write, iclass 17, count 0 2006.257.23:16:05.20#ibcon#*before return 0, iclass 17, count 0 2006.257.23:16:05.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:05.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:16:05.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.23:16:05.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.23:16:05.20$vck44/vb=7,4 2006.257.23:16:05.20#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.23:16:05.20#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.23:16:05.20#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:05.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:05.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:05.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:05.26#ibcon#enter wrdev, iclass 19, count 2 2006.257.23:16:05.26#ibcon#first serial, iclass 19, count 2 2006.257.23:16:05.26#ibcon#enter sib2, iclass 19, count 2 2006.257.23:16:05.26#ibcon#flushed, iclass 19, count 2 2006.257.23:16:05.26#ibcon#about to write, iclass 19, count 2 2006.257.23:16:05.26#ibcon#wrote, iclass 19, count 2 2006.257.23:16:05.26#ibcon#about to read 3, iclass 19, count 2 2006.257.23:16:05.28#ibcon#read 3, iclass 19, count 2 2006.257.23:16:05.28#ibcon#about to read 4, iclass 19, count 2 2006.257.23:16:05.28#ibcon#read 4, iclass 19, count 2 2006.257.23:16:05.28#ibcon#about to read 5, iclass 19, count 2 2006.257.23:16:05.28#ibcon#read 5, iclass 19, count 2 2006.257.23:16:05.28#ibcon#about to read 6, iclass 19, count 2 2006.257.23:16:05.28#ibcon#read 6, iclass 19, count 2 2006.257.23:16:05.28#ibcon#end of sib2, iclass 19, count 2 2006.257.23:16:05.28#ibcon#*mode == 0, iclass 19, count 2 2006.257.23:16:05.28#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.23:16:05.28#ibcon#[27=AT07-04\r\n] 2006.257.23:16:05.28#ibcon#*before write, iclass 19, count 2 2006.257.23:16:05.28#ibcon#enter sib2, iclass 19, count 2 2006.257.23:16:05.28#ibcon#flushed, iclass 19, count 2 2006.257.23:16:05.28#ibcon#about to write, iclass 19, count 2 2006.257.23:16:05.28#ibcon#wrote, iclass 19, count 2 2006.257.23:16:05.28#ibcon#about to read 3, iclass 19, count 2 2006.257.23:16:05.31#ibcon#read 3, iclass 19, count 2 2006.257.23:16:05.31#ibcon#about to read 4, iclass 19, count 2 2006.257.23:16:05.31#ibcon#read 4, iclass 19, count 2 2006.257.23:16:05.31#ibcon#about to read 5, iclass 19, count 2 2006.257.23:16:05.31#ibcon#read 5, iclass 19, count 2 2006.257.23:16:05.31#ibcon#about to read 6, iclass 19, count 2 2006.257.23:16:05.31#ibcon#read 6, iclass 19, count 2 2006.257.23:16:05.31#ibcon#end of sib2, iclass 19, count 2 2006.257.23:16:05.31#ibcon#*after write, iclass 19, count 2 2006.257.23:16:05.31#ibcon#*before return 0, iclass 19, count 2 2006.257.23:16:05.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:05.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:16:05.31#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.23:16:05.31#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:05.31#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:05.43#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:05.43#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:05.43#ibcon#enter wrdev, iclass 19, count 0 2006.257.23:16:05.43#ibcon#first serial, iclass 19, count 0 2006.257.23:16:05.43#ibcon#enter sib2, iclass 19, count 0 2006.257.23:16:05.43#ibcon#flushed, iclass 19, count 0 2006.257.23:16:05.43#ibcon#about to write, iclass 19, count 0 2006.257.23:16:05.43#ibcon#wrote, iclass 19, count 0 2006.257.23:16:05.43#ibcon#about to read 3, iclass 19, count 0 2006.257.23:16:05.45#ibcon#read 3, iclass 19, count 0 2006.257.23:16:05.45#ibcon#about to read 4, iclass 19, count 0 2006.257.23:16:05.45#ibcon#read 4, iclass 19, count 0 2006.257.23:16:05.45#ibcon#about to read 5, iclass 19, count 0 2006.257.23:16:05.45#ibcon#read 5, iclass 19, count 0 2006.257.23:16:05.45#ibcon#about to read 6, iclass 19, count 0 2006.257.23:16:05.45#ibcon#read 6, iclass 19, count 0 2006.257.23:16:05.45#ibcon#end of sib2, iclass 19, count 0 2006.257.23:16:05.45#ibcon#*mode == 0, iclass 19, count 0 2006.257.23:16:05.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.23:16:05.45#ibcon#[27=USB\r\n] 2006.257.23:16:05.45#ibcon#*before write, iclass 19, count 0 2006.257.23:16:05.45#ibcon#enter sib2, iclass 19, count 0 2006.257.23:16:05.45#ibcon#flushed, iclass 19, count 0 2006.257.23:16:05.45#ibcon#about to write, iclass 19, count 0 2006.257.23:16:05.45#ibcon#wrote, iclass 19, count 0 2006.257.23:16:05.45#ibcon#about to read 3, iclass 19, count 0 2006.257.23:16:05.48#ibcon#read 3, iclass 19, count 0 2006.257.23:16:05.48#ibcon#about to read 4, iclass 19, count 0 2006.257.23:16:05.48#ibcon#read 4, iclass 19, count 0 2006.257.23:16:05.48#ibcon#about to read 5, iclass 19, count 0 2006.257.23:16:05.48#ibcon#read 5, iclass 19, count 0 2006.257.23:16:05.48#ibcon#about to read 6, iclass 19, count 0 2006.257.23:16:05.48#ibcon#read 6, iclass 19, count 0 2006.257.23:16:05.48#ibcon#end of sib2, iclass 19, count 0 2006.257.23:16:05.48#ibcon#*after write, iclass 19, count 0 2006.257.23:16:05.48#ibcon#*before return 0, iclass 19, count 0 2006.257.23:16:05.48#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:05.48#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:16:05.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.23:16:05.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.23:16:05.48$vck44/vblo=8,744.99 2006.257.23:16:05.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.23:16:05.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.23:16:05.48#ibcon#ireg 17 cls_cnt 0 2006.257.23:16:05.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:05.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:05.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:05.48#ibcon#enter wrdev, iclass 21, count 0 2006.257.23:16:05.48#ibcon#first serial, iclass 21, count 0 2006.257.23:16:05.48#ibcon#enter sib2, iclass 21, count 0 2006.257.23:16:05.48#ibcon#flushed, iclass 21, count 0 2006.257.23:16:05.48#ibcon#about to write, iclass 21, count 0 2006.257.23:16:05.48#ibcon#wrote, iclass 21, count 0 2006.257.23:16:05.48#ibcon#about to read 3, iclass 21, count 0 2006.257.23:16:05.50#ibcon#read 3, iclass 21, count 0 2006.257.23:16:05.50#ibcon#about to read 4, iclass 21, count 0 2006.257.23:16:05.50#ibcon#read 4, iclass 21, count 0 2006.257.23:16:05.50#ibcon#about to read 5, iclass 21, count 0 2006.257.23:16:05.50#ibcon#read 5, iclass 21, count 0 2006.257.23:16:05.50#ibcon#about to read 6, iclass 21, count 0 2006.257.23:16:05.50#ibcon#read 6, iclass 21, count 0 2006.257.23:16:05.50#ibcon#end of sib2, iclass 21, count 0 2006.257.23:16:05.50#ibcon#*mode == 0, iclass 21, count 0 2006.257.23:16:05.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.23:16:05.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:16:05.50#ibcon#*before write, iclass 21, count 0 2006.257.23:16:05.50#ibcon#enter sib2, iclass 21, count 0 2006.257.23:16:05.50#ibcon#flushed, iclass 21, count 0 2006.257.23:16:05.50#ibcon#about to write, iclass 21, count 0 2006.257.23:16:05.50#ibcon#wrote, iclass 21, count 0 2006.257.23:16:05.50#ibcon#about to read 3, iclass 21, count 0 2006.257.23:16:05.54#ibcon#read 3, iclass 21, count 0 2006.257.23:16:05.54#ibcon#about to read 4, iclass 21, count 0 2006.257.23:16:05.54#ibcon#read 4, iclass 21, count 0 2006.257.23:16:05.54#ibcon#about to read 5, iclass 21, count 0 2006.257.23:16:05.54#ibcon#read 5, iclass 21, count 0 2006.257.23:16:05.54#ibcon#about to read 6, iclass 21, count 0 2006.257.23:16:05.54#ibcon#read 6, iclass 21, count 0 2006.257.23:16:05.54#ibcon#end of sib2, iclass 21, count 0 2006.257.23:16:05.54#ibcon#*after write, iclass 21, count 0 2006.257.23:16:05.54#ibcon#*before return 0, iclass 21, count 0 2006.257.23:16:05.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:05.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:16:05.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.23:16:05.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.23:16:05.54$vck44/vb=8,4 2006.257.23:16:05.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.23:16:05.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.23:16:05.54#ibcon#ireg 11 cls_cnt 2 2006.257.23:16:05.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:05.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:05.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:05.60#ibcon#enter wrdev, iclass 23, count 2 2006.257.23:16:05.60#ibcon#first serial, iclass 23, count 2 2006.257.23:16:05.60#ibcon#enter sib2, iclass 23, count 2 2006.257.23:16:05.60#ibcon#flushed, iclass 23, count 2 2006.257.23:16:05.60#ibcon#about to write, iclass 23, count 2 2006.257.23:16:05.60#ibcon#wrote, iclass 23, count 2 2006.257.23:16:05.60#ibcon#about to read 3, iclass 23, count 2 2006.257.23:16:05.62#ibcon#read 3, iclass 23, count 2 2006.257.23:16:05.62#ibcon#about to read 4, iclass 23, count 2 2006.257.23:16:05.62#ibcon#read 4, iclass 23, count 2 2006.257.23:16:05.62#ibcon#about to read 5, iclass 23, count 2 2006.257.23:16:05.62#ibcon#read 5, iclass 23, count 2 2006.257.23:16:05.62#ibcon#about to read 6, iclass 23, count 2 2006.257.23:16:05.62#ibcon#read 6, iclass 23, count 2 2006.257.23:16:05.62#ibcon#end of sib2, iclass 23, count 2 2006.257.23:16:05.62#ibcon#*mode == 0, iclass 23, count 2 2006.257.23:16:05.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.23:16:05.62#ibcon#[27=AT08-04\r\n] 2006.257.23:16:05.62#ibcon#*before write, iclass 23, count 2 2006.257.23:16:05.62#ibcon#enter sib2, iclass 23, count 2 2006.257.23:16:05.62#ibcon#flushed, iclass 23, count 2 2006.257.23:16:05.62#ibcon#about to write, iclass 23, count 2 2006.257.23:16:05.62#ibcon#wrote, iclass 23, count 2 2006.257.23:16:05.62#ibcon#about to read 3, iclass 23, count 2 2006.257.23:16:05.65#ibcon#read 3, iclass 23, count 2 2006.257.23:16:05.65#ibcon#about to read 4, iclass 23, count 2 2006.257.23:16:05.65#ibcon#read 4, iclass 23, count 2 2006.257.23:16:05.65#ibcon#about to read 5, iclass 23, count 2 2006.257.23:16:05.65#ibcon#read 5, iclass 23, count 2 2006.257.23:16:05.65#ibcon#about to read 6, iclass 23, count 2 2006.257.23:16:05.65#ibcon#read 6, iclass 23, count 2 2006.257.23:16:05.65#ibcon#end of sib2, iclass 23, count 2 2006.257.23:16:05.65#ibcon#*after write, iclass 23, count 2 2006.257.23:16:05.65#ibcon#*before return 0, iclass 23, count 2 2006.257.23:16:05.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:05.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:16:05.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.23:16:05.65#ibcon#ireg 7 cls_cnt 0 2006.257.23:16:05.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:05.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:05.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:05.77#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:16:05.77#ibcon#first serial, iclass 23, count 0 2006.257.23:16:05.77#ibcon#enter sib2, iclass 23, count 0 2006.257.23:16:05.77#ibcon#flushed, iclass 23, count 0 2006.257.23:16:05.77#ibcon#about to write, iclass 23, count 0 2006.257.23:16:05.77#ibcon#wrote, iclass 23, count 0 2006.257.23:16:05.77#ibcon#about to read 3, iclass 23, count 0 2006.257.23:16:05.79#ibcon#read 3, iclass 23, count 0 2006.257.23:16:05.79#ibcon#about to read 4, iclass 23, count 0 2006.257.23:16:05.79#ibcon#read 4, iclass 23, count 0 2006.257.23:16:05.79#ibcon#about to read 5, iclass 23, count 0 2006.257.23:16:05.79#ibcon#read 5, iclass 23, count 0 2006.257.23:16:05.79#ibcon#about to read 6, iclass 23, count 0 2006.257.23:16:05.79#ibcon#read 6, iclass 23, count 0 2006.257.23:16:05.79#ibcon#end of sib2, iclass 23, count 0 2006.257.23:16:05.79#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:16:05.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:16:05.79#ibcon#[27=USB\r\n] 2006.257.23:16:05.79#ibcon#*before write, iclass 23, count 0 2006.257.23:16:05.79#ibcon#enter sib2, iclass 23, count 0 2006.257.23:16:05.79#ibcon#flushed, iclass 23, count 0 2006.257.23:16:05.79#ibcon#about to write, iclass 23, count 0 2006.257.23:16:05.79#ibcon#wrote, iclass 23, count 0 2006.257.23:16:05.79#ibcon#about to read 3, iclass 23, count 0 2006.257.23:16:05.82#ibcon#read 3, iclass 23, count 0 2006.257.23:16:05.82#ibcon#about to read 4, iclass 23, count 0 2006.257.23:16:05.82#ibcon#read 4, iclass 23, count 0 2006.257.23:16:05.82#ibcon#about to read 5, iclass 23, count 0 2006.257.23:16:05.82#ibcon#read 5, iclass 23, count 0 2006.257.23:16:05.82#ibcon#about to read 6, iclass 23, count 0 2006.257.23:16:05.82#ibcon#read 6, iclass 23, count 0 2006.257.23:16:05.82#ibcon#end of sib2, iclass 23, count 0 2006.257.23:16:05.82#ibcon#*after write, iclass 23, count 0 2006.257.23:16:05.82#ibcon#*before return 0, iclass 23, count 0 2006.257.23:16:05.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:05.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:16:05.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:16:05.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:16:05.82$vck44/vabw=wide 2006.257.23:16:05.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.23:16:05.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.23:16:05.82#ibcon#ireg 8 cls_cnt 0 2006.257.23:16:05.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:05.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:05.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:05.82#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:16:05.82#ibcon#first serial, iclass 25, count 0 2006.257.23:16:05.82#ibcon#enter sib2, iclass 25, count 0 2006.257.23:16:05.82#ibcon#flushed, iclass 25, count 0 2006.257.23:16:05.82#ibcon#about to write, iclass 25, count 0 2006.257.23:16:05.82#ibcon#wrote, iclass 25, count 0 2006.257.23:16:05.82#ibcon#about to read 3, iclass 25, count 0 2006.257.23:16:05.84#ibcon#read 3, iclass 25, count 0 2006.257.23:16:05.84#ibcon#about to read 4, iclass 25, count 0 2006.257.23:16:05.84#ibcon#read 4, iclass 25, count 0 2006.257.23:16:05.84#ibcon#about to read 5, iclass 25, count 0 2006.257.23:16:05.84#ibcon#read 5, iclass 25, count 0 2006.257.23:16:05.84#ibcon#about to read 6, iclass 25, count 0 2006.257.23:16:05.84#ibcon#read 6, iclass 25, count 0 2006.257.23:16:05.84#ibcon#end of sib2, iclass 25, count 0 2006.257.23:16:05.84#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:16:05.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:16:05.84#ibcon#[25=BW32\r\n] 2006.257.23:16:05.84#ibcon#*before write, iclass 25, count 0 2006.257.23:16:05.84#ibcon#enter sib2, iclass 25, count 0 2006.257.23:16:05.84#ibcon#flushed, iclass 25, count 0 2006.257.23:16:05.84#ibcon#about to write, iclass 25, count 0 2006.257.23:16:05.84#ibcon#wrote, iclass 25, count 0 2006.257.23:16:05.84#ibcon#about to read 3, iclass 25, count 0 2006.257.23:16:05.87#ibcon#read 3, iclass 25, count 0 2006.257.23:16:05.87#ibcon#about to read 4, iclass 25, count 0 2006.257.23:16:05.87#ibcon#read 4, iclass 25, count 0 2006.257.23:16:05.87#ibcon#about to read 5, iclass 25, count 0 2006.257.23:16:05.87#ibcon#read 5, iclass 25, count 0 2006.257.23:16:05.87#ibcon#about to read 6, iclass 25, count 0 2006.257.23:16:05.87#ibcon#read 6, iclass 25, count 0 2006.257.23:16:05.87#ibcon#end of sib2, iclass 25, count 0 2006.257.23:16:05.87#ibcon#*after write, iclass 25, count 0 2006.257.23:16:05.87#ibcon#*before return 0, iclass 25, count 0 2006.257.23:16:05.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:05.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:16:05.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:16:05.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:16:05.87$vck44/vbbw=wide 2006.257.23:16:05.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.23:16:05.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.23:16:05.87#ibcon#ireg 8 cls_cnt 0 2006.257.23:16:05.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:16:05.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:16:05.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:16:05.94#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:16:05.94#ibcon#first serial, iclass 27, count 0 2006.257.23:16:05.94#ibcon#enter sib2, iclass 27, count 0 2006.257.23:16:05.94#ibcon#flushed, iclass 27, count 0 2006.257.23:16:05.94#ibcon#about to write, iclass 27, count 0 2006.257.23:16:05.94#ibcon#wrote, iclass 27, count 0 2006.257.23:16:05.94#ibcon#about to read 3, iclass 27, count 0 2006.257.23:16:05.96#ibcon#read 3, iclass 27, count 0 2006.257.23:16:05.96#ibcon#about to read 4, iclass 27, count 0 2006.257.23:16:05.96#ibcon#read 4, iclass 27, count 0 2006.257.23:16:05.96#ibcon#about to read 5, iclass 27, count 0 2006.257.23:16:05.96#ibcon#read 5, iclass 27, count 0 2006.257.23:16:05.96#ibcon#about to read 6, iclass 27, count 0 2006.257.23:16:05.96#ibcon#read 6, iclass 27, count 0 2006.257.23:16:05.96#ibcon#end of sib2, iclass 27, count 0 2006.257.23:16:05.96#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:16:05.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:16:05.96#ibcon#[27=BW32\r\n] 2006.257.23:16:05.96#ibcon#*before write, iclass 27, count 0 2006.257.23:16:05.96#ibcon#enter sib2, iclass 27, count 0 2006.257.23:16:05.96#ibcon#flushed, iclass 27, count 0 2006.257.23:16:05.96#ibcon#about to write, iclass 27, count 0 2006.257.23:16:05.96#ibcon#wrote, iclass 27, count 0 2006.257.23:16:05.96#ibcon#about to read 3, iclass 27, count 0 2006.257.23:16:05.99#ibcon#read 3, iclass 27, count 0 2006.257.23:16:05.99#ibcon#about to read 4, iclass 27, count 0 2006.257.23:16:05.99#ibcon#read 4, iclass 27, count 0 2006.257.23:16:05.99#ibcon#about to read 5, iclass 27, count 0 2006.257.23:16:05.99#ibcon#read 5, iclass 27, count 0 2006.257.23:16:05.99#ibcon#about to read 6, iclass 27, count 0 2006.257.23:16:05.99#ibcon#read 6, iclass 27, count 0 2006.257.23:16:05.99#ibcon#end of sib2, iclass 27, count 0 2006.257.23:16:05.99#ibcon#*after write, iclass 27, count 0 2006.257.23:16:05.99#ibcon#*before return 0, iclass 27, count 0 2006.257.23:16:05.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:16:05.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:16:05.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:16:05.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:16:05.99$setupk4/ifdk4 2006.257.23:16:05.99$ifdk4/lo= 2006.257.23:16:05.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:16:05.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:16:05.99$ifdk4/patch= 2006.257.23:16:05.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:16:05.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:16:05.99$setupk4/!*+20s 2006.257.23:16:10.29#abcon#<5=/15 1.1 3.0 20.50 801016.1\r\n> 2006.257.23:16:10.31#abcon#{5=INTERFACE CLEAR} 2006.257.23:16:10.37#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:16:20.46#abcon#<5=/15 1.1 3.0 20.50 801016.1\r\n> 2006.257.23:16:20.48#abcon#{5=INTERFACE CLEAR} 2006.257.23:16:20.50$setupk4/"tpicd 2006.257.23:16:20.50$setupk4/echo=off 2006.257.23:16:20.50$setupk4/xlog=off 2006.257.23:16:20.50:!2006.257.23:19:07 2006.257.23:17:04.13#trakl#Source acquired 2006.257.23:17:06.13#flagr#flagr/antenna,acquired 2006.257.23:19:07.00:preob 2006.257.23:19:07.14/onsource/TRACKING 2006.257.23:19:07.14:!2006.257.23:19:17 2006.257.23:19:17.00:"tape 2006.257.23:19:17.00:"st=record 2006.257.23:19:17.00:data_valid=on 2006.257.23:19:17.00:midob 2006.257.23:19:18.14/onsource/TRACKING 2006.257.23:19:18.14/wx/20.54,1016.1,82 2006.257.23:19:18.28/cable/+6.4840E-03 2006.257.23:19:19.37/va/01,08,usb,yes,30,32 2006.257.23:19:19.37/va/02,07,usb,yes,33,33 2006.257.23:19:19.37/va/03,08,usb,yes,29,31 2006.257.23:19:19.37/va/04,07,usb,yes,33,35 2006.257.23:19:19.37/va/05,04,usb,yes,30,30 2006.257.23:19:19.37/va/06,04,usb,yes,33,33 2006.257.23:19:19.37/va/07,04,usb,yes,34,35 2006.257.23:19:19.37/va/08,04,usb,yes,28,35 2006.257.23:19:19.60/valo/01,524.99,yes,locked 2006.257.23:19:19.60/valo/02,534.99,yes,locked 2006.257.23:19:19.60/valo/03,564.99,yes,locked 2006.257.23:19:19.60/valo/04,624.99,yes,locked 2006.257.23:19:19.60/valo/05,734.99,yes,locked 2006.257.23:19:19.60/valo/06,814.99,yes,locked 2006.257.23:19:19.60/valo/07,864.99,yes,locked 2006.257.23:19:19.60/valo/08,884.99,yes,locked 2006.257.23:19:20.69/vb/01,04,usb,yes,30,28 2006.257.23:19:20.69/vb/02,05,usb,yes,29,28 2006.257.23:19:20.69/vb/03,04,usb,yes,29,32 2006.257.23:19:20.69/vb/04,05,usb,yes,30,29 2006.257.23:19:20.69/vb/05,04,usb,yes,26,29 2006.257.23:19:20.69/vb/06,04,usb,yes,31,27 2006.257.23:19:20.69/vb/07,04,usb,yes,30,30 2006.257.23:19:20.69/vb/08,04,usb,yes,28,31 2006.257.23:19:20.92/vblo/01,629.99,yes,locked 2006.257.23:19:20.92/vblo/02,634.99,yes,locked 2006.257.23:19:20.92/vblo/03,649.99,yes,locked 2006.257.23:19:20.92/vblo/04,679.99,yes,locked 2006.257.23:19:20.92/vblo/05,709.99,yes,locked 2006.257.23:19:20.92/vblo/06,719.99,yes,locked 2006.257.23:19:20.92/vblo/07,734.99,yes,locked 2006.257.23:19:20.92/vblo/08,744.99,yes,locked 2006.257.23:19:21.07/vabw/8 2006.257.23:19:21.22/vbbw/8 2006.257.23:19:21.31/xfe/off,on,15.2 2006.257.23:19:21.69/ifatt/23,28,28,28 2006.257.23:19:22.08/fmout-gps/S +4.52E-07 2006.257.23:19:22.12:!2006.257.23:20:07 2006.257.23:20:07.01:data_valid=off 2006.257.23:20:07.01:"et 2006.257.23:20:07.01:!+3s 2006.257.23:20:10.02:"tape 2006.257.23:20:10.02:postob 2006.257.23:20:10.16/cable/+6.4839E-03 2006.257.23:20:10.16/wx/20.55,1016.1,82 2006.257.23:20:11.08/fmout-gps/S +4.52E-07 2006.257.23:20:11.08:scan_name=257-2322,jd0609,210 2006.257.23:20:11.08:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.257.23:20:12.14#flagr#flagr/antenna,new-source 2006.257.23:20:12.14:checkk5 2006.257.23:20:12.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:20:12.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:20:13.15/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:20:13.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:20:13.83/chk_obsdata//k5ts1/T2572319??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.23:20:14.17/chk_obsdata//k5ts2/T2572319??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.23:20:14.50/chk_obsdata//k5ts3/T2572319??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.23:20:14.83/chk_obsdata//k5ts4/T2572319??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.257.23:20:15.49/k5log//k5ts1_log_newline 2006.257.23:20:16.15/k5log//k5ts2_log_newline 2006.257.23:20:16.80/k5log//k5ts3_log_newline 2006.257.23:20:17.47/k5log//k5ts4_log_newline 2006.257.23:20:17.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:20:17.49:setupk4=1 2006.257.23:20:17.49$setupk4/echo=on 2006.257.23:20:17.49$setupk4/pcalon 2006.257.23:20:17.49$pcalon/"no phase cal control is implemented here 2006.257.23:20:17.49$setupk4/"tpicd=stop 2006.257.23:20:17.49$setupk4/"rec=synch_on 2006.257.23:20:17.49$setupk4/"rec_mode=128 2006.257.23:20:17.49$setupk4/!* 2006.257.23:20:17.49$setupk4/recpk4 2006.257.23:20:17.49$recpk4/recpatch= 2006.257.23:20:17.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:20:17.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:20:17.50$setupk4/vck44 2006.257.23:20:17.50$vck44/valo=1,524.99 2006.257.23:20:17.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.23:20:17.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.23:20:17.50#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:17.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:17.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:17.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:17.50#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:20:17.50#ibcon#first serial, iclass 24, count 0 2006.257.23:20:17.50#ibcon#enter sib2, iclass 24, count 0 2006.257.23:20:17.50#ibcon#flushed, iclass 24, count 0 2006.257.23:20:17.50#ibcon#about to write, iclass 24, count 0 2006.257.23:20:17.50#ibcon#wrote, iclass 24, count 0 2006.257.23:20:17.50#ibcon#about to read 3, iclass 24, count 0 2006.257.23:20:17.52#ibcon#read 3, iclass 24, count 0 2006.257.23:20:17.52#ibcon#about to read 4, iclass 24, count 0 2006.257.23:20:17.52#ibcon#read 4, iclass 24, count 0 2006.257.23:20:17.52#ibcon#about to read 5, iclass 24, count 0 2006.257.23:20:17.52#ibcon#read 5, iclass 24, count 0 2006.257.23:20:17.52#ibcon#about to read 6, iclass 24, count 0 2006.257.23:20:17.52#ibcon#read 6, iclass 24, count 0 2006.257.23:20:17.52#ibcon#end of sib2, iclass 24, count 0 2006.257.23:20:17.52#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:20:17.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:20:17.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:20:17.52#ibcon#*before write, iclass 24, count 0 2006.257.23:20:17.52#ibcon#enter sib2, iclass 24, count 0 2006.257.23:20:17.52#ibcon#flushed, iclass 24, count 0 2006.257.23:20:17.52#ibcon#about to write, iclass 24, count 0 2006.257.23:20:17.52#ibcon#wrote, iclass 24, count 0 2006.257.23:20:17.52#ibcon#about to read 3, iclass 24, count 0 2006.257.23:20:17.57#ibcon#read 3, iclass 24, count 0 2006.257.23:20:17.57#ibcon#about to read 4, iclass 24, count 0 2006.257.23:20:17.57#ibcon#read 4, iclass 24, count 0 2006.257.23:20:17.57#ibcon#about to read 5, iclass 24, count 0 2006.257.23:20:17.57#ibcon#read 5, iclass 24, count 0 2006.257.23:20:17.57#ibcon#about to read 6, iclass 24, count 0 2006.257.23:20:17.57#ibcon#read 6, iclass 24, count 0 2006.257.23:20:17.57#ibcon#end of sib2, iclass 24, count 0 2006.257.23:20:17.57#ibcon#*after write, iclass 24, count 0 2006.257.23:20:17.57#ibcon#*before return 0, iclass 24, count 0 2006.257.23:20:17.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:17.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:17.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:20:17.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:20:17.57$vck44/va=1,8 2006.257.23:20:17.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.23:20:17.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.23:20:17.57#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:17.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:17.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:17.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:17.57#ibcon#enter wrdev, iclass 26, count 2 2006.257.23:20:17.57#ibcon#first serial, iclass 26, count 2 2006.257.23:20:17.57#ibcon#enter sib2, iclass 26, count 2 2006.257.23:20:17.57#ibcon#flushed, iclass 26, count 2 2006.257.23:20:17.57#ibcon#about to write, iclass 26, count 2 2006.257.23:20:17.57#ibcon#wrote, iclass 26, count 2 2006.257.23:20:17.57#ibcon#about to read 3, iclass 26, count 2 2006.257.23:20:17.59#ibcon#read 3, iclass 26, count 2 2006.257.23:20:17.59#ibcon#about to read 4, iclass 26, count 2 2006.257.23:20:17.59#ibcon#read 4, iclass 26, count 2 2006.257.23:20:17.59#ibcon#about to read 5, iclass 26, count 2 2006.257.23:20:17.59#ibcon#read 5, iclass 26, count 2 2006.257.23:20:17.59#ibcon#about to read 6, iclass 26, count 2 2006.257.23:20:17.59#ibcon#read 6, iclass 26, count 2 2006.257.23:20:17.59#ibcon#end of sib2, iclass 26, count 2 2006.257.23:20:17.59#ibcon#*mode == 0, iclass 26, count 2 2006.257.23:20:17.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.23:20:17.59#ibcon#[25=AT01-08\r\n] 2006.257.23:20:17.59#ibcon#*before write, iclass 26, count 2 2006.257.23:20:17.59#ibcon#enter sib2, iclass 26, count 2 2006.257.23:20:17.59#ibcon#flushed, iclass 26, count 2 2006.257.23:20:17.59#ibcon#about to write, iclass 26, count 2 2006.257.23:20:17.59#ibcon#wrote, iclass 26, count 2 2006.257.23:20:17.59#ibcon#about to read 3, iclass 26, count 2 2006.257.23:20:17.62#ibcon#read 3, iclass 26, count 2 2006.257.23:20:17.62#ibcon#about to read 4, iclass 26, count 2 2006.257.23:20:17.62#ibcon#read 4, iclass 26, count 2 2006.257.23:20:17.62#ibcon#about to read 5, iclass 26, count 2 2006.257.23:20:17.62#ibcon#read 5, iclass 26, count 2 2006.257.23:20:17.62#ibcon#about to read 6, iclass 26, count 2 2006.257.23:20:17.62#ibcon#read 6, iclass 26, count 2 2006.257.23:20:17.62#ibcon#end of sib2, iclass 26, count 2 2006.257.23:20:17.62#ibcon#*after write, iclass 26, count 2 2006.257.23:20:17.62#ibcon#*before return 0, iclass 26, count 2 2006.257.23:20:17.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:17.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:17.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.23:20:17.62#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:17.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:17.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:17.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:17.74#ibcon#enter wrdev, iclass 26, count 0 2006.257.23:20:17.74#ibcon#first serial, iclass 26, count 0 2006.257.23:20:17.74#ibcon#enter sib2, iclass 26, count 0 2006.257.23:20:17.74#ibcon#flushed, iclass 26, count 0 2006.257.23:20:17.74#ibcon#about to write, iclass 26, count 0 2006.257.23:20:17.74#ibcon#wrote, iclass 26, count 0 2006.257.23:20:17.74#ibcon#about to read 3, iclass 26, count 0 2006.257.23:20:17.76#ibcon#read 3, iclass 26, count 0 2006.257.23:20:17.76#ibcon#about to read 4, iclass 26, count 0 2006.257.23:20:17.76#ibcon#read 4, iclass 26, count 0 2006.257.23:20:17.76#ibcon#about to read 5, iclass 26, count 0 2006.257.23:20:17.76#ibcon#read 5, iclass 26, count 0 2006.257.23:20:17.76#ibcon#about to read 6, iclass 26, count 0 2006.257.23:20:17.76#ibcon#read 6, iclass 26, count 0 2006.257.23:20:17.76#ibcon#end of sib2, iclass 26, count 0 2006.257.23:20:17.76#ibcon#*mode == 0, iclass 26, count 0 2006.257.23:20:17.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.23:20:17.76#ibcon#[25=USB\r\n] 2006.257.23:20:17.76#ibcon#*before write, iclass 26, count 0 2006.257.23:20:17.76#ibcon#enter sib2, iclass 26, count 0 2006.257.23:20:17.76#ibcon#flushed, iclass 26, count 0 2006.257.23:20:17.76#ibcon#about to write, iclass 26, count 0 2006.257.23:20:17.76#ibcon#wrote, iclass 26, count 0 2006.257.23:20:17.76#ibcon#about to read 3, iclass 26, count 0 2006.257.23:20:17.79#ibcon#read 3, iclass 26, count 0 2006.257.23:20:17.79#ibcon#about to read 4, iclass 26, count 0 2006.257.23:20:17.79#ibcon#read 4, iclass 26, count 0 2006.257.23:20:17.79#ibcon#about to read 5, iclass 26, count 0 2006.257.23:20:17.79#ibcon#read 5, iclass 26, count 0 2006.257.23:20:17.79#ibcon#about to read 6, iclass 26, count 0 2006.257.23:20:17.79#ibcon#read 6, iclass 26, count 0 2006.257.23:20:17.79#ibcon#end of sib2, iclass 26, count 0 2006.257.23:20:17.79#ibcon#*after write, iclass 26, count 0 2006.257.23:20:17.79#ibcon#*before return 0, iclass 26, count 0 2006.257.23:20:17.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:17.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:17.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.23:20:17.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.23:20:17.79$vck44/valo=2,534.99 2006.257.23:20:17.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.23:20:17.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.23:20:17.79#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:17.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:17.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:17.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:17.79#ibcon#enter wrdev, iclass 28, count 0 2006.257.23:20:17.79#ibcon#first serial, iclass 28, count 0 2006.257.23:20:17.79#ibcon#enter sib2, iclass 28, count 0 2006.257.23:20:17.79#ibcon#flushed, iclass 28, count 0 2006.257.23:20:17.79#ibcon#about to write, iclass 28, count 0 2006.257.23:20:17.79#ibcon#wrote, iclass 28, count 0 2006.257.23:20:17.79#ibcon#about to read 3, iclass 28, count 0 2006.257.23:20:17.81#ibcon#read 3, iclass 28, count 0 2006.257.23:20:17.81#ibcon#about to read 4, iclass 28, count 0 2006.257.23:20:17.81#ibcon#read 4, iclass 28, count 0 2006.257.23:20:17.81#ibcon#about to read 5, iclass 28, count 0 2006.257.23:20:17.81#ibcon#read 5, iclass 28, count 0 2006.257.23:20:17.81#ibcon#about to read 6, iclass 28, count 0 2006.257.23:20:17.81#ibcon#read 6, iclass 28, count 0 2006.257.23:20:17.81#ibcon#end of sib2, iclass 28, count 0 2006.257.23:20:17.81#ibcon#*mode == 0, iclass 28, count 0 2006.257.23:20:17.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.23:20:17.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:20:17.81#ibcon#*before write, iclass 28, count 0 2006.257.23:20:17.81#ibcon#enter sib2, iclass 28, count 0 2006.257.23:20:17.81#ibcon#flushed, iclass 28, count 0 2006.257.23:20:17.81#ibcon#about to write, iclass 28, count 0 2006.257.23:20:17.81#ibcon#wrote, iclass 28, count 0 2006.257.23:20:17.81#ibcon#about to read 3, iclass 28, count 0 2006.257.23:20:17.85#ibcon#read 3, iclass 28, count 0 2006.257.23:20:17.85#ibcon#about to read 4, iclass 28, count 0 2006.257.23:20:17.85#ibcon#read 4, iclass 28, count 0 2006.257.23:20:17.85#ibcon#about to read 5, iclass 28, count 0 2006.257.23:20:17.85#ibcon#read 5, iclass 28, count 0 2006.257.23:20:17.85#ibcon#about to read 6, iclass 28, count 0 2006.257.23:20:17.85#ibcon#read 6, iclass 28, count 0 2006.257.23:20:17.85#ibcon#end of sib2, iclass 28, count 0 2006.257.23:20:17.85#ibcon#*after write, iclass 28, count 0 2006.257.23:20:17.85#ibcon#*before return 0, iclass 28, count 0 2006.257.23:20:17.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:17.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:17.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.23:20:17.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.23:20:17.85$vck44/va=2,7 2006.257.23:20:17.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.23:20:17.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.23:20:17.85#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:17.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:17.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:17.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:17.91#ibcon#enter wrdev, iclass 30, count 2 2006.257.23:20:17.91#ibcon#first serial, iclass 30, count 2 2006.257.23:20:17.91#ibcon#enter sib2, iclass 30, count 2 2006.257.23:20:17.91#ibcon#flushed, iclass 30, count 2 2006.257.23:20:17.91#ibcon#about to write, iclass 30, count 2 2006.257.23:20:17.91#ibcon#wrote, iclass 30, count 2 2006.257.23:20:17.91#ibcon#about to read 3, iclass 30, count 2 2006.257.23:20:17.93#ibcon#read 3, iclass 30, count 2 2006.257.23:20:17.93#ibcon#about to read 4, iclass 30, count 2 2006.257.23:20:17.93#ibcon#read 4, iclass 30, count 2 2006.257.23:20:17.93#ibcon#about to read 5, iclass 30, count 2 2006.257.23:20:17.93#ibcon#read 5, iclass 30, count 2 2006.257.23:20:17.93#ibcon#about to read 6, iclass 30, count 2 2006.257.23:20:17.93#ibcon#read 6, iclass 30, count 2 2006.257.23:20:17.93#ibcon#end of sib2, iclass 30, count 2 2006.257.23:20:17.93#ibcon#*mode == 0, iclass 30, count 2 2006.257.23:20:17.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.23:20:17.93#ibcon#[25=AT02-07\r\n] 2006.257.23:20:17.93#ibcon#*before write, iclass 30, count 2 2006.257.23:20:17.93#ibcon#enter sib2, iclass 30, count 2 2006.257.23:20:17.93#ibcon#flushed, iclass 30, count 2 2006.257.23:20:17.93#ibcon#about to write, iclass 30, count 2 2006.257.23:20:17.93#ibcon#wrote, iclass 30, count 2 2006.257.23:20:17.93#ibcon#about to read 3, iclass 30, count 2 2006.257.23:20:17.96#ibcon#read 3, iclass 30, count 2 2006.257.23:20:17.96#ibcon#about to read 4, iclass 30, count 2 2006.257.23:20:17.96#ibcon#read 4, iclass 30, count 2 2006.257.23:20:17.96#ibcon#about to read 5, iclass 30, count 2 2006.257.23:20:17.96#ibcon#read 5, iclass 30, count 2 2006.257.23:20:17.96#ibcon#about to read 6, iclass 30, count 2 2006.257.23:20:17.96#ibcon#read 6, iclass 30, count 2 2006.257.23:20:17.96#ibcon#end of sib2, iclass 30, count 2 2006.257.23:20:17.96#ibcon#*after write, iclass 30, count 2 2006.257.23:20:17.96#ibcon#*before return 0, iclass 30, count 2 2006.257.23:20:17.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:17.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:17.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.23:20:17.96#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:17.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:18.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:18.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:18.08#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:20:18.08#ibcon#first serial, iclass 30, count 0 2006.257.23:20:18.08#ibcon#enter sib2, iclass 30, count 0 2006.257.23:20:18.08#ibcon#flushed, iclass 30, count 0 2006.257.23:20:18.08#ibcon#about to write, iclass 30, count 0 2006.257.23:20:18.08#ibcon#wrote, iclass 30, count 0 2006.257.23:20:18.08#ibcon#about to read 3, iclass 30, count 0 2006.257.23:20:18.10#ibcon#read 3, iclass 30, count 0 2006.257.23:20:18.10#ibcon#about to read 4, iclass 30, count 0 2006.257.23:20:18.10#ibcon#read 4, iclass 30, count 0 2006.257.23:20:18.10#ibcon#about to read 5, iclass 30, count 0 2006.257.23:20:18.10#ibcon#read 5, iclass 30, count 0 2006.257.23:20:18.10#ibcon#about to read 6, iclass 30, count 0 2006.257.23:20:18.10#ibcon#read 6, iclass 30, count 0 2006.257.23:20:18.10#ibcon#end of sib2, iclass 30, count 0 2006.257.23:20:18.10#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:20:18.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:20:18.10#ibcon#[25=USB\r\n] 2006.257.23:20:18.10#ibcon#*before write, iclass 30, count 0 2006.257.23:20:18.10#ibcon#enter sib2, iclass 30, count 0 2006.257.23:20:18.10#ibcon#flushed, iclass 30, count 0 2006.257.23:20:18.10#ibcon#about to write, iclass 30, count 0 2006.257.23:20:18.10#ibcon#wrote, iclass 30, count 0 2006.257.23:20:18.10#ibcon#about to read 3, iclass 30, count 0 2006.257.23:20:18.13#ibcon#read 3, iclass 30, count 0 2006.257.23:20:18.13#ibcon#about to read 4, iclass 30, count 0 2006.257.23:20:18.13#ibcon#read 4, iclass 30, count 0 2006.257.23:20:18.13#ibcon#about to read 5, iclass 30, count 0 2006.257.23:20:18.13#ibcon#read 5, iclass 30, count 0 2006.257.23:20:18.13#ibcon#about to read 6, iclass 30, count 0 2006.257.23:20:18.13#ibcon#read 6, iclass 30, count 0 2006.257.23:20:18.13#ibcon#end of sib2, iclass 30, count 0 2006.257.23:20:18.13#ibcon#*after write, iclass 30, count 0 2006.257.23:20:18.13#ibcon#*before return 0, iclass 30, count 0 2006.257.23:20:18.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:18.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:18.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:20:18.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:20:18.13$vck44/valo=3,564.99 2006.257.23:20:18.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.23:20:18.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.23:20:18.13#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:18.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:18.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:18.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:18.13#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:20:18.13#ibcon#first serial, iclass 32, count 0 2006.257.23:20:18.13#ibcon#enter sib2, iclass 32, count 0 2006.257.23:20:18.13#ibcon#flushed, iclass 32, count 0 2006.257.23:20:18.13#ibcon#about to write, iclass 32, count 0 2006.257.23:20:18.13#ibcon#wrote, iclass 32, count 0 2006.257.23:20:18.13#ibcon#about to read 3, iclass 32, count 0 2006.257.23:20:18.15#ibcon#read 3, iclass 32, count 0 2006.257.23:20:18.15#ibcon#about to read 4, iclass 32, count 0 2006.257.23:20:18.15#ibcon#read 4, iclass 32, count 0 2006.257.23:20:18.15#ibcon#about to read 5, iclass 32, count 0 2006.257.23:20:18.15#ibcon#read 5, iclass 32, count 0 2006.257.23:20:18.15#ibcon#about to read 6, iclass 32, count 0 2006.257.23:20:18.15#ibcon#read 6, iclass 32, count 0 2006.257.23:20:18.15#ibcon#end of sib2, iclass 32, count 0 2006.257.23:20:18.15#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:20:18.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:20:18.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:20:18.15#ibcon#*before write, iclass 32, count 0 2006.257.23:20:18.15#ibcon#enter sib2, iclass 32, count 0 2006.257.23:20:18.15#ibcon#flushed, iclass 32, count 0 2006.257.23:20:18.15#ibcon#about to write, iclass 32, count 0 2006.257.23:20:18.15#ibcon#wrote, iclass 32, count 0 2006.257.23:20:18.15#ibcon#about to read 3, iclass 32, count 0 2006.257.23:20:18.19#ibcon#read 3, iclass 32, count 0 2006.257.23:20:18.19#ibcon#about to read 4, iclass 32, count 0 2006.257.23:20:18.19#ibcon#read 4, iclass 32, count 0 2006.257.23:20:18.19#ibcon#about to read 5, iclass 32, count 0 2006.257.23:20:18.19#ibcon#read 5, iclass 32, count 0 2006.257.23:20:18.19#ibcon#about to read 6, iclass 32, count 0 2006.257.23:20:18.19#ibcon#read 6, iclass 32, count 0 2006.257.23:20:18.19#ibcon#end of sib2, iclass 32, count 0 2006.257.23:20:18.19#ibcon#*after write, iclass 32, count 0 2006.257.23:20:18.19#ibcon#*before return 0, iclass 32, count 0 2006.257.23:20:18.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:18.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:18.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:20:18.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:20:18.19$vck44/va=3,8 2006.257.23:20:18.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.23:20:18.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.23:20:18.19#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:18.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:18.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:18.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:18.25#ibcon#enter wrdev, iclass 34, count 2 2006.257.23:20:18.25#ibcon#first serial, iclass 34, count 2 2006.257.23:20:18.25#ibcon#enter sib2, iclass 34, count 2 2006.257.23:20:18.25#ibcon#flushed, iclass 34, count 2 2006.257.23:20:18.25#ibcon#about to write, iclass 34, count 2 2006.257.23:20:18.25#ibcon#wrote, iclass 34, count 2 2006.257.23:20:18.25#ibcon#about to read 3, iclass 34, count 2 2006.257.23:20:18.27#ibcon#read 3, iclass 34, count 2 2006.257.23:20:18.27#ibcon#about to read 4, iclass 34, count 2 2006.257.23:20:18.27#ibcon#read 4, iclass 34, count 2 2006.257.23:20:18.27#ibcon#about to read 5, iclass 34, count 2 2006.257.23:20:18.27#ibcon#read 5, iclass 34, count 2 2006.257.23:20:18.27#ibcon#about to read 6, iclass 34, count 2 2006.257.23:20:18.27#ibcon#read 6, iclass 34, count 2 2006.257.23:20:18.27#ibcon#end of sib2, iclass 34, count 2 2006.257.23:20:18.27#ibcon#*mode == 0, iclass 34, count 2 2006.257.23:20:18.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.23:20:18.27#ibcon#[25=AT03-08\r\n] 2006.257.23:20:18.27#ibcon#*before write, iclass 34, count 2 2006.257.23:20:18.27#ibcon#enter sib2, iclass 34, count 2 2006.257.23:20:18.27#ibcon#flushed, iclass 34, count 2 2006.257.23:20:18.27#ibcon#about to write, iclass 34, count 2 2006.257.23:20:18.27#ibcon#wrote, iclass 34, count 2 2006.257.23:20:18.27#ibcon#about to read 3, iclass 34, count 2 2006.257.23:20:18.30#ibcon#read 3, iclass 34, count 2 2006.257.23:20:18.30#ibcon#about to read 4, iclass 34, count 2 2006.257.23:20:18.30#ibcon#read 4, iclass 34, count 2 2006.257.23:20:18.30#ibcon#about to read 5, iclass 34, count 2 2006.257.23:20:18.30#ibcon#read 5, iclass 34, count 2 2006.257.23:20:18.30#ibcon#about to read 6, iclass 34, count 2 2006.257.23:20:18.30#ibcon#read 6, iclass 34, count 2 2006.257.23:20:18.30#ibcon#end of sib2, iclass 34, count 2 2006.257.23:20:18.30#ibcon#*after write, iclass 34, count 2 2006.257.23:20:18.30#ibcon#*before return 0, iclass 34, count 2 2006.257.23:20:18.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:18.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:18.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.23:20:18.30#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:18.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:18.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:18.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:18.42#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:20:18.42#ibcon#first serial, iclass 34, count 0 2006.257.23:20:18.42#ibcon#enter sib2, iclass 34, count 0 2006.257.23:20:18.42#ibcon#flushed, iclass 34, count 0 2006.257.23:20:18.42#ibcon#about to write, iclass 34, count 0 2006.257.23:20:18.42#ibcon#wrote, iclass 34, count 0 2006.257.23:20:18.42#ibcon#about to read 3, iclass 34, count 0 2006.257.23:20:18.44#ibcon#read 3, iclass 34, count 0 2006.257.23:20:18.44#ibcon#about to read 4, iclass 34, count 0 2006.257.23:20:18.44#ibcon#read 4, iclass 34, count 0 2006.257.23:20:18.44#ibcon#about to read 5, iclass 34, count 0 2006.257.23:20:18.44#ibcon#read 5, iclass 34, count 0 2006.257.23:20:18.44#ibcon#about to read 6, iclass 34, count 0 2006.257.23:20:18.44#ibcon#read 6, iclass 34, count 0 2006.257.23:20:18.44#ibcon#end of sib2, iclass 34, count 0 2006.257.23:20:18.44#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:20:18.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:20:18.44#ibcon#[25=USB\r\n] 2006.257.23:20:18.44#ibcon#*before write, iclass 34, count 0 2006.257.23:20:18.44#ibcon#enter sib2, iclass 34, count 0 2006.257.23:20:18.44#ibcon#flushed, iclass 34, count 0 2006.257.23:20:18.44#ibcon#about to write, iclass 34, count 0 2006.257.23:20:18.44#ibcon#wrote, iclass 34, count 0 2006.257.23:20:18.44#ibcon#about to read 3, iclass 34, count 0 2006.257.23:20:18.47#ibcon#read 3, iclass 34, count 0 2006.257.23:20:18.47#ibcon#about to read 4, iclass 34, count 0 2006.257.23:20:18.47#ibcon#read 4, iclass 34, count 0 2006.257.23:20:18.47#ibcon#about to read 5, iclass 34, count 0 2006.257.23:20:18.47#ibcon#read 5, iclass 34, count 0 2006.257.23:20:18.47#ibcon#about to read 6, iclass 34, count 0 2006.257.23:20:18.47#ibcon#read 6, iclass 34, count 0 2006.257.23:20:18.47#ibcon#end of sib2, iclass 34, count 0 2006.257.23:20:18.47#ibcon#*after write, iclass 34, count 0 2006.257.23:20:18.47#ibcon#*before return 0, iclass 34, count 0 2006.257.23:20:18.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:18.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:18.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:20:18.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:20:18.47$vck44/valo=4,624.99 2006.257.23:20:18.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.23:20:18.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.23:20:18.47#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:18.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:18.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:18.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:18.47#ibcon#enter wrdev, iclass 36, count 0 2006.257.23:20:18.47#ibcon#first serial, iclass 36, count 0 2006.257.23:20:18.47#ibcon#enter sib2, iclass 36, count 0 2006.257.23:20:18.47#ibcon#flushed, iclass 36, count 0 2006.257.23:20:18.47#ibcon#about to write, iclass 36, count 0 2006.257.23:20:18.47#ibcon#wrote, iclass 36, count 0 2006.257.23:20:18.47#ibcon#about to read 3, iclass 36, count 0 2006.257.23:20:18.49#ibcon#read 3, iclass 36, count 0 2006.257.23:20:18.49#ibcon#about to read 4, iclass 36, count 0 2006.257.23:20:18.49#ibcon#read 4, iclass 36, count 0 2006.257.23:20:18.49#ibcon#about to read 5, iclass 36, count 0 2006.257.23:20:18.49#ibcon#read 5, iclass 36, count 0 2006.257.23:20:18.49#ibcon#about to read 6, iclass 36, count 0 2006.257.23:20:18.49#ibcon#read 6, iclass 36, count 0 2006.257.23:20:18.49#ibcon#end of sib2, iclass 36, count 0 2006.257.23:20:18.49#ibcon#*mode == 0, iclass 36, count 0 2006.257.23:20:18.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.23:20:18.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:20:18.49#ibcon#*before write, iclass 36, count 0 2006.257.23:20:18.49#ibcon#enter sib2, iclass 36, count 0 2006.257.23:20:18.49#ibcon#flushed, iclass 36, count 0 2006.257.23:20:18.49#ibcon#about to write, iclass 36, count 0 2006.257.23:20:18.49#ibcon#wrote, iclass 36, count 0 2006.257.23:20:18.49#ibcon#about to read 3, iclass 36, count 0 2006.257.23:20:18.53#ibcon#read 3, iclass 36, count 0 2006.257.23:20:18.53#ibcon#about to read 4, iclass 36, count 0 2006.257.23:20:18.53#ibcon#read 4, iclass 36, count 0 2006.257.23:20:18.53#ibcon#about to read 5, iclass 36, count 0 2006.257.23:20:18.53#ibcon#read 5, iclass 36, count 0 2006.257.23:20:18.53#ibcon#about to read 6, iclass 36, count 0 2006.257.23:20:18.53#ibcon#read 6, iclass 36, count 0 2006.257.23:20:18.53#ibcon#end of sib2, iclass 36, count 0 2006.257.23:20:18.53#ibcon#*after write, iclass 36, count 0 2006.257.23:20:18.53#ibcon#*before return 0, iclass 36, count 0 2006.257.23:20:18.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:18.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:18.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.23:20:18.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.23:20:18.53$vck44/va=4,7 2006.257.23:20:18.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.23:20:18.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.23:20:18.53#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:18.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:18.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:18.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:18.59#ibcon#enter wrdev, iclass 38, count 2 2006.257.23:20:18.59#ibcon#first serial, iclass 38, count 2 2006.257.23:20:18.59#ibcon#enter sib2, iclass 38, count 2 2006.257.23:20:18.59#ibcon#flushed, iclass 38, count 2 2006.257.23:20:18.59#ibcon#about to write, iclass 38, count 2 2006.257.23:20:18.59#ibcon#wrote, iclass 38, count 2 2006.257.23:20:18.59#ibcon#about to read 3, iclass 38, count 2 2006.257.23:20:18.61#ibcon#read 3, iclass 38, count 2 2006.257.23:20:18.61#ibcon#about to read 4, iclass 38, count 2 2006.257.23:20:18.61#ibcon#read 4, iclass 38, count 2 2006.257.23:20:18.61#ibcon#about to read 5, iclass 38, count 2 2006.257.23:20:18.61#ibcon#read 5, iclass 38, count 2 2006.257.23:20:18.61#ibcon#about to read 6, iclass 38, count 2 2006.257.23:20:18.61#ibcon#read 6, iclass 38, count 2 2006.257.23:20:18.61#ibcon#end of sib2, iclass 38, count 2 2006.257.23:20:18.61#ibcon#*mode == 0, iclass 38, count 2 2006.257.23:20:18.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.23:20:18.61#ibcon#[25=AT04-07\r\n] 2006.257.23:20:18.61#ibcon#*before write, iclass 38, count 2 2006.257.23:20:18.61#ibcon#enter sib2, iclass 38, count 2 2006.257.23:20:18.61#ibcon#flushed, iclass 38, count 2 2006.257.23:20:18.61#ibcon#about to write, iclass 38, count 2 2006.257.23:20:18.61#ibcon#wrote, iclass 38, count 2 2006.257.23:20:18.61#ibcon#about to read 3, iclass 38, count 2 2006.257.23:20:18.64#ibcon#read 3, iclass 38, count 2 2006.257.23:20:18.64#ibcon#about to read 4, iclass 38, count 2 2006.257.23:20:18.64#ibcon#read 4, iclass 38, count 2 2006.257.23:20:18.64#ibcon#about to read 5, iclass 38, count 2 2006.257.23:20:18.64#ibcon#read 5, iclass 38, count 2 2006.257.23:20:18.64#ibcon#about to read 6, iclass 38, count 2 2006.257.23:20:18.64#ibcon#read 6, iclass 38, count 2 2006.257.23:20:18.64#ibcon#end of sib2, iclass 38, count 2 2006.257.23:20:18.64#ibcon#*after write, iclass 38, count 2 2006.257.23:20:18.64#ibcon#*before return 0, iclass 38, count 2 2006.257.23:20:18.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:18.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:18.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.23:20:18.64#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:18.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:18.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:18.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:18.76#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:20:18.76#ibcon#first serial, iclass 38, count 0 2006.257.23:20:18.76#ibcon#enter sib2, iclass 38, count 0 2006.257.23:20:18.76#ibcon#flushed, iclass 38, count 0 2006.257.23:20:18.76#ibcon#about to write, iclass 38, count 0 2006.257.23:20:18.76#ibcon#wrote, iclass 38, count 0 2006.257.23:20:18.76#ibcon#about to read 3, iclass 38, count 0 2006.257.23:20:18.78#ibcon#read 3, iclass 38, count 0 2006.257.23:20:18.78#ibcon#about to read 4, iclass 38, count 0 2006.257.23:20:18.78#ibcon#read 4, iclass 38, count 0 2006.257.23:20:18.78#ibcon#about to read 5, iclass 38, count 0 2006.257.23:20:18.78#ibcon#read 5, iclass 38, count 0 2006.257.23:20:18.78#ibcon#about to read 6, iclass 38, count 0 2006.257.23:20:18.78#ibcon#read 6, iclass 38, count 0 2006.257.23:20:18.78#ibcon#end of sib2, iclass 38, count 0 2006.257.23:20:18.78#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:20:18.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:20:18.78#ibcon#[25=USB\r\n] 2006.257.23:20:18.78#ibcon#*before write, iclass 38, count 0 2006.257.23:20:18.78#ibcon#enter sib2, iclass 38, count 0 2006.257.23:20:18.78#ibcon#flushed, iclass 38, count 0 2006.257.23:20:18.78#ibcon#about to write, iclass 38, count 0 2006.257.23:20:18.78#ibcon#wrote, iclass 38, count 0 2006.257.23:20:18.78#ibcon#about to read 3, iclass 38, count 0 2006.257.23:20:18.81#ibcon#read 3, iclass 38, count 0 2006.257.23:20:18.81#ibcon#about to read 4, iclass 38, count 0 2006.257.23:20:18.81#ibcon#read 4, iclass 38, count 0 2006.257.23:20:18.81#ibcon#about to read 5, iclass 38, count 0 2006.257.23:20:18.81#ibcon#read 5, iclass 38, count 0 2006.257.23:20:18.81#ibcon#about to read 6, iclass 38, count 0 2006.257.23:20:18.81#ibcon#read 6, iclass 38, count 0 2006.257.23:20:18.81#ibcon#end of sib2, iclass 38, count 0 2006.257.23:20:18.81#ibcon#*after write, iclass 38, count 0 2006.257.23:20:18.81#ibcon#*before return 0, iclass 38, count 0 2006.257.23:20:18.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:18.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:18.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:20:18.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:20:18.81$vck44/valo=5,734.99 2006.257.23:20:18.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.23:20:18.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.23:20:18.81#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:18.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:18.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:18.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:18.81#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:20:18.81#ibcon#first serial, iclass 40, count 0 2006.257.23:20:18.81#ibcon#enter sib2, iclass 40, count 0 2006.257.23:20:18.81#ibcon#flushed, iclass 40, count 0 2006.257.23:20:18.81#ibcon#about to write, iclass 40, count 0 2006.257.23:20:18.81#ibcon#wrote, iclass 40, count 0 2006.257.23:20:18.81#ibcon#about to read 3, iclass 40, count 0 2006.257.23:20:18.83#ibcon#read 3, iclass 40, count 0 2006.257.23:20:18.83#ibcon#about to read 4, iclass 40, count 0 2006.257.23:20:18.83#ibcon#read 4, iclass 40, count 0 2006.257.23:20:18.83#ibcon#about to read 5, iclass 40, count 0 2006.257.23:20:18.83#ibcon#read 5, iclass 40, count 0 2006.257.23:20:18.83#ibcon#about to read 6, iclass 40, count 0 2006.257.23:20:18.83#ibcon#read 6, iclass 40, count 0 2006.257.23:20:18.83#ibcon#end of sib2, iclass 40, count 0 2006.257.23:20:18.83#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:20:18.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:20:18.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:20:18.83#ibcon#*before write, iclass 40, count 0 2006.257.23:20:18.83#ibcon#enter sib2, iclass 40, count 0 2006.257.23:20:18.83#ibcon#flushed, iclass 40, count 0 2006.257.23:20:18.83#ibcon#about to write, iclass 40, count 0 2006.257.23:20:18.83#ibcon#wrote, iclass 40, count 0 2006.257.23:20:18.83#ibcon#about to read 3, iclass 40, count 0 2006.257.23:20:18.87#ibcon#read 3, iclass 40, count 0 2006.257.23:20:18.87#ibcon#about to read 4, iclass 40, count 0 2006.257.23:20:18.87#ibcon#read 4, iclass 40, count 0 2006.257.23:20:18.87#ibcon#about to read 5, iclass 40, count 0 2006.257.23:20:18.87#ibcon#read 5, iclass 40, count 0 2006.257.23:20:18.87#ibcon#about to read 6, iclass 40, count 0 2006.257.23:20:18.87#ibcon#read 6, iclass 40, count 0 2006.257.23:20:18.87#ibcon#end of sib2, iclass 40, count 0 2006.257.23:20:18.87#ibcon#*after write, iclass 40, count 0 2006.257.23:20:18.87#ibcon#*before return 0, iclass 40, count 0 2006.257.23:20:18.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:18.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:18.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:20:18.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:20:18.87$vck44/va=5,4 2006.257.23:20:18.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.23:20:18.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.23:20:18.87#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:18.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:18.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:18.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:18.93#ibcon#enter wrdev, iclass 4, count 2 2006.257.23:20:18.93#ibcon#first serial, iclass 4, count 2 2006.257.23:20:18.93#ibcon#enter sib2, iclass 4, count 2 2006.257.23:20:18.93#ibcon#flushed, iclass 4, count 2 2006.257.23:20:18.93#ibcon#about to write, iclass 4, count 2 2006.257.23:20:18.93#ibcon#wrote, iclass 4, count 2 2006.257.23:20:18.93#ibcon#about to read 3, iclass 4, count 2 2006.257.23:20:18.95#ibcon#read 3, iclass 4, count 2 2006.257.23:20:18.95#ibcon#about to read 4, iclass 4, count 2 2006.257.23:20:18.95#ibcon#read 4, iclass 4, count 2 2006.257.23:20:18.95#ibcon#about to read 5, iclass 4, count 2 2006.257.23:20:18.95#ibcon#read 5, iclass 4, count 2 2006.257.23:20:18.95#ibcon#about to read 6, iclass 4, count 2 2006.257.23:20:18.95#ibcon#read 6, iclass 4, count 2 2006.257.23:20:18.95#ibcon#end of sib2, iclass 4, count 2 2006.257.23:20:18.95#ibcon#*mode == 0, iclass 4, count 2 2006.257.23:20:18.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.23:20:18.95#ibcon#[25=AT05-04\r\n] 2006.257.23:20:18.95#ibcon#*before write, iclass 4, count 2 2006.257.23:20:18.95#ibcon#enter sib2, iclass 4, count 2 2006.257.23:20:18.95#ibcon#flushed, iclass 4, count 2 2006.257.23:20:18.95#ibcon#about to write, iclass 4, count 2 2006.257.23:20:18.95#ibcon#wrote, iclass 4, count 2 2006.257.23:20:18.95#ibcon#about to read 3, iclass 4, count 2 2006.257.23:20:18.98#ibcon#read 3, iclass 4, count 2 2006.257.23:20:18.98#ibcon#about to read 4, iclass 4, count 2 2006.257.23:20:18.98#ibcon#read 4, iclass 4, count 2 2006.257.23:20:18.98#ibcon#about to read 5, iclass 4, count 2 2006.257.23:20:18.98#ibcon#read 5, iclass 4, count 2 2006.257.23:20:18.98#ibcon#about to read 6, iclass 4, count 2 2006.257.23:20:18.98#ibcon#read 6, iclass 4, count 2 2006.257.23:20:18.98#ibcon#end of sib2, iclass 4, count 2 2006.257.23:20:18.98#ibcon#*after write, iclass 4, count 2 2006.257.23:20:18.98#ibcon#*before return 0, iclass 4, count 2 2006.257.23:20:18.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:18.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:18.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.23:20:18.98#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:18.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:19.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:19.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:19.10#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:20:19.10#ibcon#first serial, iclass 4, count 0 2006.257.23:20:19.10#ibcon#enter sib2, iclass 4, count 0 2006.257.23:20:19.10#ibcon#flushed, iclass 4, count 0 2006.257.23:20:19.10#ibcon#about to write, iclass 4, count 0 2006.257.23:20:19.10#ibcon#wrote, iclass 4, count 0 2006.257.23:20:19.10#ibcon#about to read 3, iclass 4, count 0 2006.257.23:20:19.12#ibcon#read 3, iclass 4, count 0 2006.257.23:20:19.12#ibcon#about to read 4, iclass 4, count 0 2006.257.23:20:19.12#ibcon#read 4, iclass 4, count 0 2006.257.23:20:19.12#ibcon#about to read 5, iclass 4, count 0 2006.257.23:20:19.12#ibcon#read 5, iclass 4, count 0 2006.257.23:20:19.12#ibcon#about to read 6, iclass 4, count 0 2006.257.23:20:19.12#ibcon#read 6, iclass 4, count 0 2006.257.23:20:19.12#ibcon#end of sib2, iclass 4, count 0 2006.257.23:20:19.12#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:20:19.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:20:19.12#ibcon#[25=USB\r\n] 2006.257.23:20:19.12#ibcon#*before write, iclass 4, count 0 2006.257.23:20:19.12#ibcon#enter sib2, iclass 4, count 0 2006.257.23:20:19.12#ibcon#flushed, iclass 4, count 0 2006.257.23:20:19.12#ibcon#about to write, iclass 4, count 0 2006.257.23:20:19.12#ibcon#wrote, iclass 4, count 0 2006.257.23:20:19.12#ibcon#about to read 3, iclass 4, count 0 2006.257.23:20:19.15#ibcon#read 3, iclass 4, count 0 2006.257.23:20:19.15#ibcon#about to read 4, iclass 4, count 0 2006.257.23:20:19.15#ibcon#read 4, iclass 4, count 0 2006.257.23:20:19.15#ibcon#about to read 5, iclass 4, count 0 2006.257.23:20:19.15#ibcon#read 5, iclass 4, count 0 2006.257.23:20:19.15#ibcon#about to read 6, iclass 4, count 0 2006.257.23:20:19.15#ibcon#read 6, iclass 4, count 0 2006.257.23:20:19.15#ibcon#end of sib2, iclass 4, count 0 2006.257.23:20:19.15#ibcon#*after write, iclass 4, count 0 2006.257.23:20:19.15#ibcon#*before return 0, iclass 4, count 0 2006.257.23:20:19.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:19.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:19.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:20:19.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:20:19.15$vck44/valo=6,814.99 2006.257.23:20:19.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.23:20:19.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.23:20:19.15#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:19.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:19.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:19.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:19.15#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:20:19.15#ibcon#first serial, iclass 6, count 0 2006.257.23:20:19.15#ibcon#enter sib2, iclass 6, count 0 2006.257.23:20:19.15#ibcon#flushed, iclass 6, count 0 2006.257.23:20:19.15#ibcon#about to write, iclass 6, count 0 2006.257.23:20:19.15#ibcon#wrote, iclass 6, count 0 2006.257.23:20:19.15#ibcon#about to read 3, iclass 6, count 0 2006.257.23:20:19.17#ibcon#read 3, iclass 6, count 0 2006.257.23:20:19.17#ibcon#about to read 4, iclass 6, count 0 2006.257.23:20:19.17#ibcon#read 4, iclass 6, count 0 2006.257.23:20:19.17#ibcon#about to read 5, iclass 6, count 0 2006.257.23:20:19.17#ibcon#read 5, iclass 6, count 0 2006.257.23:20:19.17#ibcon#about to read 6, iclass 6, count 0 2006.257.23:20:19.17#ibcon#read 6, iclass 6, count 0 2006.257.23:20:19.17#ibcon#end of sib2, iclass 6, count 0 2006.257.23:20:19.17#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:20:19.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:20:19.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:20:19.17#ibcon#*before write, iclass 6, count 0 2006.257.23:20:19.17#ibcon#enter sib2, iclass 6, count 0 2006.257.23:20:19.17#ibcon#flushed, iclass 6, count 0 2006.257.23:20:19.17#ibcon#about to write, iclass 6, count 0 2006.257.23:20:19.17#ibcon#wrote, iclass 6, count 0 2006.257.23:20:19.17#ibcon#about to read 3, iclass 6, count 0 2006.257.23:20:19.21#ibcon#read 3, iclass 6, count 0 2006.257.23:20:19.21#ibcon#about to read 4, iclass 6, count 0 2006.257.23:20:19.21#ibcon#read 4, iclass 6, count 0 2006.257.23:20:19.21#ibcon#about to read 5, iclass 6, count 0 2006.257.23:20:19.21#ibcon#read 5, iclass 6, count 0 2006.257.23:20:19.21#ibcon#about to read 6, iclass 6, count 0 2006.257.23:20:19.21#ibcon#read 6, iclass 6, count 0 2006.257.23:20:19.21#ibcon#end of sib2, iclass 6, count 0 2006.257.23:20:19.21#ibcon#*after write, iclass 6, count 0 2006.257.23:20:19.21#ibcon#*before return 0, iclass 6, count 0 2006.257.23:20:19.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:19.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:19.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:20:19.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:20:19.21$vck44/va=6,4 2006.257.23:20:19.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.23:20:19.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.23:20:19.21#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:19.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:19.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:19.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:19.27#ibcon#enter wrdev, iclass 10, count 2 2006.257.23:20:19.27#ibcon#first serial, iclass 10, count 2 2006.257.23:20:19.27#ibcon#enter sib2, iclass 10, count 2 2006.257.23:20:19.27#ibcon#flushed, iclass 10, count 2 2006.257.23:20:19.27#ibcon#about to write, iclass 10, count 2 2006.257.23:20:19.27#ibcon#wrote, iclass 10, count 2 2006.257.23:20:19.27#ibcon#about to read 3, iclass 10, count 2 2006.257.23:20:19.29#ibcon#read 3, iclass 10, count 2 2006.257.23:20:19.29#ibcon#about to read 4, iclass 10, count 2 2006.257.23:20:19.29#ibcon#read 4, iclass 10, count 2 2006.257.23:20:19.29#ibcon#about to read 5, iclass 10, count 2 2006.257.23:20:19.29#ibcon#read 5, iclass 10, count 2 2006.257.23:20:19.29#ibcon#about to read 6, iclass 10, count 2 2006.257.23:20:19.29#ibcon#read 6, iclass 10, count 2 2006.257.23:20:19.29#ibcon#end of sib2, iclass 10, count 2 2006.257.23:20:19.29#ibcon#*mode == 0, iclass 10, count 2 2006.257.23:20:19.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.23:20:19.29#ibcon#[25=AT06-04\r\n] 2006.257.23:20:19.29#ibcon#*before write, iclass 10, count 2 2006.257.23:20:19.29#ibcon#enter sib2, iclass 10, count 2 2006.257.23:20:19.29#ibcon#flushed, iclass 10, count 2 2006.257.23:20:19.29#ibcon#about to write, iclass 10, count 2 2006.257.23:20:19.29#ibcon#wrote, iclass 10, count 2 2006.257.23:20:19.29#ibcon#about to read 3, iclass 10, count 2 2006.257.23:20:19.32#ibcon#read 3, iclass 10, count 2 2006.257.23:20:19.32#ibcon#about to read 4, iclass 10, count 2 2006.257.23:20:19.32#ibcon#read 4, iclass 10, count 2 2006.257.23:20:19.32#ibcon#about to read 5, iclass 10, count 2 2006.257.23:20:19.32#ibcon#read 5, iclass 10, count 2 2006.257.23:20:19.32#ibcon#about to read 6, iclass 10, count 2 2006.257.23:20:19.32#ibcon#read 6, iclass 10, count 2 2006.257.23:20:19.32#ibcon#end of sib2, iclass 10, count 2 2006.257.23:20:19.32#ibcon#*after write, iclass 10, count 2 2006.257.23:20:19.32#ibcon#*before return 0, iclass 10, count 2 2006.257.23:20:19.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:19.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:19.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.23:20:19.32#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:19.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:19.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:19.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:19.44#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:20:19.44#ibcon#first serial, iclass 10, count 0 2006.257.23:20:19.44#ibcon#enter sib2, iclass 10, count 0 2006.257.23:20:19.44#ibcon#flushed, iclass 10, count 0 2006.257.23:20:19.44#ibcon#about to write, iclass 10, count 0 2006.257.23:20:19.44#ibcon#wrote, iclass 10, count 0 2006.257.23:20:19.44#ibcon#about to read 3, iclass 10, count 0 2006.257.23:20:19.46#ibcon#read 3, iclass 10, count 0 2006.257.23:20:19.46#ibcon#about to read 4, iclass 10, count 0 2006.257.23:20:19.46#ibcon#read 4, iclass 10, count 0 2006.257.23:20:19.46#ibcon#about to read 5, iclass 10, count 0 2006.257.23:20:19.46#ibcon#read 5, iclass 10, count 0 2006.257.23:20:19.46#ibcon#about to read 6, iclass 10, count 0 2006.257.23:20:19.46#ibcon#read 6, iclass 10, count 0 2006.257.23:20:19.46#ibcon#end of sib2, iclass 10, count 0 2006.257.23:20:19.46#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:20:19.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:20:19.46#ibcon#[25=USB\r\n] 2006.257.23:20:19.46#ibcon#*before write, iclass 10, count 0 2006.257.23:20:19.46#ibcon#enter sib2, iclass 10, count 0 2006.257.23:20:19.46#ibcon#flushed, iclass 10, count 0 2006.257.23:20:19.46#ibcon#about to write, iclass 10, count 0 2006.257.23:20:19.46#ibcon#wrote, iclass 10, count 0 2006.257.23:20:19.46#ibcon#about to read 3, iclass 10, count 0 2006.257.23:20:19.49#ibcon#read 3, iclass 10, count 0 2006.257.23:20:19.49#ibcon#about to read 4, iclass 10, count 0 2006.257.23:20:19.49#ibcon#read 4, iclass 10, count 0 2006.257.23:20:19.49#ibcon#about to read 5, iclass 10, count 0 2006.257.23:20:19.49#ibcon#read 5, iclass 10, count 0 2006.257.23:20:19.49#ibcon#about to read 6, iclass 10, count 0 2006.257.23:20:19.49#ibcon#read 6, iclass 10, count 0 2006.257.23:20:19.49#ibcon#end of sib2, iclass 10, count 0 2006.257.23:20:19.49#ibcon#*after write, iclass 10, count 0 2006.257.23:20:19.49#ibcon#*before return 0, iclass 10, count 0 2006.257.23:20:19.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:19.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:19.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:20:19.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:20:19.49$vck44/valo=7,864.99 2006.257.23:20:19.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.23:20:19.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.23:20:19.49#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:19.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:19.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:19.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:19.49#ibcon#enter wrdev, iclass 12, count 0 2006.257.23:20:19.49#ibcon#first serial, iclass 12, count 0 2006.257.23:20:19.49#ibcon#enter sib2, iclass 12, count 0 2006.257.23:20:19.49#ibcon#flushed, iclass 12, count 0 2006.257.23:20:19.49#ibcon#about to write, iclass 12, count 0 2006.257.23:20:19.49#ibcon#wrote, iclass 12, count 0 2006.257.23:20:19.49#ibcon#about to read 3, iclass 12, count 0 2006.257.23:20:19.51#ibcon#read 3, iclass 12, count 0 2006.257.23:20:19.51#ibcon#about to read 4, iclass 12, count 0 2006.257.23:20:19.51#ibcon#read 4, iclass 12, count 0 2006.257.23:20:19.51#ibcon#about to read 5, iclass 12, count 0 2006.257.23:20:19.51#ibcon#read 5, iclass 12, count 0 2006.257.23:20:19.51#ibcon#about to read 6, iclass 12, count 0 2006.257.23:20:19.51#ibcon#read 6, iclass 12, count 0 2006.257.23:20:19.51#ibcon#end of sib2, iclass 12, count 0 2006.257.23:20:19.51#ibcon#*mode == 0, iclass 12, count 0 2006.257.23:20:19.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.23:20:19.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:20:19.51#ibcon#*before write, iclass 12, count 0 2006.257.23:20:19.51#ibcon#enter sib2, iclass 12, count 0 2006.257.23:20:19.51#ibcon#flushed, iclass 12, count 0 2006.257.23:20:19.51#ibcon#about to write, iclass 12, count 0 2006.257.23:20:19.51#ibcon#wrote, iclass 12, count 0 2006.257.23:20:19.51#ibcon#about to read 3, iclass 12, count 0 2006.257.23:20:19.55#ibcon#read 3, iclass 12, count 0 2006.257.23:20:19.55#ibcon#about to read 4, iclass 12, count 0 2006.257.23:20:19.55#ibcon#read 4, iclass 12, count 0 2006.257.23:20:19.55#ibcon#about to read 5, iclass 12, count 0 2006.257.23:20:19.55#ibcon#read 5, iclass 12, count 0 2006.257.23:20:19.55#ibcon#about to read 6, iclass 12, count 0 2006.257.23:20:19.55#ibcon#read 6, iclass 12, count 0 2006.257.23:20:19.55#ibcon#end of sib2, iclass 12, count 0 2006.257.23:20:19.55#ibcon#*after write, iclass 12, count 0 2006.257.23:20:19.55#ibcon#*before return 0, iclass 12, count 0 2006.257.23:20:19.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:19.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:19.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.23:20:19.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.23:20:19.55$vck44/va=7,4 2006.257.23:20:19.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.23:20:19.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.23:20:19.55#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:19.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:19.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:19.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:19.61#ibcon#enter wrdev, iclass 14, count 2 2006.257.23:20:19.61#ibcon#first serial, iclass 14, count 2 2006.257.23:20:19.61#ibcon#enter sib2, iclass 14, count 2 2006.257.23:20:19.61#ibcon#flushed, iclass 14, count 2 2006.257.23:20:19.61#ibcon#about to write, iclass 14, count 2 2006.257.23:20:19.61#ibcon#wrote, iclass 14, count 2 2006.257.23:20:19.61#ibcon#about to read 3, iclass 14, count 2 2006.257.23:20:19.63#ibcon#read 3, iclass 14, count 2 2006.257.23:20:19.63#ibcon#about to read 4, iclass 14, count 2 2006.257.23:20:19.63#ibcon#read 4, iclass 14, count 2 2006.257.23:20:19.63#ibcon#about to read 5, iclass 14, count 2 2006.257.23:20:19.63#ibcon#read 5, iclass 14, count 2 2006.257.23:20:19.63#ibcon#about to read 6, iclass 14, count 2 2006.257.23:20:19.63#ibcon#read 6, iclass 14, count 2 2006.257.23:20:19.63#ibcon#end of sib2, iclass 14, count 2 2006.257.23:20:19.63#ibcon#*mode == 0, iclass 14, count 2 2006.257.23:20:19.63#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.23:20:19.63#ibcon#[25=AT07-04\r\n] 2006.257.23:20:19.63#ibcon#*before write, iclass 14, count 2 2006.257.23:20:19.63#ibcon#enter sib2, iclass 14, count 2 2006.257.23:20:19.63#ibcon#flushed, iclass 14, count 2 2006.257.23:20:19.63#ibcon#about to write, iclass 14, count 2 2006.257.23:20:19.63#ibcon#wrote, iclass 14, count 2 2006.257.23:20:19.63#ibcon#about to read 3, iclass 14, count 2 2006.257.23:20:19.66#ibcon#read 3, iclass 14, count 2 2006.257.23:20:19.66#ibcon#about to read 4, iclass 14, count 2 2006.257.23:20:19.66#ibcon#read 4, iclass 14, count 2 2006.257.23:20:19.66#ibcon#about to read 5, iclass 14, count 2 2006.257.23:20:19.66#ibcon#read 5, iclass 14, count 2 2006.257.23:20:19.66#ibcon#about to read 6, iclass 14, count 2 2006.257.23:20:19.66#ibcon#read 6, iclass 14, count 2 2006.257.23:20:19.66#ibcon#end of sib2, iclass 14, count 2 2006.257.23:20:19.66#ibcon#*after write, iclass 14, count 2 2006.257.23:20:19.66#ibcon#*before return 0, iclass 14, count 2 2006.257.23:20:19.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:19.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:19.66#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.23:20:19.66#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:19.66#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:19.78#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:19.78#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:19.78#ibcon#enter wrdev, iclass 14, count 0 2006.257.23:20:19.78#ibcon#first serial, iclass 14, count 0 2006.257.23:20:19.78#ibcon#enter sib2, iclass 14, count 0 2006.257.23:20:19.78#ibcon#flushed, iclass 14, count 0 2006.257.23:20:19.78#ibcon#about to write, iclass 14, count 0 2006.257.23:20:19.78#ibcon#wrote, iclass 14, count 0 2006.257.23:20:19.78#ibcon#about to read 3, iclass 14, count 0 2006.257.23:20:19.80#ibcon#read 3, iclass 14, count 0 2006.257.23:20:19.80#ibcon#about to read 4, iclass 14, count 0 2006.257.23:20:19.80#ibcon#read 4, iclass 14, count 0 2006.257.23:20:19.80#ibcon#about to read 5, iclass 14, count 0 2006.257.23:20:19.80#ibcon#read 5, iclass 14, count 0 2006.257.23:20:19.80#ibcon#about to read 6, iclass 14, count 0 2006.257.23:20:19.80#ibcon#read 6, iclass 14, count 0 2006.257.23:20:19.80#ibcon#end of sib2, iclass 14, count 0 2006.257.23:20:19.80#ibcon#*mode == 0, iclass 14, count 0 2006.257.23:20:19.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.23:20:19.80#ibcon#[25=USB\r\n] 2006.257.23:20:19.80#ibcon#*before write, iclass 14, count 0 2006.257.23:20:19.80#ibcon#enter sib2, iclass 14, count 0 2006.257.23:20:19.80#ibcon#flushed, iclass 14, count 0 2006.257.23:20:19.80#ibcon#about to write, iclass 14, count 0 2006.257.23:20:19.80#ibcon#wrote, iclass 14, count 0 2006.257.23:20:19.80#ibcon#about to read 3, iclass 14, count 0 2006.257.23:20:19.83#ibcon#read 3, iclass 14, count 0 2006.257.23:20:19.83#ibcon#about to read 4, iclass 14, count 0 2006.257.23:20:19.83#ibcon#read 4, iclass 14, count 0 2006.257.23:20:19.83#ibcon#about to read 5, iclass 14, count 0 2006.257.23:20:19.83#ibcon#read 5, iclass 14, count 0 2006.257.23:20:19.83#ibcon#about to read 6, iclass 14, count 0 2006.257.23:20:19.83#ibcon#read 6, iclass 14, count 0 2006.257.23:20:19.83#ibcon#end of sib2, iclass 14, count 0 2006.257.23:20:19.83#ibcon#*after write, iclass 14, count 0 2006.257.23:20:19.83#ibcon#*before return 0, iclass 14, count 0 2006.257.23:20:19.83#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:19.83#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:19.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.23:20:19.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.23:20:19.83$vck44/valo=8,884.99 2006.257.23:20:19.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.23:20:19.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.23:20:19.83#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:19.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:19.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:19.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:19.83#ibcon#enter wrdev, iclass 16, count 0 2006.257.23:20:19.83#ibcon#first serial, iclass 16, count 0 2006.257.23:20:19.83#ibcon#enter sib2, iclass 16, count 0 2006.257.23:20:19.83#ibcon#flushed, iclass 16, count 0 2006.257.23:20:19.83#ibcon#about to write, iclass 16, count 0 2006.257.23:20:19.83#ibcon#wrote, iclass 16, count 0 2006.257.23:20:19.83#ibcon#about to read 3, iclass 16, count 0 2006.257.23:20:19.85#ibcon#read 3, iclass 16, count 0 2006.257.23:20:19.85#ibcon#about to read 4, iclass 16, count 0 2006.257.23:20:19.85#ibcon#read 4, iclass 16, count 0 2006.257.23:20:19.85#ibcon#about to read 5, iclass 16, count 0 2006.257.23:20:19.85#ibcon#read 5, iclass 16, count 0 2006.257.23:20:19.85#ibcon#about to read 6, iclass 16, count 0 2006.257.23:20:19.85#ibcon#read 6, iclass 16, count 0 2006.257.23:20:19.85#ibcon#end of sib2, iclass 16, count 0 2006.257.23:20:19.85#ibcon#*mode == 0, iclass 16, count 0 2006.257.23:20:19.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.23:20:19.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:20:19.85#ibcon#*before write, iclass 16, count 0 2006.257.23:20:19.85#ibcon#enter sib2, iclass 16, count 0 2006.257.23:20:19.85#ibcon#flushed, iclass 16, count 0 2006.257.23:20:19.85#ibcon#about to write, iclass 16, count 0 2006.257.23:20:19.85#ibcon#wrote, iclass 16, count 0 2006.257.23:20:19.85#ibcon#about to read 3, iclass 16, count 0 2006.257.23:20:19.89#ibcon#read 3, iclass 16, count 0 2006.257.23:20:19.89#ibcon#about to read 4, iclass 16, count 0 2006.257.23:20:19.89#ibcon#read 4, iclass 16, count 0 2006.257.23:20:19.89#ibcon#about to read 5, iclass 16, count 0 2006.257.23:20:19.89#ibcon#read 5, iclass 16, count 0 2006.257.23:20:19.89#ibcon#about to read 6, iclass 16, count 0 2006.257.23:20:19.89#ibcon#read 6, iclass 16, count 0 2006.257.23:20:19.89#ibcon#end of sib2, iclass 16, count 0 2006.257.23:20:19.89#ibcon#*after write, iclass 16, count 0 2006.257.23:20:19.89#ibcon#*before return 0, iclass 16, count 0 2006.257.23:20:19.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:19.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:19.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.23:20:19.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.23:20:19.89$vck44/va=8,4 2006.257.23:20:19.89#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.23:20:19.89#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.23:20:19.89#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:19.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:20:19.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:20:19.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:20:19.95#ibcon#enter wrdev, iclass 18, count 2 2006.257.23:20:19.95#ibcon#first serial, iclass 18, count 2 2006.257.23:20:19.95#ibcon#enter sib2, iclass 18, count 2 2006.257.23:20:19.95#ibcon#flushed, iclass 18, count 2 2006.257.23:20:19.95#ibcon#about to write, iclass 18, count 2 2006.257.23:20:19.95#ibcon#wrote, iclass 18, count 2 2006.257.23:20:19.95#ibcon#about to read 3, iclass 18, count 2 2006.257.23:20:19.97#ibcon#read 3, iclass 18, count 2 2006.257.23:20:19.97#ibcon#about to read 4, iclass 18, count 2 2006.257.23:20:19.97#ibcon#read 4, iclass 18, count 2 2006.257.23:20:19.97#ibcon#about to read 5, iclass 18, count 2 2006.257.23:20:19.97#ibcon#read 5, iclass 18, count 2 2006.257.23:20:19.97#ibcon#about to read 6, iclass 18, count 2 2006.257.23:20:19.97#ibcon#read 6, iclass 18, count 2 2006.257.23:20:19.97#ibcon#end of sib2, iclass 18, count 2 2006.257.23:20:19.97#ibcon#*mode == 0, iclass 18, count 2 2006.257.23:20:19.97#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.23:20:19.97#ibcon#[25=AT08-04\r\n] 2006.257.23:20:19.97#ibcon#*before write, iclass 18, count 2 2006.257.23:20:19.97#ibcon#enter sib2, iclass 18, count 2 2006.257.23:20:19.97#ibcon#flushed, iclass 18, count 2 2006.257.23:20:19.97#ibcon#about to write, iclass 18, count 2 2006.257.23:20:19.97#ibcon#wrote, iclass 18, count 2 2006.257.23:20:19.97#ibcon#about to read 3, iclass 18, count 2 2006.257.23:20:20.00#ibcon#read 3, iclass 18, count 2 2006.257.23:20:20.00#ibcon#about to read 4, iclass 18, count 2 2006.257.23:20:20.00#ibcon#read 4, iclass 18, count 2 2006.257.23:20:20.00#ibcon#about to read 5, iclass 18, count 2 2006.257.23:20:20.00#ibcon#read 5, iclass 18, count 2 2006.257.23:20:20.00#ibcon#about to read 6, iclass 18, count 2 2006.257.23:20:20.00#ibcon#read 6, iclass 18, count 2 2006.257.23:20:20.00#ibcon#end of sib2, iclass 18, count 2 2006.257.23:20:20.00#ibcon#*after write, iclass 18, count 2 2006.257.23:20:20.00#ibcon#*before return 0, iclass 18, count 2 2006.257.23:20:20.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:20:20.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:20:20.00#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.23:20:20.00#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:20.00#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:20:20.12#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:20:20.12#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:20:20.12#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:20:20.12#ibcon#first serial, iclass 18, count 0 2006.257.23:20:20.12#ibcon#enter sib2, iclass 18, count 0 2006.257.23:20:20.12#ibcon#flushed, iclass 18, count 0 2006.257.23:20:20.12#ibcon#about to write, iclass 18, count 0 2006.257.23:20:20.12#ibcon#wrote, iclass 18, count 0 2006.257.23:20:20.12#ibcon#about to read 3, iclass 18, count 0 2006.257.23:20:20.14#ibcon#read 3, iclass 18, count 0 2006.257.23:20:20.14#ibcon#about to read 4, iclass 18, count 0 2006.257.23:20:20.14#ibcon#read 4, iclass 18, count 0 2006.257.23:20:20.14#ibcon#about to read 5, iclass 18, count 0 2006.257.23:20:20.14#ibcon#read 5, iclass 18, count 0 2006.257.23:20:20.14#ibcon#about to read 6, iclass 18, count 0 2006.257.23:20:20.14#ibcon#read 6, iclass 18, count 0 2006.257.23:20:20.14#ibcon#end of sib2, iclass 18, count 0 2006.257.23:20:20.14#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:20:20.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:20:20.14#ibcon#[25=USB\r\n] 2006.257.23:20:20.14#ibcon#*before write, iclass 18, count 0 2006.257.23:20:20.14#ibcon#enter sib2, iclass 18, count 0 2006.257.23:20:20.14#ibcon#flushed, iclass 18, count 0 2006.257.23:20:20.14#ibcon#about to write, iclass 18, count 0 2006.257.23:20:20.14#ibcon#wrote, iclass 18, count 0 2006.257.23:20:20.14#ibcon#about to read 3, iclass 18, count 0 2006.257.23:20:20.17#ibcon#read 3, iclass 18, count 0 2006.257.23:20:20.17#ibcon#about to read 4, iclass 18, count 0 2006.257.23:20:20.17#ibcon#read 4, iclass 18, count 0 2006.257.23:20:20.17#ibcon#about to read 5, iclass 18, count 0 2006.257.23:20:20.17#ibcon#read 5, iclass 18, count 0 2006.257.23:20:20.17#ibcon#about to read 6, iclass 18, count 0 2006.257.23:20:20.17#ibcon#read 6, iclass 18, count 0 2006.257.23:20:20.17#ibcon#end of sib2, iclass 18, count 0 2006.257.23:20:20.17#ibcon#*after write, iclass 18, count 0 2006.257.23:20:20.17#ibcon#*before return 0, iclass 18, count 0 2006.257.23:20:20.17#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:20:20.17#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:20:20.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:20:20.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:20:20.17$vck44/vblo=1,629.99 2006.257.23:20:20.17#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.23:20:20.17#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.23:20:20.17#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:20.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:20:20.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:20:20.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:20:20.17#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:20:20.17#ibcon#first serial, iclass 20, count 0 2006.257.23:20:20.17#ibcon#enter sib2, iclass 20, count 0 2006.257.23:20:20.17#ibcon#flushed, iclass 20, count 0 2006.257.23:20:20.17#ibcon#about to write, iclass 20, count 0 2006.257.23:20:20.17#ibcon#wrote, iclass 20, count 0 2006.257.23:20:20.17#ibcon#about to read 3, iclass 20, count 0 2006.257.23:20:20.19#ibcon#read 3, iclass 20, count 0 2006.257.23:20:20.19#ibcon#about to read 4, iclass 20, count 0 2006.257.23:20:20.19#ibcon#read 4, iclass 20, count 0 2006.257.23:20:20.19#ibcon#about to read 5, iclass 20, count 0 2006.257.23:20:20.19#ibcon#read 5, iclass 20, count 0 2006.257.23:20:20.19#ibcon#about to read 6, iclass 20, count 0 2006.257.23:20:20.19#ibcon#read 6, iclass 20, count 0 2006.257.23:20:20.19#ibcon#end of sib2, iclass 20, count 0 2006.257.23:20:20.19#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:20:20.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:20:20.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:20:20.19#ibcon#*before write, iclass 20, count 0 2006.257.23:20:20.19#ibcon#enter sib2, iclass 20, count 0 2006.257.23:20:20.19#ibcon#flushed, iclass 20, count 0 2006.257.23:20:20.19#ibcon#about to write, iclass 20, count 0 2006.257.23:20:20.19#ibcon#wrote, iclass 20, count 0 2006.257.23:20:20.19#ibcon#about to read 3, iclass 20, count 0 2006.257.23:20:20.23#ibcon#read 3, iclass 20, count 0 2006.257.23:20:20.23#ibcon#about to read 4, iclass 20, count 0 2006.257.23:20:20.23#ibcon#read 4, iclass 20, count 0 2006.257.23:20:20.23#ibcon#about to read 5, iclass 20, count 0 2006.257.23:20:20.23#ibcon#read 5, iclass 20, count 0 2006.257.23:20:20.23#ibcon#about to read 6, iclass 20, count 0 2006.257.23:20:20.23#ibcon#read 6, iclass 20, count 0 2006.257.23:20:20.23#ibcon#end of sib2, iclass 20, count 0 2006.257.23:20:20.23#ibcon#*after write, iclass 20, count 0 2006.257.23:20:20.23#ibcon#*before return 0, iclass 20, count 0 2006.257.23:20:20.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:20:20.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:20:20.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:20:20.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:20:20.23$vck44/vb=1,4 2006.257.23:20:20.23#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.23:20:20.23#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.23:20:20.23#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:20.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:20:20.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:20:20.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:20:20.23#ibcon#enter wrdev, iclass 22, count 2 2006.257.23:20:20.23#ibcon#first serial, iclass 22, count 2 2006.257.23:20:20.23#ibcon#enter sib2, iclass 22, count 2 2006.257.23:20:20.23#ibcon#flushed, iclass 22, count 2 2006.257.23:20:20.23#ibcon#about to write, iclass 22, count 2 2006.257.23:20:20.23#ibcon#wrote, iclass 22, count 2 2006.257.23:20:20.23#ibcon#about to read 3, iclass 22, count 2 2006.257.23:20:20.25#ibcon#read 3, iclass 22, count 2 2006.257.23:20:20.25#ibcon#about to read 4, iclass 22, count 2 2006.257.23:20:20.25#ibcon#read 4, iclass 22, count 2 2006.257.23:20:20.25#ibcon#about to read 5, iclass 22, count 2 2006.257.23:20:20.25#ibcon#read 5, iclass 22, count 2 2006.257.23:20:20.25#ibcon#about to read 6, iclass 22, count 2 2006.257.23:20:20.25#ibcon#read 6, iclass 22, count 2 2006.257.23:20:20.25#ibcon#end of sib2, iclass 22, count 2 2006.257.23:20:20.25#ibcon#*mode == 0, iclass 22, count 2 2006.257.23:20:20.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.23:20:20.25#ibcon#[27=AT01-04\r\n] 2006.257.23:20:20.25#ibcon#*before write, iclass 22, count 2 2006.257.23:20:20.25#ibcon#enter sib2, iclass 22, count 2 2006.257.23:20:20.25#ibcon#flushed, iclass 22, count 2 2006.257.23:20:20.25#ibcon#about to write, iclass 22, count 2 2006.257.23:20:20.25#ibcon#wrote, iclass 22, count 2 2006.257.23:20:20.25#ibcon#about to read 3, iclass 22, count 2 2006.257.23:20:20.28#ibcon#read 3, iclass 22, count 2 2006.257.23:20:20.28#ibcon#about to read 4, iclass 22, count 2 2006.257.23:20:20.28#ibcon#read 4, iclass 22, count 2 2006.257.23:20:20.28#ibcon#about to read 5, iclass 22, count 2 2006.257.23:20:20.28#ibcon#read 5, iclass 22, count 2 2006.257.23:20:20.28#ibcon#about to read 6, iclass 22, count 2 2006.257.23:20:20.28#ibcon#read 6, iclass 22, count 2 2006.257.23:20:20.28#ibcon#end of sib2, iclass 22, count 2 2006.257.23:20:20.28#ibcon#*after write, iclass 22, count 2 2006.257.23:20:20.28#ibcon#*before return 0, iclass 22, count 2 2006.257.23:20:20.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:20:20.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:20:20.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.23:20:20.28#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:20.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:20:20.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:20:20.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:20:20.40#ibcon#enter wrdev, iclass 22, count 0 2006.257.23:20:20.40#ibcon#first serial, iclass 22, count 0 2006.257.23:20:20.40#ibcon#enter sib2, iclass 22, count 0 2006.257.23:20:20.40#ibcon#flushed, iclass 22, count 0 2006.257.23:20:20.40#ibcon#about to write, iclass 22, count 0 2006.257.23:20:20.40#ibcon#wrote, iclass 22, count 0 2006.257.23:20:20.40#ibcon#about to read 3, iclass 22, count 0 2006.257.23:20:20.42#ibcon#read 3, iclass 22, count 0 2006.257.23:20:20.42#ibcon#about to read 4, iclass 22, count 0 2006.257.23:20:20.42#ibcon#read 4, iclass 22, count 0 2006.257.23:20:20.42#ibcon#about to read 5, iclass 22, count 0 2006.257.23:20:20.42#ibcon#read 5, iclass 22, count 0 2006.257.23:20:20.42#ibcon#about to read 6, iclass 22, count 0 2006.257.23:20:20.42#ibcon#read 6, iclass 22, count 0 2006.257.23:20:20.42#ibcon#end of sib2, iclass 22, count 0 2006.257.23:20:20.42#ibcon#*mode == 0, iclass 22, count 0 2006.257.23:20:20.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.23:20:20.42#ibcon#[27=USB\r\n] 2006.257.23:20:20.42#ibcon#*before write, iclass 22, count 0 2006.257.23:20:20.42#ibcon#enter sib2, iclass 22, count 0 2006.257.23:20:20.42#ibcon#flushed, iclass 22, count 0 2006.257.23:20:20.42#ibcon#about to write, iclass 22, count 0 2006.257.23:20:20.42#ibcon#wrote, iclass 22, count 0 2006.257.23:20:20.42#ibcon#about to read 3, iclass 22, count 0 2006.257.23:20:20.45#ibcon#read 3, iclass 22, count 0 2006.257.23:20:20.45#ibcon#about to read 4, iclass 22, count 0 2006.257.23:20:20.45#ibcon#read 4, iclass 22, count 0 2006.257.23:20:20.45#ibcon#about to read 5, iclass 22, count 0 2006.257.23:20:20.45#ibcon#read 5, iclass 22, count 0 2006.257.23:20:20.45#ibcon#about to read 6, iclass 22, count 0 2006.257.23:20:20.45#ibcon#read 6, iclass 22, count 0 2006.257.23:20:20.45#ibcon#end of sib2, iclass 22, count 0 2006.257.23:20:20.45#ibcon#*after write, iclass 22, count 0 2006.257.23:20:20.45#ibcon#*before return 0, iclass 22, count 0 2006.257.23:20:20.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:20:20.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:20:20.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.23:20:20.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.23:20:20.45$vck44/vblo=2,634.99 2006.257.23:20:20.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.23:20:20.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.23:20:20.45#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:20.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:20.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:20.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:20.45#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:20:20.45#ibcon#first serial, iclass 24, count 0 2006.257.23:20:20.45#ibcon#enter sib2, iclass 24, count 0 2006.257.23:20:20.45#ibcon#flushed, iclass 24, count 0 2006.257.23:20:20.45#ibcon#about to write, iclass 24, count 0 2006.257.23:20:20.45#ibcon#wrote, iclass 24, count 0 2006.257.23:20:20.45#ibcon#about to read 3, iclass 24, count 0 2006.257.23:20:20.47#ibcon#read 3, iclass 24, count 0 2006.257.23:20:20.47#ibcon#about to read 4, iclass 24, count 0 2006.257.23:20:20.47#ibcon#read 4, iclass 24, count 0 2006.257.23:20:20.47#ibcon#about to read 5, iclass 24, count 0 2006.257.23:20:20.47#ibcon#read 5, iclass 24, count 0 2006.257.23:20:20.47#ibcon#about to read 6, iclass 24, count 0 2006.257.23:20:20.47#ibcon#read 6, iclass 24, count 0 2006.257.23:20:20.47#ibcon#end of sib2, iclass 24, count 0 2006.257.23:20:20.47#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:20:20.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:20:20.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:20:20.47#ibcon#*before write, iclass 24, count 0 2006.257.23:20:20.47#ibcon#enter sib2, iclass 24, count 0 2006.257.23:20:20.47#ibcon#flushed, iclass 24, count 0 2006.257.23:20:20.47#ibcon#about to write, iclass 24, count 0 2006.257.23:20:20.47#ibcon#wrote, iclass 24, count 0 2006.257.23:20:20.47#ibcon#about to read 3, iclass 24, count 0 2006.257.23:20:20.51#ibcon#read 3, iclass 24, count 0 2006.257.23:20:20.51#ibcon#about to read 4, iclass 24, count 0 2006.257.23:20:20.51#ibcon#read 4, iclass 24, count 0 2006.257.23:20:20.51#ibcon#about to read 5, iclass 24, count 0 2006.257.23:20:20.51#ibcon#read 5, iclass 24, count 0 2006.257.23:20:20.51#ibcon#about to read 6, iclass 24, count 0 2006.257.23:20:20.51#ibcon#read 6, iclass 24, count 0 2006.257.23:20:20.51#ibcon#end of sib2, iclass 24, count 0 2006.257.23:20:20.51#ibcon#*after write, iclass 24, count 0 2006.257.23:20:20.51#ibcon#*before return 0, iclass 24, count 0 2006.257.23:20:20.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:20.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:20:20.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:20:20.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:20:20.51$vck44/vb=2,5 2006.257.23:20:20.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.23:20:20.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.23:20:20.51#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:20.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:20.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:20.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:20.57#ibcon#enter wrdev, iclass 26, count 2 2006.257.23:20:20.57#ibcon#first serial, iclass 26, count 2 2006.257.23:20:20.57#ibcon#enter sib2, iclass 26, count 2 2006.257.23:20:20.57#ibcon#flushed, iclass 26, count 2 2006.257.23:20:20.57#ibcon#about to write, iclass 26, count 2 2006.257.23:20:20.57#ibcon#wrote, iclass 26, count 2 2006.257.23:20:20.57#ibcon#about to read 3, iclass 26, count 2 2006.257.23:20:20.59#ibcon#read 3, iclass 26, count 2 2006.257.23:20:20.59#ibcon#about to read 4, iclass 26, count 2 2006.257.23:20:20.59#ibcon#read 4, iclass 26, count 2 2006.257.23:20:20.59#ibcon#about to read 5, iclass 26, count 2 2006.257.23:20:20.59#ibcon#read 5, iclass 26, count 2 2006.257.23:20:20.59#ibcon#about to read 6, iclass 26, count 2 2006.257.23:20:20.59#ibcon#read 6, iclass 26, count 2 2006.257.23:20:20.59#ibcon#end of sib2, iclass 26, count 2 2006.257.23:20:20.59#ibcon#*mode == 0, iclass 26, count 2 2006.257.23:20:20.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.23:20:20.59#ibcon#[27=AT02-05\r\n] 2006.257.23:20:20.59#ibcon#*before write, iclass 26, count 2 2006.257.23:20:20.59#ibcon#enter sib2, iclass 26, count 2 2006.257.23:20:20.59#ibcon#flushed, iclass 26, count 2 2006.257.23:20:20.59#ibcon#about to write, iclass 26, count 2 2006.257.23:20:20.59#ibcon#wrote, iclass 26, count 2 2006.257.23:20:20.59#ibcon#about to read 3, iclass 26, count 2 2006.257.23:20:20.62#ibcon#read 3, iclass 26, count 2 2006.257.23:20:20.62#ibcon#about to read 4, iclass 26, count 2 2006.257.23:20:20.62#ibcon#read 4, iclass 26, count 2 2006.257.23:20:20.62#ibcon#about to read 5, iclass 26, count 2 2006.257.23:20:20.62#ibcon#read 5, iclass 26, count 2 2006.257.23:20:20.62#ibcon#about to read 6, iclass 26, count 2 2006.257.23:20:20.62#ibcon#read 6, iclass 26, count 2 2006.257.23:20:20.62#ibcon#end of sib2, iclass 26, count 2 2006.257.23:20:20.62#ibcon#*after write, iclass 26, count 2 2006.257.23:20:20.62#ibcon#*before return 0, iclass 26, count 2 2006.257.23:20:20.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:20.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:20:20.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.23:20:20.62#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:20.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:20.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:20.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:20.74#ibcon#enter wrdev, iclass 26, count 0 2006.257.23:20:20.74#ibcon#first serial, iclass 26, count 0 2006.257.23:20:20.74#ibcon#enter sib2, iclass 26, count 0 2006.257.23:20:20.74#ibcon#flushed, iclass 26, count 0 2006.257.23:20:20.74#ibcon#about to write, iclass 26, count 0 2006.257.23:20:20.74#ibcon#wrote, iclass 26, count 0 2006.257.23:20:20.74#ibcon#about to read 3, iclass 26, count 0 2006.257.23:20:20.76#ibcon#read 3, iclass 26, count 0 2006.257.23:20:20.76#ibcon#about to read 4, iclass 26, count 0 2006.257.23:20:20.76#ibcon#read 4, iclass 26, count 0 2006.257.23:20:20.76#ibcon#about to read 5, iclass 26, count 0 2006.257.23:20:20.76#ibcon#read 5, iclass 26, count 0 2006.257.23:20:20.76#ibcon#about to read 6, iclass 26, count 0 2006.257.23:20:20.76#ibcon#read 6, iclass 26, count 0 2006.257.23:20:20.76#ibcon#end of sib2, iclass 26, count 0 2006.257.23:20:20.76#ibcon#*mode == 0, iclass 26, count 0 2006.257.23:20:20.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.23:20:20.76#ibcon#[27=USB\r\n] 2006.257.23:20:20.76#ibcon#*before write, iclass 26, count 0 2006.257.23:20:20.76#ibcon#enter sib2, iclass 26, count 0 2006.257.23:20:20.76#ibcon#flushed, iclass 26, count 0 2006.257.23:20:20.76#ibcon#about to write, iclass 26, count 0 2006.257.23:20:20.76#ibcon#wrote, iclass 26, count 0 2006.257.23:20:20.76#ibcon#about to read 3, iclass 26, count 0 2006.257.23:20:20.79#ibcon#read 3, iclass 26, count 0 2006.257.23:20:20.79#ibcon#about to read 4, iclass 26, count 0 2006.257.23:20:20.79#ibcon#read 4, iclass 26, count 0 2006.257.23:20:20.79#ibcon#about to read 5, iclass 26, count 0 2006.257.23:20:20.79#ibcon#read 5, iclass 26, count 0 2006.257.23:20:20.79#ibcon#about to read 6, iclass 26, count 0 2006.257.23:20:20.79#ibcon#read 6, iclass 26, count 0 2006.257.23:20:20.79#ibcon#end of sib2, iclass 26, count 0 2006.257.23:20:20.79#ibcon#*after write, iclass 26, count 0 2006.257.23:20:20.79#ibcon#*before return 0, iclass 26, count 0 2006.257.23:20:20.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:20.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:20:20.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.23:20:20.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.23:20:20.79$vck44/vblo=3,649.99 2006.257.23:20:20.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.23:20:20.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.23:20:20.79#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:20.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:20.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:20.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:20.79#ibcon#enter wrdev, iclass 28, count 0 2006.257.23:20:20.79#ibcon#first serial, iclass 28, count 0 2006.257.23:20:20.79#ibcon#enter sib2, iclass 28, count 0 2006.257.23:20:20.79#ibcon#flushed, iclass 28, count 0 2006.257.23:20:20.79#ibcon#about to write, iclass 28, count 0 2006.257.23:20:20.79#ibcon#wrote, iclass 28, count 0 2006.257.23:20:20.79#ibcon#about to read 3, iclass 28, count 0 2006.257.23:20:20.81#ibcon#read 3, iclass 28, count 0 2006.257.23:20:20.81#ibcon#about to read 4, iclass 28, count 0 2006.257.23:20:20.81#ibcon#read 4, iclass 28, count 0 2006.257.23:20:20.81#ibcon#about to read 5, iclass 28, count 0 2006.257.23:20:20.81#ibcon#read 5, iclass 28, count 0 2006.257.23:20:20.81#ibcon#about to read 6, iclass 28, count 0 2006.257.23:20:20.81#ibcon#read 6, iclass 28, count 0 2006.257.23:20:20.81#ibcon#end of sib2, iclass 28, count 0 2006.257.23:20:20.81#ibcon#*mode == 0, iclass 28, count 0 2006.257.23:20:20.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.23:20:20.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:20:20.81#ibcon#*before write, iclass 28, count 0 2006.257.23:20:20.81#ibcon#enter sib2, iclass 28, count 0 2006.257.23:20:20.81#ibcon#flushed, iclass 28, count 0 2006.257.23:20:20.81#ibcon#about to write, iclass 28, count 0 2006.257.23:20:20.81#ibcon#wrote, iclass 28, count 0 2006.257.23:20:20.81#ibcon#about to read 3, iclass 28, count 0 2006.257.23:20:20.85#ibcon#read 3, iclass 28, count 0 2006.257.23:20:20.85#ibcon#about to read 4, iclass 28, count 0 2006.257.23:20:20.85#ibcon#read 4, iclass 28, count 0 2006.257.23:20:20.85#ibcon#about to read 5, iclass 28, count 0 2006.257.23:20:20.85#ibcon#read 5, iclass 28, count 0 2006.257.23:20:20.85#ibcon#about to read 6, iclass 28, count 0 2006.257.23:20:20.85#ibcon#read 6, iclass 28, count 0 2006.257.23:20:20.85#ibcon#end of sib2, iclass 28, count 0 2006.257.23:20:20.85#ibcon#*after write, iclass 28, count 0 2006.257.23:20:20.85#ibcon#*before return 0, iclass 28, count 0 2006.257.23:20:20.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:20.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:20:20.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.23:20:20.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.23:20:20.85$vck44/vb=3,4 2006.257.23:20:20.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.23:20:20.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.23:20:20.85#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:20.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:20.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:20.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:20.91#ibcon#enter wrdev, iclass 30, count 2 2006.257.23:20:20.91#ibcon#first serial, iclass 30, count 2 2006.257.23:20:20.91#ibcon#enter sib2, iclass 30, count 2 2006.257.23:20:20.91#ibcon#flushed, iclass 30, count 2 2006.257.23:20:20.91#ibcon#about to write, iclass 30, count 2 2006.257.23:20:20.91#ibcon#wrote, iclass 30, count 2 2006.257.23:20:20.91#ibcon#about to read 3, iclass 30, count 2 2006.257.23:20:20.93#ibcon#read 3, iclass 30, count 2 2006.257.23:20:20.93#ibcon#about to read 4, iclass 30, count 2 2006.257.23:20:20.93#ibcon#read 4, iclass 30, count 2 2006.257.23:20:20.93#ibcon#about to read 5, iclass 30, count 2 2006.257.23:20:20.93#ibcon#read 5, iclass 30, count 2 2006.257.23:20:20.93#ibcon#about to read 6, iclass 30, count 2 2006.257.23:20:20.93#ibcon#read 6, iclass 30, count 2 2006.257.23:20:20.93#ibcon#end of sib2, iclass 30, count 2 2006.257.23:20:20.93#ibcon#*mode == 0, iclass 30, count 2 2006.257.23:20:20.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.23:20:20.93#ibcon#[27=AT03-04\r\n] 2006.257.23:20:20.93#ibcon#*before write, iclass 30, count 2 2006.257.23:20:20.93#ibcon#enter sib2, iclass 30, count 2 2006.257.23:20:20.93#ibcon#flushed, iclass 30, count 2 2006.257.23:20:20.93#ibcon#about to write, iclass 30, count 2 2006.257.23:20:20.93#ibcon#wrote, iclass 30, count 2 2006.257.23:20:20.93#ibcon#about to read 3, iclass 30, count 2 2006.257.23:20:20.96#ibcon#read 3, iclass 30, count 2 2006.257.23:20:20.96#ibcon#about to read 4, iclass 30, count 2 2006.257.23:20:20.96#ibcon#read 4, iclass 30, count 2 2006.257.23:20:20.96#ibcon#about to read 5, iclass 30, count 2 2006.257.23:20:20.96#ibcon#read 5, iclass 30, count 2 2006.257.23:20:20.96#ibcon#about to read 6, iclass 30, count 2 2006.257.23:20:20.96#ibcon#read 6, iclass 30, count 2 2006.257.23:20:20.96#ibcon#end of sib2, iclass 30, count 2 2006.257.23:20:20.96#ibcon#*after write, iclass 30, count 2 2006.257.23:20:20.96#ibcon#*before return 0, iclass 30, count 2 2006.257.23:20:20.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:20.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:20:20.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.23:20:20.96#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:20.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:21.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:21.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:21.08#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:20:21.08#ibcon#first serial, iclass 30, count 0 2006.257.23:20:21.08#ibcon#enter sib2, iclass 30, count 0 2006.257.23:20:21.08#ibcon#flushed, iclass 30, count 0 2006.257.23:20:21.08#ibcon#about to write, iclass 30, count 0 2006.257.23:20:21.08#ibcon#wrote, iclass 30, count 0 2006.257.23:20:21.08#ibcon#about to read 3, iclass 30, count 0 2006.257.23:20:21.10#ibcon#read 3, iclass 30, count 0 2006.257.23:20:21.10#ibcon#about to read 4, iclass 30, count 0 2006.257.23:20:21.10#ibcon#read 4, iclass 30, count 0 2006.257.23:20:21.10#ibcon#about to read 5, iclass 30, count 0 2006.257.23:20:21.10#ibcon#read 5, iclass 30, count 0 2006.257.23:20:21.10#ibcon#about to read 6, iclass 30, count 0 2006.257.23:20:21.10#ibcon#read 6, iclass 30, count 0 2006.257.23:20:21.10#ibcon#end of sib2, iclass 30, count 0 2006.257.23:20:21.10#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:20:21.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:20:21.10#ibcon#[27=USB\r\n] 2006.257.23:20:21.10#ibcon#*before write, iclass 30, count 0 2006.257.23:20:21.10#ibcon#enter sib2, iclass 30, count 0 2006.257.23:20:21.10#ibcon#flushed, iclass 30, count 0 2006.257.23:20:21.10#ibcon#about to write, iclass 30, count 0 2006.257.23:20:21.10#ibcon#wrote, iclass 30, count 0 2006.257.23:20:21.10#ibcon#about to read 3, iclass 30, count 0 2006.257.23:20:21.13#ibcon#read 3, iclass 30, count 0 2006.257.23:20:21.13#ibcon#about to read 4, iclass 30, count 0 2006.257.23:20:21.13#ibcon#read 4, iclass 30, count 0 2006.257.23:20:21.13#ibcon#about to read 5, iclass 30, count 0 2006.257.23:20:21.13#ibcon#read 5, iclass 30, count 0 2006.257.23:20:21.13#ibcon#about to read 6, iclass 30, count 0 2006.257.23:20:21.13#ibcon#read 6, iclass 30, count 0 2006.257.23:20:21.13#ibcon#end of sib2, iclass 30, count 0 2006.257.23:20:21.13#ibcon#*after write, iclass 30, count 0 2006.257.23:20:21.13#ibcon#*before return 0, iclass 30, count 0 2006.257.23:20:21.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:21.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:20:21.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:20:21.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:20:21.13$vck44/vblo=4,679.99 2006.257.23:20:21.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.23:20:21.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.23:20:21.13#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:21.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:21.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:21.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:21.13#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:20:21.13#ibcon#first serial, iclass 32, count 0 2006.257.23:20:21.13#ibcon#enter sib2, iclass 32, count 0 2006.257.23:20:21.13#ibcon#flushed, iclass 32, count 0 2006.257.23:20:21.13#ibcon#about to write, iclass 32, count 0 2006.257.23:20:21.13#ibcon#wrote, iclass 32, count 0 2006.257.23:20:21.13#ibcon#about to read 3, iclass 32, count 0 2006.257.23:20:21.15#ibcon#read 3, iclass 32, count 0 2006.257.23:20:21.15#ibcon#about to read 4, iclass 32, count 0 2006.257.23:20:21.15#ibcon#read 4, iclass 32, count 0 2006.257.23:20:21.15#ibcon#about to read 5, iclass 32, count 0 2006.257.23:20:21.15#ibcon#read 5, iclass 32, count 0 2006.257.23:20:21.15#ibcon#about to read 6, iclass 32, count 0 2006.257.23:20:21.15#ibcon#read 6, iclass 32, count 0 2006.257.23:20:21.15#ibcon#end of sib2, iclass 32, count 0 2006.257.23:20:21.15#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:20:21.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:20:21.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:20:21.15#ibcon#*before write, iclass 32, count 0 2006.257.23:20:21.15#ibcon#enter sib2, iclass 32, count 0 2006.257.23:20:21.15#ibcon#flushed, iclass 32, count 0 2006.257.23:20:21.15#ibcon#about to write, iclass 32, count 0 2006.257.23:20:21.15#ibcon#wrote, iclass 32, count 0 2006.257.23:20:21.15#ibcon#about to read 3, iclass 32, count 0 2006.257.23:20:21.19#ibcon#read 3, iclass 32, count 0 2006.257.23:20:21.19#ibcon#about to read 4, iclass 32, count 0 2006.257.23:20:21.19#ibcon#read 4, iclass 32, count 0 2006.257.23:20:21.19#ibcon#about to read 5, iclass 32, count 0 2006.257.23:20:21.19#ibcon#read 5, iclass 32, count 0 2006.257.23:20:21.19#ibcon#about to read 6, iclass 32, count 0 2006.257.23:20:21.19#ibcon#read 6, iclass 32, count 0 2006.257.23:20:21.19#ibcon#end of sib2, iclass 32, count 0 2006.257.23:20:21.19#ibcon#*after write, iclass 32, count 0 2006.257.23:20:21.19#ibcon#*before return 0, iclass 32, count 0 2006.257.23:20:21.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:21.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:20:21.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:20:21.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:20:21.19$vck44/vb=4,5 2006.257.23:20:21.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.23:20:21.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.23:20:21.19#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:21.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:21.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:21.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:21.25#ibcon#enter wrdev, iclass 34, count 2 2006.257.23:20:21.25#ibcon#first serial, iclass 34, count 2 2006.257.23:20:21.25#ibcon#enter sib2, iclass 34, count 2 2006.257.23:20:21.25#ibcon#flushed, iclass 34, count 2 2006.257.23:20:21.25#ibcon#about to write, iclass 34, count 2 2006.257.23:20:21.25#ibcon#wrote, iclass 34, count 2 2006.257.23:20:21.25#ibcon#about to read 3, iclass 34, count 2 2006.257.23:20:21.27#ibcon#read 3, iclass 34, count 2 2006.257.23:20:21.27#ibcon#about to read 4, iclass 34, count 2 2006.257.23:20:21.27#ibcon#read 4, iclass 34, count 2 2006.257.23:20:21.27#ibcon#about to read 5, iclass 34, count 2 2006.257.23:20:21.27#ibcon#read 5, iclass 34, count 2 2006.257.23:20:21.27#ibcon#about to read 6, iclass 34, count 2 2006.257.23:20:21.27#ibcon#read 6, iclass 34, count 2 2006.257.23:20:21.27#ibcon#end of sib2, iclass 34, count 2 2006.257.23:20:21.27#ibcon#*mode == 0, iclass 34, count 2 2006.257.23:20:21.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.23:20:21.27#ibcon#[27=AT04-05\r\n] 2006.257.23:20:21.27#ibcon#*before write, iclass 34, count 2 2006.257.23:20:21.27#ibcon#enter sib2, iclass 34, count 2 2006.257.23:20:21.27#ibcon#flushed, iclass 34, count 2 2006.257.23:20:21.27#ibcon#about to write, iclass 34, count 2 2006.257.23:20:21.27#ibcon#wrote, iclass 34, count 2 2006.257.23:20:21.27#ibcon#about to read 3, iclass 34, count 2 2006.257.23:20:21.30#ibcon#read 3, iclass 34, count 2 2006.257.23:20:21.30#ibcon#about to read 4, iclass 34, count 2 2006.257.23:20:21.30#ibcon#read 4, iclass 34, count 2 2006.257.23:20:21.30#ibcon#about to read 5, iclass 34, count 2 2006.257.23:20:21.30#ibcon#read 5, iclass 34, count 2 2006.257.23:20:21.30#ibcon#about to read 6, iclass 34, count 2 2006.257.23:20:21.30#ibcon#read 6, iclass 34, count 2 2006.257.23:20:21.30#ibcon#end of sib2, iclass 34, count 2 2006.257.23:20:21.30#ibcon#*after write, iclass 34, count 2 2006.257.23:20:21.30#ibcon#*before return 0, iclass 34, count 2 2006.257.23:20:21.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:21.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:20:21.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.23:20:21.30#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:21.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:21.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:21.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:21.42#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:20:21.42#ibcon#first serial, iclass 34, count 0 2006.257.23:20:21.42#ibcon#enter sib2, iclass 34, count 0 2006.257.23:20:21.42#ibcon#flushed, iclass 34, count 0 2006.257.23:20:21.42#ibcon#about to write, iclass 34, count 0 2006.257.23:20:21.42#ibcon#wrote, iclass 34, count 0 2006.257.23:20:21.42#ibcon#about to read 3, iclass 34, count 0 2006.257.23:20:21.44#ibcon#read 3, iclass 34, count 0 2006.257.23:20:21.44#ibcon#about to read 4, iclass 34, count 0 2006.257.23:20:21.44#ibcon#read 4, iclass 34, count 0 2006.257.23:20:21.44#ibcon#about to read 5, iclass 34, count 0 2006.257.23:20:21.44#ibcon#read 5, iclass 34, count 0 2006.257.23:20:21.44#ibcon#about to read 6, iclass 34, count 0 2006.257.23:20:21.44#ibcon#read 6, iclass 34, count 0 2006.257.23:20:21.44#ibcon#end of sib2, iclass 34, count 0 2006.257.23:20:21.44#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:20:21.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:20:21.44#ibcon#[27=USB\r\n] 2006.257.23:20:21.44#ibcon#*before write, iclass 34, count 0 2006.257.23:20:21.44#ibcon#enter sib2, iclass 34, count 0 2006.257.23:20:21.44#ibcon#flushed, iclass 34, count 0 2006.257.23:20:21.44#ibcon#about to write, iclass 34, count 0 2006.257.23:20:21.44#ibcon#wrote, iclass 34, count 0 2006.257.23:20:21.44#ibcon#about to read 3, iclass 34, count 0 2006.257.23:20:21.47#ibcon#read 3, iclass 34, count 0 2006.257.23:20:21.47#ibcon#about to read 4, iclass 34, count 0 2006.257.23:20:21.47#ibcon#read 4, iclass 34, count 0 2006.257.23:20:21.47#ibcon#about to read 5, iclass 34, count 0 2006.257.23:20:21.47#ibcon#read 5, iclass 34, count 0 2006.257.23:20:21.47#ibcon#about to read 6, iclass 34, count 0 2006.257.23:20:21.47#ibcon#read 6, iclass 34, count 0 2006.257.23:20:21.47#ibcon#end of sib2, iclass 34, count 0 2006.257.23:20:21.47#ibcon#*after write, iclass 34, count 0 2006.257.23:20:21.47#ibcon#*before return 0, iclass 34, count 0 2006.257.23:20:21.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:21.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:20:21.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:20:21.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:20:21.47$vck44/vblo=5,709.99 2006.257.23:20:21.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.23:20:21.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.23:20:21.47#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:21.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:21.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:21.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:21.47#ibcon#enter wrdev, iclass 36, count 0 2006.257.23:20:21.47#ibcon#first serial, iclass 36, count 0 2006.257.23:20:21.47#ibcon#enter sib2, iclass 36, count 0 2006.257.23:20:21.47#ibcon#flushed, iclass 36, count 0 2006.257.23:20:21.47#ibcon#about to write, iclass 36, count 0 2006.257.23:20:21.47#ibcon#wrote, iclass 36, count 0 2006.257.23:20:21.47#ibcon#about to read 3, iclass 36, count 0 2006.257.23:20:21.49#ibcon#read 3, iclass 36, count 0 2006.257.23:20:21.49#ibcon#about to read 4, iclass 36, count 0 2006.257.23:20:21.49#ibcon#read 4, iclass 36, count 0 2006.257.23:20:21.49#ibcon#about to read 5, iclass 36, count 0 2006.257.23:20:21.49#ibcon#read 5, iclass 36, count 0 2006.257.23:20:21.49#ibcon#about to read 6, iclass 36, count 0 2006.257.23:20:21.49#ibcon#read 6, iclass 36, count 0 2006.257.23:20:21.49#ibcon#end of sib2, iclass 36, count 0 2006.257.23:20:21.49#ibcon#*mode == 0, iclass 36, count 0 2006.257.23:20:21.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.23:20:21.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:20:21.49#ibcon#*before write, iclass 36, count 0 2006.257.23:20:21.49#ibcon#enter sib2, iclass 36, count 0 2006.257.23:20:21.49#ibcon#flushed, iclass 36, count 0 2006.257.23:20:21.49#ibcon#about to write, iclass 36, count 0 2006.257.23:20:21.49#ibcon#wrote, iclass 36, count 0 2006.257.23:20:21.49#ibcon#about to read 3, iclass 36, count 0 2006.257.23:20:21.53#ibcon#read 3, iclass 36, count 0 2006.257.23:20:21.53#ibcon#about to read 4, iclass 36, count 0 2006.257.23:20:21.53#ibcon#read 4, iclass 36, count 0 2006.257.23:20:21.53#ibcon#about to read 5, iclass 36, count 0 2006.257.23:20:21.53#ibcon#read 5, iclass 36, count 0 2006.257.23:20:21.53#ibcon#about to read 6, iclass 36, count 0 2006.257.23:20:21.53#ibcon#read 6, iclass 36, count 0 2006.257.23:20:21.53#ibcon#end of sib2, iclass 36, count 0 2006.257.23:20:21.53#ibcon#*after write, iclass 36, count 0 2006.257.23:20:21.53#ibcon#*before return 0, iclass 36, count 0 2006.257.23:20:21.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:21.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:20:21.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.23:20:21.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.23:20:21.53$vck44/vb=5,4 2006.257.23:20:21.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.23:20:21.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.23:20:21.53#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:21.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:21.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:21.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:21.59#ibcon#enter wrdev, iclass 38, count 2 2006.257.23:20:21.59#ibcon#first serial, iclass 38, count 2 2006.257.23:20:21.59#ibcon#enter sib2, iclass 38, count 2 2006.257.23:20:21.59#ibcon#flushed, iclass 38, count 2 2006.257.23:20:21.59#ibcon#about to write, iclass 38, count 2 2006.257.23:20:21.59#ibcon#wrote, iclass 38, count 2 2006.257.23:20:21.59#ibcon#about to read 3, iclass 38, count 2 2006.257.23:20:21.61#ibcon#read 3, iclass 38, count 2 2006.257.23:20:21.61#ibcon#about to read 4, iclass 38, count 2 2006.257.23:20:21.61#ibcon#read 4, iclass 38, count 2 2006.257.23:20:21.61#ibcon#about to read 5, iclass 38, count 2 2006.257.23:20:21.61#ibcon#read 5, iclass 38, count 2 2006.257.23:20:21.61#ibcon#about to read 6, iclass 38, count 2 2006.257.23:20:21.61#ibcon#read 6, iclass 38, count 2 2006.257.23:20:21.61#ibcon#end of sib2, iclass 38, count 2 2006.257.23:20:21.61#ibcon#*mode == 0, iclass 38, count 2 2006.257.23:20:21.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.23:20:21.61#ibcon#[27=AT05-04\r\n] 2006.257.23:20:21.61#ibcon#*before write, iclass 38, count 2 2006.257.23:20:21.61#ibcon#enter sib2, iclass 38, count 2 2006.257.23:20:21.61#ibcon#flushed, iclass 38, count 2 2006.257.23:20:21.61#ibcon#about to write, iclass 38, count 2 2006.257.23:20:21.61#ibcon#wrote, iclass 38, count 2 2006.257.23:20:21.61#ibcon#about to read 3, iclass 38, count 2 2006.257.23:20:21.64#ibcon#read 3, iclass 38, count 2 2006.257.23:20:21.64#ibcon#about to read 4, iclass 38, count 2 2006.257.23:20:21.64#ibcon#read 4, iclass 38, count 2 2006.257.23:20:21.64#ibcon#about to read 5, iclass 38, count 2 2006.257.23:20:21.64#ibcon#read 5, iclass 38, count 2 2006.257.23:20:21.64#ibcon#about to read 6, iclass 38, count 2 2006.257.23:20:21.64#ibcon#read 6, iclass 38, count 2 2006.257.23:20:21.64#ibcon#end of sib2, iclass 38, count 2 2006.257.23:20:21.64#ibcon#*after write, iclass 38, count 2 2006.257.23:20:21.64#ibcon#*before return 0, iclass 38, count 2 2006.257.23:20:21.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:21.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:20:21.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.23:20:21.64#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:21.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:21.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:21.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:21.76#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:20:21.76#ibcon#first serial, iclass 38, count 0 2006.257.23:20:21.76#ibcon#enter sib2, iclass 38, count 0 2006.257.23:20:21.76#ibcon#flushed, iclass 38, count 0 2006.257.23:20:21.76#ibcon#about to write, iclass 38, count 0 2006.257.23:20:21.76#ibcon#wrote, iclass 38, count 0 2006.257.23:20:21.76#ibcon#about to read 3, iclass 38, count 0 2006.257.23:20:21.78#ibcon#read 3, iclass 38, count 0 2006.257.23:20:21.78#ibcon#about to read 4, iclass 38, count 0 2006.257.23:20:21.78#ibcon#read 4, iclass 38, count 0 2006.257.23:20:21.78#ibcon#about to read 5, iclass 38, count 0 2006.257.23:20:21.78#ibcon#read 5, iclass 38, count 0 2006.257.23:20:21.78#ibcon#about to read 6, iclass 38, count 0 2006.257.23:20:21.78#ibcon#read 6, iclass 38, count 0 2006.257.23:20:21.78#ibcon#end of sib2, iclass 38, count 0 2006.257.23:20:21.78#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:20:21.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:20:21.78#ibcon#[27=USB\r\n] 2006.257.23:20:21.78#ibcon#*before write, iclass 38, count 0 2006.257.23:20:21.78#ibcon#enter sib2, iclass 38, count 0 2006.257.23:20:21.78#ibcon#flushed, iclass 38, count 0 2006.257.23:20:21.78#ibcon#about to write, iclass 38, count 0 2006.257.23:20:21.78#ibcon#wrote, iclass 38, count 0 2006.257.23:20:21.78#ibcon#about to read 3, iclass 38, count 0 2006.257.23:20:21.81#ibcon#read 3, iclass 38, count 0 2006.257.23:20:21.81#ibcon#about to read 4, iclass 38, count 0 2006.257.23:20:21.81#ibcon#read 4, iclass 38, count 0 2006.257.23:20:21.81#ibcon#about to read 5, iclass 38, count 0 2006.257.23:20:21.81#ibcon#read 5, iclass 38, count 0 2006.257.23:20:21.81#ibcon#about to read 6, iclass 38, count 0 2006.257.23:20:21.81#ibcon#read 6, iclass 38, count 0 2006.257.23:20:21.81#ibcon#end of sib2, iclass 38, count 0 2006.257.23:20:21.81#ibcon#*after write, iclass 38, count 0 2006.257.23:20:21.81#ibcon#*before return 0, iclass 38, count 0 2006.257.23:20:21.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:21.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:20:21.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:20:21.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:20:21.81$vck44/vblo=6,719.99 2006.257.23:20:21.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.23:20:21.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.23:20:21.81#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:21.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:21.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:21.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:21.81#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:20:21.81#ibcon#first serial, iclass 40, count 0 2006.257.23:20:21.81#ibcon#enter sib2, iclass 40, count 0 2006.257.23:20:21.81#ibcon#flushed, iclass 40, count 0 2006.257.23:20:21.81#ibcon#about to write, iclass 40, count 0 2006.257.23:20:21.81#ibcon#wrote, iclass 40, count 0 2006.257.23:20:21.81#ibcon#about to read 3, iclass 40, count 0 2006.257.23:20:21.83#ibcon#read 3, iclass 40, count 0 2006.257.23:20:21.83#ibcon#about to read 4, iclass 40, count 0 2006.257.23:20:21.83#ibcon#read 4, iclass 40, count 0 2006.257.23:20:21.83#ibcon#about to read 5, iclass 40, count 0 2006.257.23:20:21.83#ibcon#read 5, iclass 40, count 0 2006.257.23:20:21.83#ibcon#about to read 6, iclass 40, count 0 2006.257.23:20:21.83#ibcon#read 6, iclass 40, count 0 2006.257.23:20:21.83#ibcon#end of sib2, iclass 40, count 0 2006.257.23:20:21.83#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:20:21.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:20:21.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:20:21.83#ibcon#*before write, iclass 40, count 0 2006.257.23:20:21.83#ibcon#enter sib2, iclass 40, count 0 2006.257.23:20:21.83#ibcon#flushed, iclass 40, count 0 2006.257.23:20:21.83#ibcon#about to write, iclass 40, count 0 2006.257.23:20:21.83#ibcon#wrote, iclass 40, count 0 2006.257.23:20:21.83#ibcon#about to read 3, iclass 40, count 0 2006.257.23:20:21.87#ibcon#read 3, iclass 40, count 0 2006.257.23:20:21.87#ibcon#about to read 4, iclass 40, count 0 2006.257.23:20:21.87#ibcon#read 4, iclass 40, count 0 2006.257.23:20:21.87#ibcon#about to read 5, iclass 40, count 0 2006.257.23:20:21.87#ibcon#read 5, iclass 40, count 0 2006.257.23:20:21.87#ibcon#about to read 6, iclass 40, count 0 2006.257.23:20:21.87#ibcon#read 6, iclass 40, count 0 2006.257.23:20:21.87#ibcon#end of sib2, iclass 40, count 0 2006.257.23:20:21.87#ibcon#*after write, iclass 40, count 0 2006.257.23:20:21.87#ibcon#*before return 0, iclass 40, count 0 2006.257.23:20:21.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:21.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:20:21.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:20:21.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:20:21.87$vck44/vb=6,4 2006.257.23:20:21.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.23:20:21.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.23:20:21.87#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:21.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:21.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:21.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:21.93#ibcon#enter wrdev, iclass 4, count 2 2006.257.23:20:21.93#ibcon#first serial, iclass 4, count 2 2006.257.23:20:21.93#ibcon#enter sib2, iclass 4, count 2 2006.257.23:20:21.93#ibcon#flushed, iclass 4, count 2 2006.257.23:20:21.93#ibcon#about to write, iclass 4, count 2 2006.257.23:20:21.93#ibcon#wrote, iclass 4, count 2 2006.257.23:20:21.93#ibcon#about to read 3, iclass 4, count 2 2006.257.23:20:21.95#ibcon#read 3, iclass 4, count 2 2006.257.23:20:21.95#ibcon#about to read 4, iclass 4, count 2 2006.257.23:20:21.95#ibcon#read 4, iclass 4, count 2 2006.257.23:20:21.95#ibcon#about to read 5, iclass 4, count 2 2006.257.23:20:21.95#ibcon#read 5, iclass 4, count 2 2006.257.23:20:21.95#ibcon#about to read 6, iclass 4, count 2 2006.257.23:20:21.95#ibcon#read 6, iclass 4, count 2 2006.257.23:20:21.95#ibcon#end of sib2, iclass 4, count 2 2006.257.23:20:21.95#ibcon#*mode == 0, iclass 4, count 2 2006.257.23:20:21.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.23:20:21.95#ibcon#[27=AT06-04\r\n] 2006.257.23:20:21.95#ibcon#*before write, iclass 4, count 2 2006.257.23:20:21.95#ibcon#enter sib2, iclass 4, count 2 2006.257.23:20:21.95#ibcon#flushed, iclass 4, count 2 2006.257.23:20:21.95#ibcon#about to write, iclass 4, count 2 2006.257.23:20:21.95#ibcon#wrote, iclass 4, count 2 2006.257.23:20:21.95#ibcon#about to read 3, iclass 4, count 2 2006.257.23:20:21.98#ibcon#read 3, iclass 4, count 2 2006.257.23:20:21.98#ibcon#about to read 4, iclass 4, count 2 2006.257.23:20:21.98#ibcon#read 4, iclass 4, count 2 2006.257.23:20:21.98#ibcon#about to read 5, iclass 4, count 2 2006.257.23:20:21.98#ibcon#read 5, iclass 4, count 2 2006.257.23:20:21.98#ibcon#about to read 6, iclass 4, count 2 2006.257.23:20:21.98#ibcon#read 6, iclass 4, count 2 2006.257.23:20:21.98#ibcon#end of sib2, iclass 4, count 2 2006.257.23:20:21.98#ibcon#*after write, iclass 4, count 2 2006.257.23:20:21.98#ibcon#*before return 0, iclass 4, count 2 2006.257.23:20:21.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:21.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:20:21.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.23:20:21.98#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:21.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:22.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:22.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:22.10#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:20:22.10#ibcon#first serial, iclass 4, count 0 2006.257.23:20:22.10#ibcon#enter sib2, iclass 4, count 0 2006.257.23:20:22.10#ibcon#flushed, iclass 4, count 0 2006.257.23:20:22.10#ibcon#about to write, iclass 4, count 0 2006.257.23:20:22.10#ibcon#wrote, iclass 4, count 0 2006.257.23:20:22.10#ibcon#about to read 3, iclass 4, count 0 2006.257.23:20:22.12#ibcon#read 3, iclass 4, count 0 2006.257.23:20:22.12#ibcon#about to read 4, iclass 4, count 0 2006.257.23:20:22.12#ibcon#read 4, iclass 4, count 0 2006.257.23:20:22.12#ibcon#about to read 5, iclass 4, count 0 2006.257.23:20:22.12#ibcon#read 5, iclass 4, count 0 2006.257.23:20:22.12#ibcon#about to read 6, iclass 4, count 0 2006.257.23:20:22.12#ibcon#read 6, iclass 4, count 0 2006.257.23:20:22.12#ibcon#end of sib2, iclass 4, count 0 2006.257.23:20:22.12#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:20:22.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:20:22.12#ibcon#[27=USB\r\n] 2006.257.23:20:22.12#ibcon#*before write, iclass 4, count 0 2006.257.23:20:22.12#ibcon#enter sib2, iclass 4, count 0 2006.257.23:20:22.12#ibcon#flushed, iclass 4, count 0 2006.257.23:20:22.12#ibcon#about to write, iclass 4, count 0 2006.257.23:20:22.12#ibcon#wrote, iclass 4, count 0 2006.257.23:20:22.12#ibcon#about to read 3, iclass 4, count 0 2006.257.23:20:22.15#ibcon#read 3, iclass 4, count 0 2006.257.23:20:22.15#ibcon#about to read 4, iclass 4, count 0 2006.257.23:20:22.15#ibcon#read 4, iclass 4, count 0 2006.257.23:20:22.15#ibcon#about to read 5, iclass 4, count 0 2006.257.23:20:22.15#ibcon#read 5, iclass 4, count 0 2006.257.23:20:22.15#ibcon#about to read 6, iclass 4, count 0 2006.257.23:20:22.15#ibcon#read 6, iclass 4, count 0 2006.257.23:20:22.15#ibcon#end of sib2, iclass 4, count 0 2006.257.23:20:22.15#ibcon#*after write, iclass 4, count 0 2006.257.23:20:22.15#ibcon#*before return 0, iclass 4, count 0 2006.257.23:20:22.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:22.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:20:22.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:20:22.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:20:22.15$vck44/vblo=7,734.99 2006.257.23:20:22.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.23:20:22.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.23:20:22.15#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:22.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:22.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:22.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:22.15#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:20:22.15#ibcon#first serial, iclass 6, count 0 2006.257.23:20:22.15#ibcon#enter sib2, iclass 6, count 0 2006.257.23:20:22.15#ibcon#flushed, iclass 6, count 0 2006.257.23:20:22.15#ibcon#about to write, iclass 6, count 0 2006.257.23:20:22.15#ibcon#wrote, iclass 6, count 0 2006.257.23:20:22.15#ibcon#about to read 3, iclass 6, count 0 2006.257.23:20:22.17#ibcon#read 3, iclass 6, count 0 2006.257.23:20:22.17#ibcon#about to read 4, iclass 6, count 0 2006.257.23:20:22.17#ibcon#read 4, iclass 6, count 0 2006.257.23:20:22.17#ibcon#about to read 5, iclass 6, count 0 2006.257.23:20:22.17#ibcon#read 5, iclass 6, count 0 2006.257.23:20:22.17#ibcon#about to read 6, iclass 6, count 0 2006.257.23:20:22.17#ibcon#read 6, iclass 6, count 0 2006.257.23:20:22.17#ibcon#end of sib2, iclass 6, count 0 2006.257.23:20:22.17#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:20:22.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:20:22.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:20:22.17#ibcon#*before write, iclass 6, count 0 2006.257.23:20:22.17#ibcon#enter sib2, iclass 6, count 0 2006.257.23:20:22.17#ibcon#flushed, iclass 6, count 0 2006.257.23:20:22.17#ibcon#about to write, iclass 6, count 0 2006.257.23:20:22.17#ibcon#wrote, iclass 6, count 0 2006.257.23:20:22.17#ibcon#about to read 3, iclass 6, count 0 2006.257.23:20:22.21#ibcon#read 3, iclass 6, count 0 2006.257.23:20:22.21#ibcon#about to read 4, iclass 6, count 0 2006.257.23:20:22.21#ibcon#read 4, iclass 6, count 0 2006.257.23:20:22.21#ibcon#about to read 5, iclass 6, count 0 2006.257.23:20:22.21#ibcon#read 5, iclass 6, count 0 2006.257.23:20:22.21#ibcon#about to read 6, iclass 6, count 0 2006.257.23:20:22.21#ibcon#read 6, iclass 6, count 0 2006.257.23:20:22.21#ibcon#end of sib2, iclass 6, count 0 2006.257.23:20:22.21#ibcon#*after write, iclass 6, count 0 2006.257.23:20:22.21#ibcon#*before return 0, iclass 6, count 0 2006.257.23:20:22.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:22.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:20:22.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:20:22.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:20:22.21$vck44/vb=7,4 2006.257.23:20:22.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.23:20:22.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.23:20:22.21#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:22.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:22.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:22.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:22.27#ibcon#enter wrdev, iclass 10, count 2 2006.257.23:20:22.27#ibcon#first serial, iclass 10, count 2 2006.257.23:20:22.27#ibcon#enter sib2, iclass 10, count 2 2006.257.23:20:22.27#ibcon#flushed, iclass 10, count 2 2006.257.23:20:22.27#ibcon#about to write, iclass 10, count 2 2006.257.23:20:22.27#ibcon#wrote, iclass 10, count 2 2006.257.23:20:22.27#ibcon#about to read 3, iclass 10, count 2 2006.257.23:20:22.29#ibcon#read 3, iclass 10, count 2 2006.257.23:20:22.29#ibcon#about to read 4, iclass 10, count 2 2006.257.23:20:22.29#ibcon#read 4, iclass 10, count 2 2006.257.23:20:22.29#ibcon#about to read 5, iclass 10, count 2 2006.257.23:20:22.29#ibcon#read 5, iclass 10, count 2 2006.257.23:20:22.29#ibcon#about to read 6, iclass 10, count 2 2006.257.23:20:22.29#ibcon#read 6, iclass 10, count 2 2006.257.23:20:22.29#ibcon#end of sib2, iclass 10, count 2 2006.257.23:20:22.29#ibcon#*mode == 0, iclass 10, count 2 2006.257.23:20:22.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.23:20:22.29#ibcon#[27=AT07-04\r\n] 2006.257.23:20:22.29#ibcon#*before write, iclass 10, count 2 2006.257.23:20:22.29#ibcon#enter sib2, iclass 10, count 2 2006.257.23:20:22.29#ibcon#flushed, iclass 10, count 2 2006.257.23:20:22.29#ibcon#about to write, iclass 10, count 2 2006.257.23:20:22.29#ibcon#wrote, iclass 10, count 2 2006.257.23:20:22.29#ibcon#about to read 3, iclass 10, count 2 2006.257.23:20:22.32#ibcon#read 3, iclass 10, count 2 2006.257.23:20:22.32#ibcon#about to read 4, iclass 10, count 2 2006.257.23:20:22.32#ibcon#read 4, iclass 10, count 2 2006.257.23:20:22.32#ibcon#about to read 5, iclass 10, count 2 2006.257.23:20:22.32#ibcon#read 5, iclass 10, count 2 2006.257.23:20:22.32#ibcon#about to read 6, iclass 10, count 2 2006.257.23:20:22.32#ibcon#read 6, iclass 10, count 2 2006.257.23:20:22.32#ibcon#end of sib2, iclass 10, count 2 2006.257.23:20:22.32#ibcon#*after write, iclass 10, count 2 2006.257.23:20:22.32#ibcon#*before return 0, iclass 10, count 2 2006.257.23:20:22.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:22.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:20:22.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.23:20:22.32#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:22.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:22.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:22.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:22.44#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:20:22.44#ibcon#first serial, iclass 10, count 0 2006.257.23:20:22.44#ibcon#enter sib2, iclass 10, count 0 2006.257.23:20:22.44#ibcon#flushed, iclass 10, count 0 2006.257.23:20:22.44#ibcon#about to write, iclass 10, count 0 2006.257.23:20:22.44#ibcon#wrote, iclass 10, count 0 2006.257.23:20:22.44#ibcon#about to read 3, iclass 10, count 0 2006.257.23:20:22.46#ibcon#read 3, iclass 10, count 0 2006.257.23:20:22.46#ibcon#about to read 4, iclass 10, count 0 2006.257.23:20:22.46#ibcon#read 4, iclass 10, count 0 2006.257.23:20:22.46#ibcon#about to read 5, iclass 10, count 0 2006.257.23:20:22.46#ibcon#read 5, iclass 10, count 0 2006.257.23:20:22.46#ibcon#about to read 6, iclass 10, count 0 2006.257.23:20:22.46#ibcon#read 6, iclass 10, count 0 2006.257.23:20:22.46#ibcon#end of sib2, iclass 10, count 0 2006.257.23:20:22.46#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:20:22.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:20:22.46#ibcon#[27=USB\r\n] 2006.257.23:20:22.46#ibcon#*before write, iclass 10, count 0 2006.257.23:20:22.46#ibcon#enter sib2, iclass 10, count 0 2006.257.23:20:22.46#ibcon#flushed, iclass 10, count 0 2006.257.23:20:22.46#ibcon#about to write, iclass 10, count 0 2006.257.23:20:22.46#ibcon#wrote, iclass 10, count 0 2006.257.23:20:22.46#ibcon#about to read 3, iclass 10, count 0 2006.257.23:20:22.49#ibcon#read 3, iclass 10, count 0 2006.257.23:20:22.49#ibcon#about to read 4, iclass 10, count 0 2006.257.23:20:22.49#ibcon#read 4, iclass 10, count 0 2006.257.23:20:22.49#ibcon#about to read 5, iclass 10, count 0 2006.257.23:20:22.49#ibcon#read 5, iclass 10, count 0 2006.257.23:20:22.49#ibcon#about to read 6, iclass 10, count 0 2006.257.23:20:22.49#ibcon#read 6, iclass 10, count 0 2006.257.23:20:22.49#ibcon#end of sib2, iclass 10, count 0 2006.257.23:20:22.49#ibcon#*after write, iclass 10, count 0 2006.257.23:20:22.49#ibcon#*before return 0, iclass 10, count 0 2006.257.23:20:22.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:22.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:20:22.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:20:22.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:20:22.49$vck44/vblo=8,744.99 2006.257.23:20:22.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.23:20:22.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.23:20:22.49#ibcon#ireg 17 cls_cnt 0 2006.257.23:20:22.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:22.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:22.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:22.49#ibcon#enter wrdev, iclass 12, count 0 2006.257.23:20:22.49#ibcon#first serial, iclass 12, count 0 2006.257.23:20:22.49#ibcon#enter sib2, iclass 12, count 0 2006.257.23:20:22.49#ibcon#flushed, iclass 12, count 0 2006.257.23:20:22.49#ibcon#about to write, iclass 12, count 0 2006.257.23:20:22.49#ibcon#wrote, iclass 12, count 0 2006.257.23:20:22.49#ibcon#about to read 3, iclass 12, count 0 2006.257.23:20:22.51#ibcon#read 3, iclass 12, count 0 2006.257.23:20:22.51#ibcon#about to read 4, iclass 12, count 0 2006.257.23:20:22.51#ibcon#read 4, iclass 12, count 0 2006.257.23:20:22.51#ibcon#about to read 5, iclass 12, count 0 2006.257.23:20:22.51#ibcon#read 5, iclass 12, count 0 2006.257.23:20:22.51#ibcon#about to read 6, iclass 12, count 0 2006.257.23:20:22.51#ibcon#read 6, iclass 12, count 0 2006.257.23:20:22.51#ibcon#end of sib2, iclass 12, count 0 2006.257.23:20:22.51#ibcon#*mode == 0, iclass 12, count 0 2006.257.23:20:22.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.23:20:22.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:20:22.51#ibcon#*before write, iclass 12, count 0 2006.257.23:20:22.51#ibcon#enter sib2, iclass 12, count 0 2006.257.23:20:22.51#ibcon#flushed, iclass 12, count 0 2006.257.23:20:22.51#ibcon#about to write, iclass 12, count 0 2006.257.23:20:22.51#ibcon#wrote, iclass 12, count 0 2006.257.23:20:22.51#ibcon#about to read 3, iclass 12, count 0 2006.257.23:20:22.55#ibcon#read 3, iclass 12, count 0 2006.257.23:20:22.55#ibcon#about to read 4, iclass 12, count 0 2006.257.23:20:22.55#ibcon#read 4, iclass 12, count 0 2006.257.23:20:22.55#ibcon#about to read 5, iclass 12, count 0 2006.257.23:20:22.55#ibcon#read 5, iclass 12, count 0 2006.257.23:20:22.55#ibcon#about to read 6, iclass 12, count 0 2006.257.23:20:22.55#ibcon#read 6, iclass 12, count 0 2006.257.23:20:22.55#ibcon#end of sib2, iclass 12, count 0 2006.257.23:20:22.55#ibcon#*after write, iclass 12, count 0 2006.257.23:20:22.55#ibcon#*before return 0, iclass 12, count 0 2006.257.23:20:22.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:22.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:20:22.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.23:20:22.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.23:20:22.55$vck44/vb=8,4 2006.257.23:20:22.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.23:20:22.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.23:20:22.55#ibcon#ireg 11 cls_cnt 2 2006.257.23:20:22.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:22.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:22.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:22.61#ibcon#enter wrdev, iclass 14, count 2 2006.257.23:20:22.61#ibcon#first serial, iclass 14, count 2 2006.257.23:20:22.61#ibcon#enter sib2, iclass 14, count 2 2006.257.23:20:22.61#ibcon#flushed, iclass 14, count 2 2006.257.23:20:22.61#ibcon#about to write, iclass 14, count 2 2006.257.23:20:22.61#ibcon#wrote, iclass 14, count 2 2006.257.23:20:22.61#ibcon#about to read 3, iclass 14, count 2 2006.257.23:20:22.63#ibcon#read 3, iclass 14, count 2 2006.257.23:20:22.63#ibcon#about to read 4, iclass 14, count 2 2006.257.23:20:22.63#ibcon#read 4, iclass 14, count 2 2006.257.23:20:22.63#ibcon#about to read 5, iclass 14, count 2 2006.257.23:20:22.63#ibcon#read 5, iclass 14, count 2 2006.257.23:20:22.63#ibcon#about to read 6, iclass 14, count 2 2006.257.23:20:22.63#ibcon#read 6, iclass 14, count 2 2006.257.23:20:22.63#ibcon#end of sib2, iclass 14, count 2 2006.257.23:20:22.63#ibcon#*mode == 0, iclass 14, count 2 2006.257.23:20:22.63#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.23:20:22.63#ibcon#[27=AT08-04\r\n] 2006.257.23:20:22.63#ibcon#*before write, iclass 14, count 2 2006.257.23:20:22.63#ibcon#enter sib2, iclass 14, count 2 2006.257.23:20:22.63#ibcon#flushed, iclass 14, count 2 2006.257.23:20:22.63#ibcon#about to write, iclass 14, count 2 2006.257.23:20:22.63#ibcon#wrote, iclass 14, count 2 2006.257.23:20:22.63#ibcon#about to read 3, iclass 14, count 2 2006.257.23:20:22.66#ibcon#read 3, iclass 14, count 2 2006.257.23:20:22.66#ibcon#about to read 4, iclass 14, count 2 2006.257.23:20:22.66#ibcon#read 4, iclass 14, count 2 2006.257.23:20:22.66#ibcon#about to read 5, iclass 14, count 2 2006.257.23:20:22.66#ibcon#read 5, iclass 14, count 2 2006.257.23:20:22.66#ibcon#about to read 6, iclass 14, count 2 2006.257.23:20:22.66#ibcon#read 6, iclass 14, count 2 2006.257.23:20:22.66#ibcon#end of sib2, iclass 14, count 2 2006.257.23:20:22.66#ibcon#*after write, iclass 14, count 2 2006.257.23:20:22.66#ibcon#*before return 0, iclass 14, count 2 2006.257.23:20:22.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:22.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:20:22.66#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.23:20:22.66#ibcon#ireg 7 cls_cnt 0 2006.257.23:20:22.66#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:22.78#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:22.78#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:22.78#ibcon#enter wrdev, iclass 14, count 0 2006.257.23:20:22.78#ibcon#first serial, iclass 14, count 0 2006.257.23:20:22.78#ibcon#enter sib2, iclass 14, count 0 2006.257.23:20:22.78#ibcon#flushed, iclass 14, count 0 2006.257.23:20:22.78#ibcon#about to write, iclass 14, count 0 2006.257.23:20:22.78#ibcon#wrote, iclass 14, count 0 2006.257.23:20:22.78#ibcon#about to read 3, iclass 14, count 0 2006.257.23:20:22.80#ibcon#read 3, iclass 14, count 0 2006.257.23:20:22.80#ibcon#about to read 4, iclass 14, count 0 2006.257.23:20:22.80#ibcon#read 4, iclass 14, count 0 2006.257.23:20:22.80#ibcon#about to read 5, iclass 14, count 0 2006.257.23:20:22.80#ibcon#read 5, iclass 14, count 0 2006.257.23:20:22.80#ibcon#about to read 6, iclass 14, count 0 2006.257.23:20:22.80#ibcon#read 6, iclass 14, count 0 2006.257.23:20:22.80#ibcon#end of sib2, iclass 14, count 0 2006.257.23:20:22.80#ibcon#*mode == 0, iclass 14, count 0 2006.257.23:20:22.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.23:20:22.80#ibcon#[27=USB\r\n] 2006.257.23:20:22.80#ibcon#*before write, iclass 14, count 0 2006.257.23:20:22.80#ibcon#enter sib2, iclass 14, count 0 2006.257.23:20:22.80#ibcon#flushed, iclass 14, count 0 2006.257.23:20:22.80#ibcon#about to write, iclass 14, count 0 2006.257.23:20:22.80#ibcon#wrote, iclass 14, count 0 2006.257.23:20:22.80#ibcon#about to read 3, iclass 14, count 0 2006.257.23:20:22.83#ibcon#read 3, iclass 14, count 0 2006.257.23:20:22.83#ibcon#about to read 4, iclass 14, count 0 2006.257.23:20:22.83#ibcon#read 4, iclass 14, count 0 2006.257.23:20:22.83#ibcon#about to read 5, iclass 14, count 0 2006.257.23:20:22.83#ibcon#read 5, iclass 14, count 0 2006.257.23:20:22.83#ibcon#about to read 6, iclass 14, count 0 2006.257.23:20:22.83#ibcon#read 6, iclass 14, count 0 2006.257.23:20:22.83#ibcon#end of sib2, iclass 14, count 0 2006.257.23:20:22.83#ibcon#*after write, iclass 14, count 0 2006.257.23:20:22.83#ibcon#*before return 0, iclass 14, count 0 2006.257.23:20:22.83#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:22.83#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:20:22.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.23:20:22.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.23:20:22.83$vck44/vabw=wide 2006.257.23:20:22.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.23:20:22.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.23:20:22.83#ibcon#ireg 8 cls_cnt 0 2006.257.23:20:22.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:22.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:22.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:22.83#ibcon#enter wrdev, iclass 16, count 0 2006.257.23:20:22.83#ibcon#first serial, iclass 16, count 0 2006.257.23:20:22.83#ibcon#enter sib2, iclass 16, count 0 2006.257.23:20:22.83#ibcon#flushed, iclass 16, count 0 2006.257.23:20:22.83#ibcon#about to write, iclass 16, count 0 2006.257.23:20:22.83#ibcon#wrote, iclass 16, count 0 2006.257.23:20:22.83#ibcon#about to read 3, iclass 16, count 0 2006.257.23:20:22.85#ibcon#read 3, iclass 16, count 0 2006.257.23:20:22.85#ibcon#about to read 4, iclass 16, count 0 2006.257.23:20:22.85#ibcon#read 4, iclass 16, count 0 2006.257.23:20:22.85#ibcon#about to read 5, iclass 16, count 0 2006.257.23:20:22.85#ibcon#read 5, iclass 16, count 0 2006.257.23:20:22.85#ibcon#about to read 6, iclass 16, count 0 2006.257.23:20:22.85#ibcon#read 6, iclass 16, count 0 2006.257.23:20:22.85#ibcon#end of sib2, iclass 16, count 0 2006.257.23:20:22.85#ibcon#*mode == 0, iclass 16, count 0 2006.257.23:20:22.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.23:20:22.85#ibcon#[25=BW32\r\n] 2006.257.23:20:22.85#ibcon#*before write, iclass 16, count 0 2006.257.23:20:22.85#ibcon#enter sib2, iclass 16, count 0 2006.257.23:20:22.85#ibcon#flushed, iclass 16, count 0 2006.257.23:20:22.85#ibcon#about to write, iclass 16, count 0 2006.257.23:20:22.85#ibcon#wrote, iclass 16, count 0 2006.257.23:20:22.85#ibcon#about to read 3, iclass 16, count 0 2006.257.23:20:22.88#ibcon#read 3, iclass 16, count 0 2006.257.23:20:22.88#ibcon#about to read 4, iclass 16, count 0 2006.257.23:20:22.88#ibcon#read 4, iclass 16, count 0 2006.257.23:20:22.88#ibcon#about to read 5, iclass 16, count 0 2006.257.23:20:22.88#ibcon#read 5, iclass 16, count 0 2006.257.23:20:22.88#ibcon#about to read 6, iclass 16, count 0 2006.257.23:20:22.88#ibcon#read 6, iclass 16, count 0 2006.257.23:20:22.88#ibcon#end of sib2, iclass 16, count 0 2006.257.23:20:22.88#ibcon#*after write, iclass 16, count 0 2006.257.23:20:22.88#ibcon#*before return 0, iclass 16, count 0 2006.257.23:20:22.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:22.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:20:22.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.23:20:22.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.23:20:22.88$vck44/vbbw=wide 2006.257.23:20:22.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.23:20:22.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.23:20:22.88#ibcon#ireg 8 cls_cnt 0 2006.257.23:20:22.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:20:22.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:20:22.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:20:22.95#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:20:22.95#ibcon#first serial, iclass 18, count 0 2006.257.23:20:22.95#ibcon#enter sib2, iclass 18, count 0 2006.257.23:20:22.95#ibcon#flushed, iclass 18, count 0 2006.257.23:20:22.95#ibcon#about to write, iclass 18, count 0 2006.257.23:20:22.95#ibcon#wrote, iclass 18, count 0 2006.257.23:20:22.95#ibcon#about to read 3, iclass 18, count 0 2006.257.23:20:22.97#ibcon#read 3, iclass 18, count 0 2006.257.23:20:22.97#ibcon#about to read 4, iclass 18, count 0 2006.257.23:20:22.97#ibcon#read 4, iclass 18, count 0 2006.257.23:20:22.97#ibcon#about to read 5, iclass 18, count 0 2006.257.23:20:22.97#ibcon#read 5, iclass 18, count 0 2006.257.23:20:22.97#ibcon#about to read 6, iclass 18, count 0 2006.257.23:20:22.97#ibcon#read 6, iclass 18, count 0 2006.257.23:20:22.97#ibcon#end of sib2, iclass 18, count 0 2006.257.23:20:22.97#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:20:22.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:20:22.97#ibcon#[27=BW32\r\n] 2006.257.23:20:22.97#ibcon#*before write, iclass 18, count 0 2006.257.23:20:22.97#ibcon#enter sib2, iclass 18, count 0 2006.257.23:20:22.97#ibcon#flushed, iclass 18, count 0 2006.257.23:20:22.97#ibcon#about to write, iclass 18, count 0 2006.257.23:20:22.97#ibcon#wrote, iclass 18, count 0 2006.257.23:20:22.97#ibcon#about to read 3, iclass 18, count 0 2006.257.23:20:23.00#ibcon#read 3, iclass 18, count 0 2006.257.23:20:23.00#ibcon#about to read 4, iclass 18, count 0 2006.257.23:20:23.00#ibcon#read 4, iclass 18, count 0 2006.257.23:20:23.00#ibcon#about to read 5, iclass 18, count 0 2006.257.23:20:23.00#ibcon#read 5, iclass 18, count 0 2006.257.23:20:23.00#ibcon#about to read 6, iclass 18, count 0 2006.257.23:20:23.00#ibcon#read 6, iclass 18, count 0 2006.257.23:20:23.00#ibcon#end of sib2, iclass 18, count 0 2006.257.23:20:23.00#ibcon#*after write, iclass 18, count 0 2006.257.23:20:23.00#ibcon#*before return 0, iclass 18, count 0 2006.257.23:20:23.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:20:23.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:20:23.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:20:23.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:20:23.00$setupk4/ifdk4 2006.257.23:20:23.00$ifdk4/lo= 2006.257.23:20:23.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:20:23.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:20:23.00$ifdk4/patch= 2006.257.23:20:23.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:20:23.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:20:23.00$setupk4/!*+20s 2006.257.23:20:24.63#abcon#<5=/15 1.3 3.2 20.55 821016.1\r\n> 2006.257.23:20:24.65#abcon#{5=INTERFACE CLEAR} 2006.257.23:20:24.71#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:20:34.80#abcon#<5=/15 1.3 3.2 20.55 821016.1\r\n> 2006.257.23:20:34.82#abcon#{5=INTERFACE CLEAR} 2006.257.23:20:34.88#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:20:37.50$setupk4/"tpicd 2006.257.23:20:37.50$setupk4/echo=off 2006.257.23:20:37.50$setupk4/xlog=off 2006.257.23:20:37.50:!2006.257.23:22:24 2006.257.23:20:41.14#trakl#Source acquired 2006.257.23:20:41.14#flagr#flagr/antenna,acquired 2006.257.23:22:24.00:preob 2006.257.23:22:24.14/onsource/TRACKING 2006.257.23:22:24.14:!2006.257.23:22:34 2006.257.23:22:34.00:"tape 2006.257.23:22:34.00:"st=record 2006.257.23:22:34.00:data_valid=on 2006.257.23:22:34.00:midob 2006.257.23:22:35.14/onsource/TRACKING 2006.257.23:22:35.14/wx/20.57,1016.1,80 2006.257.23:22:35.23/cable/+6.4833E-03 2006.257.23:22:36.32/va/01,08,usb,yes,31,33 2006.257.23:22:36.32/va/02,07,usb,yes,34,34 2006.257.23:22:36.32/va/03,08,usb,yes,30,32 2006.257.23:22:36.32/va/04,07,usb,yes,34,36 2006.257.23:22:36.32/va/05,04,usb,yes,31,31 2006.257.23:22:36.32/va/06,04,usb,yes,34,34 2006.257.23:22:36.32/va/07,04,usb,yes,35,36 2006.257.23:22:36.32/va/08,04,usb,yes,29,36 2006.257.23:22:36.55/valo/01,524.99,yes,locked 2006.257.23:22:36.55/valo/02,534.99,yes,locked 2006.257.23:22:36.55/valo/03,564.99,yes,locked 2006.257.23:22:36.55/valo/04,624.99,yes,locked 2006.257.23:22:36.55/valo/05,734.99,yes,locked 2006.257.23:22:36.55/valo/06,814.99,yes,locked 2006.257.23:22:36.55/valo/07,864.99,yes,locked 2006.257.23:22:36.55/valo/08,884.99,yes,locked 2006.257.23:22:37.64/vb/01,04,usb,yes,31,29 2006.257.23:22:37.64/vb/02,05,usb,yes,29,29 2006.257.23:22:37.64/vb/03,04,usb,yes,30,33 2006.257.23:22:37.64/vb/04,05,usb,yes,30,29 2006.257.23:22:37.64/vb/05,04,usb,yes,27,29 2006.257.23:22:37.64/vb/06,04,usb,yes,31,27 2006.257.23:22:37.64/vb/07,04,usb,yes,31,31 2006.257.23:22:37.64/vb/08,04,usb,yes,28,32 2006.257.23:22:37.88/vblo/01,629.99,yes,locked 2006.257.23:22:37.88/vblo/02,634.99,yes,locked 2006.257.23:22:37.88/vblo/03,649.99,yes,locked 2006.257.23:22:37.88/vblo/04,679.99,yes,locked 2006.257.23:22:37.88/vblo/05,709.99,yes,locked 2006.257.23:22:37.88/vblo/06,719.99,yes,locked 2006.257.23:22:37.88/vblo/07,734.99,yes,locked 2006.257.23:22:37.88/vblo/08,744.99,yes,locked 2006.257.23:22:38.03/vabw/8 2006.257.23:22:38.18/vbbw/8 2006.257.23:22:38.27/xfe/off,on,15.2 2006.257.23:22:38.66/ifatt/23,28,28,28 2006.257.23:22:39.08/fmout-gps/S +4.53E-07 2006.257.23:22:39.11:!2006.257.23:26:04 2006.257.23:26:04.00:data_valid=off 2006.257.23:26:04.00:"et 2006.257.23:26:04.00:!+3s 2006.257.23:26:07.01:"tape 2006.257.23:26:07.01:postob 2006.257.23:26:07.13/cable/+6.4828E-03 2006.257.23:26:07.13/wx/20.58,1016.1,82 2006.257.23:26:08.08/fmout-gps/S +4.54E-07 2006.257.23:26:08.08:scan_name=257-2336,jd0609,290 2006.257.23:26:08.08:source=oj287,085448.87,200630.6,2000.0,cw 2006.257.23:26:08.14#flagr#flagr/antenna,new-source 2006.257.23:26:09.14:checkk5 2006.257.23:26:09.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:26:09.84/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:26:10.19/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:26:10.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:26:10.87/chk_obsdata//k5ts1/T2572322??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.23:26:11.20/chk_obsdata//k5ts2/T2572322??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.23:26:11.53/chk_obsdata//k5ts3/T2572322??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.23:26:11.86/chk_obsdata//k5ts4/T2572322??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.257.23:26:12.53/k5log//k5ts1_log_newline 2006.257.23:26:13.19/k5log//k5ts2_log_newline 2006.257.23:26:13.86/k5log//k5ts3_log_newline 2006.257.23:26:14.52/k5log//k5ts4_log_newline 2006.257.23:26:14.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:26:14.54:setupk4=1 2006.257.23:26:14.54$setupk4/echo=on 2006.257.23:26:14.54$setupk4/pcalon 2006.257.23:26:14.54$pcalon/"no phase cal control is implemented here 2006.257.23:26:14.54$setupk4/"tpicd=stop 2006.257.23:26:14.54$setupk4/"rec=synch_on 2006.257.23:26:14.54$setupk4/"rec_mode=128 2006.257.23:26:14.54$setupk4/!* 2006.257.23:26:14.55$setupk4/recpk4 2006.257.23:26:14.55$recpk4/recpatch= 2006.257.23:26:14.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:26:14.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:26:14.55$setupk4/vck44 2006.257.23:26:14.55$vck44/valo=1,524.99 2006.257.23:26:14.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.23:26:14.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.23:26:14.55#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:14.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:14.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:14.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:14.55#ibcon#enter wrdev, iclass 14, count 0 2006.257.23:26:14.55#ibcon#first serial, iclass 14, count 0 2006.257.23:26:14.55#ibcon#enter sib2, iclass 14, count 0 2006.257.23:26:14.55#ibcon#flushed, iclass 14, count 0 2006.257.23:26:14.55#ibcon#about to write, iclass 14, count 0 2006.257.23:26:14.55#ibcon#wrote, iclass 14, count 0 2006.257.23:26:14.55#ibcon#about to read 3, iclass 14, count 0 2006.257.23:26:14.57#ibcon#read 3, iclass 14, count 0 2006.257.23:26:14.57#ibcon#about to read 4, iclass 14, count 0 2006.257.23:26:14.57#ibcon#read 4, iclass 14, count 0 2006.257.23:26:14.57#ibcon#about to read 5, iclass 14, count 0 2006.257.23:26:14.57#ibcon#read 5, iclass 14, count 0 2006.257.23:26:14.57#ibcon#about to read 6, iclass 14, count 0 2006.257.23:26:14.57#ibcon#read 6, iclass 14, count 0 2006.257.23:26:14.57#ibcon#end of sib2, iclass 14, count 0 2006.257.23:26:14.57#ibcon#*mode == 0, iclass 14, count 0 2006.257.23:26:14.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.23:26:14.57#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:26:14.57#ibcon#*before write, iclass 14, count 0 2006.257.23:26:14.57#ibcon#enter sib2, iclass 14, count 0 2006.257.23:26:14.57#ibcon#flushed, iclass 14, count 0 2006.257.23:26:14.57#ibcon#about to write, iclass 14, count 0 2006.257.23:26:14.57#ibcon#wrote, iclass 14, count 0 2006.257.23:26:14.57#ibcon#about to read 3, iclass 14, count 0 2006.257.23:26:14.62#ibcon#read 3, iclass 14, count 0 2006.257.23:26:14.62#ibcon#about to read 4, iclass 14, count 0 2006.257.23:26:14.62#ibcon#read 4, iclass 14, count 0 2006.257.23:26:14.62#ibcon#about to read 5, iclass 14, count 0 2006.257.23:26:14.62#ibcon#read 5, iclass 14, count 0 2006.257.23:26:14.62#ibcon#about to read 6, iclass 14, count 0 2006.257.23:26:14.62#ibcon#read 6, iclass 14, count 0 2006.257.23:26:14.62#ibcon#end of sib2, iclass 14, count 0 2006.257.23:26:14.62#ibcon#*after write, iclass 14, count 0 2006.257.23:26:14.62#ibcon#*before return 0, iclass 14, count 0 2006.257.23:26:14.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:14.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:14.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.23:26:14.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.23:26:14.62$vck44/va=1,8 2006.257.23:26:14.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.23:26:14.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.23:26:14.62#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:14.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:14.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:14.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:14.62#ibcon#enter wrdev, iclass 16, count 2 2006.257.23:26:14.62#ibcon#first serial, iclass 16, count 2 2006.257.23:26:14.62#ibcon#enter sib2, iclass 16, count 2 2006.257.23:26:14.62#ibcon#flushed, iclass 16, count 2 2006.257.23:26:14.62#ibcon#about to write, iclass 16, count 2 2006.257.23:26:14.62#ibcon#wrote, iclass 16, count 2 2006.257.23:26:14.62#ibcon#about to read 3, iclass 16, count 2 2006.257.23:26:14.64#ibcon#read 3, iclass 16, count 2 2006.257.23:26:14.64#ibcon#about to read 4, iclass 16, count 2 2006.257.23:26:14.64#ibcon#read 4, iclass 16, count 2 2006.257.23:26:14.64#ibcon#about to read 5, iclass 16, count 2 2006.257.23:26:14.64#ibcon#read 5, iclass 16, count 2 2006.257.23:26:14.64#ibcon#about to read 6, iclass 16, count 2 2006.257.23:26:14.64#ibcon#read 6, iclass 16, count 2 2006.257.23:26:14.64#ibcon#end of sib2, iclass 16, count 2 2006.257.23:26:14.64#ibcon#*mode == 0, iclass 16, count 2 2006.257.23:26:14.64#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.23:26:14.64#ibcon#[25=AT01-08\r\n] 2006.257.23:26:14.64#ibcon#*before write, iclass 16, count 2 2006.257.23:26:14.64#ibcon#enter sib2, iclass 16, count 2 2006.257.23:26:14.64#ibcon#flushed, iclass 16, count 2 2006.257.23:26:14.64#ibcon#about to write, iclass 16, count 2 2006.257.23:26:14.64#ibcon#wrote, iclass 16, count 2 2006.257.23:26:14.64#ibcon#about to read 3, iclass 16, count 2 2006.257.23:26:14.67#ibcon#read 3, iclass 16, count 2 2006.257.23:26:14.67#ibcon#about to read 4, iclass 16, count 2 2006.257.23:26:14.67#ibcon#read 4, iclass 16, count 2 2006.257.23:26:14.67#ibcon#about to read 5, iclass 16, count 2 2006.257.23:26:14.67#ibcon#read 5, iclass 16, count 2 2006.257.23:26:14.67#ibcon#about to read 6, iclass 16, count 2 2006.257.23:26:14.67#ibcon#read 6, iclass 16, count 2 2006.257.23:26:14.67#ibcon#end of sib2, iclass 16, count 2 2006.257.23:26:14.67#ibcon#*after write, iclass 16, count 2 2006.257.23:26:14.67#ibcon#*before return 0, iclass 16, count 2 2006.257.23:26:14.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:14.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:14.67#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.23:26:14.67#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:14.67#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:14.79#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:14.79#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:14.79#ibcon#enter wrdev, iclass 16, count 0 2006.257.23:26:14.79#ibcon#first serial, iclass 16, count 0 2006.257.23:26:14.79#ibcon#enter sib2, iclass 16, count 0 2006.257.23:26:14.79#ibcon#flushed, iclass 16, count 0 2006.257.23:26:14.79#ibcon#about to write, iclass 16, count 0 2006.257.23:26:14.79#ibcon#wrote, iclass 16, count 0 2006.257.23:26:14.79#ibcon#about to read 3, iclass 16, count 0 2006.257.23:26:14.81#ibcon#read 3, iclass 16, count 0 2006.257.23:26:14.81#ibcon#about to read 4, iclass 16, count 0 2006.257.23:26:14.81#ibcon#read 4, iclass 16, count 0 2006.257.23:26:14.81#ibcon#about to read 5, iclass 16, count 0 2006.257.23:26:14.81#ibcon#read 5, iclass 16, count 0 2006.257.23:26:14.81#ibcon#about to read 6, iclass 16, count 0 2006.257.23:26:14.81#ibcon#read 6, iclass 16, count 0 2006.257.23:26:14.81#ibcon#end of sib2, iclass 16, count 0 2006.257.23:26:14.81#ibcon#*mode == 0, iclass 16, count 0 2006.257.23:26:14.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.23:26:14.81#ibcon#[25=USB\r\n] 2006.257.23:26:14.81#ibcon#*before write, iclass 16, count 0 2006.257.23:26:14.81#ibcon#enter sib2, iclass 16, count 0 2006.257.23:26:14.81#ibcon#flushed, iclass 16, count 0 2006.257.23:26:14.81#ibcon#about to write, iclass 16, count 0 2006.257.23:26:14.81#ibcon#wrote, iclass 16, count 0 2006.257.23:26:14.81#ibcon#about to read 3, iclass 16, count 0 2006.257.23:26:14.84#ibcon#read 3, iclass 16, count 0 2006.257.23:26:14.84#ibcon#about to read 4, iclass 16, count 0 2006.257.23:26:14.84#ibcon#read 4, iclass 16, count 0 2006.257.23:26:14.84#ibcon#about to read 5, iclass 16, count 0 2006.257.23:26:14.84#ibcon#read 5, iclass 16, count 0 2006.257.23:26:14.84#ibcon#about to read 6, iclass 16, count 0 2006.257.23:26:14.84#ibcon#read 6, iclass 16, count 0 2006.257.23:26:14.84#ibcon#end of sib2, iclass 16, count 0 2006.257.23:26:14.84#ibcon#*after write, iclass 16, count 0 2006.257.23:26:14.84#ibcon#*before return 0, iclass 16, count 0 2006.257.23:26:14.84#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:14.84#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:14.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.23:26:14.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.23:26:14.84$vck44/valo=2,534.99 2006.257.23:26:14.84#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.23:26:14.84#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.23:26:14.84#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:14.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:14.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:14.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:14.84#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:26:14.84#ibcon#first serial, iclass 18, count 0 2006.257.23:26:14.84#ibcon#enter sib2, iclass 18, count 0 2006.257.23:26:14.84#ibcon#flushed, iclass 18, count 0 2006.257.23:26:14.84#ibcon#about to write, iclass 18, count 0 2006.257.23:26:14.84#ibcon#wrote, iclass 18, count 0 2006.257.23:26:14.84#ibcon#about to read 3, iclass 18, count 0 2006.257.23:26:14.86#ibcon#read 3, iclass 18, count 0 2006.257.23:26:14.86#ibcon#about to read 4, iclass 18, count 0 2006.257.23:26:14.86#ibcon#read 4, iclass 18, count 0 2006.257.23:26:14.86#ibcon#about to read 5, iclass 18, count 0 2006.257.23:26:14.86#ibcon#read 5, iclass 18, count 0 2006.257.23:26:14.86#ibcon#about to read 6, iclass 18, count 0 2006.257.23:26:14.86#ibcon#read 6, iclass 18, count 0 2006.257.23:26:14.86#ibcon#end of sib2, iclass 18, count 0 2006.257.23:26:14.86#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:26:14.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:26:14.86#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:26:14.86#ibcon#*before write, iclass 18, count 0 2006.257.23:26:14.86#ibcon#enter sib2, iclass 18, count 0 2006.257.23:26:14.86#ibcon#flushed, iclass 18, count 0 2006.257.23:26:14.86#ibcon#about to write, iclass 18, count 0 2006.257.23:26:14.86#ibcon#wrote, iclass 18, count 0 2006.257.23:26:14.86#ibcon#about to read 3, iclass 18, count 0 2006.257.23:26:14.90#ibcon#read 3, iclass 18, count 0 2006.257.23:26:14.90#ibcon#about to read 4, iclass 18, count 0 2006.257.23:26:14.90#ibcon#read 4, iclass 18, count 0 2006.257.23:26:14.90#ibcon#about to read 5, iclass 18, count 0 2006.257.23:26:14.90#ibcon#read 5, iclass 18, count 0 2006.257.23:26:14.90#ibcon#about to read 6, iclass 18, count 0 2006.257.23:26:14.90#ibcon#read 6, iclass 18, count 0 2006.257.23:26:14.90#ibcon#end of sib2, iclass 18, count 0 2006.257.23:26:14.90#ibcon#*after write, iclass 18, count 0 2006.257.23:26:14.90#ibcon#*before return 0, iclass 18, count 0 2006.257.23:26:14.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:14.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:14.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:26:14.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:26:14.90$vck44/va=2,7 2006.257.23:26:14.90#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.23:26:14.90#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.23:26:14.90#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:14.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:14.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:14.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:14.96#ibcon#enter wrdev, iclass 20, count 2 2006.257.23:26:14.96#ibcon#first serial, iclass 20, count 2 2006.257.23:26:14.96#ibcon#enter sib2, iclass 20, count 2 2006.257.23:26:14.96#ibcon#flushed, iclass 20, count 2 2006.257.23:26:14.96#ibcon#about to write, iclass 20, count 2 2006.257.23:26:14.96#ibcon#wrote, iclass 20, count 2 2006.257.23:26:14.96#ibcon#about to read 3, iclass 20, count 2 2006.257.23:26:14.98#ibcon#read 3, iclass 20, count 2 2006.257.23:26:14.98#ibcon#about to read 4, iclass 20, count 2 2006.257.23:26:14.98#ibcon#read 4, iclass 20, count 2 2006.257.23:26:14.98#ibcon#about to read 5, iclass 20, count 2 2006.257.23:26:14.98#ibcon#read 5, iclass 20, count 2 2006.257.23:26:14.98#ibcon#about to read 6, iclass 20, count 2 2006.257.23:26:14.98#ibcon#read 6, iclass 20, count 2 2006.257.23:26:14.98#ibcon#end of sib2, iclass 20, count 2 2006.257.23:26:14.98#ibcon#*mode == 0, iclass 20, count 2 2006.257.23:26:14.98#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.23:26:14.98#ibcon#[25=AT02-07\r\n] 2006.257.23:26:14.98#ibcon#*before write, iclass 20, count 2 2006.257.23:26:14.98#ibcon#enter sib2, iclass 20, count 2 2006.257.23:26:14.98#ibcon#flushed, iclass 20, count 2 2006.257.23:26:14.98#ibcon#about to write, iclass 20, count 2 2006.257.23:26:14.98#ibcon#wrote, iclass 20, count 2 2006.257.23:26:14.98#ibcon#about to read 3, iclass 20, count 2 2006.257.23:26:15.01#ibcon#read 3, iclass 20, count 2 2006.257.23:26:15.01#ibcon#about to read 4, iclass 20, count 2 2006.257.23:26:15.01#ibcon#read 4, iclass 20, count 2 2006.257.23:26:15.01#ibcon#about to read 5, iclass 20, count 2 2006.257.23:26:15.01#ibcon#read 5, iclass 20, count 2 2006.257.23:26:15.01#ibcon#about to read 6, iclass 20, count 2 2006.257.23:26:15.01#ibcon#read 6, iclass 20, count 2 2006.257.23:26:15.01#ibcon#end of sib2, iclass 20, count 2 2006.257.23:26:15.01#ibcon#*after write, iclass 20, count 2 2006.257.23:26:15.01#ibcon#*before return 0, iclass 20, count 2 2006.257.23:26:15.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:15.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:15.01#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.23:26:15.01#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:15.01#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:15.13#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:15.13#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:15.13#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:26:15.13#ibcon#first serial, iclass 20, count 0 2006.257.23:26:15.13#ibcon#enter sib2, iclass 20, count 0 2006.257.23:26:15.13#ibcon#flushed, iclass 20, count 0 2006.257.23:26:15.13#ibcon#about to write, iclass 20, count 0 2006.257.23:26:15.13#ibcon#wrote, iclass 20, count 0 2006.257.23:26:15.13#ibcon#about to read 3, iclass 20, count 0 2006.257.23:26:15.15#ibcon#read 3, iclass 20, count 0 2006.257.23:26:15.15#ibcon#about to read 4, iclass 20, count 0 2006.257.23:26:15.15#ibcon#read 4, iclass 20, count 0 2006.257.23:26:15.15#ibcon#about to read 5, iclass 20, count 0 2006.257.23:26:15.15#ibcon#read 5, iclass 20, count 0 2006.257.23:26:15.15#ibcon#about to read 6, iclass 20, count 0 2006.257.23:26:15.15#ibcon#read 6, iclass 20, count 0 2006.257.23:26:15.15#ibcon#end of sib2, iclass 20, count 0 2006.257.23:26:15.15#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:26:15.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:26:15.15#ibcon#[25=USB\r\n] 2006.257.23:26:15.15#ibcon#*before write, iclass 20, count 0 2006.257.23:26:15.15#ibcon#enter sib2, iclass 20, count 0 2006.257.23:26:15.15#ibcon#flushed, iclass 20, count 0 2006.257.23:26:15.15#ibcon#about to write, iclass 20, count 0 2006.257.23:26:15.15#ibcon#wrote, iclass 20, count 0 2006.257.23:26:15.15#ibcon#about to read 3, iclass 20, count 0 2006.257.23:26:15.18#ibcon#read 3, iclass 20, count 0 2006.257.23:26:15.18#ibcon#about to read 4, iclass 20, count 0 2006.257.23:26:15.18#ibcon#read 4, iclass 20, count 0 2006.257.23:26:15.18#ibcon#about to read 5, iclass 20, count 0 2006.257.23:26:15.18#ibcon#read 5, iclass 20, count 0 2006.257.23:26:15.18#ibcon#about to read 6, iclass 20, count 0 2006.257.23:26:15.18#ibcon#read 6, iclass 20, count 0 2006.257.23:26:15.18#ibcon#end of sib2, iclass 20, count 0 2006.257.23:26:15.18#ibcon#*after write, iclass 20, count 0 2006.257.23:26:15.18#ibcon#*before return 0, iclass 20, count 0 2006.257.23:26:15.18#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:15.18#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:15.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:26:15.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:26:15.18$vck44/valo=3,564.99 2006.257.23:26:15.18#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.23:26:15.18#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.23:26:15.18#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:15.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:15.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:15.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:15.18#ibcon#enter wrdev, iclass 22, count 0 2006.257.23:26:15.18#ibcon#first serial, iclass 22, count 0 2006.257.23:26:15.18#ibcon#enter sib2, iclass 22, count 0 2006.257.23:26:15.18#ibcon#flushed, iclass 22, count 0 2006.257.23:26:15.18#ibcon#about to write, iclass 22, count 0 2006.257.23:26:15.18#ibcon#wrote, iclass 22, count 0 2006.257.23:26:15.18#ibcon#about to read 3, iclass 22, count 0 2006.257.23:26:15.20#ibcon#read 3, iclass 22, count 0 2006.257.23:26:15.20#ibcon#about to read 4, iclass 22, count 0 2006.257.23:26:15.20#ibcon#read 4, iclass 22, count 0 2006.257.23:26:15.20#ibcon#about to read 5, iclass 22, count 0 2006.257.23:26:15.20#ibcon#read 5, iclass 22, count 0 2006.257.23:26:15.20#ibcon#about to read 6, iclass 22, count 0 2006.257.23:26:15.20#ibcon#read 6, iclass 22, count 0 2006.257.23:26:15.20#ibcon#end of sib2, iclass 22, count 0 2006.257.23:26:15.20#ibcon#*mode == 0, iclass 22, count 0 2006.257.23:26:15.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.23:26:15.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:26:15.20#ibcon#*before write, iclass 22, count 0 2006.257.23:26:15.20#ibcon#enter sib2, iclass 22, count 0 2006.257.23:26:15.20#ibcon#flushed, iclass 22, count 0 2006.257.23:26:15.20#ibcon#about to write, iclass 22, count 0 2006.257.23:26:15.20#ibcon#wrote, iclass 22, count 0 2006.257.23:26:15.20#ibcon#about to read 3, iclass 22, count 0 2006.257.23:26:15.24#ibcon#read 3, iclass 22, count 0 2006.257.23:26:15.24#ibcon#about to read 4, iclass 22, count 0 2006.257.23:26:15.24#ibcon#read 4, iclass 22, count 0 2006.257.23:26:15.24#ibcon#about to read 5, iclass 22, count 0 2006.257.23:26:15.24#ibcon#read 5, iclass 22, count 0 2006.257.23:26:15.24#ibcon#about to read 6, iclass 22, count 0 2006.257.23:26:15.24#ibcon#read 6, iclass 22, count 0 2006.257.23:26:15.24#ibcon#end of sib2, iclass 22, count 0 2006.257.23:26:15.24#ibcon#*after write, iclass 22, count 0 2006.257.23:26:15.24#ibcon#*before return 0, iclass 22, count 0 2006.257.23:26:15.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:15.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:15.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.23:26:15.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.23:26:15.24$vck44/va=3,8 2006.257.23:26:15.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.23:26:15.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.23:26:15.24#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:15.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:15.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:15.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:15.30#ibcon#enter wrdev, iclass 24, count 2 2006.257.23:26:15.30#ibcon#first serial, iclass 24, count 2 2006.257.23:26:15.30#ibcon#enter sib2, iclass 24, count 2 2006.257.23:26:15.30#ibcon#flushed, iclass 24, count 2 2006.257.23:26:15.30#ibcon#about to write, iclass 24, count 2 2006.257.23:26:15.30#ibcon#wrote, iclass 24, count 2 2006.257.23:26:15.30#ibcon#about to read 3, iclass 24, count 2 2006.257.23:26:15.32#ibcon#read 3, iclass 24, count 2 2006.257.23:26:15.32#ibcon#about to read 4, iclass 24, count 2 2006.257.23:26:15.32#ibcon#read 4, iclass 24, count 2 2006.257.23:26:15.32#ibcon#about to read 5, iclass 24, count 2 2006.257.23:26:15.32#ibcon#read 5, iclass 24, count 2 2006.257.23:26:15.32#ibcon#about to read 6, iclass 24, count 2 2006.257.23:26:15.32#ibcon#read 6, iclass 24, count 2 2006.257.23:26:15.32#ibcon#end of sib2, iclass 24, count 2 2006.257.23:26:15.32#ibcon#*mode == 0, iclass 24, count 2 2006.257.23:26:15.32#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.23:26:15.32#ibcon#[25=AT03-08\r\n] 2006.257.23:26:15.32#ibcon#*before write, iclass 24, count 2 2006.257.23:26:15.32#ibcon#enter sib2, iclass 24, count 2 2006.257.23:26:15.32#ibcon#flushed, iclass 24, count 2 2006.257.23:26:15.32#ibcon#about to write, iclass 24, count 2 2006.257.23:26:15.32#ibcon#wrote, iclass 24, count 2 2006.257.23:26:15.32#ibcon#about to read 3, iclass 24, count 2 2006.257.23:26:15.35#ibcon#read 3, iclass 24, count 2 2006.257.23:26:15.35#ibcon#about to read 4, iclass 24, count 2 2006.257.23:26:15.35#ibcon#read 4, iclass 24, count 2 2006.257.23:26:15.35#ibcon#about to read 5, iclass 24, count 2 2006.257.23:26:15.35#ibcon#read 5, iclass 24, count 2 2006.257.23:26:15.35#ibcon#about to read 6, iclass 24, count 2 2006.257.23:26:15.35#ibcon#read 6, iclass 24, count 2 2006.257.23:26:15.35#ibcon#end of sib2, iclass 24, count 2 2006.257.23:26:15.35#ibcon#*after write, iclass 24, count 2 2006.257.23:26:15.35#ibcon#*before return 0, iclass 24, count 2 2006.257.23:26:15.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:15.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:15.35#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.23:26:15.35#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:15.35#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:15.47#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:15.47#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:15.47#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:26:15.47#ibcon#first serial, iclass 24, count 0 2006.257.23:26:15.47#ibcon#enter sib2, iclass 24, count 0 2006.257.23:26:15.47#ibcon#flushed, iclass 24, count 0 2006.257.23:26:15.47#ibcon#about to write, iclass 24, count 0 2006.257.23:26:15.47#ibcon#wrote, iclass 24, count 0 2006.257.23:26:15.47#ibcon#about to read 3, iclass 24, count 0 2006.257.23:26:15.49#ibcon#read 3, iclass 24, count 0 2006.257.23:26:15.49#ibcon#about to read 4, iclass 24, count 0 2006.257.23:26:15.49#ibcon#read 4, iclass 24, count 0 2006.257.23:26:15.49#ibcon#about to read 5, iclass 24, count 0 2006.257.23:26:15.49#ibcon#read 5, iclass 24, count 0 2006.257.23:26:15.49#ibcon#about to read 6, iclass 24, count 0 2006.257.23:26:15.49#ibcon#read 6, iclass 24, count 0 2006.257.23:26:15.49#ibcon#end of sib2, iclass 24, count 0 2006.257.23:26:15.49#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:26:15.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:26:15.49#ibcon#[25=USB\r\n] 2006.257.23:26:15.49#ibcon#*before write, iclass 24, count 0 2006.257.23:26:15.49#ibcon#enter sib2, iclass 24, count 0 2006.257.23:26:15.49#ibcon#flushed, iclass 24, count 0 2006.257.23:26:15.49#ibcon#about to write, iclass 24, count 0 2006.257.23:26:15.49#ibcon#wrote, iclass 24, count 0 2006.257.23:26:15.49#ibcon#about to read 3, iclass 24, count 0 2006.257.23:26:15.52#ibcon#read 3, iclass 24, count 0 2006.257.23:26:15.52#ibcon#about to read 4, iclass 24, count 0 2006.257.23:26:15.52#ibcon#read 4, iclass 24, count 0 2006.257.23:26:15.52#ibcon#about to read 5, iclass 24, count 0 2006.257.23:26:15.52#ibcon#read 5, iclass 24, count 0 2006.257.23:26:15.52#ibcon#about to read 6, iclass 24, count 0 2006.257.23:26:15.52#ibcon#read 6, iclass 24, count 0 2006.257.23:26:15.52#ibcon#end of sib2, iclass 24, count 0 2006.257.23:26:15.52#ibcon#*after write, iclass 24, count 0 2006.257.23:26:15.52#ibcon#*before return 0, iclass 24, count 0 2006.257.23:26:15.52#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:15.52#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:15.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:26:15.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:26:15.52$vck44/valo=4,624.99 2006.257.23:26:15.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.23:26:15.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.23:26:15.52#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:15.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:15.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:15.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:15.52#ibcon#enter wrdev, iclass 26, count 0 2006.257.23:26:15.52#ibcon#first serial, iclass 26, count 0 2006.257.23:26:15.52#ibcon#enter sib2, iclass 26, count 0 2006.257.23:26:15.52#ibcon#flushed, iclass 26, count 0 2006.257.23:26:15.52#ibcon#about to write, iclass 26, count 0 2006.257.23:26:15.52#ibcon#wrote, iclass 26, count 0 2006.257.23:26:15.52#ibcon#about to read 3, iclass 26, count 0 2006.257.23:26:15.54#ibcon#read 3, iclass 26, count 0 2006.257.23:26:15.54#ibcon#about to read 4, iclass 26, count 0 2006.257.23:26:15.54#ibcon#read 4, iclass 26, count 0 2006.257.23:26:15.54#ibcon#about to read 5, iclass 26, count 0 2006.257.23:26:15.54#ibcon#read 5, iclass 26, count 0 2006.257.23:26:15.54#ibcon#about to read 6, iclass 26, count 0 2006.257.23:26:15.54#ibcon#read 6, iclass 26, count 0 2006.257.23:26:15.54#ibcon#end of sib2, iclass 26, count 0 2006.257.23:26:15.54#ibcon#*mode == 0, iclass 26, count 0 2006.257.23:26:15.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.23:26:15.54#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:26:15.54#ibcon#*before write, iclass 26, count 0 2006.257.23:26:15.54#ibcon#enter sib2, iclass 26, count 0 2006.257.23:26:15.54#ibcon#flushed, iclass 26, count 0 2006.257.23:26:15.54#ibcon#about to write, iclass 26, count 0 2006.257.23:26:15.54#ibcon#wrote, iclass 26, count 0 2006.257.23:26:15.54#ibcon#about to read 3, iclass 26, count 0 2006.257.23:26:15.58#ibcon#read 3, iclass 26, count 0 2006.257.23:26:15.58#ibcon#about to read 4, iclass 26, count 0 2006.257.23:26:15.58#ibcon#read 4, iclass 26, count 0 2006.257.23:26:15.58#ibcon#about to read 5, iclass 26, count 0 2006.257.23:26:15.58#ibcon#read 5, iclass 26, count 0 2006.257.23:26:15.58#ibcon#about to read 6, iclass 26, count 0 2006.257.23:26:15.58#ibcon#read 6, iclass 26, count 0 2006.257.23:26:15.58#ibcon#end of sib2, iclass 26, count 0 2006.257.23:26:15.58#ibcon#*after write, iclass 26, count 0 2006.257.23:26:15.58#ibcon#*before return 0, iclass 26, count 0 2006.257.23:26:15.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:15.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:15.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.23:26:15.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.23:26:15.58$vck44/va=4,7 2006.257.23:26:15.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.23:26:15.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.23:26:15.58#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:15.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:15.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:15.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:15.64#ibcon#enter wrdev, iclass 28, count 2 2006.257.23:26:15.64#ibcon#first serial, iclass 28, count 2 2006.257.23:26:15.64#ibcon#enter sib2, iclass 28, count 2 2006.257.23:26:15.64#ibcon#flushed, iclass 28, count 2 2006.257.23:26:15.64#ibcon#about to write, iclass 28, count 2 2006.257.23:26:15.64#ibcon#wrote, iclass 28, count 2 2006.257.23:26:15.64#ibcon#about to read 3, iclass 28, count 2 2006.257.23:26:15.66#ibcon#read 3, iclass 28, count 2 2006.257.23:26:15.66#ibcon#about to read 4, iclass 28, count 2 2006.257.23:26:15.66#ibcon#read 4, iclass 28, count 2 2006.257.23:26:15.66#ibcon#about to read 5, iclass 28, count 2 2006.257.23:26:15.66#ibcon#read 5, iclass 28, count 2 2006.257.23:26:15.66#ibcon#about to read 6, iclass 28, count 2 2006.257.23:26:15.66#ibcon#read 6, iclass 28, count 2 2006.257.23:26:15.66#ibcon#end of sib2, iclass 28, count 2 2006.257.23:26:15.66#ibcon#*mode == 0, iclass 28, count 2 2006.257.23:26:15.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.23:26:15.66#ibcon#[25=AT04-07\r\n] 2006.257.23:26:15.66#ibcon#*before write, iclass 28, count 2 2006.257.23:26:15.66#ibcon#enter sib2, iclass 28, count 2 2006.257.23:26:15.66#ibcon#flushed, iclass 28, count 2 2006.257.23:26:15.66#ibcon#about to write, iclass 28, count 2 2006.257.23:26:15.66#ibcon#wrote, iclass 28, count 2 2006.257.23:26:15.66#ibcon#about to read 3, iclass 28, count 2 2006.257.23:26:15.69#ibcon#read 3, iclass 28, count 2 2006.257.23:26:15.69#ibcon#about to read 4, iclass 28, count 2 2006.257.23:26:15.69#ibcon#read 4, iclass 28, count 2 2006.257.23:26:15.69#ibcon#about to read 5, iclass 28, count 2 2006.257.23:26:15.69#ibcon#read 5, iclass 28, count 2 2006.257.23:26:15.69#ibcon#about to read 6, iclass 28, count 2 2006.257.23:26:15.69#ibcon#read 6, iclass 28, count 2 2006.257.23:26:15.69#ibcon#end of sib2, iclass 28, count 2 2006.257.23:26:15.69#ibcon#*after write, iclass 28, count 2 2006.257.23:26:15.69#ibcon#*before return 0, iclass 28, count 2 2006.257.23:26:15.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:15.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:15.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.23:26:15.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:15.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:15.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:15.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:15.81#ibcon#enter wrdev, iclass 28, count 0 2006.257.23:26:15.81#ibcon#first serial, iclass 28, count 0 2006.257.23:26:15.81#ibcon#enter sib2, iclass 28, count 0 2006.257.23:26:15.81#ibcon#flushed, iclass 28, count 0 2006.257.23:26:15.81#ibcon#about to write, iclass 28, count 0 2006.257.23:26:15.81#ibcon#wrote, iclass 28, count 0 2006.257.23:26:15.81#ibcon#about to read 3, iclass 28, count 0 2006.257.23:26:15.83#ibcon#read 3, iclass 28, count 0 2006.257.23:26:15.83#ibcon#about to read 4, iclass 28, count 0 2006.257.23:26:15.83#ibcon#read 4, iclass 28, count 0 2006.257.23:26:15.83#ibcon#about to read 5, iclass 28, count 0 2006.257.23:26:15.83#ibcon#read 5, iclass 28, count 0 2006.257.23:26:15.83#ibcon#about to read 6, iclass 28, count 0 2006.257.23:26:15.83#ibcon#read 6, iclass 28, count 0 2006.257.23:26:15.83#ibcon#end of sib2, iclass 28, count 0 2006.257.23:26:15.83#ibcon#*mode == 0, iclass 28, count 0 2006.257.23:26:15.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.23:26:15.83#ibcon#[25=USB\r\n] 2006.257.23:26:15.83#ibcon#*before write, iclass 28, count 0 2006.257.23:26:15.83#ibcon#enter sib2, iclass 28, count 0 2006.257.23:26:15.83#ibcon#flushed, iclass 28, count 0 2006.257.23:26:15.83#ibcon#about to write, iclass 28, count 0 2006.257.23:26:15.83#ibcon#wrote, iclass 28, count 0 2006.257.23:26:15.83#ibcon#about to read 3, iclass 28, count 0 2006.257.23:26:15.86#ibcon#read 3, iclass 28, count 0 2006.257.23:26:15.86#ibcon#about to read 4, iclass 28, count 0 2006.257.23:26:15.86#ibcon#read 4, iclass 28, count 0 2006.257.23:26:15.86#ibcon#about to read 5, iclass 28, count 0 2006.257.23:26:15.86#ibcon#read 5, iclass 28, count 0 2006.257.23:26:15.86#ibcon#about to read 6, iclass 28, count 0 2006.257.23:26:15.86#ibcon#read 6, iclass 28, count 0 2006.257.23:26:15.86#ibcon#end of sib2, iclass 28, count 0 2006.257.23:26:15.86#ibcon#*after write, iclass 28, count 0 2006.257.23:26:15.86#ibcon#*before return 0, iclass 28, count 0 2006.257.23:26:15.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:15.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:15.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.23:26:15.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.23:26:15.86$vck44/valo=5,734.99 2006.257.23:26:15.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.23:26:15.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.23:26:15.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:15.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:15.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:15.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:15.86#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:26:15.86#ibcon#first serial, iclass 30, count 0 2006.257.23:26:15.86#ibcon#enter sib2, iclass 30, count 0 2006.257.23:26:15.86#ibcon#flushed, iclass 30, count 0 2006.257.23:26:15.86#ibcon#about to write, iclass 30, count 0 2006.257.23:26:15.86#ibcon#wrote, iclass 30, count 0 2006.257.23:26:15.86#ibcon#about to read 3, iclass 30, count 0 2006.257.23:26:15.88#ibcon#read 3, iclass 30, count 0 2006.257.23:26:15.88#ibcon#about to read 4, iclass 30, count 0 2006.257.23:26:15.88#ibcon#read 4, iclass 30, count 0 2006.257.23:26:15.88#ibcon#about to read 5, iclass 30, count 0 2006.257.23:26:15.88#ibcon#read 5, iclass 30, count 0 2006.257.23:26:15.88#ibcon#about to read 6, iclass 30, count 0 2006.257.23:26:15.88#ibcon#read 6, iclass 30, count 0 2006.257.23:26:15.88#ibcon#end of sib2, iclass 30, count 0 2006.257.23:26:15.88#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:26:15.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:26:15.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:26:15.88#ibcon#*before write, iclass 30, count 0 2006.257.23:26:15.88#ibcon#enter sib2, iclass 30, count 0 2006.257.23:26:15.88#ibcon#flushed, iclass 30, count 0 2006.257.23:26:15.88#ibcon#about to write, iclass 30, count 0 2006.257.23:26:15.88#ibcon#wrote, iclass 30, count 0 2006.257.23:26:15.88#ibcon#about to read 3, iclass 30, count 0 2006.257.23:26:15.92#ibcon#read 3, iclass 30, count 0 2006.257.23:26:15.92#ibcon#about to read 4, iclass 30, count 0 2006.257.23:26:15.92#ibcon#read 4, iclass 30, count 0 2006.257.23:26:15.92#ibcon#about to read 5, iclass 30, count 0 2006.257.23:26:15.92#ibcon#read 5, iclass 30, count 0 2006.257.23:26:15.92#ibcon#about to read 6, iclass 30, count 0 2006.257.23:26:15.92#ibcon#read 6, iclass 30, count 0 2006.257.23:26:15.92#ibcon#end of sib2, iclass 30, count 0 2006.257.23:26:15.92#ibcon#*after write, iclass 30, count 0 2006.257.23:26:15.92#ibcon#*before return 0, iclass 30, count 0 2006.257.23:26:15.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:15.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:15.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:26:15.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:26:15.92$vck44/va=5,4 2006.257.23:26:15.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.23:26:15.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.23:26:15.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:15.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:15.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:15.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:15.98#ibcon#enter wrdev, iclass 32, count 2 2006.257.23:26:15.98#ibcon#first serial, iclass 32, count 2 2006.257.23:26:15.98#ibcon#enter sib2, iclass 32, count 2 2006.257.23:26:15.98#ibcon#flushed, iclass 32, count 2 2006.257.23:26:15.98#ibcon#about to write, iclass 32, count 2 2006.257.23:26:15.98#ibcon#wrote, iclass 32, count 2 2006.257.23:26:15.98#ibcon#about to read 3, iclass 32, count 2 2006.257.23:26:16.00#ibcon#read 3, iclass 32, count 2 2006.257.23:26:16.00#ibcon#about to read 4, iclass 32, count 2 2006.257.23:26:16.00#ibcon#read 4, iclass 32, count 2 2006.257.23:26:16.00#ibcon#about to read 5, iclass 32, count 2 2006.257.23:26:16.00#ibcon#read 5, iclass 32, count 2 2006.257.23:26:16.00#ibcon#about to read 6, iclass 32, count 2 2006.257.23:26:16.00#ibcon#read 6, iclass 32, count 2 2006.257.23:26:16.00#ibcon#end of sib2, iclass 32, count 2 2006.257.23:26:16.00#ibcon#*mode == 0, iclass 32, count 2 2006.257.23:26:16.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.23:26:16.00#ibcon#[25=AT05-04\r\n] 2006.257.23:26:16.00#ibcon#*before write, iclass 32, count 2 2006.257.23:26:16.00#ibcon#enter sib2, iclass 32, count 2 2006.257.23:26:16.00#ibcon#flushed, iclass 32, count 2 2006.257.23:26:16.00#ibcon#about to write, iclass 32, count 2 2006.257.23:26:16.00#ibcon#wrote, iclass 32, count 2 2006.257.23:26:16.00#ibcon#about to read 3, iclass 32, count 2 2006.257.23:26:16.03#ibcon#read 3, iclass 32, count 2 2006.257.23:26:16.03#ibcon#about to read 4, iclass 32, count 2 2006.257.23:26:16.03#ibcon#read 4, iclass 32, count 2 2006.257.23:26:16.03#ibcon#about to read 5, iclass 32, count 2 2006.257.23:26:16.03#ibcon#read 5, iclass 32, count 2 2006.257.23:26:16.03#ibcon#about to read 6, iclass 32, count 2 2006.257.23:26:16.03#ibcon#read 6, iclass 32, count 2 2006.257.23:26:16.03#ibcon#end of sib2, iclass 32, count 2 2006.257.23:26:16.03#ibcon#*after write, iclass 32, count 2 2006.257.23:26:16.03#ibcon#*before return 0, iclass 32, count 2 2006.257.23:26:16.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:16.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:16.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.23:26:16.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:16.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:16.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:16.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:16.15#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:26:16.15#ibcon#first serial, iclass 32, count 0 2006.257.23:26:16.15#ibcon#enter sib2, iclass 32, count 0 2006.257.23:26:16.15#ibcon#flushed, iclass 32, count 0 2006.257.23:26:16.15#ibcon#about to write, iclass 32, count 0 2006.257.23:26:16.15#ibcon#wrote, iclass 32, count 0 2006.257.23:26:16.15#ibcon#about to read 3, iclass 32, count 0 2006.257.23:26:16.17#ibcon#read 3, iclass 32, count 0 2006.257.23:26:16.17#ibcon#about to read 4, iclass 32, count 0 2006.257.23:26:16.17#ibcon#read 4, iclass 32, count 0 2006.257.23:26:16.17#ibcon#about to read 5, iclass 32, count 0 2006.257.23:26:16.17#ibcon#read 5, iclass 32, count 0 2006.257.23:26:16.17#ibcon#about to read 6, iclass 32, count 0 2006.257.23:26:16.17#ibcon#read 6, iclass 32, count 0 2006.257.23:26:16.17#ibcon#end of sib2, iclass 32, count 0 2006.257.23:26:16.17#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:26:16.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:26:16.17#ibcon#[25=USB\r\n] 2006.257.23:26:16.17#ibcon#*before write, iclass 32, count 0 2006.257.23:26:16.17#ibcon#enter sib2, iclass 32, count 0 2006.257.23:26:16.17#ibcon#flushed, iclass 32, count 0 2006.257.23:26:16.17#ibcon#about to write, iclass 32, count 0 2006.257.23:26:16.17#ibcon#wrote, iclass 32, count 0 2006.257.23:26:16.17#ibcon#about to read 3, iclass 32, count 0 2006.257.23:26:16.20#ibcon#read 3, iclass 32, count 0 2006.257.23:26:16.20#ibcon#about to read 4, iclass 32, count 0 2006.257.23:26:16.20#ibcon#read 4, iclass 32, count 0 2006.257.23:26:16.20#ibcon#about to read 5, iclass 32, count 0 2006.257.23:26:16.20#ibcon#read 5, iclass 32, count 0 2006.257.23:26:16.20#ibcon#about to read 6, iclass 32, count 0 2006.257.23:26:16.20#ibcon#read 6, iclass 32, count 0 2006.257.23:26:16.20#ibcon#end of sib2, iclass 32, count 0 2006.257.23:26:16.20#ibcon#*after write, iclass 32, count 0 2006.257.23:26:16.20#ibcon#*before return 0, iclass 32, count 0 2006.257.23:26:16.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:16.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:16.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:26:16.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:26:16.20$vck44/valo=6,814.99 2006.257.23:26:16.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.23:26:16.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.23:26:16.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:16.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:16.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:16.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:16.20#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:26:16.20#ibcon#first serial, iclass 34, count 0 2006.257.23:26:16.20#ibcon#enter sib2, iclass 34, count 0 2006.257.23:26:16.20#ibcon#flushed, iclass 34, count 0 2006.257.23:26:16.20#ibcon#about to write, iclass 34, count 0 2006.257.23:26:16.20#ibcon#wrote, iclass 34, count 0 2006.257.23:26:16.20#ibcon#about to read 3, iclass 34, count 0 2006.257.23:26:16.22#ibcon#read 3, iclass 34, count 0 2006.257.23:26:16.22#ibcon#about to read 4, iclass 34, count 0 2006.257.23:26:16.22#ibcon#read 4, iclass 34, count 0 2006.257.23:26:16.22#ibcon#about to read 5, iclass 34, count 0 2006.257.23:26:16.22#ibcon#read 5, iclass 34, count 0 2006.257.23:26:16.22#ibcon#about to read 6, iclass 34, count 0 2006.257.23:26:16.22#ibcon#read 6, iclass 34, count 0 2006.257.23:26:16.22#ibcon#end of sib2, iclass 34, count 0 2006.257.23:26:16.22#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:26:16.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:26:16.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:26:16.22#ibcon#*before write, iclass 34, count 0 2006.257.23:26:16.22#ibcon#enter sib2, iclass 34, count 0 2006.257.23:26:16.22#ibcon#flushed, iclass 34, count 0 2006.257.23:26:16.22#ibcon#about to write, iclass 34, count 0 2006.257.23:26:16.22#ibcon#wrote, iclass 34, count 0 2006.257.23:26:16.22#ibcon#about to read 3, iclass 34, count 0 2006.257.23:26:16.26#ibcon#read 3, iclass 34, count 0 2006.257.23:26:16.26#ibcon#about to read 4, iclass 34, count 0 2006.257.23:26:16.26#ibcon#read 4, iclass 34, count 0 2006.257.23:26:16.26#ibcon#about to read 5, iclass 34, count 0 2006.257.23:26:16.26#ibcon#read 5, iclass 34, count 0 2006.257.23:26:16.26#ibcon#about to read 6, iclass 34, count 0 2006.257.23:26:16.26#ibcon#read 6, iclass 34, count 0 2006.257.23:26:16.26#ibcon#end of sib2, iclass 34, count 0 2006.257.23:26:16.26#ibcon#*after write, iclass 34, count 0 2006.257.23:26:16.26#ibcon#*before return 0, iclass 34, count 0 2006.257.23:26:16.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:16.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:16.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:26:16.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:26:16.26$vck44/va=6,4 2006.257.23:26:16.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.23:26:16.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.23:26:16.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:16.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:16.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:16.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:16.32#ibcon#enter wrdev, iclass 36, count 2 2006.257.23:26:16.32#ibcon#first serial, iclass 36, count 2 2006.257.23:26:16.32#ibcon#enter sib2, iclass 36, count 2 2006.257.23:26:16.32#ibcon#flushed, iclass 36, count 2 2006.257.23:26:16.32#ibcon#about to write, iclass 36, count 2 2006.257.23:26:16.32#ibcon#wrote, iclass 36, count 2 2006.257.23:26:16.32#ibcon#about to read 3, iclass 36, count 2 2006.257.23:26:16.34#ibcon#read 3, iclass 36, count 2 2006.257.23:26:16.34#ibcon#about to read 4, iclass 36, count 2 2006.257.23:26:16.34#ibcon#read 4, iclass 36, count 2 2006.257.23:26:16.34#ibcon#about to read 5, iclass 36, count 2 2006.257.23:26:16.34#ibcon#read 5, iclass 36, count 2 2006.257.23:26:16.34#ibcon#about to read 6, iclass 36, count 2 2006.257.23:26:16.34#ibcon#read 6, iclass 36, count 2 2006.257.23:26:16.34#ibcon#end of sib2, iclass 36, count 2 2006.257.23:26:16.34#ibcon#*mode == 0, iclass 36, count 2 2006.257.23:26:16.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.23:26:16.34#ibcon#[25=AT06-04\r\n] 2006.257.23:26:16.34#ibcon#*before write, iclass 36, count 2 2006.257.23:26:16.34#ibcon#enter sib2, iclass 36, count 2 2006.257.23:26:16.34#ibcon#flushed, iclass 36, count 2 2006.257.23:26:16.34#ibcon#about to write, iclass 36, count 2 2006.257.23:26:16.34#ibcon#wrote, iclass 36, count 2 2006.257.23:26:16.34#ibcon#about to read 3, iclass 36, count 2 2006.257.23:26:16.37#ibcon#read 3, iclass 36, count 2 2006.257.23:26:16.37#ibcon#about to read 4, iclass 36, count 2 2006.257.23:26:16.37#ibcon#read 4, iclass 36, count 2 2006.257.23:26:16.37#ibcon#about to read 5, iclass 36, count 2 2006.257.23:26:16.37#ibcon#read 5, iclass 36, count 2 2006.257.23:26:16.37#ibcon#about to read 6, iclass 36, count 2 2006.257.23:26:16.37#ibcon#read 6, iclass 36, count 2 2006.257.23:26:16.37#ibcon#end of sib2, iclass 36, count 2 2006.257.23:26:16.37#ibcon#*after write, iclass 36, count 2 2006.257.23:26:16.37#ibcon#*before return 0, iclass 36, count 2 2006.257.23:26:16.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:16.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:16.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.23:26:16.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:16.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:16.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:16.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:16.49#ibcon#enter wrdev, iclass 36, count 0 2006.257.23:26:16.49#ibcon#first serial, iclass 36, count 0 2006.257.23:26:16.49#ibcon#enter sib2, iclass 36, count 0 2006.257.23:26:16.49#ibcon#flushed, iclass 36, count 0 2006.257.23:26:16.49#ibcon#about to write, iclass 36, count 0 2006.257.23:26:16.49#ibcon#wrote, iclass 36, count 0 2006.257.23:26:16.49#ibcon#about to read 3, iclass 36, count 0 2006.257.23:26:16.51#ibcon#read 3, iclass 36, count 0 2006.257.23:26:16.51#ibcon#about to read 4, iclass 36, count 0 2006.257.23:26:16.51#ibcon#read 4, iclass 36, count 0 2006.257.23:26:16.51#ibcon#about to read 5, iclass 36, count 0 2006.257.23:26:16.51#ibcon#read 5, iclass 36, count 0 2006.257.23:26:16.51#ibcon#about to read 6, iclass 36, count 0 2006.257.23:26:16.51#ibcon#read 6, iclass 36, count 0 2006.257.23:26:16.51#ibcon#end of sib2, iclass 36, count 0 2006.257.23:26:16.51#ibcon#*mode == 0, iclass 36, count 0 2006.257.23:26:16.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.23:26:16.51#ibcon#[25=USB\r\n] 2006.257.23:26:16.51#ibcon#*before write, iclass 36, count 0 2006.257.23:26:16.51#ibcon#enter sib2, iclass 36, count 0 2006.257.23:26:16.51#ibcon#flushed, iclass 36, count 0 2006.257.23:26:16.51#ibcon#about to write, iclass 36, count 0 2006.257.23:26:16.51#ibcon#wrote, iclass 36, count 0 2006.257.23:26:16.51#ibcon#about to read 3, iclass 36, count 0 2006.257.23:26:16.54#ibcon#read 3, iclass 36, count 0 2006.257.23:26:16.54#ibcon#about to read 4, iclass 36, count 0 2006.257.23:26:16.54#ibcon#read 4, iclass 36, count 0 2006.257.23:26:16.54#ibcon#about to read 5, iclass 36, count 0 2006.257.23:26:16.54#ibcon#read 5, iclass 36, count 0 2006.257.23:26:16.54#ibcon#about to read 6, iclass 36, count 0 2006.257.23:26:16.54#ibcon#read 6, iclass 36, count 0 2006.257.23:26:16.54#ibcon#end of sib2, iclass 36, count 0 2006.257.23:26:16.54#ibcon#*after write, iclass 36, count 0 2006.257.23:26:16.54#ibcon#*before return 0, iclass 36, count 0 2006.257.23:26:16.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:16.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:16.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.23:26:16.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.23:26:16.54$vck44/valo=7,864.99 2006.257.23:26:16.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.23:26:16.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.23:26:16.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:16.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:16.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:16.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:16.54#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:26:16.54#ibcon#first serial, iclass 38, count 0 2006.257.23:26:16.54#ibcon#enter sib2, iclass 38, count 0 2006.257.23:26:16.54#ibcon#flushed, iclass 38, count 0 2006.257.23:26:16.54#ibcon#about to write, iclass 38, count 0 2006.257.23:26:16.54#ibcon#wrote, iclass 38, count 0 2006.257.23:26:16.54#ibcon#about to read 3, iclass 38, count 0 2006.257.23:26:16.56#ibcon#read 3, iclass 38, count 0 2006.257.23:26:16.56#ibcon#about to read 4, iclass 38, count 0 2006.257.23:26:16.56#ibcon#read 4, iclass 38, count 0 2006.257.23:26:16.56#ibcon#about to read 5, iclass 38, count 0 2006.257.23:26:16.56#ibcon#read 5, iclass 38, count 0 2006.257.23:26:16.56#ibcon#about to read 6, iclass 38, count 0 2006.257.23:26:16.56#ibcon#read 6, iclass 38, count 0 2006.257.23:26:16.56#ibcon#end of sib2, iclass 38, count 0 2006.257.23:26:16.56#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:26:16.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:26:16.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:26:16.56#ibcon#*before write, iclass 38, count 0 2006.257.23:26:16.56#ibcon#enter sib2, iclass 38, count 0 2006.257.23:26:16.56#ibcon#flushed, iclass 38, count 0 2006.257.23:26:16.56#ibcon#about to write, iclass 38, count 0 2006.257.23:26:16.56#ibcon#wrote, iclass 38, count 0 2006.257.23:26:16.56#ibcon#about to read 3, iclass 38, count 0 2006.257.23:26:16.60#ibcon#read 3, iclass 38, count 0 2006.257.23:26:16.60#ibcon#about to read 4, iclass 38, count 0 2006.257.23:26:16.60#ibcon#read 4, iclass 38, count 0 2006.257.23:26:16.60#ibcon#about to read 5, iclass 38, count 0 2006.257.23:26:16.60#ibcon#read 5, iclass 38, count 0 2006.257.23:26:16.60#ibcon#about to read 6, iclass 38, count 0 2006.257.23:26:16.60#ibcon#read 6, iclass 38, count 0 2006.257.23:26:16.60#ibcon#end of sib2, iclass 38, count 0 2006.257.23:26:16.60#ibcon#*after write, iclass 38, count 0 2006.257.23:26:16.60#ibcon#*before return 0, iclass 38, count 0 2006.257.23:26:16.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:16.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:16.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:26:16.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:26:16.60$vck44/va=7,4 2006.257.23:26:16.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.23:26:16.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.23:26:16.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:16.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:16.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:16.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:16.66#ibcon#enter wrdev, iclass 40, count 2 2006.257.23:26:16.66#ibcon#first serial, iclass 40, count 2 2006.257.23:26:16.66#ibcon#enter sib2, iclass 40, count 2 2006.257.23:26:16.66#ibcon#flushed, iclass 40, count 2 2006.257.23:26:16.66#ibcon#about to write, iclass 40, count 2 2006.257.23:26:16.66#ibcon#wrote, iclass 40, count 2 2006.257.23:26:16.66#ibcon#about to read 3, iclass 40, count 2 2006.257.23:26:16.68#ibcon#read 3, iclass 40, count 2 2006.257.23:26:16.68#ibcon#about to read 4, iclass 40, count 2 2006.257.23:26:16.68#ibcon#read 4, iclass 40, count 2 2006.257.23:26:16.68#ibcon#about to read 5, iclass 40, count 2 2006.257.23:26:16.68#ibcon#read 5, iclass 40, count 2 2006.257.23:26:16.68#ibcon#about to read 6, iclass 40, count 2 2006.257.23:26:16.68#ibcon#read 6, iclass 40, count 2 2006.257.23:26:16.68#ibcon#end of sib2, iclass 40, count 2 2006.257.23:26:16.68#ibcon#*mode == 0, iclass 40, count 2 2006.257.23:26:16.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.23:26:16.68#ibcon#[25=AT07-04\r\n] 2006.257.23:26:16.68#ibcon#*before write, iclass 40, count 2 2006.257.23:26:16.68#ibcon#enter sib2, iclass 40, count 2 2006.257.23:26:16.68#ibcon#flushed, iclass 40, count 2 2006.257.23:26:16.68#ibcon#about to write, iclass 40, count 2 2006.257.23:26:16.68#ibcon#wrote, iclass 40, count 2 2006.257.23:26:16.68#ibcon#about to read 3, iclass 40, count 2 2006.257.23:26:16.71#ibcon#read 3, iclass 40, count 2 2006.257.23:26:16.71#ibcon#about to read 4, iclass 40, count 2 2006.257.23:26:16.71#ibcon#read 4, iclass 40, count 2 2006.257.23:26:16.71#ibcon#about to read 5, iclass 40, count 2 2006.257.23:26:16.71#ibcon#read 5, iclass 40, count 2 2006.257.23:26:16.71#ibcon#about to read 6, iclass 40, count 2 2006.257.23:26:16.71#ibcon#read 6, iclass 40, count 2 2006.257.23:26:16.71#ibcon#end of sib2, iclass 40, count 2 2006.257.23:26:16.71#ibcon#*after write, iclass 40, count 2 2006.257.23:26:16.71#ibcon#*before return 0, iclass 40, count 2 2006.257.23:26:16.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:16.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:16.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.23:26:16.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:16.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:16.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:16.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:16.83#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:26:16.83#ibcon#first serial, iclass 40, count 0 2006.257.23:26:16.83#ibcon#enter sib2, iclass 40, count 0 2006.257.23:26:16.83#ibcon#flushed, iclass 40, count 0 2006.257.23:26:16.83#ibcon#about to write, iclass 40, count 0 2006.257.23:26:16.83#ibcon#wrote, iclass 40, count 0 2006.257.23:26:16.83#ibcon#about to read 3, iclass 40, count 0 2006.257.23:26:16.85#ibcon#read 3, iclass 40, count 0 2006.257.23:26:16.85#ibcon#about to read 4, iclass 40, count 0 2006.257.23:26:16.85#ibcon#read 4, iclass 40, count 0 2006.257.23:26:16.85#ibcon#about to read 5, iclass 40, count 0 2006.257.23:26:16.85#ibcon#read 5, iclass 40, count 0 2006.257.23:26:16.85#ibcon#about to read 6, iclass 40, count 0 2006.257.23:26:16.85#ibcon#read 6, iclass 40, count 0 2006.257.23:26:16.85#ibcon#end of sib2, iclass 40, count 0 2006.257.23:26:16.85#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:26:16.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:26:16.85#ibcon#[25=USB\r\n] 2006.257.23:26:16.85#ibcon#*before write, iclass 40, count 0 2006.257.23:26:16.85#ibcon#enter sib2, iclass 40, count 0 2006.257.23:26:16.85#ibcon#flushed, iclass 40, count 0 2006.257.23:26:16.85#ibcon#about to write, iclass 40, count 0 2006.257.23:26:16.85#ibcon#wrote, iclass 40, count 0 2006.257.23:26:16.85#ibcon#about to read 3, iclass 40, count 0 2006.257.23:26:16.88#ibcon#read 3, iclass 40, count 0 2006.257.23:26:16.88#ibcon#about to read 4, iclass 40, count 0 2006.257.23:26:16.88#ibcon#read 4, iclass 40, count 0 2006.257.23:26:16.88#ibcon#about to read 5, iclass 40, count 0 2006.257.23:26:16.88#ibcon#read 5, iclass 40, count 0 2006.257.23:26:16.88#ibcon#about to read 6, iclass 40, count 0 2006.257.23:26:16.88#ibcon#read 6, iclass 40, count 0 2006.257.23:26:16.88#ibcon#end of sib2, iclass 40, count 0 2006.257.23:26:16.88#ibcon#*after write, iclass 40, count 0 2006.257.23:26:16.88#ibcon#*before return 0, iclass 40, count 0 2006.257.23:26:16.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:16.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:16.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:26:16.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:26:16.88$vck44/valo=8,884.99 2006.257.23:26:16.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.23:26:16.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.23:26:16.88#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:16.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:16.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:16.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:16.88#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:26:16.88#ibcon#first serial, iclass 4, count 0 2006.257.23:26:16.88#ibcon#enter sib2, iclass 4, count 0 2006.257.23:26:16.88#ibcon#flushed, iclass 4, count 0 2006.257.23:26:16.88#ibcon#about to write, iclass 4, count 0 2006.257.23:26:16.88#ibcon#wrote, iclass 4, count 0 2006.257.23:26:16.88#ibcon#about to read 3, iclass 4, count 0 2006.257.23:26:16.90#ibcon#read 3, iclass 4, count 0 2006.257.23:26:16.90#ibcon#about to read 4, iclass 4, count 0 2006.257.23:26:16.90#ibcon#read 4, iclass 4, count 0 2006.257.23:26:16.90#ibcon#about to read 5, iclass 4, count 0 2006.257.23:26:16.90#ibcon#read 5, iclass 4, count 0 2006.257.23:26:16.90#ibcon#about to read 6, iclass 4, count 0 2006.257.23:26:16.90#ibcon#read 6, iclass 4, count 0 2006.257.23:26:16.90#ibcon#end of sib2, iclass 4, count 0 2006.257.23:26:16.90#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:26:16.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:26:16.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:26:16.90#ibcon#*before write, iclass 4, count 0 2006.257.23:26:16.90#ibcon#enter sib2, iclass 4, count 0 2006.257.23:26:16.90#ibcon#flushed, iclass 4, count 0 2006.257.23:26:16.90#ibcon#about to write, iclass 4, count 0 2006.257.23:26:16.90#ibcon#wrote, iclass 4, count 0 2006.257.23:26:16.90#ibcon#about to read 3, iclass 4, count 0 2006.257.23:26:16.94#ibcon#read 3, iclass 4, count 0 2006.257.23:26:16.94#ibcon#about to read 4, iclass 4, count 0 2006.257.23:26:16.94#ibcon#read 4, iclass 4, count 0 2006.257.23:26:16.94#ibcon#about to read 5, iclass 4, count 0 2006.257.23:26:16.94#ibcon#read 5, iclass 4, count 0 2006.257.23:26:16.94#ibcon#about to read 6, iclass 4, count 0 2006.257.23:26:16.94#ibcon#read 6, iclass 4, count 0 2006.257.23:26:16.94#ibcon#end of sib2, iclass 4, count 0 2006.257.23:26:16.94#ibcon#*after write, iclass 4, count 0 2006.257.23:26:16.94#ibcon#*before return 0, iclass 4, count 0 2006.257.23:26:16.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:16.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:16.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:26:16.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:26:16.94$vck44/va=8,4 2006.257.23:26:16.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.23:26:16.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.23:26:16.94#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:16.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:26:17.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:26:17.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:26:17.00#ibcon#enter wrdev, iclass 6, count 2 2006.257.23:26:17.00#ibcon#first serial, iclass 6, count 2 2006.257.23:26:17.00#ibcon#enter sib2, iclass 6, count 2 2006.257.23:26:17.00#ibcon#flushed, iclass 6, count 2 2006.257.23:26:17.00#ibcon#about to write, iclass 6, count 2 2006.257.23:26:17.00#ibcon#wrote, iclass 6, count 2 2006.257.23:26:17.00#ibcon#about to read 3, iclass 6, count 2 2006.257.23:26:17.02#ibcon#read 3, iclass 6, count 2 2006.257.23:26:17.02#ibcon#about to read 4, iclass 6, count 2 2006.257.23:26:17.02#ibcon#read 4, iclass 6, count 2 2006.257.23:26:17.02#ibcon#about to read 5, iclass 6, count 2 2006.257.23:26:17.02#ibcon#read 5, iclass 6, count 2 2006.257.23:26:17.02#ibcon#about to read 6, iclass 6, count 2 2006.257.23:26:17.02#ibcon#read 6, iclass 6, count 2 2006.257.23:26:17.02#ibcon#end of sib2, iclass 6, count 2 2006.257.23:26:17.02#ibcon#*mode == 0, iclass 6, count 2 2006.257.23:26:17.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.23:26:17.02#ibcon#[25=AT08-04\r\n] 2006.257.23:26:17.02#ibcon#*before write, iclass 6, count 2 2006.257.23:26:17.02#ibcon#enter sib2, iclass 6, count 2 2006.257.23:26:17.02#ibcon#flushed, iclass 6, count 2 2006.257.23:26:17.02#ibcon#about to write, iclass 6, count 2 2006.257.23:26:17.02#ibcon#wrote, iclass 6, count 2 2006.257.23:26:17.02#ibcon#about to read 3, iclass 6, count 2 2006.257.23:26:17.05#ibcon#read 3, iclass 6, count 2 2006.257.23:26:17.05#ibcon#about to read 4, iclass 6, count 2 2006.257.23:26:17.05#ibcon#read 4, iclass 6, count 2 2006.257.23:26:17.05#ibcon#about to read 5, iclass 6, count 2 2006.257.23:26:17.05#ibcon#read 5, iclass 6, count 2 2006.257.23:26:17.05#ibcon#about to read 6, iclass 6, count 2 2006.257.23:26:17.05#ibcon#read 6, iclass 6, count 2 2006.257.23:26:17.05#ibcon#end of sib2, iclass 6, count 2 2006.257.23:26:17.05#ibcon#*after write, iclass 6, count 2 2006.257.23:26:17.05#ibcon#*before return 0, iclass 6, count 2 2006.257.23:26:17.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:26:17.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:26:17.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.23:26:17.05#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:17.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:26:17.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:26:17.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:26:17.17#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:26:17.17#ibcon#first serial, iclass 6, count 0 2006.257.23:26:17.17#ibcon#enter sib2, iclass 6, count 0 2006.257.23:26:17.17#ibcon#flushed, iclass 6, count 0 2006.257.23:26:17.17#ibcon#about to write, iclass 6, count 0 2006.257.23:26:17.17#ibcon#wrote, iclass 6, count 0 2006.257.23:26:17.17#ibcon#about to read 3, iclass 6, count 0 2006.257.23:26:17.19#ibcon#read 3, iclass 6, count 0 2006.257.23:26:17.19#ibcon#about to read 4, iclass 6, count 0 2006.257.23:26:17.19#ibcon#read 4, iclass 6, count 0 2006.257.23:26:17.19#ibcon#about to read 5, iclass 6, count 0 2006.257.23:26:17.19#ibcon#read 5, iclass 6, count 0 2006.257.23:26:17.19#ibcon#about to read 6, iclass 6, count 0 2006.257.23:26:17.19#ibcon#read 6, iclass 6, count 0 2006.257.23:26:17.19#ibcon#end of sib2, iclass 6, count 0 2006.257.23:26:17.19#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:26:17.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:26:17.19#ibcon#[25=USB\r\n] 2006.257.23:26:17.19#ibcon#*before write, iclass 6, count 0 2006.257.23:26:17.19#ibcon#enter sib2, iclass 6, count 0 2006.257.23:26:17.19#ibcon#flushed, iclass 6, count 0 2006.257.23:26:17.19#ibcon#about to write, iclass 6, count 0 2006.257.23:26:17.19#ibcon#wrote, iclass 6, count 0 2006.257.23:26:17.19#ibcon#about to read 3, iclass 6, count 0 2006.257.23:26:17.22#ibcon#read 3, iclass 6, count 0 2006.257.23:26:17.22#ibcon#about to read 4, iclass 6, count 0 2006.257.23:26:17.22#ibcon#read 4, iclass 6, count 0 2006.257.23:26:17.22#ibcon#about to read 5, iclass 6, count 0 2006.257.23:26:17.22#ibcon#read 5, iclass 6, count 0 2006.257.23:26:17.22#ibcon#about to read 6, iclass 6, count 0 2006.257.23:26:17.22#ibcon#read 6, iclass 6, count 0 2006.257.23:26:17.22#ibcon#end of sib2, iclass 6, count 0 2006.257.23:26:17.22#ibcon#*after write, iclass 6, count 0 2006.257.23:26:17.22#ibcon#*before return 0, iclass 6, count 0 2006.257.23:26:17.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:26:17.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:26:17.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:26:17.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:26:17.22$vck44/vblo=1,629.99 2006.257.23:26:17.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.23:26:17.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.23:26:17.22#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:17.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:26:17.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:26:17.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:26:17.22#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:26:17.22#ibcon#first serial, iclass 10, count 0 2006.257.23:26:17.22#ibcon#enter sib2, iclass 10, count 0 2006.257.23:26:17.22#ibcon#flushed, iclass 10, count 0 2006.257.23:26:17.22#ibcon#about to write, iclass 10, count 0 2006.257.23:26:17.22#ibcon#wrote, iclass 10, count 0 2006.257.23:26:17.22#ibcon#about to read 3, iclass 10, count 0 2006.257.23:26:17.24#ibcon#read 3, iclass 10, count 0 2006.257.23:26:17.24#ibcon#about to read 4, iclass 10, count 0 2006.257.23:26:17.24#ibcon#read 4, iclass 10, count 0 2006.257.23:26:17.24#ibcon#about to read 5, iclass 10, count 0 2006.257.23:26:17.24#ibcon#read 5, iclass 10, count 0 2006.257.23:26:17.24#ibcon#about to read 6, iclass 10, count 0 2006.257.23:26:17.24#ibcon#read 6, iclass 10, count 0 2006.257.23:26:17.24#ibcon#end of sib2, iclass 10, count 0 2006.257.23:26:17.24#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:26:17.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:26:17.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:26:17.24#ibcon#*before write, iclass 10, count 0 2006.257.23:26:17.24#ibcon#enter sib2, iclass 10, count 0 2006.257.23:26:17.24#ibcon#flushed, iclass 10, count 0 2006.257.23:26:17.24#ibcon#about to write, iclass 10, count 0 2006.257.23:26:17.24#ibcon#wrote, iclass 10, count 0 2006.257.23:26:17.24#ibcon#about to read 3, iclass 10, count 0 2006.257.23:26:17.28#ibcon#read 3, iclass 10, count 0 2006.257.23:26:17.28#ibcon#about to read 4, iclass 10, count 0 2006.257.23:26:17.28#ibcon#read 4, iclass 10, count 0 2006.257.23:26:17.28#ibcon#about to read 5, iclass 10, count 0 2006.257.23:26:17.28#ibcon#read 5, iclass 10, count 0 2006.257.23:26:17.28#ibcon#about to read 6, iclass 10, count 0 2006.257.23:26:17.28#ibcon#read 6, iclass 10, count 0 2006.257.23:26:17.28#ibcon#end of sib2, iclass 10, count 0 2006.257.23:26:17.28#ibcon#*after write, iclass 10, count 0 2006.257.23:26:17.28#ibcon#*before return 0, iclass 10, count 0 2006.257.23:26:17.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:26:17.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:26:17.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:26:17.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:26:17.28$vck44/vb=1,4 2006.257.23:26:17.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.23:26:17.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.23:26:17.28#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:17.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:26:17.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:26:17.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:26:17.28#ibcon#enter wrdev, iclass 12, count 2 2006.257.23:26:17.28#ibcon#first serial, iclass 12, count 2 2006.257.23:26:17.28#ibcon#enter sib2, iclass 12, count 2 2006.257.23:26:17.28#ibcon#flushed, iclass 12, count 2 2006.257.23:26:17.28#ibcon#about to write, iclass 12, count 2 2006.257.23:26:17.28#ibcon#wrote, iclass 12, count 2 2006.257.23:26:17.28#ibcon#about to read 3, iclass 12, count 2 2006.257.23:26:17.30#ibcon#read 3, iclass 12, count 2 2006.257.23:26:17.30#ibcon#about to read 4, iclass 12, count 2 2006.257.23:26:17.30#ibcon#read 4, iclass 12, count 2 2006.257.23:26:17.30#ibcon#about to read 5, iclass 12, count 2 2006.257.23:26:17.30#ibcon#read 5, iclass 12, count 2 2006.257.23:26:17.30#ibcon#about to read 6, iclass 12, count 2 2006.257.23:26:17.30#ibcon#read 6, iclass 12, count 2 2006.257.23:26:17.30#ibcon#end of sib2, iclass 12, count 2 2006.257.23:26:17.30#ibcon#*mode == 0, iclass 12, count 2 2006.257.23:26:17.30#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.23:26:17.30#ibcon#[27=AT01-04\r\n] 2006.257.23:26:17.30#ibcon#*before write, iclass 12, count 2 2006.257.23:26:17.30#ibcon#enter sib2, iclass 12, count 2 2006.257.23:26:17.30#ibcon#flushed, iclass 12, count 2 2006.257.23:26:17.30#ibcon#about to write, iclass 12, count 2 2006.257.23:26:17.30#ibcon#wrote, iclass 12, count 2 2006.257.23:26:17.30#ibcon#about to read 3, iclass 12, count 2 2006.257.23:26:17.33#ibcon#read 3, iclass 12, count 2 2006.257.23:26:17.33#ibcon#about to read 4, iclass 12, count 2 2006.257.23:26:17.33#ibcon#read 4, iclass 12, count 2 2006.257.23:26:17.33#ibcon#about to read 5, iclass 12, count 2 2006.257.23:26:17.33#ibcon#read 5, iclass 12, count 2 2006.257.23:26:17.33#ibcon#about to read 6, iclass 12, count 2 2006.257.23:26:17.33#ibcon#read 6, iclass 12, count 2 2006.257.23:26:17.33#ibcon#end of sib2, iclass 12, count 2 2006.257.23:26:17.33#ibcon#*after write, iclass 12, count 2 2006.257.23:26:17.33#ibcon#*before return 0, iclass 12, count 2 2006.257.23:26:17.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:26:17.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:26:17.33#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.23:26:17.33#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:17.33#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:26:17.45#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:26:17.45#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:26:17.45#ibcon#enter wrdev, iclass 12, count 0 2006.257.23:26:17.45#ibcon#first serial, iclass 12, count 0 2006.257.23:26:17.45#ibcon#enter sib2, iclass 12, count 0 2006.257.23:26:17.45#ibcon#flushed, iclass 12, count 0 2006.257.23:26:17.45#ibcon#about to write, iclass 12, count 0 2006.257.23:26:17.45#ibcon#wrote, iclass 12, count 0 2006.257.23:26:17.45#ibcon#about to read 3, iclass 12, count 0 2006.257.23:26:17.47#ibcon#read 3, iclass 12, count 0 2006.257.23:26:17.47#ibcon#about to read 4, iclass 12, count 0 2006.257.23:26:17.47#ibcon#read 4, iclass 12, count 0 2006.257.23:26:17.47#ibcon#about to read 5, iclass 12, count 0 2006.257.23:26:17.47#ibcon#read 5, iclass 12, count 0 2006.257.23:26:17.47#ibcon#about to read 6, iclass 12, count 0 2006.257.23:26:17.47#ibcon#read 6, iclass 12, count 0 2006.257.23:26:17.47#ibcon#end of sib2, iclass 12, count 0 2006.257.23:26:17.47#ibcon#*mode == 0, iclass 12, count 0 2006.257.23:26:17.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.23:26:17.47#ibcon#[27=USB\r\n] 2006.257.23:26:17.47#ibcon#*before write, iclass 12, count 0 2006.257.23:26:17.47#ibcon#enter sib2, iclass 12, count 0 2006.257.23:26:17.47#ibcon#flushed, iclass 12, count 0 2006.257.23:26:17.47#ibcon#about to write, iclass 12, count 0 2006.257.23:26:17.47#ibcon#wrote, iclass 12, count 0 2006.257.23:26:17.47#ibcon#about to read 3, iclass 12, count 0 2006.257.23:26:17.50#ibcon#read 3, iclass 12, count 0 2006.257.23:26:17.50#ibcon#about to read 4, iclass 12, count 0 2006.257.23:26:17.50#ibcon#read 4, iclass 12, count 0 2006.257.23:26:17.50#ibcon#about to read 5, iclass 12, count 0 2006.257.23:26:17.50#ibcon#read 5, iclass 12, count 0 2006.257.23:26:17.50#ibcon#about to read 6, iclass 12, count 0 2006.257.23:26:17.50#ibcon#read 6, iclass 12, count 0 2006.257.23:26:17.50#ibcon#end of sib2, iclass 12, count 0 2006.257.23:26:17.50#ibcon#*after write, iclass 12, count 0 2006.257.23:26:17.50#ibcon#*before return 0, iclass 12, count 0 2006.257.23:26:17.50#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:26:17.50#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:26:17.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.23:26:17.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.23:26:17.50$vck44/vblo=2,634.99 2006.257.23:26:17.50#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.23:26:17.50#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.23:26:17.50#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:17.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:17.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:17.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:17.50#ibcon#enter wrdev, iclass 14, count 0 2006.257.23:26:17.50#ibcon#first serial, iclass 14, count 0 2006.257.23:26:17.50#ibcon#enter sib2, iclass 14, count 0 2006.257.23:26:17.50#ibcon#flushed, iclass 14, count 0 2006.257.23:26:17.50#ibcon#about to write, iclass 14, count 0 2006.257.23:26:17.50#ibcon#wrote, iclass 14, count 0 2006.257.23:26:17.50#ibcon#about to read 3, iclass 14, count 0 2006.257.23:26:17.52#ibcon#read 3, iclass 14, count 0 2006.257.23:26:17.52#ibcon#about to read 4, iclass 14, count 0 2006.257.23:26:17.52#ibcon#read 4, iclass 14, count 0 2006.257.23:26:17.52#ibcon#about to read 5, iclass 14, count 0 2006.257.23:26:17.52#ibcon#read 5, iclass 14, count 0 2006.257.23:26:17.52#ibcon#about to read 6, iclass 14, count 0 2006.257.23:26:17.52#ibcon#read 6, iclass 14, count 0 2006.257.23:26:17.52#ibcon#end of sib2, iclass 14, count 0 2006.257.23:26:17.52#ibcon#*mode == 0, iclass 14, count 0 2006.257.23:26:17.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.23:26:17.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:26:17.52#ibcon#*before write, iclass 14, count 0 2006.257.23:26:17.52#ibcon#enter sib2, iclass 14, count 0 2006.257.23:26:17.52#ibcon#flushed, iclass 14, count 0 2006.257.23:26:17.52#ibcon#about to write, iclass 14, count 0 2006.257.23:26:17.52#ibcon#wrote, iclass 14, count 0 2006.257.23:26:17.52#ibcon#about to read 3, iclass 14, count 0 2006.257.23:26:17.56#ibcon#read 3, iclass 14, count 0 2006.257.23:26:17.56#ibcon#about to read 4, iclass 14, count 0 2006.257.23:26:17.56#ibcon#read 4, iclass 14, count 0 2006.257.23:26:17.56#ibcon#about to read 5, iclass 14, count 0 2006.257.23:26:17.56#ibcon#read 5, iclass 14, count 0 2006.257.23:26:17.56#ibcon#about to read 6, iclass 14, count 0 2006.257.23:26:17.56#ibcon#read 6, iclass 14, count 0 2006.257.23:26:17.56#ibcon#end of sib2, iclass 14, count 0 2006.257.23:26:17.56#ibcon#*after write, iclass 14, count 0 2006.257.23:26:17.56#ibcon#*before return 0, iclass 14, count 0 2006.257.23:26:17.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:17.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:26:17.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.23:26:17.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.23:26:17.56$vck44/vb=2,5 2006.257.23:26:17.56#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.23:26:17.56#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.23:26:17.56#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:17.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:17.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:17.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:17.62#ibcon#enter wrdev, iclass 16, count 2 2006.257.23:26:17.62#ibcon#first serial, iclass 16, count 2 2006.257.23:26:17.62#ibcon#enter sib2, iclass 16, count 2 2006.257.23:26:17.62#ibcon#flushed, iclass 16, count 2 2006.257.23:26:17.62#ibcon#about to write, iclass 16, count 2 2006.257.23:26:17.62#ibcon#wrote, iclass 16, count 2 2006.257.23:26:17.62#ibcon#about to read 3, iclass 16, count 2 2006.257.23:26:17.64#ibcon#read 3, iclass 16, count 2 2006.257.23:26:17.64#ibcon#about to read 4, iclass 16, count 2 2006.257.23:26:17.64#ibcon#read 4, iclass 16, count 2 2006.257.23:26:17.64#ibcon#about to read 5, iclass 16, count 2 2006.257.23:26:17.64#ibcon#read 5, iclass 16, count 2 2006.257.23:26:17.64#ibcon#about to read 6, iclass 16, count 2 2006.257.23:26:17.64#ibcon#read 6, iclass 16, count 2 2006.257.23:26:17.64#ibcon#end of sib2, iclass 16, count 2 2006.257.23:26:17.64#ibcon#*mode == 0, iclass 16, count 2 2006.257.23:26:17.64#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.23:26:17.64#ibcon#[27=AT02-05\r\n] 2006.257.23:26:17.64#ibcon#*before write, iclass 16, count 2 2006.257.23:26:17.64#ibcon#enter sib2, iclass 16, count 2 2006.257.23:26:17.64#ibcon#flushed, iclass 16, count 2 2006.257.23:26:17.64#ibcon#about to write, iclass 16, count 2 2006.257.23:26:17.64#ibcon#wrote, iclass 16, count 2 2006.257.23:26:17.64#ibcon#about to read 3, iclass 16, count 2 2006.257.23:26:17.67#ibcon#read 3, iclass 16, count 2 2006.257.23:26:17.67#ibcon#about to read 4, iclass 16, count 2 2006.257.23:26:17.67#ibcon#read 4, iclass 16, count 2 2006.257.23:26:17.67#ibcon#about to read 5, iclass 16, count 2 2006.257.23:26:17.67#ibcon#read 5, iclass 16, count 2 2006.257.23:26:17.67#ibcon#about to read 6, iclass 16, count 2 2006.257.23:26:17.67#ibcon#read 6, iclass 16, count 2 2006.257.23:26:17.67#ibcon#end of sib2, iclass 16, count 2 2006.257.23:26:17.67#ibcon#*after write, iclass 16, count 2 2006.257.23:26:17.67#ibcon#*before return 0, iclass 16, count 2 2006.257.23:26:17.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:17.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:26:17.67#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.23:26:17.67#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:17.67#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:17.79#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:17.79#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:17.79#ibcon#enter wrdev, iclass 16, count 0 2006.257.23:26:17.79#ibcon#first serial, iclass 16, count 0 2006.257.23:26:17.79#ibcon#enter sib2, iclass 16, count 0 2006.257.23:26:17.79#ibcon#flushed, iclass 16, count 0 2006.257.23:26:17.79#ibcon#about to write, iclass 16, count 0 2006.257.23:26:17.79#ibcon#wrote, iclass 16, count 0 2006.257.23:26:17.79#ibcon#about to read 3, iclass 16, count 0 2006.257.23:26:17.81#ibcon#read 3, iclass 16, count 0 2006.257.23:26:17.81#ibcon#about to read 4, iclass 16, count 0 2006.257.23:26:17.81#ibcon#read 4, iclass 16, count 0 2006.257.23:26:17.81#ibcon#about to read 5, iclass 16, count 0 2006.257.23:26:17.81#ibcon#read 5, iclass 16, count 0 2006.257.23:26:17.81#ibcon#about to read 6, iclass 16, count 0 2006.257.23:26:17.81#ibcon#read 6, iclass 16, count 0 2006.257.23:26:17.81#ibcon#end of sib2, iclass 16, count 0 2006.257.23:26:17.81#ibcon#*mode == 0, iclass 16, count 0 2006.257.23:26:17.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.23:26:17.81#ibcon#[27=USB\r\n] 2006.257.23:26:17.81#ibcon#*before write, iclass 16, count 0 2006.257.23:26:17.81#ibcon#enter sib2, iclass 16, count 0 2006.257.23:26:17.81#ibcon#flushed, iclass 16, count 0 2006.257.23:26:17.81#ibcon#about to write, iclass 16, count 0 2006.257.23:26:17.81#ibcon#wrote, iclass 16, count 0 2006.257.23:26:17.81#ibcon#about to read 3, iclass 16, count 0 2006.257.23:26:17.84#ibcon#read 3, iclass 16, count 0 2006.257.23:26:17.84#ibcon#about to read 4, iclass 16, count 0 2006.257.23:26:17.84#ibcon#read 4, iclass 16, count 0 2006.257.23:26:17.84#ibcon#about to read 5, iclass 16, count 0 2006.257.23:26:17.84#ibcon#read 5, iclass 16, count 0 2006.257.23:26:17.84#ibcon#about to read 6, iclass 16, count 0 2006.257.23:26:17.84#ibcon#read 6, iclass 16, count 0 2006.257.23:26:17.84#ibcon#end of sib2, iclass 16, count 0 2006.257.23:26:17.84#ibcon#*after write, iclass 16, count 0 2006.257.23:26:17.84#ibcon#*before return 0, iclass 16, count 0 2006.257.23:26:17.84#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:17.84#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:26:17.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.23:26:17.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.23:26:17.84$vck44/vblo=3,649.99 2006.257.23:26:17.84#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.23:26:17.84#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.23:26:17.84#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:17.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:17.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:17.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:17.84#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:26:17.84#ibcon#first serial, iclass 18, count 0 2006.257.23:26:17.84#ibcon#enter sib2, iclass 18, count 0 2006.257.23:26:17.84#ibcon#flushed, iclass 18, count 0 2006.257.23:26:17.84#ibcon#about to write, iclass 18, count 0 2006.257.23:26:17.84#ibcon#wrote, iclass 18, count 0 2006.257.23:26:17.84#ibcon#about to read 3, iclass 18, count 0 2006.257.23:26:17.86#ibcon#read 3, iclass 18, count 0 2006.257.23:26:17.86#ibcon#about to read 4, iclass 18, count 0 2006.257.23:26:17.86#ibcon#read 4, iclass 18, count 0 2006.257.23:26:17.86#ibcon#about to read 5, iclass 18, count 0 2006.257.23:26:17.86#ibcon#read 5, iclass 18, count 0 2006.257.23:26:17.86#ibcon#about to read 6, iclass 18, count 0 2006.257.23:26:17.86#ibcon#read 6, iclass 18, count 0 2006.257.23:26:17.86#ibcon#end of sib2, iclass 18, count 0 2006.257.23:26:17.86#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:26:17.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:26:17.86#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:26:17.86#ibcon#*before write, iclass 18, count 0 2006.257.23:26:17.86#ibcon#enter sib2, iclass 18, count 0 2006.257.23:26:17.86#ibcon#flushed, iclass 18, count 0 2006.257.23:26:17.86#ibcon#about to write, iclass 18, count 0 2006.257.23:26:17.86#ibcon#wrote, iclass 18, count 0 2006.257.23:26:17.86#ibcon#about to read 3, iclass 18, count 0 2006.257.23:26:17.90#ibcon#read 3, iclass 18, count 0 2006.257.23:26:17.90#ibcon#about to read 4, iclass 18, count 0 2006.257.23:26:17.90#ibcon#read 4, iclass 18, count 0 2006.257.23:26:17.90#ibcon#about to read 5, iclass 18, count 0 2006.257.23:26:17.90#ibcon#read 5, iclass 18, count 0 2006.257.23:26:17.90#ibcon#about to read 6, iclass 18, count 0 2006.257.23:26:17.90#ibcon#read 6, iclass 18, count 0 2006.257.23:26:17.90#ibcon#end of sib2, iclass 18, count 0 2006.257.23:26:17.90#ibcon#*after write, iclass 18, count 0 2006.257.23:26:17.90#ibcon#*before return 0, iclass 18, count 0 2006.257.23:26:17.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:17.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:26:17.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:26:17.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:26:17.90$vck44/vb=3,4 2006.257.23:26:17.90#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.23:26:17.90#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.23:26:17.90#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:17.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:17.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:17.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:17.96#ibcon#enter wrdev, iclass 20, count 2 2006.257.23:26:17.96#ibcon#first serial, iclass 20, count 2 2006.257.23:26:17.96#ibcon#enter sib2, iclass 20, count 2 2006.257.23:26:17.96#ibcon#flushed, iclass 20, count 2 2006.257.23:26:17.96#ibcon#about to write, iclass 20, count 2 2006.257.23:26:17.96#ibcon#wrote, iclass 20, count 2 2006.257.23:26:17.96#ibcon#about to read 3, iclass 20, count 2 2006.257.23:26:17.98#ibcon#read 3, iclass 20, count 2 2006.257.23:26:17.98#ibcon#about to read 4, iclass 20, count 2 2006.257.23:26:17.98#ibcon#read 4, iclass 20, count 2 2006.257.23:26:17.98#ibcon#about to read 5, iclass 20, count 2 2006.257.23:26:17.98#ibcon#read 5, iclass 20, count 2 2006.257.23:26:17.98#ibcon#about to read 6, iclass 20, count 2 2006.257.23:26:17.98#ibcon#read 6, iclass 20, count 2 2006.257.23:26:17.98#ibcon#end of sib2, iclass 20, count 2 2006.257.23:26:17.98#ibcon#*mode == 0, iclass 20, count 2 2006.257.23:26:17.98#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.23:26:17.98#ibcon#[27=AT03-04\r\n] 2006.257.23:26:17.98#ibcon#*before write, iclass 20, count 2 2006.257.23:26:17.98#ibcon#enter sib2, iclass 20, count 2 2006.257.23:26:17.98#ibcon#flushed, iclass 20, count 2 2006.257.23:26:17.98#ibcon#about to write, iclass 20, count 2 2006.257.23:26:17.98#ibcon#wrote, iclass 20, count 2 2006.257.23:26:17.98#ibcon#about to read 3, iclass 20, count 2 2006.257.23:26:18.01#ibcon#read 3, iclass 20, count 2 2006.257.23:26:18.01#ibcon#about to read 4, iclass 20, count 2 2006.257.23:26:18.01#ibcon#read 4, iclass 20, count 2 2006.257.23:26:18.01#ibcon#about to read 5, iclass 20, count 2 2006.257.23:26:18.01#ibcon#read 5, iclass 20, count 2 2006.257.23:26:18.01#ibcon#about to read 6, iclass 20, count 2 2006.257.23:26:18.01#ibcon#read 6, iclass 20, count 2 2006.257.23:26:18.01#ibcon#end of sib2, iclass 20, count 2 2006.257.23:26:18.01#ibcon#*after write, iclass 20, count 2 2006.257.23:26:18.01#ibcon#*before return 0, iclass 20, count 2 2006.257.23:26:18.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:18.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:26:18.01#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.23:26:18.01#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:18.01#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:18.13#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:18.13#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:18.13#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:26:18.13#ibcon#first serial, iclass 20, count 0 2006.257.23:26:18.13#ibcon#enter sib2, iclass 20, count 0 2006.257.23:26:18.13#ibcon#flushed, iclass 20, count 0 2006.257.23:26:18.13#ibcon#about to write, iclass 20, count 0 2006.257.23:26:18.13#ibcon#wrote, iclass 20, count 0 2006.257.23:26:18.13#ibcon#about to read 3, iclass 20, count 0 2006.257.23:26:18.15#ibcon#read 3, iclass 20, count 0 2006.257.23:26:18.15#ibcon#about to read 4, iclass 20, count 0 2006.257.23:26:18.15#ibcon#read 4, iclass 20, count 0 2006.257.23:26:18.15#ibcon#about to read 5, iclass 20, count 0 2006.257.23:26:18.15#ibcon#read 5, iclass 20, count 0 2006.257.23:26:18.15#ibcon#about to read 6, iclass 20, count 0 2006.257.23:26:18.15#ibcon#read 6, iclass 20, count 0 2006.257.23:26:18.15#ibcon#end of sib2, iclass 20, count 0 2006.257.23:26:18.15#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:26:18.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:26:18.15#ibcon#[27=USB\r\n] 2006.257.23:26:18.15#ibcon#*before write, iclass 20, count 0 2006.257.23:26:18.15#ibcon#enter sib2, iclass 20, count 0 2006.257.23:26:18.15#ibcon#flushed, iclass 20, count 0 2006.257.23:26:18.15#ibcon#about to write, iclass 20, count 0 2006.257.23:26:18.15#ibcon#wrote, iclass 20, count 0 2006.257.23:26:18.15#ibcon#about to read 3, iclass 20, count 0 2006.257.23:26:18.18#ibcon#read 3, iclass 20, count 0 2006.257.23:26:18.18#ibcon#about to read 4, iclass 20, count 0 2006.257.23:26:18.18#ibcon#read 4, iclass 20, count 0 2006.257.23:26:18.18#ibcon#about to read 5, iclass 20, count 0 2006.257.23:26:18.18#ibcon#read 5, iclass 20, count 0 2006.257.23:26:18.18#ibcon#about to read 6, iclass 20, count 0 2006.257.23:26:18.18#ibcon#read 6, iclass 20, count 0 2006.257.23:26:18.18#ibcon#end of sib2, iclass 20, count 0 2006.257.23:26:18.18#ibcon#*after write, iclass 20, count 0 2006.257.23:26:18.18#ibcon#*before return 0, iclass 20, count 0 2006.257.23:26:18.18#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:18.18#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:26:18.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:26:18.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:26:18.18$vck44/vblo=4,679.99 2006.257.23:26:18.18#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.23:26:18.18#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.23:26:18.18#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:18.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:18.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:18.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:18.18#ibcon#enter wrdev, iclass 22, count 0 2006.257.23:26:18.18#ibcon#first serial, iclass 22, count 0 2006.257.23:26:18.18#ibcon#enter sib2, iclass 22, count 0 2006.257.23:26:18.18#ibcon#flushed, iclass 22, count 0 2006.257.23:26:18.18#ibcon#about to write, iclass 22, count 0 2006.257.23:26:18.18#ibcon#wrote, iclass 22, count 0 2006.257.23:26:18.18#ibcon#about to read 3, iclass 22, count 0 2006.257.23:26:18.20#ibcon#read 3, iclass 22, count 0 2006.257.23:26:18.20#ibcon#about to read 4, iclass 22, count 0 2006.257.23:26:18.20#ibcon#read 4, iclass 22, count 0 2006.257.23:26:18.20#ibcon#about to read 5, iclass 22, count 0 2006.257.23:26:18.20#ibcon#read 5, iclass 22, count 0 2006.257.23:26:18.20#ibcon#about to read 6, iclass 22, count 0 2006.257.23:26:18.20#ibcon#read 6, iclass 22, count 0 2006.257.23:26:18.20#ibcon#end of sib2, iclass 22, count 0 2006.257.23:26:18.20#ibcon#*mode == 0, iclass 22, count 0 2006.257.23:26:18.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.23:26:18.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:26:18.20#ibcon#*before write, iclass 22, count 0 2006.257.23:26:18.20#ibcon#enter sib2, iclass 22, count 0 2006.257.23:26:18.20#ibcon#flushed, iclass 22, count 0 2006.257.23:26:18.20#ibcon#about to write, iclass 22, count 0 2006.257.23:26:18.20#ibcon#wrote, iclass 22, count 0 2006.257.23:26:18.20#ibcon#about to read 3, iclass 22, count 0 2006.257.23:26:18.24#ibcon#read 3, iclass 22, count 0 2006.257.23:26:18.24#ibcon#about to read 4, iclass 22, count 0 2006.257.23:26:18.24#ibcon#read 4, iclass 22, count 0 2006.257.23:26:18.24#ibcon#about to read 5, iclass 22, count 0 2006.257.23:26:18.24#ibcon#read 5, iclass 22, count 0 2006.257.23:26:18.24#ibcon#about to read 6, iclass 22, count 0 2006.257.23:26:18.24#ibcon#read 6, iclass 22, count 0 2006.257.23:26:18.24#ibcon#end of sib2, iclass 22, count 0 2006.257.23:26:18.24#ibcon#*after write, iclass 22, count 0 2006.257.23:26:18.24#ibcon#*before return 0, iclass 22, count 0 2006.257.23:26:18.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:18.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:26:18.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.23:26:18.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.23:26:18.24$vck44/vb=4,5 2006.257.23:26:18.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.23:26:18.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.23:26:18.24#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:18.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:18.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:18.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:18.30#ibcon#enter wrdev, iclass 24, count 2 2006.257.23:26:18.30#ibcon#first serial, iclass 24, count 2 2006.257.23:26:18.30#ibcon#enter sib2, iclass 24, count 2 2006.257.23:26:18.30#ibcon#flushed, iclass 24, count 2 2006.257.23:26:18.30#ibcon#about to write, iclass 24, count 2 2006.257.23:26:18.30#ibcon#wrote, iclass 24, count 2 2006.257.23:26:18.30#ibcon#about to read 3, iclass 24, count 2 2006.257.23:26:18.32#ibcon#read 3, iclass 24, count 2 2006.257.23:26:18.32#ibcon#about to read 4, iclass 24, count 2 2006.257.23:26:18.32#ibcon#read 4, iclass 24, count 2 2006.257.23:26:18.32#ibcon#about to read 5, iclass 24, count 2 2006.257.23:26:18.32#ibcon#read 5, iclass 24, count 2 2006.257.23:26:18.32#ibcon#about to read 6, iclass 24, count 2 2006.257.23:26:18.32#ibcon#read 6, iclass 24, count 2 2006.257.23:26:18.32#ibcon#end of sib2, iclass 24, count 2 2006.257.23:26:18.32#ibcon#*mode == 0, iclass 24, count 2 2006.257.23:26:18.32#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.23:26:18.32#ibcon#[27=AT04-05\r\n] 2006.257.23:26:18.32#ibcon#*before write, iclass 24, count 2 2006.257.23:26:18.32#ibcon#enter sib2, iclass 24, count 2 2006.257.23:26:18.32#ibcon#flushed, iclass 24, count 2 2006.257.23:26:18.32#ibcon#about to write, iclass 24, count 2 2006.257.23:26:18.32#ibcon#wrote, iclass 24, count 2 2006.257.23:26:18.32#ibcon#about to read 3, iclass 24, count 2 2006.257.23:26:18.35#ibcon#read 3, iclass 24, count 2 2006.257.23:26:18.35#ibcon#about to read 4, iclass 24, count 2 2006.257.23:26:18.35#ibcon#read 4, iclass 24, count 2 2006.257.23:26:18.35#ibcon#about to read 5, iclass 24, count 2 2006.257.23:26:18.35#ibcon#read 5, iclass 24, count 2 2006.257.23:26:18.35#ibcon#about to read 6, iclass 24, count 2 2006.257.23:26:18.35#ibcon#read 6, iclass 24, count 2 2006.257.23:26:18.35#ibcon#end of sib2, iclass 24, count 2 2006.257.23:26:18.35#ibcon#*after write, iclass 24, count 2 2006.257.23:26:18.35#ibcon#*before return 0, iclass 24, count 2 2006.257.23:26:18.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:18.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:26:18.35#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.23:26:18.35#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:18.35#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:18.47#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:18.47#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:18.47#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:26:18.47#ibcon#first serial, iclass 24, count 0 2006.257.23:26:18.47#ibcon#enter sib2, iclass 24, count 0 2006.257.23:26:18.47#ibcon#flushed, iclass 24, count 0 2006.257.23:26:18.47#ibcon#about to write, iclass 24, count 0 2006.257.23:26:18.47#ibcon#wrote, iclass 24, count 0 2006.257.23:26:18.47#ibcon#about to read 3, iclass 24, count 0 2006.257.23:26:18.49#ibcon#read 3, iclass 24, count 0 2006.257.23:26:18.49#ibcon#about to read 4, iclass 24, count 0 2006.257.23:26:18.49#ibcon#read 4, iclass 24, count 0 2006.257.23:26:18.49#ibcon#about to read 5, iclass 24, count 0 2006.257.23:26:18.49#ibcon#read 5, iclass 24, count 0 2006.257.23:26:18.49#ibcon#about to read 6, iclass 24, count 0 2006.257.23:26:18.49#ibcon#read 6, iclass 24, count 0 2006.257.23:26:18.49#ibcon#end of sib2, iclass 24, count 0 2006.257.23:26:18.49#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:26:18.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:26:18.49#ibcon#[27=USB\r\n] 2006.257.23:26:18.49#ibcon#*before write, iclass 24, count 0 2006.257.23:26:18.49#ibcon#enter sib2, iclass 24, count 0 2006.257.23:26:18.49#ibcon#flushed, iclass 24, count 0 2006.257.23:26:18.49#ibcon#about to write, iclass 24, count 0 2006.257.23:26:18.49#ibcon#wrote, iclass 24, count 0 2006.257.23:26:18.49#ibcon#about to read 3, iclass 24, count 0 2006.257.23:26:18.52#ibcon#read 3, iclass 24, count 0 2006.257.23:26:18.52#ibcon#about to read 4, iclass 24, count 0 2006.257.23:26:18.52#ibcon#read 4, iclass 24, count 0 2006.257.23:26:18.52#ibcon#about to read 5, iclass 24, count 0 2006.257.23:26:18.52#ibcon#read 5, iclass 24, count 0 2006.257.23:26:18.52#ibcon#about to read 6, iclass 24, count 0 2006.257.23:26:18.52#ibcon#read 6, iclass 24, count 0 2006.257.23:26:18.52#ibcon#end of sib2, iclass 24, count 0 2006.257.23:26:18.52#ibcon#*after write, iclass 24, count 0 2006.257.23:26:18.52#ibcon#*before return 0, iclass 24, count 0 2006.257.23:26:18.52#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:18.52#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:26:18.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:26:18.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:26:18.52$vck44/vblo=5,709.99 2006.257.23:26:18.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.23:26:18.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.23:26:18.52#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:18.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:18.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:18.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:18.52#ibcon#enter wrdev, iclass 26, count 0 2006.257.23:26:18.52#ibcon#first serial, iclass 26, count 0 2006.257.23:26:18.52#ibcon#enter sib2, iclass 26, count 0 2006.257.23:26:18.52#ibcon#flushed, iclass 26, count 0 2006.257.23:26:18.52#ibcon#about to write, iclass 26, count 0 2006.257.23:26:18.52#ibcon#wrote, iclass 26, count 0 2006.257.23:26:18.52#ibcon#about to read 3, iclass 26, count 0 2006.257.23:26:18.54#ibcon#read 3, iclass 26, count 0 2006.257.23:26:18.54#ibcon#about to read 4, iclass 26, count 0 2006.257.23:26:18.54#ibcon#read 4, iclass 26, count 0 2006.257.23:26:18.54#ibcon#about to read 5, iclass 26, count 0 2006.257.23:26:18.54#ibcon#read 5, iclass 26, count 0 2006.257.23:26:18.54#ibcon#about to read 6, iclass 26, count 0 2006.257.23:26:18.54#ibcon#read 6, iclass 26, count 0 2006.257.23:26:18.54#ibcon#end of sib2, iclass 26, count 0 2006.257.23:26:18.54#ibcon#*mode == 0, iclass 26, count 0 2006.257.23:26:18.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.23:26:18.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:26:18.54#ibcon#*before write, iclass 26, count 0 2006.257.23:26:18.54#ibcon#enter sib2, iclass 26, count 0 2006.257.23:26:18.54#ibcon#flushed, iclass 26, count 0 2006.257.23:26:18.54#ibcon#about to write, iclass 26, count 0 2006.257.23:26:18.54#ibcon#wrote, iclass 26, count 0 2006.257.23:26:18.54#ibcon#about to read 3, iclass 26, count 0 2006.257.23:26:18.58#ibcon#read 3, iclass 26, count 0 2006.257.23:26:18.58#ibcon#about to read 4, iclass 26, count 0 2006.257.23:26:18.58#ibcon#read 4, iclass 26, count 0 2006.257.23:26:18.58#ibcon#about to read 5, iclass 26, count 0 2006.257.23:26:18.58#ibcon#read 5, iclass 26, count 0 2006.257.23:26:18.58#ibcon#about to read 6, iclass 26, count 0 2006.257.23:26:18.58#ibcon#read 6, iclass 26, count 0 2006.257.23:26:18.58#ibcon#end of sib2, iclass 26, count 0 2006.257.23:26:18.58#ibcon#*after write, iclass 26, count 0 2006.257.23:26:18.58#ibcon#*before return 0, iclass 26, count 0 2006.257.23:26:18.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:18.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:26:18.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.23:26:18.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.23:26:18.58$vck44/vb=5,4 2006.257.23:26:18.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.23:26:18.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.23:26:18.58#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:18.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:18.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:18.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:18.64#ibcon#enter wrdev, iclass 28, count 2 2006.257.23:26:18.64#ibcon#first serial, iclass 28, count 2 2006.257.23:26:18.64#ibcon#enter sib2, iclass 28, count 2 2006.257.23:26:18.64#ibcon#flushed, iclass 28, count 2 2006.257.23:26:18.64#ibcon#about to write, iclass 28, count 2 2006.257.23:26:18.64#ibcon#wrote, iclass 28, count 2 2006.257.23:26:18.64#ibcon#about to read 3, iclass 28, count 2 2006.257.23:26:18.66#ibcon#read 3, iclass 28, count 2 2006.257.23:26:18.66#ibcon#about to read 4, iclass 28, count 2 2006.257.23:26:18.66#ibcon#read 4, iclass 28, count 2 2006.257.23:26:18.66#ibcon#about to read 5, iclass 28, count 2 2006.257.23:26:18.66#ibcon#read 5, iclass 28, count 2 2006.257.23:26:18.66#ibcon#about to read 6, iclass 28, count 2 2006.257.23:26:18.66#ibcon#read 6, iclass 28, count 2 2006.257.23:26:18.66#ibcon#end of sib2, iclass 28, count 2 2006.257.23:26:18.66#ibcon#*mode == 0, iclass 28, count 2 2006.257.23:26:18.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.23:26:18.66#ibcon#[27=AT05-04\r\n] 2006.257.23:26:18.66#ibcon#*before write, iclass 28, count 2 2006.257.23:26:18.66#ibcon#enter sib2, iclass 28, count 2 2006.257.23:26:18.66#ibcon#flushed, iclass 28, count 2 2006.257.23:26:18.66#ibcon#about to write, iclass 28, count 2 2006.257.23:26:18.66#ibcon#wrote, iclass 28, count 2 2006.257.23:26:18.66#ibcon#about to read 3, iclass 28, count 2 2006.257.23:26:18.69#ibcon#read 3, iclass 28, count 2 2006.257.23:26:18.69#ibcon#about to read 4, iclass 28, count 2 2006.257.23:26:18.69#ibcon#read 4, iclass 28, count 2 2006.257.23:26:18.69#ibcon#about to read 5, iclass 28, count 2 2006.257.23:26:18.69#ibcon#read 5, iclass 28, count 2 2006.257.23:26:18.69#ibcon#about to read 6, iclass 28, count 2 2006.257.23:26:18.69#ibcon#read 6, iclass 28, count 2 2006.257.23:26:18.69#ibcon#end of sib2, iclass 28, count 2 2006.257.23:26:18.69#ibcon#*after write, iclass 28, count 2 2006.257.23:26:18.69#ibcon#*before return 0, iclass 28, count 2 2006.257.23:26:18.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:18.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:26:18.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.23:26:18.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:18.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:18.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:18.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:18.81#ibcon#enter wrdev, iclass 28, count 0 2006.257.23:26:18.81#ibcon#first serial, iclass 28, count 0 2006.257.23:26:18.81#ibcon#enter sib2, iclass 28, count 0 2006.257.23:26:18.81#ibcon#flushed, iclass 28, count 0 2006.257.23:26:18.81#ibcon#about to write, iclass 28, count 0 2006.257.23:26:18.81#ibcon#wrote, iclass 28, count 0 2006.257.23:26:18.81#ibcon#about to read 3, iclass 28, count 0 2006.257.23:26:18.83#ibcon#read 3, iclass 28, count 0 2006.257.23:26:18.83#ibcon#about to read 4, iclass 28, count 0 2006.257.23:26:18.83#ibcon#read 4, iclass 28, count 0 2006.257.23:26:18.83#ibcon#about to read 5, iclass 28, count 0 2006.257.23:26:18.83#ibcon#read 5, iclass 28, count 0 2006.257.23:26:18.83#ibcon#about to read 6, iclass 28, count 0 2006.257.23:26:18.83#ibcon#read 6, iclass 28, count 0 2006.257.23:26:18.83#ibcon#end of sib2, iclass 28, count 0 2006.257.23:26:18.83#ibcon#*mode == 0, iclass 28, count 0 2006.257.23:26:18.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.23:26:18.83#ibcon#[27=USB\r\n] 2006.257.23:26:18.83#ibcon#*before write, iclass 28, count 0 2006.257.23:26:18.83#ibcon#enter sib2, iclass 28, count 0 2006.257.23:26:18.83#ibcon#flushed, iclass 28, count 0 2006.257.23:26:18.83#ibcon#about to write, iclass 28, count 0 2006.257.23:26:18.83#ibcon#wrote, iclass 28, count 0 2006.257.23:26:18.83#ibcon#about to read 3, iclass 28, count 0 2006.257.23:26:18.86#ibcon#read 3, iclass 28, count 0 2006.257.23:26:18.86#ibcon#about to read 4, iclass 28, count 0 2006.257.23:26:18.86#ibcon#read 4, iclass 28, count 0 2006.257.23:26:18.86#ibcon#about to read 5, iclass 28, count 0 2006.257.23:26:18.86#ibcon#read 5, iclass 28, count 0 2006.257.23:26:18.86#ibcon#about to read 6, iclass 28, count 0 2006.257.23:26:18.86#ibcon#read 6, iclass 28, count 0 2006.257.23:26:18.86#ibcon#end of sib2, iclass 28, count 0 2006.257.23:26:18.86#ibcon#*after write, iclass 28, count 0 2006.257.23:26:18.86#ibcon#*before return 0, iclass 28, count 0 2006.257.23:26:18.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:18.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:26:18.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.23:26:18.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.23:26:18.86$vck44/vblo=6,719.99 2006.257.23:26:18.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.23:26:18.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.23:26:18.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:18.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:18.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:18.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:18.86#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:26:18.86#ibcon#first serial, iclass 30, count 0 2006.257.23:26:18.86#ibcon#enter sib2, iclass 30, count 0 2006.257.23:26:18.86#ibcon#flushed, iclass 30, count 0 2006.257.23:26:18.86#ibcon#about to write, iclass 30, count 0 2006.257.23:26:18.86#ibcon#wrote, iclass 30, count 0 2006.257.23:26:18.86#ibcon#about to read 3, iclass 30, count 0 2006.257.23:26:18.88#ibcon#read 3, iclass 30, count 0 2006.257.23:26:18.88#ibcon#about to read 4, iclass 30, count 0 2006.257.23:26:18.88#ibcon#read 4, iclass 30, count 0 2006.257.23:26:18.88#ibcon#about to read 5, iclass 30, count 0 2006.257.23:26:18.88#ibcon#read 5, iclass 30, count 0 2006.257.23:26:18.88#ibcon#about to read 6, iclass 30, count 0 2006.257.23:26:18.88#ibcon#read 6, iclass 30, count 0 2006.257.23:26:18.88#ibcon#end of sib2, iclass 30, count 0 2006.257.23:26:18.88#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:26:18.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:26:18.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:26:18.88#ibcon#*before write, iclass 30, count 0 2006.257.23:26:18.88#ibcon#enter sib2, iclass 30, count 0 2006.257.23:26:18.88#ibcon#flushed, iclass 30, count 0 2006.257.23:26:18.88#ibcon#about to write, iclass 30, count 0 2006.257.23:26:18.88#ibcon#wrote, iclass 30, count 0 2006.257.23:26:18.88#ibcon#about to read 3, iclass 30, count 0 2006.257.23:26:18.92#ibcon#read 3, iclass 30, count 0 2006.257.23:26:18.92#ibcon#about to read 4, iclass 30, count 0 2006.257.23:26:18.92#ibcon#read 4, iclass 30, count 0 2006.257.23:26:18.92#ibcon#about to read 5, iclass 30, count 0 2006.257.23:26:18.92#ibcon#read 5, iclass 30, count 0 2006.257.23:26:18.92#ibcon#about to read 6, iclass 30, count 0 2006.257.23:26:18.92#ibcon#read 6, iclass 30, count 0 2006.257.23:26:18.92#ibcon#end of sib2, iclass 30, count 0 2006.257.23:26:18.92#ibcon#*after write, iclass 30, count 0 2006.257.23:26:18.92#ibcon#*before return 0, iclass 30, count 0 2006.257.23:26:18.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:18.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:26:18.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:26:18.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:26:18.92$vck44/vb=6,4 2006.257.23:26:18.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.23:26:18.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.23:26:18.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:18.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:18.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:18.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:18.98#ibcon#enter wrdev, iclass 32, count 2 2006.257.23:26:18.98#ibcon#first serial, iclass 32, count 2 2006.257.23:26:18.98#ibcon#enter sib2, iclass 32, count 2 2006.257.23:26:18.98#ibcon#flushed, iclass 32, count 2 2006.257.23:26:18.98#ibcon#about to write, iclass 32, count 2 2006.257.23:26:18.98#ibcon#wrote, iclass 32, count 2 2006.257.23:26:18.98#ibcon#about to read 3, iclass 32, count 2 2006.257.23:26:19.00#ibcon#read 3, iclass 32, count 2 2006.257.23:26:19.00#ibcon#about to read 4, iclass 32, count 2 2006.257.23:26:19.00#ibcon#read 4, iclass 32, count 2 2006.257.23:26:19.00#ibcon#about to read 5, iclass 32, count 2 2006.257.23:26:19.00#ibcon#read 5, iclass 32, count 2 2006.257.23:26:19.00#ibcon#about to read 6, iclass 32, count 2 2006.257.23:26:19.00#ibcon#read 6, iclass 32, count 2 2006.257.23:26:19.00#ibcon#end of sib2, iclass 32, count 2 2006.257.23:26:19.00#ibcon#*mode == 0, iclass 32, count 2 2006.257.23:26:19.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.23:26:19.00#ibcon#[27=AT06-04\r\n] 2006.257.23:26:19.00#ibcon#*before write, iclass 32, count 2 2006.257.23:26:19.00#ibcon#enter sib2, iclass 32, count 2 2006.257.23:26:19.00#ibcon#flushed, iclass 32, count 2 2006.257.23:26:19.00#ibcon#about to write, iclass 32, count 2 2006.257.23:26:19.00#ibcon#wrote, iclass 32, count 2 2006.257.23:26:19.00#ibcon#about to read 3, iclass 32, count 2 2006.257.23:26:19.03#ibcon#read 3, iclass 32, count 2 2006.257.23:26:19.03#ibcon#about to read 4, iclass 32, count 2 2006.257.23:26:19.03#ibcon#read 4, iclass 32, count 2 2006.257.23:26:19.03#ibcon#about to read 5, iclass 32, count 2 2006.257.23:26:19.03#ibcon#read 5, iclass 32, count 2 2006.257.23:26:19.03#ibcon#about to read 6, iclass 32, count 2 2006.257.23:26:19.03#ibcon#read 6, iclass 32, count 2 2006.257.23:26:19.03#ibcon#end of sib2, iclass 32, count 2 2006.257.23:26:19.03#ibcon#*after write, iclass 32, count 2 2006.257.23:26:19.03#ibcon#*before return 0, iclass 32, count 2 2006.257.23:26:19.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:19.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:26:19.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.23:26:19.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:19.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:19.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:19.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:19.15#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:26:19.15#ibcon#first serial, iclass 32, count 0 2006.257.23:26:19.15#ibcon#enter sib2, iclass 32, count 0 2006.257.23:26:19.15#ibcon#flushed, iclass 32, count 0 2006.257.23:26:19.15#ibcon#about to write, iclass 32, count 0 2006.257.23:26:19.15#ibcon#wrote, iclass 32, count 0 2006.257.23:26:19.15#ibcon#about to read 3, iclass 32, count 0 2006.257.23:26:19.17#ibcon#read 3, iclass 32, count 0 2006.257.23:26:19.17#ibcon#about to read 4, iclass 32, count 0 2006.257.23:26:19.17#ibcon#read 4, iclass 32, count 0 2006.257.23:26:19.17#ibcon#about to read 5, iclass 32, count 0 2006.257.23:26:19.17#ibcon#read 5, iclass 32, count 0 2006.257.23:26:19.17#ibcon#about to read 6, iclass 32, count 0 2006.257.23:26:19.17#ibcon#read 6, iclass 32, count 0 2006.257.23:26:19.17#ibcon#end of sib2, iclass 32, count 0 2006.257.23:26:19.17#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:26:19.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:26:19.17#ibcon#[27=USB\r\n] 2006.257.23:26:19.17#ibcon#*before write, iclass 32, count 0 2006.257.23:26:19.17#ibcon#enter sib2, iclass 32, count 0 2006.257.23:26:19.17#ibcon#flushed, iclass 32, count 0 2006.257.23:26:19.17#ibcon#about to write, iclass 32, count 0 2006.257.23:26:19.17#ibcon#wrote, iclass 32, count 0 2006.257.23:26:19.17#ibcon#about to read 3, iclass 32, count 0 2006.257.23:26:19.20#ibcon#read 3, iclass 32, count 0 2006.257.23:26:19.20#ibcon#about to read 4, iclass 32, count 0 2006.257.23:26:19.20#ibcon#read 4, iclass 32, count 0 2006.257.23:26:19.20#ibcon#about to read 5, iclass 32, count 0 2006.257.23:26:19.20#ibcon#read 5, iclass 32, count 0 2006.257.23:26:19.20#ibcon#about to read 6, iclass 32, count 0 2006.257.23:26:19.20#ibcon#read 6, iclass 32, count 0 2006.257.23:26:19.20#ibcon#end of sib2, iclass 32, count 0 2006.257.23:26:19.20#ibcon#*after write, iclass 32, count 0 2006.257.23:26:19.20#ibcon#*before return 0, iclass 32, count 0 2006.257.23:26:19.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:19.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:26:19.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:26:19.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:26:19.20$vck44/vblo=7,734.99 2006.257.23:26:19.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.23:26:19.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.23:26:19.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:19.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:19.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:19.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:19.20#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:26:19.20#ibcon#first serial, iclass 34, count 0 2006.257.23:26:19.20#ibcon#enter sib2, iclass 34, count 0 2006.257.23:26:19.20#ibcon#flushed, iclass 34, count 0 2006.257.23:26:19.20#ibcon#about to write, iclass 34, count 0 2006.257.23:26:19.20#ibcon#wrote, iclass 34, count 0 2006.257.23:26:19.20#ibcon#about to read 3, iclass 34, count 0 2006.257.23:26:19.22#ibcon#read 3, iclass 34, count 0 2006.257.23:26:19.22#ibcon#about to read 4, iclass 34, count 0 2006.257.23:26:19.22#ibcon#read 4, iclass 34, count 0 2006.257.23:26:19.22#ibcon#about to read 5, iclass 34, count 0 2006.257.23:26:19.22#ibcon#read 5, iclass 34, count 0 2006.257.23:26:19.22#ibcon#about to read 6, iclass 34, count 0 2006.257.23:26:19.22#ibcon#read 6, iclass 34, count 0 2006.257.23:26:19.22#ibcon#end of sib2, iclass 34, count 0 2006.257.23:26:19.22#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:26:19.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:26:19.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:26:19.22#ibcon#*before write, iclass 34, count 0 2006.257.23:26:19.22#ibcon#enter sib2, iclass 34, count 0 2006.257.23:26:19.22#ibcon#flushed, iclass 34, count 0 2006.257.23:26:19.22#ibcon#about to write, iclass 34, count 0 2006.257.23:26:19.22#ibcon#wrote, iclass 34, count 0 2006.257.23:26:19.22#ibcon#about to read 3, iclass 34, count 0 2006.257.23:26:19.26#ibcon#read 3, iclass 34, count 0 2006.257.23:26:19.26#ibcon#about to read 4, iclass 34, count 0 2006.257.23:26:19.26#ibcon#read 4, iclass 34, count 0 2006.257.23:26:19.26#ibcon#about to read 5, iclass 34, count 0 2006.257.23:26:19.26#ibcon#read 5, iclass 34, count 0 2006.257.23:26:19.26#ibcon#about to read 6, iclass 34, count 0 2006.257.23:26:19.26#ibcon#read 6, iclass 34, count 0 2006.257.23:26:19.26#ibcon#end of sib2, iclass 34, count 0 2006.257.23:26:19.26#ibcon#*after write, iclass 34, count 0 2006.257.23:26:19.26#ibcon#*before return 0, iclass 34, count 0 2006.257.23:26:19.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:19.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:26:19.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:26:19.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:26:19.26$vck44/vb=7,4 2006.257.23:26:19.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.23:26:19.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.23:26:19.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:19.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:19.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:19.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:19.32#ibcon#enter wrdev, iclass 36, count 2 2006.257.23:26:19.32#ibcon#first serial, iclass 36, count 2 2006.257.23:26:19.32#ibcon#enter sib2, iclass 36, count 2 2006.257.23:26:19.32#ibcon#flushed, iclass 36, count 2 2006.257.23:26:19.32#ibcon#about to write, iclass 36, count 2 2006.257.23:26:19.32#ibcon#wrote, iclass 36, count 2 2006.257.23:26:19.32#ibcon#about to read 3, iclass 36, count 2 2006.257.23:26:19.34#ibcon#read 3, iclass 36, count 2 2006.257.23:26:19.34#ibcon#about to read 4, iclass 36, count 2 2006.257.23:26:19.34#ibcon#read 4, iclass 36, count 2 2006.257.23:26:19.34#ibcon#about to read 5, iclass 36, count 2 2006.257.23:26:19.34#ibcon#read 5, iclass 36, count 2 2006.257.23:26:19.34#ibcon#about to read 6, iclass 36, count 2 2006.257.23:26:19.34#ibcon#read 6, iclass 36, count 2 2006.257.23:26:19.34#ibcon#end of sib2, iclass 36, count 2 2006.257.23:26:19.34#ibcon#*mode == 0, iclass 36, count 2 2006.257.23:26:19.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.23:26:19.34#ibcon#[27=AT07-04\r\n] 2006.257.23:26:19.34#ibcon#*before write, iclass 36, count 2 2006.257.23:26:19.34#ibcon#enter sib2, iclass 36, count 2 2006.257.23:26:19.34#ibcon#flushed, iclass 36, count 2 2006.257.23:26:19.34#ibcon#about to write, iclass 36, count 2 2006.257.23:26:19.34#ibcon#wrote, iclass 36, count 2 2006.257.23:26:19.34#ibcon#about to read 3, iclass 36, count 2 2006.257.23:26:19.37#ibcon#read 3, iclass 36, count 2 2006.257.23:26:19.37#ibcon#about to read 4, iclass 36, count 2 2006.257.23:26:19.37#ibcon#read 4, iclass 36, count 2 2006.257.23:26:19.37#ibcon#about to read 5, iclass 36, count 2 2006.257.23:26:19.37#ibcon#read 5, iclass 36, count 2 2006.257.23:26:19.37#ibcon#about to read 6, iclass 36, count 2 2006.257.23:26:19.37#ibcon#read 6, iclass 36, count 2 2006.257.23:26:19.37#ibcon#end of sib2, iclass 36, count 2 2006.257.23:26:19.37#ibcon#*after write, iclass 36, count 2 2006.257.23:26:19.37#ibcon#*before return 0, iclass 36, count 2 2006.257.23:26:19.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:19.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:26:19.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.23:26:19.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:19.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:19.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:19.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:19.49#ibcon#enter wrdev, iclass 36, count 0 2006.257.23:26:19.49#ibcon#first serial, iclass 36, count 0 2006.257.23:26:19.49#ibcon#enter sib2, iclass 36, count 0 2006.257.23:26:19.49#ibcon#flushed, iclass 36, count 0 2006.257.23:26:19.49#ibcon#about to write, iclass 36, count 0 2006.257.23:26:19.49#ibcon#wrote, iclass 36, count 0 2006.257.23:26:19.49#ibcon#about to read 3, iclass 36, count 0 2006.257.23:26:19.51#ibcon#read 3, iclass 36, count 0 2006.257.23:26:19.51#ibcon#about to read 4, iclass 36, count 0 2006.257.23:26:19.51#ibcon#read 4, iclass 36, count 0 2006.257.23:26:19.51#ibcon#about to read 5, iclass 36, count 0 2006.257.23:26:19.51#ibcon#read 5, iclass 36, count 0 2006.257.23:26:19.51#ibcon#about to read 6, iclass 36, count 0 2006.257.23:26:19.51#ibcon#read 6, iclass 36, count 0 2006.257.23:26:19.51#ibcon#end of sib2, iclass 36, count 0 2006.257.23:26:19.51#ibcon#*mode == 0, iclass 36, count 0 2006.257.23:26:19.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.23:26:19.51#ibcon#[27=USB\r\n] 2006.257.23:26:19.51#ibcon#*before write, iclass 36, count 0 2006.257.23:26:19.51#ibcon#enter sib2, iclass 36, count 0 2006.257.23:26:19.51#ibcon#flushed, iclass 36, count 0 2006.257.23:26:19.51#ibcon#about to write, iclass 36, count 0 2006.257.23:26:19.51#ibcon#wrote, iclass 36, count 0 2006.257.23:26:19.51#ibcon#about to read 3, iclass 36, count 0 2006.257.23:26:19.54#ibcon#read 3, iclass 36, count 0 2006.257.23:26:19.54#ibcon#about to read 4, iclass 36, count 0 2006.257.23:26:19.54#ibcon#read 4, iclass 36, count 0 2006.257.23:26:19.54#ibcon#about to read 5, iclass 36, count 0 2006.257.23:26:19.54#ibcon#read 5, iclass 36, count 0 2006.257.23:26:19.54#ibcon#about to read 6, iclass 36, count 0 2006.257.23:26:19.54#ibcon#read 6, iclass 36, count 0 2006.257.23:26:19.54#ibcon#end of sib2, iclass 36, count 0 2006.257.23:26:19.54#ibcon#*after write, iclass 36, count 0 2006.257.23:26:19.54#ibcon#*before return 0, iclass 36, count 0 2006.257.23:26:19.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:19.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:26:19.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.23:26:19.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.23:26:19.54$vck44/vblo=8,744.99 2006.257.23:26:19.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.23:26:19.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.23:26:19.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:26:19.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:19.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:19.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:19.54#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:26:19.54#ibcon#first serial, iclass 38, count 0 2006.257.23:26:19.54#ibcon#enter sib2, iclass 38, count 0 2006.257.23:26:19.54#ibcon#flushed, iclass 38, count 0 2006.257.23:26:19.54#ibcon#about to write, iclass 38, count 0 2006.257.23:26:19.54#ibcon#wrote, iclass 38, count 0 2006.257.23:26:19.54#ibcon#about to read 3, iclass 38, count 0 2006.257.23:26:19.56#ibcon#read 3, iclass 38, count 0 2006.257.23:26:19.56#ibcon#about to read 4, iclass 38, count 0 2006.257.23:26:19.56#ibcon#read 4, iclass 38, count 0 2006.257.23:26:19.56#ibcon#about to read 5, iclass 38, count 0 2006.257.23:26:19.56#ibcon#read 5, iclass 38, count 0 2006.257.23:26:19.56#ibcon#about to read 6, iclass 38, count 0 2006.257.23:26:19.56#ibcon#read 6, iclass 38, count 0 2006.257.23:26:19.56#ibcon#end of sib2, iclass 38, count 0 2006.257.23:26:19.56#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:26:19.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:26:19.56#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:26:19.56#ibcon#*before write, iclass 38, count 0 2006.257.23:26:19.56#ibcon#enter sib2, iclass 38, count 0 2006.257.23:26:19.56#ibcon#flushed, iclass 38, count 0 2006.257.23:26:19.56#ibcon#about to write, iclass 38, count 0 2006.257.23:26:19.56#ibcon#wrote, iclass 38, count 0 2006.257.23:26:19.56#ibcon#about to read 3, iclass 38, count 0 2006.257.23:26:19.60#ibcon#read 3, iclass 38, count 0 2006.257.23:26:19.60#ibcon#about to read 4, iclass 38, count 0 2006.257.23:26:19.60#ibcon#read 4, iclass 38, count 0 2006.257.23:26:19.60#ibcon#about to read 5, iclass 38, count 0 2006.257.23:26:19.60#ibcon#read 5, iclass 38, count 0 2006.257.23:26:19.60#ibcon#about to read 6, iclass 38, count 0 2006.257.23:26:19.60#ibcon#read 6, iclass 38, count 0 2006.257.23:26:19.60#ibcon#end of sib2, iclass 38, count 0 2006.257.23:26:19.60#ibcon#*after write, iclass 38, count 0 2006.257.23:26:19.60#ibcon#*before return 0, iclass 38, count 0 2006.257.23:26:19.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:19.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:26:19.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:26:19.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:26:19.60$vck44/vb=8,4 2006.257.23:26:19.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.23:26:19.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.23:26:19.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:26:19.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:19.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:19.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:19.66#ibcon#enter wrdev, iclass 40, count 2 2006.257.23:26:19.66#ibcon#first serial, iclass 40, count 2 2006.257.23:26:19.66#ibcon#enter sib2, iclass 40, count 2 2006.257.23:26:19.66#ibcon#flushed, iclass 40, count 2 2006.257.23:26:19.66#ibcon#about to write, iclass 40, count 2 2006.257.23:26:19.66#ibcon#wrote, iclass 40, count 2 2006.257.23:26:19.66#ibcon#about to read 3, iclass 40, count 2 2006.257.23:26:19.68#ibcon#read 3, iclass 40, count 2 2006.257.23:26:19.68#ibcon#about to read 4, iclass 40, count 2 2006.257.23:26:19.68#ibcon#read 4, iclass 40, count 2 2006.257.23:26:19.68#ibcon#about to read 5, iclass 40, count 2 2006.257.23:26:19.68#ibcon#read 5, iclass 40, count 2 2006.257.23:26:19.68#ibcon#about to read 6, iclass 40, count 2 2006.257.23:26:19.68#ibcon#read 6, iclass 40, count 2 2006.257.23:26:19.68#ibcon#end of sib2, iclass 40, count 2 2006.257.23:26:19.68#ibcon#*mode == 0, iclass 40, count 2 2006.257.23:26:19.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.23:26:19.68#ibcon#[27=AT08-04\r\n] 2006.257.23:26:19.68#ibcon#*before write, iclass 40, count 2 2006.257.23:26:19.68#ibcon#enter sib2, iclass 40, count 2 2006.257.23:26:19.68#ibcon#flushed, iclass 40, count 2 2006.257.23:26:19.68#ibcon#about to write, iclass 40, count 2 2006.257.23:26:19.68#ibcon#wrote, iclass 40, count 2 2006.257.23:26:19.68#ibcon#about to read 3, iclass 40, count 2 2006.257.23:26:19.71#ibcon#read 3, iclass 40, count 2 2006.257.23:26:19.71#ibcon#about to read 4, iclass 40, count 2 2006.257.23:26:19.71#ibcon#read 4, iclass 40, count 2 2006.257.23:26:19.71#ibcon#about to read 5, iclass 40, count 2 2006.257.23:26:19.71#ibcon#read 5, iclass 40, count 2 2006.257.23:26:19.71#ibcon#about to read 6, iclass 40, count 2 2006.257.23:26:19.71#ibcon#read 6, iclass 40, count 2 2006.257.23:26:19.71#ibcon#end of sib2, iclass 40, count 2 2006.257.23:26:19.71#ibcon#*after write, iclass 40, count 2 2006.257.23:26:19.71#ibcon#*before return 0, iclass 40, count 2 2006.257.23:26:19.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:19.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:26:19.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.23:26:19.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:26:19.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:19.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:19.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:19.83#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:26:19.83#ibcon#first serial, iclass 40, count 0 2006.257.23:26:19.83#ibcon#enter sib2, iclass 40, count 0 2006.257.23:26:19.83#ibcon#flushed, iclass 40, count 0 2006.257.23:26:19.83#ibcon#about to write, iclass 40, count 0 2006.257.23:26:19.83#ibcon#wrote, iclass 40, count 0 2006.257.23:26:19.83#ibcon#about to read 3, iclass 40, count 0 2006.257.23:26:19.85#ibcon#read 3, iclass 40, count 0 2006.257.23:26:19.85#ibcon#about to read 4, iclass 40, count 0 2006.257.23:26:19.85#ibcon#read 4, iclass 40, count 0 2006.257.23:26:19.85#ibcon#about to read 5, iclass 40, count 0 2006.257.23:26:19.85#ibcon#read 5, iclass 40, count 0 2006.257.23:26:19.85#ibcon#about to read 6, iclass 40, count 0 2006.257.23:26:19.85#ibcon#read 6, iclass 40, count 0 2006.257.23:26:19.85#ibcon#end of sib2, iclass 40, count 0 2006.257.23:26:19.85#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:26:19.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:26:19.85#ibcon#[27=USB\r\n] 2006.257.23:26:19.85#ibcon#*before write, iclass 40, count 0 2006.257.23:26:19.85#ibcon#enter sib2, iclass 40, count 0 2006.257.23:26:19.85#ibcon#flushed, iclass 40, count 0 2006.257.23:26:19.85#ibcon#about to write, iclass 40, count 0 2006.257.23:26:19.85#ibcon#wrote, iclass 40, count 0 2006.257.23:26:19.85#ibcon#about to read 3, iclass 40, count 0 2006.257.23:26:19.88#ibcon#read 3, iclass 40, count 0 2006.257.23:26:19.88#ibcon#about to read 4, iclass 40, count 0 2006.257.23:26:19.88#ibcon#read 4, iclass 40, count 0 2006.257.23:26:19.88#ibcon#about to read 5, iclass 40, count 0 2006.257.23:26:19.88#ibcon#read 5, iclass 40, count 0 2006.257.23:26:19.88#ibcon#about to read 6, iclass 40, count 0 2006.257.23:26:19.88#ibcon#read 6, iclass 40, count 0 2006.257.23:26:19.88#ibcon#end of sib2, iclass 40, count 0 2006.257.23:26:19.88#ibcon#*after write, iclass 40, count 0 2006.257.23:26:19.88#ibcon#*before return 0, iclass 40, count 0 2006.257.23:26:19.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:19.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:26:19.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:26:19.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:26:19.88$vck44/vabw=wide 2006.257.23:26:19.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.23:26:19.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.23:26:19.88#ibcon#ireg 8 cls_cnt 0 2006.257.23:26:19.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:19.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:19.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:19.88#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:26:19.88#ibcon#first serial, iclass 4, count 0 2006.257.23:26:19.88#ibcon#enter sib2, iclass 4, count 0 2006.257.23:26:19.88#ibcon#flushed, iclass 4, count 0 2006.257.23:26:19.88#ibcon#about to write, iclass 4, count 0 2006.257.23:26:19.88#ibcon#wrote, iclass 4, count 0 2006.257.23:26:19.88#ibcon#about to read 3, iclass 4, count 0 2006.257.23:26:19.90#ibcon#read 3, iclass 4, count 0 2006.257.23:26:19.90#ibcon#about to read 4, iclass 4, count 0 2006.257.23:26:19.90#ibcon#read 4, iclass 4, count 0 2006.257.23:26:19.90#ibcon#about to read 5, iclass 4, count 0 2006.257.23:26:19.90#ibcon#read 5, iclass 4, count 0 2006.257.23:26:19.90#ibcon#about to read 6, iclass 4, count 0 2006.257.23:26:19.90#ibcon#read 6, iclass 4, count 0 2006.257.23:26:19.90#ibcon#end of sib2, iclass 4, count 0 2006.257.23:26:19.90#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:26:19.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:26:19.90#ibcon#[25=BW32\r\n] 2006.257.23:26:19.90#ibcon#*before write, iclass 4, count 0 2006.257.23:26:19.90#ibcon#enter sib2, iclass 4, count 0 2006.257.23:26:19.90#ibcon#flushed, iclass 4, count 0 2006.257.23:26:19.90#ibcon#about to write, iclass 4, count 0 2006.257.23:26:19.90#ibcon#wrote, iclass 4, count 0 2006.257.23:26:19.90#ibcon#about to read 3, iclass 4, count 0 2006.257.23:26:19.93#ibcon#read 3, iclass 4, count 0 2006.257.23:26:19.93#ibcon#about to read 4, iclass 4, count 0 2006.257.23:26:19.93#ibcon#read 4, iclass 4, count 0 2006.257.23:26:19.93#ibcon#about to read 5, iclass 4, count 0 2006.257.23:26:19.93#ibcon#read 5, iclass 4, count 0 2006.257.23:26:19.93#ibcon#about to read 6, iclass 4, count 0 2006.257.23:26:19.93#ibcon#read 6, iclass 4, count 0 2006.257.23:26:19.93#ibcon#end of sib2, iclass 4, count 0 2006.257.23:26:19.93#ibcon#*after write, iclass 4, count 0 2006.257.23:26:19.93#ibcon#*before return 0, iclass 4, count 0 2006.257.23:26:19.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:19.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:26:19.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:26:19.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:26:19.93$vck44/vbbw=wide 2006.257.23:26:19.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.23:26:19.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.23:26:19.93#ibcon#ireg 8 cls_cnt 0 2006.257.23:26:19.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:26:20.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:26:20.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:26:20.00#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:26:20.00#ibcon#first serial, iclass 6, count 0 2006.257.23:26:20.00#ibcon#enter sib2, iclass 6, count 0 2006.257.23:26:20.00#ibcon#flushed, iclass 6, count 0 2006.257.23:26:20.00#ibcon#about to write, iclass 6, count 0 2006.257.23:26:20.00#ibcon#wrote, iclass 6, count 0 2006.257.23:26:20.00#ibcon#about to read 3, iclass 6, count 0 2006.257.23:26:20.02#ibcon#read 3, iclass 6, count 0 2006.257.23:26:20.02#ibcon#about to read 4, iclass 6, count 0 2006.257.23:26:20.02#ibcon#read 4, iclass 6, count 0 2006.257.23:26:20.02#ibcon#about to read 5, iclass 6, count 0 2006.257.23:26:20.02#ibcon#read 5, iclass 6, count 0 2006.257.23:26:20.02#ibcon#about to read 6, iclass 6, count 0 2006.257.23:26:20.02#ibcon#read 6, iclass 6, count 0 2006.257.23:26:20.02#ibcon#end of sib2, iclass 6, count 0 2006.257.23:26:20.02#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:26:20.02#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:26:20.02#ibcon#[27=BW32\r\n] 2006.257.23:26:20.02#ibcon#*before write, iclass 6, count 0 2006.257.23:26:20.02#ibcon#enter sib2, iclass 6, count 0 2006.257.23:26:20.02#ibcon#flushed, iclass 6, count 0 2006.257.23:26:20.02#ibcon#about to write, iclass 6, count 0 2006.257.23:26:20.02#ibcon#wrote, iclass 6, count 0 2006.257.23:26:20.02#ibcon#about to read 3, iclass 6, count 0 2006.257.23:26:20.05#ibcon#read 3, iclass 6, count 0 2006.257.23:26:20.05#ibcon#about to read 4, iclass 6, count 0 2006.257.23:26:20.05#ibcon#read 4, iclass 6, count 0 2006.257.23:26:20.05#ibcon#about to read 5, iclass 6, count 0 2006.257.23:26:20.05#ibcon#read 5, iclass 6, count 0 2006.257.23:26:20.05#ibcon#about to read 6, iclass 6, count 0 2006.257.23:26:20.05#ibcon#read 6, iclass 6, count 0 2006.257.23:26:20.05#ibcon#end of sib2, iclass 6, count 0 2006.257.23:26:20.05#ibcon#*after write, iclass 6, count 0 2006.257.23:26:20.05#ibcon#*before return 0, iclass 6, count 0 2006.257.23:26:20.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:26:20.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:26:20.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:26:20.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:26:20.05$setupk4/ifdk4 2006.257.23:26:20.05$ifdk4/lo= 2006.257.23:26:20.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:26:20.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:26:20.05$ifdk4/patch= 2006.257.23:26:20.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:26:20.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:26:20.05$setupk4/!*+20s 2006.257.23:26:23.42#abcon#<5=/16 1.5 4.9 20.59 821016.1\r\n> 2006.257.23:26:23.45#abcon#{5=INTERFACE CLEAR} 2006.257.23:26:23.51#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:26:33.59#abcon#<5=/16 1.5 4.9 20.60 831016.1\r\n> 2006.257.23:26:33.62#abcon#{5=INTERFACE CLEAR} 2006.257.23:26:33.67#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:26:34.57$setupk4/"tpicd 2006.257.23:26:34.57$setupk4/echo=off 2006.257.23:26:34.57$setupk4/xlog=off 2006.257.23:26:34.57:!2006.257.23:36:48 2006.257.23:27:08.14#trakl#Source acquired 2006.257.23:27:08.15#flagr#flagr/antenna,acquired 2006.257.23:36:48.00:preob 2006.257.23:36:48.14/onsource/TRACKING 2006.257.23:36:48.14:!2006.257.23:36:58 2006.257.23:36:58.00:"tape 2006.257.23:36:58.00:"st=record 2006.257.23:36:58.00:data_valid=on 2006.257.23:36:58.00:midob 2006.257.23:36:59.14/onsource/TRACKING 2006.257.23:36:59.14/wx/20.82,1016.1,81 2006.257.23:36:59.24/cable/+6.4826E-03 2006.257.23:37:00.33/va/01,08,usb,yes,30,33 2006.257.23:37:00.33/va/02,07,usb,yes,33,33 2006.257.23:37:00.33/va/03,08,usb,yes,29,31 2006.257.23:37:00.33/va/04,07,usb,yes,34,35 2006.257.23:37:00.33/va/05,04,usb,yes,30,31 2006.257.23:37:00.33/va/06,04,usb,yes,34,33 2006.257.23:37:00.33/va/07,04,usb,yes,35,35 2006.257.23:37:00.33/va/08,04,usb,yes,29,35 2006.257.23:37:00.56/valo/01,524.99,yes,locked 2006.257.23:37:00.56/valo/02,534.99,yes,locked 2006.257.23:37:00.56/valo/03,564.99,yes,locked 2006.257.23:37:00.56/valo/04,624.99,yes,locked 2006.257.23:37:00.56/valo/05,734.99,yes,locked 2006.257.23:37:00.56/valo/06,814.99,yes,locked 2006.257.23:37:00.56/valo/07,864.99,yes,locked 2006.257.23:37:00.56/valo/08,884.99,yes,locked 2006.257.23:37:01.65/vb/01,04,usb,yes,30,28 2006.257.23:37:01.65/vb/02,05,usb,yes,28,28 2006.257.23:37:01.65/vb/03,04,usb,yes,29,32 2006.257.23:37:01.65/vb/04,05,usb,yes,30,29 2006.257.23:37:01.65/vb/05,04,usb,yes,26,29 2006.257.23:37:01.65/vb/06,04,usb,yes,31,27 2006.257.23:37:01.65/vb/07,04,usb,yes,30,30 2006.257.23:37:01.65/vb/08,04,usb,yes,28,31 2006.257.23:37:01.88/vblo/01,629.99,yes,locked 2006.257.23:37:01.88/vblo/02,634.99,yes,locked 2006.257.23:37:01.88/vblo/03,649.99,yes,locked 2006.257.23:37:01.88/vblo/04,679.99,yes,locked 2006.257.23:37:01.88/vblo/05,709.99,yes,locked 2006.257.23:37:01.88/vblo/06,719.99,yes,locked 2006.257.23:37:01.88/vblo/07,734.99,yes,locked 2006.257.23:37:01.88/vblo/08,744.99,yes,locked 2006.257.23:37:02.03/vabw/8 2006.257.23:37:02.18/vbbw/8 2006.257.23:37:02.27/xfe/off,on,15.2 2006.257.23:37:02.65/ifatt/23,28,28,28 2006.257.23:37:03.07/fmout-gps/S +4.55E-07 2006.257.23:37:03.11:!2006.257.23:41:48 2006.257.23:41:48.01:data_valid=off 2006.257.23:41:48.02:"et 2006.257.23:41:48.02:!+3s 2006.257.23:41:51.03:"tape 2006.257.23:41:51.03:postob 2006.257.23:41:51.27/cable/+6.4813E-03 2006.257.23:41:51.27/wx/20.90,1016.2,79 2006.257.23:41:51.33/fmout-gps/S +4.51E-07 2006.257.23:41:51.33:scan_name=257-2346,jd0609,130 2006.257.23:41:51.34:source=0059+581,010245.76,582411.1,2000.0,cw 2006.257.23:41:52.13#flagr#flagr/antenna,new-source 2006.257.23:41:52.14:checkk5 2006.257.23:41:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:41:52.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:41:53.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:41:53.51/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:41:53.85/chk_obsdata//k5ts1/T2572336??a.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.257.23:41:54.20/chk_obsdata//k5ts2/T2572336??b.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.257.23:41:54.54/chk_obsdata//k5ts3/T2572336??c.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.257.23:41:54.88/chk_obsdata//k5ts4/T2572336??d.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.257.23:41:55.55/k5log//k5ts1_log_newline 2006.257.23:41:56.21/k5log//k5ts2_log_newline 2006.257.23:41:56.87/k5log//k5ts3_log_newline 2006.257.23:41:57.52/k5log//k5ts4_log_newline 2006.257.23:41:57.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:41:57.55:setupk4=1 2006.257.23:41:57.55$setupk4/echo=on 2006.257.23:41:57.55$setupk4/pcalon 2006.257.23:41:57.55$pcalon/"no phase cal control is implemented here 2006.257.23:41:57.55$setupk4/"tpicd=stop 2006.257.23:41:57.55$setupk4/"rec=synch_on 2006.257.23:41:57.55$setupk4/"rec_mode=128 2006.257.23:41:57.55$setupk4/!* 2006.257.23:41:57.55$setupk4/recpk4 2006.257.23:41:57.55$recpk4/recpatch= 2006.257.23:41:57.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:41:57.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:41:57.55$setupk4/vck44 2006.257.23:41:57.55$vck44/valo=1,524.99 2006.257.23:41:57.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.23:41:57.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.23:41:57.55#ibcon#ireg 17 cls_cnt 0 2006.257.23:41:57.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:41:57.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:41:57.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:41:57.55#ibcon#enter wrdev, iclass 21, count 0 2006.257.23:41:57.55#ibcon#first serial, iclass 21, count 0 2006.257.23:41:57.55#ibcon#enter sib2, iclass 21, count 0 2006.257.23:41:57.55#ibcon#flushed, iclass 21, count 0 2006.257.23:41:57.55#ibcon#about to write, iclass 21, count 0 2006.257.23:41:57.55#ibcon#wrote, iclass 21, count 0 2006.257.23:41:57.55#ibcon#about to read 3, iclass 21, count 0 2006.257.23:41:57.57#ibcon#read 3, iclass 21, count 0 2006.257.23:41:57.57#ibcon#about to read 4, iclass 21, count 0 2006.257.23:41:57.57#ibcon#read 4, iclass 21, count 0 2006.257.23:41:57.57#ibcon#about to read 5, iclass 21, count 0 2006.257.23:41:57.57#ibcon#read 5, iclass 21, count 0 2006.257.23:41:57.57#ibcon#about to read 6, iclass 21, count 0 2006.257.23:41:57.57#ibcon#read 6, iclass 21, count 0 2006.257.23:41:57.57#ibcon#end of sib2, iclass 21, count 0 2006.257.23:41:57.57#ibcon#*mode == 0, iclass 21, count 0 2006.257.23:41:57.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.23:41:57.57#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:41:57.57#ibcon#*before write, iclass 21, count 0 2006.257.23:41:57.57#ibcon#enter sib2, iclass 21, count 0 2006.257.23:41:57.57#ibcon#flushed, iclass 21, count 0 2006.257.23:41:57.57#ibcon#about to write, iclass 21, count 0 2006.257.23:41:57.57#ibcon#wrote, iclass 21, count 0 2006.257.23:41:57.57#ibcon#about to read 3, iclass 21, count 0 2006.257.23:41:57.62#ibcon#read 3, iclass 21, count 0 2006.257.23:41:57.62#ibcon#about to read 4, iclass 21, count 0 2006.257.23:41:57.62#ibcon#read 4, iclass 21, count 0 2006.257.23:41:57.62#ibcon#about to read 5, iclass 21, count 0 2006.257.23:41:57.62#ibcon#read 5, iclass 21, count 0 2006.257.23:41:57.62#ibcon#about to read 6, iclass 21, count 0 2006.257.23:41:57.62#ibcon#read 6, iclass 21, count 0 2006.257.23:41:57.62#ibcon#end of sib2, iclass 21, count 0 2006.257.23:41:57.62#ibcon#*after write, iclass 21, count 0 2006.257.23:41:57.62#ibcon#*before return 0, iclass 21, count 0 2006.257.23:41:57.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:41:57.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:41:57.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.23:41:57.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.23:41:57.62$vck44/va=1,8 2006.257.23:41:57.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.23:41:57.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.23:41:57.62#ibcon#ireg 11 cls_cnt 2 2006.257.23:41:57.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:41:57.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:41:57.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:41:57.62#ibcon#enter wrdev, iclass 23, count 2 2006.257.23:41:57.62#ibcon#first serial, iclass 23, count 2 2006.257.23:41:57.62#ibcon#enter sib2, iclass 23, count 2 2006.257.23:41:57.62#ibcon#flushed, iclass 23, count 2 2006.257.23:41:57.62#ibcon#about to write, iclass 23, count 2 2006.257.23:41:57.62#ibcon#wrote, iclass 23, count 2 2006.257.23:41:57.62#ibcon#about to read 3, iclass 23, count 2 2006.257.23:41:57.64#ibcon#read 3, iclass 23, count 2 2006.257.23:41:57.64#ibcon#about to read 4, iclass 23, count 2 2006.257.23:41:57.64#ibcon#read 4, iclass 23, count 2 2006.257.23:41:57.64#ibcon#about to read 5, iclass 23, count 2 2006.257.23:41:57.64#ibcon#read 5, iclass 23, count 2 2006.257.23:41:57.64#ibcon#about to read 6, iclass 23, count 2 2006.257.23:41:57.64#ibcon#read 6, iclass 23, count 2 2006.257.23:41:57.64#ibcon#end of sib2, iclass 23, count 2 2006.257.23:41:57.64#ibcon#*mode == 0, iclass 23, count 2 2006.257.23:41:57.64#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.23:41:57.64#ibcon#[25=AT01-08\r\n] 2006.257.23:41:57.64#ibcon#*before write, iclass 23, count 2 2006.257.23:41:57.64#ibcon#enter sib2, iclass 23, count 2 2006.257.23:41:57.64#ibcon#flushed, iclass 23, count 2 2006.257.23:41:57.64#ibcon#about to write, iclass 23, count 2 2006.257.23:41:57.64#ibcon#wrote, iclass 23, count 2 2006.257.23:41:57.64#ibcon#about to read 3, iclass 23, count 2 2006.257.23:41:57.67#ibcon#read 3, iclass 23, count 2 2006.257.23:41:57.67#ibcon#about to read 4, iclass 23, count 2 2006.257.23:41:57.67#ibcon#read 4, iclass 23, count 2 2006.257.23:41:57.67#ibcon#about to read 5, iclass 23, count 2 2006.257.23:41:57.67#ibcon#read 5, iclass 23, count 2 2006.257.23:41:57.67#ibcon#about to read 6, iclass 23, count 2 2006.257.23:41:57.67#ibcon#read 6, iclass 23, count 2 2006.257.23:41:57.67#ibcon#end of sib2, iclass 23, count 2 2006.257.23:41:57.67#ibcon#*after write, iclass 23, count 2 2006.257.23:41:57.67#ibcon#*before return 0, iclass 23, count 2 2006.257.23:41:57.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:41:57.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:41:57.67#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.23:41:57.67#ibcon#ireg 7 cls_cnt 0 2006.257.23:41:57.67#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:41:57.79#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:41:57.79#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:41:57.79#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:41:57.79#ibcon#first serial, iclass 23, count 0 2006.257.23:41:57.79#ibcon#enter sib2, iclass 23, count 0 2006.257.23:41:57.79#ibcon#flushed, iclass 23, count 0 2006.257.23:41:57.79#ibcon#about to write, iclass 23, count 0 2006.257.23:41:57.79#ibcon#wrote, iclass 23, count 0 2006.257.23:41:57.79#ibcon#about to read 3, iclass 23, count 0 2006.257.23:41:57.81#ibcon#read 3, iclass 23, count 0 2006.257.23:41:57.81#ibcon#about to read 4, iclass 23, count 0 2006.257.23:41:57.81#ibcon#read 4, iclass 23, count 0 2006.257.23:41:57.81#ibcon#about to read 5, iclass 23, count 0 2006.257.23:41:57.81#ibcon#read 5, iclass 23, count 0 2006.257.23:41:57.81#ibcon#about to read 6, iclass 23, count 0 2006.257.23:41:57.81#ibcon#read 6, iclass 23, count 0 2006.257.23:41:57.81#ibcon#end of sib2, iclass 23, count 0 2006.257.23:41:57.81#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:41:57.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:41:57.81#ibcon#[25=USB\r\n] 2006.257.23:41:57.81#ibcon#*before write, iclass 23, count 0 2006.257.23:41:57.81#ibcon#enter sib2, iclass 23, count 0 2006.257.23:41:57.81#ibcon#flushed, iclass 23, count 0 2006.257.23:41:57.81#ibcon#about to write, iclass 23, count 0 2006.257.23:41:57.81#ibcon#wrote, iclass 23, count 0 2006.257.23:41:57.81#ibcon#about to read 3, iclass 23, count 0 2006.257.23:41:57.84#ibcon#read 3, iclass 23, count 0 2006.257.23:41:57.84#ibcon#about to read 4, iclass 23, count 0 2006.257.23:41:57.84#ibcon#read 4, iclass 23, count 0 2006.257.23:41:57.84#ibcon#about to read 5, iclass 23, count 0 2006.257.23:41:57.84#ibcon#read 5, iclass 23, count 0 2006.257.23:41:57.84#ibcon#about to read 6, iclass 23, count 0 2006.257.23:41:57.84#ibcon#read 6, iclass 23, count 0 2006.257.23:41:57.84#ibcon#end of sib2, iclass 23, count 0 2006.257.23:41:57.84#ibcon#*after write, iclass 23, count 0 2006.257.23:41:57.84#ibcon#*before return 0, iclass 23, count 0 2006.257.23:41:57.84#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:41:57.84#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:41:57.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:41:57.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:41:57.84$vck44/valo=2,534.99 2006.257.23:41:57.84#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.23:41:57.84#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.23:41:57.84#ibcon#ireg 17 cls_cnt 0 2006.257.23:41:57.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:41:57.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:41:57.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:41:57.84#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:41:57.84#ibcon#first serial, iclass 25, count 0 2006.257.23:41:57.84#ibcon#enter sib2, iclass 25, count 0 2006.257.23:41:57.84#ibcon#flushed, iclass 25, count 0 2006.257.23:41:57.84#ibcon#about to write, iclass 25, count 0 2006.257.23:41:57.84#ibcon#wrote, iclass 25, count 0 2006.257.23:41:57.84#ibcon#about to read 3, iclass 25, count 0 2006.257.23:41:57.86#ibcon#read 3, iclass 25, count 0 2006.257.23:41:57.86#ibcon#about to read 4, iclass 25, count 0 2006.257.23:41:57.86#ibcon#read 4, iclass 25, count 0 2006.257.23:41:57.86#ibcon#about to read 5, iclass 25, count 0 2006.257.23:41:57.86#ibcon#read 5, iclass 25, count 0 2006.257.23:41:57.86#ibcon#about to read 6, iclass 25, count 0 2006.257.23:41:57.86#ibcon#read 6, iclass 25, count 0 2006.257.23:41:57.86#ibcon#end of sib2, iclass 25, count 0 2006.257.23:41:57.86#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:41:57.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:41:57.86#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:41:57.86#ibcon#*before write, iclass 25, count 0 2006.257.23:41:57.86#ibcon#enter sib2, iclass 25, count 0 2006.257.23:41:57.86#ibcon#flushed, iclass 25, count 0 2006.257.23:41:57.86#ibcon#about to write, iclass 25, count 0 2006.257.23:41:57.86#ibcon#wrote, iclass 25, count 0 2006.257.23:41:57.86#ibcon#about to read 3, iclass 25, count 0 2006.257.23:41:57.90#ibcon#read 3, iclass 25, count 0 2006.257.23:41:57.90#ibcon#about to read 4, iclass 25, count 0 2006.257.23:41:57.90#ibcon#read 4, iclass 25, count 0 2006.257.23:41:57.90#ibcon#about to read 5, iclass 25, count 0 2006.257.23:41:57.90#ibcon#read 5, iclass 25, count 0 2006.257.23:41:57.90#ibcon#about to read 6, iclass 25, count 0 2006.257.23:41:57.90#ibcon#read 6, iclass 25, count 0 2006.257.23:41:57.90#ibcon#end of sib2, iclass 25, count 0 2006.257.23:41:57.90#ibcon#*after write, iclass 25, count 0 2006.257.23:41:57.90#ibcon#*before return 0, iclass 25, count 0 2006.257.23:41:57.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:41:57.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:41:57.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:41:57.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:41:57.90$vck44/va=2,7 2006.257.23:41:57.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.23:41:57.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.23:41:57.90#ibcon#ireg 11 cls_cnt 2 2006.257.23:41:57.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:41:57.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:41:57.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:41:57.96#ibcon#enter wrdev, iclass 27, count 2 2006.257.23:41:57.96#ibcon#first serial, iclass 27, count 2 2006.257.23:41:57.96#ibcon#enter sib2, iclass 27, count 2 2006.257.23:41:57.96#ibcon#flushed, iclass 27, count 2 2006.257.23:41:57.96#ibcon#about to write, iclass 27, count 2 2006.257.23:41:57.96#ibcon#wrote, iclass 27, count 2 2006.257.23:41:57.96#ibcon#about to read 3, iclass 27, count 2 2006.257.23:41:57.98#ibcon#read 3, iclass 27, count 2 2006.257.23:41:57.98#ibcon#about to read 4, iclass 27, count 2 2006.257.23:41:57.98#ibcon#read 4, iclass 27, count 2 2006.257.23:41:57.98#ibcon#about to read 5, iclass 27, count 2 2006.257.23:41:57.98#ibcon#read 5, iclass 27, count 2 2006.257.23:41:57.98#ibcon#about to read 6, iclass 27, count 2 2006.257.23:41:57.98#ibcon#read 6, iclass 27, count 2 2006.257.23:41:57.98#ibcon#end of sib2, iclass 27, count 2 2006.257.23:41:57.98#ibcon#*mode == 0, iclass 27, count 2 2006.257.23:41:57.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.23:41:57.98#ibcon#[25=AT02-07\r\n] 2006.257.23:41:57.98#ibcon#*before write, iclass 27, count 2 2006.257.23:41:57.98#ibcon#enter sib2, iclass 27, count 2 2006.257.23:41:57.98#ibcon#flushed, iclass 27, count 2 2006.257.23:41:57.98#ibcon#about to write, iclass 27, count 2 2006.257.23:41:57.98#ibcon#wrote, iclass 27, count 2 2006.257.23:41:57.98#ibcon#about to read 3, iclass 27, count 2 2006.257.23:41:58.01#ibcon#read 3, iclass 27, count 2 2006.257.23:41:58.01#ibcon#about to read 4, iclass 27, count 2 2006.257.23:41:58.01#ibcon#read 4, iclass 27, count 2 2006.257.23:41:58.01#ibcon#about to read 5, iclass 27, count 2 2006.257.23:41:58.01#ibcon#read 5, iclass 27, count 2 2006.257.23:41:58.01#ibcon#about to read 6, iclass 27, count 2 2006.257.23:41:58.01#ibcon#read 6, iclass 27, count 2 2006.257.23:41:58.01#ibcon#end of sib2, iclass 27, count 2 2006.257.23:41:58.01#ibcon#*after write, iclass 27, count 2 2006.257.23:41:58.01#ibcon#*before return 0, iclass 27, count 2 2006.257.23:41:58.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:41:58.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:41:58.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.23:41:58.01#ibcon#ireg 7 cls_cnt 0 2006.257.23:41:58.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:41:58.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:41:58.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:41:58.13#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:41:58.13#ibcon#first serial, iclass 27, count 0 2006.257.23:41:58.13#ibcon#enter sib2, iclass 27, count 0 2006.257.23:41:58.13#ibcon#flushed, iclass 27, count 0 2006.257.23:41:58.13#ibcon#about to write, iclass 27, count 0 2006.257.23:41:58.13#ibcon#wrote, iclass 27, count 0 2006.257.23:41:58.13#ibcon#about to read 3, iclass 27, count 0 2006.257.23:41:58.15#ibcon#read 3, iclass 27, count 0 2006.257.23:41:58.15#ibcon#about to read 4, iclass 27, count 0 2006.257.23:41:58.15#ibcon#read 4, iclass 27, count 0 2006.257.23:41:58.15#ibcon#about to read 5, iclass 27, count 0 2006.257.23:41:58.15#ibcon#read 5, iclass 27, count 0 2006.257.23:41:58.15#ibcon#about to read 6, iclass 27, count 0 2006.257.23:41:58.15#ibcon#read 6, iclass 27, count 0 2006.257.23:41:58.15#ibcon#end of sib2, iclass 27, count 0 2006.257.23:41:58.15#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:41:58.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:41:58.15#ibcon#[25=USB\r\n] 2006.257.23:41:58.15#ibcon#*before write, iclass 27, count 0 2006.257.23:41:58.15#ibcon#enter sib2, iclass 27, count 0 2006.257.23:41:58.15#ibcon#flushed, iclass 27, count 0 2006.257.23:41:58.15#ibcon#about to write, iclass 27, count 0 2006.257.23:41:58.15#ibcon#wrote, iclass 27, count 0 2006.257.23:41:58.15#ibcon#about to read 3, iclass 27, count 0 2006.257.23:41:58.18#ibcon#read 3, iclass 27, count 0 2006.257.23:41:58.18#ibcon#about to read 4, iclass 27, count 0 2006.257.23:41:58.18#ibcon#read 4, iclass 27, count 0 2006.257.23:41:58.18#ibcon#about to read 5, iclass 27, count 0 2006.257.23:41:58.18#ibcon#read 5, iclass 27, count 0 2006.257.23:41:58.18#ibcon#about to read 6, iclass 27, count 0 2006.257.23:41:58.18#ibcon#read 6, iclass 27, count 0 2006.257.23:41:58.18#ibcon#end of sib2, iclass 27, count 0 2006.257.23:41:58.18#ibcon#*after write, iclass 27, count 0 2006.257.23:41:58.18#ibcon#*before return 0, iclass 27, count 0 2006.257.23:41:58.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:41:58.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:41:58.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:41:58.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:41:58.18$vck44/valo=3,564.99 2006.257.23:41:58.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.23:41:58.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.23:41:58.18#ibcon#ireg 17 cls_cnt 0 2006.257.23:41:58.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:41:58.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:41:58.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:41:58.18#ibcon#enter wrdev, iclass 29, count 0 2006.257.23:41:58.18#ibcon#first serial, iclass 29, count 0 2006.257.23:41:58.18#ibcon#enter sib2, iclass 29, count 0 2006.257.23:41:58.18#ibcon#flushed, iclass 29, count 0 2006.257.23:41:58.18#ibcon#about to write, iclass 29, count 0 2006.257.23:41:58.18#ibcon#wrote, iclass 29, count 0 2006.257.23:41:58.18#ibcon#about to read 3, iclass 29, count 0 2006.257.23:41:58.20#ibcon#read 3, iclass 29, count 0 2006.257.23:41:58.20#ibcon#about to read 4, iclass 29, count 0 2006.257.23:41:58.20#ibcon#read 4, iclass 29, count 0 2006.257.23:41:58.20#ibcon#about to read 5, iclass 29, count 0 2006.257.23:41:58.20#ibcon#read 5, iclass 29, count 0 2006.257.23:41:58.20#ibcon#about to read 6, iclass 29, count 0 2006.257.23:41:58.20#ibcon#read 6, iclass 29, count 0 2006.257.23:41:58.20#ibcon#end of sib2, iclass 29, count 0 2006.257.23:41:58.20#ibcon#*mode == 0, iclass 29, count 0 2006.257.23:41:58.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.23:41:58.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:41:58.20#ibcon#*before write, iclass 29, count 0 2006.257.23:41:58.20#ibcon#enter sib2, iclass 29, count 0 2006.257.23:41:58.20#ibcon#flushed, iclass 29, count 0 2006.257.23:41:58.20#ibcon#about to write, iclass 29, count 0 2006.257.23:41:58.20#ibcon#wrote, iclass 29, count 0 2006.257.23:41:58.20#ibcon#about to read 3, iclass 29, count 0 2006.257.23:41:58.24#ibcon#read 3, iclass 29, count 0 2006.257.23:41:58.24#ibcon#about to read 4, iclass 29, count 0 2006.257.23:41:58.24#ibcon#read 4, iclass 29, count 0 2006.257.23:41:58.24#ibcon#about to read 5, iclass 29, count 0 2006.257.23:41:58.24#ibcon#read 5, iclass 29, count 0 2006.257.23:41:58.24#ibcon#about to read 6, iclass 29, count 0 2006.257.23:41:58.24#ibcon#read 6, iclass 29, count 0 2006.257.23:41:58.24#ibcon#end of sib2, iclass 29, count 0 2006.257.23:41:58.24#ibcon#*after write, iclass 29, count 0 2006.257.23:41:58.24#ibcon#*before return 0, iclass 29, count 0 2006.257.23:41:58.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:41:58.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:41:58.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.23:41:58.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.23:41:58.24$vck44/va=3,8 2006.257.23:41:58.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.23:41:58.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.23:41:58.24#ibcon#ireg 11 cls_cnt 2 2006.257.23:41:58.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:41:58.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:41:58.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:41:58.30#ibcon#enter wrdev, iclass 31, count 2 2006.257.23:41:58.30#ibcon#first serial, iclass 31, count 2 2006.257.23:41:58.30#ibcon#enter sib2, iclass 31, count 2 2006.257.23:41:58.30#ibcon#flushed, iclass 31, count 2 2006.257.23:41:58.30#ibcon#about to write, iclass 31, count 2 2006.257.23:41:58.30#ibcon#wrote, iclass 31, count 2 2006.257.23:41:58.30#ibcon#about to read 3, iclass 31, count 2 2006.257.23:41:58.32#ibcon#read 3, iclass 31, count 2 2006.257.23:41:58.32#ibcon#about to read 4, iclass 31, count 2 2006.257.23:41:58.32#ibcon#read 4, iclass 31, count 2 2006.257.23:41:58.32#ibcon#about to read 5, iclass 31, count 2 2006.257.23:41:58.32#ibcon#read 5, iclass 31, count 2 2006.257.23:41:58.32#ibcon#about to read 6, iclass 31, count 2 2006.257.23:41:58.32#ibcon#read 6, iclass 31, count 2 2006.257.23:41:58.32#ibcon#end of sib2, iclass 31, count 2 2006.257.23:41:58.32#ibcon#*mode == 0, iclass 31, count 2 2006.257.23:41:58.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.23:41:58.32#ibcon#[25=AT03-08\r\n] 2006.257.23:41:58.32#ibcon#*before write, iclass 31, count 2 2006.257.23:41:58.32#ibcon#enter sib2, iclass 31, count 2 2006.257.23:41:58.32#ibcon#flushed, iclass 31, count 2 2006.257.23:41:58.32#ibcon#about to write, iclass 31, count 2 2006.257.23:41:58.32#ibcon#wrote, iclass 31, count 2 2006.257.23:41:58.32#ibcon#about to read 3, iclass 31, count 2 2006.257.23:41:58.35#ibcon#read 3, iclass 31, count 2 2006.257.23:41:58.35#ibcon#about to read 4, iclass 31, count 2 2006.257.23:41:58.35#ibcon#read 4, iclass 31, count 2 2006.257.23:41:58.35#ibcon#about to read 5, iclass 31, count 2 2006.257.23:41:58.35#ibcon#read 5, iclass 31, count 2 2006.257.23:41:58.35#ibcon#about to read 6, iclass 31, count 2 2006.257.23:41:58.35#ibcon#read 6, iclass 31, count 2 2006.257.23:41:58.35#ibcon#end of sib2, iclass 31, count 2 2006.257.23:41:58.35#ibcon#*after write, iclass 31, count 2 2006.257.23:41:58.35#ibcon#*before return 0, iclass 31, count 2 2006.257.23:41:58.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:41:58.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:41:58.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.23:41:58.35#ibcon#ireg 7 cls_cnt 0 2006.257.23:41:58.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:41:58.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:41:58.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:41:58.47#ibcon#enter wrdev, iclass 31, count 0 2006.257.23:41:58.47#ibcon#first serial, iclass 31, count 0 2006.257.23:41:58.47#ibcon#enter sib2, iclass 31, count 0 2006.257.23:41:58.47#ibcon#flushed, iclass 31, count 0 2006.257.23:41:58.47#ibcon#about to write, iclass 31, count 0 2006.257.23:41:58.47#ibcon#wrote, iclass 31, count 0 2006.257.23:41:58.47#ibcon#about to read 3, iclass 31, count 0 2006.257.23:41:58.49#ibcon#read 3, iclass 31, count 0 2006.257.23:41:58.49#ibcon#about to read 4, iclass 31, count 0 2006.257.23:41:58.49#ibcon#read 4, iclass 31, count 0 2006.257.23:41:58.49#ibcon#about to read 5, iclass 31, count 0 2006.257.23:41:58.49#ibcon#read 5, iclass 31, count 0 2006.257.23:41:58.49#ibcon#about to read 6, iclass 31, count 0 2006.257.23:41:58.49#ibcon#read 6, iclass 31, count 0 2006.257.23:41:58.49#ibcon#end of sib2, iclass 31, count 0 2006.257.23:41:58.49#ibcon#*mode == 0, iclass 31, count 0 2006.257.23:41:58.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.23:41:58.49#ibcon#[25=USB\r\n] 2006.257.23:41:58.49#ibcon#*before write, iclass 31, count 0 2006.257.23:41:58.49#ibcon#enter sib2, iclass 31, count 0 2006.257.23:41:58.49#ibcon#flushed, iclass 31, count 0 2006.257.23:41:58.49#ibcon#about to write, iclass 31, count 0 2006.257.23:41:58.49#ibcon#wrote, iclass 31, count 0 2006.257.23:41:58.49#ibcon#about to read 3, iclass 31, count 0 2006.257.23:41:58.52#ibcon#read 3, iclass 31, count 0 2006.257.23:41:58.52#ibcon#about to read 4, iclass 31, count 0 2006.257.23:41:58.52#ibcon#read 4, iclass 31, count 0 2006.257.23:41:58.52#ibcon#about to read 5, iclass 31, count 0 2006.257.23:41:58.52#ibcon#read 5, iclass 31, count 0 2006.257.23:41:58.52#ibcon#about to read 6, iclass 31, count 0 2006.257.23:41:58.52#ibcon#read 6, iclass 31, count 0 2006.257.23:41:58.52#ibcon#end of sib2, iclass 31, count 0 2006.257.23:41:58.52#ibcon#*after write, iclass 31, count 0 2006.257.23:41:58.52#ibcon#*before return 0, iclass 31, count 0 2006.257.23:41:58.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:41:58.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:41:58.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.23:41:58.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.23:41:58.52$vck44/valo=4,624.99 2006.257.23:41:58.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.23:41:58.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.23:41:58.52#ibcon#ireg 17 cls_cnt 0 2006.257.23:41:58.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:41:58.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:41:58.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:41:58.52#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:41:58.52#ibcon#first serial, iclass 33, count 0 2006.257.23:41:58.52#ibcon#enter sib2, iclass 33, count 0 2006.257.23:41:58.52#ibcon#flushed, iclass 33, count 0 2006.257.23:41:58.52#ibcon#about to write, iclass 33, count 0 2006.257.23:41:58.52#ibcon#wrote, iclass 33, count 0 2006.257.23:41:58.52#ibcon#about to read 3, iclass 33, count 0 2006.257.23:41:58.54#ibcon#read 3, iclass 33, count 0 2006.257.23:41:58.54#ibcon#about to read 4, iclass 33, count 0 2006.257.23:41:58.54#ibcon#read 4, iclass 33, count 0 2006.257.23:41:58.54#ibcon#about to read 5, iclass 33, count 0 2006.257.23:41:58.54#ibcon#read 5, iclass 33, count 0 2006.257.23:41:58.54#ibcon#about to read 6, iclass 33, count 0 2006.257.23:41:58.54#ibcon#read 6, iclass 33, count 0 2006.257.23:41:58.54#ibcon#end of sib2, iclass 33, count 0 2006.257.23:41:58.54#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:41:58.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:41:58.54#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:41:58.54#ibcon#*before write, iclass 33, count 0 2006.257.23:41:58.54#ibcon#enter sib2, iclass 33, count 0 2006.257.23:41:58.54#ibcon#flushed, iclass 33, count 0 2006.257.23:41:58.54#ibcon#about to write, iclass 33, count 0 2006.257.23:41:58.54#ibcon#wrote, iclass 33, count 0 2006.257.23:41:58.54#ibcon#about to read 3, iclass 33, count 0 2006.257.23:41:58.58#ibcon#read 3, iclass 33, count 0 2006.257.23:41:58.58#ibcon#about to read 4, iclass 33, count 0 2006.257.23:41:58.58#ibcon#read 4, iclass 33, count 0 2006.257.23:41:58.58#ibcon#about to read 5, iclass 33, count 0 2006.257.23:41:58.58#ibcon#read 5, iclass 33, count 0 2006.257.23:41:58.58#ibcon#about to read 6, iclass 33, count 0 2006.257.23:41:58.58#ibcon#read 6, iclass 33, count 0 2006.257.23:41:58.58#ibcon#end of sib2, iclass 33, count 0 2006.257.23:41:58.58#ibcon#*after write, iclass 33, count 0 2006.257.23:41:58.58#ibcon#*before return 0, iclass 33, count 0 2006.257.23:41:58.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:41:58.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:41:58.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:41:58.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:41:58.58$vck44/va=4,7 2006.257.23:41:58.58#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.23:41:58.58#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.23:41:58.58#ibcon#ireg 11 cls_cnt 2 2006.257.23:41:58.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:41:58.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:41:58.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:41:58.64#ibcon#enter wrdev, iclass 35, count 2 2006.257.23:41:58.64#ibcon#first serial, iclass 35, count 2 2006.257.23:41:58.64#ibcon#enter sib2, iclass 35, count 2 2006.257.23:41:58.64#ibcon#flushed, iclass 35, count 2 2006.257.23:41:58.64#ibcon#about to write, iclass 35, count 2 2006.257.23:41:58.64#ibcon#wrote, iclass 35, count 2 2006.257.23:41:58.64#ibcon#about to read 3, iclass 35, count 2 2006.257.23:41:58.66#ibcon#read 3, iclass 35, count 2 2006.257.23:41:58.66#ibcon#about to read 4, iclass 35, count 2 2006.257.23:41:58.66#ibcon#read 4, iclass 35, count 2 2006.257.23:41:58.66#ibcon#about to read 5, iclass 35, count 2 2006.257.23:41:58.66#ibcon#read 5, iclass 35, count 2 2006.257.23:41:58.66#ibcon#about to read 6, iclass 35, count 2 2006.257.23:41:58.66#ibcon#read 6, iclass 35, count 2 2006.257.23:41:58.66#ibcon#end of sib2, iclass 35, count 2 2006.257.23:41:58.66#ibcon#*mode == 0, iclass 35, count 2 2006.257.23:41:58.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.23:41:58.66#ibcon#[25=AT04-07\r\n] 2006.257.23:41:58.66#ibcon#*before write, iclass 35, count 2 2006.257.23:41:58.66#ibcon#enter sib2, iclass 35, count 2 2006.257.23:41:58.66#ibcon#flushed, iclass 35, count 2 2006.257.23:41:58.66#ibcon#about to write, iclass 35, count 2 2006.257.23:41:58.66#ibcon#wrote, iclass 35, count 2 2006.257.23:41:58.66#ibcon#about to read 3, iclass 35, count 2 2006.257.23:41:58.69#ibcon#read 3, iclass 35, count 2 2006.257.23:41:58.69#ibcon#about to read 4, iclass 35, count 2 2006.257.23:41:58.69#ibcon#read 4, iclass 35, count 2 2006.257.23:41:58.69#ibcon#about to read 5, iclass 35, count 2 2006.257.23:41:58.69#ibcon#read 5, iclass 35, count 2 2006.257.23:41:58.69#ibcon#about to read 6, iclass 35, count 2 2006.257.23:41:58.69#ibcon#read 6, iclass 35, count 2 2006.257.23:41:58.69#ibcon#end of sib2, iclass 35, count 2 2006.257.23:41:58.69#ibcon#*after write, iclass 35, count 2 2006.257.23:41:58.69#ibcon#*before return 0, iclass 35, count 2 2006.257.23:41:58.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:41:58.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:41:58.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.23:41:58.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:41:58.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:41:58.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:41:58.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:41:58.81#ibcon#enter wrdev, iclass 35, count 0 2006.257.23:41:58.81#ibcon#first serial, iclass 35, count 0 2006.257.23:41:58.81#ibcon#enter sib2, iclass 35, count 0 2006.257.23:41:58.81#ibcon#flushed, iclass 35, count 0 2006.257.23:41:58.81#ibcon#about to write, iclass 35, count 0 2006.257.23:41:58.81#ibcon#wrote, iclass 35, count 0 2006.257.23:41:58.81#ibcon#about to read 3, iclass 35, count 0 2006.257.23:41:58.83#ibcon#read 3, iclass 35, count 0 2006.257.23:41:58.83#ibcon#about to read 4, iclass 35, count 0 2006.257.23:41:58.83#ibcon#read 4, iclass 35, count 0 2006.257.23:41:58.83#ibcon#about to read 5, iclass 35, count 0 2006.257.23:41:58.83#ibcon#read 5, iclass 35, count 0 2006.257.23:41:58.83#ibcon#about to read 6, iclass 35, count 0 2006.257.23:41:58.83#ibcon#read 6, iclass 35, count 0 2006.257.23:41:58.83#ibcon#end of sib2, iclass 35, count 0 2006.257.23:41:58.83#ibcon#*mode == 0, iclass 35, count 0 2006.257.23:41:58.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.23:41:58.83#ibcon#[25=USB\r\n] 2006.257.23:41:58.83#ibcon#*before write, iclass 35, count 0 2006.257.23:41:58.83#ibcon#enter sib2, iclass 35, count 0 2006.257.23:41:58.83#ibcon#flushed, iclass 35, count 0 2006.257.23:41:58.83#ibcon#about to write, iclass 35, count 0 2006.257.23:41:58.83#ibcon#wrote, iclass 35, count 0 2006.257.23:41:58.83#ibcon#about to read 3, iclass 35, count 0 2006.257.23:41:58.86#ibcon#read 3, iclass 35, count 0 2006.257.23:41:58.86#ibcon#about to read 4, iclass 35, count 0 2006.257.23:41:58.86#ibcon#read 4, iclass 35, count 0 2006.257.23:41:58.86#ibcon#about to read 5, iclass 35, count 0 2006.257.23:41:58.86#ibcon#read 5, iclass 35, count 0 2006.257.23:41:58.86#ibcon#about to read 6, iclass 35, count 0 2006.257.23:41:58.86#ibcon#read 6, iclass 35, count 0 2006.257.23:41:58.86#ibcon#end of sib2, iclass 35, count 0 2006.257.23:41:58.86#ibcon#*after write, iclass 35, count 0 2006.257.23:41:58.86#ibcon#*before return 0, iclass 35, count 0 2006.257.23:41:58.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:41:58.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:41:58.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.23:41:58.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.23:41:58.86$vck44/valo=5,734.99 2006.257.23:41:58.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.23:41:58.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.23:41:58.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:41:58.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:41:58.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:41:58.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:41:58.86#ibcon#enter wrdev, iclass 37, count 0 2006.257.23:41:58.86#ibcon#first serial, iclass 37, count 0 2006.257.23:41:58.86#ibcon#enter sib2, iclass 37, count 0 2006.257.23:41:58.86#ibcon#flushed, iclass 37, count 0 2006.257.23:41:58.86#ibcon#about to write, iclass 37, count 0 2006.257.23:41:58.86#ibcon#wrote, iclass 37, count 0 2006.257.23:41:58.86#ibcon#about to read 3, iclass 37, count 0 2006.257.23:41:58.88#ibcon#read 3, iclass 37, count 0 2006.257.23:41:58.88#ibcon#about to read 4, iclass 37, count 0 2006.257.23:41:58.88#ibcon#read 4, iclass 37, count 0 2006.257.23:41:58.88#ibcon#about to read 5, iclass 37, count 0 2006.257.23:41:58.88#ibcon#read 5, iclass 37, count 0 2006.257.23:41:58.88#ibcon#about to read 6, iclass 37, count 0 2006.257.23:41:58.88#ibcon#read 6, iclass 37, count 0 2006.257.23:41:58.88#ibcon#end of sib2, iclass 37, count 0 2006.257.23:41:58.88#ibcon#*mode == 0, iclass 37, count 0 2006.257.23:41:58.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.23:41:58.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:41:58.88#ibcon#*before write, iclass 37, count 0 2006.257.23:41:58.88#ibcon#enter sib2, iclass 37, count 0 2006.257.23:41:58.88#ibcon#flushed, iclass 37, count 0 2006.257.23:41:58.88#ibcon#about to write, iclass 37, count 0 2006.257.23:41:58.88#ibcon#wrote, iclass 37, count 0 2006.257.23:41:58.88#ibcon#about to read 3, iclass 37, count 0 2006.257.23:41:58.92#ibcon#read 3, iclass 37, count 0 2006.257.23:41:58.92#ibcon#about to read 4, iclass 37, count 0 2006.257.23:41:58.92#ibcon#read 4, iclass 37, count 0 2006.257.23:41:58.92#ibcon#about to read 5, iclass 37, count 0 2006.257.23:41:58.92#ibcon#read 5, iclass 37, count 0 2006.257.23:41:58.92#ibcon#about to read 6, iclass 37, count 0 2006.257.23:41:58.92#ibcon#read 6, iclass 37, count 0 2006.257.23:41:58.92#ibcon#end of sib2, iclass 37, count 0 2006.257.23:41:58.92#ibcon#*after write, iclass 37, count 0 2006.257.23:41:58.92#ibcon#*before return 0, iclass 37, count 0 2006.257.23:41:58.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:41:58.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:41:58.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.23:41:58.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.23:41:58.92$vck44/va=5,4 2006.257.23:41:58.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.23:41:58.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.23:41:58.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:41:58.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:41:58.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:41:58.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:41:58.98#ibcon#enter wrdev, iclass 39, count 2 2006.257.23:41:58.98#ibcon#first serial, iclass 39, count 2 2006.257.23:41:58.98#ibcon#enter sib2, iclass 39, count 2 2006.257.23:41:58.98#ibcon#flushed, iclass 39, count 2 2006.257.23:41:58.98#ibcon#about to write, iclass 39, count 2 2006.257.23:41:58.98#ibcon#wrote, iclass 39, count 2 2006.257.23:41:58.98#ibcon#about to read 3, iclass 39, count 2 2006.257.23:41:59.00#ibcon#read 3, iclass 39, count 2 2006.257.23:41:59.00#ibcon#about to read 4, iclass 39, count 2 2006.257.23:41:59.00#ibcon#read 4, iclass 39, count 2 2006.257.23:41:59.00#ibcon#about to read 5, iclass 39, count 2 2006.257.23:41:59.00#ibcon#read 5, iclass 39, count 2 2006.257.23:41:59.00#ibcon#about to read 6, iclass 39, count 2 2006.257.23:41:59.00#ibcon#read 6, iclass 39, count 2 2006.257.23:41:59.00#ibcon#end of sib2, iclass 39, count 2 2006.257.23:41:59.00#ibcon#*mode == 0, iclass 39, count 2 2006.257.23:41:59.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.23:41:59.00#ibcon#[25=AT05-04\r\n] 2006.257.23:41:59.00#ibcon#*before write, iclass 39, count 2 2006.257.23:41:59.00#ibcon#enter sib2, iclass 39, count 2 2006.257.23:41:59.00#ibcon#flushed, iclass 39, count 2 2006.257.23:41:59.00#ibcon#about to write, iclass 39, count 2 2006.257.23:41:59.00#ibcon#wrote, iclass 39, count 2 2006.257.23:41:59.00#ibcon#about to read 3, iclass 39, count 2 2006.257.23:41:59.03#ibcon#read 3, iclass 39, count 2 2006.257.23:41:59.03#ibcon#about to read 4, iclass 39, count 2 2006.257.23:41:59.03#ibcon#read 4, iclass 39, count 2 2006.257.23:41:59.03#ibcon#about to read 5, iclass 39, count 2 2006.257.23:41:59.03#ibcon#read 5, iclass 39, count 2 2006.257.23:41:59.03#ibcon#about to read 6, iclass 39, count 2 2006.257.23:41:59.03#ibcon#read 6, iclass 39, count 2 2006.257.23:41:59.03#ibcon#end of sib2, iclass 39, count 2 2006.257.23:41:59.03#ibcon#*after write, iclass 39, count 2 2006.257.23:41:59.03#ibcon#*before return 0, iclass 39, count 2 2006.257.23:41:59.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:41:59.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:41:59.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.23:41:59.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:41:59.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:41:59.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:41:59.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:41:59.15#ibcon#enter wrdev, iclass 39, count 0 2006.257.23:41:59.15#ibcon#first serial, iclass 39, count 0 2006.257.23:41:59.15#ibcon#enter sib2, iclass 39, count 0 2006.257.23:41:59.15#ibcon#flushed, iclass 39, count 0 2006.257.23:41:59.15#ibcon#about to write, iclass 39, count 0 2006.257.23:41:59.15#ibcon#wrote, iclass 39, count 0 2006.257.23:41:59.15#ibcon#about to read 3, iclass 39, count 0 2006.257.23:41:59.17#ibcon#read 3, iclass 39, count 0 2006.257.23:41:59.17#ibcon#about to read 4, iclass 39, count 0 2006.257.23:41:59.17#ibcon#read 4, iclass 39, count 0 2006.257.23:41:59.17#ibcon#about to read 5, iclass 39, count 0 2006.257.23:41:59.17#ibcon#read 5, iclass 39, count 0 2006.257.23:41:59.17#ibcon#about to read 6, iclass 39, count 0 2006.257.23:41:59.17#ibcon#read 6, iclass 39, count 0 2006.257.23:41:59.17#ibcon#end of sib2, iclass 39, count 0 2006.257.23:41:59.17#ibcon#*mode == 0, iclass 39, count 0 2006.257.23:41:59.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.23:41:59.17#ibcon#[25=USB\r\n] 2006.257.23:41:59.17#ibcon#*before write, iclass 39, count 0 2006.257.23:41:59.17#ibcon#enter sib2, iclass 39, count 0 2006.257.23:41:59.17#ibcon#flushed, iclass 39, count 0 2006.257.23:41:59.17#ibcon#about to write, iclass 39, count 0 2006.257.23:41:59.17#ibcon#wrote, iclass 39, count 0 2006.257.23:41:59.17#ibcon#about to read 3, iclass 39, count 0 2006.257.23:41:59.20#ibcon#read 3, iclass 39, count 0 2006.257.23:41:59.20#ibcon#about to read 4, iclass 39, count 0 2006.257.23:41:59.20#ibcon#read 4, iclass 39, count 0 2006.257.23:41:59.20#ibcon#about to read 5, iclass 39, count 0 2006.257.23:41:59.20#ibcon#read 5, iclass 39, count 0 2006.257.23:41:59.20#ibcon#about to read 6, iclass 39, count 0 2006.257.23:41:59.20#ibcon#read 6, iclass 39, count 0 2006.257.23:41:59.20#ibcon#end of sib2, iclass 39, count 0 2006.257.23:41:59.20#ibcon#*after write, iclass 39, count 0 2006.257.23:41:59.20#ibcon#*before return 0, iclass 39, count 0 2006.257.23:41:59.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:41:59.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:41:59.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.23:41:59.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.23:41:59.20$vck44/valo=6,814.99 2006.257.23:41:59.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.23:41:59.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.23:41:59.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:41:59.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:41:59.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:41:59.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:41:59.20#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:41:59.20#ibcon#first serial, iclass 3, count 0 2006.257.23:41:59.20#ibcon#enter sib2, iclass 3, count 0 2006.257.23:41:59.20#ibcon#flushed, iclass 3, count 0 2006.257.23:41:59.20#ibcon#about to write, iclass 3, count 0 2006.257.23:41:59.20#ibcon#wrote, iclass 3, count 0 2006.257.23:41:59.20#ibcon#about to read 3, iclass 3, count 0 2006.257.23:41:59.22#ibcon#read 3, iclass 3, count 0 2006.257.23:41:59.22#ibcon#about to read 4, iclass 3, count 0 2006.257.23:41:59.22#ibcon#read 4, iclass 3, count 0 2006.257.23:41:59.22#ibcon#about to read 5, iclass 3, count 0 2006.257.23:41:59.22#ibcon#read 5, iclass 3, count 0 2006.257.23:41:59.22#ibcon#about to read 6, iclass 3, count 0 2006.257.23:41:59.22#ibcon#read 6, iclass 3, count 0 2006.257.23:41:59.22#ibcon#end of sib2, iclass 3, count 0 2006.257.23:41:59.22#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:41:59.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:41:59.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:41:59.22#ibcon#*before write, iclass 3, count 0 2006.257.23:41:59.22#ibcon#enter sib2, iclass 3, count 0 2006.257.23:41:59.22#ibcon#flushed, iclass 3, count 0 2006.257.23:41:59.22#ibcon#about to write, iclass 3, count 0 2006.257.23:41:59.22#ibcon#wrote, iclass 3, count 0 2006.257.23:41:59.22#ibcon#about to read 3, iclass 3, count 0 2006.257.23:41:59.26#abcon#<5=/16 1.1 2.4 20.91 801016.2\r\n> 2006.257.23:41:59.26#ibcon#read 3, iclass 3, count 0 2006.257.23:41:59.26#ibcon#about to read 4, iclass 3, count 0 2006.257.23:41:59.26#ibcon#read 4, iclass 3, count 0 2006.257.23:41:59.26#ibcon#about to read 5, iclass 3, count 0 2006.257.23:41:59.26#ibcon#read 5, iclass 3, count 0 2006.257.23:41:59.26#ibcon#about to read 6, iclass 3, count 0 2006.257.23:41:59.26#ibcon#read 6, iclass 3, count 0 2006.257.23:41:59.26#ibcon#end of sib2, iclass 3, count 0 2006.257.23:41:59.26#ibcon#*after write, iclass 3, count 0 2006.257.23:41:59.26#ibcon#*before return 0, iclass 3, count 0 2006.257.23:41:59.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:41:59.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:41:59.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:41:59.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:41:59.26$vck44/va=6,4 2006.257.23:41:59.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.23:41:59.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.23:41:59.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:41:59.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:41:59.28#abcon#{5=INTERFACE CLEAR} 2006.257.23:41:59.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:41:59.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:41:59.32#ibcon#enter wrdev, iclass 10, count 2 2006.257.23:41:59.32#ibcon#first serial, iclass 10, count 2 2006.257.23:41:59.32#ibcon#enter sib2, iclass 10, count 2 2006.257.23:41:59.32#ibcon#flushed, iclass 10, count 2 2006.257.23:41:59.32#ibcon#about to write, iclass 10, count 2 2006.257.23:41:59.32#ibcon#wrote, iclass 10, count 2 2006.257.23:41:59.32#ibcon#about to read 3, iclass 10, count 2 2006.257.23:41:59.34#ibcon#read 3, iclass 10, count 2 2006.257.23:41:59.34#ibcon#about to read 4, iclass 10, count 2 2006.257.23:41:59.34#ibcon#read 4, iclass 10, count 2 2006.257.23:41:59.34#ibcon#about to read 5, iclass 10, count 2 2006.257.23:41:59.34#ibcon#read 5, iclass 10, count 2 2006.257.23:41:59.34#ibcon#about to read 6, iclass 10, count 2 2006.257.23:41:59.34#ibcon#read 6, iclass 10, count 2 2006.257.23:41:59.34#ibcon#end of sib2, iclass 10, count 2 2006.257.23:41:59.34#ibcon#*mode == 0, iclass 10, count 2 2006.257.23:41:59.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.23:41:59.34#ibcon#[25=AT06-04\r\n] 2006.257.23:41:59.34#ibcon#*before write, iclass 10, count 2 2006.257.23:41:59.34#ibcon#enter sib2, iclass 10, count 2 2006.257.23:41:59.34#ibcon#flushed, iclass 10, count 2 2006.257.23:41:59.34#ibcon#about to write, iclass 10, count 2 2006.257.23:41:59.34#ibcon#wrote, iclass 10, count 2 2006.257.23:41:59.34#ibcon#about to read 3, iclass 10, count 2 2006.257.23:41:59.34#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:41:59.37#ibcon#read 3, iclass 10, count 2 2006.257.23:41:59.37#ibcon#about to read 4, iclass 10, count 2 2006.257.23:41:59.37#ibcon#read 4, iclass 10, count 2 2006.257.23:41:59.37#ibcon#about to read 5, iclass 10, count 2 2006.257.23:41:59.37#ibcon#read 5, iclass 10, count 2 2006.257.23:41:59.37#ibcon#about to read 6, iclass 10, count 2 2006.257.23:41:59.37#ibcon#read 6, iclass 10, count 2 2006.257.23:41:59.37#ibcon#end of sib2, iclass 10, count 2 2006.257.23:41:59.37#ibcon#*after write, iclass 10, count 2 2006.257.23:41:59.37#ibcon#*before return 0, iclass 10, count 2 2006.257.23:41:59.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:41:59.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:41:59.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.23:41:59.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:41:59.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:41:59.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:41:59.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:41:59.49#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:41:59.49#ibcon#first serial, iclass 10, count 0 2006.257.23:41:59.49#ibcon#enter sib2, iclass 10, count 0 2006.257.23:41:59.49#ibcon#flushed, iclass 10, count 0 2006.257.23:41:59.49#ibcon#about to write, iclass 10, count 0 2006.257.23:41:59.49#ibcon#wrote, iclass 10, count 0 2006.257.23:41:59.49#ibcon#about to read 3, iclass 10, count 0 2006.257.23:41:59.51#ibcon#read 3, iclass 10, count 0 2006.257.23:41:59.51#ibcon#about to read 4, iclass 10, count 0 2006.257.23:41:59.51#ibcon#read 4, iclass 10, count 0 2006.257.23:41:59.51#ibcon#about to read 5, iclass 10, count 0 2006.257.23:41:59.51#ibcon#read 5, iclass 10, count 0 2006.257.23:41:59.51#ibcon#about to read 6, iclass 10, count 0 2006.257.23:41:59.51#ibcon#read 6, iclass 10, count 0 2006.257.23:41:59.51#ibcon#end of sib2, iclass 10, count 0 2006.257.23:41:59.51#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:41:59.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:41:59.51#ibcon#[25=USB\r\n] 2006.257.23:41:59.51#ibcon#*before write, iclass 10, count 0 2006.257.23:41:59.51#ibcon#enter sib2, iclass 10, count 0 2006.257.23:41:59.51#ibcon#flushed, iclass 10, count 0 2006.257.23:41:59.51#ibcon#about to write, iclass 10, count 0 2006.257.23:41:59.51#ibcon#wrote, iclass 10, count 0 2006.257.23:41:59.51#ibcon#about to read 3, iclass 10, count 0 2006.257.23:41:59.54#ibcon#read 3, iclass 10, count 0 2006.257.23:41:59.54#ibcon#about to read 4, iclass 10, count 0 2006.257.23:41:59.54#ibcon#read 4, iclass 10, count 0 2006.257.23:41:59.54#ibcon#about to read 5, iclass 10, count 0 2006.257.23:41:59.54#ibcon#read 5, iclass 10, count 0 2006.257.23:41:59.54#ibcon#about to read 6, iclass 10, count 0 2006.257.23:41:59.54#ibcon#read 6, iclass 10, count 0 2006.257.23:41:59.54#ibcon#end of sib2, iclass 10, count 0 2006.257.23:41:59.54#ibcon#*after write, iclass 10, count 0 2006.257.23:41:59.54#ibcon#*before return 0, iclass 10, count 0 2006.257.23:41:59.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:41:59.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:41:59.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:41:59.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:41:59.54$vck44/valo=7,864.99 2006.257.23:41:59.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.23:41:59.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.23:41:59.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:41:59.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:41:59.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:41:59.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:41:59.54#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:41:59.54#ibcon#first serial, iclass 13, count 0 2006.257.23:41:59.54#ibcon#enter sib2, iclass 13, count 0 2006.257.23:41:59.54#ibcon#flushed, iclass 13, count 0 2006.257.23:41:59.54#ibcon#about to write, iclass 13, count 0 2006.257.23:41:59.54#ibcon#wrote, iclass 13, count 0 2006.257.23:41:59.54#ibcon#about to read 3, iclass 13, count 0 2006.257.23:41:59.56#ibcon#read 3, iclass 13, count 0 2006.257.23:41:59.56#ibcon#about to read 4, iclass 13, count 0 2006.257.23:41:59.56#ibcon#read 4, iclass 13, count 0 2006.257.23:41:59.56#ibcon#about to read 5, iclass 13, count 0 2006.257.23:41:59.56#ibcon#read 5, iclass 13, count 0 2006.257.23:41:59.56#ibcon#about to read 6, iclass 13, count 0 2006.257.23:41:59.56#ibcon#read 6, iclass 13, count 0 2006.257.23:41:59.56#ibcon#end of sib2, iclass 13, count 0 2006.257.23:41:59.56#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:41:59.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:41:59.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:41:59.56#ibcon#*before write, iclass 13, count 0 2006.257.23:41:59.56#ibcon#enter sib2, iclass 13, count 0 2006.257.23:41:59.56#ibcon#flushed, iclass 13, count 0 2006.257.23:41:59.56#ibcon#about to write, iclass 13, count 0 2006.257.23:41:59.56#ibcon#wrote, iclass 13, count 0 2006.257.23:41:59.56#ibcon#about to read 3, iclass 13, count 0 2006.257.23:41:59.60#ibcon#read 3, iclass 13, count 0 2006.257.23:41:59.60#ibcon#about to read 4, iclass 13, count 0 2006.257.23:41:59.60#ibcon#read 4, iclass 13, count 0 2006.257.23:41:59.60#ibcon#about to read 5, iclass 13, count 0 2006.257.23:41:59.60#ibcon#read 5, iclass 13, count 0 2006.257.23:41:59.60#ibcon#about to read 6, iclass 13, count 0 2006.257.23:41:59.60#ibcon#read 6, iclass 13, count 0 2006.257.23:41:59.60#ibcon#end of sib2, iclass 13, count 0 2006.257.23:41:59.60#ibcon#*after write, iclass 13, count 0 2006.257.23:41:59.60#ibcon#*before return 0, iclass 13, count 0 2006.257.23:41:59.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:41:59.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:41:59.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:41:59.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:41:59.60$vck44/va=7,4 2006.257.23:41:59.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.23:41:59.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.23:41:59.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:41:59.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:41:59.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:41:59.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:41:59.66#ibcon#enter wrdev, iclass 15, count 2 2006.257.23:41:59.66#ibcon#first serial, iclass 15, count 2 2006.257.23:41:59.66#ibcon#enter sib2, iclass 15, count 2 2006.257.23:41:59.66#ibcon#flushed, iclass 15, count 2 2006.257.23:41:59.66#ibcon#about to write, iclass 15, count 2 2006.257.23:41:59.66#ibcon#wrote, iclass 15, count 2 2006.257.23:41:59.66#ibcon#about to read 3, iclass 15, count 2 2006.257.23:41:59.68#ibcon#read 3, iclass 15, count 2 2006.257.23:41:59.68#ibcon#about to read 4, iclass 15, count 2 2006.257.23:41:59.68#ibcon#read 4, iclass 15, count 2 2006.257.23:41:59.68#ibcon#about to read 5, iclass 15, count 2 2006.257.23:41:59.68#ibcon#read 5, iclass 15, count 2 2006.257.23:41:59.68#ibcon#about to read 6, iclass 15, count 2 2006.257.23:41:59.68#ibcon#read 6, iclass 15, count 2 2006.257.23:41:59.68#ibcon#end of sib2, iclass 15, count 2 2006.257.23:41:59.68#ibcon#*mode == 0, iclass 15, count 2 2006.257.23:41:59.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.23:41:59.68#ibcon#[25=AT07-04\r\n] 2006.257.23:41:59.68#ibcon#*before write, iclass 15, count 2 2006.257.23:41:59.68#ibcon#enter sib2, iclass 15, count 2 2006.257.23:41:59.68#ibcon#flushed, iclass 15, count 2 2006.257.23:41:59.68#ibcon#about to write, iclass 15, count 2 2006.257.23:41:59.68#ibcon#wrote, iclass 15, count 2 2006.257.23:41:59.68#ibcon#about to read 3, iclass 15, count 2 2006.257.23:41:59.71#ibcon#read 3, iclass 15, count 2 2006.257.23:41:59.71#ibcon#about to read 4, iclass 15, count 2 2006.257.23:41:59.71#ibcon#read 4, iclass 15, count 2 2006.257.23:41:59.71#ibcon#about to read 5, iclass 15, count 2 2006.257.23:41:59.71#ibcon#read 5, iclass 15, count 2 2006.257.23:41:59.71#ibcon#about to read 6, iclass 15, count 2 2006.257.23:41:59.71#ibcon#read 6, iclass 15, count 2 2006.257.23:41:59.71#ibcon#end of sib2, iclass 15, count 2 2006.257.23:41:59.71#ibcon#*after write, iclass 15, count 2 2006.257.23:41:59.71#ibcon#*before return 0, iclass 15, count 2 2006.257.23:41:59.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:41:59.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:41:59.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.23:41:59.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:41:59.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:41:59.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:41:59.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:41:59.83#ibcon#enter wrdev, iclass 15, count 0 2006.257.23:41:59.83#ibcon#first serial, iclass 15, count 0 2006.257.23:41:59.83#ibcon#enter sib2, iclass 15, count 0 2006.257.23:41:59.83#ibcon#flushed, iclass 15, count 0 2006.257.23:41:59.83#ibcon#about to write, iclass 15, count 0 2006.257.23:41:59.83#ibcon#wrote, iclass 15, count 0 2006.257.23:41:59.83#ibcon#about to read 3, iclass 15, count 0 2006.257.23:41:59.85#ibcon#read 3, iclass 15, count 0 2006.257.23:41:59.85#ibcon#about to read 4, iclass 15, count 0 2006.257.23:41:59.85#ibcon#read 4, iclass 15, count 0 2006.257.23:41:59.85#ibcon#about to read 5, iclass 15, count 0 2006.257.23:41:59.85#ibcon#read 5, iclass 15, count 0 2006.257.23:41:59.85#ibcon#about to read 6, iclass 15, count 0 2006.257.23:41:59.85#ibcon#read 6, iclass 15, count 0 2006.257.23:41:59.85#ibcon#end of sib2, iclass 15, count 0 2006.257.23:41:59.85#ibcon#*mode == 0, iclass 15, count 0 2006.257.23:41:59.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.23:41:59.85#ibcon#[25=USB\r\n] 2006.257.23:41:59.85#ibcon#*before write, iclass 15, count 0 2006.257.23:41:59.85#ibcon#enter sib2, iclass 15, count 0 2006.257.23:41:59.85#ibcon#flushed, iclass 15, count 0 2006.257.23:41:59.85#ibcon#about to write, iclass 15, count 0 2006.257.23:41:59.85#ibcon#wrote, iclass 15, count 0 2006.257.23:41:59.85#ibcon#about to read 3, iclass 15, count 0 2006.257.23:41:59.88#ibcon#read 3, iclass 15, count 0 2006.257.23:41:59.88#ibcon#about to read 4, iclass 15, count 0 2006.257.23:41:59.88#ibcon#read 4, iclass 15, count 0 2006.257.23:41:59.88#ibcon#about to read 5, iclass 15, count 0 2006.257.23:41:59.88#ibcon#read 5, iclass 15, count 0 2006.257.23:41:59.88#ibcon#about to read 6, iclass 15, count 0 2006.257.23:41:59.88#ibcon#read 6, iclass 15, count 0 2006.257.23:41:59.88#ibcon#end of sib2, iclass 15, count 0 2006.257.23:41:59.88#ibcon#*after write, iclass 15, count 0 2006.257.23:41:59.88#ibcon#*before return 0, iclass 15, count 0 2006.257.23:41:59.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:41:59.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:41:59.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.23:41:59.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.23:41:59.88$vck44/valo=8,884.99 2006.257.23:41:59.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.23:41:59.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.23:41:59.88#ibcon#ireg 17 cls_cnt 0 2006.257.23:41:59.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:41:59.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:41:59.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:41:59.88#ibcon#enter wrdev, iclass 17, count 0 2006.257.23:41:59.88#ibcon#first serial, iclass 17, count 0 2006.257.23:41:59.88#ibcon#enter sib2, iclass 17, count 0 2006.257.23:41:59.88#ibcon#flushed, iclass 17, count 0 2006.257.23:41:59.88#ibcon#about to write, iclass 17, count 0 2006.257.23:41:59.88#ibcon#wrote, iclass 17, count 0 2006.257.23:41:59.88#ibcon#about to read 3, iclass 17, count 0 2006.257.23:41:59.90#ibcon#read 3, iclass 17, count 0 2006.257.23:41:59.90#ibcon#about to read 4, iclass 17, count 0 2006.257.23:41:59.90#ibcon#read 4, iclass 17, count 0 2006.257.23:41:59.90#ibcon#about to read 5, iclass 17, count 0 2006.257.23:41:59.90#ibcon#read 5, iclass 17, count 0 2006.257.23:41:59.90#ibcon#about to read 6, iclass 17, count 0 2006.257.23:41:59.90#ibcon#read 6, iclass 17, count 0 2006.257.23:41:59.90#ibcon#end of sib2, iclass 17, count 0 2006.257.23:41:59.90#ibcon#*mode == 0, iclass 17, count 0 2006.257.23:41:59.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.23:41:59.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:41:59.90#ibcon#*before write, iclass 17, count 0 2006.257.23:41:59.90#ibcon#enter sib2, iclass 17, count 0 2006.257.23:41:59.90#ibcon#flushed, iclass 17, count 0 2006.257.23:41:59.90#ibcon#about to write, iclass 17, count 0 2006.257.23:41:59.90#ibcon#wrote, iclass 17, count 0 2006.257.23:41:59.90#ibcon#about to read 3, iclass 17, count 0 2006.257.23:41:59.94#ibcon#read 3, iclass 17, count 0 2006.257.23:41:59.94#ibcon#about to read 4, iclass 17, count 0 2006.257.23:41:59.94#ibcon#read 4, iclass 17, count 0 2006.257.23:41:59.94#ibcon#about to read 5, iclass 17, count 0 2006.257.23:41:59.94#ibcon#read 5, iclass 17, count 0 2006.257.23:41:59.94#ibcon#about to read 6, iclass 17, count 0 2006.257.23:41:59.94#ibcon#read 6, iclass 17, count 0 2006.257.23:41:59.94#ibcon#end of sib2, iclass 17, count 0 2006.257.23:41:59.94#ibcon#*after write, iclass 17, count 0 2006.257.23:41:59.94#ibcon#*before return 0, iclass 17, count 0 2006.257.23:41:59.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:41:59.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:41:59.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.23:41:59.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.23:41:59.94$vck44/va=8,4 2006.257.23:41:59.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.257.23:41:59.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.257.23:41:59.94#ibcon#ireg 11 cls_cnt 2 2006.257.23:41:59.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:42:00.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:42:00.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:42:00.00#ibcon#enter wrdev, iclass 19, count 2 2006.257.23:42:00.00#ibcon#first serial, iclass 19, count 2 2006.257.23:42:00.00#ibcon#enter sib2, iclass 19, count 2 2006.257.23:42:00.00#ibcon#flushed, iclass 19, count 2 2006.257.23:42:00.00#ibcon#about to write, iclass 19, count 2 2006.257.23:42:00.00#ibcon#wrote, iclass 19, count 2 2006.257.23:42:00.00#ibcon#about to read 3, iclass 19, count 2 2006.257.23:42:00.02#ibcon#read 3, iclass 19, count 2 2006.257.23:42:00.02#ibcon#about to read 4, iclass 19, count 2 2006.257.23:42:00.02#ibcon#read 4, iclass 19, count 2 2006.257.23:42:00.02#ibcon#about to read 5, iclass 19, count 2 2006.257.23:42:00.02#ibcon#read 5, iclass 19, count 2 2006.257.23:42:00.02#ibcon#about to read 6, iclass 19, count 2 2006.257.23:42:00.02#ibcon#read 6, iclass 19, count 2 2006.257.23:42:00.02#ibcon#end of sib2, iclass 19, count 2 2006.257.23:42:00.02#ibcon#*mode == 0, iclass 19, count 2 2006.257.23:42:00.02#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.257.23:42:00.02#ibcon#[25=AT08-04\r\n] 2006.257.23:42:00.02#ibcon#*before write, iclass 19, count 2 2006.257.23:42:00.02#ibcon#enter sib2, iclass 19, count 2 2006.257.23:42:00.02#ibcon#flushed, iclass 19, count 2 2006.257.23:42:00.02#ibcon#about to write, iclass 19, count 2 2006.257.23:42:00.02#ibcon#wrote, iclass 19, count 2 2006.257.23:42:00.02#ibcon#about to read 3, iclass 19, count 2 2006.257.23:42:00.05#ibcon#read 3, iclass 19, count 2 2006.257.23:42:00.05#ibcon#about to read 4, iclass 19, count 2 2006.257.23:42:00.05#ibcon#read 4, iclass 19, count 2 2006.257.23:42:00.05#ibcon#about to read 5, iclass 19, count 2 2006.257.23:42:00.05#ibcon#read 5, iclass 19, count 2 2006.257.23:42:00.05#ibcon#about to read 6, iclass 19, count 2 2006.257.23:42:00.05#ibcon#read 6, iclass 19, count 2 2006.257.23:42:00.05#ibcon#end of sib2, iclass 19, count 2 2006.257.23:42:00.05#ibcon#*after write, iclass 19, count 2 2006.257.23:42:00.05#ibcon#*before return 0, iclass 19, count 2 2006.257.23:42:00.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:42:00.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.257.23:42:00.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.257.23:42:00.05#ibcon#ireg 7 cls_cnt 0 2006.257.23:42:00.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:42:00.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:42:00.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:42:00.17#ibcon#enter wrdev, iclass 19, count 0 2006.257.23:42:00.17#ibcon#first serial, iclass 19, count 0 2006.257.23:42:00.17#ibcon#enter sib2, iclass 19, count 0 2006.257.23:42:00.17#ibcon#flushed, iclass 19, count 0 2006.257.23:42:00.17#ibcon#about to write, iclass 19, count 0 2006.257.23:42:00.17#ibcon#wrote, iclass 19, count 0 2006.257.23:42:00.17#ibcon#about to read 3, iclass 19, count 0 2006.257.23:42:00.19#ibcon#read 3, iclass 19, count 0 2006.257.23:42:00.19#ibcon#about to read 4, iclass 19, count 0 2006.257.23:42:00.19#ibcon#read 4, iclass 19, count 0 2006.257.23:42:00.19#ibcon#about to read 5, iclass 19, count 0 2006.257.23:42:00.19#ibcon#read 5, iclass 19, count 0 2006.257.23:42:00.19#ibcon#about to read 6, iclass 19, count 0 2006.257.23:42:00.19#ibcon#read 6, iclass 19, count 0 2006.257.23:42:00.19#ibcon#end of sib2, iclass 19, count 0 2006.257.23:42:00.19#ibcon#*mode == 0, iclass 19, count 0 2006.257.23:42:00.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.23:42:00.19#ibcon#[25=USB\r\n] 2006.257.23:42:00.19#ibcon#*before write, iclass 19, count 0 2006.257.23:42:00.19#ibcon#enter sib2, iclass 19, count 0 2006.257.23:42:00.19#ibcon#flushed, iclass 19, count 0 2006.257.23:42:00.19#ibcon#about to write, iclass 19, count 0 2006.257.23:42:00.19#ibcon#wrote, iclass 19, count 0 2006.257.23:42:00.19#ibcon#about to read 3, iclass 19, count 0 2006.257.23:42:00.22#ibcon#read 3, iclass 19, count 0 2006.257.23:42:00.22#ibcon#about to read 4, iclass 19, count 0 2006.257.23:42:00.22#ibcon#read 4, iclass 19, count 0 2006.257.23:42:00.22#ibcon#about to read 5, iclass 19, count 0 2006.257.23:42:00.22#ibcon#read 5, iclass 19, count 0 2006.257.23:42:00.22#ibcon#about to read 6, iclass 19, count 0 2006.257.23:42:00.22#ibcon#read 6, iclass 19, count 0 2006.257.23:42:00.22#ibcon#end of sib2, iclass 19, count 0 2006.257.23:42:00.22#ibcon#*after write, iclass 19, count 0 2006.257.23:42:00.22#ibcon#*before return 0, iclass 19, count 0 2006.257.23:42:00.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:42:00.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.257.23:42:00.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.23:42:00.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.23:42:00.22$vck44/vblo=1,629.99 2006.257.23:42:00.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.257.23:42:00.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.257.23:42:00.22#ibcon#ireg 17 cls_cnt 0 2006.257.23:42:00.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:42:00.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:42:00.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:42:00.22#ibcon#enter wrdev, iclass 21, count 0 2006.257.23:42:00.22#ibcon#first serial, iclass 21, count 0 2006.257.23:42:00.22#ibcon#enter sib2, iclass 21, count 0 2006.257.23:42:00.22#ibcon#flushed, iclass 21, count 0 2006.257.23:42:00.22#ibcon#about to write, iclass 21, count 0 2006.257.23:42:00.22#ibcon#wrote, iclass 21, count 0 2006.257.23:42:00.22#ibcon#about to read 3, iclass 21, count 0 2006.257.23:42:00.24#ibcon#read 3, iclass 21, count 0 2006.257.23:42:00.24#ibcon#about to read 4, iclass 21, count 0 2006.257.23:42:00.24#ibcon#read 4, iclass 21, count 0 2006.257.23:42:00.24#ibcon#about to read 5, iclass 21, count 0 2006.257.23:42:00.24#ibcon#read 5, iclass 21, count 0 2006.257.23:42:00.24#ibcon#about to read 6, iclass 21, count 0 2006.257.23:42:00.24#ibcon#read 6, iclass 21, count 0 2006.257.23:42:00.24#ibcon#end of sib2, iclass 21, count 0 2006.257.23:42:00.24#ibcon#*mode == 0, iclass 21, count 0 2006.257.23:42:00.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.23:42:00.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:42:00.24#ibcon#*before write, iclass 21, count 0 2006.257.23:42:00.24#ibcon#enter sib2, iclass 21, count 0 2006.257.23:42:00.24#ibcon#flushed, iclass 21, count 0 2006.257.23:42:00.24#ibcon#about to write, iclass 21, count 0 2006.257.23:42:00.24#ibcon#wrote, iclass 21, count 0 2006.257.23:42:00.24#ibcon#about to read 3, iclass 21, count 0 2006.257.23:42:00.28#ibcon#read 3, iclass 21, count 0 2006.257.23:42:00.28#ibcon#about to read 4, iclass 21, count 0 2006.257.23:42:00.28#ibcon#read 4, iclass 21, count 0 2006.257.23:42:00.28#ibcon#about to read 5, iclass 21, count 0 2006.257.23:42:00.28#ibcon#read 5, iclass 21, count 0 2006.257.23:42:00.28#ibcon#about to read 6, iclass 21, count 0 2006.257.23:42:00.28#ibcon#read 6, iclass 21, count 0 2006.257.23:42:00.28#ibcon#end of sib2, iclass 21, count 0 2006.257.23:42:00.28#ibcon#*after write, iclass 21, count 0 2006.257.23:42:00.28#ibcon#*before return 0, iclass 21, count 0 2006.257.23:42:00.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:42:00.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.257.23:42:00.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.23:42:00.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.23:42:00.28$vck44/vb=1,4 2006.257.23:42:00.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.257.23:42:00.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.257.23:42:00.28#ibcon#ireg 11 cls_cnt 2 2006.257.23:42:00.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:42:00.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:42:00.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:42:00.28#ibcon#enter wrdev, iclass 23, count 2 2006.257.23:42:00.28#ibcon#first serial, iclass 23, count 2 2006.257.23:42:00.28#ibcon#enter sib2, iclass 23, count 2 2006.257.23:42:00.28#ibcon#flushed, iclass 23, count 2 2006.257.23:42:00.28#ibcon#about to write, iclass 23, count 2 2006.257.23:42:00.28#ibcon#wrote, iclass 23, count 2 2006.257.23:42:00.28#ibcon#about to read 3, iclass 23, count 2 2006.257.23:42:00.30#ibcon#read 3, iclass 23, count 2 2006.257.23:42:00.30#ibcon#about to read 4, iclass 23, count 2 2006.257.23:42:00.30#ibcon#read 4, iclass 23, count 2 2006.257.23:42:00.30#ibcon#about to read 5, iclass 23, count 2 2006.257.23:42:00.30#ibcon#read 5, iclass 23, count 2 2006.257.23:42:00.30#ibcon#about to read 6, iclass 23, count 2 2006.257.23:42:00.30#ibcon#read 6, iclass 23, count 2 2006.257.23:42:00.30#ibcon#end of sib2, iclass 23, count 2 2006.257.23:42:00.30#ibcon#*mode == 0, iclass 23, count 2 2006.257.23:42:00.30#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.257.23:42:00.30#ibcon#[27=AT01-04\r\n] 2006.257.23:42:00.30#ibcon#*before write, iclass 23, count 2 2006.257.23:42:00.30#ibcon#enter sib2, iclass 23, count 2 2006.257.23:42:00.30#ibcon#flushed, iclass 23, count 2 2006.257.23:42:00.30#ibcon#about to write, iclass 23, count 2 2006.257.23:42:00.30#ibcon#wrote, iclass 23, count 2 2006.257.23:42:00.30#ibcon#about to read 3, iclass 23, count 2 2006.257.23:42:00.33#ibcon#read 3, iclass 23, count 2 2006.257.23:42:00.33#ibcon#about to read 4, iclass 23, count 2 2006.257.23:42:00.33#ibcon#read 4, iclass 23, count 2 2006.257.23:42:00.33#ibcon#about to read 5, iclass 23, count 2 2006.257.23:42:00.33#ibcon#read 5, iclass 23, count 2 2006.257.23:42:00.33#ibcon#about to read 6, iclass 23, count 2 2006.257.23:42:00.33#ibcon#read 6, iclass 23, count 2 2006.257.23:42:00.33#ibcon#end of sib2, iclass 23, count 2 2006.257.23:42:00.33#ibcon#*after write, iclass 23, count 2 2006.257.23:42:00.33#ibcon#*before return 0, iclass 23, count 2 2006.257.23:42:00.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:42:00.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.257.23:42:00.33#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.257.23:42:00.33#ibcon#ireg 7 cls_cnt 0 2006.257.23:42:00.33#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:42:00.45#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:42:00.45#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:42:00.45#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:42:00.45#ibcon#first serial, iclass 23, count 0 2006.257.23:42:00.45#ibcon#enter sib2, iclass 23, count 0 2006.257.23:42:00.45#ibcon#flushed, iclass 23, count 0 2006.257.23:42:00.45#ibcon#about to write, iclass 23, count 0 2006.257.23:42:00.45#ibcon#wrote, iclass 23, count 0 2006.257.23:42:00.45#ibcon#about to read 3, iclass 23, count 0 2006.257.23:42:00.47#ibcon#read 3, iclass 23, count 0 2006.257.23:42:00.47#ibcon#about to read 4, iclass 23, count 0 2006.257.23:42:00.47#ibcon#read 4, iclass 23, count 0 2006.257.23:42:00.47#ibcon#about to read 5, iclass 23, count 0 2006.257.23:42:00.47#ibcon#read 5, iclass 23, count 0 2006.257.23:42:00.47#ibcon#about to read 6, iclass 23, count 0 2006.257.23:42:00.47#ibcon#read 6, iclass 23, count 0 2006.257.23:42:00.47#ibcon#end of sib2, iclass 23, count 0 2006.257.23:42:00.47#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:42:00.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:42:00.47#ibcon#[27=USB\r\n] 2006.257.23:42:00.47#ibcon#*before write, iclass 23, count 0 2006.257.23:42:00.47#ibcon#enter sib2, iclass 23, count 0 2006.257.23:42:00.47#ibcon#flushed, iclass 23, count 0 2006.257.23:42:00.47#ibcon#about to write, iclass 23, count 0 2006.257.23:42:00.47#ibcon#wrote, iclass 23, count 0 2006.257.23:42:00.47#ibcon#about to read 3, iclass 23, count 0 2006.257.23:42:00.50#ibcon#read 3, iclass 23, count 0 2006.257.23:42:00.50#ibcon#about to read 4, iclass 23, count 0 2006.257.23:42:00.50#ibcon#read 4, iclass 23, count 0 2006.257.23:42:00.50#ibcon#about to read 5, iclass 23, count 0 2006.257.23:42:00.50#ibcon#read 5, iclass 23, count 0 2006.257.23:42:00.50#ibcon#about to read 6, iclass 23, count 0 2006.257.23:42:00.50#ibcon#read 6, iclass 23, count 0 2006.257.23:42:00.50#ibcon#end of sib2, iclass 23, count 0 2006.257.23:42:00.50#ibcon#*after write, iclass 23, count 0 2006.257.23:42:00.50#ibcon#*before return 0, iclass 23, count 0 2006.257.23:42:00.50#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:42:00.50#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.257.23:42:00.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:42:00.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:42:00.50$vck44/vblo=2,634.99 2006.257.23:42:00.50#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.23:42:00.50#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.23:42:00.50#ibcon#ireg 17 cls_cnt 0 2006.257.23:42:00.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:42:00.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:42:00.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:42:00.50#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:42:00.50#ibcon#first serial, iclass 25, count 0 2006.257.23:42:00.50#ibcon#enter sib2, iclass 25, count 0 2006.257.23:42:00.50#ibcon#flushed, iclass 25, count 0 2006.257.23:42:00.50#ibcon#about to write, iclass 25, count 0 2006.257.23:42:00.50#ibcon#wrote, iclass 25, count 0 2006.257.23:42:00.50#ibcon#about to read 3, iclass 25, count 0 2006.257.23:42:00.52#ibcon#read 3, iclass 25, count 0 2006.257.23:42:00.52#ibcon#about to read 4, iclass 25, count 0 2006.257.23:42:00.52#ibcon#read 4, iclass 25, count 0 2006.257.23:42:00.52#ibcon#about to read 5, iclass 25, count 0 2006.257.23:42:00.52#ibcon#read 5, iclass 25, count 0 2006.257.23:42:00.52#ibcon#about to read 6, iclass 25, count 0 2006.257.23:42:00.52#ibcon#read 6, iclass 25, count 0 2006.257.23:42:00.52#ibcon#end of sib2, iclass 25, count 0 2006.257.23:42:00.52#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:42:00.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:42:00.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:42:00.52#ibcon#*before write, iclass 25, count 0 2006.257.23:42:00.52#ibcon#enter sib2, iclass 25, count 0 2006.257.23:42:00.52#ibcon#flushed, iclass 25, count 0 2006.257.23:42:00.52#ibcon#about to write, iclass 25, count 0 2006.257.23:42:00.52#ibcon#wrote, iclass 25, count 0 2006.257.23:42:00.52#ibcon#about to read 3, iclass 25, count 0 2006.257.23:42:00.56#ibcon#read 3, iclass 25, count 0 2006.257.23:42:00.56#ibcon#about to read 4, iclass 25, count 0 2006.257.23:42:00.56#ibcon#read 4, iclass 25, count 0 2006.257.23:42:00.56#ibcon#about to read 5, iclass 25, count 0 2006.257.23:42:00.56#ibcon#read 5, iclass 25, count 0 2006.257.23:42:00.56#ibcon#about to read 6, iclass 25, count 0 2006.257.23:42:00.56#ibcon#read 6, iclass 25, count 0 2006.257.23:42:00.56#ibcon#end of sib2, iclass 25, count 0 2006.257.23:42:00.56#ibcon#*after write, iclass 25, count 0 2006.257.23:42:00.56#ibcon#*before return 0, iclass 25, count 0 2006.257.23:42:00.56#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:42:00.56#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:42:00.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:42:00.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:42:00.56$vck44/vb=2,5 2006.257.23:42:00.56#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.257.23:42:00.56#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.257.23:42:00.56#ibcon#ireg 11 cls_cnt 2 2006.257.23:42:00.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:42:00.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:42:00.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:42:00.62#ibcon#enter wrdev, iclass 27, count 2 2006.257.23:42:00.62#ibcon#first serial, iclass 27, count 2 2006.257.23:42:00.62#ibcon#enter sib2, iclass 27, count 2 2006.257.23:42:00.62#ibcon#flushed, iclass 27, count 2 2006.257.23:42:00.62#ibcon#about to write, iclass 27, count 2 2006.257.23:42:00.62#ibcon#wrote, iclass 27, count 2 2006.257.23:42:00.62#ibcon#about to read 3, iclass 27, count 2 2006.257.23:42:00.64#ibcon#read 3, iclass 27, count 2 2006.257.23:42:00.64#ibcon#about to read 4, iclass 27, count 2 2006.257.23:42:00.64#ibcon#read 4, iclass 27, count 2 2006.257.23:42:00.64#ibcon#about to read 5, iclass 27, count 2 2006.257.23:42:00.64#ibcon#read 5, iclass 27, count 2 2006.257.23:42:00.64#ibcon#about to read 6, iclass 27, count 2 2006.257.23:42:00.64#ibcon#read 6, iclass 27, count 2 2006.257.23:42:00.64#ibcon#end of sib2, iclass 27, count 2 2006.257.23:42:00.64#ibcon#*mode == 0, iclass 27, count 2 2006.257.23:42:00.64#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.257.23:42:00.64#ibcon#[27=AT02-05\r\n] 2006.257.23:42:00.64#ibcon#*before write, iclass 27, count 2 2006.257.23:42:00.64#ibcon#enter sib2, iclass 27, count 2 2006.257.23:42:00.64#ibcon#flushed, iclass 27, count 2 2006.257.23:42:00.64#ibcon#about to write, iclass 27, count 2 2006.257.23:42:00.64#ibcon#wrote, iclass 27, count 2 2006.257.23:42:00.64#ibcon#about to read 3, iclass 27, count 2 2006.257.23:42:00.67#ibcon#read 3, iclass 27, count 2 2006.257.23:42:00.67#ibcon#about to read 4, iclass 27, count 2 2006.257.23:42:00.67#ibcon#read 4, iclass 27, count 2 2006.257.23:42:00.67#ibcon#about to read 5, iclass 27, count 2 2006.257.23:42:00.67#ibcon#read 5, iclass 27, count 2 2006.257.23:42:00.67#ibcon#about to read 6, iclass 27, count 2 2006.257.23:42:00.67#ibcon#read 6, iclass 27, count 2 2006.257.23:42:00.67#ibcon#end of sib2, iclass 27, count 2 2006.257.23:42:00.67#ibcon#*after write, iclass 27, count 2 2006.257.23:42:00.67#ibcon#*before return 0, iclass 27, count 2 2006.257.23:42:00.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:42:00.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.257.23:42:00.67#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.257.23:42:00.67#ibcon#ireg 7 cls_cnt 0 2006.257.23:42:00.67#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:42:00.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:42:00.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:42:00.79#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:42:00.79#ibcon#first serial, iclass 27, count 0 2006.257.23:42:00.79#ibcon#enter sib2, iclass 27, count 0 2006.257.23:42:00.79#ibcon#flushed, iclass 27, count 0 2006.257.23:42:00.79#ibcon#about to write, iclass 27, count 0 2006.257.23:42:00.79#ibcon#wrote, iclass 27, count 0 2006.257.23:42:00.79#ibcon#about to read 3, iclass 27, count 0 2006.257.23:42:00.81#ibcon#read 3, iclass 27, count 0 2006.257.23:42:00.81#ibcon#about to read 4, iclass 27, count 0 2006.257.23:42:00.81#ibcon#read 4, iclass 27, count 0 2006.257.23:42:00.81#ibcon#about to read 5, iclass 27, count 0 2006.257.23:42:00.81#ibcon#read 5, iclass 27, count 0 2006.257.23:42:00.81#ibcon#about to read 6, iclass 27, count 0 2006.257.23:42:00.81#ibcon#read 6, iclass 27, count 0 2006.257.23:42:00.81#ibcon#end of sib2, iclass 27, count 0 2006.257.23:42:00.81#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:42:00.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:42:00.81#ibcon#[27=USB\r\n] 2006.257.23:42:00.81#ibcon#*before write, iclass 27, count 0 2006.257.23:42:00.81#ibcon#enter sib2, iclass 27, count 0 2006.257.23:42:00.81#ibcon#flushed, iclass 27, count 0 2006.257.23:42:00.81#ibcon#about to write, iclass 27, count 0 2006.257.23:42:00.81#ibcon#wrote, iclass 27, count 0 2006.257.23:42:00.81#ibcon#about to read 3, iclass 27, count 0 2006.257.23:42:00.84#ibcon#read 3, iclass 27, count 0 2006.257.23:42:00.84#ibcon#about to read 4, iclass 27, count 0 2006.257.23:42:00.84#ibcon#read 4, iclass 27, count 0 2006.257.23:42:00.84#ibcon#about to read 5, iclass 27, count 0 2006.257.23:42:00.84#ibcon#read 5, iclass 27, count 0 2006.257.23:42:00.84#ibcon#about to read 6, iclass 27, count 0 2006.257.23:42:00.84#ibcon#read 6, iclass 27, count 0 2006.257.23:42:00.84#ibcon#end of sib2, iclass 27, count 0 2006.257.23:42:00.84#ibcon#*after write, iclass 27, count 0 2006.257.23:42:00.84#ibcon#*before return 0, iclass 27, count 0 2006.257.23:42:00.84#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:42:00.84#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.257.23:42:00.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:42:00.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:42:00.84$vck44/vblo=3,649.99 2006.257.23:42:00.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.257.23:42:00.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.257.23:42:00.84#ibcon#ireg 17 cls_cnt 0 2006.257.23:42:00.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:42:00.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:42:00.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:42:00.84#ibcon#enter wrdev, iclass 29, count 0 2006.257.23:42:00.84#ibcon#first serial, iclass 29, count 0 2006.257.23:42:00.84#ibcon#enter sib2, iclass 29, count 0 2006.257.23:42:00.84#ibcon#flushed, iclass 29, count 0 2006.257.23:42:00.84#ibcon#about to write, iclass 29, count 0 2006.257.23:42:00.84#ibcon#wrote, iclass 29, count 0 2006.257.23:42:00.84#ibcon#about to read 3, iclass 29, count 0 2006.257.23:42:00.86#ibcon#read 3, iclass 29, count 0 2006.257.23:42:00.86#ibcon#about to read 4, iclass 29, count 0 2006.257.23:42:00.86#ibcon#read 4, iclass 29, count 0 2006.257.23:42:00.86#ibcon#about to read 5, iclass 29, count 0 2006.257.23:42:00.86#ibcon#read 5, iclass 29, count 0 2006.257.23:42:00.86#ibcon#about to read 6, iclass 29, count 0 2006.257.23:42:00.86#ibcon#read 6, iclass 29, count 0 2006.257.23:42:00.86#ibcon#end of sib2, iclass 29, count 0 2006.257.23:42:00.86#ibcon#*mode == 0, iclass 29, count 0 2006.257.23:42:00.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.23:42:00.86#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:42:00.86#ibcon#*before write, iclass 29, count 0 2006.257.23:42:00.86#ibcon#enter sib2, iclass 29, count 0 2006.257.23:42:00.86#ibcon#flushed, iclass 29, count 0 2006.257.23:42:00.86#ibcon#about to write, iclass 29, count 0 2006.257.23:42:00.86#ibcon#wrote, iclass 29, count 0 2006.257.23:42:00.86#ibcon#about to read 3, iclass 29, count 0 2006.257.23:42:00.90#ibcon#read 3, iclass 29, count 0 2006.257.23:42:00.90#ibcon#about to read 4, iclass 29, count 0 2006.257.23:42:00.90#ibcon#read 4, iclass 29, count 0 2006.257.23:42:00.90#ibcon#about to read 5, iclass 29, count 0 2006.257.23:42:00.90#ibcon#read 5, iclass 29, count 0 2006.257.23:42:00.90#ibcon#about to read 6, iclass 29, count 0 2006.257.23:42:00.90#ibcon#read 6, iclass 29, count 0 2006.257.23:42:00.90#ibcon#end of sib2, iclass 29, count 0 2006.257.23:42:00.90#ibcon#*after write, iclass 29, count 0 2006.257.23:42:00.90#ibcon#*before return 0, iclass 29, count 0 2006.257.23:42:00.90#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:42:00.90#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.257.23:42:00.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.23:42:00.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.23:42:00.90$vck44/vb=3,4 2006.257.23:42:00.90#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.257.23:42:00.90#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.257.23:42:00.90#ibcon#ireg 11 cls_cnt 2 2006.257.23:42:00.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:42:00.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:42:00.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:42:00.96#ibcon#enter wrdev, iclass 31, count 2 2006.257.23:42:00.96#ibcon#first serial, iclass 31, count 2 2006.257.23:42:00.96#ibcon#enter sib2, iclass 31, count 2 2006.257.23:42:00.96#ibcon#flushed, iclass 31, count 2 2006.257.23:42:00.96#ibcon#about to write, iclass 31, count 2 2006.257.23:42:00.96#ibcon#wrote, iclass 31, count 2 2006.257.23:42:00.96#ibcon#about to read 3, iclass 31, count 2 2006.257.23:42:00.98#ibcon#read 3, iclass 31, count 2 2006.257.23:42:00.98#ibcon#about to read 4, iclass 31, count 2 2006.257.23:42:00.98#ibcon#read 4, iclass 31, count 2 2006.257.23:42:00.98#ibcon#about to read 5, iclass 31, count 2 2006.257.23:42:00.98#ibcon#read 5, iclass 31, count 2 2006.257.23:42:00.98#ibcon#about to read 6, iclass 31, count 2 2006.257.23:42:00.98#ibcon#read 6, iclass 31, count 2 2006.257.23:42:00.98#ibcon#end of sib2, iclass 31, count 2 2006.257.23:42:00.98#ibcon#*mode == 0, iclass 31, count 2 2006.257.23:42:00.98#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.257.23:42:00.98#ibcon#[27=AT03-04\r\n] 2006.257.23:42:00.98#ibcon#*before write, iclass 31, count 2 2006.257.23:42:00.98#ibcon#enter sib2, iclass 31, count 2 2006.257.23:42:00.98#ibcon#flushed, iclass 31, count 2 2006.257.23:42:00.98#ibcon#about to write, iclass 31, count 2 2006.257.23:42:00.98#ibcon#wrote, iclass 31, count 2 2006.257.23:42:00.98#ibcon#about to read 3, iclass 31, count 2 2006.257.23:42:01.01#ibcon#read 3, iclass 31, count 2 2006.257.23:42:01.01#ibcon#about to read 4, iclass 31, count 2 2006.257.23:42:01.01#ibcon#read 4, iclass 31, count 2 2006.257.23:42:01.01#ibcon#about to read 5, iclass 31, count 2 2006.257.23:42:01.01#ibcon#read 5, iclass 31, count 2 2006.257.23:42:01.01#ibcon#about to read 6, iclass 31, count 2 2006.257.23:42:01.01#ibcon#read 6, iclass 31, count 2 2006.257.23:42:01.01#ibcon#end of sib2, iclass 31, count 2 2006.257.23:42:01.01#ibcon#*after write, iclass 31, count 2 2006.257.23:42:01.01#ibcon#*before return 0, iclass 31, count 2 2006.257.23:42:01.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:42:01.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.257.23:42:01.01#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.257.23:42:01.01#ibcon#ireg 7 cls_cnt 0 2006.257.23:42:01.01#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:42:01.13#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:42:01.13#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:42:01.13#ibcon#enter wrdev, iclass 31, count 0 2006.257.23:42:01.13#ibcon#first serial, iclass 31, count 0 2006.257.23:42:01.13#ibcon#enter sib2, iclass 31, count 0 2006.257.23:42:01.13#ibcon#flushed, iclass 31, count 0 2006.257.23:42:01.13#ibcon#about to write, iclass 31, count 0 2006.257.23:42:01.13#ibcon#wrote, iclass 31, count 0 2006.257.23:42:01.13#ibcon#about to read 3, iclass 31, count 0 2006.257.23:42:01.15#ibcon#read 3, iclass 31, count 0 2006.257.23:42:01.15#ibcon#about to read 4, iclass 31, count 0 2006.257.23:42:01.15#ibcon#read 4, iclass 31, count 0 2006.257.23:42:01.15#ibcon#about to read 5, iclass 31, count 0 2006.257.23:42:01.15#ibcon#read 5, iclass 31, count 0 2006.257.23:42:01.15#ibcon#about to read 6, iclass 31, count 0 2006.257.23:42:01.15#ibcon#read 6, iclass 31, count 0 2006.257.23:42:01.15#ibcon#end of sib2, iclass 31, count 0 2006.257.23:42:01.15#ibcon#*mode == 0, iclass 31, count 0 2006.257.23:42:01.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.23:42:01.15#ibcon#[27=USB\r\n] 2006.257.23:42:01.15#ibcon#*before write, iclass 31, count 0 2006.257.23:42:01.15#ibcon#enter sib2, iclass 31, count 0 2006.257.23:42:01.15#ibcon#flushed, iclass 31, count 0 2006.257.23:42:01.15#ibcon#about to write, iclass 31, count 0 2006.257.23:42:01.15#ibcon#wrote, iclass 31, count 0 2006.257.23:42:01.15#ibcon#about to read 3, iclass 31, count 0 2006.257.23:42:01.18#ibcon#read 3, iclass 31, count 0 2006.257.23:42:01.18#ibcon#about to read 4, iclass 31, count 0 2006.257.23:42:01.18#ibcon#read 4, iclass 31, count 0 2006.257.23:42:01.18#ibcon#about to read 5, iclass 31, count 0 2006.257.23:42:01.18#ibcon#read 5, iclass 31, count 0 2006.257.23:42:01.18#ibcon#about to read 6, iclass 31, count 0 2006.257.23:42:01.18#ibcon#read 6, iclass 31, count 0 2006.257.23:42:01.18#ibcon#end of sib2, iclass 31, count 0 2006.257.23:42:01.18#ibcon#*after write, iclass 31, count 0 2006.257.23:42:01.18#ibcon#*before return 0, iclass 31, count 0 2006.257.23:42:01.18#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:42:01.18#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.257.23:42:01.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.23:42:01.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.23:42:01.18$vck44/vblo=4,679.99 2006.257.23:42:01.18#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.257.23:42:01.18#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.257.23:42:01.18#ibcon#ireg 17 cls_cnt 0 2006.257.23:42:01.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:42:01.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:42:01.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:42:01.18#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:42:01.18#ibcon#first serial, iclass 33, count 0 2006.257.23:42:01.18#ibcon#enter sib2, iclass 33, count 0 2006.257.23:42:01.18#ibcon#flushed, iclass 33, count 0 2006.257.23:42:01.18#ibcon#about to write, iclass 33, count 0 2006.257.23:42:01.18#ibcon#wrote, iclass 33, count 0 2006.257.23:42:01.18#ibcon#about to read 3, iclass 33, count 0 2006.257.23:42:01.20#ibcon#read 3, iclass 33, count 0 2006.257.23:42:01.20#ibcon#about to read 4, iclass 33, count 0 2006.257.23:42:01.20#ibcon#read 4, iclass 33, count 0 2006.257.23:42:01.20#ibcon#about to read 5, iclass 33, count 0 2006.257.23:42:01.20#ibcon#read 5, iclass 33, count 0 2006.257.23:42:01.20#ibcon#about to read 6, iclass 33, count 0 2006.257.23:42:01.20#ibcon#read 6, iclass 33, count 0 2006.257.23:42:01.20#ibcon#end of sib2, iclass 33, count 0 2006.257.23:42:01.20#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:42:01.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:42:01.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:42:01.20#ibcon#*before write, iclass 33, count 0 2006.257.23:42:01.20#ibcon#enter sib2, iclass 33, count 0 2006.257.23:42:01.20#ibcon#flushed, iclass 33, count 0 2006.257.23:42:01.20#ibcon#about to write, iclass 33, count 0 2006.257.23:42:01.20#ibcon#wrote, iclass 33, count 0 2006.257.23:42:01.20#ibcon#about to read 3, iclass 33, count 0 2006.257.23:42:01.24#ibcon#read 3, iclass 33, count 0 2006.257.23:42:01.24#ibcon#about to read 4, iclass 33, count 0 2006.257.23:42:01.24#ibcon#read 4, iclass 33, count 0 2006.257.23:42:01.24#ibcon#about to read 5, iclass 33, count 0 2006.257.23:42:01.24#ibcon#read 5, iclass 33, count 0 2006.257.23:42:01.24#ibcon#about to read 6, iclass 33, count 0 2006.257.23:42:01.24#ibcon#read 6, iclass 33, count 0 2006.257.23:42:01.24#ibcon#end of sib2, iclass 33, count 0 2006.257.23:42:01.24#ibcon#*after write, iclass 33, count 0 2006.257.23:42:01.24#ibcon#*before return 0, iclass 33, count 0 2006.257.23:42:01.24#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:42:01.24#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.257.23:42:01.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:42:01.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:42:01.24$vck44/vb=4,5 2006.257.23:42:01.24#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.257.23:42:01.24#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.257.23:42:01.24#ibcon#ireg 11 cls_cnt 2 2006.257.23:42:01.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:42:01.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:42:01.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:42:01.30#ibcon#enter wrdev, iclass 35, count 2 2006.257.23:42:01.30#ibcon#first serial, iclass 35, count 2 2006.257.23:42:01.30#ibcon#enter sib2, iclass 35, count 2 2006.257.23:42:01.30#ibcon#flushed, iclass 35, count 2 2006.257.23:42:01.30#ibcon#about to write, iclass 35, count 2 2006.257.23:42:01.30#ibcon#wrote, iclass 35, count 2 2006.257.23:42:01.30#ibcon#about to read 3, iclass 35, count 2 2006.257.23:42:01.32#ibcon#read 3, iclass 35, count 2 2006.257.23:42:01.32#ibcon#about to read 4, iclass 35, count 2 2006.257.23:42:01.32#ibcon#read 4, iclass 35, count 2 2006.257.23:42:01.32#ibcon#about to read 5, iclass 35, count 2 2006.257.23:42:01.32#ibcon#read 5, iclass 35, count 2 2006.257.23:42:01.32#ibcon#about to read 6, iclass 35, count 2 2006.257.23:42:01.32#ibcon#read 6, iclass 35, count 2 2006.257.23:42:01.32#ibcon#end of sib2, iclass 35, count 2 2006.257.23:42:01.32#ibcon#*mode == 0, iclass 35, count 2 2006.257.23:42:01.32#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.257.23:42:01.32#ibcon#[27=AT04-05\r\n] 2006.257.23:42:01.32#ibcon#*before write, iclass 35, count 2 2006.257.23:42:01.32#ibcon#enter sib2, iclass 35, count 2 2006.257.23:42:01.32#ibcon#flushed, iclass 35, count 2 2006.257.23:42:01.32#ibcon#about to write, iclass 35, count 2 2006.257.23:42:01.32#ibcon#wrote, iclass 35, count 2 2006.257.23:42:01.32#ibcon#about to read 3, iclass 35, count 2 2006.257.23:42:01.35#ibcon#read 3, iclass 35, count 2 2006.257.23:42:01.35#ibcon#about to read 4, iclass 35, count 2 2006.257.23:42:01.35#ibcon#read 4, iclass 35, count 2 2006.257.23:42:01.35#ibcon#about to read 5, iclass 35, count 2 2006.257.23:42:01.35#ibcon#read 5, iclass 35, count 2 2006.257.23:42:01.35#ibcon#about to read 6, iclass 35, count 2 2006.257.23:42:01.35#ibcon#read 6, iclass 35, count 2 2006.257.23:42:01.35#ibcon#end of sib2, iclass 35, count 2 2006.257.23:42:01.35#ibcon#*after write, iclass 35, count 2 2006.257.23:42:01.35#ibcon#*before return 0, iclass 35, count 2 2006.257.23:42:01.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:42:01.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.257.23:42:01.35#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.257.23:42:01.35#ibcon#ireg 7 cls_cnt 0 2006.257.23:42:01.35#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:42:01.47#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:42:01.47#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:42:01.47#ibcon#enter wrdev, iclass 35, count 0 2006.257.23:42:01.47#ibcon#first serial, iclass 35, count 0 2006.257.23:42:01.47#ibcon#enter sib2, iclass 35, count 0 2006.257.23:42:01.47#ibcon#flushed, iclass 35, count 0 2006.257.23:42:01.47#ibcon#about to write, iclass 35, count 0 2006.257.23:42:01.47#ibcon#wrote, iclass 35, count 0 2006.257.23:42:01.47#ibcon#about to read 3, iclass 35, count 0 2006.257.23:42:01.49#ibcon#read 3, iclass 35, count 0 2006.257.23:42:01.49#ibcon#about to read 4, iclass 35, count 0 2006.257.23:42:01.49#ibcon#read 4, iclass 35, count 0 2006.257.23:42:01.49#ibcon#about to read 5, iclass 35, count 0 2006.257.23:42:01.49#ibcon#read 5, iclass 35, count 0 2006.257.23:42:01.49#ibcon#about to read 6, iclass 35, count 0 2006.257.23:42:01.49#ibcon#read 6, iclass 35, count 0 2006.257.23:42:01.49#ibcon#end of sib2, iclass 35, count 0 2006.257.23:42:01.49#ibcon#*mode == 0, iclass 35, count 0 2006.257.23:42:01.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.23:42:01.49#ibcon#[27=USB\r\n] 2006.257.23:42:01.49#ibcon#*before write, iclass 35, count 0 2006.257.23:42:01.49#ibcon#enter sib2, iclass 35, count 0 2006.257.23:42:01.49#ibcon#flushed, iclass 35, count 0 2006.257.23:42:01.49#ibcon#about to write, iclass 35, count 0 2006.257.23:42:01.49#ibcon#wrote, iclass 35, count 0 2006.257.23:42:01.49#ibcon#about to read 3, iclass 35, count 0 2006.257.23:42:01.52#ibcon#read 3, iclass 35, count 0 2006.257.23:42:01.52#ibcon#about to read 4, iclass 35, count 0 2006.257.23:42:01.52#ibcon#read 4, iclass 35, count 0 2006.257.23:42:01.52#ibcon#about to read 5, iclass 35, count 0 2006.257.23:42:01.52#ibcon#read 5, iclass 35, count 0 2006.257.23:42:01.52#ibcon#about to read 6, iclass 35, count 0 2006.257.23:42:01.52#ibcon#read 6, iclass 35, count 0 2006.257.23:42:01.52#ibcon#end of sib2, iclass 35, count 0 2006.257.23:42:01.52#ibcon#*after write, iclass 35, count 0 2006.257.23:42:01.52#ibcon#*before return 0, iclass 35, count 0 2006.257.23:42:01.52#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:42:01.52#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.257.23:42:01.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.23:42:01.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.23:42:01.52$vck44/vblo=5,709.99 2006.257.23:42:01.52#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.257.23:42:01.52#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.257.23:42:01.52#ibcon#ireg 17 cls_cnt 0 2006.257.23:42:01.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:42:01.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:42:01.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:42:01.52#ibcon#enter wrdev, iclass 37, count 0 2006.257.23:42:01.52#ibcon#first serial, iclass 37, count 0 2006.257.23:42:01.52#ibcon#enter sib2, iclass 37, count 0 2006.257.23:42:01.52#ibcon#flushed, iclass 37, count 0 2006.257.23:42:01.52#ibcon#about to write, iclass 37, count 0 2006.257.23:42:01.52#ibcon#wrote, iclass 37, count 0 2006.257.23:42:01.52#ibcon#about to read 3, iclass 37, count 0 2006.257.23:42:01.54#ibcon#read 3, iclass 37, count 0 2006.257.23:42:01.54#ibcon#about to read 4, iclass 37, count 0 2006.257.23:42:01.54#ibcon#read 4, iclass 37, count 0 2006.257.23:42:01.54#ibcon#about to read 5, iclass 37, count 0 2006.257.23:42:01.54#ibcon#read 5, iclass 37, count 0 2006.257.23:42:01.54#ibcon#about to read 6, iclass 37, count 0 2006.257.23:42:01.54#ibcon#read 6, iclass 37, count 0 2006.257.23:42:01.54#ibcon#end of sib2, iclass 37, count 0 2006.257.23:42:01.54#ibcon#*mode == 0, iclass 37, count 0 2006.257.23:42:01.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.23:42:01.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:42:01.54#ibcon#*before write, iclass 37, count 0 2006.257.23:42:01.54#ibcon#enter sib2, iclass 37, count 0 2006.257.23:42:01.54#ibcon#flushed, iclass 37, count 0 2006.257.23:42:01.54#ibcon#about to write, iclass 37, count 0 2006.257.23:42:01.54#ibcon#wrote, iclass 37, count 0 2006.257.23:42:01.54#ibcon#about to read 3, iclass 37, count 0 2006.257.23:42:01.58#ibcon#read 3, iclass 37, count 0 2006.257.23:42:01.58#ibcon#about to read 4, iclass 37, count 0 2006.257.23:42:01.58#ibcon#read 4, iclass 37, count 0 2006.257.23:42:01.58#ibcon#about to read 5, iclass 37, count 0 2006.257.23:42:01.58#ibcon#read 5, iclass 37, count 0 2006.257.23:42:01.58#ibcon#about to read 6, iclass 37, count 0 2006.257.23:42:01.58#ibcon#read 6, iclass 37, count 0 2006.257.23:42:01.58#ibcon#end of sib2, iclass 37, count 0 2006.257.23:42:01.58#ibcon#*after write, iclass 37, count 0 2006.257.23:42:01.58#ibcon#*before return 0, iclass 37, count 0 2006.257.23:42:01.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:42:01.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.257.23:42:01.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.23:42:01.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.23:42:01.58$vck44/vb=5,4 2006.257.23:42:01.58#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.257.23:42:01.58#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.257.23:42:01.58#ibcon#ireg 11 cls_cnt 2 2006.257.23:42:01.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:42:01.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:42:01.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:42:01.64#ibcon#enter wrdev, iclass 39, count 2 2006.257.23:42:01.64#ibcon#first serial, iclass 39, count 2 2006.257.23:42:01.64#ibcon#enter sib2, iclass 39, count 2 2006.257.23:42:01.64#ibcon#flushed, iclass 39, count 2 2006.257.23:42:01.64#ibcon#about to write, iclass 39, count 2 2006.257.23:42:01.64#ibcon#wrote, iclass 39, count 2 2006.257.23:42:01.64#ibcon#about to read 3, iclass 39, count 2 2006.257.23:42:01.66#ibcon#read 3, iclass 39, count 2 2006.257.23:42:01.66#ibcon#about to read 4, iclass 39, count 2 2006.257.23:42:01.66#ibcon#read 4, iclass 39, count 2 2006.257.23:42:01.66#ibcon#about to read 5, iclass 39, count 2 2006.257.23:42:01.66#ibcon#read 5, iclass 39, count 2 2006.257.23:42:01.66#ibcon#about to read 6, iclass 39, count 2 2006.257.23:42:01.66#ibcon#read 6, iclass 39, count 2 2006.257.23:42:01.66#ibcon#end of sib2, iclass 39, count 2 2006.257.23:42:01.66#ibcon#*mode == 0, iclass 39, count 2 2006.257.23:42:01.66#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.257.23:42:01.66#ibcon#[27=AT05-04\r\n] 2006.257.23:42:01.66#ibcon#*before write, iclass 39, count 2 2006.257.23:42:01.66#ibcon#enter sib2, iclass 39, count 2 2006.257.23:42:01.66#ibcon#flushed, iclass 39, count 2 2006.257.23:42:01.66#ibcon#about to write, iclass 39, count 2 2006.257.23:42:01.66#ibcon#wrote, iclass 39, count 2 2006.257.23:42:01.66#ibcon#about to read 3, iclass 39, count 2 2006.257.23:42:01.69#ibcon#read 3, iclass 39, count 2 2006.257.23:42:01.69#ibcon#about to read 4, iclass 39, count 2 2006.257.23:42:01.69#ibcon#read 4, iclass 39, count 2 2006.257.23:42:01.69#ibcon#about to read 5, iclass 39, count 2 2006.257.23:42:01.69#ibcon#read 5, iclass 39, count 2 2006.257.23:42:01.69#ibcon#about to read 6, iclass 39, count 2 2006.257.23:42:01.69#ibcon#read 6, iclass 39, count 2 2006.257.23:42:01.69#ibcon#end of sib2, iclass 39, count 2 2006.257.23:42:01.69#ibcon#*after write, iclass 39, count 2 2006.257.23:42:01.69#ibcon#*before return 0, iclass 39, count 2 2006.257.23:42:01.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:42:01.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.257.23:42:01.69#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.257.23:42:01.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:42:01.69#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:42:01.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:42:01.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:42:01.81#ibcon#enter wrdev, iclass 39, count 0 2006.257.23:42:01.81#ibcon#first serial, iclass 39, count 0 2006.257.23:42:01.81#ibcon#enter sib2, iclass 39, count 0 2006.257.23:42:01.81#ibcon#flushed, iclass 39, count 0 2006.257.23:42:01.81#ibcon#about to write, iclass 39, count 0 2006.257.23:42:01.81#ibcon#wrote, iclass 39, count 0 2006.257.23:42:01.81#ibcon#about to read 3, iclass 39, count 0 2006.257.23:42:01.83#ibcon#read 3, iclass 39, count 0 2006.257.23:42:01.83#ibcon#about to read 4, iclass 39, count 0 2006.257.23:42:01.83#ibcon#read 4, iclass 39, count 0 2006.257.23:42:01.83#ibcon#about to read 5, iclass 39, count 0 2006.257.23:42:01.83#ibcon#read 5, iclass 39, count 0 2006.257.23:42:01.83#ibcon#about to read 6, iclass 39, count 0 2006.257.23:42:01.83#ibcon#read 6, iclass 39, count 0 2006.257.23:42:01.83#ibcon#end of sib2, iclass 39, count 0 2006.257.23:42:01.83#ibcon#*mode == 0, iclass 39, count 0 2006.257.23:42:01.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.23:42:01.83#ibcon#[27=USB\r\n] 2006.257.23:42:01.83#ibcon#*before write, iclass 39, count 0 2006.257.23:42:01.83#ibcon#enter sib2, iclass 39, count 0 2006.257.23:42:01.83#ibcon#flushed, iclass 39, count 0 2006.257.23:42:01.83#ibcon#about to write, iclass 39, count 0 2006.257.23:42:01.83#ibcon#wrote, iclass 39, count 0 2006.257.23:42:01.83#ibcon#about to read 3, iclass 39, count 0 2006.257.23:42:01.86#ibcon#read 3, iclass 39, count 0 2006.257.23:42:01.86#ibcon#about to read 4, iclass 39, count 0 2006.257.23:42:01.86#ibcon#read 4, iclass 39, count 0 2006.257.23:42:01.86#ibcon#about to read 5, iclass 39, count 0 2006.257.23:42:01.86#ibcon#read 5, iclass 39, count 0 2006.257.23:42:01.86#ibcon#about to read 6, iclass 39, count 0 2006.257.23:42:01.86#ibcon#read 6, iclass 39, count 0 2006.257.23:42:01.86#ibcon#end of sib2, iclass 39, count 0 2006.257.23:42:01.86#ibcon#*after write, iclass 39, count 0 2006.257.23:42:01.86#ibcon#*before return 0, iclass 39, count 0 2006.257.23:42:01.86#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:42:01.86#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.257.23:42:01.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.23:42:01.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.23:42:01.86$vck44/vblo=6,719.99 2006.257.23:42:01.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.257.23:42:01.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.257.23:42:01.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:42:01.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:42:01.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:42:01.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:42:01.86#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:42:01.86#ibcon#first serial, iclass 3, count 0 2006.257.23:42:01.86#ibcon#enter sib2, iclass 3, count 0 2006.257.23:42:01.86#ibcon#flushed, iclass 3, count 0 2006.257.23:42:01.86#ibcon#about to write, iclass 3, count 0 2006.257.23:42:01.86#ibcon#wrote, iclass 3, count 0 2006.257.23:42:01.86#ibcon#about to read 3, iclass 3, count 0 2006.257.23:42:01.88#ibcon#read 3, iclass 3, count 0 2006.257.23:42:01.88#ibcon#about to read 4, iclass 3, count 0 2006.257.23:42:01.88#ibcon#read 4, iclass 3, count 0 2006.257.23:42:01.88#ibcon#about to read 5, iclass 3, count 0 2006.257.23:42:01.88#ibcon#read 5, iclass 3, count 0 2006.257.23:42:01.88#ibcon#about to read 6, iclass 3, count 0 2006.257.23:42:01.88#ibcon#read 6, iclass 3, count 0 2006.257.23:42:01.88#ibcon#end of sib2, iclass 3, count 0 2006.257.23:42:01.88#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:42:01.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:42:01.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:42:01.88#ibcon#*before write, iclass 3, count 0 2006.257.23:42:01.88#ibcon#enter sib2, iclass 3, count 0 2006.257.23:42:01.88#ibcon#flushed, iclass 3, count 0 2006.257.23:42:01.88#ibcon#about to write, iclass 3, count 0 2006.257.23:42:01.88#ibcon#wrote, iclass 3, count 0 2006.257.23:42:01.88#ibcon#about to read 3, iclass 3, count 0 2006.257.23:42:01.92#ibcon#read 3, iclass 3, count 0 2006.257.23:42:01.92#ibcon#about to read 4, iclass 3, count 0 2006.257.23:42:01.92#ibcon#read 4, iclass 3, count 0 2006.257.23:42:01.92#ibcon#about to read 5, iclass 3, count 0 2006.257.23:42:01.92#ibcon#read 5, iclass 3, count 0 2006.257.23:42:01.92#ibcon#about to read 6, iclass 3, count 0 2006.257.23:42:01.92#ibcon#read 6, iclass 3, count 0 2006.257.23:42:01.92#ibcon#end of sib2, iclass 3, count 0 2006.257.23:42:01.92#ibcon#*after write, iclass 3, count 0 2006.257.23:42:01.92#ibcon#*before return 0, iclass 3, count 0 2006.257.23:42:01.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:42:01.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.257.23:42:01.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:42:01.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:42:01.92$vck44/vb=6,4 2006.257.23:42:01.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.257.23:42:01.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.257.23:42:01.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:42:01.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:42:01.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:42:01.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:42:01.98#ibcon#enter wrdev, iclass 5, count 2 2006.257.23:42:01.98#ibcon#first serial, iclass 5, count 2 2006.257.23:42:01.98#ibcon#enter sib2, iclass 5, count 2 2006.257.23:42:01.98#ibcon#flushed, iclass 5, count 2 2006.257.23:42:01.98#ibcon#about to write, iclass 5, count 2 2006.257.23:42:01.98#ibcon#wrote, iclass 5, count 2 2006.257.23:42:01.98#ibcon#about to read 3, iclass 5, count 2 2006.257.23:42:02.00#ibcon#read 3, iclass 5, count 2 2006.257.23:42:02.00#ibcon#about to read 4, iclass 5, count 2 2006.257.23:42:02.00#ibcon#read 4, iclass 5, count 2 2006.257.23:42:02.00#ibcon#about to read 5, iclass 5, count 2 2006.257.23:42:02.00#ibcon#read 5, iclass 5, count 2 2006.257.23:42:02.00#ibcon#about to read 6, iclass 5, count 2 2006.257.23:42:02.00#ibcon#read 6, iclass 5, count 2 2006.257.23:42:02.00#ibcon#end of sib2, iclass 5, count 2 2006.257.23:42:02.00#ibcon#*mode == 0, iclass 5, count 2 2006.257.23:42:02.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.257.23:42:02.00#ibcon#[27=AT06-04\r\n] 2006.257.23:42:02.00#ibcon#*before write, iclass 5, count 2 2006.257.23:42:02.00#ibcon#enter sib2, iclass 5, count 2 2006.257.23:42:02.00#ibcon#flushed, iclass 5, count 2 2006.257.23:42:02.00#ibcon#about to write, iclass 5, count 2 2006.257.23:42:02.00#ibcon#wrote, iclass 5, count 2 2006.257.23:42:02.00#ibcon#about to read 3, iclass 5, count 2 2006.257.23:42:02.03#ibcon#read 3, iclass 5, count 2 2006.257.23:42:02.03#ibcon#about to read 4, iclass 5, count 2 2006.257.23:42:02.03#ibcon#read 4, iclass 5, count 2 2006.257.23:42:02.03#ibcon#about to read 5, iclass 5, count 2 2006.257.23:42:02.03#ibcon#read 5, iclass 5, count 2 2006.257.23:42:02.03#ibcon#about to read 6, iclass 5, count 2 2006.257.23:42:02.03#ibcon#read 6, iclass 5, count 2 2006.257.23:42:02.03#ibcon#end of sib2, iclass 5, count 2 2006.257.23:42:02.03#ibcon#*after write, iclass 5, count 2 2006.257.23:42:02.03#ibcon#*before return 0, iclass 5, count 2 2006.257.23:42:02.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:42:02.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.257.23:42:02.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.257.23:42:02.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:42:02.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:42:02.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:42:02.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:42:02.15#ibcon#enter wrdev, iclass 5, count 0 2006.257.23:42:02.15#ibcon#first serial, iclass 5, count 0 2006.257.23:42:02.15#ibcon#enter sib2, iclass 5, count 0 2006.257.23:42:02.15#ibcon#flushed, iclass 5, count 0 2006.257.23:42:02.15#ibcon#about to write, iclass 5, count 0 2006.257.23:42:02.15#ibcon#wrote, iclass 5, count 0 2006.257.23:42:02.15#ibcon#about to read 3, iclass 5, count 0 2006.257.23:42:02.17#ibcon#read 3, iclass 5, count 0 2006.257.23:42:02.17#ibcon#about to read 4, iclass 5, count 0 2006.257.23:42:02.17#ibcon#read 4, iclass 5, count 0 2006.257.23:42:02.17#ibcon#about to read 5, iclass 5, count 0 2006.257.23:42:02.17#ibcon#read 5, iclass 5, count 0 2006.257.23:42:02.17#ibcon#about to read 6, iclass 5, count 0 2006.257.23:42:02.17#ibcon#read 6, iclass 5, count 0 2006.257.23:42:02.17#ibcon#end of sib2, iclass 5, count 0 2006.257.23:42:02.17#ibcon#*mode == 0, iclass 5, count 0 2006.257.23:42:02.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.23:42:02.17#ibcon#[27=USB\r\n] 2006.257.23:42:02.17#ibcon#*before write, iclass 5, count 0 2006.257.23:42:02.17#ibcon#enter sib2, iclass 5, count 0 2006.257.23:42:02.17#ibcon#flushed, iclass 5, count 0 2006.257.23:42:02.17#ibcon#about to write, iclass 5, count 0 2006.257.23:42:02.17#ibcon#wrote, iclass 5, count 0 2006.257.23:42:02.17#ibcon#about to read 3, iclass 5, count 0 2006.257.23:42:02.20#ibcon#read 3, iclass 5, count 0 2006.257.23:42:02.20#ibcon#about to read 4, iclass 5, count 0 2006.257.23:42:02.20#ibcon#read 4, iclass 5, count 0 2006.257.23:42:02.20#ibcon#about to read 5, iclass 5, count 0 2006.257.23:42:02.20#ibcon#read 5, iclass 5, count 0 2006.257.23:42:02.20#ibcon#about to read 6, iclass 5, count 0 2006.257.23:42:02.20#ibcon#read 6, iclass 5, count 0 2006.257.23:42:02.20#ibcon#end of sib2, iclass 5, count 0 2006.257.23:42:02.20#ibcon#*after write, iclass 5, count 0 2006.257.23:42:02.20#ibcon#*before return 0, iclass 5, count 0 2006.257.23:42:02.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:42:02.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.257.23:42:02.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.23:42:02.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.23:42:02.20$vck44/vblo=7,734.99 2006.257.23:42:02.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.257.23:42:02.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.257.23:42:02.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:42:02.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:42:02.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:42:02.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:42:02.20#ibcon#enter wrdev, iclass 7, count 0 2006.257.23:42:02.20#ibcon#first serial, iclass 7, count 0 2006.257.23:42:02.20#ibcon#enter sib2, iclass 7, count 0 2006.257.23:42:02.20#ibcon#flushed, iclass 7, count 0 2006.257.23:42:02.20#ibcon#about to write, iclass 7, count 0 2006.257.23:42:02.20#ibcon#wrote, iclass 7, count 0 2006.257.23:42:02.20#ibcon#about to read 3, iclass 7, count 0 2006.257.23:42:02.22#ibcon#read 3, iclass 7, count 0 2006.257.23:42:02.22#ibcon#about to read 4, iclass 7, count 0 2006.257.23:42:02.22#ibcon#read 4, iclass 7, count 0 2006.257.23:42:02.22#ibcon#about to read 5, iclass 7, count 0 2006.257.23:42:02.22#ibcon#read 5, iclass 7, count 0 2006.257.23:42:02.22#ibcon#about to read 6, iclass 7, count 0 2006.257.23:42:02.22#ibcon#read 6, iclass 7, count 0 2006.257.23:42:02.22#ibcon#end of sib2, iclass 7, count 0 2006.257.23:42:02.22#ibcon#*mode == 0, iclass 7, count 0 2006.257.23:42:02.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.23:42:02.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:42:02.22#ibcon#*before write, iclass 7, count 0 2006.257.23:42:02.22#ibcon#enter sib2, iclass 7, count 0 2006.257.23:42:02.22#ibcon#flushed, iclass 7, count 0 2006.257.23:42:02.22#ibcon#about to write, iclass 7, count 0 2006.257.23:42:02.22#ibcon#wrote, iclass 7, count 0 2006.257.23:42:02.22#ibcon#about to read 3, iclass 7, count 0 2006.257.23:42:02.26#ibcon#read 3, iclass 7, count 0 2006.257.23:42:02.26#ibcon#about to read 4, iclass 7, count 0 2006.257.23:42:02.26#ibcon#read 4, iclass 7, count 0 2006.257.23:42:02.26#ibcon#about to read 5, iclass 7, count 0 2006.257.23:42:02.26#ibcon#read 5, iclass 7, count 0 2006.257.23:42:02.26#ibcon#about to read 6, iclass 7, count 0 2006.257.23:42:02.26#ibcon#read 6, iclass 7, count 0 2006.257.23:42:02.26#ibcon#end of sib2, iclass 7, count 0 2006.257.23:42:02.26#ibcon#*after write, iclass 7, count 0 2006.257.23:42:02.26#ibcon#*before return 0, iclass 7, count 0 2006.257.23:42:02.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:42:02.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.257.23:42:02.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.23:42:02.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.23:42:02.26$vck44/vb=7,4 2006.257.23:42:02.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.257.23:42:02.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.257.23:42:02.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:42:02.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:42:02.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:42:02.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:42:02.32#ibcon#enter wrdev, iclass 11, count 2 2006.257.23:42:02.32#ibcon#first serial, iclass 11, count 2 2006.257.23:42:02.32#ibcon#enter sib2, iclass 11, count 2 2006.257.23:42:02.32#ibcon#flushed, iclass 11, count 2 2006.257.23:42:02.32#ibcon#about to write, iclass 11, count 2 2006.257.23:42:02.32#ibcon#wrote, iclass 11, count 2 2006.257.23:42:02.32#ibcon#about to read 3, iclass 11, count 2 2006.257.23:42:02.34#ibcon#read 3, iclass 11, count 2 2006.257.23:42:02.34#ibcon#about to read 4, iclass 11, count 2 2006.257.23:42:02.34#ibcon#read 4, iclass 11, count 2 2006.257.23:42:02.34#ibcon#about to read 5, iclass 11, count 2 2006.257.23:42:02.34#ibcon#read 5, iclass 11, count 2 2006.257.23:42:02.34#ibcon#about to read 6, iclass 11, count 2 2006.257.23:42:02.34#ibcon#read 6, iclass 11, count 2 2006.257.23:42:02.34#ibcon#end of sib2, iclass 11, count 2 2006.257.23:42:02.34#ibcon#*mode == 0, iclass 11, count 2 2006.257.23:42:02.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.257.23:42:02.34#ibcon#[27=AT07-04\r\n] 2006.257.23:42:02.34#ibcon#*before write, iclass 11, count 2 2006.257.23:42:02.34#ibcon#enter sib2, iclass 11, count 2 2006.257.23:42:02.34#ibcon#flushed, iclass 11, count 2 2006.257.23:42:02.34#ibcon#about to write, iclass 11, count 2 2006.257.23:42:02.34#ibcon#wrote, iclass 11, count 2 2006.257.23:42:02.34#ibcon#about to read 3, iclass 11, count 2 2006.257.23:42:02.37#ibcon#read 3, iclass 11, count 2 2006.257.23:42:02.37#ibcon#about to read 4, iclass 11, count 2 2006.257.23:42:02.37#ibcon#read 4, iclass 11, count 2 2006.257.23:42:02.37#ibcon#about to read 5, iclass 11, count 2 2006.257.23:42:02.37#ibcon#read 5, iclass 11, count 2 2006.257.23:42:02.37#ibcon#about to read 6, iclass 11, count 2 2006.257.23:42:02.37#ibcon#read 6, iclass 11, count 2 2006.257.23:42:02.37#ibcon#end of sib2, iclass 11, count 2 2006.257.23:42:02.37#ibcon#*after write, iclass 11, count 2 2006.257.23:42:02.37#ibcon#*before return 0, iclass 11, count 2 2006.257.23:42:02.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:42:02.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.257.23:42:02.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.257.23:42:02.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:42:02.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:42:02.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:42:02.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:42:02.49#ibcon#enter wrdev, iclass 11, count 0 2006.257.23:42:02.49#ibcon#first serial, iclass 11, count 0 2006.257.23:42:02.49#ibcon#enter sib2, iclass 11, count 0 2006.257.23:42:02.49#ibcon#flushed, iclass 11, count 0 2006.257.23:42:02.49#ibcon#about to write, iclass 11, count 0 2006.257.23:42:02.49#ibcon#wrote, iclass 11, count 0 2006.257.23:42:02.49#ibcon#about to read 3, iclass 11, count 0 2006.257.23:42:02.51#ibcon#read 3, iclass 11, count 0 2006.257.23:42:02.51#ibcon#about to read 4, iclass 11, count 0 2006.257.23:42:02.51#ibcon#read 4, iclass 11, count 0 2006.257.23:42:02.51#ibcon#about to read 5, iclass 11, count 0 2006.257.23:42:02.51#ibcon#read 5, iclass 11, count 0 2006.257.23:42:02.51#ibcon#about to read 6, iclass 11, count 0 2006.257.23:42:02.51#ibcon#read 6, iclass 11, count 0 2006.257.23:42:02.51#ibcon#end of sib2, iclass 11, count 0 2006.257.23:42:02.51#ibcon#*mode == 0, iclass 11, count 0 2006.257.23:42:02.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.23:42:02.51#ibcon#[27=USB\r\n] 2006.257.23:42:02.51#ibcon#*before write, iclass 11, count 0 2006.257.23:42:02.51#ibcon#enter sib2, iclass 11, count 0 2006.257.23:42:02.51#ibcon#flushed, iclass 11, count 0 2006.257.23:42:02.51#ibcon#about to write, iclass 11, count 0 2006.257.23:42:02.51#ibcon#wrote, iclass 11, count 0 2006.257.23:42:02.51#ibcon#about to read 3, iclass 11, count 0 2006.257.23:42:02.54#ibcon#read 3, iclass 11, count 0 2006.257.23:42:02.54#ibcon#about to read 4, iclass 11, count 0 2006.257.23:42:02.54#ibcon#read 4, iclass 11, count 0 2006.257.23:42:02.54#ibcon#about to read 5, iclass 11, count 0 2006.257.23:42:02.54#ibcon#read 5, iclass 11, count 0 2006.257.23:42:02.54#ibcon#about to read 6, iclass 11, count 0 2006.257.23:42:02.54#ibcon#read 6, iclass 11, count 0 2006.257.23:42:02.54#ibcon#end of sib2, iclass 11, count 0 2006.257.23:42:02.54#ibcon#*after write, iclass 11, count 0 2006.257.23:42:02.54#ibcon#*before return 0, iclass 11, count 0 2006.257.23:42:02.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:42:02.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.257.23:42:02.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.23:42:02.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.23:42:02.54$vck44/vblo=8,744.99 2006.257.23:42:02.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.257.23:42:02.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.257.23:42:02.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:42:02.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:42:02.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:42:02.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:42:02.54#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:42:02.54#ibcon#first serial, iclass 13, count 0 2006.257.23:42:02.54#ibcon#enter sib2, iclass 13, count 0 2006.257.23:42:02.54#ibcon#flushed, iclass 13, count 0 2006.257.23:42:02.54#ibcon#about to write, iclass 13, count 0 2006.257.23:42:02.54#ibcon#wrote, iclass 13, count 0 2006.257.23:42:02.54#ibcon#about to read 3, iclass 13, count 0 2006.257.23:42:02.56#ibcon#read 3, iclass 13, count 0 2006.257.23:42:02.56#ibcon#about to read 4, iclass 13, count 0 2006.257.23:42:02.56#ibcon#read 4, iclass 13, count 0 2006.257.23:42:02.56#ibcon#about to read 5, iclass 13, count 0 2006.257.23:42:02.56#ibcon#read 5, iclass 13, count 0 2006.257.23:42:02.56#ibcon#about to read 6, iclass 13, count 0 2006.257.23:42:02.56#ibcon#read 6, iclass 13, count 0 2006.257.23:42:02.56#ibcon#end of sib2, iclass 13, count 0 2006.257.23:42:02.56#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:42:02.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:42:02.56#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:42:02.56#ibcon#*before write, iclass 13, count 0 2006.257.23:42:02.56#ibcon#enter sib2, iclass 13, count 0 2006.257.23:42:02.56#ibcon#flushed, iclass 13, count 0 2006.257.23:42:02.56#ibcon#about to write, iclass 13, count 0 2006.257.23:42:02.56#ibcon#wrote, iclass 13, count 0 2006.257.23:42:02.56#ibcon#about to read 3, iclass 13, count 0 2006.257.23:42:02.60#ibcon#read 3, iclass 13, count 0 2006.257.23:42:02.60#ibcon#about to read 4, iclass 13, count 0 2006.257.23:42:02.60#ibcon#read 4, iclass 13, count 0 2006.257.23:42:02.60#ibcon#about to read 5, iclass 13, count 0 2006.257.23:42:02.60#ibcon#read 5, iclass 13, count 0 2006.257.23:42:02.60#ibcon#about to read 6, iclass 13, count 0 2006.257.23:42:02.60#ibcon#read 6, iclass 13, count 0 2006.257.23:42:02.60#ibcon#end of sib2, iclass 13, count 0 2006.257.23:42:02.60#ibcon#*after write, iclass 13, count 0 2006.257.23:42:02.60#ibcon#*before return 0, iclass 13, count 0 2006.257.23:42:02.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:42:02.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.257.23:42:02.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:42:02.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:42:02.60$vck44/vb=8,4 2006.257.23:42:02.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.257.23:42:02.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.257.23:42:02.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:42:02.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:42:02.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:42:02.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:42:02.66#ibcon#enter wrdev, iclass 15, count 2 2006.257.23:42:02.66#ibcon#first serial, iclass 15, count 2 2006.257.23:42:02.66#ibcon#enter sib2, iclass 15, count 2 2006.257.23:42:02.66#ibcon#flushed, iclass 15, count 2 2006.257.23:42:02.66#ibcon#about to write, iclass 15, count 2 2006.257.23:42:02.66#ibcon#wrote, iclass 15, count 2 2006.257.23:42:02.66#ibcon#about to read 3, iclass 15, count 2 2006.257.23:42:02.68#ibcon#read 3, iclass 15, count 2 2006.257.23:42:02.68#ibcon#about to read 4, iclass 15, count 2 2006.257.23:42:02.68#ibcon#read 4, iclass 15, count 2 2006.257.23:42:02.68#ibcon#about to read 5, iclass 15, count 2 2006.257.23:42:02.68#ibcon#read 5, iclass 15, count 2 2006.257.23:42:02.68#ibcon#about to read 6, iclass 15, count 2 2006.257.23:42:02.68#ibcon#read 6, iclass 15, count 2 2006.257.23:42:02.68#ibcon#end of sib2, iclass 15, count 2 2006.257.23:42:02.68#ibcon#*mode == 0, iclass 15, count 2 2006.257.23:42:02.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.257.23:42:02.68#ibcon#[27=AT08-04\r\n] 2006.257.23:42:02.68#ibcon#*before write, iclass 15, count 2 2006.257.23:42:02.68#ibcon#enter sib2, iclass 15, count 2 2006.257.23:42:02.68#ibcon#flushed, iclass 15, count 2 2006.257.23:42:02.68#ibcon#about to write, iclass 15, count 2 2006.257.23:42:02.68#ibcon#wrote, iclass 15, count 2 2006.257.23:42:02.68#ibcon#about to read 3, iclass 15, count 2 2006.257.23:42:02.71#ibcon#read 3, iclass 15, count 2 2006.257.23:42:02.71#ibcon#about to read 4, iclass 15, count 2 2006.257.23:42:02.71#ibcon#read 4, iclass 15, count 2 2006.257.23:42:02.71#ibcon#about to read 5, iclass 15, count 2 2006.257.23:42:02.71#ibcon#read 5, iclass 15, count 2 2006.257.23:42:02.71#ibcon#about to read 6, iclass 15, count 2 2006.257.23:42:02.71#ibcon#read 6, iclass 15, count 2 2006.257.23:42:02.71#ibcon#end of sib2, iclass 15, count 2 2006.257.23:42:02.71#ibcon#*after write, iclass 15, count 2 2006.257.23:42:02.71#ibcon#*before return 0, iclass 15, count 2 2006.257.23:42:02.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:42:02.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.257.23:42:02.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.257.23:42:02.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:42:02.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:42:02.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:42:02.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:42:02.83#ibcon#enter wrdev, iclass 15, count 0 2006.257.23:42:02.83#ibcon#first serial, iclass 15, count 0 2006.257.23:42:02.83#ibcon#enter sib2, iclass 15, count 0 2006.257.23:42:02.83#ibcon#flushed, iclass 15, count 0 2006.257.23:42:02.83#ibcon#about to write, iclass 15, count 0 2006.257.23:42:02.83#ibcon#wrote, iclass 15, count 0 2006.257.23:42:02.83#ibcon#about to read 3, iclass 15, count 0 2006.257.23:42:02.85#ibcon#read 3, iclass 15, count 0 2006.257.23:42:02.85#ibcon#about to read 4, iclass 15, count 0 2006.257.23:42:02.85#ibcon#read 4, iclass 15, count 0 2006.257.23:42:02.85#ibcon#about to read 5, iclass 15, count 0 2006.257.23:42:02.85#ibcon#read 5, iclass 15, count 0 2006.257.23:42:02.85#ibcon#about to read 6, iclass 15, count 0 2006.257.23:42:02.85#ibcon#read 6, iclass 15, count 0 2006.257.23:42:02.85#ibcon#end of sib2, iclass 15, count 0 2006.257.23:42:02.85#ibcon#*mode == 0, iclass 15, count 0 2006.257.23:42:02.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.23:42:02.85#ibcon#[27=USB\r\n] 2006.257.23:42:02.85#ibcon#*before write, iclass 15, count 0 2006.257.23:42:02.85#ibcon#enter sib2, iclass 15, count 0 2006.257.23:42:02.85#ibcon#flushed, iclass 15, count 0 2006.257.23:42:02.85#ibcon#about to write, iclass 15, count 0 2006.257.23:42:02.85#ibcon#wrote, iclass 15, count 0 2006.257.23:42:02.85#ibcon#about to read 3, iclass 15, count 0 2006.257.23:42:02.88#ibcon#read 3, iclass 15, count 0 2006.257.23:42:02.88#ibcon#about to read 4, iclass 15, count 0 2006.257.23:42:02.88#ibcon#read 4, iclass 15, count 0 2006.257.23:42:02.88#ibcon#about to read 5, iclass 15, count 0 2006.257.23:42:02.88#ibcon#read 5, iclass 15, count 0 2006.257.23:42:02.88#ibcon#about to read 6, iclass 15, count 0 2006.257.23:42:02.88#ibcon#read 6, iclass 15, count 0 2006.257.23:42:02.88#ibcon#end of sib2, iclass 15, count 0 2006.257.23:42:02.88#ibcon#*after write, iclass 15, count 0 2006.257.23:42:02.88#ibcon#*before return 0, iclass 15, count 0 2006.257.23:42:02.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:42:02.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.257.23:42:02.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.23:42:02.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.23:42:02.88$vck44/vabw=wide 2006.257.23:42:02.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.257.23:42:02.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.257.23:42:02.88#ibcon#ireg 8 cls_cnt 0 2006.257.23:42:02.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:42:02.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:42:02.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:42:02.88#ibcon#enter wrdev, iclass 17, count 0 2006.257.23:42:02.88#ibcon#first serial, iclass 17, count 0 2006.257.23:42:02.88#ibcon#enter sib2, iclass 17, count 0 2006.257.23:42:02.88#ibcon#flushed, iclass 17, count 0 2006.257.23:42:02.88#ibcon#about to write, iclass 17, count 0 2006.257.23:42:02.88#ibcon#wrote, iclass 17, count 0 2006.257.23:42:02.88#ibcon#about to read 3, iclass 17, count 0 2006.257.23:42:02.90#ibcon#read 3, iclass 17, count 0 2006.257.23:42:02.90#ibcon#about to read 4, iclass 17, count 0 2006.257.23:42:02.90#ibcon#read 4, iclass 17, count 0 2006.257.23:42:02.90#ibcon#about to read 5, iclass 17, count 0 2006.257.23:42:02.90#ibcon#read 5, iclass 17, count 0 2006.257.23:42:02.90#ibcon#about to read 6, iclass 17, count 0 2006.257.23:42:02.90#ibcon#read 6, iclass 17, count 0 2006.257.23:42:02.90#ibcon#end of sib2, iclass 17, count 0 2006.257.23:42:02.90#ibcon#*mode == 0, iclass 17, count 0 2006.257.23:42:02.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.23:42:02.90#ibcon#[25=BW32\r\n] 2006.257.23:42:02.90#ibcon#*before write, iclass 17, count 0 2006.257.23:42:02.90#ibcon#enter sib2, iclass 17, count 0 2006.257.23:42:02.90#ibcon#flushed, iclass 17, count 0 2006.257.23:42:02.90#ibcon#about to write, iclass 17, count 0 2006.257.23:42:02.90#ibcon#wrote, iclass 17, count 0 2006.257.23:42:02.90#ibcon#about to read 3, iclass 17, count 0 2006.257.23:42:02.93#ibcon#read 3, iclass 17, count 0 2006.257.23:42:02.93#ibcon#about to read 4, iclass 17, count 0 2006.257.23:42:02.93#ibcon#read 4, iclass 17, count 0 2006.257.23:42:02.93#ibcon#about to read 5, iclass 17, count 0 2006.257.23:42:02.93#ibcon#read 5, iclass 17, count 0 2006.257.23:42:02.93#ibcon#about to read 6, iclass 17, count 0 2006.257.23:42:02.93#ibcon#read 6, iclass 17, count 0 2006.257.23:42:02.93#ibcon#end of sib2, iclass 17, count 0 2006.257.23:42:02.93#ibcon#*after write, iclass 17, count 0 2006.257.23:42:02.93#ibcon#*before return 0, iclass 17, count 0 2006.257.23:42:02.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:42:02.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.257.23:42:02.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.23:42:02.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.23:42:02.93$vck44/vbbw=wide 2006.257.23:42:02.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.23:42:02.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.23:42:02.93#ibcon#ireg 8 cls_cnt 0 2006.257.23:42:02.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:42:03.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:42:03.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:42:03.00#ibcon#enter wrdev, iclass 19, count 0 2006.257.23:42:03.00#ibcon#first serial, iclass 19, count 0 2006.257.23:42:03.00#ibcon#enter sib2, iclass 19, count 0 2006.257.23:42:03.00#ibcon#flushed, iclass 19, count 0 2006.257.23:42:03.00#ibcon#about to write, iclass 19, count 0 2006.257.23:42:03.00#ibcon#wrote, iclass 19, count 0 2006.257.23:42:03.00#ibcon#about to read 3, iclass 19, count 0 2006.257.23:42:03.02#ibcon#read 3, iclass 19, count 0 2006.257.23:42:03.02#ibcon#about to read 4, iclass 19, count 0 2006.257.23:42:03.02#ibcon#read 4, iclass 19, count 0 2006.257.23:42:03.02#ibcon#about to read 5, iclass 19, count 0 2006.257.23:42:03.02#ibcon#read 5, iclass 19, count 0 2006.257.23:42:03.02#ibcon#about to read 6, iclass 19, count 0 2006.257.23:42:03.02#ibcon#read 6, iclass 19, count 0 2006.257.23:42:03.02#ibcon#end of sib2, iclass 19, count 0 2006.257.23:42:03.02#ibcon#*mode == 0, iclass 19, count 0 2006.257.23:42:03.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.23:42:03.02#ibcon#[27=BW32\r\n] 2006.257.23:42:03.02#ibcon#*before write, iclass 19, count 0 2006.257.23:42:03.02#ibcon#enter sib2, iclass 19, count 0 2006.257.23:42:03.02#ibcon#flushed, iclass 19, count 0 2006.257.23:42:03.02#ibcon#about to write, iclass 19, count 0 2006.257.23:42:03.02#ibcon#wrote, iclass 19, count 0 2006.257.23:42:03.02#ibcon#about to read 3, iclass 19, count 0 2006.257.23:42:03.05#ibcon#read 3, iclass 19, count 0 2006.257.23:42:03.05#ibcon#about to read 4, iclass 19, count 0 2006.257.23:42:03.05#ibcon#read 4, iclass 19, count 0 2006.257.23:42:03.05#ibcon#about to read 5, iclass 19, count 0 2006.257.23:42:03.05#ibcon#read 5, iclass 19, count 0 2006.257.23:42:03.05#ibcon#about to read 6, iclass 19, count 0 2006.257.23:42:03.05#ibcon#read 6, iclass 19, count 0 2006.257.23:42:03.05#ibcon#end of sib2, iclass 19, count 0 2006.257.23:42:03.05#ibcon#*after write, iclass 19, count 0 2006.257.23:42:03.05#ibcon#*before return 0, iclass 19, count 0 2006.257.23:42:03.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:42:03.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:42:03.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.23:42:03.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.23:42:03.05$setupk4/ifdk4 2006.257.23:42:03.05$ifdk4/lo= 2006.257.23:42:03.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:42:03.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:42:03.05$ifdk4/patch= 2006.257.23:42:03.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:42:03.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:42:03.05$setupk4/!*+20s 2006.257.23:42:09.43#abcon#<5=/16 1.1 2.4 20.92 801016.2\r\n> 2006.257.23:42:09.45#abcon#{5=INTERFACE CLEAR} 2006.257.23:42:09.51#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:42:17.56$setupk4/"tpicd 2006.257.23:42:17.56$setupk4/echo=off 2006.257.23:42:17.56$setupk4/xlog=off 2006.257.23:42:17.56:!2006.257.23:46:19 2006.257.23:42:52.13#trakl#Source acquired 2006.257.23:42:53.13#flagr#flagr/antenna,acquired 2006.257.23:46:19.00:preob 2006.257.23:46:19.14/onsource/TRACKING 2006.257.23:46:19.14:!2006.257.23:46:29 2006.257.23:46:29.00:"tape 2006.257.23:46:29.00:"st=record 2006.257.23:46:29.00:data_valid=on 2006.257.23:46:29.00:midob 2006.257.23:46:29.14/onsource/TRACKING 2006.257.23:46:29.14/wx/21.07,1016.1,78 2006.257.23:46:29.27/cable/+6.4818E-03 2006.257.23:46:30.36/va/01,08,usb,yes,32,35 2006.257.23:46:30.36/va/02,07,usb,yes,35,35 2006.257.23:46:30.36/va/03,08,usb,yes,31,33 2006.257.23:46:30.36/va/04,07,usb,yes,36,38 2006.257.23:46:30.36/va/05,04,usb,yes,32,33 2006.257.23:46:30.36/va/06,04,usb,yes,36,35 2006.257.23:46:30.36/va/07,04,usb,yes,37,37 2006.257.23:46:30.36/va/08,04,usb,yes,31,38 2006.257.23:46:30.59/valo/01,524.99,yes,locked 2006.257.23:46:30.59/valo/02,534.99,yes,locked 2006.257.23:46:30.59/valo/03,564.99,yes,locked 2006.257.23:46:30.59/valo/04,624.99,yes,locked 2006.257.23:46:30.59/valo/05,734.99,yes,locked 2006.257.23:46:30.59/valo/06,814.99,yes,locked 2006.257.23:46:30.59/valo/07,864.99,yes,locked 2006.257.23:46:30.59/valo/08,884.99,yes,locked 2006.257.23:46:31.68/vb/01,04,usb,yes,32,30 2006.257.23:46:31.68/vb/02,05,usb,yes,30,30 2006.257.23:46:31.68/vb/03,04,usb,yes,31,34 2006.257.23:46:31.68/vb/04,05,usb,yes,34,31 2006.257.23:46:31.68/vb/05,04,usb,yes,28,31 2006.257.23:46:31.68/vb/06,04,usb,yes,33,29 2006.257.23:46:31.68/vb/07,04,usb,yes,32,32 2006.257.23:46:31.68/vb/08,04,usb,yes,30,33 2006.257.23:46:31.92/vblo/01,629.99,yes,locked 2006.257.23:46:31.92/vblo/02,634.99,yes,locked 2006.257.23:46:31.92/vblo/03,649.99,yes,locked 2006.257.23:46:31.92/vblo/04,679.99,yes,locked 2006.257.23:46:31.92/vblo/05,709.99,yes,locked 2006.257.23:46:31.92/vblo/06,719.99,yes,locked 2006.257.23:46:31.92/vblo/07,734.99,yes,locked 2006.257.23:46:31.92/vblo/08,744.99,yes,locked 2006.257.23:46:32.07/vabw/8 2006.257.23:46:32.22/vbbw/8 2006.257.23:46:32.34/xfe/off,on,15.2 2006.257.23:46:32.71/ifatt/23,28,28,28 2006.257.23:46:33.08/fmout-gps/S +4.50E-07 2006.257.23:46:33.12:!2006.257.23:48:39 2006.257.23:48:39.01:data_valid=off 2006.257.23:48:39.01:"et 2006.257.23:48:39.02:!+3s 2006.257.23:48:42.03:"tape 2006.257.23:48:42.03:postob 2006.257.23:48:42.19/cable/+6.4814E-03 2006.257.23:48:42.19/wx/21.10,1016.1,77 2006.257.23:48:42.25/fmout-gps/S +4.51E-07 2006.257.23:48:42.25:scan_name=257-2354,jd0609,100 2006.257.23:48:42.26:source=0528+134,053056.42,133155.1,2000.0,cw 2006.257.23:48:44.14#flagr#flagr/antenna,new-source 2006.257.23:48:44.14:checkk5 2006.257.23:48:44.48/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:48:44.82/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:48:45.18/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:48:45.53/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:48:45.87/chk_obsdata//k5ts1/T2572346??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.23:48:46.21/chk_obsdata//k5ts2/T2572346??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.23:48:46.55/chk_obsdata//k5ts3/T2572346??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.23:48:46.90/chk_obsdata//k5ts4/T2572346??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.257.23:48:47.57/k5log//k5ts1_log_newline 2006.257.23:48:48.22/k5log//k5ts2_log_newline 2006.257.23:48:48.87/k5log//k5ts3_log_newline 2006.257.23:48:49.54/k5log//k5ts4_log_newline 2006.257.23:48:49.57/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:48:49.57:setupk4=1 2006.257.23:48:49.57$setupk4/echo=on 2006.257.23:48:49.57$setupk4/pcalon 2006.257.23:48:49.57$pcalon/"no phase cal control is implemented here 2006.257.23:48:49.57$setupk4/"tpicd=stop 2006.257.23:48:49.57$setupk4/"rec=synch_on 2006.257.23:48:49.57$setupk4/"rec_mode=128 2006.257.23:48:49.57$setupk4/!* 2006.257.23:48:49.57$setupk4/recpk4 2006.257.23:48:49.57$recpk4/recpatch= 2006.257.23:48:49.58$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:48:49.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:48:49.58$setupk4/vck44 2006.257.23:48:49.58$vck44/valo=1,524.99 2006.257.23:48:49.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.23:48:49.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.23:48:49.58#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:49.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:49.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:49.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:49.58#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:48:49.58#ibcon#first serial, iclass 40, count 0 2006.257.23:48:49.58#ibcon#enter sib2, iclass 40, count 0 2006.257.23:48:49.58#ibcon#flushed, iclass 40, count 0 2006.257.23:48:49.58#ibcon#about to write, iclass 40, count 0 2006.257.23:48:49.58#ibcon#wrote, iclass 40, count 0 2006.257.23:48:49.58#ibcon#about to read 3, iclass 40, count 0 2006.257.23:48:49.59#ibcon#read 3, iclass 40, count 0 2006.257.23:48:49.59#ibcon#about to read 4, iclass 40, count 0 2006.257.23:48:49.59#ibcon#read 4, iclass 40, count 0 2006.257.23:48:49.59#ibcon#about to read 5, iclass 40, count 0 2006.257.23:48:49.59#ibcon#read 5, iclass 40, count 0 2006.257.23:48:49.59#ibcon#about to read 6, iclass 40, count 0 2006.257.23:48:49.59#ibcon#read 6, iclass 40, count 0 2006.257.23:48:49.59#ibcon#end of sib2, iclass 40, count 0 2006.257.23:48:49.59#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:48:49.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:48:49.59#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:48:49.59#ibcon#*before write, iclass 40, count 0 2006.257.23:48:49.59#ibcon#enter sib2, iclass 40, count 0 2006.257.23:48:49.59#ibcon#flushed, iclass 40, count 0 2006.257.23:48:49.59#ibcon#about to write, iclass 40, count 0 2006.257.23:48:49.59#ibcon#wrote, iclass 40, count 0 2006.257.23:48:49.59#ibcon#about to read 3, iclass 40, count 0 2006.257.23:48:49.64#ibcon#read 3, iclass 40, count 0 2006.257.23:48:49.64#ibcon#about to read 4, iclass 40, count 0 2006.257.23:48:49.64#ibcon#read 4, iclass 40, count 0 2006.257.23:48:49.64#ibcon#about to read 5, iclass 40, count 0 2006.257.23:48:49.64#ibcon#read 5, iclass 40, count 0 2006.257.23:48:49.64#ibcon#about to read 6, iclass 40, count 0 2006.257.23:48:49.64#ibcon#read 6, iclass 40, count 0 2006.257.23:48:49.64#ibcon#end of sib2, iclass 40, count 0 2006.257.23:48:49.64#ibcon#*after write, iclass 40, count 0 2006.257.23:48:49.64#ibcon#*before return 0, iclass 40, count 0 2006.257.23:48:49.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:49.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:49.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:48:49.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:48:49.64$vck44/va=1,8 2006.257.23:48:49.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.23:48:49.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.23:48:49.64#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:49.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:49.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:49.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:49.64#ibcon#enter wrdev, iclass 4, count 2 2006.257.23:48:49.64#ibcon#first serial, iclass 4, count 2 2006.257.23:48:49.64#ibcon#enter sib2, iclass 4, count 2 2006.257.23:48:49.64#ibcon#flushed, iclass 4, count 2 2006.257.23:48:49.64#ibcon#about to write, iclass 4, count 2 2006.257.23:48:49.64#ibcon#wrote, iclass 4, count 2 2006.257.23:48:49.64#ibcon#about to read 3, iclass 4, count 2 2006.257.23:48:49.66#ibcon#read 3, iclass 4, count 2 2006.257.23:48:49.66#ibcon#about to read 4, iclass 4, count 2 2006.257.23:48:49.66#ibcon#read 4, iclass 4, count 2 2006.257.23:48:49.66#ibcon#about to read 5, iclass 4, count 2 2006.257.23:48:49.66#ibcon#read 5, iclass 4, count 2 2006.257.23:48:49.66#ibcon#about to read 6, iclass 4, count 2 2006.257.23:48:49.66#ibcon#read 6, iclass 4, count 2 2006.257.23:48:49.66#ibcon#end of sib2, iclass 4, count 2 2006.257.23:48:49.66#ibcon#*mode == 0, iclass 4, count 2 2006.257.23:48:49.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.23:48:49.66#ibcon#[25=AT01-08\r\n] 2006.257.23:48:49.66#ibcon#*before write, iclass 4, count 2 2006.257.23:48:49.66#ibcon#enter sib2, iclass 4, count 2 2006.257.23:48:49.66#ibcon#flushed, iclass 4, count 2 2006.257.23:48:49.66#ibcon#about to write, iclass 4, count 2 2006.257.23:48:49.66#ibcon#wrote, iclass 4, count 2 2006.257.23:48:49.66#ibcon#about to read 3, iclass 4, count 2 2006.257.23:48:49.69#ibcon#read 3, iclass 4, count 2 2006.257.23:48:49.69#ibcon#about to read 4, iclass 4, count 2 2006.257.23:48:49.69#ibcon#read 4, iclass 4, count 2 2006.257.23:48:49.69#ibcon#about to read 5, iclass 4, count 2 2006.257.23:48:49.69#ibcon#read 5, iclass 4, count 2 2006.257.23:48:49.69#ibcon#about to read 6, iclass 4, count 2 2006.257.23:48:49.69#ibcon#read 6, iclass 4, count 2 2006.257.23:48:49.69#ibcon#end of sib2, iclass 4, count 2 2006.257.23:48:49.69#ibcon#*after write, iclass 4, count 2 2006.257.23:48:49.69#ibcon#*before return 0, iclass 4, count 2 2006.257.23:48:49.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:49.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:49.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.23:48:49.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:49.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:49.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:49.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:49.81#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:48:49.81#ibcon#first serial, iclass 4, count 0 2006.257.23:48:49.81#ibcon#enter sib2, iclass 4, count 0 2006.257.23:48:49.81#ibcon#flushed, iclass 4, count 0 2006.257.23:48:49.81#ibcon#about to write, iclass 4, count 0 2006.257.23:48:49.81#ibcon#wrote, iclass 4, count 0 2006.257.23:48:49.81#ibcon#about to read 3, iclass 4, count 0 2006.257.23:48:49.83#ibcon#read 3, iclass 4, count 0 2006.257.23:48:49.83#ibcon#about to read 4, iclass 4, count 0 2006.257.23:48:49.83#ibcon#read 4, iclass 4, count 0 2006.257.23:48:49.83#ibcon#about to read 5, iclass 4, count 0 2006.257.23:48:49.83#ibcon#read 5, iclass 4, count 0 2006.257.23:48:49.83#ibcon#about to read 6, iclass 4, count 0 2006.257.23:48:49.83#ibcon#read 6, iclass 4, count 0 2006.257.23:48:49.83#ibcon#end of sib2, iclass 4, count 0 2006.257.23:48:49.83#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:48:49.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:48:49.83#ibcon#[25=USB\r\n] 2006.257.23:48:49.83#ibcon#*before write, iclass 4, count 0 2006.257.23:48:49.83#ibcon#enter sib2, iclass 4, count 0 2006.257.23:48:49.83#ibcon#flushed, iclass 4, count 0 2006.257.23:48:49.83#ibcon#about to write, iclass 4, count 0 2006.257.23:48:49.83#ibcon#wrote, iclass 4, count 0 2006.257.23:48:49.83#ibcon#about to read 3, iclass 4, count 0 2006.257.23:48:49.86#ibcon#read 3, iclass 4, count 0 2006.257.23:48:49.86#ibcon#about to read 4, iclass 4, count 0 2006.257.23:48:49.86#ibcon#read 4, iclass 4, count 0 2006.257.23:48:49.86#ibcon#about to read 5, iclass 4, count 0 2006.257.23:48:49.86#ibcon#read 5, iclass 4, count 0 2006.257.23:48:49.86#ibcon#about to read 6, iclass 4, count 0 2006.257.23:48:49.86#ibcon#read 6, iclass 4, count 0 2006.257.23:48:49.86#ibcon#end of sib2, iclass 4, count 0 2006.257.23:48:49.86#ibcon#*after write, iclass 4, count 0 2006.257.23:48:49.86#ibcon#*before return 0, iclass 4, count 0 2006.257.23:48:49.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:49.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:49.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:48:49.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:48:49.86$vck44/valo=2,534.99 2006.257.23:48:49.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.23:48:49.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.23:48:49.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:49.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:49.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:49.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:49.86#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:48:49.86#ibcon#first serial, iclass 6, count 0 2006.257.23:48:49.86#ibcon#enter sib2, iclass 6, count 0 2006.257.23:48:49.86#ibcon#flushed, iclass 6, count 0 2006.257.23:48:49.86#ibcon#about to write, iclass 6, count 0 2006.257.23:48:49.86#ibcon#wrote, iclass 6, count 0 2006.257.23:48:49.86#ibcon#about to read 3, iclass 6, count 0 2006.257.23:48:49.88#ibcon#read 3, iclass 6, count 0 2006.257.23:48:49.88#ibcon#about to read 4, iclass 6, count 0 2006.257.23:48:49.88#ibcon#read 4, iclass 6, count 0 2006.257.23:48:49.88#ibcon#about to read 5, iclass 6, count 0 2006.257.23:48:49.88#ibcon#read 5, iclass 6, count 0 2006.257.23:48:49.88#ibcon#about to read 6, iclass 6, count 0 2006.257.23:48:49.88#ibcon#read 6, iclass 6, count 0 2006.257.23:48:49.88#ibcon#end of sib2, iclass 6, count 0 2006.257.23:48:49.88#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:48:49.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:48:49.88#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:48:49.88#ibcon#*before write, iclass 6, count 0 2006.257.23:48:49.88#ibcon#enter sib2, iclass 6, count 0 2006.257.23:48:49.88#ibcon#flushed, iclass 6, count 0 2006.257.23:48:49.88#ibcon#about to write, iclass 6, count 0 2006.257.23:48:49.88#ibcon#wrote, iclass 6, count 0 2006.257.23:48:49.88#ibcon#about to read 3, iclass 6, count 0 2006.257.23:48:49.92#ibcon#read 3, iclass 6, count 0 2006.257.23:48:49.92#ibcon#about to read 4, iclass 6, count 0 2006.257.23:48:49.92#ibcon#read 4, iclass 6, count 0 2006.257.23:48:49.92#ibcon#about to read 5, iclass 6, count 0 2006.257.23:48:49.92#ibcon#read 5, iclass 6, count 0 2006.257.23:48:49.92#ibcon#about to read 6, iclass 6, count 0 2006.257.23:48:49.92#ibcon#read 6, iclass 6, count 0 2006.257.23:48:49.92#ibcon#end of sib2, iclass 6, count 0 2006.257.23:48:49.92#ibcon#*after write, iclass 6, count 0 2006.257.23:48:49.92#ibcon#*before return 0, iclass 6, count 0 2006.257.23:48:49.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:49.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:49.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:48:49.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:48:49.92$vck44/va=2,7 2006.257.23:48:49.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.23:48:49.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.23:48:49.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:49.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:49.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:49.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:49.98#ibcon#enter wrdev, iclass 10, count 2 2006.257.23:48:49.98#ibcon#first serial, iclass 10, count 2 2006.257.23:48:49.98#ibcon#enter sib2, iclass 10, count 2 2006.257.23:48:49.98#ibcon#flushed, iclass 10, count 2 2006.257.23:48:49.98#ibcon#about to write, iclass 10, count 2 2006.257.23:48:49.98#ibcon#wrote, iclass 10, count 2 2006.257.23:48:49.98#ibcon#about to read 3, iclass 10, count 2 2006.257.23:48:50.00#ibcon#read 3, iclass 10, count 2 2006.257.23:48:50.00#ibcon#about to read 4, iclass 10, count 2 2006.257.23:48:50.00#ibcon#read 4, iclass 10, count 2 2006.257.23:48:50.00#ibcon#about to read 5, iclass 10, count 2 2006.257.23:48:50.00#ibcon#read 5, iclass 10, count 2 2006.257.23:48:50.00#ibcon#about to read 6, iclass 10, count 2 2006.257.23:48:50.00#ibcon#read 6, iclass 10, count 2 2006.257.23:48:50.00#ibcon#end of sib2, iclass 10, count 2 2006.257.23:48:50.00#ibcon#*mode == 0, iclass 10, count 2 2006.257.23:48:50.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.23:48:50.00#ibcon#[25=AT02-07\r\n] 2006.257.23:48:50.00#ibcon#*before write, iclass 10, count 2 2006.257.23:48:50.00#ibcon#enter sib2, iclass 10, count 2 2006.257.23:48:50.00#ibcon#flushed, iclass 10, count 2 2006.257.23:48:50.00#ibcon#about to write, iclass 10, count 2 2006.257.23:48:50.00#ibcon#wrote, iclass 10, count 2 2006.257.23:48:50.00#ibcon#about to read 3, iclass 10, count 2 2006.257.23:48:50.03#ibcon#read 3, iclass 10, count 2 2006.257.23:48:50.03#ibcon#about to read 4, iclass 10, count 2 2006.257.23:48:50.03#ibcon#read 4, iclass 10, count 2 2006.257.23:48:50.03#ibcon#about to read 5, iclass 10, count 2 2006.257.23:48:50.03#ibcon#read 5, iclass 10, count 2 2006.257.23:48:50.03#ibcon#about to read 6, iclass 10, count 2 2006.257.23:48:50.03#ibcon#read 6, iclass 10, count 2 2006.257.23:48:50.03#ibcon#end of sib2, iclass 10, count 2 2006.257.23:48:50.03#ibcon#*after write, iclass 10, count 2 2006.257.23:48:50.03#ibcon#*before return 0, iclass 10, count 2 2006.257.23:48:50.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:50.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:50.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.23:48:50.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:50.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:50.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:50.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:50.15#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:48:50.15#ibcon#first serial, iclass 10, count 0 2006.257.23:48:50.15#ibcon#enter sib2, iclass 10, count 0 2006.257.23:48:50.15#ibcon#flushed, iclass 10, count 0 2006.257.23:48:50.15#ibcon#about to write, iclass 10, count 0 2006.257.23:48:50.15#ibcon#wrote, iclass 10, count 0 2006.257.23:48:50.15#ibcon#about to read 3, iclass 10, count 0 2006.257.23:48:50.17#ibcon#read 3, iclass 10, count 0 2006.257.23:48:50.17#ibcon#about to read 4, iclass 10, count 0 2006.257.23:48:50.17#ibcon#read 4, iclass 10, count 0 2006.257.23:48:50.17#ibcon#about to read 5, iclass 10, count 0 2006.257.23:48:50.17#ibcon#read 5, iclass 10, count 0 2006.257.23:48:50.17#ibcon#about to read 6, iclass 10, count 0 2006.257.23:48:50.17#ibcon#read 6, iclass 10, count 0 2006.257.23:48:50.17#ibcon#end of sib2, iclass 10, count 0 2006.257.23:48:50.17#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:48:50.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:48:50.17#ibcon#[25=USB\r\n] 2006.257.23:48:50.17#ibcon#*before write, iclass 10, count 0 2006.257.23:48:50.17#ibcon#enter sib2, iclass 10, count 0 2006.257.23:48:50.17#ibcon#flushed, iclass 10, count 0 2006.257.23:48:50.17#ibcon#about to write, iclass 10, count 0 2006.257.23:48:50.17#ibcon#wrote, iclass 10, count 0 2006.257.23:48:50.17#ibcon#about to read 3, iclass 10, count 0 2006.257.23:48:50.20#ibcon#read 3, iclass 10, count 0 2006.257.23:48:50.20#ibcon#about to read 4, iclass 10, count 0 2006.257.23:48:50.20#ibcon#read 4, iclass 10, count 0 2006.257.23:48:50.20#ibcon#about to read 5, iclass 10, count 0 2006.257.23:48:50.20#ibcon#read 5, iclass 10, count 0 2006.257.23:48:50.20#ibcon#about to read 6, iclass 10, count 0 2006.257.23:48:50.20#ibcon#read 6, iclass 10, count 0 2006.257.23:48:50.20#ibcon#end of sib2, iclass 10, count 0 2006.257.23:48:50.20#ibcon#*after write, iclass 10, count 0 2006.257.23:48:50.20#ibcon#*before return 0, iclass 10, count 0 2006.257.23:48:50.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:50.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:50.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:48:50.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:48:50.20$vck44/valo=3,564.99 2006.257.23:48:50.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.23:48:50.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.23:48:50.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:50.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:50.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:50.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:50.20#ibcon#enter wrdev, iclass 12, count 0 2006.257.23:48:50.20#ibcon#first serial, iclass 12, count 0 2006.257.23:48:50.20#ibcon#enter sib2, iclass 12, count 0 2006.257.23:48:50.20#ibcon#flushed, iclass 12, count 0 2006.257.23:48:50.20#ibcon#about to write, iclass 12, count 0 2006.257.23:48:50.20#ibcon#wrote, iclass 12, count 0 2006.257.23:48:50.20#ibcon#about to read 3, iclass 12, count 0 2006.257.23:48:50.22#ibcon#read 3, iclass 12, count 0 2006.257.23:48:50.22#ibcon#about to read 4, iclass 12, count 0 2006.257.23:48:50.22#ibcon#read 4, iclass 12, count 0 2006.257.23:48:50.22#ibcon#about to read 5, iclass 12, count 0 2006.257.23:48:50.22#ibcon#read 5, iclass 12, count 0 2006.257.23:48:50.22#ibcon#about to read 6, iclass 12, count 0 2006.257.23:48:50.22#ibcon#read 6, iclass 12, count 0 2006.257.23:48:50.22#ibcon#end of sib2, iclass 12, count 0 2006.257.23:48:50.22#ibcon#*mode == 0, iclass 12, count 0 2006.257.23:48:50.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.23:48:50.22#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:48:50.22#ibcon#*before write, iclass 12, count 0 2006.257.23:48:50.22#ibcon#enter sib2, iclass 12, count 0 2006.257.23:48:50.22#ibcon#flushed, iclass 12, count 0 2006.257.23:48:50.22#ibcon#about to write, iclass 12, count 0 2006.257.23:48:50.22#ibcon#wrote, iclass 12, count 0 2006.257.23:48:50.22#ibcon#about to read 3, iclass 12, count 0 2006.257.23:48:50.26#ibcon#read 3, iclass 12, count 0 2006.257.23:48:50.26#ibcon#about to read 4, iclass 12, count 0 2006.257.23:48:50.26#ibcon#read 4, iclass 12, count 0 2006.257.23:48:50.26#ibcon#about to read 5, iclass 12, count 0 2006.257.23:48:50.26#ibcon#read 5, iclass 12, count 0 2006.257.23:48:50.26#ibcon#about to read 6, iclass 12, count 0 2006.257.23:48:50.26#ibcon#read 6, iclass 12, count 0 2006.257.23:48:50.26#ibcon#end of sib2, iclass 12, count 0 2006.257.23:48:50.26#ibcon#*after write, iclass 12, count 0 2006.257.23:48:50.26#ibcon#*before return 0, iclass 12, count 0 2006.257.23:48:50.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:50.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:50.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.23:48:50.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.23:48:50.26$vck44/va=3,8 2006.257.23:48:50.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.23:48:50.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.23:48:50.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:50.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:50.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:50.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:50.32#ibcon#enter wrdev, iclass 14, count 2 2006.257.23:48:50.32#ibcon#first serial, iclass 14, count 2 2006.257.23:48:50.32#ibcon#enter sib2, iclass 14, count 2 2006.257.23:48:50.32#ibcon#flushed, iclass 14, count 2 2006.257.23:48:50.32#ibcon#about to write, iclass 14, count 2 2006.257.23:48:50.32#ibcon#wrote, iclass 14, count 2 2006.257.23:48:50.32#ibcon#about to read 3, iclass 14, count 2 2006.257.23:48:50.34#ibcon#read 3, iclass 14, count 2 2006.257.23:48:50.34#ibcon#about to read 4, iclass 14, count 2 2006.257.23:48:50.34#ibcon#read 4, iclass 14, count 2 2006.257.23:48:50.34#ibcon#about to read 5, iclass 14, count 2 2006.257.23:48:50.34#ibcon#read 5, iclass 14, count 2 2006.257.23:48:50.34#ibcon#about to read 6, iclass 14, count 2 2006.257.23:48:50.34#ibcon#read 6, iclass 14, count 2 2006.257.23:48:50.34#ibcon#end of sib2, iclass 14, count 2 2006.257.23:48:50.34#ibcon#*mode == 0, iclass 14, count 2 2006.257.23:48:50.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.23:48:50.34#ibcon#[25=AT03-08\r\n] 2006.257.23:48:50.34#ibcon#*before write, iclass 14, count 2 2006.257.23:48:50.34#ibcon#enter sib2, iclass 14, count 2 2006.257.23:48:50.34#ibcon#flushed, iclass 14, count 2 2006.257.23:48:50.34#ibcon#about to write, iclass 14, count 2 2006.257.23:48:50.34#ibcon#wrote, iclass 14, count 2 2006.257.23:48:50.34#ibcon#about to read 3, iclass 14, count 2 2006.257.23:48:50.37#ibcon#read 3, iclass 14, count 2 2006.257.23:48:50.37#ibcon#about to read 4, iclass 14, count 2 2006.257.23:48:50.37#ibcon#read 4, iclass 14, count 2 2006.257.23:48:50.37#ibcon#about to read 5, iclass 14, count 2 2006.257.23:48:50.37#ibcon#read 5, iclass 14, count 2 2006.257.23:48:50.37#ibcon#about to read 6, iclass 14, count 2 2006.257.23:48:50.37#ibcon#read 6, iclass 14, count 2 2006.257.23:48:50.37#ibcon#end of sib2, iclass 14, count 2 2006.257.23:48:50.37#ibcon#*after write, iclass 14, count 2 2006.257.23:48:50.37#ibcon#*before return 0, iclass 14, count 2 2006.257.23:48:50.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:50.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:50.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.23:48:50.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:50.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:50.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:50.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:50.49#ibcon#enter wrdev, iclass 14, count 0 2006.257.23:48:50.49#ibcon#first serial, iclass 14, count 0 2006.257.23:48:50.49#ibcon#enter sib2, iclass 14, count 0 2006.257.23:48:50.49#ibcon#flushed, iclass 14, count 0 2006.257.23:48:50.49#ibcon#about to write, iclass 14, count 0 2006.257.23:48:50.49#ibcon#wrote, iclass 14, count 0 2006.257.23:48:50.49#ibcon#about to read 3, iclass 14, count 0 2006.257.23:48:50.51#ibcon#read 3, iclass 14, count 0 2006.257.23:48:50.51#ibcon#about to read 4, iclass 14, count 0 2006.257.23:48:50.51#ibcon#read 4, iclass 14, count 0 2006.257.23:48:50.51#ibcon#about to read 5, iclass 14, count 0 2006.257.23:48:50.51#ibcon#read 5, iclass 14, count 0 2006.257.23:48:50.51#ibcon#about to read 6, iclass 14, count 0 2006.257.23:48:50.51#ibcon#read 6, iclass 14, count 0 2006.257.23:48:50.51#ibcon#end of sib2, iclass 14, count 0 2006.257.23:48:50.51#ibcon#*mode == 0, iclass 14, count 0 2006.257.23:48:50.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.23:48:50.51#ibcon#[25=USB\r\n] 2006.257.23:48:50.51#ibcon#*before write, iclass 14, count 0 2006.257.23:48:50.51#ibcon#enter sib2, iclass 14, count 0 2006.257.23:48:50.51#ibcon#flushed, iclass 14, count 0 2006.257.23:48:50.51#ibcon#about to write, iclass 14, count 0 2006.257.23:48:50.51#ibcon#wrote, iclass 14, count 0 2006.257.23:48:50.51#ibcon#about to read 3, iclass 14, count 0 2006.257.23:48:50.54#ibcon#read 3, iclass 14, count 0 2006.257.23:48:50.54#ibcon#about to read 4, iclass 14, count 0 2006.257.23:48:50.54#ibcon#read 4, iclass 14, count 0 2006.257.23:48:50.54#ibcon#about to read 5, iclass 14, count 0 2006.257.23:48:50.54#ibcon#read 5, iclass 14, count 0 2006.257.23:48:50.54#ibcon#about to read 6, iclass 14, count 0 2006.257.23:48:50.54#ibcon#read 6, iclass 14, count 0 2006.257.23:48:50.54#ibcon#end of sib2, iclass 14, count 0 2006.257.23:48:50.54#ibcon#*after write, iclass 14, count 0 2006.257.23:48:50.54#ibcon#*before return 0, iclass 14, count 0 2006.257.23:48:50.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:50.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:50.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.23:48:50.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.23:48:50.54$vck44/valo=4,624.99 2006.257.23:48:50.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.23:48:50.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.23:48:50.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:50.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:50.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:50.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:50.54#ibcon#enter wrdev, iclass 16, count 0 2006.257.23:48:50.54#ibcon#first serial, iclass 16, count 0 2006.257.23:48:50.54#ibcon#enter sib2, iclass 16, count 0 2006.257.23:48:50.54#ibcon#flushed, iclass 16, count 0 2006.257.23:48:50.54#ibcon#about to write, iclass 16, count 0 2006.257.23:48:50.54#ibcon#wrote, iclass 16, count 0 2006.257.23:48:50.54#ibcon#about to read 3, iclass 16, count 0 2006.257.23:48:50.56#ibcon#read 3, iclass 16, count 0 2006.257.23:48:50.56#ibcon#about to read 4, iclass 16, count 0 2006.257.23:48:50.56#ibcon#read 4, iclass 16, count 0 2006.257.23:48:50.56#ibcon#about to read 5, iclass 16, count 0 2006.257.23:48:50.56#ibcon#read 5, iclass 16, count 0 2006.257.23:48:50.56#ibcon#about to read 6, iclass 16, count 0 2006.257.23:48:50.56#ibcon#read 6, iclass 16, count 0 2006.257.23:48:50.56#ibcon#end of sib2, iclass 16, count 0 2006.257.23:48:50.56#ibcon#*mode == 0, iclass 16, count 0 2006.257.23:48:50.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.23:48:50.56#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:48:50.56#ibcon#*before write, iclass 16, count 0 2006.257.23:48:50.56#ibcon#enter sib2, iclass 16, count 0 2006.257.23:48:50.56#ibcon#flushed, iclass 16, count 0 2006.257.23:48:50.56#ibcon#about to write, iclass 16, count 0 2006.257.23:48:50.56#ibcon#wrote, iclass 16, count 0 2006.257.23:48:50.56#ibcon#about to read 3, iclass 16, count 0 2006.257.23:48:50.60#ibcon#read 3, iclass 16, count 0 2006.257.23:48:50.60#ibcon#about to read 4, iclass 16, count 0 2006.257.23:48:50.60#ibcon#read 4, iclass 16, count 0 2006.257.23:48:50.60#ibcon#about to read 5, iclass 16, count 0 2006.257.23:48:50.60#ibcon#read 5, iclass 16, count 0 2006.257.23:48:50.60#ibcon#about to read 6, iclass 16, count 0 2006.257.23:48:50.60#ibcon#read 6, iclass 16, count 0 2006.257.23:48:50.60#ibcon#end of sib2, iclass 16, count 0 2006.257.23:48:50.60#ibcon#*after write, iclass 16, count 0 2006.257.23:48:50.60#ibcon#*before return 0, iclass 16, count 0 2006.257.23:48:50.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:50.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:50.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.23:48:50.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.23:48:50.60$vck44/va=4,7 2006.257.23:48:50.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.23:48:50.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.23:48:50.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:50.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:50.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:50.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:50.66#ibcon#enter wrdev, iclass 18, count 2 2006.257.23:48:50.66#ibcon#first serial, iclass 18, count 2 2006.257.23:48:50.66#ibcon#enter sib2, iclass 18, count 2 2006.257.23:48:50.66#ibcon#flushed, iclass 18, count 2 2006.257.23:48:50.66#ibcon#about to write, iclass 18, count 2 2006.257.23:48:50.66#ibcon#wrote, iclass 18, count 2 2006.257.23:48:50.66#ibcon#about to read 3, iclass 18, count 2 2006.257.23:48:50.68#ibcon#read 3, iclass 18, count 2 2006.257.23:48:50.68#ibcon#about to read 4, iclass 18, count 2 2006.257.23:48:50.68#ibcon#read 4, iclass 18, count 2 2006.257.23:48:50.68#ibcon#about to read 5, iclass 18, count 2 2006.257.23:48:50.68#ibcon#read 5, iclass 18, count 2 2006.257.23:48:50.68#ibcon#about to read 6, iclass 18, count 2 2006.257.23:48:50.68#ibcon#read 6, iclass 18, count 2 2006.257.23:48:50.68#ibcon#end of sib2, iclass 18, count 2 2006.257.23:48:50.68#ibcon#*mode == 0, iclass 18, count 2 2006.257.23:48:50.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.23:48:50.68#ibcon#[25=AT04-07\r\n] 2006.257.23:48:50.68#ibcon#*before write, iclass 18, count 2 2006.257.23:48:50.68#ibcon#enter sib2, iclass 18, count 2 2006.257.23:48:50.68#ibcon#flushed, iclass 18, count 2 2006.257.23:48:50.68#ibcon#about to write, iclass 18, count 2 2006.257.23:48:50.68#ibcon#wrote, iclass 18, count 2 2006.257.23:48:50.68#ibcon#about to read 3, iclass 18, count 2 2006.257.23:48:50.71#ibcon#read 3, iclass 18, count 2 2006.257.23:48:50.71#ibcon#about to read 4, iclass 18, count 2 2006.257.23:48:50.71#ibcon#read 4, iclass 18, count 2 2006.257.23:48:50.71#ibcon#about to read 5, iclass 18, count 2 2006.257.23:48:50.71#ibcon#read 5, iclass 18, count 2 2006.257.23:48:50.71#ibcon#about to read 6, iclass 18, count 2 2006.257.23:48:50.71#ibcon#read 6, iclass 18, count 2 2006.257.23:48:50.71#ibcon#end of sib2, iclass 18, count 2 2006.257.23:48:50.71#ibcon#*after write, iclass 18, count 2 2006.257.23:48:50.71#ibcon#*before return 0, iclass 18, count 2 2006.257.23:48:50.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:50.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:50.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.23:48:50.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:50.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:50.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:50.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:50.83#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:48:50.83#ibcon#first serial, iclass 18, count 0 2006.257.23:48:50.83#ibcon#enter sib2, iclass 18, count 0 2006.257.23:48:50.83#ibcon#flushed, iclass 18, count 0 2006.257.23:48:50.83#ibcon#about to write, iclass 18, count 0 2006.257.23:48:50.83#ibcon#wrote, iclass 18, count 0 2006.257.23:48:50.83#ibcon#about to read 3, iclass 18, count 0 2006.257.23:48:50.85#ibcon#read 3, iclass 18, count 0 2006.257.23:48:50.85#ibcon#about to read 4, iclass 18, count 0 2006.257.23:48:50.85#ibcon#read 4, iclass 18, count 0 2006.257.23:48:50.85#ibcon#about to read 5, iclass 18, count 0 2006.257.23:48:50.85#ibcon#read 5, iclass 18, count 0 2006.257.23:48:50.85#ibcon#about to read 6, iclass 18, count 0 2006.257.23:48:50.85#ibcon#read 6, iclass 18, count 0 2006.257.23:48:50.85#ibcon#end of sib2, iclass 18, count 0 2006.257.23:48:50.85#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:48:50.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:48:50.85#ibcon#[25=USB\r\n] 2006.257.23:48:50.85#ibcon#*before write, iclass 18, count 0 2006.257.23:48:50.85#ibcon#enter sib2, iclass 18, count 0 2006.257.23:48:50.85#ibcon#flushed, iclass 18, count 0 2006.257.23:48:50.85#ibcon#about to write, iclass 18, count 0 2006.257.23:48:50.85#ibcon#wrote, iclass 18, count 0 2006.257.23:48:50.85#ibcon#about to read 3, iclass 18, count 0 2006.257.23:48:50.88#ibcon#read 3, iclass 18, count 0 2006.257.23:48:50.88#ibcon#about to read 4, iclass 18, count 0 2006.257.23:48:50.88#ibcon#read 4, iclass 18, count 0 2006.257.23:48:50.88#ibcon#about to read 5, iclass 18, count 0 2006.257.23:48:50.88#ibcon#read 5, iclass 18, count 0 2006.257.23:48:50.88#ibcon#about to read 6, iclass 18, count 0 2006.257.23:48:50.88#ibcon#read 6, iclass 18, count 0 2006.257.23:48:50.88#ibcon#end of sib2, iclass 18, count 0 2006.257.23:48:50.88#ibcon#*after write, iclass 18, count 0 2006.257.23:48:50.88#ibcon#*before return 0, iclass 18, count 0 2006.257.23:48:50.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:50.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:50.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:48:50.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:48:50.88$vck44/valo=5,734.99 2006.257.23:48:50.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.23:48:50.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.23:48:50.88#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:50.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:50.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:50.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:50.88#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:48:50.88#ibcon#first serial, iclass 20, count 0 2006.257.23:48:50.88#ibcon#enter sib2, iclass 20, count 0 2006.257.23:48:50.88#ibcon#flushed, iclass 20, count 0 2006.257.23:48:50.88#ibcon#about to write, iclass 20, count 0 2006.257.23:48:50.88#ibcon#wrote, iclass 20, count 0 2006.257.23:48:50.88#ibcon#about to read 3, iclass 20, count 0 2006.257.23:48:50.90#ibcon#read 3, iclass 20, count 0 2006.257.23:48:50.90#ibcon#about to read 4, iclass 20, count 0 2006.257.23:48:50.90#ibcon#read 4, iclass 20, count 0 2006.257.23:48:50.90#ibcon#about to read 5, iclass 20, count 0 2006.257.23:48:50.90#ibcon#read 5, iclass 20, count 0 2006.257.23:48:50.90#ibcon#about to read 6, iclass 20, count 0 2006.257.23:48:50.90#ibcon#read 6, iclass 20, count 0 2006.257.23:48:50.90#ibcon#end of sib2, iclass 20, count 0 2006.257.23:48:50.90#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:48:50.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:48:50.90#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:48:50.90#ibcon#*before write, iclass 20, count 0 2006.257.23:48:50.90#ibcon#enter sib2, iclass 20, count 0 2006.257.23:48:50.90#ibcon#flushed, iclass 20, count 0 2006.257.23:48:50.90#ibcon#about to write, iclass 20, count 0 2006.257.23:48:50.90#ibcon#wrote, iclass 20, count 0 2006.257.23:48:50.90#ibcon#about to read 3, iclass 20, count 0 2006.257.23:48:50.94#ibcon#read 3, iclass 20, count 0 2006.257.23:48:50.94#ibcon#about to read 4, iclass 20, count 0 2006.257.23:48:50.94#ibcon#read 4, iclass 20, count 0 2006.257.23:48:50.94#ibcon#about to read 5, iclass 20, count 0 2006.257.23:48:50.94#ibcon#read 5, iclass 20, count 0 2006.257.23:48:50.94#ibcon#about to read 6, iclass 20, count 0 2006.257.23:48:50.94#ibcon#read 6, iclass 20, count 0 2006.257.23:48:50.94#ibcon#end of sib2, iclass 20, count 0 2006.257.23:48:50.94#ibcon#*after write, iclass 20, count 0 2006.257.23:48:50.94#ibcon#*before return 0, iclass 20, count 0 2006.257.23:48:50.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:50.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:50.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:48:50.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:48:50.94$vck44/va=5,4 2006.257.23:48:50.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.23:48:50.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.23:48:50.94#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:50.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:51.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:51.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:51.00#ibcon#enter wrdev, iclass 22, count 2 2006.257.23:48:51.00#ibcon#first serial, iclass 22, count 2 2006.257.23:48:51.00#ibcon#enter sib2, iclass 22, count 2 2006.257.23:48:51.00#ibcon#flushed, iclass 22, count 2 2006.257.23:48:51.00#ibcon#about to write, iclass 22, count 2 2006.257.23:48:51.00#ibcon#wrote, iclass 22, count 2 2006.257.23:48:51.00#ibcon#about to read 3, iclass 22, count 2 2006.257.23:48:51.02#ibcon#read 3, iclass 22, count 2 2006.257.23:48:51.02#ibcon#about to read 4, iclass 22, count 2 2006.257.23:48:51.02#ibcon#read 4, iclass 22, count 2 2006.257.23:48:51.02#ibcon#about to read 5, iclass 22, count 2 2006.257.23:48:51.02#ibcon#read 5, iclass 22, count 2 2006.257.23:48:51.02#ibcon#about to read 6, iclass 22, count 2 2006.257.23:48:51.02#ibcon#read 6, iclass 22, count 2 2006.257.23:48:51.02#ibcon#end of sib2, iclass 22, count 2 2006.257.23:48:51.02#ibcon#*mode == 0, iclass 22, count 2 2006.257.23:48:51.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.23:48:51.02#ibcon#[25=AT05-04\r\n] 2006.257.23:48:51.02#ibcon#*before write, iclass 22, count 2 2006.257.23:48:51.02#ibcon#enter sib2, iclass 22, count 2 2006.257.23:48:51.02#ibcon#flushed, iclass 22, count 2 2006.257.23:48:51.02#ibcon#about to write, iclass 22, count 2 2006.257.23:48:51.02#ibcon#wrote, iclass 22, count 2 2006.257.23:48:51.02#ibcon#about to read 3, iclass 22, count 2 2006.257.23:48:51.05#ibcon#read 3, iclass 22, count 2 2006.257.23:48:51.05#ibcon#about to read 4, iclass 22, count 2 2006.257.23:48:51.05#ibcon#read 4, iclass 22, count 2 2006.257.23:48:51.05#ibcon#about to read 5, iclass 22, count 2 2006.257.23:48:51.05#ibcon#read 5, iclass 22, count 2 2006.257.23:48:51.05#ibcon#about to read 6, iclass 22, count 2 2006.257.23:48:51.05#ibcon#read 6, iclass 22, count 2 2006.257.23:48:51.05#ibcon#end of sib2, iclass 22, count 2 2006.257.23:48:51.05#ibcon#*after write, iclass 22, count 2 2006.257.23:48:51.05#ibcon#*before return 0, iclass 22, count 2 2006.257.23:48:51.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:51.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:51.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.23:48:51.05#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:51.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:51.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:51.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:51.17#ibcon#enter wrdev, iclass 22, count 0 2006.257.23:48:51.17#ibcon#first serial, iclass 22, count 0 2006.257.23:48:51.17#ibcon#enter sib2, iclass 22, count 0 2006.257.23:48:51.17#ibcon#flushed, iclass 22, count 0 2006.257.23:48:51.17#ibcon#about to write, iclass 22, count 0 2006.257.23:48:51.17#ibcon#wrote, iclass 22, count 0 2006.257.23:48:51.17#ibcon#about to read 3, iclass 22, count 0 2006.257.23:48:51.19#ibcon#read 3, iclass 22, count 0 2006.257.23:48:51.19#ibcon#about to read 4, iclass 22, count 0 2006.257.23:48:51.19#ibcon#read 4, iclass 22, count 0 2006.257.23:48:51.19#ibcon#about to read 5, iclass 22, count 0 2006.257.23:48:51.19#ibcon#read 5, iclass 22, count 0 2006.257.23:48:51.19#ibcon#about to read 6, iclass 22, count 0 2006.257.23:48:51.19#ibcon#read 6, iclass 22, count 0 2006.257.23:48:51.19#ibcon#end of sib2, iclass 22, count 0 2006.257.23:48:51.19#ibcon#*mode == 0, iclass 22, count 0 2006.257.23:48:51.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.23:48:51.19#ibcon#[25=USB\r\n] 2006.257.23:48:51.19#ibcon#*before write, iclass 22, count 0 2006.257.23:48:51.19#ibcon#enter sib2, iclass 22, count 0 2006.257.23:48:51.19#ibcon#flushed, iclass 22, count 0 2006.257.23:48:51.19#ibcon#about to write, iclass 22, count 0 2006.257.23:48:51.19#ibcon#wrote, iclass 22, count 0 2006.257.23:48:51.19#ibcon#about to read 3, iclass 22, count 0 2006.257.23:48:51.22#ibcon#read 3, iclass 22, count 0 2006.257.23:48:51.22#ibcon#about to read 4, iclass 22, count 0 2006.257.23:48:51.22#ibcon#read 4, iclass 22, count 0 2006.257.23:48:51.22#ibcon#about to read 5, iclass 22, count 0 2006.257.23:48:51.22#ibcon#read 5, iclass 22, count 0 2006.257.23:48:51.22#ibcon#about to read 6, iclass 22, count 0 2006.257.23:48:51.22#ibcon#read 6, iclass 22, count 0 2006.257.23:48:51.22#ibcon#end of sib2, iclass 22, count 0 2006.257.23:48:51.22#ibcon#*after write, iclass 22, count 0 2006.257.23:48:51.22#ibcon#*before return 0, iclass 22, count 0 2006.257.23:48:51.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:51.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:51.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.23:48:51.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.23:48:51.22$vck44/valo=6,814.99 2006.257.23:48:51.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.23:48:51.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.23:48:51.22#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:51.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:51.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:51.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:51.22#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:48:51.22#ibcon#first serial, iclass 24, count 0 2006.257.23:48:51.22#ibcon#enter sib2, iclass 24, count 0 2006.257.23:48:51.22#ibcon#flushed, iclass 24, count 0 2006.257.23:48:51.22#ibcon#about to write, iclass 24, count 0 2006.257.23:48:51.22#ibcon#wrote, iclass 24, count 0 2006.257.23:48:51.22#ibcon#about to read 3, iclass 24, count 0 2006.257.23:48:51.24#ibcon#read 3, iclass 24, count 0 2006.257.23:48:51.24#ibcon#about to read 4, iclass 24, count 0 2006.257.23:48:51.24#ibcon#read 4, iclass 24, count 0 2006.257.23:48:51.24#ibcon#about to read 5, iclass 24, count 0 2006.257.23:48:51.24#ibcon#read 5, iclass 24, count 0 2006.257.23:48:51.24#ibcon#about to read 6, iclass 24, count 0 2006.257.23:48:51.24#ibcon#read 6, iclass 24, count 0 2006.257.23:48:51.24#ibcon#end of sib2, iclass 24, count 0 2006.257.23:48:51.24#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:48:51.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:48:51.24#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:48:51.24#ibcon#*before write, iclass 24, count 0 2006.257.23:48:51.24#ibcon#enter sib2, iclass 24, count 0 2006.257.23:48:51.24#ibcon#flushed, iclass 24, count 0 2006.257.23:48:51.24#ibcon#about to write, iclass 24, count 0 2006.257.23:48:51.24#ibcon#wrote, iclass 24, count 0 2006.257.23:48:51.24#ibcon#about to read 3, iclass 24, count 0 2006.257.23:48:51.28#ibcon#read 3, iclass 24, count 0 2006.257.23:48:51.28#ibcon#about to read 4, iclass 24, count 0 2006.257.23:48:51.28#ibcon#read 4, iclass 24, count 0 2006.257.23:48:51.28#ibcon#about to read 5, iclass 24, count 0 2006.257.23:48:51.28#ibcon#read 5, iclass 24, count 0 2006.257.23:48:51.28#ibcon#about to read 6, iclass 24, count 0 2006.257.23:48:51.28#ibcon#read 6, iclass 24, count 0 2006.257.23:48:51.28#ibcon#end of sib2, iclass 24, count 0 2006.257.23:48:51.28#ibcon#*after write, iclass 24, count 0 2006.257.23:48:51.28#ibcon#*before return 0, iclass 24, count 0 2006.257.23:48:51.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:51.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:51.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:48:51.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:48:51.28$vck44/va=6,4 2006.257.23:48:51.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.23:48:51.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.23:48:51.28#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:51.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:51.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:51.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:51.34#ibcon#enter wrdev, iclass 26, count 2 2006.257.23:48:51.34#ibcon#first serial, iclass 26, count 2 2006.257.23:48:51.34#ibcon#enter sib2, iclass 26, count 2 2006.257.23:48:51.34#ibcon#flushed, iclass 26, count 2 2006.257.23:48:51.34#ibcon#about to write, iclass 26, count 2 2006.257.23:48:51.34#ibcon#wrote, iclass 26, count 2 2006.257.23:48:51.34#ibcon#about to read 3, iclass 26, count 2 2006.257.23:48:51.36#ibcon#read 3, iclass 26, count 2 2006.257.23:48:51.36#ibcon#about to read 4, iclass 26, count 2 2006.257.23:48:51.36#ibcon#read 4, iclass 26, count 2 2006.257.23:48:51.36#ibcon#about to read 5, iclass 26, count 2 2006.257.23:48:51.36#ibcon#read 5, iclass 26, count 2 2006.257.23:48:51.36#ibcon#about to read 6, iclass 26, count 2 2006.257.23:48:51.36#ibcon#read 6, iclass 26, count 2 2006.257.23:48:51.36#ibcon#end of sib2, iclass 26, count 2 2006.257.23:48:51.36#ibcon#*mode == 0, iclass 26, count 2 2006.257.23:48:51.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.23:48:51.36#ibcon#[25=AT06-04\r\n] 2006.257.23:48:51.36#ibcon#*before write, iclass 26, count 2 2006.257.23:48:51.36#ibcon#enter sib2, iclass 26, count 2 2006.257.23:48:51.36#ibcon#flushed, iclass 26, count 2 2006.257.23:48:51.36#ibcon#about to write, iclass 26, count 2 2006.257.23:48:51.36#ibcon#wrote, iclass 26, count 2 2006.257.23:48:51.36#ibcon#about to read 3, iclass 26, count 2 2006.257.23:48:51.39#ibcon#read 3, iclass 26, count 2 2006.257.23:48:51.39#ibcon#about to read 4, iclass 26, count 2 2006.257.23:48:51.39#ibcon#read 4, iclass 26, count 2 2006.257.23:48:51.39#ibcon#about to read 5, iclass 26, count 2 2006.257.23:48:51.39#ibcon#read 5, iclass 26, count 2 2006.257.23:48:51.39#ibcon#about to read 6, iclass 26, count 2 2006.257.23:48:51.39#ibcon#read 6, iclass 26, count 2 2006.257.23:48:51.39#ibcon#end of sib2, iclass 26, count 2 2006.257.23:48:51.39#ibcon#*after write, iclass 26, count 2 2006.257.23:48:51.39#ibcon#*before return 0, iclass 26, count 2 2006.257.23:48:51.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:51.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:51.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.23:48:51.39#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:51.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:51.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:51.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:51.51#ibcon#enter wrdev, iclass 26, count 0 2006.257.23:48:51.51#ibcon#first serial, iclass 26, count 0 2006.257.23:48:51.51#ibcon#enter sib2, iclass 26, count 0 2006.257.23:48:51.51#ibcon#flushed, iclass 26, count 0 2006.257.23:48:51.51#ibcon#about to write, iclass 26, count 0 2006.257.23:48:51.51#ibcon#wrote, iclass 26, count 0 2006.257.23:48:51.51#ibcon#about to read 3, iclass 26, count 0 2006.257.23:48:51.53#ibcon#read 3, iclass 26, count 0 2006.257.23:48:51.53#ibcon#about to read 4, iclass 26, count 0 2006.257.23:48:51.53#ibcon#read 4, iclass 26, count 0 2006.257.23:48:51.53#ibcon#about to read 5, iclass 26, count 0 2006.257.23:48:51.53#ibcon#read 5, iclass 26, count 0 2006.257.23:48:51.53#ibcon#about to read 6, iclass 26, count 0 2006.257.23:48:51.53#ibcon#read 6, iclass 26, count 0 2006.257.23:48:51.53#ibcon#end of sib2, iclass 26, count 0 2006.257.23:48:51.53#ibcon#*mode == 0, iclass 26, count 0 2006.257.23:48:51.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.23:48:51.53#ibcon#[25=USB\r\n] 2006.257.23:48:51.53#ibcon#*before write, iclass 26, count 0 2006.257.23:48:51.53#ibcon#enter sib2, iclass 26, count 0 2006.257.23:48:51.53#ibcon#flushed, iclass 26, count 0 2006.257.23:48:51.53#ibcon#about to write, iclass 26, count 0 2006.257.23:48:51.53#ibcon#wrote, iclass 26, count 0 2006.257.23:48:51.53#ibcon#about to read 3, iclass 26, count 0 2006.257.23:48:51.56#ibcon#read 3, iclass 26, count 0 2006.257.23:48:51.56#ibcon#about to read 4, iclass 26, count 0 2006.257.23:48:51.56#ibcon#read 4, iclass 26, count 0 2006.257.23:48:51.56#ibcon#about to read 5, iclass 26, count 0 2006.257.23:48:51.56#ibcon#read 5, iclass 26, count 0 2006.257.23:48:51.56#ibcon#about to read 6, iclass 26, count 0 2006.257.23:48:51.56#ibcon#read 6, iclass 26, count 0 2006.257.23:48:51.56#ibcon#end of sib2, iclass 26, count 0 2006.257.23:48:51.56#ibcon#*after write, iclass 26, count 0 2006.257.23:48:51.56#ibcon#*before return 0, iclass 26, count 0 2006.257.23:48:51.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:51.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:51.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.23:48:51.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.23:48:51.56$vck44/valo=7,864.99 2006.257.23:48:51.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.23:48:51.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.23:48:51.56#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:51.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:51.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:51.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:51.56#ibcon#enter wrdev, iclass 28, count 0 2006.257.23:48:51.56#ibcon#first serial, iclass 28, count 0 2006.257.23:48:51.56#ibcon#enter sib2, iclass 28, count 0 2006.257.23:48:51.56#ibcon#flushed, iclass 28, count 0 2006.257.23:48:51.56#ibcon#about to write, iclass 28, count 0 2006.257.23:48:51.56#ibcon#wrote, iclass 28, count 0 2006.257.23:48:51.56#ibcon#about to read 3, iclass 28, count 0 2006.257.23:48:51.58#ibcon#read 3, iclass 28, count 0 2006.257.23:48:51.58#ibcon#about to read 4, iclass 28, count 0 2006.257.23:48:51.58#ibcon#read 4, iclass 28, count 0 2006.257.23:48:51.58#ibcon#about to read 5, iclass 28, count 0 2006.257.23:48:51.58#ibcon#read 5, iclass 28, count 0 2006.257.23:48:51.58#ibcon#about to read 6, iclass 28, count 0 2006.257.23:48:51.58#ibcon#read 6, iclass 28, count 0 2006.257.23:48:51.58#ibcon#end of sib2, iclass 28, count 0 2006.257.23:48:51.58#ibcon#*mode == 0, iclass 28, count 0 2006.257.23:48:51.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.23:48:51.58#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:48:51.58#ibcon#*before write, iclass 28, count 0 2006.257.23:48:51.58#ibcon#enter sib2, iclass 28, count 0 2006.257.23:48:51.58#ibcon#flushed, iclass 28, count 0 2006.257.23:48:51.58#ibcon#about to write, iclass 28, count 0 2006.257.23:48:51.58#ibcon#wrote, iclass 28, count 0 2006.257.23:48:51.58#ibcon#about to read 3, iclass 28, count 0 2006.257.23:48:51.62#ibcon#read 3, iclass 28, count 0 2006.257.23:48:51.62#ibcon#about to read 4, iclass 28, count 0 2006.257.23:48:51.62#ibcon#read 4, iclass 28, count 0 2006.257.23:48:51.62#ibcon#about to read 5, iclass 28, count 0 2006.257.23:48:51.62#ibcon#read 5, iclass 28, count 0 2006.257.23:48:51.62#ibcon#about to read 6, iclass 28, count 0 2006.257.23:48:51.62#ibcon#read 6, iclass 28, count 0 2006.257.23:48:51.62#ibcon#end of sib2, iclass 28, count 0 2006.257.23:48:51.62#ibcon#*after write, iclass 28, count 0 2006.257.23:48:51.62#ibcon#*before return 0, iclass 28, count 0 2006.257.23:48:51.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:51.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:51.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.23:48:51.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.23:48:51.62$vck44/va=7,4 2006.257.23:48:51.62#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.23:48:51.62#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.23:48:51.62#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:51.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:51.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:51.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:51.68#ibcon#enter wrdev, iclass 30, count 2 2006.257.23:48:51.68#ibcon#first serial, iclass 30, count 2 2006.257.23:48:51.68#ibcon#enter sib2, iclass 30, count 2 2006.257.23:48:51.68#ibcon#flushed, iclass 30, count 2 2006.257.23:48:51.68#ibcon#about to write, iclass 30, count 2 2006.257.23:48:51.68#ibcon#wrote, iclass 30, count 2 2006.257.23:48:51.68#ibcon#about to read 3, iclass 30, count 2 2006.257.23:48:51.70#ibcon#read 3, iclass 30, count 2 2006.257.23:48:51.70#ibcon#about to read 4, iclass 30, count 2 2006.257.23:48:51.70#ibcon#read 4, iclass 30, count 2 2006.257.23:48:51.70#ibcon#about to read 5, iclass 30, count 2 2006.257.23:48:51.70#ibcon#read 5, iclass 30, count 2 2006.257.23:48:51.70#ibcon#about to read 6, iclass 30, count 2 2006.257.23:48:51.70#ibcon#read 6, iclass 30, count 2 2006.257.23:48:51.70#ibcon#end of sib2, iclass 30, count 2 2006.257.23:48:51.70#ibcon#*mode == 0, iclass 30, count 2 2006.257.23:48:51.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.23:48:51.70#ibcon#[25=AT07-04\r\n] 2006.257.23:48:51.70#ibcon#*before write, iclass 30, count 2 2006.257.23:48:51.70#ibcon#enter sib2, iclass 30, count 2 2006.257.23:48:51.70#ibcon#flushed, iclass 30, count 2 2006.257.23:48:51.70#ibcon#about to write, iclass 30, count 2 2006.257.23:48:51.70#ibcon#wrote, iclass 30, count 2 2006.257.23:48:51.70#ibcon#about to read 3, iclass 30, count 2 2006.257.23:48:51.73#ibcon#read 3, iclass 30, count 2 2006.257.23:48:51.73#ibcon#about to read 4, iclass 30, count 2 2006.257.23:48:51.73#ibcon#read 4, iclass 30, count 2 2006.257.23:48:51.73#ibcon#about to read 5, iclass 30, count 2 2006.257.23:48:51.73#ibcon#read 5, iclass 30, count 2 2006.257.23:48:51.73#ibcon#about to read 6, iclass 30, count 2 2006.257.23:48:51.73#ibcon#read 6, iclass 30, count 2 2006.257.23:48:51.73#ibcon#end of sib2, iclass 30, count 2 2006.257.23:48:51.73#ibcon#*after write, iclass 30, count 2 2006.257.23:48:51.73#ibcon#*before return 0, iclass 30, count 2 2006.257.23:48:51.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:51.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:51.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.23:48:51.73#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:51.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:51.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:51.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:51.85#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:48:51.85#ibcon#first serial, iclass 30, count 0 2006.257.23:48:51.85#ibcon#enter sib2, iclass 30, count 0 2006.257.23:48:51.85#ibcon#flushed, iclass 30, count 0 2006.257.23:48:51.85#ibcon#about to write, iclass 30, count 0 2006.257.23:48:51.85#ibcon#wrote, iclass 30, count 0 2006.257.23:48:51.85#ibcon#about to read 3, iclass 30, count 0 2006.257.23:48:51.87#ibcon#read 3, iclass 30, count 0 2006.257.23:48:51.87#ibcon#about to read 4, iclass 30, count 0 2006.257.23:48:51.87#ibcon#read 4, iclass 30, count 0 2006.257.23:48:51.87#ibcon#about to read 5, iclass 30, count 0 2006.257.23:48:51.87#ibcon#read 5, iclass 30, count 0 2006.257.23:48:51.87#ibcon#about to read 6, iclass 30, count 0 2006.257.23:48:51.87#ibcon#read 6, iclass 30, count 0 2006.257.23:48:51.87#ibcon#end of sib2, iclass 30, count 0 2006.257.23:48:51.87#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:48:51.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:48:51.87#ibcon#[25=USB\r\n] 2006.257.23:48:51.87#ibcon#*before write, iclass 30, count 0 2006.257.23:48:51.87#ibcon#enter sib2, iclass 30, count 0 2006.257.23:48:51.87#ibcon#flushed, iclass 30, count 0 2006.257.23:48:51.87#ibcon#about to write, iclass 30, count 0 2006.257.23:48:51.87#ibcon#wrote, iclass 30, count 0 2006.257.23:48:51.87#ibcon#about to read 3, iclass 30, count 0 2006.257.23:48:51.90#ibcon#read 3, iclass 30, count 0 2006.257.23:48:51.90#ibcon#about to read 4, iclass 30, count 0 2006.257.23:48:51.90#ibcon#read 4, iclass 30, count 0 2006.257.23:48:51.90#ibcon#about to read 5, iclass 30, count 0 2006.257.23:48:51.90#ibcon#read 5, iclass 30, count 0 2006.257.23:48:51.90#ibcon#about to read 6, iclass 30, count 0 2006.257.23:48:51.90#ibcon#read 6, iclass 30, count 0 2006.257.23:48:51.90#ibcon#end of sib2, iclass 30, count 0 2006.257.23:48:51.90#ibcon#*after write, iclass 30, count 0 2006.257.23:48:51.90#ibcon#*before return 0, iclass 30, count 0 2006.257.23:48:51.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:51.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:51.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:48:51.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:48:51.90$vck44/valo=8,884.99 2006.257.23:48:51.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.23:48:51.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.23:48:51.90#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:51.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:51.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:51.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:51.90#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:48:51.90#ibcon#first serial, iclass 32, count 0 2006.257.23:48:51.90#ibcon#enter sib2, iclass 32, count 0 2006.257.23:48:51.90#ibcon#flushed, iclass 32, count 0 2006.257.23:48:51.90#ibcon#about to write, iclass 32, count 0 2006.257.23:48:51.90#ibcon#wrote, iclass 32, count 0 2006.257.23:48:51.90#ibcon#about to read 3, iclass 32, count 0 2006.257.23:48:51.92#ibcon#read 3, iclass 32, count 0 2006.257.23:48:51.92#ibcon#about to read 4, iclass 32, count 0 2006.257.23:48:51.92#ibcon#read 4, iclass 32, count 0 2006.257.23:48:51.92#ibcon#about to read 5, iclass 32, count 0 2006.257.23:48:51.92#ibcon#read 5, iclass 32, count 0 2006.257.23:48:51.92#ibcon#about to read 6, iclass 32, count 0 2006.257.23:48:51.92#ibcon#read 6, iclass 32, count 0 2006.257.23:48:51.92#ibcon#end of sib2, iclass 32, count 0 2006.257.23:48:51.92#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:48:51.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:48:51.92#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:48:51.92#ibcon#*before write, iclass 32, count 0 2006.257.23:48:51.92#ibcon#enter sib2, iclass 32, count 0 2006.257.23:48:51.92#ibcon#flushed, iclass 32, count 0 2006.257.23:48:51.92#ibcon#about to write, iclass 32, count 0 2006.257.23:48:51.92#ibcon#wrote, iclass 32, count 0 2006.257.23:48:51.92#ibcon#about to read 3, iclass 32, count 0 2006.257.23:48:51.96#ibcon#read 3, iclass 32, count 0 2006.257.23:48:51.96#ibcon#about to read 4, iclass 32, count 0 2006.257.23:48:51.96#ibcon#read 4, iclass 32, count 0 2006.257.23:48:51.96#ibcon#about to read 5, iclass 32, count 0 2006.257.23:48:51.96#ibcon#read 5, iclass 32, count 0 2006.257.23:48:51.96#ibcon#about to read 6, iclass 32, count 0 2006.257.23:48:51.96#ibcon#read 6, iclass 32, count 0 2006.257.23:48:51.96#ibcon#end of sib2, iclass 32, count 0 2006.257.23:48:51.96#ibcon#*after write, iclass 32, count 0 2006.257.23:48:51.96#ibcon#*before return 0, iclass 32, count 0 2006.257.23:48:51.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:51.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:51.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:48:51.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:48:51.96$vck44/va=8,4 2006.257.23:48:51.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.257.23:48:51.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.257.23:48:51.96#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:51.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:48:52.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:48:52.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:48:52.02#ibcon#enter wrdev, iclass 34, count 2 2006.257.23:48:52.02#ibcon#first serial, iclass 34, count 2 2006.257.23:48:52.02#ibcon#enter sib2, iclass 34, count 2 2006.257.23:48:52.02#ibcon#flushed, iclass 34, count 2 2006.257.23:48:52.02#ibcon#about to write, iclass 34, count 2 2006.257.23:48:52.02#ibcon#wrote, iclass 34, count 2 2006.257.23:48:52.02#ibcon#about to read 3, iclass 34, count 2 2006.257.23:48:52.04#ibcon#read 3, iclass 34, count 2 2006.257.23:48:52.04#ibcon#about to read 4, iclass 34, count 2 2006.257.23:48:52.04#ibcon#read 4, iclass 34, count 2 2006.257.23:48:52.04#ibcon#about to read 5, iclass 34, count 2 2006.257.23:48:52.04#ibcon#read 5, iclass 34, count 2 2006.257.23:48:52.04#ibcon#about to read 6, iclass 34, count 2 2006.257.23:48:52.04#ibcon#read 6, iclass 34, count 2 2006.257.23:48:52.04#ibcon#end of sib2, iclass 34, count 2 2006.257.23:48:52.04#ibcon#*mode == 0, iclass 34, count 2 2006.257.23:48:52.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.257.23:48:52.04#ibcon#[25=AT08-04\r\n] 2006.257.23:48:52.04#ibcon#*before write, iclass 34, count 2 2006.257.23:48:52.04#ibcon#enter sib2, iclass 34, count 2 2006.257.23:48:52.04#ibcon#flushed, iclass 34, count 2 2006.257.23:48:52.04#ibcon#about to write, iclass 34, count 2 2006.257.23:48:52.04#ibcon#wrote, iclass 34, count 2 2006.257.23:48:52.04#ibcon#about to read 3, iclass 34, count 2 2006.257.23:48:52.07#ibcon#read 3, iclass 34, count 2 2006.257.23:48:52.07#ibcon#about to read 4, iclass 34, count 2 2006.257.23:48:52.07#ibcon#read 4, iclass 34, count 2 2006.257.23:48:52.07#ibcon#about to read 5, iclass 34, count 2 2006.257.23:48:52.07#ibcon#read 5, iclass 34, count 2 2006.257.23:48:52.07#ibcon#about to read 6, iclass 34, count 2 2006.257.23:48:52.07#ibcon#read 6, iclass 34, count 2 2006.257.23:48:52.07#ibcon#end of sib2, iclass 34, count 2 2006.257.23:48:52.07#ibcon#*after write, iclass 34, count 2 2006.257.23:48:52.07#ibcon#*before return 0, iclass 34, count 2 2006.257.23:48:52.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:48:52.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.257.23:48:52.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.257.23:48:52.07#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:52.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:48:52.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:48:52.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:48:52.19#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:48:52.19#ibcon#first serial, iclass 34, count 0 2006.257.23:48:52.19#ibcon#enter sib2, iclass 34, count 0 2006.257.23:48:52.19#ibcon#flushed, iclass 34, count 0 2006.257.23:48:52.19#ibcon#about to write, iclass 34, count 0 2006.257.23:48:52.19#ibcon#wrote, iclass 34, count 0 2006.257.23:48:52.19#ibcon#about to read 3, iclass 34, count 0 2006.257.23:48:52.21#ibcon#read 3, iclass 34, count 0 2006.257.23:48:52.21#ibcon#about to read 4, iclass 34, count 0 2006.257.23:48:52.21#ibcon#read 4, iclass 34, count 0 2006.257.23:48:52.21#ibcon#about to read 5, iclass 34, count 0 2006.257.23:48:52.21#ibcon#read 5, iclass 34, count 0 2006.257.23:48:52.21#ibcon#about to read 6, iclass 34, count 0 2006.257.23:48:52.21#ibcon#read 6, iclass 34, count 0 2006.257.23:48:52.21#ibcon#end of sib2, iclass 34, count 0 2006.257.23:48:52.21#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:48:52.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:48:52.21#ibcon#[25=USB\r\n] 2006.257.23:48:52.21#ibcon#*before write, iclass 34, count 0 2006.257.23:48:52.21#ibcon#enter sib2, iclass 34, count 0 2006.257.23:48:52.21#ibcon#flushed, iclass 34, count 0 2006.257.23:48:52.21#ibcon#about to write, iclass 34, count 0 2006.257.23:48:52.21#ibcon#wrote, iclass 34, count 0 2006.257.23:48:52.21#ibcon#about to read 3, iclass 34, count 0 2006.257.23:48:52.24#ibcon#read 3, iclass 34, count 0 2006.257.23:48:52.24#ibcon#about to read 4, iclass 34, count 0 2006.257.23:48:52.24#ibcon#read 4, iclass 34, count 0 2006.257.23:48:52.24#ibcon#about to read 5, iclass 34, count 0 2006.257.23:48:52.24#ibcon#read 5, iclass 34, count 0 2006.257.23:48:52.24#ibcon#about to read 6, iclass 34, count 0 2006.257.23:48:52.24#ibcon#read 6, iclass 34, count 0 2006.257.23:48:52.24#ibcon#end of sib2, iclass 34, count 0 2006.257.23:48:52.24#ibcon#*after write, iclass 34, count 0 2006.257.23:48:52.24#ibcon#*before return 0, iclass 34, count 0 2006.257.23:48:52.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:48:52.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.257.23:48:52.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:48:52.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:48:52.24$vck44/vblo=1,629.99 2006.257.23:48:52.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.257.23:48:52.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.257.23:48:52.24#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:52.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:48:52.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:48:52.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:48:52.24#ibcon#enter wrdev, iclass 36, count 0 2006.257.23:48:52.24#ibcon#first serial, iclass 36, count 0 2006.257.23:48:52.24#ibcon#enter sib2, iclass 36, count 0 2006.257.23:48:52.24#ibcon#flushed, iclass 36, count 0 2006.257.23:48:52.24#ibcon#about to write, iclass 36, count 0 2006.257.23:48:52.24#ibcon#wrote, iclass 36, count 0 2006.257.23:48:52.24#ibcon#about to read 3, iclass 36, count 0 2006.257.23:48:52.26#ibcon#read 3, iclass 36, count 0 2006.257.23:48:52.26#ibcon#about to read 4, iclass 36, count 0 2006.257.23:48:52.26#ibcon#read 4, iclass 36, count 0 2006.257.23:48:52.26#ibcon#about to read 5, iclass 36, count 0 2006.257.23:48:52.26#ibcon#read 5, iclass 36, count 0 2006.257.23:48:52.26#ibcon#about to read 6, iclass 36, count 0 2006.257.23:48:52.26#ibcon#read 6, iclass 36, count 0 2006.257.23:48:52.26#ibcon#end of sib2, iclass 36, count 0 2006.257.23:48:52.26#ibcon#*mode == 0, iclass 36, count 0 2006.257.23:48:52.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.23:48:52.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:48:52.26#ibcon#*before write, iclass 36, count 0 2006.257.23:48:52.26#ibcon#enter sib2, iclass 36, count 0 2006.257.23:48:52.26#ibcon#flushed, iclass 36, count 0 2006.257.23:48:52.26#ibcon#about to write, iclass 36, count 0 2006.257.23:48:52.26#ibcon#wrote, iclass 36, count 0 2006.257.23:48:52.26#ibcon#about to read 3, iclass 36, count 0 2006.257.23:48:52.30#ibcon#read 3, iclass 36, count 0 2006.257.23:48:52.30#ibcon#about to read 4, iclass 36, count 0 2006.257.23:48:52.30#ibcon#read 4, iclass 36, count 0 2006.257.23:48:52.30#ibcon#about to read 5, iclass 36, count 0 2006.257.23:48:52.30#ibcon#read 5, iclass 36, count 0 2006.257.23:48:52.30#ibcon#about to read 6, iclass 36, count 0 2006.257.23:48:52.30#ibcon#read 6, iclass 36, count 0 2006.257.23:48:52.30#ibcon#end of sib2, iclass 36, count 0 2006.257.23:48:52.30#ibcon#*after write, iclass 36, count 0 2006.257.23:48:52.30#ibcon#*before return 0, iclass 36, count 0 2006.257.23:48:52.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:48:52.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.257.23:48:52.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.23:48:52.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.23:48:52.30$vck44/vb=1,4 2006.257.23:48:52.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.257.23:48:52.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.257.23:48:52.30#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:52.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:48:52.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:48:52.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:48:52.30#ibcon#enter wrdev, iclass 38, count 2 2006.257.23:48:52.30#ibcon#first serial, iclass 38, count 2 2006.257.23:48:52.30#ibcon#enter sib2, iclass 38, count 2 2006.257.23:48:52.30#ibcon#flushed, iclass 38, count 2 2006.257.23:48:52.30#ibcon#about to write, iclass 38, count 2 2006.257.23:48:52.30#ibcon#wrote, iclass 38, count 2 2006.257.23:48:52.30#ibcon#about to read 3, iclass 38, count 2 2006.257.23:48:52.32#ibcon#read 3, iclass 38, count 2 2006.257.23:48:52.32#ibcon#about to read 4, iclass 38, count 2 2006.257.23:48:52.32#ibcon#read 4, iclass 38, count 2 2006.257.23:48:52.32#ibcon#about to read 5, iclass 38, count 2 2006.257.23:48:52.32#ibcon#read 5, iclass 38, count 2 2006.257.23:48:52.32#ibcon#about to read 6, iclass 38, count 2 2006.257.23:48:52.32#ibcon#read 6, iclass 38, count 2 2006.257.23:48:52.32#ibcon#end of sib2, iclass 38, count 2 2006.257.23:48:52.32#ibcon#*mode == 0, iclass 38, count 2 2006.257.23:48:52.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.257.23:48:52.32#ibcon#[27=AT01-04\r\n] 2006.257.23:48:52.32#ibcon#*before write, iclass 38, count 2 2006.257.23:48:52.32#ibcon#enter sib2, iclass 38, count 2 2006.257.23:48:52.32#ibcon#flushed, iclass 38, count 2 2006.257.23:48:52.32#ibcon#about to write, iclass 38, count 2 2006.257.23:48:52.32#ibcon#wrote, iclass 38, count 2 2006.257.23:48:52.32#ibcon#about to read 3, iclass 38, count 2 2006.257.23:48:52.35#ibcon#read 3, iclass 38, count 2 2006.257.23:48:52.35#ibcon#about to read 4, iclass 38, count 2 2006.257.23:48:52.35#ibcon#read 4, iclass 38, count 2 2006.257.23:48:52.35#ibcon#about to read 5, iclass 38, count 2 2006.257.23:48:52.35#ibcon#read 5, iclass 38, count 2 2006.257.23:48:52.35#ibcon#about to read 6, iclass 38, count 2 2006.257.23:48:52.35#ibcon#read 6, iclass 38, count 2 2006.257.23:48:52.35#ibcon#end of sib2, iclass 38, count 2 2006.257.23:48:52.35#ibcon#*after write, iclass 38, count 2 2006.257.23:48:52.35#ibcon#*before return 0, iclass 38, count 2 2006.257.23:48:52.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:48:52.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.257.23:48:52.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.257.23:48:52.35#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:52.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:48:52.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:48:52.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:48:52.47#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:48:52.47#ibcon#first serial, iclass 38, count 0 2006.257.23:48:52.47#ibcon#enter sib2, iclass 38, count 0 2006.257.23:48:52.47#ibcon#flushed, iclass 38, count 0 2006.257.23:48:52.47#ibcon#about to write, iclass 38, count 0 2006.257.23:48:52.47#ibcon#wrote, iclass 38, count 0 2006.257.23:48:52.47#ibcon#about to read 3, iclass 38, count 0 2006.257.23:48:52.49#ibcon#read 3, iclass 38, count 0 2006.257.23:48:52.49#ibcon#about to read 4, iclass 38, count 0 2006.257.23:48:52.49#ibcon#read 4, iclass 38, count 0 2006.257.23:48:52.49#ibcon#about to read 5, iclass 38, count 0 2006.257.23:48:52.49#ibcon#read 5, iclass 38, count 0 2006.257.23:48:52.49#ibcon#about to read 6, iclass 38, count 0 2006.257.23:48:52.49#ibcon#read 6, iclass 38, count 0 2006.257.23:48:52.49#ibcon#end of sib2, iclass 38, count 0 2006.257.23:48:52.49#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:48:52.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:48:52.49#ibcon#[27=USB\r\n] 2006.257.23:48:52.49#ibcon#*before write, iclass 38, count 0 2006.257.23:48:52.49#ibcon#enter sib2, iclass 38, count 0 2006.257.23:48:52.49#ibcon#flushed, iclass 38, count 0 2006.257.23:48:52.49#ibcon#about to write, iclass 38, count 0 2006.257.23:48:52.49#ibcon#wrote, iclass 38, count 0 2006.257.23:48:52.49#ibcon#about to read 3, iclass 38, count 0 2006.257.23:48:52.52#ibcon#read 3, iclass 38, count 0 2006.257.23:48:52.52#ibcon#about to read 4, iclass 38, count 0 2006.257.23:48:52.52#ibcon#read 4, iclass 38, count 0 2006.257.23:48:52.52#ibcon#about to read 5, iclass 38, count 0 2006.257.23:48:52.52#ibcon#read 5, iclass 38, count 0 2006.257.23:48:52.52#ibcon#about to read 6, iclass 38, count 0 2006.257.23:48:52.52#ibcon#read 6, iclass 38, count 0 2006.257.23:48:52.52#ibcon#end of sib2, iclass 38, count 0 2006.257.23:48:52.52#ibcon#*after write, iclass 38, count 0 2006.257.23:48:52.52#ibcon#*before return 0, iclass 38, count 0 2006.257.23:48:52.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:48:52.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.257.23:48:52.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:48:52.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:48:52.52$vck44/vblo=2,634.99 2006.257.23:48:52.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.257.23:48:52.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.257.23:48:52.52#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:52.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:52.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:52.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:52.52#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:48:52.52#ibcon#first serial, iclass 40, count 0 2006.257.23:48:52.52#ibcon#enter sib2, iclass 40, count 0 2006.257.23:48:52.52#ibcon#flushed, iclass 40, count 0 2006.257.23:48:52.52#ibcon#about to write, iclass 40, count 0 2006.257.23:48:52.52#ibcon#wrote, iclass 40, count 0 2006.257.23:48:52.52#ibcon#about to read 3, iclass 40, count 0 2006.257.23:48:52.54#ibcon#read 3, iclass 40, count 0 2006.257.23:48:52.54#ibcon#about to read 4, iclass 40, count 0 2006.257.23:48:52.54#ibcon#read 4, iclass 40, count 0 2006.257.23:48:52.54#ibcon#about to read 5, iclass 40, count 0 2006.257.23:48:52.54#ibcon#read 5, iclass 40, count 0 2006.257.23:48:52.54#ibcon#about to read 6, iclass 40, count 0 2006.257.23:48:52.54#ibcon#read 6, iclass 40, count 0 2006.257.23:48:52.54#ibcon#end of sib2, iclass 40, count 0 2006.257.23:48:52.54#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:48:52.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:48:52.54#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:48:52.54#ibcon#*before write, iclass 40, count 0 2006.257.23:48:52.54#ibcon#enter sib2, iclass 40, count 0 2006.257.23:48:52.54#ibcon#flushed, iclass 40, count 0 2006.257.23:48:52.54#ibcon#about to write, iclass 40, count 0 2006.257.23:48:52.54#ibcon#wrote, iclass 40, count 0 2006.257.23:48:52.54#ibcon#about to read 3, iclass 40, count 0 2006.257.23:48:52.58#ibcon#read 3, iclass 40, count 0 2006.257.23:48:52.58#ibcon#about to read 4, iclass 40, count 0 2006.257.23:48:52.58#ibcon#read 4, iclass 40, count 0 2006.257.23:48:52.58#ibcon#about to read 5, iclass 40, count 0 2006.257.23:48:52.58#ibcon#read 5, iclass 40, count 0 2006.257.23:48:52.58#ibcon#about to read 6, iclass 40, count 0 2006.257.23:48:52.58#ibcon#read 6, iclass 40, count 0 2006.257.23:48:52.58#ibcon#end of sib2, iclass 40, count 0 2006.257.23:48:52.58#ibcon#*after write, iclass 40, count 0 2006.257.23:48:52.58#ibcon#*before return 0, iclass 40, count 0 2006.257.23:48:52.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:52.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.257.23:48:52.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:48:52.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:48:52.58$vck44/vb=2,5 2006.257.23:48:52.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.257.23:48:52.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.257.23:48:52.58#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:52.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:52.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:52.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:52.64#ibcon#enter wrdev, iclass 4, count 2 2006.257.23:48:52.64#ibcon#first serial, iclass 4, count 2 2006.257.23:48:52.64#ibcon#enter sib2, iclass 4, count 2 2006.257.23:48:52.64#ibcon#flushed, iclass 4, count 2 2006.257.23:48:52.64#ibcon#about to write, iclass 4, count 2 2006.257.23:48:52.64#ibcon#wrote, iclass 4, count 2 2006.257.23:48:52.64#ibcon#about to read 3, iclass 4, count 2 2006.257.23:48:52.66#ibcon#read 3, iclass 4, count 2 2006.257.23:48:52.66#ibcon#about to read 4, iclass 4, count 2 2006.257.23:48:52.66#ibcon#read 4, iclass 4, count 2 2006.257.23:48:52.66#ibcon#about to read 5, iclass 4, count 2 2006.257.23:48:52.66#ibcon#read 5, iclass 4, count 2 2006.257.23:48:52.66#ibcon#about to read 6, iclass 4, count 2 2006.257.23:48:52.66#ibcon#read 6, iclass 4, count 2 2006.257.23:48:52.66#ibcon#end of sib2, iclass 4, count 2 2006.257.23:48:52.66#ibcon#*mode == 0, iclass 4, count 2 2006.257.23:48:52.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.257.23:48:52.66#ibcon#[27=AT02-05\r\n] 2006.257.23:48:52.66#ibcon#*before write, iclass 4, count 2 2006.257.23:48:52.66#ibcon#enter sib2, iclass 4, count 2 2006.257.23:48:52.66#ibcon#flushed, iclass 4, count 2 2006.257.23:48:52.66#ibcon#about to write, iclass 4, count 2 2006.257.23:48:52.66#ibcon#wrote, iclass 4, count 2 2006.257.23:48:52.66#ibcon#about to read 3, iclass 4, count 2 2006.257.23:48:52.69#ibcon#read 3, iclass 4, count 2 2006.257.23:48:52.69#ibcon#about to read 4, iclass 4, count 2 2006.257.23:48:52.69#ibcon#read 4, iclass 4, count 2 2006.257.23:48:52.69#ibcon#about to read 5, iclass 4, count 2 2006.257.23:48:52.69#ibcon#read 5, iclass 4, count 2 2006.257.23:48:52.69#ibcon#about to read 6, iclass 4, count 2 2006.257.23:48:52.69#ibcon#read 6, iclass 4, count 2 2006.257.23:48:52.69#ibcon#end of sib2, iclass 4, count 2 2006.257.23:48:52.69#ibcon#*after write, iclass 4, count 2 2006.257.23:48:52.69#ibcon#*before return 0, iclass 4, count 2 2006.257.23:48:52.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:52.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.257.23:48:52.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.257.23:48:52.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:52.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:52.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:52.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:52.81#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:48:52.81#ibcon#first serial, iclass 4, count 0 2006.257.23:48:52.81#ibcon#enter sib2, iclass 4, count 0 2006.257.23:48:52.81#ibcon#flushed, iclass 4, count 0 2006.257.23:48:52.81#ibcon#about to write, iclass 4, count 0 2006.257.23:48:52.81#ibcon#wrote, iclass 4, count 0 2006.257.23:48:52.81#ibcon#about to read 3, iclass 4, count 0 2006.257.23:48:52.83#ibcon#read 3, iclass 4, count 0 2006.257.23:48:52.83#ibcon#about to read 4, iclass 4, count 0 2006.257.23:48:52.83#ibcon#read 4, iclass 4, count 0 2006.257.23:48:52.83#ibcon#about to read 5, iclass 4, count 0 2006.257.23:48:52.83#ibcon#read 5, iclass 4, count 0 2006.257.23:48:52.83#ibcon#about to read 6, iclass 4, count 0 2006.257.23:48:52.83#ibcon#read 6, iclass 4, count 0 2006.257.23:48:52.83#ibcon#end of sib2, iclass 4, count 0 2006.257.23:48:52.83#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:48:52.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:48:52.83#ibcon#[27=USB\r\n] 2006.257.23:48:52.83#ibcon#*before write, iclass 4, count 0 2006.257.23:48:52.83#ibcon#enter sib2, iclass 4, count 0 2006.257.23:48:52.83#ibcon#flushed, iclass 4, count 0 2006.257.23:48:52.83#ibcon#about to write, iclass 4, count 0 2006.257.23:48:52.83#ibcon#wrote, iclass 4, count 0 2006.257.23:48:52.83#ibcon#about to read 3, iclass 4, count 0 2006.257.23:48:52.86#ibcon#read 3, iclass 4, count 0 2006.257.23:48:52.86#ibcon#about to read 4, iclass 4, count 0 2006.257.23:48:52.86#ibcon#read 4, iclass 4, count 0 2006.257.23:48:52.86#ibcon#about to read 5, iclass 4, count 0 2006.257.23:48:52.86#ibcon#read 5, iclass 4, count 0 2006.257.23:48:52.86#ibcon#about to read 6, iclass 4, count 0 2006.257.23:48:52.86#ibcon#read 6, iclass 4, count 0 2006.257.23:48:52.86#ibcon#end of sib2, iclass 4, count 0 2006.257.23:48:52.86#ibcon#*after write, iclass 4, count 0 2006.257.23:48:52.86#ibcon#*before return 0, iclass 4, count 0 2006.257.23:48:52.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:52.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.257.23:48:52.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:48:52.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:48:52.86$vck44/vblo=3,649.99 2006.257.23:48:52.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.257.23:48:52.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.257.23:48:52.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:52.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:52.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:52.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:52.86#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:48:52.86#ibcon#first serial, iclass 6, count 0 2006.257.23:48:52.86#ibcon#enter sib2, iclass 6, count 0 2006.257.23:48:52.86#ibcon#flushed, iclass 6, count 0 2006.257.23:48:52.86#ibcon#about to write, iclass 6, count 0 2006.257.23:48:52.86#ibcon#wrote, iclass 6, count 0 2006.257.23:48:52.86#ibcon#about to read 3, iclass 6, count 0 2006.257.23:48:52.88#ibcon#read 3, iclass 6, count 0 2006.257.23:48:52.88#ibcon#about to read 4, iclass 6, count 0 2006.257.23:48:52.88#ibcon#read 4, iclass 6, count 0 2006.257.23:48:52.88#ibcon#about to read 5, iclass 6, count 0 2006.257.23:48:52.88#ibcon#read 5, iclass 6, count 0 2006.257.23:48:52.88#ibcon#about to read 6, iclass 6, count 0 2006.257.23:48:52.88#ibcon#read 6, iclass 6, count 0 2006.257.23:48:52.88#ibcon#end of sib2, iclass 6, count 0 2006.257.23:48:52.88#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:48:52.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:48:52.88#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:48:52.88#ibcon#*before write, iclass 6, count 0 2006.257.23:48:52.88#ibcon#enter sib2, iclass 6, count 0 2006.257.23:48:52.88#ibcon#flushed, iclass 6, count 0 2006.257.23:48:52.88#ibcon#about to write, iclass 6, count 0 2006.257.23:48:52.88#ibcon#wrote, iclass 6, count 0 2006.257.23:48:52.88#ibcon#about to read 3, iclass 6, count 0 2006.257.23:48:52.92#ibcon#read 3, iclass 6, count 0 2006.257.23:48:52.92#ibcon#about to read 4, iclass 6, count 0 2006.257.23:48:52.92#ibcon#read 4, iclass 6, count 0 2006.257.23:48:52.92#ibcon#about to read 5, iclass 6, count 0 2006.257.23:48:52.92#ibcon#read 5, iclass 6, count 0 2006.257.23:48:52.92#ibcon#about to read 6, iclass 6, count 0 2006.257.23:48:52.92#ibcon#read 6, iclass 6, count 0 2006.257.23:48:52.92#ibcon#end of sib2, iclass 6, count 0 2006.257.23:48:52.92#ibcon#*after write, iclass 6, count 0 2006.257.23:48:52.92#ibcon#*before return 0, iclass 6, count 0 2006.257.23:48:52.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:52.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.257.23:48:52.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:48:52.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:48:52.92$vck44/vb=3,4 2006.257.23:48:52.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.257.23:48:52.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.257.23:48:52.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:52.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:52.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:52.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:52.98#ibcon#enter wrdev, iclass 10, count 2 2006.257.23:48:52.98#ibcon#first serial, iclass 10, count 2 2006.257.23:48:52.98#ibcon#enter sib2, iclass 10, count 2 2006.257.23:48:52.98#ibcon#flushed, iclass 10, count 2 2006.257.23:48:52.98#ibcon#about to write, iclass 10, count 2 2006.257.23:48:52.98#ibcon#wrote, iclass 10, count 2 2006.257.23:48:52.98#ibcon#about to read 3, iclass 10, count 2 2006.257.23:48:53.00#ibcon#read 3, iclass 10, count 2 2006.257.23:48:53.00#ibcon#about to read 4, iclass 10, count 2 2006.257.23:48:53.00#ibcon#read 4, iclass 10, count 2 2006.257.23:48:53.00#ibcon#about to read 5, iclass 10, count 2 2006.257.23:48:53.00#ibcon#read 5, iclass 10, count 2 2006.257.23:48:53.00#ibcon#about to read 6, iclass 10, count 2 2006.257.23:48:53.00#ibcon#read 6, iclass 10, count 2 2006.257.23:48:53.00#ibcon#end of sib2, iclass 10, count 2 2006.257.23:48:53.00#ibcon#*mode == 0, iclass 10, count 2 2006.257.23:48:53.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.257.23:48:53.00#ibcon#[27=AT03-04\r\n] 2006.257.23:48:53.00#ibcon#*before write, iclass 10, count 2 2006.257.23:48:53.00#ibcon#enter sib2, iclass 10, count 2 2006.257.23:48:53.00#ibcon#flushed, iclass 10, count 2 2006.257.23:48:53.00#ibcon#about to write, iclass 10, count 2 2006.257.23:48:53.00#ibcon#wrote, iclass 10, count 2 2006.257.23:48:53.00#ibcon#about to read 3, iclass 10, count 2 2006.257.23:48:53.03#ibcon#read 3, iclass 10, count 2 2006.257.23:48:53.03#ibcon#about to read 4, iclass 10, count 2 2006.257.23:48:53.03#ibcon#read 4, iclass 10, count 2 2006.257.23:48:53.03#ibcon#about to read 5, iclass 10, count 2 2006.257.23:48:53.03#ibcon#read 5, iclass 10, count 2 2006.257.23:48:53.03#ibcon#about to read 6, iclass 10, count 2 2006.257.23:48:53.03#ibcon#read 6, iclass 10, count 2 2006.257.23:48:53.03#ibcon#end of sib2, iclass 10, count 2 2006.257.23:48:53.03#ibcon#*after write, iclass 10, count 2 2006.257.23:48:53.03#ibcon#*before return 0, iclass 10, count 2 2006.257.23:48:53.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:53.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.257.23:48:53.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.257.23:48:53.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:53.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:53.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:53.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:53.15#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:48:53.15#ibcon#first serial, iclass 10, count 0 2006.257.23:48:53.15#ibcon#enter sib2, iclass 10, count 0 2006.257.23:48:53.15#ibcon#flushed, iclass 10, count 0 2006.257.23:48:53.15#ibcon#about to write, iclass 10, count 0 2006.257.23:48:53.15#ibcon#wrote, iclass 10, count 0 2006.257.23:48:53.15#ibcon#about to read 3, iclass 10, count 0 2006.257.23:48:53.17#ibcon#read 3, iclass 10, count 0 2006.257.23:48:53.17#ibcon#about to read 4, iclass 10, count 0 2006.257.23:48:53.17#ibcon#read 4, iclass 10, count 0 2006.257.23:48:53.17#ibcon#about to read 5, iclass 10, count 0 2006.257.23:48:53.17#ibcon#read 5, iclass 10, count 0 2006.257.23:48:53.17#ibcon#about to read 6, iclass 10, count 0 2006.257.23:48:53.17#ibcon#read 6, iclass 10, count 0 2006.257.23:48:53.17#ibcon#end of sib2, iclass 10, count 0 2006.257.23:48:53.17#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:48:53.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:48:53.17#ibcon#[27=USB\r\n] 2006.257.23:48:53.17#ibcon#*before write, iclass 10, count 0 2006.257.23:48:53.17#ibcon#enter sib2, iclass 10, count 0 2006.257.23:48:53.17#ibcon#flushed, iclass 10, count 0 2006.257.23:48:53.17#ibcon#about to write, iclass 10, count 0 2006.257.23:48:53.17#ibcon#wrote, iclass 10, count 0 2006.257.23:48:53.17#ibcon#about to read 3, iclass 10, count 0 2006.257.23:48:53.20#ibcon#read 3, iclass 10, count 0 2006.257.23:48:53.20#ibcon#about to read 4, iclass 10, count 0 2006.257.23:48:53.20#ibcon#read 4, iclass 10, count 0 2006.257.23:48:53.20#ibcon#about to read 5, iclass 10, count 0 2006.257.23:48:53.20#ibcon#read 5, iclass 10, count 0 2006.257.23:48:53.20#ibcon#about to read 6, iclass 10, count 0 2006.257.23:48:53.20#ibcon#read 6, iclass 10, count 0 2006.257.23:48:53.20#ibcon#end of sib2, iclass 10, count 0 2006.257.23:48:53.20#ibcon#*after write, iclass 10, count 0 2006.257.23:48:53.20#ibcon#*before return 0, iclass 10, count 0 2006.257.23:48:53.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:53.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.257.23:48:53.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:48:53.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:48:53.20$vck44/vblo=4,679.99 2006.257.23:48:53.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.257.23:48:53.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.257.23:48:53.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:53.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:53.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:53.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:53.20#ibcon#enter wrdev, iclass 12, count 0 2006.257.23:48:53.20#ibcon#first serial, iclass 12, count 0 2006.257.23:48:53.20#ibcon#enter sib2, iclass 12, count 0 2006.257.23:48:53.20#ibcon#flushed, iclass 12, count 0 2006.257.23:48:53.20#ibcon#about to write, iclass 12, count 0 2006.257.23:48:53.20#ibcon#wrote, iclass 12, count 0 2006.257.23:48:53.20#ibcon#about to read 3, iclass 12, count 0 2006.257.23:48:53.22#ibcon#read 3, iclass 12, count 0 2006.257.23:48:53.22#ibcon#about to read 4, iclass 12, count 0 2006.257.23:48:53.22#ibcon#read 4, iclass 12, count 0 2006.257.23:48:53.22#ibcon#about to read 5, iclass 12, count 0 2006.257.23:48:53.22#ibcon#read 5, iclass 12, count 0 2006.257.23:48:53.22#ibcon#about to read 6, iclass 12, count 0 2006.257.23:48:53.22#ibcon#read 6, iclass 12, count 0 2006.257.23:48:53.22#ibcon#end of sib2, iclass 12, count 0 2006.257.23:48:53.22#ibcon#*mode == 0, iclass 12, count 0 2006.257.23:48:53.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.23:48:53.22#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:48:53.22#ibcon#*before write, iclass 12, count 0 2006.257.23:48:53.22#ibcon#enter sib2, iclass 12, count 0 2006.257.23:48:53.22#ibcon#flushed, iclass 12, count 0 2006.257.23:48:53.22#ibcon#about to write, iclass 12, count 0 2006.257.23:48:53.22#ibcon#wrote, iclass 12, count 0 2006.257.23:48:53.22#ibcon#about to read 3, iclass 12, count 0 2006.257.23:48:53.26#ibcon#read 3, iclass 12, count 0 2006.257.23:48:53.26#ibcon#about to read 4, iclass 12, count 0 2006.257.23:48:53.26#ibcon#read 4, iclass 12, count 0 2006.257.23:48:53.26#ibcon#about to read 5, iclass 12, count 0 2006.257.23:48:53.26#ibcon#read 5, iclass 12, count 0 2006.257.23:48:53.26#ibcon#about to read 6, iclass 12, count 0 2006.257.23:48:53.26#ibcon#read 6, iclass 12, count 0 2006.257.23:48:53.26#ibcon#end of sib2, iclass 12, count 0 2006.257.23:48:53.26#ibcon#*after write, iclass 12, count 0 2006.257.23:48:53.26#ibcon#*before return 0, iclass 12, count 0 2006.257.23:48:53.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:53.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.257.23:48:53.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.23:48:53.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.23:48:53.26$vck44/vb=4,5 2006.257.23:48:53.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.257.23:48:53.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.257.23:48:53.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:53.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:53.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:53.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:53.32#ibcon#enter wrdev, iclass 14, count 2 2006.257.23:48:53.32#ibcon#first serial, iclass 14, count 2 2006.257.23:48:53.32#ibcon#enter sib2, iclass 14, count 2 2006.257.23:48:53.32#ibcon#flushed, iclass 14, count 2 2006.257.23:48:53.32#ibcon#about to write, iclass 14, count 2 2006.257.23:48:53.32#ibcon#wrote, iclass 14, count 2 2006.257.23:48:53.32#ibcon#about to read 3, iclass 14, count 2 2006.257.23:48:53.34#ibcon#read 3, iclass 14, count 2 2006.257.23:48:53.34#ibcon#about to read 4, iclass 14, count 2 2006.257.23:48:53.34#ibcon#read 4, iclass 14, count 2 2006.257.23:48:53.34#ibcon#about to read 5, iclass 14, count 2 2006.257.23:48:53.34#ibcon#read 5, iclass 14, count 2 2006.257.23:48:53.34#ibcon#about to read 6, iclass 14, count 2 2006.257.23:48:53.34#ibcon#read 6, iclass 14, count 2 2006.257.23:48:53.34#ibcon#end of sib2, iclass 14, count 2 2006.257.23:48:53.34#ibcon#*mode == 0, iclass 14, count 2 2006.257.23:48:53.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.257.23:48:53.34#ibcon#[27=AT04-05\r\n] 2006.257.23:48:53.34#ibcon#*before write, iclass 14, count 2 2006.257.23:48:53.34#ibcon#enter sib2, iclass 14, count 2 2006.257.23:48:53.34#ibcon#flushed, iclass 14, count 2 2006.257.23:48:53.34#ibcon#about to write, iclass 14, count 2 2006.257.23:48:53.34#ibcon#wrote, iclass 14, count 2 2006.257.23:48:53.34#ibcon#about to read 3, iclass 14, count 2 2006.257.23:48:53.37#ibcon#read 3, iclass 14, count 2 2006.257.23:48:53.37#ibcon#about to read 4, iclass 14, count 2 2006.257.23:48:53.37#ibcon#read 4, iclass 14, count 2 2006.257.23:48:53.37#ibcon#about to read 5, iclass 14, count 2 2006.257.23:48:53.37#ibcon#read 5, iclass 14, count 2 2006.257.23:48:53.37#ibcon#about to read 6, iclass 14, count 2 2006.257.23:48:53.37#ibcon#read 6, iclass 14, count 2 2006.257.23:48:53.37#ibcon#end of sib2, iclass 14, count 2 2006.257.23:48:53.37#ibcon#*after write, iclass 14, count 2 2006.257.23:48:53.37#ibcon#*before return 0, iclass 14, count 2 2006.257.23:48:53.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:53.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.257.23:48:53.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.257.23:48:53.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:53.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:53.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:53.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:53.49#ibcon#enter wrdev, iclass 14, count 0 2006.257.23:48:53.49#ibcon#first serial, iclass 14, count 0 2006.257.23:48:53.49#ibcon#enter sib2, iclass 14, count 0 2006.257.23:48:53.49#ibcon#flushed, iclass 14, count 0 2006.257.23:48:53.49#ibcon#about to write, iclass 14, count 0 2006.257.23:48:53.49#ibcon#wrote, iclass 14, count 0 2006.257.23:48:53.49#ibcon#about to read 3, iclass 14, count 0 2006.257.23:48:53.51#ibcon#read 3, iclass 14, count 0 2006.257.23:48:53.51#ibcon#about to read 4, iclass 14, count 0 2006.257.23:48:53.51#ibcon#read 4, iclass 14, count 0 2006.257.23:48:53.51#ibcon#about to read 5, iclass 14, count 0 2006.257.23:48:53.51#ibcon#read 5, iclass 14, count 0 2006.257.23:48:53.51#ibcon#about to read 6, iclass 14, count 0 2006.257.23:48:53.51#ibcon#read 6, iclass 14, count 0 2006.257.23:48:53.51#ibcon#end of sib2, iclass 14, count 0 2006.257.23:48:53.51#ibcon#*mode == 0, iclass 14, count 0 2006.257.23:48:53.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.23:48:53.51#ibcon#[27=USB\r\n] 2006.257.23:48:53.51#ibcon#*before write, iclass 14, count 0 2006.257.23:48:53.51#ibcon#enter sib2, iclass 14, count 0 2006.257.23:48:53.51#ibcon#flushed, iclass 14, count 0 2006.257.23:48:53.51#ibcon#about to write, iclass 14, count 0 2006.257.23:48:53.51#ibcon#wrote, iclass 14, count 0 2006.257.23:48:53.51#ibcon#about to read 3, iclass 14, count 0 2006.257.23:48:53.54#ibcon#read 3, iclass 14, count 0 2006.257.23:48:53.54#ibcon#about to read 4, iclass 14, count 0 2006.257.23:48:53.54#ibcon#read 4, iclass 14, count 0 2006.257.23:48:53.54#ibcon#about to read 5, iclass 14, count 0 2006.257.23:48:53.54#ibcon#read 5, iclass 14, count 0 2006.257.23:48:53.54#ibcon#about to read 6, iclass 14, count 0 2006.257.23:48:53.54#ibcon#read 6, iclass 14, count 0 2006.257.23:48:53.54#ibcon#end of sib2, iclass 14, count 0 2006.257.23:48:53.54#ibcon#*after write, iclass 14, count 0 2006.257.23:48:53.54#ibcon#*before return 0, iclass 14, count 0 2006.257.23:48:53.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:53.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.257.23:48:53.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.23:48:53.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.23:48:53.54$vck44/vblo=5,709.99 2006.257.23:48:53.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.257.23:48:53.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.257.23:48:53.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:53.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:53.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:53.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:53.54#ibcon#enter wrdev, iclass 16, count 0 2006.257.23:48:53.54#ibcon#first serial, iclass 16, count 0 2006.257.23:48:53.54#ibcon#enter sib2, iclass 16, count 0 2006.257.23:48:53.54#ibcon#flushed, iclass 16, count 0 2006.257.23:48:53.54#ibcon#about to write, iclass 16, count 0 2006.257.23:48:53.54#ibcon#wrote, iclass 16, count 0 2006.257.23:48:53.54#ibcon#about to read 3, iclass 16, count 0 2006.257.23:48:53.56#ibcon#read 3, iclass 16, count 0 2006.257.23:48:53.56#ibcon#about to read 4, iclass 16, count 0 2006.257.23:48:53.56#ibcon#read 4, iclass 16, count 0 2006.257.23:48:53.56#ibcon#about to read 5, iclass 16, count 0 2006.257.23:48:53.56#ibcon#read 5, iclass 16, count 0 2006.257.23:48:53.56#ibcon#about to read 6, iclass 16, count 0 2006.257.23:48:53.56#ibcon#read 6, iclass 16, count 0 2006.257.23:48:53.56#ibcon#end of sib2, iclass 16, count 0 2006.257.23:48:53.56#ibcon#*mode == 0, iclass 16, count 0 2006.257.23:48:53.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.23:48:53.56#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:48:53.56#ibcon#*before write, iclass 16, count 0 2006.257.23:48:53.56#ibcon#enter sib2, iclass 16, count 0 2006.257.23:48:53.56#ibcon#flushed, iclass 16, count 0 2006.257.23:48:53.56#ibcon#about to write, iclass 16, count 0 2006.257.23:48:53.56#ibcon#wrote, iclass 16, count 0 2006.257.23:48:53.56#ibcon#about to read 3, iclass 16, count 0 2006.257.23:48:53.60#ibcon#read 3, iclass 16, count 0 2006.257.23:48:53.60#ibcon#about to read 4, iclass 16, count 0 2006.257.23:48:53.60#ibcon#read 4, iclass 16, count 0 2006.257.23:48:53.60#ibcon#about to read 5, iclass 16, count 0 2006.257.23:48:53.60#ibcon#read 5, iclass 16, count 0 2006.257.23:48:53.60#ibcon#about to read 6, iclass 16, count 0 2006.257.23:48:53.60#ibcon#read 6, iclass 16, count 0 2006.257.23:48:53.60#ibcon#end of sib2, iclass 16, count 0 2006.257.23:48:53.60#ibcon#*after write, iclass 16, count 0 2006.257.23:48:53.60#ibcon#*before return 0, iclass 16, count 0 2006.257.23:48:53.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:53.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.257.23:48:53.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.23:48:53.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.23:48:53.60$vck44/vb=5,4 2006.257.23:48:53.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.257.23:48:53.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.257.23:48:53.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:53.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:53.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:53.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:53.66#ibcon#enter wrdev, iclass 18, count 2 2006.257.23:48:53.66#ibcon#first serial, iclass 18, count 2 2006.257.23:48:53.66#ibcon#enter sib2, iclass 18, count 2 2006.257.23:48:53.66#ibcon#flushed, iclass 18, count 2 2006.257.23:48:53.66#ibcon#about to write, iclass 18, count 2 2006.257.23:48:53.66#ibcon#wrote, iclass 18, count 2 2006.257.23:48:53.66#ibcon#about to read 3, iclass 18, count 2 2006.257.23:48:53.68#ibcon#read 3, iclass 18, count 2 2006.257.23:48:53.68#ibcon#about to read 4, iclass 18, count 2 2006.257.23:48:53.68#ibcon#read 4, iclass 18, count 2 2006.257.23:48:53.68#ibcon#about to read 5, iclass 18, count 2 2006.257.23:48:53.68#ibcon#read 5, iclass 18, count 2 2006.257.23:48:53.68#ibcon#about to read 6, iclass 18, count 2 2006.257.23:48:53.68#ibcon#read 6, iclass 18, count 2 2006.257.23:48:53.68#ibcon#end of sib2, iclass 18, count 2 2006.257.23:48:53.68#ibcon#*mode == 0, iclass 18, count 2 2006.257.23:48:53.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.257.23:48:53.68#ibcon#[27=AT05-04\r\n] 2006.257.23:48:53.68#ibcon#*before write, iclass 18, count 2 2006.257.23:48:53.68#ibcon#enter sib2, iclass 18, count 2 2006.257.23:48:53.68#ibcon#flushed, iclass 18, count 2 2006.257.23:48:53.68#ibcon#about to write, iclass 18, count 2 2006.257.23:48:53.68#ibcon#wrote, iclass 18, count 2 2006.257.23:48:53.68#ibcon#about to read 3, iclass 18, count 2 2006.257.23:48:53.71#ibcon#read 3, iclass 18, count 2 2006.257.23:48:53.71#ibcon#about to read 4, iclass 18, count 2 2006.257.23:48:53.71#ibcon#read 4, iclass 18, count 2 2006.257.23:48:53.71#ibcon#about to read 5, iclass 18, count 2 2006.257.23:48:53.71#ibcon#read 5, iclass 18, count 2 2006.257.23:48:53.71#ibcon#about to read 6, iclass 18, count 2 2006.257.23:48:53.71#ibcon#read 6, iclass 18, count 2 2006.257.23:48:53.71#ibcon#end of sib2, iclass 18, count 2 2006.257.23:48:53.71#ibcon#*after write, iclass 18, count 2 2006.257.23:48:53.71#ibcon#*before return 0, iclass 18, count 2 2006.257.23:48:53.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:53.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.257.23:48:53.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.257.23:48:53.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:53.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:53.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:53.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:53.83#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:48:53.83#ibcon#first serial, iclass 18, count 0 2006.257.23:48:53.83#ibcon#enter sib2, iclass 18, count 0 2006.257.23:48:53.83#ibcon#flushed, iclass 18, count 0 2006.257.23:48:53.83#ibcon#about to write, iclass 18, count 0 2006.257.23:48:53.83#ibcon#wrote, iclass 18, count 0 2006.257.23:48:53.83#ibcon#about to read 3, iclass 18, count 0 2006.257.23:48:53.85#ibcon#read 3, iclass 18, count 0 2006.257.23:48:53.85#ibcon#about to read 4, iclass 18, count 0 2006.257.23:48:53.85#ibcon#read 4, iclass 18, count 0 2006.257.23:48:53.85#ibcon#about to read 5, iclass 18, count 0 2006.257.23:48:53.85#ibcon#read 5, iclass 18, count 0 2006.257.23:48:53.85#ibcon#about to read 6, iclass 18, count 0 2006.257.23:48:53.85#ibcon#read 6, iclass 18, count 0 2006.257.23:48:53.85#ibcon#end of sib2, iclass 18, count 0 2006.257.23:48:53.85#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:48:53.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:48:53.85#ibcon#[27=USB\r\n] 2006.257.23:48:53.85#ibcon#*before write, iclass 18, count 0 2006.257.23:48:53.85#ibcon#enter sib2, iclass 18, count 0 2006.257.23:48:53.85#ibcon#flushed, iclass 18, count 0 2006.257.23:48:53.85#ibcon#about to write, iclass 18, count 0 2006.257.23:48:53.85#ibcon#wrote, iclass 18, count 0 2006.257.23:48:53.85#ibcon#about to read 3, iclass 18, count 0 2006.257.23:48:53.88#ibcon#read 3, iclass 18, count 0 2006.257.23:48:53.88#ibcon#about to read 4, iclass 18, count 0 2006.257.23:48:53.88#ibcon#read 4, iclass 18, count 0 2006.257.23:48:53.88#ibcon#about to read 5, iclass 18, count 0 2006.257.23:48:53.88#ibcon#read 5, iclass 18, count 0 2006.257.23:48:53.88#ibcon#about to read 6, iclass 18, count 0 2006.257.23:48:53.88#ibcon#read 6, iclass 18, count 0 2006.257.23:48:53.88#ibcon#end of sib2, iclass 18, count 0 2006.257.23:48:53.88#ibcon#*after write, iclass 18, count 0 2006.257.23:48:53.88#ibcon#*before return 0, iclass 18, count 0 2006.257.23:48:53.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:53.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.257.23:48:53.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:48:53.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:48:53.88$vck44/vblo=6,719.99 2006.257.23:48:53.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.257.23:48:53.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.257.23:48:53.88#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:53.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:53.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:53.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:53.88#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:48:53.88#ibcon#first serial, iclass 20, count 0 2006.257.23:48:53.88#ibcon#enter sib2, iclass 20, count 0 2006.257.23:48:53.88#ibcon#flushed, iclass 20, count 0 2006.257.23:48:53.88#ibcon#about to write, iclass 20, count 0 2006.257.23:48:53.88#ibcon#wrote, iclass 20, count 0 2006.257.23:48:53.88#ibcon#about to read 3, iclass 20, count 0 2006.257.23:48:53.90#ibcon#read 3, iclass 20, count 0 2006.257.23:48:53.90#ibcon#about to read 4, iclass 20, count 0 2006.257.23:48:53.90#ibcon#read 4, iclass 20, count 0 2006.257.23:48:53.90#ibcon#about to read 5, iclass 20, count 0 2006.257.23:48:53.90#ibcon#read 5, iclass 20, count 0 2006.257.23:48:53.90#ibcon#about to read 6, iclass 20, count 0 2006.257.23:48:53.90#ibcon#read 6, iclass 20, count 0 2006.257.23:48:53.90#ibcon#end of sib2, iclass 20, count 0 2006.257.23:48:53.90#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:48:53.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:48:53.90#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:48:53.90#ibcon#*before write, iclass 20, count 0 2006.257.23:48:53.90#ibcon#enter sib2, iclass 20, count 0 2006.257.23:48:53.90#ibcon#flushed, iclass 20, count 0 2006.257.23:48:53.90#ibcon#about to write, iclass 20, count 0 2006.257.23:48:53.90#ibcon#wrote, iclass 20, count 0 2006.257.23:48:53.90#ibcon#about to read 3, iclass 20, count 0 2006.257.23:48:53.94#ibcon#read 3, iclass 20, count 0 2006.257.23:48:53.94#ibcon#about to read 4, iclass 20, count 0 2006.257.23:48:53.94#ibcon#read 4, iclass 20, count 0 2006.257.23:48:53.94#ibcon#about to read 5, iclass 20, count 0 2006.257.23:48:53.94#ibcon#read 5, iclass 20, count 0 2006.257.23:48:53.94#ibcon#about to read 6, iclass 20, count 0 2006.257.23:48:53.94#ibcon#read 6, iclass 20, count 0 2006.257.23:48:53.94#ibcon#end of sib2, iclass 20, count 0 2006.257.23:48:53.94#ibcon#*after write, iclass 20, count 0 2006.257.23:48:53.94#ibcon#*before return 0, iclass 20, count 0 2006.257.23:48:53.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:53.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.257.23:48:53.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:48:53.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:48:53.94$vck44/vb=6,4 2006.257.23:48:53.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.257.23:48:53.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.257.23:48:53.94#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:53.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:54.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:54.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:54.00#ibcon#enter wrdev, iclass 22, count 2 2006.257.23:48:54.00#ibcon#first serial, iclass 22, count 2 2006.257.23:48:54.00#ibcon#enter sib2, iclass 22, count 2 2006.257.23:48:54.00#ibcon#flushed, iclass 22, count 2 2006.257.23:48:54.00#ibcon#about to write, iclass 22, count 2 2006.257.23:48:54.00#ibcon#wrote, iclass 22, count 2 2006.257.23:48:54.00#ibcon#about to read 3, iclass 22, count 2 2006.257.23:48:54.02#ibcon#read 3, iclass 22, count 2 2006.257.23:48:54.02#ibcon#about to read 4, iclass 22, count 2 2006.257.23:48:54.02#ibcon#read 4, iclass 22, count 2 2006.257.23:48:54.02#ibcon#about to read 5, iclass 22, count 2 2006.257.23:48:54.02#ibcon#read 5, iclass 22, count 2 2006.257.23:48:54.02#ibcon#about to read 6, iclass 22, count 2 2006.257.23:48:54.02#ibcon#read 6, iclass 22, count 2 2006.257.23:48:54.02#ibcon#end of sib2, iclass 22, count 2 2006.257.23:48:54.02#ibcon#*mode == 0, iclass 22, count 2 2006.257.23:48:54.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.257.23:48:54.02#ibcon#[27=AT06-04\r\n] 2006.257.23:48:54.02#ibcon#*before write, iclass 22, count 2 2006.257.23:48:54.02#ibcon#enter sib2, iclass 22, count 2 2006.257.23:48:54.02#ibcon#flushed, iclass 22, count 2 2006.257.23:48:54.02#ibcon#about to write, iclass 22, count 2 2006.257.23:48:54.02#ibcon#wrote, iclass 22, count 2 2006.257.23:48:54.02#ibcon#about to read 3, iclass 22, count 2 2006.257.23:48:54.05#ibcon#read 3, iclass 22, count 2 2006.257.23:48:54.05#ibcon#about to read 4, iclass 22, count 2 2006.257.23:48:54.05#ibcon#read 4, iclass 22, count 2 2006.257.23:48:54.05#ibcon#about to read 5, iclass 22, count 2 2006.257.23:48:54.05#ibcon#read 5, iclass 22, count 2 2006.257.23:48:54.05#ibcon#about to read 6, iclass 22, count 2 2006.257.23:48:54.05#ibcon#read 6, iclass 22, count 2 2006.257.23:48:54.05#ibcon#end of sib2, iclass 22, count 2 2006.257.23:48:54.05#ibcon#*after write, iclass 22, count 2 2006.257.23:48:54.05#ibcon#*before return 0, iclass 22, count 2 2006.257.23:48:54.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:54.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.257.23:48:54.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.257.23:48:54.05#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:54.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:54.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:54.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:54.17#ibcon#enter wrdev, iclass 22, count 0 2006.257.23:48:54.17#ibcon#first serial, iclass 22, count 0 2006.257.23:48:54.17#ibcon#enter sib2, iclass 22, count 0 2006.257.23:48:54.17#ibcon#flushed, iclass 22, count 0 2006.257.23:48:54.17#ibcon#about to write, iclass 22, count 0 2006.257.23:48:54.17#ibcon#wrote, iclass 22, count 0 2006.257.23:48:54.17#ibcon#about to read 3, iclass 22, count 0 2006.257.23:48:54.19#ibcon#read 3, iclass 22, count 0 2006.257.23:48:54.19#ibcon#about to read 4, iclass 22, count 0 2006.257.23:48:54.19#ibcon#read 4, iclass 22, count 0 2006.257.23:48:54.19#ibcon#about to read 5, iclass 22, count 0 2006.257.23:48:54.19#ibcon#read 5, iclass 22, count 0 2006.257.23:48:54.19#ibcon#about to read 6, iclass 22, count 0 2006.257.23:48:54.19#ibcon#read 6, iclass 22, count 0 2006.257.23:48:54.19#ibcon#end of sib2, iclass 22, count 0 2006.257.23:48:54.19#ibcon#*mode == 0, iclass 22, count 0 2006.257.23:48:54.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.23:48:54.19#ibcon#[27=USB\r\n] 2006.257.23:48:54.19#ibcon#*before write, iclass 22, count 0 2006.257.23:48:54.19#ibcon#enter sib2, iclass 22, count 0 2006.257.23:48:54.19#ibcon#flushed, iclass 22, count 0 2006.257.23:48:54.19#ibcon#about to write, iclass 22, count 0 2006.257.23:48:54.19#ibcon#wrote, iclass 22, count 0 2006.257.23:48:54.19#ibcon#about to read 3, iclass 22, count 0 2006.257.23:48:54.22#ibcon#read 3, iclass 22, count 0 2006.257.23:48:54.22#ibcon#about to read 4, iclass 22, count 0 2006.257.23:48:54.22#ibcon#read 4, iclass 22, count 0 2006.257.23:48:54.22#ibcon#about to read 5, iclass 22, count 0 2006.257.23:48:54.22#ibcon#read 5, iclass 22, count 0 2006.257.23:48:54.22#ibcon#about to read 6, iclass 22, count 0 2006.257.23:48:54.22#ibcon#read 6, iclass 22, count 0 2006.257.23:48:54.22#ibcon#end of sib2, iclass 22, count 0 2006.257.23:48:54.22#ibcon#*after write, iclass 22, count 0 2006.257.23:48:54.22#ibcon#*before return 0, iclass 22, count 0 2006.257.23:48:54.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:54.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.257.23:48:54.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.23:48:54.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.23:48:54.22$vck44/vblo=7,734.99 2006.257.23:48:54.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.23:48:54.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.23:48:54.22#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:54.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:54.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:54.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:54.22#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:48:54.22#ibcon#first serial, iclass 24, count 0 2006.257.23:48:54.22#ibcon#enter sib2, iclass 24, count 0 2006.257.23:48:54.22#ibcon#flushed, iclass 24, count 0 2006.257.23:48:54.22#ibcon#about to write, iclass 24, count 0 2006.257.23:48:54.22#ibcon#wrote, iclass 24, count 0 2006.257.23:48:54.22#ibcon#about to read 3, iclass 24, count 0 2006.257.23:48:54.24#ibcon#read 3, iclass 24, count 0 2006.257.23:48:54.24#ibcon#about to read 4, iclass 24, count 0 2006.257.23:48:54.24#ibcon#read 4, iclass 24, count 0 2006.257.23:48:54.24#ibcon#about to read 5, iclass 24, count 0 2006.257.23:48:54.24#ibcon#read 5, iclass 24, count 0 2006.257.23:48:54.24#ibcon#about to read 6, iclass 24, count 0 2006.257.23:48:54.24#ibcon#read 6, iclass 24, count 0 2006.257.23:48:54.24#ibcon#end of sib2, iclass 24, count 0 2006.257.23:48:54.24#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:48:54.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:48:54.24#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:48:54.24#ibcon#*before write, iclass 24, count 0 2006.257.23:48:54.24#ibcon#enter sib2, iclass 24, count 0 2006.257.23:48:54.24#ibcon#flushed, iclass 24, count 0 2006.257.23:48:54.24#ibcon#about to write, iclass 24, count 0 2006.257.23:48:54.24#ibcon#wrote, iclass 24, count 0 2006.257.23:48:54.24#ibcon#about to read 3, iclass 24, count 0 2006.257.23:48:54.28#ibcon#read 3, iclass 24, count 0 2006.257.23:48:54.28#ibcon#about to read 4, iclass 24, count 0 2006.257.23:48:54.28#ibcon#read 4, iclass 24, count 0 2006.257.23:48:54.28#ibcon#about to read 5, iclass 24, count 0 2006.257.23:48:54.28#ibcon#read 5, iclass 24, count 0 2006.257.23:48:54.28#ibcon#about to read 6, iclass 24, count 0 2006.257.23:48:54.28#ibcon#read 6, iclass 24, count 0 2006.257.23:48:54.28#ibcon#end of sib2, iclass 24, count 0 2006.257.23:48:54.28#ibcon#*after write, iclass 24, count 0 2006.257.23:48:54.28#ibcon#*before return 0, iclass 24, count 0 2006.257.23:48:54.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:54.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:48:54.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:48:54.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:48:54.28$vck44/vb=7,4 2006.257.23:48:54.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.257.23:48:54.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.257.23:48:54.28#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:54.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:54.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:54.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:54.34#ibcon#enter wrdev, iclass 26, count 2 2006.257.23:48:54.34#ibcon#first serial, iclass 26, count 2 2006.257.23:48:54.34#ibcon#enter sib2, iclass 26, count 2 2006.257.23:48:54.34#ibcon#flushed, iclass 26, count 2 2006.257.23:48:54.34#ibcon#about to write, iclass 26, count 2 2006.257.23:48:54.34#ibcon#wrote, iclass 26, count 2 2006.257.23:48:54.34#ibcon#about to read 3, iclass 26, count 2 2006.257.23:48:54.36#ibcon#read 3, iclass 26, count 2 2006.257.23:48:54.36#ibcon#about to read 4, iclass 26, count 2 2006.257.23:48:54.36#ibcon#read 4, iclass 26, count 2 2006.257.23:48:54.36#ibcon#about to read 5, iclass 26, count 2 2006.257.23:48:54.36#ibcon#read 5, iclass 26, count 2 2006.257.23:48:54.36#ibcon#about to read 6, iclass 26, count 2 2006.257.23:48:54.36#ibcon#read 6, iclass 26, count 2 2006.257.23:48:54.36#ibcon#end of sib2, iclass 26, count 2 2006.257.23:48:54.36#ibcon#*mode == 0, iclass 26, count 2 2006.257.23:48:54.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.257.23:48:54.36#ibcon#[27=AT07-04\r\n] 2006.257.23:48:54.36#ibcon#*before write, iclass 26, count 2 2006.257.23:48:54.36#ibcon#enter sib2, iclass 26, count 2 2006.257.23:48:54.36#ibcon#flushed, iclass 26, count 2 2006.257.23:48:54.36#ibcon#about to write, iclass 26, count 2 2006.257.23:48:54.36#ibcon#wrote, iclass 26, count 2 2006.257.23:48:54.36#ibcon#about to read 3, iclass 26, count 2 2006.257.23:48:54.39#ibcon#read 3, iclass 26, count 2 2006.257.23:48:54.39#ibcon#about to read 4, iclass 26, count 2 2006.257.23:48:54.39#ibcon#read 4, iclass 26, count 2 2006.257.23:48:54.39#ibcon#about to read 5, iclass 26, count 2 2006.257.23:48:54.39#ibcon#read 5, iclass 26, count 2 2006.257.23:48:54.39#ibcon#about to read 6, iclass 26, count 2 2006.257.23:48:54.39#ibcon#read 6, iclass 26, count 2 2006.257.23:48:54.39#ibcon#end of sib2, iclass 26, count 2 2006.257.23:48:54.39#ibcon#*after write, iclass 26, count 2 2006.257.23:48:54.39#ibcon#*before return 0, iclass 26, count 2 2006.257.23:48:54.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:54.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.257.23:48:54.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.257.23:48:54.39#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:54.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:54.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:54.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:54.51#ibcon#enter wrdev, iclass 26, count 0 2006.257.23:48:54.51#ibcon#first serial, iclass 26, count 0 2006.257.23:48:54.51#ibcon#enter sib2, iclass 26, count 0 2006.257.23:48:54.51#ibcon#flushed, iclass 26, count 0 2006.257.23:48:54.51#ibcon#about to write, iclass 26, count 0 2006.257.23:48:54.51#ibcon#wrote, iclass 26, count 0 2006.257.23:48:54.51#ibcon#about to read 3, iclass 26, count 0 2006.257.23:48:54.53#ibcon#read 3, iclass 26, count 0 2006.257.23:48:54.53#ibcon#about to read 4, iclass 26, count 0 2006.257.23:48:54.53#ibcon#read 4, iclass 26, count 0 2006.257.23:48:54.53#ibcon#about to read 5, iclass 26, count 0 2006.257.23:48:54.53#ibcon#read 5, iclass 26, count 0 2006.257.23:48:54.53#ibcon#about to read 6, iclass 26, count 0 2006.257.23:48:54.53#ibcon#read 6, iclass 26, count 0 2006.257.23:48:54.53#ibcon#end of sib2, iclass 26, count 0 2006.257.23:48:54.53#ibcon#*mode == 0, iclass 26, count 0 2006.257.23:48:54.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.23:48:54.53#ibcon#[27=USB\r\n] 2006.257.23:48:54.53#ibcon#*before write, iclass 26, count 0 2006.257.23:48:54.53#ibcon#enter sib2, iclass 26, count 0 2006.257.23:48:54.53#ibcon#flushed, iclass 26, count 0 2006.257.23:48:54.53#ibcon#about to write, iclass 26, count 0 2006.257.23:48:54.53#ibcon#wrote, iclass 26, count 0 2006.257.23:48:54.53#ibcon#about to read 3, iclass 26, count 0 2006.257.23:48:54.56#ibcon#read 3, iclass 26, count 0 2006.257.23:48:54.56#ibcon#about to read 4, iclass 26, count 0 2006.257.23:48:54.56#ibcon#read 4, iclass 26, count 0 2006.257.23:48:54.56#ibcon#about to read 5, iclass 26, count 0 2006.257.23:48:54.56#ibcon#read 5, iclass 26, count 0 2006.257.23:48:54.56#ibcon#about to read 6, iclass 26, count 0 2006.257.23:48:54.56#ibcon#read 6, iclass 26, count 0 2006.257.23:48:54.56#ibcon#end of sib2, iclass 26, count 0 2006.257.23:48:54.56#ibcon#*after write, iclass 26, count 0 2006.257.23:48:54.56#ibcon#*before return 0, iclass 26, count 0 2006.257.23:48:54.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:54.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.257.23:48:54.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.23:48:54.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.23:48:54.56$vck44/vblo=8,744.99 2006.257.23:48:54.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.257.23:48:54.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.257.23:48:54.56#ibcon#ireg 17 cls_cnt 0 2006.257.23:48:54.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:54.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:54.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:54.56#ibcon#enter wrdev, iclass 28, count 0 2006.257.23:48:54.56#ibcon#first serial, iclass 28, count 0 2006.257.23:48:54.56#ibcon#enter sib2, iclass 28, count 0 2006.257.23:48:54.56#ibcon#flushed, iclass 28, count 0 2006.257.23:48:54.56#ibcon#about to write, iclass 28, count 0 2006.257.23:48:54.56#ibcon#wrote, iclass 28, count 0 2006.257.23:48:54.56#ibcon#about to read 3, iclass 28, count 0 2006.257.23:48:54.58#ibcon#read 3, iclass 28, count 0 2006.257.23:48:54.58#ibcon#about to read 4, iclass 28, count 0 2006.257.23:48:54.58#ibcon#read 4, iclass 28, count 0 2006.257.23:48:54.58#ibcon#about to read 5, iclass 28, count 0 2006.257.23:48:54.58#ibcon#read 5, iclass 28, count 0 2006.257.23:48:54.58#ibcon#about to read 6, iclass 28, count 0 2006.257.23:48:54.58#ibcon#read 6, iclass 28, count 0 2006.257.23:48:54.58#ibcon#end of sib2, iclass 28, count 0 2006.257.23:48:54.58#ibcon#*mode == 0, iclass 28, count 0 2006.257.23:48:54.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.23:48:54.58#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:48:54.58#ibcon#*before write, iclass 28, count 0 2006.257.23:48:54.58#ibcon#enter sib2, iclass 28, count 0 2006.257.23:48:54.58#ibcon#flushed, iclass 28, count 0 2006.257.23:48:54.58#ibcon#about to write, iclass 28, count 0 2006.257.23:48:54.58#ibcon#wrote, iclass 28, count 0 2006.257.23:48:54.58#ibcon#about to read 3, iclass 28, count 0 2006.257.23:48:54.62#ibcon#read 3, iclass 28, count 0 2006.257.23:48:54.62#ibcon#about to read 4, iclass 28, count 0 2006.257.23:48:54.62#ibcon#read 4, iclass 28, count 0 2006.257.23:48:54.62#ibcon#about to read 5, iclass 28, count 0 2006.257.23:48:54.62#ibcon#read 5, iclass 28, count 0 2006.257.23:48:54.62#ibcon#about to read 6, iclass 28, count 0 2006.257.23:48:54.62#ibcon#read 6, iclass 28, count 0 2006.257.23:48:54.62#ibcon#end of sib2, iclass 28, count 0 2006.257.23:48:54.62#ibcon#*after write, iclass 28, count 0 2006.257.23:48:54.62#ibcon#*before return 0, iclass 28, count 0 2006.257.23:48:54.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:54.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.257.23:48:54.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.23:48:54.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.23:48:54.62$vck44/vb=8,4 2006.257.23:48:54.62#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.257.23:48:54.62#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.257.23:48:54.62#ibcon#ireg 11 cls_cnt 2 2006.257.23:48:54.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:54.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:54.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:54.68#ibcon#enter wrdev, iclass 30, count 2 2006.257.23:48:54.68#ibcon#first serial, iclass 30, count 2 2006.257.23:48:54.68#ibcon#enter sib2, iclass 30, count 2 2006.257.23:48:54.68#ibcon#flushed, iclass 30, count 2 2006.257.23:48:54.68#ibcon#about to write, iclass 30, count 2 2006.257.23:48:54.68#ibcon#wrote, iclass 30, count 2 2006.257.23:48:54.68#ibcon#about to read 3, iclass 30, count 2 2006.257.23:48:54.70#ibcon#read 3, iclass 30, count 2 2006.257.23:48:54.70#ibcon#about to read 4, iclass 30, count 2 2006.257.23:48:54.70#ibcon#read 4, iclass 30, count 2 2006.257.23:48:54.70#ibcon#about to read 5, iclass 30, count 2 2006.257.23:48:54.70#ibcon#read 5, iclass 30, count 2 2006.257.23:48:54.70#ibcon#about to read 6, iclass 30, count 2 2006.257.23:48:54.70#ibcon#read 6, iclass 30, count 2 2006.257.23:48:54.70#ibcon#end of sib2, iclass 30, count 2 2006.257.23:48:54.70#ibcon#*mode == 0, iclass 30, count 2 2006.257.23:48:54.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.257.23:48:54.70#ibcon#[27=AT08-04\r\n] 2006.257.23:48:54.70#ibcon#*before write, iclass 30, count 2 2006.257.23:48:54.70#ibcon#enter sib2, iclass 30, count 2 2006.257.23:48:54.70#ibcon#flushed, iclass 30, count 2 2006.257.23:48:54.70#ibcon#about to write, iclass 30, count 2 2006.257.23:48:54.70#ibcon#wrote, iclass 30, count 2 2006.257.23:48:54.70#ibcon#about to read 3, iclass 30, count 2 2006.257.23:48:54.73#ibcon#read 3, iclass 30, count 2 2006.257.23:48:54.73#ibcon#about to read 4, iclass 30, count 2 2006.257.23:48:54.73#ibcon#read 4, iclass 30, count 2 2006.257.23:48:54.73#ibcon#about to read 5, iclass 30, count 2 2006.257.23:48:54.73#ibcon#read 5, iclass 30, count 2 2006.257.23:48:54.73#ibcon#about to read 6, iclass 30, count 2 2006.257.23:48:54.73#ibcon#read 6, iclass 30, count 2 2006.257.23:48:54.73#ibcon#end of sib2, iclass 30, count 2 2006.257.23:48:54.73#ibcon#*after write, iclass 30, count 2 2006.257.23:48:54.73#ibcon#*before return 0, iclass 30, count 2 2006.257.23:48:54.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:54.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.257.23:48:54.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.257.23:48:54.73#ibcon#ireg 7 cls_cnt 0 2006.257.23:48:54.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:54.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:54.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:54.85#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:48:54.85#ibcon#first serial, iclass 30, count 0 2006.257.23:48:54.85#ibcon#enter sib2, iclass 30, count 0 2006.257.23:48:54.85#ibcon#flushed, iclass 30, count 0 2006.257.23:48:54.85#ibcon#about to write, iclass 30, count 0 2006.257.23:48:54.85#ibcon#wrote, iclass 30, count 0 2006.257.23:48:54.85#ibcon#about to read 3, iclass 30, count 0 2006.257.23:48:54.87#ibcon#read 3, iclass 30, count 0 2006.257.23:48:54.87#ibcon#about to read 4, iclass 30, count 0 2006.257.23:48:54.87#ibcon#read 4, iclass 30, count 0 2006.257.23:48:54.87#ibcon#about to read 5, iclass 30, count 0 2006.257.23:48:54.87#ibcon#read 5, iclass 30, count 0 2006.257.23:48:54.87#ibcon#about to read 6, iclass 30, count 0 2006.257.23:48:54.87#ibcon#read 6, iclass 30, count 0 2006.257.23:48:54.87#ibcon#end of sib2, iclass 30, count 0 2006.257.23:48:54.87#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:48:54.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:48:54.87#ibcon#[27=USB\r\n] 2006.257.23:48:54.87#ibcon#*before write, iclass 30, count 0 2006.257.23:48:54.87#ibcon#enter sib2, iclass 30, count 0 2006.257.23:48:54.87#ibcon#flushed, iclass 30, count 0 2006.257.23:48:54.87#ibcon#about to write, iclass 30, count 0 2006.257.23:48:54.87#ibcon#wrote, iclass 30, count 0 2006.257.23:48:54.87#ibcon#about to read 3, iclass 30, count 0 2006.257.23:48:54.90#ibcon#read 3, iclass 30, count 0 2006.257.23:48:54.90#ibcon#about to read 4, iclass 30, count 0 2006.257.23:48:54.90#ibcon#read 4, iclass 30, count 0 2006.257.23:48:54.90#ibcon#about to read 5, iclass 30, count 0 2006.257.23:48:54.90#ibcon#read 5, iclass 30, count 0 2006.257.23:48:54.90#ibcon#about to read 6, iclass 30, count 0 2006.257.23:48:54.90#ibcon#read 6, iclass 30, count 0 2006.257.23:48:54.90#ibcon#end of sib2, iclass 30, count 0 2006.257.23:48:54.90#ibcon#*after write, iclass 30, count 0 2006.257.23:48:54.90#ibcon#*before return 0, iclass 30, count 0 2006.257.23:48:54.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:54.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.257.23:48:54.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:48:54.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:48:54.90$vck44/vabw=wide 2006.257.23:48:54.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.257.23:48:54.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.257.23:48:54.90#ibcon#ireg 8 cls_cnt 0 2006.257.23:48:54.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:54.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:54.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:54.90#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:48:54.90#ibcon#first serial, iclass 32, count 0 2006.257.23:48:54.90#ibcon#enter sib2, iclass 32, count 0 2006.257.23:48:54.90#ibcon#flushed, iclass 32, count 0 2006.257.23:48:54.90#ibcon#about to write, iclass 32, count 0 2006.257.23:48:54.90#ibcon#wrote, iclass 32, count 0 2006.257.23:48:54.90#ibcon#about to read 3, iclass 32, count 0 2006.257.23:48:54.92#ibcon#read 3, iclass 32, count 0 2006.257.23:48:54.92#ibcon#about to read 4, iclass 32, count 0 2006.257.23:48:54.92#ibcon#read 4, iclass 32, count 0 2006.257.23:48:54.92#ibcon#about to read 5, iclass 32, count 0 2006.257.23:48:54.92#ibcon#read 5, iclass 32, count 0 2006.257.23:48:54.92#ibcon#about to read 6, iclass 32, count 0 2006.257.23:48:54.92#ibcon#read 6, iclass 32, count 0 2006.257.23:48:54.92#ibcon#end of sib2, iclass 32, count 0 2006.257.23:48:54.92#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:48:54.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:48:54.92#ibcon#[25=BW32\r\n] 2006.257.23:48:54.92#ibcon#*before write, iclass 32, count 0 2006.257.23:48:54.92#ibcon#enter sib2, iclass 32, count 0 2006.257.23:48:54.92#ibcon#flushed, iclass 32, count 0 2006.257.23:48:54.92#ibcon#about to write, iclass 32, count 0 2006.257.23:48:54.92#ibcon#wrote, iclass 32, count 0 2006.257.23:48:54.92#ibcon#about to read 3, iclass 32, count 0 2006.257.23:48:54.95#ibcon#read 3, iclass 32, count 0 2006.257.23:48:54.95#ibcon#about to read 4, iclass 32, count 0 2006.257.23:48:54.95#ibcon#read 4, iclass 32, count 0 2006.257.23:48:54.95#ibcon#about to read 5, iclass 32, count 0 2006.257.23:48:54.95#ibcon#read 5, iclass 32, count 0 2006.257.23:48:54.95#ibcon#about to read 6, iclass 32, count 0 2006.257.23:48:54.95#ibcon#read 6, iclass 32, count 0 2006.257.23:48:54.95#ibcon#end of sib2, iclass 32, count 0 2006.257.23:48:54.95#ibcon#*after write, iclass 32, count 0 2006.257.23:48:54.95#ibcon#*before return 0, iclass 32, count 0 2006.257.23:48:54.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:54.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.257.23:48:54.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:48:54.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:48:54.95$vck44/vbbw=wide 2006.257.23:48:54.95#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.23:48:54.95#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.23:48:54.95#ibcon#ireg 8 cls_cnt 0 2006.257.23:48:54.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:48:55.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:48:55.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:48:55.02#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:48:55.02#ibcon#first serial, iclass 34, count 0 2006.257.23:48:55.02#ibcon#enter sib2, iclass 34, count 0 2006.257.23:48:55.02#ibcon#flushed, iclass 34, count 0 2006.257.23:48:55.02#ibcon#about to write, iclass 34, count 0 2006.257.23:48:55.02#ibcon#wrote, iclass 34, count 0 2006.257.23:48:55.02#ibcon#about to read 3, iclass 34, count 0 2006.257.23:48:55.04#ibcon#read 3, iclass 34, count 0 2006.257.23:48:55.04#ibcon#about to read 4, iclass 34, count 0 2006.257.23:48:55.04#ibcon#read 4, iclass 34, count 0 2006.257.23:48:55.04#ibcon#about to read 5, iclass 34, count 0 2006.257.23:48:55.04#ibcon#read 5, iclass 34, count 0 2006.257.23:48:55.04#ibcon#about to read 6, iclass 34, count 0 2006.257.23:48:55.04#ibcon#read 6, iclass 34, count 0 2006.257.23:48:55.04#ibcon#end of sib2, iclass 34, count 0 2006.257.23:48:55.04#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:48:55.04#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:48:55.04#ibcon#[27=BW32\r\n] 2006.257.23:48:55.04#ibcon#*before write, iclass 34, count 0 2006.257.23:48:55.04#ibcon#enter sib2, iclass 34, count 0 2006.257.23:48:55.04#ibcon#flushed, iclass 34, count 0 2006.257.23:48:55.04#ibcon#about to write, iclass 34, count 0 2006.257.23:48:55.04#ibcon#wrote, iclass 34, count 0 2006.257.23:48:55.04#ibcon#about to read 3, iclass 34, count 0 2006.257.23:48:55.07#ibcon#read 3, iclass 34, count 0 2006.257.23:48:55.07#ibcon#about to read 4, iclass 34, count 0 2006.257.23:48:55.07#ibcon#read 4, iclass 34, count 0 2006.257.23:48:55.07#ibcon#about to read 5, iclass 34, count 0 2006.257.23:48:55.07#ibcon#read 5, iclass 34, count 0 2006.257.23:48:55.07#ibcon#about to read 6, iclass 34, count 0 2006.257.23:48:55.07#ibcon#read 6, iclass 34, count 0 2006.257.23:48:55.07#ibcon#end of sib2, iclass 34, count 0 2006.257.23:48:55.07#ibcon#*after write, iclass 34, count 0 2006.257.23:48:55.07#ibcon#*before return 0, iclass 34, count 0 2006.257.23:48:55.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:48:55.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:48:55.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:48:55.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:48:55.07$setupk4/ifdk4 2006.257.23:48:55.07$ifdk4/lo= 2006.257.23:48:55.07$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:48:55.07$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:48:55.07$ifdk4/patch= 2006.257.23:48:55.07$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:48:55.07$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:48:55.07$setupk4/!*+20s 2006.257.23:48:56.23#abcon#<5=/16 1.1 3.3 21.10 771016.1\r\n> 2006.257.23:48:56.25#abcon#{5=INTERFACE CLEAR} 2006.257.23:48:56.31#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:49:06.40#abcon#<5=/16 1.1 3.3 21.10 771016.1\r\n> 2006.257.23:49:06.42#abcon#{5=INTERFACE CLEAR} 2006.257.23:49:06.48#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:49:09.58$setupk4/"tpicd 2006.257.23:49:09.58$setupk4/echo=off 2006.257.23:49:09.58$setupk4/xlog=off 2006.257.23:49:09.58:!2006.257.23:54:01 2006.257.23:49:17.13#trakl#Source acquired 2006.257.23:49:18.13#flagr#flagr/antenna,acquired 2006.257.23:54:01.00:preob 2006.257.23:54:01.14/onsource/TRACKING 2006.257.23:54:01.14:!2006.257.23:54:11 2006.257.23:54:11.00:"tape 2006.257.23:54:11.00:"st=record 2006.257.23:54:11.00:data_valid=on 2006.257.23:54:11.00:midob 2006.257.23:54:12.14/onsource/TRACKING 2006.257.23:54:12.14/wx/21.18,1016.1,78 2006.257.23:54:12.23/cable/+6.4813E-03 2006.257.23:54:13.32/va/01,08,usb,yes,31,33 2006.257.23:54:13.32/va/02,07,usb,yes,33,34 2006.257.23:54:13.32/va/03,08,usb,yes,30,32 2006.257.23:54:13.32/va/04,07,usb,yes,34,36 2006.257.23:54:13.32/va/05,04,usb,yes,31,31 2006.257.23:54:13.32/va/06,04,usb,yes,34,34 2006.257.23:54:13.32/va/07,04,usb,yes,35,35 2006.257.23:54:13.32/va/08,04,usb,yes,29,36 2006.257.23:54:13.55/valo/01,524.99,yes,locked 2006.257.23:54:13.55/valo/02,534.99,yes,locked 2006.257.23:54:13.55/valo/03,564.99,yes,locked 2006.257.23:54:13.55/valo/04,624.99,yes,locked 2006.257.23:54:13.55/valo/05,734.99,yes,locked 2006.257.23:54:13.55/valo/06,814.99,yes,locked 2006.257.23:54:13.55/valo/07,864.99,yes,locked 2006.257.23:54:13.55/valo/08,884.99,yes,locked 2006.257.23:54:14.64/vb/01,04,usb,yes,31,28 2006.257.23:54:14.64/vb/02,05,usb,yes,29,29 2006.257.23:54:14.64/vb/03,04,usb,yes,30,33 2006.257.23:54:14.64/vb/04,05,usb,yes,30,29 2006.257.23:54:14.64/vb/05,04,usb,yes,27,29 2006.257.23:54:14.64/vb/06,04,usb,yes,31,27 2006.257.23:54:14.64/vb/07,04,usb,yes,31,31 2006.257.23:54:14.64/vb/08,04,usb,yes,28,32 2006.257.23:54:14.88/vblo/01,629.99,yes,locked 2006.257.23:54:14.88/vblo/02,634.99,yes,locked 2006.257.23:54:14.88/vblo/03,649.99,yes,locked 2006.257.23:54:14.88/vblo/04,679.99,yes,locked 2006.257.23:54:14.88/vblo/05,709.99,yes,locked 2006.257.23:54:14.88/vblo/06,719.99,yes,locked 2006.257.23:54:14.88/vblo/07,734.99,yes,locked 2006.257.23:54:14.88/vblo/08,744.99,yes,locked 2006.257.23:54:15.03/vabw/8 2006.257.23:54:15.18/vbbw/8 2006.257.23:54:15.27/xfe/off,on,15.0 2006.257.23:54:15.64/ifatt/23,28,28,28 2006.257.23:54:16.08/fmout-gps/S +4.54E-07 2006.257.23:54:16.12:!2006.257.23:55:51 2006.257.23:55:51.00:data_valid=off 2006.257.23:55:51.00:"et 2006.257.23:55:51.00:!+3s 2006.257.23:55:54.02:"tape 2006.257.23:55:54.02:postob 2006.257.23:55:54.24/cable/+6.4829E-03 2006.257.23:55:54.24/wx/21.20,1016.2,80 2006.257.23:55:55.08/fmout-gps/S +4.54E-07 2006.257.23:55:55.08:scan_name=257-2357,jd0609,60 2006.257.23:55:55.08:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.257.23:55:56.14#flagr#flagr/antenna,new-source 2006.257.23:55:56.14:checkk5 2006.257.23:55:56.49/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:55:56.83/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:55:57.17/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:55:57.52/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:55:57.86/chk_obsdata//k5ts1/T2572354??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.23:55:58.20/chk_obsdata//k5ts2/T2572354??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.23:55:58.55/chk_obsdata//k5ts3/T2572354??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.23:55:58.89/chk_obsdata//k5ts4/T2572354??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.257.23:55:59.56/k5log//k5ts1_log_newline 2006.257.23:56:00.21/k5log//k5ts2_log_newline 2006.257.23:56:00.87/k5log//k5ts3_log_newline 2006.257.23:56:01.52/k5log//k5ts4_log_newline 2006.257.23:56:01.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:56:01.55:setupk4=1 2006.257.23:56:01.55$setupk4/echo=on 2006.257.23:56:01.55$setupk4/pcalon 2006.257.23:56:01.55$pcalon/"no phase cal control is implemented here 2006.257.23:56:01.55$setupk4/"tpicd=stop 2006.257.23:56:01.55$setupk4/"rec=synch_on 2006.257.23:56:01.55$setupk4/"rec_mode=128 2006.257.23:56:01.55$setupk4/!* 2006.257.23:56:01.55$setupk4/recpk4 2006.257.23:56:01.55$recpk4/recpatch= 2006.257.23:56:01.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:56:01.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:56:01.55$setupk4/vck44 2006.257.23:56:01.55$vck44/valo=1,524.99 2006.257.23:56:01.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.23:56:01.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.23:56:01.55#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:01.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:01.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:01.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:01.55#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:56:01.55#ibcon#first serial, iclass 27, count 0 2006.257.23:56:01.55#ibcon#enter sib2, iclass 27, count 0 2006.257.23:56:01.55#ibcon#flushed, iclass 27, count 0 2006.257.23:56:01.55#ibcon#about to write, iclass 27, count 0 2006.257.23:56:01.55#ibcon#wrote, iclass 27, count 0 2006.257.23:56:01.55#ibcon#about to read 3, iclass 27, count 0 2006.257.23:56:01.57#ibcon#read 3, iclass 27, count 0 2006.257.23:56:01.57#ibcon#about to read 4, iclass 27, count 0 2006.257.23:56:01.57#ibcon#read 4, iclass 27, count 0 2006.257.23:56:01.57#ibcon#about to read 5, iclass 27, count 0 2006.257.23:56:01.57#ibcon#read 5, iclass 27, count 0 2006.257.23:56:01.57#ibcon#about to read 6, iclass 27, count 0 2006.257.23:56:01.57#ibcon#read 6, iclass 27, count 0 2006.257.23:56:01.57#ibcon#end of sib2, iclass 27, count 0 2006.257.23:56:01.57#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:56:01.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:56:01.57#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:56:01.57#ibcon#*before write, iclass 27, count 0 2006.257.23:56:01.57#ibcon#enter sib2, iclass 27, count 0 2006.257.23:56:01.57#ibcon#flushed, iclass 27, count 0 2006.257.23:56:01.57#ibcon#about to write, iclass 27, count 0 2006.257.23:56:01.57#ibcon#wrote, iclass 27, count 0 2006.257.23:56:01.57#ibcon#about to read 3, iclass 27, count 0 2006.257.23:56:01.62#ibcon#read 3, iclass 27, count 0 2006.257.23:56:01.62#ibcon#about to read 4, iclass 27, count 0 2006.257.23:56:01.62#ibcon#read 4, iclass 27, count 0 2006.257.23:56:01.62#ibcon#about to read 5, iclass 27, count 0 2006.257.23:56:01.62#ibcon#read 5, iclass 27, count 0 2006.257.23:56:01.62#ibcon#about to read 6, iclass 27, count 0 2006.257.23:56:01.62#ibcon#read 6, iclass 27, count 0 2006.257.23:56:01.62#ibcon#end of sib2, iclass 27, count 0 2006.257.23:56:01.62#ibcon#*after write, iclass 27, count 0 2006.257.23:56:01.62#ibcon#*before return 0, iclass 27, count 0 2006.257.23:56:01.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:01.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:01.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:56:01.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:56:01.62$vck44/va=1,8 2006.257.23:56:01.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.23:56:01.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.23:56:01.62#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:01.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:01.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:01.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:01.62#ibcon#enter wrdev, iclass 29, count 2 2006.257.23:56:01.62#ibcon#first serial, iclass 29, count 2 2006.257.23:56:01.62#ibcon#enter sib2, iclass 29, count 2 2006.257.23:56:01.62#ibcon#flushed, iclass 29, count 2 2006.257.23:56:01.62#ibcon#about to write, iclass 29, count 2 2006.257.23:56:01.62#ibcon#wrote, iclass 29, count 2 2006.257.23:56:01.62#ibcon#about to read 3, iclass 29, count 2 2006.257.23:56:01.64#ibcon#read 3, iclass 29, count 2 2006.257.23:56:01.64#ibcon#about to read 4, iclass 29, count 2 2006.257.23:56:01.64#ibcon#read 4, iclass 29, count 2 2006.257.23:56:01.64#ibcon#about to read 5, iclass 29, count 2 2006.257.23:56:01.64#ibcon#read 5, iclass 29, count 2 2006.257.23:56:01.64#ibcon#about to read 6, iclass 29, count 2 2006.257.23:56:01.64#ibcon#read 6, iclass 29, count 2 2006.257.23:56:01.64#ibcon#end of sib2, iclass 29, count 2 2006.257.23:56:01.64#ibcon#*mode == 0, iclass 29, count 2 2006.257.23:56:01.64#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.23:56:01.64#ibcon#[25=AT01-08\r\n] 2006.257.23:56:01.64#ibcon#*before write, iclass 29, count 2 2006.257.23:56:01.64#ibcon#enter sib2, iclass 29, count 2 2006.257.23:56:01.64#ibcon#flushed, iclass 29, count 2 2006.257.23:56:01.64#ibcon#about to write, iclass 29, count 2 2006.257.23:56:01.64#ibcon#wrote, iclass 29, count 2 2006.257.23:56:01.64#ibcon#about to read 3, iclass 29, count 2 2006.257.23:56:01.67#ibcon#read 3, iclass 29, count 2 2006.257.23:56:01.67#ibcon#about to read 4, iclass 29, count 2 2006.257.23:56:01.67#ibcon#read 4, iclass 29, count 2 2006.257.23:56:01.67#ibcon#about to read 5, iclass 29, count 2 2006.257.23:56:01.67#ibcon#read 5, iclass 29, count 2 2006.257.23:56:01.67#ibcon#about to read 6, iclass 29, count 2 2006.257.23:56:01.67#ibcon#read 6, iclass 29, count 2 2006.257.23:56:01.67#ibcon#end of sib2, iclass 29, count 2 2006.257.23:56:01.67#ibcon#*after write, iclass 29, count 2 2006.257.23:56:01.67#ibcon#*before return 0, iclass 29, count 2 2006.257.23:56:01.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:01.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:01.67#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.23:56:01.67#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:01.67#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:01.79#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:01.79#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:01.79#ibcon#enter wrdev, iclass 29, count 0 2006.257.23:56:01.79#ibcon#first serial, iclass 29, count 0 2006.257.23:56:01.79#ibcon#enter sib2, iclass 29, count 0 2006.257.23:56:01.79#ibcon#flushed, iclass 29, count 0 2006.257.23:56:01.79#ibcon#about to write, iclass 29, count 0 2006.257.23:56:01.79#ibcon#wrote, iclass 29, count 0 2006.257.23:56:01.79#ibcon#about to read 3, iclass 29, count 0 2006.257.23:56:01.81#ibcon#read 3, iclass 29, count 0 2006.257.23:56:01.81#ibcon#about to read 4, iclass 29, count 0 2006.257.23:56:01.81#ibcon#read 4, iclass 29, count 0 2006.257.23:56:01.81#ibcon#about to read 5, iclass 29, count 0 2006.257.23:56:01.81#ibcon#read 5, iclass 29, count 0 2006.257.23:56:01.81#ibcon#about to read 6, iclass 29, count 0 2006.257.23:56:01.81#ibcon#read 6, iclass 29, count 0 2006.257.23:56:01.81#ibcon#end of sib2, iclass 29, count 0 2006.257.23:56:01.81#ibcon#*mode == 0, iclass 29, count 0 2006.257.23:56:01.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.23:56:01.81#ibcon#[25=USB\r\n] 2006.257.23:56:01.81#ibcon#*before write, iclass 29, count 0 2006.257.23:56:01.81#ibcon#enter sib2, iclass 29, count 0 2006.257.23:56:01.81#ibcon#flushed, iclass 29, count 0 2006.257.23:56:01.81#ibcon#about to write, iclass 29, count 0 2006.257.23:56:01.81#ibcon#wrote, iclass 29, count 0 2006.257.23:56:01.81#ibcon#about to read 3, iclass 29, count 0 2006.257.23:56:01.84#ibcon#read 3, iclass 29, count 0 2006.257.23:56:01.84#ibcon#about to read 4, iclass 29, count 0 2006.257.23:56:01.84#ibcon#read 4, iclass 29, count 0 2006.257.23:56:01.84#ibcon#about to read 5, iclass 29, count 0 2006.257.23:56:01.84#ibcon#read 5, iclass 29, count 0 2006.257.23:56:01.84#ibcon#about to read 6, iclass 29, count 0 2006.257.23:56:01.84#ibcon#read 6, iclass 29, count 0 2006.257.23:56:01.84#ibcon#end of sib2, iclass 29, count 0 2006.257.23:56:01.84#ibcon#*after write, iclass 29, count 0 2006.257.23:56:01.84#ibcon#*before return 0, iclass 29, count 0 2006.257.23:56:01.84#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:01.84#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:01.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.23:56:01.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.23:56:01.84$vck44/valo=2,534.99 2006.257.23:56:01.84#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.23:56:01.84#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.23:56:01.84#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:01.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:01.84#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:01.84#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:01.84#ibcon#enter wrdev, iclass 31, count 0 2006.257.23:56:01.84#ibcon#first serial, iclass 31, count 0 2006.257.23:56:01.84#ibcon#enter sib2, iclass 31, count 0 2006.257.23:56:01.84#ibcon#flushed, iclass 31, count 0 2006.257.23:56:01.84#ibcon#about to write, iclass 31, count 0 2006.257.23:56:01.84#ibcon#wrote, iclass 31, count 0 2006.257.23:56:01.84#ibcon#about to read 3, iclass 31, count 0 2006.257.23:56:01.86#ibcon#read 3, iclass 31, count 0 2006.257.23:56:01.86#ibcon#about to read 4, iclass 31, count 0 2006.257.23:56:01.86#ibcon#read 4, iclass 31, count 0 2006.257.23:56:01.86#ibcon#about to read 5, iclass 31, count 0 2006.257.23:56:01.86#ibcon#read 5, iclass 31, count 0 2006.257.23:56:01.86#ibcon#about to read 6, iclass 31, count 0 2006.257.23:56:01.86#ibcon#read 6, iclass 31, count 0 2006.257.23:56:01.86#ibcon#end of sib2, iclass 31, count 0 2006.257.23:56:01.86#ibcon#*mode == 0, iclass 31, count 0 2006.257.23:56:01.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.23:56:01.86#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:56:01.86#ibcon#*before write, iclass 31, count 0 2006.257.23:56:01.86#ibcon#enter sib2, iclass 31, count 0 2006.257.23:56:01.86#ibcon#flushed, iclass 31, count 0 2006.257.23:56:01.86#ibcon#about to write, iclass 31, count 0 2006.257.23:56:01.86#ibcon#wrote, iclass 31, count 0 2006.257.23:56:01.86#ibcon#about to read 3, iclass 31, count 0 2006.257.23:56:01.90#ibcon#read 3, iclass 31, count 0 2006.257.23:56:01.90#ibcon#about to read 4, iclass 31, count 0 2006.257.23:56:01.90#ibcon#read 4, iclass 31, count 0 2006.257.23:56:01.90#ibcon#about to read 5, iclass 31, count 0 2006.257.23:56:01.90#ibcon#read 5, iclass 31, count 0 2006.257.23:56:01.90#ibcon#about to read 6, iclass 31, count 0 2006.257.23:56:01.90#ibcon#read 6, iclass 31, count 0 2006.257.23:56:01.90#ibcon#end of sib2, iclass 31, count 0 2006.257.23:56:01.90#ibcon#*after write, iclass 31, count 0 2006.257.23:56:01.90#ibcon#*before return 0, iclass 31, count 0 2006.257.23:56:01.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:01.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:01.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.23:56:01.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.23:56:01.90$vck44/va=2,7 2006.257.23:56:01.90#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.23:56:01.90#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.23:56:01.90#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:01.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:01.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:01.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:01.96#ibcon#enter wrdev, iclass 33, count 2 2006.257.23:56:01.96#ibcon#first serial, iclass 33, count 2 2006.257.23:56:01.96#ibcon#enter sib2, iclass 33, count 2 2006.257.23:56:01.96#ibcon#flushed, iclass 33, count 2 2006.257.23:56:01.96#ibcon#about to write, iclass 33, count 2 2006.257.23:56:01.96#ibcon#wrote, iclass 33, count 2 2006.257.23:56:01.96#ibcon#about to read 3, iclass 33, count 2 2006.257.23:56:01.98#ibcon#read 3, iclass 33, count 2 2006.257.23:56:01.98#ibcon#about to read 4, iclass 33, count 2 2006.257.23:56:01.98#ibcon#read 4, iclass 33, count 2 2006.257.23:56:01.98#ibcon#about to read 5, iclass 33, count 2 2006.257.23:56:01.98#ibcon#read 5, iclass 33, count 2 2006.257.23:56:01.98#ibcon#about to read 6, iclass 33, count 2 2006.257.23:56:01.98#ibcon#read 6, iclass 33, count 2 2006.257.23:56:01.98#ibcon#end of sib2, iclass 33, count 2 2006.257.23:56:01.98#ibcon#*mode == 0, iclass 33, count 2 2006.257.23:56:01.98#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.23:56:01.98#ibcon#[25=AT02-07\r\n] 2006.257.23:56:01.98#ibcon#*before write, iclass 33, count 2 2006.257.23:56:01.98#ibcon#enter sib2, iclass 33, count 2 2006.257.23:56:01.98#ibcon#flushed, iclass 33, count 2 2006.257.23:56:01.98#ibcon#about to write, iclass 33, count 2 2006.257.23:56:01.98#ibcon#wrote, iclass 33, count 2 2006.257.23:56:01.98#ibcon#about to read 3, iclass 33, count 2 2006.257.23:56:02.01#ibcon#read 3, iclass 33, count 2 2006.257.23:56:02.01#ibcon#about to read 4, iclass 33, count 2 2006.257.23:56:02.01#ibcon#read 4, iclass 33, count 2 2006.257.23:56:02.01#ibcon#about to read 5, iclass 33, count 2 2006.257.23:56:02.01#ibcon#read 5, iclass 33, count 2 2006.257.23:56:02.01#ibcon#about to read 6, iclass 33, count 2 2006.257.23:56:02.01#ibcon#read 6, iclass 33, count 2 2006.257.23:56:02.01#ibcon#end of sib2, iclass 33, count 2 2006.257.23:56:02.01#ibcon#*after write, iclass 33, count 2 2006.257.23:56:02.01#ibcon#*before return 0, iclass 33, count 2 2006.257.23:56:02.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:02.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:02.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.23:56:02.01#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:02.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:02.13#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:02.13#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:02.13#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:56:02.13#ibcon#first serial, iclass 33, count 0 2006.257.23:56:02.13#ibcon#enter sib2, iclass 33, count 0 2006.257.23:56:02.13#ibcon#flushed, iclass 33, count 0 2006.257.23:56:02.13#ibcon#about to write, iclass 33, count 0 2006.257.23:56:02.13#ibcon#wrote, iclass 33, count 0 2006.257.23:56:02.13#ibcon#about to read 3, iclass 33, count 0 2006.257.23:56:02.15#ibcon#read 3, iclass 33, count 0 2006.257.23:56:02.15#ibcon#about to read 4, iclass 33, count 0 2006.257.23:56:02.15#ibcon#read 4, iclass 33, count 0 2006.257.23:56:02.15#ibcon#about to read 5, iclass 33, count 0 2006.257.23:56:02.15#ibcon#read 5, iclass 33, count 0 2006.257.23:56:02.15#ibcon#about to read 6, iclass 33, count 0 2006.257.23:56:02.15#ibcon#read 6, iclass 33, count 0 2006.257.23:56:02.15#ibcon#end of sib2, iclass 33, count 0 2006.257.23:56:02.15#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:56:02.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:56:02.15#ibcon#[25=USB\r\n] 2006.257.23:56:02.15#ibcon#*before write, iclass 33, count 0 2006.257.23:56:02.15#ibcon#enter sib2, iclass 33, count 0 2006.257.23:56:02.15#ibcon#flushed, iclass 33, count 0 2006.257.23:56:02.15#ibcon#about to write, iclass 33, count 0 2006.257.23:56:02.15#ibcon#wrote, iclass 33, count 0 2006.257.23:56:02.15#ibcon#about to read 3, iclass 33, count 0 2006.257.23:56:02.18#ibcon#read 3, iclass 33, count 0 2006.257.23:56:02.18#ibcon#about to read 4, iclass 33, count 0 2006.257.23:56:02.18#ibcon#read 4, iclass 33, count 0 2006.257.23:56:02.18#ibcon#about to read 5, iclass 33, count 0 2006.257.23:56:02.18#ibcon#read 5, iclass 33, count 0 2006.257.23:56:02.18#ibcon#about to read 6, iclass 33, count 0 2006.257.23:56:02.18#ibcon#read 6, iclass 33, count 0 2006.257.23:56:02.18#ibcon#end of sib2, iclass 33, count 0 2006.257.23:56:02.18#ibcon#*after write, iclass 33, count 0 2006.257.23:56:02.18#ibcon#*before return 0, iclass 33, count 0 2006.257.23:56:02.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:02.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:02.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:56:02.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:56:02.18$vck44/valo=3,564.99 2006.257.23:56:02.18#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.23:56:02.18#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.23:56:02.18#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:02.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:02.18#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:02.18#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:02.18#ibcon#enter wrdev, iclass 35, count 0 2006.257.23:56:02.18#ibcon#first serial, iclass 35, count 0 2006.257.23:56:02.18#ibcon#enter sib2, iclass 35, count 0 2006.257.23:56:02.18#ibcon#flushed, iclass 35, count 0 2006.257.23:56:02.18#ibcon#about to write, iclass 35, count 0 2006.257.23:56:02.18#ibcon#wrote, iclass 35, count 0 2006.257.23:56:02.18#ibcon#about to read 3, iclass 35, count 0 2006.257.23:56:02.20#ibcon#read 3, iclass 35, count 0 2006.257.23:56:02.20#ibcon#about to read 4, iclass 35, count 0 2006.257.23:56:02.20#ibcon#read 4, iclass 35, count 0 2006.257.23:56:02.20#ibcon#about to read 5, iclass 35, count 0 2006.257.23:56:02.20#ibcon#read 5, iclass 35, count 0 2006.257.23:56:02.20#ibcon#about to read 6, iclass 35, count 0 2006.257.23:56:02.20#ibcon#read 6, iclass 35, count 0 2006.257.23:56:02.20#ibcon#end of sib2, iclass 35, count 0 2006.257.23:56:02.20#ibcon#*mode == 0, iclass 35, count 0 2006.257.23:56:02.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.23:56:02.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:56:02.20#ibcon#*before write, iclass 35, count 0 2006.257.23:56:02.20#ibcon#enter sib2, iclass 35, count 0 2006.257.23:56:02.20#ibcon#flushed, iclass 35, count 0 2006.257.23:56:02.20#ibcon#about to write, iclass 35, count 0 2006.257.23:56:02.20#ibcon#wrote, iclass 35, count 0 2006.257.23:56:02.20#ibcon#about to read 3, iclass 35, count 0 2006.257.23:56:02.24#ibcon#read 3, iclass 35, count 0 2006.257.23:56:02.24#ibcon#about to read 4, iclass 35, count 0 2006.257.23:56:02.24#ibcon#read 4, iclass 35, count 0 2006.257.23:56:02.24#ibcon#about to read 5, iclass 35, count 0 2006.257.23:56:02.24#ibcon#read 5, iclass 35, count 0 2006.257.23:56:02.24#ibcon#about to read 6, iclass 35, count 0 2006.257.23:56:02.24#ibcon#read 6, iclass 35, count 0 2006.257.23:56:02.24#ibcon#end of sib2, iclass 35, count 0 2006.257.23:56:02.24#ibcon#*after write, iclass 35, count 0 2006.257.23:56:02.24#ibcon#*before return 0, iclass 35, count 0 2006.257.23:56:02.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:02.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:02.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.23:56:02.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.23:56:02.24$vck44/va=3,8 2006.257.23:56:02.24#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.23:56:02.24#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.23:56:02.24#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:02.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:02.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:02.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:02.30#ibcon#enter wrdev, iclass 37, count 2 2006.257.23:56:02.30#ibcon#first serial, iclass 37, count 2 2006.257.23:56:02.30#ibcon#enter sib2, iclass 37, count 2 2006.257.23:56:02.30#ibcon#flushed, iclass 37, count 2 2006.257.23:56:02.30#ibcon#about to write, iclass 37, count 2 2006.257.23:56:02.30#ibcon#wrote, iclass 37, count 2 2006.257.23:56:02.30#ibcon#about to read 3, iclass 37, count 2 2006.257.23:56:02.32#ibcon#read 3, iclass 37, count 2 2006.257.23:56:02.32#ibcon#about to read 4, iclass 37, count 2 2006.257.23:56:02.32#ibcon#read 4, iclass 37, count 2 2006.257.23:56:02.32#ibcon#about to read 5, iclass 37, count 2 2006.257.23:56:02.32#ibcon#read 5, iclass 37, count 2 2006.257.23:56:02.32#ibcon#about to read 6, iclass 37, count 2 2006.257.23:56:02.32#ibcon#read 6, iclass 37, count 2 2006.257.23:56:02.32#ibcon#end of sib2, iclass 37, count 2 2006.257.23:56:02.32#ibcon#*mode == 0, iclass 37, count 2 2006.257.23:56:02.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.23:56:02.32#ibcon#[25=AT03-08\r\n] 2006.257.23:56:02.32#ibcon#*before write, iclass 37, count 2 2006.257.23:56:02.32#ibcon#enter sib2, iclass 37, count 2 2006.257.23:56:02.32#ibcon#flushed, iclass 37, count 2 2006.257.23:56:02.32#ibcon#about to write, iclass 37, count 2 2006.257.23:56:02.32#ibcon#wrote, iclass 37, count 2 2006.257.23:56:02.32#ibcon#about to read 3, iclass 37, count 2 2006.257.23:56:02.35#ibcon#read 3, iclass 37, count 2 2006.257.23:56:02.35#ibcon#about to read 4, iclass 37, count 2 2006.257.23:56:02.35#ibcon#read 4, iclass 37, count 2 2006.257.23:56:02.35#ibcon#about to read 5, iclass 37, count 2 2006.257.23:56:02.35#ibcon#read 5, iclass 37, count 2 2006.257.23:56:02.35#ibcon#about to read 6, iclass 37, count 2 2006.257.23:56:02.35#ibcon#read 6, iclass 37, count 2 2006.257.23:56:02.35#ibcon#end of sib2, iclass 37, count 2 2006.257.23:56:02.35#ibcon#*after write, iclass 37, count 2 2006.257.23:56:02.35#ibcon#*before return 0, iclass 37, count 2 2006.257.23:56:02.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:02.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:02.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.23:56:02.35#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:02.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:02.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:02.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:02.47#ibcon#enter wrdev, iclass 37, count 0 2006.257.23:56:02.47#ibcon#first serial, iclass 37, count 0 2006.257.23:56:02.47#ibcon#enter sib2, iclass 37, count 0 2006.257.23:56:02.47#ibcon#flushed, iclass 37, count 0 2006.257.23:56:02.47#ibcon#about to write, iclass 37, count 0 2006.257.23:56:02.47#ibcon#wrote, iclass 37, count 0 2006.257.23:56:02.47#ibcon#about to read 3, iclass 37, count 0 2006.257.23:56:02.49#ibcon#read 3, iclass 37, count 0 2006.257.23:56:02.49#ibcon#about to read 4, iclass 37, count 0 2006.257.23:56:02.49#ibcon#read 4, iclass 37, count 0 2006.257.23:56:02.49#ibcon#about to read 5, iclass 37, count 0 2006.257.23:56:02.49#ibcon#read 5, iclass 37, count 0 2006.257.23:56:02.49#ibcon#about to read 6, iclass 37, count 0 2006.257.23:56:02.49#ibcon#read 6, iclass 37, count 0 2006.257.23:56:02.49#ibcon#end of sib2, iclass 37, count 0 2006.257.23:56:02.49#ibcon#*mode == 0, iclass 37, count 0 2006.257.23:56:02.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.23:56:02.49#ibcon#[25=USB\r\n] 2006.257.23:56:02.49#ibcon#*before write, iclass 37, count 0 2006.257.23:56:02.49#ibcon#enter sib2, iclass 37, count 0 2006.257.23:56:02.49#ibcon#flushed, iclass 37, count 0 2006.257.23:56:02.49#ibcon#about to write, iclass 37, count 0 2006.257.23:56:02.49#ibcon#wrote, iclass 37, count 0 2006.257.23:56:02.49#ibcon#about to read 3, iclass 37, count 0 2006.257.23:56:02.52#ibcon#read 3, iclass 37, count 0 2006.257.23:56:02.52#ibcon#about to read 4, iclass 37, count 0 2006.257.23:56:02.52#ibcon#read 4, iclass 37, count 0 2006.257.23:56:02.52#ibcon#about to read 5, iclass 37, count 0 2006.257.23:56:02.52#ibcon#read 5, iclass 37, count 0 2006.257.23:56:02.52#ibcon#about to read 6, iclass 37, count 0 2006.257.23:56:02.52#ibcon#read 6, iclass 37, count 0 2006.257.23:56:02.52#ibcon#end of sib2, iclass 37, count 0 2006.257.23:56:02.52#ibcon#*after write, iclass 37, count 0 2006.257.23:56:02.52#ibcon#*before return 0, iclass 37, count 0 2006.257.23:56:02.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:02.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:02.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.23:56:02.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.23:56:02.52$vck44/valo=4,624.99 2006.257.23:56:02.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.23:56:02.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.23:56:02.52#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:02.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:02.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:02.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:02.52#ibcon#enter wrdev, iclass 39, count 0 2006.257.23:56:02.52#ibcon#first serial, iclass 39, count 0 2006.257.23:56:02.52#ibcon#enter sib2, iclass 39, count 0 2006.257.23:56:02.52#ibcon#flushed, iclass 39, count 0 2006.257.23:56:02.52#ibcon#about to write, iclass 39, count 0 2006.257.23:56:02.52#ibcon#wrote, iclass 39, count 0 2006.257.23:56:02.52#ibcon#about to read 3, iclass 39, count 0 2006.257.23:56:02.54#ibcon#read 3, iclass 39, count 0 2006.257.23:56:02.54#ibcon#about to read 4, iclass 39, count 0 2006.257.23:56:02.54#ibcon#read 4, iclass 39, count 0 2006.257.23:56:02.54#ibcon#about to read 5, iclass 39, count 0 2006.257.23:56:02.54#ibcon#read 5, iclass 39, count 0 2006.257.23:56:02.54#ibcon#about to read 6, iclass 39, count 0 2006.257.23:56:02.54#ibcon#read 6, iclass 39, count 0 2006.257.23:56:02.54#ibcon#end of sib2, iclass 39, count 0 2006.257.23:56:02.54#ibcon#*mode == 0, iclass 39, count 0 2006.257.23:56:02.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.23:56:02.54#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:56:02.54#ibcon#*before write, iclass 39, count 0 2006.257.23:56:02.54#ibcon#enter sib2, iclass 39, count 0 2006.257.23:56:02.54#ibcon#flushed, iclass 39, count 0 2006.257.23:56:02.54#ibcon#about to write, iclass 39, count 0 2006.257.23:56:02.54#ibcon#wrote, iclass 39, count 0 2006.257.23:56:02.54#ibcon#about to read 3, iclass 39, count 0 2006.257.23:56:02.58#ibcon#read 3, iclass 39, count 0 2006.257.23:56:02.58#ibcon#about to read 4, iclass 39, count 0 2006.257.23:56:02.58#ibcon#read 4, iclass 39, count 0 2006.257.23:56:02.58#ibcon#about to read 5, iclass 39, count 0 2006.257.23:56:02.58#ibcon#read 5, iclass 39, count 0 2006.257.23:56:02.58#ibcon#about to read 6, iclass 39, count 0 2006.257.23:56:02.58#ibcon#read 6, iclass 39, count 0 2006.257.23:56:02.58#ibcon#end of sib2, iclass 39, count 0 2006.257.23:56:02.58#ibcon#*after write, iclass 39, count 0 2006.257.23:56:02.58#ibcon#*before return 0, iclass 39, count 0 2006.257.23:56:02.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:02.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:02.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.23:56:02.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.23:56:02.58$vck44/va=4,7 2006.257.23:56:02.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.23:56:02.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.23:56:02.58#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:02.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:02.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:02.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:02.64#ibcon#enter wrdev, iclass 3, count 2 2006.257.23:56:02.64#ibcon#first serial, iclass 3, count 2 2006.257.23:56:02.64#ibcon#enter sib2, iclass 3, count 2 2006.257.23:56:02.64#ibcon#flushed, iclass 3, count 2 2006.257.23:56:02.64#ibcon#about to write, iclass 3, count 2 2006.257.23:56:02.64#ibcon#wrote, iclass 3, count 2 2006.257.23:56:02.64#ibcon#about to read 3, iclass 3, count 2 2006.257.23:56:02.66#ibcon#read 3, iclass 3, count 2 2006.257.23:56:02.66#ibcon#about to read 4, iclass 3, count 2 2006.257.23:56:02.66#ibcon#read 4, iclass 3, count 2 2006.257.23:56:02.66#ibcon#about to read 5, iclass 3, count 2 2006.257.23:56:02.66#ibcon#read 5, iclass 3, count 2 2006.257.23:56:02.66#ibcon#about to read 6, iclass 3, count 2 2006.257.23:56:02.66#ibcon#read 6, iclass 3, count 2 2006.257.23:56:02.66#ibcon#end of sib2, iclass 3, count 2 2006.257.23:56:02.66#ibcon#*mode == 0, iclass 3, count 2 2006.257.23:56:02.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.23:56:02.66#ibcon#[25=AT04-07\r\n] 2006.257.23:56:02.66#ibcon#*before write, iclass 3, count 2 2006.257.23:56:02.66#ibcon#enter sib2, iclass 3, count 2 2006.257.23:56:02.66#ibcon#flushed, iclass 3, count 2 2006.257.23:56:02.66#ibcon#about to write, iclass 3, count 2 2006.257.23:56:02.66#ibcon#wrote, iclass 3, count 2 2006.257.23:56:02.66#ibcon#about to read 3, iclass 3, count 2 2006.257.23:56:02.69#ibcon#read 3, iclass 3, count 2 2006.257.23:56:02.69#ibcon#about to read 4, iclass 3, count 2 2006.257.23:56:02.69#ibcon#read 4, iclass 3, count 2 2006.257.23:56:02.69#ibcon#about to read 5, iclass 3, count 2 2006.257.23:56:02.69#ibcon#read 5, iclass 3, count 2 2006.257.23:56:02.69#ibcon#about to read 6, iclass 3, count 2 2006.257.23:56:02.69#ibcon#read 6, iclass 3, count 2 2006.257.23:56:02.69#ibcon#end of sib2, iclass 3, count 2 2006.257.23:56:02.69#ibcon#*after write, iclass 3, count 2 2006.257.23:56:02.69#ibcon#*before return 0, iclass 3, count 2 2006.257.23:56:02.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:02.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:02.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.23:56:02.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:02.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:02.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:02.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:02.81#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:56:02.81#ibcon#first serial, iclass 3, count 0 2006.257.23:56:02.81#ibcon#enter sib2, iclass 3, count 0 2006.257.23:56:02.81#ibcon#flushed, iclass 3, count 0 2006.257.23:56:02.81#ibcon#about to write, iclass 3, count 0 2006.257.23:56:02.81#ibcon#wrote, iclass 3, count 0 2006.257.23:56:02.81#ibcon#about to read 3, iclass 3, count 0 2006.257.23:56:02.83#ibcon#read 3, iclass 3, count 0 2006.257.23:56:02.83#ibcon#about to read 4, iclass 3, count 0 2006.257.23:56:02.83#ibcon#read 4, iclass 3, count 0 2006.257.23:56:02.83#ibcon#about to read 5, iclass 3, count 0 2006.257.23:56:02.83#ibcon#read 5, iclass 3, count 0 2006.257.23:56:02.83#ibcon#about to read 6, iclass 3, count 0 2006.257.23:56:02.83#ibcon#read 6, iclass 3, count 0 2006.257.23:56:02.83#ibcon#end of sib2, iclass 3, count 0 2006.257.23:56:02.83#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:56:02.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:56:02.83#ibcon#[25=USB\r\n] 2006.257.23:56:02.83#ibcon#*before write, iclass 3, count 0 2006.257.23:56:02.83#ibcon#enter sib2, iclass 3, count 0 2006.257.23:56:02.83#ibcon#flushed, iclass 3, count 0 2006.257.23:56:02.83#ibcon#about to write, iclass 3, count 0 2006.257.23:56:02.83#ibcon#wrote, iclass 3, count 0 2006.257.23:56:02.83#ibcon#about to read 3, iclass 3, count 0 2006.257.23:56:02.86#ibcon#read 3, iclass 3, count 0 2006.257.23:56:02.86#ibcon#about to read 4, iclass 3, count 0 2006.257.23:56:02.86#ibcon#read 4, iclass 3, count 0 2006.257.23:56:02.86#ibcon#about to read 5, iclass 3, count 0 2006.257.23:56:02.86#ibcon#read 5, iclass 3, count 0 2006.257.23:56:02.86#ibcon#about to read 6, iclass 3, count 0 2006.257.23:56:02.86#ibcon#read 6, iclass 3, count 0 2006.257.23:56:02.86#ibcon#end of sib2, iclass 3, count 0 2006.257.23:56:02.86#ibcon#*after write, iclass 3, count 0 2006.257.23:56:02.86#ibcon#*before return 0, iclass 3, count 0 2006.257.23:56:02.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:02.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:02.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:56:02.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:56:02.86$vck44/valo=5,734.99 2006.257.23:56:02.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.23:56:02.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.23:56:02.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:02.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:02.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:02.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:02.86#ibcon#enter wrdev, iclass 5, count 0 2006.257.23:56:02.86#ibcon#first serial, iclass 5, count 0 2006.257.23:56:02.86#ibcon#enter sib2, iclass 5, count 0 2006.257.23:56:02.86#ibcon#flushed, iclass 5, count 0 2006.257.23:56:02.86#ibcon#about to write, iclass 5, count 0 2006.257.23:56:02.86#ibcon#wrote, iclass 5, count 0 2006.257.23:56:02.86#ibcon#about to read 3, iclass 5, count 0 2006.257.23:56:02.88#ibcon#read 3, iclass 5, count 0 2006.257.23:56:02.88#ibcon#about to read 4, iclass 5, count 0 2006.257.23:56:02.88#ibcon#read 4, iclass 5, count 0 2006.257.23:56:02.88#ibcon#about to read 5, iclass 5, count 0 2006.257.23:56:02.88#ibcon#read 5, iclass 5, count 0 2006.257.23:56:02.88#ibcon#about to read 6, iclass 5, count 0 2006.257.23:56:02.88#ibcon#read 6, iclass 5, count 0 2006.257.23:56:02.88#ibcon#end of sib2, iclass 5, count 0 2006.257.23:56:02.88#ibcon#*mode == 0, iclass 5, count 0 2006.257.23:56:02.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.23:56:02.88#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:56:02.88#ibcon#*before write, iclass 5, count 0 2006.257.23:56:02.88#ibcon#enter sib2, iclass 5, count 0 2006.257.23:56:02.88#ibcon#flushed, iclass 5, count 0 2006.257.23:56:02.88#ibcon#about to write, iclass 5, count 0 2006.257.23:56:02.88#ibcon#wrote, iclass 5, count 0 2006.257.23:56:02.88#ibcon#about to read 3, iclass 5, count 0 2006.257.23:56:02.92#ibcon#read 3, iclass 5, count 0 2006.257.23:56:02.92#ibcon#about to read 4, iclass 5, count 0 2006.257.23:56:02.92#ibcon#read 4, iclass 5, count 0 2006.257.23:56:02.92#ibcon#about to read 5, iclass 5, count 0 2006.257.23:56:02.92#ibcon#read 5, iclass 5, count 0 2006.257.23:56:02.92#ibcon#about to read 6, iclass 5, count 0 2006.257.23:56:02.92#ibcon#read 6, iclass 5, count 0 2006.257.23:56:02.92#ibcon#end of sib2, iclass 5, count 0 2006.257.23:56:02.92#ibcon#*after write, iclass 5, count 0 2006.257.23:56:02.92#ibcon#*before return 0, iclass 5, count 0 2006.257.23:56:02.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:02.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:02.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.23:56:02.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.23:56:02.92$vck44/va=5,4 2006.257.23:56:02.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.23:56:02.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.23:56:02.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:02.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:02.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:02.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:02.98#ibcon#enter wrdev, iclass 7, count 2 2006.257.23:56:02.98#ibcon#first serial, iclass 7, count 2 2006.257.23:56:02.98#ibcon#enter sib2, iclass 7, count 2 2006.257.23:56:02.98#ibcon#flushed, iclass 7, count 2 2006.257.23:56:02.98#ibcon#about to write, iclass 7, count 2 2006.257.23:56:02.98#ibcon#wrote, iclass 7, count 2 2006.257.23:56:02.98#ibcon#about to read 3, iclass 7, count 2 2006.257.23:56:03.00#ibcon#read 3, iclass 7, count 2 2006.257.23:56:03.00#ibcon#about to read 4, iclass 7, count 2 2006.257.23:56:03.00#ibcon#read 4, iclass 7, count 2 2006.257.23:56:03.00#ibcon#about to read 5, iclass 7, count 2 2006.257.23:56:03.00#ibcon#read 5, iclass 7, count 2 2006.257.23:56:03.00#ibcon#about to read 6, iclass 7, count 2 2006.257.23:56:03.00#ibcon#read 6, iclass 7, count 2 2006.257.23:56:03.00#ibcon#end of sib2, iclass 7, count 2 2006.257.23:56:03.00#ibcon#*mode == 0, iclass 7, count 2 2006.257.23:56:03.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.23:56:03.00#ibcon#[25=AT05-04\r\n] 2006.257.23:56:03.00#ibcon#*before write, iclass 7, count 2 2006.257.23:56:03.00#ibcon#enter sib2, iclass 7, count 2 2006.257.23:56:03.00#ibcon#flushed, iclass 7, count 2 2006.257.23:56:03.00#ibcon#about to write, iclass 7, count 2 2006.257.23:56:03.00#ibcon#wrote, iclass 7, count 2 2006.257.23:56:03.00#ibcon#about to read 3, iclass 7, count 2 2006.257.23:56:03.03#ibcon#read 3, iclass 7, count 2 2006.257.23:56:03.03#ibcon#about to read 4, iclass 7, count 2 2006.257.23:56:03.03#ibcon#read 4, iclass 7, count 2 2006.257.23:56:03.03#ibcon#about to read 5, iclass 7, count 2 2006.257.23:56:03.03#ibcon#read 5, iclass 7, count 2 2006.257.23:56:03.03#ibcon#about to read 6, iclass 7, count 2 2006.257.23:56:03.03#ibcon#read 6, iclass 7, count 2 2006.257.23:56:03.03#ibcon#end of sib2, iclass 7, count 2 2006.257.23:56:03.03#ibcon#*after write, iclass 7, count 2 2006.257.23:56:03.03#ibcon#*before return 0, iclass 7, count 2 2006.257.23:56:03.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:03.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:03.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.23:56:03.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:03.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:03.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:03.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:03.15#ibcon#enter wrdev, iclass 7, count 0 2006.257.23:56:03.15#ibcon#first serial, iclass 7, count 0 2006.257.23:56:03.15#ibcon#enter sib2, iclass 7, count 0 2006.257.23:56:03.15#ibcon#flushed, iclass 7, count 0 2006.257.23:56:03.15#ibcon#about to write, iclass 7, count 0 2006.257.23:56:03.15#ibcon#wrote, iclass 7, count 0 2006.257.23:56:03.15#ibcon#about to read 3, iclass 7, count 0 2006.257.23:56:03.17#ibcon#read 3, iclass 7, count 0 2006.257.23:56:03.17#ibcon#about to read 4, iclass 7, count 0 2006.257.23:56:03.17#ibcon#read 4, iclass 7, count 0 2006.257.23:56:03.17#ibcon#about to read 5, iclass 7, count 0 2006.257.23:56:03.17#ibcon#read 5, iclass 7, count 0 2006.257.23:56:03.17#ibcon#about to read 6, iclass 7, count 0 2006.257.23:56:03.17#ibcon#read 6, iclass 7, count 0 2006.257.23:56:03.17#ibcon#end of sib2, iclass 7, count 0 2006.257.23:56:03.17#ibcon#*mode == 0, iclass 7, count 0 2006.257.23:56:03.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.23:56:03.17#ibcon#[25=USB\r\n] 2006.257.23:56:03.17#ibcon#*before write, iclass 7, count 0 2006.257.23:56:03.17#ibcon#enter sib2, iclass 7, count 0 2006.257.23:56:03.17#ibcon#flushed, iclass 7, count 0 2006.257.23:56:03.17#ibcon#about to write, iclass 7, count 0 2006.257.23:56:03.17#ibcon#wrote, iclass 7, count 0 2006.257.23:56:03.17#ibcon#about to read 3, iclass 7, count 0 2006.257.23:56:03.20#ibcon#read 3, iclass 7, count 0 2006.257.23:56:03.20#ibcon#about to read 4, iclass 7, count 0 2006.257.23:56:03.20#ibcon#read 4, iclass 7, count 0 2006.257.23:56:03.20#ibcon#about to read 5, iclass 7, count 0 2006.257.23:56:03.20#ibcon#read 5, iclass 7, count 0 2006.257.23:56:03.20#ibcon#about to read 6, iclass 7, count 0 2006.257.23:56:03.20#ibcon#read 6, iclass 7, count 0 2006.257.23:56:03.20#ibcon#end of sib2, iclass 7, count 0 2006.257.23:56:03.20#ibcon#*after write, iclass 7, count 0 2006.257.23:56:03.20#ibcon#*before return 0, iclass 7, count 0 2006.257.23:56:03.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:03.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:03.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.23:56:03.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.23:56:03.20$vck44/valo=6,814.99 2006.257.23:56:03.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.23:56:03.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.23:56:03.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:03.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:03.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:03.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:03.20#ibcon#enter wrdev, iclass 11, count 0 2006.257.23:56:03.20#ibcon#first serial, iclass 11, count 0 2006.257.23:56:03.20#ibcon#enter sib2, iclass 11, count 0 2006.257.23:56:03.20#ibcon#flushed, iclass 11, count 0 2006.257.23:56:03.20#ibcon#about to write, iclass 11, count 0 2006.257.23:56:03.20#ibcon#wrote, iclass 11, count 0 2006.257.23:56:03.20#ibcon#about to read 3, iclass 11, count 0 2006.257.23:56:03.22#ibcon#read 3, iclass 11, count 0 2006.257.23:56:03.22#ibcon#about to read 4, iclass 11, count 0 2006.257.23:56:03.22#ibcon#read 4, iclass 11, count 0 2006.257.23:56:03.22#ibcon#about to read 5, iclass 11, count 0 2006.257.23:56:03.22#ibcon#read 5, iclass 11, count 0 2006.257.23:56:03.22#ibcon#about to read 6, iclass 11, count 0 2006.257.23:56:03.22#ibcon#read 6, iclass 11, count 0 2006.257.23:56:03.22#ibcon#end of sib2, iclass 11, count 0 2006.257.23:56:03.22#ibcon#*mode == 0, iclass 11, count 0 2006.257.23:56:03.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.23:56:03.22#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:56:03.22#ibcon#*before write, iclass 11, count 0 2006.257.23:56:03.22#ibcon#enter sib2, iclass 11, count 0 2006.257.23:56:03.22#ibcon#flushed, iclass 11, count 0 2006.257.23:56:03.22#ibcon#about to write, iclass 11, count 0 2006.257.23:56:03.22#ibcon#wrote, iclass 11, count 0 2006.257.23:56:03.22#ibcon#about to read 3, iclass 11, count 0 2006.257.23:56:03.26#ibcon#read 3, iclass 11, count 0 2006.257.23:56:03.26#ibcon#about to read 4, iclass 11, count 0 2006.257.23:56:03.26#ibcon#read 4, iclass 11, count 0 2006.257.23:56:03.26#ibcon#about to read 5, iclass 11, count 0 2006.257.23:56:03.26#ibcon#read 5, iclass 11, count 0 2006.257.23:56:03.26#ibcon#about to read 6, iclass 11, count 0 2006.257.23:56:03.26#ibcon#read 6, iclass 11, count 0 2006.257.23:56:03.26#ibcon#end of sib2, iclass 11, count 0 2006.257.23:56:03.26#ibcon#*after write, iclass 11, count 0 2006.257.23:56:03.26#ibcon#*before return 0, iclass 11, count 0 2006.257.23:56:03.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:03.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:03.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.23:56:03.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.23:56:03.26$vck44/va=6,4 2006.257.23:56:03.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.23:56:03.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.23:56:03.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:03.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:03.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:03.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:03.32#ibcon#enter wrdev, iclass 13, count 2 2006.257.23:56:03.32#ibcon#first serial, iclass 13, count 2 2006.257.23:56:03.32#ibcon#enter sib2, iclass 13, count 2 2006.257.23:56:03.32#ibcon#flushed, iclass 13, count 2 2006.257.23:56:03.32#ibcon#about to write, iclass 13, count 2 2006.257.23:56:03.32#ibcon#wrote, iclass 13, count 2 2006.257.23:56:03.32#ibcon#about to read 3, iclass 13, count 2 2006.257.23:56:03.34#ibcon#read 3, iclass 13, count 2 2006.257.23:56:03.34#ibcon#about to read 4, iclass 13, count 2 2006.257.23:56:03.34#ibcon#read 4, iclass 13, count 2 2006.257.23:56:03.34#ibcon#about to read 5, iclass 13, count 2 2006.257.23:56:03.34#ibcon#read 5, iclass 13, count 2 2006.257.23:56:03.34#ibcon#about to read 6, iclass 13, count 2 2006.257.23:56:03.34#ibcon#read 6, iclass 13, count 2 2006.257.23:56:03.34#ibcon#end of sib2, iclass 13, count 2 2006.257.23:56:03.34#ibcon#*mode == 0, iclass 13, count 2 2006.257.23:56:03.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.23:56:03.34#ibcon#[25=AT06-04\r\n] 2006.257.23:56:03.34#ibcon#*before write, iclass 13, count 2 2006.257.23:56:03.34#ibcon#enter sib2, iclass 13, count 2 2006.257.23:56:03.34#ibcon#flushed, iclass 13, count 2 2006.257.23:56:03.34#ibcon#about to write, iclass 13, count 2 2006.257.23:56:03.34#ibcon#wrote, iclass 13, count 2 2006.257.23:56:03.34#ibcon#about to read 3, iclass 13, count 2 2006.257.23:56:03.37#ibcon#read 3, iclass 13, count 2 2006.257.23:56:03.37#ibcon#about to read 4, iclass 13, count 2 2006.257.23:56:03.37#ibcon#read 4, iclass 13, count 2 2006.257.23:56:03.37#ibcon#about to read 5, iclass 13, count 2 2006.257.23:56:03.37#ibcon#read 5, iclass 13, count 2 2006.257.23:56:03.37#ibcon#about to read 6, iclass 13, count 2 2006.257.23:56:03.37#ibcon#read 6, iclass 13, count 2 2006.257.23:56:03.37#ibcon#end of sib2, iclass 13, count 2 2006.257.23:56:03.37#ibcon#*after write, iclass 13, count 2 2006.257.23:56:03.37#ibcon#*before return 0, iclass 13, count 2 2006.257.23:56:03.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:03.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:03.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.23:56:03.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:03.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:03.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:03.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:03.49#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:56:03.49#ibcon#first serial, iclass 13, count 0 2006.257.23:56:03.49#ibcon#enter sib2, iclass 13, count 0 2006.257.23:56:03.49#ibcon#flushed, iclass 13, count 0 2006.257.23:56:03.49#ibcon#about to write, iclass 13, count 0 2006.257.23:56:03.49#ibcon#wrote, iclass 13, count 0 2006.257.23:56:03.49#ibcon#about to read 3, iclass 13, count 0 2006.257.23:56:03.51#ibcon#read 3, iclass 13, count 0 2006.257.23:56:03.51#ibcon#about to read 4, iclass 13, count 0 2006.257.23:56:03.51#ibcon#read 4, iclass 13, count 0 2006.257.23:56:03.51#ibcon#about to read 5, iclass 13, count 0 2006.257.23:56:03.51#ibcon#read 5, iclass 13, count 0 2006.257.23:56:03.51#ibcon#about to read 6, iclass 13, count 0 2006.257.23:56:03.51#ibcon#read 6, iclass 13, count 0 2006.257.23:56:03.51#ibcon#end of sib2, iclass 13, count 0 2006.257.23:56:03.51#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:56:03.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:56:03.51#ibcon#[25=USB\r\n] 2006.257.23:56:03.51#ibcon#*before write, iclass 13, count 0 2006.257.23:56:03.51#ibcon#enter sib2, iclass 13, count 0 2006.257.23:56:03.51#ibcon#flushed, iclass 13, count 0 2006.257.23:56:03.51#ibcon#about to write, iclass 13, count 0 2006.257.23:56:03.51#ibcon#wrote, iclass 13, count 0 2006.257.23:56:03.51#ibcon#about to read 3, iclass 13, count 0 2006.257.23:56:03.51#abcon#<5=/02 2.0 5.3 21.20 801016.2\r\n> 2006.257.23:56:03.53#abcon#{5=INTERFACE CLEAR} 2006.257.23:56:03.54#ibcon#read 3, iclass 13, count 0 2006.257.23:56:03.54#ibcon#about to read 4, iclass 13, count 0 2006.257.23:56:03.54#ibcon#read 4, iclass 13, count 0 2006.257.23:56:03.54#ibcon#about to read 5, iclass 13, count 0 2006.257.23:56:03.54#ibcon#read 5, iclass 13, count 0 2006.257.23:56:03.54#ibcon#about to read 6, iclass 13, count 0 2006.257.23:56:03.54#ibcon#read 6, iclass 13, count 0 2006.257.23:56:03.54#ibcon#end of sib2, iclass 13, count 0 2006.257.23:56:03.54#ibcon#*after write, iclass 13, count 0 2006.257.23:56:03.54#ibcon#*before return 0, iclass 13, count 0 2006.257.23:56:03.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:03.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:03.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:56:03.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:56:03.54$vck44/valo=7,864.99 2006.257.23:56:03.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.23:56:03.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.23:56:03.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:03.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:56:03.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:56:03.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:56:03.54#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:56:03.54#ibcon#first serial, iclass 18, count 0 2006.257.23:56:03.54#ibcon#enter sib2, iclass 18, count 0 2006.257.23:56:03.54#ibcon#flushed, iclass 18, count 0 2006.257.23:56:03.54#ibcon#about to write, iclass 18, count 0 2006.257.23:56:03.54#ibcon#wrote, iclass 18, count 0 2006.257.23:56:03.54#ibcon#about to read 3, iclass 18, count 0 2006.257.23:56:03.56#ibcon#read 3, iclass 18, count 0 2006.257.23:56:03.56#ibcon#about to read 4, iclass 18, count 0 2006.257.23:56:03.56#ibcon#read 4, iclass 18, count 0 2006.257.23:56:03.56#ibcon#about to read 5, iclass 18, count 0 2006.257.23:56:03.56#ibcon#read 5, iclass 18, count 0 2006.257.23:56:03.56#ibcon#about to read 6, iclass 18, count 0 2006.257.23:56:03.56#ibcon#read 6, iclass 18, count 0 2006.257.23:56:03.56#ibcon#end of sib2, iclass 18, count 0 2006.257.23:56:03.56#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:56:03.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:56:03.56#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:56:03.56#ibcon#*before write, iclass 18, count 0 2006.257.23:56:03.56#ibcon#enter sib2, iclass 18, count 0 2006.257.23:56:03.56#ibcon#flushed, iclass 18, count 0 2006.257.23:56:03.56#ibcon#about to write, iclass 18, count 0 2006.257.23:56:03.56#ibcon#wrote, iclass 18, count 0 2006.257.23:56:03.56#ibcon#about to read 3, iclass 18, count 0 2006.257.23:56:03.59#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:56:03.60#ibcon#read 3, iclass 18, count 0 2006.257.23:56:03.60#ibcon#about to read 4, iclass 18, count 0 2006.257.23:56:03.60#ibcon#read 4, iclass 18, count 0 2006.257.23:56:03.60#ibcon#about to read 5, iclass 18, count 0 2006.257.23:56:03.60#ibcon#read 5, iclass 18, count 0 2006.257.23:56:03.60#ibcon#about to read 6, iclass 18, count 0 2006.257.23:56:03.60#ibcon#read 6, iclass 18, count 0 2006.257.23:56:03.60#ibcon#end of sib2, iclass 18, count 0 2006.257.23:56:03.60#ibcon#*after write, iclass 18, count 0 2006.257.23:56:03.60#ibcon#*before return 0, iclass 18, count 0 2006.257.23:56:03.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:56:03.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:56:03.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:56:03.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:56:03.60$vck44/va=7,4 2006.257.23:56:03.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.23:56:03.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.23:56:03.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:03.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:03.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:03.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:03.66#ibcon#enter wrdev, iclass 21, count 2 2006.257.23:56:03.66#ibcon#first serial, iclass 21, count 2 2006.257.23:56:03.66#ibcon#enter sib2, iclass 21, count 2 2006.257.23:56:03.66#ibcon#flushed, iclass 21, count 2 2006.257.23:56:03.66#ibcon#about to write, iclass 21, count 2 2006.257.23:56:03.66#ibcon#wrote, iclass 21, count 2 2006.257.23:56:03.66#ibcon#about to read 3, iclass 21, count 2 2006.257.23:56:03.68#ibcon#read 3, iclass 21, count 2 2006.257.23:56:03.68#ibcon#about to read 4, iclass 21, count 2 2006.257.23:56:03.68#ibcon#read 4, iclass 21, count 2 2006.257.23:56:03.68#ibcon#about to read 5, iclass 21, count 2 2006.257.23:56:03.68#ibcon#read 5, iclass 21, count 2 2006.257.23:56:03.68#ibcon#about to read 6, iclass 21, count 2 2006.257.23:56:03.68#ibcon#read 6, iclass 21, count 2 2006.257.23:56:03.68#ibcon#end of sib2, iclass 21, count 2 2006.257.23:56:03.68#ibcon#*mode == 0, iclass 21, count 2 2006.257.23:56:03.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.23:56:03.68#ibcon#[25=AT07-04\r\n] 2006.257.23:56:03.68#ibcon#*before write, iclass 21, count 2 2006.257.23:56:03.68#ibcon#enter sib2, iclass 21, count 2 2006.257.23:56:03.68#ibcon#flushed, iclass 21, count 2 2006.257.23:56:03.68#ibcon#about to write, iclass 21, count 2 2006.257.23:56:03.68#ibcon#wrote, iclass 21, count 2 2006.257.23:56:03.68#ibcon#about to read 3, iclass 21, count 2 2006.257.23:56:03.71#ibcon#read 3, iclass 21, count 2 2006.257.23:56:03.71#ibcon#about to read 4, iclass 21, count 2 2006.257.23:56:03.71#ibcon#read 4, iclass 21, count 2 2006.257.23:56:03.71#ibcon#about to read 5, iclass 21, count 2 2006.257.23:56:03.71#ibcon#read 5, iclass 21, count 2 2006.257.23:56:03.71#ibcon#about to read 6, iclass 21, count 2 2006.257.23:56:03.71#ibcon#read 6, iclass 21, count 2 2006.257.23:56:03.71#ibcon#end of sib2, iclass 21, count 2 2006.257.23:56:03.71#ibcon#*after write, iclass 21, count 2 2006.257.23:56:03.71#ibcon#*before return 0, iclass 21, count 2 2006.257.23:56:03.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:03.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:03.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.23:56:03.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:03.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:03.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:03.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:03.83#ibcon#enter wrdev, iclass 21, count 0 2006.257.23:56:03.83#ibcon#first serial, iclass 21, count 0 2006.257.23:56:03.83#ibcon#enter sib2, iclass 21, count 0 2006.257.23:56:03.83#ibcon#flushed, iclass 21, count 0 2006.257.23:56:03.83#ibcon#about to write, iclass 21, count 0 2006.257.23:56:03.83#ibcon#wrote, iclass 21, count 0 2006.257.23:56:03.83#ibcon#about to read 3, iclass 21, count 0 2006.257.23:56:03.85#ibcon#read 3, iclass 21, count 0 2006.257.23:56:03.85#ibcon#about to read 4, iclass 21, count 0 2006.257.23:56:03.85#ibcon#read 4, iclass 21, count 0 2006.257.23:56:03.85#ibcon#about to read 5, iclass 21, count 0 2006.257.23:56:03.85#ibcon#read 5, iclass 21, count 0 2006.257.23:56:03.85#ibcon#about to read 6, iclass 21, count 0 2006.257.23:56:03.85#ibcon#read 6, iclass 21, count 0 2006.257.23:56:03.85#ibcon#end of sib2, iclass 21, count 0 2006.257.23:56:03.85#ibcon#*mode == 0, iclass 21, count 0 2006.257.23:56:03.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.23:56:03.85#ibcon#[25=USB\r\n] 2006.257.23:56:03.85#ibcon#*before write, iclass 21, count 0 2006.257.23:56:03.85#ibcon#enter sib2, iclass 21, count 0 2006.257.23:56:03.85#ibcon#flushed, iclass 21, count 0 2006.257.23:56:03.85#ibcon#about to write, iclass 21, count 0 2006.257.23:56:03.85#ibcon#wrote, iclass 21, count 0 2006.257.23:56:03.85#ibcon#about to read 3, iclass 21, count 0 2006.257.23:56:03.88#ibcon#read 3, iclass 21, count 0 2006.257.23:56:03.88#ibcon#about to read 4, iclass 21, count 0 2006.257.23:56:03.88#ibcon#read 4, iclass 21, count 0 2006.257.23:56:03.88#ibcon#about to read 5, iclass 21, count 0 2006.257.23:56:03.88#ibcon#read 5, iclass 21, count 0 2006.257.23:56:03.88#ibcon#about to read 6, iclass 21, count 0 2006.257.23:56:03.88#ibcon#read 6, iclass 21, count 0 2006.257.23:56:03.88#ibcon#end of sib2, iclass 21, count 0 2006.257.23:56:03.88#ibcon#*after write, iclass 21, count 0 2006.257.23:56:03.88#ibcon#*before return 0, iclass 21, count 0 2006.257.23:56:03.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:03.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:03.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.23:56:03.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.23:56:03.88$vck44/valo=8,884.99 2006.257.23:56:03.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.23:56:03.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.23:56:03.88#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:03.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:03.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:03.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:03.88#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:56:03.88#ibcon#first serial, iclass 23, count 0 2006.257.23:56:03.88#ibcon#enter sib2, iclass 23, count 0 2006.257.23:56:03.88#ibcon#flushed, iclass 23, count 0 2006.257.23:56:03.88#ibcon#about to write, iclass 23, count 0 2006.257.23:56:03.88#ibcon#wrote, iclass 23, count 0 2006.257.23:56:03.88#ibcon#about to read 3, iclass 23, count 0 2006.257.23:56:03.90#ibcon#read 3, iclass 23, count 0 2006.257.23:56:03.90#ibcon#about to read 4, iclass 23, count 0 2006.257.23:56:03.90#ibcon#read 4, iclass 23, count 0 2006.257.23:56:03.90#ibcon#about to read 5, iclass 23, count 0 2006.257.23:56:03.90#ibcon#read 5, iclass 23, count 0 2006.257.23:56:03.90#ibcon#about to read 6, iclass 23, count 0 2006.257.23:56:03.90#ibcon#read 6, iclass 23, count 0 2006.257.23:56:03.90#ibcon#end of sib2, iclass 23, count 0 2006.257.23:56:03.90#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:56:03.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:56:03.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:56:03.90#ibcon#*before write, iclass 23, count 0 2006.257.23:56:03.90#ibcon#enter sib2, iclass 23, count 0 2006.257.23:56:03.90#ibcon#flushed, iclass 23, count 0 2006.257.23:56:03.90#ibcon#about to write, iclass 23, count 0 2006.257.23:56:03.90#ibcon#wrote, iclass 23, count 0 2006.257.23:56:03.90#ibcon#about to read 3, iclass 23, count 0 2006.257.23:56:03.94#ibcon#read 3, iclass 23, count 0 2006.257.23:56:03.94#ibcon#about to read 4, iclass 23, count 0 2006.257.23:56:03.94#ibcon#read 4, iclass 23, count 0 2006.257.23:56:03.94#ibcon#about to read 5, iclass 23, count 0 2006.257.23:56:03.94#ibcon#read 5, iclass 23, count 0 2006.257.23:56:03.94#ibcon#about to read 6, iclass 23, count 0 2006.257.23:56:03.94#ibcon#read 6, iclass 23, count 0 2006.257.23:56:03.94#ibcon#end of sib2, iclass 23, count 0 2006.257.23:56:03.94#ibcon#*after write, iclass 23, count 0 2006.257.23:56:03.94#ibcon#*before return 0, iclass 23, count 0 2006.257.23:56:03.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:03.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:03.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:56:03.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:56:03.94$vck44/va=8,4 2006.257.23:56:03.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.257.23:56:03.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.257.23:56:03.94#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:03.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:56:04.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:56:04.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:56:04.00#ibcon#enter wrdev, iclass 25, count 2 2006.257.23:56:04.00#ibcon#first serial, iclass 25, count 2 2006.257.23:56:04.00#ibcon#enter sib2, iclass 25, count 2 2006.257.23:56:04.00#ibcon#flushed, iclass 25, count 2 2006.257.23:56:04.00#ibcon#about to write, iclass 25, count 2 2006.257.23:56:04.00#ibcon#wrote, iclass 25, count 2 2006.257.23:56:04.00#ibcon#about to read 3, iclass 25, count 2 2006.257.23:56:04.02#ibcon#read 3, iclass 25, count 2 2006.257.23:56:04.02#ibcon#about to read 4, iclass 25, count 2 2006.257.23:56:04.02#ibcon#read 4, iclass 25, count 2 2006.257.23:56:04.02#ibcon#about to read 5, iclass 25, count 2 2006.257.23:56:04.02#ibcon#read 5, iclass 25, count 2 2006.257.23:56:04.02#ibcon#about to read 6, iclass 25, count 2 2006.257.23:56:04.02#ibcon#read 6, iclass 25, count 2 2006.257.23:56:04.02#ibcon#end of sib2, iclass 25, count 2 2006.257.23:56:04.02#ibcon#*mode == 0, iclass 25, count 2 2006.257.23:56:04.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.257.23:56:04.02#ibcon#[25=AT08-04\r\n] 2006.257.23:56:04.02#ibcon#*before write, iclass 25, count 2 2006.257.23:56:04.02#ibcon#enter sib2, iclass 25, count 2 2006.257.23:56:04.02#ibcon#flushed, iclass 25, count 2 2006.257.23:56:04.02#ibcon#about to write, iclass 25, count 2 2006.257.23:56:04.02#ibcon#wrote, iclass 25, count 2 2006.257.23:56:04.02#ibcon#about to read 3, iclass 25, count 2 2006.257.23:56:04.05#ibcon#read 3, iclass 25, count 2 2006.257.23:56:04.05#ibcon#about to read 4, iclass 25, count 2 2006.257.23:56:04.05#ibcon#read 4, iclass 25, count 2 2006.257.23:56:04.05#ibcon#about to read 5, iclass 25, count 2 2006.257.23:56:04.05#ibcon#read 5, iclass 25, count 2 2006.257.23:56:04.05#ibcon#about to read 6, iclass 25, count 2 2006.257.23:56:04.05#ibcon#read 6, iclass 25, count 2 2006.257.23:56:04.05#ibcon#end of sib2, iclass 25, count 2 2006.257.23:56:04.05#ibcon#*after write, iclass 25, count 2 2006.257.23:56:04.05#ibcon#*before return 0, iclass 25, count 2 2006.257.23:56:04.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:56:04.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.257.23:56:04.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.257.23:56:04.05#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:04.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:56:04.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:56:04.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:56:04.17#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:56:04.17#ibcon#first serial, iclass 25, count 0 2006.257.23:56:04.17#ibcon#enter sib2, iclass 25, count 0 2006.257.23:56:04.17#ibcon#flushed, iclass 25, count 0 2006.257.23:56:04.17#ibcon#about to write, iclass 25, count 0 2006.257.23:56:04.17#ibcon#wrote, iclass 25, count 0 2006.257.23:56:04.17#ibcon#about to read 3, iclass 25, count 0 2006.257.23:56:04.19#ibcon#read 3, iclass 25, count 0 2006.257.23:56:04.19#ibcon#about to read 4, iclass 25, count 0 2006.257.23:56:04.19#ibcon#read 4, iclass 25, count 0 2006.257.23:56:04.19#ibcon#about to read 5, iclass 25, count 0 2006.257.23:56:04.19#ibcon#read 5, iclass 25, count 0 2006.257.23:56:04.19#ibcon#about to read 6, iclass 25, count 0 2006.257.23:56:04.19#ibcon#read 6, iclass 25, count 0 2006.257.23:56:04.19#ibcon#end of sib2, iclass 25, count 0 2006.257.23:56:04.19#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:56:04.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:56:04.19#ibcon#[25=USB\r\n] 2006.257.23:56:04.19#ibcon#*before write, iclass 25, count 0 2006.257.23:56:04.19#ibcon#enter sib2, iclass 25, count 0 2006.257.23:56:04.19#ibcon#flushed, iclass 25, count 0 2006.257.23:56:04.19#ibcon#about to write, iclass 25, count 0 2006.257.23:56:04.19#ibcon#wrote, iclass 25, count 0 2006.257.23:56:04.19#ibcon#about to read 3, iclass 25, count 0 2006.257.23:56:04.22#ibcon#read 3, iclass 25, count 0 2006.257.23:56:04.22#ibcon#about to read 4, iclass 25, count 0 2006.257.23:56:04.22#ibcon#read 4, iclass 25, count 0 2006.257.23:56:04.22#ibcon#about to read 5, iclass 25, count 0 2006.257.23:56:04.22#ibcon#read 5, iclass 25, count 0 2006.257.23:56:04.22#ibcon#about to read 6, iclass 25, count 0 2006.257.23:56:04.22#ibcon#read 6, iclass 25, count 0 2006.257.23:56:04.22#ibcon#end of sib2, iclass 25, count 0 2006.257.23:56:04.22#ibcon#*after write, iclass 25, count 0 2006.257.23:56:04.22#ibcon#*before return 0, iclass 25, count 0 2006.257.23:56:04.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:56:04.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.257.23:56:04.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:56:04.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:56:04.22$vck44/vblo=1,629.99 2006.257.23:56:04.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.257.23:56:04.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.257.23:56:04.22#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:04.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:04.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:04.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:04.22#ibcon#enter wrdev, iclass 27, count 0 2006.257.23:56:04.22#ibcon#first serial, iclass 27, count 0 2006.257.23:56:04.22#ibcon#enter sib2, iclass 27, count 0 2006.257.23:56:04.22#ibcon#flushed, iclass 27, count 0 2006.257.23:56:04.22#ibcon#about to write, iclass 27, count 0 2006.257.23:56:04.22#ibcon#wrote, iclass 27, count 0 2006.257.23:56:04.22#ibcon#about to read 3, iclass 27, count 0 2006.257.23:56:04.24#ibcon#read 3, iclass 27, count 0 2006.257.23:56:04.24#ibcon#about to read 4, iclass 27, count 0 2006.257.23:56:04.24#ibcon#read 4, iclass 27, count 0 2006.257.23:56:04.24#ibcon#about to read 5, iclass 27, count 0 2006.257.23:56:04.24#ibcon#read 5, iclass 27, count 0 2006.257.23:56:04.24#ibcon#about to read 6, iclass 27, count 0 2006.257.23:56:04.24#ibcon#read 6, iclass 27, count 0 2006.257.23:56:04.24#ibcon#end of sib2, iclass 27, count 0 2006.257.23:56:04.24#ibcon#*mode == 0, iclass 27, count 0 2006.257.23:56:04.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.257.23:56:04.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:56:04.24#ibcon#*before write, iclass 27, count 0 2006.257.23:56:04.24#ibcon#enter sib2, iclass 27, count 0 2006.257.23:56:04.24#ibcon#flushed, iclass 27, count 0 2006.257.23:56:04.24#ibcon#about to write, iclass 27, count 0 2006.257.23:56:04.24#ibcon#wrote, iclass 27, count 0 2006.257.23:56:04.24#ibcon#about to read 3, iclass 27, count 0 2006.257.23:56:04.28#ibcon#read 3, iclass 27, count 0 2006.257.23:56:04.28#ibcon#about to read 4, iclass 27, count 0 2006.257.23:56:04.28#ibcon#read 4, iclass 27, count 0 2006.257.23:56:04.28#ibcon#about to read 5, iclass 27, count 0 2006.257.23:56:04.28#ibcon#read 5, iclass 27, count 0 2006.257.23:56:04.28#ibcon#about to read 6, iclass 27, count 0 2006.257.23:56:04.28#ibcon#read 6, iclass 27, count 0 2006.257.23:56:04.28#ibcon#end of sib2, iclass 27, count 0 2006.257.23:56:04.28#ibcon#*after write, iclass 27, count 0 2006.257.23:56:04.28#ibcon#*before return 0, iclass 27, count 0 2006.257.23:56:04.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:04.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.257.23:56:04.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.257.23:56:04.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.257.23:56:04.28$vck44/vb=1,4 2006.257.23:56:04.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.257.23:56:04.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.257.23:56:04.28#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:04.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:04.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:04.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:04.28#ibcon#enter wrdev, iclass 29, count 2 2006.257.23:56:04.28#ibcon#first serial, iclass 29, count 2 2006.257.23:56:04.28#ibcon#enter sib2, iclass 29, count 2 2006.257.23:56:04.28#ibcon#flushed, iclass 29, count 2 2006.257.23:56:04.28#ibcon#about to write, iclass 29, count 2 2006.257.23:56:04.28#ibcon#wrote, iclass 29, count 2 2006.257.23:56:04.28#ibcon#about to read 3, iclass 29, count 2 2006.257.23:56:04.30#ibcon#read 3, iclass 29, count 2 2006.257.23:56:04.30#ibcon#about to read 4, iclass 29, count 2 2006.257.23:56:04.30#ibcon#read 4, iclass 29, count 2 2006.257.23:56:04.30#ibcon#about to read 5, iclass 29, count 2 2006.257.23:56:04.30#ibcon#read 5, iclass 29, count 2 2006.257.23:56:04.30#ibcon#about to read 6, iclass 29, count 2 2006.257.23:56:04.30#ibcon#read 6, iclass 29, count 2 2006.257.23:56:04.30#ibcon#end of sib2, iclass 29, count 2 2006.257.23:56:04.30#ibcon#*mode == 0, iclass 29, count 2 2006.257.23:56:04.30#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.257.23:56:04.30#ibcon#[27=AT01-04\r\n] 2006.257.23:56:04.30#ibcon#*before write, iclass 29, count 2 2006.257.23:56:04.30#ibcon#enter sib2, iclass 29, count 2 2006.257.23:56:04.30#ibcon#flushed, iclass 29, count 2 2006.257.23:56:04.30#ibcon#about to write, iclass 29, count 2 2006.257.23:56:04.30#ibcon#wrote, iclass 29, count 2 2006.257.23:56:04.30#ibcon#about to read 3, iclass 29, count 2 2006.257.23:56:04.33#ibcon#read 3, iclass 29, count 2 2006.257.23:56:04.33#ibcon#about to read 4, iclass 29, count 2 2006.257.23:56:04.33#ibcon#read 4, iclass 29, count 2 2006.257.23:56:04.33#ibcon#about to read 5, iclass 29, count 2 2006.257.23:56:04.33#ibcon#read 5, iclass 29, count 2 2006.257.23:56:04.33#ibcon#about to read 6, iclass 29, count 2 2006.257.23:56:04.33#ibcon#read 6, iclass 29, count 2 2006.257.23:56:04.33#ibcon#end of sib2, iclass 29, count 2 2006.257.23:56:04.33#ibcon#*after write, iclass 29, count 2 2006.257.23:56:04.33#ibcon#*before return 0, iclass 29, count 2 2006.257.23:56:04.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:04.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.257.23:56:04.33#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.257.23:56:04.33#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:04.33#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:04.45#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:04.45#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:04.45#ibcon#enter wrdev, iclass 29, count 0 2006.257.23:56:04.45#ibcon#first serial, iclass 29, count 0 2006.257.23:56:04.45#ibcon#enter sib2, iclass 29, count 0 2006.257.23:56:04.45#ibcon#flushed, iclass 29, count 0 2006.257.23:56:04.45#ibcon#about to write, iclass 29, count 0 2006.257.23:56:04.45#ibcon#wrote, iclass 29, count 0 2006.257.23:56:04.45#ibcon#about to read 3, iclass 29, count 0 2006.257.23:56:04.47#ibcon#read 3, iclass 29, count 0 2006.257.23:56:04.47#ibcon#about to read 4, iclass 29, count 0 2006.257.23:56:04.47#ibcon#read 4, iclass 29, count 0 2006.257.23:56:04.47#ibcon#about to read 5, iclass 29, count 0 2006.257.23:56:04.47#ibcon#read 5, iclass 29, count 0 2006.257.23:56:04.47#ibcon#about to read 6, iclass 29, count 0 2006.257.23:56:04.47#ibcon#read 6, iclass 29, count 0 2006.257.23:56:04.47#ibcon#end of sib2, iclass 29, count 0 2006.257.23:56:04.47#ibcon#*mode == 0, iclass 29, count 0 2006.257.23:56:04.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.257.23:56:04.47#ibcon#[27=USB\r\n] 2006.257.23:56:04.47#ibcon#*before write, iclass 29, count 0 2006.257.23:56:04.47#ibcon#enter sib2, iclass 29, count 0 2006.257.23:56:04.47#ibcon#flushed, iclass 29, count 0 2006.257.23:56:04.47#ibcon#about to write, iclass 29, count 0 2006.257.23:56:04.47#ibcon#wrote, iclass 29, count 0 2006.257.23:56:04.47#ibcon#about to read 3, iclass 29, count 0 2006.257.23:56:04.50#ibcon#read 3, iclass 29, count 0 2006.257.23:56:04.50#ibcon#about to read 4, iclass 29, count 0 2006.257.23:56:04.50#ibcon#read 4, iclass 29, count 0 2006.257.23:56:04.50#ibcon#about to read 5, iclass 29, count 0 2006.257.23:56:04.50#ibcon#read 5, iclass 29, count 0 2006.257.23:56:04.50#ibcon#about to read 6, iclass 29, count 0 2006.257.23:56:04.50#ibcon#read 6, iclass 29, count 0 2006.257.23:56:04.50#ibcon#end of sib2, iclass 29, count 0 2006.257.23:56:04.50#ibcon#*after write, iclass 29, count 0 2006.257.23:56:04.50#ibcon#*before return 0, iclass 29, count 0 2006.257.23:56:04.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:04.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.257.23:56:04.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.257.23:56:04.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.257.23:56:04.50$vck44/vblo=2,634.99 2006.257.23:56:04.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.257.23:56:04.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.257.23:56:04.50#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:04.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:04.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:04.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:04.50#ibcon#enter wrdev, iclass 31, count 0 2006.257.23:56:04.50#ibcon#first serial, iclass 31, count 0 2006.257.23:56:04.50#ibcon#enter sib2, iclass 31, count 0 2006.257.23:56:04.50#ibcon#flushed, iclass 31, count 0 2006.257.23:56:04.50#ibcon#about to write, iclass 31, count 0 2006.257.23:56:04.50#ibcon#wrote, iclass 31, count 0 2006.257.23:56:04.50#ibcon#about to read 3, iclass 31, count 0 2006.257.23:56:04.52#ibcon#read 3, iclass 31, count 0 2006.257.23:56:04.52#ibcon#about to read 4, iclass 31, count 0 2006.257.23:56:04.52#ibcon#read 4, iclass 31, count 0 2006.257.23:56:04.52#ibcon#about to read 5, iclass 31, count 0 2006.257.23:56:04.52#ibcon#read 5, iclass 31, count 0 2006.257.23:56:04.52#ibcon#about to read 6, iclass 31, count 0 2006.257.23:56:04.52#ibcon#read 6, iclass 31, count 0 2006.257.23:56:04.52#ibcon#end of sib2, iclass 31, count 0 2006.257.23:56:04.52#ibcon#*mode == 0, iclass 31, count 0 2006.257.23:56:04.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.257.23:56:04.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:56:04.52#ibcon#*before write, iclass 31, count 0 2006.257.23:56:04.52#ibcon#enter sib2, iclass 31, count 0 2006.257.23:56:04.52#ibcon#flushed, iclass 31, count 0 2006.257.23:56:04.52#ibcon#about to write, iclass 31, count 0 2006.257.23:56:04.52#ibcon#wrote, iclass 31, count 0 2006.257.23:56:04.52#ibcon#about to read 3, iclass 31, count 0 2006.257.23:56:04.56#ibcon#read 3, iclass 31, count 0 2006.257.23:56:04.56#ibcon#about to read 4, iclass 31, count 0 2006.257.23:56:04.56#ibcon#read 4, iclass 31, count 0 2006.257.23:56:04.56#ibcon#about to read 5, iclass 31, count 0 2006.257.23:56:04.56#ibcon#read 5, iclass 31, count 0 2006.257.23:56:04.56#ibcon#about to read 6, iclass 31, count 0 2006.257.23:56:04.56#ibcon#read 6, iclass 31, count 0 2006.257.23:56:04.56#ibcon#end of sib2, iclass 31, count 0 2006.257.23:56:04.56#ibcon#*after write, iclass 31, count 0 2006.257.23:56:04.56#ibcon#*before return 0, iclass 31, count 0 2006.257.23:56:04.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:04.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.257.23:56:04.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.257.23:56:04.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.257.23:56:04.56$vck44/vb=2,5 2006.257.23:56:04.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.257.23:56:04.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.257.23:56:04.56#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:04.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:04.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:04.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:04.62#ibcon#enter wrdev, iclass 33, count 2 2006.257.23:56:04.62#ibcon#first serial, iclass 33, count 2 2006.257.23:56:04.62#ibcon#enter sib2, iclass 33, count 2 2006.257.23:56:04.62#ibcon#flushed, iclass 33, count 2 2006.257.23:56:04.62#ibcon#about to write, iclass 33, count 2 2006.257.23:56:04.62#ibcon#wrote, iclass 33, count 2 2006.257.23:56:04.62#ibcon#about to read 3, iclass 33, count 2 2006.257.23:56:04.64#ibcon#read 3, iclass 33, count 2 2006.257.23:56:04.64#ibcon#about to read 4, iclass 33, count 2 2006.257.23:56:04.64#ibcon#read 4, iclass 33, count 2 2006.257.23:56:04.64#ibcon#about to read 5, iclass 33, count 2 2006.257.23:56:04.64#ibcon#read 5, iclass 33, count 2 2006.257.23:56:04.64#ibcon#about to read 6, iclass 33, count 2 2006.257.23:56:04.64#ibcon#read 6, iclass 33, count 2 2006.257.23:56:04.64#ibcon#end of sib2, iclass 33, count 2 2006.257.23:56:04.64#ibcon#*mode == 0, iclass 33, count 2 2006.257.23:56:04.64#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.257.23:56:04.64#ibcon#[27=AT02-05\r\n] 2006.257.23:56:04.64#ibcon#*before write, iclass 33, count 2 2006.257.23:56:04.64#ibcon#enter sib2, iclass 33, count 2 2006.257.23:56:04.64#ibcon#flushed, iclass 33, count 2 2006.257.23:56:04.64#ibcon#about to write, iclass 33, count 2 2006.257.23:56:04.64#ibcon#wrote, iclass 33, count 2 2006.257.23:56:04.64#ibcon#about to read 3, iclass 33, count 2 2006.257.23:56:04.67#ibcon#read 3, iclass 33, count 2 2006.257.23:56:04.67#ibcon#about to read 4, iclass 33, count 2 2006.257.23:56:04.67#ibcon#read 4, iclass 33, count 2 2006.257.23:56:04.67#ibcon#about to read 5, iclass 33, count 2 2006.257.23:56:04.67#ibcon#read 5, iclass 33, count 2 2006.257.23:56:04.67#ibcon#about to read 6, iclass 33, count 2 2006.257.23:56:04.67#ibcon#read 6, iclass 33, count 2 2006.257.23:56:04.67#ibcon#end of sib2, iclass 33, count 2 2006.257.23:56:04.67#ibcon#*after write, iclass 33, count 2 2006.257.23:56:04.67#ibcon#*before return 0, iclass 33, count 2 2006.257.23:56:04.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:04.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.257.23:56:04.67#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.257.23:56:04.67#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:04.67#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:04.79#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:04.79#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:04.79#ibcon#enter wrdev, iclass 33, count 0 2006.257.23:56:04.79#ibcon#first serial, iclass 33, count 0 2006.257.23:56:04.79#ibcon#enter sib2, iclass 33, count 0 2006.257.23:56:04.79#ibcon#flushed, iclass 33, count 0 2006.257.23:56:04.79#ibcon#about to write, iclass 33, count 0 2006.257.23:56:04.79#ibcon#wrote, iclass 33, count 0 2006.257.23:56:04.79#ibcon#about to read 3, iclass 33, count 0 2006.257.23:56:04.81#ibcon#read 3, iclass 33, count 0 2006.257.23:56:04.81#ibcon#about to read 4, iclass 33, count 0 2006.257.23:56:04.81#ibcon#read 4, iclass 33, count 0 2006.257.23:56:04.81#ibcon#about to read 5, iclass 33, count 0 2006.257.23:56:04.81#ibcon#read 5, iclass 33, count 0 2006.257.23:56:04.81#ibcon#about to read 6, iclass 33, count 0 2006.257.23:56:04.81#ibcon#read 6, iclass 33, count 0 2006.257.23:56:04.81#ibcon#end of sib2, iclass 33, count 0 2006.257.23:56:04.81#ibcon#*mode == 0, iclass 33, count 0 2006.257.23:56:04.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.257.23:56:04.81#ibcon#[27=USB\r\n] 2006.257.23:56:04.81#ibcon#*before write, iclass 33, count 0 2006.257.23:56:04.81#ibcon#enter sib2, iclass 33, count 0 2006.257.23:56:04.81#ibcon#flushed, iclass 33, count 0 2006.257.23:56:04.81#ibcon#about to write, iclass 33, count 0 2006.257.23:56:04.81#ibcon#wrote, iclass 33, count 0 2006.257.23:56:04.81#ibcon#about to read 3, iclass 33, count 0 2006.257.23:56:04.84#ibcon#read 3, iclass 33, count 0 2006.257.23:56:04.84#ibcon#about to read 4, iclass 33, count 0 2006.257.23:56:04.84#ibcon#read 4, iclass 33, count 0 2006.257.23:56:04.84#ibcon#about to read 5, iclass 33, count 0 2006.257.23:56:04.84#ibcon#read 5, iclass 33, count 0 2006.257.23:56:04.84#ibcon#about to read 6, iclass 33, count 0 2006.257.23:56:04.84#ibcon#read 6, iclass 33, count 0 2006.257.23:56:04.84#ibcon#end of sib2, iclass 33, count 0 2006.257.23:56:04.84#ibcon#*after write, iclass 33, count 0 2006.257.23:56:04.84#ibcon#*before return 0, iclass 33, count 0 2006.257.23:56:04.84#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:04.84#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.257.23:56:04.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.257.23:56:04.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.257.23:56:04.84$vck44/vblo=3,649.99 2006.257.23:56:04.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.257.23:56:04.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.257.23:56:04.84#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:04.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:04.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:04.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:04.84#ibcon#enter wrdev, iclass 35, count 0 2006.257.23:56:04.84#ibcon#first serial, iclass 35, count 0 2006.257.23:56:04.84#ibcon#enter sib2, iclass 35, count 0 2006.257.23:56:04.84#ibcon#flushed, iclass 35, count 0 2006.257.23:56:04.84#ibcon#about to write, iclass 35, count 0 2006.257.23:56:04.84#ibcon#wrote, iclass 35, count 0 2006.257.23:56:04.84#ibcon#about to read 3, iclass 35, count 0 2006.257.23:56:04.86#ibcon#read 3, iclass 35, count 0 2006.257.23:56:04.86#ibcon#about to read 4, iclass 35, count 0 2006.257.23:56:04.86#ibcon#read 4, iclass 35, count 0 2006.257.23:56:04.86#ibcon#about to read 5, iclass 35, count 0 2006.257.23:56:04.86#ibcon#read 5, iclass 35, count 0 2006.257.23:56:04.86#ibcon#about to read 6, iclass 35, count 0 2006.257.23:56:04.86#ibcon#read 6, iclass 35, count 0 2006.257.23:56:04.86#ibcon#end of sib2, iclass 35, count 0 2006.257.23:56:04.86#ibcon#*mode == 0, iclass 35, count 0 2006.257.23:56:04.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.257.23:56:04.86#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:56:04.86#ibcon#*before write, iclass 35, count 0 2006.257.23:56:04.86#ibcon#enter sib2, iclass 35, count 0 2006.257.23:56:04.86#ibcon#flushed, iclass 35, count 0 2006.257.23:56:04.86#ibcon#about to write, iclass 35, count 0 2006.257.23:56:04.86#ibcon#wrote, iclass 35, count 0 2006.257.23:56:04.86#ibcon#about to read 3, iclass 35, count 0 2006.257.23:56:04.90#ibcon#read 3, iclass 35, count 0 2006.257.23:56:04.90#ibcon#about to read 4, iclass 35, count 0 2006.257.23:56:04.90#ibcon#read 4, iclass 35, count 0 2006.257.23:56:04.90#ibcon#about to read 5, iclass 35, count 0 2006.257.23:56:04.90#ibcon#read 5, iclass 35, count 0 2006.257.23:56:04.90#ibcon#about to read 6, iclass 35, count 0 2006.257.23:56:04.90#ibcon#read 6, iclass 35, count 0 2006.257.23:56:04.90#ibcon#end of sib2, iclass 35, count 0 2006.257.23:56:04.90#ibcon#*after write, iclass 35, count 0 2006.257.23:56:04.90#ibcon#*before return 0, iclass 35, count 0 2006.257.23:56:04.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:04.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.257.23:56:04.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.257.23:56:04.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.257.23:56:04.90$vck44/vb=3,4 2006.257.23:56:04.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.257.23:56:04.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.257.23:56:04.90#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:04.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:04.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:04.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:04.96#ibcon#enter wrdev, iclass 37, count 2 2006.257.23:56:04.96#ibcon#first serial, iclass 37, count 2 2006.257.23:56:04.96#ibcon#enter sib2, iclass 37, count 2 2006.257.23:56:04.96#ibcon#flushed, iclass 37, count 2 2006.257.23:56:04.96#ibcon#about to write, iclass 37, count 2 2006.257.23:56:04.96#ibcon#wrote, iclass 37, count 2 2006.257.23:56:04.96#ibcon#about to read 3, iclass 37, count 2 2006.257.23:56:04.98#ibcon#read 3, iclass 37, count 2 2006.257.23:56:04.98#ibcon#about to read 4, iclass 37, count 2 2006.257.23:56:04.98#ibcon#read 4, iclass 37, count 2 2006.257.23:56:04.98#ibcon#about to read 5, iclass 37, count 2 2006.257.23:56:04.98#ibcon#read 5, iclass 37, count 2 2006.257.23:56:04.98#ibcon#about to read 6, iclass 37, count 2 2006.257.23:56:04.98#ibcon#read 6, iclass 37, count 2 2006.257.23:56:04.98#ibcon#end of sib2, iclass 37, count 2 2006.257.23:56:04.98#ibcon#*mode == 0, iclass 37, count 2 2006.257.23:56:04.98#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.257.23:56:04.98#ibcon#[27=AT03-04\r\n] 2006.257.23:56:04.98#ibcon#*before write, iclass 37, count 2 2006.257.23:56:04.98#ibcon#enter sib2, iclass 37, count 2 2006.257.23:56:04.98#ibcon#flushed, iclass 37, count 2 2006.257.23:56:04.98#ibcon#about to write, iclass 37, count 2 2006.257.23:56:04.98#ibcon#wrote, iclass 37, count 2 2006.257.23:56:04.98#ibcon#about to read 3, iclass 37, count 2 2006.257.23:56:05.01#ibcon#read 3, iclass 37, count 2 2006.257.23:56:05.01#ibcon#about to read 4, iclass 37, count 2 2006.257.23:56:05.01#ibcon#read 4, iclass 37, count 2 2006.257.23:56:05.01#ibcon#about to read 5, iclass 37, count 2 2006.257.23:56:05.01#ibcon#read 5, iclass 37, count 2 2006.257.23:56:05.01#ibcon#about to read 6, iclass 37, count 2 2006.257.23:56:05.01#ibcon#read 6, iclass 37, count 2 2006.257.23:56:05.01#ibcon#end of sib2, iclass 37, count 2 2006.257.23:56:05.01#ibcon#*after write, iclass 37, count 2 2006.257.23:56:05.01#ibcon#*before return 0, iclass 37, count 2 2006.257.23:56:05.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:05.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.257.23:56:05.01#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.257.23:56:05.01#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:05.01#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:05.13#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:05.13#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:05.13#ibcon#enter wrdev, iclass 37, count 0 2006.257.23:56:05.13#ibcon#first serial, iclass 37, count 0 2006.257.23:56:05.13#ibcon#enter sib2, iclass 37, count 0 2006.257.23:56:05.13#ibcon#flushed, iclass 37, count 0 2006.257.23:56:05.13#ibcon#about to write, iclass 37, count 0 2006.257.23:56:05.13#ibcon#wrote, iclass 37, count 0 2006.257.23:56:05.13#ibcon#about to read 3, iclass 37, count 0 2006.257.23:56:05.15#ibcon#read 3, iclass 37, count 0 2006.257.23:56:05.15#ibcon#about to read 4, iclass 37, count 0 2006.257.23:56:05.15#ibcon#read 4, iclass 37, count 0 2006.257.23:56:05.15#ibcon#about to read 5, iclass 37, count 0 2006.257.23:56:05.15#ibcon#read 5, iclass 37, count 0 2006.257.23:56:05.15#ibcon#about to read 6, iclass 37, count 0 2006.257.23:56:05.15#ibcon#read 6, iclass 37, count 0 2006.257.23:56:05.15#ibcon#end of sib2, iclass 37, count 0 2006.257.23:56:05.15#ibcon#*mode == 0, iclass 37, count 0 2006.257.23:56:05.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.257.23:56:05.15#ibcon#[27=USB\r\n] 2006.257.23:56:05.15#ibcon#*before write, iclass 37, count 0 2006.257.23:56:05.15#ibcon#enter sib2, iclass 37, count 0 2006.257.23:56:05.15#ibcon#flushed, iclass 37, count 0 2006.257.23:56:05.15#ibcon#about to write, iclass 37, count 0 2006.257.23:56:05.15#ibcon#wrote, iclass 37, count 0 2006.257.23:56:05.15#ibcon#about to read 3, iclass 37, count 0 2006.257.23:56:05.18#ibcon#read 3, iclass 37, count 0 2006.257.23:56:05.18#ibcon#about to read 4, iclass 37, count 0 2006.257.23:56:05.18#ibcon#read 4, iclass 37, count 0 2006.257.23:56:05.18#ibcon#about to read 5, iclass 37, count 0 2006.257.23:56:05.18#ibcon#read 5, iclass 37, count 0 2006.257.23:56:05.18#ibcon#about to read 6, iclass 37, count 0 2006.257.23:56:05.18#ibcon#read 6, iclass 37, count 0 2006.257.23:56:05.18#ibcon#end of sib2, iclass 37, count 0 2006.257.23:56:05.18#ibcon#*after write, iclass 37, count 0 2006.257.23:56:05.18#ibcon#*before return 0, iclass 37, count 0 2006.257.23:56:05.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:05.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.257.23:56:05.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.257.23:56:05.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.257.23:56:05.18$vck44/vblo=4,679.99 2006.257.23:56:05.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.257.23:56:05.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.257.23:56:05.18#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:05.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:05.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:05.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:05.18#ibcon#enter wrdev, iclass 39, count 0 2006.257.23:56:05.18#ibcon#first serial, iclass 39, count 0 2006.257.23:56:05.18#ibcon#enter sib2, iclass 39, count 0 2006.257.23:56:05.18#ibcon#flushed, iclass 39, count 0 2006.257.23:56:05.18#ibcon#about to write, iclass 39, count 0 2006.257.23:56:05.18#ibcon#wrote, iclass 39, count 0 2006.257.23:56:05.18#ibcon#about to read 3, iclass 39, count 0 2006.257.23:56:05.20#ibcon#read 3, iclass 39, count 0 2006.257.23:56:05.20#ibcon#about to read 4, iclass 39, count 0 2006.257.23:56:05.20#ibcon#read 4, iclass 39, count 0 2006.257.23:56:05.20#ibcon#about to read 5, iclass 39, count 0 2006.257.23:56:05.20#ibcon#read 5, iclass 39, count 0 2006.257.23:56:05.20#ibcon#about to read 6, iclass 39, count 0 2006.257.23:56:05.20#ibcon#read 6, iclass 39, count 0 2006.257.23:56:05.20#ibcon#end of sib2, iclass 39, count 0 2006.257.23:56:05.20#ibcon#*mode == 0, iclass 39, count 0 2006.257.23:56:05.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.257.23:56:05.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:56:05.20#ibcon#*before write, iclass 39, count 0 2006.257.23:56:05.20#ibcon#enter sib2, iclass 39, count 0 2006.257.23:56:05.20#ibcon#flushed, iclass 39, count 0 2006.257.23:56:05.20#ibcon#about to write, iclass 39, count 0 2006.257.23:56:05.20#ibcon#wrote, iclass 39, count 0 2006.257.23:56:05.20#ibcon#about to read 3, iclass 39, count 0 2006.257.23:56:05.24#ibcon#read 3, iclass 39, count 0 2006.257.23:56:05.24#ibcon#about to read 4, iclass 39, count 0 2006.257.23:56:05.24#ibcon#read 4, iclass 39, count 0 2006.257.23:56:05.24#ibcon#about to read 5, iclass 39, count 0 2006.257.23:56:05.24#ibcon#read 5, iclass 39, count 0 2006.257.23:56:05.24#ibcon#about to read 6, iclass 39, count 0 2006.257.23:56:05.24#ibcon#read 6, iclass 39, count 0 2006.257.23:56:05.24#ibcon#end of sib2, iclass 39, count 0 2006.257.23:56:05.24#ibcon#*after write, iclass 39, count 0 2006.257.23:56:05.24#ibcon#*before return 0, iclass 39, count 0 2006.257.23:56:05.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:05.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.257.23:56:05.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.257.23:56:05.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.257.23:56:05.24$vck44/vb=4,5 2006.257.23:56:05.24#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.257.23:56:05.24#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.257.23:56:05.24#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:05.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:05.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:05.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:05.30#ibcon#enter wrdev, iclass 3, count 2 2006.257.23:56:05.30#ibcon#first serial, iclass 3, count 2 2006.257.23:56:05.30#ibcon#enter sib2, iclass 3, count 2 2006.257.23:56:05.30#ibcon#flushed, iclass 3, count 2 2006.257.23:56:05.30#ibcon#about to write, iclass 3, count 2 2006.257.23:56:05.30#ibcon#wrote, iclass 3, count 2 2006.257.23:56:05.30#ibcon#about to read 3, iclass 3, count 2 2006.257.23:56:05.32#ibcon#read 3, iclass 3, count 2 2006.257.23:56:05.32#ibcon#about to read 4, iclass 3, count 2 2006.257.23:56:05.32#ibcon#read 4, iclass 3, count 2 2006.257.23:56:05.32#ibcon#about to read 5, iclass 3, count 2 2006.257.23:56:05.32#ibcon#read 5, iclass 3, count 2 2006.257.23:56:05.32#ibcon#about to read 6, iclass 3, count 2 2006.257.23:56:05.32#ibcon#read 6, iclass 3, count 2 2006.257.23:56:05.32#ibcon#end of sib2, iclass 3, count 2 2006.257.23:56:05.32#ibcon#*mode == 0, iclass 3, count 2 2006.257.23:56:05.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.257.23:56:05.32#ibcon#[27=AT04-05\r\n] 2006.257.23:56:05.32#ibcon#*before write, iclass 3, count 2 2006.257.23:56:05.32#ibcon#enter sib2, iclass 3, count 2 2006.257.23:56:05.32#ibcon#flushed, iclass 3, count 2 2006.257.23:56:05.32#ibcon#about to write, iclass 3, count 2 2006.257.23:56:05.32#ibcon#wrote, iclass 3, count 2 2006.257.23:56:05.32#ibcon#about to read 3, iclass 3, count 2 2006.257.23:56:05.35#ibcon#read 3, iclass 3, count 2 2006.257.23:56:05.35#ibcon#about to read 4, iclass 3, count 2 2006.257.23:56:05.35#ibcon#read 4, iclass 3, count 2 2006.257.23:56:05.35#ibcon#about to read 5, iclass 3, count 2 2006.257.23:56:05.35#ibcon#read 5, iclass 3, count 2 2006.257.23:56:05.35#ibcon#about to read 6, iclass 3, count 2 2006.257.23:56:05.35#ibcon#read 6, iclass 3, count 2 2006.257.23:56:05.35#ibcon#end of sib2, iclass 3, count 2 2006.257.23:56:05.35#ibcon#*after write, iclass 3, count 2 2006.257.23:56:05.35#ibcon#*before return 0, iclass 3, count 2 2006.257.23:56:05.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:05.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.257.23:56:05.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.257.23:56:05.35#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:05.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:05.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:05.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:05.47#ibcon#enter wrdev, iclass 3, count 0 2006.257.23:56:05.47#ibcon#first serial, iclass 3, count 0 2006.257.23:56:05.47#ibcon#enter sib2, iclass 3, count 0 2006.257.23:56:05.47#ibcon#flushed, iclass 3, count 0 2006.257.23:56:05.47#ibcon#about to write, iclass 3, count 0 2006.257.23:56:05.47#ibcon#wrote, iclass 3, count 0 2006.257.23:56:05.47#ibcon#about to read 3, iclass 3, count 0 2006.257.23:56:05.49#ibcon#read 3, iclass 3, count 0 2006.257.23:56:05.49#ibcon#about to read 4, iclass 3, count 0 2006.257.23:56:05.49#ibcon#read 4, iclass 3, count 0 2006.257.23:56:05.49#ibcon#about to read 5, iclass 3, count 0 2006.257.23:56:05.49#ibcon#read 5, iclass 3, count 0 2006.257.23:56:05.49#ibcon#about to read 6, iclass 3, count 0 2006.257.23:56:05.49#ibcon#read 6, iclass 3, count 0 2006.257.23:56:05.49#ibcon#end of sib2, iclass 3, count 0 2006.257.23:56:05.49#ibcon#*mode == 0, iclass 3, count 0 2006.257.23:56:05.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.257.23:56:05.49#ibcon#[27=USB\r\n] 2006.257.23:56:05.49#ibcon#*before write, iclass 3, count 0 2006.257.23:56:05.49#ibcon#enter sib2, iclass 3, count 0 2006.257.23:56:05.49#ibcon#flushed, iclass 3, count 0 2006.257.23:56:05.49#ibcon#about to write, iclass 3, count 0 2006.257.23:56:05.49#ibcon#wrote, iclass 3, count 0 2006.257.23:56:05.49#ibcon#about to read 3, iclass 3, count 0 2006.257.23:56:05.52#ibcon#read 3, iclass 3, count 0 2006.257.23:56:05.52#ibcon#about to read 4, iclass 3, count 0 2006.257.23:56:05.52#ibcon#read 4, iclass 3, count 0 2006.257.23:56:05.52#ibcon#about to read 5, iclass 3, count 0 2006.257.23:56:05.52#ibcon#read 5, iclass 3, count 0 2006.257.23:56:05.52#ibcon#about to read 6, iclass 3, count 0 2006.257.23:56:05.52#ibcon#read 6, iclass 3, count 0 2006.257.23:56:05.52#ibcon#end of sib2, iclass 3, count 0 2006.257.23:56:05.52#ibcon#*after write, iclass 3, count 0 2006.257.23:56:05.52#ibcon#*before return 0, iclass 3, count 0 2006.257.23:56:05.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:05.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.257.23:56:05.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.257.23:56:05.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.257.23:56:05.52$vck44/vblo=5,709.99 2006.257.23:56:05.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.257.23:56:05.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.257.23:56:05.52#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:05.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:05.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:05.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:05.52#ibcon#enter wrdev, iclass 5, count 0 2006.257.23:56:05.52#ibcon#first serial, iclass 5, count 0 2006.257.23:56:05.52#ibcon#enter sib2, iclass 5, count 0 2006.257.23:56:05.52#ibcon#flushed, iclass 5, count 0 2006.257.23:56:05.52#ibcon#about to write, iclass 5, count 0 2006.257.23:56:05.52#ibcon#wrote, iclass 5, count 0 2006.257.23:56:05.52#ibcon#about to read 3, iclass 5, count 0 2006.257.23:56:05.54#ibcon#read 3, iclass 5, count 0 2006.257.23:56:05.54#ibcon#about to read 4, iclass 5, count 0 2006.257.23:56:05.54#ibcon#read 4, iclass 5, count 0 2006.257.23:56:05.54#ibcon#about to read 5, iclass 5, count 0 2006.257.23:56:05.54#ibcon#read 5, iclass 5, count 0 2006.257.23:56:05.54#ibcon#about to read 6, iclass 5, count 0 2006.257.23:56:05.54#ibcon#read 6, iclass 5, count 0 2006.257.23:56:05.54#ibcon#end of sib2, iclass 5, count 0 2006.257.23:56:05.54#ibcon#*mode == 0, iclass 5, count 0 2006.257.23:56:05.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.257.23:56:05.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:56:05.54#ibcon#*before write, iclass 5, count 0 2006.257.23:56:05.54#ibcon#enter sib2, iclass 5, count 0 2006.257.23:56:05.54#ibcon#flushed, iclass 5, count 0 2006.257.23:56:05.54#ibcon#about to write, iclass 5, count 0 2006.257.23:56:05.54#ibcon#wrote, iclass 5, count 0 2006.257.23:56:05.54#ibcon#about to read 3, iclass 5, count 0 2006.257.23:56:05.58#ibcon#read 3, iclass 5, count 0 2006.257.23:56:05.58#ibcon#about to read 4, iclass 5, count 0 2006.257.23:56:05.58#ibcon#read 4, iclass 5, count 0 2006.257.23:56:05.58#ibcon#about to read 5, iclass 5, count 0 2006.257.23:56:05.58#ibcon#read 5, iclass 5, count 0 2006.257.23:56:05.58#ibcon#about to read 6, iclass 5, count 0 2006.257.23:56:05.58#ibcon#read 6, iclass 5, count 0 2006.257.23:56:05.58#ibcon#end of sib2, iclass 5, count 0 2006.257.23:56:05.58#ibcon#*after write, iclass 5, count 0 2006.257.23:56:05.58#ibcon#*before return 0, iclass 5, count 0 2006.257.23:56:05.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:05.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.257.23:56:05.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.257.23:56:05.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.257.23:56:05.58$vck44/vb=5,4 2006.257.23:56:05.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.257.23:56:05.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.257.23:56:05.58#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:05.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:05.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:05.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:05.64#ibcon#enter wrdev, iclass 7, count 2 2006.257.23:56:05.64#ibcon#first serial, iclass 7, count 2 2006.257.23:56:05.64#ibcon#enter sib2, iclass 7, count 2 2006.257.23:56:05.64#ibcon#flushed, iclass 7, count 2 2006.257.23:56:05.64#ibcon#about to write, iclass 7, count 2 2006.257.23:56:05.64#ibcon#wrote, iclass 7, count 2 2006.257.23:56:05.64#ibcon#about to read 3, iclass 7, count 2 2006.257.23:56:05.66#ibcon#read 3, iclass 7, count 2 2006.257.23:56:05.66#ibcon#about to read 4, iclass 7, count 2 2006.257.23:56:05.66#ibcon#read 4, iclass 7, count 2 2006.257.23:56:05.66#ibcon#about to read 5, iclass 7, count 2 2006.257.23:56:05.66#ibcon#read 5, iclass 7, count 2 2006.257.23:56:05.66#ibcon#about to read 6, iclass 7, count 2 2006.257.23:56:05.66#ibcon#read 6, iclass 7, count 2 2006.257.23:56:05.66#ibcon#end of sib2, iclass 7, count 2 2006.257.23:56:05.66#ibcon#*mode == 0, iclass 7, count 2 2006.257.23:56:05.66#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.257.23:56:05.66#ibcon#[27=AT05-04\r\n] 2006.257.23:56:05.66#ibcon#*before write, iclass 7, count 2 2006.257.23:56:05.66#ibcon#enter sib2, iclass 7, count 2 2006.257.23:56:05.66#ibcon#flushed, iclass 7, count 2 2006.257.23:56:05.66#ibcon#about to write, iclass 7, count 2 2006.257.23:56:05.66#ibcon#wrote, iclass 7, count 2 2006.257.23:56:05.66#ibcon#about to read 3, iclass 7, count 2 2006.257.23:56:05.69#ibcon#read 3, iclass 7, count 2 2006.257.23:56:05.69#ibcon#about to read 4, iclass 7, count 2 2006.257.23:56:05.69#ibcon#read 4, iclass 7, count 2 2006.257.23:56:05.69#ibcon#about to read 5, iclass 7, count 2 2006.257.23:56:05.69#ibcon#read 5, iclass 7, count 2 2006.257.23:56:05.69#ibcon#about to read 6, iclass 7, count 2 2006.257.23:56:05.69#ibcon#read 6, iclass 7, count 2 2006.257.23:56:05.69#ibcon#end of sib2, iclass 7, count 2 2006.257.23:56:05.69#ibcon#*after write, iclass 7, count 2 2006.257.23:56:05.69#ibcon#*before return 0, iclass 7, count 2 2006.257.23:56:05.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:05.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.257.23:56:05.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.257.23:56:05.69#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:05.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:05.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:05.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:05.81#ibcon#enter wrdev, iclass 7, count 0 2006.257.23:56:05.81#ibcon#first serial, iclass 7, count 0 2006.257.23:56:05.81#ibcon#enter sib2, iclass 7, count 0 2006.257.23:56:05.81#ibcon#flushed, iclass 7, count 0 2006.257.23:56:05.81#ibcon#about to write, iclass 7, count 0 2006.257.23:56:05.81#ibcon#wrote, iclass 7, count 0 2006.257.23:56:05.81#ibcon#about to read 3, iclass 7, count 0 2006.257.23:56:05.83#ibcon#read 3, iclass 7, count 0 2006.257.23:56:05.83#ibcon#about to read 4, iclass 7, count 0 2006.257.23:56:05.83#ibcon#read 4, iclass 7, count 0 2006.257.23:56:05.83#ibcon#about to read 5, iclass 7, count 0 2006.257.23:56:05.83#ibcon#read 5, iclass 7, count 0 2006.257.23:56:05.83#ibcon#about to read 6, iclass 7, count 0 2006.257.23:56:05.83#ibcon#read 6, iclass 7, count 0 2006.257.23:56:05.83#ibcon#end of sib2, iclass 7, count 0 2006.257.23:56:05.83#ibcon#*mode == 0, iclass 7, count 0 2006.257.23:56:05.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.257.23:56:05.83#ibcon#[27=USB\r\n] 2006.257.23:56:05.83#ibcon#*before write, iclass 7, count 0 2006.257.23:56:05.83#ibcon#enter sib2, iclass 7, count 0 2006.257.23:56:05.83#ibcon#flushed, iclass 7, count 0 2006.257.23:56:05.83#ibcon#about to write, iclass 7, count 0 2006.257.23:56:05.83#ibcon#wrote, iclass 7, count 0 2006.257.23:56:05.83#ibcon#about to read 3, iclass 7, count 0 2006.257.23:56:05.86#ibcon#read 3, iclass 7, count 0 2006.257.23:56:05.86#ibcon#about to read 4, iclass 7, count 0 2006.257.23:56:05.86#ibcon#read 4, iclass 7, count 0 2006.257.23:56:05.86#ibcon#about to read 5, iclass 7, count 0 2006.257.23:56:05.86#ibcon#read 5, iclass 7, count 0 2006.257.23:56:05.86#ibcon#about to read 6, iclass 7, count 0 2006.257.23:56:05.86#ibcon#read 6, iclass 7, count 0 2006.257.23:56:05.86#ibcon#end of sib2, iclass 7, count 0 2006.257.23:56:05.86#ibcon#*after write, iclass 7, count 0 2006.257.23:56:05.86#ibcon#*before return 0, iclass 7, count 0 2006.257.23:56:05.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:05.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.257.23:56:05.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.257.23:56:05.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.257.23:56:05.86$vck44/vblo=6,719.99 2006.257.23:56:05.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.257.23:56:05.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.257.23:56:05.86#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:05.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:05.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:05.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:05.86#ibcon#enter wrdev, iclass 11, count 0 2006.257.23:56:05.86#ibcon#first serial, iclass 11, count 0 2006.257.23:56:05.86#ibcon#enter sib2, iclass 11, count 0 2006.257.23:56:05.86#ibcon#flushed, iclass 11, count 0 2006.257.23:56:05.86#ibcon#about to write, iclass 11, count 0 2006.257.23:56:05.86#ibcon#wrote, iclass 11, count 0 2006.257.23:56:05.86#ibcon#about to read 3, iclass 11, count 0 2006.257.23:56:05.88#ibcon#read 3, iclass 11, count 0 2006.257.23:56:05.88#ibcon#about to read 4, iclass 11, count 0 2006.257.23:56:05.88#ibcon#read 4, iclass 11, count 0 2006.257.23:56:05.88#ibcon#about to read 5, iclass 11, count 0 2006.257.23:56:05.88#ibcon#read 5, iclass 11, count 0 2006.257.23:56:05.88#ibcon#about to read 6, iclass 11, count 0 2006.257.23:56:05.88#ibcon#read 6, iclass 11, count 0 2006.257.23:56:05.88#ibcon#end of sib2, iclass 11, count 0 2006.257.23:56:05.88#ibcon#*mode == 0, iclass 11, count 0 2006.257.23:56:05.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.257.23:56:05.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:56:05.88#ibcon#*before write, iclass 11, count 0 2006.257.23:56:05.88#ibcon#enter sib2, iclass 11, count 0 2006.257.23:56:05.88#ibcon#flushed, iclass 11, count 0 2006.257.23:56:05.88#ibcon#about to write, iclass 11, count 0 2006.257.23:56:05.88#ibcon#wrote, iclass 11, count 0 2006.257.23:56:05.88#ibcon#about to read 3, iclass 11, count 0 2006.257.23:56:05.92#ibcon#read 3, iclass 11, count 0 2006.257.23:56:05.92#ibcon#about to read 4, iclass 11, count 0 2006.257.23:56:05.92#ibcon#read 4, iclass 11, count 0 2006.257.23:56:05.92#ibcon#about to read 5, iclass 11, count 0 2006.257.23:56:05.92#ibcon#read 5, iclass 11, count 0 2006.257.23:56:05.92#ibcon#about to read 6, iclass 11, count 0 2006.257.23:56:05.92#ibcon#read 6, iclass 11, count 0 2006.257.23:56:05.92#ibcon#end of sib2, iclass 11, count 0 2006.257.23:56:05.92#ibcon#*after write, iclass 11, count 0 2006.257.23:56:05.92#ibcon#*before return 0, iclass 11, count 0 2006.257.23:56:05.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:05.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.257.23:56:05.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.257.23:56:05.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.257.23:56:05.92$vck44/vb=6,4 2006.257.23:56:05.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.257.23:56:05.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.257.23:56:05.92#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:05.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:05.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:05.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:05.98#ibcon#enter wrdev, iclass 13, count 2 2006.257.23:56:05.98#ibcon#first serial, iclass 13, count 2 2006.257.23:56:05.98#ibcon#enter sib2, iclass 13, count 2 2006.257.23:56:05.98#ibcon#flushed, iclass 13, count 2 2006.257.23:56:05.98#ibcon#about to write, iclass 13, count 2 2006.257.23:56:05.98#ibcon#wrote, iclass 13, count 2 2006.257.23:56:05.98#ibcon#about to read 3, iclass 13, count 2 2006.257.23:56:06.00#ibcon#read 3, iclass 13, count 2 2006.257.23:56:06.00#ibcon#about to read 4, iclass 13, count 2 2006.257.23:56:06.00#ibcon#read 4, iclass 13, count 2 2006.257.23:56:06.00#ibcon#about to read 5, iclass 13, count 2 2006.257.23:56:06.00#ibcon#read 5, iclass 13, count 2 2006.257.23:56:06.00#ibcon#about to read 6, iclass 13, count 2 2006.257.23:56:06.00#ibcon#read 6, iclass 13, count 2 2006.257.23:56:06.00#ibcon#end of sib2, iclass 13, count 2 2006.257.23:56:06.00#ibcon#*mode == 0, iclass 13, count 2 2006.257.23:56:06.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.257.23:56:06.00#ibcon#[27=AT06-04\r\n] 2006.257.23:56:06.00#ibcon#*before write, iclass 13, count 2 2006.257.23:56:06.00#ibcon#enter sib2, iclass 13, count 2 2006.257.23:56:06.00#ibcon#flushed, iclass 13, count 2 2006.257.23:56:06.00#ibcon#about to write, iclass 13, count 2 2006.257.23:56:06.00#ibcon#wrote, iclass 13, count 2 2006.257.23:56:06.00#ibcon#about to read 3, iclass 13, count 2 2006.257.23:56:06.03#ibcon#read 3, iclass 13, count 2 2006.257.23:56:06.03#ibcon#about to read 4, iclass 13, count 2 2006.257.23:56:06.03#ibcon#read 4, iclass 13, count 2 2006.257.23:56:06.03#ibcon#about to read 5, iclass 13, count 2 2006.257.23:56:06.03#ibcon#read 5, iclass 13, count 2 2006.257.23:56:06.03#ibcon#about to read 6, iclass 13, count 2 2006.257.23:56:06.03#ibcon#read 6, iclass 13, count 2 2006.257.23:56:06.03#ibcon#end of sib2, iclass 13, count 2 2006.257.23:56:06.03#ibcon#*after write, iclass 13, count 2 2006.257.23:56:06.03#ibcon#*before return 0, iclass 13, count 2 2006.257.23:56:06.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:06.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.257.23:56:06.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.257.23:56:06.03#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:06.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:06.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:06.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:06.15#ibcon#enter wrdev, iclass 13, count 0 2006.257.23:56:06.15#ibcon#first serial, iclass 13, count 0 2006.257.23:56:06.15#ibcon#enter sib2, iclass 13, count 0 2006.257.23:56:06.15#ibcon#flushed, iclass 13, count 0 2006.257.23:56:06.15#ibcon#about to write, iclass 13, count 0 2006.257.23:56:06.15#ibcon#wrote, iclass 13, count 0 2006.257.23:56:06.15#ibcon#about to read 3, iclass 13, count 0 2006.257.23:56:06.17#ibcon#read 3, iclass 13, count 0 2006.257.23:56:06.17#ibcon#about to read 4, iclass 13, count 0 2006.257.23:56:06.17#ibcon#read 4, iclass 13, count 0 2006.257.23:56:06.17#ibcon#about to read 5, iclass 13, count 0 2006.257.23:56:06.17#ibcon#read 5, iclass 13, count 0 2006.257.23:56:06.17#ibcon#about to read 6, iclass 13, count 0 2006.257.23:56:06.17#ibcon#read 6, iclass 13, count 0 2006.257.23:56:06.17#ibcon#end of sib2, iclass 13, count 0 2006.257.23:56:06.17#ibcon#*mode == 0, iclass 13, count 0 2006.257.23:56:06.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.257.23:56:06.17#ibcon#[27=USB\r\n] 2006.257.23:56:06.17#ibcon#*before write, iclass 13, count 0 2006.257.23:56:06.17#ibcon#enter sib2, iclass 13, count 0 2006.257.23:56:06.17#ibcon#flushed, iclass 13, count 0 2006.257.23:56:06.17#ibcon#about to write, iclass 13, count 0 2006.257.23:56:06.17#ibcon#wrote, iclass 13, count 0 2006.257.23:56:06.17#ibcon#about to read 3, iclass 13, count 0 2006.257.23:56:06.20#ibcon#read 3, iclass 13, count 0 2006.257.23:56:06.20#ibcon#about to read 4, iclass 13, count 0 2006.257.23:56:06.20#ibcon#read 4, iclass 13, count 0 2006.257.23:56:06.20#ibcon#about to read 5, iclass 13, count 0 2006.257.23:56:06.20#ibcon#read 5, iclass 13, count 0 2006.257.23:56:06.20#ibcon#about to read 6, iclass 13, count 0 2006.257.23:56:06.20#ibcon#read 6, iclass 13, count 0 2006.257.23:56:06.20#ibcon#end of sib2, iclass 13, count 0 2006.257.23:56:06.20#ibcon#*after write, iclass 13, count 0 2006.257.23:56:06.20#ibcon#*before return 0, iclass 13, count 0 2006.257.23:56:06.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:06.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.257.23:56:06.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.257.23:56:06.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.257.23:56:06.20$vck44/vblo=7,734.99 2006.257.23:56:06.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.257.23:56:06.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.257.23:56:06.20#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:06.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:56:06.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:56:06.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:56:06.20#ibcon#enter wrdev, iclass 15, count 0 2006.257.23:56:06.20#ibcon#first serial, iclass 15, count 0 2006.257.23:56:06.20#ibcon#enter sib2, iclass 15, count 0 2006.257.23:56:06.20#ibcon#flushed, iclass 15, count 0 2006.257.23:56:06.20#ibcon#about to write, iclass 15, count 0 2006.257.23:56:06.20#ibcon#wrote, iclass 15, count 0 2006.257.23:56:06.20#ibcon#about to read 3, iclass 15, count 0 2006.257.23:56:06.22#ibcon#read 3, iclass 15, count 0 2006.257.23:56:06.22#ibcon#about to read 4, iclass 15, count 0 2006.257.23:56:06.22#ibcon#read 4, iclass 15, count 0 2006.257.23:56:06.22#ibcon#about to read 5, iclass 15, count 0 2006.257.23:56:06.22#ibcon#read 5, iclass 15, count 0 2006.257.23:56:06.22#ibcon#about to read 6, iclass 15, count 0 2006.257.23:56:06.22#ibcon#read 6, iclass 15, count 0 2006.257.23:56:06.22#ibcon#end of sib2, iclass 15, count 0 2006.257.23:56:06.22#ibcon#*mode == 0, iclass 15, count 0 2006.257.23:56:06.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.257.23:56:06.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:56:06.22#ibcon#*before write, iclass 15, count 0 2006.257.23:56:06.22#ibcon#enter sib2, iclass 15, count 0 2006.257.23:56:06.22#ibcon#flushed, iclass 15, count 0 2006.257.23:56:06.22#ibcon#about to write, iclass 15, count 0 2006.257.23:56:06.22#ibcon#wrote, iclass 15, count 0 2006.257.23:56:06.22#ibcon#about to read 3, iclass 15, count 0 2006.257.23:56:06.26#ibcon#read 3, iclass 15, count 0 2006.257.23:56:06.26#ibcon#about to read 4, iclass 15, count 0 2006.257.23:56:06.26#ibcon#read 4, iclass 15, count 0 2006.257.23:56:06.26#ibcon#about to read 5, iclass 15, count 0 2006.257.23:56:06.26#ibcon#read 5, iclass 15, count 0 2006.257.23:56:06.26#ibcon#about to read 6, iclass 15, count 0 2006.257.23:56:06.26#ibcon#read 6, iclass 15, count 0 2006.257.23:56:06.26#ibcon#end of sib2, iclass 15, count 0 2006.257.23:56:06.26#ibcon#*after write, iclass 15, count 0 2006.257.23:56:06.26#ibcon#*before return 0, iclass 15, count 0 2006.257.23:56:06.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:56:06.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.257.23:56:06.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.257.23:56:06.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.257.23:56:06.26$vck44/vb=7,4 2006.257.23:56:06.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.257.23:56:06.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.257.23:56:06.26#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:06.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.23:56:06.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.257.23:56:06.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.23:56:06.32#ibcon#enter wrdev, iclass 17, count 2 2006.257.23:56:06.32#ibcon#first serial, iclass 17, count 2 2006.257.23:56:06.32#ibcon#enter sib2, iclass 17, count 2 2006.257.23:56:06.32#ibcon#flushed, iclass 17, count 2 2006.257.23:56:06.32#ibcon#about to write, iclass 17, count 2 2006.257.23:56:06.32#ibcon#wrote, iclass 17, count 2 2006.257.23:56:06.32#ibcon#about to read 3, iclass 17, count 2 2006.257.23:56:06.34#ibcon#read 3, iclass 17, count 2 2006.257.23:56:06.34#ibcon#about to read 4, iclass 17, count 2 2006.257.23:56:06.34#ibcon#read 4, iclass 17, count 2 2006.257.23:56:06.34#ibcon#about to read 5, iclass 17, count 2 2006.257.23:56:06.34#ibcon#read 5, iclass 17, count 2 2006.257.23:56:06.34#ibcon#about to read 6, iclass 17, count 2 2006.257.23:56:06.34#ibcon#read 6, iclass 17, count 2 2006.257.23:56:06.34#ibcon#end of sib2, iclass 17, count 2 2006.257.23:56:06.34#ibcon#*mode == 0, iclass 17, count 2 2006.257.23:56:06.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.257.23:56:06.34#ibcon#[27=AT07-04\r\n] 2006.257.23:56:06.34#ibcon#*before write, iclass 17, count 2 2006.257.23:56:06.34#ibcon#enter sib2, iclass 17, count 2 2006.257.23:56:06.34#ibcon#flushed, iclass 17, count 2 2006.257.23:56:06.34#ibcon#about to write, iclass 17, count 2 2006.257.23:56:06.34#ibcon#wrote, iclass 17, count 2 2006.257.23:56:06.34#ibcon#about to read 3, iclass 17, count 2 2006.257.23:56:06.37#ibcon#read 3, iclass 17, count 2 2006.257.23:56:06.37#ibcon#about to read 4, iclass 17, count 2 2006.257.23:56:06.37#ibcon#read 4, iclass 17, count 2 2006.257.23:56:06.37#ibcon#about to read 5, iclass 17, count 2 2006.257.23:56:06.37#ibcon#read 5, iclass 17, count 2 2006.257.23:56:06.37#ibcon#about to read 6, iclass 17, count 2 2006.257.23:56:06.37#ibcon#read 6, iclass 17, count 2 2006.257.23:56:06.37#ibcon#end of sib2, iclass 17, count 2 2006.257.23:56:06.37#ibcon#*after write, iclass 17, count 2 2006.257.23:56:06.37#ibcon#*before return 0, iclass 17, count 2 2006.257.23:56:06.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.257.23:56:06.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.257.23:56:06.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.257.23:56:06.37#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:06.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.23:56:06.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.257.23:56:06.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.23:56:06.49#ibcon#enter wrdev, iclass 17, count 0 2006.257.23:56:06.49#ibcon#first serial, iclass 17, count 0 2006.257.23:56:06.49#ibcon#enter sib2, iclass 17, count 0 2006.257.23:56:06.49#ibcon#flushed, iclass 17, count 0 2006.257.23:56:06.49#ibcon#about to write, iclass 17, count 0 2006.257.23:56:06.49#ibcon#wrote, iclass 17, count 0 2006.257.23:56:06.49#ibcon#about to read 3, iclass 17, count 0 2006.257.23:56:06.51#ibcon#read 3, iclass 17, count 0 2006.257.23:56:06.51#ibcon#about to read 4, iclass 17, count 0 2006.257.23:56:06.51#ibcon#read 4, iclass 17, count 0 2006.257.23:56:06.51#ibcon#about to read 5, iclass 17, count 0 2006.257.23:56:06.51#ibcon#read 5, iclass 17, count 0 2006.257.23:56:06.51#ibcon#about to read 6, iclass 17, count 0 2006.257.23:56:06.51#ibcon#read 6, iclass 17, count 0 2006.257.23:56:06.51#ibcon#end of sib2, iclass 17, count 0 2006.257.23:56:06.51#ibcon#*mode == 0, iclass 17, count 0 2006.257.23:56:06.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.257.23:56:06.51#ibcon#[27=USB\r\n] 2006.257.23:56:06.51#ibcon#*before write, iclass 17, count 0 2006.257.23:56:06.51#ibcon#enter sib2, iclass 17, count 0 2006.257.23:56:06.51#ibcon#flushed, iclass 17, count 0 2006.257.23:56:06.51#ibcon#about to write, iclass 17, count 0 2006.257.23:56:06.51#ibcon#wrote, iclass 17, count 0 2006.257.23:56:06.51#ibcon#about to read 3, iclass 17, count 0 2006.257.23:56:06.54#ibcon#read 3, iclass 17, count 0 2006.257.23:56:06.54#ibcon#about to read 4, iclass 17, count 0 2006.257.23:56:06.54#ibcon#read 4, iclass 17, count 0 2006.257.23:56:06.54#ibcon#about to read 5, iclass 17, count 0 2006.257.23:56:06.54#ibcon#read 5, iclass 17, count 0 2006.257.23:56:06.54#ibcon#about to read 6, iclass 17, count 0 2006.257.23:56:06.54#ibcon#read 6, iclass 17, count 0 2006.257.23:56:06.54#ibcon#end of sib2, iclass 17, count 0 2006.257.23:56:06.54#ibcon#*after write, iclass 17, count 0 2006.257.23:56:06.54#ibcon#*before return 0, iclass 17, count 0 2006.257.23:56:06.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.257.23:56:06.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.257.23:56:06.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.257.23:56:06.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.257.23:56:06.54$vck44/vblo=8,744.99 2006.257.23:56:06.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.257.23:56:06.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.257.23:56:06.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:56:06.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:56:06.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:56:06.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:56:06.54#ibcon#enter wrdev, iclass 19, count 0 2006.257.23:56:06.54#ibcon#first serial, iclass 19, count 0 2006.257.23:56:06.54#ibcon#enter sib2, iclass 19, count 0 2006.257.23:56:06.54#ibcon#flushed, iclass 19, count 0 2006.257.23:56:06.54#ibcon#about to write, iclass 19, count 0 2006.257.23:56:06.54#ibcon#wrote, iclass 19, count 0 2006.257.23:56:06.54#ibcon#about to read 3, iclass 19, count 0 2006.257.23:56:06.56#ibcon#read 3, iclass 19, count 0 2006.257.23:56:06.56#ibcon#about to read 4, iclass 19, count 0 2006.257.23:56:06.56#ibcon#read 4, iclass 19, count 0 2006.257.23:56:06.56#ibcon#about to read 5, iclass 19, count 0 2006.257.23:56:06.56#ibcon#read 5, iclass 19, count 0 2006.257.23:56:06.56#ibcon#about to read 6, iclass 19, count 0 2006.257.23:56:06.56#ibcon#read 6, iclass 19, count 0 2006.257.23:56:06.56#ibcon#end of sib2, iclass 19, count 0 2006.257.23:56:06.56#ibcon#*mode == 0, iclass 19, count 0 2006.257.23:56:06.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.257.23:56:06.56#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:56:06.56#ibcon#*before write, iclass 19, count 0 2006.257.23:56:06.56#ibcon#enter sib2, iclass 19, count 0 2006.257.23:56:06.56#ibcon#flushed, iclass 19, count 0 2006.257.23:56:06.56#ibcon#about to write, iclass 19, count 0 2006.257.23:56:06.56#ibcon#wrote, iclass 19, count 0 2006.257.23:56:06.56#ibcon#about to read 3, iclass 19, count 0 2006.257.23:56:06.60#ibcon#read 3, iclass 19, count 0 2006.257.23:56:06.60#ibcon#about to read 4, iclass 19, count 0 2006.257.23:56:06.60#ibcon#read 4, iclass 19, count 0 2006.257.23:56:06.60#ibcon#about to read 5, iclass 19, count 0 2006.257.23:56:06.60#ibcon#read 5, iclass 19, count 0 2006.257.23:56:06.60#ibcon#about to read 6, iclass 19, count 0 2006.257.23:56:06.60#ibcon#read 6, iclass 19, count 0 2006.257.23:56:06.60#ibcon#end of sib2, iclass 19, count 0 2006.257.23:56:06.60#ibcon#*after write, iclass 19, count 0 2006.257.23:56:06.60#ibcon#*before return 0, iclass 19, count 0 2006.257.23:56:06.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:56:06.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.257.23:56:06.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.257.23:56:06.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.257.23:56:06.60$vck44/vb=8,4 2006.257.23:56:06.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.257.23:56:06.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.257.23:56:06.60#ibcon#ireg 11 cls_cnt 2 2006.257.23:56:06.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:06.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:06.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:06.66#ibcon#enter wrdev, iclass 21, count 2 2006.257.23:56:06.66#ibcon#first serial, iclass 21, count 2 2006.257.23:56:06.66#ibcon#enter sib2, iclass 21, count 2 2006.257.23:56:06.66#ibcon#flushed, iclass 21, count 2 2006.257.23:56:06.66#ibcon#about to write, iclass 21, count 2 2006.257.23:56:06.66#ibcon#wrote, iclass 21, count 2 2006.257.23:56:06.66#ibcon#about to read 3, iclass 21, count 2 2006.257.23:56:06.68#ibcon#read 3, iclass 21, count 2 2006.257.23:56:06.68#ibcon#about to read 4, iclass 21, count 2 2006.257.23:56:06.68#ibcon#read 4, iclass 21, count 2 2006.257.23:56:06.68#ibcon#about to read 5, iclass 21, count 2 2006.257.23:56:06.68#ibcon#read 5, iclass 21, count 2 2006.257.23:56:06.68#ibcon#about to read 6, iclass 21, count 2 2006.257.23:56:06.68#ibcon#read 6, iclass 21, count 2 2006.257.23:56:06.68#ibcon#end of sib2, iclass 21, count 2 2006.257.23:56:06.68#ibcon#*mode == 0, iclass 21, count 2 2006.257.23:56:06.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.257.23:56:06.68#ibcon#[27=AT08-04\r\n] 2006.257.23:56:06.68#ibcon#*before write, iclass 21, count 2 2006.257.23:56:06.68#ibcon#enter sib2, iclass 21, count 2 2006.257.23:56:06.68#ibcon#flushed, iclass 21, count 2 2006.257.23:56:06.68#ibcon#about to write, iclass 21, count 2 2006.257.23:56:06.68#ibcon#wrote, iclass 21, count 2 2006.257.23:56:06.68#ibcon#about to read 3, iclass 21, count 2 2006.257.23:56:06.71#ibcon#read 3, iclass 21, count 2 2006.257.23:56:06.71#ibcon#about to read 4, iclass 21, count 2 2006.257.23:56:06.71#ibcon#read 4, iclass 21, count 2 2006.257.23:56:06.71#ibcon#about to read 5, iclass 21, count 2 2006.257.23:56:06.71#ibcon#read 5, iclass 21, count 2 2006.257.23:56:06.71#ibcon#about to read 6, iclass 21, count 2 2006.257.23:56:06.71#ibcon#read 6, iclass 21, count 2 2006.257.23:56:06.71#ibcon#end of sib2, iclass 21, count 2 2006.257.23:56:06.71#ibcon#*after write, iclass 21, count 2 2006.257.23:56:06.71#ibcon#*before return 0, iclass 21, count 2 2006.257.23:56:06.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:06.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.257.23:56:06.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.257.23:56:06.71#ibcon#ireg 7 cls_cnt 0 2006.257.23:56:06.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:06.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:06.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:06.83#ibcon#enter wrdev, iclass 21, count 0 2006.257.23:56:06.83#ibcon#first serial, iclass 21, count 0 2006.257.23:56:06.83#ibcon#enter sib2, iclass 21, count 0 2006.257.23:56:06.83#ibcon#flushed, iclass 21, count 0 2006.257.23:56:06.83#ibcon#about to write, iclass 21, count 0 2006.257.23:56:06.83#ibcon#wrote, iclass 21, count 0 2006.257.23:56:06.83#ibcon#about to read 3, iclass 21, count 0 2006.257.23:56:06.85#ibcon#read 3, iclass 21, count 0 2006.257.23:56:06.85#ibcon#about to read 4, iclass 21, count 0 2006.257.23:56:06.85#ibcon#read 4, iclass 21, count 0 2006.257.23:56:06.85#ibcon#about to read 5, iclass 21, count 0 2006.257.23:56:06.85#ibcon#read 5, iclass 21, count 0 2006.257.23:56:06.85#ibcon#about to read 6, iclass 21, count 0 2006.257.23:56:06.85#ibcon#read 6, iclass 21, count 0 2006.257.23:56:06.85#ibcon#end of sib2, iclass 21, count 0 2006.257.23:56:06.85#ibcon#*mode == 0, iclass 21, count 0 2006.257.23:56:06.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.257.23:56:06.85#ibcon#[27=USB\r\n] 2006.257.23:56:06.85#ibcon#*before write, iclass 21, count 0 2006.257.23:56:06.85#ibcon#enter sib2, iclass 21, count 0 2006.257.23:56:06.85#ibcon#flushed, iclass 21, count 0 2006.257.23:56:06.85#ibcon#about to write, iclass 21, count 0 2006.257.23:56:06.85#ibcon#wrote, iclass 21, count 0 2006.257.23:56:06.85#ibcon#about to read 3, iclass 21, count 0 2006.257.23:56:06.88#ibcon#read 3, iclass 21, count 0 2006.257.23:56:06.88#ibcon#about to read 4, iclass 21, count 0 2006.257.23:56:06.88#ibcon#read 4, iclass 21, count 0 2006.257.23:56:06.88#ibcon#about to read 5, iclass 21, count 0 2006.257.23:56:06.88#ibcon#read 5, iclass 21, count 0 2006.257.23:56:06.88#ibcon#about to read 6, iclass 21, count 0 2006.257.23:56:06.88#ibcon#read 6, iclass 21, count 0 2006.257.23:56:06.88#ibcon#end of sib2, iclass 21, count 0 2006.257.23:56:06.88#ibcon#*after write, iclass 21, count 0 2006.257.23:56:06.88#ibcon#*before return 0, iclass 21, count 0 2006.257.23:56:06.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:06.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.257.23:56:06.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.257.23:56:06.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.257.23:56:06.88$vck44/vabw=wide 2006.257.23:56:06.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.257.23:56:06.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.257.23:56:06.88#ibcon#ireg 8 cls_cnt 0 2006.257.23:56:06.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:06.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:06.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:06.88#ibcon#enter wrdev, iclass 23, count 0 2006.257.23:56:06.88#ibcon#first serial, iclass 23, count 0 2006.257.23:56:06.88#ibcon#enter sib2, iclass 23, count 0 2006.257.23:56:06.88#ibcon#flushed, iclass 23, count 0 2006.257.23:56:06.88#ibcon#about to write, iclass 23, count 0 2006.257.23:56:06.88#ibcon#wrote, iclass 23, count 0 2006.257.23:56:06.88#ibcon#about to read 3, iclass 23, count 0 2006.257.23:56:06.90#ibcon#read 3, iclass 23, count 0 2006.257.23:56:06.90#ibcon#about to read 4, iclass 23, count 0 2006.257.23:56:06.90#ibcon#read 4, iclass 23, count 0 2006.257.23:56:06.90#ibcon#about to read 5, iclass 23, count 0 2006.257.23:56:06.90#ibcon#read 5, iclass 23, count 0 2006.257.23:56:06.90#ibcon#about to read 6, iclass 23, count 0 2006.257.23:56:06.90#ibcon#read 6, iclass 23, count 0 2006.257.23:56:06.90#ibcon#end of sib2, iclass 23, count 0 2006.257.23:56:06.90#ibcon#*mode == 0, iclass 23, count 0 2006.257.23:56:06.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.257.23:56:06.90#ibcon#[25=BW32\r\n] 2006.257.23:56:06.90#ibcon#*before write, iclass 23, count 0 2006.257.23:56:06.90#ibcon#enter sib2, iclass 23, count 0 2006.257.23:56:06.90#ibcon#flushed, iclass 23, count 0 2006.257.23:56:06.90#ibcon#about to write, iclass 23, count 0 2006.257.23:56:06.90#ibcon#wrote, iclass 23, count 0 2006.257.23:56:06.90#ibcon#about to read 3, iclass 23, count 0 2006.257.23:56:06.93#ibcon#read 3, iclass 23, count 0 2006.257.23:56:06.93#ibcon#about to read 4, iclass 23, count 0 2006.257.23:56:06.93#ibcon#read 4, iclass 23, count 0 2006.257.23:56:06.93#ibcon#about to read 5, iclass 23, count 0 2006.257.23:56:06.93#ibcon#read 5, iclass 23, count 0 2006.257.23:56:06.93#ibcon#about to read 6, iclass 23, count 0 2006.257.23:56:06.93#ibcon#read 6, iclass 23, count 0 2006.257.23:56:06.93#ibcon#end of sib2, iclass 23, count 0 2006.257.23:56:06.93#ibcon#*after write, iclass 23, count 0 2006.257.23:56:06.93#ibcon#*before return 0, iclass 23, count 0 2006.257.23:56:06.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:06.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.257.23:56:06.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.257.23:56:06.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.257.23:56:06.93$vck44/vbbw=wide 2006.257.23:56:06.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.257.23:56:06.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.257.23:56:06.93#ibcon#ireg 8 cls_cnt 0 2006.257.23:56:06.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:56:07.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:56:07.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:56:07.00#ibcon#enter wrdev, iclass 25, count 0 2006.257.23:56:07.00#ibcon#first serial, iclass 25, count 0 2006.257.23:56:07.00#ibcon#enter sib2, iclass 25, count 0 2006.257.23:56:07.00#ibcon#flushed, iclass 25, count 0 2006.257.23:56:07.00#ibcon#about to write, iclass 25, count 0 2006.257.23:56:07.00#ibcon#wrote, iclass 25, count 0 2006.257.23:56:07.00#ibcon#about to read 3, iclass 25, count 0 2006.257.23:56:07.02#ibcon#read 3, iclass 25, count 0 2006.257.23:56:07.02#ibcon#about to read 4, iclass 25, count 0 2006.257.23:56:07.02#ibcon#read 4, iclass 25, count 0 2006.257.23:56:07.02#ibcon#about to read 5, iclass 25, count 0 2006.257.23:56:07.02#ibcon#read 5, iclass 25, count 0 2006.257.23:56:07.02#ibcon#about to read 6, iclass 25, count 0 2006.257.23:56:07.02#ibcon#read 6, iclass 25, count 0 2006.257.23:56:07.02#ibcon#end of sib2, iclass 25, count 0 2006.257.23:56:07.02#ibcon#*mode == 0, iclass 25, count 0 2006.257.23:56:07.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.257.23:56:07.02#ibcon#[27=BW32\r\n] 2006.257.23:56:07.02#ibcon#*before write, iclass 25, count 0 2006.257.23:56:07.02#ibcon#enter sib2, iclass 25, count 0 2006.257.23:56:07.02#ibcon#flushed, iclass 25, count 0 2006.257.23:56:07.02#ibcon#about to write, iclass 25, count 0 2006.257.23:56:07.02#ibcon#wrote, iclass 25, count 0 2006.257.23:56:07.02#ibcon#about to read 3, iclass 25, count 0 2006.257.23:56:07.05#ibcon#read 3, iclass 25, count 0 2006.257.23:56:07.05#ibcon#about to read 4, iclass 25, count 0 2006.257.23:56:07.05#ibcon#read 4, iclass 25, count 0 2006.257.23:56:07.05#ibcon#about to read 5, iclass 25, count 0 2006.257.23:56:07.05#ibcon#read 5, iclass 25, count 0 2006.257.23:56:07.05#ibcon#about to read 6, iclass 25, count 0 2006.257.23:56:07.05#ibcon#read 6, iclass 25, count 0 2006.257.23:56:07.05#ibcon#end of sib2, iclass 25, count 0 2006.257.23:56:07.05#ibcon#*after write, iclass 25, count 0 2006.257.23:56:07.05#ibcon#*before return 0, iclass 25, count 0 2006.257.23:56:07.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:56:07.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.257.23:56:07.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.257.23:56:07.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.257.23:56:07.05$setupk4/ifdk4 2006.257.23:56:07.05$ifdk4/lo= 2006.257.23:56:07.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:56:07.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:56:07.05$ifdk4/patch= 2006.257.23:56:07.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:56:07.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:56:07.05$setupk4/!*+20s 2006.257.23:56:13.68#abcon#<5=/02 2.0 5.3 21.21 801016.2\r\n> 2006.257.23:56:13.70#abcon#{5=INTERFACE CLEAR} 2006.257.23:56:13.76#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:56:21.14#trakl#Source acquired 2006.257.23:56:21.14#flagr#flagr/antenna,acquired 2006.257.23:56:21.56$setupk4/"tpicd 2006.257.23:56:21.56$setupk4/echo=off 2006.257.23:56:21.56$setupk4/xlog=off 2006.257.23:56:21.56:!2006.257.23:57:48 2006.257.23:57:48.00:preob 2006.257.23:57:49.13/onsource/TRACKING 2006.257.23:57:49.13:!2006.257.23:57:58 2006.257.23:57:58.00:"tape 2006.257.23:57:58.00:"st=record 2006.257.23:57:58.00:data_valid=on 2006.257.23:57:58.00:midob 2006.257.23:57:58.13/onsource/TRACKING 2006.257.23:57:58.13/wx/21.27,1016.2,80 2006.257.23:57:58.29/cable/+6.4819E-03 2006.257.23:57:59.38/va/01,08,usb,yes,31,34 2006.257.23:57:59.38/va/02,07,usb,yes,34,34 2006.257.23:57:59.38/va/03,08,usb,yes,30,32 2006.257.23:57:59.38/va/04,07,usb,yes,35,36 2006.257.23:57:59.38/va/05,04,usb,yes,31,31 2006.257.23:57:59.38/va/06,04,usb,yes,34,34 2006.257.23:57:59.38/va/07,04,usb,yes,35,36 2006.257.23:57:59.38/va/08,04,usb,yes,29,36 2006.257.23:57:59.61/valo/01,524.99,yes,locked 2006.257.23:57:59.61/valo/02,534.99,yes,locked 2006.257.23:57:59.61/valo/03,564.99,yes,locked 2006.257.23:57:59.61/valo/04,624.99,yes,locked 2006.257.23:57:59.61/valo/05,734.99,yes,locked 2006.257.23:57:59.61/valo/06,814.99,yes,locked 2006.257.23:57:59.61/valo/07,864.99,yes,locked 2006.257.23:57:59.61/valo/08,884.99,yes,locked 2006.257.23:58:00.70/vb/01,04,usb,yes,31,29 2006.257.23:58:00.70/vb/02,05,usb,yes,29,29 2006.257.23:58:00.70/vb/03,04,usb,yes,30,33 2006.257.23:58:00.70/vb/04,05,usb,yes,30,29 2006.257.23:58:00.70/vb/05,04,usb,yes,27,29 2006.257.23:58:00.70/vb/06,04,usb,yes,31,27 2006.257.23:58:00.70/vb/07,04,usb,yes,31,31 2006.257.23:58:00.70/vb/08,04,usb,yes,28,32 2006.257.23:58:00.93/vblo/01,629.99,yes,locked 2006.257.23:58:00.93/vblo/02,634.99,yes,locked 2006.257.23:58:00.93/vblo/03,649.99,yes,locked 2006.257.23:58:00.93/vblo/04,679.99,yes,locked 2006.257.23:58:00.93/vblo/05,709.99,yes,locked 2006.257.23:58:00.93/vblo/06,719.99,yes,locked 2006.257.23:58:00.93/vblo/07,734.99,yes,locked 2006.257.23:58:00.93/vblo/08,744.99,yes,locked 2006.257.23:58:01.08/vabw/8 2006.257.23:58:01.23/vbbw/8 2006.257.23:58:01.32/xfe/off,on,15.2 2006.257.23:58:01.70/ifatt/23,28,28,28 2006.257.23:58:02.08/fmout-gps/S +4.54E-07 2006.257.23:58:02.11:!2006.257.23:58:58 2006.257.23:58:58.00:data_valid=off 2006.257.23:58:58.00:"et 2006.257.23:58:58.00:!+3s 2006.257.23:59:01.01:"tape 2006.257.23:59:01.01:postob 2006.257.23:59:01.20/cable/+6.4808E-03 2006.257.23:59:01.20/wx/21.29,1016.2,80 2006.257.23:59:02.08/fmout-gps/S +4.54E-07 2006.257.23:59:02.08:scan_name=258-0001,jd0609,40 2006.257.23:59:02.08:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.257.23:59:02.13#flagr#flagr/antenna,new-source 2006.257.23:59:03.13:checkk5 2006.257.23:59:03.47/chk_autoobs//k5ts1/ autoobs is running! 2006.257.23:59:03.81/chk_autoobs//k5ts2/ autoobs is running! 2006.257.23:59:04.16/chk_autoobs//k5ts3/ autoobs is running! 2006.257.23:59:04.50/chk_autoobs//k5ts4/ autoobs is running! 2006.257.23:59:04.84/chk_obsdata//k5ts1/T2572357??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.23:59:05.19/chk_obsdata//k5ts2/T2572357??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.23:59:05.53/chk_obsdata//k5ts3/T2572357??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.23:59:05.87/chk_obsdata//k5ts4/T2572357??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.257.23:59:06.54/k5log//k5ts1_log_newline 2006.257.23:59:07.19/k5log//k5ts2_log_newline 2006.257.23:59:07.85/k5log//k5ts3_log_newline 2006.257.23:59:08.51/k5log//k5ts4_log_newline 2006.257.23:59:08.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.257.23:59:08.54:setupk4=1 2006.257.23:59:08.54$setupk4/echo=on 2006.257.23:59:08.54$setupk4/pcalon 2006.257.23:59:08.54$pcalon/"no phase cal control is implemented here 2006.257.23:59:08.54$setupk4/"tpicd=stop 2006.257.23:59:08.54$setupk4/"rec=synch_on 2006.257.23:59:08.54$setupk4/"rec_mode=128 2006.257.23:59:08.54$setupk4/!* 2006.257.23:59:08.54$setupk4/recpk4 2006.257.23:59:08.54$recpk4/recpatch= 2006.257.23:59:08.54$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.257.23:59:08.54$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.257.23:59:08.54$setupk4/vck44 2006.257.23:59:08.54$vck44/valo=1,524.99 2006.257.23:59:08.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.23:59:08.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.23:59:08.54#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:08.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:08.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:08.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:08.54#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:59:08.54#ibcon#first serial, iclass 30, count 0 2006.257.23:59:08.54#ibcon#enter sib2, iclass 30, count 0 2006.257.23:59:08.54#ibcon#flushed, iclass 30, count 0 2006.257.23:59:08.54#ibcon#about to write, iclass 30, count 0 2006.257.23:59:08.54#ibcon#wrote, iclass 30, count 0 2006.257.23:59:08.54#ibcon#about to read 3, iclass 30, count 0 2006.257.23:59:08.56#ibcon#read 3, iclass 30, count 0 2006.257.23:59:08.56#ibcon#about to read 4, iclass 30, count 0 2006.257.23:59:08.56#ibcon#read 4, iclass 30, count 0 2006.257.23:59:08.56#ibcon#about to read 5, iclass 30, count 0 2006.257.23:59:08.56#ibcon#read 5, iclass 30, count 0 2006.257.23:59:08.56#ibcon#about to read 6, iclass 30, count 0 2006.257.23:59:08.56#ibcon#read 6, iclass 30, count 0 2006.257.23:59:08.56#ibcon#end of sib2, iclass 30, count 0 2006.257.23:59:08.56#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:59:08.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:59:08.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.257.23:59:08.56#ibcon#*before write, iclass 30, count 0 2006.257.23:59:08.56#ibcon#enter sib2, iclass 30, count 0 2006.257.23:59:08.56#ibcon#flushed, iclass 30, count 0 2006.257.23:59:08.56#ibcon#about to write, iclass 30, count 0 2006.257.23:59:08.56#ibcon#wrote, iclass 30, count 0 2006.257.23:59:08.56#ibcon#about to read 3, iclass 30, count 0 2006.257.23:59:08.61#ibcon#read 3, iclass 30, count 0 2006.257.23:59:08.61#ibcon#about to read 4, iclass 30, count 0 2006.257.23:59:08.61#ibcon#read 4, iclass 30, count 0 2006.257.23:59:08.61#ibcon#about to read 5, iclass 30, count 0 2006.257.23:59:08.61#ibcon#read 5, iclass 30, count 0 2006.257.23:59:08.61#ibcon#about to read 6, iclass 30, count 0 2006.257.23:59:08.61#ibcon#read 6, iclass 30, count 0 2006.257.23:59:08.61#ibcon#end of sib2, iclass 30, count 0 2006.257.23:59:08.61#ibcon#*after write, iclass 30, count 0 2006.257.23:59:08.61#ibcon#*before return 0, iclass 30, count 0 2006.257.23:59:08.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:08.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:08.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:59:08.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:59:08.61$vck44/va=1,8 2006.257.23:59:08.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.23:59:08.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.23:59:08.61#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:08.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:08.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:08.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:08.61#ibcon#enter wrdev, iclass 32, count 2 2006.257.23:59:08.61#ibcon#first serial, iclass 32, count 2 2006.257.23:59:08.61#ibcon#enter sib2, iclass 32, count 2 2006.257.23:59:08.61#ibcon#flushed, iclass 32, count 2 2006.257.23:59:08.61#ibcon#about to write, iclass 32, count 2 2006.257.23:59:08.61#ibcon#wrote, iclass 32, count 2 2006.257.23:59:08.61#ibcon#about to read 3, iclass 32, count 2 2006.257.23:59:08.63#ibcon#read 3, iclass 32, count 2 2006.257.23:59:08.63#ibcon#about to read 4, iclass 32, count 2 2006.257.23:59:08.63#ibcon#read 4, iclass 32, count 2 2006.257.23:59:08.63#ibcon#about to read 5, iclass 32, count 2 2006.257.23:59:08.63#ibcon#read 5, iclass 32, count 2 2006.257.23:59:08.63#ibcon#about to read 6, iclass 32, count 2 2006.257.23:59:08.63#ibcon#read 6, iclass 32, count 2 2006.257.23:59:08.63#ibcon#end of sib2, iclass 32, count 2 2006.257.23:59:08.63#ibcon#*mode == 0, iclass 32, count 2 2006.257.23:59:08.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.23:59:08.63#ibcon#[25=AT01-08\r\n] 2006.257.23:59:08.63#ibcon#*before write, iclass 32, count 2 2006.257.23:59:08.63#ibcon#enter sib2, iclass 32, count 2 2006.257.23:59:08.63#ibcon#flushed, iclass 32, count 2 2006.257.23:59:08.63#ibcon#about to write, iclass 32, count 2 2006.257.23:59:08.63#ibcon#wrote, iclass 32, count 2 2006.257.23:59:08.63#ibcon#about to read 3, iclass 32, count 2 2006.257.23:59:08.66#ibcon#read 3, iclass 32, count 2 2006.257.23:59:08.66#ibcon#about to read 4, iclass 32, count 2 2006.257.23:59:08.66#ibcon#read 4, iclass 32, count 2 2006.257.23:59:08.66#ibcon#about to read 5, iclass 32, count 2 2006.257.23:59:08.66#ibcon#read 5, iclass 32, count 2 2006.257.23:59:08.66#ibcon#about to read 6, iclass 32, count 2 2006.257.23:59:08.66#ibcon#read 6, iclass 32, count 2 2006.257.23:59:08.66#ibcon#end of sib2, iclass 32, count 2 2006.257.23:59:08.66#ibcon#*after write, iclass 32, count 2 2006.257.23:59:08.66#ibcon#*before return 0, iclass 32, count 2 2006.257.23:59:08.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:08.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:08.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.23:59:08.66#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:08.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:08.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:08.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:08.78#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:59:08.78#ibcon#first serial, iclass 32, count 0 2006.257.23:59:08.78#ibcon#enter sib2, iclass 32, count 0 2006.257.23:59:08.78#ibcon#flushed, iclass 32, count 0 2006.257.23:59:08.78#ibcon#about to write, iclass 32, count 0 2006.257.23:59:08.78#ibcon#wrote, iclass 32, count 0 2006.257.23:59:08.78#ibcon#about to read 3, iclass 32, count 0 2006.257.23:59:08.80#ibcon#read 3, iclass 32, count 0 2006.257.23:59:08.80#ibcon#about to read 4, iclass 32, count 0 2006.257.23:59:08.80#ibcon#read 4, iclass 32, count 0 2006.257.23:59:08.80#ibcon#about to read 5, iclass 32, count 0 2006.257.23:59:08.80#ibcon#read 5, iclass 32, count 0 2006.257.23:59:08.80#ibcon#about to read 6, iclass 32, count 0 2006.257.23:59:08.80#ibcon#read 6, iclass 32, count 0 2006.257.23:59:08.80#ibcon#end of sib2, iclass 32, count 0 2006.257.23:59:08.80#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:59:08.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:59:08.80#ibcon#[25=USB\r\n] 2006.257.23:59:08.80#ibcon#*before write, iclass 32, count 0 2006.257.23:59:08.80#ibcon#enter sib2, iclass 32, count 0 2006.257.23:59:08.80#ibcon#flushed, iclass 32, count 0 2006.257.23:59:08.80#ibcon#about to write, iclass 32, count 0 2006.257.23:59:08.80#ibcon#wrote, iclass 32, count 0 2006.257.23:59:08.80#ibcon#about to read 3, iclass 32, count 0 2006.257.23:59:08.83#ibcon#read 3, iclass 32, count 0 2006.257.23:59:08.83#ibcon#about to read 4, iclass 32, count 0 2006.257.23:59:08.83#ibcon#read 4, iclass 32, count 0 2006.257.23:59:08.83#ibcon#about to read 5, iclass 32, count 0 2006.257.23:59:08.83#ibcon#read 5, iclass 32, count 0 2006.257.23:59:08.83#ibcon#about to read 6, iclass 32, count 0 2006.257.23:59:08.83#ibcon#read 6, iclass 32, count 0 2006.257.23:59:08.83#ibcon#end of sib2, iclass 32, count 0 2006.257.23:59:08.83#ibcon#*after write, iclass 32, count 0 2006.257.23:59:08.83#ibcon#*before return 0, iclass 32, count 0 2006.257.23:59:08.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:08.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:08.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:59:08.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:59:08.83$vck44/valo=2,534.99 2006.257.23:59:08.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.23:59:08.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.23:59:08.83#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:08.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:08.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:08.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:08.83#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:59:08.83#ibcon#first serial, iclass 34, count 0 2006.257.23:59:08.83#ibcon#enter sib2, iclass 34, count 0 2006.257.23:59:08.83#ibcon#flushed, iclass 34, count 0 2006.257.23:59:08.83#ibcon#about to write, iclass 34, count 0 2006.257.23:59:08.83#ibcon#wrote, iclass 34, count 0 2006.257.23:59:08.83#ibcon#about to read 3, iclass 34, count 0 2006.257.23:59:08.85#ibcon#read 3, iclass 34, count 0 2006.257.23:59:08.85#ibcon#about to read 4, iclass 34, count 0 2006.257.23:59:08.85#ibcon#read 4, iclass 34, count 0 2006.257.23:59:08.85#ibcon#about to read 5, iclass 34, count 0 2006.257.23:59:08.85#ibcon#read 5, iclass 34, count 0 2006.257.23:59:08.85#ibcon#about to read 6, iclass 34, count 0 2006.257.23:59:08.85#ibcon#read 6, iclass 34, count 0 2006.257.23:59:08.85#ibcon#end of sib2, iclass 34, count 0 2006.257.23:59:08.85#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:59:08.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:59:08.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.257.23:59:08.85#ibcon#*before write, iclass 34, count 0 2006.257.23:59:08.85#ibcon#enter sib2, iclass 34, count 0 2006.257.23:59:08.85#ibcon#flushed, iclass 34, count 0 2006.257.23:59:08.85#ibcon#about to write, iclass 34, count 0 2006.257.23:59:08.85#ibcon#wrote, iclass 34, count 0 2006.257.23:59:08.85#ibcon#about to read 3, iclass 34, count 0 2006.257.23:59:08.89#ibcon#read 3, iclass 34, count 0 2006.257.23:59:08.89#ibcon#about to read 4, iclass 34, count 0 2006.257.23:59:08.89#ibcon#read 4, iclass 34, count 0 2006.257.23:59:08.89#ibcon#about to read 5, iclass 34, count 0 2006.257.23:59:08.89#ibcon#read 5, iclass 34, count 0 2006.257.23:59:08.89#ibcon#about to read 6, iclass 34, count 0 2006.257.23:59:08.89#ibcon#read 6, iclass 34, count 0 2006.257.23:59:08.89#ibcon#end of sib2, iclass 34, count 0 2006.257.23:59:08.89#ibcon#*after write, iclass 34, count 0 2006.257.23:59:08.89#ibcon#*before return 0, iclass 34, count 0 2006.257.23:59:08.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:08.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:08.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:59:08.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:59:08.89$vck44/va=2,7 2006.257.23:59:08.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.23:59:08.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.23:59:08.89#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:08.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:08.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:08.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:08.95#ibcon#enter wrdev, iclass 36, count 2 2006.257.23:59:08.95#ibcon#first serial, iclass 36, count 2 2006.257.23:59:08.95#ibcon#enter sib2, iclass 36, count 2 2006.257.23:59:08.95#ibcon#flushed, iclass 36, count 2 2006.257.23:59:08.95#ibcon#about to write, iclass 36, count 2 2006.257.23:59:08.95#ibcon#wrote, iclass 36, count 2 2006.257.23:59:08.95#ibcon#about to read 3, iclass 36, count 2 2006.257.23:59:08.97#ibcon#read 3, iclass 36, count 2 2006.257.23:59:08.97#ibcon#about to read 4, iclass 36, count 2 2006.257.23:59:08.97#ibcon#read 4, iclass 36, count 2 2006.257.23:59:08.97#ibcon#about to read 5, iclass 36, count 2 2006.257.23:59:08.97#ibcon#read 5, iclass 36, count 2 2006.257.23:59:08.97#ibcon#about to read 6, iclass 36, count 2 2006.257.23:59:08.97#ibcon#read 6, iclass 36, count 2 2006.257.23:59:08.97#ibcon#end of sib2, iclass 36, count 2 2006.257.23:59:08.97#ibcon#*mode == 0, iclass 36, count 2 2006.257.23:59:08.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.23:59:08.97#ibcon#[25=AT02-07\r\n] 2006.257.23:59:08.97#ibcon#*before write, iclass 36, count 2 2006.257.23:59:08.97#ibcon#enter sib2, iclass 36, count 2 2006.257.23:59:08.97#ibcon#flushed, iclass 36, count 2 2006.257.23:59:08.97#ibcon#about to write, iclass 36, count 2 2006.257.23:59:08.97#ibcon#wrote, iclass 36, count 2 2006.257.23:59:08.97#ibcon#about to read 3, iclass 36, count 2 2006.257.23:59:09.00#ibcon#read 3, iclass 36, count 2 2006.257.23:59:09.00#ibcon#about to read 4, iclass 36, count 2 2006.257.23:59:09.00#ibcon#read 4, iclass 36, count 2 2006.257.23:59:09.00#ibcon#about to read 5, iclass 36, count 2 2006.257.23:59:09.00#ibcon#read 5, iclass 36, count 2 2006.257.23:59:09.00#ibcon#about to read 6, iclass 36, count 2 2006.257.23:59:09.00#ibcon#read 6, iclass 36, count 2 2006.257.23:59:09.00#ibcon#end of sib2, iclass 36, count 2 2006.257.23:59:09.00#ibcon#*after write, iclass 36, count 2 2006.257.23:59:09.00#ibcon#*before return 0, iclass 36, count 2 2006.257.23:59:09.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:09.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:09.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.23:59:09.00#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:09.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:09.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:09.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:09.12#ibcon#enter wrdev, iclass 36, count 0 2006.257.23:59:09.12#ibcon#first serial, iclass 36, count 0 2006.257.23:59:09.12#ibcon#enter sib2, iclass 36, count 0 2006.257.23:59:09.12#ibcon#flushed, iclass 36, count 0 2006.257.23:59:09.12#ibcon#about to write, iclass 36, count 0 2006.257.23:59:09.12#ibcon#wrote, iclass 36, count 0 2006.257.23:59:09.12#ibcon#about to read 3, iclass 36, count 0 2006.257.23:59:09.14#ibcon#read 3, iclass 36, count 0 2006.257.23:59:09.14#ibcon#about to read 4, iclass 36, count 0 2006.257.23:59:09.14#ibcon#read 4, iclass 36, count 0 2006.257.23:59:09.14#ibcon#about to read 5, iclass 36, count 0 2006.257.23:59:09.14#ibcon#read 5, iclass 36, count 0 2006.257.23:59:09.14#ibcon#about to read 6, iclass 36, count 0 2006.257.23:59:09.14#ibcon#read 6, iclass 36, count 0 2006.257.23:59:09.14#ibcon#end of sib2, iclass 36, count 0 2006.257.23:59:09.14#ibcon#*mode == 0, iclass 36, count 0 2006.257.23:59:09.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.23:59:09.14#ibcon#[25=USB\r\n] 2006.257.23:59:09.14#ibcon#*before write, iclass 36, count 0 2006.257.23:59:09.14#ibcon#enter sib2, iclass 36, count 0 2006.257.23:59:09.14#ibcon#flushed, iclass 36, count 0 2006.257.23:59:09.14#ibcon#about to write, iclass 36, count 0 2006.257.23:59:09.14#ibcon#wrote, iclass 36, count 0 2006.257.23:59:09.14#ibcon#about to read 3, iclass 36, count 0 2006.257.23:59:09.17#ibcon#read 3, iclass 36, count 0 2006.257.23:59:09.17#ibcon#about to read 4, iclass 36, count 0 2006.257.23:59:09.17#ibcon#read 4, iclass 36, count 0 2006.257.23:59:09.17#ibcon#about to read 5, iclass 36, count 0 2006.257.23:59:09.17#ibcon#read 5, iclass 36, count 0 2006.257.23:59:09.17#ibcon#about to read 6, iclass 36, count 0 2006.257.23:59:09.17#ibcon#read 6, iclass 36, count 0 2006.257.23:59:09.17#ibcon#end of sib2, iclass 36, count 0 2006.257.23:59:09.17#ibcon#*after write, iclass 36, count 0 2006.257.23:59:09.17#ibcon#*before return 0, iclass 36, count 0 2006.257.23:59:09.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:09.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:09.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.23:59:09.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.23:59:09.17$vck44/valo=3,564.99 2006.257.23:59:09.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.23:59:09.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.23:59:09.17#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:09.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:09.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:09.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:09.17#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:59:09.17#ibcon#first serial, iclass 38, count 0 2006.257.23:59:09.17#ibcon#enter sib2, iclass 38, count 0 2006.257.23:59:09.17#ibcon#flushed, iclass 38, count 0 2006.257.23:59:09.17#ibcon#about to write, iclass 38, count 0 2006.257.23:59:09.17#ibcon#wrote, iclass 38, count 0 2006.257.23:59:09.17#ibcon#about to read 3, iclass 38, count 0 2006.257.23:59:09.19#ibcon#read 3, iclass 38, count 0 2006.257.23:59:09.19#ibcon#about to read 4, iclass 38, count 0 2006.257.23:59:09.19#ibcon#read 4, iclass 38, count 0 2006.257.23:59:09.19#ibcon#about to read 5, iclass 38, count 0 2006.257.23:59:09.19#ibcon#read 5, iclass 38, count 0 2006.257.23:59:09.19#ibcon#about to read 6, iclass 38, count 0 2006.257.23:59:09.19#ibcon#read 6, iclass 38, count 0 2006.257.23:59:09.19#ibcon#end of sib2, iclass 38, count 0 2006.257.23:59:09.19#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:59:09.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:59:09.19#ibcon#[26=FRQ=03,564.99\r\n] 2006.257.23:59:09.19#ibcon#*before write, iclass 38, count 0 2006.257.23:59:09.19#ibcon#enter sib2, iclass 38, count 0 2006.257.23:59:09.19#ibcon#flushed, iclass 38, count 0 2006.257.23:59:09.19#ibcon#about to write, iclass 38, count 0 2006.257.23:59:09.19#ibcon#wrote, iclass 38, count 0 2006.257.23:59:09.19#ibcon#about to read 3, iclass 38, count 0 2006.257.23:59:09.23#ibcon#read 3, iclass 38, count 0 2006.257.23:59:09.23#ibcon#about to read 4, iclass 38, count 0 2006.257.23:59:09.23#ibcon#read 4, iclass 38, count 0 2006.257.23:59:09.23#ibcon#about to read 5, iclass 38, count 0 2006.257.23:59:09.23#ibcon#read 5, iclass 38, count 0 2006.257.23:59:09.23#ibcon#about to read 6, iclass 38, count 0 2006.257.23:59:09.23#ibcon#read 6, iclass 38, count 0 2006.257.23:59:09.23#ibcon#end of sib2, iclass 38, count 0 2006.257.23:59:09.23#ibcon#*after write, iclass 38, count 0 2006.257.23:59:09.23#ibcon#*before return 0, iclass 38, count 0 2006.257.23:59:09.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:09.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:09.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:59:09.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:59:09.23$vck44/va=3,8 2006.257.23:59:09.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.23:59:09.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.23:59:09.23#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:09.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:09.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:09.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:09.29#ibcon#enter wrdev, iclass 40, count 2 2006.257.23:59:09.29#ibcon#first serial, iclass 40, count 2 2006.257.23:59:09.29#ibcon#enter sib2, iclass 40, count 2 2006.257.23:59:09.29#ibcon#flushed, iclass 40, count 2 2006.257.23:59:09.29#ibcon#about to write, iclass 40, count 2 2006.257.23:59:09.29#ibcon#wrote, iclass 40, count 2 2006.257.23:59:09.29#ibcon#about to read 3, iclass 40, count 2 2006.257.23:59:09.31#ibcon#read 3, iclass 40, count 2 2006.257.23:59:09.31#ibcon#about to read 4, iclass 40, count 2 2006.257.23:59:09.31#ibcon#read 4, iclass 40, count 2 2006.257.23:59:09.31#ibcon#about to read 5, iclass 40, count 2 2006.257.23:59:09.31#ibcon#read 5, iclass 40, count 2 2006.257.23:59:09.31#ibcon#about to read 6, iclass 40, count 2 2006.257.23:59:09.31#ibcon#read 6, iclass 40, count 2 2006.257.23:59:09.31#ibcon#end of sib2, iclass 40, count 2 2006.257.23:59:09.31#ibcon#*mode == 0, iclass 40, count 2 2006.257.23:59:09.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.23:59:09.31#ibcon#[25=AT03-08\r\n] 2006.257.23:59:09.31#ibcon#*before write, iclass 40, count 2 2006.257.23:59:09.31#ibcon#enter sib2, iclass 40, count 2 2006.257.23:59:09.31#ibcon#flushed, iclass 40, count 2 2006.257.23:59:09.31#ibcon#about to write, iclass 40, count 2 2006.257.23:59:09.31#ibcon#wrote, iclass 40, count 2 2006.257.23:59:09.31#ibcon#about to read 3, iclass 40, count 2 2006.257.23:59:09.34#ibcon#read 3, iclass 40, count 2 2006.257.23:59:09.34#ibcon#about to read 4, iclass 40, count 2 2006.257.23:59:09.34#ibcon#read 4, iclass 40, count 2 2006.257.23:59:09.34#ibcon#about to read 5, iclass 40, count 2 2006.257.23:59:09.34#ibcon#read 5, iclass 40, count 2 2006.257.23:59:09.34#ibcon#about to read 6, iclass 40, count 2 2006.257.23:59:09.34#ibcon#read 6, iclass 40, count 2 2006.257.23:59:09.34#ibcon#end of sib2, iclass 40, count 2 2006.257.23:59:09.34#ibcon#*after write, iclass 40, count 2 2006.257.23:59:09.34#ibcon#*before return 0, iclass 40, count 2 2006.257.23:59:09.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:09.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:09.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.23:59:09.34#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:09.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:09.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:09.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:09.46#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:59:09.46#ibcon#first serial, iclass 40, count 0 2006.257.23:59:09.46#ibcon#enter sib2, iclass 40, count 0 2006.257.23:59:09.46#ibcon#flushed, iclass 40, count 0 2006.257.23:59:09.46#ibcon#about to write, iclass 40, count 0 2006.257.23:59:09.46#ibcon#wrote, iclass 40, count 0 2006.257.23:59:09.46#ibcon#about to read 3, iclass 40, count 0 2006.257.23:59:09.48#ibcon#read 3, iclass 40, count 0 2006.257.23:59:09.48#ibcon#about to read 4, iclass 40, count 0 2006.257.23:59:09.48#ibcon#read 4, iclass 40, count 0 2006.257.23:59:09.48#ibcon#about to read 5, iclass 40, count 0 2006.257.23:59:09.48#ibcon#read 5, iclass 40, count 0 2006.257.23:59:09.48#ibcon#about to read 6, iclass 40, count 0 2006.257.23:59:09.48#ibcon#read 6, iclass 40, count 0 2006.257.23:59:09.48#ibcon#end of sib2, iclass 40, count 0 2006.257.23:59:09.48#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:59:09.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:59:09.48#ibcon#[25=USB\r\n] 2006.257.23:59:09.48#ibcon#*before write, iclass 40, count 0 2006.257.23:59:09.48#ibcon#enter sib2, iclass 40, count 0 2006.257.23:59:09.48#ibcon#flushed, iclass 40, count 0 2006.257.23:59:09.48#ibcon#about to write, iclass 40, count 0 2006.257.23:59:09.48#ibcon#wrote, iclass 40, count 0 2006.257.23:59:09.48#ibcon#about to read 3, iclass 40, count 0 2006.257.23:59:09.51#ibcon#read 3, iclass 40, count 0 2006.257.23:59:09.51#ibcon#about to read 4, iclass 40, count 0 2006.257.23:59:09.51#ibcon#read 4, iclass 40, count 0 2006.257.23:59:09.51#ibcon#about to read 5, iclass 40, count 0 2006.257.23:59:09.51#ibcon#read 5, iclass 40, count 0 2006.257.23:59:09.51#ibcon#about to read 6, iclass 40, count 0 2006.257.23:59:09.51#ibcon#read 6, iclass 40, count 0 2006.257.23:59:09.51#ibcon#end of sib2, iclass 40, count 0 2006.257.23:59:09.51#ibcon#*after write, iclass 40, count 0 2006.257.23:59:09.51#ibcon#*before return 0, iclass 40, count 0 2006.257.23:59:09.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:09.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:09.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:59:09.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:59:09.51$vck44/valo=4,624.99 2006.257.23:59:09.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.23:59:09.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.23:59:09.51#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:09.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:09.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:09.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:09.51#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:59:09.51#ibcon#first serial, iclass 4, count 0 2006.257.23:59:09.51#ibcon#enter sib2, iclass 4, count 0 2006.257.23:59:09.51#ibcon#flushed, iclass 4, count 0 2006.257.23:59:09.51#ibcon#about to write, iclass 4, count 0 2006.257.23:59:09.51#ibcon#wrote, iclass 4, count 0 2006.257.23:59:09.51#ibcon#about to read 3, iclass 4, count 0 2006.257.23:59:09.53#ibcon#read 3, iclass 4, count 0 2006.257.23:59:09.53#ibcon#about to read 4, iclass 4, count 0 2006.257.23:59:09.53#ibcon#read 4, iclass 4, count 0 2006.257.23:59:09.53#ibcon#about to read 5, iclass 4, count 0 2006.257.23:59:09.53#ibcon#read 5, iclass 4, count 0 2006.257.23:59:09.53#ibcon#about to read 6, iclass 4, count 0 2006.257.23:59:09.53#ibcon#read 6, iclass 4, count 0 2006.257.23:59:09.53#ibcon#end of sib2, iclass 4, count 0 2006.257.23:59:09.53#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:59:09.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:59:09.53#ibcon#[26=FRQ=04,624.99\r\n] 2006.257.23:59:09.53#ibcon#*before write, iclass 4, count 0 2006.257.23:59:09.53#ibcon#enter sib2, iclass 4, count 0 2006.257.23:59:09.53#ibcon#flushed, iclass 4, count 0 2006.257.23:59:09.53#ibcon#about to write, iclass 4, count 0 2006.257.23:59:09.53#ibcon#wrote, iclass 4, count 0 2006.257.23:59:09.53#ibcon#about to read 3, iclass 4, count 0 2006.257.23:59:09.57#ibcon#read 3, iclass 4, count 0 2006.257.23:59:09.57#ibcon#about to read 4, iclass 4, count 0 2006.257.23:59:09.57#ibcon#read 4, iclass 4, count 0 2006.257.23:59:09.57#ibcon#about to read 5, iclass 4, count 0 2006.257.23:59:09.57#ibcon#read 5, iclass 4, count 0 2006.257.23:59:09.57#ibcon#about to read 6, iclass 4, count 0 2006.257.23:59:09.57#ibcon#read 6, iclass 4, count 0 2006.257.23:59:09.57#ibcon#end of sib2, iclass 4, count 0 2006.257.23:59:09.57#ibcon#*after write, iclass 4, count 0 2006.257.23:59:09.57#ibcon#*before return 0, iclass 4, count 0 2006.257.23:59:09.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:09.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:09.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:59:09.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:59:09.57$vck44/va=4,7 2006.257.23:59:09.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.23:59:09.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.23:59:09.57#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:09.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:09.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:09.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:09.63#ibcon#enter wrdev, iclass 6, count 2 2006.257.23:59:09.63#ibcon#first serial, iclass 6, count 2 2006.257.23:59:09.63#ibcon#enter sib2, iclass 6, count 2 2006.257.23:59:09.63#ibcon#flushed, iclass 6, count 2 2006.257.23:59:09.63#ibcon#about to write, iclass 6, count 2 2006.257.23:59:09.63#ibcon#wrote, iclass 6, count 2 2006.257.23:59:09.63#ibcon#about to read 3, iclass 6, count 2 2006.257.23:59:09.65#ibcon#read 3, iclass 6, count 2 2006.257.23:59:09.65#ibcon#about to read 4, iclass 6, count 2 2006.257.23:59:09.65#ibcon#read 4, iclass 6, count 2 2006.257.23:59:09.65#ibcon#about to read 5, iclass 6, count 2 2006.257.23:59:09.65#ibcon#read 5, iclass 6, count 2 2006.257.23:59:09.65#ibcon#about to read 6, iclass 6, count 2 2006.257.23:59:09.65#ibcon#read 6, iclass 6, count 2 2006.257.23:59:09.65#ibcon#end of sib2, iclass 6, count 2 2006.257.23:59:09.65#ibcon#*mode == 0, iclass 6, count 2 2006.257.23:59:09.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.23:59:09.65#ibcon#[25=AT04-07\r\n] 2006.257.23:59:09.65#ibcon#*before write, iclass 6, count 2 2006.257.23:59:09.65#ibcon#enter sib2, iclass 6, count 2 2006.257.23:59:09.65#ibcon#flushed, iclass 6, count 2 2006.257.23:59:09.65#ibcon#about to write, iclass 6, count 2 2006.257.23:59:09.65#ibcon#wrote, iclass 6, count 2 2006.257.23:59:09.65#ibcon#about to read 3, iclass 6, count 2 2006.257.23:59:09.68#ibcon#read 3, iclass 6, count 2 2006.257.23:59:09.68#ibcon#about to read 4, iclass 6, count 2 2006.257.23:59:09.68#ibcon#read 4, iclass 6, count 2 2006.257.23:59:09.68#ibcon#about to read 5, iclass 6, count 2 2006.257.23:59:09.68#ibcon#read 5, iclass 6, count 2 2006.257.23:59:09.68#ibcon#about to read 6, iclass 6, count 2 2006.257.23:59:09.68#ibcon#read 6, iclass 6, count 2 2006.257.23:59:09.68#ibcon#end of sib2, iclass 6, count 2 2006.257.23:59:09.68#ibcon#*after write, iclass 6, count 2 2006.257.23:59:09.68#ibcon#*before return 0, iclass 6, count 2 2006.257.23:59:09.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:09.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:09.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.23:59:09.68#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:09.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:09.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:09.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:09.80#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:59:09.80#ibcon#first serial, iclass 6, count 0 2006.257.23:59:09.80#ibcon#enter sib2, iclass 6, count 0 2006.257.23:59:09.80#ibcon#flushed, iclass 6, count 0 2006.257.23:59:09.80#ibcon#about to write, iclass 6, count 0 2006.257.23:59:09.80#ibcon#wrote, iclass 6, count 0 2006.257.23:59:09.80#ibcon#about to read 3, iclass 6, count 0 2006.257.23:59:09.82#ibcon#read 3, iclass 6, count 0 2006.257.23:59:09.82#ibcon#about to read 4, iclass 6, count 0 2006.257.23:59:09.82#ibcon#read 4, iclass 6, count 0 2006.257.23:59:09.82#ibcon#about to read 5, iclass 6, count 0 2006.257.23:59:09.82#ibcon#read 5, iclass 6, count 0 2006.257.23:59:09.82#ibcon#about to read 6, iclass 6, count 0 2006.257.23:59:09.82#ibcon#read 6, iclass 6, count 0 2006.257.23:59:09.82#ibcon#end of sib2, iclass 6, count 0 2006.257.23:59:09.82#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:59:09.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:59:09.82#ibcon#[25=USB\r\n] 2006.257.23:59:09.82#ibcon#*before write, iclass 6, count 0 2006.257.23:59:09.82#ibcon#enter sib2, iclass 6, count 0 2006.257.23:59:09.82#ibcon#flushed, iclass 6, count 0 2006.257.23:59:09.82#ibcon#about to write, iclass 6, count 0 2006.257.23:59:09.82#ibcon#wrote, iclass 6, count 0 2006.257.23:59:09.82#ibcon#about to read 3, iclass 6, count 0 2006.257.23:59:09.85#ibcon#read 3, iclass 6, count 0 2006.257.23:59:09.85#ibcon#about to read 4, iclass 6, count 0 2006.257.23:59:09.85#ibcon#read 4, iclass 6, count 0 2006.257.23:59:09.85#ibcon#about to read 5, iclass 6, count 0 2006.257.23:59:09.85#ibcon#read 5, iclass 6, count 0 2006.257.23:59:09.85#ibcon#about to read 6, iclass 6, count 0 2006.257.23:59:09.85#ibcon#read 6, iclass 6, count 0 2006.257.23:59:09.85#ibcon#end of sib2, iclass 6, count 0 2006.257.23:59:09.85#ibcon#*after write, iclass 6, count 0 2006.257.23:59:09.85#ibcon#*before return 0, iclass 6, count 0 2006.257.23:59:09.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:09.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:09.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:59:09.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:59:09.85$vck44/valo=5,734.99 2006.257.23:59:09.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.23:59:09.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.23:59:09.85#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:09.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:09.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:09.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:09.85#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:59:09.85#ibcon#first serial, iclass 10, count 0 2006.257.23:59:09.85#ibcon#enter sib2, iclass 10, count 0 2006.257.23:59:09.85#ibcon#flushed, iclass 10, count 0 2006.257.23:59:09.85#ibcon#about to write, iclass 10, count 0 2006.257.23:59:09.85#ibcon#wrote, iclass 10, count 0 2006.257.23:59:09.85#ibcon#about to read 3, iclass 10, count 0 2006.257.23:59:09.87#ibcon#read 3, iclass 10, count 0 2006.257.23:59:09.87#ibcon#about to read 4, iclass 10, count 0 2006.257.23:59:09.87#ibcon#read 4, iclass 10, count 0 2006.257.23:59:09.87#ibcon#about to read 5, iclass 10, count 0 2006.257.23:59:09.87#ibcon#read 5, iclass 10, count 0 2006.257.23:59:09.87#ibcon#about to read 6, iclass 10, count 0 2006.257.23:59:09.87#ibcon#read 6, iclass 10, count 0 2006.257.23:59:09.87#ibcon#end of sib2, iclass 10, count 0 2006.257.23:59:09.87#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:59:09.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:59:09.87#ibcon#[26=FRQ=05,734.99\r\n] 2006.257.23:59:09.87#ibcon#*before write, iclass 10, count 0 2006.257.23:59:09.87#ibcon#enter sib2, iclass 10, count 0 2006.257.23:59:09.87#ibcon#flushed, iclass 10, count 0 2006.257.23:59:09.87#ibcon#about to write, iclass 10, count 0 2006.257.23:59:09.87#ibcon#wrote, iclass 10, count 0 2006.257.23:59:09.87#ibcon#about to read 3, iclass 10, count 0 2006.257.23:59:09.91#ibcon#read 3, iclass 10, count 0 2006.257.23:59:09.91#ibcon#about to read 4, iclass 10, count 0 2006.257.23:59:09.91#ibcon#read 4, iclass 10, count 0 2006.257.23:59:09.91#ibcon#about to read 5, iclass 10, count 0 2006.257.23:59:09.91#ibcon#read 5, iclass 10, count 0 2006.257.23:59:09.91#ibcon#about to read 6, iclass 10, count 0 2006.257.23:59:09.91#ibcon#read 6, iclass 10, count 0 2006.257.23:59:09.91#ibcon#end of sib2, iclass 10, count 0 2006.257.23:59:09.91#ibcon#*after write, iclass 10, count 0 2006.257.23:59:09.91#ibcon#*before return 0, iclass 10, count 0 2006.257.23:59:09.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:09.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:09.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:59:09.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:59:09.91$vck44/va=5,4 2006.257.23:59:09.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.23:59:09.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.23:59:09.91#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:09.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:09.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:09.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:09.97#ibcon#enter wrdev, iclass 12, count 2 2006.257.23:59:09.97#ibcon#first serial, iclass 12, count 2 2006.257.23:59:09.97#ibcon#enter sib2, iclass 12, count 2 2006.257.23:59:09.97#ibcon#flushed, iclass 12, count 2 2006.257.23:59:09.97#ibcon#about to write, iclass 12, count 2 2006.257.23:59:09.97#ibcon#wrote, iclass 12, count 2 2006.257.23:59:09.97#ibcon#about to read 3, iclass 12, count 2 2006.257.23:59:09.99#ibcon#read 3, iclass 12, count 2 2006.257.23:59:09.99#ibcon#about to read 4, iclass 12, count 2 2006.257.23:59:09.99#ibcon#read 4, iclass 12, count 2 2006.257.23:59:09.99#ibcon#about to read 5, iclass 12, count 2 2006.257.23:59:09.99#ibcon#read 5, iclass 12, count 2 2006.257.23:59:09.99#ibcon#about to read 6, iclass 12, count 2 2006.257.23:59:09.99#ibcon#read 6, iclass 12, count 2 2006.257.23:59:09.99#ibcon#end of sib2, iclass 12, count 2 2006.257.23:59:09.99#ibcon#*mode == 0, iclass 12, count 2 2006.257.23:59:09.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.23:59:09.99#ibcon#[25=AT05-04\r\n] 2006.257.23:59:09.99#ibcon#*before write, iclass 12, count 2 2006.257.23:59:09.99#ibcon#enter sib2, iclass 12, count 2 2006.257.23:59:09.99#ibcon#flushed, iclass 12, count 2 2006.257.23:59:09.99#ibcon#about to write, iclass 12, count 2 2006.257.23:59:09.99#ibcon#wrote, iclass 12, count 2 2006.257.23:59:09.99#ibcon#about to read 3, iclass 12, count 2 2006.257.23:59:10.02#ibcon#read 3, iclass 12, count 2 2006.257.23:59:10.02#ibcon#about to read 4, iclass 12, count 2 2006.257.23:59:10.02#ibcon#read 4, iclass 12, count 2 2006.257.23:59:10.02#ibcon#about to read 5, iclass 12, count 2 2006.257.23:59:10.02#ibcon#read 5, iclass 12, count 2 2006.257.23:59:10.02#ibcon#about to read 6, iclass 12, count 2 2006.257.23:59:10.02#ibcon#read 6, iclass 12, count 2 2006.257.23:59:10.02#ibcon#end of sib2, iclass 12, count 2 2006.257.23:59:10.02#ibcon#*after write, iclass 12, count 2 2006.257.23:59:10.02#ibcon#*before return 0, iclass 12, count 2 2006.257.23:59:10.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:10.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:10.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.23:59:10.02#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:10.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:10.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:10.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:10.14#ibcon#enter wrdev, iclass 12, count 0 2006.257.23:59:10.14#ibcon#first serial, iclass 12, count 0 2006.257.23:59:10.14#ibcon#enter sib2, iclass 12, count 0 2006.257.23:59:10.14#ibcon#flushed, iclass 12, count 0 2006.257.23:59:10.14#ibcon#about to write, iclass 12, count 0 2006.257.23:59:10.14#ibcon#wrote, iclass 12, count 0 2006.257.23:59:10.14#ibcon#about to read 3, iclass 12, count 0 2006.257.23:59:10.16#ibcon#read 3, iclass 12, count 0 2006.257.23:59:10.16#ibcon#about to read 4, iclass 12, count 0 2006.257.23:59:10.16#ibcon#read 4, iclass 12, count 0 2006.257.23:59:10.16#ibcon#about to read 5, iclass 12, count 0 2006.257.23:59:10.16#ibcon#read 5, iclass 12, count 0 2006.257.23:59:10.16#ibcon#about to read 6, iclass 12, count 0 2006.257.23:59:10.16#ibcon#read 6, iclass 12, count 0 2006.257.23:59:10.16#ibcon#end of sib2, iclass 12, count 0 2006.257.23:59:10.16#ibcon#*mode == 0, iclass 12, count 0 2006.257.23:59:10.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.23:59:10.16#ibcon#[25=USB\r\n] 2006.257.23:59:10.16#ibcon#*before write, iclass 12, count 0 2006.257.23:59:10.16#ibcon#enter sib2, iclass 12, count 0 2006.257.23:59:10.16#ibcon#flushed, iclass 12, count 0 2006.257.23:59:10.16#ibcon#about to write, iclass 12, count 0 2006.257.23:59:10.16#ibcon#wrote, iclass 12, count 0 2006.257.23:59:10.16#ibcon#about to read 3, iclass 12, count 0 2006.257.23:59:10.19#ibcon#read 3, iclass 12, count 0 2006.257.23:59:10.19#ibcon#about to read 4, iclass 12, count 0 2006.257.23:59:10.19#ibcon#read 4, iclass 12, count 0 2006.257.23:59:10.19#ibcon#about to read 5, iclass 12, count 0 2006.257.23:59:10.19#ibcon#read 5, iclass 12, count 0 2006.257.23:59:10.19#ibcon#about to read 6, iclass 12, count 0 2006.257.23:59:10.19#ibcon#read 6, iclass 12, count 0 2006.257.23:59:10.19#ibcon#end of sib2, iclass 12, count 0 2006.257.23:59:10.19#ibcon#*after write, iclass 12, count 0 2006.257.23:59:10.19#ibcon#*before return 0, iclass 12, count 0 2006.257.23:59:10.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:10.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:10.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.23:59:10.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.23:59:10.19$vck44/valo=6,814.99 2006.257.23:59:10.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.23:59:10.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.23:59:10.19#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:10.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:10.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:10.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:10.19#ibcon#enter wrdev, iclass 14, count 0 2006.257.23:59:10.19#ibcon#first serial, iclass 14, count 0 2006.257.23:59:10.19#ibcon#enter sib2, iclass 14, count 0 2006.257.23:59:10.19#ibcon#flushed, iclass 14, count 0 2006.257.23:59:10.19#ibcon#about to write, iclass 14, count 0 2006.257.23:59:10.19#ibcon#wrote, iclass 14, count 0 2006.257.23:59:10.19#ibcon#about to read 3, iclass 14, count 0 2006.257.23:59:10.21#ibcon#read 3, iclass 14, count 0 2006.257.23:59:10.21#ibcon#about to read 4, iclass 14, count 0 2006.257.23:59:10.21#ibcon#read 4, iclass 14, count 0 2006.257.23:59:10.21#ibcon#about to read 5, iclass 14, count 0 2006.257.23:59:10.21#ibcon#read 5, iclass 14, count 0 2006.257.23:59:10.21#ibcon#about to read 6, iclass 14, count 0 2006.257.23:59:10.21#ibcon#read 6, iclass 14, count 0 2006.257.23:59:10.21#ibcon#end of sib2, iclass 14, count 0 2006.257.23:59:10.21#ibcon#*mode == 0, iclass 14, count 0 2006.257.23:59:10.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.23:59:10.21#ibcon#[26=FRQ=06,814.99\r\n] 2006.257.23:59:10.21#ibcon#*before write, iclass 14, count 0 2006.257.23:59:10.21#ibcon#enter sib2, iclass 14, count 0 2006.257.23:59:10.21#ibcon#flushed, iclass 14, count 0 2006.257.23:59:10.21#ibcon#about to write, iclass 14, count 0 2006.257.23:59:10.21#ibcon#wrote, iclass 14, count 0 2006.257.23:59:10.21#ibcon#about to read 3, iclass 14, count 0 2006.257.23:59:10.25#ibcon#read 3, iclass 14, count 0 2006.257.23:59:10.25#ibcon#about to read 4, iclass 14, count 0 2006.257.23:59:10.25#ibcon#read 4, iclass 14, count 0 2006.257.23:59:10.25#ibcon#about to read 5, iclass 14, count 0 2006.257.23:59:10.25#ibcon#read 5, iclass 14, count 0 2006.257.23:59:10.25#ibcon#about to read 6, iclass 14, count 0 2006.257.23:59:10.25#ibcon#read 6, iclass 14, count 0 2006.257.23:59:10.25#ibcon#end of sib2, iclass 14, count 0 2006.257.23:59:10.25#ibcon#*after write, iclass 14, count 0 2006.257.23:59:10.25#ibcon#*before return 0, iclass 14, count 0 2006.257.23:59:10.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:10.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:10.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.23:59:10.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.23:59:10.25$vck44/va=6,4 2006.257.23:59:10.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.23:59:10.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.23:59:10.25#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:10.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:10.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:10.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:10.31#ibcon#enter wrdev, iclass 16, count 2 2006.257.23:59:10.31#ibcon#first serial, iclass 16, count 2 2006.257.23:59:10.31#ibcon#enter sib2, iclass 16, count 2 2006.257.23:59:10.31#ibcon#flushed, iclass 16, count 2 2006.257.23:59:10.31#ibcon#about to write, iclass 16, count 2 2006.257.23:59:10.31#ibcon#wrote, iclass 16, count 2 2006.257.23:59:10.31#ibcon#about to read 3, iclass 16, count 2 2006.257.23:59:10.33#ibcon#read 3, iclass 16, count 2 2006.257.23:59:10.33#ibcon#about to read 4, iclass 16, count 2 2006.257.23:59:10.33#ibcon#read 4, iclass 16, count 2 2006.257.23:59:10.33#ibcon#about to read 5, iclass 16, count 2 2006.257.23:59:10.33#ibcon#read 5, iclass 16, count 2 2006.257.23:59:10.33#ibcon#about to read 6, iclass 16, count 2 2006.257.23:59:10.33#ibcon#read 6, iclass 16, count 2 2006.257.23:59:10.33#ibcon#end of sib2, iclass 16, count 2 2006.257.23:59:10.33#ibcon#*mode == 0, iclass 16, count 2 2006.257.23:59:10.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.23:59:10.33#ibcon#[25=AT06-04\r\n] 2006.257.23:59:10.33#ibcon#*before write, iclass 16, count 2 2006.257.23:59:10.33#ibcon#enter sib2, iclass 16, count 2 2006.257.23:59:10.33#ibcon#flushed, iclass 16, count 2 2006.257.23:59:10.33#ibcon#about to write, iclass 16, count 2 2006.257.23:59:10.33#ibcon#wrote, iclass 16, count 2 2006.257.23:59:10.33#ibcon#about to read 3, iclass 16, count 2 2006.257.23:59:10.36#ibcon#read 3, iclass 16, count 2 2006.257.23:59:10.36#ibcon#about to read 4, iclass 16, count 2 2006.257.23:59:10.36#ibcon#read 4, iclass 16, count 2 2006.257.23:59:10.36#ibcon#about to read 5, iclass 16, count 2 2006.257.23:59:10.36#ibcon#read 5, iclass 16, count 2 2006.257.23:59:10.36#ibcon#about to read 6, iclass 16, count 2 2006.257.23:59:10.36#ibcon#read 6, iclass 16, count 2 2006.257.23:59:10.36#ibcon#end of sib2, iclass 16, count 2 2006.257.23:59:10.36#ibcon#*after write, iclass 16, count 2 2006.257.23:59:10.36#ibcon#*before return 0, iclass 16, count 2 2006.257.23:59:10.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:10.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:10.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.23:59:10.36#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:10.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:10.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:10.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:10.48#ibcon#enter wrdev, iclass 16, count 0 2006.257.23:59:10.48#ibcon#first serial, iclass 16, count 0 2006.257.23:59:10.48#ibcon#enter sib2, iclass 16, count 0 2006.257.23:59:10.48#ibcon#flushed, iclass 16, count 0 2006.257.23:59:10.48#ibcon#about to write, iclass 16, count 0 2006.257.23:59:10.48#ibcon#wrote, iclass 16, count 0 2006.257.23:59:10.48#ibcon#about to read 3, iclass 16, count 0 2006.257.23:59:10.50#ibcon#read 3, iclass 16, count 0 2006.257.23:59:10.50#ibcon#about to read 4, iclass 16, count 0 2006.257.23:59:10.50#ibcon#read 4, iclass 16, count 0 2006.257.23:59:10.50#ibcon#about to read 5, iclass 16, count 0 2006.257.23:59:10.50#ibcon#read 5, iclass 16, count 0 2006.257.23:59:10.50#ibcon#about to read 6, iclass 16, count 0 2006.257.23:59:10.50#ibcon#read 6, iclass 16, count 0 2006.257.23:59:10.50#ibcon#end of sib2, iclass 16, count 0 2006.257.23:59:10.50#ibcon#*mode == 0, iclass 16, count 0 2006.257.23:59:10.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.23:59:10.50#ibcon#[25=USB\r\n] 2006.257.23:59:10.50#ibcon#*before write, iclass 16, count 0 2006.257.23:59:10.50#ibcon#enter sib2, iclass 16, count 0 2006.257.23:59:10.50#ibcon#flushed, iclass 16, count 0 2006.257.23:59:10.50#ibcon#about to write, iclass 16, count 0 2006.257.23:59:10.50#ibcon#wrote, iclass 16, count 0 2006.257.23:59:10.50#ibcon#about to read 3, iclass 16, count 0 2006.257.23:59:10.53#ibcon#read 3, iclass 16, count 0 2006.257.23:59:10.53#ibcon#about to read 4, iclass 16, count 0 2006.257.23:59:10.53#ibcon#read 4, iclass 16, count 0 2006.257.23:59:10.53#ibcon#about to read 5, iclass 16, count 0 2006.257.23:59:10.53#ibcon#read 5, iclass 16, count 0 2006.257.23:59:10.53#ibcon#about to read 6, iclass 16, count 0 2006.257.23:59:10.53#ibcon#read 6, iclass 16, count 0 2006.257.23:59:10.53#ibcon#end of sib2, iclass 16, count 0 2006.257.23:59:10.53#ibcon#*after write, iclass 16, count 0 2006.257.23:59:10.53#ibcon#*before return 0, iclass 16, count 0 2006.257.23:59:10.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:10.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:10.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.23:59:10.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.23:59:10.53$vck44/valo=7,864.99 2006.257.23:59:10.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.23:59:10.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.23:59:10.53#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:10.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:10.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:10.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:10.53#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:59:10.53#ibcon#first serial, iclass 18, count 0 2006.257.23:59:10.53#ibcon#enter sib2, iclass 18, count 0 2006.257.23:59:10.53#ibcon#flushed, iclass 18, count 0 2006.257.23:59:10.53#ibcon#about to write, iclass 18, count 0 2006.257.23:59:10.53#ibcon#wrote, iclass 18, count 0 2006.257.23:59:10.53#ibcon#about to read 3, iclass 18, count 0 2006.257.23:59:10.55#ibcon#read 3, iclass 18, count 0 2006.257.23:59:10.55#ibcon#about to read 4, iclass 18, count 0 2006.257.23:59:10.55#ibcon#read 4, iclass 18, count 0 2006.257.23:59:10.55#ibcon#about to read 5, iclass 18, count 0 2006.257.23:59:10.55#ibcon#read 5, iclass 18, count 0 2006.257.23:59:10.55#ibcon#about to read 6, iclass 18, count 0 2006.257.23:59:10.55#ibcon#read 6, iclass 18, count 0 2006.257.23:59:10.55#ibcon#end of sib2, iclass 18, count 0 2006.257.23:59:10.55#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:59:10.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:59:10.55#ibcon#[26=FRQ=07,864.99\r\n] 2006.257.23:59:10.55#ibcon#*before write, iclass 18, count 0 2006.257.23:59:10.55#ibcon#enter sib2, iclass 18, count 0 2006.257.23:59:10.55#ibcon#flushed, iclass 18, count 0 2006.257.23:59:10.55#ibcon#about to write, iclass 18, count 0 2006.257.23:59:10.55#ibcon#wrote, iclass 18, count 0 2006.257.23:59:10.55#ibcon#about to read 3, iclass 18, count 0 2006.257.23:59:10.59#ibcon#read 3, iclass 18, count 0 2006.257.23:59:10.59#ibcon#about to read 4, iclass 18, count 0 2006.257.23:59:10.59#ibcon#read 4, iclass 18, count 0 2006.257.23:59:10.59#ibcon#about to read 5, iclass 18, count 0 2006.257.23:59:10.59#ibcon#read 5, iclass 18, count 0 2006.257.23:59:10.59#ibcon#about to read 6, iclass 18, count 0 2006.257.23:59:10.59#ibcon#read 6, iclass 18, count 0 2006.257.23:59:10.59#ibcon#end of sib2, iclass 18, count 0 2006.257.23:59:10.59#ibcon#*after write, iclass 18, count 0 2006.257.23:59:10.59#ibcon#*before return 0, iclass 18, count 0 2006.257.23:59:10.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:10.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:10.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:59:10.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:59:10.59$vck44/va=7,4 2006.257.23:59:10.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.23:59:10.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.23:59:10.59#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:10.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:10.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:10.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:10.65#ibcon#enter wrdev, iclass 20, count 2 2006.257.23:59:10.65#ibcon#first serial, iclass 20, count 2 2006.257.23:59:10.65#ibcon#enter sib2, iclass 20, count 2 2006.257.23:59:10.65#ibcon#flushed, iclass 20, count 2 2006.257.23:59:10.65#ibcon#about to write, iclass 20, count 2 2006.257.23:59:10.65#ibcon#wrote, iclass 20, count 2 2006.257.23:59:10.65#ibcon#about to read 3, iclass 20, count 2 2006.257.23:59:10.67#ibcon#read 3, iclass 20, count 2 2006.257.23:59:10.67#ibcon#about to read 4, iclass 20, count 2 2006.257.23:59:10.67#ibcon#read 4, iclass 20, count 2 2006.257.23:59:10.67#ibcon#about to read 5, iclass 20, count 2 2006.257.23:59:10.67#ibcon#read 5, iclass 20, count 2 2006.257.23:59:10.67#ibcon#about to read 6, iclass 20, count 2 2006.257.23:59:10.67#ibcon#read 6, iclass 20, count 2 2006.257.23:59:10.67#ibcon#end of sib2, iclass 20, count 2 2006.257.23:59:10.67#ibcon#*mode == 0, iclass 20, count 2 2006.257.23:59:10.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.23:59:10.67#ibcon#[25=AT07-04\r\n] 2006.257.23:59:10.67#ibcon#*before write, iclass 20, count 2 2006.257.23:59:10.67#ibcon#enter sib2, iclass 20, count 2 2006.257.23:59:10.67#ibcon#flushed, iclass 20, count 2 2006.257.23:59:10.67#ibcon#about to write, iclass 20, count 2 2006.257.23:59:10.67#ibcon#wrote, iclass 20, count 2 2006.257.23:59:10.67#ibcon#about to read 3, iclass 20, count 2 2006.257.23:59:10.70#ibcon#read 3, iclass 20, count 2 2006.257.23:59:10.70#ibcon#about to read 4, iclass 20, count 2 2006.257.23:59:10.70#ibcon#read 4, iclass 20, count 2 2006.257.23:59:10.70#ibcon#about to read 5, iclass 20, count 2 2006.257.23:59:10.70#ibcon#read 5, iclass 20, count 2 2006.257.23:59:10.70#ibcon#about to read 6, iclass 20, count 2 2006.257.23:59:10.70#ibcon#read 6, iclass 20, count 2 2006.257.23:59:10.70#ibcon#end of sib2, iclass 20, count 2 2006.257.23:59:10.70#ibcon#*after write, iclass 20, count 2 2006.257.23:59:10.70#ibcon#*before return 0, iclass 20, count 2 2006.257.23:59:10.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:10.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:10.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.23:59:10.70#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:10.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:10.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:10.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:10.82#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:59:10.82#ibcon#first serial, iclass 20, count 0 2006.257.23:59:10.82#ibcon#enter sib2, iclass 20, count 0 2006.257.23:59:10.82#ibcon#flushed, iclass 20, count 0 2006.257.23:59:10.82#ibcon#about to write, iclass 20, count 0 2006.257.23:59:10.82#ibcon#wrote, iclass 20, count 0 2006.257.23:59:10.82#ibcon#about to read 3, iclass 20, count 0 2006.257.23:59:10.84#ibcon#read 3, iclass 20, count 0 2006.257.23:59:10.84#ibcon#about to read 4, iclass 20, count 0 2006.257.23:59:10.84#ibcon#read 4, iclass 20, count 0 2006.257.23:59:10.84#ibcon#about to read 5, iclass 20, count 0 2006.257.23:59:10.84#ibcon#read 5, iclass 20, count 0 2006.257.23:59:10.84#ibcon#about to read 6, iclass 20, count 0 2006.257.23:59:10.84#ibcon#read 6, iclass 20, count 0 2006.257.23:59:10.84#ibcon#end of sib2, iclass 20, count 0 2006.257.23:59:10.84#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:59:10.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:59:10.84#ibcon#[25=USB\r\n] 2006.257.23:59:10.84#ibcon#*before write, iclass 20, count 0 2006.257.23:59:10.84#ibcon#enter sib2, iclass 20, count 0 2006.257.23:59:10.84#ibcon#flushed, iclass 20, count 0 2006.257.23:59:10.84#ibcon#about to write, iclass 20, count 0 2006.257.23:59:10.84#ibcon#wrote, iclass 20, count 0 2006.257.23:59:10.84#ibcon#about to read 3, iclass 20, count 0 2006.257.23:59:10.87#ibcon#read 3, iclass 20, count 0 2006.257.23:59:10.87#ibcon#about to read 4, iclass 20, count 0 2006.257.23:59:10.87#ibcon#read 4, iclass 20, count 0 2006.257.23:59:10.87#ibcon#about to read 5, iclass 20, count 0 2006.257.23:59:10.87#ibcon#read 5, iclass 20, count 0 2006.257.23:59:10.87#ibcon#about to read 6, iclass 20, count 0 2006.257.23:59:10.87#ibcon#read 6, iclass 20, count 0 2006.257.23:59:10.87#ibcon#end of sib2, iclass 20, count 0 2006.257.23:59:10.87#ibcon#*after write, iclass 20, count 0 2006.257.23:59:10.87#ibcon#*before return 0, iclass 20, count 0 2006.257.23:59:10.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:10.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:10.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:59:10.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:59:10.87$vck44/valo=8,884.99 2006.257.23:59:10.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.23:59:10.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.23:59:10.87#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:10.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:10.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:10.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:10.87#ibcon#enter wrdev, iclass 22, count 0 2006.257.23:59:10.87#ibcon#first serial, iclass 22, count 0 2006.257.23:59:10.87#ibcon#enter sib2, iclass 22, count 0 2006.257.23:59:10.87#ibcon#flushed, iclass 22, count 0 2006.257.23:59:10.87#ibcon#about to write, iclass 22, count 0 2006.257.23:59:10.87#ibcon#wrote, iclass 22, count 0 2006.257.23:59:10.87#ibcon#about to read 3, iclass 22, count 0 2006.257.23:59:10.89#ibcon#read 3, iclass 22, count 0 2006.257.23:59:10.89#ibcon#about to read 4, iclass 22, count 0 2006.257.23:59:10.89#ibcon#read 4, iclass 22, count 0 2006.257.23:59:10.89#ibcon#about to read 5, iclass 22, count 0 2006.257.23:59:10.89#ibcon#read 5, iclass 22, count 0 2006.257.23:59:10.89#ibcon#about to read 6, iclass 22, count 0 2006.257.23:59:10.89#ibcon#read 6, iclass 22, count 0 2006.257.23:59:10.89#ibcon#end of sib2, iclass 22, count 0 2006.257.23:59:10.89#ibcon#*mode == 0, iclass 22, count 0 2006.257.23:59:10.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.23:59:10.89#ibcon#[26=FRQ=08,884.99\r\n] 2006.257.23:59:10.89#ibcon#*before write, iclass 22, count 0 2006.257.23:59:10.89#ibcon#enter sib2, iclass 22, count 0 2006.257.23:59:10.89#ibcon#flushed, iclass 22, count 0 2006.257.23:59:10.89#ibcon#about to write, iclass 22, count 0 2006.257.23:59:10.89#ibcon#wrote, iclass 22, count 0 2006.257.23:59:10.89#ibcon#about to read 3, iclass 22, count 0 2006.257.23:59:10.93#ibcon#read 3, iclass 22, count 0 2006.257.23:59:10.93#ibcon#about to read 4, iclass 22, count 0 2006.257.23:59:10.93#ibcon#read 4, iclass 22, count 0 2006.257.23:59:10.93#ibcon#about to read 5, iclass 22, count 0 2006.257.23:59:10.93#ibcon#read 5, iclass 22, count 0 2006.257.23:59:10.93#ibcon#about to read 6, iclass 22, count 0 2006.257.23:59:10.93#ibcon#read 6, iclass 22, count 0 2006.257.23:59:10.93#ibcon#end of sib2, iclass 22, count 0 2006.257.23:59:10.93#ibcon#*after write, iclass 22, count 0 2006.257.23:59:10.93#ibcon#*before return 0, iclass 22, count 0 2006.257.23:59:10.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:10.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:10.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.23:59:10.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.23:59:10.93$vck44/va=8,4 2006.257.23:59:10.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.257.23:59:10.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.257.23:59:10.93#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:10.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:59:10.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:59:10.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:59:10.99#ibcon#enter wrdev, iclass 24, count 2 2006.257.23:59:10.99#ibcon#first serial, iclass 24, count 2 2006.257.23:59:10.99#ibcon#enter sib2, iclass 24, count 2 2006.257.23:59:10.99#ibcon#flushed, iclass 24, count 2 2006.257.23:59:10.99#ibcon#about to write, iclass 24, count 2 2006.257.23:59:10.99#ibcon#wrote, iclass 24, count 2 2006.257.23:59:10.99#ibcon#about to read 3, iclass 24, count 2 2006.257.23:59:11.01#ibcon#read 3, iclass 24, count 2 2006.257.23:59:11.01#ibcon#about to read 4, iclass 24, count 2 2006.257.23:59:11.01#ibcon#read 4, iclass 24, count 2 2006.257.23:59:11.01#ibcon#about to read 5, iclass 24, count 2 2006.257.23:59:11.01#ibcon#read 5, iclass 24, count 2 2006.257.23:59:11.01#ibcon#about to read 6, iclass 24, count 2 2006.257.23:59:11.01#ibcon#read 6, iclass 24, count 2 2006.257.23:59:11.01#ibcon#end of sib2, iclass 24, count 2 2006.257.23:59:11.01#ibcon#*mode == 0, iclass 24, count 2 2006.257.23:59:11.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.257.23:59:11.01#ibcon#[25=AT08-04\r\n] 2006.257.23:59:11.01#ibcon#*before write, iclass 24, count 2 2006.257.23:59:11.01#ibcon#enter sib2, iclass 24, count 2 2006.257.23:59:11.01#ibcon#flushed, iclass 24, count 2 2006.257.23:59:11.01#ibcon#about to write, iclass 24, count 2 2006.257.23:59:11.01#ibcon#wrote, iclass 24, count 2 2006.257.23:59:11.01#ibcon#about to read 3, iclass 24, count 2 2006.257.23:59:11.04#ibcon#read 3, iclass 24, count 2 2006.257.23:59:11.04#ibcon#about to read 4, iclass 24, count 2 2006.257.23:59:11.04#ibcon#read 4, iclass 24, count 2 2006.257.23:59:11.04#ibcon#about to read 5, iclass 24, count 2 2006.257.23:59:11.04#ibcon#read 5, iclass 24, count 2 2006.257.23:59:11.04#ibcon#about to read 6, iclass 24, count 2 2006.257.23:59:11.04#ibcon#read 6, iclass 24, count 2 2006.257.23:59:11.04#ibcon#end of sib2, iclass 24, count 2 2006.257.23:59:11.04#ibcon#*after write, iclass 24, count 2 2006.257.23:59:11.04#ibcon#*before return 0, iclass 24, count 2 2006.257.23:59:11.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:59:11.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.257.23:59:11.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.257.23:59:11.04#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:11.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:59:11.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:59:11.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:59:11.16#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:59:11.16#ibcon#first serial, iclass 24, count 0 2006.257.23:59:11.16#ibcon#enter sib2, iclass 24, count 0 2006.257.23:59:11.16#ibcon#flushed, iclass 24, count 0 2006.257.23:59:11.16#ibcon#about to write, iclass 24, count 0 2006.257.23:59:11.16#ibcon#wrote, iclass 24, count 0 2006.257.23:59:11.16#ibcon#about to read 3, iclass 24, count 0 2006.257.23:59:11.18#ibcon#read 3, iclass 24, count 0 2006.257.23:59:11.18#ibcon#about to read 4, iclass 24, count 0 2006.257.23:59:11.18#ibcon#read 4, iclass 24, count 0 2006.257.23:59:11.18#ibcon#about to read 5, iclass 24, count 0 2006.257.23:59:11.18#ibcon#read 5, iclass 24, count 0 2006.257.23:59:11.18#ibcon#about to read 6, iclass 24, count 0 2006.257.23:59:11.18#ibcon#read 6, iclass 24, count 0 2006.257.23:59:11.18#ibcon#end of sib2, iclass 24, count 0 2006.257.23:59:11.18#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:59:11.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:59:11.18#ibcon#[25=USB\r\n] 2006.257.23:59:11.18#ibcon#*before write, iclass 24, count 0 2006.257.23:59:11.18#ibcon#enter sib2, iclass 24, count 0 2006.257.23:59:11.18#ibcon#flushed, iclass 24, count 0 2006.257.23:59:11.18#ibcon#about to write, iclass 24, count 0 2006.257.23:59:11.18#ibcon#wrote, iclass 24, count 0 2006.257.23:59:11.18#ibcon#about to read 3, iclass 24, count 0 2006.257.23:59:11.21#ibcon#read 3, iclass 24, count 0 2006.257.23:59:11.21#ibcon#about to read 4, iclass 24, count 0 2006.257.23:59:11.21#ibcon#read 4, iclass 24, count 0 2006.257.23:59:11.21#ibcon#about to read 5, iclass 24, count 0 2006.257.23:59:11.21#ibcon#read 5, iclass 24, count 0 2006.257.23:59:11.21#ibcon#about to read 6, iclass 24, count 0 2006.257.23:59:11.21#ibcon#read 6, iclass 24, count 0 2006.257.23:59:11.21#ibcon#end of sib2, iclass 24, count 0 2006.257.23:59:11.21#ibcon#*after write, iclass 24, count 0 2006.257.23:59:11.21#ibcon#*before return 0, iclass 24, count 0 2006.257.23:59:11.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:59:11.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.257.23:59:11.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:59:11.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:59:11.21$vck44/vblo=1,629.99 2006.257.23:59:11.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.257.23:59:11.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.257.23:59:11.21#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:11.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:59:11.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:59:11.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:59:11.21#ibcon#enter wrdev, iclass 26, count 0 2006.257.23:59:11.21#ibcon#first serial, iclass 26, count 0 2006.257.23:59:11.21#ibcon#enter sib2, iclass 26, count 0 2006.257.23:59:11.21#ibcon#flushed, iclass 26, count 0 2006.257.23:59:11.21#ibcon#about to write, iclass 26, count 0 2006.257.23:59:11.21#ibcon#wrote, iclass 26, count 0 2006.257.23:59:11.21#ibcon#about to read 3, iclass 26, count 0 2006.257.23:59:11.23#ibcon#read 3, iclass 26, count 0 2006.257.23:59:11.23#ibcon#about to read 4, iclass 26, count 0 2006.257.23:59:11.23#ibcon#read 4, iclass 26, count 0 2006.257.23:59:11.23#ibcon#about to read 5, iclass 26, count 0 2006.257.23:59:11.23#ibcon#read 5, iclass 26, count 0 2006.257.23:59:11.23#ibcon#about to read 6, iclass 26, count 0 2006.257.23:59:11.23#ibcon#read 6, iclass 26, count 0 2006.257.23:59:11.23#ibcon#end of sib2, iclass 26, count 0 2006.257.23:59:11.23#ibcon#*mode == 0, iclass 26, count 0 2006.257.23:59:11.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.257.23:59:11.23#ibcon#[28=FRQ=01,629.99\r\n] 2006.257.23:59:11.23#ibcon#*before write, iclass 26, count 0 2006.257.23:59:11.23#ibcon#enter sib2, iclass 26, count 0 2006.257.23:59:11.23#ibcon#flushed, iclass 26, count 0 2006.257.23:59:11.23#ibcon#about to write, iclass 26, count 0 2006.257.23:59:11.23#ibcon#wrote, iclass 26, count 0 2006.257.23:59:11.23#ibcon#about to read 3, iclass 26, count 0 2006.257.23:59:11.27#ibcon#read 3, iclass 26, count 0 2006.257.23:59:11.27#ibcon#about to read 4, iclass 26, count 0 2006.257.23:59:11.27#ibcon#read 4, iclass 26, count 0 2006.257.23:59:11.27#ibcon#about to read 5, iclass 26, count 0 2006.257.23:59:11.27#ibcon#read 5, iclass 26, count 0 2006.257.23:59:11.27#ibcon#about to read 6, iclass 26, count 0 2006.257.23:59:11.27#ibcon#read 6, iclass 26, count 0 2006.257.23:59:11.27#ibcon#end of sib2, iclass 26, count 0 2006.257.23:59:11.27#ibcon#*after write, iclass 26, count 0 2006.257.23:59:11.27#ibcon#*before return 0, iclass 26, count 0 2006.257.23:59:11.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:59:11.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.257.23:59:11.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.257.23:59:11.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.257.23:59:11.27$vck44/vb=1,4 2006.257.23:59:11.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.257.23:59:11.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.257.23:59:11.27#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:11.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:59:11.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:59:11.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:59:11.27#ibcon#enter wrdev, iclass 28, count 2 2006.257.23:59:11.27#ibcon#first serial, iclass 28, count 2 2006.257.23:59:11.27#ibcon#enter sib2, iclass 28, count 2 2006.257.23:59:11.27#ibcon#flushed, iclass 28, count 2 2006.257.23:59:11.27#ibcon#about to write, iclass 28, count 2 2006.257.23:59:11.27#ibcon#wrote, iclass 28, count 2 2006.257.23:59:11.27#ibcon#about to read 3, iclass 28, count 2 2006.257.23:59:11.29#ibcon#read 3, iclass 28, count 2 2006.257.23:59:11.29#ibcon#about to read 4, iclass 28, count 2 2006.257.23:59:11.29#ibcon#read 4, iclass 28, count 2 2006.257.23:59:11.29#ibcon#about to read 5, iclass 28, count 2 2006.257.23:59:11.29#ibcon#read 5, iclass 28, count 2 2006.257.23:59:11.29#ibcon#about to read 6, iclass 28, count 2 2006.257.23:59:11.29#ibcon#read 6, iclass 28, count 2 2006.257.23:59:11.29#ibcon#end of sib2, iclass 28, count 2 2006.257.23:59:11.29#ibcon#*mode == 0, iclass 28, count 2 2006.257.23:59:11.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.257.23:59:11.29#ibcon#[27=AT01-04\r\n] 2006.257.23:59:11.29#ibcon#*before write, iclass 28, count 2 2006.257.23:59:11.29#ibcon#enter sib2, iclass 28, count 2 2006.257.23:59:11.29#ibcon#flushed, iclass 28, count 2 2006.257.23:59:11.29#ibcon#about to write, iclass 28, count 2 2006.257.23:59:11.29#ibcon#wrote, iclass 28, count 2 2006.257.23:59:11.29#ibcon#about to read 3, iclass 28, count 2 2006.257.23:59:11.32#ibcon#read 3, iclass 28, count 2 2006.257.23:59:11.32#ibcon#about to read 4, iclass 28, count 2 2006.257.23:59:11.32#ibcon#read 4, iclass 28, count 2 2006.257.23:59:11.32#ibcon#about to read 5, iclass 28, count 2 2006.257.23:59:11.32#ibcon#read 5, iclass 28, count 2 2006.257.23:59:11.32#ibcon#about to read 6, iclass 28, count 2 2006.257.23:59:11.32#ibcon#read 6, iclass 28, count 2 2006.257.23:59:11.32#ibcon#end of sib2, iclass 28, count 2 2006.257.23:59:11.32#ibcon#*after write, iclass 28, count 2 2006.257.23:59:11.32#ibcon#*before return 0, iclass 28, count 2 2006.257.23:59:11.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:59:11.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.257.23:59:11.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.257.23:59:11.32#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:11.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:59:11.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:59:11.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:59:11.44#ibcon#enter wrdev, iclass 28, count 0 2006.257.23:59:11.44#ibcon#first serial, iclass 28, count 0 2006.257.23:59:11.44#ibcon#enter sib2, iclass 28, count 0 2006.257.23:59:11.44#ibcon#flushed, iclass 28, count 0 2006.257.23:59:11.44#ibcon#about to write, iclass 28, count 0 2006.257.23:59:11.44#ibcon#wrote, iclass 28, count 0 2006.257.23:59:11.44#ibcon#about to read 3, iclass 28, count 0 2006.257.23:59:11.46#ibcon#read 3, iclass 28, count 0 2006.257.23:59:11.46#ibcon#about to read 4, iclass 28, count 0 2006.257.23:59:11.46#ibcon#read 4, iclass 28, count 0 2006.257.23:59:11.46#ibcon#about to read 5, iclass 28, count 0 2006.257.23:59:11.46#ibcon#read 5, iclass 28, count 0 2006.257.23:59:11.46#ibcon#about to read 6, iclass 28, count 0 2006.257.23:59:11.46#ibcon#read 6, iclass 28, count 0 2006.257.23:59:11.46#ibcon#end of sib2, iclass 28, count 0 2006.257.23:59:11.46#ibcon#*mode == 0, iclass 28, count 0 2006.257.23:59:11.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.257.23:59:11.46#ibcon#[27=USB\r\n] 2006.257.23:59:11.46#ibcon#*before write, iclass 28, count 0 2006.257.23:59:11.46#ibcon#enter sib2, iclass 28, count 0 2006.257.23:59:11.46#ibcon#flushed, iclass 28, count 0 2006.257.23:59:11.46#ibcon#about to write, iclass 28, count 0 2006.257.23:59:11.46#ibcon#wrote, iclass 28, count 0 2006.257.23:59:11.46#ibcon#about to read 3, iclass 28, count 0 2006.257.23:59:11.49#ibcon#read 3, iclass 28, count 0 2006.257.23:59:11.49#ibcon#about to read 4, iclass 28, count 0 2006.257.23:59:11.49#ibcon#read 4, iclass 28, count 0 2006.257.23:59:11.49#ibcon#about to read 5, iclass 28, count 0 2006.257.23:59:11.49#ibcon#read 5, iclass 28, count 0 2006.257.23:59:11.49#ibcon#about to read 6, iclass 28, count 0 2006.257.23:59:11.49#ibcon#read 6, iclass 28, count 0 2006.257.23:59:11.49#ibcon#end of sib2, iclass 28, count 0 2006.257.23:59:11.49#ibcon#*after write, iclass 28, count 0 2006.257.23:59:11.49#ibcon#*before return 0, iclass 28, count 0 2006.257.23:59:11.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:59:11.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.257.23:59:11.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.257.23:59:11.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.257.23:59:11.49$vck44/vblo=2,634.99 2006.257.23:59:11.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.257.23:59:11.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.257.23:59:11.49#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:11.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:11.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:11.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:11.49#ibcon#enter wrdev, iclass 30, count 0 2006.257.23:59:11.49#ibcon#first serial, iclass 30, count 0 2006.257.23:59:11.49#ibcon#enter sib2, iclass 30, count 0 2006.257.23:59:11.49#ibcon#flushed, iclass 30, count 0 2006.257.23:59:11.49#ibcon#about to write, iclass 30, count 0 2006.257.23:59:11.49#ibcon#wrote, iclass 30, count 0 2006.257.23:59:11.49#ibcon#about to read 3, iclass 30, count 0 2006.257.23:59:11.51#ibcon#read 3, iclass 30, count 0 2006.257.23:59:11.51#ibcon#about to read 4, iclass 30, count 0 2006.257.23:59:11.51#ibcon#read 4, iclass 30, count 0 2006.257.23:59:11.51#ibcon#about to read 5, iclass 30, count 0 2006.257.23:59:11.51#ibcon#read 5, iclass 30, count 0 2006.257.23:59:11.51#ibcon#about to read 6, iclass 30, count 0 2006.257.23:59:11.51#ibcon#read 6, iclass 30, count 0 2006.257.23:59:11.51#ibcon#end of sib2, iclass 30, count 0 2006.257.23:59:11.51#ibcon#*mode == 0, iclass 30, count 0 2006.257.23:59:11.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.257.23:59:11.51#ibcon#[28=FRQ=02,634.99\r\n] 2006.257.23:59:11.51#ibcon#*before write, iclass 30, count 0 2006.257.23:59:11.51#ibcon#enter sib2, iclass 30, count 0 2006.257.23:59:11.51#ibcon#flushed, iclass 30, count 0 2006.257.23:59:11.51#ibcon#about to write, iclass 30, count 0 2006.257.23:59:11.51#ibcon#wrote, iclass 30, count 0 2006.257.23:59:11.51#ibcon#about to read 3, iclass 30, count 0 2006.257.23:59:11.55#ibcon#read 3, iclass 30, count 0 2006.257.23:59:11.55#ibcon#about to read 4, iclass 30, count 0 2006.257.23:59:11.55#ibcon#read 4, iclass 30, count 0 2006.257.23:59:11.55#ibcon#about to read 5, iclass 30, count 0 2006.257.23:59:11.55#ibcon#read 5, iclass 30, count 0 2006.257.23:59:11.55#ibcon#about to read 6, iclass 30, count 0 2006.257.23:59:11.55#ibcon#read 6, iclass 30, count 0 2006.257.23:59:11.55#ibcon#end of sib2, iclass 30, count 0 2006.257.23:59:11.55#ibcon#*after write, iclass 30, count 0 2006.257.23:59:11.55#ibcon#*before return 0, iclass 30, count 0 2006.257.23:59:11.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:11.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.257.23:59:11.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.257.23:59:11.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.257.23:59:11.55$vck44/vb=2,5 2006.257.23:59:11.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.257.23:59:11.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.257.23:59:11.55#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:11.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:11.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:11.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:11.61#ibcon#enter wrdev, iclass 32, count 2 2006.257.23:59:11.61#ibcon#first serial, iclass 32, count 2 2006.257.23:59:11.61#ibcon#enter sib2, iclass 32, count 2 2006.257.23:59:11.61#ibcon#flushed, iclass 32, count 2 2006.257.23:59:11.61#ibcon#about to write, iclass 32, count 2 2006.257.23:59:11.61#ibcon#wrote, iclass 32, count 2 2006.257.23:59:11.61#ibcon#about to read 3, iclass 32, count 2 2006.257.23:59:11.63#ibcon#read 3, iclass 32, count 2 2006.257.23:59:11.63#ibcon#about to read 4, iclass 32, count 2 2006.257.23:59:11.63#ibcon#read 4, iclass 32, count 2 2006.257.23:59:11.63#ibcon#about to read 5, iclass 32, count 2 2006.257.23:59:11.63#ibcon#read 5, iclass 32, count 2 2006.257.23:59:11.63#ibcon#about to read 6, iclass 32, count 2 2006.257.23:59:11.63#ibcon#read 6, iclass 32, count 2 2006.257.23:59:11.63#ibcon#end of sib2, iclass 32, count 2 2006.257.23:59:11.63#ibcon#*mode == 0, iclass 32, count 2 2006.257.23:59:11.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.257.23:59:11.63#ibcon#[27=AT02-05\r\n] 2006.257.23:59:11.63#ibcon#*before write, iclass 32, count 2 2006.257.23:59:11.63#ibcon#enter sib2, iclass 32, count 2 2006.257.23:59:11.63#ibcon#flushed, iclass 32, count 2 2006.257.23:59:11.63#ibcon#about to write, iclass 32, count 2 2006.257.23:59:11.63#ibcon#wrote, iclass 32, count 2 2006.257.23:59:11.63#ibcon#about to read 3, iclass 32, count 2 2006.257.23:59:11.66#ibcon#read 3, iclass 32, count 2 2006.257.23:59:11.66#ibcon#about to read 4, iclass 32, count 2 2006.257.23:59:11.66#ibcon#read 4, iclass 32, count 2 2006.257.23:59:11.66#ibcon#about to read 5, iclass 32, count 2 2006.257.23:59:11.66#ibcon#read 5, iclass 32, count 2 2006.257.23:59:11.66#ibcon#about to read 6, iclass 32, count 2 2006.257.23:59:11.66#ibcon#read 6, iclass 32, count 2 2006.257.23:59:11.66#ibcon#end of sib2, iclass 32, count 2 2006.257.23:59:11.66#ibcon#*after write, iclass 32, count 2 2006.257.23:59:11.66#ibcon#*before return 0, iclass 32, count 2 2006.257.23:59:11.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:11.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.257.23:59:11.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.257.23:59:11.66#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:11.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:11.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:11.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:11.78#ibcon#enter wrdev, iclass 32, count 0 2006.257.23:59:11.78#ibcon#first serial, iclass 32, count 0 2006.257.23:59:11.78#ibcon#enter sib2, iclass 32, count 0 2006.257.23:59:11.78#ibcon#flushed, iclass 32, count 0 2006.257.23:59:11.78#ibcon#about to write, iclass 32, count 0 2006.257.23:59:11.78#ibcon#wrote, iclass 32, count 0 2006.257.23:59:11.78#ibcon#about to read 3, iclass 32, count 0 2006.257.23:59:11.80#ibcon#read 3, iclass 32, count 0 2006.257.23:59:11.80#ibcon#about to read 4, iclass 32, count 0 2006.257.23:59:11.80#ibcon#read 4, iclass 32, count 0 2006.257.23:59:11.80#ibcon#about to read 5, iclass 32, count 0 2006.257.23:59:11.80#ibcon#read 5, iclass 32, count 0 2006.257.23:59:11.80#ibcon#about to read 6, iclass 32, count 0 2006.257.23:59:11.80#ibcon#read 6, iclass 32, count 0 2006.257.23:59:11.80#ibcon#end of sib2, iclass 32, count 0 2006.257.23:59:11.80#ibcon#*mode == 0, iclass 32, count 0 2006.257.23:59:11.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.257.23:59:11.80#ibcon#[27=USB\r\n] 2006.257.23:59:11.80#ibcon#*before write, iclass 32, count 0 2006.257.23:59:11.80#ibcon#enter sib2, iclass 32, count 0 2006.257.23:59:11.80#ibcon#flushed, iclass 32, count 0 2006.257.23:59:11.80#ibcon#about to write, iclass 32, count 0 2006.257.23:59:11.80#ibcon#wrote, iclass 32, count 0 2006.257.23:59:11.80#ibcon#about to read 3, iclass 32, count 0 2006.257.23:59:11.83#ibcon#read 3, iclass 32, count 0 2006.257.23:59:11.83#ibcon#about to read 4, iclass 32, count 0 2006.257.23:59:11.83#ibcon#read 4, iclass 32, count 0 2006.257.23:59:11.83#ibcon#about to read 5, iclass 32, count 0 2006.257.23:59:11.83#ibcon#read 5, iclass 32, count 0 2006.257.23:59:11.83#ibcon#about to read 6, iclass 32, count 0 2006.257.23:59:11.83#ibcon#read 6, iclass 32, count 0 2006.257.23:59:11.83#ibcon#end of sib2, iclass 32, count 0 2006.257.23:59:11.83#ibcon#*after write, iclass 32, count 0 2006.257.23:59:11.83#ibcon#*before return 0, iclass 32, count 0 2006.257.23:59:11.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:11.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.257.23:59:11.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.257.23:59:11.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.257.23:59:11.83$vck44/vblo=3,649.99 2006.257.23:59:11.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.257.23:59:11.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.257.23:59:11.83#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:11.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:11.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:11.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:11.83#ibcon#enter wrdev, iclass 34, count 0 2006.257.23:59:11.83#ibcon#first serial, iclass 34, count 0 2006.257.23:59:11.83#ibcon#enter sib2, iclass 34, count 0 2006.257.23:59:11.83#ibcon#flushed, iclass 34, count 0 2006.257.23:59:11.83#ibcon#about to write, iclass 34, count 0 2006.257.23:59:11.83#ibcon#wrote, iclass 34, count 0 2006.257.23:59:11.83#ibcon#about to read 3, iclass 34, count 0 2006.257.23:59:11.85#ibcon#read 3, iclass 34, count 0 2006.257.23:59:11.85#ibcon#about to read 4, iclass 34, count 0 2006.257.23:59:11.85#ibcon#read 4, iclass 34, count 0 2006.257.23:59:11.85#ibcon#about to read 5, iclass 34, count 0 2006.257.23:59:11.85#ibcon#read 5, iclass 34, count 0 2006.257.23:59:11.85#ibcon#about to read 6, iclass 34, count 0 2006.257.23:59:11.85#ibcon#read 6, iclass 34, count 0 2006.257.23:59:11.85#ibcon#end of sib2, iclass 34, count 0 2006.257.23:59:11.85#ibcon#*mode == 0, iclass 34, count 0 2006.257.23:59:11.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.257.23:59:11.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.257.23:59:11.85#ibcon#*before write, iclass 34, count 0 2006.257.23:59:11.85#ibcon#enter sib2, iclass 34, count 0 2006.257.23:59:11.85#ibcon#flushed, iclass 34, count 0 2006.257.23:59:11.85#ibcon#about to write, iclass 34, count 0 2006.257.23:59:11.85#ibcon#wrote, iclass 34, count 0 2006.257.23:59:11.85#ibcon#about to read 3, iclass 34, count 0 2006.257.23:59:11.89#ibcon#read 3, iclass 34, count 0 2006.257.23:59:11.89#ibcon#about to read 4, iclass 34, count 0 2006.257.23:59:11.89#ibcon#read 4, iclass 34, count 0 2006.257.23:59:11.89#ibcon#about to read 5, iclass 34, count 0 2006.257.23:59:11.89#ibcon#read 5, iclass 34, count 0 2006.257.23:59:11.89#ibcon#about to read 6, iclass 34, count 0 2006.257.23:59:11.89#ibcon#read 6, iclass 34, count 0 2006.257.23:59:11.89#ibcon#end of sib2, iclass 34, count 0 2006.257.23:59:11.89#ibcon#*after write, iclass 34, count 0 2006.257.23:59:11.89#ibcon#*before return 0, iclass 34, count 0 2006.257.23:59:11.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:11.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.257.23:59:11.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.257.23:59:11.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.257.23:59:11.89$vck44/vb=3,4 2006.257.23:59:11.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.257.23:59:11.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.257.23:59:11.89#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:11.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:11.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:11.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:11.95#ibcon#enter wrdev, iclass 36, count 2 2006.257.23:59:11.95#ibcon#first serial, iclass 36, count 2 2006.257.23:59:11.95#ibcon#enter sib2, iclass 36, count 2 2006.257.23:59:11.95#ibcon#flushed, iclass 36, count 2 2006.257.23:59:11.95#ibcon#about to write, iclass 36, count 2 2006.257.23:59:11.95#ibcon#wrote, iclass 36, count 2 2006.257.23:59:11.95#ibcon#about to read 3, iclass 36, count 2 2006.257.23:59:11.97#ibcon#read 3, iclass 36, count 2 2006.257.23:59:11.97#ibcon#about to read 4, iclass 36, count 2 2006.257.23:59:11.97#ibcon#read 4, iclass 36, count 2 2006.257.23:59:11.97#ibcon#about to read 5, iclass 36, count 2 2006.257.23:59:11.97#ibcon#read 5, iclass 36, count 2 2006.257.23:59:11.97#ibcon#about to read 6, iclass 36, count 2 2006.257.23:59:11.97#ibcon#read 6, iclass 36, count 2 2006.257.23:59:11.97#ibcon#end of sib2, iclass 36, count 2 2006.257.23:59:11.97#ibcon#*mode == 0, iclass 36, count 2 2006.257.23:59:11.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.257.23:59:11.97#ibcon#[27=AT03-04\r\n] 2006.257.23:59:11.97#ibcon#*before write, iclass 36, count 2 2006.257.23:59:11.97#ibcon#enter sib2, iclass 36, count 2 2006.257.23:59:11.97#ibcon#flushed, iclass 36, count 2 2006.257.23:59:11.97#ibcon#about to write, iclass 36, count 2 2006.257.23:59:11.97#ibcon#wrote, iclass 36, count 2 2006.257.23:59:11.97#ibcon#about to read 3, iclass 36, count 2 2006.257.23:59:12.00#ibcon#read 3, iclass 36, count 2 2006.257.23:59:12.00#ibcon#about to read 4, iclass 36, count 2 2006.257.23:59:12.00#ibcon#read 4, iclass 36, count 2 2006.257.23:59:12.00#ibcon#about to read 5, iclass 36, count 2 2006.257.23:59:12.00#ibcon#read 5, iclass 36, count 2 2006.257.23:59:12.00#ibcon#about to read 6, iclass 36, count 2 2006.257.23:59:12.00#ibcon#read 6, iclass 36, count 2 2006.257.23:59:12.00#ibcon#end of sib2, iclass 36, count 2 2006.257.23:59:12.00#ibcon#*after write, iclass 36, count 2 2006.257.23:59:12.00#ibcon#*before return 0, iclass 36, count 2 2006.257.23:59:12.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:12.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.257.23:59:12.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.257.23:59:12.00#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:12.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:12.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:12.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:12.12#ibcon#enter wrdev, iclass 36, count 0 2006.257.23:59:12.12#ibcon#first serial, iclass 36, count 0 2006.257.23:59:12.12#ibcon#enter sib2, iclass 36, count 0 2006.257.23:59:12.12#ibcon#flushed, iclass 36, count 0 2006.257.23:59:12.12#ibcon#about to write, iclass 36, count 0 2006.257.23:59:12.12#ibcon#wrote, iclass 36, count 0 2006.257.23:59:12.12#ibcon#about to read 3, iclass 36, count 0 2006.257.23:59:12.14#ibcon#read 3, iclass 36, count 0 2006.257.23:59:12.14#ibcon#about to read 4, iclass 36, count 0 2006.257.23:59:12.14#ibcon#read 4, iclass 36, count 0 2006.257.23:59:12.14#ibcon#about to read 5, iclass 36, count 0 2006.257.23:59:12.14#ibcon#read 5, iclass 36, count 0 2006.257.23:59:12.14#ibcon#about to read 6, iclass 36, count 0 2006.257.23:59:12.14#ibcon#read 6, iclass 36, count 0 2006.257.23:59:12.14#ibcon#end of sib2, iclass 36, count 0 2006.257.23:59:12.14#ibcon#*mode == 0, iclass 36, count 0 2006.257.23:59:12.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.257.23:59:12.14#ibcon#[27=USB\r\n] 2006.257.23:59:12.14#ibcon#*before write, iclass 36, count 0 2006.257.23:59:12.14#ibcon#enter sib2, iclass 36, count 0 2006.257.23:59:12.14#ibcon#flushed, iclass 36, count 0 2006.257.23:59:12.14#ibcon#about to write, iclass 36, count 0 2006.257.23:59:12.14#ibcon#wrote, iclass 36, count 0 2006.257.23:59:12.14#ibcon#about to read 3, iclass 36, count 0 2006.257.23:59:12.17#ibcon#read 3, iclass 36, count 0 2006.257.23:59:12.17#ibcon#about to read 4, iclass 36, count 0 2006.257.23:59:12.17#ibcon#read 4, iclass 36, count 0 2006.257.23:59:12.17#ibcon#about to read 5, iclass 36, count 0 2006.257.23:59:12.17#ibcon#read 5, iclass 36, count 0 2006.257.23:59:12.17#ibcon#about to read 6, iclass 36, count 0 2006.257.23:59:12.17#ibcon#read 6, iclass 36, count 0 2006.257.23:59:12.17#ibcon#end of sib2, iclass 36, count 0 2006.257.23:59:12.17#ibcon#*after write, iclass 36, count 0 2006.257.23:59:12.17#ibcon#*before return 0, iclass 36, count 0 2006.257.23:59:12.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:12.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.257.23:59:12.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.257.23:59:12.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.257.23:59:12.17$vck44/vblo=4,679.99 2006.257.23:59:12.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.257.23:59:12.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.257.23:59:12.17#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:12.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:12.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:12.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:12.17#ibcon#enter wrdev, iclass 38, count 0 2006.257.23:59:12.17#ibcon#first serial, iclass 38, count 0 2006.257.23:59:12.17#ibcon#enter sib2, iclass 38, count 0 2006.257.23:59:12.17#ibcon#flushed, iclass 38, count 0 2006.257.23:59:12.17#ibcon#about to write, iclass 38, count 0 2006.257.23:59:12.17#ibcon#wrote, iclass 38, count 0 2006.257.23:59:12.17#ibcon#about to read 3, iclass 38, count 0 2006.257.23:59:12.19#ibcon#read 3, iclass 38, count 0 2006.257.23:59:12.19#ibcon#about to read 4, iclass 38, count 0 2006.257.23:59:12.19#ibcon#read 4, iclass 38, count 0 2006.257.23:59:12.19#ibcon#about to read 5, iclass 38, count 0 2006.257.23:59:12.19#ibcon#read 5, iclass 38, count 0 2006.257.23:59:12.19#ibcon#about to read 6, iclass 38, count 0 2006.257.23:59:12.19#ibcon#read 6, iclass 38, count 0 2006.257.23:59:12.19#ibcon#end of sib2, iclass 38, count 0 2006.257.23:59:12.19#ibcon#*mode == 0, iclass 38, count 0 2006.257.23:59:12.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.257.23:59:12.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.257.23:59:12.19#ibcon#*before write, iclass 38, count 0 2006.257.23:59:12.19#ibcon#enter sib2, iclass 38, count 0 2006.257.23:59:12.19#ibcon#flushed, iclass 38, count 0 2006.257.23:59:12.19#ibcon#about to write, iclass 38, count 0 2006.257.23:59:12.19#ibcon#wrote, iclass 38, count 0 2006.257.23:59:12.19#ibcon#about to read 3, iclass 38, count 0 2006.257.23:59:12.23#ibcon#read 3, iclass 38, count 0 2006.257.23:59:12.23#ibcon#about to read 4, iclass 38, count 0 2006.257.23:59:12.23#ibcon#read 4, iclass 38, count 0 2006.257.23:59:12.23#ibcon#about to read 5, iclass 38, count 0 2006.257.23:59:12.23#ibcon#read 5, iclass 38, count 0 2006.257.23:59:12.23#ibcon#about to read 6, iclass 38, count 0 2006.257.23:59:12.23#ibcon#read 6, iclass 38, count 0 2006.257.23:59:12.23#ibcon#end of sib2, iclass 38, count 0 2006.257.23:59:12.23#ibcon#*after write, iclass 38, count 0 2006.257.23:59:12.23#ibcon#*before return 0, iclass 38, count 0 2006.257.23:59:12.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:12.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.257.23:59:12.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.257.23:59:12.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.257.23:59:12.23$vck44/vb=4,5 2006.257.23:59:12.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.257.23:59:12.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.257.23:59:12.23#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:12.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:12.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:12.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:12.29#ibcon#enter wrdev, iclass 40, count 2 2006.257.23:59:12.29#ibcon#first serial, iclass 40, count 2 2006.257.23:59:12.29#ibcon#enter sib2, iclass 40, count 2 2006.257.23:59:12.29#ibcon#flushed, iclass 40, count 2 2006.257.23:59:12.29#ibcon#about to write, iclass 40, count 2 2006.257.23:59:12.29#ibcon#wrote, iclass 40, count 2 2006.257.23:59:12.29#ibcon#about to read 3, iclass 40, count 2 2006.257.23:59:12.31#ibcon#read 3, iclass 40, count 2 2006.257.23:59:12.31#ibcon#about to read 4, iclass 40, count 2 2006.257.23:59:12.31#ibcon#read 4, iclass 40, count 2 2006.257.23:59:12.31#ibcon#about to read 5, iclass 40, count 2 2006.257.23:59:12.31#ibcon#read 5, iclass 40, count 2 2006.257.23:59:12.31#ibcon#about to read 6, iclass 40, count 2 2006.257.23:59:12.31#ibcon#read 6, iclass 40, count 2 2006.257.23:59:12.31#ibcon#end of sib2, iclass 40, count 2 2006.257.23:59:12.31#ibcon#*mode == 0, iclass 40, count 2 2006.257.23:59:12.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.257.23:59:12.31#ibcon#[27=AT04-05\r\n] 2006.257.23:59:12.31#ibcon#*before write, iclass 40, count 2 2006.257.23:59:12.31#ibcon#enter sib2, iclass 40, count 2 2006.257.23:59:12.31#ibcon#flushed, iclass 40, count 2 2006.257.23:59:12.31#ibcon#about to write, iclass 40, count 2 2006.257.23:59:12.31#ibcon#wrote, iclass 40, count 2 2006.257.23:59:12.31#ibcon#about to read 3, iclass 40, count 2 2006.257.23:59:12.34#ibcon#read 3, iclass 40, count 2 2006.257.23:59:12.34#ibcon#about to read 4, iclass 40, count 2 2006.257.23:59:12.34#ibcon#read 4, iclass 40, count 2 2006.257.23:59:12.34#ibcon#about to read 5, iclass 40, count 2 2006.257.23:59:12.34#ibcon#read 5, iclass 40, count 2 2006.257.23:59:12.34#ibcon#about to read 6, iclass 40, count 2 2006.257.23:59:12.34#ibcon#read 6, iclass 40, count 2 2006.257.23:59:12.34#ibcon#end of sib2, iclass 40, count 2 2006.257.23:59:12.34#ibcon#*after write, iclass 40, count 2 2006.257.23:59:12.34#ibcon#*before return 0, iclass 40, count 2 2006.257.23:59:12.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:12.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.257.23:59:12.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.257.23:59:12.34#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:12.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:12.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:12.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:12.46#ibcon#enter wrdev, iclass 40, count 0 2006.257.23:59:12.46#ibcon#first serial, iclass 40, count 0 2006.257.23:59:12.46#ibcon#enter sib2, iclass 40, count 0 2006.257.23:59:12.46#ibcon#flushed, iclass 40, count 0 2006.257.23:59:12.46#ibcon#about to write, iclass 40, count 0 2006.257.23:59:12.46#ibcon#wrote, iclass 40, count 0 2006.257.23:59:12.46#ibcon#about to read 3, iclass 40, count 0 2006.257.23:59:12.48#ibcon#read 3, iclass 40, count 0 2006.257.23:59:12.48#ibcon#about to read 4, iclass 40, count 0 2006.257.23:59:12.48#ibcon#read 4, iclass 40, count 0 2006.257.23:59:12.48#ibcon#about to read 5, iclass 40, count 0 2006.257.23:59:12.48#ibcon#read 5, iclass 40, count 0 2006.257.23:59:12.48#ibcon#about to read 6, iclass 40, count 0 2006.257.23:59:12.48#ibcon#read 6, iclass 40, count 0 2006.257.23:59:12.48#ibcon#end of sib2, iclass 40, count 0 2006.257.23:59:12.48#ibcon#*mode == 0, iclass 40, count 0 2006.257.23:59:12.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.257.23:59:12.48#ibcon#[27=USB\r\n] 2006.257.23:59:12.48#ibcon#*before write, iclass 40, count 0 2006.257.23:59:12.48#ibcon#enter sib2, iclass 40, count 0 2006.257.23:59:12.48#ibcon#flushed, iclass 40, count 0 2006.257.23:59:12.48#ibcon#about to write, iclass 40, count 0 2006.257.23:59:12.48#ibcon#wrote, iclass 40, count 0 2006.257.23:59:12.48#ibcon#about to read 3, iclass 40, count 0 2006.257.23:59:12.51#ibcon#read 3, iclass 40, count 0 2006.257.23:59:12.51#ibcon#about to read 4, iclass 40, count 0 2006.257.23:59:12.51#ibcon#read 4, iclass 40, count 0 2006.257.23:59:12.51#ibcon#about to read 5, iclass 40, count 0 2006.257.23:59:12.51#ibcon#read 5, iclass 40, count 0 2006.257.23:59:12.51#ibcon#about to read 6, iclass 40, count 0 2006.257.23:59:12.51#ibcon#read 6, iclass 40, count 0 2006.257.23:59:12.51#ibcon#end of sib2, iclass 40, count 0 2006.257.23:59:12.51#ibcon#*after write, iclass 40, count 0 2006.257.23:59:12.51#ibcon#*before return 0, iclass 40, count 0 2006.257.23:59:12.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:12.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.257.23:59:12.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.257.23:59:12.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.257.23:59:12.51$vck44/vblo=5,709.99 2006.257.23:59:12.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.257.23:59:12.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.257.23:59:12.51#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:12.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:12.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:12.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:12.51#ibcon#enter wrdev, iclass 4, count 0 2006.257.23:59:12.51#ibcon#first serial, iclass 4, count 0 2006.257.23:59:12.51#ibcon#enter sib2, iclass 4, count 0 2006.257.23:59:12.51#ibcon#flushed, iclass 4, count 0 2006.257.23:59:12.51#ibcon#about to write, iclass 4, count 0 2006.257.23:59:12.51#ibcon#wrote, iclass 4, count 0 2006.257.23:59:12.51#ibcon#about to read 3, iclass 4, count 0 2006.257.23:59:12.53#ibcon#read 3, iclass 4, count 0 2006.257.23:59:12.53#ibcon#about to read 4, iclass 4, count 0 2006.257.23:59:12.53#ibcon#read 4, iclass 4, count 0 2006.257.23:59:12.53#ibcon#about to read 5, iclass 4, count 0 2006.257.23:59:12.53#ibcon#read 5, iclass 4, count 0 2006.257.23:59:12.53#ibcon#about to read 6, iclass 4, count 0 2006.257.23:59:12.53#ibcon#read 6, iclass 4, count 0 2006.257.23:59:12.53#ibcon#end of sib2, iclass 4, count 0 2006.257.23:59:12.53#ibcon#*mode == 0, iclass 4, count 0 2006.257.23:59:12.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.257.23:59:12.53#ibcon#[28=FRQ=05,709.99\r\n] 2006.257.23:59:12.53#ibcon#*before write, iclass 4, count 0 2006.257.23:59:12.53#ibcon#enter sib2, iclass 4, count 0 2006.257.23:59:12.53#ibcon#flushed, iclass 4, count 0 2006.257.23:59:12.53#ibcon#about to write, iclass 4, count 0 2006.257.23:59:12.53#ibcon#wrote, iclass 4, count 0 2006.257.23:59:12.53#ibcon#about to read 3, iclass 4, count 0 2006.257.23:59:12.57#ibcon#read 3, iclass 4, count 0 2006.257.23:59:12.57#ibcon#about to read 4, iclass 4, count 0 2006.257.23:59:12.57#ibcon#read 4, iclass 4, count 0 2006.257.23:59:12.57#ibcon#about to read 5, iclass 4, count 0 2006.257.23:59:12.57#ibcon#read 5, iclass 4, count 0 2006.257.23:59:12.57#ibcon#about to read 6, iclass 4, count 0 2006.257.23:59:12.57#ibcon#read 6, iclass 4, count 0 2006.257.23:59:12.57#ibcon#end of sib2, iclass 4, count 0 2006.257.23:59:12.57#ibcon#*after write, iclass 4, count 0 2006.257.23:59:12.57#ibcon#*before return 0, iclass 4, count 0 2006.257.23:59:12.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:12.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.257.23:59:12.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.257.23:59:12.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.257.23:59:12.57$vck44/vb=5,4 2006.257.23:59:12.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.257.23:59:12.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.257.23:59:12.57#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:12.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:12.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:12.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:12.63#ibcon#enter wrdev, iclass 6, count 2 2006.257.23:59:12.63#ibcon#first serial, iclass 6, count 2 2006.257.23:59:12.63#ibcon#enter sib2, iclass 6, count 2 2006.257.23:59:12.63#ibcon#flushed, iclass 6, count 2 2006.257.23:59:12.63#ibcon#about to write, iclass 6, count 2 2006.257.23:59:12.63#ibcon#wrote, iclass 6, count 2 2006.257.23:59:12.63#ibcon#about to read 3, iclass 6, count 2 2006.257.23:59:12.65#ibcon#read 3, iclass 6, count 2 2006.257.23:59:12.65#ibcon#about to read 4, iclass 6, count 2 2006.257.23:59:12.65#ibcon#read 4, iclass 6, count 2 2006.257.23:59:12.65#ibcon#about to read 5, iclass 6, count 2 2006.257.23:59:12.65#ibcon#read 5, iclass 6, count 2 2006.257.23:59:12.65#ibcon#about to read 6, iclass 6, count 2 2006.257.23:59:12.65#ibcon#read 6, iclass 6, count 2 2006.257.23:59:12.65#ibcon#end of sib2, iclass 6, count 2 2006.257.23:59:12.65#ibcon#*mode == 0, iclass 6, count 2 2006.257.23:59:12.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.257.23:59:12.65#ibcon#[27=AT05-04\r\n] 2006.257.23:59:12.65#ibcon#*before write, iclass 6, count 2 2006.257.23:59:12.65#ibcon#enter sib2, iclass 6, count 2 2006.257.23:59:12.65#ibcon#flushed, iclass 6, count 2 2006.257.23:59:12.65#ibcon#about to write, iclass 6, count 2 2006.257.23:59:12.65#ibcon#wrote, iclass 6, count 2 2006.257.23:59:12.65#ibcon#about to read 3, iclass 6, count 2 2006.257.23:59:12.68#ibcon#read 3, iclass 6, count 2 2006.257.23:59:12.68#ibcon#about to read 4, iclass 6, count 2 2006.257.23:59:12.68#ibcon#read 4, iclass 6, count 2 2006.257.23:59:12.68#ibcon#about to read 5, iclass 6, count 2 2006.257.23:59:12.68#ibcon#read 5, iclass 6, count 2 2006.257.23:59:12.68#ibcon#about to read 6, iclass 6, count 2 2006.257.23:59:12.68#ibcon#read 6, iclass 6, count 2 2006.257.23:59:12.68#ibcon#end of sib2, iclass 6, count 2 2006.257.23:59:12.68#ibcon#*after write, iclass 6, count 2 2006.257.23:59:12.68#ibcon#*before return 0, iclass 6, count 2 2006.257.23:59:12.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:12.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.257.23:59:12.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.257.23:59:12.68#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:12.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:12.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:12.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:12.80#ibcon#enter wrdev, iclass 6, count 0 2006.257.23:59:12.80#ibcon#first serial, iclass 6, count 0 2006.257.23:59:12.80#ibcon#enter sib2, iclass 6, count 0 2006.257.23:59:12.80#ibcon#flushed, iclass 6, count 0 2006.257.23:59:12.80#ibcon#about to write, iclass 6, count 0 2006.257.23:59:12.80#ibcon#wrote, iclass 6, count 0 2006.257.23:59:12.80#ibcon#about to read 3, iclass 6, count 0 2006.257.23:59:12.82#ibcon#read 3, iclass 6, count 0 2006.257.23:59:12.82#ibcon#about to read 4, iclass 6, count 0 2006.257.23:59:12.82#ibcon#read 4, iclass 6, count 0 2006.257.23:59:12.82#ibcon#about to read 5, iclass 6, count 0 2006.257.23:59:12.82#ibcon#read 5, iclass 6, count 0 2006.257.23:59:12.82#ibcon#about to read 6, iclass 6, count 0 2006.257.23:59:12.82#ibcon#read 6, iclass 6, count 0 2006.257.23:59:12.82#ibcon#end of sib2, iclass 6, count 0 2006.257.23:59:12.82#ibcon#*mode == 0, iclass 6, count 0 2006.257.23:59:12.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.257.23:59:12.82#ibcon#[27=USB\r\n] 2006.257.23:59:12.82#ibcon#*before write, iclass 6, count 0 2006.257.23:59:12.82#ibcon#enter sib2, iclass 6, count 0 2006.257.23:59:12.82#ibcon#flushed, iclass 6, count 0 2006.257.23:59:12.82#ibcon#about to write, iclass 6, count 0 2006.257.23:59:12.82#ibcon#wrote, iclass 6, count 0 2006.257.23:59:12.82#ibcon#about to read 3, iclass 6, count 0 2006.257.23:59:12.85#ibcon#read 3, iclass 6, count 0 2006.257.23:59:12.85#ibcon#about to read 4, iclass 6, count 0 2006.257.23:59:12.85#ibcon#read 4, iclass 6, count 0 2006.257.23:59:12.85#ibcon#about to read 5, iclass 6, count 0 2006.257.23:59:12.85#ibcon#read 5, iclass 6, count 0 2006.257.23:59:12.85#ibcon#about to read 6, iclass 6, count 0 2006.257.23:59:12.85#ibcon#read 6, iclass 6, count 0 2006.257.23:59:12.85#ibcon#end of sib2, iclass 6, count 0 2006.257.23:59:12.85#ibcon#*after write, iclass 6, count 0 2006.257.23:59:12.85#ibcon#*before return 0, iclass 6, count 0 2006.257.23:59:12.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:12.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.257.23:59:12.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.257.23:59:12.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.257.23:59:12.85$vck44/vblo=6,719.99 2006.257.23:59:12.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.257.23:59:12.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.257.23:59:12.85#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:12.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:12.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:12.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:12.85#ibcon#enter wrdev, iclass 10, count 0 2006.257.23:59:12.85#ibcon#first serial, iclass 10, count 0 2006.257.23:59:12.85#ibcon#enter sib2, iclass 10, count 0 2006.257.23:59:12.85#ibcon#flushed, iclass 10, count 0 2006.257.23:59:12.85#ibcon#about to write, iclass 10, count 0 2006.257.23:59:12.85#ibcon#wrote, iclass 10, count 0 2006.257.23:59:12.85#ibcon#about to read 3, iclass 10, count 0 2006.257.23:59:12.87#ibcon#read 3, iclass 10, count 0 2006.257.23:59:12.87#ibcon#about to read 4, iclass 10, count 0 2006.257.23:59:12.87#ibcon#read 4, iclass 10, count 0 2006.257.23:59:12.87#ibcon#about to read 5, iclass 10, count 0 2006.257.23:59:12.87#ibcon#read 5, iclass 10, count 0 2006.257.23:59:12.87#ibcon#about to read 6, iclass 10, count 0 2006.257.23:59:12.87#ibcon#read 6, iclass 10, count 0 2006.257.23:59:12.87#ibcon#end of sib2, iclass 10, count 0 2006.257.23:59:12.87#ibcon#*mode == 0, iclass 10, count 0 2006.257.23:59:12.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.257.23:59:12.87#ibcon#[28=FRQ=06,719.99\r\n] 2006.257.23:59:12.87#ibcon#*before write, iclass 10, count 0 2006.257.23:59:12.87#ibcon#enter sib2, iclass 10, count 0 2006.257.23:59:12.87#ibcon#flushed, iclass 10, count 0 2006.257.23:59:12.87#ibcon#about to write, iclass 10, count 0 2006.257.23:59:12.87#ibcon#wrote, iclass 10, count 0 2006.257.23:59:12.87#ibcon#about to read 3, iclass 10, count 0 2006.257.23:59:12.91#ibcon#read 3, iclass 10, count 0 2006.257.23:59:12.91#ibcon#about to read 4, iclass 10, count 0 2006.257.23:59:12.91#ibcon#read 4, iclass 10, count 0 2006.257.23:59:12.91#ibcon#about to read 5, iclass 10, count 0 2006.257.23:59:12.91#ibcon#read 5, iclass 10, count 0 2006.257.23:59:12.91#ibcon#about to read 6, iclass 10, count 0 2006.257.23:59:12.91#ibcon#read 6, iclass 10, count 0 2006.257.23:59:12.91#ibcon#end of sib2, iclass 10, count 0 2006.257.23:59:12.91#ibcon#*after write, iclass 10, count 0 2006.257.23:59:12.91#ibcon#*before return 0, iclass 10, count 0 2006.257.23:59:12.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:12.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.257.23:59:12.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.257.23:59:12.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.257.23:59:12.91$vck44/vb=6,4 2006.257.23:59:12.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.257.23:59:12.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.257.23:59:12.91#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:12.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:12.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:12.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:12.97#ibcon#enter wrdev, iclass 12, count 2 2006.257.23:59:12.97#ibcon#first serial, iclass 12, count 2 2006.257.23:59:12.97#ibcon#enter sib2, iclass 12, count 2 2006.257.23:59:12.97#ibcon#flushed, iclass 12, count 2 2006.257.23:59:12.97#ibcon#about to write, iclass 12, count 2 2006.257.23:59:12.97#ibcon#wrote, iclass 12, count 2 2006.257.23:59:12.97#ibcon#about to read 3, iclass 12, count 2 2006.257.23:59:12.99#ibcon#read 3, iclass 12, count 2 2006.257.23:59:12.99#ibcon#about to read 4, iclass 12, count 2 2006.257.23:59:12.99#ibcon#read 4, iclass 12, count 2 2006.257.23:59:12.99#ibcon#about to read 5, iclass 12, count 2 2006.257.23:59:12.99#ibcon#read 5, iclass 12, count 2 2006.257.23:59:12.99#ibcon#about to read 6, iclass 12, count 2 2006.257.23:59:12.99#ibcon#read 6, iclass 12, count 2 2006.257.23:59:12.99#ibcon#end of sib2, iclass 12, count 2 2006.257.23:59:12.99#ibcon#*mode == 0, iclass 12, count 2 2006.257.23:59:12.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.257.23:59:12.99#ibcon#[27=AT06-04\r\n] 2006.257.23:59:12.99#ibcon#*before write, iclass 12, count 2 2006.257.23:59:12.99#ibcon#enter sib2, iclass 12, count 2 2006.257.23:59:12.99#ibcon#flushed, iclass 12, count 2 2006.257.23:59:12.99#ibcon#about to write, iclass 12, count 2 2006.257.23:59:12.99#ibcon#wrote, iclass 12, count 2 2006.257.23:59:12.99#ibcon#about to read 3, iclass 12, count 2 2006.257.23:59:13.02#ibcon#read 3, iclass 12, count 2 2006.257.23:59:13.02#ibcon#about to read 4, iclass 12, count 2 2006.257.23:59:13.02#ibcon#read 4, iclass 12, count 2 2006.257.23:59:13.02#ibcon#about to read 5, iclass 12, count 2 2006.257.23:59:13.02#ibcon#read 5, iclass 12, count 2 2006.257.23:59:13.02#ibcon#about to read 6, iclass 12, count 2 2006.257.23:59:13.02#ibcon#read 6, iclass 12, count 2 2006.257.23:59:13.02#ibcon#end of sib2, iclass 12, count 2 2006.257.23:59:13.02#ibcon#*after write, iclass 12, count 2 2006.257.23:59:13.02#ibcon#*before return 0, iclass 12, count 2 2006.257.23:59:13.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:13.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.257.23:59:13.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.257.23:59:13.02#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:13.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:13.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:13.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:13.14#ibcon#enter wrdev, iclass 12, count 0 2006.257.23:59:13.14#ibcon#first serial, iclass 12, count 0 2006.257.23:59:13.14#ibcon#enter sib2, iclass 12, count 0 2006.257.23:59:13.14#ibcon#flushed, iclass 12, count 0 2006.257.23:59:13.14#ibcon#about to write, iclass 12, count 0 2006.257.23:59:13.14#ibcon#wrote, iclass 12, count 0 2006.257.23:59:13.14#ibcon#about to read 3, iclass 12, count 0 2006.257.23:59:13.16#ibcon#read 3, iclass 12, count 0 2006.257.23:59:13.16#ibcon#about to read 4, iclass 12, count 0 2006.257.23:59:13.16#ibcon#read 4, iclass 12, count 0 2006.257.23:59:13.16#ibcon#about to read 5, iclass 12, count 0 2006.257.23:59:13.16#ibcon#read 5, iclass 12, count 0 2006.257.23:59:13.16#ibcon#about to read 6, iclass 12, count 0 2006.257.23:59:13.16#ibcon#read 6, iclass 12, count 0 2006.257.23:59:13.16#ibcon#end of sib2, iclass 12, count 0 2006.257.23:59:13.16#ibcon#*mode == 0, iclass 12, count 0 2006.257.23:59:13.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.257.23:59:13.16#ibcon#[27=USB\r\n] 2006.257.23:59:13.16#ibcon#*before write, iclass 12, count 0 2006.257.23:59:13.16#ibcon#enter sib2, iclass 12, count 0 2006.257.23:59:13.16#ibcon#flushed, iclass 12, count 0 2006.257.23:59:13.16#ibcon#about to write, iclass 12, count 0 2006.257.23:59:13.16#ibcon#wrote, iclass 12, count 0 2006.257.23:59:13.16#ibcon#about to read 3, iclass 12, count 0 2006.257.23:59:13.19#ibcon#read 3, iclass 12, count 0 2006.257.23:59:13.19#ibcon#about to read 4, iclass 12, count 0 2006.257.23:59:13.19#ibcon#read 4, iclass 12, count 0 2006.257.23:59:13.19#ibcon#about to read 5, iclass 12, count 0 2006.257.23:59:13.19#ibcon#read 5, iclass 12, count 0 2006.257.23:59:13.19#ibcon#about to read 6, iclass 12, count 0 2006.257.23:59:13.19#ibcon#read 6, iclass 12, count 0 2006.257.23:59:13.19#ibcon#end of sib2, iclass 12, count 0 2006.257.23:59:13.19#ibcon#*after write, iclass 12, count 0 2006.257.23:59:13.19#ibcon#*before return 0, iclass 12, count 0 2006.257.23:59:13.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:13.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.257.23:59:13.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.257.23:59:13.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.257.23:59:13.19$vck44/vblo=7,734.99 2006.257.23:59:13.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.257.23:59:13.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.257.23:59:13.19#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:13.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:13.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:13.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:13.19#ibcon#enter wrdev, iclass 14, count 0 2006.257.23:59:13.19#ibcon#first serial, iclass 14, count 0 2006.257.23:59:13.19#ibcon#enter sib2, iclass 14, count 0 2006.257.23:59:13.19#ibcon#flushed, iclass 14, count 0 2006.257.23:59:13.19#ibcon#about to write, iclass 14, count 0 2006.257.23:59:13.19#ibcon#wrote, iclass 14, count 0 2006.257.23:59:13.19#ibcon#about to read 3, iclass 14, count 0 2006.257.23:59:13.21#ibcon#read 3, iclass 14, count 0 2006.257.23:59:13.21#ibcon#about to read 4, iclass 14, count 0 2006.257.23:59:13.21#ibcon#read 4, iclass 14, count 0 2006.257.23:59:13.21#ibcon#about to read 5, iclass 14, count 0 2006.257.23:59:13.21#ibcon#read 5, iclass 14, count 0 2006.257.23:59:13.21#ibcon#about to read 6, iclass 14, count 0 2006.257.23:59:13.21#ibcon#read 6, iclass 14, count 0 2006.257.23:59:13.21#ibcon#end of sib2, iclass 14, count 0 2006.257.23:59:13.21#ibcon#*mode == 0, iclass 14, count 0 2006.257.23:59:13.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.257.23:59:13.21#ibcon#[28=FRQ=07,734.99\r\n] 2006.257.23:59:13.21#ibcon#*before write, iclass 14, count 0 2006.257.23:59:13.21#ibcon#enter sib2, iclass 14, count 0 2006.257.23:59:13.21#ibcon#flushed, iclass 14, count 0 2006.257.23:59:13.21#ibcon#about to write, iclass 14, count 0 2006.257.23:59:13.21#ibcon#wrote, iclass 14, count 0 2006.257.23:59:13.21#ibcon#about to read 3, iclass 14, count 0 2006.257.23:59:13.25#ibcon#read 3, iclass 14, count 0 2006.257.23:59:13.25#ibcon#about to read 4, iclass 14, count 0 2006.257.23:59:13.25#ibcon#read 4, iclass 14, count 0 2006.257.23:59:13.25#ibcon#about to read 5, iclass 14, count 0 2006.257.23:59:13.25#ibcon#read 5, iclass 14, count 0 2006.257.23:59:13.25#ibcon#about to read 6, iclass 14, count 0 2006.257.23:59:13.25#ibcon#read 6, iclass 14, count 0 2006.257.23:59:13.25#ibcon#end of sib2, iclass 14, count 0 2006.257.23:59:13.25#ibcon#*after write, iclass 14, count 0 2006.257.23:59:13.25#ibcon#*before return 0, iclass 14, count 0 2006.257.23:59:13.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:13.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.257.23:59:13.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.257.23:59:13.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.257.23:59:13.25$vck44/vb=7,4 2006.257.23:59:13.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.257.23:59:13.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.257.23:59:13.25#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:13.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:13.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:13.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:13.31#ibcon#enter wrdev, iclass 16, count 2 2006.257.23:59:13.31#ibcon#first serial, iclass 16, count 2 2006.257.23:59:13.31#ibcon#enter sib2, iclass 16, count 2 2006.257.23:59:13.31#ibcon#flushed, iclass 16, count 2 2006.257.23:59:13.31#ibcon#about to write, iclass 16, count 2 2006.257.23:59:13.31#ibcon#wrote, iclass 16, count 2 2006.257.23:59:13.31#ibcon#about to read 3, iclass 16, count 2 2006.257.23:59:13.33#ibcon#read 3, iclass 16, count 2 2006.257.23:59:13.33#ibcon#about to read 4, iclass 16, count 2 2006.257.23:59:13.33#ibcon#read 4, iclass 16, count 2 2006.257.23:59:13.33#ibcon#about to read 5, iclass 16, count 2 2006.257.23:59:13.33#ibcon#read 5, iclass 16, count 2 2006.257.23:59:13.33#ibcon#about to read 6, iclass 16, count 2 2006.257.23:59:13.33#ibcon#read 6, iclass 16, count 2 2006.257.23:59:13.33#ibcon#end of sib2, iclass 16, count 2 2006.257.23:59:13.33#ibcon#*mode == 0, iclass 16, count 2 2006.257.23:59:13.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.257.23:59:13.33#ibcon#[27=AT07-04\r\n] 2006.257.23:59:13.33#ibcon#*before write, iclass 16, count 2 2006.257.23:59:13.33#ibcon#enter sib2, iclass 16, count 2 2006.257.23:59:13.33#ibcon#flushed, iclass 16, count 2 2006.257.23:59:13.33#ibcon#about to write, iclass 16, count 2 2006.257.23:59:13.33#ibcon#wrote, iclass 16, count 2 2006.257.23:59:13.33#ibcon#about to read 3, iclass 16, count 2 2006.257.23:59:13.36#ibcon#read 3, iclass 16, count 2 2006.257.23:59:13.36#ibcon#about to read 4, iclass 16, count 2 2006.257.23:59:13.36#ibcon#read 4, iclass 16, count 2 2006.257.23:59:13.36#ibcon#about to read 5, iclass 16, count 2 2006.257.23:59:13.36#ibcon#read 5, iclass 16, count 2 2006.257.23:59:13.36#ibcon#about to read 6, iclass 16, count 2 2006.257.23:59:13.36#ibcon#read 6, iclass 16, count 2 2006.257.23:59:13.36#ibcon#end of sib2, iclass 16, count 2 2006.257.23:59:13.36#ibcon#*after write, iclass 16, count 2 2006.257.23:59:13.36#ibcon#*before return 0, iclass 16, count 2 2006.257.23:59:13.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:13.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.257.23:59:13.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.257.23:59:13.36#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:13.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:13.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:13.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:13.48#ibcon#enter wrdev, iclass 16, count 0 2006.257.23:59:13.48#ibcon#first serial, iclass 16, count 0 2006.257.23:59:13.48#ibcon#enter sib2, iclass 16, count 0 2006.257.23:59:13.48#ibcon#flushed, iclass 16, count 0 2006.257.23:59:13.48#ibcon#about to write, iclass 16, count 0 2006.257.23:59:13.48#ibcon#wrote, iclass 16, count 0 2006.257.23:59:13.48#ibcon#about to read 3, iclass 16, count 0 2006.257.23:59:13.50#ibcon#read 3, iclass 16, count 0 2006.257.23:59:13.50#ibcon#about to read 4, iclass 16, count 0 2006.257.23:59:13.50#ibcon#read 4, iclass 16, count 0 2006.257.23:59:13.50#ibcon#about to read 5, iclass 16, count 0 2006.257.23:59:13.50#ibcon#read 5, iclass 16, count 0 2006.257.23:59:13.50#ibcon#about to read 6, iclass 16, count 0 2006.257.23:59:13.50#ibcon#read 6, iclass 16, count 0 2006.257.23:59:13.50#ibcon#end of sib2, iclass 16, count 0 2006.257.23:59:13.50#ibcon#*mode == 0, iclass 16, count 0 2006.257.23:59:13.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.257.23:59:13.50#ibcon#[27=USB\r\n] 2006.257.23:59:13.50#ibcon#*before write, iclass 16, count 0 2006.257.23:59:13.50#ibcon#enter sib2, iclass 16, count 0 2006.257.23:59:13.50#ibcon#flushed, iclass 16, count 0 2006.257.23:59:13.50#ibcon#about to write, iclass 16, count 0 2006.257.23:59:13.50#ibcon#wrote, iclass 16, count 0 2006.257.23:59:13.50#ibcon#about to read 3, iclass 16, count 0 2006.257.23:59:13.53#ibcon#read 3, iclass 16, count 0 2006.257.23:59:13.53#ibcon#about to read 4, iclass 16, count 0 2006.257.23:59:13.53#ibcon#read 4, iclass 16, count 0 2006.257.23:59:13.53#ibcon#about to read 5, iclass 16, count 0 2006.257.23:59:13.53#ibcon#read 5, iclass 16, count 0 2006.257.23:59:13.53#ibcon#about to read 6, iclass 16, count 0 2006.257.23:59:13.53#ibcon#read 6, iclass 16, count 0 2006.257.23:59:13.53#ibcon#end of sib2, iclass 16, count 0 2006.257.23:59:13.53#ibcon#*after write, iclass 16, count 0 2006.257.23:59:13.53#ibcon#*before return 0, iclass 16, count 0 2006.257.23:59:13.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:13.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.257.23:59:13.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.257.23:59:13.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.257.23:59:13.53$vck44/vblo=8,744.99 2006.257.23:59:13.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.257.23:59:13.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.257.23:59:13.53#ibcon#ireg 17 cls_cnt 0 2006.257.23:59:13.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:13.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:13.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:13.53#ibcon#enter wrdev, iclass 18, count 0 2006.257.23:59:13.53#ibcon#first serial, iclass 18, count 0 2006.257.23:59:13.53#ibcon#enter sib2, iclass 18, count 0 2006.257.23:59:13.53#ibcon#flushed, iclass 18, count 0 2006.257.23:59:13.53#ibcon#about to write, iclass 18, count 0 2006.257.23:59:13.53#ibcon#wrote, iclass 18, count 0 2006.257.23:59:13.53#ibcon#about to read 3, iclass 18, count 0 2006.257.23:59:13.55#ibcon#read 3, iclass 18, count 0 2006.257.23:59:13.55#ibcon#about to read 4, iclass 18, count 0 2006.257.23:59:13.55#ibcon#read 4, iclass 18, count 0 2006.257.23:59:13.55#ibcon#about to read 5, iclass 18, count 0 2006.257.23:59:13.55#ibcon#read 5, iclass 18, count 0 2006.257.23:59:13.55#ibcon#about to read 6, iclass 18, count 0 2006.257.23:59:13.55#ibcon#read 6, iclass 18, count 0 2006.257.23:59:13.55#ibcon#end of sib2, iclass 18, count 0 2006.257.23:59:13.55#ibcon#*mode == 0, iclass 18, count 0 2006.257.23:59:13.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.257.23:59:13.55#ibcon#[28=FRQ=08,744.99\r\n] 2006.257.23:59:13.55#ibcon#*before write, iclass 18, count 0 2006.257.23:59:13.55#ibcon#enter sib2, iclass 18, count 0 2006.257.23:59:13.55#ibcon#flushed, iclass 18, count 0 2006.257.23:59:13.55#ibcon#about to write, iclass 18, count 0 2006.257.23:59:13.55#ibcon#wrote, iclass 18, count 0 2006.257.23:59:13.55#ibcon#about to read 3, iclass 18, count 0 2006.257.23:59:13.59#ibcon#read 3, iclass 18, count 0 2006.257.23:59:13.59#ibcon#about to read 4, iclass 18, count 0 2006.257.23:59:13.59#ibcon#read 4, iclass 18, count 0 2006.257.23:59:13.59#ibcon#about to read 5, iclass 18, count 0 2006.257.23:59:13.59#ibcon#read 5, iclass 18, count 0 2006.257.23:59:13.59#ibcon#about to read 6, iclass 18, count 0 2006.257.23:59:13.59#ibcon#read 6, iclass 18, count 0 2006.257.23:59:13.59#ibcon#end of sib2, iclass 18, count 0 2006.257.23:59:13.59#ibcon#*after write, iclass 18, count 0 2006.257.23:59:13.59#ibcon#*before return 0, iclass 18, count 0 2006.257.23:59:13.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:13.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.257.23:59:13.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.257.23:59:13.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.257.23:59:13.59$vck44/vb=8,4 2006.257.23:59:13.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.257.23:59:13.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.257.23:59:13.59#ibcon#ireg 11 cls_cnt 2 2006.257.23:59:13.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:13.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:13.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:13.65#ibcon#enter wrdev, iclass 20, count 2 2006.257.23:59:13.65#ibcon#first serial, iclass 20, count 2 2006.257.23:59:13.65#ibcon#enter sib2, iclass 20, count 2 2006.257.23:59:13.65#ibcon#flushed, iclass 20, count 2 2006.257.23:59:13.65#ibcon#about to write, iclass 20, count 2 2006.257.23:59:13.65#ibcon#wrote, iclass 20, count 2 2006.257.23:59:13.65#ibcon#about to read 3, iclass 20, count 2 2006.257.23:59:13.67#ibcon#read 3, iclass 20, count 2 2006.257.23:59:13.67#ibcon#about to read 4, iclass 20, count 2 2006.257.23:59:13.67#ibcon#read 4, iclass 20, count 2 2006.257.23:59:13.67#ibcon#about to read 5, iclass 20, count 2 2006.257.23:59:13.67#ibcon#read 5, iclass 20, count 2 2006.257.23:59:13.67#ibcon#about to read 6, iclass 20, count 2 2006.257.23:59:13.67#ibcon#read 6, iclass 20, count 2 2006.257.23:59:13.67#ibcon#end of sib2, iclass 20, count 2 2006.257.23:59:13.67#ibcon#*mode == 0, iclass 20, count 2 2006.257.23:59:13.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.257.23:59:13.67#ibcon#[27=AT08-04\r\n] 2006.257.23:59:13.67#ibcon#*before write, iclass 20, count 2 2006.257.23:59:13.67#ibcon#enter sib2, iclass 20, count 2 2006.257.23:59:13.67#ibcon#flushed, iclass 20, count 2 2006.257.23:59:13.67#ibcon#about to write, iclass 20, count 2 2006.257.23:59:13.67#ibcon#wrote, iclass 20, count 2 2006.257.23:59:13.67#ibcon#about to read 3, iclass 20, count 2 2006.257.23:59:13.70#ibcon#read 3, iclass 20, count 2 2006.257.23:59:13.70#ibcon#about to read 4, iclass 20, count 2 2006.257.23:59:13.70#ibcon#read 4, iclass 20, count 2 2006.257.23:59:13.70#ibcon#about to read 5, iclass 20, count 2 2006.257.23:59:13.70#ibcon#read 5, iclass 20, count 2 2006.257.23:59:13.70#ibcon#about to read 6, iclass 20, count 2 2006.257.23:59:13.70#ibcon#read 6, iclass 20, count 2 2006.257.23:59:13.70#ibcon#end of sib2, iclass 20, count 2 2006.257.23:59:13.70#ibcon#*after write, iclass 20, count 2 2006.257.23:59:13.70#ibcon#*before return 0, iclass 20, count 2 2006.257.23:59:13.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:13.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.257.23:59:13.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.257.23:59:13.70#ibcon#ireg 7 cls_cnt 0 2006.257.23:59:13.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:13.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:13.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:13.82#ibcon#enter wrdev, iclass 20, count 0 2006.257.23:59:13.82#ibcon#first serial, iclass 20, count 0 2006.257.23:59:13.82#ibcon#enter sib2, iclass 20, count 0 2006.257.23:59:13.82#ibcon#flushed, iclass 20, count 0 2006.257.23:59:13.82#ibcon#about to write, iclass 20, count 0 2006.257.23:59:13.82#ibcon#wrote, iclass 20, count 0 2006.257.23:59:13.82#ibcon#about to read 3, iclass 20, count 0 2006.257.23:59:13.84#ibcon#read 3, iclass 20, count 0 2006.257.23:59:13.84#ibcon#about to read 4, iclass 20, count 0 2006.257.23:59:13.84#ibcon#read 4, iclass 20, count 0 2006.257.23:59:13.84#ibcon#about to read 5, iclass 20, count 0 2006.257.23:59:13.84#ibcon#read 5, iclass 20, count 0 2006.257.23:59:13.84#ibcon#about to read 6, iclass 20, count 0 2006.257.23:59:13.84#ibcon#read 6, iclass 20, count 0 2006.257.23:59:13.84#ibcon#end of sib2, iclass 20, count 0 2006.257.23:59:13.84#ibcon#*mode == 0, iclass 20, count 0 2006.257.23:59:13.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.257.23:59:13.84#ibcon#[27=USB\r\n] 2006.257.23:59:13.84#ibcon#*before write, iclass 20, count 0 2006.257.23:59:13.84#ibcon#enter sib2, iclass 20, count 0 2006.257.23:59:13.84#ibcon#flushed, iclass 20, count 0 2006.257.23:59:13.84#ibcon#about to write, iclass 20, count 0 2006.257.23:59:13.84#ibcon#wrote, iclass 20, count 0 2006.257.23:59:13.84#ibcon#about to read 3, iclass 20, count 0 2006.257.23:59:13.87#ibcon#read 3, iclass 20, count 0 2006.257.23:59:13.87#ibcon#about to read 4, iclass 20, count 0 2006.257.23:59:13.87#ibcon#read 4, iclass 20, count 0 2006.257.23:59:13.87#ibcon#about to read 5, iclass 20, count 0 2006.257.23:59:13.87#ibcon#read 5, iclass 20, count 0 2006.257.23:59:13.87#ibcon#about to read 6, iclass 20, count 0 2006.257.23:59:13.87#ibcon#read 6, iclass 20, count 0 2006.257.23:59:13.87#ibcon#end of sib2, iclass 20, count 0 2006.257.23:59:13.87#ibcon#*after write, iclass 20, count 0 2006.257.23:59:13.87#ibcon#*before return 0, iclass 20, count 0 2006.257.23:59:13.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:13.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.257.23:59:13.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.257.23:59:13.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.257.23:59:13.87$vck44/vabw=wide 2006.257.23:59:13.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.257.23:59:13.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.257.23:59:13.87#ibcon#ireg 8 cls_cnt 0 2006.257.23:59:13.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:13.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:13.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:13.87#ibcon#enter wrdev, iclass 22, count 0 2006.257.23:59:13.87#ibcon#first serial, iclass 22, count 0 2006.257.23:59:13.87#ibcon#enter sib2, iclass 22, count 0 2006.257.23:59:13.87#ibcon#flushed, iclass 22, count 0 2006.257.23:59:13.87#ibcon#about to write, iclass 22, count 0 2006.257.23:59:13.87#ibcon#wrote, iclass 22, count 0 2006.257.23:59:13.87#ibcon#about to read 3, iclass 22, count 0 2006.257.23:59:13.89#ibcon#read 3, iclass 22, count 0 2006.257.23:59:13.89#ibcon#about to read 4, iclass 22, count 0 2006.257.23:59:13.89#ibcon#read 4, iclass 22, count 0 2006.257.23:59:13.89#ibcon#about to read 5, iclass 22, count 0 2006.257.23:59:13.89#ibcon#read 5, iclass 22, count 0 2006.257.23:59:13.89#ibcon#about to read 6, iclass 22, count 0 2006.257.23:59:13.89#ibcon#read 6, iclass 22, count 0 2006.257.23:59:13.89#ibcon#end of sib2, iclass 22, count 0 2006.257.23:59:13.89#ibcon#*mode == 0, iclass 22, count 0 2006.257.23:59:13.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.257.23:59:13.89#ibcon#[25=BW32\r\n] 2006.257.23:59:13.89#ibcon#*before write, iclass 22, count 0 2006.257.23:59:13.89#ibcon#enter sib2, iclass 22, count 0 2006.257.23:59:13.89#ibcon#flushed, iclass 22, count 0 2006.257.23:59:13.89#ibcon#about to write, iclass 22, count 0 2006.257.23:59:13.89#ibcon#wrote, iclass 22, count 0 2006.257.23:59:13.89#ibcon#about to read 3, iclass 22, count 0 2006.257.23:59:13.92#ibcon#read 3, iclass 22, count 0 2006.257.23:59:13.92#ibcon#about to read 4, iclass 22, count 0 2006.257.23:59:13.92#ibcon#read 4, iclass 22, count 0 2006.257.23:59:13.92#ibcon#about to read 5, iclass 22, count 0 2006.257.23:59:13.92#ibcon#read 5, iclass 22, count 0 2006.257.23:59:13.92#ibcon#about to read 6, iclass 22, count 0 2006.257.23:59:13.92#ibcon#read 6, iclass 22, count 0 2006.257.23:59:13.92#ibcon#end of sib2, iclass 22, count 0 2006.257.23:59:13.92#ibcon#*after write, iclass 22, count 0 2006.257.23:59:13.92#ibcon#*before return 0, iclass 22, count 0 2006.257.23:59:13.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:13.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.257.23:59:13.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.257.23:59:13.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.257.23:59:13.92$vck44/vbbw=wide 2006.257.23:59:13.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.257.23:59:13.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.257.23:59:13.92#ibcon#ireg 8 cls_cnt 0 2006.257.23:59:13.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:59:13.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:59:13.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:59:13.99#ibcon#enter wrdev, iclass 24, count 0 2006.257.23:59:13.99#ibcon#first serial, iclass 24, count 0 2006.257.23:59:13.99#ibcon#enter sib2, iclass 24, count 0 2006.257.23:59:13.99#ibcon#flushed, iclass 24, count 0 2006.257.23:59:13.99#ibcon#about to write, iclass 24, count 0 2006.257.23:59:13.99#ibcon#wrote, iclass 24, count 0 2006.257.23:59:13.99#ibcon#about to read 3, iclass 24, count 0 2006.257.23:59:14.01#ibcon#read 3, iclass 24, count 0 2006.257.23:59:14.01#ibcon#about to read 4, iclass 24, count 0 2006.257.23:59:14.01#ibcon#read 4, iclass 24, count 0 2006.257.23:59:14.01#ibcon#about to read 5, iclass 24, count 0 2006.257.23:59:14.01#ibcon#read 5, iclass 24, count 0 2006.257.23:59:14.01#ibcon#about to read 6, iclass 24, count 0 2006.257.23:59:14.01#ibcon#read 6, iclass 24, count 0 2006.257.23:59:14.01#ibcon#end of sib2, iclass 24, count 0 2006.257.23:59:14.01#ibcon#*mode == 0, iclass 24, count 0 2006.257.23:59:14.01#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.257.23:59:14.01#ibcon#[27=BW32\r\n] 2006.257.23:59:14.01#ibcon#*before write, iclass 24, count 0 2006.257.23:59:14.01#ibcon#enter sib2, iclass 24, count 0 2006.257.23:59:14.01#ibcon#flushed, iclass 24, count 0 2006.257.23:59:14.01#ibcon#about to write, iclass 24, count 0 2006.257.23:59:14.01#ibcon#wrote, iclass 24, count 0 2006.257.23:59:14.01#ibcon#about to read 3, iclass 24, count 0 2006.257.23:59:14.04#ibcon#read 3, iclass 24, count 0 2006.257.23:59:14.04#ibcon#about to read 4, iclass 24, count 0 2006.257.23:59:14.04#ibcon#read 4, iclass 24, count 0 2006.257.23:59:14.04#ibcon#about to read 5, iclass 24, count 0 2006.257.23:59:14.04#ibcon#read 5, iclass 24, count 0 2006.257.23:59:14.04#ibcon#about to read 6, iclass 24, count 0 2006.257.23:59:14.04#ibcon#read 6, iclass 24, count 0 2006.257.23:59:14.04#ibcon#end of sib2, iclass 24, count 0 2006.257.23:59:14.04#ibcon#*after write, iclass 24, count 0 2006.257.23:59:14.04#ibcon#*before return 0, iclass 24, count 0 2006.257.23:59:14.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:59:14.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.257.23:59:14.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.257.23:59:14.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.257.23:59:14.04$setupk4/ifdk4 2006.257.23:59:14.04$ifdk4/lo= 2006.257.23:59:14.04$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.257.23:59:14.04$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.257.23:59:14.04$ifdk4/patch= 2006.257.23:59:14.04$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.257.23:59:14.04$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.257.23:59:14.04$setupk4/!*+20s 2006.257.23:59:16.75#abcon#<5=/02 2.0 5.3 21.30 791016.2\r\n> 2006.257.23:59:16.77#abcon#{5=INTERFACE CLEAR} 2006.257.23:59:16.83#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:59:26.92#abcon#<5=/02 2.0 5.3 21.31 791016.3\r\n> 2006.257.23:59:26.94#abcon#{5=INTERFACE CLEAR} 2006.257.23:59:27.00#abcon#[5=S1D000X0/0*\r\n] 2006.257.23:59:28.55$setupk4/"tpicd 2006.257.23:59:28.55$setupk4/echo=off 2006.257.23:59:28.55$setupk4/xlog=off 2006.257.23:59:28.55:!2006.258.00:01:08 2006.257.23:59:42.13#trakl#Source acquired 2006.257.23:59:44.13#flagr#flagr/antenna,acquired 2006.258.00:01:08.00:preob 2006.258.00:01:09.14/onsource/TRACKING 2006.258.00:01:09.14:!2006.258.00:01:18 2006.258.00:01:18.00:"tape 2006.258.00:01:18.00:"st=record 2006.258.00:01:18.00:data_valid=on 2006.258.00:01:18.00:midob 2006.258.00:01:18.14/onsource/TRACKING 2006.258.00:01:18.14/wx/21.34,1016.2,79 2006.258.00:01:18.19/cable/+6.4818E-03 2006.258.00:01:19.28/va/01,08,usb,yes,37,39 2006.258.00:01:19.28/va/02,07,usb,yes,40,40 2006.258.00:01:19.28/va/03,08,usb,yes,36,38 2006.258.00:01:19.28/va/04,07,usb,yes,41,43 2006.258.00:01:19.28/va/05,04,usb,yes,36,37 2006.258.00:01:19.28/va/06,04,usb,yes,40,40 2006.258.00:01:19.28/va/07,04,usb,yes,41,42 2006.258.00:01:19.28/va/08,04,usb,yes,35,42 2006.258.00:01:19.51/valo/01,524.99,yes,locked 2006.258.00:01:19.51/valo/02,534.99,yes,locked 2006.258.00:01:19.51/valo/03,564.99,yes,locked 2006.258.00:01:19.51/valo/04,624.99,yes,locked 2006.258.00:01:19.51/valo/05,734.99,yes,locked 2006.258.00:01:19.51/valo/06,814.99,yes,locked 2006.258.00:01:19.51/valo/07,864.99,yes,locked 2006.258.00:01:19.51/valo/08,884.99,yes,locked 2006.258.00:01:20.60/vb/01,04,usb,yes,33,31 2006.258.00:01:20.60/vb/02,05,usb,yes,31,31 2006.258.00:01:20.60/vb/03,04,usb,yes,32,36 2006.258.00:01:20.60/vb/04,05,usb,yes,33,32 2006.258.00:01:20.60/vb/05,04,usb,yes,29,32 2006.258.00:01:20.60/vb/06,04,usb,yes,34,30 2006.258.00:01:20.60/vb/07,04,usb,yes,34,34 2006.258.00:01:20.60/vb/08,04,usb,yes,31,35 2006.258.00:01:20.84/vblo/01,629.99,yes,locked 2006.258.00:01:20.84/vblo/02,634.99,yes,locked 2006.258.00:01:20.84/vblo/03,649.99,yes,locked 2006.258.00:01:20.84/vblo/04,679.99,yes,locked 2006.258.00:01:20.84/vblo/05,709.99,yes,locked 2006.258.00:01:20.84/vblo/06,719.99,yes,locked 2006.258.00:01:20.84/vblo/07,734.99,yes,locked 2006.258.00:01:20.84/vblo/08,744.99,yes,locked 2006.258.00:01:20.99/vabw/8 2006.258.00:01:21.14/vbbw/8 2006.258.00:01:21.23/xfe/off,on,15.0 2006.258.00:01:21.61/ifatt/23,28,28,28 2006.258.00:01:22.08/fmout-gps/S +4.54E-07 2006.258.00:01:22.12:!2006.258.00:01:58 2006.258.00:01:58.00:data_valid=off 2006.258.00:01:58.00:"et 2006.258.00:01:58.00:!+3s 2006.258.00:02:01.02:"tape 2006.258.00:02:01.02:postob 2006.258.00:02:01.21/cable/+6.4799E-03 2006.258.00:02:01.21/wx/21.39,1016.2,80 2006.258.00:02:02.08/fmout-gps/S +4.55E-07 2006.258.00:02:02.08:scan_name=258-0003,jd0609,50 2006.258.00:02:02.08:source=3c345,164258.81,394837.0,2000.0,cw 2006.258.00:02:03.14#flagr#flagr/antenna,new-source 2006.258.00:02:03.14:checkk5 2006.258.00:02:03.49/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:02:03.83/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:02:04.18/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:02:04.52/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:02:04.87/chk_obsdata//k5ts1/T2580001??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.258.00:02:05.22/chk_obsdata//k5ts2/T2580001??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.258.00:02:05.56/chk_obsdata//k5ts3/T2580001??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.258.00:02:05.90/chk_obsdata//k5ts4/T2580001??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.258.00:02:06.58/k5log//k5ts1_log_newline 2006.258.00:02:07.24/k5log//k5ts2_log_newline 2006.258.00:02:07.89/k5log//k5ts3_log_newline 2006.258.00:02:08.55/k5log//k5ts4_log_newline 2006.258.00:02:08.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:02:08.58:setupk4=1 2006.258.00:02:08.58$setupk4/echo=on 2006.258.00:02:08.58$setupk4/pcalon 2006.258.00:02:08.58$pcalon/"no phase cal control is implemented here 2006.258.00:02:08.58$setupk4/"tpicd=stop 2006.258.00:02:08.58$setupk4/"rec=synch_on 2006.258.00:02:08.58$setupk4/"rec_mode=128 2006.258.00:02:08.58$setupk4/!* 2006.258.00:02:08.58$setupk4/recpk4 2006.258.00:02:08.58$recpk4/recpatch= 2006.258.00:02:08.58$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:02:08.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:02:08.58$setupk4/vck44 2006.258.00:02:08.58$vck44/valo=1,524.99 2006.258.00:02:08.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.00:02:08.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.00:02:08.58#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:08.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:08.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:08.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:08.58#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:02:08.58#ibcon#first serial, iclass 20, count 0 2006.258.00:02:08.58#ibcon#enter sib2, iclass 20, count 0 2006.258.00:02:08.58#ibcon#flushed, iclass 20, count 0 2006.258.00:02:08.58#ibcon#about to write, iclass 20, count 0 2006.258.00:02:08.58#ibcon#wrote, iclass 20, count 0 2006.258.00:02:08.58#ibcon#about to read 3, iclass 20, count 0 2006.258.00:02:08.60#ibcon#read 3, iclass 20, count 0 2006.258.00:02:08.60#ibcon#about to read 4, iclass 20, count 0 2006.258.00:02:08.60#ibcon#read 4, iclass 20, count 0 2006.258.00:02:08.60#ibcon#about to read 5, iclass 20, count 0 2006.258.00:02:08.60#ibcon#read 5, iclass 20, count 0 2006.258.00:02:08.60#ibcon#about to read 6, iclass 20, count 0 2006.258.00:02:08.60#ibcon#read 6, iclass 20, count 0 2006.258.00:02:08.60#ibcon#end of sib2, iclass 20, count 0 2006.258.00:02:08.60#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:02:08.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:02:08.60#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:02:08.60#ibcon#*before write, iclass 20, count 0 2006.258.00:02:08.60#ibcon#enter sib2, iclass 20, count 0 2006.258.00:02:08.60#ibcon#flushed, iclass 20, count 0 2006.258.00:02:08.60#ibcon#about to write, iclass 20, count 0 2006.258.00:02:08.60#ibcon#wrote, iclass 20, count 0 2006.258.00:02:08.60#ibcon#about to read 3, iclass 20, count 0 2006.258.00:02:08.65#ibcon#read 3, iclass 20, count 0 2006.258.00:02:08.65#ibcon#about to read 4, iclass 20, count 0 2006.258.00:02:08.65#ibcon#read 4, iclass 20, count 0 2006.258.00:02:08.65#ibcon#about to read 5, iclass 20, count 0 2006.258.00:02:08.65#ibcon#read 5, iclass 20, count 0 2006.258.00:02:08.65#ibcon#about to read 6, iclass 20, count 0 2006.258.00:02:08.65#ibcon#read 6, iclass 20, count 0 2006.258.00:02:08.65#ibcon#end of sib2, iclass 20, count 0 2006.258.00:02:08.65#ibcon#*after write, iclass 20, count 0 2006.258.00:02:08.65#ibcon#*before return 0, iclass 20, count 0 2006.258.00:02:08.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:08.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:08.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:02:08.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:02:08.65$vck44/va=1,8 2006.258.00:02:08.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.00:02:08.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.00:02:08.65#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:08.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:08.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:08.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:08.65#ibcon#enter wrdev, iclass 22, count 2 2006.258.00:02:08.65#ibcon#first serial, iclass 22, count 2 2006.258.00:02:08.65#ibcon#enter sib2, iclass 22, count 2 2006.258.00:02:08.65#ibcon#flushed, iclass 22, count 2 2006.258.00:02:08.65#ibcon#about to write, iclass 22, count 2 2006.258.00:02:08.65#ibcon#wrote, iclass 22, count 2 2006.258.00:02:08.65#ibcon#about to read 3, iclass 22, count 2 2006.258.00:02:08.67#ibcon#read 3, iclass 22, count 2 2006.258.00:02:08.67#ibcon#about to read 4, iclass 22, count 2 2006.258.00:02:08.67#ibcon#read 4, iclass 22, count 2 2006.258.00:02:08.67#ibcon#about to read 5, iclass 22, count 2 2006.258.00:02:08.67#ibcon#read 5, iclass 22, count 2 2006.258.00:02:08.67#ibcon#about to read 6, iclass 22, count 2 2006.258.00:02:08.67#ibcon#read 6, iclass 22, count 2 2006.258.00:02:08.67#ibcon#end of sib2, iclass 22, count 2 2006.258.00:02:08.67#ibcon#*mode == 0, iclass 22, count 2 2006.258.00:02:08.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.00:02:08.67#ibcon#[25=AT01-08\r\n] 2006.258.00:02:08.67#ibcon#*before write, iclass 22, count 2 2006.258.00:02:08.67#ibcon#enter sib2, iclass 22, count 2 2006.258.00:02:08.67#ibcon#flushed, iclass 22, count 2 2006.258.00:02:08.67#ibcon#about to write, iclass 22, count 2 2006.258.00:02:08.67#ibcon#wrote, iclass 22, count 2 2006.258.00:02:08.67#ibcon#about to read 3, iclass 22, count 2 2006.258.00:02:08.70#ibcon#read 3, iclass 22, count 2 2006.258.00:02:08.70#ibcon#about to read 4, iclass 22, count 2 2006.258.00:02:08.70#ibcon#read 4, iclass 22, count 2 2006.258.00:02:08.70#ibcon#about to read 5, iclass 22, count 2 2006.258.00:02:08.70#ibcon#read 5, iclass 22, count 2 2006.258.00:02:08.70#ibcon#about to read 6, iclass 22, count 2 2006.258.00:02:08.70#ibcon#read 6, iclass 22, count 2 2006.258.00:02:08.70#ibcon#end of sib2, iclass 22, count 2 2006.258.00:02:08.70#ibcon#*after write, iclass 22, count 2 2006.258.00:02:08.70#ibcon#*before return 0, iclass 22, count 2 2006.258.00:02:08.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:08.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:08.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.00:02:08.70#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:08.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:08.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:08.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:08.82#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:02:08.82#ibcon#first serial, iclass 22, count 0 2006.258.00:02:08.82#ibcon#enter sib2, iclass 22, count 0 2006.258.00:02:08.82#ibcon#flushed, iclass 22, count 0 2006.258.00:02:08.82#ibcon#about to write, iclass 22, count 0 2006.258.00:02:08.82#ibcon#wrote, iclass 22, count 0 2006.258.00:02:08.82#ibcon#about to read 3, iclass 22, count 0 2006.258.00:02:08.84#ibcon#read 3, iclass 22, count 0 2006.258.00:02:08.84#ibcon#about to read 4, iclass 22, count 0 2006.258.00:02:08.84#ibcon#read 4, iclass 22, count 0 2006.258.00:02:08.84#ibcon#about to read 5, iclass 22, count 0 2006.258.00:02:08.84#ibcon#read 5, iclass 22, count 0 2006.258.00:02:08.84#ibcon#about to read 6, iclass 22, count 0 2006.258.00:02:08.84#ibcon#read 6, iclass 22, count 0 2006.258.00:02:08.84#ibcon#end of sib2, iclass 22, count 0 2006.258.00:02:08.84#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:02:08.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:02:08.84#ibcon#[25=USB\r\n] 2006.258.00:02:08.84#ibcon#*before write, iclass 22, count 0 2006.258.00:02:08.84#ibcon#enter sib2, iclass 22, count 0 2006.258.00:02:08.84#ibcon#flushed, iclass 22, count 0 2006.258.00:02:08.84#ibcon#about to write, iclass 22, count 0 2006.258.00:02:08.84#ibcon#wrote, iclass 22, count 0 2006.258.00:02:08.84#ibcon#about to read 3, iclass 22, count 0 2006.258.00:02:08.87#ibcon#read 3, iclass 22, count 0 2006.258.00:02:08.87#ibcon#about to read 4, iclass 22, count 0 2006.258.00:02:08.87#ibcon#read 4, iclass 22, count 0 2006.258.00:02:08.87#ibcon#about to read 5, iclass 22, count 0 2006.258.00:02:08.87#ibcon#read 5, iclass 22, count 0 2006.258.00:02:08.87#ibcon#about to read 6, iclass 22, count 0 2006.258.00:02:08.87#ibcon#read 6, iclass 22, count 0 2006.258.00:02:08.87#ibcon#end of sib2, iclass 22, count 0 2006.258.00:02:08.87#ibcon#*after write, iclass 22, count 0 2006.258.00:02:08.87#ibcon#*before return 0, iclass 22, count 0 2006.258.00:02:08.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:08.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:08.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:02:08.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:02:08.87$vck44/valo=2,534.99 2006.258.00:02:08.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.00:02:08.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.00:02:08.87#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:08.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:08.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:08.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:08.87#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:02:08.87#ibcon#first serial, iclass 24, count 0 2006.258.00:02:08.87#ibcon#enter sib2, iclass 24, count 0 2006.258.00:02:08.87#ibcon#flushed, iclass 24, count 0 2006.258.00:02:08.87#ibcon#about to write, iclass 24, count 0 2006.258.00:02:08.87#ibcon#wrote, iclass 24, count 0 2006.258.00:02:08.87#ibcon#about to read 3, iclass 24, count 0 2006.258.00:02:08.89#ibcon#read 3, iclass 24, count 0 2006.258.00:02:08.89#ibcon#about to read 4, iclass 24, count 0 2006.258.00:02:08.89#ibcon#read 4, iclass 24, count 0 2006.258.00:02:08.89#ibcon#about to read 5, iclass 24, count 0 2006.258.00:02:08.89#ibcon#read 5, iclass 24, count 0 2006.258.00:02:08.89#ibcon#about to read 6, iclass 24, count 0 2006.258.00:02:08.89#ibcon#read 6, iclass 24, count 0 2006.258.00:02:08.89#ibcon#end of sib2, iclass 24, count 0 2006.258.00:02:08.89#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:02:08.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:02:08.89#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:02:08.89#ibcon#*before write, iclass 24, count 0 2006.258.00:02:08.89#ibcon#enter sib2, iclass 24, count 0 2006.258.00:02:08.89#ibcon#flushed, iclass 24, count 0 2006.258.00:02:08.89#ibcon#about to write, iclass 24, count 0 2006.258.00:02:08.89#ibcon#wrote, iclass 24, count 0 2006.258.00:02:08.89#ibcon#about to read 3, iclass 24, count 0 2006.258.00:02:08.93#ibcon#read 3, iclass 24, count 0 2006.258.00:02:08.93#ibcon#about to read 4, iclass 24, count 0 2006.258.00:02:08.93#ibcon#read 4, iclass 24, count 0 2006.258.00:02:08.93#ibcon#about to read 5, iclass 24, count 0 2006.258.00:02:08.93#ibcon#read 5, iclass 24, count 0 2006.258.00:02:08.93#ibcon#about to read 6, iclass 24, count 0 2006.258.00:02:08.93#ibcon#read 6, iclass 24, count 0 2006.258.00:02:08.93#ibcon#end of sib2, iclass 24, count 0 2006.258.00:02:08.93#ibcon#*after write, iclass 24, count 0 2006.258.00:02:08.93#ibcon#*before return 0, iclass 24, count 0 2006.258.00:02:08.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:08.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:08.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:02:08.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:02:08.93$vck44/va=2,7 2006.258.00:02:08.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.00:02:08.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.00:02:08.93#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:08.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:08.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:08.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:08.99#ibcon#enter wrdev, iclass 26, count 2 2006.258.00:02:08.99#ibcon#first serial, iclass 26, count 2 2006.258.00:02:08.99#ibcon#enter sib2, iclass 26, count 2 2006.258.00:02:08.99#ibcon#flushed, iclass 26, count 2 2006.258.00:02:08.99#ibcon#about to write, iclass 26, count 2 2006.258.00:02:08.99#ibcon#wrote, iclass 26, count 2 2006.258.00:02:08.99#ibcon#about to read 3, iclass 26, count 2 2006.258.00:02:09.01#ibcon#read 3, iclass 26, count 2 2006.258.00:02:09.01#ibcon#about to read 4, iclass 26, count 2 2006.258.00:02:09.01#ibcon#read 4, iclass 26, count 2 2006.258.00:02:09.01#ibcon#about to read 5, iclass 26, count 2 2006.258.00:02:09.01#ibcon#read 5, iclass 26, count 2 2006.258.00:02:09.01#ibcon#about to read 6, iclass 26, count 2 2006.258.00:02:09.01#ibcon#read 6, iclass 26, count 2 2006.258.00:02:09.01#ibcon#end of sib2, iclass 26, count 2 2006.258.00:02:09.01#ibcon#*mode == 0, iclass 26, count 2 2006.258.00:02:09.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.00:02:09.01#ibcon#[25=AT02-07\r\n] 2006.258.00:02:09.01#ibcon#*before write, iclass 26, count 2 2006.258.00:02:09.01#ibcon#enter sib2, iclass 26, count 2 2006.258.00:02:09.01#ibcon#flushed, iclass 26, count 2 2006.258.00:02:09.01#ibcon#about to write, iclass 26, count 2 2006.258.00:02:09.01#ibcon#wrote, iclass 26, count 2 2006.258.00:02:09.01#ibcon#about to read 3, iclass 26, count 2 2006.258.00:02:09.04#ibcon#read 3, iclass 26, count 2 2006.258.00:02:09.04#ibcon#about to read 4, iclass 26, count 2 2006.258.00:02:09.04#ibcon#read 4, iclass 26, count 2 2006.258.00:02:09.04#ibcon#about to read 5, iclass 26, count 2 2006.258.00:02:09.04#ibcon#read 5, iclass 26, count 2 2006.258.00:02:09.04#ibcon#about to read 6, iclass 26, count 2 2006.258.00:02:09.04#ibcon#read 6, iclass 26, count 2 2006.258.00:02:09.04#ibcon#end of sib2, iclass 26, count 2 2006.258.00:02:09.04#ibcon#*after write, iclass 26, count 2 2006.258.00:02:09.04#ibcon#*before return 0, iclass 26, count 2 2006.258.00:02:09.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:09.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:09.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.00:02:09.04#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:09.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:09.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:09.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:09.16#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:02:09.16#ibcon#first serial, iclass 26, count 0 2006.258.00:02:09.16#ibcon#enter sib2, iclass 26, count 0 2006.258.00:02:09.16#ibcon#flushed, iclass 26, count 0 2006.258.00:02:09.16#ibcon#about to write, iclass 26, count 0 2006.258.00:02:09.16#ibcon#wrote, iclass 26, count 0 2006.258.00:02:09.16#ibcon#about to read 3, iclass 26, count 0 2006.258.00:02:09.18#ibcon#read 3, iclass 26, count 0 2006.258.00:02:09.18#ibcon#about to read 4, iclass 26, count 0 2006.258.00:02:09.18#ibcon#read 4, iclass 26, count 0 2006.258.00:02:09.18#ibcon#about to read 5, iclass 26, count 0 2006.258.00:02:09.18#ibcon#read 5, iclass 26, count 0 2006.258.00:02:09.18#ibcon#about to read 6, iclass 26, count 0 2006.258.00:02:09.18#ibcon#read 6, iclass 26, count 0 2006.258.00:02:09.18#ibcon#end of sib2, iclass 26, count 0 2006.258.00:02:09.18#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:02:09.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:02:09.18#ibcon#[25=USB\r\n] 2006.258.00:02:09.18#ibcon#*before write, iclass 26, count 0 2006.258.00:02:09.18#ibcon#enter sib2, iclass 26, count 0 2006.258.00:02:09.18#ibcon#flushed, iclass 26, count 0 2006.258.00:02:09.18#ibcon#about to write, iclass 26, count 0 2006.258.00:02:09.18#ibcon#wrote, iclass 26, count 0 2006.258.00:02:09.18#ibcon#about to read 3, iclass 26, count 0 2006.258.00:02:09.21#ibcon#read 3, iclass 26, count 0 2006.258.00:02:09.21#ibcon#about to read 4, iclass 26, count 0 2006.258.00:02:09.21#ibcon#read 4, iclass 26, count 0 2006.258.00:02:09.21#ibcon#about to read 5, iclass 26, count 0 2006.258.00:02:09.21#ibcon#read 5, iclass 26, count 0 2006.258.00:02:09.21#ibcon#about to read 6, iclass 26, count 0 2006.258.00:02:09.21#ibcon#read 6, iclass 26, count 0 2006.258.00:02:09.21#ibcon#end of sib2, iclass 26, count 0 2006.258.00:02:09.21#ibcon#*after write, iclass 26, count 0 2006.258.00:02:09.21#ibcon#*before return 0, iclass 26, count 0 2006.258.00:02:09.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:09.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:09.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:02:09.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:02:09.21$vck44/valo=3,564.99 2006.258.00:02:09.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.00:02:09.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.00:02:09.21#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:09.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:09.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:09.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:09.21#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:02:09.21#ibcon#first serial, iclass 28, count 0 2006.258.00:02:09.21#ibcon#enter sib2, iclass 28, count 0 2006.258.00:02:09.21#ibcon#flushed, iclass 28, count 0 2006.258.00:02:09.21#ibcon#about to write, iclass 28, count 0 2006.258.00:02:09.21#ibcon#wrote, iclass 28, count 0 2006.258.00:02:09.21#ibcon#about to read 3, iclass 28, count 0 2006.258.00:02:09.23#ibcon#read 3, iclass 28, count 0 2006.258.00:02:09.23#ibcon#about to read 4, iclass 28, count 0 2006.258.00:02:09.23#ibcon#read 4, iclass 28, count 0 2006.258.00:02:09.23#ibcon#about to read 5, iclass 28, count 0 2006.258.00:02:09.23#ibcon#read 5, iclass 28, count 0 2006.258.00:02:09.23#ibcon#about to read 6, iclass 28, count 0 2006.258.00:02:09.23#ibcon#read 6, iclass 28, count 0 2006.258.00:02:09.23#ibcon#end of sib2, iclass 28, count 0 2006.258.00:02:09.23#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:02:09.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:02:09.23#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:02:09.23#ibcon#*before write, iclass 28, count 0 2006.258.00:02:09.23#ibcon#enter sib2, iclass 28, count 0 2006.258.00:02:09.23#ibcon#flushed, iclass 28, count 0 2006.258.00:02:09.23#ibcon#about to write, iclass 28, count 0 2006.258.00:02:09.23#ibcon#wrote, iclass 28, count 0 2006.258.00:02:09.23#ibcon#about to read 3, iclass 28, count 0 2006.258.00:02:09.27#ibcon#read 3, iclass 28, count 0 2006.258.00:02:09.27#ibcon#about to read 4, iclass 28, count 0 2006.258.00:02:09.27#ibcon#read 4, iclass 28, count 0 2006.258.00:02:09.27#ibcon#about to read 5, iclass 28, count 0 2006.258.00:02:09.27#ibcon#read 5, iclass 28, count 0 2006.258.00:02:09.27#ibcon#about to read 6, iclass 28, count 0 2006.258.00:02:09.27#ibcon#read 6, iclass 28, count 0 2006.258.00:02:09.27#ibcon#end of sib2, iclass 28, count 0 2006.258.00:02:09.27#ibcon#*after write, iclass 28, count 0 2006.258.00:02:09.27#ibcon#*before return 0, iclass 28, count 0 2006.258.00:02:09.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:09.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:09.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:02:09.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:02:09.27$vck44/va=3,8 2006.258.00:02:09.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.00:02:09.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.00:02:09.27#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:09.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:09.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:09.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:09.33#ibcon#enter wrdev, iclass 30, count 2 2006.258.00:02:09.33#ibcon#first serial, iclass 30, count 2 2006.258.00:02:09.33#ibcon#enter sib2, iclass 30, count 2 2006.258.00:02:09.33#ibcon#flushed, iclass 30, count 2 2006.258.00:02:09.33#ibcon#about to write, iclass 30, count 2 2006.258.00:02:09.33#ibcon#wrote, iclass 30, count 2 2006.258.00:02:09.33#ibcon#about to read 3, iclass 30, count 2 2006.258.00:02:09.35#ibcon#read 3, iclass 30, count 2 2006.258.00:02:09.35#ibcon#about to read 4, iclass 30, count 2 2006.258.00:02:09.35#ibcon#read 4, iclass 30, count 2 2006.258.00:02:09.35#ibcon#about to read 5, iclass 30, count 2 2006.258.00:02:09.35#ibcon#read 5, iclass 30, count 2 2006.258.00:02:09.35#ibcon#about to read 6, iclass 30, count 2 2006.258.00:02:09.35#ibcon#read 6, iclass 30, count 2 2006.258.00:02:09.35#ibcon#end of sib2, iclass 30, count 2 2006.258.00:02:09.35#ibcon#*mode == 0, iclass 30, count 2 2006.258.00:02:09.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.00:02:09.35#ibcon#[25=AT03-08\r\n] 2006.258.00:02:09.35#ibcon#*before write, iclass 30, count 2 2006.258.00:02:09.35#ibcon#enter sib2, iclass 30, count 2 2006.258.00:02:09.35#ibcon#flushed, iclass 30, count 2 2006.258.00:02:09.35#ibcon#about to write, iclass 30, count 2 2006.258.00:02:09.35#ibcon#wrote, iclass 30, count 2 2006.258.00:02:09.35#ibcon#about to read 3, iclass 30, count 2 2006.258.00:02:09.38#ibcon#read 3, iclass 30, count 2 2006.258.00:02:09.38#ibcon#about to read 4, iclass 30, count 2 2006.258.00:02:09.38#ibcon#read 4, iclass 30, count 2 2006.258.00:02:09.38#ibcon#about to read 5, iclass 30, count 2 2006.258.00:02:09.38#ibcon#read 5, iclass 30, count 2 2006.258.00:02:09.38#ibcon#about to read 6, iclass 30, count 2 2006.258.00:02:09.38#ibcon#read 6, iclass 30, count 2 2006.258.00:02:09.38#ibcon#end of sib2, iclass 30, count 2 2006.258.00:02:09.38#ibcon#*after write, iclass 30, count 2 2006.258.00:02:09.38#ibcon#*before return 0, iclass 30, count 2 2006.258.00:02:09.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:09.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:09.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.00:02:09.38#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:09.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:09.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:09.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:09.50#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:02:09.50#ibcon#first serial, iclass 30, count 0 2006.258.00:02:09.50#ibcon#enter sib2, iclass 30, count 0 2006.258.00:02:09.50#ibcon#flushed, iclass 30, count 0 2006.258.00:02:09.50#ibcon#about to write, iclass 30, count 0 2006.258.00:02:09.50#ibcon#wrote, iclass 30, count 0 2006.258.00:02:09.50#ibcon#about to read 3, iclass 30, count 0 2006.258.00:02:09.52#ibcon#read 3, iclass 30, count 0 2006.258.00:02:09.52#ibcon#about to read 4, iclass 30, count 0 2006.258.00:02:09.52#ibcon#read 4, iclass 30, count 0 2006.258.00:02:09.52#ibcon#about to read 5, iclass 30, count 0 2006.258.00:02:09.52#ibcon#read 5, iclass 30, count 0 2006.258.00:02:09.52#ibcon#about to read 6, iclass 30, count 0 2006.258.00:02:09.52#ibcon#read 6, iclass 30, count 0 2006.258.00:02:09.52#ibcon#end of sib2, iclass 30, count 0 2006.258.00:02:09.52#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:02:09.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:02:09.52#ibcon#[25=USB\r\n] 2006.258.00:02:09.52#ibcon#*before write, iclass 30, count 0 2006.258.00:02:09.52#ibcon#enter sib2, iclass 30, count 0 2006.258.00:02:09.52#ibcon#flushed, iclass 30, count 0 2006.258.00:02:09.52#ibcon#about to write, iclass 30, count 0 2006.258.00:02:09.52#ibcon#wrote, iclass 30, count 0 2006.258.00:02:09.52#ibcon#about to read 3, iclass 30, count 0 2006.258.00:02:09.55#ibcon#read 3, iclass 30, count 0 2006.258.00:02:09.55#ibcon#about to read 4, iclass 30, count 0 2006.258.00:02:09.55#ibcon#read 4, iclass 30, count 0 2006.258.00:02:09.55#ibcon#about to read 5, iclass 30, count 0 2006.258.00:02:09.55#ibcon#read 5, iclass 30, count 0 2006.258.00:02:09.55#ibcon#about to read 6, iclass 30, count 0 2006.258.00:02:09.55#ibcon#read 6, iclass 30, count 0 2006.258.00:02:09.55#ibcon#end of sib2, iclass 30, count 0 2006.258.00:02:09.55#ibcon#*after write, iclass 30, count 0 2006.258.00:02:09.55#ibcon#*before return 0, iclass 30, count 0 2006.258.00:02:09.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:09.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:09.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:02:09.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:02:09.55$vck44/valo=4,624.99 2006.258.00:02:09.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.258.00:02:09.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.258.00:02:09.55#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:09.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:02:09.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:02:09.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:02:09.55#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:02:09.55#ibcon#first serial, iclass 32, count 0 2006.258.00:02:09.55#ibcon#enter sib2, iclass 32, count 0 2006.258.00:02:09.55#ibcon#flushed, iclass 32, count 0 2006.258.00:02:09.55#ibcon#about to write, iclass 32, count 0 2006.258.00:02:09.55#ibcon#wrote, iclass 32, count 0 2006.258.00:02:09.55#ibcon#about to read 3, iclass 32, count 0 2006.258.00:02:09.57#ibcon#read 3, iclass 32, count 0 2006.258.00:02:09.57#ibcon#about to read 4, iclass 32, count 0 2006.258.00:02:09.57#ibcon#read 4, iclass 32, count 0 2006.258.00:02:09.57#ibcon#about to read 5, iclass 32, count 0 2006.258.00:02:09.57#ibcon#read 5, iclass 32, count 0 2006.258.00:02:09.57#ibcon#about to read 6, iclass 32, count 0 2006.258.00:02:09.57#ibcon#read 6, iclass 32, count 0 2006.258.00:02:09.57#ibcon#end of sib2, iclass 32, count 0 2006.258.00:02:09.57#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:02:09.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:02:09.57#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:02:09.57#ibcon#*before write, iclass 32, count 0 2006.258.00:02:09.57#ibcon#enter sib2, iclass 32, count 0 2006.258.00:02:09.57#ibcon#flushed, iclass 32, count 0 2006.258.00:02:09.57#ibcon#about to write, iclass 32, count 0 2006.258.00:02:09.57#ibcon#wrote, iclass 32, count 0 2006.258.00:02:09.57#ibcon#about to read 3, iclass 32, count 0 2006.258.00:02:09.61#ibcon#read 3, iclass 32, count 0 2006.258.00:02:09.61#ibcon#about to read 4, iclass 32, count 0 2006.258.00:02:09.61#ibcon#read 4, iclass 32, count 0 2006.258.00:02:09.61#ibcon#about to read 5, iclass 32, count 0 2006.258.00:02:09.61#ibcon#read 5, iclass 32, count 0 2006.258.00:02:09.61#ibcon#about to read 6, iclass 32, count 0 2006.258.00:02:09.61#ibcon#read 6, iclass 32, count 0 2006.258.00:02:09.61#ibcon#end of sib2, iclass 32, count 0 2006.258.00:02:09.61#ibcon#*after write, iclass 32, count 0 2006.258.00:02:09.61#ibcon#*before return 0, iclass 32, count 0 2006.258.00:02:09.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:02:09.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:02:09.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:02:09.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:02:09.61$vck44/va=4,7 2006.258.00:02:09.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.258.00:02:09.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.258.00:02:09.61#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:09.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:02:09.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:02:09.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:02:09.67#ibcon#enter wrdev, iclass 34, count 2 2006.258.00:02:09.67#ibcon#first serial, iclass 34, count 2 2006.258.00:02:09.67#ibcon#enter sib2, iclass 34, count 2 2006.258.00:02:09.67#ibcon#flushed, iclass 34, count 2 2006.258.00:02:09.67#ibcon#about to write, iclass 34, count 2 2006.258.00:02:09.67#ibcon#wrote, iclass 34, count 2 2006.258.00:02:09.67#ibcon#about to read 3, iclass 34, count 2 2006.258.00:02:09.69#ibcon#read 3, iclass 34, count 2 2006.258.00:02:09.69#ibcon#about to read 4, iclass 34, count 2 2006.258.00:02:09.69#ibcon#read 4, iclass 34, count 2 2006.258.00:02:09.69#ibcon#about to read 5, iclass 34, count 2 2006.258.00:02:09.69#ibcon#read 5, iclass 34, count 2 2006.258.00:02:09.69#ibcon#about to read 6, iclass 34, count 2 2006.258.00:02:09.69#ibcon#read 6, iclass 34, count 2 2006.258.00:02:09.69#ibcon#end of sib2, iclass 34, count 2 2006.258.00:02:09.69#ibcon#*mode == 0, iclass 34, count 2 2006.258.00:02:09.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.258.00:02:09.69#ibcon#[25=AT04-07\r\n] 2006.258.00:02:09.69#ibcon#*before write, iclass 34, count 2 2006.258.00:02:09.69#ibcon#enter sib2, iclass 34, count 2 2006.258.00:02:09.69#ibcon#flushed, iclass 34, count 2 2006.258.00:02:09.69#ibcon#about to write, iclass 34, count 2 2006.258.00:02:09.69#ibcon#wrote, iclass 34, count 2 2006.258.00:02:09.69#ibcon#about to read 3, iclass 34, count 2 2006.258.00:02:09.72#ibcon#read 3, iclass 34, count 2 2006.258.00:02:09.72#ibcon#about to read 4, iclass 34, count 2 2006.258.00:02:09.72#ibcon#read 4, iclass 34, count 2 2006.258.00:02:09.72#ibcon#about to read 5, iclass 34, count 2 2006.258.00:02:09.72#ibcon#read 5, iclass 34, count 2 2006.258.00:02:09.72#ibcon#about to read 6, iclass 34, count 2 2006.258.00:02:09.72#ibcon#read 6, iclass 34, count 2 2006.258.00:02:09.72#ibcon#end of sib2, iclass 34, count 2 2006.258.00:02:09.72#ibcon#*after write, iclass 34, count 2 2006.258.00:02:09.72#ibcon#*before return 0, iclass 34, count 2 2006.258.00:02:09.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:02:09.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:02:09.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.258.00:02:09.72#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:09.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:02:09.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:02:09.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:02:09.84#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:02:09.84#ibcon#first serial, iclass 34, count 0 2006.258.00:02:09.84#ibcon#enter sib2, iclass 34, count 0 2006.258.00:02:09.84#ibcon#flushed, iclass 34, count 0 2006.258.00:02:09.84#ibcon#about to write, iclass 34, count 0 2006.258.00:02:09.84#ibcon#wrote, iclass 34, count 0 2006.258.00:02:09.84#ibcon#about to read 3, iclass 34, count 0 2006.258.00:02:09.86#ibcon#read 3, iclass 34, count 0 2006.258.00:02:09.86#ibcon#about to read 4, iclass 34, count 0 2006.258.00:02:09.86#ibcon#read 4, iclass 34, count 0 2006.258.00:02:09.86#ibcon#about to read 5, iclass 34, count 0 2006.258.00:02:09.86#ibcon#read 5, iclass 34, count 0 2006.258.00:02:09.86#ibcon#about to read 6, iclass 34, count 0 2006.258.00:02:09.86#ibcon#read 6, iclass 34, count 0 2006.258.00:02:09.86#ibcon#end of sib2, iclass 34, count 0 2006.258.00:02:09.86#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:02:09.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:02:09.86#ibcon#[25=USB\r\n] 2006.258.00:02:09.86#ibcon#*before write, iclass 34, count 0 2006.258.00:02:09.86#ibcon#enter sib2, iclass 34, count 0 2006.258.00:02:09.86#ibcon#flushed, iclass 34, count 0 2006.258.00:02:09.86#ibcon#about to write, iclass 34, count 0 2006.258.00:02:09.86#ibcon#wrote, iclass 34, count 0 2006.258.00:02:09.86#ibcon#about to read 3, iclass 34, count 0 2006.258.00:02:09.89#ibcon#read 3, iclass 34, count 0 2006.258.00:02:09.89#ibcon#about to read 4, iclass 34, count 0 2006.258.00:02:09.89#ibcon#read 4, iclass 34, count 0 2006.258.00:02:09.89#ibcon#about to read 5, iclass 34, count 0 2006.258.00:02:09.89#ibcon#read 5, iclass 34, count 0 2006.258.00:02:09.89#ibcon#about to read 6, iclass 34, count 0 2006.258.00:02:09.89#ibcon#read 6, iclass 34, count 0 2006.258.00:02:09.89#ibcon#end of sib2, iclass 34, count 0 2006.258.00:02:09.89#ibcon#*after write, iclass 34, count 0 2006.258.00:02:09.89#ibcon#*before return 0, iclass 34, count 0 2006.258.00:02:09.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:02:09.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:02:09.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:02:09.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:02:09.89$vck44/valo=5,734.99 2006.258.00:02:09.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.258.00:02:09.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.258.00:02:09.89#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:09.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:02:09.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:02:09.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:02:09.89#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:02:09.89#ibcon#first serial, iclass 36, count 0 2006.258.00:02:09.89#ibcon#enter sib2, iclass 36, count 0 2006.258.00:02:09.89#ibcon#flushed, iclass 36, count 0 2006.258.00:02:09.89#ibcon#about to write, iclass 36, count 0 2006.258.00:02:09.89#ibcon#wrote, iclass 36, count 0 2006.258.00:02:09.89#ibcon#about to read 3, iclass 36, count 0 2006.258.00:02:09.91#ibcon#read 3, iclass 36, count 0 2006.258.00:02:09.91#ibcon#about to read 4, iclass 36, count 0 2006.258.00:02:09.91#ibcon#read 4, iclass 36, count 0 2006.258.00:02:09.91#ibcon#about to read 5, iclass 36, count 0 2006.258.00:02:09.91#ibcon#read 5, iclass 36, count 0 2006.258.00:02:09.91#ibcon#about to read 6, iclass 36, count 0 2006.258.00:02:09.91#ibcon#read 6, iclass 36, count 0 2006.258.00:02:09.91#ibcon#end of sib2, iclass 36, count 0 2006.258.00:02:09.91#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:02:09.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:02:09.91#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:02:09.91#ibcon#*before write, iclass 36, count 0 2006.258.00:02:09.91#ibcon#enter sib2, iclass 36, count 0 2006.258.00:02:09.91#ibcon#flushed, iclass 36, count 0 2006.258.00:02:09.91#ibcon#about to write, iclass 36, count 0 2006.258.00:02:09.91#ibcon#wrote, iclass 36, count 0 2006.258.00:02:09.91#ibcon#about to read 3, iclass 36, count 0 2006.258.00:02:09.95#ibcon#read 3, iclass 36, count 0 2006.258.00:02:09.95#ibcon#about to read 4, iclass 36, count 0 2006.258.00:02:09.95#ibcon#read 4, iclass 36, count 0 2006.258.00:02:09.95#ibcon#about to read 5, iclass 36, count 0 2006.258.00:02:09.95#ibcon#read 5, iclass 36, count 0 2006.258.00:02:09.95#ibcon#about to read 6, iclass 36, count 0 2006.258.00:02:09.95#ibcon#read 6, iclass 36, count 0 2006.258.00:02:09.95#ibcon#end of sib2, iclass 36, count 0 2006.258.00:02:09.95#ibcon#*after write, iclass 36, count 0 2006.258.00:02:09.95#ibcon#*before return 0, iclass 36, count 0 2006.258.00:02:09.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:02:09.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:02:09.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:02:09.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:02:09.95$vck44/va=5,4 2006.258.00:02:09.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.258.00:02:09.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.258.00:02:09.95#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:09.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:10.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:10.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:10.01#ibcon#enter wrdev, iclass 38, count 2 2006.258.00:02:10.01#ibcon#first serial, iclass 38, count 2 2006.258.00:02:10.01#ibcon#enter sib2, iclass 38, count 2 2006.258.00:02:10.01#ibcon#flushed, iclass 38, count 2 2006.258.00:02:10.01#ibcon#about to write, iclass 38, count 2 2006.258.00:02:10.01#ibcon#wrote, iclass 38, count 2 2006.258.00:02:10.01#ibcon#about to read 3, iclass 38, count 2 2006.258.00:02:10.03#ibcon#read 3, iclass 38, count 2 2006.258.00:02:10.03#ibcon#about to read 4, iclass 38, count 2 2006.258.00:02:10.03#ibcon#read 4, iclass 38, count 2 2006.258.00:02:10.03#ibcon#about to read 5, iclass 38, count 2 2006.258.00:02:10.03#ibcon#read 5, iclass 38, count 2 2006.258.00:02:10.03#ibcon#about to read 6, iclass 38, count 2 2006.258.00:02:10.03#ibcon#read 6, iclass 38, count 2 2006.258.00:02:10.03#ibcon#end of sib2, iclass 38, count 2 2006.258.00:02:10.03#ibcon#*mode == 0, iclass 38, count 2 2006.258.00:02:10.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.258.00:02:10.03#ibcon#[25=AT05-04\r\n] 2006.258.00:02:10.03#ibcon#*before write, iclass 38, count 2 2006.258.00:02:10.03#ibcon#enter sib2, iclass 38, count 2 2006.258.00:02:10.03#ibcon#flushed, iclass 38, count 2 2006.258.00:02:10.03#ibcon#about to write, iclass 38, count 2 2006.258.00:02:10.03#ibcon#wrote, iclass 38, count 2 2006.258.00:02:10.03#ibcon#about to read 3, iclass 38, count 2 2006.258.00:02:10.06#ibcon#read 3, iclass 38, count 2 2006.258.00:02:10.06#ibcon#about to read 4, iclass 38, count 2 2006.258.00:02:10.06#ibcon#read 4, iclass 38, count 2 2006.258.00:02:10.06#ibcon#about to read 5, iclass 38, count 2 2006.258.00:02:10.06#ibcon#read 5, iclass 38, count 2 2006.258.00:02:10.06#ibcon#about to read 6, iclass 38, count 2 2006.258.00:02:10.06#ibcon#read 6, iclass 38, count 2 2006.258.00:02:10.06#ibcon#end of sib2, iclass 38, count 2 2006.258.00:02:10.06#ibcon#*after write, iclass 38, count 2 2006.258.00:02:10.06#ibcon#*before return 0, iclass 38, count 2 2006.258.00:02:10.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:10.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:10.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.258.00:02:10.06#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:10.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:10.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:10.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:10.18#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:02:10.18#ibcon#first serial, iclass 38, count 0 2006.258.00:02:10.18#ibcon#enter sib2, iclass 38, count 0 2006.258.00:02:10.18#ibcon#flushed, iclass 38, count 0 2006.258.00:02:10.18#ibcon#about to write, iclass 38, count 0 2006.258.00:02:10.18#ibcon#wrote, iclass 38, count 0 2006.258.00:02:10.18#ibcon#about to read 3, iclass 38, count 0 2006.258.00:02:10.20#ibcon#read 3, iclass 38, count 0 2006.258.00:02:10.20#ibcon#about to read 4, iclass 38, count 0 2006.258.00:02:10.20#ibcon#read 4, iclass 38, count 0 2006.258.00:02:10.20#ibcon#about to read 5, iclass 38, count 0 2006.258.00:02:10.20#ibcon#read 5, iclass 38, count 0 2006.258.00:02:10.20#ibcon#about to read 6, iclass 38, count 0 2006.258.00:02:10.20#ibcon#read 6, iclass 38, count 0 2006.258.00:02:10.20#ibcon#end of sib2, iclass 38, count 0 2006.258.00:02:10.20#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:02:10.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:02:10.20#ibcon#[25=USB\r\n] 2006.258.00:02:10.20#ibcon#*before write, iclass 38, count 0 2006.258.00:02:10.20#ibcon#enter sib2, iclass 38, count 0 2006.258.00:02:10.20#ibcon#flushed, iclass 38, count 0 2006.258.00:02:10.20#ibcon#about to write, iclass 38, count 0 2006.258.00:02:10.20#ibcon#wrote, iclass 38, count 0 2006.258.00:02:10.20#ibcon#about to read 3, iclass 38, count 0 2006.258.00:02:10.23#ibcon#read 3, iclass 38, count 0 2006.258.00:02:10.23#ibcon#about to read 4, iclass 38, count 0 2006.258.00:02:10.23#ibcon#read 4, iclass 38, count 0 2006.258.00:02:10.23#ibcon#about to read 5, iclass 38, count 0 2006.258.00:02:10.23#ibcon#read 5, iclass 38, count 0 2006.258.00:02:10.23#ibcon#about to read 6, iclass 38, count 0 2006.258.00:02:10.23#ibcon#read 6, iclass 38, count 0 2006.258.00:02:10.23#ibcon#end of sib2, iclass 38, count 0 2006.258.00:02:10.23#ibcon#*after write, iclass 38, count 0 2006.258.00:02:10.23#ibcon#*before return 0, iclass 38, count 0 2006.258.00:02:10.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:10.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:10.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:02:10.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:02:10.23$vck44/valo=6,814.99 2006.258.00:02:10.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.00:02:10.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.00:02:10.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:10.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:10.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:10.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:10.23#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:02:10.23#ibcon#first serial, iclass 40, count 0 2006.258.00:02:10.23#ibcon#enter sib2, iclass 40, count 0 2006.258.00:02:10.23#ibcon#flushed, iclass 40, count 0 2006.258.00:02:10.23#ibcon#about to write, iclass 40, count 0 2006.258.00:02:10.23#ibcon#wrote, iclass 40, count 0 2006.258.00:02:10.23#ibcon#about to read 3, iclass 40, count 0 2006.258.00:02:10.25#ibcon#read 3, iclass 40, count 0 2006.258.00:02:10.25#ibcon#about to read 4, iclass 40, count 0 2006.258.00:02:10.25#ibcon#read 4, iclass 40, count 0 2006.258.00:02:10.25#ibcon#about to read 5, iclass 40, count 0 2006.258.00:02:10.25#ibcon#read 5, iclass 40, count 0 2006.258.00:02:10.25#ibcon#about to read 6, iclass 40, count 0 2006.258.00:02:10.25#ibcon#read 6, iclass 40, count 0 2006.258.00:02:10.25#ibcon#end of sib2, iclass 40, count 0 2006.258.00:02:10.25#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:02:10.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:02:10.25#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:02:10.25#ibcon#*before write, iclass 40, count 0 2006.258.00:02:10.25#ibcon#enter sib2, iclass 40, count 0 2006.258.00:02:10.25#ibcon#flushed, iclass 40, count 0 2006.258.00:02:10.25#ibcon#about to write, iclass 40, count 0 2006.258.00:02:10.25#ibcon#wrote, iclass 40, count 0 2006.258.00:02:10.25#ibcon#about to read 3, iclass 40, count 0 2006.258.00:02:10.29#ibcon#read 3, iclass 40, count 0 2006.258.00:02:10.29#ibcon#about to read 4, iclass 40, count 0 2006.258.00:02:10.29#ibcon#read 4, iclass 40, count 0 2006.258.00:02:10.29#ibcon#about to read 5, iclass 40, count 0 2006.258.00:02:10.29#ibcon#read 5, iclass 40, count 0 2006.258.00:02:10.29#ibcon#about to read 6, iclass 40, count 0 2006.258.00:02:10.29#ibcon#read 6, iclass 40, count 0 2006.258.00:02:10.29#ibcon#end of sib2, iclass 40, count 0 2006.258.00:02:10.29#ibcon#*after write, iclass 40, count 0 2006.258.00:02:10.29#ibcon#*before return 0, iclass 40, count 0 2006.258.00:02:10.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:10.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:10.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:02:10.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:02:10.29$vck44/va=6,4 2006.258.00:02:10.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.258.00:02:10.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.258.00:02:10.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:10.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:10.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:10.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:10.35#ibcon#enter wrdev, iclass 4, count 2 2006.258.00:02:10.35#ibcon#first serial, iclass 4, count 2 2006.258.00:02:10.35#ibcon#enter sib2, iclass 4, count 2 2006.258.00:02:10.35#ibcon#flushed, iclass 4, count 2 2006.258.00:02:10.35#ibcon#about to write, iclass 4, count 2 2006.258.00:02:10.35#ibcon#wrote, iclass 4, count 2 2006.258.00:02:10.35#ibcon#about to read 3, iclass 4, count 2 2006.258.00:02:10.37#ibcon#read 3, iclass 4, count 2 2006.258.00:02:10.37#ibcon#about to read 4, iclass 4, count 2 2006.258.00:02:10.37#ibcon#read 4, iclass 4, count 2 2006.258.00:02:10.37#ibcon#about to read 5, iclass 4, count 2 2006.258.00:02:10.37#ibcon#read 5, iclass 4, count 2 2006.258.00:02:10.37#ibcon#about to read 6, iclass 4, count 2 2006.258.00:02:10.37#ibcon#read 6, iclass 4, count 2 2006.258.00:02:10.37#ibcon#end of sib2, iclass 4, count 2 2006.258.00:02:10.37#ibcon#*mode == 0, iclass 4, count 2 2006.258.00:02:10.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.258.00:02:10.37#ibcon#[25=AT06-04\r\n] 2006.258.00:02:10.37#ibcon#*before write, iclass 4, count 2 2006.258.00:02:10.37#ibcon#enter sib2, iclass 4, count 2 2006.258.00:02:10.37#ibcon#flushed, iclass 4, count 2 2006.258.00:02:10.37#ibcon#about to write, iclass 4, count 2 2006.258.00:02:10.37#ibcon#wrote, iclass 4, count 2 2006.258.00:02:10.37#ibcon#about to read 3, iclass 4, count 2 2006.258.00:02:10.40#ibcon#read 3, iclass 4, count 2 2006.258.00:02:10.40#ibcon#about to read 4, iclass 4, count 2 2006.258.00:02:10.40#ibcon#read 4, iclass 4, count 2 2006.258.00:02:10.40#ibcon#about to read 5, iclass 4, count 2 2006.258.00:02:10.40#ibcon#read 5, iclass 4, count 2 2006.258.00:02:10.40#ibcon#about to read 6, iclass 4, count 2 2006.258.00:02:10.40#ibcon#read 6, iclass 4, count 2 2006.258.00:02:10.40#ibcon#end of sib2, iclass 4, count 2 2006.258.00:02:10.40#ibcon#*after write, iclass 4, count 2 2006.258.00:02:10.40#ibcon#*before return 0, iclass 4, count 2 2006.258.00:02:10.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:10.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:10.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.258.00:02:10.40#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:10.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:10.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:10.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:10.52#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:02:10.52#ibcon#first serial, iclass 4, count 0 2006.258.00:02:10.52#ibcon#enter sib2, iclass 4, count 0 2006.258.00:02:10.52#ibcon#flushed, iclass 4, count 0 2006.258.00:02:10.52#ibcon#about to write, iclass 4, count 0 2006.258.00:02:10.52#ibcon#wrote, iclass 4, count 0 2006.258.00:02:10.52#ibcon#about to read 3, iclass 4, count 0 2006.258.00:02:10.54#ibcon#read 3, iclass 4, count 0 2006.258.00:02:10.54#ibcon#about to read 4, iclass 4, count 0 2006.258.00:02:10.54#ibcon#read 4, iclass 4, count 0 2006.258.00:02:10.54#ibcon#about to read 5, iclass 4, count 0 2006.258.00:02:10.54#ibcon#read 5, iclass 4, count 0 2006.258.00:02:10.54#ibcon#about to read 6, iclass 4, count 0 2006.258.00:02:10.54#ibcon#read 6, iclass 4, count 0 2006.258.00:02:10.54#ibcon#end of sib2, iclass 4, count 0 2006.258.00:02:10.54#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:02:10.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:02:10.54#ibcon#[25=USB\r\n] 2006.258.00:02:10.54#ibcon#*before write, iclass 4, count 0 2006.258.00:02:10.54#ibcon#enter sib2, iclass 4, count 0 2006.258.00:02:10.54#ibcon#flushed, iclass 4, count 0 2006.258.00:02:10.54#ibcon#about to write, iclass 4, count 0 2006.258.00:02:10.54#ibcon#wrote, iclass 4, count 0 2006.258.00:02:10.54#ibcon#about to read 3, iclass 4, count 0 2006.258.00:02:10.57#ibcon#read 3, iclass 4, count 0 2006.258.00:02:10.57#ibcon#about to read 4, iclass 4, count 0 2006.258.00:02:10.57#ibcon#read 4, iclass 4, count 0 2006.258.00:02:10.57#ibcon#about to read 5, iclass 4, count 0 2006.258.00:02:10.57#ibcon#read 5, iclass 4, count 0 2006.258.00:02:10.57#ibcon#about to read 6, iclass 4, count 0 2006.258.00:02:10.57#ibcon#read 6, iclass 4, count 0 2006.258.00:02:10.57#ibcon#end of sib2, iclass 4, count 0 2006.258.00:02:10.57#ibcon#*after write, iclass 4, count 0 2006.258.00:02:10.57#ibcon#*before return 0, iclass 4, count 0 2006.258.00:02:10.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:10.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:10.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:02:10.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:02:10.57$vck44/valo=7,864.99 2006.258.00:02:10.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.00:02:10.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.00:02:10.57#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:10.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:10.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:10.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:10.57#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:02:10.57#ibcon#first serial, iclass 6, count 0 2006.258.00:02:10.57#ibcon#enter sib2, iclass 6, count 0 2006.258.00:02:10.57#ibcon#flushed, iclass 6, count 0 2006.258.00:02:10.57#ibcon#about to write, iclass 6, count 0 2006.258.00:02:10.57#ibcon#wrote, iclass 6, count 0 2006.258.00:02:10.57#ibcon#about to read 3, iclass 6, count 0 2006.258.00:02:10.59#ibcon#read 3, iclass 6, count 0 2006.258.00:02:10.59#ibcon#about to read 4, iclass 6, count 0 2006.258.00:02:10.59#ibcon#read 4, iclass 6, count 0 2006.258.00:02:10.59#ibcon#about to read 5, iclass 6, count 0 2006.258.00:02:10.59#ibcon#read 5, iclass 6, count 0 2006.258.00:02:10.59#ibcon#about to read 6, iclass 6, count 0 2006.258.00:02:10.59#ibcon#read 6, iclass 6, count 0 2006.258.00:02:10.59#ibcon#end of sib2, iclass 6, count 0 2006.258.00:02:10.59#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:02:10.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:02:10.59#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:02:10.59#ibcon#*before write, iclass 6, count 0 2006.258.00:02:10.59#ibcon#enter sib2, iclass 6, count 0 2006.258.00:02:10.59#ibcon#flushed, iclass 6, count 0 2006.258.00:02:10.59#ibcon#about to write, iclass 6, count 0 2006.258.00:02:10.59#ibcon#wrote, iclass 6, count 0 2006.258.00:02:10.59#ibcon#about to read 3, iclass 6, count 0 2006.258.00:02:10.63#ibcon#read 3, iclass 6, count 0 2006.258.00:02:10.63#ibcon#about to read 4, iclass 6, count 0 2006.258.00:02:10.63#ibcon#read 4, iclass 6, count 0 2006.258.00:02:10.63#ibcon#about to read 5, iclass 6, count 0 2006.258.00:02:10.63#ibcon#read 5, iclass 6, count 0 2006.258.00:02:10.63#ibcon#about to read 6, iclass 6, count 0 2006.258.00:02:10.63#ibcon#read 6, iclass 6, count 0 2006.258.00:02:10.63#ibcon#end of sib2, iclass 6, count 0 2006.258.00:02:10.63#ibcon#*after write, iclass 6, count 0 2006.258.00:02:10.63#ibcon#*before return 0, iclass 6, count 0 2006.258.00:02:10.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:10.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:10.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:02:10.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:02:10.63$vck44/va=7,4 2006.258.00:02:10.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.258.00:02:10.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.258.00:02:10.63#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:10.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:10.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:10.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:10.69#ibcon#enter wrdev, iclass 10, count 2 2006.258.00:02:10.69#ibcon#first serial, iclass 10, count 2 2006.258.00:02:10.69#ibcon#enter sib2, iclass 10, count 2 2006.258.00:02:10.69#ibcon#flushed, iclass 10, count 2 2006.258.00:02:10.69#ibcon#about to write, iclass 10, count 2 2006.258.00:02:10.69#ibcon#wrote, iclass 10, count 2 2006.258.00:02:10.69#ibcon#about to read 3, iclass 10, count 2 2006.258.00:02:10.71#ibcon#read 3, iclass 10, count 2 2006.258.00:02:10.71#ibcon#about to read 4, iclass 10, count 2 2006.258.00:02:10.71#ibcon#read 4, iclass 10, count 2 2006.258.00:02:10.71#ibcon#about to read 5, iclass 10, count 2 2006.258.00:02:10.71#ibcon#read 5, iclass 10, count 2 2006.258.00:02:10.71#ibcon#about to read 6, iclass 10, count 2 2006.258.00:02:10.71#ibcon#read 6, iclass 10, count 2 2006.258.00:02:10.71#ibcon#end of sib2, iclass 10, count 2 2006.258.00:02:10.71#ibcon#*mode == 0, iclass 10, count 2 2006.258.00:02:10.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.258.00:02:10.71#ibcon#[25=AT07-04\r\n] 2006.258.00:02:10.71#ibcon#*before write, iclass 10, count 2 2006.258.00:02:10.71#ibcon#enter sib2, iclass 10, count 2 2006.258.00:02:10.71#ibcon#flushed, iclass 10, count 2 2006.258.00:02:10.71#ibcon#about to write, iclass 10, count 2 2006.258.00:02:10.71#ibcon#wrote, iclass 10, count 2 2006.258.00:02:10.71#ibcon#about to read 3, iclass 10, count 2 2006.258.00:02:10.74#ibcon#read 3, iclass 10, count 2 2006.258.00:02:10.74#ibcon#about to read 4, iclass 10, count 2 2006.258.00:02:10.74#ibcon#read 4, iclass 10, count 2 2006.258.00:02:10.74#ibcon#about to read 5, iclass 10, count 2 2006.258.00:02:10.74#ibcon#read 5, iclass 10, count 2 2006.258.00:02:10.74#ibcon#about to read 6, iclass 10, count 2 2006.258.00:02:10.74#ibcon#read 6, iclass 10, count 2 2006.258.00:02:10.74#ibcon#end of sib2, iclass 10, count 2 2006.258.00:02:10.74#ibcon#*after write, iclass 10, count 2 2006.258.00:02:10.74#ibcon#*before return 0, iclass 10, count 2 2006.258.00:02:10.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:10.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:10.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.258.00:02:10.74#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:10.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:10.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:10.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:10.86#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:02:10.86#ibcon#first serial, iclass 10, count 0 2006.258.00:02:10.86#ibcon#enter sib2, iclass 10, count 0 2006.258.00:02:10.86#ibcon#flushed, iclass 10, count 0 2006.258.00:02:10.86#ibcon#about to write, iclass 10, count 0 2006.258.00:02:10.86#ibcon#wrote, iclass 10, count 0 2006.258.00:02:10.86#ibcon#about to read 3, iclass 10, count 0 2006.258.00:02:10.88#ibcon#read 3, iclass 10, count 0 2006.258.00:02:10.88#ibcon#about to read 4, iclass 10, count 0 2006.258.00:02:10.88#ibcon#read 4, iclass 10, count 0 2006.258.00:02:10.88#ibcon#about to read 5, iclass 10, count 0 2006.258.00:02:10.88#ibcon#read 5, iclass 10, count 0 2006.258.00:02:10.88#ibcon#about to read 6, iclass 10, count 0 2006.258.00:02:10.88#ibcon#read 6, iclass 10, count 0 2006.258.00:02:10.88#ibcon#end of sib2, iclass 10, count 0 2006.258.00:02:10.88#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:02:10.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:02:10.88#ibcon#[25=USB\r\n] 2006.258.00:02:10.88#ibcon#*before write, iclass 10, count 0 2006.258.00:02:10.88#ibcon#enter sib2, iclass 10, count 0 2006.258.00:02:10.88#ibcon#flushed, iclass 10, count 0 2006.258.00:02:10.88#ibcon#about to write, iclass 10, count 0 2006.258.00:02:10.88#ibcon#wrote, iclass 10, count 0 2006.258.00:02:10.88#ibcon#about to read 3, iclass 10, count 0 2006.258.00:02:10.91#ibcon#read 3, iclass 10, count 0 2006.258.00:02:10.91#ibcon#about to read 4, iclass 10, count 0 2006.258.00:02:10.91#ibcon#read 4, iclass 10, count 0 2006.258.00:02:10.91#ibcon#about to read 5, iclass 10, count 0 2006.258.00:02:10.91#ibcon#read 5, iclass 10, count 0 2006.258.00:02:10.91#ibcon#about to read 6, iclass 10, count 0 2006.258.00:02:10.91#ibcon#read 6, iclass 10, count 0 2006.258.00:02:10.91#ibcon#end of sib2, iclass 10, count 0 2006.258.00:02:10.91#ibcon#*after write, iclass 10, count 0 2006.258.00:02:10.91#ibcon#*before return 0, iclass 10, count 0 2006.258.00:02:10.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:10.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:10.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:02:10.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:02:10.91$vck44/valo=8,884.99 2006.258.00:02:10.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.00:02:10.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.00:02:10.91#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:10.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:10.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:10.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:10.91#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:02:10.91#ibcon#first serial, iclass 12, count 0 2006.258.00:02:10.91#ibcon#enter sib2, iclass 12, count 0 2006.258.00:02:10.91#ibcon#flushed, iclass 12, count 0 2006.258.00:02:10.91#ibcon#about to write, iclass 12, count 0 2006.258.00:02:10.91#ibcon#wrote, iclass 12, count 0 2006.258.00:02:10.91#ibcon#about to read 3, iclass 12, count 0 2006.258.00:02:10.93#ibcon#read 3, iclass 12, count 0 2006.258.00:02:10.93#ibcon#about to read 4, iclass 12, count 0 2006.258.00:02:10.93#ibcon#read 4, iclass 12, count 0 2006.258.00:02:10.93#ibcon#about to read 5, iclass 12, count 0 2006.258.00:02:10.93#ibcon#read 5, iclass 12, count 0 2006.258.00:02:10.93#ibcon#about to read 6, iclass 12, count 0 2006.258.00:02:10.93#ibcon#read 6, iclass 12, count 0 2006.258.00:02:10.93#ibcon#end of sib2, iclass 12, count 0 2006.258.00:02:10.93#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:02:10.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:02:10.93#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:02:10.93#ibcon#*before write, iclass 12, count 0 2006.258.00:02:10.93#ibcon#enter sib2, iclass 12, count 0 2006.258.00:02:10.93#ibcon#flushed, iclass 12, count 0 2006.258.00:02:10.93#ibcon#about to write, iclass 12, count 0 2006.258.00:02:10.93#ibcon#wrote, iclass 12, count 0 2006.258.00:02:10.93#ibcon#about to read 3, iclass 12, count 0 2006.258.00:02:10.97#ibcon#read 3, iclass 12, count 0 2006.258.00:02:10.97#ibcon#about to read 4, iclass 12, count 0 2006.258.00:02:10.97#ibcon#read 4, iclass 12, count 0 2006.258.00:02:10.97#ibcon#about to read 5, iclass 12, count 0 2006.258.00:02:10.97#ibcon#read 5, iclass 12, count 0 2006.258.00:02:10.97#ibcon#about to read 6, iclass 12, count 0 2006.258.00:02:10.97#ibcon#read 6, iclass 12, count 0 2006.258.00:02:10.97#ibcon#end of sib2, iclass 12, count 0 2006.258.00:02:10.97#ibcon#*after write, iclass 12, count 0 2006.258.00:02:10.97#ibcon#*before return 0, iclass 12, count 0 2006.258.00:02:10.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:10.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:10.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:02:10.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:02:10.97$vck44/va=8,4 2006.258.00:02:10.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.258.00:02:10.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.258.00:02:10.97#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:10.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:11.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:11.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:11.03#ibcon#enter wrdev, iclass 14, count 2 2006.258.00:02:11.03#ibcon#first serial, iclass 14, count 2 2006.258.00:02:11.03#ibcon#enter sib2, iclass 14, count 2 2006.258.00:02:11.03#ibcon#flushed, iclass 14, count 2 2006.258.00:02:11.03#ibcon#about to write, iclass 14, count 2 2006.258.00:02:11.03#ibcon#wrote, iclass 14, count 2 2006.258.00:02:11.03#ibcon#about to read 3, iclass 14, count 2 2006.258.00:02:11.05#ibcon#read 3, iclass 14, count 2 2006.258.00:02:11.05#ibcon#about to read 4, iclass 14, count 2 2006.258.00:02:11.05#ibcon#read 4, iclass 14, count 2 2006.258.00:02:11.05#ibcon#about to read 5, iclass 14, count 2 2006.258.00:02:11.05#ibcon#read 5, iclass 14, count 2 2006.258.00:02:11.05#ibcon#about to read 6, iclass 14, count 2 2006.258.00:02:11.05#ibcon#read 6, iclass 14, count 2 2006.258.00:02:11.05#ibcon#end of sib2, iclass 14, count 2 2006.258.00:02:11.05#ibcon#*mode == 0, iclass 14, count 2 2006.258.00:02:11.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.258.00:02:11.05#ibcon#[25=AT08-04\r\n] 2006.258.00:02:11.05#ibcon#*before write, iclass 14, count 2 2006.258.00:02:11.05#ibcon#enter sib2, iclass 14, count 2 2006.258.00:02:11.05#ibcon#flushed, iclass 14, count 2 2006.258.00:02:11.05#ibcon#about to write, iclass 14, count 2 2006.258.00:02:11.05#ibcon#wrote, iclass 14, count 2 2006.258.00:02:11.05#ibcon#about to read 3, iclass 14, count 2 2006.258.00:02:11.08#ibcon#read 3, iclass 14, count 2 2006.258.00:02:11.08#ibcon#about to read 4, iclass 14, count 2 2006.258.00:02:11.08#ibcon#read 4, iclass 14, count 2 2006.258.00:02:11.08#ibcon#about to read 5, iclass 14, count 2 2006.258.00:02:11.08#ibcon#read 5, iclass 14, count 2 2006.258.00:02:11.08#ibcon#about to read 6, iclass 14, count 2 2006.258.00:02:11.08#ibcon#read 6, iclass 14, count 2 2006.258.00:02:11.08#ibcon#end of sib2, iclass 14, count 2 2006.258.00:02:11.08#ibcon#*after write, iclass 14, count 2 2006.258.00:02:11.08#ibcon#*before return 0, iclass 14, count 2 2006.258.00:02:11.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:11.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:11.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.258.00:02:11.08#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:11.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:11.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:11.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:11.20#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:02:11.20#ibcon#first serial, iclass 14, count 0 2006.258.00:02:11.20#ibcon#enter sib2, iclass 14, count 0 2006.258.00:02:11.20#ibcon#flushed, iclass 14, count 0 2006.258.00:02:11.20#ibcon#about to write, iclass 14, count 0 2006.258.00:02:11.20#ibcon#wrote, iclass 14, count 0 2006.258.00:02:11.20#ibcon#about to read 3, iclass 14, count 0 2006.258.00:02:11.22#ibcon#read 3, iclass 14, count 0 2006.258.00:02:11.22#ibcon#about to read 4, iclass 14, count 0 2006.258.00:02:11.22#ibcon#read 4, iclass 14, count 0 2006.258.00:02:11.22#ibcon#about to read 5, iclass 14, count 0 2006.258.00:02:11.22#ibcon#read 5, iclass 14, count 0 2006.258.00:02:11.22#ibcon#about to read 6, iclass 14, count 0 2006.258.00:02:11.22#ibcon#read 6, iclass 14, count 0 2006.258.00:02:11.22#ibcon#end of sib2, iclass 14, count 0 2006.258.00:02:11.22#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:02:11.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:02:11.22#ibcon#[25=USB\r\n] 2006.258.00:02:11.22#ibcon#*before write, iclass 14, count 0 2006.258.00:02:11.22#ibcon#enter sib2, iclass 14, count 0 2006.258.00:02:11.22#ibcon#flushed, iclass 14, count 0 2006.258.00:02:11.22#ibcon#about to write, iclass 14, count 0 2006.258.00:02:11.22#ibcon#wrote, iclass 14, count 0 2006.258.00:02:11.22#ibcon#about to read 3, iclass 14, count 0 2006.258.00:02:11.25#ibcon#read 3, iclass 14, count 0 2006.258.00:02:11.25#ibcon#about to read 4, iclass 14, count 0 2006.258.00:02:11.25#ibcon#read 4, iclass 14, count 0 2006.258.00:02:11.25#ibcon#about to read 5, iclass 14, count 0 2006.258.00:02:11.25#ibcon#read 5, iclass 14, count 0 2006.258.00:02:11.25#ibcon#about to read 6, iclass 14, count 0 2006.258.00:02:11.25#ibcon#read 6, iclass 14, count 0 2006.258.00:02:11.25#ibcon#end of sib2, iclass 14, count 0 2006.258.00:02:11.25#ibcon#*after write, iclass 14, count 0 2006.258.00:02:11.25#ibcon#*before return 0, iclass 14, count 0 2006.258.00:02:11.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:11.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:11.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:02:11.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:02:11.25$vck44/vblo=1,629.99 2006.258.00:02:11.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.00:02:11.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.00:02:11.25#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:11.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:11.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:11.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:11.25#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:02:11.25#ibcon#first serial, iclass 16, count 0 2006.258.00:02:11.25#ibcon#enter sib2, iclass 16, count 0 2006.258.00:02:11.25#ibcon#flushed, iclass 16, count 0 2006.258.00:02:11.25#ibcon#about to write, iclass 16, count 0 2006.258.00:02:11.25#ibcon#wrote, iclass 16, count 0 2006.258.00:02:11.25#ibcon#about to read 3, iclass 16, count 0 2006.258.00:02:11.27#ibcon#read 3, iclass 16, count 0 2006.258.00:02:11.27#ibcon#about to read 4, iclass 16, count 0 2006.258.00:02:11.27#ibcon#read 4, iclass 16, count 0 2006.258.00:02:11.27#ibcon#about to read 5, iclass 16, count 0 2006.258.00:02:11.27#ibcon#read 5, iclass 16, count 0 2006.258.00:02:11.27#ibcon#about to read 6, iclass 16, count 0 2006.258.00:02:11.27#ibcon#read 6, iclass 16, count 0 2006.258.00:02:11.27#ibcon#end of sib2, iclass 16, count 0 2006.258.00:02:11.27#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:02:11.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:02:11.27#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:02:11.27#ibcon#*before write, iclass 16, count 0 2006.258.00:02:11.27#ibcon#enter sib2, iclass 16, count 0 2006.258.00:02:11.27#ibcon#flushed, iclass 16, count 0 2006.258.00:02:11.27#ibcon#about to write, iclass 16, count 0 2006.258.00:02:11.27#ibcon#wrote, iclass 16, count 0 2006.258.00:02:11.27#ibcon#about to read 3, iclass 16, count 0 2006.258.00:02:11.31#ibcon#read 3, iclass 16, count 0 2006.258.00:02:11.31#ibcon#about to read 4, iclass 16, count 0 2006.258.00:02:11.31#ibcon#read 4, iclass 16, count 0 2006.258.00:02:11.31#ibcon#about to read 5, iclass 16, count 0 2006.258.00:02:11.31#ibcon#read 5, iclass 16, count 0 2006.258.00:02:11.31#ibcon#about to read 6, iclass 16, count 0 2006.258.00:02:11.31#ibcon#read 6, iclass 16, count 0 2006.258.00:02:11.31#ibcon#end of sib2, iclass 16, count 0 2006.258.00:02:11.31#ibcon#*after write, iclass 16, count 0 2006.258.00:02:11.31#ibcon#*before return 0, iclass 16, count 0 2006.258.00:02:11.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:11.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:11.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:02:11.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:02:11.31$vck44/vb=1,4 2006.258.00:02:11.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.258.00:02:11.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.258.00:02:11.31#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:11.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:02:11.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:02:11.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:02:11.31#ibcon#enter wrdev, iclass 18, count 2 2006.258.00:02:11.31#ibcon#first serial, iclass 18, count 2 2006.258.00:02:11.31#ibcon#enter sib2, iclass 18, count 2 2006.258.00:02:11.31#ibcon#flushed, iclass 18, count 2 2006.258.00:02:11.31#ibcon#about to write, iclass 18, count 2 2006.258.00:02:11.31#ibcon#wrote, iclass 18, count 2 2006.258.00:02:11.31#ibcon#about to read 3, iclass 18, count 2 2006.258.00:02:11.33#ibcon#read 3, iclass 18, count 2 2006.258.00:02:11.33#ibcon#about to read 4, iclass 18, count 2 2006.258.00:02:11.33#ibcon#read 4, iclass 18, count 2 2006.258.00:02:11.33#ibcon#about to read 5, iclass 18, count 2 2006.258.00:02:11.33#ibcon#read 5, iclass 18, count 2 2006.258.00:02:11.33#ibcon#about to read 6, iclass 18, count 2 2006.258.00:02:11.33#ibcon#read 6, iclass 18, count 2 2006.258.00:02:11.33#ibcon#end of sib2, iclass 18, count 2 2006.258.00:02:11.33#ibcon#*mode == 0, iclass 18, count 2 2006.258.00:02:11.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.258.00:02:11.33#ibcon#[27=AT01-04\r\n] 2006.258.00:02:11.33#ibcon#*before write, iclass 18, count 2 2006.258.00:02:11.33#ibcon#enter sib2, iclass 18, count 2 2006.258.00:02:11.33#ibcon#flushed, iclass 18, count 2 2006.258.00:02:11.33#ibcon#about to write, iclass 18, count 2 2006.258.00:02:11.33#ibcon#wrote, iclass 18, count 2 2006.258.00:02:11.33#ibcon#about to read 3, iclass 18, count 2 2006.258.00:02:11.36#ibcon#read 3, iclass 18, count 2 2006.258.00:02:11.36#ibcon#about to read 4, iclass 18, count 2 2006.258.00:02:11.36#ibcon#read 4, iclass 18, count 2 2006.258.00:02:11.36#ibcon#about to read 5, iclass 18, count 2 2006.258.00:02:11.36#ibcon#read 5, iclass 18, count 2 2006.258.00:02:11.36#ibcon#about to read 6, iclass 18, count 2 2006.258.00:02:11.36#ibcon#read 6, iclass 18, count 2 2006.258.00:02:11.36#ibcon#end of sib2, iclass 18, count 2 2006.258.00:02:11.36#ibcon#*after write, iclass 18, count 2 2006.258.00:02:11.36#ibcon#*before return 0, iclass 18, count 2 2006.258.00:02:11.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:02:11.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:02:11.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.258.00:02:11.36#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:11.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:02:11.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:02:11.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:02:11.48#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:02:11.48#ibcon#first serial, iclass 18, count 0 2006.258.00:02:11.48#ibcon#enter sib2, iclass 18, count 0 2006.258.00:02:11.48#ibcon#flushed, iclass 18, count 0 2006.258.00:02:11.48#ibcon#about to write, iclass 18, count 0 2006.258.00:02:11.48#ibcon#wrote, iclass 18, count 0 2006.258.00:02:11.48#ibcon#about to read 3, iclass 18, count 0 2006.258.00:02:11.50#ibcon#read 3, iclass 18, count 0 2006.258.00:02:11.50#ibcon#about to read 4, iclass 18, count 0 2006.258.00:02:11.50#ibcon#read 4, iclass 18, count 0 2006.258.00:02:11.50#ibcon#about to read 5, iclass 18, count 0 2006.258.00:02:11.50#ibcon#read 5, iclass 18, count 0 2006.258.00:02:11.50#ibcon#about to read 6, iclass 18, count 0 2006.258.00:02:11.50#ibcon#read 6, iclass 18, count 0 2006.258.00:02:11.50#ibcon#end of sib2, iclass 18, count 0 2006.258.00:02:11.50#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:02:11.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:02:11.50#ibcon#[27=USB\r\n] 2006.258.00:02:11.50#ibcon#*before write, iclass 18, count 0 2006.258.00:02:11.50#ibcon#enter sib2, iclass 18, count 0 2006.258.00:02:11.50#ibcon#flushed, iclass 18, count 0 2006.258.00:02:11.50#ibcon#about to write, iclass 18, count 0 2006.258.00:02:11.50#ibcon#wrote, iclass 18, count 0 2006.258.00:02:11.50#ibcon#about to read 3, iclass 18, count 0 2006.258.00:02:11.53#ibcon#read 3, iclass 18, count 0 2006.258.00:02:11.53#ibcon#about to read 4, iclass 18, count 0 2006.258.00:02:11.53#ibcon#read 4, iclass 18, count 0 2006.258.00:02:11.53#ibcon#about to read 5, iclass 18, count 0 2006.258.00:02:11.53#ibcon#read 5, iclass 18, count 0 2006.258.00:02:11.53#ibcon#about to read 6, iclass 18, count 0 2006.258.00:02:11.53#ibcon#read 6, iclass 18, count 0 2006.258.00:02:11.53#ibcon#end of sib2, iclass 18, count 0 2006.258.00:02:11.53#ibcon#*after write, iclass 18, count 0 2006.258.00:02:11.53#ibcon#*before return 0, iclass 18, count 0 2006.258.00:02:11.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:02:11.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:02:11.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:02:11.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:02:11.53$vck44/vblo=2,634.99 2006.258.00:02:11.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.00:02:11.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.00:02:11.53#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:11.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:11.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:11.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:11.53#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:02:11.53#ibcon#first serial, iclass 20, count 0 2006.258.00:02:11.53#ibcon#enter sib2, iclass 20, count 0 2006.258.00:02:11.53#ibcon#flushed, iclass 20, count 0 2006.258.00:02:11.53#ibcon#about to write, iclass 20, count 0 2006.258.00:02:11.53#ibcon#wrote, iclass 20, count 0 2006.258.00:02:11.53#ibcon#about to read 3, iclass 20, count 0 2006.258.00:02:11.55#ibcon#read 3, iclass 20, count 0 2006.258.00:02:11.55#ibcon#about to read 4, iclass 20, count 0 2006.258.00:02:11.55#ibcon#read 4, iclass 20, count 0 2006.258.00:02:11.55#ibcon#about to read 5, iclass 20, count 0 2006.258.00:02:11.55#ibcon#read 5, iclass 20, count 0 2006.258.00:02:11.55#ibcon#about to read 6, iclass 20, count 0 2006.258.00:02:11.55#ibcon#read 6, iclass 20, count 0 2006.258.00:02:11.55#ibcon#end of sib2, iclass 20, count 0 2006.258.00:02:11.55#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:02:11.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:02:11.55#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:02:11.55#ibcon#*before write, iclass 20, count 0 2006.258.00:02:11.55#ibcon#enter sib2, iclass 20, count 0 2006.258.00:02:11.55#ibcon#flushed, iclass 20, count 0 2006.258.00:02:11.55#ibcon#about to write, iclass 20, count 0 2006.258.00:02:11.55#ibcon#wrote, iclass 20, count 0 2006.258.00:02:11.55#ibcon#about to read 3, iclass 20, count 0 2006.258.00:02:11.59#ibcon#read 3, iclass 20, count 0 2006.258.00:02:11.59#ibcon#about to read 4, iclass 20, count 0 2006.258.00:02:11.59#ibcon#read 4, iclass 20, count 0 2006.258.00:02:11.59#ibcon#about to read 5, iclass 20, count 0 2006.258.00:02:11.59#ibcon#read 5, iclass 20, count 0 2006.258.00:02:11.59#ibcon#about to read 6, iclass 20, count 0 2006.258.00:02:11.59#ibcon#read 6, iclass 20, count 0 2006.258.00:02:11.59#ibcon#end of sib2, iclass 20, count 0 2006.258.00:02:11.59#ibcon#*after write, iclass 20, count 0 2006.258.00:02:11.59#ibcon#*before return 0, iclass 20, count 0 2006.258.00:02:11.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:11.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:02:11.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:02:11.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:02:11.59$vck44/vb=2,5 2006.258.00:02:11.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.00:02:11.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.00:02:11.59#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:11.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:11.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:11.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:11.65#ibcon#enter wrdev, iclass 22, count 2 2006.258.00:02:11.65#ibcon#first serial, iclass 22, count 2 2006.258.00:02:11.65#ibcon#enter sib2, iclass 22, count 2 2006.258.00:02:11.65#ibcon#flushed, iclass 22, count 2 2006.258.00:02:11.65#ibcon#about to write, iclass 22, count 2 2006.258.00:02:11.65#ibcon#wrote, iclass 22, count 2 2006.258.00:02:11.65#ibcon#about to read 3, iclass 22, count 2 2006.258.00:02:11.67#ibcon#read 3, iclass 22, count 2 2006.258.00:02:11.67#ibcon#about to read 4, iclass 22, count 2 2006.258.00:02:11.67#ibcon#read 4, iclass 22, count 2 2006.258.00:02:11.67#ibcon#about to read 5, iclass 22, count 2 2006.258.00:02:11.67#ibcon#read 5, iclass 22, count 2 2006.258.00:02:11.67#ibcon#about to read 6, iclass 22, count 2 2006.258.00:02:11.67#ibcon#read 6, iclass 22, count 2 2006.258.00:02:11.67#ibcon#end of sib2, iclass 22, count 2 2006.258.00:02:11.67#ibcon#*mode == 0, iclass 22, count 2 2006.258.00:02:11.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.00:02:11.67#ibcon#[27=AT02-05\r\n] 2006.258.00:02:11.67#ibcon#*before write, iclass 22, count 2 2006.258.00:02:11.67#ibcon#enter sib2, iclass 22, count 2 2006.258.00:02:11.67#ibcon#flushed, iclass 22, count 2 2006.258.00:02:11.67#ibcon#about to write, iclass 22, count 2 2006.258.00:02:11.67#ibcon#wrote, iclass 22, count 2 2006.258.00:02:11.67#ibcon#about to read 3, iclass 22, count 2 2006.258.00:02:11.70#ibcon#read 3, iclass 22, count 2 2006.258.00:02:11.70#ibcon#about to read 4, iclass 22, count 2 2006.258.00:02:11.70#ibcon#read 4, iclass 22, count 2 2006.258.00:02:11.70#ibcon#about to read 5, iclass 22, count 2 2006.258.00:02:11.70#ibcon#read 5, iclass 22, count 2 2006.258.00:02:11.70#ibcon#about to read 6, iclass 22, count 2 2006.258.00:02:11.70#ibcon#read 6, iclass 22, count 2 2006.258.00:02:11.70#ibcon#end of sib2, iclass 22, count 2 2006.258.00:02:11.70#ibcon#*after write, iclass 22, count 2 2006.258.00:02:11.70#ibcon#*before return 0, iclass 22, count 2 2006.258.00:02:11.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:11.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:02:11.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.00:02:11.70#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:11.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:11.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:11.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:11.82#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:02:11.82#ibcon#first serial, iclass 22, count 0 2006.258.00:02:11.82#ibcon#enter sib2, iclass 22, count 0 2006.258.00:02:11.82#ibcon#flushed, iclass 22, count 0 2006.258.00:02:11.82#ibcon#about to write, iclass 22, count 0 2006.258.00:02:11.82#ibcon#wrote, iclass 22, count 0 2006.258.00:02:11.82#ibcon#about to read 3, iclass 22, count 0 2006.258.00:02:11.84#ibcon#read 3, iclass 22, count 0 2006.258.00:02:11.84#ibcon#about to read 4, iclass 22, count 0 2006.258.00:02:11.84#ibcon#read 4, iclass 22, count 0 2006.258.00:02:11.84#ibcon#about to read 5, iclass 22, count 0 2006.258.00:02:11.84#ibcon#read 5, iclass 22, count 0 2006.258.00:02:11.84#ibcon#about to read 6, iclass 22, count 0 2006.258.00:02:11.84#ibcon#read 6, iclass 22, count 0 2006.258.00:02:11.84#ibcon#end of sib2, iclass 22, count 0 2006.258.00:02:11.84#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:02:11.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:02:11.84#ibcon#[27=USB\r\n] 2006.258.00:02:11.84#ibcon#*before write, iclass 22, count 0 2006.258.00:02:11.84#ibcon#enter sib2, iclass 22, count 0 2006.258.00:02:11.84#ibcon#flushed, iclass 22, count 0 2006.258.00:02:11.84#ibcon#about to write, iclass 22, count 0 2006.258.00:02:11.84#ibcon#wrote, iclass 22, count 0 2006.258.00:02:11.84#ibcon#about to read 3, iclass 22, count 0 2006.258.00:02:11.87#ibcon#read 3, iclass 22, count 0 2006.258.00:02:11.87#ibcon#about to read 4, iclass 22, count 0 2006.258.00:02:11.87#ibcon#read 4, iclass 22, count 0 2006.258.00:02:11.87#ibcon#about to read 5, iclass 22, count 0 2006.258.00:02:11.87#ibcon#read 5, iclass 22, count 0 2006.258.00:02:11.87#ibcon#about to read 6, iclass 22, count 0 2006.258.00:02:11.87#ibcon#read 6, iclass 22, count 0 2006.258.00:02:11.87#ibcon#end of sib2, iclass 22, count 0 2006.258.00:02:11.87#ibcon#*after write, iclass 22, count 0 2006.258.00:02:11.87#ibcon#*before return 0, iclass 22, count 0 2006.258.00:02:11.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:11.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:02:11.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:02:11.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:02:11.87$vck44/vblo=3,649.99 2006.258.00:02:11.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.00:02:11.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.00:02:11.87#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:11.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:11.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:11.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:11.87#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:02:11.87#ibcon#first serial, iclass 24, count 0 2006.258.00:02:11.87#ibcon#enter sib2, iclass 24, count 0 2006.258.00:02:11.87#ibcon#flushed, iclass 24, count 0 2006.258.00:02:11.87#ibcon#about to write, iclass 24, count 0 2006.258.00:02:11.87#ibcon#wrote, iclass 24, count 0 2006.258.00:02:11.87#ibcon#about to read 3, iclass 24, count 0 2006.258.00:02:11.89#ibcon#read 3, iclass 24, count 0 2006.258.00:02:11.89#ibcon#about to read 4, iclass 24, count 0 2006.258.00:02:11.89#ibcon#read 4, iclass 24, count 0 2006.258.00:02:11.89#ibcon#about to read 5, iclass 24, count 0 2006.258.00:02:11.89#ibcon#read 5, iclass 24, count 0 2006.258.00:02:11.89#ibcon#about to read 6, iclass 24, count 0 2006.258.00:02:11.89#ibcon#read 6, iclass 24, count 0 2006.258.00:02:11.89#ibcon#end of sib2, iclass 24, count 0 2006.258.00:02:11.89#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:02:11.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:02:11.89#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:02:11.89#ibcon#*before write, iclass 24, count 0 2006.258.00:02:11.89#ibcon#enter sib2, iclass 24, count 0 2006.258.00:02:11.89#ibcon#flushed, iclass 24, count 0 2006.258.00:02:11.89#ibcon#about to write, iclass 24, count 0 2006.258.00:02:11.89#ibcon#wrote, iclass 24, count 0 2006.258.00:02:11.89#ibcon#about to read 3, iclass 24, count 0 2006.258.00:02:11.93#ibcon#read 3, iclass 24, count 0 2006.258.00:02:11.93#ibcon#about to read 4, iclass 24, count 0 2006.258.00:02:11.93#ibcon#read 4, iclass 24, count 0 2006.258.00:02:11.93#ibcon#about to read 5, iclass 24, count 0 2006.258.00:02:11.93#ibcon#read 5, iclass 24, count 0 2006.258.00:02:11.93#ibcon#about to read 6, iclass 24, count 0 2006.258.00:02:11.93#ibcon#read 6, iclass 24, count 0 2006.258.00:02:11.93#ibcon#end of sib2, iclass 24, count 0 2006.258.00:02:11.93#ibcon#*after write, iclass 24, count 0 2006.258.00:02:11.93#ibcon#*before return 0, iclass 24, count 0 2006.258.00:02:11.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:11.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:02:11.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:02:11.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:02:11.93$vck44/vb=3,4 2006.258.00:02:11.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.00:02:11.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.00:02:11.93#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:11.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:11.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:11.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:11.99#ibcon#enter wrdev, iclass 26, count 2 2006.258.00:02:11.99#ibcon#first serial, iclass 26, count 2 2006.258.00:02:11.99#ibcon#enter sib2, iclass 26, count 2 2006.258.00:02:11.99#ibcon#flushed, iclass 26, count 2 2006.258.00:02:11.99#ibcon#about to write, iclass 26, count 2 2006.258.00:02:11.99#ibcon#wrote, iclass 26, count 2 2006.258.00:02:11.99#ibcon#about to read 3, iclass 26, count 2 2006.258.00:02:12.01#ibcon#read 3, iclass 26, count 2 2006.258.00:02:12.01#ibcon#about to read 4, iclass 26, count 2 2006.258.00:02:12.01#ibcon#read 4, iclass 26, count 2 2006.258.00:02:12.01#ibcon#about to read 5, iclass 26, count 2 2006.258.00:02:12.01#ibcon#read 5, iclass 26, count 2 2006.258.00:02:12.01#ibcon#about to read 6, iclass 26, count 2 2006.258.00:02:12.01#ibcon#read 6, iclass 26, count 2 2006.258.00:02:12.01#ibcon#end of sib2, iclass 26, count 2 2006.258.00:02:12.01#ibcon#*mode == 0, iclass 26, count 2 2006.258.00:02:12.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.00:02:12.01#ibcon#[27=AT03-04\r\n] 2006.258.00:02:12.01#ibcon#*before write, iclass 26, count 2 2006.258.00:02:12.01#ibcon#enter sib2, iclass 26, count 2 2006.258.00:02:12.01#ibcon#flushed, iclass 26, count 2 2006.258.00:02:12.01#ibcon#about to write, iclass 26, count 2 2006.258.00:02:12.01#ibcon#wrote, iclass 26, count 2 2006.258.00:02:12.01#ibcon#about to read 3, iclass 26, count 2 2006.258.00:02:12.04#ibcon#read 3, iclass 26, count 2 2006.258.00:02:12.04#ibcon#about to read 4, iclass 26, count 2 2006.258.00:02:12.04#ibcon#read 4, iclass 26, count 2 2006.258.00:02:12.04#ibcon#about to read 5, iclass 26, count 2 2006.258.00:02:12.04#ibcon#read 5, iclass 26, count 2 2006.258.00:02:12.04#ibcon#about to read 6, iclass 26, count 2 2006.258.00:02:12.04#ibcon#read 6, iclass 26, count 2 2006.258.00:02:12.04#ibcon#end of sib2, iclass 26, count 2 2006.258.00:02:12.04#ibcon#*after write, iclass 26, count 2 2006.258.00:02:12.04#ibcon#*before return 0, iclass 26, count 2 2006.258.00:02:12.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:12.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:02:12.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.00:02:12.04#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:12.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:12.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:12.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:12.16#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:02:12.16#ibcon#first serial, iclass 26, count 0 2006.258.00:02:12.16#ibcon#enter sib2, iclass 26, count 0 2006.258.00:02:12.16#ibcon#flushed, iclass 26, count 0 2006.258.00:02:12.16#ibcon#about to write, iclass 26, count 0 2006.258.00:02:12.16#ibcon#wrote, iclass 26, count 0 2006.258.00:02:12.16#ibcon#about to read 3, iclass 26, count 0 2006.258.00:02:12.18#ibcon#read 3, iclass 26, count 0 2006.258.00:02:12.18#ibcon#about to read 4, iclass 26, count 0 2006.258.00:02:12.18#ibcon#read 4, iclass 26, count 0 2006.258.00:02:12.18#ibcon#about to read 5, iclass 26, count 0 2006.258.00:02:12.18#ibcon#read 5, iclass 26, count 0 2006.258.00:02:12.18#ibcon#about to read 6, iclass 26, count 0 2006.258.00:02:12.18#ibcon#read 6, iclass 26, count 0 2006.258.00:02:12.18#ibcon#end of sib2, iclass 26, count 0 2006.258.00:02:12.18#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:02:12.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:02:12.18#ibcon#[27=USB\r\n] 2006.258.00:02:12.18#ibcon#*before write, iclass 26, count 0 2006.258.00:02:12.18#ibcon#enter sib2, iclass 26, count 0 2006.258.00:02:12.18#ibcon#flushed, iclass 26, count 0 2006.258.00:02:12.18#ibcon#about to write, iclass 26, count 0 2006.258.00:02:12.18#ibcon#wrote, iclass 26, count 0 2006.258.00:02:12.18#ibcon#about to read 3, iclass 26, count 0 2006.258.00:02:12.21#ibcon#read 3, iclass 26, count 0 2006.258.00:02:12.21#ibcon#about to read 4, iclass 26, count 0 2006.258.00:02:12.21#ibcon#read 4, iclass 26, count 0 2006.258.00:02:12.21#ibcon#about to read 5, iclass 26, count 0 2006.258.00:02:12.21#ibcon#read 5, iclass 26, count 0 2006.258.00:02:12.21#ibcon#about to read 6, iclass 26, count 0 2006.258.00:02:12.21#ibcon#read 6, iclass 26, count 0 2006.258.00:02:12.21#ibcon#end of sib2, iclass 26, count 0 2006.258.00:02:12.21#ibcon#*after write, iclass 26, count 0 2006.258.00:02:12.21#ibcon#*before return 0, iclass 26, count 0 2006.258.00:02:12.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:12.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:02:12.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:02:12.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:02:12.21$vck44/vblo=4,679.99 2006.258.00:02:12.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.00:02:12.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.00:02:12.21#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:12.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:12.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:12.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:12.21#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:02:12.21#ibcon#first serial, iclass 28, count 0 2006.258.00:02:12.21#ibcon#enter sib2, iclass 28, count 0 2006.258.00:02:12.21#ibcon#flushed, iclass 28, count 0 2006.258.00:02:12.21#ibcon#about to write, iclass 28, count 0 2006.258.00:02:12.21#ibcon#wrote, iclass 28, count 0 2006.258.00:02:12.21#ibcon#about to read 3, iclass 28, count 0 2006.258.00:02:12.23#ibcon#read 3, iclass 28, count 0 2006.258.00:02:12.23#ibcon#about to read 4, iclass 28, count 0 2006.258.00:02:12.23#ibcon#read 4, iclass 28, count 0 2006.258.00:02:12.23#ibcon#about to read 5, iclass 28, count 0 2006.258.00:02:12.23#ibcon#read 5, iclass 28, count 0 2006.258.00:02:12.23#ibcon#about to read 6, iclass 28, count 0 2006.258.00:02:12.23#ibcon#read 6, iclass 28, count 0 2006.258.00:02:12.23#ibcon#end of sib2, iclass 28, count 0 2006.258.00:02:12.23#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:02:12.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:02:12.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:02:12.23#ibcon#*before write, iclass 28, count 0 2006.258.00:02:12.23#ibcon#enter sib2, iclass 28, count 0 2006.258.00:02:12.23#ibcon#flushed, iclass 28, count 0 2006.258.00:02:12.23#ibcon#about to write, iclass 28, count 0 2006.258.00:02:12.23#ibcon#wrote, iclass 28, count 0 2006.258.00:02:12.23#ibcon#about to read 3, iclass 28, count 0 2006.258.00:02:12.27#ibcon#read 3, iclass 28, count 0 2006.258.00:02:12.27#ibcon#about to read 4, iclass 28, count 0 2006.258.00:02:12.27#ibcon#read 4, iclass 28, count 0 2006.258.00:02:12.27#ibcon#about to read 5, iclass 28, count 0 2006.258.00:02:12.27#ibcon#read 5, iclass 28, count 0 2006.258.00:02:12.27#ibcon#about to read 6, iclass 28, count 0 2006.258.00:02:12.27#ibcon#read 6, iclass 28, count 0 2006.258.00:02:12.27#ibcon#end of sib2, iclass 28, count 0 2006.258.00:02:12.27#ibcon#*after write, iclass 28, count 0 2006.258.00:02:12.27#ibcon#*before return 0, iclass 28, count 0 2006.258.00:02:12.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:12.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:02:12.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:02:12.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:02:12.27$vck44/vb=4,5 2006.258.00:02:12.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.00:02:12.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.00:02:12.27#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:12.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:12.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:12.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:12.33#ibcon#enter wrdev, iclass 30, count 2 2006.258.00:02:12.33#ibcon#first serial, iclass 30, count 2 2006.258.00:02:12.33#ibcon#enter sib2, iclass 30, count 2 2006.258.00:02:12.33#ibcon#flushed, iclass 30, count 2 2006.258.00:02:12.33#ibcon#about to write, iclass 30, count 2 2006.258.00:02:12.33#ibcon#wrote, iclass 30, count 2 2006.258.00:02:12.33#ibcon#about to read 3, iclass 30, count 2 2006.258.00:02:12.35#ibcon#read 3, iclass 30, count 2 2006.258.00:02:12.35#ibcon#about to read 4, iclass 30, count 2 2006.258.00:02:12.35#ibcon#read 4, iclass 30, count 2 2006.258.00:02:12.35#ibcon#about to read 5, iclass 30, count 2 2006.258.00:02:12.35#ibcon#read 5, iclass 30, count 2 2006.258.00:02:12.35#ibcon#about to read 6, iclass 30, count 2 2006.258.00:02:12.35#ibcon#read 6, iclass 30, count 2 2006.258.00:02:12.35#ibcon#end of sib2, iclass 30, count 2 2006.258.00:02:12.35#ibcon#*mode == 0, iclass 30, count 2 2006.258.00:02:12.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.00:02:12.35#ibcon#[27=AT04-05\r\n] 2006.258.00:02:12.35#ibcon#*before write, iclass 30, count 2 2006.258.00:02:12.35#ibcon#enter sib2, iclass 30, count 2 2006.258.00:02:12.35#ibcon#flushed, iclass 30, count 2 2006.258.00:02:12.35#ibcon#about to write, iclass 30, count 2 2006.258.00:02:12.35#ibcon#wrote, iclass 30, count 2 2006.258.00:02:12.35#ibcon#about to read 3, iclass 30, count 2 2006.258.00:02:12.38#ibcon#read 3, iclass 30, count 2 2006.258.00:02:12.38#ibcon#about to read 4, iclass 30, count 2 2006.258.00:02:12.38#ibcon#read 4, iclass 30, count 2 2006.258.00:02:12.38#ibcon#about to read 5, iclass 30, count 2 2006.258.00:02:12.38#ibcon#read 5, iclass 30, count 2 2006.258.00:02:12.38#ibcon#about to read 6, iclass 30, count 2 2006.258.00:02:12.38#ibcon#read 6, iclass 30, count 2 2006.258.00:02:12.38#ibcon#end of sib2, iclass 30, count 2 2006.258.00:02:12.38#ibcon#*after write, iclass 30, count 2 2006.258.00:02:12.38#ibcon#*before return 0, iclass 30, count 2 2006.258.00:02:12.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:12.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:02:12.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.00:02:12.38#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:12.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:12.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:12.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:12.50#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:02:12.50#ibcon#first serial, iclass 30, count 0 2006.258.00:02:12.50#ibcon#enter sib2, iclass 30, count 0 2006.258.00:02:12.50#ibcon#flushed, iclass 30, count 0 2006.258.00:02:12.50#ibcon#about to write, iclass 30, count 0 2006.258.00:02:12.50#ibcon#wrote, iclass 30, count 0 2006.258.00:02:12.50#ibcon#about to read 3, iclass 30, count 0 2006.258.00:02:12.51#abcon#<5=/01 1.7 5.1 21.41 791016.2\r\n> 2006.258.00:02:12.52#ibcon#read 3, iclass 30, count 0 2006.258.00:02:12.52#ibcon#about to read 4, iclass 30, count 0 2006.258.00:02:12.52#ibcon#read 4, iclass 30, count 0 2006.258.00:02:12.52#ibcon#about to read 5, iclass 30, count 0 2006.258.00:02:12.52#ibcon#read 5, iclass 30, count 0 2006.258.00:02:12.52#ibcon#about to read 6, iclass 30, count 0 2006.258.00:02:12.52#ibcon#read 6, iclass 30, count 0 2006.258.00:02:12.52#ibcon#end of sib2, iclass 30, count 0 2006.258.00:02:12.52#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:02:12.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:02:12.52#ibcon#[27=USB\r\n] 2006.258.00:02:12.52#ibcon#*before write, iclass 30, count 0 2006.258.00:02:12.52#ibcon#enter sib2, iclass 30, count 0 2006.258.00:02:12.52#ibcon#flushed, iclass 30, count 0 2006.258.00:02:12.52#ibcon#about to write, iclass 30, count 0 2006.258.00:02:12.52#ibcon#wrote, iclass 30, count 0 2006.258.00:02:12.52#ibcon#about to read 3, iclass 30, count 0 2006.258.00:02:12.53#abcon#{5=INTERFACE CLEAR} 2006.258.00:02:12.55#ibcon#read 3, iclass 30, count 0 2006.258.00:02:12.55#ibcon#about to read 4, iclass 30, count 0 2006.258.00:02:12.55#ibcon#read 4, iclass 30, count 0 2006.258.00:02:12.55#ibcon#about to read 5, iclass 30, count 0 2006.258.00:02:12.55#ibcon#read 5, iclass 30, count 0 2006.258.00:02:12.55#ibcon#about to read 6, iclass 30, count 0 2006.258.00:02:12.55#ibcon#read 6, iclass 30, count 0 2006.258.00:02:12.55#ibcon#end of sib2, iclass 30, count 0 2006.258.00:02:12.55#ibcon#*after write, iclass 30, count 0 2006.258.00:02:12.55#ibcon#*before return 0, iclass 30, count 0 2006.258.00:02:12.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:12.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:02:12.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:02:12.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:02:12.55$vck44/vblo=5,709.99 2006.258.00:02:12.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.00:02:12.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.00:02:12.55#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:12.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:02:12.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:02:12.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:02:12.55#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:02:12.55#ibcon#first serial, iclass 35, count 0 2006.258.00:02:12.55#ibcon#enter sib2, iclass 35, count 0 2006.258.00:02:12.55#ibcon#flushed, iclass 35, count 0 2006.258.00:02:12.55#ibcon#about to write, iclass 35, count 0 2006.258.00:02:12.55#ibcon#wrote, iclass 35, count 0 2006.258.00:02:12.55#ibcon#about to read 3, iclass 35, count 0 2006.258.00:02:12.57#ibcon#read 3, iclass 35, count 0 2006.258.00:02:12.57#ibcon#about to read 4, iclass 35, count 0 2006.258.00:02:12.57#ibcon#read 4, iclass 35, count 0 2006.258.00:02:12.57#ibcon#about to read 5, iclass 35, count 0 2006.258.00:02:12.57#ibcon#read 5, iclass 35, count 0 2006.258.00:02:12.57#ibcon#about to read 6, iclass 35, count 0 2006.258.00:02:12.57#ibcon#read 6, iclass 35, count 0 2006.258.00:02:12.57#ibcon#end of sib2, iclass 35, count 0 2006.258.00:02:12.57#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:02:12.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:02:12.57#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:02:12.57#ibcon#*before write, iclass 35, count 0 2006.258.00:02:12.57#ibcon#enter sib2, iclass 35, count 0 2006.258.00:02:12.57#ibcon#flushed, iclass 35, count 0 2006.258.00:02:12.57#ibcon#about to write, iclass 35, count 0 2006.258.00:02:12.57#ibcon#wrote, iclass 35, count 0 2006.258.00:02:12.57#ibcon#about to read 3, iclass 35, count 0 2006.258.00:02:12.59#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:02:12.61#ibcon#read 3, iclass 35, count 0 2006.258.00:02:12.61#ibcon#about to read 4, iclass 35, count 0 2006.258.00:02:12.61#ibcon#read 4, iclass 35, count 0 2006.258.00:02:12.61#ibcon#about to read 5, iclass 35, count 0 2006.258.00:02:12.61#ibcon#read 5, iclass 35, count 0 2006.258.00:02:12.61#ibcon#about to read 6, iclass 35, count 0 2006.258.00:02:12.61#ibcon#read 6, iclass 35, count 0 2006.258.00:02:12.61#ibcon#end of sib2, iclass 35, count 0 2006.258.00:02:12.61#ibcon#*after write, iclass 35, count 0 2006.258.00:02:12.61#ibcon#*before return 0, iclass 35, count 0 2006.258.00:02:12.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:02:12.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:02:12.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:02:12.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:02:12.61$vck44/vb=5,4 2006.258.00:02:12.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.258.00:02:12.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.258.00:02:12.61#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:12.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:12.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:12.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:12.67#ibcon#enter wrdev, iclass 38, count 2 2006.258.00:02:12.67#ibcon#first serial, iclass 38, count 2 2006.258.00:02:12.67#ibcon#enter sib2, iclass 38, count 2 2006.258.00:02:12.67#ibcon#flushed, iclass 38, count 2 2006.258.00:02:12.67#ibcon#about to write, iclass 38, count 2 2006.258.00:02:12.67#ibcon#wrote, iclass 38, count 2 2006.258.00:02:12.67#ibcon#about to read 3, iclass 38, count 2 2006.258.00:02:12.69#ibcon#read 3, iclass 38, count 2 2006.258.00:02:12.69#ibcon#about to read 4, iclass 38, count 2 2006.258.00:02:12.69#ibcon#read 4, iclass 38, count 2 2006.258.00:02:12.69#ibcon#about to read 5, iclass 38, count 2 2006.258.00:02:12.69#ibcon#read 5, iclass 38, count 2 2006.258.00:02:12.69#ibcon#about to read 6, iclass 38, count 2 2006.258.00:02:12.69#ibcon#read 6, iclass 38, count 2 2006.258.00:02:12.69#ibcon#end of sib2, iclass 38, count 2 2006.258.00:02:12.69#ibcon#*mode == 0, iclass 38, count 2 2006.258.00:02:12.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.258.00:02:12.69#ibcon#[27=AT05-04\r\n] 2006.258.00:02:12.69#ibcon#*before write, iclass 38, count 2 2006.258.00:02:12.69#ibcon#enter sib2, iclass 38, count 2 2006.258.00:02:12.69#ibcon#flushed, iclass 38, count 2 2006.258.00:02:12.69#ibcon#about to write, iclass 38, count 2 2006.258.00:02:12.69#ibcon#wrote, iclass 38, count 2 2006.258.00:02:12.69#ibcon#about to read 3, iclass 38, count 2 2006.258.00:02:12.72#ibcon#read 3, iclass 38, count 2 2006.258.00:02:12.72#ibcon#about to read 4, iclass 38, count 2 2006.258.00:02:12.72#ibcon#read 4, iclass 38, count 2 2006.258.00:02:12.72#ibcon#about to read 5, iclass 38, count 2 2006.258.00:02:12.72#ibcon#read 5, iclass 38, count 2 2006.258.00:02:12.72#ibcon#about to read 6, iclass 38, count 2 2006.258.00:02:12.72#ibcon#read 6, iclass 38, count 2 2006.258.00:02:12.72#ibcon#end of sib2, iclass 38, count 2 2006.258.00:02:12.72#ibcon#*after write, iclass 38, count 2 2006.258.00:02:12.72#ibcon#*before return 0, iclass 38, count 2 2006.258.00:02:12.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:12.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:02:12.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.258.00:02:12.72#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:12.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:12.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:12.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:12.84#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:02:12.84#ibcon#first serial, iclass 38, count 0 2006.258.00:02:12.84#ibcon#enter sib2, iclass 38, count 0 2006.258.00:02:12.84#ibcon#flushed, iclass 38, count 0 2006.258.00:02:12.84#ibcon#about to write, iclass 38, count 0 2006.258.00:02:12.84#ibcon#wrote, iclass 38, count 0 2006.258.00:02:12.84#ibcon#about to read 3, iclass 38, count 0 2006.258.00:02:12.86#ibcon#read 3, iclass 38, count 0 2006.258.00:02:12.86#ibcon#about to read 4, iclass 38, count 0 2006.258.00:02:12.86#ibcon#read 4, iclass 38, count 0 2006.258.00:02:12.86#ibcon#about to read 5, iclass 38, count 0 2006.258.00:02:12.86#ibcon#read 5, iclass 38, count 0 2006.258.00:02:12.86#ibcon#about to read 6, iclass 38, count 0 2006.258.00:02:12.86#ibcon#read 6, iclass 38, count 0 2006.258.00:02:12.86#ibcon#end of sib2, iclass 38, count 0 2006.258.00:02:12.86#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:02:12.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:02:12.86#ibcon#[27=USB\r\n] 2006.258.00:02:12.86#ibcon#*before write, iclass 38, count 0 2006.258.00:02:12.86#ibcon#enter sib2, iclass 38, count 0 2006.258.00:02:12.86#ibcon#flushed, iclass 38, count 0 2006.258.00:02:12.86#ibcon#about to write, iclass 38, count 0 2006.258.00:02:12.86#ibcon#wrote, iclass 38, count 0 2006.258.00:02:12.86#ibcon#about to read 3, iclass 38, count 0 2006.258.00:02:12.89#ibcon#read 3, iclass 38, count 0 2006.258.00:02:12.89#ibcon#about to read 4, iclass 38, count 0 2006.258.00:02:12.89#ibcon#read 4, iclass 38, count 0 2006.258.00:02:12.89#ibcon#about to read 5, iclass 38, count 0 2006.258.00:02:12.89#ibcon#read 5, iclass 38, count 0 2006.258.00:02:12.89#ibcon#about to read 6, iclass 38, count 0 2006.258.00:02:12.89#ibcon#read 6, iclass 38, count 0 2006.258.00:02:12.89#ibcon#end of sib2, iclass 38, count 0 2006.258.00:02:12.89#ibcon#*after write, iclass 38, count 0 2006.258.00:02:12.89#ibcon#*before return 0, iclass 38, count 0 2006.258.00:02:12.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:12.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:02:12.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:02:12.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:02:12.89$vck44/vblo=6,719.99 2006.258.00:02:12.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.00:02:12.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.00:02:12.89#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:12.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:12.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:12.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:12.89#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:02:12.89#ibcon#first serial, iclass 40, count 0 2006.258.00:02:12.89#ibcon#enter sib2, iclass 40, count 0 2006.258.00:02:12.89#ibcon#flushed, iclass 40, count 0 2006.258.00:02:12.89#ibcon#about to write, iclass 40, count 0 2006.258.00:02:12.89#ibcon#wrote, iclass 40, count 0 2006.258.00:02:12.89#ibcon#about to read 3, iclass 40, count 0 2006.258.00:02:12.91#ibcon#read 3, iclass 40, count 0 2006.258.00:02:12.91#ibcon#about to read 4, iclass 40, count 0 2006.258.00:02:12.91#ibcon#read 4, iclass 40, count 0 2006.258.00:02:12.91#ibcon#about to read 5, iclass 40, count 0 2006.258.00:02:12.91#ibcon#read 5, iclass 40, count 0 2006.258.00:02:12.91#ibcon#about to read 6, iclass 40, count 0 2006.258.00:02:12.91#ibcon#read 6, iclass 40, count 0 2006.258.00:02:12.91#ibcon#end of sib2, iclass 40, count 0 2006.258.00:02:12.91#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:02:12.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:02:12.91#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:02:12.91#ibcon#*before write, iclass 40, count 0 2006.258.00:02:12.91#ibcon#enter sib2, iclass 40, count 0 2006.258.00:02:12.91#ibcon#flushed, iclass 40, count 0 2006.258.00:02:12.91#ibcon#about to write, iclass 40, count 0 2006.258.00:02:12.91#ibcon#wrote, iclass 40, count 0 2006.258.00:02:12.91#ibcon#about to read 3, iclass 40, count 0 2006.258.00:02:12.95#ibcon#read 3, iclass 40, count 0 2006.258.00:02:12.95#ibcon#about to read 4, iclass 40, count 0 2006.258.00:02:12.95#ibcon#read 4, iclass 40, count 0 2006.258.00:02:12.95#ibcon#about to read 5, iclass 40, count 0 2006.258.00:02:12.95#ibcon#read 5, iclass 40, count 0 2006.258.00:02:12.95#ibcon#about to read 6, iclass 40, count 0 2006.258.00:02:12.95#ibcon#read 6, iclass 40, count 0 2006.258.00:02:12.95#ibcon#end of sib2, iclass 40, count 0 2006.258.00:02:12.95#ibcon#*after write, iclass 40, count 0 2006.258.00:02:12.95#ibcon#*before return 0, iclass 40, count 0 2006.258.00:02:12.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:12.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:02:12.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:02:12.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:02:12.95$vck44/vb=6,4 2006.258.00:02:12.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.258.00:02:12.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.258.00:02:12.95#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:12.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:13.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:13.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:13.01#ibcon#enter wrdev, iclass 4, count 2 2006.258.00:02:13.01#ibcon#first serial, iclass 4, count 2 2006.258.00:02:13.01#ibcon#enter sib2, iclass 4, count 2 2006.258.00:02:13.01#ibcon#flushed, iclass 4, count 2 2006.258.00:02:13.01#ibcon#about to write, iclass 4, count 2 2006.258.00:02:13.01#ibcon#wrote, iclass 4, count 2 2006.258.00:02:13.01#ibcon#about to read 3, iclass 4, count 2 2006.258.00:02:13.03#ibcon#read 3, iclass 4, count 2 2006.258.00:02:13.03#ibcon#about to read 4, iclass 4, count 2 2006.258.00:02:13.03#ibcon#read 4, iclass 4, count 2 2006.258.00:02:13.03#ibcon#about to read 5, iclass 4, count 2 2006.258.00:02:13.03#ibcon#read 5, iclass 4, count 2 2006.258.00:02:13.03#ibcon#about to read 6, iclass 4, count 2 2006.258.00:02:13.03#ibcon#read 6, iclass 4, count 2 2006.258.00:02:13.03#ibcon#end of sib2, iclass 4, count 2 2006.258.00:02:13.03#ibcon#*mode == 0, iclass 4, count 2 2006.258.00:02:13.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.258.00:02:13.03#ibcon#[27=AT06-04\r\n] 2006.258.00:02:13.03#ibcon#*before write, iclass 4, count 2 2006.258.00:02:13.03#ibcon#enter sib2, iclass 4, count 2 2006.258.00:02:13.03#ibcon#flushed, iclass 4, count 2 2006.258.00:02:13.03#ibcon#about to write, iclass 4, count 2 2006.258.00:02:13.03#ibcon#wrote, iclass 4, count 2 2006.258.00:02:13.03#ibcon#about to read 3, iclass 4, count 2 2006.258.00:02:13.06#ibcon#read 3, iclass 4, count 2 2006.258.00:02:13.06#ibcon#about to read 4, iclass 4, count 2 2006.258.00:02:13.06#ibcon#read 4, iclass 4, count 2 2006.258.00:02:13.06#ibcon#about to read 5, iclass 4, count 2 2006.258.00:02:13.06#ibcon#read 5, iclass 4, count 2 2006.258.00:02:13.06#ibcon#about to read 6, iclass 4, count 2 2006.258.00:02:13.06#ibcon#read 6, iclass 4, count 2 2006.258.00:02:13.06#ibcon#end of sib2, iclass 4, count 2 2006.258.00:02:13.06#ibcon#*after write, iclass 4, count 2 2006.258.00:02:13.06#ibcon#*before return 0, iclass 4, count 2 2006.258.00:02:13.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:13.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:02:13.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.258.00:02:13.06#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:13.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:13.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:13.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:13.18#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:02:13.18#ibcon#first serial, iclass 4, count 0 2006.258.00:02:13.18#ibcon#enter sib2, iclass 4, count 0 2006.258.00:02:13.18#ibcon#flushed, iclass 4, count 0 2006.258.00:02:13.18#ibcon#about to write, iclass 4, count 0 2006.258.00:02:13.18#ibcon#wrote, iclass 4, count 0 2006.258.00:02:13.18#ibcon#about to read 3, iclass 4, count 0 2006.258.00:02:13.20#ibcon#read 3, iclass 4, count 0 2006.258.00:02:13.20#ibcon#about to read 4, iclass 4, count 0 2006.258.00:02:13.20#ibcon#read 4, iclass 4, count 0 2006.258.00:02:13.20#ibcon#about to read 5, iclass 4, count 0 2006.258.00:02:13.20#ibcon#read 5, iclass 4, count 0 2006.258.00:02:13.20#ibcon#about to read 6, iclass 4, count 0 2006.258.00:02:13.20#ibcon#read 6, iclass 4, count 0 2006.258.00:02:13.20#ibcon#end of sib2, iclass 4, count 0 2006.258.00:02:13.20#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:02:13.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:02:13.20#ibcon#[27=USB\r\n] 2006.258.00:02:13.20#ibcon#*before write, iclass 4, count 0 2006.258.00:02:13.20#ibcon#enter sib2, iclass 4, count 0 2006.258.00:02:13.20#ibcon#flushed, iclass 4, count 0 2006.258.00:02:13.20#ibcon#about to write, iclass 4, count 0 2006.258.00:02:13.20#ibcon#wrote, iclass 4, count 0 2006.258.00:02:13.20#ibcon#about to read 3, iclass 4, count 0 2006.258.00:02:13.23#ibcon#read 3, iclass 4, count 0 2006.258.00:02:13.23#ibcon#about to read 4, iclass 4, count 0 2006.258.00:02:13.23#ibcon#read 4, iclass 4, count 0 2006.258.00:02:13.23#ibcon#about to read 5, iclass 4, count 0 2006.258.00:02:13.23#ibcon#read 5, iclass 4, count 0 2006.258.00:02:13.23#ibcon#about to read 6, iclass 4, count 0 2006.258.00:02:13.23#ibcon#read 6, iclass 4, count 0 2006.258.00:02:13.23#ibcon#end of sib2, iclass 4, count 0 2006.258.00:02:13.23#ibcon#*after write, iclass 4, count 0 2006.258.00:02:13.23#ibcon#*before return 0, iclass 4, count 0 2006.258.00:02:13.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:13.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:02:13.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:02:13.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:02:13.23$vck44/vblo=7,734.99 2006.258.00:02:13.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.00:02:13.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.00:02:13.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:13.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:13.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:13.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:13.23#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:02:13.23#ibcon#first serial, iclass 6, count 0 2006.258.00:02:13.23#ibcon#enter sib2, iclass 6, count 0 2006.258.00:02:13.23#ibcon#flushed, iclass 6, count 0 2006.258.00:02:13.23#ibcon#about to write, iclass 6, count 0 2006.258.00:02:13.23#ibcon#wrote, iclass 6, count 0 2006.258.00:02:13.23#ibcon#about to read 3, iclass 6, count 0 2006.258.00:02:13.25#ibcon#read 3, iclass 6, count 0 2006.258.00:02:13.25#ibcon#about to read 4, iclass 6, count 0 2006.258.00:02:13.25#ibcon#read 4, iclass 6, count 0 2006.258.00:02:13.25#ibcon#about to read 5, iclass 6, count 0 2006.258.00:02:13.25#ibcon#read 5, iclass 6, count 0 2006.258.00:02:13.25#ibcon#about to read 6, iclass 6, count 0 2006.258.00:02:13.25#ibcon#read 6, iclass 6, count 0 2006.258.00:02:13.25#ibcon#end of sib2, iclass 6, count 0 2006.258.00:02:13.25#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:02:13.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:02:13.25#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:02:13.25#ibcon#*before write, iclass 6, count 0 2006.258.00:02:13.25#ibcon#enter sib2, iclass 6, count 0 2006.258.00:02:13.25#ibcon#flushed, iclass 6, count 0 2006.258.00:02:13.25#ibcon#about to write, iclass 6, count 0 2006.258.00:02:13.25#ibcon#wrote, iclass 6, count 0 2006.258.00:02:13.25#ibcon#about to read 3, iclass 6, count 0 2006.258.00:02:13.29#ibcon#read 3, iclass 6, count 0 2006.258.00:02:13.29#ibcon#about to read 4, iclass 6, count 0 2006.258.00:02:13.29#ibcon#read 4, iclass 6, count 0 2006.258.00:02:13.29#ibcon#about to read 5, iclass 6, count 0 2006.258.00:02:13.29#ibcon#read 5, iclass 6, count 0 2006.258.00:02:13.29#ibcon#about to read 6, iclass 6, count 0 2006.258.00:02:13.29#ibcon#read 6, iclass 6, count 0 2006.258.00:02:13.29#ibcon#end of sib2, iclass 6, count 0 2006.258.00:02:13.29#ibcon#*after write, iclass 6, count 0 2006.258.00:02:13.29#ibcon#*before return 0, iclass 6, count 0 2006.258.00:02:13.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:13.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:02:13.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:02:13.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:02:13.29$vck44/vb=7,4 2006.258.00:02:13.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.258.00:02:13.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.258.00:02:13.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:13.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:13.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:13.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:13.35#ibcon#enter wrdev, iclass 10, count 2 2006.258.00:02:13.35#ibcon#first serial, iclass 10, count 2 2006.258.00:02:13.35#ibcon#enter sib2, iclass 10, count 2 2006.258.00:02:13.35#ibcon#flushed, iclass 10, count 2 2006.258.00:02:13.35#ibcon#about to write, iclass 10, count 2 2006.258.00:02:13.35#ibcon#wrote, iclass 10, count 2 2006.258.00:02:13.35#ibcon#about to read 3, iclass 10, count 2 2006.258.00:02:13.37#ibcon#read 3, iclass 10, count 2 2006.258.00:02:13.37#ibcon#about to read 4, iclass 10, count 2 2006.258.00:02:13.37#ibcon#read 4, iclass 10, count 2 2006.258.00:02:13.37#ibcon#about to read 5, iclass 10, count 2 2006.258.00:02:13.37#ibcon#read 5, iclass 10, count 2 2006.258.00:02:13.37#ibcon#about to read 6, iclass 10, count 2 2006.258.00:02:13.37#ibcon#read 6, iclass 10, count 2 2006.258.00:02:13.37#ibcon#end of sib2, iclass 10, count 2 2006.258.00:02:13.37#ibcon#*mode == 0, iclass 10, count 2 2006.258.00:02:13.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.258.00:02:13.37#ibcon#[27=AT07-04\r\n] 2006.258.00:02:13.37#ibcon#*before write, iclass 10, count 2 2006.258.00:02:13.37#ibcon#enter sib2, iclass 10, count 2 2006.258.00:02:13.37#ibcon#flushed, iclass 10, count 2 2006.258.00:02:13.37#ibcon#about to write, iclass 10, count 2 2006.258.00:02:13.37#ibcon#wrote, iclass 10, count 2 2006.258.00:02:13.37#ibcon#about to read 3, iclass 10, count 2 2006.258.00:02:13.42#ibcon#read 3, iclass 10, count 2 2006.258.00:02:13.42#ibcon#about to read 4, iclass 10, count 2 2006.258.00:02:13.42#ibcon#read 4, iclass 10, count 2 2006.258.00:02:13.42#ibcon#about to read 5, iclass 10, count 2 2006.258.00:02:13.42#ibcon#read 5, iclass 10, count 2 2006.258.00:02:13.42#ibcon#about to read 6, iclass 10, count 2 2006.258.00:02:13.42#ibcon#read 6, iclass 10, count 2 2006.258.00:02:13.42#ibcon#end of sib2, iclass 10, count 2 2006.258.00:02:13.42#ibcon#*after write, iclass 10, count 2 2006.258.00:02:13.42#ibcon#*before return 0, iclass 10, count 2 2006.258.00:02:13.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:13.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:02:13.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.258.00:02:13.42#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:13.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:13.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:13.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:13.54#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:02:13.54#ibcon#first serial, iclass 10, count 0 2006.258.00:02:13.54#ibcon#enter sib2, iclass 10, count 0 2006.258.00:02:13.54#ibcon#flushed, iclass 10, count 0 2006.258.00:02:13.54#ibcon#about to write, iclass 10, count 0 2006.258.00:02:13.54#ibcon#wrote, iclass 10, count 0 2006.258.00:02:13.54#ibcon#about to read 3, iclass 10, count 0 2006.258.00:02:13.56#ibcon#read 3, iclass 10, count 0 2006.258.00:02:13.56#ibcon#about to read 4, iclass 10, count 0 2006.258.00:02:13.56#ibcon#read 4, iclass 10, count 0 2006.258.00:02:13.56#ibcon#about to read 5, iclass 10, count 0 2006.258.00:02:13.56#ibcon#read 5, iclass 10, count 0 2006.258.00:02:13.56#ibcon#about to read 6, iclass 10, count 0 2006.258.00:02:13.56#ibcon#read 6, iclass 10, count 0 2006.258.00:02:13.56#ibcon#end of sib2, iclass 10, count 0 2006.258.00:02:13.56#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:02:13.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:02:13.56#ibcon#[27=USB\r\n] 2006.258.00:02:13.56#ibcon#*before write, iclass 10, count 0 2006.258.00:02:13.56#ibcon#enter sib2, iclass 10, count 0 2006.258.00:02:13.56#ibcon#flushed, iclass 10, count 0 2006.258.00:02:13.56#ibcon#about to write, iclass 10, count 0 2006.258.00:02:13.56#ibcon#wrote, iclass 10, count 0 2006.258.00:02:13.56#ibcon#about to read 3, iclass 10, count 0 2006.258.00:02:13.59#ibcon#read 3, iclass 10, count 0 2006.258.00:02:13.59#ibcon#about to read 4, iclass 10, count 0 2006.258.00:02:13.59#ibcon#read 4, iclass 10, count 0 2006.258.00:02:13.59#ibcon#about to read 5, iclass 10, count 0 2006.258.00:02:13.59#ibcon#read 5, iclass 10, count 0 2006.258.00:02:13.59#ibcon#about to read 6, iclass 10, count 0 2006.258.00:02:13.59#ibcon#read 6, iclass 10, count 0 2006.258.00:02:13.59#ibcon#end of sib2, iclass 10, count 0 2006.258.00:02:13.59#ibcon#*after write, iclass 10, count 0 2006.258.00:02:13.59#ibcon#*before return 0, iclass 10, count 0 2006.258.00:02:13.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:13.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:02:13.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:02:13.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:02:13.59$vck44/vblo=8,744.99 2006.258.00:02:13.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.00:02:13.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.00:02:13.59#ibcon#ireg 17 cls_cnt 0 2006.258.00:02:13.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:13.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:13.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:13.59#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:02:13.59#ibcon#first serial, iclass 12, count 0 2006.258.00:02:13.59#ibcon#enter sib2, iclass 12, count 0 2006.258.00:02:13.59#ibcon#flushed, iclass 12, count 0 2006.258.00:02:13.59#ibcon#about to write, iclass 12, count 0 2006.258.00:02:13.59#ibcon#wrote, iclass 12, count 0 2006.258.00:02:13.59#ibcon#about to read 3, iclass 12, count 0 2006.258.00:02:13.61#ibcon#read 3, iclass 12, count 0 2006.258.00:02:13.61#ibcon#about to read 4, iclass 12, count 0 2006.258.00:02:13.61#ibcon#read 4, iclass 12, count 0 2006.258.00:02:13.61#ibcon#about to read 5, iclass 12, count 0 2006.258.00:02:13.61#ibcon#read 5, iclass 12, count 0 2006.258.00:02:13.61#ibcon#about to read 6, iclass 12, count 0 2006.258.00:02:13.61#ibcon#read 6, iclass 12, count 0 2006.258.00:02:13.61#ibcon#end of sib2, iclass 12, count 0 2006.258.00:02:13.61#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:02:13.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:02:13.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:02:13.61#ibcon#*before write, iclass 12, count 0 2006.258.00:02:13.61#ibcon#enter sib2, iclass 12, count 0 2006.258.00:02:13.61#ibcon#flushed, iclass 12, count 0 2006.258.00:02:13.61#ibcon#about to write, iclass 12, count 0 2006.258.00:02:13.61#ibcon#wrote, iclass 12, count 0 2006.258.00:02:13.61#ibcon#about to read 3, iclass 12, count 0 2006.258.00:02:13.65#ibcon#read 3, iclass 12, count 0 2006.258.00:02:13.65#ibcon#about to read 4, iclass 12, count 0 2006.258.00:02:13.65#ibcon#read 4, iclass 12, count 0 2006.258.00:02:13.65#ibcon#about to read 5, iclass 12, count 0 2006.258.00:02:13.65#ibcon#read 5, iclass 12, count 0 2006.258.00:02:13.65#ibcon#about to read 6, iclass 12, count 0 2006.258.00:02:13.65#ibcon#read 6, iclass 12, count 0 2006.258.00:02:13.65#ibcon#end of sib2, iclass 12, count 0 2006.258.00:02:13.65#ibcon#*after write, iclass 12, count 0 2006.258.00:02:13.65#ibcon#*before return 0, iclass 12, count 0 2006.258.00:02:13.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:13.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:02:13.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:02:13.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:02:13.65$vck44/vb=8,4 2006.258.00:02:13.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.258.00:02:13.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.258.00:02:13.65#ibcon#ireg 11 cls_cnt 2 2006.258.00:02:13.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:13.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:13.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:13.71#ibcon#enter wrdev, iclass 14, count 2 2006.258.00:02:13.71#ibcon#first serial, iclass 14, count 2 2006.258.00:02:13.71#ibcon#enter sib2, iclass 14, count 2 2006.258.00:02:13.71#ibcon#flushed, iclass 14, count 2 2006.258.00:02:13.71#ibcon#about to write, iclass 14, count 2 2006.258.00:02:13.71#ibcon#wrote, iclass 14, count 2 2006.258.00:02:13.71#ibcon#about to read 3, iclass 14, count 2 2006.258.00:02:13.73#ibcon#read 3, iclass 14, count 2 2006.258.00:02:13.73#ibcon#about to read 4, iclass 14, count 2 2006.258.00:02:13.73#ibcon#read 4, iclass 14, count 2 2006.258.00:02:13.73#ibcon#about to read 5, iclass 14, count 2 2006.258.00:02:13.73#ibcon#read 5, iclass 14, count 2 2006.258.00:02:13.73#ibcon#about to read 6, iclass 14, count 2 2006.258.00:02:13.73#ibcon#read 6, iclass 14, count 2 2006.258.00:02:13.73#ibcon#end of sib2, iclass 14, count 2 2006.258.00:02:13.73#ibcon#*mode == 0, iclass 14, count 2 2006.258.00:02:13.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.258.00:02:13.73#ibcon#[27=AT08-04\r\n] 2006.258.00:02:13.73#ibcon#*before write, iclass 14, count 2 2006.258.00:02:13.73#ibcon#enter sib2, iclass 14, count 2 2006.258.00:02:13.73#ibcon#flushed, iclass 14, count 2 2006.258.00:02:13.73#ibcon#about to write, iclass 14, count 2 2006.258.00:02:13.73#ibcon#wrote, iclass 14, count 2 2006.258.00:02:13.73#ibcon#about to read 3, iclass 14, count 2 2006.258.00:02:13.76#ibcon#read 3, iclass 14, count 2 2006.258.00:02:13.76#ibcon#about to read 4, iclass 14, count 2 2006.258.00:02:13.76#ibcon#read 4, iclass 14, count 2 2006.258.00:02:13.76#ibcon#about to read 5, iclass 14, count 2 2006.258.00:02:13.76#ibcon#read 5, iclass 14, count 2 2006.258.00:02:13.76#ibcon#about to read 6, iclass 14, count 2 2006.258.00:02:13.76#ibcon#read 6, iclass 14, count 2 2006.258.00:02:13.76#ibcon#end of sib2, iclass 14, count 2 2006.258.00:02:13.76#ibcon#*after write, iclass 14, count 2 2006.258.00:02:13.76#ibcon#*before return 0, iclass 14, count 2 2006.258.00:02:13.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:13.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:02:13.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.258.00:02:13.76#ibcon#ireg 7 cls_cnt 0 2006.258.00:02:13.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:13.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:13.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:13.88#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:02:13.88#ibcon#first serial, iclass 14, count 0 2006.258.00:02:13.88#ibcon#enter sib2, iclass 14, count 0 2006.258.00:02:13.88#ibcon#flushed, iclass 14, count 0 2006.258.00:02:13.88#ibcon#about to write, iclass 14, count 0 2006.258.00:02:13.88#ibcon#wrote, iclass 14, count 0 2006.258.00:02:13.88#ibcon#about to read 3, iclass 14, count 0 2006.258.00:02:13.90#ibcon#read 3, iclass 14, count 0 2006.258.00:02:13.90#ibcon#about to read 4, iclass 14, count 0 2006.258.00:02:13.90#ibcon#read 4, iclass 14, count 0 2006.258.00:02:13.90#ibcon#about to read 5, iclass 14, count 0 2006.258.00:02:13.90#ibcon#read 5, iclass 14, count 0 2006.258.00:02:13.90#ibcon#about to read 6, iclass 14, count 0 2006.258.00:02:13.90#ibcon#read 6, iclass 14, count 0 2006.258.00:02:13.90#ibcon#end of sib2, iclass 14, count 0 2006.258.00:02:13.90#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:02:13.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:02:13.90#ibcon#[27=USB\r\n] 2006.258.00:02:13.90#ibcon#*before write, iclass 14, count 0 2006.258.00:02:13.90#ibcon#enter sib2, iclass 14, count 0 2006.258.00:02:13.90#ibcon#flushed, iclass 14, count 0 2006.258.00:02:13.90#ibcon#about to write, iclass 14, count 0 2006.258.00:02:13.90#ibcon#wrote, iclass 14, count 0 2006.258.00:02:13.90#ibcon#about to read 3, iclass 14, count 0 2006.258.00:02:13.93#ibcon#read 3, iclass 14, count 0 2006.258.00:02:13.93#ibcon#about to read 4, iclass 14, count 0 2006.258.00:02:13.93#ibcon#read 4, iclass 14, count 0 2006.258.00:02:13.93#ibcon#about to read 5, iclass 14, count 0 2006.258.00:02:13.93#ibcon#read 5, iclass 14, count 0 2006.258.00:02:13.93#ibcon#about to read 6, iclass 14, count 0 2006.258.00:02:13.93#ibcon#read 6, iclass 14, count 0 2006.258.00:02:13.93#ibcon#end of sib2, iclass 14, count 0 2006.258.00:02:13.93#ibcon#*after write, iclass 14, count 0 2006.258.00:02:13.93#ibcon#*before return 0, iclass 14, count 0 2006.258.00:02:13.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:13.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:02:13.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:02:13.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:02:13.93$vck44/vabw=wide 2006.258.00:02:13.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.00:02:13.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.00:02:13.93#ibcon#ireg 8 cls_cnt 0 2006.258.00:02:13.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:13.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:13.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:13.93#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:02:13.93#ibcon#first serial, iclass 16, count 0 2006.258.00:02:13.93#ibcon#enter sib2, iclass 16, count 0 2006.258.00:02:13.93#ibcon#flushed, iclass 16, count 0 2006.258.00:02:13.93#ibcon#about to write, iclass 16, count 0 2006.258.00:02:13.93#ibcon#wrote, iclass 16, count 0 2006.258.00:02:13.93#ibcon#about to read 3, iclass 16, count 0 2006.258.00:02:13.95#ibcon#read 3, iclass 16, count 0 2006.258.00:02:13.95#ibcon#about to read 4, iclass 16, count 0 2006.258.00:02:13.95#ibcon#read 4, iclass 16, count 0 2006.258.00:02:13.95#ibcon#about to read 5, iclass 16, count 0 2006.258.00:02:13.95#ibcon#read 5, iclass 16, count 0 2006.258.00:02:13.95#ibcon#about to read 6, iclass 16, count 0 2006.258.00:02:13.95#ibcon#read 6, iclass 16, count 0 2006.258.00:02:13.95#ibcon#end of sib2, iclass 16, count 0 2006.258.00:02:13.95#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:02:13.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:02:13.95#ibcon#[25=BW32\r\n] 2006.258.00:02:13.95#ibcon#*before write, iclass 16, count 0 2006.258.00:02:13.95#ibcon#enter sib2, iclass 16, count 0 2006.258.00:02:13.95#ibcon#flushed, iclass 16, count 0 2006.258.00:02:13.95#ibcon#about to write, iclass 16, count 0 2006.258.00:02:13.95#ibcon#wrote, iclass 16, count 0 2006.258.00:02:13.95#ibcon#about to read 3, iclass 16, count 0 2006.258.00:02:13.98#ibcon#read 3, iclass 16, count 0 2006.258.00:02:13.98#ibcon#about to read 4, iclass 16, count 0 2006.258.00:02:13.98#ibcon#read 4, iclass 16, count 0 2006.258.00:02:13.98#ibcon#about to read 5, iclass 16, count 0 2006.258.00:02:13.98#ibcon#read 5, iclass 16, count 0 2006.258.00:02:13.98#ibcon#about to read 6, iclass 16, count 0 2006.258.00:02:13.98#ibcon#read 6, iclass 16, count 0 2006.258.00:02:13.98#ibcon#end of sib2, iclass 16, count 0 2006.258.00:02:13.98#ibcon#*after write, iclass 16, count 0 2006.258.00:02:13.98#ibcon#*before return 0, iclass 16, count 0 2006.258.00:02:13.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:13.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:02:13.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:02:13.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:02:13.98$vck44/vbbw=wide 2006.258.00:02:13.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.00:02:13.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.00:02:13.98#ibcon#ireg 8 cls_cnt 0 2006.258.00:02:13.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:02:14.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:02:14.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:02:14.05#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:02:14.05#ibcon#first serial, iclass 18, count 0 2006.258.00:02:14.05#ibcon#enter sib2, iclass 18, count 0 2006.258.00:02:14.05#ibcon#flushed, iclass 18, count 0 2006.258.00:02:14.05#ibcon#about to write, iclass 18, count 0 2006.258.00:02:14.05#ibcon#wrote, iclass 18, count 0 2006.258.00:02:14.05#ibcon#about to read 3, iclass 18, count 0 2006.258.00:02:14.07#ibcon#read 3, iclass 18, count 0 2006.258.00:02:14.07#ibcon#about to read 4, iclass 18, count 0 2006.258.00:02:14.07#ibcon#read 4, iclass 18, count 0 2006.258.00:02:14.07#ibcon#about to read 5, iclass 18, count 0 2006.258.00:02:14.07#ibcon#read 5, iclass 18, count 0 2006.258.00:02:14.07#ibcon#about to read 6, iclass 18, count 0 2006.258.00:02:14.07#ibcon#read 6, iclass 18, count 0 2006.258.00:02:14.07#ibcon#end of sib2, iclass 18, count 0 2006.258.00:02:14.07#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:02:14.07#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:02:14.07#ibcon#[27=BW32\r\n] 2006.258.00:02:14.07#ibcon#*before write, iclass 18, count 0 2006.258.00:02:14.07#ibcon#enter sib2, iclass 18, count 0 2006.258.00:02:14.07#ibcon#flushed, iclass 18, count 0 2006.258.00:02:14.07#ibcon#about to write, iclass 18, count 0 2006.258.00:02:14.07#ibcon#wrote, iclass 18, count 0 2006.258.00:02:14.07#ibcon#about to read 3, iclass 18, count 0 2006.258.00:02:14.10#ibcon#read 3, iclass 18, count 0 2006.258.00:02:14.10#ibcon#about to read 4, iclass 18, count 0 2006.258.00:02:14.10#ibcon#read 4, iclass 18, count 0 2006.258.00:02:14.10#ibcon#about to read 5, iclass 18, count 0 2006.258.00:02:14.10#ibcon#read 5, iclass 18, count 0 2006.258.00:02:14.10#ibcon#about to read 6, iclass 18, count 0 2006.258.00:02:14.10#ibcon#read 6, iclass 18, count 0 2006.258.00:02:14.10#ibcon#end of sib2, iclass 18, count 0 2006.258.00:02:14.10#ibcon#*after write, iclass 18, count 0 2006.258.00:02:14.10#ibcon#*before return 0, iclass 18, count 0 2006.258.00:02:14.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:02:14.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:02:14.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:02:14.10#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:02:14.10$setupk4/ifdk4 2006.258.00:02:14.10$ifdk4/lo= 2006.258.00:02:14.10$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:02:14.10$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:02:14.10$ifdk4/patch= 2006.258.00:02:14.10$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:02:14.10$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:02:14.10$setupk4/!*+20s 2006.258.00:02:22.68#abcon#<5=/01 1.7 5.1 21.42 791016.2\r\n> 2006.258.00:02:22.70#abcon#{5=INTERFACE CLEAR} 2006.258.00:02:22.76#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:02:28.59$setupk4/"tpicd 2006.258.00:02:28.59$setupk4/echo=off 2006.258.00:02:28.59$setupk4/xlog=off 2006.258.00:02:28.59:!2006.258.00:02:51 2006.258.00:02:36.14#trakl#Source acquired 2006.258.00:02:37.14#flagr#flagr/antenna,acquired 2006.258.00:02:51.02:preob 2006.258.00:02:52.14/onsource/TRACKING 2006.258.00:02:52.14:!2006.258.00:03:01 2006.258.00:03:01.02:"tape 2006.258.00:03:01.02:"st=record 2006.258.00:03:01.02:data_valid=on 2006.258.00:03:01.02:midob 2006.258.00:03:02.14/onsource/TRACKING 2006.258.00:03:02.14/wx/21.45,1016.3,78 2006.258.00:03:02.27/cable/+6.4811E-03 2006.258.00:03:03.36/va/01,08,usb,yes,38,41 2006.258.00:03:03.36/va/02,07,usb,yes,41,42 2006.258.00:03:03.36/va/03,08,usb,yes,37,39 2006.258.00:03:03.36/va/04,07,usb,yes,42,44 2006.258.00:03:03.36/va/05,04,usb,yes,38,38 2006.258.00:03:03.36/va/06,04,usb,yes,42,41 2006.258.00:03:03.36/va/07,04,usb,yes,43,44 2006.258.00:03:03.36/va/08,04,usb,yes,36,44 2006.258.00:03:03.59/valo/01,524.99,yes,locked 2006.258.00:03:03.59/valo/02,534.99,yes,locked 2006.258.00:03:03.59/valo/03,564.99,yes,locked 2006.258.00:03:03.59/valo/04,624.99,yes,locked 2006.258.00:03:03.59/valo/05,734.99,yes,locked 2006.258.00:03:03.59/valo/06,814.99,yes,locked 2006.258.00:03:03.59/valo/07,864.99,yes,locked 2006.258.00:03:03.59/valo/08,884.99,yes,locked 2006.258.00:03:04.68/vb/01,04,usb,yes,36,34 2006.258.00:03:04.68/vb/02,05,usb,yes,34,34 2006.258.00:03:04.68/vb/03,04,usb,yes,35,39 2006.258.00:03:04.68/vb/04,05,usb,yes,36,35 2006.258.00:03:04.68/vb/05,04,usb,yes,32,35 2006.258.00:03:04.68/vb/06,04,usb,yes,37,33 2006.258.00:03:04.68/vb/07,04,usb,yes,37,37 2006.258.00:03:04.68/vb/08,04,usb,yes,34,38 2006.258.00:03:04.92/vblo/01,629.99,yes,locked 2006.258.00:03:04.92/vblo/02,634.99,yes,locked 2006.258.00:03:04.92/vblo/03,649.99,yes,locked 2006.258.00:03:04.92/vblo/04,679.99,yes,locked 2006.258.00:03:04.92/vblo/05,709.99,yes,locked 2006.258.00:03:04.92/vblo/06,719.99,yes,locked 2006.258.00:03:04.92/vblo/07,734.99,yes,locked 2006.258.00:03:04.92/vblo/08,744.99,yes,locked 2006.258.00:03:05.07/vabw/8 2006.258.00:03:05.21/vbbw/8 2006.258.00:03:05.31/xfe/off,on,15.0 2006.258.00:03:05.70/ifatt/23,28,28,28 2006.258.00:03:06.08/fmout-gps/S +4.55E-07 2006.258.00:03:06.12:!2006.258.00:03:51 2006.258.00:03:51.02:data_valid=off 2006.258.00:03:51.02:"et 2006.258.00:03:51.02:!+3s 2006.258.00:03:54.04:"tape 2006.258.00:03:54.05:postob 2006.258.00:03:54.10/cable/+6.4803E-03 2006.258.00:03:54.11/wx/21.49,1016.3,78 2006.258.00:03:54.16/fmout-gps/S +4.55E-07 2006.258.00:03:54.17:scan_name=258-0004,jd0609,260 2006.258.00:03:54.17:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.258.00:03:55.15#flagr#flagr/antenna,new-source 2006.258.00:03:55.15:checkk5 2006.258.00:03:55.51/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:03:55.91/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:03:56.34/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:03:56.74/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:03:57.13/chk_obsdata//k5ts1/T2580003??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.258.00:03:57.55/chk_obsdata//k5ts2/T2580003??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.258.00:03:57.94/chk_obsdata//k5ts3/T2580003??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.258.00:03:58.34/chk_obsdata//k5ts4/T2580003??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.258.00:03:59.08/k5log//k5ts1_log_newline 2006.258.00:03:59.80/k5log//k5ts2_log_newline 2006.258.00:04:00.51/k5log//k5ts3_log_newline 2006.258.00:04:01.23/k5log//k5ts4_log_newline 2006.258.00:04:01.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:04:01.25:setupk4=1 2006.258.00:04:01.25$setupk4/echo=on 2006.258.00:04:01.25$setupk4/pcalon 2006.258.00:04:01.25$pcalon/"no phase cal control is implemented here 2006.258.00:04:01.25$setupk4/"tpicd=stop 2006.258.00:04:01.25$setupk4/"rec=synch_on 2006.258.00:04:01.25$setupk4/"rec_mode=128 2006.258.00:04:01.25$setupk4/!* 2006.258.00:04:01.25$setupk4/recpk4 2006.258.00:04:01.25$recpk4/recpatch= 2006.258.00:04:01.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:04:01.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:04:01.25$setupk4/vck44 2006.258.00:04:01.25$vck44/valo=1,524.99 2006.258.00:04:01.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.00:04:01.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.00:04:01.25#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:01.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:01.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:01.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:01.25#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:04:01.25#ibcon#first serial, iclass 27, count 0 2006.258.00:04:01.25#ibcon#enter sib2, iclass 27, count 0 2006.258.00:04:01.25#ibcon#flushed, iclass 27, count 0 2006.258.00:04:01.25#ibcon#about to write, iclass 27, count 0 2006.258.00:04:01.25#ibcon#wrote, iclass 27, count 0 2006.258.00:04:01.25#ibcon#about to read 3, iclass 27, count 0 2006.258.00:04:01.26#ibcon#read 3, iclass 27, count 0 2006.258.00:04:01.26#ibcon#about to read 4, iclass 27, count 0 2006.258.00:04:01.26#ibcon#read 4, iclass 27, count 0 2006.258.00:04:01.26#ibcon#about to read 5, iclass 27, count 0 2006.258.00:04:01.26#ibcon#read 5, iclass 27, count 0 2006.258.00:04:01.26#ibcon#about to read 6, iclass 27, count 0 2006.258.00:04:01.26#ibcon#read 6, iclass 27, count 0 2006.258.00:04:01.26#ibcon#end of sib2, iclass 27, count 0 2006.258.00:04:01.26#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:04:01.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:04:01.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:04:01.26#ibcon#*before write, iclass 27, count 0 2006.258.00:04:01.26#ibcon#enter sib2, iclass 27, count 0 2006.258.00:04:01.26#ibcon#flushed, iclass 27, count 0 2006.258.00:04:01.26#ibcon#about to write, iclass 27, count 0 2006.258.00:04:01.26#ibcon#wrote, iclass 27, count 0 2006.258.00:04:01.26#ibcon#about to read 3, iclass 27, count 0 2006.258.00:04:01.31#ibcon#read 3, iclass 27, count 0 2006.258.00:04:01.31#ibcon#about to read 4, iclass 27, count 0 2006.258.00:04:01.31#ibcon#read 4, iclass 27, count 0 2006.258.00:04:01.31#ibcon#about to read 5, iclass 27, count 0 2006.258.00:04:01.31#ibcon#read 5, iclass 27, count 0 2006.258.00:04:01.31#ibcon#about to read 6, iclass 27, count 0 2006.258.00:04:01.31#ibcon#read 6, iclass 27, count 0 2006.258.00:04:01.31#ibcon#end of sib2, iclass 27, count 0 2006.258.00:04:01.31#ibcon#*after write, iclass 27, count 0 2006.258.00:04:01.31#ibcon#*before return 0, iclass 27, count 0 2006.258.00:04:01.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:01.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:01.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:04:01.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:04:01.32$vck44/va=1,8 2006.258.00:04:01.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.00:04:01.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.00:04:01.32#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:01.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:01.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:01.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:01.32#ibcon#enter wrdev, iclass 29, count 2 2006.258.00:04:01.32#ibcon#first serial, iclass 29, count 2 2006.258.00:04:01.32#ibcon#enter sib2, iclass 29, count 2 2006.258.00:04:01.32#ibcon#flushed, iclass 29, count 2 2006.258.00:04:01.32#ibcon#about to write, iclass 29, count 2 2006.258.00:04:01.32#ibcon#wrote, iclass 29, count 2 2006.258.00:04:01.32#ibcon#about to read 3, iclass 29, count 2 2006.258.00:04:01.33#ibcon#read 3, iclass 29, count 2 2006.258.00:04:01.33#ibcon#about to read 4, iclass 29, count 2 2006.258.00:04:01.33#ibcon#read 4, iclass 29, count 2 2006.258.00:04:01.33#ibcon#about to read 5, iclass 29, count 2 2006.258.00:04:01.33#ibcon#read 5, iclass 29, count 2 2006.258.00:04:01.33#ibcon#about to read 6, iclass 29, count 2 2006.258.00:04:01.33#ibcon#read 6, iclass 29, count 2 2006.258.00:04:01.33#ibcon#end of sib2, iclass 29, count 2 2006.258.00:04:01.33#ibcon#*mode == 0, iclass 29, count 2 2006.258.00:04:01.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.00:04:01.33#ibcon#[25=AT01-08\r\n] 2006.258.00:04:01.33#ibcon#*before write, iclass 29, count 2 2006.258.00:04:01.33#ibcon#enter sib2, iclass 29, count 2 2006.258.00:04:01.33#ibcon#flushed, iclass 29, count 2 2006.258.00:04:01.33#ibcon#about to write, iclass 29, count 2 2006.258.00:04:01.33#ibcon#wrote, iclass 29, count 2 2006.258.00:04:01.33#ibcon#about to read 3, iclass 29, count 2 2006.258.00:04:01.36#ibcon#read 3, iclass 29, count 2 2006.258.00:04:01.36#ibcon#about to read 4, iclass 29, count 2 2006.258.00:04:01.36#ibcon#read 4, iclass 29, count 2 2006.258.00:04:01.36#ibcon#about to read 5, iclass 29, count 2 2006.258.00:04:01.36#ibcon#read 5, iclass 29, count 2 2006.258.00:04:01.36#ibcon#about to read 6, iclass 29, count 2 2006.258.00:04:01.36#ibcon#read 6, iclass 29, count 2 2006.258.00:04:01.36#ibcon#end of sib2, iclass 29, count 2 2006.258.00:04:01.36#ibcon#*after write, iclass 29, count 2 2006.258.00:04:01.36#ibcon#*before return 0, iclass 29, count 2 2006.258.00:04:01.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:01.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:01.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.00:04:01.36#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:01.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:01.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:01.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:01.48#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:04:01.48#ibcon#first serial, iclass 29, count 0 2006.258.00:04:01.48#ibcon#enter sib2, iclass 29, count 0 2006.258.00:04:01.48#ibcon#flushed, iclass 29, count 0 2006.258.00:04:01.48#ibcon#about to write, iclass 29, count 0 2006.258.00:04:01.48#ibcon#wrote, iclass 29, count 0 2006.258.00:04:01.48#ibcon#about to read 3, iclass 29, count 0 2006.258.00:04:01.50#ibcon#read 3, iclass 29, count 0 2006.258.00:04:01.50#ibcon#about to read 4, iclass 29, count 0 2006.258.00:04:01.50#ibcon#read 4, iclass 29, count 0 2006.258.00:04:01.50#ibcon#about to read 5, iclass 29, count 0 2006.258.00:04:01.50#ibcon#read 5, iclass 29, count 0 2006.258.00:04:01.50#ibcon#about to read 6, iclass 29, count 0 2006.258.00:04:01.50#ibcon#read 6, iclass 29, count 0 2006.258.00:04:01.50#ibcon#end of sib2, iclass 29, count 0 2006.258.00:04:01.50#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:04:01.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:04:01.50#ibcon#[25=USB\r\n] 2006.258.00:04:01.50#ibcon#*before write, iclass 29, count 0 2006.258.00:04:01.50#ibcon#enter sib2, iclass 29, count 0 2006.258.00:04:01.50#ibcon#flushed, iclass 29, count 0 2006.258.00:04:01.50#ibcon#about to write, iclass 29, count 0 2006.258.00:04:01.50#ibcon#wrote, iclass 29, count 0 2006.258.00:04:01.50#ibcon#about to read 3, iclass 29, count 0 2006.258.00:04:01.53#ibcon#read 3, iclass 29, count 0 2006.258.00:04:01.53#ibcon#about to read 4, iclass 29, count 0 2006.258.00:04:01.53#ibcon#read 4, iclass 29, count 0 2006.258.00:04:01.53#ibcon#about to read 5, iclass 29, count 0 2006.258.00:04:01.53#ibcon#read 5, iclass 29, count 0 2006.258.00:04:01.53#ibcon#about to read 6, iclass 29, count 0 2006.258.00:04:01.53#ibcon#read 6, iclass 29, count 0 2006.258.00:04:01.53#ibcon#end of sib2, iclass 29, count 0 2006.258.00:04:01.53#ibcon#*after write, iclass 29, count 0 2006.258.00:04:01.53#ibcon#*before return 0, iclass 29, count 0 2006.258.00:04:01.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:01.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:01.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:04:01.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:04:01.54$vck44/valo=2,534.99 2006.258.00:04:01.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.258.00:04:01.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.258.00:04:01.54#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:01.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:04:01.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:04:01.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:04:01.54#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:04:01.54#ibcon#first serial, iclass 31, count 0 2006.258.00:04:01.54#ibcon#enter sib2, iclass 31, count 0 2006.258.00:04:01.54#ibcon#flushed, iclass 31, count 0 2006.258.00:04:01.54#ibcon#about to write, iclass 31, count 0 2006.258.00:04:01.54#ibcon#wrote, iclass 31, count 0 2006.258.00:04:01.54#ibcon#about to read 3, iclass 31, count 0 2006.258.00:04:01.55#ibcon#read 3, iclass 31, count 0 2006.258.00:04:01.55#ibcon#about to read 4, iclass 31, count 0 2006.258.00:04:01.55#ibcon#read 4, iclass 31, count 0 2006.258.00:04:01.55#ibcon#about to read 5, iclass 31, count 0 2006.258.00:04:01.55#ibcon#read 5, iclass 31, count 0 2006.258.00:04:01.55#ibcon#about to read 6, iclass 31, count 0 2006.258.00:04:01.55#ibcon#read 6, iclass 31, count 0 2006.258.00:04:01.55#ibcon#end of sib2, iclass 31, count 0 2006.258.00:04:01.55#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:04:01.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:04:01.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:04:01.55#ibcon#*before write, iclass 31, count 0 2006.258.00:04:01.55#ibcon#enter sib2, iclass 31, count 0 2006.258.00:04:01.55#ibcon#flushed, iclass 31, count 0 2006.258.00:04:01.55#ibcon#about to write, iclass 31, count 0 2006.258.00:04:01.55#ibcon#wrote, iclass 31, count 0 2006.258.00:04:01.55#ibcon#about to read 3, iclass 31, count 0 2006.258.00:04:01.59#ibcon#read 3, iclass 31, count 0 2006.258.00:04:01.59#ibcon#about to read 4, iclass 31, count 0 2006.258.00:04:01.59#ibcon#read 4, iclass 31, count 0 2006.258.00:04:01.59#ibcon#about to read 5, iclass 31, count 0 2006.258.00:04:01.59#ibcon#read 5, iclass 31, count 0 2006.258.00:04:01.59#ibcon#about to read 6, iclass 31, count 0 2006.258.00:04:01.59#ibcon#read 6, iclass 31, count 0 2006.258.00:04:01.59#ibcon#end of sib2, iclass 31, count 0 2006.258.00:04:01.59#ibcon#*after write, iclass 31, count 0 2006.258.00:04:01.59#ibcon#*before return 0, iclass 31, count 0 2006.258.00:04:01.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:04:01.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:04:01.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:04:01.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:04:01.60$vck44/va=2,7 2006.258.00:04:01.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.00:04:01.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.00:04:01.60#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:01.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:04:01.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:04:01.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:04:01.64#ibcon#enter wrdev, iclass 33, count 2 2006.258.00:04:01.64#ibcon#first serial, iclass 33, count 2 2006.258.00:04:01.64#ibcon#enter sib2, iclass 33, count 2 2006.258.00:04:01.64#ibcon#flushed, iclass 33, count 2 2006.258.00:04:01.64#ibcon#about to write, iclass 33, count 2 2006.258.00:04:01.64#ibcon#wrote, iclass 33, count 2 2006.258.00:04:01.64#ibcon#about to read 3, iclass 33, count 2 2006.258.00:04:01.66#ibcon#read 3, iclass 33, count 2 2006.258.00:04:01.66#ibcon#about to read 4, iclass 33, count 2 2006.258.00:04:01.66#ibcon#read 4, iclass 33, count 2 2006.258.00:04:01.66#ibcon#about to read 5, iclass 33, count 2 2006.258.00:04:01.66#ibcon#read 5, iclass 33, count 2 2006.258.00:04:01.66#ibcon#about to read 6, iclass 33, count 2 2006.258.00:04:01.66#ibcon#read 6, iclass 33, count 2 2006.258.00:04:01.66#ibcon#end of sib2, iclass 33, count 2 2006.258.00:04:01.66#ibcon#*mode == 0, iclass 33, count 2 2006.258.00:04:01.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.00:04:01.66#ibcon#[25=AT02-07\r\n] 2006.258.00:04:01.66#ibcon#*before write, iclass 33, count 2 2006.258.00:04:01.66#ibcon#enter sib2, iclass 33, count 2 2006.258.00:04:01.66#ibcon#flushed, iclass 33, count 2 2006.258.00:04:01.66#ibcon#about to write, iclass 33, count 2 2006.258.00:04:01.66#ibcon#wrote, iclass 33, count 2 2006.258.00:04:01.66#ibcon#about to read 3, iclass 33, count 2 2006.258.00:04:01.69#ibcon#read 3, iclass 33, count 2 2006.258.00:04:01.69#ibcon#about to read 4, iclass 33, count 2 2006.258.00:04:01.69#ibcon#read 4, iclass 33, count 2 2006.258.00:04:01.69#ibcon#about to read 5, iclass 33, count 2 2006.258.00:04:01.69#ibcon#read 5, iclass 33, count 2 2006.258.00:04:01.69#ibcon#about to read 6, iclass 33, count 2 2006.258.00:04:01.69#ibcon#read 6, iclass 33, count 2 2006.258.00:04:01.69#ibcon#end of sib2, iclass 33, count 2 2006.258.00:04:01.69#ibcon#*after write, iclass 33, count 2 2006.258.00:04:01.69#ibcon#*before return 0, iclass 33, count 2 2006.258.00:04:01.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:04:01.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:04:01.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.00:04:01.69#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:01.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:04:01.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:04:01.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:04:01.81#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:04:01.81#ibcon#first serial, iclass 33, count 0 2006.258.00:04:01.81#ibcon#enter sib2, iclass 33, count 0 2006.258.00:04:01.81#ibcon#flushed, iclass 33, count 0 2006.258.00:04:01.81#ibcon#about to write, iclass 33, count 0 2006.258.00:04:01.81#ibcon#wrote, iclass 33, count 0 2006.258.00:04:01.81#ibcon#about to read 3, iclass 33, count 0 2006.258.00:04:01.83#ibcon#read 3, iclass 33, count 0 2006.258.00:04:01.83#ibcon#about to read 4, iclass 33, count 0 2006.258.00:04:01.83#ibcon#read 4, iclass 33, count 0 2006.258.00:04:01.83#ibcon#about to read 5, iclass 33, count 0 2006.258.00:04:01.83#ibcon#read 5, iclass 33, count 0 2006.258.00:04:01.83#ibcon#about to read 6, iclass 33, count 0 2006.258.00:04:01.83#ibcon#read 6, iclass 33, count 0 2006.258.00:04:01.83#ibcon#end of sib2, iclass 33, count 0 2006.258.00:04:01.83#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:04:01.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:04:01.83#ibcon#[25=USB\r\n] 2006.258.00:04:01.83#ibcon#*before write, iclass 33, count 0 2006.258.00:04:01.83#ibcon#enter sib2, iclass 33, count 0 2006.258.00:04:01.83#ibcon#flushed, iclass 33, count 0 2006.258.00:04:01.83#ibcon#about to write, iclass 33, count 0 2006.258.00:04:01.83#ibcon#wrote, iclass 33, count 0 2006.258.00:04:01.83#ibcon#about to read 3, iclass 33, count 0 2006.258.00:04:01.86#ibcon#read 3, iclass 33, count 0 2006.258.00:04:01.86#ibcon#about to read 4, iclass 33, count 0 2006.258.00:04:01.86#ibcon#read 4, iclass 33, count 0 2006.258.00:04:01.86#ibcon#about to read 5, iclass 33, count 0 2006.258.00:04:01.86#ibcon#read 5, iclass 33, count 0 2006.258.00:04:01.86#ibcon#about to read 6, iclass 33, count 0 2006.258.00:04:01.86#ibcon#read 6, iclass 33, count 0 2006.258.00:04:01.86#ibcon#end of sib2, iclass 33, count 0 2006.258.00:04:01.86#ibcon#*after write, iclass 33, count 0 2006.258.00:04:01.86#ibcon#*before return 0, iclass 33, count 0 2006.258.00:04:01.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:04:01.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:04:01.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:04:01.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:04:01.87$vck44/valo=3,564.99 2006.258.00:04:01.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.00:04:01.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.00:04:01.87#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:01.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:01.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:01.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:01.87#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:04:01.87#ibcon#first serial, iclass 35, count 0 2006.258.00:04:01.87#ibcon#enter sib2, iclass 35, count 0 2006.258.00:04:01.87#ibcon#flushed, iclass 35, count 0 2006.258.00:04:01.87#ibcon#about to write, iclass 35, count 0 2006.258.00:04:01.87#ibcon#wrote, iclass 35, count 0 2006.258.00:04:01.87#ibcon#about to read 3, iclass 35, count 0 2006.258.00:04:01.88#ibcon#read 3, iclass 35, count 0 2006.258.00:04:01.88#ibcon#about to read 4, iclass 35, count 0 2006.258.00:04:01.88#ibcon#read 4, iclass 35, count 0 2006.258.00:04:01.88#ibcon#about to read 5, iclass 35, count 0 2006.258.00:04:01.88#ibcon#read 5, iclass 35, count 0 2006.258.00:04:01.88#ibcon#about to read 6, iclass 35, count 0 2006.258.00:04:01.88#ibcon#read 6, iclass 35, count 0 2006.258.00:04:01.88#ibcon#end of sib2, iclass 35, count 0 2006.258.00:04:01.88#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:04:01.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:04:01.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:04:01.88#ibcon#*before write, iclass 35, count 0 2006.258.00:04:01.88#ibcon#enter sib2, iclass 35, count 0 2006.258.00:04:01.88#ibcon#flushed, iclass 35, count 0 2006.258.00:04:01.88#ibcon#about to write, iclass 35, count 0 2006.258.00:04:01.88#ibcon#wrote, iclass 35, count 0 2006.258.00:04:01.88#ibcon#about to read 3, iclass 35, count 0 2006.258.00:04:01.92#ibcon#read 3, iclass 35, count 0 2006.258.00:04:01.92#ibcon#about to read 4, iclass 35, count 0 2006.258.00:04:01.92#ibcon#read 4, iclass 35, count 0 2006.258.00:04:01.92#ibcon#about to read 5, iclass 35, count 0 2006.258.00:04:01.92#ibcon#read 5, iclass 35, count 0 2006.258.00:04:01.92#ibcon#about to read 6, iclass 35, count 0 2006.258.00:04:01.92#ibcon#read 6, iclass 35, count 0 2006.258.00:04:01.92#ibcon#end of sib2, iclass 35, count 0 2006.258.00:04:01.92#ibcon#*after write, iclass 35, count 0 2006.258.00:04:01.92#ibcon#*before return 0, iclass 35, count 0 2006.258.00:04:01.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:01.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:01.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:04:01.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:04:01.93$vck44/va=3,8 2006.258.00:04:01.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.00:04:01.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.00:04:01.93#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:01.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:01.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:01.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:01.97#ibcon#enter wrdev, iclass 37, count 2 2006.258.00:04:01.97#ibcon#first serial, iclass 37, count 2 2006.258.00:04:01.97#ibcon#enter sib2, iclass 37, count 2 2006.258.00:04:01.97#ibcon#flushed, iclass 37, count 2 2006.258.00:04:01.97#ibcon#about to write, iclass 37, count 2 2006.258.00:04:01.97#ibcon#wrote, iclass 37, count 2 2006.258.00:04:01.97#ibcon#about to read 3, iclass 37, count 2 2006.258.00:04:01.99#ibcon#read 3, iclass 37, count 2 2006.258.00:04:01.99#ibcon#about to read 4, iclass 37, count 2 2006.258.00:04:01.99#ibcon#read 4, iclass 37, count 2 2006.258.00:04:01.99#ibcon#about to read 5, iclass 37, count 2 2006.258.00:04:01.99#ibcon#read 5, iclass 37, count 2 2006.258.00:04:01.99#ibcon#about to read 6, iclass 37, count 2 2006.258.00:04:01.99#ibcon#read 6, iclass 37, count 2 2006.258.00:04:01.99#ibcon#end of sib2, iclass 37, count 2 2006.258.00:04:01.99#ibcon#*mode == 0, iclass 37, count 2 2006.258.00:04:01.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.00:04:01.99#ibcon#[25=AT03-08\r\n] 2006.258.00:04:01.99#ibcon#*before write, iclass 37, count 2 2006.258.00:04:01.99#ibcon#enter sib2, iclass 37, count 2 2006.258.00:04:01.99#ibcon#flushed, iclass 37, count 2 2006.258.00:04:01.99#ibcon#about to write, iclass 37, count 2 2006.258.00:04:01.99#ibcon#wrote, iclass 37, count 2 2006.258.00:04:01.99#ibcon#about to read 3, iclass 37, count 2 2006.258.00:04:02.02#ibcon#read 3, iclass 37, count 2 2006.258.00:04:02.02#ibcon#about to read 4, iclass 37, count 2 2006.258.00:04:02.02#ibcon#read 4, iclass 37, count 2 2006.258.00:04:02.02#ibcon#about to read 5, iclass 37, count 2 2006.258.00:04:02.02#ibcon#read 5, iclass 37, count 2 2006.258.00:04:02.02#ibcon#about to read 6, iclass 37, count 2 2006.258.00:04:02.02#ibcon#read 6, iclass 37, count 2 2006.258.00:04:02.02#ibcon#end of sib2, iclass 37, count 2 2006.258.00:04:02.02#ibcon#*after write, iclass 37, count 2 2006.258.00:04:02.02#ibcon#*before return 0, iclass 37, count 2 2006.258.00:04:02.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:02.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:02.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.00:04:02.02#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:02.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:02.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:02.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:02.14#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:04:02.14#ibcon#first serial, iclass 37, count 0 2006.258.00:04:02.14#ibcon#enter sib2, iclass 37, count 0 2006.258.00:04:02.14#ibcon#flushed, iclass 37, count 0 2006.258.00:04:02.14#ibcon#about to write, iclass 37, count 0 2006.258.00:04:02.14#ibcon#wrote, iclass 37, count 0 2006.258.00:04:02.14#ibcon#about to read 3, iclass 37, count 0 2006.258.00:04:02.16#ibcon#read 3, iclass 37, count 0 2006.258.00:04:02.16#ibcon#about to read 4, iclass 37, count 0 2006.258.00:04:02.16#ibcon#read 4, iclass 37, count 0 2006.258.00:04:02.16#ibcon#about to read 5, iclass 37, count 0 2006.258.00:04:02.16#ibcon#read 5, iclass 37, count 0 2006.258.00:04:02.16#ibcon#about to read 6, iclass 37, count 0 2006.258.00:04:02.16#ibcon#read 6, iclass 37, count 0 2006.258.00:04:02.16#ibcon#end of sib2, iclass 37, count 0 2006.258.00:04:02.16#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:04:02.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:04:02.16#ibcon#[25=USB\r\n] 2006.258.00:04:02.16#ibcon#*before write, iclass 37, count 0 2006.258.00:04:02.16#ibcon#enter sib2, iclass 37, count 0 2006.258.00:04:02.16#ibcon#flushed, iclass 37, count 0 2006.258.00:04:02.16#ibcon#about to write, iclass 37, count 0 2006.258.00:04:02.16#ibcon#wrote, iclass 37, count 0 2006.258.00:04:02.16#ibcon#about to read 3, iclass 37, count 0 2006.258.00:04:02.19#ibcon#read 3, iclass 37, count 0 2006.258.00:04:02.19#ibcon#about to read 4, iclass 37, count 0 2006.258.00:04:02.19#ibcon#read 4, iclass 37, count 0 2006.258.00:04:02.19#ibcon#about to read 5, iclass 37, count 0 2006.258.00:04:02.19#ibcon#read 5, iclass 37, count 0 2006.258.00:04:02.19#ibcon#about to read 6, iclass 37, count 0 2006.258.00:04:02.19#ibcon#read 6, iclass 37, count 0 2006.258.00:04:02.19#ibcon#end of sib2, iclass 37, count 0 2006.258.00:04:02.19#ibcon#*after write, iclass 37, count 0 2006.258.00:04:02.19#ibcon#*before return 0, iclass 37, count 0 2006.258.00:04:02.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:02.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:02.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:04:02.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:04:02.20$vck44/valo=4,624.99 2006.258.00:04:02.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.00:04:02.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.00:04:02.20#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:02.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:02.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:02.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:02.20#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:04:02.20#ibcon#first serial, iclass 39, count 0 2006.258.00:04:02.20#ibcon#enter sib2, iclass 39, count 0 2006.258.00:04:02.20#ibcon#flushed, iclass 39, count 0 2006.258.00:04:02.20#ibcon#about to write, iclass 39, count 0 2006.258.00:04:02.20#ibcon#wrote, iclass 39, count 0 2006.258.00:04:02.20#ibcon#about to read 3, iclass 39, count 0 2006.258.00:04:02.21#ibcon#read 3, iclass 39, count 0 2006.258.00:04:02.21#ibcon#about to read 4, iclass 39, count 0 2006.258.00:04:02.21#ibcon#read 4, iclass 39, count 0 2006.258.00:04:02.21#ibcon#about to read 5, iclass 39, count 0 2006.258.00:04:02.21#ibcon#read 5, iclass 39, count 0 2006.258.00:04:02.21#ibcon#about to read 6, iclass 39, count 0 2006.258.00:04:02.21#ibcon#read 6, iclass 39, count 0 2006.258.00:04:02.21#ibcon#end of sib2, iclass 39, count 0 2006.258.00:04:02.21#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:04:02.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:04:02.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:04:02.21#ibcon#*before write, iclass 39, count 0 2006.258.00:04:02.21#ibcon#enter sib2, iclass 39, count 0 2006.258.00:04:02.21#ibcon#flushed, iclass 39, count 0 2006.258.00:04:02.21#ibcon#about to write, iclass 39, count 0 2006.258.00:04:02.21#ibcon#wrote, iclass 39, count 0 2006.258.00:04:02.21#ibcon#about to read 3, iclass 39, count 0 2006.258.00:04:02.25#ibcon#read 3, iclass 39, count 0 2006.258.00:04:02.25#ibcon#about to read 4, iclass 39, count 0 2006.258.00:04:02.25#ibcon#read 4, iclass 39, count 0 2006.258.00:04:02.25#ibcon#about to read 5, iclass 39, count 0 2006.258.00:04:02.25#ibcon#read 5, iclass 39, count 0 2006.258.00:04:02.25#ibcon#about to read 6, iclass 39, count 0 2006.258.00:04:02.25#ibcon#read 6, iclass 39, count 0 2006.258.00:04:02.25#ibcon#end of sib2, iclass 39, count 0 2006.258.00:04:02.25#ibcon#*after write, iclass 39, count 0 2006.258.00:04:02.25#ibcon#*before return 0, iclass 39, count 0 2006.258.00:04:02.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:02.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:02.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:04:02.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:04:02.26$vck44/va=4,7 2006.258.00:04:02.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.00:04:02.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.00:04:02.26#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:02.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:02.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:02.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:02.30#ibcon#enter wrdev, iclass 3, count 2 2006.258.00:04:02.30#ibcon#first serial, iclass 3, count 2 2006.258.00:04:02.30#ibcon#enter sib2, iclass 3, count 2 2006.258.00:04:02.30#ibcon#flushed, iclass 3, count 2 2006.258.00:04:02.30#ibcon#about to write, iclass 3, count 2 2006.258.00:04:02.30#ibcon#wrote, iclass 3, count 2 2006.258.00:04:02.30#ibcon#about to read 3, iclass 3, count 2 2006.258.00:04:02.32#ibcon#read 3, iclass 3, count 2 2006.258.00:04:02.32#ibcon#about to read 4, iclass 3, count 2 2006.258.00:04:02.32#ibcon#read 4, iclass 3, count 2 2006.258.00:04:02.32#ibcon#about to read 5, iclass 3, count 2 2006.258.00:04:02.32#ibcon#read 5, iclass 3, count 2 2006.258.00:04:02.32#ibcon#about to read 6, iclass 3, count 2 2006.258.00:04:02.32#ibcon#read 6, iclass 3, count 2 2006.258.00:04:02.32#ibcon#end of sib2, iclass 3, count 2 2006.258.00:04:02.32#ibcon#*mode == 0, iclass 3, count 2 2006.258.00:04:02.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.00:04:02.32#ibcon#[25=AT04-07\r\n] 2006.258.00:04:02.32#ibcon#*before write, iclass 3, count 2 2006.258.00:04:02.32#ibcon#enter sib2, iclass 3, count 2 2006.258.00:04:02.32#ibcon#flushed, iclass 3, count 2 2006.258.00:04:02.32#ibcon#about to write, iclass 3, count 2 2006.258.00:04:02.32#ibcon#wrote, iclass 3, count 2 2006.258.00:04:02.32#ibcon#about to read 3, iclass 3, count 2 2006.258.00:04:02.35#ibcon#read 3, iclass 3, count 2 2006.258.00:04:02.35#ibcon#about to read 4, iclass 3, count 2 2006.258.00:04:02.35#ibcon#read 4, iclass 3, count 2 2006.258.00:04:02.35#ibcon#about to read 5, iclass 3, count 2 2006.258.00:04:02.35#ibcon#read 5, iclass 3, count 2 2006.258.00:04:02.35#ibcon#about to read 6, iclass 3, count 2 2006.258.00:04:02.35#ibcon#read 6, iclass 3, count 2 2006.258.00:04:02.35#ibcon#end of sib2, iclass 3, count 2 2006.258.00:04:02.35#ibcon#*after write, iclass 3, count 2 2006.258.00:04:02.35#ibcon#*before return 0, iclass 3, count 2 2006.258.00:04:02.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:02.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:02.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.00:04:02.35#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:02.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:02.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:02.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:02.47#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:04:02.47#ibcon#first serial, iclass 3, count 0 2006.258.00:04:02.47#ibcon#enter sib2, iclass 3, count 0 2006.258.00:04:02.47#ibcon#flushed, iclass 3, count 0 2006.258.00:04:02.47#ibcon#about to write, iclass 3, count 0 2006.258.00:04:02.47#ibcon#wrote, iclass 3, count 0 2006.258.00:04:02.47#ibcon#about to read 3, iclass 3, count 0 2006.258.00:04:02.49#ibcon#read 3, iclass 3, count 0 2006.258.00:04:02.49#ibcon#about to read 4, iclass 3, count 0 2006.258.00:04:02.49#ibcon#read 4, iclass 3, count 0 2006.258.00:04:02.49#ibcon#about to read 5, iclass 3, count 0 2006.258.00:04:02.49#ibcon#read 5, iclass 3, count 0 2006.258.00:04:02.49#ibcon#about to read 6, iclass 3, count 0 2006.258.00:04:02.49#ibcon#read 6, iclass 3, count 0 2006.258.00:04:02.49#ibcon#end of sib2, iclass 3, count 0 2006.258.00:04:02.49#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:04:02.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:04:02.49#ibcon#[25=USB\r\n] 2006.258.00:04:02.49#ibcon#*before write, iclass 3, count 0 2006.258.00:04:02.49#ibcon#enter sib2, iclass 3, count 0 2006.258.00:04:02.49#ibcon#flushed, iclass 3, count 0 2006.258.00:04:02.49#ibcon#about to write, iclass 3, count 0 2006.258.00:04:02.49#ibcon#wrote, iclass 3, count 0 2006.258.00:04:02.49#ibcon#about to read 3, iclass 3, count 0 2006.258.00:04:02.52#ibcon#read 3, iclass 3, count 0 2006.258.00:04:02.52#ibcon#about to read 4, iclass 3, count 0 2006.258.00:04:02.52#ibcon#read 4, iclass 3, count 0 2006.258.00:04:02.52#ibcon#about to read 5, iclass 3, count 0 2006.258.00:04:02.52#ibcon#read 5, iclass 3, count 0 2006.258.00:04:02.52#ibcon#about to read 6, iclass 3, count 0 2006.258.00:04:02.52#ibcon#read 6, iclass 3, count 0 2006.258.00:04:02.52#ibcon#end of sib2, iclass 3, count 0 2006.258.00:04:02.52#ibcon#*after write, iclass 3, count 0 2006.258.00:04:02.52#ibcon#*before return 0, iclass 3, count 0 2006.258.00:04:02.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:02.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:02.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:04:02.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:04:02.53$vck44/valo=5,734.99 2006.258.00:04:02.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.00:04:02.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.00:04:02.53#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:02.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:02.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:02.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:02.53#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:04:02.53#ibcon#first serial, iclass 5, count 0 2006.258.00:04:02.53#ibcon#enter sib2, iclass 5, count 0 2006.258.00:04:02.53#ibcon#flushed, iclass 5, count 0 2006.258.00:04:02.53#ibcon#about to write, iclass 5, count 0 2006.258.00:04:02.53#ibcon#wrote, iclass 5, count 0 2006.258.00:04:02.53#ibcon#about to read 3, iclass 5, count 0 2006.258.00:04:02.54#ibcon#read 3, iclass 5, count 0 2006.258.00:04:02.54#ibcon#about to read 4, iclass 5, count 0 2006.258.00:04:02.54#ibcon#read 4, iclass 5, count 0 2006.258.00:04:02.54#ibcon#about to read 5, iclass 5, count 0 2006.258.00:04:02.54#ibcon#read 5, iclass 5, count 0 2006.258.00:04:02.54#ibcon#about to read 6, iclass 5, count 0 2006.258.00:04:02.54#ibcon#read 6, iclass 5, count 0 2006.258.00:04:02.54#ibcon#end of sib2, iclass 5, count 0 2006.258.00:04:02.54#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:04:02.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:04:02.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:04:02.54#ibcon#*before write, iclass 5, count 0 2006.258.00:04:02.54#ibcon#enter sib2, iclass 5, count 0 2006.258.00:04:02.54#ibcon#flushed, iclass 5, count 0 2006.258.00:04:02.54#ibcon#about to write, iclass 5, count 0 2006.258.00:04:02.54#ibcon#wrote, iclass 5, count 0 2006.258.00:04:02.54#ibcon#about to read 3, iclass 5, count 0 2006.258.00:04:02.58#ibcon#read 3, iclass 5, count 0 2006.258.00:04:02.58#ibcon#about to read 4, iclass 5, count 0 2006.258.00:04:02.58#ibcon#read 4, iclass 5, count 0 2006.258.00:04:02.58#ibcon#about to read 5, iclass 5, count 0 2006.258.00:04:02.58#ibcon#read 5, iclass 5, count 0 2006.258.00:04:02.58#ibcon#about to read 6, iclass 5, count 0 2006.258.00:04:02.58#ibcon#read 6, iclass 5, count 0 2006.258.00:04:02.58#ibcon#end of sib2, iclass 5, count 0 2006.258.00:04:02.58#ibcon#*after write, iclass 5, count 0 2006.258.00:04:02.58#ibcon#*before return 0, iclass 5, count 0 2006.258.00:04:02.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:02.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:02.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:04:02.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:04:02.59$vck44/va=5,4 2006.258.00:04:02.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.00:04:02.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.00:04:02.59#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:02.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:02.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:02.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:02.63#ibcon#enter wrdev, iclass 7, count 2 2006.258.00:04:02.63#ibcon#first serial, iclass 7, count 2 2006.258.00:04:02.63#ibcon#enter sib2, iclass 7, count 2 2006.258.00:04:02.63#ibcon#flushed, iclass 7, count 2 2006.258.00:04:02.63#ibcon#about to write, iclass 7, count 2 2006.258.00:04:02.63#ibcon#wrote, iclass 7, count 2 2006.258.00:04:02.63#ibcon#about to read 3, iclass 7, count 2 2006.258.00:04:02.65#ibcon#read 3, iclass 7, count 2 2006.258.00:04:02.65#ibcon#about to read 4, iclass 7, count 2 2006.258.00:04:02.65#ibcon#read 4, iclass 7, count 2 2006.258.00:04:02.65#ibcon#about to read 5, iclass 7, count 2 2006.258.00:04:02.65#ibcon#read 5, iclass 7, count 2 2006.258.00:04:02.65#ibcon#about to read 6, iclass 7, count 2 2006.258.00:04:02.65#ibcon#read 6, iclass 7, count 2 2006.258.00:04:02.65#ibcon#end of sib2, iclass 7, count 2 2006.258.00:04:02.65#ibcon#*mode == 0, iclass 7, count 2 2006.258.00:04:02.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.00:04:02.65#ibcon#[25=AT05-04\r\n] 2006.258.00:04:02.65#ibcon#*before write, iclass 7, count 2 2006.258.00:04:02.65#ibcon#enter sib2, iclass 7, count 2 2006.258.00:04:02.65#ibcon#flushed, iclass 7, count 2 2006.258.00:04:02.65#ibcon#about to write, iclass 7, count 2 2006.258.00:04:02.65#ibcon#wrote, iclass 7, count 2 2006.258.00:04:02.65#ibcon#about to read 3, iclass 7, count 2 2006.258.00:04:02.68#ibcon#read 3, iclass 7, count 2 2006.258.00:04:02.68#ibcon#about to read 4, iclass 7, count 2 2006.258.00:04:02.68#ibcon#read 4, iclass 7, count 2 2006.258.00:04:02.68#ibcon#about to read 5, iclass 7, count 2 2006.258.00:04:02.68#ibcon#read 5, iclass 7, count 2 2006.258.00:04:02.68#ibcon#about to read 6, iclass 7, count 2 2006.258.00:04:02.68#ibcon#read 6, iclass 7, count 2 2006.258.00:04:02.68#ibcon#end of sib2, iclass 7, count 2 2006.258.00:04:02.68#ibcon#*after write, iclass 7, count 2 2006.258.00:04:02.68#ibcon#*before return 0, iclass 7, count 2 2006.258.00:04:02.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:02.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:02.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.00:04:02.68#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:02.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:02.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:02.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:02.80#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:04:02.80#ibcon#first serial, iclass 7, count 0 2006.258.00:04:02.80#ibcon#enter sib2, iclass 7, count 0 2006.258.00:04:02.80#ibcon#flushed, iclass 7, count 0 2006.258.00:04:02.80#ibcon#about to write, iclass 7, count 0 2006.258.00:04:02.80#ibcon#wrote, iclass 7, count 0 2006.258.00:04:02.80#ibcon#about to read 3, iclass 7, count 0 2006.258.00:04:02.82#ibcon#read 3, iclass 7, count 0 2006.258.00:04:02.82#ibcon#about to read 4, iclass 7, count 0 2006.258.00:04:02.82#ibcon#read 4, iclass 7, count 0 2006.258.00:04:02.82#ibcon#about to read 5, iclass 7, count 0 2006.258.00:04:02.82#ibcon#read 5, iclass 7, count 0 2006.258.00:04:02.82#ibcon#about to read 6, iclass 7, count 0 2006.258.00:04:02.82#ibcon#read 6, iclass 7, count 0 2006.258.00:04:02.82#ibcon#end of sib2, iclass 7, count 0 2006.258.00:04:02.82#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:04:02.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:04:02.82#ibcon#[25=USB\r\n] 2006.258.00:04:02.82#ibcon#*before write, iclass 7, count 0 2006.258.00:04:02.82#ibcon#enter sib2, iclass 7, count 0 2006.258.00:04:02.82#ibcon#flushed, iclass 7, count 0 2006.258.00:04:02.82#ibcon#about to write, iclass 7, count 0 2006.258.00:04:02.82#ibcon#wrote, iclass 7, count 0 2006.258.00:04:02.82#ibcon#about to read 3, iclass 7, count 0 2006.258.00:04:02.85#ibcon#read 3, iclass 7, count 0 2006.258.00:04:02.85#ibcon#about to read 4, iclass 7, count 0 2006.258.00:04:02.85#ibcon#read 4, iclass 7, count 0 2006.258.00:04:02.85#ibcon#about to read 5, iclass 7, count 0 2006.258.00:04:02.85#ibcon#read 5, iclass 7, count 0 2006.258.00:04:02.85#ibcon#about to read 6, iclass 7, count 0 2006.258.00:04:02.85#ibcon#read 6, iclass 7, count 0 2006.258.00:04:02.85#ibcon#end of sib2, iclass 7, count 0 2006.258.00:04:02.85#ibcon#*after write, iclass 7, count 0 2006.258.00:04:02.85#ibcon#*before return 0, iclass 7, count 0 2006.258.00:04:02.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:02.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:02.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:04:02.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:04:02.86$vck44/valo=6,814.99 2006.258.00:04:02.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.00:04:02.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.00:04:02.86#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:02.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:02.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:02.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:02.86#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:04:02.86#ibcon#first serial, iclass 11, count 0 2006.258.00:04:02.86#ibcon#enter sib2, iclass 11, count 0 2006.258.00:04:02.86#ibcon#flushed, iclass 11, count 0 2006.258.00:04:02.86#ibcon#about to write, iclass 11, count 0 2006.258.00:04:02.86#ibcon#wrote, iclass 11, count 0 2006.258.00:04:02.86#ibcon#about to read 3, iclass 11, count 0 2006.258.00:04:02.87#ibcon#read 3, iclass 11, count 0 2006.258.00:04:02.87#ibcon#about to read 4, iclass 11, count 0 2006.258.00:04:02.87#ibcon#read 4, iclass 11, count 0 2006.258.00:04:02.87#ibcon#about to read 5, iclass 11, count 0 2006.258.00:04:02.87#ibcon#read 5, iclass 11, count 0 2006.258.00:04:02.87#ibcon#about to read 6, iclass 11, count 0 2006.258.00:04:02.87#ibcon#read 6, iclass 11, count 0 2006.258.00:04:02.87#ibcon#end of sib2, iclass 11, count 0 2006.258.00:04:02.87#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:04:02.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:04:02.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:04:02.87#ibcon#*before write, iclass 11, count 0 2006.258.00:04:02.87#ibcon#enter sib2, iclass 11, count 0 2006.258.00:04:02.87#ibcon#flushed, iclass 11, count 0 2006.258.00:04:02.87#ibcon#about to write, iclass 11, count 0 2006.258.00:04:02.87#ibcon#wrote, iclass 11, count 0 2006.258.00:04:02.87#ibcon#about to read 3, iclass 11, count 0 2006.258.00:04:02.91#ibcon#read 3, iclass 11, count 0 2006.258.00:04:02.91#ibcon#about to read 4, iclass 11, count 0 2006.258.00:04:02.91#ibcon#read 4, iclass 11, count 0 2006.258.00:04:02.91#ibcon#about to read 5, iclass 11, count 0 2006.258.00:04:02.91#ibcon#read 5, iclass 11, count 0 2006.258.00:04:02.91#ibcon#about to read 6, iclass 11, count 0 2006.258.00:04:02.91#ibcon#read 6, iclass 11, count 0 2006.258.00:04:02.91#ibcon#end of sib2, iclass 11, count 0 2006.258.00:04:02.91#ibcon#*after write, iclass 11, count 0 2006.258.00:04:02.91#ibcon#*before return 0, iclass 11, count 0 2006.258.00:04:02.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:02.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:02.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:04:02.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:04:02.92$vck44/va=6,4 2006.258.00:04:02.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.00:04:02.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.00:04:02.92#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:02.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:02.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:02.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:02.96#ibcon#enter wrdev, iclass 13, count 2 2006.258.00:04:02.96#ibcon#first serial, iclass 13, count 2 2006.258.00:04:02.96#ibcon#enter sib2, iclass 13, count 2 2006.258.00:04:02.96#ibcon#flushed, iclass 13, count 2 2006.258.00:04:02.96#ibcon#about to write, iclass 13, count 2 2006.258.00:04:02.96#ibcon#wrote, iclass 13, count 2 2006.258.00:04:02.96#ibcon#about to read 3, iclass 13, count 2 2006.258.00:04:02.98#ibcon#read 3, iclass 13, count 2 2006.258.00:04:02.98#ibcon#about to read 4, iclass 13, count 2 2006.258.00:04:02.98#ibcon#read 4, iclass 13, count 2 2006.258.00:04:02.98#ibcon#about to read 5, iclass 13, count 2 2006.258.00:04:02.98#ibcon#read 5, iclass 13, count 2 2006.258.00:04:02.98#ibcon#about to read 6, iclass 13, count 2 2006.258.00:04:02.98#ibcon#read 6, iclass 13, count 2 2006.258.00:04:02.98#ibcon#end of sib2, iclass 13, count 2 2006.258.00:04:02.98#ibcon#*mode == 0, iclass 13, count 2 2006.258.00:04:02.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.00:04:02.98#ibcon#[25=AT06-04\r\n] 2006.258.00:04:02.98#ibcon#*before write, iclass 13, count 2 2006.258.00:04:02.98#ibcon#enter sib2, iclass 13, count 2 2006.258.00:04:02.98#ibcon#flushed, iclass 13, count 2 2006.258.00:04:02.98#ibcon#about to write, iclass 13, count 2 2006.258.00:04:02.98#ibcon#wrote, iclass 13, count 2 2006.258.00:04:02.98#ibcon#about to read 3, iclass 13, count 2 2006.258.00:04:03.01#ibcon#read 3, iclass 13, count 2 2006.258.00:04:03.01#ibcon#about to read 4, iclass 13, count 2 2006.258.00:04:03.01#ibcon#read 4, iclass 13, count 2 2006.258.00:04:03.01#ibcon#about to read 5, iclass 13, count 2 2006.258.00:04:03.01#ibcon#read 5, iclass 13, count 2 2006.258.00:04:03.01#ibcon#about to read 6, iclass 13, count 2 2006.258.00:04:03.01#ibcon#read 6, iclass 13, count 2 2006.258.00:04:03.01#ibcon#end of sib2, iclass 13, count 2 2006.258.00:04:03.01#ibcon#*after write, iclass 13, count 2 2006.258.00:04:03.01#ibcon#*before return 0, iclass 13, count 2 2006.258.00:04:03.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:03.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:03.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.00:04:03.01#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:03.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:03.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:03.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:03.13#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:04:03.13#ibcon#first serial, iclass 13, count 0 2006.258.00:04:03.13#ibcon#enter sib2, iclass 13, count 0 2006.258.00:04:03.13#ibcon#flushed, iclass 13, count 0 2006.258.00:04:03.13#ibcon#about to write, iclass 13, count 0 2006.258.00:04:03.13#ibcon#wrote, iclass 13, count 0 2006.258.00:04:03.13#ibcon#about to read 3, iclass 13, count 0 2006.258.00:04:03.15#ibcon#read 3, iclass 13, count 0 2006.258.00:04:03.15#ibcon#about to read 4, iclass 13, count 0 2006.258.00:04:03.15#ibcon#read 4, iclass 13, count 0 2006.258.00:04:03.15#ibcon#about to read 5, iclass 13, count 0 2006.258.00:04:03.15#ibcon#read 5, iclass 13, count 0 2006.258.00:04:03.15#ibcon#about to read 6, iclass 13, count 0 2006.258.00:04:03.15#ibcon#read 6, iclass 13, count 0 2006.258.00:04:03.15#ibcon#end of sib2, iclass 13, count 0 2006.258.00:04:03.15#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:04:03.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:04:03.15#ibcon#[25=USB\r\n] 2006.258.00:04:03.15#ibcon#*before write, iclass 13, count 0 2006.258.00:04:03.15#ibcon#enter sib2, iclass 13, count 0 2006.258.00:04:03.15#ibcon#flushed, iclass 13, count 0 2006.258.00:04:03.15#ibcon#about to write, iclass 13, count 0 2006.258.00:04:03.15#ibcon#wrote, iclass 13, count 0 2006.258.00:04:03.15#ibcon#about to read 3, iclass 13, count 0 2006.258.00:04:03.18#ibcon#read 3, iclass 13, count 0 2006.258.00:04:03.18#ibcon#about to read 4, iclass 13, count 0 2006.258.00:04:03.18#ibcon#read 4, iclass 13, count 0 2006.258.00:04:03.18#ibcon#about to read 5, iclass 13, count 0 2006.258.00:04:03.18#ibcon#read 5, iclass 13, count 0 2006.258.00:04:03.18#ibcon#about to read 6, iclass 13, count 0 2006.258.00:04:03.18#ibcon#read 6, iclass 13, count 0 2006.258.00:04:03.18#ibcon#end of sib2, iclass 13, count 0 2006.258.00:04:03.18#ibcon#*after write, iclass 13, count 0 2006.258.00:04:03.18#ibcon#*before return 0, iclass 13, count 0 2006.258.00:04:03.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:03.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:03.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:04:03.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:04:03.19$vck44/valo=7,864.99 2006.258.00:04:03.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.00:04:03.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.00:04:03.19#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:03.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:03.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:03.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:03.19#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:04:03.19#ibcon#first serial, iclass 15, count 0 2006.258.00:04:03.19#ibcon#enter sib2, iclass 15, count 0 2006.258.00:04:03.19#ibcon#flushed, iclass 15, count 0 2006.258.00:04:03.19#ibcon#about to write, iclass 15, count 0 2006.258.00:04:03.19#ibcon#wrote, iclass 15, count 0 2006.258.00:04:03.19#ibcon#about to read 3, iclass 15, count 0 2006.258.00:04:03.20#ibcon#read 3, iclass 15, count 0 2006.258.00:04:03.20#ibcon#about to read 4, iclass 15, count 0 2006.258.00:04:03.20#ibcon#read 4, iclass 15, count 0 2006.258.00:04:03.20#ibcon#about to read 5, iclass 15, count 0 2006.258.00:04:03.20#ibcon#read 5, iclass 15, count 0 2006.258.00:04:03.20#ibcon#about to read 6, iclass 15, count 0 2006.258.00:04:03.20#ibcon#read 6, iclass 15, count 0 2006.258.00:04:03.20#ibcon#end of sib2, iclass 15, count 0 2006.258.00:04:03.20#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:04:03.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:04:03.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:04:03.20#ibcon#*before write, iclass 15, count 0 2006.258.00:04:03.20#ibcon#enter sib2, iclass 15, count 0 2006.258.00:04:03.20#ibcon#flushed, iclass 15, count 0 2006.258.00:04:03.20#ibcon#about to write, iclass 15, count 0 2006.258.00:04:03.20#ibcon#wrote, iclass 15, count 0 2006.258.00:04:03.20#ibcon#about to read 3, iclass 15, count 0 2006.258.00:04:03.24#ibcon#read 3, iclass 15, count 0 2006.258.00:04:03.24#ibcon#about to read 4, iclass 15, count 0 2006.258.00:04:03.24#ibcon#read 4, iclass 15, count 0 2006.258.00:04:03.24#ibcon#about to read 5, iclass 15, count 0 2006.258.00:04:03.24#ibcon#read 5, iclass 15, count 0 2006.258.00:04:03.24#ibcon#about to read 6, iclass 15, count 0 2006.258.00:04:03.24#ibcon#read 6, iclass 15, count 0 2006.258.00:04:03.24#ibcon#end of sib2, iclass 15, count 0 2006.258.00:04:03.24#ibcon#*after write, iclass 15, count 0 2006.258.00:04:03.24#ibcon#*before return 0, iclass 15, count 0 2006.258.00:04:03.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:03.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:03.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:04:03.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:04:03.25$vck44/va=7,4 2006.258.00:04:03.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.00:04:03.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.00:04:03.25#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:03.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:03.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:03.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:03.29#ibcon#enter wrdev, iclass 17, count 2 2006.258.00:04:03.29#ibcon#first serial, iclass 17, count 2 2006.258.00:04:03.29#ibcon#enter sib2, iclass 17, count 2 2006.258.00:04:03.29#ibcon#flushed, iclass 17, count 2 2006.258.00:04:03.29#ibcon#about to write, iclass 17, count 2 2006.258.00:04:03.29#ibcon#wrote, iclass 17, count 2 2006.258.00:04:03.29#ibcon#about to read 3, iclass 17, count 2 2006.258.00:04:03.31#ibcon#read 3, iclass 17, count 2 2006.258.00:04:03.31#ibcon#about to read 4, iclass 17, count 2 2006.258.00:04:03.31#ibcon#read 4, iclass 17, count 2 2006.258.00:04:03.31#ibcon#about to read 5, iclass 17, count 2 2006.258.00:04:03.31#ibcon#read 5, iclass 17, count 2 2006.258.00:04:03.31#ibcon#about to read 6, iclass 17, count 2 2006.258.00:04:03.31#ibcon#read 6, iclass 17, count 2 2006.258.00:04:03.31#ibcon#end of sib2, iclass 17, count 2 2006.258.00:04:03.31#ibcon#*mode == 0, iclass 17, count 2 2006.258.00:04:03.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.00:04:03.31#ibcon#[25=AT07-04\r\n] 2006.258.00:04:03.31#ibcon#*before write, iclass 17, count 2 2006.258.00:04:03.31#ibcon#enter sib2, iclass 17, count 2 2006.258.00:04:03.31#ibcon#flushed, iclass 17, count 2 2006.258.00:04:03.31#ibcon#about to write, iclass 17, count 2 2006.258.00:04:03.31#ibcon#wrote, iclass 17, count 2 2006.258.00:04:03.31#ibcon#about to read 3, iclass 17, count 2 2006.258.00:04:03.34#ibcon#read 3, iclass 17, count 2 2006.258.00:04:03.34#ibcon#about to read 4, iclass 17, count 2 2006.258.00:04:03.34#ibcon#read 4, iclass 17, count 2 2006.258.00:04:03.34#ibcon#about to read 5, iclass 17, count 2 2006.258.00:04:03.34#ibcon#read 5, iclass 17, count 2 2006.258.00:04:03.34#ibcon#about to read 6, iclass 17, count 2 2006.258.00:04:03.34#ibcon#read 6, iclass 17, count 2 2006.258.00:04:03.34#ibcon#end of sib2, iclass 17, count 2 2006.258.00:04:03.34#ibcon#*after write, iclass 17, count 2 2006.258.00:04:03.34#ibcon#*before return 0, iclass 17, count 2 2006.258.00:04:03.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:03.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:03.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.00:04:03.34#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:03.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:03.46#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:03.46#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:03.46#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:04:03.46#ibcon#first serial, iclass 17, count 0 2006.258.00:04:03.46#ibcon#enter sib2, iclass 17, count 0 2006.258.00:04:03.46#ibcon#flushed, iclass 17, count 0 2006.258.00:04:03.46#ibcon#about to write, iclass 17, count 0 2006.258.00:04:03.46#ibcon#wrote, iclass 17, count 0 2006.258.00:04:03.46#ibcon#about to read 3, iclass 17, count 0 2006.258.00:04:03.48#ibcon#read 3, iclass 17, count 0 2006.258.00:04:03.48#ibcon#about to read 4, iclass 17, count 0 2006.258.00:04:03.48#ibcon#read 4, iclass 17, count 0 2006.258.00:04:03.48#ibcon#about to read 5, iclass 17, count 0 2006.258.00:04:03.48#ibcon#read 5, iclass 17, count 0 2006.258.00:04:03.48#ibcon#about to read 6, iclass 17, count 0 2006.258.00:04:03.48#ibcon#read 6, iclass 17, count 0 2006.258.00:04:03.48#ibcon#end of sib2, iclass 17, count 0 2006.258.00:04:03.48#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:04:03.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:04:03.48#ibcon#[25=USB\r\n] 2006.258.00:04:03.48#ibcon#*before write, iclass 17, count 0 2006.258.00:04:03.48#ibcon#enter sib2, iclass 17, count 0 2006.258.00:04:03.48#ibcon#flushed, iclass 17, count 0 2006.258.00:04:03.48#ibcon#about to write, iclass 17, count 0 2006.258.00:04:03.48#ibcon#wrote, iclass 17, count 0 2006.258.00:04:03.48#ibcon#about to read 3, iclass 17, count 0 2006.258.00:04:03.51#ibcon#read 3, iclass 17, count 0 2006.258.00:04:03.51#ibcon#about to read 4, iclass 17, count 0 2006.258.00:04:03.51#ibcon#read 4, iclass 17, count 0 2006.258.00:04:03.51#ibcon#about to read 5, iclass 17, count 0 2006.258.00:04:03.51#ibcon#read 5, iclass 17, count 0 2006.258.00:04:03.51#ibcon#about to read 6, iclass 17, count 0 2006.258.00:04:03.51#ibcon#read 6, iclass 17, count 0 2006.258.00:04:03.51#ibcon#end of sib2, iclass 17, count 0 2006.258.00:04:03.51#ibcon#*after write, iclass 17, count 0 2006.258.00:04:03.51#ibcon#*before return 0, iclass 17, count 0 2006.258.00:04:03.51#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:03.51#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:03.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:04:03.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:04:03.52$vck44/valo=8,884.99 2006.258.00:04:03.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.00:04:03.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.00:04:03.52#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:03.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:03.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:03.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:03.52#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:04:03.52#ibcon#first serial, iclass 19, count 0 2006.258.00:04:03.52#ibcon#enter sib2, iclass 19, count 0 2006.258.00:04:03.52#ibcon#flushed, iclass 19, count 0 2006.258.00:04:03.52#ibcon#about to write, iclass 19, count 0 2006.258.00:04:03.52#ibcon#wrote, iclass 19, count 0 2006.258.00:04:03.52#ibcon#about to read 3, iclass 19, count 0 2006.258.00:04:03.53#ibcon#read 3, iclass 19, count 0 2006.258.00:04:03.53#ibcon#about to read 4, iclass 19, count 0 2006.258.00:04:03.53#ibcon#read 4, iclass 19, count 0 2006.258.00:04:03.53#ibcon#about to read 5, iclass 19, count 0 2006.258.00:04:03.53#ibcon#read 5, iclass 19, count 0 2006.258.00:04:03.53#ibcon#about to read 6, iclass 19, count 0 2006.258.00:04:03.53#ibcon#read 6, iclass 19, count 0 2006.258.00:04:03.53#ibcon#end of sib2, iclass 19, count 0 2006.258.00:04:03.53#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:04:03.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:04:03.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:04:03.53#ibcon#*before write, iclass 19, count 0 2006.258.00:04:03.53#ibcon#enter sib2, iclass 19, count 0 2006.258.00:04:03.53#ibcon#flushed, iclass 19, count 0 2006.258.00:04:03.53#ibcon#about to write, iclass 19, count 0 2006.258.00:04:03.53#ibcon#wrote, iclass 19, count 0 2006.258.00:04:03.53#ibcon#about to read 3, iclass 19, count 0 2006.258.00:04:03.57#ibcon#read 3, iclass 19, count 0 2006.258.00:04:03.57#ibcon#about to read 4, iclass 19, count 0 2006.258.00:04:03.57#ibcon#read 4, iclass 19, count 0 2006.258.00:04:03.57#ibcon#about to read 5, iclass 19, count 0 2006.258.00:04:03.57#ibcon#read 5, iclass 19, count 0 2006.258.00:04:03.57#ibcon#about to read 6, iclass 19, count 0 2006.258.00:04:03.57#ibcon#read 6, iclass 19, count 0 2006.258.00:04:03.57#ibcon#end of sib2, iclass 19, count 0 2006.258.00:04:03.57#ibcon#*after write, iclass 19, count 0 2006.258.00:04:03.57#ibcon#*before return 0, iclass 19, count 0 2006.258.00:04:03.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:03.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:03.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:04:03.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:04:03.58$vck44/va=8,4 2006.258.00:04:03.58#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.00:04:03.58#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.00:04:03.58#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:03.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:03.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:03.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:03.62#ibcon#enter wrdev, iclass 21, count 2 2006.258.00:04:03.62#ibcon#first serial, iclass 21, count 2 2006.258.00:04:03.62#ibcon#enter sib2, iclass 21, count 2 2006.258.00:04:03.62#ibcon#flushed, iclass 21, count 2 2006.258.00:04:03.62#ibcon#about to write, iclass 21, count 2 2006.258.00:04:03.62#ibcon#wrote, iclass 21, count 2 2006.258.00:04:03.62#ibcon#about to read 3, iclass 21, count 2 2006.258.00:04:03.64#ibcon#read 3, iclass 21, count 2 2006.258.00:04:03.64#ibcon#about to read 4, iclass 21, count 2 2006.258.00:04:03.64#ibcon#read 4, iclass 21, count 2 2006.258.00:04:03.64#ibcon#about to read 5, iclass 21, count 2 2006.258.00:04:03.64#ibcon#read 5, iclass 21, count 2 2006.258.00:04:03.64#ibcon#about to read 6, iclass 21, count 2 2006.258.00:04:03.64#ibcon#read 6, iclass 21, count 2 2006.258.00:04:03.64#ibcon#end of sib2, iclass 21, count 2 2006.258.00:04:03.64#ibcon#*mode == 0, iclass 21, count 2 2006.258.00:04:03.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.00:04:03.64#ibcon#[25=AT08-04\r\n] 2006.258.00:04:03.64#ibcon#*before write, iclass 21, count 2 2006.258.00:04:03.64#ibcon#enter sib2, iclass 21, count 2 2006.258.00:04:03.64#ibcon#flushed, iclass 21, count 2 2006.258.00:04:03.64#ibcon#about to write, iclass 21, count 2 2006.258.00:04:03.64#ibcon#wrote, iclass 21, count 2 2006.258.00:04:03.64#ibcon#about to read 3, iclass 21, count 2 2006.258.00:04:03.67#ibcon#read 3, iclass 21, count 2 2006.258.00:04:03.67#ibcon#about to read 4, iclass 21, count 2 2006.258.00:04:03.67#ibcon#read 4, iclass 21, count 2 2006.258.00:04:03.67#ibcon#about to read 5, iclass 21, count 2 2006.258.00:04:03.67#ibcon#read 5, iclass 21, count 2 2006.258.00:04:03.67#ibcon#about to read 6, iclass 21, count 2 2006.258.00:04:03.67#ibcon#read 6, iclass 21, count 2 2006.258.00:04:03.67#ibcon#end of sib2, iclass 21, count 2 2006.258.00:04:03.67#ibcon#*after write, iclass 21, count 2 2006.258.00:04:03.67#ibcon#*before return 0, iclass 21, count 2 2006.258.00:04:03.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:03.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:03.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.00:04:03.67#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:03.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:03.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:03.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:03.79#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:04:03.79#ibcon#first serial, iclass 21, count 0 2006.258.00:04:03.79#ibcon#enter sib2, iclass 21, count 0 2006.258.00:04:03.79#ibcon#flushed, iclass 21, count 0 2006.258.00:04:03.79#ibcon#about to write, iclass 21, count 0 2006.258.00:04:03.79#ibcon#wrote, iclass 21, count 0 2006.258.00:04:03.79#ibcon#about to read 3, iclass 21, count 0 2006.258.00:04:03.81#ibcon#read 3, iclass 21, count 0 2006.258.00:04:03.81#ibcon#about to read 4, iclass 21, count 0 2006.258.00:04:03.81#ibcon#read 4, iclass 21, count 0 2006.258.00:04:03.81#ibcon#about to read 5, iclass 21, count 0 2006.258.00:04:03.81#ibcon#read 5, iclass 21, count 0 2006.258.00:04:03.81#ibcon#about to read 6, iclass 21, count 0 2006.258.00:04:03.81#ibcon#read 6, iclass 21, count 0 2006.258.00:04:03.81#ibcon#end of sib2, iclass 21, count 0 2006.258.00:04:03.81#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:04:03.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:04:03.81#ibcon#[25=USB\r\n] 2006.258.00:04:03.81#ibcon#*before write, iclass 21, count 0 2006.258.00:04:03.81#ibcon#enter sib2, iclass 21, count 0 2006.258.00:04:03.81#ibcon#flushed, iclass 21, count 0 2006.258.00:04:03.81#ibcon#about to write, iclass 21, count 0 2006.258.00:04:03.81#ibcon#wrote, iclass 21, count 0 2006.258.00:04:03.81#ibcon#about to read 3, iclass 21, count 0 2006.258.00:04:03.84#ibcon#read 3, iclass 21, count 0 2006.258.00:04:03.84#ibcon#about to read 4, iclass 21, count 0 2006.258.00:04:03.84#ibcon#read 4, iclass 21, count 0 2006.258.00:04:03.84#ibcon#about to read 5, iclass 21, count 0 2006.258.00:04:03.84#ibcon#read 5, iclass 21, count 0 2006.258.00:04:03.84#ibcon#about to read 6, iclass 21, count 0 2006.258.00:04:03.84#ibcon#read 6, iclass 21, count 0 2006.258.00:04:03.84#ibcon#end of sib2, iclass 21, count 0 2006.258.00:04:03.84#ibcon#*after write, iclass 21, count 0 2006.258.00:04:03.84#ibcon#*before return 0, iclass 21, count 0 2006.258.00:04:03.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:03.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:03.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:04:03.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:04:03.85$vck44/vblo=1,629.99 2006.258.00:04:03.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.00:04:03.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.00:04:03.85#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:03.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:03.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:03.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:03.85#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:04:03.85#ibcon#first serial, iclass 23, count 0 2006.258.00:04:03.85#ibcon#enter sib2, iclass 23, count 0 2006.258.00:04:03.85#ibcon#flushed, iclass 23, count 0 2006.258.00:04:03.85#ibcon#about to write, iclass 23, count 0 2006.258.00:04:03.85#ibcon#wrote, iclass 23, count 0 2006.258.00:04:03.85#ibcon#about to read 3, iclass 23, count 0 2006.258.00:04:03.86#ibcon#read 3, iclass 23, count 0 2006.258.00:04:03.86#ibcon#about to read 4, iclass 23, count 0 2006.258.00:04:03.86#ibcon#read 4, iclass 23, count 0 2006.258.00:04:03.86#ibcon#about to read 5, iclass 23, count 0 2006.258.00:04:03.86#ibcon#read 5, iclass 23, count 0 2006.258.00:04:03.86#ibcon#about to read 6, iclass 23, count 0 2006.258.00:04:03.86#ibcon#read 6, iclass 23, count 0 2006.258.00:04:03.86#ibcon#end of sib2, iclass 23, count 0 2006.258.00:04:03.86#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:04:03.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:04:03.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:04:03.86#ibcon#*before write, iclass 23, count 0 2006.258.00:04:03.86#ibcon#enter sib2, iclass 23, count 0 2006.258.00:04:03.86#ibcon#flushed, iclass 23, count 0 2006.258.00:04:03.86#ibcon#about to write, iclass 23, count 0 2006.258.00:04:03.86#ibcon#wrote, iclass 23, count 0 2006.258.00:04:03.86#ibcon#about to read 3, iclass 23, count 0 2006.258.00:04:03.90#ibcon#read 3, iclass 23, count 0 2006.258.00:04:03.90#ibcon#about to read 4, iclass 23, count 0 2006.258.00:04:03.90#ibcon#read 4, iclass 23, count 0 2006.258.00:04:03.90#ibcon#about to read 5, iclass 23, count 0 2006.258.00:04:03.90#ibcon#read 5, iclass 23, count 0 2006.258.00:04:03.90#ibcon#about to read 6, iclass 23, count 0 2006.258.00:04:03.90#ibcon#read 6, iclass 23, count 0 2006.258.00:04:03.90#ibcon#end of sib2, iclass 23, count 0 2006.258.00:04:03.90#ibcon#*after write, iclass 23, count 0 2006.258.00:04:03.90#ibcon#*before return 0, iclass 23, count 0 2006.258.00:04:03.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:03.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:03.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:04:03.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:04:03.91$vck44/vb=1,4 2006.258.00:04:03.91#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.258.00:04:03.91#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.258.00:04:03.91#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:03.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:04:03.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:04:03.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:04:03.91#ibcon#enter wrdev, iclass 25, count 2 2006.258.00:04:03.91#ibcon#first serial, iclass 25, count 2 2006.258.00:04:03.91#ibcon#enter sib2, iclass 25, count 2 2006.258.00:04:03.91#ibcon#flushed, iclass 25, count 2 2006.258.00:04:03.91#ibcon#about to write, iclass 25, count 2 2006.258.00:04:03.91#ibcon#wrote, iclass 25, count 2 2006.258.00:04:03.91#ibcon#about to read 3, iclass 25, count 2 2006.258.00:04:03.92#ibcon#read 3, iclass 25, count 2 2006.258.00:04:03.92#ibcon#about to read 4, iclass 25, count 2 2006.258.00:04:03.92#ibcon#read 4, iclass 25, count 2 2006.258.00:04:03.92#ibcon#about to read 5, iclass 25, count 2 2006.258.00:04:03.92#ibcon#read 5, iclass 25, count 2 2006.258.00:04:03.92#ibcon#about to read 6, iclass 25, count 2 2006.258.00:04:03.92#ibcon#read 6, iclass 25, count 2 2006.258.00:04:03.92#ibcon#end of sib2, iclass 25, count 2 2006.258.00:04:03.92#ibcon#*mode == 0, iclass 25, count 2 2006.258.00:04:03.92#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.258.00:04:03.92#ibcon#[27=AT01-04\r\n] 2006.258.00:04:03.92#ibcon#*before write, iclass 25, count 2 2006.258.00:04:03.92#ibcon#enter sib2, iclass 25, count 2 2006.258.00:04:03.92#ibcon#flushed, iclass 25, count 2 2006.258.00:04:03.92#ibcon#about to write, iclass 25, count 2 2006.258.00:04:03.92#ibcon#wrote, iclass 25, count 2 2006.258.00:04:03.92#ibcon#about to read 3, iclass 25, count 2 2006.258.00:04:03.95#ibcon#read 3, iclass 25, count 2 2006.258.00:04:03.95#ibcon#about to read 4, iclass 25, count 2 2006.258.00:04:03.95#ibcon#read 4, iclass 25, count 2 2006.258.00:04:03.95#ibcon#about to read 5, iclass 25, count 2 2006.258.00:04:03.95#ibcon#read 5, iclass 25, count 2 2006.258.00:04:03.95#ibcon#about to read 6, iclass 25, count 2 2006.258.00:04:03.95#ibcon#read 6, iclass 25, count 2 2006.258.00:04:03.95#ibcon#end of sib2, iclass 25, count 2 2006.258.00:04:03.95#ibcon#*after write, iclass 25, count 2 2006.258.00:04:03.95#ibcon#*before return 0, iclass 25, count 2 2006.258.00:04:03.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:04:03.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:04:03.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.258.00:04:03.95#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:03.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:04:04.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:04:04.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:04:04.07#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:04:04.07#ibcon#first serial, iclass 25, count 0 2006.258.00:04:04.07#ibcon#enter sib2, iclass 25, count 0 2006.258.00:04:04.07#ibcon#flushed, iclass 25, count 0 2006.258.00:04:04.07#ibcon#about to write, iclass 25, count 0 2006.258.00:04:04.07#ibcon#wrote, iclass 25, count 0 2006.258.00:04:04.07#ibcon#about to read 3, iclass 25, count 0 2006.258.00:04:04.09#ibcon#read 3, iclass 25, count 0 2006.258.00:04:04.09#ibcon#about to read 4, iclass 25, count 0 2006.258.00:04:04.09#ibcon#read 4, iclass 25, count 0 2006.258.00:04:04.09#ibcon#about to read 5, iclass 25, count 0 2006.258.00:04:04.09#ibcon#read 5, iclass 25, count 0 2006.258.00:04:04.09#ibcon#about to read 6, iclass 25, count 0 2006.258.00:04:04.09#ibcon#read 6, iclass 25, count 0 2006.258.00:04:04.09#ibcon#end of sib2, iclass 25, count 0 2006.258.00:04:04.09#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:04:04.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:04:04.09#ibcon#[27=USB\r\n] 2006.258.00:04:04.09#ibcon#*before write, iclass 25, count 0 2006.258.00:04:04.09#ibcon#enter sib2, iclass 25, count 0 2006.258.00:04:04.09#ibcon#flushed, iclass 25, count 0 2006.258.00:04:04.09#ibcon#about to write, iclass 25, count 0 2006.258.00:04:04.09#ibcon#wrote, iclass 25, count 0 2006.258.00:04:04.09#ibcon#about to read 3, iclass 25, count 0 2006.258.00:04:04.12#ibcon#read 3, iclass 25, count 0 2006.258.00:04:04.12#ibcon#about to read 4, iclass 25, count 0 2006.258.00:04:04.12#ibcon#read 4, iclass 25, count 0 2006.258.00:04:04.12#ibcon#about to read 5, iclass 25, count 0 2006.258.00:04:04.12#ibcon#read 5, iclass 25, count 0 2006.258.00:04:04.12#ibcon#about to read 6, iclass 25, count 0 2006.258.00:04:04.12#ibcon#read 6, iclass 25, count 0 2006.258.00:04:04.12#ibcon#end of sib2, iclass 25, count 0 2006.258.00:04:04.12#ibcon#*after write, iclass 25, count 0 2006.258.00:04:04.12#ibcon#*before return 0, iclass 25, count 0 2006.258.00:04:04.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:04:04.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:04:04.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:04:04.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:04:04.13$vck44/vblo=2,634.99 2006.258.00:04:04.13#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.00:04:04.13#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.00:04:04.13#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:04.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:04.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:04.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:04.13#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:04:04.13#ibcon#first serial, iclass 27, count 0 2006.258.00:04:04.13#ibcon#enter sib2, iclass 27, count 0 2006.258.00:04:04.13#ibcon#flushed, iclass 27, count 0 2006.258.00:04:04.13#ibcon#about to write, iclass 27, count 0 2006.258.00:04:04.13#ibcon#wrote, iclass 27, count 0 2006.258.00:04:04.13#ibcon#about to read 3, iclass 27, count 0 2006.258.00:04:04.14#ibcon#read 3, iclass 27, count 0 2006.258.00:04:04.14#ibcon#about to read 4, iclass 27, count 0 2006.258.00:04:04.14#ibcon#read 4, iclass 27, count 0 2006.258.00:04:04.14#ibcon#about to read 5, iclass 27, count 0 2006.258.00:04:04.14#ibcon#read 5, iclass 27, count 0 2006.258.00:04:04.14#ibcon#about to read 6, iclass 27, count 0 2006.258.00:04:04.14#ibcon#read 6, iclass 27, count 0 2006.258.00:04:04.14#ibcon#end of sib2, iclass 27, count 0 2006.258.00:04:04.14#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:04:04.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:04:04.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:04:04.14#ibcon#*before write, iclass 27, count 0 2006.258.00:04:04.14#ibcon#enter sib2, iclass 27, count 0 2006.258.00:04:04.14#ibcon#flushed, iclass 27, count 0 2006.258.00:04:04.14#ibcon#about to write, iclass 27, count 0 2006.258.00:04:04.14#ibcon#wrote, iclass 27, count 0 2006.258.00:04:04.14#ibcon#about to read 3, iclass 27, count 0 2006.258.00:04:04.18#ibcon#read 3, iclass 27, count 0 2006.258.00:04:04.18#ibcon#about to read 4, iclass 27, count 0 2006.258.00:04:04.18#ibcon#read 4, iclass 27, count 0 2006.258.00:04:04.18#ibcon#about to read 5, iclass 27, count 0 2006.258.00:04:04.18#ibcon#read 5, iclass 27, count 0 2006.258.00:04:04.18#ibcon#about to read 6, iclass 27, count 0 2006.258.00:04:04.18#ibcon#read 6, iclass 27, count 0 2006.258.00:04:04.18#ibcon#end of sib2, iclass 27, count 0 2006.258.00:04:04.18#ibcon#*after write, iclass 27, count 0 2006.258.00:04:04.18#ibcon#*before return 0, iclass 27, count 0 2006.258.00:04:04.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:04.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:04:04.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:04:04.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:04:04.19$vck44/vb=2,5 2006.258.00:04:04.19#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.00:04:04.19#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.00:04:04.19#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:04.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:04.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:04.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:04.23#ibcon#enter wrdev, iclass 29, count 2 2006.258.00:04:04.23#ibcon#first serial, iclass 29, count 2 2006.258.00:04:04.23#ibcon#enter sib2, iclass 29, count 2 2006.258.00:04:04.23#ibcon#flushed, iclass 29, count 2 2006.258.00:04:04.23#ibcon#about to write, iclass 29, count 2 2006.258.00:04:04.23#ibcon#wrote, iclass 29, count 2 2006.258.00:04:04.23#ibcon#about to read 3, iclass 29, count 2 2006.258.00:04:04.25#ibcon#read 3, iclass 29, count 2 2006.258.00:04:04.25#ibcon#about to read 4, iclass 29, count 2 2006.258.00:04:04.25#ibcon#read 4, iclass 29, count 2 2006.258.00:04:04.25#ibcon#about to read 5, iclass 29, count 2 2006.258.00:04:04.25#ibcon#read 5, iclass 29, count 2 2006.258.00:04:04.25#ibcon#about to read 6, iclass 29, count 2 2006.258.00:04:04.25#ibcon#read 6, iclass 29, count 2 2006.258.00:04:04.25#ibcon#end of sib2, iclass 29, count 2 2006.258.00:04:04.25#ibcon#*mode == 0, iclass 29, count 2 2006.258.00:04:04.25#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.00:04:04.25#ibcon#[27=AT02-05\r\n] 2006.258.00:04:04.25#ibcon#*before write, iclass 29, count 2 2006.258.00:04:04.25#ibcon#enter sib2, iclass 29, count 2 2006.258.00:04:04.25#ibcon#flushed, iclass 29, count 2 2006.258.00:04:04.25#ibcon#about to write, iclass 29, count 2 2006.258.00:04:04.25#ibcon#wrote, iclass 29, count 2 2006.258.00:04:04.25#ibcon#about to read 3, iclass 29, count 2 2006.258.00:04:04.28#ibcon#read 3, iclass 29, count 2 2006.258.00:04:04.28#ibcon#about to read 4, iclass 29, count 2 2006.258.00:04:04.28#ibcon#read 4, iclass 29, count 2 2006.258.00:04:04.28#ibcon#about to read 5, iclass 29, count 2 2006.258.00:04:04.28#ibcon#read 5, iclass 29, count 2 2006.258.00:04:04.28#ibcon#about to read 6, iclass 29, count 2 2006.258.00:04:04.28#ibcon#read 6, iclass 29, count 2 2006.258.00:04:04.28#ibcon#end of sib2, iclass 29, count 2 2006.258.00:04:04.28#ibcon#*after write, iclass 29, count 2 2006.258.00:04:04.28#ibcon#*before return 0, iclass 29, count 2 2006.258.00:04:04.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:04.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:04:04.28#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.00:04:04.28#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:04.28#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:04.37#abcon#<5=/16 1.5 3.9 21.51 761016.2\r\n> 2006.258.00:04:04.39#abcon#{5=INTERFACE CLEAR} 2006.258.00:04:04.40#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:04.40#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:04.40#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:04:04.40#ibcon#first serial, iclass 29, count 0 2006.258.00:04:04.40#ibcon#enter sib2, iclass 29, count 0 2006.258.00:04:04.40#ibcon#flushed, iclass 29, count 0 2006.258.00:04:04.40#ibcon#about to write, iclass 29, count 0 2006.258.00:04:04.40#ibcon#wrote, iclass 29, count 0 2006.258.00:04:04.40#ibcon#about to read 3, iclass 29, count 0 2006.258.00:04:04.42#ibcon#read 3, iclass 29, count 0 2006.258.00:04:04.42#ibcon#about to read 4, iclass 29, count 0 2006.258.00:04:04.42#ibcon#read 4, iclass 29, count 0 2006.258.00:04:04.42#ibcon#about to read 5, iclass 29, count 0 2006.258.00:04:04.42#ibcon#read 5, iclass 29, count 0 2006.258.00:04:04.42#ibcon#about to read 6, iclass 29, count 0 2006.258.00:04:04.42#ibcon#read 6, iclass 29, count 0 2006.258.00:04:04.42#ibcon#end of sib2, iclass 29, count 0 2006.258.00:04:04.42#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:04:04.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:04:04.42#ibcon#[27=USB\r\n] 2006.258.00:04:04.42#ibcon#*before write, iclass 29, count 0 2006.258.00:04:04.42#ibcon#enter sib2, iclass 29, count 0 2006.258.00:04:04.42#ibcon#flushed, iclass 29, count 0 2006.258.00:04:04.42#ibcon#about to write, iclass 29, count 0 2006.258.00:04:04.42#ibcon#wrote, iclass 29, count 0 2006.258.00:04:04.42#ibcon#about to read 3, iclass 29, count 0 2006.258.00:04:04.45#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:04:04.45#ibcon#read 3, iclass 29, count 0 2006.258.00:04:04.45#ibcon#about to read 4, iclass 29, count 0 2006.258.00:04:04.45#ibcon#read 4, iclass 29, count 0 2006.258.00:04:04.45#ibcon#about to read 5, iclass 29, count 0 2006.258.00:04:04.45#ibcon#read 5, iclass 29, count 0 2006.258.00:04:04.45#ibcon#about to read 6, iclass 29, count 0 2006.258.00:04:04.45#ibcon#read 6, iclass 29, count 0 2006.258.00:04:04.45#ibcon#end of sib2, iclass 29, count 0 2006.258.00:04:04.45#ibcon#*after write, iclass 29, count 0 2006.258.00:04:04.45#ibcon#*before return 0, iclass 29, count 0 2006.258.00:04:04.45#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:04.45#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:04:04.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:04:04.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:04:04.46$vck44/vblo=3,649.99 2006.258.00:04:04.46#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.00:04:04.46#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.00:04:04.46#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:04.46#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:04.46#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:04.46#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:04.46#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:04:04.46#ibcon#first serial, iclass 35, count 0 2006.258.00:04:04.46#ibcon#enter sib2, iclass 35, count 0 2006.258.00:04:04.46#ibcon#flushed, iclass 35, count 0 2006.258.00:04:04.46#ibcon#about to write, iclass 35, count 0 2006.258.00:04:04.46#ibcon#wrote, iclass 35, count 0 2006.258.00:04:04.46#ibcon#about to read 3, iclass 35, count 0 2006.258.00:04:04.47#ibcon#read 3, iclass 35, count 0 2006.258.00:04:04.47#ibcon#about to read 4, iclass 35, count 0 2006.258.00:04:04.47#ibcon#read 4, iclass 35, count 0 2006.258.00:04:04.47#ibcon#about to read 5, iclass 35, count 0 2006.258.00:04:04.47#ibcon#read 5, iclass 35, count 0 2006.258.00:04:04.47#ibcon#about to read 6, iclass 35, count 0 2006.258.00:04:04.47#ibcon#read 6, iclass 35, count 0 2006.258.00:04:04.47#ibcon#end of sib2, iclass 35, count 0 2006.258.00:04:04.47#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:04:04.47#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:04:04.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:04:04.47#ibcon#*before write, iclass 35, count 0 2006.258.00:04:04.47#ibcon#enter sib2, iclass 35, count 0 2006.258.00:04:04.47#ibcon#flushed, iclass 35, count 0 2006.258.00:04:04.47#ibcon#about to write, iclass 35, count 0 2006.258.00:04:04.47#ibcon#wrote, iclass 35, count 0 2006.258.00:04:04.47#ibcon#about to read 3, iclass 35, count 0 2006.258.00:04:04.51#ibcon#read 3, iclass 35, count 0 2006.258.00:04:04.51#ibcon#about to read 4, iclass 35, count 0 2006.258.00:04:04.51#ibcon#read 4, iclass 35, count 0 2006.258.00:04:04.51#ibcon#about to read 5, iclass 35, count 0 2006.258.00:04:04.51#ibcon#read 5, iclass 35, count 0 2006.258.00:04:04.51#ibcon#about to read 6, iclass 35, count 0 2006.258.00:04:04.51#ibcon#read 6, iclass 35, count 0 2006.258.00:04:04.51#ibcon#end of sib2, iclass 35, count 0 2006.258.00:04:04.51#ibcon#*after write, iclass 35, count 0 2006.258.00:04:04.51#ibcon#*before return 0, iclass 35, count 0 2006.258.00:04:04.51#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:04.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:04:04.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:04:04.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:04:04.60$vck44/vb=3,4 2006.258.00:04:04.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.00:04:04.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.00:04:04.60#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:04.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:04.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:04.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:04.60#ibcon#enter wrdev, iclass 37, count 2 2006.258.00:04:04.60#ibcon#first serial, iclass 37, count 2 2006.258.00:04:04.60#ibcon#enter sib2, iclass 37, count 2 2006.258.00:04:04.60#ibcon#flushed, iclass 37, count 2 2006.258.00:04:04.60#ibcon#about to write, iclass 37, count 2 2006.258.00:04:04.60#ibcon#wrote, iclass 37, count 2 2006.258.00:04:04.60#ibcon#about to read 3, iclass 37, count 2 2006.258.00:04:04.62#ibcon#read 3, iclass 37, count 2 2006.258.00:04:04.62#ibcon#about to read 4, iclass 37, count 2 2006.258.00:04:04.62#ibcon#read 4, iclass 37, count 2 2006.258.00:04:04.62#ibcon#about to read 5, iclass 37, count 2 2006.258.00:04:04.62#ibcon#read 5, iclass 37, count 2 2006.258.00:04:04.62#ibcon#about to read 6, iclass 37, count 2 2006.258.00:04:04.62#ibcon#read 6, iclass 37, count 2 2006.258.00:04:04.62#ibcon#end of sib2, iclass 37, count 2 2006.258.00:04:04.62#ibcon#*mode == 0, iclass 37, count 2 2006.258.00:04:04.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.00:04:04.62#ibcon#[27=AT03-04\r\n] 2006.258.00:04:04.62#ibcon#*before write, iclass 37, count 2 2006.258.00:04:04.62#ibcon#enter sib2, iclass 37, count 2 2006.258.00:04:04.62#ibcon#flushed, iclass 37, count 2 2006.258.00:04:04.62#ibcon#about to write, iclass 37, count 2 2006.258.00:04:04.62#ibcon#wrote, iclass 37, count 2 2006.258.00:04:04.62#ibcon#about to read 3, iclass 37, count 2 2006.258.00:04:04.65#ibcon#read 3, iclass 37, count 2 2006.258.00:04:04.65#ibcon#about to read 4, iclass 37, count 2 2006.258.00:04:04.65#ibcon#read 4, iclass 37, count 2 2006.258.00:04:04.65#ibcon#about to read 5, iclass 37, count 2 2006.258.00:04:04.65#ibcon#read 5, iclass 37, count 2 2006.258.00:04:04.65#ibcon#about to read 6, iclass 37, count 2 2006.258.00:04:04.65#ibcon#read 6, iclass 37, count 2 2006.258.00:04:04.65#ibcon#end of sib2, iclass 37, count 2 2006.258.00:04:04.65#ibcon#*after write, iclass 37, count 2 2006.258.00:04:04.65#ibcon#*before return 0, iclass 37, count 2 2006.258.00:04:04.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:04.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:04:04.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.00:04:04.65#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:04.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:04.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:04.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:04.77#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:04:04.77#ibcon#first serial, iclass 37, count 0 2006.258.00:04:04.77#ibcon#enter sib2, iclass 37, count 0 2006.258.00:04:04.77#ibcon#flushed, iclass 37, count 0 2006.258.00:04:04.77#ibcon#about to write, iclass 37, count 0 2006.258.00:04:04.77#ibcon#wrote, iclass 37, count 0 2006.258.00:04:04.77#ibcon#about to read 3, iclass 37, count 0 2006.258.00:04:04.79#ibcon#read 3, iclass 37, count 0 2006.258.00:04:04.79#ibcon#about to read 4, iclass 37, count 0 2006.258.00:04:04.79#ibcon#read 4, iclass 37, count 0 2006.258.00:04:04.79#ibcon#about to read 5, iclass 37, count 0 2006.258.00:04:04.79#ibcon#read 5, iclass 37, count 0 2006.258.00:04:04.79#ibcon#about to read 6, iclass 37, count 0 2006.258.00:04:04.79#ibcon#read 6, iclass 37, count 0 2006.258.00:04:04.79#ibcon#end of sib2, iclass 37, count 0 2006.258.00:04:04.79#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:04:04.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:04:04.79#ibcon#[27=USB\r\n] 2006.258.00:04:04.79#ibcon#*before write, iclass 37, count 0 2006.258.00:04:04.79#ibcon#enter sib2, iclass 37, count 0 2006.258.00:04:04.79#ibcon#flushed, iclass 37, count 0 2006.258.00:04:04.79#ibcon#about to write, iclass 37, count 0 2006.258.00:04:04.79#ibcon#wrote, iclass 37, count 0 2006.258.00:04:04.79#ibcon#about to read 3, iclass 37, count 0 2006.258.00:04:04.82#ibcon#read 3, iclass 37, count 0 2006.258.00:04:04.82#ibcon#about to read 4, iclass 37, count 0 2006.258.00:04:04.82#ibcon#read 4, iclass 37, count 0 2006.258.00:04:04.82#ibcon#about to read 5, iclass 37, count 0 2006.258.00:04:04.82#ibcon#read 5, iclass 37, count 0 2006.258.00:04:04.82#ibcon#about to read 6, iclass 37, count 0 2006.258.00:04:04.82#ibcon#read 6, iclass 37, count 0 2006.258.00:04:04.82#ibcon#end of sib2, iclass 37, count 0 2006.258.00:04:04.82#ibcon#*after write, iclass 37, count 0 2006.258.00:04:04.82#ibcon#*before return 0, iclass 37, count 0 2006.258.00:04:04.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:04.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:04:04.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:04:04.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:04:04.83$vck44/vblo=4,679.99 2006.258.00:04:04.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.00:04:04.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.00:04:04.83#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:04.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:04.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:04.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:04.83#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:04:04.83#ibcon#first serial, iclass 39, count 0 2006.258.00:04:04.83#ibcon#enter sib2, iclass 39, count 0 2006.258.00:04:04.83#ibcon#flushed, iclass 39, count 0 2006.258.00:04:04.83#ibcon#about to write, iclass 39, count 0 2006.258.00:04:04.83#ibcon#wrote, iclass 39, count 0 2006.258.00:04:04.83#ibcon#about to read 3, iclass 39, count 0 2006.258.00:04:04.84#ibcon#read 3, iclass 39, count 0 2006.258.00:04:04.84#ibcon#about to read 4, iclass 39, count 0 2006.258.00:04:04.84#ibcon#read 4, iclass 39, count 0 2006.258.00:04:04.84#ibcon#about to read 5, iclass 39, count 0 2006.258.00:04:04.84#ibcon#read 5, iclass 39, count 0 2006.258.00:04:04.84#ibcon#about to read 6, iclass 39, count 0 2006.258.00:04:04.84#ibcon#read 6, iclass 39, count 0 2006.258.00:04:04.84#ibcon#end of sib2, iclass 39, count 0 2006.258.00:04:04.84#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:04:04.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:04:04.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:04:04.84#ibcon#*before write, iclass 39, count 0 2006.258.00:04:04.84#ibcon#enter sib2, iclass 39, count 0 2006.258.00:04:04.84#ibcon#flushed, iclass 39, count 0 2006.258.00:04:04.84#ibcon#about to write, iclass 39, count 0 2006.258.00:04:04.84#ibcon#wrote, iclass 39, count 0 2006.258.00:04:04.84#ibcon#about to read 3, iclass 39, count 0 2006.258.00:04:04.88#ibcon#read 3, iclass 39, count 0 2006.258.00:04:04.88#ibcon#about to read 4, iclass 39, count 0 2006.258.00:04:04.88#ibcon#read 4, iclass 39, count 0 2006.258.00:04:04.88#ibcon#about to read 5, iclass 39, count 0 2006.258.00:04:04.88#ibcon#read 5, iclass 39, count 0 2006.258.00:04:04.88#ibcon#about to read 6, iclass 39, count 0 2006.258.00:04:04.88#ibcon#read 6, iclass 39, count 0 2006.258.00:04:04.88#ibcon#end of sib2, iclass 39, count 0 2006.258.00:04:04.88#ibcon#*after write, iclass 39, count 0 2006.258.00:04:04.88#ibcon#*before return 0, iclass 39, count 0 2006.258.00:04:04.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:04.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:04:04.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:04:04.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:04:04.89$vck44/vb=4,5 2006.258.00:04:04.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.00:04:04.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.00:04:04.89#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:04.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:04.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:04.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:04.93#ibcon#enter wrdev, iclass 3, count 2 2006.258.00:04:04.93#ibcon#first serial, iclass 3, count 2 2006.258.00:04:04.93#ibcon#enter sib2, iclass 3, count 2 2006.258.00:04:04.93#ibcon#flushed, iclass 3, count 2 2006.258.00:04:04.93#ibcon#about to write, iclass 3, count 2 2006.258.00:04:04.93#ibcon#wrote, iclass 3, count 2 2006.258.00:04:04.93#ibcon#about to read 3, iclass 3, count 2 2006.258.00:04:04.95#ibcon#read 3, iclass 3, count 2 2006.258.00:04:04.95#ibcon#about to read 4, iclass 3, count 2 2006.258.00:04:04.95#ibcon#read 4, iclass 3, count 2 2006.258.00:04:04.95#ibcon#about to read 5, iclass 3, count 2 2006.258.00:04:04.95#ibcon#read 5, iclass 3, count 2 2006.258.00:04:04.95#ibcon#about to read 6, iclass 3, count 2 2006.258.00:04:04.95#ibcon#read 6, iclass 3, count 2 2006.258.00:04:04.95#ibcon#end of sib2, iclass 3, count 2 2006.258.00:04:04.95#ibcon#*mode == 0, iclass 3, count 2 2006.258.00:04:04.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.00:04:04.95#ibcon#[27=AT04-05\r\n] 2006.258.00:04:04.95#ibcon#*before write, iclass 3, count 2 2006.258.00:04:04.95#ibcon#enter sib2, iclass 3, count 2 2006.258.00:04:04.95#ibcon#flushed, iclass 3, count 2 2006.258.00:04:04.95#ibcon#about to write, iclass 3, count 2 2006.258.00:04:04.95#ibcon#wrote, iclass 3, count 2 2006.258.00:04:04.95#ibcon#about to read 3, iclass 3, count 2 2006.258.00:04:04.98#ibcon#read 3, iclass 3, count 2 2006.258.00:04:04.98#ibcon#about to read 4, iclass 3, count 2 2006.258.00:04:04.98#ibcon#read 4, iclass 3, count 2 2006.258.00:04:04.98#ibcon#about to read 5, iclass 3, count 2 2006.258.00:04:04.98#ibcon#read 5, iclass 3, count 2 2006.258.00:04:04.98#ibcon#about to read 6, iclass 3, count 2 2006.258.00:04:04.98#ibcon#read 6, iclass 3, count 2 2006.258.00:04:04.98#ibcon#end of sib2, iclass 3, count 2 2006.258.00:04:04.98#ibcon#*after write, iclass 3, count 2 2006.258.00:04:04.98#ibcon#*before return 0, iclass 3, count 2 2006.258.00:04:04.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:04.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:04:04.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.00:04:04.98#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:04.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:05.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:05.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:05.10#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:04:05.10#ibcon#first serial, iclass 3, count 0 2006.258.00:04:05.10#ibcon#enter sib2, iclass 3, count 0 2006.258.00:04:05.10#ibcon#flushed, iclass 3, count 0 2006.258.00:04:05.10#ibcon#about to write, iclass 3, count 0 2006.258.00:04:05.10#ibcon#wrote, iclass 3, count 0 2006.258.00:04:05.10#ibcon#about to read 3, iclass 3, count 0 2006.258.00:04:05.12#ibcon#read 3, iclass 3, count 0 2006.258.00:04:05.12#ibcon#about to read 4, iclass 3, count 0 2006.258.00:04:05.12#ibcon#read 4, iclass 3, count 0 2006.258.00:04:05.12#ibcon#about to read 5, iclass 3, count 0 2006.258.00:04:05.12#ibcon#read 5, iclass 3, count 0 2006.258.00:04:05.12#ibcon#about to read 6, iclass 3, count 0 2006.258.00:04:05.12#ibcon#read 6, iclass 3, count 0 2006.258.00:04:05.12#ibcon#end of sib2, iclass 3, count 0 2006.258.00:04:05.12#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:04:05.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:04:05.12#ibcon#[27=USB\r\n] 2006.258.00:04:05.12#ibcon#*before write, iclass 3, count 0 2006.258.00:04:05.12#ibcon#enter sib2, iclass 3, count 0 2006.258.00:04:05.12#ibcon#flushed, iclass 3, count 0 2006.258.00:04:05.12#ibcon#about to write, iclass 3, count 0 2006.258.00:04:05.12#ibcon#wrote, iclass 3, count 0 2006.258.00:04:05.12#ibcon#about to read 3, iclass 3, count 0 2006.258.00:04:05.15#ibcon#read 3, iclass 3, count 0 2006.258.00:04:05.15#ibcon#about to read 4, iclass 3, count 0 2006.258.00:04:05.15#ibcon#read 4, iclass 3, count 0 2006.258.00:04:05.15#ibcon#about to read 5, iclass 3, count 0 2006.258.00:04:05.15#ibcon#read 5, iclass 3, count 0 2006.258.00:04:05.15#ibcon#about to read 6, iclass 3, count 0 2006.258.00:04:05.15#ibcon#read 6, iclass 3, count 0 2006.258.00:04:05.15#ibcon#end of sib2, iclass 3, count 0 2006.258.00:04:05.15#ibcon#*after write, iclass 3, count 0 2006.258.00:04:05.15#ibcon#*before return 0, iclass 3, count 0 2006.258.00:04:05.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:05.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:04:05.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:04:05.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:04:05.16$vck44/vblo=5,709.99 2006.258.00:04:05.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.00:04:05.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.00:04:05.16#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:05.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:05.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:05.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:05.16#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:04:05.16#ibcon#first serial, iclass 5, count 0 2006.258.00:04:05.16#ibcon#enter sib2, iclass 5, count 0 2006.258.00:04:05.16#ibcon#flushed, iclass 5, count 0 2006.258.00:04:05.16#ibcon#about to write, iclass 5, count 0 2006.258.00:04:05.16#ibcon#wrote, iclass 5, count 0 2006.258.00:04:05.16#ibcon#about to read 3, iclass 5, count 0 2006.258.00:04:05.17#ibcon#read 3, iclass 5, count 0 2006.258.00:04:05.17#ibcon#about to read 4, iclass 5, count 0 2006.258.00:04:05.17#ibcon#read 4, iclass 5, count 0 2006.258.00:04:05.17#ibcon#about to read 5, iclass 5, count 0 2006.258.00:04:05.17#ibcon#read 5, iclass 5, count 0 2006.258.00:04:05.17#ibcon#about to read 6, iclass 5, count 0 2006.258.00:04:05.17#ibcon#read 6, iclass 5, count 0 2006.258.00:04:05.17#ibcon#end of sib2, iclass 5, count 0 2006.258.00:04:05.17#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:04:05.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:04:05.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:04:05.17#ibcon#*before write, iclass 5, count 0 2006.258.00:04:05.17#ibcon#enter sib2, iclass 5, count 0 2006.258.00:04:05.17#ibcon#flushed, iclass 5, count 0 2006.258.00:04:05.17#ibcon#about to write, iclass 5, count 0 2006.258.00:04:05.17#ibcon#wrote, iclass 5, count 0 2006.258.00:04:05.17#ibcon#about to read 3, iclass 5, count 0 2006.258.00:04:05.21#ibcon#read 3, iclass 5, count 0 2006.258.00:04:05.21#ibcon#about to read 4, iclass 5, count 0 2006.258.00:04:05.21#ibcon#read 4, iclass 5, count 0 2006.258.00:04:05.21#ibcon#about to read 5, iclass 5, count 0 2006.258.00:04:05.21#ibcon#read 5, iclass 5, count 0 2006.258.00:04:05.21#ibcon#about to read 6, iclass 5, count 0 2006.258.00:04:05.21#ibcon#read 6, iclass 5, count 0 2006.258.00:04:05.21#ibcon#end of sib2, iclass 5, count 0 2006.258.00:04:05.21#ibcon#*after write, iclass 5, count 0 2006.258.00:04:05.21#ibcon#*before return 0, iclass 5, count 0 2006.258.00:04:05.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:05.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:04:05.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:04:05.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:04:05.22$vck44/vb=5,4 2006.258.00:04:05.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.00:04:05.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.00:04:05.22#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:05.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:05.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:05.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:05.26#ibcon#enter wrdev, iclass 7, count 2 2006.258.00:04:05.26#ibcon#first serial, iclass 7, count 2 2006.258.00:04:05.26#ibcon#enter sib2, iclass 7, count 2 2006.258.00:04:05.26#ibcon#flushed, iclass 7, count 2 2006.258.00:04:05.26#ibcon#about to write, iclass 7, count 2 2006.258.00:04:05.26#ibcon#wrote, iclass 7, count 2 2006.258.00:04:05.26#ibcon#about to read 3, iclass 7, count 2 2006.258.00:04:05.28#ibcon#read 3, iclass 7, count 2 2006.258.00:04:05.28#ibcon#about to read 4, iclass 7, count 2 2006.258.00:04:05.28#ibcon#read 4, iclass 7, count 2 2006.258.00:04:05.28#ibcon#about to read 5, iclass 7, count 2 2006.258.00:04:05.28#ibcon#read 5, iclass 7, count 2 2006.258.00:04:05.28#ibcon#about to read 6, iclass 7, count 2 2006.258.00:04:05.28#ibcon#read 6, iclass 7, count 2 2006.258.00:04:05.28#ibcon#end of sib2, iclass 7, count 2 2006.258.00:04:05.28#ibcon#*mode == 0, iclass 7, count 2 2006.258.00:04:05.28#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.00:04:05.28#ibcon#[27=AT05-04\r\n] 2006.258.00:04:05.28#ibcon#*before write, iclass 7, count 2 2006.258.00:04:05.28#ibcon#enter sib2, iclass 7, count 2 2006.258.00:04:05.28#ibcon#flushed, iclass 7, count 2 2006.258.00:04:05.28#ibcon#about to write, iclass 7, count 2 2006.258.00:04:05.28#ibcon#wrote, iclass 7, count 2 2006.258.00:04:05.28#ibcon#about to read 3, iclass 7, count 2 2006.258.00:04:05.31#ibcon#read 3, iclass 7, count 2 2006.258.00:04:05.31#ibcon#about to read 4, iclass 7, count 2 2006.258.00:04:05.31#ibcon#read 4, iclass 7, count 2 2006.258.00:04:05.31#ibcon#about to read 5, iclass 7, count 2 2006.258.00:04:05.31#ibcon#read 5, iclass 7, count 2 2006.258.00:04:05.31#ibcon#about to read 6, iclass 7, count 2 2006.258.00:04:05.31#ibcon#read 6, iclass 7, count 2 2006.258.00:04:05.31#ibcon#end of sib2, iclass 7, count 2 2006.258.00:04:05.31#ibcon#*after write, iclass 7, count 2 2006.258.00:04:05.31#ibcon#*before return 0, iclass 7, count 2 2006.258.00:04:05.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:05.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:04:05.31#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.00:04:05.31#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:05.31#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:05.43#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:05.43#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:05.43#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:04:05.43#ibcon#first serial, iclass 7, count 0 2006.258.00:04:05.43#ibcon#enter sib2, iclass 7, count 0 2006.258.00:04:05.43#ibcon#flushed, iclass 7, count 0 2006.258.00:04:05.43#ibcon#about to write, iclass 7, count 0 2006.258.00:04:05.43#ibcon#wrote, iclass 7, count 0 2006.258.00:04:05.43#ibcon#about to read 3, iclass 7, count 0 2006.258.00:04:05.45#ibcon#read 3, iclass 7, count 0 2006.258.00:04:05.45#ibcon#about to read 4, iclass 7, count 0 2006.258.00:04:05.45#ibcon#read 4, iclass 7, count 0 2006.258.00:04:05.45#ibcon#about to read 5, iclass 7, count 0 2006.258.00:04:05.45#ibcon#read 5, iclass 7, count 0 2006.258.00:04:05.45#ibcon#about to read 6, iclass 7, count 0 2006.258.00:04:05.45#ibcon#read 6, iclass 7, count 0 2006.258.00:04:05.45#ibcon#end of sib2, iclass 7, count 0 2006.258.00:04:05.45#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:04:05.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:04:05.45#ibcon#[27=USB\r\n] 2006.258.00:04:05.45#ibcon#*before write, iclass 7, count 0 2006.258.00:04:05.45#ibcon#enter sib2, iclass 7, count 0 2006.258.00:04:05.45#ibcon#flushed, iclass 7, count 0 2006.258.00:04:05.45#ibcon#about to write, iclass 7, count 0 2006.258.00:04:05.45#ibcon#wrote, iclass 7, count 0 2006.258.00:04:05.45#ibcon#about to read 3, iclass 7, count 0 2006.258.00:04:05.48#ibcon#read 3, iclass 7, count 0 2006.258.00:04:05.48#ibcon#about to read 4, iclass 7, count 0 2006.258.00:04:05.48#ibcon#read 4, iclass 7, count 0 2006.258.00:04:05.48#ibcon#about to read 5, iclass 7, count 0 2006.258.00:04:05.48#ibcon#read 5, iclass 7, count 0 2006.258.00:04:05.48#ibcon#about to read 6, iclass 7, count 0 2006.258.00:04:05.48#ibcon#read 6, iclass 7, count 0 2006.258.00:04:05.48#ibcon#end of sib2, iclass 7, count 0 2006.258.00:04:05.48#ibcon#*after write, iclass 7, count 0 2006.258.00:04:05.48#ibcon#*before return 0, iclass 7, count 0 2006.258.00:04:05.48#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:05.48#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:04:05.48#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:04:05.48#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:04:05.49$vck44/vblo=6,719.99 2006.258.00:04:05.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.00:04:05.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.00:04:05.49#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:05.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:05.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:05.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:05.49#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:04:05.49#ibcon#first serial, iclass 11, count 0 2006.258.00:04:05.49#ibcon#enter sib2, iclass 11, count 0 2006.258.00:04:05.49#ibcon#flushed, iclass 11, count 0 2006.258.00:04:05.49#ibcon#about to write, iclass 11, count 0 2006.258.00:04:05.49#ibcon#wrote, iclass 11, count 0 2006.258.00:04:05.49#ibcon#about to read 3, iclass 11, count 0 2006.258.00:04:05.50#ibcon#read 3, iclass 11, count 0 2006.258.00:04:05.50#ibcon#about to read 4, iclass 11, count 0 2006.258.00:04:05.50#ibcon#read 4, iclass 11, count 0 2006.258.00:04:05.50#ibcon#about to read 5, iclass 11, count 0 2006.258.00:04:05.50#ibcon#read 5, iclass 11, count 0 2006.258.00:04:05.50#ibcon#about to read 6, iclass 11, count 0 2006.258.00:04:05.50#ibcon#read 6, iclass 11, count 0 2006.258.00:04:05.50#ibcon#end of sib2, iclass 11, count 0 2006.258.00:04:05.50#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:04:05.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:04:05.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:04:05.50#ibcon#*before write, iclass 11, count 0 2006.258.00:04:05.50#ibcon#enter sib2, iclass 11, count 0 2006.258.00:04:05.50#ibcon#flushed, iclass 11, count 0 2006.258.00:04:05.50#ibcon#about to write, iclass 11, count 0 2006.258.00:04:05.50#ibcon#wrote, iclass 11, count 0 2006.258.00:04:05.50#ibcon#about to read 3, iclass 11, count 0 2006.258.00:04:05.54#ibcon#read 3, iclass 11, count 0 2006.258.00:04:05.54#ibcon#about to read 4, iclass 11, count 0 2006.258.00:04:05.54#ibcon#read 4, iclass 11, count 0 2006.258.00:04:05.54#ibcon#about to read 5, iclass 11, count 0 2006.258.00:04:05.54#ibcon#read 5, iclass 11, count 0 2006.258.00:04:05.54#ibcon#about to read 6, iclass 11, count 0 2006.258.00:04:05.54#ibcon#read 6, iclass 11, count 0 2006.258.00:04:05.54#ibcon#end of sib2, iclass 11, count 0 2006.258.00:04:05.54#ibcon#*after write, iclass 11, count 0 2006.258.00:04:05.54#ibcon#*before return 0, iclass 11, count 0 2006.258.00:04:05.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:05.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:04:05.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:04:05.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:04:05.55$vck44/vb=6,4 2006.258.00:04:05.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.00:04:05.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.00:04:05.55#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:05.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:05.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:05.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:05.59#ibcon#enter wrdev, iclass 13, count 2 2006.258.00:04:05.59#ibcon#first serial, iclass 13, count 2 2006.258.00:04:05.59#ibcon#enter sib2, iclass 13, count 2 2006.258.00:04:05.59#ibcon#flushed, iclass 13, count 2 2006.258.00:04:05.59#ibcon#about to write, iclass 13, count 2 2006.258.00:04:05.59#ibcon#wrote, iclass 13, count 2 2006.258.00:04:05.59#ibcon#about to read 3, iclass 13, count 2 2006.258.00:04:05.61#ibcon#read 3, iclass 13, count 2 2006.258.00:04:05.61#ibcon#about to read 4, iclass 13, count 2 2006.258.00:04:05.61#ibcon#read 4, iclass 13, count 2 2006.258.00:04:05.61#ibcon#about to read 5, iclass 13, count 2 2006.258.00:04:05.61#ibcon#read 5, iclass 13, count 2 2006.258.00:04:05.61#ibcon#about to read 6, iclass 13, count 2 2006.258.00:04:05.61#ibcon#read 6, iclass 13, count 2 2006.258.00:04:05.61#ibcon#end of sib2, iclass 13, count 2 2006.258.00:04:05.61#ibcon#*mode == 0, iclass 13, count 2 2006.258.00:04:05.61#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.00:04:05.61#ibcon#[27=AT06-04\r\n] 2006.258.00:04:05.61#ibcon#*before write, iclass 13, count 2 2006.258.00:04:05.61#ibcon#enter sib2, iclass 13, count 2 2006.258.00:04:05.61#ibcon#flushed, iclass 13, count 2 2006.258.00:04:05.61#ibcon#about to write, iclass 13, count 2 2006.258.00:04:05.61#ibcon#wrote, iclass 13, count 2 2006.258.00:04:05.61#ibcon#about to read 3, iclass 13, count 2 2006.258.00:04:05.64#ibcon#read 3, iclass 13, count 2 2006.258.00:04:05.64#ibcon#about to read 4, iclass 13, count 2 2006.258.00:04:05.64#ibcon#read 4, iclass 13, count 2 2006.258.00:04:05.64#ibcon#about to read 5, iclass 13, count 2 2006.258.00:04:05.64#ibcon#read 5, iclass 13, count 2 2006.258.00:04:05.64#ibcon#about to read 6, iclass 13, count 2 2006.258.00:04:05.64#ibcon#read 6, iclass 13, count 2 2006.258.00:04:05.64#ibcon#end of sib2, iclass 13, count 2 2006.258.00:04:05.64#ibcon#*after write, iclass 13, count 2 2006.258.00:04:05.64#ibcon#*before return 0, iclass 13, count 2 2006.258.00:04:05.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:05.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:04:05.64#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.00:04:05.64#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:05.64#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:05.76#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:05.76#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:05.76#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:04:05.76#ibcon#first serial, iclass 13, count 0 2006.258.00:04:05.76#ibcon#enter sib2, iclass 13, count 0 2006.258.00:04:05.76#ibcon#flushed, iclass 13, count 0 2006.258.00:04:05.76#ibcon#about to write, iclass 13, count 0 2006.258.00:04:05.76#ibcon#wrote, iclass 13, count 0 2006.258.00:04:05.76#ibcon#about to read 3, iclass 13, count 0 2006.258.00:04:05.78#ibcon#read 3, iclass 13, count 0 2006.258.00:04:05.78#ibcon#about to read 4, iclass 13, count 0 2006.258.00:04:05.78#ibcon#read 4, iclass 13, count 0 2006.258.00:04:05.78#ibcon#about to read 5, iclass 13, count 0 2006.258.00:04:05.78#ibcon#read 5, iclass 13, count 0 2006.258.00:04:05.78#ibcon#about to read 6, iclass 13, count 0 2006.258.00:04:05.78#ibcon#read 6, iclass 13, count 0 2006.258.00:04:05.78#ibcon#end of sib2, iclass 13, count 0 2006.258.00:04:05.78#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:04:05.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:04:05.78#ibcon#[27=USB\r\n] 2006.258.00:04:05.78#ibcon#*before write, iclass 13, count 0 2006.258.00:04:05.78#ibcon#enter sib2, iclass 13, count 0 2006.258.00:04:05.78#ibcon#flushed, iclass 13, count 0 2006.258.00:04:05.78#ibcon#about to write, iclass 13, count 0 2006.258.00:04:05.78#ibcon#wrote, iclass 13, count 0 2006.258.00:04:05.78#ibcon#about to read 3, iclass 13, count 0 2006.258.00:04:05.81#ibcon#read 3, iclass 13, count 0 2006.258.00:04:05.81#ibcon#about to read 4, iclass 13, count 0 2006.258.00:04:05.81#ibcon#read 4, iclass 13, count 0 2006.258.00:04:05.81#ibcon#about to read 5, iclass 13, count 0 2006.258.00:04:05.81#ibcon#read 5, iclass 13, count 0 2006.258.00:04:05.81#ibcon#about to read 6, iclass 13, count 0 2006.258.00:04:05.81#ibcon#read 6, iclass 13, count 0 2006.258.00:04:05.81#ibcon#end of sib2, iclass 13, count 0 2006.258.00:04:05.81#ibcon#*after write, iclass 13, count 0 2006.258.00:04:05.81#ibcon#*before return 0, iclass 13, count 0 2006.258.00:04:05.81#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:05.81#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:04:05.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:04:05.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:04:05.82$vck44/vblo=7,734.99 2006.258.00:04:05.82#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.00:04:05.82#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.00:04:05.82#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:05.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:05.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:05.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:05.82#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:04:05.82#ibcon#first serial, iclass 15, count 0 2006.258.00:04:05.82#ibcon#enter sib2, iclass 15, count 0 2006.258.00:04:05.82#ibcon#flushed, iclass 15, count 0 2006.258.00:04:05.82#ibcon#about to write, iclass 15, count 0 2006.258.00:04:05.82#ibcon#wrote, iclass 15, count 0 2006.258.00:04:05.82#ibcon#about to read 3, iclass 15, count 0 2006.258.00:04:05.83#ibcon#read 3, iclass 15, count 0 2006.258.00:04:05.83#ibcon#about to read 4, iclass 15, count 0 2006.258.00:04:05.83#ibcon#read 4, iclass 15, count 0 2006.258.00:04:05.83#ibcon#about to read 5, iclass 15, count 0 2006.258.00:04:05.83#ibcon#read 5, iclass 15, count 0 2006.258.00:04:05.83#ibcon#about to read 6, iclass 15, count 0 2006.258.00:04:05.83#ibcon#read 6, iclass 15, count 0 2006.258.00:04:05.83#ibcon#end of sib2, iclass 15, count 0 2006.258.00:04:05.83#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:04:05.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:04:05.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:04:05.83#ibcon#*before write, iclass 15, count 0 2006.258.00:04:05.83#ibcon#enter sib2, iclass 15, count 0 2006.258.00:04:05.83#ibcon#flushed, iclass 15, count 0 2006.258.00:04:05.83#ibcon#about to write, iclass 15, count 0 2006.258.00:04:05.83#ibcon#wrote, iclass 15, count 0 2006.258.00:04:05.83#ibcon#about to read 3, iclass 15, count 0 2006.258.00:04:05.87#ibcon#read 3, iclass 15, count 0 2006.258.00:04:05.87#ibcon#about to read 4, iclass 15, count 0 2006.258.00:04:05.87#ibcon#read 4, iclass 15, count 0 2006.258.00:04:05.87#ibcon#about to read 5, iclass 15, count 0 2006.258.00:04:05.87#ibcon#read 5, iclass 15, count 0 2006.258.00:04:05.87#ibcon#about to read 6, iclass 15, count 0 2006.258.00:04:05.87#ibcon#read 6, iclass 15, count 0 2006.258.00:04:05.87#ibcon#end of sib2, iclass 15, count 0 2006.258.00:04:05.87#ibcon#*after write, iclass 15, count 0 2006.258.00:04:05.87#ibcon#*before return 0, iclass 15, count 0 2006.258.00:04:05.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:05.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:04:05.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:04:05.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:04:05.88$vck44/vb=7,4 2006.258.00:04:05.88#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.00:04:05.88#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.00:04:05.88#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:05.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:05.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:05.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:05.92#ibcon#enter wrdev, iclass 17, count 2 2006.258.00:04:05.92#ibcon#first serial, iclass 17, count 2 2006.258.00:04:05.92#ibcon#enter sib2, iclass 17, count 2 2006.258.00:04:05.92#ibcon#flushed, iclass 17, count 2 2006.258.00:04:05.92#ibcon#about to write, iclass 17, count 2 2006.258.00:04:05.92#ibcon#wrote, iclass 17, count 2 2006.258.00:04:05.92#ibcon#about to read 3, iclass 17, count 2 2006.258.00:04:05.94#ibcon#read 3, iclass 17, count 2 2006.258.00:04:05.94#ibcon#about to read 4, iclass 17, count 2 2006.258.00:04:05.94#ibcon#read 4, iclass 17, count 2 2006.258.00:04:05.94#ibcon#about to read 5, iclass 17, count 2 2006.258.00:04:05.94#ibcon#read 5, iclass 17, count 2 2006.258.00:04:05.94#ibcon#about to read 6, iclass 17, count 2 2006.258.00:04:05.94#ibcon#read 6, iclass 17, count 2 2006.258.00:04:05.94#ibcon#end of sib2, iclass 17, count 2 2006.258.00:04:05.94#ibcon#*mode == 0, iclass 17, count 2 2006.258.00:04:05.94#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.00:04:05.94#ibcon#[27=AT07-04\r\n] 2006.258.00:04:05.94#ibcon#*before write, iclass 17, count 2 2006.258.00:04:05.94#ibcon#enter sib2, iclass 17, count 2 2006.258.00:04:05.94#ibcon#flushed, iclass 17, count 2 2006.258.00:04:05.94#ibcon#about to write, iclass 17, count 2 2006.258.00:04:05.94#ibcon#wrote, iclass 17, count 2 2006.258.00:04:05.94#ibcon#about to read 3, iclass 17, count 2 2006.258.00:04:05.97#ibcon#read 3, iclass 17, count 2 2006.258.00:04:05.97#ibcon#about to read 4, iclass 17, count 2 2006.258.00:04:05.97#ibcon#read 4, iclass 17, count 2 2006.258.00:04:05.97#ibcon#about to read 5, iclass 17, count 2 2006.258.00:04:05.97#ibcon#read 5, iclass 17, count 2 2006.258.00:04:05.97#ibcon#about to read 6, iclass 17, count 2 2006.258.00:04:05.97#ibcon#read 6, iclass 17, count 2 2006.258.00:04:05.97#ibcon#end of sib2, iclass 17, count 2 2006.258.00:04:05.97#ibcon#*after write, iclass 17, count 2 2006.258.00:04:05.97#ibcon#*before return 0, iclass 17, count 2 2006.258.00:04:05.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:05.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:04:05.97#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.00:04:05.97#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:05.97#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:06.09#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:06.09#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:06.09#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:04:06.09#ibcon#first serial, iclass 17, count 0 2006.258.00:04:06.09#ibcon#enter sib2, iclass 17, count 0 2006.258.00:04:06.09#ibcon#flushed, iclass 17, count 0 2006.258.00:04:06.09#ibcon#about to write, iclass 17, count 0 2006.258.00:04:06.09#ibcon#wrote, iclass 17, count 0 2006.258.00:04:06.09#ibcon#about to read 3, iclass 17, count 0 2006.258.00:04:06.11#ibcon#read 3, iclass 17, count 0 2006.258.00:04:06.11#ibcon#about to read 4, iclass 17, count 0 2006.258.00:04:06.11#ibcon#read 4, iclass 17, count 0 2006.258.00:04:06.11#ibcon#about to read 5, iclass 17, count 0 2006.258.00:04:06.11#ibcon#read 5, iclass 17, count 0 2006.258.00:04:06.11#ibcon#about to read 6, iclass 17, count 0 2006.258.00:04:06.11#ibcon#read 6, iclass 17, count 0 2006.258.00:04:06.11#ibcon#end of sib2, iclass 17, count 0 2006.258.00:04:06.11#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:04:06.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:04:06.11#ibcon#[27=USB\r\n] 2006.258.00:04:06.11#ibcon#*before write, iclass 17, count 0 2006.258.00:04:06.11#ibcon#enter sib2, iclass 17, count 0 2006.258.00:04:06.11#ibcon#flushed, iclass 17, count 0 2006.258.00:04:06.11#ibcon#about to write, iclass 17, count 0 2006.258.00:04:06.11#ibcon#wrote, iclass 17, count 0 2006.258.00:04:06.11#ibcon#about to read 3, iclass 17, count 0 2006.258.00:04:06.15#ibcon#read 3, iclass 17, count 0 2006.258.00:04:06.15#ibcon#about to read 4, iclass 17, count 0 2006.258.00:04:06.15#ibcon#read 4, iclass 17, count 0 2006.258.00:04:06.15#ibcon#about to read 5, iclass 17, count 0 2006.258.00:04:06.15#ibcon#read 5, iclass 17, count 0 2006.258.00:04:06.15#ibcon#about to read 6, iclass 17, count 0 2006.258.00:04:06.15#ibcon#read 6, iclass 17, count 0 2006.258.00:04:06.15#ibcon#end of sib2, iclass 17, count 0 2006.258.00:04:06.15#ibcon#*after write, iclass 17, count 0 2006.258.00:04:06.15#ibcon#*before return 0, iclass 17, count 0 2006.258.00:04:06.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:06.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:04:06.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:04:06.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:04:06.15$vck44/vblo=8,744.99 2006.258.00:04:06.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.00:04:06.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.00:04:06.15#ibcon#ireg 17 cls_cnt 0 2006.258.00:04:06.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:06.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:06.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:06.15#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:04:06.15#ibcon#first serial, iclass 19, count 0 2006.258.00:04:06.15#ibcon#enter sib2, iclass 19, count 0 2006.258.00:04:06.15#ibcon#flushed, iclass 19, count 0 2006.258.00:04:06.15#ibcon#about to write, iclass 19, count 0 2006.258.00:04:06.15#ibcon#wrote, iclass 19, count 0 2006.258.00:04:06.15#ibcon#about to read 3, iclass 19, count 0 2006.258.00:04:06.16#ibcon#read 3, iclass 19, count 0 2006.258.00:04:06.16#ibcon#about to read 4, iclass 19, count 0 2006.258.00:04:06.16#ibcon#read 4, iclass 19, count 0 2006.258.00:04:06.16#ibcon#about to read 5, iclass 19, count 0 2006.258.00:04:06.16#ibcon#read 5, iclass 19, count 0 2006.258.00:04:06.16#ibcon#about to read 6, iclass 19, count 0 2006.258.00:04:06.16#ibcon#read 6, iclass 19, count 0 2006.258.00:04:06.16#ibcon#end of sib2, iclass 19, count 0 2006.258.00:04:06.16#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:04:06.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:04:06.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:04:06.16#ibcon#*before write, iclass 19, count 0 2006.258.00:04:06.16#ibcon#enter sib2, iclass 19, count 0 2006.258.00:04:06.16#ibcon#flushed, iclass 19, count 0 2006.258.00:04:06.16#ibcon#about to write, iclass 19, count 0 2006.258.00:04:06.16#ibcon#wrote, iclass 19, count 0 2006.258.00:04:06.16#ibcon#about to read 3, iclass 19, count 0 2006.258.00:04:06.20#ibcon#read 3, iclass 19, count 0 2006.258.00:04:06.20#ibcon#about to read 4, iclass 19, count 0 2006.258.00:04:06.20#ibcon#read 4, iclass 19, count 0 2006.258.00:04:06.20#ibcon#about to read 5, iclass 19, count 0 2006.258.00:04:06.20#ibcon#read 5, iclass 19, count 0 2006.258.00:04:06.20#ibcon#about to read 6, iclass 19, count 0 2006.258.00:04:06.20#ibcon#read 6, iclass 19, count 0 2006.258.00:04:06.20#ibcon#end of sib2, iclass 19, count 0 2006.258.00:04:06.20#ibcon#*after write, iclass 19, count 0 2006.258.00:04:06.20#ibcon#*before return 0, iclass 19, count 0 2006.258.00:04:06.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:06.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:04:06.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:04:06.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:04:06.21$vck44/vb=8,4 2006.258.00:04:06.21#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.00:04:06.21#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.00:04:06.21#ibcon#ireg 11 cls_cnt 2 2006.258.00:04:06.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:06.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:06.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:06.26#ibcon#enter wrdev, iclass 21, count 2 2006.258.00:04:06.26#ibcon#first serial, iclass 21, count 2 2006.258.00:04:06.26#ibcon#enter sib2, iclass 21, count 2 2006.258.00:04:06.26#ibcon#flushed, iclass 21, count 2 2006.258.00:04:06.26#ibcon#about to write, iclass 21, count 2 2006.258.00:04:06.26#ibcon#wrote, iclass 21, count 2 2006.258.00:04:06.26#ibcon#about to read 3, iclass 21, count 2 2006.258.00:04:06.28#ibcon#read 3, iclass 21, count 2 2006.258.00:04:06.28#ibcon#about to read 4, iclass 21, count 2 2006.258.00:04:06.28#ibcon#read 4, iclass 21, count 2 2006.258.00:04:06.28#ibcon#about to read 5, iclass 21, count 2 2006.258.00:04:06.28#ibcon#read 5, iclass 21, count 2 2006.258.00:04:06.28#ibcon#about to read 6, iclass 21, count 2 2006.258.00:04:06.28#ibcon#read 6, iclass 21, count 2 2006.258.00:04:06.28#ibcon#end of sib2, iclass 21, count 2 2006.258.00:04:06.28#ibcon#*mode == 0, iclass 21, count 2 2006.258.00:04:06.28#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.00:04:06.28#ibcon#[27=AT08-04\r\n] 2006.258.00:04:06.28#ibcon#*before write, iclass 21, count 2 2006.258.00:04:06.28#ibcon#enter sib2, iclass 21, count 2 2006.258.00:04:06.28#ibcon#flushed, iclass 21, count 2 2006.258.00:04:06.28#ibcon#about to write, iclass 21, count 2 2006.258.00:04:06.28#ibcon#wrote, iclass 21, count 2 2006.258.00:04:06.28#ibcon#about to read 3, iclass 21, count 2 2006.258.00:04:06.31#ibcon#read 3, iclass 21, count 2 2006.258.00:04:06.31#ibcon#about to read 4, iclass 21, count 2 2006.258.00:04:06.31#ibcon#read 4, iclass 21, count 2 2006.258.00:04:06.31#ibcon#about to read 5, iclass 21, count 2 2006.258.00:04:06.31#ibcon#read 5, iclass 21, count 2 2006.258.00:04:06.31#ibcon#about to read 6, iclass 21, count 2 2006.258.00:04:06.31#ibcon#read 6, iclass 21, count 2 2006.258.00:04:06.31#ibcon#end of sib2, iclass 21, count 2 2006.258.00:04:06.31#ibcon#*after write, iclass 21, count 2 2006.258.00:04:06.31#ibcon#*before return 0, iclass 21, count 2 2006.258.00:04:06.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:06.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:04:06.31#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.00:04:06.31#ibcon#ireg 7 cls_cnt 0 2006.258.00:04:06.31#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:06.43#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:06.43#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:06.43#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:04:06.43#ibcon#first serial, iclass 21, count 0 2006.258.00:04:06.43#ibcon#enter sib2, iclass 21, count 0 2006.258.00:04:06.43#ibcon#flushed, iclass 21, count 0 2006.258.00:04:06.43#ibcon#about to write, iclass 21, count 0 2006.258.00:04:06.43#ibcon#wrote, iclass 21, count 0 2006.258.00:04:06.43#ibcon#about to read 3, iclass 21, count 0 2006.258.00:04:06.45#ibcon#read 3, iclass 21, count 0 2006.258.00:04:06.45#ibcon#about to read 4, iclass 21, count 0 2006.258.00:04:06.45#ibcon#read 4, iclass 21, count 0 2006.258.00:04:06.45#ibcon#about to read 5, iclass 21, count 0 2006.258.00:04:06.45#ibcon#read 5, iclass 21, count 0 2006.258.00:04:06.45#ibcon#about to read 6, iclass 21, count 0 2006.258.00:04:06.45#ibcon#read 6, iclass 21, count 0 2006.258.00:04:06.45#ibcon#end of sib2, iclass 21, count 0 2006.258.00:04:06.45#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:04:06.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:04:06.45#ibcon#[27=USB\r\n] 2006.258.00:04:06.45#ibcon#*before write, iclass 21, count 0 2006.258.00:04:06.45#ibcon#enter sib2, iclass 21, count 0 2006.258.00:04:06.45#ibcon#flushed, iclass 21, count 0 2006.258.00:04:06.45#ibcon#about to write, iclass 21, count 0 2006.258.00:04:06.45#ibcon#wrote, iclass 21, count 0 2006.258.00:04:06.45#ibcon#about to read 3, iclass 21, count 0 2006.258.00:04:06.48#ibcon#read 3, iclass 21, count 0 2006.258.00:04:06.48#ibcon#about to read 4, iclass 21, count 0 2006.258.00:04:06.48#ibcon#read 4, iclass 21, count 0 2006.258.00:04:06.48#ibcon#about to read 5, iclass 21, count 0 2006.258.00:04:06.48#ibcon#read 5, iclass 21, count 0 2006.258.00:04:06.48#ibcon#about to read 6, iclass 21, count 0 2006.258.00:04:06.48#ibcon#read 6, iclass 21, count 0 2006.258.00:04:06.48#ibcon#end of sib2, iclass 21, count 0 2006.258.00:04:06.48#ibcon#*after write, iclass 21, count 0 2006.258.00:04:06.48#ibcon#*before return 0, iclass 21, count 0 2006.258.00:04:06.48#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:06.48#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:04:06.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:04:06.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:04:06.49$vck44/vabw=wide 2006.258.00:04:06.49#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.00:04:06.49#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.00:04:06.49#ibcon#ireg 8 cls_cnt 0 2006.258.00:04:06.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:06.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:06.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:06.49#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:04:06.49#ibcon#first serial, iclass 23, count 0 2006.258.00:04:06.49#ibcon#enter sib2, iclass 23, count 0 2006.258.00:04:06.49#ibcon#flushed, iclass 23, count 0 2006.258.00:04:06.49#ibcon#about to write, iclass 23, count 0 2006.258.00:04:06.49#ibcon#wrote, iclass 23, count 0 2006.258.00:04:06.49#ibcon#about to read 3, iclass 23, count 0 2006.258.00:04:06.50#ibcon#read 3, iclass 23, count 0 2006.258.00:04:06.50#ibcon#about to read 4, iclass 23, count 0 2006.258.00:04:06.50#ibcon#read 4, iclass 23, count 0 2006.258.00:04:06.50#ibcon#about to read 5, iclass 23, count 0 2006.258.00:04:06.50#ibcon#read 5, iclass 23, count 0 2006.258.00:04:06.50#ibcon#about to read 6, iclass 23, count 0 2006.258.00:04:06.50#ibcon#read 6, iclass 23, count 0 2006.258.00:04:06.50#ibcon#end of sib2, iclass 23, count 0 2006.258.00:04:06.50#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:04:06.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:04:06.50#ibcon#[25=BW32\r\n] 2006.258.00:04:06.50#ibcon#*before write, iclass 23, count 0 2006.258.00:04:06.50#ibcon#enter sib2, iclass 23, count 0 2006.258.00:04:06.50#ibcon#flushed, iclass 23, count 0 2006.258.00:04:06.50#ibcon#about to write, iclass 23, count 0 2006.258.00:04:06.50#ibcon#wrote, iclass 23, count 0 2006.258.00:04:06.50#ibcon#about to read 3, iclass 23, count 0 2006.258.00:04:06.53#ibcon#read 3, iclass 23, count 0 2006.258.00:04:06.53#ibcon#about to read 4, iclass 23, count 0 2006.258.00:04:06.53#ibcon#read 4, iclass 23, count 0 2006.258.00:04:06.53#ibcon#about to read 5, iclass 23, count 0 2006.258.00:04:06.53#ibcon#read 5, iclass 23, count 0 2006.258.00:04:06.53#ibcon#about to read 6, iclass 23, count 0 2006.258.00:04:06.53#ibcon#read 6, iclass 23, count 0 2006.258.00:04:06.53#ibcon#end of sib2, iclass 23, count 0 2006.258.00:04:06.53#ibcon#*after write, iclass 23, count 0 2006.258.00:04:06.53#ibcon#*before return 0, iclass 23, count 0 2006.258.00:04:06.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:06.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:04:06.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:04:06.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:04:06.54$vck44/vbbw=wide 2006.258.00:04:06.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.00:04:06.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.00:04:06.54#ibcon#ireg 8 cls_cnt 0 2006.258.00:04:06.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:04:06.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:04:06.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:04:06.59#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:04:06.59#ibcon#first serial, iclass 25, count 0 2006.258.00:04:06.59#ibcon#enter sib2, iclass 25, count 0 2006.258.00:04:06.59#ibcon#flushed, iclass 25, count 0 2006.258.00:04:06.59#ibcon#about to write, iclass 25, count 0 2006.258.00:04:06.59#ibcon#wrote, iclass 25, count 0 2006.258.00:04:06.59#ibcon#about to read 3, iclass 25, count 0 2006.258.00:04:06.61#ibcon#read 3, iclass 25, count 0 2006.258.00:04:06.61#ibcon#about to read 4, iclass 25, count 0 2006.258.00:04:06.61#ibcon#read 4, iclass 25, count 0 2006.258.00:04:06.61#ibcon#about to read 5, iclass 25, count 0 2006.258.00:04:06.61#ibcon#read 5, iclass 25, count 0 2006.258.00:04:06.61#ibcon#about to read 6, iclass 25, count 0 2006.258.00:04:06.61#ibcon#read 6, iclass 25, count 0 2006.258.00:04:06.61#ibcon#end of sib2, iclass 25, count 0 2006.258.00:04:06.61#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:04:06.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:04:06.61#ibcon#[27=BW32\r\n] 2006.258.00:04:06.61#ibcon#*before write, iclass 25, count 0 2006.258.00:04:06.61#ibcon#enter sib2, iclass 25, count 0 2006.258.00:04:06.61#ibcon#flushed, iclass 25, count 0 2006.258.00:04:06.61#ibcon#about to write, iclass 25, count 0 2006.258.00:04:06.61#ibcon#wrote, iclass 25, count 0 2006.258.00:04:06.61#ibcon#about to read 3, iclass 25, count 0 2006.258.00:04:06.70#ibcon#read 3, iclass 25, count 0 2006.258.00:04:06.70#ibcon#about to read 4, iclass 25, count 0 2006.258.00:04:06.70#ibcon#read 4, iclass 25, count 0 2006.258.00:04:06.70#ibcon#about to read 5, iclass 25, count 0 2006.258.00:04:06.70#ibcon#read 5, iclass 25, count 0 2006.258.00:04:06.70#ibcon#about to read 6, iclass 25, count 0 2006.258.00:04:06.70#ibcon#read 6, iclass 25, count 0 2006.258.00:04:06.70#ibcon#end of sib2, iclass 25, count 0 2006.258.00:04:06.70#ibcon#*after write, iclass 25, count 0 2006.258.00:04:06.70#ibcon#*before return 0, iclass 25, count 0 2006.258.00:04:06.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:04:06.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:04:06.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:04:06.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:04:06.70$setupk4/ifdk4 2006.258.00:04:06.70$ifdk4/lo= 2006.258.00:04:06.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:04:06.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:04:06.71$ifdk4/patch= 2006.258.00:04:06.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:04:06.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:04:06.71$setupk4/!*+20s 2006.258.00:04:14.54#abcon#<5=/16 1.4 3.9 21.52 761016.2\r\n> 2006.258.00:04:14.56#abcon#{5=INTERFACE CLEAR} 2006.258.00:04:14.62#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:04:18.14#trakl#Source acquired 2006.258.00:04:20.15#flagr#flagr/antenna,acquired 2006.258.00:04:21.27$setupk4/"tpicd 2006.258.00:04:21.27$setupk4/echo=off 2006.258.00:04:21.27$setupk4/xlog=off 2006.258.00:04:21.27:!2006.258.00:04:43 2006.258.00:04:43.02:preob 2006.258.00:04:44.15/onsource/TRACKING 2006.258.00:04:44.15:!2006.258.00:04:53 2006.258.00:04:53.02:"tape 2006.258.00:04:53.02:"st=record 2006.258.00:04:53.02:data_valid=on 2006.258.00:04:53.02:midob 2006.258.00:04:54.15/onsource/TRACKING 2006.258.00:04:54.15/wx/21.54,1016.2,76 2006.258.00:04:54.31/cable/+6.4811E-03 2006.258.00:04:55.40/va/01,08,usb,yes,31,34 2006.258.00:04:55.40/va/02,07,usb,yes,34,35 2006.258.00:04:55.40/va/03,08,usb,yes,30,32 2006.258.00:04:55.40/va/04,07,usb,yes,35,37 2006.258.00:04:55.40/va/05,04,usb,yes,31,32 2006.258.00:04:55.40/va/06,04,usb,yes,35,34 2006.258.00:04:55.40/va/07,04,usb,yes,36,36 2006.258.00:04:55.40/va/08,04,usb,yes,30,37 2006.258.00:04:55.63/valo/01,524.99,yes,locked 2006.258.00:04:55.63/valo/02,534.99,yes,locked 2006.258.00:04:55.63/valo/03,564.99,yes,locked 2006.258.00:04:55.63/valo/04,624.99,yes,locked 2006.258.00:04:55.63/valo/05,734.99,yes,locked 2006.258.00:04:55.63/valo/06,814.99,yes,locked 2006.258.00:04:55.63/valo/07,864.99,yes,locked 2006.258.00:04:55.63/valo/08,884.99,yes,locked 2006.258.00:04:56.72/vb/01,04,usb,yes,30,33 2006.258.00:04:56.72/vb/02,05,usb,yes,29,33 2006.258.00:04:56.72/vb/03,04,usb,yes,30,34 2006.258.00:04:56.72/vb/04,05,usb,yes,30,29 2006.258.00:04:56.72/vb/05,04,usb,yes,27,29 2006.258.00:04:56.72/vb/06,04,usb,yes,31,28 2006.258.00:04:56.72/vb/07,04,usb,yes,31,31 2006.258.00:04:56.72/vb/08,04,usb,yes,28,32 2006.258.00:04:56.96/vblo/01,629.99,yes,locked 2006.258.00:04:56.96/vblo/02,634.99,yes,locked 2006.258.00:04:56.96/vblo/03,649.99,yes,locked 2006.258.00:04:56.96/vblo/04,679.99,yes,locked 2006.258.00:04:56.96/vblo/05,709.99,yes,locked 2006.258.00:04:56.96/vblo/06,719.99,yes,locked 2006.258.00:04:56.96/vblo/07,734.99,yes,locked 2006.258.00:04:56.96/vblo/08,744.99,yes,locked 2006.258.00:04:57.11/vabw/8 2006.258.00:04:57.26/vbbw/8 2006.258.00:04:57.35/xfe/off,on,15.0 2006.258.00:04:57.72/ifatt/23,28,28,28 2006.258.00:04:58.06/fmout-gps/S +4.55E-07 2006.258.00:04:58.11:!2006.258.00:09:13 2006.258.00:09:13.01:data_valid=off 2006.258.00:09:13.02:"et 2006.258.00:09:13.02:!+3s 2006.258.00:09:16.03:"tape 2006.258.00:09:16.03:postob 2006.258.00:09:16.12/cable/+6.4823E-03 2006.258.00:09:16.12/wx/21.70,1016.3,79 2006.258.00:09:16.18/fmout-gps/S +4.56E-07 2006.258.00:09:16.18:scan_name=258-0010,jd0609,110 2006.258.00:09:16.18:source=1611+343,161341.06,341247.9,2000.0,cw 2006.258.00:09:18.14#flagr#flagr/antenna,new-source 2006.258.00:09:18.14:checkk5 2006.258.00:09:18.55/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:09:18.96/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:09:19.38/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:09:19.78/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:09:20.18/chk_obsdata//k5ts1/T2580004??a.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.258.00:09:20.59/chk_obsdata//k5ts2/T2580004??b.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.258.00:09:20.99/chk_obsdata//k5ts3/T2580004??c.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.258.00:09:21.41/chk_obsdata//k5ts4/T2580004??d.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.258.00:09:22.13/k5log//k5ts1_log_newline 2006.258.00:09:22.86/k5log//k5ts2_log_newline 2006.258.00:09:23.57/k5log//k5ts3_log_newline 2006.258.00:09:24.29/k5log//k5ts4_log_newline 2006.258.00:09:24.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:09:24.31:setupk4=1 2006.258.00:09:24.31$setupk4/echo=on 2006.258.00:09:24.31$setupk4/pcalon 2006.258.00:09:24.31$pcalon/"no phase cal control is implemented here 2006.258.00:09:24.31$setupk4/"tpicd=stop 2006.258.00:09:24.31$setupk4/"rec=synch_on 2006.258.00:09:24.31$setupk4/"rec_mode=128 2006.258.00:09:24.31$setupk4/!* 2006.258.00:09:24.31$setupk4/recpk4 2006.258.00:09:24.31$recpk4/recpatch= 2006.258.00:09:24.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:09:24.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:09:24.32$setupk4/vck44 2006.258.00:09:24.32$vck44/valo=1,524.99 2006.258.00:09:24.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.258.00:09:24.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.258.00:09:24.32#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:24.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:24.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:24.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:24.32#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:09:24.32#ibcon#first serial, iclass 10, count 0 2006.258.00:09:24.32#ibcon#enter sib2, iclass 10, count 0 2006.258.00:09:24.32#ibcon#flushed, iclass 10, count 0 2006.258.00:09:24.32#ibcon#about to write, iclass 10, count 0 2006.258.00:09:24.32#ibcon#wrote, iclass 10, count 0 2006.258.00:09:24.32#ibcon#about to read 3, iclass 10, count 0 2006.258.00:09:24.33#ibcon#read 3, iclass 10, count 0 2006.258.00:09:24.33#ibcon#about to read 4, iclass 10, count 0 2006.258.00:09:24.33#ibcon#read 4, iclass 10, count 0 2006.258.00:09:24.33#ibcon#about to read 5, iclass 10, count 0 2006.258.00:09:24.33#ibcon#read 5, iclass 10, count 0 2006.258.00:09:24.33#ibcon#about to read 6, iclass 10, count 0 2006.258.00:09:24.33#ibcon#read 6, iclass 10, count 0 2006.258.00:09:24.33#ibcon#end of sib2, iclass 10, count 0 2006.258.00:09:24.33#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:09:24.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:09:24.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:09:24.33#ibcon#*before write, iclass 10, count 0 2006.258.00:09:24.33#ibcon#enter sib2, iclass 10, count 0 2006.258.00:09:24.33#ibcon#flushed, iclass 10, count 0 2006.258.00:09:24.33#ibcon#about to write, iclass 10, count 0 2006.258.00:09:24.33#ibcon#wrote, iclass 10, count 0 2006.258.00:09:24.33#ibcon#about to read 3, iclass 10, count 0 2006.258.00:09:24.38#ibcon#read 3, iclass 10, count 0 2006.258.00:09:24.38#ibcon#about to read 4, iclass 10, count 0 2006.258.00:09:24.38#ibcon#read 4, iclass 10, count 0 2006.258.00:09:24.38#ibcon#about to read 5, iclass 10, count 0 2006.258.00:09:24.38#ibcon#read 5, iclass 10, count 0 2006.258.00:09:24.38#ibcon#about to read 6, iclass 10, count 0 2006.258.00:09:24.38#ibcon#read 6, iclass 10, count 0 2006.258.00:09:24.38#ibcon#end of sib2, iclass 10, count 0 2006.258.00:09:24.38#ibcon#*after write, iclass 10, count 0 2006.258.00:09:24.38#ibcon#*before return 0, iclass 10, count 0 2006.258.00:09:24.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:24.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:24.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:09:24.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:09:24.38$vck44/va=1,8 2006.258.00:09:24.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.258.00:09:24.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.258.00:09:24.38#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:24.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:24.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:24.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:24.38#ibcon#enter wrdev, iclass 12, count 2 2006.258.00:09:24.38#ibcon#first serial, iclass 12, count 2 2006.258.00:09:24.38#ibcon#enter sib2, iclass 12, count 2 2006.258.00:09:24.38#ibcon#flushed, iclass 12, count 2 2006.258.00:09:24.38#ibcon#about to write, iclass 12, count 2 2006.258.00:09:24.38#ibcon#wrote, iclass 12, count 2 2006.258.00:09:24.38#ibcon#about to read 3, iclass 12, count 2 2006.258.00:09:24.40#ibcon#read 3, iclass 12, count 2 2006.258.00:09:24.40#ibcon#about to read 4, iclass 12, count 2 2006.258.00:09:24.40#ibcon#read 4, iclass 12, count 2 2006.258.00:09:24.40#ibcon#about to read 5, iclass 12, count 2 2006.258.00:09:24.40#ibcon#read 5, iclass 12, count 2 2006.258.00:09:24.40#ibcon#about to read 6, iclass 12, count 2 2006.258.00:09:24.40#ibcon#read 6, iclass 12, count 2 2006.258.00:09:24.40#ibcon#end of sib2, iclass 12, count 2 2006.258.00:09:24.40#ibcon#*mode == 0, iclass 12, count 2 2006.258.00:09:24.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.258.00:09:24.40#ibcon#[25=AT01-08\r\n] 2006.258.00:09:24.40#ibcon#*before write, iclass 12, count 2 2006.258.00:09:24.40#ibcon#enter sib2, iclass 12, count 2 2006.258.00:09:24.40#ibcon#flushed, iclass 12, count 2 2006.258.00:09:24.40#ibcon#about to write, iclass 12, count 2 2006.258.00:09:24.40#ibcon#wrote, iclass 12, count 2 2006.258.00:09:24.40#ibcon#about to read 3, iclass 12, count 2 2006.258.00:09:24.43#ibcon#read 3, iclass 12, count 2 2006.258.00:09:24.43#ibcon#about to read 4, iclass 12, count 2 2006.258.00:09:24.43#ibcon#read 4, iclass 12, count 2 2006.258.00:09:24.43#ibcon#about to read 5, iclass 12, count 2 2006.258.00:09:24.43#ibcon#read 5, iclass 12, count 2 2006.258.00:09:24.43#ibcon#about to read 6, iclass 12, count 2 2006.258.00:09:24.43#ibcon#read 6, iclass 12, count 2 2006.258.00:09:24.43#ibcon#end of sib2, iclass 12, count 2 2006.258.00:09:24.43#ibcon#*after write, iclass 12, count 2 2006.258.00:09:24.43#ibcon#*before return 0, iclass 12, count 2 2006.258.00:09:24.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:24.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:24.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.258.00:09:24.43#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:24.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:24.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:24.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:24.55#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:09:24.55#ibcon#first serial, iclass 12, count 0 2006.258.00:09:24.55#ibcon#enter sib2, iclass 12, count 0 2006.258.00:09:24.55#ibcon#flushed, iclass 12, count 0 2006.258.00:09:24.55#ibcon#about to write, iclass 12, count 0 2006.258.00:09:24.55#ibcon#wrote, iclass 12, count 0 2006.258.00:09:24.55#ibcon#about to read 3, iclass 12, count 0 2006.258.00:09:24.57#ibcon#read 3, iclass 12, count 0 2006.258.00:09:24.57#ibcon#about to read 4, iclass 12, count 0 2006.258.00:09:24.57#ibcon#read 4, iclass 12, count 0 2006.258.00:09:24.57#ibcon#about to read 5, iclass 12, count 0 2006.258.00:09:24.57#ibcon#read 5, iclass 12, count 0 2006.258.00:09:24.57#ibcon#about to read 6, iclass 12, count 0 2006.258.00:09:24.57#ibcon#read 6, iclass 12, count 0 2006.258.00:09:24.57#ibcon#end of sib2, iclass 12, count 0 2006.258.00:09:24.57#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:09:24.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:09:24.57#ibcon#[25=USB\r\n] 2006.258.00:09:24.57#ibcon#*before write, iclass 12, count 0 2006.258.00:09:24.57#ibcon#enter sib2, iclass 12, count 0 2006.258.00:09:24.57#ibcon#flushed, iclass 12, count 0 2006.258.00:09:24.57#ibcon#about to write, iclass 12, count 0 2006.258.00:09:24.57#ibcon#wrote, iclass 12, count 0 2006.258.00:09:24.57#ibcon#about to read 3, iclass 12, count 0 2006.258.00:09:24.60#ibcon#read 3, iclass 12, count 0 2006.258.00:09:24.60#ibcon#about to read 4, iclass 12, count 0 2006.258.00:09:24.60#ibcon#read 4, iclass 12, count 0 2006.258.00:09:24.60#ibcon#about to read 5, iclass 12, count 0 2006.258.00:09:24.60#ibcon#read 5, iclass 12, count 0 2006.258.00:09:24.60#ibcon#about to read 6, iclass 12, count 0 2006.258.00:09:24.60#ibcon#read 6, iclass 12, count 0 2006.258.00:09:24.60#ibcon#end of sib2, iclass 12, count 0 2006.258.00:09:24.60#ibcon#*after write, iclass 12, count 0 2006.258.00:09:24.60#ibcon#*before return 0, iclass 12, count 0 2006.258.00:09:24.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:24.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:24.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:09:24.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:09:24.60$vck44/valo=2,534.99 2006.258.00:09:24.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.00:09:24.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.00:09:24.60#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:24.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:24.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:24.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:24.60#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:09:24.60#ibcon#first serial, iclass 14, count 0 2006.258.00:09:24.60#ibcon#enter sib2, iclass 14, count 0 2006.258.00:09:24.60#ibcon#flushed, iclass 14, count 0 2006.258.00:09:24.60#ibcon#about to write, iclass 14, count 0 2006.258.00:09:24.60#ibcon#wrote, iclass 14, count 0 2006.258.00:09:24.60#ibcon#about to read 3, iclass 14, count 0 2006.258.00:09:24.62#ibcon#read 3, iclass 14, count 0 2006.258.00:09:24.62#ibcon#about to read 4, iclass 14, count 0 2006.258.00:09:24.62#ibcon#read 4, iclass 14, count 0 2006.258.00:09:24.62#ibcon#about to read 5, iclass 14, count 0 2006.258.00:09:24.62#ibcon#read 5, iclass 14, count 0 2006.258.00:09:24.62#ibcon#about to read 6, iclass 14, count 0 2006.258.00:09:24.62#ibcon#read 6, iclass 14, count 0 2006.258.00:09:24.62#ibcon#end of sib2, iclass 14, count 0 2006.258.00:09:24.62#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:09:24.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:09:24.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:09:24.62#ibcon#*before write, iclass 14, count 0 2006.258.00:09:24.62#ibcon#enter sib2, iclass 14, count 0 2006.258.00:09:24.62#ibcon#flushed, iclass 14, count 0 2006.258.00:09:24.62#ibcon#about to write, iclass 14, count 0 2006.258.00:09:24.62#ibcon#wrote, iclass 14, count 0 2006.258.00:09:24.62#ibcon#about to read 3, iclass 14, count 0 2006.258.00:09:24.66#ibcon#read 3, iclass 14, count 0 2006.258.00:09:24.66#ibcon#about to read 4, iclass 14, count 0 2006.258.00:09:24.66#ibcon#read 4, iclass 14, count 0 2006.258.00:09:24.66#ibcon#about to read 5, iclass 14, count 0 2006.258.00:09:24.66#ibcon#read 5, iclass 14, count 0 2006.258.00:09:24.66#ibcon#about to read 6, iclass 14, count 0 2006.258.00:09:24.66#ibcon#read 6, iclass 14, count 0 2006.258.00:09:24.66#ibcon#end of sib2, iclass 14, count 0 2006.258.00:09:24.66#ibcon#*after write, iclass 14, count 0 2006.258.00:09:24.66#ibcon#*before return 0, iclass 14, count 0 2006.258.00:09:24.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:24.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:24.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:09:24.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:09:24.66$vck44/va=2,7 2006.258.00:09:24.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.258.00:09:24.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.258.00:09:24.66#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:24.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:24.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:24.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:24.72#ibcon#enter wrdev, iclass 16, count 2 2006.258.00:09:24.72#ibcon#first serial, iclass 16, count 2 2006.258.00:09:24.72#ibcon#enter sib2, iclass 16, count 2 2006.258.00:09:24.72#ibcon#flushed, iclass 16, count 2 2006.258.00:09:24.72#ibcon#about to write, iclass 16, count 2 2006.258.00:09:24.72#ibcon#wrote, iclass 16, count 2 2006.258.00:09:24.72#ibcon#about to read 3, iclass 16, count 2 2006.258.00:09:24.74#ibcon#read 3, iclass 16, count 2 2006.258.00:09:24.74#ibcon#about to read 4, iclass 16, count 2 2006.258.00:09:24.74#ibcon#read 4, iclass 16, count 2 2006.258.00:09:24.74#ibcon#about to read 5, iclass 16, count 2 2006.258.00:09:24.74#ibcon#read 5, iclass 16, count 2 2006.258.00:09:24.74#ibcon#about to read 6, iclass 16, count 2 2006.258.00:09:24.74#ibcon#read 6, iclass 16, count 2 2006.258.00:09:24.74#ibcon#end of sib2, iclass 16, count 2 2006.258.00:09:24.74#ibcon#*mode == 0, iclass 16, count 2 2006.258.00:09:24.74#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.258.00:09:24.74#ibcon#[25=AT02-07\r\n] 2006.258.00:09:24.74#ibcon#*before write, iclass 16, count 2 2006.258.00:09:24.74#ibcon#enter sib2, iclass 16, count 2 2006.258.00:09:24.74#ibcon#flushed, iclass 16, count 2 2006.258.00:09:24.74#ibcon#about to write, iclass 16, count 2 2006.258.00:09:24.74#ibcon#wrote, iclass 16, count 2 2006.258.00:09:24.74#ibcon#about to read 3, iclass 16, count 2 2006.258.00:09:24.77#ibcon#read 3, iclass 16, count 2 2006.258.00:09:24.77#ibcon#about to read 4, iclass 16, count 2 2006.258.00:09:24.77#ibcon#read 4, iclass 16, count 2 2006.258.00:09:24.77#ibcon#about to read 5, iclass 16, count 2 2006.258.00:09:24.77#ibcon#read 5, iclass 16, count 2 2006.258.00:09:24.77#ibcon#about to read 6, iclass 16, count 2 2006.258.00:09:24.77#ibcon#read 6, iclass 16, count 2 2006.258.00:09:24.77#ibcon#end of sib2, iclass 16, count 2 2006.258.00:09:24.77#ibcon#*after write, iclass 16, count 2 2006.258.00:09:24.77#ibcon#*before return 0, iclass 16, count 2 2006.258.00:09:24.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:24.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:24.77#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.258.00:09:24.77#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:24.77#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:24.89#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:24.89#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:24.89#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:09:24.89#ibcon#first serial, iclass 16, count 0 2006.258.00:09:24.89#ibcon#enter sib2, iclass 16, count 0 2006.258.00:09:24.89#ibcon#flushed, iclass 16, count 0 2006.258.00:09:24.89#ibcon#about to write, iclass 16, count 0 2006.258.00:09:24.89#ibcon#wrote, iclass 16, count 0 2006.258.00:09:24.89#ibcon#about to read 3, iclass 16, count 0 2006.258.00:09:24.91#ibcon#read 3, iclass 16, count 0 2006.258.00:09:24.91#ibcon#about to read 4, iclass 16, count 0 2006.258.00:09:24.91#ibcon#read 4, iclass 16, count 0 2006.258.00:09:24.91#ibcon#about to read 5, iclass 16, count 0 2006.258.00:09:24.91#ibcon#read 5, iclass 16, count 0 2006.258.00:09:24.91#ibcon#about to read 6, iclass 16, count 0 2006.258.00:09:24.91#ibcon#read 6, iclass 16, count 0 2006.258.00:09:24.91#ibcon#end of sib2, iclass 16, count 0 2006.258.00:09:24.91#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:09:24.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:09:24.91#ibcon#[25=USB\r\n] 2006.258.00:09:24.91#ibcon#*before write, iclass 16, count 0 2006.258.00:09:24.91#ibcon#enter sib2, iclass 16, count 0 2006.258.00:09:24.91#ibcon#flushed, iclass 16, count 0 2006.258.00:09:24.91#ibcon#about to write, iclass 16, count 0 2006.258.00:09:24.91#ibcon#wrote, iclass 16, count 0 2006.258.00:09:24.91#ibcon#about to read 3, iclass 16, count 0 2006.258.00:09:24.94#ibcon#read 3, iclass 16, count 0 2006.258.00:09:24.94#ibcon#about to read 4, iclass 16, count 0 2006.258.00:09:24.94#ibcon#read 4, iclass 16, count 0 2006.258.00:09:24.94#ibcon#about to read 5, iclass 16, count 0 2006.258.00:09:24.94#ibcon#read 5, iclass 16, count 0 2006.258.00:09:24.94#ibcon#about to read 6, iclass 16, count 0 2006.258.00:09:24.94#ibcon#read 6, iclass 16, count 0 2006.258.00:09:24.94#ibcon#end of sib2, iclass 16, count 0 2006.258.00:09:24.94#ibcon#*after write, iclass 16, count 0 2006.258.00:09:24.94#ibcon#*before return 0, iclass 16, count 0 2006.258.00:09:24.94#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:24.94#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:24.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:09:24.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:09:24.94$vck44/valo=3,564.99 2006.258.00:09:24.94#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.00:09:24.94#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.00:09:24.94#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:24.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:24.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:24.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:24.94#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:09:24.94#ibcon#first serial, iclass 18, count 0 2006.258.00:09:24.94#ibcon#enter sib2, iclass 18, count 0 2006.258.00:09:24.94#ibcon#flushed, iclass 18, count 0 2006.258.00:09:24.94#ibcon#about to write, iclass 18, count 0 2006.258.00:09:24.94#ibcon#wrote, iclass 18, count 0 2006.258.00:09:24.94#ibcon#about to read 3, iclass 18, count 0 2006.258.00:09:24.96#ibcon#read 3, iclass 18, count 0 2006.258.00:09:24.96#ibcon#about to read 4, iclass 18, count 0 2006.258.00:09:24.96#ibcon#read 4, iclass 18, count 0 2006.258.00:09:24.96#ibcon#about to read 5, iclass 18, count 0 2006.258.00:09:24.96#ibcon#read 5, iclass 18, count 0 2006.258.00:09:24.96#ibcon#about to read 6, iclass 18, count 0 2006.258.00:09:24.96#ibcon#read 6, iclass 18, count 0 2006.258.00:09:24.96#ibcon#end of sib2, iclass 18, count 0 2006.258.00:09:24.96#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:09:24.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:09:24.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:09:24.96#ibcon#*before write, iclass 18, count 0 2006.258.00:09:24.96#ibcon#enter sib2, iclass 18, count 0 2006.258.00:09:24.96#ibcon#flushed, iclass 18, count 0 2006.258.00:09:24.96#ibcon#about to write, iclass 18, count 0 2006.258.00:09:24.96#ibcon#wrote, iclass 18, count 0 2006.258.00:09:24.96#ibcon#about to read 3, iclass 18, count 0 2006.258.00:09:25.00#ibcon#read 3, iclass 18, count 0 2006.258.00:09:25.00#ibcon#about to read 4, iclass 18, count 0 2006.258.00:09:25.00#ibcon#read 4, iclass 18, count 0 2006.258.00:09:25.00#ibcon#about to read 5, iclass 18, count 0 2006.258.00:09:25.00#ibcon#read 5, iclass 18, count 0 2006.258.00:09:25.00#ibcon#about to read 6, iclass 18, count 0 2006.258.00:09:25.00#ibcon#read 6, iclass 18, count 0 2006.258.00:09:25.00#ibcon#end of sib2, iclass 18, count 0 2006.258.00:09:25.00#ibcon#*after write, iclass 18, count 0 2006.258.00:09:25.00#ibcon#*before return 0, iclass 18, count 0 2006.258.00:09:25.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:25.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:25.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:09:25.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:09:25.00$vck44/va=3,8 2006.258.00:09:25.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.00:09:25.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.00:09:25.00#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:25.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:25.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:25.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:25.06#ibcon#enter wrdev, iclass 20, count 2 2006.258.00:09:25.06#ibcon#first serial, iclass 20, count 2 2006.258.00:09:25.06#ibcon#enter sib2, iclass 20, count 2 2006.258.00:09:25.06#ibcon#flushed, iclass 20, count 2 2006.258.00:09:25.06#ibcon#about to write, iclass 20, count 2 2006.258.00:09:25.06#ibcon#wrote, iclass 20, count 2 2006.258.00:09:25.06#ibcon#about to read 3, iclass 20, count 2 2006.258.00:09:25.08#ibcon#read 3, iclass 20, count 2 2006.258.00:09:25.08#ibcon#about to read 4, iclass 20, count 2 2006.258.00:09:25.08#ibcon#read 4, iclass 20, count 2 2006.258.00:09:25.08#ibcon#about to read 5, iclass 20, count 2 2006.258.00:09:25.08#ibcon#read 5, iclass 20, count 2 2006.258.00:09:25.08#ibcon#about to read 6, iclass 20, count 2 2006.258.00:09:25.08#ibcon#read 6, iclass 20, count 2 2006.258.00:09:25.08#ibcon#end of sib2, iclass 20, count 2 2006.258.00:09:25.08#ibcon#*mode == 0, iclass 20, count 2 2006.258.00:09:25.08#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.00:09:25.08#ibcon#[25=AT03-08\r\n] 2006.258.00:09:25.08#ibcon#*before write, iclass 20, count 2 2006.258.00:09:25.08#ibcon#enter sib2, iclass 20, count 2 2006.258.00:09:25.08#ibcon#flushed, iclass 20, count 2 2006.258.00:09:25.08#ibcon#about to write, iclass 20, count 2 2006.258.00:09:25.08#ibcon#wrote, iclass 20, count 2 2006.258.00:09:25.08#ibcon#about to read 3, iclass 20, count 2 2006.258.00:09:25.11#ibcon#read 3, iclass 20, count 2 2006.258.00:09:25.11#ibcon#about to read 4, iclass 20, count 2 2006.258.00:09:25.11#ibcon#read 4, iclass 20, count 2 2006.258.00:09:25.11#ibcon#about to read 5, iclass 20, count 2 2006.258.00:09:25.11#ibcon#read 5, iclass 20, count 2 2006.258.00:09:25.11#ibcon#about to read 6, iclass 20, count 2 2006.258.00:09:25.11#ibcon#read 6, iclass 20, count 2 2006.258.00:09:25.11#ibcon#end of sib2, iclass 20, count 2 2006.258.00:09:25.11#ibcon#*after write, iclass 20, count 2 2006.258.00:09:25.11#ibcon#*before return 0, iclass 20, count 2 2006.258.00:09:25.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:25.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:25.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.00:09:25.11#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:25.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:25.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:25.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:25.23#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:09:25.23#ibcon#first serial, iclass 20, count 0 2006.258.00:09:25.23#ibcon#enter sib2, iclass 20, count 0 2006.258.00:09:25.23#ibcon#flushed, iclass 20, count 0 2006.258.00:09:25.23#ibcon#about to write, iclass 20, count 0 2006.258.00:09:25.23#ibcon#wrote, iclass 20, count 0 2006.258.00:09:25.23#ibcon#about to read 3, iclass 20, count 0 2006.258.00:09:25.25#ibcon#read 3, iclass 20, count 0 2006.258.00:09:25.25#ibcon#about to read 4, iclass 20, count 0 2006.258.00:09:25.25#ibcon#read 4, iclass 20, count 0 2006.258.00:09:25.25#ibcon#about to read 5, iclass 20, count 0 2006.258.00:09:25.25#ibcon#read 5, iclass 20, count 0 2006.258.00:09:25.25#ibcon#about to read 6, iclass 20, count 0 2006.258.00:09:25.25#ibcon#read 6, iclass 20, count 0 2006.258.00:09:25.25#ibcon#end of sib2, iclass 20, count 0 2006.258.00:09:25.25#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:09:25.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:09:25.25#ibcon#[25=USB\r\n] 2006.258.00:09:25.25#ibcon#*before write, iclass 20, count 0 2006.258.00:09:25.25#ibcon#enter sib2, iclass 20, count 0 2006.258.00:09:25.25#ibcon#flushed, iclass 20, count 0 2006.258.00:09:25.25#ibcon#about to write, iclass 20, count 0 2006.258.00:09:25.25#ibcon#wrote, iclass 20, count 0 2006.258.00:09:25.25#ibcon#about to read 3, iclass 20, count 0 2006.258.00:09:25.28#ibcon#read 3, iclass 20, count 0 2006.258.00:09:25.28#ibcon#about to read 4, iclass 20, count 0 2006.258.00:09:25.28#ibcon#read 4, iclass 20, count 0 2006.258.00:09:25.28#ibcon#about to read 5, iclass 20, count 0 2006.258.00:09:25.28#ibcon#read 5, iclass 20, count 0 2006.258.00:09:25.28#ibcon#about to read 6, iclass 20, count 0 2006.258.00:09:25.28#ibcon#read 6, iclass 20, count 0 2006.258.00:09:25.28#ibcon#end of sib2, iclass 20, count 0 2006.258.00:09:25.28#ibcon#*after write, iclass 20, count 0 2006.258.00:09:25.28#ibcon#*before return 0, iclass 20, count 0 2006.258.00:09:25.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:25.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:25.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:09:25.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:09:25.28$vck44/valo=4,624.99 2006.258.00:09:25.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.00:09:25.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.00:09:25.28#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:25.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:25.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:25.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:25.28#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:09:25.28#ibcon#first serial, iclass 22, count 0 2006.258.00:09:25.28#ibcon#enter sib2, iclass 22, count 0 2006.258.00:09:25.28#ibcon#flushed, iclass 22, count 0 2006.258.00:09:25.28#ibcon#about to write, iclass 22, count 0 2006.258.00:09:25.28#ibcon#wrote, iclass 22, count 0 2006.258.00:09:25.28#ibcon#about to read 3, iclass 22, count 0 2006.258.00:09:25.30#ibcon#read 3, iclass 22, count 0 2006.258.00:09:25.30#ibcon#about to read 4, iclass 22, count 0 2006.258.00:09:25.30#ibcon#read 4, iclass 22, count 0 2006.258.00:09:25.30#ibcon#about to read 5, iclass 22, count 0 2006.258.00:09:25.30#ibcon#read 5, iclass 22, count 0 2006.258.00:09:25.30#ibcon#about to read 6, iclass 22, count 0 2006.258.00:09:25.30#ibcon#read 6, iclass 22, count 0 2006.258.00:09:25.30#ibcon#end of sib2, iclass 22, count 0 2006.258.00:09:25.30#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:09:25.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:09:25.30#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:09:25.30#ibcon#*before write, iclass 22, count 0 2006.258.00:09:25.30#ibcon#enter sib2, iclass 22, count 0 2006.258.00:09:25.30#ibcon#flushed, iclass 22, count 0 2006.258.00:09:25.30#ibcon#about to write, iclass 22, count 0 2006.258.00:09:25.30#ibcon#wrote, iclass 22, count 0 2006.258.00:09:25.30#ibcon#about to read 3, iclass 22, count 0 2006.258.00:09:25.34#ibcon#read 3, iclass 22, count 0 2006.258.00:09:25.34#ibcon#about to read 4, iclass 22, count 0 2006.258.00:09:25.34#ibcon#read 4, iclass 22, count 0 2006.258.00:09:25.34#ibcon#about to read 5, iclass 22, count 0 2006.258.00:09:25.34#ibcon#read 5, iclass 22, count 0 2006.258.00:09:25.34#ibcon#about to read 6, iclass 22, count 0 2006.258.00:09:25.34#ibcon#read 6, iclass 22, count 0 2006.258.00:09:25.34#ibcon#end of sib2, iclass 22, count 0 2006.258.00:09:25.34#ibcon#*after write, iclass 22, count 0 2006.258.00:09:25.34#ibcon#*before return 0, iclass 22, count 0 2006.258.00:09:25.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:25.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:25.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:09:25.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:09:25.34$vck44/va=4,7 2006.258.00:09:25.34#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.00:09:25.34#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.00:09:25.34#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:25.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:25.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:25.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:25.40#ibcon#enter wrdev, iclass 24, count 2 2006.258.00:09:25.40#ibcon#first serial, iclass 24, count 2 2006.258.00:09:25.40#ibcon#enter sib2, iclass 24, count 2 2006.258.00:09:25.40#ibcon#flushed, iclass 24, count 2 2006.258.00:09:25.40#ibcon#about to write, iclass 24, count 2 2006.258.00:09:25.40#ibcon#wrote, iclass 24, count 2 2006.258.00:09:25.40#ibcon#about to read 3, iclass 24, count 2 2006.258.00:09:25.42#ibcon#read 3, iclass 24, count 2 2006.258.00:09:25.42#ibcon#about to read 4, iclass 24, count 2 2006.258.00:09:25.42#ibcon#read 4, iclass 24, count 2 2006.258.00:09:25.42#ibcon#about to read 5, iclass 24, count 2 2006.258.00:09:25.42#ibcon#read 5, iclass 24, count 2 2006.258.00:09:25.42#ibcon#about to read 6, iclass 24, count 2 2006.258.00:09:25.42#ibcon#read 6, iclass 24, count 2 2006.258.00:09:25.42#ibcon#end of sib2, iclass 24, count 2 2006.258.00:09:25.42#ibcon#*mode == 0, iclass 24, count 2 2006.258.00:09:25.42#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.00:09:25.42#ibcon#[25=AT04-07\r\n] 2006.258.00:09:25.42#ibcon#*before write, iclass 24, count 2 2006.258.00:09:25.42#ibcon#enter sib2, iclass 24, count 2 2006.258.00:09:25.42#ibcon#flushed, iclass 24, count 2 2006.258.00:09:25.42#ibcon#about to write, iclass 24, count 2 2006.258.00:09:25.42#ibcon#wrote, iclass 24, count 2 2006.258.00:09:25.42#ibcon#about to read 3, iclass 24, count 2 2006.258.00:09:25.45#ibcon#read 3, iclass 24, count 2 2006.258.00:09:25.45#ibcon#about to read 4, iclass 24, count 2 2006.258.00:09:25.45#ibcon#read 4, iclass 24, count 2 2006.258.00:09:25.45#ibcon#about to read 5, iclass 24, count 2 2006.258.00:09:25.45#ibcon#read 5, iclass 24, count 2 2006.258.00:09:25.45#ibcon#about to read 6, iclass 24, count 2 2006.258.00:09:25.45#ibcon#read 6, iclass 24, count 2 2006.258.00:09:25.45#ibcon#end of sib2, iclass 24, count 2 2006.258.00:09:25.45#ibcon#*after write, iclass 24, count 2 2006.258.00:09:25.45#ibcon#*before return 0, iclass 24, count 2 2006.258.00:09:25.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:25.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:25.48#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.00:09:25.48#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:25.48#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:25.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:25.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:25.59#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:09:25.59#ibcon#first serial, iclass 24, count 0 2006.258.00:09:25.59#ibcon#enter sib2, iclass 24, count 0 2006.258.00:09:25.59#ibcon#flushed, iclass 24, count 0 2006.258.00:09:25.59#ibcon#about to write, iclass 24, count 0 2006.258.00:09:25.59#ibcon#wrote, iclass 24, count 0 2006.258.00:09:25.59#ibcon#about to read 3, iclass 24, count 0 2006.258.00:09:25.61#ibcon#read 3, iclass 24, count 0 2006.258.00:09:25.61#ibcon#about to read 4, iclass 24, count 0 2006.258.00:09:25.61#ibcon#read 4, iclass 24, count 0 2006.258.00:09:25.61#ibcon#about to read 5, iclass 24, count 0 2006.258.00:09:25.61#ibcon#read 5, iclass 24, count 0 2006.258.00:09:25.61#ibcon#about to read 6, iclass 24, count 0 2006.258.00:09:25.61#ibcon#read 6, iclass 24, count 0 2006.258.00:09:25.61#ibcon#end of sib2, iclass 24, count 0 2006.258.00:09:25.61#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:09:25.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:09:25.61#ibcon#[25=USB\r\n] 2006.258.00:09:25.61#ibcon#*before write, iclass 24, count 0 2006.258.00:09:25.61#ibcon#enter sib2, iclass 24, count 0 2006.258.00:09:25.61#ibcon#flushed, iclass 24, count 0 2006.258.00:09:25.61#ibcon#about to write, iclass 24, count 0 2006.258.00:09:25.61#ibcon#wrote, iclass 24, count 0 2006.258.00:09:25.61#ibcon#about to read 3, iclass 24, count 0 2006.258.00:09:25.64#ibcon#read 3, iclass 24, count 0 2006.258.00:09:25.64#ibcon#about to read 4, iclass 24, count 0 2006.258.00:09:25.64#ibcon#read 4, iclass 24, count 0 2006.258.00:09:25.64#ibcon#about to read 5, iclass 24, count 0 2006.258.00:09:25.64#ibcon#read 5, iclass 24, count 0 2006.258.00:09:25.64#ibcon#about to read 6, iclass 24, count 0 2006.258.00:09:25.64#ibcon#read 6, iclass 24, count 0 2006.258.00:09:25.64#ibcon#end of sib2, iclass 24, count 0 2006.258.00:09:25.64#ibcon#*after write, iclass 24, count 0 2006.258.00:09:25.64#ibcon#*before return 0, iclass 24, count 0 2006.258.00:09:25.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:25.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:25.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:09:25.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:09:25.64$vck44/valo=5,734.99 2006.258.00:09:25.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.00:09:25.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.00:09:25.64#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:25.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:25.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:25.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:25.64#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:09:25.64#ibcon#first serial, iclass 26, count 0 2006.258.00:09:25.64#ibcon#enter sib2, iclass 26, count 0 2006.258.00:09:25.64#ibcon#flushed, iclass 26, count 0 2006.258.00:09:25.64#ibcon#about to write, iclass 26, count 0 2006.258.00:09:25.64#ibcon#wrote, iclass 26, count 0 2006.258.00:09:25.64#ibcon#about to read 3, iclass 26, count 0 2006.258.00:09:25.66#ibcon#read 3, iclass 26, count 0 2006.258.00:09:25.66#ibcon#about to read 4, iclass 26, count 0 2006.258.00:09:25.66#ibcon#read 4, iclass 26, count 0 2006.258.00:09:25.66#ibcon#about to read 5, iclass 26, count 0 2006.258.00:09:25.66#ibcon#read 5, iclass 26, count 0 2006.258.00:09:25.66#ibcon#about to read 6, iclass 26, count 0 2006.258.00:09:25.66#ibcon#read 6, iclass 26, count 0 2006.258.00:09:25.66#ibcon#end of sib2, iclass 26, count 0 2006.258.00:09:25.66#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:09:25.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:09:25.66#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:09:25.66#ibcon#*before write, iclass 26, count 0 2006.258.00:09:25.66#ibcon#enter sib2, iclass 26, count 0 2006.258.00:09:25.66#ibcon#flushed, iclass 26, count 0 2006.258.00:09:25.66#ibcon#about to write, iclass 26, count 0 2006.258.00:09:25.66#ibcon#wrote, iclass 26, count 0 2006.258.00:09:25.66#ibcon#about to read 3, iclass 26, count 0 2006.258.00:09:25.70#ibcon#read 3, iclass 26, count 0 2006.258.00:09:25.70#ibcon#about to read 4, iclass 26, count 0 2006.258.00:09:25.70#ibcon#read 4, iclass 26, count 0 2006.258.00:09:25.70#ibcon#about to read 5, iclass 26, count 0 2006.258.00:09:25.70#ibcon#read 5, iclass 26, count 0 2006.258.00:09:25.70#ibcon#about to read 6, iclass 26, count 0 2006.258.00:09:25.70#ibcon#read 6, iclass 26, count 0 2006.258.00:09:25.70#ibcon#end of sib2, iclass 26, count 0 2006.258.00:09:25.70#ibcon#*after write, iclass 26, count 0 2006.258.00:09:25.70#ibcon#*before return 0, iclass 26, count 0 2006.258.00:09:25.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:25.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:25.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:09:25.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:09:25.70$vck44/va=5,4 2006.258.00:09:25.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.00:09:25.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.00:09:25.70#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:25.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:25.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:25.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:25.76#ibcon#enter wrdev, iclass 28, count 2 2006.258.00:09:25.76#ibcon#first serial, iclass 28, count 2 2006.258.00:09:25.76#ibcon#enter sib2, iclass 28, count 2 2006.258.00:09:25.76#ibcon#flushed, iclass 28, count 2 2006.258.00:09:25.76#ibcon#about to write, iclass 28, count 2 2006.258.00:09:25.76#ibcon#wrote, iclass 28, count 2 2006.258.00:09:25.76#ibcon#about to read 3, iclass 28, count 2 2006.258.00:09:25.78#ibcon#read 3, iclass 28, count 2 2006.258.00:09:25.78#ibcon#about to read 4, iclass 28, count 2 2006.258.00:09:25.78#ibcon#read 4, iclass 28, count 2 2006.258.00:09:25.78#ibcon#about to read 5, iclass 28, count 2 2006.258.00:09:25.78#ibcon#read 5, iclass 28, count 2 2006.258.00:09:25.78#ibcon#about to read 6, iclass 28, count 2 2006.258.00:09:25.78#ibcon#read 6, iclass 28, count 2 2006.258.00:09:25.78#ibcon#end of sib2, iclass 28, count 2 2006.258.00:09:25.78#ibcon#*mode == 0, iclass 28, count 2 2006.258.00:09:25.78#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.00:09:25.78#ibcon#[25=AT05-04\r\n] 2006.258.00:09:25.78#ibcon#*before write, iclass 28, count 2 2006.258.00:09:25.78#ibcon#enter sib2, iclass 28, count 2 2006.258.00:09:25.78#ibcon#flushed, iclass 28, count 2 2006.258.00:09:25.78#ibcon#about to write, iclass 28, count 2 2006.258.00:09:25.78#ibcon#wrote, iclass 28, count 2 2006.258.00:09:25.78#ibcon#about to read 3, iclass 28, count 2 2006.258.00:09:25.81#ibcon#read 3, iclass 28, count 2 2006.258.00:09:25.81#ibcon#about to read 4, iclass 28, count 2 2006.258.00:09:25.81#ibcon#read 4, iclass 28, count 2 2006.258.00:09:25.81#ibcon#about to read 5, iclass 28, count 2 2006.258.00:09:25.81#ibcon#read 5, iclass 28, count 2 2006.258.00:09:25.81#ibcon#about to read 6, iclass 28, count 2 2006.258.00:09:25.81#ibcon#read 6, iclass 28, count 2 2006.258.00:09:25.81#ibcon#end of sib2, iclass 28, count 2 2006.258.00:09:25.81#ibcon#*after write, iclass 28, count 2 2006.258.00:09:25.81#ibcon#*before return 0, iclass 28, count 2 2006.258.00:09:25.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:25.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:25.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.00:09:25.81#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:25.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:25.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:25.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:25.93#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:09:25.93#ibcon#first serial, iclass 28, count 0 2006.258.00:09:25.93#ibcon#enter sib2, iclass 28, count 0 2006.258.00:09:25.93#ibcon#flushed, iclass 28, count 0 2006.258.00:09:25.93#ibcon#about to write, iclass 28, count 0 2006.258.00:09:25.93#ibcon#wrote, iclass 28, count 0 2006.258.00:09:25.93#ibcon#about to read 3, iclass 28, count 0 2006.258.00:09:25.95#ibcon#read 3, iclass 28, count 0 2006.258.00:09:25.95#ibcon#about to read 4, iclass 28, count 0 2006.258.00:09:25.95#ibcon#read 4, iclass 28, count 0 2006.258.00:09:25.95#ibcon#about to read 5, iclass 28, count 0 2006.258.00:09:25.95#ibcon#read 5, iclass 28, count 0 2006.258.00:09:25.95#ibcon#about to read 6, iclass 28, count 0 2006.258.00:09:25.95#ibcon#read 6, iclass 28, count 0 2006.258.00:09:25.95#ibcon#end of sib2, iclass 28, count 0 2006.258.00:09:25.95#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:09:25.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:09:25.95#ibcon#[25=USB\r\n] 2006.258.00:09:25.95#ibcon#*before write, iclass 28, count 0 2006.258.00:09:25.95#ibcon#enter sib2, iclass 28, count 0 2006.258.00:09:25.95#ibcon#flushed, iclass 28, count 0 2006.258.00:09:25.95#ibcon#about to write, iclass 28, count 0 2006.258.00:09:25.95#ibcon#wrote, iclass 28, count 0 2006.258.00:09:25.95#ibcon#about to read 3, iclass 28, count 0 2006.258.00:09:25.98#ibcon#read 3, iclass 28, count 0 2006.258.00:09:25.98#ibcon#about to read 4, iclass 28, count 0 2006.258.00:09:25.98#ibcon#read 4, iclass 28, count 0 2006.258.00:09:25.98#ibcon#about to read 5, iclass 28, count 0 2006.258.00:09:25.98#ibcon#read 5, iclass 28, count 0 2006.258.00:09:25.98#ibcon#about to read 6, iclass 28, count 0 2006.258.00:09:25.98#ibcon#read 6, iclass 28, count 0 2006.258.00:09:25.98#ibcon#end of sib2, iclass 28, count 0 2006.258.00:09:25.98#ibcon#*after write, iclass 28, count 0 2006.258.00:09:25.98#ibcon#*before return 0, iclass 28, count 0 2006.258.00:09:25.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:25.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:25.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:09:25.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:09:25.98$vck44/valo=6,814.99 2006.258.00:09:25.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.00:09:25.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.00:09:25.98#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:25.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:25.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:25.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:25.98#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:09:25.98#ibcon#first serial, iclass 30, count 0 2006.258.00:09:25.98#ibcon#enter sib2, iclass 30, count 0 2006.258.00:09:25.98#ibcon#flushed, iclass 30, count 0 2006.258.00:09:25.98#ibcon#about to write, iclass 30, count 0 2006.258.00:09:25.98#ibcon#wrote, iclass 30, count 0 2006.258.00:09:25.98#ibcon#about to read 3, iclass 30, count 0 2006.258.00:09:26.00#ibcon#read 3, iclass 30, count 0 2006.258.00:09:26.00#ibcon#about to read 4, iclass 30, count 0 2006.258.00:09:26.00#ibcon#read 4, iclass 30, count 0 2006.258.00:09:26.00#ibcon#about to read 5, iclass 30, count 0 2006.258.00:09:26.00#ibcon#read 5, iclass 30, count 0 2006.258.00:09:26.00#ibcon#about to read 6, iclass 30, count 0 2006.258.00:09:26.00#ibcon#read 6, iclass 30, count 0 2006.258.00:09:26.00#ibcon#end of sib2, iclass 30, count 0 2006.258.00:09:26.00#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:09:26.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:09:26.00#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:09:26.00#ibcon#*before write, iclass 30, count 0 2006.258.00:09:26.00#ibcon#enter sib2, iclass 30, count 0 2006.258.00:09:26.00#ibcon#flushed, iclass 30, count 0 2006.258.00:09:26.00#ibcon#about to write, iclass 30, count 0 2006.258.00:09:26.00#ibcon#wrote, iclass 30, count 0 2006.258.00:09:26.00#ibcon#about to read 3, iclass 30, count 0 2006.258.00:09:26.04#ibcon#read 3, iclass 30, count 0 2006.258.00:09:26.04#ibcon#about to read 4, iclass 30, count 0 2006.258.00:09:26.04#ibcon#read 4, iclass 30, count 0 2006.258.00:09:26.04#ibcon#about to read 5, iclass 30, count 0 2006.258.00:09:26.04#ibcon#read 5, iclass 30, count 0 2006.258.00:09:26.04#ibcon#about to read 6, iclass 30, count 0 2006.258.00:09:26.04#ibcon#read 6, iclass 30, count 0 2006.258.00:09:26.04#ibcon#end of sib2, iclass 30, count 0 2006.258.00:09:26.04#ibcon#*after write, iclass 30, count 0 2006.258.00:09:26.04#ibcon#*before return 0, iclass 30, count 0 2006.258.00:09:26.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:26.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:26.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:09:26.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:09:26.04$vck44/va=6,4 2006.258.00:09:26.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.258.00:09:26.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.258.00:09:26.04#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:26.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:26.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:26.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:26.10#ibcon#enter wrdev, iclass 32, count 2 2006.258.00:09:26.10#ibcon#first serial, iclass 32, count 2 2006.258.00:09:26.10#ibcon#enter sib2, iclass 32, count 2 2006.258.00:09:26.10#ibcon#flushed, iclass 32, count 2 2006.258.00:09:26.10#ibcon#about to write, iclass 32, count 2 2006.258.00:09:26.10#ibcon#wrote, iclass 32, count 2 2006.258.00:09:26.10#ibcon#about to read 3, iclass 32, count 2 2006.258.00:09:26.12#ibcon#read 3, iclass 32, count 2 2006.258.00:09:26.12#ibcon#about to read 4, iclass 32, count 2 2006.258.00:09:26.12#ibcon#read 4, iclass 32, count 2 2006.258.00:09:26.12#ibcon#about to read 5, iclass 32, count 2 2006.258.00:09:26.12#ibcon#read 5, iclass 32, count 2 2006.258.00:09:26.12#ibcon#about to read 6, iclass 32, count 2 2006.258.00:09:26.12#ibcon#read 6, iclass 32, count 2 2006.258.00:09:26.12#ibcon#end of sib2, iclass 32, count 2 2006.258.00:09:26.12#ibcon#*mode == 0, iclass 32, count 2 2006.258.00:09:26.12#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.258.00:09:26.12#ibcon#[25=AT06-04\r\n] 2006.258.00:09:26.12#ibcon#*before write, iclass 32, count 2 2006.258.00:09:26.12#ibcon#enter sib2, iclass 32, count 2 2006.258.00:09:26.12#ibcon#flushed, iclass 32, count 2 2006.258.00:09:26.12#ibcon#about to write, iclass 32, count 2 2006.258.00:09:26.12#ibcon#wrote, iclass 32, count 2 2006.258.00:09:26.12#ibcon#about to read 3, iclass 32, count 2 2006.258.00:09:26.15#ibcon#read 3, iclass 32, count 2 2006.258.00:09:26.15#ibcon#about to read 4, iclass 32, count 2 2006.258.00:09:26.15#ibcon#read 4, iclass 32, count 2 2006.258.00:09:26.15#ibcon#about to read 5, iclass 32, count 2 2006.258.00:09:26.15#ibcon#read 5, iclass 32, count 2 2006.258.00:09:26.15#ibcon#about to read 6, iclass 32, count 2 2006.258.00:09:26.15#ibcon#read 6, iclass 32, count 2 2006.258.00:09:26.15#ibcon#end of sib2, iclass 32, count 2 2006.258.00:09:26.15#ibcon#*after write, iclass 32, count 2 2006.258.00:09:26.15#ibcon#*before return 0, iclass 32, count 2 2006.258.00:09:26.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:26.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:26.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.258.00:09:26.15#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:26.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:26.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:26.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:26.27#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:09:26.27#ibcon#first serial, iclass 32, count 0 2006.258.00:09:26.27#ibcon#enter sib2, iclass 32, count 0 2006.258.00:09:26.27#ibcon#flushed, iclass 32, count 0 2006.258.00:09:26.27#ibcon#about to write, iclass 32, count 0 2006.258.00:09:26.27#ibcon#wrote, iclass 32, count 0 2006.258.00:09:26.27#ibcon#about to read 3, iclass 32, count 0 2006.258.00:09:26.29#ibcon#read 3, iclass 32, count 0 2006.258.00:09:26.29#ibcon#about to read 4, iclass 32, count 0 2006.258.00:09:26.29#ibcon#read 4, iclass 32, count 0 2006.258.00:09:26.29#ibcon#about to read 5, iclass 32, count 0 2006.258.00:09:26.29#ibcon#read 5, iclass 32, count 0 2006.258.00:09:26.29#ibcon#about to read 6, iclass 32, count 0 2006.258.00:09:26.29#ibcon#read 6, iclass 32, count 0 2006.258.00:09:26.29#ibcon#end of sib2, iclass 32, count 0 2006.258.00:09:26.29#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:09:26.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:09:26.29#ibcon#[25=USB\r\n] 2006.258.00:09:26.29#ibcon#*before write, iclass 32, count 0 2006.258.00:09:26.29#ibcon#enter sib2, iclass 32, count 0 2006.258.00:09:26.29#ibcon#flushed, iclass 32, count 0 2006.258.00:09:26.29#ibcon#about to write, iclass 32, count 0 2006.258.00:09:26.29#ibcon#wrote, iclass 32, count 0 2006.258.00:09:26.29#ibcon#about to read 3, iclass 32, count 0 2006.258.00:09:26.32#ibcon#read 3, iclass 32, count 0 2006.258.00:09:26.32#ibcon#about to read 4, iclass 32, count 0 2006.258.00:09:26.32#ibcon#read 4, iclass 32, count 0 2006.258.00:09:26.32#ibcon#about to read 5, iclass 32, count 0 2006.258.00:09:26.32#ibcon#read 5, iclass 32, count 0 2006.258.00:09:26.32#ibcon#about to read 6, iclass 32, count 0 2006.258.00:09:26.32#ibcon#read 6, iclass 32, count 0 2006.258.00:09:26.32#ibcon#end of sib2, iclass 32, count 0 2006.258.00:09:26.32#ibcon#*after write, iclass 32, count 0 2006.258.00:09:26.32#ibcon#*before return 0, iclass 32, count 0 2006.258.00:09:26.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:26.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:26.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:09:26.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:09:26.32$vck44/valo=7,864.99 2006.258.00:09:26.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.00:09:26.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.00:09:26.32#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:26.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:26.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:26.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:26.32#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:09:26.32#ibcon#first serial, iclass 34, count 0 2006.258.00:09:26.32#ibcon#enter sib2, iclass 34, count 0 2006.258.00:09:26.32#ibcon#flushed, iclass 34, count 0 2006.258.00:09:26.32#ibcon#about to write, iclass 34, count 0 2006.258.00:09:26.32#ibcon#wrote, iclass 34, count 0 2006.258.00:09:26.32#ibcon#about to read 3, iclass 34, count 0 2006.258.00:09:26.34#ibcon#read 3, iclass 34, count 0 2006.258.00:09:26.34#ibcon#about to read 4, iclass 34, count 0 2006.258.00:09:26.34#ibcon#read 4, iclass 34, count 0 2006.258.00:09:26.34#ibcon#about to read 5, iclass 34, count 0 2006.258.00:09:26.34#ibcon#read 5, iclass 34, count 0 2006.258.00:09:26.34#ibcon#about to read 6, iclass 34, count 0 2006.258.00:09:26.34#ibcon#read 6, iclass 34, count 0 2006.258.00:09:26.34#ibcon#end of sib2, iclass 34, count 0 2006.258.00:09:26.34#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:09:26.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:09:26.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:09:26.34#ibcon#*before write, iclass 34, count 0 2006.258.00:09:26.34#ibcon#enter sib2, iclass 34, count 0 2006.258.00:09:26.34#ibcon#flushed, iclass 34, count 0 2006.258.00:09:26.34#ibcon#about to write, iclass 34, count 0 2006.258.00:09:26.34#ibcon#wrote, iclass 34, count 0 2006.258.00:09:26.34#ibcon#about to read 3, iclass 34, count 0 2006.258.00:09:26.38#ibcon#read 3, iclass 34, count 0 2006.258.00:09:26.38#ibcon#about to read 4, iclass 34, count 0 2006.258.00:09:26.38#ibcon#read 4, iclass 34, count 0 2006.258.00:09:26.38#ibcon#about to read 5, iclass 34, count 0 2006.258.00:09:26.38#ibcon#read 5, iclass 34, count 0 2006.258.00:09:26.38#ibcon#about to read 6, iclass 34, count 0 2006.258.00:09:26.38#ibcon#read 6, iclass 34, count 0 2006.258.00:09:26.38#ibcon#end of sib2, iclass 34, count 0 2006.258.00:09:26.38#ibcon#*after write, iclass 34, count 0 2006.258.00:09:26.38#ibcon#*before return 0, iclass 34, count 0 2006.258.00:09:26.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:26.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:26.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:09:26.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:09:26.38$vck44/va=7,4 2006.258.00:09:26.38#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.258.00:09:26.38#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.258.00:09:26.38#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:26.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:26.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:26.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:26.44#ibcon#enter wrdev, iclass 36, count 2 2006.258.00:09:26.44#ibcon#first serial, iclass 36, count 2 2006.258.00:09:26.44#ibcon#enter sib2, iclass 36, count 2 2006.258.00:09:26.44#ibcon#flushed, iclass 36, count 2 2006.258.00:09:26.44#ibcon#about to write, iclass 36, count 2 2006.258.00:09:26.44#ibcon#wrote, iclass 36, count 2 2006.258.00:09:26.44#ibcon#about to read 3, iclass 36, count 2 2006.258.00:09:26.46#ibcon#read 3, iclass 36, count 2 2006.258.00:09:26.46#ibcon#about to read 4, iclass 36, count 2 2006.258.00:09:26.46#ibcon#read 4, iclass 36, count 2 2006.258.00:09:26.46#ibcon#about to read 5, iclass 36, count 2 2006.258.00:09:26.46#ibcon#read 5, iclass 36, count 2 2006.258.00:09:26.46#ibcon#about to read 6, iclass 36, count 2 2006.258.00:09:26.46#ibcon#read 6, iclass 36, count 2 2006.258.00:09:26.46#ibcon#end of sib2, iclass 36, count 2 2006.258.00:09:26.46#ibcon#*mode == 0, iclass 36, count 2 2006.258.00:09:26.46#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.258.00:09:26.46#ibcon#[25=AT07-04\r\n] 2006.258.00:09:26.46#ibcon#*before write, iclass 36, count 2 2006.258.00:09:26.46#ibcon#enter sib2, iclass 36, count 2 2006.258.00:09:26.46#ibcon#flushed, iclass 36, count 2 2006.258.00:09:26.46#ibcon#about to write, iclass 36, count 2 2006.258.00:09:26.46#ibcon#wrote, iclass 36, count 2 2006.258.00:09:26.46#ibcon#about to read 3, iclass 36, count 2 2006.258.00:09:26.49#ibcon#read 3, iclass 36, count 2 2006.258.00:09:26.51#ibcon#about to read 4, iclass 36, count 2 2006.258.00:09:26.51#ibcon#read 4, iclass 36, count 2 2006.258.00:09:26.51#ibcon#about to read 5, iclass 36, count 2 2006.258.00:09:26.52#ibcon#read 5, iclass 36, count 2 2006.258.00:09:26.52#ibcon#about to read 6, iclass 36, count 2 2006.258.00:09:26.52#ibcon#read 6, iclass 36, count 2 2006.258.00:09:26.52#ibcon#end of sib2, iclass 36, count 2 2006.258.00:09:26.52#ibcon#*after write, iclass 36, count 2 2006.258.00:09:26.52#ibcon#*before return 0, iclass 36, count 2 2006.258.00:09:26.52#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:26.52#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:26.52#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.258.00:09:26.52#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:26.52#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:26.63#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:26.63#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:26.63#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:09:26.63#ibcon#first serial, iclass 36, count 0 2006.258.00:09:26.63#ibcon#enter sib2, iclass 36, count 0 2006.258.00:09:26.63#ibcon#flushed, iclass 36, count 0 2006.258.00:09:26.63#ibcon#about to write, iclass 36, count 0 2006.258.00:09:26.63#ibcon#wrote, iclass 36, count 0 2006.258.00:09:26.63#ibcon#about to read 3, iclass 36, count 0 2006.258.00:09:26.65#ibcon#read 3, iclass 36, count 0 2006.258.00:09:26.65#ibcon#about to read 4, iclass 36, count 0 2006.258.00:09:26.65#ibcon#read 4, iclass 36, count 0 2006.258.00:09:26.65#ibcon#about to read 5, iclass 36, count 0 2006.258.00:09:26.65#ibcon#read 5, iclass 36, count 0 2006.258.00:09:26.65#ibcon#about to read 6, iclass 36, count 0 2006.258.00:09:26.65#ibcon#read 6, iclass 36, count 0 2006.258.00:09:26.65#ibcon#end of sib2, iclass 36, count 0 2006.258.00:09:26.65#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:09:26.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:09:26.65#ibcon#[25=USB\r\n] 2006.258.00:09:26.65#ibcon#*before write, iclass 36, count 0 2006.258.00:09:26.65#ibcon#enter sib2, iclass 36, count 0 2006.258.00:09:26.65#ibcon#flushed, iclass 36, count 0 2006.258.00:09:26.65#ibcon#about to write, iclass 36, count 0 2006.258.00:09:26.65#ibcon#wrote, iclass 36, count 0 2006.258.00:09:26.65#ibcon#about to read 3, iclass 36, count 0 2006.258.00:09:26.68#ibcon#read 3, iclass 36, count 0 2006.258.00:09:26.68#ibcon#about to read 4, iclass 36, count 0 2006.258.00:09:26.68#ibcon#read 4, iclass 36, count 0 2006.258.00:09:26.68#ibcon#about to read 5, iclass 36, count 0 2006.258.00:09:26.68#ibcon#read 5, iclass 36, count 0 2006.258.00:09:26.68#ibcon#about to read 6, iclass 36, count 0 2006.258.00:09:26.68#ibcon#read 6, iclass 36, count 0 2006.258.00:09:26.68#ibcon#end of sib2, iclass 36, count 0 2006.258.00:09:26.68#ibcon#*after write, iclass 36, count 0 2006.258.00:09:26.68#ibcon#*before return 0, iclass 36, count 0 2006.258.00:09:26.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:26.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:26.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:09:26.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:09:26.68$vck44/valo=8,884.99 2006.258.00:09:26.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.00:09:26.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.00:09:26.68#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:26.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:26.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:26.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:26.68#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:09:26.68#ibcon#first serial, iclass 38, count 0 2006.258.00:09:26.68#ibcon#enter sib2, iclass 38, count 0 2006.258.00:09:26.68#ibcon#flushed, iclass 38, count 0 2006.258.00:09:26.68#ibcon#about to write, iclass 38, count 0 2006.258.00:09:26.68#ibcon#wrote, iclass 38, count 0 2006.258.00:09:26.68#ibcon#about to read 3, iclass 38, count 0 2006.258.00:09:26.70#ibcon#read 3, iclass 38, count 0 2006.258.00:09:26.70#ibcon#about to read 4, iclass 38, count 0 2006.258.00:09:26.70#ibcon#read 4, iclass 38, count 0 2006.258.00:09:26.70#ibcon#about to read 5, iclass 38, count 0 2006.258.00:09:26.70#ibcon#read 5, iclass 38, count 0 2006.258.00:09:26.70#ibcon#about to read 6, iclass 38, count 0 2006.258.00:09:26.70#ibcon#read 6, iclass 38, count 0 2006.258.00:09:26.70#ibcon#end of sib2, iclass 38, count 0 2006.258.00:09:26.70#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:09:26.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:09:26.70#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:09:26.70#ibcon#*before write, iclass 38, count 0 2006.258.00:09:26.70#ibcon#enter sib2, iclass 38, count 0 2006.258.00:09:26.70#ibcon#flushed, iclass 38, count 0 2006.258.00:09:26.70#ibcon#about to write, iclass 38, count 0 2006.258.00:09:26.70#ibcon#wrote, iclass 38, count 0 2006.258.00:09:26.70#ibcon#about to read 3, iclass 38, count 0 2006.258.00:09:26.74#ibcon#read 3, iclass 38, count 0 2006.258.00:09:26.74#ibcon#about to read 4, iclass 38, count 0 2006.258.00:09:26.74#ibcon#read 4, iclass 38, count 0 2006.258.00:09:26.74#ibcon#about to read 5, iclass 38, count 0 2006.258.00:09:26.74#ibcon#read 5, iclass 38, count 0 2006.258.00:09:26.74#ibcon#about to read 6, iclass 38, count 0 2006.258.00:09:26.74#ibcon#read 6, iclass 38, count 0 2006.258.00:09:26.74#ibcon#end of sib2, iclass 38, count 0 2006.258.00:09:26.74#ibcon#*after write, iclass 38, count 0 2006.258.00:09:26.74#ibcon#*before return 0, iclass 38, count 0 2006.258.00:09:26.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:26.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:26.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:09:26.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:09:26.74$vck44/va=8,4 2006.258.00:09:26.74#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.258.00:09:26.74#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.258.00:09:26.74#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:26.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:09:26.80#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:09:26.80#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:09:26.80#ibcon#enter wrdev, iclass 40, count 2 2006.258.00:09:26.80#ibcon#first serial, iclass 40, count 2 2006.258.00:09:26.80#ibcon#enter sib2, iclass 40, count 2 2006.258.00:09:26.80#ibcon#flushed, iclass 40, count 2 2006.258.00:09:26.80#ibcon#about to write, iclass 40, count 2 2006.258.00:09:26.80#ibcon#wrote, iclass 40, count 2 2006.258.00:09:26.80#ibcon#about to read 3, iclass 40, count 2 2006.258.00:09:26.82#ibcon#read 3, iclass 40, count 2 2006.258.00:09:26.82#ibcon#about to read 4, iclass 40, count 2 2006.258.00:09:26.82#ibcon#read 4, iclass 40, count 2 2006.258.00:09:26.82#ibcon#about to read 5, iclass 40, count 2 2006.258.00:09:26.82#ibcon#read 5, iclass 40, count 2 2006.258.00:09:26.82#ibcon#about to read 6, iclass 40, count 2 2006.258.00:09:26.82#ibcon#read 6, iclass 40, count 2 2006.258.00:09:26.82#ibcon#end of sib2, iclass 40, count 2 2006.258.00:09:26.82#ibcon#*mode == 0, iclass 40, count 2 2006.258.00:09:26.82#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.258.00:09:26.82#ibcon#[25=AT08-04\r\n] 2006.258.00:09:26.82#ibcon#*before write, iclass 40, count 2 2006.258.00:09:26.82#ibcon#enter sib2, iclass 40, count 2 2006.258.00:09:26.82#ibcon#flushed, iclass 40, count 2 2006.258.00:09:26.82#ibcon#about to write, iclass 40, count 2 2006.258.00:09:26.82#ibcon#wrote, iclass 40, count 2 2006.258.00:09:26.82#ibcon#about to read 3, iclass 40, count 2 2006.258.00:09:26.85#ibcon#read 3, iclass 40, count 2 2006.258.00:09:26.85#ibcon#about to read 4, iclass 40, count 2 2006.258.00:09:26.85#ibcon#read 4, iclass 40, count 2 2006.258.00:09:26.85#ibcon#about to read 5, iclass 40, count 2 2006.258.00:09:26.85#ibcon#read 5, iclass 40, count 2 2006.258.00:09:26.85#ibcon#about to read 6, iclass 40, count 2 2006.258.00:09:26.85#ibcon#read 6, iclass 40, count 2 2006.258.00:09:26.85#ibcon#end of sib2, iclass 40, count 2 2006.258.00:09:26.85#ibcon#*after write, iclass 40, count 2 2006.258.00:09:26.85#ibcon#*before return 0, iclass 40, count 2 2006.258.00:09:26.85#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:09:26.85#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:09:26.85#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.258.00:09:26.85#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:26.85#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:09:26.97#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:09:26.97#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:09:26.97#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:09:26.97#ibcon#first serial, iclass 40, count 0 2006.258.00:09:26.97#ibcon#enter sib2, iclass 40, count 0 2006.258.00:09:26.97#ibcon#flushed, iclass 40, count 0 2006.258.00:09:26.97#ibcon#about to write, iclass 40, count 0 2006.258.00:09:26.97#ibcon#wrote, iclass 40, count 0 2006.258.00:09:26.97#ibcon#about to read 3, iclass 40, count 0 2006.258.00:09:26.99#ibcon#read 3, iclass 40, count 0 2006.258.00:09:26.99#ibcon#about to read 4, iclass 40, count 0 2006.258.00:09:26.99#ibcon#read 4, iclass 40, count 0 2006.258.00:09:26.99#ibcon#about to read 5, iclass 40, count 0 2006.258.00:09:26.99#ibcon#read 5, iclass 40, count 0 2006.258.00:09:26.99#ibcon#about to read 6, iclass 40, count 0 2006.258.00:09:26.99#ibcon#read 6, iclass 40, count 0 2006.258.00:09:26.99#ibcon#end of sib2, iclass 40, count 0 2006.258.00:09:26.99#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:09:26.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:09:26.99#ibcon#[25=USB\r\n] 2006.258.00:09:26.99#ibcon#*before write, iclass 40, count 0 2006.258.00:09:26.99#ibcon#enter sib2, iclass 40, count 0 2006.258.00:09:26.99#ibcon#flushed, iclass 40, count 0 2006.258.00:09:26.99#ibcon#about to write, iclass 40, count 0 2006.258.00:09:26.99#ibcon#wrote, iclass 40, count 0 2006.258.00:09:26.99#ibcon#about to read 3, iclass 40, count 0 2006.258.00:09:27.02#ibcon#read 3, iclass 40, count 0 2006.258.00:09:27.02#ibcon#about to read 4, iclass 40, count 0 2006.258.00:09:27.02#ibcon#read 4, iclass 40, count 0 2006.258.00:09:27.02#ibcon#about to read 5, iclass 40, count 0 2006.258.00:09:27.02#ibcon#read 5, iclass 40, count 0 2006.258.00:09:27.02#ibcon#about to read 6, iclass 40, count 0 2006.258.00:09:27.02#ibcon#read 6, iclass 40, count 0 2006.258.00:09:27.02#ibcon#end of sib2, iclass 40, count 0 2006.258.00:09:27.02#ibcon#*after write, iclass 40, count 0 2006.258.00:09:27.02#ibcon#*before return 0, iclass 40, count 0 2006.258.00:09:27.02#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:09:27.02#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:09:27.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:09:27.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:09:27.02$vck44/vblo=1,629.99 2006.258.00:09:27.02#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.258.00:09:27.02#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.258.00:09:27.02#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:27.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:09:27.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:09:27.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:09:27.02#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:09:27.02#ibcon#first serial, iclass 4, count 0 2006.258.00:09:27.02#ibcon#enter sib2, iclass 4, count 0 2006.258.00:09:27.02#ibcon#flushed, iclass 4, count 0 2006.258.00:09:27.02#ibcon#about to write, iclass 4, count 0 2006.258.00:09:27.02#ibcon#wrote, iclass 4, count 0 2006.258.00:09:27.02#ibcon#about to read 3, iclass 4, count 0 2006.258.00:09:27.04#ibcon#read 3, iclass 4, count 0 2006.258.00:09:27.04#ibcon#about to read 4, iclass 4, count 0 2006.258.00:09:27.04#ibcon#read 4, iclass 4, count 0 2006.258.00:09:27.04#ibcon#about to read 5, iclass 4, count 0 2006.258.00:09:27.04#ibcon#read 5, iclass 4, count 0 2006.258.00:09:27.04#ibcon#about to read 6, iclass 4, count 0 2006.258.00:09:27.04#ibcon#read 6, iclass 4, count 0 2006.258.00:09:27.04#ibcon#end of sib2, iclass 4, count 0 2006.258.00:09:27.04#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:09:27.04#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:09:27.04#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:09:27.04#ibcon#*before write, iclass 4, count 0 2006.258.00:09:27.04#ibcon#enter sib2, iclass 4, count 0 2006.258.00:09:27.04#ibcon#flushed, iclass 4, count 0 2006.258.00:09:27.04#ibcon#about to write, iclass 4, count 0 2006.258.00:09:27.04#ibcon#wrote, iclass 4, count 0 2006.258.00:09:27.04#ibcon#about to read 3, iclass 4, count 0 2006.258.00:09:27.08#ibcon#read 3, iclass 4, count 0 2006.258.00:09:27.08#ibcon#about to read 4, iclass 4, count 0 2006.258.00:09:27.08#ibcon#read 4, iclass 4, count 0 2006.258.00:09:27.08#ibcon#about to read 5, iclass 4, count 0 2006.258.00:09:27.08#ibcon#read 5, iclass 4, count 0 2006.258.00:09:27.08#ibcon#about to read 6, iclass 4, count 0 2006.258.00:09:27.08#ibcon#read 6, iclass 4, count 0 2006.258.00:09:27.08#ibcon#end of sib2, iclass 4, count 0 2006.258.00:09:27.08#ibcon#*after write, iclass 4, count 0 2006.258.00:09:27.08#ibcon#*before return 0, iclass 4, count 0 2006.258.00:09:27.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:09:27.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:09:27.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:09:27.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:09:27.08$vck44/vb=1,4 2006.258.00:09:27.08#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.258.00:09:27.08#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.258.00:09:27.08#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:27.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:09:27.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:09:27.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:09:27.08#ibcon#enter wrdev, iclass 6, count 2 2006.258.00:09:27.08#ibcon#first serial, iclass 6, count 2 2006.258.00:09:27.08#ibcon#enter sib2, iclass 6, count 2 2006.258.00:09:27.08#ibcon#flushed, iclass 6, count 2 2006.258.00:09:27.08#ibcon#about to write, iclass 6, count 2 2006.258.00:09:27.08#ibcon#wrote, iclass 6, count 2 2006.258.00:09:27.08#ibcon#about to read 3, iclass 6, count 2 2006.258.00:09:27.10#ibcon#read 3, iclass 6, count 2 2006.258.00:09:27.10#ibcon#about to read 4, iclass 6, count 2 2006.258.00:09:27.10#ibcon#read 4, iclass 6, count 2 2006.258.00:09:27.10#ibcon#about to read 5, iclass 6, count 2 2006.258.00:09:27.10#ibcon#read 5, iclass 6, count 2 2006.258.00:09:27.10#ibcon#about to read 6, iclass 6, count 2 2006.258.00:09:27.10#ibcon#read 6, iclass 6, count 2 2006.258.00:09:27.10#ibcon#end of sib2, iclass 6, count 2 2006.258.00:09:27.10#ibcon#*mode == 0, iclass 6, count 2 2006.258.00:09:27.10#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.258.00:09:27.10#ibcon#[27=AT01-04\r\n] 2006.258.00:09:27.10#ibcon#*before write, iclass 6, count 2 2006.258.00:09:27.10#ibcon#enter sib2, iclass 6, count 2 2006.258.00:09:27.10#ibcon#flushed, iclass 6, count 2 2006.258.00:09:27.10#ibcon#about to write, iclass 6, count 2 2006.258.00:09:27.10#ibcon#wrote, iclass 6, count 2 2006.258.00:09:27.10#ibcon#about to read 3, iclass 6, count 2 2006.258.00:09:27.13#ibcon#read 3, iclass 6, count 2 2006.258.00:09:27.13#ibcon#about to read 4, iclass 6, count 2 2006.258.00:09:27.13#ibcon#read 4, iclass 6, count 2 2006.258.00:09:27.13#ibcon#about to read 5, iclass 6, count 2 2006.258.00:09:27.13#ibcon#read 5, iclass 6, count 2 2006.258.00:09:27.13#ibcon#about to read 6, iclass 6, count 2 2006.258.00:09:27.13#ibcon#read 6, iclass 6, count 2 2006.258.00:09:27.13#ibcon#end of sib2, iclass 6, count 2 2006.258.00:09:27.13#ibcon#*after write, iclass 6, count 2 2006.258.00:09:27.13#ibcon#*before return 0, iclass 6, count 2 2006.258.00:09:27.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:09:27.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:09:27.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.258.00:09:27.13#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:27.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:09:27.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:09:27.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:09:27.25#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:09:27.25#ibcon#first serial, iclass 6, count 0 2006.258.00:09:27.25#ibcon#enter sib2, iclass 6, count 0 2006.258.00:09:27.25#ibcon#flushed, iclass 6, count 0 2006.258.00:09:27.25#ibcon#about to write, iclass 6, count 0 2006.258.00:09:27.25#ibcon#wrote, iclass 6, count 0 2006.258.00:09:27.25#ibcon#about to read 3, iclass 6, count 0 2006.258.00:09:27.27#ibcon#read 3, iclass 6, count 0 2006.258.00:09:27.27#ibcon#about to read 4, iclass 6, count 0 2006.258.00:09:27.27#ibcon#read 4, iclass 6, count 0 2006.258.00:09:27.27#ibcon#about to read 5, iclass 6, count 0 2006.258.00:09:27.27#ibcon#read 5, iclass 6, count 0 2006.258.00:09:27.27#ibcon#about to read 6, iclass 6, count 0 2006.258.00:09:27.27#ibcon#read 6, iclass 6, count 0 2006.258.00:09:27.27#ibcon#end of sib2, iclass 6, count 0 2006.258.00:09:27.27#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:09:27.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:09:27.27#ibcon#[27=USB\r\n] 2006.258.00:09:27.27#ibcon#*before write, iclass 6, count 0 2006.258.00:09:27.27#ibcon#enter sib2, iclass 6, count 0 2006.258.00:09:27.27#ibcon#flushed, iclass 6, count 0 2006.258.00:09:27.27#ibcon#about to write, iclass 6, count 0 2006.258.00:09:27.27#ibcon#wrote, iclass 6, count 0 2006.258.00:09:27.27#ibcon#about to read 3, iclass 6, count 0 2006.258.00:09:27.30#ibcon#read 3, iclass 6, count 0 2006.258.00:09:27.30#ibcon#about to read 4, iclass 6, count 0 2006.258.00:09:27.30#ibcon#read 4, iclass 6, count 0 2006.258.00:09:27.30#ibcon#about to read 5, iclass 6, count 0 2006.258.00:09:27.30#ibcon#read 5, iclass 6, count 0 2006.258.00:09:27.30#ibcon#about to read 6, iclass 6, count 0 2006.258.00:09:27.30#ibcon#read 6, iclass 6, count 0 2006.258.00:09:27.30#ibcon#end of sib2, iclass 6, count 0 2006.258.00:09:27.30#ibcon#*after write, iclass 6, count 0 2006.258.00:09:27.30#ibcon#*before return 0, iclass 6, count 0 2006.258.00:09:27.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:09:27.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:09:27.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:09:27.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:09:27.30$vck44/vblo=2,634.99 2006.258.00:09:27.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.258.00:09:27.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.258.00:09:27.30#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:27.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:27.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:27.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:27.30#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:09:27.30#ibcon#first serial, iclass 10, count 0 2006.258.00:09:27.30#ibcon#enter sib2, iclass 10, count 0 2006.258.00:09:27.30#ibcon#flushed, iclass 10, count 0 2006.258.00:09:27.30#ibcon#about to write, iclass 10, count 0 2006.258.00:09:27.30#ibcon#wrote, iclass 10, count 0 2006.258.00:09:27.30#ibcon#about to read 3, iclass 10, count 0 2006.258.00:09:27.32#ibcon#read 3, iclass 10, count 0 2006.258.00:09:27.32#ibcon#about to read 4, iclass 10, count 0 2006.258.00:09:27.32#ibcon#read 4, iclass 10, count 0 2006.258.00:09:27.32#ibcon#about to read 5, iclass 10, count 0 2006.258.00:09:27.32#ibcon#read 5, iclass 10, count 0 2006.258.00:09:27.32#ibcon#about to read 6, iclass 10, count 0 2006.258.00:09:27.32#ibcon#read 6, iclass 10, count 0 2006.258.00:09:27.32#ibcon#end of sib2, iclass 10, count 0 2006.258.00:09:27.32#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:09:27.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:09:27.32#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:09:27.32#ibcon#*before write, iclass 10, count 0 2006.258.00:09:27.32#ibcon#enter sib2, iclass 10, count 0 2006.258.00:09:27.32#ibcon#flushed, iclass 10, count 0 2006.258.00:09:27.32#ibcon#about to write, iclass 10, count 0 2006.258.00:09:27.32#ibcon#wrote, iclass 10, count 0 2006.258.00:09:27.32#ibcon#about to read 3, iclass 10, count 0 2006.258.00:09:27.36#ibcon#read 3, iclass 10, count 0 2006.258.00:09:27.36#ibcon#about to read 4, iclass 10, count 0 2006.258.00:09:27.36#ibcon#read 4, iclass 10, count 0 2006.258.00:09:27.36#ibcon#about to read 5, iclass 10, count 0 2006.258.00:09:27.36#ibcon#read 5, iclass 10, count 0 2006.258.00:09:27.36#ibcon#about to read 6, iclass 10, count 0 2006.258.00:09:27.36#ibcon#read 6, iclass 10, count 0 2006.258.00:09:27.36#ibcon#end of sib2, iclass 10, count 0 2006.258.00:09:27.36#ibcon#*after write, iclass 10, count 0 2006.258.00:09:27.36#ibcon#*before return 0, iclass 10, count 0 2006.258.00:09:27.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:27.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:09:27.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:09:27.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:09:27.36$vck44/vb=2,5 2006.258.00:09:27.36#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.258.00:09:27.36#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.258.00:09:27.36#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:27.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:27.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:27.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:27.42#ibcon#enter wrdev, iclass 12, count 2 2006.258.00:09:27.42#ibcon#first serial, iclass 12, count 2 2006.258.00:09:27.42#ibcon#enter sib2, iclass 12, count 2 2006.258.00:09:27.42#ibcon#flushed, iclass 12, count 2 2006.258.00:09:27.42#ibcon#about to write, iclass 12, count 2 2006.258.00:09:27.42#ibcon#wrote, iclass 12, count 2 2006.258.00:09:27.42#ibcon#about to read 3, iclass 12, count 2 2006.258.00:09:27.44#ibcon#read 3, iclass 12, count 2 2006.258.00:09:27.44#ibcon#about to read 4, iclass 12, count 2 2006.258.00:09:27.44#ibcon#read 4, iclass 12, count 2 2006.258.00:09:27.44#ibcon#about to read 5, iclass 12, count 2 2006.258.00:09:27.44#ibcon#read 5, iclass 12, count 2 2006.258.00:09:27.44#ibcon#about to read 6, iclass 12, count 2 2006.258.00:09:27.44#ibcon#read 6, iclass 12, count 2 2006.258.00:09:27.44#ibcon#end of sib2, iclass 12, count 2 2006.258.00:09:27.44#ibcon#*mode == 0, iclass 12, count 2 2006.258.00:09:27.44#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.258.00:09:27.44#ibcon#[27=AT02-05\r\n] 2006.258.00:09:27.44#ibcon#*before write, iclass 12, count 2 2006.258.00:09:27.44#ibcon#enter sib2, iclass 12, count 2 2006.258.00:09:27.44#ibcon#flushed, iclass 12, count 2 2006.258.00:09:27.44#ibcon#about to write, iclass 12, count 2 2006.258.00:09:27.44#ibcon#wrote, iclass 12, count 2 2006.258.00:09:27.44#ibcon#about to read 3, iclass 12, count 2 2006.258.00:09:27.47#ibcon#read 3, iclass 12, count 2 2006.258.00:09:27.47#ibcon#about to read 4, iclass 12, count 2 2006.258.00:09:27.47#ibcon#read 4, iclass 12, count 2 2006.258.00:09:27.47#ibcon#about to read 5, iclass 12, count 2 2006.258.00:09:27.47#ibcon#read 5, iclass 12, count 2 2006.258.00:09:27.47#ibcon#about to read 6, iclass 12, count 2 2006.258.00:09:27.47#ibcon#read 6, iclass 12, count 2 2006.258.00:09:27.47#ibcon#end of sib2, iclass 12, count 2 2006.258.00:09:27.47#ibcon#*after write, iclass 12, count 2 2006.258.00:09:27.47#ibcon#*before return 0, iclass 12, count 2 2006.258.00:09:27.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:27.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:09:27.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.258.00:09:27.56#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:27.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:27.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:27.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:27.68#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:09:27.68#ibcon#first serial, iclass 12, count 0 2006.258.00:09:27.68#ibcon#enter sib2, iclass 12, count 0 2006.258.00:09:27.68#ibcon#flushed, iclass 12, count 0 2006.258.00:09:27.68#ibcon#about to write, iclass 12, count 0 2006.258.00:09:27.68#ibcon#wrote, iclass 12, count 0 2006.258.00:09:27.68#ibcon#about to read 3, iclass 12, count 0 2006.258.00:09:27.70#ibcon#read 3, iclass 12, count 0 2006.258.00:09:27.70#ibcon#about to read 4, iclass 12, count 0 2006.258.00:09:27.70#ibcon#read 4, iclass 12, count 0 2006.258.00:09:27.70#ibcon#about to read 5, iclass 12, count 0 2006.258.00:09:27.70#ibcon#read 5, iclass 12, count 0 2006.258.00:09:27.70#ibcon#about to read 6, iclass 12, count 0 2006.258.00:09:27.70#ibcon#read 6, iclass 12, count 0 2006.258.00:09:27.70#ibcon#end of sib2, iclass 12, count 0 2006.258.00:09:27.70#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:09:27.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:09:27.70#ibcon#[27=USB\r\n] 2006.258.00:09:27.70#ibcon#*before write, iclass 12, count 0 2006.258.00:09:27.70#ibcon#enter sib2, iclass 12, count 0 2006.258.00:09:27.70#ibcon#flushed, iclass 12, count 0 2006.258.00:09:27.70#ibcon#about to write, iclass 12, count 0 2006.258.00:09:27.70#ibcon#wrote, iclass 12, count 0 2006.258.00:09:27.70#ibcon#about to read 3, iclass 12, count 0 2006.258.00:09:27.73#ibcon#read 3, iclass 12, count 0 2006.258.00:09:27.73#ibcon#about to read 4, iclass 12, count 0 2006.258.00:09:27.73#ibcon#read 4, iclass 12, count 0 2006.258.00:09:27.73#ibcon#about to read 5, iclass 12, count 0 2006.258.00:09:27.73#ibcon#read 5, iclass 12, count 0 2006.258.00:09:27.73#ibcon#about to read 6, iclass 12, count 0 2006.258.00:09:27.73#ibcon#read 6, iclass 12, count 0 2006.258.00:09:27.73#ibcon#end of sib2, iclass 12, count 0 2006.258.00:09:27.73#ibcon#*after write, iclass 12, count 0 2006.258.00:09:27.73#ibcon#*before return 0, iclass 12, count 0 2006.258.00:09:27.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:27.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:09:27.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:09:27.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:09:27.73$vck44/vblo=3,649.99 2006.258.00:09:27.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.00:09:27.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.00:09:27.73#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:27.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:27.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:27.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:27.73#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:09:27.73#ibcon#first serial, iclass 14, count 0 2006.258.00:09:27.73#ibcon#enter sib2, iclass 14, count 0 2006.258.00:09:27.73#ibcon#flushed, iclass 14, count 0 2006.258.00:09:27.73#ibcon#about to write, iclass 14, count 0 2006.258.00:09:27.73#ibcon#wrote, iclass 14, count 0 2006.258.00:09:27.73#ibcon#about to read 3, iclass 14, count 0 2006.258.00:09:27.75#ibcon#read 3, iclass 14, count 0 2006.258.00:09:27.75#ibcon#about to read 4, iclass 14, count 0 2006.258.00:09:27.75#ibcon#read 4, iclass 14, count 0 2006.258.00:09:27.75#ibcon#about to read 5, iclass 14, count 0 2006.258.00:09:27.75#ibcon#read 5, iclass 14, count 0 2006.258.00:09:27.75#ibcon#about to read 6, iclass 14, count 0 2006.258.00:09:27.75#ibcon#read 6, iclass 14, count 0 2006.258.00:09:27.75#ibcon#end of sib2, iclass 14, count 0 2006.258.00:09:27.75#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:09:27.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:09:27.75#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:09:27.75#ibcon#*before write, iclass 14, count 0 2006.258.00:09:27.75#ibcon#enter sib2, iclass 14, count 0 2006.258.00:09:27.75#ibcon#flushed, iclass 14, count 0 2006.258.00:09:27.75#ibcon#about to write, iclass 14, count 0 2006.258.00:09:27.75#ibcon#wrote, iclass 14, count 0 2006.258.00:09:27.75#ibcon#about to read 3, iclass 14, count 0 2006.258.00:09:27.79#ibcon#read 3, iclass 14, count 0 2006.258.00:09:27.79#ibcon#about to read 4, iclass 14, count 0 2006.258.00:09:27.79#ibcon#read 4, iclass 14, count 0 2006.258.00:09:27.79#ibcon#about to read 5, iclass 14, count 0 2006.258.00:09:27.79#ibcon#read 5, iclass 14, count 0 2006.258.00:09:27.79#ibcon#about to read 6, iclass 14, count 0 2006.258.00:09:27.79#ibcon#read 6, iclass 14, count 0 2006.258.00:09:27.79#ibcon#end of sib2, iclass 14, count 0 2006.258.00:09:27.79#ibcon#*after write, iclass 14, count 0 2006.258.00:09:27.79#ibcon#*before return 0, iclass 14, count 0 2006.258.00:09:27.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:27.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:09:27.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:09:27.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:09:27.79$vck44/vb=3,4 2006.258.00:09:27.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.258.00:09:27.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.258.00:09:27.79#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:27.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:27.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:27.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:27.85#ibcon#enter wrdev, iclass 16, count 2 2006.258.00:09:27.85#ibcon#first serial, iclass 16, count 2 2006.258.00:09:27.85#ibcon#enter sib2, iclass 16, count 2 2006.258.00:09:27.85#ibcon#flushed, iclass 16, count 2 2006.258.00:09:27.85#ibcon#about to write, iclass 16, count 2 2006.258.00:09:27.85#ibcon#wrote, iclass 16, count 2 2006.258.00:09:27.85#ibcon#about to read 3, iclass 16, count 2 2006.258.00:09:27.87#ibcon#read 3, iclass 16, count 2 2006.258.00:09:27.87#ibcon#about to read 4, iclass 16, count 2 2006.258.00:09:27.87#ibcon#read 4, iclass 16, count 2 2006.258.00:09:27.87#ibcon#about to read 5, iclass 16, count 2 2006.258.00:09:27.87#ibcon#read 5, iclass 16, count 2 2006.258.00:09:27.87#ibcon#about to read 6, iclass 16, count 2 2006.258.00:09:27.87#ibcon#read 6, iclass 16, count 2 2006.258.00:09:27.87#ibcon#end of sib2, iclass 16, count 2 2006.258.00:09:27.87#ibcon#*mode == 0, iclass 16, count 2 2006.258.00:09:27.87#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.258.00:09:27.87#ibcon#[27=AT03-04\r\n] 2006.258.00:09:27.87#ibcon#*before write, iclass 16, count 2 2006.258.00:09:27.87#ibcon#enter sib2, iclass 16, count 2 2006.258.00:09:27.87#ibcon#flushed, iclass 16, count 2 2006.258.00:09:27.87#ibcon#about to write, iclass 16, count 2 2006.258.00:09:27.87#ibcon#wrote, iclass 16, count 2 2006.258.00:09:27.87#ibcon#about to read 3, iclass 16, count 2 2006.258.00:09:27.90#ibcon#read 3, iclass 16, count 2 2006.258.00:09:27.90#ibcon#about to read 4, iclass 16, count 2 2006.258.00:09:27.90#ibcon#read 4, iclass 16, count 2 2006.258.00:09:27.90#ibcon#about to read 5, iclass 16, count 2 2006.258.00:09:27.90#ibcon#read 5, iclass 16, count 2 2006.258.00:09:27.90#ibcon#about to read 6, iclass 16, count 2 2006.258.00:09:27.90#ibcon#read 6, iclass 16, count 2 2006.258.00:09:27.90#ibcon#end of sib2, iclass 16, count 2 2006.258.00:09:27.90#ibcon#*after write, iclass 16, count 2 2006.258.00:09:27.90#ibcon#*before return 0, iclass 16, count 2 2006.258.00:09:27.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:27.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:09:27.90#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.258.00:09:27.90#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:27.90#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:28.02#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:28.02#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:28.02#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:09:28.02#ibcon#first serial, iclass 16, count 0 2006.258.00:09:28.02#ibcon#enter sib2, iclass 16, count 0 2006.258.00:09:28.02#ibcon#flushed, iclass 16, count 0 2006.258.00:09:28.02#ibcon#about to write, iclass 16, count 0 2006.258.00:09:28.02#ibcon#wrote, iclass 16, count 0 2006.258.00:09:28.02#ibcon#about to read 3, iclass 16, count 0 2006.258.00:09:28.04#ibcon#read 3, iclass 16, count 0 2006.258.00:09:28.04#ibcon#about to read 4, iclass 16, count 0 2006.258.00:09:28.04#ibcon#read 4, iclass 16, count 0 2006.258.00:09:28.04#ibcon#about to read 5, iclass 16, count 0 2006.258.00:09:28.04#ibcon#read 5, iclass 16, count 0 2006.258.00:09:28.04#ibcon#about to read 6, iclass 16, count 0 2006.258.00:09:28.04#ibcon#read 6, iclass 16, count 0 2006.258.00:09:28.04#ibcon#end of sib2, iclass 16, count 0 2006.258.00:09:28.04#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:09:28.04#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:09:28.04#ibcon#[27=USB\r\n] 2006.258.00:09:28.04#ibcon#*before write, iclass 16, count 0 2006.258.00:09:28.04#ibcon#enter sib2, iclass 16, count 0 2006.258.00:09:28.04#ibcon#flushed, iclass 16, count 0 2006.258.00:09:28.04#ibcon#about to write, iclass 16, count 0 2006.258.00:09:28.04#ibcon#wrote, iclass 16, count 0 2006.258.00:09:28.04#ibcon#about to read 3, iclass 16, count 0 2006.258.00:09:28.07#ibcon#read 3, iclass 16, count 0 2006.258.00:09:28.07#ibcon#about to read 4, iclass 16, count 0 2006.258.00:09:28.07#ibcon#read 4, iclass 16, count 0 2006.258.00:09:28.07#ibcon#about to read 5, iclass 16, count 0 2006.258.00:09:28.07#ibcon#read 5, iclass 16, count 0 2006.258.00:09:28.07#ibcon#about to read 6, iclass 16, count 0 2006.258.00:09:28.07#ibcon#read 6, iclass 16, count 0 2006.258.00:09:28.07#ibcon#end of sib2, iclass 16, count 0 2006.258.00:09:28.07#ibcon#*after write, iclass 16, count 0 2006.258.00:09:28.07#ibcon#*before return 0, iclass 16, count 0 2006.258.00:09:28.07#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:28.07#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:09:28.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:09:28.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:09:28.07$vck44/vblo=4,679.99 2006.258.00:09:28.07#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.00:09:28.07#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.00:09:28.07#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:28.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:28.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:28.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:28.07#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:09:28.07#ibcon#first serial, iclass 18, count 0 2006.258.00:09:28.07#ibcon#enter sib2, iclass 18, count 0 2006.258.00:09:28.07#ibcon#flushed, iclass 18, count 0 2006.258.00:09:28.07#ibcon#about to write, iclass 18, count 0 2006.258.00:09:28.07#ibcon#wrote, iclass 18, count 0 2006.258.00:09:28.07#ibcon#about to read 3, iclass 18, count 0 2006.258.00:09:28.09#ibcon#read 3, iclass 18, count 0 2006.258.00:09:28.09#ibcon#about to read 4, iclass 18, count 0 2006.258.00:09:28.09#ibcon#read 4, iclass 18, count 0 2006.258.00:09:28.09#ibcon#about to read 5, iclass 18, count 0 2006.258.00:09:28.09#ibcon#read 5, iclass 18, count 0 2006.258.00:09:28.09#ibcon#about to read 6, iclass 18, count 0 2006.258.00:09:28.09#ibcon#read 6, iclass 18, count 0 2006.258.00:09:28.09#ibcon#end of sib2, iclass 18, count 0 2006.258.00:09:28.09#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:09:28.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:09:28.09#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:09:28.09#ibcon#*before write, iclass 18, count 0 2006.258.00:09:28.09#ibcon#enter sib2, iclass 18, count 0 2006.258.00:09:28.09#ibcon#flushed, iclass 18, count 0 2006.258.00:09:28.09#ibcon#about to write, iclass 18, count 0 2006.258.00:09:28.09#ibcon#wrote, iclass 18, count 0 2006.258.00:09:28.09#ibcon#about to read 3, iclass 18, count 0 2006.258.00:09:28.13#ibcon#read 3, iclass 18, count 0 2006.258.00:09:28.13#ibcon#about to read 4, iclass 18, count 0 2006.258.00:09:28.13#ibcon#read 4, iclass 18, count 0 2006.258.00:09:28.13#ibcon#about to read 5, iclass 18, count 0 2006.258.00:09:28.13#ibcon#read 5, iclass 18, count 0 2006.258.00:09:28.13#ibcon#about to read 6, iclass 18, count 0 2006.258.00:09:28.13#ibcon#read 6, iclass 18, count 0 2006.258.00:09:28.13#ibcon#end of sib2, iclass 18, count 0 2006.258.00:09:28.13#ibcon#*after write, iclass 18, count 0 2006.258.00:09:28.13#ibcon#*before return 0, iclass 18, count 0 2006.258.00:09:28.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:28.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:09:28.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:09:28.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:09:28.13$vck44/vb=4,5 2006.258.00:09:28.13#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.00:09:28.13#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.00:09:28.13#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:28.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:28.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:28.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:28.19#ibcon#enter wrdev, iclass 20, count 2 2006.258.00:09:28.19#ibcon#first serial, iclass 20, count 2 2006.258.00:09:28.19#ibcon#enter sib2, iclass 20, count 2 2006.258.00:09:28.19#ibcon#flushed, iclass 20, count 2 2006.258.00:09:28.19#ibcon#about to write, iclass 20, count 2 2006.258.00:09:28.19#ibcon#wrote, iclass 20, count 2 2006.258.00:09:28.19#ibcon#about to read 3, iclass 20, count 2 2006.258.00:09:28.21#ibcon#read 3, iclass 20, count 2 2006.258.00:09:28.21#ibcon#about to read 4, iclass 20, count 2 2006.258.00:09:28.21#ibcon#read 4, iclass 20, count 2 2006.258.00:09:28.21#ibcon#about to read 5, iclass 20, count 2 2006.258.00:09:28.21#ibcon#read 5, iclass 20, count 2 2006.258.00:09:28.21#ibcon#about to read 6, iclass 20, count 2 2006.258.00:09:28.21#ibcon#read 6, iclass 20, count 2 2006.258.00:09:28.21#ibcon#end of sib2, iclass 20, count 2 2006.258.00:09:28.21#ibcon#*mode == 0, iclass 20, count 2 2006.258.00:09:28.21#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.00:09:28.21#ibcon#[27=AT04-05\r\n] 2006.258.00:09:28.21#ibcon#*before write, iclass 20, count 2 2006.258.00:09:28.21#ibcon#enter sib2, iclass 20, count 2 2006.258.00:09:28.21#ibcon#flushed, iclass 20, count 2 2006.258.00:09:28.21#ibcon#about to write, iclass 20, count 2 2006.258.00:09:28.21#ibcon#wrote, iclass 20, count 2 2006.258.00:09:28.21#ibcon#about to read 3, iclass 20, count 2 2006.258.00:09:28.24#ibcon#read 3, iclass 20, count 2 2006.258.00:09:28.24#ibcon#about to read 4, iclass 20, count 2 2006.258.00:09:28.24#ibcon#read 4, iclass 20, count 2 2006.258.00:09:28.24#ibcon#about to read 5, iclass 20, count 2 2006.258.00:09:28.24#ibcon#read 5, iclass 20, count 2 2006.258.00:09:28.24#ibcon#about to read 6, iclass 20, count 2 2006.258.00:09:28.24#ibcon#read 6, iclass 20, count 2 2006.258.00:09:28.24#ibcon#end of sib2, iclass 20, count 2 2006.258.00:09:28.24#ibcon#*after write, iclass 20, count 2 2006.258.00:09:28.24#ibcon#*before return 0, iclass 20, count 2 2006.258.00:09:28.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:28.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:09:28.24#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.00:09:28.24#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:28.24#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:28.36#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:28.36#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:28.36#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:09:28.36#ibcon#first serial, iclass 20, count 0 2006.258.00:09:28.36#ibcon#enter sib2, iclass 20, count 0 2006.258.00:09:28.36#ibcon#flushed, iclass 20, count 0 2006.258.00:09:28.36#ibcon#about to write, iclass 20, count 0 2006.258.00:09:28.36#ibcon#wrote, iclass 20, count 0 2006.258.00:09:28.36#ibcon#about to read 3, iclass 20, count 0 2006.258.00:09:28.38#ibcon#read 3, iclass 20, count 0 2006.258.00:09:28.38#ibcon#about to read 4, iclass 20, count 0 2006.258.00:09:28.38#ibcon#read 4, iclass 20, count 0 2006.258.00:09:28.38#ibcon#about to read 5, iclass 20, count 0 2006.258.00:09:28.38#ibcon#read 5, iclass 20, count 0 2006.258.00:09:28.38#ibcon#about to read 6, iclass 20, count 0 2006.258.00:09:28.38#ibcon#read 6, iclass 20, count 0 2006.258.00:09:28.38#ibcon#end of sib2, iclass 20, count 0 2006.258.00:09:28.38#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:09:28.38#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:09:28.38#ibcon#[27=USB\r\n] 2006.258.00:09:28.38#ibcon#*before write, iclass 20, count 0 2006.258.00:09:28.38#ibcon#enter sib2, iclass 20, count 0 2006.258.00:09:28.38#ibcon#flushed, iclass 20, count 0 2006.258.00:09:28.38#ibcon#about to write, iclass 20, count 0 2006.258.00:09:28.38#ibcon#wrote, iclass 20, count 0 2006.258.00:09:28.38#ibcon#about to read 3, iclass 20, count 0 2006.258.00:09:28.41#ibcon#read 3, iclass 20, count 0 2006.258.00:09:28.41#ibcon#about to read 4, iclass 20, count 0 2006.258.00:09:28.41#ibcon#read 4, iclass 20, count 0 2006.258.00:09:28.41#ibcon#about to read 5, iclass 20, count 0 2006.258.00:09:28.41#ibcon#read 5, iclass 20, count 0 2006.258.00:09:28.41#ibcon#about to read 6, iclass 20, count 0 2006.258.00:09:28.41#ibcon#read 6, iclass 20, count 0 2006.258.00:09:28.41#ibcon#end of sib2, iclass 20, count 0 2006.258.00:09:28.41#ibcon#*after write, iclass 20, count 0 2006.258.00:09:28.41#ibcon#*before return 0, iclass 20, count 0 2006.258.00:09:28.41#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:28.41#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:09:28.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:09:28.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:09:28.41$vck44/vblo=5,709.99 2006.258.00:09:28.41#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.00:09:28.41#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.00:09:28.41#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:28.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:28.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:28.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:28.41#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:09:28.41#ibcon#first serial, iclass 22, count 0 2006.258.00:09:28.41#ibcon#enter sib2, iclass 22, count 0 2006.258.00:09:28.41#ibcon#flushed, iclass 22, count 0 2006.258.00:09:28.41#ibcon#about to write, iclass 22, count 0 2006.258.00:09:28.41#ibcon#wrote, iclass 22, count 0 2006.258.00:09:28.41#ibcon#about to read 3, iclass 22, count 0 2006.258.00:09:28.43#ibcon#read 3, iclass 22, count 0 2006.258.00:09:28.43#ibcon#about to read 4, iclass 22, count 0 2006.258.00:09:28.43#ibcon#read 4, iclass 22, count 0 2006.258.00:09:28.43#ibcon#about to read 5, iclass 22, count 0 2006.258.00:09:28.43#ibcon#read 5, iclass 22, count 0 2006.258.00:09:28.43#ibcon#about to read 6, iclass 22, count 0 2006.258.00:09:28.43#ibcon#read 6, iclass 22, count 0 2006.258.00:09:28.43#ibcon#end of sib2, iclass 22, count 0 2006.258.00:09:28.43#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:09:28.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:09:28.43#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:09:28.43#ibcon#*before write, iclass 22, count 0 2006.258.00:09:28.43#ibcon#enter sib2, iclass 22, count 0 2006.258.00:09:28.43#ibcon#flushed, iclass 22, count 0 2006.258.00:09:28.43#ibcon#about to write, iclass 22, count 0 2006.258.00:09:28.43#ibcon#wrote, iclass 22, count 0 2006.258.00:09:28.43#ibcon#about to read 3, iclass 22, count 0 2006.258.00:09:28.47#ibcon#read 3, iclass 22, count 0 2006.258.00:09:28.47#ibcon#about to read 4, iclass 22, count 0 2006.258.00:09:28.47#ibcon#read 4, iclass 22, count 0 2006.258.00:09:28.47#ibcon#about to read 5, iclass 22, count 0 2006.258.00:09:28.47#ibcon#read 5, iclass 22, count 0 2006.258.00:09:28.47#ibcon#about to read 6, iclass 22, count 0 2006.258.00:09:28.47#ibcon#read 6, iclass 22, count 0 2006.258.00:09:28.47#ibcon#end of sib2, iclass 22, count 0 2006.258.00:09:28.47#ibcon#*after write, iclass 22, count 0 2006.258.00:09:28.47#ibcon#*before return 0, iclass 22, count 0 2006.258.00:09:28.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:28.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:09:28.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:09:28.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:09:28.47$vck44/vb=5,4 2006.258.00:09:28.47#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.00:09:28.47#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.00:09:28.47#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:28.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:28.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:28.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:28.53#ibcon#enter wrdev, iclass 24, count 2 2006.258.00:09:28.53#ibcon#first serial, iclass 24, count 2 2006.258.00:09:28.53#ibcon#enter sib2, iclass 24, count 2 2006.258.00:09:28.53#ibcon#flushed, iclass 24, count 2 2006.258.00:09:28.53#ibcon#about to write, iclass 24, count 2 2006.258.00:09:28.53#ibcon#wrote, iclass 24, count 2 2006.258.00:09:28.53#ibcon#about to read 3, iclass 24, count 2 2006.258.00:09:28.55#ibcon#read 3, iclass 24, count 2 2006.258.00:09:28.55#ibcon#about to read 4, iclass 24, count 2 2006.258.00:09:28.55#ibcon#read 4, iclass 24, count 2 2006.258.00:09:28.55#ibcon#about to read 5, iclass 24, count 2 2006.258.00:09:28.55#ibcon#read 5, iclass 24, count 2 2006.258.00:09:28.55#ibcon#about to read 6, iclass 24, count 2 2006.258.00:09:28.55#ibcon#read 6, iclass 24, count 2 2006.258.00:09:28.55#ibcon#end of sib2, iclass 24, count 2 2006.258.00:09:28.55#ibcon#*mode == 0, iclass 24, count 2 2006.258.00:09:28.55#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.00:09:28.55#ibcon#[27=AT05-04\r\n] 2006.258.00:09:28.55#ibcon#*before write, iclass 24, count 2 2006.258.00:09:28.55#ibcon#enter sib2, iclass 24, count 2 2006.258.00:09:28.55#ibcon#flushed, iclass 24, count 2 2006.258.00:09:28.55#ibcon#about to write, iclass 24, count 2 2006.258.00:09:28.55#ibcon#wrote, iclass 24, count 2 2006.258.00:09:28.55#ibcon#about to read 3, iclass 24, count 2 2006.258.00:09:28.58#ibcon#read 3, iclass 24, count 2 2006.258.00:09:28.61#ibcon#about to read 4, iclass 24, count 2 2006.258.00:09:28.61#ibcon#read 4, iclass 24, count 2 2006.258.00:09:28.61#ibcon#about to read 5, iclass 24, count 2 2006.258.00:09:28.61#ibcon#read 5, iclass 24, count 2 2006.258.00:09:28.61#ibcon#about to read 6, iclass 24, count 2 2006.258.00:09:28.61#ibcon#read 6, iclass 24, count 2 2006.258.00:09:28.61#ibcon#end of sib2, iclass 24, count 2 2006.258.00:09:28.61#ibcon#*after write, iclass 24, count 2 2006.258.00:09:28.61#ibcon#*before return 0, iclass 24, count 2 2006.258.00:09:28.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:28.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:09:28.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.00:09:28.61#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:28.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:28.72#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:28.72#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:28.72#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:09:28.72#ibcon#first serial, iclass 24, count 0 2006.258.00:09:28.72#ibcon#enter sib2, iclass 24, count 0 2006.258.00:09:28.72#ibcon#flushed, iclass 24, count 0 2006.258.00:09:28.72#ibcon#about to write, iclass 24, count 0 2006.258.00:09:28.72#ibcon#wrote, iclass 24, count 0 2006.258.00:09:28.72#ibcon#about to read 3, iclass 24, count 0 2006.258.00:09:28.74#ibcon#read 3, iclass 24, count 0 2006.258.00:09:28.74#ibcon#about to read 4, iclass 24, count 0 2006.258.00:09:28.74#ibcon#read 4, iclass 24, count 0 2006.258.00:09:28.74#ibcon#about to read 5, iclass 24, count 0 2006.258.00:09:28.74#ibcon#read 5, iclass 24, count 0 2006.258.00:09:28.74#ibcon#about to read 6, iclass 24, count 0 2006.258.00:09:28.74#ibcon#read 6, iclass 24, count 0 2006.258.00:09:28.74#ibcon#end of sib2, iclass 24, count 0 2006.258.00:09:28.74#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:09:28.74#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:09:28.74#ibcon#[27=USB\r\n] 2006.258.00:09:28.74#ibcon#*before write, iclass 24, count 0 2006.258.00:09:28.74#ibcon#enter sib2, iclass 24, count 0 2006.258.00:09:28.74#ibcon#flushed, iclass 24, count 0 2006.258.00:09:28.74#ibcon#about to write, iclass 24, count 0 2006.258.00:09:28.74#ibcon#wrote, iclass 24, count 0 2006.258.00:09:28.74#ibcon#about to read 3, iclass 24, count 0 2006.258.00:09:28.77#ibcon#read 3, iclass 24, count 0 2006.258.00:09:28.77#ibcon#about to read 4, iclass 24, count 0 2006.258.00:09:28.77#ibcon#read 4, iclass 24, count 0 2006.258.00:09:28.77#ibcon#about to read 5, iclass 24, count 0 2006.258.00:09:28.77#ibcon#read 5, iclass 24, count 0 2006.258.00:09:28.77#ibcon#about to read 6, iclass 24, count 0 2006.258.00:09:28.77#ibcon#read 6, iclass 24, count 0 2006.258.00:09:28.77#ibcon#end of sib2, iclass 24, count 0 2006.258.00:09:28.77#ibcon#*after write, iclass 24, count 0 2006.258.00:09:28.77#ibcon#*before return 0, iclass 24, count 0 2006.258.00:09:28.77#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:28.77#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:09:28.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:09:28.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:09:28.77$vck44/vblo=6,719.99 2006.258.00:09:28.77#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.00:09:28.77#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.00:09:28.77#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:28.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:28.77#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:28.77#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:28.77#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:09:28.77#ibcon#first serial, iclass 26, count 0 2006.258.00:09:28.77#ibcon#enter sib2, iclass 26, count 0 2006.258.00:09:28.77#ibcon#flushed, iclass 26, count 0 2006.258.00:09:28.77#ibcon#about to write, iclass 26, count 0 2006.258.00:09:28.77#ibcon#wrote, iclass 26, count 0 2006.258.00:09:28.77#ibcon#about to read 3, iclass 26, count 0 2006.258.00:09:28.79#ibcon#read 3, iclass 26, count 0 2006.258.00:09:28.79#ibcon#about to read 4, iclass 26, count 0 2006.258.00:09:28.79#ibcon#read 4, iclass 26, count 0 2006.258.00:09:28.79#ibcon#about to read 5, iclass 26, count 0 2006.258.00:09:28.79#ibcon#read 5, iclass 26, count 0 2006.258.00:09:28.79#ibcon#about to read 6, iclass 26, count 0 2006.258.00:09:28.79#ibcon#read 6, iclass 26, count 0 2006.258.00:09:28.79#ibcon#end of sib2, iclass 26, count 0 2006.258.00:09:28.79#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:09:28.79#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:09:28.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:09:28.79#ibcon#*before write, iclass 26, count 0 2006.258.00:09:28.79#ibcon#enter sib2, iclass 26, count 0 2006.258.00:09:28.79#ibcon#flushed, iclass 26, count 0 2006.258.00:09:28.79#ibcon#about to write, iclass 26, count 0 2006.258.00:09:28.79#ibcon#wrote, iclass 26, count 0 2006.258.00:09:28.79#ibcon#about to read 3, iclass 26, count 0 2006.258.00:09:28.83#ibcon#read 3, iclass 26, count 0 2006.258.00:09:28.83#ibcon#about to read 4, iclass 26, count 0 2006.258.00:09:28.83#ibcon#read 4, iclass 26, count 0 2006.258.00:09:28.83#ibcon#about to read 5, iclass 26, count 0 2006.258.00:09:28.83#ibcon#read 5, iclass 26, count 0 2006.258.00:09:28.83#ibcon#about to read 6, iclass 26, count 0 2006.258.00:09:28.83#ibcon#read 6, iclass 26, count 0 2006.258.00:09:28.83#ibcon#end of sib2, iclass 26, count 0 2006.258.00:09:28.83#ibcon#*after write, iclass 26, count 0 2006.258.00:09:28.83#ibcon#*before return 0, iclass 26, count 0 2006.258.00:09:28.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:28.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:09:28.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:09:28.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:09:28.83$vck44/vb=6,4 2006.258.00:09:28.83#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.00:09:28.83#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.00:09:28.83#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:28.83#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:28.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:28.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:28.89#ibcon#enter wrdev, iclass 28, count 2 2006.258.00:09:28.89#ibcon#first serial, iclass 28, count 2 2006.258.00:09:28.89#ibcon#enter sib2, iclass 28, count 2 2006.258.00:09:28.89#ibcon#flushed, iclass 28, count 2 2006.258.00:09:28.89#ibcon#about to write, iclass 28, count 2 2006.258.00:09:28.89#ibcon#wrote, iclass 28, count 2 2006.258.00:09:28.89#ibcon#about to read 3, iclass 28, count 2 2006.258.00:09:28.91#ibcon#read 3, iclass 28, count 2 2006.258.00:09:28.91#ibcon#about to read 4, iclass 28, count 2 2006.258.00:09:28.91#ibcon#read 4, iclass 28, count 2 2006.258.00:09:28.91#ibcon#about to read 5, iclass 28, count 2 2006.258.00:09:28.91#ibcon#read 5, iclass 28, count 2 2006.258.00:09:28.91#ibcon#about to read 6, iclass 28, count 2 2006.258.00:09:28.91#ibcon#read 6, iclass 28, count 2 2006.258.00:09:28.91#ibcon#end of sib2, iclass 28, count 2 2006.258.00:09:28.91#ibcon#*mode == 0, iclass 28, count 2 2006.258.00:09:28.91#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.00:09:28.91#ibcon#[27=AT06-04\r\n] 2006.258.00:09:28.91#ibcon#*before write, iclass 28, count 2 2006.258.00:09:28.91#ibcon#enter sib2, iclass 28, count 2 2006.258.00:09:28.91#ibcon#flushed, iclass 28, count 2 2006.258.00:09:28.91#ibcon#about to write, iclass 28, count 2 2006.258.00:09:28.91#ibcon#wrote, iclass 28, count 2 2006.258.00:09:28.91#ibcon#about to read 3, iclass 28, count 2 2006.258.00:09:28.94#ibcon#read 3, iclass 28, count 2 2006.258.00:09:28.94#ibcon#about to read 4, iclass 28, count 2 2006.258.00:09:28.94#ibcon#read 4, iclass 28, count 2 2006.258.00:09:28.94#ibcon#about to read 5, iclass 28, count 2 2006.258.00:09:28.94#ibcon#read 5, iclass 28, count 2 2006.258.00:09:28.94#ibcon#about to read 6, iclass 28, count 2 2006.258.00:09:28.94#ibcon#read 6, iclass 28, count 2 2006.258.00:09:28.94#ibcon#end of sib2, iclass 28, count 2 2006.258.00:09:28.94#ibcon#*after write, iclass 28, count 2 2006.258.00:09:28.94#ibcon#*before return 0, iclass 28, count 2 2006.258.00:09:28.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:28.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:09:28.94#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.00:09:28.94#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:28.94#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:29.06#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:29.06#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:29.06#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:09:29.06#ibcon#first serial, iclass 28, count 0 2006.258.00:09:29.06#ibcon#enter sib2, iclass 28, count 0 2006.258.00:09:29.06#ibcon#flushed, iclass 28, count 0 2006.258.00:09:29.06#ibcon#about to write, iclass 28, count 0 2006.258.00:09:29.06#ibcon#wrote, iclass 28, count 0 2006.258.00:09:29.06#ibcon#about to read 3, iclass 28, count 0 2006.258.00:09:29.08#ibcon#read 3, iclass 28, count 0 2006.258.00:09:29.08#ibcon#about to read 4, iclass 28, count 0 2006.258.00:09:29.08#ibcon#read 4, iclass 28, count 0 2006.258.00:09:29.08#ibcon#about to read 5, iclass 28, count 0 2006.258.00:09:29.08#ibcon#read 5, iclass 28, count 0 2006.258.00:09:29.08#ibcon#about to read 6, iclass 28, count 0 2006.258.00:09:29.08#ibcon#read 6, iclass 28, count 0 2006.258.00:09:29.08#ibcon#end of sib2, iclass 28, count 0 2006.258.00:09:29.08#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:09:29.08#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:09:29.08#ibcon#[27=USB\r\n] 2006.258.00:09:29.08#ibcon#*before write, iclass 28, count 0 2006.258.00:09:29.08#ibcon#enter sib2, iclass 28, count 0 2006.258.00:09:29.08#ibcon#flushed, iclass 28, count 0 2006.258.00:09:29.08#ibcon#about to write, iclass 28, count 0 2006.258.00:09:29.08#ibcon#wrote, iclass 28, count 0 2006.258.00:09:29.08#ibcon#about to read 3, iclass 28, count 0 2006.258.00:09:29.11#ibcon#read 3, iclass 28, count 0 2006.258.00:09:29.11#ibcon#about to read 4, iclass 28, count 0 2006.258.00:09:29.11#ibcon#read 4, iclass 28, count 0 2006.258.00:09:29.11#ibcon#about to read 5, iclass 28, count 0 2006.258.00:09:29.11#ibcon#read 5, iclass 28, count 0 2006.258.00:09:29.11#ibcon#about to read 6, iclass 28, count 0 2006.258.00:09:29.11#ibcon#read 6, iclass 28, count 0 2006.258.00:09:29.11#ibcon#end of sib2, iclass 28, count 0 2006.258.00:09:29.11#ibcon#*after write, iclass 28, count 0 2006.258.00:09:29.11#ibcon#*before return 0, iclass 28, count 0 2006.258.00:09:29.11#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:29.11#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:09:29.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:09:29.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:09:29.11$vck44/vblo=7,734.99 2006.258.00:09:29.11#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.00:09:29.11#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.00:09:29.11#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:29.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:29.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:29.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:29.11#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:09:29.11#ibcon#first serial, iclass 30, count 0 2006.258.00:09:29.11#ibcon#enter sib2, iclass 30, count 0 2006.258.00:09:29.11#ibcon#flushed, iclass 30, count 0 2006.258.00:09:29.11#ibcon#about to write, iclass 30, count 0 2006.258.00:09:29.11#ibcon#wrote, iclass 30, count 0 2006.258.00:09:29.11#ibcon#about to read 3, iclass 30, count 0 2006.258.00:09:29.13#ibcon#read 3, iclass 30, count 0 2006.258.00:09:29.13#ibcon#about to read 4, iclass 30, count 0 2006.258.00:09:29.13#ibcon#read 4, iclass 30, count 0 2006.258.00:09:29.13#ibcon#about to read 5, iclass 30, count 0 2006.258.00:09:29.13#ibcon#read 5, iclass 30, count 0 2006.258.00:09:29.13#ibcon#about to read 6, iclass 30, count 0 2006.258.00:09:29.13#ibcon#read 6, iclass 30, count 0 2006.258.00:09:29.13#ibcon#end of sib2, iclass 30, count 0 2006.258.00:09:29.13#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:09:29.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:09:29.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:09:29.13#ibcon#*before write, iclass 30, count 0 2006.258.00:09:29.13#ibcon#enter sib2, iclass 30, count 0 2006.258.00:09:29.13#ibcon#flushed, iclass 30, count 0 2006.258.00:09:29.13#ibcon#about to write, iclass 30, count 0 2006.258.00:09:29.13#ibcon#wrote, iclass 30, count 0 2006.258.00:09:29.13#ibcon#about to read 3, iclass 30, count 0 2006.258.00:09:29.17#ibcon#read 3, iclass 30, count 0 2006.258.00:09:29.17#ibcon#about to read 4, iclass 30, count 0 2006.258.00:09:29.17#ibcon#read 4, iclass 30, count 0 2006.258.00:09:29.17#ibcon#about to read 5, iclass 30, count 0 2006.258.00:09:29.17#ibcon#read 5, iclass 30, count 0 2006.258.00:09:29.17#ibcon#about to read 6, iclass 30, count 0 2006.258.00:09:29.17#ibcon#read 6, iclass 30, count 0 2006.258.00:09:29.17#ibcon#end of sib2, iclass 30, count 0 2006.258.00:09:29.17#ibcon#*after write, iclass 30, count 0 2006.258.00:09:29.17#ibcon#*before return 0, iclass 30, count 0 2006.258.00:09:29.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:29.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:09:29.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:09:29.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:09:29.17$vck44/vb=7,4 2006.258.00:09:29.17#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.258.00:09:29.17#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.258.00:09:29.17#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:29.17#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:29.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:29.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:29.23#ibcon#enter wrdev, iclass 32, count 2 2006.258.00:09:29.23#ibcon#first serial, iclass 32, count 2 2006.258.00:09:29.23#ibcon#enter sib2, iclass 32, count 2 2006.258.00:09:29.23#ibcon#flushed, iclass 32, count 2 2006.258.00:09:29.23#ibcon#about to write, iclass 32, count 2 2006.258.00:09:29.23#ibcon#wrote, iclass 32, count 2 2006.258.00:09:29.23#ibcon#about to read 3, iclass 32, count 2 2006.258.00:09:29.25#ibcon#read 3, iclass 32, count 2 2006.258.00:09:29.25#ibcon#about to read 4, iclass 32, count 2 2006.258.00:09:29.25#ibcon#read 4, iclass 32, count 2 2006.258.00:09:29.25#ibcon#about to read 5, iclass 32, count 2 2006.258.00:09:29.25#ibcon#read 5, iclass 32, count 2 2006.258.00:09:29.25#ibcon#about to read 6, iclass 32, count 2 2006.258.00:09:29.25#ibcon#read 6, iclass 32, count 2 2006.258.00:09:29.25#ibcon#end of sib2, iclass 32, count 2 2006.258.00:09:29.25#ibcon#*mode == 0, iclass 32, count 2 2006.258.00:09:29.25#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.258.00:09:29.25#ibcon#[27=AT07-04\r\n] 2006.258.00:09:29.25#ibcon#*before write, iclass 32, count 2 2006.258.00:09:29.25#ibcon#enter sib2, iclass 32, count 2 2006.258.00:09:29.25#ibcon#flushed, iclass 32, count 2 2006.258.00:09:29.25#ibcon#about to write, iclass 32, count 2 2006.258.00:09:29.25#ibcon#wrote, iclass 32, count 2 2006.258.00:09:29.25#ibcon#about to read 3, iclass 32, count 2 2006.258.00:09:29.28#ibcon#read 3, iclass 32, count 2 2006.258.00:09:29.28#ibcon#about to read 4, iclass 32, count 2 2006.258.00:09:29.28#ibcon#read 4, iclass 32, count 2 2006.258.00:09:29.28#ibcon#about to read 5, iclass 32, count 2 2006.258.00:09:29.28#ibcon#read 5, iclass 32, count 2 2006.258.00:09:29.28#ibcon#about to read 6, iclass 32, count 2 2006.258.00:09:29.28#ibcon#read 6, iclass 32, count 2 2006.258.00:09:29.28#ibcon#end of sib2, iclass 32, count 2 2006.258.00:09:29.28#ibcon#*after write, iclass 32, count 2 2006.258.00:09:29.28#ibcon#*before return 0, iclass 32, count 2 2006.258.00:09:29.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:29.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:09:29.28#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.258.00:09:29.28#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:29.28#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:29.40#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:29.40#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:29.40#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:09:29.40#ibcon#first serial, iclass 32, count 0 2006.258.00:09:29.40#ibcon#enter sib2, iclass 32, count 0 2006.258.00:09:29.40#ibcon#flushed, iclass 32, count 0 2006.258.00:09:29.40#ibcon#about to write, iclass 32, count 0 2006.258.00:09:29.40#ibcon#wrote, iclass 32, count 0 2006.258.00:09:29.40#ibcon#about to read 3, iclass 32, count 0 2006.258.00:09:29.42#ibcon#read 3, iclass 32, count 0 2006.258.00:09:29.42#ibcon#about to read 4, iclass 32, count 0 2006.258.00:09:29.42#ibcon#read 4, iclass 32, count 0 2006.258.00:09:29.42#ibcon#about to read 5, iclass 32, count 0 2006.258.00:09:29.42#ibcon#read 5, iclass 32, count 0 2006.258.00:09:29.42#ibcon#about to read 6, iclass 32, count 0 2006.258.00:09:29.42#ibcon#read 6, iclass 32, count 0 2006.258.00:09:29.42#ibcon#end of sib2, iclass 32, count 0 2006.258.00:09:29.42#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:09:29.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:09:29.42#ibcon#[27=USB\r\n] 2006.258.00:09:29.42#ibcon#*before write, iclass 32, count 0 2006.258.00:09:29.42#ibcon#enter sib2, iclass 32, count 0 2006.258.00:09:29.42#ibcon#flushed, iclass 32, count 0 2006.258.00:09:29.42#ibcon#about to write, iclass 32, count 0 2006.258.00:09:29.42#ibcon#wrote, iclass 32, count 0 2006.258.00:09:29.42#ibcon#about to read 3, iclass 32, count 0 2006.258.00:09:29.45#ibcon#read 3, iclass 32, count 0 2006.258.00:09:29.45#ibcon#about to read 4, iclass 32, count 0 2006.258.00:09:29.45#ibcon#read 4, iclass 32, count 0 2006.258.00:09:29.45#ibcon#about to read 5, iclass 32, count 0 2006.258.00:09:29.45#ibcon#read 5, iclass 32, count 0 2006.258.00:09:29.45#ibcon#about to read 6, iclass 32, count 0 2006.258.00:09:29.45#ibcon#read 6, iclass 32, count 0 2006.258.00:09:29.45#ibcon#end of sib2, iclass 32, count 0 2006.258.00:09:29.45#ibcon#*after write, iclass 32, count 0 2006.258.00:09:29.45#ibcon#*before return 0, iclass 32, count 0 2006.258.00:09:29.45#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:29.45#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:09:29.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:09:29.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:09:29.45$vck44/vblo=8,744.99 2006.258.00:09:29.45#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.00:09:29.45#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.00:09:29.45#ibcon#ireg 17 cls_cnt 0 2006.258.00:09:29.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:29.45#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:29.45#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:29.45#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:09:29.45#ibcon#first serial, iclass 34, count 0 2006.258.00:09:29.45#ibcon#enter sib2, iclass 34, count 0 2006.258.00:09:29.45#ibcon#flushed, iclass 34, count 0 2006.258.00:09:29.45#ibcon#about to write, iclass 34, count 0 2006.258.00:09:29.45#ibcon#wrote, iclass 34, count 0 2006.258.00:09:29.45#ibcon#about to read 3, iclass 34, count 0 2006.258.00:09:29.47#ibcon#read 3, iclass 34, count 0 2006.258.00:09:29.47#ibcon#about to read 4, iclass 34, count 0 2006.258.00:09:29.47#ibcon#read 4, iclass 34, count 0 2006.258.00:09:29.47#ibcon#about to read 5, iclass 34, count 0 2006.258.00:09:29.47#ibcon#read 5, iclass 34, count 0 2006.258.00:09:29.47#ibcon#about to read 6, iclass 34, count 0 2006.258.00:09:29.47#ibcon#read 6, iclass 34, count 0 2006.258.00:09:29.47#ibcon#end of sib2, iclass 34, count 0 2006.258.00:09:29.47#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:09:29.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:09:29.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:09:29.47#ibcon#*before write, iclass 34, count 0 2006.258.00:09:29.47#ibcon#enter sib2, iclass 34, count 0 2006.258.00:09:29.47#ibcon#flushed, iclass 34, count 0 2006.258.00:09:29.47#ibcon#about to write, iclass 34, count 0 2006.258.00:09:29.47#ibcon#wrote, iclass 34, count 0 2006.258.00:09:29.47#ibcon#about to read 3, iclass 34, count 0 2006.258.00:09:29.51#ibcon#read 3, iclass 34, count 0 2006.258.00:09:29.51#ibcon#about to read 4, iclass 34, count 0 2006.258.00:09:29.51#ibcon#read 4, iclass 34, count 0 2006.258.00:09:29.51#ibcon#about to read 5, iclass 34, count 0 2006.258.00:09:29.51#ibcon#read 5, iclass 34, count 0 2006.258.00:09:29.51#ibcon#about to read 6, iclass 34, count 0 2006.258.00:09:29.51#ibcon#read 6, iclass 34, count 0 2006.258.00:09:29.51#ibcon#end of sib2, iclass 34, count 0 2006.258.00:09:29.51#ibcon#*after write, iclass 34, count 0 2006.258.00:09:29.51#ibcon#*before return 0, iclass 34, count 0 2006.258.00:09:29.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:29.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:09:29.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:09:29.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:09:29.51$vck44/vb=8,4 2006.258.00:09:29.51#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.258.00:09:29.51#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.258.00:09:29.51#ibcon#ireg 11 cls_cnt 2 2006.258.00:09:29.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:29.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:29.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:29.57#ibcon#enter wrdev, iclass 36, count 2 2006.258.00:09:29.57#ibcon#first serial, iclass 36, count 2 2006.258.00:09:29.57#ibcon#enter sib2, iclass 36, count 2 2006.258.00:09:29.57#ibcon#flushed, iclass 36, count 2 2006.258.00:09:29.57#ibcon#about to write, iclass 36, count 2 2006.258.00:09:29.57#ibcon#wrote, iclass 36, count 2 2006.258.00:09:29.57#ibcon#about to read 3, iclass 36, count 2 2006.258.00:09:29.59#ibcon#read 3, iclass 36, count 2 2006.258.00:09:29.59#ibcon#about to read 4, iclass 36, count 2 2006.258.00:09:29.59#ibcon#read 4, iclass 36, count 2 2006.258.00:09:29.59#ibcon#about to read 5, iclass 36, count 2 2006.258.00:09:29.59#ibcon#read 5, iclass 36, count 2 2006.258.00:09:29.59#ibcon#about to read 6, iclass 36, count 2 2006.258.00:09:29.59#ibcon#read 6, iclass 36, count 2 2006.258.00:09:29.59#ibcon#end of sib2, iclass 36, count 2 2006.258.00:09:29.59#ibcon#*mode == 0, iclass 36, count 2 2006.258.00:09:29.59#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.258.00:09:29.59#ibcon#[27=AT08-04\r\n] 2006.258.00:09:29.59#ibcon#*before write, iclass 36, count 2 2006.258.00:09:29.59#ibcon#enter sib2, iclass 36, count 2 2006.258.00:09:29.59#ibcon#flushed, iclass 36, count 2 2006.258.00:09:29.59#ibcon#about to write, iclass 36, count 2 2006.258.00:09:29.59#ibcon#wrote, iclass 36, count 2 2006.258.00:09:29.59#ibcon#about to read 3, iclass 36, count 2 2006.258.00:09:29.62#ibcon#read 3, iclass 36, count 2 2006.258.00:09:29.62#ibcon#about to read 4, iclass 36, count 2 2006.258.00:09:29.62#ibcon#read 4, iclass 36, count 2 2006.258.00:09:29.62#ibcon#about to read 5, iclass 36, count 2 2006.258.00:09:29.62#ibcon#read 5, iclass 36, count 2 2006.258.00:09:29.62#ibcon#about to read 6, iclass 36, count 2 2006.258.00:09:29.62#ibcon#read 6, iclass 36, count 2 2006.258.00:09:29.62#ibcon#end of sib2, iclass 36, count 2 2006.258.00:09:29.62#ibcon#*after write, iclass 36, count 2 2006.258.00:09:29.65#ibcon#*before return 0, iclass 36, count 2 2006.258.00:09:29.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:29.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:09:29.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.258.00:09:29.66#ibcon#ireg 7 cls_cnt 0 2006.258.00:09:29.66#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:29.76#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:29.76#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:29.76#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:09:29.76#ibcon#first serial, iclass 36, count 0 2006.258.00:09:29.76#ibcon#enter sib2, iclass 36, count 0 2006.258.00:09:29.76#ibcon#flushed, iclass 36, count 0 2006.258.00:09:29.76#ibcon#about to write, iclass 36, count 0 2006.258.00:09:29.76#ibcon#wrote, iclass 36, count 0 2006.258.00:09:29.76#ibcon#about to read 3, iclass 36, count 0 2006.258.00:09:29.78#ibcon#read 3, iclass 36, count 0 2006.258.00:09:29.78#ibcon#about to read 4, iclass 36, count 0 2006.258.00:09:29.78#ibcon#read 4, iclass 36, count 0 2006.258.00:09:29.78#ibcon#about to read 5, iclass 36, count 0 2006.258.00:09:29.78#ibcon#read 5, iclass 36, count 0 2006.258.00:09:29.78#ibcon#about to read 6, iclass 36, count 0 2006.258.00:09:29.78#ibcon#read 6, iclass 36, count 0 2006.258.00:09:29.78#ibcon#end of sib2, iclass 36, count 0 2006.258.00:09:29.78#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:09:29.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:09:29.78#ibcon#[27=USB\r\n] 2006.258.00:09:29.78#ibcon#*before write, iclass 36, count 0 2006.258.00:09:29.78#ibcon#enter sib2, iclass 36, count 0 2006.258.00:09:29.78#ibcon#flushed, iclass 36, count 0 2006.258.00:09:29.78#ibcon#about to write, iclass 36, count 0 2006.258.00:09:29.78#ibcon#wrote, iclass 36, count 0 2006.258.00:09:29.78#ibcon#about to read 3, iclass 36, count 0 2006.258.00:09:29.81#ibcon#read 3, iclass 36, count 0 2006.258.00:09:29.81#ibcon#about to read 4, iclass 36, count 0 2006.258.00:09:29.81#ibcon#read 4, iclass 36, count 0 2006.258.00:09:29.81#ibcon#about to read 5, iclass 36, count 0 2006.258.00:09:29.81#ibcon#read 5, iclass 36, count 0 2006.258.00:09:29.81#ibcon#about to read 6, iclass 36, count 0 2006.258.00:09:29.81#ibcon#read 6, iclass 36, count 0 2006.258.00:09:29.81#ibcon#end of sib2, iclass 36, count 0 2006.258.00:09:29.81#ibcon#*after write, iclass 36, count 0 2006.258.00:09:29.81#ibcon#*before return 0, iclass 36, count 0 2006.258.00:09:29.81#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:29.81#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:09:29.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:09:29.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:09:29.81$vck44/vabw=wide 2006.258.00:09:29.81#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.00:09:29.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.00:09:29.81#ibcon#ireg 8 cls_cnt 0 2006.258.00:09:29.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:29.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:29.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:29.81#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:09:29.81#ibcon#first serial, iclass 38, count 0 2006.258.00:09:29.81#ibcon#enter sib2, iclass 38, count 0 2006.258.00:09:29.81#ibcon#flushed, iclass 38, count 0 2006.258.00:09:29.81#ibcon#about to write, iclass 38, count 0 2006.258.00:09:29.81#ibcon#wrote, iclass 38, count 0 2006.258.00:09:29.81#ibcon#about to read 3, iclass 38, count 0 2006.258.00:09:29.83#ibcon#read 3, iclass 38, count 0 2006.258.00:09:29.83#ibcon#about to read 4, iclass 38, count 0 2006.258.00:09:29.83#ibcon#read 4, iclass 38, count 0 2006.258.00:09:29.83#ibcon#about to read 5, iclass 38, count 0 2006.258.00:09:29.83#ibcon#read 5, iclass 38, count 0 2006.258.00:09:29.83#ibcon#about to read 6, iclass 38, count 0 2006.258.00:09:29.83#ibcon#read 6, iclass 38, count 0 2006.258.00:09:29.83#ibcon#end of sib2, iclass 38, count 0 2006.258.00:09:29.83#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:09:29.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:09:29.83#ibcon#[25=BW32\r\n] 2006.258.00:09:29.83#ibcon#*before write, iclass 38, count 0 2006.258.00:09:29.83#ibcon#enter sib2, iclass 38, count 0 2006.258.00:09:29.83#ibcon#flushed, iclass 38, count 0 2006.258.00:09:29.83#ibcon#about to write, iclass 38, count 0 2006.258.00:09:29.83#ibcon#wrote, iclass 38, count 0 2006.258.00:09:29.83#ibcon#about to read 3, iclass 38, count 0 2006.258.00:09:29.86#ibcon#read 3, iclass 38, count 0 2006.258.00:09:29.86#ibcon#about to read 4, iclass 38, count 0 2006.258.00:09:29.86#ibcon#read 4, iclass 38, count 0 2006.258.00:09:29.86#ibcon#about to read 5, iclass 38, count 0 2006.258.00:09:29.86#ibcon#read 5, iclass 38, count 0 2006.258.00:09:29.86#ibcon#about to read 6, iclass 38, count 0 2006.258.00:09:29.86#ibcon#read 6, iclass 38, count 0 2006.258.00:09:29.86#ibcon#end of sib2, iclass 38, count 0 2006.258.00:09:29.86#ibcon#*after write, iclass 38, count 0 2006.258.00:09:29.86#ibcon#*before return 0, iclass 38, count 0 2006.258.00:09:29.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:29.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:09:29.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:09:29.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:09:29.86$vck44/vbbw=wide 2006.258.00:09:29.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.00:09:29.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.00:09:29.86#ibcon#ireg 8 cls_cnt 0 2006.258.00:09:29.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:09:29.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:09:29.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:09:29.93#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:09:29.93#ibcon#first serial, iclass 40, count 0 2006.258.00:09:29.93#ibcon#enter sib2, iclass 40, count 0 2006.258.00:09:29.93#ibcon#flushed, iclass 40, count 0 2006.258.00:09:29.93#ibcon#about to write, iclass 40, count 0 2006.258.00:09:29.93#ibcon#wrote, iclass 40, count 0 2006.258.00:09:29.93#ibcon#about to read 3, iclass 40, count 0 2006.258.00:09:29.95#ibcon#read 3, iclass 40, count 0 2006.258.00:09:29.95#ibcon#about to read 4, iclass 40, count 0 2006.258.00:09:29.95#ibcon#read 4, iclass 40, count 0 2006.258.00:09:29.95#ibcon#about to read 5, iclass 40, count 0 2006.258.00:09:29.95#ibcon#read 5, iclass 40, count 0 2006.258.00:09:29.95#ibcon#about to read 6, iclass 40, count 0 2006.258.00:09:29.95#ibcon#read 6, iclass 40, count 0 2006.258.00:09:29.95#ibcon#end of sib2, iclass 40, count 0 2006.258.00:09:29.95#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:09:29.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:09:29.95#ibcon#[27=BW32\r\n] 2006.258.00:09:29.95#ibcon#*before write, iclass 40, count 0 2006.258.00:09:29.95#ibcon#enter sib2, iclass 40, count 0 2006.258.00:09:29.95#ibcon#flushed, iclass 40, count 0 2006.258.00:09:29.95#ibcon#about to write, iclass 40, count 0 2006.258.00:09:29.95#ibcon#wrote, iclass 40, count 0 2006.258.00:09:29.95#ibcon#about to read 3, iclass 40, count 0 2006.258.00:09:29.98#ibcon#read 3, iclass 40, count 0 2006.258.00:09:29.98#ibcon#about to read 4, iclass 40, count 0 2006.258.00:09:29.98#ibcon#read 4, iclass 40, count 0 2006.258.00:09:29.98#ibcon#about to read 5, iclass 40, count 0 2006.258.00:09:29.98#ibcon#read 5, iclass 40, count 0 2006.258.00:09:29.98#ibcon#about to read 6, iclass 40, count 0 2006.258.00:09:29.98#ibcon#read 6, iclass 40, count 0 2006.258.00:09:29.98#ibcon#end of sib2, iclass 40, count 0 2006.258.00:09:29.98#ibcon#*after write, iclass 40, count 0 2006.258.00:09:29.98#ibcon#*before return 0, iclass 40, count 0 2006.258.00:09:29.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:09:29.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:09:29.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:09:29.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:09:29.98$setupk4/ifdk4 2006.258.00:09:29.98$ifdk4/lo= 2006.258.00:09:29.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:09:29.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:09:29.98$ifdk4/patch= 2006.258.00:09:29.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:09:29.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:09:29.98$setupk4/!*+20s 2006.258.00:09:30.27#abcon#<5=/01 1.4 4.0 21.71 791016.3\r\n> 2006.258.00:09:30.29#abcon#{5=INTERFACE CLEAR} 2006.258.00:09:30.35#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:09:40.44#abcon#<5=/01 1.4 4.0 21.72 791016.3\r\n> 2006.258.00:09:40.46#abcon#{5=INTERFACE CLEAR} 2006.258.00:09:40.52#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:09:41.14#trakl#Source acquired 2006.258.00:09:43.14#flagr#flagr/antenna,acquired 2006.258.00:09:44.33$setupk4/"tpicd 2006.258.00:09:44.33$setupk4/echo=off 2006.258.00:09:44.33$setupk4/xlog=off 2006.258.00:09:44.33:!2006.258.00:10:14 2006.258.00:10:14.00:preob 2006.258.00:10:14.14/onsource/TRACKING 2006.258.00:10:14.14:!2006.258.00:10:24 2006.258.00:10:24.00:"tape 2006.258.00:10:24.00:"st=record 2006.258.00:10:24.00:data_valid=on 2006.258.00:10:24.00:midob 2006.258.00:10:25.14/onsource/TRACKING 2006.258.00:10:25.14/wx/21.73,1016.3,79 2006.258.00:10:25.23/cable/+6.4812E-03 2006.258.00:10:26.32/va/01,08,usb,yes,36,39 2006.258.00:10:26.32/va/02,07,usb,yes,39,40 2006.258.00:10:26.32/va/03,08,usb,yes,35,37 2006.258.00:10:26.32/va/04,07,usb,yes,40,42 2006.258.00:10:26.32/va/05,04,usb,yes,36,36 2006.258.00:10:26.32/va/06,04,usb,yes,40,39 2006.258.00:10:26.32/va/07,04,usb,yes,41,41 2006.258.00:10:26.32/va/08,04,usb,yes,34,42 2006.258.00:10:26.55/valo/01,524.99,yes,locked 2006.258.00:10:26.55/valo/02,534.99,yes,locked 2006.258.00:10:26.55/valo/03,564.99,yes,locked 2006.258.00:10:26.55/valo/04,624.99,yes,locked 2006.258.00:10:26.55/valo/05,734.99,yes,locked 2006.258.00:10:26.55/valo/06,814.99,yes,locked 2006.258.00:10:26.55/valo/07,864.99,yes,locked 2006.258.00:10:26.55/valo/08,884.99,yes,locked 2006.258.00:10:27.64/vb/01,04,usb,yes,35,32 2006.258.00:10:27.64/vb/02,05,usb,yes,33,33 2006.258.00:10:27.64/vb/03,04,usb,yes,34,38 2006.258.00:10:27.64/vb/04,05,usb,yes,34,33 2006.258.00:10:27.64/vb/05,04,usb,yes,31,33 2006.258.00:10:27.64/vb/06,04,usb,yes,36,32 2006.258.00:10:27.64/vb/07,04,usb,yes,35,35 2006.258.00:10:27.64/vb/08,04,usb,yes,33,36 2006.258.00:10:27.87/vblo/01,629.99,yes,locked 2006.258.00:10:27.87/vblo/02,634.99,yes,locked 2006.258.00:10:27.87/vblo/03,649.99,yes,locked 2006.258.00:10:27.87/vblo/04,679.99,yes,locked 2006.258.00:10:27.87/vblo/05,709.99,yes,locked 2006.258.00:10:27.87/vblo/06,719.99,yes,locked 2006.258.00:10:27.87/vblo/07,734.99,yes,locked 2006.258.00:10:27.87/vblo/08,744.99,yes,locked 2006.258.00:10:28.02/vabw/8 2006.258.00:10:28.17/vbbw/8 2006.258.00:10:28.26/xfe/off,on,15.0 2006.258.00:10:28.64/ifatt/23,28,28,28 2006.258.00:10:29.07/fmout-gps/S +4.56E-07 2006.258.00:10:29.11:!2006.258.00:12:14 2006.258.00:12:14.01:data_valid=off 2006.258.00:12:14.01:"et 2006.258.00:12:14.01:!+3s 2006.258.00:12:17.02:"tape 2006.258.00:12:17.02:postob 2006.258.00:12:17.24/cable/+6.4804E-03 2006.258.00:12:17.24/wx/21.77,1016.2,78 2006.258.00:12:17.30/fmout-gps/S +4.57E-07 2006.258.00:12:17.30:scan_name=258-0018,jd0609,200 2006.258.00:12:17.30:source=1044+719,104827.62,714335.9,2000.0,cw 2006.258.00:12:18.14#flagr#flagr/antenna,new-source 2006.258.00:12:18.14:checkk5 2006.258.00:12:18.50/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:12:18.91/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:12:19.33/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:12:19.71/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:12:20.10/chk_obsdata//k5ts1/T2580010??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.258.00:12:20.50/chk_obsdata//k5ts2/T2580010??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.258.00:12:20.91/chk_obsdata//k5ts3/T2580010??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.258.00:12:21.32/chk_obsdata//k5ts4/T2580010??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.258.00:12:22.06/k5log//k5ts1_log_newline 2006.258.00:12:22.79/k5log//k5ts2_log_newline 2006.258.00:12:23.52/k5log//k5ts3_log_newline 2006.258.00:12:24.24/k5log//k5ts4_log_newline 2006.258.00:12:24.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:12:24.26:setupk4=1 2006.258.00:12:24.26$setupk4/echo=on 2006.258.00:12:24.26$setupk4/pcalon 2006.258.00:12:24.26$pcalon/"no phase cal control is implemented here 2006.258.00:12:24.26$setupk4/"tpicd=stop 2006.258.00:12:24.26$setupk4/"rec=synch_on 2006.258.00:12:24.26$setupk4/"rec_mode=128 2006.258.00:12:24.26$setupk4/!* 2006.258.00:12:24.26$setupk4/recpk4 2006.258.00:12:24.26$recpk4/recpatch= 2006.258.00:12:24.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:12:24.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:12:24.27$setupk4/vck44 2006.258.00:12:24.27$vck44/valo=1,524.99 2006.258.00:12:24.27#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.00:12:24.27#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.00:12:24.27#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:24.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:24.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:24.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:24.27#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:12:24.27#ibcon#first serial, iclass 7, count 0 2006.258.00:12:24.27#ibcon#enter sib2, iclass 7, count 0 2006.258.00:12:24.27#ibcon#flushed, iclass 7, count 0 2006.258.00:12:24.27#ibcon#about to write, iclass 7, count 0 2006.258.00:12:24.27#ibcon#wrote, iclass 7, count 0 2006.258.00:12:24.27#ibcon#about to read 3, iclass 7, count 0 2006.258.00:12:24.28#ibcon#read 3, iclass 7, count 0 2006.258.00:12:24.28#ibcon#about to read 4, iclass 7, count 0 2006.258.00:12:24.28#ibcon#read 4, iclass 7, count 0 2006.258.00:12:24.28#ibcon#about to read 5, iclass 7, count 0 2006.258.00:12:24.28#ibcon#read 5, iclass 7, count 0 2006.258.00:12:24.28#ibcon#about to read 6, iclass 7, count 0 2006.258.00:12:24.28#ibcon#read 6, iclass 7, count 0 2006.258.00:12:24.28#ibcon#end of sib2, iclass 7, count 0 2006.258.00:12:24.28#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:12:24.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:12:24.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:12:24.28#ibcon#*before write, iclass 7, count 0 2006.258.00:12:24.28#ibcon#enter sib2, iclass 7, count 0 2006.258.00:12:24.28#ibcon#flushed, iclass 7, count 0 2006.258.00:12:24.28#ibcon#about to write, iclass 7, count 0 2006.258.00:12:24.28#ibcon#wrote, iclass 7, count 0 2006.258.00:12:24.28#ibcon#about to read 3, iclass 7, count 0 2006.258.00:12:24.33#ibcon#read 3, iclass 7, count 0 2006.258.00:12:24.33#ibcon#about to read 4, iclass 7, count 0 2006.258.00:12:24.33#ibcon#read 4, iclass 7, count 0 2006.258.00:12:24.33#ibcon#about to read 5, iclass 7, count 0 2006.258.00:12:24.33#ibcon#read 5, iclass 7, count 0 2006.258.00:12:24.33#ibcon#about to read 6, iclass 7, count 0 2006.258.00:12:24.33#ibcon#read 6, iclass 7, count 0 2006.258.00:12:24.33#ibcon#end of sib2, iclass 7, count 0 2006.258.00:12:24.33#ibcon#*after write, iclass 7, count 0 2006.258.00:12:24.33#ibcon#*before return 0, iclass 7, count 0 2006.258.00:12:24.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:24.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:24.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:12:24.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:12:24.33$vck44/va=1,8 2006.258.00:12:24.33#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.00:12:24.33#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.00:12:24.33#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:24.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:24.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:24.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:24.33#ibcon#enter wrdev, iclass 11, count 2 2006.258.00:12:24.33#ibcon#first serial, iclass 11, count 2 2006.258.00:12:24.33#ibcon#enter sib2, iclass 11, count 2 2006.258.00:12:24.33#ibcon#flushed, iclass 11, count 2 2006.258.00:12:24.33#ibcon#about to write, iclass 11, count 2 2006.258.00:12:24.33#ibcon#wrote, iclass 11, count 2 2006.258.00:12:24.33#ibcon#about to read 3, iclass 11, count 2 2006.258.00:12:24.35#ibcon#read 3, iclass 11, count 2 2006.258.00:12:24.35#ibcon#about to read 4, iclass 11, count 2 2006.258.00:12:24.35#ibcon#read 4, iclass 11, count 2 2006.258.00:12:24.35#ibcon#about to read 5, iclass 11, count 2 2006.258.00:12:24.35#ibcon#read 5, iclass 11, count 2 2006.258.00:12:24.35#ibcon#about to read 6, iclass 11, count 2 2006.258.00:12:24.35#ibcon#read 6, iclass 11, count 2 2006.258.00:12:24.35#ibcon#end of sib2, iclass 11, count 2 2006.258.00:12:24.35#ibcon#*mode == 0, iclass 11, count 2 2006.258.00:12:24.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.00:12:24.35#ibcon#[25=AT01-08\r\n] 2006.258.00:12:24.35#ibcon#*before write, iclass 11, count 2 2006.258.00:12:24.35#ibcon#enter sib2, iclass 11, count 2 2006.258.00:12:24.35#ibcon#flushed, iclass 11, count 2 2006.258.00:12:24.35#ibcon#about to write, iclass 11, count 2 2006.258.00:12:24.35#ibcon#wrote, iclass 11, count 2 2006.258.00:12:24.35#ibcon#about to read 3, iclass 11, count 2 2006.258.00:12:24.38#ibcon#read 3, iclass 11, count 2 2006.258.00:12:24.38#ibcon#about to read 4, iclass 11, count 2 2006.258.00:12:24.38#ibcon#read 4, iclass 11, count 2 2006.258.00:12:24.38#ibcon#about to read 5, iclass 11, count 2 2006.258.00:12:24.38#ibcon#read 5, iclass 11, count 2 2006.258.00:12:24.38#ibcon#about to read 6, iclass 11, count 2 2006.258.00:12:24.38#ibcon#read 6, iclass 11, count 2 2006.258.00:12:24.38#ibcon#end of sib2, iclass 11, count 2 2006.258.00:12:24.38#ibcon#*after write, iclass 11, count 2 2006.258.00:12:24.38#ibcon#*before return 0, iclass 11, count 2 2006.258.00:12:24.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:24.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:24.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.00:12:24.38#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:24.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:24.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:24.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:24.50#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:12:24.50#ibcon#first serial, iclass 11, count 0 2006.258.00:12:24.50#ibcon#enter sib2, iclass 11, count 0 2006.258.00:12:24.50#ibcon#flushed, iclass 11, count 0 2006.258.00:12:24.50#ibcon#about to write, iclass 11, count 0 2006.258.00:12:24.50#ibcon#wrote, iclass 11, count 0 2006.258.00:12:24.50#ibcon#about to read 3, iclass 11, count 0 2006.258.00:12:24.52#ibcon#read 3, iclass 11, count 0 2006.258.00:12:24.52#ibcon#about to read 4, iclass 11, count 0 2006.258.00:12:24.52#ibcon#read 4, iclass 11, count 0 2006.258.00:12:24.52#ibcon#about to read 5, iclass 11, count 0 2006.258.00:12:24.52#ibcon#read 5, iclass 11, count 0 2006.258.00:12:24.52#ibcon#about to read 6, iclass 11, count 0 2006.258.00:12:24.52#ibcon#read 6, iclass 11, count 0 2006.258.00:12:24.52#ibcon#end of sib2, iclass 11, count 0 2006.258.00:12:24.52#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:12:24.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:12:24.52#ibcon#[25=USB\r\n] 2006.258.00:12:24.52#ibcon#*before write, iclass 11, count 0 2006.258.00:12:24.52#ibcon#enter sib2, iclass 11, count 0 2006.258.00:12:24.52#ibcon#flushed, iclass 11, count 0 2006.258.00:12:24.52#ibcon#about to write, iclass 11, count 0 2006.258.00:12:24.52#ibcon#wrote, iclass 11, count 0 2006.258.00:12:24.52#ibcon#about to read 3, iclass 11, count 0 2006.258.00:12:24.55#ibcon#read 3, iclass 11, count 0 2006.258.00:12:24.55#ibcon#about to read 4, iclass 11, count 0 2006.258.00:12:24.55#ibcon#read 4, iclass 11, count 0 2006.258.00:12:24.55#ibcon#about to read 5, iclass 11, count 0 2006.258.00:12:24.55#ibcon#read 5, iclass 11, count 0 2006.258.00:12:24.55#ibcon#about to read 6, iclass 11, count 0 2006.258.00:12:24.55#ibcon#read 6, iclass 11, count 0 2006.258.00:12:24.55#ibcon#end of sib2, iclass 11, count 0 2006.258.00:12:24.55#ibcon#*after write, iclass 11, count 0 2006.258.00:12:24.55#ibcon#*before return 0, iclass 11, count 0 2006.258.00:12:24.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:24.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:24.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:12:24.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:12:24.55$vck44/valo=2,534.99 2006.258.00:12:24.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.258.00:12:24.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.258.00:12:24.55#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:24.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:24.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:24.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:24.55#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:12:24.55#ibcon#first serial, iclass 13, count 0 2006.258.00:12:24.55#ibcon#enter sib2, iclass 13, count 0 2006.258.00:12:24.55#ibcon#flushed, iclass 13, count 0 2006.258.00:12:24.55#ibcon#about to write, iclass 13, count 0 2006.258.00:12:24.55#ibcon#wrote, iclass 13, count 0 2006.258.00:12:24.55#ibcon#about to read 3, iclass 13, count 0 2006.258.00:12:24.57#ibcon#read 3, iclass 13, count 0 2006.258.00:12:24.57#ibcon#about to read 4, iclass 13, count 0 2006.258.00:12:24.57#ibcon#read 4, iclass 13, count 0 2006.258.00:12:24.57#ibcon#about to read 5, iclass 13, count 0 2006.258.00:12:24.57#ibcon#read 5, iclass 13, count 0 2006.258.00:12:24.57#ibcon#about to read 6, iclass 13, count 0 2006.258.00:12:24.57#ibcon#read 6, iclass 13, count 0 2006.258.00:12:24.57#ibcon#end of sib2, iclass 13, count 0 2006.258.00:12:24.57#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:12:24.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:12:24.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:12:24.57#ibcon#*before write, iclass 13, count 0 2006.258.00:12:24.57#ibcon#enter sib2, iclass 13, count 0 2006.258.00:12:24.57#ibcon#flushed, iclass 13, count 0 2006.258.00:12:24.57#ibcon#about to write, iclass 13, count 0 2006.258.00:12:24.57#ibcon#wrote, iclass 13, count 0 2006.258.00:12:24.57#ibcon#about to read 3, iclass 13, count 0 2006.258.00:12:24.61#ibcon#read 3, iclass 13, count 0 2006.258.00:12:24.61#ibcon#about to read 4, iclass 13, count 0 2006.258.00:12:24.61#ibcon#read 4, iclass 13, count 0 2006.258.00:12:24.61#ibcon#about to read 5, iclass 13, count 0 2006.258.00:12:24.61#ibcon#read 5, iclass 13, count 0 2006.258.00:12:24.61#ibcon#about to read 6, iclass 13, count 0 2006.258.00:12:24.61#ibcon#read 6, iclass 13, count 0 2006.258.00:12:24.61#ibcon#end of sib2, iclass 13, count 0 2006.258.00:12:24.61#ibcon#*after write, iclass 13, count 0 2006.258.00:12:24.61#ibcon#*before return 0, iclass 13, count 0 2006.258.00:12:24.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:24.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:24.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:12:24.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:12:24.61$vck44/va=2,7 2006.258.00:12:24.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.258.00:12:24.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.258.00:12:24.61#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:24.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:24.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:24.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:24.67#ibcon#enter wrdev, iclass 15, count 2 2006.258.00:12:24.67#ibcon#first serial, iclass 15, count 2 2006.258.00:12:24.67#ibcon#enter sib2, iclass 15, count 2 2006.258.00:12:24.67#ibcon#flushed, iclass 15, count 2 2006.258.00:12:24.67#ibcon#about to write, iclass 15, count 2 2006.258.00:12:24.67#ibcon#wrote, iclass 15, count 2 2006.258.00:12:24.67#ibcon#about to read 3, iclass 15, count 2 2006.258.00:12:24.69#ibcon#read 3, iclass 15, count 2 2006.258.00:12:24.69#ibcon#about to read 4, iclass 15, count 2 2006.258.00:12:24.69#ibcon#read 4, iclass 15, count 2 2006.258.00:12:24.69#ibcon#about to read 5, iclass 15, count 2 2006.258.00:12:24.69#ibcon#read 5, iclass 15, count 2 2006.258.00:12:24.69#ibcon#about to read 6, iclass 15, count 2 2006.258.00:12:24.69#ibcon#read 6, iclass 15, count 2 2006.258.00:12:24.69#ibcon#end of sib2, iclass 15, count 2 2006.258.00:12:24.69#ibcon#*mode == 0, iclass 15, count 2 2006.258.00:12:24.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.258.00:12:24.69#ibcon#[25=AT02-07\r\n] 2006.258.00:12:24.69#ibcon#*before write, iclass 15, count 2 2006.258.00:12:24.69#ibcon#enter sib2, iclass 15, count 2 2006.258.00:12:24.69#ibcon#flushed, iclass 15, count 2 2006.258.00:12:24.69#ibcon#about to write, iclass 15, count 2 2006.258.00:12:24.69#ibcon#wrote, iclass 15, count 2 2006.258.00:12:24.69#ibcon#about to read 3, iclass 15, count 2 2006.258.00:12:24.72#ibcon#read 3, iclass 15, count 2 2006.258.00:12:24.72#ibcon#about to read 4, iclass 15, count 2 2006.258.00:12:24.72#ibcon#read 4, iclass 15, count 2 2006.258.00:12:24.72#ibcon#about to read 5, iclass 15, count 2 2006.258.00:12:24.72#ibcon#read 5, iclass 15, count 2 2006.258.00:12:24.72#ibcon#about to read 6, iclass 15, count 2 2006.258.00:12:24.72#ibcon#read 6, iclass 15, count 2 2006.258.00:12:24.72#ibcon#end of sib2, iclass 15, count 2 2006.258.00:12:24.72#ibcon#*after write, iclass 15, count 2 2006.258.00:12:24.72#ibcon#*before return 0, iclass 15, count 2 2006.258.00:12:24.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:24.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:24.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.258.00:12:24.72#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:24.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:24.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:24.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:24.84#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:12:24.84#ibcon#first serial, iclass 15, count 0 2006.258.00:12:24.84#ibcon#enter sib2, iclass 15, count 0 2006.258.00:12:24.84#ibcon#flushed, iclass 15, count 0 2006.258.00:12:24.84#ibcon#about to write, iclass 15, count 0 2006.258.00:12:24.84#ibcon#wrote, iclass 15, count 0 2006.258.00:12:24.84#ibcon#about to read 3, iclass 15, count 0 2006.258.00:12:24.86#ibcon#read 3, iclass 15, count 0 2006.258.00:12:24.86#ibcon#about to read 4, iclass 15, count 0 2006.258.00:12:24.86#ibcon#read 4, iclass 15, count 0 2006.258.00:12:24.86#ibcon#about to read 5, iclass 15, count 0 2006.258.00:12:24.86#ibcon#read 5, iclass 15, count 0 2006.258.00:12:24.86#ibcon#about to read 6, iclass 15, count 0 2006.258.00:12:24.86#ibcon#read 6, iclass 15, count 0 2006.258.00:12:24.86#ibcon#end of sib2, iclass 15, count 0 2006.258.00:12:24.86#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:12:24.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:12:24.86#ibcon#[25=USB\r\n] 2006.258.00:12:24.86#ibcon#*before write, iclass 15, count 0 2006.258.00:12:24.86#ibcon#enter sib2, iclass 15, count 0 2006.258.00:12:24.86#ibcon#flushed, iclass 15, count 0 2006.258.00:12:24.86#ibcon#about to write, iclass 15, count 0 2006.258.00:12:24.86#ibcon#wrote, iclass 15, count 0 2006.258.00:12:24.86#ibcon#about to read 3, iclass 15, count 0 2006.258.00:12:24.89#ibcon#read 3, iclass 15, count 0 2006.258.00:12:24.89#ibcon#about to read 4, iclass 15, count 0 2006.258.00:12:24.89#ibcon#read 4, iclass 15, count 0 2006.258.00:12:24.89#ibcon#about to read 5, iclass 15, count 0 2006.258.00:12:24.89#ibcon#read 5, iclass 15, count 0 2006.258.00:12:24.89#ibcon#about to read 6, iclass 15, count 0 2006.258.00:12:24.89#ibcon#read 6, iclass 15, count 0 2006.258.00:12:24.89#ibcon#end of sib2, iclass 15, count 0 2006.258.00:12:24.89#ibcon#*after write, iclass 15, count 0 2006.258.00:12:24.89#ibcon#*before return 0, iclass 15, count 0 2006.258.00:12:24.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:24.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:24.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:12:24.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:12:24.89$vck44/valo=3,564.99 2006.258.00:12:24.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.258.00:12:24.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.258.00:12:24.89#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:24.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:24.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:24.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:24.89#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:12:24.89#ibcon#first serial, iclass 17, count 0 2006.258.00:12:24.89#ibcon#enter sib2, iclass 17, count 0 2006.258.00:12:24.89#ibcon#flushed, iclass 17, count 0 2006.258.00:12:24.89#ibcon#about to write, iclass 17, count 0 2006.258.00:12:24.89#ibcon#wrote, iclass 17, count 0 2006.258.00:12:24.89#ibcon#about to read 3, iclass 17, count 0 2006.258.00:12:24.91#ibcon#read 3, iclass 17, count 0 2006.258.00:12:24.91#ibcon#about to read 4, iclass 17, count 0 2006.258.00:12:24.91#ibcon#read 4, iclass 17, count 0 2006.258.00:12:24.91#ibcon#about to read 5, iclass 17, count 0 2006.258.00:12:24.91#ibcon#read 5, iclass 17, count 0 2006.258.00:12:24.91#ibcon#about to read 6, iclass 17, count 0 2006.258.00:12:24.91#ibcon#read 6, iclass 17, count 0 2006.258.00:12:24.91#ibcon#end of sib2, iclass 17, count 0 2006.258.00:12:24.91#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:12:24.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:12:24.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:12:24.91#ibcon#*before write, iclass 17, count 0 2006.258.00:12:24.91#ibcon#enter sib2, iclass 17, count 0 2006.258.00:12:24.91#ibcon#flushed, iclass 17, count 0 2006.258.00:12:24.91#ibcon#about to write, iclass 17, count 0 2006.258.00:12:24.91#ibcon#wrote, iclass 17, count 0 2006.258.00:12:24.91#ibcon#about to read 3, iclass 17, count 0 2006.258.00:12:24.95#ibcon#read 3, iclass 17, count 0 2006.258.00:12:24.95#ibcon#about to read 4, iclass 17, count 0 2006.258.00:12:24.95#ibcon#read 4, iclass 17, count 0 2006.258.00:12:24.95#ibcon#about to read 5, iclass 17, count 0 2006.258.00:12:24.95#ibcon#read 5, iclass 17, count 0 2006.258.00:12:24.95#ibcon#about to read 6, iclass 17, count 0 2006.258.00:12:24.95#ibcon#read 6, iclass 17, count 0 2006.258.00:12:24.95#ibcon#end of sib2, iclass 17, count 0 2006.258.00:12:24.95#ibcon#*after write, iclass 17, count 0 2006.258.00:12:24.95#ibcon#*before return 0, iclass 17, count 0 2006.258.00:12:24.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:24.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:24.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:12:24.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:12:24.95$vck44/va=3,8 2006.258.00:12:24.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.258.00:12:24.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.258.00:12:24.95#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:24.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:25.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:25.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:25.01#ibcon#enter wrdev, iclass 19, count 2 2006.258.00:12:25.01#ibcon#first serial, iclass 19, count 2 2006.258.00:12:25.01#ibcon#enter sib2, iclass 19, count 2 2006.258.00:12:25.01#ibcon#flushed, iclass 19, count 2 2006.258.00:12:25.01#ibcon#about to write, iclass 19, count 2 2006.258.00:12:25.01#ibcon#wrote, iclass 19, count 2 2006.258.00:12:25.01#ibcon#about to read 3, iclass 19, count 2 2006.258.00:12:25.03#ibcon#read 3, iclass 19, count 2 2006.258.00:12:25.03#ibcon#about to read 4, iclass 19, count 2 2006.258.00:12:25.03#ibcon#read 4, iclass 19, count 2 2006.258.00:12:25.03#ibcon#about to read 5, iclass 19, count 2 2006.258.00:12:25.03#ibcon#read 5, iclass 19, count 2 2006.258.00:12:25.03#ibcon#about to read 6, iclass 19, count 2 2006.258.00:12:25.03#ibcon#read 6, iclass 19, count 2 2006.258.00:12:25.03#ibcon#end of sib2, iclass 19, count 2 2006.258.00:12:25.03#ibcon#*mode == 0, iclass 19, count 2 2006.258.00:12:25.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.258.00:12:25.03#ibcon#[25=AT03-08\r\n] 2006.258.00:12:25.03#ibcon#*before write, iclass 19, count 2 2006.258.00:12:25.03#ibcon#enter sib2, iclass 19, count 2 2006.258.00:12:25.03#ibcon#flushed, iclass 19, count 2 2006.258.00:12:25.03#ibcon#about to write, iclass 19, count 2 2006.258.00:12:25.03#ibcon#wrote, iclass 19, count 2 2006.258.00:12:25.03#ibcon#about to read 3, iclass 19, count 2 2006.258.00:12:25.06#ibcon#read 3, iclass 19, count 2 2006.258.00:12:25.06#ibcon#about to read 4, iclass 19, count 2 2006.258.00:12:25.06#ibcon#read 4, iclass 19, count 2 2006.258.00:12:25.06#ibcon#about to read 5, iclass 19, count 2 2006.258.00:12:25.06#ibcon#read 5, iclass 19, count 2 2006.258.00:12:25.06#ibcon#about to read 6, iclass 19, count 2 2006.258.00:12:25.06#ibcon#read 6, iclass 19, count 2 2006.258.00:12:25.06#ibcon#end of sib2, iclass 19, count 2 2006.258.00:12:25.06#ibcon#*after write, iclass 19, count 2 2006.258.00:12:25.06#ibcon#*before return 0, iclass 19, count 2 2006.258.00:12:25.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:25.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:25.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.258.00:12:25.06#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:25.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:25.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:25.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:25.18#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:12:25.18#ibcon#first serial, iclass 19, count 0 2006.258.00:12:25.18#ibcon#enter sib2, iclass 19, count 0 2006.258.00:12:25.18#ibcon#flushed, iclass 19, count 0 2006.258.00:12:25.18#ibcon#about to write, iclass 19, count 0 2006.258.00:12:25.18#ibcon#wrote, iclass 19, count 0 2006.258.00:12:25.18#ibcon#about to read 3, iclass 19, count 0 2006.258.00:12:25.20#ibcon#read 3, iclass 19, count 0 2006.258.00:12:25.20#ibcon#about to read 4, iclass 19, count 0 2006.258.00:12:25.20#ibcon#read 4, iclass 19, count 0 2006.258.00:12:25.20#ibcon#about to read 5, iclass 19, count 0 2006.258.00:12:25.20#ibcon#read 5, iclass 19, count 0 2006.258.00:12:25.20#ibcon#about to read 6, iclass 19, count 0 2006.258.00:12:25.20#ibcon#read 6, iclass 19, count 0 2006.258.00:12:25.20#ibcon#end of sib2, iclass 19, count 0 2006.258.00:12:25.20#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:12:25.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:12:25.20#ibcon#[25=USB\r\n] 2006.258.00:12:25.20#ibcon#*before write, iclass 19, count 0 2006.258.00:12:25.20#ibcon#enter sib2, iclass 19, count 0 2006.258.00:12:25.20#ibcon#flushed, iclass 19, count 0 2006.258.00:12:25.20#ibcon#about to write, iclass 19, count 0 2006.258.00:12:25.20#ibcon#wrote, iclass 19, count 0 2006.258.00:12:25.20#ibcon#about to read 3, iclass 19, count 0 2006.258.00:12:25.23#ibcon#read 3, iclass 19, count 0 2006.258.00:12:25.23#ibcon#about to read 4, iclass 19, count 0 2006.258.00:12:25.23#ibcon#read 4, iclass 19, count 0 2006.258.00:12:25.23#ibcon#about to read 5, iclass 19, count 0 2006.258.00:12:25.23#ibcon#read 5, iclass 19, count 0 2006.258.00:12:25.23#ibcon#about to read 6, iclass 19, count 0 2006.258.00:12:25.23#ibcon#read 6, iclass 19, count 0 2006.258.00:12:25.23#ibcon#end of sib2, iclass 19, count 0 2006.258.00:12:25.23#ibcon#*after write, iclass 19, count 0 2006.258.00:12:25.23#ibcon#*before return 0, iclass 19, count 0 2006.258.00:12:25.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:25.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:25.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:12:25.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:12:25.23$vck44/valo=4,624.99 2006.258.00:12:25.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.258.00:12:25.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.258.00:12:25.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:25.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:25.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:25.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:25.23#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:12:25.23#ibcon#first serial, iclass 21, count 0 2006.258.00:12:25.23#ibcon#enter sib2, iclass 21, count 0 2006.258.00:12:25.23#ibcon#flushed, iclass 21, count 0 2006.258.00:12:25.23#ibcon#about to write, iclass 21, count 0 2006.258.00:12:25.23#ibcon#wrote, iclass 21, count 0 2006.258.00:12:25.23#ibcon#about to read 3, iclass 21, count 0 2006.258.00:12:25.25#ibcon#read 3, iclass 21, count 0 2006.258.00:12:25.25#ibcon#about to read 4, iclass 21, count 0 2006.258.00:12:25.25#ibcon#read 4, iclass 21, count 0 2006.258.00:12:25.25#ibcon#about to read 5, iclass 21, count 0 2006.258.00:12:25.25#ibcon#read 5, iclass 21, count 0 2006.258.00:12:25.25#ibcon#about to read 6, iclass 21, count 0 2006.258.00:12:25.25#ibcon#read 6, iclass 21, count 0 2006.258.00:12:25.25#ibcon#end of sib2, iclass 21, count 0 2006.258.00:12:25.25#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:12:25.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:12:25.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:12:25.25#ibcon#*before write, iclass 21, count 0 2006.258.00:12:25.25#ibcon#enter sib2, iclass 21, count 0 2006.258.00:12:25.25#ibcon#flushed, iclass 21, count 0 2006.258.00:12:25.25#ibcon#about to write, iclass 21, count 0 2006.258.00:12:25.25#ibcon#wrote, iclass 21, count 0 2006.258.00:12:25.25#ibcon#about to read 3, iclass 21, count 0 2006.258.00:12:25.29#ibcon#read 3, iclass 21, count 0 2006.258.00:12:25.29#ibcon#about to read 4, iclass 21, count 0 2006.258.00:12:25.29#ibcon#read 4, iclass 21, count 0 2006.258.00:12:25.29#ibcon#about to read 5, iclass 21, count 0 2006.258.00:12:25.29#ibcon#read 5, iclass 21, count 0 2006.258.00:12:25.29#ibcon#about to read 6, iclass 21, count 0 2006.258.00:12:25.29#ibcon#read 6, iclass 21, count 0 2006.258.00:12:25.29#ibcon#end of sib2, iclass 21, count 0 2006.258.00:12:25.29#ibcon#*after write, iclass 21, count 0 2006.258.00:12:25.29#ibcon#*before return 0, iclass 21, count 0 2006.258.00:12:25.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:25.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:25.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:12:25.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:12:25.29$vck44/va=4,7 2006.258.00:12:25.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.258.00:12:25.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.258.00:12:25.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:25.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:25.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:25.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:25.35#ibcon#enter wrdev, iclass 23, count 2 2006.258.00:12:25.35#ibcon#first serial, iclass 23, count 2 2006.258.00:12:25.35#ibcon#enter sib2, iclass 23, count 2 2006.258.00:12:25.35#ibcon#flushed, iclass 23, count 2 2006.258.00:12:25.35#ibcon#about to write, iclass 23, count 2 2006.258.00:12:25.35#ibcon#wrote, iclass 23, count 2 2006.258.00:12:25.35#ibcon#about to read 3, iclass 23, count 2 2006.258.00:12:25.37#ibcon#read 3, iclass 23, count 2 2006.258.00:12:25.37#ibcon#about to read 4, iclass 23, count 2 2006.258.00:12:25.37#ibcon#read 4, iclass 23, count 2 2006.258.00:12:25.37#ibcon#about to read 5, iclass 23, count 2 2006.258.00:12:25.37#ibcon#read 5, iclass 23, count 2 2006.258.00:12:25.37#ibcon#about to read 6, iclass 23, count 2 2006.258.00:12:25.37#ibcon#read 6, iclass 23, count 2 2006.258.00:12:25.37#ibcon#end of sib2, iclass 23, count 2 2006.258.00:12:25.37#ibcon#*mode == 0, iclass 23, count 2 2006.258.00:12:25.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.258.00:12:25.37#ibcon#[25=AT04-07\r\n] 2006.258.00:12:25.37#ibcon#*before write, iclass 23, count 2 2006.258.00:12:25.37#ibcon#enter sib2, iclass 23, count 2 2006.258.00:12:25.37#ibcon#flushed, iclass 23, count 2 2006.258.00:12:25.37#ibcon#about to write, iclass 23, count 2 2006.258.00:12:25.37#ibcon#wrote, iclass 23, count 2 2006.258.00:12:25.37#ibcon#about to read 3, iclass 23, count 2 2006.258.00:12:25.40#ibcon#read 3, iclass 23, count 2 2006.258.00:12:25.40#ibcon#about to read 4, iclass 23, count 2 2006.258.00:12:25.40#ibcon#read 4, iclass 23, count 2 2006.258.00:12:25.40#ibcon#about to read 5, iclass 23, count 2 2006.258.00:12:25.40#ibcon#read 5, iclass 23, count 2 2006.258.00:12:25.40#ibcon#about to read 6, iclass 23, count 2 2006.258.00:12:25.40#ibcon#read 6, iclass 23, count 2 2006.258.00:12:25.40#ibcon#end of sib2, iclass 23, count 2 2006.258.00:12:25.40#ibcon#*after write, iclass 23, count 2 2006.258.00:12:25.40#ibcon#*before return 0, iclass 23, count 2 2006.258.00:12:25.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:25.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:25.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.258.00:12:25.40#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:25.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:25.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:25.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:25.52#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:12:25.52#ibcon#first serial, iclass 23, count 0 2006.258.00:12:25.52#ibcon#enter sib2, iclass 23, count 0 2006.258.00:12:25.52#ibcon#flushed, iclass 23, count 0 2006.258.00:12:25.52#ibcon#about to write, iclass 23, count 0 2006.258.00:12:25.52#ibcon#wrote, iclass 23, count 0 2006.258.00:12:25.52#ibcon#about to read 3, iclass 23, count 0 2006.258.00:12:25.54#ibcon#read 3, iclass 23, count 0 2006.258.00:12:25.54#ibcon#about to read 4, iclass 23, count 0 2006.258.00:12:25.54#ibcon#read 4, iclass 23, count 0 2006.258.00:12:25.54#ibcon#about to read 5, iclass 23, count 0 2006.258.00:12:25.54#ibcon#read 5, iclass 23, count 0 2006.258.00:12:25.54#ibcon#about to read 6, iclass 23, count 0 2006.258.00:12:25.54#ibcon#read 6, iclass 23, count 0 2006.258.00:12:25.54#ibcon#end of sib2, iclass 23, count 0 2006.258.00:12:25.54#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:12:25.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:12:25.54#ibcon#[25=USB\r\n] 2006.258.00:12:25.54#ibcon#*before write, iclass 23, count 0 2006.258.00:12:25.54#ibcon#enter sib2, iclass 23, count 0 2006.258.00:12:25.54#ibcon#flushed, iclass 23, count 0 2006.258.00:12:25.54#ibcon#about to write, iclass 23, count 0 2006.258.00:12:25.54#ibcon#wrote, iclass 23, count 0 2006.258.00:12:25.54#ibcon#about to read 3, iclass 23, count 0 2006.258.00:12:25.57#ibcon#read 3, iclass 23, count 0 2006.258.00:12:25.57#ibcon#about to read 4, iclass 23, count 0 2006.258.00:12:25.57#ibcon#read 4, iclass 23, count 0 2006.258.00:12:25.57#ibcon#about to read 5, iclass 23, count 0 2006.258.00:12:25.57#ibcon#read 5, iclass 23, count 0 2006.258.00:12:25.57#ibcon#about to read 6, iclass 23, count 0 2006.258.00:12:25.57#ibcon#read 6, iclass 23, count 0 2006.258.00:12:25.57#ibcon#end of sib2, iclass 23, count 0 2006.258.00:12:25.57#ibcon#*after write, iclass 23, count 0 2006.258.00:12:25.57#ibcon#*before return 0, iclass 23, count 0 2006.258.00:12:25.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:25.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:25.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:12:25.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:12:25.57$vck44/valo=5,734.99 2006.258.00:12:25.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.00:12:25.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.00:12:25.57#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:25.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:25.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:25.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:25.57#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:12:25.57#ibcon#first serial, iclass 25, count 0 2006.258.00:12:25.57#ibcon#enter sib2, iclass 25, count 0 2006.258.00:12:25.57#ibcon#flushed, iclass 25, count 0 2006.258.00:12:25.57#ibcon#about to write, iclass 25, count 0 2006.258.00:12:25.57#ibcon#wrote, iclass 25, count 0 2006.258.00:12:25.57#ibcon#about to read 3, iclass 25, count 0 2006.258.00:12:25.59#ibcon#read 3, iclass 25, count 0 2006.258.00:12:25.59#ibcon#about to read 4, iclass 25, count 0 2006.258.00:12:25.59#ibcon#read 4, iclass 25, count 0 2006.258.00:12:25.59#ibcon#about to read 5, iclass 25, count 0 2006.258.00:12:25.59#ibcon#read 5, iclass 25, count 0 2006.258.00:12:25.59#ibcon#about to read 6, iclass 25, count 0 2006.258.00:12:25.59#ibcon#read 6, iclass 25, count 0 2006.258.00:12:25.59#ibcon#end of sib2, iclass 25, count 0 2006.258.00:12:25.59#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:12:25.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:12:25.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:12:25.59#ibcon#*before write, iclass 25, count 0 2006.258.00:12:25.59#ibcon#enter sib2, iclass 25, count 0 2006.258.00:12:25.59#ibcon#flushed, iclass 25, count 0 2006.258.00:12:25.59#ibcon#about to write, iclass 25, count 0 2006.258.00:12:25.59#ibcon#wrote, iclass 25, count 0 2006.258.00:12:25.59#ibcon#about to read 3, iclass 25, count 0 2006.258.00:12:25.63#ibcon#read 3, iclass 25, count 0 2006.258.00:12:25.63#ibcon#about to read 4, iclass 25, count 0 2006.258.00:12:25.63#ibcon#read 4, iclass 25, count 0 2006.258.00:12:25.63#ibcon#about to read 5, iclass 25, count 0 2006.258.00:12:25.63#ibcon#read 5, iclass 25, count 0 2006.258.00:12:25.63#ibcon#about to read 6, iclass 25, count 0 2006.258.00:12:25.63#ibcon#read 6, iclass 25, count 0 2006.258.00:12:25.63#ibcon#end of sib2, iclass 25, count 0 2006.258.00:12:25.63#ibcon#*after write, iclass 25, count 0 2006.258.00:12:25.63#ibcon#*before return 0, iclass 25, count 0 2006.258.00:12:25.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:25.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:25.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:12:25.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:12:25.63$vck44/va=5,4 2006.258.00:12:25.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.258.00:12:25.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.258.00:12:25.63#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:25.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:25.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:25.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:25.69#ibcon#enter wrdev, iclass 27, count 2 2006.258.00:12:25.69#ibcon#first serial, iclass 27, count 2 2006.258.00:12:25.69#ibcon#enter sib2, iclass 27, count 2 2006.258.00:12:25.69#ibcon#flushed, iclass 27, count 2 2006.258.00:12:25.69#ibcon#about to write, iclass 27, count 2 2006.258.00:12:25.69#ibcon#wrote, iclass 27, count 2 2006.258.00:12:25.69#ibcon#about to read 3, iclass 27, count 2 2006.258.00:12:25.71#ibcon#read 3, iclass 27, count 2 2006.258.00:12:25.71#ibcon#about to read 4, iclass 27, count 2 2006.258.00:12:25.71#ibcon#read 4, iclass 27, count 2 2006.258.00:12:25.71#ibcon#about to read 5, iclass 27, count 2 2006.258.00:12:25.71#ibcon#read 5, iclass 27, count 2 2006.258.00:12:25.71#ibcon#about to read 6, iclass 27, count 2 2006.258.00:12:25.71#ibcon#read 6, iclass 27, count 2 2006.258.00:12:25.71#ibcon#end of sib2, iclass 27, count 2 2006.258.00:12:25.71#ibcon#*mode == 0, iclass 27, count 2 2006.258.00:12:25.71#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.258.00:12:25.71#ibcon#[25=AT05-04\r\n] 2006.258.00:12:25.71#ibcon#*before write, iclass 27, count 2 2006.258.00:12:25.71#ibcon#enter sib2, iclass 27, count 2 2006.258.00:12:25.71#ibcon#flushed, iclass 27, count 2 2006.258.00:12:25.71#ibcon#about to write, iclass 27, count 2 2006.258.00:12:25.71#ibcon#wrote, iclass 27, count 2 2006.258.00:12:25.71#ibcon#about to read 3, iclass 27, count 2 2006.258.00:12:25.74#ibcon#read 3, iclass 27, count 2 2006.258.00:12:25.74#ibcon#about to read 4, iclass 27, count 2 2006.258.00:12:25.74#ibcon#read 4, iclass 27, count 2 2006.258.00:12:25.74#ibcon#about to read 5, iclass 27, count 2 2006.258.00:12:25.74#ibcon#read 5, iclass 27, count 2 2006.258.00:12:25.74#ibcon#about to read 6, iclass 27, count 2 2006.258.00:12:25.74#ibcon#read 6, iclass 27, count 2 2006.258.00:12:25.74#ibcon#end of sib2, iclass 27, count 2 2006.258.00:12:25.74#ibcon#*after write, iclass 27, count 2 2006.258.00:12:25.74#ibcon#*before return 0, iclass 27, count 2 2006.258.00:12:25.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:25.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:25.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.258.00:12:25.74#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:25.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:25.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:25.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:25.86#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:12:25.86#ibcon#first serial, iclass 27, count 0 2006.258.00:12:25.86#ibcon#enter sib2, iclass 27, count 0 2006.258.00:12:25.86#ibcon#flushed, iclass 27, count 0 2006.258.00:12:25.86#ibcon#about to write, iclass 27, count 0 2006.258.00:12:25.86#ibcon#wrote, iclass 27, count 0 2006.258.00:12:25.86#ibcon#about to read 3, iclass 27, count 0 2006.258.00:12:25.88#ibcon#read 3, iclass 27, count 0 2006.258.00:12:25.88#ibcon#about to read 4, iclass 27, count 0 2006.258.00:12:25.88#ibcon#read 4, iclass 27, count 0 2006.258.00:12:25.88#ibcon#about to read 5, iclass 27, count 0 2006.258.00:12:25.88#ibcon#read 5, iclass 27, count 0 2006.258.00:12:25.88#ibcon#about to read 6, iclass 27, count 0 2006.258.00:12:25.88#ibcon#read 6, iclass 27, count 0 2006.258.00:12:25.88#ibcon#end of sib2, iclass 27, count 0 2006.258.00:12:25.88#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:12:25.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:12:25.88#ibcon#[25=USB\r\n] 2006.258.00:12:25.88#ibcon#*before write, iclass 27, count 0 2006.258.00:12:25.88#ibcon#enter sib2, iclass 27, count 0 2006.258.00:12:25.88#ibcon#flushed, iclass 27, count 0 2006.258.00:12:25.88#ibcon#about to write, iclass 27, count 0 2006.258.00:12:25.88#ibcon#wrote, iclass 27, count 0 2006.258.00:12:25.88#ibcon#about to read 3, iclass 27, count 0 2006.258.00:12:25.91#ibcon#read 3, iclass 27, count 0 2006.258.00:12:25.91#ibcon#about to read 4, iclass 27, count 0 2006.258.00:12:25.91#ibcon#read 4, iclass 27, count 0 2006.258.00:12:25.91#ibcon#about to read 5, iclass 27, count 0 2006.258.00:12:25.91#ibcon#read 5, iclass 27, count 0 2006.258.00:12:25.91#ibcon#about to read 6, iclass 27, count 0 2006.258.00:12:25.91#ibcon#read 6, iclass 27, count 0 2006.258.00:12:25.91#ibcon#end of sib2, iclass 27, count 0 2006.258.00:12:25.91#ibcon#*after write, iclass 27, count 0 2006.258.00:12:25.91#ibcon#*before return 0, iclass 27, count 0 2006.258.00:12:25.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:25.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:25.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:12:25.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:12:25.91$vck44/valo=6,814.99 2006.258.00:12:25.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.00:12:25.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.00:12:25.91#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:25.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:25.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:25.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:25.91#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:12:25.91#ibcon#first serial, iclass 29, count 0 2006.258.00:12:25.91#ibcon#enter sib2, iclass 29, count 0 2006.258.00:12:25.91#ibcon#flushed, iclass 29, count 0 2006.258.00:12:25.91#ibcon#about to write, iclass 29, count 0 2006.258.00:12:25.91#ibcon#wrote, iclass 29, count 0 2006.258.00:12:25.91#ibcon#about to read 3, iclass 29, count 0 2006.258.00:12:25.93#ibcon#read 3, iclass 29, count 0 2006.258.00:12:25.93#ibcon#about to read 4, iclass 29, count 0 2006.258.00:12:25.93#ibcon#read 4, iclass 29, count 0 2006.258.00:12:25.93#ibcon#about to read 5, iclass 29, count 0 2006.258.00:12:25.93#ibcon#read 5, iclass 29, count 0 2006.258.00:12:25.93#ibcon#about to read 6, iclass 29, count 0 2006.258.00:12:25.93#ibcon#read 6, iclass 29, count 0 2006.258.00:12:25.93#ibcon#end of sib2, iclass 29, count 0 2006.258.00:12:25.93#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:12:25.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:12:25.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:12:25.93#ibcon#*before write, iclass 29, count 0 2006.258.00:12:25.93#ibcon#enter sib2, iclass 29, count 0 2006.258.00:12:25.93#ibcon#flushed, iclass 29, count 0 2006.258.00:12:25.93#ibcon#about to write, iclass 29, count 0 2006.258.00:12:25.93#ibcon#wrote, iclass 29, count 0 2006.258.00:12:25.93#ibcon#about to read 3, iclass 29, count 0 2006.258.00:12:25.97#ibcon#read 3, iclass 29, count 0 2006.258.00:12:25.97#ibcon#about to read 4, iclass 29, count 0 2006.258.00:12:25.97#ibcon#read 4, iclass 29, count 0 2006.258.00:12:25.97#ibcon#about to read 5, iclass 29, count 0 2006.258.00:12:25.97#ibcon#read 5, iclass 29, count 0 2006.258.00:12:25.97#ibcon#about to read 6, iclass 29, count 0 2006.258.00:12:25.97#ibcon#read 6, iclass 29, count 0 2006.258.00:12:25.97#ibcon#end of sib2, iclass 29, count 0 2006.258.00:12:25.97#ibcon#*after write, iclass 29, count 0 2006.258.00:12:25.97#ibcon#*before return 0, iclass 29, count 0 2006.258.00:12:25.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:25.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:25.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:12:25.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:12:25.97$vck44/va=6,4 2006.258.00:12:25.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.00:12:25.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.00:12:25.97#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:25.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:26.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:26.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:26.03#ibcon#enter wrdev, iclass 31, count 2 2006.258.00:12:26.03#ibcon#first serial, iclass 31, count 2 2006.258.00:12:26.03#ibcon#enter sib2, iclass 31, count 2 2006.258.00:12:26.03#ibcon#flushed, iclass 31, count 2 2006.258.00:12:26.03#ibcon#about to write, iclass 31, count 2 2006.258.00:12:26.03#ibcon#wrote, iclass 31, count 2 2006.258.00:12:26.03#ibcon#about to read 3, iclass 31, count 2 2006.258.00:12:26.05#ibcon#read 3, iclass 31, count 2 2006.258.00:12:26.05#ibcon#about to read 4, iclass 31, count 2 2006.258.00:12:26.05#ibcon#read 4, iclass 31, count 2 2006.258.00:12:26.05#ibcon#about to read 5, iclass 31, count 2 2006.258.00:12:26.05#ibcon#read 5, iclass 31, count 2 2006.258.00:12:26.05#ibcon#about to read 6, iclass 31, count 2 2006.258.00:12:26.05#ibcon#read 6, iclass 31, count 2 2006.258.00:12:26.05#ibcon#end of sib2, iclass 31, count 2 2006.258.00:12:26.05#ibcon#*mode == 0, iclass 31, count 2 2006.258.00:12:26.05#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.00:12:26.05#ibcon#[25=AT06-04\r\n] 2006.258.00:12:26.05#ibcon#*before write, iclass 31, count 2 2006.258.00:12:26.05#ibcon#enter sib2, iclass 31, count 2 2006.258.00:12:26.05#ibcon#flushed, iclass 31, count 2 2006.258.00:12:26.05#ibcon#about to write, iclass 31, count 2 2006.258.00:12:26.05#ibcon#wrote, iclass 31, count 2 2006.258.00:12:26.05#ibcon#about to read 3, iclass 31, count 2 2006.258.00:12:26.08#ibcon#read 3, iclass 31, count 2 2006.258.00:12:26.08#ibcon#about to read 4, iclass 31, count 2 2006.258.00:12:26.08#ibcon#read 4, iclass 31, count 2 2006.258.00:12:26.08#ibcon#about to read 5, iclass 31, count 2 2006.258.00:12:26.08#ibcon#read 5, iclass 31, count 2 2006.258.00:12:26.08#ibcon#about to read 6, iclass 31, count 2 2006.258.00:12:26.08#ibcon#read 6, iclass 31, count 2 2006.258.00:12:26.08#ibcon#end of sib2, iclass 31, count 2 2006.258.00:12:26.08#ibcon#*after write, iclass 31, count 2 2006.258.00:12:26.08#ibcon#*before return 0, iclass 31, count 2 2006.258.00:12:26.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:26.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:26.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.00:12:26.08#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:26.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:26.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:26.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:26.20#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:12:26.20#ibcon#first serial, iclass 31, count 0 2006.258.00:12:26.20#ibcon#enter sib2, iclass 31, count 0 2006.258.00:12:26.20#ibcon#flushed, iclass 31, count 0 2006.258.00:12:26.20#ibcon#about to write, iclass 31, count 0 2006.258.00:12:26.20#ibcon#wrote, iclass 31, count 0 2006.258.00:12:26.20#ibcon#about to read 3, iclass 31, count 0 2006.258.00:12:26.22#ibcon#read 3, iclass 31, count 0 2006.258.00:12:26.22#ibcon#about to read 4, iclass 31, count 0 2006.258.00:12:26.22#ibcon#read 4, iclass 31, count 0 2006.258.00:12:26.22#ibcon#about to read 5, iclass 31, count 0 2006.258.00:12:26.22#ibcon#read 5, iclass 31, count 0 2006.258.00:12:26.22#ibcon#about to read 6, iclass 31, count 0 2006.258.00:12:26.22#ibcon#read 6, iclass 31, count 0 2006.258.00:12:26.22#ibcon#end of sib2, iclass 31, count 0 2006.258.00:12:26.22#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:12:26.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:12:26.22#ibcon#[25=USB\r\n] 2006.258.00:12:26.22#ibcon#*before write, iclass 31, count 0 2006.258.00:12:26.22#ibcon#enter sib2, iclass 31, count 0 2006.258.00:12:26.22#ibcon#flushed, iclass 31, count 0 2006.258.00:12:26.22#ibcon#about to write, iclass 31, count 0 2006.258.00:12:26.22#ibcon#wrote, iclass 31, count 0 2006.258.00:12:26.22#ibcon#about to read 3, iclass 31, count 0 2006.258.00:12:26.25#ibcon#read 3, iclass 31, count 0 2006.258.00:12:26.25#ibcon#about to read 4, iclass 31, count 0 2006.258.00:12:26.25#ibcon#read 4, iclass 31, count 0 2006.258.00:12:26.25#ibcon#about to read 5, iclass 31, count 0 2006.258.00:12:26.25#ibcon#read 5, iclass 31, count 0 2006.258.00:12:26.25#ibcon#about to read 6, iclass 31, count 0 2006.258.00:12:26.25#ibcon#read 6, iclass 31, count 0 2006.258.00:12:26.25#ibcon#end of sib2, iclass 31, count 0 2006.258.00:12:26.25#ibcon#*after write, iclass 31, count 0 2006.258.00:12:26.25#ibcon#*before return 0, iclass 31, count 0 2006.258.00:12:26.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:26.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:26.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:12:26.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:12:26.25$vck44/valo=7,864.99 2006.258.00:12:26.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.00:12:26.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.00:12:26.25#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:26.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:26.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:26.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:26.25#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:12:26.25#ibcon#first serial, iclass 33, count 0 2006.258.00:12:26.25#ibcon#enter sib2, iclass 33, count 0 2006.258.00:12:26.25#ibcon#flushed, iclass 33, count 0 2006.258.00:12:26.25#ibcon#about to write, iclass 33, count 0 2006.258.00:12:26.25#ibcon#wrote, iclass 33, count 0 2006.258.00:12:26.25#ibcon#about to read 3, iclass 33, count 0 2006.258.00:12:26.27#ibcon#read 3, iclass 33, count 0 2006.258.00:12:26.27#ibcon#about to read 4, iclass 33, count 0 2006.258.00:12:26.27#ibcon#read 4, iclass 33, count 0 2006.258.00:12:26.27#ibcon#about to read 5, iclass 33, count 0 2006.258.00:12:26.27#ibcon#read 5, iclass 33, count 0 2006.258.00:12:26.27#ibcon#about to read 6, iclass 33, count 0 2006.258.00:12:26.27#ibcon#read 6, iclass 33, count 0 2006.258.00:12:26.27#ibcon#end of sib2, iclass 33, count 0 2006.258.00:12:26.27#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:12:26.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:12:26.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:12:26.27#ibcon#*before write, iclass 33, count 0 2006.258.00:12:26.27#ibcon#enter sib2, iclass 33, count 0 2006.258.00:12:26.27#ibcon#flushed, iclass 33, count 0 2006.258.00:12:26.27#ibcon#about to write, iclass 33, count 0 2006.258.00:12:26.27#ibcon#wrote, iclass 33, count 0 2006.258.00:12:26.27#ibcon#about to read 3, iclass 33, count 0 2006.258.00:12:26.31#ibcon#read 3, iclass 33, count 0 2006.258.00:12:26.31#ibcon#about to read 4, iclass 33, count 0 2006.258.00:12:26.31#ibcon#read 4, iclass 33, count 0 2006.258.00:12:26.31#ibcon#about to read 5, iclass 33, count 0 2006.258.00:12:26.31#ibcon#read 5, iclass 33, count 0 2006.258.00:12:26.31#ibcon#about to read 6, iclass 33, count 0 2006.258.00:12:26.31#ibcon#read 6, iclass 33, count 0 2006.258.00:12:26.31#ibcon#end of sib2, iclass 33, count 0 2006.258.00:12:26.31#ibcon#*after write, iclass 33, count 0 2006.258.00:12:26.31#ibcon#*before return 0, iclass 33, count 0 2006.258.00:12:26.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:26.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:26.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:12:26.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:12:26.31$vck44/va=7,4 2006.258.00:12:26.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.00:12:26.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.00:12:26.31#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:26.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:26.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:26.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:26.37#ibcon#enter wrdev, iclass 35, count 2 2006.258.00:12:26.37#ibcon#first serial, iclass 35, count 2 2006.258.00:12:26.37#ibcon#enter sib2, iclass 35, count 2 2006.258.00:12:26.37#ibcon#flushed, iclass 35, count 2 2006.258.00:12:26.37#ibcon#about to write, iclass 35, count 2 2006.258.00:12:26.37#ibcon#wrote, iclass 35, count 2 2006.258.00:12:26.37#ibcon#about to read 3, iclass 35, count 2 2006.258.00:12:26.39#ibcon#read 3, iclass 35, count 2 2006.258.00:12:26.39#ibcon#about to read 4, iclass 35, count 2 2006.258.00:12:26.39#ibcon#read 4, iclass 35, count 2 2006.258.00:12:26.39#ibcon#about to read 5, iclass 35, count 2 2006.258.00:12:26.39#ibcon#read 5, iclass 35, count 2 2006.258.00:12:26.39#ibcon#about to read 6, iclass 35, count 2 2006.258.00:12:26.39#ibcon#read 6, iclass 35, count 2 2006.258.00:12:26.39#ibcon#end of sib2, iclass 35, count 2 2006.258.00:12:26.39#ibcon#*mode == 0, iclass 35, count 2 2006.258.00:12:26.39#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.00:12:26.39#ibcon#[25=AT07-04\r\n] 2006.258.00:12:26.39#ibcon#*before write, iclass 35, count 2 2006.258.00:12:26.39#ibcon#enter sib2, iclass 35, count 2 2006.258.00:12:26.39#ibcon#flushed, iclass 35, count 2 2006.258.00:12:26.39#ibcon#about to write, iclass 35, count 2 2006.258.00:12:26.39#ibcon#wrote, iclass 35, count 2 2006.258.00:12:26.39#ibcon#about to read 3, iclass 35, count 2 2006.258.00:12:26.42#ibcon#read 3, iclass 35, count 2 2006.258.00:12:26.45#ibcon#about to read 4, iclass 35, count 2 2006.258.00:12:26.45#ibcon#read 4, iclass 35, count 2 2006.258.00:12:26.45#ibcon#about to read 5, iclass 35, count 2 2006.258.00:12:26.45#ibcon#read 5, iclass 35, count 2 2006.258.00:12:26.45#ibcon#about to read 6, iclass 35, count 2 2006.258.00:12:26.45#ibcon#read 6, iclass 35, count 2 2006.258.00:12:26.45#ibcon#end of sib2, iclass 35, count 2 2006.258.00:12:26.45#ibcon#*after write, iclass 35, count 2 2006.258.00:12:26.45#ibcon#*before return 0, iclass 35, count 2 2006.258.00:12:26.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:26.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:26.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.00:12:26.46#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:26.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:26.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:26.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:26.56#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:12:26.56#ibcon#first serial, iclass 35, count 0 2006.258.00:12:26.56#ibcon#enter sib2, iclass 35, count 0 2006.258.00:12:26.56#ibcon#flushed, iclass 35, count 0 2006.258.00:12:26.56#ibcon#about to write, iclass 35, count 0 2006.258.00:12:26.56#ibcon#wrote, iclass 35, count 0 2006.258.00:12:26.56#ibcon#about to read 3, iclass 35, count 0 2006.258.00:12:26.58#ibcon#read 3, iclass 35, count 0 2006.258.00:12:26.58#ibcon#about to read 4, iclass 35, count 0 2006.258.00:12:26.58#ibcon#read 4, iclass 35, count 0 2006.258.00:12:26.58#ibcon#about to read 5, iclass 35, count 0 2006.258.00:12:26.58#ibcon#read 5, iclass 35, count 0 2006.258.00:12:26.58#ibcon#about to read 6, iclass 35, count 0 2006.258.00:12:26.58#ibcon#read 6, iclass 35, count 0 2006.258.00:12:26.58#ibcon#end of sib2, iclass 35, count 0 2006.258.00:12:26.58#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:12:26.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:12:26.58#ibcon#[25=USB\r\n] 2006.258.00:12:26.58#ibcon#*before write, iclass 35, count 0 2006.258.00:12:26.58#ibcon#enter sib2, iclass 35, count 0 2006.258.00:12:26.58#ibcon#flushed, iclass 35, count 0 2006.258.00:12:26.58#ibcon#about to write, iclass 35, count 0 2006.258.00:12:26.58#ibcon#wrote, iclass 35, count 0 2006.258.00:12:26.58#ibcon#about to read 3, iclass 35, count 0 2006.258.00:12:26.61#ibcon#read 3, iclass 35, count 0 2006.258.00:12:26.61#ibcon#about to read 4, iclass 35, count 0 2006.258.00:12:26.61#ibcon#read 4, iclass 35, count 0 2006.258.00:12:26.61#ibcon#about to read 5, iclass 35, count 0 2006.258.00:12:26.61#ibcon#read 5, iclass 35, count 0 2006.258.00:12:26.61#ibcon#about to read 6, iclass 35, count 0 2006.258.00:12:26.61#ibcon#read 6, iclass 35, count 0 2006.258.00:12:26.61#ibcon#end of sib2, iclass 35, count 0 2006.258.00:12:26.61#ibcon#*after write, iclass 35, count 0 2006.258.00:12:26.61#ibcon#*before return 0, iclass 35, count 0 2006.258.00:12:26.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:26.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:26.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:12:26.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:12:26.61$vck44/valo=8,884.99 2006.258.00:12:26.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.00:12:26.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.00:12:26.61#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:26.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:26.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:26.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:26.61#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:12:26.61#ibcon#first serial, iclass 37, count 0 2006.258.00:12:26.61#ibcon#enter sib2, iclass 37, count 0 2006.258.00:12:26.61#ibcon#flushed, iclass 37, count 0 2006.258.00:12:26.61#ibcon#about to write, iclass 37, count 0 2006.258.00:12:26.61#ibcon#wrote, iclass 37, count 0 2006.258.00:12:26.61#ibcon#about to read 3, iclass 37, count 0 2006.258.00:12:26.63#ibcon#read 3, iclass 37, count 0 2006.258.00:12:26.63#ibcon#about to read 4, iclass 37, count 0 2006.258.00:12:26.63#ibcon#read 4, iclass 37, count 0 2006.258.00:12:26.63#ibcon#about to read 5, iclass 37, count 0 2006.258.00:12:26.63#ibcon#read 5, iclass 37, count 0 2006.258.00:12:26.63#ibcon#about to read 6, iclass 37, count 0 2006.258.00:12:26.63#ibcon#read 6, iclass 37, count 0 2006.258.00:12:26.63#ibcon#end of sib2, iclass 37, count 0 2006.258.00:12:26.63#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:12:26.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:12:26.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:12:26.63#ibcon#*before write, iclass 37, count 0 2006.258.00:12:26.63#ibcon#enter sib2, iclass 37, count 0 2006.258.00:12:26.63#ibcon#flushed, iclass 37, count 0 2006.258.00:12:26.63#ibcon#about to write, iclass 37, count 0 2006.258.00:12:26.63#ibcon#wrote, iclass 37, count 0 2006.258.00:12:26.63#ibcon#about to read 3, iclass 37, count 0 2006.258.00:12:26.67#ibcon#read 3, iclass 37, count 0 2006.258.00:12:26.67#ibcon#about to read 4, iclass 37, count 0 2006.258.00:12:26.67#ibcon#read 4, iclass 37, count 0 2006.258.00:12:26.67#ibcon#about to read 5, iclass 37, count 0 2006.258.00:12:26.67#ibcon#read 5, iclass 37, count 0 2006.258.00:12:26.67#ibcon#about to read 6, iclass 37, count 0 2006.258.00:12:26.67#ibcon#read 6, iclass 37, count 0 2006.258.00:12:26.67#ibcon#end of sib2, iclass 37, count 0 2006.258.00:12:26.67#ibcon#*after write, iclass 37, count 0 2006.258.00:12:26.67#ibcon#*before return 0, iclass 37, count 0 2006.258.00:12:26.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:26.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:26.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:12:26.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:12:26.67$vck44/va=8,4 2006.258.00:12:26.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.258.00:12:26.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.258.00:12:26.67#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:26.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:12:26.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:12:26.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:12:26.73#ibcon#enter wrdev, iclass 39, count 2 2006.258.00:12:26.73#ibcon#first serial, iclass 39, count 2 2006.258.00:12:26.73#ibcon#enter sib2, iclass 39, count 2 2006.258.00:12:26.73#ibcon#flushed, iclass 39, count 2 2006.258.00:12:26.73#ibcon#about to write, iclass 39, count 2 2006.258.00:12:26.73#ibcon#wrote, iclass 39, count 2 2006.258.00:12:26.73#ibcon#about to read 3, iclass 39, count 2 2006.258.00:12:26.75#ibcon#read 3, iclass 39, count 2 2006.258.00:12:26.75#ibcon#about to read 4, iclass 39, count 2 2006.258.00:12:26.75#ibcon#read 4, iclass 39, count 2 2006.258.00:12:26.75#ibcon#about to read 5, iclass 39, count 2 2006.258.00:12:26.75#ibcon#read 5, iclass 39, count 2 2006.258.00:12:26.75#ibcon#about to read 6, iclass 39, count 2 2006.258.00:12:26.75#ibcon#read 6, iclass 39, count 2 2006.258.00:12:26.75#ibcon#end of sib2, iclass 39, count 2 2006.258.00:12:26.75#ibcon#*mode == 0, iclass 39, count 2 2006.258.00:12:26.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.258.00:12:26.75#ibcon#[25=AT08-04\r\n] 2006.258.00:12:26.75#ibcon#*before write, iclass 39, count 2 2006.258.00:12:26.75#ibcon#enter sib2, iclass 39, count 2 2006.258.00:12:26.75#ibcon#flushed, iclass 39, count 2 2006.258.00:12:26.75#ibcon#about to write, iclass 39, count 2 2006.258.00:12:26.75#ibcon#wrote, iclass 39, count 2 2006.258.00:12:26.75#ibcon#about to read 3, iclass 39, count 2 2006.258.00:12:26.78#ibcon#read 3, iclass 39, count 2 2006.258.00:12:26.78#ibcon#about to read 4, iclass 39, count 2 2006.258.00:12:26.78#ibcon#read 4, iclass 39, count 2 2006.258.00:12:26.78#ibcon#about to read 5, iclass 39, count 2 2006.258.00:12:26.78#ibcon#read 5, iclass 39, count 2 2006.258.00:12:26.78#ibcon#about to read 6, iclass 39, count 2 2006.258.00:12:26.78#ibcon#read 6, iclass 39, count 2 2006.258.00:12:26.78#ibcon#end of sib2, iclass 39, count 2 2006.258.00:12:26.78#ibcon#*after write, iclass 39, count 2 2006.258.00:12:26.78#ibcon#*before return 0, iclass 39, count 2 2006.258.00:12:26.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:12:26.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:12:26.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.258.00:12:26.78#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:26.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:12:26.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:12:26.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:12:26.90#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:12:26.90#ibcon#first serial, iclass 39, count 0 2006.258.00:12:26.90#ibcon#enter sib2, iclass 39, count 0 2006.258.00:12:26.90#ibcon#flushed, iclass 39, count 0 2006.258.00:12:26.90#ibcon#about to write, iclass 39, count 0 2006.258.00:12:26.90#ibcon#wrote, iclass 39, count 0 2006.258.00:12:26.90#ibcon#about to read 3, iclass 39, count 0 2006.258.00:12:26.92#ibcon#read 3, iclass 39, count 0 2006.258.00:12:26.92#ibcon#about to read 4, iclass 39, count 0 2006.258.00:12:26.92#ibcon#read 4, iclass 39, count 0 2006.258.00:12:26.92#ibcon#about to read 5, iclass 39, count 0 2006.258.00:12:26.92#ibcon#read 5, iclass 39, count 0 2006.258.00:12:26.92#ibcon#about to read 6, iclass 39, count 0 2006.258.00:12:26.92#ibcon#read 6, iclass 39, count 0 2006.258.00:12:26.92#ibcon#end of sib2, iclass 39, count 0 2006.258.00:12:26.92#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:12:26.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:12:26.92#ibcon#[25=USB\r\n] 2006.258.00:12:26.92#ibcon#*before write, iclass 39, count 0 2006.258.00:12:26.92#ibcon#enter sib2, iclass 39, count 0 2006.258.00:12:26.92#ibcon#flushed, iclass 39, count 0 2006.258.00:12:26.92#ibcon#about to write, iclass 39, count 0 2006.258.00:12:26.92#ibcon#wrote, iclass 39, count 0 2006.258.00:12:26.92#ibcon#about to read 3, iclass 39, count 0 2006.258.00:12:26.95#ibcon#read 3, iclass 39, count 0 2006.258.00:12:26.95#ibcon#about to read 4, iclass 39, count 0 2006.258.00:12:26.95#ibcon#read 4, iclass 39, count 0 2006.258.00:12:26.95#ibcon#about to read 5, iclass 39, count 0 2006.258.00:12:26.95#ibcon#read 5, iclass 39, count 0 2006.258.00:12:26.95#ibcon#about to read 6, iclass 39, count 0 2006.258.00:12:26.95#ibcon#read 6, iclass 39, count 0 2006.258.00:12:26.95#ibcon#end of sib2, iclass 39, count 0 2006.258.00:12:26.95#ibcon#*after write, iclass 39, count 0 2006.258.00:12:26.95#ibcon#*before return 0, iclass 39, count 0 2006.258.00:12:26.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:12:26.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:12:26.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:12:26.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:12:26.95$vck44/vblo=1,629.99 2006.258.00:12:26.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.00:12:26.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.00:12:26.95#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:26.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:12:26.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:12:26.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:12:26.95#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:12:26.95#ibcon#first serial, iclass 3, count 0 2006.258.00:12:26.95#ibcon#enter sib2, iclass 3, count 0 2006.258.00:12:26.95#ibcon#flushed, iclass 3, count 0 2006.258.00:12:26.95#ibcon#about to write, iclass 3, count 0 2006.258.00:12:26.95#ibcon#wrote, iclass 3, count 0 2006.258.00:12:26.95#ibcon#about to read 3, iclass 3, count 0 2006.258.00:12:26.97#ibcon#read 3, iclass 3, count 0 2006.258.00:12:26.97#ibcon#about to read 4, iclass 3, count 0 2006.258.00:12:26.97#ibcon#read 4, iclass 3, count 0 2006.258.00:12:26.97#ibcon#about to read 5, iclass 3, count 0 2006.258.00:12:26.97#ibcon#read 5, iclass 3, count 0 2006.258.00:12:26.97#ibcon#about to read 6, iclass 3, count 0 2006.258.00:12:26.97#ibcon#read 6, iclass 3, count 0 2006.258.00:12:26.97#ibcon#end of sib2, iclass 3, count 0 2006.258.00:12:26.97#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:12:26.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:12:26.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:12:26.97#ibcon#*before write, iclass 3, count 0 2006.258.00:12:26.97#ibcon#enter sib2, iclass 3, count 0 2006.258.00:12:26.97#ibcon#flushed, iclass 3, count 0 2006.258.00:12:26.97#ibcon#about to write, iclass 3, count 0 2006.258.00:12:26.97#ibcon#wrote, iclass 3, count 0 2006.258.00:12:26.97#ibcon#about to read 3, iclass 3, count 0 2006.258.00:12:27.01#ibcon#read 3, iclass 3, count 0 2006.258.00:12:27.01#ibcon#about to read 4, iclass 3, count 0 2006.258.00:12:27.01#ibcon#read 4, iclass 3, count 0 2006.258.00:12:27.01#ibcon#about to read 5, iclass 3, count 0 2006.258.00:12:27.01#ibcon#read 5, iclass 3, count 0 2006.258.00:12:27.01#ibcon#about to read 6, iclass 3, count 0 2006.258.00:12:27.01#ibcon#read 6, iclass 3, count 0 2006.258.00:12:27.01#ibcon#end of sib2, iclass 3, count 0 2006.258.00:12:27.01#ibcon#*after write, iclass 3, count 0 2006.258.00:12:27.01#ibcon#*before return 0, iclass 3, count 0 2006.258.00:12:27.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:12:27.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:12:27.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:12:27.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:12:27.01$vck44/vb=1,4 2006.258.00:12:27.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.258.00:12:27.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.258.00:12:27.01#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:27.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:12:27.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:12:27.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:12:27.01#ibcon#enter wrdev, iclass 5, count 2 2006.258.00:12:27.01#ibcon#first serial, iclass 5, count 2 2006.258.00:12:27.01#ibcon#enter sib2, iclass 5, count 2 2006.258.00:12:27.01#ibcon#flushed, iclass 5, count 2 2006.258.00:12:27.01#ibcon#about to write, iclass 5, count 2 2006.258.00:12:27.01#ibcon#wrote, iclass 5, count 2 2006.258.00:12:27.01#ibcon#about to read 3, iclass 5, count 2 2006.258.00:12:27.03#ibcon#read 3, iclass 5, count 2 2006.258.00:12:27.03#ibcon#about to read 4, iclass 5, count 2 2006.258.00:12:27.03#ibcon#read 4, iclass 5, count 2 2006.258.00:12:27.03#ibcon#about to read 5, iclass 5, count 2 2006.258.00:12:27.03#ibcon#read 5, iclass 5, count 2 2006.258.00:12:27.03#ibcon#about to read 6, iclass 5, count 2 2006.258.00:12:27.03#ibcon#read 6, iclass 5, count 2 2006.258.00:12:27.03#ibcon#end of sib2, iclass 5, count 2 2006.258.00:12:27.03#ibcon#*mode == 0, iclass 5, count 2 2006.258.00:12:27.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.258.00:12:27.03#ibcon#[27=AT01-04\r\n] 2006.258.00:12:27.03#ibcon#*before write, iclass 5, count 2 2006.258.00:12:27.03#ibcon#enter sib2, iclass 5, count 2 2006.258.00:12:27.03#ibcon#flushed, iclass 5, count 2 2006.258.00:12:27.03#ibcon#about to write, iclass 5, count 2 2006.258.00:12:27.03#ibcon#wrote, iclass 5, count 2 2006.258.00:12:27.03#ibcon#about to read 3, iclass 5, count 2 2006.258.00:12:27.06#ibcon#read 3, iclass 5, count 2 2006.258.00:12:27.06#ibcon#about to read 4, iclass 5, count 2 2006.258.00:12:27.06#ibcon#read 4, iclass 5, count 2 2006.258.00:12:27.06#ibcon#about to read 5, iclass 5, count 2 2006.258.00:12:27.06#ibcon#read 5, iclass 5, count 2 2006.258.00:12:27.06#ibcon#about to read 6, iclass 5, count 2 2006.258.00:12:27.06#ibcon#read 6, iclass 5, count 2 2006.258.00:12:27.06#ibcon#end of sib2, iclass 5, count 2 2006.258.00:12:27.06#ibcon#*after write, iclass 5, count 2 2006.258.00:12:27.06#ibcon#*before return 0, iclass 5, count 2 2006.258.00:12:27.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:12:27.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:12:27.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.258.00:12:27.06#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:27.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:12:27.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:12:27.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:12:27.18#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:12:27.18#ibcon#first serial, iclass 5, count 0 2006.258.00:12:27.18#ibcon#enter sib2, iclass 5, count 0 2006.258.00:12:27.18#ibcon#flushed, iclass 5, count 0 2006.258.00:12:27.18#ibcon#about to write, iclass 5, count 0 2006.258.00:12:27.18#ibcon#wrote, iclass 5, count 0 2006.258.00:12:27.18#ibcon#about to read 3, iclass 5, count 0 2006.258.00:12:27.20#ibcon#read 3, iclass 5, count 0 2006.258.00:12:27.20#ibcon#about to read 4, iclass 5, count 0 2006.258.00:12:27.20#ibcon#read 4, iclass 5, count 0 2006.258.00:12:27.20#ibcon#about to read 5, iclass 5, count 0 2006.258.00:12:27.20#ibcon#read 5, iclass 5, count 0 2006.258.00:12:27.20#ibcon#about to read 6, iclass 5, count 0 2006.258.00:12:27.20#ibcon#read 6, iclass 5, count 0 2006.258.00:12:27.20#ibcon#end of sib2, iclass 5, count 0 2006.258.00:12:27.20#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:12:27.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:12:27.20#ibcon#[27=USB\r\n] 2006.258.00:12:27.20#ibcon#*before write, iclass 5, count 0 2006.258.00:12:27.20#ibcon#enter sib2, iclass 5, count 0 2006.258.00:12:27.20#ibcon#flushed, iclass 5, count 0 2006.258.00:12:27.20#ibcon#about to write, iclass 5, count 0 2006.258.00:12:27.20#ibcon#wrote, iclass 5, count 0 2006.258.00:12:27.20#ibcon#about to read 3, iclass 5, count 0 2006.258.00:12:27.23#ibcon#read 3, iclass 5, count 0 2006.258.00:12:27.23#ibcon#about to read 4, iclass 5, count 0 2006.258.00:12:27.23#ibcon#read 4, iclass 5, count 0 2006.258.00:12:27.23#ibcon#about to read 5, iclass 5, count 0 2006.258.00:12:27.23#ibcon#read 5, iclass 5, count 0 2006.258.00:12:27.23#ibcon#about to read 6, iclass 5, count 0 2006.258.00:12:27.23#ibcon#read 6, iclass 5, count 0 2006.258.00:12:27.23#ibcon#end of sib2, iclass 5, count 0 2006.258.00:12:27.23#ibcon#*after write, iclass 5, count 0 2006.258.00:12:27.23#ibcon#*before return 0, iclass 5, count 0 2006.258.00:12:27.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:12:27.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:12:27.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:12:27.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:12:27.23$vck44/vblo=2,634.99 2006.258.00:12:27.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.00:12:27.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.00:12:27.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:27.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:27.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:27.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:27.23#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:12:27.23#ibcon#first serial, iclass 7, count 0 2006.258.00:12:27.23#ibcon#enter sib2, iclass 7, count 0 2006.258.00:12:27.23#ibcon#flushed, iclass 7, count 0 2006.258.00:12:27.23#ibcon#about to write, iclass 7, count 0 2006.258.00:12:27.23#ibcon#wrote, iclass 7, count 0 2006.258.00:12:27.23#ibcon#about to read 3, iclass 7, count 0 2006.258.00:12:27.25#ibcon#read 3, iclass 7, count 0 2006.258.00:12:27.25#ibcon#about to read 4, iclass 7, count 0 2006.258.00:12:27.25#ibcon#read 4, iclass 7, count 0 2006.258.00:12:27.25#ibcon#about to read 5, iclass 7, count 0 2006.258.00:12:27.25#ibcon#read 5, iclass 7, count 0 2006.258.00:12:27.25#ibcon#about to read 6, iclass 7, count 0 2006.258.00:12:27.25#ibcon#read 6, iclass 7, count 0 2006.258.00:12:27.25#ibcon#end of sib2, iclass 7, count 0 2006.258.00:12:27.25#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:12:27.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:12:27.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:12:27.25#ibcon#*before write, iclass 7, count 0 2006.258.00:12:27.25#ibcon#enter sib2, iclass 7, count 0 2006.258.00:12:27.25#ibcon#flushed, iclass 7, count 0 2006.258.00:12:27.25#ibcon#about to write, iclass 7, count 0 2006.258.00:12:27.25#ibcon#wrote, iclass 7, count 0 2006.258.00:12:27.25#ibcon#about to read 3, iclass 7, count 0 2006.258.00:12:27.29#ibcon#read 3, iclass 7, count 0 2006.258.00:12:27.29#ibcon#about to read 4, iclass 7, count 0 2006.258.00:12:27.29#ibcon#read 4, iclass 7, count 0 2006.258.00:12:27.29#ibcon#about to read 5, iclass 7, count 0 2006.258.00:12:27.29#ibcon#read 5, iclass 7, count 0 2006.258.00:12:27.29#ibcon#about to read 6, iclass 7, count 0 2006.258.00:12:27.29#ibcon#read 6, iclass 7, count 0 2006.258.00:12:27.29#ibcon#end of sib2, iclass 7, count 0 2006.258.00:12:27.29#ibcon#*after write, iclass 7, count 0 2006.258.00:12:27.29#ibcon#*before return 0, iclass 7, count 0 2006.258.00:12:27.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:27.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:12:27.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:12:27.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:12:27.29$vck44/vb=2,5 2006.258.00:12:27.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.00:12:27.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.00:12:27.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:27.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:27.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:27.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:27.35#ibcon#enter wrdev, iclass 11, count 2 2006.258.00:12:27.35#ibcon#first serial, iclass 11, count 2 2006.258.00:12:27.35#ibcon#enter sib2, iclass 11, count 2 2006.258.00:12:27.35#ibcon#flushed, iclass 11, count 2 2006.258.00:12:27.35#ibcon#about to write, iclass 11, count 2 2006.258.00:12:27.35#ibcon#wrote, iclass 11, count 2 2006.258.00:12:27.35#ibcon#about to read 3, iclass 11, count 2 2006.258.00:12:27.37#ibcon#read 3, iclass 11, count 2 2006.258.00:12:27.37#ibcon#about to read 4, iclass 11, count 2 2006.258.00:12:27.37#ibcon#read 4, iclass 11, count 2 2006.258.00:12:27.37#ibcon#about to read 5, iclass 11, count 2 2006.258.00:12:27.37#ibcon#read 5, iclass 11, count 2 2006.258.00:12:27.37#ibcon#about to read 6, iclass 11, count 2 2006.258.00:12:27.37#ibcon#read 6, iclass 11, count 2 2006.258.00:12:27.37#ibcon#end of sib2, iclass 11, count 2 2006.258.00:12:27.37#ibcon#*mode == 0, iclass 11, count 2 2006.258.00:12:27.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.00:12:27.37#ibcon#[27=AT02-05\r\n] 2006.258.00:12:27.37#ibcon#*before write, iclass 11, count 2 2006.258.00:12:27.37#ibcon#enter sib2, iclass 11, count 2 2006.258.00:12:27.37#ibcon#flushed, iclass 11, count 2 2006.258.00:12:27.37#ibcon#about to write, iclass 11, count 2 2006.258.00:12:27.37#ibcon#wrote, iclass 11, count 2 2006.258.00:12:27.37#ibcon#about to read 3, iclass 11, count 2 2006.258.00:12:27.40#ibcon#read 3, iclass 11, count 2 2006.258.00:12:27.40#ibcon#about to read 4, iclass 11, count 2 2006.258.00:12:27.40#ibcon#read 4, iclass 11, count 2 2006.258.00:12:27.51#ibcon#about to read 5, iclass 11, count 2 2006.258.00:12:27.51#ibcon#read 5, iclass 11, count 2 2006.258.00:12:27.51#ibcon#about to read 6, iclass 11, count 2 2006.258.00:12:27.51#ibcon#read 6, iclass 11, count 2 2006.258.00:12:27.51#ibcon#end of sib2, iclass 11, count 2 2006.258.00:12:27.51#ibcon#*after write, iclass 11, count 2 2006.258.00:12:27.51#ibcon#*before return 0, iclass 11, count 2 2006.258.00:12:27.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:27.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:12:27.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.00:12:27.51#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:27.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:27.62#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:27.62#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:27.62#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:12:27.62#ibcon#first serial, iclass 11, count 0 2006.258.00:12:27.62#ibcon#enter sib2, iclass 11, count 0 2006.258.00:12:27.62#ibcon#flushed, iclass 11, count 0 2006.258.00:12:27.62#ibcon#about to write, iclass 11, count 0 2006.258.00:12:27.62#ibcon#wrote, iclass 11, count 0 2006.258.00:12:27.62#ibcon#about to read 3, iclass 11, count 0 2006.258.00:12:27.64#ibcon#read 3, iclass 11, count 0 2006.258.00:12:27.64#ibcon#about to read 4, iclass 11, count 0 2006.258.00:12:27.64#ibcon#read 4, iclass 11, count 0 2006.258.00:12:27.64#ibcon#about to read 5, iclass 11, count 0 2006.258.00:12:27.64#ibcon#read 5, iclass 11, count 0 2006.258.00:12:27.64#ibcon#about to read 6, iclass 11, count 0 2006.258.00:12:27.64#ibcon#read 6, iclass 11, count 0 2006.258.00:12:27.64#ibcon#end of sib2, iclass 11, count 0 2006.258.00:12:27.64#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:12:27.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:12:27.64#ibcon#[27=USB\r\n] 2006.258.00:12:27.64#ibcon#*before write, iclass 11, count 0 2006.258.00:12:27.64#ibcon#enter sib2, iclass 11, count 0 2006.258.00:12:27.64#ibcon#flushed, iclass 11, count 0 2006.258.00:12:27.64#ibcon#about to write, iclass 11, count 0 2006.258.00:12:27.64#ibcon#wrote, iclass 11, count 0 2006.258.00:12:27.64#ibcon#about to read 3, iclass 11, count 0 2006.258.00:12:27.67#ibcon#read 3, iclass 11, count 0 2006.258.00:12:27.67#ibcon#about to read 4, iclass 11, count 0 2006.258.00:12:27.67#ibcon#read 4, iclass 11, count 0 2006.258.00:12:27.67#ibcon#about to read 5, iclass 11, count 0 2006.258.00:12:27.67#ibcon#read 5, iclass 11, count 0 2006.258.00:12:27.67#ibcon#about to read 6, iclass 11, count 0 2006.258.00:12:27.67#ibcon#read 6, iclass 11, count 0 2006.258.00:12:27.67#ibcon#end of sib2, iclass 11, count 0 2006.258.00:12:27.67#ibcon#*after write, iclass 11, count 0 2006.258.00:12:27.67#ibcon#*before return 0, iclass 11, count 0 2006.258.00:12:27.67#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:27.67#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:12:27.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:12:27.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:12:27.67$vck44/vblo=3,649.99 2006.258.00:12:27.67#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.258.00:12:27.67#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.258.00:12:27.67#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:27.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:27.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:27.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:27.67#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:12:27.67#ibcon#first serial, iclass 13, count 0 2006.258.00:12:27.67#ibcon#enter sib2, iclass 13, count 0 2006.258.00:12:27.67#ibcon#flushed, iclass 13, count 0 2006.258.00:12:27.67#ibcon#about to write, iclass 13, count 0 2006.258.00:12:27.67#ibcon#wrote, iclass 13, count 0 2006.258.00:12:27.67#ibcon#about to read 3, iclass 13, count 0 2006.258.00:12:27.69#ibcon#read 3, iclass 13, count 0 2006.258.00:12:27.69#ibcon#about to read 4, iclass 13, count 0 2006.258.00:12:27.69#ibcon#read 4, iclass 13, count 0 2006.258.00:12:27.69#ibcon#about to read 5, iclass 13, count 0 2006.258.00:12:27.69#ibcon#read 5, iclass 13, count 0 2006.258.00:12:27.69#ibcon#about to read 6, iclass 13, count 0 2006.258.00:12:27.69#ibcon#read 6, iclass 13, count 0 2006.258.00:12:27.69#ibcon#end of sib2, iclass 13, count 0 2006.258.00:12:27.69#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:12:27.69#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:12:27.69#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:12:27.69#ibcon#*before write, iclass 13, count 0 2006.258.00:12:27.69#ibcon#enter sib2, iclass 13, count 0 2006.258.00:12:27.69#ibcon#flushed, iclass 13, count 0 2006.258.00:12:27.69#ibcon#about to write, iclass 13, count 0 2006.258.00:12:27.69#ibcon#wrote, iclass 13, count 0 2006.258.00:12:27.69#ibcon#about to read 3, iclass 13, count 0 2006.258.00:12:27.73#ibcon#read 3, iclass 13, count 0 2006.258.00:12:27.73#ibcon#about to read 4, iclass 13, count 0 2006.258.00:12:27.73#ibcon#read 4, iclass 13, count 0 2006.258.00:12:27.73#ibcon#about to read 5, iclass 13, count 0 2006.258.00:12:27.73#ibcon#read 5, iclass 13, count 0 2006.258.00:12:27.73#ibcon#about to read 6, iclass 13, count 0 2006.258.00:12:27.73#ibcon#read 6, iclass 13, count 0 2006.258.00:12:27.73#ibcon#end of sib2, iclass 13, count 0 2006.258.00:12:27.73#ibcon#*after write, iclass 13, count 0 2006.258.00:12:27.73#ibcon#*before return 0, iclass 13, count 0 2006.258.00:12:27.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:27.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:12:27.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:12:27.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:12:27.73$vck44/vb=3,4 2006.258.00:12:27.73#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.258.00:12:27.73#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.258.00:12:27.73#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:27.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:27.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:27.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:27.79#ibcon#enter wrdev, iclass 15, count 2 2006.258.00:12:27.79#ibcon#first serial, iclass 15, count 2 2006.258.00:12:27.79#ibcon#enter sib2, iclass 15, count 2 2006.258.00:12:27.79#ibcon#flushed, iclass 15, count 2 2006.258.00:12:27.79#ibcon#about to write, iclass 15, count 2 2006.258.00:12:27.79#ibcon#wrote, iclass 15, count 2 2006.258.00:12:27.79#ibcon#about to read 3, iclass 15, count 2 2006.258.00:12:27.81#ibcon#read 3, iclass 15, count 2 2006.258.00:12:27.81#ibcon#about to read 4, iclass 15, count 2 2006.258.00:12:27.81#ibcon#read 4, iclass 15, count 2 2006.258.00:12:27.81#ibcon#about to read 5, iclass 15, count 2 2006.258.00:12:27.81#ibcon#read 5, iclass 15, count 2 2006.258.00:12:27.81#ibcon#about to read 6, iclass 15, count 2 2006.258.00:12:27.81#ibcon#read 6, iclass 15, count 2 2006.258.00:12:27.81#ibcon#end of sib2, iclass 15, count 2 2006.258.00:12:27.81#ibcon#*mode == 0, iclass 15, count 2 2006.258.00:12:27.81#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.258.00:12:27.81#ibcon#[27=AT03-04\r\n] 2006.258.00:12:27.81#ibcon#*before write, iclass 15, count 2 2006.258.00:12:27.81#ibcon#enter sib2, iclass 15, count 2 2006.258.00:12:27.81#ibcon#flushed, iclass 15, count 2 2006.258.00:12:27.81#ibcon#about to write, iclass 15, count 2 2006.258.00:12:27.81#ibcon#wrote, iclass 15, count 2 2006.258.00:12:27.81#ibcon#about to read 3, iclass 15, count 2 2006.258.00:12:27.84#ibcon#read 3, iclass 15, count 2 2006.258.00:12:27.84#ibcon#about to read 4, iclass 15, count 2 2006.258.00:12:27.84#ibcon#read 4, iclass 15, count 2 2006.258.00:12:27.84#ibcon#about to read 5, iclass 15, count 2 2006.258.00:12:27.84#ibcon#read 5, iclass 15, count 2 2006.258.00:12:27.84#ibcon#about to read 6, iclass 15, count 2 2006.258.00:12:27.84#ibcon#read 6, iclass 15, count 2 2006.258.00:12:27.84#ibcon#end of sib2, iclass 15, count 2 2006.258.00:12:27.84#ibcon#*after write, iclass 15, count 2 2006.258.00:12:27.84#ibcon#*before return 0, iclass 15, count 2 2006.258.00:12:27.84#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:27.84#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:12:27.84#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.258.00:12:27.84#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:27.84#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:27.96#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:27.96#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:27.96#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:12:27.96#ibcon#first serial, iclass 15, count 0 2006.258.00:12:27.96#ibcon#enter sib2, iclass 15, count 0 2006.258.00:12:27.96#ibcon#flushed, iclass 15, count 0 2006.258.00:12:27.96#ibcon#about to write, iclass 15, count 0 2006.258.00:12:27.96#ibcon#wrote, iclass 15, count 0 2006.258.00:12:27.96#ibcon#about to read 3, iclass 15, count 0 2006.258.00:12:27.98#ibcon#read 3, iclass 15, count 0 2006.258.00:12:27.98#ibcon#about to read 4, iclass 15, count 0 2006.258.00:12:27.98#ibcon#read 4, iclass 15, count 0 2006.258.00:12:27.98#ibcon#about to read 5, iclass 15, count 0 2006.258.00:12:27.98#ibcon#read 5, iclass 15, count 0 2006.258.00:12:27.98#ibcon#about to read 6, iclass 15, count 0 2006.258.00:12:27.98#ibcon#read 6, iclass 15, count 0 2006.258.00:12:27.98#ibcon#end of sib2, iclass 15, count 0 2006.258.00:12:27.98#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:12:27.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:12:27.98#ibcon#[27=USB\r\n] 2006.258.00:12:27.98#ibcon#*before write, iclass 15, count 0 2006.258.00:12:27.98#ibcon#enter sib2, iclass 15, count 0 2006.258.00:12:27.98#ibcon#flushed, iclass 15, count 0 2006.258.00:12:27.98#ibcon#about to write, iclass 15, count 0 2006.258.00:12:27.98#ibcon#wrote, iclass 15, count 0 2006.258.00:12:27.98#ibcon#about to read 3, iclass 15, count 0 2006.258.00:12:28.01#ibcon#read 3, iclass 15, count 0 2006.258.00:12:28.01#ibcon#about to read 4, iclass 15, count 0 2006.258.00:12:28.01#ibcon#read 4, iclass 15, count 0 2006.258.00:12:28.01#ibcon#about to read 5, iclass 15, count 0 2006.258.00:12:28.01#ibcon#read 5, iclass 15, count 0 2006.258.00:12:28.01#ibcon#about to read 6, iclass 15, count 0 2006.258.00:12:28.01#ibcon#read 6, iclass 15, count 0 2006.258.00:12:28.01#ibcon#end of sib2, iclass 15, count 0 2006.258.00:12:28.01#ibcon#*after write, iclass 15, count 0 2006.258.00:12:28.01#ibcon#*before return 0, iclass 15, count 0 2006.258.00:12:28.01#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:28.01#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:12:28.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:12:28.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:12:28.01$vck44/vblo=4,679.99 2006.258.00:12:28.01#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.258.00:12:28.01#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.258.00:12:28.01#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:28.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:28.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:28.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:28.01#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:12:28.01#ibcon#first serial, iclass 17, count 0 2006.258.00:12:28.01#ibcon#enter sib2, iclass 17, count 0 2006.258.00:12:28.01#ibcon#flushed, iclass 17, count 0 2006.258.00:12:28.01#ibcon#about to write, iclass 17, count 0 2006.258.00:12:28.01#ibcon#wrote, iclass 17, count 0 2006.258.00:12:28.01#ibcon#about to read 3, iclass 17, count 0 2006.258.00:12:28.03#ibcon#read 3, iclass 17, count 0 2006.258.00:12:28.03#ibcon#about to read 4, iclass 17, count 0 2006.258.00:12:28.03#ibcon#read 4, iclass 17, count 0 2006.258.00:12:28.03#ibcon#about to read 5, iclass 17, count 0 2006.258.00:12:28.03#ibcon#read 5, iclass 17, count 0 2006.258.00:12:28.03#ibcon#about to read 6, iclass 17, count 0 2006.258.00:12:28.03#ibcon#read 6, iclass 17, count 0 2006.258.00:12:28.03#ibcon#end of sib2, iclass 17, count 0 2006.258.00:12:28.03#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:12:28.03#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:12:28.03#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:12:28.03#ibcon#*before write, iclass 17, count 0 2006.258.00:12:28.03#ibcon#enter sib2, iclass 17, count 0 2006.258.00:12:28.03#ibcon#flushed, iclass 17, count 0 2006.258.00:12:28.03#ibcon#about to write, iclass 17, count 0 2006.258.00:12:28.03#ibcon#wrote, iclass 17, count 0 2006.258.00:12:28.03#ibcon#about to read 3, iclass 17, count 0 2006.258.00:12:28.07#ibcon#read 3, iclass 17, count 0 2006.258.00:12:28.07#ibcon#about to read 4, iclass 17, count 0 2006.258.00:12:28.07#ibcon#read 4, iclass 17, count 0 2006.258.00:12:28.07#ibcon#about to read 5, iclass 17, count 0 2006.258.00:12:28.07#ibcon#read 5, iclass 17, count 0 2006.258.00:12:28.07#ibcon#about to read 6, iclass 17, count 0 2006.258.00:12:28.07#ibcon#read 6, iclass 17, count 0 2006.258.00:12:28.07#ibcon#end of sib2, iclass 17, count 0 2006.258.00:12:28.07#ibcon#*after write, iclass 17, count 0 2006.258.00:12:28.07#ibcon#*before return 0, iclass 17, count 0 2006.258.00:12:28.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:28.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:12:28.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:12:28.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:12:28.07$vck44/vb=4,5 2006.258.00:12:28.07#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.258.00:12:28.07#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.258.00:12:28.07#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:28.07#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:28.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:28.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:28.13#ibcon#enter wrdev, iclass 19, count 2 2006.258.00:12:28.13#ibcon#first serial, iclass 19, count 2 2006.258.00:12:28.13#ibcon#enter sib2, iclass 19, count 2 2006.258.00:12:28.13#ibcon#flushed, iclass 19, count 2 2006.258.00:12:28.13#ibcon#about to write, iclass 19, count 2 2006.258.00:12:28.13#ibcon#wrote, iclass 19, count 2 2006.258.00:12:28.13#ibcon#about to read 3, iclass 19, count 2 2006.258.00:12:28.15#ibcon#read 3, iclass 19, count 2 2006.258.00:12:28.15#ibcon#about to read 4, iclass 19, count 2 2006.258.00:12:28.15#ibcon#read 4, iclass 19, count 2 2006.258.00:12:28.15#ibcon#about to read 5, iclass 19, count 2 2006.258.00:12:28.15#ibcon#read 5, iclass 19, count 2 2006.258.00:12:28.15#ibcon#about to read 6, iclass 19, count 2 2006.258.00:12:28.15#ibcon#read 6, iclass 19, count 2 2006.258.00:12:28.15#ibcon#end of sib2, iclass 19, count 2 2006.258.00:12:28.15#ibcon#*mode == 0, iclass 19, count 2 2006.258.00:12:28.15#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.258.00:12:28.15#ibcon#[27=AT04-05\r\n] 2006.258.00:12:28.15#ibcon#*before write, iclass 19, count 2 2006.258.00:12:28.15#ibcon#enter sib2, iclass 19, count 2 2006.258.00:12:28.15#ibcon#flushed, iclass 19, count 2 2006.258.00:12:28.15#ibcon#about to write, iclass 19, count 2 2006.258.00:12:28.15#ibcon#wrote, iclass 19, count 2 2006.258.00:12:28.15#ibcon#about to read 3, iclass 19, count 2 2006.258.00:12:28.18#ibcon#read 3, iclass 19, count 2 2006.258.00:12:28.18#ibcon#about to read 4, iclass 19, count 2 2006.258.00:12:28.18#ibcon#read 4, iclass 19, count 2 2006.258.00:12:28.18#ibcon#about to read 5, iclass 19, count 2 2006.258.00:12:28.18#ibcon#read 5, iclass 19, count 2 2006.258.00:12:28.18#ibcon#about to read 6, iclass 19, count 2 2006.258.00:12:28.18#ibcon#read 6, iclass 19, count 2 2006.258.00:12:28.18#ibcon#end of sib2, iclass 19, count 2 2006.258.00:12:28.18#ibcon#*after write, iclass 19, count 2 2006.258.00:12:28.18#ibcon#*before return 0, iclass 19, count 2 2006.258.00:12:28.18#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:28.18#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:12:28.18#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.258.00:12:28.18#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:28.18#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:28.30#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:28.30#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:28.30#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:12:28.30#ibcon#first serial, iclass 19, count 0 2006.258.00:12:28.30#ibcon#enter sib2, iclass 19, count 0 2006.258.00:12:28.30#ibcon#flushed, iclass 19, count 0 2006.258.00:12:28.30#ibcon#about to write, iclass 19, count 0 2006.258.00:12:28.30#ibcon#wrote, iclass 19, count 0 2006.258.00:12:28.30#ibcon#about to read 3, iclass 19, count 0 2006.258.00:12:28.32#ibcon#read 3, iclass 19, count 0 2006.258.00:12:28.32#ibcon#about to read 4, iclass 19, count 0 2006.258.00:12:28.32#ibcon#read 4, iclass 19, count 0 2006.258.00:12:28.32#ibcon#about to read 5, iclass 19, count 0 2006.258.00:12:28.32#ibcon#read 5, iclass 19, count 0 2006.258.00:12:28.32#ibcon#about to read 6, iclass 19, count 0 2006.258.00:12:28.32#ibcon#read 6, iclass 19, count 0 2006.258.00:12:28.32#ibcon#end of sib2, iclass 19, count 0 2006.258.00:12:28.32#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:12:28.32#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:12:28.32#ibcon#[27=USB\r\n] 2006.258.00:12:28.32#ibcon#*before write, iclass 19, count 0 2006.258.00:12:28.32#ibcon#enter sib2, iclass 19, count 0 2006.258.00:12:28.32#ibcon#flushed, iclass 19, count 0 2006.258.00:12:28.32#ibcon#about to write, iclass 19, count 0 2006.258.00:12:28.32#ibcon#wrote, iclass 19, count 0 2006.258.00:12:28.32#ibcon#about to read 3, iclass 19, count 0 2006.258.00:12:28.35#ibcon#read 3, iclass 19, count 0 2006.258.00:12:28.35#ibcon#about to read 4, iclass 19, count 0 2006.258.00:12:28.35#ibcon#read 4, iclass 19, count 0 2006.258.00:12:28.35#ibcon#about to read 5, iclass 19, count 0 2006.258.00:12:28.35#ibcon#read 5, iclass 19, count 0 2006.258.00:12:28.35#ibcon#about to read 6, iclass 19, count 0 2006.258.00:12:28.35#ibcon#read 6, iclass 19, count 0 2006.258.00:12:28.35#ibcon#end of sib2, iclass 19, count 0 2006.258.00:12:28.35#ibcon#*after write, iclass 19, count 0 2006.258.00:12:28.35#ibcon#*before return 0, iclass 19, count 0 2006.258.00:12:28.35#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:28.35#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:12:28.35#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:12:28.35#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:12:28.35$vck44/vblo=5,709.99 2006.258.00:12:28.35#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.258.00:12:28.35#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.258.00:12:28.35#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:28.35#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:28.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:28.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:28.35#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:12:28.35#ibcon#first serial, iclass 21, count 0 2006.258.00:12:28.35#ibcon#enter sib2, iclass 21, count 0 2006.258.00:12:28.35#ibcon#flushed, iclass 21, count 0 2006.258.00:12:28.35#ibcon#about to write, iclass 21, count 0 2006.258.00:12:28.35#ibcon#wrote, iclass 21, count 0 2006.258.00:12:28.35#ibcon#about to read 3, iclass 21, count 0 2006.258.00:12:28.37#ibcon#read 3, iclass 21, count 0 2006.258.00:12:28.37#ibcon#about to read 4, iclass 21, count 0 2006.258.00:12:28.37#ibcon#read 4, iclass 21, count 0 2006.258.00:12:28.37#ibcon#about to read 5, iclass 21, count 0 2006.258.00:12:28.37#ibcon#read 5, iclass 21, count 0 2006.258.00:12:28.37#ibcon#about to read 6, iclass 21, count 0 2006.258.00:12:28.37#ibcon#read 6, iclass 21, count 0 2006.258.00:12:28.37#ibcon#end of sib2, iclass 21, count 0 2006.258.00:12:28.37#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:12:28.37#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:12:28.37#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:12:28.37#ibcon#*before write, iclass 21, count 0 2006.258.00:12:28.37#ibcon#enter sib2, iclass 21, count 0 2006.258.00:12:28.37#ibcon#flushed, iclass 21, count 0 2006.258.00:12:28.37#ibcon#about to write, iclass 21, count 0 2006.258.00:12:28.37#ibcon#wrote, iclass 21, count 0 2006.258.00:12:28.37#ibcon#about to read 3, iclass 21, count 0 2006.258.00:12:28.41#ibcon#read 3, iclass 21, count 0 2006.258.00:12:28.41#ibcon#about to read 4, iclass 21, count 0 2006.258.00:12:28.41#ibcon#read 4, iclass 21, count 0 2006.258.00:12:28.41#ibcon#about to read 5, iclass 21, count 0 2006.258.00:12:28.41#ibcon#read 5, iclass 21, count 0 2006.258.00:12:28.41#ibcon#about to read 6, iclass 21, count 0 2006.258.00:12:28.41#ibcon#read 6, iclass 21, count 0 2006.258.00:12:28.41#ibcon#end of sib2, iclass 21, count 0 2006.258.00:12:28.41#ibcon#*after write, iclass 21, count 0 2006.258.00:12:28.41#ibcon#*before return 0, iclass 21, count 0 2006.258.00:12:28.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:28.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:12:28.41#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:12:28.41#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:12:28.41$vck44/vb=5,4 2006.258.00:12:28.41#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.258.00:12:28.41#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.258.00:12:28.41#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:28.41#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:28.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:28.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:28.47#ibcon#enter wrdev, iclass 23, count 2 2006.258.00:12:28.47#ibcon#first serial, iclass 23, count 2 2006.258.00:12:28.47#ibcon#enter sib2, iclass 23, count 2 2006.258.00:12:28.47#ibcon#flushed, iclass 23, count 2 2006.258.00:12:28.47#ibcon#about to write, iclass 23, count 2 2006.258.00:12:28.47#ibcon#wrote, iclass 23, count 2 2006.258.00:12:28.47#ibcon#about to read 3, iclass 23, count 2 2006.258.00:12:28.49#ibcon#read 3, iclass 23, count 2 2006.258.00:12:28.49#ibcon#about to read 4, iclass 23, count 2 2006.258.00:12:28.49#ibcon#read 4, iclass 23, count 2 2006.258.00:12:28.49#ibcon#about to read 5, iclass 23, count 2 2006.258.00:12:28.49#ibcon#read 5, iclass 23, count 2 2006.258.00:12:28.49#ibcon#about to read 6, iclass 23, count 2 2006.258.00:12:28.49#ibcon#read 6, iclass 23, count 2 2006.258.00:12:28.49#ibcon#end of sib2, iclass 23, count 2 2006.258.00:12:28.49#ibcon#*mode == 0, iclass 23, count 2 2006.258.00:12:28.49#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.258.00:12:28.49#ibcon#[27=AT05-04\r\n] 2006.258.00:12:28.49#ibcon#*before write, iclass 23, count 2 2006.258.00:12:28.49#ibcon#enter sib2, iclass 23, count 2 2006.258.00:12:28.49#ibcon#flushed, iclass 23, count 2 2006.258.00:12:28.49#ibcon#about to write, iclass 23, count 2 2006.258.00:12:28.49#ibcon#wrote, iclass 23, count 2 2006.258.00:12:28.49#ibcon#about to read 3, iclass 23, count 2 2006.258.00:12:28.52#ibcon#read 3, iclass 23, count 2 2006.258.00:12:28.52#ibcon#about to read 4, iclass 23, count 2 2006.258.00:12:28.52#ibcon#read 4, iclass 23, count 2 2006.258.00:12:28.52#ibcon#about to read 5, iclass 23, count 2 2006.258.00:12:28.52#ibcon#read 5, iclass 23, count 2 2006.258.00:12:28.52#ibcon#about to read 6, iclass 23, count 2 2006.258.00:12:28.52#ibcon#read 6, iclass 23, count 2 2006.258.00:12:28.52#ibcon#end of sib2, iclass 23, count 2 2006.258.00:12:28.52#ibcon#*after write, iclass 23, count 2 2006.258.00:12:28.55#ibcon#*before return 0, iclass 23, count 2 2006.258.00:12:28.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:28.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:12:28.55#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.258.00:12:28.55#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:28.55#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:28.66#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:28.66#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:28.66#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:12:28.66#ibcon#first serial, iclass 23, count 0 2006.258.00:12:28.66#ibcon#enter sib2, iclass 23, count 0 2006.258.00:12:28.66#ibcon#flushed, iclass 23, count 0 2006.258.00:12:28.66#ibcon#about to write, iclass 23, count 0 2006.258.00:12:28.66#ibcon#wrote, iclass 23, count 0 2006.258.00:12:28.66#ibcon#about to read 3, iclass 23, count 0 2006.258.00:12:28.68#ibcon#read 3, iclass 23, count 0 2006.258.00:12:28.68#ibcon#about to read 4, iclass 23, count 0 2006.258.00:12:28.68#ibcon#read 4, iclass 23, count 0 2006.258.00:12:28.68#ibcon#about to read 5, iclass 23, count 0 2006.258.00:12:28.68#ibcon#read 5, iclass 23, count 0 2006.258.00:12:28.68#ibcon#about to read 6, iclass 23, count 0 2006.258.00:12:28.68#ibcon#read 6, iclass 23, count 0 2006.258.00:12:28.68#ibcon#end of sib2, iclass 23, count 0 2006.258.00:12:28.68#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:12:28.68#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:12:28.68#ibcon#[27=USB\r\n] 2006.258.00:12:28.68#ibcon#*before write, iclass 23, count 0 2006.258.00:12:28.68#ibcon#enter sib2, iclass 23, count 0 2006.258.00:12:28.68#ibcon#flushed, iclass 23, count 0 2006.258.00:12:28.68#ibcon#about to write, iclass 23, count 0 2006.258.00:12:28.68#ibcon#wrote, iclass 23, count 0 2006.258.00:12:28.68#ibcon#about to read 3, iclass 23, count 0 2006.258.00:12:28.71#ibcon#read 3, iclass 23, count 0 2006.258.00:12:28.71#ibcon#about to read 4, iclass 23, count 0 2006.258.00:12:28.71#ibcon#read 4, iclass 23, count 0 2006.258.00:12:28.71#ibcon#about to read 5, iclass 23, count 0 2006.258.00:12:28.71#ibcon#read 5, iclass 23, count 0 2006.258.00:12:28.71#ibcon#about to read 6, iclass 23, count 0 2006.258.00:12:28.71#ibcon#read 6, iclass 23, count 0 2006.258.00:12:28.71#ibcon#end of sib2, iclass 23, count 0 2006.258.00:12:28.71#ibcon#*after write, iclass 23, count 0 2006.258.00:12:28.71#ibcon#*before return 0, iclass 23, count 0 2006.258.00:12:28.71#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:28.71#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:12:28.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:12:28.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:12:28.71$vck44/vblo=6,719.99 2006.258.00:12:28.71#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.00:12:28.71#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.00:12:28.71#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:28.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:28.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:28.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:28.71#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:12:28.71#ibcon#first serial, iclass 25, count 0 2006.258.00:12:28.71#ibcon#enter sib2, iclass 25, count 0 2006.258.00:12:28.71#ibcon#flushed, iclass 25, count 0 2006.258.00:12:28.71#ibcon#about to write, iclass 25, count 0 2006.258.00:12:28.71#ibcon#wrote, iclass 25, count 0 2006.258.00:12:28.71#ibcon#about to read 3, iclass 25, count 0 2006.258.00:12:28.73#ibcon#read 3, iclass 25, count 0 2006.258.00:12:28.73#ibcon#about to read 4, iclass 25, count 0 2006.258.00:12:28.73#ibcon#read 4, iclass 25, count 0 2006.258.00:12:28.73#ibcon#about to read 5, iclass 25, count 0 2006.258.00:12:28.73#ibcon#read 5, iclass 25, count 0 2006.258.00:12:28.73#ibcon#about to read 6, iclass 25, count 0 2006.258.00:12:28.73#ibcon#read 6, iclass 25, count 0 2006.258.00:12:28.73#ibcon#end of sib2, iclass 25, count 0 2006.258.00:12:28.73#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:12:28.73#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:12:28.73#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:12:28.73#ibcon#*before write, iclass 25, count 0 2006.258.00:12:28.73#ibcon#enter sib2, iclass 25, count 0 2006.258.00:12:28.73#ibcon#flushed, iclass 25, count 0 2006.258.00:12:28.73#ibcon#about to write, iclass 25, count 0 2006.258.00:12:28.73#ibcon#wrote, iclass 25, count 0 2006.258.00:12:28.73#ibcon#about to read 3, iclass 25, count 0 2006.258.00:12:28.77#ibcon#read 3, iclass 25, count 0 2006.258.00:12:28.77#ibcon#about to read 4, iclass 25, count 0 2006.258.00:12:28.77#ibcon#read 4, iclass 25, count 0 2006.258.00:12:28.77#ibcon#about to read 5, iclass 25, count 0 2006.258.00:12:28.77#ibcon#read 5, iclass 25, count 0 2006.258.00:12:28.77#ibcon#about to read 6, iclass 25, count 0 2006.258.00:12:28.77#ibcon#read 6, iclass 25, count 0 2006.258.00:12:28.77#ibcon#end of sib2, iclass 25, count 0 2006.258.00:12:28.77#ibcon#*after write, iclass 25, count 0 2006.258.00:12:28.77#ibcon#*before return 0, iclass 25, count 0 2006.258.00:12:28.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:28.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:12:28.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:12:28.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:12:28.77$vck44/vb=6,4 2006.258.00:12:28.77#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.258.00:12:28.77#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.258.00:12:28.77#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:28.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:28.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:28.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:28.83#ibcon#enter wrdev, iclass 27, count 2 2006.258.00:12:28.83#ibcon#first serial, iclass 27, count 2 2006.258.00:12:28.83#ibcon#enter sib2, iclass 27, count 2 2006.258.00:12:28.83#ibcon#flushed, iclass 27, count 2 2006.258.00:12:28.83#ibcon#about to write, iclass 27, count 2 2006.258.00:12:28.83#ibcon#wrote, iclass 27, count 2 2006.258.00:12:28.83#ibcon#about to read 3, iclass 27, count 2 2006.258.00:12:28.85#ibcon#read 3, iclass 27, count 2 2006.258.00:12:28.85#ibcon#about to read 4, iclass 27, count 2 2006.258.00:12:28.85#ibcon#read 4, iclass 27, count 2 2006.258.00:12:28.85#ibcon#about to read 5, iclass 27, count 2 2006.258.00:12:28.85#ibcon#read 5, iclass 27, count 2 2006.258.00:12:28.85#ibcon#about to read 6, iclass 27, count 2 2006.258.00:12:28.85#ibcon#read 6, iclass 27, count 2 2006.258.00:12:28.85#ibcon#end of sib2, iclass 27, count 2 2006.258.00:12:28.85#ibcon#*mode == 0, iclass 27, count 2 2006.258.00:12:28.85#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.258.00:12:28.85#ibcon#[27=AT06-04\r\n] 2006.258.00:12:28.85#ibcon#*before write, iclass 27, count 2 2006.258.00:12:28.85#ibcon#enter sib2, iclass 27, count 2 2006.258.00:12:28.85#ibcon#flushed, iclass 27, count 2 2006.258.00:12:28.85#ibcon#about to write, iclass 27, count 2 2006.258.00:12:28.85#ibcon#wrote, iclass 27, count 2 2006.258.00:12:28.85#ibcon#about to read 3, iclass 27, count 2 2006.258.00:12:28.88#ibcon#read 3, iclass 27, count 2 2006.258.00:12:28.88#ibcon#about to read 4, iclass 27, count 2 2006.258.00:12:28.88#ibcon#read 4, iclass 27, count 2 2006.258.00:12:28.88#ibcon#about to read 5, iclass 27, count 2 2006.258.00:12:28.88#ibcon#read 5, iclass 27, count 2 2006.258.00:12:28.88#ibcon#about to read 6, iclass 27, count 2 2006.258.00:12:28.88#ibcon#read 6, iclass 27, count 2 2006.258.00:12:28.88#ibcon#end of sib2, iclass 27, count 2 2006.258.00:12:28.88#ibcon#*after write, iclass 27, count 2 2006.258.00:12:28.88#ibcon#*before return 0, iclass 27, count 2 2006.258.00:12:28.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:28.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:12:28.88#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.258.00:12:28.88#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:28.88#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:29.00#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:29.00#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:29.00#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:12:29.00#ibcon#first serial, iclass 27, count 0 2006.258.00:12:29.00#ibcon#enter sib2, iclass 27, count 0 2006.258.00:12:29.00#ibcon#flushed, iclass 27, count 0 2006.258.00:12:29.00#ibcon#about to write, iclass 27, count 0 2006.258.00:12:29.00#ibcon#wrote, iclass 27, count 0 2006.258.00:12:29.00#ibcon#about to read 3, iclass 27, count 0 2006.258.00:12:29.02#ibcon#read 3, iclass 27, count 0 2006.258.00:12:29.02#ibcon#about to read 4, iclass 27, count 0 2006.258.00:12:29.02#ibcon#read 4, iclass 27, count 0 2006.258.00:12:29.02#ibcon#about to read 5, iclass 27, count 0 2006.258.00:12:29.02#ibcon#read 5, iclass 27, count 0 2006.258.00:12:29.02#ibcon#about to read 6, iclass 27, count 0 2006.258.00:12:29.02#ibcon#read 6, iclass 27, count 0 2006.258.00:12:29.02#ibcon#end of sib2, iclass 27, count 0 2006.258.00:12:29.02#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:12:29.02#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:12:29.02#ibcon#[27=USB\r\n] 2006.258.00:12:29.02#ibcon#*before write, iclass 27, count 0 2006.258.00:12:29.02#ibcon#enter sib2, iclass 27, count 0 2006.258.00:12:29.02#ibcon#flushed, iclass 27, count 0 2006.258.00:12:29.02#ibcon#about to write, iclass 27, count 0 2006.258.00:12:29.02#ibcon#wrote, iclass 27, count 0 2006.258.00:12:29.02#ibcon#about to read 3, iclass 27, count 0 2006.258.00:12:29.05#ibcon#read 3, iclass 27, count 0 2006.258.00:12:29.05#ibcon#about to read 4, iclass 27, count 0 2006.258.00:12:29.05#ibcon#read 4, iclass 27, count 0 2006.258.00:12:29.05#ibcon#about to read 5, iclass 27, count 0 2006.258.00:12:29.05#ibcon#read 5, iclass 27, count 0 2006.258.00:12:29.05#ibcon#about to read 6, iclass 27, count 0 2006.258.00:12:29.05#ibcon#read 6, iclass 27, count 0 2006.258.00:12:29.05#ibcon#end of sib2, iclass 27, count 0 2006.258.00:12:29.05#ibcon#*after write, iclass 27, count 0 2006.258.00:12:29.05#ibcon#*before return 0, iclass 27, count 0 2006.258.00:12:29.05#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:29.05#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:12:29.05#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:12:29.05#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:12:29.05$vck44/vblo=7,734.99 2006.258.00:12:29.05#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.00:12:29.05#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.00:12:29.05#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:29.05#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:29.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:29.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:29.05#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:12:29.05#ibcon#first serial, iclass 29, count 0 2006.258.00:12:29.05#ibcon#enter sib2, iclass 29, count 0 2006.258.00:12:29.05#ibcon#flushed, iclass 29, count 0 2006.258.00:12:29.05#ibcon#about to write, iclass 29, count 0 2006.258.00:12:29.05#ibcon#wrote, iclass 29, count 0 2006.258.00:12:29.05#ibcon#about to read 3, iclass 29, count 0 2006.258.00:12:29.07#ibcon#read 3, iclass 29, count 0 2006.258.00:12:29.07#ibcon#about to read 4, iclass 29, count 0 2006.258.00:12:29.07#ibcon#read 4, iclass 29, count 0 2006.258.00:12:29.07#ibcon#about to read 5, iclass 29, count 0 2006.258.00:12:29.07#ibcon#read 5, iclass 29, count 0 2006.258.00:12:29.07#ibcon#about to read 6, iclass 29, count 0 2006.258.00:12:29.07#ibcon#read 6, iclass 29, count 0 2006.258.00:12:29.07#ibcon#end of sib2, iclass 29, count 0 2006.258.00:12:29.07#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:12:29.07#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:12:29.07#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:12:29.07#ibcon#*before write, iclass 29, count 0 2006.258.00:12:29.07#ibcon#enter sib2, iclass 29, count 0 2006.258.00:12:29.07#ibcon#flushed, iclass 29, count 0 2006.258.00:12:29.07#ibcon#about to write, iclass 29, count 0 2006.258.00:12:29.07#ibcon#wrote, iclass 29, count 0 2006.258.00:12:29.07#ibcon#about to read 3, iclass 29, count 0 2006.258.00:12:29.11#ibcon#read 3, iclass 29, count 0 2006.258.00:12:29.11#ibcon#about to read 4, iclass 29, count 0 2006.258.00:12:29.11#ibcon#read 4, iclass 29, count 0 2006.258.00:12:29.11#ibcon#about to read 5, iclass 29, count 0 2006.258.00:12:29.11#ibcon#read 5, iclass 29, count 0 2006.258.00:12:29.11#ibcon#about to read 6, iclass 29, count 0 2006.258.00:12:29.11#ibcon#read 6, iclass 29, count 0 2006.258.00:12:29.11#ibcon#end of sib2, iclass 29, count 0 2006.258.00:12:29.11#ibcon#*after write, iclass 29, count 0 2006.258.00:12:29.11#ibcon#*before return 0, iclass 29, count 0 2006.258.00:12:29.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:29.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:12:29.11#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:12:29.11#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:12:29.11$vck44/vb=7,4 2006.258.00:12:29.11#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.00:12:29.11#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.00:12:29.11#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:29.11#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:29.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:29.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:29.17#ibcon#enter wrdev, iclass 31, count 2 2006.258.00:12:29.17#ibcon#first serial, iclass 31, count 2 2006.258.00:12:29.17#ibcon#enter sib2, iclass 31, count 2 2006.258.00:12:29.17#ibcon#flushed, iclass 31, count 2 2006.258.00:12:29.17#ibcon#about to write, iclass 31, count 2 2006.258.00:12:29.17#ibcon#wrote, iclass 31, count 2 2006.258.00:12:29.17#ibcon#about to read 3, iclass 31, count 2 2006.258.00:12:29.19#ibcon#read 3, iclass 31, count 2 2006.258.00:12:29.19#ibcon#about to read 4, iclass 31, count 2 2006.258.00:12:29.19#ibcon#read 4, iclass 31, count 2 2006.258.00:12:29.19#ibcon#about to read 5, iclass 31, count 2 2006.258.00:12:29.19#ibcon#read 5, iclass 31, count 2 2006.258.00:12:29.19#ibcon#about to read 6, iclass 31, count 2 2006.258.00:12:29.19#ibcon#read 6, iclass 31, count 2 2006.258.00:12:29.19#ibcon#end of sib2, iclass 31, count 2 2006.258.00:12:29.19#ibcon#*mode == 0, iclass 31, count 2 2006.258.00:12:29.19#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.00:12:29.19#ibcon#[27=AT07-04\r\n] 2006.258.00:12:29.19#ibcon#*before write, iclass 31, count 2 2006.258.00:12:29.19#ibcon#enter sib2, iclass 31, count 2 2006.258.00:12:29.19#ibcon#flushed, iclass 31, count 2 2006.258.00:12:29.19#ibcon#about to write, iclass 31, count 2 2006.258.00:12:29.19#ibcon#wrote, iclass 31, count 2 2006.258.00:12:29.19#ibcon#about to read 3, iclass 31, count 2 2006.258.00:12:29.22#ibcon#read 3, iclass 31, count 2 2006.258.00:12:29.22#ibcon#about to read 4, iclass 31, count 2 2006.258.00:12:29.22#ibcon#read 4, iclass 31, count 2 2006.258.00:12:29.22#ibcon#about to read 5, iclass 31, count 2 2006.258.00:12:29.22#ibcon#read 5, iclass 31, count 2 2006.258.00:12:29.22#ibcon#about to read 6, iclass 31, count 2 2006.258.00:12:29.22#ibcon#read 6, iclass 31, count 2 2006.258.00:12:29.22#ibcon#end of sib2, iclass 31, count 2 2006.258.00:12:29.22#ibcon#*after write, iclass 31, count 2 2006.258.00:12:29.22#ibcon#*before return 0, iclass 31, count 2 2006.258.00:12:29.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:29.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:12:29.22#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.00:12:29.22#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:29.22#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:29.34#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:29.34#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:29.34#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:12:29.34#ibcon#first serial, iclass 31, count 0 2006.258.00:12:29.34#ibcon#enter sib2, iclass 31, count 0 2006.258.00:12:29.34#ibcon#flushed, iclass 31, count 0 2006.258.00:12:29.34#ibcon#about to write, iclass 31, count 0 2006.258.00:12:29.34#ibcon#wrote, iclass 31, count 0 2006.258.00:12:29.34#ibcon#about to read 3, iclass 31, count 0 2006.258.00:12:29.36#ibcon#read 3, iclass 31, count 0 2006.258.00:12:29.36#ibcon#about to read 4, iclass 31, count 0 2006.258.00:12:29.36#ibcon#read 4, iclass 31, count 0 2006.258.00:12:29.36#ibcon#about to read 5, iclass 31, count 0 2006.258.00:12:29.36#ibcon#read 5, iclass 31, count 0 2006.258.00:12:29.36#ibcon#about to read 6, iclass 31, count 0 2006.258.00:12:29.36#ibcon#read 6, iclass 31, count 0 2006.258.00:12:29.36#ibcon#end of sib2, iclass 31, count 0 2006.258.00:12:29.36#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:12:29.36#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:12:29.36#ibcon#[27=USB\r\n] 2006.258.00:12:29.36#ibcon#*before write, iclass 31, count 0 2006.258.00:12:29.36#ibcon#enter sib2, iclass 31, count 0 2006.258.00:12:29.36#ibcon#flushed, iclass 31, count 0 2006.258.00:12:29.36#ibcon#about to write, iclass 31, count 0 2006.258.00:12:29.36#ibcon#wrote, iclass 31, count 0 2006.258.00:12:29.36#ibcon#about to read 3, iclass 31, count 0 2006.258.00:12:29.39#ibcon#read 3, iclass 31, count 0 2006.258.00:12:29.39#ibcon#about to read 4, iclass 31, count 0 2006.258.00:12:29.39#ibcon#read 4, iclass 31, count 0 2006.258.00:12:29.39#ibcon#about to read 5, iclass 31, count 0 2006.258.00:12:29.39#ibcon#read 5, iclass 31, count 0 2006.258.00:12:29.39#ibcon#about to read 6, iclass 31, count 0 2006.258.00:12:29.39#ibcon#read 6, iclass 31, count 0 2006.258.00:12:29.39#ibcon#end of sib2, iclass 31, count 0 2006.258.00:12:29.39#ibcon#*after write, iclass 31, count 0 2006.258.00:12:29.39#ibcon#*before return 0, iclass 31, count 0 2006.258.00:12:29.39#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:29.39#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:12:29.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:12:29.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:12:29.39$vck44/vblo=8,744.99 2006.258.00:12:29.39#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.00:12:29.39#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.00:12:29.39#ibcon#ireg 17 cls_cnt 0 2006.258.00:12:29.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:29.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:29.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:29.39#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:12:29.39#ibcon#first serial, iclass 33, count 0 2006.258.00:12:29.39#ibcon#enter sib2, iclass 33, count 0 2006.258.00:12:29.39#ibcon#flushed, iclass 33, count 0 2006.258.00:12:29.39#ibcon#about to write, iclass 33, count 0 2006.258.00:12:29.39#ibcon#wrote, iclass 33, count 0 2006.258.00:12:29.39#ibcon#about to read 3, iclass 33, count 0 2006.258.00:12:29.41#ibcon#read 3, iclass 33, count 0 2006.258.00:12:29.41#ibcon#about to read 4, iclass 33, count 0 2006.258.00:12:29.41#ibcon#read 4, iclass 33, count 0 2006.258.00:12:29.41#ibcon#about to read 5, iclass 33, count 0 2006.258.00:12:29.41#ibcon#read 5, iclass 33, count 0 2006.258.00:12:29.41#ibcon#about to read 6, iclass 33, count 0 2006.258.00:12:29.41#ibcon#read 6, iclass 33, count 0 2006.258.00:12:29.41#ibcon#end of sib2, iclass 33, count 0 2006.258.00:12:29.41#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:12:29.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:12:29.41#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:12:29.41#ibcon#*before write, iclass 33, count 0 2006.258.00:12:29.41#ibcon#enter sib2, iclass 33, count 0 2006.258.00:12:29.41#ibcon#flushed, iclass 33, count 0 2006.258.00:12:29.41#ibcon#about to write, iclass 33, count 0 2006.258.00:12:29.41#ibcon#wrote, iclass 33, count 0 2006.258.00:12:29.41#ibcon#about to read 3, iclass 33, count 0 2006.258.00:12:29.45#ibcon#read 3, iclass 33, count 0 2006.258.00:12:29.45#ibcon#about to read 4, iclass 33, count 0 2006.258.00:12:29.45#ibcon#read 4, iclass 33, count 0 2006.258.00:12:29.45#ibcon#about to read 5, iclass 33, count 0 2006.258.00:12:29.45#ibcon#read 5, iclass 33, count 0 2006.258.00:12:29.45#ibcon#about to read 6, iclass 33, count 0 2006.258.00:12:29.45#ibcon#read 6, iclass 33, count 0 2006.258.00:12:29.45#ibcon#end of sib2, iclass 33, count 0 2006.258.00:12:29.45#ibcon#*after write, iclass 33, count 0 2006.258.00:12:29.45#ibcon#*before return 0, iclass 33, count 0 2006.258.00:12:29.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:29.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:12:29.45#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:12:29.45#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:12:29.45$vck44/vb=8,4 2006.258.00:12:29.45#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.00:12:29.45#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.00:12:29.45#ibcon#ireg 11 cls_cnt 2 2006.258.00:12:29.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:29.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:29.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:29.51#ibcon#enter wrdev, iclass 35, count 2 2006.258.00:12:29.51#ibcon#first serial, iclass 35, count 2 2006.258.00:12:29.51#ibcon#enter sib2, iclass 35, count 2 2006.258.00:12:29.51#ibcon#flushed, iclass 35, count 2 2006.258.00:12:29.51#ibcon#about to write, iclass 35, count 2 2006.258.00:12:29.51#ibcon#wrote, iclass 35, count 2 2006.258.00:12:29.51#ibcon#about to read 3, iclass 35, count 2 2006.258.00:12:29.53#ibcon#read 3, iclass 35, count 2 2006.258.00:12:29.53#ibcon#about to read 4, iclass 35, count 2 2006.258.00:12:29.53#ibcon#read 4, iclass 35, count 2 2006.258.00:12:29.53#ibcon#about to read 5, iclass 35, count 2 2006.258.00:12:29.53#ibcon#read 5, iclass 35, count 2 2006.258.00:12:29.53#ibcon#about to read 6, iclass 35, count 2 2006.258.00:12:29.53#ibcon#read 6, iclass 35, count 2 2006.258.00:12:29.53#ibcon#end of sib2, iclass 35, count 2 2006.258.00:12:29.53#ibcon#*mode == 0, iclass 35, count 2 2006.258.00:12:29.53#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.00:12:29.53#ibcon#[27=AT08-04\r\n] 2006.258.00:12:29.53#ibcon#*before write, iclass 35, count 2 2006.258.00:12:29.53#ibcon#enter sib2, iclass 35, count 2 2006.258.00:12:29.53#ibcon#flushed, iclass 35, count 2 2006.258.00:12:29.53#ibcon#about to write, iclass 35, count 2 2006.258.00:12:29.53#ibcon#wrote, iclass 35, count 2 2006.258.00:12:29.53#ibcon#about to read 3, iclass 35, count 2 2006.258.00:12:29.56#ibcon#read 3, iclass 35, count 2 2006.258.00:12:29.56#ibcon#about to read 4, iclass 35, count 2 2006.258.00:12:29.56#ibcon#read 4, iclass 35, count 2 2006.258.00:12:29.56#ibcon#about to read 5, iclass 35, count 2 2006.258.00:12:29.56#ibcon#read 5, iclass 35, count 2 2006.258.00:12:29.56#ibcon#about to read 6, iclass 35, count 2 2006.258.00:12:29.56#ibcon#read 6, iclass 35, count 2 2006.258.00:12:29.56#ibcon#end of sib2, iclass 35, count 2 2006.258.00:12:29.56#ibcon#*after write, iclass 35, count 2 2006.258.00:12:29.59#ibcon#*before return 0, iclass 35, count 2 2006.258.00:12:29.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:29.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:12:29.59#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.00:12:29.59#ibcon#ireg 7 cls_cnt 0 2006.258.00:12:29.59#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:29.70#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:29.70#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:29.70#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:12:29.70#ibcon#first serial, iclass 35, count 0 2006.258.00:12:29.70#ibcon#enter sib2, iclass 35, count 0 2006.258.00:12:29.70#ibcon#flushed, iclass 35, count 0 2006.258.00:12:29.70#ibcon#about to write, iclass 35, count 0 2006.258.00:12:29.70#ibcon#wrote, iclass 35, count 0 2006.258.00:12:29.70#ibcon#about to read 3, iclass 35, count 0 2006.258.00:12:29.72#ibcon#read 3, iclass 35, count 0 2006.258.00:12:29.72#ibcon#about to read 4, iclass 35, count 0 2006.258.00:12:29.72#ibcon#read 4, iclass 35, count 0 2006.258.00:12:29.72#ibcon#about to read 5, iclass 35, count 0 2006.258.00:12:29.72#ibcon#read 5, iclass 35, count 0 2006.258.00:12:29.72#ibcon#about to read 6, iclass 35, count 0 2006.258.00:12:29.72#ibcon#read 6, iclass 35, count 0 2006.258.00:12:29.72#ibcon#end of sib2, iclass 35, count 0 2006.258.00:12:29.72#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:12:29.72#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:12:29.72#ibcon#[27=USB\r\n] 2006.258.00:12:29.72#ibcon#*before write, iclass 35, count 0 2006.258.00:12:29.72#ibcon#enter sib2, iclass 35, count 0 2006.258.00:12:29.72#ibcon#flushed, iclass 35, count 0 2006.258.00:12:29.72#ibcon#about to write, iclass 35, count 0 2006.258.00:12:29.72#ibcon#wrote, iclass 35, count 0 2006.258.00:12:29.72#ibcon#about to read 3, iclass 35, count 0 2006.258.00:12:29.75#ibcon#read 3, iclass 35, count 0 2006.258.00:12:29.75#ibcon#about to read 4, iclass 35, count 0 2006.258.00:12:29.75#ibcon#read 4, iclass 35, count 0 2006.258.00:12:29.75#ibcon#about to read 5, iclass 35, count 0 2006.258.00:12:29.75#ibcon#read 5, iclass 35, count 0 2006.258.00:12:29.75#ibcon#about to read 6, iclass 35, count 0 2006.258.00:12:29.75#ibcon#read 6, iclass 35, count 0 2006.258.00:12:29.75#ibcon#end of sib2, iclass 35, count 0 2006.258.00:12:29.75#ibcon#*after write, iclass 35, count 0 2006.258.00:12:29.75#ibcon#*before return 0, iclass 35, count 0 2006.258.00:12:29.75#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:29.75#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:12:29.75#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:12:29.75#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:12:29.75$vck44/vabw=wide 2006.258.00:12:29.75#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.00:12:29.75#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.00:12:29.75#ibcon#ireg 8 cls_cnt 0 2006.258.00:12:29.75#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:29.75#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:29.75#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:29.75#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:12:29.75#ibcon#first serial, iclass 37, count 0 2006.258.00:12:29.75#ibcon#enter sib2, iclass 37, count 0 2006.258.00:12:29.75#ibcon#flushed, iclass 37, count 0 2006.258.00:12:29.75#ibcon#about to write, iclass 37, count 0 2006.258.00:12:29.75#ibcon#wrote, iclass 37, count 0 2006.258.00:12:29.75#ibcon#about to read 3, iclass 37, count 0 2006.258.00:12:29.77#ibcon#read 3, iclass 37, count 0 2006.258.00:12:29.77#ibcon#about to read 4, iclass 37, count 0 2006.258.00:12:29.77#ibcon#read 4, iclass 37, count 0 2006.258.00:12:29.77#ibcon#about to read 5, iclass 37, count 0 2006.258.00:12:29.77#ibcon#read 5, iclass 37, count 0 2006.258.00:12:29.77#ibcon#about to read 6, iclass 37, count 0 2006.258.00:12:29.77#ibcon#read 6, iclass 37, count 0 2006.258.00:12:29.77#ibcon#end of sib2, iclass 37, count 0 2006.258.00:12:29.77#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:12:29.77#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:12:29.77#ibcon#[25=BW32\r\n] 2006.258.00:12:29.77#ibcon#*before write, iclass 37, count 0 2006.258.00:12:29.77#ibcon#enter sib2, iclass 37, count 0 2006.258.00:12:29.77#ibcon#flushed, iclass 37, count 0 2006.258.00:12:29.77#ibcon#about to write, iclass 37, count 0 2006.258.00:12:29.77#ibcon#wrote, iclass 37, count 0 2006.258.00:12:29.77#ibcon#about to read 3, iclass 37, count 0 2006.258.00:12:29.80#ibcon#read 3, iclass 37, count 0 2006.258.00:12:29.80#ibcon#about to read 4, iclass 37, count 0 2006.258.00:12:29.80#ibcon#read 4, iclass 37, count 0 2006.258.00:12:29.80#ibcon#about to read 5, iclass 37, count 0 2006.258.00:12:29.80#ibcon#read 5, iclass 37, count 0 2006.258.00:12:29.80#ibcon#about to read 6, iclass 37, count 0 2006.258.00:12:29.80#ibcon#read 6, iclass 37, count 0 2006.258.00:12:29.80#ibcon#end of sib2, iclass 37, count 0 2006.258.00:12:29.80#ibcon#*after write, iclass 37, count 0 2006.258.00:12:29.80#ibcon#*before return 0, iclass 37, count 0 2006.258.00:12:29.80#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:29.80#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:12:29.80#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:12:29.80#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:12:29.80$vck44/vbbw=wide 2006.258.00:12:29.80#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.00:12:29.80#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.00:12:29.80#ibcon#ireg 8 cls_cnt 0 2006.258.00:12:29.80#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:12:29.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:12:29.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:12:29.87#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:12:29.87#ibcon#first serial, iclass 39, count 0 2006.258.00:12:29.87#ibcon#enter sib2, iclass 39, count 0 2006.258.00:12:29.87#ibcon#flushed, iclass 39, count 0 2006.258.00:12:29.87#ibcon#about to write, iclass 39, count 0 2006.258.00:12:29.87#ibcon#wrote, iclass 39, count 0 2006.258.00:12:29.87#ibcon#about to read 3, iclass 39, count 0 2006.258.00:12:29.89#ibcon#read 3, iclass 39, count 0 2006.258.00:12:29.89#ibcon#about to read 4, iclass 39, count 0 2006.258.00:12:29.89#ibcon#read 4, iclass 39, count 0 2006.258.00:12:29.89#ibcon#about to read 5, iclass 39, count 0 2006.258.00:12:29.89#ibcon#read 5, iclass 39, count 0 2006.258.00:12:29.89#ibcon#about to read 6, iclass 39, count 0 2006.258.00:12:29.89#ibcon#read 6, iclass 39, count 0 2006.258.00:12:29.89#ibcon#end of sib2, iclass 39, count 0 2006.258.00:12:29.89#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:12:29.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:12:29.89#ibcon#[27=BW32\r\n] 2006.258.00:12:29.89#ibcon#*before write, iclass 39, count 0 2006.258.00:12:29.89#ibcon#enter sib2, iclass 39, count 0 2006.258.00:12:29.89#ibcon#flushed, iclass 39, count 0 2006.258.00:12:29.89#ibcon#about to write, iclass 39, count 0 2006.258.00:12:29.89#ibcon#wrote, iclass 39, count 0 2006.258.00:12:29.89#ibcon#about to read 3, iclass 39, count 0 2006.258.00:12:29.92#ibcon#read 3, iclass 39, count 0 2006.258.00:12:29.92#ibcon#about to read 4, iclass 39, count 0 2006.258.00:12:29.92#ibcon#read 4, iclass 39, count 0 2006.258.00:12:29.92#ibcon#about to read 5, iclass 39, count 0 2006.258.00:12:29.92#ibcon#read 5, iclass 39, count 0 2006.258.00:12:29.92#ibcon#about to read 6, iclass 39, count 0 2006.258.00:12:29.92#ibcon#read 6, iclass 39, count 0 2006.258.00:12:29.92#ibcon#end of sib2, iclass 39, count 0 2006.258.00:12:29.92#ibcon#*after write, iclass 39, count 0 2006.258.00:12:29.92#ibcon#*before return 0, iclass 39, count 0 2006.258.00:12:29.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:12:29.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:12:29.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:12:29.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:12:29.92$setupk4/ifdk4 2006.258.00:12:29.92$ifdk4/lo= 2006.258.00:12:29.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:12:29.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:12:29.92$ifdk4/patch= 2006.258.00:12:29.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:12:29.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:12:29.92$setupk4/!*+20s 2006.258.00:12:33.33#abcon#<5=/01 1.4 4.0 21.77 781016.2\r\n> 2006.258.00:12:33.35#abcon#{5=INTERFACE CLEAR} 2006.258.00:12:33.41#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:12:43.14#trakl#Source acquired 2006.258.00:12:43.14#flagr#flagr/antenna,acquired 2006.258.00:12:43.50#abcon#<5=/01 1.4 4.0 21.77 781016.2\r\n> 2006.258.00:12:43.52#abcon#{5=INTERFACE CLEAR} 2006.258.00:12:43.58#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:12:44.27$setupk4/"tpicd 2006.258.00:12:44.27$setupk4/echo=off 2006.258.00:12:44.27$setupk4/xlog=off 2006.258.00:12:44.27:!2006.258.00:18:34 2006.258.00:18:34.00:preob 2006.258.00:18:35.14/onsource/TRACKING 2006.258.00:18:35.14:!2006.258.00:18:44 2006.258.00:18:44.00:"tape 2006.258.00:18:44.00:"st=record 2006.258.00:18:44.00:data_valid=on 2006.258.00:18:44.00:midob 2006.258.00:18:44.14/onsource/TRACKING 2006.258.00:18:44.14/wx/21.81,1016.2,81 2006.258.00:18:44.31/cable/+6.4800E-03 2006.258.00:18:45.40/va/01,08,usb,yes,30,33 2006.258.00:18:45.40/va/02,07,usb,yes,33,33 2006.258.00:18:45.40/va/03,08,usb,yes,29,31 2006.258.00:18:45.40/va/04,07,usb,yes,34,35 2006.258.00:18:45.40/va/05,04,usb,yes,30,31 2006.258.00:18:45.40/va/06,04,usb,yes,34,33 2006.258.00:18:45.40/va/07,04,usb,yes,35,35 2006.258.00:18:45.40/va/08,04,usb,yes,29,35 2006.258.00:18:45.63/valo/01,524.99,yes,locked 2006.258.00:18:45.63/valo/02,534.99,yes,locked 2006.258.00:18:45.63/valo/03,564.99,yes,locked 2006.258.00:18:45.63/valo/04,624.99,yes,locked 2006.258.00:18:45.63/valo/05,734.99,yes,locked 2006.258.00:18:45.63/valo/06,814.99,yes,locked 2006.258.00:18:45.63/valo/07,864.99,yes,locked 2006.258.00:18:45.63/valo/08,884.99,yes,locked 2006.258.00:18:46.72/vb/01,04,usb,yes,30,28 2006.258.00:18:46.72/vb/02,05,usb,yes,29,29 2006.258.00:18:46.72/vb/03,04,usb,yes,30,33 2006.258.00:18:46.72/vb/04,05,usb,yes,30,29 2006.258.00:18:46.72/vb/05,04,usb,yes,26,29 2006.258.00:18:46.72/vb/06,04,usb,yes,31,27 2006.258.00:18:46.72/vb/07,04,usb,yes,31,31 2006.258.00:18:46.72/vb/08,04,usb,yes,28,32 2006.258.00:18:46.95/vblo/01,629.99,yes,locked 2006.258.00:18:46.95/vblo/02,634.99,yes,locked 2006.258.00:18:46.95/vblo/03,649.99,yes,locked 2006.258.00:18:46.95/vblo/04,679.99,yes,locked 2006.258.00:18:46.95/vblo/05,709.99,yes,locked 2006.258.00:18:46.95/vblo/06,719.99,yes,locked 2006.258.00:18:46.95/vblo/07,734.99,yes,locked 2006.258.00:18:46.95/vblo/08,744.99,yes,locked 2006.258.00:18:47.10/vabw/8 2006.258.00:18:47.25/vbbw/8 2006.258.00:18:47.34/xfe/off,on,15.0 2006.258.00:18:47.71/ifatt/23,28,28,28 2006.258.00:18:48.07/fmout-gps/S +4.56E-07 2006.258.00:18:48.11:!2006.258.00:22:04 2006.258.00:22:04.00:data_valid=off 2006.258.00:22:04.00:"et 2006.258.00:22:04.00:!+3s 2006.258.00:22:07.01:"tape 2006.258.00:22:07.01:postob 2006.258.00:22:07.07/cable/+6.4796E-03 2006.258.00:22:07.07/wx/21.84,1016.1,79 2006.258.00:22:08.07/fmout-gps/S +4.56E-07 2006.258.00:22:08.07:scan_name=258-0025,jd0609,50 2006.258.00:22:08.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.258.00:22:09.14#flagr#flagr/antenna,new-source 2006.258.00:22:09.14:checkk5 2006.258.00:22:09.55/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:22:09.95/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:22:10.36/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:22:10.76/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:22:11.13/chk_obsdata//k5ts1/T2580018??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.258.00:22:11.52/chk_obsdata//k5ts2/T2580018??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.258.00:22:11.92/chk_obsdata//k5ts3/T2580018??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.258.00:22:12.32/chk_obsdata//k5ts4/T2580018??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.258.00:22:13.04/k5log//k5ts1_log_newline 2006.258.00:22:13.73/k5log//k5ts2_log_newline 2006.258.00:22:14.45/k5log//k5ts3_log_newline 2006.258.00:22:15.15/k5log//k5ts4_log_newline 2006.258.00:22:15.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:22:15.18:setupk4=1 2006.258.00:22:15.18$setupk4/echo=on 2006.258.00:22:15.18$setupk4/pcalon 2006.258.00:22:15.18$pcalon/"no phase cal control is implemented here 2006.258.00:22:15.18$setupk4/"tpicd=stop 2006.258.00:22:15.18$setupk4/"rec=synch_on 2006.258.00:22:15.18$setupk4/"rec_mode=128 2006.258.00:22:15.18$setupk4/!* 2006.258.00:22:15.18$setupk4/recpk4 2006.258.00:22:15.18$recpk4/recpatch= 2006.258.00:22:15.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:22:15.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:22:15.18$setupk4/vck44 2006.258.00:22:15.18$vck44/valo=1,524.99 2006.258.00:22:15.18#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.00:22:15.18#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.00:22:15.18#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:15.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:15.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:15.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:15.18#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:22:15.18#ibcon#first serial, iclass 24, count 0 2006.258.00:22:15.18#ibcon#enter sib2, iclass 24, count 0 2006.258.00:22:15.18#ibcon#flushed, iclass 24, count 0 2006.258.00:22:15.18#ibcon#about to write, iclass 24, count 0 2006.258.00:22:15.18#ibcon#wrote, iclass 24, count 0 2006.258.00:22:15.18#ibcon#about to read 3, iclass 24, count 0 2006.258.00:22:15.20#ibcon#read 3, iclass 24, count 0 2006.258.00:22:15.20#ibcon#about to read 4, iclass 24, count 0 2006.258.00:22:15.20#ibcon#read 4, iclass 24, count 0 2006.258.00:22:15.20#ibcon#about to read 5, iclass 24, count 0 2006.258.00:22:15.20#ibcon#read 5, iclass 24, count 0 2006.258.00:22:15.20#ibcon#about to read 6, iclass 24, count 0 2006.258.00:22:15.20#ibcon#read 6, iclass 24, count 0 2006.258.00:22:15.20#ibcon#end of sib2, iclass 24, count 0 2006.258.00:22:15.20#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:22:15.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:22:15.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:22:15.20#ibcon#*before write, iclass 24, count 0 2006.258.00:22:15.20#ibcon#enter sib2, iclass 24, count 0 2006.258.00:22:15.20#ibcon#flushed, iclass 24, count 0 2006.258.00:22:15.20#ibcon#about to write, iclass 24, count 0 2006.258.00:22:15.20#ibcon#wrote, iclass 24, count 0 2006.258.00:22:15.20#ibcon#about to read 3, iclass 24, count 0 2006.258.00:22:15.25#ibcon#read 3, iclass 24, count 0 2006.258.00:22:15.25#ibcon#about to read 4, iclass 24, count 0 2006.258.00:22:15.25#ibcon#read 4, iclass 24, count 0 2006.258.00:22:15.25#ibcon#about to read 5, iclass 24, count 0 2006.258.00:22:15.25#ibcon#read 5, iclass 24, count 0 2006.258.00:22:15.25#ibcon#about to read 6, iclass 24, count 0 2006.258.00:22:15.25#ibcon#read 6, iclass 24, count 0 2006.258.00:22:15.25#ibcon#end of sib2, iclass 24, count 0 2006.258.00:22:15.25#ibcon#*after write, iclass 24, count 0 2006.258.00:22:15.25#ibcon#*before return 0, iclass 24, count 0 2006.258.00:22:15.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:15.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:15.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:22:15.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:22:15.25$vck44/va=1,8 2006.258.00:22:15.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.00:22:15.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.00:22:15.25#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:15.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:15.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:15.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:15.25#ibcon#enter wrdev, iclass 26, count 2 2006.258.00:22:15.25#ibcon#first serial, iclass 26, count 2 2006.258.00:22:15.25#ibcon#enter sib2, iclass 26, count 2 2006.258.00:22:15.25#ibcon#flushed, iclass 26, count 2 2006.258.00:22:15.25#ibcon#about to write, iclass 26, count 2 2006.258.00:22:15.25#ibcon#wrote, iclass 26, count 2 2006.258.00:22:15.25#ibcon#about to read 3, iclass 26, count 2 2006.258.00:22:15.27#ibcon#read 3, iclass 26, count 2 2006.258.00:22:15.27#ibcon#about to read 4, iclass 26, count 2 2006.258.00:22:15.27#ibcon#read 4, iclass 26, count 2 2006.258.00:22:15.27#ibcon#about to read 5, iclass 26, count 2 2006.258.00:22:15.27#ibcon#read 5, iclass 26, count 2 2006.258.00:22:15.27#ibcon#about to read 6, iclass 26, count 2 2006.258.00:22:15.27#ibcon#read 6, iclass 26, count 2 2006.258.00:22:15.27#ibcon#end of sib2, iclass 26, count 2 2006.258.00:22:15.27#ibcon#*mode == 0, iclass 26, count 2 2006.258.00:22:15.27#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.00:22:15.27#ibcon#[25=AT01-08\r\n] 2006.258.00:22:15.27#ibcon#*before write, iclass 26, count 2 2006.258.00:22:15.27#ibcon#enter sib2, iclass 26, count 2 2006.258.00:22:15.27#ibcon#flushed, iclass 26, count 2 2006.258.00:22:15.27#ibcon#about to write, iclass 26, count 2 2006.258.00:22:15.27#ibcon#wrote, iclass 26, count 2 2006.258.00:22:15.27#ibcon#about to read 3, iclass 26, count 2 2006.258.00:22:15.30#ibcon#read 3, iclass 26, count 2 2006.258.00:22:15.30#ibcon#about to read 4, iclass 26, count 2 2006.258.00:22:15.30#ibcon#read 4, iclass 26, count 2 2006.258.00:22:15.30#ibcon#about to read 5, iclass 26, count 2 2006.258.00:22:15.30#ibcon#read 5, iclass 26, count 2 2006.258.00:22:15.30#ibcon#about to read 6, iclass 26, count 2 2006.258.00:22:15.30#ibcon#read 6, iclass 26, count 2 2006.258.00:22:15.30#ibcon#end of sib2, iclass 26, count 2 2006.258.00:22:15.30#ibcon#*after write, iclass 26, count 2 2006.258.00:22:15.30#ibcon#*before return 0, iclass 26, count 2 2006.258.00:22:15.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:15.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:15.30#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.00:22:15.30#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:15.30#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:15.42#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:15.42#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:15.42#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:22:15.42#ibcon#first serial, iclass 26, count 0 2006.258.00:22:15.42#ibcon#enter sib2, iclass 26, count 0 2006.258.00:22:15.42#ibcon#flushed, iclass 26, count 0 2006.258.00:22:15.42#ibcon#about to write, iclass 26, count 0 2006.258.00:22:15.42#ibcon#wrote, iclass 26, count 0 2006.258.00:22:15.42#ibcon#about to read 3, iclass 26, count 0 2006.258.00:22:15.44#ibcon#read 3, iclass 26, count 0 2006.258.00:22:15.44#ibcon#about to read 4, iclass 26, count 0 2006.258.00:22:15.44#ibcon#read 4, iclass 26, count 0 2006.258.00:22:15.44#ibcon#about to read 5, iclass 26, count 0 2006.258.00:22:15.44#ibcon#read 5, iclass 26, count 0 2006.258.00:22:15.44#ibcon#about to read 6, iclass 26, count 0 2006.258.00:22:15.44#ibcon#read 6, iclass 26, count 0 2006.258.00:22:15.44#ibcon#end of sib2, iclass 26, count 0 2006.258.00:22:15.44#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:22:15.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:22:15.44#ibcon#[25=USB\r\n] 2006.258.00:22:15.44#ibcon#*before write, iclass 26, count 0 2006.258.00:22:15.44#ibcon#enter sib2, iclass 26, count 0 2006.258.00:22:15.44#ibcon#flushed, iclass 26, count 0 2006.258.00:22:15.44#ibcon#about to write, iclass 26, count 0 2006.258.00:22:15.44#ibcon#wrote, iclass 26, count 0 2006.258.00:22:15.44#ibcon#about to read 3, iclass 26, count 0 2006.258.00:22:15.47#ibcon#read 3, iclass 26, count 0 2006.258.00:22:15.47#ibcon#about to read 4, iclass 26, count 0 2006.258.00:22:15.47#ibcon#read 4, iclass 26, count 0 2006.258.00:22:15.47#ibcon#about to read 5, iclass 26, count 0 2006.258.00:22:15.47#ibcon#read 5, iclass 26, count 0 2006.258.00:22:15.47#ibcon#about to read 6, iclass 26, count 0 2006.258.00:22:15.47#ibcon#read 6, iclass 26, count 0 2006.258.00:22:15.47#ibcon#end of sib2, iclass 26, count 0 2006.258.00:22:15.47#ibcon#*after write, iclass 26, count 0 2006.258.00:22:15.47#ibcon#*before return 0, iclass 26, count 0 2006.258.00:22:15.47#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:15.47#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:15.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:22:15.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:22:15.47$vck44/valo=2,534.99 2006.258.00:22:15.47#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.00:22:15.47#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.00:22:15.47#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:15.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:15.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:15.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:15.47#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:22:15.47#ibcon#first serial, iclass 28, count 0 2006.258.00:22:15.47#ibcon#enter sib2, iclass 28, count 0 2006.258.00:22:15.47#ibcon#flushed, iclass 28, count 0 2006.258.00:22:15.47#ibcon#about to write, iclass 28, count 0 2006.258.00:22:15.47#ibcon#wrote, iclass 28, count 0 2006.258.00:22:15.47#ibcon#about to read 3, iclass 28, count 0 2006.258.00:22:15.49#ibcon#read 3, iclass 28, count 0 2006.258.00:22:15.49#ibcon#about to read 4, iclass 28, count 0 2006.258.00:22:15.49#ibcon#read 4, iclass 28, count 0 2006.258.00:22:15.49#ibcon#about to read 5, iclass 28, count 0 2006.258.00:22:15.49#ibcon#read 5, iclass 28, count 0 2006.258.00:22:15.49#ibcon#about to read 6, iclass 28, count 0 2006.258.00:22:15.49#ibcon#read 6, iclass 28, count 0 2006.258.00:22:15.49#ibcon#end of sib2, iclass 28, count 0 2006.258.00:22:15.49#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:22:15.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:22:15.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:22:15.49#ibcon#*before write, iclass 28, count 0 2006.258.00:22:15.49#ibcon#enter sib2, iclass 28, count 0 2006.258.00:22:15.49#ibcon#flushed, iclass 28, count 0 2006.258.00:22:15.49#ibcon#about to write, iclass 28, count 0 2006.258.00:22:15.49#ibcon#wrote, iclass 28, count 0 2006.258.00:22:15.49#ibcon#about to read 3, iclass 28, count 0 2006.258.00:22:15.53#ibcon#read 3, iclass 28, count 0 2006.258.00:22:15.53#ibcon#about to read 4, iclass 28, count 0 2006.258.00:22:15.53#ibcon#read 4, iclass 28, count 0 2006.258.00:22:15.53#ibcon#about to read 5, iclass 28, count 0 2006.258.00:22:15.53#ibcon#read 5, iclass 28, count 0 2006.258.00:22:15.53#ibcon#about to read 6, iclass 28, count 0 2006.258.00:22:15.53#ibcon#read 6, iclass 28, count 0 2006.258.00:22:15.53#ibcon#end of sib2, iclass 28, count 0 2006.258.00:22:15.53#ibcon#*after write, iclass 28, count 0 2006.258.00:22:15.53#ibcon#*before return 0, iclass 28, count 0 2006.258.00:22:15.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:15.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:15.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:22:15.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:22:15.53$vck44/va=2,7 2006.258.00:22:15.53#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.00:22:15.53#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.00:22:15.53#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:15.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:15.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:15.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:15.59#ibcon#enter wrdev, iclass 30, count 2 2006.258.00:22:15.59#ibcon#first serial, iclass 30, count 2 2006.258.00:22:15.59#ibcon#enter sib2, iclass 30, count 2 2006.258.00:22:15.59#ibcon#flushed, iclass 30, count 2 2006.258.00:22:15.59#ibcon#about to write, iclass 30, count 2 2006.258.00:22:15.59#ibcon#wrote, iclass 30, count 2 2006.258.00:22:15.59#ibcon#about to read 3, iclass 30, count 2 2006.258.00:22:15.61#ibcon#read 3, iclass 30, count 2 2006.258.00:22:15.61#ibcon#about to read 4, iclass 30, count 2 2006.258.00:22:15.61#ibcon#read 4, iclass 30, count 2 2006.258.00:22:15.61#ibcon#about to read 5, iclass 30, count 2 2006.258.00:22:15.61#ibcon#read 5, iclass 30, count 2 2006.258.00:22:15.61#ibcon#about to read 6, iclass 30, count 2 2006.258.00:22:15.61#ibcon#read 6, iclass 30, count 2 2006.258.00:22:15.61#ibcon#end of sib2, iclass 30, count 2 2006.258.00:22:15.61#ibcon#*mode == 0, iclass 30, count 2 2006.258.00:22:15.61#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.00:22:15.61#ibcon#[25=AT02-07\r\n] 2006.258.00:22:15.61#ibcon#*before write, iclass 30, count 2 2006.258.00:22:15.61#ibcon#enter sib2, iclass 30, count 2 2006.258.00:22:15.61#ibcon#flushed, iclass 30, count 2 2006.258.00:22:15.61#ibcon#about to write, iclass 30, count 2 2006.258.00:22:15.61#ibcon#wrote, iclass 30, count 2 2006.258.00:22:15.61#ibcon#about to read 3, iclass 30, count 2 2006.258.00:22:15.64#ibcon#read 3, iclass 30, count 2 2006.258.00:22:15.64#ibcon#about to read 4, iclass 30, count 2 2006.258.00:22:15.64#ibcon#read 4, iclass 30, count 2 2006.258.00:22:15.64#ibcon#about to read 5, iclass 30, count 2 2006.258.00:22:15.64#ibcon#read 5, iclass 30, count 2 2006.258.00:22:15.64#ibcon#about to read 6, iclass 30, count 2 2006.258.00:22:15.64#ibcon#read 6, iclass 30, count 2 2006.258.00:22:15.64#ibcon#end of sib2, iclass 30, count 2 2006.258.00:22:15.64#ibcon#*after write, iclass 30, count 2 2006.258.00:22:15.64#ibcon#*before return 0, iclass 30, count 2 2006.258.00:22:15.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:15.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:15.64#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.00:22:15.64#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:15.64#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:15.76#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:15.76#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:15.76#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:22:15.76#ibcon#first serial, iclass 30, count 0 2006.258.00:22:15.76#ibcon#enter sib2, iclass 30, count 0 2006.258.00:22:15.76#ibcon#flushed, iclass 30, count 0 2006.258.00:22:15.76#ibcon#about to write, iclass 30, count 0 2006.258.00:22:15.76#ibcon#wrote, iclass 30, count 0 2006.258.00:22:15.76#ibcon#about to read 3, iclass 30, count 0 2006.258.00:22:15.78#ibcon#read 3, iclass 30, count 0 2006.258.00:22:15.78#ibcon#about to read 4, iclass 30, count 0 2006.258.00:22:15.78#ibcon#read 4, iclass 30, count 0 2006.258.00:22:15.78#ibcon#about to read 5, iclass 30, count 0 2006.258.00:22:15.78#ibcon#read 5, iclass 30, count 0 2006.258.00:22:15.78#ibcon#about to read 6, iclass 30, count 0 2006.258.00:22:15.78#ibcon#read 6, iclass 30, count 0 2006.258.00:22:15.78#ibcon#end of sib2, iclass 30, count 0 2006.258.00:22:15.78#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:22:15.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:22:15.78#ibcon#[25=USB\r\n] 2006.258.00:22:15.78#ibcon#*before write, iclass 30, count 0 2006.258.00:22:15.78#ibcon#enter sib2, iclass 30, count 0 2006.258.00:22:15.78#ibcon#flushed, iclass 30, count 0 2006.258.00:22:15.78#ibcon#about to write, iclass 30, count 0 2006.258.00:22:15.78#ibcon#wrote, iclass 30, count 0 2006.258.00:22:15.78#ibcon#about to read 3, iclass 30, count 0 2006.258.00:22:15.81#ibcon#read 3, iclass 30, count 0 2006.258.00:22:15.81#ibcon#about to read 4, iclass 30, count 0 2006.258.00:22:15.81#ibcon#read 4, iclass 30, count 0 2006.258.00:22:15.81#ibcon#about to read 5, iclass 30, count 0 2006.258.00:22:15.81#ibcon#read 5, iclass 30, count 0 2006.258.00:22:15.81#ibcon#about to read 6, iclass 30, count 0 2006.258.00:22:15.81#ibcon#read 6, iclass 30, count 0 2006.258.00:22:15.81#ibcon#end of sib2, iclass 30, count 0 2006.258.00:22:15.81#ibcon#*after write, iclass 30, count 0 2006.258.00:22:15.81#ibcon#*before return 0, iclass 30, count 0 2006.258.00:22:15.81#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:15.81#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:15.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:22:15.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:22:15.81$vck44/valo=3,564.99 2006.258.00:22:15.81#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.258.00:22:15.81#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.258.00:22:15.81#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:15.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:15.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:15.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:15.81#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:22:15.81#ibcon#first serial, iclass 32, count 0 2006.258.00:22:15.81#ibcon#enter sib2, iclass 32, count 0 2006.258.00:22:15.81#ibcon#flushed, iclass 32, count 0 2006.258.00:22:15.81#ibcon#about to write, iclass 32, count 0 2006.258.00:22:15.81#ibcon#wrote, iclass 32, count 0 2006.258.00:22:15.81#ibcon#about to read 3, iclass 32, count 0 2006.258.00:22:15.83#ibcon#read 3, iclass 32, count 0 2006.258.00:22:15.83#ibcon#about to read 4, iclass 32, count 0 2006.258.00:22:15.83#ibcon#read 4, iclass 32, count 0 2006.258.00:22:15.83#ibcon#about to read 5, iclass 32, count 0 2006.258.00:22:15.83#ibcon#read 5, iclass 32, count 0 2006.258.00:22:15.83#ibcon#about to read 6, iclass 32, count 0 2006.258.00:22:15.83#ibcon#read 6, iclass 32, count 0 2006.258.00:22:15.83#ibcon#end of sib2, iclass 32, count 0 2006.258.00:22:15.83#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:22:15.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:22:15.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:22:15.83#ibcon#*before write, iclass 32, count 0 2006.258.00:22:15.83#ibcon#enter sib2, iclass 32, count 0 2006.258.00:22:15.83#ibcon#flushed, iclass 32, count 0 2006.258.00:22:15.83#ibcon#about to write, iclass 32, count 0 2006.258.00:22:15.83#ibcon#wrote, iclass 32, count 0 2006.258.00:22:15.83#ibcon#about to read 3, iclass 32, count 0 2006.258.00:22:15.87#ibcon#read 3, iclass 32, count 0 2006.258.00:22:15.87#ibcon#about to read 4, iclass 32, count 0 2006.258.00:22:15.87#ibcon#read 4, iclass 32, count 0 2006.258.00:22:15.87#ibcon#about to read 5, iclass 32, count 0 2006.258.00:22:15.87#ibcon#read 5, iclass 32, count 0 2006.258.00:22:15.87#ibcon#about to read 6, iclass 32, count 0 2006.258.00:22:15.87#ibcon#read 6, iclass 32, count 0 2006.258.00:22:15.87#ibcon#end of sib2, iclass 32, count 0 2006.258.00:22:15.87#ibcon#*after write, iclass 32, count 0 2006.258.00:22:15.87#ibcon#*before return 0, iclass 32, count 0 2006.258.00:22:15.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:15.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:15.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:22:15.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:22:15.87$vck44/va=3,8 2006.258.00:22:15.87#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.258.00:22:15.87#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.258.00:22:15.87#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:15.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:15.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:15.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:15.93#ibcon#enter wrdev, iclass 34, count 2 2006.258.00:22:15.93#ibcon#first serial, iclass 34, count 2 2006.258.00:22:15.93#ibcon#enter sib2, iclass 34, count 2 2006.258.00:22:15.93#ibcon#flushed, iclass 34, count 2 2006.258.00:22:15.93#ibcon#about to write, iclass 34, count 2 2006.258.00:22:15.93#ibcon#wrote, iclass 34, count 2 2006.258.00:22:15.93#ibcon#about to read 3, iclass 34, count 2 2006.258.00:22:15.95#ibcon#read 3, iclass 34, count 2 2006.258.00:22:15.95#ibcon#about to read 4, iclass 34, count 2 2006.258.00:22:15.95#ibcon#read 4, iclass 34, count 2 2006.258.00:22:15.95#ibcon#about to read 5, iclass 34, count 2 2006.258.00:22:15.95#ibcon#read 5, iclass 34, count 2 2006.258.00:22:15.95#ibcon#about to read 6, iclass 34, count 2 2006.258.00:22:15.95#ibcon#read 6, iclass 34, count 2 2006.258.00:22:15.95#ibcon#end of sib2, iclass 34, count 2 2006.258.00:22:15.95#ibcon#*mode == 0, iclass 34, count 2 2006.258.00:22:15.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.258.00:22:15.95#ibcon#[25=AT03-08\r\n] 2006.258.00:22:15.95#ibcon#*before write, iclass 34, count 2 2006.258.00:22:15.95#ibcon#enter sib2, iclass 34, count 2 2006.258.00:22:15.95#ibcon#flushed, iclass 34, count 2 2006.258.00:22:15.95#ibcon#about to write, iclass 34, count 2 2006.258.00:22:15.95#ibcon#wrote, iclass 34, count 2 2006.258.00:22:15.95#ibcon#about to read 3, iclass 34, count 2 2006.258.00:22:15.98#ibcon#read 3, iclass 34, count 2 2006.258.00:22:15.98#ibcon#about to read 4, iclass 34, count 2 2006.258.00:22:15.98#ibcon#read 4, iclass 34, count 2 2006.258.00:22:15.98#ibcon#about to read 5, iclass 34, count 2 2006.258.00:22:15.98#ibcon#read 5, iclass 34, count 2 2006.258.00:22:15.98#ibcon#about to read 6, iclass 34, count 2 2006.258.00:22:15.98#ibcon#read 6, iclass 34, count 2 2006.258.00:22:15.98#ibcon#end of sib2, iclass 34, count 2 2006.258.00:22:15.98#ibcon#*after write, iclass 34, count 2 2006.258.00:22:15.98#ibcon#*before return 0, iclass 34, count 2 2006.258.00:22:15.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:15.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:15.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.258.00:22:15.98#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:15.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:16.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:16.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:16.10#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:22:16.10#ibcon#first serial, iclass 34, count 0 2006.258.00:22:16.10#ibcon#enter sib2, iclass 34, count 0 2006.258.00:22:16.10#ibcon#flushed, iclass 34, count 0 2006.258.00:22:16.10#ibcon#about to write, iclass 34, count 0 2006.258.00:22:16.10#ibcon#wrote, iclass 34, count 0 2006.258.00:22:16.10#ibcon#about to read 3, iclass 34, count 0 2006.258.00:22:16.12#ibcon#read 3, iclass 34, count 0 2006.258.00:22:16.12#ibcon#about to read 4, iclass 34, count 0 2006.258.00:22:16.12#ibcon#read 4, iclass 34, count 0 2006.258.00:22:16.12#ibcon#about to read 5, iclass 34, count 0 2006.258.00:22:16.12#ibcon#read 5, iclass 34, count 0 2006.258.00:22:16.12#ibcon#about to read 6, iclass 34, count 0 2006.258.00:22:16.12#ibcon#read 6, iclass 34, count 0 2006.258.00:22:16.12#ibcon#end of sib2, iclass 34, count 0 2006.258.00:22:16.12#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:22:16.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:22:16.12#ibcon#[25=USB\r\n] 2006.258.00:22:16.12#ibcon#*before write, iclass 34, count 0 2006.258.00:22:16.12#ibcon#enter sib2, iclass 34, count 0 2006.258.00:22:16.12#ibcon#flushed, iclass 34, count 0 2006.258.00:22:16.12#ibcon#about to write, iclass 34, count 0 2006.258.00:22:16.12#ibcon#wrote, iclass 34, count 0 2006.258.00:22:16.12#ibcon#about to read 3, iclass 34, count 0 2006.258.00:22:16.15#ibcon#read 3, iclass 34, count 0 2006.258.00:22:16.15#ibcon#about to read 4, iclass 34, count 0 2006.258.00:22:16.15#ibcon#read 4, iclass 34, count 0 2006.258.00:22:16.15#ibcon#about to read 5, iclass 34, count 0 2006.258.00:22:16.15#ibcon#read 5, iclass 34, count 0 2006.258.00:22:16.15#ibcon#about to read 6, iclass 34, count 0 2006.258.00:22:16.15#ibcon#read 6, iclass 34, count 0 2006.258.00:22:16.15#ibcon#end of sib2, iclass 34, count 0 2006.258.00:22:16.15#ibcon#*after write, iclass 34, count 0 2006.258.00:22:16.15#ibcon#*before return 0, iclass 34, count 0 2006.258.00:22:16.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:16.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:16.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:22:16.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:22:16.15$vck44/valo=4,624.99 2006.258.00:22:16.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.258.00:22:16.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.258.00:22:16.15#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:16.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:16.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:16.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:16.15#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:22:16.15#ibcon#first serial, iclass 36, count 0 2006.258.00:22:16.15#ibcon#enter sib2, iclass 36, count 0 2006.258.00:22:16.15#ibcon#flushed, iclass 36, count 0 2006.258.00:22:16.15#ibcon#about to write, iclass 36, count 0 2006.258.00:22:16.15#ibcon#wrote, iclass 36, count 0 2006.258.00:22:16.15#ibcon#about to read 3, iclass 36, count 0 2006.258.00:22:16.17#ibcon#read 3, iclass 36, count 0 2006.258.00:22:16.17#ibcon#about to read 4, iclass 36, count 0 2006.258.00:22:16.17#ibcon#read 4, iclass 36, count 0 2006.258.00:22:16.17#ibcon#about to read 5, iclass 36, count 0 2006.258.00:22:16.17#ibcon#read 5, iclass 36, count 0 2006.258.00:22:16.17#ibcon#about to read 6, iclass 36, count 0 2006.258.00:22:16.17#ibcon#read 6, iclass 36, count 0 2006.258.00:22:16.17#ibcon#end of sib2, iclass 36, count 0 2006.258.00:22:16.17#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:22:16.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:22:16.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:22:16.17#ibcon#*before write, iclass 36, count 0 2006.258.00:22:16.17#ibcon#enter sib2, iclass 36, count 0 2006.258.00:22:16.17#ibcon#flushed, iclass 36, count 0 2006.258.00:22:16.17#ibcon#about to write, iclass 36, count 0 2006.258.00:22:16.17#ibcon#wrote, iclass 36, count 0 2006.258.00:22:16.17#ibcon#about to read 3, iclass 36, count 0 2006.258.00:22:16.21#ibcon#read 3, iclass 36, count 0 2006.258.00:22:16.21#ibcon#about to read 4, iclass 36, count 0 2006.258.00:22:16.21#ibcon#read 4, iclass 36, count 0 2006.258.00:22:16.21#ibcon#about to read 5, iclass 36, count 0 2006.258.00:22:16.21#ibcon#read 5, iclass 36, count 0 2006.258.00:22:16.21#ibcon#about to read 6, iclass 36, count 0 2006.258.00:22:16.21#ibcon#read 6, iclass 36, count 0 2006.258.00:22:16.21#ibcon#end of sib2, iclass 36, count 0 2006.258.00:22:16.21#ibcon#*after write, iclass 36, count 0 2006.258.00:22:16.21#ibcon#*before return 0, iclass 36, count 0 2006.258.00:22:16.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:16.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:16.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:22:16.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:22:16.21$vck44/va=4,7 2006.258.00:22:16.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.258.00:22:16.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.258.00:22:16.21#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:16.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:16.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:16.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:16.27#ibcon#enter wrdev, iclass 38, count 2 2006.258.00:22:16.27#ibcon#first serial, iclass 38, count 2 2006.258.00:22:16.27#ibcon#enter sib2, iclass 38, count 2 2006.258.00:22:16.27#ibcon#flushed, iclass 38, count 2 2006.258.00:22:16.27#ibcon#about to write, iclass 38, count 2 2006.258.00:22:16.27#ibcon#wrote, iclass 38, count 2 2006.258.00:22:16.27#ibcon#about to read 3, iclass 38, count 2 2006.258.00:22:16.29#ibcon#read 3, iclass 38, count 2 2006.258.00:22:16.29#ibcon#about to read 4, iclass 38, count 2 2006.258.00:22:16.29#ibcon#read 4, iclass 38, count 2 2006.258.00:22:16.29#ibcon#about to read 5, iclass 38, count 2 2006.258.00:22:16.29#ibcon#read 5, iclass 38, count 2 2006.258.00:22:16.29#ibcon#about to read 6, iclass 38, count 2 2006.258.00:22:16.29#ibcon#read 6, iclass 38, count 2 2006.258.00:22:16.29#ibcon#end of sib2, iclass 38, count 2 2006.258.00:22:16.29#ibcon#*mode == 0, iclass 38, count 2 2006.258.00:22:16.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.258.00:22:16.29#ibcon#[25=AT04-07\r\n] 2006.258.00:22:16.29#ibcon#*before write, iclass 38, count 2 2006.258.00:22:16.29#ibcon#enter sib2, iclass 38, count 2 2006.258.00:22:16.29#ibcon#flushed, iclass 38, count 2 2006.258.00:22:16.29#ibcon#about to write, iclass 38, count 2 2006.258.00:22:16.29#ibcon#wrote, iclass 38, count 2 2006.258.00:22:16.29#ibcon#about to read 3, iclass 38, count 2 2006.258.00:22:16.32#ibcon#read 3, iclass 38, count 2 2006.258.00:22:16.32#ibcon#about to read 4, iclass 38, count 2 2006.258.00:22:16.32#ibcon#read 4, iclass 38, count 2 2006.258.00:22:16.32#ibcon#about to read 5, iclass 38, count 2 2006.258.00:22:16.32#ibcon#read 5, iclass 38, count 2 2006.258.00:22:16.32#ibcon#about to read 6, iclass 38, count 2 2006.258.00:22:16.32#ibcon#read 6, iclass 38, count 2 2006.258.00:22:16.32#ibcon#end of sib2, iclass 38, count 2 2006.258.00:22:16.32#ibcon#*after write, iclass 38, count 2 2006.258.00:22:16.32#ibcon#*before return 0, iclass 38, count 2 2006.258.00:22:16.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:16.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:16.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.258.00:22:16.32#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:16.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:16.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:16.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:16.44#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:22:16.44#ibcon#first serial, iclass 38, count 0 2006.258.00:22:16.44#ibcon#enter sib2, iclass 38, count 0 2006.258.00:22:16.44#ibcon#flushed, iclass 38, count 0 2006.258.00:22:16.44#ibcon#about to write, iclass 38, count 0 2006.258.00:22:16.44#ibcon#wrote, iclass 38, count 0 2006.258.00:22:16.44#ibcon#about to read 3, iclass 38, count 0 2006.258.00:22:16.46#ibcon#read 3, iclass 38, count 0 2006.258.00:22:16.46#ibcon#about to read 4, iclass 38, count 0 2006.258.00:22:16.46#ibcon#read 4, iclass 38, count 0 2006.258.00:22:16.46#ibcon#about to read 5, iclass 38, count 0 2006.258.00:22:16.46#ibcon#read 5, iclass 38, count 0 2006.258.00:22:16.46#ibcon#about to read 6, iclass 38, count 0 2006.258.00:22:16.46#ibcon#read 6, iclass 38, count 0 2006.258.00:22:16.46#ibcon#end of sib2, iclass 38, count 0 2006.258.00:22:16.46#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:22:16.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:22:16.46#ibcon#[25=USB\r\n] 2006.258.00:22:16.46#ibcon#*before write, iclass 38, count 0 2006.258.00:22:16.46#ibcon#enter sib2, iclass 38, count 0 2006.258.00:22:16.46#ibcon#flushed, iclass 38, count 0 2006.258.00:22:16.46#ibcon#about to write, iclass 38, count 0 2006.258.00:22:16.46#ibcon#wrote, iclass 38, count 0 2006.258.00:22:16.46#ibcon#about to read 3, iclass 38, count 0 2006.258.00:22:16.49#ibcon#read 3, iclass 38, count 0 2006.258.00:22:16.49#ibcon#about to read 4, iclass 38, count 0 2006.258.00:22:16.49#ibcon#read 4, iclass 38, count 0 2006.258.00:22:16.49#ibcon#about to read 5, iclass 38, count 0 2006.258.00:22:16.49#ibcon#read 5, iclass 38, count 0 2006.258.00:22:16.49#ibcon#about to read 6, iclass 38, count 0 2006.258.00:22:16.49#ibcon#read 6, iclass 38, count 0 2006.258.00:22:16.49#ibcon#end of sib2, iclass 38, count 0 2006.258.00:22:16.49#ibcon#*after write, iclass 38, count 0 2006.258.00:22:16.49#ibcon#*before return 0, iclass 38, count 0 2006.258.00:22:16.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:16.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:16.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:22:16.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:22:16.49$vck44/valo=5,734.99 2006.258.00:22:16.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.00:22:16.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.00:22:16.49#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:16.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:16.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:16.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:16.49#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:22:16.49#ibcon#first serial, iclass 40, count 0 2006.258.00:22:16.49#ibcon#enter sib2, iclass 40, count 0 2006.258.00:22:16.49#ibcon#flushed, iclass 40, count 0 2006.258.00:22:16.49#ibcon#about to write, iclass 40, count 0 2006.258.00:22:16.49#ibcon#wrote, iclass 40, count 0 2006.258.00:22:16.49#ibcon#about to read 3, iclass 40, count 0 2006.258.00:22:16.51#ibcon#read 3, iclass 40, count 0 2006.258.00:22:16.51#ibcon#about to read 4, iclass 40, count 0 2006.258.00:22:16.51#ibcon#read 4, iclass 40, count 0 2006.258.00:22:16.51#ibcon#about to read 5, iclass 40, count 0 2006.258.00:22:16.51#ibcon#read 5, iclass 40, count 0 2006.258.00:22:16.51#ibcon#about to read 6, iclass 40, count 0 2006.258.00:22:16.51#ibcon#read 6, iclass 40, count 0 2006.258.00:22:16.51#ibcon#end of sib2, iclass 40, count 0 2006.258.00:22:16.51#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:22:16.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:22:16.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:22:16.51#ibcon#*before write, iclass 40, count 0 2006.258.00:22:16.51#ibcon#enter sib2, iclass 40, count 0 2006.258.00:22:16.51#ibcon#flushed, iclass 40, count 0 2006.258.00:22:16.51#ibcon#about to write, iclass 40, count 0 2006.258.00:22:16.51#ibcon#wrote, iclass 40, count 0 2006.258.00:22:16.51#ibcon#about to read 3, iclass 40, count 0 2006.258.00:22:16.55#ibcon#read 3, iclass 40, count 0 2006.258.00:22:16.55#ibcon#about to read 4, iclass 40, count 0 2006.258.00:22:16.55#ibcon#read 4, iclass 40, count 0 2006.258.00:22:16.55#ibcon#about to read 5, iclass 40, count 0 2006.258.00:22:16.55#ibcon#read 5, iclass 40, count 0 2006.258.00:22:16.55#ibcon#about to read 6, iclass 40, count 0 2006.258.00:22:16.55#ibcon#read 6, iclass 40, count 0 2006.258.00:22:16.55#ibcon#end of sib2, iclass 40, count 0 2006.258.00:22:16.55#ibcon#*after write, iclass 40, count 0 2006.258.00:22:16.55#ibcon#*before return 0, iclass 40, count 0 2006.258.00:22:16.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:16.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:16.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:22:16.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:22:16.55$vck44/va=5,4 2006.258.00:22:16.55#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.258.00:22:16.55#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.258.00:22:16.55#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:16.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:16.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:16.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:16.61#ibcon#enter wrdev, iclass 4, count 2 2006.258.00:22:16.61#ibcon#first serial, iclass 4, count 2 2006.258.00:22:16.61#ibcon#enter sib2, iclass 4, count 2 2006.258.00:22:16.61#ibcon#flushed, iclass 4, count 2 2006.258.00:22:16.61#ibcon#about to write, iclass 4, count 2 2006.258.00:22:16.61#ibcon#wrote, iclass 4, count 2 2006.258.00:22:16.61#ibcon#about to read 3, iclass 4, count 2 2006.258.00:22:16.63#ibcon#read 3, iclass 4, count 2 2006.258.00:22:16.63#ibcon#about to read 4, iclass 4, count 2 2006.258.00:22:16.63#ibcon#read 4, iclass 4, count 2 2006.258.00:22:16.63#ibcon#about to read 5, iclass 4, count 2 2006.258.00:22:16.63#ibcon#read 5, iclass 4, count 2 2006.258.00:22:16.63#ibcon#about to read 6, iclass 4, count 2 2006.258.00:22:16.63#ibcon#read 6, iclass 4, count 2 2006.258.00:22:16.63#ibcon#end of sib2, iclass 4, count 2 2006.258.00:22:16.63#ibcon#*mode == 0, iclass 4, count 2 2006.258.00:22:16.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.258.00:22:16.63#ibcon#[25=AT05-04\r\n] 2006.258.00:22:16.63#ibcon#*before write, iclass 4, count 2 2006.258.00:22:16.63#ibcon#enter sib2, iclass 4, count 2 2006.258.00:22:16.63#ibcon#flushed, iclass 4, count 2 2006.258.00:22:16.63#ibcon#about to write, iclass 4, count 2 2006.258.00:22:16.63#ibcon#wrote, iclass 4, count 2 2006.258.00:22:16.63#ibcon#about to read 3, iclass 4, count 2 2006.258.00:22:16.66#ibcon#read 3, iclass 4, count 2 2006.258.00:22:16.66#ibcon#about to read 4, iclass 4, count 2 2006.258.00:22:16.66#ibcon#read 4, iclass 4, count 2 2006.258.00:22:16.66#ibcon#about to read 5, iclass 4, count 2 2006.258.00:22:16.66#ibcon#read 5, iclass 4, count 2 2006.258.00:22:16.66#ibcon#about to read 6, iclass 4, count 2 2006.258.00:22:16.66#ibcon#read 6, iclass 4, count 2 2006.258.00:22:16.66#ibcon#end of sib2, iclass 4, count 2 2006.258.00:22:16.66#ibcon#*after write, iclass 4, count 2 2006.258.00:22:16.66#ibcon#*before return 0, iclass 4, count 2 2006.258.00:22:16.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:16.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:16.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.258.00:22:16.66#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:16.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:16.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:16.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:16.78#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:22:16.78#ibcon#first serial, iclass 4, count 0 2006.258.00:22:16.78#ibcon#enter sib2, iclass 4, count 0 2006.258.00:22:16.78#ibcon#flushed, iclass 4, count 0 2006.258.00:22:16.78#ibcon#about to write, iclass 4, count 0 2006.258.00:22:16.78#ibcon#wrote, iclass 4, count 0 2006.258.00:22:16.78#ibcon#about to read 3, iclass 4, count 0 2006.258.00:22:16.80#ibcon#read 3, iclass 4, count 0 2006.258.00:22:16.80#ibcon#about to read 4, iclass 4, count 0 2006.258.00:22:16.80#ibcon#read 4, iclass 4, count 0 2006.258.00:22:16.80#ibcon#about to read 5, iclass 4, count 0 2006.258.00:22:16.80#ibcon#read 5, iclass 4, count 0 2006.258.00:22:16.80#ibcon#about to read 6, iclass 4, count 0 2006.258.00:22:16.80#ibcon#read 6, iclass 4, count 0 2006.258.00:22:16.80#ibcon#end of sib2, iclass 4, count 0 2006.258.00:22:16.80#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:22:16.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:22:16.80#ibcon#[25=USB\r\n] 2006.258.00:22:16.80#ibcon#*before write, iclass 4, count 0 2006.258.00:22:16.80#ibcon#enter sib2, iclass 4, count 0 2006.258.00:22:16.80#ibcon#flushed, iclass 4, count 0 2006.258.00:22:16.80#ibcon#about to write, iclass 4, count 0 2006.258.00:22:16.80#ibcon#wrote, iclass 4, count 0 2006.258.00:22:16.80#ibcon#about to read 3, iclass 4, count 0 2006.258.00:22:16.83#ibcon#read 3, iclass 4, count 0 2006.258.00:22:16.83#ibcon#about to read 4, iclass 4, count 0 2006.258.00:22:16.83#ibcon#read 4, iclass 4, count 0 2006.258.00:22:16.83#ibcon#about to read 5, iclass 4, count 0 2006.258.00:22:16.83#ibcon#read 5, iclass 4, count 0 2006.258.00:22:16.83#ibcon#about to read 6, iclass 4, count 0 2006.258.00:22:16.83#ibcon#read 6, iclass 4, count 0 2006.258.00:22:16.83#ibcon#end of sib2, iclass 4, count 0 2006.258.00:22:16.83#ibcon#*after write, iclass 4, count 0 2006.258.00:22:16.83#ibcon#*before return 0, iclass 4, count 0 2006.258.00:22:16.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:16.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:16.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:22:16.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:22:16.83$vck44/valo=6,814.99 2006.258.00:22:16.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.00:22:16.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.00:22:16.83#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:16.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:16.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:16.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:16.83#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:22:16.83#ibcon#first serial, iclass 6, count 0 2006.258.00:22:16.83#ibcon#enter sib2, iclass 6, count 0 2006.258.00:22:16.83#ibcon#flushed, iclass 6, count 0 2006.258.00:22:16.83#ibcon#about to write, iclass 6, count 0 2006.258.00:22:16.83#ibcon#wrote, iclass 6, count 0 2006.258.00:22:16.83#ibcon#about to read 3, iclass 6, count 0 2006.258.00:22:16.85#ibcon#read 3, iclass 6, count 0 2006.258.00:22:16.85#ibcon#about to read 4, iclass 6, count 0 2006.258.00:22:16.85#ibcon#read 4, iclass 6, count 0 2006.258.00:22:16.85#ibcon#about to read 5, iclass 6, count 0 2006.258.00:22:16.85#ibcon#read 5, iclass 6, count 0 2006.258.00:22:16.85#ibcon#about to read 6, iclass 6, count 0 2006.258.00:22:16.85#ibcon#read 6, iclass 6, count 0 2006.258.00:22:16.85#ibcon#end of sib2, iclass 6, count 0 2006.258.00:22:16.85#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:22:16.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:22:16.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:22:16.85#ibcon#*before write, iclass 6, count 0 2006.258.00:22:16.85#ibcon#enter sib2, iclass 6, count 0 2006.258.00:22:16.85#ibcon#flushed, iclass 6, count 0 2006.258.00:22:16.85#ibcon#about to write, iclass 6, count 0 2006.258.00:22:16.85#ibcon#wrote, iclass 6, count 0 2006.258.00:22:16.85#ibcon#about to read 3, iclass 6, count 0 2006.258.00:22:16.89#ibcon#read 3, iclass 6, count 0 2006.258.00:22:16.89#ibcon#about to read 4, iclass 6, count 0 2006.258.00:22:16.89#ibcon#read 4, iclass 6, count 0 2006.258.00:22:16.89#ibcon#about to read 5, iclass 6, count 0 2006.258.00:22:16.89#ibcon#read 5, iclass 6, count 0 2006.258.00:22:16.89#ibcon#about to read 6, iclass 6, count 0 2006.258.00:22:16.89#ibcon#read 6, iclass 6, count 0 2006.258.00:22:16.89#ibcon#end of sib2, iclass 6, count 0 2006.258.00:22:16.89#ibcon#*after write, iclass 6, count 0 2006.258.00:22:16.89#ibcon#*before return 0, iclass 6, count 0 2006.258.00:22:16.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:16.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:16.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:22:16.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:22:16.89$vck44/va=6,4 2006.258.00:22:16.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.258.00:22:16.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.258.00:22:16.89#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:16.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:16.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:16.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:16.95#ibcon#enter wrdev, iclass 10, count 2 2006.258.00:22:16.95#ibcon#first serial, iclass 10, count 2 2006.258.00:22:16.95#ibcon#enter sib2, iclass 10, count 2 2006.258.00:22:16.95#ibcon#flushed, iclass 10, count 2 2006.258.00:22:16.95#ibcon#about to write, iclass 10, count 2 2006.258.00:22:16.95#ibcon#wrote, iclass 10, count 2 2006.258.00:22:16.95#ibcon#about to read 3, iclass 10, count 2 2006.258.00:22:16.97#ibcon#read 3, iclass 10, count 2 2006.258.00:22:16.97#ibcon#about to read 4, iclass 10, count 2 2006.258.00:22:16.97#ibcon#read 4, iclass 10, count 2 2006.258.00:22:16.97#ibcon#about to read 5, iclass 10, count 2 2006.258.00:22:16.97#ibcon#read 5, iclass 10, count 2 2006.258.00:22:16.97#ibcon#about to read 6, iclass 10, count 2 2006.258.00:22:16.97#ibcon#read 6, iclass 10, count 2 2006.258.00:22:16.97#ibcon#end of sib2, iclass 10, count 2 2006.258.00:22:16.97#ibcon#*mode == 0, iclass 10, count 2 2006.258.00:22:16.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.258.00:22:16.97#ibcon#[25=AT06-04\r\n] 2006.258.00:22:16.97#ibcon#*before write, iclass 10, count 2 2006.258.00:22:16.97#ibcon#enter sib2, iclass 10, count 2 2006.258.00:22:16.97#ibcon#flushed, iclass 10, count 2 2006.258.00:22:16.97#ibcon#about to write, iclass 10, count 2 2006.258.00:22:16.97#ibcon#wrote, iclass 10, count 2 2006.258.00:22:16.97#ibcon#about to read 3, iclass 10, count 2 2006.258.00:22:17.00#ibcon#read 3, iclass 10, count 2 2006.258.00:22:17.00#ibcon#about to read 4, iclass 10, count 2 2006.258.00:22:17.00#ibcon#read 4, iclass 10, count 2 2006.258.00:22:17.00#ibcon#about to read 5, iclass 10, count 2 2006.258.00:22:17.00#ibcon#read 5, iclass 10, count 2 2006.258.00:22:17.00#ibcon#about to read 6, iclass 10, count 2 2006.258.00:22:17.00#ibcon#read 6, iclass 10, count 2 2006.258.00:22:17.00#ibcon#end of sib2, iclass 10, count 2 2006.258.00:22:17.00#ibcon#*after write, iclass 10, count 2 2006.258.00:22:17.00#ibcon#*before return 0, iclass 10, count 2 2006.258.00:22:17.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:17.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:17.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.258.00:22:17.00#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:17.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:17.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:17.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:17.12#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:22:17.12#ibcon#first serial, iclass 10, count 0 2006.258.00:22:17.12#ibcon#enter sib2, iclass 10, count 0 2006.258.00:22:17.12#ibcon#flushed, iclass 10, count 0 2006.258.00:22:17.12#ibcon#about to write, iclass 10, count 0 2006.258.00:22:17.12#ibcon#wrote, iclass 10, count 0 2006.258.00:22:17.12#ibcon#about to read 3, iclass 10, count 0 2006.258.00:22:17.14#ibcon#read 3, iclass 10, count 0 2006.258.00:22:17.14#ibcon#about to read 4, iclass 10, count 0 2006.258.00:22:17.14#ibcon#read 4, iclass 10, count 0 2006.258.00:22:17.14#ibcon#about to read 5, iclass 10, count 0 2006.258.00:22:17.14#ibcon#read 5, iclass 10, count 0 2006.258.00:22:17.14#ibcon#about to read 6, iclass 10, count 0 2006.258.00:22:17.14#ibcon#read 6, iclass 10, count 0 2006.258.00:22:17.14#ibcon#end of sib2, iclass 10, count 0 2006.258.00:22:17.14#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:22:17.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:22:17.14#ibcon#[25=USB\r\n] 2006.258.00:22:17.14#ibcon#*before write, iclass 10, count 0 2006.258.00:22:17.14#ibcon#enter sib2, iclass 10, count 0 2006.258.00:22:17.14#ibcon#flushed, iclass 10, count 0 2006.258.00:22:17.14#ibcon#about to write, iclass 10, count 0 2006.258.00:22:17.14#ibcon#wrote, iclass 10, count 0 2006.258.00:22:17.14#ibcon#about to read 3, iclass 10, count 0 2006.258.00:22:17.17#ibcon#read 3, iclass 10, count 0 2006.258.00:22:17.17#ibcon#about to read 4, iclass 10, count 0 2006.258.00:22:17.17#ibcon#read 4, iclass 10, count 0 2006.258.00:22:17.17#ibcon#about to read 5, iclass 10, count 0 2006.258.00:22:17.17#ibcon#read 5, iclass 10, count 0 2006.258.00:22:17.17#ibcon#about to read 6, iclass 10, count 0 2006.258.00:22:17.17#ibcon#read 6, iclass 10, count 0 2006.258.00:22:17.17#ibcon#end of sib2, iclass 10, count 0 2006.258.00:22:17.17#ibcon#*after write, iclass 10, count 0 2006.258.00:22:17.17#ibcon#*before return 0, iclass 10, count 0 2006.258.00:22:17.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:17.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:17.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:22:17.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:22:17.17$vck44/valo=7,864.99 2006.258.00:22:17.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.00:22:17.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.00:22:17.17#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:17.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:17.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:17.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:17.17#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:22:17.17#ibcon#first serial, iclass 12, count 0 2006.258.00:22:17.17#ibcon#enter sib2, iclass 12, count 0 2006.258.00:22:17.17#ibcon#flushed, iclass 12, count 0 2006.258.00:22:17.17#ibcon#about to write, iclass 12, count 0 2006.258.00:22:17.17#ibcon#wrote, iclass 12, count 0 2006.258.00:22:17.17#ibcon#about to read 3, iclass 12, count 0 2006.258.00:22:17.19#ibcon#read 3, iclass 12, count 0 2006.258.00:22:17.19#ibcon#about to read 4, iclass 12, count 0 2006.258.00:22:17.19#ibcon#read 4, iclass 12, count 0 2006.258.00:22:17.19#ibcon#about to read 5, iclass 12, count 0 2006.258.00:22:17.19#ibcon#read 5, iclass 12, count 0 2006.258.00:22:17.19#ibcon#about to read 6, iclass 12, count 0 2006.258.00:22:17.19#ibcon#read 6, iclass 12, count 0 2006.258.00:22:17.19#ibcon#end of sib2, iclass 12, count 0 2006.258.00:22:17.19#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:22:17.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:22:17.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:22:17.19#ibcon#*before write, iclass 12, count 0 2006.258.00:22:17.19#ibcon#enter sib2, iclass 12, count 0 2006.258.00:22:17.19#ibcon#flushed, iclass 12, count 0 2006.258.00:22:17.19#ibcon#about to write, iclass 12, count 0 2006.258.00:22:17.19#ibcon#wrote, iclass 12, count 0 2006.258.00:22:17.19#ibcon#about to read 3, iclass 12, count 0 2006.258.00:22:17.23#ibcon#read 3, iclass 12, count 0 2006.258.00:22:17.23#ibcon#about to read 4, iclass 12, count 0 2006.258.00:22:17.23#ibcon#read 4, iclass 12, count 0 2006.258.00:22:17.23#ibcon#about to read 5, iclass 12, count 0 2006.258.00:22:17.23#ibcon#read 5, iclass 12, count 0 2006.258.00:22:17.23#ibcon#about to read 6, iclass 12, count 0 2006.258.00:22:17.23#ibcon#read 6, iclass 12, count 0 2006.258.00:22:17.23#ibcon#end of sib2, iclass 12, count 0 2006.258.00:22:17.23#ibcon#*after write, iclass 12, count 0 2006.258.00:22:17.23#ibcon#*before return 0, iclass 12, count 0 2006.258.00:22:17.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:17.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:17.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:22:17.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:22:17.23$vck44/va=7,4 2006.258.00:22:17.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.258.00:22:17.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.258.00:22:17.23#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:17.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:17.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:17.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:17.29#ibcon#enter wrdev, iclass 14, count 2 2006.258.00:22:17.29#ibcon#first serial, iclass 14, count 2 2006.258.00:22:17.29#ibcon#enter sib2, iclass 14, count 2 2006.258.00:22:17.29#ibcon#flushed, iclass 14, count 2 2006.258.00:22:17.29#ibcon#about to write, iclass 14, count 2 2006.258.00:22:17.29#ibcon#wrote, iclass 14, count 2 2006.258.00:22:17.29#ibcon#about to read 3, iclass 14, count 2 2006.258.00:22:17.31#ibcon#read 3, iclass 14, count 2 2006.258.00:22:17.31#ibcon#about to read 4, iclass 14, count 2 2006.258.00:22:17.31#ibcon#read 4, iclass 14, count 2 2006.258.00:22:17.31#ibcon#about to read 5, iclass 14, count 2 2006.258.00:22:17.31#ibcon#read 5, iclass 14, count 2 2006.258.00:22:17.31#ibcon#about to read 6, iclass 14, count 2 2006.258.00:22:17.31#ibcon#read 6, iclass 14, count 2 2006.258.00:22:17.31#ibcon#end of sib2, iclass 14, count 2 2006.258.00:22:17.31#ibcon#*mode == 0, iclass 14, count 2 2006.258.00:22:17.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.258.00:22:17.31#ibcon#[25=AT07-04\r\n] 2006.258.00:22:17.31#ibcon#*before write, iclass 14, count 2 2006.258.00:22:17.31#ibcon#enter sib2, iclass 14, count 2 2006.258.00:22:17.31#ibcon#flushed, iclass 14, count 2 2006.258.00:22:17.31#ibcon#about to write, iclass 14, count 2 2006.258.00:22:17.31#ibcon#wrote, iclass 14, count 2 2006.258.00:22:17.31#ibcon#about to read 3, iclass 14, count 2 2006.258.00:22:17.34#ibcon#read 3, iclass 14, count 2 2006.258.00:22:17.34#ibcon#about to read 4, iclass 14, count 2 2006.258.00:22:17.34#ibcon#read 4, iclass 14, count 2 2006.258.00:22:17.34#ibcon#about to read 5, iclass 14, count 2 2006.258.00:22:17.34#ibcon#read 5, iclass 14, count 2 2006.258.00:22:17.34#ibcon#about to read 6, iclass 14, count 2 2006.258.00:22:17.34#ibcon#read 6, iclass 14, count 2 2006.258.00:22:17.34#ibcon#end of sib2, iclass 14, count 2 2006.258.00:22:17.34#ibcon#*after write, iclass 14, count 2 2006.258.00:22:17.34#ibcon#*before return 0, iclass 14, count 2 2006.258.00:22:17.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:17.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:17.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.258.00:22:17.34#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:17.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:17.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:17.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:17.46#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:22:17.46#ibcon#first serial, iclass 14, count 0 2006.258.00:22:17.46#ibcon#enter sib2, iclass 14, count 0 2006.258.00:22:17.46#ibcon#flushed, iclass 14, count 0 2006.258.00:22:17.46#ibcon#about to write, iclass 14, count 0 2006.258.00:22:17.46#ibcon#wrote, iclass 14, count 0 2006.258.00:22:17.46#ibcon#about to read 3, iclass 14, count 0 2006.258.00:22:17.48#ibcon#read 3, iclass 14, count 0 2006.258.00:22:17.48#ibcon#about to read 4, iclass 14, count 0 2006.258.00:22:17.48#ibcon#read 4, iclass 14, count 0 2006.258.00:22:17.48#ibcon#about to read 5, iclass 14, count 0 2006.258.00:22:17.48#ibcon#read 5, iclass 14, count 0 2006.258.00:22:17.48#ibcon#about to read 6, iclass 14, count 0 2006.258.00:22:17.48#ibcon#read 6, iclass 14, count 0 2006.258.00:22:17.48#ibcon#end of sib2, iclass 14, count 0 2006.258.00:22:17.48#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:22:17.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:22:17.48#ibcon#[25=USB\r\n] 2006.258.00:22:17.48#ibcon#*before write, iclass 14, count 0 2006.258.00:22:17.48#ibcon#enter sib2, iclass 14, count 0 2006.258.00:22:17.48#ibcon#flushed, iclass 14, count 0 2006.258.00:22:17.48#ibcon#about to write, iclass 14, count 0 2006.258.00:22:17.48#ibcon#wrote, iclass 14, count 0 2006.258.00:22:17.48#ibcon#about to read 3, iclass 14, count 0 2006.258.00:22:17.51#ibcon#read 3, iclass 14, count 0 2006.258.00:22:17.51#ibcon#about to read 4, iclass 14, count 0 2006.258.00:22:17.51#ibcon#read 4, iclass 14, count 0 2006.258.00:22:17.51#ibcon#about to read 5, iclass 14, count 0 2006.258.00:22:17.51#ibcon#read 5, iclass 14, count 0 2006.258.00:22:17.51#ibcon#about to read 6, iclass 14, count 0 2006.258.00:22:17.51#ibcon#read 6, iclass 14, count 0 2006.258.00:22:17.51#ibcon#end of sib2, iclass 14, count 0 2006.258.00:22:17.51#ibcon#*after write, iclass 14, count 0 2006.258.00:22:17.51#ibcon#*before return 0, iclass 14, count 0 2006.258.00:22:17.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:17.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:17.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:22:17.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:22:17.51$vck44/valo=8,884.99 2006.258.00:22:17.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.00:22:17.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.00:22:17.51#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:17.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:17.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:17.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:17.51#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:22:17.51#ibcon#first serial, iclass 16, count 0 2006.258.00:22:17.51#ibcon#enter sib2, iclass 16, count 0 2006.258.00:22:17.51#ibcon#flushed, iclass 16, count 0 2006.258.00:22:17.51#ibcon#about to write, iclass 16, count 0 2006.258.00:22:17.51#ibcon#wrote, iclass 16, count 0 2006.258.00:22:17.51#ibcon#about to read 3, iclass 16, count 0 2006.258.00:22:17.53#ibcon#read 3, iclass 16, count 0 2006.258.00:22:17.53#ibcon#about to read 4, iclass 16, count 0 2006.258.00:22:17.53#ibcon#read 4, iclass 16, count 0 2006.258.00:22:17.53#ibcon#about to read 5, iclass 16, count 0 2006.258.00:22:17.53#ibcon#read 5, iclass 16, count 0 2006.258.00:22:17.53#ibcon#about to read 6, iclass 16, count 0 2006.258.00:22:17.53#ibcon#read 6, iclass 16, count 0 2006.258.00:22:17.53#ibcon#end of sib2, iclass 16, count 0 2006.258.00:22:17.53#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:22:17.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:22:17.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:22:17.53#ibcon#*before write, iclass 16, count 0 2006.258.00:22:17.53#ibcon#enter sib2, iclass 16, count 0 2006.258.00:22:17.53#ibcon#flushed, iclass 16, count 0 2006.258.00:22:17.53#ibcon#about to write, iclass 16, count 0 2006.258.00:22:17.53#ibcon#wrote, iclass 16, count 0 2006.258.00:22:17.53#ibcon#about to read 3, iclass 16, count 0 2006.258.00:22:17.57#ibcon#read 3, iclass 16, count 0 2006.258.00:22:17.57#ibcon#about to read 4, iclass 16, count 0 2006.258.00:22:17.57#ibcon#read 4, iclass 16, count 0 2006.258.00:22:17.57#ibcon#about to read 5, iclass 16, count 0 2006.258.00:22:17.57#ibcon#read 5, iclass 16, count 0 2006.258.00:22:17.57#ibcon#about to read 6, iclass 16, count 0 2006.258.00:22:17.57#ibcon#read 6, iclass 16, count 0 2006.258.00:22:17.57#ibcon#end of sib2, iclass 16, count 0 2006.258.00:22:17.57#ibcon#*after write, iclass 16, count 0 2006.258.00:22:17.57#ibcon#*before return 0, iclass 16, count 0 2006.258.00:22:17.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:17.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:17.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:22:17.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:22:17.57$vck44/va=8,4 2006.258.00:22:17.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.258.00:22:17.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.258.00:22:17.57#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:17.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:22:17.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:22:17.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:22:17.63#ibcon#enter wrdev, iclass 18, count 2 2006.258.00:22:17.63#ibcon#first serial, iclass 18, count 2 2006.258.00:22:17.63#ibcon#enter sib2, iclass 18, count 2 2006.258.00:22:17.63#ibcon#flushed, iclass 18, count 2 2006.258.00:22:17.63#ibcon#about to write, iclass 18, count 2 2006.258.00:22:17.63#ibcon#wrote, iclass 18, count 2 2006.258.00:22:17.63#ibcon#about to read 3, iclass 18, count 2 2006.258.00:22:17.65#ibcon#read 3, iclass 18, count 2 2006.258.00:22:17.65#ibcon#about to read 4, iclass 18, count 2 2006.258.00:22:17.65#ibcon#read 4, iclass 18, count 2 2006.258.00:22:17.65#ibcon#about to read 5, iclass 18, count 2 2006.258.00:22:17.65#ibcon#read 5, iclass 18, count 2 2006.258.00:22:17.65#ibcon#about to read 6, iclass 18, count 2 2006.258.00:22:17.65#ibcon#read 6, iclass 18, count 2 2006.258.00:22:17.65#ibcon#end of sib2, iclass 18, count 2 2006.258.00:22:17.65#ibcon#*mode == 0, iclass 18, count 2 2006.258.00:22:17.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.258.00:22:17.65#ibcon#[25=AT08-04\r\n] 2006.258.00:22:17.65#ibcon#*before write, iclass 18, count 2 2006.258.00:22:17.65#ibcon#enter sib2, iclass 18, count 2 2006.258.00:22:17.65#ibcon#flushed, iclass 18, count 2 2006.258.00:22:17.65#ibcon#about to write, iclass 18, count 2 2006.258.00:22:17.65#ibcon#wrote, iclass 18, count 2 2006.258.00:22:17.65#ibcon#about to read 3, iclass 18, count 2 2006.258.00:22:17.68#ibcon#read 3, iclass 18, count 2 2006.258.00:22:17.68#ibcon#about to read 4, iclass 18, count 2 2006.258.00:22:17.68#ibcon#read 4, iclass 18, count 2 2006.258.00:22:17.68#ibcon#about to read 5, iclass 18, count 2 2006.258.00:22:17.68#ibcon#read 5, iclass 18, count 2 2006.258.00:22:17.68#ibcon#about to read 6, iclass 18, count 2 2006.258.00:22:17.68#ibcon#read 6, iclass 18, count 2 2006.258.00:22:17.68#ibcon#end of sib2, iclass 18, count 2 2006.258.00:22:17.68#ibcon#*after write, iclass 18, count 2 2006.258.00:22:17.68#ibcon#*before return 0, iclass 18, count 2 2006.258.00:22:17.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:22:17.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:22:17.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.258.00:22:17.68#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:17.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:22:17.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:22:17.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:22:17.80#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:22:17.80#ibcon#first serial, iclass 18, count 0 2006.258.00:22:17.80#ibcon#enter sib2, iclass 18, count 0 2006.258.00:22:17.80#ibcon#flushed, iclass 18, count 0 2006.258.00:22:17.80#ibcon#about to write, iclass 18, count 0 2006.258.00:22:17.80#ibcon#wrote, iclass 18, count 0 2006.258.00:22:17.80#ibcon#about to read 3, iclass 18, count 0 2006.258.00:22:17.82#ibcon#read 3, iclass 18, count 0 2006.258.00:22:17.82#ibcon#about to read 4, iclass 18, count 0 2006.258.00:22:17.82#ibcon#read 4, iclass 18, count 0 2006.258.00:22:17.82#ibcon#about to read 5, iclass 18, count 0 2006.258.00:22:17.82#ibcon#read 5, iclass 18, count 0 2006.258.00:22:17.82#ibcon#about to read 6, iclass 18, count 0 2006.258.00:22:17.82#ibcon#read 6, iclass 18, count 0 2006.258.00:22:17.82#ibcon#end of sib2, iclass 18, count 0 2006.258.00:22:17.82#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:22:17.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:22:17.82#ibcon#[25=USB\r\n] 2006.258.00:22:17.82#ibcon#*before write, iclass 18, count 0 2006.258.00:22:17.82#ibcon#enter sib2, iclass 18, count 0 2006.258.00:22:17.82#ibcon#flushed, iclass 18, count 0 2006.258.00:22:17.82#ibcon#about to write, iclass 18, count 0 2006.258.00:22:17.82#ibcon#wrote, iclass 18, count 0 2006.258.00:22:17.82#ibcon#about to read 3, iclass 18, count 0 2006.258.00:22:17.85#ibcon#read 3, iclass 18, count 0 2006.258.00:22:17.85#ibcon#about to read 4, iclass 18, count 0 2006.258.00:22:17.85#ibcon#read 4, iclass 18, count 0 2006.258.00:22:17.85#ibcon#about to read 5, iclass 18, count 0 2006.258.00:22:17.85#ibcon#read 5, iclass 18, count 0 2006.258.00:22:17.85#ibcon#about to read 6, iclass 18, count 0 2006.258.00:22:17.85#ibcon#read 6, iclass 18, count 0 2006.258.00:22:17.85#ibcon#end of sib2, iclass 18, count 0 2006.258.00:22:17.85#ibcon#*after write, iclass 18, count 0 2006.258.00:22:17.85#ibcon#*before return 0, iclass 18, count 0 2006.258.00:22:17.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:22:17.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:22:17.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:22:17.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:22:17.85$vck44/vblo=1,629.99 2006.258.00:22:17.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.00:22:17.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.00:22:17.85#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:17.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:22:17.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:22:17.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:22:17.85#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:22:17.85#ibcon#first serial, iclass 20, count 0 2006.258.00:22:17.85#ibcon#enter sib2, iclass 20, count 0 2006.258.00:22:17.85#ibcon#flushed, iclass 20, count 0 2006.258.00:22:17.85#ibcon#about to write, iclass 20, count 0 2006.258.00:22:17.85#ibcon#wrote, iclass 20, count 0 2006.258.00:22:17.85#ibcon#about to read 3, iclass 20, count 0 2006.258.00:22:17.87#ibcon#read 3, iclass 20, count 0 2006.258.00:22:17.87#ibcon#about to read 4, iclass 20, count 0 2006.258.00:22:17.87#ibcon#read 4, iclass 20, count 0 2006.258.00:22:17.87#ibcon#about to read 5, iclass 20, count 0 2006.258.00:22:17.87#ibcon#read 5, iclass 20, count 0 2006.258.00:22:17.87#ibcon#about to read 6, iclass 20, count 0 2006.258.00:22:17.87#ibcon#read 6, iclass 20, count 0 2006.258.00:22:17.87#ibcon#end of sib2, iclass 20, count 0 2006.258.00:22:17.87#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:22:17.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:22:17.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:22:17.87#ibcon#*before write, iclass 20, count 0 2006.258.00:22:17.87#ibcon#enter sib2, iclass 20, count 0 2006.258.00:22:17.87#ibcon#flushed, iclass 20, count 0 2006.258.00:22:17.87#ibcon#about to write, iclass 20, count 0 2006.258.00:22:17.87#ibcon#wrote, iclass 20, count 0 2006.258.00:22:17.87#ibcon#about to read 3, iclass 20, count 0 2006.258.00:22:17.91#ibcon#read 3, iclass 20, count 0 2006.258.00:22:17.91#ibcon#about to read 4, iclass 20, count 0 2006.258.00:22:17.91#ibcon#read 4, iclass 20, count 0 2006.258.00:22:17.91#ibcon#about to read 5, iclass 20, count 0 2006.258.00:22:17.91#ibcon#read 5, iclass 20, count 0 2006.258.00:22:17.91#ibcon#about to read 6, iclass 20, count 0 2006.258.00:22:17.91#ibcon#read 6, iclass 20, count 0 2006.258.00:22:17.91#ibcon#end of sib2, iclass 20, count 0 2006.258.00:22:17.91#ibcon#*after write, iclass 20, count 0 2006.258.00:22:17.91#ibcon#*before return 0, iclass 20, count 0 2006.258.00:22:17.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:22:17.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:22:17.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:22:17.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:22:17.91$vck44/vb=1,4 2006.258.00:22:17.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.00:22:17.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.00:22:17.91#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:17.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:22:17.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:22:17.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:22:17.91#ibcon#enter wrdev, iclass 22, count 2 2006.258.00:22:17.91#ibcon#first serial, iclass 22, count 2 2006.258.00:22:17.91#ibcon#enter sib2, iclass 22, count 2 2006.258.00:22:17.91#ibcon#flushed, iclass 22, count 2 2006.258.00:22:17.91#ibcon#about to write, iclass 22, count 2 2006.258.00:22:17.91#ibcon#wrote, iclass 22, count 2 2006.258.00:22:17.91#ibcon#about to read 3, iclass 22, count 2 2006.258.00:22:17.93#ibcon#read 3, iclass 22, count 2 2006.258.00:22:17.93#ibcon#about to read 4, iclass 22, count 2 2006.258.00:22:17.93#ibcon#read 4, iclass 22, count 2 2006.258.00:22:17.93#ibcon#about to read 5, iclass 22, count 2 2006.258.00:22:17.93#ibcon#read 5, iclass 22, count 2 2006.258.00:22:17.93#ibcon#about to read 6, iclass 22, count 2 2006.258.00:22:17.93#ibcon#read 6, iclass 22, count 2 2006.258.00:22:17.93#ibcon#end of sib2, iclass 22, count 2 2006.258.00:22:17.93#ibcon#*mode == 0, iclass 22, count 2 2006.258.00:22:17.93#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.00:22:17.93#ibcon#[27=AT01-04\r\n] 2006.258.00:22:17.93#ibcon#*before write, iclass 22, count 2 2006.258.00:22:17.93#ibcon#enter sib2, iclass 22, count 2 2006.258.00:22:17.93#ibcon#flushed, iclass 22, count 2 2006.258.00:22:17.93#ibcon#about to write, iclass 22, count 2 2006.258.00:22:17.93#ibcon#wrote, iclass 22, count 2 2006.258.00:22:17.93#ibcon#about to read 3, iclass 22, count 2 2006.258.00:22:17.96#ibcon#read 3, iclass 22, count 2 2006.258.00:22:17.96#ibcon#about to read 4, iclass 22, count 2 2006.258.00:22:17.96#ibcon#read 4, iclass 22, count 2 2006.258.00:22:17.96#ibcon#about to read 5, iclass 22, count 2 2006.258.00:22:17.96#ibcon#read 5, iclass 22, count 2 2006.258.00:22:17.96#ibcon#about to read 6, iclass 22, count 2 2006.258.00:22:17.96#ibcon#read 6, iclass 22, count 2 2006.258.00:22:17.96#ibcon#end of sib2, iclass 22, count 2 2006.258.00:22:17.96#ibcon#*after write, iclass 22, count 2 2006.258.00:22:17.96#ibcon#*before return 0, iclass 22, count 2 2006.258.00:22:17.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:22:17.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:22:17.96#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.00:22:17.96#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:17.96#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:22:18.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:22:18.08#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:22:18.08#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:22:18.08#ibcon#first serial, iclass 22, count 0 2006.258.00:22:18.08#ibcon#enter sib2, iclass 22, count 0 2006.258.00:22:18.08#ibcon#flushed, iclass 22, count 0 2006.258.00:22:18.08#ibcon#about to write, iclass 22, count 0 2006.258.00:22:18.08#ibcon#wrote, iclass 22, count 0 2006.258.00:22:18.08#ibcon#about to read 3, iclass 22, count 0 2006.258.00:22:18.10#ibcon#read 3, iclass 22, count 0 2006.258.00:22:18.10#ibcon#about to read 4, iclass 22, count 0 2006.258.00:22:18.10#ibcon#read 4, iclass 22, count 0 2006.258.00:22:18.10#ibcon#about to read 5, iclass 22, count 0 2006.258.00:22:18.10#ibcon#read 5, iclass 22, count 0 2006.258.00:22:18.10#ibcon#about to read 6, iclass 22, count 0 2006.258.00:22:18.10#ibcon#read 6, iclass 22, count 0 2006.258.00:22:18.10#ibcon#end of sib2, iclass 22, count 0 2006.258.00:22:18.10#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:22:18.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:22:18.10#ibcon#[27=USB\r\n] 2006.258.00:22:18.10#ibcon#*before write, iclass 22, count 0 2006.258.00:22:18.10#ibcon#enter sib2, iclass 22, count 0 2006.258.00:22:18.10#ibcon#flushed, iclass 22, count 0 2006.258.00:22:18.10#ibcon#about to write, iclass 22, count 0 2006.258.00:22:18.10#ibcon#wrote, iclass 22, count 0 2006.258.00:22:18.10#ibcon#about to read 3, iclass 22, count 0 2006.258.00:22:18.13#ibcon#read 3, iclass 22, count 0 2006.258.00:22:18.13#ibcon#about to read 4, iclass 22, count 0 2006.258.00:22:18.13#ibcon#read 4, iclass 22, count 0 2006.258.00:22:18.13#ibcon#about to read 5, iclass 22, count 0 2006.258.00:22:18.13#ibcon#read 5, iclass 22, count 0 2006.258.00:22:18.13#ibcon#about to read 6, iclass 22, count 0 2006.258.00:22:18.13#ibcon#read 6, iclass 22, count 0 2006.258.00:22:18.13#ibcon#end of sib2, iclass 22, count 0 2006.258.00:22:18.13#ibcon#*after write, iclass 22, count 0 2006.258.00:22:18.13#ibcon#*before return 0, iclass 22, count 0 2006.258.00:22:18.13#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:22:18.13#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:22:18.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:22:18.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:22:18.13$vck44/vblo=2,634.99 2006.258.00:22:18.13#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.00:22:18.13#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.00:22:18.13#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:18.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:18.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:18.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:18.13#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:22:18.13#ibcon#first serial, iclass 24, count 0 2006.258.00:22:18.13#ibcon#enter sib2, iclass 24, count 0 2006.258.00:22:18.13#ibcon#flushed, iclass 24, count 0 2006.258.00:22:18.13#ibcon#about to write, iclass 24, count 0 2006.258.00:22:18.13#ibcon#wrote, iclass 24, count 0 2006.258.00:22:18.13#ibcon#about to read 3, iclass 24, count 0 2006.258.00:22:18.15#ibcon#read 3, iclass 24, count 0 2006.258.00:22:18.15#ibcon#about to read 4, iclass 24, count 0 2006.258.00:22:18.15#ibcon#read 4, iclass 24, count 0 2006.258.00:22:18.15#ibcon#about to read 5, iclass 24, count 0 2006.258.00:22:18.15#ibcon#read 5, iclass 24, count 0 2006.258.00:22:18.15#ibcon#about to read 6, iclass 24, count 0 2006.258.00:22:18.15#ibcon#read 6, iclass 24, count 0 2006.258.00:22:18.15#ibcon#end of sib2, iclass 24, count 0 2006.258.00:22:18.15#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:22:18.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:22:18.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:22:18.15#ibcon#*before write, iclass 24, count 0 2006.258.00:22:18.15#ibcon#enter sib2, iclass 24, count 0 2006.258.00:22:18.15#ibcon#flushed, iclass 24, count 0 2006.258.00:22:18.15#ibcon#about to write, iclass 24, count 0 2006.258.00:22:18.15#ibcon#wrote, iclass 24, count 0 2006.258.00:22:18.15#ibcon#about to read 3, iclass 24, count 0 2006.258.00:22:18.19#ibcon#read 3, iclass 24, count 0 2006.258.00:22:18.19#ibcon#about to read 4, iclass 24, count 0 2006.258.00:22:18.19#ibcon#read 4, iclass 24, count 0 2006.258.00:22:18.19#ibcon#about to read 5, iclass 24, count 0 2006.258.00:22:18.19#ibcon#read 5, iclass 24, count 0 2006.258.00:22:18.19#ibcon#about to read 6, iclass 24, count 0 2006.258.00:22:18.19#ibcon#read 6, iclass 24, count 0 2006.258.00:22:18.19#ibcon#end of sib2, iclass 24, count 0 2006.258.00:22:18.19#ibcon#*after write, iclass 24, count 0 2006.258.00:22:18.19#ibcon#*before return 0, iclass 24, count 0 2006.258.00:22:18.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:18.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:22:18.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:22:18.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:22:18.19$vck44/vb=2,5 2006.258.00:22:18.19#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.00:22:18.19#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.00:22:18.19#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:18.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:18.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:18.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:18.25#ibcon#enter wrdev, iclass 26, count 2 2006.258.00:22:18.25#ibcon#first serial, iclass 26, count 2 2006.258.00:22:18.25#ibcon#enter sib2, iclass 26, count 2 2006.258.00:22:18.25#ibcon#flushed, iclass 26, count 2 2006.258.00:22:18.25#ibcon#about to write, iclass 26, count 2 2006.258.00:22:18.25#ibcon#wrote, iclass 26, count 2 2006.258.00:22:18.25#ibcon#about to read 3, iclass 26, count 2 2006.258.00:22:18.27#ibcon#read 3, iclass 26, count 2 2006.258.00:22:18.27#ibcon#about to read 4, iclass 26, count 2 2006.258.00:22:18.27#ibcon#read 4, iclass 26, count 2 2006.258.00:22:18.27#ibcon#about to read 5, iclass 26, count 2 2006.258.00:22:18.27#ibcon#read 5, iclass 26, count 2 2006.258.00:22:18.27#ibcon#about to read 6, iclass 26, count 2 2006.258.00:22:18.27#ibcon#read 6, iclass 26, count 2 2006.258.00:22:18.27#ibcon#end of sib2, iclass 26, count 2 2006.258.00:22:18.27#ibcon#*mode == 0, iclass 26, count 2 2006.258.00:22:18.27#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.00:22:18.27#ibcon#[27=AT02-05\r\n] 2006.258.00:22:18.27#ibcon#*before write, iclass 26, count 2 2006.258.00:22:18.27#ibcon#enter sib2, iclass 26, count 2 2006.258.00:22:18.27#ibcon#flushed, iclass 26, count 2 2006.258.00:22:18.27#ibcon#about to write, iclass 26, count 2 2006.258.00:22:18.27#ibcon#wrote, iclass 26, count 2 2006.258.00:22:18.27#ibcon#about to read 3, iclass 26, count 2 2006.258.00:22:18.30#ibcon#read 3, iclass 26, count 2 2006.258.00:22:18.30#ibcon#about to read 4, iclass 26, count 2 2006.258.00:22:18.30#ibcon#read 4, iclass 26, count 2 2006.258.00:22:18.30#ibcon#about to read 5, iclass 26, count 2 2006.258.00:22:18.30#ibcon#read 5, iclass 26, count 2 2006.258.00:22:18.30#ibcon#about to read 6, iclass 26, count 2 2006.258.00:22:18.30#ibcon#read 6, iclass 26, count 2 2006.258.00:22:18.30#ibcon#end of sib2, iclass 26, count 2 2006.258.00:22:18.30#ibcon#*after write, iclass 26, count 2 2006.258.00:22:18.30#ibcon#*before return 0, iclass 26, count 2 2006.258.00:22:18.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:18.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:22:18.30#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.00:22:18.30#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:18.30#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:18.42#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:18.42#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:18.42#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:22:18.42#ibcon#first serial, iclass 26, count 0 2006.258.00:22:18.42#ibcon#enter sib2, iclass 26, count 0 2006.258.00:22:18.42#ibcon#flushed, iclass 26, count 0 2006.258.00:22:18.42#ibcon#about to write, iclass 26, count 0 2006.258.00:22:18.42#ibcon#wrote, iclass 26, count 0 2006.258.00:22:18.42#ibcon#about to read 3, iclass 26, count 0 2006.258.00:22:18.44#ibcon#read 3, iclass 26, count 0 2006.258.00:22:18.44#ibcon#about to read 4, iclass 26, count 0 2006.258.00:22:18.44#ibcon#read 4, iclass 26, count 0 2006.258.00:22:18.44#ibcon#about to read 5, iclass 26, count 0 2006.258.00:22:18.44#ibcon#read 5, iclass 26, count 0 2006.258.00:22:18.44#ibcon#about to read 6, iclass 26, count 0 2006.258.00:22:18.44#ibcon#read 6, iclass 26, count 0 2006.258.00:22:18.44#ibcon#end of sib2, iclass 26, count 0 2006.258.00:22:18.44#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:22:18.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:22:18.44#ibcon#[27=USB\r\n] 2006.258.00:22:18.44#ibcon#*before write, iclass 26, count 0 2006.258.00:22:18.44#ibcon#enter sib2, iclass 26, count 0 2006.258.00:22:18.44#ibcon#flushed, iclass 26, count 0 2006.258.00:22:18.44#ibcon#about to write, iclass 26, count 0 2006.258.00:22:18.44#ibcon#wrote, iclass 26, count 0 2006.258.00:22:18.44#ibcon#about to read 3, iclass 26, count 0 2006.258.00:22:18.47#ibcon#read 3, iclass 26, count 0 2006.258.00:22:18.47#ibcon#about to read 4, iclass 26, count 0 2006.258.00:22:18.47#ibcon#read 4, iclass 26, count 0 2006.258.00:22:18.47#ibcon#about to read 5, iclass 26, count 0 2006.258.00:22:18.47#ibcon#read 5, iclass 26, count 0 2006.258.00:22:18.47#ibcon#about to read 6, iclass 26, count 0 2006.258.00:22:18.47#ibcon#read 6, iclass 26, count 0 2006.258.00:22:18.47#ibcon#end of sib2, iclass 26, count 0 2006.258.00:22:18.47#ibcon#*after write, iclass 26, count 0 2006.258.00:22:18.47#ibcon#*before return 0, iclass 26, count 0 2006.258.00:22:18.47#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:18.47#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:22:18.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:22:18.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:22:18.47$vck44/vblo=3,649.99 2006.258.00:22:18.47#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.00:22:18.47#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.00:22:18.47#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:18.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:18.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:18.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:18.47#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:22:18.47#ibcon#first serial, iclass 28, count 0 2006.258.00:22:18.47#ibcon#enter sib2, iclass 28, count 0 2006.258.00:22:18.47#ibcon#flushed, iclass 28, count 0 2006.258.00:22:18.47#ibcon#about to write, iclass 28, count 0 2006.258.00:22:18.47#ibcon#wrote, iclass 28, count 0 2006.258.00:22:18.47#ibcon#about to read 3, iclass 28, count 0 2006.258.00:22:18.49#ibcon#read 3, iclass 28, count 0 2006.258.00:22:18.49#ibcon#about to read 4, iclass 28, count 0 2006.258.00:22:18.49#ibcon#read 4, iclass 28, count 0 2006.258.00:22:18.49#ibcon#about to read 5, iclass 28, count 0 2006.258.00:22:18.49#ibcon#read 5, iclass 28, count 0 2006.258.00:22:18.49#ibcon#about to read 6, iclass 28, count 0 2006.258.00:22:18.49#ibcon#read 6, iclass 28, count 0 2006.258.00:22:18.49#ibcon#end of sib2, iclass 28, count 0 2006.258.00:22:18.49#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:22:18.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:22:18.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:22:18.49#ibcon#*before write, iclass 28, count 0 2006.258.00:22:18.49#ibcon#enter sib2, iclass 28, count 0 2006.258.00:22:18.49#ibcon#flushed, iclass 28, count 0 2006.258.00:22:18.49#ibcon#about to write, iclass 28, count 0 2006.258.00:22:18.49#ibcon#wrote, iclass 28, count 0 2006.258.00:22:18.49#ibcon#about to read 3, iclass 28, count 0 2006.258.00:22:18.53#ibcon#read 3, iclass 28, count 0 2006.258.00:22:18.53#ibcon#about to read 4, iclass 28, count 0 2006.258.00:22:18.53#ibcon#read 4, iclass 28, count 0 2006.258.00:22:18.53#ibcon#about to read 5, iclass 28, count 0 2006.258.00:22:18.53#ibcon#read 5, iclass 28, count 0 2006.258.00:22:18.53#ibcon#about to read 6, iclass 28, count 0 2006.258.00:22:18.53#ibcon#read 6, iclass 28, count 0 2006.258.00:22:18.53#ibcon#end of sib2, iclass 28, count 0 2006.258.00:22:18.53#ibcon#*after write, iclass 28, count 0 2006.258.00:22:18.53#ibcon#*before return 0, iclass 28, count 0 2006.258.00:22:18.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:18.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:22:18.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:22:18.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:22:18.53$vck44/vb=3,4 2006.258.00:22:18.53#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.00:22:18.53#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.00:22:18.53#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:18.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:18.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:18.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:18.59#ibcon#enter wrdev, iclass 30, count 2 2006.258.00:22:18.59#ibcon#first serial, iclass 30, count 2 2006.258.00:22:18.59#ibcon#enter sib2, iclass 30, count 2 2006.258.00:22:18.59#ibcon#flushed, iclass 30, count 2 2006.258.00:22:18.59#ibcon#about to write, iclass 30, count 2 2006.258.00:22:18.59#ibcon#wrote, iclass 30, count 2 2006.258.00:22:18.59#ibcon#about to read 3, iclass 30, count 2 2006.258.00:22:18.61#ibcon#read 3, iclass 30, count 2 2006.258.00:22:18.61#ibcon#about to read 4, iclass 30, count 2 2006.258.00:22:18.61#ibcon#read 4, iclass 30, count 2 2006.258.00:22:18.61#ibcon#about to read 5, iclass 30, count 2 2006.258.00:22:18.61#ibcon#read 5, iclass 30, count 2 2006.258.00:22:18.61#ibcon#about to read 6, iclass 30, count 2 2006.258.00:22:18.61#ibcon#read 6, iclass 30, count 2 2006.258.00:22:18.61#ibcon#end of sib2, iclass 30, count 2 2006.258.00:22:18.61#ibcon#*mode == 0, iclass 30, count 2 2006.258.00:22:18.61#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.00:22:18.61#ibcon#[27=AT03-04\r\n] 2006.258.00:22:18.61#ibcon#*before write, iclass 30, count 2 2006.258.00:22:18.61#ibcon#enter sib2, iclass 30, count 2 2006.258.00:22:18.61#ibcon#flushed, iclass 30, count 2 2006.258.00:22:18.61#ibcon#about to write, iclass 30, count 2 2006.258.00:22:18.61#ibcon#wrote, iclass 30, count 2 2006.258.00:22:18.61#ibcon#about to read 3, iclass 30, count 2 2006.258.00:22:18.64#ibcon#read 3, iclass 30, count 2 2006.258.00:22:18.64#ibcon#about to read 4, iclass 30, count 2 2006.258.00:22:18.64#ibcon#read 4, iclass 30, count 2 2006.258.00:22:18.64#ibcon#about to read 5, iclass 30, count 2 2006.258.00:22:18.64#ibcon#read 5, iclass 30, count 2 2006.258.00:22:18.64#ibcon#about to read 6, iclass 30, count 2 2006.258.00:22:18.64#ibcon#read 6, iclass 30, count 2 2006.258.00:22:18.64#ibcon#end of sib2, iclass 30, count 2 2006.258.00:22:18.64#ibcon#*after write, iclass 30, count 2 2006.258.00:22:18.64#ibcon#*before return 0, iclass 30, count 2 2006.258.00:22:18.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:18.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:22:18.64#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.00:22:18.64#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:18.64#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:18.76#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:18.76#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:18.76#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:22:18.76#ibcon#first serial, iclass 30, count 0 2006.258.00:22:18.76#ibcon#enter sib2, iclass 30, count 0 2006.258.00:22:18.76#ibcon#flushed, iclass 30, count 0 2006.258.00:22:18.76#ibcon#about to write, iclass 30, count 0 2006.258.00:22:18.76#ibcon#wrote, iclass 30, count 0 2006.258.00:22:18.76#ibcon#about to read 3, iclass 30, count 0 2006.258.00:22:18.78#ibcon#read 3, iclass 30, count 0 2006.258.00:22:18.78#ibcon#about to read 4, iclass 30, count 0 2006.258.00:22:18.78#ibcon#read 4, iclass 30, count 0 2006.258.00:22:18.78#ibcon#about to read 5, iclass 30, count 0 2006.258.00:22:18.78#ibcon#read 5, iclass 30, count 0 2006.258.00:22:18.78#ibcon#about to read 6, iclass 30, count 0 2006.258.00:22:18.78#ibcon#read 6, iclass 30, count 0 2006.258.00:22:18.78#ibcon#end of sib2, iclass 30, count 0 2006.258.00:22:18.78#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:22:18.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:22:18.78#ibcon#[27=USB\r\n] 2006.258.00:22:18.78#ibcon#*before write, iclass 30, count 0 2006.258.00:22:18.78#ibcon#enter sib2, iclass 30, count 0 2006.258.00:22:18.78#ibcon#flushed, iclass 30, count 0 2006.258.00:22:18.78#ibcon#about to write, iclass 30, count 0 2006.258.00:22:18.78#ibcon#wrote, iclass 30, count 0 2006.258.00:22:18.78#ibcon#about to read 3, iclass 30, count 0 2006.258.00:22:18.81#ibcon#read 3, iclass 30, count 0 2006.258.00:22:18.81#ibcon#about to read 4, iclass 30, count 0 2006.258.00:22:18.81#ibcon#read 4, iclass 30, count 0 2006.258.00:22:18.81#ibcon#about to read 5, iclass 30, count 0 2006.258.00:22:18.81#ibcon#read 5, iclass 30, count 0 2006.258.00:22:18.81#ibcon#about to read 6, iclass 30, count 0 2006.258.00:22:18.81#ibcon#read 6, iclass 30, count 0 2006.258.00:22:18.81#ibcon#end of sib2, iclass 30, count 0 2006.258.00:22:18.81#ibcon#*after write, iclass 30, count 0 2006.258.00:22:18.81#ibcon#*before return 0, iclass 30, count 0 2006.258.00:22:18.81#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:18.81#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:22:18.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:22:18.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:22:18.81$vck44/vblo=4,679.99 2006.258.00:22:18.81#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.258.00:22:18.81#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.258.00:22:18.81#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:18.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:18.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:18.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:18.81#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:22:18.81#ibcon#first serial, iclass 32, count 0 2006.258.00:22:18.81#ibcon#enter sib2, iclass 32, count 0 2006.258.00:22:18.81#ibcon#flushed, iclass 32, count 0 2006.258.00:22:18.81#ibcon#about to write, iclass 32, count 0 2006.258.00:22:18.81#ibcon#wrote, iclass 32, count 0 2006.258.00:22:18.81#ibcon#about to read 3, iclass 32, count 0 2006.258.00:22:18.83#ibcon#read 3, iclass 32, count 0 2006.258.00:22:18.83#ibcon#about to read 4, iclass 32, count 0 2006.258.00:22:18.83#ibcon#read 4, iclass 32, count 0 2006.258.00:22:18.83#ibcon#about to read 5, iclass 32, count 0 2006.258.00:22:18.83#ibcon#read 5, iclass 32, count 0 2006.258.00:22:18.83#ibcon#about to read 6, iclass 32, count 0 2006.258.00:22:18.83#ibcon#read 6, iclass 32, count 0 2006.258.00:22:18.83#ibcon#end of sib2, iclass 32, count 0 2006.258.00:22:18.83#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:22:18.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:22:18.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:22:18.83#ibcon#*before write, iclass 32, count 0 2006.258.00:22:18.83#ibcon#enter sib2, iclass 32, count 0 2006.258.00:22:18.83#ibcon#flushed, iclass 32, count 0 2006.258.00:22:18.83#ibcon#about to write, iclass 32, count 0 2006.258.00:22:18.83#ibcon#wrote, iclass 32, count 0 2006.258.00:22:18.83#ibcon#about to read 3, iclass 32, count 0 2006.258.00:22:18.87#ibcon#read 3, iclass 32, count 0 2006.258.00:22:18.87#ibcon#about to read 4, iclass 32, count 0 2006.258.00:22:18.87#ibcon#read 4, iclass 32, count 0 2006.258.00:22:18.87#ibcon#about to read 5, iclass 32, count 0 2006.258.00:22:18.87#ibcon#read 5, iclass 32, count 0 2006.258.00:22:18.87#ibcon#about to read 6, iclass 32, count 0 2006.258.00:22:18.87#ibcon#read 6, iclass 32, count 0 2006.258.00:22:18.87#ibcon#end of sib2, iclass 32, count 0 2006.258.00:22:18.87#ibcon#*after write, iclass 32, count 0 2006.258.00:22:18.87#ibcon#*before return 0, iclass 32, count 0 2006.258.00:22:18.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:18.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:22:18.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:22:18.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:22:18.87$vck44/vb=4,5 2006.258.00:22:18.87#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.258.00:22:18.87#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.258.00:22:18.87#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:18.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:18.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:18.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:18.93#ibcon#enter wrdev, iclass 34, count 2 2006.258.00:22:18.93#ibcon#first serial, iclass 34, count 2 2006.258.00:22:18.93#ibcon#enter sib2, iclass 34, count 2 2006.258.00:22:18.93#ibcon#flushed, iclass 34, count 2 2006.258.00:22:18.93#ibcon#about to write, iclass 34, count 2 2006.258.00:22:18.93#ibcon#wrote, iclass 34, count 2 2006.258.00:22:18.93#ibcon#about to read 3, iclass 34, count 2 2006.258.00:22:18.95#ibcon#read 3, iclass 34, count 2 2006.258.00:22:18.95#ibcon#about to read 4, iclass 34, count 2 2006.258.00:22:18.95#ibcon#read 4, iclass 34, count 2 2006.258.00:22:18.95#ibcon#about to read 5, iclass 34, count 2 2006.258.00:22:18.95#ibcon#read 5, iclass 34, count 2 2006.258.00:22:18.95#ibcon#about to read 6, iclass 34, count 2 2006.258.00:22:18.95#ibcon#read 6, iclass 34, count 2 2006.258.00:22:18.95#ibcon#end of sib2, iclass 34, count 2 2006.258.00:22:18.95#ibcon#*mode == 0, iclass 34, count 2 2006.258.00:22:18.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.258.00:22:18.95#ibcon#[27=AT04-05\r\n] 2006.258.00:22:18.95#ibcon#*before write, iclass 34, count 2 2006.258.00:22:18.95#ibcon#enter sib2, iclass 34, count 2 2006.258.00:22:18.95#ibcon#flushed, iclass 34, count 2 2006.258.00:22:18.95#ibcon#about to write, iclass 34, count 2 2006.258.00:22:18.95#ibcon#wrote, iclass 34, count 2 2006.258.00:22:18.95#ibcon#about to read 3, iclass 34, count 2 2006.258.00:22:18.98#ibcon#read 3, iclass 34, count 2 2006.258.00:22:18.98#ibcon#about to read 4, iclass 34, count 2 2006.258.00:22:18.98#ibcon#read 4, iclass 34, count 2 2006.258.00:22:18.98#ibcon#about to read 5, iclass 34, count 2 2006.258.00:22:18.98#ibcon#read 5, iclass 34, count 2 2006.258.00:22:18.98#ibcon#about to read 6, iclass 34, count 2 2006.258.00:22:18.98#ibcon#read 6, iclass 34, count 2 2006.258.00:22:18.98#ibcon#end of sib2, iclass 34, count 2 2006.258.00:22:18.98#ibcon#*after write, iclass 34, count 2 2006.258.00:22:18.98#ibcon#*before return 0, iclass 34, count 2 2006.258.00:22:18.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:18.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:22:18.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.258.00:22:18.98#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:18.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:19.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:19.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:19.10#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:22:19.10#ibcon#first serial, iclass 34, count 0 2006.258.00:22:19.10#ibcon#enter sib2, iclass 34, count 0 2006.258.00:22:19.10#ibcon#flushed, iclass 34, count 0 2006.258.00:22:19.10#ibcon#about to write, iclass 34, count 0 2006.258.00:22:19.10#ibcon#wrote, iclass 34, count 0 2006.258.00:22:19.10#ibcon#about to read 3, iclass 34, count 0 2006.258.00:22:19.12#ibcon#read 3, iclass 34, count 0 2006.258.00:22:19.12#ibcon#about to read 4, iclass 34, count 0 2006.258.00:22:19.12#ibcon#read 4, iclass 34, count 0 2006.258.00:22:19.12#ibcon#about to read 5, iclass 34, count 0 2006.258.00:22:19.12#ibcon#read 5, iclass 34, count 0 2006.258.00:22:19.12#ibcon#about to read 6, iclass 34, count 0 2006.258.00:22:19.12#ibcon#read 6, iclass 34, count 0 2006.258.00:22:19.12#ibcon#end of sib2, iclass 34, count 0 2006.258.00:22:19.12#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:22:19.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:22:19.12#ibcon#[27=USB\r\n] 2006.258.00:22:19.12#ibcon#*before write, iclass 34, count 0 2006.258.00:22:19.12#ibcon#enter sib2, iclass 34, count 0 2006.258.00:22:19.12#ibcon#flushed, iclass 34, count 0 2006.258.00:22:19.12#ibcon#about to write, iclass 34, count 0 2006.258.00:22:19.12#ibcon#wrote, iclass 34, count 0 2006.258.00:22:19.12#ibcon#about to read 3, iclass 34, count 0 2006.258.00:22:19.15#ibcon#read 3, iclass 34, count 0 2006.258.00:22:19.15#ibcon#about to read 4, iclass 34, count 0 2006.258.00:22:19.15#ibcon#read 4, iclass 34, count 0 2006.258.00:22:19.15#ibcon#about to read 5, iclass 34, count 0 2006.258.00:22:19.15#ibcon#read 5, iclass 34, count 0 2006.258.00:22:19.15#ibcon#about to read 6, iclass 34, count 0 2006.258.00:22:19.15#ibcon#read 6, iclass 34, count 0 2006.258.00:22:19.15#ibcon#end of sib2, iclass 34, count 0 2006.258.00:22:19.15#ibcon#*after write, iclass 34, count 0 2006.258.00:22:19.15#ibcon#*before return 0, iclass 34, count 0 2006.258.00:22:19.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:19.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:22:19.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:22:19.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:22:19.15$vck44/vblo=5,709.99 2006.258.00:22:19.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.258.00:22:19.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.258.00:22:19.15#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:19.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:19.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:19.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:19.15#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:22:19.15#ibcon#first serial, iclass 36, count 0 2006.258.00:22:19.15#ibcon#enter sib2, iclass 36, count 0 2006.258.00:22:19.15#ibcon#flushed, iclass 36, count 0 2006.258.00:22:19.15#ibcon#about to write, iclass 36, count 0 2006.258.00:22:19.15#ibcon#wrote, iclass 36, count 0 2006.258.00:22:19.15#ibcon#about to read 3, iclass 36, count 0 2006.258.00:22:19.17#ibcon#read 3, iclass 36, count 0 2006.258.00:22:19.17#ibcon#about to read 4, iclass 36, count 0 2006.258.00:22:19.17#ibcon#read 4, iclass 36, count 0 2006.258.00:22:19.17#ibcon#about to read 5, iclass 36, count 0 2006.258.00:22:19.17#ibcon#read 5, iclass 36, count 0 2006.258.00:22:19.17#ibcon#about to read 6, iclass 36, count 0 2006.258.00:22:19.17#ibcon#read 6, iclass 36, count 0 2006.258.00:22:19.17#ibcon#end of sib2, iclass 36, count 0 2006.258.00:22:19.17#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:22:19.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:22:19.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:22:19.17#ibcon#*before write, iclass 36, count 0 2006.258.00:22:19.17#ibcon#enter sib2, iclass 36, count 0 2006.258.00:22:19.17#ibcon#flushed, iclass 36, count 0 2006.258.00:22:19.17#ibcon#about to write, iclass 36, count 0 2006.258.00:22:19.17#ibcon#wrote, iclass 36, count 0 2006.258.00:22:19.17#ibcon#about to read 3, iclass 36, count 0 2006.258.00:22:19.21#ibcon#read 3, iclass 36, count 0 2006.258.00:22:19.21#ibcon#about to read 4, iclass 36, count 0 2006.258.00:22:19.21#ibcon#read 4, iclass 36, count 0 2006.258.00:22:19.21#ibcon#about to read 5, iclass 36, count 0 2006.258.00:22:19.21#ibcon#read 5, iclass 36, count 0 2006.258.00:22:19.21#ibcon#about to read 6, iclass 36, count 0 2006.258.00:22:19.21#ibcon#read 6, iclass 36, count 0 2006.258.00:22:19.21#ibcon#end of sib2, iclass 36, count 0 2006.258.00:22:19.21#ibcon#*after write, iclass 36, count 0 2006.258.00:22:19.21#ibcon#*before return 0, iclass 36, count 0 2006.258.00:22:19.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:19.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:22:19.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:22:19.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:22:19.21$vck44/vb=5,4 2006.258.00:22:19.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.258.00:22:19.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.258.00:22:19.21#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:19.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:19.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:19.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:19.27#ibcon#enter wrdev, iclass 38, count 2 2006.258.00:22:19.27#ibcon#first serial, iclass 38, count 2 2006.258.00:22:19.27#ibcon#enter sib2, iclass 38, count 2 2006.258.00:22:19.27#ibcon#flushed, iclass 38, count 2 2006.258.00:22:19.27#ibcon#about to write, iclass 38, count 2 2006.258.00:22:19.27#ibcon#wrote, iclass 38, count 2 2006.258.00:22:19.27#ibcon#about to read 3, iclass 38, count 2 2006.258.00:22:19.29#ibcon#read 3, iclass 38, count 2 2006.258.00:22:19.29#ibcon#about to read 4, iclass 38, count 2 2006.258.00:22:19.29#ibcon#read 4, iclass 38, count 2 2006.258.00:22:19.29#ibcon#about to read 5, iclass 38, count 2 2006.258.00:22:19.29#ibcon#read 5, iclass 38, count 2 2006.258.00:22:19.29#ibcon#about to read 6, iclass 38, count 2 2006.258.00:22:19.29#ibcon#read 6, iclass 38, count 2 2006.258.00:22:19.29#ibcon#end of sib2, iclass 38, count 2 2006.258.00:22:19.29#ibcon#*mode == 0, iclass 38, count 2 2006.258.00:22:19.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.258.00:22:19.29#ibcon#[27=AT05-04\r\n] 2006.258.00:22:19.29#ibcon#*before write, iclass 38, count 2 2006.258.00:22:19.29#ibcon#enter sib2, iclass 38, count 2 2006.258.00:22:19.29#ibcon#flushed, iclass 38, count 2 2006.258.00:22:19.29#ibcon#about to write, iclass 38, count 2 2006.258.00:22:19.29#ibcon#wrote, iclass 38, count 2 2006.258.00:22:19.29#ibcon#about to read 3, iclass 38, count 2 2006.258.00:22:19.32#ibcon#read 3, iclass 38, count 2 2006.258.00:22:19.32#ibcon#about to read 4, iclass 38, count 2 2006.258.00:22:19.32#ibcon#read 4, iclass 38, count 2 2006.258.00:22:19.32#ibcon#about to read 5, iclass 38, count 2 2006.258.00:22:19.32#ibcon#read 5, iclass 38, count 2 2006.258.00:22:19.32#ibcon#about to read 6, iclass 38, count 2 2006.258.00:22:19.32#ibcon#read 6, iclass 38, count 2 2006.258.00:22:19.32#ibcon#end of sib2, iclass 38, count 2 2006.258.00:22:19.32#ibcon#*after write, iclass 38, count 2 2006.258.00:22:19.33#ibcon#*before return 0, iclass 38, count 2 2006.258.00:22:19.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:19.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:22:19.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.258.00:22:19.33#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:19.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:19.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:19.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:19.45#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:22:19.45#ibcon#first serial, iclass 38, count 0 2006.258.00:22:19.45#ibcon#enter sib2, iclass 38, count 0 2006.258.00:22:19.45#ibcon#flushed, iclass 38, count 0 2006.258.00:22:19.45#ibcon#about to write, iclass 38, count 0 2006.258.00:22:19.45#ibcon#wrote, iclass 38, count 0 2006.258.00:22:19.45#ibcon#about to read 3, iclass 38, count 0 2006.258.00:22:19.47#ibcon#read 3, iclass 38, count 0 2006.258.00:22:19.47#ibcon#about to read 4, iclass 38, count 0 2006.258.00:22:19.47#ibcon#read 4, iclass 38, count 0 2006.258.00:22:19.47#ibcon#about to read 5, iclass 38, count 0 2006.258.00:22:19.47#ibcon#read 5, iclass 38, count 0 2006.258.00:22:19.47#ibcon#about to read 6, iclass 38, count 0 2006.258.00:22:19.47#ibcon#read 6, iclass 38, count 0 2006.258.00:22:19.47#ibcon#end of sib2, iclass 38, count 0 2006.258.00:22:19.47#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:22:19.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:22:19.47#ibcon#[27=USB\r\n] 2006.258.00:22:19.47#ibcon#*before write, iclass 38, count 0 2006.258.00:22:19.47#ibcon#enter sib2, iclass 38, count 0 2006.258.00:22:19.47#ibcon#flushed, iclass 38, count 0 2006.258.00:22:19.47#ibcon#about to write, iclass 38, count 0 2006.258.00:22:19.47#ibcon#wrote, iclass 38, count 0 2006.258.00:22:19.47#ibcon#about to read 3, iclass 38, count 0 2006.258.00:22:19.50#ibcon#read 3, iclass 38, count 0 2006.258.00:22:19.50#ibcon#about to read 4, iclass 38, count 0 2006.258.00:22:19.50#ibcon#read 4, iclass 38, count 0 2006.258.00:22:19.50#ibcon#about to read 5, iclass 38, count 0 2006.258.00:22:19.50#ibcon#read 5, iclass 38, count 0 2006.258.00:22:19.50#ibcon#about to read 6, iclass 38, count 0 2006.258.00:22:19.50#ibcon#read 6, iclass 38, count 0 2006.258.00:22:19.50#ibcon#end of sib2, iclass 38, count 0 2006.258.00:22:19.50#ibcon#*after write, iclass 38, count 0 2006.258.00:22:19.50#ibcon#*before return 0, iclass 38, count 0 2006.258.00:22:19.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:19.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:22:19.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:22:19.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:22:19.50$vck44/vblo=6,719.99 2006.258.00:22:19.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.00:22:19.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.00:22:19.50#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:19.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:19.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:19.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:19.50#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:22:19.50#ibcon#first serial, iclass 40, count 0 2006.258.00:22:19.50#ibcon#enter sib2, iclass 40, count 0 2006.258.00:22:19.50#ibcon#flushed, iclass 40, count 0 2006.258.00:22:19.50#ibcon#about to write, iclass 40, count 0 2006.258.00:22:19.50#ibcon#wrote, iclass 40, count 0 2006.258.00:22:19.50#ibcon#about to read 3, iclass 40, count 0 2006.258.00:22:19.52#ibcon#read 3, iclass 40, count 0 2006.258.00:22:19.52#ibcon#about to read 4, iclass 40, count 0 2006.258.00:22:19.52#ibcon#read 4, iclass 40, count 0 2006.258.00:22:19.52#ibcon#about to read 5, iclass 40, count 0 2006.258.00:22:19.52#ibcon#read 5, iclass 40, count 0 2006.258.00:22:19.52#ibcon#about to read 6, iclass 40, count 0 2006.258.00:22:19.52#ibcon#read 6, iclass 40, count 0 2006.258.00:22:19.52#ibcon#end of sib2, iclass 40, count 0 2006.258.00:22:19.52#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:22:19.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:22:19.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:22:19.52#ibcon#*before write, iclass 40, count 0 2006.258.00:22:19.52#ibcon#enter sib2, iclass 40, count 0 2006.258.00:22:19.52#ibcon#flushed, iclass 40, count 0 2006.258.00:22:19.52#ibcon#about to write, iclass 40, count 0 2006.258.00:22:19.52#ibcon#wrote, iclass 40, count 0 2006.258.00:22:19.52#ibcon#about to read 3, iclass 40, count 0 2006.258.00:22:19.56#ibcon#read 3, iclass 40, count 0 2006.258.00:22:19.56#ibcon#about to read 4, iclass 40, count 0 2006.258.00:22:19.56#ibcon#read 4, iclass 40, count 0 2006.258.00:22:19.56#ibcon#about to read 5, iclass 40, count 0 2006.258.00:22:19.56#ibcon#read 5, iclass 40, count 0 2006.258.00:22:19.56#ibcon#about to read 6, iclass 40, count 0 2006.258.00:22:19.56#ibcon#read 6, iclass 40, count 0 2006.258.00:22:19.56#ibcon#end of sib2, iclass 40, count 0 2006.258.00:22:19.56#ibcon#*after write, iclass 40, count 0 2006.258.00:22:19.56#ibcon#*before return 0, iclass 40, count 0 2006.258.00:22:19.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:19.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:22:19.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:22:19.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:22:19.56$vck44/vb=6,4 2006.258.00:22:19.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.258.00:22:19.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.258.00:22:19.56#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:19.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:19.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:19.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:19.62#ibcon#enter wrdev, iclass 4, count 2 2006.258.00:22:19.62#ibcon#first serial, iclass 4, count 2 2006.258.00:22:19.62#ibcon#enter sib2, iclass 4, count 2 2006.258.00:22:19.62#ibcon#flushed, iclass 4, count 2 2006.258.00:22:19.62#ibcon#about to write, iclass 4, count 2 2006.258.00:22:19.62#ibcon#wrote, iclass 4, count 2 2006.258.00:22:19.62#ibcon#about to read 3, iclass 4, count 2 2006.258.00:22:19.64#ibcon#read 3, iclass 4, count 2 2006.258.00:22:19.64#ibcon#about to read 4, iclass 4, count 2 2006.258.00:22:19.64#ibcon#read 4, iclass 4, count 2 2006.258.00:22:19.64#ibcon#about to read 5, iclass 4, count 2 2006.258.00:22:19.64#ibcon#read 5, iclass 4, count 2 2006.258.00:22:19.64#ibcon#about to read 6, iclass 4, count 2 2006.258.00:22:19.64#ibcon#read 6, iclass 4, count 2 2006.258.00:22:19.64#ibcon#end of sib2, iclass 4, count 2 2006.258.00:22:19.64#ibcon#*mode == 0, iclass 4, count 2 2006.258.00:22:19.64#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.258.00:22:19.64#ibcon#[27=AT06-04\r\n] 2006.258.00:22:19.64#ibcon#*before write, iclass 4, count 2 2006.258.00:22:19.64#ibcon#enter sib2, iclass 4, count 2 2006.258.00:22:19.64#ibcon#flushed, iclass 4, count 2 2006.258.00:22:19.64#ibcon#about to write, iclass 4, count 2 2006.258.00:22:19.64#ibcon#wrote, iclass 4, count 2 2006.258.00:22:19.64#ibcon#about to read 3, iclass 4, count 2 2006.258.00:22:19.67#ibcon#read 3, iclass 4, count 2 2006.258.00:22:19.67#ibcon#about to read 4, iclass 4, count 2 2006.258.00:22:19.67#ibcon#read 4, iclass 4, count 2 2006.258.00:22:19.67#ibcon#about to read 5, iclass 4, count 2 2006.258.00:22:19.67#ibcon#read 5, iclass 4, count 2 2006.258.00:22:19.67#ibcon#about to read 6, iclass 4, count 2 2006.258.00:22:19.67#ibcon#read 6, iclass 4, count 2 2006.258.00:22:19.67#ibcon#end of sib2, iclass 4, count 2 2006.258.00:22:19.67#ibcon#*after write, iclass 4, count 2 2006.258.00:22:19.67#ibcon#*before return 0, iclass 4, count 2 2006.258.00:22:19.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:19.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:22:19.67#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.258.00:22:19.67#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:19.67#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:19.79#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:19.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:19.79#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:22:19.79#ibcon#first serial, iclass 4, count 0 2006.258.00:22:19.79#ibcon#enter sib2, iclass 4, count 0 2006.258.00:22:19.79#ibcon#flushed, iclass 4, count 0 2006.258.00:22:19.79#ibcon#about to write, iclass 4, count 0 2006.258.00:22:19.79#ibcon#wrote, iclass 4, count 0 2006.258.00:22:19.79#ibcon#about to read 3, iclass 4, count 0 2006.258.00:22:19.81#ibcon#read 3, iclass 4, count 0 2006.258.00:22:19.81#ibcon#about to read 4, iclass 4, count 0 2006.258.00:22:19.81#ibcon#read 4, iclass 4, count 0 2006.258.00:22:19.81#ibcon#about to read 5, iclass 4, count 0 2006.258.00:22:19.81#ibcon#read 5, iclass 4, count 0 2006.258.00:22:19.81#ibcon#about to read 6, iclass 4, count 0 2006.258.00:22:19.81#ibcon#read 6, iclass 4, count 0 2006.258.00:22:19.81#ibcon#end of sib2, iclass 4, count 0 2006.258.00:22:19.81#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:22:19.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:22:19.81#ibcon#[27=USB\r\n] 2006.258.00:22:19.81#ibcon#*before write, iclass 4, count 0 2006.258.00:22:19.81#ibcon#enter sib2, iclass 4, count 0 2006.258.00:22:19.81#ibcon#flushed, iclass 4, count 0 2006.258.00:22:19.81#ibcon#about to write, iclass 4, count 0 2006.258.00:22:19.81#ibcon#wrote, iclass 4, count 0 2006.258.00:22:19.81#ibcon#about to read 3, iclass 4, count 0 2006.258.00:22:19.84#ibcon#read 3, iclass 4, count 0 2006.258.00:22:19.84#ibcon#about to read 4, iclass 4, count 0 2006.258.00:22:19.84#ibcon#read 4, iclass 4, count 0 2006.258.00:22:19.84#ibcon#about to read 5, iclass 4, count 0 2006.258.00:22:19.84#ibcon#read 5, iclass 4, count 0 2006.258.00:22:19.84#ibcon#about to read 6, iclass 4, count 0 2006.258.00:22:19.84#ibcon#read 6, iclass 4, count 0 2006.258.00:22:19.84#ibcon#end of sib2, iclass 4, count 0 2006.258.00:22:19.84#ibcon#*after write, iclass 4, count 0 2006.258.00:22:19.84#ibcon#*before return 0, iclass 4, count 0 2006.258.00:22:19.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:19.84#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:22:19.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:22:19.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:22:19.84$vck44/vblo=7,734.99 2006.258.00:22:19.84#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.00:22:19.84#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.00:22:19.84#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:19.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:19.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:19.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:19.84#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:22:19.84#ibcon#first serial, iclass 6, count 0 2006.258.00:22:19.84#ibcon#enter sib2, iclass 6, count 0 2006.258.00:22:19.84#ibcon#flushed, iclass 6, count 0 2006.258.00:22:19.84#ibcon#about to write, iclass 6, count 0 2006.258.00:22:19.84#ibcon#wrote, iclass 6, count 0 2006.258.00:22:19.84#ibcon#about to read 3, iclass 6, count 0 2006.258.00:22:19.86#ibcon#read 3, iclass 6, count 0 2006.258.00:22:19.86#ibcon#about to read 4, iclass 6, count 0 2006.258.00:22:19.86#ibcon#read 4, iclass 6, count 0 2006.258.00:22:19.86#ibcon#about to read 5, iclass 6, count 0 2006.258.00:22:19.86#ibcon#read 5, iclass 6, count 0 2006.258.00:22:19.86#ibcon#about to read 6, iclass 6, count 0 2006.258.00:22:19.86#ibcon#read 6, iclass 6, count 0 2006.258.00:22:19.86#ibcon#end of sib2, iclass 6, count 0 2006.258.00:22:19.86#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:22:19.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:22:19.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:22:19.86#ibcon#*before write, iclass 6, count 0 2006.258.00:22:19.86#ibcon#enter sib2, iclass 6, count 0 2006.258.00:22:19.86#ibcon#flushed, iclass 6, count 0 2006.258.00:22:19.86#ibcon#about to write, iclass 6, count 0 2006.258.00:22:19.86#ibcon#wrote, iclass 6, count 0 2006.258.00:22:19.86#ibcon#about to read 3, iclass 6, count 0 2006.258.00:22:19.90#ibcon#read 3, iclass 6, count 0 2006.258.00:22:19.90#ibcon#about to read 4, iclass 6, count 0 2006.258.00:22:19.90#ibcon#read 4, iclass 6, count 0 2006.258.00:22:19.90#ibcon#about to read 5, iclass 6, count 0 2006.258.00:22:19.90#ibcon#read 5, iclass 6, count 0 2006.258.00:22:19.90#ibcon#about to read 6, iclass 6, count 0 2006.258.00:22:19.90#ibcon#read 6, iclass 6, count 0 2006.258.00:22:19.90#ibcon#end of sib2, iclass 6, count 0 2006.258.00:22:19.90#ibcon#*after write, iclass 6, count 0 2006.258.00:22:19.90#ibcon#*before return 0, iclass 6, count 0 2006.258.00:22:19.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:19.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:22:19.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:22:19.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:22:19.90$vck44/vb=7,4 2006.258.00:22:19.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.258.00:22:19.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.258.00:22:19.90#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:19.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:19.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:19.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:19.96#ibcon#enter wrdev, iclass 10, count 2 2006.258.00:22:19.96#ibcon#first serial, iclass 10, count 2 2006.258.00:22:19.96#ibcon#enter sib2, iclass 10, count 2 2006.258.00:22:19.96#ibcon#flushed, iclass 10, count 2 2006.258.00:22:19.96#ibcon#about to write, iclass 10, count 2 2006.258.00:22:19.96#ibcon#wrote, iclass 10, count 2 2006.258.00:22:19.96#ibcon#about to read 3, iclass 10, count 2 2006.258.00:22:19.98#ibcon#read 3, iclass 10, count 2 2006.258.00:22:19.98#ibcon#about to read 4, iclass 10, count 2 2006.258.00:22:19.98#ibcon#read 4, iclass 10, count 2 2006.258.00:22:19.98#ibcon#about to read 5, iclass 10, count 2 2006.258.00:22:19.98#ibcon#read 5, iclass 10, count 2 2006.258.00:22:19.98#ibcon#about to read 6, iclass 10, count 2 2006.258.00:22:19.98#ibcon#read 6, iclass 10, count 2 2006.258.00:22:19.98#ibcon#end of sib2, iclass 10, count 2 2006.258.00:22:19.98#ibcon#*mode == 0, iclass 10, count 2 2006.258.00:22:19.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.258.00:22:19.98#ibcon#[27=AT07-04\r\n] 2006.258.00:22:19.98#ibcon#*before write, iclass 10, count 2 2006.258.00:22:19.98#ibcon#enter sib2, iclass 10, count 2 2006.258.00:22:19.98#ibcon#flushed, iclass 10, count 2 2006.258.00:22:19.98#ibcon#about to write, iclass 10, count 2 2006.258.00:22:19.98#ibcon#wrote, iclass 10, count 2 2006.258.00:22:19.98#ibcon#about to read 3, iclass 10, count 2 2006.258.00:22:20.01#ibcon#read 3, iclass 10, count 2 2006.258.00:22:20.01#ibcon#about to read 4, iclass 10, count 2 2006.258.00:22:20.01#ibcon#read 4, iclass 10, count 2 2006.258.00:22:20.01#ibcon#about to read 5, iclass 10, count 2 2006.258.00:22:20.01#ibcon#read 5, iclass 10, count 2 2006.258.00:22:20.01#ibcon#about to read 6, iclass 10, count 2 2006.258.00:22:20.01#ibcon#read 6, iclass 10, count 2 2006.258.00:22:20.01#ibcon#end of sib2, iclass 10, count 2 2006.258.00:22:20.01#ibcon#*after write, iclass 10, count 2 2006.258.00:22:20.01#ibcon#*before return 0, iclass 10, count 2 2006.258.00:22:20.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:20.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:22:20.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.258.00:22:20.01#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:20.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:20.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:20.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:20.13#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:22:20.13#ibcon#first serial, iclass 10, count 0 2006.258.00:22:20.13#ibcon#enter sib2, iclass 10, count 0 2006.258.00:22:20.13#ibcon#flushed, iclass 10, count 0 2006.258.00:22:20.13#ibcon#about to write, iclass 10, count 0 2006.258.00:22:20.13#ibcon#wrote, iclass 10, count 0 2006.258.00:22:20.13#ibcon#about to read 3, iclass 10, count 0 2006.258.00:22:20.15#ibcon#read 3, iclass 10, count 0 2006.258.00:22:20.15#ibcon#about to read 4, iclass 10, count 0 2006.258.00:22:20.15#ibcon#read 4, iclass 10, count 0 2006.258.00:22:20.15#ibcon#about to read 5, iclass 10, count 0 2006.258.00:22:20.15#ibcon#read 5, iclass 10, count 0 2006.258.00:22:20.15#ibcon#about to read 6, iclass 10, count 0 2006.258.00:22:20.15#ibcon#read 6, iclass 10, count 0 2006.258.00:22:20.15#ibcon#end of sib2, iclass 10, count 0 2006.258.00:22:20.15#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:22:20.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:22:20.15#ibcon#[27=USB\r\n] 2006.258.00:22:20.15#ibcon#*before write, iclass 10, count 0 2006.258.00:22:20.15#ibcon#enter sib2, iclass 10, count 0 2006.258.00:22:20.15#ibcon#flushed, iclass 10, count 0 2006.258.00:22:20.15#ibcon#about to write, iclass 10, count 0 2006.258.00:22:20.15#ibcon#wrote, iclass 10, count 0 2006.258.00:22:20.15#ibcon#about to read 3, iclass 10, count 0 2006.258.00:22:20.18#ibcon#read 3, iclass 10, count 0 2006.258.00:22:20.18#ibcon#about to read 4, iclass 10, count 0 2006.258.00:22:20.18#ibcon#read 4, iclass 10, count 0 2006.258.00:22:20.18#ibcon#about to read 5, iclass 10, count 0 2006.258.00:22:20.18#ibcon#read 5, iclass 10, count 0 2006.258.00:22:20.18#ibcon#about to read 6, iclass 10, count 0 2006.258.00:22:20.18#ibcon#read 6, iclass 10, count 0 2006.258.00:22:20.18#ibcon#end of sib2, iclass 10, count 0 2006.258.00:22:20.18#ibcon#*after write, iclass 10, count 0 2006.258.00:22:20.18#ibcon#*before return 0, iclass 10, count 0 2006.258.00:22:20.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:20.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:22:20.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:22:20.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:22:20.18$vck44/vblo=8,744.99 2006.258.00:22:20.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.00:22:20.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.00:22:20.18#ibcon#ireg 17 cls_cnt 0 2006.258.00:22:20.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:20.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:20.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:20.18#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:22:20.18#ibcon#first serial, iclass 12, count 0 2006.258.00:22:20.18#ibcon#enter sib2, iclass 12, count 0 2006.258.00:22:20.18#ibcon#flushed, iclass 12, count 0 2006.258.00:22:20.18#ibcon#about to write, iclass 12, count 0 2006.258.00:22:20.18#ibcon#wrote, iclass 12, count 0 2006.258.00:22:20.18#ibcon#about to read 3, iclass 12, count 0 2006.258.00:22:20.20#ibcon#read 3, iclass 12, count 0 2006.258.00:22:20.20#ibcon#about to read 4, iclass 12, count 0 2006.258.00:22:20.20#ibcon#read 4, iclass 12, count 0 2006.258.00:22:20.20#ibcon#about to read 5, iclass 12, count 0 2006.258.00:22:20.20#ibcon#read 5, iclass 12, count 0 2006.258.00:22:20.20#ibcon#about to read 6, iclass 12, count 0 2006.258.00:22:20.20#ibcon#read 6, iclass 12, count 0 2006.258.00:22:20.20#ibcon#end of sib2, iclass 12, count 0 2006.258.00:22:20.20#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:22:20.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:22:20.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:22:20.20#ibcon#*before write, iclass 12, count 0 2006.258.00:22:20.20#ibcon#enter sib2, iclass 12, count 0 2006.258.00:22:20.20#ibcon#flushed, iclass 12, count 0 2006.258.00:22:20.20#ibcon#about to write, iclass 12, count 0 2006.258.00:22:20.20#ibcon#wrote, iclass 12, count 0 2006.258.00:22:20.20#ibcon#about to read 3, iclass 12, count 0 2006.258.00:22:20.24#ibcon#read 3, iclass 12, count 0 2006.258.00:22:20.24#ibcon#about to read 4, iclass 12, count 0 2006.258.00:22:20.24#ibcon#read 4, iclass 12, count 0 2006.258.00:22:20.24#ibcon#about to read 5, iclass 12, count 0 2006.258.00:22:20.24#ibcon#read 5, iclass 12, count 0 2006.258.00:22:20.24#ibcon#about to read 6, iclass 12, count 0 2006.258.00:22:20.24#ibcon#read 6, iclass 12, count 0 2006.258.00:22:20.24#ibcon#end of sib2, iclass 12, count 0 2006.258.00:22:20.24#ibcon#*after write, iclass 12, count 0 2006.258.00:22:20.24#ibcon#*before return 0, iclass 12, count 0 2006.258.00:22:20.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:20.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:22:20.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:22:20.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:22:20.24$vck44/vb=8,4 2006.258.00:22:20.24#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.258.00:22:20.24#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.258.00:22:20.24#ibcon#ireg 11 cls_cnt 2 2006.258.00:22:20.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:20.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:20.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:20.30#ibcon#enter wrdev, iclass 14, count 2 2006.258.00:22:20.30#ibcon#first serial, iclass 14, count 2 2006.258.00:22:20.30#ibcon#enter sib2, iclass 14, count 2 2006.258.00:22:20.30#ibcon#flushed, iclass 14, count 2 2006.258.00:22:20.30#ibcon#about to write, iclass 14, count 2 2006.258.00:22:20.30#ibcon#wrote, iclass 14, count 2 2006.258.00:22:20.30#ibcon#about to read 3, iclass 14, count 2 2006.258.00:22:20.32#ibcon#read 3, iclass 14, count 2 2006.258.00:22:20.32#ibcon#about to read 4, iclass 14, count 2 2006.258.00:22:20.32#ibcon#read 4, iclass 14, count 2 2006.258.00:22:20.32#ibcon#about to read 5, iclass 14, count 2 2006.258.00:22:20.32#ibcon#read 5, iclass 14, count 2 2006.258.00:22:20.32#ibcon#about to read 6, iclass 14, count 2 2006.258.00:22:20.32#ibcon#read 6, iclass 14, count 2 2006.258.00:22:20.32#ibcon#end of sib2, iclass 14, count 2 2006.258.00:22:20.32#ibcon#*mode == 0, iclass 14, count 2 2006.258.00:22:20.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.258.00:22:20.32#ibcon#[27=AT08-04\r\n] 2006.258.00:22:20.32#ibcon#*before write, iclass 14, count 2 2006.258.00:22:20.32#ibcon#enter sib2, iclass 14, count 2 2006.258.00:22:20.32#ibcon#flushed, iclass 14, count 2 2006.258.00:22:20.32#ibcon#about to write, iclass 14, count 2 2006.258.00:22:20.32#ibcon#wrote, iclass 14, count 2 2006.258.00:22:20.32#ibcon#about to read 3, iclass 14, count 2 2006.258.00:22:20.35#ibcon#read 3, iclass 14, count 2 2006.258.00:22:20.35#ibcon#about to read 4, iclass 14, count 2 2006.258.00:22:20.35#ibcon#read 4, iclass 14, count 2 2006.258.00:22:20.35#ibcon#about to read 5, iclass 14, count 2 2006.258.00:22:20.35#ibcon#read 5, iclass 14, count 2 2006.258.00:22:20.35#ibcon#about to read 6, iclass 14, count 2 2006.258.00:22:20.35#ibcon#read 6, iclass 14, count 2 2006.258.00:22:20.35#ibcon#end of sib2, iclass 14, count 2 2006.258.00:22:20.35#ibcon#*after write, iclass 14, count 2 2006.258.00:22:20.35#ibcon#*before return 0, iclass 14, count 2 2006.258.00:22:20.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:20.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:22:20.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.258.00:22:20.35#ibcon#ireg 7 cls_cnt 0 2006.258.00:22:20.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:20.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:20.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:20.47#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:22:20.47#ibcon#first serial, iclass 14, count 0 2006.258.00:22:20.47#ibcon#enter sib2, iclass 14, count 0 2006.258.00:22:20.47#ibcon#flushed, iclass 14, count 0 2006.258.00:22:20.47#ibcon#about to write, iclass 14, count 0 2006.258.00:22:20.47#ibcon#wrote, iclass 14, count 0 2006.258.00:22:20.47#ibcon#about to read 3, iclass 14, count 0 2006.258.00:22:20.49#ibcon#read 3, iclass 14, count 0 2006.258.00:22:20.49#ibcon#about to read 4, iclass 14, count 0 2006.258.00:22:20.49#ibcon#read 4, iclass 14, count 0 2006.258.00:22:20.49#ibcon#about to read 5, iclass 14, count 0 2006.258.00:22:20.49#ibcon#read 5, iclass 14, count 0 2006.258.00:22:20.49#ibcon#about to read 6, iclass 14, count 0 2006.258.00:22:20.49#ibcon#read 6, iclass 14, count 0 2006.258.00:22:20.49#ibcon#end of sib2, iclass 14, count 0 2006.258.00:22:20.49#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:22:20.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:22:20.49#ibcon#[27=USB\r\n] 2006.258.00:22:20.49#ibcon#*before write, iclass 14, count 0 2006.258.00:22:20.49#ibcon#enter sib2, iclass 14, count 0 2006.258.00:22:20.49#ibcon#flushed, iclass 14, count 0 2006.258.00:22:20.49#ibcon#about to write, iclass 14, count 0 2006.258.00:22:20.49#ibcon#wrote, iclass 14, count 0 2006.258.00:22:20.49#ibcon#about to read 3, iclass 14, count 0 2006.258.00:22:20.52#ibcon#read 3, iclass 14, count 0 2006.258.00:22:20.52#ibcon#about to read 4, iclass 14, count 0 2006.258.00:22:20.52#ibcon#read 4, iclass 14, count 0 2006.258.00:22:20.52#ibcon#about to read 5, iclass 14, count 0 2006.258.00:22:20.52#ibcon#read 5, iclass 14, count 0 2006.258.00:22:20.52#ibcon#about to read 6, iclass 14, count 0 2006.258.00:22:20.52#ibcon#read 6, iclass 14, count 0 2006.258.00:22:20.52#ibcon#end of sib2, iclass 14, count 0 2006.258.00:22:20.52#ibcon#*after write, iclass 14, count 0 2006.258.00:22:20.52#ibcon#*before return 0, iclass 14, count 0 2006.258.00:22:20.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:20.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:22:20.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:22:20.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:22:20.52$vck44/vabw=wide 2006.258.00:22:20.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.00:22:20.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.00:22:20.52#ibcon#ireg 8 cls_cnt 0 2006.258.00:22:20.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:20.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:20.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:20.52#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:22:20.52#ibcon#first serial, iclass 16, count 0 2006.258.00:22:20.52#ibcon#enter sib2, iclass 16, count 0 2006.258.00:22:20.52#ibcon#flushed, iclass 16, count 0 2006.258.00:22:20.52#ibcon#about to write, iclass 16, count 0 2006.258.00:22:20.52#ibcon#wrote, iclass 16, count 0 2006.258.00:22:20.52#ibcon#about to read 3, iclass 16, count 0 2006.258.00:22:20.54#ibcon#read 3, iclass 16, count 0 2006.258.00:22:20.54#ibcon#about to read 4, iclass 16, count 0 2006.258.00:22:20.54#ibcon#read 4, iclass 16, count 0 2006.258.00:22:20.54#ibcon#about to read 5, iclass 16, count 0 2006.258.00:22:20.54#ibcon#read 5, iclass 16, count 0 2006.258.00:22:20.54#ibcon#about to read 6, iclass 16, count 0 2006.258.00:22:20.54#ibcon#read 6, iclass 16, count 0 2006.258.00:22:20.54#ibcon#end of sib2, iclass 16, count 0 2006.258.00:22:20.54#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:22:20.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:22:20.54#ibcon#[25=BW32\r\n] 2006.258.00:22:20.54#ibcon#*before write, iclass 16, count 0 2006.258.00:22:20.54#ibcon#enter sib2, iclass 16, count 0 2006.258.00:22:20.54#ibcon#flushed, iclass 16, count 0 2006.258.00:22:20.54#ibcon#about to write, iclass 16, count 0 2006.258.00:22:20.54#ibcon#wrote, iclass 16, count 0 2006.258.00:22:20.54#ibcon#about to read 3, iclass 16, count 0 2006.258.00:22:20.57#ibcon#read 3, iclass 16, count 0 2006.258.00:22:20.57#ibcon#about to read 4, iclass 16, count 0 2006.258.00:22:20.57#ibcon#read 4, iclass 16, count 0 2006.258.00:22:20.57#ibcon#about to read 5, iclass 16, count 0 2006.258.00:22:20.57#ibcon#read 5, iclass 16, count 0 2006.258.00:22:20.57#ibcon#about to read 6, iclass 16, count 0 2006.258.00:22:20.57#ibcon#read 6, iclass 16, count 0 2006.258.00:22:20.57#ibcon#end of sib2, iclass 16, count 0 2006.258.00:22:20.57#ibcon#*after write, iclass 16, count 0 2006.258.00:22:20.57#ibcon#*before return 0, iclass 16, count 0 2006.258.00:22:20.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:20.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:22:20.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:22:20.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:22:20.57$vck44/vbbw=wide 2006.258.00:22:20.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.00:22:20.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.00:22:20.57#ibcon#ireg 8 cls_cnt 0 2006.258.00:22:20.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:22:20.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:22:20.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:22:20.64#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:22:20.64#ibcon#first serial, iclass 18, count 0 2006.258.00:22:20.64#ibcon#enter sib2, iclass 18, count 0 2006.258.00:22:20.64#ibcon#flushed, iclass 18, count 0 2006.258.00:22:20.64#ibcon#about to write, iclass 18, count 0 2006.258.00:22:20.64#ibcon#wrote, iclass 18, count 0 2006.258.00:22:20.64#ibcon#about to read 3, iclass 18, count 0 2006.258.00:22:20.66#ibcon#read 3, iclass 18, count 0 2006.258.00:22:20.66#ibcon#about to read 4, iclass 18, count 0 2006.258.00:22:20.66#ibcon#read 4, iclass 18, count 0 2006.258.00:22:20.66#ibcon#about to read 5, iclass 18, count 0 2006.258.00:22:20.66#ibcon#read 5, iclass 18, count 0 2006.258.00:22:20.66#ibcon#about to read 6, iclass 18, count 0 2006.258.00:22:20.66#ibcon#read 6, iclass 18, count 0 2006.258.00:22:20.66#ibcon#end of sib2, iclass 18, count 0 2006.258.00:22:20.66#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:22:20.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:22:20.66#ibcon#[27=BW32\r\n] 2006.258.00:22:20.66#ibcon#*before write, iclass 18, count 0 2006.258.00:22:20.66#ibcon#enter sib2, iclass 18, count 0 2006.258.00:22:20.66#ibcon#flushed, iclass 18, count 0 2006.258.00:22:20.66#ibcon#about to write, iclass 18, count 0 2006.258.00:22:20.66#ibcon#wrote, iclass 18, count 0 2006.258.00:22:20.66#ibcon#about to read 3, iclass 18, count 0 2006.258.00:22:20.69#ibcon#read 3, iclass 18, count 0 2006.258.00:22:20.69#ibcon#about to read 4, iclass 18, count 0 2006.258.00:22:20.69#ibcon#read 4, iclass 18, count 0 2006.258.00:22:20.69#ibcon#about to read 5, iclass 18, count 0 2006.258.00:22:20.69#ibcon#read 5, iclass 18, count 0 2006.258.00:22:20.69#ibcon#about to read 6, iclass 18, count 0 2006.258.00:22:20.69#ibcon#read 6, iclass 18, count 0 2006.258.00:22:20.69#ibcon#end of sib2, iclass 18, count 0 2006.258.00:22:20.69#ibcon#*after write, iclass 18, count 0 2006.258.00:22:20.69#ibcon#*before return 0, iclass 18, count 0 2006.258.00:22:20.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:22:20.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:22:20.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:22:20.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:22:20.69$setupk4/ifdk4 2006.258.00:22:20.69$ifdk4/lo= 2006.258.00:22:20.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:22:20.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:22:20.69$ifdk4/patch= 2006.258.00:22:20.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:22:20.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:22:20.69$setupk4/!*+20s 2006.258.00:22:23.37#abcon#<5=/02 1.4 4.3 21.84 791016.1\r\n> 2006.258.00:22:23.39#abcon#{5=INTERFACE CLEAR} 2006.258.00:22:23.45#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:22:33.54#abcon#<5=/02 1.4 4.3 21.84 801016.1\r\n> 2006.258.00:22:33.56#abcon#{5=INTERFACE CLEAR} 2006.258.00:22:33.62#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:22:35.19$setupk4/"tpicd 2006.258.00:22:35.19$setupk4/echo=off 2006.258.00:22:35.19$setupk4/xlog=off 2006.258.00:22:35.19:!2006.258.00:25:17 2006.258.00:22:43.14#trakl#Source acquired 2006.258.00:22:44.14#flagr#flagr/antenna,acquired 2006.258.00:25:17.00:preob 2006.258.00:25:18.13/onsource/TRACKING 2006.258.00:25:18.13:!2006.258.00:25:27 2006.258.00:25:27.00:"tape 2006.258.00:25:27.00:"st=record 2006.258.00:25:27.00:data_valid=on 2006.258.00:25:27.00:midob 2006.258.00:25:27.14/onsource/TRACKING 2006.258.00:25:27.14/wx/21.94,1016.1,78 2006.258.00:25:27.28/cable/+6.4797E-03 2006.258.00:25:28.37/va/01,08,usb,yes,31,33 2006.258.00:25:28.37/va/02,07,usb,yes,33,34 2006.258.00:25:28.37/va/03,08,usb,yes,30,31 2006.258.00:25:28.37/va/04,07,usb,yes,34,36 2006.258.00:25:28.37/va/05,04,usb,yes,30,31 2006.258.00:25:28.37/va/06,04,usb,yes,34,33 2006.258.00:25:28.37/va/07,04,usb,yes,35,35 2006.258.00:25:28.37/va/08,04,usb,yes,29,36 2006.258.00:25:28.60/valo/01,524.99,yes,locked 2006.258.00:25:28.60/valo/02,534.99,yes,locked 2006.258.00:25:28.60/valo/03,564.99,yes,locked 2006.258.00:25:28.60/valo/04,624.99,yes,locked 2006.258.00:25:28.60/valo/05,734.99,yes,locked 2006.258.00:25:28.60/valo/06,814.99,yes,locked 2006.258.00:25:28.60/valo/07,864.99,yes,locked 2006.258.00:25:28.60/valo/08,884.99,yes,locked 2006.258.00:25:29.69/vb/01,04,usb,yes,31,28 2006.258.00:25:29.69/vb/02,05,usb,yes,29,29 2006.258.00:25:29.69/vb/03,04,usb,yes,30,33 2006.258.00:25:29.69/vb/04,05,usb,yes,30,29 2006.258.00:25:29.69/vb/05,04,usb,yes,27,29 2006.258.00:25:29.69/vb/06,04,usb,yes,31,27 2006.258.00:25:29.69/vb/07,04,usb,yes,31,31 2006.258.00:25:29.69/vb/08,04,usb,yes,28,32 2006.258.00:25:29.93/vblo/01,629.99,yes,locked 2006.258.00:25:29.93/vblo/02,634.99,yes,locked 2006.258.00:25:29.93/vblo/03,649.99,yes,locked 2006.258.00:25:29.93/vblo/04,679.99,yes,locked 2006.258.00:25:29.93/vblo/05,709.99,yes,locked 2006.258.00:25:29.93/vblo/06,719.99,yes,locked 2006.258.00:25:29.93/vblo/07,734.99,yes,locked 2006.258.00:25:29.93/vblo/08,744.99,yes,locked 2006.258.00:25:30.08/vabw/8 2006.258.00:25:30.23/vbbw/8 2006.258.00:25:30.32/xfe/off,on,15.0 2006.258.00:25:30.70/ifatt/23,28,28,28 2006.258.00:25:31.07/fmout-gps/S +4.56E-07 2006.258.00:25:31.11:!2006.258.00:26:17 2006.258.00:26:17.00:data_valid=off 2006.258.00:26:17.00:"et 2006.258.00:26:17.01:!+3s 2006.258.00:26:20.02:"tape 2006.258.00:26:20.02:postob 2006.258.00:26:20.25/cable/+6.4815E-03 2006.258.00:26:20.25/wx/21.96,1016.1,78 2006.258.00:26:20.31/fmout-gps/S +4.56E-07 2006.258.00:26:20.31:scan_name=258-0028,jd0609,110 2006.258.00:26:20.31:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.258.00:26:21.14#flagr#flagr/antenna,new-source 2006.258.00:26:21.14:checkk5 2006.258.00:26:21.50/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:26:21.90/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:26:22.32/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:26:22.72/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:26:23.11/chk_obsdata//k5ts1/T2580025??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.258.00:26:23.52/chk_obsdata//k5ts2/T2580025??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.258.00:26:23.92/chk_obsdata//k5ts3/T2580025??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.258.00:26:24.32/chk_obsdata//k5ts4/T2580025??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.258.00:26:25.04/k5log//k5ts1_log_newline 2006.258.00:26:25.74/k5log//k5ts2_log_newline 2006.258.00:26:26.46/k5log//k5ts3_log_newline 2006.258.00:26:27.16/k5log//k5ts4_log_newline 2006.258.00:26:27.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:26:27.19:setupk4=1 2006.258.00:26:27.19$setupk4/echo=on 2006.258.00:26:27.19$setupk4/pcalon 2006.258.00:26:27.19$pcalon/"no phase cal control is implemented here 2006.258.00:26:27.19$setupk4/"tpicd=stop 2006.258.00:26:27.19$setupk4/"rec=synch_on 2006.258.00:26:27.19$setupk4/"rec_mode=128 2006.258.00:26:27.19$setupk4/!* 2006.258.00:26:27.19$setupk4/recpk4 2006.258.00:26:27.19$recpk4/recpatch= 2006.258.00:26:27.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:26:27.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:26:27.20$setupk4/vck44 2006.258.00:26:27.20$vck44/valo=1,524.99 2006.258.00:26:27.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.00:26:27.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.00:26:27.20#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:27.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:27.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:27.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:27.20#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:26:27.20#ibcon#first serial, iclass 11, count 0 2006.258.00:26:27.20#ibcon#enter sib2, iclass 11, count 0 2006.258.00:26:27.20#ibcon#flushed, iclass 11, count 0 2006.258.00:26:27.20#ibcon#about to write, iclass 11, count 0 2006.258.00:26:27.20#ibcon#wrote, iclass 11, count 0 2006.258.00:26:27.20#ibcon#about to read 3, iclass 11, count 0 2006.258.00:26:27.21#ibcon#read 3, iclass 11, count 0 2006.258.00:26:27.21#ibcon#about to read 4, iclass 11, count 0 2006.258.00:26:27.21#ibcon#read 4, iclass 11, count 0 2006.258.00:26:27.21#ibcon#about to read 5, iclass 11, count 0 2006.258.00:26:27.21#ibcon#read 5, iclass 11, count 0 2006.258.00:26:27.21#ibcon#about to read 6, iclass 11, count 0 2006.258.00:26:27.21#ibcon#read 6, iclass 11, count 0 2006.258.00:26:27.21#ibcon#end of sib2, iclass 11, count 0 2006.258.00:26:27.21#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:26:27.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:26:27.21#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:26:27.21#ibcon#*before write, iclass 11, count 0 2006.258.00:26:27.21#ibcon#enter sib2, iclass 11, count 0 2006.258.00:26:27.21#ibcon#flushed, iclass 11, count 0 2006.258.00:26:27.21#ibcon#about to write, iclass 11, count 0 2006.258.00:26:27.21#ibcon#wrote, iclass 11, count 0 2006.258.00:26:27.21#ibcon#about to read 3, iclass 11, count 0 2006.258.00:26:27.26#ibcon#read 3, iclass 11, count 0 2006.258.00:26:27.26#ibcon#about to read 4, iclass 11, count 0 2006.258.00:26:27.26#ibcon#read 4, iclass 11, count 0 2006.258.00:26:27.26#ibcon#about to read 5, iclass 11, count 0 2006.258.00:26:27.26#ibcon#read 5, iclass 11, count 0 2006.258.00:26:27.26#ibcon#about to read 6, iclass 11, count 0 2006.258.00:26:27.26#ibcon#read 6, iclass 11, count 0 2006.258.00:26:27.26#ibcon#end of sib2, iclass 11, count 0 2006.258.00:26:27.26#ibcon#*after write, iclass 11, count 0 2006.258.00:26:27.26#ibcon#*before return 0, iclass 11, count 0 2006.258.00:26:27.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:27.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:27.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:26:27.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:26:27.26$vck44/va=1,8 2006.258.00:26:27.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.00:26:27.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.00:26:27.26#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:27.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:27.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:27.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:27.26#ibcon#enter wrdev, iclass 13, count 2 2006.258.00:26:27.26#ibcon#first serial, iclass 13, count 2 2006.258.00:26:27.26#ibcon#enter sib2, iclass 13, count 2 2006.258.00:26:27.26#ibcon#flushed, iclass 13, count 2 2006.258.00:26:27.26#ibcon#about to write, iclass 13, count 2 2006.258.00:26:27.26#ibcon#wrote, iclass 13, count 2 2006.258.00:26:27.26#ibcon#about to read 3, iclass 13, count 2 2006.258.00:26:27.28#ibcon#read 3, iclass 13, count 2 2006.258.00:26:27.28#ibcon#about to read 4, iclass 13, count 2 2006.258.00:26:27.28#ibcon#read 4, iclass 13, count 2 2006.258.00:26:27.28#ibcon#about to read 5, iclass 13, count 2 2006.258.00:26:27.28#ibcon#read 5, iclass 13, count 2 2006.258.00:26:27.28#ibcon#about to read 6, iclass 13, count 2 2006.258.00:26:27.28#ibcon#read 6, iclass 13, count 2 2006.258.00:26:27.28#ibcon#end of sib2, iclass 13, count 2 2006.258.00:26:27.28#ibcon#*mode == 0, iclass 13, count 2 2006.258.00:26:27.28#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.00:26:27.28#ibcon#[25=AT01-08\r\n] 2006.258.00:26:27.28#ibcon#*before write, iclass 13, count 2 2006.258.00:26:27.28#ibcon#enter sib2, iclass 13, count 2 2006.258.00:26:27.28#ibcon#flushed, iclass 13, count 2 2006.258.00:26:27.28#ibcon#about to write, iclass 13, count 2 2006.258.00:26:27.28#ibcon#wrote, iclass 13, count 2 2006.258.00:26:27.28#ibcon#about to read 3, iclass 13, count 2 2006.258.00:26:27.31#ibcon#read 3, iclass 13, count 2 2006.258.00:26:27.31#ibcon#about to read 4, iclass 13, count 2 2006.258.00:26:27.31#ibcon#read 4, iclass 13, count 2 2006.258.00:26:27.31#ibcon#about to read 5, iclass 13, count 2 2006.258.00:26:27.31#ibcon#read 5, iclass 13, count 2 2006.258.00:26:27.31#ibcon#about to read 6, iclass 13, count 2 2006.258.00:26:27.31#ibcon#read 6, iclass 13, count 2 2006.258.00:26:27.31#ibcon#end of sib2, iclass 13, count 2 2006.258.00:26:27.31#ibcon#*after write, iclass 13, count 2 2006.258.00:26:27.31#ibcon#*before return 0, iclass 13, count 2 2006.258.00:26:27.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:27.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:27.31#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.00:26:27.31#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:27.31#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:27.43#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:27.43#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:27.43#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:26:27.43#ibcon#first serial, iclass 13, count 0 2006.258.00:26:27.43#ibcon#enter sib2, iclass 13, count 0 2006.258.00:26:27.43#ibcon#flushed, iclass 13, count 0 2006.258.00:26:27.43#ibcon#about to write, iclass 13, count 0 2006.258.00:26:27.43#ibcon#wrote, iclass 13, count 0 2006.258.00:26:27.43#ibcon#about to read 3, iclass 13, count 0 2006.258.00:26:27.45#ibcon#read 3, iclass 13, count 0 2006.258.00:26:27.45#ibcon#about to read 4, iclass 13, count 0 2006.258.00:26:27.45#ibcon#read 4, iclass 13, count 0 2006.258.00:26:27.45#ibcon#about to read 5, iclass 13, count 0 2006.258.00:26:27.45#ibcon#read 5, iclass 13, count 0 2006.258.00:26:27.45#ibcon#about to read 6, iclass 13, count 0 2006.258.00:26:27.45#ibcon#read 6, iclass 13, count 0 2006.258.00:26:27.45#ibcon#end of sib2, iclass 13, count 0 2006.258.00:26:27.45#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:26:27.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:26:27.45#ibcon#[25=USB\r\n] 2006.258.00:26:27.45#ibcon#*before write, iclass 13, count 0 2006.258.00:26:27.45#ibcon#enter sib2, iclass 13, count 0 2006.258.00:26:27.45#ibcon#flushed, iclass 13, count 0 2006.258.00:26:27.45#ibcon#about to write, iclass 13, count 0 2006.258.00:26:27.45#ibcon#wrote, iclass 13, count 0 2006.258.00:26:27.45#ibcon#about to read 3, iclass 13, count 0 2006.258.00:26:27.48#ibcon#read 3, iclass 13, count 0 2006.258.00:26:27.48#ibcon#about to read 4, iclass 13, count 0 2006.258.00:26:27.48#ibcon#read 4, iclass 13, count 0 2006.258.00:26:27.48#ibcon#about to read 5, iclass 13, count 0 2006.258.00:26:27.48#ibcon#read 5, iclass 13, count 0 2006.258.00:26:27.48#ibcon#about to read 6, iclass 13, count 0 2006.258.00:26:27.48#ibcon#read 6, iclass 13, count 0 2006.258.00:26:27.48#ibcon#end of sib2, iclass 13, count 0 2006.258.00:26:27.48#ibcon#*after write, iclass 13, count 0 2006.258.00:26:27.48#ibcon#*before return 0, iclass 13, count 0 2006.258.00:26:27.48#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:27.48#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:27.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:26:27.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:26:27.48$vck44/valo=2,534.99 2006.258.00:26:27.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.00:26:27.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.00:26:27.48#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:27.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:27.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:27.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:27.48#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:26:27.48#ibcon#first serial, iclass 15, count 0 2006.258.00:26:27.48#ibcon#enter sib2, iclass 15, count 0 2006.258.00:26:27.48#ibcon#flushed, iclass 15, count 0 2006.258.00:26:27.48#ibcon#about to write, iclass 15, count 0 2006.258.00:26:27.48#ibcon#wrote, iclass 15, count 0 2006.258.00:26:27.48#ibcon#about to read 3, iclass 15, count 0 2006.258.00:26:27.50#ibcon#read 3, iclass 15, count 0 2006.258.00:26:27.50#ibcon#about to read 4, iclass 15, count 0 2006.258.00:26:27.50#ibcon#read 4, iclass 15, count 0 2006.258.00:26:27.50#ibcon#about to read 5, iclass 15, count 0 2006.258.00:26:27.50#ibcon#read 5, iclass 15, count 0 2006.258.00:26:27.50#ibcon#about to read 6, iclass 15, count 0 2006.258.00:26:27.50#ibcon#read 6, iclass 15, count 0 2006.258.00:26:27.50#ibcon#end of sib2, iclass 15, count 0 2006.258.00:26:27.50#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:26:27.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:26:27.50#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:26:27.50#ibcon#*before write, iclass 15, count 0 2006.258.00:26:27.50#ibcon#enter sib2, iclass 15, count 0 2006.258.00:26:27.50#ibcon#flushed, iclass 15, count 0 2006.258.00:26:27.50#ibcon#about to write, iclass 15, count 0 2006.258.00:26:27.50#ibcon#wrote, iclass 15, count 0 2006.258.00:26:27.50#ibcon#about to read 3, iclass 15, count 0 2006.258.00:26:27.54#abcon#<5=/02 1.4 4.3 21.97 781016.2\r\n> 2006.258.00:26:27.54#ibcon#read 3, iclass 15, count 0 2006.258.00:26:27.54#ibcon#about to read 4, iclass 15, count 0 2006.258.00:26:27.54#ibcon#read 4, iclass 15, count 0 2006.258.00:26:27.54#ibcon#about to read 5, iclass 15, count 0 2006.258.00:26:27.54#ibcon#read 5, iclass 15, count 0 2006.258.00:26:27.54#ibcon#about to read 6, iclass 15, count 0 2006.258.00:26:27.54#ibcon#read 6, iclass 15, count 0 2006.258.00:26:27.54#ibcon#end of sib2, iclass 15, count 0 2006.258.00:26:27.54#ibcon#*after write, iclass 15, count 0 2006.258.00:26:27.54#ibcon#*before return 0, iclass 15, count 0 2006.258.00:26:27.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:27.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:27.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:26:27.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:26:27.54$vck44/va=2,7 2006.258.00:26:27.54#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.00:26:27.54#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.00:26:27.54#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:27.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:26:27.56#abcon#{5=INTERFACE CLEAR} 2006.258.00:26:27.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:26:27.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:26:27.60#ibcon#enter wrdev, iclass 20, count 2 2006.258.00:26:27.60#ibcon#first serial, iclass 20, count 2 2006.258.00:26:27.60#ibcon#enter sib2, iclass 20, count 2 2006.258.00:26:27.60#ibcon#flushed, iclass 20, count 2 2006.258.00:26:27.60#ibcon#about to write, iclass 20, count 2 2006.258.00:26:27.60#ibcon#wrote, iclass 20, count 2 2006.258.00:26:27.60#ibcon#about to read 3, iclass 20, count 2 2006.258.00:26:27.62#ibcon#read 3, iclass 20, count 2 2006.258.00:26:27.62#ibcon#about to read 4, iclass 20, count 2 2006.258.00:26:27.62#ibcon#read 4, iclass 20, count 2 2006.258.00:26:27.62#ibcon#about to read 5, iclass 20, count 2 2006.258.00:26:27.62#ibcon#read 5, iclass 20, count 2 2006.258.00:26:27.62#ibcon#about to read 6, iclass 20, count 2 2006.258.00:26:27.62#ibcon#read 6, iclass 20, count 2 2006.258.00:26:27.62#ibcon#end of sib2, iclass 20, count 2 2006.258.00:26:27.62#ibcon#*mode == 0, iclass 20, count 2 2006.258.00:26:27.62#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.00:26:27.62#ibcon#[25=AT02-07\r\n] 2006.258.00:26:27.62#ibcon#*before write, iclass 20, count 2 2006.258.00:26:27.62#ibcon#enter sib2, iclass 20, count 2 2006.258.00:26:27.62#ibcon#flushed, iclass 20, count 2 2006.258.00:26:27.62#ibcon#about to write, iclass 20, count 2 2006.258.00:26:27.62#ibcon#wrote, iclass 20, count 2 2006.258.00:26:27.62#ibcon#about to read 3, iclass 20, count 2 2006.258.00:26:27.62#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:26:27.65#ibcon#read 3, iclass 20, count 2 2006.258.00:26:27.65#ibcon#about to read 4, iclass 20, count 2 2006.258.00:26:27.65#ibcon#read 4, iclass 20, count 2 2006.258.00:26:27.65#ibcon#about to read 5, iclass 20, count 2 2006.258.00:26:27.65#ibcon#read 5, iclass 20, count 2 2006.258.00:26:27.65#ibcon#about to read 6, iclass 20, count 2 2006.258.00:26:27.65#ibcon#read 6, iclass 20, count 2 2006.258.00:26:27.65#ibcon#end of sib2, iclass 20, count 2 2006.258.00:26:27.65#ibcon#*after write, iclass 20, count 2 2006.258.00:26:27.65#ibcon#*before return 0, iclass 20, count 2 2006.258.00:26:27.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:26:27.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:26:27.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.00:26:27.65#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:27.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:26:27.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:26:27.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:26:27.77#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:26:27.77#ibcon#first serial, iclass 20, count 0 2006.258.00:26:27.77#ibcon#enter sib2, iclass 20, count 0 2006.258.00:26:27.77#ibcon#flushed, iclass 20, count 0 2006.258.00:26:27.77#ibcon#about to write, iclass 20, count 0 2006.258.00:26:27.77#ibcon#wrote, iclass 20, count 0 2006.258.00:26:27.77#ibcon#about to read 3, iclass 20, count 0 2006.258.00:26:27.79#ibcon#read 3, iclass 20, count 0 2006.258.00:26:27.79#ibcon#about to read 4, iclass 20, count 0 2006.258.00:26:27.79#ibcon#read 4, iclass 20, count 0 2006.258.00:26:27.79#ibcon#about to read 5, iclass 20, count 0 2006.258.00:26:27.79#ibcon#read 5, iclass 20, count 0 2006.258.00:26:27.79#ibcon#about to read 6, iclass 20, count 0 2006.258.00:26:27.79#ibcon#read 6, iclass 20, count 0 2006.258.00:26:27.79#ibcon#end of sib2, iclass 20, count 0 2006.258.00:26:27.79#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:26:27.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:26:27.79#ibcon#[25=USB\r\n] 2006.258.00:26:27.79#ibcon#*before write, iclass 20, count 0 2006.258.00:26:27.79#ibcon#enter sib2, iclass 20, count 0 2006.258.00:26:27.79#ibcon#flushed, iclass 20, count 0 2006.258.00:26:27.79#ibcon#about to write, iclass 20, count 0 2006.258.00:26:27.79#ibcon#wrote, iclass 20, count 0 2006.258.00:26:27.79#ibcon#about to read 3, iclass 20, count 0 2006.258.00:26:27.82#ibcon#read 3, iclass 20, count 0 2006.258.00:26:27.82#ibcon#about to read 4, iclass 20, count 0 2006.258.00:26:27.82#ibcon#read 4, iclass 20, count 0 2006.258.00:26:27.82#ibcon#about to read 5, iclass 20, count 0 2006.258.00:26:27.82#ibcon#read 5, iclass 20, count 0 2006.258.00:26:27.82#ibcon#about to read 6, iclass 20, count 0 2006.258.00:26:27.82#ibcon#read 6, iclass 20, count 0 2006.258.00:26:27.82#ibcon#end of sib2, iclass 20, count 0 2006.258.00:26:27.82#ibcon#*after write, iclass 20, count 0 2006.258.00:26:27.82#ibcon#*before return 0, iclass 20, count 0 2006.258.00:26:27.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:26:27.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:26:27.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:26:27.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:26:27.82$vck44/valo=3,564.99 2006.258.00:26:27.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.00:26:27.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.00:26:27.82#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:27.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:27.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:27.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:27.82#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:26:27.82#ibcon#first serial, iclass 23, count 0 2006.258.00:26:27.82#ibcon#enter sib2, iclass 23, count 0 2006.258.00:26:27.82#ibcon#flushed, iclass 23, count 0 2006.258.00:26:27.82#ibcon#about to write, iclass 23, count 0 2006.258.00:26:27.82#ibcon#wrote, iclass 23, count 0 2006.258.00:26:27.82#ibcon#about to read 3, iclass 23, count 0 2006.258.00:26:27.84#ibcon#read 3, iclass 23, count 0 2006.258.00:26:27.84#ibcon#about to read 4, iclass 23, count 0 2006.258.00:26:27.84#ibcon#read 4, iclass 23, count 0 2006.258.00:26:27.84#ibcon#about to read 5, iclass 23, count 0 2006.258.00:26:27.84#ibcon#read 5, iclass 23, count 0 2006.258.00:26:27.84#ibcon#about to read 6, iclass 23, count 0 2006.258.00:26:27.84#ibcon#read 6, iclass 23, count 0 2006.258.00:26:27.84#ibcon#end of sib2, iclass 23, count 0 2006.258.00:26:27.84#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:26:27.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:26:27.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:26:27.84#ibcon#*before write, iclass 23, count 0 2006.258.00:26:27.84#ibcon#enter sib2, iclass 23, count 0 2006.258.00:26:27.84#ibcon#flushed, iclass 23, count 0 2006.258.00:26:27.84#ibcon#about to write, iclass 23, count 0 2006.258.00:26:27.84#ibcon#wrote, iclass 23, count 0 2006.258.00:26:27.84#ibcon#about to read 3, iclass 23, count 0 2006.258.00:26:27.88#ibcon#read 3, iclass 23, count 0 2006.258.00:26:27.88#ibcon#about to read 4, iclass 23, count 0 2006.258.00:26:27.88#ibcon#read 4, iclass 23, count 0 2006.258.00:26:27.88#ibcon#about to read 5, iclass 23, count 0 2006.258.00:26:27.88#ibcon#read 5, iclass 23, count 0 2006.258.00:26:27.88#ibcon#about to read 6, iclass 23, count 0 2006.258.00:26:27.88#ibcon#read 6, iclass 23, count 0 2006.258.00:26:27.88#ibcon#end of sib2, iclass 23, count 0 2006.258.00:26:27.88#ibcon#*after write, iclass 23, count 0 2006.258.00:26:27.88#ibcon#*before return 0, iclass 23, count 0 2006.258.00:26:27.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:27.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:27.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:26:27.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:26:27.88$vck44/va=3,8 2006.258.00:26:27.88#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.258.00:26:27.88#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.258.00:26:27.88#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:27.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:27.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:27.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:27.94#ibcon#enter wrdev, iclass 25, count 2 2006.258.00:26:27.94#ibcon#first serial, iclass 25, count 2 2006.258.00:26:27.94#ibcon#enter sib2, iclass 25, count 2 2006.258.00:26:27.94#ibcon#flushed, iclass 25, count 2 2006.258.00:26:27.94#ibcon#about to write, iclass 25, count 2 2006.258.00:26:27.94#ibcon#wrote, iclass 25, count 2 2006.258.00:26:27.94#ibcon#about to read 3, iclass 25, count 2 2006.258.00:26:27.96#ibcon#read 3, iclass 25, count 2 2006.258.00:26:27.96#ibcon#about to read 4, iclass 25, count 2 2006.258.00:26:27.96#ibcon#read 4, iclass 25, count 2 2006.258.00:26:27.96#ibcon#about to read 5, iclass 25, count 2 2006.258.00:26:27.96#ibcon#read 5, iclass 25, count 2 2006.258.00:26:27.96#ibcon#about to read 6, iclass 25, count 2 2006.258.00:26:27.96#ibcon#read 6, iclass 25, count 2 2006.258.00:26:27.96#ibcon#end of sib2, iclass 25, count 2 2006.258.00:26:27.96#ibcon#*mode == 0, iclass 25, count 2 2006.258.00:26:27.96#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.258.00:26:27.96#ibcon#[25=AT03-08\r\n] 2006.258.00:26:27.96#ibcon#*before write, iclass 25, count 2 2006.258.00:26:27.96#ibcon#enter sib2, iclass 25, count 2 2006.258.00:26:27.96#ibcon#flushed, iclass 25, count 2 2006.258.00:26:27.96#ibcon#about to write, iclass 25, count 2 2006.258.00:26:27.96#ibcon#wrote, iclass 25, count 2 2006.258.00:26:27.96#ibcon#about to read 3, iclass 25, count 2 2006.258.00:26:27.99#ibcon#read 3, iclass 25, count 2 2006.258.00:26:27.99#ibcon#about to read 4, iclass 25, count 2 2006.258.00:26:27.99#ibcon#read 4, iclass 25, count 2 2006.258.00:26:27.99#ibcon#about to read 5, iclass 25, count 2 2006.258.00:26:27.99#ibcon#read 5, iclass 25, count 2 2006.258.00:26:27.99#ibcon#about to read 6, iclass 25, count 2 2006.258.00:26:27.99#ibcon#read 6, iclass 25, count 2 2006.258.00:26:27.99#ibcon#end of sib2, iclass 25, count 2 2006.258.00:26:27.99#ibcon#*after write, iclass 25, count 2 2006.258.00:26:27.99#ibcon#*before return 0, iclass 25, count 2 2006.258.00:26:27.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:27.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:27.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.258.00:26:27.99#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:27.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:28.11#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:28.11#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:28.11#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:26:28.11#ibcon#first serial, iclass 25, count 0 2006.258.00:26:28.11#ibcon#enter sib2, iclass 25, count 0 2006.258.00:26:28.11#ibcon#flushed, iclass 25, count 0 2006.258.00:26:28.11#ibcon#about to write, iclass 25, count 0 2006.258.00:26:28.11#ibcon#wrote, iclass 25, count 0 2006.258.00:26:28.11#ibcon#about to read 3, iclass 25, count 0 2006.258.00:26:28.13#ibcon#read 3, iclass 25, count 0 2006.258.00:26:28.13#ibcon#about to read 4, iclass 25, count 0 2006.258.00:26:28.13#ibcon#read 4, iclass 25, count 0 2006.258.00:26:28.13#ibcon#about to read 5, iclass 25, count 0 2006.258.00:26:28.13#ibcon#read 5, iclass 25, count 0 2006.258.00:26:28.13#ibcon#about to read 6, iclass 25, count 0 2006.258.00:26:28.13#ibcon#read 6, iclass 25, count 0 2006.258.00:26:28.13#ibcon#end of sib2, iclass 25, count 0 2006.258.00:26:28.13#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:26:28.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:26:28.13#ibcon#[25=USB\r\n] 2006.258.00:26:28.13#ibcon#*before write, iclass 25, count 0 2006.258.00:26:28.13#ibcon#enter sib2, iclass 25, count 0 2006.258.00:26:28.13#ibcon#flushed, iclass 25, count 0 2006.258.00:26:28.13#ibcon#about to write, iclass 25, count 0 2006.258.00:26:28.13#ibcon#wrote, iclass 25, count 0 2006.258.00:26:28.13#ibcon#about to read 3, iclass 25, count 0 2006.258.00:26:28.16#ibcon#read 3, iclass 25, count 0 2006.258.00:26:28.16#ibcon#about to read 4, iclass 25, count 0 2006.258.00:26:28.16#ibcon#read 4, iclass 25, count 0 2006.258.00:26:28.16#ibcon#about to read 5, iclass 25, count 0 2006.258.00:26:28.16#ibcon#read 5, iclass 25, count 0 2006.258.00:26:28.16#ibcon#about to read 6, iclass 25, count 0 2006.258.00:26:28.16#ibcon#read 6, iclass 25, count 0 2006.258.00:26:28.16#ibcon#end of sib2, iclass 25, count 0 2006.258.00:26:28.16#ibcon#*after write, iclass 25, count 0 2006.258.00:26:28.16#ibcon#*before return 0, iclass 25, count 0 2006.258.00:26:28.16#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:28.16#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:28.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:26:28.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:26:28.16$vck44/valo=4,624.99 2006.258.00:26:28.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.00:26:28.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.00:26:28.16#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:28.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:28.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:28.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:28.16#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:26:28.16#ibcon#first serial, iclass 27, count 0 2006.258.00:26:28.16#ibcon#enter sib2, iclass 27, count 0 2006.258.00:26:28.16#ibcon#flushed, iclass 27, count 0 2006.258.00:26:28.16#ibcon#about to write, iclass 27, count 0 2006.258.00:26:28.16#ibcon#wrote, iclass 27, count 0 2006.258.00:26:28.16#ibcon#about to read 3, iclass 27, count 0 2006.258.00:26:28.18#ibcon#read 3, iclass 27, count 0 2006.258.00:26:28.18#ibcon#about to read 4, iclass 27, count 0 2006.258.00:26:28.18#ibcon#read 4, iclass 27, count 0 2006.258.00:26:28.18#ibcon#about to read 5, iclass 27, count 0 2006.258.00:26:28.18#ibcon#read 5, iclass 27, count 0 2006.258.00:26:28.18#ibcon#about to read 6, iclass 27, count 0 2006.258.00:26:28.18#ibcon#read 6, iclass 27, count 0 2006.258.00:26:28.18#ibcon#end of sib2, iclass 27, count 0 2006.258.00:26:28.18#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:26:28.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:26:28.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:26:28.18#ibcon#*before write, iclass 27, count 0 2006.258.00:26:28.18#ibcon#enter sib2, iclass 27, count 0 2006.258.00:26:28.18#ibcon#flushed, iclass 27, count 0 2006.258.00:26:28.18#ibcon#about to write, iclass 27, count 0 2006.258.00:26:28.18#ibcon#wrote, iclass 27, count 0 2006.258.00:26:28.18#ibcon#about to read 3, iclass 27, count 0 2006.258.00:26:28.22#ibcon#read 3, iclass 27, count 0 2006.258.00:26:28.22#ibcon#about to read 4, iclass 27, count 0 2006.258.00:26:28.22#ibcon#read 4, iclass 27, count 0 2006.258.00:26:28.22#ibcon#about to read 5, iclass 27, count 0 2006.258.00:26:28.22#ibcon#read 5, iclass 27, count 0 2006.258.00:26:28.22#ibcon#about to read 6, iclass 27, count 0 2006.258.00:26:28.22#ibcon#read 6, iclass 27, count 0 2006.258.00:26:28.22#ibcon#end of sib2, iclass 27, count 0 2006.258.00:26:28.22#ibcon#*after write, iclass 27, count 0 2006.258.00:26:28.22#ibcon#*before return 0, iclass 27, count 0 2006.258.00:26:28.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:28.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:28.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:26:28.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:26:28.22$vck44/va=4,7 2006.258.00:26:28.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.00:26:28.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.00:26:28.22#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:28.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:28.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:28.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:28.28#ibcon#enter wrdev, iclass 29, count 2 2006.258.00:26:28.28#ibcon#first serial, iclass 29, count 2 2006.258.00:26:28.28#ibcon#enter sib2, iclass 29, count 2 2006.258.00:26:28.28#ibcon#flushed, iclass 29, count 2 2006.258.00:26:28.28#ibcon#about to write, iclass 29, count 2 2006.258.00:26:28.28#ibcon#wrote, iclass 29, count 2 2006.258.00:26:28.28#ibcon#about to read 3, iclass 29, count 2 2006.258.00:26:28.30#ibcon#read 3, iclass 29, count 2 2006.258.00:26:28.30#ibcon#about to read 4, iclass 29, count 2 2006.258.00:26:28.30#ibcon#read 4, iclass 29, count 2 2006.258.00:26:28.30#ibcon#about to read 5, iclass 29, count 2 2006.258.00:26:28.30#ibcon#read 5, iclass 29, count 2 2006.258.00:26:28.30#ibcon#about to read 6, iclass 29, count 2 2006.258.00:26:28.30#ibcon#read 6, iclass 29, count 2 2006.258.00:26:28.30#ibcon#end of sib2, iclass 29, count 2 2006.258.00:26:28.30#ibcon#*mode == 0, iclass 29, count 2 2006.258.00:26:28.30#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.00:26:28.30#ibcon#[25=AT04-07\r\n] 2006.258.00:26:28.30#ibcon#*before write, iclass 29, count 2 2006.258.00:26:28.30#ibcon#enter sib2, iclass 29, count 2 2006.258.00:26:28.30#ibcon#flushed, iclass 29, count 2 2006.258.00:26:28.30#ibcon#about to write, iclass 29, count 2 2006.258.00:26:28.30#ibcon#wrote, iclass 29, count 2 2006.258.00:26:28.30#ibcon#about to read 3, iclass 29, count 2 2006.258.00:26:28.33#ibcon#read 3, iclass 29, count 2 2006.258.00:26:28.33#ibcon#about to read 4, iclass 29, count 2 2006.258.00:26:28.33#ibcon#read 4, iclass 29, count 2 2006.258.00:26:28.33#ibcon#about to read 5, iclass 29, count 2 2006.258.00:26:28.33#ibcon#read 5, iclass 29, count 2 2006.258.00:26:28.33#ibcon#about to read 6, iclass 29, count 2 2006.258.00:26:28.33#ibcon#read 6, iclass 29, count 2 2006.258.00:26:28.33#ibcon#end of sib2, iclass 29, count 2 2006.258.00:26:28.33#ibcon#*after write, iclass 29, count 2 2006.258.00:26:28.33#ibcon#*before return 0, iclass 29, count 2 2006.258.00:26:28.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:28.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:28.33#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.00:26:28.33#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:28.33#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:28.45#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:28.45#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:28.45#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:26:28.45#ibcon#first serial, iclass 29, count 0 2006.258.00:26:28.45#ibcon#enter sib2, iclass 29, count 0 2006.258.00:26:28.45#ibcon#flushed, iclass 29, count 0 2006.258.00:26:28.45#ibcon#about to write, iclass 29, count 0 2006.258.00:26:28.45#ibcon#wrote, iclass 29, count 0 2006.258.00:26:28.45#ibcon#about to read 3, iclass 29, count 0 2006.258.00:26:28.47#ibcon#read 3, iclass 29, count 0 2006.258.00:26:28.47#ibcon#about to read 4, iclass 29, count 0 2006.258.00:26:28.47#ibcon#read 4, iclass 29, count 0 2006.258.00:26:28.47#ibcon#about to read 5, iclass 29, count 0 2006.258.00:26:28.47#ibcon#read 5, iclass 29, count 0 2006.258.00:26:28.47#ibcon#about to read 6, iclass 29, count 0 2006.258.00:26:28.47#ibcon#read 6, iclass 29, count 0 2006.258.00:26:28.47#ibcon#end of sib2, iclass 29, count 0 2006.258.00:26:28.47#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:26:28.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:26:28.47#ibcon#[25=USB\r\n] 2006.258.00:26:28.47#ibcon#*before write, iclass 29, count 0 2006.258.00:26:28.47#ibcon#enter sib2, iclass 29, count 0 2006.258.00:26:28.47#ibcon#flushed, iclass 29, count 0 2006.258.00:26:28.47#ibcon#about to write, iclass 29, count 0 2006.258.00:26:28.47#ibcon#wrote, iclass 29, count 0 2006.258.00:26:28.47#ibcon#about to read 3, iclass 29, count 0 2006.258.00:26:28.50#ibcon#read 3, iclass 29, count 0 2006.258.00:26:28.50#ibcon#about to read 4, iclass 29, count 0 2006.258.00:26:28.50#ibcon#read 4, iclass 29, count 0 2006.258.00:26:28.50#ibcon#about to read 5, iclass 29, count 0 2006.258.00:26:28.50#ibcon#read 5, iclass 29, count 0 2006.258.00:26:28.50#ibcon#about to read 6, iclass 29, count 0 2006.258.00:26:28.50#ibcon#read 6, iclass 29, count 0 2006.258.00:26:28.50#ibcon#end of sib2, iclass 29, count 0 2006.258.00:26:28.50#ibcon#*after write, iclass 29, count 0 2006.258.00:26:28.50#ibcon#*before return 0, iclass 29, count 0 2006.258.00:26:28.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:28.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:28.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:26:28.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:26:28.50$vck44/valo=5,734.99 2006.258.00:26:28.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.258.00:26:28.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.258.00:26:28.50#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:28.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:28.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:28.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:28.50#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:26:28.50#ibcon#first serial, iclass 31, count 0 2006.258.00:26:28.50#ibcon#enter sib2, iclass 31, count 0 2006.258.00:26:28.50#ibcon#flushed, iclass 31, count 0 2006.258.00:26:28.50#ibcon#about to write, iclass 31, count 0 2006.258.00:26:28.50#ibcon#wrote, iclass 31, count 0 2006.258.00:26:28.50#ibcon#about to read 3, iclass 31, count 0 2006.258.00:26:28.52#ibcon#read 3, iclass 31, count 0 2006.258.00:26:28.52#ibcon#about to read 4, iclass 31, count 0 2006.258.00:26:28.52#ibcon#read 4, iclass 31, count 0 2006.258.00:26:28.52#ibcon#about to read 5, iclass 31, count 0 2006.258.00:26:28.52#ibcon#read 5, iclass 31, count 0 2006.258.00:26:28.52#ibcon#about to read 6, iclass 31, count 0 2006.258.00:26:28.52#ibcon#read 6, iclass 31, count 0 2006.258.00:26:28.52#ibcon#end of sib2, iclass 31, count 0 2006.258.00:26:28.52#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:26:28.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:26:28.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:26:28.52#ibcon#*before write, iclass 31, count 0 2006.258.00:26:28.52#ibcon#enter sib2, iclass 31, count 0 2006.258.00:26:28.52#ibcon#flushed, iclass 31, count 0 2006.258.00:26:28.52#ibcon#about to write, iclass 31, count 0 2006.258.00:26:28.52#ibcon#wrote, iclass 31, count 0 2006.258.00:26:28.52#ibcon#about to read 3, iclass 31, count 0 2006.258.00:26:28.56#ibcon#read 3, iclass 31, count 0 2006.258.00:26:28.56#ibcon#about to read 4, iclass 31, count 0 2006.258.00:26:28.56#ibcon#read 4, iclass 31, count 0 2006.258.00:26:28.56#ibcon#about to read 5, iclass 31, count 0 2006.258.00:26:28.56#ibcon#read 5, iclass 31, count 0 2006.258.00:26:28.56#ibcon#about to read 6, iclass 31, count 0 2006.258.00:26:28.56#ibcon#read 6, iclass 31, count 0 2006.258.00:26:28.56#ibcon#end of sib2, iclass 31, count 0 2006.258.00:26:28.56#ibcon#*after write, iclass 31, count 0 2006.258.00:26:28.56#ibcon#*before return 0, iclass 31, count 0 2006.258.00:26:28.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:28.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:28.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:26:28.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:26:28.56$vck44/va=5,4 2006.258.00:26:28.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.00:26:28.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.00:26:28.56#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:28.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:28.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:28.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:28.62#ibcon#enter wrdev, iclass 33, count 2 2006.258.00:26:28.62#ibcon#first serial, iclass 33, count 2 2006.258.00:26:28.62#ibcon#enter sib2, iclass 33, count 2 2006.258.00:26:28.62#ibcon#flushed, iclass 33, count 2 2006.258.00:26:28.62#ibcon#about to write, iclass 33, count 2 2006.258.00:26:28.62#ibcon#wrote, iclass 33, count 2 2006.258.00:26:28.62#ibcon#about to read 3, iclass 33, count 2 2006.258.00:26:28.64#ibcon#read 3, iclass 33, count 2 2006.258.00:26:28.64#ibcon#about to read 4, iclass 33, count 2 2006.258.00:26:28.64#ibcon#read 4, iclass 33, count 2 2006.258.00:26:28.64#ibcon#about to read 5, iclass 33, count 2 2006.258.00:26:28.64#ibcon#read 5, iclass 33, count 2 2006.258.00:26:28.64#ibcon#about to read 6, iclass 33, count 2 2006.258.00:26:28.64#ibcon#read 6, iclass 33, count 2 2006.258.00:26:28.64#ibcon#end of sib2, iclass 33, count 2 2006.258.00:26:28.64#ibcon#*mode == 0, iclass 33, count 2 2006.258.00:26:28.64#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.00:26:28.64#ibcon#[25=AT05-04\r\n] 2006.258.00:26:28.64#ibcon#*before write, iclass 33, count 2 2006.258.00:26:28.64#ibcon#enter sib2, iclass 33, count 2 2006.258.00:26:28.64#ibcon#flushed, iclass 33, count 2 2006.258.00:26:28.64#ibcon#about to write, iclass 33, count 2 2006.258.00:26:28.64#ibcon#wrote, iclass 33, count 2 2006.258.00:26:28.64#ibcon#about to read 3, iclass 33, count 2 2006.258.00:26:28.67#ibcon#read 3, iclass 33, count 2 2006.258.00:26:28.67#ibcon#about to read 4, iclass 33, count 2 2006.258.00:26:28.67#ibcon#read 4, iclass 33, count 2 2006.258.00:26:28.67#ibcon#about to read 5, iclass 33, count 2 2006.258.00:26:28.67#ibcon#read 5, iclass 33, count 2 2006.258.00:26:28.67#ibcon#about to read 6, iclass 33, count 2 2006.258.00:26:28.67#ibcon#read 6, iclass 33, count 2 2006.258.00:26:28.67#ibcon#end of sib2, iclass 33, count 2 2006.258.00:26:28.67#ibcon#*after write, iclass 33, count 2 2006.258.00:26:28.67#ibcon#*before return 0, iclass 33, count 2 2006.258.00:26:28.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:28.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:28.67#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.00:26:28.67#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:28.67#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:28.79#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:28.79#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:28.79#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:26:28.79#ibcon#first serial, iclass 33, count 0 2006.258.00:26:28.79#ibcon#enter sib2, iclass 33, count 0 2006.258.00:26:28.79#ibcon#flushed, iclass 33, count 0 2006.258.00:26:28.79#ibcon#about to write, iclass 33, count 0 2006.258.00:26:28.79#ibcon#wrote, iclass 33, count 0 2006.258.00:26:28.79#ibcon#about to read 3, iclass 33, count 0 2006.258.00:26:28.81#ibcon#read 3, iclass 33, count 0 2006.258.00:26:28.81#ibcon#about to read 4, iclass 33, count 0 2006.258.00:26:28.81#ibcon#read 4, iclass 33, count 0 2006.258.00:26:28.81#ibcon#about to read 5, iclass 33, count 0 2006.258.00:26:28.81#ibcon#read 5, iclass 33, count 0 2006.258.00:26:28.81#ibcon#about to read 6, iclass 33, count 0 2006.258.00:26:28.81#ibcon#read 6, iclass 33, count 0 2006.258.00:26:28.81#ibcon#end of sib2, iclass 33, count 0 2006.258.00:26:28.81#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:26:28.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:26:28.81#ibcon#[25=USB\r\n] 2006.258.00:26:28.81#ibcon#*before write, iclass 33, count 0 2006.258.00:26:28.81#ibcon#enter sib2, iclass 33, count 0 2006.258.00:26:28.81#ibcon#flushed, iclass 33, count 0 2006.258.00:26:28.81#ibcon#about to write, iclass 33, count 0 2006.258.00:26:28.81#ibcon#wrote, iclass 33, count 0 2006.258.00:26:28.81#ibcon#about to read 3, iclass 33, count 0 2006.258.00:26:28.84#ibcon#read 3, iclass 33, count 0 2006.258.00:26:28.84#ibcon#about to read 4, iclass 33, count 0 2006.258.00:26:28.84#ibcon#read 4, iclass 33, count 0 2006.258.00:26:28.84#ibcon#about to read 5, iclass 33, count 0 2006.258.00:26:28.84#ibcon#read 5, iclass 33, count 0 2006.258.00:26:28.84#ibcon#about to read 6, iclass 33, count 0 2006.258.00:26:28.84#ibcon#read 6, iclass 33, count 0 2006.258.00:26:28.84#ibcon#end of sib2, iclass 33, count 0 2006.258.00:26:28.84#ibcon#*after write, iclass 33, count 0 2006.258.00:26:28.84#ibcon#*before return 0, iclass 33, count 0 2006.258.00:26:28.84#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:28.84#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:28.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:26:28.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:26:28.84$vck44/valo=6,814.99 2006.258.00:26:28.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.00:26:28.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.00:26:28.84#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:28.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:28.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:28.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:28.84#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:26:28.84#ibcon#first serial, iclass 35, count 0 2006.258.00:26:28.84#ibcon#enter sib2, iclass 35, count 0 2006.258.00:26:28.84#ibcon#flushed, iclass 35, count 0 2006.258.00:26:28.84#ibcon#about to write, iclass 35, count 0 2006.258.00:26:28.84#ibcon#wrote, iclass 35, count 0 2006.258.00:26:28.84#ibcon#about to read 3, iclass 35, count 0 2006.258.00:26:28.86#ibcon#read 3, iclass 35, count 0 2006.258.00:26:28.86#ibcon#about to read 4, iclass 35, count 0 2006.258.00:26:28.86#ibcon#read 4, iclass 35, count 0 2006.258.00:26:28.86#ibcon#about to read 5, iclass 35, count 0 2006.258.00:26:28.86#ibcon#read 5, iclass 35, count 0 2006.258.00:26:28.86#ibcon#about to read 6, iclass 35, count 0 2006.258.00:26:28.86#ibcon#read 6, iclass 35, count 0 2006.258.00:26:28.86#ibcon#end of sib2, iclass 35, count 0 2006.258.00:26:28.86#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:26:28.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:26:28.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:26:28.86#ibcon#*before write, iclass 35, count 0 2006.258.00:26:28.86#ibcon#enter sib2, iclass 35, count 0 2006.258.00:26:28.86#ibcon#flushed, iclass 35, count 0 2006.258.00:26:28.86#ibcon#about to write, iclass 35, count 0 2006.258.00:26:28.86#ibcon#wrote, iclass 35, count 0 2006.258.00:26:28.86#ibcon#about to read 3, iclass 35, count 0 2006.258.00:26:28.90#ibcon#read 3, iclass 35, count 0 2006.258.00:26:28.90#ibcon#about to read 4, iclass 35, count 0 2006.258.00:26:28.90#ibcon#read 4, iclass 35, count 0 2006.258.00:26:28.90#ibcon#about to read 5, iclass 35, count 0 2006.258.00:26:28.90#ibcon#read 5, iclass 35, count 0 2006.258.00:26:28.90#ibcon#about to read 6, iclass 35, count 0 2006.258.00:26:28.90#ibcon#read 6, iclass 35, count 0 2006.258.00:26:28.90#ibcon#end of sib2, iclass 35, count 0 2006.258.00:26:28.90#ibcon#*after write, iclass 35, count 0 2006.258.00:26:28.90#ibcon#*before return 0, iclass 35, count 0 2006.258.00:26:28.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:28.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:28.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:26:28.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:26:28.90$vck44/va=6,4 2006.258.00:26:28.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.00:26:28.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.00:26:28.90#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:28.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:28.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:28.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:28.96#ibcon#enter wrdev, iclass 37, count 2 2006.258.00:26:28.96#ibcon#first serial, iclass 37, count 2 2006.258.00:26:28.96#ibcon#enter sib2, iclass 37, count 2 2006.258.00:26:28.96#ibcon#flushed, iclass 37, count 2 2006.258.00:26:28.96#ibcon#about to write, iclass 37, count 2 2006.258.00:26:28.96#ibcon#wrote, iclass 37, count 2 2006.258.00:26:28.96#ibcon#about to read 3, iclass 37, count 2 2006.258.00:26:28.98#ibcon#read 3, iclass 37, count 2 2006.258.00:26:28.98#ibcon#about to read 4, iclass 37, count 2 2006.258.00:26:28.98#ibcon#read 4, iclass 37, count 2 2006.258.00:26:28.98#ibcon#about to read 5, iclass 37, count 2 2006.258.00:26:28.98#ibcon#read 5, iclass 37, count 2 2006.258.00:26:28.98#ibcon#about to read 6, iclass 37, count 2 2006.258.00:26:28.98#ibcon#read 6, iclass 37, count 2 2006.258.00:26:28.98#ibcon#end of sib2, iclass 37, count 2 2006.258.00:26:28.98#ibcon#*mode == 0, iclass 37, count 2 2006.258.00:26:28.98#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.00:26:28.98#ibcon#[25=AT06-04\r\n] 2006.258.00:26:28.98#ibcon#*before write, iclass 37, count 2 2006.258.00:26:28.98#ibcon#enter sib2, iclass 37, count 2 2006.258.00:26:28.98#ibcon#flushed, iclass 37, count 2 2006.258.00:26:28.98#ibcon#about to write, iclass 37, count 2 2006.258.00:26:28.98#ibcon#wrote, iclass 37, count 2 2006.258.00:26:28.98#ibcon#about to read 3, iclass 37, count 2 2006.258.00:26:29.01#ibcon#read 3, iclass 37, count 2 2006.258.00:26:29.01#ibcon#about to read 4, iclass 37, count 2 2006.258.00:26:29.01#ibcon#read 4, iclass 37, count 2 2006.258.00:26:29.01#ibcon#about to read 5, iclass 37, count 2 2006.258.00:26:29.01#ibcon#read 5, iclass 37, count 2 2006.258.00:26:29.01#ibcon#about to read 6, iclass 37, count 2 2006.258.00:26:29.01#ibcon#read 6, iclass 37, count 2 2006.258.00:26:29.01#ibcon#end of sib2, iclass 37, count 2 2006.258.00:26:29.01#ibcon#*after write, iclass 37, count 2 2006.258.00:26:29.01#ibcon#*before return 0, iclass 37, count 2 2006.258.00:26:29.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:29.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:29.01#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.00:26:29.01#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:29.01#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:29.13#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:29.13#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:29.13#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:26:29.13#ibcon#first serial, iclass 37, count 0 2006.258.00:26:29.13#ibcon#enter sib2, iclass 37, count 0 2006.258.00:26:29.13#ibcon#flushed, iclass 37, count 0 2006.258.00:26:29.13#ibcon#about to write, iclass 37, count 0 2006.258.00:26:29.13#ibcon#wrote, iclass 37, count 0 2006.258.00:26:29.13#ibcon#about to read 3, iclass 37, count 0 2006.258.00:26:29.15#ibcon#read 3, iclass 37, count 0 2006.258.00:26:29.15#ibcon#about to read 4, iclass 37, count 0 2006.258.00:26:29.15#ibcon#read 4, iclass 37, count 0 2006.258.00:26:29.15#ibcon#about to read 5, iclass 37, count 0 2006.258.00:26:29.15#ibcon#read 5, iclass 37, count 0 2006.258.00:26:29.15#ibcon#about to read 6, iclass 37, count 0 2006.258.00:26:29.15#ibcon#read 6, iclass 37, count 0 2006.258.00:26:29.15#ibcon#end of sib2, iclass 37, count 0 2006.258.00:26:29.15#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:26:29.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:26:29.15#ibcon#[25=USB\r\n] 2006.258.00:26:29.15#ibcon#*before write, iclass 37, count 0 2006.258.00:26:29.15#ibcon#enter sib2, iclass 37, count 0 2006.258.00:26:29.15#ibcon#flushed, iclass 37, count 0 2006.258.00:26:29.15#ibcon#about to write, iclass 37, count 0 2006.258.00:26:29.15#ibcon#wrote, iclass 37, count 0 2006.258.00:26:29.15#ibcon#about to read 3, iclass 37, count 0 2006.258.00:26:29.18#ibcon#read 3, iclass 37, count 0 2006.258.00:26:29.18#ibcon#about to read 4, iclass 37, count 0 2006.258.00:26:29.18#ibcon#read 4, iclass 37, count 0 2006.258.00:26:29.18#ibcon#about to read 5, iclass 37, count 0 2006.258.00:26:29.18#ibcon#read 5, iclass 37, count 0 2006.258.00:26:29.18#ibcon#about to read 6, iclass 37, count 0 2006.258.00:26:29.18#ibcon#read 6, iclass 37, count 0 2006.258.00:26:29.18#ibcon#end of sib2, iclass 37, count 0 2006.258.00:26:29.18#ibcon#*after write, iclass 37, count 0 2006.258.00:26:29.18#ibcon#*before return 0, iclass 37, count 0 2006.258.00:26:29.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:29.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:29.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:26:29.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:26:29.18$vck44/valo=7,864.99 2006.258.00:26:29.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.00:26:29.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.00:26:29.18#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:29.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:29.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:29.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:29.18#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:26:29.18#ibcon#first serial, iclass 39, count 0 2006.258.00:26:29.18#ibcon#enter sib2, iclass 39, count 0 2006.258.00:26:29.18#ibcon#flushed, iclass 39, count 0 2006.258.00:26:29.18#ibcon#about to write, iclass 39, count 0 2006.258.00:26:29.18#ibcon#wrote, iclass 39, count 0 2006.258.00:26:29.18#ibcon#about to read 3, iclass 39, count 0 2006.258.00:26:29.20#ibcon#read 3, iclass 39, count 0 2006.258.00:26:29.20#ibcon#about to read 4, iclass 39, count 0 2006.258.00:26:29.20#ibcon#read 4, iclass 39, count 0 2006.258.00:26:29.20#ibcon#about to read 5, iclass 39, count 0 2006.258.00:26:29.20#ibcon#read 5, iclass 39, count 0 2006.258.00:26:29.20#ibcon#about to read 6, iclass 39, count 0 2006.258.00:26:29.20#ibcon#read 6, iclass 39, count 0 2006.258.00:26:29.20#ibcon#end of sib2, iclass 39, count 0 2006.258.00:26:29.20#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:26:29.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:26:29.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:26:29.20#ibcon#*before write, iclass 39, count 0 2006.258.00:26:29.20#ibcon#enter sib2, iclass 39, count 0 2006.258.00:26:29.20#ibcon#flushed, iclass 39, count 0 2006.258.00:26:29.20#ibcon#about to write, iclass 39, count 0 2006.258.00:26:29.20#ibcon#wrote, iclass 39, count 0 2006.258.00:26:29.20#ibcon#about to read 3, iclass 39, count 0 2006.258.00:26:29.24#ibcon#read 3, iclass 39, count 0 2006.258.00:26:29.24#ibcon#about to read 4, iclass 39, count 0 2006.258.00:26:29.24#ibcon#read 4, iclass 39, count 0 2006.258.00:26:29.24#ibcon#about to read 5, iclass 39, count 0 2006.258.00:26:29.24#ibcon#read 5, iclass 39, count 0 2006.258.00:26:29.24#ibcon#about to read 6, iclass 39, count 0 2006.258.00:26:29.24#ibcon#read 6, iclass 39, count 0 2006.258.00:26:29.24#ibcon#end of sib2, iclass 39, count 0 2006.258.00:26:29.24#ibcon#*after write, iclass 39, count 0 2006.258.00:26:29.24#ibcon#*before return 0, iclass 39, count 0 2006.258.00:26:29.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:29.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:29.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:26:29.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:26:29.24$vck44/va=7,4 2006.258.00:26:29.24#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.00:26:29.24#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.00:26:29.24#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:29.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:29.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:29.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:29.30#ibcon#enter wrdev, iclass 3, count 2 2006.258.00:26:29.30#ibcon#first serial, iclass 3, count 2 2006.258.00:26:29.30#ibcon#enter sib2, iclass 3, count 2 2006.258.00:26:29.30#ibcon#flushed, iclass 3, count 2 2006.258.00:26:29.30#ibcon#about to write, iclass 3, count 2 2006.258.00:26:29.30#ibcon#wrote, iclass 3, count 2 2006.258.00:26:29.30#ibcon#about to read 3, iclass 3, count 2 2006.258.00:26:29.32#ibcon#read 3, iclass 3, count 2 2006.258.00:26:29.32#ibcon#about to read 4, iclass 3, count 2 2006.258.00:26:29.32#ibcon#read 4, iclass 3, count 2 2006.258.00:26:29.32#ibcon#about to read 5, iclass 3, count 2 2006.258.00:26:29.32#ibcon#read 5, iclass 3, count 2 2006.258.00:26:29.32#ibcon#about to read 6, iclass 3, count 2 2006.258.00:26:29.32#ibcon#read 6, iclass 3, count 2 2006.258.00:26:29.32#ibcon#end of sib2, iclass 3, count 2 2006.258.00:26:29.32#ibcon#*mode == 0, iclass 3, count 2 2006.258.00:26:29.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.00:26:29.32#ibcon#[25=AT07-04\r\n] 2006.258.00:26:29.32#ibcon#*before write, iclass 3, count 2 2006.258.00:26:29.32#ibcon#enter sib2, iclass 3, count 2 2006.258.00:26:29.32#ibcon#flushed, iclass 3, count 2 2006.258.00:26:29.32#ibcon#about to write, iclass 3, count 2 2006.258.00:26:29.32#ibcon#wrote, iclass 3, count 2 2006.258.00:26:29.32#ibcon#about to read 3, iclass 3, count 2 2006.258.00:26:29.35#ibcon#read 3, iclass 3, count 2 2006.258.00:26:29.35#ibcon#about to read 4, iclass 3, count 2 2006.258.00:26:29.35#ibcon#read 4, iclass 3, count 2 2006.258.00:26:29.35#ibcon#about to read 5, iclass 3, count 2 2006.258.00:26:29.35#ibcon#read 5, iclass 3, count 2 2006.258.00:26:29.35#ibcon#about to read 6, iclass 3, count 2 2006.258.00:26:29.35#ibcon#read 6, iclass 3, count 2 2006.258.00:26:29.35#ibcon#end of sib2, iclass 3, count 2 2006.258.00:26:29.35#ibcon#*after write, iclass 3, count 2 2006.258.00:26:29.35#ibcon#*before return 0, iclass 3, count 2 2006.258.00:26:29.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:29.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:29.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.00:26:29.35#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:29.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:29.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:29.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:29.47#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:26:29.47#ibcon#first serial, iclass 3, count 0 2006.258.00:26:29.47#ibcon#enter sib2, iclass 3, count 0 2006.258.00:26:29.47#ibcon#flushed, iclass 3, count 0 2006.258.00:26:29.47#ibcon#about to write, iclass 3, count 0 2006.258.00:26:29.47#ibcon#wrote, iclass 3, count 0 2006.258.00:26:29.47#ibcon#about to read 3, iclass 3, count 0 2006.258.00:26:29.49#ibcon#read 3, iclass 3, count 0 2006.258.00:26:29.49#ibcon#about to read 4, iclass 3, count 0 2006.258.00:26:29.49#ibcon#read 4, iclass 3, count 0 2006.258.00:26:29.49#ibcon#about to read 5, iclass 3, count 0 2006.258.00:26:29.49#ibcon#read 5, iclass 3, count 0 2006.258.00:26:29.49#ibcon#about to read 6, iclass 3, count 0 2006.258.00:26:29.49#ibcon#read 6, iclass 3, count 0 2006.258.00:26:29.49#ibcon#end of sib2, iclass 3, count 0 2006.258.00:26:29.49#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:26:29.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:26:29.49#ibcon#[25=USB\r\n] 2006.258.00:26:29.49#ibcon#*before write, iclass 3, count 0 2006.258.00:26:29.49#ibcon#enter sib2, iclass 3, count 0 2006.258.00:26:29.49#ibcon#flushed, iclass 3, count 0 2006.258.00:26:29.49#ibcon#about to write, iclass 3, count 0 2006.258.00:26:29.49#ibcon#wrote, iclass 3, count 0 2006.258.00:26:29.49#ibcon#about to read 3, iclass 3, count 0 2006.258.00:26:29.52#ibcon#read 3, iclass 3, count 0 2006.258.00:26:29.52#ibcon#about to read 4, iclass 3, count 0 2006.258.00:26:29.52#ibcon#read 4, iclass 3, count 0 2006.258.00:26:29.52#ibcon#about to read 5, iclass 3, count 0 2006.258.00:26:29.52#ibcon#read 5, iclass 3, count 0 2006.258.00:26:29.52#ibcon#about to read 6, iclass 3, count 0 2006.258.00:26:29.52#ibcon#read 6, iclass 3, count 0 2006.258.00:26:29.52#ibcon#end of sib2, iclass 3, count 0 2006.258.00:26:29.52#ibcon#*after write, iclass 3, count 0 2006.258.00:26:29.52#ibcon#*before return 0, iclass 3, count 0 2006.258.00:26:29.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:29.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:29.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:26:29.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:26:29.52$vck44/valo=8,884.99 2006.258.00:26:29.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.00:26:29.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.00:26:29.52#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:29.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:29.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:29.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:29.52#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:26:29.52#ibcon#first serial, iclass 5, count 0 2006.258.00:26:29.52#ibcon#enter sib2, iclass 5, count 0 2006.258.00:26:29.52#ibcon#flushed, iclass 5, count 0 2006.258.00:26:29.52#ibcon#about to write, iclass 5, count 0 2006.258.00:26:29.52#ibcon#wrote, iclass 5, count 0 2006.258.00:26:29.52#ibcon#about to read 3, iclass 5, count 0 2006.258.00:26:29.54#ibcon#read 3, iclass 5, count 0 2006.258.00:26:29.54#ibcon#about to read 4, iclass 5, count 0 2006.258.00:26:29.54#ibcon#read 4, iclass 5, count 0 2006.258.00:26:29.54#ibcon#about to read 5, iclass 5, count 0 2006.258.00:26:29.54#ibcon#read 5, iclass 5, count 0 2006.258.00:26:29.54#ibcon#about to read 6, iclass 5, count 0 2006.258.00:26:29.54#ibcon#read 6, iclass 5, count 0 2006.258.00:26:29.54#ibcon#end of sib2, iclass 5, count 0 2006.258.00:26:29.54#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:26:29.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:26:29.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:26:29.54#ibcon#*before write, iclass 5, count 0 2006.258.00:26:29.54#ibcon#enter sib2, iclass 5, count 0 2006.258.00:26:29.54#ibcon#flushed, iclass 5, count 0 2006.258.00:26:29.54#ibcon#about to write, iclass 5, count 0 2006.258.00:26:29.54#ibcon#wrote, iclass 5, count 0 2006.258.00:26:29.54#ibcon#about to read 3, iclass 5, count 0 2006.258.00:26:29.58#ibcon#read 3, iclass 5, count 0 2006.258.00:26:29.58#ibcon#about to read 4, iclass 5, count 0 2006.258.00:26:29.58#ibcon#read 4, iclass 5, count 0 2006.258.00:26:29.58#ibcon#about to read 5, iclass 5, count 0 2006.258.00:26:29.58#ibcon#read 5, iclass 5, count 0 2006.258.00:26:29.58#ibcon#about to read 6, iclass 5, count 0 2006.258.00:26:29.58#ibcon#read 6, iclass 5, count 0 2006.258.00:26:29.58#ibcon#end of sib2, iclass 5, count 0 2006.258.00:26:29.58#ibcon#*after write, iclass 5, count 0 2006.258.00:26:29.58#ibcon#*before return 0, iclass 5, count 0 2006.258.00:26:29.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:29.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:29.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:26:29.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:26:29.58$vck44/va=8,4 2006.258.00:26:29.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.00:26:29.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.00:26:29.58#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:29.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:26:29.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:26:29.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:26:29.64#ibcon#enter wrdev, iclass 7, count 2 2006.258.00:26:29.64#ibcon#first serial, iclass 7, count 2 2006.258.00:26:29.64#ibcon#enter sib2, iclass 7, count 2 2006.258.00:26:29.64#ibcon#flushed, iclass 7, count 2 2006.258.00:26:29.64#ibcon#about to write, iclass 7, count 2 2006.258.00:26:29.64#ibcon#wrote, iclass 7, count 2 2006.258.00:26:29.64#ibcon#about to read 3, iclass 7, count 2 2006.258.00:26:29.66#ibcon#read 3, iclass 7, count 2 2006.258.00:26:29.66#ibcon#about to read 4, iclass 7, count 2 2006.258.00:26:29.66#ibcon#read 4, iclass 7, count 2 2006.258.00:26:29.66#ibcon#about to read 5, iclass 7, count 2 2006.258.00:26:29.66#ibcon#read 5, iclass 7, count 2 2006.258.00:26:29.66#ibcon#about to read 6, iclass 7, count 2 2006.258.00:26:29.66#ibcon#read 6, iclass 7, count 2 2006.258.00:26:29.66#ibcon#end of sib2, iclass 7, count 2 2006.258.00:26:29.66#ibcon#*mode == 0, iclass 7, count 2 2006.258.00:26:29.66#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.00:26:29.66#ibcon#[25=AT08-04\r\n] 2006.258.00:26:29.66#ibcon#*before write, iclass 7, count 2 2006.258.00:26:29.66#ibcon#enter sib2, iclass 7, count 2 2006.258.00:26:29.66#ibcon#flushed, iclass 7, count 2 2006.258.00:26:29.66#ibcon#about to write, iclass 7, count 2 2006.258.00:26:29.66#ibcon#wrote, iclass 7, count 2 2006.258.00:26:29.66#ibcon#about to read 3, iclass 7, count 2 2006.258.00:26:29.69#ibcon#read 3, iclass 7, count 2 2006.258.00:26:29.69#ibcon#about to read 4, iclass 7, count 2 2006.258.00:26:29.69#ibcon#read 4, iclass 7, count 2 2006.258.00:26:29.69#ibcon#about to read 5, iclass 7, count 2 2006.258.00:26:29.69#ibcon#read 5, iclass 7, count 2 2006.258.00:26:29.69#ibcon#about to read 6, iclass 7, count 2 2006.258.00:26:29.69#ibcon#read 6, iclass 7, count 2 2006.258.00:26:29.69#ibcon#end of sib2, iclass 7, count 2 2006.258.00:26:29.69#ibcon#*after write, iclass 7, count 2 2006.258.00:26:29.69#ibcon#*before return 0, iclass 7, count 2 2006.258.00:26:29.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:26:29.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:26:29.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.00:26:29.69#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:29.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:26:29.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:26:29.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:26:29.81#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:26:29.81#ibcon#first serial, iclass 7, count 0 2006.258.00:26:29.81#ibcon#enter sib2, iclass 7, count 0 2006.258.00:26:29.81#ibcon#flushed, iclass 7, count 0 2006.258.00:26:29.81#ibcon#about to write, iclass 7, count 0 2006.258.00:26:29.81#ibcon#wrote, iclass 7, count 0 2006.258.00:26:29.81#ibcon#about to read 3, iclass 7, count 0 2006.258.00:26:29.83#ibcon#read 3, iclass 7, count 0 2006.258.00:26:29.83#ibcon#about to read 4, iclass 7, count 0 2006.258.00:26:29.83#ibcon#read 4, iclass 7, count 0 2006.258.00:26:29.83#ibcon#about to read 5, iclass 7, count 0 2006.258.00:26:29.83#ibcon#read 5, iclass 7, count 0 2006.258.00:26:29.83#ibcon#about to read 6, iclass 7, count 0 2006.258.00:26:29.83#ibcon#read 6, iclass 7, count 0 2006.258.00:26:29.83#ibcon#end of sib2, iclass 7, count 0 2006.258.00:26:29.83#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:26:29.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:26:29.83#ibcon#[25=USB\r\n] 2006.258.00:26:29.83#ibcon#*before write, iclass 7, count 0 2006.258.00:26:29.83#ibcon#enter sib2, iclass 7, count 0 2006.258.00:26:29.83#ibcon#flushed, iclass 7, count 0 2006.258.00:26:29.83#ibcon#about to write, iclass 7, count 0 2006.258.00:26:29.83#ibcon#wrote, iclass 7, count 0 2006.258.00:26:29.83#ibcon#about to read 3, iclass 7, count 0 2006.258.00:26:29.86#ibcon#read 3, iclass 7, count 0 2006.258.00:26:29.86#ibcon#about to read 4, iclass 7, count 0 2006.258.00:26:29.86#ibcon#read 4, iclass 7, count 0 2006.258.00:26:29.86#ibcon#about to read 5, iclass 7, count 0 2006.258.00:26:29.86#ibcon#read 5, iclass 7, count 0 2006.258.00:26:29.86#ibcon#about to read 6, iclass 7, count 0 2006.258.00:26:29.86#ibcon#read 6, iclass 7, count 0 2006.258.00:26:29.86#ibcon#end of sib2, iclass 7, count 0 2006.258.00:26:29.86#ibcon#*after write, iclass 7, count 0 2006.258.00:26:29.86#ibcon#*before return 0, iclass 7, count 0 2006.258.00:26:29.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:26:29.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:26:29.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:26:29.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:26:29.86$vck44/vblo=1,629.99 2006.258.00:26:29.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.00:26:29.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.00:26:29.86#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:29.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:29.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:29.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:29.86#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:26:29.86#ibcon#first serial, iclass 11, count 0 2006.258.00:26:29.86#ibcon#enter sib2, iclass 11, count 0 2006.258.00:26:29.86#ibcon#flushed, iclass 11, count 0 2006.258.00:26:29.86#ibcon#about to write, iclass 11, count 0 2006.258.00:26:29.86#ibcon#wrote, iclass 11, count 0 2006.258.00:26:29.86#ibcon#about to read 3, iclass 11, count 0 2006.258.00:26:29.88#ibcon#read 3, iclass 11, count 0 2006.258.00:26:29.88#ibcon#about to read 4, iclass 11, count 0 2006.258.00:26:29.88#ibcon#read 4, iclass 11, count 0 2006.258.00:26:29.88#ibcon#about to read 5, iclass 11, count 0 2006.258.00:26:29.88#ibcon#read 5, iclass 11, count 0 2006.258.00:26:29.88#ibcon#about to read 6, iclass 11, count 0 2006.258.00:26:29.88#ibcon#read 6, iclass 11, count 0 2006.258.00:26:29.88#ibcon#end of sib2, iclass 11, count 0 2006.258.00:26:29.88#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:26:29.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:26:29.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:26:29.88#ibcon#*before write, iclass 11, count 0 2006.258.00:26:29.88#ibcon#enter sib2, iclass 11, count 0 2006.258.00:26:29.88#ibcon#flushed, iclass 11, count 0 2006.258.00:26:29.88#ibcon#about to write, iclass 11, count 0 2006.258.00:26:29.88#ibcon#wrote, iclass 11, count 0 2006.258.00:26:29.88#ibcon#about to read 3, iclass 11, count 0 2006.258.00:26:29.92#ibcon#read 3, iclass 11, count 0 2006.258.00:26:29.92#ibcon#about to read 4, iclass 11, count 0 2006.258.00:26:29.92#ibcon#read 4, iclass 11, count 0 2006.258.00:26:29.92#ibcon#about to read 5, iclass 11, count 0 2006.258.00:26:29.92#ibcon#read 5, iclass 11, count 0 2006.258.00:26:29.92#ibcon#about to read 6, iclass 11, count 0 2006.258.00:26:29.92#ibcon#read 6, iclass 11, count 0 2006.258.00:26:29.92#ibcon#end of sib2, iclass 11, count 0 2006.258.00:26:29.92#ibcon#*after write, iclass 11, count 0 2006.258.00:26:29.92#ibcon#*before return 0, iclass 11, count 0 2006.258.00:26:29.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:29.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:26:29.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:26:29.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:26:29.92$vck44/vb=1,4 2006.258.00:26:29.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.00:26:29.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.00:26:29.92#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:29.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:29.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:29.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:29.92#ibcon#enter wrdev, iclass 13, count 2 2006.258.00:26:29.92#ibcon#first serial, iclass 13, count 2 2006.258.00:26:29.92#ibcon#enter sib2, iclass 13, count 2 2006.258.00:26:29.92#ibcon#flushed, iclass 13, count 2 2006.258.00:26:29.92#ibcon#about to write, iclass 13, count 2 2006.258.00:26:29.92#ibcon#wrote, iclass 13, count 2 2006.258.00:26:29.92#ibcon#about to read 3, iclass 13, count 2 2006.258.00:26:29.94#ibcon#read 3, iclass 13, count 2 2006.258.00:26:29.94#ibcon#about to read 4, iclass 13, count 2 2006.258.00:26:29.94#ibcon#read 4, iclass 13, count 2 2006.258.00:26:29.94#ibcon#about to read 5, iclass 13, count 2 2006.258.00:26:29.94#ibcon#read 5, iclass 13, count 2 2006.258.00:26:29.94#ibcon#about to read 6, iclass 13, count 2 2006.258.00:26:29.94#ibcon#read 6, iclass 13, count 2 2006.258.00:26:29.94#ibcon#end of sib2, iclass 13, count 2 2006.258.00:26:29.94#ibcon#*mode == 0, iclass 13, count 2 2006.258.00:26:29.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.00:26:29.94#ibcon#[27=AT01-04\r\n] 2006.258.00:26:29.94#ibcon#*before write, iclass 13, count 2 2006.258.00:26:29.94#ibcon#enter sib2, iclass 13, count 2 2006.258.00:26:29.94#ibcon#flushed, iclass 13, count 2 2006.258.00:26:29.94#ibcon#about to write, iclass 13, count 2 2006.258.00:26:29.94#ibcon#wrote, iclass 13, count 2 2006.258.00:26:29.94#ibcon#about to read 3, iclass 13, count 2 2006.258.00:26:29.97#ibcon#read 3, iclass 13, count 2 2006.258.00:26:29.97#ibcon#about to read 4, iclass 13, count 2 2006.258.00:26:29.97#ibcon#read 4, iclass 13, count 2 2006.258.00:26:29.97#ibcon#about to read 5, iclass 13, count 2 2006.258.00:26:29.97#ibcon#read 5, iclass 13, count 2 2006.258.00:26:29.97#ibcon#about to read 6, iclass 13, count 2 2006.258.00:26:29.97#ibcon#read 6, iclass 13, count 2 2006.258.00:26:29.97#ibcon#end of sib2, iclass 13, count 2 2006.258.00:26:29.97#ibcon#*after write, iclass 13, count 2 2006.258.00:26:29.97#ibcon#*before return 0, iclass 13, count 2 2006.258.00:26:29.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:29.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:26:29.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.00:26:29.97#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:29.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:30.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:30.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:30.09#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:26:30.09#ibcon#first serial, iclass 13, count 0 2006.258.00:26:30.09#ibcon#enter sib2, iclass 13, count 0 2006.258.00:26:30.09#ibcon#flushed, iclass 13, count 0 2006.258.00:26:30.09#ibcon#about to write, iclass 13, count 0 2006.258.00:26:30.09#ibcon#wrote, iclass 13, count 0 2006.258.00:26:30.09#ibcon#about to read 3, iclass 13, count 0 2006.258.00:26:30.11#ibcon#read 3, iclass 13, count 0 2006.258.00:26:30.11#ibcon#about to read 4, iclass 13, count 0 2006.258.00:26:30.11#ibcon#read 4, iclass 13, count 0 2006.258.00:26:30.11#ibcon#about to read 5, iclass 13, count 0 2006.258.00:26:30.11#ibcon#read 5, iclass 13, count 0 2006.258.00:26:30.11#ibcon#about to read 6, iclass 13, count 0 2006.258.00:26:30.11#ibcon#read 6, iclass 13, count 0 2006.258.00:26:30.11#ibcon#end of sib2, iclass 13, count 0 2006.258.00:26:30.11#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:26:30.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:26:30.11#ibcon#[27=USB\r\n] 2006.258.00:26:30.11#ibcon#*before write, iclass 13, count 0 2006.258.00:26:30.11#ibcon#enter sib2, iclass 13, count 0 2006.258.00:26:30.11#ibcon#flushed, iclass 13, count 0 2006.258.00:26:30.11#ibcon#about to write, iclass 13, count 0 2006.258.00:26:30.11#ibcon#wrote, iclass 13, count 0 2006.258.00:26:30.11#ibcon#about to read 3, iclass 13, count 0 2006.258.00:26:30.14#ibcon#read 3, iclass 13, count 0 2006.258.00:26:30.14#ibcon#about to read 4, iclass 13, count 0 2006.258.00:26:30.14#ibcon#read 4, iclass 13, count 0 2006.258.00:26:30.14#ibcon#about to read 5, iclass 13, count 0 2006.258.00:26:30.14#ibcon#read 5, iclass 13, count 0 2006.258.00:26:30.14#ibcon#about to read 6, iclass 13, count 0 2006.258.00:26:30.14#ibcon#read 6, iclass 13, count 0 2006.258.00:26:30.14#ibcon#end of sib2, iclass 13, count 0 2006.258.00:26:30.14#ibcon#*after write, iclass 13, count 0 2006.258.00:26:30.14#ibcon#*before return 0, iclass 13, count 0 2006.258.00:26:30.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:30.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:26:30.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:26:30.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:26:30.14$vck44/vblo=2,634.99 2006.258.00:26:30.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.00:26:30.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.00:26:30.14#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:30.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:30.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:30.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:30.14#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:26:30.14#ibcon#first serial, iclass 15, count 0 2006.258.00:26:30.14#ibcon#enter sib2, iclass 15, count 0 2006.258.00:26:30.14#ibcon#flushed, iclass 15, count 0 2006.258.00:26:30.14#ibcon#about to write, iclass 15, count 0 2006.258.00:26:30.14#ibcon#wrote, iclass 15, count 0 2006.258.00:26:30.14#ibcon#about to read 3, iclass 15, count 0 2006.258.00:26:30.16#ibcon#read 3, iclass 15, count 0 2006.258.00:26:30.16#ibcon#about to read 4, iclass 15, count 0 2006.258.00:26:30.16#ibcon#read 4, iclass 15, count 0 2006.258.00:26:30.16#ibcon#about to read 5, iclass 15, count 0 2006.258.00:26:30.16#ibcon#read 5, iclass 15, count 0 2006.258.00:26:30.16#ibcon#about to read 6, iclass 15, count 0 2006.258.00:26:30.16#ibcon#read 6, iclass 15, count 0 2006.258.00:26:30.16#ibcon#end of sib2, iclass 15, count 0 2006.258.00:26:30.16#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:26:30.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:26:30.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:26:30.16#ibcon#*before write, iclass 15, count 0 2006.258.00:26:30.16#ibcon#enter sib2, iclass 15, count 0 2006.258.00:26:30.16#ibcon#flushed, iclass 15, count 0 2006.258.00:26:30.16#ibcon#about to write, iclass 15, count 0 2006.258.00:26:30.16#ibcon#wrote, iclass 15, count 0 2006.258.00:26:30.16#ibcon#about to read 3, iclass 15, count 0 2006.258.00:26:30.20#ibcon#read 3, iclass 15, count 0 2006.258.00:26:30.20#ibcon#about to read 4, iclass 15, count 0 2006.258.00:26:30.20#ibcon#read 4, iclass 15, count 0 2006.258.00:26:30.20#ibcon#about to read 5, iclass 15, count 0 2006.258.00:26:30.20#ibcon#read 5, iclass 15, count 0 2006.258.00:26:30.20#ibcon#about to read 6, iclass 15, count 0 2006.258.00:26:30.20#ibcon#read 6, iclass 15, count 0 2006.258.00:26:30.20#ibcon#end of sib2, iclass 15, count 0 2006.258.00:26:30.20#ibcon#*after write, iclass 15, count 0 2006.258.00:26:30.21#ibcon#*before return 0, iclass 15, count 0 2006.258.00:26:30.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:30.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:26:30.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:26:30.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:26:30.21$vck44/vb=2,5 2006.258.00:26:30.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.00:26:30.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.00:26:30.21#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:30.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:26:30.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:26:30.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:26:30.26#ibcon#enter wrdev, iclass 17, count 2 2006.258.00:26:30.26#ibcon#first serial, iclass 17, count 2 2006.258.00:26:30.26#ibcon#enter sib2, iclass 17, count 2 2006.258.00:26:30.26#ibcon#flushed, iclass 17, count 2 2006.258.00:26:30.26#ibcon#about to write, iclass 17, count 2 2006.258.00:26:30.26#ibcon#wrote, iclass 17, count 2 2006.258.00:26:30.26#ibcon#about to read 3, iclass 17, count 2 2006.258.00:26:30.28#ibcon#read 3, iclass 17, count 2 2006.258.00:26:30.28#ibcon#about to read 4, iclass 17, count 2 2006.258.00:26:30.28#ibcon#read 4, iclass 17, count 2 2006.258.00:26:30.28#ibcon#about to read 5, iclass 17, count 2 2006.258.00:26:30.28#ibcon#read 5, iclass 17, count 2 2006.258.00:26:30.28#ibcon#about to read 6, iclass 17, count 2 2006.258.00:26:30.28#ibcon#read 6, iclass 17, count 2 2006.258.00:26:30.28#ibcon#end of sib2, iclass 17, count 2 2006.258.00:26:30.28#ibcon#*mode == 0, iclass 17, count 2 2006.258.00:26:30.28#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.00:26:30.28#ibcon#[27=AT02-05\r\n] 2006.258.00:26:30.28#ibcon#*before write, iclass 17, count 2 2006.258.00:26:30.28#ibcon#enter sib2, iclass 17, count 2 2006.258.00:26:30.28#ibcon#flushed, iclass 17, count 2 2006.258.00:26:30.28#ibcon#about to write, iclass 17, count 2 2006.258.00:26:30.28#ibcon#wrote, iclass 17, count 2 2006.258.00:26:30.28#ibcon#about to read 3, iclass 17, count 2 2006.258.00:26:30.31#ibcon#read 3, iclass 17, count 2 2006.258.00:26:30.31#ibcon#about to read 4, iclass 17, count 2 2006.258.00:26:30.31#ibcon#read 4, iclass 17, count 2 2006.258.00:26:30.31#ibcon#about to read 5, iclass 17, count 2 2006.258.00:26:30.31#ibcon#read 5, iclass 17, count 2 2006.258.00:26:30.31#ibcon#about to read 6, iclass 17, count 2 2006.258.00:26:30.31#ibcon#read 6, iclass 17, count 2 2006.258.00:26:30.31#ibcon#end of sib2, iclass 17, count 2 2006.258.00:26:30.31#ibcon#*after write, iclass 17, count 2 2006.258.00:26:30.31#ibcon#*before return 0, iclass 17, count 2 2006.258.00:26:30.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:26:30.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:26:30.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.00:26:30.31#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:30.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:26:30.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:26:30.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:26:30.43#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:26:30.43#ibcon#first serial, iclass 17, count 0 2006.258.00:26:30.43#ibcon#enter sib2, iclass 17, count 0 2006.258.00:26:30.43#ibcon#flushed, iclass 17, count 0 2006.258.00:26:30.43#ibcon#about to write, iclass 17, count 0 2006.258.00:26:30.43#ibcon#wrote, iclass 17, count 0 2006.258.00:26:30.43#ibcon#about to read 3, iclass 17, count 0 2006.258.00:26:30.45#ibcon#read 3, iclass 17, count 0 2006.258.00:26:30.45#ibcon#about to read 4, iclass 17, count 0 2006.258.00:26:30.45#ibcon#read 4, iclass 17, count 0 2006.258.00:26:30.45#ibcon#about to read 5, iclass 17, count 0 2006.258.00:26:30.45#ibcon#read 5, iclass 17, count 0 2006.258.00:26:30.45#ibcon#about to read 6, iclass 17, count 0 2006.258.00:26:30.45#ibcon#read 6, iclass 17, count 0 2006.258.00:26:30.45#ibcon#end of sib2, iclass 17, count 0 2006.258.00:26:30.45#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:26:30.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:26:30.45#ibcon#[27=USB\r\n] 2006.258.00:26:30.45#ibcon#*before write, iclass 17, count 0 2006.258.00:26:30.45#ibcon#enter sib2, iclass 17, count 0 2006.258.00:26:30.45#ibcon#flushed, iclass 17, count 0 2006.258.00:26:30.45#ibcon#about to write, iclass 17, count 0 2006.258.00:26:30.45#ibcon#wrote, iclass 17, count 0 2006.258.00:26:30.45#ibcon#about to read 3, iclass 17, count 0 2006.258.00:26:30.48#ibcon#read 3, iclass 17, count 0 2006.258.00:26:30.48#ibcon#about to read 4, iclass 17, count 0 2006.258.00:26:30.48#ibcon#read 4, iclass 17, count 0 2006.258.00:26:30.48#ibcon#about to read 5, iclass 17, count 0 2006.258.00:26:30.48#ibcon#read 5, iclass 17, count 0 2006.258.00:26:30.48#ibcon#about to read 6, iclass 17, count 0 2006.258.00:26:30.48#ibcon#read 6, iclass 17, count 0 2006.258.00:26:30.48#ibcon#end of sib2, iclass 17, count 0 2006.258.00:26:30.48#ibcon#*after write, iclass 17, count 0 2006.258.00:26:30.48#ibcon#*before return 0, iclass 17, count 0 2006.258.00:26:30.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:26:30.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:26:30.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:26:30.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:26:30.48$vck44/vblo=3,649.99 2006.258.00:26:30.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.00:26:30.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.00:26:30.48#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:30.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:26:30.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:26:30.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:26:30.48#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:26:30.48#ibcon#first serial, iclass 19, count 0 2006.258.00:26:30.48#ibcon#enter sib2, iclass 19, count 0 2006.258.00:26:30.48#ibcon#flushed, iclass 19, count 0 2006.258.00:26:30.48#ibcon#about to write, iclass 19, count 0 2006.258.00:26:30.48#ibcon#wrote, iclass 19, count 0 2006.258.00:26:30.48#ibcon#about to read 3, iclass 19, count 0 2006.258.00:26:30.50#ibcon#read 3, iclass 19, count 0 2006.258.00:26:30.50#ibcon#about to read 4, iclass 19, count 0 2006.258.00:26:30.50#ibcon#read 4, iclass 19, count 0 2006.258.00:26:30.50#ibcon#about to read 5, iclass 19, count 0 2006.258.00:26:30.50#ibcon#read 5, iclass 19, count 0 2006.258.00:26:30.50#ibcon#about to read 6, iclass 19, count 0 2006.258.00:26:30.50#ibcon#read 6, iclass 19, count 0 2006.258.00:26:30.50#ibcon#end of sib2, iclass 19, count 0 2006.258.00:26:30.50#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:26:30.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:26:30.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:26:30.50#ibcon#*before write, iclass 19, count 0 2006.258.00:26:30.50#ibcon#enter sib2, iclass 19, count 0 2006.258.00:26:30.50#ibcon#flushed, iclass 19, count 0 2006.258.00:26:30.50#ibcon#about to write, iclass 19, count 0 2006.258.00:26:30.50#ibcon#wrote, iclass 19, count 0 2006.258.00:26:30.50#ibcon#about to read 3, iclass 19, count 0 2006.258.00:26:30.54#ibcon#read 3, iclass 19, count 0 2006.258.00:26:30.54#ibcon#about to read 4, iclass 19, count 0 2006.258.00:26:30.54#ibcon#read 4, iclass 19, count 0 2006.258.00:26:30.54#ibcon#about to read 5, iclass 19, count 0 2006.258.00:26:30.54#ibcon#read 5, iclass 19, count 0 2006.258.00:26:30.54#ibcon#about to read 6, iclass 19, count 0 2006.258.00:26:30.54#ibcon#read 6, iclass 19, count 0 2006.258.00:26:30.54#ibcon#end of sib2, iclass 19, count 0 2006.258.00:26:30.54#ibcon#*after write, iclass 19, count 0 2006.258.00:26:30.54#ibcon#*before return 0, iclass 19, count 0 2006.258.00:26:30.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:26:30.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:26:30.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:26:30.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:26:30.54$vck44/vb=3,4 2006.258.00:26:30.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.00:26:30.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.00:26:30.54#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:30.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:26:30.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:26:30.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:26:30.60#ibcon#enter wrdev, iclass 21, count 2 2006.258.00:26:30.60#ibcon#first serial, iclass 21, count 2 2006.258.00:26:30.60#ibcon#enter sib2, iclass 21, count 2 2006.258.00:26:30.60#ibcon#flushed, iclass 21, count 2 2006.258.00:26:30.60#ibcon#about to write, iclass 21, count 2 2006.258.00:26:30.60#ibcon#wrote, iclass 21, count 2 2006.258.00:26:30.60#ibcon#about to read 3, iclass 21, count 2 2006.258.00:26:30.62#ibcon#read 3, iclass 21, count 2 2006.258.00:26:30.62#ibcon#about to read 4, iclass 21, count 2 2006.258.00:26:30.62#ibcon#read 4, iclass 21, count 2 2006.258.00:26:30.62#ibcon#about to read 5, iclass 21, count 2 2006.258.00:26:30.62#ibcon#read 5, iclass 21, count 2 2006.258.00:26:30.62#ibcon#about to read 6, iclass 21, count 2 2006.258.00:26:30.62#ibcon#read 6, iclass 21, count 2 2006.258.00:26:30.62#ibcon#end of sib2, iclass 21, count 2 2006.258.00:26:30.62#ibcon#*mode == 0, iclass 21, count 2 2006.258.00:26:30.62#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.00:26:30.62#ibcon#[27=AT03-04\r\n] 2006.258.00:26:30.62#ibcon#*before write, iclass 21, count 2 2006.258.00:26:30.62#ibcon#enter sib2, iclass 21, count 2 2006.258.00:26:30.62#ibcon#flushed, iclass 21, count 2 2006.258.00:26:30.62#ibcon#about to write, iclass 21, count 2 2006.258.00:26:30.62#ibcon#wrote, iclass 21, count 2 2006.258.00:26:30.62#ibcon#about to read 3, iclass 21, count 2 2006.258.00:26:30.65#ibcon#read 3, iclass 21, count 2 2006.258.00:26:30.65#ibcon#about to read 4, iclass 21, count 2 2006.258.00:26:30.65#ibcon#read 4, iclass 21, count 2 2006.258.00:26:30.65#ibcon#about to read 5, iclass 21, count 2 2006.258.00:26:30.65#ibcon#read 5, iclass 21, count 2 2006.258.00:26:30.65#ibcon#about to read 6, iclass 21, count 2 2006.258.00:26:30.65#ibcon#read 6, iclass 21, count 2 2006.258.00:26:30.65#ibcon#end of sib2, iclass 21, count 2 2006.258.00:26:30.65#ibcon#*after write, iclass 21, count 2 2006.258.00:26:30.65#ibcon#*before return 0, iclass 21, count 2 2006.258.00:26:30.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:26:30.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:26:30.65#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.00:26:30.65#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:30.65#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:26:30.77#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:26:30.77#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:26:30.77#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:26:30.77#ibcon#first serial, iclass 21, count 0 2006.258.00:26:30.77#ibcon#enter sib2, iclass 21, count 0 2006.258.00:26:30.77#ibcon#flushed, iclass 21, count 0 2006.258.00:26:30.77#ibcon#about to write, iclass 21, count 0 2006.258.00:26:30.77#ibcon#wrote, iclass 21, count 0 2006.258.00:26:30.77#ibcon#about to read 3, iclass 21, count 0 2006.258.00:26:30.79#ibcon#read 3, iclass 21, count 0 2006.258.00:26:30.79#ibcon#about to read 4, iclass 21, count 0 2006.258.00:26:30.79#ibcon#read 4, iclass 21, count 0 2006.258.00:26:30.79#ibcon#about to read 5, iclass 21, count 0 2006.258.00:26:30.79#ibcon#read 5, iclass 21, count 0 2006.258.00:26:30.79#ibcon#about to read 6, iclass 21, count 0 2006.258.00:26:30.79#ibcon#read 6, iclass 21, count 0 2006.258.00:26:30.79#ibcon#end of sib2, iclass 21, count 0 2006.258.00:26:30.79#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:26:30.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:26:30.79#ibcon#[27=USB\r\n] 2006.258.00:26:30.79#ibcon#*before write, iclass 21, count 0 2006.258.00:26:30.79#ibcon#enter sib2, iclass 21, count 0 2006.258.00:26:30.79#ibcon#flushed, iclass 21, count 0 2006.258.00:26:30.79#ibcon#about to write, iclass 21, count 0 2006.258.00:26:30.79#ibcon#wrote, iclass 21, count 0 2006.258.00:26:30.79#ibcon#about to read 3, iclass 21, count 0 2006.258.00:26:30.82#ibcon#read 3, iclass 21, count 0 2006.258.00:26:30.82#ibcon#about to read 4, iclass 21, count 0 2006.258.00:26:30.82#ibcon#read 4, iclass 21, count 0 2006.258.00:26:30.82#ibcon#about to read 5, iclass 21, count 0 2006.258.00:26:30.82#ibcon#read 5, iclass 21, count 0 2006.258.00:26:30.82#ibcon#about to read 6, iclass 21, count 0 2006.258.00:26:30.82#ibcon#read 6, iclass 21, count 0 2006.258.00:26:30.82#ibcon#end of sib2, iclass 21, count 0 2006.258.00:26:30.82#ibcon#*after write, iclass 21, count 0 2006.258.00:26:30.82#ibcon#*before return 0, iclass 21, count 0 2006.258.00:26:30.82#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:26:30.82#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:26:30.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:26:30.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:26:30.82$vck44/vblo=4,679.99 2006.258.00:26:30.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.00:26:30.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.00:26:30.82#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:30.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:30.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:30.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:30.82#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:26:30.82#ibcon#first serial, iclass 23, count 0 2006.258.00:26:30.82#ibcon#enter sib2, iclass 23, count 0 2006.258.00:26:30.82#ibcon#flushed, iclass 23, count 0 2006.258.00:26:30.82#ibcon#about to write, iclass 23, count 0 2006.258.00:26:30.82#ibcon#wrote, iclass 23, count 0 2006.258.00:26:30.82#ibcon#about to read 3, iclass 23, count 0 2006.258.00:26:30.84#ibcon#read 3, iclass 23, count 0 2006.258.00:26:30.84#ibcon#about to read 4, iclass 23, count 0 2006.258.00:26:30.84#ibcon#read 4, iclass 23, count 0 2006.258.00:26:30.84#ibcon#about to read 5, iclass 23, count 0 2006.258.00:26:30.84#ibcon#read 5, iclass 23, count 0 2006.258.00:26:30.84#ibcon#about to read 6, iclass 23, count 0 2006.258.00:26:30.84#ibcon#read 6, iclass 23, count 0 2006.258.00:26:30.84#ibcon#end of sib2, iclass 23, count 0 2006.258.00:26:30.84#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:26:30.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:26:30.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:26:30.84#ibcon#*before write, iclass 23, count 0 2006.258.00:26:30.84#ibcon#enter sib2, iclass 23, count 0 2006.258.00:26:30.84#ibcon#flushed, iclass 23, count 0 2006.258.00:26:30.84#ibcon#about to write, iclass 23, count 0 2006.258.00:26:30.84#ibcon#wrote, iclass 23, count 0 2006.258.00:26:30.84#ibcon#about to read 3, iclass 23, count 0 2006.258.00:26:30.88#ibcon#read 3, iclass 23, count 0 2006.258.00:26:30.88#ibcon#about to read 4, iclass 23, count 0 2006.258.00:26:30.88#ibcon#read 4, iclass 23, count 0 2006.258.00:26:30.88#ibcon#about to read 5, iclass 23, count 0 2006.258.00:26:30.88#ibcon#read 5, iclass 23, count 0 2006.258.00:26:30.88#ibcon#about to read 6, iclass 23, count 0 2006.258.00:26:30.88#ibcon#read 6, iclass 23, count 0 2006.258.00:26:30.88#ibcon#end of sib2, iclass 23, count 0 2006.258.00:26:30.88#ibcon#*after write, iclass 23, count 0 2006.258.00:26:30.88#ibcon#*before return 0, iclass 23, count 0 2006.258.00:26:30.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:30.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:26:30.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:26:30.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:26:30.88$vck44/vb=4,5 2006.258.00:26:30.88#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.258.00:26:30.88#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.258.00:26:30.88#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:30.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:30.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:30.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:30.94#ibcon#enter wrdev, iclass 25, count 2 2006.258.00:26:30.94#ibcon#first serial, iclass 25, count 2 2006.258.00:26:30.94#ibcon#enter sib2, iclass 25, count 2 2006.258.00:26:30.94#ibcon#flushed, iclass 25, count 2 2006.258.00:26:30.94#ibcon#about to write, iclass 25, count 2 2006.258.00:26:30.94#ibcon#wrote, iclass 25, count 2 2006.258.00:26:30.94#ibcon#about to read 3, iclass 25, count 2 2006.258.00:26:30.96#ibcon#read 3, iclass 25, count 2 2006.258.00:26:30.96#ibcon#about to read 4, iclass 25, count 2 2006.258.00:26:30.96#ibcon#read 4, iclass 25, count 2 2006.258.00:26:30.96#ibcon#about to read 5, iclass 25, count 2 2006.258.00:26:30.96#ibcon#read 5, iclass 25, count 2 2006.258.00:26:30.96#ibcon#about to read 6, iclass 25, count 2 2006.258.00:26:30.96#ibcon#read 6, iclass 25, count 2 2006.258.00:26:30.96#ibcon#end of sib2, iclass 25, count 2 2006.258.00:26:30.96#ibcon#*mode == 0, iclass 25, count 2 2006.258.00:26:30.96#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.258.00:26:30.96#ibcon#[27=AT04-05\r\n] 2006.258.00:26:30.96#ibcon#*before write, iclass 25, count 2 2006.258.00:26:30.96#ibcon#enter sib2, iclass 25, count 2 2006.258.00:26:30.96#ibcon#flushed, iclass 25, count 2 2006.258.00:26:30.96#ibcon#about to write, iclass 25, count 2 2006.258.00:26:30.96#ibcon#wrote, iclass 25, count 2 2006.258.00:26:30.96#ibcon#about to read 3, iclass 25, count 2 2006.258.00:26:30.99#ibcon#read 3, iclass 25, count 2 2006.258.00:26:30.99#ibcon#about to read 4, iclass 25, count 2 2006.258.00:26:30.99#ibcon#read 4, iclass 25, count 2 2006.258.00:26:30.99#ibcon#about to read 5, iclass 25, count 2 2006.258.00:26:30.99#ibcon#read 5, iclass 25, count 2 2006.258.00:26:30.99#ibcon#about to read 6, iclass 25, count 2 2006.258.00:26:30.99#ibcon#read 6, iclass 25, count 2 2006.258.00:26:30.99#ibcon#end of sib2, iclass 25, count 2 2006.258.00:26:30.99#ibcon#*after write, iclass 25, count 2 2006.258.00:26:30.99#ibcon#*before return 0, iclass 25, count 2 2006.258.00:26:30.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:30.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:26:30.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.258.00:26:30.99#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:30.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:31.11#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:31.11#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:31.11#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:26:31.11#ibcon#first serial, iclass 25, count 0 2006.258.00:26:31.11#ibcon#enter sib2, iclass 25, count 0 2006.258.00:26:31.11#ibcon#flushed, iclass 25, count 0 2006.258.00:26:31.11#ibcon#about to write, iclass 25, count 0 2006.258.00:26:31.11#ibcon#wrote, iclass 25, count 0 2006.258.00:26:31.11#ibcon#about to read 3, iclass 25, count 0 2006.258.00:26:31.13#ibcon#read 3, iclass 25, count 0 2006.258.00:26:31.13#ibcon#about to read 4, iclass 25, count 0 2006.258.00:26:31.13#ibcon#read 4, iclass 25, count 0 2006.258.00:26:31.13#ibcon#about to read 5, iclass 25, count 0 2006.258.00:26:31.13#ibcon#read 5, iclass 25, count 0 2006.258.00:26:31.13#ibcon#about to read 6, iclass 25, count 0 2006.258.00:26:31.13#ibcon#read 6, iclass 25, count 0 2006.258.00:26:31.13#ibcon#end of sib2, iclass 25, count 0 2006.258.00:26:31.13#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:26:31.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:26:31.13#ibcon#[27=USB\r\n] 2006.258.00:26:31.13#ibcon#*before write, iclass 25, count 0 2006.258.00:26:31.13#ibcon#enter sib2, iclass 25, count 0 2006.258.00:26:31.13#ibcon#flushed, iclass 25, count 0 2006.258.00:26:31.13#ibcon#about to write, iclass 25, count 0 2006.258.00:26:31.13#ibcon#wrote, iclass 25, count 0 2006.258.00:26:31.13#ibcon#about to read 3, iclass 25, count 0 2006.258.00:26:31.16#ibcon#read 3, iclass 25, count 0 2006.258.00:26:31.16#ibcon#about to read 4, iclass 25, count 0 2006.258.00:26:31.16#ibcon#read 4, iclass 25, count 0 2006.258.00:26:31.16#ibcon#about to read 5, iclass 25, count 0 2006.258.00:26:31.16#ibcon#read 5, iclass 25, count 0 2006.258.00:26:31.16#ibcon#about to read 6, iclass 25, count 0 2006.258.00:26:31.16#ibcon#read 6, iclass 25, count 0 2006.258.00:26:31.16#ibcon#end of sib2, iclass 25, count 0 2006.258.00:26:31.16#ibcon#*after write, iclass 25, count 0 2006.258.00:26:31.16#ibcon#*before return 0, iclass 25, count 0 2006.258.00:26:31.16#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:31.16#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:26:31.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:26:31.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:26:31.16$vck44/vblo=5,709.99 2006.258.00:26:31.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.00:26:31.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.00:26:31.16#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:31.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:31.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:31.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:31.16#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:26:31.16#ibcon#first serial, iclass 27, count 0 2006.258.00:26:31.16#ibcon#enter sib2, iclass 27, count 0 2006.258.00:26:31.16#ibcon#flushed, iclass 27, count 0 2006.258.00:26:31.16#ibcon#about to write, iclass 27, count 0 2006.258.00:26:31.16#ibcon#wrote, iclass 27, count 0 2006.258.00:26:31.16#ibcon#about to read 3, iclass 27, count 0 2006.258.00:26:31.18#ibcon#read 3, iclass 27, count 0 2006.258.00:26:31.18#ibcon#about to read 4, iclass 27, count 0 2006.258.00:26:31.18#ibcon#read 4, iclass 27, count 0 2006.258.00:26:31.18#ibcon#about to read 5, iclass 27, count 0 2006.258.00:26:31.18#ibcon#read 5, iclass 27, count 0 2006.258.00:26:31.18#ibcon#about to read 6, iclass 27, count 0 2006.258.00:26:31.18#ibcon#read 6, iclass 27, count 0 2006.258.00:26:31.18#ibcon#end of sib2, iclass 27, count 0 2006.258.00:26:31.18#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:26:31.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:26:31.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:26:31.18#ibcon#*before write, iclass 27, count 0 2006.258.00:26:31.18#ibcon#enter sib2, iclass 27, count 0 2006.258.00:26:31.18#ibcon#flushed, iclass 27, count 0 2006.258.00:26:31.18#ibcon#about to write, iclass 27, count 0 2006.258.00:26:31.18#ibcon#wrote, iclass 27, count 0 2006.258.00:26:31.18#ibcon#about to read 3, iclass 27, count 0 2006.258.00:26:31.22#ibcon#read 3, iclass 27, count 0 2006.258.00:26:31.22#ibcon#about to read 4, iclass 27, count 0 2006.258.00:26:31.22#ibcon#read 4, iclass 27, count 0 2006.258.00:26:31.22#ibcon#about to read 5, iclass 27, count 0 2006.258.00:26:31.22#ibcon#read 5, iclass 27, count 0 2006.258.00:26:31.22#ibcon#about to read 6, iclass 27, count 0 2006.258.00:26:31.22#ibcon#read 6, iclass 27, count 0 2006.258.00:26:31.22#ibcon#end of sib2, iclass 27, count 0 2006.258.00:26:31.22#ibcon#*after write, iclass 27, count 0 2006.258.00:26:31.22#ibcon#*before return 0, iclass 27, count 0 2006.258.00:26:31.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:31.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:26:31.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:26:31.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:26:31.22$vck44/vb=5,4 2006.258.00:26:31.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.00:26:31.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.00:26:31.22#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:31.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:31.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:31.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:31.28#ibcon#enter wrdev, iclass 29, count 2 2006.258.00:26:31.28#ibcon#first serial, iclass 29, count 2 2006.258.00:26:31.28#ibcon#enter sib2, iclass 29, count 2 2006.258.00:26:31.28#ibcon#flushed, iclass 29, count 2 2006.258.00:26:31.28#ibcon#about to write, iclass 29, count 2 2006.258.00:26:31.28#ibcon#wrote, iclass 29, count 2 2006.258.00:26:31.28#ibcon#about to read 3, iclass 29, count 2 2006.258.00:26:31.30#ibcon#read 3, iclass 29, count 2 2006.258.00:26:31.30#ibcon#about to read 4, iclass 29, count 2 2006.258.00:26:31.30#ibcon#read 4, iclass 29, count 2 2006.258.00:26:31.30#ibcon#about to read 5, iclass 29, count 2 2006.258.00:26:31.30#ibcon#read 5, iclass 29, count 2 2006.258.00:26:31.30#ibcon#about to read 6, iclass 29, count 2 2006.258.00:26:31.30#ibcon#read 6, iclass 29, count 2 2006.258.00:26:31.30#ibcon#end of sib2, iclass 29, count 2 2006.258.00:26:31.30#ibcon#*mode == 0, iclass 29, count 2 2006.258.00:26:31.30#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.00:26:31.30#ibcon#[27=AT05-04\r\n] 2006.258.00:26:31.30#ibcon#*before write, iclass 29, count 2 2006.258.00:26:31.30#ibcon#enter sib2, iclass 29, count 2 2006.258.00:26:31.30#ibcon#flushed, iclass 29, count 2 2006.258.00:26:31.30#ibcon#about to write, iclass 29, count 2 2006.258.00:26:31.30#ibcon#wrote, iclass 29, count 2 2006.258.00:26:31.30#ibcon#about to read 3, iclass 29, count 2 2006.258.00:26:31.33#ibcon#read 3, iclass 29, count 2 2006.258.00:26:31.33#ibcon#about to read 4, iclass 29, count 2 2006.258.00:26:31.33#ibcon#read 4, iclass 29, count 2 2006.258.00:26:31.33#ibcon#about to read 5, iclass 29, count 2 2006.258.00:26:31.33#ibcon#read 5, iclass 29, count 2 2006.258.00:26:31.33#ibcon#about to read 6, iclass 29, count 2 2006.258.00:26:31.33#ibcon#read 6, iclass 29, count 2 2006.258.00:26:31.33#ibcon#end of sib2, iclass 29, count 2 2006.258.00:26:31.33#ibcon#*after write, iclass 29, count 2 2006.258.00:26:31.33#ibcon#*before return 0, iclass 29, count 2 2006.258.00:26:31.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:31.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:26:31.33#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.00:26:31.33#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:31.33#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:31.45#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:31.45#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:31.45#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:26:31.45#ibcon#first serial, iclass 29, count 0 2006.258.00:26:31.45#ibcon#enter sib2, iclass 29, count 0 2006.258.00:26:31.45#ibcon#flushed, iclass 29, count 0 2006.258.00:26:31.45#ibcon#about to write, iclass 29, count 0 2006.258.00:26:31.45#ibcon#wrote, iclass 29, count 0 2006.258.00:26:31.45#ibcon#about to read 3, iclass 29, count 0 2006.258.00:26:31.47#ibcon#read 3, iclass 29, count 0 2006.258.00:26:31.47#ibcon#about to read 4, iclass 29, count 0 2006.258.00:26:31.47#ibcon#read 4, iclass 29, count 0 2006.258.00:26:31.47#ibcon#about to read 5, iclass 29, count 0 2006.258.00:26:31.47#ibcon#read 5, iclass 29, count 0 2006.258.00:26:31.47#ibcon#about to read 6, iclass 29, count 0 2006.258.00:26:31.47#ibcon#read 6, iclass 29, count 0 2006.258.00:26:31.47#ibcon#end of sib2, iclass 29, count 0 2006.258.00:26:31.47#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:26:31.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:26:31.47#ibcon#[27=USB\r\n] 2006.258.00:26:31.47#ibcon#*before write, iclass 29, count 0 2006.258.00:26:31.47#ibcon#enter sib2, iclass 29, count 0 2006.258.00:26:31.47#ibcon#flushed, iclass 29, count 0 2006.258.00:26:31.47#ibcon#about to write, iclass 29, count 0 2006.258.00:26:31.47#ibcon#wrote, iclass 29, count 0 2006.258.00:26:31.47#ibcon#about to read 3, iclass 29, count 0 2006.258.00:26:31.50#ibcon#read 3, iclass 29, count 0 2006.258.00:26:31.50#ibcon#about to read 4, iclass 29, count 0 2006.258.00:26:31.50#ibcon#read 4, iclass 29, count 0 2006.258.00:26:31.50#ibcon#about to read 5, iclass 29, count 0 2006.258.00:26:31.50#ibcon#read 5, iclass 29, count 0 2006.258.00:26:31.50#ibcon#about to read 6, iclass 29, count 0 2006.258.00:26:31.50#ibcon#read 6, iclass 29, count 0 2006.258.00:26:31.50#ibcon#end of sib2, iclass 29, count 0 2006.258.00:26:31.50#ibcon#*after write, iclass 29, count 0 2006.258.00:26:31.50#ibcon#*before return 0, iclass 29, count 0 2006.258.00:26:31.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:31.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:26:31.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:26:31.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:26:31.50$vck44/vblo=6,719.99 2006.258.00:26:31.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.258.00:26:31.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.258.00:26:31.50#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:31.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:31.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:31.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:31.50#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:26:31.50#ibcon#first serial, iclass 31, count 0 2006.258.00:26:31.50#ibcon#enter sib2, iclass 31, count 0 2006.258.00:26:31.50#ibcon#flushed, iclass 31, count 0 2006.258.00:26:31.50#ibcon#about to write, iclass 31, count 0 2006.258.00:26:31.50#ibcon#wrote, iclass 31, count 0 2006.258.00:26:31.50#ibcon#about to read 3, iclass 31, count 0 2006.258.00:26:31.52#ibcon#read 3, iclass 31, count 0 2006.258.00:26:31.52#ibcon#about to read 4, iclass 31, count 0 2006.258.00:26:31.52#ibcon#read 4, iclass 31, count 0 2006.258.00:26:31.52#ibcon#about to read 5, iclass 31, count 0 2006.258.00:26:31.52#ibcon#read 5, iclass 31, count 0 2006.258.00:26:31.52#ibcon#about to read 6, iclass 31, count 0 2006.258.00:26:31.52#ibcon#read 6, iclass 31, count 0 2006.258.00:26:31.52#ibcon#end of sib2, iclass 31, count 0 2006.258.00:26:31.52#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:26:31.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:26:31.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:26:31.52#ibcon#*before write, iclass 31, count 0 2006.258.00:26:31.52#ibcon#enter sib2, iclass 31, count 0 2006.258.00:26:31.52#ibcon#flushed, iclass 31, count 0 2006.258.00:26:31.52#ibcon#about to write, iclass 31, count 0 2006.258.00:26:31.52#ibcon#wrote, iclass 31, count 0 2006.258.00:26:31.52#ibcon#about to read 3, iclass 31, count 0 2006.258.00:26:31.56#ibcon#read 3, iclass 31, count 0 2006.258.00:26:31.56#ibcon#about to read 4, iclass 31, count 0 2006.258.00:26:31.56#ibcon#read 4, iclass 31, count 0 2006.258.00:26:31.56#ibcon#about to read 5, iclass 31, count 0 2006.258.00:26:31.56#ibcon#read 5, iclass 31, count 0 2006.258.00:26:31.56#ibcon#about to read 6, iclass 31, count 0 2006.258.00:26:31.56#ibcon#read 6, iclass 31, count 0 2006.258.00:26:31.56#ibcon#end of sib2, iclass 31, count 0 2006.258.00:26:31.56#ibcon#*after write, iclass 31, count 0 2006.258.00:26:31.56#ibcon#*before return 0, iclass 31, count 0 2006.258.00:26:31.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:31.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:26:31.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:26:31.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:26:31.56$vck44/vb=6,4 2006.258.00:26:31.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.00:26:31.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.00:26:31.56#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:31.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:31.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:31.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:31.62#ibcon#enter wrdev, iclass 33, count 2 2006.258.00:26:31.62#ibcon#first serial, iclass 33, count 2 2006.258.00:26:31.62#ibcon#enter sib2, iclass 33, count 2 2006.258.00:26:31.62#ibcon#flushed, iclass 33, count 2 2006.258.00:26:31.62#ibcon#about to write, iclass 33, count 2 2006.258.00:26:31.62#ibcon#wrote, iclass 33, count 2 2006.258.00:26:31.62#ibcon#about to read 3, iclass 33, count 2 2006.258.00:26:31.64#ibcon#read 3, iclass 33, count 2 2006.258.00:26:31.64#ibcon#about to read 4, iclass 33, count 2 2006.258.00:26:31.64#ibcon#read 4, iclass 33, count 2 2006.258.00:26:31.64#ibcon#about to read 5, iclass 33, count 2 2006.258.00:26:31.64#ibcon#read 5, iclass 33, count 2 2006.258.00:26:31.64#ibcon#about to read 6, iclass 33, count 2 2006.258.00:26:31.64#ibcon#read 6, iclass 33, count 2 2006.258.00:26:31.64#ibcon#end of sib2, iclass 33, count 2 2006.258.00:26:31.64#ibcon#*mode == 0, iclass 33, count 2 2006.258.00:26:31.64#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.00:26:31.64#ibcon#[27=AT06-04\r\n] 2006.258.00:26:31.64#ibcon#*before write, iclass 33, count 2 2006.258.00:26:31.64#ibcon#enter sib2, iclass 33, count 2 2006.258.00:26:31.64#ibcon#flushed, iclass 33, count 2 2006.258.00:26:31.64#ibcon#about to write, iclass 33, count 2 2006.258.00:26:31.64#ibcon#wrote, iclass 33, count 2 2006.258.00:26:31.64#ibcon#about to read 3, iclass 33, count 2 2006.258.00:26:31.67#ibcon#read 3, iclass 33, count 2 2006.258.00:26:31.67#ibcon#about to read 4, iclass 33, count 2 2006.258.00:26:31.67#ibcon#read 4, iclass 33, count 2 2006.258.00:26:31.67#ibcon#about to read 5, iclass 33, count 2 2006.258.00:26:31.67#ibcon#read 5, iclass 33, count 2 2006.258.00:26:31.67#ibcon#about to read 6, iclass 33, count 2 2006.258.00:26:31.67#ibcon#read 6, iclass 33, count 2 2006.258.00:26:31.67#ibcon#end of sib2, iclass 33, count 2 2006.258.00:26:31.67#ibcon#*after write, iclass 33, count 2 2006.258.00:26:31.67#ibcon#*before return 0, iclass 33, count 2 2006.258.00:26:31.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:31.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:26:31.67#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.00:26:31.67#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:31.67#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:31.79#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:31.79#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:31.79#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:26:31.79#ibcon#first serial, iclass 33, count 0 2006.258.00:26:31.79#ibcon#enter sib2, iclass 33, count 0 2006.258.00:26:31.79#ibcon#flushed, iclass 33, count 0 2006.258.00:26:31.79#ibcon#about to write, iclass 33, count 0 2006.258.00:26:31.79#ibcon#wrote, iclass 33, count 0 2006.258.00:26:31.79#ibcon#about to read 3, iclass 33, count 0 2006.258.00:26:31.81#ibcon#read 3, iclass 33, count 0 2006.258.00:26:31.81#ibcon#about to read 4, iclass 33, count 0 2006.258.00:26:31.81#ibcon#read 4, iclass 33, count 0 2006.258.00:26:31.81#ibcon#about to read 5, iclass 33, count 0 2006.258.00:26:31.81#ibcon#read 5, iclass 33, count 0 2006.258.00:26:31.81#ibcon#about to read 6, iclass 33, count 0 2006.258.00:26:31.81#ibcon#read 6, iclass 33, count 0 2006.258.00:26:31.81#ibcon#end of sib2, iclass 33, count 0 2006.258.00:26:31.81#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:26:31.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:26:31.81#ibcon#[27=USB\r\n] 2006.258.00:26:31.81#ibcon#*before write, iclass 33, count 0 2006.258.00:26:31.81#ibcon#enter sib2, iclass 33, count 0 2006.258.00:26:31.81#ibcon#flushed, iclass 33, count 0 2006.258.00:26:31.81#ibcon#about to write, iclass 33, count 0 2006.258.00:26:31.81#ibcon#wrote, iclass 33, count 0 2006.258.00:26:31.81#ibcon#about to read 3, iclass 33, count 0 2006.258.00:26:31.84#ibcon#read 3, iclass 33, count 0 2006.258.00:26:31.84#ibcon#about to read 4, iclass 33, count 0 2006.258.00:26:31.84#ibcon#read 4, iclass 33, count 0 2006.258.00:26:31.84#ibcon#about to read 5, iclass 33, count 0 2006.258.00:26:31.84#ibcon#read 5, iclass 33, count 0 2006.258.00:26:31.84#ibcon#about to read 6, iclass 33, count 0 2006.258.00:26:31.84#ibcon#read 6, iclass 33, count 0 2006.258.00:26:31.84#ibcon#end of sib2, iclass 33, count 0 2006.258.00:26:31.84#ibcon#*after write, iclass 33, count 0 2006.258.00:26:31.84#ibcon#*before return 0, iclass 33, count 0 2006.258.00:26:31.84#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:31.84#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:26:31.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:26:31.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:26:31.84$vck44/vblo=7,734.99 2006.258.00:26:31.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.00:26:31.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.00:26:31.84#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:31.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:31.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:31.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:31.84#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:26:31.84#ibcon#first serial, iclass 35, count 0 2006.258.00:26:31.84#ibcon#enter sib2, iclass 35, count 0 2006.258.00:26:31.84#ibcon#flushed, iclass 35, count 0 2006.258.00:26:31.84#ibcon#about to write, iclass 35, count 0 2006.258.00:26:31.84#ibcon#wrote, iclass 35, count 0 2006.258.00:26:31.84#ibcon#about to read 3, iclass 35, count 0 2006.258.00:26:31.86#ibcon#read 3, iclass 35, count 0 2006.258.00:26:31.86#ibcon#about to read 4, iclass 35, count 0 2006.258.00:26:31.86#ibcon#read 4, iclass 35, count 0 2006.258.00:26:31.86#ibcon#about to read 5, iclass 35, count 0 2006.258.00:26:31.86#ibcon#read 5, iclass 35, count 0 2006.258.00:26:31.86#ibcon#about to read 6, iclass 35, count 0 2006.258.00:26:31.86#ibcon#read 6, iclass 35, count 0 2006.258.00:26:31.86#ibcon#end of sib2, iclass 35, count 0 2006.258.00:26:31.86#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:26:31.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:26:31.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:26:31.86#ibcon#*before write, iclass 35, count 0 2006.258.00:26:31.86#ibcon#enter sib2, iclass 35, count 0 2006.258.00:26:31.86#ibcon#flushed, iclass 35, count 0 2006.258.00:26:31.86#ibcon#about to write, iclass 35, count 0 2006.258.00:26:31.86#ibcon#wrote, iclass 35, count 0 2006.258.00:26:31.86#ibcon#about to read 3, iclass 35, count 0 2006.258.00:26:31.90#ibcon#read 3, iclass 35, count 0 2006.258.00:26:31.90#ibcon#about to read 4, iclass 35, count 0 2006.258.00:26:31.90#ibcon#read 4, iclass 35, count 0 2006.258.00:26:31.90#ibcon#about to read 5, iclass 35, count 0 2006.258.00:26:31.90#ibcon#read 5, iclass 35, count 0 2006.258.00:26:31.90#ibcon#about to read 6, iclass 35, count 0 2006.258.00:26:31.90#ibcon#read 6, iclass 35, count 0 2006.258.00:26:31.90#ibcon#end of sib2, iclass 35, count 0 2006.258.00:26:31.90#ibcon#*after write, iclass 35, count 0 2006.258.00:26:31.90#ibcon#*before return 0, iclass 35, count 0 2006.258.00:26:31.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:31.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:26:31.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:26:31.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:26:31.90$vck44/vb=7,4 2006.258.00:26:31.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.00:26:31.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.00:26:31.90#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:31.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:31.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:31.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:31.96#ibcon#enter wrdev, iclass 37, count 2 2006.258.00:26:31.96#ibcon#first serial, iclass 37, count 2 2006.258.00:26:31.96#ibcon#enter sib2, iclass 37, count 2 2006.258.00:26:31.96#ibcon#flushed, iclass 37, count 2 2006.258.00:26:31.96#ibcon#about to write, iclass 37, count 2 2006.258.00:26:31.96#ibcon#wrote, iclass 37, count 2 2006.258.00:26:31.96#ibcon#about to read 3, iclass 37, count 2 2006.258.00:26:31.98#ibcon#read 3, iclass 37, count 2 2006.258.00:26:31.98#ibcon#about to read 4, iclass 37, count 2 2006.258.00:26:31.98#ibcon#read 4, iclass 37, count 2 2006.258.00:26:31.98#ibcon#about to read 5, iclass 37, count 2 2006.258.00:26:31.98#ibcon#read 5, iclass 37, count 2 2006.258.00:26:31.98#ibcon#about to read 6, iclass 37, count 2 2006.258.00:26:31.98#ibcon#read 6, iclass 37, count 2 2006.258.00:26:31.98#ibcon#end of sib2, iclass 37, count 2 2006.258.00:26:31.98#ibcon#*mode == 0, iclass 37, count 2 2006.258.00:26:31.98#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.00:26:31.98#ibcon#[27=AT07-04\r\n] 2006.258.00:26:31.98#ibcon#*before write, iclass 37, count 2 2006.258.00:26:31.98#ibcon#enter sib2, iclass 37, count 2 2006.258.00:26:31.98#ibcon#flushed, iclass 37, count 2 2006.258.00:26:31.98#ibcon#about to write, iclass 37, count 2 2006.258.00:26:31.98#ibcon#wrote, iclass 37, count 2 2006.258.00:26:31.98#ibcon#about to read 3, iclass 37, count 2 2006.258.00:26:32.01#ibcon#read 3, iclass 37, count 2 2006.258.00:26:32.01#ibcon#about to read 4, iclass 37, count 2 2006.258.00:26:32.01#ibcon#read 4, iclass 37, count 2 2006.258.00:26:32.01#ibcon#about to read 5, iclass 37, count 2 2006.258.00:26:32.01#ibcon#read 5, iclass 37, count 2 2006.258.00:26:32.01#ibcon#about to read 6, iclass 37, count 2 2006.258.00:26:32.01#ibcon#read 6, iclass 37, count 2 2006.258.00:26:32.01#ibcon#end of sib2, iclass 37, count 2 2006.258.00:26:32.01#ibcon#*after write, iclass 37, count 2 2006.258.00:26:32.01#ibcon#*before return 0, iclass 37, count 2 2006.258.00:26:32.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:32.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:26:32.01#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.00:26:32.01#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:32.01#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:32.13#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:32.13#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:32.13#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:26:32.13#ibcon#first serial, iclass 37, count 0 2006.258.00:26:32.13#ibcon#enter sib2, iclass 37, count 0 2006.258.00:26:32.13#ibcon#flushed, iclass 37, count 0 2006.258.00:26:32.13#ibcon#about to write, iclass 37, count 0 2006.258.00:26:32.13#ibcon#wrote, iclass 37, count 0 2006.258.00:26:32.13#ibcon#about to read 3, iclass 37, count 0 2006.258.00:26:32.15#ibcon#read 3, iclass 37, count 0 2006.258.00:26:32.15#ibcon#about to read 4, iclass 37, count 0 2006.258.00:26:32.15#ibcon#read 4, iclass 37, count 0 2006.258.00:26:32.15#ibcon#about to read 5, iclass 37, count 0 2006.258.00:26:32.15#ibcon#read 5, iclass 37, count 0 2006.258.00:26:32.15#ibcon#about to read 6, iclass 37, count 0 2006.258.00:26:32.15#ibcon#read 6, iclass 37, count 0 2006.258.00:26:32.15#ibcon#end of sib2, iclass 37, count 0 2006.258.00:26:32.15#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:26:32.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:26:32.15#ibcon#[27=USB\r\n] 2006.258.00:26:32.15#ibcon#*before write, iclass 37, count 0 2006.258.00:26:32.15#ibcon#enter sib2, iclass 37, count 0 2006.258.00:26:32.15#ibcon#flushed, iclass 37, count 0 2006.258.00:26:32.15#ibcon#about to write, iclass 37, count 0 2006.258.00:26:32.15#ibcon#wrote, iclass 37, count 0 2006.258.00:26:32.15#ibcon#about to read 3, iclass 37, count 0 2006.258.00:26:32.18#ibcon#read 3, iclass 37, count 0 2006.258.00:26:32.18#ibcon#about to read 4, iclass 37, count 0 2006.258.00:26:32.18#ibcon#read 4, iclass 37, count 0 2006.258.00:26:32.18#ibcon#about to read 5, iclass 37, count 0 2006.258.00:26:32.18#ibcon#read 5, iclass 37, count 0 2006.258.00:26:32.18#ibcon#about to read 6, iclass 37, count 0 2006.258.00:26:32.18#ibcon#read 6, iclass 37, count 0 2006.258.00:26:32.18#ibcon#end of sib2, iclass 37, count 0 2006.258.00:26:32.18#ibcon#*after write, iclass 37, count 0 2006.258.00:26:32.18#ibcon#*before return 0, iclass 37, count 0 2006.258.00:26:32.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:32.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:26:32.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:26:32.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:26:32.18$vck44/vblo=8,744.99 2006.258.00:26:32.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.00:26:32.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.00:26:32.18#ibcon#ireg 17 cls_cnt 0 2006.258.00:26:32.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:32.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:32.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:32.18#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:26:32.18#ibcon#first serial, iclass 39, count 0 2006.258.00:26:32.18#ibcon#enter sib2, iclass 39, count 0 2006.258.00:26:32.18#ibcon#flushed, iclass 39, count 0 2006.258.00:26:32.18#ibcon#about to write, iclass 39, count 0 2006.258.00:26:32.18#ibcon#wrote, iclass 39, count 0 2006.258.00:26:32.18#ibcon#about to read 3, iclass 39, count 0 2006.258.00:26:32.20#ibcon#read 3, iclass 39, count 0 2006.258.00:26:32.20#ibcon#about to read 4, iclass 39, count 0 2006.258.00:26:32.20#ibcon#read 4, iclass 39, count 0 2006.258.00:26:32.20#ibcon#about to read 5, iclass 39, count 0 2006.258.00:26:32.20#ibcon#read 5, iclass 39, count 0 2006.258.00:26:32.20#ibcon#about to read 6, iclass 39, count 0 2006.258.00:26:32.20#ibcon#read 6, iclass 39, count 0 2006.258.00:26:32.20#ibcon#end of sib2, iclass 39, count 0 2006.258.00:26:32.20#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:26:32.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:26:32.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:26:32.20#ibcon#*before write, iclass 39, count 0 2006.258.00:26:32.20#ibcon#enter sib2, iclass 39, count 0 2006.258.00:26:32.20#ibcon#flushed, iclass 39, count 0 2006.258.00:26:32.20#ibcon#about to write, iclass 39, count 0 2006.258.00:26:32.20#ibcon#wrote, iclass 39, count 0 2006.258.00:26:32.20#ibcon#about to read 3, iclass 39, count 0 2006.258.00:26:32.24#ibcon#read 3, iclass 39, count 0 2006.258.00:26:32.24#ibcon#about to read 4, iclass 39, count 0 2006.258.00:26:32.24#ibcon#read 4, iclass 39, count 0 2006.258.00:26:32.24#ibcon#about to read 5, iclass 39, count 0 2006.258.00:26:32.24#ibcon#read 5, iclass 39, count 0 2006.258.00:26:32.24#ibcon#about to read 6, iclass 39, count 0 2006.258.00:26:32.24#ibcon#read 6, iclass 39, count 0 2006.258.00:26:32.24#ibcon#end of sib2, iclass 39, count 0 2006.258.00:26:32.24#ibcon#*after write, iclass 39, count 0 2006.258.00:26:32.24#ibcon#*before return 0, iclass 39, count 0 2006.258.00:26:32.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:32.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:26:32.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:26:32.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:26:32.24$vck44/vb=8,4 2006.258.00:26:32.24#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.00:26:32.24#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.00:26:32.24#ibcon#ireg 11 cls_cnt 2 2006.258.00:26:32.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:32.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:32.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:32.30#ibcon#enter wrdev, iclass 3, count 2 2006.258.00:26:32.30#ibcon#first serial, iclass 3, count 2 2006.258.00:26:32.30#ibcon#enter sib2, iclass 3, count 2 2006.258.00:26:32.30#ibcon#flushed, iclass 3, count 2 2006.258.00:26:32.30#ibcon#about to write, iclass 3, count 2 2006.258.00:26:32.30#ibcon#wrote, iclass 3, count 2 2006.258.00:26:32.30#ibcon#about to read 3, iclass 3, count 2 2006.258.00:26:32.32#ibcon#read 3, iclass 3, count 2 2006.258.00:26:32.32#ibcon#about to read 4, iclass 3, count 2 2006.258.00:26:32.32#ibcon#read 4, iclass 3, count 2 2006.258.00:26:32.32#ibcon#about to read 5, iclass 3, count 2 2006.258.00:26:32.32#ibcon#read 5, iclass 3, count 2 2006.258.00:26:32.32#ibcon#about to read 6, iclass 3, count 2 2006.258.00:26:32.32#ibcon#read 6, iclass 3, count 2 2006.258.00:26:32.32#ibcon#end of sib2, iclass 3, count 2 2006.258.00:26:32.32#ibcon#*mode == 0, iclass 3, count 2 2006.258.00:26:32.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.00:26:32.32#ibcon#[27=AT08-04\r\n] 2006.258.00:26:32.32#ibcon#*before write, iclass 3, count 2 2006.258.00:26:32.32#ibcon#enter sib2, iclass 3, count 2 2006.258.00:26:32.32#ibcon#flushed, iclass 3, count 2 2006.258.00:26:32.32#ibcon#about to write, iclass 3, count 2 2006.258.00:26:32.32#ibcon#wrote, iclass 3, count 2 2006.258.00:26:32.32#ibcon#about to read 3, iclass 3, count 2 2006.258.00:26:32.35#ibcon#read 3, iclass 3, count 2 2006.258.00:26:32.35#ibcon#about to read 4, iclass 3, count 2 2006.258.00:26:32.35#ibcon#read 4, iclass 3, count 2 2006.258.00:26:32.35#ibcon#about to read 5, iclass 3, count 2 2006.258.00:26:32.35#ibcon#read 5, iclass 3, count 2 2006.258.00:26:32.35#ibcon#about to read 6, iclass 3, count 2 2006.258.00:26:32.35#ibcon#read 6, iclass 3, count 2 2006.258.00:26:32.35#ibcon#end of sib2, iclass 3, count 2 2006.258.00:26:32.35#ibcon#*after write, iclass 3, count 2 2006.258.00:26:32.35#ibcon#*before return 0, iclass 3, count 2 2006.258.00:26:32.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:32.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:26:32.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.00:26:32.35#ibcon#ireg 7 cls_cnt 0 2006.258.00:26:32.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:32.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:32.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:32.47#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:26:32.47#ibcon#first serial, iclass 3, count 0 2006.258.00:26:32.47#ibcon#enter sib2, iclass 3, count 0 2006.258.00:26:32.47#ibcon#flushed, iclass 3, count 0 2006.258.00:26:32.47#ibcon#about to write, iclass 3, count 0 2006.258.00:26:32.47#ibcon#wrote, iclass 3, count 0 2006.258.00:26:32.47#ibcon#about to read 3, iclass 3, count 0 2006.258.00:26:32.49#ibcon#read 3, iclass 3, count 0 2006.258.00:26:32.49#ibcon#about to read 4, iclass 3, count 0 2006.258.00:26:32.49#ibcon#read 4, iclass 3, count 0 2006.258.00:26:32.49#ibcon#about to read 5, iclass 3, count 0 2006.258.00:26:32.49#ibcon#read 5, iclass 3, count 0 2006.258.00:26:32.49#ibcon#about to read 6, iclass 3, count 0 2006.258.00:26:32.49#ibcon#read 6, iclass 3, count 0 2006.258.00:26:32.49#ibcon#end of sib2, iclass 3, count 0 2006.258.00:26:32.49#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:26:32.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:26:32.49#ibcon#[27=USB\r\n] 2006.258.00:26:32.49#ibcon#*before write, iclass 3, count 0 2006.258.00:26:32.49#ibcon#enter sib2, iclass 3, count 0 2006.258.00:26:32.49#ibcon#flushed, iclass 3, count 0 2006.258.00:26:32.49#ibcon#about to write, iclass 3, count 0 2006.258.00:26:32.49#ibcon#wrote, iclass 3, count 0 2006.258.00:26:32.49#ibcon#about to read 3, iclass 3, count 0 2006.258.00:26:32.52#ibcon#read 3, iclass 3, count 0 2006.258.00:26:32.52#ibcon#about to read 4, iclass 3, count 0 2006.258.00:26:32.52#ibcon#read 4, iclass 3, count 0 2006.258.00:26:32.52#ibcon#about to read 5, iclass 3, count 0 2006.258.00:26:32.52#ibcon#read 5, iclass 3, count 0 2006.258.00:26:32.52#ibcon#about to read 6, iclass 3, count 0 2006.258.00:26:32.52#ibcon#read 6, iclass 3, count 0 2006.258.00:26:32.52#ibcon#end of sib2, iclass 3, count 0 2006.258.00:26:32.52#ibcon#*after write, iclass 3, count 0 2006.258.00:26:32.52#ibcon#*before return 0, iclass 3, count 0 2006.258.00:26:32.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:32.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:26:32.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:26:32.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:26:32.52$vck44/vabw=wide 2006.258.00:26:32.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.00:26:32.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.00:26:32.52#ibcon#ireg 8 cls_cnt 0 2006.258.00:26:32.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:32.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:32.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:32.52#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:26:32.52#ibcon#first serial, iclass 5, count 0 2006.258.00:26:32.52#ibcon#enter sib2, iclass 5, count 0 2006.258.00:26:32.52#ibcon#flushed, iclass 5, count 0 2006.258.00:26:32.52#ibcon#about to write, iclass 5, count 0 2006.258.00:26:32.52#ibcon#wrote, iclass 5, count 0 2006.258.00:26:32.52#ibcon#about to read 3, iclass 5, count 0 2006.258.00:26:32.54#ibcon#read 3, iclass 5, count 0 2006.258.00:26:32.54#ibcon#about to read 4, iclass 5, count 0 2006.258.00:26:32.54#ibcon#read 4, iclass 5, count 0 2006.258.00:26:32.54#ibcon#about to read 5, iclass 5, count 0 2006.258.00:26:32.54#ibcon#read 5, iclass 5, count 0 2006.258.00:26:32.54#ibcon#about to read 6, iclass 5, count 0 2006.258.00:26:32.54#ibcon#read 6, iclass 5, count 0 2006.258.00:26:32.54#ibcon#end of sib2, iclass 5, count 0 2006.258.00:26:32.54#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:26:32.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:26:32.54#ibcon#[25=BW32\r\n] 2006.258.00:26:32.54#ibcon#*before write, iclass 5, count 0 2006.258.00:26:32.54#ibcon#enter sib2, iclass 5, count 0 2006.258.00:26:32.54#ibcon#flushed, iclass 5, count 0 2006.258.00:26:32.54#ibcon#about to write, iclass 5, count 0 2006.258.00:26:32.54#ibcon#wrote, iclass 5, count 0 2006.258.00:26:32.54#ibcon#about to read 3, iclass 5, count 0 2006.258.00:26:32.57#ibcon#read 3, iclass 5, count 0 2006.258.00:26:32.57#ibcon#about to read 4, iclass 5, count 0 2006.258.00:26:32.57#ibcon#read 4, iclass 5, count 0 2006.258.00:26:32.57#ibcon#about to read 5, iclass 5, count 0 2006.258.00:26:32.57#ibcon#read 5, iclass 5, count 0 2006.258.00:26:32.57#ibcon#about to read 6, iclass 5, count 0 2006.258.00:26:32.57#ibcon#read 6, iclass 5, count 0 2006.258.00:26:32.57#ibcon#end of sib2, iclass 5, count 0 2006.258.00:26:32.57#ibcon#*after write, iclass 5, count 0 2006.258.00:26:32.57#ibcon#*before return 0, iclass 5, count 0 2006.258.00:26:32.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:32.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:26:32.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:26:32.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:26:32.57$vck44/vbbw=wide 2006.258.00:26:32.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.00:26:32.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.00:26:32.57#ibcon#ireg 8 cls_cnt 0 2006.258.00:26:32.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:26:32.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:26:32.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:26:32.64#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:26:32.64#ibcon#first serial, iclass 7, count 0 2006.258.00:26:32.64#ibcon#enter sib2, iclass 7, count 0 2006.258.00:26:32.64#ibcon#flushed, iclass 7, count 0 2006.258.00:26:32.64#ibcon#about to write, iclass 7, count 0 2006.258.00:26:32.64#ibcon#wrote, iclass 7, count 0 2006.258.00:26:32.64#ibcon#about to read 3, iclass 7, count 0 2006.258.00:26:32.66#ibcon#read 3, iclass 7, count 0 2006.258.00:26:32.66#ibcon#about to read 4, iclass 7, count 0 2006.258.00:26:32.66#ibcon#read 4, iclass 7, count 0 2006.258.00:26:32.66#ibcon#about to read 5, iclass 7, count 0 2006.258.00:26:32.66#ibcon#read 5, iclass 7, count 0 2006.258.00:26:32.66#ibcon#about to read 6, iclass 7, count 0 2006.258.00:26:32.66#ibcon#read 6, iclass 7, count 0 2006.258.00:26:32.66#ibcon#end of sib2, iclass 7, count 0 2006.258.00:26:32.66#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:26:32.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:26:32.66#ibcon#[27=BW32\r\n] 2006.258.00:26:32.66#ibcon#*before write, iclass 7, count 0 2006.258.00:26:32.66#ibcon#enter sib2, iclass 7, count 0 2006.258.00:26:32.66#ibcon#flushed, iclass 7, count 0 2006.258.00:26:32.66#ibcon#about to write, iclass 7, count 0 2006.258.00:26:32.66#ibcon#wrote, iclass 7, count 0 2006.258.00:26:32.66#ibcon#about to read 3, iclass 7, count 0 2006.258.00:26:32.69#ibcon#read 3, iclass 7, count 0 2006.258.00:26:32.69#ibcon#about to read 4, iclass 7, count 0 2006.258.00:26:32.69#ibcon#read 4, iclass 7, count 0 2006.258.00:26:32.69#ibcon#about to read 5, iclass 7, count 0 2006.258.00:26:32.69#ibcon#read 5, iclass 7, count 0 2006.258.00:26:32.69#ibcon#about to read 6, iclass 7, count 0 2006.258.00:26:32.69#ibcon#read 6, iclass 7, count 0 2006.258.00:26:32.69#ibcon#end of sib2, iclass 7, count 0 2006.258.00:26:32.69#ibcon#*after write, iclass 7, count 0 2006.258.00:26:32.69#ibcon#*before return 0, iclass 7, count 0 2006.258.00:26:32.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:26:32.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:26:32.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:26:32.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:26:32.69$setupk4/ifdk4 2006.258.00:26:32.69$ifdk4/lo= 2006.258.00:26:32.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:26:32.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:26:32.69$ifdk4/patch= 2006.258.00:26:32.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:26:32.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:26:32.69$setupk4/!*+20s 2006.258.00:26:37.71#abcon#<5=/02 1.4 4.3 21.97 781016.1\r\n> 2006.258.00:26:37.73#abcon#{5=INTERFACE CLEAR} 2006.258.00:26:37.79#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:26:40.14#trakl#Source acquired 2006.258.00:26:40.14#flagr#flagr/antenna,acquired 2006.258.00:26:47.20$setupk4/"tpicd 2006.258.00:26:47.20$setupk4/echo=off 2006.258.00:26:47.20$setupk4/xlog=off 2006.258.00:26:47.20:!2006.258.00:28:44 2006.258.00:28:44.00:preob 2006.258.00:28:44.14/onsource/TRACKING 2006.258.00:28:44.14:!2006.258.00:28:54 2006.258.00:28:54.00:"tape 2006.258.00:28:54.00:"st=record 2006.258.00:28:54.00:data_valid=on 2006.258.00:28:54.00:midob 2006.258.00:28:55.14/onsource/TRACKING 2006.258.00:28:55.14/wx/22.06,1016.1,78 2006.258.00:28:55.29/cable/+6.4809E-03 2006.258.00:28:56.38/va/01,08,usb,yes,31,33 2006.258.00:28:56.38/va/02,07,usb,yes,34,34 2006.258.00:28:56.38/va/03,08,usb,yes,30,32 2006.258.00:28:56.38/va/04,07,usb,yes,35,36 2006.258.00:28:56.38/va/05,04,usb,yes,31,31 2006.258.00:28:56.38/va/06,04,usb,yes,34,34 2006.258.00:28:56.38/va/07,04,usb,yes,35,36 2006.258.00:28:56.38/va/08,04,usb,yes,29,36 2006.258.00:28:56.61/valo/01,524.99,yes,locked 2006.258.00:28:56.61/valo/02,534.99,yes,locked 2006.258.00:28:56.61/valo/03,564.99,yes,locked 2006.258.00:28:56.61/valo/04,624.99,yes,locked 2006.258.00:28:56.61/valo/05,734.99,yes,locked 2006.258.00:28:56.61/valo/06,814.99,yes,locked 2006.258.00:28:56.61/valo/07,864.99,yes,locked 2006.258.00:28:56.61/valo/08,884.99,yes,locked 2006.258.00:28:57.70/vb/01,04,usb,yes,31,29 2006.258.00:28:57.70/vb/02,05,usb,yes,29,29 2006.258.00:28:57.70/vb/03,04,usb,yes,30,33 2006.258.00:28:57.70/vb/04,05,usb,yes,30,29 2006.258.00:28:57.70/vb/05,04,usb,yes,27,29 2006.258.00:28:57.70/vb/06,04,usb,yes,31,28 2006.258.00:28:57.70/vb/07,04,usb,yes,31,31 2006.258.00:28:57.70/vb/08,04,usb,yes,29,32 2006.258.00:28:57.94/vblo/01,629.99,yes,locked 2006.258.00:28:57.94/vblo/02,634.99,yes,locked 2006.258.00:28:57.94/vblo/03,649.99,yes,locked 2006.258.00:28:57.94/vblo/04,679.99,yes,locked 2006.258.00:28:57.94/vblo/05,709.99,yes,locked 2006.258.00:28:57.94/vblo/06,719.99,yes,locked 2006.258.00:28:57.94/vblo/07,734.99,yes,locked 2006.258.00:28:57.94/vblo/08,744.99,yes,locked 2006.258.00:28:58.09/vabw/8 2006.258.00:28:58.24/vbbw/8 2006.258.00:28:58.33/xfe/off,on,15.0 2006.258.00:28:58.71/ifatt/23,28,28,28 2006.258.00:28:59.07/fmout-gps/S +4.57E-07 2006.258.00:28:59.11:!2006.258.00:30:44 2006.258.00:30:44.00:data_valid=off 2006.258.00:30:44.00:"et 2006.258.00:30:44.00:!+3s 2006.258.00:30:47.02:"tape 2006.258.00:30:47.02:postob 2006.258.00:30:47.20/cable/+6.4798E-03 2006.258.00:30:47.20/wx/22.12,1016.2,75 2006.258.00:30:47.26/fmout-gps/S +4.56E-07 2006.258.00:30:47.26:scan_name=258-0032,jd0609,60 2006.258.00:30:47.26:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.258.00:30:48.14#flagr#flagr/antenna,new-source 2006.258.00:30:48.14:checkk5 2006.258.00:30:48.49/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:30:48.90/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:30:49.33/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:30:49.74/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:30:50.11/chk_obsdata//k5ts1/T2580028??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.258.00:30:50.52/chk_obsdata//k5ts2/T2580028??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.258.00:30:50.93/chk_obsdata//k5ts3/T2580028??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.258.00:30:51.34/chk_obsdata//k5ts4/T2580028??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.258.00:30:52.06/k5log//k5ts1_log_newline 2006.258.00:30:52.76/k5log//k5ts2_log_newline 2006.258.00:30:53.49/k5log//k5ts3_log_newline 2006.258.00:30:54.20/k5log//k5ts4_log_newline 2006.258.00:30:54.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:30:54.22:setupk4=1 2006.258.00:30:54.22$setupk4/echo=on 2006.258.00:30:54.22$setupk4/pcalon 2006.258.00:30:54.22$pcalon/"no phase cal control is implemented here 2006.258.00:30:54.22$setupk4/"tpicd=stop 2006.258.00:30:54.22$setupk4/"rec=synch_on 2006.258.00:30:54.22$setupk4/"rec_mode=128 2006.258.00:30:54.22$setupk4/!* 2006.258.00:30:54.22$setupk4/recpk4 2006.258.00:30:54.22$recpk4/recpatch= 2006.258.00:30:54.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:30:54.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:30:54.22$setupk4/vck44 2006.258.00:30:54.22$vck44/valo=1,524.99 2006.258.00:30:54.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.258.00:30:54.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.258.00:30:54.22#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:54.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:54.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:54.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:54.22#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:30:54.22#ibcon#first serial, iclass 10, count 0 2006.258.00:30:54.22#ibcon#enter sib2, iclass 10, count 0 2006.258.00:30:54.22#ibcon#flushed, iclass 10, count 0 2006.258.00:30:54.22#ibcon#about to write, iclass 10, count 0 2006.258.00:30:54.22#ibcon#wrote, iclass 10, count 0 2006.258.00:30:54.22#ibcon#about to read 3, iclass 10, count 0 2006.258.00:30:54.24#ibcon#read 3, iclass 10, count 0 2006.258.00:30:54.24#ibcon#about to read 4, iclass 10, count 0 2006.258.00:30:54.24#ibcon#read 4, iclass 10, count 0 2006.258.00:30:54.24#ibcon#about to read 5, iclass 10, count 0 2006.258.00:30:54.24#ibcon#read 5, iclass 10, count 0 2006.258.00:30:54.24#ibcon#about to read 6, iclass 10, count 0 2006.258.00:30:54.24#ibcon#read 6, iclass 10, count 0 2006.258.00:30:54.24#ibcon#end of sib2, iclass 10, count 0 2006.258.00:30:54.24#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:30:54.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:30:54.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:30:54.24#ibcon#*before write, iclass 10, count 0 2006.258.00:30:54.24#ibcon#enter sib2, iclass 10, count 0 2006.258.00:30:54.24#ibcon#flushed, iclass 10, count 0 2006.258.00:30:54.24#ibcon#about to write, iclass 10, count 0 2006.258.00:30:54.24#ibcon#wrote, iclass 10, count 0 2006.258.00:30:54.24#ibcon#about to read 3, iclass 10, count 0 2006.258.00:30:54.29#ibcon#read 3, iclass 10, count 0 2006.258.00:30:54.29#ibcon#about to read 4, iclass 10, count 0 2006.258.00:30:54.29#ibcon#read 4, iclass 10, count 0 2006.258.00:30:54.29#ibcon#about to read 5, iclass 10, count 0 2006.258.00:30:54.29#ibcon#read 5, iclass 10, count 0 2006.258.00:30:54.29#ibcon#about to read 6, iclass 10, count 0 2006.258.00:30:54.29#ibcon#read 6, iclass 10, count 0 2006.258.00:30:54.29#ibcon#end of sib2, iclass 10, count 0 2006.258.00:30:54.29#ibcon#*after write, iclass 10, count 0 2006.258.00:30:54.29#ibcon#*before return 0, iclass 10, count 0 2006.258.00:30:54.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:54.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:54.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:30:54.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:30:54.29$vck44/va=1,8 2006.258.00:30:54.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.258.00:30:54.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.258.00:30:54.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:54.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:54.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:54.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:54.29#ibcon#enter wrdev, iclass 12, count 2 2006.258.00:30:54.29#ibcon#first serial, iclass 12, count 2 2006.258.00:30:54.29#ibcon#enter sib2, iclass 12, count 2 2006.258.00:30:54.29#ibcon#flushed, iclass 12, count 2 2006.258.00:30:54.29#ibcon#about to write, iclass 12, count 2 2006.258.00:30:54.29#ibcon#wrote, iclass 12, count 2 2006.258.00:30:54.29#ibcon#about to read 3, iclass 12, count 2 2006.258.00:30:54.31#ibcon#read 3, iclass 12, count 2 2006.258.00:30:54.31#ibcon#about to read 4, iclass 12, count 2 2006.258.00:30:54.31#ibcon#read 4, iclass 12, count 2 2006.258.00:30:54.31#ibcon#about to read 5, iclass 12, count 2 2006.258.00:30:54.31#ibcon#read 5, iclass 12, count 2 2006.258.00:30:54.31#ibcon#about to read 6, iclass 12, count 2 2006.258.00:30:54.31#ibcon#read 6, iclass 12, count 2 2006.258.00:30:54.31#ibcon#end of sib2, iclass 12, count 2 2006.258.00:30:54.31#ibcon#*mode == 0, iclass 12, count 2 2006.258.00:30:54.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.258.00:30:54.31#ibcon#[25=AT01-08\r\n] 2006.258.00:30:54.31#ibcon#*before write, iclass 12, count 2 2006.258.00:30:54.31#ibcon#enter sib2, iclass 12, count 2 2006.258.00:30:54.31#ibcon#flushed, iclass 12, count 2 2006.258.00:30:54.31#ibcon#about to write, iclass 12, count 2 2006.258.00:30:54.31#ibcon#wrote, iclass 12, count 2 2006.258.00:30:54.31#ibcon#about to read 3, iclass 12, count 2 2006.258.00:30:54.34#ibcon#read 3, iclass 12, count 2 2006.258.00:30:54.34#ibcon#about to read 4, iclass 12, count 2 2006.258.00:30:54.34#ibcon#read 4, iclass 12, count 2 2006.258.00:30:54.34#ibcon#about to read 5, iclass 12, count 2 2006.258.00:30:54.34#ibcon#read 5, iclass 12, count 2 2006.258.00:30:54.34#ibcon#about to read 6, iclass 12, count 2 2006.258.00:30:54.34#ibcon#read 6, iclass 12, count 2 2006.258.00:30:54.34#ibcon#end of sib2, iclass 12, count 2 2006.258.00:30:54.34#ibcon#*after write, iclass 12, count 2 2006.258.00:30:54.34#ibcon#*before return 0, iclass 12, count 2 2006.258.00:30:54.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:54.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:54.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.258.00:30:54.34#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:54.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:54.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:54.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:54.46#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:30:54.46#ibcon#first serial, iclass 12, count 0 2006.258.00:30:54.46#ibcon#enter sib2, iclass 12, count 0 2006.258.00:30:54.46#ibcon#flushed, iclass 12, count 0 2006.258.00:30:54.46#ibcon#about to write, iclass 12, count 0 2006.258.00:30:54.46#ibcon#wrote, iclass 12, count 0 2006.258.00:30:54.46#ibcon#about to read 3, iclass 12, count 0 2006.258.00:30:54.48#ibcon#read 3, iclass 12, count 0 2006.258.00:30:54.48#ibcon#about to read 4, iclass 12, count 0 2006.258.00:30:54.48#ibcon#read 4, iclass 12, count 0 2006.258.00:30:54.48#ibcon#about to read 5, iclass 12, count 0 2006.258.00:30:54.48#ibcon#read 5, iclass 12, count 0 2006.258.00:30:54.48#ibcon#about to read 6, iclass 12, count 0 2006.258.00:30:54.48#ibcon#read 6, iclass 12, count 0 2006.258.00:30:54.48#ibcon#end of sib2, iclass 12, count 0 2006.258.00:30:54.48#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:30:54.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:30:54.48#ibcon#[25=USB\r\n] 2006.258.00:30:54.48#ibcon#*before write, iclass 12, count 0 2006.258.00:30:54.48#ibcon#enter sib2, iclass 12, count 0 2006.258.00:30:54.48#ibcon#flushed, iclass 12, count 0 2006.258.00:30:54.48#ibcon#about to write, iclass 12, count 0 2006.258.00:30:54.48#ibcon#wrote, iclass 12, count 0 2006.258.00:30:54.48#ibcon#about to read 3, iclass 12, count 0 2006.258.00:30:54.51#ibcon#read 3, iclass 12, count 0 2006.258.00:30:54.51#ibcon#about to read 4, iclass 12, count 0 2006.258.00:30:54.51#ibcon#read 4, iclass 12, count 0 2006.258.00:30:54.51#ibcon#about to read 5, iclass 12, count 0 2006.258.00:30:54.51#ibcon#read 5, iclass 12, count 0 2006.258.00:30:54.51#ibcon#about to read 6, iclass 12, count 0 2006.258.00:30:54.51#ibcon#read 6, iclass 12, count 0 2006.258.00:30:54.51#ibcon#end of sib2, iclass 12, count 0 2006.258.00:30:54.51#ibcon#*after write, iclass 12, count 0 2006.258.00:30:54.51#ibcon#*before return 0, iclass 12, count 0 2006.258.00:30:54.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:54.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:54.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:30:54.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:30:54.51$vck44/valo=2,534.99 2006.258.00:30:54.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.00:30:54.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.00:30:54.51#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:54.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:54.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:54.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:54.51#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:30:54.51#ibcon#first serial, iclass 14, count 0 2006.258.00:30:54.51#ibcon#enter sib2, iclass 14, count 0 2006.258.00:30:54.51#ibcon#flushed, iclass 14, count 0 2006.258.00:30:54.51#ibcon#about to write, iclass 14, count 0 2006.258.00:30:54.51#ibcon#wrote, iclass 14, count 0 2006.258.00:30:54.51#ibcon#about to read 3, iclass 14, count 0 2006.258.00:30:54.53#ibcon#read 3, iclass 14, count 0 2006.258.00:30:54.53#ibcon#about to read 4, iclass 14, count 0 2006.258.00:30:54.53#ibcon#read 4, iclass 14, count 0 2006.258.00:30:54.53#ibcon#about to read 5, iclass 14, count 0 2006.258.00:30:54.53#ibcon#read 5, iclass 14, count 0 2006.258.00:30:54.53#ibcon#about to read 6, iclass 14, count 0 2006.258.00:30:54.53#ibcon#read 6, iclass 14, count 0 2006.258.00:30:54.53#ibcon#end of sib2, iclass 14, count 0 2006.258.00:30:54.53#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:30:54.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:30:54.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:30:54.53#ibcon#*before write, iclass 14, count 0 2006.258.00:30:54.53#ibcon#enter sib2, iclass 14, count 0 2006.258.00:30:54.53#ibcon#flushed, iclass 14, count 0 2006.258.00:30:54.53#ibcon#about to write, iclass 14, count 0 2006.258.00:30:54.53#ibcon#wrote, iclass 14, count 0 2006.258.00:30:54.53#ibcon#about to read 3, iclass 14, count 0 2006.258.00:30:54.57#ibcon#read 3, iclass 14, count 0 2006.258.00:30:54.57#ibcon#about to read 4, iclass 14, count 0 2006.258.00:30:54.57#ibcon#read 4, iclass 14, count 0 2006.258.00:30:54.57#ibcon#about to read 5, iclass 14, count 0 2006.258.00:30:54.57#ibcon#read 5, iclass 14, count 0 2006.258.00:30:54.57#ibcon#about to read 6, iclass 14, count 0 2006.258.00:30:54.57#ibcon#read 6, iclass 14, count 0 2006.258.00:30:54.57#ibcon#end of sib2, iclass 14, count 0 2006.258.00:30:54.57#ibcon#*after write, iclass 14, count 0 2006.258.00:30:54.57#ibcon#*before return 0, iclass 14, count 0 2006.258.00:30:54.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:54.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:54.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:30:54.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:30:54.57$vck44/va=2,7 2006.258.00:30:54.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.258.00:30:54.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.258.00:30:54.57#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:54.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:54.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:54.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:54.63#ibcon#enter wrdev, iclass 16, count 2 2006.258.00:30:54.63#ibcon#first serial, iclass 16, count 2 2006.258.00:30:54.63#ibcon#enter sib2, iclass 16, count 2 2006.258.00:30:54.63#ibcon#flushed, iclass 16, count 2 2006.258.00:30:54.63#ibcon#about to write, iclass 16, count 2 2006.258.00:30:54.63#ibcon#wrote, iclass 16, count 2 2006.258.00:30:54.63#ibcon#about to read 3, iclass 16, count 2 2006.258.00:30:54.65#ibcon#read 3, iclass 16, count 2 2006.258.00:30:54.65#ibcon#about to read 4, iclass 16, count 2 2006.258.00:30:54.65#ibcon#read 4, iclass 16, count 2 2006.258.00:30:54.65#ibcon#about to read 5, iclass 16, count 2 2006.258.00:30:54.65#ibcon#read 5, iclass 16, count 2 2006.258.00:30:54.65#ibcon#about to read 6, iclass 16, count 2 2006.258.00:30:54.65#ibcon#read 6, iclass 16, count 2 2006.258.00:30:54.65#ibcon#end of sib2, iclass 16, count 2 2006.258.00:30:54.65#ibcon#*mode == 0, iclass 16, count 2 2006.258.00:30:54.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.258.00:30:54.65#ibcon#[25=AT02-07\r\n] 2006.258.00:30:54.65#ibcon#*before write, iclass 16, count 2 2006.258.00:30:54.65#ibcon#enter sib2, iclass 16, count 2 2006.258.00:30:54.65#ibcon#flushed, iclass 16, count 2 2006.258.00:30:54.65#ibcon#about to write, iclass 16, count 2 2006.258.00:30:54.65#ibcon#wrote, iclass 16, count 2 2006.258.00:30:54.65#ibcon#about to read 3, iclass 16, count 2 2006.258.00:30:54.68#ibcon#read 3, iclass 16, count 2 2006.258.00:30:54.68#ibcon#about to read 4, iclass 16, count 2 2006.258.00:30:54.68#ibcon#read 4, iclass 16, count 2 2006.258.00:30:54.68#ibcon#about to read 5, iclass 16, count 2 2006.258.00:30:54.68#ibcon#read 5, iclass 16, count 2 2006.258.00:30:54.68#ibcon#about to read 6, iclass 16, count 2 2006.258.00:30:54.68#ibcon#read 6, iclass 16, count 2 2006.258.00:30:54.68#ibcon#end of sib2, iclass 16, count 2 2006.258.00:30:54.68#ibcon#*after write, iclass 16, count 2 2006.258.00:30:54.68#ibcon#*before return 0, iclass 16, count 2 2006.258.00:30:54.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:54.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:54.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.258.00:30:54.68#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:54.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:54.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:54.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:54.80#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:30:54.80#ibcon#first serial, iclass 16, count 0 2006.258.00:30:54.80#ibcon#enter sib2, iclass 16, count 0 2006.258.00:30:54.80#ibcon#flushed, iclass 16, count 0 2006.258.00:30:54.80#ibcon#about to write, iclass 16, count 0 2006.258.00:30:54.80#ibcon#wrote, iclass 16, count 0 2006.258.00:30:54.80#ibcon#about to read 3, iclass 16, count 0 2006.258.00:30:54.82#ibcon#read 3, iclass 16, count 0 2006.258.00:30:54.82#ibcon#about to read 4, iclass 16, count 0 2006.258.00:30:54.82#ibcon#read 4, iclass 16, count 0 2006.258.00:30:54.82#ibcon#about to read 5, iclass 16, count 0 2006.258.00:30:54.82#ibcon#read 5, iclass 16, count 0 2006.258.00:30:54.82#ibcon#about to read 6, iclass 16, count 0 2006.258.00:30:54.82#ibcon#read 6, iclass 16, count 0 2006.258.00:30:54.82#ibcon#end of sib2, iclass 16, count 0 2006.258.00:30:54.82#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:30:54.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:30:54.82#ibcon#[25=USB\r\n] 2006.258.00:30:54.82#ibcon#*before write, iclass 16, count 0 2006.258.00:30:54.82#ibcon#enter sib2, iclass 16, count 0 2006.258.00:30:54.82#ibcon#flushed, iclass 16, count 0 2006.258.00:30:54.82#ibcon#about to write, iclass 16, count 0 2006.258.00:30:54.82#ibcon#wrote, iclass 16, count 0 2006.258.00:30:54.82#ibcon#about to read 3, iclass 16, count 0 2006.258.00:30:54.85#ibcon#read 3, iclass 16, count 0 2006.258.00:30:54.85#ibcon#about to read 4, iclass 16, count 0 2006.258.00:30:54.85#ibcon#read 4, iclass 16, count 0 2006.258.00:30:54.85#ibcon#about to read 5, iclass 16, count 0 2006.258.00:30:54.85#ibcon#read 5, iclass 16, count 0 2006.258.00:30:54.85#ibcon#about to read 6, iclass 16, count 0 2006.258.00:30:54.85#ibcon#read 6, iclass 16, count 0 2006.258.00:30:54.85#ibcon#end of sib2, iclass 16, count 0 2006.258.00:30:54.85#ibcon#*after write, iclass 16, count 0 2006.258.00:30:54.85#ibcon#*before return 0, iclass 16, count 0 2006.258.00:30:54.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:54.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:54.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:30:54.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:30:54.85$vck44/valo=3,564.99 2006.258.00:30:54.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.00:30:54.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.00:30:54.85#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:54.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:54.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:54.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:54.85#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:30:54.85#ibcon#first serial, iclass 18, count 0 2006.258.00:30:54.85#ibcon#enter sib2, iclass 18, count 0 2006.258.00:30:54.85#ibcon#flushed, iclass 18, count 0 2006.258.00:30:54.85#ibcon#about to write, iclass 18, count 0 2006.258.00:30:54.85#ibcon#wrote, iclass 18, count 0 2006.258.00:30:54.85#ibcon#about to read 3, iclass 18, count 0 2006.258.00:30:54.87#ibcon#read 3, iclass 18, count 0 2006.258.00:30:54.87#ibcon#about to read 4, iclass 18, count 0 2006.258.00:30:54.87#ibcon#read 4, iclass 18, count 0 2006.258.00:30:54.87#ibcon#about to read 5, iclass 18, count 0 2006.258.00:30:54.87#ibcon#read 5, iclass 18, count 0 2006.258.00:30:54.87#ibcon#about to read 6, iclass 18, count 0 2006.258.00:30:54.87#ibcon#read 6, iclass 18, count 0 2006.258.00:30:54.87#ibcon#end of sib2, iclass 18, count 0 2006.258.00:30:54.87#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:30:54.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:30:54.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:30:54.87#ibcon#*before write, iclass 18, count 0 2006.258.00:30:54.87#ibcon#enter sib2, iclass 18, count 0 2006.258.00:30:54.87#ibcon#flushed, iclass 18, count 0 2006.258.00:30:54.87#ibcon#about to write, iclass 18, count 0 2006.258.00:30:54.87#ibcon#wrote, iclass 18, count 0 2006.258.00:30:54.87#ibcon#about to read 3, iclass 18, count 0 2006.258.00:30:54.91#ibcon#read 3, iclass 18, count 0 2006.258.00:30:54.91#ibcon#about to read 4, iclass 18, count 0 2006.258.00:30:54.91#ibcon#read 4, iclass 18, count 0 2006.258.00:30:54.91#ibcon#about to read 5, iclass 18, count 0 2006.258.00:30:54.91#ibcon#read 5, iclass 18, count 0 2006.258.00:30:54.91#ibcon#about to read 6, iclass 18, count 0 2006.258.00:30:54.91#ibcon#read 6, iclass 18, count 0 2006.258.00:30:54.91#ibcon#end of sib2, iclass 18, count 0 2006.258.00:30:54.91#ibcon#*after write, iclass 18, count 0 2006.258.00:30:54.91#ibcon#*before return 0, iclass 18, count 0 2006.258.00:30:54.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:54.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:54.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:30:54.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:30:54.91$vck44/va=3,8 2006.258.00:30:54.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.00:30:54.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.00:30:54.91#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:54.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:54.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:54.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:54.97#ibcon#enter wrdev, iclass 20, count 2 2006.258.00:30:54.97#ibcon#first serial, iclass 20, count 2 2006.258.00:30:54.97#ibcon#enter sib2, iclass 20, count 2 2006.258.00:30:54.97#ibcon#flushed, iclass 20, count 2 2006.258.00:30:54.97#ibcon#about to write, iclass 20, count 2 2006.258.00:30:54.97#ibcon#wrote, iclass 20, count 2 2006.258.00:30:54.97#ibcon#about to read 3, iclass 20, count 2 2006.258.00:30:54.99#ibcon#read 3, iclass 20, count 2 2006.258.00:30:54.99#ibcon#about to read 4, iclass 20, count 2 2006.258.00:30:54.99#ibcon#read 4, iclass 20, count 2 2006.258.00:30:54.99#ibcon#about to read 5, iclass 20, count 2 2006.258.00:30:54.99#ibcon#read 5, iclass 20, count 2 2006.258.00:30:54.99#ibcon#about to read 6, iclass 20, count 2 2006.258.00:30:54.99#ibcon#read 6, iclass 20, count 2 2006.258.00:30:54.99#ibcon#end of sib2, iclass 20, count 2 2006.258.00:30:54.99#ibcon#*mode == 0, iclass 20, count 2 2006.258.00:30:54.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.00:30:54.99#ibcon#[25=AT03-08\r\n] 2006.258.00:30:54.99#ibcon#*before write, iclass 20, count 2 2006.258.00:30:54.99#ibcon#enter sib2, iclass 20, count 2 2006.258.00:30:54.99#ibcon#flushed, iclass 20, count 2 2006.258.00:30:54.99#ibcon#about to write, iclass 20, count 2 2006.258.00:30:54.99#ibcon#wrote, iclass 20, count 2 2006.258.00:30:54.99#ibcon#about to read 3, iclass 20, count 2 2006.258.00:30:55.02#ibcon#read 3, iclass 20, count 2 2006.258.00:30:55.02#ibcon#about to read 4, iclass 20, count 2 2006.258.00:30:55.02#ibcon#read 4, iclass 20, count 2 2006.258.00:30:55.02#ibcon#about to read 5, iclass 20, count 2 2006.258.00:30:55.02#ibcon#read 5, iclass 20, count 2 2006.258.00:30:55.02#ibcon#about to read 6, iclass 20, count 2 2006.258.00:30:55.02#ibcon#read 6, iclass 20, count 2 2006.258.00:30:55.02#ibcon#end of sib2, iclass 20, count 2 2006.258.00:30:55.02#ibcon#*after write, iclass 20, count 2 2006.258.00:30:55.02#ibcon#*before return 0, iclass 20, count 2 2006.258.00:30:55.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:55.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:55.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.00:30:55.02#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:55.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:55.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:55.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:55.14#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:30:55.14#ibcon#first serial, iclass 20, count 0 2006.258.00:30:55.14#ibcon#enter sib2, iclass 20, count 0 2006.258.00:30:55.14#ibcon#flushed, iclass 20, count 0 2006.258.00:30:55.14#ibcon#about to write, iclass 20, count 0 2006.258.00:30:55.14#ibcon#wrote, iclass 20, count 0 2006.258.00:30:55.14#ibcon#about to read 3, iclass 20, count 0 2006.258.00:30:55.16#ibcon#read 3, iclass 20, count 0 2006.258.00:30:55.16#ibcon#about to read 4, iclass 20, count 0 2006.258.00:30:55.16#ibcon#read 4, iclass 20, count 0 2006.258.00:30:55.16#ibcon#about to read 5, iclass 20, count 0 2006.258.00:30:55.16#ibcon#read 5, iclass 20, count 0 2006.258.00:30:55.16#ibcon#about to read 6, iclass 20, count 0 2006.258.00:30:55.16#ibcon#read 6, iclass 20, count 0 2006.258.00:30:55.16#ibcon#end of sib2, iclass 20, count 0 2006.258.00:30:55.16#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:30:55.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:30:55.16#ibcon#[25=USB\r\n] 2006.258.00:30:55.16#ibcon#*before write, iclass 20, count 0 2006.258.00:30:55.16#ibcon#enter sib2, iclass 20, count 0 2006.258.00:30:55.16#ibcon#flushed, iclass 20, count 0 2006.258.00:30:55.16#ibcon#about to write, iclass 20, count 0 2006.258.00:30:55.16#ibcon#wrote, iclass 20, count 0 2006.258.00:30:55.16#ibcon#about to read 3, iclass 20, count 0 2006.258.00:30:55.19#ibcon#read 3, iclass 20, count 0 2006.258.00:30:55.19#ibcon#about to read 4, iclass 20, count 0 2006.258.00:30:55.19#ibcon#read 4, iclass 20, count 0 2006.258.00:30:55.19#ibcon#about to read 5, iclass 20, count 0 2006.258.00:30:55.19#ibcon#read 5, iclass 20, count 0 2006.258.00:30:55.19#ibcon#about to read 6, iclass 20, count 0 2006.258.00:30:55.19#ibcon#read 6, iclass 20, count 0 2006.258.00:30:55.19#ibcon#end of sib2, iclass 20, count 0 2006.258.00:30:55.19#ibcon#*after write, iclass 20, count 0 2006.258.00:30:55.19#ibcon#*before return 0, iclass 20, count 0 2006.258.00:30:55.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:55.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:55.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:30:55.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:30:55.19$vck44/valo=4,624.99 2006.258.00:30:55.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.00:30:55.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.00:30:55.19#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:55.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:55.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:55.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:55.19#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:30:55.19#ibcon#first serial, iclass 22, count 0 2006.258.00:30:55.19#ibcon#enter sib2, iclass 22, count 0 2006.258.00:30:55.19#ibcon#flushed, iclass 22, count 0 2006.258.00:30:55.19#ibcon#about to write, iclass 22, count 0 2006.258.00:30:55.19#ibcon#wrote, iclass 22, count 0 2006.258.00:30:55.19#ibcon#about to read 3, iclass 22, count 0 2006.258.00:30:55.21#ibcon#read 3, iclass 22, count 0 2006.258.00:30:55.21#ibcon#about to read 4, iclass 22, count 0 2006.258.00:30:55.21#ibcon#read 4, iclass 22, count 0 2006.258.00:30:55.21#ibcon#about to read 5, iclass 22, count 0 2006.258.00:30:55.21#ibcon#read 5, iclass 22, count 0 2006.258.00:30:55.21#ibcon#about to read 6, iclass 22, count 0 2006.258.00:30:55.21#ibcon#read 6, iclass 22, count 0 2006.258.00:30:55.21#ibcon#end of sib2, iclass 22, count 0 2006.258.00:30:55.21#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:30:55.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:30:55.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:30:55.21#ibcon#*before write, iclass 22, count 0 2006.258.00:30:55.21#ibcon#enter sib2, iclass 22, count 0 2006.258.00:30:55.21#ibcon#flushed, iclass 22, count 0 2006.258.00:30:55.21#ibcon#about to write, iclass 22, count 0 2006.258.00:30:55.21#ibcon#wrote, iclass 22, count 0 2006.258.00:30:55.21#ibcon#about to read 3, iclass 22, count 0 2006.258.00:30:55.25#ibcon#read 3, iclass 22, count 0 2006.258.00:30:55.25#ibcon#about to read 4, iclass 22, count 0 2006.258.00:30:55.25#ibcon#read 4, iclass 22, count 0 2006.258.00:30:55.25#ibcon#about to read 5, iclass 22, count 0 2006.258.00:30:55.25#ibcon#read 5, iclass 22, count 0 2006.258.00:30:55.25#ibcon#about to read 6, iclass 22, count 0 2006.258.00:30:55.25#ibcon#read 6, iclass 22, count 0 2006.258.00:30:55.25#ibcon#end of sib2, iclass 22, count 0 2006.258.00:30:55.25#ibcon#*after write, iclass 22, count 0 2006.258.00:30:55.25#ibcon#*before return 0, iclass 22, count 0 2006.258.00:30:55.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:55.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:55.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:30:55.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:30:55.25$vck44/va=4,7 2006.258.00:30:55.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.00:30:55.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.00:30:55.25#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:55.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:55.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:55.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:55.31#ibcon#enter wrdev, iclass 24, count 2 2006.258.00:30:55.31#ibcon#first serial, iclass 24, count 2 2006.258.00:30:55.31#ibcon#enter sib2, iclass 24, count 2 2006.258.00:30:55.31#ibcon#flushed, iclass 24, count 2 2006.258.00:30:55.31#ibcon#about to write, iclass 24, count 2 2006.258.00:30:55.31#ibcon#wrote, iclass 24, count 2 2006.258.00:30:55.31#ibcon#about to read 3, iclass 24, count 2 2006.258.00:30:55.33#ibcon#read 3, iclass 24, count 2 2006.258.00:30:55.33#ibcon#about to read 4, iclass 24, count 2 2006.258.00:30:55.33#ibcon#read 4, iclass 24, count 2 2006.258.00:30:55.33#ibcon#about to read 5, iclass 24, count 2 2006.258.00:30:55.33#ibcon#read 5, iclass 24, count 2 2006.258.00:30:55.33#ibcon#about to read 6, iclass 24, count 2 2006.258.00:30:55.33#ibcon#read 6, iclass 24, count 2 2006.258.00:30:55.33#ibcon#end of sib2, iclass 24, count 2 2006.258.00:30:55.33#ibcon#*mode == 0, iclass 24, count 2 2006.258.00:30:55.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.00:30:55.33#ibcon#[25=AT04-07\r\n] 2006.258.00:30:55.33#ibcon#*before write, iclass 24, count 2 2006.258.00:30:55.33#ibcon#enter sib2, iclass 24, count 2 2006.258.00:30:55.33#ibcon#flushed, iclass 24, count 2 2006.258.00:30:55.33#ibcon#about to write, iclass 24, count 2 2006.258.00:30:55.33#ibcon#wrote, iclass 24, count 2 2006.258.00:30:55.33#ibcon#about to read 3, iclass 24, count 2 2006.258.00:30:55.36#ibcon#read 3, iclass 24, count 2 2006.258.00:30:55.36#ibcon#about to read 4, iclass 24, count 2 2006.258.00:30:55.36#ibcon#read 4, iclass 24, count 2 2006.258.00:30:55.36#ibcon#about to read 5, iclass 24, count 2 2006.258.00:30:55.36#ibcon#read 5, iclass 24, count 2 2006.258.00:30:55.36#ibcon#about to read 6, iclass 24, count 2 2006.258.00:30:55.36#ibcon#read 6, iclass 24, count 2 2006.258.00:30:55.36#ibcon#end of sib2, iclass 24, count 2 2006.258.00:30:55.36#ibcon#*after write, iclass 24, count 2 2006.258.00:30:55.36#ibcon#*before return 0, iclass 24, count 2 2006.258.00:30:55.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:55.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:55.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.00:30:55.37#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:55.37#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:55.47#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:55.47#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:55.47#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:30:55.47#ibcon#first serial, iclass 24, count 0 2006.258.00:30:55.47#ibcon#enter sib2, iclass 24, count 0 2006.258.00:30:55.47#ibcon#flushed, iclass 24, count 0 2006.258.00:30:55.47#ibcon#about to write, iclass 24, count 0 2006.258.00:30:55.47#ibcon#wrote, iclass 24, count 0 2006.258.00:30:55.47#ibcon#about to read 3, iclass 24, count 0 2006.258.00:30:55.49#ibcon#read 3, iclass 24, count 0 2006.258.00:30:55.49#ibcon#about to read 4, iclass 24, count 0 2006.258.00:30:55.49#ibcon#read 4, iclass 24, count 0 2006.258.00:30:55.49#ibcon#about to read 5, iclass 24, count 0 2006.258.00:30:55.49#ibcon#read 5, iclass 24, count 0 2006.258.00:30:55.49#ibcon#about to read 6, iclass 24, count 0 2006.258.00:30:55.49#ibcon#read 6, iclass 24, count 0 2006.258.00:30:55.49#ibcon#end of sib2, iclass 24, count 0 2006.258.00:30:55.49#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:30:55.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:30:55.49#ibcon#[25=USB\r\n] 2006.258.00:30:55.49#ibcon#*before write, iclass 24, count 0 2006.258.00:30:55.49#ibcon#enter sib2, iclass 24, count 0 2006.258.00:30:55.49#ibcon#flushed, iclass 24, count 0 2006.258.00:30:55.49#ibcon#about to write, iclass 24, count 0 2006.258.00:30:55.49#ibcon#wrote, iclass 24, count 0 2006.258.00:30:55.49#ibcon#about to read 3, iclass 24, count 0 2006.258.00:30:55.52#ibcon#read 3, iclass 24, count 0 2006.258.00:30:55.52#ibcon#about to read 4, iclass 24, count 0 2006.258.00:30:55.52#ibcon#read 4, iclass 24, count 0 2006.258.00:30:55.52#ibcon#about to read 5, iclass 24, count 0 2006.258.00:30:55.52#ibcon#read 5, iclass 24, count 0 2006.258.00:30:55.52#ibcon#about to read 6, iclass 24, count 0 2006.258.00:30:55.52#ibcon#read 6, iclass 24, count 0 2006.258.00:30:55.52#ibcon#end of sib2, iclass 24, count 0 2006.258.00:30:55.52#ibcon#*after write, iclass 24, count 0 2006.258.00:30:55.52#ibcon#*before return 0, iclass 24, count 0 2006.258.00:30:55.52#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:55.52#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:55.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:30:55.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:30:55.52$vck44/valo=5,734.99 2006.258.00:30:55.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.00:30:55.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.00:30:55.52#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:55.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:55.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:55.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:55.52#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:30:55.52#ibcon#first serial, iclass 26, count 0 2006.258.00:30:55.52#ibcon#enter sib2, iclass 26, count 0 2006.258.00:30:55.52#ibcon#flushed, iclass 26, count 0 2006.258.00:30:55.52#ibcon#about to write, iclass 26, count 0 2006.258.00:30:55.52#ibcon#wrote, iclass 26, count 0 2006.258.00:30:55.52#ibcon#about to read 3, iclass 26, count 0 2006.258.00:30:55.54#ibcon#read 3, iclass 26, count 0 2006.258.00:30:55.54#ibcon#about to read 4, iclass 26, count 0 2006.258.00:30:55.54#ibcon#read 4, iclass 26, count 0 2006.258.00:30:55.54#ibcon#about to read 5, iclass 26, count 0 2006.258.00:30:55.54#ibcon#read 5, iclass 26, count 0 2006.258.00:30:55.54#ibcon#about to read 6, iclass 26, count 0 2006.258.00:30:55.54#ibcon#read 6, iclass 26, count 0 2006.258.00:30:55.54#ibcon#end of sib2, iclass 26, count 0 2006.258.00:30:55.54#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:30:55.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:30:55.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:30:55.54#ibcon#*before write, iclass 26, count 0 2006.258.00:30:55.54#ibcon#enter sib2, iclass 26, count 0 2006.258.00:30:55.54#ibcon#flushed, iclass 26, count 0 2006.258.00:30:55.54#ibcon#about to write, iclass 26, count 0 2006.258.00:30:55.54#ibcon#wrote, iclass 26, count 0 2006.258.00:30:55.54#ibcon#about to read 3, iclass 26, count 0 2006.258.00:30:55.58#ibcon#read 3, iclass 26, count 0 2006.258.00:30:55.58#ibcon#about to read 4, iclass 26, count 0 2006.258.00:30:55.58#ibcon#read 4, iclass 26, count 0 2006.258.00:30:55.58#ibcon#about to read 5, iclass 26, count 0 2006.258.00:30:55.58#ibcon#read 5, iclass 26, count 0 2006.258.00:30:55.58#ibcon#about to read 6, iclass 26, count 0 2006.258.00:30:55.58#ibcon#read 6, iclass 26, count 0 2006.258.00:30:55.58#ibcon#end of sib2, iclass 26, count 0 2006.258.00:30:55.58#ibcon#*after write, iclass 26, count 0 2006.258.00:30:55.58#ibcon#*before return 0, iclass 26, count 0 2006.258.00:30:55.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:55.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:55.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:30:55.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:30:55.58$vck44/va=5,4 2006.258.00:30:55.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.00:30:55.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.00:30:55.58#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:55.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:55.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:55.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:55.64#ibcon#enter wrdev, iclass 28, count 2 2006.258.00:30:55.64#ibcon#first serial, iclass 28, count 2 2006.258.00:30:55.64#ibcon#enter sib2, iclass 28, count 2 2006.258.00:30:55.64#ibcon#flushed, iclass 28, count 2 2006.258.00:30:55.64#ibcon#about to write, iclass 28, count 2 2006.258.00:30:55.64#ibcon#wrote, iclass 28, count 2 2006.258.00:30:55.64#ibcon#about to read 3, iclass 28, count 2 2006.258.00:30:55.66#ibcon#read 3, iclass 28, count 2 2006.258.00:30:55.66#ibcon#about to read 4, iclass 28, count 2 2006.258.00:30:55.66#ibcon#read 4, iclass 28, count 2 2006.258.00:30:55.66#ibcon#about to read 5, iclass 28, count 2 2006.258.00:30:55.66#ibcon#read 5, iclass 28, count 2 2006.258.00:30:55.66#ibcon#about to read 6, iclass 28, count 2 2006.258.00:30:55.66#ibcon#read 6, iclass 28, count 2 2006.258.00:30:55.66#ibcon#end of sib2, iclass 28, count 2 2006.258.00:30:55.66#ibcon#*mode == 0, iclass 28, count 2 2006.258.00:30:55.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.00:30:55.66#ibcon#[25=AT05-04\r\n] 2006.258.00:30:55.66#ibcon#*before write, iclass 28, count 2 2006.258.00:30:55.66#ibcon#enter sib2, iclass 28, count 2 2006.258.00:30:55.66#ibcon#flushed, iclass 28, count 2 2006.258.00:30:55.66#ibcon#about to write, iclass 28, count 2 2006.258.00:30:55.66#ibcon#wrote, iclass 28, count 2 2006.258.00:30:55.66#ibcon#about to read 3, iclass 28, count 2 2006.258.00:30:55.69#ibcon#read 3, iclass 28, count 2 2006.258.00:30:55.69#ibcon#about to read 4, iclass 28, count 2 2006.258.00:30:55.69#ibcon#read 4, iclass 28, count 2 2006.258.00:30:55.69#ibcon#about to read 5, iclass 28, count 2 2006.258.00:30:55.69#ibcon#read 5, iclass 28, count 2 2006.258.00:30:55.69#ibcon#about to read 6, iclass 28, count 2 2006.258.00:30:55.69#ibcon#read 6, iclass 28, count 2 2006.258.00:30:55.69#ibcon#end of sib2, iclass 28, count 2 2006.258.00:30:55.69#ibcon#*after write, iclass 28, count 2 2006.258.00:30:55.69#ibcon#*before return 0, iclass 28, count 2 2006.258.00:30:55.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:55.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:55.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.00:30:55.69#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:55.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:55.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:55.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:55.81#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:30:55.81#ibcon#first serial, iclass 28, count 0 2006.258.00:30:55.81#ibcon#enter sib2, iclass 28, count 0 2006.258.00:30:55.81#ibcon#flushed, iclass 28, count 0 2006.258.00:30:55.81#ibcon#about to write, iclass 28, count 0 2006.258.00:30:55.81#ibcon#wrote, iclass 28, count 0 2006.258.00:30:55.81#ibcon#about to read 3, iclass 28, count 0 2006.258.00:30:55.83#ibcon#read 3, iclass 28, count 0 2006.258.00:30:55.83#ibcon#about to read 4, iclass 28, count 0 2006.258.00:30:55.83#ibcon#read 4, iclass 28, count 0 2006.258.00:30:55.83#ibcon#about to read 5, iclass 28, count 0 2006.258.00:30:55.83#ibcon#read 5, iclass 28, count 0 2006.258.00:30:55.83#ibcon#about to read 6, iclass 28, count 0 2006.258.00:30:55.83#ibcon#read 6, iclass 28, count 0 2006.258.00:30:55.83#ibcon#end of sib2, iclass 28, count 0 2006.258.00:30:55.83#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:30:55.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:30:55.83#ibcon#[25=USB\r\n] 2006.258.00:30:55.83#ibcon#*before write, iclass 28, count 0 2006.258.00:30:55.83#ibcon#enter sib2, iclass 28, count 0 2006.258.00:30:55.83#ibcon#flushed, iclass 28, count 0 2006.258.00:30:55.83#ibcon#about to write, iclass 28, count 0 2006.258.00:30:55.83#ibcon#wrote, iclass 28, count 0 2006.258.00:30:55.83#ibcon#about to read 3, iclass 28, count 0 2006.258.00:30:55.86#ibcon#read 3, iclass 28, count 0 2006.258.00:30:55.86#ibcon#about to read 4, iclass 28, count 0 2006.258.00:30:55.86#ibcon#read 4, iclass 28, count 0 2006.258.00:30:55.86#ibcon#about to read 5, iclass 28, count 0 2006.258.00:30:55.86#ibcon#read 5, iclass 28, count 0 2006.258.00:30:55.86#ibcon#about to read 6, iclass 28, count 0 2006.258.00:30:55.86#ibcon#read 6, iclass 28, count 0 2006.258.00:30:55.86#ibcon#end of sib2, iclass 28, count 0 2006.258.00:30:55.86#ibcon#*after write, iclass 28, count 0 2006.258.00:30:55.86#ibcon#*before return 0, iclass 28, count 0 2006.258.00:30:55.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:55.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:55.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:30:55.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:30:55.86$vck44/valo=6,814.99 2006.258.00:30:55.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.00:30:55.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.00:30:55.86#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:55.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:55.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:55.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:55.86#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:30:55.86#ibcon#first serial, iclass 30, count 0 2006.258.00:30:55.86#ibcon#enter sib2, iclass 30, count 0 2006.258.00:30:55.86#ibcon#flushed, iclass 30, count 0 2006.258.00:30:55.86#ibcon#about to write, iclass 30, count 0 2006.258.00:30:55.86#ibcon#wrote, iclass 30, count 0 2006.258.00:30:55.86#ibcon#about to read 3, iclass 30, count 0 2006.258.00:30:55.88#ibcon#read 3, iclass 30, count 0 2006.258.00:30:55.88#ibcon#about to read 4, iclass 30, count 0 2006.258.00:30:55.88#ibcon#read 4, iclass 30, count 0 2006.258.00:30:55.88#ibcon#about to read 5, iclass 30, count 0 2006.258.00:30:55.88#ibcon#read 5, iclass 30, count 0 2006.258.00:30:55.88#ibcon#about to read 6, iclass 30, count 0 2006.258.00:30:55.88#ibcon#read 6, iclass 30, count 0 2006.258.00:30:55.88#ibcon#end of sib2, iclass 30, count 0 2006.258.00:30:55.88#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:30:55.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:30:55.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:30:55.88#ibcon#*before write, iclass 30, count 0 2006.258.00:30:55.88#ibcon#enter sib2, iclass 30, count 0 2006.258.00:30:55.88#ibcon#flushed, iclass 30, count 0 2006.258.00:30:55.88#ibcon#about to write, iclass 30, count 0 2006.258.00:30:55.88#ibcon#wrote, iclass 30, count 0 2006.258.00:30:55.88#ibcon#about to read 3, iclass 30, count 0 2006.258.00:30:55.92#ibcon#read 3, iclass 30, count 0 2006.258.00:30:55.92#ibcon#about to read 4, iclass 30, count 0 2006.258.00:30:55.92#ibcon#read 4, iclass 30, count 0 2006.258.00:30:55.92#ibcon#about to read 5, iclass 30, count 0 2006.258.00:30:55.92#ibcon#read 5, iclass 30, count 0 2006.258.00:30:55.92#ibcon#about to read 6, iclass 30, count 0 2006.258.00:30:55.92#ibcon#read 6, iclass 30, count 0 2006.258.00:30:55.92#ibcon#end of sib2, iclass 30, count 0 2006.258.00:30:55.92#ibcon#*after write, iclass 30, count 0 2006.258.00:30:55.92#ibcon#*before return 0, iclass 30, count 0 2006.258.00:30:55.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:55.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:55.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:30:55.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:30:55.92$vck44/va=6,4 2006.258.00:30:55.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.258.00:30:55.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.258.00:30:55.92#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:55.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:55.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:55.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:55.98#ibcon#enter wrdev, iclass 32, count 2 2006.258.00:30:55.98#ibcon#first serial, iclass 32, count 2 2006.258.00:30:55.98#ibcon#enter sib2, iclass 32, count 2 2006.258.00:30:55.98#ibcon#flushed, iclass 32, count 2 2006.258.00:30:55.98#ibcon#about to write, iclass 32, count 2 2006.258.00:30:55.98#ibcon#wrote, iclass 32, count 2 2006.258.00:30:55.98#ibcon#about to read 3, iclass 32, count 2 2006.258.00:30:56.00#ibcon#read 3, iclass 32, count 2 2006.258.00:30:56.00#ibcon#about to read 4, iclass 32, count 2 2006.258.00:30:56.00#ibcon#read 4, iclass 32, count 2 2006.258.00:30:56.00#ibcon#about to read 5, iclass 32, count 2 2006.258.00:30:56.00#ibcon#read 5, iclass 32, count 2 2006.258.00:30:56.00#ibcon#about to read 6, iclass 32, count 2 2006.258.00:30:56.00#ibcon#read 6, iclass 32, count 2 2006.258.00:30:56.00#ibcon#end of sib2, iclass 32, count 2 2006.258.00:30:56.00#ibcon#*mode == 0, iclass 32, count 2 2006.258.00:30:56.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.258.00:30:56.00#ibcon#[25=AT06-04\r\n] 2006.258.00:30:56.00#ibcon#*before write, iclass 32, count 2 2006.258.00:30:56.00#ibcon#enter sib2, iclass 32, count 2 2006.258.00:30:56.00#ibcon#flushed, iclass 32, count 2 2006.258.00:30:56.00#ibcon#about to write, iclass 32, count 2 2006.258.00:30:56.00#ibcon#wrote, iclass 32, count 2 2006.258.00:30:56.00#ibcon#about to read 3, iclass 32, count 2 2006.258.00:30:56.03#ibcon#read 3, iclass 32, count 2 2006.258.00:30:56.03#ibcon#about to read 4, iclass 32, count 2 2006.258.00:30:56.03#ibcon#read 4, iclass 32, count 2 2006.258.00:30:56.03#ibcon#about to read 5, iclass 32, count 2 2006.258.00:30:56.03#ibcon#read 5, iclass 32, count 2 2006.258.00:30:56.03#ibcon#about to read 6, iclass 32, count 2 2006.258.00:30:56.03#ibcon#read 6, iclass 32, count 2 2006.258.00:30:56.03#ibcon#end of sib2, iclass 32, count 2 2006.258.00:30:56.03#ibcon#*after write, iclass 32, count 2 2006.258.00:30:56.03#ibcon#*before return 0, iclass 32, count 2 2006.258.00:30:56.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:56.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:56.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.258.00:30:56.03#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:56.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:56.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:56.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:56.15#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:30:56.15#ibcon#first serial, iclass 32, count 0 2006.258.00:30:56.15#ibcon#enter sib2, iclass 32, count 0 2006.258.00:30:56.15#ibcon#flushed, iclass 32, count 0 2006.258.00:30:56.15#ibcon#about to write, iclass 32, count 0 2006.258.00:30:56.15#ibcon#wrote, iclass 32, count 0 2006.258.00:30:56.15#ibcon#about to read 3, iclass 32, count 0 2006.258.00:30:56.17#ibcon#read 3, iclass 32, count 0 2006.258.00:30:56.17#ibcon#about to read 4, iclass 32, count 0 2006.258.00:30:56.17#ibcon#read 4, iclass 32, count 0 2006.258.00:30:56.17#ibcon#about to read 5, iclass 32, count 0 2006.258.00:30:56.17#ibcon#read 5, iclass 32, count 0 2006.258.00:30:56.17#ibcon#about to read 6, iclass 32, count 0 2006.258.00:30:56.17#ibcon#read 6, iclass 32, count 0 2006.258.00:30:56.17#ibcon#end of sib2, iclass 32, count 0 2006.258.00:30:56.17#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:30:56.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:30:56.17#ibcon#[25=USB\r\n] 2006.258.00:30:56.17#ibcon#*before write, iclass 32, count 0 2006.258.00:30:56.17#ibcon#enter sib2, iclass 32, count 0 2006.258.00:30:56.17#ibcon#flushed, iclass 32, count 0 2006.258.00:30:56.17#ibcon#about to write, iclass 32, count 0 2006.258.00:30:56.17#ibcon#wrote, iclass 32, count 0 2006.258.00:30:56.17#ibcon#about to read 3, iclass 32, count 0 2006.258.00:30:56.20#ibcon#read 3, iclass 32, count 0 2006.258.00:30:56.20#ibcon#about to read 4, iclass 32, count 0 2006.258.00:30:56.20#ibcon#read 4, iclass 32, count 0 2006.258.00:30:56.20#ibcon#about to read 5, iclass 32, count 0 2006.258.00:30:56.20#ibcon#read 5, iclass 32, count 0 2006.258.00:30:56.20#ibcon#about to read 6, iclass 32, count 0 2006.258.00:30:56.20#ibcon#read 6, iclass 32, count 0 2006.258.00:30:56.20#ibcon#end of sib2, iclass 32, count 0 2006.258.00:30:56.20#ibcon#*after write, iclass 32, count 0 2006.258.00:30:56.20#ibcon#*before return 0, iclass 32, count 0 2006.258.00:30:56.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:56.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:56.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:30:56.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:30:56.20$vck44/valo=7,864.99 2006.258.00:30:56.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.00:30:56.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.00:30:56.20#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:56.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:56.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:56.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:56.20#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:30:56.20#ibcon#first serial, iclass 34, count 0 2006.258.00:30:56.20#ibcon#enter sib2, iclass 34, count 0 2006.258.00:30:56.20#ibcon#flushed, iclass 34, count 0 2006.258.00:30:56.20#ibcon#about to write, iclass 34, count 0 2006.258.00:30:56.20#ibcon#wrote, iclass 34, count 0 2006.258.00:30:56.20#ibcon#about to read 3, iclass 34, count 0 2006.258.00:30:56.22#ibcon#read 3, iclass 34, count 0 2006.258.00:30:56.22#ibcon#about to read 4, iclass 34, count 0 2006.258.00:30:56.22#ibcon#read 4, iclass 34, count 0 2006.258.00:30:56.22#ibcon#about to read 5, iclass 34, count 0 2006.258.00:30:56.22#ibcon#read 5, iclass 34, count 0 2006.258.00:30:56.22#ibcon#about to read 6, iclass 34, count 0 2006.258.00:30:56.22#ibcon#read 6, iclass 34, count 0 2006.258.00:30:56.22#ibcon#end of sib2, iclass 34, count 0 2006.258.00:30:56.22#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:30:56.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:30:56.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:30:56.22#ibcon#*before write, iclass 34, count 0 2006.258.00:30:56.22#ibcon#enter sib2, iclass 34, count 0 2006.258.00:30:56.22#ibcon#flushed, iclass 34, count 0 2006.258.00:30:56.22#ibcon#about to write, iclass 34, count 0 2006.258.00:30:56.22#ibcon#wrote, iclass 34, count 0 2006.258.00:30:56.22#ibcon#about to read 3, iclass 34, count 0 2006.258.00:30:56.26#ibcon#read 3, iclass 34, count 0 2006.258.00:30:56.26#ibcon#about to read 4, iclass 34, count 0 2006.258.00:30:56.26#ibcon#read 4, iclass 34, count 0 2006.258.00:30:56.26#ibcon#about to read 5, iclass 34, count 0 2006.258.00:30:56.26#ibcon#read 5, iclass 34, count 0 2006.258.00:30:56.26#ibcon#about to read 6, iclass 34, count 0 2006.258.00:30:56.26#ibcon#read 6, iclass 34, count 0 2006.258.00:30:56.26#ibcon#end of sib2, iclass 34, count 0 2006.258.00:30:56.26#ibcon#*after write, iclass 34, count 0 2006.258.00:30:56.26#ibcon#*before return 0, iclass 34, count 0 2006.258.00:30:56.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:56.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:56.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:30:56.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:30:56.26$vck44/va=7,4 2006.258.00:30:56.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.258.00:30:56.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.258.00:30:56.26#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:56.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:56.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:56.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:56.32#ibcon#enter wrdev, iclass 36, count 2 2006.258.00:30:56.32#ibcon#first serial, iclass 36, count 2 2006.258.00:30:56.32#ibcon#enter sib2, iclass 36, count 2 2006.258.00:30:56.32#ibcon#flushed, iclass 36, count 2 2006.258.00:30:56.32#ibcon#about to write, iclass 36, count 2 2006.258.00:30:56.32#ibcon#wrote, iclass 36, count 2 2006.258.00:30:56.32#ibcon#about to read 3, iclass 36, count 2 2006.258.00:30:56.34#ibcon#read 3, iclass 36, count 2 2006.258.00:30:56.34#ibcon#about to read 4, iclass 36, count 2 2006.258.00:30:56.34#ibcon#read 4, iclass 36, count 2 2006.258.00:30:56.34#ibcon#about to read 5, iclass 36, count 2 2006.258.00:30:56.34#ibcon#read 5, iclass 36, count 2 2006.258.00:30:56.34#ibcon#about to read 6, iclass 36, count 2 2006.258.00:30:56.34#ibcon#read 6, iclass 36, count 2 2006.258.00:30:56.34#ibcon#end of sib2, iclass 36, count 2 2006.258.00:30:56.34#ibcon#*mode == 0, iclass 36, count 2 2006.258.00:30:56.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.258.00:30:56.34#ibcon#[25=AT07-04\r\n] 2006.258.00:30:56.34#ibcon#*before write, iclass 36, count 2 2006.258.00:30:56.34#ibcon#enter sib2, iclass 36, count 2 2006.258.00:30:56.34#ibcon#flushed, iclass 36, count 2 2006.258.00:30:56.34#ibcon#about to write, iclass 36, count 2 2006.258.00:30:56.34#ibcon#wrote, iclass 36, count 2 2006.258.00:30:56.34#ibcon#about to read 3, iclass 36, count 2 2006.258.00:30:56.37#ibcon#read 3, iclass 36, count 2 2006.258.00:30:56.37#ibcon#about to read 4, iclass 36, count 2 2006.258.00:30:56.37#ibcon#read 4, iclass 36, count 2 2006.258.00:30:56.37#ibcon#about to read 5, iclass 36, count 2 2006.258.00:30:56.37#ibcon#read 5, iclass 36, count 2 2006.258.00:30:56.37#ibcon#about to read 6, iclass 36, count 2 2006.258.00:30:56.37#ibcon#read 6, iclass 36, count 2 2006.258.00:30:56.37#ibcon#end of sib2, iclass 36, count 2 2006.258.00:30:56.37#ibcon#*after write, iclass 36, count 2 2006.258.00:30:56.37#ibcon#*before return 0, iclass 36, count 2 2006.258.00:30:56.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:56.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:56.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.258.00:30:56.37#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:56.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:56.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:56.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:56.49#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:30:56.49#ibcon#first serial, iclass 36, count 0 2006.258.00:30:56.49#ibcon#enter sib2, iclass 36, count 0 2006.258.00:30:56.49#ibcon#flushed, iclass 36, count 0 2006.258.00:30:56.49#ibcon#about to write, iclass 36, count 0 2006.258.00:30:56.49#ibcon#wrote, iclass 36, count 0 2006.258.00:30:56.49#ibcon#about to read 3, iclass 36, count 0 2006.258.00:30:56.51#ibcon#read 3, iclass 36, count 0 2006.258.00:30:56.51#ibcon#about to read 4, iclass 36, count 0 2006.258.00:30:56.51#ibcon#read 4, iclass 36, count 0 2006.258.00:30:56.51#ibcon#about to read 5, iclass 36, count 0 2006.258.00:30:56.51#ibcon#read 5, iclass 36, count 0 2006.258.00:30:56.51#ibcon#about to read 6, iclass 36, count 0 2006.258.00:30:56.51#ibcon#read 6, iclass 36, count 0 2006.258.00:30:56.51#ibcon#end of sib2, iclass 36, count 0 2006.258.00:30:56.51#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:30:56.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:30:56.51#ibcon#[25=USB\r\n] 2006.258.00:30:56.51#ibcon#*before write, iclass 36, count 0 2006.258.00:30:56.51#ibcon#enter sib2, iclass 36, count 0 2006.258.00:30:56.51#ibcon#flushed, iclass 36, count 0 2006.258.00:30:56.51#ibcon#about to write, iclass 36, count 0 2006.258.00:30:56.51#ibcon#wrote, iclass 36, count 0 2006.258.00:30:56.51#ibcon#about to read 3, iclass 36, count 0 2006.258.00:30:56.54#ibcon#read 3, iclass 36, count 0 2006.258.00:30:56.54#ibcon#about to read 4, iclass 36, count 0 2006.258.00:30:56.54#ibcon#read 4, iclass 36, count 0 2006.258.00:30:56.54#ibcon#about to read 5, iclass 36, count 0 2006.258.00:30:56.54#ibcon#read 5, iclass 36, count 0 2006.258.00:30:56.54#ibcon#about to read 6, iclass 36, count 0 2006.258.00:30:56.54#ibcon#read 6, iclass 36, count 0 2006.258.00:30:56.54#ibcon#end of sib2, iclass 36, count 0 2006.258.00:30:56.54#ibcon#*after write, iclass 36, count 0 2006.258.00:30:56.54#ibcon#*before return 0, iclass 36, count 0 2006.258.00:30:56.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:56.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:56.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:30:56.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:30:56.54$vck44/valo=8,884.99 2006.258.00:30:56.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.00:30:56.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.00:30:56.54#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:56.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:56.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:56.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:56.54#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:30:56.54#ibcon#first serial, iclass 38, count 0 2006.258.00:30:56.54#ibcon#enter sib2, iclass 38, count 0 2006.258.00:30:56.54#ibcon#flushed, iclass 38, count 0 2006.258.00:30:56.54#ibcon#about to write, iclass 38, count 0 2006.258.00:30:56.54#ibcon#wrote, iclass 38, count 0 2006.258.00:30:56.54#ibcon#about to read 3, iclass 38, count 0 2006.258.00:30:56.56#ibcon#read 3, iclass 38, count 0 2006.258.00:30:56.56#ibcon#about to read 4, iclass 38, count 0 2006.258.00:30:56.56#ibcon#read 4, iclass 38, count 0 2006.258.00:30:56.56#ibcon#about to read 5, iclass 38, count 0 2006.258.00:30:56.56#ibcon#read 5, iclass 38, count 0 2006.258.00:30:56.56#ibcon#about to read 6, iclass 38, count 0 2006.258.00:30:56.56#ibcon#read 6, iclass 38, count 0 2006.258.00:30:56.56#ibcon#end of sib2, iclass 38, count 0 2006.258.00:30:56.56#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:30:56.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:30:56.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:30:56.56#ibcon#*before write, iclass 38, count 0 2006.258.00:30:56.56#ibcon#enter sib2, iclass 38, count 0 2006.258.00:30:56.56#ibcon#flushed, iclass 38, count 0 2006.258.00:30:56.56#ibcon#about to write, iclass 38, count 0 2006.258.00:30:56.56#ibcon#wrote, iclass 38, count 0 2006.258.00:30:56.56#ibcon#about to read 3, iclass 38, count 0 2006.258.00:30:56.60#ibcon#read 3, iclass 38, count 0 2006.258.00:30:56.60#ibcon#about to read 4, iclass 38, count 0 2006.258.00:30:56.60#ibcon#read 4, iclass 38, count 0 2006.258.00:30:56.60#ibcon#about to read 5, iclass 38, count 0 2006.258.00:30:56.60#ibcon#read 5, iclass 38, count 0 2006.258.00:30:56.60#ibcon#about to read 6, iclass 38, count 0 2006.258.00:30:56.60#ibcon#read 6, iclass 38, count 0 2006.258.00:30:56.60#ibcon#end of sib2, iclass 38, count 0 2006.258.00:30:56.60#ibcon#*after write, iclass 38, count 0 2006.258.00:30:56.60#ibcon#*before return 0, iclass 38, count 0 2006.258.00:30:56.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:56.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:56.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:30:56.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:30:56.60$vck44/va=8,4 2006.258.00:30:56.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.258.00:30:56.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.258.00:30:56.60#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:56.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:30:56.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:30:56.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:30:56.66#ibcon#enter wrdev, iclass 40, count 2 2006.258.00:30:56.66#ibcon#first serial, iclass 40, count 2 2006.258.00:30:56.66#ibcon#enter sib2, iclass 40, count 2 2006.258.00:30:56.66#ibcon#flushed, iclass 40, count 2 2006.258.00:30:56.66#ibcon#about to write, iclass 40, count 2 2006.258.00:30:56.66#ibcon#wrote, iclass 40, count 2 2006.258.00:30:56.66#ibcon#about to read 3, iclass 40, count 2 2006.258.00:30:56.68#ibcon#read 3, iclass 40, count 2 2006.258.00:30:56.68#ibcon#about to read 4, iclass 40, count 2 2006.258.00:30:56.68#ibcon#read 4, iclass 40, count 2 2006.258.00:30:56.68#ibcon#about to read 5, iclass 40, count 2 2006.258.00:30:56.68#ibcon#read 5, iclass 40, count 2 2006.258.00:30:56.68#ibcon#about to read 6, iclass 40, count 2 2006.258.00:30:56.68#ibcon#read 6, iclass 40, count 2 2006.258.00:30:56.68#ibcon#end of sib2, iclass 40, count 2 2006.258.00:30:56.68#ibcon#*mode == 0, iclass 40, count 2 2006.258.00:30:56.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.258.00:30:56.68#ibcon#[25=AT08-04\r\n] 2006.258.00:30:56.68#ibcon#*before write, iclass 40, count 2 2006.258.00:30:56.68#ibcon#enter sib2, iclass 40, count 2 2006.258.00:30:56.68#ibcon#flushed, iclass 40, count 2 2006.258.00:30:56.68#ibcon#about to write, iclass 40, count 2 2006.258.00:30:56.68#ibcon#wrote, iclass 40, count 2 2006.258.00:30:56.68#ibcon#about to read 3, iclass 40, count 2 2006.258.00:30:56.71#ibcon#read 3, iclass 40, count 2 2006.258.00:30:56.71#ibcon#about to read 4, iclass 40, count 2 2006.258.00:30:56.71#ibcon#read 4, iclass 40, count 2 2006.258.00:30:56.71#ibcon#about to read 5, iclass 40, count 2 2006.258.00:30:56.71#ibcon#read 5, iclass 40, count 2 2006.258.00:30:56.71#ibcon#about to read 6, iclass 40, count 2 2006.258.00:30:56.71#ibcon#read 6, iclass 40, count 2 2006.258.00:30:56.71#ibcon#end of sib2, iclass 40, count 2 2006.258.00:30:56.71#ibcon#*after write, iclass 40, count 2 2006.258.00:30:56.71#ibcon#*before return 0, iclass 40, count 2 2006.258.00:30:56.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:30:56.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:30:56.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.258.00:30:56.71#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:56.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:30:56.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:30:56.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:30:56.83#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:30:56.83#ibcon#first serial, iclass 40, count 0 2006.258.00:30:56.83#ibcon#enter sib2, iclass 40, count 0 2006.258.00:30:56.83#ibcon#flushed, iclass 40, count 0 2006.258.00:30:56.83#ibcon#about to write, iclass 40, count 0 2006.258.00:30:56.83#ibcon#wrote, iclass 40, count 0 2006.258.00:30:56.83#ibcon#about to read 3, iclass 40, count 0 2006.258.00:30:56.85#ibcon#read 3, iclass 40, count 0 2006.258.00:30:56.85#ibcon#about to read 4, iclass 40, count 0 2006.258.00:30:56.85#ibcon#read 4, iclass 40, count 0 2006.258.00:30:56.85#ibcon#about to read 5, iclass 40, count 0 2006.258.00:30:56.85#ibcon#read 5, iclass 40, count 0 2006.258.00:30:56.85#ibcon#about to read 6, iclass 40, count 0 2006.258.00:30:56.85#ibcon#read 6, iclass 40, count 0 2006.258.00:30:56.85#ibcon#end of sib2, iclass 40, count 0 2006.258.00:30:56.85#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:30:56.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:30:56.85#ibcon#[25=USB\r\n] 2006.258.00:30:56.85#ibcon#*before write, iclass 40, count 0 2006.258.00:30:56.85#ibcon#enter sib2, iclass 40, count 0 2006.258.00:30:56.85#ibcon#flushed, iclass 40, count 0 2006.258.00:30:56.85#ibcon#about to write, iclass 40, count 0 2006.258.00:30:56.85#ibcon#wrote, iclass 40, count 0 2006.258.00:30:56.85#ibcon#about to read 3, iclass 40, count 0 2006.258.00:30:56.88#ibcon#read 3, iclass 40, count 0 2006.258.00:30:56.88#ibcon#about to read 4, iclass 40, count 0 2006.258.00:30:56.88#ibcon#read 4, iclass 40, count 0 2006.258.00:30:56.88#ibcon#about to read 5, iclass 40, count 0 2006.258.00:30:56.88#ibcon#read 5, iclass 40, count 0 2006.258.00:30:56.88#ibcon#about to read 6, iclass 40, count 0 2006.258.00:30:56.88#ibcon#read 6, iclass 40, count 0 2006.258.00:30:56.88#ibcon#end of sib2, iclass 40, count 0 2006.258.00:30:56.88#ibcon#*after write, iclass 40, count 0 2006.258.00:30:56.88#ibcon#*before return 0, iclass 40, count 0 2006.258.00:30:56.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:30:56.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:30:56.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:30:56.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:30:56.88$vck44/vblo=1,629.99 2006.258.00:30:56.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.258.00:30:56.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.258.00:30:56.88#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:56.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:30:56.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:30:56.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:30:56.88#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:30:56.88#ibcon#first serial, iclass 4, count 0 2006.258.00:30:56.88#ibcon#enter sib2, iclass 4, count 0 2006.258.00:30:56.88#ibcon#flushed, iclass 4, count 0 2006.258.00:30:56.88#ibcon#about to write, iclass 4, count 0 2006.258.00:30:56.88#ibcon#wrote, iclass 4, count 0 2006.258.00:30:56.88#ibcon#about to read 3, iclass 4, count 0 2006.258.00:30:56.90#ibcon#read 3, iclass 4, count 0 2006.258.00:30:56.90#ibcon#about to read 4, iclass 4, count 0 2006.258.00:30:56.90#ibcon#read 4, iclass 4, count 0 2006.258.00:30:56.90#ibcon#about to read 5, iclass 4, count 0 2006.258.00:30:56.90#ibcon#read 5, iclass 4, count 0 2006.258.00:30:56.90#ibcon#about to read 6, iclass 4, count 0 2006.258.00:30:56.90#ibcon#read 6, iclass 4, count 0 2006.258.00:30:56.90#ibcon#end of sib2, iclass 4, count 0 2006.258.00:30:56.90#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:30:56.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:30:56.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:30:56.90#ibcon#*before write, iclass 4, count 0 2006.258.00:30:56.90#ibcon#enter sib2, iclass 4, count 0 2006.258.00:30:56.90#ibcon#flushed, iclass 4, count 0 2006.258.00:30:56.90#ibcon#about to write, iclass 4, count 0 2006.258.00:30:56.90#ibcon#wrote, iclass 4, count 0 2006.258.00:30:56.90#ibcon#about to read 3, iclass 4, count 0 2006.258.00:30:56.94#ibcon#read 3, iclass 4, count 0 2006.258.00:30:56.94#ibcon#about to read 4, iclass 4, count 0 2006.258.00:30:56.94#ibcon#read 4, iclass 4, count 0 2006.258.00:30:56.94#ibcon#about to read 5, iclass 4, count 0 2006.258.00:30:56.94#ibcon#read 5, iclass 4, count 0 2006.258.00:30:56.94#ibcon#about to read 6, iclass 4, count 0 2006.258.00:30:56.94#ibcon#read 6, iclass 4, count 0 2006.258.00:30:56.94#ibcon#end of sib2, iclass 4, count 0 2006.258.00:30:56.94#ibcon#*after write, iclass 4, count 0 2006.258.00:30:56.94#ibcon#*before return 0, iclass 4, count 0 2006.258.00:30:56.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:30:56.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:30:56.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:30:56.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:30:56.94$vck44/vb=1,4 2006.258.00:30:56.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.258.00:30:56.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.258.00:30:56.94#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:56.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:30:56.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:30:56.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:30:56.94#ibcon#enter wrdev, iclass 6, count 2 2006.258.00:30:56.94#ibcon#first serial, iclass 6, count 2 2006.258.00:30:56.94#ibcon#enter sib2, iclass 6, count 2 2006.258.00:30:56.94#ibcon#flushed, iclass 6, count 2 2006.258.00:30:56.94#ibcon#about to write, iclass 6, count 2 2006.258.00:30:56.94#ibcon#wrote, iclass 6, count 2 2006.258.00:30:56.94#ibcon#about to read 3, iclass 6, count 2 2006.258.00:30:56.96#ibcon#read 3, iclass 6, count 2 2006.258.00:30:56.96#ibcon#about to read 4, iclass 6, count 2 2006.258.00:30:56.96#ibcon#read 4, iclass 6, count 2 2006.258.00:30:56.96#ibcon#about to read 5, iclass 6, count 2 2006.258.00:30:56.96#ibcon#read 5, iclass 6, count 2 2006.258.00:30:56.96#ibcon#about to read 6, iclass 6, count 2 2006.258.00:30:56.96#ibcon#read 6, iclass 6, count 2 2006.258.00:30:56.96#ibcon#end of sib2, iclass 6, count 2 2006.258.00:30:56.96#ibcon#*mode == 0, iclass 6, count 2 2006.258.00:30:56.96#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.258.00:30:56.96#ibcon#[27=AT01-04\r\n] 2006.258.00:30:56.96#ibcon#*before write, iclass 6, count 2 2006.258.00:30:56.96#ibcon#enter sib2, iclass 6, count 2 2006.258.00:30:56.96#ibcon#flushed, iclass 6, count 2 2006.258.00:30:56.96#ibcon#about to write, iclass 6, count 2 2006.258.00:30:56.96#ibcon#wrote, iclass 6, count 2 2006.258.00:30:56.96#ibcon#about to read 3, iclass 6, count 2 2006.258.00:30:56.99#ibcon#read 3, iclass 6, count 2 2006.258.00:30:56.99#ibcon#about to read 4, iclass 6, count 2 2006.258.00:30:56.99#ibcon#read 4, iclass 6, count 2 2006.258.00:30:56.99#ibcon#about to read 5, iclass 6, count 2 2006.258.00:30:56.99#ibcon#read 5, iclass 6, count 2 2006.258.00:30:56.99#ibcon#about to read 6, iclass 6, count 2 2006.258.00:30:56.99#ibcon#read 6, iclass 6, count 2 2006.258.00:30:56.99#ibcon#end of sib2, iclass 6, count 2 2006.258.00:30:56.99#ibcon#*after write, iclass 6, count 2 2006.258.00:30:56.99#ibcon#*before return 0, iclass 6, count 2 2006.258.00:30:56.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:30:56.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:30:56.99#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.258.00:30:56.99#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:56.99#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:30:57.11#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:30:57.11#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:30:57.11#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:30:57.11#ibcon#first serial, iclass 6, count 0 2006.258.00:30:57.11#ibcon#enter sib2, iclass 6, count 0 2006.258.00:30:57.11#ibcon#flushed, iclass 6, count 0 2006.258.00:30:57.11#ibcon#about to write, iclass 6, count 0 2006.258.00:30:57.11#ibcon#wrote, iclass 6, count 0 2006.258.00:30:57.11#ibcon#about to read 3, iclass 6, count 0 2006.258.00:30:57.13#ibcon#read 3, iclass 6, count 0 2006.258.00:30:57.13#ibcon#about to read 4, iclass 6, count 0 2006.258.00:30:57.13#ibcon#read 4, iclass 6, count 0 2006.258.00:30:57.13#ibcon#about to read 5, iclass 6, count 0 2006.258.00:30:57.13#ibcon#read 5, iclass 6, count 0 2006.258.00:30:57.13#ibcon#about to read 6, iclass 6, count 0 2006.258.00:30:57.13#ibcon#read 6, iclass 6, count 0 2006.258.00:30:57.13#ibcon#end of sib2, iclass 6, count 0 2006.258.00:30:57.13#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:30:57.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:30:57.13#ibcon#[27=USB\r\n] 2006.258.00:30:57.13#ibcon#*before write, iclass 6, count 0 2006.258.00:30:57.13#ibcon#enter sib2, iclass 6, count 0 2006.258.00:30:57.13#ibcon#flushed, iclass 6, count 0 2006.258.00:30:57.13#ibcon#about to write, iclass 6, count 0 2006.258.00:30:57.13#ibcon#wrote, iclass 6, count 0 2006.258.00:30:57.13#ibcon#about to read 3, iclass 6, count 0 2006.258.00:30:57.16#ibcon#read 3, iclass 6, count 0 2006.258.00:30:57.16#ibcon#about to read 4, iclass 6, count 0 2006.258.00:30:57.16#ibcon#read 4, iclass 6, count 0 2006.258.00:30:57.16#ibcon#about to read 5, iclass 6, count 0 2006.258.00:30:57.16#ibcon#read 5, iclass 6, count 0 2006.258.00:30:57.16#ibcon#about to read 6, iclass 6, count 0 2006.258.00:30:57.16#ibcon#read 6, iclass 6, count 0 2006.258.00:30:57.16#ibcon#end of sib2, iclass 6, count 0 2006.258.00:30:57.16#ibcon#*after write, iclass 6, count 0 2006.258.00:30:57.16#ibcon#*before return 0, iclass 6, count 0 2006.258.00:30:57.16#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:30:57.16#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:30:57.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:30:57.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:30:57.16$vck44/vblo=2,634.99 2006.258.00:30:57.16#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.258.00:30:57.16#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.258.00:30:57.16#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:57.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:57.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:57.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:57.16#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:30:57.16#ibcon#first serial, iclass 10, count 0 2006.258.00:30:57.16#ibcon#enter sib2, iclass 10, count 0 2006.258.00:30:57.16#ibcon#flushed, iclass 10, count 0 2006.258.00:30:57.16#ibcon#about to write, iclass 10, count 0 2006.258.00:30:57.16#ibcon#wrote, iclass 10, count 0 2006.258.00:30:57.16#ibcon#about to read 3, iclass 10, count 0 2006.258.00:30:57.18#ibcon#read 3, iclass 10, count 0 2006.258.00:30:57.18#ibcon#about to read 4, iclass 10, count 0 2006.258.00:30:57.18#ibcon#read 4, iclass 10, count 0 2006.258.00:30:57.18#ibcon#about to read 5, iclass 10, count 0 2006.258.00:30:57.18#ibcon#read 5, iclass 10, count 0 2006.258.00:30:57.18#ibcon#about to read 6, iclass 10, count 0 2006.258.00:30:57.18#ibcon#read 6, iclass 10, count 0 2006.258.00:30:57.18#ibcon#end of sib2, iclass 10, count 0 2006.258.00:30:57.18#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:30:57.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:30:57.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:30:57.18#ibcon#*before write, iclass 10, count 0 2006.258.00:30:57.18#ibcon#enter sib2, iclass 10, count 0 2006.258.00:30:57.18#ibcon#flushed, iclass 10, count 0 2006.258.00:30:57.18#ibcon#about to write, iclass 10, count 0 2006.258.00:30:57.18#ibcon#wrote, iclass 10, count 0 2006.258.00:30:57.18#ibcon#about to read 3, iclass 10, count 0 2006.258.00:30:57.22#ibcon#read 3, iclass 10, count 0 2006.258.00:30:57.22#ibcon#about to read 4, iclass 10, count 0 2006.258.00:30:57.22#ibcon#read 4, iclass 10, count 0 2006.258.00:30:57.22#ibcon#about to read 5, iclass 10, count 0 2006.258.00:30:57.22#ibcon#read 5, iclass 10, count 0 2006.258.00:30:57.22#ibcon#about to read 6, iclass 10, count 0 2006.258.00:30:57.22#ibcon#read 6, iclass 10, count 0 2006.258.00:30:57.22#ibcon#end of sib2, iclass 10, count 0 2006.258.00:30:57.22#ibcon#*after write, iclass 10, count 0 2006.258.00:30:57.22#ibcon#*before return 0, iclass 10, count 0 2006.258.00:30:57.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:57.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:30:57.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:30:57.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:30:57.22$vck44/vb=2,5 2006.258.00:30:57.22#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.258.00:30:57.22#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.258.00:30:57.22#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:57.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:57.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:57.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:57.28#ibcon#enter wrdev, iclass 12, count 2 2006.258.00:30:57.28#ibcon#first serial, iclass 12, count 2 2006.258.00:30:57.28#ibcon#enter sib2, iclass 12, count 2 2006.258.00:30:57.28#ibcon#flushed, iclass 12, count 2 2006.258.00:30:57.28#ibcon#about to write, iclass 12, count 2 2006.258.00:30:57.28#ibcon#wrote, iclass 12, count 2 2006.258.00:30:57.28#ibcon#about to read 3, iclass 12, count 2 2006.258.00:30:57.30#ibcon#read 3, iclass 12, count 2 2006.258.00:30:57.30#ibcon#about to read 4, iclass 12, count 2 2006.258.00:30:57.30#ibcon#read 4, iclass 12, count 2 2006.258.00:30:57.30#ibcon#about to read 5, iclass 12, count 2 2006.258.00:30:57.30#ibcon#read 5, iclass 12, count 2 2006.258.00:30:57.30#ibcon#about to read 6, iclass 12, count 2 2006.258.00:30:57.30#ibcon#read 6, iclass 12, count 2 2006.258.00:30:57.30#ibcon#end of sib2, iclass 12, count 2 2006.258.00:30:57.30#ibcon#*mode == 0, iclass 12, count 2 2006.258.00:30:57.30#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.258.00:30:57.30#ibcon#[27=AT02-05\r\n] 2006.258.00:30:57.30#ibcon#*before write, iclass 12, count 2 2006.258.00:30:57.30#ibcon#enter sib2, iclass 12, count 2 2006.258.00:30:57.30#ibcon#flushed, iclass 12, count 2 2006.258.00:30:57.30#ibcon#about to write, iclass 12, count 2 2006.258.00:30:57.30#ibcon#wrote, iclass 12, count 2 2006.258.00:30:57.30#ibcon#about to read 3, iclass 12, count 2 2006.258.00:30:57.33#ibcon#read 3, iclass 12, count 2 2006.258.00:30:57.33#ibcon#about to read 4, iclass 12, count 2 2006.258.00:30:57.33#ibcon#read 4, iclass 12, count 2 2006.258.00:30:57.33#ibcon#about to read 5, iclass 12, count 2 2006.258.00:30:57.33#ibcon#read 5, iclass 12, count 2 2006.258.00:30:57.33#ibcon#about to read 6, iclass 12, count 2 2006.258.00:30:57.33#ibcon#read 6, iclass 12, count 2 2006.258.00:30:57.33#ibcon#end of sib2, iclass 12, count 2 2006.258.00:30:57.33#ibcon#*after write, iclass 12, count 2 2006.258.00:30:57.33#ibcon#*before return 0, iclass 12, count 2 2006.258.00:30:57.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:57.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:30:57.33#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.258.00:30:57.33#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:57.33#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:57.45#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:57.45#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:57.45#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:30:57.45#ibcon#first serial, iclass 12, count 0 2006.258.00:30:57.45#ibcon#enter sib2, iclass 12, count 0 2006.258.00:30:57.45#ibcon#flushed, iclass 12, count 0 2006.258.00:30:57.45#ibcon#about to write, iclass 12, count 0 2006.258.00:30:57.45#ibcon#wrote, iclass 12, count 0 2006.258.00:30:57.45#ibcon#about to read 3, iclass 12, count 0 2006.258.00:30:57.47#ibcon#read 3, iclass 12, count 0 2006.258.00:30:57.47#ibcon#about to read 4, iclass 12, count 0 2006.258.00:30:57.47#ibcon#read 4, iclass 12, count 0 2006.258.00:30:57.47#ibcon#about to read 5, iclass 12, count 0 2006.258.00:30:57.47#ibcon#read 5, iclass 12, count 0 2006.258.00:30:57.47#ibcon#about to read 6, iclass 12, count 0 2006.258.00:30:57.47#ibcon#read 6, iclass 12, count 0 2006.258.00:30:57.47#ibcon#end of sib2, iclass 12, count 0 2006.258.00:30:57.47#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:30:57.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:30:57.47#ibcon#[27=USB\r\n] 2006.258.00:30:57.47#ibcon#*before write, iclass 12, count 0 2006.258.00:30:57.47#ibcon#enter sib2, iclass 12, count 0 2006.258.00:30:57.47#ibcon#flushed, iclass 12, count 0 2006.258.00:30:57.47#ibcon#about to write, iclass 12, count 0 2006.258.00:30:57.47#ibcon#wrote, iclass 12, count 0 2006.258.00:30:57.47#ibcon#about to read 3, iclass 12, count 0 2006.258.00:30:57.50#ibcon#read 3, iclass 12, count 0 2006.258.00:30:57.50#ibcon#about to read 4, iclass 12, count 0 2006.258.00:30:57.50#ibcon#read 4, iclass 12, count 0 2006.258.00:30:57.50#ibcon#about to read 5, iclass 12, count 0 2006.258.00:30:57.50#ibcon#read 5, iclass 12, count 0 2006.258.00:30:57.50#ibcon#about to read 6, iclass 12, count 0 2006.258.00:30:57.50#ibcon#read 6, iclass 12, count 0 2006.258.00:30:57.50#ibcon#end of sib2, iclass 12, count 0 2006.258.00:30:57.50#ibcon#*after write, iclass 12, count 0 2006.258.00:30:57.50#ibcon#*before return 0, iclass 12, count 0 2006.258.00:30:57.50#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:57.50#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:30:57.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:30:57.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:30:57.50$vck44/vblo=3,649.99 2006.258.00:30:57.50#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.00:30:57.50#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.00:30:57.50#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:57.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:57.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:57.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:57.50#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:30:57.50#ibcon#first serial, iclass 14, count 0 2006.258.00:30:57.50#ibcon#enter sib2, iclass 14, count 0 2006.258.00:30:57.50#ibcon#flushed, iclass 14, count 0 2006.258.00:30:57.50#ibcon#about to write, iclass 14, count 0 2006.258.00:30:57.50#ibcon#wrote, iclass 14, count 0 2006.258.00:30:57.51#ibcon#about to read 3, iclass 14, count 0 2006.258.00:30:57.52#ibcon#read 3, iclass 14, count 0 2006.258.00:30:57.52#ibcon#about to read 4, iclass 14, count 0 2006.258.00:30:57.52#ibcon#read 4, iclass 14, count 0 2006.258.00:30:57.52#ibcon#about to read 5, iclass 14, count 0 2006.258.00:30:57.52#ibcon#read 5, iclass 14, count 0 2006.258.00:30:57.52#ibcon#about to read 6, iclass 14, count 0 2006.258.00:30:57.52#ibcon#read 6, iclass 14, count 0 2006.258.00:30:57.52#ibcon#end of sib2, iclass 14, count 0 2006.258.00:30:57.52#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:30:57.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:30:57.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:30:57.52#ibcon#*before write, iclass 14, count 0 2006.258.00:30:57.52#ibcon#enter sib2, iclass 14, count 0 2006.258.00:30:57.52#ibcon#flushed, iclass 14, count 0 2006.258.00:30:57.52#ibcon#about to write, iclass 14, count 0 2006.258.00:30:57.52#ibcon#wrote, iclass 14, count 0 2006.258.00:30:57.52#ibcon#about to read 3, iclass 14, count 0 2006.258.00:30:57.56#ibcon#read 3, iclass 14, count 0 2006.258.00:30:57.56#ibcon#about to read 4, iclass 14, count 0 2006.258.00:30:57.56#ibcon#read 4, iclass 14, count 0 2006.258.00:30:57.56#ibcon#about to read 5, iclass 14, count 0 2006.258.00:30:57.56#ibcon#read 5, iclass 14, count 0 2006.258.00:30:57.56#ibcon#about to read 6, iclass 14, count 0 2006.258.00:30:57.56#ibcon#read 6, iclass 14, count 0 2006.258.00:30:57.56#ibcon#end of sib2, iclass 14, count 0 2006.258.00:30:57.56#ibcon#*after write, iclass 14, count 0 2006.258.00:30:57.56#ibcon#*before return 0, iclass 14, count 0 2006.258.00:30:57.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:57.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:30:57.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:30:57.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:30:57.56$vck44/vb=3,4 2006.258.00:30:57.56#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.258.00:30:57.56#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.258.00:30:57.56#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:57.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:57.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:57.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:57.62#ibcon#enter wrdev, iclass 16, count 2 2006.258.00:30:57.62#ibcon#first serial, iclass 16, count 2 2006.258.00:30:57.62#ibcon#enter sib2, iclass 16, count 2 2006.258.00:30:57.62#ibcon#flushed, iclass 16, count 2 2006.258.00:30:57.62#ibcon#about to write, iclass 16, count 2 2006.258.00:30:57.62#ibcon#wrote, iclass 16, count 2 2006.258.00:30:57.62#ibcon#about to read 3, iclass 16, count 2 2006.258.00:30:57.64#ibcon#read 3, iclass 16, count 2 2006.258.00:30:57.64#ibcon#about to read 4, iclass 16, count 2 2006.258.00:30:57.64#ibcon#read 4, iclass 16, count 2 2006.258.00:30:57.64#ibcon#about to read 5, iclass 16, count 2 2006.258.00:30:57.64#ibcon#read 5, iclass 16, count 2 2006.258.00:30:57.64#ibcon#about to read 6, iclass 16, count 2 2006.258.00:30:57.64#ibcon#read 6, iclass 16, count 2 2006.258.00:30:57.64#ibcon#end of sib2, iclass 16, count 2 2006.258.00:30:57.64#ibcon#*mode == 0, iclass 16, count 2 2006.258.00:30:57.64#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.258.00:30:57.64#ibcon#[27=AT03-04\r\n] 2006.258.00:30:57.64#ibcon#*before write, iclass 16, count 2 2006.258.00:30:57.64#ibcon#enter sib2, iclass 16, count 2 2006.258.00:30:57.64#ibcon#flushed, iclass 16, count 2 2006.258.00:30:57.64#ibcon#about to write, iclass 16, count 2 2006.258.00:30:57.64#ibcon#wrote, iclass 16, count 2 2006.258.00:30:57.64#ibcon#about to read 3, iclass 16, count 2 2006.258.00:30:57.67#ibcon#read 3, iclass 16, count 2 2006.258.00:30:57.67#ibcon#about to read 4, iclass 16, count 2 2006.258.00:30:57.67#ibcon#read 4, iclass 16, count 2 2006.258.00:30:57.67#ibcon#about to read 5, iclass 16, count 2 2006.258.00:30:57.67#ibcon#read 5, iclass 16, count 2 2006.258.00:30:57.67#ibcon#about to read 6, iclass 16, count 2 2006.258.00:30:57.67#ibcon#read 6, iclass 16, count 2 2006.258.00:30:57.67#ibcon#end of sib2, iclass 16, count 2 2006.258.00:30:57.67#ibcon#*after write, iclass 16, count 2 2006.258.00:30:57.67#ibcon#*before return 0, iclass 16, count 2 2006.258.00:30:57.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:57.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:30:57.67#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.258.00:30:57.67#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:57.67#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:57.79#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:57.79#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:57.79#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:30:57.79#ibcon#first serial, iclass 16, count 0 2006.258.00:30:57.79#ibcon#enter sib2, iclass 16, count 0 2006.258.00:30:57.79#ibcon#flushed, iclass 16, count 0 2006.258.00:30:57.79#ibcon#about to write, iclass 16, count 0 2006.258.00:30:57.79#ibcon#wrote, iclass 16, count 0 2006.258.00:30:57.79#ibcon#about to read 3, iclass 16, count 0 2006.258.00:30:57.81#ibcon#read 3, iclass 16, count 0 2006.258.00:30:57.81#ibcon#about to read 4, iclass 16, count 0 2006.258.00:30:57.81#ibcon#read 4, iclass 16, count 0 2006.258.00:30:57.81#ibcon#about to read 5, iclass 16, count 0 2006.258.00:30:57.81#ibcon#read 5, iclass 16, count 0 2006.258.00:30:57.81#ibcon#about to read 6, iclass 16, count 0 2006.258.00:30:57.81#ibcon#read 6, iclass 16, count 0 2006.258.00:30:57.81#ibcon#end of sib2, iclass 16, count 0 2006.258.00:30:57.81#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:30:57.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:30:57.81#ibcon#[27=USB\r\n] 2006.258.00:30:57.81#ibcon#*before write, iclass 16, count 0 2006.258.00:30:57.81#ibcon#enter sib2, iclass 16, count 0 2006.258.00:30:57.81#ibcon#flushed, iclass 16, count 0 2006.258.00:30:57.81#ibcon#about to write, iclass 16, count 0 2006.258.00:30:57.81#ibcon#wrote, iclass 16, count 0 2006.258.00:30:57.81#ibcon#about to read 3, iclass 16, count 0 2006.258.00:30:57.84#ibcon#read 3, iclass 16, count 0 2006.258.00:30:57.84#ibcon#about to read 4, iclass 16, count 0 2006.258.00:30:57.84#ibcon#read 4, iclass 16, count 0 2006.258.00:30:57.84#ibcon#about to read 5, iclass 16, count 0 2006.258.00:30:57.84#ibcon#read 5, iclass 16, count 0 2006.258.00:30:57.84#ibcon#about to read 6, iclass 16, count 0 2006.258.00:30:57.84#ibcon#read 6, iclass 16, count 0 2006.258.00:30:57.84#ibcon#end of sib2, iclass 16, count 0 2006.258.00:30:57.84#ibcon#*after write, iclass 16, count 0 2006.258.00:30:57.84#ibcon#*before return 0, iclass 16, count 0 2006.258.00:30:57.84#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:57.84#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:30:57.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:30:57.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:30:57.84$vck44/vblo=4,679.99 2006.258.00:30:57.84#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.00:30:57.84#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.00:30:57.84#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:57.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:57.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:57.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:57.84#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:30:57.84#ibcon#first serial, iclass 18, count 0 2006.258.00:30:57.84#ibcon#enter sib2, iclass 18, count 0 2006.258.00:30:57.84#ibcon#flushed, iclass 18, count 0 2006.258.00:30:57.84#ibcon#about to write, iclass 18, count 0 2006.258.00:30:57.84#ibcon#wrote, iclass 18, count 0 2006.258.00:30:57.84#ibcon#about to read 3, iclass 18, count 0 2006.258.00:30:57.86#ibcon#read 3, iclass 18, count 0 2006.258.00:30:57.86#ibcon#about to read 4, iclass 18, count 0 2006.258.00:30:57.86#ibcon#read 4, iclass 18, count 0 2006.258.00:30:57.86#ibcon#about to read 5, iclass 18, count 0 2006.258.00:30:57.86#ibcon#read 5, iclass 18, count 0 2006.258.00:30:57.86#ibcon#about to read 6, iclass 18, count 0 2006.258.00:30:57.86#ibcon#read 6, iclass 18, count 0 2006.258.00:30:57.86#ibcon#end of sib2, iclass 18, count 0 2006.258.00:30:57.86#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:30:57.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:30:57.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:30:57.86#ibcon#*before write, iclass 18, count 0 2006.258.00:30:57.86#ibcon#enter sib2, iclass 18, count 0 2006.258.00:30:57.86#ibcon#flushed, iclass 18, count 0 2006.258.00:30:57.86#ibcon#about to write, iclass 18, count 0 2006.258.00:30:57.86#ibcon#wrote, iclass 18, count 0 2006.258.00:30:57.86#ibcon#about to read 3, iclass 18, count 0 2006.258.00:30:57.90#ibcon#read 3, iclass 18, count 0 2006.258.00:30:57.90#ibcon#about to read 4, iclass 18, count 0 2006.258.00:30:57.90#ibcon#read 4, iclass 18, count 0 2006.258.00:30:57.90#ibcon#about to read 5, iclass 18, count 0 2006.258.00:30:57.90#ibcon#read 5, iclass 18, count 0 2006.258.00:30:57.90#ibcon#about to read 6, iclass 18, count 0 2006.258.00:30:57.90#ibcon#read 6, iclass 18, count 0 2006.258.00:30:57.90#ibcon#end of sib2, iclass 18, count 0 2006.258.00:30:57.90#ibcon#*after write, iclass 18, count 0 2006.258.00:30:57.90#ibcon#*before return 0, iclass 18, count 0 2006.258.00:30:57.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:57.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:30:57.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:30:57.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:30:57.90$vck44/vb=4,5 2006.258.00:30:57.90#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.00:30:57.90#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.00:30:57.90#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:57.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:57.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:57.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:57.96#ibcon#enter wrdev, iclass 20, count 2 2006.258.00:30:57.96#ibcon#first serial, iclass 20, count 2 2006.258.00:30:57.96#ibcon#enter sib2, iclass 20, count 2 2006.258.00:30:57.96#ibcon#flushed, iclass 20, count 2 2006.258.00:30:57.96#ibcon#about to write, iclass 20, count 2 2006.258.00:30:57.96#ibcon#wrote, iclass 20, count 2 2006.258.00:30:57.96#ibcon#about to read 3, iclass 20, count 2 2006.258.00:30:57.98#ibcon#read 3, iclass 20, count 2 2006.258.00:30:57.98#ibcon#about to read 4, iclass 20, count 2 2006.258.00:30:57.98#ibcon#read 4, iclass 20, count 2 2006.258.00:30:57.98#ibcon#about to read 5, iclass 20, count 2 2006.258.00:30:57.98#ibcon#read 5, iclass 20, count 2 2006.258.00:30:57.98#ibcon#about to read 6, iclass 20, count 2 2006.258.00:30:57.98#ibcon#read 6, iclass 20, count 2 2006.258.00:30:57.98#ibcon#end of sib2, iclass 20, count 2 2006.258.00:30:57.98#ibcon#*mode == 0, iclass 20, count 2 2006.258.00:30:57.98#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.00:30:57.98#ibcon#[27=AT04-05\r\n] 2006.258.00:30:57.98#ibcon#*before write, iclass 20, count 2 2006.258.00:30:57.98#ibcon#enter sib2, iclass 20, count 2 2006.258.00:30:57.98#ibcon#flushed, iclass 20, count 2 2006.258.00:30:57.98#ibcon#about to write, iclass 20, count 2 2006.258.00:30:57.98#ibcon#wrote, iclass 20, count 2 2006.258.00:30:57.98#ibcon#about to read 3, iclass 20, count 2 2006.258.00:30:58.01#ibcon#read 3, iclass 20, count 2 2006.258.00:30:58.01#ibcon#about to read 4, iclass 20, count 2 2006.258.00:30:58.01#ibcon#read 4, iclass 20, count 2 2006.258.00:30:58.01#ibcon#about to read 5, iclass 20, count 2 2006.258.00:30:58.01#ibcon#read 5, iclass 20, count 2 2006.258.00:30:58.01#ibcon#about to read 6, iclass 20, count 2 2006.258.00:30:58.01#ibcon#read 6, iclass 20, count 2 2006.258.00:30:58.01#ibcon#end of sib2, iclass 20, count 2 2006.258.00:30:58.01#ibcon#*after write, iclass 20, count 2 2006.258.00:30:58.01#ibcon#*before return 0, iclass 20, count 2 2006.258.00:30:58.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:58.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:30:58.01#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.00:30:58.01#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:58.01#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:58.13#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:58.13#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:58.13#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:30:58.13#ibcon#first serial, iclass 20, count 0 2006.258.00:30:58.13#ibcon#enter sib2, iclass 20, count 0 2006.258.00:30:58.13#ibcon#flushed, iclass 20, count 0 2006.258.00:30:58.13#ibcon#about to write, iclass 20, count 0 2006.258.00:30:58.13#ibcon#wrote, iclass 20, count 0 2006.258.00:30:58.13#ibcon#about to read 3, iclass 20, count 0 2006.258.00:30:58.15#ibcon#read 3, iclass 20, count 0 2006.258.00:30:58.15#ibcon#about to read 4, iclass 20, count 0 2006.258.00:30:58.15#ibcon#read 4, iclass 20, count 0 2006.258.00:30:58.15#ibcon#about to read 5, iclass 20, count 0 2006.258.00:30:58.15#ibcon#read 5, iclass 20, count 0 2006.258.00:30:58.15#ibcon#about to read 6, iclass 20, count 0 2006.258.00:30:58.15#ibcon#read 6, iclass 20, count 0 2006.258.00:30:58.15#ibcon#end of sib2, iclass 20, count 0 2006.258.00:30:58.15#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:30:58.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:30:58.15#ibcon#[27=USB\r\n] 2006.258.00:30:58.15#ibcon#*before write, iclass 20, count 0 2006.258.00:30:58.15#ibcon#enter sib2, iclass 20, count 0 2006.258.00:30:58.15#ibcon#flushed, iclass 20, count 0 2006.258.00:30:58.15#ibcon#about to write, iclass 20, count 0 2006.258.00:30:58.15#ibcon#wrote, iclass 20, count 0 2006.258.00:30:58.15#ibcon#about to read 3, iclass 20, count 0 2006.258.00:30:58.18#ibcon#read 3, iclass 20, count 0 2006.258.00:30:58.18#ibcon#about to read 4, iclass 20, count 0 2006.258.00:30:58.18#ibcon#read 4, iclass 20, count 0 2006.258.00:30:58.18#ibcon#about to read 5, iclass 20, count 0 2006.258.00:30:58.18#ibcon#read 5, iclass 20, count 0 2006.258.00:30:58.18#ibcon#about to read 6, iclass 20, count 0 2006.258.00:30:58.18#ibcon#read 6, iclass 20, count 0 2006.258.00:30:58.18#ibcon#end of sib2, iclass 20, count 0 2006.258.00:30:58.18#ibcon#*after write, iclass 20, count 0 2006.258.00:30:58.18#ibcon#*before return 0, iclass 20, count 0 2006.258.00:30:58.18#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:58.18#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:30:58.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:30:58.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:30:58.18$vck44/vblo=5,709.99 2006.258.00:30:58.18#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.00:30:58.18#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.00:30:58.18#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:58.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:58.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:58.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:58.18#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:30:58.18#ibcon#first serial, iclass 22, count 0 2006.258.00:30:58.18#ibcon#enter sib2, iclass 22, count 0 2006.258.00:30:58.18#ibcon#flushed, iclass 22, count 0 2006.258.00:30:58.18#ibcon#about to write, iclass 22, count 0 2006.258.00:30:58.18#ibcon#wrote, iclass 22, count 0 2006.258.00:30:58.18#ibcon#about to read 3, iclass 22, count 0 2006.258.00:30:58.20#ibcon#read 3, iclass 22, count 0 2006.258.00:30:58.20#ibcon#about to read 4, iclass 22, count 0 2006.258.00:30:58.20#ibcon#read 4, iclass 22, count 0 2006.258.00:30:58.20#ibcon#about to read 5, iclass 22, count 0 2006.258.00:30:58.20#ibcon#read 5, iclass 22, count 0 2006.258.00:30:58.20#ibcon#about to read 6, iclass 22, count 0 2006.258.00:30:58.20#ibcon#read 6, iclass 22, count 0 2006.258.00:30:58.20#ibcon#end of sib2, iclass 22, count 0 2006.258.00:30:58.20#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:30:58.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:30:58.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:30:58.20#ibcon#*before write, iclass 22, count 0 2006.258.00:30:58.20#ibcon#enter sib2, iclass 22, count 0 2006.258.00:30:58.20#ibcon#flushed, iclass 22, count 0 2006.258.00:30:58.20#ibcon#about to write, iclass 22, count 0 2006.258.00:30:58.20#ibcon#wrote, iclass 22, count 0 2006.258.00:30:58.20#ibcon#about to read 3, iclass 22, count 0 2006.258.00:30:58.24#ibcon#read 3, iclass 22, count 0 2006.258.00:30:58.24#ibcon#about to read 4, iclass 22, count 0 2006.258.00:30:58.24#ibcon#read 4, iclass 22, count 0 2006.258.00:30:58.24#ibcon#about to read 5, iclass 22, count 0 2006.258.00:30:58.24#ibcon#read 5, iclass 22, count 0 2006.258.00:30:58.24#ibcon#about to read 6, iclass 22, count 0 2006.258.00:30:58.24#ibcon#read 6, iclass 22, count 0 2006.258.00:30:58.24#ibcon#end of sib2, iclass 22, count 0 2006.258.00:30:58.24#ibcon#*after write, iclass 22, count 0 2006.258.00:30:58.24#ibcon#*before return 0, iclass 22, count 0 2006.258.00:30:58.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:58.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:30:58.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:30:58.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:30:58.24$vck44/vb=5,4 2006.258.00:30:58.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.00:30:58.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.00:30:58.24#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:58.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:58.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:58.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:58.30#ibcon#enter wrdev, iclass 24, count 2 2006.258.00:30:58.30#ibcon#first serial, iclass 24, count 2 2006.258.00:30:58.30#ibcon#enter sib2, iclass 24, count 2 2006.258.00:30:58.30#ibcon#flushed, iclass 24, count 2 2006.258.00:30:58.30#ibcon#about to write, iclass 24, count 2 2006.258.00:30:58.30#ibcon#wrote, iclass 24, count 2 2006.258.00:30:58.30#ibcon#about to read 3, iclass 24, count 2 2006.258.00:30:58.32#ibcon#read 3, iclass 24, count 2 2006.258.00:30:58.32#ibcon#about to read 4, iclass 24, count 2 2006.258.00:30:58.32#ibcon#read 4, iclass 24, count 2 2006.258.00:30:58.32#ibcon#about to read 5, iclass 24, count 2 2006.258.00:30:58.32#ibcon#read 5, iclass 24, count 2 2006.258.00:30:58.32#ibcon#about to read 6, iclass 24, count 2 2006.258.00:30:58.32#ibcon#read 6, iclass 24, count 2 2006.258.00:30:58.32#ibcon#end of sib2, iclass 24, count 2 2006.258.00:30:58.32#ibcon#*mode == 0, iclass 24, count 2 2006.258.00:30:58.32#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.00:30:58.32#ibcon#[27=AT05-04\r\n] 2006.258.00:30:58.32#ibcon#*before write, iclass 24, count 2 2006.258.00:30:58.32#ibcon#enter sib2, iclass 24, count 2 2006.258.00:30:58.32#ibcon#flushed, iclass 24, count 2 2006.258.00:30:58.32#ibcon#about to write, iclass 24, count 2 2006.258.00:30:58.32#ibcon#wrote, iclass 24, count 2 2006.258.00:30:58.32#ibcon#about to read 3, iclass 24, count 2 2006.258.00:30:58.35#ibcon#read 3, iclass 24, count 2 2006.258.00:30:58.35#ibcon#about to read 4, iclass 24, count 2 2006.258.00:30:58.35#ibcon#read 4, iclass 24, count 2 2006.258.00:30:58.35#ibcon#about to read 5, iclass 24, count 2 2006.258.00:30:58.35#ibcon#read 5, iclass 24, count 2 2006.258.00:30:58.35#ibcon#about to read 6, iclass 24, count 2 2006.258.00:30:58.35#ibcon#read 6, iclass 24, count 2 2006.258.00:30:58.35#ibcon#end of sib2, iclass 24, count 2 2006.258.00:30:58.35#ibcon#*after write, iclass 24, count 2 2006.258.00:30:58.35#ibcon#*before return 0, iclass 24, count 2 2006.258.00:30:58.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:58.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:30:58.35#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.00:30:58.35#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:58.35#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:58.47#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:58.47#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:58.47#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:30:58.47#ibcon#first serial, iclass 24, count 0 2006.258.00:30:58.47#ibcon#enter sib2, iclass 24, count 0 2006.258.00:30:58.47#ibcon#flushed, iclass 24, count 0 2006.258.00:30:58.47#ibcon#about to write, iclass 24, count 0 2006.258.00:30:58.47#ibcon#wrote, iclass 24, count 0 2006.258.00:30:58.47#ibcon#about to read 3, iclass 24, count 0 2006.258.00:30:58.49#ibcon#read 3, iclass 24, count 0 2006.258.00:30:58.49#ibcon#about to read 4, iclass 24, count 0 2006.258.00:30:58.49#ibcon#read 4, iclass 24, count 0 2006.258.00:30:58.49#ibcon#about to read 5, iclass 24, count 0 2006.258.00:30:58.49#ibcon#read 5, iclass 24, count 0 2006.258.00:30:58.49#ibcon#about to read 6, iclass 24, count 0 2006.258.00:30:58.49#ibcon#read 6, iclass 24, count 0 2006.258.00:30:58.49#ibcon#end of sib2, iclass 24, count 0 2006.258.00:30:58.49#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:30:58.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:30:58.49#ibcon#[27=USB\r\n] 2006.258.00:30:58.49#ibcon#*before write, iclass 24, count 0 2006.258.00:30:58.49#ibcon#enter sib2, iclass 24, count 0 2006.258.00:30:58.49#ibcon#flushed, iclass 24, count 0 2006.258.00:30:58.49#ibcon#about to write, iclass 24, count 0 2006.258.00:30:58.49#ibcon#wrote, iclass 24, count 0 2006.258.00:30:58.49#ibcon#about to read 3, iclass 24, count 0 2006.258.00:30:58.52#ibcon#read 3, iclass 24, count 0 2006.258.00:30:58.52#ibcon#about to read 4, iclass 24, count 0 2006.258.00:30:58.52#ibcon#read 4, iclass 24, count 0 2006.258.00:30:58.52#ibcon#about to read 5, iclass 24, count 0 2006.258.00:30:58.52#ibcon#read 5, iclass 24, count 0 2006.258.00:30:58.52#ibcon#about to read 6, iclass 24, count 0 2006.258.00:30:58.52#ibcon#read 6, iclass 24, count 0 2006.258.00:30:58.52#ibcon#end of sib2, iclass 24, count 0 2006.258.00:30:58.52#ibcon#*after write, iclass 24, count 0 2006.258.00:30:58.52#ibcon#*before return 0, iclass 24, count 0 2006.258.00:30:58.52#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:58.52#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:30:58.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:30:58.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:30:58.52$vck44/vblo=6,719.99 2006.258.00:30:58.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.00:30:58.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.00:30:58.52#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:58.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:58.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:58.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:58.52#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:30:58.52#ibcon#first serial, iclass 26, count 0 2006.258.00:30:58.52#ibcon#enter sib2, iclass 26, count 0 2006.258.00:30:58.52#ibcon#flushed, iclass 26, count 0 2006.258.00:30:58.52#ibcon#about to write, iclass 26, count 0 2006.258.00:30:58.52#ibcon#wrote, iclass 26, count 0 2006.258.00:30:58.52#ibcon#about to read 3, iclass 26, count 0 2006.258.00:30:58.54#ibcon#read 3, iclass 26, count 0 2006.258.00:30:58.54#ibcon#about to read 4, iclass 26, count 0 2006.258.00:30:58.54#ibcon#read 4, iclass 26, count 0 2006.258.00:30:58.54#ibcon#about to read 5, iclass 26, count 0 2006.258.00:30:58.54#ibcon#read 5, iclass 26, count 0 2006.258.00:30:58.54#ibcon#about to read 6, iclass 26, count 0 2006.258.00:30:58.54#ibcon#read 6, iclass 26, count 0 2006.258.00:30:58.54#ibcon#end of sib2, iclass 26, count 0 2006.258.00:30:58.54#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:30:58.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:30:58.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:30:58.54#ibcon#*before write, iclass 26, count 0 2006.258.00:30:58.54#ibcon#enter sib2, iclass 26, count 0 2006.258.00:30:58.54#ibcon#flushed, iclass 26, count 0 2006.258.00:30:58.54#ibcon#about to write, iclass 26, count 0 2006.258.00:30:58.54#ibcon#wrote, iclass 26, count 0 2006.258.00:30:58.54#ibcon#about to read 3, iclass 26, count 0 2006.258.00:30:58.58#ibcon#read 3, iclass 26, count 0 2006.258.00:30:58.58#ibcon#about to read 4, iclass 26, count 0 2006.258.00:30:58.58#ibcon#read 4, iclass 26, count 0 2006.258.00:30:58.58#ibcon#about to read 5, iclass 26, count 0 2006.258.00:30:58.58#ibcon#read 5, iclass 26, count 0 2006.258.00:30:58.58#ibcon#about to read 6, iclass 26, count 0 2006.258.00:30:58.58#ibcon#read 6, iclass 26, count 0 2006.258.00:30:58.58#ibcon#end of sib2, iclass 26, count 0 2006.258.00:30:58.58#ibcon#*after write, iclass 26, count 0 2006.258.00:30:58.58#ibcon#*before return 0, iclass 26, count 0 2006.258.00:30:58.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:58.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:30:58.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:30:58.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:30:58.58$vck44/vb=6,4 2006.258.00:30:58.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.00:30:58.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.00:30:58.58#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:58.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:58.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:58.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:58.64#ibcon#enter wrdev, iclass 28, count 2 2006.258.00:30:58.64#ibcon#first serial, iclass 28, count 2 2006.258.00:30:58.64#ibcon#enter sib2, iclass 28, count 2 2006.258.00:30:58.64#ibcon#flushed, iclass 28, count 2 2006.258.00:30:58.64#ibcon#about to write, iclass 28, count 2 2006.258.00:30:58.64#ibcon#wrote, iclass 28, count 2 2006.258.00:30:58.64#ibcon#about to read 3, iclass 28, count 2 2006.258.00:30:58.66#ibcon#read 3, iclass 28, count 2 2006.258.00:30:58.66#ibcon#about to read 4, iclass 28, count 2 2006.258.00:30:58.66#ibcon#read 4, iclass 28, count 2 2006.258.00:30:58.66#ibcon#about to read 5, iclass 28, count 2 2006.258.00:30:58.66#ibcon#read 5, iclass 28, count 2 2006.258.00:30:58.66#ibcon#about to read 6, iclass 28, count 2 2006.258.00:30:58.66#ibcon#read 6, iclass 28, count 2 2006.258.00:30:58.66#ibcon#end of sib2, iclass 28, count 2 2006.258.00:30:58.66#ibcon#*mode == 0, iclass 28, count 2 2006.258.00:30:58.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.00:30:58.66#ibcon#[27=AT06-04\r\n] 2006.258.00:30:58.66#ibcon#*before write, iclass 28, count 2 2006.258.00:30:58.66#ibcon#enter sib2, iclass 28, count 2 2006.258.00:30:58.66#ibcon#flushed, iclass 28, count 2 2006.258.00:30:58.66#ibcon#about to write, iclass 28, count 2 2006.258.00:30:58.66#ibcon#wrote, iclass 28, count 2 2006.258.00:30:58.66#ibcon#about to read 3, iclass 28, count 2 2006.258.00:30:58.69#ibcon#read 3, iclass 28, count 2 2006.258.00:30:58.69#ibcon#about to read 4, iclass 28, count 2 2006.258.00:30:58.69#ibcon#read 4, iclass 28, count 2 2006.258.00:30:58.69#ibcon#about to read 5, iclass 28, count 2 2006.258.00:30:58.69#ibcon#read 5, iclass 28, count 2 2006.258.00:30:58.69#ibcon#about to read 6, iclass 28, count 2 2006.258.00:30:58.69#ibcon#read 6, iclass 28, count 2 2006.258.00:30:58.69#ibcon#end of sib2, iclass 28, count 2 2006.258.00:30:58.69#ibcon#*after write, iclass 28, count 2 2006.258.00:30:58.69#ibcon#*before return 0, iclass 28, count 2 2006.258.00:30:58.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:58.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:30:58.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.00:30:58.69#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:58.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:58.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:58.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:58.81#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:30:58.81#ibcon#first serial, iclass 28, count 0 2006.258.00:30:58.81#ibcon#enter sib2, iclass 28, count 0 2006.258.00:30:58.81#ibcon#flushed, iclass 28, count 0 2006.258.00:30:58.81#ibcon#about to write, iclass 28, count 0 2006.258.00:30:58.81#ibcon#wrote, iclass 28, count 0 2006.258.00:30:58.81#ibcon#about to read 3, iclass 28, count 0 2006.258.00:30:58.83#ibcon#read 3, iclass 28, count 0 2006.258.00:30:58.83#ibcon#about to read 4, iclass 28, count 0 2006.258.00:30:58.83#ibcon#read 4, iclass 28, count 0 2006.258.00:30:58.83#ibcon#about to read 5, iclass 28, count 0 2006.258.00:30:58.83#ibcon#read 5, iclass 28, count 0 2006.258.00:30:58.83#ibcon#about to read 6, iclass 28, count 0 2006.258.00:30:58.83#ibcon#read 6, iclass 28, count 0 2006.258.00:30:58.83#ibcon#end of sib2, iclass 28, count 0 2006.258.00:30:58.83#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:30:58.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:30:58.83#ibcon#[27=USB\r\n] 2006.258.00:30:58.83#ibcon#*before write, iclass 28, count 0 2006.258.00:30:58.83#ibcon#enter sib2, iclass 28, count 0 2006.258.00:30:58.83#ibcon#flushed, iclass 28, count 0 2006.258.00:30:58.83#ibcon#about to write, iclass 28, count 0 2006.258.00:30:58.83#ibcon#wrote, iclass 28, count 0 2006.258.00:30:58.83#ibcon#about to read 3, iclass 28, count 0 2006.258.00:30:58.86#ibcon#read 3, iclass 28, count 0 2006.258.00:30:58.86#ibcon#about to read 4, iclass 28, count 0 2006.258.00:30:58.86#ibcon#read 4, iclass 28, count 0 2006.258.00:30:58.86#ibcon#about to read 5, iclass 28, count 0 2006.258.00:30:58.86#ibcon#read 5, iclass 28, count 0 2006.258.00:30:58.86#ibcon#about to read 6, iclass 28, count 0 2006.258.00:30:58.86#ibcon#read 6, iclass 28, count 0 2006.258.00:30:58.86#ibcon#end of sib2, iclass 28, count 0 2006.258.00:30:58.86#ibcon#*after write, iclass 28, count 0 2006.258.00:30:58.86#ibcon#*before return 0, iclass 28, count 0 2006.258.00:30:58.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:58.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:30:58.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:30:58.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:30:58.86$vck44/vblo=7,734.99 2006.258.00:30:58.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.00:30:58.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.00:30:58.86#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:58.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:58.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:58.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:58.86#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:30:58.86#ibcon#first serial, iclass 30, count 0 2006.258.00:30:58.86#ibcon#enter sib2, iclass 30, count 0 2006.258.00:30:58.86#ibcon#flushed, iclass 30, count 0 2006.258.00:30:58.86#ibcon#about to write, iclass 30, count 0 2006.258.00:30:58.86#ibcon#wrote, iclass 30, count 0 2006.258.00:30:58.86#ibcon#about to read 3, iclass 30, count 0 2006.258.00:30:58.88#ibcon#read 3, iclass 30, count 0 2006.258.00:30:58.88#ibcon#about to read 4, iclass 30, count 0 2006.258.00:30:58.88#ibcon#read 4, iclass 30, count 0 2006.258.00:30:58.88#ibcon#about to read 5, iclass 30, count 0 2006.258.00:30:58.88#ibcon#read 5, iclass 30, count 0 2006.258.00:30:58.88#ibcon#about to read 6, iclass 30, count 0 2006.258.00:30:58.88#ibcon#read 6, iclass 30, count 0 2006.258.00:30:58.88#ibcon#end of sib2, iclass 30, count 0 2006.258.00:30:58.88#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:30:58.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:30:58.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:30:58.88#ibcon#*before write, iclass 30, count 0 2006.258.00:30:58.88#ibcon#enter sib2, iclass 30, count 0 2006.258.00:30:58.88#ibcon#flushed, iclass 30, count 0 2006.258.00:30:58.88#ibcon#about to write, iclass 30, count 0 2006.258.00:30:58.88#ibcon#wrote, iclass 30, count 0 2006.258.00:30:58.88#ibcon#about to read 3, iclass 30, count 0 2006.258.00:30:58.92#ibcon#read 3, iclass 30, count 0 2006.258.00:30:58.92#ibcon#about to read 4, iclass 30, count 0 2006.258.00:30:58.92#ibcon#read 4, iclass 30, count 0 2006.258.00:30:58.92#ibcon#about to read 5, iclass 30, count 0 2006.258.00:30:58.92#ibcon#read 5, iclass 30, count 0 2006.258.00:30:58.92#ibcon#about to read 6, iclass 30, count 0 2006.258.00:30:58.92#ibcon#read 6, iclass 30, count 0 2006.258.00:30:58.92#ibcon#end of sib2, iclass 30, count 0 2006.258.00:30:58.92#ibcon#*after write, iclass 30, count 0 2006.258.00:30:58.92#ibcon#*before return 0, iclass 30, count 0 2006.258.00:30:58.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:58.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:30:58.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:30:58.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:30:58.92$vck44/vb=7,4 2006.258.00:30:58.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.258.00:30:58.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.258.00:30:58.92#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:58.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:58.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:58.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:58.98#ibcon#enter wrdev, iclass 32, count 2 2006.258.00:30:58.98#ibcon#first serial, iclass 32, count 2 2006.258.00:30:58.98#ibcon#enter sib2, iclass 32, count 2 2006.258.00:30:58.98#ibcon#flushed, iclass 32, count 2 2006.258.00:30:58.98#ibcon#about to write, iclass 32, count 2 2006.258.00:30:58.98#ibcon#wrote, iclass 32, count 2 2006.258.00:30:58.98#ibcon#about to read 3, iclass 32, count 2 2006.258.00:30:59.00#ibcon#read 3, iclass 32, count 2 2006.258.00:30:59.00#ibcon#about to read 4, iclass 32, count 2 2006.258.00:30:59.00#ibcon#read 4, iclass 32, count 2 2006.258.00:30:59.00#ibcon#about to read 5, iclass 32, count 2 2006.258.00:30:59.00#ibcon#read 5, iclass 32, count 2 2006.258.00:30:59.00#ibcon#about to read 6, iclass 32, count 2 2006.258.00:30:59.00#ibcon#read 6, iclass 32, count 2 2006.258.00:30:59.00#ibcon#end of sib2, iclass 32, count 2 2006.258.00:30:59.00#ibcon#*mode == 0, iclass 32, count 2 2006.258.00:30:59.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.258.00:30:59.00#ibcon#[27=AT07-04\r\n] 2006.258.00:30:59.00#ibcon#*before write, iclass 32, count 2 2006.258.00:30:59.00#ibcon#enter sib2, iclass 32, count 2 2006.258.00:30:59.00#ibcon#flushed, iclass 32, count 2 2006.258.00:30:59.00#ibcon#about to write, iclass 32, count 2 2006.258.00:30:59.00#ibcon#wrote, iclass 32, count 2 2006.258.00:30:59.00#ibcon#about to read 3, iclass 32, count 2 2006.258.00:30:59.03#ibcon#read 3, iclass 32, count 2 2006.258.00:30:59.03#ibcon#about to read 4, iclass 32, count 2 2006.258.00:30:59.03#ibcon#read 4, iclass 32, count 2 2006.258.00:30:59.03#ibcon#about to read 5, iclass 32, count 2 2006.258.00:30:59.03#ibcon#read 5, iclass 32, count 2 2006.258.00:30:59.03#ibcon#about to read 6, iclass 32, count 2 2006.258.00:30:59.03#ibcon#read 6, iclass 32, count 2 2006.258.00:30:59.03#ibcon#end of sib2, iclass 32, count 2 2006.258.00:30:59.03#ibcon#*after write, iclass 32, count 2 2006.258.00:30:59.03#ibcon#*before return 0, iclass 32, count 2 2006.258.00:30:59.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:59.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:30:59.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.258.00:30:59.03#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:59.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:59.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:59.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:59.15#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:30:59.15#ibcon#first serial, iclass 32, count 0 2006.258.00:30:59.15#ibcon#enter sib2, iclass 32, count 0 2006.258.00:30:59.15#ibcon#flushed, iclass 32, count 0 2006.258.00:30:59.15#ibcon#about to write, iclass 32, count 0 2006.258.00:30:59.15#ibcon#wrote, iclass 32, count 0 2006.258.00:30:59.15#ibcon#about to read 3, iclass 32, count 0 2006.258.00:30:59.17#ibcon#read 3, iclass 32, count 0 2006.258.00:30:59.17#ibcon#about to read 4, iclass 32, count 0 2006.258.00:30:59.17#ibcon#read 4, iclass 32, count 0 2006.258.00:30:59.17#ibcon#about to read 5, iclass 32, count 0 2006.258.00:30:59.17#ibcon#read 5, iclass 32, count 0 2006.258.00:30:59.17#ibcon#about to read 6, iclass 32, count 0 2006.258.00:30:59.17#ibcon#read 6, iclass 32, count 0 2006.258.00:30:59.17#ibcon#end of sib2, iclass 32, count 0 2006.258.00:30:59.17#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:30:59.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:30:59.17#ibcon#[27=USB\r\n] 2006.258.00:30:59.17#ibcon#*before write, iclass 32, count 0 2006.258.00:30:59.17#ibcon#enter sib2, iclass 32, count 0 2006.258.00:30:59.17#ibcon#flushed, iclass 32, count 0 2006.258.00:30:59.17#ibcon#about to write, iclass 32, count 0 2006.258.00:30:59.17#ibcon#wrote, iclass 32, count 0 2006.258.00:30:59.17#ibcon#about to read 3, iclass 32, count 0 2006.258.00:30:59.20#ibcon#read 3, iclass 32, count 0 2006.258.00:30:59.20#ibcon#about to read 4, iclass 32, count 0 2006.258.00:30:59.20#ibcon#read 4, iclass 32, count 0 2006.258.00:30:59.20#ibcon#about to read 5, iclass 32, count 0 2006.258.00:30:59.20#ibcon#read 5, iclass 32, count 0 2006.258.00:30:59.20#ibcon#about to read 6, iclass 32, count 0 2006.258.00:30:59.20#ibcon#read 6, iclass 32, count 0 2006.258.00:30:59.20#ibcon#end of sib2, iclass 32, count 0 2006.258.00:30:59.20#ibcon#*after write, iclass 32, count 0 2006.258.00:30:59.20#ibcon#*before return 0, iclass 32, count 0 2006.258.00:30:59.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:59.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:30:59.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:30:59.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:30:59.20$vck44/vblo=8,744.99 2006.258.00:30:59.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.00:30:59.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.00:30:59.20#ibcon#ireg 17 cls_cnt 0 2006.258.00:30:59.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:59.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:59.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:59.20#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:30:59.20#ibcon#first serial, iclass 34, count 0 2006.258.00:30:59.20#ibcon#enter sib2, iclass 34, count 0 2006.258.00:30:59.20#ibcon#flushed, iclass 34, count 0 2006.258.00:30:59.20#ibcon#about to write, iclass 34, count 0 2006.258.00:30:59.20#ibcon#wrote, iclass 34, count 0 2006.258.00:30:59.20#ibcon#about to read 3, iclass 34, count 0 2006.258.00:30:59.22#ibcon#read 3, iclass 34, count 0 2006.258.00:30:59.22#ibcon#about to read 4, iclass 34, count 0 2006.258.00:30:59.22#ibcon#read 4, iclass 34, count 0 2006.258.00:30:59.22#ibcon#about to read 5, iclass 34, count 0 2006.258.00:30:59.22#ibcon#read 5, iclass 34, count 0 2006.258.00:30:59.22#ibcon#about to read 6, iclass 34, count 0 2006.258.00:30:59.22#ibcon#read 6, iclass 34, count 0 2006.258.00:30:59.22#ibcon#end of sib2, iclass 34, count 0 2006.258.00:30:59.22#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:30:59.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:30:59.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:30:59.22#ibcon#*before write, iclass 34, count 0 2006.258.00:30:59.22#ibcon#enter sib2, iclass 34, count 0 2006.258.00:30:59.22#ibcon#flushed, iclass 34, count 0 2006.258.00:30:59.22#ibcon#about to write, iclass 34, count 0 2006.258.00:30:59.22#ibcon#wrote, iclass 34, count 0 2006.258.00:30:59.22#ibcon#about to read 3, iclass 34, count 0 2006.258.00:30:59.26#ibcon#read 3, iclass 34, count 0 2006.258.00:30:59.26#ibcon#about to read 4, iclass 34, count 0 2006.258.00:30:59.26#ibcon#read 4, iclass 34, count 0 2006.258.00:30:59.26#ibcon#about to read 5, iclass 34, count 0 2006.258.00:30:59.26#ibcon#read 5, iclass 34, count 0 2006.258.00:30:59.26#ibcon#about to read 6, iclass 34, count 0 2006.258.00:30:59.26#ibcon#read 6, iclass 34, count 0 2006.258.00:30:59.26#ibcon#end of sib2, iclass 34, count 0 2006.258.00:30:59.26#ibcon#*after write, iclass 34, count 0 2006.258.00:30:59.26#ibcon#*before return 0, iclass 34, count 0 2006.258.00:30:59.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:59.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:30:59.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:30:59.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:30:59.26$vck44/vb=8,4 2006.258.00:30:59.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.258.00:30:59.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.258.00:30:59.26#ibcon#ireg 11 cls_cnt 2 2006.258.00:30:59.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:59.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:59.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:59.32#ibcon#enter wrdev, iclass 36, count 2 2006.258.00:30:59.32#ibcon#first serial, iclass 36, count 2 2006.258.00:30:59.32#ibcon#enter sib2, iclass 36, count 2 2006.258.00:30:59.32#ibcon#flushed, iclass 36, count 2 2006.258.00:30:59.32#ibcon#about to write, iclass 36, count 2 2006.258.00:30:59.32#ibcon#wrote, iclass 36, count 2 2006.258.00:30:59.32#ibcon#about to read 3, iclass 36, count 2 2006.258.00:30:59.34#ibcon#read 3, iclass 36, count 2 2006.258.00:30:59.34#ibcon#about to read 4, iclass 36, count 2 2006.258.00:30:59.34#ibcon#read 4, iclass 36, count 2 2006.258.00:30:59.34#ibcon#about to read 5, iclass 36, count 2 2006.258.00:30:59.34#ibcon#read 5, iclass 36, count 2 2006.258.00:30:59.34#ibcon#about to read 6, iclass 36, count 2 2006.258.00:30:59.34#ibcon#read 6, iclass 36, count 2 2006.258.00:30:59.34#ibcon#end of sib2, iclass 36, count 2 2006.258.00:30:59.34#ibcon#*mode == 0, iclass 36, count 2 2006.258.00:30:59.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.258.00:30:59.34#ibcon#[27=AT08-04\r\n] 2006.258.00:30:59.34#ibcon#*before write, iclass 36, count 2 2006.258.00:30:59.34#ibcon#enter sib2, iclass 36, count 2 2006.258.00:30:59.34#ibcon#flushed, iclass 36, count 2 2006.258.00:30:59.34#ibcon#about to write, iclass 36, count 2 2006.258.00:30:59.34#ibcon#wrote, iclass 36, count 2 2006.258.00:30:59.34#ibcon#about to read 3, iclass 36, count 2 2006.258.00:30:59.37#ibcon#read 3, iclass 36, count 2 2006.258.00:30:59.37#ibcon#about to read 4, iclass 36, count 2 2006.258.00:30:59.37#ibcon#read 4, iclass 36, count 2 2006.258.00:30:59.37#ibcon#about to read 5, iclass 36, count 2 2006.258.00:30:59.37#ibcon#read 5, iclass 36, count 2 2006.258.00:30:59.37#ibcon#about to read 6, iclass 36, count 2 2006.258.00:30:59.37#ibcon#read 6, iclass 36, count 2 2006.258.00:30:59.37#ibcon#end of sib2, iclass 36, count 2 2006.258.00:30:59.37#ibcon#*after write, iclass 36, count 2 2006.258.00:30:59.37#ibcon#*before return 0, iclass 36, count 2 2006.258.00:30:59.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:59.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:30:59.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.258.00:30:59.37#ibcon#ireg 7 cls_cnt 0 2006.258.00:30:59.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:59.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:59.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:59.49#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:30:59.49#ibcon#first serial, iclass 36, count 0 2006.258.00:30:59.49#ibcon#enter sib2, iclass 36, count 0 2006.258.00:30:59.49#ibcon#flushed, iclass 36, count 0 2006.258.00:30:59.49#ibcon#about to write, iclass 36, count 0 2006.258.00:30:59.49#ibcon#wrote, iclass 36, count 0 2006.258.00:30:59.49#ibcon#about to read 3, iclass 36, count 0 2006.258.00:30:59.51#ibcon#read 3, iclass 36, count 0 2006.258.00:30:59.51#ibcon#about to read 4, iclass 36, count 0 2006.258.00:30:59.51#ibcon#read 4, iclass 36, count 0 2006.258.00:30:59.51#ibcon#about to read 5, iclass 36, count 0 2006.258.00:30:59.51#ibcon#read 5, iclass 36, count 0 2006.258.00:30:59.51#ibcon#about to read 6, iclass 36, count 0 2006.258.00:30:59.51#ibcon#read 6, iclass 36, count 0 2006.258.00:30:59.51#ibcon#end of sib2, iclass 36, count 0 2006.258.00:30:59.51#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:30:59.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:30:59.51#ibcon#[27=USB\r\n] 2006.258.00:30:59.51#ibcon#*before write, iclass 36, count 0 2006.258.00:30:59.51#ibcon#enter sib2, iclass 36, count 0 2006.258.00:30:59.51#ibcon#flushed, iclass 36, count 0 2006.258.00:30:59.51#ibcon#about to write, iclass 36, count 0 2006.258.00:30:59.51#ibcon#wrote, iclass 36, count 0 2006.258.00:30:59.51#ibcon#about to read 3, iclass 36, count 0 2006.258.00:30:59.54#ibcon#read 3, iclass 36, count 0 2006.258.00:30:59.54#ibcon#about to read 4, iclass 36, count 0 2006.258.00:30:59.54#ibcon#read 4, iclass 36, count 0 2006.258.00:30:59.54#ibcon#about to read 5, iclass 36, count 0 2006.258.00:30:59.54#ibcon#read 5, iclass 36, count 0 2006.258.00:30:59.54#ibcon#about to read 6, iclass 36, count 0 2006.258.00:30:59.54#ibcon#read 6, iclass 36, count 0 2006.258.00:30:59.54#ibcon#end of sib2, iclass 36, count 0 2006.258.00:30:59.54#ibcon#*after write, iclass 36, count 0 2006.258.00:30:59.54#ibcon#*before return 0, iclass 36, count 0 2006.258.00:30:59.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:59.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:30:59.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:30:59.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:30:59.54$vck44/vabw=wide 2006.258.00:30:59.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.00:30:59.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.00:30:59.54#ibcon#ireg 8 cls_cnt 0 2006.258.00:30:59.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:59.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:59.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:59.54#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:30:59.54#ibcon#first serial, iclass 38, count 0 2006.258.00:30:59.54#ibcon#enter sib2, iclass 38, count 0 2006.258.00:30:59.54#ibcon#flushed, iclass 38, count 0 2006.258.00:30:59.54#ibcon#about to write, iclass 38, count 0 2006.258.00:30:59.54#ibcon#wrote, iclass 38, count 0 2006.258.00:30:59.54#ibcon#about to read 3, iclass 38, count 0 2006.258.00:30:59.56#ibcon#read 3, iclass 38, count 0 2006.258.00:30:59.56#ibcon#about to read 4, iclass 38, count 0 2006.258.00:30:59.56#ibcon#read 4, iclass 38, count 0 2006.258.00:30:59.56#ibcon#about to read 5, iclass 38, count 0 2006.258.00:30:59.56#ibcon#read 5, iclass 38, count 0 2006.258.00:30:59.56#ibcon#about to read 6, iclass 38, count 0 2006.258.00:30:59.56#ibcon#read 6, iclass 38, count 0 2006.258.00:30:59.56#ibcon#end of sib2, iclass 38, count 0 2006.258.00:30:59.56#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:30:59.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:30:59.56#ibcon#[25=BW32\r\n] 2006.258.00:30:59.56#ibcon#*before write, iclass 38, count 0 2006.258.00:30:59.56#ibcon#enter sib2, iclass 38, count 0 2006.258.00:30:59.56#ibcon#flushed, iclass 38, count 0 2006.258.00:30:59.56#ibcon#about to write, iclass 38, count 0 2006.258.00:30:59.56#ibcon#wrote, iclass 38, count 0 2006.258.00:30:59.56#ibcon#about to read 3, iclass 38, count 0 2006.258.00:30:59.59#ibcon#read 3, iclass 38, count 0 2006.258.00:30:59.59#ibcon#about to read 4, iclass 38, count 0 2006.258.00:30:59.59#ibcon#read 4, iclass 38, count 0 2006.258.00:30:59.59#ibcon#about to read 5, iclass 38, count 0 2006.258.00:30:59.59#ibcon#read 5, iclass 38, count 0 2006.258.00:30:59.59#ibcon#about to read 6, iclass 38, count 0 2006.258.00:30:59.59#ibcon#read 6, iclass 38, count 0 2006.258.00:30:59.59#ibcon#end of sib2, iclass 38, count 0 2006.258.00:30:59.59#ibcon#*after write, iclass 38, count 0 2006.258.00:30:59.59#ibcon#*before return 0, iclass 38, count 0 2006.258.00:30:59.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:59.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:30:59.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:30:59.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:30:59.59$vck44/vbbw=wide 2006.258.00:30:59.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.00:30:59.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.00:30:59.59#ibcon#ireg 8 cls_cnt 0 2006.258.00:30:59.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:30:59.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:30:59.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:30:59.66#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:30:59.66#ibcon#first serial, iclass 40, count 0 2006.258.00:30:59.66#ibcon#enter sib2, iclass 40, count 0 2006.258.00:30:59.66#ibcon#flushed, iclass 40, count 0 2006.258.00:30:59.66#ibcon#about to write, iclass 40, count 0 2006.258.00:30:59.66#ibcon#wrote, iclass 40, count 0 2006.258.00:30:59.66#ibcon#about to read 3, iclass 40, count 0 2006.258.00:30:59.68#ibcon#read 3, iclass 40, count 0 2006.258.00:30:59.68#ibcon#about to read 4, iclass 40, count 0 2006.258.00:30:59.68#ibcon#read 4, iclass 40, count 0 2006.258.00:30:59.68#ibcon#about to read 5, iclass 40, count 0 2006.258.00:30:59.68#ibcon#read 5, iclass 40, count 0 2006.258.00:30:59.68#ibcon#about to read 6, iclass 40, count 0 2006.258.00:30:59.68#ibcon#read 6, iclass 40, count 0 2006.258.00:30:59.68#ibcon#end of sib2, iclass 40, count 0 2006.258.00:30:59.68#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:30:59.68#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:30:59.68#ibcon#[27=BW32\r\n] 2006.258.00:30:59.68#ibcon#*before write, iclass 40, count 0 2006.258.00:30:59.68#ibcon#enter sib2, iclass 40, count 0 2006.258.00:30:59.68#ibcon#flushed, iclass 40, count 0 2006.258.00:30:59.68#ibcon#about to write, iclass 40, count 0 2006.258.00:30:59.68#ibcon#wrote, iclass 40, count 0 2006.258.00:30:59.68#ibcon#about to read 3, iclass 40, count 0 2006.258.00:30:59.71#ibcon#read 3, iclass 40, count 0 2006.258.00:30:59.71#ibcon#about to read 4, iclass 40, count 0 2006.258.00:30:59.71#ibcon#read 4, iclass 40, count 0 2006.258.00:30:59.71#ibcon#about to read 5, iclass 40, count 0 2006.258.00:30:59.71#ibcon#read 5, iclass 40, count 0 2006.258.00:30:59.71#ibcon#about to read 6, iclass 40, count 0 2006.258.00:30:59.71#ibcon#read 6, iclass 40, count 0 2006.258.00:30:59.71#ibcon#end of sib2, iclass 40, count 0 2006.258.00:30:59.71#ibcon#*after write, iclass 40, count 0 2006.258.00:30:59.71#ibcon#*before return 0, iclass 40, count 0 2006.258.00:30:59.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:30:59.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:30:59.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:30:59.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:30:59.71$setupk4/ifdk4 2006.258.00:30:59.71$ifdk4/lo= 2006.258.00:30:59.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:30:59.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:30:59.71$ifdk4/patch= 2006.258.00:30:59.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:30:59.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:30:59.71$setupk4/!*+20s 2006.258.00:31:02.32#abcon#<5=/02 1.4 4.3 22.13 761016.2\r\n> 2006.258.00:31:02.34#abcon#{5=INTERFACE CLEAR} 2006.258.00:31:02.40#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:31:12.14#trakl#Source acquired 2006.258.00:31:12.49#abcon#<5=/02 1.4 4.3 22.14 761016.2\r\n> 2006.258.00:31:12.51#abcon#{5=INTERFACE CLEAR} 2006.258.00:31:12.57#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:31:13.14#flagr#flagr/antenna,acquired 2006.258.00:31:14.23$setupk4/"tpicd 2006.258.00:31:14.23$setupk4/echo=off 2006.258.00:31:14.23$setupk4/xlog=off 2006.258.00:31:14.23:!2006.258.00:32:41 2006.258.00:32:41.00:preob 2006.258.00:32:41.13/onsource/TRACKING 2006.258.00:32:41.13:!2006.258.00:32:51 2006.258.00:32:51.00:"tape 2006.258.00:32:51.00:"st=record 2006.258.00:32:51.00:data_valid=on 2006.258.00:32:51.00:midob 2006.258.00:32:52.13/onsource/TRACKING 2006.258.00:32:52.13/wx/22.16,1016.1,76 2006.258.00:32:52.31/cable/+6.4785E-03 2006.258.00:32:53.40/va/01,08,usb,yes,31,33 2006.258.00:32:53.40/va/02,07,usb,yes,34,34 2006.258.00:32:53.40/va/03,08,usb,yes,30,32 2006.258.00:32:53.40/va/04,07,usb,yes,35,36 2006.258.00:32:53.40/va/05,04,usb,yes,31,31 2006.258.00:32:53.40/va/06,04,usb,yes,34,34 2006.258.00:32:53.40/va/07,04,usb,yes,35,36 2006.258.00:32:53.40/va/08,04,usb,yes,29,36 2006.258.00:32:53.63/valo/01,524.99,yes,locked 2006.258.00:32:53.63/valo/02,534.99,yes,locked 2006.258.00:32:53.63/valo/03,564.99,yes,locked 2006.258.00:32:53.63/valo/04,624.99,yes,locked 2006.258.00:32:53.63/valo/05,734.99,yes,locked 2006.258.00:32:53.63/valo/06,814.99,yes,locked 2006.258.00:32:53.63/valo/07,864.99,yes,locked 2006.258.00:32:53.63/valo/08,884.99,yes,locked 2006.258.00:32:54.72/vb/01,04,usb,yes,31,29 2006.258.00:32:54.72/vb/02,05,usb,yes,29,29 2006.258.00:32:54.72/vb/03,04,usb,yes,30,33 2006.258.00:32:54.72/vb/04,05,usb,yes,31,30 2006.258.00:32:54.72/vb/05,04,usb,yes,27,29 2006.258.00:32:54.72/vb/06,04,usb,yes,32,28 2006.258.00:32:54.72/vb/07,04,usb,yes,31,31 2006.258.00:32:54.72/vb/08,04,usb,yes,29,32 2006.258.00:32:54.95/vblo/01,629.99,yes,locked 2006.258.00:32:54.95/vblo/02,634.99,yes,locked 2006.258.00:32:54.95/vblo/03,649.99,yes,locked 2006.258.00:32:54.95/vblo/04,679.99,yes,locked 2006.258.00:32:54.95/vblo/05,709.99,yes,locked 2006.258.00:32:54.95/vblo/06,719.99,yes,locked 2006.258.00:32:54.95/vblo/07,734.99,yes,locked 2006.258.00:32:54.95/vblo/08,744.99,yes,locked 2006.258.00:32:55.10/vabw/8 2006.258.00:32:55.25/vbbw/8 2006.258.00:32:55.34/xfe/off,on,15.0 2006.258.00:32:55.71/ifatt/23,28,28,28 2006.258.00:32:56.07/fmout-gps/S +4.56E-07 2006.258.00:32:56.10:!2006.258.00:33:51 2006.258.00:33:51.01:data_valid=off 2006.258.00:33:51.01:"et 2006.258.00:33:51.01:!+3s 2006.258.00:33:54.02:"tape 2006.258.00:33:54.02:postob 2006.258.00:33:54.08/cable/+6.4800E-03 2006.258.00:33:54.08/wx/22.18,1016.1,77 2006.258.00:33:55.08/fmout-gps/S +4.56E-07 2006.258.00:33:55.08:scan_name=258-0036,jd0609,300 2006.258.00:33:55.08:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.258.00:33:55.13#flagr#flagr/antenna,new-source 2006.258.00:33:56.14:checkk5 2006.258.00:33:56.55/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:33:56.95/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:33:57.34/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:33:57.74/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:33:58.12/chk_obsdata//k5ts1/T2580032??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.258.00:33:58.52/chk_obsdata//k5ts2/T2580032??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.258.00:33:58.92/chk_obsdata//k5ts3/T2580032??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.258.00:33:59.32/chk_obsdata//k5ts4/T2580032??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.258.00:34:00.04/k5log//k5ts1_log_newline 2006.258.00:34:00.76/k5log//k5ts2_log_newline 2006.258.00:34:01.48/k5log//k5ts3_log_newline 2006.258.00:34:02.18/k5log//k5ts4_log_newline 2006.258.00:34:02.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:34:02.21:setupk4=1 2006.258.00:34:02.21$setupk4/echo=on 2006.258.00:34:02.21$setupk4/pcalon 2006.258.00:34:02.21$pcalon/"no phase cal control is implemented here 2006.258.00:34:02.21$setupk4/"tpicd=stop 2006.258.00:34:02.21$setupk4/"rec=synch_on 2006.258.00:34:02.21$setupk4/"rec_mode=128 2006.258.00:34:02.21$setupk4/!* 2006.258.00:34:02.21$setupk4/recpk4 2006.258.00:34:02.21$recpk4/recpatch= 2006.258.00:34:02.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:34:02.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:34:02.22$setupk4/vck44 2006.258.00:34:02.22$vck44/valo=1,524.99 2006.258.00:34:02.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.00:34:02.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.00:34:02.22#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:02.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:02.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:02.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:02.22#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:34:02.22#ibcon#first serial, iclass 7, count 0 2006.258.00:34:02.22#ibcon#enter sib2, iclass 7, count 0 2006.258.00:34:02.22#ibcon#flushed, iclass 7, count 0 2006.258.00:34:02.22#ibcon#about to write, iclass 7, count 0 2006.258.00:34:02.22#ibcon#wrote, iclass 7, count 0 2006.258.00:34:02.22#ibcon#about to read 3, iclass 7, count 0 2006.258.00:34:02.24#ibcon#read 3, iclass 7, count 0 2006.258.00:34:02.24#ibcon#about to read 4, iclass 7, count 0 2006.258.00:34:02.24#ibcon#read 4, iclass 7, count 0 2006.258.00:34:02.24#ibcon#about to read 5, iclass 7, count 0 2006.258.00:34:02.24#ibcon#read 5, iclass 7, count 0 2006.258.00:34:02.24#ibcon#about to read 6, iclass 7, count 0 2006.258.00:34:02.24#ibcon#read 6, iclass 7, count 0 2006.258.00:34:02.24#ibcon#end of sib2, iclass 7, count 0 2006.258.00:34:02.24#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:34:02.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:34:02.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:34:02.24#ibcon#*before write, iclass 7, count 0 2006.258.00:34:02.24#ibcon#enter sib2, iclass 7, count 0 2006.258.00:34:02.24#ibcon#flushed, iclass 7, count 0 2006.258.00:34:02.24#ibcon#about to write, iclass 7, count 0 2006.258.00:34:02.24#ibcon#wrote, iclass 7, count 0 2006.258.00:34:02.24#ibcon#about to read 3, iclass 7, count 0 2006.258.00:34:02.29#ibcon#read 3, iclass 7, count 0 2006.258.00:34:02.29#ibcon#about to read 4, iclass 7, count 0 2006.258.00:34:02.29#ibcon#read 4, iclass 7, count 0 2006.258.00:34:02.29#ibcon#about to read 5, iclass 7, count 0 2006.258.00:34:02.29#ibcon#read 5, iclass 7, count 0 2006.258.00:34:02.29#ibcon#about to read 6, iclass 7, count 0 2006.258.00:34:02.29#ibcon#read 6, iclass 7, count 0 2006.258.00:34:02.29#ibcon#end of sib2, iclass 7, count 0 2006.258.00:34:02.29#ibcon#*after write, iclass 7, count 0 2006.258.00:34:02.29#ibcon#*before return 0, iclass 7, count 0 2006.258.00:34:02.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:02.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:02.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:34:02.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:34:02.29$vck44/va=1,8 2006.258.00:34:02.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.00:34:02.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.00:34:02.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:02.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:02.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:02.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:02.29#ibcon#enter wrdev, iclass 11, count 2 2006.258.00:34:02.29#ibcon#first serial, iclass 11, count 2 2006.258.00:34:02.29#ibcon#enter sib2, iclass 11, count 2 2006.258.00:34:02.29#ibcon#flushed, iclass 11, count 2 2006.258.00:34:02.29#ibcon#about to write, iclass 11, count 2 2006.258.00:34:02.29#ibcon#wrote, iclass 11, count 2 2006.258.00:34:02.29#ibcon#about to read 3, iclass 11, count 2 2006.258.00:34:02.31#ibcon#read 3, iclass 11, count 2 2006.258.00:34:02.31#ibcon#about to read 4, iclass 11, count 2 2006.258.00:34:02.31#ibcon#read 4, iclass 11, count 2 2006.258.00:34:02.31#ibcon#about to read 5, iclass 11, count 2 2006.258.00:34:02.31#ibcon#read 5, iclass 11, count 2 2006.258.00:34:02.31#ibcon#about to read 6, iclass 11, count 2 2006.258.00:34:02.31#ibcon#read 6, iclass 11, count 2 2006.258.00:34:02.31#ibcon#end of sib2, iclass 11, count 2 2006.258.00:34:02.31#ibcon#*mode == 0, iclass 11, count 2 2006.258.00:34:02.31#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.00:34:02.31#ibcon#[25=AT01-08\r\n] 2006.258.00:34:02.31#ibcon#*before write, iclass 11, count 2 2006.258.00:34:02.31#ibcon#enter sib2, iclass 11, count 2 2006.258.00:34:02.31#ibcon#flushed, iclass 11, count 2 2006.258.00:34:02.31#ibcon#about to write, iclass 11, count 2 2006.258.00:34:02.31#ibcon#wrote, iclass 11, count 2 2006.258.00:34:02.31#ibcon#about to read 3, iclass 11, count 2 2006.258.00:34:02.34#ibcon#read 3, iclass 11, count 2 2006.258.00:34:02.34#ibcon#about to read 4, iclass 11, count 2 2006.258.00:34:02.34#ibcon#read 4, iclass 11, count 2 2006.258.00:34:02.34#ibcon#about to read 5, iclass 11, count 2 2006.258.00:34:02.34#ibcon#read 5, iclass 11, count 2 2006.258.00:34:02.34#ibcon#about to read 6, iclass 11, count 2 2006.258.00:34:02.34#ibcon#read 6, iclass 11, count 2 2006.258.00:34:02.34#ibcon#end of sib2, iclass 11, count 2 2006.258.00:34:02.34#ibcon#*after write, iclass 11, count 2 2006.258.00:34:02.34#ibcon#*before return 0, iclass 11, count 2 2006.258.00:34:02.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:02.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:02.34#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.00:34:02.34#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:02.34#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:02.46#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:02.46#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:02.46#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:34:02.46#ibcon#first serial, iclass 11, count 0 2006.258.00:34:02.46#ibcon#enter sib2, iclass 11, count 0 2006.258.00:34:02.46#ibcon#flushed, iclass 11, count 0 2006.258.00:34:02.46#ibcon#about to write, iclass 11, count 0 2006.258.00:34:02.46#ibcon#wrote, iclass 11, count 0 2006.258.00:34:02.46#ibcon#about to read 3, iclass 11, count 0 2006.258.00:34:02.48#ibcon#read 3, iclass 11, count 0 2006.258.00:34:02.48#ibcon#about to read 4, iclass 11, count 0 2006.258.00:34:02.48#ibcon#read 4, iclass 11, count 0 2006.258.00:34:02.48#ibcon#about to read 5, iclass 11, count 0 2006.258.00:34:02.48#ibcon#read 5, iclass 11, count 0 2006.258.00:34:02.48#ibcon#about to read 6, iclass 11, count 0 2006.258.00:34:02.48#ibcon#read 6, iclass 11, count 0 2006.258.00:34:02.48#ibcon#end of sib2, iclass 11, count 0 2006.258.00:34:02.48#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:34:02.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:34:02.48#ibcon#[25=USB\r\n] 2006.258.00:34:02.48#ibcon#*before write, iclass 11, count 0 2006.258.00:34:02.48#ibcon#enter sib2, iclass 11, count 0 2006.258.00:34:02.48#ibcon#flushed, iclass 11, count 0 2006.258.00:34:02.48#ibcon#about to write, iclass 11, count 0 2006.258.00:34:02.48#ibcon#wrote, iclass 11, count 0 2006.258.00:34:02.48#ibcon#about to read 3, iclass 11, count 0 2006.258.00:34:02.51#ibcon#read 3, iclass 11, count 0 2006.258.00:34:02.51#ibcon#about to read 4, iclass 11, count 0 2006.258.00:34:02.51#ibcon#read 4, iclass 11, count 0 2006.258.00:34:02.51#ibcon#about to read 5, iclass 11, count 0 2006.258.00:34:02.51#ibcon#read 5, iclass 11, count 0 2006.258.00:34:02.51#ibcon#about to read 6, iclass 11, count 0 2006.258.00:34:02.51#ibcon#read 6, iclass 11, count 0 2006.258.00:34:02.51#ibcon#end of sib2, iclass 11, count 0 2006.258.00:34:02.51#ibcon#*after write, iclass 11, count 0 2006.258.00:34:02.51#ibcon#*before return 0, iclass 11, count 0 2006.258.00:34:02.51#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:02.51#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:02.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:34:02.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:34:02.51$vck44/valo=2,534.99 2006.258.00:34:02.51#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.258.00:34:02.51#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.258.00:34:02.51#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:02.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:34:02.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:34:02.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:34:02.51#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:34:02.51#ibcon#first serial, iclass 13, count 0 2006.258.00:34:02.51#ibcon#enter sib2, iclass 13, count 0 2006.258.00:34:02.51#ibcon#flushed, iclass 13, count 0 2006.258.00:34:02.51#ibcon#about to write, iclass 13, count 0 2006.258.00:34:02.51#ibcon#wrote, iclass 13, count 0 2006.258.00:34:02.51#ibcon#about to read 3, iclass 13, count 0 2006.258.00:34:02.53#ibcon#read 3, iclass 13, count 0 2006.258.00:34:02.53#ibcon#about to read 4, iclass 13, count 0 2006.258.00:34:02.53#ibcon#read 4, iclass 13, count 0 2006.258.00:34:02.53#ibcon#about to read 5, iclass 13, count 0 2006.258.00:34:02.53#ibcon#read 5, iclass 13, count 0 2006.258.00:34:02.53#ibcon#about to read 6, iclass 13, count 0 2006.258.00:34:02.53#ibcon#read 6, iclass 13, count 0 2006.258.00:34:02.53#ibcon#end of sib2, iclass 13, count 0 2006.258.00:34:02.53#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:34:02.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:34:02.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:34:02.53#ibcon#*before write, iclass 13, count 0 2006.258.00:34:02.53#ibcon#enter sib2, iclass 13, count 0 2006.258.00:34:02.53#ibcon#flushed, iclass 13, count 0 2006.258.00:34:02.53#ibcon#about to write, iclass 13, count 0 2006.258.00:34:02.53#ibcon#wrote, iclass 13, count 0 2006.258.00:34:02.53#ibcon#about to read 3, iclass 13, count 0 2006.258.00:34:02.57#ibcon#read 3, iclass 13, count 0 2006.258.00:34:02.57#ibcon#about to read 4, iclass 13, count 0 2006.258.00:34:02.57#ibcon#read 4, iclass 13, count 0 2006.258.00:34:02.57#ibcon#about to read 5, iclass 13, count 0 2006.258.00:34:02.57#ibcon#read 5, iclass 13, count 0 2006.258.00:34:02.57#ibcon#about to read 6, iclass 13, count 0 2006.258.00:34:02.57#ibcon#read 6, iclass 13, count 0 2006.258.00:34:02.57#ibcon#end of sib2, iclass 13, count 0 2006.258.00:34:02.57#ibcon#*after write, iclass 13, count 0 2006.258.00:34:02.57#ibcon#*before return 0, iclass 13, count 0 2006.258.00:34:02.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:34:02.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:34:02.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:34:02.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:34:02.57$vck44/va=2,7 2006.258.00:34:02.57#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.258.00:34:02.57#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.258.00:34:02.57#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:02.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:34:02.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:34:02.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:34:02.63#ibcon#enter wrdev, iclass 15, count 2 2006.258.00:34:02.63#ibcon#first serial, iclass 15, count 2 2006.258.00:34:02.63#ibcon#enter sib2, iclass 15, count 2 2006.258.00:34:02.63#ibcon#flushed, iclass 15, count 2 2006.258.00:34:02.63#ibcon#about to write, iclass 15, count 2 2006.258.00:34:02.63#ibcon#wrote, iclass 15, count 2 2006.258.00:34:02.63#ibcon#about to read 3, iclass 15, count 2 2006.258.00:34:02.65#ibcon#read 3, iclass 15, count 2 2006.258.00:34:02.65#ibcon#about to read 4, iclass 15, count 2 2006.258.00:34:02.65#ibcon#read 4, iclass 15, count 2 2006.258.00:34:02.65#ibcon#about to read 5, iclass 15, count 2 2006.258.00:34:02.65#ibcon#read 5, iclass 15, count 2 2006.258.00:34:02.65#ibcon#about to read 6, iclass 15, count 2 2006.258.00:34:02.65#ibcon#read 6, iclass 15, count 2 2006.258.00:34:02.65#ibcon#end of sib2, iclass 15, count 2 2006.258.00:34:02.65#ibcon#*mode == 0, iclass 15, count 2 2006.258.00:34:02.65#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.258.00:34:02.65#ibcon#[25=AT02-07\r\n] 2006.258.00:34:02.65#ibcon#*before write, iclass 15, count 2 2006.258.00:34:02.65#ibcon#enter sib2, iclass 15, count 2 2006.258.00:34:02.65#ibcon#flushed, iclass 15, count 2 2006.258.00:34:02.65#ibcon#about to write, iclass 15, count 2 2006.258.00:34:02.65#ibcon#wrote, iclass 15, count 2 2006.258.00:34:02.65#ibcon#about to read 3, iclass 15, count 2 2006.258.00:34:02.68#ibcon#read 3, iclass 15, count 2 2006.258.00:34:02.68#ibcon#about to read 4, iclass 15, count 2 2006.258.00:34:02.68#ibcon#read 4, iclass 15, count 2 2006.258.00:34:02.68#ibcon#about to read 5, iclass 15, count 2 2006.258.00:34:02.68#ibcon#read 5, iclass 15, count 2 2006.258.00:34:02.68#ibcon#about to read 6, iclass 15, count 2 2006.258.00:34:02.68#ibcon#read 6, iclass 15, count 2 2006.258.00:34:02.68#ibcon#end of sib2, iclass 15, count 2 2006.258.00:34:02.68#ibcon#*after write, iclass 15, count 2 2006.258.00:34:02.68#ibcon#*before return 0, iclass 15, count 2 2006.258.00:34:02.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:34:02.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:34:02.68#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.258.00:34:02.68#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:02.68#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:34:02.80#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:34:02.80#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:34:02.80#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:34:02.80#ibcon#first serial, iclass 15, count 0 2006.258.00:34:02.80#ibcon#enter sib2, iclass 15, count 0 2006.258.00:34:02.80#ibcon#flushed, iclass 15, count 0 2006.258.00:34:02.80#ibcon#about to write, iclass 15, count 0 2006.258.00:34:02.80#ibcon#wrote, iclass 15, count 0 2006.258.00:34:02.80#ibcon#about to read 3, iclass 15, count 0 2006.258.00:34:02.82#ibcon#read 3, iclass 15, count 0 2006.258.00:34:02.82#ibcon#about to read 4, iclass 15, count 0 2006.258.00:34:02.82#ibcon#read 4, iclass 15, count 0 2006.258.00:34:02.82#ibcon#about to read 5, iclass 15, count 0 2006.258.00:34:02.82#ibcon#read 5, iclass 15, count 0 2006.258.00:34:02.82#ibcon#about to read 6, iclass 15, count 0 2006.258.00:34:02.82#ibcon#read 6, iclass 15, count 0 2006.258.00:34:02.82#ibcon#end of sib2, iclass 15, count 0 2006.258.00:34:02.82#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:34:02.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:34:02.82#ibcon#[25=USB\r\n] 2006.258.00:34:02.82#ibcon#*before write, iclass 15, count 0 2006.258.00:34:02.82#ibcon#enter sib2, iclass 15, count 0 2006.258.00:34:02.82#ibcon#flushed, iclass 15, count 0 2006.258.00:34:02.82#ibcon#about to write, iclass 15, count 0 2006.258.00:34:02.82#ibcon#wrote, iclass 15, count 0 2006.258.00:34:02.82#ibcon#about to read 3, iclass 15, count 0 2006.258.00:34:02.85#ibcon#read 3, iclass 15, count 0 2006.258.00:34:02.85#ibcon#about to read 4, iclass 15, count 0 2006.258.00:34:02.85#ibcon#read 4, iclass 15, count 0 2006.258.00:34:02.85#ibcon#about to read 5, iclass 15, count 0 2006.258.00:34:02.85#ibcon#read 5, iclass 15, count 0 2006.258.00:34:02.85#ibcon#about to read 6, iclass 15, count 0 2006.258.00:34:02.85#ibcon#read 6, iclass 15, count 0 2006.258.00:34:02.85#ibcon#end of sib2, iclass 15, count 0 2006.258.00:34:02.85#ibcon#*after write, iclass 15, count 0 2006.258.00:34:02.85#ibcon#*before return 0, iclass 15, count 0 2006.258.00:34:02.85#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:34:02.85#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:34:02.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:34:02.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:34:02.85$vck44/valo=3,564.99 2006.258.00:34:02.85#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.258.00:34:02.85#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.258.00:34:02.85#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:02.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:02.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:02.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:02.85#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:34:02.85#ibcon#first serial, iclass 17, count 0 2006.258.00:34:02.85#ibcon#enter sib2, iclass 17, count 0 2006.258.00:34:02.85#ibcon#flushed, iclass 17, count 0 2006.258.00:34:02.85#ibcon#about to write, iclass 17, count 0 2006.258.00:34:02.85#ibcon#wrote, iclass 17, count 0 2006.258.00:34:02.85#ibcon#about to read 3, iclass 17, count 0 2006.258.00:34:02.87#ibcon#read 3, iclass 17, count 0 2006.258.00:34:02.87#ibcon#about to read 4, iclass 17, count 0 2006.258.00:34:02.87#ibcon#read 4, iclass 17, count 0 2006.258.00:34:02.87#ibcon#about to read 5, iclass 17, count 0 2006.258.00:34:02.87#ibcon#read 5, iclass 17, count 0 2006.258.00:34:02.87#ibcon#about to read 6, iclass 17, count 0 2006.258.00:34:02.87#ibcon#read 6, iclass 17, count 0 2006.258.00:34:02.87#ibcon#end of sib2, iclass 17, count 0 2006.258.00:34:02.87#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:34:02.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:34:02.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:34:02.87#ibcon#*before write, iclass 17, count 0 2006.258.00:34:02.87#ibcon#enter sib2, iclass 17, count 0 2006.258.00:34:02.87#ibcon#flushed, iclass 17, count 0 2006.258.00:34:02.87#ibcon#about to write, iclass 17, count 0 2006.258.00:34:02.87#ibcon#wrote, iclass 17, count 0 2006.258.00:34:02.87#ibcon#about to read 3, iclass 17, count 0 2006.258.00:34:02.91#ibcon#read 3, iclass 17, count 0 2006.258.00:34:02.91#ibcon#about to read 4, iclass 17, count 0 2006.258.00:34:02.91#ibcon#read 4, iclass 17, count 0 2006.258.00:34:02.91#ibcon#about to read 5, iclass 17, count 0 2006.258.00:34:02.91#ibcon#read 5, iclass 17, count 0 2006.258.00:34:02.91#ibcon#about to read 6, iclass 17, count 0 2006.258.00:34:02.91#ibcon#read 6, iclass 17, count 0 2006.258.00:34:02.91#ibcon#end of sib2, iclass 17, count 0 2006.258.00:34:02.91#ibcon#*after write, iclass 17, count 0 2006.258.00:34:02.91#ibcon#*before return 0, iclass 17, count 0 2006.258.00:34:02.91#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:02.91#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:02.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:34:02.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:34:02.91$vck44/va=3,8 2006.258.00:34:02.91#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.258.00:34:02.91#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.258.00:34:02.91#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:02.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:02.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:02.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:02.97#ibcon#enter wrdev, iclass 19, count 2 2006.258.00:34:02.97#ibcon#first serial, iclass 19, count 2 2006.258.00:34:02.97#ibcon#enter sib2, iclass 19, count 2 2006.258.00:34:02.97#ibcon#flushed, iclass 19, count 2 2006.258.00:34:02.97#ibcon#about to write, iclass 19, count 2 2006.258.00:34:02.97#ibcon#wrote, iclass 19, count 2 2006.258.00:34:02.97#ibcon#about to read 3, iclass 19, count 2 2006.258.00:34:02.99#ibcon#read 3, iclass 19, count 2 2006.258.00:34:02.99#ibcon#about to read 4, iclass 19, count 2 2006.258.00:34:02.99#ibcon#read 4, iclass 19, count 2 2006.258.00:34:02.99#ibcon#about to read 5, iclass 19, count 2 2006.258.00:34:02.99#ibcon#read 5, iclass 19, count 2 2006.258.00:34:02.99#ibcon#about to read 6, iclass 19, count 2 2006.258.00:34:02.99#ibcon#read 6, iclass 19, count 2 2006.258.00:34:02.99#ibcon#end of sib2, iclass 19, count 2 2006.258.00:34:02.99#ibcon#*mode == 0, iclass 19, count 2 2006.258.00:34:02.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.258.00:34:02.99#ibcon#[25=AT03-08\r\n] 2006.258.00:34:02.99#ibcon#*before write, iclass 19, count 2 2006.258.00:34:02.99#ibcon#enter sib2, iclass 19, count 2 2006.258.00:34:02.99#ibcon#flushed, iclass 19, count 2 2006.258.00:34:02.99#ibcon#about to write, iclass 19, count 2 2006.258.00:34:02.99#ibcon#wrote, iclass 19, count 2 2006.258.00:34:02.99#ibcon#about to read 3, iclass 19, count 2 2006.258.00:34:03.02#ibcon#read 3, iclass 19, count 2 2006.258.00:34:03.02#ibcon#about to read 4, iclass 19, count 2 2006.258.00:34:03.02#ibcon#read 4, iclass 19, count 2 2006.258.00:34:03.02#ibcon#about to read 5, iclass 19, count 2 2006.258.00:34:03.02#ibcon#read 5, iclass 19, count 2 2006.258.00:34:03.02#ibcon#about to read 6, iclass 19, count 2 2006.258.00:34:03.02#ibcon#read 6, iclass 19, count 2 2006.258.00:34:03.02#ibcon#end of sib2, iclass 19, count 2 2006.258.00:34:03.02#ibcon#*after write, iclass 19, count 2 2006.258.00:34:03.02#ibcon#*before return 0, iclass 19, count 2 2006.258.00:34:03.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:03.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:03.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.258.00:34:03.02#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:03.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:03.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:03.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:03.14#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:34:03.14#ibcon#first serial, iclass 19, count 0 2006.258.00:34:03.14#ibcon#enter sib2, iclass 19, count 0 2006.258.00:34:03.14#ibcon#flushed, iclass 19, count 0 2006.258.00:34:03.14#ibcon#about to write, iclass 19, count 0 2006.258.00:34:03.14#ibcon#wrote, iclass 19, count 0 2006.258.00:34:03.14#ibcon#about to read 3, iclass 19, count 0 2006.258.00:34:03.16#ibcon#read 3, iclass 19, count 0 2006.258.00:34:03.16#ibcon#about to read 4, iclass 19, count 0 2006.258.00:34:03.16#ibcon#read 4, iclass 19, count 0 2006.258.00:34:03.16#ibcon#about to read 5, iclass 19, count 0 2006.258.00:34:03.16#ibcon#read 5, iclass 19, count 0 2006.258.00:34:03.16#ibcon#about to read 6, iclass 19, count 0 2006.258.00:34:03.16#ibcon#read 6, iclass 19, count 0 2006.258.00:34:03.16#ibcon#end of sib2, iclass 19, count 0 2006.258.00:34:03.16#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:34:03.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:34:03.16#ibcon#[25=USB\r\n] 2006.258.00:34:03.16#ibcon#*before write, iclass 19, count 0 2006.258.00:34:03.16#ibcon#enter sib2, iclass 19, count 0 2006.258.00:34:03.16#ibcon#flushed, iclass 19, count 0 2006.258.00:34:03.16#ibcon#about to write, iclass 19, count 0 2006.258.00:34:03.16#ibcon#wrote, iclass 19, count 0 2006.258.00:34:03.16#ibcon#about to read 3, iclass 19, count 0 2006.258.00:34:03.19#ibcon#read 3, iclass 19, count 0 2006.258.00:34:03.19#ibcon#about to read 4, iclass 19, count 0 2006.258.00:34:03.19#ibcon#read 4, iclass 19, count 0 2006.258.00:34:03.19#ibcon#about to read 5, iclass 19, count 0 2006.258.00:34:03.19#ibcon#read 5, iclass 19, count 0 2006.258.00:34:03.19#ibcon#about to read 6, iclass 19, count 0 2006.258.00:34:03.19#ibcon#read 6, iclass 19, count 0 2006.258.00:34:03.19#ibcon#end of sib2, iclass 19, count 0 2006.258.00:34:03.19#ibcon#*after write, iclass 19, count 0 2006.258.00:34:03.19#ibcon#*before return 0, iclass 19, count 0 2006.258.00:34:03.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:03.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:03.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:34:03.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:34:03.19$vck44/valo=4,624.99 2006.258.00:34:03.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.258.00:34:03.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.258.00:34:03.19#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:03.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:03.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:03.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:03.19#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:34:03.19#ibcon#first serial, iclass 21, count 0 2006.258.00:34:03.19#ibcon#enter sib2, iclass 21, count 0 2006.258.00:34:03.19#ibcon#flushed, iclass 21, count 0 2006.258.00:34:03.19#ibcon#about to write, iclass 21, count 0 2006.258.00:34:03.19#ibcon#wrote, iclass 21, count 0 2006.258.00:34:03.19#ibcon#about to read 3, iclass 21, count 0 2006.258.00:34:03.21#ibcon#read 3, iclass 21, count 0 2006.258.00:34:03.21#ibcon#about to read 4, iclass 21, count 0 2006.258.00:34:03.21#ibcon#read 4, iclass 21, count 0 2006.258.00:34:03.21#ibcon#about to read 5, iclass 21, count 0 2006.258.00:34:03.21#ibcon#read 5, iclass 21, count 0 2006.258.00:34:03.21#ibcon#about to read 6, iclass 21, count 0 2006.258.00:34:03.21#ibcon#read 6, iclass 21, count 0 2006.258.00:34:03.21#ibcon#end of sib2, iclass 21, count 0 2006.258.00:34:03.21#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:34:03.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:34:03.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:34:03.21#ibcon#*before write, iclass 21, count 0 2006.258.00:34:03.21#ibcon#enter sib2, iclass 21, count 0 2006.258.00:34:03.21#ibcon#flushed, iclass 21, count 0 2006.258.00:34:03.21#ibcon#about to write, iclass 21, count 0 2006.258.00:34:03.21#ibcon#wrote, iclass 21, count 0 2006.258.00:34:03.21#ibcon#about to read 3, iclass 21, count 0 2006.258.00:34:03.25#ibcon#read 3, iclass 21, count 0 2006.258.00:34:03.25#ibcon#about to read 4, iclass 21, count 0 2006.258.00:34:03.25#ibcon#read 4, iclass 21, count 0 2006.258.00:34:03.25#ibcon#about to read 5, iclass 21, count 0 2006.258.00:34:03.25#ibcon#read 5, iclass 21, count 0 2006.258.00:34:03.25#ibcon#about to read 6, iclass 21, count 0 2006.258.00:34:03.25#ibcon#read 6, iclass 21, count 0 2006.258.00:34:03.25#ibcon#end of sib2, iclass 21, count 0 2006.258.00:34:03.25#ibcon#*after write, iclass 21, count 0 2006.258.00:34:03.25#ibcon#*before return 0, iclass 21, count 0 2006.258.00:34:03.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:03.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:03.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:34:03.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:34:03.25$vck44/va=4,7 2006.258.00:34:03.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.258.00:34:03.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.258.00:34:03.25#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:03.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:03.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:03.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:03.31#ibcon#enter wrdev, iclass 23, count 2 2006.258.00:34:03.31#ibcon#first serial, iclass 23, count 2 2006.258.00:34:03.31#ibcon#enter sib2, iclass 23, count 2 2006.258.00:34:03.31#ibcon#flushed, iclass 23, count 2 2006.258.00:34:03.31#ibcon#about to write, iclass 23, count 2 2006.258.00:34:03.31#ibcon#wrote, iclass 23, count 2 2006.258.00:34:03.31#ibcon#about to read 3, iclass 23, count 2 2006.258.00:34:03.33#ibcon#read 3, iclass 23, count 2 2006.258.00:34:03.33#ibcon#about to read 4, iclass 23, count 2 2006.258.00:34:03.33#ibcon#read 4, iclass 23, count 2 2006.258.00:34:03.33#ibcon#about to read 5, iclass 23, count 2 2006.258.00:34:03.33#ibcon#read 5, iclass 23, count 2 2006.258.00:34:03.33#ibcon#about to read 6, iclass 23, count 2 2006.258.00:34:03.33#ibcon#read 6, iclass 23, count 2 2006.258.00:34:03.33#ibcon#end of sib2, iclass 23, count 2 2006.258.00:34:03.33#ibcon#*mode == 0, iclass 23, count 2 2006.258.00:34:03.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.258.00:34:03.33#ibcon#[25=AT04-07\r\n] 2006.258.00:34:03.33#ibcon#*before write, iclass 23, count 2 2006.258.00:34:03.33#ibcon#enter sib2, iclass 23, count 2 2006.258.00:34:03.33#ibcon#flushed, iclass 23, count 2 2006.258.00:34:03.33#ibcon#about to write, iclass 23, count 2 2006.258.00:34:03.33#ibcon#wrote, iclass 23, count 2 2006.258.00:34:03.33#ibcon#about to read 3, iclass 23, count 2 2006.258.00:34:03.36#ibcon#read 3, iclass 23, count 2 2006.258.00:34:03.36#ibcon#about to read 4, iclass 23, count 2 2006.258.00:34:03.36#ibcon#read 4, iclass 23, count 2 2006.258.00:34:03.36#ibcon#about to read 5, iclass 23, count 2 2006.258.00:34:03.36#ibcon#read 5, iclass 23, count 2 2006.258.00:34:03.36#ibcon#about to read 6, iclass 23, count 2 2006.258.00:34:03.36#ibcon#read 6, iclass 23, count 2 2006.258.00:34:03.36#ibcon#end of sib2, iclass 23, count 2 2006.258.00:34:03.36#ibcon#*after write, iclass 23, count 2 2006.258.00:34:03.40#ibcon#*before return 0, iclass 23, count 2 2006.258.00:34:03.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:03.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:03.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.258.00:34:03.40#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:03.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:03.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:03.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:03.52#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:34:03.52#ibcon#first serial, iclass 23, count 0 2006.258.00:34:03.52#ibcon#enter sib2, iclass 23, count 0 2006.258.00:34:03.52#ibcon#flushed, iclass 23, count 0 2006.258.00:34:03.52#ibcon#about to write, iclass 23, count 0 2006.258.00:34:03.52#ibcon#wrote, iclass 23, count 0 2006.258.00:34:03.52#ibcon#about to read 3, iclass 23, count 0 2006.258.00:34:03.54#ibcon#read 3, iclass 23, count 0 2006.258.00:34:03.54#ibcon#about to read 4, iclass 23, count 0 2006.258.00:34:03.54#ibcon#read 4, iclass 23, count 0 2006.258.00:34:03.54#ibcon#about to read 5, iclass 23, count 0 2006.258.00:34:03.54#ibcon#read 5, iclass 23, count 0 2006.258.00:34:03.54#ibcon#about to read 6, iclass 23, count 0 2006.258.00:34:03.54#ibcon#read 6, iclass 23, count 0 2006.258.00:34:03.54#ibcon#end of sib2, iclass 23, count 0 2006.258.00:34:03.54#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:34:03.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:34:03.54#ibcon#[25=USB\r\n] 2006.258.00:34:03.54#ibcon#*before write, iclass 23, count 0 2006.258.00:34:03.54#ibcon#enter sib2, iclass 23, count 0 2006.258.00:34:03.54#ibcon#flushed, iclass 23, count 0 2006.258.00:34:03.54#ibcon#about to write, iclass 23, count 0 2006.258.00:34:03.54#ibcon#wrote, iclass 23, count 0 2006.258.00:34:03.54#ibcon#about to read 3, iclass 23, count 0 2006.258.00:34:03.57#ibcon#read 3, iclass 23, count 0 2006.258.00:34:03.57#ibcon#about to read 4, iclass 23, count 0 2006.258.00:34:03.57#ibcon#read 4, iclass 23, count 0 2006.258.00:34:03.57#ibcon#about to read 5, iclass 23, count 0 2006.258.00:34:03.57#ibcon#read 5, iclass 23, count 0 2006.258.00:34:03.57#ibcon#about to read 6, iclass 23, count 0 2006.258.00:34:03.57#ibcon#read 6, iclass 23, count 0 2006.258.00:34:03.57#ibcon#end of sib2, iclass 23, count 0 2006.258.00:34:03.57#ibcon#*after write, iclass 23, count 0 2006.258.00:34:03.57#ibcon#*before return 0, iclass 23, count 0 2006.258.00:34:03.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:03.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:03.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:34:03.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:34:03.57$vck44/valo=5,734.99 2006.258.00:34:03.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.00:34:03.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.00:34:03.57#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:03.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:03.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:03.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:03.57#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:34:03.57#ibcon#first serial, iclass 25, count 0 2006.258.00:34:03.57#ibcon#enter sib2, iclass 25, count 0 2006.258.00:34:03.57#ibcon#flushed, iclass 25, count 0 2006.258.00:34:03.57#ibcon#about to write, iclass 25, count 0 2006.258.00:34:03.57#ibcon#wrote, iclass 25, count 0 2006.258.00:34:03.57#ibcon#about to read 3, iclass 25, count 0 2006.258.00:34:03.59#ibcon#read 3, iclass 25, count 0 2006.258.00:34:03.59#ibcon#about to read 4, iclass 25, count 0 2006.258.00:34:03.59#ibcon#read 4, iclass 25, count 0 2006.258.00:34:03.59#ibcon#about to read 5, iclass 25, count 0 2006.258.00:34:03.59#ibcon#read 5, iclass 25, count 0 2006.258.00:34:03.59#ibcon#about to read 6, iclass 25, count 0 2006.258.00:34:03.59#ibcon#read 6, iclass 25, count 0 2006.258.00:34:03.59#ibcon#end of sib2, iclass 25, count 0 2006.258.00:34:03.59#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:34:03.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:34:03.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:34:03.59#ibcon#*before write, iclass 25, count 0 2006.258.00:34:03.59#ibcon#enter sib2, iclass 25, count 0 2006.258.00:34:03.59#ibcon#flushed, iclass 25, count 0 2006.258.00:34:03.59#ibcon#about to write, iclass 25, count 0 2006.258.00:34:03.59#ibcon#wrote, iclass 25, count 0 2006.258.00:34:03.59#ibcon#about to read 3, iclass 25, count 0 2006.258.00:34:03.63#ibcon#read 3, iclass 25, count 0 2006.258.00:34:03.63#ibcon#about to read 4, iclass 25, count 0 2006.258.00:34:03.63#ibcon#read 4, iclass 25, count 0 2006.258.00:34:03.63#ibcon#about to read 5, iclass 25, count 0 2006.258.00:34:03.63#ibcon#read 5, iclass 25, count 0 2006.258.00:34:03.63#ibcon#about to read 6, iclass 25, count 0 2006.258.00:34:03.63#ibcon#read 6, iclass 25, count 0 2006.258.00:34:03.63#ibcon#end of sib2, iclass 25, count 0 2006.258.00:34:03.63#ibcon#*after write, iclass 25, count 0 2006.258.00:34:03.63#ibcon#*before return 0, iclass 25, count 0 2006.258.00:34:03.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:03.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:03.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:34:03.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:34:03.63$vck44/va=5,4 2006.258.00:34:03.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.258.00:34:03.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.258.00:34:03.63#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:03.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:03.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:03.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:03.69#ibcon#enter wrdev, iclass 27, count 2 2006.258.00:34:03.69#ibcon#first serial, iclass 27, count 2 2006.258.00:34:03.69#ibcon#enter sib2, iclass 27, count 2 2006.258.00:34:03.69#ibcon#flushed, iclass 27, count 2 2006.258.00:34:03.69#ibcon#about to write, iclass 27, count 2 2006.258.00:34:03.69#ibcon#wrote, iclass 27, count 2 2006.258.00:34:03.69#ibcon#about to read 3, iclass 27, count 2 2006.258.00:34:03.71#ibcon#read 3, iclass 27, count 2 2006.258.00:34:03.71#ibcon#about to read 4, iclass 27, count 2 2006.258.00:34:03.71#ibcon#read 4, iclass 27, count 2 2006.258.00:34:03.71#ibcon#about to read 5, iclass 27, count 2 2006.258.00:34:03.71#ibcon#read 5, iclass 27, count 2 2006.258.00:34:03.71#ibcon#about to read 6, iclass 27, count 2 2006.258.00:34:03.71#ibcon#read 6, iclass 27, count 2 2006.258.00:34:03.71#ibcon#end of sib2, iclass 27, count 2 2006.258.00:34:03.71#ibcon#*mode == 0, iclass 27, count 2 2006.258.00:34:03.71#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.258.00:34:03.71#ibcon#[25=AT05-04\r\n] 2006.258.00:34:03.71#ibcon#*before write, iclass 27, count 2 2006.258.00:34:03.71#ibcon#enter sib2, iclass 27, count 2 2006.258.00:34:03.71#ibcon#flushed, iclass 27, count 2 2006.258.00:34:03.71#ibcon#about to write, iclass 27, count 2 2006.258.00:34:03.71#ibcon#wrote, iclass 27, count 2 2006.258.00:34:03.71#ibcon#about to read 3, iclass 27, count 2 2006.258.00:34:03.74#ibcon#read 3, iclass 27, count 2 2006.258.00:34:03.74#ibcon#about to read 4, iclass 27, count 2 2006.258.00:34:03.74#ibcon#read 4, iclass 27, count 2 2006.258.00:34:03.74#ibcon#about to read 5, iclass 27, count 2 2006.258.00:34:03.74#ibcon#read 5, iclass 27, count 2 2006.258.00:34:03.74#ibcon#about to read 6, iclass 27, count 2 2006.258.00:34:03.74#ibcon#read 6, iclass 27, count 2 2006.258.00:34:03.74#ibcon#end of sib2, iclass 27, count 2 2006.258.00:34:03.74#ibcon#*after write, iclass 27, count 2 2006.258.00:34:03.74#ibcon#*before return 0, iclass 27, count 2 2006.258.00:34:03.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:03.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:03.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.258.00:34:03.74#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:03.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:03.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:03.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:03.86#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:34:03.86#ibcon#first serial, iclass 27, count 0 2006.258.00:34:03.86#ibcon#enter sib2, iclass 27, count 0 2006.258.00:34:03.86#ibcon#flushed, iclass 27, count 0 2006.258.00:34:03.86#ibcon#about to write, iclass 27, count 0 2006.258.00:34:03.86#ibcon#wrote, iclass 27, count 0 2006.258.00:34:03.86#ibcon#about to read 3, iclass 27, count 0 2006.258.00:34:03.88#ibcon#read 3, iclass 27, count 0 2006.258.00:34:03.88#ibcon#about to read 4, iclass 27, count 0 2006.258.00:34:03.88#ibcon#read 4, iclass 27, count 0 2006.258.00:34:03.88#ibcon#about to read 5, iclass 27, count 0 2006.258.00:34:03.88#ibcon#read 5, iclass 27, count 0 2006.258.00:34:03.88#ibcon#about to read 6, iclass 27, count 0 2006.258.00:34:03.88#ibcon#read 6, iclass 27, count 0 2006.258.00:34:03.88#ibcon#end of sib2, iclass 27, count 0 2006.258.00:34:03.88#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:34:03.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:34:03.88#ibcon#[25=USB\r\n] 2006.258.00:34:03.88#ibcon#*before write, iclass 27, count 0 2006.258.00:34:03.88#ibcon#enter sib2, iclass 27, count 0 2006.258.00:34:03.88#ibcon#flushed, iclass 27, count 0 2006.258.00:34:03.88#ibcon#about to write, iclass 27, count 0 2006.258.00:34:03.88#ibcon#wrote, iclass 27, count 0 2006.258.00:34:03.88#ibcon#about to read 3, iclass 27, count 0 2006.258.00:34:03.91#ibcon#read 3, iclass 27, count 0 2006.258.00:34:03.91#ibcon#about to read 4, iclass 27, count 0 2006.258.00:34:03.91#ibcon#read 4, iclass 27, count 0 2006.258.00:34:03.91#ibcon#about to read 5, iclass 27, count 0 2006.258.00:34:03.91#ibcon#read 5, iclass 27, count 0 2006.258.00:34:03.91#ibcon#about to read 6, iclass 27, count 0 2006.258.00:34:03.91#ibcon#read 6, iclass 27, count 0 2006.258.00:34:03.91#ibcon#end of sib2, iclass 27, count 0 2006.258.00:34:03.91#ibcon#*after write, iclass 27, count 0 2006.258.00:34:03.91#ibcon#*before return 0, iclass 27, count 0 2006.258.00:34:03.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:03.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:03.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:34:03.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:34:03.91$vck44/valo=6,814.99 2006.258.00:34:03.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.00:34:03.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.00:34:03.91#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:03.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:03.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:03.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:03.91#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:34:03.91#ibcon#first serial, iclass 29, count 0 2006.258.00:34:03.91#ibcon#enter sib2, iclass 29, count 0 2006.258.00:34:03.91#ibcon#flushed, iclass 29, count 0 2006.258.00:34:03.91#ibcon#about to write, iclass 29, count 0 2006.258.00:34:03.91#ibcon#wrote, iclass 29, count 0 2006.258.00:34:03.91#ibcon#about to read 3, iclass 29, count 0 2006.258.00:34:03.93#ibcon#read 3, iclass 29, count 0 2006.258.00:34:03.93#ibcon#about to read 4, iclass 29, count 0 2006.258.00:34:03.93#ibcon#read 4, iclass 29, count 0 2006.258.00:34:03.93#ibcon#about to read 5, iclass 29, count 0 2006.258.00:34:03.93#ibcon#read 5, iclass 29, count 0 2006.258.00:34:03.93#ibcon#about to read 6, iclass 29, count 0 2006.258.00:34:03.93#ibcon#read 6, iclass 29, count 0 2006.258.00:34:03.93#ibcon#end of sib2, iclass 29, count 0 2006.258.00:34:03.93#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:34:03.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:34:03.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:34:03.93#ibcon#*before write, iclass 29, count 0 2006.258.00:34:03.93#ibcon#enter sib2, iclass 29, count 0 2006.258.00:34:03.93#ibcon#flushed, iclass 29, count 0 2006.258.00:34:03.93#ibcon#about to write, iclass 29, count 0 2006.258.00:34:03.93#ibcon#wrote, iclass 29, count 0 2006.258.00:34:03.93#ibcon#about to read 3, iclass 29, count 0 2006.258.00:34:03.97#ibcon#read 3, iclass 29, count 0 2006.258.00:34:03.97#ibcon#about to read 4, iclass 29, count 0 2006.258.00:34:03.97#ibcon#read 4, iclass 29, count 0 2006.258.00:34:03.97#ibcon#about to read 5, iclass 29, count 0 2006.258.00:34:03.97#ibcon#read 5, iclass 29, count 0 2006.258.00:34:03.97#ibcon#about to read 6, iclass 29, count 0 2006.258.00:34:03.97#ibcon#read 6, iclass 29, count 0 2006.258.00:34:03.97#ibcon#end of sib2, iclass 29, count 0 2006.258.00:34:03.97#ibcon#*after write, iclass 29, count 0 2006.258.00:34:03.97#ibcon#*before return 0, iclass 29, count 0 2006.258.00:34:03.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:03.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:03.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:34:03.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:34:03.97$vck44/va=6,4 2006.258.00:34:03.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.00:34:03.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.00:34:03.97#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:03.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:04.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:04.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:04.03#ibcon#enter wrdev, iclass 31, count 2 2006.258.00:34:04.03#ibcon#first serial, iclass 31, count 2 2006.258.00:34:04.03#ibcon#enter sib2, iclass 31, count 2 2006.258.00:34:04.03#ibcon#flushed, iclass 31, count 2 2006.258.00:34:04.03#ibcon#about to write, iclass 31, count 2 2006.258.00:34:04.03#ibcon#wrote, iclass 31, count 2 2006.258.00:34:04.03#ibcon#about to read 3, iclass 31, count 2 2006.258.00:34:04.05#ibcon#read 3, iclass 31, count 2 2006.258.00:34:04.05#ibcon#about to read 4, iclass 31, count 2 2006.258.00:34:04.05#ibcon#read 4, iclass 31, count 2 2006.258.00:34:04.05#ibcon#about to read 5, iclass 31, count 2 2006.258.00:34:04.05#ibcon#read 5, iclass 31, count 2 2006.258.00:34:04.05#ibcon#about to read 6, iclass 31, count 2 2006.258.00:34:04.05#ibcon#read 6, iclass 31, count 2 2006.258.00:34:04.05#ibcon#end of sib2, iclass 31, count 2 2006.258.00:34:04.05#ibcon#*mode == 0, iclass 31, count 2 2006.258.00:34:04.05#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.00:34:04.05#ibcon#[25=AT06-04\r\n] 2006.258.00:34:04.05#ibcon#*before write, iclass 31, count 2 2006.258.00:34:04.05#ibcon#enter sib2, iclass 31, count 2 2006.258.00:34:04.05#ibcon#flushed, iclass 31, count 2 2006.258.00:34:04.05#ibcon#about to write, iclass 31, count 2 2006.258.00:34:04.05#ibcon#wrote, iclass 31, count 2 2006.258.00:34:04.05#ibcon#about to read 3, iclass 31, count 2 2006.258.00:34:04.08#ibcon#read 3, iclass 31, count 2 2006.258.00:34:04.08#ibcon#about to read 4, iclass 31, count 2 2006.258.00:34:04.08#ibcon#read 4, iclass 31, count 2 2006.258.00:34:04.08#ibcon#about to read 5, iclass 31, count 2 2006.258.00:34:04.08#ibcon#read 5, iclass 31, count 2 2006.258.00:34:04.08#ibcon#about to read 6, iclass 31, count 2 2006.258.00:34:04.08#ibcon#read 6, iclass 31, count 2 2006.258.00:34:04.08#ibcon#end of sib2, iclass 31, count 2 2006.258.00:34:04.08#ibcon#*after write, iclass 31, count 2 2006.258.00:34:04.08#ibcon#*before return 0, iclass 31, count 2 2006.258.00:34:04.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:04.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:04.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.00:34:04.08#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:04.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:04.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:04.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:04.20#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:34:04.20#ibcon#first serial, iclass 31, count 0 2006.258.00:34:04.20#ibcon#enter sib2, iclass 31, count 0 2006.258.00:34:04.20#ibcon#flushed, iclass 31, count 0 2006.258.00:34:04.20#ibcon#about to write, iclass 31, count 0 2006.258.00:34:04.20#ibcon#wrote, iclass 31, count 0 2006.258.00:34:04.20#ibcon#about to read 3, iclass 31, count 0 2006.258.00:34:04.22#ibcon#read 3, iclass 31, count 0 2006.258.00:34:04.22#ibcon#about to read 4, iclass 31, count 0 2006.258.00:34:04.22#ibcon#read 4, iclass 31, count 0 2006.258.00:34:04.22#ibcon#about to read 5, iclass 31, count 0 2006.258.00:34:04.22#ibcon#read 5, iclass 31, count 0 2006.258.00:34:04.22#ibcon#about to read 6, iclass 31, count 0 2006.258.00:34:04.22#ibcon#read 6, iclass 31, count 0 2006.258.00:34:04.22#ibcon#end of sib2, iclass 31, count 0 2006.258.00:34:04.22#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:34:04.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:34:04.22#ibcon#[25=USB\r\n] 2006.258.00:34:04.22#ibcon#*before write, iclass 31, count 0 2006.258.00:34:04.22#ibcon#enter sib2, iclass 31, count 0 2006.258.00:34:04.22#ibcon#flushed, iclass 31, count 0 2006.258.00:34:04.22#ibcon#about to write, iclass 31, count 0 2006.258.00:34:04.22#ibcon#wrote, iclass 31, count 0 2006.258.00:34:04.22#ibcon#about to read 3, iclass 31, count 0 2006.258.00:34:04.25#ibcon#read 3, iclass 31, count 0 2006.258.00:34:04.25#ibcon#about to read 4, iclass 31, count 0 2006.258.00:34:04.25#ibcon#read 4, iclass 31, count 0 2006.258.00:34:04.25#ibcon#about to read 5, iclass 31, count 0 2006.258.00:34:04.25#ibcon#read 5, iclass 31, count 0 2006.258.00:34:04.25#ibcon#about to read 6, iclass 31, count 0 2006.258.00:34:04.25#ibcon#read 6, iclass 31, count 0 2006.258.00:34:04.25#ibcon#end of sib2, iclass 31, count 0 2006.258.00:34:04.25#ibcon#*after write, iclass 31, count 0 2006.258.00:34:04.25#ibcon#*before return 0, iclass 31, count 0 2006.258.00:34:04.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:04.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:04.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:34:04.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:34:04.25$vck44/valo=7,864.99 2006.258.00:34:04.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.00:34:04.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.00:34:04.25#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:04.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:04.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:04.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:04.25#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:34:04.25#ibcon#first serial, iclass 33, count 0 2006.258.00:34:04.25#ibcon#enter sib2, iclass 33, count 0 2006.258.00:34:04.25#ibcon#flushed, iclass 33, count 0 2006.258.00:34:04.25#ibcon#about to write, iclass 33, count 0 2006.258.00:34:04.25#ibcon#wrote, iclass 33, count 0 2006.258.00:34:04.25#ibcon#about to read 3, iclass 33, count 0 2006.258.00:34:04.27#ibcon#read 3, iclass 33, count 0 2006.258.00:34:04.27#ibcon#about to read 4, iclass 33, count 0 2006.258.00:34:04.27#ibcon#read 4, iclass 33, count 0 2006.258.00:34:04.27#ibcon#about to read 5, iclass 33, count 0 2006.258.00:34:04.27#ibcon#read 5, iclass 33, count 0 2006.258.00:34:04.27#ibcon#about to read 6, iclass 33, count 0 2006.258.00:34:04.27#ibcon#read 6, iclass 33, count 0 2006.258.00:34:04.27#ibcon#end of sib2, iclass 33, count 0 2006.258.00:34:04.27#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:34:04.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:34:04.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:34:04.27#ibcon#*before write, iclass 33, count 0 2006.258.00:34:04.27#ibcon#enter sib2, iclass 33, count 0 2006.258.00:34:04.27#ibcon#flushed, iclass 33, count 0 2006.258.00:34:04.27#ibcon#about to write, iclass 33, count 0 2006.258.00:34:04.27#ibcon#wrote, iclass 33, count 0 2006.258.00:34:04.27#ibcon#about to read 3, iclass 33, count 0 2006.258.00:34:04.31#ibcon#read 3, iclass 33, count 0 2006.258.00:34:04.31#ibcon#about to read 4, iclass 33, count 0 2006.258.00:34:04.31#ibcon#read 4, iclass 33, count 0 2006.258.00:34:04.31#ibcon#about to read 5, iclass 33, count 0 2006.258.00:34:04.31#ibcon#read 5, iclass 33, count 0 2006.258.00:34:04.31#ibcon#about to read 6, iclass 33, count 0 2006.258.00:34:04.31#ibcon#read 6, iclass 33, count 0 2006.258.00:34:04.31#ibcon#end of sib2, iclass 33, count 0 2006.258.00:34:04.31#ibcon#*after write, iclass 33, count 0 2006.258.00:34:04.31#ibcon#*before return 0, iclass 33, count 0 2006.258.00:34:04.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:04.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:04.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:34:04.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:34:04.31$vck44/va=7,4 2006.258.00:34:04.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.00:34:04.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.00:34:04.31#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:04.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:04.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:04.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:04.37#ibcon#enter wrdev, iclass 35, count 2 2006.258.00:34:04.37#ibcon#first serial, iclass 35, count 2 2006.258.00:34:04.37#ibcon#enter sib2, iclass 35, count 2 2006.258.00:34:04.37#ibcon#flushed, iclass 35, count 2 2006.258.00:34:04.37#ibcon#about to write, iclass 35, count 2 2006.258.00:34:04.37#ibcon#wrote, iclass 35, count 2 2006.258.00:34:04.37#ibcon#about to read 3, iclass 35, count 2 2006.258.00:34:04.39#ibcon#read 3, iclass 35, count 2 2006.258.00:34:04.39#ibcon#about to read 4, iclass 35, count 2 2006.258.00:34:04.39#ibcon#read 4, iclass 35, count 2 2006.258.00:34:04.39#ibcon#about to read 5, iclass 35, count 2 2006.258.00:34:04.39#ibcon#read 5, iclass 35, count 2 2006.258.00:34:04.39#ibcon#about to read 6, iclass 35, count 2 2006.258.00:34:04.39#ibcon#read 6, iclass 35, count 2 2006.258.00:34:04.39#ibcon#end of sib2, iclass 35, count 2 2006.258.00:34:04.39#ibcon#*mode == 0, iclass 35, count 2 2006.258.00:34:04.39#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.00:34:04.39#ibcon#[25=AT07-04\r\n] 2006.258.00:34:04.39#ibcon#*before write, iclass 35, count 2 2006.258.00:34:04.39#ibcon#enter sib2, iclass 35, count 2 2006.258.00:34:04.39#ibcon#flushed, iclass 35, count 2 2006.258.00:34:04.39#ibcon#about to write, iclass 35, count 2 2006.258.00:34:04.39#ibcon#wrote, iclass 35, count 2 2006.258.00:34:04.39#ibcon#about to read 3, iclass 35, count 2 2006.258.00:34:04.42#ibcon#read 3, iclass 35, count 2 2006.258.00:34:04.42#ibcon#about to read 4, iclass 35, count 2 2006.258.00:34:04.42#ibcon#read 4, iclass 35, count 2 2006.258.00:34:04.42#ibcon#about to read 5, iclass 35, count 2 2006.258.00:34:04.42#ibcon#read 5, iclass 35, count 2 2006.258.00:34:04.42#ibcon#about to read 6, iclass 35, count 2 2006.258.00:34:04.42#ibcon#read 6, iclass 35, count 2 2006.258.00:34:04.42#ibcon#end of sib2, iclass 35, count 2 2006.258.00:34:04.42#ibcon#*after write, iclass 35, count 2 2006.258.00:34:04.42#ibcon#*before return 0, iclass 35, count 2 2006.258.00:34:04.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:04.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:04.42#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.00:34:04.42#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:04.42#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:04.54#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:04.54#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:04.54#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:34:04.54#ibcon#first serial, iclass 35, count 0 2006.258.00:34:04.54#ibcon#enter sib2, iclass 35, count 0 2006.258.00:34:04.54#ibcon#flushed, iclass 35, count 0 2006.258.00:34:04.54#ibcon#about to write, iclass 35, count 0 2006.258.00:34:04.54#ibcon#wrote, iclass 35, count 0 2006.258.00:34:04.54#ibcon#about to read 3, iclass 35, count 0 2006.258.00:34:04.56#ibcon#read 3, iclass 35, count 0 2006.258.00:34:04.56#ibcon#about to read 4, iclass 35, count 0 2006.258.00:34:04.56#ibcon#read 4, iclass 35, count 0 2006.258.00:34:04.56#ibcon#about to read 5, iclass 35, count 0 2006.258.00:34:04.56#ibcon#read 5, iclass 35, count 0 2006.258.00:34:04.56#ibcon#about to read 6, iclass 35, count 0 2006.258.00:34:04.56#ibcon#read 6, iclass 35, count 0 2006.258.00:34:04.56#ibcon#end of sib2, iclass 35, count 0 2006.258.00:34:04.56#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:34:04.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:34:04.56#ibcon#[25=USB\r\n] 2006.258.00:34:04.56#ibcon#*before write, iclass 35, count 0 2006.258.00:34:04.56#ibcon#enter sib2, iclass 35, count 0 2006.258.00:34:04.56#ibcon#flushed, iclass 35, count 0 2006.258.00:34:04.56#ibcon#about to write, iclass 35, count 0 2006.258.00:34:04.56#ibcon#wrote, iclass 35, count 0 2006.258.00:34:04.56#ibcon#about to read 3, iclass 35, count 0 2006.258.00:34:04.59#ibcon#read 3, iclass 35, count 0 2006.258.00:34:04.59#ibcon#about to read 4, iclass 35, count 0 2006.258.00:34:04.59#ibcon#read 4, iclass 35, count 0 2006.258.00:34:04.59#ibcon#about to read 5, iclass 35, count 0 2006.258.00:34:04.59#ibcon#read 5, iclass 35, count 0 2006.258.00:34:04.59#ibcon#about to read 6, iclass 35, count 0 2006.258.00:34:04.59#ibcon#read 6, iclass 35, count 0 2006.258.00:34:04.59#ibcon#end of sib2, iclass 35, count 0 2006.258.00:34:04.59#ibcon#*after write, iclass 35, count 0 2006.258.00:34:04.59#ibcon#*before return 0, iclass 35, count 0 2006.258.00:34:04.59#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:04.59#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:04.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:34:04.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:34:04.59$vck44/valo=8,884.99 2006.258.00:34:04.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.00:34:04.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.00:34:04.59#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:04.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:04.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:04.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:04.59#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:34:04.59#ibcon#first serial, iclass 37, count 0 2006.258.00:34:04.59#ibcon#enter sib2, iclass 37, count 0 2006.258.00:34:04.59#ibcon#flushed, iclass 37, count 0 2006.258.00:34:04.59#ibcon#about to write, iclass 37, count 0 2006.258.00:34:04.59#ibcon#wrote, iclass 37, count 0 2006.258.00:34:04.59#ibcon#about to read 3, iclass 37, count 0 2006.258.00:34:04.61#ibcon#read 3, iclass 37, count 0 2006.258.00:34:04.61#ibcon#about to read 4, iclass 37, count 0 2006.258.00:34:04.61#ibcon#read 4, iclass 37, count 0 2006.258.00:34:04.61#ibcon#about to read 5, iclass 37, count 0 2006.258.00:34:04.61#ibcon#read 5, iclass 37, count 0 2006.258.00:34:04.61#ibcon#about to read 6, iclass 37, count 0 2006.258.00:34:04.61#ibcon#read 6, iclass 37, count 0 2006.258.00:34:04.61#ibcon#end of sib2, iclass 37, count 0 2006.258.00:34:04.61#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:34:04.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:34:04.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:34:04.61#ibcon#*before write, iclass 37, count 0 2006.258.00:34:04.61#ibcon#enter sib2, iclass 37, count 0 2006.258.00:34:04.61#ibcon#flushed, iclass 37, count 0 2006.258.00:34:04.61#ibcon#about to write, iclass 37, count 0 2006.258.00:34:04.61#ibcon#wrote, iclass 37, count 0 2006.258.00:34:04.61#ibcon#about to read 3, iclass 37, count 0 2006.258.00:34:04.65#ibcon#read 3, iclass 37, count 0 2006.258.00:34:04.65#ibcon#about to read 4, iclass 37, count 0 2006.258.00:34:04.65#ibcon#read 4, iclass 37, count 0 2006.258.00:34:04.65#ibcon#about to read 5, iclass 37, count 0 2006.258.00:34:04.65#ibcon#read 5, iclass 37, count 0 2006.258.00:34:04.65#ibcon#about to read 6, iclass 37, count 0 2006.258.00:34:04.65#ibcon#read 6, iclass 37, count 0 2006.258.00:34:04.65#ibcon#end of sib2, iclass 37, count 0 2006.258.00:34:04.65#ibcon#*after write, iclass 37, count 0 2006.258.00:34:04.65#ibcon#*before return 0, iclass 37, count 0 2006.258.00:34:04.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:04.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:04.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:34:04.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:34:04.65$vck44/va=8,4 2006.258.00:34:04.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.258.00:34:04.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.258.00:34:04.65#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:04.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:04.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:04.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:04.71#ibcon#enter wrdev, iclass 39, count 2 2006.258.00:34:04.71#ibcon#first serial, iclass 39, count 2 2006.258.00:34:04.71#ibcon#enter sib2, iclass 39, count 2 2006.258.00:34:04.71#ibcon#flushed, iclass 39, count 2 2006.258.00:34:04.71#ibcon#about to write, iclass 39, count 2 2006.258.00:34:04.71#ibcon#wrote, iclass 39, count 2 2006.258.00:34:04.71#ibcon#about to read 3, iclass 39, count 2 2006.258.00:34:04.73#ibcon#read 3, iclass 39, count 2 2006.258.00:34:04.73#ibcon#about to read 4, iclass 39, count 2 2006.258.00:34:04.73#ibcon#read 4, iclass 39, count 2 2006.258.00:34:04.73#ibcon#about to read 5, iclass 39, count 2 2006.258.00:34:04.73#ibcon#read 5, iclass 39, count 2 2006.258.00:34:04.73#ibcon#about to read 6, iclass 39, count 2 2006.258.00:34:04.73#ibcon#read 6, iclass 39, count 2 2006.258.00:34:04.73#ibcon#end of sib2, iclass 39, count 2 2006.258.00:34:04.73#ibcon#*mode == 0, iclass 39, count 2 2006.258.00:34:04.73#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.258.00:34:04.73#ibcon#[25=AT08-04\r\n] 2006.258.00:34:04.73#ibcon#*before write, iclass 39, count 2 2006.258.00:34:04.73#ibcon#enter sib2, iclass 39, count 2 2006.258.00:34:04.73#ibcon#flushed, iclass 39, count 2 2006.258.00:34:04.73#ibcon#about to write, iclass 39, count 2 2006.258.00:34:04.73#ibcon#wrote, iclass 39, count 2 2006.258.00:34:04.73#ibcon#about to read 3, iclass 39, count 2 2006.258.00:34:04.76#ibcon#read 3, iclass 39, count 2 2006.258.00:34:04.76#ibcon#about to read 4, iclass 39, count 2 2006.258.00:34:04.76#ibcon#read 4, iclass 39, count 2 2006.258.00:34:04.76#ibcon#about to read 5, iclass 39, count 2 2006.258.00:34:04.76#ibcon#read 5, iclass 39, count 2 2006.258.00:34:04.76#ibcon#about to read 6, iclass 39, count 2 2006.258.00:34:04.76#ibcon#read 6, iclass 39, count 2 2006.258.00:34:04.76#ibcon#end of sib2, iclass 39, count 2 2006.258.00:34:04.76#ibcon#*after write, iclass 39, count 2 2006.258.00:34:04.76#ibcon#*before return 0, iclass 39, count 2 2006.258.00:34:04.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:04.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:04.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.258.00:34:04.76#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:04.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:04.88#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:04.88#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:04.88#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:34:04.88#ibcon#first serial, iclass 39, count 0 2006.258.00:34:04.88#ibcon#enter sib2, iclass 39, count 0 2006.258.00:34:04.88#ibcon#flushed, iclass 39, count 0 2006.258.00:34:04.88#ibcon#about to write, iclass 39, count 0 2006.258.00:34:04.88#ibcon#wrote, iclass 39, count 0 2006.258.00:34:04.88#ibcon#about to read 3, iclass 39, count 0 2006.258.00:34:04.90#ibcon#read 3, iclass 39, count 0 2006.258.00:34:04.90#ibcon#about to read 4, iclass 39, count 0 2006.258.00:34:04.90#ibcon#read 4, iclass 39, count 0 2006.258.00:34:04.90#ibcon#about to read 5, iclass 39, count 0 2006.258.00:34:04.90#ibcon#read 5, iclass 39, count 0 2006.258.00:34:04.90#ibcon#about to read 6, iclass 39, count 0 2006.258.00:34:04.90#ibcon#read 6, iclass 39, count 0 2006.258.00:34:04.90#ibcon#end of sib2, iclass 39, count 0 2006.258.00:34:04.90#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:34:04.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:34:04.90#ibcon#[25=USB\r\n] 2006.258.00:34:04.90#ibcon#*before write, iclass 39, count 0 2006.258.00:34:04.90#ibcon#enter sib2, iclass 39, count 0 2006.258.00:34:04.90#ibcon#flushed, iclass 39, count 0 2006.258.00:34:04.90#ibcon#about to write, iclass 39, count 0 2006.258.00:34:04.90#ibcon#wrote, iclass 39, count 0 2006.258.00:34:04.90#ibcon#about to read 3, iclass 39, count 0 2006.258.00:34:04.93#ibcon#read 3, iclass 39, count 0 2006.258.00:34:04.93#ibcon#about to read 4, iclass 39, count 0 2006.258.00:34:04.93#ibcon#read 4, iclass 39, count 0 2006.258.00:34:04.93#ibcon#about to read 5, iclass 39, count 0 2006.258.00:34:04.93#ibcon#read 5, iclass 39, count 0 2006.258.00:34:04.93#ibcon#about to read 6, iclass 39, count 0 2006.258.00:34:04.93#ibcon#read 6, iclass 39, count 0 2006.258.00:34:04.93#ibcon#end of sib2, iclass 39, count 0 2006.258.00:34:04.93#ibcon#*after write, iclass 39, count 0 2006.258.00:34:04.93#ibcon#*before return 0, iclass 39, count 0 2006.258.00:34:04.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:04.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:04.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:34:04.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:34:04.93$vck44/vblo=1,629.99 2006.258.00:34:04.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.00:34:04.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.00:34:04.93#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:04.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:04.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:04.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:04.93#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:34:04.93#ibcon#first serial, iclass 3, count 0 2006.258.00:34:04.93#ibcon#enter sib2, iclass 3, count 0 2006.258.00:34:04.93#ibcon#flushed, iclass 3, count 0 2006.258.00:34:04.93#ibcon#about to write, iclass 3, count 0 2006.258.00:34:04.93#ibcon#wrote, iclass 3, count 0 2006.258.00:34:04.93#ibcon#about to read 3, iclass 3, count 0 2006.258.00:34:04.95#ibcon#read 3, iclass 3, count 0 2006.258.00:34:04.95#ibcon#about to read 4, iclass 3, count 0 2006.258.00:34:04.95#ibcon#read 4, iclass 3, count 0 2006.258.00:34:04.95#ibcon#about to read 5, iclass 3, count 0 2006.258.00:34:04.95#ibcon#read 5, iclass 3, count 0 2006.258.00:34:04.95#ibcon#about to read 6, iclass 3, count 0 2006.258.00:34:04.95#ibcon#read 6, iclass 3, count 0 2006.258.00:34:04.95#ibcon#end of sib2, iclass 3, count 0 2006.258.00:34:04.95#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:34:04.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:34:04.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:34:04.95#ibcon#*before write, iclass 3, count 0 2006.258.00:34:04.95#ibcon#enter sib2, iclass 3, count 0 2006.258.00:34:04.95#ibcon#flushed, iclass 3, count 0 2006.258.00:34:04.95#ibcon#about to write, iclass 3, count 0 2006.258.00:34:04.95#ibcon#wrote, iclass 3, count 0 2006.258.00:34:04.95#ibcon#about to read 3, iclass 3, count 0 2006.258.00:34:04.99#ibcon#read 3, iclass 3, count 0 2006.258.00:34:04.99#ibcon#about to read 4, iclass 3, count 0 2006.258.00:34:04.99#ibcon#read 4, iclass 3, count 0 2006.258.00:34:04.99#ibcon#about to read 5, iclass 3, count 0 2006.258.00:34:04.99#ibcon#read 5, iclass 3, count 0 2006.258.00:34:04.99#ibcon#about to read 6, iclass 3, count 0 2006.258.00:34:04.99#ibcon#read 6, iclass 3, count 0 2006.258.00:34:04.99#ibcon#end of sib2, iclass 3, count 0 2006.258.00:34:04.99#ibcon#*after write, iclass 3, count 0 2006.258.00:34:04.99#ibcon#*before return 0, iclass 3, count 0 2006.258.00:34:04.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:04.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:04.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:34:04.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:34:04.99$vck44/vb=1,4 2006.258.00:34:04.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.258.00:34:04.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.258.00:34:04.99#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:04.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:34:04.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:34:04.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:34:04.99#ibcon#enter wrdev, iclass 5, count 2 2006.258.00:34:04.99#ibcon#first serial, iclass 5, count 2 2006.258.00:34:04.99#ibcon#enter sib2, iclass 5, count 2 2006.258.00:34:04.99#ibcon#flushed, iclass 5, count 2 2006.258.00:34:04.99#ibcon#about to write, iclass 5, count 2 2006.258.00:34:04.99#ibcon#wrote, iclass 5, count 2 2006.258.00:34:04.99#ibcon#about to read 3, iclass 5, count 2 2006.258.00:34:05.01#ibcon#read 3, iclass 5, count 2 2006.258.00:34:05.01#ibcon#about to read 4, iclass 5, count 2 2006.258.00:34:05.01#ibcon#read 4, iclass 5, count 2 2006.258.00:34:05.01#ibcon#about to read 5, iclass 5, count 2 2006.258.00:34:05.01#ibcon#read 5, iclass 5, count 2 2006.258.00:34:05.01#ibcon#about to read 6, iclass 5, count 2 2006.258.00:34:05.01#ibcon#read 6, iclass 5, count 2 2006.258.00:34:05.01#ibcon#end of sib2, iclass 5, count 2 2006.258.00:34:05.01#ibcon#*mode == 0, iclass 5, count 2 2006.258.00:34:05.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.258.00:34:05.01#ibcon#[27=AT01-04\r\n] 2006.258.00:34:05.01#ibcon#*before write, iclass 5, count 2 2006.258.00:34:05.01#ibcon#enter sib2, iclass 5, count 2 2006.258.00:34:05.01#ibcon#flushed, iclass 5, count 2 2006.258.00:34:05.01#ibcon#about to write, iclass 5, count 2 2006.258.00:34:05.01#ibcon#wrote, iclass 5, count 2 2006.258.00:34:05.01#ibcon#about to read 3, iclass 5, count 2 2006.258.00:34:05.04#ibcon#read 3, iclass 5, count 2 2006.258.00:34:05.04#ibcon#about to read 4, iclass 5, count 2 2006.258.00:34:05.04#ibcon#read 4, iclass 5, count 2 2006.258.00:34:05.04#ibcon#about to read 5, iclass 5, count 2 2006.258.00:34:05.04#ibcon#read 5, iclass 5, count 2 2006.258.00:34:05.04#ibcon#about to read 6, iclass 5, count 2 2006.258.00:34:05.04#ibcon#read 6, iclass 5, count 2 2006.258.00:34:05.04#ibcon#end of sib2, iclass 5, count 2 2006.258.00:34:05.04#ibcon#*after write, iclass 5, count 2 2006.258.00:34:05.04#ibcon#*before return 0, iclass 5, count 2 2006.258.00:34:05.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:34:05.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:34:05.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.258.00:34:05.04#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:05.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:34:05.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:34:05.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:34:05.16#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:34:05.16#ibcon#first serial, iclass 5, count 0 2006.258.00:34:05.16#ibcon#enter sib2, iclass 5, count 0 2006.258.00:34:05.16#ibcon#flushed, iclass 5, count 0 2006.258.00:34:05.16#ibcon#about to write, iclass 5, count 0 2006.258.00:34:05.16#ibcon#wrote, iclass 5, count 0 2006.258.00:34:05.16#ibcon#about to read 3, iclass 5, count 0 2006.258.00:34:05.18#ibcon#read 3, iclass 5, count 0 2006.258.00:34:05.18#ibcon#about to read 4, iclass 5, count 0 2006.258.00:34:05.18#ibcon#read 4, iclass 5, count 0 2006.258.00:34:05.18#ibcon#about to read 5, iclass 5, count 0 2006.258.00:34:05.18#ibcon#read 5, iclass 5, count 0 2006.258.00:34:05.18#ibcon#about to read 6, iclass 5, count 0 2006.258.00:34:05.18#ibcon#read 6, iclass 5, count 0 2006.258.00:34:05.18#ibcon#end of sib2, iclass 5, count 0 2006.258.00:34:05.18#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:34:05.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:34:05.18#ibcon#[27=USB\r\n] 2006.258.00:34:05.18#ibcon#*before write, iclass 5, count 0 2006.258.00:34:05.18#ibcon#enter sib2, iclass 5, count 0 2006.258.00:34:05.18#ibcon#flushed, iclass 5, count 0 2006.258.00:34:05.18#ibcon#about to write, iclass 5, count 0 2006.258.00:34:05.18#ibcon#wrote, iclass 5, count 0 2006.258.00:34:05.18#ibcon#about to read 3, iclass 5, count 0 2006.258.00:34:05.21#ibcon#read 3, iclass 5, count 0 2006.258.00:34:05.21#ibcon#about to read 4, iclass 5, count 0 2006.258.00:34:05.21#ibcon#read 4, iclass 5, count 0 2006.258.00:34:05.21#ibcon#about to read 5, iclass 5, count 0 2006.258.00:34:05.21#ibcon#read 5, iclass 5, count 0 2006.258.00:34:05.21#ibcon#about to read 6, iclass 5, count 0 2006.258.00:34:05.21#ibcon#read 6, iclass 5, count 0 2006.258.00:34:05.21#ibcon#end of sib2, iclass 5, count 0 2006.258.00:34:05.21#ibcon#*after write, iclass 5, count 0 2006.258.00:34:05.21#ibcon#*before return 0, iclass 5, count 0 2006.258.00:34:05.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:34:05.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:34:05.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:34:05.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:34:05.21$vck44/vblo=2,634.99 2006.258.00:34:05.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.00:34:05.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.00:34:05.21#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:05.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:05.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:05.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:05.21#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:34:05.21#ibcon#first serial, iclass 7, count 0 2006.258.00:34:05.21#ibcon#enter sib2, iclass 7, count 0 2006.258.00:34:05.21#ibcon#flushed, iclass 7, count 0 2006.258.00:34:05.21#ibcon#about to write, iclass 7, count 0 2006.258.00:34:05.21#ibcon#wrote, iclass 7, count 0 2006.258.00:34:05.21#ibcon#about to read 3, iclass 7, count 0 2006.258.00:34:05.23#ibcon#read 3, iclass 7, count 0 2006.258.00:34:05.23#ibcon#about to read 4, iclass 7, count 0 2006.258.00:34:05.23#ibcon#read 4, iclass 7, count 0 2006.258.00:34:05.23#ibcon#about to read 5, iclass 7, count 0 2006.258.00:34:05.23#ibcon#read 5, iclass 7, count 0 2006.258.00:34:05.23#ibcon#about to read 6, iclass 7, count 0 2006.258.00:34:05.23#ibcon#read 6, iclass 7, count 0 2006.258.00:34:05.23#ibcon#end of sib2, iclass 7, count 0 2006.258.00:34:05.23#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:34:05.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:34:05.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:34:05.23#ibcon#*before write, iclass 7, count 0 2006.258.00:34:05.23#ibcon#enter sib2, iclass 7, count 0 2006.258.00:34:05.23#ibcon#flushed, iclass 7, count 0 2006.258.00:34:05.23#ibcon#about to write, iclass 7, count 0 2006.258.00:34:05.23#ibcon#wrote, iclass 7, count 0 2006.258.00:34:05.23#ibcon#about to read 3, iclass 7, count 0 2006.258.00:34:05.27#ibcon#read 3, iclass 7, count 0 2006.258.00:34:05.27#ibcon#about to read 4, iclass 7, count 0 2006.258.00:34:05.27#ibcon#read 4, iclass 7, count 0 2006.258.00:34:05.27#ibcon#about to read 5, iclass 7, count 0 2006.258.00:34:05.27#ibcon#read 5, iclass 7, count 0 2006.258.00:34:05.27#ibcon#about to read 6, iclass 7, count 0 2006.258.00:34:05.27#ibcon#read 6, iclass 7, count 0 2006.258.00:34:05.27#ibcon#end of sib2, iclass 7, count 0 2006.258.00:34:05.27#ibcon#*after write, iclass 7, count 0 2006.258.00:34:05.27#ibcon#*before return 0, iclass 7, count 0 2006.258.00:34:05.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:05.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:34:05.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:34:05.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:34:05.27$vck44/vb=2,5 2006.258.00:34:05.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.00:34:05.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.00:34:05.27#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:05.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:05.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:05.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:05.33#ibcon#enter wrdev, iclass 11, count 2 2006.258.00:34:05.33#ibcon#first serial, iclass 11, count 2 2006.258.00:34:05.33#ibcon#enter sib2, iclass 11, count 2 2006.258.00:34:05.33#ibcon#flushed, iclass 11, count 2 2006.258.00:34:05.33#ibcon#about to write, iclass 11, count 2 2006.258.00:34:05.33#ibcon#wrote, iclass 11, count 2 2006.258.00:34:05.33#ibcon#about to read 3, iclass 11, count 2 2006.258.00:34:05.35#ibcon#read 3, iclass 11, count 2 2006.258.00:34:05.35#ibcon#about to read 4, iclass 11, count 2 2006.258.00:34:05.35#ibcon#read 4, iclass 11, count 2 2006.258.00:34:05.35#ibcon#about to read 5, iclass 11, count 2 2006.258.00:34:05.35#ibcon#read 5, iclass 11, count 2 2006.258.00:34:05.35#ibcon#about to read 6, iclass 11, count 2 2006.258.00:34:05.35#ibcon#read 6, iclass 11, count 2 2006.258.00:34:05.35#ibcon#end of sib2, iclass 11, count 2 2006.258.00:34:05.35#ibcon#*mode == 0, iclass 11, count 2 2006.258.00:34:05.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.00:34:05.35#ibcon#[27=AT02-05\r\n] 2006.258.00:34:05.35#ibcon#*before write, iclass 11, count 2 2006.258.00:34:05.35#ibcon#enter sib2, iclass 11, count 2 2006.258.00:34:05.35#ibcon#flushed, iclass 11, count 2 2006.258.00:34:05.35#ibcon#about to write, iclass 11, count 2 2006.258.00:34:05.35#ibcon#wrote, iclass 11, count 2 2006.258.00:34:05.35#ibcon#about to read 3, iclass 11, count 2 2006.258.00:34:05.38#abcon#<5=/02 2.0 7.3 22.19 771016.1\r\n> 2006.258.00:34:05.38#ibcon#read 3, iclass 11, count 2 2006.258.00:34:05.38#ibcon#about to read 4, iclass 11, count 2 2006.258.00:34:05.38#ibcon#read 4, iclass 11, count 2 2006.258.00:34:05.38#ibcon#about to read 5, iclass 11, count 2 2006.258.00:34:05.38#ibcon#read 5, iclass 11, count 2 2006.258.00:34:05.38#ibcon#about to read 6, iclass 11, count 2 2006.258.00:34:05.38#ibcon#read 6, iclass 11, count 2 2006.258.00:34:05.38#ibcon#end of sib2, iclass 11, count 2 2006.258.00:34:05.38#ibcon#*after write, iclass 11, count 2 2006.258.00:34:05.38#ibcon#*before return 0, iclass 11, count 2 2006.258.00:34:05.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:05.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:34:05.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.00:34:05.38#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:05.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:05.40#abcon#{5=INTERFACE CLEAR} 2006.258.00:34:05.46#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:34:05.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:05.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:05.50#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:34:05.50#ibcon#first serial, iclass 11, count 0 2006.258.00:34:05.50#ibcon#enter sib2, iclass 11, count 0 2006.258.00:34:05.50#ibcon#flushed, iclass 11, count 0 2006.258.00:34:05.50#ibcon#about to write, iclass 11, count 0 2006.258.00:34:05.50#ibcon#wrote, iclass 11, count 0 2006.258.00:34:05.50#ibcon#about to read 3, iclass 11, count 0 2006.258.00:34:05.52#ibcon#read 3, iclass 11, count 0 2006.258.00:34:05.52#ibcon#about to read 4, iclass 11, count 0 2006.258.00:34:05.52#ibcon#read 4, iclass 11, count 0 2006.258.00:34:05.52#ibcon#about to read 5, iclass 11, count 0 2006.258.00:34:05.52#ibcon#read 5, iclass 11, count 0 2006.258.00:34:05.52#ibcon#about to read 6, iclass 11, count 0 2006.258.00:34:05.52#ibcon#read 6, iclass 11, count 0 2006.258.00:34:05.52#ibcon#end of sib2, iclass 11, count 0 2006.258.00:34:05.52#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:34:05.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:34:05.52#ibcon#[27=USB\r\n] 2006.258.00:34:05.52#ibcon#*before write, iclass 11, count 0 2006.258.00:34:05.52#ibcon#enter sib2, iclass 11, count 0 2006.258.00:34:05.52#ibcon#flushed, iclass 11, count 0 2006.258.00:34:05.52#ibcon#about to write, iclass 11, count 0 2006.258.00:34:05.52#ibcon#wrote, iclass 11, count 0 2006.258.00:34:05.52#ibcon#about to read 3, iclass 11, count 0 2006.258.00:34:05.55#ibcon#read 3, iclass 11, count 0 2006.258.00:34:05.55#ibcon#about to read 4, iclass 11, count 0 2006.258.00:34:05.55#ibcon#read 4, iclass 11, count 0 2006.258.00:34:05.55#ibcon#about to read 5, iclass 11, count 0 2006.258.00:34:05.55#ibcon#read 5, iclass 11, count 0 2006.258.00:34:05.55#ibcon#about to read 6, iclass 11, count 0 2006.258.00:34:05.55#ibcon#read 6, iclass 11, count 0 2006.258.00:34:05.55#ibcon#end of sib2, iclass 11, count 0 2006.258.00:34:05.55#ibcon#*after write, iclass 11, count 0 2006.258.00:34:05.55#ibcon#*before return 0, iclass 11, count 0 2006.258.00:34:05.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:05.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:34:05.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:34:05.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:34:05.55$vck44/vblo=3,649.99 2006.258.00:34:05.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.258.00:34:05.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.258.00:34:05.55#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:05.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:05.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:05.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:05.55#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:34:05.55#ibcon#first serial, iclass 17, count 0 2006.258.00:34:05.55#ibcon#enter sib2, iclass 17, count 0 2006.258.00:34:05.55#ibcon#flushed, iclass 17, count 0 2006.258.00:34:05.55#ibcon#about to write, iclass 17, count 0 2006.258.00:34:05.57#ibcon#wrote, iclass 17, count 0 2006.258.00:34:05.57#ibcon#about to read 3, iclass 17, count 0 2006.258.00:34:05.59#ibcon#read 3, iclass 17, count 0 2006.258.00:34:05.59#ibcon#about to read 4, iclass 17, count 0 2006.258.00:34:05.59#ibcon#read 4, iclass 17, count 0 2006.258.00:34:05.59#ibcon#about to read 5, iclass 17, count 0 2006.258.00:34:05.59#ibcon#read 5, iclass 17, count 0 2006.258.00:34:05.59#ibcon#about to read 6, iclass 17, count 0 2006.258.00:34:05.59#ibcon#read 6, iclass 17, count 0 2006.258.00:34:05.59#ibcon#end of sib2, iclass 17, count 0 2006.258.00:34:05.59#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:34:05.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:34:05.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:34:05.59#ibcon#*before write, iclass 17, count 0 2006.258.00:34:05.59#ibcon#enter sib2, iclass 17, count 0 2006.258.00:34:05.59#ibcon#flushed, iclass 17, count 0 2006.258.00:34:05.59#ibcon#about to write, iclass 17, count 0 2006.258.00:34:05.59#ibcon#wrote, iclass 17, count 0 2006.258.00:34:05.59#ibcon#about to read 3, iclass 17, count 0 2006.258.00:34:05.63#ibcon#read 3, iclass 17, count 0 2006.258.00:34:05.63#ibcon#about to read 4, iclass 17, count 0 2006.258.00:34:05.63#ibcon#read 4, iclass 17, count 0 2006.258.00:34:05.63#ibcon#about to read 5, iclass 17, count 0 2006.258.00:34:05.63#ibcon#read 5, iclass 17, count 0 2006.258.00:34:05.63#ibcon#about to read 6, iclass 17, count 0 2006.258.00:34:05.63#ibcon#read 6, iclass 17, count 0 2006.258.00:34:05.63#ibcon#end of sib2, iclass 17, count 0 2006.258.00:34:05.63#ibcon#*after write, iclass 17, count 0 2006.258.00:34:05.63#ibcon#*before return 0, iclass 17, count 0 2006.258.00:34:05.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:05.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:34:05.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:34:05.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:34:05.63$vck44/vb=3,4 2006.258.00:34:05.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.258.00:34:05.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.258.00:34:05.63#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:05.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:05.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:05.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:05.67#ibcon#enter wrdev, iclass 19, count 2 2006.258.00:34:05.67#ibcon#first serial, iclass 19, count 2 2006.258.00:34:05.67#ibcon#enter sib2, iclass 19, count 2 2006.258.00:34:05.67#ibcon#flushed, iclass 19, count 2 2006.258.00:34:05.67#ibcon#about to write, iclass 19, count 2 2006.258.00:34:05.67#ibcon#wrote, iclass 19, count 2 2006.258.00:34:05.67#ibcon#about to read 3, iclass 19, count 2 2006.258.00:34:05.69#ibcon#read 3, iclass 19, count 2 2006.258.00:34:05.69#ibcon#about to read 4, iclass 19, count 2 2006.258.00:34:05.69#ibcon#read 4, iclass 19, count 2 2006.258.00:34:05.69#ibcon#about to read 5, iclass 19, count 2 2006.258.00:34:05.69#ibcon#read 5, iclass 19, count 2 2006.258.00:34:05.69#ibcon#about to read 6, iclass 19, count 2 2006.258.00:34:05.69#ibcon#read 6, iclass 19, count 2 2006.258.00:34:05.69#ibcon#end of sib2, iclass 19, count 2 2006.258.00:34:05.69#ibcon#*mode == 0, iclass 19, count 2 2006.258.00:34:05.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.258.00:34:05.69#ibcon#[27=AT03-04\r\n] 2006.258.00:34:05.69#ibcon#*before write, iclass 19, count 2 2006.258.00:34:05.69#ibcon#enter sib2, iclass 19, count 2 2006.258.00:34:05.69#ibcon#flushed, iclass 19, count 2 2006.258.00:34:05.69#ibcon#about to write, iclass 19, count 2 2006.258.00:34:05.69#ibcon#wrote, iclass 19, count 2 2006.258.00:34:05.69#ibcon#about to read 3, iclass 19, count 2 2006.258.00:34:05.72#ibcon#read 3, iclass 19, count 2 2006.258.00:34:05.72#ibcon#about to read 4, iclass 19, count 2 2006.258.00:34:05.72#ibcon#read 4, iclass 19, count 2 2006.258.00:34:05.72#ibcon#about to read 5, iclass 19, count 2 2006.258.00:34:05.72#ibcon#read 5, iclass 19, count 2 2006.258.00:34:05.72#ibcon#about to read 6, iclass 19, count 2 2006.258.00:34:05.72#ibcon#read 6, iclass 19, count 2 2006.258.00:34:05.72#ibcon#end of sib2, iclass 19, count 2 2006.258.00:34:05.72#ibcon#*after write, iclass 19, count 2 2006.258.00:34:05.72#ibcon#*before return 0, iclass 19, count 2 2006.258.00:34:05.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:05.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:34:05.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.258.00:34:05.72#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:05.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:05.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:05.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:05.84#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:34:05.84#ibcon#first serial, iclass 19, count 0 2006.258.00:34:05.84#ibcon#enter sib2, iclass 19, count 0 2006.258.00:34:05.84#ibcon#flushed, iclass 19, count 0 2006.258.00:34:05.84#ibcon#about to write, iclass 19, count 0 2006.258.00:34:05.84#ibcon#wrote, iclass 19, count 0 2006.258.00:34:05.84#ibcon#about to read 3, iclass 19, count 0 2006.258.00:34:05.86#ibcon#read 3, iclass 19, count 0 2006.258.00:34:05.86#ibcon#about to read 4, iclass 19, count 0 2006.258.00:34:05.86#ibcon#read 4, iclass 19, count 0 2006.258.00:34:05.86#ibcon#about to read 5, iclass 19, count 0 2006.258.00:34:05.86#ibcon#read 5, iclass 19, count 0 2006.258.00:34:05.86#ibcon#about to read 6, iclass 19, count 0 2006.258.00:34:05.86#ibcon#read 6, iclass 19, count 0 2006.258.00:34:05.86#ibcon#end of sib2, iclass 19, count 0 2006.258.00:34:05.86#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:34:05.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:34:05.86#ibcon#[27=USB\r\n] 2006.258.00:34:05.86#ibcon#*before write, iclass 19, count 0 2006.258.00:34:05.86#ibcon#enter sib2, iclass 19, count 0 2006.258.00:34:05.86#ibcon#flushed, iclass 19, count 0 2006.258.00:34:05.86#ibcon#about to write, iclass 19, count 0 2006.258.00:34:05.86#ibcon#wrote, iclass 19, count 0 2006.258.00:34:05.86#ibcon#about to read 3, iclass 19, count 0 2006.258.00:34:05.89#ibcon#read 3, iclass 19, count 0 2006.258.00:34:05.89#ibcon#about to read 4, iclass 19, count 0 2006.258.00:34:05.89#ibcon#read 4, iclass 19, count 0 2006.258.00:34:05.89#ibcon#about to read 5, iclass 19, count 0 2006.258.00:34:05.89#ibcon#read 5, iclass 19, count 0 2006.258.00:34:05.89#ibcon#about to read 6, iclass 19, count 0 2006.258.00:34:05.89#ibcon#read 6, iclass 19, count 0 2006.258.00:34:05.89#ibcon#end of sib2, iclass 19, count 0 2006.258.00:34:05.89#ibcon#*after write, iclass 19, count 0 2006.258.00:34:05.89#ibcon#*before return 0, iclass 19, count 0 2006.258.00:34:05.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:05.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:34:05.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:34:05.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:34:05.89$vck44/vblo=4,679.99 2006.258.00:34:05.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.258.00:34:05.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.258.00:34:05.89#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:05.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:05.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:05.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:05.89#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:34:05.89#ibcon#first serial, iclass 21, count 0 2006.258.00:34:05.89#ibcon#enter sib2, iclass 21, count 0 2006.258.00:34:05.89#ibcon#flushed, iclass 21, count 0 2006.258.00:34:05.89#ibcon#about to write, iclass 21, count 0 2006.258.00:34:05.89#ibcon#wrote, iclass 21, count 0 2006.258.00:34:05.89#ibcon#about to read 3, iclass 21, count 0 2006.258.00:34:05.91#ibcon#read 3, iclass 21, count 0 2006.258.00:34:05.91#ibcon#about to read 4, iclass 21, count 0 2006.258.00:34:05.91#ibcon#read 4, iclass 21, count 0 2006.258.00:34:05.91#ibcon#about to read 5, iclass 21, count 0 2006.258.00:34:05.91#ibcon#read 5, iclass 21, count 0 2006.258.00:34:05.91#ibcon#about to read 6, iclass 21, count 0 2006.258.00:34:05.91#ibcon#read 6, iclass 21, count 0 2006.258.00:34:05.91#ibcon#end of sib2, iclass 21, count 0 2006.258.00:34:05.91#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:34:05.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:34:05.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:34:05.91#ibcon#*before write, iclass 21, count 0 2006.258.00:34:05.91#ibcon#enter sib2, iclass 21, count 0 2006.258.00:34:05.91#ibcon#flushed, iclass 21, count 0 2006.258.00:34:05.91#ibcon#about to write, iclass 21, count 0 2006.258.00:34:05.91#ibcon#wrote, iclass 21, count 0 2006.258.00:34:05.91#ibcon#about to read 3, iclass 21, count 0 2006.258.00:34:05.95#ibcon#read 3, iclass 21, count 0 2006.258.00:34:05.95#ibcon#about to read 4, iclass 21, count 0 2006.258.00:34:05.95#ibcon#read 4, iclass 21, count 0 2006.258.00:34:05.95#ibcon#about to read 5, iclass 21, count 0 2006.258.00:34:05.95#ibcon#read 5, iclass 21, count 0 2006.258.00:34:05.95#ibcon#about to read 6, iclass 21, count 0 2006.258.00:34:05.95#ibcon#read 6, iclass 21, count 0 2006.258.00:34:05.95#ibcon#end of sib2, iclass 21, count 0 2006.258.00:34:05.95#ibcon#*after write, iclass 21, count 0 2006.258.00:34:05.95#ibcon#*before return 0, iclass 21, count 0 2006.258.00:34:05.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:05.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:34:05.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:34:05.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:34:05.95$vck44/vb=4,5 2006.258.00:34:05.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.258.00:34:05.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.258.00:34:05.95#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:05.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:06.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:06.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:06.01#ibcon#enter wrdev, iclass 23, count 2 2006.258.00:34:06.01#ibcon#first serial, iclass 23, count 2 2006.258.00:34:06.01#ibcon#enter sib2, iclass 23, count 2 2006.258.00:34:06.01#ibcon#flushed, iclass 23, count 2 2006.258.00:34:06.01#ibcon#about to write, iclass 23, count 2 2006.258.00:34:06.01#ibcon#wrote, iclass 23, count 2 2006.258.00:34:06.01#ibcon#about to read 3, iclass 23, count 2 2006.258.00:34:06.03#ibcon#read 3, iclass 23, count 2 2006.258.00:34:06.03#ibcon#about to read 4, iclass 23, count 2 2006.258.00:34:06.03#ibcon#read 4, iclass 23, count 2 2006.258.00:34:06.03#ibcon#about to read 5, iclass 23, count 2 2006.258.00:34:06.03#ibcon#read 5, iclass 23, count 2 2006.258.00:34:06.03#ibcon#about to read 6, iclass 23, count 2 2006.258.00:34:06.03#ibcon#read 6, iclass 23, count 2 2006.258.00:34:06.03#ibcon#end of sib2, iclass 23, count 2 2006.258.00:34:06.03#ibcon#*mode == 0, iclass 23, count 2 2006.258.00:34:06.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.258.00:34:06.03#ibcon#[27=AT04-05\r\n] 2006.258.00:34:06.03#ibcon#*before write, iclass 23, count 2 2006.258.00:34:06.03#ibcon#enter sib2, iclass 23, count 2 2006.258.00:34:06.03#ibcon#flushed, iclass 23, count 2 2006.258.00:34:06.03#ibcon#about to write, iclass 23, count 2 2006.258.00:34:06.03#ibcon#wrote, iclass 23, count 2 2006.258.00:34:06.03#ibcon#about to read 3, iclass 23, count 2 2006.258.00:34:06.06#ibcon#read 3, iclass 23, count 2 2006.258.00:34:06.06#ibcon#about to read 4, iclass 23, count 2 2006.258.00:34:06.06#ibcon#read 4, iclass 23, count 2 2006.258.00:34:06.06#ibcon#about to read 5, iclass 23, count 2 2006.258.00:34:06.06#ibcon#read 5, iclass 23, count 2 2006.258.00:34:06.06#ibcon#about to read 6, iclass 23, count 2 2006.258.00:34:06.06#ibcon#read 6, iclass 23, count 2 2006.258.00:34:06.06#ibcon#end of sib2, iclass 23, count 2 2006.258.00:34:06.06#ibcon#*after write, iclass 23, count 2 2006.258.00:34:06.06#ibcon#*before return 0, iclass 23, count 2 2006.258.00:34:06.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:06.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:34:06.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.258.00:34:06.06#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:06.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:06.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:06.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:06.18#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:34:06.18#ibcon#first serial, iclass 23, count 0 2006.258.00:34:06.18#ibcon#enter sib2, iclass 23, count 0 2006.258.00:34:06.18#ibcon#flushed, iclass 23, count 0 2006.258.00:34:06.18#ibcon#about to write, iclass 23, count 0 2006.258.00:34:06.18#ibcon#wrote, iclass 23, count 0 2006.258.00:34:06.18#ibcon#about to read 3, iclass 23, count 0 2006.258.00:34:06.20#ibcon#read 3, iclass 23, count 0 2006.258.00:34:06.20#ibcon#about to read 4, iclass 23, count 0 2006.258.00:34:06.20#ibcon#read 4, iclass 23, count 0 2006.258.00:34:06.20#ibcon#about to read 5, iclass 23, count 0 2006.258.00:34:06.20#ibcon#read 5, iclass 23, count 0 2006.258.00:34:06.20#ibcon#about to read 6, iclass 23, count 0 2006.258.00:34:06.20#ibcon#read 6, iclass 23, count 0 2006.258.00:34:06.20#ibcon#end of sib2, iclass 23, count 0 2006.258.00:34:06.20#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:34:06.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:34:06.20#ibcon#[27=USB\r\n] 2006.258.00:34:06.20#ibcon#*before write, iclass 23, count 0 2006.258.00:34:06.20#ibcon#enter sib2, iclass 23, count 0 2006.258.00:34:06.20#ibcon#flushed, iclass 23, count 0 2006.258.00:34:06.20#ibcon#about to write, iclass 23, count 0 2006.258.00:34:06.20#ibcon#wrote, iclass 23, count 0 2006.258.00:34:06.20#ibcon#about to read 3, iclass 23, count 0 2006.258.00:34:06.23#ibcon#read 3, iclass 23, count 0 2006.258.00:34:06.23#ibcon#about to read 4, iclass 23, count 0 2006.258.00:34:06.23#ibcon#read 4, iclass 23, count 0 2006.258.00:34:06.23#ibcon#about to read 5, iclass 23, count 0 2006.258.00:34:06.23#ibcon#read 5, iclass 23, count 0 2006.258.00:34:06.23#ibcon#about to read 6, iclass 23, count 0 2006.258.00:34:06.23#ibcon#read 6, iclass 23, count 0 2006.258.00:34:06.23#ibcon#end of sib2, iclass 23, count 0 2006.258.00:34:06.23#ibcon#*after write, iclass 23, count 0 2006.258.00:34:06.23#ibcon#*before return 0, iclass 23, count 0 2006.258.00:34:06.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:06.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:34:06.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:34:06.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:34:06.23$vck44/vblo=5,709.99 2006.258.00:34:06.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.00:34:06.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.00:34:06.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:06.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:06.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:06.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:06.23#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:34:06.23#ibcon#first serial, iclass 25, count 0 2006.258.00:34:06.23#ibcon#enter sib2, iclass 25, count 0 2006.258.00:34:06.23#ibcon#flushed, iclass 25, count 0 2006.258.00:34:06.23#ibcon#about to write, iclass 25, count 0 2006.258.00:34:06.23#ibcon#wrote, iclass 25, count 0 2006.258.00:34:06.23#ibcon#about to read 3, iclass 25, count 0 2006.258.00:34:06.25#ibcon#read 3, iclass 25, count 0 2006.258.00:34:06.25#ibcon#about to read 4, iclass 25, count 0 2006.258.00:34:06.25#ibcon#read 4, iclass 25, count 0 2006.258.00:34:06.25#ibcon#about to read 5, iclass 25, count 0 2006.258.00:34:06.25#ibcon#read 5, iclass 25, count 0 2006.258.00:34:06.25#ibcon#about to read 6, iclass 25, count 0 2006.258.00:34:06.25#ibcon#read 6, iclass 25, count 0 2006.258.00:34:06.25#ibcon#end of sib2, iclass 25, count 0 2006.258.00:34:06.25#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:34:06.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:34:06.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:34:06.25#ibcon#*before write, iclass 25, count 0 2006.258.00:34:06.25#ibcon#enter sib2, iclass 25, count 0 2006.258.00:34:06.25#ibcon#flushed, iclass 25, count 0 2006.258.00:34:06.25#ibcon#about to write, iclass 25, count 0 2006.258.00:34:06.25#ibcon#wrote, iclass 25, count 0 2006.258.00:34:06.25#ibcon#about to read 3, iclass 25, count 0 2006.258.00:34:06.29#ibcon#read 3, iclass 25, count 0 2006.258.00:34:06.29#ibcon#about to read 4, iclass 25, count 0 2006.258.00:34:06.29#ibcon#read 4, iclass 25, count 0 2006.258.00:34:06.29#ibcon#about to read 5, iclass 25, count 0 2006.258.00:34:06.29#ibcon#read 5, iclass 25, count 0 2006.258.00:34:06.29#ibcon#about to read 6, iclass 25, count 0 2006.258.00:34:06.29#ibcon#read 6, iclass 25, count 0 2006.258.00:34:06.29#ibcon#end of sib2, iclass 25, count 0 2006.258.00:34:06.29#ibcon#*after write, iclass 25, count 0 2006.258.00:34:06.29#ibcon#*before return 0, iclass 25, count 0 2006.258.00:34:06.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:06.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:34:06.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:34:06.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:34:06.29$vck44/vb=5,4 2006.258.00:34:06.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.258.00:34:06.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.258.00:34:06.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:06.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:06.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:06.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:06.35#ibcon#enter wrdev, iclass 27, count 2 2006.258.00:34:06.35#ibcon#first serial, iclass 27, count 2 2006.258.00:34:06.35#ibcon#enter sib2, iclass 27, count 2 2006.258.00:34:06.35#ibcon#flushed, iclass 27, count 2 2006.258.00:34:06.35#ibcon#about to write, iclass 27, count 2 2006.258.00:34:06.35#ibcon#wrote, iclass 27, count 2 2006.258.00:34:06.35#ibcon#about to read 3, iclass 27, count 2 2006.258.00:34:06.37#ibcon#read 3, iclass 27, count 2 2006.258.00:34:06.37#ibcon#about to read 4, iclass 27, count 2 2006.258.00:34:06.37#ibcon#read 4, iclass 27, count 2 2006.258.00:34:06.37#ibcon#about to read 5, iclass 27, count 2 2006.258.00:34:06.37#ibcon#read 5, iclass 27, count 2 2006.258.00:34:06.37#ibcon#about to read 6, iclass 27, count 2 2006.258.00:34:06.37#ibcon#read 6, iclass 27, count 2 2006.258.00:34:06.37#ibcon#end of sib2, iclass 27, count 2 2006.258.00:34:06.37#ibcon#*mode == 0, iclass 27, count 2 2006.258.00:34:06.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.258.00:34:06.37#ibcon#[27=AT05-04\r\n] 2006.258.00:34:06.37#ibcon#*before write, iclass 27, count 2 2006.258.00:34:06.37#ibcon#enter sib2, iclass 27, count 2 2006.258.00:34:06.37#ibcon#flushed, iclass 27, count 2 2006.258.00:34:06.37#ibcon#about to write, iclass 27, count 2 2006.258.00:34:06.37#ibcon#wrote, iclass 27, count 2 2006.258.00:34:06.37#ibcon#about to read 3, iclass 27, count 2 2006.258.00:34:06.40#ibcon#read 3, iclass 27, count 2 2006.258.00:34:06.40#ibcon#about to read 4, iclass 27, count 2 2006.258.00:34:06.40#ibcon#read 4, iclass 27, count 2 2006.258.00:34:06.40#ibcon#about to read 5, iclass 27, count 2 2006.258.00:34:06.40#ibcon#read 5, iclass 27, count 2 2006.258.00:34:06.40#ibcon#about to read 6, iclass 27, count 2 2006.258.00:34:06.40#ibcon#read 6, iclass 27, count 2 2006.258.00:34:06.40#ibcon#end of sib2, iclass 27, count 2 2006.258.00:34:06.40#ibcon#*after write, iclass 27, count 2 2006.258.00:34:06.40#ibcon#*before return 0, iclass 27, count 2 2006.258.00:34:06.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:06.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:34:06.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.258.00:34:06.40#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:06.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:06.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:06.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:06.52#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:34:06.52#ibcon#first serial, iclass 27, count 0 2006.258.00:34:06.52#ibcon#enter sib2, iclass 27, count 0 2006.258.00:34:06.52#ibcon#flushed, iclass 27, count 0 2006.258.00:34:06.52#ibcon#about to write, iclass 27, count 0 2006.258.00:34:06.52#ibcon#wrote, iclass 27, count 0 2006.258.00:34:06.52#ibcon#about to read 3, iclass 27, count 0 2006.258.00:34:06.54#ibcon#read 3, iclass 27, count 0 2006.258.00:34:06.54#ibcon#about to read 4, iclass 27, count 0 2006.258.00:34:06.54#ibcon#read 4, iclass 27, count 0 2006.258.00:34:06.54#ibcon#about to read 5, iclass 27, count 0 2006.258.00:34:06.54#ibcon#read 5, iclass 27, count 0 2006.258.00:34:06.54#ibcon#about to read 6, iclass 27, count 0 2006.258.00:34:06.54#ibcon#read 6, iclass 27, count 0 2006.258.00:34:06.54#ibcon#end of sib2, iclass 27, count 0 2006.258.00:34:06.54#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:34:06.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:34:06.54#ibcon#[27=USB\r\n] 2006.258.00:34:06.54#ibcon#*before write, iclass 27, count 0 2006.258.00:34:06.54#ibcon#enter sib2, iclass 27, count 0 2006.258.00:34:06.54#ibcon#flushed, iclass 27, count 0 2006.258.00:34:06.54#ibcon#about to write, iclass 27, count 0 2006.258.00:34:06.54#ibcon#wrote, iclass 27, count 0 2006.258.00:34:06.54#ibcon#about to read 3, iclass 27, count 0 2006.258.00:34:06.57#ibcon#read 3, iclass 27, count 0 2006.258.00:34:06.57#ibcon#about to read 4, iclass 27, count 0 2006.258.00:34:06.57#ibcon#read 4, iclass 27, count 0 2006.258.00:34:06.57#ibcon#about to read 5, iclass 27, count 0 2006.258.00:34:06.57#ibcon#read 5, iclass 27, count 0 2006.258.00:34:06.57#ibcon#about to read 6, iclass 27, count 0 2006.258.00:34:06.57#ibcon#read 6, iclass 27, count 0 2006.258.00:34:06.57#ibcon#end of sib2, iclass 27, count 0 2006.258.00:34:06.57#ibcon#*after write, iclass 27, count 0 2006.258.00:34:06.57#ibcon#*before return 0, iclass 27, count 0 2006.258.00:34:06.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:06.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:34:06.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:34:06.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:34:06.57$vck44/vblo=6,719.99 2006.258.00:34:06.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.00:34:06.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.00:34:06.57#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:06.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:06.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:06.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:06.57#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:34:06.57#ibcon#first serial, iclass 29, count 0 2006.258.00:34:06.57#ibcon#enter sib2, iclass 29, count 0 2006.258.00:34:06.57#ibcon#flushed, iclass 29, count 0 2006.258.00:34:06.57#ibcon#about to write, iclass 29, count 0 2006.258.00:34:06.57#ibcon#wrote, iclass 29, count 0 2006.258.00:34:06.57#ibcon#about to read 3, iclass 29, count 0 2006.258.00:34:06.59#ibcon#read 3, iclass 29, count 0 2006.258.00:34:06.59#ibcon#about to read 4, iclass 29, count 0 2006.258.00:34:06.59#ibcon#read 4, iclass 29, count 0 2006.258.00:34:06.59#ibcon#about to read 5, iclass 29, count 0 2006.258.00:34:06.59#ibcon#read 5, iclass 29, count 0 2006.258.00:34:06.59#ibcon#about to read 6, iclass 29, count 0 2006.258.00:34:06.59#ibcon#read 6, iclass 29, count 0 2006.258.00:34:06.59#ibcon#end of sib2, iclass 29, count 0 2006.258.00:34:06.59#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:34:06.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:34:06.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:34:06.59#ibcon#*before write, iclass 29, count 0 2006.258.00:34:06.59#ibcon#enter sib2, iclass 29, count 0 2006.258.00:34:06.59#ibcon#flushed, iclass 29, count 0 2006.258.00:34:06.59#ibcon#about to write, iclass 29, count 0 2006.258.00:34:06.59#ibcon#wrote, iclass 29, count 0 2006.258.00:34:06.59#ibcon#about to read 3, iclass 29, count 0 2006.258.00:34:06.63#ibcon#read 3, iclass 29, count 0 2006.258.00:34:06.63#ibcon#about to read 4, iclass 29, count 0 2006.258.00:34:06.63#ibcon#read 4, iclass 29, count 0 2006.258.00:34:06.63#ibcon#about to read 5, iclass 29, count 0 2006.258.00:34:06.63#ibcon#read 5, iclass 29, count 0 2006.258.00:34:06.63#ibcon#about to read 6, iclass 29, count 0 2006.258.00:34:06.63#ibcon#read 6, iclass 29, count 0 2006.258.00:34:06.63#ibcon#end of sib2, iclass 29, count 0 2006.258.00:34:06.63#ibcon#*after write, iclass 29, count 0 2006.258.00:34:06.63#ibcon#*before return 0, iclass 29, count 0 2006.258.00:34:06.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:06.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:34:06.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:34:06.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:34:06.63$vck44/vb=6,4 2006.258.00:34:06.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.00:34:06.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.00:34:06.63#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:06.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:06.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:06.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:06.69#ibcon#enter wrdev, iclass 31, count 2 2006.258.00:34:06.69#ibcon#first serial, iclass 31, count 2 2006.258.00:34:06.69#ibcon#enter sib2, iclass 31, count 2 2006.258.00:34:06.69#ibcon#flushed, iclass 31, count 2 2006.258.00:34:06.69#ibcon#about to write, iclass 31, count 2 2006.258.00:34:06.69#ibcon#wrote, iclass 31, count 2 2006.258.00:34:06.69#ibcon#about to read 3, iclass 31, count 2 2006.258.00:34:06.71#ibcon#read 3, iclass 31, count 2 2006.258.00:34:06.71#ibcon#about to read 4, iclass 31, count 2 2006.258.00:34:06.71#ibcon#read 4, iclass 31, count 2 2006.258.00:34:06.71#ibcon#about to read 5, iclass 31, count 2 2006.258.00:34:06.71#ibcon#read 5, iclass 31, count 2 2006.258.00:34:06.71#ibcon#about to read 6, iclass 31, count 2 2006.258.00:34:06.71#ibcon#read 6, iclass 31, count 2 2006.258.00:34:06.71#ibcon#end of sib2, iclass 31, count 2 2006.258.00:34:06.71#ibcon#*mode == 0, iclass 31, count 2 2006.258.00:34:06.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.00:34:06.71#ibcon#[27=AT06-04\r\n] 2006.258.00:34:06.71#ibcon#*before write, iclass 31, count 2 2006.258.00:34:06.71#ibcon#enter sib2, iclass 31, count 2 2006.258.00:34:06.71#ibcon#flushed, iclass 31, count 2 2006.258.00:34:06.71#ibcon#about to write, iclass 31, count 2 2006.258.00:34:06.71#ibcon#wrote, iclass 31, count 2 2006.258.00:34:06.71#ibcon#about to read 3, iclass 31, count 2 2006.258.00:34:06.74#ibcon#read 3, iclass 31, count 2 2006.258.00:34:06.74#ibcon#about to read 4, iclass 31, count 2 2006.258.00:34:06.74#ibcon#read 4, iclass 31, count 2 2006.258.00:34:06.74#ibcon#about to read 5, iclass 31, count 2 2006.258.00:34:06.74#ibcon#read 5, iclass 31, count 2 2006.258.00:34:06.74#ibcon#about to read 6, iclass 31, count 2 2006.258.00:34:06.74#ibcon#read 6, iclass 31, count 2 2006.258.00:34:06.74#ibcon#end of sib2, iclass 31, count 2 2006.258.00:34:06.74#ibcon#*after write, iclass 31, count 2 2006.258.00:34:06.74#ibcon#*before return 0, iclass 31, count 2 2006.258.00:34:06.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:06.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:34:06.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.00:34:06.74#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:06.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:06.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:06.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:06.86#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:34:06.86#ibcon#first serial, iclass 31, count 0 2006.258.00:34:06.86#ibcon#enter sib2, iclass 31, count 0 2006.258.00:34:06.86#ibcon#flushed, iclass 31, count 0 2006.258.00:34:06.86#ibcon#about to write, iclass 31, count 0 2006.258.00:34:06.86#ibcon#wrote, iclass 31, count 0 2006.258.00:34:06.86#ibcon#about to read 3, iclass 31, count 0 2006.258.00:34:06.88#ibcon#read 3, iclass 31, count 0 2006.258.00:34:06.88#ibcon#about to read 4, iclass 31, count 0 2006.258.00:34:06.88#ibcon#read 4, iclass 31, count 0 2006.258.00:34:06.88#ibcon#about to read 5, iclass 31, count 0 2006.258.00:34:06.88#ibcon#read 5, iclass 31, count 0 2006.258.00:34:06.88#ibcon#about to read 6, iclass 31, count 0 2006.258.00:34:06.88#ibcon#read 6, iclass 31, count 0 2006.258.00:34:06.88#ibcon#end of sib2, iclass 31, count 0 2006.258.00:34:06.88#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:34:06.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:34:06.88#ibcon#[27=USB\r\n] 2006.258.00:34:06.88#ibcon#*before write, iclass 31, count 0 2006.258.00:34:06.88#ibcon#enter sib2, iclass 31, count 0 2006.258.00:34:06.88#ibcon#flushed, iclass 31, count 0 2006.258.00:34:06.88#ibcon#about to write, iclass 31, count 0 2006.258.00:34:06.88#ibcon#wrote, iclass 31, count 0 2006.258.00:34:06.88#ibcon#about to read 3, iclass 31, count 0 2006.258.00:34:06.91#ibcon#read 3, iclass 31, count 0 2006.258.00:34:06.91#ibcon#about to read 4, iclass 31, count 0 2006.258.00:34:06.91#ibcon#read 4, iclass 31, count 0 2006.258.00:34:06.91#ibcon#about to read 5, iclass 31, count 0 2006.258.00:34:06.91#ibcon#read 5, iclass 31, count 0 2006.258.00:34:06.91#ibcon#about to read 6, iclass 31, count 0 2006.258.00:34:06.91#ibcon#read 6, iclass 31, count 0 2006.258.00:34:06.91#ibcon#end of sib2, iclass 31, count 0 2006.258.00:34:06.91#ibcon#*after write, iclass 31, count 0 2006.258.00:34:06.91#ibcon#*before return 0, iclass 31, count 0 2006.258.00:34:06.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:06.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:34:06.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:34:06.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:34:06.91$vck44/vblo=7,734.99 2006.258.00:34:06.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.00:34:06.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.00:34:06.91#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:06.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:06.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:06.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:06.91#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:34:06.91#ibcon#first serial, iclass 33, count 0 2006.258.00:34:06.91#ibcon#enter sib2, iclass 33, count 0 2006.258.00:34:06.91#ibcon#flushed, iclass 33, count 0 2006.258.00:34:06.91#ibcon#about to write, iclass 33, count 0 2006.258.00:34:06.91#ibcon#wrote, iclass 33, count 0 2006.258.00:34:06.91#ibcon#about to read 3, iclass 33, count 0 2006.258.00:34:06.93#ibcon#read 3, iclass 33, count 0 2006.258.00:34:06.93#ibcon#about to read 4, iclass 33, count 0 2006.258.00:34:06.93#ibcon#read 4, iclass 33, count 0 2006.258.00:34:06.93#ibcon#about to read 5, iclass 33, count 0 2006.258.00:34:06.93#ibcon#read 5, iclass 33, count 0 2006.258.00:34:06.93#ibcon#about to read 6, iclass 33, count 0 2006.258.00:34:06.93#ibcon#read 6, iclass 33, count 0 2006.258.00:34:06.93#ibcon#end of sib2, iclass 33, count 0 2006.258.00:34:06.93#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:34:06.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:34:06.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:34:06.93#ibcon#*before write, iclass 33, count 0 2006.258.00:34:06.93#ibcon#enter sib2, iclass 33, count 0 2006.258.00:34:06.93#ibcon#flushed, iclass 33, count 0 2006.258.00:34:06.93#ibcon#about to write, iclass 33, count 0 2006.258.00:34:06.93#ibcon#wrote, iclass 33, count 0 2006.258.00:34:06.93#ibcon#about to read 3, iclass 33, count 0 2006.258.00:34:06.97#ibcon#read 3, iclass 33, count 0 2006.258.00:34:06.97#ibcon#about to read 4, iclass 33, count 0 2006.258.00:34:06.97#ibcon#read 4, iclass 33, count 0 2006.258.00:34:06.97#ibcon#about to read 5, iclass 33, count 0 2006.258.00:34:06.97#ibcon#read 5, iclass 33, count 0 2006.258.00:34:06.97#ibcon#about to read 6, iclass 33, count 0 2006.258.00:34:06.97#ibcon#read 6, iclass 33, count 0 2006.258.00:34:06.97#ibcon#end of sib2, iclass 33, count 0 2006.258.00:34:06.97#ibcon#*after write, iclass 33, count 0 2006.258.00:34:06.97#ibcon#*before return 0, iclass 33, count 0 2006.258.00:34:06.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:06.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:34:06.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:34:06.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:34:06.97$vck44/vb=7,4 2006.258.00:34:06.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.00:34:06.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.00:34:06.97#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:06.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:07.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:07.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:07.03#ibcon#enter wrdev, iclass 35, count 2 2006.258.00:34:07.03#ibcon#first serial, iclass 35, count 2 2006.258.00:34:07.03#ibcon#enter sib2, iclass 35, count 2 2006.258.00:34:07.03#ibcon#flushed, iclass 35, count 2 2006.258.00:34:07.03#ibcon#about to write, iclass 35, count 2 2006.258.00:34:07.03#ibcon#wrote, iclass 35, count 2 2006.258.00:34:07.03#ibcon#about to read 3, iclass 35, count 2 2006.258.00:34:07.05#ibcon#read 3, iclass 35, count 2 2006.258.00:34:07.05#ibcon#about to read 4, iclass 35, count 2 2006.258.00:34:07.05#ibcon#read 4, iclass 35, count 2 2006.258.00:34:07.05#ibcon#about to read 5, iclass 35, count 2 2006.258.00:34:07.05#ibcon#read 5, iclass 35, count 2 2006.258.00:34:07.05#ibcon#about to read 6, iclass 35, count 2 2006.258.00:34:07.05#ibcon#read 6, iclass 35, count 2 2006.258.00:34:07.05#ibcon#end of sib2, iclass 35, count 2 2006.258.00:34:07.05#ibcon#*mode == 0, iclass 35, count 2 2006.258.00:34:07.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.00:34:07.05#ibcon#[27=AT07-04\r\n] 2006.258.00:34:07.05#ibcon#*before write, iclass 35, count 2 2006.258.00:34:07.05#ibcon#enter sib2, iclass 35, count 2 2006.258.00:34:07.05#ibcon#flushed, iclass 35, count 2 2006.258.00:34:07.05#ibcon#about to write, iclass 35, count 2 2006.258.00:34:07.05#ibcon#wrote, iclass 35, count 2 2006.258.00:34:07.05#ibcon#about to read 3, iclass 35, count 2 2006.258.00:34:07.08#ibcon#read 3, iclass 35, count 2 2006.258.00:34:07.08#ibcon#about to read 4, iclass 35, count 2 2006.258.00:34:07.08#ibcon#read 4, iclass 35, count 2 2006.258.00:34:07.08#ibcon#about to read 5, iclass 35, count 2 2006.258.00:34:07.08#ibcon#read 5, iclass 35, count 2 2006.258.00:34:07.08#ibcon#about to read 6, iclass 35, count 2 2006.258.00:34:07.08#ibcon#read 6, iclass 35, count 2 2006.258.00:34:07.08#ibcon#end of sib2, iclass 35, count 2 2006.258.00:34:07.08#ibcon#*after write, iclass 35, count 2 2006.258.00:34:07.08#ibcon#*before return 0, iclass 35, count 2 2006.258.00:34:07.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:07.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:34:07.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.00:34:07.08#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:07.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:07.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:07.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:07.20#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:34:07.20#ibcon#first serial, iclass 35, count 0 2006.258.00:34:07.20#ibcon#enter sib2, iclass 35, count 0 2006.258.00:34:07.20#ibcon#flushed, iclass 35, count 0 2006.258.00:34:07.20#ibcon#about to write, iclass 35, count 0 2006.258.00:34:07.20#ibcon#wrote, iclass 35, count 0 2006.258.00:34:07.20#ibcon#about to read 3, iclass 35, count 0 2006.258.00:34:07.22#ibcon#read 3, iclass 35, count 0 2006.258.00:34:07.22#ibcon#about to read 4, iclass 35, count 0 2006.258.00:34:07.22#ibcon#read 4, iclass 35, count 0 2006.258.00:34:07.22#ibcon#about to read 5, iclass 35, count 0 2006.258.00:34:07.22#ibcon#read 5, iclass 35, count 0 2006.258.00:34:07.22#ibcon#about to read 6, iclass 35, count 0 2006.258.00:34:07.22#ibcon#read 6, iclass 35, count 0 2006.258.00:34:07.22#ibcon#end of sib2, iclass 35, count 0 2006.258.00:34:07.22#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:34:07.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:34:07.22#ibcon#[27=USB\r\n] 2006.258.00:34:07.22#ibcon#*before write, iclass 35, count 0 2006.258.00:34:07.22#ibcon#enter sib2, iclass 35, count 0 2006.258.00:34:07.22#ibcon#flushed, iclass 35, count 0 2006.258.00:34:07.22#ibcon#about to write, iclass 35, count 0 2006.258.00:34:07.22#ibcon#wrote, iclass 35, count 0 2006.258.00:34:07.22#ibcon#about to read 3, iclass 35, count 0 2006.258.00:34:07.25#ibcon#read 3, iclass 35, count 0 2006.258.00:34:07.25#ibcon#about to read 4, iclass 35, count 0 2006.258.00:34:07.25#ibcon#read 4, iclass 35, count 0 2006.258.00:34:07.25#ibcon#about to read 5, iclass 35, count 0 2006.258.00:34:07.25#ibcon#read 5, iclass 35, count 0 2006.258.00:34:07.25#ibcon#about to read 6, iclass 35, count 0 2006.258.00:34:07.25#ibcon#read 6, iclass 35, count 0 2006.258.00:34:07.25#ibcon#end of sib2, iclass 35, count 0 2006.258.00:34:07.25#ibcon#*after write, iclass 35, count 0 2006.258.00:34:07.25#ibcon#*before return 0, iclass 35, count 0 2006.258.00:34:07.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:07.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:34:07.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:34:07.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:34:07.25$vck44/vblo=8,744.99 2006.258.00:34:07.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.00:34:07.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.00:34:07.25#ibcon#ireg 17 cls_cnt 0 2006.258.00:34:07.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:07.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:07.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:07.25#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:34:07.25#ibcon#first serial, iclass 37, count 0 2006.258.00:34:07.25#ibcon#enter sib2, iclass 37, count 0 2006.258.00:34:07.25#ibcon#flushed, iclass 37, count 0 2006.258.00:34:07.25#ibcon#about to write, iclass 37, count 0 2006.258.00:34:07.25#ibcon#wrote, iclass 37, count 0 2006.258.00:34:07.25#ibcon#about to read 3, iclass 37, count 0 2006.258.00:34:07.27#ibcon#read 3, iclass 37, count 0 2006.258.00:34:07.27#ibcon#about to read 4, iclass 37, count 0 2006.258.00:34:07.27#ibcon#read 4, iclass 37, count 0 2006.258.00:34:07.27#ibcon#about to read 5, iclass 37, count 0 2006.258.00:34:07.27#ibcon#read 5, iclass 37, count 0 2006.258.00:34:07.27#ibcon#about to read 6, iclass 37, count 0 2006.258.00:34:07.27#ibcon#read 6, iclass 37, count 0 2006.258.00:34:07.27#ibcon#end of sib2, iclass 37, count 0 2006.258.00:34:07.27#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:34:07.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:34:07.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:34:07.27#ibcon#*before write, iclass 37, count 0 2006.258.00:34:07.27#ibcon#enter sib2, iclass 37, count 0 2006.258.00:34:07.27#ibcon#flushed, iclass 37, count 0 2006.258.00:34:07.27#ibcon#about to write, iclass 37, count 0 2006.258.00:34:07.27#ibcon#wrote, iclass 37, count 0 2006.258.00:34:07.27#ibcon#about to read 3, iclass 37, count 0 2006.258.00:34:07.31#ibcon#read 3, iclass 37, count 0 2006.258.00:34:07.31#ibcon#about to read 4, iclass 37, count 0 2006.258.00:34:07.31#ibcon#read 4, iclass 37, count 0 2006.258.00:34:07.31#ibcon#about to read 5, iclass 37, count 0 2006.258.00:34:07.31#ibcon#read 5, iclass 37, count 0 2006.258.00:34:07.31#ibcon#about to read 6, iclass 37, count 0 2006.258.00:34:07.31#ibcon#read 6, iclass 37, count 0 2006.258.00:34:07.31#ibcon#end of sib2, iclass 37, count 0 2006.258.00:34:07.31#ibcon#*after write, iclass 37, count 0 2006.258.00:34:07.31#ibcon#*before return 0, iclass 37, count 0 2006.258.00:34:07.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:07.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:34:07.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:34:07.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:34:07.31$vck44/vb=8,4 2006.258.00:34:07.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.258.00:34:07.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.258.00:34:07.31#ibcon#ireg 11 cls_cnt 2 2006.258.00:34:07.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:07.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:07.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:07.37#ibcon#enter wrdev, iclass 39, count 2 2006.258.00:34:07.37#ibcon#first serial, iclass 39, count 2 2006.258.00:34:07.37#ibcon#enter sib2, iclass 39, count 2 2006.258.00:34:07.37#ibcon#flushed, iclass 39, count 2 2006.258.00:34:07.37#ibcon#about to write, iclass 39, count 2 2006.258.00:34:07.37#ibcon#wrote, iclass 39, count 2 2006.258.00:34:07.37#ibcon#about to read 3, iclass 39, count 2 2006.258.00:34:07.39#ibcon#read 3, iclass 39, count 2 2006.258.00:34:07.39#ibcon#about to read 4, iclass 39, count 2 2006.258.00:34:07.39#ibcon#read 4, iclass 39, count 2 2006.258.00:34:07.39#ibcon#about to read 5, iclass 39, count 2 2006.258.00:34:07.39#ibcon#read 5, iclass 39, count 2 2006.258.00:34:07.39#ibcon#about to read 6, iclass 39, count 2 2006.258.00:34:07.39#ibcon#read 6, iclass 39, count 2 2006.258.00:34:07.39#ibcon#end of sib2, iclass 39, count 2 2006.258.00:34:07.39#ibcon#*mode == 0, iclass 39, count 2 2006.258.00:34:07.39#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.258.00:34:07.39#ibcon#[27=AT08-04\r\n] 2006.258.00:34:07.39#ibcon#*before write, iclass 39, count 2 2006.258.00:34:07.39#ibcon#enter sib2, iclass 39, count 2 2006.258.00:34:07.39#ibcon#flushed, iclass 39, count 2 2006.258.00:34:07.39#ibcon#about to write, iclass 39, count 2 2006.258.00:34:07.39#ibcon#wrote, iclass 39, count 2 2006.258.00:34:07.39#ibcon#about to read 3, iclass 39, count 2 2006.258.00:34:07.42#ibcon#read 3, iclass 39, count 2 2006.258.00:34:07.42#ibcon#about to read 4, iclass 39, count 2 2006.258.00:34:07.42#ibcon#read 4, iclass 39, count 2 2006.258.00:34:07.42#ibcon#about to read 5, iclass 39, count 2 2006.258.00:34:07.42#ibcon#read 5, iclass 39, count 2 2006.258.00:34:07.42#ibcon#about to read 6, iclass 39, count 2 2006.258.00:34:07.42#ibcon#read 6, iclass 39, count 2 2006.258.00:34:07.42#ibcon#end of sib2, iclass 39, count 2 2006.258.00:34:07.42#ibcon#*after write, iclass 39, count 2 2006.258.00:34:07.42#ibcon#*before return 0, iclass 39, count 2 2006.258.00:34:07.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:07.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:34:07.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.258.00:34:07.42#ibcon#ireg 7 cls_cnt 0 2006.258.00:34:07.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:07.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:07.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:07.54#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:34:07.54#ibcon#first serial, iclass 39, count 0 2006.258.00:34:07.54#ibcon#enter sib2, iclass 39, count 0 2006.258.00:34:07.54#ibcon#flushed, iclass 39, count 0 2006.258.00:34:07.54#ibcon#about to write, iclass 39, count 0 2006.258.00:34:07.54#ibcon#wrote, iclass 39, count 0 2006.258.00:34:07.54#ibcon#about to read 3, iclass 39, count 0 2006.258.00:34:07.56#ibcon#read 3, iclass 39, count 0 2006.258.00:34:07.56#ibcon#about to read 4, iclass 39, count 0 2006.258.00:34:07.56#ibcon#read 4, iclass 39, count 0 2006.258.00:34:07.56#ibcon#about to read 5, iclass 39, count 0 2006.258.00:34:07.56#ibcon#read 5, iclass 39, count 0 2006.258.00:34:07.56#ibcon#about to read 6, iclass 39, count 0 2006.258.00:34:07.56#ibcon#read 6, iclass 39, count 0 2006.258.00:34:07.56#ibcon#end of sib2, iclass 39, count 0 2006.258.00:34:07.56#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:34:07.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:34:07.56#ibcon#[27=USB\r\n] 2006.258.00:34:07.56#ibcon#*before write, iclass 39, count 0 2006.258.00:34:07.56#ibcon#enter sib2, iclass 39, count 0 2006.258.00:34:07.56#ibcon#flushed, iclass 39, count 0 2006.258.00:34:07.56#ibcon#about to write, iclass 39, count 0 2006.258.00:34:07.56#ibcon#wrote, iclass 39, count 0 2006.258.00:34:07.56#ibcon#about to read 3, iclass 39, count 0 2006.258.00:34:07.59#ibcon#read 3, iclass 39, count 0 2006.258.00:34:07.59#ibcon#about to read 4, iclass 39, count 0 2006.258.00:34:07.59#ibcon#read 4, iclass 39, count 0 2006.258.00:34:07.59#ibcon#about to read 5, iclass 39, count 0 2006.258.00:34:07.59#ibcon#read 5, iclass 39, count 0 2006.258.00:34:07.59#ibcon#about to read 6, iclass 39, count 0 2006.258.00:34:07.59#ibcon#read 6, iclass 39, count 0 2006.258.00:34:07.59#ibcon#end of sib2, iclass 39, count 0 2006.258.00:34:07.59#ibcon#*after write, iclass 39, count 0 2006.258.00:34:07.59#ibcon#*before return 0, iclass 39, count 0 2006.258.00:34:07.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:07.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:34:07.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:34:07.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:34:07.59$vck44/vabw=wide 2006.258.00:34:07.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.00:34:07.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.00:34:07.59#ibcon#ireg 8 cls_cnt 0 2006.258.00:34:07.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:07.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:07.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:07.59#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:34:07.59#ibcon#first serial, iclass 3, count 0 2006.258.00:34:07.59#ibcon#enter sib2, iclass 3, count 0 2006.258.00:34:07.59#ibcon#flushed, iclass 3, count 0 2006.258.00:34:07.59#ibcon#about to write, iclass 3, count 0 2006.258.00:34:07.59#ibcon#wrote, iclass 3, count 0 2006.258.00:34:07.59#ibcon#about to read 3, iclass 3, count 0 2006.258.00:34:07.61#ibcon#read 3, iclass 3, count 0 2006.258.00:34:07.61#ibcon#about to read 4, iclass 3, count 0 2006.258.00:34:07.61#ibcon#read 4, iclass 3, count 0 2006.258.00:34:07.61#ibcon#about to read 5, iclass 3, count 0 2006.258.00:34:07.61#ibcon#read 5, iclass 3, count 0 2006.258.00:34:07.61#ibcon#about to read 6, iclass 3, count 0 2006.258.00:34:07.61#ibcon#read 6, iclass 3, count 0 2006.258.00:34:07.61#ibcon#end of sib2, iclass 3, count 0 2006.258.00:34:07.61#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:34:07.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:34:07.61#ibcon#[25=BW32\r\n] 2006.258.00:34:07.61#ibcon#*before write, iclass 3, count 0 2006.258.00:34:07.61#ibcon#enter sib2, iclass 3, count 0 2006.258.00:34:07.61#ibcon#flushed, iclass 3, count 0 2006.258.00:34:07.61#ibcon#about to write, iclass 3, count 0 2006.258.00:34:07.61#ibcon#wrote, iclass 3, count 0 2006.258.00:34:07.61#ibcon#about to read 3, iclass 3, count 0 2006.258.00:34:07.64#ibcon#read 3, iclass 3, count 0 2006.258.00:34:07.64#ibcon#about to read 4, iclass 3, count 0 2006.258.00:34:07.64#ibcon#read 4, iclass 3, count 0 2006.258.00:34:07.64#ibcon#about to read 5, iclass 3, count 0 2006.258.00:34:07.64#ibcon#read 5, iclass 3, count 0 2006.258.00:34:07.64#ibcon#about to read 6, iclass 3, count 0 2006.258.00:34:07.64#ibcon#read 6, iclass 3, count 0 2006.258.00:34:07.64#ibcon#end of sib2, iclass 3, count 0 2006.258.00:34:07.64#ibcon#*after write, iclass 3, count 0 2006.258.00:34:07.64#ibcon#*before return 0, iclass 3, count 0 2006.258.00:34:07.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:07.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:34:07.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:34:07.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:34:07.64$vck44/vbbw=wide 2006.258.00:34:07.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.00:34:07.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.00:34:07.64#ibcon#ireg 8 cls_cnt 0 2006.258.00:34:07.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:34:07.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:34:07.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:34:07.71#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:34:07.71#ibcon#first serial, iclass 5, count 0 2006.258.00:34:07.71#ibcon#enter sib2, iclass 5, count 0 2006.258.00:34:07.71#ibcon#flushed, iclass 5, count 0 2006.258.00:34:07.71#ibcon#about to write, iclass 5, count 0 2006.258.00:34:07.71#ibcon#wrote, iclass 5, count 0 2006.258.00:34:07.71#ibcon#about to read 3, iclass 5, count 0 2006.258.00:34:07.73#ibcon#read 3, iclass 5, count 0 2006.258.00:34:07.73#ibcon#about to read 4, iclass 5, count 0 2006.258.00:34:07.73#ibcon#read 4, iclass 5, count 0 2006.258.00:34:07.73#ibcon#about to read 5, iclass 5, count 0 2006.258.00:34:07.73#ibcon#read 5, iclass 5, count 0 2006.258.00:34:07.73#ibcon#about to read 6, iclass 5, count 0 2006.258.00:34:07.73#ibcon#read 6, iclass 5, count 0 2006.258.00:34:07.73#ibcon#end of sib2, iclass 5, count 0 2006.258.00:34:07.73#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:34:07.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:34:07.73#ibcon#[27=BW32\r\n] 2006.258.00:34:07.73#ibcon#*before write, iclass 5, count 0 2006.258.00:34:07.73#ibcon#enter sib2, iclass 5, count 0 2006.258.00:34:07.73#ibcon#flushed, iclass 5, count 0 2006.258.00:34:07.73#ibcon#about to write, iclass 5, count 0 2006.258.00:34:07.73#ibcon#wrote, iclass 5, count 0 2006.258.00:34:07.73#ibcon#about to read 3, iclass 5, count 0 2006.258.00:34:07.76#ibcon#read 3, iclass 5, count 0 2006.258.00:34:07.76#ibcon#about to read 4, iclass 5, count 0 2006.258.00:34:07.76#ibcon#read 4, iclass 5, count 0 2006.258.00:34:07.76#ibcon#about to read 5, iclass 5, count 0 2006.258.00:34:07.76#ibcon#read 5, iclass 5, count 0 2006.258.00:34:07.76#ibcon#about to read 6, iclass 5, count 0 2006.258.00:34:07.76#ibcon#read 6, iclass 5, count 0 2006.258.00:34:07.76#ibcon#end of sib2, iclass 5, count 0 2006.258.00:34:07.76#ibcon#*after write, iclass 5, count 0 2006.258.00:34:07.76#ibcon#*before return 0, iclass 5, count 0 2006.258.00:34:07.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:34:07.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:34:07.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:34:07.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:34:07.76$setupk4/ifdk4 2006.258.00:34:07.76$ifdk4/lo= 2006.258.00:34:07.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:34:07.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:34:07.76$ifdk4/patch= 2006.258.00:34:07.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:34:07.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:34:07.76$setupk4/!*+20s 2006.258.00:34:15.55#abcon#<5=/02 2.0 7.3 22.19 771016.1\r\n> 2006.258.00:34:15.57#abcon#{5=INTERFACE CLEAR} 2006.258.00:34:15.63#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:34:22.22$setupk4/"tpicd 2006.258.00:34:22.22$setupk4/echo=off 2006.258.00:34:22.22$setupk4/xlog=off 2006.258.00:34:22.22:!2006.258.00:36:03 2006.258.00:34:36.14#trakl#Source acquired 2006.258.00:34:37.14#flagr#flagr/antenna,acquired 2006.258.00:36:03.00:preob 2006.258.00:36:03.14/onsource/TRACKING 2006.258.00:36:03.14:!2006.258.00:36:13 2006.258.00:36:13.00:"tape 2006.258.00:36:13.00:"st=record 2006.258.00:36:13.00:data_valid=on 2006.258.00:36:13.00:midob 2006.258.00:36:13.14/onsource/TRACKING 2006.258.00:36:13.14/wx/22.23,1016.1,79 2006.258.00:36:13.31/cable/+6.4785E-03 2006.258.00:36:14.40/va/01,08,usb,yes,33,36 2006.258.00:36:14.40/va/02,07,usb,yes,36,37 2006.258.00:36:14.40/va/03,08,usb,yes,32,34 2006.258.00:36:14.40/va/04,07,usb,yes,37,39 2006.258.00:36:14.40/va/05,04,usb,yes,33,34 2006.258.00:36:14.40/va/06,04,usb,yes,37,37 2006.258.00:36:14.40/va/07,04,usb,yes,38,38 2006.258.00:36:14.40/va/08,04,usb,yes,32,39 2006.258.00:36:14.63/valo/01,524.99,yes,locked 2006.258.00:36:14.63/valo/02,534.99,yes,locked 2006.258.00:36:14.63/valo/03,564.99,yes,locked 2006.258.00:36:14.63/valo/04,624.99,yes,locked 2006.258.00:36:14.63/valo/05,734.99,yes,locked 2006.258.00:36:14.63/valo/06,814.99,yes,locked 2006.258.00:36:14.63/valo/07,864.99,yes,locked 2006.258.00:36:14.63/valo/08,884.99,yes,locked 2006.258.00:36:15.72/vb/01,04,usb,yes,32,30 2006.258.00:36:15.72/vb/02,05,usb,yes,30,30 2006.258.00:36:15.72/vb/03,04,usb,yes,31,34 2006.258.00:36:15.72/vb/04,05,usb,yes,31,30 2006.258.00:36:15.72/vb/05,04,usb,yes,28,30 2006.258.00:36:15.72/vb/06,04,usb,yes,33,29 2006.258.00:36:15.72/vb/07,04,usb,yes,32,32 2006.258.00:36:15.72/vb/08,04,usb,yes,30,33 2006.258.00:36:15.95/vblo/01,629.99,yes,locked 2006.258.00:36:15.95/vblo/02,634.99,yes,locked 2006.258.00:36:15.95/vblo/03,649.99,yes,locked 2006.258.00:36:15.95/vblo/04,679.99,yes,locked 2006.258.00:36:15.95/vblo/05,709.99,yes,locked 2006.258.00:36:15.95/vblo/06,719.99,yes,locked 2006.258.00:36:15.95/vblo/07,734.99,yes,locked 2006.258.00:36:15.95/vblo/08,744.99,yes,locked 2006.258.00:36:16.10/vabw/8 2006.258.00:36:16.25/vbbw/8 2006.258.00:36:16.34/xfe/off,on,15.0 2006.258.00:36:16.73/ifatt/23,28,28,28 2006.258.00:36:17.08/fmout-gps/S +4.57E-07 2006.258.00:36:17.12:!2006.258.00:41:13 2006.258.00:41:13.01:data_valid=off 2006.258.00:41:13.02:"et 2006.258.00:41:13.02:!+3s 2006.258.00:41:16.04:"tape 2006.258.00:41:16.04:postob 2006.258.00:41:16.12/cable/+6.4782E-03 2006.258.00:41:16.13/wx/22.35,1016.2,75 2006.258.00:41:16.18/fmout-gps/S +4.57E-07 2006.258.00:41:16.19:scan_name=258-0044,jd0609,90 2006.258.00:41:16.19:source=3c274,123049.42,122328.0,2000.0,ccw 2006.258.00:41:17.14#flagr#flagr/antenna,new-source 2006.258.00:41:17.14:checkk5 2006.258.00:41:17.55/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:41:17.96/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:41:18.36/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:41:18.76/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:41:19.15/chk_obsdata//k5ts1/T2580036??a.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.258.00:41:19.54/chk_obsdata//k5ts2/T2580036??b.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.258.00:41:19.94/chk_obsdata//k5ts3/T2580036??c.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.258.00:41:20.34/chk_obsdata//k5ts4/T2580036??d.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.258.00:41:21.07/k5log//k5ts1_log_newline 2006.258.00:41:21.78/k5log//k5ts2_log_newline 2006.258.00:41:22.48/k5log//k5ts3_log_newline 2006.258.00:41:23.20/k5log//k5ts4_log_newline 2006.258.00:41:23.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:41:23.23:setupk4=1 2006.258.00:41:23.23$setupk4/echo=on 2006.258.00:41:23.23$setupk4/pcalon 2006.258.00:41:23.23$pcalon/"no phase cal control is implemented here 2006.258.00:41:23.23$setupk4/"tpicd=stop 2006.258.00:41:23.23$setupk4/"rec=synch_on 2006.258.00:41:23.23$setupk4/"rec_mode=128 2006.258.00:41:23.23$setupk4/!* 2006.258.00:41:23.23$setupk4/recpk4 2006.258.00:41:23.23$recpk4/recpatch= 2006.258.00:41:23.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:41:23.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:41:23.23$setupk4/vck44 2006.258.00:41:23.23$vck44/valo=1,524.99 2006.258.00:41:23.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.00:41:23.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.00:41:23.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:23.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:23.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:23.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:23.23#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:41:23.23#ibcon#first serial, iclass 40, count 0 2006.258.00:41:23.23#ibcon#enter sib2, iclass 40, count 0 2006.258.00:41:23.23#ibcon#flushed, iclass 40, count 0 2006.258.00:41:23.23#ibcon#about to write, iclass 40, count 0 2006.258.00:41:23.23#ibcon#wrote, iclass 40, count 0 2006.258.00:41:23.23#ibcon#about to read 3, iclass 40, count 0 2006.258.00:41:23.24#ibcon#read 3, iclass 40, count 0 2006.258.00:41:23.24#ibcon#about to read 4, iclass 40, count 0 2006.258.00:41:23.24#ibcon#read 4, iclass 40, count 0 2006.258.00:41:23.24#ibcon#about to read 5, iclass 40, count 0 2006.258.00:41:23.24#ibcon#read 5, iclass 40, count 0 2006.258.00:41:23.24#ibcon#about to read 6, iclass 40, count 0 2006.258.00:41:23.24#ibcon#read 6, iclass 40, count 0 2006.258.00:41:23.24#ibcon#end of sib2, iclass 40, count 0 2006.258.00:41:23.24#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:41:23.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:41:23.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:41:23.24#ibcon#*before write, iclass 40, count 0 2006.258.00:41:23.24#ibcon#enter sib2, iclass 40, count 0 2006.258.00:41:23.24#ibcon#flushed, iclass 40, count 0 2006.258.00:41:23.24#ibcon#about to write, iclass 40, count 0 2006.258.00:41:23.24#ibcon#wrote, iclass 40, count 0 2006.258.00:41:23.24#ibcon#about to read 3, iclass 40, count 0 2006.258.00:41:23.29#ibcon#read 3, iclass 40, count 0 2006.258.00:41:23.29#ibcon#about to read 4, iclass 40, count 0 2006.258.00:41:23.29#ibcon#read 4, iclass 40, count 0 2006.258.00:41:23.29#ibcon#about to read 5, iclass 40, count 0 2006.258.00:41:23.29#ibcon#read 5, iclass 40, count 0 2006.258.00:41:23.29#ibcon#about to read 6, iclass 40, count 0 2006.258.00:41:23.29#ibcon#read 6, iclass 40, count 0 2006.258.00:41:23.29#ibcon#end of sib2, iclass 40, count 0 2006.258.00:41:23.29#ibcon#*after write, iclass 40, count 0 2006.258.00:41:23.29#ibcon#*before return 0, iclass 40, count 0 2006.258.00:41:23.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:23.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:23.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:41:23.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:41:23.29$vck44/va=1,8 2006.258.00:41:23.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.258.00:41:23.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.258.00:41:23.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:23.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:23.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:23.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:23.29#ibcon#enter wrdev, iclass 4, count 2 2006.258.00:41:23.29#ibcon#first serial, iclass 4, count 2 2006.258.00:41:23.30#ibcon#enter sib2, iclass 4, count 2 2006.258.00:41:23.30#ibcon#flushed, iclass 4, count 2 2006.258.00:41:23.30#ibcon#about to write, iclass 4, count 2 2006.258.00:41:23.30#ibcon#wrote, iclass 4, count 2 2006.258.00:41:23.30#ibcon#about to read 3, iclass 4, count 2 2006.258.00:41:23.31#ibcon#read 3, iclass 4, count 2 2006.258.00:41:23.31#ibcon#about to read 4, iclass 4, count 2 2006.258.00:41:23.31#ibcon#read 4, iclass 4, count 2 2006.258.00:41:23.31#ibcon#about to read 5, iclass 4, count 2 2006.258.00:41:23.31#ibcon#read 5, iclass 4, count 2 2006.258.00:41:23.31#ibcon#about to read 6, iclass 4, count 2 2006.258.00:41:23.31#ibcon#read 6, iclass 4, count 2 2006.258.00:41:23.31#ibcon#end of sib2, iclass 4, count 2 2006.258.00:41:23.31#ibcon#*mode == 0, iclass 4, count 2 2006.258.00:41:23.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.258.00:41:23.31#ibcon#[25=AT01-08\r\n] 2006.258.00:41:23.31#ibcon#*before write, iclass 4, count 2 2006.258.00:41:23.31#ibcon#enter sib2, iclass 4, count 2 2006.258.00:41:23.31#ibcon#flushed, iclass 4, count 2 2006.258.00:41:23.31#ibcon#about to write, iclass 4, count 2 2006.258.00:41:23.31#ibcon#wrote, iclass 4, count 2 2006.258.00:41:23.31#ibcon#about to read 3, iclass 4, count 2 2006.258.00:41:23.34#ibcon#read 3, iclass 4, count 2 2006.258.00:41:23.34#ibcon#about to read 4, iclass 4, count 2 2006.258.00:41:23.34#ibcon#read 4, iclass 4, count 2 2006.258.00:41:23.34#ibcon#about to read 5, iclass 4, count 2 2006.258.00:41:23.34#ibcon#read 5, iclass 4, count 2 2006.258.00:41:23.34#ibcon#about to read 6, iclass 4, count 2 2006.258.00:41:23.34#ibcon#read 6, iclass 4, count 2 2006.258.00:41:23.34#ibcon#end of sib2, iclass 4, count 2 2006.258.00:41:23.34#ibcon#*after write, iclass 4, count 2 2006.258.00:41:23.34#ibcon#*before return 0, iclass 4, count 2 2006.258.00:41:23.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:23.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:23.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.258.00:41:23.34#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:23.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:23.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:23.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:23.46#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:41:23.46#ibcon#first serial, iclass 4, count 0 2006.258.00:41:23.46#ibcon#enter sib2, iclass 4, count 0 2006.258.00:41:23.46#ibcon#flushed, iclass 4, count 0 2006.258.00:41:23.46#ibcon#about to write, iclass 4, count 0 2006.258.00:41:23.46#ibcon#wrote, iclass 4, count 0 2006.258.00:41:23.46#ibcon#about to read 3, iclass 4, count 0 2006.258.00:41:23.48#ibcon#read 3, iclass 4, count 0 2006.258.00:41:23.48#ibcon#about to read 4, iclass 4, count 0 2006.258.00:41:23.48#ibcon#read 4, iclass 4, count 0 2006.258.00:41:23.48#ibcon#about to read 5, iclass 4, count 0 2006.258.00:41:23.48#ibcon#read 5, iclass 4, count 0 2006.258.00:41:23.48#ibcon#about to read 6, iclass 4, count 0 2006.258.00:41:23.48#ibcon#read 6, iclass 4, count 0 2006.258.00:41:23.48#ibcon#end of sib2, iclass 4, count 0 2006.258.00:41:23.48#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:41:23.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:41:23.48#ibcon#[25=USB\r\n] 2006.258.00:41:23.48#ibcon#*before write, iclass 4, count 0 2006.258.00:41:23.48#ibcon#enter sib2, iclass 4, count 0 2006.258.00:41:23.48#ibcon#flushed, iclass 4, count 0 2006.258.00:41:23.48#ibcon#about to write, iclass 4, count 0 2006.258.00:41:23.48#ibcon#wrote, iclass 4, count 0 2006.258.00:41:23.48#ibcon#about to read 3, iclass 4, count 0 2006.258.00:41:23.51#ibcon#read 3, iclass 4, count 0 2006.258.00:41:23.51#ibcon#about to read 4, iclass 4, count 0 2006.258.00:41:23.51#ibcon#read 4, iclass 4, count 0 2006.258.00:41:23.51#ibcon#about to read 5, iclass 4, count 0 2006.258.00:41:23.51#ibcon#read 5, iclass 4, count 0 2006.258.00:41:23.51#ibcon#about to read 6, iclass 4, count 0 2006.258.00:41:23.51#ibcon#read 6, iclass 4, count 0 2006.258.00:41:23.51#ibcon#end of sib2, iclass 4, count 0 2006.258.00:41:23.51#ibcon#*after write, iclass 4, count 0 2006.258.00:41:23.51#ibcon#*before return 0, iclass 4, count 0 2006.258.00:41:23.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:23.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:23.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:41:23.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:41:23.51$vck44/valo=2,534.99 2006.258.00:41:23.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.00:41:23.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.00:41:23.51#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:23.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:23.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:23.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:23.51#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:41:23.51#ibcon#first serial, iclass 6, count 0 2006.258.00:41:23.51#ibcon#enter sib2, iclass 6, count 0 2006.258.00:41:23.52#ibcon#flushed, iclass 6, count 0 2006.258.00:41:23.52#ibcon#about to write, iclass 6, count 0 2006.258.00:41:23.52#ibcon#wrote, iclass 6, count 0 2006.258.00:41:23.52#ibcon#about to read 3, iclass 6, count 0 2006.258.00:41:23.53#ibcon#read 3, iclass 6, count 0 2006.258.00:41:23.53#ibcon#about to read 4, iclass 6, count 0 2006.258.00:41:23.53#ibcon#read 4, iclass 6, count 0 2006.258.00:41:23.53#ibcon#about to read 5, iclass 6, count 0 2006.258.00:41:23.53#ibcon#read 5, iclass 6, count 0 2006.258.00:41:23.53#ibcon#about to read 6, iclass 6, count 0 2006.258.00:41:23.53#ibcon#read 6, iclass 6, count 0 2006.258.00:41:23.53#ibcon#end of sib2, iclass 6, count 0 2006.258.00:41:23.53#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:41:23.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:41:23.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:41:23.53#ibcon#*before write, iclass 6, count 0 2006.258.00:41:23.53#ibcon#enter sib2, iclass 6, count 0 2006.258.00:41:23.53#ibcon#flushed, iclass 6, count 0 2006.258.00:41:23.53#ibcon#about to write, iclass 6, count 0 2006.258.00:41:23.53#ibcon#wrote, iclass 6, count 0 2006.258.00:41:23.53#ibcon#about to read 3, iclass 6, count 0 2006.258.00:41:23.57#ibcon#read 3, iclass 6, count 0 2006.258.00:41:23.57#ibcon#about to read 4, iclass 6, count 0 2006.258.00:41:23.57#ibcon#read 4, iclass 6, count 0 2006.258.00:41:23.57#ibcon#about to read 5, iclass 6, count 0 2006.258.00:41:23.57#ibcon#read 5, iclass 6, count 0 2006.258.00:41:23.57#ibcon#about to read 6, iclass 6, count 0 2006.258.00:41:23.57#ibcon#read 6, iclass 6, count 0 2006.258.00:41:23.57#ibcon#end of sib2, iclass 6, count 0 2006.258.00:41:23.57#ibcon#*after write, iclass 6, count 0 2006.258.00:41:23.57#ibcon#*before return 0, iclass 6, count 0 2006.258.00:41:23.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:23.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:23.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:41:23.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:41:23.57$vck44/va=2,7 2006.258.00:41:23.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.258.00:41:23.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.258.00:41:23.57#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:23.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:23.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:23.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:23.63#ibcon#enter wrdev, iclass 10, count 2 2006.258.00:41:23.63#ibcon#first serial, iclass 10, count 2 2006.258.00:41:23.63#ibcon#enter sib2, iclass 10, count 2 2006.258.00:41:23.63#ibcon#flushed, iclass 10, count 2 2006.258.00:41:23.63#ibcon#about to write, iclass 10, count 2 2006.258.00:41:23.63#ibcon#wrote, iclass 10, count 2 2006.258.00:41:23.63#ibcon#about to read 3, iclass 10, count 2 2006.258.00:41:23.65#ibcon#read 3, iclass 10, count 2 2006.258.00:41:23.65#ibcon#about to read 4, iclass 10, count 2 2006.258.00:41:23.65#ibcon#read 4, iclass 10, count 2 2006.258.00:41:23.65#ibcon#about to read 5, iclass 10, count 2 2006.258.00:41:23.65#ibcon#read 5, iclass 10, count 2 2006.258.00:41:23.65#ibcon#about to read 6, iclass 10, count 2 2006.258.00:41:23.65#ibcon#read 6, iclass 10, count 2 2006.258.00:41:23.65#ibcon#end of sib2, iclass 10, count 2 2006.258.00:41:23.65#ibcon#*mode == 0, iclass 10, count 2 2006.258.00:41:23.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.258.00:41:23.65#ibcon#[25=AT02-07\r\n] 2006.258.00:41:23.65#ibcon#*before write, iclass 10, count 2 2006.258.00:41:23.65#ibcon#enter sib2, iclass 10, count 2 2006.258.00:41:23.65#ibcon#flushed, iclass 10, count 2 2006.258.00:41:23.65#ibcon#about to write, iclass 10, count 2 2006.258.00:41:23.65#ibcon#wrote, iclass 10, count 2 2006.258.00:41:23.65#ibcon#about to read 3, iclass 10, count 2 2006.258.00:41:23.68#ibcon#read 3, iclass 10, count 2 2006.258.00:41:23.68#ibcon#about to read 4, iclass 10, count 2 2006.258.00:41:23.68#ibcon#read 4, iclass 10, count 2 2006.258.00:41:23.68#ibcon#about to read 5, iclass 10, count 2 2006.258.00:41:23.68#ibcon#read 5, iclass 10, count 2 2006.258.00:41:23.68#ibcon#about to read 6, iclass 10, count 2 2006.258.00:41:23.68#ibcon#read 6, iclass 10, count 2 2006.258.00:41:23.68#ibcon#end of sib2, iclass 10, count 2 2006.258.00:41:23.68#ibcon#*after write, iclass 10, count 2 2006.258.00:41:23.68#ibcon#*before return 0, iclass 10, count 2 2006.258.00:41:23.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:23.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:23.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.258.00:41:23.68#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:23.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:23.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:23.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:23.80#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:41:23.80#ibcon#first serial, iclass 10, count 0 2006.258.00:41:23.80#ibcon#enter sib2, iclass 10, count 0 2006.258.00:41:23.80#ibcon#flushed, iclass 10, count 0 2006.258.00:41:23.80#ibcon#about to write, iclass 10, count 0 2006.258.00:41:23.80#ibcon#wrote, iclass 10, count 0 2006.258.00:41:23.80#ibcon#about to read 3, iclass 10, count 0 2006.258.00:41:23.82#ibcon#read 3, iclass 10, count 0 2006.258.00:41:23.82#ibcon#about to read 4, iclass 10, count 0 2006.258.00:41:23.82#ibcon#read 4, iclass 10, count 0 2006.258.00:41:23.82#ibcon#about to read 5, iclass 10, count 0 2006.258.00:41:23.82#ibcon#read 5, iclass 10, count 0 2006.258.00:41:23.82#ibcon#about to read 6, iclass 10, count 0 2006.258.00:41:23.82#ibcon#read 6, iclass 10, count 0 2006.258.00:41:23.82#ibcon#end of sib2, iclass 10, count 0 2006.258.00:41:23.82#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:41:23.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:41:23.82#ibcon#[25=USB\r\n] 2006.258.00:41:23.82#ibcon#*before write, iclass 10, count 0 2006.258.00:41:23.82#ibcon#enter sib2, iclass 10, count 0 2006.258.00:41:23.82#ibcon#flushed, iclass 10, count 0 2006.258.00:41:23.82#ibcon#about to write, iclass 10, count 0 2006.258.00:41:23.82#ibcon#wrote, iclass 10, count 0 2006.258.00:41:23.82#ibcon#about to read 3, iclass 10, count 0 2006.258.00:41:23.85#ibcon#read 3, iclass 10, count 0 2006.258.00:41:23.85#ibcon#about to read 4, iclass 10, count 0 2006.258.00:41:23.85#ibcon#read 4, iclass 10, count 0 2006.258.00:41:23.85#ibcon#about to read 5, iclass 10, count 0 2006.258.00:41:23.85#ibcon#read 5, iclass 10, count 0 2006.258.00:41:23.85#ibcon#about to read 6, iclass 10, count 0 2006.258.00:41:23.85#ibcon#read 6, iclass 10, count 0 2006.258.00:41:23.85#ibcon#end of sib2, iclass 10, count 0 2006.258.00:41:23.85#ibcon#*after write, iclass 10, count 0 2006.258.00:41:23.85#ibcon#*before return 0, iclass 10, count 0 2006.258.00:41:23.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:23.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:23.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:41:23.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:41:23.85$vck44/valo=3,564.99 2006.258.00:41:23.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.00:41:23.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.00:41:23.85#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:23.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:23.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:23.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:23.85#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:41:23.85#ibcon#first serial, iclass 12, count 0 2006.258.00:41:23.85#ibcon#enter sib2, iclass 12, count 0 2006.258.00:41:23.86#ibcon#flushed, iclass 12, count 0 2006.258.00:41:23.86#ibcon#about to write, iclass 12, count 0 2006.258.00:41:23.86#ibcon#wrote, iclass 12, count 0 2006.258.00:41:23.86#ibcon#about to read 3, iclass 12, count 0 2006.258.00:41:23.87#ibcon#read 3, iclass 12, count 0 2006.258.00:41:23.87#ibcon#about to read 4, iclass 12, count 0 2006.258.00:41:23.87#ibcon#read 4, iclass 12, count 0 2006.258.00:41:23.87#ibcon#about to read 5, iclass 12, count 0 2006.258.00:41:23.87#ibcon#read 5, iclass 12, count 0 2006.258.00:41:23.87#ibcon#about to read 6, iclass 12, count 0 2006.258.00:41:23.87#ibcon#read 6, iclass 12, count 0 2006.258.00:41:23.87#ibcon#end of sib2, iclass 12, count 0 2006.258.00:41:23.87#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:41:23.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:41:23.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:41:23.87#ibcon#*before write, iclass 12, count 0 2006.258.00:41:23.87#ibcon#enter sib2, iclass 12, count 0 2006.258.00:41:23.87#ibcon#flushed, iclass 12, count 0 2006.258.00:41:23.87#ibcon#about to write, iclass 12, count 0 2006.258.00:41:23.87#ibcon#wrote, iclass 12, count 0 2006.258.00:41:23.87#ibcon#about to read 3, iclass 12, count 0 2006.258.00:41:23.91#ibcon#read 3, iclass 12, count 0 2006.258.00:41:23.91#ibcon#about to read 4, iclass 12, count 0 2006.258.00:41:23.91#ibcon#read 4, iclass 12, count 0 2006.258.00:41:23.91#ibcon#about to read 5, iclass 12, count 0 2006.258.00:41:23.91#ibcon#read 5, iclass 12, count 0 2006.258.00:41:23.91#ibcon#about to read 6, iclass 12, count 0 2006.258.00:41:23.91#ibcon#read 6, iclass 12, count 0 2006.258.00:41:23.91#ibcon#end of sib2, iclass 12, count 0 2006.258.00:41:23.91#ibcon#*after write, iclass 12, count 0 2006.258.00:41:23.91#ibcon#*before return 0, iclass 12, count 0 2006.258.00:41:23.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:23.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:23.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:41:23.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:41:23.91$vck44/va=3,8 2006.258.00:41:23.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.258.00:41:23.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.258.00:41:23.91#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:23.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:23.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:23.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:23.97#ibcon#enter wrdev, iclass 14, count 2 2006.258.00:41:23.97#ibcon#first serial, iclass 14, count 2 2006.258.00:41:23.97#ibcon#enter sib2, iclass 14, count 2 2006.258.00:41:23.97#ibcon#flushed, iclass 14, count 2 2006.258.00:41:23.97#ibcon#about to write, iclass 14, count 2 2006.258.00:41:23.97#ibcon#wrote, iclass 14, count 2 2006.258.00:41:23.97#ibcon#about to read 3, iclass 14, count 2 2006.258.00:41:23.99#ibcon#read 3, iclass 14, count 2 2006.258.00:41:23.99#ibcon#about to read 4, iclass 14, count 2 2006.258.00:41:23.99#ibcon#read 4, iclass 14, count 2 2006.258.00:41:23.99#ibcon#about to read 5, iclass 14, count 2 2006.258.00:41:23.99#ibcon#read 5, iclass 14, count 2 2006.258.00:41:23.99#ibcon#about to read 6, iclass 14, count 2 2006.258.00:41:23.99#ibcon#read 6, iclass 14, count 2 2006.258.00:41:23.99#ibcon#end of sib2, iclass 14, count 2 2006.258.00:41:23.99#ibcon#*mode == 0, iclass 14, count 2 2006.258.00:41:23.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.258.00:41:23.99#ibcon#[25=AT03-08\r\n] 2006.258.00:41:23.99#ibcon#*before write, iclass 14, count 2 2006.258.00:41:23.99#ibcon#enter sib2, iclass 14, count 2 2006.258.00:41:23.99#ibcon#flushed, iclass 14, count 2 2006.258.00:41:23.99#ibcon#about to write, iclass 14, count 2 2006.258.00:41:23.99#ibcon#wrote, iclass 14, count 2 2006.258.00:41:23.99#ibcon#about to read 3, iclass 14, count 2 2006.258.00:41:24.02#ibcon#read 3, iclass 14, count 2 2006.258.00:41:24.02#ibcon#about to read 4, iclass 14, count 2 2006.258.00:41:24.02#ibcon#read 4, iclass 14, count 2 2006.258.00:41:24.02#ibcon#about to read 5, iclass 14, count 2 2006.258.00:41:24.02#ibcon#read 5, iclass 14, count 2 2006.258.00:41:24.02#ibcon#about to read 6, iclass 14, count 2 2006.258.00:41:24.02#ibcon#read 6, iclass 14, count 2 2006.258.00:41:24.02#ibcon#end of sib2, iclass 14, count 2 2006.258.00:41:24.02#ibcon#*after write, iclass 14, count 2 2006.258.00:41:24.02#ibcon#*before return 0, iclass 14, count 2 2006.258.00:41:24.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:24.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:24.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.258.00:41:24.02#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:24.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:24.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:24.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:24.14#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:41:24.14#ibcon#first serial, iclass 14, count 0 2006.258.00:41:24.14#ibcon#enter sib2, iclass 14, count 0 2006.258.00:41:24.14#ibcon#flushed, iclass 14, count 0 2006.258.00:41:24.14#ibcon#about to write, iclass 14, count 0 2006.258.00:41:24.14#ibcon#wrote, iclass 14, count 0 2006.258.00:41:24.14#ibcon#about to read 3, iclass 14, count 0 2006.258.00:41:24.16#ibcon#read 3, iclass 14, count 0 2006.258.00:41:24.16#ibcon#about to read 4, iclass 14, count 0 2006.258.00:41:24.16#ibcon#read 4, iclass 14, count 0 2006.258.00:41:24.16#ibcon#about to read 5, iclass 14, count 0 2006.258.00:41:24.16#ibcon#read 5, iclass 14, count 0 2006.258.00:41:24.16#ibcon#about to read 6, iclass 14, count 0 2006.258.00:41:24.16#ibcon#read 6, iclass 14, count 0 2006.258.00:41:24.16#ibcon#end of sib2, iclass 14, count 0 2006.258.00:41:24.16#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:41:24.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:41:24.16#ibcon#[25=USB\r\n] 2006.258.00:41:24.16#ibcon#*before write, iclass 14, count 0 2006.258.00:41:24.16#ibcon#enter sib2, iclass 14, count 0 2006.258.00:41:24.16#ibcon#flushed, iclass 14, count 0 2006.258.00:41:24.16#ibcon#about to write, iclass 14, count 0 2006.258.00:41:24.16#ibcon#wrote, iclass 14, count 0 2006.258.00:41:24.16#ibcon#about to read 3, iclass 14, count 0 2006.258.00:41:24.19#ibcon#read 3, iclass 14, count 0 2006.258.00:41:24.19#ibcon#about to read 4, iclass 14, count 0 2006.258.00:41:24.19#ibcon#read 4, iclass 14, count 0 2006.258.00:41:24.19#ibcon#about to read 5, iclass 14, count 0 2006.258.00:41:24.19#ibcon#read 5, iclass 14, count 0 2006.258.00:41:24.19#ibcon#about to read 6, iclass 14, count 0 2006.258.00:41:24.19#ibcon#read 6, iclass 14, count 0 2006.258.00:41:24.19#ibcon#end of sib2, iclass 14, count 0 2006.258.00:41:24.19#ibcon#*after write, iclass 14, count 0 2006.258.00:41:24.19#ibcon#*before return 0, iclass 14, count 0 2006.258.00:41:24.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:24.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:24.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:41:24.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:41:24.19$vck44/valo=4,624.99 2006.258.00:41:24.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.00:41:24.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.00:41:24.19#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:24.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:24.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:24.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:24.20#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:41:24.20#ibcon#first serial, iclass 16, count 0 2006.258.00:41:24.20#ibcon#enter sib2, iclass 16, count 0 2006.258.00:41:24.20#ibcon#flushed, iclass 16, count 0 2006.258.00:41:24.20#ibcon#about to write, iclass 16, count 0 2006.258.00:41:24.20#ibcon#wrote, iclass 16, count 0 2006.258.00:41:24.20#ibcon#about to read 3, iclass 16, count 0 2006.258.00:41:24.21#ibcon#read 3, iclass 16, count 0 2006.258.00:41:24.21#ibcon#about to read 4, iclass 16, count 0 2006.258.00:41:24.21#ibcon#read 4, iclass 16, count 0 2006.258.00:41:24.21#ibcon#about to read 5, iclass 16, count 0 2006.258.00:41:24.21#ibcon#read 5, iclass 16, count 0 2006.258.00:41:24.21#ibcon#about to read 6, iclass 16, count 0 2006.258.00:41:24.21#ibcon#read 6, iclass 16, count 0 2006.258.00:41:24.21#ibcon#end of sib2, iclass 16, count 0 2006.258.00:41:24.21#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:41:24.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:41:24.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:41:24.21#ibcon#*before write, iclass 16, count 0 2006.258.00:41:24.21#ibcon#enter sib2, iclass 16, count 0 2006.258.00:41:24.21#ibcon#flushed, iclass 16, count 0 2006.258.00:41:24.21#ibcon#about to write, iclass 16, count 0 2006.258.00:41:24.21#ibcon#wrote, iclass 16, count 0 2006.258.00:41:24.21#ibcon#about to read 3, iclass 16, count 0 2006.258.00:41:24.25#ibcon#read 3, iclass 16, count 0 2006.258.00:41:24.25#ibcon#about to read 4, iclass 16, count 0 2006.258.00:41:24.25#ibcon#read 4, iclass 16, count 0 2006.258.00:41:24.25#ibcon#about to read 5, iclass 16, count 0 2006.258.00:41:24.25#ibcon#read 5, iclass 16, count 0 2006.258.00:41:24.25#ibcon#about to read 6, iclass 16, count 0 2006.258.00:41:24.25#ibcon#read 6, iclass 16, count 0 2006.258.00:41:24.25#ibcon#end of sib2, iclass 16, count 0 2006.258.00:41:24.25#ibcon#*after write, iclass 16, count 0 2006.258.00:41:24.25#ibcon#*before return 0, iclass 16, count 0 2006.258.00:41:24.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:24.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:24.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:41:24.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:41:24.25$vck44/va=4,7 2006.258.00:41:24.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.258.00:41:24.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.258.00:41:24.25#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:24.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:24.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:24.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:24.31#ibcon#enter wrdev, iclass 18, count 2 2006.258.00:41:24.31#ibcon#first serial, iclass 18, count 2 2006.258.00:41:24.31#ibcon#enter sib2, iclass 18, count 2 2006.258.00:41:24.31#ibcon#flushed, iclass 18, count 2 2006.258.00:41:24.31#ibcon#about to write, iclass 18, count 2 2006.258.00:41:24.31#ibcon#wrote, iclass 18, count 2 2006.258.00:41:24.31#ibcon#about to read 3, iclass 18, count 2 2006.258.00:41:24.33#ibcon#read 3, iclass 18, count 2 2006.258.00:41:24.33#ibcon#about to read 4, iclass 18, count 2 2006.258.00:41:24.33#ibcon#read 4, iclass 18, count 2 2006.258.00:41:24.33#ibcon#about to read 5, iclass 18, count 2 2006.258.00:41:24.33#ibcon#read 5, iclass 18, count 2 2006.258.00:41:24.33#ibcon#about to read 6, iclass 18, count 2 2006.258.00:41:24.33#ibcon#read 6, iclass 18, count 2 2006.258.00:41:24.33#ibcon#end of sib2, iclass 18, count 2 2006.258.00:41:24.33#ibcon#*mode == 0, iclass 18, count 2 2006.258.00:41:24.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.258.00:41:24.33#ibcon#[25=AT04-07\r\n] 2006.258.00:41:24.33#ibcon#*before write, iclass 18, count 2 2006.258.00:41:24.33#ibcon#enter sib2, iclass 18, count 2 2006.258.00:41:24.33#ibcon#flushed, iclass 18, count 2 2006.258.00:41:24.33#ibcon#about to write, iclass 18, count 2 2006.258.00:41:24.33#ibcon#wrote, iclass 18, count 2 2006.258.00:41:24.33#ibcon#about to read 3, iclass 18, count 2 2006.258.00:41:24.36#ibcon#read 3, iclass 18, count 2 2006.258.00:41:24.36#ibcon#about to read 4, iclass 18, count 2 2006.258.00:41:24.36#ibcon#read 4, iclass 18, count 2 2006.258.00:41:24.36#ibcon#about to read 5, iclass 18, count 2 2006.258.00:41:24.36#ibcon#read 5, iclass 18, count 2 2006.258.00:41:24.36#ibcon#about to read 6, iclass 18, count 2 2006.258.00:41:24.36#ibcon#read 6, iclass 18, count 2 2006.258.00:41:24.36#ibcon#end of sib2, iclass 18, count 2 2006.258.00:41:24.36#ibcon#*after write, iclass 18, count 2 2006.258.00:41:24.36#ibcon#*before return 0, iclass 18, count 2 2006.258.00:41:24.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:24.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:24.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.258.00:41:24.36#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:24.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:24.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:24.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:24.48#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:41:24.48#ibcon#first serial, iclass 18, count 0 2006.258.00:41:24.48#ibcon#enter sib2, iclass 18, count 0 2006.258.00:41:24.48#ibcon#flushed, iclass 18, count 0 2006.258.00:41:24.48#ibcon#about to write, iclass 18, count 0 2006.258.00:41:24.48#ibcon#wrote, iclass 18, count 0 2006.258.00:41:24.48#ibcon#about to read 3, iclass 18, count 0 2006.258.00:41:24.50#ibcon#read 3, iclass 18, count 0 2006.258.00:41:24.50#ibcon#about to read 4, iclass 18, count 0 2006.258.00:41:24.50#ibcon#read 4, iclass 18, count 0 2006.258.00:41:24.50#ibcon#about to read 5, iclass 18, count 0 2006.258.00:41:24.50#ibcon#read 5, iclass 18, count 0 2006.258.00:41:24.50#ibcon#about to read 6, iclass 18, count 0 2006.258.00:41:24.50#ibcon#read 6, iclass 18, count 0 2006.258.00:41:24.50#ibcon#end of sib2, iclass 18, count 0 2006.258.00:41:24.50#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:41:24.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:41:24.50#ibcon#[25=USB\r\n] 2006.258.00:41:24.50#ibcon#*before write, iclass 18, count 0 2006.258.00:41:24.50#ibcon#enter sib2, iclass 18, count 0 2006.258.00:41:24.50#ibcon#flushed, iclass 18, count 0 2006.258.00:41:24.50#ibcon#about to write, iclass 18, count 0 2006.258.00:41:24.50#ibcon#wrote, iclass 18, count 0 2006.258.00:41:24.50#ibcon#about to read 3, iclass 18, count 0 2006.258.00:41:24.53#ibcon#read 3, iclass 18, count 0 2006.258.00:41:24.53#ibcon#about to read 4, iclass 18, count 0 2006.258.00:41:24.53#ibcon#read 4, iclass 18, count 0 2006.258.00:41:24.53#ibcon#about to read 5, iclass 18, count 0 2006.258.00:41:24.53#ibcon#read 5, iclass 18, count 0 2006.258.00:41:24.53#ibcon#about to read 6, iclass 18, count 0 2006.258.00:41:24.53#ibcon#read 6, iclass 18, count 0 2006.258.00:41:24.53#ibcon#end of sib2, iclass 18, count 0 2006.258.00:41:24.53#ibcon#*after write, iclass 18, count 0 2006.258.00:41:24.53#ibcon#*before return 0, iclass 18, count 0 2006.258.00:41:24.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:24.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:24.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:41:24.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:41:24.53$vck44/valo=5,734.99 2006.258.00:41:24.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.00:41:24.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.00:41:24.53#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:24.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:24.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:24.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:24.54#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:41:24.54#ibcon#first serial, iclass 20, count 0 2006.258.00:41:24.54#ibcon#enter sib2, iclass 20, count 0 2006.258.00:41:24.54#ibcon#flushed, iclass 20, count 0 2006.258.00:41:24.54#ibcon#about to write, iclass 20, count 0 2006.258.00:41:24.54#ibcon#wrote, iclass 20, count 0 2006.258.00:41:24.54#ibcon#about to read 3, iclass 20, count 0 2006.258.00:41:24.55#ibcon#read 3, iclass 20, count 0 2006.258.00:41:24.55#ibcon#about to read 4, iclass 20, count 0 2006.258.00:41:24.55#ibcon#read 4, iclass 20, count 0 2006.258.00:41:24.55#ibcon#about to read 5, iclass 20, count 0 2006.258.00:41:24.55#ibcon#read 5, iclass 20, count 0 2006.258.00:41:24.55#ibcon#about to read 6, iclass 20, count 0 2006.258.00:41:24.55#ibcon#read 6, iclass 20, count 0 2006.258.00:41:24.55#ibcon#end of sib2, iclass 20, count 0 2006.258.00:41:24.55#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:41:24.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:41:24.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:41:24.55#ibcon#*before write, iclass 20, count 0 2006.258.00:41:24.55#ibcon#enter sib2, iclass 20, count 0 2006.258.00:41:24.55#ibcon#flushed, iclass 20, count 0 2006.258.00:41:24.55#ibcon#about to write, iclass 20, count 0 2006.258.00:41:24.55#ibcon#wrote, iclass 20, count 0 2006.258.00:41:24.55#ibcon#about to read 3, iclass 20, count 0 2006.258.00:41:24.59#ibcon#read 3, iclass 20, count 0 2006.258.00:41:24.59#ibcon#about to read 4, iclass 20, count 0 2006.258.00:41:24.59#ibcon#read 4, iclass 20, count 0 2006.258.00:41:24.59#ibcon#about to read 5, iclass 20, count 0 2006.258.00:41:24.59#ibcon#read 5, iclass 20, count 0 2006.258.00:41:24.59#ibcon#about to read 6, iclass 20, count 0 2006.258.00:41:24.59#ibcon#read 6, iclass 20, count 0 2006.258.00:41:24.59#ibcon#end of sib2, iclass 20, count 0 2006.258.00:41:24.59#ibcon#*after write, iclass 20, count 0 2006.258.00:41:24.59#ibcon#*before return 0, iclass 20, count 0 2006.258.00:41:24.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:24.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:24.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:41:24.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:41:24.59$vck44/va=5,4 2006.258.00:41:24.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.00:41:24.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.00:41:24.59#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:24.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:24.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:24.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:24.65#ibcon#enter wrdev, iclass 22, count 2 2006.258.00:41:24.65#ibcon#first serial, iclass 22, count 2 2006.258.00:41:24.65#ibcon#enter sib2, iclass 22, count 2 2006.258.00:41:24.65#ibcon#flushed, iclass 22, count 2 2006.258.00:41:24.65#ibcon#about to write, iclass 22, count 2 2006.258.00:41:24.65#ibcon#wrote, iclass 22, count 2 2006.258.00:41:24.65#ibcon#about to read 3, iclass 22, count 2 2006.258.00:41:24.67#ibcon#read 3, iclass 22, count 2 2006.258.00:41:24.67#ibcon#about to read 4, iclass 22, count 2 2006.258.00:41:24.67#ibcon#read 4, iclass 22, count 2 2006.258.00:41:24.67#ibcon#about to read 5, iclass 22, count 2 2006.258.00:41:24.67#ibcon#read 5, iclass 22, count 2 2006.258.00:41:24.67#ibcon#about to read 6, iclass 22, count 2 2006.258.00:41:24.67#ibcon#read 6, iclass 22, count 2 2006.258.00:41:24.67#ibcon#end of sib2, iclass 22, count 2 2006.258.00:41:24.67#ibcon#*mode == 0, iclass 22, count 2 2006.258.00:41:24.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.00:41:24.67#ibcon#[25=AT05-04\r\n] 2006.258.00:41:24.67#ibcon#*before write, iclass 22, count 2 2006.258.00:41:24.67#ibcon#enter sib2, iclass 22, count 2 2006.258.00:41:24.67#ibcon#flushed, iclass 22, count 2 2006.258.00:41:24.67#ibcon#about to write, iclass 22, count 2 2006.258.00:41:24.67#ibcon#wrote, iclass 22, count 2 2006.258.00:41:24.67#ibcon#about to read 3, iclass 22, count 2 2006.258.00:41:24.70#ibcon#read 3, iclass 22, count 2 2006.258.00:41:24.70#ibcon#about to read 4, iclass 22, count 2 2006.258.00:41:24.70#ibcon#read 4, iclass 22, count 2 2006.258.00:41:24.70#ibcon#about to read 5, iclass 22, count 2 2006.258.00:41:24.70#ibcon#read 5, iclass 22, count 2 2006.258.00:41:24.70#ibcon#about to read 6, iclass 22, count 2 2006.258.00:41:24.70#ibcon#read 6, iclass 22, count 2 2006.258.00:41:24.70#ibcon#end of sib2, iclass 22, count 2 2006.258.00:41:24.70#ibcon#*after write, iclass 22, count 2 2006.258.00:41:24.70#ibcon#*before return 0, iclass 22, count 2 2006.258.00:41:24.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:24.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:24.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.00:41:24.70#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:24.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:24.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:24.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:24.82#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:41:24.82#ibcon#first serial, iclass 22, count 0 2006.258.00:41:24.82#ibcon#enter sib2, iclass 22, count 0 2006.258.00:41:24.82#ibcon#flushed, iclass 22, count 0 2006.258.00:41:24.82#ibcon#about to write, iclass 22, count 0 2006.258.00:41:24.82#ibcon#wrote, iclass 22, count 0 2006.258.00:41:24.82#ibcon#about to read 3, iclass 22, count 0 2006.258.00:41:24.84#ibcon#read 3, iclass 22, count 0 2006.258.00:41:24.84#ibcon#about to read 4, iclass 22, count 0 2006.258.00:41:24.84#ibcon#read 4, iclass 22, count 0 2006.258.00:41:24.84#ibcon#about to read 5, iclass 22, count 0 2006.258.00:41:24.84#ibcon#read 5, iclass 22, count 0 2006.258.00:41:24.84#ibcon#about to read 6, iclass 22, count 0 2006.258.00:41:24.84#ibcon#read 6, iclass 22, count 0 2006.258.00:41:24.84#ibcon#end of sib2, iclass 22, count 0 2006.258.00:41:24.84#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:41:24.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:41:24.84#ibcon#[25=USB\r\n] 2006.258.00:41:24.84#ibcon#*before write, iclass 22, count 0 2006.258.00:41:24.84#ibcon#enter sib2, iclass 22, count 0 2006.258.00:41:24.84#ibcon#flushed, iclass 22, count 0 2006.258.00:41:24.84#ibcon#about to write, iclass 22, count 0 2006.258.00:41:24.84#ibcon#wrote, iclass 22, count 0 2006.258.00:41:24.84#ibcon#about to read 3, iclass 22, count 0 2006.258.00:41:24.87#ibcon#read 3, iclass 22, count 0 2006.258.00:41:24.87#ibcon#about to read 4, iclass 22, count 0 2006.258.00:41:24.87#ibcon#read 4, iclass 22, count 0 2006.258.00:41:24.87#ibcon#about to read 5, iclass 22, count 0 2006.258.00:41:24.87#ibcon#read 5, iclass 22, count 0 2006.258.00:41:24.87#ibcon#about to read 6, iclass 22, count 0 2006.258.00:41:24.87#ibcon#read 6, iclass 22, count 0 2006.258.00:41:24.87#ibcon#end of sib2, iclass 22, count 0 2006.258.00:41:24.87#ibcon#*after write, iclass 22, count 0 2006.258.00:41:24.87#ibcon#*before return 0, iclass 22, count 0 2006.258.00:41:24.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:24.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:24.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:41:24.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:41:24.87$vck44/valo=6,814.99 2006.258.00:41:24.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.00:41:24.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.00:41:24.87#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:24.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:24.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:24.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:24.87#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:41:24.87#ibcon#first serial, iclass 24, count 0 2006.258.00:41:24.87#ibcon#enter sib2, iclass 24, count 0 2006.258.00:41:24.88#ibcon#flushed, iclass 24, count 0 2006.258.00:41:24.88#ibcon#about to write, iclass 24, count 0 2006.258.00:41:24.88#ibcon#wrote, iclass 24, count 0 2006.258.00:41:24.88#ibcon#about to read 3, iclass 24, count 0 2006.258.00:41:24.89#ibcon#read 3, iclass 24, count 0 2006.258.00:41:24.89#ibcon#about to read 4, iclass 24, count 0 2006.258.00:41:24.89#ibcon#read 4, iclass 24, count 0 2006.258.00:41:24.89#ibcon#about to read 5, iclass 24, count 0 2006.258.00:41:24.89#ibcon#read 5, iclass 24, count 0 2006.258.00:41:24.89#ibcon#about to read 6, iclass 24, count 0 2006.258.00:41:24.89#ibcon#read 6, iclass 24, count 0 2006.258.00:41:24.89#ibcon#end of sib2, iclass 24, count 0 2006.258.00:41:24.89#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:41:24.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:41:24.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:41:24.89#ibcon#*before write, iclass 24, count 0 2006.258.00:41:24.89#ibcon#enter sib2, iclass 24, count 0 2006.258.00:41:24.89#ibcon#flushed, iclass 24, count 0 2006.258.00:41:24.89#ibcon#about to write, iclass 24, count 0 2006.258.00:41:24.89#ibcon#wrote, iclass 24, count 0 2006.258.00:41:24.89#ibcon#about to read 3, iclass 24, count 0 2006.258.00:41:24.93#ibcon#read 3, iclass 24, count 0 2006.258.00:41:24.93#ibcon#about to read 4, iclass 24, count 0 2006.258.00:41:24.93#ibcon#read 4, iclass 24, count 0 2006.258.00:41:24.93#ibcon#about to read 5, iclass 24, count 0 2006.258.00:41:24.93#ibcon#read 5, iclass 24, count 0 2006.258.00:41:24.93#ibcon#about to read 6, iclass 24, count 0 2006.258.00:41:24.93#ibcon#read 6, iclass 24, count 0 2006.258.00:41:24.93#ibcon#end of sib2, iclass 24, count 0 2006.258.00:41:24.93#ibcon#*after write, iclass 24, count 0 2006.258.00:41:24.93#ibcon#*before return 0, iclass 24, count 0 2006.258.00:41:24.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:24.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:24.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:41:24.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:41:24.93$vck44/va=6,4 2006.258.00:41:24.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.00:41:24.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.00:41:24.93#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:24.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:24.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:24.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:24.99#ibcon#enter wrdev, iclass 26, count 2 2006.258.00:41:24.99#ibcon#first serial, iclass 26, count 2 2006.258.00:41:24.99#ibcon#enter sib2, iclass 26, count 2 2006.258.00:41:24.99#ibcon#flushed, iclass 26, count 2 2006.258.00:41:24.99#ibcon#about to write, iclass 26, count 2 2006.258.00:41:24.99#ibcon#wrote, iclass 26, count 2 2006.258.00:41:24.99#ibcon#about to read 3, iclass 26, count 2 2006.258.00:41:25.01#ibcon#read 3, iclass 26, count 2 2006.258.00:41:25.01#ibcon#about to read 4, iclass 26, count 2 2006.258.00:41:25.01#ibcon#read 4, iclass 26, count 2 2006.258.00:41:25.01#ibcon#about to read 5, iclass 26, count 2 2006.258.00:41:25.01#ibcon#read 5, iclass 26, count 2 2006.258.00:41:25.01#ibcon#about to read 6, iclass 26, count 2 2006.258.00:41:25.01#ibcon#read 6, iclass 26, count 2 2006.258.00:41:25.01#ibcon#end of sib2, iclass 26, count 2 2006.258.00:41:25.01#ibcon#*mode == 0, iclass 26, count 2 2006.258.00:41:25.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.00:41:25.01#ibcon#[25=AT06-04\r\n] 2006.258.00:41:25.01#ibcon#*before write, iclass 26, count 2 2006.258.00:41:25.01#ibcon#enter sib2, iclass 26, count 2 2006.258.00:41:25.01#ibcon#flushed, iclass 26, count 2 2006.258.00:41:25.01#ibcon#about to write, iclass 26, count 2 2006.258.00:41:25.01#ibcon#wrote, iclass 26, count 2 2006.258.00:41:25.01#ibcon#about to read 3, iclass 26, count 2 2006.258.00:41:25.04#ibcon#read 3, iclass 26, count 2 2006.258.00:41:25.04#ibcon#about to read 4, iclass 26, count 2 2006.258.00:41:25.04#ibcon#read 4, iclass 26, count 2 2006.258.00:41:25.04#ibcon#about to read 5, iclass 26, count 2 2006.258.00:41:25.04#ibcon#read 5, iclass 26, count 2 2006.258.00:41:25.04#ibcon#about to read 6, iclass 26, count 2 2006.258.00:41:25.04#ibcon#read 6, iclass 26, count 2 2006.258.00:41:25.04#ibcon#end of sib2, iclass 26, count 2 2006.258.00:41:25.04#ibcon#*after write, iclass 26, count 2 2006.258.00:41:25.04#ibcon#*before return 0, iclass 26, count 2 2006.258.00:41:25.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:25.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:25.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.00:41:25.04#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:25.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:25.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:25.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:25.16#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:41:25.16#ibcon#first serial, iclass 26, count 0 2006.258.00:41:25.16#ibcon#enter sib2, iclass 26, count 0 2006.258.00:41:25.16#ibcon#flushed, iclass 26, count 0 2006.258.00:41:25.16#ibcon#about to write, iclass 26, count 0 2006.258.00:41:25.16#ibcon#wrote, iclass 26, count 0 2006.258.00:41:25.16#ibcon#about to read 3, iclass 26, count 0 2006.258.00:41:25.18#ibcon#read 3, iclass 26, count 0 2006.258.00:41:25.18#ibcon#about to read 4, iclass 26, count 0 2006.258.00:41:25.18#ibcon#read 4, iclass 26, count 0 2006.258.00:41:25.18#ibcon#about to read 5, iclass 26, count 0 2006.258.00:41:25.18#ibcon#read 5, iclass 26, count 0 2006.258.00:41:25.18#ibcon#about to read 6, iclass 26, count 0 2006.258.00:41:25.18#ibcon#read 6, iclass 26, count 0 2006.258.00:41:25.18#ibcon#end of sib2, iclass 26, count 0 2006.258.00:41:25.18#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:41:25.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:41:25.18#ibcon#[25=USB\r\n] 2006.258.00:41:25.18#ibcon#*before write, iclass 26, count 0 2006.258.00:41:25.18#ibcon#enter sib2, iclass 26, count 0 2006.258.00:41:25.18#ibcon#flushed, iclass 26, count 0 2006.258.00:41:25.18#ibcon#about to write, iclass 26, count 0 2006.258.00:41:25.18#ibcon#wrote, iclass 26, count 0 2006.258.00:41:25.18#ibcon#about to read 3, iclass 26, count 0 2006.258.00:41:25.21#ibcon#read 3, iclass 26, count 0 2006.258.00:41:25.21#ibcon#about to read 4, iclass 26, count 0 2006.258.00:41:25.21#ibcon#read 4, iclass 26, count 0 2006.258.00:41:25.21#ibcon#about to read 5, iclass 26, count 0 2006.258.00:41:25.21#ibcon#read 5, iclass 26, count 0 2006.258.00:41:25.21#ibcon#about to read 6, iclass 26, count 0 2006.258.00:41:25.21#ibcon#read 6, iclass 26, count 0 2006.258.00:41:25.21#ibcon#end of sib2, iclass 26, count 0 2006.258.00:41:25.21#ibcon#*after write, iclass 26, count 0 2006.258.00:41:25.21#ibcon#*before return 0, iclass 26, count 0 2006.258.00:41:25.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:25.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:25.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:41:25.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:41:25.21$vck44/valo=7,864.99 2006.258.00:41:25.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.00:41:25.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.00:41:25.21#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:25.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:25.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:25.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:25.22#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:41:25.22#ibcon#first serial, iclass 28, count 0 2006.258.00:41:25.22#ibcon#enter sib2, iclass 28, count 0 2006.258.00:41:25.22#ibcon#flushed, iclass 28, count 0 2006.258.00:41:25.22#ibcon#about to write, iclass 28, count 0 2006.258.00:41:25.22#ibcon#wrote, iclass 28, count 0 2006.258.00:41:25.22#ibcon#about to read 3, iclass 28, count 0 2006.258.00:41:25.23#ibcon#read 3, iclass 28, count 0 2006.258.00:41:25.23#ibcon#about to read 4, iclass 28, count 0 2006.258.00:41:25.23#ibcon#read 4, iclass 28, count 0 2006.258.00:41:25.23#ibcon#about to read 5, iclass 28, count 0 2006.258.00:41:25.23#ibcon#read 5, iclass 28, count 0 2006.258.00:41:25.23#ibcon#about to read 6, iclass 28, count 0 2006.258.00:41:25.23#ibcon#read 6, iclass 28, count 0 2006.258.00:41:25.23#ibcon#end of sib2, iclass 28, count 0 2006.258.00:41:25.23#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:41:25.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:41:25.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:41:25.23#ibcon#*before write, iclass 28, count 0 2006.258.00:41:25.23#ibcon#enter sib2, iclass 28, count 0 2006.258.00:41:25.23#ibcon#flushed, iclass 28, count 0 2006.258.00:41:25.23#ibcon#about to write, iclass 28, count 0 2006.258.00:41:25.23#ibcon#wrote, iclass 28, count 0 2006.258.00:41:25.23#ibcon#about to read 3, iclass 28, count 0 2006.258.00:41:25.27#ibcon#read 3, iclass 28, count 0 2006.258.00:41:25.27#ibcon#about to read 4, iclass 28, count 0 2006.258.00:41:25.27#ibcon#read 4, iclass 28, count 0 2006.258.00:41:25.27#ibcon#about to read 5, iclass 28, count 0 2006.258.00:41:25.27#ibcon#read 5, iclass 28, count 0 2006.258.00:41:25.27#ibcon#about to read 6, iclass 28, count 0 2006.258.00:41:25.27#ibcon#read 6, iclass 28, count 0 2006.258.00:41:25.27#ibcon#end of sib2, iclass 28, count 0 2006.258.00:41:25.27#ibcon#*after write, iclass 28, count 0 2006.258.00:41:25.27#ibcon#*before return 0, iclass 28, count 0 2006.258.00:41:25.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:25.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:25.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:41:25.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:41:25.27$vck44/va=7,4 2006.258.00:41:25.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.00:41:25.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.00:41:25.27#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:25.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:25.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:25.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:25.33#ibcon#enter wrdev, iclass 30, count 2 2006.258.00:41:25.33#ibcon#first serial, iclass 30, count 2 2006.258.00:41:25.33#ibcon#enter sib2, iclass 30, count 2 2006.258.00:41:25.33#ibcon#flushed, iclass 30, count 2 2006.258.00:41:25.33#ibcon#about to write, iclass 30, count 2 2006.258.00:41:25.33#ibcon#wrote, iclass 30, count 2 2006.258.00:41:25.33#ibcon#about to read 3, iclass 30, count 2 2006.258.00:41:25.35#ibcon#read 3, iclass 30, count 2 2006.258.00:41:25.35#ibcon#about to read 4, iclass 30, count 2 2006.258.00:41:25.35#ibcon#read 4, iclass 30, count 2 2006.258.00:41:25.35#ibcon#about to read 5, iclass 30, count 2 2006.258.00:41:25.35#ibcon#read 5, iclass 30, count 2 2006.258.00:41:25.35#ibcon#about to read 6, iclass 30, count 2 2006.258.00:41:25.35#ibcon#read 6, iclass 30, count 2 2006.258.00:41:25.35#ibcon#end of sib2, iclass 30, count 2 2006.258.00:41:25.35#ibcon#*mode == 0, iclass 30, count 2 2006.258.00:41:25.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.00:41:25.35#ibcon#[25=AT07-04\r\n] 2006.258.00:41:25.35#ibcon#*before write, iclass 30, count 2 2006.258.00:41:25.35#ibcon#enter sib2, iclass 30, count 2 2006.258.00:41:25.35#ibcon#flushed, iclass 30, count 2 2006.258.00:41:25.35#ibcon#about to write, iclass 30, count 2 2006.258.00:41:25.35#ibcon#wrote, iclass 30, count 2 2006.258.00:41:25.35#ibcon#about to read 3, iclass 30, count 2 2006.258.00:41:25.38#ibcon#read 3, iclass 30, count 2 2006.258.00:41:25.42#ibcon#about to read 4, iclass 30, count 2 2006.258.00:41:25.42#ibcon#read 4, iclass 30, count 2 2006.258.00:41:25.42#ibcon#about to read 5, iclass 30, count 2 2006.258.00:41:25.42#ibcon#read 5, iclass 30, count 2 2006.258.00:41:25.42#ibcon#about to read 6, iclass 30, count 2 2006.258.00:41:25.42#ibcon#read 6, iclass 30, count 2 2006.258.00:41:25.42#ibcon#end of sib2, iclass 30, count 2 2006.258.00:41:25.42#ibcon#*after write, iclass 30, count 2 2006.258.00:41:25.42#ibcon#*before return 0, iclass 30, count 2 2006.258.00:41:25.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:25.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:25.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.00:41:25.42#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:25.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:25.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:25.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:25.53#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:41:25.53#ibcon#first serial, iclass 30, count 0 2006.258.00:41:25.53#ibcon#enter sib2, iclass 30, count 0 2006.258.00:41:25.53#ibcon#flushed, iclass 30, count 0 2006.258.00:41:25.53#ibcon#about to write, iclass 30, count 0 2006.258.00:41:25.53#ibcon#wrote, iclass 30, count 0 2006.258.00:41:25.53#ibcon#about to read 3, iclass 30, count 0 2006.258.00:41:25.55#ibcon#read 3, iclass 30, count 0 2006.258.00:41:25.55#ibcon#about to read 4, iclass 30, count 0 2006.258.00:41:25.55#ibcon#read 4, iclass 30, count 0 2006.258.00:41:25.55#ibcon#about to read 5, iclass 30, count 0 2006.258.00:41:25.55#ibcon#read 5, iclass 30, count 0 2006.258.00:41:25.55#ibcon#about to read 6, iclass 30, count 0 2006.258.00:41:25.55#ibcon#read 6, iclass 30, count 0 2006.258.00:41:25.55#ibcon#end of sib2, iclass 30, count 0 2006.258.00:41:25.55#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:41:25.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:41:25.55#ibcon#[25=USB\r\n] 2006.258.00:41:25.55#ibcon#*before write, iclass 30, count 0 2006.258.00:41:25.55#ibcon#enter sib2, iclass 30, count 0 2006.258.00:41:25.55#ibcon#flushed, iclass 30, count 0 2006.258.00:41:25.55#ibcon#about to write, iclass 30, count 0 2006.258.00:41:25.55#ibcon#wrote, iclass 30, count 0 2006.258.00:41:25.55#ibcon#about to read 3, iclass 30, count 0 2006.258.00:41:25.58#ibcon#read 3, iclass 30, count 0 2006.258.00:41:25.58#ibcon#about to read 4, iclass 30, count 0 2006.258.00:41:25.58#ibcon#read 4, iclass 30, count 0 2006.258.00:41:25.58#ibcon#about to read 5, iclass 30, count 0 2006.258.00:41:25.58#ibcon#read 5, iclass 30, count 0 2006.258.00:41:25.58#ibcon#about to read 6, iclass 30, count 0 2006.258.00:41:25.58#ibcon#read 6, iclass 30, count 0 2006.258.00:41:25.58#ibcon#end of sib2, iclass 30, count 0 2006.258.00:41:25.58#ibcon#*after write, iclass 30, count 0 2006.258.00:41:25.58#ibcon#*before return 0, iclass 30, count 0 2006.258.00:41:25.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:25.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:25.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:41:25.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:41:25.58$vck44/valo=8,884.99 2006.258.00:41:25.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.258.00:41:25.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.258.00:41:25.58#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:25.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:25.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:25.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:25.59#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:41:25.59#ibcon#first serial, iclass 32, count 0 2006.258.00:41:25.59#ibcon#enter sib2, iclass 32, count 0 2006.258.00:41:25.59#ibcon#flushed, iclass 32, count 0 2006.258.00:41:25.59#ibcon#about to write, iclass 32, count 0 2006.258.00:41:25.59#ibcon#wrote, iclass 32, count 0 2006.258.00:41:25.59#ibcon#about to read 3, iclass 32, count 0 2006.258.00:41:25.60#ibcon#read 3, iclass 32, count 0 2006.258.00:41:25.60#ibcon#about to read 4, iclass 32, count 0 2006.258.00:41:25.60#ibcon#read 4, iclass 32, count 0 2006.258.00:41:25.60#ibcon#about to read 5, iclass 32, count 0 2006.258.00:41:25.60#ibcon#read 5, iclass 32, count 0 2006.258.00:41:25.60#ibcon#about to read 6, iclass 32, count 0 2006.258.00:41:25.60#ibcon#read 6, iclass 32, count 0 2006.258.00:41:25.60#ibcon#end of sib2, iclass 32, count 0 2006.258.00:41:25.60#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:41:25.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:41:25.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:41:25.60#ibcon#*before write, iclass 32, count 0 2006.258.00:41:25.60#ibcon#enter sib2, iclass 32, count 0 2006.258.00:41:25.60#ibcon#flushed, iclass 32, count 0 2006.258.00:41:25.60#ibcon#about to write, iclass 32, count 0 2006.258.00:41:25.60#ibcon#wrote, iclass 32, count 0 2006.258.00:41:25.60#ibcon#about to read 3, iclass 32, count 0 2006.258.00:41:25.64#ibcon#read 3, iclass 32, count 0 2006.258.00:41:25.64#ibcon#about to read 4, iclass 32, count 0 2006.258.00:41:25.64#ibcon#read 4, iclass 32, count 0 2006.258.00:41:25.64#ibcon#about to read 5, iclass 32, count 0 2006.258.00:41:25.64#ibcon#read 5, iclass 32, count 0 2006.258.00:41:25.64#ibcon#about to read 6, iclass 32, count 0 2006.258.00:41:25.64#ibcon#read 6, iclass 32, count 0 2006.258.00:41:25.64#ibcon#end of sib2, iclass 32, count 0 2006.258.00:41:25.64#ibcon#*after write, iclass 32, count 0 2006.258.00:41:25.64#ibcon#*before return 0, iclass 32, count 0 2006.258.00:41:25.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:25.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:25.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:41:25.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:41:25.64$vck44/va=8,4 2006.258.00:41:25.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.258.00:41:25.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.258.00:41:25.64#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:25.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:41:25.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:41:25.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:41:25.70#ibcon#enter wrdev, iclass 34, count 2 2006.258.00:41:25.70#ibcon#first serial, iclass 34, count 2 2006.258.00:41:25.70#ibcon#enter sib2, iclass 34, count 2 2006.258.00:41:25.70#ibcon#flushed, iclass 34, count 2 2006.258.00:41:25.70#ibcon#about to write, iclass 34, count 2 2006.258.00:41:25.70#ibcon#wrote, iclass 34, count 2 2006.258.00:41:25.70#ibcon#about to read 3, iclass 34, count 2 2006.258.00:41:25.72#ibcon#read 3, iclass 34, count 2 2006.258.00:41:25.72#ibcon#about to read 4, iclass 34, count 2 2006.258.00:41:25.72#ibcon#read 4, iclass 34, count 2 2006.258.00:41:25.72#ibcon#about to read 5, iclass 34, count 2 2006.258.00:41:25.72#ibcon#read 5, iclass 34, count 2 2006.258.00:41:25.72#ibcon#about to read 6, iclass 34, count 2 2006.258.00:41:25.72#ibcon#read 6, iclass 34, count 2 2006.258.00:41:25.72#ibcon#end of sib2, iclass 34, count 2 2006.258.00:41:25.72#ibcon#*mode == 0, iclass 34, count 2 2006.258.00:41:25.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.258.00:41:25.72#ibcon#[25=AT08-04\r\n] 2006.258.00:41:25.72#ibcon#*before write, iclass 34, count 2 2006.258.00:41:25.72#ibcon#enter sib2, iclass 34, count 2 2006.258.00:41:25.72#ibcon#flushed, iclass 34, count 2 2006.258.00:41:25.72#ibcon#about to write, iclass 34, count 2 2006.258.00:41:25.72#ibcon#wrote, iclass 34, count 2 2006.258.00:41:25.72#ibcon#about to read 3, iclass 34, count 2 2006.258.00:41:25.75#ibcon#read 3, iclass 34, count 2 2006.258.00:41:25.75#ibcon#about to read 4, iclass 34, count 2 2006.258.00:41:25.75#ibcon#read 4, iclass 34, count 2 2006.258.00:41:25.75#ibcon#about to read 5, iclass 34, count 2 2006.258.00:41:25.75#ibcon#read 5, iclass 34, count 2 2006.258.00:41:25.75#ibcon#about to read 6, iclass 34, count 2 2006.258.00:41:25.75#ibcon#read 6, iclass 34, count 2 2006.258.00:41:25.75#ibcon#end of sib2, iclass 34, count 2 2006.258.00:41:25.75#ibcon#*after write, iclass 34, count 2 2006.258.00:41:25.75#ibcon#*before return 0, iclass 34, count 2 2006.258.00:41:25.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:41:25.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.258.00:41:25.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.258.00:41:25.75#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:25.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:41:25.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:41:25.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:41:25.87#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:41:25.87#ibcon#first serial, iclass 34, count 0 2006.258.00:41:25.87#ibcon#enter sib2, iclass 34, count 0 2006.258.00:41:25.87#ibcon#flushed, iclass 34, count 0 2006.258.00:41:25.87#ibcon#about to write, iclass 34, count 0 2006.258.00:41:25.87#ibcon#wrote, iclass 34, count 0 2006.258.00:41:25.87#ibcon#about to read 3, iclass 34, count 0 2006.258.00:41:25.89#ibcon#read 3, iclass 34, count 0 2006.258.00:41:25.89#ibcon#about to read 4, iclass 34, count 0 2006.258.00:41:25.89#ibcon#read 4, iclass 34, count 0 2006.258.00:41:25.89#ibcon#about to read 5, iclass 34, count 0 2006.258.00:41:25.89#ibcon#read 5, iclass 34, count 0 2006.258.00:41:25.89#ibcon#about to read 6, iclass 34, count 0 2006.258.00:41:25.89#ibcon#read 6, iclass 34, count 0 2006.258.00:41:25.89#ibcon#end of sib2, iclass 34, count 0 2006.258.00:41:25.89#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:41:25.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:41:25.89#ibcon#[25=USB\r\n] 2006.258.00:41:25.89#ibcon#*before write, iclass 34, count 0 2006.258.00:41:25.89#ibcon#enter sib2, iclass 34, count 0 2006.258.00:41:25.89#ibcon#flushed, iclass 34, count 0 2006.258.00:41:25.89#ibcon#about to write, iclass 34, count 0 2006.258.00:41:25.89#ibcon#wrote, iclass 34, count 0 2006.258.00:41:25.89#ibcon#about to read 3, iclass 34, count 0 2006.258.00:41:25.92#ibcon#read 3, iclass 34, count 0 2006.258.00:41:25.92#ibcon#about to read 4, iclass 34, count 0 2006.258.00:41:25.92#ibcon#read 4, iclass 34, count 0 2006.258.00:41:25.92#ibcon#about to read 5, iclass 34, count 0 2006.258.00:41:25.92#ibcon#read 5, iclass 34, count 0 2006.258.00:41:25.92#ibcon#about to read 6, iclass 34, count 0 2006.258.00:41:25.92#ibcon#read 6, iclass 34, count 0 2006.258.00:41:25.92#ibcon#end of sib2, iclass 34, count 0 2006.258.00:41:25.92#ibcon#*after write, iclass 34, count 0 2006.258.00:41:25.92#ibcon#*before return 0, iclass 34, count 0 2006.258.00:41:25.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:41:25.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.258.00:41:25.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:41:25.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:41:25.92$vck44/vblo=1,629.99 2006.258.00:41:25.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.258.00:41:25.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.258.00:41:25.92#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:25.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:41:25.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:41:25.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:41:25.92#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:41:25.92#ibcon#first serial, iclass 36, count 0 2006.258.00:41:25.93#ibcon#enter sib2, iclass 36, count 0 2006.258.00:41:25.93#ibcon#flushed, iclass 36, count 0 2006.258.00:41:25.93#ibcon#about to write, iclass 36, count 0 2006.258.00:41:25.93#ibcon#wrote, iclass 36, count 0 2006.258.00:41:25.93#ibcon#about to read 3, iclass 36, count 0 2006.258.00:41:25.94#ibcon#read 3, iclass 36, count 0 2006.258.00:41:25.94#ibcon#about to read 4, iclass 36, count 0 2006.258.00:41:25.94#ibcon#read 4, iclass 36, count 0 2006.258.00:41:25.94#ibcon#about to read 5, iclass 36, count 0 2006.258.00:41:25.94#ibcon#read 5, iclass 36, count 0 2006.258.00:41:25.94#ibcon#about to read 6, iclass 36, count 0 2006.258.00:41:25.94#ibcon#read 6, iclass 36, count 0 2006.258.00:41:25.94#ibcon#end of sib2, iclass 36, count 0 2006.258.00:41:25.94#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:41:25.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:41:25.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:41:25.94#ibcon#*before write, iclass 36, count 0 2006.258.00:41:25.94#ibcon#enter sib2, iclass 36, count 0 2006.258.00:41:25.94#ibcon#flushed, iclass 36, count 0 2006.258.00:41:25.94#ibcon#about to write, iclass 36, count 0 2006.258.00:41:25.94#ibcon#wrote, iclass 36, count 0 2006.258.00:41:25.94#ibcon#about to read 3, iclass 36, count 0 2006.258.00:41:25.98#ibcon#read 3, iclass 36, count 0 2006.258.00:41:25.98#ibcon#about to read 4, iclass 36, count 0 2006.258.00:41:25.98#ibcon#read 4, iclass 36, count 0 2006.258.00:41:25.98#ibcon#about to read 5, iclass 36, count 0 2006.258.00:41:25.98#ibcon#read 5, iclass 36, count 0 2006.258.00:41:25.98#ibcon#about to read 6, iclass 36, count 0 2006.258.00:41:25.98#ibcon#read 6, iclass 36, count 0 2006.258.00:41:25.98#ibcon#end of sib2, iclass 36, count 0 2006.258.00:41:25.98#ibcon#*after write, iclass 36, count 0 2006.258.00:41:25.98#ibcon#*before return 0, iclass 36, count 0 2006.258.00:41:25.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:41:25.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.258.00:41:25.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:41:25.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:41:25.98$vck44/vb=1,4 2006.258.00:41:25.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.258.00:41:25.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.258.00:41:25.98#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:25.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:41:25.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:41:25.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:41:25.99#ibcon#enter wrdev, iclass 38, count 2 2006.258.00:41:25.99#ibcon#first serial, iclass 38, count 2 2006.258.00:41:25.99#ibcon#enter sib2, iclass 38, count 2 2006.258.00:41:25.99#ibcon#flushed, iclass 38, count 2 2006.258.00:41:25.99#ibcon#about to write, iclass 38, count 2 2006.258.00:41:25.99#ibcon#wrote, iclass 38, count 2 2006.258.00:41:25.99#ibcon#about to read 3, iclass 38, count 2 2006.258.00:41:26.00#ibcon#read 3, iclass 38, count 2 2006.258.00:41:26.00#ibcon#about to read 4, iclass 38, count 2 2006.258.00:41:26.00#ibcon#read 4, iclass 38, count 2 2006.258.00:41:26.00#ibcon#about to read 5, iclass 38, count 2 2006.258.00:41:26.00#ibcon#read 5, iclass 38, count 2 2006.258.00:41:26.00#ibcon#about to read 6, iclass 38, count 2 2006.258.00:41:26.00#ibcon#read 6, iclass 38, count 2 2006.258.00:41:26.00#ibcon#end of sib2, iclass 38, count 2 2006.258.00:41:26.00#ibcon#*mode == 0, iclass 38, count 2 2006.258.00:41:26.00#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.258.00:41:26.00#ibcon#[27=AT01-04\r\n] 2006.258.00:41:26.00#ibcon#*before write, iclass 38, count 2 2006.258.00:41:26.00#ibcon#enter sib2, iclass 38, count 2 2006.258.00:41:26.00#ibcon#flushed, iclass 38, count 2 2006.258.00:41:26.00#ibcon#about to write, iclass 38, count 2 2006.258.00:41:26.00#ibcon#wrote, iclass 38, count 2 2006.258.00:41:26.00#ibcon#about to read 3, iclass 38, count 2 2006.258.00:41:26.03#ibcon#read 3, iclass 38, count 2 2006.258.00:41:26.03#ibcon#about to read 4, iclass 38, count 2 2006.258.00:41:26.03#ibcon#read 4, iclass 38, count 2 2006.258.00:41:26.03#ibcon#about to read 5, iclass 38, count 2 2006.258.00:41:26.03#ibcon#read 5, iclass 38, count 2 2006.258.00:41:26.03#ibcon#about to read 6, iclass 38, count 2 2006.258.00:41:26.03#ibcon#read 6, iclass 38, count 2 2006.258.00:41:26.03#ibcon#end of sib2, iclass 38, count 2 2006.258.00:41:26.03#ibcon#*after write, iclass 38, count 2 2006.258.00:41:26.03#ibcon#*before return 0, iclass 38, count 2 2006.258.00:41:26.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:41:26.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.258.00:41:26.03#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.258.00:41:26.03#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:26.03#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:41:26.15#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:41:26.15#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:41:26.15#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:41:26.15#ibcon#first serial, iclass 38, count 0 2006.258.00:41:26.15#ibcon#enter sib2, iclass 38, count 0 2006.258.00:41:26.15#ibcon#flushed, iclass 38, count 0 2006.258.00:41:26.15#ibcon#about to write, iclass 38, count 0 2006.258.00:41:26.15#ibcon#wrote, iclass 38, count 0 2006.258.00:41:26.15#ibcon#about to read 3, iclass 38, count 0 2006.258.00:41:26.17#ibcon#read 3, iclass 38, count 0 2006.258.00:41:26.17#ibcon#about to read 4, iclass 38, count 0 2006.258.00:41:26.17#ibcon#read 4, iclass 38, count 0 2006.258.00:41:26.17#ibcon#about to read 5, iclass 38, count 0 2006.258.00:41:26.17#ibcon#read 5, iclass 38, count 0 2006.258.00:41:26.17#ibcon#about to read 6, iclass 38, count 0 2006.258.00:41:26.17#ibcon#read 6, iclass 38, count 0 2006.258.00:41:26.17#ibcon#end of sib2, iclass 38, count 0 2006.258.00:41:26.17#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:41:26.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:41:26.17#ibcon#[27=USB\r\n] 2006.258.00:41:26.17#ibcon#*before write, iclass 38, count 0 2006.258.00:41:26.17#ibcon#enter sib2, iclass 38, count 0 2006.258.00:41:26.17#ibcon#flushed, iclass 38, count 0 2006.258.00:41:26.17#ibcon#about to write, iclass 38, count 0 2006.258.00:41:26.17#ibcon#wrote, iclass 38, count 0 2006.258.00:41:26.17#ibcon#about to read 3, iclass 38, count 0 2006.258.00:41:26.20#ibcon#read 3, iclass 38, count 0 2006.258.00:41:26.20#ibcon#about to read 4, iclass 38, count 0 2006.258.00:41:26.20#ibcon#read 4, iclass 38, count 0 2006.258.00:41:26.20#ibcon#about to read 5, iclass 38, count 0 2006.258.00:41:26.20#ibcon#read 5, iclass 38, count 0 2006.258.00:41:26.20#ibcon#about to read 6, iclass 38, count 0 2006.258.00:41:26.20#ibcon#read 6, iclass 38, count 0 2006.258.00:41:26.20#ibcon#end of sib2, iclass 38, count 0 2006.258.00:41:26.20#ibcon#*after write, iclass 38, count 0 2006.258.00:41:26.20#ibcon#*before return 0, iclass 38, count 0 2006.258.00:41:26.20#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:41:26.20#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.258.00:41:26.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:41:26.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:41:26.20$vck44/vblo=2,634.99 2006.258.00:41:26.20#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.00:41:26.20#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.00:41:26.20#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:26.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:26.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:26.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:26.21#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:41:26.21#ibcon#first serial, iclass 40, count 0 2006.258.00:41:26.21#ibcon#enter sib2, iclass 40, count 0 2006.258.00:41:26.21#ibcon#flushed, iclass 40, count 0 2006.258.00:41:26.21#ibcon#about to write, iclass 40, count 0 2006.258.00:41:26.21#ibcon#wrote, iclass 40, count 0 2006.258.00:41:26.21#ibcon#about to read 3, iclass 40, count 0 2006.258.00:41:26.22#ibcon#read 3, iclass 40, count 0 2006.258.00:41:26.22#ibcon#about to read 4, iclass 40, count 0 2006.258.00:41:26.22#ibcon#read 4, iclass 40, count 0 2006.258.00:41:26.22#ibcon#about to read 5, iclass 40, count 0 2006.258.00:41:26.22#ibcon#read 5, iclass 40, count 0 2006.258.00:41:26.22#ibcon#about to read 6, iclass 40, count 0 2006.258.00:41:26.22#ibcon#read 6, iclass 40, count 0 2006.258.00:41:26.22#ibcon#end of sib2, iclass 40, count 0 2006.258.00:41:26.22#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:41:26.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:41:26.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:41:26.22#ibcon#*before write, iclass 40, count 0 2006.258.00:41:26.22#ibcon#enter sib2, iclass 40, count 0 2006.258.00:41:26.22#ibcon#flushed, iclass 40, count 0 2006.258.00:41:26.22#ibcon#about to write, iclass 40, count 0 2006.258.00:41:26.22#ibcon#wrote, iclass 40, count 0 2006.258.00:41:26.22#ibcon#about to read 3, iclass 40, count 0 2006.258.00:41:26.26#ibcon#read 3, iclass 40, count 0 2006.258.00:41:26.26#ibcon#about to read 4, iclass 40, count 0 2006.258.00:41:26.26#ibcon#read 4, iclass 40, count 0 2006.258.00:41:26.26#ibcon#about to read 5, iclass 40, count 0 2006.258.00:41:26.26#ibcon#read 5, iclass 40, count 0 2006.258.00:41:26.26#ibcon#about to read 6, iclass 40, count 0 2006.258.00:41:26.26#ibcon#read 6, iclass 40, count 0 2006.258.00:41:26.26#ibcon#end of sib2, iclass 40, count 0 2006.258.00:41:26.26#ibcon#*after write, iclass 40, count 0 2006.258.00:41:26.26#ibcon#*before return 0, iclass 40, count 0 2006.258.00:41:26.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:26.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.00:41:26.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:41:26.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:41:26.26$vck44/vb=2,5 2006.258.00:41:26.26#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.258.00:41:26.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.258.00:41:26.27#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:26.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:26.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:26.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:26.31#ibcon#enter wrdev, iclass 4, count 2 2006.258.00:41:26.31#ibcon#first serial, iclass 4, count 2 2006.258.00:41:26.31#ibcon#enter sib2, iclass 4, count 2 2006.258.00:41:26.31#ibcon#flushed, iclass 4, count 2 2006.258.00:41:26.31#ibcon#about to write, iclass 4, count 2 2006.258.00:41:26.31#ibcon#wrote, iclass 4, count 2 2006.258.00:41:26.31#ibcon#about to read 3, iclass 4, count 2 2006.258.00:41:26.33#ibcon#read 3, iclass 4, count 2 2006.258.00:41:26.33#ibcon#about to read 4, iclass 4, count 2 2006.258.00:41:26.33#ibcon#read 4, iclass 4, count 2 2006.258.00:41:26.33#ibcon#about to read 5, iclass 4, count 2 2006.258.00:41:26.33#ibcon#read 5, iclass 4, count 2 2006.258.00:41:26.33#ibcon#about to read 6, iclass 4, count 2 2006.258.00:41:26.33#ibcon#read 6, iclass 4, count 2 2006.258.00:41:26.33#ibcon#end of sib2, iclass 4, count 2 2006.258.00:41:26.33#ibcon#*mode == 0, iclass 4, count 2 2006.258.00:41:26.33#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.258.00:41:26.33#ibcon#[27=AT02-05\r\n] 2006.258.00:41:26.33#ibcon#*before write, iclass 4, count 2 2006.258.00:41:26.33#ibcon#enter sib2, iclass 4, count 2 2006.258.00:41:26.33#ibcon#flushed, iclass 4, count 2 2006.258.00:41:26.33#ibcon#about to write, iclass 4, count 2 2006.258.00:41:26.33#ibcon#wrote, iclass 4, count 2 2006.258.00:41:26.33#ibcon#about to read 3, iclass 4, count 2 2006.258.00:41:26.36#ibcon#read 3, iclass 4, count 2 2006.258.00:41:26.36#ibcon#about to read 4, iclass 4, count 2 2006.258.00:41:26.36#ibcon#read 4, iclass 4, count 2 2006.258.00:41:26.36#ibcon#about to read 5, iclass 4, count 2 2006.258.00:41:26.36#ibcon#read 5, iclass 4, count 2 2006.258.00:41:26.36#ibcon#about to read 6, iclass 4, count 2 2006.258.00:41:26.36#ibcon#read 6, iclass 4, count 2 2006.258.00:41:26.36#ibcon#end of sib2, iclass 4, count 2 2006.258.00:41:26.36#ibcon#*after write, iclass 4, count 2 2006.258.00:41:26.44#ibcon#*before return 0, iclass 4, count 2 2006.258.00:41:26.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:26.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.258.00:41:26.44#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.258.00:41:26.44#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:26.44#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:26.56#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:26.56#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:26.56#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:41:26.56#ibcon#first serial, iclass 4, count 0 2006.258.00:41:26.56#ibcon#enter sib2, iclass 4, count 0 2006.258.00:41:26.56#ibcon#flushed, iclass 4, count 0 2006.258.00:41:26.56#ibcon#about to write, iclass 4, count 0 2006.258.00:41:26.56#ibcon#wrote, iclass 4, count 0 2006.258.00:41:26.56#ibcon#about to read 3, iclass 4, count 0 2006.258.00:41:26.58#ibcon#read 3, iclass 4, count 0 2006.258.00:41:26.58#ibcon#about to read 4, iclass 4, count 0 2006.258.00:41:26.58#ibcon#read 4, iclass 4, count 0 2006.258.00:41:26.58#ibcon#about to read 5, iclass 4, count 0 2006.258.00:41:26.58#ibcon#read 5, iclass 4, count 0 2006.258.00:41:26.58#ibcon#about to read 6, iclass 4, count 0 2006.258.00:41:26.58#ibcon#read 6, iclass 4, count 0 2006.258.00:41:26.58#ibcon#end of sib2, iclass 4, count 0 2006.258.00:41:26.58#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:41:26.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:41:26.58#ibcon#[27=USB\r\n] 2006.258.00:41:26.58#ibcon#*before write, iclass 4, count 0 2006.258.00:41:26.58#ibcon#enter sib2, iclass 4, count 0 2006.258.00:41:26.58#ibcon#flushed, iclass 4, count 0 2006.258.00:41:26.58#ibcon#about to write, iclass 4, count 0 2006.258.00:41:26.58#ibcon#wrote, iclass 4, count 0 2006.258.00:41:26.58#ibcon#about to read 3, iclass 4, count 0 2006.258.00:41:26.61#ibcon#read 3, iclass 4, count 0 2006.258.00:41:26.61#ibcon#about to read 4, iclass 4, count 0 2006.258.00:41:26.61#ibcon#read 4, iclass 4, count 0 2006.258.00:41:26.61#ibcon#about to read 5, iclass 4, count 0 2006.258.00:41:26.61#ibcon#read 5, iclass 4, count 0 2006.258.00:41:26.61#ibcon#about to read 6, iclass 4, count 0 2006.258.00:41:26.61#ibcon#read 6, iclass 4, count 0 2006.258.00:41:26.61#ibcon#end of sib2, iclass 4, count 0 2006.258.00:41:26.61#ibcon#*after write, iclass 4, count 0 2006.258.00:41:26.61#ibcon#*before return 0, iclass 4, count 0 2006.258.00:41:26.61#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:26.61#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.258.00:41:26.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:41:26.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:41:26.61$vck44/vblo=3,649.99 2006.258.00:41:26.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.00:41:26.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.00:41:26.61#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:26.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:26.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:26.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:26.62#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:41:26.62#ibcon#first serial, iclass 6, count 0 2006.258.00:41:26.62#ibcon#enter sib2, iclass 6, count 0 2006.258.00:41:26.62#ibcon#flushed, iclass 6, count 0 2006.258.00:41:26.62#ibcon#about to write, iclass 6, count 0 2006.258.00:41:26.62#ibcon#wrote, iclass 6, count 0 2006.258.00:41:26.62#ibcon#about to read 3, iclass 6, count 0 2006.258.00:41:26.63#ibcon#read 3, iclass 6, count 0 2006.258.00:41:26.63#ibcon#about to read 4, iclass 6, count 0 2006.258.00:41:26.63#ibcon#read 4, iclass 6, count 0 2006.258.00:41:26.63#ibcon#about to read 5, iclass 6, count 0 2006.258.00:41:26.63#ibcon#read 5, iclass 6, count 0 2006.258.00:41:26.63#ibcon#about to read 6, iclass 6, count 0 2006.258.00:41:26.63#ibcon#read 6, iclass 6, count 0 2006.258.00:41:26.63#ibcon#end of sib2, iclass 6, count 0 2006.258.00:41:26.63#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:41:26.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:41:26.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:41:26.63#ibcon#*before write, iclass 6, count 0 2006.258.00:41:26.63#ibcon#enter sib2, iclass 6, count 0 2006.258.00:41:26.63#ibcon#flushed, iclass 6, count 0 2006.258.00:41:26.63#ibcon#about to write, iclass 6, count 0 2006.258.00:41:26.63#ibcon#wrote, iclass 6, count 0 2006.258.00:41:26.63#ibcon#about to read 3, iclass 6, count 0 2006.258.00:41:26.67#ibcon#read 3, iclass 6, count 0 2006.258.00:41:26.67#ibcon#about to read 4, iclass 6, count 0 2006.258.00:41:26.67#ibcon#read 4, iclass 6, count 0 2006.258.00:41:26.67#ibcon#about to read 5, iclass 6, count 0 2006.258.00:41:26.67#ibcon#read 5, iclass 6, count 0 2006.258.00:41:26.67#ibcon#about to read 6, iclass 6, count 0 2006.258.00:41:26.67#ibcon#read 6, iclass 6, count 0 2006.258.00:41:26.67#ibcon#end of sib2, iclass 6, count 0 2006.258.00:41:26.67#ibcon#*after write, iclass 6, count 0 2006.258.00:41:26.67#ibcon#*before return 0, iclass 6, count 0 2006.258.00:41:26.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:26.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.00:41:26.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:41:26.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:41:26.67$vck44/vb=3,4 2006.258.00:41:26.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.258.00:41:26.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.258.00:41:26.67#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:26.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:26.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:26.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:26.73#ibcon#enter wrdev, iclass 10, count 2 2006.258.00:41:26.73#ibcon#first serial, iclass 10, count 2 2006.258.00:41:26.73#ibcon#enter sib2, iclass 10, count 2 2006.258.00:41:26.73#ibcon#flushed, iclass 10, count 2 2006.258.00:41:26.73#ibcon#about to write, iclass 10, count 2 2006.258.00:41:26.73#ibcon#wrote, iclass 10, count 2 2006.258.00:41:26.73#ibcon#about to read 3, iclass 10, count 2 2006.258.00:41:26.75#ibcon#read 3, iclass 10, count 2 2006.258.00:41:26.75#ibcon#about to read 4, iclass 10, count 2 2006.258.00:41:26.75#ibcon#read 4, iclass 10, count 2 2006.258.00:41:26.75#ibcon#about to read 5, iclass 10, count 2 2006.258.00:41:26.75#ibcon#read 5, iclass 10, count 2 2006.258.00:41:26.75#ibcon#about to read 6, iclass 10, count 2 2006.258.00:41:26.75#ibcon#read 6, iclass 10, count 2 2006.258.00:41:26.75#ibcon#end of sib2, iclass 10, count 2 2006.258.00:41:26.75#ibcon#*mode == 0, iclass 10, count 2 2006.258.00:41:26.75#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.258.00:41:26.75#ibcon#[27=AT03-04\r\n] 2006.258.00:41:26.75#ibcon#*before write, iclass 10, count 2 2006.258.00:41:26.75#ibcon#enter sib2, iclass 10, count 2 2006.258.00:41:26.75#ibcon#flushed, iclass 10, count 2 2006.258.00:41:26.75#ibcon#about to write, iclass 10, count 2 2006.258.00:41:26.75#ibcon#wrote, iclass 10, count 2 2006.258.00:41:26.75#ibcon#about to read 3, iclass 10, count 2 2006.258.00:41:26.78#ibcon#read 3, iclass 10, count 2 2006.258.00:41:26.78#ibcon#about to read 4, iclass 10, count 2 2006.258.00:41:26.78#ibcon#read 4, iclass 10, count 2 2006.258.00:41:26.78#ibcon#about to read 5, iclass 10, count 2 2006.258.00:41:26.78#ibcon#read 5, iclass 10, count 2 2006.258.00:41:26.78#ibcon#about to read 6, iclass 10, count 2 2006.258.00:41:26.78#ibcon#read 6, iclass 10, count 2 2006.258.00:41:26.78#ibcon#end of sib2, iclass 10, count 2 2006.258.00:41:26.78#ibcon#*after write, iclass 10, count 2 2006.258.00:41:26.78#ibcon#*before return 0, iclass 10, count 2 2006.258.00:41:26.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:26.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.258.00:41:26.78#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.258.00:41:26.78#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:26.78#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:26.90#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:26.90#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:26.90#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:41:26.90#ibcon#first serial, iclass 10, count 0 2006.258.00:41:26.90#ibcon#enter sib2, iclass 10, count 0 2006.258.00:41:26.90#ibcon#flushed, iclass 10, count 0 2006.258.00:41:26.90#ibcon#about to write, iclass 10, count 0 2006.258.00:41:26.90#ibcon#wrote, iclass 10, count 0 2006.258.00:41:26.90#ibcon#about to read 3, iclass 10, count 0 2006.258.00:41:26.92#ibcon#read 3, iclass 10, count 0 2006.258.00:41:26.92#ibcon#about to read 4, iclass 10, count 0 2006.258.00:41:26.92#ibcon#read 4, iclass 10, count 0 2006.258.00:41:26.92#ibcon#about to read 5, iclass 10, count 0 2006.258.00:41:26.92#ibcon#read 5, iclass 10, count 0 2006.258.00:41:26.92#ibcon#about to read 6, iclass 10, count 0 2006.258.00:41:26.92#ibcon#read 6, iclass 10, count 0 2006.258.00:41:26.92#ibcon#end of sib2, iclass 10, count 0 2006.258.00:41:26.92#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:41:26.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:41:26.92#ibcon#[27=USB\r\n] 2006.258.00:41:26.92#ibcon#*before write, iclass 10, count 0 2006.258.00:41:26.92#ibcon#enter sib2, iclass 10, count 0 2006.258.00:41:26.92#ibcon#flushed, iclass 10, count 0 2006.258.00:41:26.92#ibcon#about to write, iclass 10, count 0 2006.258.00:41:26.92#ibcon#wrote, iclass 10, count 0 2006.258.00:41:26.92#ibcon#about to read 3, iclass 10, count 0 2006.258.00:41:26.95#ibcon#read 3, iclass 10, count 0 2006.258.00:41:26.95#ibcon#about to read 4, iclass 10, count 0 2006.258.00:41:26.95#ibcon#read 4, iclass 10, count 0 2006.258.00:41:26.95#ibcon#about to read 5, iclass 10, count 0 2006.258.00:41:26.95#ibcon#read 5, iclass 10, count 0 2006.258.00:41:26.95#ibcon#about to read 6, iclass 10, count 0 2006.258.00:41:26.95#ibcon#read 6, iclass 10, count 0 2006.258.00:41:26.95#ibcon#end of sib2, iclass 10, count 0 2006.258.00:41:26.95#ibcon#*after write, iclass 10, count 0 2006.258.00:41:26.95#ibcon#*before return 0, iclass 10, count 0 2006.258.00:41:26.95#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:26.95#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.258.00:41:26.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:41:26.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:41:26.95$vck44/vblo=4,679.99 2006.258.00:41:26.95#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.00:41:26.95#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.00:41:26.95#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:26.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:26.95#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:26.95#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:26.95#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:41:26.95#ibcon#first serial, iclass 12, count 0 2006.258.00:41:26.95#ibcon#enter sib2, iclass 12, count 0 2006.258.00:41:26.95#ibcon#flushed, iclass 12, count 0 2006.258.00:41:26.96#ibcon#about to write, iclass 12, count 0 2006.258.00:41:26.96#ibcon#wrote, iclass 12, count 0 2006.258.00:41:26.96#ibcon#about to read 3, iclass 12, count 0 2006.258.00:41:26.97#ibcon#read 3, iclass 12, count 0 2006.258.00:41:26.97#ibcon#about to read 4, iclass 12, count 0 2006.258.00:41:26.97#ibcon#read 4, iclass 12, count 0 2006.258.00:41:26.97#ibcon#about to read 5, iclass 12, count 0 2006.258.00:41:26.97#ibcon#read 5, iclass 12, count 0 2006.258.00:41:26.97#ibcon#about to read 6, iclass 12, count 0 2006.258.00:41:26.97#ibcon#read 6, iclass 12, count 0 2006.258.00:41:26.97#ibcon#end of sib2, iclass 12, count 0 2006.258.00:41:26.97#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:41:26.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:41:26.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:41:26.97#ibcon#*before write, iclass 12, count 0 2006.258.00:41:26.97#ibcon#enter sib2, iclass 12, count 0 2006.258.00:41:26.97#ibcon#flushed, iclass 12, count 0 2006.258.00:41:26.97#ibcon#about to write, iclass 12, count 0 2006.258.00:41:26.97#ibcon#wrote, iclass 12, count 0 2006.258.00:41:26.97#ibcon#about to read 3, iclass 12, count 0 2006.258.00:41:27.01#ibcon#read 3, iclass 12, count 0 2006.258.00:41:27.01#ibcon#about to read 4, iclass 12, count 0 2006.258.00:41:27.01#ibcon#read 4, iclass 12, count 0 2006.258.00:41:27.01#ibcon#about to read 5, iclass 12, count 0 2006.258.00:41:27.01#ibcon#read 5, iclass 12, count 0 2006.258.00:41:27.01#ibcon#about to read 6, iclass 12, count 0 2006.258.00:41:27.01#ibcon#read 6, iclass 12, count 0 2006.258.00:41:27.01#ibcon#end of sib2, iclass 12, count 0 2006.258.00:41:27.01#ibcon#*after write, iclass 12, count 0 2006.258.00:41:27.01#ibcon#*before return 0, iclass 12, count 0 2006.258.00:41:27.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:27.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.00:41:27.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:41:27.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:41:27.01$vck44/vb=4,5 2006.258.00:41:27.01#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.258.00:41:27.01#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.258.00:41:27.01#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:27.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:27.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:27.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:27.07#ibcon#enter wrdev, iclass 14, count 2 2006.258.00:41:27.07#ibcon#first serial, iclass 14, count 2 2006.258.00:41:27.07#ibcon#enter sib2, iclass 14, count 2 2006.258.00:41:27.07#ibcon#flushed, iclass 14, count 2 2006.258.00:41:27.07#ibcon#about to write, iclass 14, count 2 2006.258.00:41:27.07#ibcon#wrote, iclass 14, count 2 2006.258.00:41:27.07#ibcon#about to read 3, iclass 14, count 2 2006.258.00:41:27.09#ibcon#read 3, iclass 14, count 2 2006.258.00:41:27.09#ibcon#about to read 4, iclass 14, count 2 2006.258.00:41:27.09#ibcon#read 4, iclass 14, count 2 2006.258.00:41:27.09#ibcon#about to read 5, iclass 14, count 2 2006.258.00:41:27.09#ibcon#read 5, iclass 14, count 2 2006.258.00:41:27.09#ibcon#about to read 6, iclass 14, count 2 2006.258.00:41:27.09#ibcon#read 6, iclass 14, count 2 2006.258.00:41:27.09#ibcon#end of sib2, iclass 14, count 2 2006.258.00:41:27.09#ibcon#*mode == 0, iclass 14, count 2 2006.258.00:41:27.09#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.258.00:41:27.09#ibcon#[27=AT04-05\r\n] 2006.258.00:41:27.09#ibcon#*before write, iclass 14, count 2 2006.258.00:41:27.09#ibcon#enter sib2, iclass 14, count 2 2006.258.00:41:27.09#ibcon#flushed, iclass 14, count 2 2006.258.00:41:27.09#ibcon#about to write, iclass 14, count 2 2006.258.00:41:27.09#ibcon#wrote, iclass 14, count 2 2006.258.00:41:27.09#ibcon#about to read 3, iclass 14, count 2 2006.258.00:41:27.12#ibcon#read 3, iclass 14, count 2 2006.258.00:41:27.12#ibcon#about to read 4, iclass 14, count 2 2006.258.00:41:27.12#ibcon#read 4, iclass 14, count 2 2006.258.00:41:27.12#ibcon#about to read 5, iclass 14, count 2 2006.258.00:41:27.12#ibcon#read 5, iclass 14, count 2 2006.258.00:41:27.12#ibcon#about to read 6, iclass 14, count 2 2006.258.00:41:27.12#ibcon#read 6, iclass 14, count 2 2006.258.00:41:27.12#ibcon#end of sib2, iclass 14, count 2 2006.258.00:41:27.12#ibcon#*after write, iclass 14, count 2 2006.258.00:41:27.12#ibcon#*before return 0, iclass 14, count 2 2006.258.00:41:27.12#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:27.12#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.258.00:41:27.12#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.258.00:41:27.12#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:27.12#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:27.24#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:27.24#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:27.24#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:41:27.24#ibcon#first serial, iclass 14, count 0 2006.258.00:41:27.24#ibcon#enter sib2, iclass 14, count 0 2006.258.00:41:27.24#ibcon#flushed, iclass 14, count 0 2006.258.00:41:27.24#ibcon#about to write, iclass 14, count 0 2006.258.00:41:27.24#ibcon#wrote, iclass 14, count 0 2006.258.00:41:27.24#ibcon#about to read 3, iclass 14, count 0 2006.258.00:41:27.26#ibcon#read 3, iclass 14, count 0 2006.258.00:41:27.26#ibcon#about to read 4, iclass 14, count 0 2006.258.00:41:27.26#ibcon#read 4, iclass 14, count 0 2006.258.00:41:27.26#ibcon#about to read 5, iclass 14, count 0 2006.258.00:41:27.26#ibcon#read 5, iclass 14, count 0 2006.258.00:41:27.26#ibcon#about to read 6, iclass 14, count 0 2006.258.00:41:27.26#ibcon#read 6, iclass 14, count 0 2006.258.00:41:27.26#ibcon#end of sib2, iclass 14, count 0 2006.258.00:41:27.26#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:41:27.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:41:27.26#ibcon#[27=USB\r\n] 2006.258.00:41:27.26#ibcon#*before write, iclass 14, count 0 2006.258.00:41:27.26#ibcon#enter sib2, iclass 14, count 0 2006.258.00:41:27.26#ibcon#flushed, iclass 14, count 0 2006.258.00:41:27.26#ibcon#about to write, iclass 14, count 0 2006.258.00:41:27.26#ibcon#wrote, iclass 14, count 0 2006.258.00:41:27.26#ibcon#about to read 3, iclass 14, count 0 2006.258.00:41:27.29#ibcon#read 3, iclass 14, count 0 2006.258.00:41:27.29#ibcon#about to read 4, iclass 14, count 0 2006.258.00:41:27.29#ibcon#read 4, iclass 14, count 0 2006.258.00:41:27.29#ibcon#about to read 5, iclass 14, count 0 2006.258.00:41:27.29#ibcon#read 5, iclass 14, count 0 2006.258.00:41:27.29#ibcon#about to read 6, iclass 14, count 0 2006.258.00:41:27.29#ibcon#read 6, iclass 14, count 0 2006.258.00:41:27.29#ibcon#end of sib2, iclass 14, count 0 2006.258.00:41:27.29#ibcon#*after write, iclass 14, count 0 2006.258.00:41:27.29#ibcon#*before return 0, iclass 14, count 0 2006.258.00:41:27.29#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:27.29#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.258.00:41:27.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:41:27.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:41:27.29$vck44/vblo=5,709.99 2006.258.00:41:27.29#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.00:41:27.29#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.00:41:27.30#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:27.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:27.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:27.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:27.30#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:41:27.30#ibcon#first serial, iclass 16, count 0 2006.258.00:41:27.30#ibcon#enter sib2, iclass 16, count 0 2006.258.00:41:27.30#ibcon#flushed, iclass 16, count 0 2006.258.00:41:27.30#ibcon#about to write, iclass 16, count 0 2006.258.00:41:27.30#ibcon#wrote, iclass 16, count 0 2006.258.00:41:27.30#ibcon#about to read 3, iclass 16, count 0 2006.258.00:41:27.31#ibcon#read 3, iclass 16, count 0 2006.258.00:41:27.31#ibcon#about to read 4, iclass 16, count 0 2006.258.00:41:27.31#ibcon#read 4, iclass 16, count 0 2006.258.00:41:27.31#ibcon#about to read 5, iclass 16, count 0 2006.258.00:41:27.31#ibcon#read 5, iclass 16, count 0 2006.258.00:41:27.31#ibcon#about to read 6, iclass 16, count 0 2006.258.00:41:27.31#ibcon#read 6, iclass 16, count 0 2006.258.00:41:27.31#ibcon#end of sib2, iclass 16, count 0 2006.258.00:41:27.31#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:41:27.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:41:27.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:41:27.31#ibcon#*before write, iclass 16, count 0 2006.258.00:41:27.31#ibcon#enter sib2, iclass 16, count 0 2006.258.00:41:27.31#ibcon#flushed, iclass 16, count 0 2006.258.00:41:27.31#ibcon#about to write, iclass 16, count 0 2006.258.00:41:27.31#ibcon#wrote, iclass 16, count 0 2006.258.00:41:27.31#ibcon#about to read 3, iclass 16, count 0 2006.258.00:41:27.35#ibcon#read 3, iclass 16, count 0 2006.258.00:41:27.35#ibcon#about to read 4, iclass 16, count 0 2006.258.00:41:27.35#ibcon#read 4, iclass 16, count 0 2006.258.00:41:27.35#ibcon#about to read 5, iclass 16, count 0 2006.258.00:41:27.35#ibcon#read 5, iclass 16, count 0 2006.258.00:41:27.35#ibcon#about to read 6, iclass 16, count 0 2006.258.00:41:27.35#ibcon#read 6, iclass 16, count 0 2006.258.00:41:27.35#ibcon#end of sib2, iclass 16, count 0 2006.258.00:41:27.35#ibcon#*after write, iclass 16, count 0 2006.258.00:41:27.35#ibcon#*before return 0, iclass 16, count 0 2006.258.00:41:27.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:27.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.00:41:27.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:41:27.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:41:27.35$vck44/vb=5,4 2006.258.00:41:27.35#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.258.00:41:27.35#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.258.00:41:27.35#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:27.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:27.41#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:27.41#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:27.41#ibcon#enter wrdev, iclass 18, count 2 2006.258.00:41:27.41#ibcon#first serial, iclass 18, count 2 2006.258.00:41:27.41#ibcon#enter sib2, iclass 18, count 2 2006.258.00:41:27.41#ibcon#flushed, iclass 18, count 2 2006.258.00:41:27.41#ibcon#about to write, iclass 18, count 2 2006.258.00:41:27.41#ibcon#wrote, iclass 18, count 2 2006.258.00:41:27.41#ibcon#about to read 3, iclass 18, count 2 2006.258.00:41:27.43#ibcon#read 3, iclass 18, count 2 2006.258.00:41:27.43#ibcon#about to read 4, iclass 18, count 2 2006.258.00:41:27.43#ibcon#read 4, iclass 18, count 2 2006.258.00:41:27.43#ibcon#about to read 5, iclass 18, count 2 2006.258.00:41:27.43#ibcon#read 5, iclass 18, count 2 2006.258.00:41:27.43#ibcon#about to read 6, iclass 18, count 2 2006.258.00:41:27.43#ibcon#read 6, iclass 18, count 2 2006.258.00:41:27.43#ibcon#end of sib2, iclass 18, count 2 2006.258.00:41:27.43#ibcon#*mode == 0, iclass 18, count 2 2006.258.00:41:27.43#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.258.00:41:27.43#ibcon#[27=AT05-04\r\n] 2006.258.00:41:27.43#ibcon#*before write, iclass 18, count 2 2006.258.00:41:27.43#ibcon#enter sib2, iclass 18, count 2 2006.258.00:41:27.43#ibcon#flushed, iclass 18, count 2 2006.258.00:41:27.43#ibcon#about to write, iclass 18, count 2 2006.258.00:41:27.43#ibcon#wrote, iclass 18, count 2 2006.258.00:41:27.43#ibcon#about to read 3, iclass 18, count 2 2006.258.00:41:27.46#ibcon#read 3, iclass 18, count 2 2006.258.00:41:27.46#ibcon#about to read 4, iclass 18, count 2 2006.258.00:41:27.46#ibcon#read 4, iclass 18, count 2 2006.258.00:41:27.46#ibcon#about to read 5, iclass 18, count 2 2006.258.00:41:27.46#ibcon#read 5, iclass 18, count 2 2006.258.00:41:27.46#ibcon#about to read 6, iclass 18, count 2 2006.258.00:41:27.46#ibcon#read 6, iclass 18, count 2 2006.258.00:41:27.46#ibcon#end of sib2, iclass 18, count 2 2006.258.00:41:27.46#ibcon#*after write, iclass 18, count 2 2006.258.00:41:27.48#ibcon#*before return 0, iclass 18, count 2 2006.258.00:41:27.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:27.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.258.00:41:27.48#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.258.00:41:27.48#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:27.48#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:27.59#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:27.59#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:27.59#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:41:27.59#ibcon#first serial, iclass 18, count 0 2006.258.00:41:27.59#ibcon#enter sib2, iclass 18, count 0 2006.258.00:41:27.59#ibcon#flushed, iclass 18, count 0 2006.258.00:41:27.59#ibcon#about to write, iclass 18, count 0 2006.258.00:41:27.59#ibcon#wrote, iclass 18, count 0 2006.258.00:41:27.59#ibcon#about to read 3, iclass 18, count 0 2006.258.00:41:27.61#ibcon#read 3, iclass 18, count 0 2006.258.00:41:27.61#ibcon#about to read 4, iclass 18, count 0 2006.258.00:41:27.61#ibcon#read 4, iclass 18, count 0 2006.258.00:41:27.61#ibcon#about to read 5, iclass 18, count 0 2006.258.00:41:27.61#ibcon#read 5, iclass 18, count 0 2006.258.00:41:27.61#ibcon#about to read 6, iclass 18, count 0 2006.258.00:41:27.61#ibcon#read 6, iclass 18, count 0 2006.258.00:41:27.61#ibcon#end of sib2, iclass 18, count 0 2006.258.00:41:27.61#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:41:27.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:41:27.61#ibcon#[27=USB\r\n] 2006.258.00:41:27.61#ibcon#*before write, iclass 18, count 0 2006.258.00:41:27.61#ibcon#enter sib2, iclass 18, count 0 2006.258.00:41:27.61#ibcon#flushed, iclass 18, count 0 2006.258.00:41:27.61#ibcon#about to write, iclass 18, count 0 2006.258.00:41:27.61#ibcon#wrote, iclass 18, count 0 2006.258.00:41:27.61#ibcon#about to read 3, iclass 18, count 0 2006.258.00:41:27.64#ibcon#read 3, iclass 18, count 0 2006.258.00:41:27.64#ibcon#about to read 4, iclass 18, count 0 2006.258.00:41:27.64#ibcon#read 4, iclass 18, count 0 2006.258.00:41:27.64#ibcon#about to read 5, iclass 18, count 0 2006.258.00:41:27.64#ibcon#read 5, iclass 18, count 0 2006.258.00:41:27.64#ibcon#about to read 6, iclass 18, count 0 2006.258.00:41:27.64#ibcon#read 6, iclass 18, count 0 2006.258.00:41:27.64#ibcon#end of sib2, iclass 18, count 0 2006.258.00:41:27.64#ibcon#*after write, iclass 18, count 0 2006.258.00:41:27.64#ibcon#*before return 0, iclass 18, count 0 2006.258.00:41:27.64#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:27.64#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.258.00:41:27.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:41:27.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:41:27.64$vck44/vblo=6,719.99 2006.258.00:41:27.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.00:41:27.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.00:41:27.64#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:27.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:27.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:27.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:27.64#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:41:27.64#ibcon#first serial, iclass 20, count 0 2006.258.00:41:27.64#ibcon#enter sib2, iclass 20, count 0 2006.258.00:41:27.64#ibcon#flushed, iclass 20, count 0 2006.258.00:41:27.65#ibcon#about to write, iclass 20, count 0 2006.258.00:41:27.65#ibcon#wrote, iclass 20, count 0 2006.258.00:41:27.65#ibcon#about to read 3, iclass 20, count 0 2006.258.00:41:27.66#ibcon#read 3, iclass 20, count 0 2006.258.00:41:27.66#ibcon#about to read 4, iclass 20, count 0 2006.258.00:41:27.66#ibcon#read 4, iclass 20, count 0 2006.258.00:41:27.66#ibcon#about to read 5, iclass 20, count 0 2006.258.00:41:27.66#ibcon#read 5, iclass 20, count 0 2006.258.00:41:27.66#ibcon#about to read 6, iclass 20, count 0 2006.258.00:41:27.66#ibcon#read 6, iclass 20, count 0 2006.258.00:41:27.66#ibcon#end of sib2, iclass 20, count 0 2006.258.00:41:27.66#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:41:27.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:41:27.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:41:27.66#ibcon#*before write, iclass 20, count 0 2006.258.00:41:27.66#ibcon#enter sib2, iclass 20, count 0 2006.258.00:41:27.66#ibcon#flushed, iclass 20, count 0 2006.258.00:41:27.66#ibcon#about to write, iclass 20, count 0 2006.258.00:41:27.66#ibcon#wrote, iclass 20, count 0 2006.258.00:41:27.66#ibcon#about to read 3, iclass 20, count 0 2006.258.00:41:27.70#ibcon#read 3, iclass 20, count 0 2006.258.00:41:27.70#ibcon#about to read 4, iclass 20, count 0 2006.258.00:41:27.70#ibcon#read 4, iclass 20, count 0 2006.258.00:41:27.70#ibcon#about to read 5, iclass 20, count 0 2006.258.00:41:27.70#ibcon#read 5, iclass 20, count 0 2006.258.00:41:27.70#ibcon#about to read 6, iclass 20, count 0 2006.258.00:41:27.70#ibcon#read 6, iclass 20, count 0 2006.258.00:41:27.70#ibcon#end of sib2, iclass 20, count 0 2006.258.00:41:27.70#ibcon#*after write, iclass 20, count 0 2006.258.00:41:27.70#ibcon#*before return 0, iclass 20, count 0 2006.258.00:41:27.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:27.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.00:41:27.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:41:27.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:41:27.70$vck44/vb=6,4 2006.258.00:41:27.70#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.00:41:27.70#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.00:41:27.70#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:27.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:27.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:27.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:27.76#ibcon#enter wrdev, iclass 22, count 2 2006.258.00:41:27.76#ibcon#first serial, iclass 22, count 2 2006.258.00:41:27.76#ibcon#enter sib2, iclass 22, count 2 2006.258.00:41:27.76#ibcon#flushed, iclass 22, count 2 2006.258.00:41:27.76#ibcon#about to write, iclass 22, count 2 2006.258.00:41:27.76#ibcon#wrote, iclass 22, count 2 2006.258.00:41:27.76#ibcon#about to read 3, iclass 22, count 2 2006.258.00:41:27.78#ibcon#read 3, iclass 22, count 2 2006.258.00:41:27.78#ibcon#about to read 4, iclass 22, count 2 2006.258.00:41:27.78#ibcon#read 4, iclass 22, count 2 2006.258.00:41:27.78#ibcon#about to read 5, iclass 22, count 2 2006.258.00:41:27.78#ibcon#read 5, iclass 22, count 2 2006.258.00:41:27.78#ibcon#about to read 6, iclass 22, count 2 2006.258.00:41:27.78#ibcon#read 6, iclass 22, count 2 2006.258.00:41:27.78#ibcon#end of sib2, iclass 22, count 2 2006.258.00:41:27.78#ibcon#*mode == 0, iclass 22, count 2 2006.258.00:41:27.78#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.00:41:27.78#ibcon#[27=AT06-04\r\n] 2006.258.00:41:27.78#ibcon#*before write, iclass 22, count 2 2006.258.00:41:27.78#ibcon#enter sib2, iclass 22, count 2 2006.258.00:41:27.78#ibcon#flushed, iclass 22, count 2 2006.258.00:41:27.78#ibcon#about to write, iclass 22, count 2 2006.258.00:41:27.78#ibcon#wrote, iclass 22, count 2 2006.258.00:41:27.78#ibcon#about to read 3, iclass 22, count 2 2006.258.00:41:27.81#ibcon#read 3, iclass 22, count 2 2006.258.00:41:27.81#ibcon#about to read 4, iclass 22, count 2 2006.258.00:41:27.81#ibcon#read 4, iclass 22, count 2 2006.258.00:41:27.81#ibcon#about to read 5, iclass 22, count 2 2006.258.00:41:27.81#ibcon#read 5, iclass 22, count 2 2006.258.00:41:27.81#ibcon#about to read 6, iclass 22, count 2 2006.258.00:41:27.81#ibcon#read 6, iclass 22, count 2 2006.258.00:41:27.81#ibcon#end of sib2, iclass 22, count 2 2006.258.00:41:27.81#ibcon#*after write, iclass 22, count 2 2006.258.00:41:27.81#ibcon#*before return 0, iclass 22, count 2 2006.258.00:41:27.81#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:27.81#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:41:27.81#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.00:41:27.81#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:27.81#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:27.93#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:27.93#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:27.93#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:41:27.93#ibcon#first serial, iclass 22, count 0 2006.258.00:41:27.93#ibcon#enter sib2, iclass 22, count 0 2006.258.00:41:27.93#ibcon#flushed, iclass 22, count 0 2006.258.00:41:27.93#ibcon#about to write, iclass 22, count 0 2006.258.00:41:27.93#ibcon#wrote, iclass 22, count 0 2006.258.00:41:27.93#ibcon#about to read 3, iclass 22, count 0 2006.258.00:41:27.95#ibcon#read 3, iclass 22, count 0 2006.258.00:41:27.95#ibcon#about to read 4, iclass 22, count 0 2006.258.00:41:27.95#ibcon#read 4, iclass 22, count 0 2006.258.00:41:27.95#ibcon#about to read 5, iclass 22, count 0 2006.258.00:41:27.95#ibcon#read 5, iclass 22, count 0 2006.258.00:41:27.95#ibcon#about to read 6, iclass 22, count 0 2006.258.00:41:27.95#ibcon#read 6, iclass 22, count 0 2006.258.00:41:27.95#ibcon#end of sib2, iclass 22, count 0 2006.258.00:41:27.95#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:41:27.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:41:27.95#ibcon#[27=USB\r\n] 2006.258.00:41:27.95#ibcon#*before write, iclass 22, count 0 2006.258.00:41:27.95#ibcon#enter sib2, iclass 22, count 0 2006.258.00:41:27.95#ibcon#flushed, iclass 22, count 0 2006.258.00:41:27.95#ibcon#about to write, iclass 22, count 0 2006.258.00:41:27.95#ibcon#wrote, iclass 22, count 0 2006.258.00:41:27.95#ibcon#about to read 3, iclass 22, count 0 2006.258.00:41:27.98#ibcon#read 3, iclass 22, count 0 2006.258.00:41:27.98#ibcon#about to read 4, iclass 22, count 0 2006.258.00:41:27.98#ibcon#read 4, iclass 22, count 0 2006.258.00:41:27.98#ibcon#about to read 5, iclass 22, count 0 2006.258.00:41:27.98#ibcon#read 5, iclass 22, count 0 2006.258.00:41:27.98#ibcon#about to read 6, iclass 22, count 0 2006.258.00:41:27.98#ibcon#read 6, iclass 22, count 0 2006.258.00:41:27.98#ibcon#end of sib2, iclass 22, count 0 2006.258.00:41:27.98#ibcon#*after write, iclass 22, count 0 2006.258.00:41:27.98#ibcon#*before return 0, iclass 22, count 0 2006.258.00:41:27.98#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:27.98#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:41:27.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:41:27.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:41:27.98$vck44/vblo=7,734.99 2006.258.00:41:27.98#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.00:41:27.98#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.00:41:27.98#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:27.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:27.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:27.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:27.98#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:41:27.98#ibcon#first serial, iclass 24, count 0 2006.258.00:41:27.98#ibcon#enter sib2, iclass 24, count 0 2006.258.00:41:27.98#ibcon#flushed, iclass 24, count 0 2006.258.00:41:27.98#ibcon#about to write, iclass 24, count 0 2006.258.00:41:27.99#ibcon#wrote, iclass 24, count 0 2006.258.00:41:27.99#ibcon#about to read 3, iclass 24, count 0 2006.258.00:41:28.00#ibcon#read 3, iclass 24, count 0 2006.258.00:41:28.00#ibcon#about to read 4, iclass 24, count 0 2006.258.00:41:28.00#ibcon#read 4, iclass 24, count 0 2006.258.00:41:28.00#ibcon#about to read 5, iclass 24, count 0 2006.258.00:41:28.00#ibcon#read 5, iclass 24, count 0 2006.258.00:41:28.00#ibcon#about to read 6, iclass 24, count 0 2006.258.00:41:28.00#ibcon#read 6, iclass 24, count 0 2006.258.00:41:28.00#ibcon#end of sib2, iclass 24, count 0 2006.258.00:41:28.00#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:41:28.00#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:41:28.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:41:28.00#ibcon#*before write, iclass 24, count 0 2006.258.00:41:28.00#ibcon#enter sib2, iclass 24, count 0 2006.258.00:41:28.00#ibcon#flushed, iclass 24, count 0 2006.258.00:41:28.00#ibcon#about to write, iclass 24, count 0 2006.258.00:41:28.00#ibcon#wrote, iclass 24, count 0 2006.258.00:41:28.00#ibcon#about to read 3, iclass 24, count 0 2006.258.00:41:28.04#ibcon#read 3, iclass 24, count 0 2006.258.00:41:28.04#ibcon#about to read 4, iclass 24, count 0 2006.258.00:41:28.04#ibcon#read 4, iclass 24, count 0 2006.258.00:41:28.04#ibcon#about to read 5, iclass 24, count 0 2006.258.00:41:28.04#ibcon#read 5, iclass 24, count 0 2006.258.00:41:28.04#ibcon#about to read 6, iclass 24, count 0 2006.258.00:41:28.04#ibcon#read 6, iclass 24, count 0 2006.258.00:41:28.04#ibcon#end of sib2, iclass 24, count 0 2006.258.00:41:28.04#ibcon#*after write, iclass 24, count 0 2006.258.00:41:28.04#ibcon#*before return 0, iclass 24, count 0 2006.258.00:41:28.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:28.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:41:28.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:41:28.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:41:28.04$vck44/vb=7,4 2006.258.00:41:28.04#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.00:41:28.04#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.00:41:28.04#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:28.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:28.10#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:28.10#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:28.10#ibcon#enter wrdev, iclass 26, count 2 2006.258.00:41:28.10#ibcon#first serial, iclass 26, count 2 2006.258.00:41:28.10#ibcon#enter sib2, iclass 26, count 2 2006.258.00:41:28.10#ibcon#flushed, iclass 26, count 2 2006.258.00:41:28.10#ibcon#about to write, iclass 26, count 2 2006.258.00:41:28.10#ibcon#wrote, iclass 26, count 2 2006.258.00:41:28.10#ibcon#about to read 3, iclass 26, count 2 2006.258.00:41:28.12#ibcon#read 3, iclass 26, count 2 2006.258.00:41:28.12#ibcon#about to read 4, iclass 26, count 2 2006.258.00:41:28.12#ibcon#read 4, iclass 26, count 2 2006.258.00:41:28.12#ibcon#about to read 5, iclass 26, count 2 2006.258.00:41:28.12#ibcon#read 5, iclass 26, count 2 2006.258.00:41:28.12#ibcon#about to read 6, iclass 26, count 2 2006.258.00:41:28.12#ibcon#read 6, iclass 26, count 2 2006.258.00:41:28.12#ibcon#end of sib2, iclass 26, count 2 2006.258.00:41:28.12#ibcon#*mode == 0, iclass 26, count 2 2006.258.00:41:28.12#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.00:41:28.12#ibcon#[27=AT07-04\r\n] 2006.258.00:41:28.12#ibcon#*before write, iclass 26, count 2 2006.258.00:41:28.12#ibcon#enter sib2, iclass 26, count 2 2006.258.00:41:28.12#ibcon#flushed, iclass 26, count 2 2006.258.00:41:28.12#ibcon#about to write, iclass 26, count 2 2006.258.00:41:28.12#ibcon#wrote, iclass 26, count 2 2006.258.00:41:28.12#ibcon#about to read 3, iclass 26, count 2 2006.258.00:41:28.15#ibcon#read 3, iclass 26, count 2 2006.258.00:41:28.15#ibcon#about to read 4, iclass 26, count 2 2006.258.00:41:28.15#ibcon#read 4, iclass 26, count 2 2006.258.00:41:28.15#ibcon#about to read 5, iclass 26, count 2 2006.258.00:41:28.15#ibcon#read 5, iclass 26, count 2 2006.258.00:41:28.15#ibcon#about to read 6, iclass 26, count 2 2006.258.00:41:28.15#ibcon#read 6, iclass 26, count 2 2006.258.00:41:28.15#ibcon#end of sib2, iclass 26, count 2 2006.258.00:41:28.15#ibcon#*after write, iclass 26, count 2 2006.258.00:41:28.15#ibcon#*before return 0, iclass 26, count 2 2006.258.00:41:28.15#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:28.15#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.00:41:28.15#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.00:41:28.15#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:28.15#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:28.27#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:28.27#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:28.27#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:41:28.27#ibcon#first serial, iclass 26, count 0 2006.258.00:41:28.27#ibcon#enter sib2, iclass 26, count 0 2006.258.00:41:28.27#ibcon#flushed, iclass 26, count 0 2006.258.00:41:28.27#ibcon#about to write, iclass 26, count 0 2006.258.00:41:28.27#ibcon#wrote, iclass 26, count 0 2006.258.00:41:28.27#ibcon#about to read 3, iclass 26, count 0 2006.258.00:41:28.29#ibcon#read 3, iclass 26, count 0 2006.258.00:41:28.29#ibcon#about to read 4, iclass 26, count 0 2006.258.00:41:28.29#ibcon#read 4, iclass 26, count 0 2006.258.00:41:28.29#ibcon#about to read 5, iclass 26, count 0 2006.258.00:41:28.29#ibcon#read 5, iclass 26, count 0 2006.258.00:41:28.29#ibcon#about to read 6, iclass 26, count 0 2006.258.00:41:28.29#ibcon#read 6, iclass 26, count 0 2006.258.00:41:28.29#ibcon#end of sib2, iclass 26, count 0 2006.258.00:41:28.29#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:41:28.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:41:28.29#ibcon#[27=USB\r\n] 2006.258.00:41:28.29#ibcon#*before write, iclass 26, count 0 2006.258.00:41:28.29#ibcon#enter sib2, iclass 26, count 0 2006.258.00:41:28.29#ibcon#flushed, iclass 26, count 0 2006.258.00:41:28.29#ibcon#about to write, iclass 26, count 0 2006.258.00:41:28.29#ibcon#wrote, iclass 26, count 0 2006.258.00:41:28.29#ibcon#about to read 3, iclass 26, count 0 2006.258.00:41:28.32#ibcon#read 3, iclass 26, count 0 2006.258.00:41:28.32#ibcon#about to read 4, iclass 26, count 0 2006.258.00:41:28.32#ibcon#read 4, iclass 26, count 0 2006.258.00:41:28.32#ibcon#about to read 5, iclass 26, count 0 2006.258.00:41:28.32#ibcon#read 5, iclass 26, count 0 2006.258.00:41:28.32#ibcon#about to read 6, iclass 26, count 0 2006.258.00:41:28.32#ibcon#read 6, iclass 26, count 0 2006.258.00:41:28.32#ibcon#end of sib2, iclass 26, count 0 2006.258.00:41:28.32#ibcon#*after write, iclass 26, count 0 2006.258.00:41:28.32#ibcon#*before return 0, iclass 26, count 0 2006.258.00:41:28.32#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:28.32#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.00:41:28.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:41:28.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:41:28.32$vck44/vblo=8,744.99 2006.258.00:41:28.32#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.00:41:28.32#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.00:41:28.32#ibcon#ireg 17 cls_cnt 0 2006.258.00:41:28.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:28.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:28.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:28.33#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:41:28.33#ibcon#first serial, iclass 28, count 0 2006.258.00:41:28.33#ibcon#enter sib2, iclass 28, count 0 2006.258.00:41:28.33#ibcon#flushed, iclass 28, count 0 2006.258.00:41:28.33#ibcon#about to write, iclass 28, count 0 2006.258.00:41:28.33#ibcon#wrote, iclass 28, count 0 2006.258.00:41:28.33#ibcon#about to read 3, iclass 28, count 0 2006.258.00:41:28.34#ibcon#read 3, iclass 28, count 0 2006.258.00:41:28.34#ibcon#about to read 4, iclass 28, count 0 2006.258.00:41:28.34#ibcon#read 4, iclass 28, count 0 2006.258.00:41:28.34#ibcon#about to read 5, iclass 28, count 0 2006.258.00:41:28.34#ibcon#read 5, iclass 28, count 0 2006.258.00:41:28.34#ibcon#about to read 6, iclass 28, count 0 2006.258.00:41:28.34#ibcon#read 6, iclass 28, count 0 2006.258.00:41:28.34#ibcon#end of sib2, iclass 28, count 0 2006.258.00:41:28.34#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:41:28.34#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:41:28.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:41:28.34#ibcon#*before write, iclass 28, count 0 2006.258.00:41:28.34#ibcon#enter sib2, iclass 28, count 0 2006.258.00:41:28.34#ibcon#flushed, iclass 28, count 0 2006.258.00:41:28.34#ibcon#about to write, iclass 28, count 0 2006.258.00:41:28.34#ibcon#wrote, iclass 28, count 0 2006.258.00:41:28.34#ibcon#about to read 3, iclass 28, count 0 2006.258.00:41:28.38#ibcon#read 3, iclass 28, count 0 2006.258.00:41:28.38#ibcon#about to read 4, iclass 28, count 0 2006.258.00:41:28.38#ibcon#read 4, iclass 28, count 0 2006.258.00:41:28.38#ibcon#about to read 5, iclass 28, count 0 2006.258.00:41:28.38#ibcon#read 5, iclass 28, count 0 2006.258.00:41:28.38#ibcon#about to read 6, iclass 28, count 0 2006.258.00:41:28.38#ibcon#read 6, iclass 28, count 0 2006.258.00:41:28.38#ibcon#end of sib2, iclass 28, count 0 2006.258.00:41:28.38#ibcon#*after write, iclass 28, count 0 2006.258.00:41:28.38#ibcon#*before return 0, iclass 28, count 0 2006.258.00:41:28.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:28.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.00:41:28.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:41:28.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:41:28.38$vck44/vb=8,4 2006.258.00:41:28.38#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.00:41:28.38#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.00:41:28.38#ibcon#ireg 11 cls_cnt 2 2006.258.00:41:28.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:28.44#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:28.44#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:28.44#ibcon#enter wrdev, iclass 30, count 2 2006.258.00:41:28.44#ibcon#first serial, iclass 30, count 2 2006.258.00:41:28.44#ibcon#enter sib2, iclass 30, count 2 2006.258.00:41:28.44#ibcon#flushed, iclass 30, count 2 2006.258.00:41:28.44#ibcon#about to write, iclass 30, count 2 2006.258.00:41:28.44#ibcon#wrote, iclass 30, count 2 2006.258.00:41:28.44#ibcon#about to read 3, iclass 30, count 2 2006.258.00:41:28.46#ibcon#read 3, iclass 30, count 2 2006.258.00:41:28.46#ibcon#about to read 4, iclass 30, count 2 2006.258.00:41:28.46#ibcon#read 4, iclass 30, count 2 2006.258.00:41:28.46#ibcon#about to read 5, iclass 30, count 2 2006.258.00:41:28.46#ibcon#read 5, iclass 30, count 2 2006.258.00:41:28.46#ibcon#about to read 6, iclass 30, count 2 2006.258.00:41:28.46#ibcon#read 6, iclass 30, count 2 2006.258.00:41:28.46#ibcon#end of sib2, iclass 30, count 2 2006.258.00:41:28.46#ibcon#*mode == 0, iclass 30, count 2 2006.258.00:41:28.46#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.00:41:28.46#ibcon#[27=AT08-04\r\n] 2006.258.00:41:28.46#ibcon#*before write, iclass 30, count 2 2006.258.00:41:28.46#ibcon#enter sib2, iclass 30, count 2 2006.258.00:41:28.46#ibcon#flushed, iclass 30, count 2 2006.258.00:41:28.46#ibcon#about to write, iclass 30, count 2 2006.258.00:41:28.46#ibcon#wrote, iclass 30, count 2 2006.258.00:41:28.46#ibcon#about to read 3, iclass 30, count 2 2006.258.00:41:28.49#ibcon#read 3, iclass 30, count 2 2006.258.00:41:28.49#ibcon#about to read 4, iclass 30, count 2 2006.258.00:41:28.49#ibcon#read 4, iclass 30, count 2 2006.258.00:41:28.49#ibcon#about to read 5, iclass 30, count 2 2006.258.00:41:28.49#ibcon#read 5, iclass 30, count 2 2006.258.00:41:28.49#ibcon#about to read 6, iclass 30, count 2 2006.258.00:41:28.49#ibcon#read 6, iclass 30, count 2 2006.258.00:41:28.49#ibcon#end of sib2, iclass 30, count 2 2006.258.00:41:28.49#ibcon#*after write, iclass 30, count 2 2006.258.00:41:28.49#ibcon#*before return 0, iclass 30, count 2 2006.258.00:41:28.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:28.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.00:41:28.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.00:41:28.51#ibcon#ireg 7 cls_cnt 0 2006.258.00:41:28.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:28.62#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:28.62#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:28.62#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:41:28.62#ibcon#first serial, iclass 30, count 0 2006.258.00:41:28.62#ibcon#enter sib2, iclass 30, count 0 2006.258.00:41:28.62#ibcon#flushed, iclass 30, count 0 2006.258.00:41:28.62#ibcon#about to write, iclass 30, count 0 2006.258.00:41:28.62#ibcon#wrote, iclass 30, count 0 2006.258.00:41:28.62#ibcon#about to read 3, iclass 30, count 0 2006.258.00:41:28.64#ibcon#read 3, iclass 30, count 0 2006.258.00:41:28.64#ibcon#about to read 4, iclass 30, count 0 2006.258.00:41:28.64#ibcon#read 4, iclass 30, count 0 2006.258.00:41:28.64#ibcon#about to read 5, iclass 30, count 0 2006.258.00:41:28.64#ibcon#read 5, iclass 30, count 0 2006.258.00:41:28.64#ibcon#about to read 6, iclass 30, count 0 2006.258.00:41:28.64#ibcon#read 6, iclass 30, count 0 2006.258.00:41:28.64#ibcon#end of sib2, iclass 30, count 0 2006.258.00:41:28.64#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:41:28.64#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:41:28.64#ibcon#[27=USB\r\n] 2006.258.00:41:28.64#ibcon#*before write, iclass 30, count 0 2006.258.00:41:28.64#ibcon#enter sib2, iclass 30, count 0 2006.258.00:41:28.64#ibcon#flushed, iclass 30, count 0 2006.258.00:41:28.64#ibcon#about to write, iclass 30, count 0 2006.258.00:41:28.64#ibcon#wrote, iclass 30, count 0 2006.258.00:41:28.64#ibcon#about to read 3, iclass 30, count 0 2006.258.00:41:28.67#ibcon#read 3, iclass 30, count 0 2006.258.00:41:28.67#ibcon#about to read 4, iclass 30, count 0 2006.258.00:41:28.67#ibcon#read 4, iclass 30, count 0 2006.258.00:41:28.67#ibcon#about to read 5, iclass 30, count 0 2006.258.00:41:28.67#ibcon#read 5, iclass 30, count 0 2006.258.00:41:28.67#ibcon#about to read 6, iclass 30, count 0 2006.258.00:41:28.67#ibcon#read 6, iclass 30, count 0 2006.258.00:41:28.67#ibcon#end of sib2, iclass 30, count 0 2006.258.00:41:28.67#ibcon#*after write, iclass 30, count 0 2006.258.00:41:28.67#ibcon#*before return 0, iclass 30, count 0 2006.258.00:41:28.67#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:28.67#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.00:41:28.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:41:28.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:41:28.67$vck44/vabw=wide 2006.258.00:41:28.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.258.00:41:28.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.258.00:41:28.67#ibcon#ireg 8 cls_cnt 0 2006.258.00:41:28.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:28.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:28.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:28.67#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:41:28.67#ibcon#first serial, iclass 32, count 0 2006.258.00:41:28.67#ibcon#enter sib2, iclass 32, count 0 2006.258.00:41:28.68#ibcon#flushed, iclass 32, count 0 2006.258.00:41:28.68#ibcon#about to write, iclass 32, count 0 2006.258.00:41:28.68#ibcon#wrote, iclass 32, count 0 2006.258.00:41:28.68#ibcon#about to read 3, iclass 32, count 0 2006.258.00:41:28.69#ibcon#read 3, iclass 32, count 0 2006.258.00:41:28.69#ibcon#about to read 4, iclass 32, count 0 2006.258.00:41:28.69#ibcon#read 4, iclass 32, count 0 2006.258.00:41:28.69#ibcon#about to read 5, iclass 32, count 0 2006.258.00:41:28.69#ibcon#read 5, iclass 32, count 0 2006.258.00:41:28.69#ibcon#about to read 6, iclass 32, count 0 2006.258.00:41:28.69#ibcon#read 6, iclass 32, count 0 2006.258.00:41:28.69#ibcon#end of sib2, iclass 32, count 0 2006.258.00:41:28.69#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:41:28.69#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:41:28.69#ibcon#[25=BW32\r\n] 2006.258.00:41:28.69#ibcon#*before write, iclass 32, count 0 2006.258.00:41:28.69#ibcon#enter sib2, iclass 32, count 0 2006.258.00:41:28.69#ibcon#flushed, iclass 32, count 0 2006.258.00:41:28.69#ibcon#about to write, iclass 32, count 0 2006.258.00:41:28.69#ibcon#wrote, iclass 32, count 0 2006.258.00:41:28.69#ibcon#about to read 3, iclass 32, count 0 2006.258.00:41:28.72#ibcon#read 3, iclass 32, count 0 2006.258.00:41:28.72#ibcon#about to read 4, iclass 32, count 0 2006.258.00:41:28.72#ibcon#read 4, iclass 32, count 0 2006.258.00:41:28.72#ibcon#about to read 5, iclass 32, count 0 2006.258.00:41:28.72#ibcon#read 5, iclass 32, count 0 2006.258.00:41:28.72#ibcon#about to read 6, iclass 32, count 0 2006.258.00:41:28.72#ibcon#read 6, iclass 32, count 0 2006.258.00:41:28.72#ibcon#end of sib2, iclass 32, count 0 2006.258.00:41:28.72#ibcon#*after write, iclass 32, count 0 2006.258.00:41:28.72#ibcon#*before return 0, iclass 32, count 0 2006.258.00:41:28.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:28.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.258.00:41:28.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:41:28.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:41:28.72$vck44/vbbw=wide 2006.258.00:41:28.72#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.00:41:28.72#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.00:41:28.72#ibcon#ireg 8 cls_cnt 0 2006.258.00:41:28.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:41:28.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:41:28.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:41:28.79#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:41:28.79#ibcon#first serial, iclass 34, count 0 2006.258.00:41:28.79#ibcon#enter sib2, iclass 34, count 0 2006.258.00:41:28.79#ibcon#flushed, iclass 34, count 0 2006.258.00:41:28.79#ibcon#about to write, iclass 34, count 0 2006.258.00:41:28.79#ibcon#wrote, iclass 34, count 0 2006.258.00:41:28.79#ibcon#about to read 3, iclass 34, count 0 2006.258.00:41:28.81#ibcon#read 3, iclass 34, count 0 2006.258.00:41:28.81#ibcon#about to read 4, iclass 34, count 0 2006.258.00:41:28.81#ibcon#read 4, iclass 34, count 0 2006.258.00:41:28.81#ibcon#about to read 5, iclass 34, count 0 2006.258.00:41:28.81#ibcon#read 5, iclass 34, count 0 2006.258.00:41:28.81#ibcon#about to read 6, iclass 34, count 0 2006.258.00:41:28.81#ibcon#read 6, iclass 34, count 0 2006.258.00:41:28.81#ibcon#end of sib2, iclass 34, count 0 2006.258.00:41:28.81#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:41:28.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:41:28.81#ibcon#[27=BW32\r\n] 2006.258.00:41:28.81#ibcon#*before write, iclass 34, count 0 2006.258.00:41:28.81#ibcon#enter sib2, iclass 34, count 0 2006.258.00:41:28.81#ibcon#flushed, iclass 34, count 0 2006.258.00:41:28.81#ibcon#about to write, iclass 34, count 0 2006.258.00:41:28.81#ibcon#wrote, iclass 34, count 0 2006.258.00:41:28.81#ibcon#about to read 3, iclass 34, count 0 2006.258.00:41:28.84#ibcon#read 3, iclass 34, count 0 2006.258.00:41:28.84#ibcon#about to read 4, iclass 34, count 0 2006.258.00:41:28.84#ibcon#read 4, iclass 34, count 0 2006.258.00:41:28.84#ibcon#about to read 5, iclass 34, count 0 2006.258.00:41:28.84#ibcon#read 5, iclass 34, count 0 2006.258.00:41:28.84#ibcon#about to read 6, iclass 34, count 0 2006.258.00:41:28.84#ibcon#read 6, iclass 34, count 0 2006.258.00:41:28.84#ibcon#end of sib2, iclass 34, count 0 2006.258.00:41:28.84#ibcon#*after write, iclass 34, count 0 2006.258.00:41:28.84#ibcon#*before return 0, iclass 34, count 0 2006.258.00:41:28.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:41:28.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:41:28.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:41:28.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:41:28.84$setupk4/ifdk4 2006.258.00:41:28.84$ifdk4/lo= 2006.258.00:41:28.85$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:41:28.85$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:41:28.85$ifdk4/patch= 2006.258.00:41:28.85$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:41:28.85$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:41:28.85$setupk4/!*+20s 2006.258.00:41:32.98#abcon#<5=/02 1.9 7.3 22.36 751016.2\r\n> 2006.258.00:41:33.00#abcon#{5=INTERFACE CLEAR} 2006.258.00:41:33.06#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:41:37.13#trakl#Source acquired 2006.258.00:41:37.13#flagr#flagr/antenna,acquired 2006.258.00:41:43.15#abcon#<5=/02 1.9 7.3 22.36 751016.2\r\n> 2006.258.00:41:43.17#abcon#{5=INTERFACE CLEAR} 2006.258.00:41:43.23#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:41:43.25$setupk4/"tpicd 2006.258.00:41:43.25$setupk4/echo=off 2006.258.00:41:43.25$setupk4/xlog=off 2006.258.00:41:43.25:!2006.258.00:44:00 2006.258.00:44:00.00:preob 2006.258.00:44:00.14/onsource/TRACKING 2006.258.00:44:00.14:!2006.258.00:44:10 2006.258.00:44:10.00:"tape 2006.258.00:44:10.00:"st=record 2006.258.00:44:10.00:data_valid=on 2006.258.00:44:10.00:midob 2006.258.00:44:10.14/onsource/TRACKING 2006.258.00:44:10.14/wx/22.46,1016.2,76 2006.258.00:44:10.32/cable/+6.4779E-03 2006.258.00:44:11.41/va/01,08,usb,yes,33,36 2006.258.00:44:11.41/va/02,07,usb,yes,36,36 2006.258.00:44:11.41/va/03,08,usb,yes,32,34 2006.258.00:44:11.41/va/04,07,usb,yes,37,39 2006.258.00:44:11.41/va/05,04,usb,yes,33,33 2006.258.00:44:11.41/va/06,04,usb,yes,36,36 2006.258.00:44:11.41/va/07,04,usb,yes,37,38 2006.258.00:44:11.41/va/08,04,usb,yes,31,38 2006.258.00:44:11.64/valo/01,524.99,yes,locked 2006.258.00:44:11.64/valo/02,534.99,yes,locked 2006.258.00:44:11.64/valo/03,564.99,yes,locked 2006.258.00:44:11.64/valo/04,624.99,yes,locked 2006.258.00:44:11.64/valo/05,734.99,yes,locked 2006.258.00:44:11.64/valo/06,814.99,yes,locked 2006.258.00:44:11.64/valo/07,864.99,yes,locked 2006.258.00:44:11.64/valo/08,884.99,yes,locked 2006.258.00:44:12.73/vb/01,04,usb,yes,38,35 2006.258.00:44:12.73/vb/02,05,usb,yes,36,36 2006.258.00:44:12.73/vb/03,04,usb,yes,37,41 2006.258.00:44:12.73/vb/04,05,usb,yes,37,36 2006.258.00:44:12.73/vb/05,04,usb,yes,33,36 2006.258.00:44:12.73/vb/06,04,usb,yes,39,34 2006.258.00:44:12.73/vb/07,04,usb,yes,38,38 2006.258.00:44:12.73/vb/08,04,usb,yes,35,39 2006.258.00:44:12.97/vblo/01,629.99,yes,locked 2006.258.00:44:12.97/vblo/02,634.99,yes,locked 2006.258.00:44:12.97/vblo/03,649.99,yes,locked 2006.258.00:44:12.97/vblo/04,679.99,yes,locked 2006.258.00:44:12.97/vblo/05,709.99,yes,locked 2006.258.00:44:12.97/vblo/06,719.99,yes,locked 2006.258.00:44:12.97/vblo/07,734.99,yes,locked 2006.258.00:44:12.97/vblo/08,744.99,yes,locked 2006.258.00:44:13.12/vabw/8 2006.258.00:44:13.27/vbbw/8 2006.258.00:44:13.36/xfe/off,on,15.0 2006.258.00:44:13.74/ifatt/23,28,28,28 2006.258.00:44:14.07/fmout-gps/S +4.54E-07 2006.258.00:44:14.11:!2006.258.00:45:40 2006.258.00:45:40.01:data_valid=off 2006.258.00:45:40.01:"et 2006.258.00:45:40.01:!+3s 2006.258.00:45:43.02:"tape 2006.258.00:45:43.02:postob 2006.258.00:45:43.12/cable/+6.4778E-03 2006.258.00:45:43.12/wx/22.53,1016.2,74 2006.258.00:45:43.18/fmout-gps/S +4.55E-07 2006.258.00:45:43.18:scan_name=258-0047,jd0609,80 2006.258.00:45:43.18:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.258.00:45:44.14#flagr#flagr/antenna,new-source 2006.258.00:45:44.14:checkk5 2006.258.00:45:44.56/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:45:44.97/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:45:45.37/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:45:45.77/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:45:46.15/chk_obsdata//k5ts1/T2580044??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.258.00:45:46.58/chk_obsdata//k5ts2/T2580044??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.258.00:45:46.98/chk_obsdata//k5ts3/T2580044??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.258.00:45:47.39/chk_obsdata//k5ts4/T2580044??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.258.00:45:48.12/k5log//k5ts1_log_newline 2006.258.00:45:48.85/k5log//k5ts2_log_newline 2006.258.00:45:49.58/k5log//k5ts3_log_newline 2006.258.00:45:50.30/k5log//k5ts4_log_newline 2006.258.00:45:50.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:45:50.32:setupk4=1 2006.258.00:45:50.32$setupk4/echo=on 2006.258.00:45:50.32$setupk4/pcalon 2006.258.00:45:50.32$pcalon/"no phase cal control is implemented here 2006.258.00:45:50.32$setupk4/"tpicd=stop 2006.258.00:45:50.32$setupk4/"rec=synch_on 2006.258.00:45:50.32$setupk4/"rec_mode=128 2006.258.00:45:50.32$setupk4/!* 2006.258.00:45:50.32$setupk4/recpk4 2006.258.00:45:50.32$recpk4/recpatch= 2006.258.00:45:50.33$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:45:50.33$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:45:50.33$setupk4/vck44 2006.258.00:45:50.33$vck44/valo=1,524.99 2006.258.00:45:50.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.00:45:50.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.00:45:50.33#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:50.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:50.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:50.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:50.33#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:45:50.33#ibcon#first serial, iclass 35, count 0 2006.258.00:45:50.33#ibcon#enter sib2, iclass 35, count 0 2006.258.00:45:50.33#ibcon#flushed, iclass 35, count 0 2006.258.00:45:50.33#ibcon#about to write, iclass 35, count 0 2006.258.00:45:50.33#ibcon#wrote, iclass 35, count 0 2006.258.00:45:50.33#ibcon#about to read 3, iclass 35, count 0 2006.258.00:45:50.34#ibcon#read 3, iclass 35, count 0 2006.258.00:45:50.34#ibcon#about to read 4, iclass 35, count 0 2006.258.00:45:50.34#ibcon#read 4, iclass 35, count 0 2006.258.00:45:50.34#ibcon#about to read 5, iclass 35, count 0 2006.258.00:45:50.34#ibcon#read 5, iclass 35, count 0 2006.258.00:45:50.34#ibcon#about to read 6, iclass 35, count 0 2006.258.00:45:50.34#ibcon#read 6, iclass 35, count 0 2006.258.00:45:50.34#ibcon#end of sib2, iclass 35, count 0 2006.258.00:45:50.34#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:45:50.34#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:45:50.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:45:50.34#ibcon#*before write, iclass 35, count 0 2006.258.00:45:50.34#ibcon#enter sib2, iclass 35, count 0 2006.258.00:45:50.34#ibcon#flushed, iclass 35, count 0 2006.258.00:45:50.34#ibcon#about to write, iclass 35, count 0 2006.258.00:45:50.34#ibcon#wrote, iclass 35, count 0 2006.258.00:45:50.34#ibcon#about to read 3, iclass 35, count 0 2006.258.00:45:50.39#ibcon#read 3, iclass 35, count 0 2006.258.00:45:50.39#ibcon#about to read 4, iclass 35, count 0 2006.258.00:45:50.39#ibcon#read 4, iclass 35, count 0 2006.258.00:45:50.39#ibcon#about to read 5, iclass 35, count 0 2006.258.00:45:50.39#ibcon#read 5, iclass 35, count 0 2006.258.00:45:50.39#ibcon#about to read 6, iclass 35, count 0 2006.258.00:45:50.39#ibcon#read 6, iclass 35, count 0 2006.258.00:45:50.39#ibcon#end of sib2, iclass 35, count 0 2006.258.00:45:50.39#ibcon#*after write, iclass 35, count 0 2006.258.00:45:50.39#ibcon#*before return 0, iclass 35, count 0 2006.258.00:45:50.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:50.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:50.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:45:50.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:45:50.39$vck44/va=1,8 2006.258.00:45:50.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.00:45:50.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.00:45:50.39#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:50.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:50.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:50.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:50.39#ibcon#enter wrdev, iclass 37, count 2 2006.258.00:45:50.39#ibcon#first serial, iclass 37, count 2 2006.258.00:45:50.39#ibcon#enter sib2, iclass 37, count 2 2006.258.00:45:50.39#ibcon#flushed, iclass 37, count 2 2006.258.00:45:50.39#ibcon#about to write, iclass 37, count 2 2006.258.00:45:50.39#ibcon#wrote, iclass 37, count 2 2006.258.00:45:50.39#ibcon#about to read 3, iclass 37, count 2 2006.258.00:45:50.41#ibcon#read 3, iclass 37, count 2 2006.258.00:45:50.41#ibcon#about to read 4, iclass 37, count 2 2006.258.00:45:50.41#ibcon#read 4, iclass 37, count 2 2006.258.00:45:50.41#ibcon#about to read 5, iclass 37, count 2 2006.258.00:45:50.41#ibcon#read 5, iclass 37, count 2 2006.258.00:45:50.41#ibcon#about to read 6, iclass 37, count 2 2006.258.00:45:50.41#ibcon#read 6, iclass 37, count 2 2006.258.00:45:50.41#ibcon#end of sib2, iclass 37, count 2 2006.258.00:45:50.41#ibcon#*mode == 0, iclass 37, count 2 2006.258.00:45:50.41#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.00:45:50.41#ibcon#[25=AT01-08\r\n] 2006.258.00:45:50.41#ibcon#*before write, iclass 37, count 2 2006.258.00:45:50.41#ibcon#enter sib2, iclass 37, count 2 2006.258.00:45:50.41#ibcon#flushed, iclass 37, count 2 2006.258.00:45:50.41#ibcon#about to write, iclass 37, count 2 2006.258.00:45:50.41#ibcon#wrote, iclass 37, count 2 2006.258.00:45:50.41#ibcon#about to read 3, iclass 37, count 2 2006.258.00:45:50.44#ibcon#read 3, iclass 37, count 2 2006.258.00:45:50.44#ibcon#about to read 4, iclass 37, count 2 2006.258.00:45:50.44#ibcon#read 4, iclass 37, count 2 2006.258.00:45:50.44#ibcon#about to read 5, iclass 37, count 2 2006.258.00:45:50.44#ibcon#read 5, iclass 37, count 2 2006.258.00:45:50.44#ibcon#about to read 6, iclass 37, count 2 2006.258.00:45:50.44#ibcon#read 6, iclass 37, count 2 2006.258.00:45:50.44#ibcon#end of sib2, iclass 37, count 2 2006.258.00:45:50.44#ibcon#*after write, iclass 37, count 2 2006.258.00:45:50.44#ibcon#*before return 0, iclass 37, count 2 2006.258.00:45:50.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:50.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:50.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.00:45:50.44#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:50.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:50.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:50.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:50.56#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:45:50.56#ibcon#first serial, iclass 37, count 0 2006.258.00:45:50.56#ibcon#enter sib2, iclass 37, count 0 2006.258.00:45:50.56#ibcon#flushed, iclass 37, count 0 2006.258.00:45:50.56#ibcon#about to write, iclass 37, count 0 2006.258.00:45:50.56#ibcon#wrote, iclass 37, count 0 2006.258.00:45:50.56#ibcon#about to read 3, iclass 37, count 0 2006.258.00:45:50.58#ibcon#read 3, iclass 37, count 0 2006.258.00:45:50.58#ibcon#about to read 4, iclass 37, count 0 2006.258.00:45:50.58#ibcon#read 4, iclass 37, count 0 2006.258.00:45:50.58#ibcon#about to read 5, iclass 37, count 0 2006.258.00:45:50.58#ibcon#read 5, iclass 37, count 0 2006.258.00:45:50.58#ibcon#about to read 6, iclass 37, count 0 2006.258.00:45:50.58#ibcon#read 6, iclass 37, count 0 2006.258.00:45:50.58#ibcon#end of sib2, iclass 37, count 0 2006.258.00:45:50.58#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:45:50.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:45:50.58#ibcon#[25=USB\r\n] 2006.258.00:45:50.58#ibcon#*before write, iclass 37, count 0 2006.258.00:45:50.58#ibcon#enter sib2, iclass 37, count 0 2006.258.00:45:50.58#ibcon#flushed, iclass 37, count 0 2006.258.00:45:50.58#ibcon#about to write, iclass 37, count 0 2006.258.00:45:50.58#ibcon#wrote, iclass 37, count 0 2006.258.00:45:50.58#ibcon#about to read 3, iclass 37, count 0 2006.258.00:45:50.61#ibcon#read 3, iclass 37, count 0 2006.258.00:45:50.61#ibcon#about to read 4, iclass 37, count 0 2006.258.00:45:50.61#ibcon#read 4, iclass 37, count 0 2006.258.00:45:50.61#ibcon#about to read 5, iclass 37, count 0 2006.258.00:45:50.61#ibcon#read 5, iclass 37, count 0 2006.258.00:45:50.61#ibcon#about to read 6, iclass 37, count 0 2006.258.00:45:50.61#ibcon#read 6, iclass 37, count 0 2006.258.00:45:50.61#ibcon#end of sib2, iclass 37, count 0 2006.258.00:45:50.61#ibcon#*after write, iclass 37, count 0 2006.258.00:45:50.61#ibcon#*before return 0, iclass 37, count 0 2006.258.00:45:50.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:50.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:50.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:45:50.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:45:50.61$vck44/valo=2,534.99 2006.258.00:45:50.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.00:45:50.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.00:45:50.61#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:50.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:50.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:50.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:50.61#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:45:50.61#ibcon#first serial, iclass 39, count 0 2006.258.00:45:50.61#ibcon#enter sib2, iclass 39, count 0 2006.258.00:45:50.61#ibcon#flushed, iclass 39, count 0 2006.258.00:45:50.61#ibcon#about to write, iclass 39, count 0 2006.258.00:45:50.61#ibcon#wrote, iclass 39, count 0 2006.258.00:45:50.61#ibcon#about to read 3, iclass 39, count 0 2006.258.00:45:50.63#ibcon#read 3, iclass 39, count 0 2006.258.00:45:50.63#ibcon#about to read 4, iclass 39, count 0 2006.258.00:45:50.63#ibcon#read 4, iclass 39, count 0 2006.258.00:45:50.63#ibcon#about to read 5, iclass 39, count 0 2006.258.00:45:50.63#ibcon#read 5, iclass 39, count 0 2006.258.00:45:50.63#ibcon#about to read 6, iclass 39, count 0 2006.258.00:45:50.63#ibcon#read 6, iclass 39, count 0 2006.258.00:45:50.63#ibcon#end of sib2, iclass 39, count 0 2006.258.00:45:50.63#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:45:50.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:45:50.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:45:50.63#ibcon#*before write, iclass 39, count 0 2006.258.00:45:50.63#ibcon#enter sib2, iclass 39, count 0 2006.258.00:45:50.63#ibcon#flushed, iclass 39, count 0 2006.258.00:45:50.63#ibcon#about to write, iclass 39, count 0 2006.258.00:45:50.63#ibcon#wrote, iclass 39, count 0 2006.258.00:45:50.63#ibcon#about to read 3, iclass 39, count 0 2006.258.00:45:50.67#ibcon#read 3, iclass 39, count 0 2006.258.00:45:50.67#ibcon#about to read 4, iclass 39, count 0 2006.258.00:45:50.67#ibcon#read 4, iclass 39, count 0 2006.258.00:45:50.67#ibcon#about to read 5, iclass 39, count 0 2006.258.00:45:50.67#ibcon#read 5, iclass 39, count 0 2006.258.00:45:50.67#ibcon#about to read 6, iclass 39, count 0 2006.258.00:45:50.67#ibcon#read 6, iclass 39, count 0 2006.258.00:45:50.67#ibcon#end of sib2, iclass 39, count 0 2006.258.00:45:50.67#ibcon#*after write, iclass 39, count 0 2006.258.00:45:50.67#ibcon#*before return 0, iclass 39, count 0 2006.258.00:45:50.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:50.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:50.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:45:50.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:45:50.67$vck44/va=2,7 2006.258.00:45:50.67#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.00:45:50.67#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.00:45:50.67#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:50.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:50.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:50.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:50.73#ibcon#enter wrdev, iclass 3, count 2 2006.258.00:45:50.73#ibcon#first serial, iclass 3, count 2 2006.258.00:45:50.73#ibcon#enter sib2, iclass 3, count 2 2006.258.00:45:50.73#ibcon#flushed, iclass 3, count 2 2006.258.00:45:50.73#ibcon#about to write, iclass 3, count 2 2006.258.00:45:50.73#ibcon#wrote, iclass 3, count 2 2006.258.00:45:50.73#ibcon#about to read 3, iclass 3, count 2 2006.258.00:45:50.75#ibcon#read 3, iclass 3, count 2 2006.258.00:45:50.75#ibcon#about to read 4, iclass 3, count 2 2006.258.00:45:50.75#ibcon#read 4, iclass 3, count 2 2006.258.00:45:50.75#ibcon#about to read 5, iclass 3, count 2 2006.258.00:45:50.75#ibcon#read 5, iclass 3, count 2 2006.258.00:45:50.75#ibcon#about to read 6, iclass 3, count 2 2006.258.00:45:50.75#ibcon#read 6, iclass 3, count 2 2006.258.00:45:50.75#ibcon#end of sib2, iclass 3, count 2 2006.258.00:45:50.75#ibcon#*mode == 0, iclass 3, count 2 2006.258.00:45:50.75#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.00:45:50.75#ibcon#[25=AT02-07\r\n] 2006.258.00:45:50.75#ibcon#*before write, iclass 3, count 2 2006.258.00:45:50.75#ibcon#enter sib2, iclass 3, count 2 2006.258.00:45:50.75#ibcon#flushed, iclass 3, count 2 2006.258.00:45:50.75#ibcon#about to write, iclass 3, count 2 2006.258.00:45:50.75#ibcon#wrote, iclass 3, count 2 2006.258.00:45:50.75#ibcon#about to read 3, iclass 3, count 2 2006.258.00:45:50.78#ibcon#read 3, iclass 3, count 2 2006.258.00:45:50.78#ibcon#about to read 4, iclass 3, count 2 2006.258.00:45:50.78#ibcon#read 4, iclass 3, count 2 2006.258.00:45:50.78#ibcon#about to read 5, iclass 3, count 2 2006.258.00:45:50.78#ibcon#read 5, iclass 3, count 2 2006.258.00:45:50.78#ibcon#about to read 6, iclass 3, count 2 2006.258.00:45:50.78#ibcon#read 6, iclass 3, count 2 2006.258.00:45:50.78#ibcon#end of sib2, iclass 3, count 2 2006.258.00:45:50.78#ibcon#*after write, iclass 3, count 2 2006.258.00:45:50.78#ibcon#*before return 0, iclass 3, count 2 2006.258.00:45:50.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:50.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:50.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.00:45:50.78#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:50.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:50.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:50.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:50.90#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:45:50.90#ibcon#first serial, iclass 3, count 0 2006.258.00:45:50.90#ibcon#enter sib2, iclass 3, count 0 2006.258.00:45:50.90#ibcon#flushed, iclass 3, count 0 2006.258.00:45:50.90#ibcon#about to write, iclass 3, count 0 2006.258.00:45:50.90#ibcon#wrote, iclass 3, count 0 2006.258.00:45:50.90#ibcon#about to read 3, iclass 3, count 0 2006.258.00:45:50.92#ibcon#read 3, iclass 3, count 0 2006.258.00:45:50.92#ibcon#about to read 4, iclass 3, count 0 2006.258.00:45:50.92#ibcon#read 4, iclass 3, count 0 2006.258.00:45:50.92#ibcon#about to read 5, iclass 3, count 0 2006.258.00:45:50.92#ibcon#read 5, iclass 3, count 0 2006.258.00:45:50.92#ibcon#about to read 6, iclass 3, count 0 2006.258.00:45:50.92#ibcon#read 6, iclass 3, count 0 2006.258.00:45:50.92#ibcon#end of sib2, iclass 3, count 0 2006.258.00:45:50.92#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:45:50.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:45:50.92#ibcon#[25=USB\r\n] 2006.258.00:45:50.92#ibcon#*before write, iclass 3, count 0 2006.258.00:45:50.92#ibcon#enter sib2, iclass 3, count 0 2006.258.00:45:50.92#ibcon#flushed, iclass 3, count 0 2006.258.00:45:50.92#ibcon#about to write, iclass 3, count 0 2006.258.00:45:50.92#ibcon#wrote, iclass 3, count 0 2006.258.00:45:50.92#ibcon#about to read 3, iclass 3, count 0 2006.258.00:45:50.95#ibcon#read 3, iclass 3, count 0 2006.258.00:45:50.95#ibcon#about to read 4, iclass 3, count 0 2006.258.00:45:50.95#ibcon#read 4, iclass 3, count 0 2006.258.00:45:50.95#ibcon#about to read 5, iclass 3, count 0 2006.258.00:45:50.95#ibcon#read 5, iclass 3, count 0 2006.258.00:45:50.95#ibcon#about to read 6, iclass 3, count 0 2006.258.00:45:50.95#ibcon#read 6, iclass 3, count 0 2006.258.00:45:50.95#ibcon#end of sib2, iclass 3, count 0 2006.258.00:45:50.95#ibcon#*after write, iclass 3, count 0 2006.258.00:45:50.95#ibcon#*before return 0, iclass 3, count 0 2006.258.00:45:50.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:50.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:50.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:45:50.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:45:50.95$vck44/valo=3,564.99 2006.258.00:45:50.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.00:45:50.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.00:45:50.95#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:50.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:50.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:50.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:50.95#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:45:50.95#ibcon#first serial, iclass 5, count 0 2006.258.00:45:50.95#ibcon#enter sib2, iclass 5, count 0 2006.258.00:45:50.95#ibcon#flushed, iclass 5, count 0 2006.258.00:45:50.95#ibcon#about to write, iclass 5, count 0 2006.258.00:45:50.95#ibcon#wrote, iclass 5, count 0 2006.258.00:45:50.95#ibcon#about to read 3, iclass 5, count 0 2006.258.00:45:50.97#ibcon#read 3, iclass 5, count 0 2006.258.00:45:50.97#ibcon#about to read 4, iclass 5, count 0 2006.258.00:45:50.97#ibcon#read 4, iclass 5, count 0 2006.258.00:45:50.97#ibcon#about to read 5, iclass 5, count 0 2006.258.00:45:50.97#ibcon#read 5, iclass 5, count 0 2006.258.00:45:50.97#ibcon#about to read 6, iclass 5, count 0 2006.258.00:45:50.97#ibcon#read 6, iclass 5, count 0 2006.258.00:45:50.97#ibcon#end of sib2, iclass 5, count 0 2006.258.00:45:50.97#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:45:50.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:45:50.97#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:45:50.97#ibcon#*before write, iclass 5, count 0 2006.258.00:45:50.97#ibcon#enter sib2, iclass 5, count 0 2006.258.00:45:50.97#ibcon#flushed, iclass 5, count 0 2006.258.00:45:50.97#ibcon#about to write, iclass 5, count 0 2006.258.00:45:50.97#ibcon#wrote, iclass 5, count 0 2006.258.00:45:50.97#ibcon#about to read 3, iclass 5, count 0 2006.258.00:45:51.01#ibcon#read 3, iclass 5, count 0 2006.258.00:45:51.01#ibcon#about to read 4, iclass 5, count 0 2006.258.00:45:51.01#ibcon#read 4, iclass 5, count 0 2006.258.00:45:51.01#ibcon#about to read 5, iclass 5, count 0 2006.258.00:45:51.01#ibcon#read 5, iclass 5, count 0 2006.258.00:45:51.01#ibcon#about to read 6, iclass 5, count 0 2006.258.00:45:51.01#ibcon#read 6, iclass 5, count 0 2006.258.00:45:51.01#ibcon#end of sib2, iclass 5, count 0 2006.258.00:45:51.01#ibcon#*after write, iclass 5, count 0 2006.258.00:45:51.01#ibcon#*before return 0, iclass 5, count 0 2006.258.00:45:51.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:51.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:51.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:45:51.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:45:51.01$vck44/va=3,8 2006.258.00:45:51.01#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.00:45:51.01#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.00:45:51.01#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:51.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:51.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:51.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:51.07#ibcon#enter wrdev, iclass 7, count 2 2006.258.00:45:51.07#ibcon#first serial, iclass 7, count 2 2006.258.00:45:51.07#ibcon#enter sib2, iclass 7, count 2 2006.258.00:45:51.07#ibcon#flushed, iclass 7, count 2 2006.258.00:45:51.07#ibcon#about to write, iclass 7, count 2 2006.258.00:45:51.07#ibcon#wrote, iclass 7, count 2 2006.258.00:45:51.07#ibcon#about to read 3, iclass 7, count 2 2006.258.00:45:51.09#ibcon#read 3, iclass 7, count 2 2006.258.00:45:51.09#ibcon#about to read 4, iclass 7, count 2 2006.258.00:45:51.09#ibcon#read 4, iclass 7, count 2 2006.258.00:45:51.09#ibcon#about to read 5, iclass 7, count 2 2006.258.00:45:51.09#ibcon#read 5, iclass 7, count 2 2006.258.00:45:51.09#ibcon#about to read 6, iclass 7, count 2 2006.258.00:45:51.09#ibcon#read 6, iclass 7, count 2 2006.258.00:45:51.09#ibcon#end of sib2, iclass 7, count 2 2006.258.00:45:51.09#ibcon#*mode == 0, iclass 7, count 2 2006.258.00:45:51.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.00:45:51.09#ibcon#[25=AT03-08\r\n] 2006.258.00:45:51.09#ibcon#*before write, iclass 7, count 2 2006.258.00:45:51.09#ibcon#enter sib2, iclass 7, count 2 2006.258.00:45:51.09#ibcon#flushed, iclass 7, count 2 2006.258.00:45:51.09#ibcon#about to write, iclass 7, count 2 2006.258.00:45:51.09#ibcon#wrote, iclass 7, count 2 2006.258.00:45:51.09#ibcon#about to read 3, iclass 7, count 2 2006.258.00:45:51.12#ibcon#read 3, iclass 7, count 2 2006.258.00:45:51.12#ibcon#about to read 4, iclass 7, count 2 2006.258.00:45:51.12#ibcon#read 4, iclass 7, count 2 2006.258.00:45:51.12#ibcon#about to read 5, iclass 7, count 2 2006.258.00:45:51.12#ibcon#read 5, iclass 7, count 2 2006.258.00:45:51.12#ibcon#about to read 6, iclass 7, count 2 2006.258.00:45:51.12#ibcon#read 6, iclass 7, count 2 2006.258.00:45:51.12#ibcon#end of sib2, iclass 7, count 2 2006.258.00:45:51.12#ibcon#*after write, iclass 7, count 2 2006.258.00:45:51.12#ibcon#*before return 0, iclass 7, count 2 2006.258.00:45:51.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:51.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:51.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.00:45:51.12#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:51.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:51.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:51.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:51.24#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:45:51.24#ibcon#first serial, iclass 7, count 0 2006.258.00:45:51.24#ibcon#enter sib2, iclass 7, count 0 2006.258.00:45:51.24#ibcon#flushed, iclass 7, count 0 2006.258.00:45:51.24#ibcon#about to write, iclass 7, count 0 2006.258.00:45:51.24#ibcon#wrote, iclass 7, count 0 2006.258.00:45:51.24#ibcon#about to read 3, iclass 7, count 0 2006.258.00:45:51.26#ibcon#read 3, iclass 7, count 0 2006.258.00:45:51.26#ibcon#about to read 4, iclass 7, count 0 2006.258.00:45:51.26#ibcon#read 4, iclass 7, count 0 2006.258.00:45:51.26#ibcon#about to read 5, iclass 7, count 0 2006.258.00:45:51.26#ibcon#read 5, iclass 7, count 0 2006.258.00:45:51.26#ibcon#about to read 6, iclass 7, count 0 2006.258.00:45:51.26#ibcon#read 6, iclass 7, count 0 2006.258.00:45:51.26#ibcon#end of sib2, iclass 7, count 0 2006.258.00:45:51.26#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:45:51.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:45:51.26#ibcon#[25=USB\r\n] 2006.258.00:45:51.26#ibcon#*before write, iclass 7, count 0 2006.258.00:45:51.26#ibcon#enter sib2, iclass 7, count 0 2006.258.00:45:51.26#ibcon#flushed, iclass 7, count 0 2006.258.00:45:51.26#ibcon#about to write, iclass 7, count 0 2006.258.00:45:51.26#ibcon#wrote, iclass 7, count 0 2006.258.00:45:51.26#ibcon#about to read 3, iclass 7, count 0 2006.258.00:45:51.29#ibcon#read 3, iclass 7, count 0 2006.258.00:45:51.29#ibcon#about to read 4, iclass 7, count 0 2006.258.00:45:51.29#ibcon#read 4, iclass 7, count 0 2006.258.00:45:51.29#ibcon#about to read 5, iclass 7, count 0 2006.258.00:45:51.29#ibcon#read 5, iclass 7, count 0 2006.258.00:45:51.29#ibcon#about to read 6, iclass 7, count 0 2006.258.00:45:51.29#ibcon#read 6, iclass 7, count 0 2006.258.00:45:51.29#ibcon#end of sib2, iclass 7, count 0 2006.258.00:45:51.29#ibcon#*after write, iclass 7, count 0 2006.258.00:45:51.29#ibcon#*before return 0, iclass 7, count 0 2006.258.00:45:51.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:51.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:51.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:45:51.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:45:51.29$vck44/valo=4,624.99 2006.258.00:45:51.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.00:45:51.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.00:45:51.29#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:51.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:51.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:51.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:51.29#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:45:51.29#ibcon#first serial, iclass 11, count 0 2006.258.00:45:51.29#ibcon#enter sib2, iclass 11, count 0 2006.258.00:45:51.29#ibcon#flushed, iclass 11, count 0 2006.258.00:45:51.29#ibcon#about to write, iclass 11, count 0 2006.258.00:45:51.29#ibcon#wrote, iclass 11, count 0 2006.258.00:45:51.29#ibcon#about to read 3, iclass 11, count 0 2006.258.00:45:51.31#ibcon#read 3, iclass 11, count 0 2006.258.00:45:51.31#ibcon#about to read 4, iclass 11, count 0 2006.258.00:45:51.31#ibcon#read 4, iclass 11, count 0 2006.258.00:45:51.31#ibcon#about to read 5, iclass 11, count 0 2006.258.00:45:51.31#ibcon#read 5, iclass 11, count 0 2006.258.00:45:51.31#ibcon#about to read 6, iclass 11, count 0 2006.258.00:45:51.31#ibcon#read 6, iclass 11, count 0 2006.258.00:45:51.31#ibcon#end of sib2, iclass 11, count 0 2006.258.00:45:51.31#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:45:51.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:45:51.31#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:45:51.31#ibcon#*before write, iclass 11, count 0 2006.258.00:45:51.31#ibcon#enter sib2, iclass 11, count 0 2006.258.00:45:51.31#ibcon#flushed, iclass 11, count 0 2006.258.00:45:51.31#ibcon#about to write, iclass 11, count 0 2006.258.00:45:51.31#ibcon#wrote, iclass 11, count 0 2006.258.00:45:51.31#ibcon#about to read 3, iclass 11, count 0 2006.258.00:45:51.35#ibcon#read 3, iclass 11, count 0 2006.258.00:45:51.35#ibcon#about to read 4, iclass 11, count 0 2006.258.00:45:51.35#ibcon#read 4, iclass 11, count 0 2006.258.00:45:51.35#ibcon#about to read 5, iclass 11, count 0 2006.258.00:45:51.35#ibcon#read 5, iclass 11, count 0 2006.258.00:45:51.35#ibcon#about to read 6, iclass 11, count 0 2006.258.00:45:51.35#ibcon#read 6, iclass 11, count 0 2006.258.00:45:51.35#ibcon#end of sib2, iclass 11, count 0 2006.258.00:45:51.35#ibcon#*after write, iclass 11, count 0 2006.258.00:45:51.35#ibcon#*before return 0, iclass 11, count 0 2006.258.00:45:51.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:51.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:51.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:45:51.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:45:51.35$vck44/va=4,7 2006.258.00:45:51.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.00:45:51.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.00:45:51.35#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:51.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:51.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:51.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:51.41#ibcon#enter wrdev, iclass 13, count 2 2006.258.00:45:51.41#ibcon#first serial, iclass 13, count 2 2006.258.00:45:51.41#ibcon#enter sib2, iclass 13, count 2 2006.258.00:45:51.41#ibcon#flushed, iclass 13, count 2 2006.258.00:45:51.41#ibcon#about to write, iclass 13, count 2 2006.258.00:45:51.41#ibcon#wrote, iclass 13, count 2 2006.258.00:45:51.41#ibcon#about to read 3, iclass 13, count 2 2006.258.00:45:51.43#ibcon#read 3, iclass 13, count 2 2006.258.00:45:51.43#ibcon#about to read 4, iclass 13, count 2 2006.258.00:45:51.43#ibcon#read 4, iclass 13, count 2 2006.258.00:45:51.43#ibcon#about to read 5, iclass 13, count 2 2006.258.00:45:51.43#ibcon#read 5, iclass 13, count 2 2006.258.00:45:51.43#ibcon#about to read 6, iclass 13, count 2 2006.258.00:45:51.43#ibcon#read 6, iclass 13, count 2 2006.258.00:45:51.43#ibcon#end of sib2, iclass 13, count 2 2006.258.00:45:51.43#ibcon#*mode == 0, iclass 13, count 2 2006.258.00:45:51.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.00:45:51.43#ibcon#[25=AT04-07\r\n] 2006.258.00:45:51.43#ibcon#*before write, iclass 13, count 2 2006.258.00:45:51.43#ibcon#enter sib2, iclass 13, count 2 2006.258.00:45:51.43#ibcon#flushed, iclass 13, count 2 2006.258.00:45:51.43#ibcon#about to write, iclass 13, count 2 2006.258.00:45:51.43#ibcon#wrote, iclass 13, count 2 2006.258.00:45:51.43#ibcon#about to read 3, iclass 13, count 2 2006.258.00:45:51.46#ibcon#read 3, iclass 13, count 2 2006.258.00:45:51.46#ibcon#about to read 4, iclass 13, count 2 2006.258.00:45:51.46#ibcon#read 4, iclass 13, count 2 2006.258.00:45:51.46#ibcon#about to read 5, iclass 13, count 2 2006.258.00:45:51.46#ibcon#read 5, iclass 13, count 2 2006.258.00:45:51.46#ibcon#about to read 6, iclass 13, count 2 2006.258.00:45:51.46#ibcon#read 6, iclass 13, count 2 2006.258.00:45:51.46#ibcon#end of sib2, iclass 13, count 2 2006.258.00:45:51.46#ibcon#*after write, iclass 13, count 2 2006.258.00:45:51.46#ibcon#*before return 0, iclass 13, count 2 2006.258.00:45:51.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:51.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:51.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.00:45:51.46#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:51.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:51.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:51.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:51.58#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:45:51.58#ibcon#first serial, iclass 13, count 0 2006.258.00:45:51.58#ibcon#enter sib2, iclass 13, count 0 2006.258.00:45:51.58#ibcon#flushed, iclass 13, count 0 2006.258.00:45:51.58#ibcon#about to write, iclass 13, count 0 2006.258.00:45:51.58#ibcon#wrote, iclass 13, count 0 2006.258.00:45:51.58#ibcon#about to read 3, iclass 13, count 0 2006.258.00:45:51.60#ibcon#read 3, iclass 13, count 0 2006.258.00:45:51.60#ibcon#about to read 4, iclass 13, count 0 2006.258.00:45:51.60#ibcon#read 4, iclass 13, count 0 2006.258.00:45:51.60#ibcon#about to read 5, iclass 13, count 0 2006.258.00:45:51.60#ibcon#read 5, iclass 13, count 0 2006.258.00:45:51.60#ibcon#about to read 6, iclass 13, count 0 2006.258.00:45:51.60#ibcon#read 6, iclass 13, count 0 2006.258.00:45:51.60#ibcon#end of sib2, iclass 13, count 0 2006.258.00:45:51.60#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:45:51.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:45:51.60#ibcon#[25=USB\r\n] 2006.258.00:45:51.60#ibcon#*before write, iclass 13, count 0 2006.258.00:45:51.60#ibcon#enter sib2, iclass 13, count 0 2006.258.00:45:51.60#ibcon#flushed, iclass 13, count 0 2006.258.00:45:51.60#ibcon#about to write, iclass 13, count 0 2006.258.00:45:51.60#ibcon#wrote, iclass 13, count 0 2006.258.00:45:51.60#ibcon#about to read 3, iclass 13, count 0 2006.258.00:45:51.63#ibcon#read 3, iclass 13, count 0 2006.258.00:45:51.63#ibcon#about to read 4, iclass 13, count 0 2006.258.00:45:51.63#ibcon#read 4, iclass 13, count 0 2006.258.00:45:51.63#ibcon#about to read 5, iclass 13, count 0 2006.258.00:45:51.63#ibcon#read 5, iclass 13, count 0 2006.258.00:45:51.63#ibcon#about to read 6, iclass 13, count 0 2006.258.00:45:51.63#ibcon#read 6, iclass 13, count 0 2006.258.00:45:51.63#ibcon#end of sib2, iclass 13, count 0 2006.258.00:45:51.63#ibcon#*after write, iclass 13, count 0 2006.258.00:45:51.63#ibcon#*before return 0, iclass 13, count 0 2006.258.00:45:51.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:51.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:51.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:45:51.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:45:51.63$vck44/valo=5,734.99 2006.258.00:45:51.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.00:45:51.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.00:45:51.63#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:51.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:51.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:51.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:51.63#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:45:51.63#ibcon#first serial, iclass 15, count 0 2006.258.00:45:51.63#ibcon#enter sib2, iclass 15, count 0 2006.258.00:45:51.63#ibcon#flushed, iclass 15, count 0 2006.258.00:45:51.63#ibcon#about to write, iclass 15, count 0 2006.258.00:45:51.63#ibcon#wrote, iclass 15, count 0 2006.258.00:45:51.63#ibcon#about to read 3, iclass 15, count 0 2006.258.00:45:51.65#ibcon#read 3, iclass 15, count 0 2006.258.00:45:51.65#ibcon#about to read 4, iclass 15, count 0 2006.258.00:45:51.65#ibcon#read 4, iclass 15, count 0 2006.258.00:45:51.65#ibcon#about to read 5, iclass 15, count 0 2006.258.00:45:51.65#ibcon#read 5, iclass 15, count 0 2006.258.00:45:51.65#ibcon#about to read 6, iclass 15, count 0 2006.258.00:45:51.65#ibcon#read 6, iclass 15, count 0 2006.258.00:45:51.65#ibcon#end of sib2, iclass 15, count 0 2006.258.00:45:51.65#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:45:51.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:45:51.65#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:45:51.65#ibcon#*before write, iclass 15, count 0 2006.258.00:45:51.65#ibcon#enter sib2, iclass 15, count 0 2006.258.00:45:51.65#ibcon#flushed, iclass 15, count 0 2006.258.00:45:51.65#ibcon#about to write, iclass 15, count 0 2006.258.00:45:51.65#ibcon#wrote, iclass 15, count 0 2006.258.00:45:51.65#ibcon#about to read 3, iclass 15, count 0 2006.258.00:45:51.69#ibcon#read 3, iclass 15, count 0 2006.258.00:45:51.69#ibcon#about to read 4, iclass 15, count 0 2006.258.00:45:51.69#ibcon#read 4, iclass 15, count 0 2006.258.00:45:51.69#ibcon#about to read 5, iclass 15, count 0 2006.258.00:45:51.69#ibcon#read 5, iclass 15, count 0 2006.258.00:45:51.69#ibcon#about to read 6, iclass 15, count 0 2006.258.00:45:51.69#ibcon#read 6, iclass 15, count 0 2006.258.00:45:51.69#ibcon#end of sib2, iclass 15, count 0 2006.258.00:45:51.69#ibcon#*after write, iclass 15, count 0 2006.258.00:45:51.69#ibcon#*before return 0, iclass 15, count 0 2006.258.00:45:51.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:51.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:51.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:45:51.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:45:51.69$vck44/va=5,4 2006.258.00:45:51.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.00:45:51.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.00:45:51.69#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:51.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:51.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:51.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:51.75#ibcon#enter wrdev, iclass 17, count 2 2006.258.00:45:51.75#ibcon#first serial, iclass 17, count 2 2006.258.00:45:51.75#ibcon#enter sib2, iclass 17, count 2 2006.258.00:45:51.75#ibcon#flushed, iclass 17, count 2 2006.258.00:45:51.75#ibcon#about to write, iclass 17, count 2 2006.258.00:45:51.75#ibcon#wrote, iclass 17, count 2 2006.258.00:45:51.75#ibcon#about to read 3, iclass 17, count 2 2006.258.00:45:51.77#ibcon#read 3, iclass 17, count 2 2006.258.00:45:51.77#ibcon#about to read 4, iclass 17, count 2 2006.258.00:45:51.77#ibcon#read 4, iclass 17, count 2 2006.258.00:45:51.77#ibcon#about to read 5, iclass 17, count 2 2006.258.00:45:51.77#ibcon#read 5, iclass 17, count 2 2006.258.00:45:51.77#ibcon#about to read 6, iclass 17, count 2 2006.258.00:45:51.77#ibcon#read 6, iclass 17, count 2 2006.258.00:45:51.77#ibcon#end of sib2, iclass 17, count 2 2006.258.00:45:51.77#ibcon#*mode == 0, iclass 17, count 2 2006.258.00:45:51.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.00:45:51.77#ibcon#[25=AT05-04\r\n] 2006.258.00:45:51.77#ibcon#*before write, iclass 17, count 2 2006.258.00:45:51.77#ibcon#enter sib2, iclass 17, count 2 2006.258.00:45:51.77#ibcon#flushed, iclass 17, count 2 2006.258.00:45:51.77#ibcon#about to write, iclass 17, count 2 2006.258.00:45:51.77#ibcon#wrote, iclass 17, count 2 2006.258.00:45:51.77#ibcon#about to read 3, iclass 17, count 2 2006.258.00:45:51.80#ibcon#read 3, iclass 17, count 2 2006.258.00:45:51.80#ibcon#about to read 4, iclass 17, count 2 2006.258.00:45:51.80#ibcon#read 4, iclass 17, count 2 2006.258.00:45:51.80#ibcon#about to read 5, iclass 17, count 2 2006.258.00:45:51.80#ibcon#read 5, iclass 17, count 2 2006.258.00:45:51.80#ibcon#about to read 6, iclass 17, count 2 2006.258.00:45:51.80#ibcon#read 6, iclass 17, count 2 2006.258.00:45:51.80#ibcon#end of sib2, iclass 17, count 2 2006.258.00:45:51.80#ibcon#*after write, iclass 17, count 2 2006.258.00:45:51.80#ibcon#*before return 0, iclass 17, count 2 2006.258.00:45:51.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:51.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:51.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.00:45:51.80#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:51.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:51.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:51.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:51.92#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:45:51.92#ibcon#first serial, iclass 17, count 0 2006.258.00:45:51.92#ibcon#enter sib2, iclass 17, count 0 2006.258.00:45:51.92#ibcon#flushed, iclass 17, count 0 2006.258.00:45:51.92#ibcon#about to write, iclass 17, count 0 2006.258.00:45:51.92#ibcon#wrote, iclass 17, count 0 2006.258.00:45:51.92#ibcon#about to read 3, iclass 17, count 0 2006.258.00:45:51.94#ibcon#read 3, iclass 17, count 0 2006.258.00:45:51.94#ibcon#about to read 4, iclass 17, count 0 2006.258.00:45:51.94#ibcon#read 4, iclass 17, count 0 2006.258.00:45:51.94#ibcon#about to read 5, iclass 17, count 0 2006.258.00:45:51.94#ibcon#read 5, iclass 17, count 0 2006.258.00:45:51.94#ibcon#about to read 6, iclass 17, count 0 2006.258.00:45:51.94#ibcon#read 6, iclass 17, count 0 2006.258.00:45:51.94#ibcon#end of sib2, iclass 17, count 0 2006.258.00:45:51.94#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:45:51.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:45:51.94#ibcon#[25=USB\r\n] 2006.258.00:45:51.94#ibcon#*before write, iclass 17, count 0 2006.258.00:45:51.94#ibcon#enter sib2, iclass 17, count 0 2006.258.00:45:51.94#ibcon#flushed, iclass 17, count 0 2006.258.00:45:51.94#ibcon#about to write, iclass 17, count 0 2006.258.00:45:51.94#ibcon#wrote, iclass 17, count 0 2006.258.00:45:51.94#ibcon#about to read 3, iclass 17, count 0 2006.258.00:45:51.97#ibcon#read 3, iclass 17, count 0 2006.258.00:45:51.97#ibcon#about to read 4, iclass 17, count 0 2006.258.00:45:51.97#ibcon#read 4, iclass 17, count 0 2006.258.00:45:51.97#ibcon#about to read 5, iclass 17, count 0 2006.258.00:45:51.97#ibcon#read 5, iclass 17, count 0 2006.258.00:45:51.97#ibcon#about to read 6, iclass 17, count 0 2006.258.00:45:51.97#ibcon#read 6, iclass 17, count 0 2006.258.00:45:51.97#ibcon#end of sib2, iclass 17, count 0 2006.258.00:45:51.97#ibcon#*after write, iclass 17, count 0 2006.258.00:45:51.97#ibcon#*before return 0, iclass 17, count 0 2006.258.00:45:51.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:51.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:51.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:45:51.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:45:51.97$vck44/valo=6,814.99 2006.258.00:45:51.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.00:45:51.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.00:45:51.97#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:51.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:51.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:51.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:51.97#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:45:51.97#ibcon#first serial, iclass 19, count 0 2006.258.00:45:51.97#ibcon#enter sib2, iclass 19, count 0 2006.258.00:45:51.97#ibcon#flushed, iclass 19, count 0 2006.258.00:45:51.97#ibcon#about to write, iclass 19, count 0 2006.258.00:45:51.97#ibcon#wrote, iclass 19, count 0 2006.258.00:45:51.97#ibcon#about to read 3, iclass 19, count 0 2006.258.00:45:51.99#ibcon#read 3, iclass 19, count 0 2006.258.00:45:51.99#ibcon#about to read 4, iclass 19, count 0 2006.258.00:45:51.99#ibcon#read 4, iclass 19, count 0 2006.258.00:45:51.99#ibcon#about to read 5, iclass 19, count 0 2006.258.00:45:51.99#ibcon#read 5, iclass 19, count 0 2006.258.00:45:51.99#ibcon#about to read 6, iclass 19, count 0 2006.258.00:45:51.99#ibcon#read 6, iclass 19, count 0 2006.258.00:45:51.99#ibcon#end of sib2, iclass 19, count 0 2006.258.00:45:51.99#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:45:51.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:45:51.99#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:45:51.99#ibcon#*before write, iclass 19, count 0 2006.258.00:45:51.99#ibcon#enter sib2, iclass 19, count 0 2006.258.00:45:51.99#ibcon#flushed, iclass 19, count 0 2006.258.00:45:51.99#ibcon#about to write, iclass 19, count 0 2006.258.00:45:51.99#ibcon#wrote, iclass 19, count 0 2006.258.00:45:51.99#ibcon#about to read 3, iclass 19, count 0 2006.258.00:45:52.03#ibcon#read 3, iclass 19, count 0 2006.258.00:45:52.03#ibcon#about to read 4, iclass 19, count 0 2006.258.00:45:52.03#ibcon#read 4, iclass 19, count 0 2006.258.00:45:52.03#ibcon#about to read 5, iclass 19, count 0 2006.258.00:45:52.03#ibcon#read 5, iclass 19, count 0 2006.258.00:45:52.03#ibcon#about to read 6, iclass 19, count 0 2006.258.00:45:52.03#ibcon#read 6, iclass 19, count 0 2006.258.00:45:52.03#ibcon#end of sib2, iclass 19, count 0 2006.258.00:45:52.03#ibcon#*after write, iclass 19, count 0 2006.258.00:45:52.03#ibcon#*before return 0, iclass 19, count 0 2006.258.00:45:52.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:52.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:52.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:45:52.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:45:52.03$vck44/va=6,4 2006.258.00:45:52.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.00:45:52.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.00:45:52.03#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:52.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:52.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:52.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:52.09#ibcon#enter wrdev, iclass 21, count 2 2006.258.00:45:52.09#ibcon#first serial, iclass 21, count 2 2006.258.00:45:52.09#ibcon#enter sib2, iclass 21, count 2 2006.258.00:45:52.09#ibcon#flushed, iclass 21, count 2 2006.258.00:45:52.09#ibcon#about to write, iclass 21, count 2 2006.258.00:45:52.09#ibcon#wrote, iclass 21, count 2 2006.258.00:45:52.09#ibcon#about to read 3, iclass 21, count 2 2006.258.00:45:52.11#ibcon#read 3, iclass 21, count 2 2006.258.00:45:52.11#ibcon#about to read 4, iclass 21, count 2 2006.258.00:45:52.11#ibcon#read 4, iclass 21, count 2 2006.258.00:45:52.11#ibcon#about to read 5, iclass 21, count 2 2006.258.00:45:52.11#ibcon#read 5, iclass 21, count 2 2006.258.00:45:52.11#ibcon#about to read 6, iclass 21, count 2 2006.258.00:45:52.11#ibcon#read 6, iclass 21, count 2 2006.258.00:45:52.11#ibcon#end of sib2, iclass 21, count 2 2006.258.00:45:52.11#ibcon#*mode == 0, iclass 21, count 2 2006.258.00:45:52.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.00:45:52.11#ibcon#[25=AT06-04\r\n] 2006.258.00:45:52.11#ibcon#*before write, iclass 21, count 2 2006.258.00:45:52.11#ibcon#enter sib2, iclass 21, count 2 2006.258.00:45:52.11#ibcon#flushed, iclass 21, count 2 2006.258.00:45:52.11#ibcon#about to write, iclass 21, count 2 2006.258.00:45:52.11#ibcon#wrote, iclass 21, count 2 2006.258.00:45:52.11#ibcon#about to read 3, iclass 21, count 2 2006.258.00:45:52.14#ibcon#read 3, iclass 21, count 2 2006.258.00:45:52.14#ibcon#about to read 4, iclass 21, count 2 2006.258.00:45:52.14#ibcon#read 4, iclass 21, count 2 2006.258.00:45:52.14#ibcon#about to read 5, iclass 21, count 2 2006.258.00:45:52.14#ibcon#read 5, iclass 21, count 2 2006.258.00:45:52.14#ibcon#about to read 6, iclass 21, count 2 2006.258.00:45:52.14#ibcon#read 6, iclass 21, count 2 2006.258.00:45:52.14#ibcon#end of sib2, iclass 21, count 2 2006.258.00:45:52.14#ibcon#*after write, iclass 21, count 2 2006.258.00:45:52.14#ibcon#*before return 0, iclass 21, count 2 2006.258.00:45:52.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:52.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:52.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.00:45:52.14#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:52.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:52.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:52.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:52.26#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:45:52.26#ibcon#first serial, iclass 21, count 0 2006.258.00:45:52.26#ibcon#enter sib2, iclass 21, count 0 2006.258.00:45:52.26#ibcon#flushed, iclass 21, count 0 2006.258.00:45:52.26#ibcon#about to write, iclass 21, count 0 2006.258.00:45:52.26#ibcon#wrote, iclass 21, count 0 2006.258.00:45:52.26#ibcon#about to read 3, iclass 21, count 0 2006.258.00:45:52.28#ibcon#read 3, iclass 21, count 0 2006.258.00:45:52.28#ibcon#about to read 4, iclass 21, count 0 2006.258.00:45:52.28#ibcon#read 4, iclass 21, count 0 2006.258.00:45:52.28#ibcon#about to read 5, iclass 21, count 0 2006.258.00:45:52.28#ibcon#read 5, iclass 21, count 0 2006.258.00:45:52.28#ibcon#about to read 6, iclass 21, count 0 2006.258.00:45:52.28#ibcon#read 6, iclass 21, count 0 2006.258.00:45:52.28#ibcon#end of sib2, iclass 21, count 0 2006.258.00:45:52.28#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:45:52.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:45:52.28#ibcon#[25=USB\r\n] 2006.258.00:45:52.28#ibcon#*before write, iclass 21, count 0 2006.258.00:45:52.28#ibcon#enter sib2, iclass 21, count 0 2006.258.00:45:52.28#ibcon#flushed, iclass 21, count 0 2006.258.00:45:52.28#ibcon#about to write, iclass 21, count 0 2006.258.00:45:52.28#ibcon#wrote, iclass 21, count 0 2006.258.00:45:52.28#ibcon#about to read 3, iclass 21, count 0 2006.258.00:45:52.31#ibcon#read 3, iclass 21, count 0 2006.258.00:45:52.31#ibcon#about to read 4, iclass 21, count 0 2006.258.00:45:52.31#ibcon#read 4, iclass 21, count 0 2006.258.00:45:52.31#ibcon#about to read 5, iclass 21, count 0 2006.258.00:45:52.31#ibcon#read 5, iclass 21, count 0 2006.258.00:45:52.31#ibcon#about to read 6, iclass 21, count 0 2006.258.00:45:52.31#ibcon#read 6, iclass 21, count 0 2006.258.00:45:52.31#ibcon#end of sib2, iclass 21, count 0 2006.258.00:45:52.31#ibcon#*after write, iclass 21, count 0 2006.258.00:45:52.31#ibcon#*before return 0, iclass 21, count 0 2006.258.00:45:52.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:52.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:52.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:45:52.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:45:52.31$vck44/valo=7,864.99 2006.258.00:45:52.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.00:45:52.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.00:45:52.31#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:52.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:52.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:52.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:52.31#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:45:52.31#ibcon#first serial, iclass 23, count 0 2006.258.00:45:52.31#ibcon#enter sib2, iclass 23, count 0 2006.258.00:45:52.31#ibcon#flushed, iclass 23, count 0 2006.258.00:45:52.31#ibcon#about to write, iclass 23, count 0 2006.258.00:45:52.31#ibcon#wrote, iclass 23, count 0 2006.258.00:45:52.31#ibcon#about to read 3, iclass 23, count 0 2006.258.00:45:52.33#ibcon#read 3, iclass 23, count 0 2006.258.00:45:52.33#ibcon#about to read 4, iclass 23, count 0 2006.258.00:45:52.33#ibcon#read 4, iclass 23, count 0 2006.258.00:45:52.33#ibcon#about to read 5, iclass 23, count 0 2006.258.00:45:52.33#ibcon#read 5, iclass 23, count 0 2006.258.00:45:52.33#ibcon#about to read 6, iclass 23, count 0 2006.258.00:45:52.33#ibcon#read 6, iclass 23, count 0 2006.258.00:45:52.33#ibcon#end of sib2, iclass 23, count 0 2006.258.00:45:52.33#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:45:52.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:45:52.33#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:45:52.33#ibcon#*before write, iclass 23, count 0 2006.258.00:45:52.33#ibcon#enter sib2, iclass 23, count 0 2006.258.00:45:52.33#ibcon#flushed, iclass 23, count 0 2006.258.00:45:52.33#ibcon#about to write, iclass 23, count 0 2006.258.00:45:52.33#ibcon#wrote, iclass 23, count 0 2006.258.00:45:52.33#ibcon#about to read 3, iclass 23, count 0 2006.258.00:45:52.37#ibcon#read 3, iclass 23, count 0 2006.258.00:45:52.37#ibcon#about to read 4, iclass 23, count 0 2006.258.00:45:52.37#ibcon#read 4, iclass 23, count 0 2006.258.00:45:52.37#ibcon#about to read 5, iclass 23, count 0 2006.258.00:45:52.37#ibcon#read 5, iclass 23, count 0 2006.258.00:45:52.37#ibcon#about to read 6, iclass 23, count 0 2006.258.00:45:52.37#ibcon#read 6, iclass 23, count 0 2006.258.00:45:52.37#ibcon#end of sib2, iclass 23, count 0 2006.258.00:45:52.37#ibcon#*after write, iclass 23, count 0 2006.258.00:45:52.37#ibcon#*before return 0, iclass 23, count 0 2006.258.00:45:52.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:52.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:52.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:45:52.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:45:52.37$vck44/va=7,4 2006.258.00:45:52.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.258.00:45:52.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.258.00:45:52.37#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:52.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:52.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:52.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:52.43#ibcon#enter wrdev, iclass 25, count 2 2006.258.00:45:52.43#ibcon#first serial, iclass 25, count 2 2006.258.00:45:52.43#ibcon#enter sib2, iclass 25, count 2 2006.258.00:45:52.43#ibcon#flushed, iclass 25, count 2 2006.258.00:45:52.43#ibcon#about to write, iclass 25, count 2 2006.258.00:45:52.43#ibcon#wrote, iclass 25, count 2 2006.258.00:45:52.43#ibcon#about to read 3, iclass 25, count 2 2006.258.00:45:52.45#ibcon#read 3, iclass 25, count 2 2006.258.00:45:52.45#ibcon#about to read 4, iclass 25, count 2 2006.258.00:45:52.45#ibcon#read 4, iclass 25, count 2 2006.258.00:45:52.45#ibcon#about to read 5, iclass 25, count 2 2006.258.00:45:52.45#ibcon#read 5, iclass 25, count 2 2006.258.00:45:52.45#ibcon#about to read 6, iclass 25, count 2 2006.258.00:45:52.45#ibcon#read 6, iclass 25, count 2 2006.258.00:45:52.45#ibcon#end of sib2, iclass 25, count 2 2006.258.00:45:52.45#ibcon#*mode == 0, iclass 25, count 2 2006.258.00:45:52.45#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.258.00:45:52.45#ibcon#[25=AT07-04\r\n] 2006.258.00:45:52.45#ibcon#*before write, iclass 25, count 2 2006.258.00:45:52.45#ibcon#enter sib2, iclass 25, count 2 2006.258.00:45:52.45#ibcon#flushed, iclass 25, count 2 2006.258.00:45:52.45#ibcon#about to write, iclass 25, count 2 2006.258.00:45:52.45#ibcon#wrote, iclass 25, count 2 2006.258.00:45:52.45#ibcon#about to read 3, iclass 25, count 2 2006.258.00:45:52.48#ibcon#read 3, iclass 25, count 2 2006.258.00:45:52.48#ibcon#about to read 4, iclass 25, count 2 2006.258.00:45:52.48#ibcon#read 4, iclass 25, count 2 2006.258.00:45:52.48#ibcon#about to read 5, iclass 25, count 2 2006.258.00:45:52.48#ibcon#read 5, iclass 25, count 2 2006.258.00:45:52.48#ibcon#about to read 6, iclass 25, count 2 2006.258.00:45:52.48#ibcon#read 6, iclass 25, count 2 2006.258.00:45:52.48#ibcon#end of sib2, iclass 25, count 2 2006.258.00:45:52.48#ibcon#*after write, iclass 25, count 2 2006.258.00:45:52.49#ibcon#*before return 0, iclass 25, count 2 2006.258.00:45:52.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:52.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:52.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.258.00:45:52.49#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:52.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:52.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:52.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:52.60#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:45:52.60#ibcon#first serial, iclass 25, count 0 2006.258.00:45:52.60#ibcon#enter sib2, iclass 25, count 0 2006.258.00:45:52.60#ibcon#flushed, iclass 25, count 0 2006.258.00:45:52.60#ibcon#about to write, iclass 25, count 0 2006.258.00:45:52.60#ibcon#wrote, iclass 25, count 0 2006.258.00:45:52.60#ibcon#about to read 3, iclass 25, count 0 2006.258.00:45:52.62#ibcon#read 3, iclass 25, count 0 2006.258.00:45:52.62#ibcon#about to read 4, iclass 25, count 0 2006.258.00:45:52.62#ibcon#read 4, iclass 25, count 0 2006.258.00:45:52.62#ibcon#about to read 5, iclass 25, count 0 2006.258.00:45:52.62#ibcon#read 5, iclass 25, count 0 2006.258.00:45:52.62#ibcon#about to read 6, iclass 25, count 0 2006.258.00:45:52.62#ibcon#read 6, iclass 25, count 0 2006.258.00:45:52.62#ibcon#end of sib2, iclass 25, count 0 2006.258.00:45:52.62#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:45:52.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:45:52.62#ibcon#[25=USB\r\n] 2006.258.00:45:52.62#ibcon#*before write, iclass 25, count 0 2006.258.00:45:52.62#ibcon#enter sib2, iclass 25, count 0 2006.258.00:45:52.62#ibcon#flushed, iclass 25, count 0 2006.258.00:45:52.62#ibcon#about to write, iclass 25, count 0 2006.258.00:45:52.62#ibcon#wrote, iclass 25, count 0 2006.258.00:45:52.62#ibcon#about to read 3, iclass 25, count 0 2006.258.00:45:52.65#ibcon#read 3, iclass 25, count 0 2006.258.00:45:52.65#ibcon#about to read 4, iclass 25, count 0 2006.258.00:45:52.65#ibcon#read 4, iclass 25, count 0 2006.258.00:45:52.65#ibcon#about to read 5, iclass 25, count 0 2006.258.00:45:52.65#ibcon#read 5, iclass 25, count 0 2006.258.00:45:52.65#ibcon#about to read 6, iclass 25, count 0 2006.258.00:45:52.65#ibcon#read 6, iclass 25, count 0 2006.258.00:45:52.65#ibcon#end of sib2, iclass 25, count 0 2006.258.00:45:52.65#ibcon#*after write, iclass 25, count 0 2006.258.00:45:52.65#ibcon#*before return 0, iclass 25, count 0 2006.258.00:45:52.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:52.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:52.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:45:52.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:45:52.65$vck44/valo=8,884.99 2006.258.00:45:52.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.00:45:52.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.00:45:52.65#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:52.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:52.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:52.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:52.65#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:45:52.65#ibcon#first serial, iclass 27, count 0 2006.258.00:45:52.65#ibcon#enter sib2, iclass 27, count 0 2006.258.00:45:52.65#ibcon#flushed, iclass 27, count 0 2006.258.00:45:52.65#ibcon#about to write, iclass 27, count 0 2006.258.00:45:52.65#ibcon#wrote, iclass 27, count 0 2006.258.00:45:52.65#ibcon#about to read 3, iclass 27, count 0 2006.258.00:45:52.67#ibcon#read 3, iclass 27, count 0 2006.258.00:45:52.67#ibcon#about to read 4, iclass 27, count 0 2006.258.00:45:52.67#ibcon#read 4, iclass 27, count 0 2006.258.00:45:52.67#ibcon#about to read 5, iclass 27, count 0 2006.258.00:45:52.67#ibcon#read 5, iclass 27, count 0 2006.258.00:45:52.67#ibcon#about to read 6, iclass 27, count 0 2006.258.00:45:52.67#ibcon#read 6, iclass 27, count 0 2006.258.00:45:52.67#ibcon#end of sib2, iclass 27, count 0 2006.258.00:45:52.67#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:45:52.67#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:45:52.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:45:52.67#ibcon#*before write, iclass 27, count 0 2006.258.00:45:52.67#ibcon#enter sib2, iclass 27, count 0 2006.258.00:45:52.67#ibcon#flushed, iclass 27, count 0 2006.258.00:45:52.67#ibcon#about to write, iclass 27, count 0 2006.258.00:45:52.67#ibcon#wrote, iclass 27, count 0 2006.258.00:45:52.67#ibcon#about to read 3, iclass 27, count 0 2006.258.00:45:52.71#ibcon#read 3, iclass 27, count 0 2006.258.00:45:52.71#ibcon#about to read 4, iclass 27, count 0 2006.258.00:45:52.71#ibcon#read 4, iclass 27, count 0 2006.258.00:45:52.71#ibcon#about to read 5, iclass 27, count 0 2006.258.00:45:52.71#ibcon#read 5, iclass 27, count 0 2006.258.00:45:52.71#ibcon#about to read 6, iclass 27, count 0 2006.258.00:45:52.71#ibcon#read 6, iclass 27, count 0 2006.258.00:45:52.71#ibcon#end of sib2, iclass 27, count 0 2006.258.00:45:52.71#ibcon#*after write, iclass 27, count 0 2006.258.00:45:52.71#ibcon#*before return 0, iclass 27, count 0 2006.258.00:45:52.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:52.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:52.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:45:52.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:45:52.71$vck44/va=8,4 2006.258.00:45:52.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.00:45:52.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.00:45:52.71#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:52.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:45:52.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:45:52.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:45:52.77#ibcon#enter wrdev, iclass 29, count 2 2006.258.00:45:52.77#ibcon#first serial, iclass 29, count 2 2006.258.00:45:52.77#ibcon#enter sib2, iclass 29, count 2 2006.258.00:45:52.77#ibcon#flushed, iclass 29, count 2 2006.258.00:45:52.77#ibcon#about to write, iclass 29, count 2 2006.258.00:45:52.77#ibcon#wrote, iclass 29, count 2 2006.258.00:45:52.77#ibcon#about to read 3, iclass 29, count 2 2006.258.00:45:52.79#ibcon#read 3, iclass 29, count 2 2006.258.00:45:52.79#ibcon#about to read 4, iclass 29, count 2 2006.258.00:45:52.79#ibcon#read 4, iclass 29, count 2 2006.258.00:45:52.79#ibcon#about to read 5, iclass 29, count 2 2006.258.00:45:52.79#ibcon#read 5, iclass 29, count 2 2006.258.00:45:52.79#ibcon#about to read 6, iclass 29, count 2 2006.258.00:45:52.79#ibcon#read 6, iclass 29, count 2 2006.258.00:45:52.79#ibcon#end of sib2, iclass 29, count 2 2006.258.00:45:52.79#ibcon#*mode == 0, iclass 29, count 2 2006.258.00:45:52.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.00:45:52.79#ibcon#[25=AT08-04\r\n] 2006.258.00:45:52.79#ibcon#*before write, iclass 29, count 2 2006.258.00:45:52.79#ibcon#enter sib2, iclass 29, count 2 2006.258.00:45:52.79#ibcon#flushed, iclass 29, count 2 2006.258.00:45:52.79#ibcon#about to write, iclass 29, count 2 2006.258.00:45:52.79#ibcon#wrote, iclass 29, count 2 2006.258.00:45:52.79#ibcon#about to read 3, iclass 29, count 2 2006.258.00:45:52.82#ibcon#read 3, iclass 29, count 2 2006.258.00:45:52.82#ibcon#about to read 4, iclass 29, count 2 2006.258.00:45:52.82#ibcon#read 4, iclass 29, count 2 2006.258.00:45:52.82#ibcon#about to read 5, iclass 29, count 2 2006.258.00:45:52.82#ibcon#read 5, iclass 29, count 2 2006.258.00:45:52.82#ibcon#about to read 6, iclass 29, count 2 2006.258.00:45:52.82#ibcon#read 6, iclass 29, count 2 2006.258.00:45:52.82#ibcon#end of sib2, iclass 29, count 2 2006.258.00:45:52.82#ibcon#*after write, iclass 29, count 2 2006.258.00:45:52.82#ibcon#*before return 0, iclass 29, count 2 2006.258.00:45:52.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:45:52.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.00:45:52.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.00:45:52.82#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:52.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:45:52.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:45:52.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:45:52.94#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:45:52.94#ibcon#first serial, iclass 29, count 0 2006.258.00:45:52.94#ibcon#enter sib2, iclass 29, count 0 2006.258.00:45:52.94#ibcon#flushed, iclass 29, count 0 2006.258.00:45:52.94#ibcon#about to write, iclass 29, count 0 2006.258.00:45:52.94#ibcon#wrote, iclass 29, count 0 2006.258.00:45:52.94#ibcon#about to read 3, iclass 29, count 0 2006.258.00:45:52.96#ibcon#read 3, iclass 29, count 0 2006.258.00:45:52.96#ibcon#about to read 4, iclass 29, count 0 2006.258.00:45:52.96#ibcon#read 4, iclass 29, count 0 2006.258.00:45:52.96#ibcon#about to read 5, iclass 29, count 0 2006.258.00:45:52.96#ibcon#read 5, iclass 29, count 0 2006.258.00:45:52.96#ibcon#about to read 6, iclass 29, count 0 2006.258.00:45:52.96#ibcon#read 6, iclass 29, count 0 2006.258.00:45:52.96#ibcon#end of sib2, iclass 29, count 0 2006.258.00:45:52.96#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:45:52.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:45:52.96#ibcon#[25=USB\r\n] 2006.258.00:45:52.96#ibcon#*before write, iclass 29, count 0 2006.258.00:45:52.96#ibcon#enter sib2, iclass 29, count 0 2006.258.00:45:52.96#ibcon#flushed, iclass 29, count 0 2006.258.00:45:52.96#ibcon#about to write, iclass 29, count 0 2006.258.00:45:52.96#ibcon#wrote, iclass 29, count 0 2006.258.00:45:52.96#ibcon#about to read 3, iclass 29, count 0 2006.258.00:45:52.99#ibcon#read 3, iclass 29, count 0 2006.258.00:45:52.99#ibcon#about to read 4, iclass 29, count 0 2006.258.00:45:52.99#ibcon#read 4, iclass 29, count 0 2006.258.00:45:52.99#ibcon#about to read 5, iclass 29, count 0 2006.258.00:45:52.99#ibcon#read 5, iclass 29, count 0 2006.258.00:45:52.99#ibcon#about to read 6, iclass 29, count 0 2006.258.00:45:52.99#ibcon#read 6, iclass 29, count 0 2006.258.00:45:52.99#ibcon#end of sib2, iclass 29, count 0 2006.258.00:45:52.99#ibcon#*after write, iclass 29, count 0 2006.258.00:45:52.99#ibcon#*before return 0, iclass 29, count 0 2006.258.00:45:52.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:45:52.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.00:45:52.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:45:52.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:45:52.99$vck44/vblo=1,629.99 2006.258.00:45:52.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.258.00:45:52.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.258.00:45:52.99#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:52.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:45:52.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:45:52.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:45:52.99#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:45:52.99#ibcon#first serial, iclass 31, count 0 2006.258.00:45:52.99#ibcon#enter sib2, iclass 31, count 0 2006.258.00:45:52.99#ibcon#flushed, iclass 31, count 0 2006.258.00:45:52.99#ibcon#about to write, iclass 31, count 0 2006.258.00:45:52.99#ibcon#wrote, iclass 31, count 0 2006.258.00:45:52.99#ibcon#about to read 3, iclass 31, count 0 2006.258.00:45:53.01#ibcon#read 3, iclass 31, count 0 2006.258.00:45:53.01#ibcon#about to read 4, iclass 31, count 0 2006.258.00:45:53.01#ibcon#read 4, iclass 31, count 0 2006.258.00:45:53.01#ibcon#about to read 5, iclass 31, count 0 2006.258.00:45:53.01#ibcon#read 5, iclass 31, count 0 2006.258.00:45:53.01#ibcon#about to read 6, iclass 31, count 0 2006.258.00:45:53.01#ibcon#read 6, iclass 31, count 0 2006.258.00:45:53.01#ibcon#end of sib2, iclass 31, count 0 2006.258.00:45:53.01#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:45:53.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:45:53.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:45:53.01#ibcon#*before write, iclass 31, count 0 2006.258.00:45:53.01#ibcon#enter sib2, iclass 31, count 0 2006.258.00:45:53.01#ibcon#flushed, iclass 31, count 0 2006.258.00:45:53.01#ibcon#about to write, iclass 31, count 0 2006.258.00:45:53.01#ibcon#wrote, iclass 31, count 0 2006.258.00:45:53.01#ibcon#about to read 3, iclass 31, count 0 2006.258.00:45:53.05#ibcon#read 3, iclass 31, count 0 2006.258.00:45:53.05#ibcon#about to read 4, iclass 31, count 0 2006.258.00:45:53.05#ibcon#read 4, iclass 31, count 0 2006.258.00:45:53.05#ibcon#about to read 5, iclass 31, count 0 2006.258.00:45:53.05#ibcon#read 5, iclass 31, count 0 2006.258.00:45:53.05#ibcon#about to read 6, iclass 31, count 0 2006.258.00:45:53.05#ibcon#read 6, iclass 31, count 0 2006.258.00:45:53.05#ibcon#end of sib2, iclass 31, count 0 2006.258.00:45:53.05#ibcon#*after write, iclass 31, count 0 2006.258.00:45:53.05#ibcon#*before return 0, iclass 31, count 0 2006.258.00:45:53.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:45:53.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.258.00:45:53.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:45:53.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:45:53.05$vck44/vb=1,4 2006.258.00:45:53.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.00:45:53.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.00:45:53.05#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:53.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:45:53.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:45:53.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:45:53.05#ibcon#enter wrdev, iclass 33, count 2 2006.258.00:45:53.05#ibcon#first serial, iclass 33, count 2 2006.258.00:45:53.05#ibcon#enter sib2, iclass 33, count 2 2006.258.00:45:53.05#ibcon#flushed, iclass 33, count 2 2006.258.00:45:53.05#ibcon#about to write, iclass 33, count 2 2006.258.00:45:53.05#ibcon#wrote, iclass 33, count 2 2006.258.00:45:53.05#ibcon#about to read 3, iclass 33, count 2 2006.258.00:45:53.07#ibcon#read 3, iclass 33, count 2 2006.258.00:45:53.07#ibcon#about to read 4, iclass 33, count 2 2006.258.00:45:53.07#ibcon#read 4, iclass 33, count 2 2006.258.00:45:53.07#ibcon#about to read 5, iclass 33, count 2 2006.258.00:45:53.07#ibcon#read 5, iclass 33, count 2 2006.258.00:45:53.07#ibcon#about to read 6, iclass 33, count 2 2006.258.00:45:53.07#ibcon#read 6, iclass 33, count 2 2006.258.00:45:53.07#ibcon#end of sib2, iclass 33, count 2 2006.258.00:45:53.07#ibcon#*mode == 0, iclass 33, count 2 2006.258.00:45:53.07#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.00:45:53.07#ibcon#[27=AT01-04\r\n] 2006.258.00:45:53.07#ibcon#*before write, iclass 33, count 2 2006.258.00:45:53.07#ibcon#enter sib2, iclass 33, count 2 2006.258.00:45:53.07#ibcon#flushed, iclass 33, count 2 2006.258.00:45:53.07#ibcon#about to write, iclass 33, count 2 2006.258.00:45:53.07#ibcon#wrote, iclass 33, count 2 2006.258.00:45:53.07#ibcon#about to read 3, iclass 33, count 2 2006.258.00:45:53.10#ibcon#read 3, iclass 33, count 2 2006.258.00:45:53.10#ibcon#about to read 4, iclass 33, count 2 2006.258.00:45:53.10#ibcon#read 4, iclass 33, count 2 2006.258.00:45:53.10#ibcon#about to read 5, iclass 33, count 2 2006.258.00:45:53.10#ibcon#read 5, iclass 33, count 2 2006.258.00:45:53.10#ibcon#about to read 6, iclass 33, count 2 2006.258.00:45:53.10#ibcon#read 6, iclass 33, count 2 2006.258.00:45:53.10#ibcon#end of sib2, iclass 33, count 2 2006.258.00:45:53.10#ibcon#*after write, iclass 33, count 2 2006.258.00:45:53.10#ibcon#*before return 0, iclass 33, count 2 2006.258.00:45:53.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:45:53.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.00:45:53.10#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.00:45:53.10#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:53.10#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:45:53.22#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:45:53.22#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:45:53.22#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:45:53.22#ibcon#first serial, iclass 33, count 0 2006.258.00:45:53.22#ibcon#enter sib2, iclass 33, count 0 2006.258.00:45:53.22#ibcon#flushed, iclass 33, count 0 2006.258.00:45:53.22#ibcon#about to write, iclass 33, count 0 2006.258.00:45:53.22#ibcon#wrote, iclass 33, count 0 2006.258.00:45:53.22#ibcon#about to read 3, iclass 33, count 0 2006.258.00:45:53.24#ibcon#read 3, iclass 33, count 0 2006.258.00:45:53.24#ibcon#about to read 4, iclass 33, count 0 2006.258.00:45:53.24#ibcon#read 4, iclass 33, count 0 2006.258.00:45:53.24#ibcon#about to read 5, iclass 33, count 0 2006.258.00:45:53.24#ibcon#read 5, iclass 33, count 0 2006.258.00:45:53.24#ibcon#about to read 6, iclass 33, count 0 2006.258.00:45:53.24#ibcon#read 6, iclass 33, count 0 2006.258.00:45:53.24#ibcon#end of sib2, iclass 33, count 0 2006.258.00:45:53.24#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:45:53.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:45:53.24#ibcon#[27=USB\r\n] 2006.258.00:45:53.24#ibcon#*before write, iclass 33, count 0 2006.258.00:45:53.24#ibcon#enter sib2, iclass 33, count 0 2006.258.00:45:53.24#ibcon#flushed, iclass 33, count 0 2006.258.00:45:53.24#ibcon#about to write, iclass 33, count 0 2006.258.00:45:53.24#ibcon#wrote, iclass 33, count 0 2006.258.00:45:53.24#ibcon#about to read 3, iclass 33, count 0 2006.258.00:45:53.27#ibcon#read 3, iclass 33, count 0 2006.258.00:45:53.27#ibcon#about to read 4, iclass 33, count 0 2006.258.00:45:53.27#ibcon#read 4, iclass 33, count 0 2006.258.00:45:53.27#ibcon#about to read 5, iclass 33, count 0 2006.258.00:45:53.27#ibcon#read 5, iclass 33, count 0 2006.258.00:45:53.27#ibcon#about to read 6, iclass 33, count 0 2006.258.00:45:53.27#ibcon#read 6, iclass 33, count 0 2006.258.00:45:53.27#ibcon#end of sib2, iclass 33, count 0 2006.258.00:45:53.27#ibcon#*after write, iclass 33, count 0 2006.258.00:45:53.27#ibcon#*before return 0, iclass 33, count 0 2006.258.00:45:53.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:45:53.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.00:45:53.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:45:53.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:45:53.27$vck44/vblo=2,634.99 2006.258.00:45:53.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.00:45:53.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.00:45:53.27#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:53.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:53.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:53.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:53.27#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:45:53.27#ibcon#first serial, iclass 35, count 0 2006.258.00:45:53.27#ibcon#enter sib2, iclass 35, count 0 2006.258.00:45:53.27#ibcon#flushed, iclass 35, count 0 2006.258.00:45:53.27#ibcon#about to write, iclass 35, count 0 2006.258.00:45:53.27#ibcon#wrote, iclass 35, count 0 2006.258.00:45:53.27#ibcon#about to read 3, iclass 35, count 0 2006.258.00:45:53.29#ibcon#read 3, iclass 35, count 0 2006.258.00:45:53.29#ibcon#about to read 4, iclass 35, count 0 2006.258.00:45:53.29#ibcon#read 4, iclass 35, count 0 2006.258.00:45:53.29#ibcon#about to read 5, iclass 35, count 0 2006.258.00:45:53.29#ibcon#read 5, iclass 35, count 0 2006.258.00:45:53.29#ibcon#about to read 6, iclass 35, count 0 2006.258.00:45:53.29#ibcon#read 6, iclass 35, count 0 2006.258.00:45:53.29#ibcon#end of sib2, iclass 35, count 0 2006.258.00:45:53.29#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:45:53.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:45:53.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:45:53.29#ibcon#*before write, iclass 35, count 0 2006.258.00:45:53.29#ibcon#enter sib2, iclass 35, count 0 2006.258.00:45:53.29#ibcon#flushed, iclass 35, count 0 2006.258.00:45:53.29#ibcon#about to write, iclass 35, count 0 2006.258.00:45:53.29#ibcon#wrote, iclass 35, count 0 2006.258.00:45:53.29#ibcon#about to read 3, iclass 35, count 0 2006.258.00:45:53.33#ibcon#read 3, iclass 35, count 0 2006.258.00:45:53.33#ibcon#about to read 4, iclass 35, count 0 2006.258.00:45:53.33#ibcon#read 4, iclass 35, count 0 2006.258.00:45:53.33#ibcon#about to read 5, iclass 35, count 0 2006.258.00:45:53.33#ibcon#read 5, iclass 35, count 0 2006.258.00:45:53.33#ibcon#about to read 6, iclass 35, count 0 2006.258.00:45:53.33#ibcon#read 6, iclass 35, count 0 2006.258.00:45:53.33#ibcon#end of sib2, iclass 35, count 0 2006.258.00:45:53.33#ibcon#*after write, iclass 35, count 0 2006.258.00:45:53.33#ibcon#*before return 0, iclass 35, count 0 2006.258.00:45:53.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:53.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.00:45:53.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:45:53.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:45:53.33$vck44/vb=2,5 2006.258.00:45:53.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.00:45:53.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.00:45:53.33#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:53.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:53.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:53.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:53.39#ibcon#enter wrdev, iclass 37, count 2 2006.258.00:45:53.39#ibcon#first serial, iclass 37, count 2 2006.258.00:45:53.39#ibcon#enter sib2, iclass 37, count 2 2006.258.00:45:53.39#ibcon#flushed, iclass 37, count 2 2006.258.00:45:53.39#ibcon#about to write, iclass 37, count 2 2006.258.00:45:53.39#ibcon#wrote, iclass 37, count 2 2006.258.00:45:53.39#ibcon#about to read 3, iclass 37, count 2 2006.258.00:45:53.41#ibcon#read 3, iclass 37, count 2 2006.258.00:45:53.41#ibcon#about to read 4, iclass 37, count 2 2006.258.00:45:53.41#ibcon#read 4, iclass 37, count 2 2006.258.00:45:53.41#ibcon#about to read 5, iclass 37, count 2 2006.258.00:45:53.41#ibcon#read 5, iclass 37, count 2 2006.258.00:45:53.41#ibcon#about to read 6, iclass 37, count 2 2006.258.00:45:53.41#ibcon#read 6, iclass 37, count 2 2006.258.00:45:53.41#ibcon#end of sib2, iclass 37, count 2 2006.258.00:45:53.41#ibcon#*mode == 0, iclass 37, count 2 2006.258.00:45:53.41#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.00:45:53.41#ibcon#[27=AT02-05\r\n] 2006.258.00:45:53.41#ibcon#*before write, iclass 37, count 2 2006.258.00:45:53.41#ibcon#enter sib2, iclass 37, count 2 2006.258.00:45:53.41#ibcon#flushed, iclass 37, count 2 2006.258.00:45:53.41#ibcon#about to write, iclass 37, count 2 2006.258.00:45:53.41#ibcon#wrote, iclass 37, count 2 2006.258.00:45:53.41#ibcon#about to read 3, iclass 37, count 2 2006.258.00:45:53.44#ibcon#read 3, iclass 37, count 2 2006.258.00:45:53.44#ibcon#about to read 4, iclass 37, count 2 2006.258.00:45:53.44#ibcon#read 4, iclass 37, count 2 2006.258.00:45:53.44#ibcon#about to read 5, iclass 37, count 2 2006.258.00:45:53.44#ibcon#read 5, iclass 37, count 2 2006.258.00:45:53.44#ibcon#about to read 6, iclass 37, count 2 2006.258.00:45:53.44#ibcon#read 6, iclass 37, count 2 2006.258.00:45:53.44#ibcon#end of sib2, iclass 37, count 2 2006.258.00:45:53.44#ibcon#*after write, iclass 37, count 2 2006.258.00:45:53.52#ibcon#*before return 0, iclass 37, count 2 2006.258.00:45:53.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:53.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.00:45:53.52#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.00:45:53.52#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:53.52#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:53.64#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:53.64#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:53.64#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:45:53.64#ibcon#first serial, iclass 37, count 0 2006.258.00:45:53.64#ibcon#enter sib2, iclass 37, count 0 2006.258.00:45:53.64#ibcon#flushed, iclass 37, count 0 2006.258.00:45:53.64#ibcon#about to write, iclass 37, count 0 2006.258.00:45:53.64#ibcon#wrote, iclass 37, count 0 2006.258.00:45:53.64#ibcon#about to read 3, iclass 37, count 0 2006.258.00:45:53.66#ibcon#read 3, iclass 37, count 0 2006.258.00:45:53.66#ibcon#about to read 4, iclass 37, count 0 2006.258.00:45:53.66#ibcon#read 4, iclass 37, count 0 2006.258.00:45:53.66#ibcon#about to read 5, iclass 37, count 0 2006.258.00:45:53.66#ibcon#read 5, iclass 37, count 0 2006.258.00:45:53.66#ibcon#about to read 6, iclass 37, count 0 2006.258.00:45:53.66#ibcon#read 6, iclass 37, count 0 2006.258.00:45:53.66#ibcon#end of sib2, iclass 37, count 0 2006.258.00:45:53.66#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:45:53.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:45:53.66#ibcon#[27=USB\r\n] 2006.258.00:45:53.66#ibcon#*before write, iclass 37, count 0 2006.258.00:45:53.66#ibcon#enter sib2, iclass 37, count 0 2006.258.00:45:53.66#ibcon#flushed, iclass 37, count 0 2006.258.00:45:53.66#ibcon#about to write, iclass 37, count 0 2006.258.00:45:53.66#ibcon#wrote, iclass 37, count 0 2006.258.00:45:53.66#ibcon#about to read 3, iclass 37, count 0 2006.258.00:45:53.69#ibcon#read 3, iclass 37, count 0 2006.258.00:45:53.69#ibcon#about to read 4, iclass 37, count 0 2006.258.00:45:53.69#ibcon#read 4, iclass 37, count 0 2006.258.00:45:53.69#ibcon#about to read 5, iclass 37, count 0 2006.258.00:45:53.69#ibcon#read 5, iclass 37, count 0 2006.258.00:45:53.69#ibcon#about to read 6, iclass 37, count 0 2006.258.00:45:53.69#ibcon#read 6, iclass 37, count 0 2006.258.00:45:53.69#ibcon#end of sib2, iclass 37, count 0 2006.258.00:45:53.69#ibcon#*after write, iclass 37, count 0 2006.258.00:45:53.69#ibcon#*before return 0, iclass 37, count 0 2006.258.00:45:53.69#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:53.69#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.00:45:53.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:45:53.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:45:53.69$vck44/vblo=3,649.99 2006.258.00:45:53.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.00:45:53.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.00:45:53.69#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:53.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:53.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:53.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:53.69#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:45:53.69#ibcon#first serial, iclass 39, count 0 2006.258.00:45:53.69#ibcon#enter sib2, iclass 39, count 0 2006.258.00:45:53.69#ibcon#flushed, iclass 39, count 0 2006.258.00:45:53.69#ibcon#about to write, iclass 39, count 0 2006.258.00:45:53.69#ibcon#wrote, iclass 39, count 0 2006.258.00:45:53.69#ibcon#about to read 3, iclass 39, count 0 2006.258.00:45:53.71#ibcon#read 3, iclass 39, count 0 2006.258.00:45:53.71#ibcon#about to read 4, iclass 39, count 0 2006.258.00:45:53.71#ibcon#read 4, iclass 39, count 0 2006.258.00:45:53.71#ibcon#about to read 5, iclass 39, count 0 2006.258.00:45:53.71#ibcon#read 5, iclass 39, count 0 2006.258.00:45:53.71#ibcon#about to read 6, iclass 39, count 0 2006.258.00:45:53.71#ibcon#read 6, iclass 39, count 0 2006.258.00:45:53.71#ibcon#end of sib2, iclass 39, count 0 2006.258.00:45:53.71#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:45:53.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:45:53.71#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:45:53.71#ibcon#*before write, iclass 39, count 0 2006.258.00:45:53.71#ibcon#enter sib2, iclass 39, count 0 2006.258.00:45:53.71#ibcon#flushed, iclass 39, count 0 2006.258.00:45:53.71#ibcon#about to write, iclass 39, count 0 2006.258.00:45:53.71#ibcon#wrote, iclass 39, count 0 2006.258.00:45:53.71#ibcon#about to read 3, iclass 39, count 0 2006.258.00:45:53.75#ibcon#read 3, iclass 39, count 0 2006.258.00:45:53.75#ibcon#about to read 4, iclass 39, count 0 2006.258.00:45:53.75#ibcon#read 4, iclass 39, count 0 2006.258.00:45:53.75#ibcon#about to read 5, iclass 39, count 0 2006.258.00:45:53.75#ibcon#read 5, iclass 39, count 0 2006.258.00:45:53.75#ibcon#about to read 6, iclass 39, count 0 2006.258.00:45:53.75#ibcon#read 6, iclass 39, count 0 2006.258.00:45:53.75#ibcon#end of sib2, iclass 39, count 0 2006.258.00:45:53.75#ibcon#*after write, iclass 39, count 0 2006.258.00:45:53.75#ibcon#*before return 0, iclass 39, count 0 2006.258.00:45:53.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:53.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.00:45:53.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:45:53.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:45:53.75$vck44/vb=3,4 2006.258.00:45:53.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.00:45:53.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.00:45:53.75#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:53.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:53.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:53.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:53.81#ibcon#enter wrdev, iclass 3, count 2 2006.258.00:45:53.81#ibcon#first serial, iclass 3, count 2 2006.258.00:45:53.81#ibcon#enter sib2, iclass 3, count 2 2006.258.00:45:53.81#ibcon#flushed, iclass 3, count 2 2006.258.00:45:53.81#ibcon#about to write, iclass 3, count 2 2006.258.00:45:53.81#ibcon#wrote, iclass 3, count 2 2006.258.00:45:53.81#ibcon#about to read 3, iclass 3, count 2 2006.258.00:45:53.83#ibcon#read 3, iclass 3, count 2 2006.258.00:45:53.83#ibcon#about to read 4, iclass 3, count 2 2006.258.00:45:53.83#ibcon#read 4, iclass 3, count 2 2006.258.00:45:53.83#ibcon#about to read 5, iclass 3, count 2 2006.258.00:45:53.83#ibcon#read 5, iclass 3, count 2 2006.258.00:45:53.83#ibcon#about to read 6, iclass 3, count 2 2006.258.00:45:53.83#ibcon#read 6, iclass 3, count 2 2006.258.00:45:53.83#ibcon#end of sib2, iclass 3, count 2 2006.258.00:45:53.83#ibcon#*mode == 0, iclass 3, count 2 2006.258.00:45:53.83#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.00:45:53.83#ibcon#[27=AT03-04\r\n] 2006.258.00:45:53.83#ibcon#*before write, iclass 3, count 2 2006.258.00:45:53.83#ibcon#enter sib2, iclass 3, count 2 2006.258.00:45:53.83#ibcon#flushed, iclass 3, count 2 2006.258.00:45:53.83#ibcon#about to write, iclass 3, count 2 2006.258.00:45:53.83#ibcon#wrote, iclass 3, count 2 2006.258.00:45:53.83#ibcon#about to read 3, iclass 3, count 2 2006.258.00:45:53.86#ibcon#read 3, iclass 3, count 2 2006.258.00:45:53.86#ibcon#about to read 4, iclass 3, count 2 2006.258.00:45:53.86#ibcon#read 4, iclass 3, count 2 2006.258.00:45:53.86#ibcon#about to read 5, iclass 3, count 2 2006.258.00:45:53.86#ibcon#read 5, iclass 3, count 2 2006.258.00:45:53.86#ibcon#about to read 6, iclass 3, count 2 2006.258.00:45:53.86#ibcon#read 6, iclass 3, count 2 2006.258.00:45:53.86#ibcon#end of sib2, iclass 3, count 2 2006.258.00:45:53.86#ibcon#*after write, iclass 3, count 2 2006.258.00:45:53.86#ibcon#*before return 0, iclass 3, count 2 2006.258.00:45:53.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:53.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.00:45:53.86#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.00:45:53.86#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:53.86#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:53.98#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:53.98#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:53.98#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:45:53.98#ibcon#first serial, iclass 3, count 0 2006.258.00:45:53.98#ibcon#enter sib2, iclass 3, count 0 2006.258.00:45:53.98#ibcon#flushed, iclass 3, count 0 2006.258.00:45:53.98#ibcon#about to write, iclass 3, count 0 2006.258.00:45:53.98#ibcon#wrote, iclass 3, count 0 2006.258.00:45:53.98#ibcon#about to read 3, iclass 3, count 0 2006.258.00:45:54.00#ibcon#read 3, iclass 3, count 0 2006.258.00:45:54.00#ibcon#about to read 4, iclass 3, count 0 2006.258.00:45:54.00#ibcon#read 4, iclass 3, count 0 2006.258.00:45:54.00#ibcon#about to read 5, iclass 3, count 0 2006.258.00:45:54.00#ibcon#read 5, iclass 3, count 0 2006.258.00:45:54.00#ibcon#about to read 6, iclass 3, count 0 2006.258.00:45:54.00#ibcon#read 6, iclass 3, count 0 2006.258.00:45:54.00#ibcon#end of sib2, iclass 3, count 0 2006.258.00:45:54.00#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:45:54.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:45:54.00#ibcon#[27=USB\r\n] 2006.258.00:45:54.00#ibcon#*before write, iclass 3, count 0 2006.258.00:45:54.00#ibcon#enter sib2, iclass 3, count 0 2006.258.00:45:54.00#ibcon#flushed, iclass 3, count 0 2006.258.00:45:54.00#ibcon#about to write, iclass 3, count 0 2006.258.00:45:54.00#ibcon#wrote, iclass 3, count 0 2006.258.00:45:54.00#ibcon#about to read 3, iclass 3, count 0 2006.258.00:45:54.03#ibcon#read 3, iclass 3, count 0 2006.258.00:45:54.03#ibcon#about to read 4, iclass 3, count 0 2006.258.00:45:54.03#ibcon#read 4, iclass 3, count 0 2006.258.00:45:54.03#ibcon#about to read 5, iclass 3, count 0 2006.258.00:45:54.03#ibcon#read 5, iclass 3, count 0 2006.258.00:45:54.03#ibcon#about to read 6, iclass 3, count 0 2006.258.00:45:54.03#ibcon#read 6, iclass 3, count 0 2006.258.00:45:54.03#ibcon#end of sib2, iclass 3, count 0 2006.258.00:45:54.03#ibcon#*after write, iclass 3, count 0 2006.258.00:45:54.03#ibcon#*before return 0, iclass 3, count 0 2006.258.00:45:54.03#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:54.03#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.00:45:54.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:45:54.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:45:54.03$vck44/vblo=4,679.99 2006.258.00:45:54.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.00:45:54.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.00:45:54.03#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:54.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:54.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:54.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:54.03#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:45:54.03#ibcon#first serial, iclass 5, count 0 2006.258.00:45:54.03#ibcon#enter sib2, iclass 5, count 0 2006.258.00:45:54.03#ibcon#flushed, iclass 5, count 0 2006.258.00:45:54.03#ibcon#about to write, iclass 5, count 0 2006.258.00:45:54.03#ibcon#wrote, iclass 5, count 0 2006.258.00:45:54.03#ibcon#about to read 3, iclass 5, count 0 2006.258.00:45:54.05#ibcon#read 3, iclass 5, count 0 2006.258.00:45:54.05#ibcon#about to read 4, iclass 5, count 0 2006.258.00:45:54.05#ibcon#read 4, iclass 5, count 0 2006.258.00:45:54.05#ibcon#about to read 5, iclass 5, count 0 2006.258.00:45:54.05#ibcon#read 5, iclass 5, count 0 2006.258.00:45:54.05#ibcon#about to read 6, iclass 5, count 0 2006.258.00:45:54.05#ibcon#read 6, iclass 5, count 0 2006.258.00:45:54.05#ibcon#end of sib2, iclass 5, count 0 2006.258.00:45:54.05#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:45:54.05#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:45:54.05#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:45:54.05#ibcon#*before write, iclass 5, count 0 2006.258.00:45:54.05#ibcon#enter sib2, iclass 5, count 0 2006.258.00:45:54.05#ibcon#flushed, iclass 5, count 0 2006.258.00:45:54.05#ibcon#about to write, iclass 5, count 0 2006.258.00:45:54.05#ibcon#wrote, iclass 5, count 0 2006.258.00:45:54.05#ibcon#about to read 3, iclass 5, count 0 2006.258.00:45:54.09#ibcon#read 3, iclass 5, count 0 2006.258.00:45:54.09#ibcon#about to read 4, iclass 5, count 0 2006.258.00:45:54.09#ibcon#read 4, iclass 5, count 0 2006.258.00:45:54.09#ibcon#about to read 5, iclass 5, count 0 2006.258.00:45:54.09#ibcon#read 5, iclass 5, count 0 2006.258.00:45:54.09#ibcon#about to read 6, iclass 5, count 0 2006.258.00:45:54.09#ibcon#read 6, iclass 5, count 0 2006.258.00:45:54.09#ibcon#end of sib2, iclass 5, count 0 2006.258.00:45:54.09#ibcon#*after write, iclass 5, count 0 2006.258.00:45:54.09#ibcon#*before return 0, iclass 5, count 0 2006.258.00:45:54.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:54.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.00:45:54.09#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:45:54.09#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:45:54.09$vck44/vb=4,5 2006.258.00:45:54.09#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.00:45:54.09#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.00:45:54.09#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:54.09#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:54.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:54.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:54.15#ibcon#enter wrdev, iclass 7, count 2 2006.258.00:45:54.15#ibcon#first serial, iclass 7, count 2 2006.258.00:45:54.15#ibcon#enter sib2, iclass 7, count 2 2006.258.00:45:54.15#ibcon#flushed, iclass 7, count 2 2006.258.00:45:54.15#ibcon#about to write, iclass 7, count 2 2006.258.00:45:54.15#ibcon#wrote, iclass 7, count 2 2006.258.00:45:54.15#ibcon#about to read 3, iclass 7, count 2 2006.258.00:45:54.17#ibcon#read 3, iclass 7, count 2 2006.258.00:45:54.17#ibcon#about to read 4, iclass 7, count 2 2006.258.00:45:54.17#ibcon#read 4, iclass 7, count 2 2006.258.00:45:54.17#ibcon#about to read 5, iclass 7, count 2 2006.258.00:45:54.17#ibcon#read 5, iclass 7, count 2 2006.258.00:45:54.17#ibcon#about to read 6, iclass 7, count 2 2006.258.00:45:54.17#ibcon#read 6, iclass 7, count 2 2006.258.00:45:54.17#ibcon#end of sib2, iclass 7, count 2 2006.258.00:45:54.17#ibcon#*mode == 0, iclass 7, count 2 2006.258.00:45:54.17#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.00:45:54.17#ibcon#[27=AT04-05\r\n] 2006.258.00:45:54.17#ibcon#*before write, iclass 7, count 2 2006.258.00:45:54.17#ibcon#enter sib2, iclass 7, count 2 2006.258.00:45:54.17#ibcon#flushed, iclass 7, count 2 2006.258.00:45:54.17#ibcon#about to write, iclass 7, count 2 2006.258.00:45:54.17#ibcon#wrote, iclass 7, count 2 2006.258.00:45:54.17#ibcon#about to read 3, iclass 7, count 2 2006.258.00:45:54.20#ibcon#read 3, iclass 7, count 2 2006.258.00:45:54.20#ibcon#about to read 4, iclass 7, count 2 2006.258.00:45:54.20#ibcon#read 4, iclass 7, count 2 2006.258.00:45:54.20#ibcon#about to read 5, iclass 7, count 2 2006.258.00:45:54.20#ibcon#read 5, iclass 7, count 2 2006.258.00:45:54.20#ibcon#about to read 6, iclass 7, count 2 2006.258.00:45:54.20#ibcon#read 6, iclass 7, count 2 2006.258.00:45:54.20#ibcon#end of sib2, iclass 7, count 2 2006.258.00:45:54.20#ibcon#*after write, iclass 7, count 2 2006.258.00:45:54.20#ibcon#*before return 0, iclass 7, count 2 2006.258.00:45:54.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:54.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.00:45:54.20#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.00:45:54.20#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:54.20#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:54.32#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:54.32#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:54.32#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:45:54.32#ibcon#first serial, iclass 7, count 0 2006.258.00:45:54.32#ibcon#enter sib2, iclass 7, count 0 2006.258.00:45:54.32#ibcon#flushed, iclass 7, count 0 2006.258.00:45:54.32#ibcon#about to write, iclass 7, count 0 2006.258.00:45:54.32#ibcon#wrote, iclass 7, count 0 2006.258.00:45:54.32#ibcon#about to read 3, iclass 7, count 0 2006.258.00:45:54.34#ibcon#read 3, iclass 7, count 0 2006.258.00:45:54.34#ibcon#about to read 4, iclass 7, count 0 2006.258.00:45:54.34#ibcon#read 4, iclass 7, count 0 2006.258.00:45:54.34#ibcon#about to read 5, iclass 7, count 0 2006.258.00:45:54.34#ibcon#read 5, iclass 7, count 0 2006.258.00:45:54.34#ibcon#about to read 6, iclass 7, count 0 2006.258.00:45:54.34#ibcon#read 6, iclass 7, count 0 2006.258.00:45:54.34#ibcon#end of sib2, iclass 7, count 0 2006.258.00:45:54.34#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:45:54.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:45:54.34#ibcon#[27=USB\r\n] 2006.258.00:45:54.34#ibcon#*before write, iclass 7, count 0 2006.258.00:45:54.34#ibcon#enter sib2, iclass 7, count 0 2006.258.00:45:54.34#ibcon#flushed, iclass 7, count 0 2006.258.00:45:54.34#ibcon#about to write, iclass 7, count 0 2006.258.00:45:54.34#ibcon#wrote, iclass 7, count 0 2006.258.00:45:54.34#ibcon#about to read 3, iclass 7, count 0 2006.258.00:45:54.37#ibcon#read 3, iclass 7, count 0 2006.258.00:45:54.37#ibcon#about to read 4, iclass 7, count 0 2006.258.00:45:54.37#ibcon#read 4, iclass 7, count 0 2006.258.00:45:54.37#ibcon#about to read 5, iclass 7, count 0 2006.258.00:45:54.37#ibcon#read 5, iclass 7, count 0 2006.258.00:45:54.37#ibcon#about to read 6, iclass 7, count 0 2006.258.00:45:54.37#ibcon#read 6, iclass 7, count 0 2006.258.00:45:54.37#ibcon#end of sib2, iclass 7, count 0 2006.258.00:45:54.37#ibcon#*after write, iclass 7, count 0 2006.258.00:45:54.37#ibcon#*before return 0, iclass 7, count 0 2006.258.00:45:54.37#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:54.37#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.00:45:54.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:45:54.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:45:54.37$vck44/vblo=5,709.99 2006.258.00:45:54.37#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.00:45:54.37#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.00:45:54.37#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:54.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:54.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:54.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:54.37#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:45:54.37#ibcon#first serial, iclass 11, count 0 2006.258.00:45:54.37#ibcon#enter sib2, iclass 11, count 0 2006.258.00:45:54.37#ibcon#flushed, iclass 11, count 0 2006.258.00:45:54.37#ibcon#about to write, iclass 11, count 0 2006.258.00:45:54.37#ibcon#wrote, iclass 11, count 0 2006.258.00:45:54.37#ibcon#about to read 3, iclass 11, count 0 2006.258.00:45:54.39#ibcon#read 3, iclass 11, count 0 2006.258.00:45:54.39#ibcon#about to read 4, iclass 11, count 0 2006.258.00:45:54.39#ibcon#read 4, iclass 11, count 0 2006.258.00:45:54.39#ibcon#about to read 5, iclass 11, count 0 2006.258.00:45:54.39#ibcon#read 5, iclass 11, count 0 2006.258.00:45:54.39#ibcon#about to read 6, iclass 11, count 0 2006.258.00:45:54.39#ibcon#read 6, iclass 11, count 0 2006.258.00:45:54.39#ibcon#end of sib2, iclass 11, count 0 2006.258.00:45:54.39#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:45:54.39#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:45:54.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:45:54.39#ibcon#*before write, iclass 11, count 0 2006.258.00:45:54.39#ibcon#enter sib2, iclass 11, count 0 2006.258.00:45:54.39#ibcon#flushed, iclass 11, count 0 2006.258.00:45:54.39#ibcon#about to write, iclass 11, count 0 2006.258.00:45:54.39#ibcon#wrote, iclass 11, count 0 2006.258.00:45:54.39#ibcon#about to read 3, iclass 11, count 0 2006.258.00:45:54.43#ibcon#read 3, iclass 11, count 0 2006.258.00:45:54.43#ibcon#about to read 4, iclass 11, count 0 2006.258.00:45:54.43#ibcon#read 4, iclass 11, count 0 2006.258.00:45:54.43#ibcon#about to read 5, iclass 11, count 0 2006.258.00:45:54.43#ibcon#read 5, iclass 11, count 0 2006.258.00:45:54.43#ibcon#about to read 6, iclass 11, count 0 2006.258.00:45:54.43#ibcon#read 6, iclass 11, count 0 2006.258.00:45:54.43#ibcon#end of sib2, iclass 11, count 0 2006.258.00:45:54.43#ibcon#*after write, iclass 11, count 0 2006.258.00:45:54.43#ibcon#*before return 0, iclass 11, count 0 2006.258.00:45:54.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:54.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.00:45:54.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:45:54.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:45:54.43$vck44/vb=5,4 2006.258.00:45:54.43#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.00:45:54.43#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.00:45:54.43#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:54.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:54.49#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:54.49#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:54.49#ibcon#enter wrdev, iclass 13, count 2 2006.258.00:45:54.49#ibcon#first serial, iclass 13, count 2 2006.258.00:45:54.49#ibcon#enter sib2, iclass 13, count 2 2006.258.00:45:54.49#ibcon#flushed, iclass 13, count 2 2006.258.00:45:54.49#ibcon#about to write, iclass 13, count 2 2006.258.00:45:54.49#ibcon#wrote, iclass 13, count 2 2006.258.00:45:54.49#ibcon#about to read 3, iclass 13, count 2 2006.258.00:45:54.51#ibcon#read 3, iclass 13, count 2 2006.258.00:45:54.51#ibcon#about to read 4, iclass 13, count 2 2006.258.00:45:54.51#ibcon#read 4, iclass 13, count 2 2006.258.00:45:54.51#ibcon#about to read 5, iclass 13, count 2 2006.258.00:45:54.51#ibcon#read 5, iclass 13, count 2 2006.258.00:45:54.51#ibcon#about to read 6, iclass 13, count 2 2006.258.00:45:54.51#ibcon#read 6, iclass 13, count 2 2006.258.00:45:54.51#ibcon#end of sib2, iclass 13, count 2 2006.258.00:45:54.51#ibcon#*mode == 0, iclass 13, count 2 2006.258.00:45:54.51#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.00:45:54.51#ibcon#[27=AT05-04\r\n] 2006.258.00:45:54.51#ibcon#*before write, iclass 13, count 2 2006.258.00:45:54.51#ibcon#enter sib2, iclass 13, count 2 2006.258.00:45:54.51#ibcon#flushed, iclass 13, count 2 2006.258.00:45:54.51#ibcon#about to write, iclass 13, count 2 2006.258.00:45:54.51#ibcon#wrote, iclass 13, count 2 2006.258.00:45:54.51#ibcon#about to read 3, iclass 13, count 2 2006.258.00:45:54.54#ibcon#read 3, iclass 13, count 2 2006.258.00:45:54.54#ibcon#about to read 4, iclass 13, count 2 2006.258.00:45:54.54#ibcon#read 4, iclass 13, count 2 2006.258.00:45:54.54#ibcon#about to read 5, iclass 13, count 2 2006.258.00:45:54.54#ibcon#read 5, iclass 13, count 2 2006.258.00:45:54.54#ibcon#about to read 6, iclass 13, count 2 2006.258.00:45:54.54#ibcon#read 6, iclass 13, count 2 2006.258.00:45:54.54#ibcon#end of sib2, iclass 13, count 2 2006.258.00:45:54.54#ibcon#*after write, iclass 13, count 2 2006.258.00:45:54.54#ibcon#*before return 0, iclass 13, count 2 2006.258.00:45:54.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:54.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.00:45:54.58#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.00:45:54.58#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:54.58#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:54.70#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:54.70#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:54.70#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:45:54.70#ibcon#first serial, iclass 13, count 0 2006.258.00:45:54.70#ibcon#enter sib2, iclass 13, count 0 2006.258.00:45:54.70#ibcon#flushed, iclass 13, count 0 2006.258.00:45:54.70#ibcon#about to write, iclass 13, count 0 2006.258.00:45:54.70#ibcon#wrote, iclass 13, count 0 2006.258.00:45:54.70#ibcon#about to read 3, iclass 13, count 0 2006.258.00:45:54.72#ibcon#read 3, iclass 13, count 0 2006.258.00:45:54.72#ibcon#about to read 4, iclass 13, count 0 2006.258.00:45:54.72#ibcon#read 4, iclass 13, count 0 2006.258.00:45:54.72#ibcon#about to read 5, iclass 13, count 0 2006.258.00:45:54.72#ibcon#read 5, iclass 13, count 0 2006.258.00:45:54.72#ibcon#about to read 6, iclass 13, count 0 2006.258.00:45:54.72#ibcon#read 6, iclass 13, count 0 2006.258.00:45:54.72#ibcon#end of sib2, iclass 13, count 0 2006.258.00:45:54.72#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:45:54.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:45:54.72#ibcon#[27=USB\r\n] 2006.258.00:45:54.72#ibcon#*before write, iclass 13, count 0 2006.258.00:45:54.72#ibcon#enter sib2, iclass 13, count 0 2006.258.00:45:54.72#ibcon#flushed, iclass 13, count 0 2006.258.00:45:54.72#ibcon#about to write, iclass 13, count 0 2006.258.00:45:54.72#ibcon#wrote, iclass 13, count 0 2006.258.00:45:54.72#ibcon#about to read 3, iclass 13, count 0 2006.258.00:45:54.75#ibcon#read 3, iclass 13, count 0 2006.258.00:45:54.75#ibcon#about to read 4, iclass 13, count 0 2006.258.00:45:54.75#ibcon#read 4, iclass 13, count 0 2006.258.00:45:54.75#ibcon#about to read 5, iclass 13, count 0 2006.258.00:45:54.75#ibcon#read 5, iclass 13, count 0 2006.258.00:45:54.75#ibcon#about to read 6, iclass 13, count 0 2006.258.00:45:54.75#ibcon#read 6, iclass 13, count 0 2006.258.00:45:54.75#ibcon#end of sib2, iclass 13, count 0 2006.258.00:45:54.75#ibcon#*after write, iclass 13, count 0 2006.258.00:45:54.75#ibcon#*before return 0, iclass 13, count 0 2006.258.00:45:54.75#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:54.75#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.00:45:54.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:45:54.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:45:54.75$vck44/vblo=6,719.99 2006.258.00:45:54.75#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.00:45:54.75#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.00:45:54.75#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:54.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:54.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:54.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:54.75#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:45:54.75#ibcon#first serial, iclass 15, count 0 2006.258.00:45:54.75#ibcon#enter sib2, iclass 15, count 0 2006.258.00:45:54.75#ibcon#flushed, iclass 15, count 0 2006.258.00:45:54.75#ibcon#about to write, iclass 15, count 0 2006.258.00:45:54.75#ibcon#wrote, iclass 15, count 0 2006.258.00:45:54.75#ibcon#about to read 3, iclass 15, count 0 2006.258.00:45:54.77#ibcon#read 3, iclass 15, count 0 2006.258.00:45:54.77#ibcon#about to read 4, iclass 15, count 0 2006.258.00:45:54.77#ibcon#read 4, iclass 15, count 0 2006.258.00:45:54.77#ibcon#about to read 5, iclass 15, count 0 2006.258.00:45:54.77#ibcon#read 5, iclass 15, count 0 2006.258.00:45:54.77#ibcon#about to read 6, iclass 15, count 0 2006.258.00:45:54.77#ibcon#read 6, iclass 15, count 0 2006.258.00:45:54.77#ibcon#end of sib2, iclass 15, count 0 2006.258.00:45:54.77#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:45:54.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:45:54.77#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:45:54.77#ibcon#*before write, iclass 15, count 0 2006.258.00:45:54.77#ibcon#enter sib2, iclass 15, count 0 2006.258.00:45:54.77#ibcon#flushed, iclass 15, count 0 2006.258.00:45:54.77#ibcon#about to write, iclass 15, count 0 2006.258.00:45:54.77#ibcon#wrote, iclass 15, count 0 2006.258.00:45:54.77#ibcon#about to read 3, iclass 15, count 0 2006.258.00:45:54.81#ibcon#read 3, iclass 15, count 0 2006.258.00:45:54.81#ibcon#about to read 4, iclass 15, count 0 2006.258.00:45:54.81#ibcon#read 4, iclass 15, count 0 2006.258.00:45:54.81#ibcon#about to read 5, iclass 15, count 0 2006.258.00:45:54.81#ibcon#read 5, iclass 15, count 0 2006.258.00:45:54.81#ibcon#about to read 6, iclass 15, count 0 2006.258.00:45:54.81#ibcon#read 6, iclass 15, count 0 2006.258.00:45:54.81#ibcon#end of sib2, iclass 15, count 0 2006.258.00:45:54.81#ibcon#*after write, iclass 15, count 0 2006.258.00:45:54.81#ibcon#*before return 0, iclass 15, count 0 2006.258.00:45:54.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:54.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.00:45:54.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:45:54.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:45:54.81$vck44/vb=6,4 2006.258.00:45:54.81#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.00:45:54.81#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.00:45:54.81#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:54.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:54.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:54.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:54.87#ibcon#enter wrdev, iclass 17, count 2 2006.258.00:45:54.87#ibcon#first serial, iclass 17, count 2 2006.258.00:45:54.87#ibcon#enter sib2, iclass 17, count 2 2006.258.00:45:54.87#ibcon#flushed, iclass 17, count 2 2006.258.00:45:54.87#ibcon#about to write, iclass 17, count 2 2006.258.00:45:54.87#ibcon#wrote, iclass 17, count 2 2006.258.00:45:54.87#ibcon#about to read 3, iclass 17, count 2 2006.258.00:45:54.89#ibcon#read 3, iclass 17, count 2 2006.258.00:45:54.89#ibcon#about to read 4, iclass 17, count 2 2006.258.00:45:54.89#ibcon#read 4, iclass 17, count 2 2006.258.00:45:54.89#ibcon#about to read 5, iclass 17, count 2 2006.258.00:45:54.89#ibcon#read 5, iclass 17, count 2 2006.258.00:45:54.89#ibcon#about to read 6, iclass 17, count 2 2006.258.00:45:54.89#ibcon#read 6, iclass 17, count 2 2006.258.00:45:54.89#ibcon#end of sib2, iclass 17, count 2 2006.258.00:45:54.89#ibcon#*mode == 0, iclass 17, count 2 2006.258.00:45:54.89#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.00:45:54.89#ibcon#[27=AT06-04\r\n] 2006.258.00:45:54.89#ibcon#*before write, iclass 17, count 2 2006.258.00:45:54.89#ibcon#enter sib2, iclass 17, count 2 2006.258.00:45:54.89#ibcon#flushed, iclass 17, count 2 2006.258.00:45:54.89#ibcon#about to write, iclass 17, count 2 2006.258.00:45:54.89#ibcon#wrote, iclass 17, count 2 2006.258.00:45:54.89#ibcon#about to read 3, iclass 17, count 2 2006.258.00:45:54.92#ibcon#read 3, iclass 17, count 2 2006.258.00:45:54.92#ibcon#about to read 4, iclass 17, count 2 2006.258.00:45:54.92#ibcon#read 4, iclass 17, count 2 2006.258.00:45:54.92#ibcon#about to read 5, iclass 17, count 2 2006.258.00:45:54.92#ibcon#read 5, iclass 17, count 2 2006.258.00:45:54.92#ibcon#about to read 6, iclass 17, count 2 2006.258.00:45:54.92#ibcon#read 6, iclass 17, count 2 2006.258.00:45:54.92#ibcon#end of sib2, iclass 17, count 2 2006.258.00:45:54.92#ibcon#*after write, iclass 17, count 2 2006.258.00:45:54.92#ibcon#*before return 0, iclass 17, count 2 2006.258.00:45:54.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:54.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.00:45:54.92#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.00:45:54.92#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:54.92#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:55.04#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:55.04#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:55.04#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:45:55.04#ibcon#first serial, iclass 17, count 0 2006.258.00:45:55.04#ibcon#enter sib2, iclass 17, count 0 2006.258.00:45:55.04#ibcon#flushed, iclass 17, count 0 2006.258.00:45:55.04#ibcon#about to write, iclass 17, count 0 2006.258.00:45:55.04#ibcon#wrote, iclass 17, count 0 2006.258.00:45:55.04#ibcon#about to read 3, iclass 17, count 0 2006.258.00:45:55.06#ibcon#read 3, iclass 17, count 0 2006.258.00:45:55.06#ibcon#about to read 4, iclass 17, count 0 2006.258.00:45:55.06#ibcon#read 4, iclass 17, count 0 2006.258.00:45:55.06#ibcon#about to read 5, iclass 17, count 0 2006.258.00:45:55.06#ibcon#read 5, iclass 17, count 0 2006.258.00:45:55.06#ibcon#about to read 6, iclass 17, count 0 2006.258.00:45:55.06#ibcon#read 6, iclass 17, count 0 2006.258.00:45:55.06#ibcon#end of sib2, iclass 17, count 0 2006.258.00:45:55.06#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:45:55.06#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:45:55.06#ibcon#[27=USB\r\n] 2006.258.00:45:55.06#ibcon#*before write, iclass 17, count 0 2006.258.00:45:55.06#ibcon#enter sib2, iclass 17, count 0 2006.258.00:45:55.06#ibcon#flushed, iclass 17, count 0 2006.258.00:45:55.06#ibcon#about to write, iclass 17, count 0 2006.258.00:45:55.06#ibcon#wrote, iclass 17, count 0 2006.258.00:45:55.06#ibcon#about to read 3, iclass 17, count 0 2006.258.00:45:55.09#ibcon#read 3, iclass 17, count 0 2006.258.00:45:55.09#ibcon#about to read 4, iclass 17, count 0 2006.258.00:45:55.09#ibcon#read 4, iclass 17, count 0 2006.258.00:45:55.09#ibcon#about to read 5, iclass 17, count 0 2006.258.00:45:55.09#ibcon#read 5, iclass 17, count 0 2006.258.00:45:55.09#ibcon#about to read 6, iclass 17, count 0 2006.258.00:45:55.09#ibcon#read 6, iclass 17, count 0 2006.258.00:45:55.09#ibcon#end of sib2, iclass 17, count 0 2006.258.00:45:55.09#ibcon#*after write, iclass 17, count 0 2006.258.00:45:55.09#ibcon#*before return 0, iclass 17, count 0 2006.258.00:45:55.09#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:55.09#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.00:45:55.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:45:55.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:45:55.09$vck44/vblo=7,734.99 2006.258.00:45:55.09#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.00:45:55.09#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.00:45:55.09#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:55.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:55.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:55.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:55.09#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:45:55.09#ibcon#first serial, iclass 19, count 0 2006.258.00:45:55.09#ibcon#enter sib2, iclass 19, count 0 2006.258.00:45:55.09#ibcon#flushed, iclass 19, count 0 2006.258.00:45:55.09#ibcon#about to write, iclass 19, count 0 2006.258.00:45:55.09#ibcon#wrote, iclass 19, count 0 2006.258.00:45:55.09#ibcon#about to read 3, iclass 19, count 0 2006.258.00:45:55.11#ibcon#read 3, iclass 19, count 0 2006.258.00:45:55.11#ibcon#about to read 4, iclass 19, count 0 2006.258.00:45:55.11#ibcon#read 4, iclass 19, count 0 2006.258.00:45:55.11#ibcon#about to read 5, iclass 19, count 0 2006.258.00:45:55.11#ibcon#read 5, iclass 19, count 0 2006.258.00:45:55.11#ibcon#about to read 6, iclass 19, count 0 2006.258.00:45:55.11#ibcon#read 6, iclass 19, count 0 2006.258.00:45:55.11#ibcon#end of sib2, iclass 19, count 0 2006.258.00:45:55.11#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:45:55.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:45:55.11#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:45:55.11#ibcon#*before write, iclass 19, count 0 2006.258.00:45:55.11#ibcon#enter sib2, iclass 19, count 0 2006.258.00:45:55.11#ibcon#flushed, iclass 19, count 0 2006.258.00:45:55.11#ibcon#about to write, iclass 19, count 0 2006.258.00:45:55.11#ibcon#wrote, iclass 19, count 0 2006.258.00:45:55.11#ibcon#about to read 3, iclass 19, count 0 2006.258.00:45:55.15#ibcon#read 3, iclass 19, count 0 2006.258.00:45:55.15#ibcon#about to read 4, iclass 19, count 0 2006.258.00:45:55.15#ibcon#read 4, iclass 19, count 0 2006.258.00:45:55.15#ibcon#about to read 5, iclass 19, count 0 2006.258.00:45:55.15#ibcon#read 5, iclass 19, count 0 2006.258.00:45:55.15#ibcon#about to read 6, iclass 19, count 0 2006.258.00:45:55.15#ibcon#read 6, iclass 19, count 0 2006.258.00:45:55.15#ibcon#end of sib2, iclass 19, count 0 2006.258.00:45:55.15#ibcon#*after write, iclass 19, count 0 2006.258.00:45:55.15#ibcon#*before return 0, iclass 19, count 0 2006.258.00:45:55.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:55.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.00:45:55.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:45:55.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:45:55.15$vck44/vb=7,4 2006.258.00:45:55.15#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.00:45:55.15#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.00:45:55.15#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:55.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:55.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:55.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:55.21#ibcon#enter wrdev, iclass 21, count 2 2006.258.00:45:55.21#ibcon#first serial, iclass 21, count 2 2006.258.00:45:55.21#ibcon#enter sib2, iclass 21, count 2 2006.258.00:45:55.21#ibcon#flushed, iclass 21, count 2 2006.258.00:45:55.21#ibcon#about to write, iclass 21, count 2 2006.258.00:45:55.21#ibcon#wrote, iclass 21, count 2 2006.258.00:45:55.21#ibcon#about to read 3, iclass 21, count 2 2006.258.00:45:55.23#ibcon#read 3, iclass 21, count 2 2006.258.00:45:55.23#ibcon#about to read 4, iclass 21, count 2 2006.258.00:45:55.23#ibcon#read 4, iclass 21, count 2 2006.258.00:45:55.23#ibcon#about to read 5, iclass 21, count 2 2006.258.00:45:55.23#ibcon#read 5, iclass 21, count 2 2006.258.00:45:55.23#ibcon#about to read 6, iclass 21, count 2 2006.258.00:45:55.23#ibcon#read 6, iclass 21, count 2 2006.258.00:45:55.23#ibcon#end of sib2, iclass 21, count 2 2006.258.00:45:55.23#ibcon#*mode == 0, iclass 21, count 2 2006.258.00:45:55.23#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.00:45:55.23#ibcon#[27=AT07-04\r\n] 2006.258.00:45:55.23#ibcon#*before write, iclass 21, count 2 2006.258.00:45:55.23#ibcon#enter sib2, iclass 21, count 2 2006.258.00:45:55.23#ibcon#flushed, iclass 21, count 2 2006.258.00:45:55.23#ibcon#about to write, iclass 21, count 2 2006.258.00:45:55.23#ibcon#wrote, iclass 21, count 2 2006.258.00:45:55.23#ibcon#about to read 3, iclass 21, count 2 2006.258.00:45:55.26#ibcon#read 3, iclass 21, count 2 2006.258.00:45:55.26#ibcon#about to read 4, iclass 21, count 2 2006.258.00:45:55.26#ibcon#read 4, iclass 21, count 2 2006.258.00:45:55.26#ibcon#about to read 5, iclass 21, count 2 2006.258.00:45:55.26#ibcon#read 5, iclass 21, count 2 2006.258.00:45:55.26#ibcon#about to read 6, iclass 21, count 2 2006.258.00:45:55.26#ibcon#read 6, iclass 21, count 2 2006.258.00:45:55.26#ibcon#end of sib2, iclass 21, count 2 2006.258.00:45:55.26#ibcon#*after write, iclass 21, count 2 2006.258.00:45:55.26#ibcon#*before return 0, iclass 21, count 2 2006.258.00:45:55.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:55.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.00:45:55.26#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.00:45:55.26#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:55.26#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:55.38#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:55.38#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:55.38#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:45:55.38#ibcon#first serial, iclass 21, count 0 2006.258.00:45:55.38#ibcon#enter sib2, iclass 21, count 0 2006.258.00:45:55.38#ibcon#flushed, iclass 21, count 0 2006.258.00:45:55.38#ibcon#about to write, iclass 21, count 0 2006.258.00:45:55.38#ibcon#wrote, iclass 21, count 0 2006.258.00:45:55.38#ibcon#about to read 3, iclass 21, count 0 2006.258.00:45:55.40#ibcon#read 3, iclass 21, count 0 2006.258.00:45:55.40#ibcon#about to read 4, iclass 21, count 0 2006.258.00:45:55.40#ibcon#read 4, iclass 21, count 0 2006.258.00:45:55.40#ibcon#about to read 5, iclass 21, count 0 2006.258.00:45:55.40#ibcon#read 5, iclass 21, count 0 2006.258.00:45:55.40#ibcon#about to read 6, iclass 21, count 0 2006.258.00:45:55.40#ibcon#read 6, iclass 21, count 0 2006.258.00:45:55.40#ibcon#end of sib2, iclass 21, count 0 2006.258.00:45:55.40#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:45:55.40#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:45:55.40#ibcon#[27=USB\r\n] 2006.258.00:45:55.40#ibcon#*before write, iclass 21, count 0 2006.258.00:45:55.40#ibcon#enter sib2, iclass 21, count 0 2006.258.00:45:55.40#ibcon#flushed, iclass 21, count 0 2006.258.00:45:55.40#ibcon#about to write, iclass 21, count 0 2006.258.00:45:55.40#ibcon#wrote, iclass 21, count 0 2006.258.00:45:55.40#ibcon#about to read 3, iclass 21, count 0 2006.258.00:45:55.43#ibcon#read 3, iclass 21, count 0 2006.258.00:45:55.43#ibcon#about to read 4, iclass 21, count 0 2006.258.00:45:55.43#ibcon#read 4, iclass 21, count 0 2006.258.00:45:55.43#ibcon#about to read 5, iclass 21, count 0 2006.258.00:45:55.43#ibcon#read 5, iclass 21, count 0 2006.258.00:45:55.43#ibcon#about to read 6, iclass 21, count 0 2006.258.00:45:55.43#ibcon#read 6, iclass 21, count 0 2006.258.00:45:55.43#ibcon#end of sib2, iclass 21, count 0 2006.258.00:45:55.43#ibcon#*after write, iclass 21, count 0 2006.258.00:45:55.43#ibcon#*before return 0, iclass 21, count 0 2006.258.00:45:55.43#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:55.43#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.00:45:55.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:45:55.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:45:55.43$vck44/vblo=8,744.99 2006.258.00:45:55.43#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.00:45:55.43#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.00:45:55.43#ibcon#ireg 17 cls_cnt 0 2006.258.00:45:55.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:55.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:55.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:55.43#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:45:55.43#ibcon#first serial, iclass 23, count 0 2006.258.00:45:55.43#ibcon#enter sib2, iclass 23, count 0 2006.258.00:45:55.43#ibcon#flushed, iclass 23, count 0 2006.258.00:45:55.43#ibcon#about to write, iclass 23, count 0 2006.258.00:45:55.43#ibcon#wrote, iclass 23, count 0 2006.258.00:45:55.43#ibcon#about to read 3, iclass 23, count 0 2006.258.00:45:55.45#ibcon#read 3, iclass 23, count 0 2006.258.00:45:55.45#ibcon#about to read 4, iclass 23, count 0 2006.258.00:45:55.45#ibcon#read 4, iclass 23, count 0 2006.258.00:45:55.45#ibcon#about to read 5, iclass 23, count 0 2006.258.00:45:55.45#ibcon#read 5, iclass 23, count 0 2006.258.00:45:55.45#ibcon#about to read 6, iclass 23, count 0 2006.258.00:45:55.45#ibcon#read 6, iclass 23, count 0 2006.258.00:45:55.45#ibcon#end of sib2, iclass 23, count 0 2006.258.00:45:55.45#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:45:55.45#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:45:55.45#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:45:55.45#ibcon#*before write, iclass 23, count 0 2006.258.00:45:55.45#ibcon#enter sib2, iclass 23, count 0 2006.258.00:45:55.45#ibcon#flushed, iclass 23, count 0 2006.258.00:45:55.45#ibcon#about to write, iclass 23, count 0 2006.258.00:45:55.45#ibcon#wrote, iclass 23, count 0 2006.258.00:45:55.45#ibcon#about to read 3, iclass 23, count 0 2006.258.00:45:55.49#ibcon#read 3, iclass 23, count 0 2006.258.00:45:55.49#ibcon#about to read 4, iclass 23, count 0 2006.258.00:45:55.49#ibcon#read 4, iclass 23, count 0 2006.258.00:45:55.49#ibcon#about to read 5, iclass 23, count 0 2006.258.00:45:55.49#ibcon#read 5, iclass 23, count 0 2006.258.00:45:55.49#ibcon#about to read 6, iclass 23, count 0 2006.258.00:45:55.49#ibcon#read 6, iclass 23, count 0 2006.258.00:45:55.49#ibcon#end of sib2, iclass 23, count 0 2006.258.00:45:55.49#ibcon#*after write, iclass 23, count 0 2006.258.00:45:55.49#ibcon#*before return 0, iclass 23, count 0 2006.258.00:45:55.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:55.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.00:45:55.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:45:55.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:45:55.49$vck44/vb=8,4 2006.258.00:45:55.49#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.258.00:45:55.49#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.258.00:45:55.49#ibcon#ireg 11 cls_cnt 2 2006.258.00:45:55.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:55.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:55.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:55.55#ibcon#enter wrdev, iclass 25, count 2 2006.258.00:45:55.55#ibcon#first serial, iclass 25, count 2 2006.258.00:45:55.55#ibcon#enter sib2, iclass 25, count 2 2006.258.00:45:55.55#ibcon#flushed, iclass 25, count 2 2006.258.00:45:55.55#ibcon#about to write, iclass 25, count 2 2006.258.00:45:55.55#ibcon#wrote, iclass 25, count 2 2006.258.00:45:55.55#ibcon#about to read 3, iclass 25, count 2 2006.258.00:45:55.57#ibcon#read 3, iclass 25, count 2 2006.258.00:45:55.57#ibcon#about to read 4, iclass 25, count 2 2006.258.00:45:55.57#ibcon#read 4, iclass 25, count 2 2006.258.00:45:55.57#ibcon#about to read 5, iclass 25, count 2 2006.258.00:45:55.57#ibcon#read 5, iclass 25, count 2 2006.258.00:45:55.57#ibcon#about to read 6, iclass 25, count 2 2006.258.00:45:55.57#ibcon#read 6, iclass 25, count 2 2006.258.00:45:55.57#ibcon#end of sib2, iclass 25, count 2 2006.258.00:45:55.57#ibcon#*mode == 0, iclass 25, count 2 2006.258.00:45:55.57#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.258.00:45:55.57#ibcon#[27=AT08-04\r\n] 2006.258.00:45:55.57#ibcon#*before write, iclass 25, count 2 2006.258.00:45:55.57#ibcon#enter sib2, iclass 25, count 2 2006.258.00:45:55.57#ibcon#flushed, iclass 25, count 2 2006.258.00:45:55.57#ibcon#about to write, iclass 25, count 2 2006.258.00:45:55.57#ibcon#wrote, iclass 25, count 2 2006.258.00:45:55.57#ibcon#about to read 3, iclass 25, count 2 2006.258.00:45:55.60#ibcon#read 3, iclass 25, count 2 2006.258.00:45:55.63#ibcon#about to read 4, iclass 25, count 2 2006.258.00:45:55.63#ibcon#read 4, iclass 25, count 2 2006.258.00:45:55.63#ibcon#about to read 5, iclass 25, count 2 2006.258.00:45:55.63#ibcon#read 5, iclass 25, count 2 2006.258.00:45:55.63#ibcon#about to read 6, iclass 25, count 2 2006.258.00:45:55.63#ibcon#read 6, iclass 25, count 2 2006.258.00:45:55.63#ibcon#end of sib2, iclass 25, count 2 2006.258.00:45:55.63#ibcon#*after write, iclass 25, count 2 2006.258.00:45:55.63#ibcon#*before return 0, iclass 25, count 2 2006.258.00:45:55.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:55.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.258.00:45:55.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.258.00:45:55.63#ibcon#ireg 7 cls_cnt 0 2006.258.00:45:55.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:55.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:55.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:55.75#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:45:55.75#ibcon#first serial, iclass 25, count 0 2006.258.00:45:55.75#ibcon#enter sib2, iclass 25, count 0 2006.258.00:45:55.75#ibcon#flushed, iclass 25, count 0 2006.258.00:45:55.75#ibcon#about to write, iclass 25, count 0 2006.258.00:45:55.75#ibcon#wrote, iclass 25, count 0 2006.258.00:45:55.75#ibcon#about to read 3, iclass 25, count 0 2006.258.00:45:55.77#ibcon#read 3, iclass 25, count 0 2006.258.00:45:55.77#ibcon#about to read 4, iclass 25, count 0 2006.258.00:45:55.77#ibcon#read 4, iclass 25, count 0 2006.258.00:45:55.77#ibcon#about to read 5, iclass 25, count 0 2006.258.00:45:55.77#ibcon#read 5, iclass 25, count 0 2006.258.00:45:55.77#ibcon#about to read 6, iclass 25, count 0 2006.258.00:45:55.77#ibcon#read 6, iclass 25, count 0 2006.258.00:45:55.77#ibcon#end of sib2, iclass 25, count 0 2006.258.00:45:55.77#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:45:55.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:45:55.77#ibcon#[27=USB\r\n] 2006.258.00:45:55.77#ibcon#*before write, iclass 25, count 0 2006.258.00:45:55.77#ibcon#enter sib2, iclass 25, count 0 2006.258.00:45:55.77#ibcon#flushed, iclass 25, count 0 2006.258.00:45:55.77#ibcon#about to write, iclass 25, count 0 2006.258.00:45:55.77#ibcon#wrote, iclass 25, count 0 2006.258.00:45:55.77#ibcon#about to read 3, iclass 25, count 0 2006.258.00:45:55.80#ibcon#read 3, iclass 25, count 0 2006.258.00:45:55.80#ibcon#about to read 4, iclass 25, count 0 2006.258.00:45:55.80#ibcon#read 4, iclass 25, count 0 2006.258.00:45:55.80#ibcon#about to read 5, iclass 25, count 0 2006.258.00:45:55.80#ibcon#read 5, iclass 25, count 0 2006.258.00:45:55.80#ibcon#about to read 6, iclass 25, count 0 2006.258.00:45:55.80#ibcon#read 6, iclass 25, count 0 2006.258.00:45:55.80#ibcon#end of sib2, iclass 25, count 0 2006.258.00:45:55.80#ibcon#*after write, iclass 25, count 0 2006.258.00:45:55.80#ibcon#*before return 0, iclass 25, count 0 2006.258.00:45:55.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:55.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.258.00:45:55.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:45:55.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:45:55.80$vck44/vabw=wide 2006.258.00:45:55.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.00:45:55.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.00:45:55.80#ibcon#ireg 8 cls_cnt 0 2006.258.00:45:55.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:55.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:55.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:55.80#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:45:55.80#ibcon#first serial, iclass 27, count 0 2006.258.00:45:55.80#ibcon#enter sib2, iclass 27, count 0 2006.258.00:45:55.80#ibcon#flushed, iclass 27, count 0 2006.258.00:45:55.80#ibcon#about to write, iclass 27, count 0 2006.258.00:45:55.80#ibcon#wrote, iclass 27, count 0 2006.258.00:45:55.80#ibcon#about to read 3, iclass 27, count 0 2006.258.00:45:55.82#ibcon#read 3, iclass 27, count 0 2006.258.00:45:55.82#ibcon#about to read 4, iclass 27, count 0 2006.258.00:45:55.82#ibcon#read 4, iclass 27, count 0 2006.258.00:45:55.82#ibcon#about to read 5, iclass 27, count 0 2006.258.00:45:55.82#ibcon#read 5, iclass 27, count 0 2006.258.00:45:55.82#ibcon#about to read 6, iclass 27, count 0 2006.258.00:45:55.82#ibcon#read 6, iclass 27, count 0 2006.258.00:45:55.82#ibcon#end of sib2, iclass 27, count 0 2006.258.00:45:55.82#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:45:55.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:45:55.82#ibcon#[25=BW32\r\n] 2006.258.00:45:55.82#ibcon#*before write, iclass 27, count 0 2006.258.00:45:55.82#ibcon#enter sib2, iclass 27, count 0 2006.258.00:45:55.82#ibcon#flushed, iclass 27, count 0 2006.258.00:45:55.82#ibcon#about to write, iclass 27, count 0 2006.258.00:45:55.82#ibcon#wrote, iclass 27, count 0 2006.258.00:45:55.82#ibcon#about to read 3, iclass 27, count 0 2006.258.00:45:55.85#ibcon#read 3, iclass 27, count 0 2006.258.00:45:55.85#ibcon#about to read 4, iclass 27, count 0 2006.258.00:45:55.85#ibcon#read 4, iclass 27, count 0 2006.258.00:45:55.85#ibcon#about to read 5, iclass 27, count 0 2006.258.00:45:55.85#ibcon#read 5, iclass 27, count 0 2006.258.00:45:55.85#ibcon#about to read 6, iclass 27, count 0 2006.258.00:45:55.85#ibcon#read 6, iclass 27, count 0 2006.258.00:45:55.85#ibcon#end of sib2, iclass 27, count 0 2006.258.00:45:55.85#ibcon#*after write, iclass 27, count 0 2006.258.00:45:55.85#ibcon#*before return 0, iclass 27, count 0 2006.258.00:45:55.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:55.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:45:55.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:45:55.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:45:55.85$vck44/vbbw=wide 2006.258.00:45:55.85#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.00:45:55.85#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.00:45:55.85#ibcon#ireg 8 cls_cnt 0 2006.258.00:45:55.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:45:55.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:45:55.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:45:55.92#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:45:55.92#ibcon#first serial, iclass 29, count 0 2006.258.00:45:55.92#ibcon#enter sib2, iclass 29, count 0 2006.258.00:45:55.92#ibcon#flushed, iclass 29, count 0 2006.258.00:45:55.92#ibcon#about to write, iclass 29, count 0 2006.258.00:45:55.92#ibcon#wrote, iclass 29, count 0 2006.258.00:45:55.92#ibcon#about to read 3, iclass 29, count 0 2006.258.00:45:55.94#ibcon#read 3, iclass 29, count 0 2006.258.00:45:55.94#ibcon#about to read 4, iclass 29, count 0 2006.258.00:45:55.94#ibcon#read 4, iclass 29, count 0 2006.258.00:45:55.94#ibcon#about to read 5, iclass 29, count 0 2006.258.00:45:55.94#ibcon#read 5, iclass 29, count 0 2006.258.00:45:55.94#ibcon#about to read 6, iclass 29, count 0 2006.258.00:45:55.94#ibcon#read 6, iclass 29, count 0 2006.258.00:45:55.94#ibcon#end of sib2, iclass 29, count 0 2006.258.00:45:55.94#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:45:55.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:45:55.94#ibcon#[27=BW32\r\n] 2006.258.00:45:55.94#ibcon#*before write, iclass 29, count 0 2006.258.00:45:55.94#ibcon#enter sib2, iclass 29, count 0 2006.258.00:45:55.94#ibcon#flushed, iclass 29, count 0 2006.258.00:45:55.94#ibcon#about to write, iclass 29, count 0 2006.258.00:45:55.94#ibcon#wrote, iclass 29, count 0 2006.258.00:45:55.94#ibcon#about to read 3, iclass 29, count 0 2006.258.00:45:55.97#ibcon#read 3, iclass 29, count 0 2006.258.00:45:55.97#ibcon#about to read 4, iclass 29, count 0 2006.258.00:45:55.97#ibcon#read 4, iclass 29, count 0 2006.258.00:45:55.97#ibcon#about to read 5, iclass 29, count 0 2006.258.00:45:55.97#ibcon#read 5, iclass 29, count 0 2006.258.00:45:55.97#ibcon#about to read 6, iclass 29, count 0 2006.258.00:45:55.97#ibcon#read 6, iclass 29, count 0 2006.258.00:45:55.97#ibcon#end of sib2, iclass 29, count 0 2006.258.00:45:55.97#ibcon#*after write, iclass 29, count 0 2006.258.00:45:55.97#ibcon#*before return 0, iclass 29, count 0 2006.258.00:45:55.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:45:55.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:45:55.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:45:55.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:45:55.97$setupk4/ifdk4 2006.258.00:45:55.97$ifdk4/lo= 2006.258.00:45:55.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:45:55.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:45:55.97$ifdk4/patch= 2006.258.00:45:55.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:45:55.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:45:55.97$setupk4/!*+20s 2006.258.00:45:57.41#abcon#<5=/01 1.6 4.6 22.55 731016.2\r\n> 2006.258.00:45:57.43#abcon#{5=INTERFACE CLEAR} 2006.258.00:45:57.49#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:46:07.58#abcon#<5=/01 1.6 4.6 22.55 721016.2\r\n> 2006.258.00:46:07.60#abcon#{5=INTERFACE CLEAR} 2006.258.00:46:07.66#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:46:10.33$setupk4/"tpicd 2006.258.00:46:10.33$setupk4/echo=off 2006.258.00:46:10.33$setupk4/xlog=off 2006.258.00:46:10.33:!2006.258.00:46:55 2006.258.00:46:12.14#trakl#Source acquired 2006.258.00:46:13.14#flagr#flagr/antenna,acquired 2006.258.00:46:55.00:preob 2006.258.00:46:56.14/onsource/TRACKING 2006.258.00:46:56.14:!2006.258.00:47:05 2006.258.00:47:05.00:"tape 2006.258.00:47:05.00:"st=record 2006.258.00:47:05.00:data_valid=on 2006.258.00:47:05.00:midob 2006.258.00:47:05.14/onsource/TRACKING 2006.258.00:47:05.14/wx/22.57,1016.2,72 2006.258.00:47:05.35/cable/+6.4763E-03 2006.258.00:47:06.44/va/01,08,usb,yes,33,36 2006.258.00:47:06.44/va/02,07,usb,yes,36,36 2006.258.00:47:06.44/va/03,08,usb,yes,32,34 2006.258.00:47:06.44/va/04,07,usb,yes,37,39 2006.258.00:47:06.44/va/05,04,usb,yes,33,34 2006.258.00:47:06.44/va/06,04,usb,yes,37,36 2006.258.00:47:06.44/va/07,04,usb,yes,38,38 2006.258.00:47:06.44/va/08,04,usb,yes,31,39 2006.258.00:47:06.67/valo/01,524.99,yes,locked 2006.258.00:47:06.67/valo/02,534.99,yes,locked 2006.258.00:47:06.67/valo/03,564.99,yes,locked 2006.258.00:47:06.67/valo/04,624.99,yes,locked 2006.258.00:47:06.67/valo/05,734.99,yes,locked 2006.258.00:47:06.67/valo/06,814.99,yes,locked 2006.258.00:47:06.67/valo/07,864.99,yes,locked 2006.258.00:47:06.67/valo/08,884.99,yes,locked 2006.258.00:47:07.76/vb/01,04,usb,yes,33,31 2006.258.00:47:07.76/vb/02,05,usb,yes,31,31 2006.258.00:47:07.76/vb/03,04,usb,yes,32,35 2006.258.00:47:07.76/vb/04,05,usb,yes,33,31 2006.258.00:47:07.76/vb/05,04,usb,yes,29,31 2006.258.00:47:07.76/vb/06,04,usb,yes,34,30 2006.258.00:47:07.76/vb/07,04,usb,yes,33,33 2006.258.00:47:07.76/vb/08,04,usb,yes,31,34 2006.258.00:47:07.99/vblo/01,629.99,yes,locked 2006.258.00:47:07.99/vblo/02,634.99,yes,locked 2006.258.00:47:07.99/vblo/03,649.99,yes,locked 2006.258.00:47:07.99/vblo/04,679.99,yes,locked 2006.258.00:47:07.99/vblo/05,709.99,yes,locked 2006.258.00:47:07.99/vblo/06,719.99,yes,locked 2006.258.00:47:07.99/vblo/07,734.99,yes,locked 2006.258.00:47:07.99/vblo/08,744.99,yes,locked 2006.258.00:47:08.14/vabw/8 2006.258.00:47:08.29/vbbw/8 2006.258.00:47:08.38/xfe/off,on,15.0 2006.258.00:47:08.77/ifatt/23,28,28,28 2006.258.00:47:09.07/fmout-gps/S +4.55E-07 2006.258.00:47:09.11:!2006.258.00:48:25 2006.258.00:48:25.01:data_valid=off 2006.258.00:48:25.02:"et 2006.258.00:48:25.02:!+3s 2006.258.00:48:28.03:"tape 2006.258.00:48:28.03:postob 2006.258.00:48:28.20/cable/+6.4758E-03 2006.258.00:48:28.20/wx/22.59,1016.2,73 2006.258.00:48:28.26/fmout-gps/S +4.57E-07 2006.258.00:48:28.26:scan_name=258-0051,jd0609,290 2006.258.00:48:28.26:source=oj287,085448.87,200630.6,2000.0,ccw 2006.258.00:48:29.14#flagr#flagr/antenna,new-source 2006.258.00:48:29.14:checkk5 2006.258.00:48:29.50/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:48:29.90/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:48:30.32/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:48:30.72/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:48:31.12/chk_obsdata//k5ts1/T2580047??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.258.00:48:31.52/chk_obsdata//k5ts2/T2580047??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.258.00:48:31.94/chk_obsdata//k5ts3/T2580047??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.258.00:48:32.34/chk_obsdata//k5ts4/T2580047??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.258.00:48:33.06/k5log//k5ts1_log_newline 2006.258.00:48:33.77/k5log//k5ts2_log_newline 2006.258.00:48:34.51/k5log//k5ts3_log_newline 2006.258.00:48:35.22/k5log//k5ts4_log_newline 2006.258.00:48:35.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:48:35.24:setupk4=1 2006.258.00:48:35.24$setupk4/echo=on 2006.258.00:48:35.24$setupk4/pcalon 2006.258.00:48:35.24$pcalon/"no phase cal control is implemented here 2006.258.00:48:35.24$setupk4/"tpicd=stop 2006.258.00:48:35.24$setupk4/"rec=synch_on 2006.258.00:48:35.24$setupk4/"rec_mode=128 2006.258.00:48:35.24$setupk4/!* 2006.258.00:48:35.24$setupk4/recpk4 2006.258.00:48:35.24$recpk4/recpatch= 2006.258.00:48:35.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:48:35.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:48:35.24$setupk4/vck44 2006.258.00:48:35.24$vck44/valo=1,524.99 2006.258.00:48:35.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.00:48:35.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.00:48:35.24#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:35.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:35.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:35.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:35.24#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:48:35.24#ibcon#first serial, iclass 26, count 0 2006.258.00:48:35.24#ibcon#enter sib2, iclass 26, count 0 2006.258.00:48:35.24#ibcon#flushed, iclass 26, count 0 2006.258.00:48:35.24#ibcon#about to write, iclass 26, count 0 2006.258.00:48:35.24#ibcon#wrote, iclass 26, count 0 2006.258.00:48:35.24#ibcon#about to read 3, iclass 26, count 0 2006.258.00:48:35.26#ibcon#read 3, iclass 26, count 0 2006.258.00:48:35.26#ibcon#about to read 4, iclass 26, count 0 2006.258.00:48:35.26#ibcon#read 4, iclass 26, count 0 2006.258.00:48:35.26#ibcon#about to read 5, iclass 26, count 0 2006.258.00:48:35.26#ibcon#read 5, iclass 26, count 0 2006.258.00:48:35.26#ibcon#about to read 6, iclass 26, count 0 2006.258.00:48:35.26#ibcon#read 6, iclass 26, count 0 2006.258.00:48:35.26#ibcon#end of sib2, iclass 26, count 0 2006.258.00:48:35.26#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:48:35.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:48:35.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:48:35.26#ibcon#*before write, iclass 26, count 0 2006.258.00:48:35.26#ibcon#enter sib2, iclass 26, count 0 2006.258.00:48:35.26#ibcon#flushed, iclass 26, count 0 2006.258.00:48:35.26#ibcon#about to write, iclass 26, count 0 2006.258.00:48:35.26#ibcon#wrote, iclass 26, count 0 2006.258.00:48:35.26#ibcon#about to read 3, iclass 26, count 0 2006.258.00:48:35.31#ibcon#read 3, iclass 26, count 0 2006.258.00:48:35.31#ibcon#about to read 4, iclass 26, count 0 2006.258.00:48:35.31#ibcon#read 4, iclass 26, count 0 2006.258.00:48:35.31#ibcon#about to read 5, iclass 26, count 0 2006.258.00:48:35.31#ibcon#read 5, iclass 26, count 0 2006.258.00:48:35.31#ibcon#about to read 6, iclass 26, count 0 2006.258.00:48:35.31#ibcon#read 6, iclass 26, count 0 2006.258.00:48:35.31#ibcon#end of sib2, iclass 26, count 0 2006.258.00:48:35.31#ibcon#*after write, iclass 26, count 0 2006.258.00:48:35.31#ibcon#*before return 0, iclass 26, count 0 2006.258.00:48:35.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:35.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:35.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:48:35.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:48:35.31$vck44/va=1,8 2006.258.00:48:35.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.00:48:35.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.00:48:35.31#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:35.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:35.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:35.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:35.31#ibcon#enter wrdev, iclass 28, count 2 2006.258.00:48:35.31#ibcon#first serial, iclass 28, count 2 2006.258.00:48:35.31#ibcon#enter sib2, iclass 28, count 2 2006.258.00:48:35.31#ibcon#flushed, iclass 28, count 2 2006.258.00:48:35.31#ibcon#about to write, iclass 28, count 2 2006.258.00:48:35.31#ibcon#wrote, iclass 28, count 2 2006.258.00:48:35.31#ibcon#about to read 3, iclass 28, count 2 2006.258.00:48:35.33#ibcon#read 3, iclass 28, count 2 2006.258.00:48:35.33#ibcon#about to read 4, iclass 28, count 2 2006.258.00:48:35.33#ibcon#read 4, iclass 28, count 2 2006.258.00:48:35.33#ibcon#about to read 5, iclass 28, count 2 2006.258.00:48:35.33#ibcon#read 5, iclass 28, count 2 2006.258.00:48:35.33#ibcon#about to read 6, iclass 28, count 2 2006.258.00:48:35.33#ibcon#read 6, iclass 28, count 2 2006.258.00:48:35.33#ibcon#end of sib2, iclass 28, count 2 2006.258.00:48:35.33#ibcon#*mode == 0, iclass 28, count 2 2006.258.00:48:35.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.00:48:35.33#ibcon#[25=AT01-08\r\n] 2006.258.00:48:35.33#ibcon#*before write, iclass 28, count 2 2006.258.00:48:35.33#ibcon#enter sib2, iclass 28, count 2 2006.258.00:48:35.33#ibcon#flushed, iclass 28, count 2 2006.258.00:48:35.33#ibcon#about to write, iclass 28, count 2 2006.258.00:48:35.33#ibcon#wrote, iclass 28, count 2 2006.258.00:48:35.33#ibcon#about to read 3, iclass 28, count 2 2006.258.00:48:35.36#ibcon#read 3, iclass 28, count 2 2006.258.00:48:35.36#ibcon#about to read 4, iclass 28, count 2 2006.258.00:48:35.36#ibcon#read 4, iclass 28, count 2 2006.258.00:48:35.36#ibcon#about to read 5, iclass 28, count 2 2006.258.00:48:35.36#ibcon#read 5, iclass 28, count 2 2006.258.00:48:35.36#ibcon#about to read 6, iclass 28, count 2 2006.258.00:48:35.36#ibcon#read 6, iclass 28, count 2 2006.258.00:48:35.36#ibcon#end of sib2, iclass 28, count 2 2006.258.00:48:35.36#ibcon#*after write, iclass 28, count 2 2006.258.00:48:35.36#ibcon#*before return 0, iclass 28, count 2 2006.258.00:48:35.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:35.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:35.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.00:48:35.36#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:35.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:35.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:35.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:35.48#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:48:35.48#ibcon#first serial, iclass 28, count 0 2006.258.00:48:35.48#ibcon#enter sib2, iclass 28, count 0 2006.258.00:48:35.48#ibcon#flushed, iclass 28, count 0 2006.258.00:48:35.48#ibcon#about to write, iclass 28, count 0 2006.258.00:48:35.48#ibcon#wrote, iclass 28, count 0 2006.258.00:48:35.48#ibcon#about to read 3, iclass 28, count 0 2006.258.00:48:35.50#ibcon#read 3, iclass 28, count 0 2006.258.00:48:35.50#ibcon#about to read 4, iclass 28, count 0 2006.258.00:48:35.50#ibcon#read 4, iclass 28, count 0 2006.258.00:48:35.50#ibcon#about to read 5, iclass 28, count 0 2006.258.00:48:35.50#ibcon#read 5, iclass 28, count 0 2006.258.00:48:35.50#ibcon#about to read 6, iclass 28, count 0 2006.258.00:48:35.50#ibcon#read 6, iclass 28, count 0 2006.258.00:48:35.50#ibcon#end of sib2, iclass 28, count 0 2006.258.00:48:35.50#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:48:35.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:48:35.50#ibcon#[25=USB\r\n] 2006.258.00:48:35.50#ibcon#*before write, iclass 28, count 0 2006.258.00:48:35.50#ibcon#enter sib2, iclass 28, count 0 2006.258.00:48:35.50#ibcon#flushed, iclass 28, count 0 2006.258.00:48:35.50#ibcon#about to write, iclass 28, count 0 2006.258.00:48:35.50#ibcon#wrote, iclass 28, count 0 2006.258.00:48:35.50#ibcon#about to read 3, iclass 28, count 0 2006.258.00:48:35.53#ibcon#read 3, iclass 28, count 0 2006.258.00:48:35.53#ibcon#about to read 4, iclass 28, count 0 2006.258.00:48:35.53#ibcon#read 4, iclass 28, count 0 2006.258.00:48:35.53#ibcon#about to read 5, iclass 28, count 0 2006.258.00:48:35.53#ibcon#read 5, iclass 28, count 0 2006.258.00:48:35.53#ibcon#about to read 6, iclass 28, count 0 2006.258.00:48:35.53#ibcon#read 6, iclass 28, count 0 2006.258.00:48:35.53#ibcon#end of sib2, iclass 28, count 0 2006.258.00:48:35.53#ibcon#*after write, iclass 28, count 0 2006.258.00:48:35.53#ibcon#*before return 0, iclass 28, count 0 2006.258.00:48:35.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:35.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:35.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:48:35.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:48:35.53$vck44/valo=2,534.99 2006.258.00:48:35.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.00:48:35.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.00:48:35.53#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:35.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:35.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:35.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:35.53#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:48:35.53#ibcon#first serial, iclass 30, count 0 2006.258.00:48:35.53#ibcon#enter sib2, iclass 30, count 0 2006.258.00:48:35.53#ibcon#flushed, iclass 30, count 0 2006.258.00:48:35.53#ibcon#about to write, iclass 30, count 0 2006.258.00:48:35.53#ibcon#wrote, iclass 30, count 0 2006.258.00:48:35.53#ibcon#about to read 3, iclass 30, count 0 2006.258.00:48:35.55#ibcon#read 3, iclass 30, count 0 2006.258.00:48:35.55#ibcon#about to read 4, iclass 30, count 0 2006.258.00:48:35.55#ibcon#read 4, iclass 30, count 0 2006.258.00:48:35.55#ibcon#about to read 5, iclass 30, count 0 2006.258.00:48:35.55#ibcon#read 5, iclass 30, count 0 2006.258.00:48:35.55#ibcon#about to read 6, iclass 30, count 0 2006.258.00:48:35.55#ibcon#read 6, iclass 30, count 0 2006.258.00:48:35.55#ibcon#end of sib2, iclass 30, count 0 2006.258.00:48:35.55#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:48:35.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:48:35.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:48:35.55#ibcon#*before write, iclass 30, count 0 2006.258.00:48:35.55#ibcon#enter sib2, iclass 30, count 0 2006.258.00:48:35.55#ibcon#flushed, iclass 30, count 0 2006.258.00:48:35.55#ibcon#about to write, iclass 30, count 0 2006.258.00:48:35.55#ibcon#wrote, iclass 30, count 0 2006.258.00:48:35.55#ibcon#about to read 3, iclass 30, count 0 2006.258.00:48:35.59#ibcon#read 3, iclass 30, count 0 2006.258.00:48:35.59#ibcon#about to read 4, iclass 30, count 0 2006.258.00:48:35.59#ibcon#read 4, iclass 30, count 0 2006.258.00:48:35.59#ibcon#about to read 5, iclass 30, count 0 2006.258.00:48:35.59#ibcon#read 5, iclass 30, count 0 2006.258.00:48:35.59#ibcon#about to read 6, iclass 30, count 0 2006.258.00:48:35.59#ibcon#read 6, iclass 30, count 0 2006.258.00:48:35.59#ibcon#end of sib2, iclass 30, count 0 2006.258.00:48:35.59#ibcon#*after write, iclass 30, count 0 2006.258.00:48:35.59#ibcon#*before return 0, iclass 30, count 0 2006.258.00:48:35.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:35.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:35.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:48:35.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:48:35.59$vck44/va=2,7 2006.258.00:48:35.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.258.00:48:35.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.258.00:48:35.59#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:35.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:35.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:35.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:35.65#ibcon#enter wrdev, iclass 32, count 2 2006.258.00:48:35.65#ibcon#first serial, iclass 32, count 2 2006.258.00:48:35.65#ibcon#enter sib2, iclass 32, count 2 2006.258.00:48:35.65#ibcon#flushed, iclass 32, count 2 2006.258.00:48:35.65#ibcon#about to write, iclass 32, count 2 2006.258.00:48:35.65#ibcon#wrote, iclass 32, count 2 2006.258.00:48:35.65#ibcon#about to read 3, iclass 32, count 2 2006.258.00:48:35.67#ibcon#read 3, iclass 32, count 2 2006.258.00:48:35.67#ibcon#about to read 4, iclass 32, count 2 2006.258.00:48:35.67#ibcon#read 4, iclass 32, count 2 2006.258.00:48:35.67#ibcon#about to read 5, iclass 32, count 2 2006.258.00:48:35.67#ibcon#read 5, iclass 32, count 2 2006.258.00:48:35.67#ibcon#about to read 6, iclass 32, count 2 2006.258.00:48:35.67#ibcon#read 6, iclass 32, count 2 2006.258.00:48:35.67#ibcon#end of sib2, iclass 32, count 2 2006.258.00:48:35.67#ibcon#*mode == 0, iclass 32, count 2 2006.258.00:48:35.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.258.00:48:35.67#ibcon#[25=AT02-07\r\n] 2006.258.00:48:35.67#ibcon#*before write, iclass 32, count 2 2006.258.00:48:35.67#ibcon#enter sib2, iclass 32, count 2 2006.258.00:48:35.67#ibcon#flushed, iclass 32, count 2 2006.258.00:48:35.67#ibcon#about to write, iclass 32, count 2 2006.258.00:48:35.67#ibcon#wrote, iclass 32, count 2 2006.258.00:48:35.67#ibcon#about to read 3, iclass 32, count 2 2006.258.00:48:35.70#ibcon#read 3, iclass 32, count 2 2006.258.00:48:35.70#ibcon#about to read 4, iclass 32, count 2 2006.258.00:48:35.70#ibcon#read 4, iclass 32, count 2 2006.258.00:48:35.70#ibcon#about to read 5, iclass 32, count 2 2006.258.00:48:35.70#ibcon#read 5, iclass 32, count 2 2006.258.00:48:35.70#ibcon#about to read 6, iclass 32, count 2 2006.258.00:48:35.70#ibcon#read 6, iclass 32, count 2 2006.258.00:48:35.70#ibcon#end of sib2, iclass 32, count 2 2006.258.00:48:35.70#ibcon#*after write, iclass 32, count 2 2006.258.00:48:35.70#ibcon#*before return 0, iclass 32, count 2 2006.258.00:48:35.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:35.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:35.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.258.00:48:35.70#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:35.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:35.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:35.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:35.82#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:48:35.82#ibcon#first serial, iclass 32, count 0 2006.258.00:48:35.82#ibcon#enter sib2, iclass 32, count 0 2006.258.00:48:35.82#ibcon#flushed, iclass 32, count 0 2006.258.00:48:35.82#ibcon#about to write, iclass 32, count 0 2006.258.00:48:35.82#ibcon#wrote, iclass 32, count 0 2006.258.00:48:35.82#ibcon#about to read 3, iclass 32, count 0 2006.258.00:48:35.84#ibcon#read 3, iclass 32, count 0 2006.258.00:48:35.84#ibcon#about to read 4, iclass 32, count 0 2006.258.00:48:35.84#ibcon#read 4, iclass 32, count 0 2006.258.00:48:35.84#ibcon#about to read 5, iclass 32, count 0 2006.258.00:48:35.84#ibcon#read 5, iclass 32, count 0 2006.258.00:48:35.84#ibcon#about to read 6, iclass 32, count 0 2006.258.00:48:35.84#ibcon#read 6, iclass 32, count 0 2006.258.00:48:35.84#ibcon#end of sib2, iclass 32, count 0 2006.258.00:48:35.84#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:48:35.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:48:35.84#ibcon#[25=USB\r\n] 2006.258.00:48:35.84#ibcon#*before write, iclass 32, count 0 2006.258.00:48:35.84#ibcon#enter sib2, iclass 32, count 0 2006.258.00:48:35.84#ibcon#flushed, iclass 32, count 0 2006.258.00:48:35.84#ibcon#about to write, iclass 32, count 0 2006.258.00:48:35.84#ibcon#wrote, iclass 32, count 0 2006.258.00:48:35.84#ibcon#about to read 3, iclass 32, count 0 2006.258.00:48:35.87#ibcon#read 3, iclass 32, count 0 2006.258.00:48:35.87#ibcon#about to read 4, iclass 32, count 0 2006.258.00:48:35.87#ibcon#read 4, iclass 32, count 0 2006.258.00:48:35.87#ibcon#about to read 5, iclass 32, count 0 2006.258.00:48:35.87#ibcon#read 5, iclass 32, count 0 2006.258.00:48:35.87#ibcon#about to read 6, iclass 32, count 0 2006.258.00:48:35.87#ibcon#read 6, iclass 32, count 0 2006.258.00:48:35.87#ibcon#end of sib2, iclass 32, count 0 2006.258.00:48:35.87#ibcon#*after write, iclass 32, count 0 2006.258.00:48:35.87#ibcon#*before return 0, iclass 32, count 0 2006.258.00:48:35.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:35.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:35.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:48:35.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:48:35.87$vck44/valo=3,564.99 2006.258.00:48:35.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.00:48:35.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.00:48:35.87#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:35.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:35.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:35.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:35.87#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:48:35.87#ibcon#first serial, iclass 34, count 0 2006.258.00:48:35.87#ibcon#enter sib2, iclass 34, count 0 2006.258.00:48:35.87#ibcon#flushed, iclass 34, count 0 2006.258.00:48:35.87#ibcon#about to write, iclass 34, count 0 2006.258.00:48:35.87#ibcon#wrote, iclass 34, count 0 2006.258.00:48:35.87#ibcon#about to read 3, iclass 34, count 0 2006.258.00:48:35.89#ibcon#read 3, iclass 34, count 0 2006.258.00:48:35.89#ibcon#about to read 4, iclass 34, count 0 2006.258.00:48:35.89#ibcon#read 4, iclass 34, count 0 2006.258.00:48:35.89#ibcon#about to read 5, iclass 34, count 0 2006.258.00:48:35.89#ibcon#read 5, iclass 34, count 0 2006.258.00:48:35.89#ibcon#about to read 6, iclass 34, count 0 2006.258.00:48:35.89#ibcon#read 6, iclass 34, count 0 2006.258.00:48:35.89#ibcon#end of sib2, iclass 34, count 0 2006.258.00:48:35.89#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:48:35.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:48:35.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:48:35.89#ibcon#*before write, iclass 34, count 0 2006.258.00:48:35.89#ibcon#enter sib2, iclass 34, count 0 2006.258.00:48:35.89#ibcon#flushed, iclass 34, count 0 2006.258.00:48:35.89#ibcon#about to write, iclass 34, count 0 2006.258.00:48:35.89#ibcon#wrote, iclass 34, count 0 2006.258.00:48:35.89#ibcon#about to read 3, iclass 34, count 0 2006.258.00:48:35.93#ibcon#read 3, iclass 34, count 0 2006.258.00:48:35.93#ibcon#about to read 4, iclass 34, count 0 2006.258.00:48:35.93#ibcon#read 4, iclass 34, count 0 2006.258.00:48:35.93#ibcon#about to read 5, iclass 34, count 0 2006.258.00:48:35.93#ibcon#read 5, iclass 34, count 0 2006.258.00:48:35.93#ibcon#about to read 6, iclass 34, count 0 2006.258.00:48:35.93#ibcon#read 6, iclass 34, count 0 2006.258.00:48:35.93#ibcon#end of sib2, iclass 34, count 0 2006.258.00:48:35.93#ibcon#*after write, iclass 34, count 0 2006.258.00:48:35.93#ibcon#*before return 0, iclass 34, count 0 2006.258.00:48:35.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:35.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:35.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:48:35.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:48:35.93$vck44/va=3,8 2006.258.00:48:35.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.258.00:48:35.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.258.00:48:35.93#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:35.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:35.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:35.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:35.99#ibcon#enter wrdev, iclass 36, count 2 2006.258.00:48:35.99#ibcon#first serial, iclass 36, count 2 2006.258.00:48:35.99#ibcon#enter sib2, iclass 36, count 2 2006.258.00:48:35.99#ibcon#flushed, iclass 36, count 2 2006.258.00:48:35.99#ibcon#about to write, iclass 36, count 2 2006.258.00:48:35.99#ibcon#wrote, iclass 36, count 2 2006.258.00:48:35.99#ibcon#about to read 3, iclass 36, count 2 2006.258.00:48:36.01#ibcon#read 3, iclass 36, count 2 2006.258.00:48:36.01#ibcon#about to read 4, iclass 36, count 2 2006.258.00:48:36.01#ibcon#read 4, iclass 36, count 2 2006.258.00:48:36.01#ibcon#about to read 5, iclass 36, count 2 2006.258.00:48:36.01#ibcon#read 5, iclass 36, count 2 2006.258.00:48:36.01#ibcon#about to read 6, iclass 36, count 2 2006.258.00:48:36.01#ibcon#read 6, iclass 36, count 2 2006.258.00:48:36.01#ibcon#end of sib2, iclass 36, count 2 2006.258.00:48:36.01#ibcon#*mode == 0, iclass 36, count 2 2006.258.00:48:36.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.258.00:48:36.01#ibcon#[25=AT03-08\r\n] 2006.258.00:48:36.01#ibcon#*before write, iclass 36, count 2 2006.258.00:48:36.01#ibcon#enter sib2, iclass 36, count 2 2006.258.00:48:36.01#ibcon#flushed, iclass 36, count 2 2006.258.00:48:36.01#ibcon#about to write, iclass 36, count 2 2006.258.00:48:36.01#ibcon#wrote, iclass 36, count 2 2006.258.00:48:36.01#ibcon#about to read 3, iclass 36, count 2 2006.258.00:48:36.04#ibcon#read 3, iclass 36, count 2 2006.258.00:48:36.04#ibcon#about to read 4, iclass 36, count 2 2006.258.00:48:36.04#ibcon#read 4, iclass 36, count 2 2006.258.00:48:36.04#ibcon#about to read 5, iclass 36, count 2 2006.258.00:48:36.04#ibcon#read 5, iclass 36, count 2 2006.258.00:48:36.04#ibcon#about to read 6, iclass 36, count 2 2006.258.00:48:36.04#ibcon#read 6, iclass 36, count 2 2006.258.00:48:36.04#ibcon#end of sib2, iclass 36, count 2 2006.258.00:48:36.04#ibcon#*after write, iclass 36, count 2 2006.258.00:48:36.04#ibcon#*before return 0, iclass 36, count 2 2006.258.00:48:36.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:36.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:36.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.258.00:48:36.04#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:36.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:36.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:36.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:36.16#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:48:36.16#ibcon#first serial, iclass 36, count 0 2006.258.00:48:36.16#ibcon#enter sib2, iclass 36, count 0 2006.258.00:48:36.16#ibcon#flushed, iclass 36, count 0 2006.258.00:48:36.16#ibcon#about to write, iclass 36, count 0 2006.258.00:48:36.16#ibcon#wrote, iclass 36, count 0 2006.258.00:48:36.16#ibcon#about to read 3, iclass 36, count 0 2006.258.00:48:36.18#ibcon#read 3, iclass 36, count 0 2006.258.00:48:36.18#ibcon#about to read 4, iclass 36, count 0 2006.258.00:48:36.18#ibcon#read 4, iclass 36, count 0 2006.258.00:48:36.18#ibcon#about to read 5, iclass 36, count 0 2006.258.00:48:36.18#ibcon#read 5, iclass 36, count 0 2006.258.00:48:36.18#ibcon#about to read 6, iclass 36, count 0 2006.258.00:48:36.18#ibcon#read 6, iclass 36, count 0 2006.258.00:48:36.18#ibcon#end of sib2, iclass 36, count 0 2006.258.00:48:36.18#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:48:36.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:48:36.18#ibcon#[25=USB\r\n] 2006.258.00:48:36.18#ibcon#*before write, iclass 36, count 0 2006.258.00:48:36.18#ibcon#enter sib2, iclass 36, count 0 2006.258.00:48:36.18#ibcon#flushed, iclass 36, count 0 2006.258.00:48:36.18#ibcon#about to write, iclass 36, count 0 2006.258.00:48:36.18#ibcon#wrote, iclass 36, count 0 2006.258.00:48:36.18#ibcon#about to read 3, iclass 36, count 0 2006.258.00:48:36.21#ibcon#read 3, iclass 36, count 0 2006.258.00:48:36.21#ibcon#about to read 4, iclass 36, count 0 2006.258.00:48:36.21#ibcon#read 4, iclass 36, count 0 2006.258.00:48:36.21#ibcon#about to read 5, iclass 36, count 0 2006.258.00:48:36.21#ibcon#read 5, iclass 36, count 0 2006.258.00:48:36.21#ibcon#about to read 6, iclass 36, count 0 2006.258.00:48:36.21#ibcon#read 6, iclass 36, count 0 2006.258.00:48:36.21#ibcon#end of sib2, iclass 36, count 0 2006.258.00:48:36.21#ibcon#*after write, iclass 36, count 0 2006.258.00:48:36.21#ibcon#*before return 0, iclass 36, count 0 2006.258.00:48:36.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:36.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:36.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:48:36.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:48:36.21$vck44/valo=4,624.99 2006.258.00:48:36.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.00:48:36.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.00:48:36.21#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:36.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:36.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:36.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:36.21#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:48:36.21#ibcon#first serial, iclass 38, count 0 2006.258.00:48:36.21#ibcon#enter sib2, iclass 38, count 0 2006.258.00:48:36.21#ibcon#flushed, iclass 38, count 0 2006.258.00:48:36.21#ibcon#about to write, iclass 38, count 0 2006.258.00:48:36.21#ibcon#wrote, iclass 38, count 0 2006.258.00:48:36.21#ibcon#about to read 3, iclass 38, count 0 2006.258.00:48:36.23#ibcon#read 3, iclass 38, count 0 2006.258.00:48:36.23#ibcon#about to read 4, iclass 38, count 0 2006.258.00:48:36.23#ibcon#read 4, iclass 38, count 0 2006.258.00:48:36.23#ibcon#about to read 5, iclass 38, count 0 2006.258.00:48:36.23#ibcon#read 5, iclass 38, count 0 2006.258.00:48:36.23#ibcon#about to read 6, iclass 38, count 0 2006.258.00:48:36.23#ibcon#read 6, iclass 38, count 0 2006.258.00:48:36.23#ibcon#end of sib2, iclass 38, count 0 2006.258.00:48:36.23#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:48:36.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:48:36.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:48:36.23#ibcon#*before write, iclass 38, count 0 2006.258.00:48:36.23#ibcon#enter sib2, iclass 38, count 0 2006.258.00:48:36.23#ibcon#flushed, iclass 38, count 0 2006.258.00:48:36.23#ibcon#about to write, iclass 38, count 0 2006.258.00:48:36.23#ibcon#wrote, iclass 38, count 0 2006.258.00:48:36.23#ibcon#about to read 3, iclass 38, count 0 2006.258.00:48:36.27#ibcon#read 3, iclass 38, count 0 2006.258.00:48:36.27#ibcon#about to read 4, iclass 38, count 0 2006.258.00:48:36.27#ibcon#read 4, iclass 38, count 0 2006.258.00:48:36.27#ibcon#about to read 5, iclass 38, count 0 2006.258.00:48:36.27#ibcon#read 5, iclass 38, count 0 2006.258.00:48:36.27#ibcon#about to read 6, iclass 38, count 0 2006.258.00:48:36.27#ibcon#read 6, iclass 38, count 0 2006.258.00:48:36.27#ibcon#end of sib2, iclass 38, count 0 2006.258.00:48:36.27#ibcon#*after write, iclass 38, count 0 2006.258.00:48:36.27#ibcon#*before return 0, iclass 38, count 0 2006.258.00:48:36.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:36.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:36.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:48:36.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:48:36.27$vck44/va=4,7 2006.258.00:48:36.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.258.00:48:36.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.258.00:48:36.27#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:36.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:36.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:36.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:36.33#ibcon#enter wrdev, iclass 40, count 2 2006.258.00:48:36.33#ibcon#first serial, iclass 40, count 2 2006.258.00:48:36.33#ibcon#enter sib2, iclass 40, count 2 2006.258.00:48:36.33#ibcon#flushed, iclass 40, count 2 2006.258.00:48:36.33#ibcon#about to write, iclass 40, count 2 2006.258.00:48:36.33#ibcon#wrote, iclass 40, count 2 2006.258.00:48:36.33#ibcon#about to read 3, iclass 40, count 2 2006.258.00:48:36.35#ibcon#read 3, iclass 40, count 2 2006.258.00:48:36.35#ibcon#about to read 4, iclass 40, count 2 2006.258.00:48:36.35#ibcon#read 4, iclass 40, count 2 2006.258.00:48:36.35#ibcon#about to read 5, iclass 40, count 2 2006.258.00:48:36.35#ibcon#read 5, iclass 40, count 2 2006.258.00:48:36.35#ibcon#about to read 6, iclass 40, count 2 2006.258.00:48:36.35#ibcon#read 6, iclass 40, count 2 2006.258.00:48:36.35#ibcon#end of sib2, iclass 40, count 2 2006.258.00:48:36.35#ibcon#*mode == 0, iclass 40, count 2 2006.258.00:48:36.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.258.00:48:36.35#ibcon#[25=AT04-07\r\n] 2006.258.00:48:36.35#ibcon#*before write, iclass 40, count 2 2006.258.00:48:36.35#ibcon#enter sib2, iclass 40, count 2 2006.258.00:48:36.35#ibcon#flushed, iclass 40, count 2 2006.258.00:48:36.35#ibcon#about to write, iclass 40, count 2 2006.258.00:48:36.35#ibcon#wrote, iclass 40, count 2 2006.258.00:48:36.35#ibcon#about to read 3, iclass 40, count 2 2006.258.00:48:36.38#ibcon#read 3, iclass 40, count 2 2006.258.00:48:36.38#ibcon#about to read 4, iclass 40, count 2 2006.258.00:48:36.38#ibcon#read 4, iclass 40, count 2 2006.258.00:48:36.38#ibcon#about to read 5, iclass 40, count 2 2006.258.00:48:36.38#ibcon#read 5, iclass 40, count 2 2006.258.00:48:36.38#ibcon#about to read 6, iclass 40, count 2 2006.258.00:48:36.38#ibcon#read 6, iclass 40, count 2 2006.258.00:48:36.38#ibcon#end of sib2, iclass 40, count 2 2006.258.00:48:36.38#ibcon#*after write, iclass 40, count 2 2006.258.00:48:36.38#ibcon#*before return 0, iclass 40, count 2 2006.258.00:48:36.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:36.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:36.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.258.00:48:36.38#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:36.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:36.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:36.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:36.50#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:48:36.50#ibcon#first serial, iclass 40, count 0 2006.258.00:48:36.50#ibcon#enter sib2, iclass 40, count 0 2006.258.00:48:36.50#ibcon#flushed, iclass 40, count 0 2006.258.00:48:36.50#ibcon#about to write, iclass 40, count 0 2006.258.00:48:36.50#ibcon#wrote, iclass 40, count 0 2006.258.00:48:36.50#ibcon#about to read 3, iclass 40, count 0 2006.258.00:48:36.52#ibcon#read 3, iclass 40, count 0 2006.258.00:48:36.52#ibcon#about to read 4, iclass 40, count 0 2006.258.00:48:36.52#ibcon#read 4, iclass 40, count 0 2006.258.00:48:36.52#ibcon#about to read 5, iclass 40, count 0 2006.258.00:48:36.52#ibcon#read 5, iclass 40, count 0 2006.258.00:48:36.52#ibcon#about to read 6, iclass 40, count 0 2006.258.00:48:36.52#ibcon#read 6, iclass 40, count 0 2006.258.00:48:36.52#ibcon#end of sib2, iclass 40, count 0 2006.258.00:48:36.52#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:48:36.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:48:36.52#ibcon#[25=USB\r\n] 2006.258.00:48:36.52#ibcon#*before write, iclass 40, count 0 2006.258.00:48:36.52#ibcon#enter sib2, iclass 40, count 0 2006.258.00:48:36.52#ibcon#flushed, iclass 40, count 0 2006.258.00:48:36.52#ibcon#about to write, iclass 40, count 0 2006.258.00:48:36.52#ibcon#wrote, iclass 40, count 0 2006.258.00:48:36.52#ibcon#about to read 3, iclass 40, count 0 2006.258.00:48:36.55#ibcon#read 3, iclass 40, count 0 2006.258.00:48:36.55#ibcon#about to read 4, iclass 40, count 0 2006.258.00:48:36.55#ibcon#read 4, iclass 40, count 0 2006.258.00:48:36.55#ibcon#about to read 5, iclass 40, count 0 2006.258.00:48:36.55#ibcon#read 5, iclass 40, count 0 2006.258.00:48:36.55#ibcon#about to read 6, iclass 40, count 0 2006.258.00:48:36.55#ibcon#read 6, iclass 40, count 0 2006.258.00:48:36.55#ibcon#end of sib2, iclass 40, count 0 2006.258.00:48:36.55#ibcon#*after write, iclass 40, count 0 2006.258.00:48:36.55#ibcon#*before return 0, iclass 40, count 0 2006.258.00:48:36.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:36.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:36.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:48:36.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:48:36.55$vck44/valo=5,734.99 2006.258.00:48:36.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.258.00:48:36.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.258.00:48:36.55#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:36.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:36.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:36.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:36.55#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:48:36.55#ibcon#first serial, iclass 4, count 0 2006.258.00:48:36.55#ibcon#enter sib2, iclass 4, count 0 2006.258.00:48:36.55#ibcon#flushed, iclass 4, count 0 2006.258.00:48:36.55#ibcon#about to write, iclass 4, count 0 2006.258.00:48:36.55#ibcon#wrote, iclass 4, count 0 2006.258.00:48:36.55#ibcon#about to read 3, iclass 4, count 0 2006.258.00:48:36.57#ibcon#read 3, iclass 4, count 0 2006.258.00:48:36.57#ibcon#about to read 4, iclass 4, count 0 2006.258.00:48:36.57#ibcon#read 4, iclass 4, count 0 2006.258.00:48:36.57#ibcon#about to read 5, iclass 4, count 0 2006.258.00:48:36.57#ibcon#read 5, iclass 4, count 0 2006.258.00:48:36.57#ibcon#about to read 6, iclass 4, count 0 2006.258.00:48:36.57#ibcon#read 6, iclass 4, count 0 2006.258.00:48:36.57#ibcon#end of sib2, iclass 4, count 0 2006.258.00:48:36.57#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:48:36.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:48:36.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:48:36.57#ibcon#*before write, iclass 4, count 0 2006.258.00:48:36.57#ibcon#enter sib2, iclass 4, count 0 2006.258.00:48:36.57#ibcon#flushed, iclass 4, count 0 2006.258.00:48:36.57#ibcon#about to write, iclass 4, count 0 2006.258.00:48:36.57#ibcon#wrote, iclass 4, count 0 2006.258.00:48:36.57#ibcon#about to read 3, iclass 4, count 0 2006.258.00:48:36.61#ibcon#read 3, iclass 4, count 0 2006.258.00:48:36.61#ibcon#about to read 4, iclass 4, count 0 2006.258.00:48:36.61#ibcon#read 4, iclass 4, count 0 2006.258.00:48:36.61#ibcon#about to read 5, iclass 4, count 0 2006.258.00:48:36.61#ibcon#read 5, iclass 4, count 0 2006.258.00:48:36.61#ibcon#about to read 6, iclass 4, count 0 2006.258.00:48:36.61#ibcon#read 6, iclass 4, count 0 2006.258.00:48:36.61#ibcon#end of sib2, iclass 4, count 0 2006.258.00:48:36.61#ibcon#*after write, iclass 4, count 0 2006.258.00:48:36.61#ibcon#*before return 0, iclass 4, count 0 2006.258.00:48:36.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:36.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:36.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:48:36.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:48:36.61$vck44/va=5,4 2006.258.00:48:36.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.258.00:48:36.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.258.00:48:36.61#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:36.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:36.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:36.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:36.67#ibcon#enter wrdev, iclass 6, count 2 2006.258.00:48:36.67#ibcon#first serial, iclass 6, count 2 2006.258.00:48:36.67#ibcon#enter sib2, iclass 6, count 2 2006.258.00:48:36.67#ibcon#flushed, iclass 6, count 2 2006.258.00:48:36.67#ibcon#about to write, iclass 6, count 2 2006.258.00:48:36.67#ibcon#wrote, iclass 6, count 2 2006.258.00:48:36.67#ibcon#about to read 3, iclass 6, count 2 2006.258.00:48:36.69#ibcon#read 3, iclass 6, count 2 2006.258.00:48:36.69#ibcon#about to read 4, iclass 6, count 2 2006.258.00:48:36.69#ibcon#read 4, iclass 6, count 2 2006.258.00:48:36.69#ibcon#about to read 5, iclass 6, count 2 2006.258.00:48:36.69#ibcon#read 5, iclass 6, count 2 2006.258.00:48:36.69#ibcon#about to read 6, iclass 6, count 2 2006.258.00:48:36.69#ibcon#read 6, iclass 6, count 2 2006.258.00:48:36.69#ibcon#end of sib2, iclass 6, count 2 2006.258.00:48:36.69#ibcon#*mode == 0, iclass 6, count 2 2006.258.00:48:36.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.258.00:48:36.69#ibcon#[25=AT05-04\r\n] 2006.258.00:48:36.69#ibcon#*before write, iclass 6, count 2 2006.258.00:48:36.69#ibcon#enter sib2, iclass 6, count 2 2006.258.00:48:36.69#ibcon#flushed, iclass 6, count 2 2006.258.00:48:36.69#ibcon#about to write, iclass 6, count 2 2006.258.00:48:36.69#ibcon#wrote, iclass 6, count 2 2006.258.00:48:36.69#ibcon#about to read 3, iclass 6, count 2 2006.258.00:48:36.72#ibcon#read 3, iclass 6, count 2 2006.258.00:48:36.72#ibcon#about to read 4, iclass 6, count 2 2006.258.00:48:36.72#ibcon#read 4, iclass 6, count 2 2006.258.00:48:36.72#ibcon#about to read 5, iclass 6, count 2 2006.258.00:48:36.72#ibcon#read 5, iclass 6, count 2 2006.258.00:48:36.72#ibcon#about to read 6, iclass 6, count 2 2006.258.00:48:36.72#ibcon#read 6, iclass 6, count 2 2006.258.00:48:36.72#ibcon#end of sib2, iclass 6, count 2 2006.258.00:48:36.72#ibcon#*after write, iclass 6, count 2 2006.258.00:48:36.72#ibcon#*before return 0, iclass 6, count 2 2006.258.00:48:36.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:36.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:36.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.258.00:48:36.72#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:36.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:36.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:36.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:36.84#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:48:36.84#ibcon#first serial, iclass 6, count 0 2006.258.00:48:36.84#ibcon#enter sib2, iclass 6, count 0 2006.258.00:48:36.84#ibcon#flushed, iclass 6, count 0 2006.258.00:48:36.84#ibcon#about to write, iclass 6, count 0 2006.258.00:48:36.84#ibcon#wrote, iclass 6, count 0 2006.258.00:48:36.84#ibcon#about to read 3, iclass 6, count 0 2006.258.00:48:36.86#ibcon#read 3, iclass 6, count 0 2006.258.00:48:36.86#ibcon#about to read 4, iclass 6, count 0 2006.258.00:48:36.86#ibcon#read 4, iclass 6, count 0 2006.258.00:48:36.86#ibcon#about to read 5, iclass 6, count 0 2006.258.00:48:36.86#ibcon#read 5, iclass 6, count 0 2006.258.00:48:36.86#ibcon#about to read 6, iclass 6, count 0 2006.258.00:48:36.86#ibcon#read 6, iclass 6, count 0 2006.258.00:48:36.86#ibcon#end of sib2, iclass 6, count 0 2006.258.00:48:36.86#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:48:36.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:48:36.86#ibcon#[25=USB\r\n] 2006.258.00:48:36.86#ibcon#*before write, iclass 6, count 0 2006.258.00:48:36.86#ibcon#enter sib2, iclass 6, count 0 2006.258.00:48:36.86#ibcon#flushed, iclass 6, count 0 2006.258.00:48:36.86#ibcon#about to write, iclass 6, count 0 2006.258.00:48:36.86#ibcon#wrote, iclass 6, count 0 2006.258.00:48:36.86#ibcon#about to read 3, iclass 6, count 0 2006.258.00:48:36.89#ibcon#read 3, iclass 6, count 0 2006.258.00:48:36.89#ibcon#about to read 4, iclass 6, count 0 2006.258.00:48:36.89#ibcon#read 4, iclass 6, count 0 2006.258.00:48:36.89#ibcon#about to read 5, iclass 6, count 0 2006.258.00:48:36.89#ibcon#read 5, iclass 6, count 0 2006.258.00:48:36.89#ibcon#about to read 6, iclass 6, count 0 2006.258.00:48:36.89#ibcon#read 6, iclass 6, count 0 2006.258.00:48:36.89#ibcon#end of sib2, iclass 6, count 0 2006.258.00:48:36.89#ibcon#*after write, iclass 6, count 0 2006.258.00:48:36.89#ibcon#*before return 0, iclass 6, count 0 2006.258.00:48:36.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:36.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:36.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:48:36.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:48:36.89$vck44/valo=6,814.99 2006.258.00:48:36.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.258.00:48:36.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.258.00:48:36.89#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:36.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:36.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:36.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:36.89#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:48:36.89#ibcon#first serial, iclass 10, count 0 2006.258.00:48:36.89#ibcon#enter sib2, iclass 10, count 0 2006.258.00:48:36.89#ibcon#flushed, iclass 10, count 0 2006.258.00:48:36.89#ibcon#about to write, iclass 10, count 0 2006.258.00:48:36.89#ibcon#wrote, iclass 10, count 0 2006.258.00:48:36.89#ibcon#about to read 3, iclass 10, count 0 2006.258.00:48:36.91#ibcon#read 3, iclass 10, count 0 2006.258.00:48:36.91#ibcon#about to read 4, iclass 10, count 0 2006.258.00:48:36.91#ibcon#read 4, iclass 10, count 0 2006.258.00:48:36.91#ibcon#about to read 5, iclass 10, count 0 2006.258.00:48:36.91#ibcon#read 5, iclass 10, count 0 2006.258.00:48:36.91#ibcon#about to read 6, iclass 10, count 0 2006.258.00:48:36.91#ibcon#read 6, iclass 10, count 0 2006.258.00:48:36.91#ibcon#end of sib2, iclass 10, count 0 2006.258.00:48:36.91#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:48:36.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:48:36.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:48:36.91#ibcon#*before write, iclass 10, count 0 2006.258.00:48:36.91#ibcon#enter sib2, iclass 10, count 0 2006.258.00:48:36.91#ibcon#flushed, iclass 10, count 0 2006.258.00:48:36.91#ibcon#about to write, iclass 10, count 0 2006.258.00:48:36.91#ibcon#wrote, iclass 10, count 0 2006.258.00:48:36.91#ibcon#about to read 3, iclass 10, count 0 2006.258.00:48:36.95#ibcon#read 3, iclass 10, count 0 2006.258.00:48:36.95#ibcon#about to read 4, iclass 10, count 0 2006.258.00:48:36.95#ibcon#read 4, iclass 10, count 0 2006.258.00:48:36.95#ibcon#about to read 5, iclass 10, count 0 2006.258.00:48:36.95#ibcon#read 5, iclass 10, count 0 2006.258.00:48:36.95#ibcon#about to read 6, iclass 10, count 0 2006.258.00:48:36.95#ibcon#read 6, iclass 10, count 0 2006.258.00:48:36.95#ibcon#end of sib2, iclass 10, count 0 2006.258.00:48:36.95#ibcon#*after write, iclass 10, count 0 2006.258.00:48:36.95#ibcon#*before return 0, iclass 10, count 0 2006.258.00:48:36.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:36.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:36.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:48:36.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:48:36.95$vck44/va=6,4 2006.258.00:48:36.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.258.00:48:36.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.258.00:48:36.95#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:36.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:37.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:37.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:37.01#ibcon#enter wrdev, iclass 12, count 2 2006.258.00:48:37.01#ibcon#first serial, iclass 12, count 2 2006.258.00:48:37.01#ibcon#enter sib2, iclass 12, count 2 2006.258.00:48:37.01#ibcon#flushed, iclass 12, count 2 2006.258.00:48:37.01#ibcon#about to write, iclass 12, count 2 2006.258.00:48:37.01#ibcon#wrote, iclass 12, count 2 2006.258.00:48:37.01#ibcon#about to read 3, iclass 12, count 2 2006.258.00:48:37.03#ibcon#read 3, iclass 12, count 2 2006.258.00:48:37.03#ibcon#about to read 4, iclass 12, count 2 2006.258.00:48:37.03#ibcon#read 4, iclass 12, count 2 2006.258.00:48:37.03#ibcon#about to read 5, iclass 12, count 2 2006.258.00:48:37.03#ibcon#read 5, iclass 12, count 2 2006.258.00:48:37.03#ibcon#about to read 6, iclass 12, count 2 2006.258.00:48:37.03#ibcon#read 6, iclass 12, count 2 2006.258.00:48:37.03#ibcon#end of sib2, iclass 12, count 2 2006.258.00:48:37.03#ibcon#*mode == 0, iclass 12, count 2 2006.258.00:48:37.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.258.00:48:37.03#ibcon#[25=AT06-04\r\n] 2006.258.00:48:37.03#ibcon#*before write, iclass 12, count 2 2006.258.00:48:37.03#ibcon#enter sib2, iclass 12, count 2 2006.258.00:48:37.03#ibcon#flushed, iclass 12, count 2 2006.258.00:48:37.03#ibcon#about to write, iclass 12, count 2 2006.258.00:48:37.03#ibcon#wrote, iclass 12, count 2 2006.258.00:48:37.03#ibcon#about to read 3, iclass 12, count 2 2006.258.00:48:37.06#ibcon#read 3, iclass 12, count 2 2006.258.00:48:37.06#ibcon#about to read 4, iclass 12, count 2 2006.258.00:48:37.06#ibcon#read 4, iclass 12, count 2 2006.258.00:48:37.06#ibcon#about to read 5, iclass 12, count 2 2006.258.00:48:37.06#ibcon#read 5, iclass 12, count 2 2006.258.00:48:37.06#ibcon#about to read 6, iclass 12, count 2 2006.258.00:48:37.06#ibcon#read 6, iclass 12, count 2 2006.258.00:48:37.06#ibcon#end of sib2, iclass 12, count 2 2006.258.00:48:37.06#ibcon#*after write, iclass 12, count 2 2006.258.00:48:37.06#ibcon#*before return 0, iclass 12, count 2 2006.258.00:48:37.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:37.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:37.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.258.00:48:37.06#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:37.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:37.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:37.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:37.18#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:48:37.18#ibcon#first serial, iclass 12, count 0 2006.258.00:48:37.18#ibcon#enter sib2, iclass 12, count 0 2006.258.00:48:37.18#ibcon#flushed, iclass 12, count 0 2006.258.00:48:37.18#ibcon#about to write, iclass 12, count 0 2006.258.00:48:37.18#ibcon#wrote, iclass 12, count 0 2006.258.00:48:37.18#ibcon#about to read 3, iclass 12, count 0 2006.258.00:48:37.20#ibcon#read 3, iclass 12, count 0 2006.258.00:48:37.20#ibcon#about to read 4, iclass 12, count 0 2006.258.00:48:37.20#ibcon#read 4, iclass 12, count 0 2006.258.00:48:37.20#ibcon#about to read 5, iclass 12, count 0 2006.258.00:48:37.20#ibcon#read 5, iclass 12, count 0 2006.258.00:48:37.20#ibcon#about to read 6, iclass 12, count 0 2006.258.00:48:37.20#ibcon#read 6, iclass 12, count 0 2006.258.00:48:37.20#ibcon#end of sib2, iclass 12, count 0 2006.258.00:48:37.20#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:48:37.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:48:37.20#ibcon#[25=USB\r\n] 2006.258.00:48:37.20#ibcon#*before write, iclass 12, count 0 2006.258.00:48:37.20#ibcon#enter sib2, iclass 12, count 0 2006.258.00:48:37.20#ibcon#flushed, iclass 12, count 0 2006.258.00:48:37.20#ibcon#about to write, iclass 12, count 0 2006.258.00:48:37.20#ibcon#wrote, iclass 12, count 0 2006.258.00:48:37.20#ibcon#about to read 3, iclass 12, count 0 2006.258.00:48:37.23#ibcon#read 3, iclass 12, count 0 2006.258.00:48:37.23#ibcon#about to read 4, iclass 12, count 0 2006.258.00:48:37.23#ibcon#read 4, iclass 12, count 0 2006.258.00:48:37.23#ibcon#about to read 5, iclass 12, count 0 2006.258.00:48:37.23#ibcon#read 5, iclass 12, count 0 2006.258.00:48:37.23#ibcon#about to read 6, iclass 12, count 0 2006.258.00:48:37.23#ibcon#read 6, iclass 12, count 0 2006.258.00:48:37.23#ibcon#end of sib2, iclass 12, count 0 2006.258.00:48:37.23#ibcon#*after write, iclass 12, count 0 2006.258.00:48:37.23#ibcon#*before return 0, iclass 12, count 0 2006.258.00:48:37.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:37.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:37.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:48:37.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:48:37.23$vck44/valo=7,864.99 2006.258.00:48:37.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.00:48:37.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.00:48:37.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:37.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:37.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:37.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:37.23#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:48:37.23#ibcon#first serial, iclass 14, count 0 2006.258.00:48:37.23#ibcon#enter sib2, iclass 14, count 0 2006.258.00:48:37.23#ibcon#flushed, iclass 14, count 0 2006.258.00:48:37.23#ibcon#about to write, iclass 14, count 0 2006.258.00:48:37.23#ibcon#wrote, iclass 14, count 0 2006.258.00:48:37.23#ibcon#about to read 3, iclass 14, count 0 2006.258.00:48:37.25#ibcon#read 3, iclass 14, count 0 2006.258.00:48:37.25#ibcon#about to read 4, iclass 14, count 0 2006.258.00:48:37.25#ibcon#read 4, iclass 14, count 0 2006.258.00:48:37.25#ibcon#about to read 5, iclass 14, count 0 2006.258.00:48:37.25#ibcon#read 5, iclass 14, count 0 2006.258.00:48:37.25#ibcon#about to read 6, iclass 14, count 0 2006.258.00:48:37.25#ibcon#read 6, iclass 14, count 0 2006.258.00:48:37.25#ibcon#end of sib2, iclass 14, count 0 2006.258.00:48:37.25#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:48:37.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:48:37.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:48:37.25#ibcon#*before write, iclass 14, count 0 2006.258.00:48:37.25#ibcon#enter sib2, iclass 14, count 0 2006.258.00:48:37.25#ibcon#flushed, iclass 14, count 0 2006.258.00:48:37.25#ibcon#about to write, iclass 14, count 0 2006.258.00:48:37.25#ibcon#wrote, iclass 14, count 0 2006.258.00:48:37.25#ibcon#about to read 3, iclass 14, count 0 2006.258.00:48:37.29#ibcon#read 3, iclass 14, count 0 2006.258.00:48:37.29#ibcon#about to read 4, iclass 14, count 0 2006.258.00:48:37.29#ibcon#read 4, iclass 14, count 0 2006.258.00:48:37.29#ibcon#about to read 5, iclass 14, count 0 2006.258.00:48:37.29#ibcon#read 5, iclass 14, count 0 2006.258.00:48:37.29#ibcon#about to read 6, iclass 14, count 0 2006.258.00:48:37.29#ibcon#read 6, iclass 14, count 0 2006.258.00:48:37.29#ibcon#end of sib2, iclass 14, count 0 2006.258.00:48:37.29#ibcon#*after write, iclass 14, count 0 2006.258.00:48:37.29#ibcon#*before return 0, iclass 14, count 0 2006.258.00:48:37.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:37.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:37.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:48:37.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:48:37.29$vck44/va=7,4 2006.258.00:48:37.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.258.00:48:37.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.258.00:48:37.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:37.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:37.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:37.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:37.35#ibcon#enter wrdev, iclass 16, count 2 2006.258.00:48:37.35#ibcon#first serial, iclass 16, count 2 2006.258.00:48:37.35#ibcon#enter sib2, iclass 16, count 2 2006.258.00:48:37.35#ibcon#flushed, iclass 16, count 2 2006.258.00:48:37.35#ibcon#about to write, iclass 16, count 2 2006.258.00:48:37.35#ibcon#wrote, iclass 16, count 2 2006.258.00:48:37.35#ibcon#about to read 3, iclass 16, count 2 2006.258.00:48:37.37#ibcon#read 3, iclass 16, count 2 2006.258.00:48:37.37#ibcon#about to read 4, iclass 16, count 2 2006.258.00:48:37.37#ibcon#read 4, iclass 16, count 2 2006.258.00:48:37.37#ibcon#about to read 5, iclass 16, count 2 2006.258.00:48:37.37#ibcon#read 5, iclass 16, count 2 2006.258.00:48:37.37#ibcon#about to read 6, iclass 16, count 2 2006.258.00:48:37.37#ibcon#read 6, iclass 16, count 2 2006.258.00:48:37.37#ibcon#end of sib2, iclass 16, count 2 2006.258.00:48:37.37#ibcon#*mode == 0, iclass 16, count 2 2006.258.00:48:37.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.258.00:48:37.37#ibcon#[25=AT07-04\r\n] 2006.258.00:48:37.37#ibcon#*before write, iclass 16, count 2 2006.258.00:48:37.37#ibcon#enter sib2, iclass 16, count 2 2006.258.00:48:37.37#ibcon#flushed, iclass 16, count 2 2006.258.00:48:37.37#ibcon#about to write, iclass 16, count 2 2006.258.00:48:37.37#ibcon#wrote, iclass 16, count 2 2006.258.00:48:37.37#ibcon#about to read 3, iclass 16, count 2 2006.258.00:48:37.40#ibcon#read 3, iclass 16, count 2 2006.258.00:48:37.40#ibcon#about to read 4, iclass 16, count 2 2006.258.00:48:37.40#ibcon#read 4, iclass 16, count 2 2006.258.00:48:37.40#ibcon#about to read 5, iclass 16, count 2 2006.258.00:48:37.40#ibcon#read 5, iclass 16, count 2 2006.258.00:48:37.40#ibcon#about to read 6, iclass 16, count 2 2006.258.00:48:37.40#ibcon#read 6, iclass 16, count 2 2006.258.00:48:37.40#ibcon#end of sib2, iclass 16, count 2 2006.258.00:48:37.40#ibcon#*after write, iclass 16, count 2 2006.258.00:48:37.40#ibcon#*before return 0, iclass 16, count 2 2006.258.00:48:37.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:37.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:37.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.258.00:48:37.40#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:37.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:37.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:37.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:37.52#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:48:37.52#ibcon#first serial, iclass 16, count 0 2006.258.00:48:37.52#ibcon#enter sib2, iclass 16, count 0 2006.258.00:48:37.52#ibcon#flushed, iclass 16, count 0 2006.258.00:48:37.52#ibcon#about to write, iclass 16, count 0 2006.258.00:48:37.52#ibcon#wrote, iclass 16, count 0 2006.258.00:48:37.52#ibcon#about to read 3, iclass 16, count 0 2006.258.00:48:37.54#ibcon#read 3, iclass 16, count 0 2006.258.00:48:37.54#ibcon#about to read 4, iclass 16, count 0 2006.258.00:48:37.54#ibcon#read 4, iclass 16, count 0 2006.258.00:48:37.54#ibcon#about to read 5, iclass 16, count 0 2006.258.00:48:37.54#ibcon#read 5, iclass 16, count 0 2006.258.00:48:37.54#ibcon#about to read 6, iclass 16, count 0 2006.258.00:48:37.54#ibcon#read 6, iclass 16, count 0 2006.258.00:48:37.54#ibcon#end of sib2, iclass 16, count 0 2006.258.00:48:37.54#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:48:37.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:48:37.54#ibcon#[25=USB\r\n] 2006.258.00:48:37.54#ibcon#*before write, iclass 16, count 0 2006.258.00:48:37.54#ibcon#enter sib2, iclass 16, count 0 2006.258.00:48:37.54#ibcon#flushed, iclass 16, count 0 2006.258.00:48:37.54#ibcon#about to write, iclass 16, count 0 2006.258.00:48:37.54#ibcon#wrote, iclass 16, count 0 2006.258.00:48:37.54#ibcon#about to read 3, iclass 16, count 0 2006.258.00:48:37.57#ibcon#read 3, iclass 16, count 0 2006.258.00:48:37.57#ibcon#about to read 4, iclass 16, count 0 2006.258.00:48:37.57#ibcon#read 4, iclass 16, count 0 2006.258.00:48:37.57#ibcon#about to read 5, iclass 16, count 0 2006.258.00:48:37.57#ibcon#read 5, iclass 16, count 0 2006.258.00:48:37.57#ibcon#about to read 6, iclass 16, count 0 2006.258.00:48:37.57#ibcon#read 6, iclass 16, count 0 2006.258.00:48:37.57#ibcon#end of sib2, iclass 16, count 0 2006.258.00:48:37.57#ibcon#*after write, iclass 16, count 0 2006.258.00:48:37.57#ibcon#*before return 0, iclass 16, count 0 2006.258.00:48:37.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:37.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:37.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:48:37.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:48:37.57$vck44/valo=8,884.99 2006.258.00:48:37.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.00:48:37.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.00:48:37.57#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:37.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:48:37.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:48:37.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:48:37.57#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:48:37.57#ibcon#first serial, iclass 18, count 0 2006.258.00:48:37.57#ibcon#enter sib2, iclass 18, count 0 2006.258.00:48:37.57#ibcon#flushed, iclass 18, count 0 2006.258.00:48:37.57#ibcon#about to write, iclass 18, count 0 2006.258.00:48:37.57#ibcon#wrote, iclass 18, count 0 2006.258.00:48:37.57#ibcon#about to read 3, iclass 18, count 0 2006.258.00:48:37.59#ibcon#read 3, iclass 18, count 0 2006.258.00:48:37.59#ibcon#about to read 4, iclass 18, count 0 2006.258.00:48:37.59#ibcon#read 4, iclass 18, count 0 2006.258.00:48:37.59#ibcon#about to read 5, iclass 18, count 0 2006.258.00:48:37.59#ibcon#read 5, iclass 18, count 0 2006.258.00:48:37.59#ibcon#about to read 6, iclass 18, count 0 2006.258.00:48:37.59#ibcon#read 6, iclass 18, count 0 2006.258.00:48:37.59#ibcon#end of sib2, iclass 18, count 0 2006.258.00:48:37.59#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:48:37.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:48:37.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:48:37.59#ibcon#*before write, iclass 18, count 0 2006.258.00:48:37.59#ibcon#enter sib2, iclass 18, count 0 2006.258.00:48:37.59#ibcon#flushed, iclass 18, count 0 2006.258.00:48:37.59#ibcon#about to write, iclass 18, count 0 2006.258.00:48:37.59#ibcon#wrote, iclass 18, count 0 2006.258.00:48:37.59#ibcon#about to read 3, iclass 18, count 0 2006.258.00:48:37.63#ibcon#read 3, iclass 18, count 0 2006.258.00:48:37.63#ibcon#about to read 4, iclass 18, count 0 2006.258.00:48:37.63#ibcon#read 4, iclass 18, count 0 2006.258.00:48:37.63#ibcon#about to read 5, iclass 18, count 0 2006.258.00:48:37.63#ibcon#read 5, iclass 18, count 0 2006.258.00:48:37.63#ibcon#about to read 6, iclass 18, count 0 2006.258.00:48:37.63#ibcon#read 6, iclass 18, count 0 2006.258.00:48:37.63#ibcon#end of sib2, iclass 18, count 0 2006.258.00:48:37.63#ibcon#*after write, iclass 18, count 0 2006.258.00:48:37.63#ibcon#*before return 0, iclass 18, count 0 2006.258.00:48:37.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:48:37.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:48:37.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:48:37.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:48:37.63$vck44/va=8,4 2006.258.00:48:37.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.00:48:37.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.00:48:37.63#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:37.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:48:37.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:48:37.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:48:37.69#ibcon#enter wrdev, iclass 20, count 2 2006.258.00:48:37.69#ibcon#first serial, iclass 20, count 2 2006.258.00:48:37.69#ibcon#enter sib2, iclass 20, count 2 2006.258.00:48:37.69#ibcon#flushed, iclass 20, count 2 2006.258.00:48:37.69#ibcon#about to write, iclass 20, count 2 2006.258.00:48:37.69#ibcon#wrote, iclass 20, count 2 2006.258.00:48:37.69#ibcon#about to read 3, iclass 20, count 2 2006.258.00:48:37.71#ibcon#read 3, iclass 20, count 2 2006.258.00:48:37.71#ibcon#about to read 4, iclass 20, count 2 2006.258.00:48:37.71#ibcon#read 4, iclass 20, count 2 2006.258.00:48:37.71#ibcon#about to read 5, iclass 20, count 2 2006.258.00:48:37.71#ibcon#read 5, iclass 20, count 2 2006.258.00:48:37.71#ibcon#about to read 6, iclass 20, count 2 2006.258.00:48:37.71#ibcon#read 6, iclass 20, count 2 2006.258.00:48:37.71#ibcon#end of sib2, iclass 20, count 2 2006.258.00:48:37.71#ibcon#*mode == 0, iclass 20, count 2 2006.258.00:48:37.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.00:48:37.71#ibcon#[25=AT08-04\r\n] 2006.258.00:48:37.71#ibcon#*before write, iclass 20, count 2 2006.258.00:48:37.71#ibcon#enter sib2, iclass 20, count 2 2006.258.00:48:37.71#ibcon#flushed, iclass 20, count 2 2006.258.00:48:37.71#ibcon#about to write, iclass 20, count 2 2006.258.00:48:37.71#ibcon#wrote, iclass 20, count 2 2006.258.00:48:37.71#ibcon#about to read 3, iclass 20, count 2 2006.258.00:48:37.74#ibcon#read 3, iclass 20, count 2 2006.258.00:48:37.74#ibcon#about to read 4, iclass 20, count 2 2006.258.00:48:37.74#ibcon#read 4, iclass 20, count 2 2006.258.00:48:37.74#ibcon#about to read 5, iclass 20, count 2 2006.258.00:48:37.74#ibcon#read 5, iclass 20, count 2 2006.258.00:48:37.74#ibcon#about to read 6, iclass 20, count 2 2006.258.00:48:37.74#ibcon#read 6, iclass 20, count 2 2006.258.00:48:37.74#ibcon#end of sib2, iclass 20, count 2 2006.258.00:48:37.74#ibcon#*after write, iclass 20, count 2 2006.258.00:48:37.74#ibcon#*before return 0, iclass 20, count 2 2006.258.00:48:37.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:48:37.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.00:48:37.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.00:48:37.74#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:37.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:48:37.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:48:37.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:48:37.86#ibcon#enter wrdev, iclass 20, count 0 2006.258.00:48:37.86#ibcon#first serial, iclass 20, count 0 2006.258.00:48:37.86#ibcon#enter sib2, iclass 20, count 0 2006.258.00:48:37.86#ibcon#flushed, iclass 20, count 0 2006.258.00:48:37.86#ibcon#about to write, iclass 20, count 0 2006.258.00:48:37.86#ibcon#wrote, iclass 20, count 0 2006.258.00:48:37.86#ibcon#about to read 3, iclass 20, count 0 2006.258.00:48:37.88#ibcon#read 3, iclass 20, count 0 2006.258.00:48:37.88#ibcon#about to read 4, iclass 20, count 0 2006.258.00:48:37.88#ibcon#read 4, iclass 20, count 0 2006.258.00:48:37.88#ibcon#about to read 5, iclass 20, count 0 2006.258.00:48:37.88#ibcon#read 5, iclass 20, count 0 2006.258.00:48:37.88#ibcon#about to read 6, iclass 20, count 0 2006.258.00:48:37.88#ibcon#read 6, iclass 20, count 0 2006.258.00:48:37.88#ibcon#end of sib2, iclass 20, count 0 2006.258.00:48:37.88#ibcon#*mode == 0, iclass 20, count 0 2006.258.00:48:37.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.00:48:37.88#ibcon#[25=USB\r\n] 2006.258.00:48:37.88#ibcon#*before write, iclass 20, count 0 2006.258.00:48:37.88#ibcon#enter sib2, iclass 20, count 0 2006.258.00:48:37.88#ibcon#flushed, iclass 20, count 0 2006.258.00:48:37.88#ibcon#about to write, iclass 20, count 0 2006.258.00:48:37.88#ibcon#wrote, iclass 20, count 0 2006.258.00:48:37.88#ibcon#about to read 3, iclass 20, count 0 2006.258.00:48:37.91#ibcon#read 3, iclass 20, count 0 2006.258.00:48:37.91#ibcon#about to read 4, iclass 20, count 0 2006.258.00:48:37.91#ibcon#read 4, iclass 20, count 0 2006.258.00:48:37.91#ibcon#about to read 5, iclass 20, count 0 2006.258.00:48:37.91#ibcon#read 5, iclass 20, count 0 2006.258.00:48:37.91#ibcon#about to read 6, iclass 20, count 0 2006.258.00:48:37.91#ibcon#read 6, iclass 20, count 0 2006.258.00:48:37.91#ibcon#end of sib2, iclass 20, count 0 2006.258.00:48:37.91#ibcon#*after write, iclass 20, count 0 2006.258.00:48:37.91#ibcon#*before return 0, iclass 20, count 0 2006.258.00:48:37.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:48:37.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.00:48:37.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.00:48:37.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.00:48:37.91$vck44/vblo=1,629.99 2006.258.00:48:37.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.00:48:37.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.00:48:37.91#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:37.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:37.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:37.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:37.91#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:48:37.91#ibcon#first serial, iclass 22, count 0 2006.258.00:48:37.91#ibcon#enter sib2, iclass 22, count 0 2006.258.00:48:37.91#ibcon#flushed, iclass 22, count 0 2006.258.00:48:37.91#ibcon#about to write, iclass 22, count 0 2006.258.00:48:37.91#ibcon#wrote, iclass 22, count 0 2006.258.00:48:37.91#ibcon#about to read 3, iclass 22, count 0 2006.258.00:48:37.93#ibcon#read 3, iclass 22, count 0 2006.258.00:48:37.93#ibcon#about to read 4, iclass 22, count 0 2006.258.00:48:37.93#ibcon#read 4, iclass 22, count 0 2006.258.00:48:37.93#ibcon#about to read 5, iclass 22, count 0 2006.258.00:48:37.93#ibcon#read 5, iclass 22, count 0 2006.258.00:48:37.93#ibcon#about to read 6, iclass 22, count 0 2006.258.00:48:37.93#ibcon#read 6, iclass 22, count 0 2006.258.00:48:37.93#ibcon#end of sib2, iclass 22, count 0 2006.258.00:48:37.93#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:48:37.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:48:37.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:48:37.93#ibcon#*before write, iclass 22, count 0 2006.258.00:48:37.93#ibcon#enter sib2, iclass 22, count 0 2006.258.00:48:37.93#ibcon#flushed, iclass 22, count 0 2006.258.00:48:37.93#ibcon#about to write, iclass 22, count 0 2006.258.00:48:37.93#ibcon#wrote, iclass 22, count 0 2006.258.00:48:37.93#ibcon#about to read 3, iclass 22, count 0 2006.258.00:48:37.97#ibcon#read 3, iclass 22, count 0 2006.258.00:48:37.97#ibcon#about to read 4, iclass 22, count 0 2006.258.00:48:37.97#ibcon#read 4, iclass 22, count 0 2006.258.00:48:37.97#ibcon#about to read 5, iclass 22, count 0 2006.258.00:48:37.97#ibcon#read 5, iclass 22, count 0 2006.258.00:48:37.97#ibcon#about to read 6, iclass 22, count 0 2006.258.00:48:37.97#ibcon#read 6, iclass 22, count 0 2006.258.00:48:37.97#ibcon#end of sib2, iclass 22, count 0 2006.258.00:48:37.97#ibcon#*after write, iclass 22, count 0 2006.258.00:48:37.97#ibcon#*before return 0, iclass 22, count 0 2006.258.00:48:37.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:37.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:37.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:48:37.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:48:37.97$vck44/vb=1,4 2006.258.00:48:37.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.00:48:37.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.00:48:37.97#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:37.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:48:37.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:48:37.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:48:37.97#ibcon#enter wrdev, iclass 24, count 2 2006.258.00:48:37.97#ibcon#first serial, iclass 24, count 2 2006.258.00:48:37.97#ibcon#enter sib2, iclass 24, count 2 2006.258.00:48:37.97#ibcon#flushed, iclass 24, count 2 2006.258.00:48:37.97#ibcon#about to write, iclass 24, count 2 2006.258.00:48:37.97#ibcon#wrote, iclass 24, count 2 2006.258.00:48:37.97#ibcon#about to read 3, iclass 24, count 2 2006.258.00:48:37.99#ibcon#read 3, iclass 24, count 2 2006.258.00:48:37.99#ibcon#about to read 4, iclass 24, count 2 2006.258.00:48:37.99#ibcon#read 4, iclass 24, count 2 2006.258.00:48:37.99#ibcon#about to read 5, iclass 24, count 2 2006.258.00:48:37.99#ibcon#read 5, iclass 24, count 2 2006.258.00:48:37.99#ibcon#about to read 6, iclass 24, count 2 2006.258.00:48:37.99#ibcon#read 6, iclass 24, count 2 2006.258.00:48:37.99#ibcon#end of sib2, iclass 24, count 2 2006.258.00:48:37.99#ibcon#*mode == 0, iclass 24, count 2 2006.258.00:48:37.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.00:48:37.99#ibcon#[27=AT01-04\r\n] 2006.258.00:48:37.99#ibcon#*before write, iclass 24, count 2 2006.258.00:48:37.99#ibcon#enter sib2, iclass 24, count 2 2006.258.00:48:37.99#ibcon#flushed, iclass 24, count 2 2006.258.00:48:37.99#ibcon#about to write, iclass 24, count 2 2006.258.00:48:37.99#ibcon#wrote, iclass 24, count 2 2006.258.00:48:37.99#ibcon#about to read 3, iclass 24, count 2 2006.258.00:48:38.02#ibcon#read 3, iclass 24, count 2 2006.258.00:48:38.02#ibcon#about to read 4, iclass 24, count 2 2006.258.00:48:38.02#ibcon#read 4, iclass 24, count 2 2006.258.00:48:38.02#ibcon#about to read 5, iclass 24, count 2 2006.258.00:48:38.02#ibcon#read 5, iclass 24, count 2 2006.258.00:48:38.02#ibcon#about to read 6, iclass 24, count 2 2006.258.00:48:38.02#ibcon#read 6, iclass 24, count 2 2006.258.00:48:38.02#ibcon#end of sib2, iclass 24, count 2 2006.258.00:48:38.02#ibcon#*after write, iclass 24, count 2 2006.258.00:48:38.02#ibcon#*before return 0, iclass 24, count 2 2006.258.00:48:38.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:48:38.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.00:48:38.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.00:48:38.02#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:38.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:48:38.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:48:38.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:48:38.14#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:48:38.14#ibcon#first serial, iclass 24, count 0 2006.258.00:48:38.14#ibcon#enter sib2, iclass 24, count 0 2006.258.00:48:38.14#ibcon#flushed, iclass 24, count 0 2006.258.00:48:38.14#ibcon#about to write, iclass 24, count 0 2006.258.00:48:38.14#ibcon#wrote, iclass 24, count 0 2006.258.00:48:38.14#ibcon#about to read 3, iclass 24, count 0 2006.258.00:48:38.16#ibcon#read 3, iclass 24, count 0 2006.258.00:48:38.16#ibcon#about to read 4, iclass 24, count 0 2006.258.00:48:38.16#ibcon#read 4, iclass 24, count 0 2006.258.00:48:38.16#ibcon#about to read 5, iclass 24, count 0 2006.258.00:48:38.16#ibcon#read 5, iclass 24, count 0 2006.258.00:48:38.16#ibcon#about to read 6, iclass 24, count 0 2006.258.00:48:38.16#ibcon#read 6, iclass 24, count 0 2006.258.00:48:38.16#ibcon#end of sib2, iclass 24, count 0 2006.258.00:48:38.16#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:48:38.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:48:38.16#ibcon#[27=USB\r\n] 2006.258.00:48:38.16#ibcon#*before write, iclass 24, count 0 2006.258.00:48:38.16#ibcon#enter sib2, iclass 24, count 0 2006.258.00:48:38.16#ibcon#flushed, iclass 24, count 0 2006.258.00:48:38.16#ibcon#about to write, iclass 24, count 0 2006.258.00:48:38.16#ibcon#wrote, iclass 24, count 0 2006.258.00:48:38.16#ibcon#about to read 3, iclass 24, count 0 2006.258.00:48:38.19#ibcon#read 3, iclass 24, count 0 2006.258.00:48:38.19#ibcon#about to read 4, iclass 24, count 0 2006.258.00:48:38.19#ibcon#read 4, iclass 24, count 0 2006.258.00:48:38.19#ibcon#about to read 5, iclass 24, count 0 2006.258.00:48:38.19#ibcon#read 5, iclass 24, count 0 2006.258.00:48:38.19#ibcon#about to read 6, iclass 24, count 0 2006.258.00:48:38.19#ibcon#read 6, iclass 24, count 0 2006.258.00:48:38.19#ibcon#end of sib2, iclass 24, count 0 2006.258.00:48:38.19#ibcon#*after write, iclass 24, count 0 2006.258.00:48:38.19#ibcon#*before return 0, iclass 24, count 0 2006.258.00:48:38.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:48:38.19#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.00:48:38.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:48:38.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:48:38.19$vck44/vblo=2,634.99 2006.258.00:48:38.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.00:48:38.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.00:48:38.19#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:38.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:38.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:38.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:38.19#ibcon#enter wrdev, iclass 26, count 0 2006.258.00:48:38.19#ibcon#first serial, iclass 26, count 0 2006.258.00:48:38.19#ibcon#enter sib2, iclass 26, count 0 2006.258.00:48:38.19#ibcon#flushed, iclass 26, count 0 2006.258.00:48:38.19#ibcon#about to write, iclass 26, count 0 2006.258.00:48:38.19#ibcon#wrote, iclass 26, count 0 2006.258.00:48:38.19#ibcon#about to read 3, iclass 26, count 0 2006.258.00:48:38.21#ibcon#read 3, iclass 26, count 0 2006.258.00:48:38.21#ibcon#about to read 4, iclass 26, count 0 2006.258.00:48:38.21#ibcon#read 4, iclass 26, count 0 2006.258.00:48:38.21#ibcon#about to read 5, iclass 26, count 0 2006.258.00:48:38.21#ibcon#read 5, iclass 26, count 0 2006.258.00:48:38.21#ibcon#about to read 6, iclass 26, count 0 2006.258.00:48:38.21#ibcon#read 6, iclass 26, count 0 2006.258.00:48:38.21#ibcon#end of sib2, iclass 26, count 0 2006.258.00:48:38.21#ibcon#*mode == 0, iclass 26, count 0 2006.258.00:48:38.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.00:48:38.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:48:38.21#ibcon#*before write, iclass 26, count 0 2006.258.00:48:38.21#ibcon#enter sib2, iclass 26, count 0 2006.258.00:48:38.21#ibcon#flushed, iclass 26, count 0 2006.258.00:48:38.21#ibcon#about to write, iclass 26, count 0 2006.258.00:48:38.21#ibcon#wrote, iclass 26, count 0 2006.258.00:48:38.21#ibcon#about to read 3, iclass 26, count 0 2006.258.00:48:38.25#ibcon#read 3, iclass 26, count 0 2006.258.00:48:38.25#ibcon#about to read 4, iclass 26, count 0 2006.258.00:48:38.25#ibcon#read 4, iclass 26, count 0 2006.258.00:48:38.25#ibcon#about to read 5, iclass 26, count 0 2006.258.00:48:38.25#ibcon#read 5, iclass 26, count 0 2006.258.00:48:38.25#ibcon#about to read 6, iclass 26, count 0 2006.258.00:48:38.25#ibcon#read 6, iclass 26, count 0 2006.258.00:48:38.25#ibcon#end of sib2, iclass 26, count 0 2006.258.00:48:38.25#ibcon#*after write, iclass 26, count 0 2006.258.00:48:38.25#ibcon#*before return 0, iclass 26, count 0 2006.258.00:48:38.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:38.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.00:48:38.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.00:48:38.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.00:48:38.25$vck44/vb=2,5 2006.258.00:48:38.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.00:48:38.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.00:48:38.25#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:38.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:38.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:38.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:38.31#ibcon#enter wrdev, iclass 28, count 2 2006.258.00:48:38.31#ibcon#first serial, iclass 28, count 2 2006.258.00:48:38.31#ibcon#enter sib2, iclass 28, count 2 2006.258.00:48:38.31#ibcon#flushed, iclass 28, count 2 2006.258.00:48:38.31#ibcon#about to write, iclass 28, count 2 2006.258.00:48:38.31#ibcon#wrote, iclass 28, count 2 2006.258.00:48:38.31#ibcon#about to read 3, iclass 28, count 2 2006.258.00:48:38.33#ibcon#read 3, iclass 28, count 2 2006.258.00:48:38.33#ibcon#about to read 4, iclass 28, count 2 2006.258.00:48:38.33#ibcon#read 4, iclass 28, count 2 2006.258.00:48:38.33#ibcon#about to read 5, iclass 28, count 2 2006.258.00:48:38.33#ibcon#read 5, iclass 28, count 2 2006.258.00:48:38.33#ibcon#about to read 6, iclass 28, count 2 2006.258.00:48:38.33#ibcon#read 6, iclass 28, count 2 2006.258.00:48:38.33#ibcon#end of sib2, iclass 28, count 2 2006.258.00:48:38.33#ibcon#*mode == 0, iclass 28, count 2 2006.258.00:48:38.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.00:48:38.33#ibcon#[27=AT02-05\r\n] 2006.258.00:48:38.33#ibcon#*before write, iclass 28, count 2 2006.258.00:48:38.33#ibcon#enter sib2, iclass 28, count 2 2006.258.00:48:38.33#ibcon#flushed, iclass 28, count 2 2006.258.00:48:38.33#ibcon#about to write, iclass 28, count 2 2006.258.00:48:38.33#ibcon#wrote, iclass 28, count 2 2006.258.00:48:38.33#ibcon#about to read 3, iclass 28, count 2 2006.258.00:48:38.36#ibcon#read 3, iclass 28, count 2 2006.258.00:48:38.36#ibcon#about to read 4, iclass 28, count 2 2006.258.00:48:38.36#ibcon#read 4, iclass 28, count 2 2006.258.00:48:38.36#ibcon#about to read 5, iclass 28, count 2 2006.258.00:48:38.36#ibcon#read 5, iclass 28, count 2 2006.258.00:48:38.36#ibcon#about to read 6, iclass 28, count 2 2006.258.00:48:38.36#ibcon#read 6, iclass 28, count 2 2006.258.00:48:38.36#ibcon#end of sib2, iclass 28, count 2 2006.258.00:48:38.36#ibcon#*after write, iclass 28, count 2 2006.258.00:48:38.36#ibcon#*before return 0, iclass 28, count 2 2006.258.00:48:38.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:38.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.00:48:38.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.00:48:38.36#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:38.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:38.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:38.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:38.48#ibcon#enter wrdev, iclass 28, count 0 2006.258.00:48:38.48#ibcon#first serial, iclass 28, count 0 2006.258.00:48:38.48#ibcon#enter sib2, iclass 28, count 0 2006.258.00:48:38.48#ibcon#flushed, iclass 28, count 0 2006.258.00:48:38.48#ibcon#about to write, iclass 28, count 0 2006.258.00:48:38.48#ibcon#wrote, iclass 28, count 0 2006.258.00:48:38.48#ibcon#about to read 3, iclass 28, count 0 2006.258.00:48:38.50#ibcon#read 3, iclass 28, count 0 2006.258.00:48:38.50#ibcon#about to read 4, iclass 28, count 0 2006.258.00:48:38.50#ibcon#read 4, iclass 28, count 0 2006.258.00:48:38.50#ibcon#about to read 5, iclass 28, count 0 2006.258.00:48:38.50#ibcon#read 5, iclass 28, count 0 2006.258.00:48:38.50#ibcon#about to read 6, iclass 28, count 0 2006.258.00:48:38.50#ibcon#read 6, iclass 28, count 0 2006.258.00:48:38.50#ibcon#end of sib2, iclass 28, count 0 2006.258.00:48:38.50#ibcon#*mode == 0, iclass 28, count 0 2006.258.00:48:38.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.00:48:38.50#ibcon#[27=USB\r\n] 2006.258.00:48:38.50#ibcon#*before write, iclass 28, count 0 2006.258.00:48:38.50#ibcon#enter sib2, iclass 28, count 0 2006.258.00:48:38.50#ibcon#flushed, iclass 28, count 0 2006.258.00:48:38.50#ibcon#about to write, iclass 28, count 0 2006.258.00:48:38.50#ibcon#wrote, iclass 28, count 0 2006.258.00:48:38.50#ibcon#about to read 3, iclass 28, count 0 2006.258.00:48:38.53#ibcon#read 3, iclass 28, count 0 2006.258.00:48:38.53#ibcon#about to read 4, iclass 28, count 0 2006.258.00:48:38.53#ibcon#read 4, iclass 28, count 0 2006.258.00:48:38.53#ibcon#about to read 5, iclass 28, count 0 2006.258.00:48:38.53#ibcon#read 5, iclass 28, count 0 2006.258.00:48:38.53#ibcon#about to read 6, iclass 28, count 0 2006.258.00:48:38.53#ibcon#read 6, iclass 28, count 0 2006.258.00:48:38.53#ibcon#end of sib2, iclass 28, count 0 2006.258.00:48:38.53#ibcon#*after write, iclass 28, count 0 2006.258.00:48:38.53#ibcon#*before return 0, iclass 28, count 0 2006.258.00:48:38.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:38.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.00:48:38.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.00:48:38.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.00:48:38.53$vck44/vblo=3,649.99 2006.258.00:48:38.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.00:48:38.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.00:48:38.53#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:38.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:38.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:38.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:38.53#ibcon#enter wrdev, iclass 30, count 0 2006.258.00:48:38.53#ibcon#first serial, iclass 30, count 0 2006.258.00:48:38.53#ibcon#enter sib2, iclass 30, count 0 2006.258.00:48:38.53#ibcon#flushed, iclass 30, count 0 2006.258.00:48:38.53#ibcon#about to write, iclass 30, count 0 2006.258.00:48:38.53#ibcon#wrote, iclass 30, count 0 2006.258.00:48:38.53#ibcon#about to read 3, iclass 30, count 0 2006.258.00:48:38.55#ibcon#read 3, iclass 30, count 0 2006.258.00:48:38.55#ibcon#about to read 4, iclass 30, count 0 2006.258.00:48:38.55#ibcon#read 4, iclass 30, count 0 2006.258.00:48:38.55#ibcon#about to read 5, iclass 30, count 0 2006.258.00:48:38.55#ibcon#read 5, iclass 30, count 0 2006.258.00:48:38.55#ibcon#about to read 6, iclass 30, count 0 2006.258.00:48:38.55#ibcon#read 6, iclass 30, count 0 2006.258.00:48:38.55#ibcon#end of sib2, iclass 30, count 0 2006.258.00:48:38.55#ibcon#*mode == 0, iclass 30, count 0 2006.258.00:48:38.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.00:48:38.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:48:38.55#ibcon#*before write, iclass 30, count 0 2006.258.00:48:38.55#ibcon#enter sib2, iclass 30, count 0 2006.258.00:48:38.55#ibcon#flushed, iclass 30, count 0 2006.258.00:48:38.55#ibcon#about to write, iclass 30, count 0 2006.258.00:48:38.55#ibcon#wrote, iclass 30, count 0 2006.258.00:48:38.55#ibcon#about to read 3, iclass 30, count 0 2006.258.00:48:38.59#ibcon#read 3, iclass 30, count 0 2006.258.00:48:38.59#ibcon#about to read 4, iclass 30, count 0 2006.258.00:48:38.59#ibcon#read 4, iclass 30, count 0 2006.258.00:48:38.59#ibcon#about to read 5, iclass 30, count 0 2006.258.00:48:38.59#ibcon#read 5, iclass 30, count 0 2006.258.00:48:38.59#ibcon#about to read 6, iclass 30, count 0 2006.258.00:48:38.59#ibcon#read 6, iclass 30, count 0 2006.258.00:48:38.59#ibcon#end of sib2, iclass 30, count 0 2006.258.00:48:38.59#ibcon#*after write, iclass 30, count 0 2006.258.00:48:38.59#ibcon#*before return 0, iclass 30, count 0 2006.258.00:48:38.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:38.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.00:48:38.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.00:48:38.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.00:48:38.59$vck44/vb=3,4 2006.258.00:48:38.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.258.00:48:38.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.258.00:48:38.59#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:38.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:38.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:38.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:38.65#ibcon#enter wrdev, iclass 32, count 2 2006.258.00:48:38.65#ibcon#first serial, iclass 32, count 2 2006.258.00:48:38.65#ibcon#enter sib2, iclass 32, count 2 2006.258.00:48:38.65#ibcon#flushed, iclass 32, count 2 2006.258.00:48:38.65#ibcon#about to write, iclass 32, count 2 2006.258.00:48:38.65#ibcon#wrote, iclass 32, count 2 2006.258.00:48:38.65#ibcon#about to read 3, iclass 32, count 2 2006.258.00:48:38.67#ibcon#read 3, iclass 32, count 2 2006.258.00:48:38.67#ibcon#about to read 4, iclass 32, count 2 2006.258.00:48:38.67#ibcon#read 4, iclass 32, count 2 2006.258.00:48:38.67#ibcon#about to read 5, iclass 32, count 2 2006.258.00:48:38.67#ibcon#read 5, iclass 32, count 2 2006.258.00:48:38.67#ibcon#about to read 6, iclass 32, count 2 2006.258.00:48:38.67#ibcon#read 6, iclass 32, count 2 2006.258.00:48:38.67#ibcon#end of sib2, iclass 32, count 2 2006.258.00:48:38.67#ibcon#*mode == 0, iclass 32, count 2 2006.258.00:48:38.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.258.00:48:38.67#ibcon#[27=AT03-04\r\n] 2006.258.00:48:38.67#ibcon#*before write, iclass 32, count 2 2006.258.00:48:38.67#ibcon#enter sib2, iclass 32, count 2 2006.258.00:48:38.67#ibcon#flushed, iclass 32, count 2 2006.258.00:48:38.67#ibcon#about to write, iclass 32, count 2 2006.258.00:48:38.67#ibcon#wrote, iclass 32, count 2 2006.258.00:48:38.67#ibcon#about to read 3, iclass 32, count 2 2006.258.00:48:38.70#ibcon#read 3, iclass 32, count 2 2006.258.00:48:38.70#ibcon#about to read 4, iclass 32, count 2 2006.258.00:48:38.70#ibcon#read 4, iclass 32, count 2 2006.258.00:48:38.70#ibcon#about to read 5, iclass 32, count 2 2006.258.00:48:38.70#ibcon#read 5, iclass 32, count 2 2006.258.00:48:38.70#ibcon#about to read 6, iclass 32, count 2 2006.258.00:48:38.70#ibcon#read 6, iclass 32, count 2 2006.258.00:48:38.70#ibcon#end of sib2, iclass 32, count 2 2006.258.00:48:38.70#ibcon#*after write, iclass 32, count 2 2006.258.00:48:38.70#ibcon#*before return 0, iclass 32, count 2 2006.258.00:48:38.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:38.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.258.00:48:38.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.258.00:48:38.70#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:38.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:38.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:38.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:38.82#ibcon#enter wrdev, iclass 32, count 0 2006.258.00:48:38.82#ibcon#first serial, iclass 32, count 0 2006.258.00:48:38.82#ibcon#enter sib2, iclass 32, count 0 2006.258.00:48:38.82#ibcon#flushed, iclass 32, count 0 2006.258.00:48:38.82#ibcon#about to write, iclass 32, count 0 2006.258.00:48:38.82#ibcon#wrote, iclass 32, count 0 2006.258.00:48:38.82#ibcon#about to read 3, iclass 32, count 0 2006.258.00:48:38.84#ibcon#read 3, iclass 32, count 0 2006.258.00:48:38.84#ibcon#about to read 4, iclass 32, count 0 2006.258.00:48:38.84#ibcon#read 4, iclass 32, count 0 2006.258.00:48:38.84#ibcon#about to read 5, iclass 32, count 0 2006.258.00:48:38.84#ibcon#read 5, iclass 32, count 0 2006.258.00:48:38.84#ibcon#about to read 6, iclass 32, count 0 2006.258.00:48:38.84#ibcon#read 6, iclass 32, count 0 2006.258.00:48:38.84#ibcon#end of sib2, iclass 32, count 0 2006.258.00:48:38.84#ibcon#*mode == 0, iclass 32, count 0 2006.258.00:48:38.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.00:48:38.84#ibcon#[27=USB\r\n] 2006.258.00:48:38.84#ibcon#*before write, iclass 32, count 0 2006.258.00:48:38.84#ibcon#enter sib2, iclass 32, count 0 2006.258.00:48:38.84#ibcon#flushed, iclass 32, count 0 2006.258.00:48:38.84#ibcon#about to write, iclass 32, count 0 2006.258.00:48:38.84#ibcon#wrote, iclass 32, count 0 2006.258.00:48:38.84#ibcon#about to read 3, iclass 32, count 0 2006.258.00:48:38.87#ibcon#read 3, iclass 32, count 0 2006.258.00:48:38.87#ibcon#about to read 4, iclass 32, count 0 2006.258.00:48:38.87#ibcon#read 4, iclass 32, count 0 2006.258.00:48:38.87#ibcon#about to read 5, iclass 32, count 0 2006.258.00:48:38.87#ibcon#read 5, iclass 32, count 0 2006.258.00:48:38.87#ibcon#about to read 6, iclass 32, count 0 2006.258.00:48:38.87#ibcon#read 6, iclass 32, count 0 2006.258.00:48:38.87#ibcon#end of sib2, iclass 32, count 0 2006.258.00:48:38.87#ibcon#*after write, iclass 32, count 0 2006.258.00:48:38.87#ibcon#*before return 0, iclass 32, count 0 2006.258.00:48:38.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:38.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.258.00:48:38.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.00:48:38.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.00:48:38.87$vck44/vblo=4,679.99 2006.258.00:48:38.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.00:48:38.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.00:48:38.87#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:38.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:38.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:38.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:38.87#ibcon#enter wrdev, iclass 34, count 0 2006.258.00:48:38.87#ibcon#first serial, iclass 34, count 0 2006.258.00:48:38.87#ibcon#enter sib2, iclass 34, count 0 2006.258.00:48:38.87#ibcon#flushed, iclass 34, count 0 2006.258.00:48:38.87#ibcon#about to write, iclass 34, count 0 2006.258.00:48:38.87#ibcon#wrote, iclass 34, count 0 2006.258.00:48:38.87#ibcon#about to read 3, iclass 34, count 0 2006.258.00:48:38.89#ibcon#read 3, iclass 34, count 0 2006.258.00:48:38.89#ibcon#about to read 4, iclass 34, count 0 2006.258.00:48:38.89#ibcon#read 4, iclass 34, count 0 2006.258.00:48:38.89#ibcon#about to read 5, iclass 34, count 0 2006.258.00:48:38.89#ibcon#read 5, iclass 34, count 0 2006.258.00:48:38.89#ibcon#about to read 6, iclass 34, count 0 2006.258.00:48:38.89#ibcon#read 6, iclass 34, count 0 2006.258.00:48:38.89#ibcon#end of sib2, iclass 34, count 0 2006.258.00:48:38.89#ibcon#*mode == 0, iclass 34, count 0 2006.258.00:48:38.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.00:48:38.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:48:38.89#ibcon#*before write, iclass 34, count 0 2006.258.00:48:38.89#ibcon#enter sib2, iclass 34, count 0 2006.258.00:48:38.89#ibcon#flushed, iclass 34, count 0 2006.258.00:48:38.89#ibcon#about to write, iclass 34, count 0 2006.258.00:48:38.89#ibcon#wrote, iclass 34, count 0 2006.258.00:48:38.89#ibcon#about to read 3, iclass 34, count 0 2006.258.00:48:38.93#ibcon#read 3, iclass 34, count 0 2006.258.00:48:38.93#ibcon#about to read 4, iclass 34, count 0 2006.258.00:48:38.93#ibcon#read 4, iclass 34, count 0 2006.258.00:48:38.93#ibcon#about to read 5, iclass 34, count 0 2006.258.00:48:38.93#ibcon#read 5, iclass 34, count 0 2006.258.00:48:38.93#ibcon#about to read 6, iclass 34, count 0 2006.258.00:48:38.93#ibcon#read 6, iclass 34, count 0 2006.258.00:48:38.93#ibcon#end of sib2, iclass 34, count 0 2006.258.00:48:38.93#ibcon#*after write, iclass 34, count 0 2006.258.00:48:38.93#ibcon#*before return 0, iclass 34, count 0 2006.258.00:48:38.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:38.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.00:48:38.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.00:48:38.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.00:48:38.93$vck44/vb=4,5 2006.258.00:48:38.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.258.00:48:38.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.258.00:48:38.93#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:38.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:38.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:38.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:38.99#ibcon#enter wrdev, iclass 36, count 2 2006.258.00:48:38.99#ibcon#first serial, iclass 36, count 2 2006.258.00:48:38.99#ibcon#enter sib2, iclass 36, count 2 2006.258.00:48:38.99#ibcon#flushed, iclass 36, count 2 2006.258.00:48:38.99#ibcon#about to write, iclass 36, count 2 2006.258.00:48:38.99#ibcon#wrote, iclass 36, count 2 2006.258.00:48:38.99#ibcon#about to read 3, iclass 36, count 2 2006.258.00:48:39.01#ibcon#read 3, iclass 36, count 2 2006.258.00:48:39.01#ibcon#about to read 4, iclass 36, count 2 2006.258.00:48:39.01#ibcon#read 4, iclass 36, count 2 2006.258.00:48:39.01#ibcon#about to read 5, iclass 36, count 2 2006.258.00:48:39.01#ibcon#read 5, iclass 36, count 2 2006.258.00:48:39.01#ibcon#about to read 6, iclass 36, count 2 2006.258.00:48:39.01#ibcon#read 6, iclass 36, count 2 2006.258.00:48:39.01#ibcon#end of sib2, iclass 36, count 2 2006.258.00:48:39.01#ibcon#*mode == 0, iclass 36, count 2 2006.258.00:48:39.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.258.00:48:39.01#ibcon#[27=AT04-05\r\n] 2006.258.00:48:39.01#ibcon#*before write, iclass 36, count 2 2006.258.00:48:39.01#ibcon#enter sib2, iclass 36, count 2 2006.258.00:48:39.01#ibcon#flushed, iclass 36, count 2 2006.258.00:48:39.01#ibcon#about to write, iclass 36, count 2 2006.258.00:48:39.01#ibcon#wrote, iclass 36, count 2 2006.258.00:48:39.01#ibcon#about to read 3, iclass 36, count 2 2006.258.00:48:39.04#ibcon#read 3, iclass 36, count 2 2006.258.00:48:39.04#ibcon#about to read 4, iclass 36, count 2 2006.258.00:48:39.04#ibcon#read 4, iclass 36, count 2 2006.258.00:48:39.04#ibcon#about to read 5, iclass 36, count 2 2006.258.00:48:39.04#ibcon#read 5, iclass 36, count 2 2006.258.00:48:39.04#ibcon#about to read 6, iclass 36, count 2 2006.258.00:48:39.04#ibcon#read 6, iclass 36, count 2 2006.258.00:48:39.04#ibcon#end of sib2, iclass 36, count 2 2006.258.00:48:39.04#ibcon#*after write, iclass 36, count 2 2006.258.00:48:39.04#ibcon#*before return 0, iclass 36, count 2 2006.258.00:48:39.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:39.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.258.00:48:39.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.258.00:48:39.04#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:39.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:39.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:39.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:39.16#ibcon#enter wrdev, iclass 36, count 0 2006.258.00:48:39.16#ibcon#first serial, iclass 36, count 0 2006.258.00:48:39.16#ibcon#enter sib2, iclass 36, count 0 2006.258.00:48:39.16#ibcon#flushed, iclass 36, count 0 2006.258.00:48:39.16#ibcon#about to write, iclass 36, count 0 2006.258.00:48:39.16#ibcon#wrote, iclass 36, count 0 2006.258.00:48:39.16#ibcon#about to read 3, iclass 36, count 0 2006.258.00:48:39.18#ibcon#read 3, iclass 36, count 0 2006.258.00:48:39.18#ibcon#about to read 4, iclass 36, count 0 2006.258.00:48:39.18#ibcon#read 4, iclass 36, count 0 2006.258.00:48:39.18#ibcon#about to read 5, iclass 36, count 0 2006.258.00:48:39.18#ibcon#read 5, iclass 36, count 0 2006.258.00:48:39.18#ibcon#about to read 6, iclass 36, count 0 2006.258.00:48:39.18#ibcon#read 6, iclass 36, count 0 2006.258.00:48:39.18#ibcon#end of sib2, iclass 36, count 0 2006.258.00:48:39.18#ibcon#*mode == 0, iclass 36, count 0 2006.258.00:48:39.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.00:48:39.18#ibcon#[27=USB\r\n] 2006.258.00:48:39.18#ibcon#*before write, iclass 36, count 0 2006.258.00:48:39.18#ibcon#enter sib2, iclass 36, count 0 2006.258.00:48:39.18#ibcon#flushed, iclass 36, count 0 2006.258.00:48:39.18#ibcon#about to write, iclass 36, count 0 2006.258.00:48:39.18#ibcon#wrote, iclass 36, count 0 2006.258.00:48:39.18#ibcon#about to read 3, iclass 36, count 0 2006.258.00:48:39.21#ibcon#read 3, iclass 36, count 0 2006.258.00:48:39.21#ibcon#about to read 4, iclass 36, count 0 2006.258.00:48:39.21#ibcon#read 4, iclass 36, count 0 2006.258.00:48:39.21#ibcon#about to read 5, iclass 36, count 0 2006.258.00:48:39.21#ibcon#read 5, iclass 36, count 0 2006.258.00:48:39.21#ibcon#about to read 6, iclass 36, count 0 2006.258.00:48:39.21#ibcon#read 6, iclass 36, count 0 2006.258.00:48:39.21#ibcon#end of sib2, iclass 36, count 0 2006.258.00:48:39.21#ibcon#*after write, iclass 36, count 0 2006.258.00:48:39.21#ibcon#*before return 0, iclass 36, count 0 2006.258.00:48:39.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:39.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.258.00:48:39.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.00:48:39.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.00:48:39.21$vck44/vblo=5,709.99 2006.258.00:48:39.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.00:48:39.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.00:48:39.21#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:39.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:39.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:39.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:39.21#ibcon#enter wrdev, iclass 38, count 0 2006.258.00:48:39.21#ibcon#first serial, iclass 38, count 0 2006.258.00:48:39.21#ibcon#enter sib2, iclass 38, count 0 2006.258.00:48:39.21#ibcon#flushed, iclass 38, count 0 2006.258.00:48:39.21#ibcon#about to write, iclass 38, count 0 2006.258.00:48:39.21#ibcon#wrote, iclass 38, count 0 2006.258.00:48:39.21#ibcon#about to read 3, iclass 38, count 0 2006.258.00:48:39.23#ibcon#read 3, iclass 38, count 0 2006.258.00:48:39.23#ibcon#about to read 4, iclass 38, count 0 2006.258.00:48:39.23#ibcon#read 4, iclass 38, count 0 2006.258.00:48:39.23#ibcon#about to read 5, iclass 38, count 0 2006.258.00:48:39.23#ibcon#read 5, iclass 38, count 0 2006.258.00:48:39.23#ibcon#about to read 6, iclass 38, count 0 2006.258.00:48:39.23#ibcon#read 6, iclass 38, count 0 2006.258.00:48:39.23#ibcon#end of sib2, iclass 38, count 0 2006.258.00:48:39.23#ibcon#*mode == 0, iclass 38, count 0 2006.258.00:48:39.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.00:48:39.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:48:39.23#ibcon#*before write, iclass 38, count 0 2006.258.00:48:39.23#ibcon#enter sib2, iclass 38, count 0 2006.258.00:48:39.23#ibcon#flushed, iclass 38, count 0 2006.258.00:48:39.23#ibcon#about to write, iclass 38, count 0 2006.258.00:48:39.23#ibcon#wrote, iclass 38, count 0 2006.258.00:48:39.23#ibcon#about to read 3, iclass 38, count 0 2006.258.00:48:39.27#ibcon#read 3, iclass 38, count 0 2006.258.00:48:39.27#ibcon#about to read 4, iclass 38, count 0 2006.258.00:48:39.27#ibcon#read 4, iclass 38, count 0 2006.258.00:48:39.27#ibcon#about to read 5, iclass 38, count 0 2006.258.00:48:39.27#ibcon#read 5, iclass 38, count 0 2006.258.00:48:39.27#ibcon#about to read 6, iclass 38, count 0 2006.258.00:48:39.27#ibcon#read 6, iclass 38, count 0 2006.258.00:48:39.27#ibcon#end of sib2, iclass 38, count 0 2006.258.00:48:39.27#ibcon#*after write, iclass 38, count 0 2006.258.00:48:39.27#ibcon#*before return 0, iclass 38, count 0 2006.258.00:48:39.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:39.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.00:48:39.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.00:48:39.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.00:48:39.27$vck44/vb=5,4 2006.258.00:48:39.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.258.00:48:39.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.258.00:48:39.27#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:39.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:39.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:39.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:39.33#ibcon#enter wrdev, iclass 40, count 2 2006.258.00:48:39.33#ibcon#first serial, iclass 40, count 2 2006.258.00:48:39.33#ibcon#enter sib2, iclass 40, count 2 2006.258.00:48:39.33#ibcon#flushed, iclass 40, count 2 2006.258.00:48:39.33#ibcon#about to write, iclass 40, count 2 2006.258.00:48:39.33#ibcon#wrote, iclass 40, count 2 2006.258.00:48:39.33#ibcon#about to read 3, iclass 40, count 2 2006.258.00:48:39.35#ibcon#read 3, iclass 40, count 2 2006.258.00:48:39.35#ibcon#about to read 4, iclass 40, count 2 2006.258.00:48:39.35#ibcon#read 4, iclass 40, count 2 2006.258.00:48:39.35#ibcon#about to read 5, iclass 40, count 2 2006.258.00:48:39.35#ibcon#read 5, iclass 40, count 2 2006.258.00:48:39.35#ibcon#about to read 6, iclass 40, count 2 2006.258.00:48:39.35#ibcon#read 6, iclass 40, count 2 2006.258.00:48:39.35#ibcon#end of sib2, iclass 40, count 2 2006.258.00:48:39.35#ibcon#*mode == 0, iclass 40, count 2 2006.258.00:48:39.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.258.00:48:39.35#ibcon#[27=AT05-04\r\n] 2006.258.00:48:39.35#ibcon#*before write, iclass 40, count 2 2006.258.00:48:39.35#ibcon#enter sib2, iclass 40, count 2 2006.258.00:48:39.35#ibcon#flushed, iclass 40, count 2 2006.258.00:48:39.35#ibcon#about to write, iclass 40, count 2 2006.258.00:48:39.35#ibcon#wrote, iclass 40, count 2 2006.258.00:48:39.35#ibcon#about to read 3, iclass 40, count 2 2006.258.00:48:39.38#ibcon#read 3, iclass 40, count 2 2006.258.00:48:39.38#ibcon#about to read 4, iclass 40, count 2 2006.258.00:48:39.38#ibcon#read 4, iclass 40, count 2 2006.258.00:48:39.38#ibcon#about to read 5, iclass 40, count 2 2006.258.00:48:39.38#ibcon#read 5, iclass 40, count 2 2006.258.00:48:39.38#ibcon#about to read 6, iclass 40, count 2 2006.258.00:48:39.38#ibcon#read 6, iclass 40, count 2 2006.258.00:48:39.38#ibcon#end of sib2, iclass 40, count 2 2006.258.00:48:39.38#ibcon#*after write, iclass 40, count 2 2006.258.00:48:39.38#ibcon#*before return 0, iclass 40, count 2 2006.258.00:48:39.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:39.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.258.00:48:39.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.258.00:48:39.38#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:39.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:39.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:39.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:39.50#ibcon#enter wrdev, iclass 40, count 0 2006.258.00:48:39.50#ibcon#first serial, iclass 40, count 0 2006.258.00:48:39.50#ibcon#enter sib2, iclass 40, count 0 2006.258.00:48:39.50#ibcon#flushed, iclass 40, count 0 2006.258.00:48:39.50#ibcon#about to write, iclass 40, count 0 2006.258.00:48:39.50#ibcon#wrote, iclass 40, count 0 2006.258.00:48:39.50#ibcon#about to read 3, iclass 40, count 0 2006.258.00:48:39.52#ibcon#read 3, iclass 40, count 0 2006.258.00:48:39.52#ibcon#about to read 4, iclass 40, count 0 2006.258.00:48:39.52#ibcon#read 4, iclass 40, count 0 2006.258.00:48:39.52#ibcon#about to read 5, iclass 40, count 0 2006.258.00:48:39.52#ibcon#read 5, iclass 40, count 0 2006.258.00:48:39.52#ibcon#about to read 6, iclass 40, count 0 2006.258.00:48:39.52#ibcon#read 6, iclass 40, count 0 2006.258.00:48:39.52#ibcon#end of sib2, iclass 40, count 0 2006.258.00:48:39.52#ibcon#*mode == 0, iclass 40, count 0 2006.258.00:48:39.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.00:48:39.52#ibcon#[27=USB\r\n] 2006.258.00:48:39.52#ibcon#*before write, iclass 40, count 0 2006.258.00:48:39.52#ibcon#enter sib2, iclass 40, count 0 2006.258.00:48:39.52#ibcon#flushed, iclass 40, count 0 2006.258.00:48:39.52#ibcon#about to write, iclass 40, count 0 2006.258.00:48:39.52#ibcon#wrote, iclass 40, count 0 2006.258.00:48:39.52#ibcon#about to read 3, iclass 40, count 0 2006.258.00:48:39.55#ibcon#read 3, iclass 40, count 0 2006.258.00:48:39.55#ibcon#about to read 4, iclass 40, count 0 2006.258.00:48:39.55#ibcon#read 4, iclass 40, count 0 2006.258.00:48:39.55#ibcon#about to read 5, iclass 40, count 0 2006.258.00:48:39.55#ibcon#read 5, iclass 40, count 0 2006.258.00:48:39.55#ibcon#about to read 6, iclass 40, count 0 2006.258.00:48:39.55#ibcon#read 6, iclass 40, count 0 2006.258.00:48:39.55#ibcon#end of sib2, iclass 40, count 0 2006.258.00:48:39.55#ibcon#*after write, iclass 40, count 0 2006.258.00:48:39.55#ibcon#*before return 0, iclass 40, count 0 2006.258.00:48:39.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:39.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.258.00:48:39.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.00:48:39.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.00:48:39.55$vck44/vblo=6,719.99 2006.258.00:48:39.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.258.00:48:39.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.258.00:48:39.55#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:39.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:39.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:39.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:39.55#ibcon#enter wrdev, iclass 4, count 0 2006.258.00:48:39.55#ibcon#first serial, iclass 4, count 0 2006.258.00:48:39.55#ibcon#enter sib2, iclass 4, count 0 2006.258.00:48:39.55#ibcon#flushed, iclass 4, count 0 2006.258.00:48:39.55#ibcon#about to write, iclass 4, count 0 2006.258.00:48:39.55#ibcon#wrote, iclass 4, count 0 2006.258.00:48:39.55#ibcon#about to read 3, iclass 4, count 0 2006.258.00:48:39.57#ibcon#read 3, iclass 4, count 0 2006.258.00:48:39.57#ibcon#about to read 4, iclass 4, count 0 2006.258.00:48:39.57#ibcon#read 4, iclass 4, count 0 2006.258.00:48:39.57#ibcon#about to read 5, iclass 4, count 0 2006.258.00:48:39.57#ibcon#read 5, iclass 4, count 0 2006.258.00:48:39.57#ibcon#about to read 6, iclass 4, count 0 2006.258.00:48:39.57#ibcon#read 6, iclass 4, count 0 2006.258.00:48:39.57#ibcon#end of sib2, iclass 4, count 0 2006.258.00:48:39.57#ibcon#*mode == 0, iclass 4, count 0 2006.258.00:48:39.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.00:48:39.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:48:39.57#ibcon#*before write, iclass 4, count 0 2006.258.00:48:39.57#ibcon#enter sib2, iclass 4, count 0 2006.258.00:48:39.57#ibcon#flushed, iclass 4, count 0 2006.258.00:48:39.57#ibcon#about to write, iclass 4, count 0 2006.258.00:48:39.57#ibcon#wrote, iclass 4, count 0 2006.258.00:48:39.57#ibcon#about to read 3, iclass 4, count 0 2006.258.00:48:39.61#ibcon#read 3, iclass 4, count 0 2006.258.00:48:39.61#ibcon#about to read 4, iclass 4, count 0 2006.258.00:48:39.61#ibcon#read 4, iclass 4, count 0 2006.258.00:48:39.61#ibcon#about to read 5, iclass 4, count 0 2006.258.00:48:39.61#ibcon#read 5, iclass 4, count 0 2006.258.00:48:39.61#ibcon#about to read 6, iclass 4, count 0 2006.258.00:48:39.61#ibcon#read 6, iclass 4, count 0 2006.258.00:48:39.61#ibcon#end of sib2, iclass 4, count 0 2006.258.00:48:39.61#ibcon#*after write, iclass 4, count 0 2006.258.00:48:39.61#ibcon#*before return 0, iclass 4, count 0 2006.258.00:48:39.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:39.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.258.00:48:39.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.00:48:39.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.00:48:39.61$vck44/vb=6,4 2006.258.00:48:39.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.258.00:48:39.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.258.00:48:39.61#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:39.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:39.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:39.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:39.67#ibcon#enter wrdev, iclass 6, count 2 2006.258.00:48:39.67#ibcon#first serial, iclass 6, count 2 2006.258.00:48:39.67#ibcon#enter sib2, iclass 6, count 2 2006.258.00:48:39.67#ibcon#flushed, iclass 6, count 2 2006.258.00:48:39.67#ibcon#about to write, iclass 6, count 2 2006.258.00:48:39.67#ibcon#wrote, iclass 6, count 2 2006.258.00:48:39.67#ibcon#about to read 3, iclass 6, count 2 2006.258.00:48:39.69#ibcon#read 3, iclass 6, count 2 2006.258.00:48:39.69#ibcon#about to read 4, iclass 6, count 2 2006.258.00:48:39.69#ibcon#read 4, iclass 6, count 2 2006.258.00:48:39.69#ibcon#about to read 5, iclass 6, count 2 2006.258.00:48:39.69#ibcon#read 5, iclass 6, count 2 2006.258.00:48:39.69#ibcon#about to read 6, iclass 6, count 2 2006.258.00:48:39.69#ibcon#read 6, iclass 6, count 2 2006.258.00:48:39.69#ibcon#end of sib2, iclass 6, count 2 2006.258.00:48:39.69#ibcon#*mode == 0, iclass 6, count 2 2006.258.00:48:39.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.258.00:48:39.69#ibcon#[27=AT06-04\r\n] 2006.258.00:48:39.69#ibcon#*before write, iclass 6, count 2 2006.258.00:48:39.69#ibcon#enter sib2, iclass 6, count 2 2006.258.00:48:39.69#ibcon#flushed, iclass 6, count 2 2006.258.00:48:39.69#ibcon#about to write, iclass 6, count 2 2006.258.00:48:39.69#ibcon#wrote, iclass 6, count 2 2006.258.00:48:39.69#ibcon#about to read 3, iclass 6, count 2 2006.258.00:48:39.72#ibcon#read 3, iclass 6, count 2 2006.258.00:48:39.72#ibcon#about to read 4, iclass 6, count 2 2006.258.00:48:39.72#ibcon#read 4, iclass 6, count 2 2006.258.00:48:39.72#ibcon#about to read 5, iclass 6, count 2 2006.258.00:48:39.72#ibcon#read 5, iclass 6, count 2 2006.258.00:48:39.72#ibcon#about to read 6, iclass 6, count 2 2006.258.00:48:39.72#ibcon#read 6, iclass 6, count 2 2006.258.00:48:39.72#ibcon#end of sib2, iclass 6, count 2 2006.258.00:48:39.72#ibcon#*after write, iclass 6, count 2 2006.258.00:48:39.72#ibcon#*before return 0, iclass 6, count 2 2006.258.00:48:39.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:39.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.258.00:48:39.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.258.00:48:39.72#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:39.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:39.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:39.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:39.84#ibcon#enter wrdev, iclass 6, count 0 2006.258.00:48:39.84#ibcon#first serial, iclass 6, count 0 2006.258.00:48:39.84#ibcon#enter sib2, iclass 6, count 0 2006.258.00:48:39.84#ibcon#flushed, iclass 6, count 0 2006.258.00:48:39.84#ibcon#about to write, iclass 6, count 0 2006.258.00:48:39.84#ibcon#wrote, iclass 6, count 0 2006.258.00:48:39.84#ibcon#about to read 3, iclass 6, count 0 2006.258.00:48:39.86#ibcon#read 3, iclass 6, count 0 2006.258.00:48:39.86#ibcon#about to read 4, iclass 6, count 0 2006.258.00:48:39.86#ibcon#read 4, iclass 6, count 0 2006.258.00:48:39.86#ibcon#about to read 5, iclass 6, count 0 2006.258.00:48:39.86#ibcon#read 5, iclass 6, count 0 2006.258.00:48:39.86#ibcon#about to read 6, iclass 6, count 0 2006.258.00:48:39.86#ibcon#read 6, iclass 6, count 0 2006.258.00:48:39.86#ibcon#end of sib2, iclass 6, count 0 2006.258.00:48:39.86#ibcon#*mode == 0, iclass 6, count 0 2006.258.00:48:39.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.00:48:39.86#ibcon#[27=USB\r\n] 2006.258.00:48:39.86#ibcon#*before write, iclass 6, count 0 2006.258.00:48:39.86#ibcon#enter sib2, iclass 6, count 0 2006.258.00:48:39.86#ibcon#flushed, iclass 6, count 0 2006.258.00:48:39.86#ibcon#about to write, iclass 6, count 0 2006.258.00:48:39.86#ibcon#wrote, iclass 6, count 0 2006.258.00:48:39.86#ibcon#about to read 3, iclass 6, count 0 2006.258.00:48:39.89#ibcon#read 3, iclass 6, count 0 2006.258.00:48:39.89#ibcon#about to read 4, iclass 6, count 0 2006.258.00:48:39.89#ibcon#read 4, iclass 6, count 0 2006.258.00:48:39.89#ibcon#about to read 5, iclass 6, count 0 2006.258.00:48:39.89#ibcon#read 5, iclass 6, count 0 2006.258.00:48:39.89#ibcon#about to read 6, iclass 6, count 0 2006.258.00:48:39.89#ibcon#read 6, iclass 6, count 0 2006.258.00:48:39.89#ibcon#end of sib2, iclass 6, count 0 2006.258.00:48:39.89#ibcon#*after write, iclass 6, count 0 2006.258.00:48:39.89#ibcon#*before return 0, iclass 6, count 0 2006.258.00:48:39.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:39.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.258.00:48:39.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.00:48:39.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.00:48:39.89$vck44/vblo=7,734.99 2006.258.00:48:39.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.258.00:48:39.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.258.00:48:39.89#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:39.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:39.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:39.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:39.89#ibcon#enter wrdev, iclass 10, count 0 2006.258.00:48:39.89#ibcon#first serial, iclass 10, count 0 2006.258.00:48:39.89#ibcon#enter sib2, iclass 10, count 0 2006.258.00:48:39.89#ibcon#flushed, iclass 10, count 0 2006.258.00:48:39.89#ibcon#about to write, iclass 10, count 0 2006.258.00:48:39.89#ibcon#wrote, iclass 10, count 0 2006.258.00:48:39.89#ibcon#about to read 3, iclass 10, count 0 2006.258.00:48:39.91#ibcon#read 3, iclass 10, count 0 2006.258.00:48:39.91#ibcon#about to read 4, iclass 10, count 0 2006.258.00:48:39.91#ibcon#read 4, iclass 10, count 0 2006.258.00:48:39.91#ibcon#about to read 5, iclass 10, count 0 2006.258.00:48:39.91#ibcon#read 5, iclass 10, count 0 2006.258.00:48:39.91#ibcon#about to read 6, iclass 10, count 0 2006.258.00:48:39.91#ibcon#read 6, iclass 10, count 0 2006.258.00:48:39.91#ibcon#end of sib2, iclass 10, count 0 2006.258.00:48:39.91#ibcon#*mode == 0, iclass 10, count 0 2006.258.00:48:39.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.00:48:39.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:48:39.91#ibcon#*before write, iclass 10, count 0 2006.258.00:48:39.91#ibcon#enter sib2, iclass 10, count 0 2006.258.00:48:39.91#ibcon#flushed, iclass 10, count 0 2006.258.00:48:39.91#ibcon#about to write, iclass 10, count 0 2006.258.00:48:39.91#ibcon#wrote, iclass 10, count 0 2006.258.00:48:39.91#ibcon#about to read 3, iclass 10, count 0 2006.258.00:48:39.95#ibcon#read 3, iclass 10, count 0 2006.258.00:48:39.95#ibcon#about to read 4, iclass 10, count 0 2006.258.00:48:39.95#ibcon#read 4, iclass 10, count 0 2006.258.00:48:39.95#ibcon#about to read 5, iclass 10, count 0 2006.258.00:48:39.95#ibcon#read 5, iclass 10, count 0 2006.258.00:48:39.95#ibcon#about to read 6, iclass 10, count 0 2006.258.00:48:39.95#ibcon#read 6, iclass 10, count 0 2006.258.00:48:39.95#ibcon#end of sib2, iclass 10, count 0 2006.258.00:48:39.95#ibcon#*after write, iclass 10, count 0 2006.258.00:48:39.95#ibcon#*before return 0, iclass 10, count 0 2006.258.00:48:39.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:39.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.258.00:48:39.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.00:48:39.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.00:48:39.95$vck44/vb=7,4 2006.258.00:48:39.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.258.00:48:39.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.258.00:48:39.95#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:39.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:40.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:40.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:40.01#ibcon#enter wrdev, iclass 12, count 2 2006.258.00:48:40.01#ibcon#first serial, iclass 12, count 2 2006.258.00:48:40.01#ibcon#enter sib2, iclass 12, count 2 2006.258.00:48:40.01#ibcon#flushed, iclass 12, count 2 2006.258.00:48:40.01#ibcon#about to write, iclass 12, count 2 2006.258.00:48:40.01#ibcon#wrote, iclass 12, count 2 2006.258.00:48:40.01#ibcon#about to read 3, iclass 12, count 2 2006.258.00:48:40.03#ibcon#read 3, iclass 12, count 2 2006.258.00:48:40.03#ibcon#about to read 4, iclass 12, count 2 2006.258.00:48:40.03#ibcon#read 4, iclass 12, count 2 2006.258.00:48:40.03#ibcon#about to read 5, iclass 12, count 2 2006.258.00:48:40.03#ibcon#read 5, iclass 12, count 2 2006.258.00:48:40.03#ibcon#about to read 6, iclass 12, count 2 2006.258.00:48:40.03#ibcon#read 6, iclass 12, count 2 2006.258.00:48:40.03#ibcon#end of sib2, iclass 12, count 2 2006.258.00:48:40.03#ibcon#*mode == 0, iclass 12, count 2 2006.258.00:48:40.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.258.00:48:40.03#ibcon#[27=AT07-04\r\n] 2006.258.00:48:40.03#ibcon#*before write, iclass 12, count 2 2006.258.00:48:40.03#ibcon#enter sib2, iclass 12, count 2 2006.258.00:48:40.03#ibcon#flushed, iclass 12, count 2 2006.258.00:48:40.03#ibcon#about to write, iclass 12, count 2 2006.258.00:48:40.03#ibcon#wrote, iclass 12, count 2 2006.258.00:48:40.03#ibcon#about to read 3, iclass 12, count 2 2006.258.00:48:40.06#ibcon#read 3, iclass 12, count 2 2006.258.00:48:40.06#ibcon#about to read 4, iclass 12, count 2 2006.258.00:48:40.06#ibcon#read 4, iclass 12, count 2 2006.258.00:48:40.06#ibcon#about to read 5, iclass 12, count 2 2006.258.00:48:40.06#ibcon#read 5, iclass 12, count 2 2006.258.00:48:40.06#ibcon#about to read 6, iclass 12, count 2 2006.258.00:48:40.06#ibcon#read 6, iclass 12, count 2 2006.258.00:48:40.06#ibcon#end of sib2, iclass 12, count 2 2006.258.00:48:40.06#ibcon#*after write, iclass 12, count 2 2006.258.00:48:40.06#ibcon#*before return 0, iclass 12, count 2 2006.258.00:48:40.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:40.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.258.00:48:40.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.258.00:48:40.06#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:40.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:40.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:40.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:40.18#ibcon#enter wrdev, iclass 12, count 0 2006.258.00:48:40.18#ibcon#first serial, iclass 12, count 0 2006.258.00:48:40.18#ibcon#enter sib2, iclass 12, count 0 2006.258.00:48:40.18#ibcon#flushed, iclass 12, count 0 2006.258.00:48:40.18#ibcon#about to write, iclass 12, count 0 2006.258.00:48:40.18#ibcon#wrote, iclass 12, count 0 2006.258.00:48:40.18#ibcon#about to read 3, iclass 12, count 0 2006.258.00:48:40.20#ibcon#read 3, iclass 12, count 0 2006.258.00:48:40.20#ibcon#about to read 4, iclass 12, count 0 2006.258.00:48:40.20#ibcon#read 4, iclass 12, count 0 2006.258.00:48:40.20#ibcon#about to read 5, iclass 12, count 0 2006.258.00:48:40.20#ibcon#read 5, iclass 12, count 0 2006.258.00:48:40.20#ibcon#about to read 6, iclass 12, count 0 2006.258.00:48:40.20#ibcon#read 6, iclass 12, count 0 2006.258.00:48:40.20#ibcon#end of sib2, iclass 12, count 0 2006.258.00:48:40.20#ibcon#*mode == 0, iclass 12, count 0 2006.258.00:48:40.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.00:48:40.20#ibcon#[27=USB\r\n] 2006.258.00:48:40.20#ibcon#*before write, iclass 12, count 0 2006.258.00:48:40.20#ibcon#enter sib2, iclass 12, count 0 2006.258.00:48:40.20#ibcon#flushed, iclass 12, count 0 2006.258.00:48:40.20#ibcon#about to write, iclass 12, count 0 2006.258.00:48:40.20#ibcon#wrote, iclass 12, count 0 2006.258.00:48:40.20#ibcon#about to read 3, iclass 12, count 0 2006.258.00:48:40.23#ibcon#read 3, iclass 12, count 0 2006.258.00:48:40.23#ibcon#about to read 4, iclass 12, count 0 2006.258.00:48:40.23#ibcon#read 4, iclass 12, count 0 2006.258.00:48:40.23#ibcon#about to read 5, iclass 12, count 0 2006.258.00:48:40.23#ibcon#read 5, iclass 12, count 0 2006.258.00:48:40.23#ibcon#about to read 6, iclass 12, count 0 2006.258.00:48:40.23#ibcon#read 6, iclass 12, count 0 2006.258.00:48:40.23#ibcon#end of sib2, iclass 12, count 0 2006.258.00:48:40.23#ibcon#*after write, iclass 12, count 0 2006.258.00:48:40.23#ibcon#*before return 0, iclass 12, count 0 2006.258.00:48:40.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:40.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.258.00:48:40.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.00:48:40.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.00:48:40.23$vck44/vblo=8,744.99 2006.258.00:48:40.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.00:48:40.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.00:48:40.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:48:40.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:40.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:40.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:40.23#ibcon#enter wrdev, iclass 14, count 0 2006.258.00:48:40.23#ibcon#first serial, iclass 14, count 0 2006.258.00:48:40.23#ibcon#enter sib2, iclass 14, count 0 2006.258.00:48:40.23#ibcon#flushed, iclass 14, count 0 2006.258.00:48:40.23#ibcon#about to write, iclass 14, count 0 2006.258.00:48:40.23#ibcon#wrote, iclass 14, count 0 2006.258.00:48:40.23#ibcon#about to read 3, iclass 14, count 0 2006.258.00:48:40.25#ibcon#read 3, iclass 14, count 0 2006.258.00:48:40.25#ibcon#about to read 4, iclass 14, count 0 2006.258.00:48:40.25#ibcon#read 4, iclass 14, count 0 2006.258.00:48:40.25#ibcon#about to read 5, iclass 14, count 0 2006.258.00:48:40.25#ibcon#read 5, iclass 14, count 0 2006.258.00:48:40.25#ibcon#about to read 6, iclass 14, count 0 2006.258.00:48:40.25#ibcon#read 6, iclass 14, count 0 2006.258.00:48:40.25#ibcon#end of sib2, iclass 14, count 0 2006.258.00:48:40.25#ibcon#*mode == 0, iclass 14, count 0 2006.258.00:48:40.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.00:48:40.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:48:40.25#ibcon#*before write, iclass 14, count 0 2006.258.00:48:40.25#ibcon#enter sib2, iclass 14, count 0 2006.258.00:48:40.25#ibcon#flushed, iclass 14, count 0 2006.258.00:48:40.25#ibcon#about to write, iclass 14, count 0 2006.258.00:48:40.25#ibcon#wrote, iclass 14, count 0 2006.258.00:48:40.25#ibcon#about to read 3, iclass 14, count 0 2006.258.00:48:40.29#ibcon#read 3, iclass 14, count 0 2006.258.00:48:40.29#ibcon#about to read 4, iclass 14, count 0 2006.258.00:48:40.29#ibcon#read 4, iclass 14, count 0 2006.258.00:48:40.29#ibcon#about to read 5, iclass 14, count 0 2006.258.00:48:40.29#ibcon#read 5, iclass 14, count 0 2006.258.00:48:40.29#ibcon#about to read 6, iclass 14, count 0 2006.258.00:48:40.29#ibcon#read 6, iclass 14, count 0 2006.258.00:48:40.29#ibcon#end of sib2, iclass 14, count 0 2006.258.00:48:40.29#ibcon#*after write, iclass 14, count 0 2006.258.00:48:40.29#ibcon#*before return 0, iclass 14, count 0 2006.258.00:48:40.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:40.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.00:48:40.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.00:48:40.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.00:48:40.29$vck44/vb=8,4 2006.258.00:48:40.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.258.00:48:40.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.258.00:48:40.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:48:40.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:40.35#abcon#<5=/01 1.7 6.1 22.60 731016.2\r\n> 2006.258.00:48:40.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:40.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:40.35#ibcon#enter wrdev, iclass 16, count 2 2006.258.00:48:40.35#ibcon#first serial, iclass 16, count 2 2006.258.00:48:40.35#ibcon#enter sib2, iclass 16, count 2 2006.258.00:48:40.35#ibcon#flushed, iclass 16, count 2 2006.258.00:48:40.35#ibcon#about to write, iclass 16, count 2 2006.258.00:48:40.35#ibcon#wrote, iclass 16, count 2 2006.258.00:48:40.35#ibcon#about to read 3, iclass 16, count 2 2006.258.00:48:40.37#ibcon#read 3, iclass 16, count 2 2006.258.00:48:40.37#ibcon#about to read 4, iclass 16, count 2 2006.258.00:48:40.37#ibcon#read 4, iclass 16, count 2 2006.258.00:48:40.37#ibcon#about to read 5, iclass 16, count 2 2006.258.00:48:40.37#ibcon#read 5, iclass 16, count 2 2006.258.00:48:40.37#ibcon#about to read 6, iclass 16, count 2 2006.258.00:48:40.37#ibcon#read 6, iclass 16, count 2 2006.258.00:48:40.37#ibcon#end of sib2, iclass 16, count 2 2006.258.00:48:40.37#ibcon#*mode == 0, iclass 16, count 2 2006.258.00:48:40.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.258.00:48:40.37#ibcon#[27=AT08-04\r\n] 2006.258.00:48:40.37#ibcon#*before write, iclass 16, count 2 2006.258.00:48:40.37#ibcon#enter sib2, iclass 16, count 2 2006.258.00:48:40.37#ibcon#flushed, iclass 16, count 2 2006.258.00:48:40.37#ibcon#about to write, iclass 16, count 2 2006.258.00:48:40.37#ibcon#wrote, iclass 16, count 2 2006.258.00:48:40.37#ibcon#about to read 3, iclass 16, count 2 2006.258.00:48:40.37#abcon#{5=INTERFACE CLEAR} 2006.258.00:48:40.40#ibcon#read 3, iclass 16, count 2 2006.258.00:48:40.40#ibcon#about to read 4, iclass 16, count 2 2006.258.00:48:40.40#ibcon#read 4, iclass 16, count 2 2006.258.00:48:40.40#ibcon#about to read 5, iclass 16, count 2 2006.258.00:48:40.40#ibcon#read 5, iclass 16, count 2 2006.258.00:48:40.40#ibcon#about to read 6, iclass 16, count 2 2006.258.00:48:40.40#ibcon#read 6, iclass 16, count 2 2006.258.00:48:40.40#ibcon#end of sib2, iclass 16, count 2 2006.258.00:48:40.40#ibcon#*after write, iclass 16, count 2 2006.258.00:48:40.40#ibcon#*before return 0, iclass 16, count 2 2006.258.00:48:40.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:40.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.258.00:48:40.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.258.00:48:40.40#ibcon#ireg 7 cls_cnt 0 2006.258.00:48:40.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:40.43#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:48:40.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:40.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:40.52#ibcon#enter wrdev, iclass 16, count 0 2006.258.00:48:40.52#ibcon#first serial, iclass 16, count 0 2006.258.00:48:40.52#ibcon#enter sib2, iclass 16, count 0 2006.258.00:48:40.52#ibcon#flushed, iclass 16, count 0 2006.258.00:48:40.52#ibcon#about to write, iclass 16, count 0 2006.258.00:48:40.52#ibcon#wrote, iclass 16, count 0 2006.258.00:48:40.52#ibcon#about to read 3, iclass 16, count 0 2006.258.00:48:40.54#ibcon#read 3, iclass 16, count 0 2006.258.00:48:40.54#ibcon#about to read 4, iclass 16, count 0 2006.258.00:48:40.54#ibcon#read 4, iclass 16, count 0 2006.258.00:48:40.54#ibcon#about to read 5, iclass 16, count 0 2006.258.00:48:40.54#ibcon#read 5, iclass 16, count 0 2006.258.00:48:40.54#ibcon#about to read 6, iclass 16, count 0 2006.258.00:48:40.54#ibcon#read 6, iclass 16, count 0 2006.258.00:48:40.54#ibcon#end of sib2, iclass 16, count 0 2006.258.00:48:40.54#ibcon#*mode == 0, iclass 16, count 0 2006.258.00:48:40.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.00:48:40.54#ibcon#[27=USB\r\n] 2006.258.00:48:40.54#ibcon#*before write, iclass 16, count 0 2006.258.00:48:40.54#ibcon#enter sib2, iclass 16, count 0 2006.258.00:48:40.54#ibcon#flushed, iclass 16, count 0 2006.258.00:48:40.54#ibcon#about to write, iclass 16, count 0 2006.258.00:48:40.54#ibcon#wrote, iclass 16, count 0 2006.258.00:48:40.54#ibcon#about to read 3, iclass 16, count 0 2006.258.00:48:40.57#ibcon#read 3, iclass 16, count 0 2006.258.00:48:40.57#ibcon#about to read 4, iclass 16, count 0 2006.258.00:48:40.57#ibcon#read 4, iclass 16, count 0 2006.258.00:48:40.57#ibcon#about to read 5, iclass 16, count 0 2006.258.00:48:40.57#ibcon#read 5, iclass 16, count 0 2006.258.00:48:40.57#ibcon#about to read 6, iclass 16, count 0 2006.258.00:48:40.57#ibcon#read 6, iclass 16, count 0 2006.258.00:48:40.57#ibcon#end of sib2, iclass 16, count 0 2006.258.00:48:40.57#ibcon#*after write, iclass 16, count 0 2006.258.00:48:40.57#ibcon#*before return 0, iclass 16, count 0 2006.258.00:48:40.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:40.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.258.00:48:40.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.00:48:40.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.00:48:40.57$vck44/vabw=wide 2006.258.00:48:40.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.00:48:40.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.00:48:40.57#ibcon#ireg 8 cls_cnt 0 2006.258.00:48:40.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:40.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:40.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:40.57#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:48:40.57#ibcon#first serial, iclass 22, count 0 2006.258.00:48:40.57#ibcon#enter sib2, iclass 22, count 0 2006.258.00:48:40.57#ibcon#flushed, iclass 22, count 0 2006.258.00:48:40.57#ibcon#about to write, iclass 22, count 0 2006.258.00:48:40.57#ibcon#wrote, iclass 22, count 0 2006.258.00:48:40.57#ibcon#about to read 3, iclass 22, count 0 2006.258.00:48:40.59#ibcon#read 3, iclass 22, count 0 2006.258.00:48:40.59#ibcon#about to read 4, iclass 22, count 0 2006.258.00:48:40.59#ibcon#read 4, iclass 22, count 0 2006.258.00:48:40.59#ibcon#about to read 5, iclass 22, count 0 2006.258.00:48:40.59#ibcon#read 5, iclass 22, count 0 2006.258.00:48:40.59#ibcon#about to read 6, iclass 22, count 0 2006.258.00:48:40.59#ibcon#read 6, iclass 22, count 0 2006.258.00:48:40.59#ibcon#end of sib2, iclass 22, count 0 2006.258.00:48:40.59#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:48:40.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:48:40.59#ibcon#[25=BW32\r\n] 2006.258.00:48:40.59#ibcon#*before write, iclass 22, count 0 2006.258.00:48:40.59#ibcon#enter sib2, iclass 22, count 0 2006.258.00:48:40.59#ibcon#flushed, iclass 22, count 0 2006.258.00:48:40.59#ibcon#about to write, iclass 22, count 0 2006.258.00:48:40.59#ibcon#wrote, iclass 22, count 0 2006.258.00:48:40.59#ibcon#about to read 3, iclass 22, count 0 2006.258.00:48:40.62#ibcon#read 3, iclass 22, count 0 2006.258.00:48:40.62#ibcon#about to read 4, iclass 22, count 0 2006.258.00:48:40.62#ibcon#read 4, iclass 22, count 0 2006.258.00:48:40.62#ibcon#about to read 5, iclass 22, count 0 2006.258.00:48:40.62#ibcon#read 5, iclass 22, count 0 2006.258.00:48:40.62#ibcon#about to read 6, iclass 22, count 0 2006.258.00:48:40.62#ibcon#read 6, iclass 22, count 0 2006.258.00:48:40.62#ibcon#end of sib2, iclass 22, count 0 2006.258.00:48:40.62#ibcon#*after write, iclass 22, count 0 2006.258.00:48:40.62#ibcon#*before return 0, iclass 22, count 0 2006.258.00:48:40.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:40.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.00:48:40.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:48:40.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:48:40.62$vck44/vbbw=wide 2006.258.00:48:40.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.00:48:40.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.00:48:40.62#ibcon#ireg 8 cls_cnt 0 2006.258.00:48:40.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:48:40.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:48:40.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:48:40.69#ibcon#enter wrdev, iclass 24, count 0 2006.258.00:48:40.69#ibcon#first serial, iclass 24, count 0 2006.258.00:48:40.69#ibcon#enter sib2, iclass 24, count 0 2006.258.00:48:40.69#ibcon#flushed, iclass 24, count 0 2006.258.00:48:40.69#ibcon#about to write, iclass 24, count 0 2006.258.00:48:40.69#ibcon#wrote, iclass 24, count 0 2006.258.00:48:40.69#ibcon#about to read 3, iclass 24, count 0 2006.258.00:48:40.71#ibcon#read 3, iclass 24, count 0 2006.258.00:48:40.71#ibcon#about to read 4, iclass 24, count 0 2006.258.00:48:40.71#ibcon#read 4, iclass 24, count 0 2006.258.00:48:40.71#ibcon#about to read 5, iclass 24, count 0 2006.258.00:48:40.71#ibcon#read 5, iclass 24, count 0 2006.258.00:48:40.71#ibcon#about to read 6, iclass 24, count 0 2006.258.00:48:40.71#ibcon#read 6, iclass 24, count 0 2006.258.00:48:40.71#ibcon#end of sib2, iclass 24, count 0 2006.258.00:48:40.71#ibcon#*mode == 0, iclass 24, count 0 2006.258.00:48:40.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.00:48:40.71#ibcon#[27=BW32\r\n] 2006.258.00:48:40.71#ibcon#*before write, iclass 24, count 0 2006.258.00:48:40.71#ibcon#enter sib2, iclass 24, count 0 2006.258.00:48:40.71#ibcon#flushed, iclass 24, count 0 2006.258.00:48:40.71#ibcon#about to write, iclass 24, count 0 2006.258.00:48:40.71#ibcon#wrote, iclass 24, count 0 2006.258.00:48:40.71#ibcon#about to read 3, iclass 24, count 0 2006.258.00:48:40.74#ibcon#read 3, iclass 24, count 0 2006.258.00:48:40.74#ibcon#about to read 4, iclass 24, count 0 2006.258.00:48:40.74#ibcon#read 4, iclass 24, count 0 2006.258.00:48:40.74#ibcon#about to read 5, iclass 24, count 0 2006.258.00:48:40.74#ibcon#read 5, iclass 24, count 0 2006.258.00:48:40.74#ibcon#about to read 6, iclass 24, count 0 2006.258.00:48:40.74#ibcon#read 6, iclass 24, count 0 2006.258.00:48:40.74#ibcon#end of sib2, iclass 24, count 0 2006.258.00:48:40.74#ibcon#*after write, iclass 24, count 0 2006.258.00:48:40.74#ibcon#*before return 0, iclass 24, count 0 2006.258.00:48:40.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:48:40.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.00:48:40.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.00:48:40.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.00:48:40.74$setupk4/ifdk4 2006.258.00:48:40.74$ifdk4/lo= 2006.258.00:48:40.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:48:40.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:48:40.74$ifdk4/patch= 2006.258.00:48:40.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:48:40.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:48:40.74$setupk4/!*+20s 2006.258.00:48:50.52#abcon#<5=/01 1.7 6.1 22.60 731016.2\r\n> 2006.258.00:48:50.54#abcon#{5=INTERFACE CLEAR} 2006.258.00:48:50.60#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:48:55.25$setupk4/"tpicd 2006.258.00:48:55.25$setupk4/echo=off 2006.258.00:48:55.25$setupk4/xlog=off 2006.258.00:48:55.25:!2006.258.00:51:13 2006.258.00:49:28.13#trakl#Source acquired 2006.258.00:49:30.13#flagr#flagr/antenna,acquired 2006.258.00:51:13.00:preob 2006.258.00:51:13.14/onsource/TRACKING 2006.258.00:51:13.14:!2006.258.00:51:23 2006.258.00:51:23.00:"tape 2006.258.00:51:23.00:"st=record 2006.258.00:51:23.00:data_valid=on 2006.258.00:51:23.00:midob 2006.258.00:51:24.14/onsource/TRACKING 2006.258.00:51:24.14/wx/22.61,1016.2,74 2006.258.00:51:24.19/cable/+6.4790E-03 2006.258.00:51:25.28/va/01,08,usb,yes,30,33 2006.258.00:51:25.28/va/02,07,usb,yes,33,33 2006.258.00:51:25.28/va/03,08,usb,yes,29,31 2006.258.00:51:25.28/va/04,07,usb,yes,34,35 2006.258.00:51:25.28/va/05,04,usb,yes,30,31 2006.258.00:51:25.28/va/06,04,usb,yes,34,33 2006.258.00:51:25.28/va/07,04,usb,yes,35,35 2006.258.00:51:25.28/va/08,04,usb,yes,29,35 2006.258.00:51:25.51/valo/01,524.99,yes,locked 2006.258.00:51:25.51/valo/02,534.99,yes,locked 2006.258.00:51:25.51/valo/03,564.99,yes,locked 2006.258.00:51:25.51/valo/04,624.99,yes,locked 2006.258.00:51:25.51/valo/05,734.99,yes,locked 2006.258.00:51:25.51/valo/06,814.99,yes,locked 2006.258.00:51:25.51/valo/07,864.99,yes,locked 2006.258.00:51:25.51/valo/08,884.99,yes,locked 2006.258.00:51:26.60/vb/01,04,usb,yes,30,28 2006.258.00:51:26.60/vb/02,05,usb,yes,29,28 2006.258.00:51:26.60/vb/03,04,usb,yes,29,32 2006.258.00:51:26.60/vb/04,05,usb,yes,30,29 2006.258.00:51:26.60/vb/05,04,usb,yes,26,29 2006.258.00:51:26.60/vb/06,04,usb,yes,31,27 2006.258.00:51:26.60/vb/07,04,usb,yes,30,30 2006.258.00:51:26.60/vb/08,04,usb,yes,28,31 2006.258.00:51:26.84/vblo/01,629.99,yes,locked 2006.258.00:51:26.84/vblo/02,634.99,yes,locked 2006.258.00:51:26.84/vblo/03,649.99,yes,locked 2006.258.00:51:26.84/vblo/04,679.99,yes,locked 2006.258.00:51:26.84/vblo/05,709.99,yes,locked 2006.258.00:51:26.84/vblo/06,719.99,yes,locked 2006.258.00:51:26.84/vblo/07,734.99,yes,locked 2006.258.00:51:26.84/vblo/08,744.99,yes,locked 2006.258.00:51:26.99/vabw/8 2006.258.00:51:27.14/vbbw/8 2006.258.00:51:27.31/xfe/off,on,15.0 2006.258.00:51:27.69/ifatt/23,28,28,28 2006.258.00:51:28.07/fmout-gps/S +4.57E-07 2006.258.00:51:28.11:!2006.258.00:56:13 2006.258.00:56:13.01:data_valid=off 2006.258.00:56:13.01:"et 2006.258.00:56:13.01:!+3s 2006.258.00:56:16.02:"tape 2006.258.00:56:16.02:postob 2006.258.00:56:16.19/cable/+6.4761E-03 2006.258.00:56:16.19/wx/22.65,1016.2,76 2006.258.00:56:16.25/fmout-gps/S +4.58E-07 2006.258.00:56:16.25:scan_name=258-0100,jd0609,350 2006.258.00:56:16.25:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.258.00:56:17.14:checkk5 2006.258.00:56:17.14#flagr#flagr/antenna,new-source 2006.258.00:56:17.57/chk_autoobs//k5ts1/ autoobs is running! 2006.258.00:56:17.96/chk_autoobs//k5ts2/ autoobs is running! 2006.258.00:56:18.37/chk_autoobs//k5ts3/ autoobs is running! 2006.258.00:56:18.77/chk_autoobs//k5ts4/ autoobs is running! 2006.258.00:56:19.16/chk_obsdata//k5ts1/T2580051??a.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.258.00:56:19.58/chk_obsdata//k5ts2/T2580051??b.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.258.00:56:19.97/chk_obsdata//k5ts3/T2580051??c.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.258.00:56:20.37/chk_obsdata//k5ts4/T2580051??d.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.258.00:56:21.10/k5log//k5ts1_log_newline 2006.258.00:56:21.80/k5log//k5ts2_log_newline 2006.258.00:56:22.52/k5log//k5ts3_log_newline 2006.258.00:56:23.21/k5log//k5ts4_log_newline 2006.258.00:56:23.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.00:56:23.24:setupk4=1 2006.258.00:56:23.24$setupk4/echo=on 2006.258.00:56:23.24$setupk4/pcalon 2006.258.00:56:23.24$pcalon/"no phase cal control is implemented here 2006.258.00:56:23.24$setupk4/"tpicd=stop 2006.258.00:56:23.24$setupk4/"rec=synch_on 2006.258.00:56:23.24$setupk4/"rec_mode=128 2006.258.00:56:23.24$setupk4/!* 2006.258.00:56:23.24$setupk4/recpk4 2006.258.00:56:23.24$recpk4/recpatch= 2006.258.00:56:23.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.00:56:23.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.00:56:23.24$setupk4/vck44 2006.258.00:56:23.24$vck44/valo=1,524.99 2006.258.00:56:23.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.00:56:23.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.00:56:23.24#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:23.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:23.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:23.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:23.24#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:56:23.24#ibcon#first serial, iclass 29, count 0 2006.258.00:56:23.24#ibcon#enter sib2, iclass 29, count 0 2006.258.00:56:23.24#ibcon#flushed, iclass 29, count 0 2006.258.00:56:23.24#ibcon#about to write, iclass 29, count 0 2006.258.00:56:23.24#ibcon#wrote, iclass 29, count 0 2006.258.00:56:23.24#ibcon#about to read 3, iclass 29, count 0 2006.258.00:56:23.26#ibcon#read 3, iclass 29, count 0 2006.258.00:56:23.26#ibcon#about to read 4, iclass 29, count 0 2006.258.00:56:23.26#ibcon#read 4, iclass 29, count 0 2006.258.00:56:23.26#ibcon#about to read 5, iclass 29, count 0 2006.258.00:56:23.26#ibcon#read 5, iclass 29, count 0 2006.258.00:56:23.26#ibcon#about to read 6, iclass 29, count 0 2006.258.00:56:23.26#ibcon#read 6, iclass 29, count 0 2006.258.00:56:23.26#ibcon#end of sib2, iclass 29, count 0 2006.258.00:56:23.26#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:56:23.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:56:23.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.00:56:23.26#ibcon#*before write, iclass 29, count 0 2006.258.00:56:23.26#ibcon#enter sib2, iclass 29, count 0 2006.258.00:56:23.26#ibcon#flushed, iclass 29, count 0 2006.258.00:56:23.26#ibcon#about to write, iclass 29, count 0 2006.258.00:56:23.26#ibcon#wrote, iclass 29, count 0 2006.258.00:56:23.26#ibcon#about to read 3, iclass 29, count 0 2006.258.00:56:23.31#ibcon#read 3, iclass 29, count 0 2006.258.00:56:23.31#ibcon#about to read 4, iclass 29, count 0 2006.258.00:56:23.31#ibcon#read 4, iclass 29, count 0 2006.258.00:56:23.31#ibcon#about to read 5, iclass 29, count 0 2006.258.00:56:23.31#ibcon#read 5, iclass 29, count 0 2006.258.00:56:23.31#ibcon#about to read 6, iclass 29, count 0 2006.258.00:56:23.31#ibcon#read 6, iclass 29, count 0 2006.258.00:56:23.31#ibcon#end of sib2, iclass 29, count 0 2006.258.00:56:23.31#ibcon#*after write, iclass 29, count 0 2006.258.00:56:23.31#ibcon#*before return 0, iclass 29, count 0 2006.258.00:56:23.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:23.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:23.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:56:23.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:56:23.31$vck44/va=1,8 2006.258.00:56:23.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.00:56:23.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.00:56:23.31#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:23.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:23.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:23.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:23.31#ibcon#enter wrdev, iclass 31, count 2 2006.258.00:56:23.31#ibcon#first serial, iclass 31, count 2 2006.258.00:56:23.31#ibcon#enter sib2, iclass 31, count 2 2006.258.00:56:23.31#ibcon#flushed, iclass 31, count 2 2006.258.00:56:23.31#ibcon#about to write, iclass 31, count 2 2006.258.00:56:23.31#ibcon#wrote, iclass 31, count 2 2006.258.00:56:23.31#ibcon#about to read 3, iclass 31, count 2 2006.258.00:56:23.33#ibcon#read 3, iclass 31, count 2 2006.258.00:56:23.33#ibcon#about to read 4, iclass 31, count 2 2006.258.00:56:23.33#ibcon#read 4, iclass 31, count 2 2006.258.00:56:23.33#ibcon#about to read 5, iclass 31, count 2 2006.258.00:56:23.33#ibcon#read 5, iclass 31, count 2 2006.258.00:56:23.33#ibcon#about to read 6, iclass 31, count 2 2006.258.00:56:23.33#ibcon#read 6, iclass 31, count 2 2006.258.00:56:23.33#ibcon#end of sib2, iclass 31, count 2 2006.258.00:56:23.33#ibcon#*mode == 0, iclass 31, count 2 2006.258.00:56:23.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.00:56:23.33#ibcon#[25=AT01-08\r\n] 2006.258.00:56:23.33#ibcon#*before write, iclass 31, count 2 2006.258.00:56:23.33#ibcon#enter sib2, iclass 31, count 2 2006.258.00:56:23.33#ibcon#flushed, iclass 31, count 2 2006.258.00:56:23.33#ibcon#about to write, iclass 31, count 2 2006.258.00:56:23.33#ibcon#wrote, iclass 31, count 2 2006.258.00:56:23.33#ibcon#about to read 3, iclass 31, count 2 2006.258.00:56:23.36#ibcon#read 3, iclass 31, count 2 2006.258.00:56:23.36#ibcon#about to read 4, iclass 31, count 2 2006.258.00:56:23.36#ibcon#read 4, iclass 31, count 2 2006.258.00:56:23.36#ibcon#about to read 5, iclass 31, count 2 2006.258.00:56:23.36#ibcon#read 5, iclass 31, count 2 2006.258.00:56:23.36#ibcon#about to read 6, iclass 31, count 2 2006.258.00:56:23.36#ibcon#read 6, iclass 31, count 2 2006.258.00:56:23.36#ibcon#end of sib2, iclass 31, count 2 2006.258.00:56:23.36#ibcon#*after write, iclass 31, count 2 2006.258.00:56:23.36#ibcon#*before return 0, iclass 31, count 2 2006.258.00:56:23.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:23.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:23.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.00:56:23.36#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:23.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:23.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:23.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:23.48#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:56:23.48#ibcon#first serial, iclass 31, count 0 2006.258.00:56:23.48#ibcon#enter sib2, iclass 31, count 0 2006.258.00:56:23.48#ibcon#flushed, iclass 31, count 0 2006.258.00:56:23.48#ibcon#about to write, iclass 31, count 0 2006.258.00:56:23.48#ibcon#wrote, iclass 31, count 0 2006.258.00:56:23.48#ibcon#about to read 3, iclass 31, count 0 2006.258.00:56:23.50#ibcon#read 3, iclass 31, count 0 2006.258.00:56:23.50#ibcon#about to read 4, iclass 31, count 0 2006.258.00:56:23.50#ibcon#read 4, iclass 31, count 0 2006.258.00:56:23.50#ibcon#about to read 5, iclass 31, count 0 2006.258.00:56:23.50#ibcon#read 5, iclass 31, count 0 2006.258.00:56:23.50#ibcon#about to read 6, iclass 31, count 0 2006.258.00:56:23.50#ibcon#read 6, iclass 31, count 0 2006.258.00:56:23.50#ibcon#end of sib2, iclass 31, count 0 2006.258.00:56:23.50#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:56:23.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:56:23.50#ibcon#[25=USB\r\n] 2006.258.00:56:23.50#ibcon#*before write, iclass 31, count 0 2006.258.00:56:23.50#ibcon#enter sib2, iclass 31, count 0 2006.258.00:56:23.50#ibcon#flushed, iclass 31, count 0 2006.258.00:56:23.50#ibcon#about to write, iclass 31, count 0 2006.258.00:56:23.50#ibcon#wrote, iclass 31, count 0 2006.258.00:56:23.50#ibcon#about to read 3, iclass 31, count 0 2006.258.00:56:23.53#ibcon#read 3, iclass 31, count 0 2006.258.00:56:23.53#ibcon#about to read 4, iclass 31, count 0 2006.258.00:56:23.53#ibcon#read 4, iclass 31, count 0 2006.258.00:56:23.53#ibcon#about to read 5, iclass 31, count 0 2006.258.00:56:23.53#ibcon#read 5, iclass 31, count 0 2006.258.00:56:23.53#ibcon#about to read 6, iclass 31, count 0 2006.258.00:56:23.53#ibcon#read 6, iclass 31, count 0 2006.258.00:56:23.53#ibcon#end of sib2, iclass 31, count 0 2006.258.00:56:23.53#ibcon#*after write, iclass 31, count 0 2006.258.00:56:23.53#ibcon#*before return 0, iclass 31, count 0 2006.258.00:56:23.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:23.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:23.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:56:23.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:56:23.53$vck44/valo=2,534.99 2006.258.00:56:23.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.00:56:23.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.00:56:23.53#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:23.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:23.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:23.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:23.53#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:56:23.53#ibcon#first serial, iclass 33, count 0 2006.258.00:56:23.53#ibcon#enter sib2, iclass 33, count 0 2006.258.00:56:23.53#ibcon#flushed, iclass 33, count 0 2006.258.00:56:23.53#ibcon#about to write, iclass 33, count 0 2006.258.00:56:23.53#ibcon#wrote, iclass 33, count 0 2006.258.00:56:23.53#ibcon#about to read 3, iclass 33, count 0 2006.258.00:56:23.55#ibcon#read 3, iclass 33, count 0 2006.258.00:56:23.55#ibcon#about to read 4, iclass 33, count 0 2006.258.00:56:23.55#ibcon#read 4, iclass 33, count 0 2006.258.00:56:23.55#ibcon#about to read 5, iclass 33, count 0 2006.258.00:56:23.55#ibcon#read 5, iclass 33, count 0 2006.258.00:56:23.55#ibcon#about to read 6, iclass 33, count 0 2006.258.00:56:23.55#ibcon#read 6, iclass 33, count 0 2006.258.00:56:23.55#ibcon#end of sib2, iclass 33, count 0 2006.258.00:56:23.55#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:56:23.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:56:23.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.00:56:23.55#ibcon#*before write, iclass 33, count 0 2006.258.00:56:23.55#ibcon#enter sib2, iclass 33, count 0 2006.258.00:56:23.55#ibcon#flushed, iclass 33, count 0 2006.258.00:56:23.55#ibcon#about to write, iclass 33, count 0 2006.258.00:56:23.55#ibcon#wrote, iclass 33, count 0 2006.258.00:56:23.55#ibcon#about to read 3, iclass 33, count 0 2006.258.00:56:23.59#ibcon#read 3, iclass 33, count 0 2006.258.00:56:23.59#ibcon#about to read 4, iclass 33, count 0 2006.258.00:56:23.59#ibcon#read 4, iclass 33, count 0 2006.258.00:56:23.59#ibcon#about to read 5, iclass 33, count 0 2006.258.00:56:23.59#ibcon#read 5, iclass 33, count 0 2006.258.00:56:23.59#ibcon#about to read 6, iclass 33, count 0 2006.258.00:56:23.59#ibcon#read 6, iclass 33, count 0 2006.258.00:56:23.59#ibcon#end of sib2, iclass 33, count 0 2006.258.00:56:23.59#ibcon#*after write, iclass 33, count 0 2006.258.00:56:23.59#ibcon#*before return 0, iclass 33, count 0 2006.258.00:56:23.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:23.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:23.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:56:23.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:56:23.59$vck44/va=2,7 2006.258.00:56:23.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.00:56:23.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.00:56:23.59#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:23.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:23.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:23.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:23.65#ibcon#enter wrdev, iclass 35, count 2 2006.258.00:56:23.65#ibcon#first serial, iclass 35, count 2 2006.258.00:56:23.65#ibcon#enter sib2, iclass 35, count 2 2006.258.00:56:23.65#ibcon#flushed, iclass 35, count 2 2006.258.00:56:23.65#ibcon#about to write, iclass 35, count 2 2006.258.00:56:23.65#ibcon#wrote, iclass 35, count 2 2006.258.00:56:23.65#ibcon#about to read 3, iclass 35, count 2 2006.258.00:56:23.67#ibcon#read 3, iclass 35, count 2 2006.258.00:56:23.67#ibcon#about to read 4, iclass 35, count 2 2006.258.00:56:23.67#ibcon#read 4, iclass 35, count 2 2006.258.00:56:23.67#ibcon#about to read 5, iclass 35, count 2 2006.258.00:56:23.67#ibcon#read 5, iclass 35, count 2 2006.258.00:56:23.67#ibcon#about to read 6, iclass 35, count 2 2006.258.00:56:23.67#ibcon#read 6, iclass 35, count 2 2006.258.00:56:23.67#ibcon#end of sib2, iclass 35, count 2 2006.258.00:56:23.67#ibcon#*mode == 0, iclass 35, count 2 2006.258.00:56:23.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.00:56:23.67#ibcon#[25=AT02-07\r\n] 2006.258.00:56:23.67#ibcon#*before write, iclass 35, count 2 2006.258.00:56:23.67#ibcon#enter sib2, iclass 35, count 2 2006.258.00:56:23.67#ibcon#flushed, iclass 35, count 2 2006.258.00:56:23.67#ibcon#about to write, iclass 35, count 2 2006.258.00:56:23.67#ibcon#wrote, iclass 35, count 2 2006.258.00:56:23.67#ibcon#about to read 3, iclass 35, count 2 2006.258.00:56:23.70#ibcon#read 3, iclass 35, count 2 2006.258.00:56:23.70#ibcon#about to read 4, iclass 35, count 2 2006.258.00:56:23.70#ibcon#read 4, iclass 35, count 2 2006.258.00:56:23.70#ibcon#about to read 5, iclass 35, count 2 2006.258.00:56:23.70#ibcon#read 5, iclass 35, count 2 2006.258.00:56:23.70#ibcon#about to read 6, iclass 35, count 2 2006.258.00:56:23.70#ibcon#read 6, iclass 35, count 2 2006.258.00:56:23.70#ibcon#end of sib2, iclass 35, count 2 2006.258.00:56:23.70#ibcon#*after write, iclass 35, count 2 2006.258.00:56:23.70#ibcon#*before return 0, iclass 35, count 2 2006.258.00:56:23.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:23.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:23.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.00:56:23.70#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:23.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:23.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:23.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:23.82#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:56:23.82#ibcon#first serial, iclass 35, count 0 2006.258.00:56:23.82#ibcon#enter sib2, iclass 35, count 0 2006.258.00:56:23.82#ibcon#flushed, iclass 35, count 0 2006.258.00:56:23.82#ibcon#about to write, iclass 35, count 0 2006.258.00:56:23.82#ibcon#wrote, iclass 35, count 0 2006.258.00:56:23.82#ibcon#about to read 3, iclass 35, count 0 2006.258.00:56:23.84#ibcon#read 3, iclass 35, count 0 2006.258.00:56:23.84#ibcon#about to read 4, iclass 35, count 0 2006.258.00:56:23.84#ibcon#read 4, iclass 35, count 0 2006.258.00:56:23.84#ibcon#about to read 5, iclass 35, count 0 2006.258.00:56:23.84#ibcon#read 5, iclass 35, count 0 2006.258.00:56:23.84#ibcon#about to read 6, iclass 35, count 0 2006.258.00:56:23.84#ibcon#read 6, iclass 35, count 0 2006.258.00:56:23.84#ibcon#end of sib2, iclass 35, count 0 2006.258.00:56:23.84#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:56:23.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:56:23.84#ibcon#[25=USB\r\n] 2006.258.00:56:23.84#ibcon#*before write, iclass 35, count 0 2006.258.00:56:23.84#ibcon#enter sib2, iclass 35, count 0 2006.258.00:56:23.84#ibcon#flushed, iclass 35, count 0 2006.258.00:56:23.84#ibcon#about to write, iclass 35, count 0 2006.258.00:56:23.84#ibcon#wrote, iclass 35, count 0 2006.258.00:56:23.84#ibcon#about to read 3, iclass 35, count 0 2006.258.00:56:23.87#ibcon#read 3, iclass 35, count 0 2006.258.00:56:23.87#ibcon#about to read 4, iclass 35, count 0 2006.258.00:56:23.87#ibcon#read 4, iclass 35, count 0 2006.258.00:56:23.87#ibcon#about to read 5, iclass 35, count 0 2006.258.00:56:23.87#ibcon#read 5, iclass 35, count 0 2006.258.00:56:23.87#ibcon#about to read 6, iclass 35, count 0 2006.258.00:56:23.87#ibcon#read 6, iclass 35, count 0 2006.258.00:56:23.87#ibcon#end of sib2, iclass 35, count 0 2006.258.00:56:23.87#ibcon#*after write, iclass 35, count 0 2006.258.00:56:23.87#ibcon#*before return 0, iclass 35, count 0 2006.258.00:56:23.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:23.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:23.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:56:23.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:56:23.87$vck44/valo=3,564.99 2006.258.00:56:23.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.00:56:23.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.00:56:23.87#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:23.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:23.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:23.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:23.87#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:56:23.87#ibcon#first serial, iclass 37, count 0 2006.258.00:56:23.87#ibcon#enter sib2, iclass 37, count 0 2006.258.00:56:23.87#ibcon#flushed, iclass 37, count 0 2006.258.00:56:23.87#ibcon#about to write, iclass 37, count 0 2006.258.00:56:23.87#ibcon#wrote, iclass 37, count 0 2006.258.00:56:23.87#ibcon#about to read 3, iclass 37, count 0 2006.258.00:56:23.89#ibcon#read 3, iclass 37, count 0 2006.258.00:56:23.89#ibcon#about to read 4, iclass 37, count 0 2006.258.00:56:23.89#ibcon#read 4, iclass 37, count 0 2006.258.00:56:23.89#ibcon#about to read 5, iclass 37, count 0 2006.258.00:56:23.89#ibcon#read 5, iclass 37, count 0 2006.258.00:56:23.89#ibcon#about to read 6, iclass 37, count 0 2006.258.00:56:23.89#ibcon#read 6, iclass 37, count 0 2006.258.00:56:23.89#ibcon#end of sib2, iclass 37, count 0 2006.258.00:56:23.89#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:56:23.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:56:23.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.00:56:23.89#ibcon#*before write, iclass 37, count 0 2006.258.00:56:23.89#ibcon#enter sib2, iclass 37, count 0 2006.258.00:56:23.89#ibcon#flushed, iclass 37, count 0 2006.258.00:56:23.89#ibcon#about to write, iclass 37, count 0 2006.258.00:56:23.89#ibcon#wrote, iclass 37, count 0 2006.258.00:56:23.89#ibcon#about to read 3, iclass 37, count 0 2006.258.00:56:23.93#ibcon#read 3, iclass 37, count 0 2006.258.00:56:23.93#ibcon#about to read 4, iclass 37, count 0 2006.258.00:56:23.93#ibcon#read 4, iclass 37, count 0 2006.258.00:56:23.93#ibcon#about to read 5, iclass 37, count 0 2006.258.00:56:23.93#ibcon#read 5, iclass 37, count 0 2006.258.00:56:23.93#ibcon#about to read 6, iclass 37, count 0 2006.258.00:56:23.93#ibcon#read 6, iclass 37, count 0 2006.258.00:56:23.93#ibcon#end of sib2, iclass 37, count 0 2006.258.00:56:23.93#ibcon#*after write, iclass 37, count 0 2006.258.00:56:23.93#ibcon#*before return 0, iclass 37, count 0 2006.258.00:56:23.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:23.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:23.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:56:23.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:56:23.93$vck44/va=3,8 2006.258.00:56:23.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.258.00:56:23.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.258.00:56:23.93#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:23.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:23.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:23.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:23.99#ibcon#enter wrdev, iclass 39, count 2 2006.258.00:56:23.99#ibcon#first serial, iclass 39, count 2 2006.258.00:56:23.99#ibcon#enter sib2, iclass 39, count 2 2006.258.00:56:23.99#ibcon#flushed, iclass 39, count 2 2006.258.00:56:23.99#ibcon#about to write, iclass 39, count 2 2006.258.00:56:23.99#ibcon#wrote, iclass 39, count 2 2006.258.00:56:23.99#ibcon#about to read 3, iclass 39, count 2 2006.258.00:56:24.01#ibcon#read 3, iclass 39, count 2 2006.258.00:56:24.01#ibcon#about to read 4, iclass 39, count 2 2006.258.00:56:24.01#ibcon#read 4, iclass 39, count 2 2006.258.00:56:24.01#ibcon#about to read 5, iclass 39, count 2 2006.258.00:56:24.01#ibcon#read 5, iclass 39, count 2 2006.258.00:56:24.01#ibcon#about to read 6, iclass 39, count 2 2006.258.00:56:24.01#ibcon#read 6, iclass 39, count 2 2006.258.00:56:24.01#ibcon#end of sib2, iclass 39, count 2 2006.258.00:56:24.01#ibcon#*mode == 0, iclass 39, count 2 2006.258.00:56:24.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.258.00:56:24.01#ibcon#[25=AT03-08\r\n] 2006.258.00:56:24.01#ibcon#*before write, iclass 39, count 2 2006.258.00:56:24.01#ibcon#enter sib2, iclass 39, count 2 2006.258.00:56:24.01#ibcon#flushed, iclass 39, count 2 2006.258.00:56:24.01#ibcon#about to write, iclass 39, count 2 2006.258.00:56:24.01#ibcon#wrote, iclass 39, count 2 2006.258.00:56:24.01#ibcon#about to read 3, iclass 39, count 2 2006.258.00:56:24.04#ibcon#read 3, iclass 39, count 2 2006.258.00:56:24.04#ibcon#about to read 4, iclass 39, count 2 2006.258.00:56:24.04#ibcon#read 4, iclass 39, count 2 2006.258.00:56:24.04#ibcon#about to read 5, iclass 39, count 2 2006.258.00:56:24.04#ibcon#read 5, iclass 39, count 2 2006.258.00:56:24.04#ibcon#about to read 6, iclass 39, count 2 2006.258.00:56:24.04#ibcon#read 6, iclass 39, count 2 2006.258.00:56:24.04#ibcon#end of sib2, iclass 39, count 2 2006.258.00:56:24.04#ibcon#*after write, iclass 39, count 2 2006.258.00:56:24.04#ibcon#*before return 0, iclass 39, count 2 2006.258.00:56:24.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:24.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:24.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.258.00:56:24.04#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:24.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:24.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:24.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:24.16#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:56:24.16#ibcon#first serial, iclass 39, count 0 2006.258.00:56:24.16#ibcon#enter sib2, iclass 39, count 0 2006.258.00:56:24.16#ibcon#flushed, iclass 39, count 0 2006.258.00:56:24.16#ibcon#about to write, iclass 39, count 0 2006.258.00:56:24.16#ibcon#wrote, iclass 39, count 0 2006.258.00:56:24.16#ibcon#about to read 3, iclass 39, count 0 2006.258.00:56:24.18#ibcon#read 3, iclass 39, count 0 2006.258.00:56:24.18#ibcon#about to read 4, iclass 39, count 0 2006.258.00:56:24.18#ibcon#read 4, iclass 39, count 0 2006.258.00:56:24.18#ibcon#about to read 5, iclass 39, count 0 2006.258.00:56:24.18#ibcon#read 5, iclass 39, count 0 2006.258.00:56:24.18#ibcon#about to read 6, iclass 39, count 0 2006.258.00:56:24.18#ibcon#read 6, iclass 39, count 0 2006.258.00:56:24.18#ibcon#end of sib2, iclass 39, count 0 2006.258.00:56:24.18#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:56:24.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:56:24.18#ibcon#[25=USB\r\n] 2006.258.00:56:24.18#ibcon#*before write, iclass 39, count 0 2006.258.00:56:24.18#ibcon#enter sib2, iclass 39, count 0 2006.258.00:56:24.18#ibcon#flushed, iclass 39, count 0 2006.258.00:56:24.18#ibcon#about to write, iclass 39, count 0 2006.258.00:56:24.18#ibcon#wrote, iclass 39, count 0 2006.258.00:56:24.18#ibcon#about to read 3, iclass 39, count 0 2006.258.00:56:24.21#ibcon#read 3, iclass 39, count 0 2006.258.00:56:24.21#ibcon#about to read 4, iclass 39, count 0 2006.258.00:56:24.21#ibcon#read 4, iclass 39, count 0 2006.258.00:56:24.21#ibcon#about to read 5, iclass 39, count 0 2006.258.00:56:24.21#ibcon#read 5, iclass 39, count 0 2006.258.00:56:24.21#ibcon#about to read 6, iclass 39, count 0 2006.258.00:56:24.21#ibcon#read 6, iclass 39, count 0 2006.258.00:56:24.21#ibcon#end of sib2, iclass 39, count 0 2006.258.00:56:24.21#ibcon#*after write, iclass 39, count 0 2006.258.00:56:24.21#ibcon#*before return 0, iclass 39, count 0 2006.258.00:56:24.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:24.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:24.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:56:24.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:56:24.21$vck44/valo=4,624.99 2006.258.00:56:24.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.00:56:24.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.00:56:24.21#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:24.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:24.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:24.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:24.21#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:56:24.21#ibcon#first serial, iclass 3, count 0 2006.258.00:56:24.21#ibcon#enter sib2, iclass 3, count 0 2006.258.00:56:24.21#ibcon#flushed, iclass 3, count 0 2006.258.00:56:24.21#ibcon#about to write, iclass 3, count 0 2006.258.00:56:24.21#ibcon#wrote, iclass 3, count 0 2006.258.00:56:24.21#ibcon#about to read 3, iclass 3, count 0 2006.258.00:56:24.23#ibcon#read 3, iclass 3, count 0 2006.258.00:56:24.23#ibcon#about to read 4, iclass 3, count 0 2006.258.00:56:24.23#ibcon#read 4, iclass 3, count 0 2006.258.00:56:24.23#ibcon#about to read 5, iclass 3, count 0 2006.258.00:56:24.23#ibcon#read 5, iclass 3, count 0 2006.258.00:56:24.23#ibcon#about to read 6, iclass 3, count 0 2006.258.00:56:24.23#ibcon#read 6, iclass 3, count 0 2006.258.00:56:24.23#ibcon#end of sib2, iclass 3, count 0 2006.258.00:56:24.23#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:56:24.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:56:24.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.00:56:24.23#ibcon#*before write, iclass 3, count 0 2006.258.00:56:24.23#ibcon#enter sib2, iclass 3, count 0 2006.258.00:56:24.23#ibcon#flushed, iclass 3, count 0 2006.258.00:56:24.23#ibcon#about to write, iclass 3, count 0 2006.258.00:56:24.23#ibcon#wrote, iclass 3, count 0 2006.258.00:56:24.23#ibcon#about to read 3, iclass 3, count 0 2006.258.00:56:24.27#ibcon#read 3, iclass 3, count 0 2006.258.00:56:24.27#ibcon#about to read 4, iclass 3, count 0 2006.258.00:56:24.27#ibcon#read 4, iclass 3, count 0 2006.258.00:56:24.27#ibcon#about to read 5, iclass 3, count 0 2006.258.00:56:24.27#ibcon#read 5, iclass 3, count 0 2006.258.00:56:24.27#ibcon#about to read 6, iclass 3, count 0 2006.258.00:56:24.27#ibcon#read 6, iclass 3, count 0 2006.258.00:56:24.27#ibcon#end of sib2, iclass 3, count 0 2006.258.00:56:24.27#ibcon#*after write, iclass 3, count 0 2006.258.00:56:24.27#ibcon#*before return 0, iclass 3, count 0 2006.258.00:56:24.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:24.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:24.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:56:24.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:56:24.27$vck44/va=4,7 2006.258.00:56:24.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.258.00:56:24.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.258.00:56:24.27#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:24.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:24.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:24.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:24.33#ibcon#enter wrdev, iclass 5, count 2 2006.258.00:56:24.33#ibcon#first serial, iclass 5, count 2 2006.258.00:56:24.33#ibcon#enter sib2, iclass 5, count 2 2006.258.00:56:24.33#ibcon#flushed, iclass 5, count 2 2006.258.00:56:24.33#ibcon#about to write, iclass 5, count 2 2006.258.00:56:24.33#ibcon#wrote, iclass 5, count 2 2006.258.00:56:24.33#ibcon#about to read 3, iclass 5, count 2 2006.258.00:56:24.35#ibcon#read 3, iclass 5, count 2 2006.258.00:56:24.35#ibcon#about to read 4, iclass 5, count 2 2006.258.00:56:24.35#ibcon#read 4, iclass 5, count 2 2006.258.00:56:24.35#ibcon#about to read 5, iclass 5, count 2 2006.258.00:56:24.35#ibcon#read 5, iclass 5, count 2 2006.258.00:56:24.35#ibcon#about to read 6, iclass 5, count 2 2006.258.00:56:24.35#ibcon#read 6, iclass 5, count 2 2006.258.00:56:24.35#ibcon#end of sib2, iclass 5, count 2 2006.258.00:56:24.35#ibcon#*mode == 0, iclass 5, count 2 2006.258.00:56:24.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.258.00:56:24.35#ibcon#[25=AT04-07\r\n] 2006.258.00:56:24.35#ibcon#*before write, iclass 5, count 2 2006.258.00:56:24.35#ibcon#enter sib2, iclass 5, count 2 2006.258.00:56:24.35#ibcon#flushed, iclass 5, count 2 2006.258.00:56:24.35#ibcon#about to write, iclass 5, count 2 2006.258.00:56:24.35#ibcon#wrote, iclass 5, count 2 2006.258.00:56:24.35#ibcon#about to read 3, iclass 5, count 2 2006.258.00:56:24.38#ibcon#read 3, iclass 5, count 2 2006.258.00:56:24.38#ibcon#about to read 4, iclass 5, count 2 2006.258.00:56:24.38#ibcon#read 4, iclass 5, count 2 2006.258.00:56:24.38#ibcon#about to read 5, iclass 5, count 2 2006.258.00:56:24.38#ibcon#read 5, iclass 5, count 2 2006.258.00:56:24.38#ibcon#about to read 6, iclass 5, count 2 2006.258.00:56:24.38#ibcon#read 6, iclass 5, count 2 2006.258.00:56:24.38#ibcon#end of sib2, iclass 5, count 2 2006.258.00:56:24.38#ibcon#*after write, iclass 5, count 2 2006.258.00:56:24.38#ibcon#*before return 0, iclass 5, count 2 2006.258.00:56:24.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:24.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:24.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.258.00:56:24.39#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:24.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:24.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:24.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:24.50#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:56:24.50#ibcon#first serial, iclass 5, count 0 2006.258.00:56:24.50#ibcon#enter sib2, iclass 5, count 0 2006.258.00:56:24.50#ibcon#flushed, iclass 5, count 0 2006.258.00:56:24.50#ibcon#about to write, iclass 5, count 0 2006.258.00:56:24.50#ibcon#wrote, iclass 5, count 0 2006.258.00:56:24.50#ibcon#about to read 3, iclass 5, count 0 2006.258.00:56:24.52#ibcon#read 3, iclass 5, count 0 2006.258.00:56:24.52#ibcon#about to read 4, iclass 5, count 0 2006.258.00:56:24.52#ibcon#read 4, iclass 5, count 0 2006.258.00:56:24.52#ibcon#about to read 5, iclass 5, count 0 2006.258.00:56:24.52#ibcon#read 5, iclass 5, count 0 2006.258.00:56:24.52#ibcon#about to read 6, iclass 5, count 0 2006.258.00:56:24.52#ibcon#read 6, iclass 5, count 0 2006.258.00:56:24.52#ibcon#end of sib2, iclass 5, count 0 2006.258.00:56:24.52#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:56:24.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:56:24.52#ibcon#[25=USB\r\n] 2006.258.00:56:24.52#ibcon#*before write, iclass 5, count 0 2006.258.00:56:24.52#ibcon#enter sib2, iclass 5, count 0 2006.258.00:56:24.52#ibcon#flushed, iclass 5, count 0 2006.258.00:56:24.52#ibcon#about to write, iclass 5, count 0 2006.258.00:56:24.52#ibcon#wrote, iclass 5, count 0 2006.258.00:56:24.52#ibcon#about to read 3, iclass 5, count 0 2006.258.00:56:24.55#ibcon#read 3, iclass 5, count 0 2006.258.00:56:24.55#ibcon#about to read 4, iclass 5, count 0 2006.258.00:56:24.55#ibcon#read 4, iclass 5, count 0 2006.258.00:56:24.55#ibcon#about to read 5, iclass 5, count 0 2006.258.00:56:24.55#ibcon#read 5, iclass 5, count 0 2006.258.00:56:24.55#ibcon#about to read 6, iclass 5, count 0 2006.258.00:56:24.55#ibcon#read 6, iclass 5, count 0 2006.258.00:56:24.55#ibcon#end of sib2, iclass 5, count 0 2006.258.00:56:24.55#ibcon#*after write, iclass 5, count 0 2006.258.00:56:24.55#ibcon#*before return 0, iclass 5, count 0 2006.258.00:56:24.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:24.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:24.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:56:24.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:56:24.55$vck44/valo=5,734.99 2006.258.00:56:24.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.00:56:24.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.00:56:24.55#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:24.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:24.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:24.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:24.55#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:56:24.55#ibcon#first serial, iclass 7, count 0 2006.258.00:56:24.55#ibcon#enter sib2, iclass 7, count 0 2006.258.00:56:24.55#ibcon#flushed, iclass 7, count 0 2006.258.00:56:24.55#ibcon#about to write, iclass 7, count 0 2006.258.00:56:24.55#ibcon#wrote, iclass 7, count 0 2006.258.00:56:24.55#ibcon#about to read 3, iclass 7, count 0 2006.258.00:56:24.57#ibcon#read 3, iclass 7, count 0 2006.258.00:56:24.57#ibcon#about to read 4, iclass 7, count 0 2006.258.00:56:24.57#ibcon#read 4, iclass 7, count 0 2006.258.00:56:24.57#ibcon#about to read 5, iclass 7, count 0 2006.258.00:56:24.57#ibcon#read 5, iclass 7, count 0 2006.258.00:56:24.57#ibcon#about to read 6, iclass 7, count 0 2006.258.00:56:24.57#ibcon#read 6, iclass 7, count 0 2006.258.00:56:24.57#ibcon#end of sib2, iclass 7, count 0 2006.258.00:56:24.57#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:56:24.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:56:24.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.00:56:24.57#ibcon#*before write, iclass 7, count 0 2006.258.00:56:24.57#ibcon#enter sib2, iclass 7, count 0 2006.258.00:56:24.57#ibcon#flushed, iclass 7, count 0 2006.258.00:56:24.57#ibcon#about to write, iclass 7, count 0 2006.258.00:56:24.57#ibcon#wrote, iclass 7, count 0 2006.258.00:56:24.57#ibcon#about to read 3, iclass 7, count 0 2006.258.00:56:24.61#ibcon#read 3, iclass 7, count 0 2006.258.00:56:24.61#ibcon#about to read 4, iclass 7, count 0 2006.258.00:56:24.61#ibcon#read 4, iclass 7, count 0 2006.258.00:56:24.61#ibcon#about to read 5, iclass 7, count 0 2006.258.00:56:24.61#ibcon#read 5, iclass 7, count 0 2006.258.00:56:24.61#ibcon#about to read 6, iclass 7, count 0 2006.258.00:56:24.61#ibcon#read 6, iclass 7, count 0 2006.258.00:56:24.61#ibcon#end of sib2, iclass 7, count 0 2006.258.00:56:24.61#ibcon#*after write, iclass 7, count 0 2006.258.00:56:24.61#ibcon#*before return 0, iclass 7, count 0 2006.258.00:56:24.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:24.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:24.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:56:24.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:56:24.61$vck44/va=5,4 2006.258.00:56:24.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.00:56:24.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.00:56:24.61#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:24.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:24.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:24.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:24.67#ibcon#enter wrdev, iclass 11, count 2 2006.258.00:56:24.67#ibcon#first serial, iclass 11, count 2 2006.258.00:56:24.67#ibcon#enter sib2, iclass 11, count 2 2006.258.00:56:24.67#ibcon#flushed, iclass 11, count 2 2006.258.00:56:24.67#ibcon#about to write, iclass 11, count 2 2006.258.00:56:24.67#ibcon#wrote, iclass 11, count 2 2006.258.00:56:24.67#ibcon#about to read 3, iclass 11, count 2 2006.258.00:56:24.69#ibcon#read 3, iclass 11, count 2 2006.258.00:56:24.69#ibcon#about to read 4, iclass 11, count 2 2006.258.00:56:24.69#ibcon#read 4, iclass 11, count 2 2006.258.00:56:24.69#ibcon#about to read 5, iclass 11, count 2 2006.258.00:56:24.69#ibcon#read 5, iclass 11, count 2 2006.258.00:56:24.69#ibcon#about to read 6, iclass 11, count 2 2006.258.00:56:24.69#ibcon#read 6, iclass 11, count 2 2006.258.00:56:24.69#ibcon#end of sib2, iclass 11, count 2 2006.258.00:56:24.69#ibcon#*mode == 0, iclass 11, count 2 2006.258.00:56:24.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.00:56:24.69#ibcon#[25=AT05-04\r\n] 2006.258.00:56:24.69#ibcon#*before write, iclass 11, count 2 2006.258.00:56:24.69#ibcon#enter sib2, iclass 11, count 2 2006.258.00:56:24.69#ibcon#flushed, iclass 11, count 2 2006.258.00:56:24.69#ibcon#about to write, iclass 11, count 2 2006.258.00:56:24.69#ibcon#wrote, iclass 11, count 2 2006.258.00:56:24.69#ibcon#about to read 3, iclass 11, count 2 2006.258.00:56:24.72#ibcon#read 3, iclass 11, count 2 2006.258.00:56:24.72#ibcon#about to read 4, iclass 11, count 2 2006.258.00:56:24.72#ibcon#read 4, iclass 11, count 2 2006.258.00:56:24.72#ibcon#about to read 5, iclass 11, count 2 2006.258.00:56:24.72#ibcon#read 5, iclass 11, count 2 2006.258.00:56:24.72#ibcon#about to read 6, iclass 11, count 2 2006.258.00:56:24.72#ibcon#read 6, iclass 11, count 2 2006.258.00:56:24.72#ibcon#end of sib2, iclass 11, count 2 2006.258.00:56:24.72#ibcon#*after write, iclass 11, count 2 2006.258.00:56:24.72#ibcon#*before return 0, iclass 11, count 2 2006.258.00:56:24.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:24.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:24.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.00:56:24.72#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:24.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:24.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:24.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:24.84#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:56:24.84#ibcon#first serial, iclass 11, count 0 2006.258.00:56:24.84#ibcon#enter sib2, iclass 11, count 0 2006.258.00:56:24.84#ibcon#flushed, iclass 11, count 0 2006.258.00:56:24.84#ibcon#about to write, iclass 11, count 0 2006.258.00:56:24.84#ibcon#wrote, iclass 11, count 0 2006.258.00:56:24.84#ibcon#about to read 3, iclass 11, count 0 2006.258.00:56:24.86#ibcon#read 3, iclass 11, count 0 2006.258.00:56:24.86#ibcon#about to read 4, iclass 11, count 0 2006.258.00:56:24.86#ibcon#read 4, iclass 11, count 0 2006.258.00:56:24.86#ibcon#about to read 5, iclass 11, count 0 2006.258.00:56:24.86#ibcon#read 5, iclass 11, count 0 2006.258.00:56:24.86#ibcon#about to read 6, iclass 11, count 0 2006.258.00:56:24.86#ibcon#read 6, iclass 11, count 0 2006.258.00:56:24.86#ibcon#end of sib2, iclass 11, count 0 2006.258.00:56:24.86#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:56:24.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:56:24.86#ibcon#[25=USB\r\n] 2006.258.00:56:24.86#ibcon#*before write, iclass 11, count 0 2006.258.00:56:24.86#ibcon#enter sib2, iclass 11, count 0 2006.258.00:56:24.86#ibcon#flushed, iclass 11, count 0 2006.258.00:56:24.86#ibcon#about to write, iclass 11, count 0 2006.258.00:56:24.86#ibcon#wrote, iclass 11, count 0 2006.258.00:56:24.86#ibcon#about to read 3, iclass 11, count 0 2006.258.00:56:24.89#ibcon#read 3, iclass 11, count 0 2006.258.00:56:24.89#ibcon#about to read 4, iclass 11, count 0 2006.258.00:56:24.89#ibcon#read 4, iclass 11, count 0 2006.258.00:56:24.89#ibcon#about to read 5, iclass 11, count 0 2006.258.00:56:24.89#ibcon#read 5, iclass 11, count 0 2006.258.00:56:24.89#ibcon#about to read 6, iclass 11, count 0 2006.258.00:56:24.89#ibcon#read 6, iclass 11, count 0 2006.258.00:56:24.89#ibcon#end of sib2, iclass 11, count 0 2006.258.00:56:24.89#ibcon#*after write, iclass 11, count 0 2006.258.00:56:24.89#ibcon#*before return 0, iclass 11, count 0 2006.258.00:56:24.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:24.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:24.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:56:24.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:56:24.89$vck44/valo=6,814.99 2006.258.00:56:24.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.258.00:56:24.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.258.00:56:24.89#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:24.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:24.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:24.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:24.89#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:56:24.89#ibcon#first serial, iclass 13, count 0 2006.258.00:56:24.89#ibcon#enter sib2, iclass 13, count 0 2006.258.00:56:24.89#ibcon#flushed, iclass 13, count 0 2006.258.00:56:24.89#ibcon#about to write, iclass 13, count 0 2006.258.00:56:24.89#ibcon#wrote, iclass 13, count 0 2006.258.00:56:24.89#ibcon#about to read 3, iclass 13, count 0 2006.258.00:56:24.91#ibcon#read 3, iclass 13, count 0 2006.258.00:56:24.91#ibcon#about to read 4, iclass 13, count 0 2006.258.00:56:24.91#ibcon#read 4, iclass 13, count 0 2006.258.00:56:24.91#ibcon#about to read 5, iclass 13, count 0 2006.258.00:56:24.91#ibcon#read 5, iclass 13, count 0 2006.258.00:56:24.91#ibcon#about to read 6, iclass 13, count 0 2006.258.00:56:24.91#ibcon#read 6, iclass 13, count 0 2006.258.00:56:24.91#ibcon#end of sib2, iclass 13, count 0 2006.258.00:56:24.91#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:56:24.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:56:24.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.00:56:24.91#ibcon#*before write, iclass 13, count 0 2006.258.00:56:24.91#ibcon#enter sib2, iclass 13, count 0 2006.258.00:56:24.91#ibcon#flushed, iclass 13, count 0 2006.258.00:56:24.91#ibcon#about to write, iclass 13, count 0 2006.258.00:56:24.91#ibcon#wrote, iclass 13, count 0 2006.258.00:56:24.91#ibcon#about to read 3, iclass 13, count 0 2006.258.00:56:24.95#ibcon#read 3, iclass 13, count 0 2006.258.00:56:24.95#ibcon#about to read 4, iclass 13, count 0 2006.258.00:56:24.95#ibcon#read 4, iclass 13, count 0 2006.258.00:56:24.95#ibcon#about to read 5, iclass 13, count 0 2006.258.00:56:24.95#ibcon#read 5, iclass 13, count 0 2006.258.00:56:24.95#ibcon#about to read 6, iclass 13, count 0 2006.258.00:56:24.95#ibcon#read 6, iclass 13, count 0 2006.258.00:56:24.95#ibcon#end of sib2, iclass 13, count 0 2006.258.00:56:24.95#ibcon#*after write, iclass 13, count 0 2006.258.00:56:24.95#ibcon#*before return 0, iclass 13, count 0 2006.258.00:56:24.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:24.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:24.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:56:24.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:56:24.95$vck44/va=6,4 2006.258.00:56:24.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.258.00:56:24.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.258.00:56:24.95#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:24.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:25.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:25.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:25.01#ibcon#enter wrdev, iclass 15, count 2 2006.258.00:56:25.01#ibcon#first serial, iclass 15, count 2 2006.258.00:56:25.01#ibcon#enter sib2, iclass 15, count 2 2006.258.00:56:25.01#ibcon#flushed, iclass 15, count 2 2006.258.00:56:25.01#ibcon#about to write, iclass 15, count 2 2006.258.00:56:25.01#ibcon#wrote, iclass 15, count 2 2006.258.00:56:25.01#ibcon#about to read 3, iclass 15, count 2 2006.258.00:56:25.03#ibcon#read 3, iclass 15, count 2 2006.258.00:56:25.03#ibcon#about to read 4, iclass 15, count 2 2006.258.00:56:25.03#ibcon#read 4, iclass 15, count 2 2006.258.00:56:25.03#ibcon#about to read 5, iclass 15, count 2 2006.258.00:56:25.03#ibcon#read 5, iclass 15, count 2 2006.258.00:56:25.03#ibcon#about to read 6, iclass 15, count 2 2006.258.00:56:25.03#ibcon#read 6, iclass 15, count 2 2006.258.00:56:25.03#ibcon#end of sib2, iclass 15, count 2 2006.258.00:56:25.03#ibcon#*mode == 0, iclass 15, count 2 2006.258.00:56:25.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.258.00:56:25.03#ibcon#[25=AT06-04\r\n] 2006.258.00:56:25.03#ibcon#*before write, iclass 15, count 2 2006.258.00:56:25.03#ibcon#enter sib2, iclass 15, count 2 2006.258.00:56:25.03#ibcon#flushed, iclass 15, count 2 2006.258.00:56:25.03#ibcon#about to write, iclass 15, count 2 2006.258.00:56:25.03#ibcon#wrote, iclass 15, count 2 2006.258.00:56:25.03#ibcon#about to read 3, iclass 15, count 2 2006.258.00:56:25.06#ibcon#read 3, iclass 15, count 2 2006.258.00:56:25.06#ibcon#about to read 4, iclass 15, count 2 2006.258.00:56:25.06#ibcon#read 4, iclass 15, count 2 2006.258.00:56:25.06#ibcon#about to read 5, iclass 15, count 2 2006.258.00:56:25.06#ibcon#read 5, iclass 15, count 2 2006.258.00:56:25.06#ibcon#about to read 6, iclass 15, count 2 2006.258.00:56:25.06#ibcon#read 6, iclass 15, count 2 2006.258.00:56:25.06#ibcon#end of sib2, iclass 15, count 2 2006.258.00:56:25.06#ibcon#*after write, iclass 15, count 2 2006.258.00:56:25.06#ibcon#*before return 0, iclass 15, count 2 2006.258.00:56:25.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:25.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:25.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.258.00:56:25.06#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:25.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:25.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:25.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:25.18#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:56:25.18#ibcon#first serial, iclass 15, count 0 2006.258.00:56:25.18#ibcon#enter sib2, iclass 15, count 0 2006.258.00:56:25.18#ibcon#flushed, iclass 15, count 0 2006.258.00:56:25.18#ibcon#about to write, iclass 15, count 0 2006.258.00:56:25.18#ibcon#wrote, iclass 15, count 0 2006.258.00:56:25.18#ibcon#about to read 3, iclass 15, count 0 2006.258.00:56:25.20#ibcon#read 3, iclass 15, count 0 2006.258.00:56:25.20#ibcon#about to read 4, iclass 15, count 0 2006.258.00:56:25.20#ibcon#read 4, iclass 15, count 0 2006.258.00:56:25.20#ibcon#about to read 5, iclass 15, count 0 2006.258.00:56:25.20#ibcon#read 5, iclass 15, count 0 2006.258.00:56:25.20#ibcon#about to read 6, iclass 15, count 0 2006.258.00:56:25.20#ibcon#read 6, iclass 15, count 0 2006.258.00:56:25.20#ibcon#end of sib2, iclass 15, count 0 2006.258.00:56:25.20#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:56:25.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:56:25.20#ibcon#[25=USB\r\n] 2006.258.00:56:25.20#ibcon#*before write, iclass 15, count 0 2006.258.00:56:25.20#ibcon#enter sib2, iclass 15, count 0 2006.258.00:56:25.20#ibcon#flushed, iclass 15, count 0 2006.258.00:56:25.20#ibcon#about to write, iclass 15, count 0 2006.258.00:56:25.20#ibcon#wrote, iclass 15, count 0 2006.258.00:56:25.20#ibcon#about to read 3, iclass 15, count 0 2006.258.00:56:25.23#ibcon#read 3, iclass 15, count 0 2006.258.00:56:25.23#ibcon#about to read 4, iclass 15, count 0 2006.258.00:56:25.23#ibcon#read 4, iclass 15, count 0 2006.258.00:56:25.23#ibcon#about to read 5, iclass 15, count 0 2006.258.00:56:25.23#ibcon#read 5, iclass 15, count 0 2006.258.00:56:25.23#ibcon#about to read 6, iclass 15, count 0 2006.258.00:56:25.23#ibcon#read 6, iclass 15, count 0 2006.258.00:56:25.23#ibcon#end of sib2, iclass 15, count 0 2006.258.00:56:25.23#ibcon#*after write, iclass 15, count 0 2006.258.00:56:25.23#ibcon#*before return 0, iclass 15, count 0 2006.258.00:56:25.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:25.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:25.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:56:25.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:56:25.23$vck44/valo=7,864.99 2006.258.00:56:25.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.258.00:56:25.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.258.00:56:25.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:25.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:56:25.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:56:25.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:56:25.23#ibcon#enter wrdev, iclass 17, count 0 2006.258.00:56:25.23#ibcon#first serial, iclass 17, count 0 2006.258.00:56:25.23#ibcon#enter sib2, iclass 17, count 0 2006.258.00:56:25.23#ibcon#flushed, iclass 17, count 0 2006.258.00:56:25.23#ibcon#about to write, iclass 17, count 0 2006.258.00:56:25.23#ibcon#wrote, iclass 17, count 0 2006.258.00:56:25.23#ibcon#about to read 3, iclass 17, count 0 2006.258.00:56:25.25#ibcon#read 3, iclass 17, count 0 2006.258.00:56:25.25#ibcon#about to read 4, iclass 17, count 0 2006.258.00:56:25.25#ibcon#read 4, iclass 17, count 0 2006.258.00:56:25.25#ibcon#about to read 5, iclass 17, count 0 2006.258.00:56:25.25#ibcon#read 5, iclass 17, count 0 2006.258.00:56:25.25#ibcon#about to read 6, iclass 17, count 0 2006.258.00:56:25.25#ibcon#read 6, iclass 17, count 0 2006.258.00:56:25.25#ibcon#end of sib2, iclass 17, count 0 2006.258.00:56:25.25#ibcon#*mode == 0, iclass 17, count 0 2006.258.00:56:25.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.00:56:25.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.00:56:25.25#ibcon#*before write, iclass 17, count 0 2006.258.00:56:25.25#ibcon#enter sib2, iclass 17, count 0 2006.258.00:56:25.25#ibcon#flushed, iclass 17, count 0 2006.258.00:56:25.25#ibcon#about to write, iclass 17, count 0 2006.258.00:56:25.25#ibcon#wrote, iclass 17, count 0 2006.258.00:56:25.25#ibcon#about to read 3, iclass 17, count 0 2006.258.00:56:25.29#ibcon#read 3, iclass 17, count 0 2006.258.00:56:25.29#ibcon#about to read 4, iclass 17, count 0 2006.258.00:56:25.29#ibcon#read 4, iclass 17, count 0 2006.258.00:56:25.29#ibcon#about to read 5, iclass 17, count 0 2006.258.00:56:25.29#ibcon#read 5, iclass 17, count 0 2006.258.00:56:25.29#ibcon#about to read 6, iclass 17, count 0 2006.258.00:56:25.29#ibcon#read 6, iclass 17, count 0 2006.258.00:56:25.29#ibcon#end of sib2, iclass 17, count 0 2006.258.00:56:25.29#ibcon#*after write, iclass 17, count 0 2006.258.00:56:25.29#ibcon#*before return 0, iclass 17, count 0 2006.258.00:56:25.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:56:25.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.258.00:56:25.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.00:56:25.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.00:56:25.29$vck44/va=7,4 2006.258.00:56:25.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.258.00:56:25.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.258.00:56:25.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:25.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:56:25.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:56:25.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:56:25.35#ibcon#enter wrdev, iclass 19, count 2 2006.258.00:56:25.35#ibcon#first serial, iclass 19, count 2 2006.258.00:56:25.35#ibcon#enter sib2, iclass 19, count 2 2006.258.00:56:25.35#ibcon#flushed, iclass 19, count 2 2006.258.00:56:25.35#ibcon#about to write, iclass 19, count 2 2006.258.00:56:25.35#ibcon#wrote, iclass 19, count 2 2006.258.00:56:25.35#ibcon#about to read 3, iclass 19, count 2 2006.258.00:56:25.37#ibcon#read 3, iclass 19, count 2 2006.258.00:56:25.37#ibcon#about to read 4, iclass 19, count 2 2006.258.00:56:25.37#ibcon#read 4, iclass 19, count 2 2006.258.00:56:25.37#ibcon#about to read 5, iclass 19, count 2 2006.258.00:56:25.37#ibcon#read 5, iclass 19, count 2 2006.258.00:56:25.37#ibcon#about to read 6, iclass 19, count 2 2006.258.00:56:25.37#ibcon#read 6, iclass 19, count 2 2006.258.00:56:25.37#ibcon#end of sib2, iclass 19, count 2 2006.258.00:56:25.37#ibcon#*mode == 0, iclass 19, count 2 2006.258.00:56:25.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.258.00:56:25.37#ibcon#[25=AT07-04\r\n] 2006.258.00:56:25.37#ibcon#*before write, iclass 19, count 2 2006.258.00:56:25.37#ibcon#enter sib2, iclass 19, count 2 2006.258.00:56:25.37#ibcon#flushed, iclass 19, count 2 2006.258.00:56:25.37#ibcon#about to write, iclass 19, count 2 2006.258.00:56:25.37#ibcon#wrote, iclass 19, count 2 2006.258.00:56:25.37#ibcon#about to read 3, iclass 19, count 2 2006.258.00:56:25.40#ibcon#read 3, iclass 19, count 2 2006.258.00:56:25.40#ibcon#about to read 4, iclass 19, count 2 2006.258.00:56:25.40#ibcon#read 4, iclass 19, count 2 2006.258.00:56:25.40#ibcon#about to read 5, iclass 19, count 2 2006.258.00:56:25.40#ibcon#read 5, iclass 19, count 2 2006.258.00:56:25.40#ibcon#about to read 6, iclass 19, count 2 2006.258.00:56:25.40#ibcon#read 6, iclass 19, count 2 2006.258.00:56:25.40#ibcon#end of sib2, iclass 19, count 2 2006.258.00:56:25.40#ibcon#*after write, iclass 19, count 2 2006.258.00:56:25.40#ibcon#*before return 0, iclass 19, count 2 2006.258.00:56:25.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:56:25.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.258.00:56:25.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.258.00:56:25.40#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:25.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:56:25.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:56:25.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:56:25.52#ibcon#enter wrdev, iclass 19, count 0 2006.258.00:56:25.52#ibcon#first serial, iclass 19, count 0 2006.258.00:56:25.52#ibcon#enter sib2, iclass 19, count 0 2006.258.00:56:25.52#ibcon#flushed, iclass 19, count 0 2006.258.00:56:25.52#ibcon#about to write, iclass 19, count 0 2006.258.00:56:25.52#ibcon#wrote, iclass 19, count 0 2006.258.00:56:25.52#ibcon#about to read 3, iclass 19, count 0 2006.258.00:56:25.54#ibcon#read 3, iclass 19, count 0 2006.258.00:56:25.54#ibcon#about to read 4, iclass 19, count 0 2006.258.00:56:25.54#ibcon#read 4, iclass 19, count 0 2006.258.00:56:25.54#ibcon#about to read 5, iclass 19, count 0 2006.258.00:56:25.54#ibcon#read 5, iclass 19, count 0 2006.258.00:56:25.54#ibcon#about to read 6, iclass 19, count 0 2006.258.00:56:25.54#ibcon#read 6, iclass 19, count 0 2006.258.00:56:25.54#ibcon#end of sib2, iclass 19, count 0 2006.258.00:56:25.54#ibcon#*mode == 0, iclass 19, count 0 2006.258.00:56:25.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.00:56:25.54#ibcon#[25=USB\r\n] 2006.258.00:56:25.54#ibcon#*before write, iclass 19, count 0 2006.258.00:56:25.54#ibcon#enter sib2, iclass 19, count 0 2006.258.00:56:25.54#ibcon#flushed, iclass 19, count 0 2006.258.00:56:25.54#ibcon#about to write, iclass 19, count 0 2006.258.00:56:25.54#ibcon#wrote, iclass 19, count 0 2006.258.00:56:25.54#ibcon#about to read 3, iclass 19, count 0 2006.258.00:56:25.57#ibcon#read 3, iclass 19, count 0 2006.258.00:56:25.57#ibcon#about to read 4, iclass 19, count 0 2006.258.00:56:25.57#ibcon#read 4, iclass 19, count 0 2006.258.00:56:25.57#ibcon#about to read 5, iclass 19, count 0 2006.258.00:56:25.57#ibcon#read 5, iclass 19, count 0 2006.258.00:56:25.57#ibcon#about to read 6, iclass 19, count 0 2006.258.00:56:25.57#ibcon#read 6, iclass 19, count 0 2006.258.00:56:25.57#ibcon#end of sib2, iclass 19, count 0 2006.258.00:56:25.57#ibcon#*after write, iclass 19, count 0 2006.258.00:56:25.57#ibcon#*before return 0, iclass 19, count 0 2006.258.00:56:25.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:56:25.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.258.00:56:25.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.00:56:25.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.00:56:25.57$vck44/valo=8,884.99 2006.258.00:56:25.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.258.00:56:25.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.258.00:56:25.57#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:25.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:56:25.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:56:25.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:56:25.57#ibcon#enter wrdev, iclass 21, count 0 2006.258.00:56:25.57#ibcon#first serial, iclass 21, count 0 2006.258.00:56:25.57#ibcon#enter sib2, iclass 21, count 0 2006.258.00:56:25.57#ibcon#flushed, iclass 21, count 0 2006.258.00:56:25.57#ibcon#about to write, iclass 21, count 0 2006.258.00:56:25.57#ibcon#wrote, iclass 21, count 0 2006.258.00:56:25.57#ibcon#about to read 3, iclass 21, count 0 2006.258.00:56:25.59#ibcon#read 3, iclass 21, count 0 2006.258.00:56:25.59#ibcon#about to read 4, iclass 21, count 0 2006.258.00:56:25.59#ibcon#read 4, iclass 21, count 0 2006.258.00:56:25.59#ibcon#about to read 5, iclass 21, count 0 2006.258.00:56:25.59#ibcon#read 5, iclass 21, count 0 2006.258.00:56:25.59#ibcon#about to read 6, iclass 21, count 0 2006.258.00:56:25.59#ibcon#read 6, iclass 21, count 0 2006.258.00:56:25.59#ibcon#end of sib2, iclass 21, count 0 2006.258.00:56:25.59#ibcon#*mode == 0, iclass 21, count 0 2006.258.00:56:25.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.00:56:25.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.00:56:25.59#ibcon#*before write, iclass 21, count 0 2006.258.00:56:25.59#ibcon#enter sib2, iclass 21, count 0 2006.258.00:56:25.59#ibcon#flushed, iclass 21, count 0 2006.258.00:56:25.59#ibcon#about to write, iclass 21, count 0 2006.258.00:56:25.59#ibcon#wrote, iclass 21, count 0 2006.258.00:56:25.59#ibcon#about to read 3, iclass 21, count 0 2006.258.00:56:25.63#ibcon#read 3, iclass 21, count 0 2006.258.00:56:25.63#ibcon#about to read 4, iclass 21, count 0 2006.258.00:56:25.63#ibcon#read 4, iclass 21, count 0 2006.258.00:56:25.63#ibcon#about to read 5, iclass 21, count 0 2006.258.00:56:25.63#ibcon#read 5, iclass 21, count 0 2006.258.00:56:25.63#ibcon#about to read 6, iclass 21, count 0 2006.258.00:56:25.63#ibcon#read 6, iclass 21, count 0 2006.258.00:56:25.63#ibcon#end of sib2, iclass 21, count 0 2006.258.00:56:25.63#ibcon#*after write, iclass 21, count 0 2006.258.00:56:25.63#ibcon#*before return 0, iclass 21, count 0 2006.258.00:56:25.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:56:25.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.258.00:56:25.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.00:56:25.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.00:56:25.63$vck44/va=8,4 2006.258.00:56:25.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.258.00:56:25.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.258.00:56:25.63#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:25.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:56:25.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:56:25.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:56:25.69#ibcon#enter wrdev, iclass 23, count 2 2006.258.00:56:25.69#ibcon#first serial, iclass 23, count 2 2006.258.00:56:25.69#ibcon#enter sib2, iclass 23, count 2 2006.258.00:56:25.69#ibcon#flushed, iclass 23, count 2 2006.258.00:56:25.69#ibcon#about to write, iclass 23, count 2 2006.258.00:56:25.69#ibcon#wrote, iclass 23, count 2 2006.258.00:56:25.69#ibcon#about to read 3, iclass 23, count 2 2006.258.00:56:25.71#ibcon#read 3, iclass 23, count 2 2006.258.00:56:25.71#ibcon#about to read 4, iclass 23, count 2 2006.258.00:56:25.71#ibcon#read 4, iclass 23, count 2 2006.258.00:56:25.71#ibcon#about to read 5, iclass 23, count 2 2006.258.00:56:25.71#ibcon#read 5, iclass 23, count 2 2006.258.00:56:25.71#ibcon#about to read 6, iclass 23, count 2 2006.258.00:56:25.71#ibcon#read 6, iclass 23, count 2 2006.258.00:56:25.71#ibcon#end of sib2, iclass 23, count 2 2006.258.00:56:25.71#ibcon#*mode == 0, iclass 23, count 2 2006.258.00:56:25.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.258.00:56:25.71#ibcon#[25=AT08-04\r\n] 2006.258.00:56:25.71#ibcon#*before write, iclass 23, count 2 2006.258.00:56:25.71#ibcon#enter sib2, iclass 23, count 2 2006.258.00:56:25.71#ibcon#flushed, iclass 23, count 2 2006.258.00:56:25.71#ibcon#about to write, iclass 23, count 2 2006.258.00:56:25.71#ibcon#wrote, iclass 23, count 2 2006.258.00:56:25.71#ibcon#about to read 3, iclass 23, count 2 2006.258.00:56:25.74#ibcon#read 3, iclass 23, count 2 2006.258.00:56:25.74#ibcon#about to read 4, iclass 23, count 2 2006.258.00:56:25.74#ibcon#read 4, iclass 23, count 2 2006.258.00:56:25.74#ibcon#about to read 5, iclass 23, count 2 2006.258.00:56:25.74#ibcon#read 5, iclass 23, count 2 2006.258.00:56:25.74#ibcon#about to read 6, iclass 23, count 2 2006.258.00:56:25.74#ibcon#read 6, iclass 23, count 2 2006.258.00:56:25.74#ibcon#end of sib2, iclass 23, count 2 2006.258.00:56:25.74#ibcon#*after write, iclass 23, count 2 2006.258.00:56:25.74#ibcon#*before return 0, iclass 23, count 2 2006.258.00:56:25.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:56:25.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.258.00:56:25.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.258.00:56:25.74#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:25.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:56:25.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:56:25.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:56:25.86#ibcon#enter wrdev, iclass 23, count 0 2006.258.00:56:25.86#ibcon#first serial, iclass 23, count 0 2006.258.00:56:25.86#ibcon#enter sib2, iclass 23, count 0 2006.258.00:56:25.86#ibcon#flushed, iclass 23, count 0 2006.258.00:56:25.86#ibcon#about to write, iclass 23, count 0 2006.258.00:56:25.86#ibcon#wrote, iclass 23, count 0 2006.258.00:56:25.86#ibcon#about to read 3, iclass 23, count 0 2006.258.00:56:25.88#ibcon#read 3, iclass 23, count 0 2006.258.00:56:25.88#ibcon#about to read 4, iclass 23, count 0 2006.258.00:56:25.88#ibcon#read 4, iclass 23, count 0 2006.258.00:56:25.88#ibcon#about to read 5, iclass 23, count 0 2006.258.00:56:25.88#ibcon#read 5, iclass 23, count 0 2006.258.00:56:25.88#ibcon#about to read 6, iclass 23, count 0 2006.258.00:56:25.88#ibcon#read 6, iclass 23, count 0 2006.258.00:56:25.88#ibcon#end of sib2, iclass 23, count 0 2006.258.00:56:25.88#ibcon#*mode == 0, iclass 23, count 0 2006.258.00:56:25.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.00:56:25.88#ibcon#[25=USB\r\n] 2006.258.00:56:25.88#ibcon#*before write, iclass 23, count 0 2006.258.00:56:25.88#ibcon#enter sib2, iclass 23, count 0 2006.258.00:56:25.88#ibcon#flushed, iclass 23, count 0 2006.258.00:56:25.88#ibcon#about to write, iclass 23, count 0 2006.258.00:56:25.88#ibcon#wrote, iclass 23, count 0 2006.258.00:56:25.88#ibcon#about to read 3, iclass 23, count 0 2006.258.00:56:25.91#ibcon#read 3, iclass 23, count 0 2006.258.00:56:25.91#ibcon#about to read 4, iclass 23, count 0 2006.258.00:56:25.91#ibcon#read 4, iclass 23, count 0 2006.258.00:56:25.91#ibcon#about to read 5, iclass 23, count 0 2006.258.00:56:25.91#ibcon#read 5, iclass 23, count 0 2006.258.00:56:25.91#ibcon#about to read 6, iclass 23, count 0 2006.258.00:56:25.91#ibcon#read 6, iclass 23, count 0 2006.258.00:56:25.91#ibcon#end of sib2, iclass 23, count 0 2006.258.00:56:25.91#ibcon#*after write, iclass 23, count 0 2006.258.00:56:25.91#ibcon#*before return 0, iclass 23, count 0 2006.258.00:56:25.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:56:25.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.258.00:56:25.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.00:56:25.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.00:56:25.91$vck44/vblo=1,629.99 2006.258.00:56:25.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.00:56:25.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.00:56:25.91#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:25.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:25.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:25.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:25.91#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:56:25.91#ibcon#first serial, iclass 25, count 0 2006.258.00:56:25.91#ibcon#enter sib2, iclass 25, count 0 2006.258.00:56:25.91#ibcon#flushed, iclass 25, count 0 2006.258.00:56:25.91#ibcon#about to write, iclass 25, count 0 2006.258.00:56:25.91#ibcon#wrote, iclass 25, count 0 2006.258.00:56:25.91#ibcon#about to read 3, iclass 25, count 0 2006.258.00:56:25.93#ibcon#read 3, iclass 25, count 0 2006.258.00:56:25.93#ibcon#about to read 4, iclass 25, count 0 2006.258.00:56:25.93#ibcon#read 4, iclass 25, count 0 2006.258.00:56:25.93#ibcon#about to read 5, iclass 25, count 0 2006.258.00:56:25.93#ibcon#read 5, iclass 25, count 0 2006.258.00:56:25.93#ibcon#about to read 6, iclass 25, count 0 2006.258.00:56:25.93#ibcon#read 6, iclass 25, count 0 2006.258.00:56:25.93#ibcon#end of sib2, iclass 25, count 0 2006.258.00:56:25.93#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:56:25.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:56:25.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.00:56:25.93#ibcon#*before write, iclass 25, count 0 2006.258.00:56:25.93#ibcon#enter sib2, iclass 25, count 0 2006.258.00:56:25.93#ibcon#flushed, iclass 25, count 0 2006.258.00:56:25.93#ibcon#about to write, iclass 25, count 0 2006.258.00:56:25.93#ibcon#wrote, iclass 25, count 0 2006.258.00:56:25.93#ibcon#about to read 3, iclass 25, count 0 2006.258.00:56:25.97#ibcon#read 3, iclass 25, count 0 2006.258.00:56:25.97#ibcon#about to read 4, iclass 25, count 0 2006.258.00:56:25.97#ibcon#read 4, iclass 25, count 0 2006.258.00:56:25.97#ibcon#about to read 5, iclass 25, count 0 2006.258.00:56:25.97#ibcon#read 5, iclass 25, count 0 2006.258.00:56:25.97#ibcon#about to read 6, iclass 25, count 0 2006.258.00:56:25.97#ibcon#read 6, iclass 25, count 0 2006.258.00:56:25.97#ibcon#end of sib2, iclass 25, count 0 2006.258.00:56:25.97#ibcon#*after write, iclass 25, count 0 2006.258.00:56:25.97#ibcon#*before return 0, iclass 25, count 0 2006.258.00:56:25.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:25.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:25.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:56:25.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:56:25.97$vck44/vb=1,4 2006.258.00:56:25.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.258.00:56:25.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.258.00:56:25.97#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:25.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:56:25.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:56:25.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:56:25.97#ibcon#enter wrdev, iclass 27, count 2 2006.258.00:56:25.97#ibcon#first serial, iclass 27, count 2 2006.258.00:56:25.97#ibcon#enter sib2, iclass 27, count 2 2006.258.00:56:25.97#ibcon#flushed, iclass 27, count 2 2006.258.00:56:25.97#ibcon#about to write, iclass 27, count 2 2006.258.00:56:25.97#ibcon#wrote, iclass 27, count 2 2006.258.00:56:25.97#ibcon#about to read 3, iclass 27, count 2 2006.258.00:56:25.99#ibcon#read 3, iclass 27, count 2 2006.258.00:56:25.99#ibcon#about to read 4, iclass 27, count 2 2006.258.00:56:25.99#ibcon#read 4, iclass 27, count 2 2006.258.00:56:25.99#ibcon#about to read 5, iclass 27, count 2 2006.258.00:56:25.99#ibcon#read 5, iclass 27, count 2 2006.258.00:56:25.99#ibcon#about to read 6, iclass 27, count 2 2006.258.00:56:25.99#ibcon#read 6, iclass 27, count 2 2006.258.00:56:25.99#ibcon#end of sib2, iclass 27, count 2 2006.258.00:56:25.99#ibcon#*mode == 0, iclass 27, count 2 2006.258.00:56:25.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.258.00:56:25.99#ibcon#[27=AT01-04\r\n] 2006.258.00:56:25.99#ibcon#*before write, iclass 27, count 2 2006.258.00:56:25.99#ibcon#enter sib2, iclass 27, count 2 2006.258.00:56:25.99#ibcon#flushed, iclass 27, count 2 2006.258.00:56:25.99#ibcon#about to write, iclass 27, count 2 2006.258.00:56:25.99#ibcon#wrote, iclass 27, count 2 2006.258.00:56:25.99#ibcon#about to read 3, iclass 27, count 2 2006.258.00:56:26.02#ibcon#read 3, iclass 27, count 2 2006.258.00:56:26.02#ibcon#about to read 4, iclass 27, count 2 2006.258.00:56:26.02#ibcon#read 4, iclass 27, count 2 2006.258.00:56:26.02#ibcon#about to read 5, iclass 27, count 2 2006.258.00:56:26.02#ibcon#read 5, iclass 27, count 2 2006.258.00:56:26.02#ibcon#about to read 6, iclass 27, count 2 2006.258.00:56:26.02#ibcon#read 6, iclass 27, count 2 2006.258.00:56:26.02#ibcon#end of sib2, iclass 27, count 2 2006.258.00:56:26.02#ibcon#*after write, iclass 27, count 2 2006.258.00:56:26.02#ibcon#*before return 0, iclass 27, count 2 2006.258.00:56:26.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:56:26.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.258.00:56:26.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.258.00:56:26.02#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:26.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:56:26.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:56:26.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:56:26.14#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:56:26.14#ibcon#first serial, iclass 27, count 0 2006.258.00:56:26.14#ibcon#enter sib2, iclass 27, count 0 2006.258.00:56:26.14#ibcon#flushed, iclass 27, count 0 2006.258.00:56:26.14#ibcon#about to write, iclass 27, count 0 2006.258.00:56:26.14#ibcon#wrote, iclass 27, count 0 2006.258.00:56:26.14#ibcon#about to read 3, iclass 27, count 0 2006.258.00:56:26.16#ibcon#read 3, iclass 27, count 0 2006.258.00:56:26.16#ibcon#about to read 4, iclass 27, count 0 2006.258.00:56:26.16#ibcon#read 4, iclass 27, count 0 2006.258.00:56:26.16#ibcon#about to read 5, iclass 27, count 0 2006.258.00:56:26.16#ibcon#read 5, iclass 27, count 0 2006.258.00:56:26.16#ibcon#about to read 6, iclass 27, count 0 2006.258.00:56:26.16#ibcon#read 6, iclass 27, count 0 2006.258.00:56:26.16#ibcon#end of sib2, iclass 27, count 0 2006.258.00:56:26.16#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:56:26.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:56:26.16#ibcon#[27=USB\r\n] 2006.258.00:56:26.16#ibcon#*before write, iclass 27, count 0 2006.258.00:56:26.16#ibcon#enter sib2, iclass 27, count 0 2006.258.00:56:26.16#ibcon#flushed, iclass 27, count 0 2006.258.00:56:26.16#ibcon#about to write, iclass 27, count 0 2006.258.00:56:26.16#ibcon#wrote, iclass 27, count 0 2006.258.00:56:26.16#ibcon#about to read 3, iclass 27, count 0 2006.258.00:56:26.19#ibcon#read 3, iclass 27, count 0 2006.258.00:56:26.19#ibcon#about to read 4, iclass 27, count 0 2006.258.00:56:26.19#ibcon#read 4, iclass 27, count 0 2006.258.00:56:26.19#ibcon#about to read 5, iclass 27, count 0 2006.258.00:56:26.19#ibcon#read 5, iclass 27, count 0 2006.258.00:56:26.19#ibcon#about to read 6, iclass 27, count 0 2006.258.00:56:26.19#ibcon#read 6, iclass 27, count 0 2006.258.00:56:26.19#ibcon#end of sib2, iclass 27, count 0 2006.258.00:56:26.19#ibcon#*after write, iclass 27, count 0 2006.258.00:56:26.19#ibcon#*before return 0, iclass 27, count 0 2006.258.00:56:26.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:56:26.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.258.00:56:26.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:56:26.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:56:26.19$vck44/vblo=2,634.99 2006.258.00:56:26.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.00:56:26.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.00:56:26.19#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:26.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:26.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:26.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:26.19#ibcon#enter wrdev, iclass 29, count 0 2006.258.00:56:26.19#ibcon#first serial, iclass 29, count 0 2006.258.00:56:26.19#ibcon#enter sib2, iclass 29, count 0 2006.258.00:56:26.19#ibcon#flushed, iclass 29, count 0 2006.258.00:56:26.19#ibcon#about to write, iclass 29, count 0 2006.258.00:56:26.19#ibcon#wrote, iclass 29, count 0 2006.258.00:56:26.19#ibcon#about to read 3, iclass 29, count 0 2006.258.00:56:26.21#ibcon#read 3, iclass 29, count 0 2006.258.00:56:26.21#ibcon#about to read 4, iclass 29, count 0 2006.258.00:56:26.21#ibcon#read 4, iclass 29, count 0 2006.258.00:56:26.21#ibcon#about to read 5, iclass 29, count 0 2006.258.00:56:26.21#ibcon#read 5, iclass 29, count 0 2006.258.00:56:26.21#ibcon#about to read 6, iclass 29, count 0 2006.258.00:56:26.21#ibcon#read 6, iclass 29, count 0 2006.258.00:56:26.21#ibcon#end of sib2, iclass 29, count 0 2006.258.00:56:26.21#ibcon#*mode == 0, iclass 29, count 0 2006.258.00:56:26.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.00:56:26.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.00:56:26.21#ibcon#*before write, iclass 29, count 0 2006.258.00:56:26.21#ibcon#enter sib2, iclass 29, count 0 2006.258.00:56:26.21#ibcon#flushed, iclass 29, count 0 2006.258.00:56:26.21#ibcon#about to write, iclass 29, count 0 2006.258.00:56:26.21#ibcon#wrote, iclass 29, count 0 2006.258.00:56:26.21#ibcon#about to read 3, iclass 29, count 0 2006.258.00:56:26.25#ibcon#read 3, iclass 29, count 0 2006.258.00:56:26.25#ibcon#about to read 4, iclass 29, count 0 2006.258.00:56:26.25#ibcon#read 4, iclass 29, count 0 2006.258.00:56:26.25#ibcon#about to read 5, iclass 29, count 0 2006.258.00:56:26.25#ibcon#read 5, iclass 29, count 0 2006.258.00:56:26.25#ibcon#about to read 6, iclass 29, count 0 2006.258.00:56:26.25#ibcon#read 6, iclass 29, count 0 2006.258.00:56:26.25#ibcon#end of sib2, iclass 29, count 0 2006.258.00:56:26.25#ibcon#*after write, iclass 29, count 0 2006.258.00:56:26.25#ibcon#*before return 0, iclass 29, count 0 2006.258.00:56:26.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:26.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.00:56:26.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.00:56:26.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.00:56:26.25$vck44/vb=2,5 2006.258.00:56:26.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.00:56:26.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.00:56:26.25#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:26.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:26.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:26.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:26.31#ibcon#enter wrdev, iclass 31, count 2 2006.258.00:56:26.31#ibcon#first serial, iclass 31, count 2 2006.258.00:56:26.31#ibcon#enter sib2, iclass 31, count 2 2006.258.00:56:26.31#ibcon#flushed, iclass 31, count 2 2006.258.00:56:26.31#ibcon#about to write, iclass 31, count 2 2006.258.00:56:26.31#ibcon#wrote, iclass 31, count 2 2006.258.00:56:26.31#ibcon#about to read 3, iclass 31, count 2 2006.258.00:56:26.33#ibcon#read 3, iclass 31, count 2 2006.258.00:56:26.33#ibcon#about to read 4, iclass 31, count 2 2006.258.00:56:26.33#ibcon#read 4, iclass 31, count 2 2006.258.00:56:26.33#ibcon#about to read 5, iclass 31, count 2 2006.258.00:56:26.33#ibcon#read 5, iclass 31, count 2 2006.258.00:56:26.33#ibcon#about to read 6, iclass 31, count 2 2006.258.00:56:26.33#ibcon#read 6, iclass 31, count 2 2006.258.00:56:26.33#ibcon#end of sib2, iclass 31, count 2 2006.258.00:56:26.33#ibcon#*mode == 0, iclass 31, count 2 2006.258.00:56:26.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.00:56:26.33#ibcon#[27=AT02-05\r\n] 2006.258.00:56:26.33#ibcon#*before write, iclass 31, count 2 2006.258.00:56:26.33#ibcon#enter sib2, iclass 31, count 2 2006.258.00:56:26.33#ibcon#flushed, iclass 31, count 2 2006.258.00:56:26.33#ibcon#about to write, iclass 31, count 2 2006.258.00:56:26.33#ibcon#wrote, iclass 31, count 2 2006.258.00:56:26.33#ibcon#about to read 3, iclass 31, count 2 2006.258.00:56:26.36#ibcon#read 3, iclass 31, count 2 2006.258.00:56:26.36#ibcon#about to read 4, iclass 31, count 2 2006.258.00:56:26.36#ibcon#read 4, iclass 31, count 2 2006.258.00:56:26.36#ibcon#about to read 5, iclass 31, count 2 2006.258.00:56:26.36#ibcon#read 5, iclass 31, count 2 2006.258.00:56:26.36#ibcon#about to read 6, iclass 31, count 2 2006.258.00:56:26.36#ibcon#read 6, iclass 31, count 2 2006.258.00:56:26.36#ibcon#end of sib2, iclass 31, count 2 2006.258.00:56:26.36#ibcon#*after write, iclass 31, count 2 2006.258.00:56:26.36#ibcon#*before return 0, iclass 31, count 2 2006.258.00:56:26.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:26.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.00:56:26.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.00:56:26.36#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:26.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:26.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:26.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:26.48#ibcon#enter wrdev, iclass 31, count 0 2006.258.00:56:26.48#ibcon#first serial, iclass 31, count 0 2006.258.00:56:26.48#ibcon#enter sib2, iclass 31, count 0 2006.258.00:56:26.48#ibcon#flushed, iclass 31, count 0 2006.258.00:56:26.48#ibcon#about to write, iclass 31, count 0 2006.258.00:56:26.48#ibcon#wrote, iclass 31, count 0 2006.258.00:56:26.48#ibcon#about to read 3, iclass 31, count 0 2006.258.00:56:26.50#ibcon#read 3, iclass 31, count 0 2006.258.00:56:26.50#ibcon#about to read 4, iclass 31, count 0 2006.258.00:56:26.50#ibcon#read 4, iclass 31, count 0 2006.258.00:56:26.50#ibcon#about to read 5, iclass 31, count 0 2006.258.00:56:26.50#ibcon#read 5, iclass 31, count 0 2006.258.00:56:26.50#ibcon#about to read 6, iclass 31, count 0 2006.258.00:56:26.50#ibcon#read 6, iclass 31, count 0 2006.258.00:56:26.50#ibcon#end of sib2, iclass 31, count 0 2006.258.00:56:26.50#ibcon#*mode == 0, iclass 31, count 0 2006.258.00:56:26.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.00:56:26.50#ibcon#[27=USB\r\n] 2006.258.00:56:26.50#ibcon#*before write, iclass 31, count 0 2006.258.00:56:26.50#ibcon#enter sib2, iclass 31, count 0 2006.258.00:56:26.50#ibcon#flushed, iclass 31, count 0 2006.258.00:56:26.50#ibcon#about to write, iclass 31, count 0 2006.258.00:56:26.50#ibcon#wrote, iclass 31, count 0 2006.258.00:56:26.50#ibcon#about to read 3, iclass 31, count 0 2006.258.00:56:26.53#ibcon#read 3, iclass 31, count 0 2006.258.00:56:26.53#ibcon#about to read 4, iclass 31, count 0 2006.258.00:56:26.53#ibcon#read 4, iclass 31, count 0 2006.258.00:56:26.53#ibcon#about to read 5, iclass 31, count 0 2006.258.00:56:26.53#ibcon#read 5, iclass 31, count 0 2006.258.00:56:26.53#ibcon#about to read 6, iclass 31, count 0 2006.258.00:56:26.53#ibcon#read 6, iclass 31, count 0 2006.258.00:56:26.53#ibcon#end of sib2, iclass 31, count 0 2006.258.00:56:26.53#ibcon#*after write, iclass 31, count 0 2006.258.00:56:26.53#ibcon#*before return 0, iclass 31, count 0 2006.258.00:56:26.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:26.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.00:56:26.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.00:56:26.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.00:56:26.53$vck44/vblo=3,649.99 2006.258.00:56:26.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.00:56:26.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.00:56:26.53#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:26.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:26.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:26.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:26.53#ibcon#enter wrdev, iclass 33, count 0 2006.258.00:56:26.53#ibcon#first serial, iclass 33, count 0 2006.258.00:56:26.53#ibcon#enter sib2, iclass 33, count 0 2006.258.00:56:26.53#ibcon#flushed, iclass 33, count 0 2006.258.00:56:26.53#ibcon#about to write, iclass 33, count 0 2006.258.00:56:26.53#ibcon#wrote, iclass 33, count 0 2006.258.00:56:26.53#ibcon#about to read 3, iclass 33, count 0 2006.258.00:56:26.55#ibcon#read 3, iclass 33, count 0 2006.258.00:56:26.55#ibcon#about to read 4, iclass 33, count 0 2006.258.00:56:26.55#ibcon#read 4, iclass 33, count 0 2006.258.00:56:26.55#ibcon#about to read 5, iclass 33, count 0 2006.258.00:56:26.55#ibcon#read 5, iclass 33, count 0 2006.258.00:56:26.55#ibcon#about to read 6, iclass 33, count 0 2006.258.00:56:26.55#ibcon#read 6, iclass 33, count 0 2006.258.00:56:26.55#ibcon#end of sib2, iclass 33, count 0 2006.258.00:56:26.55#ibcon#*mode == 0, iclass 33, count 0 2006.258.00:56:26.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.00:56:26.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.00:56:26.55#ibcon#*before write, iclass 33, count 0 2006.258.00:56:26.55#ibcon#enter sib2, iclass 33, count 0 2006.258.00:56:26.55#ibcon#flushed, iclass 33, count 0 2006.258.00:56:26.55#ibcon#about to write, iclass 33, count 0 2006.258.00:56:26.55#ibcon#wrote, iclass 33, count 0 2006.258.00:56:26.55#ibcon#about to read 3, iclass 33, count 0 2006.258.00:56:26.59#ibcon#read 3, iclass 33, count 0 2006.258.00:56:26.59#ibcon#about to read 4, iclass 33, count 0 2006.258.00:56:26.59#ibcon#read 4, iclass 33, count 0 2006.258.00:56:26.59#ibcon#about to read 5, iclass 33, count 0 2006.258.00:56:26.59#ibcon#read 5, iclass 33, count 0 2006.258.00:56:26.60#ibcon#about to read 6, iclass 33, count 0 2006.258.00:56:26.60#ibcon#read 6, iclass 33, count 0 2006.258.00:56:26.60#ibcon#end of sib2, iclass 33, count 0 2006.258.00:56:26.60#ibcon#*after write, iclass 33, count 0 2006.258.00:56:26.60#ibcon#*before return 0, iclass 33, count 0 2006.258.00:56:26.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:26.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.00:56:26.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.00:56:26.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.00:56:26.60$vck44/vb=3,4 2006.258.00:56:26.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.00:56:26.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.00:56:26.60#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:26.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:26.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:26.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:26.65#ibcon#enter wrdev, iclass 35, count 2 2006.258.00:56:26.65#ibcon#first serial, iclass 35, count 2 2006.258.00:56:26.65#ibcon#enter sib2, iclass 35, count 2 2006.258.00:56:26.65#ibcon#flushed, iclass 35, count 2 2006.258.00:56:26.65#ibcon#about to write, iclass 35, count 2 2006.258.00:56:26.65#ibcon#wrote, iclass 35, count 2 2006.258.00:56:26.65#ibcon#about to read 3, iclass 35, count 2 2006.258.00:56:26.67#ibcon#read 3, iclass 35, count 2 2006.258.00:56:26.67#ibcon#about to read 4, iclass 35, count 2 2006.258.00:56:26.67#ibcon#read 4, iclass 35, count 2 2006.258.00:56:26.67#ibcon#about to read 5, iclass 35, count 2 2006.258.00:56:26.67#ibcon#read 5, iclass 35, count 2 2006.258.00:56:26.67#ibcon#about to read 6, iclass 35, count 2 2006.258.00:56:26.67#ibcon#read 6, iclass 35, count 2 2006.258.00:56:26.67#ibcon#end of sib2, iclass 35, count 2 2006.258.00:56:26.67#ibcon#*mode == 0, iclass 35, count 2 2006.258.00:56:26.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.00:56:26.67#ibcon#[27=AT03-04\r\n] 2006.258.00:56:26.67#ibcon#*before write, iclass 35, count 2 2006.258.00:56:26.67#ibcon#enter sib2, iclass 35, count 2 2006.258.00:56:26.67#ibcon#flushed, iclass 35, count 2 2006.258.00:56:26.67#ibcon#about to write, iclass 35, count 2 2006.258.00:56:26.67#ibcon#wrote, iclass 35, count 2 2006.258.00:56:26.67#ibcon#about to read 3, iclass 35, count 2 2006.258.00:56:26.70#ibcon#read 3, iclass 35, count 2 2006.258.00:56:26.70#ibcon#about to read 4, iclass 35, count 2 2006.258.00:56:26.70#ibcon#read 4, iclass 35, count 2 2006.258.00:56:26.70#ibcon#about to read 5, iclass 35, count 2 2006.258.00:56:26.70#ibcon#read 5, iclass 35, count 2 2006.258.00:56:26.70#ibcon#about to read 6, iclass 35, count 2 2006.258.00:56:26.70#ibcon#read 6, iclass 35, count 2 2006.258.00:56:26.70#ibcon#end of sib2, iclass 35, count 2 2006.258.00:56:26.70#ibcon#*after write, iclass 35, count 2 2006.258.00:56:26.70#ibcon#*before return 0, iclass 35, count 2 2006.258.00:56:26.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:26.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.00:56:26.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.00:56:26.70#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:26.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:26.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:26.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:26.82#ibcon#enter wrdev, iclass 35, count 0 2006.258.00:56:26.82#ibcon#first serial, iclass 35, count 0 2006.258.00:56:26.82#ibcon#enter sib2, iclass 35, count 0 2006.258.00:56:26.82#ibcon#flushed, iclass 35, count 0 2006.258.00:56:26.82#ibcon#about to write, iclass 35, count 0 2006.258.00:56:26.82#ibcon#wrote, iclass 35, count 0 2006.258.00:56:26.82#ibcon#about to read 3, iclass 35, count 0 2006.258.00:56:26.84#ibcon#read 3, iclass 35, count 0 2006.258.00:56:26.84#ibcon#about to read 4, iclass 35, count 0 2006.258.00:56:26.84#ibcon#read 4, iclass 35, count 0 2006.258.00:56:26.84#ibcon#about to read 5, iclass 35, count 0 2006.258.00:56:26.84#ibcon#read 5, iclass 35, count 0 2006.258.00:56:26.84#ibcon#about to read 6, iclass 35, count 0 2006.258.00:56:26.84#ibcon#read 6, iclass 35, count 0 2006.258.00:56:26.84#ibcon#end of sib2, iclass 35, count 0 2006.258.00:56:26.84#ibcon#*mode == 0, iclass 35, count 0 2006.258.00:56:26.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.00:56:26.84#ibcon#[27=USB\r\n] 2006.258.00:56:26.84#ibcon#*before write, iclass 35, count 0 2006.258.00:56:26.84#ibcon#enter sib2, iclass 35, count 0 2006.258.00:56:26.84#ibcon#flushed, iclass 35, count 0 2006.258.00:56:26.84#ibcon#about to write, iclass 35, count 0 2006.258.00:56:26.84#ibcon#wrote, iclass 35, count 0 2006.258.00:56:26.84#ibcon#about to read 3, iclass 35, count 0 2006.258.00:56:26.87#ibcon#read 3, iclass 35, count 0 2006.258.00:56:26.87#ibcon#about to read 4, iclass 35, count 0 2006.258.00:56:26.87#ibcon#read 4, iclass 35, count 0 2006.258.00:56:26.87#ibcon#about to read 5, iclass 35, count 0 2006.258.00:56:26.87#ibcon#read 5, iclass 35, count 0 2006.258.00:56:26.87#ibcon#about to read 6, iclass 35, count 0 2006.258.00:56:26.87#ibcon#read 6, iclass 35, count 0 2006.258.00:56:26.87#ibcon#end of sib2, iclass 35, count 0 2006.258.00:56:26.87#ibcon#*after write, iclass 35, count 0 2006.258.00:56:26.87#ibcon#*before return 0, iclass 35, count 0 2006.258.00:56:26.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:26.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.00:56:26.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.00:56:26.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.00:56:26.87$vck44/vblo=4,679.99 2006.258.00:56:26.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.00:56:26.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.00:56:26.87#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:26.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:26.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:26.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:26.87#ibcon#enter wrdev, iclass 37, count 0 2006.258.00:56:26.87#ibcon#first serial, iclass 37, count 0 2006.258.00:56:26.87#ibcon#enter sib2, iclass 37, count 0 2006.258.00:56:26.87#ibcon#flushed, iclass 37, count 0 2006.258.00:56:26.87#ibcon#about to write, iclass 37, count 0 2006.258.00:56:26.87#ibcon#wrote, iclass 37, count 0 2006.258.00:56:26.87#ibcon#about to read 3, iclass 37, count 0 2006.258.00:56:26.89#ibcon#read 3, iclass 37, count 0 2006.258.00:56:26.89#ibcon#about to read 4, iclass 37, count 0 2006.258.00:56:26.89#ibcon#read 4, iclass 37, count 0 2006.258.00:56:26.89#ibcon#about to read 5, iclass 37, count 0 2006.258.00:56:26.89#ibcon#read 5, iclass 37, count 0 2006.258.00:56:26.89#ibcon#about to read 6, iclass 37, count 0 2006.258.00:56:26.89#ibcon#read 6, iclass 37, count 0 2006.258.00:56:26.89#ibcon#end of sib2, iclass 37, count 0 2006.258.00:56:26.89#ibcon#*mode == 0, iclass 37, count 0 2006.258.00:56:26.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.00:56:26.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.00:56:26.89#ibcon#*before write, iclass 37, count 0 2006.258.00:56:26.89#ibcon#enter sib2, iclass 37, count 0 2006.258.00:56:26.89#ibcon#flushed, iclass 37, count 0 2006.258.00:56:26.89#ibcon#about to write, iclass 37, count 0 2006.258.00:56:26.89#ibcon#wrote, iclass 37, count 0 2006.258.00:56:26.89#ibcon#about to read 3, iclass 37, count 0 2006.258.00:56:26.93#ibcon#read 3, iclass 37, count 0 2006.258.00:56:26.93#ibcon#about to read 4, iclass 37, count 0 2006.258.00:56:26.93#ibcon#read 4, iclass 37, count 0 2006.258.00:56:26.93#ibcon#about to read 5, iclass 37, count 0 2006.258.00:56:26.93#ibcon#read 5, iclass 37, count 0 2006.258.00:56:26.93#ibcon#about to read 6, iclass 37, count 0 2006.258.00:56:26.93#ibcon#read 6, iclass 37, count 0 2006.258.00:56:26.93#ibcon#end of sib2, iclass 37, count 0 2006.258.00:56:26.93#ibcon#*after write, iclass 37, count 0 2006.258.00:56:26.93#ibcon#*before return 0, iclass 37, count 0 2006.258.00:56:26.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:26.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.00:56:26.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.00:56:26.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.00:56:26.93$vck44/vb=4,5 2006.258.00:56:26.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.258.00:56:26.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.258.00:56:26.93#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:26.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:26.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:26.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:26.99#ibcon#enter wrdev, iclass 39, count 2 2006.258.00:56:26.99#ibcon#first serial, iclass 39, count 2 2006.258.00:56:26.99#ibcon#enter sib2, iclass 39, count 2 2006.258.00:56:26.99#ibcon#flushed, iclass 39, count 2 2006.258.00:56:26.99#ibcon#about to write, iclass 39, count 2 2006.258.00:56:26.99#ibcon#wrote, iclass 39, count 2 2006.258.00:56:26.99#ibcon#about to read 3, iclass 39, count 2 2006.258.00:56:27.01#ibcon#read 3, iclass 39, count 2 2006.258.00:56:27.01#ibcon#about to read 4, iclass 39, count 2 2006.258.00:56:27.01#ibcon#read 4, iclass 39, count 2 2006.258.00:56:27.01#ibcon#about to read 5, iclass 39, count 2 2006.258.00:56:27.01#ibcon#read 5, iclass 39, count 2 2006.258.00:56:27.01#ibcon#about to read 6, iclass 39, count 2 2006.258.00:56:27.01#ibcon#read 6, iclass 39, count 2 2006.258.00:56:27.01#ibcon#end of sib2, iclass 39, count 2 2006.258.00:56:27.01#ibcon#*mode == 0, iclass 39, count 2 2006.258.00:56:27.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.258.00:56:27.01#ibcon#[27=AT04-05\r\n] 2006.258.00:56:27.01#ibcon#*before write, iclass 39, count 2 2006.258.00:56:27.01#ibcon#enter sib2, iclass 39, count 2 2006.258.00:56:27.01#ibcon#flushed, iclass 39, count 2 2006.258.00:56:27.01#ibcon#about to write, iclass 39, count 2 2006.258.00:56:27.01#ibcon#wrote, iclass 39, count 2 2006.258.00:56:27.01#ibcon#about to read 3, iclass 39, count 2 2006.258.00:56:27.04#ibcon#read 3, iclass 39, count 2 2006.258.00:56:27.04#ibcon#about to read 4, iclass 39, count 2 2006.258.00:56:27.04#ibcon#read 4, iclass 39, count 2 2006.258.00:56:27.04#ibcon#about to read 5, iclass 39, count 2 2006.258.00:56:27.04#ibcon#read 5, iclass 39, count 2 2006.258.00:56:27.04#ibcon#about to read 6, iclass 39, count 2 2006.258.00:56:27.04#ibcon#read 6, iclass 39, count 2 2006.258.00:56:27.04#ibcon#end of sib2, iclass 39, count 2 2006.258.00:56:27.04#ibcon#*after write, iclass 39, count 2 2006.258.00:56:27.04#ibcon#*before return 0, iclass 39, count 2 2006.258.00:56:27.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:27.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.258.00:56:27.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.258.00:56:27.04#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:27.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:27.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:27.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:27.16#ibcon#enter wrdev, iclass 39, count 0 2006.258.00:56:27.16#ibcon#first serial, iclass 39, count 0 2006.258.00:56:27.16#ibcon#enter sib2, iclass 39, count 0 2006.258.00:56:27.16#ibcon#flushed, iclass 39, count 0 2006.258.00:56:27.16#ibcon#about to write, iclass 39, count 0 2006.258.00:56:27.16#ibcon#wrote, iclass 39, count 0 2006.258.00:56:27.16#ibcon#about to read 3, iclass 39, count 0 2006.258.00:56:27.18#ibcon#read 3, iclass 39, count 0 2006.258.00:56:27.18#ibcon#about to read 4, iclass 39, count 0 2006.258.00:56:27.18#ibcon#read 4, iclass 39, count 0 2006.258.00:56:27.18#ibcon#about to read 5, iclass 39, count 0 2006.258.00:56:27.18#ibcon#read 5, iclass 39, count 0 2006.258.00:56:27.18#ibcon#about to read 6, iclass 39, count 0 2006.258.00:56:27.18#ibcon#read 6, iclass 39, count 0 2006.258.00:56:27.18#ibcon#end of sib2, iclass 39, count 0 2006.258.00:56:27.18#ibcon#*mode == 0, iclass 39, count 0 2006.258.00:56:27.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.00:56:27.18#ibcon#[27=USB\r\n] 2006.258.00:56:27.18#ibcon#*before write, iclass 39, count 0 2006.258.00:56:27.18#ibcon#enter sib2, iclass 39, count 0 2006.258.00:56:27.18#ibcon#flushed, iclass 39, count 0 2006.258.00:56:27.18#ibcon#about to write, iclass 39, count 0 2006.258.00:56:27.18#ibcon#wrote, iclass 39, count 0 2006.258.00:56:27.18#ibcon#about to read 3, iclass 39, count 0 2006.258.00:56:27.21#ibcon#read 3, iclass 39, count 0 2006.258.00:56:27.21#ibcon#about to read 4, iclass 39, count 0 2006.258.00:56:27.21#ibcon#read 4, iclass 39, count 0 2006.258.00:56:27.21#ibcon#about to read 5, iclass 39, count 0 2006.258.00:56:27.21#ibcon#read 5, iclass 39, count 0 2006.258.00:56:27.21#ibcon#about to read 6, iclass 39, count 0 2006.258.00:56:27.21#ibcon#read 6, iclass 39, count 0 2006.258.00:56:27.21#ibcon#end of sib2, iclass 39, count 0 2006.258.00:56:27.21#ibcon#*after write, iclass 39, count 0 2006.258.00:56:27.21#ibcon#*before return 0, iclass 39, count 0 2006.258.00:56:27.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:27.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.258.00:56:27.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.00:56:27.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.00:56:27.21$vck44/vblo=5,709.99 2006.258.00:56:27.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.00:56:27.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.00:56:27.21#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:27.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:27.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:27.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:27.21#ibcon#enter wrdev, iclass 3, count 0 2006.258.00:56:27.21#ibcon#first serial, iclass 3, count 0 2006.258.00:56:27.21#ibcon#enter sib2, iclass 3, count 0 2006.258.00:56:27.21#ibcon#flushed, iclass 3, count 0 2006.258.00:56:27.21#ibcon#about to write, iclass 3, count 0 2006.258.00:56:27.21#ibcon#wrote, iclass 3, count 0 2006.258.00:56:27.21#ibcon#about to read 3, iclass 3, count 0 2006.258.00:56:27.23#ibcon#read 3, iclass 3, count 0 2006.258.00:56:27.23#ibcon#about to read 4, iclass 3, count 0 2006.258.00:56:27.23#ibcon#read 4, iclass 3, count 0 2006.258.00:56:27.23#ibcon#about to read 5, iclass 3, count 0 2006.258.00:56:27.23#ibcon#read 5, iclass 3, count 0 2006.258.00:56:27.23#ibcon#about to read 6, iclass 3, count 0 2006.258.00:56:27.23#ibcon#read 6, iclass 3, count 0 2006.258.00:56:27.23#ibcon#end of sib2, iclass 3, count 0 2006.258.00:56:27.23#ibcon#*mode == 0, iclass 3, count 0 2006.258.00:56:27.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.00:56:27.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.00:56:27.23#ibcon#*before write, iclass 3, count 0 2006.258.00:56:27.23#ibcon#enter sib2, iclass 3, count 0 2006.258.00:56:27.23#ibcon#flushed, iclass 3, count 0 2006.258.00:56:27.23#ibcon#about to write, iclass 3, count 0 2006.258.00:56:27.23#ibcon#wrote, iclass 3, count 0 2006.258.00:56:27.23#ibcon#about to read 3, iclass 3, count 0 2006.258.00:56:27.27#ibcon#read 3, iclass 3, count 0 2006.258.00:56:27.27#ibcon#about to read 4, iclass 3, count 0 2006.258.00:56:27.27#ibcon#read 4, iclass 3, count 0 2006.258.00:56:27.27#ibcon#about to read 5, iclass 3, count 0 2006.258.00:56:27.27#ibcon#read 5, iclass 3, count 0 2006.258.00:56:27.27#ibcon#about to read 6, iclass 3, count 0 2006.258.00:56:27.27#ibcon#read 6, iclass 3, count 0 2006.258.00:56:27.27#ibcon#end of sib2, iclass 3, count 0 2006.258.00:56:27.27#ibcon#*after write, iclass 3, count 0 2006.258.00:56:27.27#ibcon#*before return 0, iclass 3, count 0 2006.258.00:56:27.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:27.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.00:56:27.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.00:56:27.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.00:56:27.27$vck44/vb=5,4 2006.258.00:56:27.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.258.00:56:27.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.258.00:56:27.27#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:27.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:27.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:27.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:27.33#ibcon#enter wrdev, iclass 5, count 2 2006.258.00:56:27.33#ibcon#first serial, iclass 5, count 2 2006.258.00:56:27.33#ibcon#enter sib2, iclass 5, count 2 2006.258.00:56:27.33#ibcon#flushed, iclass 5, count 2 2006.258.00:56:27.33#ibcon#about to write, iclass 5, count 2 2006.258.00:56:27.33#ibcon#wrote, iclass 5, count 2 2006.258.00:56:27.33#ibcon#about to read 3, iclass 5, count 2 2006.258.00:56:27.35#ibcon#read 3, iclass 5, count 2 2006.258.00:56:27.35#ibcon#about to read 4, iclass 5, count 2 2006.258.00:56:27.35#ibcon#read 4, iclass 5, count 2 2006.258.00:56:27.35#ibcon#about to read 5, iclass 5, count 2 2006.258.00:56:27.35#ibcon#read 5, iclass 5, count 2 2006.258.00:56:27.35#ibcon#about to read 6, iclass 5, count 2 2006.258.00:56:27.35#ibcon#read 6, iclass 5, count 2 2006.258.00:56:27.35#ibcon#end of sib2, iclass 5, count 2 2006.258.00:56:27.35#ibcon#*mode == 0, iclass 5, count 2 2006.258.00:56:27.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.258.00:56:27.35#ibcon#[27=AT05-04\r\n] 2006.258.00:56:27.35#ibcon#*before write, iclass 5, count 2 2006.258.00:56:27.35#ibcon#enter sib2, iclass 5, count 2 2006.258.00:56:27.35#ibcon#flushed, iclass 5, count 2 2006.258.00:56:27.35#ibcon#about to write, iclass 5, count 2 2006.258.00:56:27.35#ibcon#wrote, iclass 5, count 2 2006.258.00:56:27.35#ibcon#about to read 3, iclass 5, count 2 2006.258.00:56:27.38#ibcon#read 3, iclass 5, count 2 2006.258.00:56:27.38#ibcon#about to read 4, iclass 5, count 2 2006.258.00:56:27.38#ibcon#read 4, iclass 5, count 2 2006.258.00:56:27.38#ibcon#about to read 5, iclass 5, count 2 2006.258.00:56:27.38#ibcon#read 5, iclass 5, count 2 2006.258.00:56:27.38#ibcon#about to read 6, iclass 5, count 2 2006.258.00:56:27.38#ibcon#read 6, iclass 5, count 2 2006.258.00:56:27.38#ibcon#end of sib2, iclass 5, count 2 2006.258.00:56:27.38#ibcon#*after write, iclass 5, count 2 2006.258.00:56:27.38#ibcon#*before return 0, iclass 5, count 2 2006.258.00:56:27.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:27.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.258.00:56:27.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.258.00:56:27.38#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:27.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:27.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:27.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:27.50#ibcon#enter wrdev, iclass 5, count 0 2006.258.00:56:27.50#ibcon#first serial, iclass 5, count 0 2006.258.00:56:27.50#ibcon#enter sib2, iclass 5, count 0 2006.258.00:56:27.50#ibcon#flushed, iclass 5, count 0 2006.258.00:56:27.50#ibcon#about to write, iclass 5, count 0 2006.258.00:56:27.50#ibcon#wrote, iclass 5, count 0 2006.258.00:56:27.50#ibcon#about to read 3, iclass 5, count 0 2006.258.00:56:27.52#ibcon#read 3, iclass 5, count 0 2006.258.00:56:27.52#ibcon#about to read 4, iclass 5, count 0 2006.258.00:56:27.52#ibcon#read 4, iclass 5, count 0 2006.258.00:56:27.52#ibcon#about to read 5, iclass 5, count 0 2006.258.00:56:27.52#ibcon#read 5, iclass 5, count 0 2006.258.00:56:27.52#ibcon#about to read 6, iclass 5, count 0 2006.258.00:56:27.52#ibcon#read 6, iclass 5, count 0 2006.258.00:56:27.52#ibcon#end of sib2, iclass 5, count 0 2006.258.00:56:27.52#ibcon#*mode == 0, iclass 5, count 0 2006.258.00:56:27.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.00:56:27.52#ibcon#[27=USB\r\n] 2006.258.00:56:27.52#ibcon#*before write, iclass 5, count 0 2006.258.00:56:27.52#ibcon#enter sib2, iclass 5, count 0 2006.258.00:56:27.52#ibcon#flushed, iclass 5, count 0 2006.258.00:56:27.52#ibcon#about to write, iclass 5, count 0 2006.258.00:56:27.52#ibcon#wrote, iclass 5, count 0 2006.258.00:56:27.52#ibcon#about to read 3, iclass 5, count 0 2006.258.00:56:27.55#ibcon#read 3, iclass 5, count 0 2006.258.00:56:27.55#ibcon#about to read 4, iclass 5, count 0 2006.258.00:56:27.55#ibcon#read 4, iclass 5, count 0 2006.258.00:56:27.55#ibcon#about to read 5, iclass 5, count 0 2006.258.00:56:27.55#ibcon#read 5, iclass 5, count 0 2006.258.00:56:27.55#ibcon#about to read 6, iclass 5, count 0 2006.258.00:56:27.55#ibcon#read 6, iclass 5, count 0 2006.258.00:56:27.55#ibcon#end of sib2, iclass 5, count 0 2006.258.00:56:27.55#ibcon#*after write, iclass 5, count 0 2006.258.00:56:27.55#ibcon#*before return 0, iclass 5, count 0 2006.258.00:56:27.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:27.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.258.00:56:27.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.00:56:27.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.00:56:27.55$vck44/vblo=6,719.99 2006.258.00:56:27.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.00:56:27.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.00:56:27.55#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:27.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:27.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:27.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:27.55#ibcon#enter wrdev, iclass 7, count 0 2006.258.00:56:27.55#ibcon#first serial, iclass 7, count 0 2006.258.00:56:27.55#ibcon#enter sib2, iclass 7, count 0 2006.258.00:56:27.55#ibcon#flushed, iclass 7, count 0 2006.258.00:56:27.55#ibcon#about to write, iclass 7, count 0 2006.258.00:56:27.55#ibcon#wrote, iclass 7, count 0 2006.258.00:56:27.55#ibcon#about to read 3, iclass 7, count 0 2006.258.00:56:27.57#ibcon#read 3, iclass 7, count 0 2006.258.00:56:27.57#ibcon#about to read 4, iclass 7, count 0 2006.258.00:56:27.57#ibcon#read 4, iclass 7, count 0 2006.258.00:56:27.57#ibcon#about to read 5, iclass 7, count 0 2006.258.00:56:27.57#ibcon#read 5, iclass 7, count 0 2006.258.00:56:27.57#ibcon#about to read 6, iclass 7, count 0 2006.258.00:56:27.57#ibcon#read 6, iclass 7, count 0 2006.258.00:56:27.57#ibcon#end of sib2, iclass 7, count 0 2006.258.00:56:27.57#ibcon#*mode == 0, iclass 7, count 0 2006.258.00:56:27.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.00:56:27.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.00:56:27.57#ibcon#*before write, iclass 7, count 0 2006.258.00:56:27.57#ibcon#enter sib2, iclass 7, count 0 2006.258.00:56:27.57#ibcon#flushed, iclass 7, count 0 2006.258.00:56:27.57#ibcon#about to write, iclass 7, count 0 2006.258.00:56:27.57#ibcon#wrote, iclass 7, count 0 2006.258.00:56:27.57#ibcon#about to read 3, iclass 7, count 0 2006.258.00:56:27.61#ibcon#read 3, iclass 7, count 0 2006.258.00:56:27.61#ibcon#about to read 4, iclass 7, count 0 2006.258.00:56:27.61#ibcon#read 4, iclass 7, count 0 2006.258.00:56:27.61#ibcon#about to read 5, iclass 7, count 0 2006.258.00:56:27.61#ibcon#read 5, iclass 7, count 0 2006.258.00:56:27.61#ibcon#about to read 6, iclass 7, count 0 2006.258.00:56:27.61#ibcon#read 6, iclass 7, count 0 2006.258.00:56:27.61#ibcon#end of sib2, iclass 7, count 0 2006.258.00:56:27.61#ibcon#*after write, iclass 7, count 0 2006.258.00:56:27.61#ibcon#*before return 0, iclass 7, count 0 2006.258.00:56:27.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:27.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.00:56:27.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.00:56:27.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.00:56:27.61$vck44/vb=6,4 2006.258.00:56:27.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.00:56:27.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.00:56:27.61#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:27.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:27.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:27.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:27.67#ibcon#enter wrdev, iclass 11, count 2 2006.258.00:56:27.67#ibcon#first serial, iclass 11, count 2 2006.258.00:56:27.67#ibcon#enter sib2, iclass 11, count 2 2006.258.00:56:27.67#ibcon#flushed, iclass 11, count 2 2006.258.00:56:27.67#ibcon#about to write, iclass 11, count 2 2006.258.00:56:27.67#ibcon#wrote, iclass 11, count 2 2006.258.00:56:27.67#ibcon#about to read 3, iclass 11, count 2 2006.258.00:56:27.69#ibcon#read 3, iclass 11, count 2 2006.258.00:56:27.69#ibcon#about to read 4, iclass 11, count 2 2006.258.00:56:27.69#ibcon#read 4, iclass 11, count 2 2006.258.00:56:27.69#ibcon#about to read 5, iclass 11, count 2 2006.258.00:56:27.69#ibcon#read 5, iclass 11, count 2 2006.258.00:56:27.69#ibcon#about to read 6, iclass 11, count 2 2006.258.00:56:27.69#ibcon#read 6, iclass 11, count 2 2006.258.00:56:27.69#ibcon#end of sib2, iclass 11, count 2 2006.258.00:56:27.69#ibcon#*mode == 0, iclass 11, count 2 2006.258.00:56:27.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.00:56:27.69#ibcon#[27=AT06-04\r\n] 2006.258.00:56:27.69#ibcon#*before write, iclass 11, count 2 2006.258.00:56:27.69#ibcon#enter sib2, iclass 11, count 2 2006.258.00:56:27.69#ibcon#flushed, iclass 11, count 2 2006.258.00:56:27.69#ibcon#about to write, iclass 11, count 2 2006.258.00:56:27.69#ibcon#wrote, iclass 11, count 2 2006.258.00:56:27.69#ibcon#about to read 3, iclass 11, count 2 2006.258.00:56:27.72#ibcon#read 3, iclass 11, count 2 2006.258.00:56:27.72#ibcon#about to read 4, iclass 11, count 2 2006.258.00:56:27.72#ibcon#read 4, iclass 11, count 2 2006.258.00:56:27.72#ibcon#about to read 5, iclass 11, count 2 2006.258.00:56:27.72#ibcon#read 5, iclass 11, count 2 2006.258.00:56:27.72#ibcon#about to read 6, iclass 11, count 2 2006.258.00:56:27.72#ibcon#read 6, iclass 11, count 2 2006.258.00:56:27.72#ibcon#end of sib2, iclass 11, count 2 2006.258.00:56:27.72#ibcon#*after write, iclass 11, count 2 2006.258.00:56:27.72#ibcon#*before return 0, iclass 11, count 2 2006.258.00:56:27.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:27.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.00:56:27.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.00:56:27.72#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:27.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:27.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:27.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:27.84#ibcon#enter wrdev, iclass 11, count 0 2006.258.00:56:27.84#ibcon#first serial, iclass 11, count 0 2006.258.00:56:27.84#ibcon#enter sib2, iclass 11, count 0 2006.258.00:56:27.84#ibcon#flushed, iclass 11, count 0 2006.258.00:56:27.84#ibcon#about to write, iclass 11, count 0 2006.258.00:56:27.84#ibcon#wrote, iclass 11, count 0 2006.258.00:56:27.84#ibcon#about to read 3, iclass 11, count 0 2006.258.00:56:27.86#ibcon#read 3, iclass 11, count 0 2006.258.00:56:27.86#ibcon#about to read 4, iclass 11, count 0 2006.258.00:56:27.86#ibcon#read 4, iclass 11, count 0 2006.258.00:56:27.86#ibcon#about to read 5, iclass 11, count 0 2006.258.00:56:27.86#ibcon#read 5, iclass 11, count 0 2006.258.00:56:27.86#ibcon#about to read 6, iclass 11, count 0 2006.258.00:56:27.86#ibcon#read 6, iclass 11, count 0 2006.258.00:56:27.86#ibcon#end of sib2, iclass 11, count 0 2006.258.00:56:27.86#ibcon#*mode == 0, iclass 11, count 0 2006.258.00:56:27.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.00:56:27.86#ibcon#[27=USB\r\n] 2006.258.00:56:27.86#ibcon#*before write, iclass 11, count 0 2006.258.00:56:27.86#ibcon#enter sib2, iclass 11, count 0 2006.258.00:56:27.86#ibcon#flushed, iclass 11, count 0 2006.258.00:56:27.86#ibcon#about to write, iclass 11, count 0 2006.258.00:56:27.86#ibcon#wrote, iclass 11, count 0 2006.258.00:56:27.86#ibcon#about to read 3, iclass 11, count 0 2006.258.00:56:27.89#ibcon#read 3, iclass 11, count 0 2006.258.00:56:27.89#ibcon#about to read 4, iclass 11, count 0 2006.258.00:56:27.89#ibcon#read 4, iclass 11, count 0 2006.258.00:56:27.89#ibcon#about to read 5, iclass 11, count 0 2006.258.00:56:27.89#ibcon#read 5, iclass 11, count 0 2006.258.00:56:27.89#ibcon#about to read 6, iclass 11, count 0 2006.258.00:56:27.89#ibcon#read 6, iclass 11, count 0 2006.258.00:56:27.89#ibcon#end of sib2, iclass 11, count 0 2006.258.00:56:27.89#ibcon#*after write, iclass 11, count 0 2006.258.00:56:27.89#ibcon#*before return 0, iclass 11, count 0 2006.258.00:56:27.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:27.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.00:56:27.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.00:56:27.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.00:56:27.89$vck44/vblo=7,734.99 2006.258.00:56:27.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.258.00:56:27.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.258.00:56:27.89#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:27.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:27.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:27.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:27.89#ibcon#enter wrdev, iclass 13, count 0 2006.258.00:56:27.89#ibcon#first serial, iclass 13, count 0 2006.258.00:56:27.89#ibcon#enter sib2, iclass 13, count 0 2006.258.00:56:27.89#ibcon#flushed, iclass 13, count 0 2006.258.00:56:27.89#ibcon#about to write, iclass 13, count 0 2006.258.00:56:27.89#ibcon#wrote, iclass 13, count 0 2006.258.00:56:27.89#ibcon#about to read 3, iclass 13, count 0 2006.258.00:56:27.91#ibcon#read 3, iclass 13, count 0 2006.258.00:56:27.91#ibcon#about to read 4, iclass 13, count 0 2006.258.00:56:27.91#ibcon#read 4, iclass 13, count 0 2006.258.00:56:27.91#ibcon#about to read 5, iclass 13, count 0 2006.258.00:56:27.91#ibcon#read 5, iclass 13, count 0 2006.258.00:56:27.91#ibcon#about to read 6, iclass 13, count 0 2006.258.00:56:27.91#ibcon#read 6, iclass 13, count 0 2006.258.00:56:27.91#ibcon#end of sib2, iclass 13, count 0 2006.258.00:56:27.91#ibcon#*mode == 0, iclass 13, count 0 2006.258.00:56:27.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.00:56:27.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.00:56:27.91#ibcon#*before write, iclass 13, count 0 2006.258.00:56:27.91#ibcon#enter sib2, iclass 13, count 0 2006.258.00:56:27.91#ibcon#flushed, iclass 13, count 0 2006.258.00:56:27.91#ibcon#about to write, iclass 13, count 0 2006.258.00:56:27.91#ibcon#wrote, iclass 13, count 0 2006.258.00:56:27.91#ibcon#about to read 3, iclass 13, count 0 2006.258.00:56:27.95#ibcon#read 3, iclass 13, count 0 2006.258.00:56:27.95#ibcon#about to read 4, iclass 13, count 0 2006.258.00:56:27.95#ibcon#read 4, iclass 13, count 0 2006.258.00:56:27.95#ibcon#about to read 5, iclass 13, count 0 2006.258.00:56:27.95#ibcon#read 5, iclass 13, count 0 2006.258.00:56:27.95#ibcon#about to read 6, iclass 13, count 0 2006.258.00:56:27.95#ibcon#read 6, iclass 13, count 0 2006.258.00:56:27.95#ibcon#end of sib2, iclass 13, count 0 2006.258.00:56:27.95#ibcon#*after write, iclass 13, count 0 2006.258.00:56:27.95#ibcon#*before return 0, iclass 13, count 0 2006.258.00:56:27.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:27.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.258.00:56:27.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.00:56:27.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.00:56:27.95$vck44/vb=7,4 2006.258.00:56:27.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.258.00:56:27.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.258.00:56:27.95#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:27.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:28.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:28.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:28.01#ibcon#enter wrdev, iclass 15, count 2 2006.258.00:56:28.01#ibcon#first serial, iclass 15, count 2 2006.258.00:56:28.01#ibcon#enter sib2, iclass 15, count 2 2006.258.00:56:28.01#ibcon#flushed, iclass 15, count 2 2006.258.00:56:28.01#ibcon#about to write, iclass 15, count 2 2006.258.00:56:28.01#ibcon#wrote, iclass 15, count 2 2006.258.00:56:28.01#ibcon#about to read 3, iclass 15, count 2 2006.258.00:56:28.03#ibcon#read 3, iclass 15, count 2 2006.258.00:56:28.03#ibcon#about to read 4, iclass 15, count 2 2006.258.00:56:28.03#ibcon#read 4, iclass 15, count 2 2006.258.00:56:28.03#ibcon#about to read 5, iclass 15, count 2 2006.258.00:56:28.03#ibcon#read 5, iclass 15, count 2 2006.258.00:56:28.03#ibcon#about to read 6, iclass 15, count 2 2006.258.00:56:28.03#ibcon#read 6, iclass 15, count 2 2006.258.00:56:28.03#ibcon#end of sib2, iclass 15, count 2 2006.258.00:56:28.03#ibcon#*mode == 0, iclass 15, count 2 2006.258.00:56:28.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.258.00:56:28.03#ibcon#[27=AT07-04\r\n] 2006.258.00:56:28.03#ibcon#*before write, iclass 15, count 2 2006.258.00:56:28.03#ibcon#enter sib2, iclass 15, count 2 2006.258.00:56:28.03#ibcon#flushed, iclass 15, count 2 2006.258.00:56:28.03#ibcon#about to write, iclass 15, count 2 2006.258.00:56:28.03#ibcon#wrote, iclass 15, count 2 2006.258.00:56:28.03#ibcon#about to read 3, iclass 15, count 2 2006.258.00:56:28.06#ibcon#read 3, iclass 15, count 2 2006.258.00:56:28.06#ibcon#about to read 4, iclass 15, count 2 2006.258.00:56:28.06#ibcon#read 4, iclass 15, count 2 2006.258.00:56:28.06#ibcon#about to read 5, iclass 15, count 2 2006.258.00:56:28.06#ibcon#read 5, iclass 15, count 2 2006.258.00:56:28.06#ibcon#about to read 6, iclass 15, count 2 2006.258.00:56:28.06#ibcon#read 6, iclass 15, count 2 2006.258.00:56:28.06#ibcon#end of sib2, iclass 15, count 2 2006.258.00:56:28.06#ibcon#*after write, iclass 15, count 2 2006.258.00:56:28.06#ibcon#*before return 0, iclass 15, count 2 2006.258.00:56:28.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:28.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.258.00:56:28.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.258.00:56:28.06#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:28.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:28.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:28.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:28.18#ibcon#enter wrdev, iclass 15, count 0 2006.258.00:56:28.18#ibcon#first serial, iclass 15, count 0 2006.258.00:56:28.18#ibcon#enter sib2, iclass 15, count 0 2006.258.00:56:28.18#ibcon#flushed, iclass 15, count 0 2006.258.00:56:28.18#ibcon#about to write, iclass 15, count 0 2006.258.00:56:28.18#ibcon#wrote, iclass 15, count 0 2006.258.00:56:28.18#ibcon#about to read 3, iclass 15, count 0 2006.258.00:56:28.20#ibcon#read 3, iclass 15, count 0 2006.258.00:56:28.20#ibcon#about to read 4, iclass 15, count 0 2006.258.00:56:28.20#ibcon#read 4, iclass 15, count 0 2006.258.00:56:28.20#ibcon#about to read 5, iclass 15, count 0 2006.258.00:56:28.20#ibcon#read 5, iclass 15, count 0 2006.258.00:56:28.20#ibcon#about to read 6, iclass 15, count 0 2006.258.00:56:28.20#ibcon#read 6, iclass 15, count 0 2006.258.00:56:28.20#ibcon#end of sib2, iclass 15, count 0 2006.258.00:56:28.20#ibcon#*mode == 0, iclass 15, count 0 2006.258.00:56:28.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.00:56:28.20#ibcon#[27=USB\r\n] 2006.258.00:56:28.20#ibcon#*before write, iclass 15, count 0 2006.258.00:56:28.20#ibcon#enter sib2, iclass 15, count 0 2006.258.00:56:28.20#ibcon#flushed, iclass 15, count 0 2006.258.00:56:28.20#ibcon#about to write, iclass 15, count 0 2006.258.00:56:28.20#ibcon#wrote, iclass 15, count 0 2006.258.00:56:28.20#ibcon#about to read 3, iclass 15, count 0 2006.258.00:56:28.23#ibcon#read 3, iclass 15, count 0 2006.258.00:56:28.23#ibcon#about to read 4, iclass 15, count 0 2006.258.00:56:28.23#ibcon#read 4, iclass 15, count 0 2006.258.00:56:28.23#ibcon#about to read 5, iclass 15, count 0 2006.258.00:56:28.23#ibcon#read 5, iclass 15, count 0 2006.258.00:56:28.23#ibcon#about to read 6, iclass 15, count 0 2006.258.00:56:28.23#ibcon#read 6, iclass 15, count 0 2006.258.00:56:28.23#ibcon#end of sib2, iclass 15, count 0 2006.258.00:56:28.23#ibcon#*after write, iclass 15, count 0 2006.258.00:56:28.23#ibcon#*before return 0, iclass 15, count 0 2006.258.00:56:28.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:28.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.258.00:56:28.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.00:56:28.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.00:56:28.23$vck44/vblo=8,744.99 2006.258.00:56:28.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.00:56:28.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.00:56:28.23#ibcon#ireg 17 cls_cnt 0 2006.258.00:56:28.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:56:28.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:56:28.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:56:28.23#ibcon#enter wrdev, iclass 18, count 0 2006.258.00:56:28.23#ibcon#first serial, iclass 18, count 0 2006.258.00:56:28.23#ibcon#enter sib2, iclass 18, count 0 2006.258.00:56:28.23#ibcon#flushed, iclass 18, count 0 2006.258.00:56:28.23#ibcon#about to write, iclass 18, count 0 2006.258.00:56:28.23#ibcon#wrote, iclass 18, count 0 2006.258.00:56:28.23#ibcon#about to read 3, iclass 18, count 0 2006.258.00:56:28.25#ibcon#read 3, iclass 18, count 0 2006.258.00:56:28.25#ibcon#about to read 4, iclass 18, count 0 2006.258.00:56:28.25#ibcon#read 4, iclass 18, count 0 2006.258.00:56:28.25#ibcon#about to read 5, iclass 18, count 0 2006.258.00:56:28.25#ibcon#read 5, iclass 18, count 0 2006.258.00:56:28.25#ibcon#about to read 6, iclass 18, count 0 2006.258.00:56:28.25#ibcon#read 6, iclass 18, count 0 2006.258.00:56:28.25#ibcon#end of sib2, iclass 18, count 0 2006.258.00:56:28.25#ibcon#*mode == 0, iclass 18, count 0 2006.258.00:56:28.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.00:56:28.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.00:56:28.25#ibcon#*before write, iclass 18, count 0 2006.258.00:56:28.25#ibcon#enter sib2, iclass 18, count 0 2006.258.00:56:28.25#ibcon#flushed, iclass 18, count 0 2006.258.00:56:28.25#ibcon#about to write, iclass 18, count 0 2006.258.00:56:28.25#ibcon#wrote, iclass 18, count 0 2006.258.00:56:28.25#ibcon#about to read 3, iclass 18, count 0 2006.258.00:56:28.26#abcon#<5=/01 1.8 6.1 22.65 751016.2\r\n> 2006.258.00:56:28.28#abcon#{5=INTERFACE CLEAR} 2006.258.00:56:28.29#ibcon#read 3, iclass 18, count 0 2006.258.00:56:28.29#ibcon#about to read 4, iclass 18, count 0 2006.258.00:56:28.29#ibcon#read 4, iclass 18, count 0 2006.258.00:56:28.29#ibcon#about to read 5, iclass 18, count 0 2006.258.00:56:28.29#ibcon#read 5, iclass 18, count 0 2006.258.00:56:28.29#ibcon#about to read 6, iclass 18, count 0 2006.258.00:56:28.29#ibcon#read 6, iclass 18, count 0 2006.258.00:56:28.29#ibcon#end of sib2, iclass 18, count 0 2006.258.00:56:28.29#ibcon#*after write, iclass 18, count 0 2006.258.00:56:28.29#ibcon#*before return 0, iclass 18, count 0 2006.258.00:56:28.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:56:28.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.00:56:28.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.00:56:28.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.00:56:28.29$vck44/vb=8,4 2006.258.00:56:28.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.00:56:28.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.00:56:28.29#ibcon#ireg 11 cls_cnt 2 2006.258.00:56:28.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:56:28.34#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:56:28.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:56:28.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:56:28.35#ibcon#enter wrdev, iclass 22, count 2 2006.258.00:56:28.35#ibcon#first serial, iclass 22, count 2 2006.258.00:56:28.35#ibcon#enter sib2, iclass 22, count 2 2006.258.00:56:28.35#ibcon#flushed, iclass 22, count 2 2006.258.00:56:28.35#ibcon#about to write, iclass 22, count 2 2006.258.00:56:28.35#ibcon#wrote, iclass 22, count 2 2006.258.00:56:28.35#ibcon#about to read 3, iclass 22, count 2 2006.258.00:56:28.37#ibcon#read 3, iclass 22, count 2 2006.258.00:56:28.37#ibcon#about to read 4, iclass 22, count 2 2006.258.00:56:28.37#ibcon#read 4, iclass 22, count 2 2006.258.00:56:28.37#ibcon#about to read 5, iclass 22, count 2 2006.258.00:56:28.37#ibcon#read 5, iclass 22, count 2 2006.258.00:56:28.37#ibcon#about to read 6, iclass 22, count 2 2006.258.00:56:28.37#ibcon#read 6, iclass 22, count 2 2006.258.00:56:28.37#ibcon#end of sib2, iclass 22, count 2 2006.258.00:56:28.37#ibcon#*mode == 0, iclass 22, count 2 2006.258.00:56:28.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.00:56:28.37#ibcon#[27=AT08-04\r\n] 2006.258.00:56:28.37#ibcon#*before write, iclass 22, count 2 2006.258.00:56:28.37#ibcon#enter sib2, iclass 22, count 2 2006.258.00:56:28.37#ibcon#flushed, iclass 22, count 2 2006.258.00:56:28.37#ibcon#about to write, iclass 22, count 2 2006.258.00:56:28.37#ibcon#wrote, iclass 22, count 2 2006.258.00:56:28.37#ibcon#about to read 3, iclass 22, count 2 2006.258.00:56:28.40#ibcon#read 3, iclass 22, count 2 2006.258.00:56:28.40#ibcon#about to read 4, iclass 22, count 2 2006.258.00:56:28.40#ibcon#read 4, iclass 22, count 2 2006.258.00:56:28.40#ibcon#about to read 5, iclass 22, count 2 2006.258.00:56:28.40#ibcon#read 5, iclass 22, count 2 2006.258.00:56:28.40#ibcon#about to read 6, iclass 22, count 2 2006.258.00:56:28.40#ibcon#read 6, iclass 22, count 2 2006.258.00:56:28.40#ibcon#end of sib2, iclass 22, count 2 2006.258.00:56:28.40#ibcon#*after write, iclass 22, count 2 2006.258.00:56:28.40#ibcon#*before return 0, iclass 22, count 2 2006.258.00:56:28.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:56:28.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.00:56:28.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.00:56:28.40#ibcon#ireg 7 cls_cnt 0 2006.258.00:56:28.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:56:28.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:56:28.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:56:28.52#ibcon#enter wrdev, iclass 22, count 0 2006.258.00:56:28.52#ibcon#first serial, iclass 22, count 0 2006.258.00:56:28.52#ibcon#enter sib2, iclass 22, count 0 2006.258.00:56:28.52#ibcon#flushed, iclass 22, count 0 2006.258.00:56:28.52#ibcon#about to write, iclass 22, count 0 2006.258.00:56:28.52#ibcon#wrote, iclass 22, count 0 2006.258.00:56:28.52#ibcon#about to read 3, iclass 22, count 0 2006.258.00:56:28.54#ibcon#read 3, iclass 22, count 0 2006.258.00:56:28.54#ibcon#about to read 4, iclass 22, count 0 2006.258.00:56:28.54#ibcon#read 4, iclass 22, count 0 2006.258.00:56:28.54#ibcon#about to read 5, iclass 22, count 0 2006.258.00:56:28.54#ibcon#read 5, iclass 22, count 0 2006.258.00:56:28.54#ibcon#about to read 6, iclass 22, count 0 2006.258.00:56:28.54#ibcon#read 6, iclass 22, count 0 2006.258.00:56:28.54#ibcon#end of sib2, iclass 22, count 0 2006.258.00:56:28.54#ibcon#*mode == 0, iclass 22, count 0 2006.258.00:56:28.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.00:56:28.54#ibcon#[27=USB\r\n] 2006.258.00:56:28.54#ibcon#*before write, iclass 22, count 0 2006.258.00:56:28.54#ibcon#enter sib2, iclass 22, count 0 2006.258.00:56:28.54#ibcon#flushed, iclass 22, count 0 2006.258.00:56:28.54#ibcon#about to write, iclass 22, count 0 2006.258.00:56:28.54#ibcon#wrote, iclass 22, count 0 2006.258.00:56:28.54#ibcon#about to read 3, iclass 22, count 0 2006.258.00:56:28.57#ibcon#read 3, iclass 22, count 0 2006.258.00:56:28.57#ibcon#about to read 4, iclass 22, count 0 2006.258.00:56:28.57#ibcon#read 4, iclass 22, count 0 2006.258.00:56:28.57#ibcon#about to read 5, iclass 22, count 0 2006.258.00:56:28.57#ibcon#read 5, iclass 22, count 0 2006.258.00:56:28.57#ibcon#about to read 6, iclass 22, count 0 2006.258.00:56:28.57#ibcon#read 6, iclass 22, count 0 2006.258.00:56:28.57#ibcon#end of sib2, iclass 22, count 0 2006.258.00:56:28.57#ibcon#*after write, iclass 22, count 0 2006.258.00:56:28.57#ibcon#*before return 0, iclass 22, count 0 2006.258.00:56:28.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:56:28.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.00:56:28.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.00:56:28.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.00:56:28.57$vck44/vabw=wide 2006.258.00:56:28.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.00:56:28.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.00:56:28.57#ibcon#ireg 8 cls_cnt 0 2006.258.00:56:28.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:28.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:28.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:28.57#ibcon#enter wrdev, iclass 25, count 0 2006.258.00:56:28.57#ibcon#first serial, iclass 25, count 0 2006.258.00:56:28.57#ibcon#enter sib2, iclass 25, count 0 2006.258.00:56:28.57#ibcon#flushed, iclass 25, count 0 2006.258.00:56:28.57#ibcon#about to write, iclass 25, count 0 2006.258.00:56:28.57#ibcon#wrote, iclass 25, count 0 2006.258.00:56:28.57#ibcon#about to read 3, iclass 25, count 0 2006.258.00:56:28.59#ibcon#read 3, iclass 25, count 0 2006.258.00:56:28.59#ibcon#about to read 4, iclass 25, count 0 2006.258.00:56:28.59#ibcon#read 4, iclass 25, count 0 2006.258.00:56:28.59#ibcon#about to read 5, iclass 25, count 0 2006.258.00:56:28.59#ibcon#read 5, iclass 25, count 0 2006.258.00:56:28.59#ibcon#about to read 6, iclass 25, count 0 2006.258.00:56:28.59#ibcon#read 6, iclass 25, count 0 2006.258.00:56:28.59#ibcon#end of sib2, iclass 25, count 0 2006.258.00:56:28.59#ibcon#*mode == 0, iclass 25, count 0 2006.258.00:56:28.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.00:56:28.59#ibcon#[25=BW32\r\n] 2006.258.00:56:28.59#ibcon#*before write, iclass 25, count 0 2006.258.00:56:28.59#ibcon#enter sib2, iclass 25, count 0 2006.258.00:56:28.59#ibcon#flushed, iclass 25, count 0 2006.258.00:56:28.59#ibcon#about to write, iclass 25, count 0 2006.258.00:56:28.59#ibcon#wrote, iclass 25, count 0 2006.258.00:56:28.59#ibcon#about to read 3, iclass 25, count 0 2006.258.00:56:28.62#ibcon#read 3, iclass 25, count 0 2006.258.00:56:28.62#ibcon#about to read 4, iclass 25, count 0 2006.258.00:56:28.62#ibcon#read 4, iclass 25, count 0 2006.258.00:56:28.62#ibcon#about to read 5, iclass 25, count 0 2006.258.00:56:28.62#ibcon#read 5, iclass 25, count 0 2006.258.00:56:28.62#ibcon#about to read 6, iclass 25, count 0 2006.258.00:56:28.62#ibcon#read 6, iclass 25, count 0 2006.258.00:56:28.62#ibcon#end of sib2, iclass 25, count 0 2006.258.00:56:28.62#ibcon#*after write, iclass 25, count 0 2006.258.00:56:28.62#ibcon#*before return 0, iclass 25, count 0 2006.258.00:56:28.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:28.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.00:56:28.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.00:56:28.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.00:56:28.62$vck44/vbbw=wide 2006.258.00:56:28.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.00:56:28.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.00:56:28.62#ibcon#ireg 8 cls_cnt 0 2006.258.00:56:28.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:56:28.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:56:28.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:56:28.69#ibcon#enter wrdev, iclass 27, count 0 2006.258.00:56:28.69#ibcon#first serial, iclass 27, count 0 2006.258.00:56:28.69#ibcon#enter sib2, iclass 27, count 0 2006.258.00:56:28.69#ibcon#flushed, iclass 27, count 0 2006.258.00:56:28.69#ibcon#about to write, iclass 27, count 0 2006.258.00:56:28.69#ibcon#wrote, iclass 27, count 0 2006.258.00:56:28.69#ibcon#about to read 3, iclass 27, count 0 2006.258.00:56:28.71#ibcon#read 3, iclass 27, count 0 2006.258.00:56:28.71#ibcon#about to read 4, iclass 27, count 0 2006.258.00:56:28.71#ibcon#read 4, iclass 27, count 0 2006.258.00:56:28.71#ibcon#about to read 5, iclass 27, count 0 2006.258.00:56:28.71#ibcon#read 5, iclass 27, count 0 2006.258.00:56:28.71#ibcon#about to read 6, iclass 27, count 0 2006.258.00:56:28.71#ibcon#read 6, iclass 27, count 0 2006.258.00:56:28.71#ibcon#end of sib2, iclass 27, count 0 2006.258.00:56:28.71#ibcon#*mode == 0, iclass 27, count 0 2006.258.00:56:28.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.00:56:28.71#ibcon#[27=BW32\r\n] 2006.258.00:56:28.71#ibcon#*before write, iclass 27, count 0 2006.258.00:56:28.71#ibcon#enter sib2, iclass 27, count 0 2006.258.00:56:28.71#ibcon#flushed, iclass 27, count 0 2006.258.00:56:28.71#ibcon#about to write, iclass 27, count 0 2006.258.00:56:28.71#ibcon#wrote, iclass 27, count 0 2006.258.00:56:28.71#ibcon#about to read 3, iclass 27, count 0 2006.258.00:56:28.74#ibcon#read 3, iclass 27, count 0 2006.258.00:56:28.74#ibcon#about to read 4, iclass 27, count 0 2006.258.00:56:28.74#ibcon#read 4, iclass 27, count 0 2006.258.00:56:28.74#ibcon#about to read 5, iclass 27, count 0 2006.258.00:56:28.74#ibcon#read 5, iclass 27, count 0 2006.258.00:56:28.74#ibcon#about to read 6, iclass 27, count 0 2006.258.00:56:28.74#ibcon#read 6, iclass 27, count 0 2006.258.00:56:28.74#ibcon#end of sib2, iclass 27, count 0 2006.258.00:56:28.74#ibcon#*after write, iclass 27, count 0 2006.258.00:56:28.74#ibcon#*before return 0, iclass 27, count 0 2006.258.00:56:28.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:56:28.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.00:56:28.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.00:56:28.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.00:56:28.74$setupk4/ifdk4 2006.258.00:56:28.74$ifdk4/lo= 2006.258.00:56:28.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.00:56:28.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.00:56:28.74$ifdk4/patch= 2006.258.00:56:28.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.00:56:28.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.00:56:28.74$setupk4/!*+20s 2006.258.00:56:38.57#abcon#<5=/01 1.9 6.1 22.66 761016.2\r\n> 2006.258.00:56:38.59#abcon#{5=INTERFACE CLEAR} 2006.258.00:56:38.65#abcon#[5=S1D000X0/0*\r\n] 2006.258.00:56:43.25$setupk4/"tpicd 2006.258.00:56:43.25$setupk4/echo=off 2006.258.00:56:43.25$setupk4/xlog=off 2006.258.00:56:43.25:!2006.258.01:00:26 2006.258.00:56:55.14#trakl#Source acquired 2006.258.00:56:57.14#flagr#flagr/antenna,acquired 2006.258.01:00:26.00:preob 2006.258.01:00:26.14/onsource/TRACKING 2006.258.01:00:26.14:!2006.258.01:00:36 2006.258.01:00:36.00:"tape 2006.258.01:00:36.00:"st=record 2006.258.01:00:36.00:data_valid=on 2006.258.01:00:36.00:midob 2006.258.01:00:36.14/onsource/TRACKING 2006.258.01:00:36.14/wx/22.74,1016.1,77 2006.258.01:00:36.32/cable/+6.4757E-03 2006.258.01:00:37.41/va/01,08,usb,yes,32,34 2006.258.01:00:37.41/va/02,07,usb,yes,34,35 2006.258.01:00:37.41/va/03,08,usb,yes,31,32 2006.258.01:00:37.41/va/04,07,usb,yes,35,37 2006.258.01:00:37.41/va/05,04,usb,yes,31,32 2006.258.01:00:37.41/va/06,04,usb,yes,35,35 2006.258.01:00:37.41/va/07,04,usb,yes,36,36 2006.258.01:00:37.41/va/08,04,usb,yes,30,37 2006.258.01:00:37.64/valo/01,524.99,yes,locked 2006.258.01:00:37.64/valo/02,534.99,yes,locked 2006.258.01:00:37.64/valo/03,564.99,yes,locked 2006.258.01:00:37.64/valo/04,624.99,yes,locked 2006.258.01:00:37.64/valo/05,734.99,yes,locked 2006.258.01:00:37.64/valo/06,814.99,yes,locked 2006.258.01:00:37.64/valo/07,864.99,yes,locked 2006.258.01:00:37.64/valo/08,884.99,yes,locked 2006.258.01:00:38.73/vb/01,04,usb,yes,36,30 2006.258.01:00:38.73/vb/02,05,usb,yes,30,34 2006.258.01:00:38.73/vb/03,04,usb,yes,31,35 2006.258.01:00:38.73/vb/04,05,usb,yes,31,30 2006.258.01:00:38.73/vb/05,04,usb,yes,27,30 2006.258.01:00:38.73/vb/06,04,usb,yes,32,28 2006.258.01:00:38.73/vb/07,04,usb,yes,32,32 2006.258.01:00:38.73/vb/08,04,usb,yes,29,33 2006.258.01:00:38.97/vblo/01,629.99,yes,locked 2006.258.01:00:38.97/vblo/02,634.99,yes,locked 2006.258.01:00:38.97/vblo/03,649.99,yes,locked 2006.258.01:00:38.97/vblo/04,679.99,yes,locked 2006.258.01:00:38.97/vblo/05,709.99,yes,locked 2006.258.01:00:38.97/vblo/06,719.99,yes,locked 2006.258.01:00:38.97/vblo/07,734.99,yes,locked 2006.258.01:00:38.97/vblo/08,744.99,yes,locked 2006.258.01:00:39.12/vabw/8 2006.258.01:00:39.27/vbbw/8 2006.258.01:00:39.40/xfe/off,on,15.0 2006.258.01:00:39.80/ifatt/23,28,28,28 2006.258.01:00:40.08/fmout-gps/S +4.58E-07 2006.258.01:00:40.12:!2006.258.01:06:26 2006.258.01:06:26.00:data_valid=off 2006.258.01:06:26.00:"et 2006.258.01:06:26.00:!+3s 2006.258.01:06:29.01:"tape 2006.258.01:06:29.01:postob 2006.258.01:06:29.12/cable/+6.4760E-03 2006.258.01:06:29.12/wx/22.68,1016.1,75 2006.258.01:06:30.07/fmout-gps/S +4.56E-07 2006.258.01:06:30.07:scan_name=258-0111,jd0609,120 2006.258.01:06:30.07:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.258.01:06:31.13:checkk5 2006.258.01:06:31.13#flagr#flagr/antenna,new-source 2006.258.01:06:31.55/chk_autoobs//k5ts1/ autoobs is running! 2006.258.01:06:31.95/chk_autoobs//k5ts2/ autoobs is running! 2006.258.01:06:32.36/chk_autoobs//k5ts3/ autoobs is running! 2006.258.01:06:32.77/chk_autoobs//k5ts4/ autoobs is running! 2006.258.01:06:33.23/chk_obsdata//k5ts1/T2580100??a.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.258.01:06:33.64/chk_obsdata//k5ts2/T2580100??b.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.258.01:06:34.03/chk_obsdata//k5ts3/T2580100??c.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.258.01:06:34.44/chk_obsdata//k5ts4/T2580100??d.dat file size is correct (nominal:1400MB, actual:1400MB). 2006.258.01:06:35.16/k5log//k5ts1_log_newline 2006.258.01:06:35.89/k5log//k5ts2_log_newline 2006.258.01:06:36.60/k5log//k5ts3_log_newline 2006.258.01:06:37.31/k5log//k5ts4_log_newline 2006.258.01:06:37.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:06:37.33:setupk4=1 2006.258.01:06:37.33$setupk4/echo=on 2006.258.01:06:37.33$setupk4/pcalon 2006.258.01:06:37.33$pcalon/"no phase cal control is implemented here 2006.258.01:06:37.33$setupk4/"tpicd=stop 2006.258.01:06:37.33$setupk4/"rec=synch_on 2006.258.01:06:37.33$setupk4/"rec_mode=128 2006.258.01:06:37.33$setupk4/!* 2006.258.01:06:37.33$setupk4/recpk4 2006.258.01:06:37.33$recpk4/recpatch= 2006.258.01:06:37.34$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.01:06:37.34$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.01:06:37.34$setupk4/vck44 2006.258.01:06:37.34$vck44/valo=1,524.99 2006.258.01:06:37.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.01:06:37.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.01:06:37.34#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:37.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:37.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:37.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:37.34#ibcon#enter wrdev, iclass 16, count 0 2006.258.01:06:37.34#ibcon#first serial, iclass 16, count 0 2006.258.01:06:37.34#ibcon#enter sib2, iclass 16, count 0 2006.258.01:06:37.34#ibcon#flushed, iclass 16, count 0 2006.258.01:06:37.34#ibcon#about to write, iclass 16, count 0 2006.258.01:06:37.34#ibcon#wrote, iclass 16, count 0 2006.258.01:06:37.34#ibcon#about to read 3, iclass 16, count 0 2006.258.01:06:37.36#ibcon#read 3, iclass 16, count 0 2006.258.01:06:37.36#ibcon#about to read 4, iclass 16, count 0 2006.258.01:06:37.36#ibcon#read 4, iclass 16, count 0 2006.258.01:06:37.36#ibcon#about to read 5, iclass 16, count 0 2006.258.01:06:37.36#ibcon#read 5, iclass 16, count 0 2006.258.01:06:37.36#ibcon#about to read 6, iclass 16, count 0 2006.258.01:06:37.36#ibcon#read 6, iclass 16, count 0 2006.258.01:06:37.36#ibcon#end of sib2, iclass 16, count 0 2006.258.01:06:37.36#ibcon#*mode == 0, iclass 16, count 0 2006.258.01:06:37.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.01:06:37.36#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.01:06:37.36#ibcon#*before write, iclass 16, count 0 2006.258.01:06:37.36#ibcon#enter sib2, iclass 16, count 0 2006.258.01:06:37.36#ibcon#flushed, iclass 16, count 0 2006.258.01:06:37.36#ibcon#about to write, iclass 16, count 0 2006.258.01:06:37.36#ibcon#wrote, iclass 16, count 0 2006.258.01:06:37.36#ibcon#about to read 3, iclass 16, count 0 2006.258.01:06:37.41#ibcon#read 3, iclass 16, count 0 2006.258.01:06:37.41#ibcon#about to read 4, iclass 16, count 0 2006.258.01:06:37.41#ibcon#read 4, iclass 16, count 0 2006.258.01:06:37.41#ibcon#about to read 5, iclass 16, count 0 2006.258.01:06:37.41#ibcon#read 5, iclass 16, count 0 2006.258.01:06:37.41#ibcon#about to read 6, iclass 16, count 0 2006.258.01:06:37.41#ibcon#read 6, iclass 16, count 0 2006.258.01:06:37.41#ibcon#end of sib2, iclass 16, count 0 2006.258.01:06:37.41#ibcon#*after write, iclass 16, count 0 2006.258.01:06:37.41#ibcon#*before return 0, iclass 16, count 0 2006.258.01:06:37.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:37.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:37.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.01:06:37.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.01:06:37.41$vck44/va=1,8 2006.258.01:06:37.41#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.258.01:06:37.41#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.258.01:06:37.41#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:37.41#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:37.41#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:37.41#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:37.41#ibcon#enter wrdev, iclass 18, count 2 2006.258.01:06:37.41#ibcon#first serial, iclass 18, count 2 2006.258.01:06:37.41#ibcon#enter sib2, iclass 18, count 2 2006.258.01:06:37.41#ibcon#flushed, iclass 18, count 2 2006.258.01:06:37.41#ibcon#about to write, iclass 18, count 2 2006.258.01:06:37.41#ibcon#wrote, iclass 18, count 2 2006.258.01:06:37.41#ibcon#about to read 3, iclass 18, count 2 2006.258.01:06:37.43#ibcon#read 3, iclass 18, count 2 2006.258.01:06:37.43#ibcon#about to read 4, iclass 18, count 2 2006.258.01:06:37.43#ibcon#read 4, iclass 18, count 2 2006.258.01:06:37.43#ibcon#about to read 5, iclass 18, count 2 2006.258.01:06:37.43#ibcon#read 5, iclass 18, count 2 2006.258.01:06:37.43#ibcon#about to read 6, iclass 18, count 2 2006.258.01:06:37.43#ibcon#read 6, iclass 18, count 2 2006.258.01:06:37.43#ibcon#end of sib2, iclass 18, count 2 2006.258.01:06:37.43#ibcon#*mode == 0, iclass 18, count 2 2006.258.01:06:37.43#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.258.01:06:37.43#ibcon#[25=AT01-08\r\n] 2006.258.01:06:37.43#ibcon#*before write, iclass 18, count 2 2006.258.01:06:37.43#ibcon#enter sib2, iclass 18, count 2 2006.258.01:06:37.43#ibcon#flushed, iclass 18, count 2 2006.258.01:06:37.43#ibcon#about to write, iclass 18, count 2 2006.258.01:06:37.43#ibcon#wrote, iclass 18, count 2 2006.258.01:06:37.43#ibcon#about to read 3, iclass 18, count 2 2006.258.01:06:37.46#ibcon#read 3, iclass 18, count 2 2006.258.01:06:37.46#ibcon#about to read 4, iclass 18, count 2 2006.258.01:06:37.46#ibcon#read 4, iclass 18, count 2 2006.258.01:06:37.46#ibcon#about to read 5, iclass 18, count 2 2006.258.01:06:37.46#ibcon#read 5, iclass 18, count 2 2006.258.01:06:37.46#ibcon#about to read 6, iclass 18, count 2 2006.258.01:06:37.46#ibcon#read 6, iclass 18, count 2 2006.258.01:06:37.46#ibcon#end of sib2, iclass 18, count 2 2006.258.01:06:37.46#ibcon#*after write, iclass 18, count 2 2006.258.01:06:37.46#ibcon#*before return 0, iclass 18, count 2 2006.258.01:06:37.46#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:37.46#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:37.46#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.258.01:06:37.46#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:37.46#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:37.58#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:37.58#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:37.58#ibcon#enter wrdev, iclass 18, count 0 2006.258.01:06:37.58#ibcon#first serial, iclass 18, count 0 2006.258.01:06:37.58#ibcon#enter sib2, iclass 18, count 0 2006.258.01:06:37.58#ibcon#flushed, iclass 18, count 0 2006.258.01:06:37.58#ibcon#about to write, iclass 18, count 0 2006.258.01:06:37.58#ibcon#wrote, iclass 18, count 0 2006.258.01:06:37.58#ibcon#about to read 3, iclass 18, count 0 2006.258.01:06:37.60#ibcon#read 3, iclass 18, count 0 2006.258.01:06:37.60#ibcon#about to read 4, iclass 18, count 0 2006.258.01:06:37.60#ibcon#read 4, iclass 18, count 0 2006.258.01:06:37.60#ibcon#about to read 5, iclass 18, count 0 2006.258.01:06:37.60#ibcon#read 5, iclass 18, count 0 2006.258.01:06:37.60#ibcon#about to read 6, iclass 18, count 0 2006.258.01:06:37.60#ibcon#read 6, iclass 18, count 0 2006.258.01:06:37.60#ibcon#end of sib2, iclass 18, count 0 2006.258.01:06:37.60#ibcon#*mode == 0, iclass 18, count 0 2006.258.01:06:37.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.01:06:37.60#ibcon#[25=USB\r\n] 2006.258.01:06:37.60#ibcon#*before write, iclass 18, count 0 2006.258.01:06:37.60#ibcon#enter sib2, iclass 18, count 0 2006.258.01:06:37.60#ibcon#flushed, iclass 18, count 0 2006.258.01:06:37.60#ibcon#about to write, iclass 18, count 0 2006.258.01:06:37.60#ibcon#wrote, iclass 18, count 0 2006.258.01:06:37.60#ibcon#about to read 3, iclass 18, count 0 2006.258.01:06:37.63#ibcon#read 3, iclass 18, count 0 2006.258.01:06:37.63#ibcon#about to read 4, iclass 18, count 0 2006.258.01:06:37.63#ibcon#read 4, iclass 18, count 0 2006.258.01:06:37.63#ibcon#about to read 5, iclass 18, count 0 2006.258.01:06:37.63#ibcon#read 5, iclass 18, count 0 2006.258.01:06:37.63#ibcon#about to read 6, iclass 18, count 0 2006.258.01:06:37.63#ibcon#read 6, iclass 18, count 0 2006.258.01:06:37.63#ibcon#end of sib2, iclass 18, count 0 2006.258.01:06:37.63#ibcon#*after write, iclass 18, count 0 2006.258.01:06:37.63#ibcon#*before return 0, iclass 18, count 0 2006.258.01:06:37.63#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:37.63#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:37.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.01:06:37.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.01:06:37.63$vck44/valo=2,534.99 2006.258.01:06:37.63#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.01:06:37.63#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.01:06:37.63#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:37.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:37.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:37.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:37.63#ibcon#enter wrdev, iclass 20, count 0 2006.258.01:06:37.63#ibcon#first serial, iclass 20, count 0 2006.258.01:06:37.63#ibcon#enter sib2, iclass 20, count 0 2006.258.01:06:37.63#ibcon#flushed, iclass 20, count 0 2006.258.01:06:37.63#ibcon#about to write, iclass 20, count 0 2006.258.01:06:37.63#ibcon#wrote, iclass 20, count 0 2006.258.01:06:37.63#ibcon#about to read 3, iclass 20, count 0 2006.258.01:06:37.65#ibcon#read 3, iclass 20, count 0 2006.258.01:06:37.65#ibcon#about to read 4, iclass 20, count 0 2006.258.01:06:37.65#ibcon#read 4, iclass 20, count 0 2006.258.01:06:37.65#ibcon#about to read 5, iclass 20, count 0 2006.258.01:06:37.65#ibcon#read 5, iclass 20, count 0 2006.258.01:06:37.65#ibcon#about to read 6, iclass 20, count 0 2006.258.01:06:37.65#ibcon#read 6, iclass 20, count 0 2006.258.01:06:37.65#ibcon#end of sib2, iclass 20, count 0 2006.258.01:06:37.65#ibcon#*mode == 0, iclass 20, count 0 2006.258.01:06:37.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.01:06:37.65#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.01:06:37.65#ibcon#*before write, iclass 20, count 0 2006.258.01:06:37.65#ibcon#enter sib2, iclass 20, count 0 2006.258.01:06:37.65#ibcon#flushed, iclass 20, count 0 2006.258.01:06:37.65#ibcon#about to write, iclass 20, count 0 2006.258.01:06:37.65#ibcon#wrote, iclass 20, count 0 2006.258.01:06:37.65#ibcon#about to read 3, iclass 20, count 0 2006.258.01:06:37.69#ibcon#read 3, iclass 20, count 0 2006.258.01:06:37.69#ibcon#about to read 4, iclass 20, count 0 2006.258.01:06:37.69#ibcon#read 4, iclass 20, count 0 2006.258.01:06:37.69#ibcon#about to read 5, iclass 20, count 0 2006.258.01:06:37.69#ibcon#read 5, iclass 20, count 0 2006.258.01:06:37.69#ibcon#about to read 6, iclass 20, count 0 2006.258.01:06:37.69#ibcon#read 6, iclass 20, count 0 2006.258.01:06:37.69#ibcon#end of sib2, iclass 20, count 0 2006.258.01:06:37.69#ibcon#*after write, iclass 20, count 0 2006.258.01:06:37.69#ibcon#*before return 0, iclass 20, count 0 2006.258.01:06:37.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:37.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:37.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.01:06:37.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.01:06:37.69$vck44/va=2,7 2006.258.01:06:37.69#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.01:06:37.69#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.01:06:37.69#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:37.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:37.75#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:37.75#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:37.75#ibcon#enter wrdev, iclass 22, count 2 2006.258.01:06:37.75#ibcon#first serial, iclass 22, count 2 2006.258.01:06:37.75#ibcon#enter sib2, iclass 22, count 2 2006.258.01:06:37.75#ibcon#flushed, iclass 22, count 2 2006.258.01:06:37.75#ibcon#about to write, iclass 22, count 2 2006.258.01:06:37.75#ibcon#wrote, iclass 22, count 2 2006.258.01:06:37.75#ibcon#about to read 3, iclass 22, count 2 2006.258.01:06:37.77#ibcon#read 3, iclass 22, count 2 2006.258.01:06:37.77#ibcon#about to read 4, iclass 22, count 2 2006.258.01:06:37.77#ibcon#read 4, iclass 22, count 2 2006.258.01:06:37.77#ibcon#about to read 5, iclass 22, count 2 2006.258.01:06:37.77#ibcon#read 5, iclass 22, count 2 2006.258.01:06:37.77#ibcon#about to read 6, iclass 22, count 2 2006.258.01:06:37.77#ibcon#read 6, iclass 22, count 2 2006.258.01:06:37.77#ibcon#end of sib2, iclass 22, count 2 2006.258.01:06:37.77#ibcon#*mode == 0, iclass 22, count 2 2006.258.01:06:37.77#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.01:06:37.77#ibcon#[25=AT02-07\r\n] 2006.258.01:06:37.77#ibcon#*before write, iclass 22, count 2 2006.258.01:06:37.77#ibcon#enter sib2, iclass 22, count 2 2006.258.01:06:37.77#ibcon#flushed, iclass 22, count 2 2006.258.01:06:37.77#ibcon#about to write, iclass 22, count 2 2006.258.01:06:37.77#ibcon#wrote, iclass 22, count 2 2006.258.01:06:37.77#ibcon#about to read 3, iclass 22, count 2 2006.258.01:06:37.80#ibcon#read 3, iclass 22, count 2 2006.258.01:06:37.80#ibcon#about to read 4, iclass 22, count 2 2006.258.01:06:37.80#ibcon#read 4, iclass 22, count 2 2006.258.01:06:37.80#ibcon#about to read 5, iclass 22, count 2 2006.258.01:06:37.80#ibcon#read 5, iclass 22, count 2 2006.258.01:06:37.80#ibcon#about to read 6, iclass 22, count 2 2006.258.01:06:37.80#ibcon#read 6, iclass 22, count 2 2006.258.01:06:37.80#ibcon#end of sib2, iclass 22, count 2 2006.258.01:06:37.80#ibcon#*after write, iclass 22, count 2 2006.258.01:06:37.80#ibcon#*before return 0, iclass 22, count 2 2006.258.01:06:37.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:37.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:37.80#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.01:06:37.80#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:37.80#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:37.92#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:37.92#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:37.92#ibcon#enter wrdev, iclass 22, count 0 2006.258.01:06:37.92#ibcon#first serial, iclass 22, count 0 2006.258.01:06:37.92#ibcon#enter sib2, iclass 22, count 0 2006.258.01:06:37.92#ibcon#flushed, iclass 22, count 0 2006.258.01:06:37.92#ibcon#about to write, iclass 22, count 0 2006.258.01:06:37.92#ibcon#wrote, iclass 22, count 0 2006.258.01:06:37.92#ibcon#about to read 3, iclass 22, count 0 2006.258.01:06:37.94#ibcon#read 3, iclass 22, count 0 2006.258.01:06:37.94#ibcon#about to read 4, iclass 22, count 0 2006.258.01:06:37.94#ibcon#read 4, iclass 22, count 0 2006.258.01:06:37.94#ibcon#about to read 5, iclass 22, count 0 2006.258.01:06:37.94#ibcon#read 5, iclass 22, count 0 2006.258.01:06:37.94#ibcon#about to read 6, iclass 22, count 0 2006.258.01:06:37.94#ibcon#read 6, iclass 22, count 0 2006.258.01:06:37.94#ibcon#end of sib2, iclass 22, count 0 2006.258.01:06:37.94#ibcon#*mode == 0, iclass 22, count 0 2006.258.01:06:37.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.01:06:37.94#ibcon#[25=USB\r\n] 2006.258.01:06:37.94#ibcon#*before write, iclass 22, count 0 2006.258.01:06:37.94#ibcon#enter sib2, iclass 22, count 0 2006.258.01:06:37.94#ibcon#flushed, iclass 22, count 0 2006.258.01:06:37.94#ibcon#about to write, iclass 22, count 0 2006.258.01:06:37.94#ibcon#wrote, iclass 22, count 0 2006.258.01:06:37.94#ibcon#about to read 3, iclass 22, count 0 2006.258.01:06:37.97#ibcon#read 3, iclass 22, count 0 2006.258.01:06:37.97#ibcon#about to read 4, iclass 22, count 0 2006.258.01:06:37.97#ibcon#read 4, iclass 22, count 0 2006.258.01:06:37.97#ibcon#about to read 5, iclass 22, count 0 2006.258.01:06:37.97#ibcon#read 5, iclass 22, count 0 2006.258.01:06:37.97#ibcon#about to read 6, iclass 22, count 0 2006.258.01:06:37.97#ibcon#read 6, iclass 22, count 0 2006.258.01:06:37.97#ibcon#end of sib2, iclass 22, count 0 2006.258.01:06:37.97#ibcon#*after write, iclass 22, count 0 2006.258.01:06:37.97#ibcon#*before return 0, iclass 22, count 0 2006.258.01:06:37.97#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:37.97#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:37.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.01:06:37.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.01:06:37.97$vck44/valo=3,564.99 2006.258.01:06:37.97#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.01:06:37.97#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.01:06:37.97#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:37.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:37.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:37.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:37.97#ibcon#enter wrdev, iclass 24, count 0 2006.258.01:06:37.97#ibcon#first serial, iclass 24, count 0 2006.258.01:06:37.97#ibcon#enter sib2, iclass 24, count 0 2006.258.01:06:37.97#ibcon#flushed, iclass 24, count 0 2006.258.01:06:37.97#ibcon#about to write, iclass 24, count 0 2006.258.01:06:37.97#ibcon#wrote, iclass 24, count 0 2006.258.01:06:37.97#ibcon#about to read 3, iclass 24, count 0 2006.258.01:06:37.99#ibcon#read 3, iclass 24, count 0 2006.258.01:06:37.99#ibcon#about to read 4, iclass 24, count 0 2006.258.01:06:37.99#ibcon#read 4, iclass 24, count 0 2006.258.01:06:37.99#ibcon#about to read 5, iclass 24, count 0 2006.258.01:06:37.99#ibcon#read 5, iclass 24, count 0 2006.258.01:06:37.99#ibcon#about to read 6, iclass 24, count 0 2006.258.01:06:37.99#ibcon#read 6, iclass 24, count 0 2006.258.01:06:37.99#ibcon#end of sib2, iclass 24, count 0 2006.258.01:06:37.99#ibcon#*mode == 0, iclass 24, count 0 2006.258.01:06:37.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.01:06:37.99#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.01:06:37.99#ibcon#*before write, iclass 24, count 0 2006.258.01:06:37.99#ibcon#enter sib2, iclass 24, count 0 2006.258.01:06:37.99#ibcon#flushed, iclass 24, count 0 2006.258.01:06:37.99#ibcon#about to write, iclass 24, count 0 2006.258.01:06:37.99#ibcon#wrote, iclass 24, count 0 2006.258.01:06:37.99#ibcon#about to read 3, iclass 24, count 0 2006.258.01:06:38.03#ibcon#read 3, iclass 24, count 0 2006.258.01:06:38.03#ibcon#about to read 4, iclass 24, count 0 2006.258.01:06:38.03#ibcon#read 4, iclass 24, count 0 2006.258.01:06:38.03#ibcon#about to read 5, iclass 24, count 0 2006.258.01:06:38.03#ibcon#read 5, iclass 24, count 0 2006.258.01:06:38.03#ibcon#about to read 6, iclass 24, count 0 2006.258.01:06:38.03#ibcon#read 6, iclass 24, count 0 2006.258.01:06:38.03#ibcon#end of sib2, iclass 24, count 0 2006.258.01:06:38.03#ibcon#*after write, iclass 24, count 0 2006.258.01:06:38.03#ibcon#*before return 0, iclass 24, count 0 2006.258.01:06:38.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:38.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:38.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.01:06:38.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.01:06:38.03$vck44/va=3,8 2006.258.01:06:38.03#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.01:06:38.03#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.01:06:38.03#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:38.03#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:38.09#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:38.09#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:38.09#ibcon#enter wrdev, iclass 26, count 2 2006.258.01:06:38.09#ibcon#first serial, iclass 26, count 2 2006.258.01:06:38.09#ibcon#enter sib2, iclass 26, count 2 2006.258.01:06:38.09#ibcon#flushed, iclass 26, count 2 2006.258.01:06:38.09#ibcon#about to write, iclass 26, count 2 2006.258.01:06:38.09#ibcon#wrote, iclass 26, count 2 2006.258.01:06:38.09#ibcon#about to read 3, iclass 26, count 2 2006.258.01:06:38.11#ibcon#read 3, iclass 26, count 2 2006.258.01:06:38.11#ibcon#about to read 4, iclass 26, count 2 2006.258.01:06:38.11#ibcon#read 4, iclass 26, count 2 2006.258.01:06:38.11#ibcon#about to read 5, iclass 26, count 2 2006.258.01:06:38.11#ibcon#read 5, iclass 26, count 2 2006.258.01:06:38.11#ibcon#about to read 6, iclass 26, count 2 2006.258.01:06:38.11#ibcon#read 6, iclass 26, count 2 2006.258.01:06:38.11#ibcon#end of sib2, iclass 26, count 2 2006.258.01:06:38.11#ibcon#*mode == 0, iclass 26, count 2 2006.258.01:06:38.11#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.01:06:38.11#ibcon#[25=AT03-08\r\n] 2006.258.01:06:38.11#ibcon#*before write, iclass 26, count 2 2006.258.01:06:38.11#ibcon#enter sib2, iclass 26, count 2 2006.258.01:06:38.11#ibcon#flushed, iclass 26, count 2 2006.258.01:06:38.11#ibcon#about to write, iclass 26, count 2 2006.258.01:06:38.11#ibcon#wrote, iclass 26, count 2 2006.258.01:06:38.11#ibcon#about to read 3, iclass 26, count 2 2006.258.01:06:38.14#ibcon#read 3, iclass 26, count 2 2006.258.01:06:38.14#ibcon#about to read 4, iclass 26, count 2 2006.258.01:06:38.14#ibcon#read 4, iclass 26, count 2 2006.258.01:06:38.14#ibcon#about to read 5, iclass 26, count 2 2006.258.01:06:38.14#ibcon#read 5, iclass 26, count 2 2006.258.01:06:38.14#ibcon#about to read 6, iclass 26, count 2 2006.258.01:06:38.14#ibcon#read 6, iclass 26, count 2 2006.258.01:06:38.14#ibcon#end of sib2, iclass 26, count 2 2006.258.01:06:38.14#ibcon#*after write, iclass 26, count 2 2006.258.01:06:38.14#ibcon#*before return 0, iclass 26, count 2 2006.258.01:06:38.14#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:38.14#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:38.14#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.01:06:38.14#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:38.14#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:38.26#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:38.26#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:38.26#ibcon#enter wrdev, iclass 26, count 0 2006.258.01:06:38.26#ibcon#first serial, iclass 26, count 0 2006.258.01:06:38.26#ibcon#enter sib2, iclass 26, count 0 2006.258.01:06:38.26#ibcon#flushed, iclass 26, count 0 2006.258.01:06:38.26#ibcon#about to write, iclass 26, count 0 2006.258.01:06:38.26#ibcon#wrote, iclass 26, count 0 2006.258.01:06:38.26#ibcon#about to read 3, iclass 26, count 0 2006.258.01:06:38.28#ibcon#read 3, iclass 26, count 0 2006.258.01:06:38.28#ibcon#about to read 4, iclass 26, count 0 2006.258.01:06:38.28#ibcon#read 4, iclass 26, count 0 2006.258.01:06:38.28#ibcon#about to read 5, iclass 26, count 0 2006.258.01:06:38.28#ibcon#read 5, iclass 26, count 0 2006.258.01:06:38.28#ibcon#about to read 6, iclass 26, count 0 2006.258.01:06:38.28#ibcon#read 6, iclass 26, count 0 2006.258.01:06:38.28#ibcon#end of sib2, iclass 26, count 0 2006.258.01:06:38.28#ibcon#*mode == 0, iclass 26, count 0 2006.258.01:06:38.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.01:06:38.28#ibcon#[25=USB\r\n] 2006.258.01:06:38.28#ibcon#*before write, iclass 26, count 0 2006.258.01:06:38.28#ibcon#enter sib2, iclass 26, count 0 2006.258.01:06:38.28#ibcon#flushed, iclass 26, count 0 2006.258.01:06:38.28#ibcon#about to write, iclass 26, count 0 2006.258.01:06:38.28#ibcon#wrote, iclass 26, count 0 2006.258.01:06:38.28#ibcon#about to read 3, iclass 26, count 0 2006.258.01:06:38.31#ibcon#read 3, iclass 26, count 0 2006.258.01:06:38.31#ibcon#about to read 4, iclass 26, count 0 2006.258.01:06:38.31#ibcon#read 4, iclass 26, count 0 2006.258.01:06:38.31#ibcon#about to read 5, iclass 26, count 0 2006.258.01:06:38.31#ibcon#read 5, iclass 26, count 0 2006.258.01:06:38.31#ibcon#about to read 6, iclass 26, count 0 2006.258.01:06:38.31#ibcon#read 6, iclass 26, count 0 2006.258.01:06:38.31#ibcon#end of sib2, iclass 26, count 0 2006.258.01:06:38.31#ibcon#*after write, iclass 26, count 0 2006.258.01:06:38.31#ibcon#*before return 0, iclass 26, count 0 2006.258.01:06:38.31#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:38.31#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:38.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.01:06:38.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.01:06:38.31$vck44/valo=4,624.99 2006.258.01:06:38.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.01:06:38.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.01:06:38.31#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:38.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:38.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:38.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:38.31#ibcon#enter wrdev, iclass 28, count 0 2006.258.01:06:38.31#ibcon#first serial, iclass 28, count 0 2006.258.01:06:38.31#ibcon#enter sib2, iclass 28, count 0 2006.258.01:06:38.31#ibcon#flushed, iclass 28, count 0 2006.258.01:06:38.31#ibcon#about to write, iclass 28, count 0 2006.258.01:06:38.31#ibcon#wrote, iclass 28, count 0 2006.258.01:06:38.31#ibcon#about to read 3, iclass 28, count 0 2006.258.01:06:38.33#ibcon#read 3, iclass 28, count 0 2006.258.01:06:38.33#ibcon#about to read 4, iclass 28, count 0 2006.258.01:06:38.33#ibcon#read 4, iclass 28, count 0 2006.258.01:06:38.33#ibcon#about to read 5, iclass 28, count 0 2006.258.01:06:38.33#ibcon#read 5, iclass 28, count 0 2006.258.01:06:38.33#ibcon#about to read 6, iclass 28, count 0 2006.258.01:06:38.33#ibcon#read 6, iclass 28, count 0 2006.258.01:06:38.33#ibcon#end of sib2, iclass 28, count 0 2006.258.01:06:38.33#ibcon#*mode == 0, iclass 28, count 0 2006.258.01:06:38.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.01:06:38.33#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.01:06:38.33#ibcon#*before write, iclass 28, count 0 2006.258.01:06:38.33#ibcon#enter sib2, iclass 28, count 0 2006.258.01:06:38.33#ibcon#flushed, iclass 28, count 0 2006.258.01:06:38.33#ibcon#about to write, iclass 28, count 0 2006.258.01:06:38.33#ibcon#wrote, iclass 28, count 0 2006.258.01:06:38.33#ibcon#about to read 3, iclass 28, count 0 2006.258.01:06:38.37#ibcon#read 3, iclass 28, count 0 2006.258.01:06:38.37#ibcon#about to read 4, iclass 28, count 0 2006.258.01:06:38.37#ibcon#read 4, iclass 28, count 0 2006.258.01:06:38.37#ibcon#about to read 5, iclass 28, count 0 2006.258.01:06:38.37#ibcon#read 5, iclass 28, count 0 2006.258.01:06:38.37#ibcon#about to read 6, iclass 28, count 0 2006.258.01:06:38.37#ibcon#read 6, iclass 28, count 0 2006.258.01:06:38.37#ibcon#end of sib2, iclass 28, count 0 2006.258.01:06:38.37#ibcon#*after write, iclass 28, count 0 2006.258.01:06:38.37#ibcon#*before return 0, iclass 28, count 0 2006.258.01:06:38.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:38.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:38.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.01:06:38.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.01:06:38.37$vck44/va=4,7 2006.258.01:06:38.37#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.01:06:38.37#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.01:06:38.37#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:38.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:38.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:38.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:38.43#ibcon#enter wrdev, iclass 30, count 2 2006.258.01:06:38.43#ibcon#first serial, iclass 30, count 2 2006.258.01:06:38.43#ibcon#enter sib2, iclass 30, count 2 2006.258.01:06:38.43#ibcon#flushed, iclass 30, count 2 2006.258.01:06:38.43#ibcon#about to write, iclass 30, count 2 2006.258.01:06:38.43#ibcon#wrote, iclass 30, count 2 2006.258.01:06:38.43#ibcon#about to read 3, iclass 30, count 2 2006.258.01:06:38.45#ibcon#read 3, iclass 30, count 2 2006.258.01:06:38.45#ibcon#about to read 4, iclass 30, count 2 2006.258.01:06:38.45#ibcon#read 4, iclass 30, count 2 2006.258.01:06:38.45#ibcon#about to read 5, iclass 30, count 2 2006.258.01:06:38.45#ibcon#read 5, iclass 30, count 2 2006.258.01:06:38.45#ibcon#about to read 6, iclass 30, count 2 2006.258.01:06:38.45#ibcon#read 6, iclass 30, count 2 2006.258.01:06:38.45#ibcon#end of sib2, iclass 30, count 2 2006.258.01:06:38.45#ibcon#*mode == 0, iclass 30, count 2 2006.258.01:06:38.45#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.01:06:38.45#ibcon#[25=AT04-07\r\n] 2006.258.01:06:38.45#ibcon#*before write, iclass 30, count 2 2006.258.01:06:38.45#ibcon#enter sib2, iclass 30, count 2 2006.258.01:06:38.45#ibcon#flushed, iclass 30, count 2 2006.258.01:06:38.45#ibcon#about to write, iclass 30, count 2 2006.258.01:06:38.45#ibcon#wrote, iclass 30, count 2 2006.258.01:06:38.45#ibcon#about to read 3, iclass 30, count 2 2006.258.01:06:38.48#ibcon#read 3, iclass 30, count 2 2006.258.01:06:38.48#ibcon#about to read 4, iclass 30, count 2 2006.258.01:06:38.48#ibcon#read 4, iclass 30, count 2 2006.258.01:06:38.48#ibcon#about to read 5, iclass 30, count 2 2006.258.01:06:38.48#ibcon#read 5, iclass 30, count 2 2006.258.01:06:38.48#ibcon#about to read 6, iclass 30, count 2 2006.258.01:06:38.48#ibcon#read 6, iclass 30, count 2 2006.258.01:06:38.48#ibcon#end of sib2, iclass 30, count 2 2006.258.01:06:38.48#ibcon#*after write, iclass 30, count 2 2006.258.01:06:38.49#ibcon#*before return 0, iclass 30, count 2 2006.258.01:06:38.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:38.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:38.49#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.01:06:38.49#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:38.49#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:38.61#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:38.61#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:38.61#ibcon#enter wrdev, iclass 30, count 0 2006.258.01:06:38.61#ibcon#first serial, iclass 30, count 0 2006.258.01:06:38.61#ibcon#enter sib2, iclass 30, count 0 2006.258.01:06:38.61#ibcon#flushed, iclass 30, count 0 2006.258.01:06:38.61#ibcon#about to write, iclass 30, count 0 2006.258.01:06:38.61#ibcon#wrote, iclass 30, count 0 2006.258.01:06:38.61#ibcon#about to read 3, iclass 30, count 0 2006.258.01:06:38.63#ibcon#read 3, iclass 30, count 0 2006.258.01:06:38.63#ibcon#about to read 4, iclass 30, count 0 2006.258.01:06:38.63#ibcon#read 4, iclass 30, count 0 2006.258.01:06:38.63#ibcon#about to read 5, iclass 30, count 0 2006.258.01:06:38.63#ibcon#read 5, iclass 30, count 0 2006.258.01:06:38.63#ibcon#about to read 6, iclass 30, count 0 2006.258.01:06:38.63#ibcon#read 6, iclass 30, count 0 2006.258.01:06:38.63#ibcon#end of sib2, iclass 30, count 0 2006.258.01:06:38.63#ibcon#*mode == 0, iclass 30, count 0 2006.258.01:06:38.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.01:06:38.63#ibcon#[25=USB\r\n] 2006.258.01:06:38.63#ibcon#*before write, iclass 30, count 0 2006.258.01:06:38.63#ibcon#enter sib2, iclass 30, count 0 2006.258.01:06:38.63#ibcon#flushed, iclass 30, count 0 2006.258.01:06:38.63#ibcon#about to write, iclass 30, count 0 2006.258.01:06:38.63#ibcon#wrote, iclass 30, count 0 2006.258.01:06:38.63#ibcon#about to read 3, iclass 30, count 0 2006.258.01:06:38.66#ibcon#read 3, iclass 30, count 0 2006.258.01:06:38.66#ibcon#about to read 4, iclass 30, count 0 2006.258.01:06:38.66#ibcon#read 4, iclass 30, count 0 2006.258.01:06:38.66#ibcon#about to read 5, iclass 30, count 0 2006.258.01:06:38.66#ibcon#read 5, iclass 30, count 0 2006.258.01:06:38.66#ibcon#about to read 6, iclass 30, count 0 2006.258.01:06:38.66#ibcon#read 6, iclass 30, count 0 2006.258.01:06:38.66#ibcon#end of sib2, iclass 30, count 0 2006.258.01:06:38.66#ibcon#*after write, iclass 30, count 0 2006.258.01:06:38.66#ibcon#*before return 0, iclass 30, count 0 2006.258.01:06:38.66#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:38.66#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:38.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.01:06:38.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.01:06:38.66$vck44/valo=5,734.99 2006.258.01:06:38.66#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.258.01:06:38.66#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.258.01:06:38.66#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:38.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:38.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:38.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:38.66#ibcon#enter wrdev, iclass 32, count 0 2006.258.01:06:38.66#ibcon#first serial, iclass 32, count 0 2006.258.01:06:38.66#ibcon#enter sib2, iclass 32, count 0 2006.258.01:06:38.66#ibcon#flushed, iclass 32, count 0 2006.258.01:06:38.66#ibcon#about to write, iclass 32, count 0 2006.258.01:06:38.66#ibcon#wrote, iclass 32, count 0 2006.258.01:06:38.66#ibcon#about to read 3, iclass 32, count 0 2006.258.01:06:38.68#ibcon#read 3, iclass 32, count 0 2006.258.01:06:38.68#ibcon#about to read 4, iclass 32, count 0 2006.258.01:06:38.68#ibcon#read 4, iclass 32, count 0 2006.258.01:06:38.68#ibcon#about to read 5, iclass 32, count 0 2006.258.01:06:38.68#ibcon#read 5, iclass 32, count 0 2006.258.01:06:38.68#ibcon#about to read 6, iclass 32, count 0 2006.258.01:06:38.68#ibcon#read 6, iclass 32, count 0 2006.258.01:06:38.68#ibcon#end of sib2, iclass 32, count 0 2006.258.01:06:38.68#ibcon#*mode == 0, iclass 32, count 0 2006.258.01:06:38.68#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.01:06:38.68#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.01:06:38.68#ibcon#*before write, iclass 32, count 0 2006.258.01:06:38.68#ibcon#enter sib2, iclass 32, count 0 2006.258.01:06:38.68#ibcon#flushed, iclass 32, count 0 2006.258.01:06:38.68#ibcon#about to write, iclass 32, count 0 2006.258.01:06:38.68#ibcon#wrote, iclass 32, count 0 2006.258.01:06:38.68#ibcon#about to read 3, iclass 32, count 0 2006.258.01:06:38.72#ibcon#read 3, iclass 32, count 0 2006.258.01:06:38.72#ibcon#about to read 4, iclass 32, count 0 2006.258.01:06:38.72#ibcon#read 4, iclass 32, count 0 2006.258.01:06:38.72#ibcon#about to read 5, iclass 32, count 0 2006.258.01:06:38.72#ibcon#read 5, iclass 32, count 0 2006.258.01:06:38.72#ibcon#about to read 6, iclass 32, count 0 2006.258.01:06:38.72#ibcon#read 6, iclass 32, count 0 2006.258.01:06:38.72#ibcon#end of sib2, iclass 32, count 0 2006.258.01:06:38.72#ibcon#*after write, iclass 32, count 0 2006.258.01:06:38.72#ibcon#*before return 0, iclass 32, count 0 2006.258.01:06:38.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:38.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:38.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.01:06:38.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.01:06:38.72$vck44/va=5,4 2006.258.01:06:38.72#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.258.01:06:38.72#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.258.01:06:38.72#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:38.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:38.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:38.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:38.78#ibcon#enter wrdev, iclass 34, count 2 2006.258.01:06:38.78#ibcon#first serial, iclass 34, count 2 2006.258.01:06:38.78#ibcon#enter sib2, iclass 34, count 2 2006.258.01:06:38.78#ibcon#flushed, iclass 34, count 2 2006.258.01:06:38.78#ibcon#about to write, iclass 34, count 2 2006.258.01:06:38.78#ibcon#wrote, iclass 34, count 2 2006.258.01:06:38.78#ibcon#about to read 3, iclass 34, count 2 2006.258.01:06:38.80#ibcon#read 3, iclass 34, count 2 2006.258.01:06:38.80#ibcon#about to read 4, iclass 34, count 2 2006.258.01:06:38.80#ibcon#read 4, iclass 34, count 2 2006.258.01:06:38.80#ibcon#about to read 5, iclass 34, count 2 2006.258.01:06:38.80#ibcon#read 5, iclass 34, count 2 2006.258.01:06:38.80#ibcon#about to read 6, iclass 34, count 2 2006.258.01:06:38.80#ibcon#read 6, iclass 34, count 2 2006.258.01:06:38.80#ibcon#end of sib2, iclass 34, count 2 2006.258.01:06:38.80#ibcon#*mode == 0, iclass 34, count 2 2006.258.01:06:38.80#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.258.01:06:38.80#ibcon#[25=AT05-04\r\n] 2006.258.01:06:38.80#ibcon#*before write, iclass 34, count 2 2006.258.01:06:38.80#ibcon#enter sib2, iclass 34, count 2 2006.258.01:06:38.80#ibcon#flushed, iclass 34, count 2 2006.258.01:06:38.80#ibcon#about to write, iclass 34, count 2 2006.258.01:06:38.80#ibcon#wrote, iclass 34, count 2 2006.258.01:06:38.80#ibcon#about to read 3, iclass 34, count 2 2006.258.01:06:38.83#abcon#<5=/02 2.3 8.1 22.68 741016.1\r\n> 2006.258.01:06:38.83#ibcon#read 3, iclass 34, count 2 2006.258.01:06:38.83#ibcon#about to read 4, iclass 34, count 2 2006.258.01:06:38.83#ibcon#read 4, iclass 34, count 2 2006.258.01:06:38.83#ibcon#about to read 5, iclass 34, count 2 2006.258.01:06:38.83#ibcon#read 5, iclass 34, count 2 2006.258.01:06:38.83#ibcon#about to read 6, iclass 34, count 2 2006.258.01:06:38.83#ibcon#read 6, iclass 34, count 2 2006.258.01:06:38.83#ibcon#end of sib2, iclass 34, count 2 2006.258.01:06:38.83#ibcon#*after write, iclass 34, count 2 2006.258.01:06:38.83#ibcon#*before return 0, iclass 34, count 2 2006.258.01:06:38.83#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:38.83#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:38.83#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.258.01:06:38.83#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:38.83#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:38.85#abcon#{5=INTERFACE CLEAR} 2006.258.01:06:38.91#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:06:38.95#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:38.95#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:38.95#ibcon#enter wrdev, iclass 34, count 0 2006.258.01:06:38.95#ibcon#first serial, iclass 34, count 0 2006.258.01:06:38.95#ibcon#enter sib2, iclass 34, count 0 2006.258.01:06:38.95#ibcon#flushed, iclass 34, count 0 2006.258.01:06:38.95#ibcon#about to write, iclass 34, count 0 2006.258.01:06:38.95#ibcon#wrote, iclass 34, count 0 2006.258.01:06:38.95#ibcon#about to read 3, iclass 34, count 0 2006.258.01:06:38.97#ibcon#read 3, iclass 34, count 0 2006.258.01:06:38.97#ibcon#about to read 4, iclass 34, count 0 2006.258.01:06:38.97#ibcon#read 4, iclass 34, count 0 2006.258.01:06:38.97#ibcon#about to read 5, iclass 34, count 0 2006.258.01:06:38.97#ibcon#read 5, iclass 34, count 0 2006.258.01:06:38.97#ibcon#about to read 6, iclass 34, count 0 2006.258.01:06:38.97#ibcon#read 6, iclass 34, count 0 2006.258.01:06:38.97#ibcon#end of sib2, iclass 34, count 0 2006.258.01:06:38.97#ibcon#*mode == 0, iclass 34, count 0 2006.258.01:06:38.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.01:06:38.97#ibcon#[25=USB\r\n] 2006.258.01:06:38.97#ibcon#*before write, iclass 34, count 0 2006.258.01:06:38.97#ibcon#enter sib2, iclass 34, count 0 2006.258.01:06:38.97#ibcon#flushed, iclass 34, count 0 2006.258.01:06:38.97#ibcon#about to write, iclass 34, count 0 2006.258.01:06:38.97#ibcon#wrote, iclass 34, count 0 2006.258.01:06:38.97#ibcon#about to read 3, iclass 34, count 0 2006.258.01:06:39.00#ibcon#read 3, iclass 34, count 0 2006.258.01:06:39.00#ibcon#about to read 4, iclass 34, count 0 2006.258.01:06:39.00#ibcon#read 4, iclass 34, count 0 2006.258.01:06:39.00#ibcon#about to read 5, iclass 34, count 0 2006.258.01:06:39.00#ibcon#read 5, iclass 34, count 0 2006.258.01:06:39.00#ibcon#about to read 6, iclass 34, count 0 2006.258.01:06:39.00#ibcon#read 6, iclass 34, count 0 2006.258.01:06:39.00#ibcon#end of sib2, iclass 34, count 0 2006.258.01:06:39.00#ibcon#*after write, iclass 34, count 0 2006.258.01:06:39.00#ibcon#*before return 0, iclass 34, count 0 2006.258.01:06:39.00#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:39.00#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:39.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.01:06:39.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.01:06:39.00$vck44/valo=6,814.99 2006.258.01:06:39.00#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.01:06:39.00#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.01:06:39.00#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:39.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:39.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:39.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:39.00#ibcon#enter wrdev, iclass 40, count 0 2006.258.01:06:39.00#ibcon#first serial, iclass 40, count 0 2006.258.01:06:39.00#ibcon#enter sib2, iclass 40, count 0 2006.258.01:06:39.00#ibcon#flushed, iclass 40, count 0 2006.258.01:06:39.00#ibcon#about to write, iclass 40, count 0 2006.258.01:06:39.00#ibcon#wrote, iclass 40, count 0 2006.258.01:06:39.00#ibcon#about to read 3, iclass 40, count 0 2006.258.01:06:39.02#ibcon#read 3, iclass 40, count 0 2006.258.01:06:39.02#ibcon#about to read 4, iclass 40, count 0 2006.258.01:06:39.02#ibcon#read 4, iclass 40, count 0 2006.258.01:06:39.02#ibcon#about to read 5, iclass 40, count 0 2006.258.01:06:39.02#ibcon#read 5, iclass 40, count 0 2006.258.01:06:39.02#ibcon#about to read 6, iclass 40, count 0 2006.258.01:06:39.02#ibcon#read 6, iclass 40, count 0 2006.258.01:06:39.02#ibcon#end of sib2, iclass 40, count 0 2006.258.01:06:39.02#ibcon#*mode == 0, iclass 40, count 0 2006.258.01:06:39.02#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.01:06:39.02#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.01:06:39.02#ibcon#*before write, iclass 40, count 0 2006.258.01:06:39.02#ibcon#enter sib2, iclass 40, count 0 2006.258.01:06:39.02#ibcon#flushed, iclass 40, count 0 2006.258.01:06:39.02#ibcon#about to write, iclass 40, count 0 2006.258.01:06:39.02#ibcon#wrote, iclass 40, count 0 2006.258.01:06:39.02#ibcon#about to read 3, iclass 40, count 0 2006.258.01:06:39.06#ibcon#read 3, iclass 40, count 0 2006.258.01:06:39.06#ibcon#about to read 4, iclass 40, count 0 2006.258.01:06:39.06#ibcon#read 4, iclass 40, count 0 2006.258.01:06:39.06#ibcon#about to read 5, iclass 40, count 0 2006.258.01:06:39.06#ibcon#read 5, iclass 40, count 0 2006.258.01:06:39.06#ibcon#about to read 6, iclass 40, count 0 2006.258.01:06:39.06#ibcon#read 6, iclass 40, count 0 2006.258.01:06:39.06#ibcon#end of sib2, iclass 40, count 0 2006.258.01:06:39.06#ibcon#*after write, iclass 40, count 0 2006.258.01:06:39.06#ibcon#*before return 0, iclass 40, count 0 2006.258.01:06:39.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:39.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:39.06#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.01:06:39.06#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.01:06:39.06$vck44/va=6,4 2006.258.01:06:39.06#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.258.01:06:39.06#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.258.01:06:39.06#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:39.06#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:39.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:39.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:39.12#ibcon#enter wrdev, iclass 4, count 2 2006.258.01:06:39.12#ibcon#first serial, iclass 4, count 2 2006.258.01:06:39.12#ibcon#enter sib2, iclass 4, count 2 2006.258.01:06:39.12#ibcon#flushed, iclass 4, count 2 2006.258.01:06:39.12#ibcon#about to write, iclass 4, count 2 2006.258.01:06:39.12#ibcon#wrote, iclass 4, count 2 2006.258.01:06:39.12#ibcon#about to read 3, iclass 4, count 2 2006.258.01:06:39.14#ibcon#read 3, iclass 4, count 2 2006.258.01:06:39.14#ibcon#about to read 4, iclass 4, count 2 2006.258.01:06:39.14#ibcon#read 4, iclass 4, count 2 2006.258.01:06:39.14#ibcon#about to read 5, iclass 4, count 2 2006.258.01:06:39.14#ibcon#read 5, iclass 4, count 2 2006.258.01:06:39.14#ibcon#about to read 6, iclass 4, count 2 2006.258.01:06:39.14#ibcon#read 6, iclass 4, count 2 2006.258.01:06:39.14#ibcon#end of sib2, iclass 4, count 2 2006.258.01:06:39.14#ibcon#*mode == 0, iclass 4, count 2 2006.258.01:06:39.14#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.258.01:06:39.14#ibcon#[25=AT06-04\r\n] 2006.258.01:06:39.14#ibcon#*before write, iclass 4, count 2 2006.258.01:06:39.14#ibcon#enter sib2, iclass 4, count 2 2006.258.01:06:39.14#ibcon#flushed, iclass 4, count 2 2006.258.01:06:39.14#ibcon#about to write, iclass 4, count 2 2006.258.01:06:39.14#ibcon#wrote, iclass 4, count 2 2006.258.01:06:39.14#ibcon#about to read 3, iclass 4, count 2 2006.258.01:06:39.17#ibcon#read 3, iclass 4, count 2 2006.258.01:06:39.17#ibcon#about to read 4, iclass 4, count 2 2006.258.01:06:39.17#ibcon#read 4, iclass 4, count 2 2006.258.01:06:39.17#ibcon#about to read 5, iclass 4, count 2 2006.258.01:06:39.17#ibcon#read 5, iclass 4, count 2 2006.258.01:06:39.17#ibcon#about to read 6, iclass 4, count 2 2006.258.01:06:39.17#ibcon#read 6, iclass 4, count 2 2006.258.01:06:39.17#ibcon#end of sib2, iclass 4, count 2 2006.258.01:06:39.17#ibcon#*after write, iclass 4, count 2 2006.258.01:06:39.17#ibcon#*before return 0, iclass 4, count 2 2006.258.01:06:39.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:39.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:39.17#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.258.01:06:39.17#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:39.17#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:39.29#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:39.29#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:39.29#ibcon#enter wrdev, iclass 4, count 0 2006.258.01:06:39.29#ibcon#first serial, iclass 4, count 0 2006.258.01:06:39.29#ibcon#enter sib2, iclass 4, count 0 2006.258.01:06:39.29#ibcon#flushed, iclass 4, count 0 2006.258.01:06:39.29#ibcon#about to write, iclass 4, count 0 2006.258.01:06:39.29#ibcon#wrote, iclass 4, count 0 2006.258.01:06:39.29#ibcon#about to read 3, iclass 4, count 0 2006.258.01:06:39.31#ibcon#read 3, iclass 4, count 0 2006.258.01:06:39.31#ibcon#about to read 4, iclass 4, count 0 2006.258.01:06:39.31#ibcon#read 4, iclass 4, count 0 2006.258.01:06:39.31#ibcon#about to read 5, iclass 4, count 0 2006.258.01:06:39.31#ibcon#read 5, iclass 4, count 0 2006.258.01:06:39.31#ibcon#about to read 6, iclass 4, count 0 2006.258.01:06:39.31#ibcon#read 6, iclass 4, count 0 2006.258.01:06:39.31#ibcon#end of sib2, iclass 4, count 0 2006.258.01:06:39.31#ibcon#*mode == 0, iclass 4, count 0 2006.258.01:06:39.31#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.01:06:39.31#ibcon#[25=USB\r\n] 2006.258.01:06:39.31#ibcon#*before write, iclass 4, count 0 2006.258.01:06:39.31#ibcon#enter sib2, iclass 4, count 0 2006.258.01:06:39.31#ibcon#flushed, iclass 4, count 0 2006.258.01:06:39.31#ibcon#about to write, iclass 4, count 0 2006.258.01:06:39.31#ibcon#wrote, iclass 4, count 0 2006.258.01:06:39.31#ibcon#about to read 3, iclass 4, count 0 2006.258.01:06:39.34#ibcon#read 3, iclass 4, count 0 2006.258.01:06:39.34#ibcon#about to read 4, iclass 4, count 0 2006.258.01:06:39.34#ibcon#read 4, iclass 4, count 0 2006.258.01:06:39.34#ibcon#about to read 5, iclass 4, count 0 2006.258.01:06:39.34#ibcon#read 5, iclass 4, count 0 2006.258.01:06:39.34#ibcon#about to read 6, iclass 4, count 0 2006.258.01:06:39.34#ibcon#read 6, iclass 4, count 0 2006.258.01:06:39.34#ibcon#end of sib2, iclass 4, count 0 2006.258.01:06:39.34#ibcon#*after write, iclass 4, count 0 2006.258.01:06:39.34#ibcon#*before return 0, iclass 4, count 0 2006.258.01:06:39.34#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:39.34#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:39.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.01:06:39.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.01:06:39.34$vck44/valo=7,864.99 2006.258.01:06:39.34#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.01:06:39.34#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.01:06:39.34#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:39.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:39.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:39.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:39.34#ibcon#enter wrdev, iclass 6, count 0 2006.258.01:06:39.34#ibcon#first serial, iclass 6, count 0 2006.258.01:06:39.34#ibcon#enter sib2, iclass 6, count 0 2006.258.01:06:39.34#ibcon#flushed, iclass 6, count 0 2006.258.01:06:39.34#ibcon#about to write, iclass 6, count 0 2006.258.01:06:39.34#ibcon#wrote, iclass 6, count 0 2006.258.01:06:39.34#ibcon#about to read 3, iclass 6, count 0 2006.258.01:06:39.36#ibcon#read 3, iclass 6, count 0 2006.258.01:06:39.36#ibcon#about to read 4, iclass 6, count 0 2006.258.01:06:39.36#ibcon#read 4, iclass 6, count 0 2006.258.01:06:39.36#ibcon#about to read 5, iclass 6, count 0 2006.258.01:06:39.36#ibcon#read 5, iclass 6, count 0 2006.258.01:06:39.36#ibcon#about to read 6, iclass 6, count 0 2006.258.01:06:39.36#ibcon#read 6, iclass 6, count 0 2006.258.01:06:39.36#ibcon#end of sib2, iclass 6, count 0 2006.258.01:06:39.36#ibcon#*mode == 0, iclass 6, count 0 2006.258.01:06:39.36#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.01:06:39.36#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.01:06:39.36#ibcon#*before write, iclass 6, count 0 2006.258.01:06:39.36#ibcon#enter sib2, iclass 6, count 0 2006.258.01:06:39.36#ibcon#flushed, iclass 6, count 0 2006.258.01:06:39.36#ibcon#about to write, iclass 6, count 0 2006.258.01:06:39.36#ibcon#wrote, iclass 6, count 0 2006.258.01:06:39.36#ibcon#about to read 3, iclass 6, count 0 2006.258.01:06:39.40#ibcon#read 3, iclass 6, count 0 2006.258.01:06:39.40#ibcon#about to read 4, iclass 6, count 0 2006.258.01:06:39.40#ibcon#read 4, iclass 6, count 0 2006.258.01:06:39.40#ibcon#about to read 5, iclass 6, count 0 2006.258.01:06:39.40#ibcon#read 5, iclass 6, count 0 2006.258.01:06:39.40#ibcon#about to read 6, iclass 6, count 0 2006.258.01:06:39.40#ibcon#read 6, iclass 6, count 0 2006.258.01:06:39.40#ibcon#end of sib2, iclass 6, count 0 2006.258.01:06:39.40#ibcon#*after write, iclass 6, count 0 2006.258.01:06:39.40#ibcon#*before return 0, iclass 6, count 0 2006.258.01:06:39.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:39.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:39.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.01:06:39.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.01:06:39.40$vck44/va=7,4 2006.258.01:06:39.40#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.258.01:06:39.40#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.258.01:06:39.40#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:39.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:39.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:39.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:39.46#ibcon#enter wrdev, iclass 10, count 2 2006.258.01:06:39.46#ibcon#first serial, iclass 10, count 2 2006.258.01:06:39.46#ibcon#enter sib2, iclass 10, count 2 2006.258.01:06:39.46#ibcon#flushed, iclass 10, count 2 2006.258.01:06:39.46#ibcon#about to write, iclass 10, count 2 2006.258.01:06:39.46#ibcon#wrote, iclass 10, count 2 2006.258.01:06:39.46#ibcon#about to read 3, iclass 10, count 2 2006.258.01:06:39.48#ibcon#read 3, iclass 10, count 2 2006.258.01:06:39.48#ibcon#about to read 4, iclass 10, count 2 2006.258.01:06:39.48#ibcon#read 4, iclass 10, count 2 2006.258.01:06:39.48#ibcon#about to read 5, iclass 10, count 2 2006.258.01:06:39.48#ibcon#read 5, iclass 10, count 2 2006.258.01:06:39.48#ibcon#about to read 6, iclass 10, count 2 2006.258.01:06:39.48#ibcon#read 6, iclass 10, count 2 2006.258.01:06:39.48#ibcon#end of sib2, iclass 10, count 2 2006.258.01:06:39.48#ibcon#*mode == 0, iclass 10, count 2 2006.258.01:06:39.48#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.258.01:06:39.48#ibcon#[25=AT07-04\r\n] 2006.258.01:06:39.48#ibcon#*before write, iclass 10, count 2 2006.258.01:06:39.48#ibcon#enter sib2, iclass 10, count 2 2006.258.01:06:39.48#ibcon#flushed, iclass 10, count 2 2006.258.01:06:39.48#ibcon#about to write, iclass 10, count 2 2006.258.01:06:39.48#ibcon#wrote, iclass 10, count 2 2006.258.01:06:39.48#ibcon#about to read 3, iclass 10, count 2 2006.258.01:06:39.51#ibcon#read 3, iclass 10, count 2 2006.258.01:06:39.51#ibcon#about to read 4, iclass 10, count 2 2006.258.01:06:39.51#ibcon#read 4, iclass 10, count 2 2006.258.01:06:39.51#ibcon#about to read 5, iclass 10, count 2 2006.258.01:06:39.51#ibcon#read 5, iclass 10, count 2 2006.258.01:06:39.51#ibcon#about to read 6, iclass 10, count 2 2006.258.01:06:39.51#ibcon#read 6, iclass 10, count 2 2006.258.01:06:39.51#ibcon#end of sib2, iclass 10, count 2 2006.258.01:06:39.55#ibcon#*after write, iclass 10, count 2 2006.258.01:06:39.55#ibcon#*before return 0, iclass 10, count 2 2006.258.01:06:39.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:39.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:39.55#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.258.01:06:39.55#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:39.55#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:39.67#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:39.67#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:39.67#ibcon#enter wrdev, iclass 10, count 0 2006.258.01:06:39.67#ibcon#first serial, iclass 10, count 0 2006.258.01:06:39.67#ibcon#enter sib2, iclass 10, count 0 2006.258.01:06:39.67#ibcon#flushed, iclass 10, count 0 2006.258.01:06:39.67#ibcon#about to write, iclass 10, count 0 2006.258.01:06:39.67#ibcon#wrote, iclass 10, count 0 2006.258.01:06:39.67#ibcon#about to read 3, iclass 10, count 0 2006.258.01:06:39.69#ibcon#read 3, iclass 10, count 0 2006.258.01:06:39.69#ibcon#about to read 4, iclass 10, count 0 2006.258.01:06:39.69#ibcon#read 4, iclass 10, count 0 2006.258.01:06:39.69#ibcon#about to read 5, iclass 10, count 0 2006.258.01:06:39.69#ibcon#read 5, iclass 10, count 0 2006.258.01:06:39.69#ibcon#about to read 6, iclass 10, count 0 2006.258.01:06:39.69#ibcon#read 6, iclass 10, count 0 2006.258.01:06:39.69#ibcon#end of sib2, iclass 10, count 0 2006.258.01:06:39.69#ibcon#*mode == 0, iclass 10, count 0 2006.258.01:06:39.69#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.01:06:39.69#ibcon#[25=USB\r\n] 2006.258.01:06:39.69#ibcon#*before write, iclass 10, count 0 2006.258.01:06:39.69#ibcon#enter sib2, iclass 10, count 0 2006.258.01:06:39.69#ibcon#flushed, iclass 10, count 0 2006.258.01:06:39.69#ibcon#about to write, iclass 10, count 0 2006.258.01:06:39.69#ibcon#wrote, iclass 10, count 0 2006.258.01:06:39.69#ibcon#about to read 3, iclass 10, count 0 2006.258.01:06:39.72#ibcon#read 3, iclass 10, count 0 2006.258.01:06:39.72#ibcon#about to read 4, iclass 10, count 0 2006.258.01:06:39.72#ibcon#read 4, iclass 10, count 0 2006.258.01:06:39.72#ibcon#about to read 5, iclass 10, count 0 2006.258.01:06:39.72#ibcon#read 5, iclass 10, count 0 2006.258.01:06:39.72#ibcon#about to read 6, iclass 10, count 0 2006.258.01:06:39.72#ibcon#read 6, iclass 10, count 0 2006.258.01:06:39.72#ibcon#end of sib2, iclass 10, count 0 2006.258.01:06:39.72#ibcon#*after write, iclass 10, count 0 2006.258.01:06:39.72#ibcon#*before return 0, iclass 10, count 0 2006.258.01:06:39.72#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:39.72#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:39.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.01:06:39.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.01:06:39.72$vck44/valo=8,884.99 2006.258.01:06:39.72#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.01:06:39.72#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.01:06:39.72#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:39.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:39.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:39.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:39.72#ibcon#enter wrdev, iclass 12, count 0 2006.258.01:06:39.72#ibcon#first serial, iclass 12, count 0 2006.258.01:06:39.72#ibcon#enter sib2, iclass 12, count 0 2006.258.01:06:39.72#ibcon#flushed, iclass 12, count 0 2006.258.01:06:39.72#ibcon#about to write, iclass 12, count 0 2006.258.01:06:39.72#ibcon#wrote, iclass 12, count 0 2006.258.01:06:39.72#ibcon#about to read 3, iclass 12, count 0 2006.258.01:06:39.74#ibcon#read 3, iclass 12, count 0 2006.258.01:06:39.74#ibcon#about to read 4, iclass 12, count 0 2006.258.01:06:39.74#ibcon#read 4, iclass 12, count 0 2006.258.01:06:39.74#ibcon#about to read 5, iclass 12, count 0 2006.258.01:06:39.74#ibcon#read 5, iclass 12, count 0 2006.258.01:06:39.74#ibcon#about to read 6, iclass 12, count 0 2006.258.01:06:39.74#ibcon#read 6, iclass 12, count 0 2006.258.01:06:39.74#ibcon#end of sib2, iclass 12, count 0 2006.258.01:06:39.74#ibcon#*mode == 0, iclass 12, count 0 2006.258.01:06:39.74#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.01:06:39.74#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.01:06:39.74#ibcon#*before write, iclass 12, count 0 2006.258.01:06:39.74#ibcon#enter sib2, iclass 12, count 0 2006.258.01:06:39.74#ibcon#flushed, iclass 12, count 0 2006.258.01:06:39.74#ibcon#about to write, iclass 12, count 0 2006.258.01:06:39.74#ibcon#wrote, iclass 12, count 0 2006.258.01:06:39.74#ibcon#about to read 3, iclass 12, count 0 2006.258.01:06:39.78#ibcon#read 3, iclass 12, count 0 2006.258.01:06:39.78#ibcon#about to read 4, iclass 12, count 0 2006.258.01:06:39.78#ibcon#read 4, iclass 12, count 0 2006.258.01:06:39.78#ibcon#about to read 5, iclass 12, count 0 2006.258.01:06:39.78#ibcon#read 5, iclass 12, count 0 2006.258.01:06:39.78#ibcon#about to read 6, iclass 12, count 0 2006.258.01:06:39.78#ibcon#read 6, iclass 12, count 0 2006.258.01:06:39.78#ibcon#end of sib2, iclass 12, count 0 2006.258.01:06:39.78#ibcon#*after write, iclass 12, count 0 2006.258.01:06:39.78#ibcon#*before return 0, iclass 12, count 0 2006.258.01:06:39.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:39.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:39.78#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.01:06:39.78#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.01:06:39.78$vck44/va=8,4 2006.258.01:06:39.78#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.258.01:06:39.78#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.258.01:06:39.78#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:39.78#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:06:39.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:06:39.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:06:39.84#ibcon#enter wrdev, iclass 14, count 2 2006.258.01:06:39.84#ibcon#first serial, iclass 14, count 2 2006.258.01:06:39.84#ibcon#enter sib2, iclass 14, count 2 2006.258.01:06:39.84#ibcon#flushed, iclass 14, count 2 2006.258.01:06:39.84#ibcon#about to write, iclass 14, count 2 2006.258.01:06:39.84#ibcon#wrote, iclass 14, count 2 2006.258.01:06:39.84#ibcon#about to read 3, iclass 14, count 2 2006.258.01:06:39.86#ibcon#read 3, iclass 14, count 2 2006.258.01:06:39.86#ibcon#about to read 4, iclass 14, count 2 2006.258.01:06:39.86#ibcon#read 4, iclass 14, count 2 2006.258.01:06:39.86#ibcon#about to read 5, iclass 14, count 2 2006.258.01:06:39.86#ibcon#read 5, iclass 14, count 2 2006.258.01:06:39.86#ibcon#about to read 6, iclass 14, count 2 2006.258.01:06:39.86#ibcon#read 6, iclass 14, count 2 2006.258.01:06:39.86#ibcon#end of sib2, iclass 14, count 2 2006.258.01:06:39.86#ibcon#*mode == 0, iclass 14, count 2 2006.258.01:06:39.86#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.258.01:06:39.86#ibcon#[25=AT08-04\r\n] 2006.258.01:06:39.86#ibcon#*before write, iclass 14, count 2 2006.258.01:06:39.86#ibcon#enter sib2, iclass 14, count 2 2006.258.01:06:39.86#ibcon#flushed, iclass 14, count 2 2006.258.01:06:39.86#ibcon#about to write, iclass 14, count 2 2006.258.01:06:39.86#ibcon#wrote, iclass 14, count 2 2006.258.01:06:39.86#ibcon#about to read 3, iclass 14, count 2 2006.258.01:06:39.89#ibcon#read 3, iclass 14, count 2 2006.258.01:06:39.89#ibcon#about to read 4, iclass 14, count 2 2006.258.01:06:39.89#ibcon#read 4, iclass 14, count 2 2006.258.01:06:39.89#ibcon#about to read 5, iclass 14, count 2 2006.258.01:06:39.89#ibcon#read 5, iclass 14, count 2 2006.258.01:06:39.89#ibcon#about to read 6, iclass 14, count 2 2006.258.01:06:39.89#ibcon#read 6, iclass 14, count 2 2006.258.01:06:39.89#ibcon#end of sib2, iclass 14, count 2 2006.258.01:06:39.89#ibcon#*after write, iclass 14, count 2 2006.258.01:06:39.89#ibcon#*before return 0, iclass 14, count 2 2006.258.01:06:39.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:06:39.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:06:39.89#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.258.01:06:39.89#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:39.89#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:06:40.01#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:06:40.01#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:06:40.01#ibcon#enter wrdev, iclass 14, count 0 2006.258.01:06:40.01#ibcon#first serial, iclass 14, count 0 2006.258.01:06:40.01#ibcon#enter sib2, iclass 14, count 0 2006.258.01:06:40.01#ibcon#flushed, iclass 14, count 0 2006.258.01:06:40.01#ibcon#about to write, iclass 14, count 0 2006.258.01:06:40.01#ibcon#wrote, iclass 14, count 0 2006.258.01:06:40.01#ibcon#about to read 3, iclass 14, count 0 2006.258.01:06:40.03#ibcon#read 3, iclass 14, count 0 2006.258.01:06:40.03#ibcon#about to read 4, iclass 14, count 0 2006.258.01:06:40.03#ibcon#read 4, iclass 14, count 0 2006.258.01:06:40.03#ibcon#about to read 5, iclass 14, count 0 2006.258.01:06:40.03#ibcon#read 5, iclass 14, count 0 2006.258.01:06:40.03#ibcon#about to read 6, iclass 14, count 0 2006.258.01:06:40.03#ibcon#read 6, iclass 14, count 0 2006.258.01:06:40.03#ibcon#end of sib2, iclass 14, count 0 2006.258.01:06:40.03#ibcon#*mode == 0, iclass 14, count 0 2006.258.01:06:40.03#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.01:06:40.03#ibcon#[25=USB\r\n] 2006.258.01:06:40.03#ibcon#*before write, iclass 14, count 0 2006.258.01:06:40.03#ibcon#enter sib2, iclass 14, count 0 2006.258.01:06:40.03#ibcon#flushed, iclass 14, count 0 2006.258.01:06:40.03#ibcon#about to write, iclass 14, count 0 2006.258.01:06:40.03#ibcon#wrote, iclass 14, count 0 2006.258.01:06:40.03#ibcon#about to read 3, iclass 14, count 0 2006.258.01:06:40.06#ibcon#read 3, iclass 14, count 0 2006.258.01:06:40.06#ibcon#about to read 4, iclass 14, count 0 2006.258.01:06:40.06#ibcon#read 4, iclass 14, count 0 2006.258.01:06:40.06#ibcon#about to read 5, iclass 14, count 0 2006.258.01:06:40.06#ibcon#read 5, iclass 14, count 0 2006.258.01:06:40.06#ibcon#about to read 6, iclass 14, count 0 2006.258.01:06:40.06#ibcon#read 6, iclass 14, count 0 2006.258.01:06:40.06#ibcon#end of sib2, iclass 14, count 0 2006.258.01:06:40.06#ibcon#*after write, iclass 14, count 0 2006.258.01:06:40.06#ibcon#*before return 0, iclass 14, count 0 2006.258.01:06:40.06#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:06:40.06#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:06:40.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.01:06:40.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.01:06:40.06$vck44/vblo=1,629.99 2006.258.01:06:40.06#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.01:06:40.06#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.01:06:40.06#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:40.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:40.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:40.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:40.06#ibcon#enter wrdev, iclass 16, count 0 2006.258.01:06:40.06#ibcon#first serial, iclass 16, count 0 2006.258.01:06:40.06#ibcon#enter sib2, iclass 16, count 0 2006.258.01:06:40.06#ibcon#flushed, iclass 16, count 0 2006.258.01:06:40.06#ibcon#about to write, iclass 16, count 0 2006.258.01:06:40.06#ibcon#wrote, iclass 16, count 0 2006.258.01:06:40.06#ibcon#about to read 3, iclass 16, count 0 2006.258.01:06:40.08#ibcon#read 3, iclass 16, count 0 2006.258.01:06:40.08#ibcon#about to read 4, iclass 16, count 0 2006.258.01:06:40.08#ibcon#read 4, iclass 16, count 0 2006.258.01:06:40.08#ibcon#about to read 5, iclass 16, count 0 2006.258.01:06:40.08#ibcon#read 5, iclass 16, count 0 2006.258.01:06:40.08#ibcon#about to read 6, iclass 16, count 0 2006.258.01:06:40.08#ibcon#read 6, iclass 16, count 0 2006.258.01:06:40.08#ibcon#end of sib2, iclass 16, count 0 2006.258.01:06:40.08#ibcon#*mode == 0, iclass 16, count 0 2006.258.01:06:40.08#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.01:06:40.08#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.01:06:40.08#ibcon#*before write, iclass 16, count 0 2006.258.01:06:40.08#ibcon#enter sib2, iclass 16, count 0 2006.258.01:06:40.08#ibcon#flushed, iclass 16, count 0 2006.258.01:06:40.08#ibcon#about to write, iclass 16, count 0 2006.258.01:06:40.08#ibcon#wrote, iclass 16, count 0 2006.258.01:06:40.08#ibcon#about to read 3, iclass 16, count 0 2006.258.01:06:40.12#ibcon#read 3, iclass 16, count 0 2006.258.01:06:40.12#ibcon#about to read 4, iclass 16, count 0 2006.258.01:06:40.12#ibcon#read 4, iclass 16, count 0 2006.258.01:06:40.12#ibcon#about to read 5, iclass 16, count 0 2006.258.01:06:40.12#ibcon#read 5, iclass 16, count 0 2006.258.01:06:40.12#ibcon#about to read 6, iclass 16, count 0 2006.258.01:06:40.12#ibcon#read 6, iclass 16, count 0 2006.258.01:06:40.12#ibcon#end of sib2, iclass 16, count 0 2006.258.01:06:40.12#ibcon#*after write, iclass 16, count 0 2006.258.01:06:40.12#ibcon#*before return 0, iclass 16, count 0 2006.258.01:06:40.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:40.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:06:40.12#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.01:06:40.12#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.01:06:40.12$vck44/vb=1,4 2006.258.01:06:40.12#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.258.01:06:40.12#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.258.01:06:40.12#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:40.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:40.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:40.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:40.12#ibcon#enter wrdev, iclass 18, count 2 2006.258.01:06:40.12#ibcon#first serial, iclass 18, count 2 2006.258.01:06:40.12#ibcon#enter sib2, iclass 18, count 2 2006.258.01:06:40.12#ibcon#flushed, iclass 18, count 2 2006.258.01:06:40.12#ibcon#about to write, iclass 18, count 2 2006.258.01:06:40.12#ibcon#wrote, iclass 18, count 2 2006.258.01:06:40.12#ibcon#about to read 3, iclass 18, count 2 2006.258.01:06:40.14#ibcon#read 3, iclass 18, count 2 2006.258.01:06:40.14#ibcon#about to read 4, iclass 18, count 2 2006.258.01:06:40.14#ibcon#read 4, iclass 18, count 2 2006.258.01:06:40.14#ibcon#about to read 5, iclass 18, count 2 2006.258.01:06:40.14#ibcon#read 5, iclass 18, count 2 2006.258.01:06:40.14#ibcon#about to read 6, iclass 18, count 2 2006.258.01:06:40.14#ibcon#read 6, iclass 18, count 2 2006.258.01:06:40.14#ibcon#end of sib2, iclass 18, count 2 2006.258.01:06:40.14#ibcon#*mode == 0, iclass 18, count 2 2006.258.01:06:40.14#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.258.01:06:40.14#ibcon#[27=AT01-04\r\n] 2006.258.01:06:40.14#ibcon#*before write, iclass 18, count 2 2006.258.01:06:40.14#ibcon#enter sib2, iclass 18, count 2 2006.258.01:06:40.14#ibcon#flushed, iclass 18, count 2 2006.258.01:06:40.14#ibcon#about to write, iclass 18, count 2 2006.258.01:06:40.14#ibcon#wrote, iclass 18, count 2 2006.258.01:06:40.14#ibcon#about to read 3, iclass 18, count 2 2006.258.01:06:40.17#ibcon#read 3, iclass 18, count 2 2006.258.01:06:40.17#ibcon#about to read 4, iclass 18, count 2 2006.258.01:06:40.17#ibcon#read 4, iclass 18, count 2 2006.258.01:06:40.17#ibcon#about to read 5, iclass 18, count 2 2006.258.01:06:40.17#ibcon#read 5, iclass 18, count 2 2006.258.01:06:40.17#ibcon#about to read 6, iclass 18, count 2 2006.258.01:06:40.17#ibcon#read 6, iclass 18, count 2 2006.258.01:06:40.17#ibcon#end of sib2, iclass 18, count 2 2006.258.01:06:40.17#ibcon#*after write, iclass 18, count 2 2006.258.01:06:40.17#ibcon#*before return 0, iclass 18, count 2 2006.258.01:06:40.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:40.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:06:40.17#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.258.01:06:40.17#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:40.17#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:40.29#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:40.29#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:40.29#ibcon#enter wrdev, iclass 18, count 0 2006.258.01:06:40.29#ibcon#first serial, iclass 18, count 0 2006.258.01:06:40.29#ibcon#enter sib2, iclass 18, count 0 2006.258.01:06:40.29#ibcon#flushed, iclass 18, count 0 2006.258.01:06:40.29#ibcon#about to write, iclass 18, count 0 2006.258.01:06:40.29#ibcon#wrote, iclass 18, count 0 2006.258.01:06:40.29#ibcon#about to read 3, iclass 18, count 0 2006.258.01:06:40.31#ibcon#read 3, iclass 18, count 0 2006.258.01:06:40.31#ibcon#about to read 4, iclass 18, count 0 2006.258.01:06:40.31#ibcon#read 4, iclass 18, count 0 2006.258.01:06:40.31#ibcon#about to read 5, iclass 18, count 0 2006.258.01:06:40.31#ibcon#read 5, iclass 18, count 0 2006.258.01:06:40.31#ibcon#about to read 6, iclass 18, count 0 2006.258.01:06:40.31#ibcon#read 6, iclass 18, count 0 2006.258.01:06:40.31#ibcon#end of sib2, iclass 18, count 0 2006.258.01:06:40.31#ibcon#*mode == 0, iclass 18, count 0 2006.258.01:06:40.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.01:06:40.31#ibcon#[27=USB\r\n] 2006.258.01:06:40.31#ibcon#*before write, iclass 18, count 0 2006.258.01:06:40.31#ibcon#enter sib2, iclass 18, count 0 2006.258.01:06:40.31#ibcon#flushed, iclass 18, count 0 2006.258.01:06:40.31#ibcon#about to write, iclass 18, count 0 2006.258.01:06:40.31#ibcon#wrote, iclass 18, count 0 2006.258.01:06:40.31#ibcon#about to read 3, iclass 18, count 0 2006.258.01:06:40.34#ibcon#read 3, iclass 18, count 0 2006.258.01:06:40.34#ibcon#about to read 4, iclass 18, count 0 2006.258.01:06:40.34#ibcon#read 4, iclass 18, count 0 2006.258.01:06:40.34#ibcon#about to read 5, iclass 18, count 0 2006.258.01:06:40.34#ibcon#read 5, iclass 18, count 0 2006.258.01:06:40.34#ibcon#about to read 6, iclass 18, count 0 2006.258.01:06:40.34#ibcon#read 6, iclass 18, count 0 2006.258.01:06:40.34#ibcon#end of sib2, iclass 18, count 0 2006.258.01:06:40.34#ibcon#*after write, iclass 18, count 0 2006.258.01:06:40.34#ibcon#*before return 0, iclass 18, count 0 2006.258.01:06:40.34#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:40.34#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:06:40.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.01:06:40.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.01:06:40.34$vck44/vblo=2,634.99 2006.258.01:06:40.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.01:06:40.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.01:06:40.34#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:40.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:40.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:40.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:40.34#ibcon#enter wrdev, iclass 20, count 0 2006.258.01:06:40.34#ibcon#first serial, iclass 20, count 0 2006.258.01:06:40.34#ibcon#enter sib2, iclass 20, count 0 2006.258.01:06:40.34#ibcon#flushed, iclass 20, count 0 2006.258.01:06:40.34#ibcon#about to write, iclass 20, count 0 2006.258.01:06:40.34#ibcon#wrote, iclass 20, count 0 2006.258.01:06:40.34#ibcon#about to read 3, iclass 20, count 0 2006.258.01:06:40.36#ibcon#read 3, iclass 20, count 0 2006.258.01:06:40.36#ibcon#about to read 4, iclass 20, count 0 2006.258.01:06:40.36#ibcon#read 4, iclass 20, count 0 2006.258.01:06:40.36#ibcon#about to read 5, iclass 20, count 0 2006.258.01:06:40.36#ibcon#read 5, iclass 20, count 0 2006.258.01:06:40.36#ibcon#about to read 6, iclass 20, count 0 2006.258.01:06:40.36#ibcon#read 6, iclass 20, count 0 2006.258.01:06:40.36#ibcon#end of sib2, iclass 20, count 0 2006.258.01:06:40.36#ibcon#*mode == 0, iclass 20, count 0 2006.258.01:06:40.36#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.01:06:40.36#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.01:06:40.36#ibcon#*before write, iclass 20, count 0 2006.258.01:06:40.36#ibcon#enter sib2, iclass 20, count 0 2006.258.01:06:40.36#ibcon#flushed, iclass 20, count 0 2006.258.01:06:40.36#ibcon#about to write, iclass 20, count 0 2006.258.01:06:40.36#ibcon#wrote, iclass 20, count 0 2006.258.01:06:40.36#ibcon#about to read 3, iclass 20, count 0 2006.258.01:06:40.40#ibcon#read 3, iclass 20, count 0 2006.258.01:06:40.40#ibcon#about to read 4, iclass 20, count 0 2006.258.01:06:40.40#ibcon#read 4, iclass 20, count 0 2006.258.01:06:40.40#ibcon#about to read 5, iclass 20, count 0 2006.258.01:06:40.40#ibcon#read 5, iclass 20, count 0 2006.258.01:06:40.40#ibcon#about to read 6, iclass 20, count 0 2006.258.01:06:40.40#ibcon#read 6, iclass 20, count 0 2006.258.01:06:40.40#ibcon#end of sib2, iclass 20, count 0 2006.258.01:06:40.40#ibcon#*after write, iclass 20, count 0 2006.258.01:06:40.40#ibcon#*before return 0, iclass 20, count 0 2006.258.01:06:40.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:40.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:06:40.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.01:06:40.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.01:06:40.40$vck44/vb=2,5 2006.258.01:06:40.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.01:06:40.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.01:06:40.40#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:40.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:40.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:40.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:40.46#ibcon#enter wrdev, iclass 22, count 2 2006.258.01:06:40.46#ibcon#first serial, iclass 22, count 2 2006.258.01:06:40.46#ibcon#enter sib2, iclass 22, count 2 2006.258.01:06:40.46#ibcon#flushed, iclass 22, count 2 2006.258.01:06:40.46#ibcon#about to write, iclass 22, count 2 2006.258.01:06:40.46#ibcon#wrote, iclass 22, count 2 2006.258.01:06:40.46#ibcon#about to read 3, iclass 22, count 2 2006.258.01:06:40.48#ibcon#read 3, iclass 22, count 2 2006.258.01:06:40.48#ibcon#about to read 4, iclass 22, count 2 2006.258.01:06:40.48#ibcon#read 4, iclass 22, count 2 2006.258.01:06:40.48#ibcon#about to read 5, iclass 22, count 2 2006.258.01:06:40.48#ibcon#read 5, iclass 22, count 2 2006.258.01:06:40.48#ibcon#about to read 6, iclass 22, count 2 2006.258.01:06:40.48#ibcon#read 6, iclass 22, count 2 2006.258.01:06:40.48#ibcon#end of sib2, iclass 22, count 2 2006.258.01:06:40.48#ibcon#*mode == 0, iclass 22, count 2 2006.258.01:06:40.48#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.01:06:40.48#ibcon#[27=AT02-05\r\n] 2006.258.01:06:40.48#ibcon#*before write, iclass 22, count 2 2006.258.01:06:40.48#ibcon#enter sib2, iclass 22, count 2 2006.258.01:06:40.48#ibcon#flushed, iclass 22, count 2 2006.258.01:06:40.48#ibcon#about to write, iclass 22, count 2 2006.258.01:06:40.48#ibcon#wrote, iclass 22, count 2 2006.258.01:06:40.48#ibcon#about to read 3, iclass 22, count 2 2006.258.01:06:40.51#ibcon#read 3, iclass 22, count 2 2006.258.01:06:40.55#ibcon#about to read 4, iclass 22, count 2 2006.258.01:06:40.55#ibcon#read 4, iclass 22, count 2 2006.258.01:06:40.55#ibcon#about to read 5, iclass 22, count 2 2006.258.01:06:40.55#ibcon#read 5, iclass 22, count 2 2006.258.01:06:40.56#ibcon#about to read 6, iclass 22, count 2 2006.258.01:06:40.56#ibcon#read 6, iclass 22, count 2 2006.258.01:06:40.56#ibcon#end of sib2, iclass 22, count 2 2006.258.01:06:40.56#ibcon#*after write, iclass 22, count 2 2006.258.01:06:40.56#ibcon#*before return 0, iclass 22, count 2 2006.258.01:06:40.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:40.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:06:40.56#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.01:06:40.56#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:40.56#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:40.68#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:40.68#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:40.68#ibcon#enter wrdev, iclass 22, count 0 2006.258.01:06:40.68#ibcon#first serial, iclass 22, count 0 2006.258.01:06:40.68#ibcon#enter sib2, iclass 22, count 0 2006.258.01:06:40.68#ibcon#flushed, iclass 22, count 0 2006.258.01:06:40.68#ibcon#about to write, iclass 22, count 0 2006.258.01:06:40.68#ibcon#wrote, iclass 22, count 0 2006.258.01:06:40.68#ibcon#about to read 3, iclass 22, count 0 2006.258.01:06:40.70#ibcon#read 3, iclass 22, count 0 2006.258.01:06:40.70#ibcon#about to read 4, iclass 22, count 0 2006.258.01:06:40.70#ibcon#read 4, iclass 22, count 0 2006.258.01:06:40.70#ibcon#about to read 5, iclass 22, count 0 2006.258.01:06:40.70#ibcon#read 5, iclass 22, count 0 2006.258.01:06:40.70#ibcon#about to read 6, iclass 22, count 0 2006.258.01:06:40.70#ibcon#read 6, iclass 22, count 0 2006.258.01:06:40.70#ibcon#end of sib2, iclass 22, count 0 2006.258.01:06:40.70#ibcon#*mode == 0, iclass 22, count 0 2006.258.01:06:40.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.01:06:40.70#ibcon#[27=USB\r\n] 2006.258.01:06:40.70#ibcon#*before write, iclass 22, count 0 2006.258.01:06:40.70#ibcon#enter sib2, iclass 22, count 0 2006.258.01:06:40.70#ibcon#flushed, iclass 22, count 0 2006.258.01:06:40.70#ibcon#about to write, iclass 22, count 0 2006.258.01:06:40.70#ibcon#wrote, iclass 22, count 0 2006.258.01:06:40.70#ibcon#about to read 3, iclass 22, count 0 2006.258.01:06:40.73#ibcon#read 3, iclass 22, count 0 2006.258.01:06:40.73#ibcon#about to read 4, iclass 22, count 0 2006.258.01:06:40.73#ibcon#read 4, iclass 22, count 0 2006.258.01:06:40.73#ibcon#about to read 5, iclass 22, count 0 2006.258.01:06:40.73#ibcon#read 5, iclass 22, count 0 2006.258.01:06:40.73#ibcon#about to read 6, iclass 22, count 0 2006.258.01:06:40.73#ibcon#read 6, iclass 22, count 0 2006.258.01:06:40.73#ibcon#end of sib2, iclass 22, count 0 2006.258.01:06:40.73#ibcon#*after write, iclass 22, count 0 2006.258.01:06:40.73#ibcon#*before return 0, iclass 22, count 0 2006.258.01:06:40.73#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:40.73#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:06:40.73#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.01:06:40.73#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.01:06:40.73$vck44/vblo=3,649.99 2006.258.01:06:40.73#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.01:06:40.73#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.01:06:40.73#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:40.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:40.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:40.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:40.73#ibcon#enter wrdev, iclass 24, count 0 2006.258.01:06:40.73#ibcon#first serial, iclass 24, count 0 2006.258.01:06:40.73#ibcon#enter sib2, iclass 24, count 0 2006.258.01:06:40.73#ibcon#flushed, iclass 24, count 0 2006.258.01:06:40.73#ibcon#about to write, iclass 24, count 0 2006.258.01:06:40.73#ibcon#wrote, iclass 24, count 0 2006.258.01:06:40.73#ibcon#about to read 3, iclass 24, count 0 2006.258.01:06:40.75#ibcon#read 3, iclass 24, count 0 2006.258.01:06:40.75#ibcon#about to read 4, iclass 24, count 0 2006.258.01:06:40.75#ibcon#read 4, iclass 24, count 0 2006.258.01:06:40.75#ibcon#about to read 5, iclass 24, count 0 2006.258.01:06:40.75#ibcon#read 5, iclass 24, count 0 2006.258.01:06:40.75#ibcon#about to read 6, iclass 24, count 0 2006.258.01:06:40.75#ibcon#read 6, iclass 24, count 0 2006.258.01:06:40.75#ibcon#end of sib2, iclass 24, count 0 2006.258.01:06:40.75#ibcon#*mode == 0, iclass 24, count 0 2006.258.01:06:40.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.01:06:40.75#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.01:06:40.75#ibcon#*before write, iclass 24, count 0 2006.258.01:06:40.75#ibcon#enter sib2, iclass 24, count 0 2006.258.01:06:40.75#ibcon#flushed, iclass 24, count 0 2006.258.01:06:40.75#ibcon#about to write, iclass 24, count 0 2006.258.01:06:40.75#ibcon#wrote, iclass 24, count 0 2006.258.01:06:40.75#ibcon#about to read 3, iclass 24, count 0 2006.258.01:06:40.79#ibcon#read 3, iclass 24, count 0 2006.258.01:06:40.79#ibcon#about to read 4, iclass 24, count 0 2006.258.01:06:40.79#ibcon#read 4, iclass 24, count 0 2006.258.01:06:40.79#ibcon#about to read 5, iclass 24, count 0 2006.258.01:06:40.79#ibcon#read 5, iclass 24, count 0 2006.258.01:06:40.79#ibcon#about to read 6, iclass 24, count 0 2006.258.01:06:40.79#ibcon#read 6, iclass 24, count 0 2006.258.01:06:40.79#ibcon#end of sib2, iclass 24, count 0 2006.258.01:06:40.79#ibcon#*after write, iclass 24, count 0 2006.258.01:06:40.79#ibcon#*before return 0, iclass 24, count 0 2006.258.01:06:40.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:40.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:06:40.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.01:06:40.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.01:06:40.79$vck44/vb=3,4 2006.258.01:06:40.79#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.01:06:40.79#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.01:06:40.79#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:40.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:40.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:40.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:40.85#ibcon#enter wrdev, iclass 26, count 2 2006.258.01:06:40.85#ibcon#first serial, iclass 26, count 2 2006.258.01:06:40.85#ibcon#enter sib2, iclass 26, count 2 2006.258.01:06:40.85#ibcon#flushed, iclass 26, count 2 2006.258.01:06:40.85#ibcon#about to write, iclass 26, count 2 2006.258.01:06:40.85#ibcon#wrote, iclass 26, count 2 2006.258.01:06:40.85#ibcon#about to read 3, iclass 26, count 2 2006.258.01:06:40.87#ibcon#read 3, iclass 26, count 2 2006.258.01:06:40.87#ibcon#about to read 4, iclass 26, count 2 2006.258.01:06:40.87#ibcon#read 4, iclass 26, count 2 2006.258.01:06:40.87#ibcon#about to read 5, iclass 26, count 2 2006.258.01:06:40.87#ibcon#read 5, iclass 26, count 2 2006.258.01:06:40.87#ibcon#about to read 6, iclass 26, count 2 2006.258.01:06:40.87#ibcon#read 6, iclass 26, count 2 2006.258.01:06:40.87#ibcon#end of sib2, iclass 26, count 2 2006.258.01:06:40.87#ibcon#*mode == 0, iclass 26, count 2 2006.258.01:06:40.87#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.01:06:40.87#ibcon#[27=AT03-04\r\n] 2006.258.01:06:40.87#ibcon#*before write, iclass 26, count 2 2006.258.01:06:40.87#ibcon#enter sib2, iclass 26, count 2 2006.258.01:06:40.87#ibcon#flushed, iclass 26, count 2 2006.258.01:06:40.87#ibcon#about to write, iclass 26, count 2 2006.258.01:06:40.87#ibcon#wrote, iclass 26, count 2 2006.258.01:06:40.87#ibcon#about to read 3, iclass 26, count 2 2006.258.01:06:40.90#ibcon#read 3, iclass 26, count 2 2006.258.01:06:40.90#ibcon#about to read 4, iclass 26, count 2 2006.258.01:06:40.90#ibcon#read 4, iclass 26, count 2 2006.258.01:06:40.90#ibcon#about to read 5, iclass 26, count 2 2006.258.01:06:40.90#ibcon#read 5, iclass 26, count 2 2006.258.01:06:40.90#ibcon#about to read 6, iclass 26, count 2 2006.258.01:06:40.90#ibcon#read 6, iclass 26, count 2 2006.258.01:06:40.90#ibcon#end of sib2, iclass 26, count 2 2006.258.01:06:40.90#ibcon#*after write, iclass 26, count 2 2006.258.01:06:40.90#ibcon#*before return 0, iclass 26, count 2 2006.258.01:06:40.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:40.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:06:40.90#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.01:06:40.90#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:40.90#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:41.02#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:41.02#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:41.02#ibcon#enter wrdev, iclass 26, count 0 2006.258.01:06:41.02#ibcon#first serial, iclass 26, count 0 2006.258.01:06:41.02#ibcon#enter sib2, iclass 26, count 0 2006.258.01:06:41.02#ibcon#flushed, iclass 26, count 0 2006.258.01:06:41.02#ibcon#about to write, iclass 26, count 0 2006.258.01:06:41.02#ibcon#wrote, iclass 26, count 0 2006.258.01:06:41.02#ibcon#about to read 3, iclass 26, count 0 2006.258.01:06:41.04#ibcon#read 3, iclass 26, count 0 2006.258.01:06:41.04#ibcon#about to read 4, iclass 26, count 0 2006.258.01:06:41.04#ibcon#read 4, iclass 26, count 0 2006.258.01:06:41.04#ibcon#about to read 5, iclass 26, count 0 2006.258.01:06:41.04#ibcon#read 5, iclass 26, count 0 2006.258.01:06:41.04#ibcon#about to read 6, iclass 26, count 0 2006.258.01:06:41.04#ibcon#read 6, iclass 26, count 0 2006.258.01:06:41.04#ibcon#end of sib2, iclass 26, count 0 2006.258.01:06:41.04#ibcon#*mode == 0, iclass 26, count 0 2006.258.01:06:41.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.01:06:41.04#ibcon#[27=USB\r\n] 2006.258.01:06:41.04#ibcon#*before write, iclass 26, count 0 2006.258.01:06:41.04#ibcon#enter sib2, iclass 26, count 0 2006.258.01:06:41.04#ibcon#flushed, iclass 26, count 0 2006.258.01:06:41.04#ibcon#about to write, iclass 26, count 0 2006.258.01:06:41.04#ibcon#wrote, iclass 26, count 0 2006.258.01:06:41.04#ibcon#about to read 3, iclass 26, count 0 2006.258.01:06:41.07#ibcon#read 3, iclass 26, count 0 2006.258.01:06:41.07#ibcon#about to read 4, iclass 26, count 0 2006.258.01:06:41.07#ibcon#read 4, iclass 26, count 0 2006.258.01:06:41.07#ibcon#about to read 5, iclass 26, count 0 2006.258.01:06:41.07#ibcon#read 5, iclass 26, count 0 2006.258.01:06:41.07#ibcon#about to read 6, iclass 26, count 0 2006.258.01:06:41.07#ibcon#read 6, iclass 26, count 0 2006.258.01:06:41.07#ibcon#end of sib2, iclass 26, count 0 2006.258.01:06:41.07#ibcon#*after write, iclass 26, count 0 2006.258.01:06:41.07#ibcon#*before return 0, iclass 26, count 0 2006.258.01:06:41.07#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:41.07#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:06:41.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.01:06:41.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.01:06:41.07$vck44/vblo=4,679.99 2006.258.01:06:41.07#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.01:06:41.07#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.01:06:41.07#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:41.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:41.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:41.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:41.07#ibcon#enter wrdev, iclass 28, count 0 2006.258.01:06:41.07#ibcon#first serial, iclass 28, count 0 2006.258.01:06:41.07#ibcon#enter sib2, iclass 28, count 0 2006.258.01:06:41.07#ibcon#flushed, iclass 28, count 0 2006.258.01:06:41.07#ibcon#about to write, iclass 28, count 0 2006.258.01:06:41.07#ibcon#wrote, iclass 28, count 0 2006.258.01:06:41.07#ibcon#about to read 3, iclass 28, count 0 2006.258.01:06:41.09#ibcon#read 3, iclass 28, count 0 2006.258.01:06:41.09#ibcon#about to read 4, iclass 28, count 0 2006.258.01:06:41.09#ibcon#read 4, iclass 28, count 0 2006.258.01:06:41.09#ibcon#about to read 5, iclass 28, count 0 2006.258.01:06:41.09#ibcon#read 5, iclass 28, count 0 2006.258.01:06:41.09#ibcon#about to read 6, iclass 28, count 0 2006.258.01:06:41.09#ibcon#read 6, iclass 28, count 0 2006.258.01:06:41.09#ibcon#end of sib2, iclass 28, count 0 2006.258.01:06:41.09#ibcon#*mode == 0, iclass 28, count 0 2006.258.01:06:41.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.01:06:41.09#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.01:06:41.09#ibcon#*before write, iclass 28, count 0 2006.258.01:06:41.09#ibcon#enter sib2, iclass 28, count 0 2006.258.01:06:41.09#ibcon#flushed, iclass 28, count 0 2006.258.01:06:41.09#ibcon#about to write, iclass 28, count 0 2006.258.01:06:41.09#ibcon#wrote, iclass 28, count 0 2006.258.01:06:41.09#ibcon#about to read 3, iclass 28, count 0 2006.258.01:06:41.13#ibcon#read 3, iclass 28, count 0 2006.258.01:06:41.13#ibcon#about to read 4, iclass 28, count 0 2006.258.01:06:41.13#ibcon#read 4, iclass 28, count 0 2006.258.01:06:41.13#ibcon#about to read 5, iclass 28, count 0 2006.258.01:06:41.13#ibcon#read 5, iclass 28, count 0 2006.258.01:06:41.13#ibcon#about to read 6, iclass 28, count 0 2006.258.01:06:41.13#ibcon#read 6, iclass 28, count 0 2006.258.01:06:41.13#ibcon#end of sib2, iclass 28, count 0 2006.258.01:06:41.13#ibcon#*after write, iclass 28, count 0 2006.258.01:06:41.13#ibcon#*before return 0, iclass 28, count 0 2006.258.01:06:41.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:41.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:06:41.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.01:06:41.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.01:06:41.13$vck44/vb=4,5 2006.258.01:06:41.13#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.01:06:41.13#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.01:06:41.13#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:41.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:41.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:41.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:41.19#ibcon#enter wrdev, iclass 30, count 2 2006.258.01:06:41.19#ibcon#first serial, iclass 30, count 2 2006.258.01:06:41.19#ibcon#enter sib2, iclass 30, count 2 2006.258.01:06:41.19#ibcon#flushed, iclass 30, count 2 2006.258.01:06:41.19#ibcon#about to write, iclass 30, count 2 2006.258.01:06:41.19#ibcon#wrote, iclass 30, count 2 2006.258.01:06:41.19#ibcon#about to read 3, iclass 30, count 2 2006.258.01:06:41.21#ibcon#read 3, iclass 30, count 2 2006.258.01:06:41.21#ibcon#about to read 4, iclass 30, count 2 2006.258.01:06:41.21#ibcon#read 4, iclass 30, count 2 2006.258.01:06:41.21#ibcon#about to read 5, iclass 30, count 2 2006.258.01:06:41.21#ibcon#read 5, iclass 30, count 2 2006.258.01:06:41.21#ibcon#about to read 6, iclass 30, count 2 2006.258.01:06:41.21#ibcon#read 6, iclass 30, count 2 2006.258.01:06:41.21#ibcon#end of sib2, iclass 30, count 2 2006.258.01:06:41.21#ibcon#*mode == 0, iclass 30, count 2 2006.258.01:06:41.21#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.01:06:41.21#ibcon#[27=AT04-05\r\n] 2006.258.01:06:41.21#ibcon#*before write, iclass 30, count 2 2006.258.01:06:41.21#ibcon#enter sib2, iclass 30, count 2 2006.258.01:06:41.21#ibcon#flushed, iclass 30, count 2 2006.258.01:06:41.21#ibcon#about to write, iclass 30, count 2 2006.258.01:06:41.21#ibcon#wrote, iclass 30, count 2 2006.258.01:06:41.21#ibcon#about to read 3, iclass 30, count 2 2006.258.01:06:41.24#ibcon#read 3, iclass 30, count 2 2006.258.01:06:41.24#ibcon#about to read 4, iclass 30, count 2 2006.258.01:06:41.24#ibcon#read 4, iclass 30, count 2 2006.258.01:06:41.24#ibcon#about to read 5, iclass 30, count 2 2006.258.01:06:41.24#ibcon#read 5, iclass 30, count 2 2006.258.01:06:41.24#ibcon#about to read 6, iclass 30, count 2 2006.258.01:06:41.24#ibcon#read 6, iclass 30, count 2 2006.258.01:06:41.24#ibcon#end of sib2, iclass 30, count 2 2006.258.01:06:41.24#ibcon#*after write, iclass 30, count 2 2006.258.01:06:41.24#ibcon#*before return 0, iclass 30, count 2 2006.258.01:06:41.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:41.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:06:41.24#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.01:06:41.24#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:41.24#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:41.36#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:41.36#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:41.36#ibcon#enter wrdev, iclass 30, count 0 2006.258.01:06:41.36#ibcon#first serial, iclass 30, count 0 2006.258.01:06:41.36#ibcon#enter sib2, iclass 30, count 0 2006.258.01:06:41.36#ibcon#flushed, iclass 30, count 0 2006.258.01:06:41.36#ibcon#about to write, iclass 30, count 0 2006.258.01:06:41.36#ibcon#wrote, iclass 30, count 0 2006.258.01:06:41.36#ibcon#about to read 3, iclass 30, count 0 2006.258.01:06:41.38#ibcon#read 3, iclass 30, count 0 2006.258.01:06:41.38#ibcon#about to read 4, iclass 30, count 0 2006.258.01:06:41.38#ibcon#read 4, iclass 30, count 0 2006.258.01:06:41.38#ibcon#about to read 5, iclass 30, count 0 2006.258.01:06:41.38#ibcon#read 5, iclass 30, count 0 2006.258.01:06:41.38#ibcon#about to read 6, iclass 30, count 0 2006.258.01:06:41.38#ibcon#read 6, iclass 30, count 0 2006.258.01:06:41.38#ibcon#end of sib2, iclass 30, count 0 2006.258.01:06:41.38#ibcon#*mode == 0, iclass 30, count 0 2006.258.01:06:41.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.01:06:41.38#ibcon#[27=USB\r\n] 2006.258.01:06:41.38#ibcon#*before write, iclass 30, count 0 2006.258.01:06:41.38#ibcon#enter sib2, iclass 30, count 0 2006.258.01:06:41.38#ibcon#flushed, iclass 30, count 0 2006.258.01:06:41.38#ibcon#about to write, iclass 30, count 0 2006.258.01:06:41.38#ibcon#wrote, iclass 30, count 0 2006.258.01:06:41.38#ibcon#about to read 3, iclass 30, count 0 2006.258.01:06:41.41#ibcon#read 3, iclass 30, count 0 2006.258.01:06:41.41#ibcon#about to read 4, iclass 30, count 0 2006.258.01:06:41.41#ibcon#read 4, iclass 30, count 0 2006.258.01:06:41.41#ibcon#about to read 5, iclass 30, count 0 2006.258.01:06:41.41#ibcon#read 5, iclass 30, count 0 2006.258.01:06:41.41#ibcon#about to read 6, iclass 30, count 0 2006.258.01:06:41.41#ibcon#read 6, iclass 30, count 0 2006.258.01:06:41.41#ibcon#end of sib2, iclass 30, count 0 2006.258.01:06:41.41#ibcon#*after write, iclass 30, count 0 2006.258.01:06:41.41#ibcon#*before return 0, iclass 30, count 0 2006.258.01:06:41.41#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:41.41#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:06:41.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.01:06:41.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.01:06:41.41$vck44/vblo=5,709.99 2006.258.01:06:41.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.258.01:06:41.41#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.258.01:06:41.41#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:41.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:41.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:41.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:41.41#ibcon#enter wrdev, iclass 32, count 0 2006.258.01:06:41.41#ibcon#first serial, iclass 32, count 0 2006.258.01:06:41.41#ibcon#enter sib2, iclass 32, count 0 2006.258.01:06:41.41#ibcon#flushed, iclass 32, count 0 2006.258.01:06:41.41#ibcon#about to write, iclass 32, count 0 2006.258.01:06:41.41#ibcon#wrote, iclass 32, count 0 2006.258.01:06:41.41#ibcon#about to read 3, iclass 32, count 0 2006.258.01:06:41.43#ibcon#read 3, iclass 32, count 0 2006.258.01:06:41.43#ibcon#about to read 4, iclass 32, count 0 2006.258.01:06:41.43#ibcon#read 4, iclass 32, count 0 2006.258.01:06:41.43#ibcon#about to read 5, iclass 32, count 0 2006.258.01:06:41.43#ibcon#read 5, iclass 32, count 0 2006.258.01:06:41.43#ibcon#about to read 6, iclass 32, count 0 2006.258.01:06:41.43#ibcon#read 6, iclass 32, count 0 2006.258.01:06:41.43#ibcon#end of sib2, iclass 32, count 0 2006.258.01:06:41.43#ibcon#*mode == 0, iclass 32, count 0 2006.258.01:06:41.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.01:06:41.43#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.01:06:41.43#ibcon#*before write, iclass 32, count 0 2006.258.01:06:41.43#ibcon#enter sib2, iclass 32, count 0 2006.258.01:06:41.43#ibcon#flushed, iclass 32, count 0 2006.258.01:06:41.43#ibcon#about to write, iclass 32, count 0 2006.258.01:06:41.43#ibcon#wrote, iclass 32, count 0 2006.258.01:06:41.43#ibcon#about to read 3, iclass 32, count 0 2006.258.01:06:41.47#ibcon#read 3, iclass 32, count 0 2006.258.01:06:41.47#ibcon#about to read 4, iclass 32, count 0 2006.258.01:06:41.47#ibcon#read 4, iclass 32, count 0 2006.258.01:06:41.47#ibcon#about to read 5, iclass 32, count 0 2006.258.01:06:41.47#ibcon#read 5, iclass 32, count 0 2006.258.01:06:41.47#ibcon#about to read 6, iclass 32, count 0 2006.258.01:06:41.47#ibcon#read 6, iclass 32, count 0 2006.258.01:06:41.47#ibcon#end of sib2, iclass 32, count 0 2006.258.01:06:41.47#ibcon#*after write, iclass 32, count 0 2006.258.01:06:41.47#ibcon#*before return 0, iclass 32, count 0 2006.258.01:06:41.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:41.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:06:41.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.01:06:41.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.01:06:41.47$vck44/vb=5,4 2006.258.01:06:41.47#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.258.01:06:41.47#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.258.01:06:41.47#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:41.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:41.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:41.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:41.53#ibcon#enter wrdev, iclass 34, count 2 2006.258.01:06:41.53#ibcon#first serial, iclass 34, count 2 2006.258.01:06:41.53#ibcon#enter sib2, iclass 34, count 2 2006.258.01:06:41.53#ibcon#flushed, iclass 34, count 2 2006.258.01:06:41.53#ibcon#about to write, iclass 34, count 2 2006.258.01:06:41.53#ibcon#wrote, iclass 34, count 2 2006.258.01:06:41.53#ibcon#about to read 3, iclass 34, count 2 2006.258.01:06:41.55#ibcon#read 3, iclass 34, count 2 2006.258.01:06:41.55#ibcon#about to read 4, iclass 34, count 2 2006.258.01:06:41.55#ibcon#read 4, iclass 34, count 2 2006.258.01:06:41.55#ibcon#about to read 5, iclass 34, count 2 2006.258.01:06:41.55#ibcon#read 5, iclass 34, count 2 2006.258.01:06:41.55#ibcon#about to read 6, iclass 34, count 2 2006.258.01:06:41.55#ibcon#read 6, iclass 34, count 2 2006.258.01:06:41.55#ibcon#end of sib2, iclass 34, count 2 2006.258.01:06:41.55#ibcon#*mode == 0, iclass 34, count 2 2006.258.01:06:41.55#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.258.01:06:41.55#ibcon#[27=AT05-04\r\n] 2006.258.01:06:41.55#ibcon#*before write, iclass 34, count 2 2006.258.01:06:41.55#ibcon#enter sib2, iclass 34, count 2 2006.258.01:06:41.55#ibcon#flushed, iclass 34, count 2 2006.258.01:06:41.55#ibcon#about to write, iclass 34, count 2 2006.258.01:06:41.55#ibcon#wrote, iclass 34, count 2 2006.258.01:06:41.55#ibcon#about to read 3, iclass 34, count 2 2006.258.01:06:41.58#ibcon#read 3, iclass 34, count 2 2006.258.01:06:41.58#ibcon#about to read 4, iclass 34, count 2 2006.258.01:06:41.58#ibcon#read 4, iclass 34, count 2 2006.258.01:06:41.58#ibcon#about to read 5, iclass 34, count 2 2006.258.01:06:41.58#ibcon#read 5, iclass 34, count 2 2006.258.01:06:41.58#ibcon#about to read 6, iclass 34, count 2 2006.258.01:06:41.58#ibcon#read 6, iclass 34, count 2 2006.258.01:06:41.58#ibcon#end of sib2, iclass 34, count 2 2006.258.01:06:41.58#ibcon#*after write, iclass 34, count 2 2006.258.01:06:41.60#ibcon#*before return 0, iclass 34, count 2 2006.258.01:06:41.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:41.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:06:41.60#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.258.01:06:41.60#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:41.60#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:41.71#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:41.71#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:41.71#ibcon#enter wrdev, iclass 34, count 0 2006.258.01:06:41.71#ibcon#first serial, iclass 34, count 0 2006.258.01:06:41.71#ibcon#enter sib2, iclass 34, count 0 2006.258.01:06:41.71#ibcon#flushed, iclass 34, count 0 2006.258.01:06:41.71#ibcon#about to write, iclass 34, count 0 2006.258.01:06:41.71#ibcon#wrote, iclass 34, count 0 2006.258.01:06:41.71#ibcon#about to read 3, iclass 34, count 0 2006.258.01:06:41.73#ibcon#read 3, iclass 34, count 0 2006.258.01:06:41.73#ibcon#about to read 4, iclass 34, count 0 2006.258.01:06:41.73#ibcon#read 4, iclass 34, count 0 2006.258.01:06:41.73#ibcon#about to read 5, iclass 34, count 0 2006.258.01:06:41.73#ibcon#read 5, iclass 34, count 0 2006.258.01:06:41.73#ibcon#about to read 6, iclass 34, count 0 2006.258.01:06:41.73#ibcon#read 6, iclass 34, count 0 2006.258.01:06:41.73#ibcon#end of sib2, iclass 34, count 0 2006.258.01:06:41.73#ibcon#*mode == 0, iclass 34, count 0 2006.258.01:06:41.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.01:06:41.73#ibcon#[27=USB\r\n] 2006.258.01:06:41.73#ibcon#*before write, iclass 34, count 0 2006.258.01:06:41.73#ibcon#enter sib2, iclass 34, count 0 2006.258.01:06:41.73#ibcon#flushed, iclass 34, count 0 2006.258.01:06:41.73#ibcon#about to write, iclass 34, count 0 2006.258.01:06:41.73#ibcon#wrote, iclass 34, count 0 2006.258.01:06:41.73#ibcon#about to read 3, iclass 34, count 0 2006.258.01:06:41.76#ibcon#read 3, iclass 34, count 0 2006.258.01:06:41.76#ibcon#about to read 4, iclass 34, count 0 2006.258.01:06:41.76#ibcon#read 4, iclass 34, count 0 2006.258.01:06:41.76#ibcon#about to read 5, iclass 34, count 0 2006.258.01:06:41.76#ibcon#read 5, iclass 34, count 0 2006.258.01:06:41.76#ibcon#about to read 6, iclass 34, count 0 2006.258.01:06:41.76#ibcon#read 6, iclass 34, count 0 2006.258.01:06:41.76#ibcon#end of sib2, iclass 34, count 0 2006.258.01:06:41.76#ibcon#*after write, iclass 34, count 0 2006.258.01:06:41.76#ibcon#*before return 0, iclass 34, count 0 2006.258.01:06:41.76#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:41.76#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:06:41.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.01:06:41.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.01:06:41.76$vck44/vblo=6,719.99 2006.258.01:06:41.76#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.258.01:06:41.76#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.258.01:06:41.76#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:41.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:06:41.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:06:41.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:06:41.76#ibcon#enter wrdev, iclass 36, count 0 2006.258.01:06:41.76#ibcon#first serial, iclass 36, count 0 2006.258.01:06:41.76#ibcon#enter sib2, iclass 36, count 0 2006.258.01:06:41.76#ibcon#flushed, iclass 36, count 0 2006.258.01:06:41.76#ibcon#about to write, iclass 36, count 0 2006.258.01:06:41.76#ibcon#wrote, iclass 36, count 0 2006.258.01:06:41.76#ibcon#about to read 3, iclass 36, count 0 2006.258.01:06:41.78#ibcon#read 3, iclass 36, count 0 2006.258.01:06:41.78#ibcon#about to read 4, iclass 36, count 0 2006.258.01:06:41.78#ibcon#read 4, iclass 36, count 0 2006.258.01:06:41.78#ibcon#about to read 5, iclass 36, count 0 2006.258.01:06:41.78#ibcon#read 5, iclass 36, count 0 2006.258.01:06:41.78#ibcon#about to read 6, iclass 36, count 0 2006.258.01:06:41.78#ibcon#read 6, iclass 36, count 0 2006.258.01:06:41.78#ibcon#end of sib2, iclass 36, count 0 2006.258.01:06:41.78#ibcon#*mode == 0, iclass 36, count 0 2006.258.01:06:41.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.01:06:41.78#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.01:06:41.78#ibcon#*before write, iclass 36, count 0 2006.258.01:06:41.78#ibcon#enter sib2, iclass 36, count 0 2006.258.01:06:41.78#ibcon#flushed, iclass 36, count 0 2006.258.01:06:41.78#ibcon#about to write, iclass 36, count 0 2006.258.01:06:41.78#ibcon#wrote, iclass 36, count 0 2006.258.01:06:41.78#ibcon#about to read 3, iclass 36, count 0 2006.258.01:06:41.82#ibcon#read 3, iclass 36, count 0 2006.258.01:06:41.82#ibcon#about to read 4, iclass 36, count 0 2006.258.01:06:41.82#ibcon#read 4, iclass 36, count 0 2006.258.01:06:41.82#ibcon#about to read 5, iclass 36, count 0 2006.258.01:06:41.82#ibcon#read 5, iclass 36, count 0 2006.258.01:06:41.82#ibcon#about to read 6, iclass 36, count 0 2006.258.01:06:41.82#ibcon#read 6, iclass 36, count 0 2006.258.01:06:41.82#ibcon#end of sib2, iclass 36, count 0 2006.258.01:06:41.82#ibcon#*after write, iclass 36, count 0 2006.258.01:06:41.82#ibcon#*before return 0, iclass 36, count 0 2006.258.01:06:41.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:06:41.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:06:41.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.01:06:41.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.01:06:41.82$vck44/vb=6,4 2006.258.01:06:41.82#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.258.01:06:41.82#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.258.01:06:41.82#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:41.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:06:41.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:06:41.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:06:41.88#ibcon#enter wrdev, iclass 38, count 2 2006.258.01:06:41.88#ibcon#first serial, iclass 38, count 2 2006.258.01:06:41.88#ibcon#enter sib2, iclass 38, count 2 2006.258.01:06:41.88#ibcon#flushed, iclass 38, count 2 2006.258.01:06:41.88#ibcon#about to write, iclass 38, count 2 2006.258.01:06:41.88#ibcon#wrote, iclass 38, count 2 2006.258.01:06:41.88#ibcon#about to read 3, iclass 38, count 2 2006.258.01:06:41.90#ibcon#read 3, iclass 38, count 2 2006.258.01:06:41.90#ibcon#about to read 4, iclass 38, count 2 2006.258.01:06:41.90#ibcon#read 4, iclass 38, count 2 2006.258.01:06:41.90#ibcon#about to read 5, iclass 38, count 2 2006.258.01:06:41.90#ibcon#read 5, iclass 38, count 2 2006.258.01:06:41.90#ibcon#about to read 6, iclass 38, count 2 2006.258.01:06:41.90#ibcon#read 6, iclass 38, count 2 2006.258.01:06:41.90#ibcon#end of sib2, iclass 38, count 2 2006.258.01:06:41.90#ibcon#*mode == 0, iclass 38, count 2 2006.258.01:06:41.90#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.258.01:06:41.90#ibcon#[27=AT06-04\r\n] 2006.258.01:06:41.90#ibcon#*before write, iclass 38, count 2 2006.258.01:06:41.90#ibcon#enter sib2, iclass 38, count 2 2006.258.01:06:41.90#ibcon#flushed, iclass 38, count 2 2006.258.01:06:41.90#ibcon#about to write, iclass 38, count 2 2006.258.01:06:41.90#ibcon#wrote, iclass 38, count 2 2006.258.01:06:41.90#ibcon#about to read 3, iclass 38, count 2 2006.258.01:06:41.93#ibcon#read 3, iclass 38, count 2 2006.258.01:06:41.93#ibcon#about to read 4, iclass 38, count 2 2006.258.01:06:41.93#ibcon#read 4, iclass 38, count 2 2006.258.01:06:41.93#ibcon#about to read 5, iclass 38, count 2 2006.258.01:06:41.93#ibcon#read 5, iclass 38, count 2 2006.258.01:06:41.93#ibcon#about to read 6, iclass 38, count 2 2006.258.01:06:41.93#ibcon#read 6, iclass 38, count 2 2006.258.01:06:41.93#ibcon#end of sib2, iclass 38, count 2 2006.258.01:06:41.93#ibcon#*after write, iclass 38, count 2 2006.258.01:06:41.93#ibcon#*before return 0, iclass 38, count 2 2006.258.01:06:41.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:06:41.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:06:41.93#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.258.01:06:41.93#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:41.93#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:06:42.05#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:06:42.05#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:06:42.05#ibcon#enter wrdev, iclass 38, count 0 2006.258.01:06:42.05#ibcon#first serial, iclass 38, count 0 2006.258.01:06:42.05#ibcon#enter sib2, iclass 38, count 0 2006.258.01:06:42.05#ibcon#flushed, iclass 38, count 0 2006.258.01:06:42.05#ibcon#about to write, iclass 38, count 0 2006.258.01:06:42.05#ibcon#wrote, iclass 38, count 0 2006.258.01:06:42.05#ibcon#about to read 3, iclass 38, count 0 2006.258.01:06:42.07#ibcon#read 3, iclass 38, count 0 2006.258.01:06:42.07#ibcon#about to read 4, iclass 38, count 0 2006.258.01:06:42.07#ibcon#read 4, iclass 38, count 0 2006.258.01:06:42.07#ibcon#about to read 5, iclass 38, count 0 2006.258.01:06:42.07#ibcon#read 5, iclass 38, count 0 2006.258.01:06:42.07#ibcon#about to read 6, iclass 38, count 0 2006.258.01:06:42.07#ibcon#read 6, iclass 38, count 0 2006.258.01:06:42.07#ibcon#end of sib2, iclass 38, count 0 2006.258.01:06:42.07#ibcon#*mode == 0, iclass 38, count 0 2006.258.01:06:42.07#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.01:06:42.07#ibcon#[27=USB\r\n] 2006.258.01:06:42.07#ibcon#*before write, iclass 38, count 0 2006.258.01:06:42.07#ibcon#enter sib2, iclass 38, count 0 2006.258.01:06:42.07#ibcon#flushed, iclass 38, count 0 2006.258.01:06:42.07#ibcon#about to write, iclass 38, count 0 2006.258.01:06:42.07#ibcon#wrote, iclass 38, count 0 2006.258.01:06:42.07#ibcon#about to read 3, iclass 38, count 0 2006.258.01:06:42.10#ibcon#read 3, iclass 38, count 0 2006.258.01:06:42.10#ibcon#about to read 4, iclass 38, count 0 2006.258.01:06:42.10#ibcon#read 4, iclass 38, count 0 2006.258.01:06:42.10#ibcon#about to read 5, iclass 38, count 0 2006.258.01:06:42.10#ibcon#read 5, iclass 38, count 0 2006.258.01:06:42.10#ibcon#about to read 6, iclass 38, count 0 2006.258.01:06:42.10#ibcon#read 6, iclass 38, count 0 2006.258.01:06:42.10#ibcon#end of sib2, iclass 38, count 0 2006.258.01:06:42.10#ibcon#*after write, iclass 38, count 0 2006.258.01:06:42.10#ibcon#*before return 0, iclass 38, count 0 2006.258.01:06:42.10#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:06:42.10#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:06:42.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.01:06:42.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.01:06:42.10$vck44/vblo=7,734.99 2006.258.01:06:42.10#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.01:06:42.10#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.01:06:42.10#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:42.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:42.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:42.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:42.10#ibcon#enter wrdev, iclass 40, count 0 2006.258.01:06:42.10#ibcon#first serial, iclass 40, count 0 2006.258.01:06:42.10#ibcon#enter sib2, iclass 40, count 0 2006.258.01:06:42.10#ibcon#flushed, iclass 40, count 0 2006.258.01:06:42.10#ibcon#about to write, iclass 40, count 0 2006.258.01:06:42.10#ibcon#wrote, iclass 40, count 0 2006.258.01:06:42.10#ibcon#about to read 3, iclass 40, count 0 2006.258.01:06:42.12#ibcon#read 3, iclass 40, count 0 2006.258.01:06:42.12#ibcon#about to read 4, iclass 40, count 0 2006.258.01:06:42.12#ibcon#read 4, iclass 40, count 0 2006.258.01:06:42.12#ibcon#about to read 5, iclass 40, count 0 2006.258.01:06:42.12#ibcon#read 5, iclass 40, count 0 2006.258.01:06:42.12#ibcon#about to read 6, iclass 40, count 0 2006.258.01:06:42.12#ibcon#read 6, iclass 40, count 0 2006.258.01:06:42.12#ibcon#end of sib2, iclass 40, count 0 2006.258.01:06:42.12#ibcon#*mode == 0, iclass 40, count 0 2006.258.01:06:42.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.01:06:42.12#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.01:06:42.12#ibcon#*before write, iclass 40, count 0 2006.258.01:06:42.12#ibcon#enter sib2, iclass 40, count 0 2006.258.01:06:42.12#ibcon#flushed, iclass 40, count 0 2006.258.01:06:42.12#ibcon#about to write, iclass 40, count 0 2006.258.01:06:42.12#ibcon#wrote, iclass 40, count 0 2006.258.01:06:42.12#ibcon#about to read 3, iclass 40, count 0 2006.258.01:06:42.16#ibcon#read 3, iclass 40, count 0 2006.258.01:06:42.16#ibcon#about to read 4, iclass 40, count 0 2006.258.01:06:42.16#ibcon#read 4, iclass 40, count 0 2006.258.01:06:42.16#ibcon#about to read 5, iclass 40, count 0 2006.258.01:06:42.16#ibcon#read 5, iclass 40, count 0 2006.258.01:06:42.16#ibcon#about to read 6, iclass 40, count 0 2006.258.01:06:42.16#ibcon#read 6, iclass 40, count 0 2006.258.01:06:42.16#ibcon#end of sib2, iclass 40, count 0 2006.258.01:06:42.16#ibcon#*after write, iclass 40, count 0 2006.258.01:06:42.16#ibcon#*before return 0, iclass 40, count 0 2006.258.01:06:42.16#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:42.16#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:06:42.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.01:06:42.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.01:06:42.16$vck44/vb=7,4 2006.258.01:06:42.16#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.258.01:06:42.16#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.258.01:06:42.16#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:42.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:42.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:42.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:42.22#ibcon#enter wrdev, iclass 4, count 2 2006.258.01:06:42.22#ibcon#first serial, iclass 4, count 2 2006.258.01:06:42.22#ibcon#enter sib2, iclass 4, count 2 2006.258.01:06:42.22#ibcon#flushed, iclass 4, count 2 2006.258.01:06:42.22#ibcon#about to write, iclass 4, count 2 2006.258.01:06:42.22#ibcon#wrote, iclass 4, count 2 2006.258.01:06:42.22#ibcon#about to read 3, iclass 4, count 2 2006.258.01:06:42.24#ibcon#read 3, iclass 4, count 2 2006.258.01:06:42.24#ibcon#about to read 4, iclass 4, count 2 2006.258.01:06:42.24#ibcon#read 4, iclass 4, count 2 2006.258.01:06:42.24#ibcon#about to read 5, iclass 4, count 2 2006.258.01:06:42.24#ibcon#read 5, iclass 4, count 2 2006.258.01:06:42.24#ibcon#about to read 6, iclass 4, count 2 2006.258.01:06:42.24#ibcon#read 6, iclass 4, count 2 2006.258.01:06:42.24#ibcon#end of sib2, iclass 4, count 2 2006.258.01:06:42.24#ibcon#*mode == 0, iclass 4, count 2 2006.258.01:06:42.24#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.258.01:06:42.24#ibcon#[27=AT07-04\r\n] 2006.258.01:06:42.24#ibcon#*before write, iclass 4, count 2 2006.258.01:06:42.24#ibcon#enter sib2, iclass 4, count 2 2006.258.01:06:42.24#ibcon#flushed, iclass 4, count 2 2006.258.01:06:42.24#ibcon#about to write, iclass 4, count 2 2006.258.01:06:42.24#ibcon#wrote, iclass 4, count 2 2006.258.01:06:42.24#ibcon#about to read 3, iclass 4, count 2 2006.258.01:06:42.27#ibcon#read 3, iclass 4, count 2 2006.258.01:06:42.27#ibcon#about to read 4, iclass 4, count 2 2006.258.01:06:42.27#ibcon#read 4, iclass 4, count 2 2006.258.01:06:42.27#ibcon#about to read 5, iclass 4, count 2 2006.258.01:06:42.27#ibcon#read 5, iclass 4, count 2 2006.258.01:06:42.27#ibcon#about to read 6, iclass 4, count 2 2006.258.01:06:42.27#ibcon#read 6, iclass 4, count 2 2006.258.01:06:42.27#ibcon#end of sib2, iclass 4, count 2 2006.258.01:06:42.27#ibcon#*after write, iclass 4, count 2 2006.258.01:06:42.27#ibcon#*before return 0, iclass 4, count 2 2006.258.01:06:42.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:42.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:06:42.27#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.258.01:06:42.27#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:42.27#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:42.39#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:42.39#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:42.39#ibcon#enter wrdev, iclass 4, count 0 2006.258.01:06:42.39#ibcon#first serial, iclass 4, count 0 2006.258.01:06:42.39#ibcon#enter sib2, iclass 4, count 0 2006.258.01:06:42.39#ibcon#flushed, iclass 4, count 0 2006.258.01:06:42.39#ibcon#about to write, iclass 4, count 0 2006.258.01:06:42.39#ibcon#wrote, iclass 4, count 0 2006.258.01:06:42.39#ibcon#about to read 3, iclass 4, count 0 2006.258.01:06:42.41#ibcon#read 3, iclass 4, count 0 2006.258.01:06:42.41#ibcon#about to read 4, iclass 4, count 0 2006.258.01:06:42.41#ibcon#read 4, iclass 4, count 0 2006.258.01:06:42.41#ibcon#about to read 5, iclass 4, count 0 2006.258.01:06:42.41#ibcon#read 5, iclass 4, count 0 2006.258.01:06:42.41#ibcon#about to read 6, iclass 4, count 0 2006.258.01:06:42.41#ibcon#read 6, iclass 4, count 0 2006.258.01:06:42.41#ibcon#end of sib2, iclass 4, count 0 2006.258.01:06:42.41#ibcon#*mode == 0, iclass 4, count 0 2006.258.01:06:42.41#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.01:06:42.41#ibcon#[27=USB\r\n] 2006.258.01:06:42.41#ibcon#*before write, iclass 4, count 0 2006.258.01:06:42.41#ibcon#enter sib2, iclass 4, count 0 2006.258.01:06:42.41#ibcon#flushed, iclass 4, count 0 2006.258.01:06:42.41#ibcon#about to write, iclass 4, count 0 2006.258.01:06:42.41#ibcon#wrote, iclass 4, count 0 2006.258.01:06:42.41#ibcon#about to read 3, iclass 4, count 0 2006.258.01:06:42.44#ibcon#read 3, iclass 4, count 0 2006.258.01:06:42.44#ibcon#about to read 4, iclass 4, count 0 2006.258.01:06:42.44#ibcon#read 4, iclass 4, count 0 2006.258.01:06:42.44#ibcon#about to read 5, iclass 4, count 0 2006.258.01:06:42.44#ibcon#read 5, iclass 4, count 0 2006.258.01:06:42.44#ibcon#about to read 6, iclass 4, count 0 2006.258.01:06:42.44#ibcon#read 6, iclass 4, count 0 2006.258.01:06:42.44#ibcon#end of sib2, iclass 4, count 0 2006.258.01:06:42.44#ibcon#*after write, iclass 4, count 0 2006.258.01:06:42.44#ibcon#*before return 0, iclass 4, count 0 2006.258.01:06:42.44#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:42.44#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:06:42.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.01:06:42.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.01:06:42.44$vck44/vblo=8,744.99 2006.258.01:06:42.44#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.01:06:42.44#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.01:06:42.44#ibcon#ireg 17 cls_cnt 0 2006.258.01:06:42.44#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:42.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:42.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:42.44#ibcon#enter wrdev, iclass 6, count 0 2006.258.01:06:42.44#ibcon#first serial, iclass 6, count 0 2006.258.01:06:42.44#ibcon#enter sib2, iclass 6, count 0 2006.258.01:06:42.44#ibcon#flushed, iclass 6, count 0 2006.258.01:06:42.44#ibcon#about to write, iclass 6, count 0 2006.258.01:06:42.44#ibcon#wrote, iclass 6, count 0 2006.258.01:06:42.44#ibcon#about to read 3, iclass 6, count 0 2006.258.01:06:42.46#ibcon#read 3, iclass 6, count 0 2006.258.01:06:42.46#ibcon#about to read 4, iclass 6, count 0 2006.258.01:06:42.46#ibcon#read 4, iclass 6, count 0 2006.258.01:06:42.46#ibcon#about to read 5, iclass 6, count 0 2006.258.01:06:42.46#ibcon#read 5, iclass 6, count 0 2006.258.01:06:42.46#ibcon#about to read 6, iclass 6, count 0 2006.258.01:06:42.46#ibcon#read 6, iclass 6, count 0 2006.258.01:06:42.46#ibcon#end of sib2, iclass 6, count 0 2006.258.01:06:42.46#ibcon#*mode == 0, iclass 6, count 0 2006.258.01:06:42.46#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.01:06:42.46#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.01:06:42.46#ibcon#*before write, iclass 6, count 0 2006.258.01:06:42.46#ibcon#enter sib2, iclass 6, count 0 2006.258.01:06:42.46#ibcon#flushed, iclass 6, count 0 2006.258.01:06:42.46#ibcon#about to write, iclass 6, count 0 2006.258.01:06:42.46#ibcon#wrote, iclass 6, count 0 2006.258.01:06:42.46#ibcon#about to read 3, iclass 6, count 0 2006.258.01:06:42.50#ibcon#read 3, iclass 6, count 0 2006.258.01:06:42.50#ibcon#about to read 4, iclass 6, count 0 2006.258.01:06:42.50#ibcon#read 4, iclass 6, count 0 2006.258.01:06:42.50#ibcon#about to read 5, iclass 6, count 0 2006.258.01:06:42.50#ibcon#read 5, iclass 6, count 0 2006.258.01:06:42.50#ibcon#about to read 6, iclass 6, count 0 2006.258.01:06:42.50#ibcon#read 6, iclass 6, count 0 2006.258.01:06:42.50#ibcon#end of sib2, iclass 6, count 0 2006.258.01:06:42.50#ibcon#*after write, iclass 6, count 0 2006.258.01:06:42.50#ibcon#*before return 0, iclass 6, count 0 2006.258.01:06:42.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:42.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:06:42.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.01:06:42.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.01:06:42.50$vck44/vb=8,4 2006.258.01:06:42.50#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.258.01:06:42.50#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.258.01:06:42.50#ibcon#ireg 11 cls_cnt 2 2006.258.01:06:42.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:42.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:42.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:42.56#ibcon#enter wrdev, iclass 10, count 2 2006.258.01:06:42.56#ibcon#first serial, iclass 10, count 2 2006.258.01:06:42.56#ibcon#enter sib2, iclass 10, count 2 2006.258.01:06:42.56#ibcon#flushed, iclass 10, count 2 2006.258.01:06:42.56#ibcon#about to write, iclass 10, count 2 2006.258.01:06:42.56#ibcon#wrote, iclass 10, count 2 2006.258.01:06:42.56#ibcon#about to read 3, iclass 10, count 2 2006.258.01:06:42.58#ibcon#read 3, iclass 10, count 2 2006.258.01:06:42.58#ibcon#about to read 4, iclass 10, count 2 2006.258.01:06:42.58#ibcon#read 4, iclass 10, count 2 2006.258.01:06:42.58#ibcon#about to read 5, iclass 10, count 2 2006.258.01:06:42.58#ibcon#read 5, iclass 10, count 2 2006.258.01:06:42.58#ibcon#about to read 6, iclass 10, count 2 2006.258.01:06:42.58#ibcon#read 6, iclass 10, count 2 2006.258.01:06:42.58#ibcon#end of sib2, iclass 10, count 2 2006.258.01:06:42.58#ibcon#*mode == 0, iclass 10, count 2 2006.258.01:06:42.58#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.258.01:06:42.58#ibcon#[27=AT08-04\r\n] 2006.258.01:06:42.58#ibcon#*before write, iclass 10, count 2 2006.258.01:06:42.58#ibcon#enter sib2, iclass 10, count 2 2006.258.01:06:42.58#ibcon#flushed, iclass 10, count 2 2006.258.01:06:42.58#ibcon#about to write, iclass 10, count 2 2006.258.01:06:42.58#ibcon#wrote, iclass 10, count 2 2006.258.01:06:42.58#ibcon#about to read 3, iclass 10, count 2 2006.258.01:06:42.61#ibcon#read 3, iclass 10, count 2 2006.258.01:06:42.61#ibcon#about to read 4, iclass 10, count 2 2006.258.01:06:42.62#ibcon#read 4, iclass 10, count 2 2006.258.01:06:42.62#ibcon#about to read 5, iclass 10, count 2 2006.258.01:06:42.62#ibcon#read 5, iclass 10, count 2 2006.258.01:06:42.62#ibcon#about to read 6, iclass 10, count 2 2006.258.01:06:42.62#ibcon#read 6, iclass 10, count 2 2006.258.01:06:42.62#ibcon#end of sib2, iclass 10, count 2 2006.258.01:06:42.62#ibcon#*after write, iclass 10, count 2 2006.258.01:06:42.62#ibcon#*before return 0, iclass 10, count 2 2006.258.01:06:42.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:42.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:06:42.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.258.01:06:42.62#ibcon#ireg 7 cls_cnt 0 2006.258.01:06:42.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:42.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:42.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:42.74#ibcon#enter wrdev, iclass 10, count 0 2006.258.01:06:42.74#ibcon#first serial, iclass 10, count 0 2006.258.01:06:42.74#ibcon#enter sib2, iclass 10, count 0 2006.258.01:06:42.74#ibcon#flushed, iclass 10, count 0 2006.258.01:06:42.74#ibcon#about to write, iclass 10, count 0 2006.258.01:06:42.74#ibcon#wrote, iclass 10, count 0 2006.258.01:06:42.74#ibcon#about to read 3, iclass 10, count 0 2006.258.01:06:42.76#ibcon#read 3, iclass 10, count 0 2006.258.01:06:42.76#ibcon#about to read 4, iclass 10, count 0 2006.258.01:06:42.76#ibcon#read 4, iclass 10, count 0 2006.258.01:06:42.76#ibcon#about to read 5, iclass 10, count 0 2006.258.01:06:42.76#ibcon#read 5, iclass 10, count 0 2006.258.01:06:42.76#ibcon#about to read 6, iclass 10, count 0 2006.258.01:06:42.76#ibcon#read 6, iclass 10, count 0 2006.258.01:06:42.76#ibcon#end of sib2, iclass 10, count 0 2006.258.01:06:42.76#ibcon#*mode == 0, iclass 10, count 0 2006.258.01:06:42.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.01:06:42.76#ibcon#[27=USB\r\n] 2006.258.01:06:42.76#ibcon#*before write, iclass 10, count 0 2006.258.01:06:42.76#ibcon#enter sib2, iclass 10, count 0 2006.258.01:06:42.76#ibcon#flushed, iclass 10, count 0 2006.258.01:06:42.76#ibcon#about to write, iclass 10, count 0 2006.258.01:06:42.76#ibcon#wrote, iclass 10, count 0 2006.258.01:06:42.76#ibcon#about to read 3, iclass 10, count 0 2006.258.01:06:42.79#ibcon#read 3, iclass 10, count 0 2006.258.01:06:42.79#ibcon#about to read 4, iclass 10, count 0 2006.258.01:06:42.79#ibcon#read 4, iclass 10, count 0 2006.258.01:06:42.79#ibcon#about to read 5, iclass 10, count 0 2006.258.01:06:42.79#ibcon#read 5, iclass 10, count 0 2006.258.01:06:42.79#ibcon#about to read 6, iclass 10, count 0 2006.258.01:06:42.79#ibcon#read 6, iclass 10, count 0 2006.258.01:06:42.79#ibcon#end of sib2, iclass 10, count 0 2006.258.01:06:42.79#ibcon#*after write, iclass 10, count 0 2006.258.01:06:42.79#ibcon#*before return 0, iclass 10, count 0 2006.258.01:06:42.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:42.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:06:42.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.01:06:42.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.01:06:42.79$vck44/vabw=wide 2006.258.01:06:42.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.01:06:42.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.01:06:42.79#ibcon#ireg 8 cls_cnt 0 2006.258.01:06:42.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:42.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:42.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:42.79#ibcon#enter wrdev, iclass 12, count 0 2006.258.01:06:42.79#ibcon#first serial, iclass 12, count 0 2006.258.01:06:42.79#ibcon#enter sib2, iclass 12, count 0 2006.258.01:06:42.79#ibcon#flushed, iclass 12, count 0 2006.258.01:06:42.79#ibcon#about to write, iclass 12, count 0 2006.258.01:06:42.79#ibcon#wrote, iclass 12, count 0 2006.258.01:06:42.79#ibcon#about to read 3, iclass 12, count 0 2006.258.01:06:42.81#ibcon#read 3, iclass 12, count 0 2006.258.01:06:42.81#ibcon#about to read 4, iclass 12, count 0 2006.258.01:06:42.81#ibcon#read 4, iclass 12, count 0 2006.258.01:06:42.81#ibcon#about to read 5, iclass 12, count 0 2006.258.01:06:42.81#ibcon#read 5, iclass 12, count 0 2006.258.01:06:42.81#ibcon#about to read 6, iclass 12, count 0 2006.258.01:06:42.81#ibcon#read 6, iclass 12, count 0 2006.258.01:06:42.81#ibcon#end of sib2, iclass 12, count 0 2006.258.01:06:42.81#ibcon#*mode == 0, iclass 12, count 0 2006.258.01:06:42.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.01:06:42.81#ibcon#[25=BW32\r\n] 2006.258.01:06:42.81#ibcon#*before write, iclass 12, count 0 2006.258.01:06:42.81#ibcon#enter sib2, iclass 12, count 0 2006.258.01:06:42.81#ibcon#flushed, iclass 12, count 0 2006.258.01:06:42.81#ibcon#about to write, iclass 12, count 0 2006.258.01:06:42.81#ibcon#wrote, iclass 12, count 0 2006.258.01:06:42.81#ibcon#about to read 3, iclass 12, count 0 2006.258.01:06:42.84#ibcon#read 3, iclass 12, count 0 2006.258.01:06:42.84#ibcon#about to read 4, iclass 12, count 0 2006.258.01:06:42.84#ibcon#read 4, iclass 12, count 0 2006.258.01:06:42.84#ibcon#about to read 5, iclass 12, count 0 2006.258.01:06:42.84#ibcon#read 5, iclass 12, count 0 2006.258.01:06:42.84#ibcon#about to read 6, iclass 12, count 0 2006.258.01:06:42.84#ibcon#read 6, iclass 12, count 0 2006.258.01:06:42.84#ibcon#end of sib2, iclass 12, count 0 2006.258.01:06:42.84#ibcon#*after write, iclass 12, count 0 2006.258.01:06:42.84#ibcon#*before return 0, iclass 12, count 0 2006.258.01:06:42.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:42.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:06:42.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.01:06:42.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.01:06:42.84$vck44/vbbw=wide 2006.258.01:06:42.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.01:06:42.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.01:06:42.84#ibcon#ireg 8 cls_cnt 0 2006.258.01:06:42.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:06:42.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:06:42.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:06:42.91#ibcon#enter wrdev, iclass 14, count 0 2006.258.01:06:42.91#ibcon#first serial, iclass 14, count 0 2006.258.01:06:42.91#ibcon#enter sib2, iclass 14, count 0 2006.258.01:06:42.91#ibcon#flushed, iclass 14, count 0 2006.258.01:06:42.91#ibcon#about to write, iclass 14, count 0 2006.258.01:06:42.91#ibcon#wrote, iclass 14, count 0 2006.258.01:06:42.91#ibcon#about to read 3, iclass 14, count 0 2006.258.01:06:42.93#ibcon#read 3, iclass 14, count 0 2006.258.01:06:42.93#ibcon#about to read 4, iclass 14, count 0 2006.258.01:06:42.93#ibcon#read 4, iclass 14, count 0 2006.258.01:06:42.93#ibcon#about to read 5, iclass 14, count 0 2006.258.01:06:42.93#ibcon#read 5, iclass 14, count 0 2006.258.01:06:42.93#ibcon#about to read 6, iclass 14, count 0 2006.258.01:06:42.93#ibcon#read 6, iclass 14, count 0 2006.258.01:06:42.93#ibcon#end of sib2, iclass 14, count 0 2006.258.01:06:42.93#ibcon#*mode == 0, iclass 14, count 0 2006.258.01:06:42.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.01:06:42.93#ibcon#[27=BW32\r\n] 2006.258.01:06:42.93#ibcon#*before write, iclass 14, count 0 2006.258.01:06:42.93#ibcon#enter sib2, iclass 14, count 0 2006.258.01:06:42.93#ibcon#flushed, iclass 14, count 0 2006.258.01:06:42.93#ibcon#about to write, iclass 14, count 0 2006.258.01:06:42.93#ibcon#wrote, iclass 14, count 0 2006.258.01:06:42.93#ibcon#about to read 3, iclass 14, count 0 2006.258.01:06:42.96#ibcon#read 3, iclass 14, count 0 2006.258.01:06:42.96#ibcon#about to read 4, iclass 14, count 0 2006.258.01:06:42.96#ibcon#read 4, iclass 14, count 0 2006.258.01:06:42.96#ibcon#about to read 5, iclass 14, count 0 2006.258.01:06:42.96#ibcon#read 5, iclass 14, count 0 2006.258.01:06:42.96#ibcon#about to read 6, iclass 14, count 0 2006.258.01:06:42.96#ibcon#read 6, iclass 14, count 0 2006.258.01:06:42.96#ibcon#end of sib2, iclass 14, count 0 2006.258.01:06:42.96#ibcon#*after write, iclass 14, count 0 2006.258.01:06:42.96#ibcon#*before return 0, iclass 14, count 0 2006.258.01:06:42.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:06:42.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:06:42.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.01:06:42.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.01:06:42.96$setupk4/ifdk4 2006.258.01:06:42.96$ifdk4/lo= 2006.258.01:06:42.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.01:06:42.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.01:06:42.96$ifdk4/patch= 2006.258.01:06:42.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.01:06:42.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.01:06:42.96$setupk4/!*+20s 2006.258.01:06:49.00#abcon#<5=/02 2.3 8.1 22.68 751016.1\r\n> 2006.258.01:06:49.02#abcon#{5=INTERFACE CLEAR} 2006.258.01:06:49.08#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:06:57.13#trakl#Source acquired 2006.258.01:06:57.34$setupk4/"tpicd 2006.258.01:06:57.34$setupk4/echo=off 2006.258.01:06:57.34$setupk4/xlog=off 2006.258.01:06:57.34:!2006.258.01:11:33 2006.258.01:06:59.13#flagr#flagr/antenna,acquired 2006.258.01:11:33.00:preob 2006.258.01:11:33.14/onsource/TRACKING 2006.258.01:11:33.14:!2006.258.01:11:43 2006.258.01:11:43.00:"tape 2006.258.01:11:43.00:"st=record 2006.258.01:11:43.00:data_valid=on 2006.258.01:11:43.00:midob 2006.258.01:11:44.14/onsource/TRACKING 2006.258.01:11:44.14/wx/22.62,1016.1,75 2006.258.01:11:44.36/cable/+6.4765E-03 2006.258.01:11:45.45/va/01,08,usb,yes,32,34 2006.258.01:11:45.45/va/02,07,usb,yes,34,35 2006.258.01:11:45.45/va/03,08,usb,yes,30,32 2006.258.01:11:45.45/va/04,07,usb,yes,35,37 2006.258.01:11:45.45/va/05,04,usb,yes,31,32 2006.258.01:11:45.45/va/06,04,usb,yes,35,34 2006.258.01:11:45.45/va/07,04,usb,yes,36,36 2006.258.01:11:45.45/va/08,04,usb,yes,30,37 2006.258.01:11:45.68/valo/01,524.99,yes,locked 2006.258.01:11:45.68/valo/02,534.99,yes,locked 2006.258.01:11:45.68/valo/03,564.99,yes,locked 2006.258.01:11:45.68/valo/04,624.99,yes,locked 2006.258.01:11:45.68/valo/05,734.99,yes,locked 2006.258.01:11:45.68/valo/06,814.99,yes,locked 2006.258.01:11:45.68/valo/07,864.99,yes,locked 2006.258.01:11:45.68/valo/08,884.99,yes,locked 2006.258.01:11:46.77/vb/01,04,usb,yes,31,29 2006.258.01:11:46.77/vb/02,05,usb,yes,30,29 2006.258.01:11:46.77/vb/03,04,usb,yes,31,34 2006.258.01:11:46.77/vb/04,05,usb,yes,31,30 2006.258.01:11:46.77/vb/05,04,usb,yes,27,30 2006.258.01:11:46.77/vb/06,04,usb,yes,32,28 2006.258.01:11:46.77/vb/07,04,usb,yes,32,32 2006.258.01:11:46.77/vb/08,04,usb,yes,29,33 2006.258.01:11:47.01/vblo/01,629.99,yes,locked 2006.258.01:11:47.01/vblo/02,634.99,yes,locked 2006.258.01:11:47.01/vblo/03,649.99,yes,locked 2006.258.01:11:47.01/vblo/04,679.99,yes,locked 2006.258.01:11:47.01/vblo/05,709.99,yes,locked 2006.258.01:11:47.01/vblo/06,719.99,yes,locked 2006.258.01:11:47.01/vblo/07,734.99,yes,locked 2006.258.01:11:47.01/vblo/08,744.99,yes,locked 2006.258.01:11:47.16/vabw/8 2006.258.01:11:47.31/vbbw/8 2006.258.01:11:47.40/xfe/off,on,14.7 2006.258.01:11:47.79/ifatt/23,28,28,28 2006.258.01:11:48.08/fmout-gps/S +4.54E-07 2006.258.01:11:48.12:!2006.258.01:13:43 2006.258.01:13:43.00:data_valid=off 2006.258.01:13:43.00:"et 2006.258.01:13:43.00:!+3s 2006.258.01:13:46.02:"tape 2006.258.01:13:46.02:postob 2006.258.01:13:46.19/cable/+6.4745E-03 2006.258.01:13:46.19/wx/22.68,1016.0,75 2006.258.01:13:47.08/fmout-gps/S +4.54E-07 2006.258.01:13:47.08:scan_name=258-0116,jd0609,60 2006.258.01:13:47.08:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.258.01:13:47.14#flagr#flagr/antenna,new-source 2006.258.01:13:48.14:checkk5 2006.258.01:13:48.53/chk_autoobs//k5ts1/ autoobs is running! 2006.258.01:13:48.93/chk_autoobs//k5ts2/ autoobs is running! 2006.258.01:13:49.34/chk_autoobs//k5ts3/ autoobs is running! 2006.258.01:13:49.73/chk_autoobs//k5ts4/ autoobs is running! 2006.258.01:13:50.12/chk_obsdata//k5ts1/T2580111??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.258.01:13:50.52/chk_obsdata//k5ts2/T2580111??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.258.01:13:50.92/chk_obsdata//k5ts3/T2580111??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.258.01:13:51.31/chk_obsdata//k5ts4/T2580111??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.258.01:13:52.04/k5log//k5ts1_log_newline 2006.258.01:13:52.74/k5log//k5ts2_log_newline 2006.258.01:13:53.48/k5log//k5ts3_log_newline 2006.258.01:13:54.18/k5log//k5ts4_log_newline 2006.258.01:13:54.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:13:54.20:setupk4=1 2006.258.01:13:54.20$setupk4/echo=on 2006.258.01:13:54.20$setupk4/pcalon 2006.258.01:13:54.20$pcalon/"no phase cal control is implemented here 2006.258.01:13:54.20$setupk4/"tpicd=stop 2006.258.01:13:54.20$setupk4/"rec=synch_on 2006.258.01:13:54.20$setupk4/"rec_mode=128 2006.258.01:13:54.20$setupk4/!* 2006.258.01:13:54.20$setupk4/recpk4 2006.258.01:13:54.20$recpk4/recpatch= 2006.258.01:13:54.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.01:13:54.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.01:13:54.21$setupk4/vck44 2006.258.01:13:54.21$vck44/valo=1,524.99 2006.258.01:13:54.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.01:13:54.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.01:13:54.21#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:54.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:54.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:54.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:54.21#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:13:54.21#ibcon#first serial, iclass 5, count 0 2006.258.01:13:54.21#ibcon#enter sib2, iclass 5, count 0 2006.258.01:13:54.21#ibcon#flushed, iclass 5, count 0 2006.258.01:13:54.21#ibcon#about to write, iclass 5, count 0 2006.258.01:13:54.21#ibcon#wrote, iclass 5, count 0 2006.258.01:13:54.21#ibcon#about to read 3, iclass 5, count 0 2006.258.01:13:54.23#ibcon#read 3, iclass 5, count 0 2006.258.01:13:54.23#ibcon#about to read 4, iclass 5, count 0 2006.258.01:13:54.23#ibcon#read 4, iclass 5, count 0 2006.258.01:13:54.23#ibcon#about to read 5, iclass 5, count 0 2006.258.01:13:54.23#ibcon#read 5, iclass 5, count 0 2006.258.01:13:54.23#ibcon#about to read 6, iclass 5, count 0 2006.258.01:13:54.23#ibcon#read 6, iclass 5, count 0 2006.258.01:13:54.23#ibcon#end of sib2, iclass 5, count 0 2006.258.01:13:54.23#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:13:54.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:13:54.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.01:13:54.23#ibcon#*before write, iclass 5, count 0 2006.258.01:13:54.23#ibcon#enter sib2, iclass 5, count 0 2006.258.01:13:54.23#ibcon#flushed, iclass 5, count 0 2006.258.01:13:54.23#ibcon#about to write, iclass 5, count 0 2006.258.01:13:54.23#ibcon#wrote, iclass 5, count 0 2006.258.01:13:54.23#ibcon#about to read 3, iclass 5, count 0 2006.258.01:13:54.28#ibcon#read 3, iclass 5, count 0 2006.258.01:13:54.28#ibcon#about to read 4, iclass 5, count 0 2006.258.01:13:54.28#ibcon#read 4, iclass 5, count 0 2006.258.01:13:54.28#ibcon#about to read 5, iclass 5, count 0 2006.258.01:13:54.28#ibcon#read 5, iclass 5, count 0 2006.258.01:13:54.28#ibcon#about to read 6, iclass 5, count 0 2006.258.01:13:54.28#ibcon#read 6, iclass 5, count 0 2006.258.01:13:54.28#ibcon#end of sib2, iclass 5, count 0 2006.258.01:13:54.28#ibcon#*after write, iclass 5, count 0 2006.258.01:13:54.28#ibcon#*before return 0, iclass 5, count 0 2006.258.01:13:54.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:54.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:54.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:13:54.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:13:54.28$vck44/va=1,8 2006.258.01:13:54.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.01:13:54.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.01:13:54.28#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:54.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:54.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:54.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:54.28#ibcon#enter wrdev, iclass 7, count 2 2006.258.01:13:54.28#ibcon#first serial, iclass 7, count 2 2006.258.01:13:54.28#ibcon#enter sib2, iclass 7, count 2 2006.258.01:13:54.28#ibcon#flushed, iclass 7, count 2 2006.258.01:13:54.28#ibcon#about to write, iclass 7, count 2 2006.258.01:13:54.28#ibcon#wrote, iclass 7, count 2 2006.258.01:13:54.28#ibcon#about to read 3, iclass 7, count 2 2006.258.01:13:54.30#ibcon#read 3, iclass 7, count 2 2006.258.01:13:54.30#ibcon#about to read 4, iclass 7, count 2 2006.258.01:13:54.30#ibcon#read 4, iclass 7, count 2 2006.258.01:13:54.30#ibcon#about to read 5, iclass 7, count 2 2006.258.01:13:54.30#ibcon#read 5, iclass 7, count 2 2006.258.01:13:54.30#ibcon#about to read 6, iclass 7, count 2 2006.258.01:13:54.30#ibcon#read 6, iclass 7, count 2 2006.258.01:13:54.30#ibcon#end of sib2, iclass 7, count 2 2006.258.01:13:54.30#ibcon#*mode == 0, iclass 7, count 2 2006.258.01:13:54.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.01:13:54.30#ibcon#[25=AT01-08\r\n] 2006.258.01:13:54.30#ibcon#*before write, iclass 7, count 2 2006.258.01:13:54.30#ibcon#enter sib2, iclass 7, count 2 2006.258.01:13:54.30#ibcon#flushed, iclass 7, count 2 2006.258.01:13:54.30#ibcon#about to write, iclass 7, count 2 2006.258.01:13:54.30#ibcon#wrote, iclass 7, count 2 2006.258.01:13:54.30#ibcon#about to read 3, iclass 7, count 2 2006.258.01:13:54.33#ibcon#read 3, iclass 7, count 2 2006.258.01:13:54.33#ibcon#about to read 4, iclass 7, count 2 2006.258.01:13:54.33#ibcon#read 4, iclass 7, count 2 2006.258.01:13:54.33#ibcon#about to read 5, iclass 7, count 2 2006.258.01:13:54.33#ibcon#read 5, iclass 7, count 2 2006.258.01:13:54.33#ibcon#about to read 6, iclass 7, count 2 2006.258.01:13:54.33#ibcon#read 6, iclass 7, count 2 2006.258.01:13:54.33#ibcon#end of sib2, iclass 7, count 2 2006.258.01:13:54.33#ibcon#*after write, iclass 7, count 2 2006.258.01:13:54.33#ibcon#*before return 0, iclass 7, count 2 2006.258.01:13:54.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:54.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:54.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.01:13:54.33#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:54.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:54.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:54.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:54.45#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:13:54.45#ibcon#first serial, iclass 7, count 0 2006.258.01:13:54.45#ibcon#enter sib2, iclass 7, count 0 2006.258.01:13:54.45#ibcon#flushed, iclass 7, count 0 2006.258.01:13:54.45#ibcon#about to write, iclass 7, count 0 2006.258.01:13:54.45#ibcon#wrote, iclass 7, count 0 2006.258.01:13:54.45#ibcon#about to read 3, iclass 7, count 0 2006.258.01:13:54.47#ibcon#read 3, iclass 7, count 0 2006.258.01:13:54.47#ibcon#about to read 4, iclass 7, count 0 2006.258.01:13:54.47#ibcon#read 4, iclass 7, count 0 2006.258.01:13:54.47#ibcon#about to read 5, iclass 7, count 0 2006.258.01:13:54.47#ibcon#read 5, iclass 7, count 0 2006.258.01:13:54.47#ibcon#about to read 6, iclass 7, count 0 2006.258.01:13:54.47#ibcon#read 6, iclass 7, count 0 2006.258.01:13:54.47#ibcon#end of sib2, iclass 7, count 0 2006.258.01:13:54.47#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:13:54.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:13:54.47#ibcon#[25=USB\r\n] 2006.258.01:13:54.47#ibcon#*before write, iclass 7, count 0 2006.258.01:13:54.47#ibcon#enter sib2, iclass 7, count 0 2006.258.01:13:54.47#ibcon#flushed, iclass 7, count 0 2006.258.01:13:54.47#ibcon#about to write, iclass 7, count 0 2006.258.01:13:54.47#ibcon#wrote, iclass 7, count 0 2006.258.01:13:54.47#ibcon#about to read 3, iclass 7, count 0 2006.258.01:13:54.50#ibcon#read 3, iclass 7, count 0 2006.258.01:13:54.50#ibcon#about to read 4, iclass 7, count 0 2006.258.01:13:54.50#ibcon#read 4, iclass 7, count 0 2006.258.01:13:54.50#ibcon#about to read 5, iclass 7, count 0 2006.258.01:13:54.50#ibcon#read 5, iclass 7, count 0 2006.258.01:13:54.50#ibcon#about to read 6, iclass 7, count 0 2006.258.01:13:54.50#ibcon#read 6, iclass 7, count 0 2006.258.01:13:54.50#ibcon#end of sib2, iclass 7, count 0 2006.258.01:13:54.50#ibcon#*after write, iclass 7, count 0 2006.258.01:13:54.50#ibcon#*before return 0, iclass 7, count 0 2006.258.01:13:54.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:54.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:54.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:13:54.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:13:54.50$vck44/valo=2,534.99 2006.258.01:13:54.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.01:13:54.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.01:13:54.50#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:54.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:54.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:54.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:54.50#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:13:54.50#ibcon#first serial, iclass 11, count 0 2006.258.01:13:54.50#ibcon#enter sib2, iclass 11, count 0 2006.258.01:13:54.50#ibcon#flushed, iclass 11, count 0 2006.258.01:13:54.50#ibcon#about to write, iclass 11, count 0 2006.258.01:13:54.50#ibcon#wrote, iclass 11, count 0 2006.258.01:13:54.50#ibcon#about to read 3, iclass 11, count 0 2006.258.01:13:54.52#ibcon#read 3, iclass 11, count 0 2006.258.01:13:54.52#ibcon#about to read 4, iclass 11, count 0 2006.258.01:13:54.52#ibcon#read 4, iclass 11, count 0 2006.258.01:13:54.52#ibcon#about to read 5, iclass 11, count 0 2006.258.01:13:54.52#ibcon#read 5, iclass 11, count 0 2006.258.01:13:54.52#ibcon#about to read 6, iclass 11, count 0 2006.258.01:13:54.52#ibcon#read 6, iclass 11, count 0 2006.258.01:13:54.52#ibcon#end of sib2, iclass 11, count 0 2006.258.01:13:54.52#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:13:54.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:13:54.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.01:13:54.52#ibcon#*before write, iclass 11, count 0 2006.258.01:13:54.52#ibcon#enter sib2, iclass 11, count 0 2006.258.01:13:54.52#ibcon#flushed, iclass 11, count 0 2006.258.01:13:54.52#ibcon#about to write, iclass 11, count 0 2006.258.01:13:54.52#ibcon#wrote, iclass 11, count 0 2006.258.01:13:54.52#ibcon#about to read 3, iclass 11, count 0 2006.258.01:13:54.56#ibcon#read 3, iclass 11, count 0 2006.258.01:13:54.56#ibcon#about to read 4, iclass 11, count 0 2006.258.01:13:54.56#ibcon#read 4, iclass 11, count 0 2006.258.01:13:54.56#ibcon#about to read 5, iclass 11, count 0 2006.258.01:13:54.56#ibcon#read 5, iclass 11, count 0 2006.258.01:13:54.56#ibcon#about to read 6, iclass 11, count 0 2006.258.01:13:54.56#ibcon#read 6, iclass 11, count 0 2006.258.01:13:54.56#ibcon#end of sib2, iclass 11, count 0 2006.258.01:13:54.56#ibcon#*after write, iclass 11, count 0 2006.258.01:13:54.56#ibcon#*before return 0, iclass 11, count 0 2006.258.01:13:54.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:54.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:54.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:13:54.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:13:54.56$vck44/va=2,7 2006.258.01:13:54.56#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.01:13:54.56#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.01:13:54.56#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:54.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:54.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:54.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:54.62#ibcon#enter wrdev, iclass 13, count 2 2006.258.01:13:54.62#ibcon#first serial, iclass 13, count 2 2006.258.01:13:54.62#ibcon#enter sib2, iclass 13, count 2 2006.258.01:13:54.62#ibcon#flushed, iclass 13, count 2 2006.258.01:13:54.62#ibcon#about to write, iclass 13, count 2 2006.258.01:13:54.62#ibcon#wrote, iclass 13, count 2 2006.258.01:13:54.62#ibcon#about to read 3, iclass 13, count 2 2006.258.01:13:54.64#ibcon#read 3, iclass 13, count 2 2006.258.01:13:54.64#ibcon#about to read 4, iclass 13, count 2 2006.258.01:13:54.64#ibcon#read 4, iclass 13, count 2 2006.258.01:13:54.64#ibcon#about to read 5, iclass 13, count 2 2006.258.01:13:54.64#ibcon#read 5, iclass 13, count 2 2006.258.01:13:54.64#ibcon#about to read 6, iclass 13, count 2 2006.258.01:13:54.64#ibcon#read 6, iclass 13, count 2 2006.258.01:13:54.64#ibcon#end of sib2, iclass 13, count 2 2006.258.01:13:54.64#ibcon#*mode == 0, iclass 13, count 2 2006.258.01:13:54.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.01:13:54.64#ibcon#[25=AT02-07\r\n] 2006.258.01:13:54.64#ibcon#*before write, iclass 13, count 2 2006.258.01:13:54.64#ibcon#enter sib2, iclass 13, count 2 2006.258.01:13:54.64#ibcon#flushed, iclass 13, count 2 2006.258.01:13:54.64#ibcon#about to write, iclass 13, count 2 2006.258.01:13:54.64#ibcon#wrote, iclass 13, count 2 2006.258.01:13:54.64#ibcon#about to read 3, iclass 13, count 2 2006.258.01:13:54.67#ibcon#read 3, iclass 13, count 2 2006.258.01:13:54.67#ibcon#about to read 4, iclass 13, count 2 2006.258.01:13:54.67#ibcon#read 4, iclass 13, count 2 2006.258.01:13:54.67#ibcon#about to read 5, iclass 13, count 2 2006.258.01:13:54.67#ibcon#read 5, iclass 13, count 2 2006.258.01:13:54.67#ibcon#about to read 6, iclass 13, count 2 2006.258.01:13:54.67#ibcon#read 6, iclass 13, count 2 2006.258.01:13:54.67#ibcon#end of sib2, iclass 13, count 2 2006.258.01:13:54.67#ibcon#*after write, iclass 13, count 2 2006.258.01:13:54.67#ibcon#*before return 0, iclass 13, count 2 2006.258.01:13:54.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:54.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:54.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.01:13:54.67#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:54.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:54.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:54.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:54.79#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:13:54.79#ibcon#first serial, iclass 13, count 0 2006.258.01:13:54.79#ibcon#enter sib2, iclass 13, count 0 2006.258.01:13:54.79#ibcon#flushed, iclass 13, count 0 2006.258.01:13:54.79#ibcon#about to write, iclass 13, count 0 2006.258.01:13:54.79#ibcon#wrote, iclass 13, count 0 2006.258.01:13:54.79#ibcon#about to read 3, iclass 13, count 0 2006.258.01:13:54.81#ibcon#read 3, iclass 13, count 0 2006.258.01:13:54.81#ibcon#about to read 4, iclass 13, count 0 2006.258.01:13:54.81#ibcon#read 4, iclass 13, count 0 2006.258.01:13:54.81#ibcon#about to read 5, iclass 13, count 0 2006.258.01:13:54.81#ibcon#read 5, iclass 13, count 0 2006.258.01:13:54.81#ibcon#about to read 6, iclass 13, count 0 2006.258.01:13:54.81#ibcon#read 6, iclass 13, count 0 2006.258.01:13:54.81#ibcon#end of sib2, iclass 13, count 0 2006.258.01:13:54.81#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:13:54.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:13:54.81#ibcon#[25=USB\r\n] 2006.258.01:13:54.81#ibcon#*before write, iclass 13, count 0 2006.258.01:13:54.81#ibcon#enter sib2, iclass 13, count 0 2006.258.01:13:54.81#ibcon#flushed, iclass 13, count 0 2006.258.01:13:54.81#ibcon#about to write, iclass 13, count 0 2006.258.01:13:54.81#ibcon#wrote, iclass 13, count 0 2006.258.01:13:54.81#ibcon#about to read 3, iclass 13, count 0 2006.258.01:13:54.84#ibcon#read 3, iclass 13, count 0 2006.258.01:13:54.84#ibcon#about to read 4, iclass 13, count 0 2006.258.01:13:54.84#ibcon#read 4, iclass 13, count 0 2006.258.01:13:54.84#ibcon#about to read 5, iclass 13, count 0 2006.258.01:13:54.84#ibcon#read 5, iclass 13, count 0 2006.258.01:13:54.84#ibcon#about to read 6, iclass 13, count 0 2006.258.01:13:54.84#ibcon#read 6, iclass 13, count 0 2006.258.01:13:54.84#ibcon#end of sib2, iclass 13, count 0 2006.258.01:13:54.84#ibcon#*after write, iclass 13, count 0 2006.258.01:13:54.84#ibcon#*before return 0, iclass 13, count 0 2006.258.01:13:54.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:54.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:54.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:13:54.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:13:54.84$vck44/valo=3,564.99 2006.258.01:13:54.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.01:13:54.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.01:13:54.84#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:54.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:54.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:54.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:54.84#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:13:54.84#ibcon#first serial, iclass 15, count 0 2006.258.01:13:54.84#ibcon#enter sib2, iclass 15, count 0 2006.258.01:13:54.84#ibcon#flushed, iclass 15, count 0 2006.258.01:13:54.84#ibcon#about to write, iclass 15, count 0 2006.258.01:13:54.84#ibcon#wrote, iclass 15, count 0 2006.258.01:13:54.84#ibcon#about to read 3, iclass 15, count 0 2006.258.01:13:54.86#ibcon#read 3, iclass 15, count 0 2006.258.01:13:54.86#ibcon#about to read 4, iclass 15, count 0 2006.258.01:13:54.86#ibcon#read 4, iclass 15, count 0 2006.258.01:13:54.86#ibcon#about to read 5, iclass 15, count 0 2006.258.01:13:54.86#ibcon#read 5, iclass 15, count 0 2006.258.01:13:54.86#ibcon#about to read 6, iclass 15, count 0 2006.258.01:13:54.86#ibcon#read 6, iclass 15, count 0 2006.258.01:13:54.86#ibcon#end of sib2, iclass 15, count 0 2006.258.01:13:54.86#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:13:54.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:13:54.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.01:13:54.86#ibcon#*before write, iclass 15, count 0 2006.258.01:13:54.86#ibcon#enter sib2, iclass 15, count 0 2006.258.01:13:54.86#ibcon#flushed, iclass 15, count 0 2006.258.01:13:54.86#ibcon#about to write, iclass 15, count 0 2006.258.01:13:54.86#ibcon#wrote, iclass 15, count 0 2006.258.01:13:54.86#ibcon#about to read 3, iclass 15, count 0 2006.258.01:13:54.90#ibcon#read 3, iclass 15, count 0 2006.258.01:13:54.90#ibcon#about to read 4, iclass 15, count 0 2006.258.01:13:54.90#ibcon#read 4, iclass 15, count 0 2006.258.01:13:54.90#ibcon#about to read 5, iclass 15, count 0 2006.258.01:13:54.90#ibcon#read 5, iclass 15, count 0 2006.258.01:13:54.90#ibcon#about to read 6, iclass 15, count 0 2006.258.01:13:54.90#ibcon#read 6, iclass 15, count 0 2006.258.01:13:54.90#ibcon#end of sib2, iclass 15, count 0 2006.258.01:13:54.90#ibcon#*after write, iclass 15, count 0 2006.258.01:13:54.90#ibcon#*before return 0, iclass 15, count 0 2006.258.01:13:54.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:54.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:54.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:13:54.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:13:54.90$vck44/va=3,8 2006.258.01:13:54.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.01:13:54.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.01:13:54.90#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:54.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:54.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:54.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:54.96#ibcon#enter wrdev, iclass 17, count 2 2006.258.01:13:54.96#ibcon#first serial, iclass 17, count 2 2006.258.01:13:54.96#ibcon#enter sib2, iclass 17, count 2 2006.258.01:13:54.96#ibcon#flushed, iclass 17, count 2 2006.258.01:13:54.96#ibcon#about to write, iclass 17, count 2 2006.258.01:13:54.96#ibcon#wrote, iclass 17, count 2 2006.258.01:13:54.96#ibcon#about to read 3, iclass 17, count 2 2006.258.01:13:54.98#ibcon#read 3, iclass 17, count 2 2006.258.01:13:54.98#ibcon#about to read 4, iclass 17, count 2 2006.258.01:13:54.98#ibcon#read 4, iclass 17, count 2 2006.258.01:13:54.98#ibcon#about to read 5, iclass 17, count 2 2006.258.01:13:54.98#ibcon#read 5, iclass 17, count 2 2006.258.01:13:54.98#ibcon#about to read 6, iclass 17, count 2 2006.258.01:13:54.98#ibcon#read 6, iclass 17, count 2 2006.258.01:13:54.98#ibcon#end of sib2, iclass 17, count 2 2006.258.01:13:54.98#ibcon#*mode == 0, iclass 17, count 2 2006.258.01:13:54.98#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.01:13:54.98#ibcon#[25=AT03-08\r\n] 2006.258.01:13:54.98#ibcon#*before write, iclass 17, count 2 2006.258.01:13:54.98#ibcon#enter sib2, iclass 17, count 2 2006.258.01:13:54.98#ibcon#flushed, iclass 17, count 2 2006.258.01:13:54.98#ibcon#about to write, iclass 17, count 2 2006.258.01:13:54.98#ibcon#wrote, iclass 17, count 2 2006.258.01:13:54.98#ibcon#about to read 3, iclass 17, count 2 2006.258.01:13:55.01#ibcon#read 3, iclass 17, count 2 2006.258.01:13:55.01#ibcon#about to read 4, iclass 17, count 2 2006.258.01:13:55.01#ibcon#read 4, iclass 17, count 2 2006.258.01:13:55.01#ibcon#about to read 5, iclass 17, count 2 2006.258.01:13:55.01#ibcon#read 5, iclass 17, count 2 2006.258.01:13:55.01#ibcon#about to read 6, iclass 17, count 2 2006.258.01:13:55.01#ibcon#read 6, iclass 17, count 2 2006.258.01:13:55.01#ibcon#end of sib2, iclass 17, count 2 2006.258.01:13:55.01#ibcon#*after write, iclass 17, count 2 2006.258.01:13:55.01#ibcon#*before return 0, iclass 17, count 2 2006.258.01:13:55.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:55.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:55.01#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.01:13:55.01#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:55.01#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:55.13#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:55.13#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:55.13#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:13:55.13#ibcon#first serial, iclass 17, count 0 2006.258.01:13:55.13#ibcon#enter sib2, iclass 17, count 0 2006.258.01:13:55.13#ibcon#flushed, iclass 17, count 0 2006.258.01:13:55.13#ibcon#about to write, iclass 17, count 0 2006.258.01:13:55.13#ibcon#wrote, iclass 17, count 0 2006.258.01:13:55.13#ibcon#about to read 3, iclass 17, count 0 2006.258.01:13:55.15#ibcon#read 3, iclass 17, count 0 2006.258.01:13:55.15#ibcon#about to read 4, iclass 17, count 0 2006.258.01:13:55.15#ibcon#read 4, iclass 17, count 0 2006.258.01:13:55.15#ibcon#about to read 5, iclass 17, count 0 2006.258.01:13:55.15#ibcon#read 5, iclass 17, count 0 2006.258.01:13:55.15#ibcon#about to read 6, iclass 17, count 0 2006.258.01:13:55.15#ibcon#read 6, iclass 17, count 0 2006.258.01:13:55.15#ibcon#end of sib2, iclass 17, count 0 2006.258.01:13:55.15#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:13:55.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:13:55.15#ibcon#[25=USB\r\n] 2006.258.01:13:55.15#ibcon#*before write, iclass 17, count 0 2006.258.01:13:55.15#ibcon#enter sib2, iclass 17, count 0 2006.258.01:13:55.15#ibcon#flushed, iclass 17, count 0 2006.258.01:13:55.15#ibcon#about to write, iclass 17, count 0 2006.258.01:13:55.15#ibcon#wrote, iclass 17, count 0 2006.258.01:13:55.15#ibcon#about to read 3, iclass 17, count 0 2006.258.01:13:55.18#ibcon#read 3, iclass 17, count 0 2006.258.01:13:55.18#ibcon#about to read 4, iclass 17, count 0 2006.258.01:13:55.18#ibcon#read 4, iclass 17, count 0 2006.258.01:13:55.18#ibcon#about to read 5, iclass 17, count 0 2006.258.01:13:55.18#ibcon#read 5, iclass 17, count 0 2006.258.01:13:55.18#ibcon#about to read 6, iclass 17, count 0 2006.258.01:13:55.18#ibcon#read 6, iclass 17, count 0 2006.258.01:13:55.18#ibcon#end of sib2, iclass 17, count 0 2006.258.01:13:55.18#ibcon#*after write, iclass 17, count 0 2006.258.01:13:55.18#ibcon#*before return 0, iclass 17, count 0 2006.258.01:13:55.18#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:55.18#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:55.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:13:55.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:13:55.18$vck44/valo=4,624.99 2006.258.01:13:55.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.01:13:55.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.01:13:55.18#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:55.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:55.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:55.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:55.18#ibcon#enter wrdev, iclass 19, count 0 2006.258.01:13:55.18#ibcon#first serial, iclass 19, count 0 2006.258.01:13:55.18#ibcon#enter sib2, iclass 19, count 0 2006.258.01:13:55.18#ibcon#flushed, iclass 19, count 0 2006.258.01:13:55.18#ibcon#about to write, iclass 19, count 0 2006.258.01:13:55.18#ibcon#wrote, iclass 19, count 0 2006.258.01:13:55.18#ibcon#about to read 3, iclass 19, count 0 2006.258.01:13:55.20#ibcon#read 3, iclass 19, count 0 2006.258.01:13:55.20#ibcon#about to read 4, iclass 19, count 0 2006.258.01:13:55.20#ibcon#read 4, iclass 19, count 0 2006.258.01:13:55.20#ibcon#about to read 5, iclass 19, count 0 2006.258.01:13:55.20#ibcon#read 5, iclass 19, count 0 2006.258.01:13:55.20#ibcon#about to read 6, iclass 19, count 0 2006.258.01:13:55.20#ibcon#read 6, iclass 19, count 0 2006.258.01:13:55.20#ibcon#end of sib2, iclass 19, count 0 2006.258.01:13:55.20#ibcon#*mode == 0, iclass 19, count 0 2006.258.01:13:55.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.01:13:55.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.01:13:55.20#ibcon#*before write, iclass 19, count 0 2006.258.01:13:55.20#ibcon#enter sib2, iclass 19, count 0 2006.258.01:13:55.20#ibcon#flushed, iclass 19, count 0 2006.258.01:13:55.20#ibcon#about to write, iclass 19, count 0 2006.258.01:13:55.20#ibcon#wrote, iclass 19, count 0 2006.258.01:13:55.20#ibcon#about to read 3, iclass 19, count 0 2006.258.01:13:55.24#ibcon#read 3, iclass 19, count 0 2006.258.01:13:55.24#ibcon#about to read 4, iclass 19, count 0 2006.258.01:13:55.24#ibcon#read 4, iclass 19, count 0 2006.258.01:13:55.24#ibcon#about to read 5, iclass 19, count 0 2006.258.01:13:55.24#ibcon#read 5, iclass 19, count 0 2006.258.01:13:55.24#ibcon#about to read 6, iclass 19, count 0 2006.258.01:13:55.24#ibcon#read 6, iclass 19, count 0 2006.258.01:13:55.24#ibcon#end of sib2, iclass 19, count 0 2006.258.01:13:55.24#ibcon#*after write, iclass 19, count 0 2006.258.01:13:55.24#ibcon#*before return 0, iclass 19, count 0 2006.258.01:13:55.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:55.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:55.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.01:13:55.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.01:13:55.24$vck44/va=4,7 2006.258.01:13:55.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.01:13:55.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.01:13:55.24#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:55.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:55.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:55.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:55.30#ibcon#enter wrdev, iclass 21, count 2 2006.258.01:13:55.30#ibcon#first serial, iclass 21, count 2 2006.258.01:13:55.30#ibcon#enter sib2, iclass 21, count 2 2006.258.01:13:55.30#ibcon#flushed, iclass 21, count 2 2006.258.01:13:55.30#ibcon#about to write, iclass 21, count 2 2006.258.01:13:55.30#ibcon#wrote, iclass 21, count 2 2006.258.01:13:55.30#ibcon#about to read 3, iclass 21, count 2 2006.258.01:13:55.32#ibcon#read 3, iclass 21, count 2 2006.258.01:13:55.32#ibcon#about to read 4, iclass 21, count 2 2006.258.01:13:55.32#ibcon#read 4, iclass 21, count 2 2006.258.01:13:55.32#ibcon#about to read 5, iclass 21, count 2 2006.258.01:13:55.32#ibcon#read 5, iclass 21, count 2 2006.258.01:13:55.32#ibcon#about to read 6, iclass 21, count 2 2006.258.01:13:55.32#ibcon#read 6, iclass 21, count 2 2006.258.01:13:55.32#ibcon#end of sib2, iclass 21, count 2 2006.258.01:13:55.32#ibcon#*mode == 0, iclass 21, count 2 2006.258.01:13:55.32#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.01:13:55.32#ibcon#[25=AT04-07\r\n] 2006.258.01:13:55.32#ibcon#*before write, iclass 21, count 2 2006.258.01:13:55.32#ibcon#enter sib2, iclass 21, count 2 2006.258.01:13:55.32#ibcon#flushed, iclass 21, count 2 2006.258.01:13:55.32#ibcon#about to write, iclass 21, count 2 2006.258.01:13:55.32#ibcon#wrote, iclass 21, count 2 2006.258.01:13:55.32#ibcon#about to read 3, iclass 21, count 2 2006.258.01:13:55.35#ibcon#read 3, iclass 21, count 2 2006.258.01:13:55.35#ibcon#about to read 4, iclass 21, count 2 2006.258.01:13:55.35#ibcon#read 4, iclass 21, count 2 2006.258.01:13:55.35#ibcon#about to read 5, iclass 21, count 2 2006.258.01:13:55.35#ibcon#read 5, iclass 21, count 2 2006.258.01:13:55.35#ibcon#about to read 6, iclass 21, count 2 2006.258.01:13:55.35#ibcon#read 6, iclass 21, count 2 2006.258.01:13:55.35#ibcon#end of sib2, iclass 21, count 2 2006.258.01:13:55.35#ibcon#*after write, iclass 21, count 2 2006.258.01:13:55.35#ibcon#*before return 0, iclass 21, count 2 2006.258.01:13:55.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:55.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:55.35#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.01:13:55.35#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:55.35#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:55.47#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:55.47#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:55.47#ibcon#enter wrdev, iclass 21, count 0 2006.258.01:13:55.47#ibcon#first serial, iclass 21, count 0 2006.258.01:13:55.47#ibcon#enter sib2, iclass 21, count 0 2006.258.01:13:55.47#ibcon#flushed, iclass 21, count 0 2006.258.01:13:55.47#ibcon#about to write, iclass 21, count 0 2006.258.01:13:55.47#ibcon#wrote, iclass 21, count 0 2006.258.01:13:55.47#ibcon#about to read 3, iclass 21, count 0 2006.258.01:13:55.49#ibcon#read 3, iclass 21, count 0 2006.258.01:13:55.49#ibcon#about to read 4, iclass 21, count 0 2006.258.01:13:55.49#ibcon#read 4, iclass 21, count 0 2006.258.01:13:55.49#ibcon#about to read 5, iclass 21, count 0 2006.258.01:13:55.49#ibcon#read 5, iclass 21, count 0 2006.258.01:13:55.49#ibcon#about to read 6, iclass 21, count 0 2006.258.01:13:55.49#ibcon#read 6, iclass 21, count 0 2006.258.01:13:55.49#ibcon#end of sib2, iclass 21, count 0 2006.258.01:13:55.49#ibcon#*mode == 0, iclass 21, count 0 2006.258.01:13:55.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.01:13:55.49#ibcon#[25=USB\r\n] 2006.258.01:13:55.49#ibcon#*before write, iclass 21, count 0 2006.258.01:13:55.49#ibcon#enter sib2, iclass 21, count 0 2006.258.01:13:55.49#ibcon#flushed, iclass 21, count 0 2006.258.01:13:55.49#ibcon#about to write, iclass 21, count 0 2006.258.01:13:55.49#ibcon#wrote, iclass 21, count 0 2006.258.01:13:55.49#ibcon#about to read 3, iclass 21, count 0 2006.258.01:13:55.52#ibcon#read 3, iclass 21, count 0 2006.258.01:13:55.52#ibcon#about to read 4, iclass 21, count 0 2006.258.01:13:55.52#ibcon#read 4, iclass 21, count 0 2006.258.01:13:55.52#ibcon#about to read 5, iclass 21, count 0 2006.258.01:13:55.52#ibcon#read 5, iclass 21, count 0 2006.258.01:13:55.52#ibcon#about to read 6, iclass 21, count 0 2006.258.01:13:55.52#ibcon#read 6, iclass 21, count 0 2006.258.01:13:55.52#ibcon#end of sib2, iclass 21, count 0 2006.258.01:13:55.52#ibcon#*after write, iclass 21, count 0 2006.258.01:13:55.52#ibcon#*before return 0, iclass 21, count 0 2006.258.01:13:55.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:55.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:55.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.01:13:55.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.01:13:55.52$vck44/valo=5,734.99 2006.258.01:13:55.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.01:13:55.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.01:13:55.52#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:55.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:55.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:55.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:55.52#ibcon#enter wrdev, iclass 23, count 0 2006.258.01:13:55.52#ibcon#first serial, iclass 23, count 0 2006.258.01:13:55.52#ibcon#enter sib2, iclass 23, count 0 2006.258.01:13:55.52#ibcon#flushed, iclass 23, count 0 2006.258.01:13:55.52#ibcon#about to write, iclass 23, count 0 2006.258.01:13:55.52#ibcon#wrote, iclass 23, count 0 2006.258.01:13:55.52#ibcon#about to read 3, iclass 23, count 0 2006.258.01:13:55.54#ibcon#read 3, iclass 23, count 0 2006.258.01:13:55.54#ibcon#about to read 4, iclass 23, count 0 2006.258.01:13:55.54#ibcon#read 4, iclass 23, count 0 2006.258.01:13:55.54#ibcon#about to read 5, iclass 23, count 0 2006.258.01:13:55.54#ibcon#read 5, iclass 23, count 0 2006.258.01:13:55.54#ibcon#about to read 6, iclass 23, count 0 2006.258.01:13:55.54#ibcon#read 6, iclass 23, count 0 2006.258.01:13:55.54#ibcon#end of sib2, iclass 23, count 0 2006.258.01:13:55.54#ibcon#*mode == 0, iclass 23, count 0 2006.258.01:13:55.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.01:13:55.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.01:13:55.54#ibcon#*before write, iclass 23, count 0 2006.258.01:13:55.54#ibcon#enter sib2, iclass 23, count 0 2006.258.01:13:55.54#ibcon#flushed, iclass 23, count 0 2006.258.01:13:55.54#ibcon#about to write, iclass 23, count 0 2006.258.01:13:55.54#ibcon#wrote, iclass 23, count 0 2006.258.01:13:55.54#ibcon#about to read 3, iclass 23, count 0 2006.258.01:13:55.58#ibcon#read 3, iclass 23, count 0 2006.258.01:13:55.58#ibcon#about to read 4, iclass 23, count 0 2006.258.01:13:55.58#ibcon#read 4, iclass 23, count 0 2006.258.01:13:55.58#ibcon#about to read 5, iclass 23, count 0 2006.258.01:13:55.58#ibcon#read 5, iclass 23, count 0 2006.258.01:13:55.58#ibcon#about to read 6, iclass 23, count 0 2006.258.01:13:55.58#ibcon#read 6, iclass 23, count 0 2006.258.01:13:55.58#ibcon#end of sib2, iclass 23, count 0 2006.258.01:13:55.58#ibcon#*after write, iclass 23, count 0 2006.258.01:13:55.58#ibcon#*before return 0, iclass 23, count 0 2006.258.01:13:55.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:55.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:55.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.01:13:55.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.01:13:55.58$vck44/va=5,4 2006.258.01:13:55.58#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.258.01:13:55.58#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.258.01:13:55.58#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:55.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:55.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:55.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:55.64#ibcon#enter wrdev, iclass 25, count 2 2006.258.01:13:55.64#ibcon#first serial, iclass 25, count 2 2006.258.01:13:55.64#ibcon#enter sib2, iclass 25, count 2 2006.258.01:13:55.64#ibcon#flushed, iclass 25, count 2 2006.258.01:13:55.64#ibcon#about to write, iclass 25, count 2 2006.258.01:13:55.64#ibcon#wrote, iclass 25, count 2 2006.258.01:13:55.64#ibcon#about to read 3, iclass 25, count 2 2006.258.01:13:55.66#ibcon#read 3, iclass 25, count 2 2006.258.01:13:55.66#ibcon#about to read 4, iclass 25, count 2 2006.258.01:13:55.66#ibcon#read 4, iclass 25, count 2 2006.258.01:13:55.66#ibcon#about to read 5, iclass 25, count 2 2006.258.01:13:55.66#ibcon#read 5, iclass 25, count 2 2006.258.01:13:55.66#ibcon#about to read 6, iclass 25, count 2 2006.258.01:13:55.66#ibcon#read 6, iclass 25, count 2 2006.258.01:13:55.66#ibcon#end of sib2, iclass 25, count 2 2006.258.01:13:55.66#ibcon#*mode == 0, iclass 25, count 2 2006.258.01:13:55.66#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.258.01:13:55.66#ibcon#[25=AT05-04\r\n] 2006.258.01:13:55.66#ibcon#*before write, iclass 25, count 2 2006.258.01:13:55.66#ibcon#enter sib2, iclass 25, count 2 2006.258.01:13:55.66#ibcon#flushed, iclass 25, count 2 2006.258.01:13:55.66#ibcon#about to write, iclass 25, count 2 2006.258.01:13:55.66#ibcon#wrote, iclass 25, count 2 2006.258.01:13:55.66#ibcon#about to read 3, iclass 25, count 2 2006.258.01:13:55.69#ibcon#read 3, iclass 25, count 2 2006.258.01:13:55.69#ibcon#about to read 4, iclass 25, count 2 2006.258.01:13:55.69#ibcon#read 4, iclass 25, count 2 2006.258.01:13:55.69#ibcon#about to read 5, iclass 25, count 2 2006.258.01:13:55.69#ibcon#read 5, iclass 25, count 2 2006.258.01:13:55.69#ibcon#about to read 6, iclass 25, count 2 2006.258.01:13:55.69#ibcon#read 6, iclass 25, count 2 2006.258.01:13:55.69#ibcon#end of sib2, iclass 25, count 2 2006.258.01:13:55.69#ibcon#*after write, iclass 25, count 2 2006.258.01:13:55.69#ibcon#*before return 0, iclass 25, count 2 2006.258.01:13:55.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:55.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:55.69#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.258.01:13:55.69#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:55.69#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:55.81#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:55.81#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:55.81#ibcon#enter wrdev, iclass 25, count 0 2006.258.01:13:55.81#ibcon#first serial, iclass 25, count 0 2006.258.01:13:55.81#ibcon#enter sib2, iclass 25, count 0 2006.258.01:13:55.81#ibcon#flushed, iclass 25, count 0 2006.258.01:13:55.81#ibcon#about to write, iclass 25, count 0 2006.258.01:13:55.81#ibcon#wrote, iclass 25, count 0 2006.258.01:13:55.81#ibcon#about to read 3, iclass 25, count 0 2006.258.01:13:55.83#ibcon#read 3, iclass 25, count 0 2006.258.01:13:55.83#ibcon#about to read 4, iclass 25, count 0 2006.258.01:13:55.83#ibcon#read 4, iclass 25, count 0 2006.258.01:13:55.83#ibcon#about to read 5, iclass 25, count 0 2006.258.01:13:55.83#ibcon#read 5, iclass 25, count 0 2006.258.01:13:55.83#ibcon#about to read 6, iclass 25, count 0 2006.258.01:13:55.83#ibcon#read 6, iclass 25, count 0 2006.258.01:13:55.83#ibcon#end of sib2, iclass 25, count 0 2006.258.01:13:55.83#ibcon#*mode == 0, iclass 25, count 0 2006.258.01:13:55.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.01:13:55.83#ibcon#[25=USB\r\n] 2006.258.01:13:55.83#ibcon#*before write, iclass 25, count 0 2006.258.01:13:55.83#ibcon#enter sib2, iclass 25, count 0 2006.258.01:13:55.83#ibcon#flushed, iclass 25, count 0 2006.258.01:13:55.83#ibcon#about to write, iclass 25, count 0 2006.258.01:13:55.83#ibcon#wrote, iclass 25, count 0 2006.258.01:13:55.83#ibcon#about to read 3, iclass 25, count 0 2006.258.01:13:55.86#ibcon#read 3, iclass 25, count 0 2006.258.01:13:55.86#ibcon#about to read 4, iclass 25, count 0 2006.258.01:13:55.86#ibcon#read 4, iclass 25, count 0 2006.258.01:13:55.86#ibcon#about to read 5, iclass 25, count 0 2006.258.01:13:55.86#ibcon#read 5, iclass 25, count 0 2006.258.01:13:55.86#ibcon#about to read 6, iclass 25, count 0 2006.258.01:13:55.86#ibcon#read 6, iclass 25, count 0 2006.258.01:13:55.86#ibcon#end of sib2, iclass 25, count 0 2006.258.01:13:55.86#ibcon#*after write, iclass 25, count 0 2006.258.01:13:55.86#ibcon#*before return 0, iclass 25, count 0 2006.258.01:13:55.86#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:55.86#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:55.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.01:13:55.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.01:13:55.86$vck44/valo=6,814.99 2006.258.01:13:55.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.01:13:55.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.01:13:55.86#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:55.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:55.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:55.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:55.86#ibcon#enter wrdev, iclass 27, count 0 2006.258.01:13:55.86#ibcon#first serial, iclass 27, count 0 2006.258.01:13:55.86#ibcon#enter sib2, iclass 27, count 0 2006.258.01:13:55.86#ibcon#flushed, iclass 27, count 0 2006.258.01:13:55.86#ibcon#about to write, iclass 27, count 0 2006.258.01:13:55.86#ibcon#wrote, iclass 27, count 0 2006.258.01:13:55.86#ibcon#about to read 3, iclass 27, count 0 2006.258.01:13:55.88#ibcon#read 3, iclass 27, count 0 2006.258.01:13:55.88#ibcon#about to read 4, iclass 27, count 0 2006.258.01:13:55.88#ibcon#read 4, iclass 27, count 0 2006.258.01:13:55.88#ibcon#about to read 5, iclass 27, count 0 2006.258.01:13:55.88#ibcon#read 5, iclass 27, count 0 2006.258.01:13:55.88#ibcon#about to read 6, iclass 27, count 0 2006.258.01:13:55.88#ibcon#read 6, iclass 27, count 0 2006.258.01:13:55.88#ibcon#end of sib2, iclass 27, count 0 2006.258.01:13:55.88#ibcon#*mode == 0, iclass 27, count 0 2006.258.01:13:55.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.01:13:55.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.01:13:55.88#ibcon#*before write, iclass 27, count 0 2006.258.01:13:55.88#ibcon#enter sib2, iclass 27, count 0 2006.258.01:13:55.88#ibcon#flushed, iclass 27, count 0 2006.258.01:13:55.88#ibcon#about to write, iclass 27, count 0 2006.258.01:13:55.88#ibcon#wrote, iclass 27, count 0 2006.258.01:13:55.88#ibcon#about to read 3, iclass 27, count 0 2006.258.01:13:55.92#ibcon#read 3, iclass 27, count 0 2006.258.01:13:55.92#ibcon#about to read 4, iclass 27, count 0 2006.258.01:13:55.92#ibcon#read 4, iclass 27, count 0 2006.258.01:13:55.92#ibcon#about to read 5, iclass 27, count 0 2006.258.01:13:55.92#ibcon#read 5, iclass 27, count 0 2006.258.01:13:55.92#ibcon#about to read 6, iclass 27, count 0 2006.258.01:13:55.92#ibcon#read 6, iclass 27, count 0 2006.258.01:13:55.92#ibcon#end of sib2, iclass 27, count 0 2006.258.01:13:55.92#ibcon#*after write, iclass 27, count 0 2006.258.01:13:55.92#ibcon#*before return 0, iclass 27, count 0 2006.258.01:13:55.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:55.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:55.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.01:13:55.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.01:13:55.92$vck44/va=6,4 2006.258.01:13:55.92#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.01:13:55.92#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.01:13:55.92#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:55.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:55.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:55.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:55.98#ibcon#enter wrdev, iclass 29, count 2 2006.258.01:13:55.98#ibcon#first serial, iclass 29, count 2 2006.258.01:13:55.98#ibcon#enter sib2, iclass 29, count 2 2006.258.01:13:55.98#ibcon#flushed, iclass 29, count 2 2006.258.01:13:55.98#ibcon#about to write, iclass 29, count 2 2006.258.01:13:55.98#ibcon#wrote, iclass 29, count 2 2006.258.01:13:55.98#ibcon#about to read 3, iclass 29, count 2 2006.258.01:13:56.00#ibcon#read 3, iclass 29, count 2 2006.258.01:13:56.00#ibcon#about to read 4, iclass 29, count 2 2006.258.01:13:56.00#ibcon#read 4, iclass 29, count 2 2006.258.01:13:56.00#ibcon#about to read 5, iclass 29, count 2 2006.258.01:13:56.00#ibcon#read 5, iclass 29, count 2 2006.258.01:13:56.00#ibcon#about to read 6, iclass 29, count 2 2006.258.01:13:56.00#ibcon#read 6, iclass 29, count 2 2006.258.01:13:56.00#ibcon#end of sib2, iclass 29, count 2 2006.258.01:13:56.00#ibcon#*mode == 0, iclass 29, count 2 2006.258.01:13:56.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.01:13:56.00#ibcon#[25=AT06-04\r\n] 2006.258.01:13:56.00#ibcon#*before write, iclass 29, count 2 2006.258.01:13:56.00#ibcon#enter sib2, iclass 29, count 2 2006.258.01:13:56.00#ibcon#flushed, iclass 29, count 2 2006.258.01:13:56.00#ibcon#about to write, iclass 29, count 2 2006.258.01:13:56.00#ibcon#wrote, iclass 29, count 2 2006.258.01:13:56.00#ibcon#about to read 3, iclass 29, count 2 2006.258.01:13:56.03#ibcon#read 3, iclass 29, count 2 2006.258.01:13:56.03#ibcon#about to read 4, iclass 29, count 2 2006.258.01:13:56.03#ibcon#read 4, iclass 29, count 2 2006.258.01:13:56.03#ibcon#about to read 5, iclass 29, count 2 2006.258.01:13:56.03#ibcon#read 5, iclass 29, count 2 2006.258.01:13:56.03#ibcon#about to read 6, iclass 29, count 2 2006.258.01:13:56.03#ibcon#read 6, iclass 29, count 2 2006.258.01:13:56.03#ibcon#end of sib2, iclass 29, count 2 2006.258.01:13:56.03#ibcon#*after write, iclass 29, count 2 2006.258.01:13:56.03#ibcon#*before return 0, iclass 29, count 2 2006.258.01:13:56.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:56.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:56.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.01:13:56.03#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:56.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:56.14#abcon#<5=/03 2.8 5.3 22.69 761016.0\r\n> 2006.258.01:13:56.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:56.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:56.15#ibcon#enter wrdev, iclass 29, count 0 2006.258.01:13:56.15#ibcon#first serial, iclass 29, count 0 2006.258.01:13:56.15#ibcon#enter sib2, iclass 29, count 0 2006.258.01:13:56.15#ibcon#flushed, iclass 29, count 0 2006.258.01:13:56.15#ibcon#about to write, iclass 29, count 0 2006.258.01:13:56.15#ibcon#wrote, iclass 29, count 0 2006.258.01:13:56.15#ibcon#about to read 3, iclass 29, count 0 2006.258.01:13:56.16#abcon#{5=INTERFACE CLEAR} 2006.258.01:13:56.17#ibcon#read 3, iclass 29, count 0 2006.258.01:13:56.17#ibcon#about to read 4, iclass 29, count 0 2006.258.01:13:56.17#ibcon#read 4, iclass 29, count 0 2006.258.01:13:56.17#ibcon#about to read 5, iclass 29, count 0 2006.258.01:13:56.17#ibcon#read 5, iclass 29, count 0 2006.258.01:13:56.17#ibcon#about to read 6, iclass 29, count 0 2006.258.01:13:56.17#ibcon#read 6, iclass 29, count 0 2006.258.01:13:56.17#ibcon#end of sib2, iclass 29, count 0 2006.258.01:13:56.17#ibcon#*mode == 0, iclass 29, count 0 2006.258.01:13:56.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.01:13:56.17#ibcon#[25=USB\r\n] 2006.258.01:13:56.17#ibcon#*before write, iclass 29, count 0 2006.258.01:13:56.17#ibcon#enter sib2, iclass 29, count 0 2006.258.01:13:56.17#ibcon#flushed, iclass 29, count 0 2006.258.01:13:56.17#ibcon#about to write, iclass 29, count 0 2006.258.01:13:56.17#ibcon#wrote, iclass 29, count 0 2006.258.01:13:56.17#ibcon#about to read 3, iclass 29, count 0 2006.258.01:13:56.20#ibcon#read 3, iclass 29, count 0 2006.258.01:13:56.20#ibcon#about to read 4, iclass 29, count 0 2006.258.01:13:56.20#ibcon#read 4, iclass 29, count 0 2006.258.01:13:56.20#ibcon#about to read 5, iclass 29, count 0 2006.258.01:13:56.20#ibcon#read 5, iclass 29, count 0 2006.258.01:13:56.20#ibcon#about to read 6, iclass 29, count 0 2006.258.01:13:56.20#ibcon#read 6, iclass 29, count 0 2006.258.01:13:56.20#ibcon#end of sib2, iclass 29, count 0 2006.258.01:13:56.20#ibcon#*after write, iclass 29, count 0 2006.258.01:13:56.20#ibcon#*before return 0, iclass 29, count 0 2006.258.01:13:56.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:56.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:56.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.01:13:56.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.01:13:56.20$vck44/valo=7,864.99 2006.258.01:13:56.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.01:13:56.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.01:13:56.20#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:56.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:13:56.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:13:56.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:13:56.20#ibcon#enter wrdev, iclass 34, count 0 2006.258.01:13:56.20#ibcon#first serial, iclass 34, count 0 2006.258.01:13:56.20#ibcon#enter sib2, iclass 34, count 0 2006.258.01:13:56.20#ibcon#flushed, iclass 34, count 0 2006.258.01:13:56.20#ibcon#about to write, iclass 34, count 0 2006.258.01:13:56.20#ibcon#wrote, iclass 34, count 0 2006.258.01:13:56.20#ibcon#about to read 3, iclass 34, count 0 2006.258.01:13:56.22#ibcon#read 3, iclass 34, count 0 2006.258.01:13:56.22#ibcon#about to read 4, iclass 34, count 0 2006.258.01:13:56.22#ibcon#read 4, iclass 34, count 0 2006.258.01:13:56.22#ibcon#about to read 5, iclass 34, count 0 2006.258.01:13:56.22#ibcon#read 5, iclass 34, count 0 2006.258.01:13:56.22#ibcon#about to read 6, iclass 34, count 0 2006.258.01:13:56.22#ibcon#read 6, iclass 34, count 0 2006.258.01:13:56.22#ibcon#end of sib2, iclass 34, count 0 2006.258.01:13:56.22#ibcon#*mode == 0, iclass 34, count 0 2006.258.01:13:56.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.01:13:56.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.01:13:56.22#ibcon#*before write, iclass 34, count 0 2006.258.01:13:56.22#ibcon#enter sib2, iclass 34, count 0 2006.258.01:13:56.22#ibcon#flushed, iclass 34, count 0 2006.258.01:13:56.22#ibcon#about to write, iclass 34, count 0 2006.258.01:13:56.22#ibcon#wrote, iclass 34, count 0 2006.258.01:13:56.22#ibcon#about to read 3, iclass 34, count 0 2006.258.01:13:56.22#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:13:56.26#ibcon#read 3, iclass 34, count 0 2006.258.01:13:56.26#ibcon#about to read 4, iclass 34, count 0 2006.258.01:13:56.26#ibcon#read 4, iclass 34, count 0 2006.258.01:13:56.26#ibcon#about to read 5, iclass 34, count 0 2006.258.01:13:56.26#ibcon#read 5, iclass 34, count 0 2006.258.01:13:56.26#ibcon#about to read 6, iclass 34, count 0 2006.258.01:13:56.26#ibcon#read 6, iclass 34, count 0 2006.258.01:13:56.26#ibcon#end of sib2, iclass 34, count 0 2006.258.01:13:56.26#ibcon#*after write, iclass 34, count 0 2006.258.01:13:56.26#ibcon#*before return 0, iclass 34, count 0 2006.258.01:13:56.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:13:56.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:13:56.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.01:13:56.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.01:13:56.26$vck44/va=7,4 2006.258.01:13:56.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.01:13:56.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.01:13:56.26#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:56.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:56.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:56.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:56.32#ibcon#enter wrdev, iclass 37, count 2 2006.258.01:13:56.32#ibcon#first serial, iclass 37, count 2 2006.258.01:13:56.32#ibcon#enter sib2, iclass 37, count 2 2006.258.01:13:56.32#ibcon#flushed, iclass 37, count 2 2006.258.01:13:56.32#ibcon#about to write, iclass 37, count 2 2006.258.01:13:56.32#ibcon#wrote, iclass 37, count 2 2006.258.01:13:56.32#ibcon#about to read 3, iclass 37, count 2 2006.258.01:13:56.34#ibcon#read 3, iclass 37, count 2 2006.258.01:13:56.34#ibcon#about to read 4, iclass 37, count 2 2006.258.01:13:56.34#ibcon#read 4, iclass 37, count 2 2006.258.01:13:56.34#ibcon#about to read 5, iclass 37, count 2 2006.258.01:13:56.34#ibcon#read 5, iclass 37, count 2 2006.258.01:13:56.34#ibcon#about to read 6, iclass 37, count 2 2006.258.01:13:56.34#ibcon#read 6, iclass 37, count 2 2006.258.01:13:56.34#ibcon#end of sib2, iclass 37, count 2 2006.258.01:13:56.34#ibcon#*mode == 0, iclass 37, count 2 2006.258.01:13:56.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.01:13:56.34#ibcon#[25=AT07-04\r\n] 2006.258.01:13:56.34#ibcon#*before write, iclass 37, count 2 2006.258.01:13:56.34#ibcon#enter sib2, iclass 37, count 2 2006.258.01:13:56.34#ibcon#flushed, iclass 37, count 2 2006.258.01:13:56.34#ibcon#about to write, iclass 37, count 2 2006.258.01:13:56.34#ibcon#wrote, iclass 37, count 2 2006.258.01:13:56.34#ibcon#about to read 3, iclass 37, count 2 2006.258.01:13:56.37#ibcon#read 3, iclass 37, count 2 2006.258.01:13:56.37#ibcon#about to read 4, iclass 37, count 2 2006.258.01:13:56.37#ibcon#read 4, iclass 37, count 2 2006.258.01:13:56.37#ibcon#about to read 5, iclass 37, count 2 2006.258.01:13:56.37#ibcon#read 5, iclass 37, count 2 2006.258.01:13:56.37#ibcon#about to read 6, iclass 37, count 2 2006.258.01:13:56.37#ibcon#read 6, iclass 37, count 2 2006.258.01:13:56.37#ibcon#end of sib2, iclass 37, count 2 2006.258.01:13:56.37#ibcon#*after write, iclass 37, count 2 2006.258.01:13:56.37#ibcon#*before return 0, iclass 37, count 2 2006.258.01:13:56.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:56.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:56.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.01:13:56.37#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:56.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:56.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:56.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:56.49#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:13:56.49#ibcon#first serial, iclass 37, count 0 2006.258.01:13:56.49#ibcon#enter sib2, iclass 37, count 0 2006.258.01:13:56.49#ibcon#flushed, iclass 37, count 0 2006.258.01:13:56.49#ibcon#about to write, iclass 37, count 0 2006.258.01:13:56.49#ibcon#wrote, iclass 37, count 0 2006.258.01:13:56.49#ibcon#about to read 3, iclass 37, count 0 2006.258.01:13:56.51#ibcon#read 3, iclass 37, count 0 2006.258.01:13:56.51#ibcon#about to read 4, iclass 37, count 0 2006.258.01:13:56.51#ibcon#read 4, iclass 37, count 0 2006.258.01:13:56.51#ibcon#about to read 5, iclass 37, count 0 2006.258.01:13:56.51#ibcon#read 5, iclass 37, count 0 2006.258.01:13:56.51#ibcon#about to read 6, iclass 37, count 0 2006.258.01:13:56.51#ibcon#read 6, iclass 37, count 0 2006.258.01:13:56.51#ibcon#end of sib2, iclass 37, count 0 2006.258.01:13:56.51#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:13:56.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:13:56.51#ibcon#[25=USB\r\n] 2006.258.01:13:56.51#ibcon#*before write, iclass 37, count 0 2006.258.01:13:56.51#ibcon#enter sib2, iclass 37, count 0 2006.258.01:13:56.51#ibcon#flushed, iclass 37, count 0 2006.258.01:13:56.51#ibcon#about to write, iclass 37, count 0 2006.258.01:13:56.51#ibcon#wrote, iclass 37, count 0 2006.258.01:13:56.51#ibcon#about to read 3, iclass 37, count 0 2006.258.01:13:56.54#ibcon#read 3, iclass 37, count 0 2006.258.01:13:56.54#ibcon#about to read 4, iclass 37, count 0 2006.258.01:13:56.54#ibcon#read 4, iclass 37, count 0 2006.258.01:13:56.54#ibcon#about to read 5, iclass 37, count 0 2006.258.01:13:56.54#ibcon#read 5, iclass 37, count 0 2006.258.01:13:56.54#ibcon#about to read 6, iclass 37, count 0 2006.258.01:13:56.54#ibcon#read 6, iclass 37, count 0 2006.258.01:13:56.54#ibcon#end of sib2, iclass 37, count 0 2006.258.01:13:56.54#ibcon#*after write, iclass 37, count 0 2006.258.01:13:56.54#ibcon#*before return 0, iclass 37, count 0 2006.258.01:13:56.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:56.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:56.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:13:56.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:13:56.54$vck44/valo=8,884.99 2006.258.01:13:56.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.01:13:56.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.01:13:56.54#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:56.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:56.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:56.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:56.54#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:13:56.54#ibcon#first serial, iclass 39, count 0 2006.258.01:13:56.54#ibcon#enter sib2, iclass 39, count 0 2006.258.01:13:56.54#ibcon#flushed, iclass 39, count 0 2006.258.01:13:56.54#ibcon#about to write, iclass 39, count 0 2006.258.01:13:56.54#ibcon#wrote, iclass 39, count 0 2006.258.01:13:56.54#ibcon#about to read 3, iclass 39, count 0 2006.258.01:13:56.56#ibcon#read 3, iclass 39, count 0 2006.258.01:13:56.56#ibcon#about to read 4, iclass 39, count 0 2006.258.01:13:56.56#ibcon#read 4, iclass 39, count 0 2006.258.01:13:56.56#ibcon#about to read 5, iclass 39, count 0 2006.258.01:13:56.56#ibcon#read 5, iclass 39, count 0 2006.258.01:13:56.56#ibcon#about to read 6, iclass 39, count 0 2006.258.01:13:56.56#ibcon#read 6, iclass 39, count 0 2006.258.01:13:56.56#ibcon#end of sib2, iclass 39, count 0 2006.258.01:13:56.56#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:13:56.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:13:56.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.01:13:56.56#ibcon#*before write, iclass 39, count 0 2006.258.01:13:56.56#ibcon#enter sib2, iclass 39, count 0 2006.258.01:13:56.56#ibcon#flushed, iclass 39, count 0 2006.258.01:13:56.56#ibcon#about to write, iclass 39, count 0 2006.258.01:13:56.56#ibcon#wrote, iclass 39, count 0 2006.258.01:13:56.56#ibcon#about to read 3, iclass 39, count 0 2006.258.01:13:56.60#ibcon#read 3, iclass 39, count 0 2006.258.01:13:56.60#ibcon#about to read 4, iclass 39, count 0 2006.258.01:13:56.60#ibcon#read 4, iclass 39, count 0 2006.258.01:13:56.60#ibcon#about to read 5, iclass 39, count 0 2006.258.01:13:56.60#ibcon#read 5, iclass 39, count 0 2006.258.01:13:56.60#ibcon#about to read 6, iclass 39, count 0 2006.258.01:13:56.60#ibcon#read 6, iclass 39, count 0 2006.258.01:13:56.60#ibcon#end of sib2, iclass 39, count 0 2006.258.01:13:56.60#ibcon#*after write, iclass 39, count 0 2006.258.01:13:56.60#ibcon#*before return 0, iclass 39, count 0 2006.258.01:13:56.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:56.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:56.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:13:56.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:13:56.60$vck44/va=8,4 2006.258.01:13:56.60#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.01:13:56.60#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.01:13:56.60#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:56.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:13:56.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:13:56.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:13:56.66#ibcon#enter wrdev, iclass 3, count 2 2006.258.01:13:56.66#ibcon#first serial, iclass 3, count 2 2006.258.01:13:56.66#ibcon#enter sib2, iclass 3, count 2 2006.258.01:13:56.66#ibcon#flushed, iclass 3, count 2 2006.258.01:13:56.66#ibcon#about to write, iclass 3, count 2 2006.258.01:13:56.66#ibcon#wrote, iclass 3, count 2 2006.258.01:13:56.66#ibcon#about to read 3, iclass 3, count 2 2006.258.01:13:56.68#ibcon#read 3, iclass 3, count 2 2006.258.01:13:56.68#ibcon#about to read 4, iclass 3, count 2 2006.258.01:13:56.68#ibcon#read 4, iclass 3, count 2 2006.258.01:13:56.68#ibcon#about to read 5, iclass 3, count 2 2006.258.01:13:56.68#ibcon#read 5, iclass 3, count 2 2006.258.01:13:56.68#ibcon#about to read 6, iclass 3, count 2 2006.258.01:13:56.68#ibcon#read 6, iclass 3, count 2 2006.258.01:13:56.68#ibcon#end of sib2, iclass 3, count 2 2006.258.01:13:56.68#ibcon#*mode == 0, iclass 3, count 2 2006.258.01:13:56.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.01:13:56.68#ibcon#[25=AT08-04\r\n] 2006.258.01:13:56.68#ibcon#*before write, iclass 3, count 2 2006.258.01:13:56.68#ibcon#enter sib2, iclass 3, count 2 2006.258.01:13:56.68#ibcon#flushed, iclass 3, count 2 2006.258.01:13:56.68#ibcon#about to write, iclass 3, count 2 2006.258.01:13:56.68#ibcon#wrote, iclass 3, count 2 2006.258.01:13:56.68#ibcon#about to read 3, iclass 3, count 2 2006.258.01:13:56.71#ibcon#read 3, iclass 3, count 2 2006.258.01:13:56.71#ibcon#about to read 4, iclass 3, count 2 2006.258.01:13:56.71#ibcon#read 4, iclass 3, count 2 2006.258.01:13:56.71#ibcon#about to read 5, iclass 3, count 2 2006.258.01:13:56.71#ibcon#read 5, iclass 3, count 2 2006.258.01:13:56.71#ibcon#about to read 6, iclass 3, count 2 2006.258.01:13:56.71#ibcon#read 6, iclass 3, count 2 2006.258.01:13:56.71#ibcon#end of sib2, iclass 3, count 2 2006.258.01:13:56.71#ibcon#*after write, iclass 3, count 2 2006.258.01:13:56.71#ibcon#*before return 0, iclass 3, count 2 2006.258.01:13:56.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:13:56.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:13:56.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.01:13:56.71#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:56.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:13:56.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:13:56.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:13:56.83#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:13:56.83#ibcon#first serial, iclass 3, count 0 2006.258.01:13:56.83#ibcon#enter sib2, iclass 3, count 0 2006.258.01:13:56.83#ibcon#flushed, iclass 3, count 0 2006.258.01:13:56.83#ibcon#about to write, iclass 3, count 0 2006.258.01:13:56.83#ibcon#wrote, iclass 3, count 0 2006.258.01:13:56.83#ibcon#about to read 3, iclass 3, count 0 2006.258.01:13:56.85#ibcon#read 3, iclass 3, count 0 2006.258.01:13:56.85#ibcon#about to read 4, iclass 3, count 0 2006.258.01:13:56.85#ibcon#read 4, iclass 3, count 0 2006.258.01:13:56.85#ibcon#about to read 5, iclass 3, count 0 2006.258.01:13:56.85#ibcon#read 5, iclass 3, count 0 2006.258.01:13:56.85#ibcon#about to read 6, iclass 3, count 0 2006.258.01:13:56.85#ibcon#read 6, iclass 3, count 0 2006.258.01:13:56.85#ibcon#end of sib2, iclass 3, count 0 2006.258.01:13:56.85#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:13:56.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:13:56.85#ibcon#[25=USB\r\n] 2006.258.01:13:56.85#ibcon#*before write, iclass 3, count 0 2006.258.01:13:56.85#ibcon#enter sib2, iclass 3, count 0 2006.258.01:13:56.85#ibcon#flushed, iclass 3, count 0 2006.258.01:13:56.85#ibcon#about to write, iclass 3, count 0 2006.258.01:13:56.85#ibcon#wrote, iclass 3, count 0 2006.258.01:13:56.85#ibcon#about to read 3, iclass 3, count 0 2006.258.01:13:56.88#ibcon#read 3, iclass 3, count 0 2006.258.01:13:56.88#ibcon#about to read 4, iclass 3, count 0 2006.258.01:13:56.88#ibcon#read 4, iclass 3, count 0 2006.258.01:13:56.88#ibcon#about to read 5, iclass 3, count 0 2006.258.01:13:56.88#ibcon#read 5, iclass 3, count 0 2006.258.01:13:56.88#ibcon#about to read 6, iclass 3, count 0 2006.258.01:13:56.88#ibcon#read 6, iclass 3, count 0 2006.258.01:13:56.88#ibcon#end of sib2, iclass 3, count 0 2006.258.01:13:56.88#ibcon#*after write, iclass 3, count 0 2006.258.01:13:56.88#ibcon#*before return 0, iclass 3, count 0 2006.258.01:13:56.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:13:56.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:13:56.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:13:56.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:13:56.88$vck44/vblo=1,629.99 2006.258.01:13:56.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.01:13:56.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.01:13:56.88#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:56.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:56.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:56.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:56.88#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:13:56.88#ibcon#first serial, iclass 5, count 0 2006.258.01:13:56.88#ibcon#enter sib2, iclass 5, count 0 2006.258.01:13:56.88#ibcon#flushed, iclass 5, count 0 2006.258.01:13:56.88#ibcon#about to write, iclass 5, count 0 2006.258.01:13:56.88#ibcon#wrote, iclass 5, count 0 2006.258.01:13:56.88#ibcon#about to read 3, iclass 5, count 0 2006.258.01:13:56.90#ibcon#read 3, iclass 5, count 0 2006.258.01:13:56.90#ibcon#about to read 4, iclass 5, count 0 2006.258.01:13:56.90#ibcon#read 4, iclass 5, count 0 2006.258.01:13:56.90#ibcon#about to read 5, iclass 5, count 0 2006.258.01:13:56.90#ibcon#read 5, iclass 5, count 0 2006.258.01:13:56.90#ibcon#about to read 6, iclass 5, count 0 2006.258.01:13:56.90#ibcon#read 6, iclass 5, count 0 2006.258.01:13:56.90#ibcon#end of sib2, iclass 5, count 0 2006.258.01:13:56.90#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:13:56.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:13:56.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.01:13:56.90#ibcon#*before write, iclass 5, count 0 2006.258.01:13:56.90#ibcon#enter sib2, iclass 5, count 0 2006.258.01:13:56.90#ibcon#flushed, iclass 5, count 0 2006.258.01:13:56.90#ibcon#about to write, iclass 5, count 0 2006.258.01:13:56.90#ibcon#wrote, iclass 5, count 0 2006.258.01:13:56.90#ibcon#about to read 3, iclass 5, count 0 2006.258.01:13:56.94#ibcon#read 3, iclass 5, count 0 2006.258.01:13:56.94#ibcon#about to read 4, iclass 5, count 0 2006.258.01:13:56.94#ibcon#read 4, iclass 5, count 0 2006.258.01:13:56.94#ibcon#about to read 5, iclass 5, count 0 2006.258.01:13:56.94#ibcon#read 5, iclass 5, count 0 2006.258.01:13:56.94#ibcon#about to read 6, iclass 5, count 0 2006.258.01:13:56.94#ibcon#read 6, iclass 5, count 0 2006.258.01:13:56.94#ibcon#end of sib2, iclass 5, count 0 2006.258.01:13:56.94#ibcon#*after write, iclass 5, count 0 2006.258.01:13:56.94#ibcon#*before return 0, iclass 5, count 0 2006.258.01:13:56.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:56.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:13:56.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:13:56.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:13:56.94$vck44/vb=1,4 2006.258.01:13:56.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.01:13:56.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.01:13:56.94#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:56.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:56.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:56.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:56.94#ibcon#enter wrdev, iclass 7, count 2 2006.258.01:13:56.94#ibcon#first serial, iclass 7, count 2 2006.258.01:13:56.94#ibcon#enter sib2, iclass 7, count 2 2006.258.01:13:56.94#ibcon#flushed, iclass 7, count 2 2006.258.01:13:56.94#ibcon#about to write, iclass 7, count 2 2006.258.01:13:56.94#ibcon#wrote, iclass 7, count 2 2006.258.01:13:56.94#ibcon#about to read 3, iclass 7, count 2 2006.258.01:13:56.96#ibcon#read 3, iclass 7, count 2 2006.258.01:13:56.96#ibcon#about to read 4, iclass 7, count 2 2006.258.01:13:56.96#ibcon#read 4, iclass 7, count 2 2006.258.01:13:56.96#ibcon#about to read 5, iclass 7, count 2 2006.258.01:13:56.96#ibcon#read 5, iclass 7, count 2 2006.258.01:13:56.96#ibcon#about to read 6, iclass 7, count 2 2006.258.01:13:56.96#ibcon#read 6, iclass 7, count 2 2006.258.01:13:56.96#ibcon#end of sib2, iclass 7, count 2 2006.258.01:13:56.96#ibcon#*mode == 0, iclass 7, count 2 2006.258.01:13:56.96#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.01:13:56.96#ibcon#[27=AT01-04\r\n] 2006.258.01:13:56.96#ibcon#*before write, iclass 7, count 2 2006.258.01:13:56.96#ibcon#enter sib2, iclass 7, count 2 2006.258.01:13:56.96#ibcon#flushed, iclass 7, count 2 2006.258.01:13:56.96#ibcon#about to write, iclass 7, count 2 2006.258.01:13:56.96#ibcon#wrote, iclass 7, count 2 2006.258.01:13:56.96#ibcon#about to read 3, iclass 7, count 2 2006.258.01:13:56.99#ibcon#read 3, iclass 7, count 2 2006.258.01:13:56.99#ibcon#about to read 4, iclass 7, count 2 2006.258.01:13:56.99#ibcon#read 4, iclass 7, count 2 2006.258.01:13:56.99#ibcon#about to read 5, iclass 7, count 2 2006.258.01:13:56.99#ibcon#read 5, iclass 7, count 2 2006.258.01:13:56.99#ibcon#about to read 6, iclass 7, count 2 2006.258.01:13:56.99#ibcon#read 6, iclass 7, count 2 2006.258.01:13:56.99#ibcon#end of sib2, iclass 7, count 2 2006.258.01:13:56.99#ibcon#*after write, iclass 7, count 2 2006.258.01:13:56.99#ibcon#*before return 0, iclass 7, count 2 2006.258.01:13:56.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:56.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:13:56.99#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.01:13:56.99#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:56.99#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:57.11#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:57.11#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:57.11#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:13:57.11#ibcon#first serial, iclass 7, count 0 2006.258.01:13:57.11#ibcon#enter sib2, iclass 7, count 0 2006.258.01:13:57.11#ibcon#flushed, iclass 7, count 0 2006.258.01:13:57.11#ibcon#about to write, iclass 7, count 0 2006.258.01:13:57.11#ibcon#wrote, iclass 7, count 0 2006.258.01:13:57.11#ibcon#about to read 3, iclass 7, count 0 2006.258.01:13:57.13#ibcon#read 3, iclass 7, count 0 2006.258.01:13:57.13#ibcon#about to read 4, iclass 7, count 0 2006.258.01:13:57.13#ibcon#read 4, iclass 7, count 0 2006.258.01:13:57.13#ibcon#about to read 5, iclass 7, count 0 2006.258.01:13:57.13#ibcon#read 5, iclass 7, count 0 2006.258.01:13:57.13#ibcon#about to read 6, iclass 7, count 0 2006.258.01:13:57.13#ibcon#read 6, iclass 7, count 0 2006.258.01:13:57.13#ibcon#end of sib2, iclass 7, count 0 2006.258.01:13:57.13#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:13:57.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:13:57.13#ibcon#[27=USB\r\n] 2006.258.01:13:57.13#ibcon#*before write, iclass 7, count 0 2006.258.01:13:57.13#ibcon#enter sib2, iclass 7, count 0 2006.258.01:13:57.13#ibcon#flushed, iclass 7, count 0 2006.258.01:13:57.13#ibcon#about to write, iclass 7, count 0 2006.258.01:13:57.13#ibcon#wrote, iclass 7, count 0 2006.258.01:13:57.13#ibcon#about to read 3, iclass 7, count 0 2006.258.01:13:57.16#ibcon#read 3, iclass 7, count 0 2006.258.01:13:57.16#ibcon#about to read 4, iclass 7, count 0 2006.258.01:13:57.16#ibcon#read 4, iclass 7, count 0 2006.258.01:13:57.16#ibcon#about to read 5, iclass 7, count 0 2006.258.01:13:57.16#ibcon#read 5, iclass 7, count 0 2006.258.01:13:57.16#ibcon#about to read 6, iclass 7, count 0 2006.258.01:13:57.16#ibcon#read 6, iclass 7, count 0 2006.258.01:13:57.16#ibcon#end of sib2, iclass 7, count 0 2006.258.01:13:57.16#ibcon#*after write, iclass 7, count 0 2006.258.01:13:57.16#ibcon#*before return 0, iclass 7, count 0 2006.258.01:13:57.16#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:57.16#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:13:57.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:13:57.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:13:57.16$vck44/vblo=2,634.99 2006.258.01:13:57.16#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.01:13:57.16#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.01:13:57.16#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:57.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:57.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:57.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:57.16#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:13:57.16#ibcon#first serial, iclass 11, count 0 2006.258.01:13:57.16#ibcon#enter sib2, iclass 11, count 0 2006.258.01:13:57.16#ibcon#flushed, iclass 11, count 0 2006.258.01:13:57.16#ibcon#about to write, iclass 11, count 0 2006.258.01:13:57.16#ibcon#wrote, iclass 11, count 0 2006.258.01:13:57.16#ibcon#about to read 3, iclass 11, count 0 2006.258.01:13:57.18#ibcon#read 3, iclass 11, count 0 2006.258.01:13:57.18#ibcon#about to read 4, iclass 11, count 0 2006.258.01:13:57.18#ibcon#read 4, iclass 11, count 0 2006.258.01:13:57.18#ibcon#about to read 5, iclass 11, count 0 2006.258.01:13:57.18#ibcon#read 5, iclass 11, count 0 2006.258.01:13:57.18#ibcon#about to read 6, iclass 11, count 0 2006.258.01:13:57.18#ibcon#read 6, iclass 11, count 0 2006.258.01:13:57.18#ibcon#end of sib2, iclass 11, count 0 2006.258.01:13:57.18#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:13:57.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:13:57.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.01:13:57.18#ibcon#*before write, iclass 11, count 0 2006.258.01:13:57.18#ibcon#enter sib2, iclass 11, count 0 2006.258.01:13:57.18#ibcon#flushed, iclass 11, count 0 2006.258.01:13:57.18#ibcon#about to write, iclass 11, count 0 2006.258.01:13:57.18#ibcon#wrote, iclass 11, count 0 2006.258.01:13:57.18#ibcon#about to read 3, iclass 11, count 0 2006.258.01:13:57.22#ibcon#read 3, iclass 11, count 0 2006.258.01:13:57.22#ibcon#about to read 4, iclass 11, count 0 2006.258.01:13:57.22#ibcon#read 4, iclass 11, count 0 2006.258.01:13:57.22#ibcon#about to read 5, iclass 11, count 0 2006.258.01:13:57.22#ibcon#read 5, iclass 11, count 0 2006.258.01:13:57.22#ibcon#about to read 6, iclass 11, count 0 2006.258.01:13:57.22#ibcon#read 6, iclass 11, count 0 2006.258.01:13:57.22#ibcon#end of sib2, iclass 11, count 0 2006.258.01:13:57.22#ibcon#*after write, iclass 11, count 0 2006.258.01:13:57.22#ibcon#*before return 0, iclass 11, count 0 2006.258.01:13:57.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:57.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:13:57.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:13:57.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:13:57.22$vck44/vb=2,5 2006.258.01:13:57.22#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.01:13:57.22#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.01:13:57.22#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:57.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:57.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:57.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:57.28#ibcon#enter wrdev, iclass 13, count 2 2006.258.01:13:57.28#ibcon#first serial, iclass 13, count 2 2006.258.01:13:57.28#ibcon#enter sib2, iclass 13, count 2 2006.258.01:13:57.28#ibcon#flushed, iclass 13, count 2 2006.258.01:13:57.28#ibcon#about to write, iclass 13, count 2 2006.258.01:13:57.28#ibcon#wrote, iclass 13, count 2 2006.258.01:13:57.28#ibcon#about to read 3, iclass 13, count 2 2006.258.01:13:57.30#ibcon#read 3, iclass 13, count 2 2006.258.01:13:57.30#ibcon#about to read 4, iclass 13, count 2 2006.258.01:13:57.30#ibcon#read 4, iclass 13, count 2 2006.258.01:13:57.30#ibcon#about to read 5, iclass 13, count 2 2006.258.01:13:57.30#ibcon#read 5, iclass 13, count 2 2006.258.01:13:57.30#ibcon#about to read 6, iclass 13, count 2 2006.258.01:13:57.30#ibcon#read 6, iclass 13, count 2 2006.258.01:13:57.30#ibcon#end of sib2, iclass 13, count 2 2006.258.01:13:57.30#ibcon#*mode == 0, iclass 13, count 2 2006.258.01:13:57.30#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.01:13:57.30#ibcon#[27=AT02-05\r\n] 2006.258.01:13:57.30#ibcon#*before write, iclass 13, count 2 2006.258.01:13:57.30#ibcon#enter sib2, iclass 13, count 2 2006.258.01:13:57.30#ibcon#flushed, iclass 13, count 2 2006.258.01:13:57.30#ibcon#about to write, iclass 13, count 2 2006.258.01:13:57.30#ibcon#wrote, iclass 13, count 2 2006.258.01:13:57.30#ibcon#about to read 3, iclass 13, count 2 2006.258.01:13:57.33#ibcon#read 3, iclass 13, count 2 2006.258.01:13:57.33#ibcon#about to read 4, iclass 13, count 2 2006.258.01:13:57.33#ibcon#read 4, iclass 13, count 2 2006.258.01:13:57.38#ibcon#about to read 5, iclass 13, count 2 2006.258.01:13:57.38#ibcon#read 5, iclass 13, count 2 2006.258.01:13:57.38#ibcon#about to read 6, iclass 13, count 2 2006.258.01:13:57.38#ibcon#read 6, iclass 13, count 2 2006.258.01:13:57.38#ibcon#end of sib2, iclass 13, count 2 2006.258.01:13:57.38#ibcon#*after write, iclass 13, count 2 2006.258.01:13:57.38#ibcon#*before return 0, iclass 13, count 2 2006.258.01:13:57.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:57.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:13:57.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.01:13:57.39#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:57.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:57.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:57.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:57.50#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:13:57.50#ibcon#first serial, iclass 13, count 0 2006.258.01:13:57.50#ibcon#enter sib2, iclass 13, count 0 2006.258.01:13:57.50#ibcon#flushed, iclass 13, count 0 2006.258.01:13:57.50#ibcon#about to write, iclass 13, count 0 2006.258.01:13:57.50#ibcon#wrote, iclass 13, count 0 2006.258.01:13:57.50#ibcon#about to read 3, iclass 13, count 0 2006.258.01:13:57.52#ibcon#read 3, iclass 13, count 0 2006.258.01:13:57.52#ibcon#about to read 4, iclass 13, count 0 2006.258.01:13:57.52#ibcon#read 4, iclass 13, count 0 2006.258.01:13:57.52#ibcon#about to read 5, iclass 13, count 0 2006.258.01:13:57.52#ibcon#read 5, iclass 13, count 0 2006.258.01:13:57.52#ibcon#about to read 6, iclass 13, count 0 2006.258.01:13:57.52#ibcon#read 6, iclass 13, count 0 2006.258.01:13:57.52#ibcon#end of sib2, iclass 13, count 0 2006.258.01:13:57.52#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:13:57.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:13:57.52#ibcon#[27=USB\r\n] 2006.258.01:13:57.52#ibcon#*before write, iclass 13, count 0 2006.258.01:13:57.52#ibcon#enter sib2, iclass 13, count 0 2006.258.01:13:57.52#ibcon#flushed, iclass 13, count 0 2006.258.01:13:57.52#ibcon#about to write, iclass 13, count 0 2006.258.01:13:57.52#ibcon#wrote, iclass 13, count 0 2006.258.01:13:57.52#ibcon#about to read 3, iclass 13, count 0 2006.258.01:13:57.55#ibcon#read 3, iclass 13, count 0 2006.258.01:13:57.55#ibcon#about to read 4, iclass 13, count 0 2006.258.01:13:57.55#ibcon#read 4, iclass 13, count 0 2006.258.01:13:57.55#ibcon#about to read 5, iclass 13, count 0 2006.258.01:13:57.55#ibcon#read 5, iclass 13, count 0 2006.258.01:13:57.55#ibcon#about to read 6, iclass 13, count 0 2006.258.01:13:57.55#ibcon#read 6, iclass 13, count 0 2006.258.01:13:57.55#ibcon#end of sib2, iclass 13, count 0 2006.258.01:13:57.55#ibcon#*after write, iclass 13, count 0 2006.258.01:13:57.55#ibcon#*before return 0, iclass 13, count 0 2006.258.01:13:57.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:57.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:13:57.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:13:57.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:13:57.55$vck44/vblo=3,649.99 2006.258.01:13:57.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.01:13:57.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.01:13:57.55#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:57.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:57.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:57.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:57.55#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:13:57.55#ibcon#first serial, iclass 15, count 0 2006.258.01:13:57.55#ibcon#enter sib2, iclass 15, count 0 2006.258.01:13:57.55#ibcon#flushed, iclass 15, count 0 2006.258.01:13:57.55#ibcon#about to write, iclass 15, count 0 2006.258.01:13:57.55#ibcon#wrote, iclass 15, count 0 2006.258.01:13:57.55#ibcon#about to read 3, iclass 15, count 0 2006.258.01:13:57.57#ibcon#read 3, iclass 15, count 0 2006.258.01:13:57.57#ibcon#about to read 4, iclass 15, count 0 2006.258.01:13:57.57#ibcon#read 4, iclass 15, count 0 2006.258.01:13:57.57#ibcon#about to read 5, iclass 15, count 0 2006.258.01:13:57.57#ibcon#read 5, iclass 15, count 0 2006.258.01:13:57.57#ibcon#about to read 6, iclass 15, count 0 2006.258.01:13:57.57#ibcon#read 6, iclass 15, count 0 2006.258.01:13:57.57#ibcon#end of sib2, iclass 15, count 0 2006.258.01:13:57.57#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:13:57.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:13:57.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.01:13:57.57#ibcon#*before write, iclass 15, count 0 2006.258.01:13:57.57#ibcon#enter sib2, iclass 15, count 0 2006.258.01:13:57.57#ibcon#flushed, iclass 15, count 0 2006.258.01:13:57.57#ibcon#about to write, iclass 15, count 0 2006.258.01:13:57.57#ibcon#wrote, iclass 15, count 0 2006.258.01:13:57.57#ibcon#about to read 3, iclass 15, count 0 2006.258.01:13:57.61#ibcon#read 3, iclass 15, count 0 2006.258.01:13:57.61#ibcon#about to read 4, iclass 15, count 0 2006.258.01:13:57.61#ibcon#read 4, iclass 15, count 0 2006.258.01:13:57.61#ibcon#about to read 5, iclass 15, count 0 2006.258.01:13:57.61#ibcon#read 5, iclass 15, count 0 2006.258.01:13:57.61#ibcon#about to read 6, iclass 15, count 0 2006.258.01:13:57.61#ibcon#read 6, iclass 15, count 0 2006.258.01:13:57.61#ibcon#end of sib2, iclass 15, count 0 2006.258.01:13:57.61#ibcon#*after write, iclass 15, count 0 2006.258.01:13:57.61#ibcon#*before return 0, iclass 15, count 0 2006.258.01:13:57.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:57.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:13:57.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:13:57.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:13:57.61$vck44/vb=3,4 2006.258.01:13:57.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.01:13:57.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.01:13:57.61#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:57.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:57.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:57.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:57.67#ibcon#enter wrdev, iclass 17, count 2 2006.258.01:13:57.67#ibcon#first serial, iclass 17, count 2 2006.258.01:13:57.67#ibcon#enter sib2, iclass 17, count 2 2006.258.01:13:57.67#ibcon#flushed, iclass 17, count 2 2006.258.01:13:57.67#ibcon#about to write, iclass 17, count 2 2006.258.01:13:57.67#ibcon#wrote, iclass 17, count 2 2006.258.01:13:57.67#ibcon#about to read 3, iclass 17, count 2 2006.258.01:13:57.69#ibcon#read 3, iclass 17, count 2 2006.258.01:13:57.69#ibcon#about to read 4, iclass 17, count 2 2006.258.01:13:57.69#ibcon#read 4, iclass 17, count 2 2006.258.01:13:57.69#ibcon#about to read 5, iclass 17, count 2 2006.258.01:13:57.69#ibcon#read 5, iclass 17, count 2 2006.258.01:13:57.69#ibcon#about to read 6, iclass 17, count 2 2006.258.01:13:57.69#ibcon#read 6, iclass 17, count 2 2006.258.01:13:57.69#ibcon#end of sib2, iclass 17, count 2 2006.258.01:13:57.69#ibcon#*mode == 0, iclass 17, count 2 2006.258.01:13:57.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.01:13:57.69#ibcon#[27=AT03-04\r\n] 2006.258.01:13:57.69#ibcon#*before write, iclass 17, count 2 2006.258.01:13:57.69#ibcon#enter sib2, iclass 17, count 2 2006.258.01:13:57.69#ibcon#flushed, iclass 17, count 2 2006.258.01:13:57.69#ibcon#about to write, iclass 17, count 2 2006.258.01:13:57.69#ibcon#wrote, iclass 17, count 2 2006.258.01:13:57.69#ibcon#about to read 3, iclass 17, count 2 2006.258.01:13:57.72#ibcon#read 3, iclass 17, count 2 2006.258.01:13:57.72#ibcon#about to read 4, iclass 17, count 2 2006.258.01:13:57.72#ibcon#read 4, iclass 17, count 2 2006.258.01:13:57.72#ibcon#about to read 5, iclass 17, count 2 2006.258.01:13:57.72#ibcon#read 5, iclass 17, count 2 2006.258.01:13:57.72#ibcon#about to read 6, iclass 17, count 2 2006.258.01:13:57.72#ibcon#read 6, iclass 17, count 2 2006.258.01:13:57.72#ibcon#end of sib2, iclass 17, count 2 2006.258.01:13:57.72#ibcon#*after write, iclass 17, count 2 2006.258.01:13:57.72#ibcon#*before return 0, iclass 17, count 2 2006.258.01:13:57.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:57.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:13:57.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.01:13:57.72#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:57.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:57.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:57.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:57.84#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:13:57.84#ibcon#first serial, iclass 17, count 0 2006.258.01:13:57.84#ibcon#enter sib2, iclass 17, count 0 2006.258.01:13:57.84#ibcon#flushed, iclass 17, count 0 2006.258.01:13:57.84#ibcon#about to write, iclass 17, count 0 2006.258.01:13:57.84#ibcon#wrote, iclass 17, count 0 2006.258.01:13:57.84#ibcon#about to read 3, iclass 17, count 0 2006.258.01:13:57.86#ibcon#read 3, iclass 17, count 0 2006.258.01:13:57.86#ibcon#about to read 4, iclass 17, count 0 2006.258.01:13:57.86#ibcon#read 4, iclass 17, count 0 2006.258.01:13:57.86#ibcon#about to read 5, iclass 17, count 0 2006.258.01:13:57.86#ibcon#read 5, iclass 17, count 0 2006.258.01:13:57.86#ibcon#about to read 6, iclass 17, count 0 2006.258.01:13:57.86#ibcon#read 6, iclass 17, count 0 2006.258.01:13:57.86#ibcon#end of sib2, iclass 17, count 0 2006.258.01:13:57.86#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:13:57.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:13:57.86#ibcon#[27=USB\r\n] 2006.258.01:13:57.86#ibcon#*before write, iclass 17, count 0 2006.258.01:13:57.86#ibcon#enter sib2, iclass 17, count 0 2006.258.01:13:57.86#ibcon#flushed, iclass 17, count 0 2006.258.01:13:57.86#ibcon#about to write, iclass 17, count 0 2006.258.01:13:57.86#ibcon#wrote, iclass 17, count 0 2006.258.01:13:57.86#ibcon#about to read 3, iclass 17, count 0 2006.258.01:13:57.89#ibcon#read 3, iclass 17, count 0 2006.258.01:13:57.89#ibcon#about to read 4, iclass 17, count 0 2006.258.01:13:57.89#ibcon#read 4, iclass 17, count 0 2006.258.01:13:57.89#ibcon#about to read 5, iclass 17, count 0 2006.258.01:13:57.89#ibcon#read 5, iclass 17, count 0 2006.258.01:13:57.89#ibcon#about to read 6, iclass 17, count 0 2006.258.01:13:57.89#ibcon#read 6, iclass 17, count 0 2006.258.01:13:57.89#ibcon#end of sib2, iclass 17, count 0 2006.258.01:13:57.89#ibcon#*after write, iclass 17, count 0 2006.258.01:13:57.89#ibcon#*before return 0, iclass 17, count 0 2006.258.01:13:57.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:57.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:13:57.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:13:57.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:13:57.89$vck44/vblo=4,679.99 2006.258.01:13:57.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.01:13:57.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.01:13:57.89#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:57.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:57.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:57.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:57.89#ibcon#enter wrdev, iclass 19, count 0 2006.258.01:13:57.89#ibcon#first serial, iclass 19, count 0 2006.258.01:13:57.89#ibcon#enter sib2, iclass 19, count 0 2006.258.01:13:57.89#ibcon#flushed, iclass 19, count 0 2006.258.01:13:57.89#ibcon#about to write, iclass 19, count 0 2006.258.01:13:57.89#ibcon#wrote, iclass 19, count 0 2006.258.01:13:57.89#ibcon#about to read 3, iclass 19, count 0 2006.258.01:13:57.91#ibcon#read 3, iclass 19, count 0 2006.258.01:13:57.91#ibcon#about to read 4, iclass 19, count 0 2006.258.01:13:57.91#ibcon#read 4, iclass 19, count 0 2006.258.01:13:57.91#ibcon#about to read 5, iclass 19, count 0 2006.258.01:13:57.91#ibcon#read 5, iclass 19, count 0 2006.258.01:13:57.91#ibcon#about to read 6, iclass 19, count 0 2006.258.01:13:57.91#ibcon#read 6, iclass 19, count 0 2006.258.01:13:57.91#ibcon#end of sib2, iclass 19, count 0 2006.258.01:13:57.91#ibcon#*mode == 0, iclass 19, count 0 2006.258.01:13:57.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.01:13:57.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.01:13:57.91#ibcon#*before write, iclass 19, count 0 2006.258.01:13:57.91#ibcon#enter sib2, iclass 19, count 0 2006.258.01:13:57.91#ibcon#flushed, iclass 19, count 0 2006.258.01:13:57.91#ibcon#about to write, iclass 19, count 0 2006.258.01:13:57.91#ibcon#wrote, iclass 19, count 0 2006.258.01:13:57.91#ibcon#about to read 3, iclass 19, count 0 2006.258.01:13:57.95#ibcon#read 3, iclass 19, count 0 2006.258.01:13:57.95#ibcon#about to read 4, iclass 19, count 0 2006.258.01:13:57.95#ibcon#read 4, iclass 19, count 0 2006.258.01:13:57.95#ibcon#about to read 5, iclass 19, count 0 2006.258.01:13:57.95#ibcon#read 5, iclass 19, count 0 2006.258.01:13:57.95#ibcon#about to read 6, iclass 19, count 0 2006.258.01:13:57.95#ibcon#read 6, iclass 19, count 0 2006.258.01:13:57.95#ibcon#end of sib2, iclass 19, count 0 2006.258.01:13:57.95#ibcon#*after write, iclass 19, count 0 2006.258.01:13:57.95#ibcon#*before return 0, iclass 19, count 0 2006.258.01:13:57.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:57.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:13:57.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.01:13:57.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.01:13:57.95$vck44/vb=4,5 2006.258.01:13:57.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.01:13:57.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.01:13:57.95#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:57.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:58.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:58.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:58.01#ibcon#enter wrdev, iclass 21, count 2 2006.258.01:13:58.01#ibcon#first serial, iclass 21, count 2 2006.258.01:13:58.01#ibcon#enter sib2, iclass 21, count 2 2006.258.01:13:58.01#ibcon#flushed, iclass 21, count 2 2006.258.01:13:58.01#ibcon#about to write, iclass 21, count 2 2006.258.01:13:58.01#ibcon#wrote, iclass 21, count 2 2006.258.01:13:58.01#ibcon#about to read 3, iclass 21, count 2 2006.258.01:13:58.03#ibcon#read 3, iclass 21, count 2 2006.258.01:13:58.03#ibcon#about to read 4, iclass 21, count 2 2006.258.01:13:58.03#ibcon#read 4, iclass 21, count 2 2006.258.01:13:58.03#ibcon#about to read 5, iclass 21, count 2 2006.258.01:13:58.03#ibcon#read 5, iclass 21, count 2 2006.258.01:13:58.03#ibcon#about to read 6, iclass 21, count 2 2006.258.01:13:58.03#ibcon#read 6, iclass 21, count 2 2006.258.01:13:58.03#ibcon#end of sib2, iclass 21, count 2 2006.258.01:13:58.03#ibcon#*mode == 0, iclass 21, count 2 2006.258.01:13:58.03#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.01:13:58.03#ibcon#[27=AT04-05\r\n] 2006.258.01:13:58.03#ibcon#*before write, iclass 21, count 2 2006.258.01:13:58.03#ibcon#enter sib2, iclass 21, count 2 2006.258.01:13:58.03#ibcon#flushed, iclass 21, count 2 2006.258.01:13:58.03#ibcon#about to write, iclass 21, count 2 2006.258.01:13:58.03#ibcon#wrote, iclass 21, count 2 2006.258.01:13:58.03#ibcon#about to read 3, iclass 21, count 2 2006.258.01:13:58.06#ibcon#read 3, iclass 21, count 2 2006.258.01:13:58.06#ibcon#about to read 4, iclass 21, count 2 2006.258.01:13:58.06#ibcon#read 4, iclass 21, count 2 2006.258.01:13:58.06#ibcon#about to read 5, iclass 21, count 2 2006.258.01:13:58.06#ibcon#read 5, iclass 21, count 2 2006.258.01:13:58.06#ibcon#about to read 6, iclass 21, count 2 2006.258.01:13:58.06#ibcon#read 6, iclass 21, count 2 2006.258.01:13:58.06#ibcon#end of sib2, iclass 21, count 2 2006.258.01:13:58.06#ibcon#*after write, iclass 21, count 2 2006.258.01:13:58.06#ibcon#*before return 0, iclass 21, count 2 2006.258.01:13:58.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:58.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:13:58.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.01:13:58.06#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:58.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:58.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:58.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:58.18#ibcon#enter wrdev, iclass 21, count 0 2006.258.01:13:58.18#ibcon#first serial, iclass 21, count 0 2006.258.01:13:58.18#ibcon#enter sib2, iclass 21, count 0 2006.258.01:13:58.18#ibcon#flushed, iclass 21, count 0 2006.258.01:13:58.18#ibcon#about to write, iclass 21, count 0 2006.258.01:13:58.18#ibcon#wrote, iclass 21, count 0 2006.258.01:13:58.18#ibcon#about to read 3, iclass 21, count 0 2006.258.01:13:58.20#ibcon#read 3, iclass 21, count 0 2006.258.01:13:58.20#ibcon#about to read 4, iclass 21, count 0 2006.258.01:13:58.20#ibcon#read 4, iclass 21, count 0 2006.258.01:13:58.20#ibcon#about to read 5, iclass 21, count 0 2006.258.01:13:58.20#ibcon#read 5, iclass 21, count 0 2006.258.01:13:58.20#ibcon#about to read 6, iclass 21, count 0 2006.258.01:13:58.20#ibcon#read 6, iclass 21, count 0 2006.258.01:13:58.20#ibcon#end of sib2, iclass 21, count 0 2006.258.01:13:58.20#ibcon#*mode == 0, iclass 21, count 0 2006.258.01:13:58.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.01:13:58.20#ibcon#[27=USB\r\n] 2006.258.01:13:58.20#ibcon#*before write, iclass 21, count 0 2006.258.01:13:58.20#ibcon#enter sib2, iclass 21, count 0 2006.258.01:13:58.20#ibcon#flushed, iclass 21, count 0 2006.258.01:13:58.20#ibcon#about to write, iclass 21, count 0 2006.258.01:13:58.20#ibcon#wrote, iclass 21, count 0 2006.258.01:13:58.20#ibcon#about to read 3, iclass 21, count 0 2006.258.01:13:58.23#ibcon#read 3, iclass 21, count 0 2006.258.01:13:58.23#ibcon#about to read 4, iclass 21, count 0 2006.258.01:13:58.23#ibcon#read 4, iclass 21, count 0 2006.258.01:13:58.23#ibcon#about to read 5, iclass 21, count 0 2006.258.01:13:58.23#ibcon#read 5, iclass 21, count 0 2006.258.01:13:58.23#ibcon#about to read 6, iclass 21, count 0 2006.258.01:13:58.23#ibcon#read 6, iclass 21, count 0 2006.258.01:13:58.23#ibcon#end of sib2, iclass 21, count 0 2006.258.01:13:58.23#ibcon#*after write, iclass 21, count 0 2006.258.01:13:58.23#ibcon#*before return 0, iclass 21, count 0 2006.258.01:13:58.23#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:58.23#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:13:58.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.01:13:58.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.01:13:58.23$vck44/vblo=5,709.99 2006.258.01:13:58.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.01:13:58.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.01:13:58.23#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:58.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:58.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:58.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:58.23#ibcon#enter wrdev, iclass 23, count 0 2006.258.01:13:58.23#ibcon#first serial, iclass 23, count 0 2006.258.01:13:58.23#ibcon#enter sib2, iclass 23, count 0 2006.258.01:13:58.23#ibcon#flushed, iclass 23, count 0 2006.258.01:13:58.23#ibcon#about to write, iclass 23, count 0 2006.258.01:13:58.23#ibcon#wrote, iclass 23, count 0 2006.258.01:13:58.23#ibcon#about to read 3, iclass 23, count 0 2006.258.01:13:58.25#ibcon#read 3, iclass 23, count 0 2006.258.01:13:58.25#ibcon#about to read 4, iclass 23, count 0 2006.258.01:13:58.25#ibcon#read 4, iclass 23, count 0 2006.258.01:13:58.25#ibcon#about to read 5, iclass 23, count 0 2006.258.01:13:58.25#ibcon#read 5, iclass 23, count 0 2006.258.01:13:58.25#ibcon#about to read 6, iclass 23, count 0 2006.258.01:13:58.25#ibcon#read 6, iclass 23, count 0 2006.258.01:13:58.25#ibcon#end of sib2, iclass 23, count 0 2006.258.01:13:58.25#ibcon#*mode == 0, iclass 23, count 0 2006.258.01:13:58.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.01:13:58.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.01:13:58.25#ibcon#*before write, iclass 23, count 0 2006.258.01:13:58.25#ibcon#enter sib2, iclass 23, count 0 2006.258.01:13:58.25#ibcon#flushed, iclass 23, count 0 2006.258.01:13:58.25#ibcon#about to write, iclass 23, count 0 2006.258.01:13:58.25#ibcon#wrote, iclass 23, count 0 2006.258.01:13:58.25#ibcon#about to read 3, iclass 23, count 0 2006.258.01:13:58.29#ibcon#read 3, iclass 23, count 0 2006.258.01:13:58.29#ibcon#about to read 4, iclass 23, count 0 2006.258.01:13:58.29#ibcon#read 4, iclass 23, count 0 2006.258.01:13:58.29#ibcon#about to read 5, iclass 23, count 0 2006.258.01:13:58.29#ibcon#read 5, iclass 23, count 0 2006.258.01:13:58.29#ibcon#about to read 6, iclass 23, count 0 2006.258.01:13:58.29#ibcon#read 6, iclass 23, count 0 2006.258.01:13:58.29#ibcon#end of sib2, iclass 23, count 0 2006.258.01:13:58.29#ibcon#*after write, iclass 23, count 0 2006.258.01:13:58.29#ibcon#*before return 0, iclass 23, count 0 2006.258.01:13:58.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:58.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:13:58.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.01:13:58.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.01:13:58.29$vck44/vb=5,4 2006.258.01:13:58.29#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.258.01:13:58.29#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.258.01:13:58.29#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:58.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:58.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:58.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:58.35#ibcon#enter wrdev, iclass 25, count 2 2006.258.01:13:58.35#ibcon#first serial, iclass 25, count 2 2006.258.01:13:58.35#ibcon#enter sib2, iclass 25, count 2 2006.258.01:13:58.35#ibcon#flushed, iclass 25, count 2 2006.258.01:13:58.35#ibcon#about to write, iclass 25, count 2 2006.258.01:13:58.35#ibcon#wrote, iclass 25, count 2 2006.258.01:13:58.35#ibcon#about to read 3, iclass 25, count 2 2006.258.01:13:58.37#ibcon#read 3, iclass 25, count 2 2006.258.01:13:58.37#ibcon#about to read 4, iclass 25, count 2 2006.258.01:13:58.37#ibcon#read 4, iclass 25, count 2 2006.258.01:13:58.37#ibcon#about to read 5, iclass 25, count 2 2006.258.01:13:58.37#ibcon#read 5, iclass 25, count 2 2006.258.01:13:58.37#ibcon#about to read 6, iclass 25, count 2 2006.258.01:13:58.37#ibcon#read 6, iclass 25, count 2 2006.258.01:13:58.37#ibcon#end of sib2, iclass 25, count 2 2006.258.01:13:58.37#ibcon#*mode == 0, iclass 25, count 2 2006.258.01:13:58.37#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.258.01:13:58.37#ibcon#[27=AT05-04\r\n] 2006.258.01:13:58.37#ibcon#*before write, iclass 25, count 2 2006.258.01:13:58.37#ibcon#enter sib2, iclass 25, count 2 2006.258.01:13:58.37#ibcon#flushed, iclass 25, count 2 2006.258.01:13:58.37#ibcon#about to write, iclass 25, count 2 2006.258.01:13:58.37#ibcon#wrote, iclass 25, count 2 2006.258.01:13:58.37#ibcon#about to read 3, iclass 25, count 2 2006.258.01:13:58.40#ibcon#read 3, iclass 25, count 2 2006.258.01:13:58.40#ibcon#about to read 4, iclass 25, count 2 2006.258.01:13:58.40#ibcon#read 4, iclass 25, count 2 2006.258.01:13:58.40#ibcon#about to read 5, iclass 25, count 2 2006.258.01:13:58.40#ibcon#read 5, iclass 25, count 2 2006.258.01:13:58.40#ibcon#about to read 6, iclass 25, count 2 2006.258.01:13:58.40#ibcon#read 6, iclass 25, count 2 2006.258.01:13:58.40#ibcon#end of sib2, iclass 25, count 2 2006.258.01:13:58.40#ibcon#*after write, iclass 25, count 2 2006.258.01:13:58.41#ibcon#*before return 0, iclass 25, count 2 2006.258.01:13:58.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:58.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:13:58.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.258.01:13:58.41#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:58.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:58.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:58.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:58.53#ibcon#enter wrdev, iclass 25, count 0 2006.258.01:13:58.53#ibcon#first serial, iclass 25, count 0 2006.258.01:13:58.53#ibcon#enter sib2, iclass 25, count 0 2006.258.01:13:58.53#ibcon#flushed, iclass 25, count 0 2006.258.01:13:58.53#ibcon#about to write, iclass 25, count 0 2006.258.01:13:58.53#ibcon#wrote, iclass 25, count 0 2006.258.01:13:58.53#ibcon#about to read 3, iclass 25, count 0 2006.258.01:13:58.55#ibcon#read 3, iclass 25, count 0 2006.258.01:13:58.55#ibcon#about to read 4, iclass 25, count 0 2006.258.01:13:58.55#ibcon#read 4, iclass 25, count 0 2006.258.01:13:58.55#ibcon#about to read 5, iclass 25, count 0 2006.258.01:13:58.55#ibcon#read 5, iclass 25, count 0 2006.258.01:13:58.55#ibcon#about to read 6, iclass 25, count 0 2006.258.01:13:58.55#ibcon#read 6, iclass 25, count 0 2006.258.01:13:58.55#ibcon#end of sib2, iclass 25, count 0 2006.258.01:13:58.55#ibcon#*mode == 0, iclass 25, count 0 2006.258.01:13:58.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.01:13:58.55#ibcon#[27=USB\r\n] 2006.258.01:13:58.55#ibcon#*before write, iclass 25, count 0 2006.258.01:13:58.55#ibcon#enter sib2, iclass 25, count 0 2006.258.01:13:58.55#ibcon#flushed, iclass 25, count 0 2006.258.01:13:58.55#ibcon#about to write, iclass 25, count 0 2006.258.01:13:58.55#ibcon#wrote, iclass 25, count 0 2006.258.01:13:58.55#ibcon#about to read 3, iclass 25, count 0 2006.258.01:13:58.58#ibcon#read 3, iclass 25, count 0 2006.258.01:13:58.58#ibcon#about to read 4, iclass 25, count 0 2006.258.01:13:58.58#ibcon#read 4, iclass 25, count 0 2006.258.01:13:58.58#ibcon#about to read 5, iclass 25, count 0 2006.258.01:13:58.58#ibcon#read 5, iclass 25, count 0 2006.258.01:13:58.58#ibcon#about to read 6, iclass 25, count 0 2006.258.01:13:58.58#ibcon#read 6, iclass 25, count 0 2006.258.01:13:58.58#ibcon#end of sib2, iclass 25, count 0 2006.258.01:13:58.58#ibcon#*after write, iclass 25, count 0 2006.258.01:13:58.58#ibcon#*before return 0, iclass 25, count 0 2006.258.01:13:58.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:58.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:13:58.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.01:13:58.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.01:13:58.58$vck44/vblo=6,719.99 2006.258.01:13:58.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.01:13:58.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.01:13:58.58#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:58.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:58.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:58.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:58.58#ibcon#enter wrdev, iclass 27, count 0 2006.258.01:13:58.58#ibcon#first serial, iclass 27, count 0 2006.258.01:13:58.58#ibcon#enter sib2, iclass 27, count 0 2006.258.01:13:58.58#ibcon#flushed, iclass 27, count 0 2006.258.01:13:58.58#ibcon#about to write, iclass 27, count 0 2006.258.01:13:58.58#ibcon#wrote, iclass 27, count 0 2006.258.01:13:58.58#ibcon#about to read 3, iclass 27, count 0 2006.258.01:13:58.60#ibcon#read 3, iclass 27, count 0 2006.258.01:13:58.60#ibcon#about to read 4, iclass 27, count 0 2006.258.01:13:58.60#ibcon#read 4, iclass 27, count 0 2006.258.01:13:58.60#ibcon#about to read 5, iclass 27, count 0 2006.258.01:13:58.60#ibcon#read 5, iclass 27, count 0 2006.258.01:13:58.60#ibcon#about to read 6, iclass 27, count 0 2006.258.01:13:58.60#ibcon#read 6, iclass 27, count 0 2006.258.01:13:58.60#ibcon#end of sib2, iclass 27, count 0 2006.258.01:13:58.60#ibcon#*mode == 0, iclass 27, count 0 2006.258.01:13:58.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.01:13:58.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.01:13:58.60#ibcon#*before write, iclass 27, count 0 2006.258.01:13:58.60#ibcon#enter sib2, iclass 27, count 0 2006.258.01:13:58.60#ibcon#flushed, iclass 27, count 0 2006.258.01:13:58.60#ibcon#about to write, iclass 27, count 0 2006.258.01:13:58.60#ibcon#wrote, iclass 27, count 0 2006.258.01:13:58.60#ibcon#about to read 3, iclass 27, count 0 2006.258.01:13:58.64#ibcon#read 3, iclass 27, count 0 2006.258.01:13:58.64#ibcon#about to read 4, iclass 27, count 0 2006.258.01:13:58.64#ibcon#read 4, iclass 27, count 0 2006.258.01:13:58.64#ibcon#about to read 5, iclass 27, count 0 2006.258.01:13:58.64#ibcon#read 5, iclass 27, count 0 2006.258.01:13:58.64#ibcon#about to read 6, iclass 27, count 0 2006.258.01:13:58.64#ibcon#read 6, iclass 27, count 0 2006.258.01:13:58.64#ibcon#end of sib2, iclass 27, count 0 2006.258.01:13:58.64#ibcon#*after write, iclass 27, count 0 2006.258.01:13:58.64#ibcon#*before return 0, iclass 27, count 0 2006.258.01:13:58.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:58.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:13:58.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.01:13:58.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.01:13:58.64$vck44/vb=6,4 2006.258.01:13:58.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.01:13:58.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.01:13:58.64#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:58.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:58.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:58.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:58.70#ibcon#enter wrdev, iclass 29, count 2 2006.258.01:13:58.70#ibcon#first serial, iclass 29, count 2 2006.258.01:13:58.70#ibcon#enter sib2, iclass 29, count 2 2006.258.01:13:58.70#ibcon#flushed, iclass 29, count 2 2006.258.01:13:58.70#ibcon#about to write, iclass 29, count 2 2006.258.01:13:58.70#ibcon#wrote, iclass 29, count 2 2006.258.01:13:58.70#ibcon#about to read 3, iclass 29, count 2 2006.258.01:13:58.72#ibcon#read 3, iclass 29, count 2 2006.258.01:13:58.72#ibcon#about to read 4, iclass 29, count 2 2006.258.01:13:58.72#ibcon#read 4, iclass 29, count 2 2006.258.01:13:58.72#ibcon#about to read 5, iclass 29, count 2 2006.258.01:13:58.72#ibcon#read 5, iclass 29, count 2 2006.258.01:13:58.72#ibcon#about to read 6, iclass 29, count 2 2006.258.01:13:58.72#ibcon#read 6, iclass 29, count 2 2006.258.01:13:58.72#ibcon#end of sib2, iclass 29, count 2 2006.258.01:13:58.72#ibcon#*mode == 0, iclass 29, count 2 2006.258.01:13:58.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.01:13:58.72#ibcon#[27=AT06-04\r\n] 2006.258.01:13:58.72#ibcon#*before write, iclass 29, count 2 2006.258.01:13:58.72#ibcon#enter sib2, iclass 29, count 2 2006.258.01:13:58.72#ibcon#flushed, iclass 29, count 2 2006.258.01:13:58.72#ibcon#about to write, iclass 29, count 2 2006.258.01:13:58.72#ibcon#wrote, iclass 29, count 2 2006.258.01:13:58.72#ibcon#about to read 3, iclass 29, count 2 2006.258.01:13:58.75#ibcon#read 3, iclass 29, count 2 2006.258.01:13:58.75#ibcon#about to read 4, iclass 29, count 2 2006.258.01:13:58.75#ibcon#read 4, iclass 29, count 2 2006.258.01:13:58.75#ibcon#about to read 5, iclass 29, count 2 2006.258.01:13:58.75#ibcon#read 5, iclass 29, count 2 2006.258.01:13:58.75#ibcon#about to read 6, iclass 29, count 2 2006.258.01:13:58.75#ibcon#read 6, iclass 29, count 2 2006.258.01:13:58.75#ibcon#end of sib2, iclass 29, count 2 2006.258.01:13:58.75#ibcon#*after write, iclass 29, count 2 2006.258.01:13:58.75#ibcon#*before return 0, iclass 29, count 2 2006.258.01:13:58.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:58.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:13:58.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.01:13:58.75#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:58.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:58.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:58.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:58.87#ibcon#enter wrdev, iclass 29, count 0 2006.258.01:13:58.87#ibcon#first serial, iclass 29, count 0 2006.258.01:13:58.87#ibcon#enter sib2, iclass 29, count 0 2006.258.01:13:58.87#ibcon#flushed, iclass 29, count 0 2006.258.01:13:58.87#ibcon#about to write, iclass 29, count 0 2006.258.01:13:58.87#ibcon#wrote, iclass 29, count 0 2006.258.01:13:58.87#ibcon#about to read 3, iclass 29, count 0 2006.258.01:13:58.89#ibcon#read 3, iclass 29, count 0 2006.258.01:13:58.89#ibcon#about to read 4, iclass 29, count 0 2006.258.01:13:58.89#ibcon#read 4, iclass 29, count 0 2006.258.01:13:58.89#ibcon#about to read 5, iclass 29, count 0 2006.258.01:13:58.89#ibcon#read 5, iclass 29, count 0 2006.258.01:13:58.89#ibcon#about to read 6, iclass 29, count 0 2006.258.01:13:58.89#ibcon#read 6, iclass 29, count 0 2006.258.01:13:58.89#ibcon#end of sib2, iclass 29, count 0 2006.258.01:13:58.89#ibcon#*mode == 0, iclass 29, count 0 2006.258.01:13:58.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.01:13:58.89#ibcon#[27=USB\r\n] 2006.258.01:13:58.89#ibcon#*before write, iclass 29, count 0 2006.258.01:13:58.89#ibcon#enter sib2, iclass 29, count 0 2006.258.01:13:58.89#ibcon#flushed, iclass 29, count 0 2006.258.01:13:58.89#ibcon#about to write, iclass 29, count 0 2006.258.01:13:58.89#ibcon#wrote, iclass 29, count 0 2006.258.01:13:58.89#ibcon#about to read 3, iclass 29, count 0 2006.258.01:13:58.92#ibcon#read 3, iclass 29, count 0 2006.258.01:13:58.92#ibcon#about to read 4, iclass 29, count 0 2006.258.01:13:58.92#ibcon#read 4, iclass 29, count 0 2006.258.01:13:58.92#ibcon#about to read 5, iclass 29, count 0 2006.258.01:13:58.92#ibcon#read 5, iclass 29, count 0 2006.258.01:13:58.92#ibcon#about to read 6, iclass 29, count 0 2006.258.01:13:58.92#ibcon#read 6, iclass 29, count 0 2006.258.01:13:58.92#ibcon#end of sib2, iclass 29, count 0 2006.258.01:13:58.92#ibcon#*after write, iclass 29, count 0 2006.258.01:13:58.92#ibcon#*before return 0, iclass 29, count 0 2006.258.01:13:58.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:58.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:13:58.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.01:13:58.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.01:13:58.92$vck44/vblo=7,734.99 2006.258.01:13:58.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.258.01:13:58.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.258.01:13:58.92#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:58.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:13:58.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:13:58.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:13:58.92#ibcon#enter wrdev, iclass 31, count 0 2006.258.01:13:58.92#ibcon#first serial, iclass 31, count 0 2006.258.01:13:58.92#ibcon#enter sib2, iclass 31, count 0 2006.258.01:13:58.92#ibcon#flushed, iclass 31, count 0 2006.258.01:13:58.92#ibcon#about to write, iclass 31, count 0 2006.258.01:13:58.92#ibcon#wrote, iclass 31, count 0 2006.258.01:13:58.92#ibcon#about to read 3, iclass 31, count 0 2006.258.01:13:58.94#ibcon#read 3, iclass 31, count 0 2006.258.01:13:58.94#ibcon#about to read 4, iclass 31, count 0 2006.258.01:13:58.94#ibcon#read 4, iclass 31, count 0 2006.258.01:13:58.94#ibcon#about to read 5, iclass 31, count 0 2006.258.01:13:58.94#ibcon#read 5, iclass 31, count 0 2006.258.01:13:58.94#ibcon#about to read 6, iclass 31, count 0 2006.258.01:13:58.94#ibcon#read 6, iclass 31, count 0 2006.258.01:13:58.94#ibcon#end of sib2, iclass 31, count 0 2006.258.01:13:58.94#ibcon#*mode == 0, iclass 31, count 0 2006.258.01:13:58.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.01:13:58.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.01:13:58.94#ibcon#*before write, iclass 31, count 0 2006.258.01:13:58.94#ibcon#enter sib2, iclass 31, count 0 2006.258.01:13:58.94#ibcon#flushed, iclass 31, count 0 2006.258.01:13:58.94#ibcon#about to write, iclass 31, count 0 2006.258.01:13:58.94#ibcon#wrote, iclass 31, count 0 2006.258.01:13:58.94#ibcon#about to read 3, iclass 31, count 0 2006.258.01:13:58.98#ibcon#read 3, iclass 31, count 0 2006.258.01:13:58.98#ibcon#about to read 4, iclass 31, count 0 2006.258.01:13:58.98#ibcon#read 4, iclass 31, count 0 2006.258.01:13:58.98#ibcon#about to read 5, iclass 31, count 0 2006.258.01:13:58.98#ibcon#read 5, iclass 31, count 0 2006.258.01:13:58.98#ibcon#about to read 6, iclass 31, count 0 2006.258.01:13:58.98#ibcon#read 6, iclass 31, count 0 2006.258.01:13:58.98#ibcon#end of sib2, iclass 31, count 0 2006.258.01:13:58.98#ibcon#*after write, iclass 31, count 0 2006.258.01:13:58.98#ibcon#*before return 0, iclass 31, count 0 2006.258.01:13:58.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:13:58.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:13:58.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.01:13:58.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.01:13:58.98$vck44/vb=7,4 2006.258.01:13:58.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.01:13:58.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.01:13:58.98#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:58.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:13:59.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:13:59.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:13:59.04#ibcon#enter wrdev, iclass 33, count 2 2006.258.01:13:59.04#ibcon#first serial, iclass 33, count 2 2006.258.01:13:59.04#ibcon#enter sib2, iclass 33, count 2 2006.258.01:13:59.04#ibcon#flushed, iclass 33, count 2 2006.258.01:13:59.04#ibcon#about to write, iclass 33, count 2 2006.258.01:13:59.04#ibcon#wrote, iclass 33, count 2 2006.258.01:13:59.04#ibcon#about to read 3, iclass 33, count 2 2006.258.01:13:59.06#ibcon#read 3, iclass 33, count 2 2006.258.01:13:59.06#ibcon#about to read 4, iclass 33, count 2 2006.258.01:13:59.06#ibcon#read 4, iclass 33, count 2 2006.258.01:13:59.06#ibcon#about to read 5, iclass 33, count 2 2006.258.01:13:59.06#ibcon#read 5, iclass 33, count 2 2006.258.01:13:59.06#ibcon#about to read 6, iclass 33, count 2 2006.258.01:13:59.06#ibcon#read 6, iclass 33, count 2 2006.258.01:13:59.06#ibcon#end of sib2, iclass 33, count 2 2006.258.01:13:59.06#ibcon#*mode == 0, iclass 33, count 2 2006.258.01:13:59.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.01:13:59.06#ibcon#[27=AT07-04\r\n] 2006.258.01:13:59.06#ibcon#*before write, iclass 33, count 2 2006.258.01:13:59.06#ibcon#enter sib2, iclass 33, count 2 2006.258.01:13:59.06#ibcon#flushed, iclass 33, count 2 2006.258.01:13:59.06#ibcon#about to write, iclass 33, count 2 2006.258.01:13:59.06#ibcon#wrote, iclass 33, count 2 2006.258.01:13:59.06#ibcon#about to read 3, iclass 33, count 2 2006.258.01:13:59.09#ibcon#read 3, iclass 33, count 2 2006.258.01:13:59.09#ibcon#about to read 4, iclass 33, count 2 2006.258.01:13:59.09#ibcon#read 4, iclass 33, count 2 2006.258.01:13:59.09#ibcon#about to read 5, iclass 33, count 2 2006.258.01:13:59.09#ibcon#read 5, iclass 33, count 2 2006.258.01:13:59.09#ibcon#about to read 6, iclass 33, count 2 2006.258.01:13:59.09#ibcon#read 6, iclass 33, count 2 2006.258.01:13:59.09#ibcon#end of sib2, iclass 33, count 2 2006.258.01:13:59.09#ibcon#*after write, iclass 33, count 2 2006.258.01:13:59.09#ibcon#*before return 0, iclass 33, count 2 2006.258.01:13:59.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:13:59.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:13:59.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.01:13:59.09#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:59.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:13:59.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:13:59.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:13:59.21#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:13:59.21#ibcon#first serial, iclass 33, count 0 2006.258.01:13:59.21#ibcon#enter sib2, iclass 33, count 0 2006.258.01:13:59.21#ibcon#flushed, iclass 33, count 0 2006.258.01:13:59.21#ibcon#about to write, iclass 33, count 0 2006.258.01:13:59.21#ibcon#wrote, iclass 33, count 0 2006.258.01:13:59.21#ibcon#about to read 3, iclass 33, count 0 2006.258.01:13:59.23#ibcon#read 3, iclass 33, count 0 2006.258.01:13:59.23#ibcon#about to read 4, iclass 33, count 0 2006.258.01:13:59.23#ibcon#read 4, iclass 33, count 0 2006.258.01:13:59.23#ibcon#about to read 5, iclass 33, count 0 2006.258.01:13:59.23#ibcon#read 5, iclass 33, count 0 2006.258.01:13:59.23#ibcon#about to read 6, iclass 33, count 0 2006.258.01:13:59.23#ibcon#read 6, iclass 33, count 0 2006.258.01:13:59.23#ibcon#end of sib2, iclass 33, count 0 2006.258.01:13:59.23#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:13:59.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:13:59.23#ibcon#[27=USB\r\n] 2006.258.01:13:59.23#ibcon#*before write, iclass 33, count 0 2006.258.01:13:59.23#ibcon#enter sib2, iclass 33, count 0 2006.258.01:13:59.23#ibcon#flushed, iclass 33, count 0 2006.258.01:13:59.23#ibcon#about to write, iclass 33, count 0 2006.258.01:13:59.23#ibcon#wrote, iclass 33, count 0 2006.258.01:13:59.23#ibcon#about to read 3, iclass 33, count 0 2006.258.01:13:59.26#ibcon#read 3, iclass 33, count 0 2006.258.01:13:59.26#ibcon#about to read 4, iclass 33, count 0 2006.258.01:13:59.26#ibcon#read 4, iclass 33, count 0 2006.258.01:13:59.26#ibcon#about to read 5, iclass 33, count 0 2006.258.01:13:59.26#ibcon#read 5, iclass 33, count 0 2006.258.01:13:59.26#ibcon#about to read 6, iclass 33, count 0 2006.258.01:13:59.26#ibcon#read 6, iclass 33, count 0 2006.258.01:13:59.26#ibcon#end of sib2, iclass 33, count 0 2006.258.01:13:59.26#ibcon#*after write, iclass 33, count 0 2006.258.01:13:59.26#ibcon#*before return 0, iclass 33, count 0 2006.258.01:13:59.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:13:59.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:13:59.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:13:59.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:13:59.26$vck44/vblo=8,744.99 2006.258.01:13:59.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.01:13:59.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.01:13:59.26#ibcon#ireg 17 cls_cnt 0 2006.258.01:13:59.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:13:59.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:13:59.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:13:59.26#ibcon#enter wrdev, iclass 35, count 0 2006.258.01:13:59.26#ibcon#first serial, iclass 35, count 0 2006.258.01:13:59.26#ibcon#enter sib2, iclass 35, count 0 2006.258.01:13:59.26#ibcon#flushed, iclass 35, count 0 2006.258.01:13:59.26#ibcon#about to write, iclass 35, count 0 2006.258.01:13:59.26#ibcon#wrote, iclass 35, count 0 2006.258.01:13:59.26#ibcon#about to read 3, iclass 35, count 0 2006.258.01:13:59.28#ibcon#read 3, iclass 35, count 0 2006.258.01:13:59.28#ibcon#about to read 4, iclass 35, count 0 2006.258.01:13:59.28#ibcon#read 4, iclass 35, count 0 2006.258.01:13:59.28#ibcon#about to read 5, iclass 35, count 0 2006.258.01:13:59.28#ibcon#read 5, iclass 35, count 0 2006.258.01:13:59.28#ibcon#about to read 6, iclass 35, count 0 2006.258.01:13:59.28#ibcon#read 6, iclass 35, count 0 2006.258.01:13:59.28#ibcon#end of sib2, iclass 35, count 0 2006.258.01:13:59.28#ibcon#*mode == 0, iclass 35, count 0 2006.258.01:13:59.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.01:13:59.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.01:13:59.28#ibcon#*before write, iclass 35, count 0 2006.258.01:13:59.28#ibcon#enter sib2, iclass 35, count 0 2006.258.01:13:59.28#ibcon#flushed, iclass 35, count 0 2006.258.01:13:59.28#ibcon#about to write, iclass 35, count 0 2006.258.01:13:59.28#ibcon#wrote, iclass 35, count 0 2006.258.01:13:59.28#ibcon#about to read 3, iclass 35, count 0 2006.258.01:13:59.32#ibcon#read 3, iclass 35, count 0 2006.258.01:13:59.32#ibcon#about to read 4, iclass 35, count 0 2006.258.01:13:59.32#ibcon#read 4, iclass 35, count 0 2006.258.01:13:59.32#ibcon#about to read 5, iclass 35, count 0 2006.258.01:13:59.32#ibcon#read 5, iclass 35, count 0 2006.258.01:13:59.32#ibcon#about to read 6, iclass 35, count 0 2006.258.01:13:59.32#ibcon#read 6, iclass 35, count 0 2006.258.01:13:59.32#ibcon#end of sib2, iclass 35, count 0 2006.258.01:13:59.32#ibcon#*after write, iclass 35, count 0 2006.258.01:13:59.32#ibcon#*before return 0, iclass 35, count 0 2006.258.01:13:59.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:13:59.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:13:59.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.01:13:59.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.01:13:59.32$vck44/vb=8,4 2006.258.01:13:59.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.01:13:59.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.01:13:59.32#ibcon#ireg 11 cls_cnt 2 2006.258.01:13:59.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:59.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:59.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:59.38#ibcon#enter wrdev, iclass 37, count 2 2006.258.01:13:59.38#ibcon#first serial, iclass 37, count 2 2006.258.01:13:59.38#ibcon#enter sib2, iclass 37, count 2 2006.258.01:13:59.38#ibcon#flushed, iclass 37, count 2 2006.258.01:13:59.38#ibcon#about to write, iclass 37, count 2 2006.258.01:13:59.38#ibcon#wrote, iclass 37, count 2 2006.258.01:13:59.38#ibcon#about to read 3, iclass 37, count 2 2006.258.01:13:59.40#ibcon#read 3, iclass 37, count 2 2006.258.01:13:59.40#ibcon#about to read 4, iclass 37, count 2 2006.258.01:13:59.40#ibcon#read 4, iclass 37, count 2 2006.258.01:13:59.40#ibcon#about to read 5, iclass 37, count 2 2006.258.01:13:59.40#ibcon#read 5, iclass 37, count 2 2006.258.01:13:59.40#ibcon#about to read 6, iclass 37, count 2 2006.258.01:13:59.40#ibcon#read 6, iclass 37, count 2 2006.258.01:13:59.40#ibcon#end of sib2, iclass 37, count 2 2006.258.01:13:59.40#ibcon#*mode == 0, iclass 37, count 2 2006.258.01:13:59.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.01:13:59.40#ibcon#[27=AT08-04\r\n] 2006.258.01:13:59.40#ibcon#*before write, iclass 37, count 2 2006.258.01:13:59.40#ibcon#enter sib2, iclass 37, count 2 2006.258.01:13:59.40#ibcon#flushed, iclass 37, count 2 2006.258.01:13:59.40#ibcon#about to write, iclass 37, count 2 2006.258.01:13:59.40#ibcon#wrote, iclass 37, count 2 2006.258.01:13:59.40#ibcon#about to read 3, iclass 37, count 2 2006.258.01:13:59.43#ibcon#read 3, iclass 37, count 2 2006.258.01:13:59.43#ibcon#about to read 4, iclass 37, count 2 2006.258.01:13:59.43#ibcon#read 4, iclass 37, count 2 2006.258.01:13:59.43#ibcon#about to read 5, iclass 37, count 2 2006.258.01:13:59.43#ibcon#read 5, iclass 37, count 2 2006.258.01:13:59.43#ibcon#about to read 6, iclass 37, count 2 2006.258.01:13:59.43#ibcon#read 6, iclass 37, count 2 2006.258.01:13:59.43#ibcon#end of sib2, iclass 37, count 2 2006.258.01:13:59.43#ibcon#*after write, iclass 37, count 2 2006.258.01:13:59.43#ibcon#*before return 0, iclass 37, count 2 2006.258.01:13:59.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:59.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:13:59.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.01:13:59.43#ibcon#ireg 7 cls_cnt 0 2006.258.01:13:59.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:59.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:59.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:59.55#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:13:59.55#ibcon#first serial, iclass 37, count 0 2006.258.01:13:59.55#ibcon#enter sib2, iclass 37, count 0 2006.258.01:13:59.55#ibcon#flushed, iclass 37, count 0 2006.258.01:13:59.55#ibcon#about to write, iclass 37, count 0 2006.258.01:13:59.55#ibcon#wrote, iclass 37, count 0 2006.258.01:13:59.55#ibcon#about to read 3, iclass 37, count 0 2006.258.01:13:59.57#ibcon#read 3, iclass 37, count 0 2006.258.01:13:59.57#ibcon#about to read 4, iclass 37, count 0 2006.258.01:13:59.57#ibcon#read 4, iclass 37, count 0 2006.258.01:13:59.57#ibcon#about to read 5, iclass 37, count 0 2006.258.01:13:59.57#ibcon#read 5, iclass 37, count 0 2006.258.01:13:59.57#ibcon#about to read 6, iclass 37, count 0 2006.258.01:13:59.57#ibcon#read 6, iclass 37, count 0 2006.258.01:13:59.57#ibcon#end of sib2, iclass 37, count 0 2006.258.01:13:59.57#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:13:59.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:13:59.57#ibcon#[27=USB\r\n] 2006.258.01:13:59.57#ibcon#*before write, iclass 37, count 0 2006.258.01:13:59.57#ibcon#enter sib2, iclass 37, count 0 2006.258.01:13:59.57#ibcon#flushed, iclass 37, count 0 2006.258.01:13:59.57#ibcon#about to write, iclass 37, count 0 2006.258.01:13:59.57#ibcon#wrote, iclass 37, count 0 2006.258.01:13:59.57#ibcon#about to read 3, iclass 37, count 0 2006.258.01:13:59.60#ibcon#read 3, iclass 37, count 0 2006.258.01:13:59.60#ibcon#about to read 4, iclass 37, count 0 2006.258.01:13:59.60#ibcon#read 4, iclass 37, count 0 2006.258.01:13:59.60#ibcon#about to read 5, iclass 37, count 0 2006.258.01:13:59.60#ibcon#read 5, iclass 37, count 0 2006.258.01:13:59.60#ibcon#about to read 6, iclass 37, count 0 2006.258.01:13:59.60#ibcon#read 6, iclass 37, count 0 2006.258.01:13:59.60#ibcon#end of sib2, iclass 37, count 0 2006.258.01:13:59.60#ibcon#*after write, iclass 37, count 0 2006.258.01:13:59.60#ibcon#*before return 0, iclass 37, count 0 2006.258.01:13:59.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:59.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:13:59.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:13:59.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:13:59.60$vck44/vabw=wide 2006.258.01:13:59.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.01:13:59.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.01:13:59.60#ibcon#ireg 8 cls_cnt 0 2006.258.01:13:59.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:59.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:59.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:59.60#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:13:59.60#ibcon#first serial, iclass 39, count 0 2006.258.01:13:59.60#ibcon#enter sib2, iclass 39, count 0 2006.258.01:13:59.60#ibcon#flushed, iclass 39, count 0 2006.258.01:13:59.60#ibcon#about to write, iclass 39, count 0 2006.258.01:13:59.60#ibcon#wrote, iclass 39, count 0 2006.258.01:13:59.60#ibcon#about to read 3, iclass 39, count 0 2006.258.01:13:59.62#ibcon#read 3, iclass 39, count 0 2006.258.01:13:59.62#ibcon#about to read 4, iclass 39, count 0 2006.258.01:13:59.62#ibcon#read 4, iclass 39, count 0 2006.258.01:13:59.62#ibcon#about to read 5, iclass 39, count 0 2006.258.01:13:59.62#ibcon#read 5, iclass 39, count 0 2006.258.01:13:59.62#ibcon#about to read 6, iclass 39, count 0 2006.258.01:13:59.62#ibcon#read 6, iclass 39, count 0 2006.258.01:13:59.62#ibcon#end of sib2, iclass 39, count 0 2006.258.01:13:59.62#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:13:59.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:13:59.62#ibcon#[25=BW32\r\n] 2006.258.01:13:59.62#ibcon#*before write, iclass 39, count 0 2006.258.01:13:59.62#ibcon#enter sib2, iclass 39, count 0 2006.258.01:13:59.62#ibcon#flushed, iclass 39, count 0 2006.258.01:13:59.62#ibcon#about to write, iclass 39, count 0 2006.258.01:13:59.62#ibcon#wrote, iclass 39, count 0 2006.258.01:13:59.62#ibcon#about to read 3, iclass 39, count 0 2006.258.01:13:59.65#ibcon#read 3, iclass 39, count 0 2006.258.01:13:59.65#ibcon#about to read 4, iclass 39, count 0 2006.258.01:13:59.65#ibcon#read 4, iclass 39, count 0 2006.258.01:13:59.65#ibcon#about to read 5, iclass 39, count 0 2006.258.01:13:59.65#ibcon#read 5, iclass 39, count 0 2006.258.01:13:59.65#ibcon#about to read 6, iclass 39, count 0 2006.258.01:13:59.65#ibcon#read 6, iclass 39, count 0 2006.258.01:13:59.65#ibcon#end of sib2, iclass 39, count 0 2006.258.01:13:59.65#ibcon#*after write, iclass 39, count 0 2006.258.01:13:59.65#ibcon#*before return 0, iclass 39, count 0 2006.258.01:13:59.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:59.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:13:59.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:13:59.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:13:59.65$vck44/vbbw=wide 2006.258.01:13:59.65#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.01:13:59.65#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.01:13:59.65#ibcon#ireg 8 cls_cnt 0 2006.258.01:13:59.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:13:59.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:13:59.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:13:59.72#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:13:59.72#ibcon#first serial, iclass 3, count 0 2006.258.01:13:59.72#ibcon#enter sib2, iclass 3, count 0 2006.258.01:13:59.72#ibcon#flushed, iclass 3, count 0 2006.258.01:13:59.72#ibcon#about to write, iclass 3, count 0 2006.258.01:13:59.72#ibcon#wrote, iclass 3, count 0 2006.258.01:13:59.72#ibcon#about to read 3, iclass 3, count 0 2006.258.01:13:59.74#ibcon#read 3, iclass 3, count 0 2006.258.01:13:59.74#ibcon#about to read 4, iclass 3, count 0 2006.258.01:13:59.74#ibcon#read 4, iclass 3, count 0 2006.258.01:13:59.74#ibcon#about to read 5, iclass 3, count 0 2006.258.01:13:59.74#ibcon#read 5, iclass 3, count 0 2006.258.01:13:59.74#ibcon#about to read 6, iclass 3, count 0 2006.258.01:13:59.74#ibcon#read 6, iclass 3, count 0 2006.258.01:13:59.74#ibcon#end of sib2, iclass 3, count 0 2006.258.01:13:59.74#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:13:59.74#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:13:59.74#ibcon#[27=BW32\r\n] 2006.258.01:13:59.74#ibcon#*before write, iclass 3, count 0 2006.258.01:13:59.74#ibcon#enter sib2, iclass 3, count 0 2006.258.01:13:59.74#ibcon#flushed, iclass 3, count 0 2006.258.01:13:59.74#ibcon#about to write, iclass 3, count 0 2006.258.01:13:59.74#ibcon#wrote, iclass 3, count 0 2006.258.01:13:59.74#ibcon#about to read 3, iclass 3, count 0 2006.258.01:13:59.77#ibcon#read 3, iclass 3, count 0 2006.258.01:13:59.77#ibcon#about to read 4, iclass 3, count 0 2006.258.01:13:59.77#ibcon#read 4, iclass 3, count 0 2006.258.01:13:59.77#ibcon#about to read 5, iclass 3, count 0 2006.258.01:13:59.77#ibcon#read 5, iclass 3, count 0 2006.258.01:13:59.77#ibcon#about to read 6, iclass 3, count 0 2006.258.01:13:59.77#ibcon#read 6, iclass 3, count 0 2006.258.01:13:59.77#ibcon#end of sib2, iclass 3, count 0 2006.258.01:13:59.77#ibcon#*after write, iclass 3, count 0 2006.258.01:13:59.77#ibcon#*before return 0, iclass 3, count 0 2006.258.01:13:59.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:13:59.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:13:59.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:13:59.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:13:59.77$setupk4/ifdk4 2006.258.01:13:59.77$ifdk4/lo= 2006.258.01:13:59.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.01:13:59.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.01:13:59.77$ifdk4/patch= 2006.258.01:13:59.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.01:13:59.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.01:13:59.77$setupk4/!*+20s 2006.258.01:14:06.40#abcon#<5=/03 2.8 5.3 22.70 741016.0\r\n> 2006.258.01:14:06.42#abcon#{5=INTERFACE CLEAR} 2006.258.01:14:06.48#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:14:11.14#trakl#Source acquired 2006.258.01:14:11.14#flagr#flagr/antenna,acquired 2006.258.01:14:14.21$setupk4/"tpicd 2006.258.01:14:14.21$setupk4/echo=off 2006.258.01:14:14.21$setupk4/xlog=off 2006.258.01:14:14.21:!2006.258.01:15:50 2006.258.01:15:50.02:preob 2006.258.01:15:51.14/onsource/TRACKING 2006.258.01:15:51.14:!2006.258.01:16:00 2006.258.01:16:00.02:"tape 2006.258.01:16:00.02:"st=record 2006.258.01:16:00.02:data_valid=on 2006.258.01:16:00.02:midob 2006.258.01:16:01.14/onsource/TRACKING 2006.258.01:16:01.14/wx/22.82,1016.1,73 2006.258.01:16:01.31/cable/+6.4765E-03 2006.258.01:16:02.40/va/01,08,usb,yes,31,34 2006.258.01:16:02.40/va/02,07,usb,yes,34,34 2006.258.01:16:02.40/va/03,08,usb,yes,30,32 2006.258.01:16:02.40/va/04,07,usb,yes,35,37 2006.258.01:16:02.40/va/05,04,usb,yes,31,32 2006.258.01:16:02.40/va/06,04,usb,yes,35,34 2006.258.01:16:02.40/va/07,04,usb,yes,36,36 2006.258.01:16:02.40/va/08,04,usb,yes,30,37 2006.258.01:16:02.63/valo/01,524.99,yes,locked 2006.258.01:16:02.63/valo/02,534.99,yes,locked 2006.258.01:16:02.63/valo/03,564.99,yes,locked 2006.258.01:16:02.63/valo/04,624.99,yes,locked 2006.258.01:16:02.63/valo/05,734.99,yes,locked 2006.258.01:16:02.63/valo/06,814.99,yes,locked 2006.258.01:16:02.63/valo/07,864.99,yes,locked 2006.258.01:16:02.63/valo/08,884.99,yes,locked 2006.258.01:16:03.72/vb/01,04,usb,yes,31,29 2006.258.01:16:03.72/vb/02,05,usb,yes,30,29 2006.258.01:16:03.72/vb/03,04,usb,yes,30,34 2006.258.01:16:03.72/vb/04,05,usb,yes,31,30 2006.258.01:16:03.72/vb/05,04,usb,yes,27,30 2006.258.01:16:03.72/vb/06,04,usb,yes,32,28 2006.258.01:16:03.72/vb/07,04,usb,yes,31,31 2006.258.01:16:03.72/vb/08,04,usb,yes,29,32 2006.258.01:16:03.96/vblo/01,629.99,yes,locked 2006.258.01:16:03.96/vblo/02,634.99,yes,locked 2006.258.01:16:03.96/vblo/03,649.99,yes,locked 2006.258.01:16:03.96/vblo/04,679.99,yes,locked 2006.258.01:16:03.96/vblo/05,709.99,yes,locked 2006.258.01:16:03.96/vblo/06,719.99,yes,locked 2006.258.01:16:03.96/vblo/07,734.99,yes,locked 2006.258.01:16:03.96/vblo/08,744.99,yes,locked 2006.258.01:16:04.11/vabw/8 2006.258.01:16:04.26/vbbw/8 2006.258.01:16:04.35/xfe/off,on,15.0 2006.258.01:16:04.72/ifatt/23,28,28,28 2006.258.01:16:05.07/fmout-gps/S +4.52E-07 2006.258.01:16:05.12:!2006.258.01:17:00 2006.258.01:17:00.02:data_valid=off 2006.258.01:17:00.02:"et 2006.258.01:17:00.02:!+3s 2006.258.01:17:03.03:"tape 2006.258.01:17:03.04:postob 2006.258.01:17:03.20/cable/+6.4771E-03 2006.258.01:17:03.21/wx/22.90,1016.1,72 2006.258.01:17:03.26/fmout-gps/S +4.53E-07 2006.258.01:17:03.27:scan_name=258-0119,jd0609,160 2006.258.01:17:03.27:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.258.01:17:04.15#flagr#flagr/antenna,new-source 2006.258.01:17:04.15:checkk5 2006.258.01:17:04.55/chk_autoobs//k5ts1/ autoobs is running! 2006.258.01:17:04.96/chk_autoobs//k5ts2/ autoobs is running! 2006.258.01:17:05.37/chk_autoobs//k5ts3/ autoobs is running! 2006.258.01:17:05.77/chk_autoobs//k5ts4/ autoobs is running! 2006.258.01:17:06.16/chk_obsdata//k5ts1/T2580116??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.258.01:17:06.55/chk_obsdata//k5ts2/T2580116??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.258.01:17:06.96/chk_obsdata//k5ts3/T2580116??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.258.01:17:07.37/chk_obsdata//k5ts4/T2580116??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.258.01:17:08.10/k5log//k5ts1_log_newline 2006.258.01:17:08.82/k5log//k5ts2_log_newline 2006.258.01:17:09.53/k5log//k5ts3_log_newline 2006.258.01:17:10.24/k5log//k5ts4_log_newline 2006.258.01:17:10.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:17:10.26:setupk4=1 2006.258.01:17:10.26$setupk4/echo=on 2006.258.01:17:10.26$setupk4/pcalon 2006.258.01:17:10.26$pcalon/"no phase cal control is implemented here 2006.258.01:17:10.26$setupk4/"tpicd=stop 2006.258.01:17:10.26$setupk4/"rec=synch_on 2006.258.01:17:10.26$setupk4/"rec_mode=128 2006.258.01:17:10.26$setupk4/!* 2006.258.01:17:10.26$setupk4/recpk4 2006.258.01:17:10.26$recpk4/recpatch= 2006.258.01:17:10.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.01:17:10.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.01:17:10.27$setupk4/vck44 2006.258.01:17:10.27$vck44/valo=1,524.99 2006.258.01:17:10.27#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.01:17:10.27#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.01:17:10.27#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:10.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:10.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:10.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:10.27#ibcon#enter wrdev, iclass 14, count 0 2006.258.01:17:10.27#ibcon#first serial, iclass 14, count 0 2006.258.01:17:10.27#ibcon#enter sib2, iclass 14, count 0 2006.258.01:17:10.27#ibcon#flushed, iclass 14, count 0 2006.258.01:17:10.27#ibcon#about to write, iclass 14, count 0 2006.258.01:17:10.27#ibcon#wrote, iclass 14, count 0 2006.258.01:17:10.27#ibcon#about to read 3, iclass 14, count 0 2006.258.01:17:10.28#ibcon#read 3, iclass 14, count 0 2006.258.01:17:10.28#ibcon#about to read 4, iclass 14, count 0 2006.258.01:17:10.28#ibcon#read 4, iclass 14, count 0 2006.258.01:17:10.28#ibcon#about to read 5, iclass 14, count 0 2006.258.01:17:10.28#ibcon#read 5, iclass 14, count 0 2006.258.01:17:10.28#ibcon#about to read 6, iclass 14, count 0 2006.258.01:17:10.28#ibcon#read 6, iclass 14, count 0 2006.258.01:17:10.28#ibcon#end of sib2, iclass 14, count 0 2006.258.01:17:10.28#ibcon#*mode == 0, iclass 14, count 0 2006.258.01:17:10.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.01:17:10.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.01:17:10.28#ibcon#*before write, iclass 14, count 0 2006.258.01:17:10.28#ibcon#enter sib2, iclass 14, count 0 2006.258.01:17:10.28#ibcon#flushed, iclass 14, count 0 2006.258.01:17:10.28#ibcon#about to write, iclass 14, count 0 2006.258.01:17:10.28#ibcon#wrote, iclass 14, count 0 2006.258.01:17:10.28#ibcon#about to read 3, iclass 14, count 0 2006.258.01:17:10.33#ibcon#read 3, iclass 14, count 0 2006.258.01:17:10.33#ibcon#about to read 4, iclass 14, count 0 2006.258.01:17:10.33#ibcon#read 4, iclass 14, count 0 2006.258.01:17:10.33#ibcon#about to read 5, iclass 14, count 0 2006.258.01:17:10.33#ibcon#read 5, iclass 14, count 0 2006.258.01:17:10.33#ibcon#about to read 6, iclass 14, count 0 2006.258.01:17:10.33#ibcon#read 6, iclass 14, count 0 2006.258.01:17:10.33#ibcon#end of sib2, iclass 14, count 0 2006.258.01:17:10.33#ibcon#*after write, iclass 14, count 0 2006.258.01:17:10.33#ibcon#*before return 0, iclass 14, count 0 2006.258.01:17:10.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:10.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:10.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.01:17:10.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.01:17:10.33$vck44/va=1,8 2006.258.01:17:10.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.258.01:17:10.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.258.01:17:10.33#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:10.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:10.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:10.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:10.34#ibcon#enter wrdev, iclass 16, count 2 2006.258.01:17:10.34#ibcon#first serial, iclass 16, count 2 2006.258.01:17:10.34#ibcon#enter sib2, iclass 16, count 2 2006.258.01:17:10.34#ibcon#flushed, iclass 16, count 2 2006.258.01:17:10.34#ibcon#about to write, iclass 16, count 2 2006.258.01:17:10.34#ibcon#wrote, iclass 16, count 2 2006.258.01:17:10.34#ibcon#about to read 3, iclass 16, count 2 2006.258.01:17:10.35#ibcon#read 3, iclass 16, count 2 2006.258.01:17:10.35#ibcon#about to read 4, iclass 16, count 2 2006.258.01:17:10.35#ibcon#read 4, iclass 16, count 2 2006.258.01:17:10.35#ibcon#about to read 5, iclass 16, count 2 2006.258.01:17:10.35#ibcon#read 5, iclass 16, count 2 2006.258.01:17:10.35#ibcon#about to read 6, iclass 16, count 2 2006.258.01:17:10.35#ibcon#read 6, iclass 16, count 2 2006.258.01:17:10.35#ibcon#end of sib2, iclass 16, count 2 2006.258.01:17:10.35#ibcon#*mode == 0, iclass 16, count 2 2006.258.01:17:10.35#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.258.01:17:10.35#ibcon#[25=AT01-08\r\n] 2006.258.01:17:10.35#ibcon#*before write, iclass 16, count 2 2006.258.01:17:10.35#ibcon#enter sib2, iclass 16, count 2 2006.258.01:17:10.35#ibcon#flushed, iclass 16, count 2 2006.258.01:17:10.35#ibcon#about to write, iclass 16, count 2 2006.258.01:17:10.35#ibcon#wrote, iclass 16, count 2 2006.258.01:17:10.35#ibcon#about to read 3, iclass 16, count 2 2006.258.01:17:10.38#ibcon#read 3, iclass 16, count 2 2006.258.01:17:10.38#ibcon#about to read 4, iclass 16, count 2 2006.258.01:17:10.38#ibcon#read 4, iclass 16, count 2 2006.258.01:17:10.38#ibcon#about to read 5, iclass 16, count 2 2006.258.01:17:10.38#ibcon#read 5, iclass 16, count 2 2006.258.01:17:10.38#ibcon#about to read 6, iclass 16, count 2 2006.258.01:17:10.38#ibcon#read 6, iclass 16, count 2 2006.258.01:17:10.38#ibcon#end of sib2, iclass 16, count 2 2006.258.01:17:10.38#ibcon#*after write, iclass 16, count 2 2006.258.01:17:10.38#ibcon#*before return 0, iclass 16, count 2 2006.258.01:17:10.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:10.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:10.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.258.01:17:10.38#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:10.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:10.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:10.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:10.50#ibcon#enter wrdev, iclass 16, count 0 2006.258.01:17:10.50#ibcon#first serial, iclass 16, count 0 2006.258.01:17:10.50#ibcon#enter sib2, iclass 16, count 0 2006.258.01:17:10.50#ibcon#flushed, iclass 16, count 0 2006.258.01:17:10.50#ibcon#about to write, iclass 16, count 0 2006.258.01:17:10.50#ibcon#wrote, iclass 16, count 0 2006.258.01:17:10.50#ibcon#about to read 3, iclass 16, count 0 2006.258.01:17:10.52#ibcon#read 3, iclass 16, count 0 2006.258.01:17:10.52#ibcon#about to read 4, iclass 16, count 0 2006.258.01:17:10.52#ibcon#read 4, iclass 16, count 0 2006.258.01:17:10.52#ibcon#about to read 5, iclass 16, count 0 2006.258.01:17:10.52#ibcon#read 5, iclass 16, count 0 2006.258.01:17:10.52#ibcon#about to read 6, iclass 16, count 0 2006.258.01:17:10.52#ibcon#read 6, iclass 16, count 0 2006.258.01:17:10.52#ibcon#end of sib2, iclass 16, count 0 2006.258.01:17:10.52#ibcon#*mode == 0, iclass 16, count 0 2006.258.01:17:10.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.01:17:10.52#ibcon#[25=USB\r\n] 2006.258.01:17:10.52#ibcon#*before write, iclass 16, count 0 2006.258.01:17:10.52#ibcon#enter sib2, iclass 16, count 0 2006.258.01:17:10.52#ibcon#flushed, iclass 16, count 0 2006.258.01:17:10.52#ibcon#about to write, iclass 16, count 0 2006.258.01:17:10.52#ibcon#wrote, iclass 16, count 0 2006.258.01:17:10.52#ibcon#about to read 3, iclass 16, count 0 2006.258.01:17:10.55#ibcon#read 3, iclass 16, count 0 2006.258.01:17:10.55#ibcon#about to read 4, iclass 16, count 0 2006.258.01:17:10.55#ibcon#read 4, iclass 16, count 0 2006.258.01:17:10.55#ibcon#about to read 5, iclass 16, count 0 2006.258.01:17:10.55#ibcon#read 5, iclass 16, count 0 2006.258.01:17:10.55#ibcon#about to read 6, iclass 16, count 0 2006.258.01:17:10.55#ibcon#read 6, iclass 16, count 0 2006.258.01:17:10.55#ibcon#end of sib2, iclass 16, count 0 2006.258.01:17:10.55#ibcon#*after write, iclass 16, count 0 2006.258.01:17:10.55#ibcon#*before return 0, iclass 16, count 0 2006.258.01:17:10.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:10.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:10.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.01:17:10.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.01:17:10.55$vck44/valo=2,534.99 2006.258.01:17:10.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.01:17:10.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.01:17:10.55#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:10.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:10.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:10.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:10.55#ibcon#enter wrdev, iclass 18, count 0 2006.258.01:17:10.56#ibcon#first serial, iclass 18, count 0 2006.258.01:17:10.56#ibcon#enter sib2, iclass 18, count 0 2006.258.01:17:10.56#ibcon#flushed, iclass 18, count 0 2006.258.01:17:10.56#ibcon#about to write, iclass 18, count 0 2006.258.01:17:10.56#ibcon#wrote, iclass 18, count 0 2006.258.01:17:10.56#ibcon#about to read 3, iclass 18, count 0 2006.258.01:17:10.57#ibcon#read 3, iclass 18, count 0 2006.258.01:17:10.57#ibcon#about to read 4, iclass 18, count 0 2006.258.01:17:10.57#ibcon#read 4, iclass 18, count 0 2006.258.01:17:10.57#ibcon#about to read 5, iclass 18, count 0 2006.258.01:17:10.57#ibcon#read 5, iclass 18, count 0 2006.258.01:17:10.57#ibcon#about to read 6, iclass 18, count 0 2006.258.01:17:10.57#ibcon#read 6, iclass 18, count 0 2006.258.01:17:10.57#ibcon#end of sib2, iclass 18, count 0 2006.258.01:17:10.57#ibcon#*mode == 0, iclass 18, count 0 2006.258.01:17:10.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.01:17:10.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.01:17:10.57#ibcon#*before write, iclass 18, count 0 2006.258.01:17:10.57#ibcon#enter sib2, iclass 18, count 0 2006.258.01:17:10.57#ibcon#flushed, iclass 18, count 0 2006.258.01:17:10.57#ibcon#about to write, iclass 18, count 0 2006.258.01:17:10.57#ibcon#wrote, iclass 18, count 0 2006.258.01:17:10.57#ibcon#about to read 3, iclass 18, count 0 2006.258.01:17:10.61#ibcon#read 3, iclass 18, count 0 2006.258.01:17:10.61#ibcon#about to read 4, iclass 18, count 0 2006.258.01:17:10.61#ibcon#read 4, iclass 18, count 0 2006.258.01:17:10.61#ibcon#about to read 5, iclass 18, count 0 2006.258.01:17:10.61#ibcon#read 5, iclass 18, count 0 2006.258.01:17:10.61#ibcon#about to read 6, iclass 18, count 0 2006.258.01:17:10.61#ibcon#read 6, iclass 18, count 0 2006.258.01:17:10.61#ibcon#end of sib2, iclass 18, count 0 2006.258.01:17:10.61#ibcon#*after write, iclass 18, count 0 2006.258.01:17:10.61#ibcon#*before return 0, iclass 18, count 0 2006.258.01:17:10.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:10.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:10.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.01:17:10.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.01:17:10.61$vck44/va=2,7 2006.258.01:17:10.61#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.01:17:10.61#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.01:17:10.61#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:10.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:10.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:10.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:10.67#ibcon#enter wrdev, iclass 20, count 2 2006.258.01:17:10.67#ibcon#first serial, iclass 20, count 2 2006.258.01:17:10.67#ibcon#enter sib2, iclass 20, count 2 2006.258.01:17:10.67#ibcon#flushed, iclass 20, count 2 2006.258.01:17:10.67#ibcon#about to write, iclass 20, count 2 2006.258.01:17:10.67#ibcon#wrote, iclass 20, count 2 2006.258.01:17:10.67#ibcon#about to read 3, iclass 20, count 2 2006.258.01:17:10.69#ibcon#read 3, iclass 20, count 2 2006.258.01:17:10.69#ibcon#about to read 4, iclass 20, count 2 2006.258.01:17:10.69#ibcon#read 4, iclass 20, count 2 2006.258.01:17:10.69#ibcon#about to read 5, iclass 20, count 2 2006.258.01:17:10.69#ibcon#read 5, iclass 20, count 2 2006.258.01:17:10.69#ibcon#about to read 6, iclass 20, count 2 2006.258.01:17:10.69#ibcon#read 6, iclass 20, count 2 2006.258.01:17:10.69#ibcon#end of sib2, iclass 20, count 2 2006.258.01:17:10.69#ibcon#*mode == 0, iclass 20, count 2 2006.258.01:17:10.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.01:17:10.69#ibcon#[25=AT02-07\r\n] 2006.258.01:17:10.69#ibcon#*before write, iclass 20, count 2 2006.258.01:17:10.69#ibcon#enter sib2, iclass 20, count 2 2006.258.01:17:10.69#ibcon#flushed, iclass 20, count 2 2006.258.01:17:10.69#ibcon#about to write, iclass 20, count 2 2006.258.01:17:10.69#ibcon#wrote, iclass 20, count 2 2006.258.01:17:10.69#ibcon#about to read 3, iclass 20, count 2 2006.258.01:17:10.72#ibcon#read 3, iclass 20, count 2 2006.258.01:17:10.72#ibcon#about to read 4, iclass 20, count 2 2006.258.01:17:10.72#ibcon#read 4, iclass 20, count 2 2006.258.01:17:10.72#ibcon#about to read 5, iclass 20, count 2 2006.258.01:17:10.72#ibcon#read 5, iclass 20, count 2 2006.258.01:17:10.72#ibcon#about to read 6, iclass 20, count 2 2006.258.01:17:10.72#ibcon#read 6, iclass 20, count 2 2006.258.01:17:10.72#ibcon#end of sib2, iclass 20, count 2 2006.258.01:17:10.72#ibcon#*after write, iclass 20, count 2 2006.258.01:17:10.72#ibcon#*before return 0, iclass 20, count 2 2006.258.01:17:10.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:10.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:10.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.01:17:10.72#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:10.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:10.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:10.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:10.84#ibcon#enter wrdev, iclass 20, count 0 2006.258.01:17:10.84#ibcon#first serial, iclass 20, count 0 2006.258.01:17:10.84#ibcon#enter sib2, iclass 20, count 0 2006.258.01:17:10.84#ibcon#flushed, iclass 20, count 0 2006.258.01:17:10.84#ibcon#about to write, iclass 20, count 0 2006.258.01:17:10.84#ibcon#wrote, iclass 20, count 0 2006.258.01:17:10.84#ibcon#about to read 3, iclass 20, count 0 2006.258.01:17:10.86#ibcon#read 3, iclass 20, count 0 2006.258.01:17:10.86#ibcon#about to read 4, iclass 20, count 0 2006.258.01:17:10.86#ibcon#read 4, iclass 20, count 0 2006.258.01:17:10.86#ibcon#about to read 5, iclass 20, count 0 2006.258.01:17:10.86#ibcon#read 5, iclass 20, count 0 2006.258.01:17:10.86#ibcon#about to read 6, iclass 20, count 0 2006.258.01:17:10.86#ibcon#read 6, iclass 20, count 0 2006.258.01:17:10.86#ibcon#end of sib2, iclass 20, count 0 2006.258.01:17:10.86#ibcon#*mode == 0, iclass 20, count 0 2006.258.01:17:10.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.01:17:10.86#ibcon#[25=USB\r\n] 2006.258.01:17:10.86#ibcon#*before write, iclass 20, count 0 2006.258.01:17:10.86#ibcon#enter sib2, iclass 20, count 0 2006.258.01:17:10.86#ibcon#flushed, iclass 20, count 0 2006.258.01:17:10.86#ibcon#about to write, iclass 20, count 0 2006.258.01:17:10.86#ibcon#wrote, iclass 20, count 0 2006.258.01:17:10.86#ibcon#about to read 3, iclass 20, count 0 2006.258.01:17:10.89#ibcon#read 3, iclass 20, count 0 2006.258.01:17:10.89#ibcon#about to read 4, iclass 20, count 0 2006.258.01:17:10.89#ibcon#read 4, iclass 20, count 0 2006.258.01:17:10.89#ibcon#about to read 5, iclass 20, count 0 2006.258.01:17:10.89#ibcon#read 5, iclass 20, count 0 2006.258.01:17:10.89#ibcon#about to read 6, iclass 20, count 0 2006.258.01:17:10.89#ibcon#read 6, iclass 20, count 0 2006.258.01:17:10.89#ibcon#end of sib2, iclass 20, count 0 2006.258.01:17:10.89#ibcon#*after write, iclass 20, count 0 2006.258.01:17:10.89#ibcon#*before return 0, iclass 20, count 0 2006.258.01:17:10.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:10.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:10.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.01:17:10.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.01:17:10.89$vck44/valo=3,564.99 2006.258.01:17:10.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.01:17:10.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.01:17:10.89#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:10.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:10.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:10.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:10.89#ibcon#enter wrdev, iclass 22, count 0 2006.258.01:17:10.89#ibcon#first serial, iclass 22, count 0 2006.258.01:17:10.89#ibcon#enter sib2, iclass 22, count 0 2006.258.01:17:10.90#ibcon#flushed, iclass 22, count 0 2006.258.01:17:10.90#ibcon#about to write, iclass 22, count 0 2006.258.01:17:10.90#ibcon#wrote, iclass 22, count 0 2006.258.01:17:10.90#ibcon#about to read 3, iclass 22, count 0 2006.258.01:17:10.91#ibcon#read 3, iclass 22, count 0 2006.258.01:17:10.91#ibcon#about to read 4, iclass 22, count 0 2006.258.01:17:10.91#ibcon#read 4, iclass 22, count 0 2006.258.01:17:10.91#ibcon#about to read 5, iclass 22, count 0 2006.258.01:17:10.91#ibcon#read 5, iclass 22, count 0 2006.258.01:17:10.91#ibcon#about to read 6, iclass 22, count 0 2006.258.01:17:10.91#ibcon#read 6, iclass 22, count 0 2006.258.01:17:10.91#ibcon#end of sib2, iclass 22, count 0 2006.258.01:17:10.91#ibcon#*mode == 0, iclass 22, count 0 2006.258.01:17:10.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.01:17:10.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.01:17:10.91#ibcon#*before write, iclass 22, count 0 2006.258.01:17:10.91#ibcon#enter sib2, iclass 22, count 0 2006.258.01:17:10.91#ibcon#flushed, iclass 22, count 0 2006.258.01:17:10.91#ibcon#about to write, iclass 22, count 0 2006.258.01:17:10.91#ibcon#wrote, iclass 22, count 0 2006.258.01:17:10.91#ibcon#about to read 3, iclass 22, count 0 2006.258.01:17:10.95#ibcon#read 3, iclass 22, count 0 2006.258.01:17:10.95#ibcon#about to read 4, iclass 22, count 0 2006.258.01:17:10.95#ibcon#read 4, iclass 22, count 0 2006.258.01:17:10.95#ibcon#about to read 5, iclass 22, count 0 2006.258.01:17:10.95#ibcon#read 5, iclass 22, count 0 2006.258.01:17:10.95#ibcon#about to read 6, iclass 22, count 0 2006.258.01:17:10.95#ibcon#read 6, iclass 22, count 0 2006.258.01:17:10.95#ibcon#end of sib2, iclass 22, count 0 2006.258.01:17:10.95#ibcon#*after write, iclass 22, count 0 2006.258.01:17:10.95#ibcon#*before return 0, iclass 22, count 0 2006.258.01:17:10.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:10.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:10.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.01:17:10.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.01:17:10.95$vck44/va=3,8 2006.258.01:17:10.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.01:17:10.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.01:17:10.95#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:10.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:11.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:11.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:11.01#ibcon#enter wrdev, iclass 24, count 2 2006.258.01:17:11.01#ibcon#first serial, iclass 24, count 2 2006.258.01:17:11.01#ibcon#enter sib2, iclass 24, count 2 2006.258.01:17:11.01#ibcon#flushed, iclass 24, count 2 2006.258.01:17:11.01#ibcon#about to write, iclass 24, count 2 2006.258.01:17:11.02#ibcon#wrote, iclass 24, count 2 2006.258.01:17:11.02#ibcon#about to read 3, iclass 24, count 2 2006.258.01:17:11.03#ibcon#read 3, iclass 24, count 2 2006.258.01:17:11.03#ibcon#about to read 4, iclass 24, count 2 2006.258.01:17:11.03#ibcon#read 4, iclass 24, count 2 2006.258.01:17:11.03#ibcon#about to read 5, iclass 24, count 2 2006.258.01:17:11.03#ibcon#read 5, iclass 24, count 2 2006.258.01:17:11.03#ibcon#about to read 6, iclass 24, count 2 2006.258.01:17:11.03#ibcon#read 6, iclass 24, count 2 2006.258.01:17:11.03#ibcon#end of sib2, iclass 24, count 2 2006.258.01:17:11.03#ibcon#*mode == 0, iclass 24, count 2 2006.258.01:17:11.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.01:17:11.03#ibcon#[25=AT03-08\r\n] 2006.258.01:17:11.03#ibcon#*before write, iclass 24, count 2 2006.258.01:17:11.03#ibcon#enter sib2, iclass 24, count 2 2006.258.01:17:11.03#ibcon#flushed, iclass 24, count 2 2006.258.01:17:11.03#ibcon#about to write, iclass 24, count 2 2006.258.01:17:11.03#ibcon#wrote, iclass 24, count 2 2006.258.01:17:11.03#ibcon#about to read 3, iclass 24, count 2 2006.258.01:17:11.06#ibcon#read 3, iclass 24, count 2 2006.258.01:17:11.06#ibcon#about to read 4, iclass 24, count 2 2006.258.01:17:11.06#ibcon#read 4, iclass 24, count 2 2006.258.01:17:11.06#ibcon#about to read 5, iclass 24, count 2 2006.258.01:17:11.06#ibcon#read 5, iclass 24, count 2 2006.258.01:17:11.06#ibcon#about to read 6, iclass 24, count 2 2006.258.01:17:11.06#ibcon#read 6, iclass 24, count 2 2006.258.01:17:11.06#ibcon#end of sib2, iclass 24, count 2 2006.258.01:17:11.06#ibcon#*after write, iclass 24, count 2 2006.258.01:17:11.06#ibcon#*before return 0, iclass 24, count 2 2006.258.01:17:11.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:11.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:11.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.01:17:11.06#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:11.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:11.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:11.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:11.18#ibcon#enter wrdev, iclass 24, count 0 2006.258.01:17:11.18#ibcon#first serial, iclass 24, count 0 2006.258.01:17:11.18#ibcon#enter sib2, iclass 24, count 0 2006.258.01:17:11.18#ibcon#flushed, iclass 24, count 0 2006.258.01:17:11.18#ibcon#about to write, iclass 24, count 0 2006.258.01:17:11.18#ibcon#wrote, iclass 24, count 0 2006.258.01:17:11.18#ibcon#about to read 3, iclass 24, count 0 2006.258.01:17:11.20#ibcon#read 3, iclass 24, count 0 2006.258.01:17:11.20#ibcon#about to read 4, iclass 24, count 0 2006.258.01:17:11.20#ibcon#read 4, iclass 24, count 0 2006.258.01:17:11.20#ibcon#about to read 5, iclass 24, count 0 2006.258.01:17:11.20#ibcon#read 5, iclass 24, count 0 2006.258.01:17:11.20#ibcon#about to read 6, iclass 24, count 0 2006.258.01:17:11.20#ibcon#read 6, iclass 24, count 0 2006.258.01:17:11.20#ibcon#end of sib2, iclass 24, count 0 2006.258.01:17:11.20#ibcon#*mode == 0, iclass 24, count 0 2006.258.01:17:11.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.01:17:11.20#ibcon#[25=USB\r\n] 2006.258.01:17:11.20#ibcon#*before write, iclass 24, count 0 2006.258.01:17:11.20#ibcon#enter sib2, iclass 24, count 0 2006.258.01:17:11.20#ibcon#flushed, iclass 24, count 0 2006.258.01:17:11.20#ibcon#about to write, iclass 24, count 0 2006.258.01:17:11.20#ibcon#wrote, iclass 24, count 0 2006.258.01:17:11.20#ibcon#about to read 3, iclass 24, count 0 2006.258.01:17:11.23#ibcon#read 3, iclass 24, count 0 2006.258.01:17:11.23#ibcon#about to read 4, iclass 24, count 0 2006.258.01:17:11.23#ibcon#read 4, iclass 24, count 0 2006.258.01:17:11.23#ibcon#about to read 5, iclass 24, count 0 2006.258.01:17:11.23#ibcon#read 5, iclass 24, count 0 2006.258.01:17:11.23#ibcon#about to read 6, iclass 24, count 0 2006.258.01:17:11.23#ibcon#read 6, iclass 24, count 0 2006.258.01:17:11.23#ibcon#end of sib2, iclass 24, count 0 2006.258.01:17:11.23#ibcon#*after write, iclass 24, count 0 2006.258.01:17:11.23#ibcon#*before return 0, iclass 24, count 0 2006.258.01:17:11.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:11.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:11.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.01:17:11.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.01:17:11.23$vck44/valo=4,624.99 2006.258.01:17:11.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.01:17:11.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.01:17:11.23#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:11.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:11.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:11.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:11.24#ibcon#enter wrdev, iclass 26, count 0 2006.258.01:17:11.24#ibcon#first serial, iclass 26, count 0 2006.258.01:17:11.24#ibcon#enter sib2, iclass 26, count 0 2006.258.01:17:11.24#ibcon#flushed, iclass 26, count 0 2006.258.01:17:11.24#ibcon#about to write, iclass 26, count 0 2006.258.01:17:11.24#ibcon#wrote, iclass 26, count 0 2006.258.01:17:11.24#ibcon#about to read 3, iclass 26, count 0 2006.258.01:17:11.25#ibcon#read 3, iclass 26, count 0 2006.258.01:17:11.25#ibcon#about to read 4, iclass 26, count 0 2006.258.01:17:11.25#ibcon#read 4, iclass 26, count 0 2006.258.01:17:11.25#ibcon#about to read 5, iclass 26, count 0 2006.258.01:17:11.25#ibcon#read 5, iclass 26, count 0 2006.258.01:17:11.25#ibcon#about to read 6, iclass 26, count 0 2006.258.01:17:11.25#ibcon#read 6, iclass 26, count 0 2006.258.01:17:11.25#ibcon#end of sib2, iclass 26, count 0 2006.258.01:17:11.25#ibcon#*mode == 0, iclass 26, count 0 2006.258.01:17:11.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.01:17:11.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.01:17:11.25#ibcon#*before write, iclass 26, count 0 2006.258.01:17:11.25#ibcon#enter sib2, iclass 26, count 0 2006.258.01:17:11.25#ibcon#flushed, iclass 26, count 0 2006.258.01:17:11.25#ibcon#about to write, iclass 26, count 0 2006.258.01:17:11.25#ibcon#wrote, iclass 26, count 0 2006.258.01:17:11.25#ibcon#about to read 3, iclass 26, count 0 2006.258.01:17:11.29#ibcon#read 3, iclass 26, count 0 2006.258.01:17:11.29#ibcon#about to read 4, iclass 26, count 0 2006.258.01:17:11.29#ibcon#read 4, iclass 26, count 0 2006.258.01:17:11.29#ibcon#about to read 5, iclass 26, count 0 2006.258.01:17:11.29#ibcon#read 5, iclass 26, count 0 2006.258.01:17:11.29#ibcon#about to read 6, iclass 26, count 0 2006.258.01:17:11.29#ibcon#read 6, iclass 26, count 0 2006.258.01:17:11.29#ibcon#end of sib2, iclass 26, count 0 2006.258.01:17:11.29#ibcon#*after write, iclass 26, count 0 2006.258.01:17:11.29#ibcon#*before return 0, iclass 26, count 0 2006.258.01:17:11.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:11.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:11.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.01:17:11.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.01:17:11.29$vck44/va=4,7 2006.258.01:17:11.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.01:17:11.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.01:17:11.29#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:11.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:11.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:11.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:11.35#ibcon#enter wrdev, iclass 28, count 2 2006.258.01:17:11.35#ibcon#first serial, iclass 28, count 2 2006.258.01:17:11.35#ibcon#enter sib2, iclass 28, count 2 2006.258.01:17:11.35#ibcon#flushed, iclass 28, count 2 2006.258.01:17:11.35#ibcon#about to write, iclass 28, count 2 2006.258.01:17:11.35#ibcon#wrote, iclass 28, count 2 2006.258.01:17:11.35#ibcon#about to read 3, iclass 28, count 2 2006.258.01:17:11.37#ibcon#read 3, iclass 28, count 2 2006.258.01:17:11.37#ibcon#about to read 4, iclass 28, count 2 2006.258.01:17:11.37#ibcon#read 4, iclass 28, count 2 2006.258.01:17:11.37#ibcon#about to read 5, iclass 28, count 2 2006.258.01:17:11.37#ibcon#read 5, iclass 28, count 2 2006.258.01:17:11.37#ibcon#about to read 6, iclass 28, count 2 2006.258.01:17:11.37#ibcon#read 6, iclass 28, count 2 2006.258.01:17:11.37#ibcon#end of sib2, iclass 28, count 2 2006.258.01:17:11.37#ibcon#*mode == 0, iclass 28, count 2 2006.258.01:17:11.37#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.01:17:11.37#ibcon#[25=AT04-07\r\n] 2006.258.01:17:11.37#ibcon#*before write, iclass 28, count 2 2006.258.01:17:11.37#ibcon#enter sib2, iclass 28, count 2 2006.258.01:17:11.37#ibcon#flushed, iclass 28, count 2 2006.258.01:17:11.37#ibcon#about to write, iclass 28, count 2 2006.258.01:17:11.37#ibcon#wrote, iclass 28, count 2 2006.258.01:17:11.37#ibcon#about to read 3, iclass 28, count 2 2006.258.01:17:11.40#ibcon#read 3, iclass 28, count 2 2006.258.01:17:11.40#ibcon#about to read 4, iclass 28, count 2 2006.258.01:17:11.40#ibcon#read 4, iclass 28, count 2 2006.258.01:17:11.40#ibcon#about to read 5, iclass 28, count 2 2006.258.01:17:11.40#ibcon#read 5, iclass 28, count 2 2006.258.01:17:11.40#ibcon#about to read 6, iclass 28, count 2 2006.258.01:17:11.40#ibcon#read 6, iclass 28, count 2 2006.258.01:17:11.40#ibcon#end of sib2, iclass 28, count 2 2006.258.01:17:11.40#ibcon#*after write, iclass 28, count 2 2006.258.01:17:11.43#ibcon#*before return 0, iclass 28, count 2 2006.258.01:17:11.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:11.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:11.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.01:17:11.43#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:11.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:11.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:11.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:11.54#ibcon#enter wrdev, iclass 28, count 0 2006.258.01:17:11.54#ibcon#first serial, iclass 28, count 0 2006.258.01:17:11.54#ibcon#enter sib2, iclass 28, count 0 2006.258.01:17:11.54#ibcon#flushed, iclass 28, count 0 2006.258.01:17:11.54#ibcon#about to write, iclass 28, count 0 2006.258.01:17:11.54#ibcon#wrote, iclass 28, count 0 2006.258.01:17:11.54#ibcon#about to read 3, iclass 28, count 0 2006.258.01:17:11.56#ibcon#read 3, iclass 28, count 0 2006.258.01:17:11.56#ibcon#about to read 4, iclass 28, count 0 2006.258.01:17:11.56#ibcon#read 4, iclass 28, count 0 2006.258.01:17:11.56#ibcon#about to read 5, iclass 28, count 0 2006.258.01:17:11.56#ibcon#read 5, iclass 28, count 0 2006.258.01:17:11.56#ibcon#about to read 6, iclass 28, count 0 2006.258.01:17:11.56#ibcon#read 6, iclass 28, count 0 2006.258.01:17:11.56#ibcon#end of sib2, iclass 28, count 0 2006.258.01:17:11.56#ibcon#*mode == 0, iclass 28, count 0 2006.258.01:17:11.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.01:17:11.56#ibcon#[25=USB\r\n] 2006.258.01:17:11.56#ibcon#*before write, iclass 28, count 0 2006.258.01:17:11.56#ibcon#enter sib2, iclass 28, count 0 2006.258.01:17:11.56#ibcon#flushed, iclass 28, count 0 2006.258.01:17:11.56#ibcon#about to write, iclass 28, count 0 2006.258.01:17:11.56#ibcon#wrote, iclass 28, count 0 2006.258.01:17:11.56#ibcon#about to read 3, iclass 28, count 0 2006.258.01:17:11.59#ibcon#read 3, iclass 28, count 0 2006.258.01:17:11.59#ibcon#about to read 4, iclass 28, count 0 2006.258.01:17:11.59#ibcon#read 4, iclass 28, count 0 2006.258.01:17:11.59#ibcon#about to read 5, iclass 28, count 0 2006.258.01:17:11.59#ibcon#read 5, iclass 28, count 0 2006.258.01:17:11.59#ibcon#about to read 6, iclass 28, count 0 2006.258.01:17:11.59#ibcon#read 6, iclass 28, count 0 2006.258.01:17:11.59#ibcon#end of sib2, iclass 28, count 0 2006.258.01:17:11.59#ibcon#*after write, iclass 28, count 0 2006.258.01:17:11.59#ibcon#*before return 0, iclass 28, count 0 2006.258.01:17:11.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:11.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:11.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.01:17:11.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.01:17:11.59$vck44/valo=5,734.99 2006.258.01:17:11.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.01:17:11.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.01:17:11.59#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:11.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:11.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:11.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:11.60#ibcon#enter wrdev, iclass 30, count 0 2006.258.01:17:11.60#ibcon#first serial, iclass 30, count 0 2006.258.01:17:11.60#ibcon#enter sib2, iclass 30, count 0 2006.258.01:17:11.60#ibcon#flushed, iclass 30, count 0 2006.258.01:17:11.60#ibcon#about to write, iclass 30, count 0 2006.258.01:17:11.60#ibcon#wrote, iclass 30, count 0 2006.258.01:17:11.60#ibcon#about to read 3, iclass 30, count 0 2006.258.01:17:11.61#ibcon#read 3, iclass 30, count 0 2006.258.01:17:11.61#ibcon#about to read 4, iclass 30, count 0 2006.258.01:17:11.61#ibcon#read 4, iclass 30, count 0 2006.258.01:17:11.61#ibcon#about to read 5, iclass 30, count 0 2006.258.01:17:11.61#ibcon#read 5, iclass 30, count 0 2006.258.01:17:11.61#ibcon#about to read 6, iclass 30, count 0 2006.258.01:17:11.61#ibcon#read 6, iclass 30, count 0 2006.258.01:17:11.61#ibcon#end of sib2, iclass 30, count 0 2006.258.01:17:11.61#ibcon#*mode == 0, iclass 30, count 0 2006.258.01:17:11.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.01:17:11.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.01:17:11.61#ibcon#*before write, iclass 30, count 0 2006.258.01:17:11.61#ibcon#enter sib2, iclass 30, count 0 2006.258.01:17:11.61#ibcon#flushed, iclass 30, count 0 2006.258.01:17:11.61#ibcon#about to write, iclass 30, count 0 2006.258.01:17:11.61#ibcon#wrote, iclass 30, count 0 2006.258.01:17:11.61#ibcon#about to read 3, iclass 30, count 0 2006.258.01:17:11.65#ibcon#read 3, iclass 30, count 0 2006.258.01:17:11.65#ibcon#about to read 4, iclass 30, count 0 2006.258.01:17:11.65#ibcon#read 4, iclass 30, count 0 2006.258.01:17:11.65#ibcon#about to read 5, iclass 30, count 0 2006.258.01:17:11.65#ibcon#read 5, iclass 30, count 0 2006.258.01:17:11.65#ibcon#about to read 6, iclass 30, count 0 2006.258.01:17:11.65#ibcon#read 6, iclass 30, count 0 2006.258.01:17:11.65#ibcon#end of sib2, iclass 30, count 0 2006.258.01:17:11.65#ibcon#*after write, iclass 30, count 0 2006.258.01:17:11.65#ibcon#*before return 0, iclass 30, count 0 2006.258.01:17:11.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:11.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:11.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.01:17:11.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.01:17:11.65$vck44/va=5,4 2006.258.01:17:11.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.258.01:17:11.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.258.01:17:11.65#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:11.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:11.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:11.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:11.71#ibcon#enter wrdev, iclass 32, count 2 2006.258.01:17:11.71#ibcon#first serial, iclass 32, count 2 2006.258.01:17:11.71#ibcon#enter sib2, iclass 32, count 2 2006.258.01:17:11.71#ibcon#flushed, iclass 32, count 2 2006.258.01:17:11.71#ibcon#about to write, iclass 32, count 2 2006.258.01:17:11.71#ibcon#wrote, iclass 32, count 2 2006.258.01:17:11.71#ibcon#about to read 3, iclass 32, count 2 2006.258.01:17:11.73#ibcon#read 3, iclass 32, count 2 2006.258.01:17:11.73#ibcon#about to read 4, iclass 32, count 2 2006.258.01:17:11.73#ibcon#read 4, iclass 32, count 2 2006.258.01:17:11.73#ibcon#about to read 5, iclass 32, count 2 2006.258.01:17:11.73#ibcon#read 5, iclass 32, count 2 2006.258.01:17:11.73#ibcon#about to read 6, iclass 32, count 2 2006.258.01:17:11.73#ibcon#read 6, iclass 32, count 2 2006.258.01:17:11.73#ibcon#end of sib2, iclass 32, count 2 2006.258.01:17:11.73#ibcon#*mode == 0, iclass 32, count 2 2006.258.01:17:11.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.258.01:17:11.73#ibcon#[25=AT05-04\r\n] 2006.258.01:17:11.73#ibcon#*before write, iclass 32, count 2 2006.258.01:17:11.73#ibcon#enter sib2, iclass 32, count 2 2006.258.01:17:11.73#ibcon#flushed, iclass 32, count 2 2006.258.01:17:11.73#ibcon#about to write, iclass 32, count 2 2006.258.01:17:11.73#ibcon#wrote, iclass 32, count 2 2006.258.01:17:11.73#ibcon#about to read 3, iclass 32, count 2 2006.258.01:17:11.76#ibcon#read 3, iclass 32, count 2 2006.258.01:17:11.76#ibcon#about to read 4, iclass 32, count 2 2006.258.01:17:11.76#ibcon#read 4, iclass 32, count 2 2006.258.01:17:11.76#ibcon#about to read 5, iclass 32, count 2 2006.258.01:17:11.76#ibcon#read 5, iclass 32, count 2 2006.258.01:17:11.76#ibcon#about to read 6, iclass 32, count 2 2006.258.01:17:11.76#ibcon#read 6, iclass 32, count 2 2006.258.01:17:11.76#ibcon#end of sib2, iclass 32, count 2 2006.258.01:17:11.76#ibcon#*after write, iclass 32, count 2 2006.258.01:17:11.76#ibcon#*before return 0, iclass 32, count 2 2006.258.01:17:11.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:11.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:11.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.258.01:17:11.76#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:11.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:11.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:11.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:11.88#ibcon#enter wrdev, iclass 32, count 0 2006.258.01:17:11.88#ibcon#first serial, iclass 32, count 0 2006.258.01:17:11.88#ibcon#enter sib2, iclass 32, count 0 2006.258.01:17:11.88#ibcon#flushed, iclass 32, count 0 2006.258.01:17:11.88#ibcon#about to write, iclass 32, count 0 2006.258.01:17:11.88#ibcon#wrote, iclass 32, count 0 2006.258.01:17:11.88#ibcon#about to read 3, iclass 32, count 0 2006.258.01:17:11.90#ibcon#read 3, iclass 32, count 0 2006.258.01:17:11.90#ibcon#about to read 4, iclass 32, count 0 2006.258.01:17:11.90#ibcon#read 4, iclass 32, count 0 2006.258.01:17:11.90#ibcon#about to read 5, iclass 32, count 0 2006.258.01:17:11.90#ibcon#read 5, iclass 32, count 0 2006.258.01:17:11.90#ibcon#about to read 6, iclass 32, count 0 2006.258.01:17:11.90#ibcon#read 6, iclass 32, count 0 2006.258.01:17:11.90#ibcon#end of sib2, iclass 32, count 0 2006.258.01:17:11.90#ibcon#*mode == 0, iclass 32, count 0 2006.258.01:17:11.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.01:17:11.90#ibcon#[25=USB\r\n] 2006.258.01:17:11.90#ibcon#*before write, iclass 32, count 0 2006.258.01:17:11.90#ibcon#enter sib2, iclass 32, count 0 2006.258.01:17:11.90#ibcon#flushed, iclass 32, count 0 2006.258.01:17:11.90#ibcon#about to write, iclass 32, count 0 2006.258.01:17:11.90#ibcon#wrote, iclass 32, count 0 2006.258.01:17:11.90#ibcon#about to read 3, iclass 32, count 0 2006.258.01:17:11.93#ibcon#read 3, iclass 32, count 0 2006.258.01:17:11.93#ibcon#about to read 4, iclass 32, count 0 2006.258.01:17:11.93#ibcon#read 4, iclass 32, count 0 2006.258.01:17:11.93#ibcon#about to read 5, iclass 32, count 0 2006.258.01:17:11.93#ibcon#read 5, iclass 32, count 0 2006.258.01:17:11.93#ibcon#about to read 6, iclass 32, count 0 2006.258.01:17:11.93#ibcon#read 6, iclass 32, count 0 2006.258.01:17:11.93#ibcon#end of sib2, iclass 32, count 0 2006.258.01:17:11.93#ibcon#*after write, iclass 32, count 0 2006.258.01:17:11.93#ibcon#*before return 0, iclass 32, count 0 2006.258.01:17:11.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:11.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:11.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.01:17:11.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.01:17:11.93$vck44/valo=6,814.99 2006.258.01:17:11.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.01:17:11.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.01:17:11.93#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:11.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:11.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:11.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:11.93#ibcon#enter wrdev, iclass 34, count 0 2006.258.01:17:11.93#ibcon#first serial, iclass 34, count 0 2006.258.01:17:11.93#ibcon#enter sib2, iclass 34, count 0 2006.258.01:17:11.94#ibcon#flushed, iclass 34, count 0 2006.258.01:17:11.94#ibcon#about to write, iclass 34, count 0 2006.258.01:17:11.94#ibcon#wrote, iclass 34, count 0 2006.258.01:17:11.94#ibcon#about to read 3, iclass 34, count 0 2006.258.01:17:11.95#ibcon#read 3, iclass 34, count 0 2006.258.01:17:11.95#ibcon#about to read 4, iclass 34, count 0 2006.258.01:17:11.95#ibcon#read 4, iclass 34, count 0 2006.258.01:17:11.95#ibcon#about to read 5, iclass 34, count 0 2006.258.01:17:11.95#ibcon#read 5, iclass 34, count 0 2006.258.01:17:11.95#ibcon#about to read 6, iclass 34, count 0 2006.258.01:17:11.95#ibcon#read 6, iclass 34, count 0 2006.258.01:17:11.95#ibcon#end of sib2, iclass 34, count 0 2006.258.01:17:11.95#ibcon#*mode == 0, iclass 34, count 0 2006.258.01:17:11.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.01:17:11.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.01:17:11.95#ibcon#*before write, iclass 34, count 0 2006.258.01:17:11.95#ibcon#enter sib2, iclass 34, count 0 2006.258.01:17:11.95#ibcon#flushed, iclass 34, count 0 2006.258.01:17:11.95#ibcon#about to write, iclass 34, count 0 2006.258.01:17:11.95#ibcon#wrote, iclass 34, count 0 2006.258.01:17:11.95#ibcon#about to read 3, iclass 34, count 0 2006.258.01:17:11.99#ibcon#read 3, iclass 34, count 0 2006.258.01:17:11.99#ibcon#about to read 4, iclass 34, count 0 2006.258.01:17:11.99#ibcon#read 4, iclass 34, count 0 2006.258.01:17:11.99#ibcon#about to read 5, iclass 34, count 0 2006.258.01:17:11.99#ibcon#read 5, iclass 34, count 0 2006.258.01:17:11.99#ibcon#about to read 6, iclass 34, count 0 2006.258.01:17:11.99#ibcon#read 6, iclass 34, count 0 2006.258.01:17:11.99#ibcon#end of sib2, iclass 34, count 0 2006.258.01:17:11.99#ibcon#*after write, iclass 34, count 0 2006.258.01:17:11.99#ibcon#*before return 0, iclass 34, count 0 2006.258.01:17:11.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:11.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:11.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.01:17:11.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.01:17:11.99$vck44/va=6,4 2006.258.01:17:11.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.258.01:17:11.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.258.01:17:11.99#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:12.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:12.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:12.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:12.05#ibcon#enter wrdev, iclass 36, count 2 2006.258.01:17:12.05#ibcon#first serial, iclass 36, count 2 2006.258.01:17:12.05#ibcon#enter sib2, iclass 36, count 2 2006.258.01:17:12.05#ibcon#flushed, iclass 36, count 2 2006.258.01:17:12.05#ibcon#about to write, iclass 36, count 2 2006.258.01:17:12.05#ibcon#wrote, iclass 36, count 2 2006.258.01:17:12.05#ibcon#about to read 3, iclass 36, count 2 2006.258.01:17:12.07#ibcon#read 3, iclass 36, count 2 2006.258.01:17:12.07#ibcon#about to read 4, iclass 36, count 2 2006.258.01:17:12.07#ibcon#read 4, iclass 36, count 2 2006.258.01:17:12.07#ibcon#about to read 5, iclass 36, count 2 2006.258.01:17:12.07#ibcon#read 5, iclass 36, count 2 2006.258.01:17:12.07#ibcon#about to read 6, iclass 36, count 2 2006.258.01:17:12.07#ibcon#read 6, iclass 36, count 2 2006.258.01:17:12.07#ibcon#end of sib2, iclass 36, count 2 2006.258.01:17:12.07#ibcon#*mode == 0, iclass 36, count 2 2006.258.01:17:12.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.258.01:17:12.07#ibcon#[25=AT06-04\r\n] 2006.258.01:17:12.07#ibcon#*before write, iclass 36, count 2 2006.258.01:17:12.07#ibcon#enter sib2, iclass 36, count 2 2006.258.01:17:12.07#ibcon#flushed, iclass 36, count 2 2006.258.01:17:12.07#ibcon#about to write, iclass 36, count 2 2006.258.01:17:12.07#ibcon#wrote, iclass 36, count 2 2006.258.01:17:12.07#ibcon#about to read 3, iclass 36, count 2 2006.258.01:17:12.10#ibcon#read 3, iclass 36, count 2 2006.258.01:17:12.10#ibcon#about to read 4, iclass 36, count 2 2006.258.01:17:12.10#ibcon#read 4, iclass 36, count 2 2006.258.01:17:12.10#ibcon#about to read 5, iclass 36, count 2 2006.258.01:17:12.10#ibcon#read 5, iclass 36, count 2 2006.258.01:17:12.10#ibcon#about to read 6, iclass 36, count 2 2006.258.01:17:12.10#ibcon#read 6, iclass 36, count 2 2006.258.01:17:12.10#ibcon#end of sib2, iclass 36, count 2 2006.258.01:17:12.10#ibcon#*after write, iclass 36, count 2 2006.258.01:17:12.10#ibcon#*before return 0, iclass 36, count 2 2006.258.01:17:12.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:12.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:12.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.258.01:17:12.10#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:12.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:12.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:12.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:12.22#ibcon#enter wrdev, iclass 36, count 0 2006.258.01:17:12.22#ibcon#first serial, iclass 36, count 0 2006.258.01:17:12.22#ibcon#enter sib2, iclass 36, count 0 2006.258.01:17:12.22#ibcon#flushed, iclass 36, count 0 2006.258.01:17:12.22#ibcon#about to write, iclass 36, count 0 2006.258.01:17:12.22#ibcon#wrote, iclass 36, count 0 2006.258.01:17:12.22#ibcon#about to read 3, iclass 36, count 0 2006.258.01:17:12.24#ibcon#read 3, iclass 36, count 0 2006.258.01:17:12.24#ibcon#about to read 4, iclass 36, count 0 2006.258.01:17:12.24#ibcon#read 4, iclass 36, count 0 2006.258.01:17:12.24#ibcon#about to read 5, iclass 36, count 0 2006.258.01:17:12.24#ibcon#read 5, iclass 36, count 0 2006.258.01:17:12.24#ibcon#about to read 6, iclass 36, count 0 2006.258.01:17:12.24#ibcon#read 6, iclass 36, count 0 2006.258.01:17:12.24#ibcon#end of sib2, iclass 36, count 0 2006.258.01:17:12.24#ibcon#*mode == 0, iclass 36, count 0 2006.258.01:17:12.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.01:17:12.24#ibcon#[25=USB\r\n] 2006.258.01:17:12.24#ibcon#*before write, iclass 36, count 0 2006.258.01:17:12.24#ibcon#enter sib2, iclass 36, count 0 2006.258.01:17:12.24#ibcon#flushed, iclass 36, count 0 2006.258.01:17:12.24#ibcon#about to write, iclass 36, count 0 2006.258.01:17:12.24#ibcon#wrote, iclass 36, count 0 2006.258.01:17:12.24#ibcon#about to read 3, iclass 36, count 0 2006.258.01:17:12.27#ibcon#read 3, iclass 36, count 0 2006.258.01:17:12.27#ibcon#about to read 4, iclass 36, count 0 2006.258.01:17:12.27#ibcon#read 4, iclass 36, count 0 2006.258.01:17:12.27#ibcon#about to read 5, iclass 36, count 0 2006.258.01:17:12.27#ibcon#read 5, iclass 36, count 0 2006.258.01:17:12.27#ibcon#about to read 6, iclass 36, count 0 2006.258.01:17:12.27#ibcon#read 6, iclass 36, count 0 2006.258.01:17:12.27#ibcon#end of sib2, iclass 36, count 0 2006.258.01:17:12.27#ibcon#*after write, iclass 36, count 0 2006.258.01:17:12.27#ibcon#*before return 0, iclass 36, count 0 2006.258.01:17:12.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:12.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:12.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.01:17:12.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.01:17:12.27$vck44/valo=7,864.99 2006.258.01:17:12.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.01:17:12.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.01:17:12.28#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:12.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:12.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:12.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:12.28#ibcon#enter wrdev, iclass 38, count 0 2006.258.01:17:12.28#ibcon#first serial, iclass 38, count 0 2006.258.01:17:12.28#ibcon#enter sib2, iclass 38, count 0 2006.258.01:17:12.28#ibcon#flushed, iclass 38, count 0 2006.258.01:17:12.28#ibcon#about to write, iclass 38, count 0 2006.258.01:17:12.28#ibcon#wrote, iclass 38, count 0 2006.258.01:17:12.28#ibcon#about to read 3, iclass 38, count 0 2006.258.01:17:12.29#ibcon#read 3, iclass 38, count 0 2006.258.01:17:12.29#ibcon#about to read 4, iclass 38, count 0 2006.258.01:17:12.29#ibcon#read 4, iclass 38, count 0 2006.258.01:17:12.29#ibcon#about to read 5, iclass 38, count 0 2006.258.01:17:12.29#ibcon#read 5, iclass 38, count 0 2006.258.01:17:12.29#ibcon#about to read 6, iclass 38, count 0 2006.258.01:17:12.29#ibcon#read 6, iclass 38, count 0 2006.258.01:17:12.29#ibcon#end of sib2, iclass 38, count 0 2006.258.01:17:12.29#ibcon#*mode == 0, iclass 38, count 0 2006.258.01:17:12.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.01:17:12.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.01:17:12.29#ibcon#*before write, iclass 38, count 0 2006.258.01:17:12.29#ibcon#enter sib2, iclass 38, count 0 2006.258.01:17:12.29#ibcon#flushed, iclass 38, count 0 2006.258.01:17:12.29#ibcon#about to write, iclass 38, count 0 2006.258.01:17:12.29#ibcon#wrote, iclass 38, count 0 2006.258.01:17:12.29#ibcon#about to read 3, iclass 38, count 0 2006.258.01:17:12.33#ibcon#read 3, iclass 38, count 0 2006.258.01:17:12.33#ibcon#about to read 4, iclass 38, count 0 2006.258.01:17:12.33#ibcon#read 4, iclass 38, count 0 2006.258.01:17:12.33#ibcon#about to read 5, iclass 38, count 0 2006.258.01:17:12.33#ibcon#read 5, iclass 38, count 0 2006.258.01:17:12.33#ibcon#about to read 6, iclass 38, count 0 2006.258.01:17:12.33#ibcon#read 6, iclass 38, count 0 2006.258.01:17:12.33#ibcon#end of sib2, iclass 38, count 0 2006.258.01:17:12.33#ibcon#*after write, iclass 38, count 0 2006.258.01:17:12.33#ibcon#*before return 0, iclass 38, count 0 2006.258.01:17:12.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:12.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:12.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.01:17:12.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.01:17:12.33$vck44/va=7,4 2006.258.01:17:12.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.258.01:17:12.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.258.01:17:12.33#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:12.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:12.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:12.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:12.39#ibcon#enter wrdev, iclass 40, count 2 2006.258.01:17:12.39#ibcon#first serial, iclass 40, count 2 2006.258.01:17:12.39#ibcon#enter sib2, iclass 40, count 2 2006.258.01:17:12.39#ibcon#flushed, iclass 40, count 2 2006.258.01:17:12.39#ibcon#about to write, iclass 40, count 2 2006.258.01:17:12.39#ibcon#wrote, iclass 40, count 2 2006.258.01:17:12.39#ibcon#about to read 3, iclass 40, count 2 2006.258.01:17:12.41#ibcon#read 3, iclass 40, count 2 2006.258.01:17:12.41#ibcon#about to read 4, iclass 40, count 2 2006.258.01:17:12.41#ibcon#read 4, iclass 40, count 2 2006.258.01:17:12.41#ibcon#about to read 5, iclass 40, count 2 2006.258.01:17:12.41#ibcon#read 5, iclass 40, count 2 2006.258.01:17:12.41#ibcon#about to read 6, iclass 40, count 2 2006.258.01:17:12.41#ibcon#read 6, iclass 40, count 2 2006.258.01:17:12.41#ibcon#end of sib2, iclass 40, count 2 2006.258.01:17:12.41#ibcon#*mode == 0, iclass 40, count 2 2006.258.01:17:12.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.258.01:17:12.41#ibcon#[25=AT07-04\r\n] 2006.258.01:17:12.41#ibcon#*before write, iclass 40, count 2 2006.258.01:17:12.41#ibcon#enter sib2, iclass 40, count 2 2006.258.01:17:12.41#ibcon#flushed, iclass 40, count 2 2006.258.01:17:12.41#ibcon#about to write, iclass 40, count 2 2006.258.01:17:12.41#ibcon#wrote, iclass 40, count 2 2006.258.01:17:12.41#ibcon#about to read 3, iclass 40, count 2 2006.258.01:17:12.44#ibcon#read 3, iclass 40, count 2 2006.258.01:17:12.45#ibcon#about to read 4, iclass 40, count 2 2006.258.01:17:12.45#ibcon#read 4, iclass 40, count 2 2006.258.01:17:12.45#ibcon#about to read 5, iclass 40, count 2 2006.258.01:17:12.45#ibcon#read 5, iclass 40, count 2 2006.258.01:17:12.45#ibcon#about to read 6, iclass 40, count 2 2006.258.01:17:12.45#ibcon#read 6, iclass 40, count 2 2006.258.01:17:12.45#ibcon#end of sib2, iclass 40, count 2 2006.258.01:17:12.45#ibcon#*after write, iclass 40, count 2 2006.258.01:17:12.45#ibcon#*before return 0, iclass 40, count 2 2006.258.01:17:12.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:12.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:12.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.258.01:17:12.45#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:12.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:12.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:12.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:12.56#ibcon#enter wrdev, iclass 40, count 0 2006.258.01:17:12.56#ibcon#first serial, iclass 40, count 0 2006.258.01:17:12.56#ibcon#enter sib2, iclass 40, count 0 2006.258.01:17:12.56#ibcon#flushed, iclass 40, count 0 2006.258.01:17:12.56#ibcon#about to write, iclass 40, count 0 2006.258.01:17:12.56#ibcon#wrote, iclass 40, count 0 2006.258.01:17:12.56#ibcon#about to read 3, iclass 40, count 0 2006.258.01:17:12.58#ibcon#read 3, iclass 40, count 0 2006.258.01:17:12.58#ibcon#about to read 4, iclass 40, count 0 2006.258.01:17:12.58#ibcon#read 4, iclass 40, count 0 2006.258.01:17:12.58#ibcon#about to read 5, iclass 40, count 0 2006.258.01:17:12.58#ibcon#read 5, iclass 40, count 0 2006.258.01:17:12.58#ibcon#about to read 6, iclass 40, count 0 2006.258.01:17:12.58#ibcon#read 6, iclass 40, count 0 2006.258.01:17:12.58#ibcon#end of sib2, iclass 40, count 0 2006.258.01:17:12.58#ibcon#*mode == 0, iclass 40, count 0 2006.258.01:17:12.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.01:17:12.58#ibcon#[25=USB\r\n] 2006.258.01:17:12.58#ibcon#*before write, iclass 40, count 0 2006.258.01:17:12.58#ibcon#enter sib2, iclass 40, count 0 2006.258.01:17:12.58#ibcon#flushed, iclass 40, count 0 2006.258.01:17:12.58#ibcon#about to write, iclass 40, count 0 2006.258.01:17:12.58#ibcon#wrote, iclass 40, count 0 2006.258.01:17:12.58#ibcon#about to read 3, iclass 40, count 0 2006.258.01:17:12.61#ibcon#read 3, iclass 40, count 0 2006.258.01:17:12.61#ibcon#about to read 4, iclass 40, count 0 2006.258.01:17:12.61#ibcon#read 4, iclass 40, count 0 2006.258.01:17:12.61#ibcon#about to read 5, iclass 40, count 0 2006.258.01:17:12.61#ibcon#read 5, iclass 40, count 0 2006.258.01:17:12.61#ibcon#about to read 6, iclass 40, count 0 2006.258.01:17:12.61#ibcon#read 6, iclass 40, count 0 2006.258.01:17:12.61#ibcon#end of sib2, iclass 40, count 0 2006.258.01:17:12.61#ibcon#*after write, iclass 40, count 0 2006.258.01:17:12.61#ibcon#*before return 0, iclass 40, count 0 2006.258.01:17:12.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:12.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:12.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.01:17:12.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.01:17:12.61$vck44/valo=8,884.99 2006.258.01:17:12.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.258.01:17:12.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.258.01:17:12.62#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:12.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:12.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:12.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:12.62#ibcon#enter wrdev, iclass 4, count 0 2006.258.01:17:12.62#ibcon#first serial, iclass 4, count 0 2006.258.01:17:12.62#ibcon#enter sib2, iclass 4, count 0 2006.258.01:17:12.62#ibcon#flushed, iclass 4, count 0 2006.258.01:17:12.62#ibcon#about to write, iclass 4, count 0 2006.258.01:17:12.62#ibcon#wrote, iclass 4, count 0 2006.258.01:17:12.62#ibcon#about to read 3, iclass 4, count 0 2006.258.01:17:12.63#ibcon#read 3, iclass 4, count 0 2006.258.01:17:12.63#ibcon#about to read 4, iclass 4, count 0 2006.258.01:17:12.63#ibcon#read 4, iclass 4, count 0 2006.258.01:17:12.63#ibcon#about to read 5, iclass 4, count 0 2006.258.01:17:12.63#ibcon#read 5, iclass 4, count 0 2006.258.01:17:12.63#ibcon#about to read 6, iclass 4, count 0 2006.258.01:17:12.63#ibcon#read 6, iclass 4, count 0 2006.258.01:17:12.63#ibcon#end of sib2, iclass 4, count 0 2006.258.01:17:12.63#ibcon#*mode == 0, iclass 4, count 0 2006.258.01:17:12.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.01:17:12.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.01:17:12.63#ibcon#*before write, iclass 4, count 0 2006.258.01:17:12.63#ibcon#enter sib2, iclass 4, count 0 2006.258.01:17:12.63#ibcon#flushed, iclass 4, count 0 2006.258.01:17:12.63#ibcon#about to write, iclass 4, count 0 2006.258.01:17:12.63#ibcon#wrote, iclass 4, count 0 2006.258.01:17:12.63#ibcon#about to read 3, iclass 4, count 0 2006.258.01:17:12.67#ibcon#read 3, iclass 4, count 0 2006.258.01:17:12.67#ibcon#about to read 4, iclass 4, count 0 2006.258.01:17:12.67#ibcon#read 4, iclass 4, count 0 2006.258.01:17:12.67#ibcon#about to read 5, iclass 4, count 0 2006.258.01:17:12.67#ibcon#read 5, iclass 4, count 0 2006.258.01:17:12.67#ibcon#about to read 6, iclass 4, count 0 2006.258.01:17:12.67#ibcon#read 6, iclass 4, count 0 2006.258.01:17:12.67#ibcon#end of sib2, iclass 4, count 0 2006.258.01:17:12.67#ibcon#*after write, iclass 4, count 0 2006.258.01:17:12.67#ibcon#*before return 0, iclass 4, count 0 2006.258.01:17:12.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:12.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:12.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.01:17:12.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.01:17:12.67$vck44/va=8,4 2006.258.01:17:12.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.258.01:17:12.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.258.01:17:12.67#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:12.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:17:12.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:17:12.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:17:12.73#ibcon#enter wrdev, iclass 6, count 2 2006.258.01:17:12.73#ibcon#first serial, iclass 6, count 2 2006.258.01:17:12.73#ibcon#enter sib2, iclass 6, count 2 2006.258.01:17:12.73#ibcon#flushed, iclass 6, count 2 2006.258.01:17:12.73#ibcon#about to write, iclass 6, count 2 2006.258.01:17:12.73#ibcon#wrote, iclass 6, count 2 2006.258.01:17:12.73#ibcon#about to read 3, iclass 6, count 2 2006.258.01:17:12.75#ibcon#read 3, iclass 6, count 2 2006.258.01:17:12.75#ibcon#about to read 4, iclass 6, count 2 2006.258.01:17:12.75#ibcon#read 4, iclass 6, count 2 2006.258.01:17:12.75#ibcon#about to read 5, iclass 6, count 2 2006.258.01:17:12.75#ibcon#read 5, iclass 6, count 2 2006.258.01:17:12.75#ibcon#about to read 6, iclass 6, count 2 2006.258.01:17:12.75#ibcon#read 6, iclass 6, count 2 2006.258.01:17:12.75#ibcon#end of sib2, iclass 6, count 2 2006.258.01:17:12.75#ibcon#*mode == 0, iclass 6, count 2 2006.258.01:17:12.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.258.01:17:12.75#ibcon#[25=AT08-04\r\n] 2006.258.01:17:12.75#ibcon#*before write, iclass 6, count 2 2006.258.01:17:12.75#ibcon#enter sib2, iclass 6, count 2 2006.258.01:17:12.75#ibcon#flushed, iclass 6, count 2 2006.258.01:17:12.75#ibcon#about to write, iclass 6, count 2 2006.258.01:17:12.75#ibcon#wrote, iclass 6, count 2 2006.258.01:17:12.75#ibcon#about to read 3, iclass 6, count 2 2006.258.01:17:12.78#ibcon#read 3, iclass 6, count 2 2006.258.01:17:12.78#ibcon#about to read 4, iclass 6, count 2 2006.258.01:17:12.78#ibcon#read 4, iclass 6, count 2 2006.258.01:17:12.78#ibcon#about to read 5, iclass 6, count 2 2006.258.01:17:12.78#ibcon#read 5, iclass 6, count 2 2006.258.01:17:12.78#ibcon#about to read 6, iclass 6, count 2 2006.258.01:17:12.78#ibcon#read 6, iclass 6, count 2 2006.258.01:17:12.78#ibcon#end of sib2, iclass 6, count 2 2006.258.01:17:12.78#ibcon#*after write, iclass 6, count 2 2006.258.01:17:12.78#ibcon#*before return 0, iclass 6, count 2 2006.258.01:17:12.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:17:12.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:17:12.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.258.01:17:12.79#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:12.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:17:12.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:17:12.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:17:12.89#ibcon#enter wrdev, iclass 6, count 0 2006.258.01:17:12.89#ibcon#first serial, iclass 6, count 0 2006.258.01:17:12.89#ibcon#enter sib2, iclass 6, count 0 2006.258.01:17:12.89#ibcon#flushed, iclass 6, count 0 2006.258.01:17:12.89#ibcon#about to write, iclass 6, count 0 2006.258.01:17:12.89#ibcon#wrote, iclass 6, count 0 2006.258.01:17:12.89#ibcon#about to read 3, iclass 6, count 0 2006.258.01:17:12.91#ibcon#read 3, iclass 6, count 0 2006.258.01:17:12.91#ibcon#about to read 4, iclass 6, count 0 2006.258.01:17:12.91#ibcon#read 4, iclass 6, count 0 2006.258.01:17:12.91#ibcon#about to read 5, iclass 6, count 0 2006.258.01:17:12.91#ibcon#read 5, iclass 6, count 0 2006.258.01:17:12.91#ibcon#about to read 6, iclass 6, count 0 2006.258.01:17:12.91#ibcon#read 6, iclass 6, count 0 2006.258.01:17:12.91#ibcon#end of sib2, iclass 6, count 0 2006.258.01:17:12.91#ibcon#*mode == 0, iclass 6, count 0 2006.258.01:17:12.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.01:17:12.91#ibcon#[25=USB\r\n] 2006.258.01:17:12.91#ibcon#*before write, iclass 6, count 0 2006.258.01:17:12.91#ibcon#enter sib2, iclass 6, count 0 2006.258.01:17:12.91#ibcon#flushed, iclass 6, count 0 2006.258.01:17:12.91#ibcon#about to write, iclass 6, count 0 2006.258.01:17:12.91#ibcon#wrote, iclass 6, count 0 2006.258.01:17:12.91#ibcon#about to read 3, iclass 6, count 0 2006.258.01:17:12.94#ibcon#read 3, iclass 6, count 0 2006.258.01:17:12.94#ibcon#about to read 4, iclass 6, count 0 2006.258.01:17:12.94#ibcon#read 4, iclass 6, count 0 2006.258.01:17:12.94#ibcon#about to read 5, iclass 6, count 0 2006.258.01:17:12.94#ibcon#read 5, iclass 6, count 0 2006.258.01:17:12.94#ibcon#about to read 6, iclass 6, count 0 2006.258.01:17:12.94#ibcon#read 6, iclass 6, count 0 2006.258.01:17:12.94#ibcon#end of sib2, iclass 6, count 0 2006.258.01:17:12.94#ibcon#*after write, iclass 6, count 0 2006.258.01:17:12.94#ibcon#*before return 0, iclass 6, count 0 2006.258.01:17:12.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:17:12.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:17:12.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.01:17:12.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.01:17:12.94$vck44/vblo=1,629.99 2006.258.01:17:12.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.258.01:17:12.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.258.01:17:12.94#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:12.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:17:12.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:17:12.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:17:12.95#ibcon#enter wrdev, iclass 10, count 0 2006.258.01:17:12.95#ibcon#first serial, iclass 10, count 0 2006.258.01:17:12.95#ibcon#enter sib2, iclass 10, count 0 2006.258.01:17:12.95#ibcon#flushed, iclass 10, count 0 2006.258.01:17:12.95#ibcon#about to write, iclass 10, count 0 2006.258.01:17:12.95#ibcon#wrote, iclass 10, count 0 2006.258.01:17:12.95#ibcon#about to read 3, iclass 10, count 0 2006.258.01:17:12.96#ibcon#read 3, iclass 10, count 0 2006.258.01:17:12.96#ibcon#about to read 4, iclass 10, count 0 2006.258.01:17:12.96#ibcon#read 4, iclass 10, count 0 2006.258.01:17:12.96#ibcon#about to read 5, iclass 10, count 0 2006.258.01:17:12.96#ibcon#read 5, iclass 10, count 0 2006.258.01:17:12.96#ibcon#about to read 6, iclass 10, count 0 2006.258.01:17:12.96#ibcon#read 6, iclass 10, count 0 2006.258.01:17:12.96#ibcon#end of sib2, iclass 10, count 0 2006.258.01:17:12.96#ibcon#*mode == 0, iclass 10, count 0 2006.258.01:17:12.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.01:17:12.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.01:17:12.96#ibcon#*before write, iclass 10, count 0 2006.258.01:17:12.96#ibcon#enter sib2, iclass 10, count 0 2006.258.01:17:12.96#ibcon#flushed, iclass 10, count 0 2006.258.01:17:12.96#ibcon#about to write, iclass 10, count 0 2006.258.01:17:12.96#ibcon#wrote, iclass 10, count 0 2006.258.01:17:12.96#ibcon#about to read 3, iclass 10, count 0 2006.258.01:17:13.00#ibcon#read 3, iclass 10, count 0 2006.258.01:17:13.00#ibcon#about to read 4, iclass 10, count 0 2006.258.01:17:13.00#ibcon#read 4, iclass 10, count 0 2006.258.01:17:13.00#ibcon#about to read 5, iclass 10, count 0 2006.258.01:17:13.00#ibcon#read 5, iclass 10, count 0 2006.258.01:17:13.00#ibcon#about to read 6, iclass 10, count 0 2006.258.01:17:13.00#ibcon#read 6, iclass 10, count 0 2006.258.01:17:13.00#ibcon#end of sib2, iclass 10, count 0 2006.258.01:17:13.00#ibcon#*after write, iclass 10, count 0 2006.258.01:17:13.00#ibcon#*before return 0, iclass 10, count 0 2006.258.01:17:13.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:17:13.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:17:13.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.01:17:13.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.01:17:13.00$vck44/vb=1,4 2006.258.01:17:13.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.258.01:17:13.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.258.01:17:13.00#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:13.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:17:13.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:17:13.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:17:13.00#ibcon#enter wrdev, iclass 12, count 2 2006.258.01:17:13.01#ibcon#first serial, iclass 12, count 2 2006.258.01:17:13.01#ibcon#enter sib2, iclass 12, count 2 2006.258.01:17:13.01#ibcon#flushed, iclass 12, count 2 2006.258.01:17:13.01#ibcon#about to write, iclass 12, count 2 2006.258.01:17:13.01#ibcon#wrote, iclass 12, count 2 2006.258.01:17:13.01#ibcon#about to read 3, iclass 12, count 2 2006.258.01:17:13.02#ibcon#read 3, iclass 12, count 2 2006.258.01:17:13.02#ibcon#about to read 4, iclass 12, count 2 2006.258.01:17:13.02#ibcon#read 4, iclass 12, count 2 2006.258.01:17:13.02#ibcon#about to read 5, iclass 12, count 2 2006.258.01:17:13.02#ibcon#read 5, iclass 12, count 2 2006.258.01:17:13.02#ibcon#about to read 6, iclass 12, count 2 2006.258.01:17:13.02#ibcon#read 6, iclass 12, count 2 2006.258.01:17:13.02#ibcon#end of sib2, iclass 12, count 2 2006.258.01:17:13.02#ibcon#*mode == 0, iclass 12, count 2 2006.258.01:17:13.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.258.01:17:13.02#ibcon#[27=AT01-04\r\n] 2006.258.01:17:13.02#ibcon#*before write, iclass 12, count 2 2006.258.01:17:13.02#ibcon#enter sib2, iclass 12, count 2 2006.258.01:17:13.02#ibcon#flushed, iclass 12, count 2 2006.258.01:17:13.02#ibcon#about to write, iclass 12, count 2 2006.258.01:17:13.02#ibcon#wrote, iclass 12, count 2 2006.258.01:17:13.02#ibcon#about to read 3, iclass 12, count 2 2006.258.01:17:13.05#ibcon#read 3, iclass 12, count 2 2006.258.01:17:13.05#ibcon#about to read 4, iclass 12, count 2 2006.258.01:17:13.05#ibcon#read 4, iclass 12, count 2 2006.258.01:17:13.05#ibcon#about to read 5, iclass 12, count 2 2006.258.01:17:13.05#ibcon#read 5, iclass 12, count 2 2006.258.01:17:13.05#ibcon#about to read 6, iclass 12, count 2 2006.258.01:17:13.05#ibcon#read 6, iclass 12, count 2 2006.258.01:17:13.05#ibcon#end of sib2, iclass 12, count 2 2006.258.01:17:13.05#ibcon#*after write, iclass 12, count 2 2006.258.01:17:13.05#ibcon#*before return 0, iclass 12, count 2 2006.258.01:17:13.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:17:13.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:17:13.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.258.01:17:13.05#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:13.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:17:13.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:17:13.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:17:13.17#ibcon#enter wrdev, iclass 12, count 0 2006.258.01:17:13.17#ibcon#first serial, iclass 12, count 0 2006.258.01:17:13.17#ibcon#enter sib2, iclass 12, count 0 2006.258.01:17:13.17#ibcon#flushed, iclass 12, count 0 2006.258.01:17:13.17#ibcon#about to write, iclass 12, count 0 2006.258.01:17:13.17#ibcon#wrote, iclass 12, count 0 2006.258.01:17:13.17#ibcon#about to read 3, iclass 12, count 0 2006.258.01:17:13.19#ibcon#read 3, iclass 12, count 0 2006.258.01:17:13.19#ibcon#about to read 4, iclass 12, count 0 2006.258.01:17:13.19#ibcon#read 4, iclass 12, count 0 2006.258.01:17:13.19#ibcon#about to read 5, iclass 12, count 0 2006.258.01:17:13.19#ibcon#read 5, iclass 12, count 0 2006.258.01:17:13.19#ibcon#about to read 6, iclass 12, count 0 2006.258.01:17:13.19#ibcon#read 6, iclass 12, count 0 2006.258.01:17:13.19#ibcon#end of sib2, iclass 12, count 0 2006.258.01:17:13.19#ibcon#*mode == 0, iclass 12, count 0 2006.258.01:17:13.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.01:17:13.19#ibcon#[27=USB\r\n] 2006.258.01:17:13.19#ibcon#*before write, iclass 12, count 0 2006.258.01:17:13.19#ibcon#enter sib2, iclass 12, count 0 2006.258.01:17:13.19#ibcon#flushed, iclass 12, count 0 2006.258.01:17:13.19#ibcon#about to write, iclass 12, count 0 2006.258.01:17:13.19#ibcon#wrote, iclass 12, count 0 2006.258.01:17:13.19#ibcon#about to read 3, iclass 12, count 0 2006.258.01:17:13.22#ibcon#read 3, iclass 12, count 0 2006.258.01:17:13.22#ibcon#about to read 4, iclass 12, count 0 2006.258.01:17:13.22#ibcon#read 4, iclass 12, count 0 2006.258.01:17:13.22#ibcon#about to read 5, iclass 12, count 0 2006.258.01:17:13.22#ibcon#read 5, iclass 12, count 0 2006.258.01:17:13.22#ibcon#about to read 6, iclass 12, count 0 2006.258.01:17:13.22#ibcon#read 6, iclass 12, count 0 2006.258.01:17:13.22#ibcon#end of sib2, iclass 12, count 0 2006.258.01:17:13.22#ibcon#*after write, iclass 12, count 0 2006.258.01:17:13.22#ibcon#*before return 0, iclass 12, count 0 2006.258.01:17:13.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:17:13.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:17:13.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.01:17:13.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.01:17:13.22$vck44/vblo=2,634.99 2006.258.01:17:13.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.01:17:13.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.01:17:13.22#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:13.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:13.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:13.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:13.22#ibcon#enter wrdev, iclass 14, count 0 2006.258.01:17:13.22#ibcon#first serial, iclass 14, count 0 2006.258.01:17:13.22#ibcon#enter sib2, iclass 14, count 0 2006.258.01:17:13.23#ibcon#flushed, iclass 14, count 0 2006.258.01:17:13.23#ibcon#about to write, iclass 14, count 0 2006.258.01:17:13.23#ibcon#wrote, iclass 14, count 0 2006.258.01:17:13.23#ibcon#about to read 3, iclass 14, count 0 2006.258.01:17:13.24#ibcon#read 3, iclass 14, count 0 2006.258.01:17:13.24#ibcon#about to read 4, iclass 14, count 0 2006.258.01:17:13.24#ibcon#read 4, iclass 14, count 0 2006.258.01:17:13.24#ibcon#about to read 5, iclass 14, count 0 2006.258.01:17:13.24#ibcon#read 5, iclass 14, count 0 2006.258.01:17:13.24#ibcon#about to read 6, iclass 14, count 0 2006.258.01:17:13.24#ibcon#read 6, iclass 14, count 0 2006.258.01:17:13.24#ibcon#end of sib2, iclass 14, count 0 2006.258.01:17:13.24#ibcon#*mode == 0, iclass 14, count 0 2006.258.01:17:13.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.01:17:13.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.01:17:13.24#ibcon#*before write, iclass 14, count 0 2006.258.01:17:13.24#ibcon#enter sib2, iclass 14, count 0 2006.258.01:17:13.24#ibcon#flushed, iclass 14, count 0 2006.258.01:17:13.24#ibcon#about to write, iclass 14, count 0 2006.258.01:17:13.24#ibcon#wrote, iclass 14, count 0 2006.258.01:17:13.24#ibcon#about to read 3, iclass 14, count 0 2006.258.01:17:13.28#ibcon#read 3, iclass 14, count 0 2006.258.01:17:13.28#ibcon#about to read 4, iclass 14, count 0 2006.258.01:17:13.28#ibcon#read 4, iclass 14, count 0 2006.258.01:17:13.28#ibcon#about to read 5, iclass 14, count 0 2006.258.01:17:13.28#ibcon#read 5, iclass 14, count 0 2006.258.01:17:13.28#ibcon#about to read 6, iclass 14, count 0 2006.258.01:17:13.28#ibcon#read 6, iclass 14, count 0 2006.258.01:17:13.28#ibcon#end of sib2, iclass 14, count 0 2006.258.01:17:13.28#ibcon#*after write, iclass 14, count 0 2006.258.01:17:13.28#ibcon#*before return 0, iclass 14, count 0 2006.258.01:17:13.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:13.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:17:13.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.01:17:13.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.01:17:13.28$vck44/vb=2,5 2006.258.01:17:13.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.258.01:17:13.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.258.01:17:13.28#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:13.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:13.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:13.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:13.34#ibcon#enter wrdev, iclass 16, count 2 2006.258.01:17:13.34#ibcon#first serial, iclass 16, count 2 2006.258.01:17:13.34#ibcon#enter sib2, iclass 16, count 2 2006.258.01:17:13.34#ibcon#flushed, iclass 16, count 2 2006.258.01:17:13.34#ibcon#about to write, iclass 16, count 2 2006.258.01:17:13.34#ibcon#wrote, iclass 16, count 2 2006.258.01:17:13.34#ibcon#about to read 3, iclass 16, count 2 2006.258.01:17:13.36#ibcon#read 3, iclass 16, count 2 2006.258.01:17:13.36#ibcon#about to read 4, iclass 16, count 2 2006.258.01:17:13.36#ibcon#read 4, iclass 16, count 2 2006.258.01:17:13.36#ibcon#about to read 5, iclass 16, count 2 2006.258.01:17:13.36#ibcon#read 5, iclass 16, count 2 2006.258.01:17:13.36#ibcon#about to read 6, iclass 16, count 2 2006.258.01:17:13.36#ibcon#read 6, iclass 16, count 2 2006.258.01:17:13.36#ibcon#end of sib2, iclass 16, count 2 2006.258.01:17:13.36#ibcon#*mode == 0, iclass 16, count 2 2006.258.01:17:13.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.258.01:17:13.36#ibcon#[27=AT02-05\r\n] 2006.258.01:17:13.36#ibcon#*before write, iclass 16, count 2 2006.258.01:17:13.36#ibcon#enter sib2, iclass 16, count 2 2006.258.01:17:13.36#ibcon#flushed, iclass 16, count 2 2006.258.01:17:13.36#ibcon#about to write, iclass 16, count 2 2006.258.01:17:13.36#ibcon#wrote, iclass 16, count 2 2006.258.01:17:13.36#ibcon#about to read 3, iclass 16, count 2 2006.258.01:17:13.39#ibcon#read 3, iclass 16, count 2 2006.258.01:17:13.39#ibcon#about to read 4, iclass 16, count 2 2006.258.01:17:13.39#ibcon#read 4, iclass 16, count 2 2006.258.01:17:13.39#ibcon#about to read 5, iclass 16, count 2 2006.258.01:17:13.39#ibcon#read 5, iclass 16, count 2 2006.258.01:17:13.39#ibcon#about to read 6, iclass 16, count 2 2006.258.01:17:13.39#ibcon#read 6, iclass 16, count 2 2006.258.01:17:13.39#ibcon#end of sib2, iclass 16, count 2 2006.258.01:17:13.39#ibcon#*after write, iclass 16, count 2 2006.258.01:17:13.39#ibcon#*before return 0, iclass 16, count 2 2006.258.01:17:13.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:13.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:17:13.51#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.258.01:17:13.51#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:13.51#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:13.62#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:13.62#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:13.62#ibcon#enter wrdev, iclass 16, count 0 2006.258.01:17:13.62#ibcon#first serial, iclass 16, count 0 2006.258.01:17:13.62#ibcon#enter sib2, iclass 16, count 0 2006.258.01:17:13.62#ibcon#flushed, iclass 16, count 0 2006.258.01:17:13.62#ibcon#about to write, iclass 16, count 0 2006.258.01:17:13.62#ibcon#wrote, iclass 16, count 0 2006.258.01:17:13.62#ibcon#about to read 3, iclass 16, count 0 2006.258.01:17:13.64#ibcon#read 3, iclass 16, count 0 2006.258.01:17:13.64#ibcon#about to read 4, iclass 16, count 0 2006.258.01:17:13.64#ibcon#read 4, iclass 16, count 0 2006.258.01:17:13.64#ibcon#about to read 5, iclass 16, count 0 2006.258.01:17:13.64#ibcon#read 5, iclass 16, count 0 2006.258.01:17:13.64#ibcon#about to read 6, iclass 16, count 0 2006.258.01:17:13.64#ibcon#read 6, iclass 16, count 0 2006.258.01:17:13.64#ibcon#end of sib2, iclass 16, count 0 2006.258.01:17:13.64#ibcon#*mode == 0, iclass 16, count 0 2006.258.01:17:13.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.01:17:13.64#ibcon#[27=USB\r\n] 2006.258.01:17:13.64#ibcon#*before write, iclass 16, count 0 2006.258.01:17:13.64#ibcon#enter sib2, iclass 16, count 0 2006.258.01:17:13.64#ibcon#flushed, iclass 16, count 0 2006.258.01:17:13.64#ibcon#about to write, iclass 16, count 0 2006.258.01:17:13.64#ibcon#wrote, iclass 16, count 0 2006.258.01:17:13.64#ibcon#about to read 3, iclass 16, count 0 2006.258.01:17:13.67#ibcon#read 3, iclass 16, count 0 2006.258.01:17:13.67#ibcon#about to read 4, iclass 16, count 0 2006.258.01:17:13.67#ibcon#read 4, iclass 16, count 0 2006.258.01:17:13.67#ibcon#about to read 5, iclass 16, count 0 2006.258.01:17:13.67#ibcon#read 5, iclass 16, count 0 2006.258.01:17:13.67#ibcon#about to read 6, iclass 16, count 0 2006.258.01:17:13.67#ibcon#read 6, iclass 16, count 0 2006.258.01:17:13.67#ibcon#end of sib2, iclass 16, count 0 2006.258.01:17:13.67#ibcon#*after write, iclass 16, count 0 2006.258.01:17:13.67#ibcon#*before return 0, iclass 16, count 0 2006.258.01:17:13.67#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:13.67#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:17:13.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.01:17:13.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.01:17:13.67$vck44/vblo=3,649.99 2006.258.01:17:13.67#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.01:17:13.67#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.01:17:13.67#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:13.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:13.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:13.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:13.68#ibcon#enter wrdev, iclass 18, count 0 2006.258.01:17:13.68#ibcon#first serial, iclass 18, count 0 2006.258.01:17:13.68#ibcon#enter sib2, iclass 18, count 0 2006.258.01:17:13.68#ibcon#flushed, iclass 18, count 0 2006.258.01:17:13.68#ibcon#about to write, iclass 18, count 0 2006.258.01:17:13.68#ibcon#wrote, iclass 18, count 0 2006.258.01:17:13.68#ibcon#about to read 3, iclass 18, count 0 2006.258.01:17:13.69#ibcon#read 3, iclass 18, count 0 2006.258.01:17:13.69#ibcon#about to read 4, iclass 18, count 0 2006.258.01:17:13.69#ibcon#read 4, iclass 18, count 0 2006.258.01:17:13.69#ibcon#about to read 5, iclass 18, count 0 2006.258.01:17:13.69#ibcon#read 5, iclass 18, count 0 2006.258.01:17:13.69#ibcon#about to read 6, iclass 18, count 0 2006.258.01:17:13.69#ibcon#read 6, iclass 18, count 0 2006.258.01:17:13.69#ibcon#end of sib2, iclass 18, count 0 2006.258.01:17:13.69#ibcon#*mode == 0, iclass 18, count 0 2006.258.01:17:13.69#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.01:17:13.69#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.01:17:13.69#ibcon#*before write, iclass 18, count 0 2006.258.01:17:13.69#ibcon#enter sib2, iclass 18, count 0 2006.258.01:17:13.69#ibcon#flushed, iclass 18, count 0 2006.258.01:17:13.69#ibcon#about to write, iclass 18, count 0 2006.258.01:17:13.69#ibcon#wrote, iclass 18, count 0 2006.258.01:17:13.69#ibcon#about to read 3, iclass 18, count 0 2006.258.01:17:13.73#ibcon#read 3, iclass 18, count 0 2006.258.01:17:13.73#ibcon#about to read 4, iclass 18, count 0 2006.258.01:17:13.73#ibcon#read 4, iclass 18, count 0 2006.258.01:17:13.73#ibcon#about to read 5, iclass 18, count 0 2006.258.01:17:13.73#ibcon#read 5, iclass 18, count 0 2006.258.01:17:13.73#ibcon#about to read 6, iclass 18, count 0 2006.258.01:17:13.73#ibcon#read 6, iclass 18, count 0 2006.258.01:17:13.73#ibcon#end of sib2, iclass 18, count 0 2006.258.01:17:13.73#ibcon#*after write, iclass 18, count 0 2006.258.01:17:13.73#ibcon#*before return 0, iclass 18, count 0 2006.258.01:17:13.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:13.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:17:13.73#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.01:17:13.73#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.01:17:13.73$vck44/vb=3,4 2006.258.01:17:13.73#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.01:17:13.73#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.01:17:13.73#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:13.73#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:13.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:13.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:13.79#ibcon#enter wrdev, iclass 20, count 2 2006.258.01:17:13.79#ibcon#first serial, iclass 20, count 2 2006.258.01:17:13.79#ibcon#enter sib2, iclass 20, count 2 2006.258.01:17:13.79#ibcon#flushed, iclass 20, count 2 2006.258.01:17:13.79#ibcon#about to write, iclass 20, count 2 2006.258.01:17:13.79#ibcon#wrote, iclass 20, count 2 2006.258.01:17:13.79#ibcon#about to read 3, iclass 20, count 2 2006.258.01:17:13.81#ibcon#read 3, iclass 20, count 2 2006.258.01:17:13.81#ibcon#about to read 4, iclass 20, count 2 2006.258.01:17:13.81#ibcon#read 4, iclass 20, count 2 2006.258.01:17:13.81#ibcon#about to read 5, iclass 20, count 2 2006.258.01:17:13.81#ibcon#read 5, iclass 20, count 2 2006.258.01:17:13.81#ibcon#about to read 6, iclass 20, count 2 2006.258.01:17:13.81#ibcon#read 6, iclass 20, count 2 2006.258.01:17:13.81#ibcon#end of sib2, iclass 20, count 2 2006.258.01:17:13.81#ibcon#*mode == 0, iclass 20, count 2 2006.258.01:17:13.81#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.01:17:13.81#ibcon#[27=AT03-04\r\n] 2006.258.01:17:13.81#ibcon#*before write, iclass 20, count 2 2006.258.01:17:13.81#ibcon#enter sib2, iclass 20, count 2 2006.258.01:17:13.81#ibcon#flushed, iclass 20, count 2 2006.258.01:17:13.81#ibcon#about to write, iclass 20, count 2 2006.258.01:17:13.81#ibcon#wrote, iclass 20, count 2 2006.258.01:17:13.81#ibcon#about to read 3, iclass 20, count 2 2006.258.01:17:13.84#ibcon#read 3, iclass 20, count 2 2006.258.01:17:13.84#ibcon#about to read 4, iclass 20, count 2 2006.258.01:17:13.84#ibcon#read 4, iclass 20, count 2 2006.258.01:17:13.84#ibcon#about to read 5, iclass 20, count 2 2006.258.01:17:13.84#ibcon#read 5, iclass 20, count 2 2006.258.01:17:13.84#ibcon#about to read 6, iclass 20, count 2 2006.258.01:17:13.84#ibcon#read 6, iclass 20, count 2 2006.258.01:17:13.84#ibcon#end of sib2, iclass 20, count 2 2006.258.01:17:13.84#ibcon#*after write, iclass 20, count 2 2006.258.01:17:13.84#ibcon#*before return 0, iclass 20, count 2 2006.258.01:17:13.84#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:13.84#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:17:13.84#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.01:17:13.84#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:13.84#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:13.96#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:13.96#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:13.96#ibcon#enter wrdev, iclass 20, count 0 2006.258.01:17:13.96#ibcon#first serial, iclass 20, count 0 2006.258.01:17:13.96#ibcon#enter sib2, iclass 20, count 0 2006.258.01:17:13.96#ibcon#flushed, iclass 20, count 0 2006.258.01:17:13.96#ibcon#about to write, iclass 20, count 0 2006.258.01:17:13.96#ibcon#wrote, iclass 20, count 0 2006.258.01:17:13.96#ibcon#about to read 3, iclass 20, count 0 2006.258.01:17:13.98#ibcon#read 3, iclass 20, count 0 2006.258.01:17:13.98#ibcon#about to read 4, iclass 20, count 0 2006.258.01:17:13.98#ibcon#read 4, iclass 20, count 0 2006.258.01:17:13.98#ibcon#about to read 5, iclass 20, count 0 2006.258.01:17:13.98#ibcon#read 5, iclass 20, count 0 2006.258.01:17:13.98#ibcon#about to read 6, iclass 20, count 0 2006.258.01:17:13.98#ibcon#read 6, iclass 20, count 0 2006.258.01:17:13.98#ibcon#end of sib2, iclass 20, count 0 2006.258.01:17:13.98#ibcon#*mode == 0, iclass 20, count 0 2006.258.01:17:13.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.01:17:13.98#ibcon#[27=USB\r\n] 2006.258.01:17:13.98#ibcon#*before write, iclass 20, count 0 2006.258.01:17:13.98#ibcon#enter sib2, iclass 20, count 0 2006.258.01:17:13.98#ibcon#flushed, iclass 20, count 0 2006.258.01:17:13.98#ibcon#about to write, iclass 20, count 0 2006.258.01:17:13.98#ibcon#wrote, iclass 20, count 0 2006.258.01:17:13.98#ibcon#about to read 3, iclass 20, count 0 2006.258.01:17:14.01#ibcon#read 3, iclass 20, count 0 2006.258.01:17:14.01#ibcon#about to read 4, iclass 20, count 0 2006.258.01:17:14.01#ibcon#read 4, iclass 20, count 0 2006.258.01:17:14.01#ibcon#about to read 5, iclass 20, count 0 2006.258.01:17:14.01#ibcon#read 5, iclass 20, count 0 2006.258.01:17:14.01#ibcon#about to read 6, iclass 20, count 0 2006.258.01:17:14.01#ibcon#read 6, iclass 20, count 0 2006.258.01:17:14.01#ibcon#end of sib2, iclass 20, count 0 2006.258.01:17:14.01#ibcon#*after write, iclass 20, count 0 2006.258.01:17:14.01#ibcon#*before return 0, iclass 20, count 0 2006.258.01:17:14.01#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:14.01#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:17:14.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.01:17:14.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.01:17:14.01$vck44/vblo=4,679.99 2006.258.01:17:14.01#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.01:17:14.01#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.01:17:14.01#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:14.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:14.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:14.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:14.01#ibcon#enter wrdev, iclass 22, count 0 2006.258.01:17:14.01#ibcon#first serial, iclass 22, count 0 2006.258.01:17:14.01#ibcon#enter sib2, iclass 22, count 0 2006.258.01:17:14.02#ibcon#flushed, iclass 22, count 0 2006.258.01:17:14.02#ibcon#about to write, iclass 22, count 0 2006.258.01:17:14.02#ibcon#wrote, iclass 22, count 0 2006.258.01:17:14.02#ibcon#about to read 3, iclass 22, count 0 2006.258.01:17:14.03#ibcon#read 3, iclass 22, count 0 2006.258.01:17:14.03#ibcon#about to read 4, iclass 22, count 0 2006.258.01:17:14.03#ibcon#read 4, iclass 22, count 0 2006.258.01:17:14.03#ibcon#about to read 5, iclass 22, count 0 2006.258.01:17:14.03#ibcon#read 5, iclass 22, count 0 2006.258.01:17:14.03#ibcon#about to read 6, iclass 22, count 0 2006.258.01:17:14.03#ibcon#read 6, iclass 22, count 0 2006.258.01:17:14.03#ibcon#end of sib2, iclass 22, count 0 2006.258.01:17:14.03#ibcon#*mode == 0, iclass 22, count 0 2006.258.01:17:14.03#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.01:17:14.03#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.01:17:14.03#ibcon#*before write, iclass 22, count 0 2006.258.01:17:14.03#ibcon#enter sib2, iclass 22, count 0 2006.258.01:17:14.03#ibcon#flushed, iclass 22, count 0 2006.258.01:17:14.03#ibcon#about to write, iclass 22, count 0 2006.258.01:17:14.03#ibcon#wrote, iclass 22, count 0 2006.258.01:17:14.03#ibcon#about to read 3, iclass 22, count 0 2006.258.01:17:14.07#ibcon#read 3, iclass 22, count 0 2006.258.01:17:14.07#ibcon#about to read 4, iclass 22, count 0 2006.258.01:17:14.07#ibcon#read 4, iclass 22, count 0 2006.258.01:17:14.07#ibcon#about to read 5, iclass 22, count 0 2006.258.01:17:14.07#ibcon#read 5, iclass 22, count 0 2006.258.01:17:14.07#ibcon#about to read 6, iclass 22, count 0 2006.258.01:17:14.07#ibcon#read 6, iclass 22, count 0 2006.258.01:17:14.07#ibcon#end of sib2, iclass 22, count 0 2006.258.01:17:14.07#ibcon#*after write, iclass 22, count 0 2006.258.01:17:14.07#ibcon#*before return 0, iclass 22, count 0 2006.258.01:17:14.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:14.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:17:14.07#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.01:17:14.07#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.01:17:14.07$vck44/vb=4,5 2006.258.01:17:14.07#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.01:17:14.07#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.01:17:14.07#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:14.07#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:14.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:14.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:14.13#ibcon#enter wrdev, iclass 24, count 2 2006.258.01:17:14.13#ibcon#first serial, iclass 24, count 2 2006.258.01:17:14.13#ibcon#enter sib2, iclass 24, count 2 2006.258.01:17:14.13#ibcon#flushed, iclass 24, count 2 2006.258.01:17:14.13#ibcon#about to write, iclass 24, count 2 2006.258.01:17:14.13#ibcon#wrote, iclass 24, count 2 2006.258.01:17:14.13#ibcon#about to read 3, iclass 24, count 2 2006.258.01:17:14.15#ibcon#read 3, iclass 24, count 2 2006.258.01:17:14.15#ibcon#about to read 4, iclass 24, count 2 2006.258.01:17:14.15#ibcon#read 4, iclass 24, count 2 2006.258.01:17:14.15#ibcon#about to read 5, iclass 24, count 2 2006.258.01:17:14.15#ibcon#read 5, iclass 24, count 2 2006.258.01:17:14.15#ibcon#about to read 6, iclass 24, count 2 2006.258.01:17:14.15#ibcon#read 6, iclass 24, count 2 2006.258.01:17:14.15#ibcon#end of sib2, iclass 24, count 2 2006.258.01:17:14.15#ibcon#*mode == 0, iclass 24, count 2 2006.258.01:17:14.15#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.01:17:14.15#ibcon#[27=AT04-05\r\n] 2006.258.01:17:14.15#ibcon#*before write, iclass 24, count 2 2006.258.01:17:14.15#ibcon#enter sib2, iclass 24, count 2 2006.258.01:17:14.15#ibcon#flushed, iclass 24, count 2 2006.258.01:17:14.15#ibcon#about to write, iclass 24, count 2 2006.258.01:17:14.15#ibcon#wrote, iclass 24, count 2 2006.258.01:17:14.15#ibcon#about to read 3, iclass 24, count 2 2006.258.01:17:14.18#ibcon#read 3, iclass 24, count 2 2006.258.01:17:14.18#ibcon#about to read 4, iclass 24, count 2 2006.258.01:17:14.18#ibcon#read 4, iclass 24, count 2 2006.258.01:17:14.18#ibcon#about to read 5, iclass 24, count 2 2006.258.01:17:14.18#ibcon#read 5, iclass 24, count 2 2006.258.01:17:14.18#ibcon#about to read 6, iclass 24, count 2 2006.258.01:17:14.18#ibcon#read 6, iclass 24, count 2 2006.258.01:17:14.18#ibcon#end of sib2, iclass 24, count 2 2006.258.01:17:14.18#ibcon#*after write, iclass 24, count 2 2006.258.01:17:14.18#ibcon#*before return 0, iclass 24, count 2 2006.258.01:17:14.18#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:14.18#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:17:14.18#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.01:17:14.18#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:14.18#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:14.30#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:14.30#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:14.30#ibcon#enter wrdev, iclass 24, count 0 2006.258.01:17:14.30#ibcon#first serial, iclass 24, count 0 2006.258.01:17:14.30#ibcon#enter sib2, iclass 24, count 0 2006.258.01:17:14.30#ibcon#flushed, iclass 24, count 0 2006.258.01:17:14.30#ibcon#about to write, iclass 24, count 0 2006.258.01:17:14.30#ibcon#wrote, iclass 24, count 0 2006.258.01:17:14.30#ibcon#about to read 3, iclass 24, count 0 2006.258.01:17:14.32#ibcon#read 3, iclass 24, count 0 2006.258.01:17:14.32#ibcon#about to read 4, iclass 24, count 0 2006.258.01:17:14.32#ibcon#read 4, iclass 24, count 0 2006.258.01:17:14.32#ibcon#about to read 5, iclass 24, count 0 2006.258.01:17:14.32#ibcon#read 5, iclass 24, count 0 2006.258.01:17:14.32#ibcon#about to read 6, iclass 24, count 0 2006.258.01:17:14.32#ibcon#read 6, iclass 24, count 0 2006.258.01:17:14.32#ibcon#end of sib2, iclass 24, count 0 2006.258.01:17:14.32#ibcon#*mode == 0, iclass 24, count 0 2006.258.01:17:14.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.01:17:14.32#ibcon#[27=USB\r\n] 2006.258.01:17:14.32#ibcon#*before write, iclass 24, count 0 2006.258.01:17:14.32#ibcon#enter sib2, iclass 24, count 0 2006.258.01:17:14.32#ibcon#flushed, iclass 24, count 0 2006.258.01:17:14.32#ibcon#about to write, iclass 24, count 0 2006.258.01:17:14.32#ibcon#wrote, iclass 24, count 0 2006.258.01:17:14.32#ibcon#about to read 3, iclass 24, count 0 2006.258.01:17:14.35#ibcon#read 3, iclass 24, count 0 2006.258.01:17:14.35#ibcon#about to read 4, iclass 24, count 0 2006.258.01:17:14.35#ibcon#read 4, iclass 24, count 0 2006.258.01:17:14.35#ibcon#about to read 5, iclass 24, count 0 2006.258.01:17:14.35#ibcon#read 5, iclass 24, count 0 2006.258.01:17:14.35#ibcon#about to read 6, iclass 24, count 0 2006.258.01:17:14.35#ibcon#read 6, iclass 24, count 0 2006.258.01:17:14.35#ibcon#end of sib2, iclass 24, count 0 2006.258.01:17:14.35#ibcon#*after write, iclass 24, count 0 2006.258.01:17:14.35#ibcon#*before return 0, iclass 24, count 0 2006.258.01:17:14.35#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:14.35#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:17:14.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.01:17:14.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.01:17:14.35$vck44/vblo=5,709.99 2006.258.01:17:14.35#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.01:17:14.35#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.01:17:14.35#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:14.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:14.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:14.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:14.36#ibcon#enter wrdev, iclass 26, count 0 2006.258.01:17:14.36#ibcon#first serial, iclass 26, count 0 2006.258.01:17:14.36#ibcon#enter sib2, iclass 26, count 0 2006.258.01:17:14.36#ibcon#flushed, iclass 26, count 0 2006.258.01:17:14.36#ibcon#about to write, iclass 26, count 0 2006.258.01:17:14.36#ibcon#wrote, iclass 26, count 0 2006.258.01:17:14.36#ibcon#about to read 3, iclass 26, count 0 2006.258.01:17:14.37#ibcon#read 3, iclass 26, count 0 2006.258.01:17:14.37#ibcon#about to read 4, iclass 26, count 0 2006.258.01:17:14.37#ibcon#read 4, iclass 26, count 0 2006.258.01:17:14.37#ibcon#about to read 5, iclass 26, count 0 2006.258.01:17:14.37#ibcon#read 5, iclass 26, count 0 2006.258.01:17:14.37#ibcon#about to read 6, iclass 26, count 0 2006.258.01:17:14.37#ibcon#read 6, iclass 26, count 0 2006.258.01:17:14.37#ibcon#end of sib2, iclass 26, count 0 2006.258.01:17:14.37#ibcon#*mode == 0, iclass 26, count 0 2006.258.01:17:14.37#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.01:17:14.37#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.01:17:14.37#ibcon#*before write, iclass 26, count 0 2006.258.01:17:14.37#ibcon#enter sib2, iclass 26, count 0 2006.258.01:17:14.37#ibcon#flushed, iclass 26, count 0 2006.258.01:17:14.37#ibcon#about to write, iclass 26, count 0 2006.258.01:17:14.37#ibcon#wrote, iclass 26, count 0 2006.258.01:17:14.37#ibcon#about to read 3, iclass 26, count 0 2006.258.01:17:14.41#ibcon#read 3, iclass 26, count 0 2006.258.01:17:14.41#ibcon#about to read 4, iclass 26, count 0 2006.258.01:17:14.41#ibcon#read 4, iclass 26, count 0 2006.258.01:17:14.41#ibcon#about to read 5, iclass 26, count 0 2006.258.01:17:14.41#ibcon#read 5, iclass 26, count 0 2006.258.01:17:14.41#ibcon#about to read 6, iclass 26, count 0 2006.258.01:17:14.41#ibcon#read 6, iclass 26, count 0 2006.258.01:17:14.41#ibcon#end of sib2, iclass 26, count 0 2006.258.01:17:14.41#ibcon#*after write, iclass 26, count 0 2006.258.01:17:14.41#ibcon#*before return 0, iclass 26, count 0 2006.258.01:17:14.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:14.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:17:14.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.01:17:14.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.01:17:14.41$vck44/vb=5,4 2006.258.01:17:14.41#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.01:17:14.41#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.01:17:14.42#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:14.42#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:14.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:14.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:14.46#ibcon#enter wrdev, iclass 28, count 2 2006.258.01:17:14.46#ibcon#first serial, iclass 28, count 2 2006.258.01:17:14.46#ibcon#enter sib2, iclass 28, count 2 2006.258.01:17:14.46#ibcon#flushed, iclass 28, count 2 2006.258.01:17:14.46#ibcon#about to write, iclass 28, count 2 2006.258.01:17:14.46#ibcon#wrote, iclass 28, count 2 2006.258.01:17:14.46#ibcon#about to read 3, iclass 28, count 2 2006.258.01:17:14.48#ibcon#read 3, iclass 28, count 2 2006.258.01:17:14.48#ibcon#about to read 4, iclass 28, count 2 2006.258.01:17:14.48#ibcon#read 4, iclass 28, count 2 2006.258.01:17:14.48#ibcon#about to read 5, iclass 28, count 2 2006.258.01:17:14.48#ibcon#read 5, iclass 28, count 2 2006.258.01:17:14.48#ibcon#about to read 6, iclass 28, count 2 2006.258.01:17:14.48#ibcon#read 6, iclass 28, count 2 2006.258.01:17:14.48#ibcon#end of sib2, iclass 28, count 2 2006.258.01:17:14.48#ibcon#*mode == 0, iclass 28, count 2 2006.258.01:17:14.48#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.01:17:14.48#ibcon#[27=AT05-04\r\n] 2006.258.01:17:14.48#ibcon#*before write, iclass 28, count 2 2006.258.01:17:14.48#ibcon#enter sib2, iclass 28, count 2 2006.258.01:17:14.48#ibcon#flushed, iclass 28, count 2 2006.258.01:17:14.48#ibcon#about to write, iclass 28, count 2 2006.258.01:17:14.48#ibcon#wrote, iclass 28, count 2 2006.258.01:17:14.48#ibcon#about to read 3, iclass 28, count 2 2006.258.01:17:14.51#ibcon#read 3, iclass 28, count 2 2006.258.01:17:14.57#ibcon#about to read 4, iclass 28, count 2 2006.258.01:17:14.57#ibcon#read 4, iclass 28, count 2 2006.258.01:17:14.57#ibcon#about to read 5, iclass 28, count 2 2006.258.01:17:14.57#ibcon#read 5, iclass 28, count 2 2006.258.01:17:14.57#ibcon#about to read 6, iclass 28, count 2 2006.258.01:17:14.57#ibcon#read 6, iclass 28, count 2 2006.258.01:17:14.57#ibcon#end of sib2, iclass 28, count 2 2006.258.01:17:14.57#ibcon#*after write, iclass 28, count 2 2006.258.01:17:14.57#ibcon#*before return 0, iclass 28, count 2 2006.258.01:17:14.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:14.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:17:14.57#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.01:17:14.57#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:14.57#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:14.68#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:14.68#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:14.68#ibcon#enter wrdev, iclass 28, count 0 2006.258.01:17:14.68#ibcon#first serial, iclass 28, count 0 2006.258.01:17:14.68#ibcon#enter sib2, iclass 28, count 0 2006.258.01:17:14.68#ibcon#flushed, iclass 28, count 0 2006.258.01:17:14.68#ibcon#about to write, iclass 28, count 0 2006.258.01:17:14.68#ibcon#wrote, iclass 28, count 0 2006.258.01:17:14.68#ibcon#about to read 3, iclass 28, count 0 2006.258.01:17:14.70#ibcon#read 3, iclass 28, count 0 2006.258.01:17:14.70#ibcon#about to read 4, iclass 28, count 0 2006.258.01:17:14.70#ibcon#read 4, iclass 28, count 0 2006.258.01:17:14.70#ibcon#about to read 5, iclass 28, count 0 2006.258.01:17:14.70#ibcon#read 5, iclass 28, count 0 2006.258.01:17:14.70#ibcon#about to read 6, iclass 28, count 0 2006.258.01:17:14.70#ibcon#read 6, iclass 28, count 0 2006.258.01:17:14.70#ibcon#end of sib2, iclass 28, count 0 2006.258.01:17:14.70#ibcon#*mode == 0, iclass 28, count 0 2006.258.01:17:14.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.01:17:14.70#ibcon#[27=USB\r\n] 2006.258.01:17:14.70#ibcon#*before write, iclass 28, count 0 2006.258.01:17:14.70#ibcon#enter sib2, iclass 28, count 0 2006.258.01:17:14.70#ibcon#flushed, iclass 28, count 0 2006.258.01:17:14.70#ibcon#about to write, iclass 28, count 0 2006.258.01:17:14.70#ibcon#wrote, iclass 28, count 0 2006.258.01:17:14.70#ibcon#about to read 3, iclass 28, count 0 2006.258.01:17:14.73#ibcon#read 3, iclass 28, count 0 2006.258.01:17:14.73#ibcon#about to read 4, iclass 28, count 0 2006.258.01:17:14.73#ibcon#read 4, iclass 28, count 0 2006.258.01:17:14.73#ibcon#about to read 5, iclass 28, count 0 2006.258.01:17:14.73#ibcon#read 5, iclass 28, count 0 2006.258.01:17:14.73#ibcon#about to read 6, iclass 28, count 0 2006.258.01:17:14.73#ibcon#read 6, iclass 28, count 0 2006.258.01:17:14.73#ibcon#end of sib2, iclass 28, count 0 2006.258.01:17:14.73#ibcon#*after write, iclass 28, count 0 2006.258.01:17:14.73#ibcon#*before return 0, iclass 28, count 0 2006.258.01:17:14.73#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:14.73#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:17:14.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.01:17:14.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.01:17:14.73$vck44/vblo=6,719.99 2006.258.01:17:14.73#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.01:17:14.73#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.01:17:14.73#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:14.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:14.73#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:14.73#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:14.74#ibcon#enter wrdev, iclass 30, count 0 2006.258.01:17:14.74#ibcon#first serial, iclass 30, count 0 2006.258.01:17:14.74#ibcon#enter sib2, iclass 30, count 0 2006.258.01:17:14.74#ibcon#flushed, iclass 30, count 0 2006.258.01:17:14.74#ibcon#about to write, iclass 30, count 0 2006.258.01:17:14.74#ibcon#wrote, iclass 30, count 0 2006.258.01:17:14.74#ibcon#about to read 3, iclass 30, count 0 2006.258.01:17:14.75#ibcon#read 3, iclass 30, count 0 2006.258.01:17:14.75#ibcon#about to read 4, iclass 30, count 0 2006.258.01:17:14.75#ibcon#read 4, iclass 30, count 0 2006.258.01:17:14.75#ibcon#about to read 5, iclass 30, count 0 2006.258.01:17:14.75#ibcon#read 5, iclass 30, count 0 2006.258.01:17:14.75#ibcon#about to read 6, iclass 30, count 0 2006.258.01:17:14.75#ibcon#read 6, iclass 30, count 0 2006.258.01:17:14.75#ibcon#end of sib2, iclass 30, count 0 2006.258.01:17:14.75#ibcon#*mode == 0, iclass 30, count 0 2006.258.01:17:14.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.01:17:14.75#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.01:17:14.75#ibcon#*before write, iclass 30, count 0 2006.258.01:17:14.75#ibcon#enter sib2, iclass 30, count 0 2006.258.01:17:14.75#ibcon#flushed, iclass 30, count 0 2006.258.01:17:14.75#ibcon#about to write, iclass 30, count 0 2006.258.01:17:14.75#ibcon#wrote, iclass 30, count 0 2006.258.01:17:14.75#ibcon#about to read 3, iclass 30, count 0 2006.258.01:17:14.79#ibcon#read 3, iclass 30, count 0 2006.258.01:17:14.79#ibcon#about to read 4, iclass 30, count 0 2006.258.01:17:14.79#ibcon#read 4, iclass 30, count 0 2006.258.01:17:14.79#ibcon#about to read 5, iclass 30, count 0 2006.258.01:17:14.79#ibcon#read 5, iclass 30, count 0 2006.258.01:17:14.79#ibcon#about to read 6, iclass 30, count 0 2006.258.01:17:14.79#ibcon#read 6, iclass 30, count 0 2006.258.01:17:14.79#ibcon#end of sib2, iclass 30, count 0 2006.258.01:17:14.79#ibcon#*after write, iclass 30, count 0 2006.258.01:17:14.79#ibcon#*before return 0, iclass 30, count 0 2006.258.01:17:14.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:14.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:17:14.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.01:17:14.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.01:17:14.79$vck44/vb=6,4 2006.258.01:17:14.79#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.258.01:17:14.79#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.258.01:17:14.79#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:14.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:14.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:14.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:14.85#ibcon#enter wrdev, iclass 32, count 2 2006.258.01:17:14.85#ibcon#first serial, iclass 32, count 2 2006.258.01:17:14.85#ibcon#enter sib2, iclass 32, count 2 2006.258.01:17:14.85#ibcon#flushed, iclass 32, count 2 2006.258.01:17:14.85#ibcon#about to write, iclass 32, count 2 2006.258.01:17:14.85#ibcon#wrote, iclass 32, count 2 2006.258.01:17:14.85#ibcon#about to read 3, iclass 32, count 2 2006.258.01:17:14.87#ibcon#read 3, iclass 32, count 2 2006.258.01:17:14.87#ibcon#about to read 4, iclass 32, count 2 2006.258.01:17:14.87#ibcon#read 4, iclass 32, count 2 2006.258.01:17:14.87#ibcon#about to read 5, iclass 32, count 2 2006.258.01:17:14.87#ibcon#read 5, iclass 32, count 2 2006.258.01:17:14.87#ibcon#about to read 6, iclass 32, count 2 2006.258.01:17:14.87#ibcon#read 6, iclass 32, count 2 2006.258.01:17:14.87#ibcon#end of sib2, iclass 32, count 2 2006.258.01:17:14.87#ibcon#*mode == 0, iclass 32, count 2 2006.258.01:17:14.87#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.258.01:17:14.87#ibcon#[27=AT06-04\r\n] 2006.258.01:17:14.87#ibcon#*before write, iclass 32, count 2 2006.258.01:17:14.87#ibcon#enter sib2, iclass 32, count 2 2006.258.01:17:14.87#ibcon#flushed, iclass 32, count 2 2006.258.01:17:14.87#ibcon#about to write, iclass 32, count 2 2006.258.01:17:14.87#ibcon#wrote, iclass 32, count 2 2006.258.01:17:14.87#ibcon#about to read 3, iclass 32, count 2 2006.258.01:17:14.90#ibcon#read 3, iclass 32, count 2 2006.258.01:17:14.90#ibcon#about to read 4, iclass 32, count 2 2006.258.01:17:14.90#ibcon#read 4, iclass 32, count 2 2006.258.01:17:14.90#ibcon#about to read 5, iclass 32, count 2 2006.258.01:17:14.90#ibcon#read 5, iclass 32, count 2 2006.258.01:17:14.90#ibcon#about to read 6, iclass 32, count 2 2006.258.01:17:14.90#ibcon#read 6, iclass 32, count 2 2006.258.01:17:14.90#ibcon#end of sib2, iclass 32, count 2 2006.258.01:17:14.90#ibcon#*after write, iclass 32, count 2 2006.258.01:17:14.90#ibcon#*before return 0, iclass 32, count 2 2006.258.01:17:14.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:14.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:17:14.90#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.258.01:17:14.90#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:14.90#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:15.02#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:15.02#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:15.02#ibcon#enter wrdev, iclass 32, count 0 2006.258.01:17:15.02#ibcon#first serial, iclass 32, count 0 2006.258.01:17:15.02#ibcon#enter sib2, iclass 32, count 0 2006.258.01:17:15.02#ibcon#flushed, iclass 32, count 0 2006.258.01:17:15.02#ibcon#about to write, iclass 32, count 0 2006.258.01:17:15.02#ibcon#wrote, iclass 32, count 0 2006.258.01:17:15.02#ibcon#about to read 3, iclass 32, count 0 2006.258.01:17:15.04#ibcon#read 3, iclass 32, count 0 2006.258.01:17:15.04#ibcon#about to read 4, iclass 32, count 0 2006.258.01:17:15.04#ibcon#read 4, iclass 32, count 0 2006.258.01:17:15.04#ibcon#about to read 5, iclass 32, count 0 2006.258.01:17:15.04#ibcon#read 5, iclass 32, count 0 2006.258.01:17:15.04#ibcon#about to read 6, iclass 32, count 0 2006.258.01:17:15.04#ibcon#read 6, iclass 32, count 0 2006.258.01:17:15.04#ibcon#end of sib2, iclass 32, count 0 2006.258.01:17:15.04#ibcon#*mode == 0, iclass 32, count 0 2006.258.01:17:15.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.01:17:15.04#ibcon#[27=USB\r\n] 2006.258.01:17:15.04#ibcon#*before write, iclass 32, count 0 2006.258.01:17:15.04#ibcon#enter sib2, iclass 32, count 0 2006.258.01:17:15.04#ibcon#flushed, iclass 32, count 0 2006.258.01:17:15.04#ibcon#about to write, iclass 32, count 0 2006.258.01:17:15.04#ibcon#wrote, iclass 32, count 0 2006.258.01:17:15.04#ibcon#about to read 3, iclass 32, count 0 2006.258.01:17:15.07#ibcon#read 3, iclass 32, count 0 2006.258.01:17:15.07#ibcon#about to read 4, iclass 32, count 0 2006.258.01:17:15.07#ibcon#read 4, iclass 32, count 0 2006.258.01:17:15.07#ibcon#about to read 5, iclass 32, count 0 2006.258.01:17:15.07#ibcon#read 5, iclass 32, count 0 2006.258.01:17:15.07#ibcon#about to read 6, iclass 32, count 0 2006.258.01:17:15.07#ibcon#read 6, iclass 32, count 0 2006.258.01:17:15.07#ibcon#end of sib2, iclass 32, count 0 2006.258.01:17:15.07#ibcon#*after write, iclass 32, count 0 2006.258.01:17:15.07#ibcon#*before return 0, iclass 32, count 0 2006.258.01:17:15.07#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:15.07#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:17:15.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.01:17:15.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.01:17:15.07$vck44/vblo=7,734.99 2006.258.01:17:15.07#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.01:17:15.07#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.01:17:15.07#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:15.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:15.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:15.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:15.07#ibcon#enter wrdev, iclass 34, count 0 2006.258.01:17:15.08#ibcon#first serial, iclass 34, count 0 2006.258.01:17:15.08#ibcon#enter sib2, iclass 34, count 0 2006.258.01:17:15.08#ibcon#flushed, iclass 34, count 0 2006.258.01:17:15.08#ibcon#about to write, iclass 34, count 0 2006.258.01:17:15.08#ibcon#wrote, iclass 34, count 0 2006.258.01:17:15.08#ibcon#about to read 3, iclass 34, count 0 2006.258.01:17:15.09#ibcon#read 3, iclass 34, count 0 2006.258.01:17:15.09#ibcon#about to read 4, iclass 34, count 0 2006.258.01:17:15.09#ibcon#read 4, iclass 34, count 0 2006.258.01:17:15.09#ibcon#about to read 5, iclass 34, count 0 2006.258.01:17:15.09#ibcon#read 5, iclass 34, count 0 2006.258.01:17:15.09#ibcon#about to read 6, iclass 34, count 0 2006.258.01:17:15.09#ibcon#read 6, iclass 34, count 0 2006.258.01:17:15.09#ibcon#end of sib2, iclass 34, count 0 2006.258.01:17:15.09#ibcon#*mode == 0, iclass 34, count 0 2006.258.01:17:15.09#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.01:17:15.09#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.01:17:15.09#ibcon#*before write, iclass 34, count 0 2006.258.01:17:15.09#ibcon#enter sib2, iclass 34, count 0 2006.258.01:17:15.09#ibcon#flushed, iclass 34, count 0 2006.258.01:17:15.09#ibcon#about to write, iclass 34, count 0 2006.258.01:17:15.09#ibcon#wrote, iclass 34, count 0 2006.258.01:17:15.09#ibcon#about to read 3, iclass 34, count 0 2006.258.01:17:15.13#ibcon#read 3, iclass 34, count 0 2006.258.01:17:15.13#ibcon#about to read 4, iclass 34, count 0 2006.258.01:17:15.13#ibcon#read 4, iclass 34, count 0 2006.258.01:17:15.13#ibcon#about to read 5, iclass 34, count 0 2006.258.01:17:15.13#ibcon#read 5, iclass 34, count 0 2006.258.01:17:15.13#ibcon#about to read 6, iclass 34, count 0 2006.258.01:17:15.13#ibcon#read 6, iclass 34, count 0 2006.258.01:17:15.13#ibcon#end of sib2, iclass 34, count 0 2006.258.01:17:15.13#ibcon#*after write, iclass 34, count 0 2006.258.01:17:15.13#ibcon#*before return 0, iclass 34, count 0 2006.258.01:17:15.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:15.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:17:15.13#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.01:17:15.13#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.01:17:15.13$vck44/vb=7,4 2006.258.01:17:15.13#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.258.01:17:15.13#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.258.01:17:15.13#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:15.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:15.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:15.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:15.19#ibcon#enter wrdev, iclass 36, count 2 2006.258.01:17:15.19#ibcon#first serial, iclass 36, count 2 2006.258.01:17:15.19#ibcon#enter sib2, iclass 36, count 2 2006.258.01:17:15.19#ibcon#flushed, iclass 36, count 2 2006.258.01:17:15.19#ibcon#about to write, iclass 36, count 2 2006.258.01:17:15.19#ibcon#wrote, iclass 36, count 2 2006.258.01:17:15.19#ibcon#about to read 3, iclass 36, count 2 2006.258.01:17:15.21#ibcon#read 3, iclass 36, count 2 2006.258.01:17:15.21#ibcon#about to read 4, iclass 36, count 2 2006.258.01:17:15.21#ibcon#read 4, iclass 36, count 2 2006.258.01:17:15.21#ibcon#about to read 5, iclass 36, count 2 2006.258.01:17:15.21#ibcon#read 5, iclass 36, count 2 2006.258.01:17:15.21#ibcon#about to read 6, iclass 36, count 2 2006.258.01:17:15.21#ibcon#read 6, iclass 36, count 2 2006.258.01:17:15.21#ibcon#end of sib2, iclass 36, count 2 2006.258.01:17:15.21#ibcon#*mode == 0, iclass 36, count 2 2006.258.01:17:15.21#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.258.01:17:15.21#ibcon#[27=AT07-04\r\n] 2006.258.01:17:15.21#ibcon#*before write, iclass 36, count 2 2006.258.01:17:15.21#ibcon#enter sib2, iclass 36, count 2 2006.258.01:17:15.21#ibcon#flushed, iclass 36, count 2 2006.258.01:17:15.21#ibcon#about to write, iclass 36, count 2 2006.258.01:17:15.21#ibcon#wrote, iclass 36, count 2 2006.258.01:17:15.21#ibcon#about to read 3, iclass 36, count 2 2006.258.01:17:15.24#ibcon#read 3, iclass 36, count 2 2006.258.01:17:15.24#ibcon#about to read 4, iclass 36, count 2 2006.258.01:17:15.24#ibcon#read 4, iclass 36, count 2 2006.258.01:17:15.24#ibcon#about to read 5, iclass 36, count 2 2006.258.01:17:15.24#ibcon#read 5, iclass 36, count 2 2006.258.01:17:15.24#ibcon#about to read 6, iclass 36, count 2 2006.258.01:17:15.24#ibcon#read 6, iclass 36, count 2 2006.258.01:17:15.24#ibcon#end of sib2, iclass 36, count 2 2006.258.01:17:15.24#ibcon#*after write, iclass 36, count 2 2006.258.01:17:15.24#ibcon#*before return 0, iclass 36, count 2 2006.258.01:17:15.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:15.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:17:15.24#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.258.01:17:15.24#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:15.24#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:15.36#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:15.36#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:15.36#ibcon#enter wrdev, iclass 36, count 0 2006.258.01:17:15.36#ibcon#first serial, iclass 36, count 0 2006.258.01:17:15.36#ibcon#enter sib2, iclass 36, count 0 2006.258.01:17:15.36#ibcon#flushed, iclass 36, count 0 2006.258.01:17:15.36#ibcon#about to write, iclass 36, count 0 2006.258.01:17:15.36#ibcon#wrote, iclass 36, count 0 2006.258.01:17:15.36#ibcon#about to read 3, iclass 36, count 0 2006.258.01:17:15.38#ibcon#read 3, iclass 36, count 0 2006.258.01:17:15.38#ibcon#about to read 4, iclass 36, count 0 2006.258.01:17:15.38#ibcon#read 4, iclass 36, count 0 2006.258.01:17:15.38#ibcon#about to read 5, iclass 36, count 0 2006.258.01:17:15.38#ibcon#read 5, iclass 36, count 0 2006.258.01:17:15.38#ibcon#about to read 6, iclass 36, count 0 2006.258.01:17:15.38#ibcon#read 6, iclass 36, count 0 2006.258.01:17:15.38#ibcon#end of sib2, iclass 36, count 0 2006.258.01:17:15.38#ibcon#*mode == 0, iclass 36, count 0 2006.258.01:17:15.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.01:17:15.38#ibcon#[27=USB\r\n] 2006.258.01:17:15.38#ibcon#*before write, iclass 36, count 0 2006.258.01:17:15.38#ibcon#enter sib2, iclass 36, count 0 2006.258.01:17:15.38#ibcon#flushed, iclass 36, count 0 2006.258.01:17:15.38#ibcon#about to write, iclass 36, count 0 2006.258.01:17:15.38#ibcon#wrote, iclass 36, count 0 2006.258.01:17:15.38#ibcon#about to read 3, iclass 36, count 0 2006.258.01:17:15.41#ibcon#read 3, iclass 36, count 0 2006.258.01:17:15.41#ibcon#about to read 4, iclass 36, count 0 2006.258.01:17:15.41#ibcon#read 4, iclass 36, count 0 2006.258.01:17:15.41#ibcon#about to read 5, iclass 36, count 0 2006.258.01:17:15.41#ibcon#read 5, iclass 36, count 0 2006.258.01:17:15.41#ibcon#about to read 6, iclass 36, count 0 2006.258.01:17:15.41#ibcon#read 6, iclass 36, count 0 2006.258.01:17:15.41#ibcon#end of sib2, iclass 36, count 0 2006.258.01:17:15.41#ibcon#*after write, iclass 36, count 0 2006.258.01:17:15.41#ibcon#*before return 0, iclass 36, count 0 2006.258.01:17:15.41#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:15.41#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:17:15.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.01:17:15.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.01:17:15.41$vck44/vblo=8,744.99 2006.258.01:17:15.41#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.01:17:15.42#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.01:17:15.42#ibcon#ireg 17 cls_cnt 0 2006.258.01:17:15.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:15.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:15.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:15.42#ibcon#enter wrdev, iclass 38, count 0 2006.258.01:17:15.42#ibcon#first serial, iclass 38, count 0 2006.258.01:17:15.42#ibcon#enter sib2, iclass 38, count 0 2006.258.01:17:15.42#ibcon#flushed, iclass 38, count 0 2006.258.01:17:15.42#ibcon#about to write, iclass 38, count 0 2006.258.01:17:15.42#ibcon#wrote, iclass 38, count 0 2006.258.01:17:15.42#ibcon#about to read 3, iclass 38, count 0 2006.258.01:17:15.43#ibcon#read 3, iclass 38, count 0 2006.258.01:17:15.43#ibcon#about to read 4, iclass 38, count 0 2006.258.01:17:15.43#ibcon#read 4, iclass 38, count 0 2006.258.01:17:15.43#ibcon#about to read 5, iclass 38, count 0 2006.258.01:17:15.43#ibcon#read 5, iclass 38, count 0 2006.258.01:17:15.43#ibcon#about to read 6, iclass 38, count 0 2006.258.01:17:15.43#ibcon#read 6, iclass 38, count 0 2006.258.01:17:15.43#ibcon#end of sib2, iclass 38, count 0 2006.258.01:17:15.43#ibcon#*mode == 0, iclass 38, count 0 2006.258.01:17:15.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.01:17:15.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.01:17:15.43#ibcon#*before write, iclass 38, count 0 2006.258.01:17:15.43#ibcon#enter sib2, iclass 38, count 0 2006.258.01:17:15.43#ibcon#flushed, iclass 38, count 0 2006.258.01:17:15.43#ibcon#about to write, iclass 38, count 0 2006.258.01:17:15.43#ibcon#wrote, iclass 38, count 0 2006.258.01:17:15.43#ibcon#about to read 3, iclass 38, count 0 2006.258.01:17:15.47#ibcon#read 3, iclass 38, count 0 2006.258.01:17:15.47#ibcon#about to read 4, iclass 38, count 0 2006.258.01:17:15.47#ibcon#read 4, iclass 38, count 0 2006.258.01:17:15.47#ibcon#about to read 5, iclass 38, count 0 2006.258.01:17:15.47#ibcon#read 5, iclass 38, count 0 2006.258.01:17:15.47#ibcon#about to read 6, iclass 38, count 0 2006.258.01:17:15.47#ibcon#read 6, iclass 38, count 0 2006.258.01:17:15.47#ibcon#end of sib2, iclass 38, count 0 2006.258.01:17:15.47#ibcon#*after write, iclass 38, count 0 2006.258.01:17:15.47#ibcon#*before return 0, iclass 38, count 0 2006.258.01:17:15.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:15.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:17:15.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.01:17:15.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.01:17:15.47$vck44/vb=8,4 2006.258.01:17:15.48#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.258.01:17:15.48#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.258.01:17:15.48#ibcon#ireg 11 cls_cnt 2 2006.258.01:17:15.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:15.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:15.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:15.52#ibcon#enter wrdev, iclass 40, count 2 2006.258.01:17:15.52#ibcon#first serial, iclass 40, count 2 2006.258.01:17:15.52#ibcon#enter sib2, iclass 40, count 2 2006.258.01:17:15.52#ibcon#flushed, iclass 40, count 2 2006.258.01:17:15.52#ibcon#about to write, iclass 40, count 2 2006.258.01:17:15.52#ibcon#wrote, iclass 40, count 2 2006.258.01:17:15.52#ibcon#about to read 3, iclass 40, count 2 2006.258.01:17:15.54#ibcon#read 3, iclass 40, count 2 2006.258.01:17:15.54#ibcon#about to read 4, iclass 40, count 2 2006.258.01:17:15.54#ibcon#read 4, iclass 40, count 2 2006.258.01:17:15.54#ibcon#about to read 5, iclass 40, count 2 2006.258.01:17:15.54#ibcon#read 5, iclass 40, count 2 2006.258.01:17:15.54#ibcon#about to read 6, iclass 40, count 2 2006.258.01:17:15.54#ibcon#read 6, iclass 40, count 2 2006.258.01:17:15.54#ibcon#end of sib2, iclass 40, count 2 2006.258.01:17:15.54#ibcon#*mode == 0, iclass 40, count 2 2006.258.01:17:15.54#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.258.01:17:15.54#ibcon#[27=AT08-04\r\n] 2006.258.01:17:15.54#ibcon#*before write, iclass 40, count 2 2006.258.01:17:15.54#ibcon#enter sib2, iclass 40, count 2 2006.258.01:17:15.54#ibcon#flushed, iclass 40, count 2 2006.258.01:17:15.54#ibcon#about to write, iclass 40, count 2 2006.258.01:17:15.54#ibcon#wrote, iclass 40, count 2 2006.258.01:17:15.54#ibcon#about to read 3, iclass 40, count 2 2006.258.01:17:15.57#ibcon#read 3, iclass 40, count 2 2006.258.01:17:15.57#ibcon#about to read 4, iclass 40, count 2 2006.258.01:17:15.57#ibcon#read 4, iclass 40, count 2 2006.258.01:17:15.57#ibcon#about to read 5, iclass 40, count 2 2006.258.01:17:15.57#ibcon#read 5, iclass 40, count 2 2006.258.01:17:15.57#ibcon#about to read 6, iclass 40, count 2 2006.258.01:17:15.57#ibcon#read 6, iclass 40, count 2 2006.258.01:17:15.57#ibcon#end of sib2, iclass 40, count 2 2006.258.01:17:15.57#ibcon#*after write, iclass 40, count 2 2006.258.01:17:15.61#ibcon#*before return 0, iclass 40, count 2 2006.258.01:17:15.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:15.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:17:15.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.258.01:17:15.62#ibcon#ireg 7 cls_cnt 0 2006.258.01:17:15.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:15.72#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:15.72#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:15.72#ibcon#enter wrdev, iclass 40, count 0 2006.258.01:17:15.72#ibcon#first serial, iclass 40, count 0 2006.258.01:17:15.72#ibcon#enter sib2, iclass 40, count 0 2006.258.01:17:15.72#ibcon#flushed, iclass 40, count 0 2006.258.01:17:15.72#ibcon#about to write, iclass 40, count 0 2006.258.01:17:15.72#ibcon#wrote, iclass 40, count 0 2006.258.01:17:15.72#ibcon#about to read 3, iclass 40, count 0 2006.258.01:17:15.74#ibcon#read 3, iclass 40, count 0 2006.258.01:17:15.74#ibcon#about to read 4, iclass 40, count 0 2006.258.01:17:15.74#ibcon#read 4, iclass 40, count 0 2006.258.01:17:15.74#ibcon#about to read 5, iclass 40, count 0 2006.258.01:17:15.74#ibcon#read 5, iclass 40, count 0 2006.258.01:17:15.74#ibcon#about to read 6, iclass 40, count 0 2006.258.01:17:15.74#ibcon#read 6, iclass 40, count 0 2006.258.01:17:15.74#ibcon#end of sib2, iclass 40, count 0 2006.258.01:17:15.74#ibcon#*mode == 0, iclass 40, count 0 2006.258.01:17:15.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.01:17:15.74#ibcon#[27=USB\r\n] 2006.258.01:17:15.74#ibcon#*before write, iclass 40, count 0 2006.258.01:17:15.74#ibcon#enter sib2, iclass 40, count 0 2006.258.01:17:15.74#ibcon#flushed, iclass 40, count 0 2006.258.01:17:15.74#ibcon#about to write, iclass 40, count 0 2006.258.01:17:15.74#ibcon#wrote, iclass 40, count 0 2006.258.01:17:15.74#ibcon#about to read 3, iclass 40, count 0 2006.258.01:17:15.77#ibcon#read 3, iclass 40, count 0 2006.258.01:17:15.77#ibcon#about to read 4, iclass 40, count 0 2006.258.01:17:15.77#ibcon#read 4, iclass 40, count 0 2006.258.01:17:15.77#ibcon#about to read 5, iclass 40, count 0 2006.258.01:17:15.77#ibcon#read 5, iclass 40, count 0 2006.258.01:17:15.77#ibcon#about to read 6, iclass 40, count 0 2006.258.01:17:15.77#ibcon#read 6, iclass 40, count 0 2006.258.01:17:15.77#ibcon#end of sib2, iclass 40, count 0 2006.258.01:17:15.77#ibcon#*after write, iclass 40, count 0 2006.258.01:17:15.77#ibcon#*before return 0, iclass 40, count 0 2006.258.01:17:15.77#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:15.77#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:17:15.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.01:17:15.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.01:17:15.77$vck44/vabw=wide 2006.258.01:17:15.77#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.258.01:17:15.77#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.258.01:17:15.77#ibcon#ireg 8 cls_cnt 0 2006.258.01:17:15.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:15.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:15.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:15.77#ibcon#enter wrdev, iclass 4, count 0 2006.258.01:17:15.77#ibcon#first serial, iclass 4, count 0 2006.258.01:17:15.78#ibcon#enter sib2, iclass 4, count 0 2006.258.01:17:15.78#ibcon#flushed, iclass 4, count 0 2006.258.01:17:15.78#ibcon#about to write, iclass 4, count 0 2006.258.01:17:15.78#ibcon#wrote, iclass 4, count 0 2006.258.01:17:15.78#ibcon#about to read 3, iclass 4, count 0 2006.258.01:17:15.79#ibcon#read 3, iclass 4, count 0 2006.258.01:17:15.79#ibcon#about to read 4, iclass 4, count 0 2006.258.01:17:15.79#ibcon#read 4, iclass 4, count 0 2006.258.01:17:15.79#ibcon#about to read 5, iclass 4, count 0 2006.258.01:17:15.79#ibcon#read 5, iclass 4, count 0 2006.258.01:17:15.79#ibcon#about to read 6, iclass 4, count 0 2006.258.01:17:15.79#ibcon#read 6, iclass 4, count 0 2006.258.01:17:15.79#ibcon#end of sib2, iclass 4, count 0 2006.258.01:17:15.79#ibcon#*mode == 0, iclass 4, count 0 2006.258.01:17:15.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.01:17:15.79#ibcon#[25=BW32\r\n] 2006.258.01:17:15.79#ibcon#*before write, iclass 4, count 0 2006.258.01:17:15.79#ibcon#enter sib2, iclass 4, count 0 2006.258.01:17:15.79#ibcon#flushed, iclass 4, count 0 2006.258.01:17:15.79#ibcon#about to write, iclass 4, count 0 2006.258.01:17:15.79#ibcon#wrote, iclass 4, count 0 2006.258.01:17:15.79#ibcon#about to read 3, iclass 4, count 0 2006.258.01:17:15.82#ibcon#read 3, iclass 4, count 0 2006.258.01:17:15.82#ibcon#about to read 4, iclass 4, count 0 2006.258.01:17:15.82#ibcon#read 4, iclass 4, count 0 2006.258.01:17:15.82#ibcon#about to read 5, iclass 4, count 0 2006.258.01:17:15.82#ibcon#read 5, iclass 4, count 0 2006.258.01:17:15.82#ibcon#about to read 6, iclass 4, count 0 2006.258.01:17:15.82#ibcon#read 6, iclass 4, count 0 2006.258.01:17:15.82#ibcon#end of sib2, iclass 4, count 0 2006.258.01:17:15.82#ibcon#*after write, iclass 4, count 0 2006.258.01:17:15.82#ibcon#*before return 0, iclass 4, count 0 2006.258.01:17:15.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:15.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:17:15.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.01:17:15.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.01:17:15.82$vck44/vbbw=wide 2006.258.01:17:15.82#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.01:17:15.82#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.01:17:15.82#ibcon#ireg 8 cls_cnt 0 2006.258.01:17:15.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:17:15.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:17:15.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:17:15.89#ibcon#enter wrdev, iclass 6, count 0 2006.258.01:17:15.89#ibcon#first serial, iclass 6, count 0 2006.258.01:17:15.89#ibcon#enter sib2, iclass 6, count 0 2006.258.01:17:15.89#ibcon#flushed, iclass 6, count 0 2006.258.01:17:15.89#ibcon#about to write, iclass 6, count 0 2006.258.01:17:15.89#ibcon#wrote, iclass 6, count 0 2006.258.01:17:15.89#ibcon#about to read 3, iclass 6, count 0 2006.258.01:17:15.91#ibcon#read 3, iclass 6, count 0 2006.258.01:17:15.91#ibcon#about to read 4, iclass 6, count 0 2006.258.01:17:15.91#ibcon#read 4, iclass 6, count 0 2006.258.01:17:15.91#ibcon#about to read 5, iclass 6, count 0 2006.258.01:17:15.91#ibcon#read 5, iclass 6, count 0 2006.258.01:17:15.91#ibcon#about to read 6, iclass 6, count 0 2006.258.01:17:15.91#ibcon#read 6, iclass 6, count 0 2006.258.01:17:15.91#ibcon#end of sib2, iclass 6, count 0 2006.258.01:17:15.91#ibcon#*mode == 0, iclass 6, count 0 2006.258.01:17:15.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.01:17:15.91#ibcon#[27=BW32\r\n] 2006.258.01:17:15.91#ibcon#*before write, iclass 6, count 0 2006.258.01:17:15.91#ibcon#enter sib2, iclass 6, count 0 2006.258.01:17:15.91#ibcon#flushed, iclass 6, count 0 2006.258.01:17:15.91#ibcon#about to write, iclass 6, count 0 2006.258.01:17:15.91#ibcon#wrote, iclass 6, count 0 2006.258.01:17:15.91#ibcon#about to read 3, iclass 6, count 0 2006.258.01:17:15.94#ibcon#read 3, iclass 6, count 0 2006.258.01:17:15.94#ibcon#about to read 4, iclass 6, count 0 2006.258.01:17:15.94#ibcon#read 4, iclass 6, count 0 2006.258.01:17:15.94#ibcon#about to read 5, iclass 6, count 0 2006.258.01:17:15.94#ibcon#read 5, iclass 6, count 0 2006.258.01:17:15.94#ibcon#about to read 6, iclass 6, count 0 2006.258.01:17:15.94#ibcon#read 6, iclass 6, count 0 2006.258.01:17:15.94#ibcon#end of sib2, iclass 6, count 0 2006.258.01:17:15.94#ibcon#*after write, iclass 6, count 0 2006.258.01:17:15.94#ibcon#*before return 0, iclass 6, count 0 2006.258.01:17:15.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:17:15.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:17:15.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.01:17:15.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.01:17:15.94$setupk4/ifdk4 2006.258.01:17:15.94$ifdk4/lo= 2006.258.01:17:15.95$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.01:17:15.95$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.01:17:15.95$ifdk4/patch= 2006.258.01:17:15.95$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.01:17:15.95$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.01:17:15.95$setupk4/!*+20s 2006.258.01:17:19.76#abcon#<5=/03 3.1 6.5 22.93 711016.1\r\n> 2006.258.01:17:19.78#abcon#{5=INTERFACE CLEAR} 2006.258.01:17:19.84#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:17:29.93#abcon#<5=/03 3.1 6.5 22.94 711016.0\r\n> 2006.258.01:17:29.95#abcon#{5=INTERFACE CLEAR} 2006.258.01:17:30.01#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:17:30.28$setupk4/"tpicd 2006.258.01:17:30.28$setupk4/echo=off 2006.258.01:17:30.28$setupk4/xlog=off 2006.258.01:17:30.28:!2006.258.01:19:25 2006.258.01:17:49.14#trakl#Source acquired 2006.258.01:17:50.14#flagr#flagr/antenna,acquired 2006.258.01:19:25.00:preob 2006.258.01:19:25.14/onsource/TRACKING 2006.258.01:19:25.14:!2006.258.01:19:35 2006.258.01:19:35.00:"tape 2006.258.01:19:35.00:"st=record 2006.258.01:19:35.00:data_valid=on 2006.258.01:19:35.00:midob 2006.258.01:19:35.14/onsource/TRACKING 2006.258.01:19:35.15/wx/23.07,1016.0,72 2006.258.01:19:35.31/cable/+6.4756E-03 2006.258.01:19:36.40/va/01,08,usb,yes,35,37 2006.258.01:19:36.40/va/02,07,usb,yes,37,38 2006.258.01:19:36.40/va/03,08,usb,yes,33,35 2006.258.01:19:36.40/va/04,07,usb,yes,38,40 2006.258.01:19:36.40/va/05,04,usb,yes,34,35 2006.258.01:19:36.40/va/06,04,usb,yes,38,38 2006.258.01:19:36.40/va/07,04,usb,yes,39,40 2006.258.01:19:36.40/va/08,04,usb,yes,33,40 2006.258.01:19:36.63/valo/01,524.99,yes,locked 2006.258.01:19:36.63/valo/02,534.99,yes,locked 2006.258.01:19:36.63/valo/03,564.99,yes,locked 2006.258.01:19:36.63/valo/04,624.99,yes,locked 2006.258.01:19:36.63/valo/05,734.99,yes,locked 2006.258.01:19:36.63/valo/06,814.99,yes,locked 2006.258.01:19:36.63/valo/07,864.99,yes,locked 2006.258.01:19:36.63/valo/08,884.99,yes,locked 2006.258.01:19:37.72/vb/01,04,usb,yes,33,31 2006.258.01:19:37.72/vb/02,05,usb,yes,32,31 2006.258.01:19:37.72/vb/03,04,usb,yes,33,36 2006.258.01:19:37.72/vb/04,05,usb,yes,33,32 2006.258.01:19:37.72/vb/05,04,usb,yes,29,32 2006.258.01:19:37.72/vb/06,04,usb,yes,35,30 2006.258.01:19:37.72/vb/07,04,usb,yes,34,34 2006.258.01:19:37.72/vb/08,04,usb,yes,31,35 2006.258.01:19:37.95/vblo/01,629.99,yes,locked 2006.258.01:19:37.95/vblo/02,634.99,yes,locked 2006.258.01:19:37.95/vblo/03,649.99,yes,locked 2006.258.01:19:37.95/vblo/04,679.99,yes,locked 2006.258.01:19:37.95/vblo/05,709.99,yes,locked 2006.258.01:19:37.95/vblo/06,719.99,yes,locked 2006.258.01:19:37.95/vblo/07,734.99,yes,locked 2006.258.01:19:37.95/vblo/08,744.99,yes,locked 2006.258.01:19:38.10/vabw/8 2006.258.01:19:38.25/vbbw/8 2006.258.01:19:38.40/xfe/off,on,15.2 2006.258.01:19:38.77/ifatt/23,28,28,28 2006.258.01:19:39.07/fmout-gps/S +4.53E-07 2006.258.01:19:39.12:!2006.258.01:22:15 2006.258.01:22:15.01:data_valid=off 2006.258.01:22:15.02:"et 2006.258.01:22:15.02:!+3s 2006.258.01:22:18.04:"tape 2006.258.01:22:18.04:postob 2006.258.01:22:18.11/cable/+6.4747E-03 2006.258.01:22:18.11/wx/23.15,1016.0,72 2006.258.01:22:18.17/fmout-gps/S +4.52E-07 2006.258.01:22:18.17:scan_name=258-0123,jd0609,40 2006.258.01:22:18.18:source=3c345,164258.81,394837.0,2000.0,cw 2006.258.01:22:20.14#flagr#flagr/antenna,new-source 2006.258.01:22:20.14:checkk5 2006.258.01:22:20.57/chk_autoobs//k5ts1/ autoobs is running! 2006.258.01:22:20.97/chk_autoobs//k5ts2/ autoobs is running! 2006.258.01:22:21.38/chk_autoobs//k5ts3/ autoobs is running! 2006.258.01:22:21.76/chk_autoobs//k5ts4/ autoobs is running! 2006.258.01:22:22.15/chk_obsdata//k5ts1/T2580119??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.258.01:22:22.56/chk_obsdata//k5ts2/T2580119??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.258.01:22:22.96/chk_obsdata//k5ts3/T2580119??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.258.01:22:23.37/chk_obsdata//k5ts4/T2580119??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.258.01:22:24.10/k5log//k5ts1_log_newline 2006.258.01:22:24.82/k5log//k5ts2_log_newline 2006.258.01:22:25.54/k5log//k5ts3_log_newline 2006.258.01:22:26.25/k5log//k5ts4_log_newline 2006.258.01:22:26.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:22:26.27:setupk4=1 2006.258.01:22:26.27$setupk4/echo=on 2006.258.01:22:26.27$setupk4/pcalon 2006.258.01:22:26.27$pcalon/"no phase cal control is implemented here 2006.258.01:22:26.27$setupk4/"tpicd=stop 2006.258.01:22:26.27$setupk4/"rec=synch_on 2006.258.01:22:26.27$setupk4/"rec_mode=128 2006.258.01:22:26.27$setupk4/!* 2006.258.01:22:26.27$setupk4/recpk4 2006.258.01:22:26.27$recpk4/recpatch= 2006.258.01:22:26.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.01:22:26.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.01:22:26.28$setupk4/vck44 2006.258.01:22:26.28$vck44/valo=1,524.99 2006.258.01:22:26.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.01:22:26.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.01:22:26.28#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:26.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:26.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:26.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:26.28#ibcon#enter wrdev, iclass 29, count 0 2006.258.01:22:26.28#ibcon#first serial, iclass 29, count 0 2006.258.01:22:26.28#ibcon#enter sib2, iclass 29, count 0 2006.258.01:22:26.28#ibcon#flushed, iclass 29, count 0 2006.258.01:22:26.28#ibcon#about to write, iclass 29, count 0 2006.258.01:22:26.28#ibcon#wrote, iclass 29, count 0 2006.258.01:22:26.28#ibcon#about to read 3, iclass 29, count 0 2006.258.01:22:26.30#ibcon#read 3, iclass 29, count 0 2006.258.01:22:26.30#ibcon#about to read 4, iclass 29, count 0 2006.258.01:22:26.30#ibcon#read 4, iclass 29, count 0 2006.258.01:22:26.30#ibcon#about to read 5, iclass 29, count 0 2006.258.01:22:26.30#ibcon#read 5, iclass 29, count 0 2006.258.01:22:26.30#ibcon#about to read 6, iclass 29, count 0 2006.258.01:22:26.30#ibcon#read 6, iclass 29, count 0 2006.258.01:22:26.30#ibcon#end of sib2, iclass 29, count 0 2006.258.01:22:26.30#ibcon#*mode == 0, iclass 29, count 0 2006.258.01:22:26.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.01:22:26.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.01:22:26.30#ibcon#*before write, iclass 29, count 0 2006.258.01:22:26.30#ibcon#enter sib2, iclass 29, count 0 2006.258.01:22:26.30#ibcon#flushed, iclass 29, count 0 2006.258.01:22:26.30#ibcon#about to write, iclass 29, count 0 2006.258.01:22:26.30#ibcon#wrote, iclass 29, count 0 2006.258.01:22:26.30#ibcon#about to read 3, iclass 29, count 0 2006.258.01:22:26.35#ibcon#read 3, iclass 29, count 0 2006.258.01:22:26.35#ibcon#about to read 4, iclass 29, count 0 2006.258.01:22:26.35#ibcon#read 4, iclass 29, count 0 2006.258.01:22:26.35#ibcon#about to read 5, iclass 29, count 0 2006.258.01:22:26.35#ibcon#read 5, iclass 29, count 0 2006.258.01:22:26.35#ibcon#about to read 6, iclass 29, count 0 2006.258.01:22:26.35#ibcon#read 6, iclass 29, count 0 2006.258.01:22:26.35#ibcon#end of sib2, iclass 29, count 0 2006.258.01:22:26.35#ibcon#*after write, iclass 29, count 0 2006.258.01:22:26.35#ibcon#*before return 0, iclass 29, count 0 2006.258.01:22:26.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:26.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:26.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.01:22:26.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.01:22:26.35$vck44/va=1,8 2006.258.01:22:26.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.01:22:26.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.01:22:26.35#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:26.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:26.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:26.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:26.35#ibcon#enter wrdev, iclass 31, count 2 2006.258.01:22:26.35#ibcon#first serial, iclass 31, count 2 2006.258.01:22:26.35#ibcon#enter sib2, iclass 31, count 2 2006.258.01:22:26.35#ibcon#flushed, iclass 31, count 2 2006.258.01:22:26.35#ibcon#about to write, iclass 31, count 2 2006.258.01:22:26.35#ibcon#wrote, iclass 31, count 2 2006.258.01:22:26.35#ibcon#about to read 3, iclass 31, count 2 2006.258.01:22:26.37#ibcon#read 3, iclass 31, count 2 2006.258.01:22:26.37#ibcon#about to read 4, iclass 31, count 2 2006.258.01:22:26.37#ibcon#read 4, iclass 31, count 2 2006.258.01:22:26.37#ibcon#about to read 5, iclass 31, count 2 2006.258.01:22:26.37#ibcon#read 5, iclass 31, count 2 2006.258.01:22:26.37#ibcon#about to read 6, iclass 31, count 2 2006.258.01:22:26.37#ibcon#read 6, iclass 31, count 2 2006.258.01:22:26.37#ibcon#end of sib2, iclass 31, count 2 2006.258.01:22:26.37#ibcon#*mode == 0, iclass 31, count 2 2006.258.01:22:26.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.01:22:26.37#ibcon#[25=AT01-08\r\n] 2006.258.01:22:26.37#ibcon#*before write, iclass 31, count 2 2006.258.01:22:26.37#ibcon#enter sib2, iclass 31, count 2 2006.258.01:22:26.37#ibcon#flushed, iclass 31, count 2 2006.258.01:22:26.37#ibcon#about to write, iclass 31, count 2 2006.258.01:22:26.37#ibcon#wrote, iclass 31, count 2 2006.258.01:22:26.37#ibcon#about to read 3, iclass 31, count 2 2006.258.01:22:26.40#ibcon#read 3, iclass 31, count 2 2006.258.01:22:26.40#ibcon#about to read 4, iclass 31, count 2 2006.258.01:22:26.40#ibcon#read 4, iclass 31, count 2 2006.258.01:22:26.40#ibcon#about to read 5, iclass 31, count 2 2006.258.01:22:26.40#ibcon#read 5, iclass 31, count 2 2006.258.01:22:26.40#ibcon#about to read 6, iclass 31, count 2 2006.258.01:22:26.40#ibcon#read 6, iclass 31, count 2 2006.258.01:22:26.40#ibcon#end of sib2, iclass 31, count 2 2006.258.01:22:26.40#ibcon#*after write, iclass 31, count 2 2006.258.01:22:26.40#ibcon#*before return 0, iclass 31, count 2 2006.258.01:22:26.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:26.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:26.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.01:22:26.40#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:26.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:26.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:26.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:26.52#ibcon#enter wrdev, iclass 31, count 0 2006.258.01:22:26.52#ibcon#first serial, iclass 31, count 0 2006.258.01:22:26.52#ibcon#enter sib2, iclass 31, count 0 2006.258.01:22:26.52#ibcon#flushed, iclass 31, count 0 2006.258.01:22:26.52#ibcon#about to write, iclass 31, count 0 2006.258.01:22:26.52#ibcon#wrote, iclass 31, count 0 2006.258.01:22:26.52#ibcon#about to read 3, iclass 31, count 0 2006.258.01:22:26.54#ibcon#read 3, iclass 31, count 0 2006.258.01:22:26.54#ibcon#about to read 4, iclass 31, count 0 2006.258.01:22:26.54#ibcon#read 4, iclass 31, count 0 2006.258.01:22:26.54#ibcon#about to read 5, iclass 31, count 0 2006.258.01:22:26.54#ibcon#read 5, iclass 31, count 0 2006.258.01:22:26.54#ibcon#about to read 6, iclass 31, count 0 2006.258.01:22:26.54#ibcon#read 6, iclass 31, count 0 2006.258.01:22:26.54#ibcon#end of sib2, iclass 31, count 0 2006.258.01:22:26.54#ibcon#*mode == 0, iclass 31, count 0 2006.258.01:22:26.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.01:22:26.54#ibcon#[25=USB\r\n] 2006.258.01:22:26.54#ibcon#*before write, iclass 31, count 0 2006.258.01:22:26.54#ibcon#enter sib2, iclass 31, count 0 2006.258.01:22:26.54#ibcon#flushed, iclass 31, count 0 2006.258.01:22:26.54#ibcon#about to write, iclass 31, count 0 2006.258.01:22:26.54#ibcon#wrote, iclass 31, count 0 2006.258.01:22:26.54#ibcon#about to read 3, iclass 31, count 0 2006.258.01:22:26.57#ibcon#read 3, iclass 31, count 0 2006.258.01:22:26.57#ibcon#about to read 4, iclass 31, count 0 2006.258.01:22:26.57#ibcon#read 4, iclass 31, count 0 2006.258.01:22:26.57#ibcon#about to read 5, iclass 31, count 0 2006.258.01:22:26.57#ibcon#read 5, iclass 31, count 0 2006.258.01:22:26.57#ibcon#about to read 6, iclass 31, count 0 2006.258.01:22:26.57#ibcon#read 6, iclass 31, count 0 2006.258.01:22:26.57#ibcon#end of sib2, iclass 31, count 0 2006.258.01:22:26.57#ibcon#*after write, iclass 31, count 0 2006.258.01:22:26.57#ibcon#*before return 0, iclass 31, count 0 2006.258.01:22:26.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:26.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:26.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.01:22:26.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.01:22:26.57$vck44/valo=2,534.99 2006.258.01:22:26.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.01:22:26.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.01:22:26.57#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:26.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:26.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:26.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:26.57#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:22:26.57#ibcon#first serial, iclass 33, count 0 2006.258.01:22:26.57#ibcon#enter sib2, iclass 33, count 0 2006.258.01:22:26.57#ibcon#flushed, iclass 33, count 0 2006.258.01:22:26.57#ibcon#about to write, iclass 33, count 0 2006.258.01:22:26.57#ibcon#wrote, iclass 33, count 0 2006.258.01:22:26.57#ibcon#about to read 3, iclass 33, count 0 2006.258.01:22:26.59#ibcon#read 3, iclass 33, count 0 2006.258.01:22:26.59#ibcon#about to read 4, iclass 33, count 0 2006.258.01:22:26.59#ibcon#read 4, iclass 33, count 0 2006.258.01:22:26.59#ibcon#about to read 5, iclass 33, count 0 2006.258.01:22:26.59#ibcon#read 5, iclass 33, count 0 2006.258.01:22:26.59#ibcon#about to read 6, iclass 33, count 0 2006.258.01:22:26.59#ibcon#read 6, iclass 33, count 0 2006.258.01:22:26.59#ibcon#end of sib2, iclass 33, count 0 2006.258.01:22:26.59#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:22:26.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:22:26.59#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.01:22:26.59#ibcon#*before write, iclass 33, count 0 2006.258.01:22:26.59#ibcon#enter sib2, iclass 33, count 0 2006.258.01:22:26.59#ibcon#flushed, iclass 33, count 0 2006.258.01:22:26.59#ibcon#about to write, iclass 33, count 0 2006.258.01:22:26.59#ibcon#wrote, iclass 33, count 0 2006.258.01:22:26.59#ibcon#about to read 3, iclass 33, count 0 2006.258.01:22:26.63#ibcon#read 3, iclass 33, count 0 2006.258.01:22:26.63#ibcon#about to read 4, iclass 33, count 0 2006.258.01:22:26.63#ibcon#read 4, iclass 33, count 0 2006.258.01:22:26.63#ibcon#about to read 5, iclass 33, count 0 2006.258.01:22:26.63#ibcon#read 5, iclass 33, count 0 2006.258.01:22:26.63#ibcon#about to read 6, iclass 33, count 0 2006.258.01:22:26.63#ibcon#read 6, iclass 33, count 0 2006.258.01:22:26.63#ibcon#end of sib2, iclass 33, count 0 2006.258.01:22:26.63#ibcon#*after write, iclass 33, count 0 2006.258.01:22:26.63#ibcon#*before return 0, iclass 33, count 0 2006.258.01:22:26.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:26.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:26.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:22:26.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:22:26.63$vck44/va=2,7 2006.258.01:22:26.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.01:22:26.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.01:22:26.63#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:26.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:26.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:26.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:26.69#ibcon#enter wrdev, iclass 35, count 2 2006.258.01:22:26.69#ibcon#first serial, iclass 35, count 2 2006.258.01:22:26.69#ibcon#enter sib2, iclass 35, count 2 2006.258.01:22:26.69#ibcon#flushed, iclass 35, count 2 2006.258.01:22:26.69#ibcon#about to write, iclass 35, count 2 2006.258.01:22:26.69#ibcon#wrote, iclass 35, count 2 2006.258.01:22:26.69#ibcon#about to read 3, iclass 35, count 2 2006.258.01:22:26.71#ibcon#read 3, iclass 35, count 2 2006.258.01:22:26.71#ibcon#about to read 4, iclass 35, count 2 2006.258.01:22:26.71#ibcon#read 4, iclass 35, count 2 2006.258.01:22:26.71#ibcon#about to read 5, iclass 35, count 2 2006.258.01:22:26.71#ibcon#read 5, iclass 35, count 2 2006.258.01:22:26.71#ibcon#about to read 6, iclass 35, count 2 2006.258.01:22:26.71#ibcon#read 6, iclass 35, count 2 2006.258.01:22:26.71#ibcon#end of sib2, iclass 35, count 2 2006.258.01:22:26.71#ibcon#*mode == 0, iclass 35, count 2 2006.258.01:22:26.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.01:22:26.71#ibcon#[25=AT02-07\r\n] 2006.258.01:22:26.71#ibcon#*before write, iclass 35, count 2 2006.258.01:22:26.71#ibcon#enter sib2, iclass 35, count 2 2006.258.01:22:26.71#ibcon#flushed, iclass 35, count 2 2006.258.01:22:26.71#ibcon#about to write, iclass 35, count 2 2006.258.01:22:26.71#ibcon#wrote, iclass 35, count 2 2006.258.01:22:26.71#ibcon#about to read 3, iclass 35, count 2 2006.258.01:22:26.74#ibcon#read 3, iclass 35, count 2 2006.258.01:22:26.74#ibcon#about to read 4, iclass 35, count 2 2006.258.01:22:26.74#ibcon#read 4, iclass 35, count 2 2006.258.01:22:26.74#ibcon#about to read 5, iclass 35, count 2 2006.258.01:22:26.74#ibcon#read 5, iclass 35, count 2 2006.258.01:22:26.74#ibcon#about to read 6, iclass 35, count 2 2006.258.01:22:26.74#ibcon#read 6, iclass 35, count 2 2006.258.01:22:26.74#ibcon#end of sib2, iclass 35, count 2 2006.258.01:22:26.74#ibcon#*after write, iclass 35, count 2 2006.258.01:22:26.74#ibcon#*before return 0, iclass 35, count 2 2006.258.01:22:26.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:26.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:26.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.01:22:26.74#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:26.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:26.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:26.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:26.86#ibcon#enter wrdev, iclass 35, count 0 2006.258.01:22:26.86#ibcon#first serial, iclass 35, count 0 2006.258.01:22:26.86#ibcon#enter sib2, iclass 35, count 0 2006.258.01:22:26.86#ibcon#flushed, iclass 35, count 0 2006.258.01:22:26.86#ibcon#about to write, iclass 35, count 0 2006.258.01:22:26.86#ibcon#wrote, iclass 35, count 0 2006.258.01:22:26.86#ibcon#about to read 3, iclass 35, count 0 2006.258.01:22:26.88#ibcon#read 3, iclass 35, count 0 2006.258.01:22:26.88#ibcon#about to read 4, iclass 35, count 0 2006.258.01:22:26.88#ibcon#read 4, iclass 35, count 0 2006.258.01:22:26.88#ibcon#about to read 5, iclass 35, count 0 2006.258.01:22:26.88#ibcon#read 5, iclass 35, count 0 2006.258.01:22:26.88#ibcon#about to read 6, iclass 35, count 0 2006.258.01:22:26.88#ibcon#read 6, iclass 35, count 0 2006.258.01:22:26.88#ibcon#end of sib2, iclass 35, count 0 2006.258.01:22:26.88#ibcon#*mode == 0, iclass 35, count 0 2006.258.01:22:26.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.01:22:26.88#ibcon#[25=USB\r\n] 2006.258.01:22:26.88#ibcon#*before write, iclass 35, count 0 2006.258.01:22:26.88#ibcon#enter sib2, iclass 35, count 0 2006.258.01:22:26.88#ibcon#flushed, iclass 35, count 0 2006.258.01:22:26.88#ibcon#about to write, iclass 35, count 0 2006.258.01:22:26.88#ibcon#wrote, iclass 35, count 0 2006.258.01:22:26.88#ibcon#about to read 3, iclass 35, count 0 2006.258.01:22:26.91#ibcon#read 3, iclass 35, count 0 2006.258.01:22:26.91#ibcon#about to read 4, iclass 35, count 0 2006.258.01:22:26.91#ibcon#read 4, iclass 35, count 0 2006.258.01:22:26.91#ibcon#about to read 5, iclass 35, count 0 2006.258.01:22:26.91#ibcon#read 5, iclass 35, count 0 2006.258.01:22:26.91#ibcon#about to read 6, iclass 35, count 0 2006.258.01:22:26.91#ibcon#read 6, iclass 35, count 0 2006.258.01:22:26.91#ibcon#end of sib2, iclass 35, count 0 2006.258.01:22:26.91#ibcon#*after write, iclass 35, count 0 2006.258.01:22:26.91#ibcon#*before return 0, iclass 35, count 0 2006.258.01:22:26.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:26.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:26.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.01:22:26.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.01:22:26.91$vck44/valo=3,564.99 2006.258.01:22:26.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.01:22:26.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.01:22:26.91#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:26.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:26.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:26.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:26.91#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:22:26.91#ibcon#first serial, iclass 37, count 0 2006.258.01:22:26.91#ibcon#enter sib2, iclass 37, count 0 2006.258.01:22:26.91#ibcon#flushed, iclass 37, count 0 2006.258.01:22:26.91#ibcon#about to write, iclass 37, count 0 2006.258.01:22:26.91#ibcon#wrote, iclass 37, count 0 2006.258.01:22:26.91#ibcon#about to read 3, iclass 37, count 0 2006.258.01:22:26.93#ibcon#read 3, iclass 37, count 0 2006.258.01:22:26.93#ibcon#about to read 4, iclass 37, count 0 2006.258.01:22:26.93#ibcon#read 4, iclass 37, count 0 2006.258.01:22:26.93#ibcon#about to read 5, iclass 37, count 0 2006.258.01:22:26.93#ibcon#read 5, iclass 37, count 0 2006.258.01:22:26.93#ibcon#about to read 6, iclass 37, count 0 2006.258.01:22:26.93#ibcon#read 6, iclass 37, count 0 2006.258.01:22:26.93#ibcon#end of sib2, iclass 37, count 0 2006.258.01:22:26.93#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:22:26.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:22:26.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.01:22:26.93#ibcon#*before write, iclass 37, count 0 2006.258.01:22:26.93#ibcon#enter sib2, iclass 37, count 0 2006.258.01:22:26.93#ibcon#flushed, iclass 37, count 0 2006.258.01:22:26.93#ibcon#about to write, iclass 37, count 0 2006.258.01:22:26.93#ibcon#wrote, iclass 37, count 0 2006.258.01:22:26.93#ibcon#about to read 3, iclass 37, count 0 2006.258.01:22:26.97#ibcon#read 3, iclass 37, count 0 2006.258.01:22:26.97#ibcon#about to read 4, iclass 37, count 0 2006.258.01:22:26.97#ibcon#read 4, iclass 37, count 0 2006.258.01:22:26.97#ibcon#about to read 5, iclass 37, count 0 2006.258.01:22:26.97#ibcon#read 5, iclass 37, count 0 2006.258.01:22:26.97#ibcon#about to read 6, iclass 37, count 0 2006.258.01:22:26.97#ibcon#read 6, iclass 37, count 0 2006.258.01:22:26.97#ibcon#end of sib2, iclass 37, count 0 2006.258.01:22:26.97#ibcon#*after write, iclass 37, count 0 2006.258.01:22:26.97#ibcon#*before return 0, iclass 37, count 0 2006.258.01:22:26.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:26.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:26.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:22:26.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:22:26.97$vck44/va=3,8 2006.258.01:22:26.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.258.01:22:26.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.258.01:22:26.97#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:26.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:27.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:27.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:27.03#ibcon#enter wrdev, iclass 39, count 2 2006.258.01:22:27.03#ibcon#first serial, iclass 39, count 2 2006.258.01:22:27.03#ibcon#enter sib2, iclass 39, count 2 2006.258.01:22:27.03#ibcon#flushed, iclass 39, count 2 2006.258.01:22:27.03#ibcon#about to write, iclass 39, count 2 2006.258.01:22:27.03#ibcon#wrote, iclass 39, count 2 2006.258.01:22:27.03#ibcon#about to read 3, iclass 39, count 2 2006.258.01:22:27.05#ibcon#read 3, iclass 39, count 2 2006.258.01:22:27.05#ibcon#about to read 4, iclass 39, count 2 2006.258.01:22:27.05#ibcon#read 4, iclass 39, count 2 2006.258.01:22:27.05#ibcon#about to read 5, iclass 39, count 2 2006.258.01:22:27.05#ibcon#read 5, iclass 39, count 2 2006.258.01:22:27.05#ibcon#about to read 6, iclass 39, count 2 2006.258.01:22:27.05#ibcon#read 6, iclass 39, count 2 2006.258.01:22:27.05#ibcon#end of sib2, iclass 39, count 2 2006.258.01:22:27.05#ibcon#*mode == 0, iclass 39, count 2 2006.258.01:22:27.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.258.01:22:27.05#ibcon#[25=AT03-08\r\n] 2006.258.01:22:27.05#ibcon#*before write, iclass 39, count 2 2006.258.01:22:27.05#ibcon#enter sib2, iclass 39, count 2 2006.258.01:22:27.05#ibcon#flushed, iclass 39, count 2 2006.258.01:22:27.05#ibcon#about to write, iclass 39, count 2 2006.258.01:22:27.05#ibcon#wrote, iclass 39, count 2 2006.258.01:22:27.05#ibcon#about to read 3, iclass 39, count 2 2006.258.01:22:27.08#ibcon#read 3, iclass 39, count 2 2006.258.01:22:27.08#ibcon#about to read 4, iclass 39, count 2 2006.258.01:22:27.08#ibcon#read 4, iclass 39, count 2 2006.258.01:22:27.08#ibcon#about to read 5, iclass 39, count 2 2006.258.01:22:27.08#ibcon#read 5, iclass 39, count 2 2006.258.01:22:27.08#ibcon#about to read 6, iclass 39, count 2 2006.258.01:22:27.08#ibcon#read 6, iclass 39, count 2 2006.258.01:22:27.08#ibcon#end of sib2, iclass 39, count 2 2006.258.01:22:27.08#ibcon#*after write, iclass 39, count 2 2006.258.01:22:27.08#ibcon#*before return 0, iclass 39, count 2 2006.258.01:22:27.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:27.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:27.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.258.01:22:27.08#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:27.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:27.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:27.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:27.20#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:22:27.20#ibcon#first serial, iclass 39, count 0 2006.258.01:22:27.20#ibcon#enter sib2, iclass 39, count 0 2006.258.01:22:27.20#ibcon#flushed, iclass 39, count 0 2006.258.01:22:27.20#ibcon#about to write, iclass 39, count 0 2006.258.01:22:27.20#ibcon#wrote, iclass 39, count 0 2006.258.01:22:27.20#ibcon#about to read 3, iclass 39, count 0 2006.258.01:22:27.22#ibcon#read 3, iclass 39, count 0 2006.258.01:22:27.22#ibcon#about to read 4, iclass 39, count 0 2006.258.01:22:27.22#ibcon#read 4, iclass 39, count 0 2006.258.01:22:27.22#ibcon#about to read 5, iclass 39, count 0 2006.258.01:22:27.22#ibcon#read 5, iclass 39, count 0 2006.258.01:22:27.22#ibcon#about to read 6, iclass 39, count 0 2006.258.01:22:27.22#ibcon#read 6, iclass 39, count 0 2006.258.01:22:27.22#ibcon#end of sib2, iclass 39, count 0 2006.258.01:22:27.22#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:22:27.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:22:27.22#ibcon#[25=USB\r\n] 2006.258.01:22:27.22#ibcon#*before write, iclass 39, count 0 2006.258.01:22:27.22#ibcon#enter sib2, iclass 39, count 0 2006.258.01:22:27.22#ibcon#flushed, iclass 39, count 0 2006.258.01:22:27.22#ibcon#about to write, iclass 39, count 0 2006.258.01:22:27.22#ibcon#wrote, iclass 39, count 0 2006.258.01:22:27.22#ibcon#about to read 3, iclass 39, count 0 2006.258.01:22:27.25#ibcon#read 3, iclass 39, count 0 2006.258.01:22:27.25#ibcon#about to read 4, iclass 39, count 0 2006.258.01:22:27.25#ibcon#read 4, iclass 39, count 0 2006.258.01:22:27.25#ibcon#about to read 5, iclass 39, count 0 2006.258.01:22:27.25#ibcon#read 5, iclass 39, count 0 2006.258.01:22:27.25#ibcon#about to read 6, iclass 39, count 0 2006.258.01:22:27.25#ibcon#read 6, iclass 39, count 0 2006.258.01:22:27.25#ibcon#end of sib2, iclass 39, count 0 2006.258.01:22:27.25#ibcon#*after write, iclass 39, count 0 2006.258.01:22:27.25#ibcon#*before return 0, iclass 39, count 0 2006.258.01:22:27.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:27.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:27.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:22:27.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:22:27.25$vck44/valo=4,624.99 2006.258.01:22:27.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.01:22:27.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.01:22:27.25#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:27.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:27.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:27.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:27.25#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:22:27.25#ibcon#first serial, iclass 3, count 0 2006.258.01:22:27.25#ibcon#enter sib2, iclass 3, count 0 2006.258.01:22:27.25#ibcon#flushed, iclass 3, count 0 2006.258.01:22:27.25#ibcon#about to write, iclass 3, count 0 2006.258.01:22:27.25#ibcon#wrote, iclass 3, count 0 2006.258.01:22:27.25#ibcon#about to read 3, iclass 3, count 0 2006.258.01:22:27.27#ibcon#read 3, iclass 3, count 0 2006.258.01:22:27.27#ibcon#about to read 4, iclass 3, count 0 2006.258.01:22:27.27#ibcon#read 4, iclass 3, count 0 2006.258.01:22:27.27#ibcon#about to read 5, iclass 3, count 0 2006.258.01:22:27.27#ibcon#read 5, iclass 3, count 0 2006.258.01:22:27.27#ibcon#about to read 6, iclass 3, count 0 2006.258.01:22:27.27#ibcon#read 6, iclass 3, count 0 2006.258.01:22:27.27#ibcon#end of sib2, iclass 3, count 0 2006.258.01:22:27.27#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:22:27.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:22:27.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.01:22:27.27#ibcon#*before write, iclass 3, count 0 2006.258.01:22:27.27#ibcon#enter sib2, iclass 3, count 0 2006.258.01:22:27.27#ibcon#flushed, iclass 3, count 0 2006.258.01:22:27.27#ibcon#about to write, iclass 3, count 0 2006.258.01:22:27.27#ibcon#wrote, iclass 3, count 0 2006.258.01:22:27.27#ibcon#about to read 3, iclass 3, count 0 2006.258.01:22:27.31#ibcon#read 3, iclass 3, count 0 2006.258.01:22:27.31#ibcon#about to read 4, iclass 3, count 0 2006.258.01:22:27.31#ibcon#read 4, iclass 3, count 0 2006.258.01:22:27.31#ibcon#about to read 5, iclass 3, count 0 2006.258.01:22:27.31#ibcon#read 5, iclass 3, count 0 2006.258.01:22:27.31#ibcon#about to read 6, iclass 3, count 0 2006.258.01:22:27.31#ibcon#read 6, iclass 3, count 0 2006.258.01:22:27.31#ibcon#end of sib2, iclass 3, count 0 2006.258.01:22:27.31#ibcon#*after write, iclass 3, count 0 2006.258.01:22:27.31#ibcon#*before return 0, iclass 3, count 0 2006.258.01:22:27.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:27.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:27.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:22:27.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:22:27.31$vck44/va=4,7 2006.258.01:22:27.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.258.01:22:27.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.258.01:22:27.31#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:27.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:27.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:27.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:27.37#ibcon#enter wrdev, iclass 5, count 2 2006.258.01:22:27.37#ibcon#first serial, iclass 5, count 2 2006.258.01:22:27.37#ibcon#enter sib2, iclass 5, count 2 2006.258.01:22:27.37#ibcon#flushed, iclass 5, count 2 2006.258.01:22:27.37#ibcon#about to write, iclass 5, count 2 2006.258.01:22:27.37#ibcon#wrote, iclass 5, count 2 2006.258.01:22:27.37#ibcon#about to read 3, iclass 5, count 2 2006.258.01:22:27.39#ibcon#read 3, iclass 5, count 2 2006.258.01:22:27.39#ibcon#about to read 4, iclass 5, count 2 2006.258.01:22:27.39#ibcon#read 4, iclass 5, count 2 2006.258.01:22:27.39#ibcon#about to read 5, iclass 5, count 2 2006.258.01:22:27.39#ibcon#read 5, iclass 5, count 2 2006.258.01:22:27.39#ibcon#about to read 6, iclass 5, count 2 2006.258.01:22:27.39#ibcon#read 6, iclass 5, count 2 2006.258.01:22:27.39#ibcon#end of sib2, iclass 5, count 2 2006.258.01:22:27.39#ibcon#*mode == 0, iclass 5, count 2 2006.258.01:22:27.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.258.01:22:27.39#ibcon#[25=AT04-07\r\n] 2006.258.01:22:27.39#ibcon#*before write, iclass 5, count 2 2006.258.01:22:27.39#ibcon#enter sib2, iclass 5, count 2 2006.258.01:22:27.39#ibcon#flushed, iclass 5, count 2 2006.258.01:22:27.39#ibcon#about to write, iclass 5, count 2 2006.258.01:22:27.39#ibcon#wrote, iclass 5, count 2 2006.258.01:22:27.39#ibcon#about to read 3, iclass 5, count 2 2006.258.01:22:27.42#ibcon#read 3, iclass 5, count 2 2006.258.01:22:27.42#ibcon#about to read 4, iclass 5, count 2 2006.258.01:22:27.42#ibcon#read 4, iclass 5, count 2 2006.258.01:22:27.42#ibcon#about to read 5, iclass 5, count 2 2006.258.01:22:27.42#ibcon#read 5, iclass 5, count 2 2006.258.01:22:27.42#ibcon#about to read 6, iclass 5, count 2 2006.258.01:22:27.42#ibcon#read 6, iclass 5, count 2 2006.258.01:22:27.42#ibcon#end of sib2, iclass 5, count 2 2006.258.01:22:27.42#ibcon#*after write, iclass 5, count 2 2006.258.01:22:27.42#ibcon#*before return 0, iclass 5, count 2 2006.258.01:22:27.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:27.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:27.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.258.01:22:27.42#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:27.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:27.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:27.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:27.54#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:22:27.54#ibcon#first serial, iclass 5, count 0 2006.258.01:22:27.54#ibcon#enter sib2, iclass 5, count 0 2006.258.01:22:27.54#ibcon#flushed, iclass 5, count 0 2006.258.01:22:27.54#ibcon#about to write, iclass 5, count 0 2006.258.01:22:27.54#ibcon#wrote, iclass 5, count 0 2006.258.01:22:27.54#ibcon#about to read 3, iclass 5, count 0 2006.258.01:22:27.56#ibcon#read 3, iclass 5, count 0 2006.258.01:22:27.56#ibcon#about to read 4, iclass 5, count 0 2006.258.01:22:27.56#ibcon#read 4, iclass 5, count 0 2006.258.01:22:27.56#ibcon#about to read 5, iclass 5, count 0 2006.258.01:22:27.56#ibcon#read 5, iclass 5, count 0 2006.258.01:22:27.56#ibcon#about to read 6, iclass 5, count 0 2006.258.01:22:27.56#ibcon#read 6, iclass 5, count 0 2006.258.01:22:27.56#ibcon#end of sib2, iclass 5, count 0 2006.258.01:22:27.56#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:22:27.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:22:27.56#ibcon#[25=USB\r\n] 2006.258.01:22:27.56#ibcon#*before write, iclass 5, count 0 2006.258.01:22:27.56#ibcon#enter sib2, iclass 5, count 0 2006.258.01:22:27.56#ibcon#flushed, iclass 5, count 0 2006.258.01:22:27.56#ibcon#about to write, iclass 5, count 0 2006.258.01:22:27.56#ibcon#wrote, iclass 5, count 0 2006.258.01:22:27.56#ibcon#about to read 3, iclass 5, count 0 2006.258.01:22:27.59#ibcon#read 3, iclass 5, count 0 2006.258.01:22:27.59#ibcon#about to read 4, iclass 5, count 0 2006.258.01:22:27.59#ibcon#read 4, iclass 5, count 0 2006.258.01:22:27.59#ibcon#about to read 5, iclass 5, count 0 2006.258.01:22:27.59#ibcon#read 5, iclass 5, count 0 2006.258.01:22:27.59#ibcon#about to read 6, iclass 5, count 0 2006.258.01:22:27.59#ibcon#read 6, iclass 5, count 0 2006.258.01:22:27.59#ibcon#end of sib2, iclass 5, count 0 2006.258.01:22:27.59#ibcon#*after write, iclass 5, count 0 2006.258.01:22:27.59#ibcon#*before return 0, iclass 5, count 0 2006.258.01:22:27.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:27.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:27.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:22:27.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:22:27.59$vck44/valo=5,734.99 2006.258.01:22:27.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.01:22:27.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.01:22:27.59#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:27.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:27.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:27.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:27.59#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:22:27.59#ibcon#first serial, iclass 7, count 0 2006.258.01:22:27.59#ibcon#enter sib2, iclass 7, count 0 2006.258.01:22:27.59#ibcon#flushed, iclass 7, count 0 2006.258.01:22:27.59#ibcon#about to write, iclass 7, count 0 2006.258.01:22:27.59#ibcon#wrote, iclass 7, count 0 2006.258.01:22:27.59#ibcon#about to read 3, iclass 7, count 0 2006.258.01:22:27.61#ibcon#read 3, iclass 7, count 0 2006.258.01:22:27.61#ibcon#about to read 4, iclass 7, count 0 2006.258.01:22:27.61#ibcon#read 4, iclass 7, count 0 2006.258.01:22:27.61#ibcon#about to read 5, iclass 7, count 0 2006.258.01:22:27.61#ibcon#read 5, iclass 7, count 0 2006.258.01:22:27.61#ibcon#about to read 6, iclass 7, count 0 2006.258.01:22:27.61#ibcon#read 6, iclass 7, count 0 2006.258.01:22:27.61#ibcon#end of sib2, iclass 7, count 0 2006.258.01:22:27.61#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:22:27.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:22:27.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.01:22:27.61#ibcon#*before write, iclass 7, count 0 2006.258.01:22:27.61#ibcon#enter sib2, iclass 7, count 0 2006.258.01:22:27.61#ibcon#flushed, iclass 7, count 0 2006.258.01:22:27.61#ibcon#about to write, iclass 7, count 0 2006.258.01:22:27.61#ibcon#wrote, iclass 7, count 0 2006.258.01:22:27.61#ibcon#about to read 3, iclass 7, count 0 2006.258.01:22:27.65#ibcon#read 3, iclass 7, count 0 2006.258.01:22:27.65#ibcon#about to read 4, iclass 7, count 0 2006.258.01:22:27.65#ibcon#read 4, iclass 7, count 0 2006.258.01:22:27.65#ibcon#about to read 5, iclass 7, count 0 2006.258.01:22:27.65#ibcon#read 5, iclass 7, count 0 2006.258.01:22:27.65#ibcon#about to read 6, iclass 7, count 0 2006.258.01:22:27.65#ibcon#read 6, iclass 7, count 0 2006.258.01:22:27.65#ibcon#end of sib2, iclass 7, count 0 2006.258.01:22:27.65#ibcon#*after write, iclass 7, count 0 2006.258.01:22:27.65#ibcon#*before return 0, iclass 7, count 0 2006.258.01:22:27.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:27.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:27.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:22:27.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:22:27.65$vck44/va=5,4 2006.258.01:22:27.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.01:22:27.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.01:22:27.65#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:27.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:27.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:27.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:27.71#ibcon#enter wrdev, iclass 11, count 2 2006.258.01:22:27.71#ibcon#first serial, iclass 11, count 2 2006.258.01:22:27.71#ibcon#enter sib2, iclass 11, count 2 2006.258.01:22:27.71#ibcon#flushed, iclass 11, count 2 2006.258.01:22:27.71#ibcon#about to write, iclass 11, count 2 2006.258.01:22:27.71#ibcon#wrote, iclass 11, count 2 2006.258.01:22:27.71#ibcon#about to read 3, iclass 11, count 2 2006.258.01:22:27.73#ibcon#read 3, iclass 11, count 2 2006.258.01:22:27.73#ibcon#about to read 4, iclass 11, count 2 2006.258.01:22:27.73#ibcon#read 4, iclass 11, count 2 2006.258.01:22:27.73#ibcon#about to read 5, iclass 11, count 2 2006.258.01:22:27.73#ibcon#read 5, iclass 11, count 2 2006.258.01:22:27.73#ibcon#about to read 6, iclass 11, count 2 2006.258.01:22:27.73#ibcon#read 6, iclass 11, count 2 2006.258.01:22:27.73#ibcon#end of sib2, iclass 11, count 2 2006.258.01:22:27.73#ibcon#*mode == 0, iclass 11, count 2 2006.258.01:22:27.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.01:22:27.73#ibcon#[25=AT05-04\r\n] 2006.258.01:22:27.73#ibcon#*before write, iclass 11, count 2 2006.258.01:22:27.73#ibcon#enter sib2, iclass 11, count 2 2006.258.01:22:27.73#ibcon#flushed, iclass 11, count 2 2006.258.01:22:27.73#ibcon#about to write, iclass 11, count 2 2006.258.01:22:27.73#ibcon#wrote, iclass 11, count 2 2006.258.01:22:27.73#ibcon#about to read 3, iclass 11, count 2 2006.258.01:22:27.76#ibcon#read 3, iclass 11, count 2 2006.258.01:22:27.76#ibcon#about to read 4, iclass 11, count 2 2006.258.01:22:27.76#ibcon#read 4, iclass 11, count 2 2006.258.01:22:27.76#ibcon#about to read 5, iclass 11, count 2 2006.258.01:22:27.76#ibcon#read 5, iclass 11, count 2 2006.258.01:22:27.76#ibcon#about to read 6, iclass 11, count 2 2006.258.01:22:27.76#ibcon#read 6, iclass 11, count 2 2006.258.01:22:27.76#ibcon#end of sib2, iclass 11, count 2 2006.258.01:22:27.76#ibcon#*after write, iclass 11, count 2 2006.258.01:22:27.76#ibcon#*before return 0, iclass 11, count 2 2006.258.01:22:27.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:27.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:27.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.01:22:27.76#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:27.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:27.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:27.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:27.88#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:22:27.88#ibcon#first serial, iclass 11, count 0 2006.258.01:22:27.88#ibcon#enter sib2, iclass 11, count 0 2006.258.01:22:27.88#ibcon#flushed, iclass 11, count 0 2006.258.01:22:27.88#ibcon#about to write, iclass 11, count 0 2006.258.01:22:27.88#ibcon#wrote, iclass 11, count 0 2006.258.01:22:27.88#ibcon#about to read 3, iclass 11, count 0 2006.258.01:22:27.90#ibcon#read 3, iclass 11, count 0 2006.258.01:22:27.90#ibcon#about to read 4, iclass 11, count 0 2006.258.01:22:27.90#ibcon#read 4, iclass 11, count 0 2006.258.01:22:27.90#ibcon#about to read 5, iclass 11, count 0 2006.258.01:22:27.90#ibcon#read 5, iclass 11, count 0 2006.258.01:22:27.90#ibcon#about to read 6, iclass 11, count 0 2006.258.01:22:27.90#ibcon#read 6, iclass 11, count 0 2006.258.01:22:27.90#ibcon#end of sib2, iclass 11, count 0 2006.258.01:22:27.90#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:22:27.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:22:27.90#ibcon#[25=USB\r\n] 2006.258.01:22:27.90#ibcon#*before write, iclass 11, count 0 2006.258.01:22:27.90#ibcon#enter sib2, iclass 11, count 0 2006.258.01:22:27.90#ibcon#flushed, iclass 11, count 0 2006.258.01:22:27.90#ibcon#about to write, iclass 11, count 0 2006.258.01:22:27.90#ibcon#wrote, iclass 11, count 0 2006.258.01:22:27.90#ibcon#about to read 3, iclass 11, count 0 2006.258.01:22:27.93#ibcon#read 3, iclass 11, count 0 2006.258.01:22:27.93#ibcon#about to read 4, iclass 11, count 0 2006.258.01:22:27.93#ibcon#read 4, iclass 11, count 0 2006.258.01:22:27.93#ibcon#about to read 5, iclass 11, count 0 2006.258.01:22:27.93#ibcon#read 5, iclass 11, count 0 2006.258.01:22:27.93#ibcon#about to read 6, iclass 11, count 0 2006.258.01:22:27.93#ibcon#read 6, iclass 11, count 0 2006.258.01:22:27.93#ibcon#end of sib2, iclass 11, count 0 2006.258.01:22:27.93#ibcon#*after write, iclass 11, count 0 2006.258.01:22:27.93#ibcon#*before return 0, iclass 11, count 0 2006.258.01:22:27.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:27.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:27.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:22:27.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:22:27.93$vck44/valo=6,814.99 2006.258.01:22:27.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.258.01:22:27.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.258.01:22:27.93#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:27.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:27.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:27.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:27.93#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:22:27.93#ibcon#first serial, iclass 13, count 0 2006.258.01:22:27.93#ibcon#enter sib2, iclass 13, count 0 2006.258.01:22:27.93#ibcon#flushed, iclass 13, count 0 2006.258.01:22:27.93#ibcon#about to write, iclass 13, count 0 2006.258.01:22:27.93#ibcon#wrote, iclass 13, count 0 2006.258.01:22:27.93#ibcon#about to read 3, iclass 13, count 0 2006.258.01:22:27.95#ibcon#read 3, iclass 13, count 0 2006.258.01:22:27.95#ibcon#about to read 4, iclass 13, count 0 2006.258.01:22:27.95#ibcon#read 4, iclass 13, count 0 2006.258.01:22:27.95#ibcon#about to read 5, iclass 13, count 0 2006.258.01:22:27.95#ibcon#read 5, iclass 13, count 0 2006.258.01:22:27.95#ibcon#about to read 6, iclass 13, count 0 2006.258.01:22:27.95#ibcon#read 6, iclass 13, count 0 2006.258.01:22:27.95#ibcon#end of sib2, iclass 13, count 0 2006.258.01:22:27.95#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:22:27.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:22:27.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.01:22:27.95#ibcon#*before write, iclass 13, count 0 2006.258.01:22:27.95#ibcon#enter sib2, iclass 13, count 0 2006.258.01:22:27.95#ibcon#flushed, iclass 13, count 0 2006.258.01:22:27.95#ibcon#about to write, iclass 13, count 0 2006.258.01:22:27.95#ibcon#wrote, iclass 13, count 0 2006.258.01:22:27.95#ibcon#about to read 3, iclass 13, count 0 2006.258.01:22:27.99#ibcon#read 3, iclass 13, count 0 2006.258.01:22:27.99#ibcon#about to read 4, iclass 13, count 0 2006.258.01:22:27.99#ibcon#read 4, iclass 13, count 0 2006.258.01:22:27.99#ibcon#about to read 5, iclass 13, count 0 2006.258.01:22:27.99#ibcon#read 5, iclass 13, count 0 2006.258.01:22:27.99#ibcon#about to read 6, iclass 13, count 0 2006.258.01:22:27.99#ibcon#read 6, iclass 13, count 0 2006.258.01:22:27.99#ibcon#end of sib2, iclass 13, count 0 2006.258.01:22:27.99#ibcon#*after write, iclass 13, count 0 2006.258.01:22:27.99#ibcon#*before return 0, iclass 13, count 0 2006.258.01:22:27.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:27.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:27.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:22:27.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:22:27.99$vck44/va=6,4 2006.258.01:22:27.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.258.01:22:27.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.258.01:22:27.99#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:27.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:28.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:28.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:28.05#ibcon#enter wrdev, iclass 15, count 2 2006.258.01:22:28.05#ibcon#first serial, iclass 15, count 2 2006.258.01:22:28.05#ibcon#enter sib2, iclass 15, count 2 2006.258.01:22:28.05#ibcon#flushed, iclass 15, count 2 2006.258.01:22:28.05#ibcon#about to write, iclass 15, count 2 2006.258.01:22:28.05#ibcon#wrote, iclass 15, count 2 2006.258.01:22:28.05#ibcon#about to read 3, iclass 15, count 2 2006.258.01:22:28.07#ibcon#read 3, iclass 15, count 2 2006.258.01:22:28.07#ibcon#about to read 4, iclass 15, count 2 2006.258.01:22:28.07#ibcon#read 4, iclass 15, count 2 2006.258.01:22:28.07#ibcon#about to read 5, iclass 15, count 2 2006.258.01:22:28.07#ibcon#read 5, iclass 15, count 2 2006.258.01:22:28.07#ibcon#about to read 6, iclass 15, count 2 2006.258.01:22:28.07#ibcon#read 6, iclass 15, count 2 2006.258.01:22:28.07#ibcon#end of sib2, iclass 15, count 2 2006.258.01:22:28.07#ibcon#*mode == 0, iclass 15, count 2 2006.258.01:22:28.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.258.01:22:28.07#ibcon#[25=AT06-04\r\n] 2006.258.01:22:28.07#ibcon#*before write, iclass 15, count 2 2006.258.01:22:28.07#ibcon#enter sib2, iclass 15, count 2 2006.258.01:22:28.07#ibcon#flushed, iclass 15, count 2 2006.258.01:22:28.07#ibcon#about to write, iclass 15, count 2 2006.258.01:22:28.07#ibcon#wrote, iclass 15, count 2 2006.258.01:22:28.07#ibcon#about to read 3, iclass 15, count 2 2006.258.01:22:28.10#ibcon#read 3, iclass 15, count 2 2006.258.01:22:28.10#ibcon#about to read 4, iclass 15, count 2 2006.258.01:22:28.10#ibcon#read 4, iclass 15, count 2 2006.258.01:22:28.10#ibcon#about to read 5, iclass 15, count 2 2006.258.01:22:28.10#ibcon#read 5, iclass 15, count 2 2006.258.01:22:28.10#ibcon#about to read 6, iclass 15, count 2 2006.258.01:22:28.10#ibcon#read 6, iclass 15, count 2 2006.258.01:22:28.10#ibcon#end of sib2, iclass 15, count 2 2006.258.01:22:28.10#ibcon#*after write, iclass 15, count 2 2006.258.01:22:28.10#ibcon#*before return 0, iclass 15, count 2 2006.258.01:22:28.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:28.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:28.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.258.01:22:28.10#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:28.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:28.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:28.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:28.22#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:22:28.22#ibcon#first serial, iclass 15, count 0 2006.258.01:22:28.22#ibcon#enter sib2, iclass 15, count 0 2006.258.01:22:28.22#ibcon#flushed, iclass 15, count 0 2006.258.01:22:28.22#ibcon#about to write, iclass 15, count 0 2006.258.01:22:28.22#ibcon#wrote, iclass 15, count 0 2006.258.01:22:28.22#ibcon#about to read 3, iclass 15, count 0 2006.258.01:22:28.24#ibcon#read 3, iclass 15, count 0 2006.258.01:22:28.24#ibcon#about to read 4, iclass 15, count 0 2006.258.01:22:28.24#ibcon#read 4, iclass 15, count 0 2006.258.01:22:28.24#ibcon#about to read 5, iclass 15, count 0 2006.258.01:22:28.24#ibcon#read 5, iclass 15, count 0 2006.258.01:22:28.24#ibcon#about to read 6, iclass 15, count 0 2006.258.01:22:28.24#ibcon#read 6, iclass 15, count 0 2006.258.01:22:28.24#ibcon#end of sib2, iclass 15, count 0 2006.258.01:22:28.24#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:22:28.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:22:28.24#ibcon#[25=USB\r\n] 2006.258.01:22:28.24#ibcon#*before write, iclass 15, count 0 2006.258.01:22:28.24#ibcon#enter sib2, iclass 15, count 0 2006.258.01:22:28.24#ibcon#flushed, iclass 15, count 0 2006.258.01:22:28.24#ibcon#about to write, iclass 15, count 0 2006.258.01:22:28.24#ibcon#wrote, iclass 15, count 0 2006.258.01:22:28.24#ibcon#about to read 3, iclass 15, count 0 2006.258.01:22:28.27#ibcon#read 3, iclass 15, count 0 2006.258.01:22:28.27#ibcon#about to read 4, iclass 15, count 0 2006.258.01:22:28.27#ibcon#read 4, iclass 15, count 0 2006.258.01:22:28.27#ibcon#about to read 5, iclass 15, count 0 2006.258.01:22:28.27#ibcon#read 5, iclass 15, count 0 2006.258.01:22:28.27#ibcon#about to read 6, iclass 15, count 0 2006.258.01:22:28.27#ibcon#read 6, iclass 15, count 0 2006.258.01:22:28.27#ibcon#end of sib2, iclass 15, count 0 2006.258.01:22:28.27#ibcon#*after write, iclass 15, count 0 2006.258.01:22:28.27#ibcon#*before return 0, iclass 15, count 0 2006.258.01:22:28.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:28.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:28.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:22:28.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:22:28.27$vck44/valo=7,864.99 2006.258.01:22:28.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.258.01:22:28.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.258.01:22:28.27#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:28.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:28.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:28.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:28.27#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:22:28.27#ibcon#first serial, iclass 17, count 0 2006.258.01:22:28.27#ibcon#enter sib2, iclass 17, count 0 2006.258.01:22:28.27#ibcon#flushed, iclass 17, count 0 2006.258.01:22:28.27#ibcon#about to write, iclass 17, count 0 2006.258.01:22:28.27#ibcon#wrote, iclass 17, count 0 2006.258.01:22:28.27#ibcon#about to read 3, iclass 17, count 0 2006.258.01:22:28.29#ibcon#read 3, iclass 17, count 0 2006.258.01:22:28.29#ibcon#about to read 4, iclass 17, count 0 2006.258.01:22:28.29#ibcon#read 4, iclass 17, count 0 2006.258.01:22:28.29#ibcon#about to read 5, iclass 17, count 0 2006.258.01:22:28.29#ibcon#read 5, iclass 17, count 0 2006.258.01:22:28.29#ibcon#about to read 6, iclass 17, count 0 2006.258.01:22:28.29#ibcon#read 6, iclass 17, count 0 2006.258.01:22:28.29#ibcon#end of sib2, iclass 17, count 0 2006.258.01:22:28.29#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:22:28.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:22:28.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.01:22:28.29#ibcon#*before write, iclass 17, count 0 2006.258.01:22:28.29#ibcon#enter sib2, iclass 17, count 0 2006.258.01:22:28.29#ibcon#flushed, iclass 17, count 0 2006.258.01:22:28.29#ibcon#about to write, iclass 17, count 0 2006.258.01:22:28.29#ibcon#wrote, iclass 17, count 0 2006.258.01:22:28.29#ibcon#about to read 3, iclass 17, count 0 2006.258.01:22:28.33#ibcon#read 3, iclass 17, count 0 2006.258.01:22:28.33#ibcon#about to read 4, iclass 17, count 0 2006.258.01:22:28.33#ibcon#read 4, iclass 17, count 0 2006.258.01:22:28.33#ibcon#about to read 5, iclass 17, count 0 2006.258.01:22:28.33#ibcon#read 5, iclass 17, count 0 2006.258.01:22:28.33#ibcon#about to read 6, iclass 17, count 0 2006.258.01:22:28.33#ibcon#read 6, iclass 17, count 0 2006.258.01:22:28.33#ibcon#end of sib2, iclass 17, count 0 2006.258.01:22:28.33#ibcon#*after write, iclass 17, count 0 2006.258.01:22:28.33#ibcon#*before return 0, iclass 17, count 0 2006.258.01:22:28.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:28.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:28.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:22:28.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:22:28.33$vck44/va=7,4 2006.258.01:22:28.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.258.01:22:28.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.258.01:22:28.33#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:28.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:28.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:28.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:28.39#ibcon#enter wrdev, iclass 19, count 2 2006.258.01:22:28.39#ibcon#first serial, iclass 19, count 2 2006.258.01:22:28.39#ibcon#enter sib2, iclass 19, count 2 2006.258.01:22:28.39#ibcon#flushed, iclass 19, count 2 2006.258.01:22:28.39#ibcon#about to write, iclass 19, count 2 2006.258.01:22:28.39#ibcon#wrote, iclass 19, count 2 2006.258.01:22:28.39#ibcon#about to read 3, iclass 19, count 2 2006.258.01:22:28.41#ibcon#read 3, iclass 19, count 2 2006.258.01:22:28.41#ibcon#about to read 4, iclass 19, count 2 2006.258.01:22:28.41#ibcon#read 4, iclass 19, count 2 2006.258.01:22:28.41#ibcon#about to read 5, iclass 19, count 2 2006.258.01:22:28.41#ibcon#read 5, iclass 19, count 2 2006.258.01:22:28.41#ibcon#about to read 6, iclass 19, count 2 2006.258.01:22:28.41#ibcon#read 6, iclass 19, count 2 2006.258.01:22:28.41#ibcon#end of sib2, iclass 19, count 2 2006.258.01:22:28.41#ibcon#*mode == 0, iclass 19, count 2 2006.258.01:22:28.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.258.01:22:28.41#ibcon#[25=AT07-04\r\n] 2006.258.01:22:28.41#ibcon#*before write, iclass 19, count 2 2006.258.01:22:28.41#ibcon#enter sib2, iclass 19, count 2 2006.258.01:22:28.41#ibcon#flushed, iclass 19, count 2 2006.258.01:22:28.41#ibcon#about to write, iclass 19, count 2 2006.258.01:22:28.41#ibcon#wrote, iclass 19, count 2 2006.258.01:22:28.41#ibcon#about to read 3, iclass 19, count 2 2006.258.01:22:28.44#ibcon#read 3, iclass 19, count 2 2006.258.01:22:28.44#ibcon#about to read 4, iclass 19, count 2 2006.258.01:22:28.44#ibcon#read 4, iclass 19, count 2 2006.258.01:22:28.44#ibcon#about to read 5, iclass 19, count 2 2006.258.01:22:28.44#ibcon#read 5, iclass 19, count 2 2006.258.01:22:28.44#ibcon#about to read 6, iclass 19, count 2 2006.258.01:22:28.44#ibcon#read 6, iclass 19, count 2 2006.258.01:22:28.44#ibcon#end of sib2, iclass 19, count 2 2006.258.01:22:28.44#ibcon#*after write, iclass 19, count 2 2006.258.01:22:28.50#ibcon#*before return 0, iclass 19, count 2 2006.258.01:22:28.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:28.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:28.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.258.01:22:28.50#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:28.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:28.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:28.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:28.61#ibcon#enter wrdev, iclass 19, count 0 2006.258.01:22:28.61#ibcon#first serial, iclass 19, count 0 2006.258.01:22:28.61#ibcon#enter sib2, iclass 19, count 0 2006.258.01:22:28.61#ibcon#flushed, iclass 19, count 0 2006.258.01:22:28.61#ibcon#about to write, iclass 19, count 0 2006.258.01:22:28.61#ibcon#wrote, iclass 19, count 0 2006.258.01:22:28.61#ibcon#about to read 3, iclass 19, count 0 2006.258.01:22:28.63#ibcon#read 3, iclass 19, count 0 2006.258.01:22:28.63#ibcon#about to read 4, iclass 19, count 0 2006.258.01:22:28.63#ibcon#read 4, iclass 19, count 0 2006.258.01:22:28.63#ibcon#about to read 5, iclass 19, count 0 2006.258.01:22:28.63#ibcon#read 5, iclass 19, count 0 2006.258.01:22:28.63#ibcon#about to read 6, iclass 19, count 0 2006.258.01:22:28.63#ibcon#read 6, iclass 19, count 0 2006.258.01:22:28.63#ibcon#end of sib2, iclass 19, count 0 2006.258.01:22:28.63#ibcon#*mode == 0, iclass 19, count 0 2006.258.01:22:28.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.01:22:28.63#ibcon#[25=USB\r\n] 2006.258.01:22:28.63#ibcon#*before write, iclass 19, count 0 2006.258.01:22:28.63#ibcon#enter sib2, iclass 19, count 0 2006.258.01:22:28.63#ibcon#flushed, iclass 19, count 0 2006.258.01:22:28.63#ibcon#about to write, iclass 19, count 0 2006.258.01:22:28.63#ibcon#wrote, iclass 19, count 0 2006.258.01:22:28.63#ibcon#about to read 3, iclass 19, count 0 2006.258.01:22:28.66#ibcon#read 3, iclass 19, count 0 2006.258.01:22:28.66#ibcon#about to read 4, iclass 19, count 0 2006.258.01:22:28.66#ibcon#read 4, iclass 19, count 0 2006.258.01:22:28.66#ibcon#about to read 5, iclass 19, count 0 2006.258.01:22:28.66#ibcon#read 5, iclass 19, count 0 2006.258.01:22:28.66#ibcon#about to read 6, iclass 19, count 0 2006.258.01:22:28.66#ibcon#read 6, iclass 19, count 0 2006.258.01:22:28.66#ibcon#end of sib2, iclass 19, count 0 2006.258.01:22:28.66#ibcon#*after write, iclass 19, count 0 2006.258.01:22:28.66#ibcon#*before return 0, iclass 19, count 0 2006.258.01:22:28.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:28.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:28.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.01:22:28.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.01:22:28.66$vck44/valo=8,884.99 2006.258.01:22:28.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.258.01:22:28.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.258.01:22:28.66#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:28.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:28.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:28.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:28.66#ibcon#enter wrdev, iclass 21, count 0 2006.258.01:22:28.66#ibcon#first serial, iclass 21, count 0 2006.258.01:22:28.66#ibcon#enter sib2, iclass 21, count 0 2006.258.01:22:28.66#ibcon#flushed, iclass 21, count 0 2006.258.01:22:28.66#ibcon#about to write, iclass 21, count 0 2006.258.01:22:28.66#ibcon#wrote, iclass 21, count 0 2006.258.01:22:28.66#ibcon#about to read 3, iclass 21, count 0 2006.258.01:22:28.68#ibcon#read 3, iclass 21, count 0 2006.258.01:22:28.68#ibcon#about to read 4, iclass 21, count 0 2006.258.01:22:28.68#ibcon#read 4, iclass 21, count 0 2006.258.01:22:28.68#ibcon#about to read 5, iclass 21, count 0 2006.258.01:22:28.68#ibcon#read 5, iclass 21, count 0 2006.258.01:22:28.68#ibcon#about to read 6, iclass 21, count 0 2006.258.01:22:28.68#ibcon#read 6, iclass 21, count 0 2006.258.01:22:28.68#ibcon#end of sib2, iclass 21, count 0 2006.258.01:22:28.68#ibcon#*mode == 0, iclass 21, count 0 2006.258.01:22:28.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.01:22:28.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.01:22:28.68#ibcon#*before write, iclass 21, count 0 2006.258.01:22:28.68#ibcon#enter sib2, iclass 21, count 0 2006.258.01:22:28.68#ibcon#flushed, iclass 21, count 0 2006.258.01:22:28.68#ibcon#about to write, iclass 21, count 0 2006.258.01:22:28.68#ibcon#wrote, iclass 21, count 0 2006.258.01:22:28.68#ibcon#about to read 3, iclass 21, count 0 2006.258.01:22:28.72#ibcon#read 3, iclass 21, count 0 2006.258.01:22:28.72#ibcon#about to read 4, iclass 21, count 0 2006.258.01:22:28.72#ibcon#read 4, iclass 21, count 0 2006.258.01:22:28.72#ibcon#about to read 5, iclass 21, count 0 2006.258.01:22:28.72#ibcon#read 5, iclass 21, count 0 2006.258.01:22:28.72#ibcon#about to read 6, iclass 21, count 0 2006.258.01:22:28.72#ibcon#read 6, iclass 21, count 0 2006.258.01:22:28.72#ibcon#end of sib2, iclass 21, count 0 2006.258.01:22:28.72#ibcon#*after write, iclass 21, count 0 2006.258.01:22:28.72#ibcon#*before return 0, iclass 21, count 0 2006.258.01:22:28.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:28.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:28.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.01:22:28.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.01:22:28.72$vck44/va=8,4 2006.258.01:22:28.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.258.01:22:28.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.258.01:22:28.72#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:28.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:22:28.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:22:28.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:22:28.78#ibcon#enter wrdev, iclass 23, count 2 2006.258.01:22:28.78#ibcon#first serial, iclass 23, count 2 2006.258.01:22:28.78#ibcon#enter sib2, iclass 23, count 2 2006.258.01:22:28.78#ibcon#flushed, iclass 23, count 2 2006.258.01:22:28.78#ibcon#about to write, iclass 23, count 2 2006.258.01:22:28.78#ibcon#wrote, iclass 23, count 2 2006.258.01:22:28.78#ibcon#about to read 3, iclass 23, count 2 2006.258.01:22:28.80#ibcon#read 3, iclass 23, count 2 2006.258.01:22:28.80#ibcon#about to read 4, iclass 23, count 2 2006.258.01:22:28.80#ibcon#read 4, iclass 23, count 2 2006.258.01:22:28.80#ibcon#about to read 5, iclass 23, count 2 2006.258.01:22:28.80#ibcon#read 5, iclass 23, count 2 2006.258.01:22:28.80#ibcon#about to read 6, iclass 23, count 2 2006.258.01:22:28.80#ibcon#read 6, iclass 23, count 2 2006.258.01:22:28.80#ibcon#end of sib2, iclass 23, count 2 2006.258.01:22:28.80#ibcon#*mode == 0, iclass 23, count 2 2006.258.01:22:28.80#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.258.01:22:28.80#ibcon#[25=AT08-04\r\n] 2006.258.01:22:28.80#ibcon#*before write, iclass 23, count 2 2006.258.01:22:28.80#ibcon#enter sib2, iclass 23, count 2 2006.258.01:22:28.80#ibcon#flushed, iclass 23, count 2 2006.258.01:22:28.80#ibcon#about to write, iclass 23, count 2 2006.258.01:22:28.80#ibcon#wrote, iclass 23, count 2 2006.258.01:22:28.80#ibcon#about to read 3, iclass 23, count 2 2006.258.01:22:28.83#ibcon#read 3, iclass 23, count 2 2006.258.01:22:28.83#ibcon#about to read 4, iclass 23, count 2 2006.258.01:22:28.83#ibcon#read 4, iclass 23, count 2 2006.258.01:22:28.83#ibcon#about to read 5, iclass 23, count 2 2006.258.01:22:28.83#ibcon#read 5, iclass 23, count 2 2006.258.01:22:28.83#ibcon#about to read 6, iclass 23, count 2 2006.258.01:22:28.83#ibcon#read 6, iclass 23, count 2 2006.258.01:22:28.83#ibcon#end of sib2, iclass 23, count 2 2006.258.01:22:28.83#ibcon#*after write, iclass 23, count 2 2006.258.01:22:28.83#ibcon#*before return 0, iclass 23, count 2 2006.258.01:22:28.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:22:28.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:22:28.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.258.01:22:28.83#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:28.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:22:28.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:22:28.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:22:28.95#ibcon#enter wrdev, iclass 23, count 0 2006.258.01:22:28.95#ibcon#first serial, iclass 23, count 0 2006.258.01:22:28.95#ibcon#enter sib2, iclass 23, count 0 2006.258.01:22:28.95#ibcon#flushed, iclass 23, count 0 2006.258.01:22:28.95#ibcon#about to write, iclass 23, count 0 2006.258.01:22:28.95#ibcon#wrote, iclass 23, count 0 2006.258.01:22:28.95#ibcon#about to read 3, iclass 23, count 0 2006.258.01:22:28.97#ibcon#read 3, iclass 23, count 0 2006.258.01:22:28.97#ibcon#about to read 4, iclass 23, count 0 2006.258.01:22:28.97#ibcon#read 4, iclass 23, count 0 2006.258.01:22:28.97#ibcon#about to read 5, iclass 23, count 0 2006.258.01:22:28.97#ibcon#read 5, iclass 23, count 0 2006.258.01:22:28.97#ibcon#about to read 6, iclass 23, count 0 2006.258.01:22:28.97#ibcon#read 6, iclass 23, count 0 2006.258.01:22:28.97#ibcon#end of sib2, iclass 23, count 0 2006.258.01:22:28.97#ibcon#*mode == 0, iclass 23, count 0 2006.258.01:22:28.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.01:22:28.97#ibcon#[25=USB\r\n] 2006.258.01:22:28.97#ibcon#*before write, iclass 23, count 0 2006.258.01:22:28.97#ibcon#enter sib2, iclass 23, count 0 2006.258.01:22:28.97#ibcon#flushed, iclass 23, count 0 2006.258.01:22:28.97#ibcon#about to write, iclass 23, count 0 2006.258.01:22:28.97#ibcon#wrote, iclass 23, count 0 2006.258.01:22:28.97#ibcon#about to read 3, iclass 23, count 0 2006.258.01:22:29.00#ibcon#read 3, iclass 23, count 0 2006.258.01:22:29.00#ibcon#about to read 4, iclass 23, count 0 2006.258.01:22:29.00#ibcon#read 4, iclass 23, count 0 2006.258.01:22:29.00#ibcon#about to read 5, iclass 23, count 0 2006.258.01:22:29.00#ibcon#read 5, iclass 23, count 0 2006.258.01:22:29.00#ibcon#about to read 6, iclass 23, count 0 2006.258.01:22:29.00#ibcon#read 6, iclass 23, count 0 2006.258.01:22:29.00#ibcon#end of sib2, iclass 23, count 0 2006.258.01:22:29.00#ibcon#*after write, iclass 23, count 0 2006.258.01:22:29.00#ibcon#*before return 0, iclass 23, count 0 2006.258.01:22:29.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:22:29.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:22:29.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.01:22:29.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.01:22:29.00$vck44/vblo=1,629.99 2006.258.01:22:29.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.01:22:29.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.01:22:29.00#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:29.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:22:29.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:22:29.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:22:29.00#ibcon#enter wrdev, iclass 25, count 0 2006.258.01:22:29.00#ibcon#first serial, iclass 25, count 0 2006.258.01:22:29.00#ibcon#enter sib2, iclass 25, count 0 2006.258.01:22:29.00#ibcon#flushed, iclass 25, count 0 2006.258.01:22:29.00#ibcon#about to write, iclass 25, count 0 2006.258.01:22:29.00#ibcon#wrote, iclass 25, count 0 2006.258.01:22:29.00#ibcon#about to read 3, iclass 25, count 0 2006.258.01:22:29.02#ibcon#read 3, iclass 25, count 0 2006.258.01:22:29.02#ibcon#about to read 4, iclass 25, count 0 2006.258.01:22:29.02#ibcon#read 4, iclass 25, count 0 2006.258.01:22:29.02#ibcon#about to read 5, iclass 25, count 0 2006.258.01:22:29.02#ibcon#read 5, iclass 25, count 0 2006.258.01:22:29.02#ibcon#about to read 6, iclass 25, count 0 2006.258.01:22:29.02#ibcon#read 6, iclass 25, count 0 2006.258.01:22:29.02#ibcon#end of sib2, iclass 25, count 0 2006.258.01:22:29.02#ibcon#*mode == 0, iclass 25, count 0 2006.258.01:22:29.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.01:22:29.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.01:22:29.02#ibcon#*before write, iclass 25, count 0 2006.258.01:22:29.02#ibcon#enter sib2, iclass 25, count 0 2006.258.01:22:29.02#ibcon#flushed, iclass 25, count 0 2006.258.01:22:29.02#ibcon#about to write, iclass 25, count 0 2006.258.01:22:29.02#ibcon#wrote, iclass 25, count 0 2006.258.01:22:29.02#ibcon#about to read 3, iclass 25, count 0 2006.258.01:22:29.06#ibcon#read 3, iclass 25, count 0 2006.258.01:22:29.06#ibcon#about to read 4, iclass 25, count 0 2006.258.01:22:29.06#ibcon#read 4, iclass 25, count 0 2006.258.01:22:29.06#ibcon#about to read 5, iclass 25, count 0 2006.258.01:22:29.06#ibcon#read 5, iclass 25, count 0 2006.258.01:22:29.06#ibcon#about to read 6, iclass 25, count 0 2006.258.01:22:29.06#ibcon#read 6, iclass 25, count 0 2006.258.01:22:29.06#ibcon#end of sib2, iclass 25, count 0 2006.258.01:22:29.06#ibcon#*after write, iclass 25, count 0 2006.258.01:22:29.06#ibcon#*before return 0, iclass 25, count 0 2006.258.01:22:29.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:22:29.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:22:29.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.01:22:29.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.01:22:29.06$vck44/vb=1,4 2006.258.01:22:29.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.258.01:22:29.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.258.01:22:29.06#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:29.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:22:29.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:22:29.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:22:29.06#ibcon#enter wrdev, iclass 27, count 2 2006.258.01:22:29.06#ibcon#first serial, iclass 27, count 2 2006.258.01:22:29.06#ibcon#enter sib2, iclass 27, count 2 2006.258.01:22:29.06#ibcon#flushed, iclass 27, count 2 2006.258.01:22:29.06#ibcon#about to write, iclass 27, count 2 2006.258.01:22:29.06#ibcon#wrote, iclass 27, count 2 2006.258.01:22:29.06#ibcon#about to read 3, iclass 27, count 2 2006.258.01:22:29.08#ibcon#read 3, iclass 27, count 2 2006.258.01:22:29.08#ibcon#about to read 4, iclass 27, count 2 2006.258.01:22:29.08#ibcon#read 4, iclass 27, count 2 2006.258.01:22:29.08#ibcon#about to read 5, iclass 27, count 2 2006.258.01:22:29.08#ibcon#read 5, iclass 27, count 2 2006.258.01:22:29.08#ibcon#about to read 6, iclass 27, count 2 2006.258.01:22:29.08#ibcon#read 6, iclass 27, count 2 2006.258.01:22:29.08#ibcon#end of sib2, iclass 27, count 2 2006.258.01:22:29.08#ibcon#*mode == 0, iclass 27, count 2 2006.258.01:22:29.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.258.01:22:29.08#ibcon#[27=AT01-04\r\n] 2006.258.01:22:29.08#ibcon#*before write, iclass 27, count 2 2006.258.01:22:29.08#ibcon#enter sib2, iclass 27, count 2 2006.258.01:22:29.08#ibcon#flushed, iclass 27, count 2 2006.258.01:22:29.08#ibcon#about to write, iclass 27, count 2 2006.258.01:22:29.08#ibcon#wrote, iclass 27, count 2 2006.258.01:22:29.08#ibcon#about to read 3, iclass 27, count 2 2006.258.01:22:29.11#ibcon#read 3, iclass 27, count 2 2006.258.01:22:29.11#ibcon#about to read 4, iclass 27, count 2 2006.258.01:22:29.11#ibcon#read 4, iclass 27, count 2 2006.258.01:22:29.11#ibcon#about to read 5, iclass 27, count 2 2006.258.01:22:29.11#ibcon#read 5, iclass 27, count 2 2006.258.01:22:29.11#ibcon#about to read 6, iclass 27, count 2 2006.258.01:22:29.11#ibcon#read 6, iclass 27, count 2 2006.258.01:22:29.11#ibcon#end of sib2, iclass 27, count 2 2006.258.01:22:29.11#ibcon#*after write, iclass 27, count 2 2006.258.01:22:29.11#ibcon#*before return 0, iclass 27, count 2 2006.258.01:22:29.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:22:29.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:22:29.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.258.01:22:29.11#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:29.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:22:29.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:22:29.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:22:29.23#ibcon#enter wrdev, iclass 27, count 0 2006.258.01:22:29.23#ibcon#first serial, iclass 27, count 0 2006.258.01:22:29.23#ibcon#enter sib2, iclass 27, count 0 2006.258.01:22:29.23#ibcon#flushed, iclass 27, count 0 2006.258.01:22:29.23#ibcon#about to write, iclass 27, count 0 2006.258.01:22:29.23#ibcon#wrote, iclass 27, count 0 2006.258.01:22:29.23#ibcon#about to read 3, iclass 27, count 0 2006.258.01:22:29.25#ibcon#read 3, iclass 27, count 0 2006.258.01:22:29.25#ibcon#about to read 4, iclass 27, count 0 2006.258.01:22:29.25#ibcon#read 4, iclass 27, count 0 2006.258.01:22:29.25#ibcon#about to read 5, iclass 27, count 0 2006.258.01:22:29.25#ibcon#read 5, iclass 27, count 0 2006.258.01:22:29.25#ibcon#about to read 6, iclass 27, count 0 2006.258.01:22:29.25#ibcon#read 6, iclass 27, count 0 2006.258.01:22:29.25#ibcon#end of sib2, iclass 27, count 0 2006.258.01:22:29.25#ibcon#*mode == 0, iclass 27, count 0 2006.258.01:22:29.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.01:22:29.25#ibcon#[27=USB\r\n] 2006.258.01:22:29.25#ibcon#*before write, iclass 27, count 0 2006.258.01:22:29.25#ibcon#enter sib2, iclass 27, count 0 2006.258.01:22:29.25#ibcon#flushed, iclass 27, count 0 2006.258.01:22:29.25#ibcon#about to write, iclass 27, count 0 2006.258.01:22:29.25#ibcon#wrote, iclass 27, count 0 2006.258.01:22:29.25#ibcon#about to read 3, iclass 27, count 0 2006.258.01:22:29.28#ibcon#read 3, iclass 27, count 0 2006.258.01:22:29.28#ibcon#about to read 4, iclass 27, count 0 2006.258.01:22:29.28#ibcon#read 4, iclass 27, count 0 2006.258.01:22:29.28#ibcon#about to read 5, iclass 27, count 0 2006.258.01:22:29.28#ibcon#read 5, iclass 27, count 0 2006.258.01:22:29.28#ibcon#about to read 6, iclass 27, count 0 2006.258.01:22:29.28#ibcon#read 6, iclass 27, count 0 2006.258.01:22:29.28#ibcon#end of sib2, iclass 27, count 0 2006.258.01:22:29.28#ibcon#*after write, iclass 27, count 0 2006.258.01:22:29.28#ibcon#*before return 0, iclass 27, count 0 2006.258.01:22:29.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:22:29.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:22:29.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.01:22:29.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.01:22:29.28$vck44/vblo=2,634.99 2006.258.01:22:29.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.01:22:29.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.01:22:29.28#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:29.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:29.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:29.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:29.28#ibcon#enter wrdev, iclass 29, count 0 2006.258.01:22:29.28#ibcon#first serial, iclass 29, count 0 2006.258.01:22:29.28#ibcon#enter sib2, iclass 29, count 0 2006.258.01:22:29.28#ibcon#flushed, iclass 29, count 0 2006.258.01:22:29.28#ibcon#about to write, iclass 29, count 0 2006.258.01:22:29.28#ibcon#wrote, iclass 29, count 0 2006.258.01:22:29.28#ibcon#about to read 3, iclass 29, count 0 2006.258.01:22:29.30#ibcon#read 3, iclass 29, count 0 2006.258.01:22:29.30#ibcon#about to read 4, iclass 29, count 0 2006.258.01:22:29.30#ibcon#read 4, iclass 29, count 0 2006.258.01:22:29.30#ibcon#about to read 5, iclass 29, count 0 2006.258.01:22:29.30#ibcon#read 5, iclass 29, count 0 2006.258.01:22:29.30#ibcon#about to read 6, iclass 29, count 0 2006.258.01:22:29.30#ibcon#read 6, iclass 29, count 0 2006.258.01:22:29.30#ibcon#end of sib2, iclass 29, count 0 2006.258.01:22:29.30#ibcon#*mode == 0, iclass 29, count 0 2006.258.01:22:29.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.01:22:29.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.01:22:29.30#ibcon#*before write, iclass 29, count 0 2006.258.01:22:29.30#ibcon#enter sib2, iclass 29, count 0 2006.258.01:22:29.30#ibcon#flushed, iclass 29, count 0 2006.258.01:22:29.30#ibcon#about to write, iclass 29, count 0 2006.258.01:22:29.30#ibcon#wrote, iclass 29, count 0 2006.258.01:22:29.30#ibcon#about to read 3, iclass 29, count 0 2006.258.01:22:29.34#ibcon#read 3, iclass 29, count 0 2006.258.01:22:29.34#ibcon#about to read 4, iclass 29, count 0 2006.258.01:22:29.34#ibcon#read 4, iclass 29, count 0 2006.258.01:22:29.34#ibcon#about to read 5, iclass 29, count 0 2006.258.01:22:29.34#ibcon#read 5, iclass 29, count 0 2006.258.01:22:29.34#ibcon#about to read 6, iclass 29, count 0 2006.258.01:22:29.34#ibcon#read 6, iclass 29, count 0 2006.258.01:22:29.34#ibcon#end of sib2, iclass 29, count 0 2006.258.01:22:29.34#ibcon#*after write, iclass 29, count 0 2006.258.01:22:29.34#ibcon#*before return 0, iclass 29, count 0 2006.258.01:22:29.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:29.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:22:29.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.01:22:29.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.01:22:29.34$vck44/vb=2,5 2006.258.01:22:29.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.01:22:29.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.01:22:29.34#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:29.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:29.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:29.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:29.40#ibcon#enter wrdev, iclass 31, count 2 2006.258.01:22:29.40#ibcon#first serial, iclass 31, count 2 2006.258.01:22:29.40#ibcon#enter sib2, iclass 31, count 2 2006.258.01:22:29.40#ibcon#flushed, iclass 31, count 2 2006.258.01:22:29.40#ibcon#about to write, iclass 31, count 2 2006.258.01:22:29.40#ibcon#wrote, iclass 31, count 2 2006.258.01:22:29.40#ibcon#about to read 3, iclass 31, count 2 2006.258.01:22:29.42#ibcon#read 3, iclass 31, count 2 2006.258.01:22:29.42#ibcon#about to read 4, iclass 31, count 2 2006.258.01:22:29.42#ibcon#read 4, iclass 31, count 2 2006.258.01:22:29.42#ibcon#about to read 5, iclass 31, count 2 2006.258.01:22:29.42#ibcon#read 5, iclass 31, count 2 2006.258.01:22:29.42#ibcon#about to read 6, iclass 31, count 2 2006.258.01:22:29.42#ibcon#read 6, iclass 31, count 2 2006.258.01:22:29.42#ibcon#end of sib2, iclass 31, count 2 2006.258.01:22:29.42#ibcon#*mode == 0, iclass 31, count 2 2006.258.01:22:29.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.01:22:29.42#ibcon#[27=AT02-05\r\n] 2006.258.01:22:29.42#ibcon#*before write, iclass 31, count 2 2006.258.01:22:29.42#ibcon#enter sib2, iclass 31, count 2 2006.258.01:22:29.42#ibcon#flushed, iclass 31, count 2 2006.258.01:22:29.42#ibcon#about to write, iclass 31, count 2 2006.258.01:22:29.42#ibcon#wrote, iclass 31, count 2 2006.258.01:22:29.42#ibcon#about to read 3, iclass 31, count 2 2006.258.01:22:29.45#ibcon#read 3, iclass 31, count 2 2006.258.01:22:29.52#ibcon#about to read 4, iclass 31, count 2 2006.258.01:22:29.52#ibcon#read 4, iclass 31, count 2 2006.258.01:22:29.52#ibcon#about to read 5, iclass 31, count 2 2006.258.01:22:29.52#ibcon#read 5, iclass 31, count 2 2006.258.01:22:29.52#ibcon#about to read 6, iclass 31, count 2 2006.258.01:22:29.52#ibcon#read 6, iclass 31, count 2 2006.258.01:22:29.52#ibcon#end of sib2, iclass 31, count 2 2006.258.01:22:29.52#ibcon#*after write, iclass 31, count 2 2006.258.01:22:29.52#ibcon#*before return 0, iclass 31, count 2 2006.258.01:22:29.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:29.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:22:29.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.01:22:29.52#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:29.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:29.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:29.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:29.64#ibcon#enter wrdev, iclass 31, count 0 2006.258.01:22:29.64#ibcon#first serial, iclass 31, count 0 2006.258.01:22:29.64#ibcon#enter sib2, iclass 31, count 0 2006.258.01:22:29.64#ibcon#flushed, iclass 31, count 0 2006.258.01:22:29.64#ibcon#about to write, iclass 31, count 0 2006.258.01:22:29.64#ibcon#wrote, iclass 31, count 0 2006.258.01:22:29.64#ibcon#about to read 3, iclass 31, count 0 2006.258.01:22:29.66#ibcon#read 3, iclass 31, count 0 2006.258.01:22:29.66#ibcon#about to read 4, iclass 31, count 0 2006.258.01:22:29.66#ibcon#read 4, iclass 31, count 0 2006.258.01:22:29.66#ibcon#about to read 5, iclass 31, count 0 2006.258.01:22:29.66#ibcon#read 5, iclass 31, count 0 2006.258.01:22:29.66#ibcon#about to read 6, iclass 31, count 0 2006.258.01:22:29.66#ibcon#read 6, iclass 31, count 0 2006.258.01:22:29.66#ibcon#end of sib2, iclass 31, count 0 2006.258.01:22:29.66#ibcon#*mode == 0, iclass 31, count 0 2006.258.01:22:29.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.01:22:29.66#ibcon#[27=USB\r\n] 2006.258.01:22:29.66#ibcon#*before write, iclass 31, count 0 2006.258.01:22:29.66#ibcon#enter sib2, iclass 31, count 0 2006.258.01:22:29.66#ibcon#flushed, iclass 31, count 0 2006.258.01:22:29.66#ibcon#about to write, iclass 31, count 0 2006.258.01:22:29.66#ibcon#wrote, iclass 31, count 0 2006.258.01:22:29.66#ibcon#about to read 3, iclass 31, count 0 2006.258.01:22:29.69#ibcon#read 3, iclass 31, count 0 2006.258.01:22:29.69#ibcon#about to read 4, iclass 31, count 0 2006.258.01:22:29.69#ibcon#read 4, iclass 31, count 0 2006.258.01:22:29.69#ibcon#about to read 5, iclass 31, count 0 2006.258.01:22:29.69#ibcon#read 5, iclass 31, count 0 2006.258.01:22:29.69#ibcon#about to read 6, iclass 31, count 0 2006.258.01:22:29.69#ibcon#read 6, iclass 31, count 0 2006.258.01:22:29.69#ibcon#end of sib2, iclass 31, count 0 2006.258.01:22:29.69#ibcon#*after write, iclass 31, count 0 2006.258.01:22:29.69#ibcon#*before return 0, iclass 31, count 0 2006.258.01:22:29.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:29.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:22:29.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.01:22:29.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.01:22:29.69$vck44/vblo=3,649.99 2006.258.01:22:29.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.01:22:29.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.01:22:29.69#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:29.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:29.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:29.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:29.69#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:22:29.69#ibcon#first serial, iclass 33, count 0 2006.258.01:22:29.69#ibcon#enter sib2, iclass 33, count 0 2006.258.01:22:29.69#ibcon#flushed, iclass 33, count 0 2006.258.01:22:29.69#ibcon#about to write, iclass 33, count 0 2006.258.01:22:29.69#ibcon#wrote, iclass 33, count 0 2006.258.01:22:29.69#ibcon#about to read 3, iclass 33, count 0 2006.258.01:22:29.71#ibcon#read 3, iclass 33, count 0 2006.258.01:22:29.71#ibcon#about to read 4, iclass 33, count 0 2006.258.01:22:29.71#ibcon#read 4, iclass 33, count 0 2006.258.01:22:29.71#ibcon#about to read 5, iclass 33, count 0 2006.258.01:22:29.71#ibcon#read 5, iclass 33, count 0 2006.258.01:22:29.71#ibcon#about to read 6, iclass 33, count 0 2006.258.01:22:29.71#ibcon#read 6, iclass 33, count 0 2006.258.01:22:29.71#ibcon#end of sib2, iclass 33, count 0 2006.258.01:22:29.71#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:22:29.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:22:29.71#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.01:22:29.71#ibcon#*before write, iclass 33, count 0 2006.258.01:22:29.71#ibcon#enter sib2, iclass 33, count 0 2006.258.01:22:29.71#ibcon#flushed, iclass 33, count 0 2006.258.01:22:29.71#ibcon#about to write, iclass 33, count 0 2006.258.01:22:29.71#ibcon#wrote, iclass 33, count 0 2006.258.01:22:29.71#ibcon#about to read 3, iclass 33, count 0 2006.258.01:22:29.75#ibcon#read 3, iclass 33, count 0 2006.258.01:22:29.75#ibcon#about to read 4, iclass 33, count 0 2006.258.01:22:29.75#ibcon#read 4, iclass 33, count 0 2006.258.01:22:29.75#ibcon#about to read 5, iclass 33, count 0 2006.258.01:22:29.75#ibcon#read 5, iclass 33, count 0 2006.258.01:22:29.75#ibcon#about to read 6, iclass 33, count 0 2006.258.01:22:29.75#ibcon#read 6, iclass 33, count 0 2006.258.01:22:29.75#ibcon#end of sib2, iclass 33, count 0 2006.258.01:22:29.75#ibcon#*after write, iclass 33, count 0 2006.258.01:22:29.75#ibcon#*before return 0, iclass 33, count 0 2006.258.01:22:29.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:29.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:22:29.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:22:29.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:22:29.75$vck44/vb=3,4 2006.258.01:22:29.75#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.01:22:29.75#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.01:22:29.75#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:29.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:29.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:29.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:29.81#ibcon#enter wrdev, iclass 35, count 2 2006.258.01:22:29.81#ibcon#first serial, iclass 35, count 2 2006.258.01:22:29.81#ibcon#enter sib2, iclass 35, count 2 2006.258.01:22:29.81#ibcon#flushed, iclass 35, count 2 2006.258.01:22:29.81#ibcon#about to write, iclass 35, count 2 2006.258.01:22:29.81#ibcon#wrote, iclass 35, count 2 2006.258.01:22:29.81#ibcon#about to read 3, iclass 35, count 2 2006.258.01:22:29.83#ibcon#read 3, iclass 35, count 2 2006.258.01:22:29.83#ibcon#about to read 4, iclass 35, count 2 2006.258.01:22:29.83#ibcon#read 4, iclass 35, count 2 2006.258.01:22:29.83#ibcon#about to read 5, iclass 35, count 2 2006.258.01:22:29.83#ibcon#read 5, iclass 35, count 2 2006.258.01:22:29.83#ibcon#about to read 6, iclass 35, count 2 2006.258.01:22:29.83#ibcon#read 6, iclass 35, count 2 2006.258.01:22:29.83#ibcon#end of sib2, iclass 35, count 2 2006.258.01:22:29.83#ibcon#*mode == 0, iclass 35, count 2 2006.258.01:22:29.83#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.01:22:29.83#ibcon#[27=AT03-04\r\n] 2006.258.01:22:29.83#ibcon#*before write, iclass 35, count 2 2006.258.01:22:29.83#ibcon#enter sib2, iclass 35, count 2 2006.258.01:22:29.83#ibcon#flushed, iclass 35, count 2 2006.258.01:22:29.83#ibcon#about to write, iclass 35, count 2 2006.258.01:22:29.83#ibcon#wrote, iclass 35, count 2 2006.258.01:22:29.83#ibcon#about to read 3, iclass 35, count 2 2006.258.01:22:29.86#ibcon#read 3, iclass 35, count 2 2006.258.01:22:29.86#ibcon#about to read 4, iclass 35, count 2 2006.258.01:22:29.86#ibcon#read 4, iclass 35, count 2 2006.258.01:22:29.86#ibcon#about to read 5, iclass 35, count 2 2006.258.01:22:29.86#ibcon#read 5, iclass 35, count 2 2006.258.01:22:29.86#ibcon#about to read 6, iclass 35, count 2 2006.258.01:22:29.86#ibcon#read 6, iclass 35, count 2 2006.258.01:22:29.86#ibcon#end of sib2, iclass 35, count 2 2006.258.01:22:29.86#ibcon#*after write, iclass 35, count 2 2006.258.01:22:29.86#ibcon#*before return 0, iclass 35, count 2 2006.258.01:22:29.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:29.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:22:29.86#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.01:22:29.86#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:29.86#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:29.98#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:29.98#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:29.98#ibcon#enter wrdev, iclass 35, count 0 2006.258.01:22:29.98#ibcon#first serial, iclass 35, count 0 2006.258.01:22:29.98#ibcon#enter sib2, iclass 35, count 0 2006.258.01:22:29.98#ibcon#flushed, iclass 35, count 0 2006.258.01:22:29.98#ibcon#about to write, iclass 35, count 0 2006.258.01:22:29.98#ibcon#wrote, iclass 35, count 0 2006.258.01:22:29.98#ibcon#about to read 3, iclass 35, count 0 2006.258.01:22:30.00#ibcon#read 3, iclass 35, count 0 2006.258.01:22:30.00#ibcon#about to read 4, iclass 35, count 0 2006.258.01:22:30.00#ibcon#read 4, iclass 35, count 0 2006.258.01:22:30.00#ibcon#about to read 5, iclass 35, count 0 2006.258.01:22:30.00#ibcon#read 5, iclass 35, count 0 2006.258.01:22:30.00#ibcon#about to read 6, iclass 35, count 0 2006.258.01:22:30.00#ibcon#read 6, iclass 35, count 0 2006.258.01:22:30.00#ibcon#end of sib2, iclass 35, count 0 2006.258.01:22:30.00#ibcon#*mode == 0, iclass 35, count 0 2006.258.01:22:30.00#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.01:22:30.00#ibcon#[27=USB\r\n] 2006.258.01:22:30.00#ibcon#*before write, iclass 35, count 0 2006.258.01:22:30.00#ibcon#enter sib2, iclass 35, count 0 2006.258.01:22:30.00#ibcon#flushed, iclass 35, count 0 2006.258.01:22:30.00#ibcon#about to write, iclass 35, count 0 2006.258.01:22:30.00#ibcon#wrote, iclass 35, count 0 2006.258.01:22:30.00#ibcon#about to read 3, iclass 35, count 0 2006.258.01:22:30.03#ibcon#read 3, iclass 35, count 0 2006.258.01:22:30.03#ibcon#about to read 4, iclass 35, count 0 2006.258.01:22:30.03#ibcon#read 4, iclass 35, count 0 2006.258.01:22:30.03#ibcon#about to read 5, iclass 35, count 0 2006.258.01:22:30.03#ibcon#read 5, iclass 35, count 0 2006.258.01:22:30.03#ibcon#about to read 6, iclass 35, count 0 2006.258.01:22:30.03#ibcon#read 6, iclass 35, count 0 2006.258.01:22:30.03#ibcon#end of sib2, iclass 35, count 0 2006.258.01:22:30.03#ibcon#*after write, iclass 35, count 0 2006.258.01:22:30.03#ibcon#*before return 0, iclass 35, count 0 2006.258.01:22:30.03#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:30.03#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:22:30.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.01:22:30.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.01:22:30.03$vck44/vblo=4,679.99 2006.258.01:22:30.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.01:22:30.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.01:22:30.03#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:30.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:30.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:30.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:30.03#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:22:30.03#ibcon#first serial, iclass 37, count 0 2006.258.01:22:30.03#ibcon#enter sib2, iclass 37, count 0 2006.258.01:22:30.03#ibcon#flushed, iclass 37, count 0 2006.258.01:22:30.03#ibcon#about to write, iclass 37, count 0 2006.258.01:22:30.03#ibcon#wrote, iclass 37, count 0 2006.258.01:22:30.03#ibcon#about to read 3, iclass 37, count 0 2006.258.01:22:30.05#ibcon#read 3, iclass 37, count 0 2006.258.01:22:30.05#ibcon#about to read 4, iclass 37, count 0 2006.258.01:22:30.05#ibcon#read 4, iclass 37, count 0 2006.258.01:22:30.05#ibcon#about to read 5, iclass 37, count 0 2006.258.01:22:30.05#ibcon#read 5, iclass 37, count 0 2006.258.01:22:30.05#ibcon#about to read 6, iclass 37, count 0 2006.258.01:22:30.05#ibcon#read 6, iclass 37, count 0 2006.258.01:22:30.05#ibcon#end of sib2, iclass 37, count 0 2006.258.01:22:30.05#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:22:30.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:22:30.05#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.01:22:30.05#ibcon#*before write, iclass 37, count 0 2006.258.01:22:30.05#ibcon#enter sib2, iclass 37, count 0 2006.258.01:22:30.05#ibcon#flushed, iclass 37, count 0 2006.258.01:22:30.05#ibcon#about to write, iclass 37, count 0 2006.258.01:22:30.05#ibcon#wrote, iclass 37, count 0 2006.258.01:22:30.05#ibcon#about to read 3, iclass 37, count 0 2006.258.01:22:30.09#ibcon#read 3, iclass 37, count 0 2006.258.01:22:30.09#ibcon#about to read 4, iclass 37, count 0 2006.258.01:22:30.09#ibcon#read 4, iclass 37, count 0 2006.258.01:22:30.09#ibcon#about to read 5, iclass 37, count 0 2006.258.01:22:30.09#ibcon#read 5, iclass 37, count 0 2006.258.01:22:30.09#ibcon#about to read 6, iclass 37, count 0 2006.258.01:22:30.09#ibcon#read 6, iclass 37, count 0 2006.258.01:22:30.09#ibcon#end of sib2, iclass 37, count 0 2006.258.01:22:30.09#ibcon#*after write, iclass 37, count 0 2006.258.01:22:30.09#ibcon#*before return 0, iclass 37, count 0 2006.258.01:22:30.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:30.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:22:30.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:22:30.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:22:30.09$vck44/vb=4,5 2006.258.01:22:30.09#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.258.01:22:30.09#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.258.01:22:30.09#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:30.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:30.15#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:30.15#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:30.15#ibcon#enter wrdev, iclass 39, count 2 2006.258.01:22:30.15#ibcon#first serial, iclass 39, count 2 2006.258.01:22:30.15#ibcon#enter sib2, iclass 39, count 2 2006.258.01:22:30.15#ibcon#flushed, iclass 39, count 2 2006.258.01:22:30.15#ibcon#about to write, iclass 39, count 2 2006.258.01:22:30.15#ibcon#wrote, iclass 39, count 2 2006.258.01:22:30.15#ibcon#about to read 3, iclass 39, count 2 2006.258.01:22:30.17#ibcon#read 3, iclass 39, count 2 2006.258.01:22:30.17#ibcon#about to read 4, iclass 39, count 2 2006.258.01:22:30.17#ibcon#read 4, iclass 39, count 2 2006.258.01:22:30.17#ibcon#about to read 5, iclass 39, count 2 2006.258.01:22:30.17#ibcon#read 5, iclass 39, count 2 2006.258.01:22:30.17#ibcon#about to read 6, iclass 39, count 2 2006.258.01:22:30.17#ibcon#read 6, iclass 39, count 2 2006.258.01:22:30.17#ibcon#end of sib2, iclass 39, count 2 2006.258.01:22:30.17#ibcon#*mode == 0, iclass 39, count 2 2006.258.01:22:30.17#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.258.01:22:30.17#ibcon#[27=AT04-05\r\n] 2006.258.01:22:30.17#ibcon#*before write, iclass 39, count 2 2006.258.01:22:30.17#ibcon#enter sib2, iclass 39, count 2 2006.258.01:22:30.17#ibcon#flushed, iclass 39, count 2 2006.258.01:22:30.17#ibcon#about to write, iclass 39, count 2 2006.258.01:22:30.17#ibcon#wrote, iclass 39, count 2 2006.258.01:22:30.17#ibcon#about to read 3, iclass 39, count 2 2006.258.01:22:30.20#ibcon#read 3, iclass 39, count 2 2006.258.01:22:30.20#ibcon#about to read 4, iclass 39, count 2 2006.258.01:22:30.20#ibcon#read 4, iclass 39, count 2 2006.258.01:22:30.20#ibcon#about to read 5, iclass 39, count 2 2006.258.01:22:30.20#ibcon#read 5, iclass 39, count 2 2006.258.01:22:30.20#ibcon#about to read 6, iclass 39, count 2 2006.258.01:22:30.20#ibcon#read 6, iclass 39, count 2 2006.258.01:22:30.20#ibcon#end of sib2, iclass 39, count 2 2006.258.01:22:30.20#ibcon#*after write, iclass 39, count 2 2006.258.01:22:30.20#ibcon#*before return 0, iclass 39, count 2 2006.258.01:22:30.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:30.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:22:30.20#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.258.01:22:30.20#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:30.20#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:30.32#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:30.32#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:30.32#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:22:30.32#ibcon#first serial, iclass 39, count 0 2006.258.01:22:30.32#ibcon#enter sib2, iclass 39, count 0 2006.258.01:22:30.32#ibcon#flushed, iclass 39, count 0 2006.258.01:22:30.32#ibcon#about to write, iclass 39, count 0 2006.258.01:22:30.32#ibcon#wrote, iclass 39, count 0 2006.258.01:22:30.32#ibcon#about to read 3, iclass 39, count 0 2006.258.01:22:30.34#ibcon#read 3, iclass 39, count 0 2006.258.01:22:30.34#ibcon#about to read 4, iclass 39, count 0 2006.258.01:22:30.34#ibcon#read 4, iclass 39, count 0 2006.258.01:22:30.34#ibcon#about to read 5, iclass 39, count 0 2006.258.01:22:30.34#ibcon#read 5, iclass 39, count 0 2006.258.01:22:30.34#ibcon#about to read 6, iclass 39, count 0 2006.258.01:22:30.34#ibcon#read 6, iclass 39, count 0 2006.258.01:22:30.34#ibcon#end of sib2, iclass 39, count 0 2006.258.01:22:30.34#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:22:30.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:22:30.34#ibcon#[27=USB\r\n] 2006.258.01:22:30.34#ibcon#*before write, iclass 39, count 0 2006.258.01:22:30.34#ibcon#enter sib2, iclass 39, count 0 2006.258.01:22:30.34#ibcon#flushed, iclass 39, count 0 2006.258.01:22:30.34#ibcon#about to write, iclass 39, count 0 2006.258.01:22:30.34#ibcon#wrote, iclass 39, count 0 2006.258.01:22:30.34#ibcon#about to read 3, iclass 39, count 0 2006.258.01:22:30.37#ibcon#read 3, iclass 39, count 0 2006.258.01:22:30.37#ibcon#about to read 4, iclass 39, count 0 2006.258.01:22:30.37#ibcon#read 4, iclass 39, count 0 2006.258.01:22:30.37#ibcon#about to read 5, iclass 39, count 0 2006.258.01:22:30.37#ibcon#read 5, iclass 39, count 0 2006.258.01:22:30.37#ibcon#about to read 6, iclass 39, count 0 2006.258.01:22:30.37#ibcon#read 6, iclass 39, count 0 2006.258.01:22:30.37#ibcon#end of sib2, iclass 39, count 0 2006.258.01:22:30.37#ibcon#*after write, iclass 39, count 0 2006.258.01:22:30.37#ibcon#*before return 0, iclass 39, count 0 2006.258.01:22:30.37#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:30.37#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:22:30.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:22:30.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:22:30.37$vck44/vblo=5,709.99 2006.258.01:22:30.37#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.01:22:30.37#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.01:22:30.37#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:30.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:30.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:30.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:30.37#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:22:30.37#ibcon#first serial, iclass 3, count 0 2006.258.01:22:30.37#ibcon#enter sib2, iclass 3, count 0 2006.258.01:22:30.37#ibcon#flushed, iclass 3, count 0 2006.258.01:22:30.37#ibcon#about to write, iclass 3, count 0 2006.258.01:22:30.37#ibcon#wrote, iclass 3, count 0 2006.258.01:22:30.37#ibcon#about to read 3, iclass 3, count 0 2006.258.01:22:30.39#ibcon#read 3, iclass 3, count 0 2006.258.01:22:30.39#ibcon#about to read 4, iclass 3, count 0 2006.258.01:22:30.39#ibcon#read 4, iclass 3, count 0 2006.258.01:22:30.39#ibcon#about to read 5, iclass 3, count 0 2006.258.01:22:30.39#ibcon#read 5, iclass 3, count 0 2006.258.01:22:30.39#ibcon#about to read 6, iclass 3, count 0 2006.258.01:22:30.39#ibcon#read 6, iclass 3, count 0 2006.258.01:22:30.39#ibcon#end of sib2, iclass 3, count 0 2006.258.01:22:30.39#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:22:30.39#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:22:30.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.01:22:30.39#ibcon#*before write, iclass 3, count 0 2006.258.01:22:30.39#ibcon#enter sib2, iclass 3, count 0 2006.258.01:22:30.39#ibcon#flushed, iclass 3, count 0 2006.258.01:22:30.39#ibcon#about to write, iclass 3, count 0 2006.258.01:22:30.39#ibcon#wrote, iclass 3, count 0 2006.258.01:22:30.39#ibcon#about to read 3, iclass 3, count 0 2006.258.01:22:30.43#ibcon#read 3, iclass 3, count 0 2006.258.01:22:30.43#ibcon#about to read 4, iclass 3, count 0 2006.258.01:22:30.43#ibcon#read 4, iclass 3, count 0 2006.258.01:22:30.43#ibcon#about to read 5, iclass 3, count 0 2006.258.01:22:30.43#ibcon#read 5, iclass 3, count 0 2006.258.01:22:30.43#ibcon#about to read 6, iclass 3, count 0 2006.258.01:22:30.43#ibcon#read 6, iclass 3, count 0 2006.258.01:22:30.43#ibcon#end of sib2, iclass 3, count 0 2006.258.01:22:30.43#ibcon#*after write, iclass 3, count 0 2006.258.01:22:30.43#ibcon#*before return 0, iclass 3, count 0 2006.258.01:22:30.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:30.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:22:30.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:22:30.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:22:30.43$vck44/vb=5,4 2006.258.01:22:30.43#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.258.01:22:30.43#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.258.01:22:30.43#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:30.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:30.49#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:30.49#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:30.49#ibcon#enter wrdev, iclass 5, count 2 2006.258.01:22:30.49#ibcon#first serial, iclass 5, count 2 2006.258.01:22:30.49#ibcon#enter sib2, iclass 5, count 2 2006.258.01:22:30.49#ibcon#flushed, iclass 5, count 2 2006.258.01:22:30.49#ibcon#about to write, iclass 5, count 2 2006.258.01:22:30.49#ibcon#wrote, iclass 5, count 2 2006.258.01:22:30.49#ibcon#about to read 3, iclass 5, count 2 2006.258.01:22:30.51#ibcon#read 3, iclass 5, count 2 2006.258.01:22:30.51#ibcon#about to read 4, iclass 5, count 2 2006.258.01:22:30.51#ibcon#read 4, iclass 5, count 2 2006.258.01:22:30.51#ibcon#about to read 5, iclass 5, count 2 2006.258.01:22:30.51#ibcon#read 5, iclass 5, count 2 2006.258.01:22:30.51#ibcon#about to read 6, iclass 5, count 2 2006.258.01:22:30.51#ibcon#read 6, iclass 5, count 2 2006.258.01:22:30.51#ibcon#end of sib2, iclass 5, count 2 2006.258.01:22:30.51#ibcon#*mode == 0, iclass 5, count 2 2006.258.01:22:30.51#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.258.01:22:30.51#ibcon#[27=AT05-04\r\n] 2006.258.01:22:30.51#ibcon#*before write, iclass 5, count 2 2006.258.01:22:30.51#ibcon#enter sib2, iclass 5, count 2 2006.258.01:22:30.51#ibcon#flushed, iclass 5, count 2 2006.258.01:22:30.51#ibcon#about to write, iclass 5, count 2 2006.258.01:22:30.51#ibcon#wrote, iclass 5, count 2 2006.258.01:22:30.51#ibcon#about to read 3, iclass 5, count 2 2006.258.01:22:30.54#ibcon#read 3, iclass 5, count 2 2006.258.01:22:30.54#ibcon#about to read 4, iclass 5, count 2 2006.258.01:22:30.54#ibcon#read 4, iclass 5, count 2 2006.258.01:22:30.54#ibcon#about to read 5, iclass 5, count 2 2006.258.01:22:30.54#ibcon#read 5, iclass 5, count 2 2006.258.01:22:30.54#ibcon#about to read 6, iclass 5, count 2 2006.258.01:22:30.54#ibcon#read 6, iclass 5, count 2 2006.258.01:22:30.54#ibcon#end of sib2, iclass 5, count 2 2006.258.01:22:30.54#ibcon#*after write, iclass 5, count 2 2006.258.01:22:30.54#ibcon#*before return 0, iclass 5, count 2 2006.258.01:22:30.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:30.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:22:30.54#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.258.01:22:30.54#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:30.54#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:30.66#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:30.66#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:30.66#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:22:30.66#ibcon#first serial, iclass 5, count 0 2006.258.01:22:30.66#ibcon#enter sib2, iclass 5, count 0 2006.258.01:22:30.66#ibcon#flushed, iclass 5, count 0 2006.258.01:22:30.66#ibcon#about to write, iclass 5, count 0 2006.258.01:22:30.66#ibcon#wrote, iclass 5, count 0 2006.258.01:22:30.66#ibcon#about to read 3, iclass 5, count 0 2006.258.01:22:30.68#ibcon#read 3, iclass 5, count 0 2006.258.01:22:30.68#ibcon#about to read 4, iclass 5, count 0 2006.258.01:22:30.68#ibcon#read 4, iclass 5, count 0 2006.258.01:22:30.68#ibcon#about to read 5, iclass 5, count 0 2006.258.01:22:30.68#ibcon#read 5, iclass 5, count 0 2006.258.01:22:30.68#ibcon#about to read 6, iclass 5, count 0 2006.258.01:22:30.68#ibcon#read 6, iclass 5, count 0 2006.258.01:22:30.68#ibcon#end of sib2, iclass 5, count 0 2006.258.01:22:30.68#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:22:30.68#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:22:30.68#ibcon#[27=USB\r\n] 2006.258.01:22:30.68#ibcon#*before write, iclass 5, count 0 2006.258.01:22:30.68#ibcon#enter sib2, iclass 5, count 0 2006.258.01:22:30.68#ibcon#flushed, iclass 5, count 0 2006.258.01:22:30.68#ibcon#about to write, iclass 5, count 0 2006.258.01:22:30.68#ibcon#wrote, iclass 5, count 0 2006.258.01:22:30.68#ibcon#about to read 3, iclass 5, count 0 2006.258.01:22:30.71#ibcon#read 3, iclass 5, count 0 2006.258.01:22:30.71#ibcon#about to read 4, iclass 5, count 0 2006.258.01:22:30.71#ibcon#read 4, iclass 5, count 0 2006.258.01:22:30.71#ibcon#about to read 5, iclass 5, count 0 2006.258.01:22:30.71#ibcon#read 5, iclass 5, count 0 2006.258.01:22:30.71#ibcon#about to read 6, iclass 5, count 0 2006.258.01:22:30.71#ibcon#read 6, iclass 5, count 0 2006.258.01:22:30.71#ibcon#end of sib2, iclass 5, count 0 2006.258.01:22:30.71#ibcon#*after write, iclass 5, count 0 2006.258.01:22:30.71#ibcon#*before return 0, iclass 5, count 0 2006.258.01:22:30.71#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:30.71#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:22:30.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:22:30.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:22:30.71$vck44/vblo=6,719.99 2006.258.01:22:30.71#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.01:22:30.71#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.01:22:30.71#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:30.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:30.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:30.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:30.71#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:22:30.71#ibcon#first serial, iclass 7, count 0 2006.258.01:22:30.71#ibcon#enter sib2, iclass 7, count 0 2006.258.01:22:30.71#ibcon#flushed, iclass 7, count 0 2006.258.01:22:30.71#ibcon#about to write, iclass 7, count 0 2006.258.01:22:30.71#ibcon#wrote, iclass 7, count 0 2006.258.01:22:30.71#ibcon#about to read 3, iclass 7, count 0 2006.258.01:22:30.73#ibcon#read 3, iclass 7, count 0 2006.258.01:22:30.73#ibcon#about to read 4, iclass 7, count 0 2006.258.01:22:30.73#ibcon#read 4, iclass 7, count 0 2006.258.01:22:30.73#ibcon#about to read 5, iclass 7, count 0 2006.258.01:22:30.73#ibcon#read 5, iclass 7, count 0 2006.258.01:22:30.73#ibcon#about to read 6, iclass 7, count 0 2006.258.01:22:30.73#ibcon#read 6, iclass 7, count 0 2006.258.01:22:30.73#ibcon#end of sib2, iclass 7, count 0 2006.258.01:22:30.73#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:22:30.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:22:30.73#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.01:22:30.73#ibcon#*before write, iclass 7, count 0 2006.258.01:22:30.73#ibcon#enter sib2, iclass 7, count 0 2006.258.01:22:30.73#ibcon#flushed, iclass 7, count 0 2006.258.01:22:30.73#ibcon#about to write, iclass 7, count 0 2006.258.01:22:30.73#ibcon#wrote, iclass 7, count 0 2006.258.01:22:30.73#ibcon#about to read 3, iclass 7, count 0 2006.258.01:22:30.77#ibcon#read 3, iclass 7, count 0 2006.258.01:22:30.77#ibcon#about to read 4, iclass 7, count 0 2006.258.01:22:30.77#ibcon#read 4, iclass 7, count 0 2006.258.01:22:30.77#ibcon#about to read 5, iclass 7, count 0 2006.258.01:22:30.77#ibcon#read 5, iclass 7, count 0 2006.258.01:22:30.77#ibcon#about to read 6, iclass 7, count 0 2006.258.01:22:30.77#ibcon#read 6, iclass 7, count 0 2006.258.01:22:30.77#ibcon#end of sib2, iclass 7, count 0 2006.258.01:22:30.77#ibcon#*after write, iclass 7, count 0 2006.258.01:22:30.77#ibcon#*before return 0, iclass 7, count 0 2006.258.01:22:30.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:30.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:22:30.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:22:30.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:22:30.77$vck44/vb=6,4 2006.258.01:22:30.77#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.01:22:30.77#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.01:22:30.77#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:30.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:30.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:30.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:30.83#ibcon#enter wrdev, iclass 11, count 2 2006.258.01:22:30.83#ibcon#first serial, iclass 11, count 2 2006.258.01:22:30.83#ibcon#enter sib2, iclass 11, count 2 2006.258.01:22:30.83#ibcon#flushed, iclass 11, count 2 2006.258.01:22:30.83#ibcon#about to write, iclass 11, count 2 2006.258.01:22:30.83#ibcon#wrote, iclass 11, count 2 2006.258.01:22:30.83#ibcon#about to read 3, iclass 11, count 2 2006.258.01:22:30.85#ibcon#read 3, iclass 11, count 2 2006.258.01:22:30.85#ibcon#about to read 4, iclass 11, count 2 2006.258.01:22:30.85#ibcon#read 4, iclass 11, count 2 2006.258.01:22:30.85#ibcon#about to read 5, iclass 11, count 2 2006.258.01:22:30.85#ibcon#read 5, iclass 11, count 2 2006.258.01:22:30.85#ibcon#about to read 6, iclass 11, count 2 2006.258.01:22:30.85#ibcon#read 6, iclass 11, count 2 2006.258.01:22:30.85#ibcon#end of sib2, iclass 11, count 2 2006.258.01:22:30.85#ibcon#*mode == 0, iclass 11, count 2 2006.258.01:22:30.85#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.01:22:30.85#ibcon#[27=AT06-04\r\n] 2006.258.01:22:30.85#ibcon#*before write, iclass 11, count 2 2006.258.01:22:30.85#ibcon#enter sib2, iclass 11, count 2 2006.258.01:22:30.85#ibcon#flushed, iclass 11, count 2 2006.258.01:22:30.85#ibcon#about to write, iclass 11, count 2 2006.258.01:22:30.85#ibcon#wrote, iclass 11, count 2 2006.258.01:22:30.85#ibcon#about to read 3, iclass 11, count 2 2006.258.01:22:30.88#ibcon#read 3, iclass 11, count 2 2006.258.01:22:30.88#ibcon#about to read 4, iclass 11, count 2 2006.258.01:22:30.88#ibcon#read 4, iclass 11, count 2 2006.258.01:22:30.88#ibcon#about to read 5, iclass 11, count 2 2006.258.01:22:30.88#ibcon#read 5, iclass 11, count 2 2006.258.01:22:30.88#ibcon#about to read 6, iclass 11, count 2 2006.258.01:22:30.88#ibcon#read 6, iclass 11, count 2 2006.258.01:22:30.88#ibcon#end of sib2, iclass 11, count 2 2006.258.01:22:30.88#ibcon#*after write, iclass 11, count 2 2006.258.01:22:30.88#ibcon#*before return 0, iclass 11, count 2 2006.258.01:22:30.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:30.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:22:30.88#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.01:22:30.88#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:30.88#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:31.00#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:31.00#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:31.00#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:22:31.00#ibcon#first serial, iclass 11, count 0 2006.258.01:22:31.00#ibcon#enter sib2, iclass 11, count 0 2006.258.01:22:31.00#ibcon#flushed, iclass 11, count 0 2006.258.01:22:31.00#ibcon#about to write, iclass 11, count 0 2006.258.01:22:31.00#ibcon#wrote, iclass 11, count 0 2006.258.01:22:31.00#ibcon#about to read 3, iclass 11, count 0 2006.258.01:22:31.02#ibcon#read 3, iclass 11, count 0 2006.258.01:22:31.02#ibcon#about to read 4, iclass 11, count 0 2006.258.01:22:31.02#ibcon#read 4, iclass 11, count 0 2006.258.01:22:31.02#ibcon#about to read 5, iclass 11, count 0 2006.258.01:22:31.02#ibcon#read 5, iclass 11, count 0 2006.258.01:22:31.02#ibcon#about to read 6, iclass 11, count 0 2006.258.01:22:31.02#ibcon#read 6, iclass 11, count 0 2006.258.01:22:31.02#ibcon#end of sib2, iclass 11, count 0 2006.258.01:22:31.02#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:22:31.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:22:31.02#ibcon#[27=USB\r\n] 2006.258.01:22:31.02#ibcon#*before write, iclass 11, count 0 2006.258.01:22:31.02#ibcon#enter sib2, iclass 11, count 0 2006.258.01:22:31.02#ibcon#flushed, iclass 11, count 0 2006.258.01:22:31.02#ibcon#about to write, iclass 11, count 0 2006.258.01:22:31.02#ibcon#wrote, iclass 11, count 0 2006.258.01:22:31.02#ibcon#about to read 3, iclass 11, count 0 2006.258.01:22:31.05#ibcon#read 3, iclass 11, count 0 2006.258.01:22:31.05#ibcon#about to read 4, iclass 11, count 0 2006.258.01:22:31.05#ibcon#read 4, iclass 11, count 0 2006.258.01:22:31.05#ibcon#about to read 5, iclass 11, count 0 2006.258.01:22:31.05#ibcon#read 5, iclass 11, count 0 2006.258.01:22:31.05#ibcon#about to read 6, iclass 11, count 0 2006.258.01:22:31.05#ibcon#read 6, iclass 11, count 0 2006.258.01:22:31.05#ibcon#end of sib2, iclass 11, count 0 2006.258.01:22:31.05#ibcon#*after write, iclass 11, count 0 2006.258.01:22:31.05#ibcon#*before return 0, iclass 11, count 0 2006.258.01:22:31.05#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:31.05#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:22:31.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:22:31.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:22:31.05$vck44/vblo=7,734.99 2006.258.01:22:31.05#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.258.01:22:31.05#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.258.01:22:31.05#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:31.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:31.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:31.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:31.05#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:22:31.05#ibcon#first serial, iclass 13, count 0 2006.258.01:22:31.05#ibcon#enter sib2, iclass 13, count 0 2006.258.01:22:31.05#ibcon#flushed, iclass 13, count 0 2006.258.01:22:31.05#ibcon#about to write, iclass 13, count 0 2006.258.01:22:31.05#ibcon#wrote, iclass 13, count 0 2006.258.01:22:31.05#ibcon#about to read 3, iclass 13, count 0 2006.258.01:22:31.07#ibcon#read 3, iclass 13, count 0 2006.258.01:22:31.07#ibcon#about to read 4, iclass 13, count 0 2006.258.01:22:31.07#ibcon#read 4, iclass 13, count 0 2006.258.01:22:31.07#ibcon#about to read 5, iclass 13, count 0 2006.258.01:22:31.07#ibcon#read 5, iclass 13, count 0 2006.258.01:22:31.07#ibcon#about to read 6, iclass 13, count 0 2006.258.01:22:31.07#ibcon#read 6, iclass 13, count 0 2006.258.01:22:31.07#ibcon#end of sib2, iclass 13, count 0 2006.258.01:22:31.07#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:22:31.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:22:31.07#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.01:22:31.07#ibcon#*before write, iclass 13, count 0 2006.258.01:22:31.07#ibcon#enter sib2, iclass 13, count 0 2006.258.01:22:31.07#ibcon#flushed, iclass 13, count 0 2006.258.01:22:31.07#ibcon#about to write, iclass 13, count 0 2006.258.01:22:31.07#ibcon#wrote, iclass 13, count 0 2006.258.01:22:31.07#ibcon#about to read 3, iclass 13, count 0 2006.258.01:22:31.11#ibcon#read 3, iclass 13, count 0 2006.258.01:22:31.11#ibcon#about to read 4, iclass 13, count 0 2006.258.01:22:31.11#ibcon#read 4, iclass 13, count 0 2006.258.01:22:31.11#ibcon#about to read 5, iclass 13, count 0 2006.258.01:22:31.11#ibcon#read 5, iclass 13, count 0 2006.258.01:22:31.11#ibcon#about to read 6, iclass 13, count 0 2006.258.01:22:31.11#ibcon#read 6, iclass 13, count 0 2006.258.01:22:31.11#ibcon#end of sib2, iclass 13, count 0 2006.258.01:22:31.11#ibcon#*after write, iclass 13, count 0 2006.258.01:22:31.11#ibcon#*before return 0, iclass 13, count 0 2006.258.01:22:31.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:31.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:22:31.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:22:31.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:22:31.11$vck44/vb=7,4 2006.258.01:22:31.11#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.258.01:22:31.11#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.258.01:22:31.11#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:31.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:31.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:31.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:31.17#ibcon#enter wrdev, iclass 15, count 2 2006.258.01:22:31.17#ibcon#first serial, iclass 15, count 2 2006.258.01:22:31.17#ibcon#enter sib2, iclass 15, count 2 2006.258.01:22:31.17#ibcon#flushed, iclass 15, count 2 2006.258.01:22:31.17#ibcon#about to write, iclass 15, count 2 2006.258.01:22:31.17#ibcon#wrote, iclass 15, count 2 2006.258.01:22:31.17#ibcon#about to read 3, iclass 15, count 2 2006.258.01:22:31.19#ibcon#read 3, iclass 15, count 2 2006.258.01:22:31.19#ibcon#about to read 4, iclass 15, count 2 2006.258.01:22:31.19#ibcon#read 4, iclass 15, count 2 2006.258.01:22:31.19#ibcon#about to read 5, iclass 15, count 2 2006.258.01:22:31.19#ibcon#read 5, iclass 15, count 2 2006.258.01:22:31.19#ibcon#about to read 6, iclass 15, count 2 2006.258.01:22:31.19#ibcon#read 6, iclass 15, count 2 2006.258.01:22:31.19#ibcon#end of sib2, iclass 15, count 2 2006.258.01:22:31.19#ibcon#*mode == 0, iclass 15, count 2 2006.258.01:22:31.19#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.258.01:22:31.19#ibcon#[27=AT07-04\r\n] 2006.258.01:22:31.19#ibcon#*before write, iclass 15, count 2 2006.258.01:22:31.19#ibcon#enter sib2, iclass 15, count 2 2006.258.01:22:31.19#ibcon#flushed, iclass 15, count 2 2006.258.01:22:31.19#ibcon#about to write, iclass 15, count 2 2006.258.01:22:31.19#ibcon#wrote, iclass 15, count 2 2006.258.01:22:31.19#ibcon#about to read 3, iclass 15, count 2 2006.258.01:22:31.22#ibcon#read 3, iclass 15, count 2 2006.258.01:22:31.22#ibcon#about to read 4, iclass 15, count 2 2006.258.01:22:31.22#ibcon#read 4, iclass 15, count 2 2006.258.01:22:31.22#ibcon#about to read 5, iclass 15, count 2 2006.258.01:22:31.22#ibcon#read 5, iclass 15, count 2 2006.258.01:22:31.22#ibcon#about to read 6, iclass 15, count 2 2006.258.01:22:31.22#ibcon#read 6, iclass 15, count 2 2006.258.01:22:31.22#ibcon#end of sib2, iclass 15, count 2 2006.258.01:22:31.22#ibcon#*after write, iclass 15, count 2 2006.258.01:22:31.22#ibcon#*before return 0, iclass 15, count 2 2006.258.01:22:31.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:31.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:22:31.22#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.258.01:22:31.22#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:31.22#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:31.34#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:31.34#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:31.34#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:22:31.34#ibcon#first serial, iclass 15, count 0 2006.258.01:22:31.34#ibcon#enter sib2, iclass 15, count 0 2006.258.01:22:31.34#ibcon#flushed, iclass 15, count 0 2006.258.01:22:31.34#ibcon#about to write, iclass 15, count 0 2006.258.01:22:31.34#ibcon#wrote, iclass 15, count 0 2006.258.01:22:31.34#ibcon#about to read 3, iclass 15, count 0 2006.258.01:22:31.36#ibcon#read 3, iclass 15, count 0 2006.258.01:22:31.36#ibcon#about to read 4, iclass 15, count 0 2006.258.01:22:31.36#ibcon#read 4, iclass 15, count 0 2006.258.01:22:31.36#ibcon#about to read 5, iclass 15, count 0 2006.258.01:22:31.36#ibcon#read 5, iclass 15, count 0 2006.258.01:22:31.36#ibcon#about to read 6, iclass 15, count 0 2006.258.01:22:31.36#ibcon#read 6, iclass 15, count 0 2006.258.01:22:31.36#ibcon#end of sib2, iclass 15, count 0 2006.258.01:22:31.36#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:22:31.36#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:22:31.36#ibcon#[27=USB\r\n] 2006.258.01:22:31.36#ibcon#*before write, iclass 15, count 0 2006.258.01:22:31.36#ibcon#enter sib2, iclass 15, count 0 2006.258.01:22:31.36#ibcon#flushed, iclass 15, count 0 2006.258.01:22:31.36#ibcon#about to write, iclass 15, count 0 2006.258.01:22:31.36#ibcon#wrote, iclass 15, count 0 2006.258.01:22:31.36#ibcon#about to read 3, iclass 15, count 0 2006.258.01:22:31.39#ibcon#read 3, iclass 15, count 0 2006.258.01:22:31.39#ibcon#about to read 4, iclass 15, count 0 2006.258.01:22:31.39#ibcon#read 4, iclass 15, count 0 2006.258.01:22:31.39#ibcon#about to read 5, iclass 15, count 0 2006.258.01:22:31.39#ibcon#read 5, iclass 15, count 0 2006.258.01:22:31.39#ibcon#about to read 6, iclass 15, count 0 2006.258.01:22:31.39#ibcon#read 6, iclass 15, count 0 2006.258.01:22:31.39#ibcon#end of sib2, iclass 15, count 0 2006.258.01:22:31.39#ibcon#*after write, iclass 15, count 0 2006.258.01:22:31.39#ibcon#*before return 0, iclass 15, count 0 2006.258.01:22:31.39#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:31.39#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:22:31.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:22:31.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:22:31.39$vck44/vblo=8,744.99 2006.258.01:22:31.39#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.258.01:22:31.39#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.258.01:22:31.39#ibcon#ireg 17 cls_cnt 0 2006.258.01:22:31.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:31.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:31.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:31.39#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:22:31.39#ibcon#first serial, iclass 17, count 0 2006.258.01:22:31.39#ibcon#enter sib2, iclass 17, count 0 2006.258.01:22:31.39#ibcon#flushed, iclass 17, count 0 2006.258.01:22:31.39#ibcon#about to write, iclass 17, count 0 2006.258.01:22:31.39#ibcon#wrote, iclass 17, count 0 2006.258.01:22:31.39#ibcon#about to read 3, iclass 17, count 0 2006.258.01:22:31.41#ibcon#read 3, iclass 17, count 0 2006.258.01:22:31.41#ibcon#about to read 4, iclass 17, count 0 2006.258.01:22:31.41#ibcon#read 4, iclass 17, count 0 2006.258.01:22:31.41#ibcon#about to read 5, iclass 17, count 0 2006.258.01:22:31.41#ibcon#read 5, iclass 17, count 0 2006.258.01:22:31.41#ibcon#about to read 6, iclass 17, count 0 2006.258.01:22:31.41#ibcon#read 6, iclass 17, count 0 2006.258.01:22:31.41#ibcon#end of sib2, iclass 17, count 0 2006.258.01:22:31.41#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:22:31.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:22:31.41#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.01:22:31.41#ibcon#*before write, iclass 17, count 0 2006.258.01:22:31.41#ibcon#enter sib2, iclass 17, count 0 2006.258.01:22:31.41#ibcon#flushed, iclass 17, count 0 2006.258.01:22:31.41#ibcon#about to write, iclass 17, count 0 2006.258.01:22:31.41#ibcon#wrote, iclass 17, count 0 2006.258.01:22:31.41#ibcon#about to read 3, iclass 17, count 0 2006.258.01:22:31.45#ibcon#read 3, iclass 17, count 0 2006.258.01:22:31.45#ibcon#about to read 4, iclass 17, count 0 2006.258.01:22:31.45#ibcon#read 4, iclass 17, count 0 2006.258.01:22:31.45#ibcon#about to read 5, iclass 17, count 0 2006.258.01:22:31.45#ibcon#read 5, iclass 17, count 0 2006.258.01:22:31.45#ibcon#about to read 6, iclass 17, count 0 2006.258.01:22:31.45#ibcon#read 6, iclass 17, count 0 2006.258.01:22:31.45#ibcon#end of sib2, iclass 17, count 0 2006.258.01:22:31.45#ibcon#*after write, iclass 17, count 0 2006.258.01:22:31.45#ibcon#*before return 0, iclass 17, count 0 2006.258.01:22:31.45#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:31.45#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:22:31.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:22:31.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:22:31.45$vck44/vb=8,4 2006.258.01:22:31.45#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.258.01:22:31.45#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.258.01:22:31.45#ibcon#ireg 11 cls_cnt 2 2006.258.01:22:31.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:31.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:31.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:31.51#ibcon#enter wrdev, iclass 19, count 2 2006.258.01:22:31.51#ibcon#first serial, iclass 19, count 2 2006.258.01:22:31.51#ibcon#enter sib2, iclass 19, count 2 2006.258.01:22:31.51#ibcon#flushed, iclass 19, count 2 2006.258.01:22:31.51#ibcon#about to write, iclass 19, count 2 2006.258.01:22:31.51#ibcon#wrote, iclass 19, count 2 2006.258.01:22:31.51#ibcon#about to read 3, iclass 19, count 2 2006.258.01:22:31.53#ibcon#read 3, iclass 19, count 2 2006.258.01:22:31.53#ibcon#about to read 4, iclass 19, count 2 2006.258.01:22:31.53#ibcon#read 4, iclass 19, count 2 2006.258.01:22:31.53#ibcon#about to read 5, iclass 19, count 2 2006.258.01:22:31.53#ibcon#read 5, iclass 19, count 2 2006.258.01:22:31.53#ibcon#about to read 6, iclass 19, count 2 2006.258.01:22:31.53#ibcon#read 6, iclass 19, count 2 2006.258.01:22:31.53#ibcon#end of sib2, iclass 19, count 2 2006.258.01:22:31.53#ibcon#*mode == 0, iclass 19, count 2 2006.258.01:22:31.53#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.258.01:22:31.53#ibcon#[27=AT08-04\r\n] 2006.258.01:22:31.53#ibcon#*before write, iclass 19, count 2 2006.258.01:22:31.53#ibcon#enter sib2, iclass 19, count 2 2006.258.01:22:31.53#ibcon#flushed, iclass 19, count 2 2006.258.01:22:31.53#ibcon#about to write, iclass 19, count 2 2006.258.01:22:31.53#ibcon#wrote, iclass 19, count 2 2006.258.01:22:31.53#ibcon#about to read 3, iclass 19, count 2 2006.258.01:22:31.56#ibcon#read 3, iclass 19, count 2 2006.258.01:22:31.56#ibcon#about to read 4, iclass 19, count 2 2006.258.01:22:31.56#ibcon#read 4, iclass 19, count 2 2006.258.01:22:31.56#ibcon#about to read 5, iclass 19, count 2 2006.258.01:22:31.56#ibcon#read 5, iclass 19, count 2 2006.258.01:22:31.56#ibcon#about to read 6, iclass 19, count 2 2006.258.01:22:31.56#ibcon#read 6, iclass 19, count 2 2006.258.01:22:31.56#ibcon#end of sib2, iclass 19, count 2 2006.258.01:22:31.56#ibcon#*after write, iclass 19, count 2 2006.258.01:22:31.56#ibcon#*before return 0, iclass 19, count 2 2006.258.01:22:31.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:31.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:22:31.56#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.258.01:22:31.56#ibcon#ireg 7 cls_cnt 0 2006.258.01:22:31.56#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:31.68#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:31.68#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:31.68#ibcon#enter wrdev, iclass 19, count 0 2006.258.01:22:31.68#ibcon#first serial, iclass 19, count 0 2006.258.01:22:31.68#ibcon#enter sib2, iclass 19, count 0 2006.258.01:22:31.68#ibcon#flushed, iclass 19, count 0 2006.258.01:22:31.68#ibcon#about to write, iclass 19, count 0 2006.258.01:22:31.68#ibcon#wrote, iclass 19, count 0 2006.258.01:22:31.68#ibcon#about to read 3, iclass 19, count 0 2006.258.01:22:31.70#ibcon#read 3, iclass 19, count 0 2006.258.01:22:31.70#ibcon#about to read 4, iclass 19, count 0 2006.258.01:22:31.70#ibcon#read 4, iclass 19, count 0 2006.258.01:22:31.70#ibcon#about to read 5, iclass 19, count 0 2006.258.01:22:31.70#ibcon#read 5, iclass 19, count 0 2006.258.01:22:31.70#ibcon#about to read 6, iclass 19, count 0 2006.258.01:22:31.70#ibcon#read 6, iclass 19, count 0 2006.258.01:22:31.70#ibcon#end of sib2, iclass 19, count 0 2006.258.01:22:31.70#ibcon#*mode == 0, iclass 19, count 0 2006.258.01:22:31.70#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.01:22:31.70#ibcon#[27=USB\r\n] 2006.258.01:22:31.70#ibcon#*before write, iclass 19, count 0 2006.258.01:22:31.70#ibcon#enter sib2, iclass 19, count 0 2006.258.01:22:31.70#ibcon#flushed, iclass 19, count 0 2006.258.01:22:31.70#ibcon#about to write, iclass 19, count 0 2006.258.01:22:31.70#ibcon#wrote, iclass 19, count 0 2006.258.01:22:31.70#ibcon#about to read 3, iclass 19, count 0 2006.258.01:22:31.73#ibcon#read 3, iclass 19, count 0 2006.258.01:22:31.73#ibcon#about to read 4, iclass 19, count 0 2006.258.01:22:31.73#ibcon#read 4, iclass 19, count 0 2006.258.01:22:31.73#ibcon#about to read 5, iclass 19, count 0 2006.258.01:22:31.73#ibcon#read 5, iclass 19, count 0 2006.258.01:22:31.73#ibcon#about to read 6, iclass 19, count 0 2006.258.01:22:31.73#ibcon#read 6, iclass 19, count 0 2006.258.01:22:31.73#ibcon#end of sib2, iclass 19, count 0 2006.258.01:22:31.73#ibcon#*after write, iclass 19, count 0 2006.258.01:22:31.73#ibcon#*before return 0, iclass 19, count 0 2006.258.01:22:31.73#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:31.73#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:22:31.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.01:22:31.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.01:22:31.73$vck44/vabw=wide 2006.258.01:22:31.73#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.258.01:22:31.73#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.258.01:22:31.73#ibcon#ireg 8 cls_cnt 0 2006.258.01:22:31.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:31.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:31.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:31.73#ibcon#enter wrdev, iclass 21, count 0 2006.258.01:22:31.73#ibcon#first serial, iclass 21, count 0 2006.258.01:22:31.73#ibcon#enter sib2, iclass 21, count 0 2006.258.01:22:31.73#ibcon#flushed, iclass 21, count 0 2006.258.01:22:31.73#ibcon#about to write, iclass 21, count 0 2006.258.01:22:31.73#ibcon#wrote, iclass 21, count 0 2006.258.01:22:31.73#ibcon#about to read 3, iclass 21, count 0 2006.258.01:22:31.75#ibcon#read 3, iclass 21, count 0 2006.258.01:22:31.75#ibcon#about to read 4, iclass 21, count 0 2006.258.01:22:31.75#ibcon#read 4, iclass 21, count 0 2006.258.01:22:31.75#ibcon#about to read 5, iclass 21, count 0 2006.258.01:22:31.75#ibcon#read 5, iclass 21, count 0 2006.258.01:22:31.75#ibcon#about to read 6, iclass 21, count 0 2006.258.01:22:31.75#ibcon#read 6, iclass 21, count 0 2006.258.01:22:31.75#ibcon#end of sib2, iclass 21, count 0 2006.258.01:22:31.75#ibcon#*mode == 0, iclass 21, count 0 2006.258.01:22:31.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.01:22:31.75#ibcon#[25=BW32\r\n] 2006.258.01:22:31.75#ibcon#*before write, iclass 21, count 0 2006.258.01:22:31.75#ibcon#enter sib2, iclass 21, count 0 2006.258.01:22:31.75#ibcon#flushed, iclass 21, count 0 2006.258.01:22:31.75#ibcon#about to write, iclass 21, count 0 2006.258.01:22:31.75#ibcon#wrote, iclass 21, count 0 2006.258.01:22:31.75#ibcon#about to read 3, iclass 21, count 0 2006.258.01:22:31.78#ibcon#read 3, iclass 21, count 0 2006.258.01:22:31.78#ibcon#about to read 4, iclass 21, count 0 2006.258.01:22:31.78#ibcon#read 4, iclass 21, count 0 2006.258.01:22:31.78#ibcon#about to read 5, iclass 21, count 0 2006.258.01:22:31.78#ibcon#read 5, iclass 21, count 0 2006.258.01:22:31.78#ibcon#about to read 6, iclass 21, count 0 2006.258.01:22:31.78#ibcon#read 6, iclass 21, count 0 2006.258.01:22:31.78#ibcon#end of sib2, iclass 21, count 0 2006.258.01:22:31.78#ibcon#*after write, iclass 21, count 0 2006.258.01:22:31.78#ibcon#*before return 0, iclass 21, count 0 2006.258.01:22:31.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:31.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:22:31.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.01:22:31.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.01:22:31.78$vck44/vbbw=wide 2006.258.01:22:31.78#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.01:22:31.78#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.01:22:31.78#ibcon#ireg 8 cls_cnt 0 2006.258.01:22:31.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:22:31.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:22:31.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:22:31.85#ibcon#enter wrdev, iclass 23, count 0 2006.258.01:22:31.85#ibcon#first serial, iclass 23, count 0 2006.258.01:22:31.85#ibcon#enter sib2, iclass 23, count 0 2006.258.01:22:31.85#ibcon#flushed, iclass 23, count 0 2006.258.01:22:31.85#ibcon#about to write, iclass 23, count 0 2006.258.01:22:31.85#ibcon#wrote, iclass 23, count 0 2006.258.01:22:31.85#ibcon#about to read 3, iclass 23, count 0 2006.258.01:22:31.87#ibcon#read 3, iclass 23, count 0 2006.258.01:22:31.87#ibcon#about to read 4, iclass 23, count 0 2006.258.01:22:31.87#ibcon#read 4, iclass 23, count 0 2006.258.01:22:31.87#ibcon#about to read 5, iclass 23, count 0 2006.258.01:22:31.87#ibcon#read 5, iclass 23, count 0 2006.258.01:22:31.87#ibcon#about to read 6, iclass 23, count 0 2006.258.01:22:31.87#ibcon#read 6, iclass 23, count 0 2006.258.01:22:31.87#ibcon#end of sib2, iclass 23, count 0 2006.258.01:22:31.87#ibcon#*mode == 0, iclass 23, count 0 2006.258.01:22:31.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.01:22:31.87#ibcon#[27=BW32\r\n] 2006.258.01:22:31.87#ibcon#*before write, iclass 23, count 0 2006.258.01:22:31.87#ibcon#enter sib2, iclass 23, count 0 2006.258.01:22:31.87#ibcon#flushed, iclass 23, count 0 2006.258.01:22:31.87#ibcon#about to write, iclass 23, count 0 2006.258.01:22:31.87#ibcon#wrote, iclass 23, count 0 2006.258.01:22:31.87#ibcon#about to read 3, iclass 23, count 0 2006.258.01:22:31.90#ibcon#read 3, iclass 23, count 0 2006.258.01:22:31.90#ibcon#about to read 4, iclass 23, count 0 2006.258.01:22:31.90#ibcon#read 4, iclass 23, count 0 2006.258.01:22:31.90#ibcon#about to read 5, iclass 23, count 0 2006.258.01:22:31.90#ibcon#read 5, iclass 23, count 0 2006.258.01:22:31.90#ibcon#about to read 6, iclass 23, count 0 2006.258.01:22:31.90#ibcon#read 6, iclass 23, count 0 2006.258.01:22:31.90#ibcon#end of sib2, iclass 23, count 0 2006.258.01:22:31.90#ibcon#*after write, iclass 23, count 0 2006.258.01:22:31.90#ibcon#*before return 0, iclass 23, count 0 2006.258.01:22:31.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:22:31.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:22:31.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.01:22:31.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.01:22:31.90$setupk4/ifdk4 2006.258.01:22:31.90$ifdk4/lo= 2006.258.01:22:31.90$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.01:22:31.90$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.01:22:31.90$ifdk4/patch= 2006.258.01:22:31.90$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.01:22:31.90$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.01:22:31.90$setupk4/!*+20s 2006.258.01:22:35.05#abcon#<5=/04 3.3 6.5 23.15 721016.0\r\n> 2006.258.01:22:35.07#abcon#{5=INTERFACE CLEAR} 2006.258.01:22:35.13#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:22:45.22#abcon#<5=/04 3.4 6.5 23.15 721016.0\r\n> 2006.258.01:22:45.24#abcon#{5=INTERFACE CLEAR} 2006.258.01:22:45.30#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:22:46.28$setupk4/"tpicd 2006.258.01:22:46.28$setupk4/echo=off 2006.258.01:22:46.28$setupk4/xlog=off 2006.258.01:22:46.28:!2006.258.01:23:49 2006.258.01:22:53.13#trakl#Source acquired 2006.258.01:22:54.13#flagr#flagr/antenna,acquired 2006.258.01:23:49.00:preob 2006.258.01:23:49.13/onsource/TRACKING 2006.258.01:23:49.13:!2006.258.01:23:59 2006.258.01:23:59.00:"tape 2006.258.01:23:59.00:"st=record 2006.258.01:23:59.00:data_valid=on 2006.258.01:23:59.00:midob 2006.258.01:24:00.13/onsource/TRACKING 2006.258.01:24:00.13/wx/23.16,1016.0,73 2006.258.01:24:00.20/cable/+6.4729E-03 2006.258.01:24:01.29/va/01,08,usb,yes,33,35 2006.258.01:24:01.29/va/02,07,usb,yes,35,36 2006.258.01:24:01.29/va/03,08,usb,yes,32,34 2006.258.01:24:01.29/va/04,07,usb,yes,36,38 2006.258.01:24:01.29/va/05,04,usb,yes,32,33 2006.258.01:24:01.29/va/06,04,usb,yes,36,36 2006.258.01:24:01.29/va/07,04,usb,yes,37,38 2006.258.01:24:01.29/va/08,04,usb,yes,31,38 2006.258.01:24:01.52/valo/01,524.99,yes,locked 2006.258.01:24:01.52/valo/02,534.99,yes,locked 2006.258.01:24:01.52/valo/03,564.99,yes,locked 2006.258.01:24:01.52/valo/04,624.99,yes,locked 2006.258.01:24:01.52/valo/05,734.99,yes,locked 2006.258.01:24:01.52/valo/06,814.99,yes,locked 2006.258.01:24:01.52/valo/07,864.99,yes,locked 2006.258.01:24:01.52/valo/08,884.99,yes,locked 2006.258.01:24:02.61/vb/01,04,usb,yes,32,30 2006.258.01:24:02.61/vb/02,05,usb,yes,31,30 2006.258.01:24:02.61/vb/03,04,usb,yes,32,35 2006.258.01:24:02.61/vb/04,05,usb,yes,32,31 2006.258.01:24:02.61/vb/05,04,usb,yes,28,31 2006.258.01:24:02.61/vb/06,04,usb,yes,33,29 2006.258.01:24:02.61/vb/07,04,usb,yes,33,33 2006.258.01:24:02.61/vb/08,04,usb,yes,30,34 2006.258.01:24:02.85/vblo/01,629.99,yes,locked 2006.258.01:24:02.85/vblo/02,634.99,yes,locked 2006.258.01:24:02.85/vblo/03,649.99,yes,locked 2006.258.01:24:02.85/vblo/04,679.99,yes,locked 2006.258.01:24:02.85/vblo/05,709.99,yes,locked 2006.258.01:24:02.85/vblo/06,719.99,yes,locked 2006.258.01:24:02.85/vblo/07,734.99,yes,locked 2006.258.01:24:02.85/vblo/08,744.99,yes,locked 2006.258.01:24:03.00/vabw/8 2006.258.01:24:03.15/vbbw/8 2006.258.01:24:03.24/xfe/off,on,15.2 2006.258.01:24:03.61/ifatt/23,28,28,28 2006.258.01:24:04.07/fmout-gps/S +4.52E-07 2006.258.01:24:04.11:!2006.258.01:24:39 2006.258.01:24:39.00:data_valid=off 2006.258.01:24:39.00:"et 2006.258.01:24:39.00:!+3s 2006.258.01:24:42.01:"tape 2006.258.01:24:42.01:postob 2006.258.01:24:42.12/cable/+6.4737E-03 2006.258.01:24:42.12/wx/23.16,1016.0,74 2006.258.01:24:43.07/fmout-gps/S +4.52E-07 2006.258.01:24:43.07:scan_name=258-0127,jd0609,250 2006.258.01:24:43.07:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.258.01:24:44.13#flagr#flagr/antenna,new-source 2006.258.01:24:44.13:checkk5 2006.258.01:24:44.55/chk_autoobs//k5ts1/ autoobs is running! 2006.258.01:24:44.94/chk_autoobs//k5ts2/ autoobs is running! 2006.258.01:24:45.36/chk_autoobs//k5ts3/ autoobs is running! 2006.258.01:24:45.76/chk_autoobs//k5ts4/ autoobs is running! 2006.258.01:24:46.15/chk_obsdata//k5ts1/T2580123??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.258.01:24:46.56/chk_obsdata//k5ts2/T2580123??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.258.01:24:46.97/chk_obsdata//k5ts3/T2580123??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.258.01:24:47.38/chk_obsdata//k5ts4/T2580123??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.258.01:24:48.10/k5log//k5ts1_log_newline 2006.258.01:24:48.82/k5log//k5ts2_log_newline 2006.258.01:24:49.52/k5log//k5ts3_log_newline 2006.258.01:24:50.24/k5log//k5ts4_log_newline 2006.258.01:24:50.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:24:50.26:setupk4=1 2006.258.01:24:50.26$setupk4/echo=on 2006.258.01:24:50.26$setupk4/pcalon 2006.258.01:24:50.26$pcalon/"no phase cal control is implemented here 2006.258.01:24:50.26$setupk4/"tpicd=stop 2006.258.01:24:50.26$setupk4/"rec=synch_on 2006.258.01:24:50.26$setupk4/"rec_mode=128 2006.258.01:24:50.27$setupk4/!* 2006.258.01:24:50.27$setupk4/recpk4 2006.258.01:24:50.27$recpk4/recpatch= 2006.258.01:24:50.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.01:24:50.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.01:24:50.27$setupk4/vck44 2006.258.01:24:50.27$vck44/valo=1,524.99 2006.258.01:24:50.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.01:24:50.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.01:24:50.27#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:50.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:50.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:50.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:50.27#ibcon#enter wrdev, iclass 12, count 0 2006.258.01:24:50.27#ibcon#first serial, iclass 12, count 0 2006.258.01:24:50.27#ibcon#enter sib2, iclass 12, count 0 2006.258.01:24:50.27#ibcon#flushed, iclass 12, count 0 2006.258.01:24:50.27#ibcon#about to write, iclass 12, count 0 2006.258.01:24:50.27#ibcon#wrote, iclass 12, count 0 2006.258.01:24:50.27#ibcon#about to read 3, iclass 12, count 0 2006.258.01:24:50.28#ibcon#read 3, iclass 12, count 0 2006.258.01:24:50.28#ibcon#about to read 4, iclass 12, count 0 2006.258.01:24:50.28#ibcon#read 4, iclass 12, count 0 2006.258.01:24:50.28#ibcon#about to read 5, iclass 12, count 0 2006.258.01:24:50.28#ibcon#read 5, iclass 12, count 0 2006.258.01:24:50.28#ibcon#about to read 6, iclass 12, count 0 2006.258.01:24:50.28#ibcon#read 6, iclass 12, count 0 2006.258.01:24:50.28#ibcon#end of sib2, iclass 12, count 0 2006.258.01:24:50.28#ibcon#*mode == 0, iclass 12, count 0 2006.258.01:24:50.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.01:24:50.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.01:24:50.28#ibcon#*before write, iclass 12, count 0 2006.258.01:24:50.28#ibcon#enter sib2, iclass 12, count 0 2006.258.01:24:50.28#ibcon#flushed, iclass 12, count 0 2006.258.01:24:50.28#ibcon#about to write, iclass 12, count 0 2006.258.01:24:50.28#ibcon#wrote, iclass 12, count 0 2006.258.01:24:50.28#ibcon#about to read 3, iclass 12, count 0 2006.258.01:24:50.33#ibcon#read 3, iclass 12, count 0 2006.258.01:24:50.33#ibcon#about to read 4, iclass 12, count 0 2006.258.01:24:50.33#ibcon#read 4, iclass 12, count 0 2006.258.01:24:50.33#ibcon#about to read 5, iclass 12, count 0 2006.258.01:24:50.33#ibcon#read 5, iclass 12, count 0 2006.258.01:24:50.33#ibcon#about to read 6, iclass 12, count 0 2006.258.01:24:50.33#ibcon#read 6, iclass 12, count 0 2006.258.01:24:50.33#ibcon#end of sib2, iclass 12, count 0 2006.258.01:24:50.33#ibcon#*after write, iclass 12, count 0 2006.258.01:24:50.33#ibcon#*before return 0, iclass 12, count 0 2006.258.01:24:50.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:50.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:50.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.01:24:50.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.01:24:50.33$vck44/va=1,8 2006.258.01:24:50.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.258.01:24:50.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.258.01:24:50.33#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:50.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:50.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:50.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:50.33#ibcon#enter wrdev, iclass 14, count 2 2006.258.01:24:50.33#ibcon#first serial, iclass 14, count 2 2006.258.01:24:50.33#ibcon#enter sib2, iclass 14, count 2 2006.258.01:24:50.33#ibcon#flushed, iclass 14, count 2 2006.258.01:24:50.33#ibcon#about to write, iclass 14, count 2 2006.258.01:24:50.33#ibcon#wrote, iclass 14, count 2 2006.258.01:24:50.33#ibcon#about to read 3, iclass 14, count 2 2006.258.01:24:50.35#ibcon#read 3, iclass 14, count 2 2006.258.01:24:50.35#ibcon#about to read 4, iclass 14, count 2 2006.258.01:24:50.35#ibcon#read 4, iclass 14, count 2 2006.258.01:24:50.35#ibcon#about to read 5, iclass 14, count 2 2006.258.01:24:50.35#ibcon#read 5, iclass 14, count 2 2006.258.01:24:50.35#ibcon#about to read 6, iclass 14, count 2 2006.258.01:24:50.35#ibcon#read 6, iclass 14, count 2 2006.258.01:24:50.35#ibcon#end of sib2, iclass 14, count 2 2006.258.01:24:50.35#ibcon#*mode == 0, iclass 14, count 2 2006.258.01:24:50.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.258.01:24:50.35#ibcon#[25=AT01-08\r\n] 2006.258.01:24:50.35#ibcon#*before write, iclass 14, count 2 2006.258.01:24:50.35#ibcon#enter sib2, iclass 14, count 2 2006.258.01:24:50.35#ibcon#flushed, iclass 14, count 2 2006.258.01:24:50.35#ibcon#about to write, iclass 14, count 2 2006.258.01:24:50.35#ibcon#wrote, iclass 14, count 2 2006.258.01:24:50.35#ibcon#about to read 3, iclass 14, count 2 2006.258.01:24:50.38#ibcon#read 3, iclass 14, count 2 2006.258.01:24:50.38#ibcon#about to read 4, iclass 14, count 2 2006.258.01:24:50.38#ibcon#read 4, iclass 14, count 2 2006.258.01:24:50.38#ibcon#about to read 5, iclass 14, count 2 2006.258.01:24:50.38#ibcon#read 5, iclass 14, count 2 2006.258.01:24:50.38#ibcon#about to read 6, iclass 14, count 2 2006.258.01:24:50.38#ibcon#read 6, iclass 14, count 2 2006.258.01:24:50.38#ibcon#end of sib2, iclass 14, count 2 2006.258.01:24:50.38#ibcon#*after write, iclass 14, count 2 2006.258.01:24:50.38#ibcon#*before return 0, iclass 14, count 2 2006.258.01:24:50.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:50.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:50.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.258.01:24:50.38#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:50.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:50.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:50.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:50.50#ibcon#enter wrdev, iclass 14, count 0 2006.258.01:24:50.50#ibcon#first serial, iclass 14, count 0 2006.258.01:24:50.50#ibcon#enter sib2, iclass 14, count 0 2006.258.01:24:50.50#ibcon#flushed, iclass 14, count 0 2006.258.01:24:50.50#ibcon#about to write, iclass 14, count 0 2006.258.01:24:50.50#ibcon#wrote, iclass 14, count 0 2006.258.01:24:50.50#ibcon#about to read 3, iclass 14, count 0 2006.258.01:24:50.52#ibcon#read 3, iclass 14, count 0 2006.258.01:24:50.52#ibcon#about to read 4, iclass 14, count 0 2006.258.01:24:50.52#ibcon#read 4, iclass 14, count 0 2006.258.01:24:50.52#ibcon#about to read 5, iclass 14, count 0 2006.258.01:24:50.52#ibcon#read 5, iclass 14, count 0 2006.258.01:24:50.52#ibcon#about to read 6, iclass 14, count 0 2006.258.01:24:50.52#ibcon#read 6, iclass 14, count 0 2006.258.01:24:50.52#ibcon#end of sib2, iclass 14, count 0 2006.258.01:24:50.52#ibcon#*mode == 0, iclass 14, count 0 2006.258.01:24:50.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.01:24:50.52#ibcon#[25=USB\r\n] 2006.258.01:24:50.52#ibcon#*before write, iclass 14, count 0 2006.258.01:24:50.52#ibcon#enter sib2, iclass 14, count 0 2006.258.01:24:50.52#ibcon#flushed, iclass 14, count 0 2006.258.01:24:50.52#ibcon#about to write, iclass 14, count 0 2006.258.01:24:50.52#ibcon#wrote, iclass 14, count 0 2006.258.01:24:50.52#ibcon#about to read 3, iclass 14, count 0 2006.258.01:24:50.55#ibcon#read 3, iclass 14, count 0 2006.258.01:24:50.55#ibcon#about to read 4, iclass 14, count 0 2006.258.01:24:50.55#ibcon#read 4, iclass 14, count 0 2006.258.01:24:50.55#ibcon#about to read 5, iclass 14, count 0 2006.258.01:24:50.55#ibcon#read 5, iclass 14, count 0 2006.258.01:24:50.55#ibcon#about to read 6, iclass 14, count 0 2006.258.01:24:50.55#ibcon#read 6, iclass 14, count 0 2006.258.01:24:50.55#ibcon#end of sib2, iclass 14, count 0 2006.258.01:24:50.55#ibcon#*after write, iclass 14, count 0 2006.258.01:24:50.55#ibcon#*before return 0, iclass 14, count 0 2006.258.01:24:50.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:50.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:50.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.01:24:50.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.01:24:50.55$vck44/valo=2,534.99 2006.258.01:24:50.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.01:24:50.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.01:24:50.55#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:50.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:50.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:50.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:50.55#ibcon#enter wrdev, iclass 16, count 0 2006.258.01:24:50.55#ibcon#first serial, iclass 16, count 0 2006.258.01:24:50.55#ibcon#enter sib2, iclass 16, count 0 2006.258.01:24:50.55#ibcon#flushed, iclass 16, count 0 2006.258.01:24:50.55#ibcon#about to write, iclass 16, count 0 2006.258.01:24:50.55#ibcon#wrote, iclass 16, count 0 2006.258.01:24:50.55#ibcon#about to read 3, iclass 16, count 0 2006.258.01:24:50.57#ibcon#read 3, iclass 16, count 0 2006.258.01:24:50.57#ibcon#about to read 4, iclass 16, count 0 2006.258.01:24:50.57#ibcon#read 4, iclass 16, count 0 2006.258.01:24:50.57#ibcon#about to read 5, iclass 16, count 0 2006.258.01:24:50.57#ibcon#read 5, iclass 16, count 0 2006.258.01:24:50.57#ibcon#about to read 6, iclass 16, count 0 2006.258.01:24:50.57#ibcon#read 6, iclass 16, count 0 2006.258.01:24:50.57#ibcon#end of sib2, iclass 16, count 0 2006.258.01:24:50.57#ibcon#*mode == 0, iclass 16, count 0 2006.258.01:24:50.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.01:24:50.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.01:24:50.57#ibcon#*before write, iclass 16, count 0 2006.258.01:24:50.57#ibcon#enter sib2, iclass 16, count 0 2006.258.01:24:50.57#ibcon#flushed, iclass 16, count 0 2006.258.01:24:50.57#ibcon#about to write, iclass 16, count 0 2006.258.01:24:50.57#ibcon#wrote, iclass 16, count 0 2006.258.01:24:50.57#ibcon#about to read 3, iclass 16, count 0 2006.258.01:24:50.61#ibcon#read 3, iclass 16, count 0 2006.258.01:24:50.61#ibcon#about to read 4, iclass 16, count 0 2006.258.01:24:50.61#ibcon#read 4, iclass 16, count 0 2006.258.01:24:50.61#ibcon#about to read 5, iclass 16, count 0 2006.258.01:24:50.61#ibcon#read 5, iclass 16, count 0 2006.258.01:24:50.61#ibcon#about to read 6, iclass 16, count 0 2006.258.01:24:50.61#ibcon#read 6, iclass 16, count 0 2006.258.01:24:50.61#ibcon#end of sib2, iclass 16, count 0 2006.258.01:24:50.61#ibcon#*after write, iclass 16, count 0 2006.258.01:24:50.61#ibcon#*before return 0, iclass 16, count 0 2006.258.01:24:50.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:50.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:50.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.01:24:50.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.01:24:50.61$vck44/va=2,7 2006.258.01:24:50.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.258.01:24:50.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.258.01:24:50.61#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:50.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:50.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:50.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:50.67#ibcon#enter wrdev, iclass 18, count 2 2006.258.01:24:50.67#ibcon#first serial, iclass 18, count 2 2006.258.01:24:50.67#ibcon#enter sib2, iclass 18, count 2 2006.258.01:24:50.67#ibcon#flushed, iclass 18, count 2 2006.258.01:24:50.67#ibcon#about to write, iclass 18, count 2 2006.258.01:24:50.67#ibcon#wrote, iclass 18, count 2 2006.258.01:24:50.67#ibcon#about to read 3, iclass 18, count 2 2006.258.01:24:50.69#ibcon#read 3, iclass 18, count 2 2006.258.01:24:50.69#ibcon#about to read 4, iclass 18, count 2 2006.258.01:24:50.69#ibcon#read 4, iclass 18, count 2 2006.258.01:24:50.69#ibcon#about to read 5, iclass 18, count 2 2006.258.01:24:50.69#ibcon#read 5, iclass 18, count 2 2006.258.01:24:50.69#ibcon#about to read 6, iclass 18, count 2 2006.258.01:24:50.69#ibcon#read 6, iclass 18, count 2 2006.258.01:24:50.69#ibcon#end of sib2, iclass 18, count 2 2006.258.01:24:50.69#ibcon#*mode == 0, iclass 18, count 2 2006.258.01:24:50.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.258.01:24:50.69#ibcon#[25=AT02-07\r\n] 2006.258.01:24:50.69#ibcon#*before write, iclass 18, count 2 2006.258.01:24:50.69#ibcon#enter sib2, iclass 18, count 2 2006.258.01:24:50.69#ibcon#flushed, iclass 18, count 2 2006.258.01:24:50.69#ibcon#about to write, iclass 18, count 2 2006.258.01:24:50.69#ibcon#wrote, iclass 18, count 2 2006.258.01:24:50.69#ibcon#about to read 3, iclass 18, count 2 2006.258.01:24:50.72#ibcon#read 3, iclass 18, count 2 2006.258.01:24:50.72#ibcon#about to read 4, iclass 18, count 2 2006.258.01:24:50.72#ibcon#read 4, iclass 18, count 2 2006.258.01:24:50.72#ibcon#about to read 5, iclass 18, count 2 2006.258.01:24:50.72#ibcon#read 5, iclass 18, count 2 2006.258.01:24:50.72#ibcon#about to read 6, iclass 18, count 2 2006.258.01:24:50.72#ibcon#read 6, iclass 18, count 2 2006.258.01:24:50.72#ibcon#end of sib2, iclass 18, count 2 2006.258.01:24:50.72#ibcon#*after write, iclass 18, count 2 2006.258.01:24:50.72#ibcon#*before return 0, iclass 18, count 2 2006.258.01:24:50.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:50.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:50.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.258.01:24:50.72#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:50.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:50.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:50.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:50.84#ibcon#enter wrdev, iclass 18, count 0 2006.258.01:24:50.84#ibcon#first serial, iclass 18, count 0 2006.258.01:24:50.84#ibcon#enter sib2, iclass 18, count 0 2006.258.01:24:50.84#ibcon#flushed, iclass 18, count 0 2006.258.01:24:50.84#ibcon#about to write, iclass 18, count 0 2006.258.01:24:50.84#ibcon#wrote, iclass 18, count 0 2006.258.01:24:50.84#ibcon#about to read 3, iclass 18, count 0 2006.258.01:24:50.86#ibcon#read 3, iclass 18, count 0 2006.258.01:24:50.86#ibcon#about to read 4, iclass 18, count 0 2006.258.01:24:50.86#ibcon#read 4, iclass 18, count 0 2006.258.01:24:50.86#ibcon#about to read 5, iclass 18, count 0 2006.258.01:24:50.86#ibcon#read 5, iclass 18, count 0 2006.258.01:24:50.86#ibcon#about to read 6, iclass 18, count 0 2006.258.01:24:50.86#ibcon#read 6, iclass 18, count 0 2006.258.01:24:50.86#ibcon#end of sib2, iclass 18, count 0 2006.258.01:24:50.86#ibcon#*mode == 0, iclass 18, count 0 2006.258.01:24:50.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.01:24:50.86#ibcon#[25=USB\r\n] 2006.258.01:24:50.86#ibcon#*before write, iclass 18, count 0 2006.258.01:24:50.86#ibcon#enter sib2, iclass 18, count 0 2006.258.01:24:50.86#ibcon#flushed, iclass 18, count 0 2006.258.01:24:50.86#ibcon#about to write, iclass 18, count 0 2006.258.01:24:50.86#ibcon#wrote, iclass 18, count 0 2006.258.01:24:50.86#ibcon#about to read 3, iclass 18, count 0 2006.258.01:24:50.89#ibcon#read 3, iclass 18, count 0 2006.258.01:24:50.89#ibcon#about to read 4, iclass 18, count 0 2006.258.01:24:50.89#ibcon#read 4, iclass 18, count 0 2006.258.01:24:50.89#ibcon#about to read 5, iclass 18, count 0 2006.258.01:24:50.89#ibcon#read 5, iclass 18, count 0 2006.258.01:24:50.89#ibcon#about to read 6, iclass 18, count 0 2006.258.01:24:50.89#ibcon#read 6, iclass 18, count 0 2006.258.01:24:50.89#ibcon#end of sib2, iclass 18, count 0 2006.258.01:24:50.89#ibcon#*after write, iclass 18, count 0 2006.258.01:24:50.89#ibcon#*before return 0, iclass 18, count 0 2006.258.01:24:50.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:50.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:50.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.01:24:50.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.01:24:50.89$vck44/valo=3,564.99 2006.258.01:24:50.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.01:24:50.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.01:24:50.89#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:50.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:50.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:50.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:50.89#ibcon#enter wrdev, iclass 20, count 0 2006.258.01:24:50.89#ibcon#first serial, iclass 20, count 0 2006.258.01:24:50.89#ibcon#enter sib2, iclass 20, count 0 2006.258.01:24:50.89#ibcon#flushed, iclass 20, count 0 2006.258.01:24:50.89#ibcon#about to write, iclass 20, count 0 2006.258.01:24:50.89#ibcon#wrote, iclass 20, count 0 2006.258.01:24:50.89#ibcon#about to read 3, iclass 20, count 0 2006.258.01:24:50.91#ibcon#read 3, iclass 20, count 0 2006.258.01:24:50.91#ibcon#about to read 4, iclass 20, count 0 2006.258.01:24:50.91#ibcon#read 4, iclass 20, count 0 2006.258.01:24:50.91#ibcon#about to read 5, iclass 20, count 0 2006.258.01:24:50.91#ibcon#read 5, iclass 20, count 0 2006.258.01:24:50.91#ibcon#about to read 6, iclass 20, count 0 2006.258.01:24:50.91#ibcon#read 6, iclass 20, count 0 2006.258.01:24:50.91#ibcon#end of sib2, iclass 20, count 0 2006.258.01:24:50.91#ibcon#*mode == 0, iclass 20, count 0 2006.258.01:24:50.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.01:24:50.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.01:24:50.91#ibcon#*before write, iclass 20, count 0 2006.258.01:24:50.91#ibcon#enter sib2, iclass 20, count 0 2006.258.01:24:50.91#ibcon#flushed, iclass 20, count 0 2006.258.01:24:50.91#ibcon#about to write, iclass 20, count 0 2006.258.01:24:50.91#ibcon#wrote, iclass 20, count 0 2006.258.01:24:50.91#ibcon#about to read 3, iclass 20, count 0 2006.258.01:24:50.95#ibcon#read 3, iclass 20, count 0 2006.258.01:24:50.95#ibcon#about to read 4, iclass 20, count 0 2006.258.01:24:50.95#ibcon#read 4, iclass 20, count 0 2006.258.01:24:50.95#ibcon#about to read 5, iclass 20, count 0 2006.258.01:24:50.95#ibcon#read 5, iclass 20, count 0 2006.258.01:24:50.95#ibcon#about to read 6, iclass 20, count 0 2006.258.01:24:50.95#ibcon#read 6, iclass 20, count 0 2006.258.01:24:50.95#ibcon#end of sib2, iclass 20, count 0 2006.258.01:24:50.95#ibcon#*after write, iclass 20, count 0 2006.258.01:24:50.95#ibcon#*before return 0, iclass 20, count 0 2006.258.01:24:50.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:50.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:50.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.01:24:50.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.01:24:50.95$vck44/va=3,8 2006.258.01:24:50.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.01:24:50.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.01:24:50.95#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:50.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:51.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:51.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:51.01#ibcon#enter wrdev, iclass 22, count 2 2006.258.01:24:51.01#ibcon#first serial, iclass 22, count 2 2006.258.01:24:51.01#ibcon#enter sib2, iclass 22, count 2 2006.258.01:24:51.01#ibcon#flushed, iclass 22, count 2 2006.258.01:24:51.01#ibcon#about to write, iclass 22, count 2 2006.258.01:24:51.01#ibcon#wrote, iclass 22, count 2 2006.258.01:24:51.01#ibcon#about to read 3, iclass 22, count 2 2006.258.01:24:51.03#ibcon#read 3, iclass 22, count 2 2006.258.01:24:51.03#ibcon#about to read 4, iclass 22, count 2 2006.258.01:24:51.03#ibcon#read 4, iclass 22, count 2 2006.258.01:24:51.03#ibcon#about to read 5, iclass 22, count 2 2006.258.01:24:51.03#ibcon#read 5, iclass 22, count 2 2006.258.01:24:51.03#ibcon#about to read 6, iclass 22, count 2 2006.258.01:24:51.03#ibcon#read 6, iclass 22, count 2 2006.258.01:24:51.03#ibcon#end of sib2, iclass 22, count 2 2006.258.01:24:51.03#ibcon#*mode == 0, iclass 22, count 2 2006.258.01:24:51.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.01:24:51.03#ibcon#[25=AT03-08\r\n] 2006.258.01:24:51.03#ibcon#*before write, iclass 22, count 2 2006.258.01:24:51.03#ibcon#enter sib2, iclass 22, count 2 2006.258.01:24:51.03#ibcon#flushed, iclass 22, count 2 2006.258.01:24:51.03#ibcon#about to write, iclass 22, count 2 2006.258.01:24:51.03#ibcon#wrote, iclass 22, count 2 2006.258.01:24:51.03#ibcon#about to read 3, iclass 22, count 2 2006.258.01:24:51.06#ibcon#read 3, iclass 22, count 2 2006.258.01:24:51.06#ibcon#about to read 4, iclass 22, count 2 2006.258.01:24:51.06#ibcon#read 4, iclass 22, count 2 2006.258.01:24:51.06#ibcon#about to read 5, iclass 22, count 2 2006.258.01:24:51.06#ibcon#read 5, iclass 22, count 2 2006.258.01:24:51.06#ibcon#about to read 6, iclass 22, count 2 2006.258.01:24:51.06#ibcon#read 6, iclass 22, count 2 2006.258.01:24:51.06#ibcon#end of sib2, iclass 22, count 2 2006.258.01:24:51.06#ibcon#*after write, iclass 22, count 2 2006.258.01:24:51.06#ibcon#*before return 0, iclass 22, count 2 2006.258.01:24:51.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:51.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:51.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.01:24:51.06#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:51.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:51.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:51.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:51.18#ibcon#enter wrdev, iclass 22, count 0 2006.258.01:24:51.18#ibcon#first serial, iclass 22, count 0 2006.258.01:24:51.18#ibcon#enter sib2, iclass 22, count 0 2006.258.01:24:51.18#ibcon#flushed, iclass 22, count 0 2006.258.01:24:51.18#ibcon#about to write, iclass 22, count 0 2006.258.01:24:51.18#ibcon#wrote, iclass 22, count 0 2006.258.01:24:51.18#ibcon#about to read 3, iclass 22, count 0 2006.258.01:24:51.20#ibcon#read 3, iclass 22, count 0 2006.258.01:24:51.20#ibcon#about to read 4, iclass 22, count 0 2006.258.01:24:51.20#ibcon#read 4, iclass 22, count 0 2006.258.01:24:51.20#ibcon#about to read 5, iclass 22, count 0 2006.258.01:24:51.20#ibcon#read 5, iclass 22, count 0 2006.258.01:24:51.20#ibcon#about to read 6, iclass 22, count 0 2006.258.01:24:51.20#ibcon#read 6, iclass 22, count 0 2006.258.01:24:51.20#ibcon#end of sib2, iclass 22, count 0 2006.258.01:24:51.20#ibcon#*mode == 0, iclass 22, count 0 2006.258.01:24:51.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.01:24:51.20#ibcon#[25=USB\r\n] 2006.258.01:24:51.20#ibcon#*before write, iclass 22, count 0 2006.258.01:24:51.20#ibcon#enter sib2, iclass 22, count 0 2006.258.01:24:51.20#ibcon#flushed, iclass 22, count 0 2006.258.01:24:51.20#ibcon#about to write, iclass 22, count 0 2006.258.01:24:51.20#ibcon#wrote, iclass 22, count 0 2006.258.01:24:51.20#ibcon#about to read 3, iclass 22, count 0 2006.258.01:24:51.23#ibcon#read 3, iclass 22, count 0 2006.258.01:24:51.23#ibcon#about to read 4, iclass 22, count 0 2006.258.01:24:51.23#ibcon#read 4, iclass 22, count 0 2006.258.01:24:51.23#ibcon#about to read 5, iclass 22, count 0 2006.258.01:24:51.23#ibcon#read 5, iclass 22, count 0 2006.258.01:24:51.23#ibcon#about to read 6, iclass 22, count 0 2006.258.01:24:51.23#ibcon#read 6, iclass 22, count 0 2006.258.01:24:51.23#ibcon#end of sib2, iclass 22, count 0 2006.258.01:24:51.23#ibcon#*after write, iclass 22, count 0 2006.258.01:24:51.23#ibcon#*before return 0, iclass 22, count 0 2006.258.01:24:51.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:51.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:51.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.01:24:51.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.01:24:51.23$vck44/valo=4,624.99 2006.258.01:24:51.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.01:24:51.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.01:24:51.23#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:51.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:51.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:51.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:51.23#ibcon#enter wrdev, iclass 24, count 0 2006.258.01:24:51.23#ibcon#first serial, iclass 24, count 0 2006.258.01:24:51.23#ibcon#enter sib2, iclass 24, count 0 2006.258.01:24:51.23#ibcon#flushed, iclass 24, count 0 2006.258.01:24:51.23#ibcon#about to write, iclass 24, count 0 2006.258.01:24:51.23#ibcon#wrote, iclass 24, count 0 2006.258.01:24:51.23#ibcon#about to read 3, iclass 24, count 0 2006.258.01:24:51.25#ibcon#read 3, iclass 24, count 0 2006.258.01:24:51.25#ibcon#about to read 4, iclass 24, count 0 2006.258.01:24:51.25#ibcon#read 4, iclass 24, count 0 2006.258.01:24:51.25#ibcon#about to read 5, iclass 24, count 0 2006.258.01:24:51.25#ibcon#read 5, iclass 24, count 0 2006.258.01:24:51.25#ibcon#about to read 6, iclass 24, count 0 2006.258.01:24:51.25#ibcon#read 6, iclass 24, count 0 2006.258.01:24:51.25#ibcon#end of sib2, iclass 24, count 0 2006.258.01:24:51.25#ibcon#*mode == 0, iclass 24, count 0 2006.258.01:24:51.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.01:24:51.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.01:24:51.25#ibcon#*before write, iclass 24, count 0 2006.258.01:24:51.25#ibcon#enter sib2, iclass 24, count 0 2006.258.01:24:51.25#ibcon#flushed, iclass 24, count 0 2006.258.01:24:51.25#ibcon#about to write, iclass 24, count 0 2006.258.01:24:51.25#ibcon#wrote, iclass 24, count 0 2006.258.01:24:51.25#ibcon#about to read 3, iclass 24, count 0 2006.258.01:24:51.29#ibcon#read 3, iclass 24, count 0 2006.258.01:24:51.29#ibcon#about to read 4, iclass 24, count 0 2006.258.01:24:51.29#ibcon#read 4, iclass 24, count 0 2006.258.01:24:51.29#ibcon#about to read 5, iclass 24, count 0 2006.258.01:24:51.29#ibcon#read 5, iclass 24, count 0 2006.258.01:24:51.29#ibcon#about to read 6, iclass 24, count 0 2006.258.01:24:51.29#ibcon#read 6, iclass 24, count 0 2006.258.01:24:51.29#ibcon#end of sib2, iclass 24, count 0 2006.258.01:24:51.29#ibcon#*after write, iclass 24, count 0 2006.258.01:24:51.29#ibcon#*before return 0, iclass 24, count 0 2006.258.01:24:51.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:51.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:51.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.01:24:51.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.01:24:51.29$vck44/va=4,7 2006.258.01:24:51.29#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.01:24:51.29#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.01:24:51.29#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:51.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:51.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:51.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:51.35#ibcon#enter wrdev, iclass 26, count 2 2006.258.01:24:51.35#ibcon#first serial, iclass 26, count 2 2006.258.01:24:51.35#ibcon#enter sib2, iclass 26, count 2 2006.258.01:24:51.35#ibcon#flushed, iclass 26, count 2 2006.258.01:24:51.35#ibcon#about to write, iclass 26, count 2 2006.258.01:24:51.35#ibcon#wrote, iclass 26, count 2 2006.258.01:24:51.35#ibcon#about to read 3, iclass 26, count 2 2006.258.01:24:51.37#ibcon#read 3, iclass 26, count 2 2006.258.01:24:51.37#ibcon#about to read 4, iclass 26, count 2 2006.258.01:24:51.37#ibcon#read 4, iclass 26, count 2 2006.258.01:24:51.37#ibcon#about to read 5, iclass 26, count 2 2006.258.01:24:51.37#ibcon#read 5, iclass 26, count 2 2006.258.01:24:51.37#ibcon#about to read 6, iclass 26, count 2 2006.258.01:24:51.37#ibcon#read 6, iclass 26, count 2 2006.258.01:24:51.37#ibcon#end of sib2, iclass 26, count 2 2006.258.01:24:51.37#ibcon#*mode == 0, iclass 26, count 2 2006.258.01:24:51.37#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.01:24:51.37#ibcon#[25=AT04-07\r\n] 2006.258.01:24:51.37#ibcon#*before write, iclass 26, count 2 2006.258.01:24:51.37#ibcon#enter sib2, iclass 26, count 2 2006.258.01:24:51.37#ibcon#flushed, iclass 26, count 2 2006.258.01:24:51.37#ibcon#about to write, iclass 26, count 2 2006.258.01:24:51.37#ibcon#wrote, iclass 26, count 2 2006.258.01:24:51.37#ibcon#about to read 3, iclass 26, count 2 2006.258.01:24:51.40#ibcon#read 3, iclass 26, count 2 2006.258.01:24:51.40#ibcon#about to read 4, iclass 26, count 2 2006.258.01:24:51.40#ibcon#read 4, iclass 26, count 2 2006.258.01:24:51.40#ibcon#about to read 5, iclass 26, count 2 2006.258.01:24:51.40#ibcon#read 5, iclass 26, count 2 2006.258.01:24:51.40#ibcon#about to read 6, iclass 26, count 2 2006.258.01:24:51.40#ibcon#read 6, iclass 26, count 2 2006.258.01:24:51.40#ibcon#end of sib2, iclass 26, count 2 2006.258.01:24:51.40#ibcon#*after write, iclass 26, count 2 2006.258.01:24:51.40#ibcon#*before return 0, iclass 26, count 2 2006.258.01:24:51.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:51.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:51.40#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.01:24:51.40#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:51.40#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:51.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:51.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:51.52#ibcon#enter wrdev, iclass 26, count 0 2006.258.01:24:51.52#ibcon#first serial, iclass 26, count 0 2006.258.01:24:51.52#ibcon#enter sib2, iclass 26, count 0 2006.258.01:24:51.52#ibcon#flushed, iclass 26, count 0 2006.258.01:24:51.52#ibcon#about to write, iclass 26, count 0 2006.258.01:24:51.52#ibcon#wrote, iclass 26, count 0 2006.258.01:24:51.52#ibcon#about to read 3, iclass 26, count 0 2006.258.01:24:51.54#ibcon#read 3, iclass 26, count 0 2006.258.01:24:51.54#ibcon#about to read 4, iclass 26, count 0 2006.258.01:24:51.54#ibcon#read 4, iclass 26, count 0 2006.258.01:24:51.54#ibcon#about to read 5, iclass 26, count 0 2006.258.01:24:51.54#ibcon#read 5, iclass 26, count 0 2006.258.01:24:51.54#ibcon#about to read 6, iclass 26, count 0 2006.258.01:24:51.54#ibcon#read 6, iclass 26, count 0 2006.258.01:24:51.54#ibcon#end of sib2, iclass 26, count 0 2006.258.01:24:51.54#ibcon#*mode == 0, iclass 26, count 0 2006.258.01:24:51.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.01:24:51.54#ibcon#[25=USB\r\n] 2006.258.01:24:51.54#ibcon#*before write, iclass 26, count 0 2006.258.01:24:51.54#ibcon#enter sib2, iclass 26, count 0 2006.258.01:24:51.54#ibcon#flushed, iclass 26, count 0 2006.258.01:24:51.54#ibcon#about to write, iclass 26, count 0 2006.258.01:24:51.54#ibcon#wrote, iclass 26, count 0 2006.258.01:24:51.54#ibcon#about to read 3, iclass 26, count 0 2006.258.01:24:51.57#ibcon#read 3, iclass 26, count 0 2006.258.01:24:51.57#ibcon#about to read 4, iclass 26, count 0 2006.258.01:24:51.57#ibcon#read 4, iclass 26, count 0 2006.258.01:24:51.57#ibcon#about to read 5, iclass 26, count 0 2006.258.01:24:51.57#ibcon#read 5, iclass 26, count 0 2006.258.01:24:51.57#ibcon#about to read 6, iclass 26, count 0 2006.258.01:24:51.57#ibcon#read 6, iclass 26, count 0 2006.258.01:24:51.57#ibcon#end of sib2, iclass 26, count 0 2006.258.01:24:51.57#ibcon#*after write, iclass 26, count 0 2006.258.01:24:51.57#ibcon#*before return 0, iclass 26, count 0 2006.258.01:24:51.57#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:51.57#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:51.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.01:24:51.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.01:24:51.57$vck44/valo=5,734.99 2006.258.01:24:51.57#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.01:24:51.57#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.01:24:51.57#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:51.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:51.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:51.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:51.57#ibcon#enter wrdev, iclass 28, count 0 2006.258.01:24:51.57#ibcon#first serial, iclass 28, count 0 2006.258.01:24:51.57#ibcon#enter sib2, iclass 28, count 0 2006.258.01:24:51.57#ibcon#flushed, iclass 28, count 0 2006.258.01:24:51.57#ibcon#about to write, iclass 28, count 0 2006.258.01:24:51.57#ibcon#wrote, iclass 28, count 0 2006.258.01:24:51.57#ibcon#about to read 3, iclass 28, count 0 2006.258.01:24:51.59#ibcon#read 3, iclass 28, count 0 2006.258.01:24:51.59#ibcon#about to read 4, iclass 28, count 0 2006.258.01:24:51.59#ibcon#read 4, iclass 28, count 0 2006.258.01:24:51.59#ibcon#about to read 5, iclass 28, count 0 2006.258.01:24:51.59#ibcon#read 5, iclass 28, count 0 2006.258.01:24:51.59#ibcon#about to read 6, iclass 28, count 0 2006.258.01:24:51.59#ibcon#read 6, iclass 28, count 0 2006.258.01:24:51.59#ibcon#end of sib2, iclass 28, count 0 2006.258.01:24:51.59#ibcon#*mode == 0, iclass 28, count 0 2006.258.01:24:51.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.01:24:51.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.01:24:51.59#ibcon#*before write, iclass 28, count 0 2006.258.01:24:51.59#ibcon#enter sib2, iclass 28, count 0 2006.258.01:24:51.59#ibcon#flushed, iclass 28, count 0 2006.258.01:24:51.59#ibcon#about to write, iclass 28, count 0 2006.258.01:24:51.59#ibcon#wrote, iclass 28, count 0 2006.258.01:24:51.59#ibcon#about to read 3, iclass 28, count 0 2006.258.01:24:51.63#ibcon#read 3, iclass 28, count 0 2006.258.01:24:51.63#ibcon#about to read 4, iclass 28, count 0 2006.258.01:24:51.63#ibcon#read 4, iclass 28, count 0 2006.258.01:24:51.63#ibcon#about to read 5, iclass 28, count 0 2006.258.01:24:51.63#ibcon#read 5, iclass 28, count 0 2006.258.01:24:51.63#ibcon#about to read 6, iclass 28, count 0 2006.258.01:24:51.63#ibcon#read 6, iclass 28, count 0 2006.258.01:24:51.63#ibcon#end of sib2, iclass 28, count 0 2006.258.01:24:51.63#ibcon#*after write, iclass 28, count 0 2006.258.01:24:51.63#ibcon#*before return 0, iclass 28, count 0 2006.258.01:24:51.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:51.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:51.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.01:24:51.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.01:24:51.63$vck44/va=5,4 2006.258.01:24:51.63#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.01:24:51.63#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.01:24:51.63#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:51.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:51.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:51.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:51.69#ibcon#enter wrdev, iclass 30, count 2 2006.258.01:24:51.69#ibcon#first serial, iclass 30, count 2 2006.258.01:24:51.69#ibcon#enter sib2, iclass 30, count 2 2006.258.01:24:51.69#ibcon#flushed, iclass 30, count 2 2006.258.01:24:51.69#ibcon#about to write, iclass 30, count 2 2006.258.01:24:51.69#ibcon#wrote, iclass 30, count 2 2006.258.01:24:51.69#ibcon#about to read 3, iclass 30, count 2 2006.258.01:24:51.71#ibcon#read 3, iclass 30, count 2 2006.258.01:24:51.71#ibcon#about to read 4, iclass 30, count 2 2006.258.01:24:51.71#ibcon#read 4, iclass 30, count 2 2006.258.01:24:51.71#ibcon#about to read 5, iclass 30, count 2 2006.258.01:24:51.71#ibcon#read 5, iclass 30, count 2 2006.258.01:24:51.71#ibcon#about to read 6, iclass 30, count 2 2006.258.01:24:51.71#ibcon#read 6, iclass 30, count 2 2006.258.01:24:51.71#ibcon#end of sib2, iclass 30, count 2 2006.258.01:24:51.71#ibcon#*mode == 0, iclass 30, count 2 2006.258.01:24:51.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.01:24:51.71#ibcon#[25=AT05-04\r\n] 2006.258.01:24:51.71#ibcon#*before write, iclass 30, count 2 2006.258.01:24:51.71#ibcon#enter sib2, iclass 30, count 2 2006.258.01:24:51.71#ibcon#flushed, iclass 30, count 2 2006.258.01:24:51.71#ibcon#about to write, iclass 30, count 2 2006.258.01:24:51.71#ibcon#wrote, iclass 30, count 2 2006.258.01:24:51.71#ibcon#about to read 3, iclass 30, count 2 2006.258.01:24:51.74#ibcon#read 3, iclass 30, count 2 2006.258.01:24:51.74#ibcon#about to read 4, iclass 30, count 2 2006.258.01:24:51.74#ibcon#read 4, iclass 30, count 2 2006.258.01:24:51.74#ibcon#about to read 5, iclass 30, count 2 2006.258.01:24:51.74#ibcon#read 5, iclass 30, count 2 2006.258.01:24:51.74#ibcon#about to read 6, iclass 30, count 2 2006.258.01:24:51.74#ibcon#read 6, iclass 30, count 2 2006.258.01:24:51.74#ibcon#end of sib2, iclass 30, count 2 2006.258.01:24:51.74#ibcon#*after write, iclass 30, count 2 2006.258.01:24:51.74#ibcon#*before return 0, iclass 30, count 2 2006.258.01:24:51.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:51.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:51.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.01:24:51.74#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:51.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:51.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:51.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:51.86#ibcon#enter wrdev, iclass 30, count 0 2006.258.01:24:51.86#ibcon#first serial, iclass 30, count 0 2006.258.01:24:51.86#ibcon#enter sib2, iclass 30, count 0 2006.258.01:24:51.86#ibcon#flushed, iclass 30, count 0 2006.258.01:24:51.86#ibcon#about to write, iclass 30, count 0 2006.258.01:24:51.86#ibcon#wrote, iclass 30, count 0 2006.258.01:24:51.86#ibcon#about to read 3, iclass 30, count 0 2006.258.01:24:51.88#ibcon#read 3, iclass 30, count 0 2006.258.01:24:51.88#ibcon#about to read 4, iclass 30, count 0 2006.258.01:24:51.88#ibcon#read 4, iclass 30, count 0 2006.258.01:24:51.88#ibcon#about to read 5, iclass 30, count 0 2006.258.01:24:51.88#ibcon#read 5, iclass 30, count 0 2006.258.01:24:51.88#ibcon#about to read 6, iclass 30, count 0 2006.258.01:24:51.88#ibcon#read 6, iclass 30, count 0 2006.258.01:24:51.88#ibcon#end of sib2, iclass 30, count 0 2006.258.01:24:51.88#ibcon#*mode == 0, iclass 30, count 0 2006.258.01:24:51.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.01:24:51.88#ibcon#[25=USB\r\n] 2006.258.01:24:51.88#ibcon#*before write, iclass 30, count 0 2006.258.01:24:51.88#ibcon#enter sib2, iclass 30, count 0 2006.258.01:24:51.88#ibcon#flushed, iclass 30, count 0 2006.258.01:24:51.88#ibcon#about to write, iclass 30, count 0 2006.258.01:24:51.88#ibcon#wrote, iclass 30, count 0 2006.258.01:24:51.88#ibcon#about to read 3, iclass 30, count 0 2006.258.01:24:51.91#ibcon#read 3, iclass 30, count 0 2006.258.01:24:51.91#ibcon#about to read 4, iclass 30, count 0 2006.258.01:24:51.91#ibcon#read 4, iclass 30, count 0 2006.258.01:24:51.91#ibcon#about to read 5, iclass 30, count 0 2006.258.01:24:51.91#ibcon#read 5, iclass 30, count 0 2006.258.01:24:51.91#ibcon#about to read 6, iclass 30, count 0 2006.258.01:24:51.91#ibcon#read 6, iclass 30, count 0 2006.258.01:24:51.91#ibcon#end of sib2, iclass 30, count 0 2006.258.01:24:51.91#ibcon#*after write, iclass 30, count 0 2006.258.01:24:51.91#ibcon#*before return 0, iclass 30, count 0 2006.258.01:24:51.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:51.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:51.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.01:24:51.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.01:24:51.91$vck44/valo=6,814.99 2006.258.01:24:51.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.258.01:24:51.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.258.01:24:51.91#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:51.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:51.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:51.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:51.91#ibcon#enter wrdev, iclass 32, count 0 2006.258.01:24:51.91#ibcon#first serial, iclass 32, count 0 2006.258.01:24:51.91#ibcon#enter sib2, iclass 32, count 0 2006.258.01:24:51.91#ibcon#flushed, iclass 32, count 0 2006.258.01:24:51.91#ibcon#about to write, iclass 32, count 0 2006.258.01:24:51.91#ibcon#wrote, iclass 32, count 0 2006.258.01:24:51.91#ibcon#about to read 3, iclass 32, count 0 2006.258.01:24:51.93#ibcon#read 3, iclass 32, count 0 2006.258.01:24:51.93#ibcon#about to read 4, iclass 32, count 0 2006.258.01:24:51.93#ibcon#read 4, iclass 32, count 0 2006.258.01:24:51.93#ibcon#about to read 5, iclass 32, count 0 2006.258.01:24:51.93#ibcon#read 5, iclass 32, count 0 2006.258.01:24:51.93#ibcon#about to read 6, iclass 32, count 0 2006.258.01:24:51.93#ibcon#read 6, iclass 32, count 0 2006.258.01:24:51.93#ibcon#end of sib2, iclass 32, count 0 2006.258.01:24:51.93#ibcon#*mode == 0, iclass 32, count 0 2006.258.01:24:51.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.01:24:51.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.01:24:51.93#ibcon#*before write, iclass 32, count 0 2006.258.01:24:51.93#ibcon#enter sib2, iclass 32, count 0 2006.258.01:24:51.93#ibcon#flushed, iclass 32, count 0 2006.258.01:24:51.93#ibcon#about to write, iclass 32, count 0 2006.258.01:24:51.93#ibcon#wrote, iclass 32, count 0 2006.258.01:24:51.93#ibcon#about to read 3, iclass 32, count 0 2006.258.01:24:51.97#ibcon#read 3, iclass 32, count 0 2006.258.01:24:51.97#ibcon#about to read 4, iclass 32, count 0 2006.258.01:24:51.97#ibcon#read 4, iclass 32, count 0 2006.258.01:24:51.97#ibcon#about to read 5, iclass 32, count 0 2006.258.01:24:51.97#ibcon#read 5, iclass 32, count 0 2006.258.01:24:51.97#ibcon#about to read 6, iclass 32, count 0 2006.258.01:24:51.97#ibcon#read 6, iclass 32, count 0 2006.258.01:24:51.97#ibcon#end of sib2, iclass 32, count 0 2006.258.01:24:51.97#ibcon#*after write, iclass 32, count 0 2006.258.01:24:51.97#ibcon#*before return 0, iclass 32, count 0 2006.258.01:24:51.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:51.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:51.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.01:24:51.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.01:24:51.97$vck44/va=6,4 2006.258.01:24:51.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.258.01:24:51.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.258.01:24:51.97#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:51.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:52.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:52.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:52.03#ibcon#enter wrdev, iclass 34, count 2 2006.258.01:24:52.03#ibcon#first serial, iclass 34, count 2 2006.258.01:24:52.03#ibcon#enter sib2, iclass 34, count 2 2006.258.01:24:52.03#ibcon#flushed, iclass 34, count 2 2006.258.01:24:52.03#ibcon#about to write, iclass 34, count 2 2006.258.01:24:52.03#ibcon#wrote, iclass 34, count 2 2006.258.01:24:52.03#ibcon#about to read 3, iclass 34, count 2 2006.258.01:24:52.05#ibcon#read 3, iclass 34, count 2 2006.258.01:24:52.05#ibcon#about to read 4, iclass 34, count 2 2006.258.01:24:52.05#ibcon#read 4, iclass 34, count 2 2006.258.01:24:52.05#ibcon#about to read 5, iclass 34, count 2 2006.258.01:24:52.05#ibcon#read 5, iclass 34, count 2 2006.258.01:24:52.05#ibcon#about to read 6, iclass 34, count 2 2006.258.01:24:52.05#ibcon#read 6, iclass 34, count 2 2006.258.01:24:52.05#ibcon#end of sib2, iclass 34, count 2 2006.258.01:24:52.05#ibcon#*mode == 0, iclass 34, count 2 2006.258.01:24:52.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.258.01:24:52.05#ibcon#[25=AT06-04\r\n] 2006.258.01:24:52.05#ibcon#*before write, iclass 34, count 2 2006.258.01:24:52.05#ibcon#enter sib2, iclass 34, count 2 2006.258.01:24:52.05#ibcon#flushed, iclass 34, count 2 2006.258.01:24:52.05#ibcon#about to write, iclass 34, count 2 2006.258.01:24:52.05#ibcon#wrote, iclass 34, count 2 2006.258.01:24:52.05#ibcon#about to read 3, iclass 34, count 2 2006.258.01:24:52.08#ibcon#read 3, iclass 34, count 2 2006.258.01:24:52.08#ibcon#about to read 4, iclass 34, count 2 2006.258.01:24:52.08#ibcon#read 4, iclass 34, count 2 2006.258.01:24:52.08#ibcon#about to read 5, iclass 34, count 2 2006.258.01:24:52.08#ibcon#read 5, iclass 34, count 2 2006.258.01:24:52.08#ibcon#about to read 6, iclass 34, count 2 2006.258.01:24:52.08#ibcon#read 6, iclass 34, count 2 2006.258.01:24:52.08#ibcon#end of sib2, iclass 34, count 2 2006.258.01:24:52.08#ibcon#*after write, iclass 34, count 2 2006.258.01:24:52.08#ibcon#*before return 0, iclass 34, count 2 2006.258.01:24:52.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:52.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:52.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.258.01:24:52.08#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:52.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:52.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:52.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:52.20#ibcon#enter wrdev, iclass 34, count 0 2006.258.01:24:52.20#ibcon#first serial, iclass 34, count 0 2006.258.01:24:52.20#ibcon#enter sib2, iclass 34, count 0 2006.258.01:24:52.20#ibcon#flushed, iclass 34, count 0 2006.258.01:24:52.20#ibcon#about to write, iclass 34, count 0 2006.258.01:24:52.20#ibcon#wrote, iclass 34, count 0 2006.258.01:24:52.20#ibcon#about to read 3, iclass 34, count 0 2006.258.01:24:52.22#ibcon#read 3, iclass 34, count 0 2006.258.01:24:52.22#ibcon#about to read 4, iclass 34, count 0 2006.258.01:24:52.22#ibcon#read 4, iclass 34, count 0 2006.258.01:24:52.22#ibcon#about to read 5, iclass 34, count 0 2006.258.01:24:52.22#ibcon#read 5, iclass 34, count 0 2006.258.01:24:52.22#ibcon#about to read 6, iclass 34, count 0 2006.258.01:24:52.22#ibcon#read 6, iclass 34, count 0 2006.258.01:24:52.22#ibcon#end of sib2, iclass 34, count 0 2006.258.01:24:52.22#ibcon#*mode == 0, iclass 34, count 0 2006.258.01:24:52.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.01:24:52.22#ibcon#[25=USB\r\n] 2006.258.01:24:52.22#ibcon#*before write, iclass 34, count 0 2006.258.01:24:52.22#ibcon#enter sib2, iclass 34, count 0 2006.258.01:24:52.22#ibcon#flushed, iclass 34, count 0 2006.258.01:24:52.22#ibcon#about to write, iclass 34, count 0 2006.258.01:24:52.22#ibcon#wrote, iclass 34, count 0 2006.258.01:24:52.22#ibcon#about to read 3, iclass 34, count 0 2006.258.01:24:52.25#ibcon#read 3, iclass 34, count 0 2006.258.01:24:52.25#ibcon#about to read 4, iclass 34, count 0 2006.258.01:24:52.25#ibcon#read 4, iclass 34, count 0 2006.258.01:24:52.25#ibcon#about to read 5, iclass 34, count 0 2006.258.01:24:52.25#ibcon#read 5, iclass 34, count 0 2006.258.01:24:52.25#ibcon#about to read 6, iclass 34, count 0 2006.258.01:24:52.25#ibcon#read 6, iclass 34, count 0 2006.258.01:24:52.25#ibcon#end of sib2, iclass 34, count 0 2006.258.01:24:52.25#ibcon#*after write, iclass 34, count 0 2006.258.01:24:52.25#ibcon#*before return 0, iclass 34, count 0 2006.258.01:24:52.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:52.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:52.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.01:24:52.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.01:24:52.25$vck44/valo=7,864.99 2006.258.01:24:52.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.258.01:24:52.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.258.01:24:52.25#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:52.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:52.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:52.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:52.25#ibcon#enter wrdev, iclass 36, count 0 2006.258.01:24:52.25#ibcon#first serial, iclass 36, count 0 2006.258.01:24:52.25#ibcon#enter sib2, iclass 36, count 0 2006.258.01:24:52.25#ibcon#flushed, iclass 36, count 0 2006.258.01:24:52.25#ibcon#about to write, iclass 36, count 0 2006.258.01:24:52.25#ibcon#wrote, iclass 36, count 0 2006.258.01:24:52.25#ibcon#about to read 3, iclass 36, count 0 2006.258.01:24:52.27#ibcon#read 3, iclass 36, count 0 2006.258.01:24:52.27#ibcon#about to read 4, iclass 36, count 0 2006.258.01:24:52.27#ibcon#read 4, iclass 36, count 0 2006.258.01:24:52.27#ibcon#about to read 5, iclass 36, count 0 2006.258.01:24:52.27#ibcon#read 5, iclass 36, count 0 2006.258.01:24:52.27#ibcon#about to read 6, iclass 36, count 0 2006.258.01:24:52.27#ibcon#read 6, iclass 36, count 0 2006.258.01:24:52.27#ibcon#end of sib2, iclass 36, count 0 2006.258.01:24:52.27#ibcon#*mode == 0, iclass 36, count 0 2006.258.01:24:52.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.01:24:52.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.01:24:52.27#ibcon#*before write, iclass 36, count 0 2006.258.01:24:52.27#ibcon#enter sib2, iclass 36, count 0 2006.258.01:24:52.27#ibcon#flushed, iclass 36, count 0 2006.258.01:24:52.27#ibcon#about to write, iclass 36, count 0 2006.258.01:24:52.27#ibcon#wrote, iclass 36, count 0 2006.258.01:24:52.27#ibcon#about to read 3, iclass 36, count 0 2006.258.01:24:52.31#ibcon#read 3, iclass 36, count 0 2006.258.01:24:52.31#ibcon#about to read 4, iclass 36, count 0 2006.258.01:24:52.31#ibcon#read 4, iclass 36, count 0 2006.258.01:24:52.31#ibcon#about to read 5, iclass 36, count 0 2006.258.01:24:52.31#ibcon#read 5, iclass 36, count 0 2006.258.01:24:52.31#ibcon#about to read 6, iclass 36, count 0 2006.258.01:24:52.31#ibcon#read 6, iclass 36, count 0 2006.258.01:24:52.31#ibcon#end of sib2, iclass 36, count 0 2006.258.01:24:52.31#ibcon#*after write, iclass 36, count 0 2006.258.01:24:52.31#ibcon#*before return 0, iclass 36, count 0 2006.258.01:24:52.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:52.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:52.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.01:24:52.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.01:24:52.31$vck44/va=7,4 2006.258.01:24:52.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.258.01:24:52.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.258.01:24:52.31#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:52.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:52.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:52.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:52.37#ibcon#enter wrdev, iclass 38, count 2 2006.258.01:24:52.37#ibcon#first serial, iclass 38, count 2 2006.258.01:24:52.37#ibcon#enter sib2, iclass 38, count 2 2006.258.01:24:52.37#ibcon#flushed, iclass 38, count 2 2006.258.01:24:52.37#ibcon#about to write, iclass 38, count 2 2006.258.01:24:52.37#ibcon#wrote, iclass 38, count 2 2006.258.01:24:52.37#ibcon#about to read 3, iclass 38, count 2 2006.258.01:24:52.39#ibcon#read 3, iclass 38, count 2 2006.258.01:24:52.39#ibcon#about to read 4, iclass 38, count 2 2006.258.01:24:52.39#ibcon#read 4, iclass 38, count 2 2006.258.01:24:52.39#ibcon#about to read 5, iclass 38, count 2 2006.258.01:24:52.39#ibcon#read 5, iclass 38, count 2 2006.258.01:24:52.39#ibcon#about to read 6, iclass 38, count 2 2006.258.01:24:52.39#ibcon#read 6, iclass 38, count 2 2006.258.01:24:52.39#ibcon#end of sib2, iclass 38, count 2 2006.258.01:24:52.39#ibcon#*mode == 0, iclass 38, count 2 2006.258.01:24:52.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.258.01:24:52.39#ibcon#[25=AT07-04\r\n] 2006.258.01:24:52.39#ibcon#*before write, iclass 38, count 2 2006.258.01:24:52.39#ibcon#enter sib2, iclass 38, count 2 2006.258.01:24:52.39#ibcon#flushed, iclass 38, count 2 2006.258.01:24:52.39#ibcon#about to write, iclass 38, count 2 2006.258.01:24:52.39#ibcon#wrote, iclass 38, count 2 2006.258.01:24:52.39#ibcon#about to read 3, iclass 38, count 2 2006.258.01:24:52.42#ibcon#read 3, iclass 38, count 2 2006.258.01:24:52.42#ibcon#about to read 4, iclass 38, count 2 2006.258.01:24:52.42#ibcon#read 4, iclass 38, count 2 2006.258.01:24:52.42#ibcon#about to read 5, iclass 38, count 2 2006.258.01:24:52.42#ibcon#read 5, iclass 38, count 2 2006.258.01:24:52.42#ibcon#about to read 6, iclass 38, count 2 2006.258.01:24:52.42#ibcon#read 6, iclass 38, count 2 2006.258.01:24:52.42#ibcon#end of sib2, iclass 38, count 2 2006.258.01:24:52.42#ibcon#*after write, iclass 38, count 2 2006.258.01:24:52.42#ibcon#*before return 0, iclass 38, count 2 2006.258.01:24:52.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:52.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:52.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.258.01:24:52.42#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:52.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:52.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:52.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:52.54#ibcon#enter wrdev, iclass 38, count 0 2006.258.01:24:52.54#ibcon#first serial, iclass 38, count 0 2006.258.01:24:52.54#ibcon#enter sib2, iclass 38, count 0 2006.258.01:24:52.54#ibcon#flushed, iclass 38, count 0 2006.258.01:24:52.54#ibcon#about to write, iclass 38, count 0 2006.258.01:24:52.54#ibcon#wrote, iclass 38, count 0 2006.258.01:24:52.54#ibcon#about to read 3, iclass 38, count 0 2006.258.01:24:52.56#ibcon#read 3, iclass 38, count 0 2006.258.01:24:52.56#ibcon#about to read 4, iclass 38, count 0 2006.258.01:24:52.56#ibcon#read 4, iclass 38, count 0 2006.258.01:24:52.56#ibcon#about to read 5, iclass 38, count 0 2006.258.01:24:52.56#ibcon#read 5, iclass 38, count 0 2006.258.01:24:52.56#ibcon#about to read 6, iclass 38, count 0 2006.258.01:24:52.56#ibcon#read 6, iclass 38, count 0 2006.258.01:24:52.56#ibcon#end of sib2, iclass 38, count 0 2006.258.01:24:52.56#ibcon#*mode == 0, iclass 38, count 0 2006.258.01:24:52.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.01:24:52.56#ibcon#[25=USB\r\n] 2006.258.01:24:52.56#ibcon#*before write, iclass 38, count 0 2006.258.01:24:52.56#ibcon#enter sib2, iclass 38, count 0 2006.258.01:24:52.56#ibcon#flushed, iclass 38, count 0 2006.258.01:24:52.56#ibcon#about to write, iclass 38, count 0 2006.258.01:24:52.56#ibcon#wrote, iclass 38, count 0 2006.258.01:24:52.56#ibcon#about to read 3, iclass 38, count 0 2006.258.01:24:52.59#ibcon#read 3, iclass 38, count 0 2006.258.01:24:52.59#ibcon#about to read 4, iclass 38, count 0 2006.258.01:24:52.59#ibcon#read 4, iclass 38, count 0 2006.258.01:24:52.59#ibcon#about to read 5, iclass 38, count 0 2006.258.01:24:52.59#ibcon#read 5, iclass 38, count 0 2006.258.01:24:52.59#ibcon#about to read 6, iclass 38, count 0 2006.258.01:24:52.59#ibcon#read 6, iclass 38, count 0 2006.258.01:24:52.59#ibcon#end of sib2, iclass 38, count 0 2006.258.01:24:52.59#ibcon#*after write, iclass 38, count 0 2006.258.01:24:52.59#ibcon#*before return 0, iclass 38, count 0 2006.258.01:24:52.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:52.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:52.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.01:24:52.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.01:24:52.59$vck44/valo=8,884.99 2006.258.01:24:52.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.01:24:52.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.01:24:52.59#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:52.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:52.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:52.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:52.59#ibcon#enter wrdev, iclass 40, count 0 2006.258.01:24:52.59#ibcon#first serial, iclass 40, count 0 2006.258.01:24:52.59#ibcon#enter sib2, iclass 40, count 0 2006.258.01:24:52.59#ibcon#flushed, iclass 40, count 0 2006.258.01:24:52.59#ibcon#about to write, iclass 40, count 0 2006.258.01:24:52.59#ibcon#wrote, iclass 40, count 0 2006.258.01:24:52.59#ibcon#about to read 3, iclass 40, count 0 2006.258.01:24:52.61#ibcon#read 3, iclass 40, count 0 2006.258.01:24:52.61#ibcon#about to read 4, iclass 40, count 0 2006.258.01:24:52.61#ibcon#read 4, iclass 40, count 0 2006.258.01:24:52.61#ibcon#about to read 5, iclass 40, count 0 2006.258.01:24:52.61#ibcon#read 5, iclass 40, count 0 2006.258.01:24:52.61#ibcon#about to read 6, iclass 40, count 0 2006.258.01:24:52.61#ibcon#read 6, iclass 40, count 0 2006.258.01:24:52.61#ibcon#end of sib2, iclass 40, count 0 2006.258.01:24:52.61#ibcon#*mode == 0, iclass 40, count 0 2006.258.01:24:52.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.01:24:52.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.01:24:52.61#ibcon#*before write, iclass 40, count 0 2006.258.01:24:52.61#ibcon#enter sib2, iclass 40, count 0 2006.258.01:24:52.61#ibcon#flushed, iclass 40, count 0 2006.258.01:24:52.61#ibcon#about to write, iclass 40, count 0 2006.258.01:24:52.61#ibcon#wrote, iclass 40, count 0 2006.258.01:24:52.61#ibcon#about to read 3, iclass 40, count 0 2006.258.01:24:52.65#ibcon#read 3, iclass 40, count 0 2006.258.01:24:52.65#ibcon#about to read 4, iclass 40, count 0 2006.258.01:24:52.65#ibcon#read 4, iclass 40, count 0 2006.258.01:24:52.65#ibcon#about to read 5, iclass 40, count 0 2006.258.01:24:52.65#ibcon#read 5, iclass 40, count 0 2006.258.01:24:52.65#ibcon#about to read 6, iclass 40, count 0 2006.258.01:24:52.65#ibcon#read 6, iclass 40, count 0 2006.258.01:24:52.65#ibcon#end of sib2, iclass 40, count 0 2006.258.01:24:52.65#ibcon#*after write, iclass 40, count 0 2006.258.01:24:52.65#ibcon#*before return 0, iclass 40, count 0 2006.258.01:24:52.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:52.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:52.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.01:24:52.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.01:24:52.65$vck44/va=8,4 2006.258.01:24:52.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.258.01:24:52.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.258.01:24:52.65#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:52.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:24:52.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:24:52.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:24:52.71#ibcon#enter wrdev, iclass 4, count 2 2006.258.01:24:52.71#ibcon#first serial, iclass 4, count 2 2006.258.01:24:52.71#ibcon#enter sib2, iclass 4, count 2 2006.258.01:24:52.71#ibcon#flushed, iclass 4, count 2 2006.258.01:24:52.71#ibcon#about to write, iclass 4, count 2 2006.258.01:24:52.71#ibcon#wrote, iclass 4, count 2 2006.258.01:24:52.71#ibcon#about to read 3, iclass 4, count 2 2006.258.01:24:52.73#ibcon#read 3, iclass 4, count 2 2006.258.01:24:52.73#ibcon#about to read 4, iclass 4, count 2 2006.258.01:24:52.73#ibcon#read 4, iclass 4, count 2 2006.258.01:24:52.73#ibcon#about to read 5, iclass 4, count 2 2006.258.01:24:52.73#ibcon#read 5, iclass 4, count 2 2006.258.01:24:52.73#ibcon#about to read 6, iclass 4, count 2 2006.258.01:24:52.73#ibcon#read 6, iclass 4, count 2 2006.258.01:24:52.73#ibcon#end of sib2, iclass 4, count 2 2006.258.01:24:52.73#ibcon#*mode == 0, iclass 4, count 2 2006.258.01:24:52.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.258.01:24:52.73#ibcon#[25=AT08-04\r\n] 2006.258.01:24:52.73#ibcon#*before write, iclass 4, count 2 2006.258.01:24:52.73#ibcon#enter sib2, iclass 4, count 2 2006.258.01:24:52.73#ibcon#flushed, iclass 4, count 2 2006.258.01:24:52.73#ibcon#about to write, iclass 4, count 2 2006.258.01:24:52.73#ibcon#wrote, iclass 4, count 2 2006.258.01:24:52.73#ibcon#about to read 3, iclass 4, count 2 2006.258.01:24:52.76#ibcon#read 3, iclass 4, count 2 2006.258.01:24:52.76#ibcon#about to read 4, iclass 4, count 2 2006.258.01:24:52.76#ibcon#read 4, iclass 4, count 2 2006.258.01:24:52.76#ibcon#about to read 5, iclass 4, count 2 2006.258.01:24:52.76#ibcon#read 5, iclass 4, count 2 2006.258.01:24:52.76#ibcon#about to read 6, iclass 4, count 2 2006.258.01:24:52.76#ibcon#read 6, iclass 4, count 2 2006.258.01:24:52.76#ibcon#end of sib2, iclass 4, count 2 2006.258.01:24:52.76#ibcon#*after write, iclass 4, count 2 2006.258.01:24:52.76#ibcon#*before return 0, iclass 4, count 2 2006.258.01:24:52.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:24:52.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.258.01:24:52.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.258.01:24:52.76#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:52.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:24:52.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:24:52.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:24:52.88#ibcon#enter wrdev, iclass 4, count 0 2006.258.01:24:52.88#ibcon#first serial, iclass 4, count 0 2006.258.01:24:52.88#ibcon#enter sib2, iclass 4, count 0 2006.258.01:24:52.88#ibcon#flushed, iclass 4, count 0 2006.258.01:24:52.88#ibcon#about to write, iclass 4, count 0 2006.258.01:24:52.88#ibcon#wrote, iclass 4, count 0 2006.258.01:24:52.88#ibcon#about to read 3, iclass 4, count 0 2006.258.01:24:52.90#ibcon#read 3, iclass 4, count 0 2006.258.01:24:52.90#ibcon#about to read 4, iclass 4, count 0 2006.258.01:24:52.90#ibcon#read 4, iclass 4, count 0 2006.258.01:24:52.90#ibcon#about to read 5, iclass 4, count 0 2006.258.01:24:52.90#ibcon#read 5, iclass 4, count 0 2006.258.01:24:52.90#ibcon#about to read 6, iclass 4, count 0 2006.258.01:24:52.90#ibcon#read 6, iclass 4, count 0 2006.258.01:24:52.90#ibcon#end of sib2, iclass 4, count 0 2006.258.01:24:52.90#ibcon#*mode == 0, iclass 4, count 0 2006.258.01:24:52.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.01:24:52.90#ibcon#[25=USB\r\n] 2006.258.01:24:52.90#ibcon#*before write, iclass 4, count 0 2006.258.01:24:52.90#ibcon#enter sib2, iclass 4, count 0 2006.258.01:24:52.90#ibcon#flushed, iclass 4, count 0 2006.258.01:24:52.90#ibcon#about to write, iclass 4, count 0 2006.258.01:24:52.90#ibcon#wrote, iclass 4, count 0 2006.258.01:24:52.90#ibcon#about to read 3, iclass 4, count 0 2006.258.01:24:52.93#ibcon#read 3, iclass 4, count 0 2006.258.01:24:52.93#ibcon#about to read 4, iclass 4, count 0 2006.258.01:24:52.93#ibcon#read 4, iclass 4, count 0 2006.258.01:24:52.93#ibcon#about to read 5, iclass 4, count 0 2006.258.01:24:52.93#ibcon#read 5, iclass 4, count 0 2006.258.01:24:52.93#ibcon#about to read 6, iclass 4, count 0 2006.258.01:24:52.93#ibcon#read 6, iclass 4, count 0 2006.258.01:24:52.93#ibcon#end of sib2, iclass 4, count 0 2006.258.01:24:52.93#ibcon#*after write, iclass 4, count 0 2006.258.01:24:52.93#ibcon#*before return 0, iclass 4, count 0 2006.258.01:24:52.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:24:52.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.258.01:24:52.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.01:24:52.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.01:24:52.93$vck44/vblo=1,629.99 2006.258.01:24:52.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.258.01:24:52.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.258.01:24:52.93#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:52.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:24:52.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:24:52.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:24:52.93#ibcon#enter wrdev, iclass 6, count 0 2006.258.01:24:52.93#ibcon#first serial, iclass 6, count 0 2006.258.01:24:52.93#ibcon#enter sib2, iclass 6, count 0 2006.258.01:24:52.93#ibcon#flushed, iclass 6, count 0 2006.258.01:24:52.93#ibcon#about to write, iclass 6, count 0 2006.258.01:24:52.93#ibcon#wrote, iclass 6, count 0 2006.258.01:24:52.93#ibcon#about to read 3, iclass 6, count 0 2006.258.01:24:52.95#ibcon#read 3, iclass 6, count 0 2006.258.01:24:52.95#ibcon#about to read 4, iclass 6, count 0 2006.258.01:24:52.95#ibcon#read 4, iclass 6, count 0 2006.258.01:24:52.95#ibcon#about to read 5, iclass 6, count 0 2006.258.01:24:52.95#ibcon#read 5, iclass 6, count 0 2006.258.01:24:52.95#ibcon#about to read 6, iclass 6, count 0 2006.258.01:24:52.95#ibcon#read 6, iclass 6, count 0 2006.258.01:24:52.95#ibcon#end of sib2, iclass 6, count 0 2006.258.01:24:52.95#ibcon#*mode == 0, iclass 6, count 0 2006.258.01:24:52.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.01:24:52.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.01:24:52.95#ibcon#*before write, iclass 6, count 0 2006.258.01:24:52.95#ibcon#enter sib2, iclass 6, count 0 2006.258.01:24:52.95#ibcon#flushed, iclass 6, count 0 2006.258.01:24:52.95#ibcon#about to write, iclass 6, count 0 2006.258.01:24:52.95#ibcon#wrote, iclass 6, count 0 2006.258.01:24:52.95#ibcon#about to read 3, iclass 6, count 0 2006.258.01:24:52.99#ibcon#read 3, iclass 6, count 0 2006.258.01:24:52.99#ibcon#about to read 4, iclass 6, count 0 2006.258.01:24:52.99#ibcon#read 4, iclass 6, count 0 2006.258.01:24:52.99#ibcon#about to read 5, iclass 6, count 0 2006.258.01:24:52.99#ibcon#read 5, iclass 6, count 0 2006.258.01:24:52.99#ibcon#about to read 6, iclass 6, count 0 2006.258.01:24:52.99#ibcon#read 6, iclass 6, count 0 2006.258.01:24:52.99#ibcon#end of sib2, iclass 6, count 0 2006.258.01:24:52.99#ibcon#*after write, iclass 6, count 0 2006.258.01:24:52.99#ibcon#*before return 0, iclass 6, count 0 2006.258.01:24:52.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:24:52.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.258.01:24:52.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.01:24:52.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.01:24:52.99$vck44/vb=1,4 2006.258.01:24:52.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.258.01:24:52.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.258.01:24:52.99#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:52.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:24:52.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:24:52.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:24:52.99#ibcon#enter wrdev, iclass 10, count 2 2006.258.01:24:52.99#ibcon#first serial, iclass 10, count 2 2006.258.01:24:52.99#ibcon#enter sib2, iclass 10, count 2 2006.258.01:24:52.99#ibcon#flushed, iclass 10, count 2 2006.258.01:24:52.99#ibcon#about to write, iclass 10, count 2 2006.258.01:24:52.99#ibcon#wrote, iclass 10, count 2 2006.258.01:24:52.99#ibcon#about to read 3, iclass 10, count 2 2006.258.01:24:53.01#ibcon#read 3, iclass 10, count 2 2006.258.01:24:53.01#ibcon#about to read 4, iclass 10, count 2 2006.258.01:24:53.01#ibcon#read 4, iclass 10, count 2 2006.258.01:24:53.01#ibcon#about to read 5, iclass 10, count 2 2006.258.01:24:53.01#ibcon#read 5, iclass 10, count 2 2006.258.01:24:53.01#ibcon#about to read 6, iclass 10, count 2 2006.258.01:24:53.01#ibcon#read 6, iclass 10, count 2 2006.258.01:24:53.01#ibcon#end of sib2, iclass 10, count 2 2006.258.01:24:53.01#ibcon#*mode == 0, iclass 10, count 2 2006.258.01:24:53.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.258.01:24:53.01#ibcon#[27=AT01-04\r\n] 2006.258.01:24:53.01#ibcon#*before write, iclass 10, count 2 2006.258.01:24:53.01#ibcon#enter sib2, iclass 10, count 2 2006.258.01:24:53.01#ibcon#flushed, iclass 10, count 2 2006.258.01:24:53.01#ibcon#about to write, iclass 10, count 2 2006.258.01:24:53.01#ibcon#wrote, iclass 10, count 2 2006.258.01:24:53.01#ibcon#about to read 3, iclass 10, count 2 2006.258.01:24:53.04#ibcon#read 3, iclass 10, count 2 2006.258.01:24:53.04#ibcon#about to read 4, iclass 10, count 2 2006.258.01:24:53.04#ibcon#read 4, iclass 10, count 2 2006.258.01:24:53.04#ibcon#about to read 5, iclass 10, count 2 2006.258.01:24:53.04#ibcon#read 5, iclass 10, count 2 2006.258.01:24:53.04#ibcon#about to read 6, iclass 10, count 2 2006.258.01:24:53.04#ibcon#read 6, iclass 10, count 2 2006.258.01:24:53.04#ibcon#end of sib2, iclass 10, count 2 2006.258.01:24:53.04#ibcon#*after write, iclass 10, count 2 2006.258.01:24:53.04#ibcon#*before return 0, iclass 10, count 2 2006.258.01:24:53.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:24:53.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.258.01:24:53.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.258.01:24:53.04#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:53.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:24:53.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:24:53.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:24:53.16#ibcon#enter wrdev, iclass 10, count 0 2006.258.01:24:53.16#ibcon#first serial, iclass 10, count 0 2006.258.01:24:53.16#ibcon#enter sib2, iclass 10, count 0 2006.258.01:24:53.16#ibcon#flushed, iclass 10, count 0 2006.258.01:24:53.16#ibcon#about to write, iclass 10, count 0 2006.258.01:24:53.16#ibcon#wrote, iclass 10, count 0 2006.258.01:24:53.16#ibcon#about to read 3, iclass 10, count 0 2006.258.01:24:53.18#ibcon#read 3, iclass 10, count 0 2006.258.01:24:53.18#ibcon#about to read 4, iclass 10, count 0 2006.258.01:24:53.18#ibcon#read 4, iclass 10, count 0 2006.258.01:24:53.18#ibcon#about to read 5, iclass 10, count 0 2006.258.01:24:53.18#ibcon#read 5, iclass 10, count 0 2006.258.01:24:53.18#ibcon#about to read 6, iclass 10, count 0 2006.258.01:24:53.18#ibcon#read 6, iclass 10, count 0 2006.258.01:24:53.18#ibcon#end of sib2, iclass 10, count 0 2006.258.01:24:53.18#ibcon#*mode == 0, iclass 10, count 0 2006.258.01:24:53.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.01:24:53.18#ibcon#[27=USB\r\n] 2006.258.01:24:53.18#ibcon#*before write, iclass 10, count 0 2006.258.01:24:53.18#ibcon#enter sib2, iclass 10, count 0 2006.258.01:24:53.18#ibcon#flushed, iclass 10, count 0 2006.258.01:24:53.18#ibcon#about to write, iclass 10, count 0 2006.258.01:24:53.18#ibcon#wrote, iclass 10, count 0 2006.258.01:24:53.18#ibcon#about to read 3, iclass 10, count 0 2006.258.01:24:53.21#ibcon#read 3, iclass 10, count 0 2006.258.01:24:53.21#ibcon#about to read 4, iclass 10, count 0 2006.258.01:24:53.21#ibcon#read 4, iclass 10, count 0 2006.258.01:24:53.21#ibcon#about to read 5, iclass 10, count 0 2006.258.01:24:53.21#ibcon#read 5, iclass 10, count 0 2006.258.01:24:53.21#ibcon#about to read 6, iclass 10, count 0 2006.258.01:24:53.21#ibcon#read 6, iclass 10, count 0 2006.258.01:24:53.21#ibcon#end of sib2, iclass 10, count 0 2006.258.01:24:53.21#ibcon#*after write, iclass 10, count 0 2006.258.01:24:53.21#ibcon#*before return 0, iclass 10, count 0 2006.258.01:24:53.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:24:53.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.258.01:24:53.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.01:24:53.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.01:24:53.21$vck44/vblo=2,634.99 2006.258.01:24:53.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.258.01:24:53.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.258.01:24:53.21#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:53.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:53.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:53.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:53.21#ibcon#enter wrdev, iclass 12, count 0 2006.258.01:24:53.21#ibcon#first serial, iclass 12, count 0 2006.258.01:24:53.21#ibcon#enter sib2, iclass 12, count 0 2006.258.01:24:53.21#ibcon#flushed, iclass 12, count 0 2006.258.01:24:53.21#ibcon#about to write, iclass 12, count 0 2006.258.01:24:53.21#ibcon#wrote, iclass 12, count 0 2006.258.01:24:53.21#ibcon#about to read 3, iclass 12, count 0 2006.258.01:24:53.23#ibcon#read 3, iclass 12, count 0 2006.258.01:24:53.23#ibcon#about to read 4, iclass 12, count 0 2006.258.01:24:53.23#ibcon#read 4, iclass 12, count 0 2006.258.01:24:53.23#ibcon#about to read 5, iclass 12, count 0 2006.258.01:24:53.23#ibcon#read 5, iclass 12, count 0 2006.258.01:24:53.23#ibcon#about to read 6, iclass 12, count 0 2006.258.01:24:53.23#ibcon#read 6, iclass 12, count 0 2006.258.01:24:53.23#ibcon#end of sib2, iclass 12, count 0 2006.258.01:24:53.23#ibcon#*mode == 0, iclass 12, count 0 2006.258.01:24:53.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.01:24:53.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.01:24:53.23#ibcon#*before write, iclass 12, count 0 2006.258.01:24:53.23#ibcon#enter sib2, iclass 12, count 0 2006.258.01:24:53.23#ibcon#flushed, iclass 12, count 0 2006.258.01:24:53.23#ibcon#about to write, iclass 12, count 0 2006.258.01:24:53.23#ibcon#wrote, iclass 12, count 0 2006.258.01:24:53.23#ibcon#about to read 3, iclass 12, count 0 2006.258.01:24:53.27#ibcon#read 3, iclass 12, count 0 2006.258.01:24:53.27#ibcon#about to read 4, iclass 12, count 0 2006.258.01:24:53.27#ibcon#read 4, iclass 12, count 0 2006.258.01:24:53.27#ibcon#about to read 5, iclass 12, count 0 2006.258.01:24:53.27#ibcon#read 5, iclass 12, count 0 2006.258.01:24:53.27#ibcon#about to read 6, iclass 12, count 0 2006.258.01:24:53.27#ibcon#read 6, iclass 12, count 0 2006.258.01:24:53.27#ibcon#end of sib2, iclass 12, count 0 2006.258.01:24:53.27#ibcon#*after write, iclass 12, count 0 2006.258.01:24:53.27#ibcon#*before return 0, iclass 12, count 0 2006.258.01:24:53.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:53.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.258.01:24:53.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.01:24:53.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.01:24:53.27$vck44/vb=2,5 2006.258.01:24:53.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.258.01:24:53.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.258.01:24:53.27#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:53.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:53.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:53.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:53.33#ibcon#enter wrdev, iclass 14, count 2 2006.258.01:24:53.33#ibcon#first serial, iclass 14, count 2 2006.258.01:24:53.33#ibcon#enter sib2, iclass 14, count 2 2006.258.01:24:53.33#ibcon#flushed, iclass 14, count 2 2006.258.01:24:53.33#ibcon#about to write, iclass 14, count 2 2006.258.01:24:53.33#ibcon#wrote, iclass 14, count 2 2006.258.01:24:53.33#ibcon#about to read 3, iclass 14, count 2 2006.258.01:24:53.35#ibcon#read 3, iclass 14, count 2 2006.258.01:24:53.35#ibcon#about to read 4, iclass 14, count 2 2006.258.01:24:53.35#ibcon#read 4, iclass 14, count 2 2006.258.01:24:53.35#ibcon#about to read 5, iclass 14, count 2 2006.258.01:24:53.35#ibcon#read 5, iclass 14, count 2 2006.258.01:24:53.35#ibcon#about to read 6, iclass 14, count 2 2006.258.01:24:53.35#ibcon#read 6, iclass 14, count 2 2006.258.01:24:53.35#ibcon#end of sib2, iclass 14, count 2 2006.258.01:24:53.35#ibcon#*mode == 0, iclass 14, count 2 2006.258.01:24:53.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.258.01:24:53.35#ibcon#[27=AT02-05\r\n] 2006.258.01:24:53.35#ibcon#*before write, iclass 14, count 2 2006.258.01:24:53.35#ibcon#enter sib2, iclass 14, count 2 2006.258.01:24:53.35#ibcon#flushed, iclass 14, count 2 2006.258.01:24:53.35#ibcon#about to write, iclass 14, count 2 2006.258.01:24:53.35#ibcon#wrote, iclass 14, count 2 2006.258.01:24:53.35#ibcon#about to read 3, iclass 14, count 2 2006.258.01:24:53.38#ibcon#read 3, iclass 14, count 2 2006.258.01:24:53.38#ibcon#about to read 4, iclass 14, count 2 2006.258.01:24:53.38#ibcon#read 4, iclass 14, count 2 2006.258.01:24:53.38#ibcon#about to read 5, iclass 14, count 2 2006.258.01:24:53.38#ibcon#read 5, iclass 14, count 2 2006.258.01:24:53.38#ibcon#about to read 6, iclass 14, count 2 2006.258.01:24:53.38#ibcon#read 6, iclass 14, count 2 2006.258.01:24:53.38#ibcon#end of sib2, iclass 14, count 2 2006.258.01:24:53.38#ibcon#*after write, iclass 14, count 2 2006.258.01:24:53.38#ibcon#*before return 0, iclass 14, count 2 2006.258.01:24:53.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:53.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.258.01:24:53.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.258.01:24:53.38#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:53.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:53.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:53.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:53.50#ibcon#enter wrdev, iclass 14, count 0 2006.258.01:24:53.50#ibcon#first serial, iclass 14, count 0 2006.258.01:24:53.50#ibcon#enter sib2, iclass 14, count 0 2006.258.01:24:53.50#ibcon#flushed, iclass 14, count 0 2006.258.01:24:53.50#ibcon#about to write, iclass 14, count 0 2006.258.01:24:53.50#ibcon#wrote, iclass 14, count 0 2006.258.01:24:53.50#ibcon#about to read 3, iclass 14, count 0 2006.258.01:24:53.52#ibcon#read 3, iclass 14, count 0 2006.258.01:24:53.52#ibcon#about to read 4, iclass 14, count 0 2006.258.01:24:53.52#ibcon#read 4, iclass 14, count 0 2006.258.01:24:53.52#ibcon#about to read 5, iclass 14, count 0 2006.258.01:24:53.52#ibcon#read 5, iclass 14, count 0 2006.258.01:24:53.52#ibcon#about to read 6, iclass 14, count 0 2006.258.01:24:53.52#ibcon#read 6, iclass 14, count 0 2006.258.01:24:53.52#ibcon#end of sib2, iclass 14, count 0 2006.258.01:24:53.52#ibcon#*mode == 0, iclass 14, count 0 2006.258.01:24:53.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.01:24:53.52#ibcon#[27=USB\r\n] 2006.258.01:24:53.52#ibcon#*before write, iclass 14, count 0 2006.258.01:24:53.52#ibcon#enter sib2, iclass 14, count 0 2006.258.01:24:53.52#ibcon#flushed, iclass 14, count 0 2006.258.01:24:53.52#ibcon#about to write, iclass 14, count 0 2006.258.01:24:53.52#ibcon#wrote, iclass 14, count 0 2006.258.01:24:53.52#ibcon#about to read 3, iclass 14, count 0 2006.258.01:24:53.55#ibcon#read 3, iclass 14, count 0 2006.258.01:24:53.55#ibcon#about to read 4, iclass 14, count 0 2006.258.01:24:53.55#ibcon#read 4, iclass 14, count 0 2006.258.01:24:53.55#ibcon#about to read 5, iclass 14, count 0 2006.258.01:24:53.55#ibcon#read 5, iclass 14, count 0 2006.258.01:24:53.55#ibcon#about to read 6, iclass 14, count 0 2006.258.01:24:53.55#ibcon#read 6, iclass 14, count 0 2006.258.01:24:53.55#ibcon#end of sib2, iclass 14, count 0 2006.258.01:24:53.55#ibcon#*after write, iclass 14, count 0 2006.258.01:24:53.55#ibcon#*before return 0, iclass 14, count 0 2006.258.01:24:53.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:53.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.258.01:24:53.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.01:24:53.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.01:24:53.55$vck44/vblo=3,649.99 2006.258.01:24:53.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.01:24:53.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.01:24:53.55#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:53.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:53.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:53.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:53.55#ibcon#enter wrdev, iclass 16, count 0 2006.258.01:24:53.55#ibcon#first serial, iclass 16, count 0 2006.258.01:24:53.55#ibcon#enter sib2, iclass 16, count 0 2006.258.01:24:53.55#ibcon#flushed, iclass 16, count 0 2006.258.01:24:53.55#ibcon#about to write, iclass 16, count 0 2006.258.01:24:53.55#ibcon#wrote, iclass 16, count 0 2006.258.01:24:53.55#ibcon#about to read 3, iclass 16, count 0 2006.258.01:24:53.57#ibcon#read 3, iclass 16, count 0 2006.258.01:24:53.57#ibcon#about to read 4, iclass 16, count 0 2006.258.01:24:53.57#ibcon#read 4, iclass 16, count 0 2006.258.01:24:53.57#ibcon#about to read 5, iclass 16, count 0 2006.258.01:24:53.57#ibcon#read 5, iclass 16, count 0 2006.258.01:24:53.57#ibcon#about to read 6, iclass 16, count 0 2006.258.01:24:53.57#ibcon#read 6, iclass 16, count 0 2006.258.01:24:53.57#ibcon#end of sib2, iclass 16, count 0 2006.258.01:24:53.57#ibcon#*mode == 0, iclass 16, count 0 2006.258.01:24:53.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.01:24:53.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.01:24:53.57#ibcon#*before write, iclass 16, count 0 2006.258.01:24:53.57#ibcon#enter sib2, iclass 16, count 0 2006.258.01:24:53.57#ibcon#flushed, iclass 16, count 0 2006.258.01:24:53.57#ibcon#about to write, iclass 16, count 0 2006.258.01:24:53.57#ibcon#wrote, iclass 16, count 0 2006.258.01:24:53.57#ibcon#about to read 3, iclass 16, count 0 2006.258.01:24:53.61#ibcon#read 3, iclass 16, count 0 2006.258.01:24:53.61#ibcon#about to read 4, iclass 16, count 0 2006.258.01:24:53.61#ibcon#read 4, iclass 16, count 0 2006.258.01:24:53.61#ibcon#about to read 5, iclass 16, count 0 2006.258.01:24:53.61#ibcon#read 5, iclass 16, count 0 2006.258.01:24:53.61#ibcon#about to read 6, iclass 16, count 0 2006.258.01:24:53.61#ibcon#read 6, iclass 16, count 0 2006.258.01:24:53.61#ibcon#end of sib2, iclass 16, count 0 2006.258.01:24:53.61#ibcon#*after write, iclass 16, count 0 2006.258.01:24:53.61#ibcon#*before return 0, iclass 16, count 0 2006.258.01:24:53.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:53.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:24:53.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.01:24:53.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.01:24:53.61$vck44/vb=3,4 2006.258.01:24:53.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.258.01:24:53.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.258.01:24:53.61#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:53.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:53.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:53.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:53.67#ibcon#enter wrdev, iclass 18, count 2 2006.258.01:24:53.67#ibcon#first serial, iclass 18, count 2 2006.258.01:24:53.67#ibcon#enter sib2, iclass 18, count 2 2006.258.01:24:53.67#ibcon#flushed, iclass 18, count 2 2006.258.01:24:53.67#ibcon#about to write, iclass 18, count 2 2006.258.01:24:53.67#ibcon#wrote, iclass 18, count 2 2006.258.01:24:53.67#ibcon#about to read 3, iclass 18, count 2 2006.258.01:24:53.69#ibcon#read 3, iclass 18, count 2 2006.258.01:24:53.69#ibcon#about to read 4, iclass 18, count 2 2006.258.01:24:53.69#ibcon#read 4, iclass 18, count 2 2006.258.01:24:53.69#ibcon#about to read 5, iclass 18, count 2 2006.258.01:24:53.69#ibcon#read 5, iclass 18, count 2 2006.258.01:24:53.69#ibcon#about to read 6, iclass 18, count 2 2006.258.01:24:53.69#ibcon#read 6, iclass 18, count 2 2006.258.01:24:53.69#ibcon#end of sib2, iclass 18, count 2 2006.258.01:24:53.69#ibcon#*mode == 0, iclass 18, count 2 2006.258.01:24:53.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.258.01:24:53.69#ibcon#[27=AT03-04\r\n] 2006.258.01:24:53.69#ibcon#*before write, iclass 18, count 2 2006.258.01:24:53.69#ibcon#enter sib2, iclass 18, count 2 2006.258.01:24:53.69#ibcon#flushed, iclass 18, count 2 2006.258.01:24:53.69#ibcon#about to write, iclass 18, count 2 2006.258.01:24:53.69#ibcon#wrote, iclass 18, count 2 2006.258.01:24:53.69#ibcon#about to read 3, iclass 18, count 2 2006.258.01:24:53.72#ibcon#read 3, iclass 18, count 2 2006.258.01:24:53.72#ibcon#about to read 4, iclass 18, count 2 2006.258.01:24:53.72#ibcon#read 4, iclass 18, count 2 2006.258.01:24:53.72#ibcon#about to read 5, iclass 18, count 2 2006.258.01:24:53.72#ibcon#read 5, iclass 18, count 2 2006.258.01:24:53.72#ibcon#about to read 6, iclass 18, count 2 2006.258.01:24:53.72#ibcon#read 6, iclass 18, count 2 2006.258.01:24:53.72#ibcon#end of sib2, iclass 18, count 2 2006.258.01:24:53.72#ibcon#*after write, iclass 18, count 2 2006.258.01:24:53.72#ibcon#*before return 0, iclass 18, count 2 2006.258.01:24:53.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:53.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.258.01:24:53.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.258.01:24:53.72#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:53.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:53.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:53.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:53.84#ibcon#enter wrdev, iclass 18, count 0 2006.258.01:24:53.84#ibcon#first serial, iclass 18, count 0 2006.258.01:24:53.84#ibcon#enter sib2, iclass 18, count 0 2006.258.01:24:53.84#ibcon#flushed, iclass 18, count 0 2006.258.01:24:53.84#ibcon#about to write, iclass 18, count 0 2006.258.01:24:53.84#ibcon#wrote, iclass 18, count 0 2006.258.01:24:53.84#ibcon#about to read 3, iclass 18, count 0 2006.258.01:24:53.86#ibcon#read 3, iclass 18, count 0 2006.258.01:24:53.86#ibcon#about to read 4, iclass 18, count 0 2006.258.01:24:53.86#ibcon#read 4, iclass 18, count 0 2006.258.01:24:53.86#ibcon#about to read 5, iclass 18, count 0 2006.258.01:24:53.86#ibcon#read 5, iclass 18, count 0 2006.258.01:24:53.86#ibcon#about to read 6, iclass 18, count 0 2006.258.01:24:53.86#ibcon#read 6, iclass 18, count 0 2006.258.01:24:53.86#ibcon#end of sib2, iclass 18, count 0 2006.258.01:24:53.86#ibcon#*mode == 0, iclass 18, count 0 2006.258.01:24:53.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.01:24:53.86#ibcon#[27=USB\r\n] 2006.258.01:24:53.86#ibcon#*before write, iclass 18, count 0 2006.258.01:24:53.86#ibcon#enter sib2, iclass 18, count 0 2006.258.01:24:53.86#ibcon#flushed, iclass 18, count 0 2006.258.01:24:53.86#ibcon#about to write, iclass 18, count 0 2006.258.01:24:53.86#ibcon#wrote, iclass 18, count 0 2006.258.01:24:53.86#ibcon#about to read 3, iclass 18, count 0 2006.258.01:24:53.89#ibcon#read 3, iclass 18, count 0 2006.258.01:24:53.89#ibcon#about to read 4, iclass 18, count 0 2006.258.01:24:53.89#ibcon#read 4, iclass 18, count 0 2006.258.01:24:53.89#ibcon#about to read 5, iclass 18, count 0 2006.258.01:24:53.89#ibcon#read 5, iclass 18, count 0 2006.258.01:24:53.89#ibcon#about to read 6, iclass 18, count 0 2006.258.01:24:53.89#ibcon#read 6, iclass 18, count 0 2006.258.01:24:53.89#ibcon#end of sib2, iclass 18, count 0 2006.258.01:24:53.89#ibcon#*after write, iclass 18, count 0 2006.258.01:24:53.89#ibcon#*before return 0, iclass 18, count 0 2006.258.01:24:53.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:53.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.258.01:24:53.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.01:24:53.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.01:24:53.89$vck44/vblo=4,679.99 2006.258.01:24:53.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.01:24:53.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.01:24:53.89#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:53.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:53.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:53.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:53.89#ibcon#enter wrdev, iclass 20, count 0 2006.258.01:24:53.89#ibcon#first serial, iclass 20, count 0 2006.258.01:24:53.89#ibcon#enter sib2, iclass 20, count 0 2006.258.01:24:53.89#ibcon#flushed, iclass 20, count 0 2006.258.01:24:53.89#ibcon#about to write, iclass 20, count 0 2006.258.01:24:53.89#ibcon#wrote, iclass 20, count 0 2006.258.01:24:53.89#ibcon#about to read 3, iclass 20, count 0 2006.258.01:24:53.91#ibcon#read 3, iclass 20, count 0 2006.258.01:24:53.91#ibcon#about to read 4, iclass 20, count 0 2006.258.01:24:53.91#ibcon#read 4, iclass 20, count 0 2006.258.01:24:53.91#ibcon#about to read 5, iclass 20, count 0 2006.258.01:24:53.91#ibcon#read 5, iclass 20, count 0 2006.258.01:24:53.91#ibcon#about to read 6, iclass 20, count 0 2006.258.01:24:53.91#ibcon#read 6, iclass 20, count 0 2006.258.01:24:53.91#ibcon#end of sib2, iclass 20, count 0 2006.258.01:24:53.91#ibcon#*mode == 0, iclass 20, count 0 2006.258.01:24:53.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.01:24:53.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.01:24:53.91#ibcon#*before write, iclass 20, count 0 2006.258.01:24:53.91#ibcon#enter sib2, iclass 20, count 0 2006.258.01:24:53.91#ibcon#flushed, iclass 20, count 0 2006.258.01:24:53.91#ibcon#about to write, iclass 20, count 0 2006.258.01:24:53.91#ibcon#wrote, iclass 20, count 0 2006.258.01:24:53.91#ibcon#about to read 3, iclass 20, count 0 2006.258.01:24:53.95#ibcon#read 3, iclass 20, count 0 2006.258.01:24:53.95#ibcon#about to read 4, iclass 20, count 0 2006.258.01:24:53.95#ibcon#read 4, iclass 20, count 0 2006.258.01:24:53.95#ibcon#about to read 5, iclass 20, count 0 2006.258.01:24:53.95#ibcon#read 5, iclass 20, count 0 2006.258.01:24:53.95#ibcon#about to read 6, iclass 20, count 0 2006.258.01:24:53.95#ibcon#read 6, iclass 20, count 0 2006.258.01:24:53.95#ibcon#end of sib2, iclass 20, count 0 2006.258.01:24:53.95#ibcon#*after write, iclass 20, count 0 2006.258.01:24:53.95#ibcon#*before return 0, iclass 20, count 0 2006.258.01:24:53.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:53.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:24:53.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.01:24:53.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.01:24:53.95$vck44/vb=4,5 2006.258.01:24:53.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.258.01:24:53.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.258.01:24:53.95#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:53.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:54.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:54.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:54.01#ibcon#enter wrdev, iclass 22, count 2 2006.258.01:24:54.01#ibcon#first serial, iclass 22, count 2 2006.258.01:24:54.01#ibcon#enter sib2, iclass 22, count 2 2006.258.01:24:54.01#ibcon#flushed, iclass 22, count 2 2006.258.01:24:54.01#ibcon#about to write, iclass 22, count 2 2006.258.01:24:54.01#ibcon#wrote, iclass 22, count 2 2006.258.01:24:54.01#ibcon#about to read 3, iclass 22, count 2 2006.258.01:24:54.03#ibcon#read 3, iclass 22, count 2 2006.258.01:24:54.03#ibcon#about to read 4, iclass 22, count 2 2006.258.01:24:54.03#ibcon#read 4, iclass 22, count 2 2006.258.01:24:54.03#ibcon#about to read 5, iclass 22, count 2 2006.258.01:24:54.03#ibcon#read 5, iclass 22, count 2 2006.258.01:24:54.03#ibcon#about to read 6, iclass 22, count 2 2006.258.01:24:54.03#ibcon#read 6, iclass 22, count 2 2006.258.01:24:54.03#ibcon#end of sib2, iclass 22, count 2 2006.258.01:24:54.03#ibcon#*mode == 0, iclass 22, count 2 2006.258.01:24:54.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.258.01:24:54.03#ibcon#[27=AT04-05\r\n] 2006.258.01:24:54.03#ibcon#*before write, iclass 22, count 2 2006.258.01:24:54.03#ibcon#enter sib2, iclass 22, count 2 2006.258.01:24:54.03#ibcon#flushed, iclass 22, count 2 2006.258.01:24:54.03#ibcon#about to write, iclass 22, count 2 2006.258.01:24:54.03#ibcon#wrote, iclass 22, count 2 2006.258.01:24:54.03#ibcon#about to read 3, iclass 22, count 2 2006.258.01:24:54.06#ibcon#read 3, iclass 22, count 2 2006.258.01:24:54.06#ibcon#about to read 4, iclass 22, count 2 2006.258.01:24:54.06#ibcon#read 4, iclass 22, count 2 2006.258.01:24:54.06#ibcon#about to read 5, iclass 22, count 2 2006.258.01:24:54.06#ibcon#read 5, iclass 22, count 2 2006.258.01:24:54.06#ibcon#about to read 6, iclass 22, count 2 2006.258.01:24:54.06#ibcon#read 6, iclass 22, count 2 2006.258.01:24:54.06#ibcon#end of sib2, iclass 22, count 2 2006.258.01:24:54.06#ibcon#*after write, iclass 22, count 2 2006.258.01:24:54.06#ibcon#*before return 0, iclass 22, count 2 2006.258.01:24:54.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:54.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.258.01:24:54.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.258.01:24:54.06#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:54.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:54.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:54.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:54.18#ibcon#enter wrdev, iclass 22, count 0 2006.258.01:24:54.18#ibcon#first serial, iclass 22, count 0 2006.258.01:24:54.18#ibcon#enter sib2, iclass 22, count 0 2006.258.01:24:54.18#ibcon#flushed, iclass 22, count 0 2006.258.01:24:54.18#ibcon#about to write, iclass 22, count 0 2006.258.01:24:54.18#ibcon#wrote, iclass 22, count 0 2006.258.01:24:54.18#ibcon#about to read 3, iclass 22, count 0 2006.258.01:24:54.20#ibcon#read 3, iclass 22, count 0 2006.258.01:24:54.20#ibcon#about to read 4, iclass 22, count 0 2006.258.01:24:54.20#ibcon#read 4, iclass 22, count 0 2006.258.01:24:54.20#ibcon#about to read 5, iclass 22, count 0 2006.258.01:24:54.20#ibcon#read 5, iclass 22, count 0 2006.258.01:24:54.20#ibcon#about to read 6, iclass 22, count 0 2006.258.01:24:54.20#ibcon#read 6, iclass 22, count 0 2006.258.01:24:54.20#ibcon#end of sib2, iclass 22, count 0 2006.258.01:24:54.20#ibcon#*mode == 0, iclass 22, count 0 2006.258.01:24:54.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.01:24:54.20#ibcon#[27=USB\r\n] 2006.258.01:24:54.20#ibcon#*before write, iclass 22, count 0 2006.258.01:24:54.20#ibcon#enter sib2, iclass 22, count 0 2006.258.01:24:54.20#ibcon#flushed, iclass 22, count 0 2006.258.01:24:54.20#ibcon#about to write, iclass 22, count 0 2006.258.01:24:54.20#ibcon#wrote, iclass 22, count 0 2006.258.01:24:54.20#ibcon#about to read 3, iclass 22, count 0 2006.258.01:24:54.23#ibcon#read 3, iclass 22, count 0 2006.258.01:24:54.23#ibcon#about to read 4, iclass 22, count 0 2006.258.01:24:54.23#ibcon#read 4, iclass 22, count 0 2006.258.01:24:54.23#ibcon#about to read 5, iclass 22, count 0 2006.258.01:24:54.23#ibcon#read 5, iclass 22, count 0 2006.258.01:24:54.23#ibcon#about to read 6, iclass 22, count 0 2006.258.01:24:54.23#ibcon#read 6, iclass 22, count 0 2006.258.01:24:54.23#ibcon#end of sib2, iclass 22, count 0 2006.258.01:24:54.23#ibcon#*after write, iclass 22, count 0 2006.258.01:24:54.23#ibcon#*before return 0, iclass 22, count 0 2006.258.01:24:54.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:54.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.258.01:24:54.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.01:24:54.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.01:24:54.23$vck44/vblo=5,709.99 2006.258.01:24:54.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.258.01:24:54.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.258.01:24:54.23#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:54.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:54.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:54.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:54.23#ibcon#enter wrdev, iclass 24, count 0 2006.258.01:24:54.23#ibcon#first serial, iclass 24, count 0 2006.258.01:24:54.23#ibcon#enter sib2, iclass 24, count 0 2006.258.01:24:54.23#ibcon#flushed, iclass 24, count 0 2006.258.01:24:54.23#ibcon#about to write, iclass 24, count 0 2006.258.01:24:54.23#ibcon#wrote, iclass 24, count 0 2006.258.01:24:54.23#ibcon#about to read 3, iclass 24, count 0 2006.258.01:24:54.25#ibcon#read 3, iclass 24, count 0 2006.258.01:24:54.25#ibcon#about to read 4, iclass 24, count 0 2006.258.01:24:54.25#ibcon#read 4, iclass 24, count 0 2006.258.01:24:54.25#ibcon#about to read 5, iclass 24, count 0 2006.258.01:24:54.25#ibcon#read 5, iclass 24, count 0 2006.258.01:24:54.25#ibcon#about to read 6, iclass 24, count 0 2006.258.01:24:54.25#ibcon#read 6, iclass 24, count 0 2006.258.01:24:54.25#ibcon#end of sib2, iclass 24, count 0 2006.258.01:24:54.25#ibcon#*mode == 0, iclass 24, count 0 2006.258.01:24:54.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.01:24:54.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.01:24:54.25#ibcon#*before write, iclass 24, count 0 2006.258.01:24:54.25#ibcon#enter sib2, iclass 24, count 0 2006.258.01:24:54.25#ibcon#flushed, iclass 24, count 0 2006.258.01:24:54.25#ibcon#about to write, iclass 24, count 0 2006.258.01:24:54.25#ibcon#wrote, iclass 24, count 0 2006.258.01:24:54.25#ibcon#about to read 3, iclass 24, count 0 2006.258.01:24:54.29#ibcon#read 3, iclass 24, count 0 2006.258.01:24:54.29#ibcon#about to read 4, iclass 24, count 0 2006.258.01:24:54.29#ibcon#read 4, iclass 24, count 0 2006.258.01:24:54.29#ibcon#about to read 5, iclass 24, count 0 2006.258.01:24:54.29#ibcon#read 5, iclass 24, count 0 2006.258.01:24:54.29#ibcon#about to read 6, iclass 24, count 0 2006.258.01:24:54.29#ibcon#read 6, iclass 24, count 0 2006.258.01:24:54.29#ibcon#end of sib2, iclass 24, count 0 2006.258.01:24:54.29#ibcon#*after write, iclass 24, count 0 2006.258.01:24:54.29#ibcon#*before return 0, iclass 24, count 0 2006.258.01:24:54.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:54.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.258.01:24:54.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.01:24:54.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.01:24:54.29$vck44/vb=5,4 2006.258.01:24:54.29#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.258.01:24:54.29#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.258.01:24:54.29#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:54.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:54.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:54.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:54.35#ibcon#enter wrdev, iclass 26, count 2 2006.258.01:24:54.35#ibcon#first serial, iclass 26, count 2 2006.258.01:24:54.35#ibcon#enter sib2, iclass 26, count 2 2006.258.01:24:54.35#ibcon#flushed, iclass 26, count 2 2006.258.01:24:54.35#ibcon#about to write, iclass 26, count 2 2006.258.01:24:54.35#ibcon#wrote, iclass 26, count 2 2006.258.01:24:54.35#ibcon#about to read 3, iclass 26, count 2 2006.258.01:24:54.37#ibcon#read 3, iclass 26, count 2 2006.258.01:24:54.37#ibcon#about to read 4, iclass 26, count 2 2006.258.01:24:54.37#ibcon#read 4, iclass 26, count 2 2006.258.01:24:54.37#ibcon#about to read 5, iclass 26, count 2 2006.258.01:24:54.37#ibcon#read 5, iclass 26, count 2 2006.258.01:24:54.37#ibcon#about to read 6, iclass 26, count 2 2006.258.01:24:54.37#ibcon#read 6, iclass 26, count 2 2006.258.01:24:54.37#ibcon#end of sib2, iclass 26, count 2 2006.258.01:24:54.37#ibcon#*mode == 0, iclass 26, count 2 2006.258.01:24:54.37#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.258.01:24:54.37#ibcon#[27=AT05-04\r\n] 2006.258.01:24:54.37#ibcon#*before write, iclass 26, count 2 2006.258.01:24:54.37#ibcon#enter sib2, iclass 26, count 2 2006.258.01:24:54.37#ibcon#flushed, iclass 26, count 2 2006.258.01:24:54.37#ibcon#about to write, iclass 26, count 2 2006.258.01:24:54.37#ibcon#wrote, iclass 26, count 2 2006.258.01:24:54.37#ibcon#about to read 3, iclass 26, count 2 2006.258.01:24:54.40#ibcon#read 3, iclass 26, count 2 2006.258.01:24:54.41#ibcon#about to read 4, iclass 26, count 2 2006.258.01:24:54.41#ibcon#read 4, iclass 26, count 2 2006.258.01:24:54.41#ibcon#about to read 5, iclass 26, count 2 2006.258.01:24:54.41#ibcon#read 5, iclass 26, count 2 2006.258.01:24:54.41#ibcon#about to read 6, iclass 26, count 2 2006.258.01:24:54.41#ibcon#read 6, iclass 26, count 2 2006.258.01:24:54.41#ibcon#end of sib2, iclass 26, count 2 2006.258.01:24:54.41#ibcon#*after write, iclass 26, count 2 2006.258.01:24:54.41#ibcon#*before return 0, iclass 26, count 2 2006.258.01:24:54.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:54.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.258.01:24:54.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.258.01:24:54.41#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:54.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:54.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:54.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:54.52#ibcon#enter wrdev, iclass 26, count 0 2006.258.01:24:54.52#ibcon#first serial, iclass 26, count 0 2006.258.01:24:54.52#ibcon#enter sib2, iclass 26, count 0 2006.258.01:24:54.52#ibcon#flushed, iclass 26, count 0 2006.258.01:24:54.52#ibcon#about to write, iclass 26, count 0 2006.258.01:24:54.52#ibcon#wrote, iclass 26, count 0 2006.258.01:24:54.52#ibcon#about to read 3, iclass 26, count 0 2006.258.01:24:54.54#ibcon#read 3, iclass 26, count 0 2006.258.01:24:54.54#ibcon#about to read 4, iclass 26, count 0 2006.258.01:24:54.54#ibcon#read 4, iclass 26, count 0 2006.258.01:24:54.54#ibcon#about to read 5, iclass 26, count 0 2006.258.01:24:54.54#ibcon#read 5, iclass 26, count 0 2006.258.01:24:54.54#ibcon#about to read 6, iclass 26, count 0 2006.258.01:24:54.54#ibcon#read 6, iclass 26, count 0 2006.258.01:24:54.54#ibcon#end of sib2, iclass 26, count 0 2006.258.01:24:54.54#ibcon#*mode == 0, iclass 26, count 0 2006.258.01:24:54.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.01:24:54.54#ibcon#[27=USB\r\n] 2006.258.01:24:54.54#ibcon#*before write, iclass 26, count 0 2006.258.01:24:54.54#ibcon#enter sib2, iclass 26, count 0 2006.258.01:24:54.54#ibcon#flushed, iclass 26, count 0 2006.258.01:24:54.54#ibcon#about to write, iclass 26, count 0 2006.258.01:24:54.54#ibcon#wrote, iclass 26, count 0 2006.258.01:24:54.54#ibcon#about to read 3, iclass 26, count 0 2006.258.01:24:54.57#ibcon#read 3, iclass 26, count 0 2006.258.01:24:54.57#ibcon#about to read 4, iclass 26, count 0 2006.258.01:24:54.57#ibcon#read 4, iclass 26, count 0 2006.258.01:24:54.57#ibcon#about to read 5, iclass 26, count 0 2006.258.01:24:54.57#ibcon#read 5, iclass 26, count 0 2006.258.01:24:54.57#ibcon#about to read 6, iclass 26, count 0 2006.258.01:24:54.57#ibcon#read 6, iclass 26, count 0 2006.258.01:24:54.57#ibcon#end of sib2, iclass 26, count 0 2006.258.01:24:54.57#ibcon#*after write, iclass 26, count 0 2006.258.01:24:54.57#ibcon#*before return 0, iclass 26, count 0 2006.258.01:24:54.57#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:54.57#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.258.01:24:54.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.01:24:54.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.01:24:54.57$vck44/vblo=6,719.99 2006.258.01:24:54.57#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.258.01:24:54.57#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.258.01:24:54.57#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:54.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:54.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:54.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:54.57#ibcon#enter wrdev, iclass 28, count 0 2006.258.01:24:54.57#ibcon#first serial, iclass 28, count 0 2006.258.01:24:54.57#ibcon#enter sib2, iclass 28, count 0 2006.258.01:24:54.57#ibcon#flushed, iclass 28, count 0 2006.258.01:24:54.57#ibcon#about to write, iclass 28, count 0 2006.258.01:24:54.57#ibcon#wrote, iclass 28, count 0 2006.258.01:24:54.57#ibcon#about to read 3, iclass 28, count 0 2006.258.01:24:54.59#ibcon#read 3, iclass 28, count 0 2006.258.01:24:54.59#ibcon#about to read 4, iclass 28, count 0 2006.258.01:24:54.59#ibcon#read 4, iclass 28, count 0 2006.258.01:24:54.59#ibcon#about to read 5, iclass 28, count 0 2006.258.01:24:54.59#ibcon#read 5, iclass 28, count 0 2006.258.01:24:54.59#ibcon#about to read 6, iclass 28, count 0 2006.258.01:24:54.59#ibcon#read 6, iclass 28, count 0 2006.258.01:24:54.59#ibcon#end of sib2, iclass 28, count 0 2006.258.01:24:54.59#ibcon#*mode == 0, iclass 28, count 0 2006.258.01:24:54.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.01:24:54.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.01:24:54.59#ibcon#*before write, iclass 28, count 0 2006.258.01:24:54.59#ibcon#enter sib2, iclass 28, count 0 2006.258.01:24:54.59#ibcon#flushed, iclass 28, count 0 2006.258.01:24:54.59#ibcon#about to write, iclass 28, count 0 2006.258.01:24:54.59#ibcon#wrote, iclass 28, count 0 2006.258.01:24:54.59#ibcon#about to read 3, iclass 28, count 0 2006.258.01:24:54.63#ibcon#read 3, iclass 28, count 0 2006.258.01:24:54.63#ibcon#about to read 4, iclass 28, count 0 2006.258.01:24:54.63#ibcon#read 4, iclass 28, count 0 2006.258.01:24:54.63#ibcon#about to read 5, iclass 28, count 0 2006.258.01:24:54.63#ibcon#read 5, iclass 28, count 0 2006.258.01:24:54.63#ibcon#about to read 6, iclass 28, count 0 2006.258.01:24:54.63#ibcon#read 6, iclass 28, count 0 2006.258.01:24:54.63#ibcon#end of sib2, iclass 28, count 0 2006.258.01:24:54.63#ibcon#*after write, iclass 28, count 0 2006.258.01:24:54.63#ibcon#*before return 0, iclass 28, count 0 2006.258.01:24:54.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:54.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.258.01:24:54.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.01:24:54.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.01:24:54.63$vck44/vb=6,4 2006.258.01:24:54.63#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.258.01:24:54.63#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.258.01:24:54.63#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:54.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:54.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:54.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:54.69#ibcon#enter wrdev, iclass 30, count 2 2006.258.01:24:54.69#ibcon#first serial, iclass 30, count 2 2006.258.01:24:54.69#ibcon#enter sib2, iclass 30, count 2 2006.258.01:24:54.69#ibcon#flushed, iclass 30, count 2 2006.258.01:24:54.69#ibcon#about to write, iclass 30, count 2 2006.258.01:24:54.69#ibcon#wrote, iclass 30, count 2 2006.258.01:24:54.69#ibcon#about to read 3, iclass 30, count 2 2006.258.01:24:54.71#ibcon#read 3, iclass 30, count 2 2006.258.01:24:54.71#ibcon#about to read 4, iclass 30, count 2 2006.258.01:24:54.71#ibcon#read 4, iclass 30, count 2 2006.258.01:24:54.71#ibcon#about to read 5, iclass 30, count 2 2006.258.01:24:54.71#ibcon#read 5, iclass 30, count 2 2006.258.01:24:54.71#ibcon#about to read 6, iclass 30, count 2 2006.258.01:24:54.71#ibcon#read 6, iclass 30, count 2 2006.258.01:24:54.71#ibcon#end of sib2, iclass 30, count 2 2006.258.01:24:54.71#ibcon#*mode == 0, iclass 30, count 2 2006.258.01:24:54.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.258.01:24:54.71#ibcon#[27=AT06-04\r\n] 2006.258.01:24:54.71#ibcon#*before write, iclass 30, count 2 2006.258.01:24:54.71#ibcon#enter sib2, iclass 30, count 2 2006.258.01:24:54.71#ibcon#flushed, iclass 30, count 2 2006.258.01:24:54.71#ibcon#about to write, iclass 30, count 2 2006.258.01:24:54.71#ibcon#wrote, iclass 30, count 2 2006.258.01:24:54.71#ibcon#about to read 3, iclass 30, count 2 2006.258.01:24:54.74#ibcon#read 3, iclass 30, count 2 2006.258.01:24:54.74#ibcon#about to read 4, iclass 30, count 2 2006.258.01:24:54.74#ibcon#read 4, iclass 30, count 2 2006.258.01:24:54.74#ibcon#about to read 5, iclass 30, count 2 2006.258.01:24:54.74#ibcon#read 5, iclass 30, count 2 2006.258.01:24:54.74#ibcon#about to read 6, iclass 30, count 2 2006.258.01:24:54.74#ibcon#read 6, iclass 30, count 2 2006.258.01:24:54.74#ibcon#end of sib2, iclass 30, count 2 2006.258.01:24:54.74#ibcon#*after write, iclass 30, count 2 2006.258.01:24:54.74#ibcon#*before return 0, iclass 30, count 2 2006.258.01:24:54.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:54.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.258.01:24:54.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.258.01:24:54.74#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:54.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:54.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:54.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:54.86#ibcon#enter wrdev, iclass 30, count 0 2006.258.01:24:54.86#ibcon#first serial, iclass 30, count 0 2006.258.01:24:54.86#ibcon#enter sib2, iclass 30, count 0 2006.258.01:24:54.86#ibcon#flushed, iclass 30, count 0 2006.258.01:24:54.86#ibcon#about to write, iclass 30, count 0 2006.258.01:24:54.86#ibcon#wrote, iclass 30, count 0 2006.258.01:24:54.86#ibcon#about to read 3, iclass 30, count 0 2006.258.01:24:54.88#ibcon#read 3, iclass 30, count 0 2006.258.01:24:54.88#ibcon#about to read 4, iclass 30, count 0 2006.258.01:24:54.88#ibcon#read 4, iclass 30, count 0 2006.258.01:24:54.88#ibcon#about to read 5, iclass 30, count 0 2006.258.01:24:54.88#ibcon#read 5, iclass 30, count 0 2006.258.01:24:54.88#ibcon#about to read 6, iclass 30, count 0 2006.258.01:24:54.88#ibcon#read 6, iclass 30, count 0 2006.258.01:24:54.88#ibcon#end of sib2, iclass 30, count 0 2006.258.01:24:54.88#ibcon#*mode == 0, iclass 30, count 0 2006.258.01:24:54.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.01:24:54.88#ibcon#[27=USB\r\n] 2006.258.01:24:54.88#ibcon#*before write, iclass 30, count 0 2006.258.01:24:54.88#ibcon#enter sib2, iclass 30, count 0 2006.258.01:24:54.88#ibcon#flushed, iclass 30, count 0 2006.258.01:24:54.88#ibcon#about to write, iclass 30, count 0 2006.258.01:24:54.88#ibcon#wrote, iclass 30, count 0 2006.258.01:24:54.88#ibcon#about to read 3, iclass 30, count 0 2006.258.01:24:54.91#ibcon#read 3, iclass 30, count 0 2006.258.01:24:54.91#ibcon#about to read 4, iclass 30, count 0 2006.258.01:24:54.91#ibcon#read 4, iclass 30, count 0 2006.258.01:24:54.91#ibcon#about to read 5, iclass 30, count 0 2006.258.01:24:54.91#ibcon#read 5, iclass 30, count 0 2006.258.01:24:54.91#ibcon#about to read 6, iclass 30, count 0 2006.258.01:24:54.91#ibcon#read 6, iclass 30, count 0 2006.258.01:24:54.91#ibcon#end of sib2, iclass 30, count 0 2006.258.01:24:54.91#ibcon#*after write, iclass 30, count 0 2006.258.01:24:54.91#ibcon#*before return 0, iclass 30, count 0 2006.258.01:24:54.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:54.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.258.01:24:54.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.01:24:54.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.01:24:54.91$vck44/vblo=7,734.99 2006.258.01:24:54.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.258.01:24:54.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.258.01:24:54.91#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:54.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:54.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:54.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:54.91#ibcon#enter wrdev, iclass 32, count 0 2006.258.01:24:54.91#ibcon#first serial, iclass 32, count 0 2006.258.01:24:54.91#ibcon#enter sib2, iclass 32, count 0 2006.258.01:24:54.91#ibcon#flushed, iclass 32, count 0 2006.258.01:24:54.91#ibcon#about to write, iclass 32, count 0 2006.258.01:24:54.91#ibcon#wrote, iclass 32, count 0 2006.258.01:24:54.91#ibcon#about to read 3, iclass 32, count 0 2006.258.01:24:54.93#ibcon#read 3, iclass 32, count 0 2006.258.01:24:54.93#ibcon#about to read 4, iclass 32, count 0 2006.258.01:24:54.93#ibcon#read 4, iclass 32, count 0 2006.258.01:24:54.93#ibcon#about to read 5, iclass 32, count 0 2006.258.01:24:54.93#ibcon#read 5, iclass 32, count 0 2006.258.01:24:54.93#ibcon#about to read 6, iclass 32, count 0 2006.258.01:24:54.93#ibcon#read 6, iclass 32, count 0 2006.258.01:24:54.93#ibcon#end of sib2, iclass 32, count 0 2006.258.01:24:54.93#ibcon#*mode == 0, iclass 32, count 0 2006.258.01:24:54.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.01:24:54.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.01:24:54.93#ibcon#*before write, iclass 32, count 0 2006.258.01:24:54.93#ibcon#enter sib2, iclass 32, count 0 2006.258.01:24:54.93#ibcon#flushed, iclass 32, count 0 2006.258.01:24:54.93#ibcon#about to write, iclass 32, count 0 2006.258.01:24:54.93#ibcon#wrote, iclass 32, count 0 2006.258.01:24:54.93#ibcon#about to read 3, iclass 32, count 0 2006.258.01:24:54.97#ibcon#read 3, iclass 32, count 0 2006.258.01:24:54.97#ibcon#about to read 4, iclass 32, count 0 2006.258.01:24:54.97#ibcon#read 4, iclass 32, count 0 2006.258.01:24:54.97#ibcon#about to read 5, iclass 32, count 0 2006.258.01:24:54.97#ibcon#read 5, iclass 32, count 0 2006.258.01:24:54.97#ibcon#about to read 6, iclass 32, count 0 2006.258.01:24:54.97#ibcon#read 6, iclass 32, count 0 2006.258.01:24:54.97#ibcon#end of sib2, iclass 32, count 0 2006.258.01:24:54.97#ibcon#*after write, iclass 32, count 0 2006.258.01:24:54.97#ibcon#*before return 0, iclass 32, count 0 2006.258.01:24:54.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:54.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.258.01:24:54.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.01:24:54.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.01:24:54.97$vck44/vb=7,4 2006.258.01:24:54.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.258.01:24:54.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.258.01:24:54.97#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:54.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:55.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:55.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:55.03#ibcon#enter wrdev, iclass 34, count 2 2006.258.01:24:55.03#ibcon#first serial, iclass 34, count 2 2006.258.01:24:55.03#ibcon#enter sib2, iclass 34, count 2 2006.258.01:24:55.03#ibcon#flushed, iclass 34, count 2 2006.258.01:24:55.03#ibcon#about to write, iclass 34, count 2 2006.258.01:24:55.03#ibcon#wrote, iclass 34, count 2 2006.258.01:24:55.03#ibcon#about to read 3, iclass 34, count 2 2006.258.01:24:55.05#ibcon#read 3, iclass 34, count 2 2006.258.01:24:55.05#ibcon#about to read 4, iclass 34, count 2 2006.258.01:24:55.05#ibcon#read 4, iclass 34, count 2 2006.258.01:24:55.05#ibcon#about to read 5, iclass 34, count 2 2006.258.01:24:55.05#ibcon#read 5, iclass 34, count 2 2006.258.01:24:55.05#ibcon#about to read 6, iclass 34, count 2 2006.258.01:24:55.05#ibcon#read 6, iclass 34, count 2 2006.258.01:24:55.05#ibcon#end of sib2, iclass 34, count 2 2006.258.01:24:55.05#ibcon#*mode == 0, iclass 34, count 2 2006.258.01:24:55.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.258.01:24:55.05#ibcon#[27=AT07-04\r\n] 2006.258.01:24:55.05#ibcon#*before write, iclass 34, count 2 2006.258.01:24:55.05#ibcon#enter sib2, iclass 34, count 2 2006.258.01:24:55.05#ibcon#flushed, iclass 34, count 2 2006.258.01:24:55.05#ibcon#about to write, iclass 34, count 2 2006.258.01:24:55.05#ibcon#wrote, iclass 34, count 2 2006.258.01:24:55.05#ibcon#about to read 3, iclass 34, count 2 2006.258.01:24:55.08#ibcon#read 3, iclass 34, count 2 2006.258.01:24:55.08#ibcon#about to read 4, iclass 34, count 2 2006.258.01:24:55.08#ibcon#read 4, iclass 34, count 2 2006.258.01:24:55.08#ibcon#about to read 5, iclass 34, count 2 2006.258.01:24:55.08#ibcon#read 5, iclass 34, count 2 2006.258.01:24:55.08#ibcon#about to read 6, iclass 34, count 2 2006.258.01:24:55.08#ibcon#read 6, iclass 34, count 2 2006.258.01:24:55.08#ibcon#end of sib2, iclass 34, count 2 2006.258.01:24:55.08#ibcon#*after write, iclass 34, count 2 2006.258.01:24:55.08#ibcon#*before return 0, iclass 34, count 2 2006.258.01:24:55.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:55.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.258.01:24:55.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.258.01:24:55.08#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:55.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:55.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:55.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:55.20#ibcon#enter wrdev, iclass 34, count 0 2006.258.01:24:55.20#ibcon#first serial, iclass 34, count 0 2006.258.01:24:55.20#ibcon#enter sib2, iclass 34, count 0 2006.258.01:24:55.20#ibcon#flushed, iclass 34, count 0 2006.258.01:24:55.20#ibcon#about to write, iclass 34, count 0 2006.258.01:24:55.20#ibcon#wrote, iclass 34, count 0 2006.258.01:24:55.20#ibcon#about to read 3, iclass 34, count 0 2006.258.01:24:55.22#ibcon#read 3, iclass 34, count 0 2006.258.01:24:55.22#ibcon#about to read 4, iclass 34, count 0 2006.258.01:24:55.22#ibcon#read 4, iclass 34, count 0 2006.258.01:24:55.22#ibcon#about to read 5, iclass 34, count 0 2006.258.01:24:55.22#ibcon#read 5, iclass 34, count 0 2006.258.01:24:55.22#ibcon#about to read 6, iclass 34, count 0 2006.258.01:24:55.22#ibcon#read 6, iclass 34, count 0 2006.258.01:24:55.22#ibcon#end of sib2, iclass 34, count 0 2006.258.01:24:55.22#ibcon#*mode == 0, iclass 34, count 0 2006.258.01:24:55.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.01:24:55.22#ibcon#[27=USB\r\n] 2006.258.01:24:55.22#ibcon#*before write, iclass 34, count 0 2006.258.01:24:55.22#ibcon#enter sib2, iclass 34, count 0 2006.258.01:24:55.22#ibcon#flushed, iclass 34, count 0 2006.258.01:24:55.22#ibcon#about to write, iclass 34, count 0 2006.258.01:24:55.22#ibcon#wrote, iclass 34, count 0 2006.258.01:24:55.22#ibcon#about to read 3, iclass 34, count 0 2006.258.01:24:55.25#ibcon#read 3, iclass 34, count 0 2006.258.01:24:55.25#ibcon#about to read 4, iclass 34, count 0 2006.258.01:24:55.25#ibcon#read 4, iclass 34, count 0 2006.258.01:24:55.25#ibcon#about to read 5, iclass 34, count 0 2006.258.01:24:55.25#ibcon#read 5, iclass 34, count 0 2006.258.01:24:55.25#ibcon#about to read 6, iclass 34, count 0 2006.258.01:24:55.25#ibcon#read 6, iclass 34, count 0 2006.258.01:24:55.25#ibcon#end of sib2, iclass 34, count 0 2006.258.01:24:55.25#ibcon#*after write, iclass 34, count 0 2006.258.01:24:55.25#ibcon#*before return 0, iclass 34, count 0 2006.258.01:24:55.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:55.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.258.01:24:55.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.01:24:55.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.01:24:55.25$vck44/vblo=8,744.99 2006.258.01:24:55.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.258.01:24:55.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.258.01:24:55.25#ibcon#ireg 17 cls_cnt 0 2006.258.01:24:55.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:55.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:55.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:55.25#ibcon#enter wrdev, iclass 36, count 0 2006.258.01:24:55.25#ibcon#first serial, iclass 36, count 0 2006.258.01:24:55.25#ibcon#enter sib2, iclass 36, count 0 2006.258.01:24:55.25#ibcon#flushed, iclass 36, count 0 2006.258.01:24:55.25#ibcon#about to write, iclass 36, count 0 2006.258.01:24:55.25#ibcon#wrote, iclass 36, count 0 2006.258.01:24:55.25#ibcon#about to read 3, iclass 36, count 0 2006.258.01:24:55.27#ibcon#read 3, iclass 36, count 0 2006.258.01:24:55.27#ibcon#about to read 4, iclass 36, count 0 2006.258.01:24:55.27#ibcon#read 4, iclass 36, count 0 2006.258.01:24:55.27#ibcon#about to read 5, iclass 36, count 0 2006.258.01:24:55.27#ibcon#read 5, iclass 36, count 0 2006.258.01:24:55.27#ibcon#about to read 6, iclass 36, count 0 2006.258.01:24:55.27#ibcon#read 6, iclass 36, count 0 2006.258.01:24:55.27#ibcon#end of sib2, iclass 36, count 0 2006.258.01:24:55.27#ibcon#*mode == 0, iclass 36, count 0 2006.258.01:24:55.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.01:24:55.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.01:24:55.27#ibcon#*before write, iclass 36, count 0 2006.258.01:24:55.27#ibcon#enter sib2, iclass 36, count 0 2006.258.01:24:55.27#ibcon#flushed, iclass 36, count 0 2006.258.01:24:55.27#ibcon#about to write, iclass 36, count 0 2006.258.01:24:55.27#ibcon#wrote, iclass 36, count 0 2006.258.01:24:55.27#ibcon#about to read 3, iclass 36, count 0 2006.258.01:24:55.31#ibcon#read 3, iclass 36, count 0 2006.258.01:24:55.31#ibcon#about to read 4, iclass 36, count 0 2006.258.01:24:55.31#ibcon#read 4, iclass 36, count 0 2006.258.01:24:55.31#ibcon#about to read 5, iclass 36, count 0 2006.258.01:24:55.31#ibcon#read 5, iclass 36, count 0 2006.258.01:24:55.31#ibcon#about to read 6, iclass 36, count 0 2006.258.01:24:55.31#ibcon#read 6, iclass 36, count 0 2006.258.01:24:55.31#ibcon#end of sib2, iclass 36, count 0 2006.258.01:24:55.31#ibcon#*after write, iclass 36, count 0 2006.258.01:24:55.31#ibcon#*before return 0, iclass 36, count 0 2006.258.01:24:55.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:55.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.258.01:24:55.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.01:24:55.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.01:24:55.31$vck44/vb=8,4 2006.258.01:24:55.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.258.01:24:55.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.258.01:24:55.31#ibcon#ireg 11 cls_cnt 2 2006.258.01:24:55.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:55.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:55.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:55.37#ibcon#enter wrdev, iclass 38, count 2 2006.258.01:24:55.37#ibcon#first serial, iclass 38, count 2 2006.258.01:24:55.37#ibcon#enter sib2, iclass 38, count 2 2006.258.01:24:55.37#ibcon#flushed, iclass 38, count 2 2006.258.01:24:55.37#ibcon#about to write, iclass 38, count 2 2006.258.01:24:55.37#ibcon#wrote, iclass 38, count 2 2006.258.01:24:55.37#ibcon#about to read 3, iclass 38, count 2 2006.258.01:24:55.39#ibcon#read 3, iclass 38, count 2 2006.258.01:24:55.39#ibcon#about to read 4, iclass 38, count 2 2006.258.01:24:55.39#ibcon#read 4, iclass 38, count 2 2006.258.01:24:55.39#ibcon#about to read 5, iclass 38, count 2 2006.258.01:24:55.39#ibcon#read 5, iclass 38, count 2 2006.258.01:24:55.39#ibcon#about to read 6, iclass 38, count 2 2006.258.01:24:55.39#ibcon#read 6, iclass 38, count 2 2006.258.01:24:55.39#ibcon#end of sib2, iclass 38, count 2 2006.258.01:24:55.39#ibcon#*mode == 0, iclass 38, count 2 2006.258.01:24:55.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.258.01:24:55.39#ibcon#[27=AT08-04\r\n] 2006.258.01:24:55.39#ibcon#*before write, iclass 38, count 2 2006.258.01:24:55.39#ibcon#enter sib2, iclass 38, count 2 2006.258.01:24:55.39#ibcon#flushed, iclass 38, count 2 2006.258.01:24:55.39#ibcon#about to write, iclass 38, count 2 2006.258.01:24:55.39#ibcon#wrote, iclass 38, count 2 2006.258.01:24:55.39#ibcon#about to read 3, iclass 38, count 2 2006.258.01:24:55.42#ibcon#read 3, iclass 38, count 2 2006.258.01:24:55.42#ibcon#about to read 4, iclass 38, count 2 2006.258.01:24:55.42#ibcon#read 4, iclass 38, count 2 2006.258.01:24:55.42#ibcon#about to read 5, iclass 38, count 2 2006.258.01:24:55.42#ibcon#read 5, iclass 38, count 2 2006.258.01:24:55.42#ibcon#about to read 6, iclass 38, count 2 2006.258.01:24:55.42#ibcon#read 6, iclass 38, count 2 2006.258.01:24:55.42#ibcon#end of sib2, iclass 38, count 2 2006.258.01:24:55.42#ibcon#*after write, iclass 38, count 2 2006.258.01:24:55.44#ibcon#*before return 0, iclass 38, count 2 2006.258.01:24:55.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:55.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.258.01:24:55.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.258.01:24:55.45#ibcon#ireg 7 cls_cnt 0 2006.258.01:24:55.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:55.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:55.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:55.56#ibcon#enter wrdev, iclass 38, count 0 2006.258.01:24:55.56#ibcon#first serial, iclass 38, count 0 2006.258.01:24:55.56#ibcon#enter sib2, iclass 38, count 0 2006.258.01:24:55.56#ibcon#flushed, iclass 38, count 0 2006.258.01:24:55.56#ibcon#about to write, iclass 38, count 0 2006.258.01:24:55.56#ibcon#wrote, iclass 38, count 0 2006.258.01:24:55.56#ibcon#about to read 3, iclass 38, count 0 2006.258.01:24:55.58#ibcon#read 3, iclass 38, count 0 2006.258.01:24:55.58#ibcon#about to read 4, iclass 38, count 0 2006.258.01:24:55.58#ibcon#read 4, iclass 38, count 0 2006.258.01:24:55.58#ibcon#about to read 5, iclass 38, count 0 2006.258.01:24:55.58#ibcon#read 5, iclass 38, count 0 2006.258.01:24:55.58#ibcon#about to read 6, iclass 38, count 0 2006.258.01:24:55.58#ibcon#read 6, iclass 38, count 0 2006.258.01:24:55.58#ibcon#end of sib2, iclass 38, count 0 2006.258.01:24:55.58#ibcon#*mode == 0, iclass 38, count 0 2006.258.01:24:55.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.01:24:55.58#ibcon#[27=USB\r\n] 2006.258.01:24:55.58#ibcon#*before write, iclass 38, count 0 2006.258.01:24:55.58#ibcon#enter sib2, iclass 38, count 0 2006.258.01:24:55.58#ibcon#flushed, iclass 38, count 0 2006.258.01:24:55.58#ibcon#about to write, iclass 38, count 0 2006.258.01:24:55.58#ibcon#wrote, iclass 38, count 0 2006.258.01:24:55.58#ibcon#about to read 3, iclass 38, count 0 2006.258.01:24:55.61#ibcon#read 3, iclass 38, count 0 2006.258.01:24:55.61#ibcon#about to read 4, iclass 38, count 0 2006.258.01:24:55.61#ibcon#read 4, iclass 38, count 0 2006.258.01:24:55.61#ibcon#about to read 5, iclass 38, count 0 2006.258.01:24:55.61#ibcon#read 5, iclass 38, count 0 2006.258.01:24:55.61#ibcon#about to read 6, iclass 38, count 0 2006.258.01:24:55.61#ibcon#read 6, iclass 38, count 0 2006.258.01:24:55.61#ibcon#end of sib2, iclass 38, count 0 2006.258.01:24:55.61#ibcon#*after write, iclass 38, count 0 2006.258.01:24:55.61#ibcon#*before return 0, iclass 38, count 0 2006.258.01:24:55.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:55.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.258.01:24:55.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.01:24:55.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.01:24:55.61$vck44/vabw=wide 2006.258.01:24:55.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.258.01:24:55.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.258.01:24:55.61#ibcon#ireg 8 cls_cnt 0 2006.258.01:24:55.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:55.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:55.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:55.61#ibcon#enter wrdev, iclass 40, count 0 2006.258.01:24:55.61#ibcon#first serial, iclass 40, count 0 2006.258.01:24:55.61#ibcon#enter sib2, iclass 40, count 0 2006.258.01:24:55.61#ibcon#flushed, iclass 40, count 0 2006.258.01:24:55.61#ibcon#about to write, iclass 40, count 0 2006.258.01:24:55.61#ibcon#wrote, iclass 40, count 0 2006.258.01:24:55.61#ibcon#about to read 3, iclass 40, count 0 2006.258.01:24:55.63#ibcon#read 3, iclass 40, count 0 2006.258.01:24:55.63#ibcon#about to read 4, iclass 40, count 0 2006.258.01:24:55.63#ibcon#read 4, iclass 40, count 0 2006.258.01:24:55.63#ibcon#about to read 5, iclass 40, count 0 2006.258.01:24:55.63#ibcon#read 5, iclass 40, count 0 2006.258.01:24:55.63#ibcon#about to read 6, iclass 40, count 0 2006.258.01:24:55.63#ibcon#read 6, iclass 40, count 0 2006.258.01:24:55.63#ibcon#end of sib2, iclass 40, count 0 2006.258.01:24:55.63#ibcon#*mode == 0, iclass 40, count 0 2006.258.01:24:55.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.01:24:55.63#ibcon#[25=BW32\r\n] 2006.258.01:24:55.63#ibcon#*before write, iclass 40, count 0 2006.258.01:24:55.63#ibcon#enter sib2, iclass 40, count 0 2006.258.01:24:55.63#ibcon#flushed, iclass 40, count 0 2006.258.01:24:55.63#ibcon#about to write, iclass 40, count 0 2006.258.01:24:55.63#ibcon#wrote, iclass 40, count 0 2006.258.01:24:55.63#ibcon#about to read 3, iclass 40, count 0 2006.258.01:24:55.66#ibcon#read 3, iclass 40, count 0 2006.258.01:24:55.66#ibcon#about to read 4, iclass 40, count 0 2006.258.01:24:55.66#ibcon#read 4, iclass 40, count 0 2006.258.01:24:55.66#ibcon#about to read 5, iclass 40, count 0 2006.258.01:24:55.66#ibcon#read 5, iclass 40, count 0 2006.258.01:24:55.66#ibcon#about to read 6, iclass 40, count 0 2006.258.01:24:55.66#ibcon#read 6, iclass 40, count 0 2006.258.01:24:55.66#ibcon#end of sib2, iclass 40, count 0 2006.258.01:24:55.66#ibcon#*after write, iclass 40, count 0 2006.258.01:24:55.66#ibcon#*before return 0, iclass 40, count 0 2006.258.01:24:55.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:55.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.258.01:24:55.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.01:24:55.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.01:24:55.66$vck44/vbbw=wide 2006.258.01:24:55.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.258.01:24:55.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.258.01:24:55.66#ibcon#ireg 8 cls_cnt 0 2006.258.01:24:55.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:24:55.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:24:55.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:24:55.73#ibcon#enter wrdev, iclass 4, count 0 2006.258.01:24:55.73#ibcon#first serial, iclass 4, count 0 2006.258.01:24:55.73#ibcon#enter sib2, iclass 4, count 0 2006.258.01:24:55.73#ibcon#flushed, iclass 4, count 0 2006.258.01:24:55.73#ibcon#about to write, iclass 4, count 0 2006.258.01:24:55.73#ibcon#wrote, iclass 4, count 0 2006.258.01:24:55.73#ibcon#about to read 3, iclass 4, count 0 2006.258.01:24:55.75#ibcon#read 3, iclass 4, count 0 2006.258.01:24:55.75#ibcon#about to read 4, iclass 4, count 0 2006.258.01:24:55.75#ibcon#read 4, iclass 4, count 0 2006.258.01:24:55.75#ibcon#about to read 5, iclass 4, count 0 2006.258.01:24:55.75#ibcon#read 5, iclass 4, count 0 2006.258.01:24:55.75#ibcon#about to read 6, iclass 4, count 0 2006.258.01:24:55.75#ibcon#read 6, iclass 4, count 0 2006.258.01:24:55.75#ibcon#end of sib2, iclass 4, count 0 2006.258.01:24:55.75#ibcon#*mode == 0, iclass 4, count 0 2006.258.01:24:55.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.01:24:55.75#ibcon#[27=BW32\r\n] 2006.258.01:24:55.75#ibcon#*before write, iclass 4, count 0 2006.258.01:24:55.75#ibcon#enter sib2, iclass 4, count 0 2006.258.01:24:55.75#ibcon#flushed, iclass 4, count 0 2006.258.01:24:55.75#ibcon#about to write, iclass 4, count 0 2006.258.01:24:55.75#ibcon#wrote, iclass 4, count 0 2006.258.01:24:55.75#ibcon#about to read 3, iclass 4, count 0 2006.258.01:24:55.78#ibcon#read 3, iclass 4, count 0 2006.258.01:24:55.78#ibcon#about to read 4, iclass 4, count 0 2006.258.01:24:55.78#ibcon#read 4, iclass 4, count 0 2006.258.01:24:55.78#ibcon#about to read 5, iclass 4, count 0 2006.258.01:24:55.78#ibcon#read 5, iclass 4, count 0 2006.258.01:24:55.78#ibcon#about to read 6, iclass 4, count 0 2006.258.01:24:55.78#ibcon#read 6, iclass 4, count 0 2006.258.01:24:55.78#ibcon#end of sib2, iclass 4, count 0 2006.258.01:24:55.78#ibcon#*after write, iclass 4, count 0 2006.258.01:24:55.78#ibcon#*before return 0, iclass 4, count 0 2006.258.01:24:55.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:24:55.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:24:55.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.01:24:55.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.01:24:55.78$setupk4/ifdk4 2006.258.01:24:55.78$ifdk4/lo= 2006.258.01:24:55.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.01:24:55.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.01:24:55.78$ifdk4/patch= 2006.258.01:24:55.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.01:24:55.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.01:24:55.78$setupk4/!*+20s 2006.258.01:24:57.43#abcon#<5=/04 3.4 6.4 23.16 741016.0\r\n> 2006.258.01:24:57.45#abcon#{5=INTERFACE CLEAR} 2006.258.01:24:57.51#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:25:07.60#abcon#<5=/04 3.3 6.5 23.16 751016.0\r\n> 2006.258.01:25:07.62#abcon#{5=INTERFACE CLEAR} 2006.258.01:25:07.68#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:25:10.28$setupk4/"tpicd 2006.258.01:25:10.28$setupk4/echo=off 2006.258.01:25:10.28$setupk4/xlog=off 2006.258.01:25:10.28:!2006.258.01:27:00 2006.258.01:25:18.14#trakl#Source acquired 2006.258.01:25:18.14#flagr#flagr/antenna,acquired 2006.258.01:27:00.00:preob 2006.258.01:27:01.14/onsource/TRACKING 2006.258.01:27:01.14:!2006.258.01:27:10 2006.258.01:27:10.00:"tape 2006.258.01:27:10.00:"st=record 2006.258.01:27:10.00:data_valid=on 2006.258.01:27:10.00:midob 2006.258.01:27:10.14/onsource/TRACKING 2006.258.01:27:10.14/wx/23.18,1016.1,73 2006.258.01:27:10.36/cable/+6.4746E-03 2006.258.01:27:11.45/va/01,08,usb,yes,32,34 2006.258.01:27:11.45/va/02,07,usb,yes,34,35 2006.258.01:27:11.45/va/03,08,usb,yes,31,33 2006.258.01:27:11.45/va/04,07,usb,yes,35,37 2006.258.01:27:11.45/va/05,04,usb,yes,32,32 2006.258.01:27:11.45/va/06,04,usb,yes,35,35 2006.258.01:27:11.45/va/07,04,usb,yes,36,37 2006.258.01:27:11.45/va/08,04,usb,yes,30,37 2006.258.01:27:11.68/valo/01,524.99,yes,locked 2006.258.01:27:11.68/valo/02,534.99,yes,locked 2006.258.01:27:11.68/valo/03,564.99,yes,locked 2006.258.01:27:11.68/valo/04,624.99,yes,locked 2006.258.01:27:11.68/valo/05,734.99,yes,locked 2006.258.01:27:11.68/valo/06,814.99,yes,locked 2006.258.01:27:11.68/valo/07,864.99,yes,locked 2006.258.01:27:11.68/valo/08,884.99,yes,locked 2006.258.01:27:12.77/vb/01,04,usb,yes,31,29 2006.258.01:27:12.77/vb/02,05,usb,yes,29,29 2006.258.01:27:12.77/vb/03,04,usb,yes,30,33 2006.258.01:27:12.77/vb/04,05,usb,yes,31,30 2006.258.01:27:12.77/vb/05,04,usb,yes,27,30 2006.258.01:27:12.77/vb/06,04,usb,yes,32,28 2006.258.01:27:12.77/vb/07,04,usb,yes,32,31 2006.258.01:27:12.77/vb/08,04,usb,yes,29,32 2006.258.01:27:13.01/vblo/01,629.99,yes,locked 2006.258.01:27:13.01/vblo/02,634.99,yes,locked 2006.258.01:27:13.01/vblo/03,649.99,yes,locked 2006.258.01:27:13.01/vblo/04,679.99,yes,locked 2006.258.01:27:13.01/vblo/05,709.99,yes,locked 2006.258.01:27:13.01/vblo/06,719.99,yes,locked 2006.258.01:27:13.01/vblo/07,734.99,yes,locked 2006.258.01:27:13.01/vblo/08,744.99,yes,locked 2006.258.01:27:13.16/vabw/8 2006.258.01:27:13.31/vbbw/8 2006.258.01:27:13.48/xfe/off,on,15.5 2006.258.01:27:13.85/ifatt/23,28,28,28 2006.258.01:27:14.08/fmout-gps/S +4.50E-07 2006.258.01:27:14.12:!2006.258.01:31:20 2006.258.01:30:25.14#trakl#Off source 2006.258.01:30:25.14?ERROR st -7 Antenna off-source! 2006.258.01:30:25.14#trakl#az 128.046 el 23.257 azerr*cos(el) 0.0183 elerr -0.0054 2006.258.01:30:27.14#flagr#flagr/antenna,off-source 2006.258.01:30:31.14#trakl#Source re-acquired 2006.258.01:30:33.14#flagr#flagr/antenna,re-acquired 2006.258.01:31:07.14#trakl#Off source 2006.258.01:31:07.14?ERROR st -7 Antenna off-source! 2006.258.01:31:07.14#trakl#az 128.187 el 23.369 azerr*cos(el) 0.0228 elerr 0.0012 2006.258.01:31:09.14#flagr#flagr/antenna,off-source 2006.258.01:31:14.13#trakl#Source re-acquired 2006.258.01:31:15.13#flagr#flagr/antenna,re-acquired 2006.258.01:31:20.01:data_valid=off 2006.258.01:31:20.01:"et 2006.258.01:31:20.02:!+3s 2006.258.01:31:23.03:"tape 2006.258.01:31:23.03:postob 2006.258.01:31:23.11/cable/+6.4736E-03 2006.258.01:31:23.11/wx/23.16,1016.0,71 2006.258.01:31:23.17/fmout-gps/S +4.49E-07 2006.258.01:31:23.17:scan_name=258-0134,jd0609,80 2006.258.01:31:23.18:source=3c274,123049.42,122328.0,2000.0,cw 2006.258.01:31:25.13#flagr#flagr/antenna,new-source 2006.258.01:31:25.13:checkk5 2006.258.01:31:25.55/chk_autoobs//k5ts1/ autoobs is running! 2006.258.01:31:25.95/chk_autoobs//k5ts2/ autoobs is running! 2006.258.01:31:26.35/chk_autoobs//k5ts3/ autoobs is running! 2006.258.01:31:26.75/chk_autoobs//k5ts4/ autoobs is running! 2006.258.01:31:27.16/chk_obsdata//k5ts1/T2580127??a.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.258.01:31:27.57/chk_obsdata//k5ts2/T2580127??b.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.258.01:31:27.97/chk_obsdata//k5ts3/T2580127??c.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.258.01:31:28.36/chk_obsdata//k5ts4/T2580127??d.dat file size is correct (nominal:1000MB, actual:1000MB). 2006.258.01:31:29.10/k5log//k5ts1_log_newline 2006.258.01:31:29.83/k5log//k5ts2_log_newline 2006.258.01:31:30.55/k5log//k5ts3_log_newline 2006.258.01:31:31.27/k5log//k5ts4_log_newline 2006.258.01:31:31.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:31:31.29:setupk4=1 2006.258.01:31:31.29$setupk4/echo=on 2006.258.01:31:31.29$setupk4/pcalon 2006.258.01:31:31.29$pcalon/"no phase cal control is implemented here 2006.258.01:31:31.29$setupk4/"tpicd=stop 2006.258.01:31:31.29$setupk4/"rec=synch_on 2006.258.01:31:31.29$setupk4/"rec_mode=128 2006.258.01:31:31.29$setupk4/!* 2006.258.01:31:31.29$setupk4/recpk4 2006.258.01:31:31.29$recpk4/recpatch= 2006.258.01:31:31.30$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.01:31:31.30$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.01:31:31.30$setupk4/vck44 2006.258.01:31:31.30$vck44/valo=1,524.99 2006.258.01:31:31.30#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.01:31:31.30#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.01:31:31.30#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:31.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:31:31.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:31:31.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:31:31.30#ibcon#enter wrdev, iclass 27, count 0 2006.258.01:31:31.30#ibcon#first serial, iclass 27, count 0 2006.258.01:31:31.30#ibcon#enter sib2, iclass 27, count 0 2006.258.01:31:31.30#ibcon#flushed, iclass 27, count 0 2006.258.01:31:31.30#ibcon#about to write, iclass 27, count 0 2006.258.01:31:31.30#ibcon#wrote, iclass 27, count 0 2006.258.01:31:31.30#ibcon#about to read 3, iclass 27, count 0 2006.258.01:31:31.31#ibcon#read 3, iclass 27, count 0 2006.258.01:31:31.31#ibcon#about to read 4, iclass 27, count 0 2006.258.01:31:31.31#ibcon#read 4, iclass 27, count 0 2006.258.01:31:31.31#ibcon#about to read 5, iclass 27, count 0 2006.258.01:31:31.31#ibcon#read 5, iclass 27, count 0 2006.258.01:31:31.31#ibcon#about to read 6, iclass 27, count 0 2006.258.01:31:31.31#ibcon#read 6, iclass 27, count 0 2006.258.01:31:31.31#ibcon#end of sib2, iclass 27, count 0 2006.258.01:31:31.31#ibcon#*mode == 0, iclass 27, count 0 2006.258.01:31:31.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.01:31:31.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.01:31:31.31#ibcon#*before write, iclass 27, count 0 2006.258.01:31:31.31#ibcon#enter sib2, iclass 27, count 0 2006.258.01:31:31.31#ibcon#flushed, iclass 27, count 0 2006.258.01:31:31.31#ibcon#about to write, iclass 27, count 0 2006.258.01:31:31.31#ibcon#wrote, iclass 27, count 0 2006.258.01:31:31.31#ibcon#about to read 3, iclass 27, count 0 2006.258.01:31:31.36#ibcon#read 3, iclass 27, count 0 2006.258.01:31:31.36#ibcon#about to read 4, iclass 27, count 0 2006.258.01:31:31.36#ibcon#read 4, iclass 27, count 0 2006.258.01:31:31.36#ibcon#about to read 5, iclass 27, count 0 2006.258.01:31:31.36#ibcon#read 5, iclass 27, count 0 2006.258.01:31:31.36#ibcon#about to read 6, iclass 27, count 0 2006.258.01:31:31.36#ibcon#read 6, iclass 27, count 0 2006.258.01:31:31.36#ibcon#end of sib2, iclass 27, count 0 2006.258.01:31:31.36#ibcon#*after write, iclass 27, count 0 2006.258.01:31:31.36#ibcon#*before return 0, iclass 27, count 0 2006.258.01:31:31.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:31:31.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:31:31.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.01:31:31.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.01:31:31.36$vck44/va=1,8 2006.258.01:31:31.36#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.01:31:31.36#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.01:31:31.36#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:31.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:31:31.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:31:31.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:31:31.36#ibcon#enter wrdev, iclass 29, count 2 2006.258.01:31:31.36#ibcon#first serial, iclass 29, count 2 2006.258.01:31:31.36#ibcon#enter sib2, iclass 29, count 2 2006.258.01:31:31.36#ibcon#flushed, iclass 29, count 2 2006.258.01:31:31.36#ibcon#about to write, iclass 29, count 2 2006.258.01:31:31.36#ibcon#wrote, iclass 29, count 2 2006.258.01:31:31.36#ibcon#about to read 3, iclass 29, count 2 2006.258.01:31:31.38#ibcon#read 3, iclass 29, count 2 2006.258.01:31:31.38#ibcon#about to read 4, iclass 29, count 2 2006.258.01:31:31.38#ibcon#read 4, iclass 29, count 2 2006.258.01:31:31.38#ibcon#about to read 5, iclass 29, count 2 2006.258.01:31:31.38#ibcon#read 5, iclass 29, count 2 2006.258.01:31:31.38#ibcon#about to read 6, iclass 29, count 2 2006.258.01:31:31.38#ibcon#read 6, iclass 29, count 2 2006.258.01:31:31.38#ibcon#end of sib2, iclass 29, count 2 2006.258.01:31:31.38#ibcon#*mode == 0, iclass 29, count 2 2006.258.01:31:31.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.01:31:31.38#ibcon#[25=AT01-08\r\n] 2006.258.01:31:31.38#ibcon#*before write, iclass 29, count 2 2006.258.01:31:31.38#ibcon#enter sib2, iclass 29, count 2 2006.258.01:31:31.38#ibcon#flushed, iclass 29, count 2 2006.258.01:31:31.38#ibcon#about to write, iclass 29, count 2 2006.258.01:31:31.38#ibcon#wrote, iclass 29, count 2 2006.258.01:31:31.38#ibcon#about to read 3, iclass 29, count 2 2006.258.01:31:31.41#ibcon#read 3, iclass 29, count 2 2006.258.01:31:31.41#ibcon#about to read 4, iclass 29, count 2 2006.258.01:31:31.41#ibcon#read 4, iclass 29, count 2 2006.258.01:31:31.41#ibcon#about to read 5, iclass 29, count 2 2006.258.01:31:31.41#ibcon#read 5, iclass 29, count 2 2006.258.01:31:31.41#ibcon#about to read 6, iclass 29, count 2 2006.258.01:31:31.41#ibcon#read 6, iclass 29, count 2 2006.258.01:31:31.41#ibcon#end of sib2, iclass 29, count 2 2006.258.01:31:31.41#ibcon#*after write, iclass 29, count 2 2006.258.01:31:31.41#ibcon#*before return 0, iclass 29, count 2 2006.258.01:31:31.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:31:31.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:31:31.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.01:31:31.41#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:31.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:31:31.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:31:31.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:31:31.53#ibcon#enter wrdev, iclass 29, count 0 2006.258.01:31:31.53#ibcon#first serial, iclass 29, count 0 2006.258.01:31:31.53#ibcon#enter sib2, iclass 29, count 0 2006.258.01:31:31.53#ibcon#flushed, iclass 29, count 0 2006.258.01:31:31.53#ibcon#about to write, iclass 29, count 0 2006.258.01:31:31.53#ibcon#wrote, iclass 29, count 0 2006.258.01:31:31.53#ibcon#about to read 3, iclass 29, count 0 2006.258.01:31:31.55#ibcon#read 3, iclass 29, count 0 2006.258.01:31:31.55#ibcon#about to read 4, iclass 29, count 0 2006.258.01:31:31.55#ibcon#read 4, iclass 29, count 0 2006.258.01:31:31.55#ibcon#about to read 5, iclass 29, count 0 2006.258.01:31:31.55#ibcon#read 5, iclass 29, count 0 2006.258.01:31:31.55#ibcon#about to read 6, iclass 29, count 0 2006.258.01:31:31.55#ibcon#read 6, iclass 29, count 0 2006.258.01:31:31.55#ibcon#end of sib2, iclass 29, count 0 2006.258.01:31:31.55#ibcon#*mode == 0, iclass 29, count 0 2006.258.01:31:31.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.01:31:31.55#ibcon#[25=USB\r\n] 2006.258.01:31:31.55#ibcon#*before write, iclass 29, count 0 2006.258.01:31:31.55#ibcon#enter sib2, iclass 29, count 0 2006.258.01:31:31.55#ibcon#flushed, iclass 29, count 0 2006.258.01:31:31.55#ibcon#about to write, iclass 29, count 0 2006.258.01:31:31.55#ibcon#wrote, iclass 29, count 0 2006.258.01:31:31.55#ibcon#about to read 3, iclass 29, count 0 2006.258.01:31:31.58#ibcon#read 3, iclass 29, count 0 2006.258.01:31:31.58#ibcon#about to read 4, iclass 29, count 0 2006.258.01:31:31.58#ibcon#read 4, iclass 29, count 0 2006.258.01:31:31.58#ibcon#about to read 5, iclass 29, count 0 2006.258.01:31:31.58#ibcon#read 5, iclass 29, count 0 2006.258.01:31:31.58#ibcon#about to read 6, iclass 29, count 0 2006.258.01:31:31.58#ibcon#read 6, iclass 29, count 0 2006.258.01:31:31.58#ibcon#end of sib2, iclass 29, count 0 2006.258.01:31:31.58#ibcon#*after write, iclass 29, count 0 2006.258.01:31:31.58#ibcon#*before return 0, iclass 29, count 0 2006.258.01:31:31.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:31:31.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:31:31.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.01:31:31.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.01:31:31.58$vck44/valo=2,534.99 2006.258.01:31:31.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.258.01:31:31.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.258.01:31:31.58#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:31.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:31.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:31.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:31.58#ibcon#enter wrdev, iclass 31, count 0 2006.258.01:31:31.58#ibcon#first serial, iclass 31, count 0 2006.258.01:31:31.58#ibcon#enter sib2, iclass 31, count 0 2006.258.01:31:31.58#ibcon#flushed, iclass 31, count 0 2006.258.01:31:31.58#ibcon#about to write, iclass 31, count 0 2006.258.01:31:31.58#ibcon#wrote, iclass 31, count 0 2006.258.01:31:31.58#ibcon#about to read 3, iclass 31, count 0 2006.258.01:31:31.60#ibcon#read 3, iclass 31, count 0 2006.258.01:31:31.60#ibcon#about to read 4, iclass 31, count 0 2006.258.01:31:31.60#ibcon#read 4, iclass 31, count 0 2006.258.01:31:31.60#ibcon#about to read 5, iclass 31, count 0 2006.258.01:31:31.60#ibcon#read 5, iclass 31, count 0 2006.258.01:31:31.60#ibcon#about to read 6, iclass 31, count 0 2006.258.01:31:31.60#ibcon#read 6, iclass 31, count 0 2006.258.01:31:31.60#ibcon#end of sib2, iclass 31, count 0 2006.258.01:31:31.60#ibcon#*mode == 0, iclass 31, count 0 2006.258.01:31:31.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.01:31:31.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.01:31:31.60#ibcon#*before write, iclass 31, count 0 2006.258.01:31:31.60#ibcon#enter sib2, iclass 31, count 0 2006.258.01:31:31.60#ibcon#flushed, iclass 31, count 0 2006.258.01:31:31.60#ibcon#about to write, iclass 31, count 0 2006.258.01:31:31.60#ibcon#wrote, iclass 31, count 0 2006.258.01:31:31.60#ibcon#about to read 3, iclass 31, count 0 2006.258.01:31:31.64#ibcon#read 3, iclass 31, count 0 2006.258.01:31:31.64#ibcon#about to read 4, iclass 31, count 0 2006.258.01:31:31.64#ibcon#read 4, iclass 31, count 0 2006.258.01:31:31.64#ibcon#about to read 5, iclass 31, count 0 2006.258.01:31:31.64#ibcon#read 5, iclass 31, count 0 2006.258.01:31:31.64#ibcon#about to read 6, iclass 31, count 0 2006.258.01:31:31.64#ibcon#read 6, iclass 31, count 0 2006.258.01:31:31.64#ibcon#end of sib2, iclass 31, count 0 2006.258.01:31:31.64#ibcon#*after write, iclass 31, count 0 2006.258.01:31:31.64#ibcon#*before return 0, iclass 31, count 0 2006.258.01:31:31.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:31.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:31.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.01:31:31.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.01:31:31.64$vck44/va=2,7 2006.258.01:31:31.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.01:31:31.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.01:31:31.64#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:31.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:31.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:31.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:31.70#ibcon#enter wrdev, iclass 33, count 2 2006.258.01:31:31.70#ibcon#first serial, iclass 33, count 2 2006.258.01:31:31.70#ibcon#enter sib2, iclass 33, count 2 2006.258.01:31:31.70#ibcon#flushed, iclass 33, count 2 2006.258.01:31:31.70#ibcon#about to write, iclass 33, count 2 2006.258.01:31:31.70#ibcon#wrote, iclass 33, count 2 2006.258.01:31:31.70#ibcon#about to read 3, iclass 33, count 2 2006.258.01:31:31.72#ibcon#read 3, iclass 33, count 2 2006.258.01:31:31.72#ibcon#about to read 4, iclass 33, count 2 2006.258.01:31:31.72#ibcon#read 4, iclass 33, count 2 2006.258.01:31:31.72#ibcon#about to read 5, iclass 33, count 2 2006.258.01:31:31.72#ibcon#read 5, iclass 33, count 2 2006.258.01:31:31.72#ibcon#about to read 6, iclass 33, count 2 2006.258.01:31:31.72#ibcon#read 6, iclass 33, count 2 2006.258.01:31:31.72#ibcon#end of sib2, iclass 33, count 2 2006.258.01:31:31.72#ibcon#*mode == 0, iclass 33, count 2 2006.258.01:31:31.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.01:31:31.72#ibcon#[25=AT02-07\r\n] 2006.258.01:31:31.72#ibcon#*before write, iclass 33, count 2 2006.258.01:31:31.72#ibcon#enter sib2, iclass 33, count 2 2006.258.01:31:31.72#ibcon#flushed, iclass 33, count 2 2006.258.01:31:31.72#ibcon#about to write, iclass 33, count 2 2006.258.01:31:31.72#ibcon#wrote, iclass 33, count 2 2006.258.01:31:31.72#ibcon#about to read 3, iclass 33, count 2 2006.258.01:31:31.75#ibcon#read 3, iclass 33, count 2 2006.258.01:31:31.75#ibcon#about to read 4, iclass 33, count 2 2006.258.01:31:31.75#ibcon#read 4, iclass 33, count 2 2006.258.01:31:31.75#ibcon#about to read 5, iclass 33, count 2 2006.258.01:31:31.75#ibcon#read 5, iclass 33, count 2 2006.258.01:31:31.75#ibcon#about to read 6, iclass 33, count 2 2006.258.01:31:31.75#ibcon#read 6, iclass 33, count 2 2006.258.01:31:31.75#ibcon#end of sib2, iclass 33, count 2 2006.258.01:31:31.75#ibcon#*after write, iclass 33, count 2 2006.258.01:31:31.75#ibcon#*before return 0, iclass 33, count 2 2006.258.01:31:31.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:31.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:31.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.01:31:31.75#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:31.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:31.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:31.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:31.87#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:31:31.87#ibcon#first serial, iclass 33, count 0 2006.258.01:31:31.87#ibcon#enter sib2, iclass 33, count 0 2006.258.01:31:31.87#ibcon#flushed, iclass 33, count 0 2006.258.01:31:31.87#ibcon#about to write, iclass 33, count 0 2006.258.01:31:31.87#ibcon#wrote, iclass 33, count 0 2006.258.01:31:31.87#ibcon#about to read 3, iclass 33, count 0 2006.258.01:31:31.89#ibcon#read 3, iclass 33, count 0 2006.258.01:31:31.89#ibcon#about to read 4, iclass 33, count 0 2006.258.01:31:31.89#ibcon#read 4, iclass 33, count 0 2006.258.01:31:31.89#ibcon#about to read 5, iclass 33, count 0 2006.258.01:31:31.89#ibcon#read 5, iclass 33, count 0 2006.258.01:31:31.89#ibcon#about to read 6, iclass 33, count 0 2006.258.01:31:31.89#ibcon#read 6, iclass 33, count 0 2006.258.01:31:31.89#ibcon#end of sib2, iclass 33, count 0 2006.258.01:31:31.89#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:31:31.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:31:31.89#ibcon#[25=USB\r\n] 2006.258.01:31:31.89#ibcon#*before write, iclass 33, count 0 2006.258.01:31:31.89#ibcon#enter sib2, iclass 33, count 0 2006.258.01:31:31.89#ibcon#flushed, iclass 33, count 0 2006.258.01:31:31.89#ibcon#about to write, iclass 33, count 0 2006.258.01:31:31.89#ibcon#wrote, iclass 33, count 0 2006.258.01:31:31.89#ibcon#about to read 3, iclass 33, count 0 2006.258.01:31:31.92#ibcon#read 3, iclass 33, count 0 2006.258.01:31:31.92#ibcon#about to read 4, iclass 33, count 0 2006.258.01:31:31.92#ibcon#read 4, iclass 33, count 0 2006.258.01:31:31.92#ibcon#about to read 5, iclass 33, count 0 2006.258.01:31:31.92#ibcon#read 5, iclass 33, count 0 2006.258.01:31:31.92#ibcon#about to read 6, iclass 33, count 0 2006.258.01:31:31.92#ibcon#read 6, iclass 33, count 0 2006.258.01:31:31.92#ibcon#end of sib2, iclass 33, count 0 2006.258.01:31:31.92#ibcon#*after write, iclass 33, count 0 2006.258.01:31:31.92#ibcon#*before return 0, iclass 33, count 0 2006.258.01:31:31.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:31.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:31.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:31:31.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:31:31.92$vck44/valo=3,564.99 2006.258.01:31:31.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.01:31:31.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.01:31:31.92#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:31.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:31.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:31.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:31.92#ibcon#enter wrdev, iclass 35, count 0 2006.258.01:31:31.92#ibcon#first serial, iclass 35, count 0 2006.258.01:31:31.92#ibcon#enter sib2, iclass 35, count 0 2006.258.01:31:31.92#ibcon#flushed, iclass 35, count 0 2006.258.01:31:31.92#ibcon#about to write, iclass 35, count 0 2006.258.01:31:31.92#ibcon#wrote, iclass 35, count 0 2006.258.01:31:31.92#ibcon#about to read 3, iclass 35, count 0 2006.258.01:31:31.94#ibcon#read 3, iclass 35, count 0 2006.258.01:31:31.94#ibcon#about to read 4, iclass 35, count 0 2006.258.01:31:31.94#ibcon#read 4, iclass 35, count 0 2006.258.01:31:31.94#ibcon#about to read 5, iclass 35, count 0 2006.258.01:31:31.94#ibcon#read 5, iclass 35, count 0 2006.258.01:31:31.94#ibcon#about to read 6, iclass 35, count 0 2006.258.01:31:31.94#ibcon#read 6, iclass 35, count 0 2006.258.01:31:31.94#ibcon#end of sib2, iclass 35, count 0 2006.258.01:31:31.94#ibcon#*mode == 0, iclass 35, count 0 2006.258.01:31:31.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.01:31:31.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.01:31:31.94#ibcon#*before write, iclass 35, count 0 2006.258.01:31:31.94#ibcon#enter sib2, iclass 35, count 0 2006.258.01:31:31.94#ibcon#flushed, iclass 35, count 0 2006.258.01:31:31.94#ibcon#about to write, iclass 35, count 0 2006.258.01:31:31.94#ibcon#wrote, iclass 35, count 0 2006.258.01:31:31.94#ibcon#about to read 3, iclass 35, count 0 2006.258.01:31:31.98#ibcon#read 3, iclass 35, count 0 2006.258.01:31:31.98#ibcon#about to read 4, iclass 35, count 0 2006.258.01:31:31.98#ibcon#read 4, iclass 35, count 0 2006.258.01:31:31.98#ibcon#about to read 5, iclass 35, count 0 2006.258.01:31:31.98#ibcon#read 5, iclass 35, count 0 2006.258.01:31:31.98#ibcon#about to read 6, iclass 35, count 0 2006.258.01:31:31.98#ibcon#read 6, iclass 35, count 0 2006.258.01:31:31.98#ibcon#end of sib2, iclass 35, count 0 2006.258.01:31:31.98#ibcon#*after write, iclass 35, count 0 2006.258.01:31:31.98#ibcon#*before return 0, iclass 35, count 0 2006.258.01:31:31.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:31.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:31.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.01:31:31.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.01:31:31.98$vck44/va=3,8 2006.258.01:31:31.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.01:31:31.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.01:31:31.98#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:31.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:32.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:32.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:32.04#ibcon#enter wrdev, iclass 37, count 2 2006.258.01:31:32.04#ibcon#first serial, iclass 37, count 2 2006.258.01:31:32.04#ibcon#enter sib2, iclass 37, count 2 2006.258.01:31:32.04#ibcon#flushed, iclass 37, count 2 2006.258.01:31:32.04#ibcon#about to write, iclass 37, count 2 2006.258.01:31:32.04#ibcon#wrote, iclass 37, count 2 2006.258.01:31:32.04#ibcon#about to read 3, iclass 37, count 2 2006.258.01:31:32.06#ibcon#read 3, iclass 37, count 2 2006.258.01:31:32.06#ibcon#about to read 4, iclass 37, count 2 2006.258.01:31:32.06#ibcon#read 4, iclass 37, count 2 2006.258.01:31:32.06#ibcon#about to read 5, iclass 37, count 2 2006.258.01:31:32.06#ibcon#read 5, iclass 37, count 2 2006.258.01:31:32.06#ibcon#about to read 6, iclass 37, count 2 2006.258.01:31:32.06#ibcon#read 6, iclass 37, count 2 2006.258.01:31:32.06#ibcon#end of sib2, iclass 37, count 2 2006.258.01:31:32.06#ibcon#*mode == 0, iclass 37, count 2 2006.258.01:31:32.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.01:31:32.06#ibcon#[25=AT03-08\r\n] 2006.258.01:31:32.06#ibcon#*before write, iclass 37, count 2 2006.258.01:31:32.06#ibcon#enter sib2, iclass 37, count 2 2006.258.01:31:32.06#ibcon#flushed, iclass 37, count 2 2006.258.01:31:32.06#ibcon#about to write, iclass 37, count 2 2006.258.01:31:32.06#ibcon#wrote, iclass 37, count 2 2006.258.01:31:32.06#ibcon#about to read 3, iclass 37, count 2 2006.258.01:31:32.09#ibcon#read 3, iclass 37, count 2 2006.258.01:31:32.09#ibcon#about to read 4, iclass 37, count 2 2006.258.01:31:32.09#ibcon#read 4, iclass 37, count 2 2006.258.01:31:32.09#ibcon#about to read 5, iclass 37, count 2 2006.258.01:31:32.09#ibcon#read 5, iclass 37, count 2 2006.258.01:31:32.09#ibcon#about to read 6, iclass 37, count 2 2006.258.01:31:32.09#ibcon#read 6, iclass 37, count 2 2006.258.01:31:32.09#ibcon#end of sib2, iclass 37, count 2 2006.258.01:31:32.09#ibcon#*after write, iclass 37, count 2 2006.258.01:31:32.09#ibcon#*before return 0, iclass 37, count 2 2006.258.01:31:32.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:32.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:32.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.01:31:32.09#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:32.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:32.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:32.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:32.21#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:31:32.21#ibcon#first serial, iclass 37, count 0 2006.258.01:31:32.21#ibcon#enter sib2, iclass 37, count 0 2006.258.01:31:32.21#ibcon#flushed, iclass 37, count 0 2006.258.01:31:32.21#ibcon#about to write, iclass 37, count 0 2006.258.01:31:32.21#ibcon#wrote, iclass 37, count 0 2006.258.01:31:32.21#ibcon#about to read 3, iclass 37, count 0 2006.258.01:31:32.23#ibcon#read 3, iclass 37, count 0 2006.258.01:31:32.23#ibcon#about to read 4, iclass 37, count 0 2006.258.01:31:32.23#ibcon#read 4, iclass 37, count 0 2006.258.01:31:32.23#ibcon#about to read 5, iclass 37, count 0 2006.258.01:31:32.23#ibcon#read 5, iclass 37, count 0 2006.258.01:31:32.23#ibcon#about to read 6, iclass 37, count 0 2006.258.01:31:32.23#ibcon#read 6, iclass 37, count 0 2006.258.01:31:32.23#ibcon#end of sib2, iclass 37, count 0 2006.258.01:31:32.23#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:31:32.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:31:32.23#ibcon#[25=USB\r\n] 2006.258.01:31:32.23#ibcon#*before write, iclass 37, count 0 2006.258.01:31:32.23#ibcon#enter sib2, iclass 37, count 0 2006.258.01:31:32.23#ibcon#flushed, iclass 37, count 0 2006.258.01:31:32.23#ibcon#about to write, iclass 37, count 0 2006.258.01:31:32.23#ibcon#wrote, iclass 37, count 0 2006.258.01:31:32.23#ibcon#about to read 3, iclass 37, count 0 2006.258.01:31:32.26#ibcon#read 3, iclass 37, count 0 2006.258.01:31:32.26#ibcon#about to read 4, iclass 37, count 0 2006.258.01:31:32.26#ibcon#read 4, iclass 37, count 0 2006.258.01:31:32.26#ibcon#about to read 5, iclass 37, count 0 2006.258.01:31:32.26#ibcon#read 5, iclass 37, count 0 2006.258.01:31:32.26#ibcon#about to read 6, iclass 37, count 0 2006.258.01:31:32.26#ibcon#read 6, iclass 37, count 0 2006.258.01:31:32.26#ibcon#end of sib2, iclass 37, count 0 2006.258.01:31:32.26#ibcon#*after write, iclass 37, count 0 2006.258.01:31:32.26#ibcon#*before return 0, iclass 37, count 0 2006.258.01:31:32.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:32.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:32.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:31:32.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:31:32.26$vck44/valo=4,624.99 2006.258.01:31:32.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.01:31:32.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.01:31:32.26#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:32.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:32.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:32.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:32.26#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:31:32.26#ibcon#first serial, iclass 39, count 0 2006.258.01:31:32.26#ibcon#enter sib2, iclass 39, count 0 2006.258.01:31:32.26#ibcon#flushed, iclass 39, count 0 2006.258.01:31:32.26#ibcon#about to write, iclass 39, count 0 2006.258.01:31:32.26#ibcon#wrote, iclass 39, count 0 2006.258.01:31:32.26#ibcon#about to read 3, iclass 39, count 0 2006.258.01:31:32.28#ibcon#read 3, iclass 39, count 0 2006.258.01:31:32.28#ibcon#about to read 4, iclass 39, count 0 2006.258.01:31:32.28#ibcon#read 4, iclass 39, count 0 2006.258.01:31:32.28#ibcon#about to read 5, iclass 39, count 0 2006.258.01:31:32.28#ibcon#read 5, iclass 39, count 0 2006.258.01:31:32.28#ibcon#about to read 6, iclass 39, count 0 2006.258.01:31:32.28#ibcon#read 6, iclass 39, count 0 2006.258.01:31:32.28#ibcon#end of sib2, iclass 39, count 0 2006.258.01:31:32.28#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:31:32.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:31:32.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.01:31:32.28#ibcon#*before write, iclass 39, count 0 2006.258.01:31:32.28#ibcon#enter sib2, iclass 39, count 0 2006.258.01:31:32.28#ibcon#flushed, iclass 39, count 0 2006.258.01:31:32.28#ibcon#about to write, iclass 39, count 0 2006.258.01:31:32.28#ibcon#wrote, iclass 39, count 0 2006.258.01:31:32.28#ibcon#about to read 3, iclass 39, count 0 2006.258.01:31:32.32#ibcon#read 3, iclass 39, count 0 2006.258.01:31:32.32#ibcon#about to read 4, iclass 39, count 0 2006.258.01:31:32.32#ibcon#read 4, iclass 39, count 0 2006.258.01:31:32.32#ibcon#about to read 5, iclass 39, count 0 2006.258.01:31:32.32#ibcon#read 5, iclass 39, count 0 2006.258.01:31:32.32#ibcon#about to read 6, iclass 39, count 0 2006.258.01:31:32.32#ibcon#read 6, iclass 39, count 0 2006.258.01:31:32.32#ibcon#end of sib2, iclass 39, count 0 2006.258.01:31:32.32#ibcon#*after write, iclass 39, count 0 2006.258.01:31:32.32#ibcon#*before return 0, iclass 39, count 0 2006.258.01:31:32.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:32.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:32.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:31:32.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:31:32.32$vck44/va=4,7 2006.258.01:31:32.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.01:31:32.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.01:31:32.32#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:32.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:32.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:32.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:32.38#ibcon#enter wrdev, iclass 3, count 2 2006.258.01:31:32.38#ibcon#first serial, iclass 3, count 2 2006.258.01:31:32.38#ibcon#enter sib2, iclass 3, count 2 2006.258.01:31:32.38#ibcon#flushed, iclass 3, count 2 2006.258.01:31:32.38#ibcon#about to write, iclass 3, count 2 2006.258.01:31:32.38#ibcon#wrote, iclass 3, count 2 2006.258.01:31:32.38#ibcon#about to read 3, iclass 3, count 2 2006.258.01:31:32.40#ibcon#read 3, iclass 3, count 2 2006.258.01:31:32.40#ibcon#about to read 4, iclass 3, count 2 2006.258.01:31:32.40#ibcon#read 4, iclass 3, count 2 2006.258.01:31:32.40#ibcon#about to read 5, iclass 3, count 2 2006.258.01:31:32.40#ibcon#read 5, iclass 3, count 2 2006.258.01:31:32.40#ibcon#about to read 6, iclass 3, count 2 2006.258.01:31:32.40#ibcon#read 6, iclass 3, count 2 2006.258.01:31:32.40#ibcon#end of sib2, iclass 3, count 2 2006.258.01:31:32.40#ibcon#*mode == 0, iclass 3, count 2 2006.258.01:31:32.40#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.01:31:32.40#ibcon#[25=AT04-07\r\n] 2006.258.01:31:32.40#ibcon#*before write, iclass 3, count 2 2006.258.01:31:32.40#ibcon#enter sib2, iclass 3, count 2 2006.258.01:31:32.40#ibcon#flushed, iclass 3, count 2 2006.258.01:31:32.40#ibcon#about to write, iclass 3, count 2 2006.258.01:31:32.40#ibcon#wrote, iclass 3, count 2 2006.258.01:31:32.40#ibcon#about to read 3, iclass 3, count 2 2006.258.01:31:32.43#ibcon#read 3, iclass 3, count 2 2006.258.01:31:32.43#ibcon#about to read 4, iclass 3, count 2 2006.258.01:31:32.43#ibcon#read 4, iclass 3, count 2 2006.258.01:31:32.43#ibcon#about to read 5, iclass 3, count 2 2006.258.01:31:32.43#ibcon#read 5, iclass 3, count 2 2006.258.01:31:32.43#ibcon#about to read 6, iclass 3, count 2 2006.258.01:31:32.43#ibcon#read 6, iclass 3, count 2 2006.258.01:31:32.43#ibcon#end of sib2, iclass 3, count 2 2006.258.01:31:32.43#ibcon#*after write, iclass 3, count 2 2006.258.01:31:32.43#ibcon#*before return 0, iclass 3, count 2 2006.258.01:31:32.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:32.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:32.44#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.01:31:32.44#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:32.44#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:32.56#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:32.56#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:32.56#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:31:32.56#ibcon#first serial, iclass 3, count 0 2006.258.01:31:32.56#ibcon#enter sib2, iclass 3, count 0 2006.258.01:31:32.56#ibcon#flushed, iclass 3, count 0 2006.258.01:31:32.56#ibcon#about to write, iclass 3, count 0 2006.258.01:31:32.56#ibcon#wrote, iclass 3, count 0 2006.258.01:31:32.56#ibcon#about to read 3, iclass 3, count 0 2006.258.01:31:32.58#ibcon#read 3, iclass 3, count 0 2006.258.01:31:32.58#ibcon#about to read 4, iclass 3, count 0 2006.258.01:31:32.58#ibcon#read 4, iclass 3, count 0 2006.258.01:31:32.58#ibcon#about to read 5, iclass 3, count 0 2006.258.01:31:32.58#ibcon#read 5, iclass 3, count 0 2006.258.01:31:32.58#ibcon#about to read 6, iclass 3, count 0 2006.258.01:31:32.58#ibcon#read 6, iclass 3, count 0 2006.258.01:31:32.58#ibcon#end of sib2, iclass 3, count 0 2006.258.01:31:32.58#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:31:32.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:31:32.58#ibcon#[25=USB\r\n] 2006.258.01:31:32.58#ibcon#*before write, iclass 3, count 0 2006.258.01:31:32.58#ibcon#enter sib2, iclass 3, count 0 2006.258.01:31:32.58#ibcon#flushed, iclass 3, count 0 2006.258.01:31:32.58#ibcon#about to write, iclass 3, count 0 2006.258.01:31:32.58#ibcon#wrote, iclass 3, count 0 2006.258.01:31:32.58#ibcon#about to read 3, iclass 3, count 0 2006.258.01:31:32.61#ibcon#read 3, iclass 3, count 0 2006.258.01:31:32.61#ibcon#about to read 4, iclass 3, count 0 2006.258.01:31:32.61#ibcon#read 4, iclass 3, count 0 2006.258.01:31:32.61#ibcon#about to read 5, iclass 3, count 0 2006.258.01:31:32.61#ibcon#read 5, iclass 3, count 0 2006.258.01:31:32.61#ibcon#about to read 6, iclass 3, count 0 2006.258.01:31:32.61#ibcon#read 6, iclass 3, count 0 2006.258.01:31:32.61#ibcon#end of sib2, iclass 3, count 0 2006.258.01:31:32.61#ibcon#*after write, iclass 3, count 0 2006.258.01:31:32.61#ibcon#*before return 0, iclass 3, count 0 2006.258.01:31:32.61#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:32.61#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:32.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:31:32.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:31:32.61$vck44/valo=5,734.99 2006.258.01:31:32.61#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.01:31:32.61#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.01:31:32.61#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:32.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:32.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:32.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:32.61#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:31:32.61#ibcon#first serial, iclass 5, count 0 2006.258.01:31:32.61#ibcon#enter sib2, iclass 5, count 0 2006.258.01:31:32.61#ibcon#flushed, iclass 5, count 0 2006.258.01:31:32.61#ibcon#about to write, iclass 5, count 0 2006.258.01:31:32.61#ibcon#wrote, iclass 5, count 0 2006.258.01:31:32.61#ibcon#about to read 3, iclass 5, count 0 2006.258.01:31:32.63#ibcon#read 3, iclass 5, count 0 2006.258.01:31:32.63#ibcon#about to read 4, iclass 5, count 0 2006.258.01:31:32.63#ibcon#read 4, iclass 5, count 0 2006.258.01:31:32.63#ibcon#about to read 5, iclass 5, count 0 2006.258.01:31:32.63#ibcon#read 5, iclass 5, count 0 2006.258.01:31:32.63#ibcon#about to read 6, iclass 5, count 0 2006.258.01:31:32.63#ibcon#read 6, iclass 5, count 0 2006.258.01:31:32.63#ibcon#end of sib2, iclass 5, count 0 2006.258.01:31:32.63#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:31:32.63#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:31:32.63#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.01:31:32.63#ibcon#*before write, iclass 5, count 0 2006.258.01:31:32.63#ibcon#enter sib2, iclass 5, count 0 2006.258.01:31:32.63#ibcon#flushed, iclass 5, count 0 2006.258.01:31:32.63#ibcon#about to write, iclass 5, count 0 2006.258.01:31:32.63#ibcon#wrote, iclass 5, count 0 2006.258.01:31:32.63#ibcon#about to read 3, iclass 5, count 0 2006.258.01:31:32.67#ibcon#read 3, iclass 5, count 0 2006.258.01:31:32.67#ibcon#about to read 4, iclass 5, count 0 2006.258.01:31:32.67#ibcon#read 4, iclass 5, count 0 2006.258.01:31:32.67#ibcon#about to read 5, iclass 5, count 0 2006.258.01:31:32.67#ibcon#read 5, iclass 5, count 0 2006.258.01:31:32.67#ibcon#about to read 6, iclass 5, count 0 2006.258.01:31:32.67#ibcon#read 6, iclass 5, count 0 2006.258.01:31:32.67#ibcon#end of sib2, iclass 5, count 0 2006.258.01:31:32.67#ibcon#*after write, iclass 5, count 0 2006.258.01:31:32.67#ibcon#*before return 0, iclass 5, count 0 2006.258.01:31:32.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:32.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:32.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:31:32.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:31:32.67$vck44/va=5,4 2006.258.01:31:32.67#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.01:31:32.67#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.01:31:32.67#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:32.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:32.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:32.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:32.73#ibcon#enter wrdev, iclass 7, count 2 2006.258.01:31:32.73#ibcon#first serial, iclass 7, count 2 2006.258.01:31:32.73#ibcon#enter sib2, iclass 7, count 2 2006.258.01:31:32.73#ibcon#flushed, iclass 7, count 2 2006.258.01:31:32.73#ibcon#about to write, iclass 7, count 2 2006.258.01:31:32.73#ibcon#wrote, iclass 7, count 2 2006.258.01:31:32.73#ibcon#about to read 3, iclass 7, count 2 2006.258.01:31:32.75#ibcon#read 3, iclass 7, count 2 2006.258.01:31:32.75#ibcon#about to read 4, iclass 7, count 2 2006.258.01:31:32.75#ibcon#read 4, iclass 7, count 2 2006.258.01:31:32.75#ibcon#about to read 5, iclass 7, count 2 2006.258.01:31:32.75#ibcon#read 5, iclass 7, count 2 2006.258.01:31:32.75#ibcon#about to read 6, iclass 7, count 2 2006.258.01:31:32.75#ibcon#read 6, iclass 7, count 2 2006.258.01:31:32.75#ibcon#end of sib2, iclass 7, count 2 2006.258.01:31:32.75#ibcon#*mode == 0, iclass 7, count 2 2006.258.01:31:32.75#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.01:31:32.75#ibcon#[25=AT05-04\r\n] 2006.258.01:31:32.75#ibcon#*before write, iclass 7, count 2 2006.258.01:31:32.75#ibcon#enter sib2, iclass 7, count 2 2006.258.01:31:32.75#ibcon#flushed, iclass 7, count 2 2006.258.01:31:32.75#ibcon#about to write, iclass 7, count 2 2006.258.01:31:32.75#ibcon#wrote, iclass 7, count 2 2006.258.01:31:32.75#ibcon#about to read 3, iclass 7, count 2 2006.258.01:31:32.78#ibcon#read 3, iclass 7, count 2 2006.258.01:31:32.78#ibcon#about to read 4, iclass 7, count 2 2006.258.01:31:32.78#ibcon#read 4, iclass 7, count 2 2006.258.01:31:32.78#ibcon#about to read 5, iclass 7, count 2 2006.258.01:31:32.78#ibcon#read 5, iclass 7, count 2 2006.258.01:31:32.78#ibcon#about to read 6, iclass 7, count 2 2006.258.01:31:32.78#ibcon#read 6, iclass 7, count 2 2006.258.01:31:32.78#ibcon#end of sib2, iclass 7, count 2 2006.258.01:31:32.78#ibcon#*after write, iclass 7, count 2 2006.258.01:31:32.78#ibcon#*before return 0, iclass 7, count 2 2006.258.01:31:32.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:32.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:32.78#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.01:31:32.78#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:32.78#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:32.90#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:32.90#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:32.90#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:31:32.90#ibcon#first serial, iclass 7, count 0 2006.258.01:31:32.90#ibcon#enter sib2, iclass 7, count 0 2006.258.01:31:32.90#ibcon#flushed, iclass 7, count 0 2006.258.01:31:32.90#ibcon#about to write, iclass 7, count 0 2006.258.01:31:32.90#ibcon#wrote, iclass 7, count 0 2006.258.01:31:32.90#ibcon#about to read 3, iclass 7, count 0 2006.258.01:31:32.92#ibcon#read 3, iclass 7, count 0 2006.258.01:31:32.92#ibcon#about to read 4, iclass 7, count 0 2006.258.01:31:32.92#ibcon#read 4, iclass 7, count 0 2006.258.01:31:32.92#ibcon#about to read 5, iclass 7, count 0 2006.258.01:31:32.92#ibcon#read 5, iclass 7, count 0 2006.258.01:31:32.92#ibcon#about to read 6, iclass 7, count 0 2006.258.01:31:32.92#ibcon#read 6, iclass 7, count 0 2006.258.01:31:32.92#ibcon#end of sib2, iclass 7, count 0 2006.258.01:31:32.92#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:31:32.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:31:32.92#ibcon#[25=USB\r\n] 2006.258.01:31:32.92#ibcon#*before write, iclass 7, count 0 2006.258.01:31:32.92#ibcon#enter sib2, iclass 7, count 0 2006.258.01:31:32.92#ibcon#flushed, iclass 7, count 0 2006.258.01:31:32.92#ibcon#about to write, iclass 7, count 0 2006.258.01:31:32.92#ibcon#wrote, iclass 7, count 0 2006.258.01:31:32.92#ibcon#about to read 3, iclass 7, count 0 2006.258.01:31:32.95#ibcon#read 3, iclass 7, count 0 2006.258.01:31:32.95#ibcon#about to read 4, iclass 7, count 0 2006.258.01:31:32.95#ibcon#read 4, iclass 7, count 0 2006.258.01:31:32.95#ibcon#about to read 5, iclass 7, count 0 2006.258.01:31:32.95#ibcon#read 5, iclass 7, count 0 2006.258.01:31:32.95#ibcon#about to read 6, iclass 7, count 0 2006.258.01:31:32.95#ibcon#read 6, iclass 7, count 0 2006.258.01:31:32.95#ibcon#end of sib2, iclass 7, count 0 2006.258.01:31:32.95#ibcon#*after write, iclass 7, count 0 2006.258.01:31:32.95#ibcon#*before return 0, iclass 7, count 0 2006.258.01:31:32.95#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:32.95#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:32.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:31:32.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:31:32.95$vck44/valo=6,814.99 2006.258.01:31:32.95#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.01:31:32.95#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.01:31:32.95#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:32.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:32.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:32.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:32.95#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:31:32.95#ibcon#first serial, iclass 11, count 0 2006.258.01:31:32.95#ibcon#enter sib2, iclass 11, count 0 2006.258.01:31:32.95#ibcon#flushed, iclass 11, count 0 2006.258.01:31:32.95#ibcon#about to write, iclass 11, count 0 2006.258.01:31:32.95#ibcon#wrote, iclass 11, count 0 2006.258.01:31:32.95#ibcon#about to read 3, iclass 11, count 0 2006.258.01:31:32.97#ibcon#read 3, iclass 11, count 0 2006.258.01:31:32.97#ibcon#about to read 4, iclass 11, count 0 2006.258.01:31:32.97#ibcon#read 4, iclass 11, count 0 2006.258.01:31:32.97#ibcon#about to read 5, iclass 11, count 0 2006.258.01:31:32.97#ibcon#read 5, iclass 11, count 0 2006.258.01:31:32.97#ibcon#about to read 6, iclass 11, count 0 2006.258.01:31:32.97#ibcon#read 6, iclass 11, count 0 2006.258.01:31:32.97#ibcon#end of sib2, iclass 11, count 0 2006.258.01:31:32.97#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:31:32.97#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:31:32.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.01:31:32.97#ibcon#*before write, iclass 11, count 0 2006.258.01:31:32.97#ibcon#enter sib2, iclass 11, count 0 2006.258.01:31:32.97#ibcon#flushed, iclass 11, count 0 2006.258.01:31:32.97#ibcon#about to write, iclass 11, count 0 2006.258.01:31:32.97#ibcon#wrote, iclass 11, count 0 2006.258.01:31:32.97#ibcon#about to read 3, iclass 11, count 0 2006.258.01:31:33.01#ibcon#read 3, iclass 11, count 0 2006.258.01:31:33.01#ibcon#about to read 4, iclass 11, count 0 2006.258.01:31:33.01#ibcon#read 4, iclass 11, count 0 2006.258.01:31:33.01#ibcon#about to read 5, iclass 11, count 0 2006.258.01:31:33.01#ibcon#read 5, iclass 11, count 0 2006.258.01:31:33.01#ibcon#about to read 6, iclass 11, count 0 2006.258.01:31:33.01#ibcon#read 6, iclass 11, count 0 2006.258.01:31:33.01#ibcon#end of sib2, iclass 11, count 0 2006.258.01:31:33.01#ibcon#*after write, iclass 11, count 0 2006.258.01:31:33.01#ibcon#*before return 0, iclass 11, count 0 2006.258.01:31:33.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:33.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:33.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:31:33.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:31:33.01$vck44/va=6,4 2006.258.01:31:33.01#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.01:31:33.01#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.01:31:33.01#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:33.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:33.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:33.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:33.07#ibcon#enter wrdev, iclass 13, count 2 2006.258.01:31:33.07#ibcon#first serial, iclass 13, count 2 2006.258.01:31:33.07#ibcon#enter sib2, iclass 13, count 2 2006.258.01:31:33.07#ibcon#flushed, iclass 13, count 2 2006.258.01:31:33.07#ibcon#about to write, iclass 13, count 2 2006.258.01:31:33.07#ibcon#wrote, iclass 13, count 2 2006.258.01:31:33.07#ibcon#about to read 3, iclass 13, count 2 2006.258.01:31:33.09#ibcon#read 3, iclass 13, count 2 2006.258.01:31:33.09#ibcon#about to read 4, iclass 13, count 2 2006.258.01:31:33.09#ibcon#read 4, iclass 13, count 2 2006.258.01:31:33.09#ibcon#about to read 5, iclass 13, count 2 2006.258.01:31:33.09#ibcon#read 5, iclass 13, count 2 2006.258.01:31:33.09#ibcon#about to read 6, iclass 13, count 2 2006.258.01:31:33.09#ibcon#read 6, iclass 13, count 2 2006.258.01:31:33.09#ibcon#end of sib2, iclass 13, count 2 2006.258.01:31:33.09#ibcon#*mode == 0, iclass 13, count 2 2006.258.01:31:33.09#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.01:31:33.09#ibcon#[25=AT06-04\r\n] 2006.258.01:31:33.09#ibcon#*before write, iclass 13, count 2 2006.258.01:31:33.09#ibcon#enter sib2, iclass 13, count 2 2006.258.01:31:33.09#ibcon#flushed, iclass 13, count 2 2006.258.01:31:33.09#ibcon#about to write, iclass 13, count 2 2006.258.01:31:33.09#ibcon#wrote, iclass 13, count 2 2006.258.01:31:33.09#ibcon#about to read 3, iclass 13, count 2 2006.258.01:31:33.12#ibcon#read 3, iclass 13, count 2 2006.258.01:31:33.12#ibcon#about to read 4, iclass 13, count 2 2006.258.01:31:33.12#ibcon#read 4, iclass 13, count 2 2006.258.01:31:33.12#ibcon#about to read 5, iclass 13, count 2 2006.258.01:31:33.12#ibcon#read 5, iclass 13, count 2 2006.258.01:31:33.12#ibcon#about to read 6, iclass 13, count 2 2006.258.01:31:33.12#ibcon#read 6, iclass 13, count 2 2006.258.01:31:33.12#ibcon#end of sib2, iclass 13, count 2 2006.258.01:31:33.12#ibcon#*after write, iclass 13, count 2 2006.258.01:31:33.12#ibcon#*before return 0, iclass 13, count 2 2006.258.01:31:33.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:33.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:33.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.01:31:33.12#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:33.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:33.24#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:33.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:33.24#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:31:33.24#ibcon#first serial, iclass 13, count 0 2006.258.01:31:33.24#ibcon#enter sib2, iclass 13, count 0 2006.258.01:31:33.24#ibcon#flushed, iclass 13, count 0 2006.258.01:31:33.24#ibcon#about to write, iclass 13, count 0 2006.258.01:31:33.24#ibcon#wrote, iclass 13, count 0 2006.258.01:31:33.24#ibcon#about to read 3, iclass 13, count 0 2006.258.01:31:33.26#ibcon#read 3, iclass 13, count 0 2006.258.01:31:33.26#ibcon#about to read 4, iclass 13, count 0 2006.258.01:31:33.26#ibcon#read 4, iclass 13, count 0 2006.258.01:31:33.26#ibcon#about to read 5, iclass 13, count 0 2006.258.01:31:33.26#ibcon#read 5, iclass 13, count 0 2006.258.01:31:33.26#ibcon#about to read 6, iclass 13, count 0 2006.258.01:31:33.26#ibcon#read 6, iclass 13, count 0 2006.258.01:31:33.26#ibcon#end of sib2, iclass 13, count 0 2006.258.01:31:33.26#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:31:33.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:31:33.26#ibcon#[25=USB\r\n] 2006.258.01:31:33.26#ibcon#*before write, iclass 13, count 0 2006.258.01:31:33.26#ibcon#enter sib2, iclass 13, count 0 2006.258.01:31:33.26#ibcon#flushed, iclass 13, count 0 2006.258.01:31:33.26#ibcon#about to write, iclass 13, count 0 2006.258.01:31:33.26#ibcon#wrote, iclass 13, count 0 2006.258.01:31:33.26#ibcon#about to read 3, iclass 13, count 0 2006.258.01:31:33.29#ibcon#read 3, iclass 13, count 0 2006.258.01:31:33.29#ibcon#about to read 4, iclass 13, count 0 2006.258.01:31:33.29#ibcon#read 4, iclass 13, count 0 2006.258.01:31:33.29#ibcon#about to read 5, iclass 13, count 0 2006.258.01:31:33.29#ibcon#read 5, iclass 13, count 0 2006.258.01:31:33.29#ibcon#about to read 6, iclass 13, count 0 2006.258.01:31:33.29#ibcon#read 6, iclass 13, count 0 2006.258.01:31:33.29#ibcon#end of sib2, iclass 13, count 0 2006.258.01:31:33.29#ibcon#*after write, iclass 13, count 0 2006.258.01:31:33.29#ibcon#*before return 0, iclass 13, count 0 2006.258.01:31:33.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:33.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:33.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:31:33.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:31:33.29$vck44/valo=7,864.99 2006.258.01:31:33.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.01:31:33.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.01:31:33.29#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:33.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:33.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:33.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:33.29#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:31:33.29#ibcon#first serial, iclass 15, count 0 2006.258.01:31:33.29#ibcon#enter sib2, iclass 15, count 0 2006.258.01:31:33.29#ibcon#flushed, iclass 15, count 0 2006.258.01:31:33.29#ibcon#about to write, iclass 15, count 0 2006.258.01:31:33.29#ibcon#wrote, iclass 15, count 0 2006.258.01:31:33.29#ibcon#about to read 3, iclass 15, count 0 2006.258.01:31:33.31#ibcon#read 3, iclass 15, count 0 2006.258.01:31:33.31#ibcon#about to read 4, iclass 15, count 0 2006.258.01:31:33.31#ibcon#read 4, iclass 15, count 0 2006.258.01:31:33.31#ibcon#about to read 5, iclass 15, count 0 2006.258.01:31:33.31#ibcon#read 5, iclass 15, count 0 2006.258.01:31:33.31#ibcon#about to read 6, iclass 15, count 0 2006.258.01:31:33.31#ibcon#read 6, iclass 15, count 0 2006.258.01:31:33.31#ibcon#end of sib2, iclass 15, count 0 2006.258.01:31:33.31#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:31:33.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:31:33.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.01:31:33.31#ibcon#*before write, iclass 15, count 0 2006.258.01:31:33.31#ibcon#enter sib2, iclass 15, count 0 2006.258.01:31:33.31#ibcon#flushed, iclass 15, count 0 2006.258.01:31:33.31#ibcon#about to write, iclass 15, count 0 2006.258.01:31:33.31#ibcon#wrote, iclass 15, count 0 2006.258.01:31:33.31#ibcon#about to read 3, iclass 15, count 0 2006.258.01:31:33.35#ibcon#read 3, iclass 15, count 0 2006.258.01:31:33.35#ibcon#about to read 4, iclass 15, count 0 2006.258.01:31:33.35#ibcon#read 4, iclass 15, count 0 2006.258.01:31:33.35#ibcon#about to read 5, iclass 15, count 0 2006.258.01:31:33.35#ibcon#read 5, iclass 15, count 0 2006.258.01:31:33.35#ibcon#about to read 6, iclass 15, count 0 2006.258.01:31:33.35#ibcon#read 6, iclass 15, count 0 2006.258.01:31:33.35#ibcon#end of sib2, iclass 15, count 0 2006.258.01:31:33.35#ibcon#*after write, iclass 15, count 0 2006.258.01:31:33.35#ibcon#*before return 0, iclass 15, count 0 2006.258.01:31:33.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:33.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:33.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:31:33.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:31:33.35$vck44/va=7,4 2006.258.01:31:33.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.01:31:33.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.01:31:33.35#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:33.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:33.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:33.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:33.41#ibcon#enter wrdev, iclass 17, count 2 2006.258.01:31:33.41#ibcon#first serial, iclass 17, count 2 2006.258.01:31:33.41#ibcon#enter sib2, iclass 17, count 2 2006.258.01:31:33.41#ibcon#flushed, iclass 17, count 2 2006.258.01:31:33.41#ibcon#about to write, iclass 17, count 2 2006.258.01:31:33.41#ibcon#wrote, iclass 17, count 2 2006.258.01:31:33.41#ibcon#about to read 3, iclass 17, count 2 2006.258.01:31:33.43#ibcon#read 3, iclass 17, count 2 2006.258.01:31:33.43#ibcon#about to read 4, iclass 17, count 2 2006.258.01:31:33.43#ibcon#read 4, iclass 17, count 2 2006.258.01:31:33.43#ibcon#about to read 5, iclass 17, count 2 2006.258.01:31:33.43#ibcon#read 5, iclass 17, count 2 2006.258.01:31:33.43#ibcon#about to read 6, iclass 17, count 2 2006.258.01:31:33.43#ibcon#read 6, iclass 17, count 2 2006.258.01:31:33.43#ibcon#end of sib2, iclass 17, count 2 2006.258.01:31:33.43#ibcon#*mode == 0, iclass 17, count 2 2006.258.01:31:33.43#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.01:31:33.43#ibcon#[25=AT07-04\r\n] 2006.258.01:31:33.43#ibcon#*before write, iclass 17, count 2 2006.258.01:31:33.43#ibcon#enter sib2, iclass 17, count 2 2006.258.01:31:33.43#ibcon#flushed, iclass 17, count 2 2006.258.01:31:33.43#ibcon#about to write, iclass 17, count 2 2006.258.01:31:33.43#ibcon#wrote, iclass 17, count 2 2006.258.01:31:33.43#ibcon#about to read 3, iclass 17, count 2 2006.258.01:31:33.46#ibcon#read 3, iclass 17, count 2 2006.258.01:31:33.46#ibcon#about to read 4, iclass 17, count 2 2006.258.01:31:33.46#ibcon#read 4, iclass 17, count 2 2006.258.01:31:33.46#ibcon#about to read 5, iclass 17, count 2 2006.258.01:31:33.46#ibcon#read 5, iclass 17, count 2 2006.258.01:31:33.46#ibcon#about to read 6, iclass 17, count 2 2006.258.01:31:33.46#ibcon#read 6, iclass 17, count 2 2006.258.01:31:33.46#ibcon#end of sib2, iclass 17, count 2 2006.258.01:31:33.46#ibcon#*after write, iclass 17, count 2 2006.258.01:31:33.46#ibcon#*before return 0, iclass 17, count 2 2006.258.01:31:33.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:33.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:33.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.01:31:33.46#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:33.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:33.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:33.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:33.58#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:31:33.58#ibcon#first serial, iclass 17, count 0 2006.258.01:31:33.58#ibcon#enter sib2, iclass 17, count 0 2006.258.01:31:33.58#ibcon#flushed, iclass 17, count 0 2006.258.01:31:33.58#ibcon#about to write, iclass 17, count 0 2006.258.01:31:33.58#ibcon#wrote, iclass 17, count 0 2006.258.01:31:33.58#ibcon#about to read 3, iclass 17, count 0 2006.258.01:31:33.60#ibcon#read 3, iclass 17, count 0 2006.258.01:31:33.60#ibcon#about to read 4, iclass 17, count 0 2006.258.01:31:33.60#ibcon#read 4, iclass 17, count 0 2006.258.01:31:33.60#ibcon#about to read 5, iclass 17, count 0 2006.258.01:31:33.60#ibcon#read 5, iclass 17, count 0 2006.258.01:31:33.60#ibcon#about to read 6, iclass 17, count 0 2006.258.01:31:33.60#ibcon#read 6, iclass 17, count 0 2006.258.01:31:33.60#ibcon#end of sib2, iclass 17, count 0 2006.258.01:31:33.60#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:31:33.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:31:33.60#ibcon#[25=USB\r\n] 2006.258.01:31:33.60#ibcon#*before write, iclass 17, count 0 2006.258.01:31:33.60#ibcon#enter sib2, iclass 17, count 0 2006.258.01:31:33.60#ibcon#flushed, iclass 17, count 0 2006.258.01:31:33.60#ibcon#about to write, iclass 17, count 0 2006.258.01:31:33.60#ibcon#wrote, iclass 17, count 0 2006.258.01:31:33.60#ibcon#about to read 3, iclass 17, count 0 2006.258.01:31:33.63#ibcon#read 3, iclass 17, count 0 2006.258.01:31:33.63#ibcon#about to read 4, iclass 17, count 0 2006.258.01:31:33.63#ibcon#read 4, iclass 17, count 0 2006.258.01:31:33.63#ibcon#about to read 5, iclass 17, count 0 2006.258.01:31:33.63#ibcon#read 5, iclass 17, count 0 2006.258.01:31:33.63#ibcon#about to read 6, iclass 17, count 0 2006.258.01:31:33.63#ibcon#read 6, iclass 17, count 0 2006.258.01:31:33.63#ibcon#end of sib2, iclass 17, count 0 2006.258.01:31:33.63#ibcon#*after write, iclass 17, count 0 2006.258.01:31:33.63#ibcon#*before return 0, iclass 17, count 0 2006.258.01:31:33.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:33.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:33.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:31:33.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:31:33.63$vck44/valo=8,884.99 2006.258.01:31:33.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.01:31:33.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.01:31:33.63#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:33.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:33.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:33.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:33.63#ibcon#enter wrdev, iclass 19, count 0 2006.258.01:31:33.63#ibcon#first serial, iclass 19, count 0 2006.258.01:31:33.63#ibcon#enter sib2, iclass 19, count 0 2006.258.01:31:33.63#ibcon#flushed, iclass 19, count 0 2006.258.01:31:33.63#ibcon#about to write, iclass 19, count 0 2006.258.01:31:33.63#ibcon#wrote, iclass 19, count 0 2006.258.01:31:33.63#ibcon#about to read 3, iclass 19, count 0 2006.258.01:31:33.65#ibcon#read 3, iclass 19, count 0 2006.258.01:31:33.65#ibcon#about to read 4, iclass 19, count 0 2006.258.01:31:33.65#ibcon#read 4, iclass 19, count 0 2006.258.01:31:33.65#ibcon#about to read 5, iclass 19, count 0 2006.258.01:31:33.65#ibcon#read 5, iclass 19, count 0 2006.258.01:31:33.65#ibcon#about to read 6, iclass 19, count 0 2006.258.01:31:33.65#ibcon#read 6, iclass 19, count 0 2006.258.01:31:33.65#ibcon#end of sib2, iclass 19, count 0 2006.258.01:31:33.65#ibcon#*mode == 0, iclass 19, count 0 2006.258.01:31:33.65#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.01:31:33.65#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.01:31:33.65#ibcon#*before write, iclass 19, count 0 2006.258.01:31:33.65#ibcon#enter sib2, iclass 19, count 0 2006.258.01:31:33.65#ibcon#flushed, iclass 19, count 0 2006.258.01:31:33.65#ibcon#about to write, iclass 19, count 0 2006.258.01:31:33.65#ibcon#wrote, iclass 19, count 0 2006.258.01:31:33.65#ibcon#about to read 3, iclass 19, count 0 2006.258.01:31:33.69#ibcon#read 3, iclass 19, count 0 2006.258.01:31:33.69#ibcon#about to read 4, iclass 19, count 0 2006.258.01:31:33.69#ibcon#read 4, iclass 19, count 0 2006.258.01:31:33.69#ibcon#about to read 5, iclass 19, count 0 2006.258.01:31:33.69#ibcon#read 5, iclass 19, count 0 2006.258.01:31:33.69#ibcon#about to read 6, iclass 19, count 0 2006.258.01:31:33.69#ibcon#read 6, iclass 19, count 0 2006.258.01:31:33.69#ibcon#end of sib2, iclass 19, count 0 2006.258.01:31:33.69#ibcon#*after write, iclass 19, count 0 2006.258.01:31:33.69#ibcon#*before return 0, iclass 19, count 0 2006.258.01:31:33.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:33.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:33.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.01:31:33.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.01:31:33.69$vck44/va=8,4 2006.258.01:31:33.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.01:31:33.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.01:31:33.69#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:33.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:33.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:33.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:33.75#ibcon#enter wrdev, iclass 21, count 2 2006.258.01:31:33.75#ibcon#first serial, iclass 21, count 2 2006.258.01:31:33.75#ibcon#enter sib2, iclass 21, count 2 2006.258.01:31:33.75#ibcon#flushed, iclass 21, count 2 2006.258.01:31:33.75#ibcon#about to write, iclass 21, count 2 2006.258.01:31:33.75#ibcon#wrote, iclass 21, count 2 2006.258.01:31:33.75#ibcon#about to read 3, iclass 21, count 2 2006.258.01:31:33.77#ibcon#read 3, iclass 21, count 2 2006.258.01:31:33.77#ibcon#about to read 4, iclass 21, count 2 2006.258.01:31:33.77#ibcon#read 4, iclass 21, count 2 2006.258.01:31:33.77#ibcon#about to read 5, iclass 21, count 2 2006.258.01:31:33.77#ibcon#read 5, iclass 21, count 2 2006.258.01:31:33.77#ibcon#about to read 6, iclass 21, count 2 2006.258.01:31:33.77#ibcon#read 6, iclass 21, count 2 2006.258.01:31:33.77#ibcon#end of sib2, iclass 21, count 2 2006.258.01:31:33.77#ibcon#*mode == 0, iclass 21, count 2 2006.258.01:31:33.77#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.01:31:33.77#ibcon#[25=AT08-04\r\n] 2006.258.01:31:33.77#ibcon#*before write, iclass 21, count 2 2006.258.01:31:33.77#ibcon#enter sib2, iclass 21, count 2 2006.258.01:31:33.77#ibcon#flushed, iclass 21, count 2 2006.258.01:31:33.77#ibcon#about to write, iclass 21, count 2 2006.258.01:31:33.77#ibcon#wrote, iclass 21, count 2 2006.258.01:31:33.77#ibcon#about to read 3, iclass 21, count 2 2006.258.01:31:33.80#ibcon#read 3, iclass 21, count 2 2006.258.01:31:33.80#ibcon#about to read 4, iclass 21, count 2 2006.258.01:31:33.80#ibcon#read 4, iclass 21, count 2 2006.258.01:31:33.80#ibcon#about to read 5, iclass 21, count 2 2006.258.01:31:33.80#ibcon#read 5, iclass 21, count 2 2006.258.01:31:33.80#ibcon#about to read 6, iclass 21, count 2 2006.258.01:31:33.80#ibcon#read 6, iclass 21, count 2 2006.258.01:31:33.80#ibcon#end of sib2, iclass 21, count 2 2006.258.01:31:33.80#ibcon#*after write, iclass 21, count 2 2006.258.01:31:33.80#ibcon#*before return 0, iclass 21, count 2 2006.258.01:31:33.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:33.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:33.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.01:31:33.80#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:33.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:33.92#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:33.92#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:33.92#ibcon#enter wrdev, iclass 21, count 0 2006.258.01:31:33.92#ibcon#first serial, iclass 21, count 0 2006.258.01:31:33.92#ibcon#enter sib2, iclass 21, count 0 2006.258.01:31:33.92#ibcon#flushed, iclass 21, count 0 2006.258.01:31:33.92#ibcon#about to write, iclass 21, count 0 2006.258.01:31:33.92#ibcon#wrote, iclass 21, count 0 2006.258.01:31:33.92#ibcon#about to read 3, iclass 21, count 0 2006.258.01:31:33.94#ibcon#read 3, iclass 21, count 0 2006.258.01:31:33.94#ibcon#about to read 4, iclass 21, count 0 2006.258.01:31:33.94#ibcon#read 4, iclass 21, count 0 2006.258.01:31:33.94#ibcon#about to read 5, iclass 21, count 0 2006.258.01:31:33.94#ibcon#read 5, iclass 21, count 0 2006.258.01:31:33.94#ibcon#about to read 6, iclass 21, count 0 2006.258.01:31:33.94#ibcon#read 6, iclass 21, count 0 2006.258.01:31:33.94#ibcon#end of sib2, iclass 21, count 0 2006.258.01:31:33.94#ibcon#*mode == 0, iclass 21, count 0 2006.258.01:31:33.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.01:31:33.94#ibcon#[25=USB\r\n] 2006.258.01:31:33.94#ibcon#*before write, iclass 21, count 0 2006.258.01:31:33.94#ibcon#enter sib2, iclass 21, count 0 2006.258.01:31:33.94#ibcon#flushed, iclass 21, count 0 2006.258.01:31:33.94#ibcon#about to write, iclass 21, count 0 2006.258.01:31:33.94#ibcon#wrote, iclass 21, count 0 2006.258.01:31:33.94#ibcon#about to read 3, iclass 21, count 0 2006.258.01:31:33.97#ibcon#read 3, iclass 21, count 0 2006.258.01:31:33.97#ibcon#about to read 4, iclass 21, count 0 2006.258.01:31:33.97#ibcon#read 4, iclass 21, count 0 2006.258.01:31:33.97#ibcon#about to read 5, iclass 21, count 0 2006.258.01:31:33.97#ibcon#read 5, iclass 21, count 0 2006.258.01:31:33.97#ibcon#about to read 6, iclass 21, count 0 2006.258.01:31:33.97#ibcon#read 6, iclass 21, count 0 2006.258.01:31:33.97#ibcon#end of sib2, iclass 21, count 0 2006.258.01:31:33.97#ibcon#*after write, iclass 21, count 0 2006.258.01:31:33.97#ibcon#*before return 0, iclass 21, count 0 2006.258.01:31:33.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:33.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:33.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.01:31:33.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.01:31:33.97$vck44/vblo=1,629.99 2006.258.01:31:33.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.01:31:33.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.01:31:33.97#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:33.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:33.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:33.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:33.97#ibcon#enter wrdev, iclass 23, count 0 2006.258.01:31:33.97#ibcon#first serial, iclass 23, count 0 2006.258.01:31:33.97#ibcon#enter sib2, iclass 23, count 0 2006.258.01:31:33.97#ibcon#flushed, iclass 23, count 0 2006.258.01:31:33.97#ibcon#about to write, iclass 23, count 0 2006.258.01:31:33.97#ibcon#wrote, iclass 23, count 0 2006.258.01:31:33.97#ibcon#about to read 3, iclass 23, count 0 2006.258.01:31:33.99#ibcon#read 3, iclass 23, count 0 2006.258.01:31:33.99#ibcon#about to read 4, iclass 23, count 0 2006.258.01:31:33.99#ibcon#read 4, iclass 23, count 0 2006.258.01:31:33.99#ibcon#about to read 5, iclass 23, count 0 2006.258.01:31:33.99#ibcon#read 5, iclass 23, count 0 2006.258.01:31:33.99#ibcon#about to read 6, iclass 23, count 0 2006.258.01:31:33.99#ibcon#read 6, iclass 23, count 0 2006.258.01:31:33.99#ibcon#end of sib2, iclass 23, count 0 2006.258.01:31:33.99#ibcon#*mode == 0, iclass 23, count 0 2006.258.01:31:33.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.01:31:33.99#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.01:31:33.99#ibcon#*before write, iclass 23, count 0 2006.258.01:31:33.99#ibcon#enter sib2, iclass 23, count 0 2006.258.01:31:33.99#ibcon#flushed, iclass 23, count 0 2006.258.01:31:33.99#ibcon#about to write, iclass 23, count 0 2006.258.01:31:33.99#ibcon#wrote, iclass 23, count 0 2006.258.01:31:33.99#ibcon#about to read 3, iclass 23, count 0 2006.258.01:31:34.03#ibcon#read 3, iclass 23, count 0 2006.258.01:31:34.03#ibcon#about to read 4, iclass 23, count 0 2006.258.01:31:34.03#ibcon#read 4, iclass 23, count 0 2006.258.01:31:34.03#ibcon#about to read 5, iclass 23, count 0 2006.258.01:31:34.03#ibcon#read 5, iclass 23, count 0 2006.258.01:31:34.03#ibcon#about to read 6, iclass 23, count 0 2006.258.01:31:34.03#ibcon#read 6, iclass 23, count 0 2006.258.01:31:34.03#ibcon#end of sib2, iclass 23, count 0 2006.258.01:31:34.03#ibcon#*after write, iclass 23, count 0 2006.258.01:31:34.03#ibcon#*before return 0, iclass 23, count 0 2006.258.01:31:34.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:34.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:34.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.01:31:34.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.01:31:34.03$vck44/vb=1,4 2006.258.01:31:34.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.258.01:31:34.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.258.01:31:34.03#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:34.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:31:34.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:31:34.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:31:34.03#ibcon#enter wrdev, iclass 25, count 2 2006.258.01:31:34.03#ibcon#first serial, iclass 25, count 2 2006.258.01:31:34.03#ibcon#enter sib2, iclass 25, count 2 2006.258.01:31:34.03#ibcon#flushed, iclass 25, count 2 2006.258.01:31:34.03#ibcon#about to write, iclass 25, count 2 2006.258.01:31:34.03#ibcon#wrote, iclass 25, count 2 2006.258.01:31:34.03#ibcon#about to read 3, iclass 25, count 2 2006.258.01:31:34.05#ibcon#read 3, iclass 25, count 2 2006.258.01:31:34.05#ibcon#about to read 4, iclass 25, count 2 2006.258.01:31:34.05#ibcon#read 4, iclass 25, count 2 2006.258.01:31:34.05#ibcon#about to read 5, iclass 25, count 2 2006.258.01:31:34.05#ibcon#read 5, iclass 25, count 2 2006.258.01:31:34.05#ibcon#about to read 6, iclass 25, count 2 2006.258.01:31:34.05#ibcon#read 6, iclass 25, count 2 2006.258.01:31:34.05#ibcon#end of sib2, iclass 25, count 2 2006.258.01:31:34.05#ibcon#*mode == 0, iclass 25, count 2 2006.258.01:31:34.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.258.01:31:34.05#ibcon#[27=AT01-04\r\n] 2006.258.01:31:34.05#ibcon#*before write, iclass 25, count 2 2006.258.01:31:34.05#ibcon#enter sib2, iclass 25, count 2 2006.258.01:31:34.05#ibcon#flushed, iclass 25, count 2 2006.258.01:31:34.05#ibcon#about to write, iclass 25, count 2 2006.258.01:31:34.05#ibcon#wrote, iclass 25, count 2 2006.258.01:31:34.05#ibcon#about to read 3, iclass 25, count 2 2006.258.01:31:34.08#ibcon#read 3, iclass 25, count 2 2006.258.01:31:34.08#ibcon#about to read 4, iclass 25, count 2 2006.258.01:31:34.08#ibcon#read 4, iclass 25, count 2 2006.258.01:31:34.08#ibcon#about to read 5, iclass 25, count 2 2006.258.01:31:34.08#ibcon#read 5, iclass 25, count 2 2006.258.01:31:34.08#ibcon#about to read 6, iclass 25, count 2 2006.258.01:31:34.08#ibcon#read 6, iclass 25, count 2 2006.258.01:31:34.08#ibcon#end of sib2, iclass 25, count 2 2006.258.01:31:34.08#ibcon#*after write, iclass 25, count 2 2006.258.01:31:34.08#ibcon#*before return 0, iclass 25, count 2 2006.258.01:31:34.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:31:34.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:31:34.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.258.01:31:34.08#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:34.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:31:34.17#abcon#<5=/03 3.1 7.0 23.17 701015.9\r\n> 2006.258.01:31:34.19#abcon#{5=INTERFACE CLEAR} 2006.258.01:31:34.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:31:34.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:31:34.20#ibcon#enter wrdev, iclass 25, count 0 2006.258.01:31:34.20#ibcon#first serial, iclass 25, count 0 2006.258.01:31:34.20#ibcon#enter sib2, iclass 25, count 0 2006.258.01:31:34.20#ibcon#flushed, iclass 25, count 0 2006.258.01:31:34.20#ibcon#about to write, iclass 25, count 0 2006.258.01:31:34.20#ibcon#wrote, iclass 25, count 0 2006.258.01:31:34.20#ibcon#about to read 3, iclass 25, count 0 2006.258.01:31:34.22#ibcon#read 3, iclass 25, count 0 2006.258.01:31:34.22#ibcon#about to read 4, iclass 25, count 0 2006.258.01:31:34.22#ibcon#read 4, iclass 25, count 0 2006.258.01:31:34.22#ibcon#about to read 5, iclass 25, count 0 2006.258.01:31:34.22#ibcon#read 5, iclass 25, count 0 2006.258.01:31:34.22#ibcon#about to read 6, iclass 25, count 0 2006.258.01:31:34.22#ibcon#read 6, iclass 25, count 0 2006.258.01:31:34.22#ibcon#end of sib2, iclass 25, count 0 2006.258.01:31:34.22#ibcon#*mode == 0, iclass 25, count 0 2006.258.01:31:34.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.01:31:34.22#ibcon#[27=USB\r\n] 2006.258.01:31:34.22#ibcon#*before write, iclass 25, count 0 2006.258.01:31:34.22#ibcon#enter sib2, iclass 25, count 0 2006.258.01:31:34.22#ibcon#flushed, iclass 25, count 0 2006.258.01:31:34.22#ibcon#about to write, iclass 25, count 0 2006.258.01:31:34.22#ibcon#wrote, iclass 25, count 0 2006.258.01:31:34.22#ibcon#about to read 3, iclass 25, count 0 2006.258.01:31:34.25#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:31:34.25#ibcon#read 3, iclass 25, count 0 2006.258.01:31:34.25#ibcon#about to read 4, iclass 25, count 0 2006.258.01:31:34.25#ibcon#read 4, iclass 25, count 0 2006.258.01:31:34.25#ibcon#about to read 5, iclass 25, count 0 2006.258.01:31:34.25#ibcon#read 5, iclass 25, count 0 2006.258.01:31:34.25#ibcon#about to read 6, iclass 25, count 0 2006.258.01:31:34.25#ibcon#read 6, iclass 25, count 0 2006.258.01:31:34.25#ibcon#end of sib2, iclass 25, count 0 2006.258.01:31:34.25#ibcon#*after write, iclass 25, count 0 2006.258.01:31:34.25#ibcon#*before return 0, iclass 25, count 0 2006.258.01:31:34.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:31:34.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:31:34.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.01:31:34.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.01:31:34.25$vck44/vblo=2,634.99 2006.258.01:31:34.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.258.01:31:34.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.258.01:31:34.25#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:34.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:34.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:34.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:34.25#ibcon#enter wrdev, iclass 31, count 0 2006.258.01:31:34.25#ibcon#first serial, iclass 31, count 0 2006.258.01:31:34.25#ibcon#enter sib2, iclass 31, count 0 2006.258.01:31:34.25#ibcon#flushed, iclass 31, count 0 2006.258.01:31:34.25#ibcon#about to write, iclass 31, count 0 2006.258.01:31:34.25#ibcon#wrote, iclass 31, count 0 2006.258.01:31:34.25#ibcon#about to read 3, iclass 31, count 0 2006.258.01:31:34.27#ibcon#read 3, iclass 31, count 0 2006.258.01:31:34.27#ibcon#about to read 4, iclass 31, count 0 2006.258.01:31:34.27#ibcon#read 4, iclass 31, count 0 2006.258.01:31:34.27#ibcon#about to read 5, iclass 31, count 0 2006.258.01:31:34.27#ibcon#read 5, iclass 31, count 0 2006.258.01:31:34.27#ibcon#about to read 6, iclass 31, count 0 2006.258.01:31:34.27#ibcon#read 6, iclass 31, count 0 2006.258.01:31:34.27#ibcon#end of sib2, iclass 31, count 0 2006.258.01:31:34.27#ibcon#*mode == 0, iclass 31, count 0 2006.258.01:31:34.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.01:31:34.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.01:31:34.27#ibcon#*before write, iclass 31, count 0 2006.258.01:31:34.27#ibcon#enter sib2, iclass 31, count 0 2006.258.01:31:34.27#ibcon#flushed, iclass 31, count 0 2006.258.01:31:34.27#ibcon#about to write, iclass 31, count 0 2006.258.01:31:34.27#ibcon#wrote, iclass 31, count 0 2006.258.01:31:34.27#ibcon#about to read 3, iclass 31, count 0 2006.258.01:31:34.31#ibcon#read 3, iclass 31, count 0 2006.258.01:31:34.31#ibcon#about to read 4, iclass 31, count 0 2006.258.01:31:34.31#ibcon#read 4, iclass 31, count 0 2006.258.01:31:34.31#ibcon#about to read 5, iclass 31, count 0 2006.258.01:31:34.31#ibcon#read 5, iclass 31, count 0 2006.258.01:31:34.31#ibcon#about to read 6, iclass 31, count 0 2006.258.01:31:34.31#ibcon#read 6, iclass 31, count 0 2006.258.01:31:34.31#ibcon#end of sib2, iclass 31, count 0 2006.258.01:31:34.31#ibcon#*after write, iclass 31, count 0 2006.258.01:31:34.31#ibcon#*before return 0, iclass 31, count 0 2006.258.01:31:34.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:34.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:31:34.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.01:31:34.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.01:31:34.31$vck44/vb=2,5 2006.258.01:31:34.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.01:31:34.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.01:31:34.31#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:34.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:34.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:34.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:34.37#ibcon#enter wrdev, iclass 33, count 2 2006.258.01:31:34.37#ibcon#first serial, iclass 33, count 2 2006.258.01:31:34.37#ibcon#enter sib2, iclass 33, count 2 2006.258.01:31:34.37#ibcon#flushed, iclass 33, count 2 2006.258.01:31:34.37#ibcon#about to write, iclass 33, count 2 2006.258.01:31:34.37#ibcon#wrote, iclass 33, count 2 2006.258.01:31:34.37#ibcon#about to read 3, iclass 33, count 2 2006.258.01:31:34.39#ibcon#read 3, iclass 33, count 2 2006.258.01:31:34.39#ibcon#about to read 4, iclass 33, count 2 2006.258.01:31:34.39#ibcon#read 4, iclass 33, count 2 2006.258.01:31:34.39#ibcon#about to read 5, iclass 33, count 2 2006.258.01:31:34.39#ibcon#read 5, iclass 33, count 2 2006.258.01:31:34.39#ibcon#about to read 6, iclass 33, count 2 2006.258.01:31:34.39#ibcon#read 6, iclass 33, count 2 2006.258.01:31:34.39#ibcon#end of sib2, iclass 33, count 2 2006.258.01:31:34.39#ibcon#*mode == 0, iclass 33, count 2 2006.258.01:31:34.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.01:31:34.39#ibcon#[27=AT02-05\r\n] 2006.258.01:31:34.39#ibcon#*before write, iclass 33, count 2 2006.258.01:31:34.39#ibcon#enter sib2, iclass 33, count 2 2006.258.01:31:34.39#ibcon#flushed, iclass 33, count 2 2006.258.01:31:34.39#ibcon#about to write, iclass 33, count 2 2006.258.01:31:34.39#ibcon#wrote, iclass 33, count 2 2006.258.01:31:34.39#ibcon#about to read 3, iclass 33, count 2 2006.258.01:31:34.42#ibcon#read 3, iclass 33, count 2 2006.258.01:31:34.42#ibcon#about to read 4, iclass 33, count 2 2006.258.01:31:34.42#ibcon#read 4, iclass 33, count 2 2006.258.01:31:34.42#ibcon#about to read 5, iclass 33, count 2 2006.258.01:31:34.42#ibcon#read 5, iclass 33, count 2 2006.258.01:31:34.42#ibcon#about to read 6, iclass 33, count 2 2006.258.01:31:34.42#ibcon#read 6, iclass 33, count 2 2006.258.01:31:34.42#ibcon#end of sib2, iclass 33, count 2 2006.258.01:31:34.42#ibcon#*after write, iclass 33, count 2 2006.258.01:31:34.42#ibcon#*before return 0, iclass 33, count 2 2006.258.01:31:34.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:34.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:31:34.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.01:31:34.42#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:34.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:34.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:34.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:34.54#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:31:34.54#ibcon#first serial, iclass 33, count 0 2006.258.01:31:34.54#ibcon#enter sib2, iclass 33, count 0 2006.258.01:31:34.54#ibcon#flushed, iclass 33, count 0 2006.258.01:31:34.54#ibcon#about to write, iclass 33, count 0 2006.258.01:31:34.54#ibcon#wrote, iclass 33, count 0 2006.258.01:31:34.54#ibcon#about to read 3, iclass 33, count 0 2006.258.01:31:34.56#ibcon#read 3, iclass 33, count 0 2006.258.01:31:34.56#ibcon#about to read 4, iclass 33, count 0 2006.258.01:31:34.56#ibcon#read 4, iclass 33, count 0 2006.258.01:31:34.56#ibcon#about to read 5, iclass 33, count 0 2006.258.01:31:34.56#ibcon#read 5, iclass 33, count 0 2006.258.01:31:34.56#ibcon#about to read 6, iclass 33, count 0 2006.258.01:31:34.56#ibcon#read 6, iclass 33, count 0 2006.258.01:31:34.56#ibcon#end of sib2, iclass 33, count 0 2006.258.01:31:34.56#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:31:34.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:31:34.56#ibcon#[27=USB\r\n] 2006.258.01:31:34.56#ibcon#*before write, iclass 33, count 0 2006.258.01:31:34.56#ibcon#enter sib2, iclass 33, count 0 2006.258.01:31:34.56#ibcon#flushed, iclass 33, count 0 2006.258.01:31:34.56#ibcon#about to write, iclass 33, count 0 2006.258.01:31:34.56#ibcon#wrote, iclass 33, count 0 2006.258.01:31:34.56#ibcon#about to read 3, iclass 33, count 0 2006.258.01:31:34.59#ibcon#read 3, iclass 33, count 0 2006.258.01:31:34.59#ibcon#about to read 4, iclass 33, count 0 2006.258.01:31:34.59#ibcon#read 4, iclass 33, count 0 2006.258.01:31:34.59#ibcon#about to read 5, iclass 33, count 0 2006.258.01:31:34.59#ibcon#read 5, iclass 33, count 0 2006.258.01:31:34.59#ibcon#about to read 6, iclass 33, count 0 2006.258.01:31:34.59#ibcon#read 6, iclass 33, count 0 2006.258.01:31:34.59#ibcon#end of sib2, iclass 33, count 0 2006.258.01:31:34.59#ibcon#*after write, iclass 33, count 0 2006.258.01:31:34.59#ibcon#*before return 0, iclass 33, count 0 2006.258.01:31:34.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:34.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:31:34.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:31:34.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:31:34.59$vck44/vblo=3,649.99 2006.258.01:31:34.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.01:31:34.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.01:31:34.59#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:34.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:34.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:34.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:34.59#ibcon#enter wrdev, iclass 35, count 0 2006.258.01:31:34.59#ibcon#first serial, iclass 35, count 0 2006.258.01:31:34.59#ibcon#enter sib2, iclass 35, count 0 2006.258.01:31:34.59#ibcon#flushed, iclass 35, count 0 2006.258.01:31:34.59#ibcon#about to write, iclass 35, count 0 2006.258.01:31:34.59#ibcon#wrote, iclass 35, count 0 2006.258.01:31:34.59#ibcon#about to read 3, iclass 35, count 0 2006.258.01:31:34.61#ibcon#read 3, iclass 35, count 0 2006.258.01:31:34.61#ibcon#about to read 4, iclass 35, count 0 2006.258.01:31:34.61#ibcon#read 4, iclass 35, count 0 2006.258.01:31:34.61#ibcon#about to read 5, iclass 35, count 0 2006.258.01:31:34.61#ibcon#read 5, iclass 35, count 0 2006.258.01:31:34.61#ibcon#about to read 6, iclass 35, count 0 2006.258.01:31:34.61#ibcon#read 6, iclass 35, count 0 2006.258.01:31:34.61#ibcon#end of sib2, iclass 35, count 0 2006.258.01:31:34.61#ibcon#*mode == 0, iclass 35, count 0 2006.258.01:31:34.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.01:31:34.61#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.01:31:34.61#ibcon#*before write, iclass 35, count 0 2006.258.01:31:34.61#ibcon#enter sib2, iclass 35, count 0 2006.258.01:31:34.61#ibcon#flushed, iclass 35, count 0 2006.258.01:31:34.61#ibcon#about to write, iclass 35, count 0 2006.258.01:31:34.61#ibcon#wrote, iclass 35, count 0 2006.258.01:31:34.61#ibcon#about to read 3, iclass 35, count 0 2006.258.01:31:34.65#ibcon#read 3, iclass 35, count 0 2006.258.01:31:34.65#ibcon#about to read 4, iclass 35, count 0 2006.258.01:31:34.65#ibcon#read 4, iclass 35, count 0 2006.258.01:31:34.65#ibcon#about to read 5, iclass 35, count 0 2006.258.01:31:34.65#ibcon#read 5, iclass 35, count 0 2006.258.01:31:34.65#ibcon#about to read 6, iclass 35, count 0 2006.258.01:31:34.65#ibcon#read 6, iclass 35, count 0 2006.258.01:31:34.65#ibcon#end of sib2, iclass 35, count 0 2006.258.01:31:34.65#ibcon#*after write, iclass 35, count 0 2006.258.01:31:34.66#ibcon#*before return 0, iclass 35, count 0 2006.258.01:31:34.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:34.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:31:34.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.01:31:34.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.01:31:34.66$vck44/vb=3,4 2006.258.01:31:34.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.01:31:34.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.01:31:34.66#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:34.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:34.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:34.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:34.71#ibcon#enter wrdev, iclass 37, count 2 2006.258.01:31:34.71#ibcon#first serial, iclass 37, count 2 2006.258.01:31:34.71#ibcon#enter sib2, iclass 37, count 2 2006.258.01:31:34.71#ibcon#flushed, iclass 37, count 2 2006.258.01:31:34.71#ibcon#about to write, iclass 37, count 2 2006.258.01:31:34.71#ibcon#wrote, iclass 37, count 2 2006.258.01:31:34.71#ibcon#about to read 3, iclass 37, count 2 2006.258.01:31:34.73#ibcon#read 3, iclass 37, count 2 2006.258.01:31:34.73#ibcon#about to read 4, iclass 37, count 2 2006.258.01:31:34.73#ibcon#read 4, iclass 37, count 2 2006.258.01:31:34.73#ibcon#about to read 5, iclass 37, count 2 2006.258.01:31:34.73#ibcon#read 5, iclass 37, count 2 2006.258.01:31:34.73#ibcon#about to read 6, iclass 37, count 2 2006.258.01:31:34.73#ibcon#read 6, iclass 37, count 2 2006.258.01:31:34.73#ibcon#end of sib2, iclass 37, count 2 2006.258.01:31:34.73#ibcon#*mode == 0, iclass 37, count 2 2006.258.01:31:34.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.01:31:34.73#ibcon#[27=AT03-04\r\n] 2006.258.01:31:34.73#ibcon#*before write, iclass 37, count 2 2006.258.01:31:34.73#ibcon#enter sib2, iclass 37, count 2 2006.258.01:31:34.73#ibcon#flushed, iclass 37, count 2 2006.258.01:31:34.73#ibcon#about to write, iclass 37, count 2 2006.258.01:31:34.73#ibcon#wrote, iclass 37, count 2 2006.258.01:31:34.73#ibcon#about to read 3, iclass 37, count 2 2006.258.01:31:34.76#ibcon#read 3, iclass 37, count 2 2006.258.01:31:34.76#ibcon#about to read 4, iclass 37, count 2 2006.258.01:31:34.76#ibcon#read 4, iclass 37, count 2 2006.258.01:31:34.76#ibcon#about to read 5, iclass 37, count 2 2006.258.01:31:34.76#ibcon#read 5, iclass 37, count 2 2006.258.01:31:34.76#ibcon#about to read 6, iclass 37, count 2 2006.258.01:31:34.76#ibcon#read 6, iclass 37, count 2 2006.258.01:31:34.76#ibcon#end of sib2, iclass 37, count 2 2006.258.01:31:34.76#ibcon#*after write, iclass 37, count 2 2006.258.01:31:34.76#ibcon#*before return 0, iclass 37, count 2 2006.258.01:31:34.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:34.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:31:34.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.01:31:34.76#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:34.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:34.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:34.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:34.88#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:31:34.88#ibcon#first serial, iclass 37, count 0 2006.258.01:31:34.88#ibcon#enter sib2, iclass 37, count 0 2006.258.01:31:34.88#ibcon#flushed, iclass 37, count 0 2006.258.01:31:34.88#ibcon#about to write, iclass 37, count 0 2006.258.01:31:34.88#ibcon#wrote, iclass 37, count 0 2006.258.01:31:34.88#ibcon#about to read 3, iclass 37, count 0 2006.258.01:31:34.90#ibcon#read 3, iclass 37, count 0 2006.258.01:31:34.90#ibcon#about to read 4, iclass 37, count 0 2006.258.01:31:34.90#ibcon#read 4, iclass 37, count 0 2006.258.01:31:34.90#ibcon#about to read 5, iclass 37, count 0 2006.258.01:31:34.90#ibcon#read 5, iclass 37, count 0 2006.258.01:31:34.90#ibcon#about to read 6, iclass 37, count 0 2006.258.01:31:34.90#ibcon#read 6, iclass 37, count 0 2006.258.01:31:34.90#ibcon#end of sib2, iclass 37, count 0 2006.258.01:31:34.90#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:31:34.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:31:34.90#ibcon#[27=USB\r\n] 2006.258.01:31:34.90#ibcon#*before write, iclass 37, count 0 2006.258.01:31:34.90#ibcon#enter sib2, iclass 37, count 0 2006.258.01:31:34.90#ibcon#flushed, iclass 37, count 0 2006.258.01:31:34.90#ibcon#about to write, iclass 37, count 0 2006.258.01:31:34.90#ibcon#wrote, iclass 37, count 0 2006.258.01:31:34.90#ibcon#about to read 3, iclass 37, count 0 2006.258.01:31:34.93#ibcon#read 3, iclass 37, count 0 2006.258.01:31:34.93#ibcon#about to read 4, iclass 37, count 0 2006.258.01:31:34.93#ibcon#read 4, iclass 37, count 0 2006.258.01:31:34.93#ibcon#about to read 5, iclass 37, count 0 2006.258.01:31:34.93#ibcon#read 5, iclass 37, count 0 2006.258.01:31:34.93#ibcon#about to read 6, iclass 37, count 0 2006.258.01:31:34.93#ibcon#read 6, iclass 37, count 0 2006.258.01:31:34.93#ibcon#end of sib2, iclass 37, count 0 2006.258.01:31:34.93#ibcon#*after write, iclass 37, count 0 2006.258.01:31:34.93#ibcon#*before return 0, iclass 37, count 0 2006.258.01:31:34.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:34.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:31:34.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:31:34.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:31:34.93$vck44/vblo=4,679.99 2006.258.01:31:34.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.01:31:34.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.01:31:34.93#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:34.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:34.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:34.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:34.93#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:31:34.93#ibcon#first serial, iclass 39, count 0 2006.258.01:31:34.93#ibcon#enter sib2, iclass 39, count 0 2006.258.01:31:34.93#ibcon#flushed, iclass 39, count 0 2006.258.01:31:34.93#ibcon#about to write, iclass 39, count 0 2006.258.01:31:34.93#ibcon#wrote, iclass 39, count 0 2006.258.01:31:34.93#ibcon#about to read 3, iclass 39, count 0 2006.258.01:31:34.95#ibcon#read 3, iclass 39, count 0 2006.258.01:31:34.95#ibcon#about to read 4, iclass 39, count 0 2006.258.01:31:34.95#ibcon#read 4, iclass 39, count 0 2006.258.01:31:34.95#ibcon#about to read 5, iclass 39, count 0 2006.258.01:31:34.95#ibcon#read 5, iclass 39, count 0 2006.258.01:31:34.95#ibcon#about to read 6, iclass 39, count 0 2006.258.01:31:34.95#ibcon#read 6, iclass 39, count 0 2006.258.01:31:34.95#ibcon#end of sib2, iclass 39, count 0 2006.258.01:31:34.95#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:31:34.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:31:34.95#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.01:31:34.95#ibcon#*before write, iclass 39, count 0 2006.258.01:31:34.95#ibcon#enter sib2, iclass 39, count 0 2006.258.01:31:34.95#ibcon#flushed, iclass 39, count 0 2006.258.01:31:34.95#ibcon#about to write, iclass 39, count 0 2006.258.01:31:34.95#ibcon#wrote, iclass 39, count 0 2006.258.01:31:34.95#ibcon#about to read 3, iclass 39, count 0 2006.258.01:31:34.99#ibcon#read 3, iclass 39, count 0 2006.258.01:31:34.99#ibcon#about to read 4, iclass 39, count 0 2006.258.01:31:34.99#ibcon#read 4, iclass 39, count 0 2006.258.01:31:34.99#ibcon#about to read 5, iclass 39, count 0 2006.258.01:31:34.99#ibcon#read 5, iclass 39, count 0 2006.258.01:31:34.99#ibcon#about to read 6, iclass 39, count 0 2006.258.01:31:34.99#ibcon#read 6, iclass 39, count 0 2006.258.01:31:34.99#ibcon#end of sib2, iclass 39, count 0 2006.258.01:31:34.99#ibcon#*after write, iclass 39, count 0 2006.258.01:31:34.99#ibcon#*before return 0, iclass 39, count 0 2006.258.01:31:34.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:34.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:31:34.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:31:34.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:31:34.99$vck44/vb=4,5 2006.258.01:31:34.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.01:31:34.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.01:31:34.99#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:34.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:35.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:35.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:35.05#ibcon#enter wrdev, iclass 3, count 2 2006.258.01:31:35.05#ibcon#first serial, iclass 3, count 2 2006.258.01:31:35.05#ibcon#enter sib2, iclass 3, count 2 2006.258.01:31:35.05#ibcon#flushed, iclass 3, count 2 2006.258.01:31:35.05#ibcon#about to write, iclass 3, count 2 2006.258.01:31:35.05#ibcon#wrote, iclass 3, count 2 2006.258.01:31:35.05#ibcon#about to read 3, iclass 3, count 2 2006.258.01:31:35.07#ibcon#read 3, iclass 3, count 2 2006.258.01:31:35.07#ibcon#about to read 4, iclass 3, count 2 2006.258.01:31:35.07#ibcon#read 4, iclass 3, count 2 2006.258.01:31:35.07#ibcon#about to read 5, iclass 3, count 2 2006.258.01:31:35.07#ibcon#read 5, iclass 3, count 2 2006.258.01:31:35.07#ibcon#about to read 6, iclass 3, count 2 2006.258.01:31:35.07#ibcon#read 6, iclass 3, count 2 2006.258.01:31:35.07#ibcon#end of sib2, iclass 3, count 2 2006.258.01:31:35.07#ibcon#*mode == 0, iclass 3, count 2 2006.258.01:31:35.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.01:31:35.07#ibcon#[27=AT04-05\r\n] 2006.258.01:31:35.07#ibcon#*before write, iclass 3, count 2 2006.258.01:31:35.07#ibcon#enter sib2, iclass 3, count 2 2006.258.01:31:35.07#ibcon#flushed, iclass 3, count 2 2006.258.01:31:35.07#ibcon#about to write, iclass 3, count 2 2006.258.01:31:35.07#ibcon#wrote, iclass 3, count 2 2006.258.01:31:35.07#ibcon#about to read 3, iclass 3, count 2 2006.258.01:31:35.10#ibcon#read 3, iclass 3, count 2 2006.258.01:31:35.10#ibcon#about to read 4, iclass 3, count 2 2006.258.01:31:35.10#ibcon#read 4, iclass 3, count 2 2006.258.01:31:35.10#ibcon#about to read 5, iclass 3, count 2 2006.258.01:31:35.10#ibcon#read 5, iclass 3, count 2 2006.258.01:31:35.10#ibcon#about to read 6, iclass 3, count 2 2006.258.01:31:35.10#ibcon#read 6, iclass 3, count 2 2006.258.01:31:35.10#ibcon#end of sib2, iclass 3, count 2 2006.258.01:31:35.10#ibcon#*after write, iclass 3, count 2 2006.258.01:31:35.10#ibcon#*before return 0, iclass 3, count 2 2006.258.01:31:35.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:35.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:31:35.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.01:31:35.10#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:35.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:35.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:35.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:35.22#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:31:35.22#ibcon#first serial, iclass 3, count 0 2006.258.01:31:35.22#ibcon#enter sib2, iclass 3, count 0 2006.258.01:31:35.22#ibcon#flushed, iclass 3, count 0 2006.258.01:31:35.22#ibcon#about to write, iclass 3, count 0 2006.258.01:31:35.22#ibcon#wrote, iclass 3, count 0 2006.258.01:31:35.22#ibcon#about to read 3, iclass 3, count 0 2006.258.01:31:35.24#ibcon#read 3, iclass 3, count 0 2006.258.01:31:35.24#ibcon#about to read 4, iclass 3, count 0 2006.258.01:31:35.24#ibcon#read 4, iclass 3, count 0 2006.258.01:31:35.24#ibcon#about to read 5, iclass 3, count 0 2006.258.01:31:35.24#ibcon#read 5, iclass 3, count 0 2006.258.01:31:35.24#ibcon#about to read 6, iclass 3, count 0 2006.258.01:31:35.24#ibcon#read 6, iclass 3, count 0 2006.258.01:31:35.24#ibcon#end of sib2, iclass 3, count 0 2006.258.01:31:35.24#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:31:35.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:31:35.24#ibcon#[27=USB\r\n] 2006.258.01:31:35.24#ibcon#*before write, iclass 3, count 0 2006.258.01:31:35.24#ibcon#enter sib2, iclass 3, count 0 2006.258.01:31:35.24#ibcon#flushed, iclass 3, count 0 2006.258.01:31:35.24#ibcon#about to write, iclass 3, count 0 2006.258.01:31:35.24#ibcon#wrote, iclass 3, count 0 2006.258.01:31:35.24#ibcon#about to read 3, iclass 3, count 0 2006.258.01:31:35.27#ibcon#read 3, iclass 3, count 0 2006.258.01:31:35.27#ibcon#about to read 4, iclass 3, count 0 2006.258.01:31:35.27#ibcon#read 4, iclass 3, count 0 2006.258.01:31:35.27#ibcon#about to read 5, iclass 3, count 0 2006.258.01:31:35.27#ibcon#read 5, iclass 3, count 0 2006.258.01:31:35.27#ibcon#about to read 6, iclass 3, count 0 2006.258.01:31:35.27#ibcon#read 6, iclass 3, count 0 2006.258.01:31:35.27#ibcon#end of sib2, iclass 3, count 0 2006.258.01:31:35.27#ibcon#*after write, iclass 3, count 0 2006.258.01:31:35.27#ibcon#*before return 0, iclass 3, count 0 2006.258.01:31:35.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:35.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:31:35.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:31:35.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:31:35.27$vck44/vblo=5,709.99 2006.258.01:31:35.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.01:31:35.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.01:31:35.27#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:35.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:35.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:35.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:35.27#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:31:35.27#ibcon#first serial, iclass 5, count 0 2006.258.01:31:35.27#ibcon#enter sib2, iclass 5, count 0 2006.258.01:31:35.27#ibcon#flushed, iclass 5, count 0 2006.258.01:31:35.27#ibcon#about to write, iclass 5, count 0 2006.258.01:31:35.27#ibcon#wrote, iclass 5, count 0 2006.258.01:31:35.27#ibcon#about to read 3, iclass 5, count 0 2006.258.01:31:35.29#ibcon#read 3, iclass 5, count 0 2006.258.01:31:35.29#ibcon#about to read 4, iclass 5, count 0 2006.258.01:31:35.29#ibcon#read 4, iclass 5, count 0 2006.258.01:31:35.29#ibcon#about to read 5, iclass 5, count 0 2006.258.01:31:35.29#ibcon#read 5, iclass 5, count 0 2006.258.01:31:35.29#ibcon#about to read 6, iclass 5, count 0 2006.258.01:31:35.29#ibcon#read 6, iclass 5, count 0 2006.258.01:31:35.29#ibcon#end of sib2, iclass 5, count 0 2006.258.01:31:35.29#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:31:35.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:31:35.29#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.01:31:35.29#ibcon#*before write, iclass 5, count 0 2006.258.01:31:35.29#ibcon#enter sib2, iclass 5, count 0 2006.258.01:31:35.29#ibcon#flushed, iclass 5, count 0 2006.258.01:31:35.29#ibcon#about to write, iclass 5, count 0 2006.258.01:31:35.29#ibcon#wrote, iclass 5, count 0 2006.258.01:31:35.29#ibcon#about to read 3, iclass 5, count 0 2006.258.01:31:35.33#ibcon#read 3, iclass 5, count 0 2006.258.01:31:35.33#ibcon#about to read 4, iclass 5, count 0 2006.258.01:31:35.33#ibcon#read 4, iclass 5, count 0 2006.258.01:31:35.33#ibcon#about to read 5, iclass 5, count 0 2006.258.01:31:35.33#ibcon#read 5, iclass 5, count 0 2006.258.01:31:35.33#ibcon#about to read 6, iclass 5, count 0 2006.258.01:31:35.33#ibcon#read 6, iclass 5, count 0 2006.258.01:31:35.33#ibcon#end of sib2, iclass 5, count 0 2006.258.01:31:35.33#ibcon#*after write, iclass 5, count 0 2006.258.01:31:35.33#ibcon#*before return 0, iclass 5, count 0 2006.258.01:31:35.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:35.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:31:35.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:31:35.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:31:35.33$vck44/vb=5,4 2006.258.01:31:35.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.01:31:35.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.01:31:35.33#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:35.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:35.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:35.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:35.39#ibcon#enter wrdev, iclass 7, count 2 2006.258.01:31:35.39#ibcon#first serial, iclass 7, count 2 2006.258.01:31:35.39#ibcon#enter sib2, iclass 7, count 2 2006.258.01:31:35.39#ibcon#flushed, iclass 7, count 2 2006.258.01:31:35.39#ibcon#about to write, iclass 7, count 2 2006.258.01:31:35.39#ibcon#wrote, iclass 7, count 2 2006.258.01:31:35.39#ibcon#about to read 3, iclass 7, count 2 2006.258.01:31:35.41#ibcon#read 3, iclass 7, count 2 2006.258.01:31:35.41#ibcon#about to read 4, iclass 7, count 2 2006.258.01:31:35.41#ibcon#read 4, iclass 7, count 2 2006.258.01:31:35.41#ibcon#about to read 5, iclass 7, count 2 2006.258.01:31:35.41#ibcon#read 5, iclass 7, count 2 2006.258.01:31:35.41#ibcon#about to read 6, iclass 7, count 2 2006.258.01:31:35.41#ibcon#read 6, iclass 7, count 2 2006.258.01:31:35.41#ibcon#end of sib2, iclass 7, count 2 2006.258.01:31:35.41#ibcon#*mode == 0, iclass 7, count 2 2006.258.01:31:35.41#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.01:31:35.41#ibcon#[27=AT05-04\r\n] 2006.258.01:31:35.41#ibcon#*before write, iclass 7, count 2 2006.258.01:31:35.41#ibcon#enter sib2, iclass 7, count 2 2006.258.01:31:35.41#ibcon#flushed, iclass 7, count 2 2006.258.01:31:35.41#ibcon#about to write, iclass 7, count 2 2006.258.01:31:35.41#ibcon#wrote, iclass 7, count 2 2006.258.01:31:35.41#ibcon#about to read 3, iclass 7, count 2 2006.258.01:31:35.44#ibcon#read 3, iclass 7, count 2 2006.258.01:31:35.44#ibcon#about to read 4, iclass 7, count 2 2006.258.01:31:35.44#ibcon#read 4, iclass 7, count 2 2006.258.01:31:35.44#ibcon#about to read 5, iclass 7, count 2 2006.258.01:31:35.44#ibcon#read 5, iclass 7, count 2 2006.258.01:31:35.44#ibcon#about to read 6, iclass 7, count 2 2006.258.01:31:35.44#ibcon#read 6, iclass 7, count 2 2006.258.01:31:35.44#ibcon#end of sib2, iclass 7, count 2 2006.258.01:31:35.44#ibcon#*after write, iclass 7, count 2 2006.258.01:31:35.44#ibcon#*before return 0, iclass 7, count 2 2006.258.01:31:35.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:35.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:31:35.44#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.01:31:35.44#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:35.44#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:35.56#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:35.56#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:35.56#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:31:35.56#ibcon#first serial, iclass 7, count 0 2006.258.01:31:35.56#ibcon#enter sib2, iclass 7, count 0 2006.258.01:31:35.56#ibcon#flushed, iclass 7, count 0 2006.258.01:31:35.56#ibcon#about to write, iclass 7, count 0 2006.258.01:31:35.56#ibcon#wrote, iclass 7, count 0 2006.258.01:31:35.56#ibcon#about to read 3, iclass 7, count 0 2006.258.01:31:35.58#ibcon#read 3, iclass 7, count 0 2006.258.01:31:35.58#ibcon#about to read 4, iclass 7, count 0 2006.258.01:31:35.58#ibcon#read 4, iclass 7, count 0 2006.258.01:31:35.58#ibcon#about to read 5, iclass 7, count 0 2006.258.01:31:35.58#ibcon#read 5, iclass 7, count 0 2006.258.01:31:35.58#ibcon#about to read 6, iclass 7, count 0 2006.258.01:31:35.58#ibcon#read 6, iclass 7, count 0 2006.258.01:31:35.58#ibcon#end of sib2, iclass 7, count 0 2006.258.01:31:35.58#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:31:35.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:31:35.58#ibcon#[27=USB\r\n] 2006.258.01:31:35.58#ibcon#*before write, iclass 7, count 0 2006.258.01:31:35.58#ibcon#enter sib2, iclass 7, count 0 2006.258.01:31:35.58#ibcon#flushed, iclass 7, count 0 2006.258.01:31:35.58#ibcon#about to write, iclass 7, count 0 2006.258.01:31:35.58#ibcon#wrote, iclass 7, count 0 2006.258.01:31:35.58#ibcon#about to read 3, iclass 7, count 0 2006.258.01:31:35.61#ibcon#read 3, iclass 7, count 0 2006.258.01:31:35.61#ibcon#about to read 4, iclass 7, count 0 2006.258.01:31:35.61#ibcon#read 4, iclass 7, count 0 2006.258.01:31:35.61#ibcon#about to read 5, iclass 7, count 0 2006.258.01:31:35.61#ibcon#read 5, iclass 7, count 0 2006.258.01:31:35.61#ibcon#about to read 6, iclass 7, count 0 2006.258.01:31:35.61#ibcon#read 6, iclass 7, count 0 2006.258.01:31:35.61#ibcon#end of sib2, iclass 7, count 0 2006.258.01:31:35.61#ibcon#*after write, iclass 7, count 0 2006.258.01:31:35.61#ibcon#*before return 0, iclass 7, count 0 2006.258.01:31:35.61#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:35.61#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:31:35.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:31:35.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:31:35.61$vck44/vblo=6,719.99 2006.258.01:31:35.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.01:31:35.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.01:31:35.61#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:35.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:35.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:35.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:35.61#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:31:35.61#ibcon#first serial, iclass 11, count 0 2006.258.01:31:35.61#ibcon#enter sib2, iclass 11, count 0 2006.258.01:31:35.61#ibcon#flushed, iclass 11, count 0 2006.258.01:31:35.61#ibcon#about to write, iclass 11, count 0 2006.258.01:31:35.61#ibcon#wrote, iclass 11, count 0 2006.258.01:31:35.61#ibcon#about to read 3, iclass 11, count 0 2006.258.01:31:35.63#ibcon#read 3, iclass 11, count 0 2006.258.01:31:35.63#ibcon#about to read 4, iclass 11, count 0 2006.258.01:31:35.63#ibcon#read 4, iclass 11, count 0 2006.258.01:31:35.63#ibcon#about to read 5, iclass 11, count 0 2006.258.01:31:35.63#ibcon#read 5, iclass 11, count 0 2006.258.01:31:35.63#ibcon#about to read 6, iclass 11, count 0 2006.258.01:31:35.63#ibcon#read 6, iclass 11, count 0 2006.258.01:31:35.63#ibcon#end of sib2, iclass 11, count 0 2006.258.01:31:35.63#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:31:35.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:31:35.63#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.01:31:35.63#ibcon#*before write, iclass 11, count 0 2006.258.01:31:35.63#ibcon#enter sib2, iclass 11, count 0 2006.258.01:31:35.63#ibcon#flushed, iclass 11, count 0 2006.258.01:31:35.63#ibcon#about to write, iclass 11, count 0 2006.258.01:31:35.63#ibcon#wrote, iclass 11, count 0 2006.258.01:31:35.63#ibcon#about to read 3, iclass 11, count 0 2006.258.01:31:35.67#ibcon#read 3, iclass 11, count 0 2006.258.01:31:35.67#ibcon#about to read 4, iclass 11, count 0 2006.258.01:31:35.67#ibcon#read 4, iclass 11, count 0 2006.258.01:31:35.67#ibcon#about to read 5, iclass 11, count 0 2006.258.01:31:35.67#ibcon#read 5, iclass 11, count 0 2006.258.01:31:35.67#ibcon#about to read 6, iclass 11, count 0 2006.258.01:31:35.67#ibcon#read 6, iclass 11, count 0 2006.258.01:31:35.67#ibcon#end of sib2, iclass 11, count 0 2006.258.01:31:35.67#ibcon#*after write, iclass 11, count 0 2006.258.01:31:35.67#ibcon#*before return 0, iclass 11, count 0 2006.258.01:31:35.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:35.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:31:35.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:31:35.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:31:35.67$vck44/vb=6,4 2006.258.01:31:35.67#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.01:31:35.67#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.01:31:35.67#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:35.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:35.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:35.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:35.73#ibcon#enter wrdev, iclass 13, count 2 2006.258.01:31:35.73#ibcon#first serial, iclass 13, count 2 2006.258.01:31:35.73#ibcon#enter sib2, iclass 13, count 2 2006.258.01:31:35.73#ibcon#flushed, iclass 13, count 2 2006.258.01:31:35.73#ibcon#about to write, iclass 13, count 2 2006.258.01:31:35.73#ibcon#wrote, iclass 13, count 2 2006.258.01:31:35.73#ibcon#about to read 3, iclass 13, count 2 2006.258.01:31:35.75#ibcon#read 3, iclass 13, count 2 2006.258.01:31:35.75#ibcon#about to read 4, iclass 13, count 2 2006.258.01:31:35.75#ibcon#read 4, iclass 13, count 2 2006.258.01:31:35.75#ibcon#about to read 5, iclass 13, count 2 2006.258.01:31:35.75#ibcon#read 5, iclass 13, count 2 2006.258.01:31:35.75#ibcon#about to read 6, iclass 13, count 2 2006.258.01:31:35.75#ibcon#read 6, iclass 13, count 2 2006.258.01:31:35.75#ibcon#end of sib2, iclass 13, count 2 2006.258.01:31:35.75#ibcon#*mode == 0, iclass 13, count 2 2006.258.01:31:35.75#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.01:31:35.75#ibcon#[27=AT06-04\r\n] 2006.258.01:31:35.75#ibcon#*before write, iclass 13, count 2 2006.258.01:31:35.75#ibcon#enter sib2, iclass 13, count 2 2006.258.01:31:35.75#ibcon#flushed, iclass 13, count 2 2006.258.01:31:35.75#ibcon#about to write, iclass 13, count 2 2006.258.01:31:35.75#ibcon#wrote, iclass 13, count 2 2006.258.01:31:35.75#ibcon#about to read 3, iclass 13, count 2 2006.258.01:31:35.78#ibcon#read 3, iclass 13, count 2 2006.258.01:31:35.78#ibcon#about to read 4, iclass 13, count 2 2006.258.01:31:35.78#ibcon#read 4, iclass 13, count 2 2006.258.01:31:35.78#ibcon#about to read 5, iclass 13, count 2 2006.258.01:31:35.78#ibcon#read 5, iclass 13, count 2 2006.258.01:31:35.78#ibcon#about to read 6, iclass 13, count 2 2006.258.01:31:35.78#ibcon#read 6, iclass 13, count 2 2006.258.01:31:35.78#ibcon#end of sib2, iclass 13, count 2 2006.258.01:31:35.78#ibcon#*after write, iclass 13, count 2 2006.258.01:31:35.78#ibcon#*before return 0, iclass 13, count 2 2006.258.01:31:35.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:35.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:31:35.78#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.01:31:35.78#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:35.78#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:35.90#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:35.90#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:35.90#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:31:35.90#ibcon#first serial, iclass 13, count 0 2006.258.01:31:35.90#ibcon#enter sib2, iclass 13, count 0 2006.258.01:31:35.90#ibcon#flushed, iclass 13, count 0 2006.258.01:31:35.90#ibcon#about to write, iclass 13, count 0 2006.258.01:31:35.90#ibcon#wrote, iclass 13, count 0 2006.258.01:31:35.90#ibcon#about to read 3, iclass 13, count 0 2006.258.01:31:35.92#ibcon#read 3, iclass 13, count 0 2006.258.01:31:35.92#ibcon#about to read 4, iclass 13, count 0 2006.258.01:31:35.92#ibcon#read 4, iclass 13, count 0 2006.258.01:31:35.92#ibcon#about to read 5, iclass 13, count 0 2006.258.01:31:35.92#ibcon#read 5, iclass 13, count 0 2006.258.01:31:35.92#ibcon#about to read 6, iclass 13, count 0 2006.258.01:31:35.92#ibcon#read 6, iclass 13, count 0 2006.258.01:31:35.92#ibcon#end of sib2, iclass 13, count 0 2006.258.01:31:35.92#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:31:35.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:31:35.92#ibcon#[27=USB\r\n] 2006.258.01:31:35.92#ibcon#*before write, iclass 13, count 0 2006.258.01:31:35.92#ibcon#enter sib2, iclass 13, count 0 2006.258.01:31:35.92#ibcon#flushed, iclass 13, count 0 2006.258.01:31:35.92#ibcon#about to write, iclass 13, count 0 2006.258.01:31:35.92#ibcon#wrote, iclass 13, count 0 2006.258.01:31:35.92#ibcon#about to read 3, iclass 13, count 0 2006.258.01:31:35.95#ibcon#read 3, iclass 13, count 0 2006.258.01:31:35.95#ibcon#about to read 4, iclass 13, count 0 2006.258.01:31:35.95#ibcon#read 4, iclass 13, count 0 2006.258.01:31:35.95#ibcon#about to read 5, iclass 13, count 0 2006.258.01:31:35.95#ibcon#read 5, iclass 13, count 0 2006.258.01:31:35.95#ibcon#about to read 6, iclass 13, count 0 2006.258.01:31:35.95#ibcon#read 6, iclass 13, count 0 2006.258.01:31:35.95#ibcon#end of sib2, iclass 13, count 0 2006.258.01:31:35.95#ibcon#*after write, iclass 13, count 0 2006.258.01:31:35.95#ibcon#*before return 0, iclass 13, count 0 2006.258.01:31:35.95#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:35.95#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:31:35.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:31:35.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:31:35.95$vck44/vblo=7,734.99 2006.258.01:31:35.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.01:31:35.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.01:31:35.95#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:35.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:35.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:35.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:35.95#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:31:35.95#ibcon#first serial, iclass 15, count 0 2006.258.01:31:35.95#ibcon#enter sib2, iclass 15, count 0 2006.258.01:31:35.95#ibcon#flushed, iclass 15, count 0 2006.258.01:31:35.95#ibcon#about to write, iclass 15, count 0 2006.258.01:31:35.95#ibcon#wrote, iclass 15, count 0 2006.258.01:31:35.95#ibcon#about to read 3, iclass 15, count 0 2006.258.01:31:35.97#ibcon#read 3, iclass 15, count 0 2006.258.01:31:35.97#ibcon#about to read 4, iclass 15, count 0 2006.258.01:31:35.97#ibcon#read 4, iclass 15, count 0 2006.258.01:31:35.97#ibcon#about to read 5, iclass 15, count 0 2006.258.01:31:35.97#ibcon#read 5, iclass 15, count 0 2006.258.01:31:35.97#ibcon#about to read 6, iclass 15, count 0 2006.258.01:31:35.97#ibcon#read 6, iclass 15, count 0 2006.258.01:31:35.97#ibcon#end of sib2, iclass 15, count 0 2006.258.01:31:35.97#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:31:35.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:31:35.97#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.01:31:35.97#ibcon#*before write, iclass 15, count 0 2006.258.01:31:35.97#ibcon#enter sib2, iclass 15, count 0 2006.258.01:31:35.97#ibcon#flushed, iclass 15, count 0 2006.258.01:31:35.97#ibcon#about to write, iclass 15, count 0 2006.258.01:31:35.97#ibcon#wrote, iclass 15, count 0 2006.258.01:31:35.97#ibcon#about to read 3, iclass 15, count 0 2006.258.01:31:36.01#ibcon#read 3, iclass 15, count 0 2006.258.01:31:36.01#ibcon#about to read 4, iclass 15, count 0 2006.258.01:31:36.01#ibcon#read 4, iclass 15, count 0 2006.258.01:31:36.01#ibcon#about to read 5, iclass 15, count 0 2006.258.01:31:36.01#ibcon#read 5, iclass 15, count 0 2006.258.01:31:36.01#ibcon#about to read 6, iclass 15, count 0 2006.258.01:31:36.01#ibcon#read 6, iclass 15, count 0 2006.258.01:31:36.01#ibcon#end of sib2, iclass 15, count 0 2006.258.01:31:36.01#ibcon#*after write, iclass 15, count 0 2006.258.01:31:36.01#ibcon#*before return 0, iclass 15, count 0 2006.258.01:31:36.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:36.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:31:36.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:31:36.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:31:36.01$vck44/vb=7,4 2006.258.01:31:36.01#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.01:31:36.01#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.01:31:36.01#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:36.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:36.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:36.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:36.07#ibcon#enter wrdev, iclass 17, count 2 2006.258.01:31:36.07#ibcon#first serial, iclass 17, count 2 2006.258.01:31:36.07#ibcon#enter sib2, iclass 17, count 2 2006.258.01:31:36.07#ibcon#flushed, iclass 17, count 2 2006.258.01:31:36.07#ibcon#about to write, iclass 17, count 2 2006.258.01:31:36.07#ibcon#wrote, iclass 17, count 2 2006.258.01:31:36.07#ibcon#about to read 3, iclass 17, count 2 2006.258.01:31:36.09#ibcon#read 3, iclass 17, count 2 2006.258.01:31:36.09#ibcon#about to read 4, iclass 17, count 2 2006.258.01:31:36.09#ibcon#read 4, iclass 17, count 2 2006.258.01:31:36.09#ibcon#about to read 5, iclass 17, count 2 2006.258.01:31:36.09#ibcon#read 5, iclass 17, count 2 2006.258.01:31:36.09#ibcon#about to read 6, iclass 17, count 2 2006.258.01:31:36.09#ibcon#read 6, iclass 17, count 2 2006.258.01:31:36.09#ibcon#end of sib2, iclass 17, count 2 2006.258.01:31:36.09#ibcon#*mode == 0, iclass 17, count 2 2006.258.01:31:36.09#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.01:31:36.09#ibcon#[27=AT07-04\r\n] 2006.258.01:31:36.09#ibcon#*before write, iclass 17, count 2 2006.258.01:31:36.09#ibcon#enter sib2, iclass 17, count 2 2006.258.01:31:36.09#ibcon#flushed, iclass 17, count 2 2006.258.01:31:36.09#ibcon#about to write, iclass 17, count 2 2006.258.01:31:36.09#ibcon#wrote, iclass 17, count 2 2006.258.01:31:36.09#ibcon#about to read 3, iclass 17, count 2 2006.258.01:31:36.12#ibcon#read 3, iclass 17, count 2 2006.258.01:31:36.12#ibcon#about to read 4, iclass 17, count 2 2006.258.01:31:36.12#ibcon#read 4, iclass 17, count 2 2006.258.01:31:36.12#ibcon#about to read 5, iclass 17, count 2 2006.258.01:31:36.12#ibcon#read 5, iclass 17, count 2 2006.258.01:31:36.12#ibcon#about to read 6, iclass 17, count 2 2006.258.01:31:36.12#ibcon#read 6, iclass 17, count 2 2006.258.01:31:36.12#ibcon#end of sib2, iclass 17, count 2 2006.258.01:31:36.12#ibcon#*after write, iclass 17, count 2 2006.258.01:31:36.12#ibcon#*before return 0, iclass 17, count 2 2006.258.01:31:36.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:36.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:31:36.12#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.01:31:36.12#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:36.12#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:36.24#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:36.24#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:36.24#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:31:36.24#ibcon#first serial, iclass 17, count 0 2006.258.01:31:36.24#ibcon#enter sib2, iclass 17, count 0 2006.258.01:31:36.24#ibcon#flushed, iclass 17, count 0 2006.258.01:31:36.24#ibcon#about to write, iclass 17, count 0 2006.258.01:31:36.24#ibcon#wrote, iclass 17, count 0 2006.258.01:31:36.24#ibcon#about to read 3, iclass 17, count 0 2006.258.01:31:36.26#ibcon#read 3, iclass 17, count 0 2006.258.01:31:36.26#ibcon#about to read 4, iclass 17, count 0 2006.258.01:31:36.26#ibcon#read 4, iclass 17, count 0 2006.258.01:31:36.26#ibcon#about to read 5, iclass 17, count 0 2006.258.01:31:36.26#ibcon#read 5, iclass 17, count 0 2006.258.01:31:36.26#ibcon#about to read 6, iclass 17, count 0 2006.258.01:31:36.26#ibcon#read 6, iclass 17, count 0 2006.258.01:31:36.26#ibcon#end of sib2, iclass 17, count 0 2006.258.01:31:36.26#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:31:36.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:31:36.26#ibcon#[27=USB\r\n] 2006.258.01:31:36.26#ibcon#*before write, iclass 17, count 0 2006.258.01:31:36.26#ibcon#enter sib2, iclass 17, count 0 2006.258.01:31:36.26#ibcon#flushed, iclass 17, count 0 2006.258.01:31:36.26#ibcon#about to write, iclass 17, count 0 2006.258.01:31:36.26#ibcon#wrote, iclass 17, count 0 2006.258.01:31:36.26#ibcon#about to read 3, iclass 17, count 0 2006.258.01:31:36.29#ibcon#read 3, iclass 17, count 0 2006.258.01:31:36.29#ibcon#about to read 4, iclass 17, count 0 2006.258.01:31:36.29#ibcon#read 4, iclass 17, count 0 2006.258.01:31:36.29#ibcon#about to read 5, iclass 17, count 0 2006.258.01:31:36.29#ibcon#read 5, iclass 17, count 0 2006.258.01:31:36.29#ibcon#about to read 6, iclass 17, count 0 2006.258.01:31:36.29#ibcon#read 6, iclass 17, count 0 2006.258.01:31:36.29#ibcon#end of sib2, iclass 17, count 0 2006.258.01:31:36.29#ibcon#*after write, iclass 17, count 0 2006.258.01:31:36.29#ibcon#*before return 0, iclass 17, count 0 2006.258.01:31:36.29#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:36.29#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:31:36.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:31:36.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:31:36.29$vck44/vblo=8,744.99 2006.258.01:31:36.29#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.01:31:36.29#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.01:31:36.29#ibcon#ireg 17 cls_cnt 0 2006.258.01:31:36.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:36.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:36.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:36.29#ibcon#enter wrdev, iclass 19, count 0 2006.258.01:31:36.29#ibcon#first serial, iclass 19, count 0 2006.258.01:31:36.29#ibcon#enter sib2, iclass 19, count 0 2006.258.01:31:36.29#ibcon#flushed, iclass 19, count 0 2006.258.01:31:36.29#ibcon#about to write, iclass 19, count 0 2006.258.01:31:36.29#ibcon#wrote, iclass 19, count 0 2006.258.01:31:36.29#ibcon#about to read 3, iclass 19, count 0 2006.258.01:31:36.31#ibcon#read 3, iclass 19, count 0 2006.258.01:31:36.31#ibcon#about to read 4, iclass 19, count 0 2006.258.01:31:36.31#ibcon#read 4, iclass 19, count 0 2006.258.01:31:36.31#ibcon#about to read 5, iclass 19, count 0 2006.258.01:31:36.31#ibcon#read 5, iclass 19, count 0 2006.258.01:31:36.31#ibcon#about to read 6, iclass 19, count 0 2006.258.01:31:36.31#ibcon#read 6, iclass 19, count 0 2006.258.01:31:36.31#ibcon#end of sib2, iclass 19, count 0 2006.258.01:31:36.31#ibcon#*mode == 0, iclass 19, count 0 2006.258.01:31:36.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.01:31:36.31#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.01:31:36.31#ibcon#*before write, iclass 19, count 0 2006.258.01:31:36.31#ibcon#enter sib2, iclass 19, count 0 2006.258.01:31:36.31#ibcon#flushed, iclass 19, count 0 2006.258.01:31:36.31#ibcon#about to write, iclass 19, count 0 2006.258.01:31:36.31#ibcon#wrote, iclass 19, count 0 2006.258.01:31:36.31#ibcon#about to read 3, iclass 19, count 0 2006.258.01:31:36.35#ibcon#read 3, iclass 19, count 0 2006.258.01:31:36.35#ibcon#about to read 4, iclass 19, count 0 2006.258.01:31:36.35#ibcon#read 4, iclass 19, count 0 2006.258.01:31:36.35#ibcon#about to read 5, iclass 19, count 0 2006.258.01:31:36.35#ibcon#read 5, iclass 19, count 0 2006.258.01:31:36.35#ibcon#about to read 6, iclass 19, count 0 2006.258.01:31:36.35#ibcon#read 6, iclass 19, count 0 2006.258.01:31:36.35#ibcon#end of sib2, iclass 19, count 0 2006.258.01:31:36.35#ibcon#*after write, iclass 19, count 0 2006.258.01:31:36.35#ibcon#*before return 0, iclass 19, count 0 2006.258.01:31:36.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:36.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:31:36.35#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.01:31:36.35#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.01:31:36.35$vck44/vb=8,4 2006.258.01:31:36.35#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.01:31:36.35#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.01:31:36.35#ibcon#ireg 11 cls_cnt 2 2006.258.01:31:36.35#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:36.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:36.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:36.41#ibcon#enter wrdev, iclass 21, count 2 2006.258.01:31:36.41#ibcon#first serial, iclass 21, count 2 2006.258.01:31:36.41#ibcon#enter sib2, iclass 21, count 2 2006.258.01:31:36.41#ibcon#flushed, iclass 21, count 2 2006.258.01:31:36.41#ibcon#about to write, iclass 21, count 2 2006.258.01:31:36.41#ibcon#wrote, iclass 21, count 2 2006.258.01:31:36.41#ibcon#about to read 3, iclass 21, count 2 2006.258.01:31:36.43#ibcon#read 3, iclass 21, count 2 2006.258.01:31:36.43#ibcon#about to read 4, iclass 21, count 2 2006.258.01:31:36.43#ibcon#read 4, iclass 21, count 2 2006.258.01:31:36.43#ibcon#about to read 5, iclass 21, count 2 2006.258.01:31:36.43#ibcon#read 5, iclass 21, count 2 2006.258.01:31:36.43#ibcon#about to read 6, iclass 21, count 2 2006.258.01:31:36.43#ibcon#read 6, iclass 21, count 2 2006.258.01:31:36.43#ibcon#end of sib2, iclass 21, count 2 2006.258.01:31:36.43#ibcon#*mode == 0, iclass 21, count 2 2006.258.01:31:36.43#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.01:31:36.43#ibcon#[27=AT08-04\r\n] 2006.258.01:31:36.43#ibcon#*before write, iclass 21, count 2 2006.258.01:31:36.43#ibcon#enter sib2, iclass 21, count 2 2006.258.01:31:36.43#ibcon#flushed, iclass 21, count 2 2006.258.01:31:36.43#ibcon#about to write, iclass 21, count 2 2006.258.01:31:36.43#ibcon#wrote, iclass 21, count 2 2006.258.01:31:36.43#ibcon#about to read 3, iclass 21, count 2 2006.258.01:31:36.46#ibcon#read 3, iclass 21, count 2 2006.258.01:31:36.46#ibcon#about to read 4, iclass 21, count 2 2006.258.01:31:36.46#ibcon#read 4, iclass 21, count 2 2006.258.01:31:36.46#ibcon#about to read 5, iclass 21, count 2 2006.258.01:31:36.46#ibcon#read 5, iclass 21, count 2 2006.258.01:31:36.46#ibcon#about to read 6, iclass 21, count 2 2006.258.01:31:36.46#ibcon#read 6, iclass 21, count 2 2006.258.01:31:36.46#ibcon#end of sib2, iclass 21, count 2 2006.258.01:31:36.46#ibcon#*after write, iclass 21, count 2 2006.258.01:31:36.46#ibcon#*before return 0, iclass 21, count 2 2006.258.01:31:36.46#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:36.46#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:31:36.46#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.01:31:36.46#ibcon#ireg 7 cls_cnt 0 2006.258.01:31:36.46#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:36.58#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:36.58#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:36.58#ibcon#enter wrdev, iclass 21, count 0 2006.258.01:31:36.58#ibcon#first serial, iclass 21, count 0 2006.258.01:31:36.58#ibcon#enter sib2, iclass 21, count 0 2006.258.01:31:36.58#ibcon#flushed, iclass 21, count 0 2006.258.01:31:36.58#ibcon#about to write, iclass 21, count 0 2006.258.01:31:36.58#ibcon#wrote, iclass 21, count 0 2006.258.01:31:36.58#ibcon#about to read 3, iclass 21, count 0 2006.258.01:31:36.60#ibcon#read 3, iclass 21, count 0 2006.258.01:31:36.60#ibcon#about to read 4, iclass 21, count 0 2006.258.01:31:36.60#ibcon#read 4, iclass 21, count 0 2006.258.01:31:36.60#ibcon#about to read 5, iclass 21, count 0 2006.258.01:31:36.60#ibcon#read 5, iclass 21, count 0 2006.258.01:31:36.60#ibcon#about to read 6, iclass 21, count 0 2006.258.01:31:36.60#ibcon#read 6, iclass 21, count 0 2006.258.01:31:36.60#ibcon#end of sib2, iclass 21, count 0 2006.258.01:31:36.60#ibcon#*mode == 0, iclass 21, count 0 2006.258.01:31:36.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.01:31:36.60#ibcon#[27=USB\r\n] 2006.258.01:31:36.60#ibcon#*before write, iclass 21, count 0 2006.258.01:31:36.60#ibcon#enter sib2, iclass 21, count 0 2006.258.01:31:36.60#ibcon#flushed, iclass 21, count 0 2006.258.01:31:36.60#ibcon#about to write, iclass 21, count 0 2006.258.01:31:36.60#ibcon#wrote, iclass 21, count 0 2006.258.01:31:36.60#ibcon#about to read 3, iclass 21, count 0 2006.258.01:31:36.63#ibcon#read 3, iclass 21, count 0 2006.258.01:31:36.63#ibcon#about to read 4, iclass 21, count 0 2006.258.01:31:36.63#ibcon#read 4, iclass 21, count 0 2006.258.01:31:36.63#ibcon#about to read 5, iclass 21, count 0 2006.258.01:31:36.63#ibcon#read 5, iclass 21, count 0 2006.258.01:31:36.63#ibcon#about to read 6, iclass 21, count 0 2006.258.01:31:36.63#ibcon#read 6, iclass 21, count 0 2006.258.01:31:36.63#ibcon#end of sib2, iclass 21, count 0 2006.258.01:31:36.63#ibcon#*after write, iclass 21, count 0 2006.258.01:31:36.63#ibcon#*before return 0, iclass 21, count 0 2006.258.01:31:36.63#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:36.63#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:31:36.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.01:31:36.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.01:31:36.63$vck44/vabw=wide 2006.258.01:31:36.63#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.01:31:36.63#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.01:31:36.63#ibcon#ireg 8 cls_cnt 0 2006.258.01:31:36.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:36.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:36.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:36.63#ibcon#enter wrdev, iclass 23, count 0 2006.258.01:31:36.63#ibcon#first serial, iclass 23, count 0 2006.258.01:31:36.63#ibcon#enter sib2, iclass 23, count 0 2006.258.01:31:36.63#ibcon#flushed, iclass 23, count 0 2006.258.01:31:36.63#ibcon#about to write, iclass 23, count 0 2006.258.01:31:36.63#ibcon#wrote, iclass 23, count 0 2006.258.01:31:36.63#ibcon#about to read 3, iclass 23, count 0 2006.258.01:31:36.65#ibcon#read 3, iclass 23, count 0 2006.258.01:31:36.65#ibcon#about to read 4, iclass 23, count 0 2006.258.01:31:36.65#ibcon#read 4, iclass 23, count 0 2006.258.01:31:36.65#ibcon#about to read 5, iclass 23, count 0 2006.258.01:31:36.65#ibcon#read 5, iclass 23, count 0 2006.258.01:31:36.65#ibcon#about to read 6, iclass 23, count 0 2006.258.01:31:36.65#ibcon#read 6, iclass 23, count 0 2006.258.01:31:36.65#ibcon#end of sib2, iclass 23, count 0 2006.258.01:31:36.65#ibcon#*mode == 0, iclass 23, count 0 2006.258.01:31:36.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.01:31:36.65#ibcon#[25=BW32\r\n] 2006.258.01:31:36.65#ibcon#*before write, iclass 23, count 0 2006.258.01:31:36.65#ibcon#enter sib2, iclass 23, count 0 2006.258.01:31:36.65#ibcon#flushed, iclass 23, count 0 2006.258.01:31:36.65#ibcon#about to write, iclass 23, count 0 2006.258.01:31:36.65#ibcon#wrote, iclass 23, count 0 2006.258.01:31:36.65#ibcon#about to read 3, iclass 23, count 0 2006.258.01:31:36.68#ibcon#read 3, iclass 23, count 0 2006.258.01:31:36.68#ibcon#about to read 4, iclass 23, count 0 2006.258.01:31:36.68#ibcon#read 4, iclass 23, count 0 2006.258.01:31:36.68#ibcon#about to read 5, iclass 23, count 0 2006.258.01:31:36.68#ibcon#read 5, iclass 23, count 0 2006.258.01:31:36.68#ibcon#about to read 6, iclass 23, count 0 2006.258.01:31:36.68#ibcon#read 6, iclass 23, count 0 2006.258.01:31:36.68#ibcon#end of sib2, iclass 23, count 0 2006.258.01:31:36.68#ibcon#*after write, iclass 23, count 0 2006.258.01:31:36.68#ibcon#*before return 0, iclass 23, count 0 2006.258.01:31:36.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:36.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:31:36.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.01:31:36.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.01:31:36.68$vck44/vbbw=wide 2006.258.01:31:36.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.01:31:36.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.01:31:36.68#ibcon#ireg 8 cls_cnt 0 2006.258.01:31:36.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:31:36.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:31:36.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:31:36.75#ibcon#enter wrdev, iclass 25, count 0 2006.258.01:31:36.75#ibcon#first serial, iclass 25, count 0 2006.258.01:31:36.75#ibcon#enter sib2, iclass 25, count 0 2006.258.01:31:36.75#ibcon#flushed, iclass 25, count 0 2006.258.01:31:36.75#ibcon#about to write, iclass 25, count 0 2006.258.01:31:36.75#ibcon#wrote, iclass 25, count 0 2006.258.01:31:36.75#ibcon#about to read 3, iclass 25, count 0 2006.258.01:31:36.77#ibcon#read 3, iclass 25, count 0 2006.258.01:31:36.77#ibcon#about to read 4, iclass 25, count 0 2006.258.01:31:36.77#ibcon#read 4, iclass 25, count 0 2006.258.01:31:36.77#ibcon#about to read 5, iclass 25, count 0 2006.258.01:31:36.77#ibcon#read 5, iclass 25, count 0 2006.258.01:31:36.77#ibcon#about to read 6, iclass 25, count 0 2006.258.01:31:36.77#ibcon#read 6, iclass 25, count 0 2006.258.01:31:36.77#ibcon#end of sib2, iclass 25, count 0 2006.258.01:31:36.77#ibcon#*mode == 0, iclass 25, count 0 2006.258.01:31:36.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.01:31:36.77#ibcon#[27=BW32\r\n] 2006.258.01:31:36.77#ibcon#*before write, iclass 25, count 0 2006.258.01:31:36.77#ibcon#enter sib2, iclass 25, count 0 2006.258.01:31:36.77#ibcon#flushed, iclass 25, count 0 2006.258.01:31:36.77#ibcon#about to write, iclass 25, count 0 2006.258.01:31:36.77#ibcon#wrote, iclass 25, count 0 2006.258.01:31:36.77#ibcon#about to read 3, iclass 25, count 0 2006.258.01:31:36.80#ibcon#read 3, iclass 25, count 0 2006.258.01:31:36.80#ibcon#about to read 4, iclass 25, count 0 2006.258.01:31:36.80#ibcon#read 4, iclass 25, count 0 2006.258.01:31:36.80#ibcon#about to read 5, iclass 25, count 0 2006.258.01:31:36.80#ibcon#read 5, iclass 25, count 0 2006.258.01:31:36.80#ibcon#about to read 6, iclass 25, count 0 2006.258.01:31:36.80#ibcon#read 6, iclass 25, count 0 2006.258.01:31:36.80#ibcon#end of sib2, iclass 25, count 0 2006.258.01:31:36.80#ibcon#*after write, iclass 25, count 0 2006.258.01:31:36.80#ibcon#*before return 0, iclass 25, count 0 2006.258.01:31:36.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:31:36.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:31:36.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.01:31:36.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.01:31:36.80$setupk4/ifdk4 2006.258.01:31:36.80$ifdk4/lo= 2006.258.01:31:36.80$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.01:31:36.80$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.01:31:36.80$ifdk4/patch= 2006.258.01:31:36.80$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.01:31:36.80$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.01:31:36.80$setupk4/!*+20s 2006.258.01:31:44.34#abcon#<5=/03 3.1 7.0 23.18 701015.9\r\n> 2006.258.01:31:44.36#abcon#{5=INTERFACE CLEAR} 2006.258.01:31:44.42#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:31:45.13#trakl#Source acquired 2006.258.01:31:47.13#flagr#flagr/antenna,acquired 2006.258.01:31:51.30$setupk4/"tpicd 2006.258.01:31:51.30$setupk4/echo=off 2006.258.01:31:51.30$setupk4/xlog=off 2006.258.01:31:51.30:!2006.258.01:34:07 2006.258.01:34:07.00:preob 2006.258.01:34:07.14/onsource/TRACKING 2006.258.01:34:07.14:!2006.258.01:34:17 2006.258.01:34:17.00:"tape 2006.258.01:34:17.00:"st=record 2006.258.01:34:17.00:data_valid=on 2006.258.01:34:17.00:midob 2006.258.01:34:17.14/onsource/TRACKING 2006.258.01:34:17.14/wx/23.30,1016.0,68 2006.258.01:34:17.28/cable/+6.4725E-03 2006.258.01:34:18.37/va/01,08,usb,yes,33,35 2006.258.01:34:18.37/va/02,07,usb,yes,35,36 2006.258.01:34:18.37/va/03,08,usb,yes,32,34 2006.258.01:34:18.37/va/04,07,usb,yes,36,38 2006.258.01:34:18.37/va/05,04,usb,yes,32,33 2006.258.01:34:18.37/va/06,04,usb,yes,36,36 2006.258.01:34:18.37/va/07,04,usb,yes,37,37 2006.258.01:34:18.37/va/08,04,usb,yes,31,38 2006.258.01:34:18.60/valo/01,524.99,yes,locked 2006.258.01:34:18.60/valo/02,534.99,yes,locked 2006.258.01:34:18.60/valo/03,564.99,yes,locked 2006.258.01:34:18.60/valo/04,624.99,yes,locked 2006.258.01:34:18.60/valo/05,734.99,yes,locked 2006.258.01:34:18.60/valo/06,814.99,yes,locked 2006.258.01:34:18.60/valo/07,864.99,yes,locked 2006.258.01:34:18.60/valo/08,884.99,yes,locked 2006.258.01:34:19.69/vb/01,04,usb,yes,38,35 2006.258.01:34:19.69/vb/02,05,usb,yes,36,35 2006.258.01:34:19.69/vb/03,04,usb,yes,37,41 2006.258.01:34:19.69/vb/04,05,usb,yes,37,36 2006.258.01:34:19.69/vb/05,04,usb,yes,33,36 2006.258.01:34:19.69/vb/06,04,usb,yes,38,34 2006.258.01:34:19.69/vb/07,04,usb,yes,38,38 2006.258.01:34:19.69/vb/08,04,usb,yes,35,39 2006.258.01:34:19.92/vblo/01,629.99,yes,locked 2006.258.01:34:19.92/vblo/02,634.99,yes,locked 2006.258.01:34:19.92/vblo/03,649.99,yes,locked 2006.258.01:34:19.92/vblo/04,679.99,yes,locked 2006.258.01:34:19.92/vblo/05,709.99,yes,locked 2006.258.01:34:19.92/vblo/06,719.99,yes,locked 2006.258.01:34:19.92/vblo/07,734.99,yes,locked 2006.258.01:34:19.92/vblo/08,744.99,yes,locked 2006.258.01:34:20.07/vabw/8 2006.258.01:34:20.22/vbbw/8 2006.258.01:34:20.31/xfe/off,on,15.5 2006.258.01:34:20.68/ifatt/23,28,28,28 2006.258.01:34:21.07/fmout-gps/S +4.48E-07 2006.258.01:34:21.11:!2006.258.01:35:37 2006.258.01:35:37.01:data_valid=off 2006.258.01:35:37.01:"et 2006.258.01:35:37.02:!+3s 2006.258.01:35:40.03:"tape 2006.258.01:35:40.03:postob 2006.258.01:35:40.16/cable/+6.4719E-03 2006.258.01:35:40.16/wx/23.38,1016.0,69 2006.258.01:35:40.22/fmout-gps/S +4.47E-07 2006.258.01:35:40.22:scan_name=258-0139,jd0609,60 2006.258.01:35:40.23:source=1611+343,161341.06,341247.9,2000.0,cw 2006.258.01:35:41.14#flagr#flagr/antenna,new-source 2006.258.01:35:41.14:checkk5 2006.258.01:35:41.56/chk_autoobs//k5ts1/ autoobs is running! 2006.258.01:35:41.97/chk_autoobs//k5ts2/ autoobs is running! 2006.258.01:35:42.36/chk_autoobs//k5ts3/ autoobs is running! 2006.258.01:35:42.74/chk_autoobs//k5ts4/ autoobs is running! 2006.258.01:35:43.14/chk_obsdata//k5ts1/T2580134??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.258.01:35:43.56/chk_obsdata//k5ts2/T2580134??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.258.01:35:43.96/chk_obsdata//k5ts3/T2580134??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.258.01:35:44.36/chk_obsdata//k5ts4/T2580134??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.258.01:35:45.09/k5log//k5ts1_log_newline 2006.258.01:35:45.81/k5log//k5ts2_log_newline 2006.258.01:35:46.58/k5log//k5ts3_log_newline 2006.258.01:35:47.31/k5log//k5ts4_log_newline 2006.258.01:35:47.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:35:47.34:setupk4=1 2006.258.01:35:47.34$setupk4/echo=on 2006.258.01:35:47.34$setupk4/pcalon 2006.258.01:35:47.34$pcalon/"no phase cal control is implemented here 2006.258.01:35:47.34$setupk4/"tpicd=stop 2006.258.01:35:47.34$setupk4/"rec=synch_on 2006.258.01:35:47.34$setupk4/"rec_mode=128 2006.258.01:35:47.34$setupk4/!* 2006.258.01:35:47.34$setupk4/recpk4 2006.258.01:35:47.34$recpk4/recpatch= 2006.258.01:35:47.35$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.01:35:47.35$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.01:35:47.35$setupk4/vck44 2006.258.01:35:47.35$vck44/valo=1,524.99 2006.258.01:35:47.35#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.01:35:47.35#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.01:35:47.35#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:47.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:47.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:47.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:47.35#ibcon#enter wrdev, iclass 18, count 0 2006.258.01:35:47.35#ibcon#first serial, iclass 18, count 0 2006.258.01:35:47.35#ibcon#enter sib2, iclass 18, count 0 2006.258.01:35:47.35#ibcon#flushed, iclass 18, count 0 2006.258.01:35:47.35#ibcon#about to write, iclass 18, count 0 2006.258.01:35:47.35#ibcon#wrote, iclass 18, count 0 2006.258.01:35:47.35#ibcon#about to read 3, iclass 18, count 0 2006.258.01:35:47.36#ibcon#read 3, iclass 18, count 0 2006.258.01:35:47.36#ibcon#about to read 4, iclass 18, count 0 2006.258.01:35:47.36#ibcon#read 4, iclass 18, count 0 2006.258.01:35:47.36#ibcon#about to read 5, iclass 18, count 0 2006.258.01:35:47.36#ibcon#read 5, iclass 18, count 0 2006.258.01:35:47.36#ibcon#about to read 6, iclass 18, count 0 2006.258.01:35:47.36#ibcon#read 6, iclass 18, count 0 2006.258.01:35:47.36#ibcon#end of sib2, iclass 18, count 0 2006.258.01:35:47.36#ibcon#*mode == 0, iclass 18, count 0 2006.258.01:35:47.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.01:35:47.36#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.01:35:47.36#ibcon#*before write, iclass 18, count 0 2006.258.01:35:47.36#ibcon#enter sib2, iclass 18, count 0 2006.258.01:35:47.36#ibcon#flushed, iclass 18, count 0 2006.258.01:35:47.36#ibcon#about to write, iclass 18, count 0 2006.258.01:35:47.36#ibcon#wrote, iclass 18, count 0 2006.258.01:35:47.36#ibcon#about to read 3, iclass 18, count 0 2006.258.01:35:47.41#ibcon#read 3, iclass 18, count 0 2006.258.01:35:47.41#ibcon#about to read 4, iclass 18, count 0 2006.258.01:35:47.41#ibcon#read 4, iclass 18, count 0 2006.258.01:35:47.41#ibcon#about to read 5, iclass 18, count 0 2006.258.01:35:47.41#ibcon#read 5, iclass 18, count 0 2006.258.01:35:47.41#ibcon#about to read 6, iclass 18, count 0 2006.258.01:35:47.41#ibcon#read 6, iclass 18, count 0 2006.258.01:35:47.41#ibcon#end of sib2, iclass 18, count 0 2006.258.01:35:47.41#ibcon#*after write, iclass 18, count 0 2006.258.01:35:47.41#ibcon#*before return 0, iclass 18, count 0 2006.258.01:35:47.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:47.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:47.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.01:35:47.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.01:35:47.41$vck44/va=1,8 2006.258.01:35:47.41#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.01:35:47.41#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.01:35:47.41#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:47.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:47.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:47.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:47.41#ibcon#enter wrdev, iclass 20, count 2 2006.258.01:35:47.41#ibcon#first serial, iclass 20, count 2 2006.258.01:35:47.41#ibcon#enter sib2, iclass 20, count 2 2006.258.01:35:47.41#ibcon#flushed, iclass 20, count 2 2006.258.01:35:47.41#ibcon#about to write, iclass 20, count 2 2006.258.01:35:47.41#ibcon#wrote, iclass 20, count 2 2006.258.01:35:47.41#ibcon#about to read 3, iclass 20, count 2 2006.258.01:35:47.43#ibcon#read 3, iclass 20, count 2 2006.258.01:35:47.43#ibcon#about to read 4, iclass 20, count 2 2006.258.01:35:47.43#ibcon#read 4, iclass 20, count 2 2006.258.01:35:47.43#ibcon#about to read 5, iclass 20, count 2 2006.258.01:35:47.43#ibcon#read 5, iclass 20, count 2 2006.258.01:35:47.43#ibcon#about to read 6, iclass 20, count 2 2006.258.01:35:47.43#ibcon#read 6, iclass 20, count 2 2006.258.01:35:47.43#ibcon#end of sib2, iclass 20, count 2 2006.258.01:35:47.43#ibcon#*mode == 0, iclass 20, count 2 2006.258.01:35:47.43#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.01:35:47.43#ibcon#[25=AT01-08\r\n] 2006.258.01:35:47.43#ibcon#*before write, iclass 20, count 2 2006.258.01:35:47.43#ibcon#enter sib2, iclass 20, count 2 2006.258.01:35:47.43#ibcon#flushed, iclass 20, count 2 2006.258.01:35:47.43#ibcon#about to write, iclass 20, count 2 2006.258.01:35:47.43#ibcon#wrote, iclass 20, count 2 2006.258.01:35:47.43#ibcon#about to read 3, iclass 20, count 2 2006.258.01:35:47.46#ibcon#read 3, iclass 20, count 2 2006.258.01:35:47.46#ibcon#about to read 4, iclass 20, count 2 2006.258.01:35:47.46#ibcon#read 4, iclass 20, count 2 2006.258.01:35:47.46#ibcon#about to read 5, iclass 20, count 2 2006.258.01:35:47.46#ibcon#read 5, iclass 20, count 2 2006.258.01:35:47.46#ibcon#about to read 6, iclass 20, count 2 2006.258.01:35:47.46#ibcon#read 6, iclass 20, count 2 2006.258.01:35:47.46#ibcon#end of sib2, iclass 20, count 2 2006.258.01:35:47.46#ibcon#*after write, iclass 20, count 2 2006.258.01:35:47.46#ibcon#*before return 0, iclass 20, count 2 2006.258.01:35:47.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:47.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:47.46#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.01:35:47.46#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:47.46#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:47.58#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:47.58#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:47.58#ibcon#enter wrdev, iclass 20, count 0 2006.258.01:35:47.58#ibcon#first serial, iclass 20, count 0 2006.258.01:35:47.58#ibcon#enter sib2, iclass 20, count 0 2006.258.01:35:47.58#ibcon#flushed, iclass 20, count 0 2006.258.01:35:47.58#ibcon#about to write, iclass 20, count 0 2006.258.01:35:47.58#ibcon#wrote, iclass 20, count 0 2006.258.01:35:47.58#ibcon#about to read 3, iclass 20, count 0 2006.258.01:35:47.60#ibcon#read 3, iclass 20, count 0 2006.258.01:35:47.60#ibcon#about to read 4, iclass 20, count 0 2006.258.01:35:47.60#ibcon#read 4, iclass 20, count 0 2006.258.01:35:47.60#ibcon#about to read 5, iclass 20, count 0 2006.258.01:35:47.60#ibcon#read 5, iclass 20, count 0 2006.258.01:35:47.60#ibcon#about to read 6, iclass 20, count 0 2006.258.01:35:47.60#ibcon#read 6, iclass 20, count 0 2006.258.01:35:47.60#ibcon#end of sib2, iclass 20, count 0 2006.258.01:35:47.60#ibcon#*mode == 0, iclass 20, count 0 2006.258.01:35:47.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.01:35:47.60#ibcon#[25=USB\r\n] 2006.258.01:35:47.60#ibcon#*before write, iclass 20, count 0 2006.258.01:35:47.60#ibcon#enter sib2, iclass 20, count 0 2006.258.01:35:47.60#ibcon#flushed, iclass 20, count 0 2006.258.01:35:47.60#ibcon#about to write, iclass 20, count 0 2006.258.01:35:47.60#ibcon#wrote, iclass 20, count 0 2006.258.01:35:47.60#ibcon#about to read 3, iclass 20, count 0 2006.258.01:35:47.63#ibcon#read 3, iclass 20, count 0 2006.258.01:35:47.63#ibcon#about to read 4, iclass 20, count 0 2006.258.01:35:47.63#ibcon#read 4, iclass 20, count 0 2006.258.01:35:47.63#ibcon#about to read 5, iclass 20, count 0 2006.258.01:35:47.63#ibcon#read 5, iclass 20, count 0 2006.258.01:35:47.63#ibcon#about to read 6, iclass 20, count 0 2006.258.01:35:47.63#ibcon#read 6, iclass 20, count 0 2006.258.01:35:47.63#ibcon#end of sib2, iclass 20, count 0 2006.258.01:35:47.63#ibcon#*after write, iclass 20, count 0 2006.258.01:35:47.63#ibcon#*before return 0, iclass 20, count 0 2006.258.01:35:47.63#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:47.63#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:47.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.01:35:47.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.01:35:47.63$vck44/valo=2,534.99 2006.258.01:35:47.63#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.01:35:47.63#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.01:35:47.63#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:47.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:47.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:47.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:47.63#ibcon#enter wrdev, iclass 22, count 0 2006.258.01:35:47.63#ibcon#first serial, iclass 22, count 0 2006.258.01:35:47.63#ibcon#enter sib2, iclass 22, count 0 2006.258.01:35:47.63#ibcon#flushed, iclass 22, count 0 2006.258.01:35:47.63#ibcon#about to write, iclass 22, count 0 2006.258.01:35:47.63#ibcon#wrote, iclass 22, count 0 2006.258.01:35:47.63#ibcon#about to read 3, iclass 22, count 0 2006.258.01:35:47.65#ibcon#read 3, iclass 22, count 0 2006.258.01:35:47.65#ibcon#about to read 4, iclass 22, count 0 2006.258.01:35:47.65#ibcon#read 4, iclass 22, count 0 2006.258.01:35:47.65#ibcon#about to read 5, iclass 22, count 0 2006.258.01:35:47.65#ibcon#read 5, iclass 22, count 0 2006.258.01:35:47.65#ibcon#about to read 6, iclass 22, count 0 2006.258.01:35:47.65#ibcon#read 6, iclass 22, count 0 2006.258.01:35:47.65#ibcon#end of sib2, iclass 22, count 0 2006.258.01:35:47.65#ibcon#*mode == 0, iclass 22, count 0 2006.258.01:35:47.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.01:35:47.65#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.01:35:47.65#ibcon#*before write, iclass 22, count 0 2006.258.01:35:47.65#ibcon#enter sib2, iclass 22, count 0 2006.258.01:35:47.65#ibcon#flushed, iclass 22, count 0 2006.258.01:35:47.65#ibcon#about to write, iclass 22, count 0 2006.258.01:35:47.65#ibcon#wrote, iclass 22, count 0 2006.258.01:35:47.65#ibcon#about to read 3, iclass 22, count 0 2006.258.01:35:47.69#ibcon#read 3, iclass 22, count 0 2006.258.01:35:47.69#ibcon#about to read 4, iclass 22, count 0 2006.258.01:35:47.69#ibcon#read 4, iclass 22, count 0 2006.258.01:35:47.69#ibcon#about to read 5, iclass 22, count 0 2006.258.01:35:47.69#ibcon#read 5, iclass 22, count 0 2006.258.01:35:47.69#ibcon#about to read 6, iclass 22, count 0 2006.258.01:35:47.69#ibcon#read 6, iclass 22, count 0 2006.258.01:35:47.69#ibcon#end of sib2, iclass 22, count 0 2006.258.01:35:47.69#ibcon#*after write, iclass 22, count 0 2006.258.01:35:47.69#ibcon#*before return 0, iclass 22, count 0 2006.258.01:35:47.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:47.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:47.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.01:35:47.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.01:35:47.69$vck44/va=2,7 2006.258.01:35:47.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.01:35:47.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.01:35:47.69#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:47.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:47.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:47.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:47.75#ibcon#enter wrdev, iclass 24, count 2 2006.258.01:35:47.75#ibcon#first serial, iclass 24, count 2 2006.258.01:35:47.75#ibcon#enter sib2, iclass 24, count 2 2006.258.01:35:47.75#ibcon#flushed, iclass 24, count 2 2006.258.01:35:47.75#ibcon#about to write, iclass 24, count 2 2006.258.01:35:47.75#ibcon#wrote, iclass 24, count 2 2006.258.01:35:47.75#ibcon#about to read 3, iclass 24, count 2 2006.258.01:35:47.77#ibcon#read 3, iclass 24, count 2 2006.258.01:35:47.77#ibcon#about to read 4, iclass 24, count 2 2006.258.01:35:47.77#ibcon#read 4, iclass 24, count 2 2006.258.01:35:47.77#ibcon#about to read 5, iclass 24, count 2 2006.258.01:35:47.77#ibcon#read 5, iclass 24, count 2 2006.258.01:35:47.77#ibcon#about to read 6, iclass 24, count 2 2006.258.01:35:47.77#ibcon#read 6, iclass 24, count 2 2006.258.01:35:47.77#ibcon#end of sib2, iclass 24, count 2 2006.258.01:35:47.77#ibcon#*mode == 0, iclass 24, count 2 2006.258.01:35:47.77#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.01:35:47.77#ibcon#[25=AT02-07\r\n] 2006.258.01:35:47.77#ibcon#*before write, iclass 24, count 2 2006.258.01:35:47.77#ibcon#enter sib2, iclass 24, count 2 2006.258.01:35:47.77#ibcon#flushed, iclass 24, count 2 2006.258.01:35:47.77#ibcon#about to write, iclass 24, count 2 2006.258.01:35:47.77#ibcon#wrote, iclass 24, count 2 2006.258.01:35:47.77#ibcon#about to read 3, iclass 24, count 2 2006.258.01:35:47.80#ibcon#read 3, iclass 24, count 2 2006.258.01:35:47.80#ibcon#about to read 4, iclass 24, count 2 2006.258.01:35:47.80#ibcon#read 4, iclass 24, count 2 2006.258.01:35:47.80#ibcon#about to read 5, iclass 24, count 2 2006.258.01:35:47.80#ibcon#read 5, iclass 24, count 2 2006.258.01:35:47.80#ibcon#about to read 6, iclass 24, count 2 2006.258.01:35:47.80#ibcon#read 6, iclass 24, count 2 2006.258.01:35:47.80#ibcon#end of sib2, iclass 24, count 2 2006.258.01:35:47.80#ibcon#*after write, iclass 24, count 2 2006.258.01:35:47.80#ibcon#*before return 0, iclass 24, count 2 2006.258.01:35:47.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:47.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:47.80#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.01:35:47.80#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:47.80#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:47.92#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:47.92#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:47.92#ibcon#enter wrdev, iclass 24, count 0 2006.258.01:35:47.92#ibcon#first serial, iclass 24, count 0 2006.258.01:35:47.92#ibcon#enter sib2, iclass 24, count 0 2006.258.01:35:47.92#ibcon#flushed, iclass 24, count 0 2006.258.01:35:47.92#ibcon#about to write, iclass 24, count 0 2006.258.01:35:47.92#ibcon#wrote, iclass 24, count 0 2006.258.01:35:47.92#ibcon#about to read 3, iclass 24, count 0 2006.258.01:35:47.94#ibcon#read 3, iclass 24, count 0 2006.258.01:35:47.94#ibcon#about to read 4, iclass 24, count 0 2006.258.01:35:47.94#ibcon#read 4, iclass 24, count 0 2006.258.01:35:47.94#ibcon#about to read 5, iclass 24, count 0 2006.258.01:35:47.94#ibcon#read 5, iclass 24, count 0 2006.258.01:35:47.94#ibcon#about to read 6, iclass 24, count 0 2006.258.01:35:47.94#ibcon#read 6, iclass 24, count 0 2006.258.01:35:47.94#ibcon#end of sib2, iclass 24, count 0 2006.258.01:35:47.94#ibcon#*mode == 0, iclass 24, count 0 2006.258.01:35:47.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.01:35:47.94#ibcon#[25=USB\r\n] 2006.258.01:35:47.94#ibcon#*before write, iclass 24, count 0 2006.258.01:35:47.94#ibcon#enter sib2, iclass 24, count 0 2006.258.01:35:47.94#ibcon#flushed, iclass 24, count 0 2006.258.01:35:47.94#ibcon#about to write, iclass 24, count 0 2006.258.01:35:47.94#ibcon#wrote, iclass 24, count 0 2006.258.01:35:47.94#ibcon#about to read 3, iclass 24, count 0 2006.258.01:35:47.97#ibcon#read 3, iclass 24, count 0 2006.258.01:35:47.97#ibcon#about to read 4, iclass 24, count 0 2006.258.01:35:47.97#ibcon#read 4, iclass 24, count 0 2006.258.01:35:47.97#ibcon#about to read 5, iclass 24, count 0 2006.258.01:35:47.97#ibcon#read 5, iclass 24, count 0 2006.258.01:35:47.97#ibcon#about to read 6, iclass 24, count 0 2006.258.01:35:47.97#ibcon#read 6, iclass 24, count 0 2006.258.01:35:47.97#ibcon#end of sib2, iclass 24, count 0 2006.258.01:35:47.97#ibcon#*after write, iclass 24, count 0 2006.258.01:35:47.97#ibcon#*before return 0, iclass 24, count 0 2006.258.01:35:47.97#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:47.97#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:47.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.01:35:47.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.01:35:47.97$vck44/valo=3,564.99 2006.258.01:35:47.97#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.01:35:47.97#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.01:35:47.97#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:47.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:47.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:47.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:47.97#ibcon#enter wrdev, iclass 26, count 0 2006.258.01:35:47.97#ibcon#first serial, iclass 26, count 0 2006.258.01:35:47.97#ibcon#enter sib2, iclass 26, count 0 2006.258.01:35:47.97#ibcon#flushed, iclass 26, count 0 2006.258.01:35:47.97#ibcon#about to write, iclass 26, count 0 2006.258.01:35:47.97#ibcon#wrote, iclass 26, count 0 2006.258.01:35:47.97#ibcon#about to read 3, iclass 26, count 0 2006.258.01:35:47.99#ibcon#read 3, iclass 26, count 0 2006.258.01:35:47.99#ibcon#about to read 4, iclass 26, count 0 2006.258.01:35:47.99#ibcon#read 4, iclass 26, count 0 2006.258.01:35:47.99#ibcon#about to read 5, iclass 26, count 0 2006.258.01:35:47.99#ibcon#read 5, iclass 26, count 0 2006.258.01:35:47.99#ibcon#about to read 6, iclass 26, count 0 2006.258.01:35:47.99#ibcon#read 6, iclass 26, count 0 2006.258.01:35:47.99#ibcon#end of sib2, iclass 26, count 0 2006.258.01:35:47.99#ibcon#*mode == 0, iclass 26, count 0 2006.258.01:35:47.99#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.01:35:47.99#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.01:35:47.99#ibcon#*before write, iclass 26, count 0 2006.258.01:35:47.99#ibcon#enter sib2, iclass 26, count 0 2006.258.01:35:47.99#ibcon#flushed, iclass 26, count 0 2006.258.01:35:47.99#ibcon#about to write, iclass 26, count 0 2006.258.01:35:47.99#ibcon#wrote, iclass 26, count 0 2006.258.01:35:47.99#ibcon#about to read 3, iclass 26, count 0 2006.258.01:35:48.03#ibcon#read 3, iclass 26, count 0 2006.258.01:35:48.03#ibcon#about to read 4, iclass 26, count 0 2006.258.01:35:48.03#ibcon#read 4, iclass 26, count 0 2006.258.01:35:48.03#ibcon#about to read 5, iclass 26, count 0 2006.258.01:35:48.03#ibcon#read 5, iclass 26, count 0 2006.258.01:35:48.03#ibcon#about to read 6, iclass 26, count 0 2006.258.01:35:48.03#ibcon#read 6, iclass 26, count 0 2006.258.01:35:48.03#ibcon#end of sib2, iclass 26, count 0 2006.258.01:35:48.03#ibcon#*after write, iclass 26, count 0 2006.258.01:35:48.03#ibcon#*before return 0, iclass 26, count 0 2006.258.01:35:48.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:48.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:48.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.01:35:48.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.01:35:48.03$vck44/va=3,8 2006.258.01:35:48.03#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.01:35:48.03#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.01:35:48.03#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:48.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:48.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:48.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:48.09#ibcon#enter wrdev, iclass 28, count 2 2006.258.01:35:48.09#ibcon#first serial, iclass 28, count 2 2006.258.01:35:48.09#ibcon#enter sib2, iclass 28, count 2 2006.258.01:35:48.09#ibcon#flushed, iclass 28, count 2 2006.258.01:35:48.09#ibcon#about to write, iclass 28, count 2 2006.258.01:35:48.09#ibcon#wrote, iclass 28, count 2 2006.258.01:35:48.09#ibcon#about to read 3, iclass 28, count 2 2006.258.01:35:48.11#ibcon#read 3, iclass 28, count 2 2006.258.01:35:48.11#ibcon#about to read 4, iclass 28, count 2 2006.258.01:35:48.11#ibcon#read 4, iclass 28, count 2 2006.258.01:35:48.11#ibcon#about to read 5, iclass 28, count 2 2006.258.01:35:48.11#ibcon#read 5, iclass 28, count 2 2006.258.01:35:48.11#ibcon#about to read 6, iclass 28, count 2 2006.258.01:35:48.11#ibcon#read 6, iclass 28, count 2 2006.258.01:35:48.11#ibcon#end of sib2, iclass 28, count 2 2006.258.01:35:48.11#ibcon#*mode == 0, iclass 28, count 2 2006.258.01:35:48.11#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.01:35:48.11#ibcon#[25=AT03-08\r\n] 2006.258.01:35:48.11#ibcon#*before write, iclass 28, count 2 2006.258.01:35:48.11#ibcon#enter sib2, iclass 28, count 2 2006.258.01:35:48.11#ibcon#flushed, iclass 28, count 2 2006.258.01:35:48.11#ibcon#about to write, iclass 28, count 2 2006.258.01:35:48.11#ibcon#wrote, iclass 28, count 2 2006.258.01:35:48.11#ibcon#about to read 3, iclass 28, count 2 2006.258.01:35:48.14#ibcon#read 3, iclass 28, count 2 2006.258.01:35:48.14#ibcon#about to read 4, iclass 28, count 2 2006.258.01:35:48.14#ibcon#read 4, iclass 28, count 2 2006.258.01:35:48.14#ibcon#about to read 5, iclass 28, count 2 2006.258.01:35:48.14#ibcon#read 5, iclass 28, count 2 2006.258.01:35:48.14#ibcon#about to read 6, iclass 28, count 2 2006.258.01:35:48.14#ibcon#read 6, iclass 28, count 2 2006.258.01:35:48.14#ibcon#end of sib2, iclass 28, count 2 2006.258.01:35:48.14#ibcon#*after write, iclass 28, count 2 2006.258.01:35:48.14#ibcon#*before return 0, iclass 28, count 2 2006.258.01:35:48.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:48.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:48.14#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.01:35:48.14#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:48.14#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:48.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:48.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:48.26#ibcon#enter wrdev, iclass 28, count 0 2006.258.01:35:48.26#ibcon#first serial, iclass 28, count 0 2006.258.01:35:48.26#ibcon#enter sib2, iclass 28, count 0 2006.258.01:35:48.26#ibcon#flushed, iclass 28, count 0 2006.258.01:35:48.26#ibcon#about to write, iclass 28, count 0 2006.258.01:35:48.26#ibcon#wrote, iclass 28, count 0 2006.258.01:35:48.26#ibcon#about to read 3, iclass 28, count 0 2006.258.01:35:48.28#ibcon#read 3, iclass 28, count 0 2006.258.01:35:48.28#ibcon#about to read 4, iclass 28, count 0 2006.258.01:35:48.28#ibcon#read 4, iclass 28, count 0 2006.258.01:35:48.28#ibcon#about to read 5, iclass 28, count 0 2006.258.01:35:48.28#ibcon#read 5, iclass 28, count 0 2006.258.01:35:48.28#ibcon#about to read 6, iclass 28, count 0 2006.258.01:35:48.28#ibcon#read 6, iclass 28, count 0 2006.258.01:35:48.28#ibcon#end of sib2, iclass 28, count 0 2006.258.01:35:48.28#ibcon#*mode == 0, iclass 28, count 0 2006.258.01:35:48.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.01:35:48.28#ibcon#[25=USB\r\n] 2006.258.01:35:48.28#ibcon#*before write, iclass 28, count 0 2006.258.01:35:48.28#ibcon#enter sib2, iclass 28, count 0 2006.258.01:35:48.28#ibcon#flushed, iclass 28, count 0 2006.258.01:35:48.28#ibcon#about to write, iclass 28, count 0 2006.258.01:35:48.28#ibcon#wrote, iclass 28, count 0 2006.258.01:35:48.28#ibcon#about to read 3, iclass 28, count 0 2006.258.01:35:48.31#ibcon#read 3, iclass 28, count 0 2006.258.01:35:48.31#ibcon#about to read 4, iclass 28, count 0 2006.258.01:35:48.31#ibcon#read 4, iclass 28, count 0 2006.258.01:35:48.31#ibcon#about to read 5, iclass 28, count 0 2006.258.01:35:48.31#ibcon#read 5, iclass 28, count 0 2006.258.01:35:48.31#ibcon#about to read 6, iclass 28, count 0 2006.258.01:35:48.31#ibcon#read 6, iclass 28, count 0 2006.258.01:35:48.31#ibcon#end of sib2, iclass 28, count 0 2006.258.01:35:48.31#ibcon#*after write, iclass 28, count 0 2006.258.01:35:48.31#ibcon#*before return 0, iclass 28, count 0 2006.258.01:35:48.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:48.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:48.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.01:35:48.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.01:35:48.31$vck44/valo=4,624.99 2006.258.01:35:48.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.01:35:48.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.01:35:48.31#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:48.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:48.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:48.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:48.31#ibcon#enter wrdev, iclass 30, count 0 2006.258.01:35:48.31#ibcon#first serial, iclass 30, count 0 2006.258.01:35:48.31#ibcon#enter sib2, iclass 30, count 0 2006.258.01:35:48.31#ibcon#flushed, iclass 30, count 0 2006.258.01:35:48.31#ibcon#about to write, iclass 30, count 0 2006.258.01:35:48.31#ibcon#wrote, iclass 30, count 0 2006.258.01:35:48.31#ibcon#about to read 3, iclass 30, count 0 2006.258.01:35:48.33#ibcon#read 3, iclass 30, count 0 2006.258.01:35:48.33#ibcon#about to read 4, iclass 30, count 0 2006.258.01:35:48.33#ibcon#read 4, iclass 30, count 0 2006.258.01:35:48.33#ibcon#about to read 5, iclass 30, count 0 2006.258.01:35:48.33#ibcon#read 5, iclass 30, count 0 2006.258.01:35:48.33#ibcon#about to read 6, iclass 30, count 0 2006.258.01:35:48.33#ibcon#read 6, iclass 30, count 0 2006.258.01:35:48.33#ibcon#end of sib2, iclass 30, count 0 2006.258.01:35:48.33#ibcon#*mode == 0, iclass 30, count 0 2006.258.01:35:48.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.01:35:48.33#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.01:35:48.33#ibcon#*before write, iclass 30, count 0 2006.258.01:35:48.33#ibcon#enter sib2, iclass 30, count 0 2006.258.01:35:48.33#ibcon#flushed, iclass 30, count 0 2006.258.01:35:48.33#ibcon#about to write, iclass 30, count 0 2006.258.01:35:48.33#ibcon#wrote, iclass 30, count 0 2006.258.01:35:48.33#ibcon#about to read 3, iclass 30, count 0 2006.258.01:35:48.37#ibcon#read 3, iclass 30, count 0 2006.258.01:35:48.37#ibcon#about to read 4, iclass 30, count 0 2006.258.01:35:48.37#ibcon#read 4, iclass 30, count 0 2006.258.01:35:48.37#ibcon#about to read 5, iclass 30, count 0 2006.258.01:35:48.37#ibcon#read 5, iclass 30, count 0 2006.258.01:35:48.37#ibcon#about to read 6, iclass 30, count 0 2006.258.01:35:48.37#ibcon#read 6, iclass 30, count 0 2006.258.01:35:48.37#ibcon#end of sib2, iclass 30, count 0 2006.258.01:35:48.37#ibcon#*after write, iclass 30, count 0 2006.258.01:35:48.37#ibcon#*before return 0, iclass 30, count 0 2006.258.01:35:48.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:48.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:48.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.01:35:48.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.01:35:48.37$vck44/va=4,7 2006.258.01:35:48.37#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.01:35:48.37#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.01:35:48.37#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:48.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:35:48.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:35:48.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:35:48.43#ibcon#enter wrdev, iclass 33, count 2 2006.258.01:35:48.43#ibcon#first serial, iclass 33, count 2 2006.258.01:35:48.43#ibcon#enter sib2, iclass 33, count 2 2006.258.01:35:48.43#ibcon#flushed, iclass 33, count 2 2006.258.01:35:48.43#ibcon#about to write, iclass 33, count 2 2006.258.01:35:48.43#ibcon#wrote, iclass 33, count 2 2006.258.01:35:48.43#ibcon#about to read 3, iclass 33, count 2 2006.258.01:35:48.45#ibcon#read 3, iclass 33, count 2 2006.258.01:35:48.45#ibcon#about to read 4, iclass 33, count 2 2006.258.01:35:48.45#ibcon#read 4, iclass 33, count 2 2006.258.01:35:48.45#ibcon#about to read 5, iclass 33, count 2 2006.258.01:35:48.45#ibcon#read 5, iclass 33, count 2 2006.258.01:35:48.45#ibcon#about to read 6, iclass 33, count 2 2006.258.01:35:48.45#ibcon#read 6, iclass 33, count 2 2006.258.01:35:48.45#ibcon#end of sib2, iclass 33, count 2 2006.258.01:35:48.45#ibcon#*mode == 0, iclass 33, count 2 2006.258.01:35:48.45#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.01:35:48.45#ibcon#[25=AT04-07\r\n] 2006.258.01:35:48.45#ibcon#*before write, iclass 33, count 2 2006.258.01:35:48.45#ibcon#enter sib2, iclass 33, count 2 2006.258.01:35:48.45#ibcon#flushed, iclass 33, count 2 2006.258.01:35:48.45#ibcon#about to write, iclass 33, count 2 2006.258.01:35:48.45#ibcon#wrote, iclass 33, count 2 2006.258.01:35:48.45#ibcon#about to read 3, iclass 33, count 2 2006.258.01:35:48.48#ibcon#read 3, iclass 33, count 2 2006.258.01:35:48.48#ibcon#about to read 4, iclass 33, count 2 2006.258.01:35:48.48#ibcon#read 4, iclass 33, count 2 2006.258.01:35:48.48#ibcon#about to read 5, iclass 33, count 2 2006.258.01:35:48.48#ibcon#read 5, iclass 33, count 2 2006.258.01:35:48.48#ibcon#about to read 6, iclass 33, count 2 2006.258.01:35:48.48#ibcon#read 6, iclass 33, count 2 2006.258.01:35:48.48#ibcon#end of sib2, iclass 33, count 2 2006.258.01:35:48.48#ibcon#*after write, iclass 33, count 2 2006.258.01:35:48.50#ibcon#*before return 0, iclass 33, count 2 2006.258.01:35:48.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:35:48.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:35:48.50#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.01:35:48.50#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:48.50#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:35:48.56#abcon#<5=/03 3.4 7.0 23.40 701016.0\r\n> 2006.258.01:35:48.58#abcon#{5=INTERFACE CLEAR} 2006.258.01:35:48.62#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:35:48.62#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:35:48.62#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:35:48.62#ibcon#first serial, iclass 33, count 0 2006.258.01:35:48.62#ibcon#enter sib2, iclass 33, count 0 2006.258.01:35:48.62#ibcon#flushed, iclass 33, count 0 2006.258.01:35:48.62#ibcon#about to write, iclass 33, count 0 2006.258.01:35:48.62#ibcon#wrote, iclass 33, count 0 2006.258.01:35:48.62#ibcon#about to read 3, iclass 33, count 0 2006.258.01:35:48.64#ibcon#read 3, iclass 33, count 0 2006.258.01:35:48.64#ibcon#about to read 4, iclass 33, count 0 2006.258.01:35:48.64#ibcon#read 4, iclass 33, count 0 2006.258.01:35:48.64#ibcon#about to read 5, iclass 33, count 0 2006.258.01:35:48.64#ibcon#read 5, iclass 33, count 0 2006.258.01:35:48.64#ibcon#about to read 6, iclass 33, count 0 2006.258.01:35:48.64#ibcon#read 6, iclass 33, count 0 2006.258.01:35:48.64#ibcon#end of sib2, iclass 33, count 0 2006.258.01:35:48.64#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:35:48.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:35:48.64#ibcon#[25=USB\r\n] 2006.258.01:35:48.64#ibcon#*before write, iclass 33, count 0 2006.258.01:35:48.64#ibcon#enter sib2, iclass 33, count 0 2006.258.01:35:48.64#ibcon#flushed, iclass 33, count 0 2006.258.01:35:48.64#ibcon#about to write, iclass 33, count 0 2006.258.01:35:48.64#ibcon#wrote, iclass 33, count 0 2006.258.01:35:48.64#ibcon#about to read 3, iclass 33, count 0 2006.258.01:35:48.64#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:35:48.67#ibcon#read 3, iclass 33, count 0 2006.258.01:35:48.67#ibcon#about to read 4, iclass 33, count 0 2006.258.01:35:48.67#ibcon#read 4, iclass 33, count 0 2006.258.01:35:48.67#ibcon#about to read 5, iclass 33, count 0 2006.258.01:35:48.67#ibcon#read 5, iclass 33, count 0 2006.258.01:35:48.67#ibcon#about to read 6, iclass 33, count 0 2006.258.01:35:48.67#ibcon#read 6, iclass 33, count 0 2006.258.01:35:48.67#ibcon#end of sib2, iclass 33, count 0 2006.258.01:35:48.67#ibcon#*after write, iclass 33, count 0 2006.258.01:35:48.67#ibcon#*before return 0, iclass 33, count 0 2006.258.01:35:48.67#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:35:48.67#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:35:48.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:35:48.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:35:48.67$vck44/valo=5,734.99 2006.258.01:35:48.67#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.01:35:48.67#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.01:35:48.67#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:48.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:48.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:48.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:48.67#ibcon#enter wrdev, iclass 38, count 0 2006.258.01:35:48.67#ibcon#first serial, iclass 38, count 0 2006.258.01:35:48.67#ibcon#enter sib2, iclass 38, count 0 2006.258.01:35:48.67#ibcon#flushed, iclass 38, count 0 2006.258.01:35:48.67#ibcon#about to write, iclass 38, count 0 2006.258.01:35:48.67#ibcon#wrote, iclass 38, count 0 2006.258.01:35:48.67#ibcon#about to read 3, iclass 38, count 0 2006.258.01:35:48.69#ibcon#read 3, iclass 38, count 0 2006.258.01:35:48.69#ibcon#about to read 4, iclass 38, count 0 2006.258.01:35:48.69#ibcon#read 4, iclass 38, count 0 2006.258.01:35:48.69#ibcon#about to read 5, iclass 38, count 0 2006.258.01:35:48.69#ibcon#read 5, iclass 38, count 0 2006.258.01:35:48.69#ibcon#about to read 6, iclass 38, count 0 2006.258.01:35:48.69#ibcon#read 6, iclass 38, count 0 2006.258.01:35:48.69#ibcon#end of sib2, iclass 38, count 0 2006.258.01:35:48.69#ibcon#*mode == 0, iclass 38, count 0 2006.258.01:35:48.69#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.01:35:48.69#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.01:35:48.69#ibcon#*before write, iclass 38, count 0 2006.258.01:35:48.69#ibcon#enter sib2, iclass 38, count 0 2006.258.01:35:48.69#ibcon#flushed, iclass 38, count 0 2006.258.01:35:48.69#ibcon#about to write, iclass 38, count 0 2006.258.01:35:48.69#ibcon#wrote, iclass 38, count 0 2006.258.01:35:48.69#ibcon#about to read 3, iclass 38, count 0 2006.258.01:35:48.73#ibcon#read 3, iclass 38, count 0 2006.258.01:35:48.73#ibcon#about to read 4, iclass 38, count 0 2006.258.01:35:48.73#ibcon#read 4, iclass 38, count 0 2006.258.01:35:48.73#ibcon#about to read 5, iclass 38, count 0 2006.258.01:35:48.73#ibcon#read 5, iclass 38, count 0 2006.258.01:35:48.73#ibcon#about to read 6, iclass 38, count 0 2006.258.01:35:48.73#ibcon#read 6, iclass 38, count 0 2006.258.01:35:48.73#ibcon#end of sib2, iclass 38, count 0 2006.258.01:35:48.73#ibcon#*after write, iclass 38, count 0 2006.258.01:35:48.73#ibcon#*before return 0, iclass 38, count 0 2006.258.01:35:48.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:48.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:48.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.01:35:48.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.01:35:48.73$vck44/va=5,4 2006.258.01:35:48.73#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.258.01:35:48.73#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.258.01:35:48.73#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:48.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:48.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:48.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:48.79#ibcon#enter wrdev, iclass 40, count 2 2006.258.01:35:48.79#ibcon#first serial, iclass 40, count 2 2006.258.01:35:48.79#ibcon#enter sib2, iclass 40, count 2 2006.258.01:35:48.79#ibcon#flushed, iclass 40, count 2 2006.258.01:35:48.79#ibcon#about to write, iclass 40, count 2 2006.258.01:35:48.79#ibcon#wrote, iclass 40, count 2 2006.258.01:35:48.79#ibcon#about to read 3, iclass 40, count 2 2006.258.01:35:48.81#ibcon#read 3, iclass 40, count 2 2006.258.01:35:48.81#ibcon#about to read 4, iclass 40, count 2 2006.258.01:35:48.81#ibcon#read 4, iclass 40, count 2 2006.258.01:35:48.81#ibcon#about to read 5, iclass 40, count 2 2006.258.01:35:48.81#ibcon#read 5, iclass 40, count 2 2006.258.01:35:48.81#ibcon#about to read 6, iclass 40, count 2 2006.258.01:35:48.81#ibcon#read 6, iclass 40, count 2 2006.258.01:35:48.81#ibcon#end of sib2, iclass 40, count 2 2006.258.01:35:48.81#ibcon#*mode == 0, iclass 40, count 2 2006.258.01:35:48.81#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.258.01:35:48.81#ibcon#[25=AT05-04\r\n] 2006.258.01:35:48.81#ibcon#*before write, iclass 40, count 2 2006.258.01:35:48.81#ibcon#enter sib2, iclass 40, count 2 2006.258.01:35:48.81#ibcon#flushed, iclass 40, count 2 2006.258.01:35:48.81#ibcon#about to write, iclass 40, count 2 2006.258.01:35:48.81#ibcon#wrote, iclass 40, count 2 2006.258.01:35:48.81#ibcon#about to read 3, iclass 40, count 2 2006.258.01:35:48.84#ibcon#read 3, iclass 40, count 2 2006.258.01:35:48.84#ibcon#about to read 4, iclass 40, count 2 2006.258.01:35:48.84#ibcon#read 4, iclass 40, count 2 2006.258.01:35:48.84#ibcon#about to read 5, iclass 40, count 2 2006.258.01:35:48.84#ibcon#read 5, iclass 40, count 2 2006.258.01:35:48.84#ibcon#about to read 6, iclass 40, count 2 2006.258.01:35:48.84#ibcon#read 6, iclass 40, count 2 2006.258.01:35:48.84#ibcon#end of sib2, iclass 40, count 2 2006.258.01:35:48.84#ibcon#*after write, iclass 40, count 2 2006.258.01:35:48.84#ibcon#*before return 0, iclass 40, count 2 2006.258.01:35:48.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:48.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:48.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.258.01:35:48.84#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:48.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:48.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:48.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:48.96#ibcon#enter wrdev, iclass 40, count 0 2006.258.01:35:48.96#ibcon#first serial, iclass 40, count 0 2006.258.01:35:48.96#ibcon#enter sib2, iclass 40, count 0 2006.258.01:35:48.96#ibcon#flushed, iclass 40, count 0 2006.258.01:35:48.96#ibcon#about to write, iclass 40, count 0 2006.258.01:35:48.96#ibcon#wrote, iclass 40, count 0 2006.258.01:35:48.96#ibcon#about to read 3, iclass 40, count 0 2006.258.01:35:48.98#ibcon#read 3, iclass 40, count 0 2006.258.01:35:48.98#ibcon#about to read 4, iclass 40, count 0 2006.258.01:35:48.98#ibcon#read 4, iclass 40, count 0 2006.258.01:35:48.98#ibcon#about to read 5, iclass 40, count 0 2006.258.01:35:48.98#ibcon#read 5, iclass 40, count 0 2006.258.01:35:48.98#ibcon#about to read 6, iclass 40, count 0 2006.258.01:35:48.98#ibcon#read 6, iclass 40, count 0 2006.258.01:35:48.98#ibcon#end of sib2, iclass 40, count 0 2006.258.01:35:48.98#ibcon#*mode == 0, iclass 40, count 0 2006.258.01:35:48.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.01:35:48.98#ibcon#[25=USB\r\n] 2006.258.01:35:48.98#ibcon#*before write, iclass 40, count 0 2006.258.01:35:48.98#ibcon#enter sib2, iclass 40, count 0 2006.258.01:35:48.98#ibcon#flushed, iclass 40, count 0 2006.258.01:35:48.98#ibcon#about to write, iclass 40, count 0 2006.258.01:35:48.98#ibcon#wrote, iclass 40, count 0 2006.258.01:35:48.98#ibcon#about to read 3, iclass 40, count 0 2006.258.01:35:49.01#ibcon#read 3, iclass 40, count 0 2006.258.01:35:49.01#ibcon#about to read 4, iclass 40, count 0 2006.258.01:35:49.01#ibcon#read 4, iclass 40, count 0 2006.258.01:35:49.01#ibcon#about to read 5, iclass 40, count 0 2006.258.01:35:49.01#ibcon#read 5, iclass 40, count 0 2006.258.01:35:49.01#ibcon#about to read 6, iclass 40, count 0 2006.258.01:35:49.01#ibcon#read 6, iclass 40, count 0 2006.258.01:35:49.01#ibcon#end of sib2, iclass 40, count 0 2006.258.01:35:49.01#ibcon#*after write, iclass 40, count 0 2006.258.01:35:49.01#ibcon#*before return 0, iclass 40, count 0 2006.258.01:35:49.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:49.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:49.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.01:35:49.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.01:35:49.01$vck44/valo=6,814.99 2006.258.01:35:49.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.258.01:35:49.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.258.01:35:49.01#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:49.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:49.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:49.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:49.01#ibcon#enter wrdev, iclass 4, count 0 2006.258.01:35:49.01#ibcon#first serial, iclass 4, count 0 2006.258.01:35:49.01#ibcon#enter sib2, iclass 4, count 0 2006.258.01:35:49.01#ibcon#flushed, iclass 4, count 0 2006.258.01:35:49.01#ibcon#about to write, iclass 4, count 0 2006.258.01:35:49.01#ibcon#wrote, iclass 4, count 0 2006.258.01:35:49.01#ibcon#about to read 3, iclass 4, count 0 2006.258.01:35:49.03#ibcon#read 3, iclass 4, count 0 2006.258.01:35:49.03#ibcon#about to read 4, iclass 4, count 0 2006.258.01:35:49.03#ibcon#read 4, iclass 4, count 0 2006.258.01:35:49.03#ibcon#about to read 5, iclass 4, count 0 2006.258.01:35:49.03#ibcon#read 5, iclass 4, count 0 2006.258.01:35:49.03#ibcon#about to read 6, iclass 4, count 0 2006.258.01:35:49.03#ibcon#read 6, iclass 4, count 0 2006.258.01:35:49.03#ibcon#end of sib2, iclass 4, count 0 2006.258.01:35:49.03#ibcon#*mode == 0, iclass 4, count 0 2006.258.01:35:49.03#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.01:35:49.03#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.01:35:49.03#ibcon#*before write, iclass 4, count 0 2006.258.01:35:49.03#ibcon#enter sib2, iclass 4, count 0 2006.258.01:35:49.03#ibcon#flushed, iclass 4, count 0 2006.258.01:35:49.03#ibcon#about to write, iclass 4, count 0 2006.258.01:35:49.03#ibcon#wrote, iclass 4, count 0 2006.258.01:35:49.03#ibcon#about to read 3, iclass 4, count 0 2006.258.01:35:49.07#ibcon#read 3, iclass 4, count 0 2006.258.01:35:49.07#ibcon#about to read 4, iclass 4, count 0 2006.258.01:35:49.07#ibcon#read 4, iclass 4, count 0 2006.258.01:35:49.07#ibcon#about to read 5, iclass 4, count 0 2006.258.01:35:49.07#ibcon#read 5, iclass 4, count 0 2006.258.01:35:49.07#ibcon#about to read 6, iclass 4, count 0 2006.258.01:35:49.07#ibcon#read 6, iclass 4, count 0 2006.258.01:35:49.07#ibcon#end of sib2, iclass 4, count 0 2006.258.01:35:49.07#ibcon#*after write, iclass 4, count 0 2006.258.01:35:49.07#ibcon#*before return 0, iclass 4, count 0 2006.258.01:35:49.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:49.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:49.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.01:35:49.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.01:35:49.07$vck44/va=6,4 2006.258.01:35:49.07#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.258.01:35:49.07#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.258.01:35:49.07#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:49.07#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:49.13#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:49.13#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:49.13#ibcon#enter wrdev, iclass 6, count 2 2006.258.01:35:49.13#ibcon#first serial, iclass 6, count 2 2006.258.01:35:49.13#ibcon#enter sib2, iclass 6, count 2 2006.258.01:35:49.13#ibcon#flushed, iclass 6, count 2 2006.258.01:35:49.13#ibcon#about to write, iclass 6, count 2 2006.258.01:35:49.13#ibcon#wrote, iclass 6, count 2 2006.258.01:35:49.13#ibcon#about to read 3, iclass 6, count 2 2006.258.01:35:49.15#ibcon#read 3, iclass 6, count 2 2006.258.01:35:49.15#ibcon#about to read 4, iclass 6, count 2 2006.258.01:35:49.15#ibcon#read 4, iclass 6, count 2 2006.258.01:35:49.15#ibcon#about to read 5, iclass 6, count 2 2006.258.01:35:49.15#ibcon#read 5, iclass 6, count 2 2006.258.01:35:49.15#ibcon#about to read 6, iclass 6, count 2 2006.258.01:35:49.15#ibcon#read 6, iclass 6, count 2 2006.258.01:35:49.15#ibcon#end of sib2, iclass 6, count 2 2006.258.01:35:49.15#ibcon#*mode == 0, iclass 6, count 2 2006.258.01:35:49.15#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.258.01:35:49.15#ibcon#[25=AT06-04\r\n] 2006.258.01:35:49.15#ibcon#*before write, iclass 6, count 2 2006.258.01:35:49.15#ibcon#enter sib2, iclass 6, count 2 2006.258.01:35:49.15#ibcon#flushed, iclass 6, count 2 2006.258.01:35:49.15#ibcon#about to write, iclass 6, count 2 2006.258.01:35:49.15#ibcon#wrote, iclass 6, count 2 2006.258.01:35:49.15#ibcon#about to read 3, iclass 6, count 2 2006.258.01:35:49.18#ibcon#read 3, iclass 6, count 2 2006.258.01:35:49.18#ibcon#about to read 4, iclass 6, count 2 2006.258.01:35:49.18#ibcon#read 4, iclass 6, count 2 2006.258.01:35:49.18#ibcon#about to read 5, iclass 6, count 2 2006.258.01:35:49.18#ibcon#read 5, iclass 6, count 2 2006.258.01:35:49.18#ibcon#about to read 6, iclass 6, count 2 2006.258.01:35:49.18#ibcon#read 6, iclass 6, count 2 2006.258.01:35:49.18#ibcon#end of sib2, iclass 6, count 2 2006.258.01:35:49.18#ibcon#*after write, iclass 6, count 2 2006.258.01:35:49.18#ibcon#*before return 0, iclass 6, count 2 2006.258.01:35:49.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:49.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:49.18#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.258.01:35:49.18#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:49.18#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:49.30#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:49.30#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:49.30#ibcon#enter wrdev, iclass 6, count 0 2006.258.01:35:49.30#ibcon#first serial, iclass 6, count 0 2006.258.01:35:49.30#ibcon#enter sib2, iclass 6, count 0 2006.258.01:35:49.30#ibcon#flushed, iclass 6, count 0 2006.258.01:35:49.30#ibcon#about to write, iclass 6, count 0 2006.258.01:35:49.30#ibcon#wrote, iclass 6, count 0 2006.258.01:35:49.30#ibcon#about to read 3, iclass 6, count 0 2006.258.01:35:49.32#ibcon#read 3, iclass 6, count 0 2006.258.01:35:49.32#ibcon#about to read 4, iclass 6, count 0 2006.258.01:35:49.32#ibcon#read 4, iclass 6, count 0 2006.258.01:35:49.32#ibcon#about to read 5, iclass 6, count 0 2006.258.01:35:49.32#ibcon#read 5, iclass 6, count 0 2006.258.01:35:49.32#ibcon#about to read 6, iclass 6, count 0 2006.258.01:35:49.32#ibcon#read 6, iclass 6, count 0 2006.258.01:35:49.32#ibcon#end of sib2, iclass 6, count 0 2006.258.01:35:49.32#ibcon#*mode == 0, iclass 6, count 0 2006.258.01:35:49.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.01:35:49.32#ibcon#[25=USB\r\n] 2006.258.01:35:49.32#ibcon#*before write, iclass 6, count 0 2006.258.01:35:49.32#ibcon#enter sib2, iclass 6, count 0 2006.258.01:35:49.32#ibcon#flushed, iclass 6, count 0 2006.258.01:35:49.32#ibcon#about to write, iclass 6, count 0 2006.258.01:35:49.32#ibcon#wrote, iclass 6, count 0 2006.258.01:35:49.32#ibcon#about to read 3, iclass 6, count 0 2006.258.01:35:49.35#ibcon#read 3, iclass 6, count 0 2006.258.01:35:49.35#ibcon#about to read 4, iclass 6, count 0 2006.258.01:35:49.35#ibcon#read 4, iclass 6, count 0 2006.258.01:35:49.35#ibcon#about to read 5, iclass 6, count 0 2006.258.01:35:49.35#ibcon#read 5, iclass 6, count 0 2006.258.01:35:49.35#ibcon#about to read 6, iclass 6, count 0 2006.258.01:35:49.35#ibcon#read 6, iclass 6, count 0 2006.258.01:35:49.35#ibcon#end of sib2, iclass 6, count 0 2006.258.01:35:49.35#ibcon#*after write, iclass 6, count 0 2006.258.01:35:49.35#ibcon#*before return 0, iclass 6, count 0 2006.258.01:35:49.35#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:49.35#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:49.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.01:35:49.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.01:35:49.35$vck44/valo=7,864.99 2006.258.01:35:49.35#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.258.01:35:49.35#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.258.01:35:49.35#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:49.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:49.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:49.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:49.35#ibcon#enter wrdev, iclass 10, count 0 2006.258.01:35:49.35#ibcon#first serial, iclass 10, count 0 2006.258.01:35:49.35#ibcon#enter sib2, iclass 10, count 0 2006.258.01:35:49.35#ibcon#flushed, iclass 10, count 0 2006.258.01:35:49.35#ibcon#about to write, iclass 10, count 0 2006.258.01:35:49.35#ibcon#wrote, iclass 10, count 0 2006.258.01:35:49.35#ibcon#about to read 3, iclass 10, count 0 2006.258.01:35:49.37#ibcon#read 3, iclass 10, count 0 2006.258.01:35:49.37#ibcon#about to read 4, iclass 10, count 0 2006.258.01:35:49.37#ibcon#read 4, iclass 10, count 0 2006.258.01:35:49.37#ibcon#about to read 5, iclass 10, count 0 2006.258.01:35:49.37#ibcon#read 5, iclass 10, count 0 2006.258.01:35:49.37#ibcon#about to read 6, iclass 10, count 0 2006.258.01:35:49.37#ibcon#read 6, iclass 10, count 0 2006.258.01:35:49.37#ibcon#end of sib2, iclass 10, count 0 2006.258.01:35:49.37#ibcon#*mode == 0, iclass 10, count 0 2006.258.01:35:49.37#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.01:35:49.37#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.01:35:49.37#ibcon#*before write, iclass 10, count 0 2006.258.01:35:49.37#ibcon#enter sib2, iclass 10, count 0 2006.258.01:35:49.37#ibcon#flushed, iclass 10, count 0 2006.258.01:35:49.37#ibcon#about to write, iclass 10, count 0 2006.258.01:35:49.37#ibcon#wrote, iclass 10, count 0 2006.258.01:35:49.37#ibcon#about to read 3, iclass 10, count 0 2006.258.01:35:49.41#ibcon#read 3, iclass 10, count 0 2006.258.01:35:49.41#ibcon#about to read 4, iclass 10, count 0 2006.258.01:35:49.41#ibcon#read 4, iclass 10, count 0 2006.258.01:35:49.41#ibcon#about to read 5, iclass 10, count 0 2006.258.01:35:49.41#ibcon#read 5, iclass 10, count 0 2006.258.01:35:49.41#ibcon#about to read 6, iclass 10, count 0 2006.258.01:35:49.41#ibcon#read 6, iclass 10, count 0 2006.258.01:35:49.41#ibcon#end of sib2, iclass 10, count 0 2006.258.01:35:49.41#ibcon#*after write, iclass 10, count 0 2006.258.01:35:49.41#ibcon#*before return 0, iclass 10, count 0 2006.258.01:35:49.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:49.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:49.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.01:35:49.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.01:35:49.41$vck44/va=7,4 2006.258.01:35:49.41#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.258.01:35:49.41#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.258.01:35:49.41#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:49.41#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:49.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:49.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:49.47#ibcon#enter wrdev, iclass 12, count 2 2006.258.01:35:49.47#ibcon#first serial, iclass 12, count 2 2006.258.01:35:49.47#ibcon#enter sib2, iclass 12, count 2 2006.258.01:35:49.47#ibcon#flushed, iclass 12, count 2 2006.258.01:35:49.47#ibcon#about to write, iclass 12, count 2 2006.258.01:35:49.47#ibcon#wrote, iclass 12, count 2 2006.258.01:35:49.47#ibcon#about to read 3, iclass 12, count 2 2006.258.01:35:49.49#ibcon#read 3, iclass 12, count 2 2006.258.01:35:49.49#ibcon#about to read 4, iclass 12, count 2 2006.258.01:35:49.49#ibcon#read 4, iclass 12, count 2 2006.258.01:35:49.49#ibcon#about to read 5, iclass 12, count 2 2006.258.01:35:49.49#ibcon#read 5, iclass 12, count 2 2006.258.01:35:49.49#ibcon#about to read 6, iclass 12, count 2 2006.258.01:35:49.49#ibcon#read 6, iclass 12, count 2 2006.258.01:35:49.49#ibcon#end of sib2, iclass 12, count 2 2006.258.01:35:49.49#ibcon#*mode == 0, iclass 12, count 2 2006.258.01:35:49.49#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.258.01:35:49.49#ibcon#[25=AT07-04\r\n] 2006.258.01:35:49.49#ibcon#*before write, iclass 12, count 2 2006.258.01:35:49.49#ibcon#enter sib2, iclass 12, count 2 2006.258.01:35:49.49#ibcon#flushed, iclass 12, count 2 2006.258.01:35:49.49#ibcon#about to write, iclass 12, count 2 2006.258.01:35:49.49#ibcon#wrote, iclass 12, count 2 2006.258.01:35:49.49#ibcon#about to read 3, iclass 12, count 2 2006.258.01:35:49.52#ibcon#read 3, iclass 12, count 2 2006.258.01:35:49.52#ibcon#about to read 4, iclass 12, count 2 2006.258.01:35:49.52#ibcon#read 4, iclass 12, count 2 2006.258.01:35:49.52#ibcon#about to read 5, iclass 12, count 2 2006.258.01:35:49.52#ibcon#read 5, iclass 12, count 2 2006.258.01:35:49.52#ibcon#about to read 6, iclass 12, count 2 2006.258.01:35:49.52#ibcon#read 6, iclass 12, count 2 2006.258.01:35:49.52#ibcon#end of sib2, iclass 12, count 2 2006.258.01:35:49.52#ibcon#*after write, iclass 12, count 2 2006.258.01:35:49.56#ibcon#*before return 0, iclass 12, count 2 2006.258.01:35:49.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:49.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:49.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.258.01:35:49.56#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:49.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:49.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:49.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:49.68#ibcon#enter wrdev, iclass 12, count 0 2006.258.01:35:49.68#ibcon#first serial, iclass 12, count 0 2006.258.01:35:49.68#ibcon#enter sib2, iclass 12, count 0 2006.258.01:35:49.68#ibcon#flushed, iclass 12, count 0 2006.258.01:35:49.68#ibcon#about to write, iclass 12, count 0 2006.258.01:35:49.68#ibcon#wrote, iclass 12, count 0 2006.258.01:35:49.68#ibcon#about to read 3, iclass 12, count 0 2006.258.01:35:49.70#ibcon#read 3, iclass 12, count 0 2006.258.01:35:49.70#ibcon#about to read 4, iclass 12, count 0 2006.258.01:35:49.70#ibcon#read 4, iclass 12, count 0 2006.258.01:35:49.70#ibcon#about to read 5, iclass 12, count 0 2006.258.01:35:49.70#ibcon#read 5, iclass 12, count 0 2006.258.01:35:49.70#ibcon#about to read 6, iclass 12, count 0 2006.258.01:35:49.70#ibcon#read 6, iclass 12, count 0 2006.258.01:35:49.70#ibcon#end of sib2, iclass 12, count 0 2006.258.01:35:49.70#ibcon#*mode == 0, iclass 12, count 0 2006.258.01:35:49.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.01:35:49.70#ibcon#[25=USB\r\n] 2006.258.01:35:49.70#ibcon#*before write, iclass 12, count 0 2006.258.01:35:49.70#ibcon#enter sib2, iclass 12, count 0 2006.258.01:35:49.70#ibcon#flushed, iclass 12, count 0 2006.258.01:35:49.70#ibcon#about to write, iclass 12, count 0 2006.258.01:35:49.70#ibcon#wrote, iclass 12, count 0 2006.258.01:35:49.70#ibcon#about to read 3, iclass 12, count 0 2006.258.01:35:49.73#ibcon#read 3, iclass 12, count 0 2006.258.01:35:49.73#ibcon#about to read 4, iclass 12, count 0 2006.258.01:35:49.73#ibcon#read 4, iclass 12, count 0 2006.258.01:35:49.73#ibcon#about to read 5, iclass 12, count 0 2006.258.01:35:49.73#ibcon#read 5, iclass 12, count 0 2006.258.01:35:49.73#ibcon#about to read 6, iclass 12, count 0 2006.258.01:35:49.73#ibcon#read 6, iclass 12, count 0 2006.258.01:35:49.73#ibcon#end of sib2, iclass 12, count 0 2006.258.01:35:49.73#ibcon#*after write, iclass 12, count 0 2006.258.01:35:49.73#ibcon#*before return 0, iclass 12, count 0 2006.258.01:35:49.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:49.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:49.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.01:35:49.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.01:35:49.73$vck44/valo=8,884.99 2006.258.01:35:49.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.01:35:49.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.01:35:49.73#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:49.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:49.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:49.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:49.73#ibcon#enter wrdev, iclass 14, count 0 2006.258.01:35:49.73#ibcon#first serial, iclass 14, count 0 2006.258.01:35:49.73#ibcon#enter sib2, iclass 14, count 0 2006.258.01:35:49.73#ibcon#flushed, iclass 14, count 0 2006.258.01:35:49.73#ibcon#about to write, iclass 14, count 0 2006.258.01:35:49.73#ibcon#wrote, iclass 14, count 0 2006.258.01:35:49.73#ibcon#about to read 3, iclass 14, count 0 2006.258.01:35:49.75#ibcon#read 3, iclass 14, count 0 2006.258.01:35:49.75#ibcon#about to read 4, iclass 14, count 0 2006.258.01:35:49.75#ibcon#read 4, iclass 14, count 0 2006.258.01:35:49.75#ibcon#about to read 5, iclass 14, count 0 2006.258.01:35:49.75#ibcon#read 5, iclass 14, count 0 2006.258.01:35:49.75#ibcon#about to read 6, iclass 14, count 0 2006.258.01:35:49.75#ibcon#read 6, iclass 14, count 0 2006.258.01:35:49.75#ibcon#end of sib2, iclass 14, count 0 2006.258.01:35:49.75#ibcon#*mode == 0, iclass 14, count 0 2006.258.01:35:49.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.01:35:49.75#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.01:35:49.75#ibcon#*before write, iclass 14, count 0 2006.258.01:35:49.75#ibcon#enter sib2, iclass 14, count 0 2006.258.01:35:49.75#ibcon#flushed, iclass 14, count 0 2006.258.01:35:49.75#ibcon#about to write, iclass 14, count 0 2006.258.01:35:49.75#ibcon#wrote, iclass 14, count 0 2006.258.01:35:49.75#ibcon#about to read 3, iclass 14, count 0 2006.258.01:35:49.79#ibcon#read 3, iclass 14, count 0 2006.258.01:35:49.79#ibcon#about to read 4, iclass 14, count 0 2006.258.01:35:49.79#ibcon#read 4, iclass 14, count 0 2006.258.01:35:49.79#ibcon#about to read 5, iclass 14, count 0 2006.258.01:35:49.79#ibcon#read 5, iclass 14, count 0 2006.258.01:35:49.79#ibcon#about to read 6, iclass 14, count 0 2006.258.01:35:49.79#ibcon#read 6, iclass 14, count 0 2006.258.01:35:49.79#ibcon#end of sib2, iclass 14, count 0 2006.258.01:35:49.79#ibcon#*after write, iclass 14, count 0 2006.258.01:35:49.79#ibcon#*before return 0, iclass 14, count 0 2006.258.01:35:49.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:49.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:49.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.01:35:49.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.01:35:49.79$vck44/va=8,4 2006.258.01:35:49.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.258.01:35:49.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.258.01:35:49.79#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:49.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:35:49.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:35:49.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:35:49.85#ibcon#enter wrdev, iclass 16, count 2 2006.258.01:35:49.85#ibcon#first serial, iclass 16, count 2 2006.258.01:35:49.85#ibcon#enter sib2, iclass 16, count 2 2006.258.01:35:49.85#ibcon#flushed, iclass 16, count 2 2006.258.01:35:49.85#ibcon#about to write, iclass 16, count 2 2006.258.01:35:49.85#ibcon#wrote, iclass 16, count 2 2006.258.01:35:49.85#ibcon#about to read 3, iclass 16, count 2 2006.258.01:35:49.87#ibcon#read 3, iclass 16, count 2 2006.258.01:35:49.87#ibcon#about to read 4, iclass 16, count 2 2006.258.01:35:49.87#ibcon#read 4, iclass 16, count 2 2006.258.01:35:49.87#ibcon#about to read 5, iclass 16, count 2 2006.258.01:35:49.87#ibcon#read 5, iclass 16, count 2 2006.258.01:35:49.87#ibcon#about to read 6, iclass 16, count 2 2006.258.01:35:49.87#ibcon#read 6, iclass 16, count 2 2006.258.01:35:49.87#ibcon#end of sib2, iclass 16, count 2 2006.258.01:35:49.87#ibcon#*mode == 0, iclass 16, count 2 2006.258.01:35:49.87#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.258.01:35:49.87#ibcon#[25=AT08-04\r\n] 2006.258.01:35:49.87#ibcon#*before write, iclass 16, count 2 2006.258.01:35:49.87#ibcon#enter sib2, iclass 16, count 2 2006.258.01:35:49.87#ibcon#flushed, iclass 16, count 2 2006.258.01:35:49.87#ibcon#about to write, iclass 16, count 2 2006.258.01:35:49.87#ibcon#wrote, iclass 16, count 2 2006.258.01:35:49.87#ibcon#about to read 3, iclass 16, count 2 2006.258.01:35:49.90#ibcon#read 3, iclass 16, count 2 2006.258.01:35:49.90#ibcon#about to read 4, iclass 16, count 2 2006.258.01:35:49.90#ibcon#read 4, iclass 16, count 2 2006.258.01:35:49.90#ibcon#about to read 5, iclass 16, count 2 2006.258.01:35:49.90#ibcon#read 5, iclass 16, count 2 2006.258.01:35:49.90#ibcon#about to read 6, iclass 16, count 2 2006.258.01:35:49.90#ibcon#read 6, iclass 16, count 2 2006.258.01:35:49.90#ibcon#end of sib2, iclass 16, count 2 2006.258.01:35:49.90#ibcon#*after write, iclass 16, count 2 2006.258.01:35:49.90#ibcon#*before return 0, iclass 16, count 2 2006.258.01:35:49.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:35:49.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.258.01:35:49.90#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.258.01:35:49.90#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:49.90#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:35:50.02#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:35:50.02#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:35:50.02#ibcon#enter wrdev, iclass 16, count 0 2006.258.01:35:50.02#ibcon#first serial, iclass 16, count 0 2006.258.01:35:50.02#ibcon#enter sib2, iclass 16, count 0 2006.258.01:35:50.02#ibcon#flushed, iclass 16, count 0 2006.258.01:35:50.02#ibcon#about to write, iclass 16, count 0 2006.258.01:35:50.02#ibcon#wrote, iclass 16, count 0 2006.258.01:35:50.02#ibcon#about to read 3, iclass 16, count 0 2006.258.01:35:50.04#ibcon#read 3, iclass 16, count 0 2006.258.01:35:50.04#ibcon#about to read 4, iclass 16, count 0 2006.258.01:35:50.04#ibcon#read 4, iclass 16, count 0 2006.258.01:35:50.04#ibcon#about to read 5, iclass 16, count 0 2006.258.01:35:50.04#ibcon#read 5, iclass 16, count 0 2006.258.01:35:50.04#ibcon#about to read 6, iclass 16, count 0 2006.258.01:35:50.04#ibcon#read 6, iclass 16, count 0 2006.258.01:35:50.04#ibcon#end of sib2, iclass 16, count 0 2006.258.01:35:50.04#ibcon#*mode == 0, iclass 16, count 0 2006.258.01:35:50.04#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.01:35:50.04#ibcon#[25=USB\r\n] 2006.258.01:35:50.04#ibcon#*before write, iclass 16, count 0 2006.258.01:35:50.04#ibcon#enter sib2, iclass 16, count 0 2006.258.01:35:50.04#ibcon#flushed, iclass 16, count 0 2006.258.01:35:50.04#ibcon#about to write, iclass 16, count 0 2006.258.01:35:50.04#ibcon#wrote, iclass 16, count 0 2006.258.01:35:50.04#ibcon#about to read 3, iclass 16, count 0 2006.258.01:35:50.07#ibcon#read 3, iclass 16, count 0 2006.258.01:35:50.07#ibcon#about to read 4, iclass 16, count 0 2006.258.01:35:50.07#ibcon#read 4, iclass 16, count 0 2006.258.01:35:50.07#ibcon#about to read 5, iclass 16, count 0 2006.258.01:35:50.07#ibcon#read 5, iclass 16, count 0 2006.258.01:35:50.07#ibcon#about to read 6, iclass 16, count 0 2006.258.01:35:50.07#ibcon#read 6, iclass 16, count 0 2006.258.01:35:50.07#ibcon#end of sib2, iclass 16, count 0 2006.258.01:35:50.07#ibcon#*after write, iclass 16, count 0 2006.258.01:35:50.07#ibcon#*before return 0, iclass 16, count 0 2006.258.01:35:50.07#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:35:50.07#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.258.01:35:50.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.01:35:50.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.01:35:50.07$vck44/vblo=1,629.99 2006.258.01:35:50.07#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.258.01:35:50.07#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.258.01:35:50.07#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:50.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:50.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:50.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:50.07#ibcon#enter wrdev, iclass 18, count 0 2006.258.01:35:50.07#ibcon#first serial, iclass 18, count 0 2006.258.01:35:50.07#ibcon#enter sib2, iclass 18, count 0 2006.258.01:35:50.07#ibcon#flushed, iclass 18, count 0 2006.258.01:35:50.07#ibcon#about to write, iclass 18, count 0 2006.258.01:35:50.07#ibcon#wrote, iclass 18, count 0 2006.258.01:35:50.07#ibcon#about to read 3, iclass 18, count 0 2006.258.01:35:50.09#ibcon#read 3, iclass 18, count 0 2006.258.01:35:50.09#ibcon#about to read 4, iclass 18, count 0 2006.258.01:35:50.09#ibcon#read 4, iclass 18, count 0 2006.258.01:35:50.09#ibcon#about to read 5, iclass 18, count 0 2006.258.01:35:50.09#ibcon#read 5, iclass 18, count 0 2006.258.01:35:50.09#ibcon#about to read 6, iclass 18, count 0 2006.258.01:35:50.09#ibcon#read 6, iclass 18, count 0 2006.258.01:35:50.09#ibcon#end of sib2, iclass 18, count 0 2006.258.01:35:50.09#ibcon#*mode == 0, iclass 18, count 0 2006.258.01:35:50.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.258.01:35:50.09#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.01:35:50.09#ibcon#*before write, iclass 18, count 0 2006.258.01:35:50.09#ibcon#enter sib2, iclass 18, count 0 2006.258.01:35:50.09#ibcon#flushed, iclass 18, count 0 2006.258.01:35:50.09#ibcon#about to write, iclass 18, count 0 2006.258.01:35:50.09#ibcon#wrote, iclass 18, count 0 2006.258.01:35:50.09#ibcon#about to read 3, iclass 18, count 0 2006.258.01:35:50.13#ibcon#read 3, iclass 18, count 0 2006.258.01:35:50.13#ibcon#about to read 4, iclass 18, count 0 2006.258.01:35:50.13#ibcon#read 4, iclass 18, count 0 2006.258.01:35:50.13#ibcon#about to read 5, iclass 18, count 0 2006.258.01:35:50.13#ibcon#read 5, iclass 18, count 0 2006.258.01:35:50.13#ibcon#about to read 6, iclass 18, count 0 2006.258.01:35:50.13#ibcon#read 6, iclass 18, count 0 2006.258.01:35:50.13#ibcon#end of sib2, iclass 18, count 0 2006.258.01:35:50.13#ibcon#*after write, iclass 18, count 0 2006.258.01:35:50.13#ibcon#*before return 0, iclass 18, count 0 2006.258.01:35:50.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:50.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.258.01:35:50.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.258.01:35:50.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.258.01:35:50.13$vck44/vb=1,4 2006.258.01:35:50.13#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.258.01:35:50.13#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.258.01:35:50.13#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:50.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:50.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:50.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:50.13#ibcon#enter wrdev, iclass 20, count 2 2006.258.01:35:50.13#ibcon#first serial, iclass 20, count 2 2006.258.01:35:50.13#ibcon#enter sib2, iclass 20, count 2 2006.258.01:35:50.13#ibcon#flushed, iclass 20, count 2 2006.258.01:35:50.13#ibcon#about to write, iclass 20, count 2 2006.258.01:35:50.13#ibcon#wrote, iclass 20, count 2 2006.258.01:35:50.13#ibcon#about to read 3, iclass 20, count 2 2006.258.01:35:50.15#ibcon#read 3, iclass 20, count 2 2006.258.01:35:50.15#ibcon#about to read 4, iclass 20, count 2 2006.258.01:35:50.15#ibcon#read 4, iclass 20, count 2 2006.258.01:35:50.15#ibcon#about to read 5, iclass 20, count 2 2006.258.01:35:50.15#ibcon#read 5, iclass 20, count 2 2006.258.01:35:50.15#ibcon#about to read 6, iclass 20, count 2 2006.258.01:35:50.15#ibcon#read 6, iclass 20, count 2 2006.258.01:35:50.15#ibcon#end of sib2, iclass 20, count 2 2006.258.01:35:50.15#ibcon#*mode == 0, iclass 20, count 2 2006.258.01:35:50.15#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.258.01:35:50.15#ibcon#[27=AT01-04\r\n] 2006.258.01:35:50.15#ibcon#*before write, iclass 20, count 2 2006.258.01:35:50.15#ibcon#enter sib2, iclass 20, count 2 2006.258.01:35:50.15#ibcon#flushed, iclass 20, count 2 2006.258.01:35:50.15#ibcon#about to write, iclass 20, count 2 2006.258.01:35:50.15#ibcon#wrote, iclass 20, count 2 2006.258.01:35:50.15#ibcon#about to read 3, iclass 20, count 2 2006.258.01:35:50.18#ibcon#read 3, iclass 20, count 2 2006.258.01:35:50.18#ibcon#about to read 4, iclass 20, count 2 2006.258.01:35:50.18#ibcon#read 4, iclass 20, count 2 2006.258.01:35:50.18#ibcon#about to read 5, iclass 20, count 2 2006.258.01:35:50.18#ibcon#read 5, iclass 20, count 2 2006.258.01:35:50.18#ibcon#about to read 6, iclass 20, count 2 2006.258.01:35:50.18#ibcon#read 6, iclass 20, count 2 2006.258.01:35:50.18#ibcon#end of sib2, iclass 20, count 2 2006.258.01:35:50.18#ibcon#*after write, iclass 20, count 2 2006.258.01:35:50.18#ibcon#*before return 0, iclass 20, count 2 2006.258.01:35:50.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:50.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.258.01:35:50.18#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.258.01:35:50.18#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:50.18#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:50.30#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:50.30#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:50.30#ibcon#enter wrdev, iclass 20, count 0 2006.258.01:35:50.30#ibcon#first serial, iclass 20, count 0 2006.258.01:35:50.30#ibcon#enter sib2, iclass 20, count 0 2006.258.01:35:50.30#ibcon#flushed, iclass 20, count 0 2006.258.01:35:50.30#ibcon#about to write, iclass 20, count 0 2006.258.01:35:50.30#ibcon#wrote, iclass 20, count 0 2006.258.01:35:50.30#ibcon#about to read 3, iclass 20, count 0 2006.258.01:35:50.32#ibcon#read 3, iclass 20, count 0 2006.258.01:35:50.32#ibcon#about to read 4, iclass 20, count 0 2006.258.01:35:50.32#ibcon#read 4, iclass 20, count 0 2006.258.01:35:50.32#ibcon#about to read 5, iclass 20, count 0 2006.258.01:35:50.32#ibcon#read 5, iclass 20, count 0 2006.258.01:35:50.32#ibcon#about to read 6, iclass 20, count 0 2006.258.01:35:50.32#ibcon#read 6, iclass 20, count 0 2006.258.01:35:50.32#ibcon#end of sib2, iclass 20, count 0 2006.258.01:35:50.32#ibcon#*mode == 0, iclass 20, count 0 2006.258.01:35:50.32#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.01:35:50.32#ibcon#[27=USB\r\n] 2006.258.01:35:50.32#ibcon#*before write, iclass 20, count 0 2006.258.01:35:50.32#ibcon#enter sib2, iclass 20, count 0 2006.258.01:35:50.32#ibcon#flushed, iclass 20, count 0 2006.258.01:35:50.32#ibcon#about to write, iclass 20, count 0 2006.258.01:35:50.32#ibcon#wrote, iclass 20, count 0 2006.258.01:35:50.32#ibcon#about to read 3, iclass 20, count 0 2006.258.01:35:50.35#ibcon#read 3, iclass 20, count 0 2006.258.01:35:50.35#ibcon#about to read 4, iclass 20, count 0 2006.258.01:35:50.35#ibcon#read 4, iclass 20, count 0 2006.258.01:35:50.35#ibcon#about to read 5, iclass 20, count 0 2006.258.01:35:50.35#ibcon#read 5, iclass 20, count 0 2006.258.01:35:50.35#ibcon#about to read 6, iclass 20, count 0 2006.258.01:35:50.35#ibcon#read 6, iclass 20, count 0 2006.258.01:35:50.35#ibcon#end of sib2, iclass 20, count 0 2006.258.01:35:50.35#ibcon#*after write, iclass 20, count 0 2006.258.01:35:50.35#ibcon#*before return 0, iclass 20, count 0 2006.258.01:35:50.35#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:50.35#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.258.01:35:50.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.01:35:50.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.01:35:50.35$vck44/vblo=2,634.99 2006.258.01:35:50.35#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.258.01:35:50.35#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.258.01:35:50.35#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:50.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:50.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:50.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:50.35#ibcon#enter wrdev, iclass 22, count 0 2006.258.01:35:50.35#ibcon#first serial, iclass 22, count 0 2006.258.01:35:50.35#ibcon#enter sib2, iclass 22, count 0 2006.258.01:35:50.35#ibcon#flushed, iclass 22, count 0 2006.258.01:35:50.35#ibcon#about to write, iclass 22, count 0 2006.258.01:35:50.35#ibcon#wrote, iclass 22, count 0 2006.258.01:35:50.35#ibcon#about to read 3, iclass 22, count 0 2006.258.01:35:50.37#ibcon#read 3, iclass 22, count 0 2006.258.01:35:50.37#ibcon#about to read 4, iclass 22, count 0 2006.258.01:35:50.37#ibcon#read 4, iclass 22, count 0 2006.258.01:35:50.37#ibcon#about to read 5, iclass 22, count 0 2006.258.01:35:50.37#ibcon#read 5, iclass 22, count 0 2006.258.01:35:50.37#ibcon#about to read 6, iclass 22, count 0 2006.258.01:35:50.37#ibcon#read 6, iclass 22, count 0 2006.258.01:35:50.37#ibcon#end of sib2, iclass 22, count 0 2006.258.01:35:50.37#ibcon#*mode == 0, iclass 22, count 0 2006.258.01:35:50.37#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.258.01:35:50.37#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.01:35:50.37#ibcon#*before write, iclass 22, count 0 2006.258.01:35:50.37#ibcon#enter sib2, iclass 22, count 0 2006.258.01:35:50.37#ibcon#flushed, iclass 22, count 0 2006.258.01:35:50.37#ibcon#about to write, iclass 22, count 0 2006.258.01:35:50.37#ibcon#wrote, iclass 22, count 0 2006.258.01:35:50.37#ibcon#about to read 3, iclass 22, count 0 2006.258.01:35:50.41#ibcon#read 3, iclass 22, count 0 2006.258.01:35:50.41#ibcon#about to read 4, iclass 22, count 0 2006.258.01:35:50.41#ibcon#read 4, iclass 22, count 0 2006.258.01:35:50.41#ibcon#about to read 5, iclass 22, count 0 2006.258.01:35:50.41#ibcon#read 5, iclass 22, count 0 2006.258.01:35:50.41#ibcon#about to read 6, iclass 22, count 0 2006.258.01:35:50.41#ibcon#read 6, iclass 22, count 0 2006.258.01:35:50.41#ibcon#end of sib2, iclass 22, count 0 2006.258.01:35:50.41#ibcon#*after write, iclass 22, count 0 2006.258.01:35:50.41#ibcon#*before return 0, iclass 22, count 0 2006.258.01:35:50.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:50.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.258.01:35:50.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.258.01:35:50.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.258.01:35:50.41$vck44/vb=2,5 2006.258.01:35:50.41#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.01:35:50.41#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.01:35:50.41#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:50.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:50.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:50.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:50.47#ibcon#enter wrdev, iclass 24, count 2 2006.258.01:35:50.47#ibcon#first serial, iclass 24, count 2 2006.258.01:35:50.47#ibcon#enter sib2, iclass 24, count 2 2006.258.01:35:50.47#ibcon#flushed, iclass 24, count 2 2006.258.01:35:50.47#ibcon#about to write, iclass 24, count 2 2006.258.01:35:50.47#ibcon#wrote, iclass 24, count 2 2006.258.01:35:50.47#ibcon#about to read 3, iclass 24, count 2 2006.258.01:35:50.49#ibcon#read 3, iclass 24, count 2 2006.258.01:35:50.49#ibcon#about to read 4, iclass 24, count 2 2006.258.01:35:50.49#ibcon#read 4, iclass 24, count 2 2006.258.01:35:50.49#ibcon#about to read 5, iclass 24, count 2 2006.258.01:35:50.49#ibcon#read 5, iclass 24, count 2 2006.258.01:35:50.49#ibcon#about to read 6, iclass 24, count 2 2006.258.01:35:50.49#ibcon#read 6, iclass 24, count 2 2006.258.01:35:50.49#ibcon#end of sib2, iclass 24, count 2 2006.258.01:35:50.49#ibcon#*mode == 0, iclass 24, count 2 2006.258.01:35:50.49#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.01:35:50.49#ibcon#[27=AT02-05\r\n] 2006.258.01:35:50.49#ibcon#*before write, iclass 24, count 2 2006.258.01:35:50.49#ibcon#enter sib2, iclass 24, count 2 2006.258.01:35:50.49#ibcon#flushed, iclass 24, count 2 2006.258.01:35:50.49#ibcon#about to write, iclass 24, count 2 2006.258.01:35:50.49#ibcon#wrote, iclass 24, count 2 2006.258.01:35:50.49#ibcon#about to read 3, iclass 24, count 2 2006.258.01:35:50.52#ibcon#read 3, iclass 24, count 2 2006.258.01:35:50.52#ibcon#about to read 4, iclass 24, count 2 2006.258.01:35:50.52#ibcon#read 4, iclass 24, count 2 2006.258.01:35:50.52#ibcon#about to read 5, iclass 24, count 2 2006.258.01:35:50.52#ibcon#read 5, iclass 24, count 2 2006.258.01:35:50.52#ibcon#about to read 6, iclass 24, count 2 2006.258.01:35:50.52#ibcon#read 6, iclass 24, count 2 2006.258.01:35:50.52#ibcon#end of sib2, iclass 24, count 2 2006.258.01:35:50.52#ibcon#*after write, iclass 24, count 2 2006.258.01:35:50.52#ibcon#*before return 0, iclass 24, count 2 2006.258.01:35:50.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:50.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:35:50.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.01:35:50.66#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:50.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:50.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:50.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:50.78#ibcon#enter wrdev, iclass 24, count 0 2006.258.01:35:50.78#ibcon#first serial, iclass 24, count 0 2006.258.01:35:50.78#ibcon#enter sib2, iclass 24, count 0 2006.258.01:35:50.78#ibcon#flushed, iclass 24, count 0 2006.258.01:35:50.78#ibcon#about to write, iclass 24, count 0 2006.258.01:35:50.78#ibcon#wrote, iclass 24, count 0 2006.258.01:35:50.78#ibcon#about to read 3, iclass 24, count 0 2006.258.01:35:50.80#ibcon#read 3, iclass 24, count 0 2006.258.01:35:50.80#ibcon#about to read 4, iclass 24, count 0 2006.258.01:35:50.80#ibcon#read 4, iclass 24, count 0 2006.258.01:35:50.80#ibcon#about to read 5, iclass 24, count 0 2006.258.01:35:50.80#ibcon#read 5, iclass 24, count 0 2006.258.01:35:50.80#ibcon#about to read 6, iclass 24, count 0 2006.258.01:35:50.80#ibcon#read 6, iclass 24, count 0 2006.258.01:35:50.80#ibcon#end of sib2, iclass 24, count 0 2006.258.01:35:50.80#ibcon#*mode == 0, iclass 24, count 0 2006.258.01:35:50.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.01:35:50.80#ibcon#[27=USB\r\n] 2006.258.01:35:50.80#ibcon#*before write, iclass 24, count 0 2006.258.01:35:50.80#ibcon#enter sib2, iclass 24, count 0 2006.258.01:35:50.80#ibcon#flushed, iclass 24, count 0 2006.258.01:35:50.80#ibcon#about to write, iclass 24, count 0 2006.258.01:35:50.80#ibcon#wrote, iclass 24, count 0 2006.258.01:35:50.80#ibcon#about to read 3, iclass 24, count 0 2006.258.01:35:50.83#ibcon#read 3, iclass 24, count 0 2006.258.01:35:50.83#ibcon#about to read 4, iclass 24, count 0 2006.258.01:35:50.83#ibcon#read 4, iclass 24, count 0 2006.258.01:35:50.83#ibcon#about to read 5, iclass 24, count 0 2006.258.01:35:50.83#ibcon#read 5, iclass 24, count 0 2006.258.01:35:50.83#ibcon#about to read 6, iclass 24, count 0 2006.258.01:35:50.83#ibcon#read 6, iclass 24, count 0 2006.258.01:35:50.83#ibcon#end of sib2, iclass 24, count 0 2006.258.01:35:50.83#ibcon#*after write, iclass 24, count 0 2006.258.01:35:50.83#ibcon#*before return 0, iclass 24, count 0 2006.258.01:35:50.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:50.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:35:50.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.01:35:50.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.01:35:50.83$vck44/vblo=3,649.99 2006.258.01:35:50.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.258.01:35:50.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.258.01:35:50.83#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:50.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:50.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:50.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:50.83#ibcon#enter wrdev, iclass 26, count 0 2006.258.01:35:50.83#ibcon#first serial, iclass 26, count 0 2006.258.01:35:50.83#ibcon#enter sib2, iclass 26, count 0 2006.258.01:35:50.83#ibcon#flushed, iclass 26, count 0 2006.258.01:35:50.83#ibcon#about to write, iclass 26, count 0 2006.258.01:35:50.83#ibcon#wrote, iclass 26, count 0 2006.258.01:35:50.83#ibcon#about to read 3, iclass 26, count 0 2006.258.01:35:50.85#ibcon#read 3, iclass 26, count 0 2006.258.01:35:50.85#ibcon#about to read 4, iclass 26, count 0 2006.258.01:35:50.85#ibcon#read 4, iclass 26, count 0 2006.258.01:35:50.85#ibcon#about to read 5, iclass 26, count 0 2006.258.01:35:50.85#ibcon#read 5, iclass 26, count 0 2006.258.01:35:50.85#ibcon#about to read 6, iclass 26, count 0 2006.258.01:35:50.85#ibcon#read 6, iclass 26, count 0 2006.258.01:35:50.85#ibcon#end of sib2, iclass 26, count 0 2006.258.01:35:50.85#ibcon#*mode == 0, iclass 26, count 0 2006.258.01:35:50.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.258.01:35:50.85#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.01:35:50.85#ibcon#*before write, iclass 26, count 0 2006.258.01:35:50.85#ibcon#enter sib2, iclass 26, count 0 2006.258.01:35:50.85#ibcon#flushed, iclass 26, count 0 2006.258.01:35:50.85#ibcon#about to write, iclass 26, count 0 2006.258.01:35:50.85#ibcon#wrote, iclass 26, count 0 2006.258.01:35:50.85#ibcon#about to read 3, iclass 26, count 0 2006.258.01:35:50.89#ibcon#read 3, iclass 26, count 0 2006.258.01:35:50.89#ibcon#about to read 4, iclass 26, count 0 2006.258.01:35:50.89#ibcon#read 4, iclass 26, count 0 2006.258.01:35:50.89#ibcon#about to read 5, iclass 26, count 0 2006.258.01:35:50.89#ibcon#read 5, iclass 26, count 0 2006.258.01:35:50.89#ibcon#about to read 6, iclass 26, count 0 2006.258.01:35:50.89#ibcon#read 6, iclass 26, count 0 2006.258.01:35:50.89#ibcon#end of sib2, iclass 26, count 0 2006.258.01:35:50.89#ibcon#*after write, iclass 26, count 0 2006.258.01:35:50.89#ibcon#*before return 0, iclass 26, count 0 2006.258.01:35:50.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:50.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.258.01:35:50.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.258.01:35:50.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.258.01:35:50.89$vck44/vb=3,4 2006.258.01:35:50.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.258.01:35:50.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.258.01:35:50.89#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:50.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:50.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:50.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:50.95#ibcon#enter wrdev, iclass 28, count 2 2006.258.01:35:50.95#ibcon#first serial, iclass 28, count 2 2006.258.01:35:50.95#ibcon#enter sib2, iclass 28, count 2 2006.258.01:35:50.95#ibcon#flushed, iclass 28, count 2 2006.258.01:35:50.95#ibcon#about to write, iclass 28, count 2 2006.258.01:35:50.95#ibcon#wrote, iclass 28, count 2 2006.258.01:35:50.95#ibcon#about to read 3, iclass 28, count 2 2006.258.01:35:50.97#ibcon#read 3, iclass 28, count 2 2006.258.01:35:50.97#ibcon#about to read 4, iclass 28, count 2 2006.258.01:35:50.97#ibcon#read 4, iclass 28, count 2 2006.258.01:35:50.97#ibcon#about to read 5, iclass 28, count 2 2006.258.01:35:50.97#ibcon#read 5, iclass 28, count 2 2006.258.01:35:50.97#ibcon#about to read 6, iclass 28, count 2 2006.258.01:35:50.97#ibcon#read 6, iclass 28, count 2 2006.258.01:35:50.97#ibcon#end of sib2, iclass 28, count 2 2006.258.01:35:50.97#ibcon#*mode == 0, iclass 28, count 2 2006.258.01:35:50.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.258.01:35:50.97#ibcon#[27=AT03-04\r\n] 2006.258.01:35:50.97#ibcon#*before write, iclass 28, count 2 2006.258.01:35:50.97#ibcon#enter sib2, iclass 28, count 2 2006.258.01:35:50.97#ibcon#flushed, iclass 28, count 2 2006.258.01:35:50.97#ibcon#about to write, iclass 28, count 2 2006.258.01:35:50.97#ibcon#wrote, iclass 28, count 2 2006.258.01:35:50.97#ibcon#about to read 3, iclass 28, count 2 2006.258.01:35:51.00#ibcon#read 3, iclass 28, count 2 2006.258.01:35:51.00#ibcon#about to read 4, iclass 28, count 2 2006.258.01:35:51.00#ibcon#read 4, iclass 28, count 2 2006.258.01:35:51.00#ibcon#about to read 5, iclass 28, count 2 2006.258.01:35:51.00#ibcon#read 5, iclass 28, count 2 2006.258.01:35:51.00#ibcon#about to read 6, iclass 28, count 2 2006.258.01:35:51.00#ibcon#read 6, iclass 28, count 2 2006.258.01:35:51.00#ibcon#end of sib2, iclass 28, count 2 2006.258.01:35:51.00#ibcon#*after write, iclass 28, count 2 2006.258.01:35:51.00#ibcon#*before return 0, iclass 28, count 2 2006.258.01:35:51.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:51.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.258.01:35:51.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.258.01:35:51.00#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:51.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:51.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:51.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:51.12#ibcon#enter wrdev, iclass 28, count 0 2006.258.01:35:51.12#ibcon#first serial, iclass 28, count 0 2006.258.01:35:51.12#ibcon#enter sib2, iclass 28, count 0 2006.258.01:35:51.12#ibcon#flushed, iclass 28, count 0 2006.258.01:35:51.12#ibcon#about to write, iclass 28, count 0 2006.258.01:35:51.12#ibcon#wrote, iclass 28, count 0 2006.258.01:35:51.12#ibcon#about to read 3, iclass 28, count 0 2006.258.01:35:51.14#ibcon#read 3, iclass 28, count 0 2006.258.01:35:51.14#ibcon#about to read 4, iclass 28, count 0 2006.258.01:35:51.14#ibcon#read 4, iclass 28, count 0 2006.258.01:35:51.14#ibcon#about to read 5, iclass 28, count 0 2006.258.01:35:51.14#ibcon#read 5, iclass 28, count 0 2006.258.01:35:51.14#ibcon#about to read 6, iclass 28, count 0 2006.258.01:35:51.14#ibcon#read 6, iclass 28, count 0 2006.258.01:35:51.14#ibcon#end of sib2, iclass 28, count 0 2006.258.01:35:51.14#ibcon#*mode == 0, iclass 28, count 0 2006.258.01:35:51.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.258.01:35:51.14#ibcon#[27=USB\r\n] 2006.258.01:35:51.14#ibcon#*before write, iclass 28, count 0 2006.258.01:35:51.14#ibcon#enter sib2, iclass 28, count 0 2006.258.01:35:51.14#ibcon#flushed, iclass 28, count 0 2006.258.01:35:51.14#ibcon#about to write, iclass 28, count 0 2006.258.01:35:51.14#ibcon#wrote, iclass 28, count 0 2006.258.01:35:51.14#ibcon#about to read 3, iclass 28, count 0 2006.258.01:35:51.17#ibcon#read 3, iclass 28, count 0 2006.258.01:35:51.17#ibcon#about to read 4, iclass 28, count 0 2006.258.01:35:51.17#ibcon#read 4, iclass 28, count 0 2006.258.01:35:51.17#ibcon#about to read 5, iclass 28, count 0 2006.258.01:35:51.17#ibcon#read 5, iclass 28, count 0 2006.258.01:35:51.17#ibcon#about to read 6, iclass 28, count 0 2006.258.01:35:51.17#ibcon#read 6, iclass 28, count 0 2006.258.01:35:51.17#ibcon#end of sib2, iclass 28, count 0 2006.258.01:35:51.17#ibcon#*after write, iclass 28, count 0 2006.258.01:35:51.17#ibcon#*before return 0, iclass 28, count 0 2006.258.01:35:51.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:51.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.258.01:35:51.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.258.01:35:51.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.258.01:35:51.17$vck44/vblo=4,679.99 2006.258.01:35:51.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.258.01:35:51.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.258.01:35:51.17#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:51.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:51.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:51.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:51.17#ibcon#enter wrdev, iclass 30, count 0 2006.258.01:35:51.17#ibcon#first serial, iclass 30, count 0 2006.258.01:35:51.17#ibcon#enter sib2, iclass 30, count 0 2006.258.01:35:51.17#ibcon#flushed, iclass 30, count 0 2006.258.01:35:51.17#ibcon#about to write, iclass 30, count 0 2006.258.01:35:51.17#ibcon#wrote, iclass 30, count 0 2006.258.01:35:51.17#ibcon#about to read 3, iclass 30, count 0 2006.258.01:35:51.19#ibcon#read 3, iclass 30, count 0 2006.258.01:35:51.19#ibcon#about to read 4, iclass 30, count 0 2006.258.01:35:51.19#ibcon#read 4, iclass 30, count 0 2006.258.01:35:51.19#ibcon#about to read 5, iclass 30, count 0 2006.258.01:35:51.19#ibcon#read 5, iclass 30, count 0 2006.258.01:35:51.19#ibcon#about to read 6, iclass 30, count 0 2006.258.01:35:51.19#ibcon#read 6, iclass 30, count 0 2006.258.01:35:51.19#ibcon#end of sib2, iclass 30, count 0 2006.258.01:35:51.19#ibcon#*mode == 0, iclass 30, count 0 2006.258.01:35:51.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.258.01:35:51.19#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.01:35:51.19#ibcon#*before write, iclass 30, count 0 2006.258.01:35:51.19#ibcon#enter sib2, iclass 30, count 0 2006.258.01:35:51.19#ibcon#flushed, iclass 30, count 0 2006.258.01:35:51.19#ibcon#about to write, iclass 30, count 0 2006.258.01:35:51.19#ibcon#wrote, iclass 30, count 0 2006.258.01:35:51.19#ibcon#about to read 3, iclass 30, count 0 2006.258.01:35:51.23#ibcon#read 3, iclass 30, count 0 2006.258.01:35:51.23#ibcon#about to read 4, iclass 30, count 0 2006.258.01:35:51.23#ibcon#read 4, iclass 30, count 0 2006.258.01:35:51.23#ibcon#about to read 5, iclass 30, count 0 2006.258.01:35:51.23#ibcon#read 5, iclass 30, count 0 2006.258.01:35:51.23#ibcon#about to read 6, iclass 30, count 0 2006.258.01:35:51.23#ibcon#read 6, iclass 30, count 0 2006.258.01:35:51.23#ibcon#end of sib2, iclass 30, count 0 2006.258.01:35:51.23#ibcon#*after write, iclass 30, count 0 2006.258.01:35:51.23#ibcon#*before return 0, iclass 30, count 0 2006.258.01:35:51.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:51.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.258.01:35:51.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.258.01:35:51.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.258.01:35:51.23$vck44/vb=4,5 2006.258.01:35:51.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.258.01:35:51.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.258.01:35:51.23#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:51.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:35:51.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:35:51.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:35:51.29#ibcon#enter wrdev, iclass 32, count 2 2006.258.01:35:51.29#ibcon#first serial, iclass 32, count 2 2006.258.01:35:51.29#ibcon#enter sib2, iclass 32, count 2 2006.258.01:35:51.29#ibcon#flushed, iclass 32, count 2 2006.258.01:35:51.29#ibcon#about to write, iclass 32, count 2 2006.258.01:35:51.29#ibcon#wrote, iclass 32, count 2 2006.258.01:35:51.29#ibcon#about to read 3, iclass 32, count 2 2006.258.01:35:51.31#ibcon#read 3, iclass 32, count 2 2006.258.01:35:51.31#ibcon#about to read 4, iclass 32, count 2 2006.258.01:35:51.31#ibcon#read 4, iclass 32, count 2 2006.258.01:35:51.31#ibcon#about to read 5, iclass 32, count 2 2006.258.01:35:51.31#ibcon#read 5, iclass 32, count 2 2006.258.01:35:51.31#ibcon#about to read 6, iclass 32, count 2 2006.258.01:35:51.31#ibcon#read 6, iclass 32, count 2 2006.258.01:35:51.31#ibcon#end of sib2, iclass 32, count 2 2006.258.01:35:51.31#ibcon#*mode == 0, iclass 32, count 2 2006.258.01:35:51.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.258.01:35:51.31#ibcon#[27=AT04-05\r\n] 2006.258.01:35:51.31#ibcon#*before write, iclass 32, count 2 2006.258.01:35:51.31#ibcon#enter sib2, iclass 32, count 2 2006.258.01:35:51.31#ibcon#flushed, iclass 32, count 2 2006.258.01:35:51.31#ibcon#about to write, iclass 32, count 2 2006.258.01:35:51.31#ibcon#wrote, iclass 32, count 2 2006.258.01:35:51.31#ibcon#about to read 3, iclass 32, count 2 2006.258.01:35:51.34#ibcon#read 3, iclass 32, count 2 2006.258.01:35:51.34#ibcon#about to read 4, iclass 32, count 2 2006.258.01:35:51.34#ibcon#read 4, iclass 32, count 2 2006.258.01:35:51.34#ibcon#about to read 5, iclass 32, count 2 2006.258.01:35:51.34#ibcon#read 5, iclass 32, count 2 2006.258.01:35:51.34#ibcon#about to read 6, iclass 32, count 2 2006.258.01:35:51.34#ibcon#read 6, iclass 32, count 2 2006.258.01:35:51.34#ibcon#end of sib2, iclass 32, count 2 2006.258.01:35:51.34#ibcon#*after write, iclass 32, count 2 2006.258.01:35:51.34#ibcon#*before return 0, iclass 32, count 2 2006.258.01:35:51.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:35:51.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.258.01:35:51.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.258.01:35:51.34#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:51.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:35:51.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:35:51.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:35:51.46#ibcon#enter wrdev, iclass 32, count 0 2006.258.01:35:51.46#ibcon#first serial, iclass 32, count 0 2006.258.01:35:51.46#ibcon#enter sib2, iclass 32, count 0 2006.258.01:35:51.46#ibcon#flushed, iclass 32, count 0 2006.258.01:35:51.46#ibcon#about to write, iclass 32, count 0 2006.258.01:35:51.46#ibcon#wrote, iclass 32, count 0 2006.258.01:35:51.46#ibcon#about to read 3, iclass 32, count 0 2006.258.01:35:51.48#ibcon#read 3, iclass 32, count 0 2006.258.01:35:51.48#ibcon#about to read 4, iclass 32, count 0 2006.258.01:35:51.48#ibcon#read 4, iclass 32, count 0 2006.258.01:35:51.48#ibcon#about to read 5, iclass 32, count 0 2006.258.01:35:51.48#ibcon#read 5, iclass 32, count 0 2006.258.01:35:51.48#ibcon#about to read 6, iclass 32, count 0 2006.258.01:35:51.48#ibcon#read 6, iclass 32, count 0 2006.258.01:35:51.48#ibcon#end of sib2, iclass 32, count 0 2006.258.01:35:51.48#ibcon#*mode == 0, iclass 32, count 0 2006.258.01:35:51.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.258.01:35:51.48#ibcon#[27=USB\r\n] 2006.258.01:35:51.48#ibcon#*before write, iclass 32, count 0 2006.258.01:35:51.48#ibcon#enter sib2, iclass 32, count 0 2006.258.01:35:51.48#ibcon#flushed, iclass 32, count 0 2006.258.01:35:51.48#ibcon#about to write, iclass 32, count 0 2006.258.01:35:51.48#ibcon#wrote, iclass 32, count 0 2006.258.01:35:51.48#ibcon#about to read 3, iclass 32, count 0 2006.258.01:35:51.51#ibcon#read 3, iclass 32, count 0 2006.258.01:35:51.51#ibcon#about to read 4, iclass 32, count 0 2006.258.01:35:51.51#ibcon#read 4, iclass 32, count 0 2006.258.01:35:51.51#ibcon#about to read 5, iclass 32, count 0 2006.258.01:35:51.51#ibcon#read 5, iclass 32, count 0 2006.258.01:35:51.51#ibcon#about to read 6, iclass 32, count 0 2006.258.01:35:51.51#ibcon#read 6, iclass 32, count 0 2006.258.01:35:51.51#ibcon#end of sib2, iclass 32, count 0 2006.258.01:35:51.51#ibcon#*after write, iclass 32, count 0 2006.258.01:35:51.51#ibcon#*before return 0, iclass 32, count 0 2006.258.01:35:51.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:35:51.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.258.01:35:51.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.258.01:35:51.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.258.01:35:51.51$vck44/vblo=5,709.99 2006.258.01:35:51.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.258.01:35:51.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.258.01:35:51.51#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:51.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:35:51.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:35:51.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:35:51.51#ibcon#enter wrdev, iclass 34, count 0 2006.258.01:35:51.51#ibcon#first serial, iclass 34, count 0 2006.258.01:35:51.51#ibcon#enter sib2, iclass 34, count 0 2006.258.01:35:51.51#ibcon#flushed, iclass 34, count 0 2006.258.01:35:51.51#ibcon#about to write, iclass 34, count 0 2006.258.01:35:51.51#ibcon#wrote, iclass 34, count 0 2006.258.01:35:51.51#ibcon#about to read 3, iclass 34, count 0 2006.258.01:35:51.53#ibcon#read 3, iclass 34, count 0 2006.258.01:35:51.53#ibcon#about to read 4, iclass 34, count 0 2006.258.01:35:51.53#ibcon#read 4, iclass 34, count 0 2006.258.01:35:51.53#ibcon#about to read 5, iclass 34, count 0 2006.258.01:35:51.53#ibcon#read 5, iclass 34, count 0 2006.258.01:35:51.53#ibcon#about to read 6, iclass 34, count 0 2006.258.01:35:51.53#ibcon#read 6, iclass 34, count 0 2006.258.01:35:51.53#ibcon#end of sib2, iclass 34, count 0 2006.258.01:35:51.53#ibcon#*mode == 0, iclass 34, count 0 2006.258.01:35:51.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.258.01:35:51.53#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.01:35:51.53#ibcon#*before write, iclass 34, count 0 2006.258.01:35:51.53#ibcon#enter sib2, iclass 34, count 0 2006.258.01:35:51.53#ibcon#flushed, iclass 34, count 0 2006.258.01:35:51.53#ibcon#about to write, iclass 34, count 0 2006.258.01:35:51.53#ibcon#wrote, iclass 34, count 0 2006.258.01:35:51.53#ibcon#about to read 3, iclass 34, count 0 2006.258.01:35:51.57#ibcon#read 3, iclass 34, count 0 2006.258.01:35:51.57#ibcon#about to read 4, iclass 34, count 0 2006.258.01:35:51.57#ibcon#read 4, iclass 34, count 0 2006.258.01:35:51.57#ibcon#about to read 5, iclass 34, count 0 2006.258.01:35:51.57#ibcon#read 5, iclass 34, count 0 2006.258.01:35:51.57#ibcon#about to read 6, iclass 34, count 0 2006.258.01:35:51.57#ibcon#read 6, iclass 34, count 0 2006.258.01:35:51.57#ibcon#end of sib2, iclass 34, count 0 2006.258.01:35:51.57#ibcon#*after write, iclass 34, count 0 2006.258.01:35:51.57#ibcon#*before return 0, iclass 34, count 0 2006.258.01:35:51.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:35:51.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.258.01:35:51.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.258.01:35:51.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.258.01:35:51.57$vck44/vb=5,4 2006.258.01:35:51.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.258.01:35:51.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.258.01:35:51.57#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:51.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:35:51.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:35:51.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:35:51.63#ibcon#enter wrdev, iclass 36, count 2 2006.258.01:35:51.63#ibcon#first serial, iclass 36, count 2 2006.258.01:35:51.63#ibcon#enter sib2, iclass 36, count 2 2006.258.01:35:51.63#ibcon#flushed, iclass 36, count 2 2006.258.01:35:51.63#ibcon#about to write, iclass 36, count 2 2006.258.01:35:51.63#ibcon#wrote, iclass 36, count 2 2006.258.01:35:51.63#ibcon#about to read 3, iclass 36, count 2 2006.258.01:35:51.65#ibcon#read 3, iclass 36, count 2 2006.258.01:35:51.65#ibcon#about to read 4, iclass 36, count 2 2006.258.01:35:51.65#ibcon#read 4, iclass 36, count 2 2006.258.01:35:51.65#ibcon#about to read 5, iclass 36, count 2 2006.258.01:35:51.65#ibcon#read 5, iclass 36, count 2 2006.258.01:35:51.65#ibcon#about to read 6, iclass 36, count 2 2006.258.01:35:51.65#ibcon#read 6, iclass 36, count 2 2006.258.01:35:51.65#ibcon#end of sib2, iclass 36, count 2 2006.258.01:35:51.65#ibcon#*mode == 0, iclass 36, count 2 2006.258.01:35:51.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.258.01:35:51.65#ibcon#[27=AT05-04\r\n] 2006.258.01:35:51.65#ibcon#*before write, iclass 36, count 2 2006.258.01:35:51.65#ibcon#enter sib2, iclass 36, count 2 2006.258.01:35:51.65#ibcon#flushed, iclass 36, count 2 2006.258.01:35:51.65#ibcon#about to write, iclass 36, count 2 2006.258.01:35:51.65#ibcon#wrote, iclass 36, count 2 2006.258.01:35:51.65#ibcon#about to read 3, iclass 36, count 2 2006.258.01:35:51.68#ibcon#read 3, iclass 36, count 2 2006.258.01:35:51.68#ibcon#about to read 4, iclass 36, count 2 2006.258.01:35:51.68#ibcon#read 4, iclass 36, count 2 2006.258.01:35:51.68#ibcon#about to read 5, iclass 36, count 2 2006.258.01:35:51.68#ibcon#read 5, iclass 36, count 2 2006.258.01:35:51.68#ibcon#about to read 6, iclass 36, count 2 2006.258.01:35:51.68#ibcon#read 6, iclass 36, count 2 2006.258.01:35:51.68#ibcon#end of sib2, iclass 36, count 2 2006.258.01:35:51.68#ibcon#*after write, iclass 36, count 2 2006.258.01:35:51.68#ibcon#*before return 0, iclass 36, count 2 2006.258.01:35:51.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:35:51.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.258.01:35:51.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.258.01:35:51.68#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:51.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:35:51.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:35:51.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:35:51.80#ibcon#enter wrdev, iclass 36, count 0 2006.258.01:35:51.80#ibcon#first serial, iclass 36, count 0 2006.258.01:35:51.80#ibcon#enter sib2, iclass 36, count 0 2006.258.01:35:51.80#ibcon#flushed, iclass 36, count 0 2006.258.01:35:51.80#ibcon#about to write, iclass 36, count 0 2006.258.01:35:51.80#ibcon#wrote, iclass 36, count 0 2006.258.01:35:51.80#ibcon#about to read 3, iclass 36, count 0 2006.258.01:35:51.82#ibcon#read 3, iclass 36, count 0 2006.258.01:35:51.82#ibcon#about to read 4, iclass 36, count 0 2006.258.01:35:51.82#ibcon#read 4, iclass 36, count 0 2006.258.01:35:51.82#ibcon#about to read 5, iclass 36, count 0 2006.258.01:35:51.82#ibcon#read 5, iclass 36, count 0 2006.258.01:35:51.82#ibcon#about to read 6, iclass 36, count 0 2006.258.01:35:51.82#ibcon#read 6, iclass 36, count 0 2006.258.01:35:51.82#ibcon#end of sib2, iclass 36, count 0 2006.258.01:35:51.82#ibcon#*mode == 0, iclass 36, count 0 2006.258.01:35:51.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.258.01:35:51.82#ibcon#[27=USB\r\n] 2006.258.01:35:51.82#ibcon#*before write, iclass 36, count 0 2006.258.01:35:51.82#ibcon#enter sib2, iclass 36, count 0 2006.258.01:35:51.82#ibcon#flushed, iclass 36, count 0 2006.258.01:35:51.82#ibcon#about to write, iclass 36, count 0 2006.258.01:35:51.82#ibcon#wrote, iclass 36, count 0 2006.258.01:35:51.82#ibcon#about to read 3, iclass 36, count 0 2006.258.01:35:51.85#ibcon#read 3, iclass 36, count 0 2006.258.01:35:51.85#ibcon#about to read 4, iclass 36, count 0 2006.258.01:35:51.85#ibcon#read 4, iclass 36, count 0 2006.258.01:35:51.85#ibcon#about to read 5, iclass 36, count 0 2006.258.01:35:51.85#ibcon#read 5, iclass 36, count 0 2006.258.01:35:51.85#ibcon#about to read 6, iclass 36, count 0 2006.258.01:35:51.85#ibcon#read 6, iclass 36, count 0 2006.258.01:35:51.85#ibcon#end of sib2, iclass 36, count 0 2006.258.01:35:51.85#ibcon#*after write, iclass 36, count 0 2006.258.01:35:51.85#ibcon#*before return 0, iclass 36, count 0 2006.258.01:35:51.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:35:51.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.258.01:35:51.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.258.01:35:51.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.258.01:35:51.85$vck44/vblo=6,719.99 2006.258.01:35:51.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.258.01:35:51.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.258.01:35:51.85#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:51.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:51.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:51.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:51.85#ibcon#enter wrdev, iclass 38, count 0 2006.258.01:35:51.85#ibcon#first serial, iclass 38, count 0 2006.258.01:35:51.85#ibcon#enter sib2, iclass 38, count 0 2006.258.01:35:51.85#ibcon#flushed, iclass 38, count 0 2006.258.01:35:51.85#ibcon#about to write, iclass 38, count 0 2006.258.01:35:51.85#ibcon#wrote, iclass 38, count 0 2006.258.01:35:51.85#ibcon#about to read 3, iclass 38, count 0 2006.258.01:35:51.87#ibcon#read 3, iclass 38, count 0 2006.258.01:35:51.87#ibcon#about to read 4, iclass 38, count 0 2006.258.01:35:51.87#ibcon#read 4, iclass 38, count 0 2006.258.01:35:51.87#ibcon#about to read 5, iclass 38, count 0 2006.258.01:35:51.87#ibcon#read 5, iclass 38, count 0 2006.258.01:35:51.87#ibcon#about to read 6, iclass 38, count 0 2006.258.01:35:51.87#ibcon#read 6, iclass 38, count 0 2006.258.01:35:51.87#ibcon#end of sib2, iclass 38, count 0 2006.258.01:35:51.87#ibcon#*mode == 0, iclass 38, count 0 2006.258.01:35:51.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.258.01:35:51.87#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.01:35:51.87#ibcon#*before write, iclass 38, count 0 2006.258.01:35:51.87#ibcon#enter sib2, iclass 38, count 0 2006.258.01:35:51.87#ibcon#flushed, iclass 38, count 0 2006.258.01:35:51.87#ibcon#about to write, iclass 38, count 0 2006.258.01:35:51.87#ibcon#wrote, iclass 38, count 0 2006.258.01:35:51.87#ibcon#about to read 3, iclass 38, count 0 2006.258.01:35:51.91#ibcon#read 3, iclass 38, count 0 2006.258.01:35:51.91#ibcon#about to read 4, iclass 38, count 0 2006.258.01:35:51.91#ibcon#read 4, iclass 38, count 0 2006.258.01:35:51.91#ibcon#about to read 5, iclass 38, count 0 2006.258.01:35:51.91#ibcon#read 5, iclass 38, count 0 2006.258.01:35:51.91#ibcon#about to read 6, iclass 38, count 0 2006.258.01:35:51.91#ibcon#read 6, iclass 38, count 0 2006.258.01:35:51.91#ibcon#end of sib2, iclass 38, count 0 2006.258.01:35:51.91#ibcon#*after write, iclass 38, count 0 2006.258.01:35:51.91#ibcon#*before return 0, iclass 38, count 0 2006.258.01:35:51.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:51.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.258.01:35:51.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.258.01:35:51.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.258.01:35:51.91$vck44/vb=6,4 2006.258.01:35:51.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.258.01:35:51.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.258.01:35:51.91#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:51.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:51.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:51.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:51.97#ibcon#enter wrdev, iclass 40, count 2 2006.258.01:35:51.97#ibcon#first serial, iclass 40, count 2 2006.258.01:35:51.97#ibcon#enter sib2, iclass 40, count 2 2006.258.01:35:51.97#ibcon#flushed, iclass 40, count 2 2006.258.01:35:51.97#ibcon#about to write, iclass 40, count 2 2006.258.01:35:51.97#ibcon#wrote, iclass 40, count 2 2006.258.01:35:51.97#ibcon#about to read 3, iclass 40, count 2 2006.258.01:35:51.99#ibcon#read 3, iclass 40, count 2 2006.258.01:35:51.99#ibcon#about to read 4, iclass 40, count 2 2006.258.01:35:51.99#ibcon#read 4, iclass 40, count 2 2006.258.01:35:51.99#ibcon#about to read 5, iclass 40, count 2 2006.258.01:35:51.99#ibcon#read 5, iclass 40, count 2 2006.258.01:35:51.99#ibcon#about to read 6, iclass 40, count 2 2006.258.01:35:51.99#ibcon#read 6, iclass 40, count 2 2006.258.01:35:51.99#ibcon#end of sib2, iclass 40, count 2 2006.258.01:35:51.99#ibcon#*mode == 0, iclass 40, count 2 2006.258.01:35:51.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.258.01:35:51.99#ibcon#[27=AT06-04\r\n] 2006.258.01:35:51.99#ibcon#*before write, iclass 40, count 2 2006.258.01:35:51.99#ibcon#enter sib2, iclass 40, count 2 2006.258.01:35:51.99#ibcon#flushed, iclass 40, count 2 2006.258.01:35:51.99#ibcon#about to write, iclass 40, count 2 2006.258.01:35:51.99#ibcon#wrote, iclass 40, count 2 2006.258.01:35:51.99#ibcon#about to read 3, iclass 40, count 2 2006.258.01:35:52.02#ibcon#read 3, iclass 40, count 2 2006.258.01:35:52.02#ibcon#about to read 4, iclass 40, count 2 2006.258.01:35:52.02#ibcon#read 4, iclass 40, count 2 2006.258.01:35:52.02#ibcon#about to read 5, iclass 40, count 2 2006.258.01:35:52.02#ibcon#read 5, iclass 40, count 2 2006.258.01:35:52.02#ibcon#about to read 6, iclass 40, count 2 2006.258.01:35:52.02#ibcon#read 6, iclass 40, count 2 2006.258.01:35:52.02#ibcon#end of sib2, iclass 40, count 2 2006.258.01:35:52.02#ibcon#*after write, iclass 40, count 2 2006.258.01:35:52.02#ibcon#*before return 0, iclass 40, count 2 2006.258.01:35:52.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:52.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.258.01:35:52.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.258.01:35:52.02#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:52.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:52.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:52.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:52.14#ibcon#enter wrdev, iclass 40, count 0 2006.258.01:35:52.14#ibcon#first serial, iclass 40, count 0 2006.258.01:35:52.14#ibcon#enter sib2, iclass 40, count 0 2006.258.01:35:52.14#ibcon#flushed, iclass 40, count 0 2006.258.01:35:52.14#ibcon#about to write, iclass 40, count 0 2006.258.01:35:52.14#ibcon#wrote, iclass 40, count 0 2006.258.01:35:52.14#ibcon#about to read 3, iclass 40, count 0 2006.258.01:35:52.16#ibcon#read 3, iclass 40, count 0 2006.258.01:35:52.16#ibcon#about to read 4, iclass 40, count 0 2006.258.01:35:52.16#ibcon#read 4, iclass 40, count 0 2006.258.01:35:52.16#ibcon#about to read 5, iclass 40, count 0 2006.258.01:35:52.16#ibcon#read 5, iclass 40, count 0 2006.258.01:35:52.16#ibcon#about to read 6, iclass 40, count 0 2006.258.01:35:52.16#ibcon#read 6, iclass 40, count 0 2006.258.01:35:52.16#ibcon#end of sib2, iclass 40, count 0 2006.258.01:35:52.16#ibcon#*mode == 0, iclass 40, count 0 2006.258.01:35:52.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.258.01:35:52.16#ibcon#[27=USB\r\n] 2006.258.01:35:52.16#ibcon#*before write, iclass 40, count 0 2006.258.01:35:52.16#ibcon#enter sib2, iclass 40, count 0 2006.258.01:35:52.16#ibcon#flushed, iclass 40, count 0 2006.258.01:35:52.16#ibcon#about to write, iclass 40, count 0 2006.258.01:35:52.16#ibcon#wrote, iclass 40, count 0 2006.258.01:35:52.16#ibcon#about to read 3, iclass 40, count 0 2006.258.01:35:52.19#ibcon#read 3, iclass 40, count 0 2006.258.01:35:52.19#ibcon#about to read 4, iclass 40, count 0 2006.258.01:35:52.19#ibcon#read 4, iclass 40, count 0 2006.258.01:35:52.19#ibcon#about to read 5, iclass 40, count 0 2006.258.01:35:52.19#ibcon#read 5, iclass 40, count 0 2006.258.01:35:52.19#ibcon#about to read 6, iclass 40, count 0 2006.258.01:35:52.19#ibcon#read 6, iclass 40, count 0 2006.258.01:35:52.19#ibcon#end of sib2, iclass 40, count 0 2006.258.01:35:52.19#ibcon#*after write, iclass 40, count 0 2006.258.01:35:52.19#ibcon#*before return 0, iclass 40, count 0 2006.258.01:35:52.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:52.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.258.01:35:52.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.258.01:35:52.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.258.01:35:52.19$vck44/vblo=7,734.99 2006.258.01:35:52.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.258.01:35:52.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.258.01:35:52.19#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:52.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:52.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:52.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:52.19#ibcon#enter wrdev, iclass 4, count 0 2006.258.01:35:52.19#ibcon#first serial, iclass 4, count 0 2006.258.01:35:52.19#ibcon#enter sib2, iclass 4, count 0 2006.258.01:35:52.19#ibcon#flushed, iclass 4, count 0 2006.258.01:35:52.19#ibcon#about to write, iclass 4, count 0 2006.258.01:35:52.19#ibcon#wrote, iclass 4, count 0 2006.258.01:35:52.19#ibcon#about to read 3, iclass 4, count 0 2006.258.01:35:52.21#ibcon#read 3, iclass 4, count 0 2006.258.01:35:52.21#ibcon#about to read 4, iclass 4, count 0 2006.258.01:35:52.21#ibcon#read 4, iclass 4, count 0 2006.258.01:35:52.21#ibcon#about to read 5, iclass 4, count 0 2006.258.01:35:52.21#ibcon#read 5, iclass 4, count 0 2006.258.01:35:52.21#ibcon#about to read 6, iclass 4, count 0 2006.258.01:35:52.21#ibcon#read 6, iclass 4, count 0 2006.258.01:35:52.21#ibcon#end of sib2, iclass 4, count 0 2006.258.01:35:52.21#ibcon#*mode == 0, iclass 4, count 0 2006.258.01:35:52.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.258.01:35:52.21#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.01:35:52.21#ibcon#*before write, iclass 4, count 0 2006.258.01:35:52.21#ibcon#enter sib2, iclass 4, count 0 2006.258.01:35:52.21#ibcon#flushed, iclass 4, count 0 2006.258.01:35:52.21#ibcon#about to write, iclass 4, count 0 2006.258.01:35:52.21#ibcon#wrote, iclass 4, count 0 2006.258.01:35:52.21#ibcon#about to read 3, iclass 4, count 0 2006.258.01:35:52.25#ibcon#read 3, iclass 4, count 0 2006.258.01:35:52.25#ibcon#about to read 4, iclass 4, count 0 2006.258.01:35:52.25#ibcon#read 4, iclass 4, count 0 2006.258.01:35:52.25#ibcon#about to read 5, iclass 4, count 0 2006.258.01:35:52.25#ibcon#read 5, iclass 4, count 0 2006.258.01:35:52.25#ibcon#about to read 6, iclass 4, count 0 2006.258.01:35:52.25#ibcon#read 6, iclass 4, count 0 2006.258.01:35:52.25#ibcon#end of sib2, iclass 4, count 0 2006.258.01:35:52.25#ibcon#*after write, iclass 4, count 0 2006.258.01:35:52.25#ibcon#*before return 0, iclass 4, count 0 2006.258.01:35:52.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:52.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.258.01:35:52.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.258.01:35:52.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.258.01:35:52.25$vck44/vb=7,4 2006.258.01:35:52.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.258.01:35:52.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.258.01:35:52.25#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:52.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:52.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:52.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:52.31#ibcon#enter wrdev, iclass 6, count 2 2006.258.01:35:52.31#ibcon#first serial, iclass 6, count 2 2006.258.01:35:52.31#ibcon#enter sib2, iclass 6, count 2 2006.258.01:35:52.31#ibcon#flushed, iclass 6, count 2 2006.258.01:35:52.31#ibcon#about to write, iclass 6, count 2 2006.258.01:35:52.31#ibcon#wrote, iclass 6, count 2 2006.258.01:35:52.31#ibcon#about to read 3, iclass 6, count 2 2006.258.01:35:52.33#ibcon#read 3, iclass 6, count 2 2006.258.01:35:52.33#ibcon#about to read 4, iclass 6, count 2 2006.258.01:35:52.33#ibcon#read 4, iclass 6, count 2 2006.258.01:35:52.33#ibcon#about to read 5, iclass 6, count 2 2006.258.01:35:52.33#ibcon#read 5, iclass 6, count 2 2006.258.01:35:52.33#ibcon#about to read 6, iclass 6, count 2 2006.258.01:35:52.33#ibcon#read 6, iclass 6, count 2 2006.258.01:35:52.33#ibcon#end of sib2, iclass 6, count 2 2006.258.01:35:52.33#ibcon#*mode == 0, iclass 6, count 2 2006.258.01:35:52.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.258.01:35:52.33#ibcon#[27=AT07-04\r\n] 2006.258.01:35:52.33#ibcon#*before write, iclass 6, count 2 2006.258.01:35:52.33#ibcon#enter sib2, iclass 6, count 2 2006.258.01:35:52.33#ibcon#flushed, iclass 6, count 2 2006.258.01:35:52.33#ibcon#about to write, iclass 6, count 2 2006.258.01:35:52.33#ibcon#wrote, iclass 6, count 2 2006.258.01:35:52.33#ibcon#about to read 3, iclass 6, count 2 2006.258.01:35:52.36#ibcon#read 3, iclass 6, count 2 2006.258.01:35:52.36#ibcon#about to read 4, iclass 6, count 2 2006.258.01:35:52.36#ibcon#read 4, iclass 6, count 2 2006.258.01:35:52.36#ibcon#about to read 5, iclass 6, count 2 2006.258.01:35:52.36#ibcon#read 5, iclass 6, count 2 2006.258.01:35:52.36#ibcon#about to read 6, iclass 6, count 2 2006.258.01:35:52.36#ibcon#read 6, iclass 6, count 2 2006.258.01:35:52.36#ibcon#end of sib2, iclass 6, count 2 2006.258.01:35:52.36#ibcon#*after write, iclass 6, count 2 2006.258.01:35:52.36#ibcon#*before return 0, iclass 6, count 2 2006.258.01:35:52.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:52.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.258.01:35:52.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.258.01:35:52.36#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:52.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:52.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:52.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:52.48#ibcon#enter wrdev, iclass 6, count 0 2006.258.01:35:52.48#ibcon#first serial, iclass 6, count 0 2006.258.01:35:52.48#ibcon#enter sib2, iclass 6, count 0 2006.258.01:35:52.48#ibcon#flushed, iclass 6, count 0 2006.258.01:35:52.48#ibcon#about to write, iclass 6, count 0 2006.258.01:35:52.48#ibcon#wrote, iclass 6, count 0 2006.258.01:35:52.48#ibcon#about to read 3, iclass 6, count 0 2006.258.01:35:52.50#ibcon#read 3, iclass 6, count 0 2006.258.01:35:52.50#ibcon#about to read 4, iclass 6, count 0 2006.258.01:35:52.50#ibcon#read 4, iclass 6, count 0 2006.258.01:35:52.50#ibcon#about to read 5, iclass 6, count 0 2006.258.01:35:52.50#ibcon#read 5, iclass 6, count 0 2006.258.01:35:52.50#ibcon#about to read 6, iclass 6, count 0 2006.258.01:35:52.50#ibcon#read 6, iclass 6, count 0 2006.258.01:35:52.50#ibcon#end of sib2, iclass 6, count 0 2006.258.01:35:52.50#ibcon#*mode == 0, iclass 6, count 0 2006.258.01:35:52.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.258.01:35:52.50#ibcon#[27=USB\r\n] 2006.258.01:35:52.50#ibcon#*before write, iclass 6, count 0 2006.258.01:35:52.50#ibcon#enter sib2, iclass 6, count 0 2006.258.01:35:52.50#ibcon#flushed, iclass 6, count 0 2006.258.01:35:52.50#ibcon#about to write, iclass 6, count 0 2006.258.01:35:52.50#ibcon#wrote, iclass 6, count 0 2006.258.01:35:52.50#ibcon#about to read 3, iclass 6, count 0 2006.258.01:35:52.53#ibcon#read 3, iclass 6, count 0 2006.258.01:35:52.53#ibcon#about to read 4, iclass 6, count 0 2006.258.01:35:52.53#ibcon#read 4, iclass 6, count 0 2006.258.01:35:52.53#ibcon#about to read 5, iclass 6, count 0 2006.258.01:35:52.53#ibcon#read 5, iclass 6, count 0 2006.258.01:35:52.53#ibcon#about to read 6, iclass 6, count 0 2006.258.01:35:52.53#ibcon#read 6, iclass 6, count 0 2006.258.01:35:52.53#ibcon#end of sib2, iclass 6, count 0 2006.258.01:35:52.53#ibcon#*after write, iclass 6, count 0 2006.258.01:35:52.53#ibcon#*before return 0, iclass 6, count 0 2006.258.01:35:52.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:52.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.258.01:35:52.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.258.01:35:52.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.258.01:35:52.53$vck44/vblo=8,744.99 2006.258.01:35:52.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.258.01:35:52.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.258.01:35:52.53#ibcon#ireg 17 cls_cnt 0 2006.258.01:35:52.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:52.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:52.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:52.53#ibcon#enter wrdev, iclass 10, count 0 2006.258.01:35:52.53#ibcon#first serial, iclass 10, count 0 2006.258.01:35:52.53#ibcon#enter sib2, iclass 10, count 0 2006.258.01:35:52.53#ibcon#flushed, iclass 10, count 0 2006.258.01:35:52.53#ibcon#about to write, iclass 10, count 0 2006.258.01:35:52.53#ibcon#wrote, iclass 10, count 0 2006.258.01:35:52.53#ibcon#about to read 3, iclass 10, count 0 2006.258.01:35:52.55#ibcon#read 3, iclass 10, count 0 2006.258.01:35:52.55#ibcon#about to read 4, iclass 10, count 0 2006.258.01:35:52.55#ibcon#read 4, iclass 10, count 0 2006.258.01:35:52.55#ibcon#about to read 5, iclass 10, count 0 2006.258.01:35:52.55#ibcon#read 5, iclass 10, count 0 2006.258.01:35:52.55#ibcon#about to read 6, iclass 10, count 0 2006.258.01:35:52.55#ibcon#read 6, iclass 10, count 0 2006.258.01:35:52.55#ibcon#end of sib2, iclass 10, count 0 2006.258.01:35:52.55#ibcon#*mode == 0, iclass 10, count 0 2006.258.01:35:52.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.258.01:35:52.55#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.01:35:52.55#ibcon#*before write, iclass 10, count 0 2006.258.01:35:52.55#ibcon#enter sib2, iclass 10, count 0 2006.258.01:35:52.55#ibcon#flushed, iclass 10, count 0 2006.258.01:35:52.55#ibcon#about to write, iclass 10, count 0 2006.258.01:35:52.55#ibcon#wrote, iclass 10, count 0 2006.258.01:35:52.55#ibcon#about to read 3, iclass 10, count 0 2006.258.01:35:52.59#ibcon#read 3, iclass 10, count 0 2006.258.01:35:52.59#ibcon#about to read 4, iclass 10, count 0 2006.258.01:35:52.59#ibcon#read 4, iclass 10, count 0 2006.258.01:35:52.59#ibcon#about to read 5, iclass 10, count 0 2006.258.01:35:52.59#ibcon#read 5, iclass 10, count 0 2006.258.01:35:52.59#ibcon#about to read 6, iclass 10, count 0 2006.258.01:35:52.59#ibcon#read 6, iclass 10, count 0 2006.258.01:35:52.59#ibcon#end of sib2, iclass 10, count 0 2006.258.01:35:52.59#ibcon#*after write, iclass 10, count 0 2006.258.01:35:52.59#ibcon#*before return 0, iclass 10, count 0 2006.258.01:35:52.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:52.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.258.01:35:52.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.258.01:35:52.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.258.01:35:52.59$vck44/vb=8,4 2006.258.01:35:52.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.258.01:35:52.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.258.01:35:52.59#ibcon#ireg 11 cls_cnt 2 2006.258.01:35:52.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:52.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:52.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:52.65#ibcon#enter wrdev, iclass 12, count 2 2006.258.01:35:52.65#ibcon#first serial, iclass 12, count 2 2006.258.01:35:52.65#ibcon#enter sib2, iclass 12, count 2 2006.258.01:35:52.65#ibcon#flushed, iclass 12, count 2 2006.258.01:35:52.65#ibcon#about to write, iclass 12, count 2 2006.258.01:35:52.65#ibcon#wrote, iclass 12, count 2 2006.258.01:35:52.65#ibcon#about to read 3, iclass 12, count 2 2006.258.01:35:52.67#ibcon#read 3, iclass 12, count 2 2006.258.01:35:52.67#ibcon#about to read 4, iclass 12, count 2 2006.258.01:35:52.67#ibcon#read 4, iclass 12, count 2 2006.258.01:35:52.67#ibcon#about to read 5, iclass 12, count 2 2006.258.01:35:52.67#ibcon#read 5, iclass 12, count 2 2006.258.01:35:52.67#ibcon#about to read 6, iclass 12, count 2 2006.258.01:35:52.67#ibcon#read 6, iclass 12, count 2 2006.258.01:35:52.67#ibcon#end of sib2, iclass 12, count 2 2006.258.01:35:52.67#ibcon#*mode == 0, iclass 12, count 2 2006.258.01:35:52.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.258.01:35:52.67#ibcon#[27=AT08-04\r\n] 2006.258.01:35:52.67#ibcon#*before write, iclass 12, count 2 2006.258.01:35:52.67#ibcon#enter sib2, iclass 12, count 2 2006.258.01:35:52.67#ibcon#flushed, iclass 12, count 2 2006.258.01:35:52.67#ibcon#about to write, iclass 12, count 2 2006.258.01:35:52.67#ibcon#wrote, iclass 12, count 2 2006.258.01:35:52.67#ibcon#about to read 3, iclass 12, count 2 2006.258.01:35:52.70#ibcon#read 3, iclass 12, count 2 2006.258.01:35:52.70#ibcon#about to read 4, iclass 12, count 2 2006.258.01:35:52.70#ibcon#read 4, iclass 12, count 2 2006.258.01:35:52.70#ibcon#about to read 5, iclass 12, count 2 2006.258.01:35:52.70#ibcon#read 5, iclass 12, count 2 2006.258.01:35:52.70#ibcon#about to read 6, iclass 12, count 2 2006.258.01:35:52.70#ibcon#read 6, iclass 12, count 2 2006.258.01:35:52.70#ibcon#end of sib2, iclass 12, count 2 2006.258.01:35:52.70#ibcon#*after write, iclass 12, count 2 2006.258.01:35:52.70#ibcon#*before return 0, iclass 12, count 2 2006.258.01:35:52.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:52.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.258.01:35:52.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.258.01:35:52.70#ibcon#ireg 7 cls_cnt 0 2006.258.01:35:52.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:52.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:52.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:52.82#ibcon#enter wrdev, iclass 12, count 0 2006.258.01:35:52.82#ibcon#first serial, iclass 12, count 0 2006.258.01:35:52.82#ibcon#enter sib2, iclass 12, count 0 2006.258.01:35:52.82#ibcon#flushed, iclass 12, count 0 2006.258.01:35:52.82#ibcon#about to write, iclass 12, count 0 2006.258.01:35:52.82#ibcon#wrote, iclass 12, count 0 2006.258.01:35:52.82#ibcon#about to read 3, iclass 12, count 0 2006.258.01:35:52.84#ibcon#read 3, iclass 12, count 0 2006.258.01:35:52.84#ibcon#about to read 4, iclass 12, count 0 2006.258.01:35:52.84#ibcon#read 4, iclass 12, count 0 2006.258.01:35:52.84#ibcon#about to read 5, iclass 12, count 0 2006.258.01:35:52.84#ibcon#read 5, iclass 12, count 0 2006.258.01:35:52.84#ibcon#about to read 6, iclass 12, count 0 2006.258.01:35:52.84#ibcon#read 6, iclass 12, count 0 2006.258.01:35:52.84#ibcon#end of sib2, iclass 12, count 0 2006.258.01:35:52.84#ibcon#*mode == 0, iclass 12, count 0 2006.258.01:35:52.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.258.01:35:52.84#ibcon#[27=USB\r\n] 2006.258.01:35:52.84#ibcon#*before write, iclass 12, count 0 2006.258.01:35:52.84#ibcon#enter sib2, iclass 12, count 0 2006.258.01:35:52.84#ibcon#flushed, iclass 12, count 0 2006.258.01:35:52.84#ibcon#about to write, iclass 12, count 0 2006.258.01:35:52.84#ibcon#wrote, iclass 12, count 0 2006.258.01:35:52.84#ibcon#about to read 3, iclass 12, count 0 2006.258.01:35:52.87#ibcon#read 3, iclass 12, count 0 2006.258.01:35:52.87#ibcon#about to read 4, iclass 12, count 0 2006.258.01:35:52.87#ibcon#read 4, iclass 12, count 0 2006.258.01:35:52.87#ibcon#about to read 5, iclass 12, count 0 2006.258.01:35:52.87#ibcon#read 5, iclass 12, count 0 2006.258.01:35:52.87#ibcon#about to read 6, iclass 12, count 0 2006.258.01:35:52.87#ibcon#read 6, iclass 12, count 0 2006.258.01:35:52.87#ibcon#end of sib2, iclass 12, count 0 2006.258.01:35:52.87#ibcon#*after write, iclass 12, count 0 2006.258.01:35:52.87#ibcon#*before return 0, iclass 12, count 0 2006.258.01:35:52.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:52.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.258.01:35:52.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.258.01:35:52.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.258.01:35:52.87$vck44/vabw=wide 2006.258.01:35:52.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.258.01:35:52.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.258.01:35:52.87#ibcon#ireg 8 cls_cnt 0 2006.258.01:35:52.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:52.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:52.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:52.87#ibcon#enter wrdev, iclass 14, count 0 2006.258.01:35:52.87#ibcon#first serial, iclass 14, count 0 2006.258.01:35:52.87#ibcon#enter sib2, iclass 14, count 0 2006.258.01:35:52.87#ibcon#flushed, iclass 14, count 0 2006.258.01:35:52.87#ibcon#about to write, iclass 14, count 0 2006.258.01:35:52.87#ibcon#wrote, iclass 14, count 0 2006.258.01:35:52.87#ibcon#about to read 3, iclass 14, count 0 2006.258.01:35:52.89#ibcon#read 3, iclass 14, count 0 2006.258.01:35:52.89#ibcon#about to read 4, iclass 14, count 0 2006.258.01:35:52.89#ibcon#read 4, iclass 14, count 0 2006.258.01:35:52.89#ibcon#about to read 5, iclass 14, count 0 2006.258.01:35:52.89#ibcon#read 5, iclass 14, count 0 2006.258.01:35:52.89#ibcon#about to read 6, iclass 14, count 0 2006.258.01:35:52.89#ibcon#read 6, iclass 14, count 0 2006.258.01:35:52.89#ibcon#end of sib2, iclass 14, count 0 2006.258.01:35:52.89#ibcon#*mode == 0, iclass 14, count 0 2006.258.01:35:52.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.258.01:35:52.89#ibcon#[25=BW32\r\n] 2006.258.01:35:52.89#ibcon#*before write, iclass 14, count 0 2006.258.01:35:52.89#ibcon#enter sib2, iclass 14, count 0 2006.258.01:35:52.89#ibcon#flushed, iclass 14, count 0 2006.258.01:35:52.89#ibcon#about to write, iclass 14, count 0 2006.258.01:35:52.89#ibcon#wrote, iclass 14, count 0 2006.258.01:35:52.89#ibcon#about to read 3, iclass 14, count 0 2006.258.01:35:52.92#ibcon#read 3, iclass 14, count 0 2006.258.01:35:52.92#ibcon#about to read 4, iclass 14, count 0 2006.258.01:35:52.92#ibcon#read 4, iclass 14, count 0 2006.258.01:35:52.92#ibcon#about to read 5, iclass 14, count 0 2006.258.01:35:52.92#ibcon#read 5, iclass 14, count 0 2006.258.01:35:52.92#ibcon#about to read 6, iclass 14, count 0 2006.258.01:35:52.92#ibcon#read 6, iclass 14, count 0 2006.258.01:35:52.92#ibcon#end of sib2, iclass 14, count 0 2006.258.01:35:52.92#ibcon#*after write, iclass 14, count 0 2006.258.01:35:52.92#ibcon#*before return 0, iclass 14, count 0 2006.258.01:35:52.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:52.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.258.01:35:52.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.258.01:35:52.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.258.01:35:52.92$vck44/vbbw=wide 2006.258.01:35:52.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.258.01:35:52.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.258.01:35:52.92#ibcon#ireg 8 cls_cnt 0 2006.258.01:35:52.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:35:52.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:35:52.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:35:52.99#ibcon#enter wrdev, iclass 16, count 0 2006.258.01:35:52.99#ibcon#first serial, iclass 16, count 0 2006.258.01:35:52.99#ibcon#enter sib2, iclass 16, count 0 2006.258.01:35:52.99#ibcon#flushed, iclass 16, count 0 2006.258.01:35:52.99#ibcon#about to write, iclass 16, count 0 2006.258.01:35:52.99#ibcon#wrote, iclass 16, count 0 2006.258.01:35:52.99#ibcon#about to read 3, iclass 16, count 0 2006.258.01:35:53.01#ibcon#read 3, iclass 16, count 0 2006.258.01:35:53.01#ibcon#about to read 4, iclass 16, count 0 2006.258.01:35:53.01#ibcon#read 4, iclass 16, count 0 2006.258.01:35:53.01#ibcon#about to read 5, iclass 16, count 0 2006.258.01:35:53.01#ibcon#read 5, iclass 16, count 0 2006.258.01:35:53.01#ibcon#about to read 6, iclass 16, count 0 2006.258.01:35:53.01#ibcon#read 6, iclass 16, count 0 2006.258.01:35:53.01#ibcon#end of sib2, iclass 16, count 0 2006.258.01:35:53.01#ibcon#*mode == 0, iclass 16, count 0 2006.258.01:35:53.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.258.01:35:53.01#ibcon#[27=BW32\r\n] 2006.258.01:35:53.01#ibcon#*before write, iclass 16, count 0 2006.258.01:35:53.01#ibcon#enter sib2, iclass 16, count 0 2006.258.01:35:53.01#ibcon#flushed, iclass 16, count 0 2006.258.01:35:53.01#ibcon#about to write, iclass 16, count 0 2006.258.01:35:53.01#ibcon#wrote, iclass 16, count 0 2006.258.01:35:53.01#ibcon#about to read 3, iclass 16, count 0 2006.258.01:35:53.04#ibcon#read 3, iclass 16, count 0 2006.258.01:35:53.04#ibcon#about to read 4, iclass 16, count 0 2006.258.01:35:53.04#ibcon#read 4, iclass 16, count 0 2006.258.01:35:53.04#ibcon#about to read 5, iclass 16, count 0 2006.258.01:35:53.04#ibcon#read 5, iclass 16, count 0 2006.258.01:35:53.04#ibcon#about to read 6, iclass 16, count 0 2006.258.01:35:53.04#ibcon#read 6, iclass 16, count 0 2006.258.01:35:53.04#ibcon#end of sib2, iclass 16, count 0 2006.258.01:35:53.04#ibcon#*after write, iclass 16, count 0 2006.258.01:35:53.04#ibcon#*before return 0, iclass 16, count 0 2006.258.01:35:53.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:35:53.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.258.01:35:53.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.258.01:35:53.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.258.01:35:53.04$setupk4/ifdk4 2006.258.01:35:53.04$ifdk4/lo= 2006.258.01:35:53.04$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.01:35:53.04$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.01:35:53.04$ifdk4/patch= 2006.258.01:35:53.04$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.01:35:53.04$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.01:35:53.04$setupk4/!*+20s 2006.258.01:35:58.73#abcon#<5=/03 3.4 7.0 23.41 701016.0\r\n> 2006.258.01:35:58.75#abcon#{5=INTERFACE CLEAR} 2006.258.01:35:58.81#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:36:07.35$setupk4/"tpicd 2006.258.01:36:07.35$setupk4/echo=off 2006.258.01:36:07.35$setupk4/xlog=off 2006.258.01:36:07.35:!2006.258.01:39:14 2006.258.01:36:10.14#trakl#Source acquired 2006.258.01:36:12.14#flagr#flagr/antenna,acquired 2006.258.01:39:14.00:preob 2006.258.01:39:14.14/onsource/TRACKING 2006.258.01:39:14.14:!2006.258.01:39:24 2006.258.01:39:24.00:"tape 2006.258.01:39:24.00:"st=record 2006.258.01:39:24.00:data_valid=on 2006.258.01:39:24.00:midob 2006.258.01:39:24.14/onsource/TRACKING 2006.258.01:39:24.14/wx/23.52,1016.0,71 2006.258.01:39:24.32/cable/+6.4728E-03 2006.258.01:39:25.41/va/01,08,usb,yes,32,34 2006.258.01:39:25.41/va/02,07,usb,yes,34,35 2006.258.01:39:25.41/va/03,08,usb,yes,31,33 2006.258.01:39:25.41/va/04,07,usb,yes,35,37 2006.258.01:39:25.41/va/05,04,usb,yes,32,32 2006.258.01:39:25.41/va/06,04,usb,yes,35,35 2006.258.01:39:25.41/va/07,04,usb,yes,36,37 2006.258.01:39:25.41/va/08,04,usb,yes,30,37 2006.258.01:39:25.64/valo/01,524.99,yes,locked 2006.258.01:39:25.64/valo/02,534.99,yes,locked 2006.258.01:39:25.64/valo/03,564.99,yes,locked 2006.258.01:39:25.64/valo/04,624.99,yes,locked 2006.258.01:39:25.64/valo/05,734.99,yes,locked 2006.258.01:39:25.64/valo/06,814.99,yes,locked 2006.258.01:39:25.64/valo/07,864.99,yes,locked 2006.258.01:39:25.64/valo/08,884.99,yes,locked 2006.258.01:39:26.73/vb/01,04,usb,yes,32,30 2006.258.01:39:26.73/vb/02,05,usb,yes,30,30 2006.258.01:39:26.73/vb/03,04,usb,yes,31,34 2006.258.01:39:26.73/vb/04,05,usb,yes,31,30 2006.258.01:39:26.73/vb/05,04,usb,yes,28,30 2006.258.01:39:26.73/vb/06,04,usb,yes,32,28 2006.258.01:39:26.73/vb/07,04,usb,yes,32,32 2006.258.01:39:26.73/vb/08,04,usb,yes,29,33 2006.258.01:39:26.97/vblo/01,629.99,yes,locked 2006.258.01:39:26.97/vblo/02,634.99,yes,locked 2006.258.01:39:26.97/vblo/03,649.99,yes,locked 2006.258.01:39:26.97/vblo/04,679.99,yes,locked 2006.258.01:39:26.97/vblo/05,709.99,yes,locked 2006.258.01:39:26.97/vblo/06,719.99,yes,locked 2006.258.01:39:26.97/vblo/07,734.99,yes,locked 2006.258.01:39:26.97/vblo/08,744.99,yes,locked 2006.258.01:39:27.12/vabw/8 2006.258.01:39:27.27/vbbw/8 2006.258.01:39:27.36/xfe/off,on,15.2 2006.258.01:39:27.73/ifatt/23,28,28,28 2006.258.01:39:28.07/fmout-gps/S +4.46E-07 2006.258.01:39:28.11:!2006.258.01:40:24 2006.258.01:40:24.00:data_valid=off 2006.258.01:40:24.00:"et 2006.258.01:40:24.00:!+3s 2006.258.01:40:27.02:"tape 2006.258.01:40:27.02:postob 2006.258.01:40:27.15/cable/+6.4723E-03 2006.258.01:40:27.15/wx/23.52,1016.0,71 2006.258.01:40:28.08/fmout-gps/S +4.47E-07 2006.258.01:40:28.08:scan_name=258-0148,jd0609,50 2006.258.01:40:28.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.258.01:40:28.13#flagr#flagr/antenna,new-source 2006.258.01:40:29.13:checkk5 2006.258.01:40:29.52/chk_autoobs//k5ts1/ autoobs is running! 2006.258.01:40:29.91/chk_autoobs//k5ts2/ autoobs is running! 2006.258.01:40:30.33/chk_autoobs//k5ts3/ autoobs is running! 2006.258.01:40:30.72/chk_autoobs//k5ts4/ autoobs is running! 2006.258.01:40:31.11/chk_obsdata//k5ts1/T2580139??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.258.01:40:31.50/chk_obsdata//k5ts2/T2580139??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.258.01:40:31.89/chk_obsdata//k5ts3/T2580139??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.258.01:40:32.30/chk_obsdata//k5ts4/T2580139??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.258.01:40:33.02/k5log//k5ts1_log_newline 2006.258.01:40:33.74/k5log//k5ts2_log_newline 2006.258.01:40:34.47/k5log//k5ts3_log_newline 2006.258.01:40:35.17/k5log//k5ts4_log_newline 2006.258.01:40:35.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:40:35.20:setupk4=1 2006.258.01:40:35.20$setupk4/echo=on 2006.258.01:40:35.20$setupk4/pcalon 2006.258.01:40:35.20$pcalon/"no phase cal control is implemented here 2006.258.01:40:35.20$setupk4/"tpicd=stop 2006.258.01:40:35.20$setupk4/"rec=synch_on 2006.258.01:40:35.20$setupk4/"rec_mode=128 2006.258.01:40:35.20$setupk4/!* 2006.258.01:40:35.20$setupk4/recpk4 2006.258.01:40:35.20$recpk4/recpatch= 2006.258.01:40:35.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.01:40:35.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.01:40:35.20$setupk4/vck44 2006.258.01:40:35.20$vck44/valo=1,524.99 2006.258.01:40:35.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.01:40:35.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.01:40:35.20#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:35.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:35.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:35.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:35.20#ibcon#enter wrdev, iclass 25, count 0 2006.258.01:40:35.20#ibcon#first serial, iclass 25, count 0 2006.258.01:40:35.20#ibcon#enter sib2, iclass 25, count 0 2006.258.01:40:35.20#ibcon#flushed, iclass 25, count 0 2006.258.01:40:35.20#ibcon#about to write, iclass 25, count 0 2006.258.01:40:35.20#ibcon#wrote, iclass 25, count 0 2006.258.01:40:35.20#ibcon#about to read 3, iclass 25, count 0 2006.258.01:40:35.22#ibcon#read 3, iclass 25, count 0 2006.258.01:40:35.22#ibcon#about to read 4, iclass 25, count 0 2006.258.01:40:35.22#ibcon#read 4, iclass 25, count 0 2006.258.01:40:35.22#ibcon#about to read 5, iclass 25, count 0 2006.258.01:40:35.22#ibcon#read 5, iclass 25, count 0 2006.258.01:40:35.22#ibcon#about to read 6, iclass 25, count 0 2006.258.01:40:35.22#ibcon#read 6, iclass 25, count 0 2006.258.01:40:35.22#ibcon#end of sib2, iclass 25, count 0 2006.258.01:40:35.22#ibcon#*mode == 0, iclass 25, count 0 2006.258.01:40:35.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.01:40:35.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.01:40:35.22#ibcon#*before write, iclass 25, count 0 2006.258.01:40:35.22#ibcon#enter sib2, iclass 25, count 0 2006.258.01:40:35.22#ibcon#flushed, iclass 25, count 0 2006.258.01:40:35.22#ibcon#about to write, iclass 25, count 0 2006.258.01:40:35.22#ibcon#wrote, iclass 25, count 0 2006.258.01:40:35.22#ibcon#about to read 3, iclass 25, count 0 2006.258.01:40:35.27#ibcon#read 3, iclass 25, count 0 2006.258.01:40:35.27#ibcon#about to read 4, iclass 25, count 0 2006.258.01:40:35.27#ibcon#read 4, iclass 25, count 0 2006.258.01:40:35.27#ibcon#about to read 5, iclass 25, count 0 2006.258.01:40:35.27#ibcon#read 5, iclass 25, count 0 2006.258.01:40:35.27#ibcon#about to read 6, iclass 25, count 0 2006.258.01:40:35.27#ibcon#read 6, iclass 25, count 0 2006.258.01:40:35.27#ibcon#end of sib2, iclass 25, count 0 2006.258.01:40:35.27#ibcon#*after write, iclass 25, count 0 2006.258.01:40:35.27#ibcon#*before return 0, iclass 25, count 0 2006.258.01:40:35.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:35.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:35.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.01:40:35.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.01:40:35.27$vck44/va=1,8 2006.258.01:40:35.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.258.01:40:35.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.258.01:40:35.27#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:35.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:35.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:35.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:35.27#ibcon#enter wrdev, iclass 27, count 2 2006.258.01:40:35.27#ibcon#first serial, iclass 27, count 2 2006.258.01:40:35.27#ibcon#enter sib2, iclass 27, count 2 2006.258.01:40:35.27#ibcon#flushed, iclass 27, count 2 2006.258.01:40:35.27#ibcon#about to write, iclass 27, count 2 2006.258.01:40:35.27#ibcon#wrote, iclass 27, count 2 2006.258.01:40:35.27#ibcon#about to read 3, iclass 27, count 2 2006.258.01:40:35.29#ibcon#read 3, iclass 27, count 2 2006.258.01:40:35.29#ibcon#about to read 4, iclass 27, count 2 2006.258.01:40:35.29#ibcon#read 4, iclass 27, count 2 2006.258.01:40:35.29#ibcon#about to read 5, iclass 27, count 2 2006.258.01:40:35.29#ibcon#read 5, iclass 27, count 2 2006.258.01:40:35.29#ibcon#about to read 6, iclass 27, count 2 2006.258.01:40:35.29#ibcon#read 6, iclass 27, count 2 2006.258.01:40:35.29#ibcon#end of sib2, iclass 27, count 2 2006.258.01:40:35.29#ibcon#*mode == 0, iclass 27, count 2 2006.258.01:40:35.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.258.01:40:35.29#ibcon#[25=AT01-08\r\n] 2006.258.01:40:35.29#ibcon#*before write, iclass 27, count 2 2006.258.01:40:35.29#ibcon#enter sib2, iclass 27, count 2 2006.258.01:40:35.29#ibcon#flushed, iclass 27, count 2 2006.258.01:40:35.29#ibcon#about to write, iclass 27, count 2 2006.258.01:40:35.29#ibcon#wrote, iclass 27, count 2 2006.258.01:40:35.29#ibcon#about to read 3, iclass 27, count 2 2006.258.01:40:35.32#ibcon#read 3, iclass 27, count 2 2006.258.01:40:35.32#ibcon#about to read 4, iclass 27, count 2 2006.258.01:40:35.32#ibcon#read 4, iclass 27, count 2 2006.258.01:40:35.32#ibcon#about to read 5, iclass 27, count 2 2006.258.01:40:35.32#ibcon#read 5, iclass 27, count 2 2006.258.01:40:35.32#ibcon#about to read 6, iclass 27, count 2 2006.258.01:40:35.32#ibcon#read 6, iclass 27, count 2 2006.258.01:40:35.32#ibcon#end of sib2, iclass 27, count 2 2006.258.01:40:35.32#ibcon#*after write, iclass 27, count 2 2006.258.01:40:35.32#ibcon#*before return 0, iclass 27, count 2 2006.258.01:40:35.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:35.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:35.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.258.01:40:35.32#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:35.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:35.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:35.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:35.44#ibcon#enter wrdev, iclass 27, count 0 2006.258.01:40:35.44#ibcon#first serial, iclass 27, count 0 2006.258.01:40:35.44#ibcon#enter sib2, iclass 27, count 0 2006.258.01:40:35.44#ibcon#flushed, iclass 27, count 0 2006.258.01:40:35.44#ibcon#about to write, iclass 27, count 0 2006.258.01:40:35.44#ibcon#wrote, iclass 27, count 0 2006.258.01:40:35.44#ibcon#about to read 3, iclass 27, count 0 2006.258.01:40:35.46#ibcon#read 3, iclass 27, count 0 2006.258.01:40:35.46#ibcon#about to read 4, iclass 27, count 0 2006.258.01:40:35.46#ibcon#read 4, iclass 27, count 0 2006.258.01:40:35.46#ibcon#about to read 5, iclass 27, count 0 2006.258.01:40:35.46#ibcon#read 5, iclass 27, count 0 2006.258.01:40:35.46#ibcon#about to read 6, iclass 27, count 0 2006.258.01:40:35.46#ibcon#read 6, iclass 27, count 0 2006.258.01:40:35.46#ibcon#end of sib2, iclass 27, count 0 2006.258.01:40:35.46#ibcon#*mode == 0, iclass 27, count 0 2006.258.01:40:35.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.01:40:35.46#ibcon#[25=USB\r\n] 2006.258.01:40:35.46#ibcon#*before write, iclass 27, count 0 2006.258.01:40:35.46#ibcon#enter sib2, iclass 27, count 0 2006.258.01:40:35.46#ibcon#flushed, iclass 27, count 0 2006.258.01:40:35.46#ibcon#about to write, iclass 27, count 0 2006.258.01:40:35.46#ibcon#wrote, iclass 27, count 0 2006.258.01:40:35.46#ibcon#about to read 3, iclass 27, count 0 2006.258.01:40:35.49#ibcon#read 3, iclass 27, count 0 2006.258.01:40:35.49#ibcon#about to read 4, iclass 27, count 0 2006.258.01:40:35.49#ibcon#read 4, iclass 27, count 0 2006.258.01:40:35.49#ibcon#about to read 5, iclass 27, count 0 2006.258.01:40:35.49#ibcon#read 5, iclass 27, count 0 2006.258.01:40:35.49#ibcon#about to read 6, iclass 27, count 0 2006.258.01:40:35.49#ibcon#read 6, iclass 27, count 0 2006.258.01:40:35.49#ibcon#end of sib2, iclass 27, count 0 2006.258.01:40:35.49#ibcon#*after write, iclass 27, count 0 2006.258.01:40:35.49#ibcon#*before return 0, iclass 27, count 0 2006.258.01:40:35.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:35.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:35.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.01:40:35.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.01:40:35.49$vck44/valo=2,534.99 2006.258.01:40:35.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.01:40:35.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.01:40:35.49#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:35.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:35.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:35.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:35.49#ibcon#enter wrdev, iclass 29, count 0 2006.258.01:40:35.49#ibcon#first serial, iclass 29, count 0 2006.258.01:40:35.49#ibcon#enter sib2, iclass 29, count 0 2006.258.01:40:35.49#ibcon#flushed, iclass 29, count 0 2006.258.01:40:35.49#ibcon#about to write, iclass 29, count 0 2006.258.01:40:35.49#ibcon#wrote, iclass 29, count 0 2006.258.01:40:35.49#ibcon#about to read 3, iclass 29, count 0 2006.258.01:40:35.51#ibcon#read 3, iclass 29, count 0 2006.258.01:40:35.51#ibcon#about to read 4, iclass 29, count 0 2006.258.01:40:35.51#ibcon#read 4, iclass 29, count 0 2006.258.01:40:35.51#ibcon#about to read 5, iclass 29, count 0 2006.258.01:40:35.51#ibcon#read 5, iclass 29, count 0 2006.258.01:40:35.51#ibcon#about to read 6, iclass 29, count 0 2006.258.01:40:35.51#ibcon#read 6, iclass 29, count 0 2006.258.01:40:35.51#ibcon#end of sib2, iclass 29, count 0 2006.258.01:40:35.51#ibcon#*mode == 0, iclass 29, count 0 2006.258.01:40:35.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.01:40:35.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.01:40:35.51#ibcon#*before write, iclass 29, count 0 2006.258.01:40:35.51#ibcon#enter sib2, iclass 29, count 0 2006.258.01:40:35.51#ibcon#flushed, iclass 29, count 0 2006.258.01:40:35.51#ibcon#about to write, iclass 29, count 0 2006.258.01:40:35.51#ibcon#wrote, iclass 29, count 0 2006.258.01:40:35.51#ibcon#about to read 3, iclass 29, count 0 2006.258.01:40:35.55#ibcon#read 3, iclass 29, count 0 2006.258.01:40:35.55#ibcon#about to read 4, iclass 29, count 0 2006.258.01:40:35.55#ibcon#read 4, iclass 29, count 0 2006.258.01:40:35.55#ibcon#about to read 5, iclass 29, count 0 2006.258.01:40:35.55#ibcon#read 5, iclass 29, count 0 2006.258.01:40:35.55#ibcon#about to read 6, iclass 29, count 0 2006.258.01:40:35.55#ibcon#read 6, iclass 29, count 0 2006.258.01:40:35.55#ibcon#end of sib2, iclass 29, count 0 2006.258.01:40:35.55#ibcon#*after write, iclass 29, count 0 2006.258.01:40:35.55#ibcon#*before return 0, iclass 29, count 0 2006.258.01:40:35.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:35.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:35.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.01:40:35.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.01:40:35.55$vck44/va=2,7 2006.258.01:40:35.55#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.01:40:35.55#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.01:40:35.55#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:35.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:35.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:35.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:35.61#ibcon#enter wrdev, iclass 31, count 2 2006.258.01:40:35.61#ibcon#first serial, iclass 31, count 2 2006.258.01:40:35.61#ibcon#enter sib2, iclass 31, count 2 2006.258.01:40:35.61#ibcon#flushed, iclass 31, count 2 2006.258.01:40:35.61#ibcon#about to write, iclass 31, count 2 2006.258.01:40:35.61#ibcon#wrote, iclass 31, count 2 2006.258.01:40:35.61#ibcon#about to read 3, iclass 31, count 2 2006.258.01:40:35.63#ibcon#read 3, iclass 31, count 2 2006.258.01:40:35.63#ibcon#about to read 4, iclass 31, count 2 2006.258.01:40:35.63#ibcon#read 4, iclass 31, count 2 2006.258.01:40:35.63#ibcon#about to read 5, iclass 31, count 2 2006.258.01:40:35.63#ibcon#read 5, iclass 31, count 2 2006.258.01:40:35.63#ibcon#about to read 6, iclass 31, count 2 2006.258.01:40:35.63#ibcon#read 6, iclass 31, count 2 2006.258.01:40:35.63#ibcon#end of sib2, iclass 31, count 2 2006.258.01:40:35.63#ibcon#*mode == 0, iclass 31, count 2 2006.258.01:40:35.63#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.01:40:35.63#ibcon#[25=AT02-07\r\n] 2006.258.01:40:35.63#ibcon#*before write, iclass 31, count 2 2006.258.01:40:35.63#ibcon#enter sib2, iclass 31, count 2 2006.258.01:40:35.63#ibcon#flushed, iclass 31, count 2 2006.258.01:40:35.63#ibcon#about to write, iclass 31, count 2 2006.258.01:40:35.63#ibcon#wrote, iclass 31, count 2 2006.258.01:40:35.63#ibcon#about to read 3, iclass 31, count 2 2006.258.01:40:35.66#ibcon#read 3, iclass 31, count 2 2006.258.01:40:35.66#ibcon#about to read 4, iclass 31, count 2 2006.258.01:40:35.66#ibcon#read 4, iclass 31, count 2 2006.258.01:40:35.66#ibcon#about to read 5, iclass 31, count 2 2006.258.01:40:35.66#ibcon#read 5, iclass 31, count 2 2006.258.01:40:35.66#ibcon#about to read 6, iclass 31, count 2 2006.258.01:40:35.66#ibcon#read 6, iclass 31, count 2 2006.258.01:40:35.66#ibcon#end of sib2, iclass 31, count 2 2006.258.01:40:35.66#ibcon#*after write, iclass 31, count 2 2006.258.01:40:35.66#ibcon#*before return 0, iclass 31, count 2 2006.258.01:40:35.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:35.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:35.66#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.01:40:35.66#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:35.66#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:35.78#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:35.78#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:35.78#ibcon#enter wrdev, iclass 31, count 0 2006.258.01:40:35.78#ibcon#first serial, iclass 31, count 0 2006.258.01:40:35.78#ibcon#enter sib2, iclass 31, count 0 2006.258.01:40:35.78#ibcon#flushed, iclass 31, count 0 2006.258.01:40:35.78#ibcon#about to write, iclass 31, count 0 2006.258.01:40:35.78#ibcon#wrote, iclass 31, count 0 2006.258.01:40:35.78#ibcon#about to read 3, iclass 31, count 0 2006.258.01:40:35.80#ibcon#read 3, iclass 31, count 0 2006.258.01:40:35.80#ibcon#about to read 4, iclass 31, count 0 2006.258.01:40:35.80#ibcon#read 4, iclass 31, count 0 2006.258.01:40:35.80#ibcon#about to read 5, iclass 31, count 0 2006.258.01:40:35.80#ibcon#read 5, iclass 31, count 0 2006.258.01:40:35.80#ibcon#about to read 6, iclass 31, count 0 2006.258.01:40:35.80#ibcon#read 6, iclass 31, count 0 2006.258.01:40:35.80#ibcon#end of sib2, iclass 31, count 0 2006.258.01:40:35.80#ibcon#*mode == 0, iclass 31, count 0 2006.258.01:40:35.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.01:40:35.80#ibcon#[25=USB\r\n] 2006.258.01:40:35.80#ibcon#*before write, iclass 31, count 0 2006.258.01:40:35.80#ibcon#enter sib2, iclass 31, count 0 2006.258.01:40:35.80#ibcon#flushed, iclass 31, count 0 2006.258.01:40:35.80#ibcon#about to write, iclass 31, count 0 2006.258.01:40:35.80#ibcon#wrote, iclass 31, count 0 2006.258.01:40:35.80#ibcon#about to read 3, iclass 31, count 0 2006.258.01:40:35.83#ibcon#read 3, iclass 31, count 0 2006.258.01:40:35.83#ibcon#about to read 4, iclass 31, count 0 2006.258.01:40:35.83#ibcon#read 4, iclass 31, count 0 2006.258.01:40:35.83#ibcon#about to read 5, iclass 31, count 0 2006.258.01:40:35.83#ibcon#read 5, iclass 31, count 0 2006.258.01:40:35.83#ibcon#about to read 6, iclass 31, count 0 2006.258.01:40:35.83#ibcon#read 6, iclass 31, count 0 2006.258.01:40:35.83#ibcon#end of sib2, iclass 31, count 0 2006.258.01:40:35.83#ibcon#*after write, iclass 31, count 0 2006.258.01:40:35.83#ibcon#*before return 0, iclass 31, count 0 2006.258.01:40:35.83#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:35.83#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:35.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.01:40:35.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.01:40:35.83$vck44/valo=3,564.99 2006.258.01:40:35.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.01:40:35.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.01:40:35.83#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:35.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:35.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:35.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:35.83#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:40:35.83#ibcon#first serial, iclass 33, count 0 2006.258.01:40:35.83#ibcon#enter sib2, iclass 33, count 0 2006.258.01:40:35.83#ibcon#flushed, iclass 33, count 0 2006.258.01:40:35.83#ibcon#about to write, iclass 33, count 0 2006.258.01:40:35.83#ibcon#wrote, iclass 33, count 0 2006.258.01:40:35.83#ibcon#about to read 3, iclass 33, count 0 2006.258.01:40:35.85#ibcon#read 3, iclass 33, count 0 2006.258.01:40:35.85#ibcon#about to read 4, iclass 33, count 0 2006.258.01:40:35.85#ibcon#read 4, iclass 33, count 0 2006.258.01:40:35.85#ibcon#about to read 5, iclass 33, count 0 2006.258.01:40:35.85#ibcon#read 5, iclass 33, count 0 2006.258.01:40:35.85#ibcon#about to read 6, iclass 33, count 0 2006.258.01:40:35.85#ibcon#read 6, iclass 33, count 0 2006.258.01:40:35.85#ibcon#end of sib2, iclass 33, count 0 2006.258.01:40:35.85#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:40:35.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:40:35.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.01:40:35.85#ibcon#*before write, iclass 33, count 0 2006.258.01:40:35.85#ibcon#enter sib2, iclass 33, count 0 2006.258.01:40:35.85#ibcon#flushed, iclass 33, count 0 2006.258.01:40:35.85#ibcon#about to write, iclass 33, count 0 2006.258.01:40:35.85#ibcon#wrote, iclass 33, count 0 2006.258.01:40:35.85#ibcon#about to read 3, iclass 33, count 0 2006.258.01:40:35.89#ibcon#read 3, iclass 33, count 0 2006.258.01:40:35.89#ibcon#about to read 4, iclass 33, count 0 2006.258.01:40:35.89#ibcon#read 4, iclass 33, count 0 2006.258.01:40:35.89#ibcon#about to read 5, iclass 33, count 0 2006.258.01:40:35.89#ibcon#read 5, iclass 33, count 0 2006.258.01:40:35.89#ibcon#about to read 6, iclass 33, count 0 2006.258.01:40:35.89#ibcon#read 6, iclass 33, count 0 2006.258.01:40:35.89#ibcon#end of sib2, iclass 33, count 0 2006.258.01:40:35.89#ibcon#*after write, iclass 33, count 0 2006.258.01:40:35.89#ibcon#*before return 0, iclass 33, count 0 2006.258.01:40:35.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:35.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:35.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:40:35.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:40:35.89$vck44/va=3,8 2006.258.01:40:35.89#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.01:40:35.89#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.01:40:35.89#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:35.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:35.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:35.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:35.95#ibcon#enter wrdev, iclass 35, count 2 2006.258.01:40:35.95#ibcon#first serial, iclass 35, count 2 2006.258.01:40:35.95#ibcon#enter sib2, iclass 35, count 2 2006.258.01:40:35.95#ibcon#flushed, iclass 35, count 2 2006.258.01:40:35.95#ibcon#about to write, iclass 35, count 2 2006.258.01:40:35.95#ibcon#wrote, iclass 35, count 2 2006.258.01:40:35.95#ibcon#about to read 3, iclass 35, count 2 2006.258.01:40:35.97#ibcon#read 3, iclass 35, count 2 2006.258.01:40:35.97#ibcon#about to read 4, iclass 35, count 2 2006.258.01:40:35.97#ibcon#read 4, iclass 35, count 2 2006.258.01:40:35.97#ibcon#about to read 5, iclass 35, count 2 2006.258.01:40:35.97#ibcon#read 5, iclass 35, count 2 2006.258.01:40:35.97#ibcon#about to read 6, iclass 35, count 2 2006.258.01:40:35.97#ibcon#read 6, iclass 35, count 2 2006.258.01:40:35.97#ibcon#end of sib2, iclass 35, count 2 2006.258.01:40:35.97#ibcon#*mode == 0, iclass 35, count 2 2006.258.01:40:35.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.01:40:35.97#ibcon#[25=AT03-08\r\n] 2006.258.01:40:35.97#ibcon#*before write, iclass 35, count 2 2006.258.01:40:35.97#ibcon#enter sib2, iclass 35, count 2 2006.258.01:40:35.97#ibcon#flushed, iclass 35, count 2 2006.258.01:40:35.97#ibcon#about to write, iclass 35, count 2 2006.258.01:40:35.97#ibcon#wrote, iclass 35, count 2 2006.258.01:40:35.97#ibcon#about to read 3, iclass 35, count 2 2006.258.01:40:36.00#ibcon#read 3, iclass 35, count 2 2006.258.01:40:36.00#ibcon#about to read 4, iclass 35, count 2 2006.258.01:40:36.00#ibcon#read 4, iclass 35, count 2 2006.258.01:40:36.00#ibcon#about to read 5, iclass 35, count 2 2006.258.01:40:36.00#ibcon#read 5, iclass 35, count 2 2006.258.01:40:36.00#ibcon#about to read 6, iclass 35, count 2 2006.258.01:40:36.00#ibcon#read 6, iclass 35, count 2 2006.258.01:40:36.00#ibcon#end of sib2, iclass 35, count 2 2006.258.01:40:36.00#ibcon#*after write, iclass 35, count 2 2006.258.01:40:36.00#ibcon#*before return 0, iclass 35, count 2 2006.258.01:40:36.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:36.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:36.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.01:40:36.00#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:36.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:36.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:36.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:36.12#ibcon#enter wrdev, iclass 35, count 0 2006.258.01:40:36.12#ibcon#first serial, iclass 35, count 0 2006.258.01:40:36.12#ibcon#enter sib2, iclass 35, count 0 2006.258.01:40:36.12#ibcon#flushed, iclass 35, count 0 2006.258.01:40:36.12#ibcon#about to write, iclass 35, count 0 2006.258.01:40:36.12#ibcon#wrote, iclass 35, count 0 2006.258.01:40:36.12#ibcon#about to read 3, iclass 35, count 0 2006.258.01:40:36.14#ibcon#read 3, iclass 35, count 0 2006.258.01:40:36.14#ibcon#about to read 4, iclass 35, count 0 2006.258.01:40:36.14#ibcon#read 4, iclass 35, count 0 2006.258.01:40:36.14#ibcon#about to read 5, iclass 35, count 0 2006.258.01:40:36.14#ibcon#read 5, iclass 35, count 0 2006.258.01:40:36.14#ibcon#about to read 6, iclass 35, count 0 2006.258.01:40:36.14#ibcon#read 6, iclass 35, count 0 2006.258.01:40:36.14#ibcon#end of sib2, iclass 35, count 0 2006.258.01:40:36.14#ibcon#*mode == 0, iclass 35, count 0 2006.258.01:40:36.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.01:40:36.14#ibcon#[25=USB\r\n] 2006.258.01:40:36.14#ibcon#*before write, iclass 35, count 0 2006.258.01:40:36.14#ibcon#enter sib2, iclass 35, count 0 2006.258.01:40:36.14#ibcon#flushed, iclass 35, count 0 2006.258.01:40:36.14#ibcon#about to write, iclass 35, count 0 2006.258.01:40:36.14#ibcon#wrote, iclass 35, count 0 2006.258.01:40:36.14#ibcon#about to read 3, iclass 35, count 0 2006.258.01:40:36.17#ibcon#read 3, iclass 35, count 0 2006.258.01:40:36.17#ibcon#about to read 4, iclass 35, count 0 2006.258.01:40:36.17#ibcon#read 4, iclass 35, count 0 2006.258.01:40:36.17#ibcon#about to read 5, iclass 35, count 0 2006.258.01:40:36.17#ibcon#read 5, iclass 35, count 0 2006.258.01:40:36.17#ibcon#about to read 6, iclass 35, count 0 2006.258.01:40:36.17#ibcon#read 6, iclass 35, count 0 2006.258.01:40:36.17#ibcon#end of sib2, iclass 35, count 0 2006.258.01:40:36.17#ibcon#*after write, iclass 35, count 0 2006.258.01:40:36.17#ibcon#*before return 0, iclass 35, count 0 2006.258.01:40:36.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:36.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:36.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.01:40:36.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.01:40:36.17$vck44/valo=4,624.99 2006.258.01:40:36.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.01:40:36.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.01:40:36.17#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:36.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:36.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:36.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:36.17#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:40:36.17#ibcon#first serial, iclass 37, count 0 2006.258.01:40:36.17#ibcon#enter sib2, iclass 37, count 0 2006.258.01:40:36.17#ibcon#flushed, iclass 37, count 0 2006.258.01:40:36.17#ibcon#about to write, iclass 37, count 0 2006.258.01:40:36.17#ibcon#wrote, iclass 37, count 0 2006.258.01:40:36.17#ibcon#about to read 3, iclass 37, count 0 2006.258.01:40:36.19#ibcon#read 3, iclass 37, count 0 2006.258.01:40:36.19#ibcon#about to read 4, iclass 37, count 0 2006.258.01:40:36.19#ibcon#read 4, iclass 37, count 0 2006.258.01:40:36.19#ibcon#about to read 5, iclass 37, count 0 2006.258.01:40:36.19#ibcon#read 5, iclass 37, count 0 2006.258.01:40:36.19#ibcon#about to read 6, iclass 37, count 0 2006.258.01:40:36.19#ibcon#read 6, iclass 37, count 0 2006.258.01:40:36.19#ibcon#end of sib2, iclass 37, count 0 2006.258.01:40:36.19#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:40:36.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:40:36.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.01:40:36.19#ibcon#*before write, iclass 37, count 0 2006.258.01:40:36.19#ibcon#enter sib2, iclass 37, count 0 2006.258.01:40:36.19#ibcon#flushed, iclass 37, count 0 2006.258.01:40:36.19#ibcon#about to write, iclass 37, count 0 2006.258.01:40:36.19#ibcon#wrote, iclass 37, count 0 2006.258.01:40:36.19#ibcon#about to read 3, iclass 37, count 0 2006.258.01:40:36.23#ibcon#read 3, iclass 37, count 0 2006.258.01:40:36.23#ibcon#about to read 4, iclass 37, count 0 2006.258.01:40:36.23#ibcon#read 4, iclass 37, count 0 2006.258.01:40:36.23#ibcon#about to read 5, iclass 37, count 0 2006.258.01:40:36.23#ibcon#read 5, iclass 37, count 0 2006.258.01:40:36.23#ibcon#about to read 6, iclass 37, count 0 2006.258.01:40:36.23#ibcon#read 6, iclass 37, count 0 2006.258.01:40:36.23#ibcon#end of sib2, iclass 37, count 0 2006.258.01:40:36.23#ibcon#*after write, iclass 37, count 0 2006.258.01:40:36.23#ibcon#*before return 0, iclass 37, count 0 2006.258.01:40:36.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:36.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:36.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:40:36.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:40:36.23$vck44/va=4,7 2006.258.01:40:36.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.258.01:40:36.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.258.01:40:36.23#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:36.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:36.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:36.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:36.29#ibcon#enter wrdev, iclass 39, count 2 2006.258.01:40:36.29#ibcon#first serial, iclass 39, count 2 2006.258.01:40:36.29#ibcon#enter sib2, iclass 39, count 2 2006.258.01:40:36.29#ibcon#flushed, iclass 39, count 2 2006.258.01:40:36.29#ibcon#about to write, iclass 39, count 2 2006.258.01:40:36.29#ibcon#wrote, iclass 39, count 2 2006.258.01:40:36.29#ibcon#about to read 3, iclass 39, count 2 2006.258.01:40:36.31#ibcon#read 3, iclass 39, count 2 2006.258.01:40:36.31#ibcon#about to read 4, iclass 39, count 2 2006.258.01:40:36.31#ibcon#read 4, iclass 39, count 2 2006.258.01:40:36.31#ibcon#about to read 5, iclass 39, count 2 2006.258.01:40:36.31#ibcon#read 5, iclass 39, count 2 2006.258.01:40:36.31#ibcon#about to read 6, iclass 39, count 2 2006.258.01:40:36.31#ibcon#read 6, iclass 39, count 2 2006.258.01:40:36.31#ibcon#end of sib2, iclass 39, count 2 2006.258.01:40:36.31#ibcon#*mode == 0, iclass 39, count 2 2006.258.01:40:36.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.258.01:40:36.31#ibcon#[25=AT04-07\r\n] 2006.258.01:40:36.31#ibcon#*before write, iclass 39, count 2 2006.258.01:40:36.31#ibcon#enter sib2, iclass 39, count 2 2006.258.01:40:36.31#ibcon#flushed, iclass 39, count 2 2006.258.01:40:36.31#ibcon#about to write, iclass 39, count 2 2006.258.01:40:36.31#ibcon#wrote, iclass 39, count 2 2006.258.01:40:36.31#ibcon#about to read 3, iclass 39, count 2 2006.258.01:40:36.34#ibcon#read 3, iclass 39, count 2 2006.258.01:40:36.34#ibcon#about to read 4, iclass 39, count 2 2006.258.01:40:36.34#ibcon#read 4, iclass 39, count 2 2006.258.01:40:36.34#ibcon#about to read 5, iclass 39, count 2 2006.258.01:40:36.34#ibcon#read 5, iclass 39, count 2 2006.258.01:40:36.34#ibcon#about to read 6, iclass 39, count 2 2006.258.01:40:36.34#ibcon#read 6, iclass 39, count 2 2006.258.01:40:36.34#ibcon#end of sib2, iclass 39, count 2 2006.258.01:40:36.34#ibcon#*after write, iclass 39, count 2 2006.258.01:40:36.34#ibcon#*before return 0, iclass 39, count 2 2006.258.01:40:36.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:36.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:36.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.258.01:40:36.38#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:36.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:36.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:36.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:36.50#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:40:36.50#ibcon#first serial, iclass 39, count 0 2006.258.01:40:36.50#ibcon#enter sib2, iclass 39, count 0 2006.258.01:40:36.50#ibcon#flushed, iclass 39, count 0 2006.258.01:40:36.50#ibcon#about to write, iclass 39, count 0 2006.258.01:40:36.50#ibcon#wrote, iclass 39, count 0 2006.258.01:40:36.50#ibcon#about to read 3, iclass 39, count 0 2006.258.01:40:36.52#ibcon#read 3, iclass 39, count 0 2006.258.01:40:36.52#ibcon#about to read 4, iclass 39, count 0 2006.258.01:40:36.52#ibcon#read 4, iclass 39, count 0 2006.258.01:40:36.52#ibcon#about to read 5, iclass 39, count 0 2006.258.01:40:36.52#ibcon#read 5, iclass 39, count 0 2006.258.01:40:36.52#ibcon#about to read 6, iclass 39, count 0 2006.258.01:40:36.52#ibcon#read 6, iclass 39, count 0 2006.258.01:40:36.52#ibcon#end of sib2, iclass 39, count 0 2006.258.01:40:36.52#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:40:36.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:40:36.52#ibcon#[25=USB\r\n] 2006.258.01:40:36.52#ibcon#*before write, iclass 39, count 0 2006.258.01:40:36.52#ibcon#enter sib2, iclass 39, count 0 2006.258.01:40:36.52#ibcon#flushed, iclass 39, count 0 2006.258.01:40:36.52#ibcon#about to write, iclass 39, count 0 2006.258.01:40:36.52#ibcon#wrote, iclass 39, count 0 2006.258.01:40:36.52#ibcon#about to read 3, iclass 39, count 0 2006.258.01:40:36.55#ibcon#read 3, iclass 39, count 0 2006.258.01:40:36.55#ibcon#about to read 4, iclass 39, count 0 2006.258.01:40:36.55#ibcon#read 4, iclass 39, count 0 2006.258.01:40:36.55#ibcon#about to read 5, iclass 39, count 0 2006.258.01:40:36.55#ibcon#read 5, iclass 39, count 0 2006.258.01:40:36.55#ibcon#about to read 6, iclass 39, count 0 2006.258.01:40:36.55#ibcon#read 6, iclass 39, count 0 2006.258.01:40:36.55#ibcon#end of sib2, iclass 39, count 0 2006.258.01:40:36.55#ibcon#*after write, iclass 39, count 0 2006.258.01:40:36.55#ibcon#*before return 0, iclass 39, count 0 2006.258.01:40:36.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:36.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:36.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:40:36.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:40:36.55$vck44/valo=5,734.99 2006.258.01:40:36.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.01:40:36.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.01:40:36.55#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:36.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:36.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:36.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:36.55#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:40:36.55#ibcon#first serial, iclass 3, count 0 2006.258.01:40:36.55#ibcon#enter sib2, iclass 3, count 0 2006.258.01:40:36.55#ibcon#flushed, iclass 3, count 0 2006.258.01:40:36.55#ibcon#about to write, iclass 3, count 0 2006.258.01:40:36.55#ibcon#wrote, iclass 3, count 0 2006.258.01:40:36.55#ibcon#about to read 3, iclass 3, count 0 2006.258.01:40:36.57#ibcon#read 3, iclass 3, count 0 2006.258.01:40:36.57#ibcon#about to read 4, iclass 3, count 0 2006.258.01:40:36.57#ibcon#read 4, iclass 3, count 0 2006.258.01:40:36.57#ibcon#about to read 5, iclass 3, count 0 2006.258.01:40:36.57#ibcon#read 5, iclass 3, count 0 2006.258.01:40:36.57#ibcon#about to read 6, iclass 3, count 0 2006.258.01:40:36.57#ibcon#read 6, iclass 3, count 0 2006.258.01:40:36.57#ibcon#end of sib2, iclass 3, count 0 2006.258.01:40:36.57#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:40:36.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:40:36.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.01:40:36.57#ibcon#*before write, iclass 3, count 0 2006.258.01:40:36.57#ibcon#enter sib2, iclass 3, count 0 2006.258.01:40:36.57#ibcon#flushed, iclass 3, count 0 2006.258.01:40:36.57#ibcon#about to write, iclass 3, count 0 2006.258.01:40:36.57#ibcon#wrote, iclass 3, count 0 2006.258.01:40:36.57#ibcon#about to read 3, iclass 3, count 0 2006.258.01:40:36.61#ibcon#read 3, iclass 3, count 0 2006.258.01:40:36.61#ibcon#about to read 4, iclass 3, count 0 2006.258.01:40:36.61#ibcon#read 4, iclass 3, count 0 2006.258.01:40:36.61#ibcon#about to read 5, iclass 3, count 0 2006.258.01:40:36.61#ibcon#read 5, iclass 3, count 0 2006.258.01:40:36.61#ibcon#about to read 6, iclass 3, count 0 2006.258.01:40:36.61#ibcon#read 6, iclass 3, count 0 2006.258.01:40:36.61#ibcon#end of sib2, iclass 3, count 0 2006.258.01:40:36.61#ibcon#*after write, iclass 3, count 0 2006.258.01:40:36.61#ibcon#*before return 0, iclass 3, count 0 2006.258.01:40:36.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:36.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:36.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:40:36.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:40:36.61$vck44/va=5,4 2006.258.01:40:36.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.258.01:40:36.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.258.01:40:36.61#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:36.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:36.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:36.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:36.67#ibcon#enter wrdev, iclass 5, count 2 2006.258.01:40:36.67#ibcon#first serial, iclass 5, count 2 2006.258.01:40:36.67#ibcon#enter sib2, iclass 5, count 2 2006.258.01:40:36.67#ibcon#flushed, iclass 5, count 2 2006.258.01:40:36.67#ibcon#about to write, iclass 5, count 2 2006.258.01:40:36.67#ibcon#wrote, iclass 5, count 2 2006.258.01:40:36.67#ibcon#about to read 3, iclass 5, count 2 2006.258.01:40:36.69#ibcon#read 3, iclass 5, count 2 2006.258.01:40:36.69#ibcon#about to read 4, iclass 5, count 2 2006.258.01:40:36.69#ibcon#read 4, iclass 5, count 2 2006.258.01:40:36.69#ibcon#about to read 5, iclass 5, count 2 2006.258.01:40:36.69#ibcon#read 5, iclass 5, count 2 2006.258.01:40:36.69#ibcon#about to read 6, iclass 5, count 2 2006.258.01:40:36.69#ibcon#read 6, iclass 5, count 2 2006.258.01:40:36.69#ibcon#end of sib2, iclass 5, count 2 2006.258.01:40:36.69#ibcon#*mode == 0, iclass 5, count 2 2006.258.01:40:36.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.258.01:40:36.69#ibcon#[25=AT05-04\r\n] 2006.258.01:40:36.69#ibcon#*before write, iclass 5, count 2 2006.258.01:40:36.69#ibcon#enter sib2, iclass 5, count 2 2006.258.01:40:36.69#ibcon#flushed, iclass 5, count 2 2006.258.01:40:36.69#ibcon#about to write, iclass 5, count 2 2006.258.01:40:36.69#ibcon#wrote, iclass 5, count 2 2006.258.01:40:36.69#ibcon#about to read 3, iclass 5, count 2 2006.258.01:40:36.72#ibcon#read 3, iclass 5, count 2 2006.258.01:40:36.72#ibcon#about to read 4, iclass 5, count 2 2006.258.01:40:36.72#ibcon#read 4, iclass 5, count 2 2006.258.01:40:36.72#ibcon#about to read 5, iclass 5, count 2 2006.258.01:40:36.72#ibcon#read 5, iclass 5, count 2 2006.258.01:40:36.72#ibcon#about to read 6, iclass 5, count 2 2006.258.01:40:36.72#ibcon#read 6, iclass 5, count 2 2006.258.01:40:36.72#ibcon#end of sib2, iclass 5, count 2 2006.258.01:40:36.72#ibcon#*after write, iclass 5, count 2 2006.258.01:40:36.72#ibcon#*before return 0, iclass 5, count 2 2006.258.01:40:36.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:36.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:36.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.258.01:40:36.72#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:36.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:36.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:36.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:36.84#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:40:36.84#ibcon#first serial, iclass 5, count 0 2006.258.01:40:36.84#ibcon#enter sib2, iclass 5, count 0 2006.258.01:40:36.84#ibcon#flushed, iclass 5, count 0 2006.258.01:40:36.84#ibcon#about to write, iclass 5, count 0 2006.258.01:40:36.84#ibcon#wrote, iclass 5, count 0 2006.258.01:40:36.84#ibcon#about to read 3, iclass 5, count 0 2006.258.01:40:36.86#ibcon#read 3, iclass 5, count 0 2006.258.01:40:36.86#ibcon#about to read 4, iclass 5, count 0 2006.258.01:40:36.86#ibcon#read 4, iclass 5, count 0 2006.258.01:40:36.86#ibcon#about to read 5, iclass 5, count 0 2006.258.01:40:36.86#ibcon#read 5, iclass 5, count 0 2006.258.01:40:36.86#ibcon#about to read 6, iclass 5, count 0 2006.258.01:40:36.86#ibcon#read 6, iclass 5, count 0 2006.258.01:40:36.86#ibcon#end of sib2, iclass 5, count 0 2006.258.01:40:36.86#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:40:36.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:40:36.86#ibcon#[25=USB\r\n] 2006.258.01:40:36.86#ibcon#*before write, iclass 5, count 0 2006.258.01:40:36.86#ibcon#enter sib2, iclass 5, count 0 2006.258.01:40:36.86#ibcon#flushed, iclass 5, count 0 2006.258.01:40:36.86#ibcon#about to write, iclass 5, count 0 2006.258.01:40:36.86#ibcon#wrote, iclass 5, count 0 2006.258.01:40:36.86#ibcon#about to read 3, iclass 5, count 0 2006.258.01:40:36.89#ibcon#read 3, iclass 5, count 0 2006.258.01:40:36.89#ibcon#about to read 4, iclass 5, count 0 2006.258.01:40:36.89#ibcon#read 4, iclass 5, count 0 2006.258.01:40:36.89#ibcon#about to read 5, iclass 5, count 0 2006.258.01:40:36.89#ibcon#read 5, iclass 5, count 0 2006.258.01:40:36.89#ibcon#about to read 6, iclass 5, count 0 2006.258.01:40:36.89#ibcon#read 6, iclass 5, count 0 2006.258.01:40:36.89#ibcon#end of sib2, iclass 5, count 0 2006.258.01:40:36.89#ibcon#*after write, iclass 5, count 0 2006.258.01:40:36.89#ibcon#*before return 0, iclass 5, count 0 2006.258.01:40:36.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:36.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:36.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:40:36.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:40:36.89$vck44/valo=6,814.99 2006.258.01:40:36.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.01:40:36.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.01:40:36.89#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:36.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:36.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:36.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:36.89#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:40:36.89#ibcon#first serial, iclass 7, count 0 2006.258.01:40:36.89#ibcon#enter sib2, iclass 7, count 0 2006.258.01:40:36.89#ibcon#flushed, iclass 7, count 0 2006.258.01:40:36.89#ibcon#about to write, iclass 7, count 0 2006.258.01:40:36.89#ibcon#wrote, iclass 7, count 0 2006.258.01:40:36.89#ibcon#about to read 3, iclass 7, count 0 2006.258.01:40:36.91#ibcon#read 3, iclass 7, count 0 2006.258.01:40:36.91#ibcon#about to read 4, iclass 7, count 0 2006.258.01:40:36.91#ibcon#read 4, iclass 7, count 0 2006.258.01:40:36.91#ibcon#about to read 5, iclass 7, count 0 2006.258.01:40:36.91#ibcon#read 5, iclass 7, count 0 2006.258.01:40:36.91#ibcon#about to read 6, iclass 7, count 0 2006.258.01:40:36.91#ibcon#read 6, iclass 7, count 0 2006.258.01:40:36.91#ibcon#end of sib2, iclass 7, count 0 2006.258.01:40:36.91#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:40:36.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:40:36.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.01:40:36.91#ibcon#*before write, iclass 7, count 0 2006.258.01:40:36.91#ibcon#enter sib2, iclass 7, count 0 2006.258.01:40:36.91#ibcon#flushed, iclass 7, count 0 2006.258.01:40:36.91#ibcon#about to write, iclass 7, count 0 2006.258.01:40:36.91#ibcon#wrote, iclass 7, count 0 2006.258.01:40:36.91#ibcon#about to read 3, iclass 7, count 0 2006.258.01:40:36.95#ibcon#read 3, iclass 7, count 0 2006.258.01:40:36.95#ibcon#about to read 4, iclass 7, count 0 2006.258.01:40:36.95#ibcon#read 4, iclass 7, count 0 2006.258.01:40:36.95#ibcon#about to read 5, iclass 7, count 0 2006.258.01:40:36.95#ibcon#read 5, iclass 7, count 0 2006.258.01:40:36.95#ibcon#about to read 6, iclass 7, count 0 2006.258.01:40:36.95#ibcon#read 6, iclass 7, count 0 2006.258.01:40:36.95#ibcon#end of sib2, iclass 7, count 0 2006.258.01:40:36.95#ibcon#*after write, iclass 7, count 0 2006.258.01:40:36.95#ibcon#*before return 0, iclass 7, count 0 2006.258.01:40:36.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:36.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:36.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:40:36.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:40:36.95$vck44/va=6,4 2006.258.01:40:36.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.01:40:36.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.01:40:36.95#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:36.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:37.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:37.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:37.01#ibcon#enter wrdev, iclass 11, count 2 2006.258.01:40:37.01#ibcon#first serial, iclass 11, count 2 2006.258.01:40:37.01#ibcon#enter sib2, iclass 11, count 2 2006.258.01:40:37.01#ibcon#flushed, iclass 11, count 2 2006.258.01:40:37.01#ibcon#about to write, iclass 11, count 2 2006.258.01:40:37.01#ibcon#wrote, iclass 11, count 2 2006.258.01:40:37.01#ibcon#about to read 3, iclass 11, count 2 2006.258.01:40:37.03#ibcon#read 3, iclass 11, count 2 2006.258.01:40:37.03#ibcon#about to read 4, iclass 11, count 2 2006.258.01:40:37.03#ibcon#read 4, iclass 11, count 2 2006.258.01:40:37.03#ibcon#about to read 5, iclass 11, count 2 2006.258.01:40:37.03#ibcon#read 5, iclass 11, count 2 2006.258.01:40:37.03#ibcon#about to read 6, iclass 11, count 2 2006.258.01:40:37.03#ibcon#read 6, iclass 11, count 2 2006.258.01:40:37.03#ibcon#end of sib2, iclass 11, count 2 2006.258.01:40:37.03#ibcon#*mode == 0, iclass 11, count 2 2006.258.01:40:37.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.01:40:37.03#ibcon#[25=AT06-04\r\n] 2006.258.01:40:37.03#ibcon#*before write, iclass 11, count 2 2006.258.01:40:37.03#ibcon#enter sib2, iclass 11, count 2 2006.258.01:40:37.03#ibcon#flushed, iclass 11, count 2 2006.258.01:40:37.03#ibcon#about to write, iclass 11, count 2 2006.258.01:40:37.03#ibcon#wrote, iclass 11, count 2 2006.258.01:40:37.03#ibcon#about to read 3, iclass 11, count 2 2006.258.01:40:37.06#ibcon#read 3, iclass 11, count 2 2006.258.01:40:37.06#ibcon#about to read 4, iclass 11, count 2 2006.258.01:40:37.06#ibcon#read 4, iclass 11, count 2 2006.258.01:40:37.06#ibcon#about to read 5, iclass 11, count 2 2006.258.01:40:37.06#ibcon#read 5, iclass 11, count 2 2006.258.01:40:37.06#ibcon#about to read 6, iclass 11, count 2 2006.258.01:40:37.06#ibcon#read 6, iclass 11, count 2 2006.258.01:40:37.06#ibcon#end of sib2, iclass 11, count 2 2006.258.01:40:37.06#ibcon#*after write, iclass 11, count 2 2006.258.01:40:37.06#ibcon#*before return 0, iclass 11, count 2 2006.258.01:40:37.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:37.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:37.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.01:40:37.06#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:37.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:37.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:37.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:37.18#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:40:37.18#ibcon#first serial, iclass 11, count 0 2006.258.01:40:37.18#ibcon#enter sib2, iclass 11, count 0 2006.258.01:40:37.18#ibcon#flushed, iclass 11, count 0 2006.258.01:40:37.18#ibcon#about to write, iclass 11, count 0 2006.258.01:40:37.18#ibcon#wrote, iclass 11, count 0 2006.258.01:40:37.18#ibcon#about to read 3, iclass 11, count 0 2006.258.01:40:37.20#ibcon#read 3, iclass 11, count 0 2006.258.01:40:37.20#ibcon#about to read 4, iclass 11, count 0 2006.258.01:40:37.20#ibcon#read 4, iclass 11, count 0 2006.258.01:40:37.20#ibcon#about to read 5, iclass 11, count 0 2006.258.01:40:37.20#ibcon#read 5, iclass 11, count 0 2006.258.01:40:37.20#ibcon#about to read 6, iclass 11, count 0 2006.258.01:40:37.20#ibcon#read 6, iclass 11, count 0 2006.258.01:40:37.20#ibcon#end of sib2, iclass 11, count 0 2006.258.01:40:37.20#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:40:37.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:40:37.20#ibcon#[25=USB\r\n] 2006.258.01:40:37.20#ibcon#*before write, iclass 11, count 0 2006.258.01:40:37.20#ibcon#enter sib2, iclass 11, count 0 2006.258.01:40:37.20#ibcon#flushed, iclass 11, count 0 2006.258.01:40:37.20#ibcon#about to write, iclass 11, count 0 2006.258.01:40:37.20#ibcon#wrote, iclass 11, count 0 2006.258.01:40:37.20#ibcon#about to read 3, iclass 11, count 0 2006.258.01:40:37.23#ibcon#read 3, iclass 11, count 0 2006.258.01:40:37.23#ibcon#about to read 4, iclass 11, count 0 2006.258.01:40:37.23#ibcon#read 4, iclass 11, count 0 2006.258.01:40:37.23#ibcon#about to read 5, iclass 11, count 0 2006.258.01:40:37.23#ibcon#read 5, iclass 11, count 0 2006.258.01:40:37.23#ibcon#about to read 6, iclass 11, count 0 2006.258.01:40:37.23#ibcon#read 6, iclass 11, count 0 2006.258.01:40:37.23#ibcon#end of sib2, iclass 11, count 0 2006.258.01:40:37.23#ibcon#*after write, iclass 11, count 0 2006.258.01:40:37.23#ibcon#*before return 0, iclass 11, count 0 2006.258.01:40:37.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:37.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:37.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:40:37.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:40:37.23$vck44/valo=7,864.99 2006.258.01:40:37.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.258.01:40:37.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.258.01:40:37.23#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:37.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:37.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:37.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:37.23#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:40:37.23#ibcon#first serial, iclass 13, count 0 2006.258.01:40:37.23#ibcon#enter sib2, iclass 13, count 0 2006.258.01:40:37.23#ibcon#flushed, iclass 13, count 0 2006.258.01:40:37.23#ibcon#about to write, iclass 13, count 0 2006.258.01:40:37.23#ibcon#wrote, iclass 13, count 0 2006.258.01:40:37.23#ibcon#about to read 3, iclass 13, count 0 2006.258.01:40:37.25#ibcon#read 3, iclass 13, count 0 2006.258.01:40:37.25#ibcon#about to read 4, iclass 13, count 0 2006.258.01:40:37.25#ibcon#read 4, iclass 13, count 0 2006.258.01:40:37.25#ibcon#about to read 5, iclass 13, count 0 2006.258.01:40:37.25#ibcon#read 5, iclass 13, count 0 2006.258.01:40:37.25#ibcon#about to read 6, iclass 13, count 0 2006.258.01:40:37.25#ibcon#read 6, iclass 13, count 0 2006.258.01:40:37.25#ibcon#end of sib2, iclass 13, count 0 2006.258.01:40:37.25#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:40:37.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:40:37.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.01:40:37.25#ibcon#*before write, iclass 13, count 0 2006.258.01:40:37.25#ibcon#enter sib2, iclass 13, count 0 2006.258.01:40:37.25#ibcon#flushed, iclass 13, count 0 2006.258.01:40:37.25#ibcon#about to write, iclass 13, count 0 2006.258.01:40:37.25#ibcon#wrote, iclass 13, count 0 2006.258.01:40:37.25#ibcon#about to read 3, iclass 13, count 0 2006.258.01:40:37.29#ibcon#read 3, iclass 13, count 0 2006.258.01:40:37.29#ibcon#about to read 4, iclass 13, count 0 2006.258.01:40:37.29#ibcon#read 4, iclass 13, count 0 2006.258.01:40:37.29#ibcon#about to read 5, iclass 13, count 0 2006.258.01:40:37.29#ibcon#read 5, iclass 13, count 0 2006.258.01:40:37.29#ibcon#about to read 6, iclass 13, count 0 2006.258.01:40:37.29#ibcon#read 6, iclass 13, count 0 2006.258.01:40:37.29#ibcon#end of sib2, iclass 13, count 0 2006.258.01:40:37.29#ibcon#*after write, iclass 13, count 0 2006.258.01:40:37.29#ibcon#*before return 0, iclass 13, count 0 2006.258.01:40:37.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:37.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:37.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:40:37.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:40:37.29$vck44/va=7,4 2006.258.01:40:37.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.258.01:40:37.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.258.01:40:37.29#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:37.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:37.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:37.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:37.35#ibcon#enter wrdev, iclass 15, count 2 2006.258.01:40:37.35#ibcon#first serial, iclass 15, count 2 2006.258.01:40:37.35#ibcon#enter sib2, iclass 15, count 2 2006.258.01:40:37.35#ibcon#flushed, iclass 15, count 2 2006.258.01:40:37.35#ibcon#about to write, iclass 15, count 2 2006.258.01:40:37.35#ibcon#wrote, iclass 15, count 2 2006.258.01:40:37.35#ibcon#about to read 3, iclass 15, count 2 2006.258.01:40:37.37#ibcon#read 3, iclass 15, count 2 2006.258.01:40:37.37#ibcon#about to read 4, iclass 15, count 2 2006.258.01:40:37.37#ibcon#read 4, iclass 15, count 2 2006.258.01:40:37.37#ibcon#about to read 5, iclass 15, count 2 2006.258.01:40:37.37#ibcon#read 5, iclass 15, count 2 2006.258.01:40:37.37#ibcon#about to read 6, iclass 15, count 2 2006.258.01:40:37.37#ibcon#read 6, iclass 15, count 2 2006.258.01:40:37.37#ibcon#end of sib2, iclass 15, count 2 2006.258.01:40:37.37#ibcon#*mode == 0, iclass 15, count 2 2006.258.01:40:37.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.258.01:40:37.37#ibcon#[25=AT07-04\r\n] 2006.258.01:40:37.37#ibcon#*before write, iclass 15, count 2 2006.258.01:40:37.37#ibcon#enter sib2, iclass 15, count 2 2006.258.01:40:37.37#ibcon#flushed, iclass 15, count 2 2006.258.01:40:37.37#ibcon#about to write, iclass 15, count 2 2006.258.01:40:37.37#ibcon#wrote, iclass 15, count 2 2006.258.01:40:37.37#ibcon#about to read 3, iclass 15, count 2 2006.258.01:40:37.40#ibcon#read 3, iclass 15, count 2 2006.258.01:40:37.40#ibcon#about to read 4, iclass 15, count 2 2006.258.01:40:37.40#ibcon#read 4, iclass 15, count 2 2006.258.01:40:37.40#ibcon#about to read 5, iclass 15, count 2 2006.258.01:40:37.40#ibcon#read 5, iclass 15, count 2 2006.258.01:40:37.40#ibcon#about to read 6, iclass 15, count 2 2006.258.01:40:37.40#ibcon#read 6, iclass 15, count 2 2006.258.01:40:37.40#ibcon#end of sib2, iclass 15, count 2 2006.258.01:40:37.40#ibcon#*after write, iclass 15, count 2 2006.258.01:40:37.40#ibcon#*before return 0, iclass 15, count 2 2006.258.01:40:37.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:37.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:37.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.258.01:40:37.41#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:37.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:37.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:37.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:37.53#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:40:37.53#ibcon#first serial, iclass 15, count 0 2006.258.01:40:37.53#ibcon#enter sib2, iclass 15, count 0 2006.258.01:40:37.53#ibcon#flushed, iclass 15, count 0 2006.258.01:40:37.53#ibcon#about to write, iclass 15, count 0 2006.258.01:40:37.53#ibcon#wrote, iclass 15, count 0 2006.258.01:40:37.53#ibcon#about to read 3, iclass 15, count 0 2006.258.01:40:37.55#ibcon#read 3, iclass 15, count 0 2006.258.01:40:37.55#ibcon#about to read 4, iclass 15, count 0 2006.258.01:40:37.55#ibcon#read 4, iclass 15, count 0 2006.258.01:40:37.55#ibcon#about to read 5, iclass 15, count 0 2006.258.01:40:37.55#ibcon#read 5, iclass 15, count 0 2006.258.01:40:37.55#ibcon#about to read 6, iclass 15, count 0 2006.258.01:40:37.55#ibcon#read 6, iclass 15, count 0 2006.258.01:40:37.55#ibcon#end of sib2, iclass 15, count 0 2006.258.01:40:37.55#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:40:37.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:40:37.55#ibcon#[25=USB\r\n] 2006.258.01:40:37.55#ibcon#*before write, iclass 15, count 0 2006.258.01:40:37.55#ibcon#enter sib2, iclass 15, count 0 2006.258.01:40:37.55#ibcon#flushed, iclass 15, count 0 2006.258.01:40:37.55#ibcon#about to write, iclass 15, count 0 2006.258.01:40:37.55#ibcon#wrote, iclass 15, count 0 2006.258.01:40:37.55#ibcon#about to read 3, iclass 15, count 0 2006.258.01:40:37.58#ibcon#read 3, iclass 15, count 0 2006.258.01:40:37.58#ibcon#about to read 4, iclass 15, count 0 2006.258.01:40:37.58#ibcon#read 4, iclass 15, count 0 2006.258.01:40:37.58#ibcon#about to read 5, iclass 15, count 0 2006.258.01:40:37.58#ibcon#read 5, iclass 15, count 0 2006.258.01:40:37.58#ibcon#about to read 6, iclass 15, count 0 2006.258.01:40:37.58#ibcon#read 6, iclass 15, count 0 2006.258.01:40:37.58#ibcon#end of sib2, iclass 15, count 0 2006.258.01:40:37.58#ibcon#*after write, iclass 15, count 0 2006.258.01:40:37.58#ibcon#*before return 0, iclass 15, count 0 2006.258.01:40:37.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:37.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:37.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:40:37.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:40:37.58$vck44/valo=8,884.99 2006.258.01:40:37.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.258.01:40:37.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.258.01:40:37.58#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:37.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:37.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:37.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:37.58#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:40:37.58#ibcon#first serial, iclass 17, count 0 2006.258.01:40:37.58#ibcon#enter sib2, iclass 17, count 0 2006.258.01:40:37.58#ibcon#flushed, iclass 17, count 0 2006.258.01:40:37.58#ibcon#about to write, iclass 17, count 0 2006.258.01:40:37.58#ibcon#wrote, iclass 17, count 0 2006.258.01:40:37.58#ibcon#about to read 3, iclass 17, count 0 2006.258.01:40:37.60#ibcon#read 3, iclass 17, count 0 2006.258.01:40:37.60#ibcon#about to read 4, iclass 17, count 0 2006.258.01:40:37.60#ibcon#read 4, iclass 17, count 0 2006.258.01:40:37.60#ibcon#about to read 5, iclass 17, count 0 2006.258.01:40:37.60#ibcon#read 5, iclass 17, count 0 2006.258.01:40:37.60#ibcon#about to read 6, iclass 17, count 0 2006.258.01:40:37.60#ibcon#read 6, iclass 17, count 0 2006.258.01:40:37.60#ibcon#end of sib2, iclass 17, count 0 2006.258.01:40:37.60#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:40:37.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:40:37.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.01:40:37.60#ibcon#*before write, iclass 17, count 0 2006.258.01:40:37.60#ibcon#enter sib2, iclass 17, count 0 2006.258.01:40:37.60#ibcon#flushed, iclass 17, count 0 2006.258.01:40:37.60#ibcon#about to write, iclass 17, count 0 2006.258.01:40:37.60#ibcon#wrote, iclass 17, count 0 2006.258.01:40:37.60#ibcon#about to read 3, iclass 17, count 0 2006.258.01:40:37.64#ibcon#read 3, iclass 17, count 0 2006.258.01:40:37.64#ibcon#about to read 4, iclass 17, count 0 2006.258.01:40:37.64#ibcon#read 4, iclass 17, count 0 2006.258.01:40:37.64#ibcon#about to read 5, iclass 17, count 0 2006.258.01:40:37.64#ibcon#read 5, iclass 17, count 0 2006.258.01:40:37.64#ibcon#about to read 6, iclass 17, count 0 2006.258.01:40:37.64#ibcon#read 6, iclass 17, count 0 2006.258.01:40:37.64#ibcon#end of sib2, iclass 17, count 0 2006.258.01:40:37.64#ibcon#*after write, iclass 17, count 0 2006.258.01:40:37.64#ibcon#*before return 0, iclass 17, count 0 2006.258.01:40:37.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:37.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:37.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:40:37.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:40:37.64$vck44/va=8,4 2006.258.01:40:37.64#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.258.01:40:37.64#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.258.01:40:37.64#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:37.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:40:37.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:40:37.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:40:37.70#ibcon#enter wrdev, iclass 19, count 2 2006.258.01:40:37.70#ibcon#first serial, iclass 19, count 2 2006.258.01:40:37.70#ibcon#enter sib2, iclass 19, count 2 2006.258.01:40:37.70#ibcon#flushed, iclass 19, count 2 2006.258.01:40:37.70#ibcon#about to write, iclass 19, count 2 2006.258.01:40:37.70#ibcon#wrote, iclass 19, count 2 2006.258.01:40:37.70#ibcon#about to read 3, iclass 19, count 2 2006.258.01:40:37.72#ibcon#read 3, iclass 19, count 2 2006.258.01:40:37.72#ibcon#about to read 4, iclass 19, count 2 2006.258.01:40:37.72#ibcon#read 4, iclass 19, count 2 2006.258.01:40:37.72#ibcon#about to read 5, iclass 19, count 2 2006.258.01:40:37.72#ibcon#read 5, iclass 19, count 2 2006.258.01:40:37.72#ibcon#about to read 6, iclass 19, count 2 2006.258.01:40:37.72#ibcon#read 6, iclass 19, count 2 2006.258.01:40:37.72#ibcon#end of sib2, iclass 19, count 2 2006.258.01:40:37.72#ibcon#*mode == 0, iclass 19, count 2 2006.258.01:40:37.72#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.258.01:40:37.72#ibcon#[25=AT08-04\r\n] 2006.258.01:40:37.72#ibcon#*before write, iclass 19, count 2 2006.258.01:40:37.72#ibcon#enter sib2, iclass 19, count 2 2006.258.01:40:37.72#ibcon#flushed, iclass 19, count 2 2006.258.01:40:37.72#ibcon#about to write, iclass 19, count 2 2006.258.01:40:37.72#ibcon#wrote, iclass 19, count 2 2006.258.01:40:37.72#ibcon#about to read 3, iclass 19, count 2 2006.258.01:40:37.75#ibcon#read 3, iclass 19, count 2 2006.258.01:40:37.75#ibcon#about to read 4, iclass 19, count 2 2006.258.01:40:37.75#ibcon#read 4, iclass 19, count 2 2006.258.01:40:37.75#ibcon#about to read 5, iclass 19, count 2 2006.258.01:40:37.75#ibcon#read 5, iclass 19, count 2 2006.258.01:40:37.75#ibcon#about to read 6, iclass 19, count 2 2006.258.01:40:37.75#ibcon#read 6, iclass 19, count 2 2006.258.01:40:37.75#ibcon#end of sib2, iclass 19, count 2 2006.258.01:40:37.75#ibcon#*after write, iclass 19, count 2 2006.258.01:40:37.75#ibcon#*before return 0, iclass 19, count 2 2006.258.01:40:37.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:40:37.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.258.01:40:37.75#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.258.01:40:37.75#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:37.75#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:40:37.87#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:40:37.87#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:40:37.87#ibcon#enter wrdev, iclass 19, count 0 2006.258.01:40:37.87#ibcon#first serial, iclass 19, count 0 2006.258.01:40:37.87#ibcon#enter sib2, iclass 19, count 0 2006.258.01:40:37.87#ibcon#flushed, iclass 19, count 0 2006.258.01:40:37.87#ibcon#about to write, iclass 19, count 0 2006.258.01:40:37.87#ibcon#wrote, iclass 19, count 0 2006.258.01:40:37.87#ibcon#about to read 3, iclass 19, count 0 2006.258.01:40:37.89#ibcon#read 3, iclass 19, count 0 2006.258.01:40:37.89#ibcon#about to read 4, iclass 19, count 0 2006.258.01:40:37.89#ibcon#read 4, iclass 19, count 0 2006.258.01:40:37.89#ibcon#about to read 5, iclass 19, count 0 2006.258.01:40:37.89#ibcon#read 5, iclass 19, count 0 2006.258.01:40:37.89#ibcon#about to read 6, iclass 19, count 0 2006.258.01:40:37.89#ibcon#read 6, iclass 19, count 0 2006.258.01:40:37.89#ibcon#end of sib2, iclass 19, count 0 2006.258.01:40:37.89#ibcon#*mode == 0, iclass 19, count 0 2006.258.01:40:37.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.01:40:37.89#ibcon#[25=USB\r\n] 2006.258.01:40:37.89#ibcon#*before write, iclass 19, count 0 2006.258.01:40:37.89#ibcon#enter sib2, iclass 19, count 0 2006.258.01:40:37.89#ibcon#flushed, iclass 19, count 0 2006.258.01:40:37.89#ibcon#about to write, iclass 19, count 0 2006.258.01:40:37.89#ibcon#wrote, iclass 19, count 0 2006.258.01:40:37.89#ibcon#about to read 3, iclass 19, count 0 2006.258.01:40:37.92#ibcon#read 3, iclass 19, count 0 2006.258.01:40:37.92#ibcon#about to read 4, iclass 19, count 0 2006.258.01:40:37.92#ibcon#read 4, iclass 19, count 0 2006.258.01:40:37.92#ibcon#about to read 5, iclass 19, count 0 2006.258.01:40:37.92#ibcon#read 5, iclass 19, count 0 2006.258.01:40:37.92#ibcon#about to read 6, iclass 19, count 0 2006.258.01:40:37.92#ibcon#read 6, iclass 19, count 0 2006.258.01:40:37.92#ibcon#end of sib2, iclass 19, count 0 2006.258.01:40:37.92#ibcon#*after write, iclass 19, count 0 2006.258.01:40:37.92#ibcon#*before return 0, iclass 19, count 0 2006.258.01:40:37.92#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:40:37.92#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.258.01:40:37.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.01:40:37.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.01:40:37.92$vck44/vblo=1,629.99 2006.258.01:40:37.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.258.01:40:37.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.258.01:40:37.92#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:37.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:40:37.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:40:37.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:40:37.92#ibcon#enter wrdev, iclass 21, count 0 2006.258.01:40:37.92#ibcon#first serial, iclass 21, count 0 2006.258.01:40:37.92#ibcon#enter sib2, iclass 21, count 0 2006.258.01:40:37.92#ibcon#flushed, iclass 21, count 0 2006.258.01:40:37.92#ibcon#about to write, iclass 21, count 0 2006.258.01:40:37.92#ibcon#wrote, iclass 21, count 0 2006.258.01:40:37.92#ibcon#about to read 3, iclass 21, count 0 2006.258.01:40:37.94#ibcon#read 3, iclass 21, count 0 2006.258.01:40:37.94#ibcon#about to read 4, iclass 21, count 0 2006.258.01:40:37.94#ibcon#read 4, iclass 21, count 0 2006.258.01:40:37.94#ibcon#about to read 5, iclass 21, count 0 2006.258.01:40:37.94#ibcon#read 5, iclass 21, count 0 2006.258.01:40:37.94#ibcon#about to read 6, iclass 21, count 0 2006.258.01:40:37.94#ibcon#read 6, iclass 21, count 0 2006.258.01:40:37.94#ibcon#end of sib2, iclass 21, count 0 2006.258.01:40:37.94#ibcon#*mode == 0, iclass 21, count 0 2006.258.01:40:37.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.01:40:37.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.01:40:37.94#ibcon#*before write, iclass 21, count 0 2006.258.01:40:37.94#ibcon#enter sib2, iclass 21, count 0 2006.258.01:40:37.94#ibcon#flushed, iclass 21, count 0 2006.258.01:40:37.94#ibcon#about to write, iclass 21, count 0 2006.258.01:40:37.94#ibcon#wrote, iclass 21, count 0 2006.258.01:40:37.94#ibcon#about to read 3, iclass 21, count 0 2006.258.01:40:37.98#ibcon#read 3, iclass 21, count 0 2006.258.01:40:37.98#ibcon#about to read 4, iclass 21, count 0 2006.258.01:40:37.98#ibcon#read 4, iclass 21, count 0 2006.258.01:40:37.98#ibcon#about to read 5, iclass 21, count 0 2006.258.01:40:37.98#ibcon#read 5, iclass 21, count 0 2006.258.01:40:37.98#ibcon#about to read 6, iclass 21, count 0 2006.258.01:40:37.98#ibcon#read 6, iclass 21, count 0 2006.258.01:40:37.98#ibcon#end of sib2, iclass 21, count 0 2006.258.01:40:37.98#ibcon#*after write, iclass 21, count 0 2006.258.01:40:37.98#ibcon#*before return 0, iclass 21, count 0 2006.258.01:40:37.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:40:37.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.258.01:40:37.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.01:40:37.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.01:40:37.98$vck44/vb=1,4 2006.258.01:40:37.98#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.258.01:40:37.98#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.258.01:40:37.98#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:37.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:40:37.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:40:37.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:40:37.98#ibcon#enter wrdev, iclass 23, count 2 2006.258.01:40:37.98#ibcon#first serial, iclass 23, count 2 2006.258.01:40:37.98#ibcon#enter sib2, iclass 23, count 2 2006.258.01:40:37.98#ibcon#flushed, iclass 23, count 2 2006.258.01:40:37.98#ibcon#about to write, iclass 23, count 2 2006.258.01:40:37.98#ibcon#wrote, iclass 23, count 2 2006.258.01:40:37.98#ibcon#about to read 3, iclass 23, count 2 2006.258.01:40:38.00#ibcon#read 3, iclass 23, count 2 2006.258.01:40:38.00#ibcon#about to read 4, iclass 23, count 2 2006.258.01:40:38.00#ibcon#read 4, iclass 23, count 2 2006.258.01:40:38.00#ibcon#about to read 5, iclass 23, count 2 2006.258.01:40:38.00#ibcon#read 5, iclass 23, count 2 2006.258.01:40:38.00#ibcon#about to read 6, iclass 23, count 2 2006.258.01:40:38.00#ibcon#read 6, iclass 23, count 2 2006.258.01:40:38.00#ibcon#end of sib2, iclass 23, count 2 2006.258.01:40:38.00#ibcon#*mode == 0, iclass 23, count 2 2006.258.01:40:38.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.258.01:40:38.00#ibcon#[27=AT01-04\r\n] 2006.258.01:40:38.00#ibcon#*before write, iclass 23, count 2 2006.258.01:40:38.00#ibcon#enter sib2, iclass 23, count 2 2006.258.01:40:38.00#ibcon#flushed, iclass 23, count 2 2006.258.01:40:38.00#ibcon#about to write, iclass 23, count 2 2006.258.01:40:38.00#ibcon#wrote, iclass 23, count 2 2006.258.01:40:38.00#ibcon#about to read 3, iclass 23, count 2 2006.258.01:40:38.03#ibcon#read 3, iclass 23, count 2 2006.258.01:40:38.03#ibcon#about to read 4, iclass 23, count 2 2006.258.01:40:38.03#ibcon#read 4, iclass 23, count 2 2006.258.01:40:38.03#ibcon#about to read 5, iclass 23, count 2 2006.258.01:40:38.03#ibcon#read 5, iclass 23, count 2 2006.258.01:40:38.03#ibcon#about to read 6, iclass 23, count 2 2006.258.01:40:38.03#ibcon#read 6, iclass 23, count 2 2006.258.01:40:38.03#ibcon#end of sib2, iclass 23, count 2 2006.258.01:40:38.03#ibcon#*after write, iclass 23, count 2 2006.258.01:40:38.03#ibcon#*before return 0, iclass 23, count 2 2006.258.01:40:38.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:40:38.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.258.01:40:38.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.258.01:40:38.03#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:38.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:40:38.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:40:38.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:40:38.15#ibcon#enter wrdev, iclass 23, count 0 2006.258.01:40:38.15#ibcon#first serial, iclass 23, count 0 2006.258.01:40:38.15#ibcon#enter sib2, iclass 23, count 0 2006.258.01:40:38.15#ibcon#flushed, iclass 23, count 0 2006.258.01:40:38.15#ibcon#about to write, iclass 23, count 0 2006.258.01:40:38.15#ibcon#wrote, iclass 23, count 0 2006.258.01:40:38.15#ibcon#about to read 3, iclass 23, count 0 2006.258.01:40:38.17#ibcon#read 3, iclass 23, count 0 2006.258.01:40:38.17#ibcon#about to read 4, iclass 23, count 0 2006.258.01:40:38.17#ibcon#read 4, iclass 23, count 0 2006.258.01:40:38.17#ibcon#about to read 5, iclass 23, count 0 2006.258.01:40:38.17#ibcon#read 5, iclass 23, count 0 2006.258.01:40:38.17#ibcon#about to read 6, iclass 23, count 0 2006.258.01:40:38.17#ibcon#read 6, iclass 23, count 0 2006.258.01:40:38.17#ibcon#end of sib2, iclass 23, count 0 2006.258.01:40:38.17#ibcon#*mode == 0, iclass 23, count 0 2006.258.01:40:38.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.01:40:38.17#ibcon#[27=USB\r\n] 2006.258.01:40:38.17#ibcon#*before write, iclass 23, count 0 2006.258.01:40:38.17#ibcon#enter sib2, iclass 23, count 0 2006.258.01:40:38.17#ibcon#flushed, iclass 23, count 0 2006.258.01:40:38.17#ibcon#about to write, iclass 23, count 0 2006.258.01:40:38.17#ibcon#wrote, iclass 23, count 0 2006.258.01:40:38.17#ibcon#about to read 3, iclass 23, count 0 2006.258.01:40:38.20#ibcon#read 3, iclass 23, count 0 2006.258.01:40:38.20#ibcon#about to read 4, iclass 23, count 0 2006.258.01:40:38.20#ibcon#read 4, iclass 23, count 0 2006.258.01:40:38.20#ibcon#about to read 5, iclass 23, count 0 2006.258.01:40:38.20#ibcon#read 5, iclass 23, count 0 2006.258.01:40:38.20#ibcon#about to read 6, iclass 23, count 0 2006.258.01:40:38.20#ibcon#read 6, iclass 23, count 0 2006.258.01:40:38.20#ibcon#end of sib2, iclass 23, count 0 2006.258.01:40:38.20#ibcon#*after write, iclass 23, count 0 2006.258.01:40:38.20#ibcon#*before return 0, iclass 23, count 0 2006.258.01:40:38.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:40:38.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.258.01:40:38.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.01:40:38.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.01:40:38.20$vck44/vblo=2,634.99 2006.258.01:40:38.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.258.01:40:38.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.258.01:40:38.20#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:38.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:38.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:38.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:38.20#ibcon#enter wrdev, iclass 25, count 0 2006.258.01:40:38.20#ibcon#first serial, iclass 25, count 0 2006.258.01:40:38.20#ibcon#enter sib2, iclass 25, count 0 2006.258.01:40:38.20#ibcon#flushed, iclass 25, count 0 2006.258.01:40:38.20#ibcon#about to write, iclass 25, count 0 2006.258.01:40:38.20#ibcon#wrote, iclass 25, count 0 2006.258.01:40:38.20#ibcon#about to read 3, iclass 25, count 0 2006.258.01:40:38.22#ibcon#read 3, iclass 25, count 0 2006.258.01:40:38.22#ibcon#about to read 4, iclass 25, count 0 2006.258.01:40:38.22#ibcon#read 4, iclass 25, count 0 2006.258.01:40:38.22#ibcon#about to read 5, iclass 25, count 0 2006.258.01:40:38.22#ibcon#read 5, iclass 25, count 0 2006.258.01:40:38.22#ibcon#about to read 6, iclass 25, count 0 2006.258.01:40:38.22#ibcon#read 6, iclass 25, count 0 2006.258.01:40:38.22#ibcon#end of sib2, iclass 25, count 0 2006.258.01:40:38.22#ibcon#*mode == 0, iclass 25, count 0 2006.258.01:40:38.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.01:40:38.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.01:40:38.22#ibcon#*before write, iclass 25, count 0 2006.258.01:40:38.22#ibcon#enter sib2, iclass 25, count 0 2006.258.01:40:38.22#ibcon#flushed, iclass 25, count 0 2006.258.01:40:38.22#ibcon#about to write, iclass 25, count 0 2006.258.01:40:38.22#ibcon#wrote, iclass 25, count 0 2006.258.01:40:38.22#ibcon#about to read 3, iclass 25, count 0 2006.258.01:40:38.26#ibcon#read 3, iclass 25, count 0 2006.258.01:40:38.26#ibcon#about to read 4, iclass 25, count 0 2006.258.01:40:38.26#ibcon#read 4, iclass 25, count 0 2006.258.01:40:38.26#ibcon#about to read 5, iclass 25, count 0 2006.258.01:40:38.26#ibcon#read 5, iclass 25, count 0 2006.258.01:40:38.26#ibcon#about to read 6, iclass 25, count 0 2006.258.01:40:38.26#ibcon#read 6, iclass 25, count 0 2006.258.01:40:38.26#ibcon#end of sib2, iclass 25, count 0 2006.258.01:40:38.26#ibcon#*after write, iclass 25, count 0 2006.258.01:40:38.26#ibcon#*before return 0, iclass 25, count 0 2006.258.01:40:38.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:38.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.258.01:40:38.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.01:40:38.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.01:40:38.26$vck44/vb=2,5 2006.258.01:40:38.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.258.01:40:38.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.258.01:40:38.26#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:38.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:38.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:38.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:38.32#ibcon#enter wrdev, iclass 27, count 2 2006.258.01:40:38.32#ibcon#first serial, iclass 27, count 2 2006.258.01:40:38.32#ibcon#enter sib2, iclass 27, count 2 2006.258.01:40:38.32#ibcon#flushed, iclass 27, count 2 2006.258.01:40:38.32#ibcon#about to write, iclass 27, count 2 2006.258.01:40:38.32#ibcon#wrote, iclass 27, count 2 2006.258.01:40:38.32#ibcon#about to read 3, iclass 27, count 2 2006.258.01:40:38.34#ibcon#read 3, iclass 27, count 2 2006.258.01:40:38.34#ibcon#about to read 4, iclass 27, count 2 2006.258.01:40:38.34#ibcon#read 4, iclass 27, count 2 2006.258.01:40:38.34#ibcon#about to read 5, iclass 27, count 2 2006.258.01:40:38.34#ibcon#read 5, iclass 27, count 2 2006.258.01:40:38.34#ibcon#about to read 6, iclass 27, count 2 2006.258.01:40:38.34#ibcon#read 6, iclass 27, count 2 2006.258.01:40:38.34#ibcon#end of sib2, iclass 27, count 2 2006.258.01:40:38.34#ibcon#*mode == 0, iclass 27, count 2 2006.258.01:40:38.34#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.258.01:40:38.34#ibcon#[27=AT02-05\r\n] 2006.258.01:40:38.34#ibcon#*before write, iclass 27, count 2 2006.258.01:40:38.34#ibcon#enter sib2, iclass 27, count 2 2006.258.01:40:38.34#ibcon#flushed, iclass 27, count 2 2006.258.01:40:38.34#ibcon#about to write, iclass 27, count 2 2006.258.01:40:38.34#ibcon#wrote, iclass 27, count 2 2006.258.01:40:38.34#ibcon#about to read 3, iclass 27, count 2 2006.258.01:40:38.37#ibcon#read 3, iclass 27, count 2 2006.258.01:40:38.37#ibcon#about to read 4, iclass 27, count 2 2006.258.01:40:38.37#ibcon#read 4, iclass 27, count 2 2006.258.01:40:38.37#ibcon#about to read 5, iclass 27, count 2 2006.258.01:40:38.37#ibcon#read 5, iclass 27, count 2 2006.258.01:40:38.37#ibcon#about to read 6, iclass 27, count 2 2006.258.01:40:38.37#ibcon#read 6, iclass 27, count 2 2006.258.01:40:38.37#ibcon#end of sib2, iclass 27, count 2 2006.258.01:40:38.37#ibcon#*after write, iclass 27, count 2 2006.258.01:40:38.37#ibcon#*before return 0, iclass 27, count 2 2006.258.01:40:38.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:38.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.258.01:40:38.37#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.258.01:40:38.37#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:38.37#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:38.49#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:38.49#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:38.49#ibcon#enter wrdev, iclass 27, count 0 2006.258.01:40:38.49#ibcon#first serial, iclass 27, count 0 2006.258.01:40:38.49#ibcon#enter sib2, iclass 27, count 0 2006.258.01:40:38.49#ibcon#flushed, iclass 27, count 0 2006.258.01:40:38.49#ibcon#about to write, iclass 27, count 0 2006.258.01:40:38.49#ibcon#wrote, iclass 27, count 0 2006.258.01:40:38.49#ibcon#about to read 3, iclass 27, count 0 2006.258.01:40:38.51#ibcon#read 3, iclass 27, count 0 2006.258.01:40:38.51#ibcon#about to read 4, iclass 27, count 0 2006.258.01:40:38.51#ibcon#read 4, iclass 27, count 0 2006.258.01:40:38.51#ibcon#about to read 5, iclass 27, count 0 2006.258.01:40:38.51#ibcon#read 5, iclass 27, count 0 2006.258.01:40:38.51#ibcon#about to read 6, iclass 27, count 0 2006.258.01:40:38.51#ibcon#read 6, iclass 27, count 0 2006.258.01:40:38.51#ibcon#end of sib2, iclass 27, count 0 2006.258.01:40:38.51#ibcon#*mode == 0, iclass 27, count 0 2006.258.01:40:38.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.01:40:38.51#ibcon#[27=USB\r\n] 2006.258.01:40:38.51#ibcon#*before write, iclass 27, count 0 2006.258.01:40:38.51#ibcon#enter sib2, iclass 27, count 0 2006.258.01:40:38.51#ibcon#flushed, iclass 27, count 0 2006.258.01:40:38.51#ibcon#about to write, iclass 27, count 0 2006.258.01:40:38.51#ibcon#wrote, iclass 27, count 0 2006.258.01:40:38.51#ibcon#about to read 3, iclass 27, count 0 2006.258.01:40:38.54#ibcon#read 3, iclass 27, count 0 2006.258.01:40:38.54#ibcon#about to read 4, iclass 27, count 0 2006.258.01:40:38.54#ibcon#read 4, iclass 27, count 0 2006.258.01:40:38.54#ibcon#about to read 5, iclass 27, count 0 2006.258.01:40:38.54#ibcon#read 5, iclass 27, count 0 2006.258.01:40:38.54#ibcon#about to read 6, iclass 27, count 0 2006.258.01:40:38.54#ibcon#read 6, iclass 27, count 0 2006.258.01:40:38.54#ibcon#end of sib2, iclass 27, count 0 2006.258.01:40:38.54#ibcon#*after write, iclass 27, count 0 2006.258.01:40:38.54#ibcon#*before return 0, iclass 27, count 0 2006.258.01:40:38.54#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:38.54#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.258.01:40:38.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.01:40:38.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.01:40:38.54$vck44/vblo=3,649.99 2006.258.01:40:38.54#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.258.01:40:38.54#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.258.01:40:38.54#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:38.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:38.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:38.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:38.54#ibcon#enter wrdev, iclass 29, count 0 2006.258.01:40:38.54#ibcon#first serial, iclass 29, count 0 2006.258.01:40:38.54#ibcon#enter sib2, iclass 29, count 0 2006.258.01:40:38.54#ibcon#flushed, iclass 29, count 0 2006.258.01:40:38.54#ibcon#about to write, iclass 29, count 0 2006.258.01:40:38.54#ibcon#wrote, iclass 29, count 0 2006.258.01:40:38.54#ibcon#about to read 3, iclass 29, count 0 2006.258.01:40:38.56#ibcon#read 3, iclass 29, count 0 2006.258.01:40:38.56#ibcon#about to read 4, iclass 29, count 0 2006.258.01:40:38.56#ibcon#read 4, iclass 29, count 0 2006.258.01:40:38.56#ibcon#about to read 5, iclass 29, count 0 2006.258.01:40:38.56#ibcon#read 5, iclass 29, count 0 2006.258.01:40:38.56#ibcon#about to read 6, iclass 29, count 0 2006.258.01:40:38.56#ibcon#read 6, iclass 29, count 0 2006.258.01:40:38.56#ibcon#end of sib2, iclass 29, count 0 2006.258.01:40:38.56#ibcon#*mode == 0, iclass 29, count 0 2006.258.01:40:38.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.01:40:38.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.01:40:38.56#ibcon#*before write, iclass 29, count 0 2006.258.01:40:38.56#ibcon#enter sib2, iclass 29, count 0 2006.258.01:40:38.56#ibcon#flushed, iclass 29, count 0 2006.258.01:40:38.56#ibcon#about to write, iclass 29, count 0 2006.258.01:40:38.56#ibcon#wrote, iclass 29, count 0 2006.258.01:40:38.56#ibcon#about to read 3, iclass 29, count 0 2006.258.01:40:38.60#ibcon#read 3, iclass 29, count 0 2006.258.01:40:38.60#ibcon#about to read 4, iclass 29, count 0 2006.258.01:40:38.60#ibcon#read 4, iclass 29, count 0 2006.258.01:40:38.60#ibcon#about to read 5, iclass 29, count 0 2006.258.01:40:38.60#ibcon#read 5, iclass 29, count 0 2006.258.01:40:38.60#ibcon#about to read 6, iclass 29, count 0 2006.258.01:40:38.60#ibcon#read 6, iclass 29, count 0 2006.258.01:40:38.60#ibcon#end of sib2, iclass 29, count 0 2006.258.01:40:38.60#ibcon#*after write, iclass 29, count 0 2006.258.01:40:38.60#ibcon#*before return 0, iclass 29, count 0 2006.258.01:40:38.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:38.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.258.01:40:38.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.01:40:38.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.01:40:38.60$vck44/vb=3,4 2006.258.01:40:38.60#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.258.01:40:38.60#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.258.01:40:38.60#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:38.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:38.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:38.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:38.66#ibcon#enter wrdev, iclass 31, count 2 2006.258.01:40:38.66#ibcon#first serial, iclass 31, count 2 2006.258.01:40:38.66#ibcon#enter sib2, iclass 31, count 2 2006.258.01:40:38.66#ibcon#flushed, iclass 31, count 2 2006.258.01:40:38.66#ibcon#about to write, iclass 31, count 2 2006.258.01:40:38.66#ibcon#wrote, iclass 31, count 2 2006.258.01:40:38.66#ibcon#about to read 3, iclass 31, count 2 2006.258.01:40:38.68#ibcon#read 3, iclass 31, count 2 2006.258.01:40:38.68#ibcon#about to read 4, iclass 31, count 2 2006.258.01:40:38.68#ibcon#read 4, iclass 31, count 2 2006.258.01:40:38.68#ibcon#about to read 5, iclass 31, count 2 2006.258.01:40:38.68#ibcon#read 5, iclass 31, count 2 2006.258.01:40:38.68#ibcon#about to read 6, iclass 31, count 2 2006.258.01:40:38.68#ibcon#read 6, iclass 31, count 2 2006.258.01:40:38.68#ibcon#end of sib2, iclass 31, count 2 2006.258.01:40:38.68#ibcon#*mode == 0, iclass 31, count 2 2006.258.01:40:38.68#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.258.01:40:38.68#ibcon#[27=AT03-04\r\n] 2006.258.01:40:38.68#ibcon#*before write, iclass 31, count 2 2006.258.01:40:38.68#ibcon#enter sib2, iclass 31, count 2 2006.258.01:40:38.68#ibcon#flushed, iclass 31, count 2 2006.258.01:40:38.68#ibcon#about to write, iclass 31, count 2 2006.258.01:40:38.68#ibcon#wrote, iclass 31, count 2 2006.258.01:40:38.68#ibcon#about to read 3, iclass 31, count 2 2006.258.01:40:38.71#ibcon#read 3, iclass 31, count 2 2006.258.01:40:38.71#ibcon#about to read 4, iclass 31, count 2 2006.258.01:40:38.71#ibcon#read 4, iclass 31, count 2 2006.258.01:40:38.71#ibcon#about to read 5, iclass 31, count 2 2006.258.01:40:38.71#ibcon#read 5, iclass 31, count 2 2006.258.01:40:38.71#ibcon#about to read 6, iclass 31, count 2 2006.258.01:40:38.71#ibcon#read 6, iclass 31, count 2 2006.258.01:40:38.71#ibcon#end of sib2, iclass 31, count 2 2006.258.01:40:38.71#ibcon#*after write, iclass 31, count 2 2006.258.01:40:38.71#ibcon#*before return 0, iclass 31, count 2 2006.258.01:40:38.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:38.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.258.01:40:38.71#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.258.01:40:38.71#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:38.71#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:38.83#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:38.83#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:38.83#ibcon#enter wrdev, iclass 31, count 0 2006.258.01:40:38.83#ibcon#first serial, iclass 31, count 0 2006.258.01:40:38.83#ibcon#enter sib2, iclass 31, count 0 2006.258.01:40:38.83#ibcon#flushed, iclass 31, count 0 2006.258.01:40:38.83#ibcon#about to write, iclass 31, count 0 2006.258.01:40:38.83#ibcon#wrote, iclass 31, count 0 2006.258.01:40:38.83#ibcon#about to read 3, iclass 31, count 0 2006.258.01:40:38.85#ibcon#read 3, iclass 31, count 0 2006.258.01:40:38.85#ibcon#about to read 4, iclass 31, count 0 2006.258.01:40:38.85#ibcon#read 4, iclass 31, count 0 2006.258.01:40:38.85#ibcon#about to read 5, iclass 31, count 0 2006.258.01:40:38.85#ibcon#read 5, iclass 31, count 0 2006.258.01:40:38.85#ibcon#about to read 6, iclass 31, count 0 2006.258.01:40:38.85#ibcon#read 6, iclass 31, count 0 2006.258.01:40:38.85#ibcon#end of sib2, iclass 31, count 0 2006.258.01:40:38.85#ibcon#*mode == 0, iclass 31, count 0 2006.258.01:40:38.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.01:40:38.85#ibcon#[27=USB\r\n] 2006.258.01:40:38.85#ibcon#*before write, iclass 31, count 0 2006.258.01:40:38.85#ibcon#enter sib2, iclass 31, count 0 2006.258.01:40:38.85#ibcon#flushed, iclass 31, count 0 2006.258.01:40:38.85#ibcon#about to write, iclass 31, count 0 2006.258.01:40:38.85#ibcon#wrote, iclass 31, count 0 2006.258.01:40:38.85#ibcon#about to read 3, iclass 31, count 0 2006.258.01:40:38.88#ibcon#read 3, iclass 31, count 0 2006.258.01:40:38.88#ibcon#about to read 4, iclass 31, count 0 2006.258.01:40:38.88#ibcon#read 4, iclass 31, count 0 2006.258.01:40:38.88#ibcon#about to read 5, iclass 31, count 0 2006.258.01:40:38.88#ibcon#read 5, iclass 31, count 0 2006.258.01:40:38.88#ibcon#about to read 6, iclass 31, count 0 2006.258.01:40:38.88#ibcon#read 6, iclass 31, count 0 2006.258.01:40:38.88#ibcon#end of sib2, iclass 31, count 0 2006.258.01:40:38.88#ibcon#*after write, iclass 31, count 0 2006.258.01:40:38.88#ibcon#*before return 0, iclass 31, count 0 2006.258.01:40:38.88#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:38.88#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.258.01:40:38.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.01:40:38.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.01:40:38.88$vck44/vblo=4,679.99 2006.258.01:40:38.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.258.01:40:38.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.258.01:40:38.88#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:38.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:38.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:38.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:38.88#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:40:38.88#ibcon#first serial, iclass 33, count 0 2006.258.01:40:38.88#ibcon#enter sib2, iclass 33, count 0 2006.258.01:40:38.88#ibcon#flushed, iclass 33, count 0 2006.258.01:40:38.88#ibcon#about to write, iclass 33, count 0 2006.258.01:40:38.88#ibcon#wrote, iclass 33, count 0 2006.258.01:40:38.88#ibcon#about to read 3, iclass 33, count 0 2006.258.01:40:38.90#ibcon#read 3, iclass 33, count 0 2006.258.01:40:38.90#ibcon#about to read 4, iclass 33, count 0 2006.258.01:40:38.90#ibcon#read 4, iclass 33, count 0 2006.258.01:40:38.90#ibcon#about to read 5, iclass 33, count 0 2006.258.01:40:38.90#ibcon#read 5, iclass 33, count 0 2006.258.01:40:38.90#ibcon#about to read 6, iclass 33, count 0 2006.258.01:40:38.90#ibcon#read 6, iclass 33, count 0 2006.258.01:40:38.90#ibcon#end of sib2, iclass 33, count 0 2006.258.01:40:38.90#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:40:38.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:40:38.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.01:40:38.90#ibcon#*before write, iclass 33, count 0 2006.258.01:40:38.90#ibcon#enter sib2, iclass 33, count 0 2006.258.01:40:38.90#ibcon#flushed, iclass 33, count 0 2006.258.01:40:38.90#ibcon#about to write, iclass 33, count 0 2006.258.01:40:38.90#ibcon#wrote, iclass 33, count 0 2006.258.01:40:38.90#ibcon#about to read 3, iclass 33, count 0 2006.258.01:40:38.94#ibcon#read 3, iclass 33, count 0 2006.258.01:40:38.94#ibcon#about to read 4, iclass 33, count 0 2006.258.01:40:38.94#ibcon#read 4, iclass 33, count 0 2006.258.01:40:38.94#ibcon#about to read 5, iclass 33, count 0 2006.258.01:40:38.94#ibcon#read 5, iclass 33, count 0 2006.258.01:40:38.94#ibcon#about to read 6, iclass 33, count 0 2006.258.01:40:38.94#ibcon#read 6, iclass 33, count 0 2006.258.01:40:38.94#ibcon#end of sib2, iclass 33, count 0 2006.258.01:40:38.94#ibcon#*after write, iclass 33, count 0 2006.258.01:40:38.94#ibcon#*before return 0, iclass 33, count 0 2006.258.01:40:38.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:38.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.258.01:40:38.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:40:38.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:40:38.94$vck44/vb=4,5 2006.258.01:40:38.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.258.01:40:38.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.258.01:40:38.94#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:38.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:39.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:39.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:39.00#ibcon#enter wrdev, iclass 35, count 2 2006.258.01:40:39.00#ibcon#first serial, iclass 35, count 2 2006.258.01:40:39.00#ibcon#enter sib2, iclass 35, count 2 2006.258.01:40:39.00#ibcon#flushed, iclass 35, count 2 2006.258.01:40:39.00#ibcon#about to write, iclass 35, count 2 2006.258.01:40:39.00#ibcon#wrote, iclass 35, count 2 2006.258.01:40:39.00#ibcon#about to read 3, iclass 35, count 2 2006.258.01:40:39.02#ibcon#read 3, iclass 35, count 2 2006.258.01:40:39.02#ibcon#about to read 4, iclass 35, count 2 2006.258.01:40:39.02#ibcon#read 4, iclass 35, count 2 2006.258.01:40:39.02#ibcon#about to read 5, iclass 35, count 2 2006.258.01:40:39.02#ibcon#read 5, iclass 35, count 2 2006.258.01:40:39.02#ibcon#about to read 6, iclass 35, count 2 2006.258.01:40:39.02#ibcon#read 6, iclass 35, count 2 2006.258.01:40:39.02#ibcon#end of sib2, iclass 35, count 2 2006.258.01:40:39.02#ibcon#*mode == 0, iclass 35, count 2 2006.258.01:40:39.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.258.01:40:39.02#ibcon#[27=AT04-05\r\n] 2006.258.01:40:39.02#ibcon#*before write, iclass 35, count 2 2006.258.01:40:39.02#ibcon#enter sib2, iclass 35, count 2 2006.258.01:40:39.02#ibcon#flushed, iclass 35, count 2 2006.258.01:40:39.02#ibcon#about to write, iclass 35, count 2 2006.258.01:40:39.02#ibcon#wrote, iclass 35, count 2 2006.258.01:40:39.02#ibcon#about to read 3, iclass 35, count 2 2006.258.01:40:39.05#ibcon#read 3, iclass 35, count 2 2006.258.01:40:39.05#ibcon#about to read 4, iclass 35, count 2 2006.258.01:40:39.05#ibcon#read 4, iclass 35, count 2 2006.258.01:40:39.05#ibcon#about to read 5, iclass 35, count 2 2006.258.01:40:39.05#ibcon#read 5, iclass 35, count 2 2006.258.01:40:39.05#ibcon#about to read 6, iclass 35, count 2 2006.258.01:40:39.05#ibcon#read 6, iclass 35, count 2 2006.258.01:40:39.05#ibcon#end of sib2, iclass 35, count 2 2006.258.01:40:39.05#ibcon#*after write, iclass 35, count 2 2006.258.01:40:39.05#ibcon#*before return 0, iclass 35, count 2 2006.258.01:40:39.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:39.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.258.01:40:39.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.258.01:40:39.05#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:39.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:39.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:39.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:39.17#ibcon#enter wrdev, iclass 35, count 0 2006.258.01:40:39.17#ibcon#first serial, iclass 35, count 0 2006.258.01:40:39.17#ibcon#enter sib2, iclass 35, count 0 2006.258.01:40:39.17#ibcon#flushed, iclass 35, count 0 2006.258.01:40:39.17#ibcon#about to write, iclass 35, count 0 2006.258.01:40:39.17#ibcon#wrote, iclass 35, count 0 2006.258.01:40:39.17#ibcon#about to read 3, iclass 35, count 0 2006.258.01:40:39.19#ibcon#read 3, iclass 35, count 0 2006.258.01:40:39.19#ibcon#about to read 4, iclass 35, count 0 2006.258.01:40:39.19#ibcon#read 4, iclass 35, count 0 2006.258.01:40:39.19#ibcon#about to read 5, iclass 35, count 0 2006.258.01:40:39.19#ibcon#read 5, iclass 35, count 0 2006.258.01:40:39.19#ibcon#about to read 6, iclass 35, count 0 2006.258.01:40:39.19#ibcon#read 6, iclass 35, count 0 2006.258.01:40:39.19#ibcon#end of sib2, iclass 35, count 0 2006.258.01:40:39.19#ibcon#*mode == 0, iclass 35, count 0 2006.258.01:40:39.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.01:40:39.19#ibcon#[27=USB\r\n] 2006.258.01:40:39.19#ibcon#*before write, iclass 35, count 0 2006.258.01:40:39.19#ibcon#enter sib2, iclass 35, count 0 2006.258.01:40:39.19#ibcon#flushed, iclass 35, count 0 2006.258.01:40:39.19#ibcon#about to write, iclass 35, count 0 2006.258.01:40:39.19#ibcon#wrote, iclass 35, count 0 2006.258.01:40:39.19#ibcon#about to read 3, iclass 35, count 0 2006.258.01:40:39.22#ibcon#read 3, iclass 35, count 0 2006.258.01:40:39.22#ibcon#about to read 4, iclass 35, count 0 2006.258.01:40:39.22#ibcon#read 4, iclass 35, count 0 2006.258.01:40:39.22#ibcon#about to read 5, iclass 35, count 0 2006.258.01:40:39.22#ibcon#read 5, iclass 35, count 0 2006.258.01:40:39.22#ibcon#about to read 6, iclass 35, count 0 2006.258.01:40:39.22#ibcon#read 6, iclass 35, count 0 2006.258.01:40:39.22#ibcon#end of sib2, iclass 35, count 0 2006.258.01:40:39.22#ibcon#*after write, iclass 35, count 0 2006.258.01:40:39.22#ibcon#*before return 0, iclass 35, count 0 2006.258.01:40:39.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:39.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.258.01:40:39.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.01:40:39.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.01:40:39.22$vck44/vblo=5,709.99 2006.258.01:40:39.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.258.01:40:39.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.258.01:40:39.22#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:39.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:39.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:39.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:39.22#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:40:39.22#ibcon#first serial, iclass 37, count 0 2006.258.01:40:39.22#ibcon#enter sib2, iclass 37, count 0 2006.258.01:40:39.22#ibcon#flushed, iclass 37, count 0 2006.258.01:40:39.22#ibcon#about to write, iclass 37, count 0 2006.258.01:40:39.22#ibcon#wrote, iclass 37, count 0 2006.258.01:40:39.22#ibcon#about to read 3, iclass 37, count 0 2006.258.01:40:39.24#ibcon#read 3, iclass 37, count 0 2006.258.01:40:39.24#ibcon#about to read 4, iclass 37, count 0 2006.258.01:40:39.24#ibcon#read 4, iclass 37, count 0 2006.258.01:40:39.24#ibcon#about to read 5, iclass 37, count 0 2006.258.01:40:39.24#ibcon#read 5, iclass 37, count 0 2006.258.01:40:39.24#ibcon#about to read 6, iclass 37, count 0 2006.258.01:40:39.24#ibcon#read 6, iclass 37, count 0 2006.258.01:40:39.24#ibcon#end of sib2, iclass 37, count 0 2006.258.01:40:39.24#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:40:39.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:40:39.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.01:40:39.24#ibcon#*before write, iclass 37, count 0 2006.258.01:40:39.24#ibcon#enter sib2, iclass 37, count 0 2006.258.01:40:39.24#ibcon#flushed, iclass 37, count 0 2006.258.01:40:39.24#ibcon#about to write, iclass 37, count 0 2006.258.01:40:39.24#ibcon#wrote, iclass 37, count 0 2006.258.01:40:39.24#ibcon#about to read 3, iclass 37, count 0 2006.258.01:40:39.28#ibcon#read 3, iclass 37, count 0 2006.258.01:40:39.28#ibcon#about to read 4, iclass 37, count 0 2006.258.01:40:39.28#ibcon#read 4, iclass 37, count 0 2006.258.01:40:39.28#ibcon#about to read 5, iclass 37, count 0 2006.258.01:40:39.28#ibcon#read 5, iclass 37, count 0 2006.258.01:40:39.28#ibcon#about to read 6, iclass 37, count 0 2006.258.01:40:39.28#ibcon#read 6, iclass 37, count 0 2006.258.01:40:39.28#ibcon#end of sib2, iclass 37, count 0 2006.258.01:40:39.28#ibcon#*after write, iclass 37, count 0 2006.258.01:40:39.28#ibcon#*before return 0, iclass 37, count 0 2006.258.01:40:39.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:39.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.258.01:40:39.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:40:39.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:40:39.28$vck44/vb=5,4 2006.258.01:40:39.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.258.01:40:39.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.258.01:40:39.28#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:39.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:39.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:39.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:39.34#ibcon#enter wrdev, iclass 39, count 2 2006.258.01:40:39.34#ibcon#first serial, iclass 39, count 2 2006.258.01:40:39.34#ibcon#enter sib2, iclass 39, count 2 2006.258.01:40:39.34#ibcon#flushed, iclass 39, count 2 2006.258.01:40:39.34#ibcon#about to write, iclass 39, count 2 2006.258.01:40:39.34#ibcon#wrote, iclass 39, count 2 2006.258.01:40:39.34#ibcon#about to read 3, iclass 39, count 2 2006.258.01:40:39.36#ibcon#read 3, iclass 39, count 2 2006.258.01:40:39.36#ibcon#about to read 4, iclass 39, count 2 2006.258.01:40:39.36#ibcon#read 4, iclass 39, count 2 2006.258.01:40:39.36#ibcon#about to read 5, iclass 39, count 2 2006.258.01:40:39.36#ibcon#read 5, iclass 39, count 2 2006.258.01:40:39.36#ibcon#about to read 6, iclass 39, count 2 2006.258.01:40:39.36#ibcon#read 6, iclass 39, count 2 2006.258.01:40:39.36#ibcon#end of sib2, iclass 39, count 2 2006.258.01:40:39.36#ibcon#*mode == 0, iclass 39, count 2 2006.258.01:40:39.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.258.01:40:39.36#ibcon#[27=AT05-04\r\n] 2006.258.01:40:39.36#ibcon#*before write, iclass 39, count 2 2006.258.01:40:39.36#ibcon#enter sib2, iclass 39, count 2 2006.258.01:40:39.36#ibcon#flushed, iclass 39, count 2 2006.258.01:40:39.36#ibcon#about to write, iclass 39, count 2 2006.258.01:40:39.36#ibcon#wrote, iclass 39, count 2 2006.258.01:40:39.36#ibcon#about to read 3, iclass 39, count 2 2006.258.01:40:39.39#ibcon#read 3, iclass 39, count 2 2006.258.01:40:39.39#ibcon#about to read 4, iclass 39, count 2 2006.258.01:40:39.39#ibcon#read 4, iclass 39, count 2 2006.258.01:40:39.39#ibcon#about to read 5, iclass 39, count 2 2006.258.01:40:39.39#ibcon#read 5, iclass 39, count 2 2006.258.01:40:39.39#ibcon#about to read 6, iclass 39, count 2 2006.258.01:40:39.39#ibcon#read 6, iclass 39, count 2 2006.258.01:40:39.39#ibcon#end of sib2, iclass 39, count 2 2006.258.01:40:39.39#ibcon#*after write, iclass 39, count 2 2006.258.01:40:39.39#ibcon#*before return 0, iclass 39, count 2 2006.258.01:40:39.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:39.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.258.01:40:39.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.258.01:40:39.39#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:39.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:39.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:39.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:39.51#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:40:39.51#ibcon#first serial, iclass 39, count 0 2006.258.01:40:39.51#ibcon#enter sib2, iclass 39, count 0 2006.258.01:40:39.51#ibcon#flushed, iclass 39, count 0 2006.258.01:40:39.51#ibcon#about to write, iclass 39, count 0 2006.258.01:40:39.51#ibcon#wrote, iclass 39, count 0 2006.258.01:40:39.51#ibcon#about to read 3, iclass 39, count 0 2006.258.01:40:39.53#ibcon#read 3, iclass 39, count 0 2006.258.01:40:39.53#ibcon#about to read 4, iclass 39, count 0 2006.258.01:40:39.53#ibcon#read 4, iclass 39, count 0 2006.258.01:40:39.53#ibcon#about to read 5, iclass 39, count 0 2006.258.01:40:39.53#ibcon#read 5, iclass 39, count 0 2006.258.01:40:39.53#ibcon#about to read 6, iclass 39, count 0 2006.258.01:40:39.53#ibcon#read 6, iclass 39, count 0 2006.258.01:40:39.53#ibcon#end of sib2, iclass 39, count 0 2006.258.01:40:39.53#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:40:39.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:40:39.53#ibcon#[27=USB\r\n] 2006.258.01:40:39.53#ibcon#*before write, iclass 39, count 0 2006.258.01:40:39.53#ibcon#enter sib2, iclass 39, count 0 2006.258.01:40:39.53#ibcon#flushed, iclass 39, count 0 2006.258.01:40:39.53#ibcon#about to write, iclass 39, count 0 2006.258.01:40:39.53#ibcon#wrote, iclass 39, count 0 2006.258.01:40:39.53#ibcon#about to read 3, iclass 39, count 0 2006.258.01:40:39.56#ibcon#read 3, iclass 39, count 0 2006.258.01:40:39.56#ibcon#about to read 4, iclass 39, count 0 2006.258.01:40:39.56#ibcon#read 4, iclass 39, count 0 2006.258.01:40:39.56#ibcon#about to read 5, iclass 39, count 0 2006.258.01:40:39.56#ibcon#read 5, iclass 39, count 0 2006.258.01:40:39.56#ibcon#about to read 6, iclass 39, count 0 2006.258.01:40:39.56#ibcon#read 6, iclass 39, count 0 2006.258.01:40:39.56#ibcon#end of sib2, iclass 39, count 0 2006.258.01:40:39.56#ibcon#*after write, iclass 39, count 0 2006.258.01:40:39.56#ibcon#*before return 0, iclass 39, count 0 2006.258.01:40:39.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:39.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.258.01:40:39.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:40:39.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:40:39.56$vck44/vblo=6,719.99 2006.258.01:40:39.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.258.01:40:39.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.258.01:40:39.56#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:39.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:39.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:39.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:39.56#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:40:39.56#ibcon#first serial, iclass 3, count 0 2006.258.01:40:39.56#ibcon#enter sib2, iclass 3, count 0 2006.258.01:40:39.56#ibcon#flushed, iclass 3, count 0 2006.258.01:40:39.56#ibcon#about to write, iclass 3, count 0 2006.258.01:40:39.56#ibcon#wrote, iclass 3, count 0 2006.258.01:40:39.56#ibcon#about to read 3, iclass 3, count 0 2006.258.01:40:39.58#ibcon#read 3, iclass 3, count 0 2006.258.01:40:39.58#ibcon#about to read 4, iclass 3, count 0 2006.258.01:40:39.58#ibcon#read 4, iclass 3, count 0 2006.258.01:40:39.58#ibcon#about to read 5, iclass 3, count 0 2006.258.01:40:39.58#ibcon#read 5, iclass 3, count 0 2006.258.01:40:39.58#ibcon#about to read 6, iclass 3, count 0 2006.258.01:40:39.58#ibcon#read 6, iclass 3, count 0 2006.258.01:40:39.58#ibcon#end of sib2, iclass 3, count 0 2006.258.01:40:39.58#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:40:39.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:40:39.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.01:40:39.58#ibcon#*before write, iclass 3, count 0 2006.258.01:40:39.58#ibcon#enter sib2, iclass 3, count 0 2006.258.01:40:39.58#ibcon#flushed, iclass 3, count 0 2006.258.01:40:39.58#ibcon#about to write, iclass 3, count 0 2006.258.01:40:39.58#ibcon#wrote, iclass 3, count 0 2006.258.01:40:39.58#ibcon#about to read 3, iclass 3, count 0 2006.258.01:40:39.62#ibcon#read 3, iclass 3, count 0 2006.258.01:40:39.62#ibcon#about to read 4, iclass 3, count 0 2006.258.01:40:39.62#ibcon#read 4, iclass 3, count 0 2006.258.01:40:39.62#ibcon#about to read 5, iclass 3, count 0 2006.258.01:40:39.62#ibcon#read 5, iclass 3, count 0 2006.258.01:40:39.62#ibcon#about to read 6, iclass 3, count 0 2006.258.01:40:39.62#ibcon#read 6, iclass 3, count 0 2006.258.01:40:39.62#ibcon#end of sib2, iclass 3, count 0 2006.258.01:40:39.62#ibcon#*after write, iclass 3, count 0 2006.258.01:40:39.62#ibcon#*before return 0, iclass 3, count 0 2006.258.01:40:39.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:39.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.258.01:40:39.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:40:39.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:40:39.62$vck44/vb=6,4 2006.258.01:40:39.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.258.01:40:39.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.258.01:40:39.62#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:39.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:39.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:39.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:39.68#ibcon#enter wrdev, iclass 5, count 2 2006.258.01:40:39.68#ibcon#first serial, iclass 5, count 2 2006.258.01:40:39.68#ibcon#enter sib2, iclass 5, count 2 2006.258.01:40:39.68#ibcon#flushed, iclass 5, count 2 2006.258.01:40:39.68#ibcon#about to write, iclass 5, count 2 2006.258.01:40:39.68#ibcon#wrote, iclass 5, count 2 2006.258.01:40:39.68#ibcon#about to read 3, iclass 5, count 2 2006.258.01:40:39.70#ibcon#read 3, iclass 5, count 2 2006.258.01:40:39.70#ibcon#about to read 4, iclass 5, count 2 2006.258.01:40:39.70#ibcon#read 4, iclass 5, count 2 2006.258.01:40:39.70#ibcon#about to read 5, iclass 5, count 2 2006.258.01:40:39.70#ibcon#read 5, iclass 5, count 2 2006.258.01:40:39.70#ibcon#about to read 6, iclass 5, count 2 2006.258.01:40:39.70#ibcon#read 6, iclass 5, count 2 2006.258.01:40:39.70#ibcon#end of sib2, iclass 5, count 2 2006.258.01:40:39.70#ibcon#*mode == 0, iclass 5, count 2 2006.258.01:40:39.70#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.258.01:40:39.70#ibcon#[27=AT06-04\r\n] 2006.258.01:40:39.70#ibcon#*before write, iclass 5, count 2 2006.258.01:40:39.70#ibcon#enter sib2, iclass 5, count 2 2006.258.01:40:39.70#ibcon#flushed, iclass 5, count 2 2006.258.01:40:39.70#ibcon#about to write, iclass 5, count 2 2006.258.01:40:39.70#ibcon#wrote, iclass 5, count 2 2006.258.01:40:39.70#ibcon#about to read 3, iclass 5, count 2 2006.258.01:40:39.73#ibcon#read 3, iclass 5, count 2 2006.258.01:40:39.73#ibcon#about to read 4, iclass 5, count 2 2006.258.01:40:39.73#ibcon#read 4, iclass 5, count 2 2006.258.01:40:39.73#ibcon#about to read 5, iclass 5, count 2 2006.258.01:40:39.73#ibcon#read 5, iclass 5, count 2 2006.258.01:40:39.73#ibcon#about to read 6, iclass 5, count 2 2006.258.01:40:39.73#ibcon#read 6, iclass 5, count 2 2006.258.01:40:39.73#ibcon#end of sib2, iclass 5, count 2 2006.258.01:40:39.73#ibcon#*after write, iclass 5, count 2 2006.258.01:40:39.73#ibcon#*before return 0, iclass 5, count 2 2006.258.01:40:39.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:39.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.258.01:40:39.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.258.01:40:39.73#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:39.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:39.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:39.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:39.85#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:40:39.85#ibcon#first serial, iclass 5, count 0 2006.258.01:40:39.85#ibcon#enter sib2, iclass 5, count 0 2006.258.01:40:39.85#ibcon#flushed, iclass 5, count 0 2006.258.01:40:39.85#ibcon#about to write, iclass 5, count 0 2006.258.01:40:39.85#ibcon#wrote, iclass 5, count 0 2006.258.01:40:39.85#ibcon#about to read 3, iclass 5, count 0 2006.258.01:40:39.87#ibcon#read 3, iclass 5, count 0 2006.258.01:40:39.87#ibcon#about to read 4, iclass 5, count 0 2006.258.01:40:39.87#ibcon#read 4, iclass 5, count 0 2006.258.01:40:39.87#ibcon#about to read 5, iclass 5, count 0 2006.258.01:40:39.87#ibcon#read 5, iclass 5, count 0 2006.258.01:40:39.87#ibcon#about to read 6, iclass 5, count 0 2006.258.01:40:39.87#ibcon#read 6, iclass 5, count 0 2006.258.01:40:39.87#ibcon#end of sib2, iclass 5, count 0 2006.258.01:40:39.87#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:40:39.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:40:39.87#ibcon#[27=USB\r\n] 2006.258.01:40:39.87#ibcon#*before write, iclass 5, count 0 2006.258.01:40:39.87#ibcon#enter sib2, iclass 5, count 0 2006.258.01:40:39.87#ibcon#flushed, iclass 5, count 0 2006.258.01:40:39.87#ibcon#about to write, iclass 5, count 0 2006.258.01:40:39.87#ibcon#wrote, iclass 5, count 0 2006.258.01:40:39.87#ibcon#about to read 3, iclass 5, count 0 2006.258.01:40:39.90#ibcon#read 3, iclass 5, count 0 2006.258.01:40:39.90#ibcon#about to read 4, iclass 5, count 0 2006.258.01:40:39.90#ibcon#read 4, iclass 5, count 0 2006.258.01:40:39.90#ibcon#about to read 5, iclass 5, count 0 2006.258.01:40:39.90#ibcon#read 5, iclass 5, count 0 2006.258.01:40:39.90#ibcon#about to read 6, iclass 5, count 0 2006.258.01:40:39.90#ibcon#read 6, iclass 5, count 0 2006.258.01:40:39.90#ibcon#end of sib2, iclass 5, count 0 2006.258.01:40:39.90#ibcon#*after write, iclass 5, count 0 2006.258.01:40:39.90#ibcon#*before return 0, iclass 5, count 0 2006.258.01:40:39.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:39.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.258.01:40:39.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:40:39.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:40:39.90$vck44/vblo=7,734.99 2006.258.01:40:39.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.01:40:39.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.01:40:39.90#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:39.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:39.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:39.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:39.90#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:40:39.90#ibcon#first serial, iclass 7, count 0 2006.258.01:40:39.90#ibcon#enter sib2, iclass 7, count 0 2006.258.01:40:39.90#ibcon#flushed, iclass 7, count 0 2006.258.01:40:39.90#ibcon#about to write, iclass 7, count 0 2006.258.01:40:39.90#ibcon#wrote, iclass 7, count 0 2006.258.01:40:39.90#ibcon#about to read 3, iclass 7, count 0 2006.258.01:40:39.92#ibcon#read 3, iclass 7, count 0 2006.258.01:40:39.92#ibcon#about to read 4, iclass 7, count 0 2006.258.01:40:39.92#ibcon#read 4, iclass 7, count 0 2006.258.01:40:39.92#ibcon#about to read 5, iclass 7, count 0 2006.258.01:40:39.92#ibcon#read 5, iclass 7, count 0 2006.258.01:40:39.92#ibcon#about to read 6, iclass 7, count 0 2006.258.01:40:39.92#ibcon#read 6, iclass 7, count 0 2006.258.01:40:39.92#ibcon#end of sib2, iclass 7, count 0 2006.258.01:40:39.92#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:40:39.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:40:39.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.01:40:39.92#ibcon#*before write, iclass 7, count 0 2006.258.01:40:39.92#ibcon#enter sib2, iclass 7, count 0 2006.258.01:40:39.92#ibcon#flushed, iclass 7, count 0 2006.258.01:40:39.92#ibcon#about to write, iclass 7, count 0 2006.258.01:40:39.92#ibcon#wrote, iclass 7, count 0 2006.258.01:40:39.92#ibcon#about to read 3, iclass 7, count 0 2006.258.01:40:39.96#ibcon#read 3, iclass 7, count 0 2006.258.01:40:39.96#ibcon#about to read 4, iclass 7, count 0 2006.258.01:40:39.96#ibcon#read 4, iclass 7, count 0 2006.258.01:40:39.96#ibcon#about to read 5, iclass 7, count 0 2006.258.01:40:39.96#ibcon#read 5, iclass 7, count 0 2006.258.01:40:39.96#ibcon#about to read 6, iclass 7, count 0 2006.258.01:40:39.96#ibcon#read 6, iclass 7, count 0 2006.258.01:40:39.96#ibcon#end of sib2, iclass 7, count 0 2006.258.01:40:39.96#ibcon#*after write, iclass 7, count 0 2006.258.01:40:39.96#ibcon#*before return 0, iclass 7, count 0 2006.258.01:40:39.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:39.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:40:39.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:40:39.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:40:39.96$vck44/vb=7,4 2006.258.01:40:39.96#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.258.01:40:39.96#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.258.01:40:39.96#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:39.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:40.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:40.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:40.02#ibcon#enter wrdev, iclass 11, count 2 2006.258.01:40:40.02#ibcon#first serial, iclass 11, count 2 2006.258.01:40:40.02#ibcon#enter sib2, iclass 11, count 2 2006.258.01:40:40.02#ibcon#flushed, iclass 11, count 2 2006.258.01:40:40.02#ibcon#about to write, iclass 11, count 2 2006.258.01:40:40.02#ibcon#wrote, iclass 11, count 2 2006.258.01:40:40.02#ibcon#about to read 3, iclass 11, count 2 2006.258.01:40:40.04#ibcon#read 3, iclass 11, count 2 2006.258.01:40:40.04#ibcon#about to read 4, iclass 11, count 2 2006.258.01:40:40.04#ibcon#read 4, iclass 11, count 2 2006.258.01:40:40.04#ibcon#about to read 5, iclass 11, count 2 2006.258.01:40:40.04#ibcon#read 5, iclass 11, count 2 2006.258.01:40:40.04#ibcon#about to read 6, iclass 11, count 2 2006.258.01:40:40.04#ibcon#read 6, iclass 11, count 2 2006.258.01:40:40.04#ibcon#end of sib2, iclass 11, count 2 2006.258.01:40:40.04#ibcon#*mode == 0, iclass 11, count 2 2006.258.01:40:40.04#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.258.01:40:40.04#ibcon#[27=AT07-04\r\n] 2006.258.01:40:40.04#ibcon#*before write, iclass 11, count 2 2006.258.01:40:40.04#ibcon#enter sib2, iclass 11, count 2 2006.258.01:40:40.04#ibcon#flushed, iclass 11, count 2 2006.258.01:40:40.04#ibcon#about to write, iclass 11, count 2 2006.258.01:40:40.04#ibcon#wrote, iclass 11, count 2 2006.258.01:40:40.04#ibcon#about to read 3, iclass 11, count 2 2006.258.01:40:40.07#ibcon#read 3, iclass 11, count 2 2006.258.01:40:40.07#ibcon#about to read 4, iclass 11, count 2 2006.258.01:40:40.07#ibcon#read 4, iclass 11, count 2 2006.258.01:40:40.07#ibcon#about to read 5, iclass 11, count 2 2006.258.01:40:40.07#ibcon#read 5, iclass 11, count 2 2006.258.01:40:40.07#ibcon#about to read 6, iclass 11, count 2 2006.258.01:40:40.07#ibcon#read 6, iclass 11, count 2 2006.258.01:40:40.07#ibcon#end of sib2, iclass 11, count 2 2006.258.01:40:40.07#ibcon#*after write, iclass 11, count 2 2006.258.01:40:40.07#ibcon#*before return 0, iclass 11, count 2 2006.258.01:40:40.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:40.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.258.01:40:40.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.258.01:40:40.07#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:40.07#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:40.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:40.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:40.19#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:40:40.19#ibcon#first serial, iclass 11, count 0 2006.258.01:40:40.19#ibcon#enter sib2, iclass 11, count 0 2006.258.01:40:40.19#ibcon#flushed, iclass 11, count 0 2006.258.01:40:40.19#ibcon#about to write, iclass 11, count 0 2006.258.01:40:40.19#ibcon#wrote, iclass 11, count 0 2006.258.01:40:40.19#ibcon#about to read 3, iclass 11, count 0 2006.258.01:40:40.21#ibcon#read 3, iclass 11, count 0 2006.258.01:40:40.21#ibcon#about to read 4, iclass 11, count 0 2006.258.01:40:40.21#ibcon#read 4, iclass 11, count 0 2006.258.01:40:40.21#ibcon#about to read 5, iclass 11, count 0 2006.258.01:40:40.21#ibcon#read 5, iclass 11, count 0 2006.258.01:40:40.21#ibcon#about to read 6, iclass 11, count 0 2006.258.01:40:40.21#ibcon#read 6, iclass 11, count 0 2006.258.01:40:40.21#ibcon#end of sib2, iclass 11, count 0 2006.258.01:40:40.21#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:40:40.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:40:40.21#ibcon#[27=USB\r\n] 2006.258.01:40:40.21#ibcon#*before write, iclass 11, count 0 2006.258.01:40:40.21#ibcon#enter sib2, iclass 11, count 0 2006.258.01:40:40.21#ibcon#flushed, iclass 11, count 0 2006.258.01:40:40.21#ibcon#about to write, iclass 11, count 0 2006.258.01:40:40.21#ibcon#wrote, iclass 11, count 0 2006.258.01:40:40.21#ibcon#about to read 3, iclass 11, count 0 2006.258.01:40:40.24#ibcon#read 3, iclass 11, count 0 2006.258.01:40:40.24#ibcon#about to read 4, iclass 11, count 0 2006.258.01:40:40.24#ibcon#read 4, iclass 11, count 0 2006.258.01:40:40.24#ibcon#about to read 5, iclass 11, count 0 2006.258.01:40:40.24#ibcon#read 5, iclass 11, count 0 2006.258.01:40:40.24#ibcon#about to read 6, iclass 11, count 0 2006.258.01:40:40.24#ibcon#read 6, iclass 11, count 0 2006.258.01:40:40.24#ibcon#end of sib2, iclass 11, count 0 2006.258.01:40:40.24#ibcon#*after write, iclass 11, count 0 2006.258.01:40:40.24#ibcon#*before return 0, iclass 11, count 0 2006.258.01:40:40.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:40.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.258.01:40:40.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:40:40.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:40:40.24$vck44/vblo=8,744.99 2006.258.01:40:40.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.258.01:40:40.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.258.01:40:40.24#ibcon#ireg 17 cls_cnt 0 2006.258.01:40:40.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:40.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:40.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:40.24#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:40:40.24#ibcon#first serial, iclass 13, count 0 2006.258.01:40:40.24#ibcon#enter sib2, iclass 13, count 0 2006.258.01:40:40.24#ibcon#flushed, iclass 13, count 0 2006.258.01:40:40.24#ibcon#about to write, iclass 13, count 0 2006.258.01:40:40.24#ibcon#wrote, iclass 13, count 0 2006.258.01:40:40.24#ibcon#about to read 3, iclass 13, count 0 2006.258.01:40:40.26#ibcon#read 3, iclass 13, count 0 2006.258.01:40:40.26#ibcon#about to read 4, iclass 13, count 0 2006.258.01:40:40.26#ibcon#read 4, iclass 13, count 0 2006.258.01:40:40.26#ibcon#about to read 5, iclass 13, count 0 2006.258.01:40:40.26#ibcon#read 5, iclass 13, count 0 2006.258.01:40:40.26#ibcon#about to read 6, iclass 13, count 0 2006.258.01:40:40.26#ibcon#read 6, iclass 13, count 0 2006.258.01:40:40.26#ibcon#end of sib2, iclass 13, count 0 2006.258.01:40:40.26#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:40:40.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:40:40.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.01:40:40.26#ibcon#*before write, iclass 13, count 0 2006.258.01:40:40.26#ibcon#enter sib2, iclass 13, count 0 2006.258.01:40:40.26#ibcon#flushed, iclass 13, count 0 2006.258.01:40:40.26#ibcon#about to write, iclass 13, count 0 2006.258.01:40:40.26#ibcon#wrote, iclass 13, count 0 2006.258.01:40:40.26#ibcon#about to read 3, iclass 13, count 0 2006.258.01:40:40.30#ibcon#read 3, iclass 13, count 0 2006.258.01:40:40.30#ibcon#about to read 4, iclass 13, count 0 2006.258.01:40:40.30#ibcon#read 4, iclass 13, count 0 2006.258.01:40:40.30#ibcon#about to read 5, iclass 13, count 0 2006.258.01:40:40.30#ibcon#read 5, iclass 13, count 0 2006.258.01:40:40.30#ibcon#about to read 6, iclass 13, count 0 2006.258.01:40:40.30#ibcon#read 6, iclass 13, count 0 2006.258.01:40:40.30#ibcon#end of sib2, iclass 13, count 0 2006.258.01:40:40.30#ibcon#*after write, iclass 13, count 0 2006.258.01:40:40.30#ibcon#*before return 0, iclass 13, count 0 2006.258.01:40:40.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:40.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.258.01:40:40.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:40:40.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:40:40.30$vck44/vb=8,4 2006.258.01:40:40.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.258.01:40:40.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.258.01:40:40.30#ibcon#ireg 11 cls_cnt 2 2006.258.01:40:40.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:40.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:40.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:40.36#ibcon#enter wrdev, iclass 15, count 2 2006.258.01:40:40.36#ibcon#first serial, iclass 15, count 2 2006.258.01:40:40.36#ibcon#enter sib2, iclass 15, count 2 2006.258.01:40:40.36#ibcon#flushed, iclass 15, count 2 2006.258.01:40:40.36#ibcon#about to write, iclass 15, count 2 2006.258.01:40:40.36#ibcon#wrote, iclass 15, count 2 2006.258.01:40:40.36#ibcon#about to read 3, iclass 15, count 2 2006.258.01:40:40.38#ibcon#read 3, iclass 15, count 2 2006.258.01:40:40.38#ibcon#about to read 4, iclass 15, count 2 2006.258.01:40:40.38#ibcon#read 4, iclass 15, count 2 2006.258.01:40:40.38#ibcon#about to read 5, iclass 15, count 2 2006.258.01:40:40.38#ibcon#read 5, iclass 15, count 2 2006.258.01:40:40.38#ibcon#about to read 6, iclass 15, count 2 2006.258.01:40:40.38#ibcon#read 6, iclass 15, count 2 2006.258.01:40:40.38#ibcon#end of sib2, iclass 15, count 2 2006.258.01:40:40.38#ibcon#*mode == 0, iclass 15, count 2 2006.258.01:40:40.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.258.01:40:40.38#ibcon#[27=AT08-04\r\n] 2006.258.01:40:40.38#ibcon#*before write, iclass 15, count 2 2006.258.01:40:40.38#ibcon#enter sib2, iclass 15, count 2 2006.258.01:40:40.38#ibcon#flushed, iclass 15, count 2 2006.258.01:40:40.38#ibcon#about to write, iclass 15, count 2 2006.258.01:40:40.38#ibcon#wrote, iclass 15, count 2 2006.258.01:40:40.38#ibcon#about to read 3, iclass 15, count 2 2006.258.01:40:40.41#ibcon#read 3, iclass 15, count 2 2006.258.01:40:40.41#ibcon#about to read 4, iclass 15, count 2 2006.258.01:40:40.41#ibcon#read 4, iclass 15, count 2 2006.258.01:40:40.41#ibcon#about to read 5, iclass 15, count 2 2006.258.01:40:40.41#ibcon#read 5, iclass 15, count 2 2006.258.01:40:40.41#ibcon#about to read 6, iclass 15, count 2 2006.258.01:40:40.41#ibcon#read 6, iclass 15, count 2 2006.258.01:40:40.41#ibcon#end of sib2, iclass 15, count 2 2006.258.01:40:40.41#ibcon#*after write, iclass 15, count 2 2006.258.01:40:40.41#ibcon#*before return 0, iclass 15, count 2 2006.258.01:40:40.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:40.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.258.01:40:40.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.258.01:40:40.41#ibcon#ireg 7 cls_cnt 0 2006.258.01:40:40.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:40.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:40.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:40.53#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:40:40.53#ibcon#first serial, iclass 15, count 0 2006.258.01:40:40.53#ibcon#enter sib2, iclass 15, count 0 2006.258.01:40:40.53#ibcon#flushed, iclass 15, count 0 2006.258.01:40:40.53#ibcon#about to write, iclass 15, count 0 2006.258.01:40:40.53#ibcon#wrote, iclass 15, count 0 2006.258.01:40:40.53#ibcon#about to read 3, iclass 15, count 0 2006.258.01:40:40.55#ibcon#read 3, iclass 15, count 0 2006.258.01:40:40.55#ibcon#about to read 4, iclass 15, count 0 2006.258.01:40:40.55#ibcon#read 4, iclass 15, count 0 2006.258.01:40:40.55#ibcon#about to read 5, iclass 15, count 0 2006.258.01:40:40.55#ibcon#read 5, iclass 15, count 0 2006.258.01:40:40.55#ibcon#about to read 6, iclass 15, count 0 2006.258.01:40:40.55#ibcon#read 6, iclass 15, count 0 2006.258.01:40:40.55#ibcon#end of sib2, iclass 15, count 0 2006.258.01:40:40.55#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:40:40.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:40:40.55#ibcon#[27=USB\r\n] 2006.258.01:40:40.55#ibcon#*before write, iclass 15, count 0 2006.258.01:40:40.55#ibcon#enter sib2, iclass 15, count 0 2006.258.01:40:40.55#ibcon#flushed, iclass 15, count 0 2006.258.01:40:40.55#ibcon#about to write, iclass 15, count 0 2006.258.01:40:40.55#ibcon#wrote, iclass 15, count 0 2006.258.01:40:40.55#ibcon#about to read 3, iclass 15, count 0 2006.258.01:40:40.58#ibcon#read 3, iclass 15, count 0 2006.258.01:40:40.58#ibcon#about to read 4, iclass 15, count 0 2006.258.01:40:40.58#ibcon#read 4, iclass 15, count 0 2006.258.01:40:40.58#ibcon#about to read 5, iclass 15, count 0 2006.258.01:40:40.58#ibcon#read 5, iclass 15, count 0 2006.258.01:40:40.58#ibcon#about to read 6, iclass 15, count 0 2006.258.01:40:40.58#ibcon#read 6, iclass 15, count 0 2006.258.01:40:40.58#ibcon#end of sib2, iclass 15, count 0 2006.258.01:40:40.58#ibcon#*after write, iclass 15, count 0 2006.258.01:40:40.58#ibcon#*before return 0, iclass 15, count 0 2006.258.01:40:40.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:40.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.258.01:40:40.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:40:40.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:40:40.58$vck44/vabw=wide 2006.258.01:40:40.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.258.01:40:40.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.258.01:40:40.58#ibcon#ireg 8 cls_cnt 0 2006.258.01:40:40.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:40.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:40.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:40.58#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:40:40.58#ibcon#first serial, iclass 17, count 0 2006.258.01:40:40.58#ibcon#enter sib2, iclass 17, count 0 2006.258.01:40:40.58#ibcon#flushed, iclass 17, count 0 2006.258.01:40:40.58#ibcon#about to write, iclass 17, count 0 2006.258.01:40:40.58#ibcon#wrote, iclass 17, count 0 2006.258.01:40:40.58#ibcon#about to read 3, iclass 17, count 0 2006.258.01:40:40.60#ibcon#read 3, iclass 17, count 0 2006.258.01:40:40.60#ibcon#about to read 4, iclass 17, count 0 2006.258.01:40:40.60#ibcon#read 4, iclass 17, count 0 2006.258.01:40:40.60#ibcon#about to read 5, iclass 17, count 0 2006.258.01:40:40.60#ibcon#read 5, iclass 17, count 0 2006.258.01:40:40.60#ibcon#about to read 6, iclass 17, count 0 2006.258.01:40:40.60#ibcon#read 6, iclass 17, count 0 2006.258.01:40:40.60#ibcon#end of sib2, iclass 17, count 0 2006.258.01:40:40.60#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:40:40.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:40:40.60#ibcon#[25=BW32\r\n] 2006.258.01:40:40.60#ibcon#*before write, iclass 17, count 0 2006.258.01:40:40.60#ibcon#enter sib2, iclass 17, count 0 2006.258.01:40:40.60#ibcon#flushed, iclass 17, count 0 2006.258.01:40:40.60#ibcon#about to write, iclass 17, count 0 2006.258.01:40:40.60#ibcon#wrote, iclass 17, count 0 2006.258.01:40:40.60#ibcon#about to read 3, iclass 17, count 0 2006.258.01:40:40.63#ibcon#read 3, iclass 17, count 0 2006.258.01:40:40.63#ibcon#about to read 4, iclass 17, count 0 2006.258.01:40:40.63#ibcon#read 4, iclass 17, count 0 2006.258.01:40:40.63#ibcon#about to read 5, iclass 17, count 0 2006.258.01:40:40.63#ibcon#read 5, iclass 17, count 0 2006.258.01:40:40.63#ibcon#about to read 6, iclass 17, count 0 2006.258.01:40:40.63#ibcon#read 6, iclass 17, count 0 2006.258.01:40:40.63#ibcon#end of sib2, iclass 17, count 0 2006.258.01:40:40.63#ibcon#*after write, iclass 17, count 0 2006.258.01:40:40.63#ibcon#*before return 0, iclass 17, count 0 2006.258.01:40:40.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:40.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.258.01:40:40.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:40:40.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:40:40.63$vck44/vbbw=wide 2006.258.01:40:40.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.01:40:40.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.01:40:40.63#ibcon#ireg 8 cls_cnt 0 2006.258.01:40:40.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:40:40.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:40:40.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:40:40.70#ibcon#enter wrdev, iclass 19, count 0 2006.258.01:40:40.70#ibcon#first serial, iclass 19, count 0 2006.258.01:40:40.70#ibcon#enter sib2, iclass 19, count 0 2006.258.01:40:40.70#ibcon#flushed, iclass 19, count 0 2006.258.01:40:40.70#ibcon#about to write, iclass 19, count 0 2006.258.01:40:40.70#ibcon#wrote, iclass 19, count 0 2006.258.01:40:40.70#ibcon#about to read 3, iclass 19, count 0 2006.258.01:40:40.72#ibcon#read 3, iclass 19, count 0 2006.258.01:40:40.72#ibcon#about to read 4, iclass 19, count 0 2006.258.01:40:40.72#ibcon#read 4, iclass 19, count 0 2006.258.01:40:40.72#ibcon#about to read 5, iclass 19, count 0 2006.258.01:40:40.72#ibcon#read 5, iclass 19, count 0 2006.258.01:40:40.72#ibcon#about to read 6, iclass 19, count 0 2006.258.01:40:40.72#ibcon#read 6, iclass 19, count 0 2006.258.01:40:40.72#ibcon#end of sib2, iclass 19, count 0 2006.258.01:40:40.72#ibcon#*mode == 0, iclass 19, count 0 2006.258.01:40:40.72#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.01:40:40.72#ibcon#[27=BW32\r\n] 2006.258.01:40:40.72#ibcon#*before write, iclass 19, count 0 2006.258.01:40:40.72#ibcon#enter sib2, iclass 19, count 0 2006.258.01:40:40.72#ibcon#flushed, iclass 19, count 0 2006.258.01:40:40.72#ibcon#about to write, iclass 19, count 0 2006.258.01:40:40.72#ibcon#wrote, iclass 19, count 0 2006.258.01:40:40.72#ibcon#about to read 3, iclass 19, count 0 2006.258.01:40:40.75#ibcon#read 3, iclass 19, count 0 2006.258.01:40:40.75#ibcon#about to read 4, iclass 19, count 0 2006.258.01:40:40.75#ibcon#read 4, iclass 19, count 0 2006.258.01:40:40.75#ibcon#about to read 5, iclass 19, count 0 2006.258.01:40:40.75#ibcon#read 5, iclass 19, count 0 2006.258.01:40:40.75#ibcon#about to read 6, iclass 19, count 0 2006.258.01:40:40.75#ibcon#read 6, iclass 19, count 0 2006.258.01:40:40.75#ibcon#end of sib2, iclass 19, count 0 2006.258.01:40:40.75#ibcon#*after write, iclass 19, count 0 2006.258.01:40:40.75#ibcon#*before return 0, iclass 19, count 0 2006.258.01:40:40.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:40:40.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:40:40.75#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.01:40:40.75#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.01:40:40.75$setupk4/ifdk4 2006.258.01:40:40.75$ifdk4/lo= 2006.258.01:40:40.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.01:40:40.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.01:40:40.75$ifdk4/patch= 2006.258.01:40:40.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.01:40:40.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.01:40:40.75$setupk4/!*+20s 2006.258.01:40:43.49#abcon#<5=/03 3.3 7.0 23.52 701016.0\r\n> 2006.258.01:40:43.51#abcon#{5=INTERFACE CLEAR} 2006.258.01:40:43.57#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:40:53.66#abcon#<5=/03 3.4 7.0 23.52 691016.0\r\n> 2006.258.01:40:53.68#abcon#{5=INTERFACE CLEAR} 2006.258.01:40:53.74#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:40:55.21$setupk4/"tpicd 2006.258.01:40:55.21$setupk4/echo=off 2006.258.01:40:55.21$setupk4/xlog=off 2006.258.01:40:55.21:!2006.258.01:48:21 2006.258.01:41:20.13#trakl#Source acquired 2006.258.01:41:22.13#flagr#flagr/antenna,acquired 2006.258.01:48:21.00:preob 2006.258.01:48:21.13/onsource/TRACKING 2006.258.01:48:21.13:!2006.258.01:48:31 2006.258.01:48:31.00:"tape 2006.258.01:48:31.00:"st=record 2006.258.01:48:31.00:data_valid=on 2006.258.01:48:31.00:midob 2006.258.01:48:31.13/onsource/TRACKING 2006.258.01:48:31.13/wx/23.46,1015.9,72 2006.258.01:48:31.31/cable/+6.4728E-03 2006.258.01:48:32.40/va/01,08,usb,yes,31,33 2006.258.01:48:32.40/va/02,07,usb,yes,34,34 2006.258.01:48:32.40/va/03,08,usb,yes,30,32 2006.258.01:48:32.40/va/04,07,usb,yes,34,36 2006.258.01:48:32.40/va/05,04,usb,yes,31,31 2006.258.01:48:32.40/va/06,04,usb,yes,34,34 2006.258.01:48:32.40/va/07,04,usb,yes,35,36 2006.258.01:48:32.40/va/08,04,usb,yes,29,36 2006.258.01:48:32.63/valo/01,524.99,yes,locked 2006.258.01:48:32.63/valo/02,534.99,yes,locked 2006.258.01:48:32.63/valo/03,564.99,yes,locked 2006.258.01:48:32.63/valo/04,624.99,yes,locked 2006.258.01:48:32.63/valo/05,734.99,yes,locked 2006.258.01:48:32.63/valo/06,814.99,yes,locked 2006.258.01:48:32.63/valo/07,864.99,yes,locked 2006.258.01:48:32.63/valo/08,884.99,yes,locked 2006.258.01:48:33.72/vb/01,04,usb,yes,31,29 2006.258.01:48:33.72/vb/02,05,usb,yes,29,29 2006.258.01:48:33.72/vb/03,04,usb,yes,30,33 2006.258.01:48:33.72/vb/04,05,usb,yes,30,29 2006.258.01:48:33.72/vb/05,04,usb,yes,27,29 2006.258.01:48:33.72/vb/06,04,usb,yes,31,28 2006.258.01:48:33.72/vb/07,04,usb,yes,31,31 2006.258.01:48:33.72/vb/08,04,usb,yes,29,32 2006.258.01:48:33.96/vblo/01,629.99,yes,locked 2006.258.01:48:33.96/vblo/02,634.99,yes,locked 2006.258.01:48:33.96/vblo/03,649.99,yes,locked 2006.258.01:48:33.96/vblo/04,679.99,yes,locked 2006.258.01:48:33.96/vblo/05,709.99,yes,locked 2006.258.01:48:33.96/vblo/06,719.99,yes,locked 2006.258.01:48:33.96/vblo/07,734.99,yes,locked 2006.258.01:48:33.96/vblo/08,744.99,yes,locked 2006.258.01:48:34.11/vabw/8 2006.258.01:48:34.26/vbbw/8 2006.258.01:48:34.37/xfe/off,on,15.2 2006.258.01:48:34.82/ifatt/23,28,28,28 2006.258.01:48:35.08/fmout-gps/S +4.49E-07 2006.258.01:48:35.12:!2006.258.01:49:21 2006.258.01:49:21.00:data_valid=off 2006.258.01:49:21.00:"et 2006.258.01:49:21.00:!+3s 2006.258.01:49:24.02:"tape 2006.258.01:49:24.02:postob 2006.258.01:49:24.20/cable/+6.4736E-03 2006.258.01:49:24.20/wx/23.47,1015.9,72 2006.258.01:49:25.08/fmout-gps/S +4.49E-07 2006.258.01:49:25.08:scan_name=258-0152,jd0609,130 2006.258.01:49:25.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.258.01:49:26.13#flagr#flagr/antenna,new-source 2006.258.01:49:26.13:checkk5 2006.258.01:49:26.51/chk_autoobs//k5ts1/ autoobs is running! 2006.258.01:49:26.89/chk_autoobs//k5ts2/ autoobs is running! 2006.258.01:49:27.29/chk_autoobs//k5ts3/ autoobs is running! 2006.258.01:49:27.67/chk_autoobs//k5ts4/ autoobs is running! 2006.258.01:49:28.06/chk_obsdata//k5ts1/T2580148??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.258.01:49:28.43/chk_obsdata//k5ts2/T2580148??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.258.01:49:28.80/chk_obsdata//k5ts3/T2580148??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.258.01:49:29.18/chk_obsdata//k5ts4/T2580148??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.258.01:49:29.89/k5log//k5ts1_log_newline 2006.258.01:49:30.61/k5log//k5ts2_log_newline 2006.258.01:49:31.31/k5log//k5ts3_log_newline 2006.258.01:49:32.00/k5log//k5ts4_log_newline 2006.258.01:49:32.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:49:32.03:setupk4=1 2006.258.01:49:32.03$setupk4/echo=on 2006.258.01:49:32.03$setupk4/pcalon 2006.258.01:49:32.03$pcalon/"no phase cal control is implemented here 2006.258.01:49:32.03$setupk4/"tpicd=stop 2006.258.01:49:32.03$setupk4/"rec=synch_on 2006.258.01:49:32.03$setupk4/"rec_mode=128 2006.258.01:49:32.03$setupk4/!* 2006.258.01:49:32.03$setupk4/recpk4 2006.258.01:49:32.03$recpk4/recpatch= 2006.258.01:49:32.03$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.258.01:49:32.03$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.258.01:49:32.03$setupk4/vck44 2006.258.01:49:32.04$vck44/valo=1,524.99 2006.258.01:49:32.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.01:49:32.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.01:49:32.04#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:32.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:32.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:32.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:32.04#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:49:32.04#ibcon#first serial, iclass 11, count 0 2006.258.01:49:32.04#ibcon#enter sib2, iclass 11, count 0 2006.258.01:49:32.04#ibcon#flushed, iclass 11, count 0 2006.258.01:49:32.04#ibcon#about to write, iclass 11, count 0 2006.258.01:49:32.04#ibcon#wrote, iclass 11, count 0 2006.258.01:49:32.04#ibcon#about to read 3, iclass 11, count 0 2006.258.01:49:32.12#ibcon#read 3, iclass 11, count 0 2006.258.01:49:32.12#ibcon#about to read 4, iclass 11, count 0 2006.258.01:49:32.12#ibcon#read 4, iclass 11, count 0 2006.258.01:49:32.12#ibcon#about to read 5, iclass 11, count 0 2006.258.01:49:32.12#ibcon#read 5, iclass 11, count 0 2006.258.01:49:32.12#ibcon#about to read 6, iclass 11, count 0 2006.258.01:49:32.12#ibcon#read 6, iclass 11, count 0 2006.258.01:49:32.12#ibcon#end of sib2, iclass 11, count 0 2006.258.01:49:32.12#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:49:32.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:49:32.12#ibcon#[26=FRQ=01,524.99\r\n] 2006.258.01:49:32.12#ibcon#*before write, iclass 11, count 0 2006.258.01:49:32.12#ibcon#enter sib2, iclass 11, count 0 2006.258.01:49:32.12#ibcon#flushed, iclass 11, count 0 2006.258.01:49:32.12#ibcon#about to write, iclass 11, count 0 2006.258.01:49:32.12#ibcon#wrote, iclass 11, count 0 2006.258.01:49:32.12#ibcon#about to read 3, iclass 11, count 0 2006.258.01:49:32.22#ibcon#read 3, iclass 11, count 0 2006.258.01:49:32.22#ibcon#about to read 4, iclass 11, count 0 2006.258.01:49:32.22#ibcon#read 4, iclass 11, count 0 2006.258.01:49:32.22#ibcon#about to read 5, iclass 11, count 0 2006.258.01:49:32.22#ibcon#read 5, iclass 11, count 0 2006.258.01:49:32.22#ibcon#about to read 6, iclass 11, count 0 2006.258.01:49:32.22#ibcon#read 6, iclass 11, count 0 2006.258.01:49:32.22#ibcon#end of sib2, iclass 11, count 0 2006.258.01:49:32.22#ibcon#*after write, iclass 11, count 0 2006.258.01:49:32.22#ibcon#*before return 0, iclass 11, count 0 2006.258.01:49:32.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:32.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:32.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:49:32.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:49:32.22$vck44/va=1,8 2006.258.01:49:32.22#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.01:49:32.22#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.01:49:32.22#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:32.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:32.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:32.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:32.22#ibcon#enter wrdev, iclass 13, count 2 2006.258.01:49:32.22#ibcon#first serial, iclass 13, count 2 2006.258.01:49:32.22#ibcon#enter sib2, iclass 13, count 2 2006.258.01:49:32.22#ibcon#flushed, iclass 13, count 2 2006.258.01:49:32.22#ibcon#about to write, iclass 13, count 2 2006.258.01:49:32.22#ibcon#wrote, iclass 13, count 2 2006.258.01:49:32.22#ibcon#about to read 3, iclass 13, count 2 2006.258.01:49:32.24#ibcon#read 3, iclass 13, count 2 2006.258.01:49:32.24#ibcon#about to read 4, iclass 13, count 2 2006.258.01:49:32.24#ibcon#read 4, iclass 13, count 2 2006.258.01:49:32.24#ibcon#about to read 5, iclass 13, count 2 2006.258.01:49:32.24#ibcon#read 5, iclass 13, count 2 2006.258.01:49:32.24#ibcon#about to read 6, iclass 13, count 2 2006.258.01:49:32.24#ibcon#read 6, iclass 13, count 2 2006.258.01:49:32.24#ibcon#end of sib2, iclass 13, count 2 2006.258.01:49:32.24#ibcon#*mode == 0, iclass 13, count 2 2006.258.01:49:32.24#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.01:49:32.24#ibcon#[25=AT01-08\r\n] 2006.258.01:49:32.24#ibcon#*before write, iclass 13, count 2 2006.258.01:49:32.24#ibcon#enter sib2, iclass 13, count 2 2006.258.01:49:32.24#ibcon#flushed, iclass 13, count 2 2006.258.01:49:32.24#ibcon#about to write, iclass 13, count 2 2006.258.01:49:32.24#ibcon#wrote, iclass 13, count 2 2006.258.01:49:32.24#ibcon#about to read 3, iclass 13, count 2 2006.258.01:49:32.27#ibcon#read 3, iclass 13, count 2 2006.258.01:49:32.27#ibcon#about to read 4, iclass 13, count 2 2006.258.01:49:32.27#ibcon#read 4, iclass 13, count 2 2006.258.01:49:32.27#ibcon#about to read 5, iclass 13, count 2 2006.258.01:49:32.27#ibcon#read 5, iclass 13, count 2 2006.258.01:49:32.27#ibcon#about to read 6, iclass 13, count 2 2006.258.01:49:32.27#ibcon#read 6, iclass 13, count 2 2006.258.01:49:32.27#ibcon#end of sib2, iclass 13, count 2 2006.258.01:49:32.27#ibcon#*after write, iclass 13, count 2 2006.258.01:49:32.27#ibcon#*before return 0, iclass 13, count 2 2006.258.01:49:32.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:32.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:32.27#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.01:49:32.27#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:32.27#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:32.39#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:32.39#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:32.39#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:49:32.39#ibcon#first serial, iclass 13, count 0 2006.258.01:49:32.39#ibcon#enter sib2, iclass 13, count 0 2006.258.01:49:32.39#ibcon#flushed, iclass 13, count 0 2006.258.01:49:32.39#ibcon#about to write, iclass 13, count 0 2006.258.01:49:32.39#ibcon#wrote, iclass 13, count 0 2006.258.01:49:32.39#ibcon#about to read 3, iclass 13, count 0 2006.258.01:49:32.41#ibcon#read 3, iclass 13, count 0 2006.258.01:49:32.41#ibcon#about to read 4, iclass 13, count 0 2006.258.01:49:32.41#ibcon#read 4, iclass 13, count 0 2006.258.01:49:32.41#ibcon#about to read 5, iclass 13, count 0 2006.258.01:49:32.41#ibcon#read 5, iclass 13, count 0 2006.258.01:49:32.41#ibcon#about to read 6, iclass 13, count 0 2006.258.01:49:32.41#ibcon#read 6, iclass 13, count 0 2006.258.01:49:32.41#ibcon#end of sib2, iclass 13, count 0 2006.258.01:49:32.41#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:49:32.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:49:32.41#ibcon#[25=USB\r\n] 2006.258.01:49:32.41#ibcon#*before write, iclass 13, count 0 2006.258.01:49:32.41#ibcon#enter sib2, iclass 13, count 0 2006.258.01:49:32.41#ibcon#flushed, iclass 13, count 0 2006.258.01:49:32.41#ibcon#about to write, iclass 13, count 0 2006.258.01:49:32.41#ibcon#wrote, iclass 13, count 0 2006.258.01:49:32.41#ibcon#about to read 3, iclass 13, count 0 2006.258.01:49:32.48#ibcon#read 3, iclass 13, count 0 2006.258.01:49:32.48#ibcon#about to read 4, iclass 13, count 0 2006.258.01:49:32.48#ibcon#read 4, iclass 13, count 0 2006.258.01:49:32.48#ibcon#about to read 5, iclass 13, count 0 2006.258.01:49:32.48#ibcon#read 5, iclass 13, count 0 2006.258.01:49:32.48#ibcon#about to read 6, iclass 13, count 0 2006.258.01:49:32.48#ibcon#read 6, iclass 13, count 0 2006.258.01:49:32.48#ibcon#end of sib2, iclass 13, count 0 2006.258.01:49:32.48#ibcon#*after write, iclass 13, count 0 2006.258.01:49:32.48#ibcon#*before return 0, iclass 13, count 0 2006.258.01:49:32.48#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:32.48#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:32.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:49:32.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:49:32.48$vck44/valo=2,534.99 2006.258.01:49:32.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.01:49:32.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.01:49:32.48#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:32.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:32.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:32.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:32.48#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:49:32.48#ibcon#first serial, iclass 15, count 0 2006.258.01:49:32.48#ibcon#enter sib2, iclass 15, count 0 2006.258.01:49:32.48#ibcon#flushed, iclass 15, count 0 2006.258.01:49:32.48#ibcon#about to write, iclass 15, count 0 2006.258.01:49:32.48#ibcon#wrote, iclass 15, count 0 2006.258.01:49:32.48#ibcon#about to read 3, iclass 15, count 0 2006.258.01:49:32.50#ibcon#read 3, iclass 15, count 0 2006.258.01:49:32.50#ibcon#about to read 4, iclass 15, count 0 2006.258.01:49:32.50#ibcon#read 4, iclass 15, count 0 2006.258.01:49:32.50#ibcon#about to read 5, iclass 15, count 0 2006.258.01:49:32.50#ibcon#read 5, iclass 15, count 0 2006.258.01:49:32.50#ibcon#about to read 6, iclass 15, count 0 2006.258.01:49:32.50#ibcon#read 6, iclass 15, count 0 2006.258.01:49:32.50#ibcon#end of sib2, iclass 15, count 0 2006.258.01:49:32.50#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:49:32.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:49:32.50#ibcon#[26=FRQ=02,534.99\r\n] 2006.258.01:49:32.50#ibcon#*before write, iclass 15, count 0 2006.258.01:49:32.50#ibcon#enter sib2, iclass 15, count 0 2006.258.01:49:32.50#ibcon#flushed, iclass 15, count 0 2006.258.01:49:32.50#ibcon#about to write, iclass 15, count 0 2006.258.01:49:32.50#ibcon#wrote, iclass 15, count 0 2006.258.01:49:32.50#ibcon#about to read 3, iclass 15, count 0 2006.258.01:49:32.56#ibcon#read 3, iclass 15, count 0 2006.258.01:49:32.56#ibcon#about to read 4, iclass 15, count 0 2006.258.01:49:32.56#ibcon#read 4, iclass 15, count 0 2006.258.01:49:32.56#ibcon#about to read 5, iclass 15, count 0 2006.258.01:49:32.56#ibcon#read 5, iclass 15, count 0 2006.258.01:49:32.56#ibcon#about to read 6, iclass 15, count 0 2006.258.01:49:32.56#ibcon#read 6, iclass 15, count 0 2006.258.01:49:32.56#ibcon#end of sib2, iclass 15, count 0 2006.258.01:49:32.56#ibcon#*after write, iclass 15, count 0 2006.258.01:49:32.56#ibcon#*before return 0, iclass 15, count 0 2006.258.01:49:32.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:32.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:32.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:49:32.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:49:32.56$vck44/va=2,7 2006.258.01:49:32.56#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.01:49:32.56#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.01:49:32.56#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:32.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:32.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:32.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:32.60#ibcon#enter wrdev, iclass 17, count 2 2006.258.01:49:32.60#ibcon#first serial, iclass 17, count 2 2006.258.01:49:32.60#ibcon#enter sib2, iclass 17, count 2 2006.258.01:49:32.60#ibcon#flushed, iclass 17, count 2 2006.258.01:49:32.60#ibcon#about to write, iclass 17, count 2 2006.258.01:49:32.60#ibcon#wrote, iclass 17, count 2 2006.258.01:49:32.60#ibcon#about to read 3, iclass 17, count 2 2006.258.01:49:32.62#ibcon#read 3, iclass 17, count 2 2006.258.01:49:32.62#ibcon#about to read 4, iclass 17, count 2 2006.258.01:49:32.62#ibcon#read 4, iclass 17, count 2 2006.258.01:49:32.62#ibcon#about to read 5, iclass 17, count 2 2006.258.01:49:32.62#ibcon#read 5, iclass 17, count 2 2006.258.01:49:32.62#ibcon#about to read 6, iclass 17, count 2 2006.258.01:49:32.62#ibcon#read 6, iclass 17, count 2 2006.258.01:49:32.62#ibcon#end of sib2, iclass 17, count 2 2006.258.01:49:32.62#ibcon#*mode == 0, iclass 17, count 2 2006.258.01:49:32.62#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.01:49:32.62#ibcon#[25=AT02-07\r\n] 2006.258.01:49:32.62#ibcon#*before write, iclass 17, count 2 2006.258.01:49:32.62#ibcon#enter sib2, iclass 17, count 2 2006.258.01:49:32.62#ibcon#flushed, iclass 17, count 2 2006.258.01:49:32.62#ibcon#about to write, iclass 17, count 2 2006.258.01:49:32.62#ibcon#wrote, iclass 17, count 2 2006.258.01:49:32.62#ibcon#about to read 3, iclass 17, count 2 2006.258.01:49:32.65#ibcon#read 3, iclass 17, count 2 2006.258.01:49:32.65#ibcon#about to read 4, iclass 17, count 2 2006.258.01:49:32.65#ibcon#read 4, iclass 17, count 2 2006.258.01:49:32.65#ibcon#about to read 5, iclass 17, count 2 2006.258.01:49:32.65#ibcon#read 5, iclass 17, count 2 2006.258.01:49:32.65#ibcon#about to read 6, iclass 17, count 2 2006.258.01:49:32.65#ibcon#read 6, iclass 17, count 2 2006.258.01:49:32.65#ibcon#end of sib2, iclass 17, count 2 2006.258.01:49:32.65#ibcon#*after write, iclass 17, count 2 2006.258.01:49:32.65#ibcon#*before return 0, iclass 17, count 2 2006.258.01:49:32.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:32.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:32.65#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.01:49:32.65#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:32.65#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:32.77#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:32.77#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:32.77#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:49:32.77#ibcon#first serial, iclass 17, count 0 2006.258.01:49:32.77#ibcon#enter sib2, iclass 17, count 0 2006.258.01:49:32.77#ibcon#flushed, iclass 17, count 0 2006.258.01:49:32.77#ibcon#about to write, iclass 17, count 0 2006.258.01:49:32.77#ibcon#wrote, iclass 17, count 0 2006.258.01:49:32.77#ibcon#about to read 3, iclass 17, count 0 2006.258.01:49:32.79#ibcon#read 3, iclass 17, count 0 2006.258.01:49:32.79#ibcon#about to read 4, iclass 17, count 0 2006.258.01:49:32.79#ibcon#read 4, iclass 17, count 0 2006.258.01:49:32.79#ibcon#about to read 5, iclass 17, count 0 2006.258.01:49:32.79#ibcon#read 5, iclass 17, count 0 2006.258.01:49:32.79#ibcon#about to read 6, iclass 17, count 0 2006.258.01:49:32.79#ibcon#read 6, iclass 17, count 0 2006.258.01:49:32.79#ibcon#end of sib2, iclass 17, count 0 2006.258.01:49:32.79#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:49:32.79#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:49:32.79#ibcon#[25=USB\r\n] 2006.258.01:49:32.79#ibcon#*before write, iclass 17, count 0 2006.258.01:49:32.79#ibcon#enter sib2, iclass 17, count 0 2006.258.01:49:32.79#ibcon#flushed, iclass 17, count 0 2006.258.01:49:32.79#ibcon#about to write, iclass 17, count 0 2006.258.01:49:32.79#ibcon#wrote, iclass 17, count 0 2006.258.01:49:32.79#ibcon#about to read 3, iclass 17, count 0 2006.258.01:49:32.82#ibcon#read 3, iclass 17, count 0 2006.258.01:49:32.82#ibcon#about to read 4, iclass 17, count 0 2006.258.01:49:32.82#ibcon#read 4, iclass 17, count 0 2006.258.01:49:32.82#ibcon#about to read 5, iclass 17, count 0 2006.258.01:49:32.82#ibcon#read 5, iclass 17, count 0 2006.258.01:49:32.82#ibcon#about to read 6, iclass 17, count 0 2006.258.01:49:32.82#ibcon#read 6, iclass 17, count 0 2006.258.01:49:32.82#ibcon#end of sib2, iclass 17, count 0 2006.258.01:49:32.82#ibcon#*after write, iclass 17, count 0 2006.258.01:49:32.82#ibcon#*before return 0, iclass 17, count 0 2006.258.01:49:32.82#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:32.82#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:32.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:49:32.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:49:32.82$vck44/valo=3,564.99 2006.258.01:49:32.82#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.258.01:49:32.82#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.258.01:49:32.82#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:32.82#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:49:32.82#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:49:32.82#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:49:32.82#ibcon#enter wrdev, iclass 19, count 0 2006.258.01:49:32.82#ibcon#first serial, iclass 19, count 0 2006.258.01:49:32.82#ibcon#enter sib2, iclass 19, count 0 2006.258.01:49:32.82#ibcon#flushed, iclass 19, count 0 2006.258.01:49:32.82#ibcon#about to write, iclass 19, count 0 2006.258.01:49:32.82#ibcon#wrote, iclass 19, count 0 2006.258.01:49:32.82#ibcon#about to read 3, iclass 19, count 0 2006.258.01:49:32.84#ibcon#read 3, iclass 19, count 0 2006.258.01:49:32.84#ibcon#about to read 4, iclass 19, count 0 2006.258.01:49:32.84#ibcon#read 4, iclass 19, count 0 2006.258.01:49:32.84#ibcon#about to read 5, iclass 19, count 0 2006.258.01:49:32.84#ibcon#read 5, iclass 19, count 0 2006.258.01:49:32.84#ibcon#about to read 6, iclass 19, count 0 2006.258.01:49:32.84#ibcon#read 6, iclass 19, count 0 2006.258.01:49:32.84#ibcon#end of sib2, iclass 19, count 0 2006.258.01:49:32.84#ibcon#*mode == 0, iclass 19, count 0 2006.258.01:49:32.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.258.01:49:32.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.258.01:49:32.84#ibcon#*before write, iclass 19, count 0 2006.258.01:49:32.84#ibcon#enter sib2, iclass 19, count 0 2006.258.01:49:32.84#ibcon#flushed, iclass 19, count 0 2006.258.01:49:32.84#ibcon#about to write, iclass 19, count 0 2006.258.01:49:32.84#ibcon#wrote, iclass 19, count 0 2006.258.01:49:32.84#ibcon#about to read 3, iclass 19, count 0 2006.258.01:49:32.88#ibcon#read 3, iclass 19, count 0 2006.258.01:49:32.88#ibcon#about to read 4, iclass 19, count 0 2006.258.01:49:32.88#ibcon#read 4, iclass 19, count 0 2006.258.01:49:32.88#ibcon#about to read 5, iclass 19, count 0 2006.258.01:49:32.88#ibcon#read 5, iclass 19, count 0 2006.258.01:49:32.88#ibcon#about to read 6, iclass 19, count 0 2006.258.01:49:32.88#ibcon#read 6, iclass 19, count 0 2006.258.01:49:32.88#ibcon#end of sib2, iclass 19, count 0 2006.258.01:49:32.88#ibcon#*after write, iclass 19, count 0 2006.258.01:49:32.88#ibcon#*before return 0, iclass 19, count 0 2006.258.01:49:32.88#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:49:32.88#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.258.01:49:32.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.258.01:49:32.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.258.01:49:32.88$vck44/va=3,8 2006.258.01:49:32.88#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.258.01:49:32.88#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.258.01:49:32.88#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:32.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:49:32.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:49:32.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:49:32.94#ibcon#enter wrdev, iclass 21, count 2 2006.258.01:49:32.94#ibcon#first serial, iclass 21, count 2 2006.258.01:49:32.94#ibcon#enter sib2, iclass 21, count 2 2006.258.01:49:32.94#ibcon#flushed, iclass 21, count 2 2006.258.01:49:32.94#ibcon#about to write, iclass 21, count 2 2006.258.01:49:32.94#ibcon#wrote, iclass 21, count 2 2006.258.01:49:32.94#ibcon#about to read 3, iclass 21, count 2 2006.258.01:49:32.96#ibcon#read 3, iclass 21, count 2 2006.258.01:49:32.96#ibcon#about to read 4, iclass 21, count 2 2006.258.01:49:32.96#ibcon#read 4, iclass 21, count 2 2006.258.01:49:32.96#ibcon#about to read 5, iclass 21, count 2 2006.258.01:49:32.96#ibcon#read 5, iclass 21, count 2 2006.258.01:49:32.96#ibcon#about to read 6, iclass 21, count 2 2006.258.01:49:32.96#ibcon#read 6, iclass 21, count 2 2006.258.01:49:32.96#ibcon#end of sib2, iclass 21, count 2 2006.258.01:49:32.96#ibcon#*mode == 0, iclass 21, count 2 2006.258.01:49:32.96#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.258.01:49:32.96#ibcon#[25=AT03-08\r\n] 2006.258.01:49:32.96#ibcon#*before write, iclass 21, count 2 2006.258.01:49:32.96#ibcon#enter sib2, iclass 21, count 2 2006.258.01:49:32.96#ibcon#flushed, iclass 21, count 2 2006.258.01:49:32.96#ibcon#about to write, iclass 21, count 2 2006.258.01:49:32.96#ibcon#wrote, iclass 21, count 2 2006.258.01:49:32.96#ibcon#about to read 3, iclass 21, count 2 2006.258.01:49:32.99#ibcon#read 3, iclass 21, count 2 2006.258.01:49:32.99#ibcon#about to read 4, iclass 21, count 2 2006.258.01:49:32.99#ibcon#read 4, iclass 21, count 2 2006.258.01:49:32.99#ibcon#about to read 5, iclass 21, count 2 2006.258.01:49:32.99#ibcon#read 5, iclass 21, count 2 2006.258.01:49:32.99#ibcon#about to read 6, iclass 21, count 2 2006.258.01:49:32.99#ibcon#read 6, iclass 21, count 2 2006.258.01:49:32.99#ibcon#end of sib2, iclass 21, count 2 2006.258.01:49:32.99#ibcon#*after write, iclass 21, count 2 2006.258.01:49:32.99#ibcon#*before return 0, iclass 21, count 2 2006.258.01:49:32.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:49:32.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.258.01:49:32.99#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.258.01:49:32.99#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:32.99#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:49:33.11#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:49:33.11#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:49:33.11#ibcon#enter wrdev, iclass 21, count 0 2006.258.01:49:33.11#ibcon#first serial, iclass 21, count 0 2006.258.01:49:33.11#ibcon#enter sib2, iclass 21, count 0 2006.258.01:49:33.11#ibcon#flushed, iclass 21, count 0 2006.258.01:49:33.11#ibcon#about to write, iclass 21, count 0 2006.258.01:49:33.11#ibcon#wrote, iclass 21, count 0 2006.258.01:49:33.11#ibcon#about to read 3, iclass 21, count 0 2006.258.01:49:33.13#ibcon#read 3, iclass 21, count 0 2006.258.01:49:33.13#ibcon#about to read 4, iclass 21, count 0 2006.258.01:49:33.13#ibcon#read 4, iclass 21, count 0 2006.258.01:49:33.13#ibcon#about to read 5, iclass 21, count 0 2006.258.01:49:33.13#ibcon#read 5, iclass 21, count 0 2006.258.01:49:33.13#ibcon#about to read 6, iclass 21, count 0 2006.258.01:49:33.13#ibcon#read 6, iclass 21, count 0 2006.258.01:49:33.13#ibcon#end of sib2, iclass 21, count 0 2006.258.01:49:33.13#ibcon#*mode == 0, iclass 21, count 0 2006.258.01:49:33.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.258.01:49:33.13#ibcon#[25=USB\r\n] 2006.258.01:49:33.13#ibcon#*before write, iclass 21, count 0 2006.258.01:49:33.13#ibcon#enter sib2, iclass 21, count 0 2006.258.01:49:33.13#ibcon#flushed, iclass 21, count 0 2006.258.01:49:33.13#ibcon#about to write, iclass 21, count 0 2006.258.01:49:33.13#ibcon#wrote, iclass 21, count 0 2006.258.01:49:33.13#ibcon#about to read 3, iclass 21, count 0 2006.258.01:49:33.16#ibcon#read 3, iclass 21, count 0 2006.258.01:49:33.16#ibcon#about to read 4, iclass 21, count 0 2006.258.01:49:33.16#ibcon#read 4, iclass 21, count 0 2006.258.01:49:33.16#ibcon#about to read 5, iclass 21, count 0 2006.258.01:49:33.16#ibcon#read 5, iclass 21, count 0 2006.258.01:49:33.16#ibcon#about to read 6, iclass 21, count 0 2006.258.01:49:33.16#ibcon#read 6, iclass 21, count 0 2006.258.01:49:33.16#ibcon#end of sib2, iclass 21, count 0 2006.258.01:49:33.16#ibcon#*after write, iclass 21, count 0 2006.258.01:49:33.16#ibcon#*before return 0, iclass 21, count 0 2006.258.01:49:33.16#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:49:33.16#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.258.01:49:33.16#ibcon#about to clear, iclass 21 cls_cnt 0 2006.258.01:49:33.16#ibcon#cleared, iclass 21 cls_cnt 0 2006.258.01:49:33.16$vck44/valo=4,624.99 2006.258.01:49:33.16#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.258.01:49:33.16#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.258.01:49:33.16#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:33.16#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:49:33.16#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:49:33.16#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:49:33.16#ibcon#enter wrdev, iclass 23, count 0 2006.258.01:49:33.16#ibcon#first serial, iclass 23, count 0 2006.258.01:49:33.16#ibcon#enter sib2, iclass 23, count 0 2006.258.01:49:33.16#ibcon#flushed, iclass 23, count 0 2006.258.01:49:33.16#ibcon#about to write, iclass 23, count 0 2006.258.01:49:33.16#ibcon#wrote, iclass 23, count 0 2006.258.01:49:33.16#ibcon#about to read 3, iclass 23, count 0 2006.258.01:49:33.18#ibcon#read 3, iclass 23, count 0 2006.258.01:49:33.18#ibcon#about to read 4, iclass 23, count 0 2006.258.01:49:33.18#ibcon#read 4, iclass 23, count 0 2006.258.01:49:33.18#ibcon#about to read 5, iclass 23, count 0 2006.258.01:49:33.18#ibcon#read 5, iclass 23, count 0 2006.258.01:49:33.18#ibcon#about to read 6, iclass 23, count 0 2006.258.01:49:33.18#ibcon#read 6, iclass 23, count 0 2006.258.01:49:33.18#ibcon#end of sib2, iclass 23, count 0 2006.258.01:49:33.18#ibcon#*mode == 0, iclass 23, count 0 2006.258.01:49:33.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.258.01:49:33.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.258.01:49:33.18#ibcon#*before write, iclass 23, count 0 2006.258.01:49:33.18#ibcon#enter sib2, iclass 23, count 0 2006.258.01:49:33.18#ibcon#flushed, iclass 23, count 0 2006.258.01:49:33.18#ibcon#about to write, iclass 23, count 0 2006.258.01:49:33.18#ibcon#wrote, iclass 23, count 0 2006.258.01:49:33.18#ibcon#about to read 3, iclass 23, count 0 2006.258.01:49:33.22#ibcon#read 3, iclass 23, count 0 2006.258.01:49:33.22#ibcon#about to read 4, iclass 23, count 0 2006.258.01:49:33.22#ibcon#read 4, iclass 23, count 0 2006.258.01:49:33.22#ibcon#about to read 5, iclass 23, count 0 2006.258.01:49:33.22#ibcon#read 5, iclass 23, count 0 2006.258.01:49:33.22#ibcon#about to read 6, iclass 23, count 0 2006.258.01:49:33.22#ibcon#read 6, iclass 23, count 0 2006.258.01:49:33.22#ibcon#end of sib2, iclass 23, count 0 2006.258.01:49:33.22#ibcon#*after write, iclass 23, count 0 2006.258.01:49:33.22#ibcon#*before return 0, iclass 23, count 0 2006.258.01:49:33.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:49:33.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.258.01:49:33.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.258.01:49:33.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.258.01:49:33.22$vck44/va=4,7 2006.258.01:49:33.22#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.258.01:49:33.22#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.258.01:49:33.22#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:33.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:49:33.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:49:33.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:49:33.28#ibcon#enter wrdev, iclass 25, count 2 2006.258.01:49:33.28#ibcon#first serial, iclass 25, count 2 2006.258.01:49:33.28#ibcon#enter sib2, iclass 25, count 2 2006.258.01:49:33.28#ibcon#flushed, iclass 25, count 2 2006.258.01:49:33.28#ibcon#about to write, iclass 25, count 2 2006.258.01:49:33.28#ibcon#wrote, iclass 25, count 2 2006.258.01:49:33.28#ibcon#about to read 3, iclass 25, count 2 2006.258.01:49:33.30#ibcon#read 3, iclass 25, count 2 2006.258.01:49:33.30#ibcon#about to read 4, iclass 25, count 2 2006.258.01:49:33.30#ibcon#read 4, iclass 25, count 2 2006.258.01:49:33.30#ibcon#about to read 5, iclass 25, count 2 2006.258.01:49:33.30#ibcon#read 5, iclass 25, count 2 2006.258.01:49:33.30#ibcon#about to read 6, iclass 25, count 2 2006.258.01:49:33.30#ibcon#read 6, iclass 25, count 2 2006.258.01:49:33.30#ibcon#end of sib2, iclass 25, count 2 2006.258.01:49:33.30#ibcon#*mode == 0, iclass 25, count 2 2006.258.01:49:33.30#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.258.01:49:33.30#ibcon#[25=AT04-07\r\n] 2006.258.01:49:33.30#ibcon#*before write, iclass 25, count 2 2006.258.01:49:33.30#ibcon#enter sib2, iclass 25, count 2 2006.258.01:49:33.30#ibcon#flushed, iclass 25, count 2 2006.258.01:49:33.30#ibcon#about to write, iclass 25, count 2 2006.258.01:49:33.30#ibcon#wrote, iclass 25, count 2 2006.258.01:49:33.30#ibcon#about to read 3, iclass 25, count 2 2006.258.01:49:33.33#ibcon#read 3, iclass 25, count 2 2006.258.01:49:33.33#ibcon#about to read 4, iclass 25, count 2 2006.258.01:49:33.33#ibcon#read 4, iclass 25, count 2 2006.258.01:49:33.33#ibcon#about to read 5, iclass 25, count 2 2006.258.01:49:33.33#ibcon#read 5, iclass 25, count 2 2006.258.01:49:33.33#ibcon#about to read 6, iclass 25, count 2 2006.258.01:49:33.33#ibcon#read 6, iclass 25, count 2 2006.258.01:49:33.33#ibcon#end of sib2, iclass 25, count 2 2006.258.01:49:33.33#ibcon#*after write, iclass 25, count 2 2006.258.01:49:33.33#ibcon#*before return 0, iclass 25, count 2 2006.258.01:49:33.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:49:33.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.258.01:49:33.33#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.258.01:49:33.33#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:33.33#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:49:33.45#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:49:33.45#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:49:33.45#ibcon#enter wrdev, iclass 25, count 0 2006.258.01:49:33.45#ibcon#first serial, iclass 25, count 0 2006.258.01:49:33.45#ibcon#enter sib2, iclass 25, count 0 2006.258.01:49:33.45#ibcon#flushed, iclass 25, count 0 2006.258.01:49:33.45#ibcon#about to write, iclass 25, count 0 2006.258.01:49:33.45#ibcon#wrote, iclass 25, count 0 2006.258.01:49:33.45#ibcon#about to read 3, iclass 25, count 0 2006.258.01:49:33.47#ibcon#read 3, iclass 25, count 0 2006.258.01:49:33.47#ibcon#about to read 4, iclass 25, count 0 2006.258.01:49:33.47#ibcon#read 4, iclass 25, count 0 2006.258.01:49:33.47#ibcon#about to read 5, iclass 25, count 0 2006.258.01:49:33.47#ibcon#read 5, iclass 25, count 0 2006.258.01:49:33.47#ibcon#about to read 6, iclass 25, count 0 2006.258.01:49:33.47#ibcon#read 6, iclass 25, count 0 2006.258.01:49:33.47#ibcon#end of sib2, iclass 25, count 0 2006.258.01:49:33.47#ibcon#*mode == 0, iclass 25, count 0 2006.258.01:49:33.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.258.01:49:33.47#ibcon#[25=USB\r\n] 2006.258.01:49:33.47#ibcon#*before write, iclass 25, count 0 2006.258.01:49:33.47#ibcon#enter sib2, iclass 25, count 0 2006.258.01:49:33.47#ibcon#flushed, iclass 25, count 0 2006.258.01:49:33.47#ibcon#about to write, iclass 25, count 0 2006.258.01:49:33.47#ibcon#wrote, iclass 25, count 0 2006.258.01:49:33.47#ibcon#about to read 3, iclass 25, count 0 2006.258.01:49:33.50#ibcon#read 3, iclass 25, count 0 2006.258.01:49:33.50#ibcon#about to read 4, iclass 25, count 0 2006.258.01:49:33.50#ibcon#read 4, iclass 25, count 0 2006.258.01:49:33.50#ibcon#about to read 5, iclass 25, count 0 2006.258.01:49:33.50#ibcon#read 5, iclass 25, count 0 2006.258.01:49:33.50#ibcon#about to read 6, iclass 25, count 0 2006.258.01:49:33.50#ibcon#read 6, iclass 25, count 0 2006.258.01:49:33.50#ibcon#end of sib2, iclass 25, count 0 2006.258.01:49:33.50#ibcon#*after write, iclass 25, count 0 2006.258.01:49:33.50#ibcon#*before return 0, iclass 25, count 0 2006.258.01:49:33.50#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:49:33.50#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.258.01:49:33.50#ibcon#about to clear, iclass 25 cls_cnt 0 2006.258.01:49:33.50#ibcon#cleared, iclass 25 cls_cnt 0 2006.258.01:49:33.50$vck44/valo=5,734.99 2006.258.01:49:33.50#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.01:49:33.50#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.01:49:33.50#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:33.50#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:33.50#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:33.50#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:33.50#ibcon#enter wrdev, iclass 27, count 0 2006.258.01:49:33.50#ibcon#first serial, iclass 27, count 0 2006.258.01:49:33.50#ibcon#enter sib2, iclass 27, count 0 2006.258.01:49:33.50#ibcon#flushed, iclass 27, count 0 2006.258.01:49:33.50#ibcon#about to write, iclass 27, count 0 2006.258.01:49:33.50#ibcon#wrote, iclass 27, count 0 2006.258.01:49:33.50#ibcon#about to read 3, iclass 27, count 0 2006.258.01:49:33.52#ibcon#read 3, iclass 27, count 0 2006.258.01:49:33.52#ibcon#about to read 4, iclass 27, count 0 2006.258.01:49:33.52#ibcon#read 4, iclass 27, count 0 2006.258.01:49:33.52#ibcon#about to read 5, iclass 27, count 0 2006.258.01:49:33.52#ibcon#read 5, iclass 27, count 0 2006.258.01:49:33.52#ibcon#about to read 6, iclass 27, count 0 2006.258.01:49:33.52#ibcon#read 6, iclass 27, count 0 2006.258.01:49:33.52#ibcon#end of sib2, iclass 27, count 0 2006.258.01:49:33.52#ibcon#*mode == 0, iclass 27, count 0 2006.258.01:49:33.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.01:49:33.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.258.01:49:33.52#ibcon#*before write, iclass 27, count 0 2006.258.01:49:33.52#ibcon#enter sib2, iclass 27, count 0 2006.258.01:49:33.52#ibcon#flushed, iclass 27, count 0 2006.258.01:49:33.52#ibcon#about to write, iclass 27, count 0 2006.258.01:49:33.52#ibcon#wrote, iclass 27, count 0 2006.258.01:49:33.52#ibcon#about to read 3, iclass 27, count 0 2006.258.01:49:33.56#ibcon#read 3, iclass 27, count 0 2006.258.01:49:33.56#ibcon#about to read 4, iclass 27, count 0 2006.258.01:49:33.56#ibcon#read 4, iclass 27, count 0 2006.258.01:49:33.56#ibcon#about to read 5, iclass 27, count 0 2006.258.01:49:33.56#ibcon#read 5, iclass 27, count 0 2006.258.01:49:33.56#ibcon#about to read 6, iclass 27, count 0 2006.258.01:49:33.56#ibcon#read 6, iclass 27, count 0 2006.258.01:49:33.56#ibcon#end of sib2, iclass 27, count 0 2006.258.01:49:33.56#ibcon#*after write, iclass 27, count 0 2006.258.01:49:33.56#ibcon#*before return 0, iclass 27, count 0 2006.258.01:49:33.56#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:33.56#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:33.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.01:49:33.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.01:49:33.56$vck44/va=5,4 2006.258.01:49:33.56#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.01:49:33.56#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.01:49:33.56#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:33.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:33.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:33.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:33.62#ibcon#enter wrdev, iclass 29, count 2 2006.258.01:49:33.62#ibcon#first serial, iclass 29, count 2 2006.258.01:49:33.62#ibcon#enter sib2, iclass 29, count 2 2006.258.01:49:33.62#ibcon#flushed, iclass 29, count 2 2006.258.01:49:33.62#ibcon#about to write, iclass 29, count 2 2006.258.01:49:33.62#ibcon#wrote, iclass 29, count 2 2006.258.01:49:33.62#ibcon#about to read 3, iclass 29, count 2 2006.258.01:49:33.64#ibcon#read 3, iclass 29, count 2 2006.258.01:49:33.64#ibcon#about to read 4, iclass 29, count 2 2006.258.01:49:33.64#ibcon#read 4, iclass 29, count 2 2006.258.01:49:33.64#ibcon#about to read 5, iclass 29, count 2 2006.258.01:49:33.64#ibcon#read 5, iclass 29, count 2 2006.258.01:49:33.64#ibcon#about to read 6, iclass 29, count 2 2006.258.01:49:33.64#ibcon#read 6, iclass 29, count 2 2006.258.01:49:33.64#ibcon#end of sib2, iclass 29, count 2 2006.258.01:49:33.64#ibcon#*mode == 0, iclass 29, count 2 2006.258.01:49:33.64#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.01:49:33.64#ibcon#[25=AT05-04\r\n] 2006.258.01:49:33.64#ibcon#*before write, iclass 29, count 2 2006.258.01:49:33.64#ibcon#enter sib2, iclass 29, count 2 2006.258.01:49:33.64#ibcon#flushed, iclass 29, count 2 2006.258.01:49:33.64#ibcon#about to write, iclass 29, count 2 2006.258.01:49:33.64#ibcon#wrote, iclass 29, count 2 2006.258.01:49:33.64#ibcon#about to read 3, iclass 29, count 2 2006.258.01:49:33.67#ibcon#read 3, iclass 29, count 2 2006.258.01:49:33.67#ibcon#about to read 4, iclass 29, count 2 2006.258.01:49:33.67#ibcon#read 4, iclass 29, count 2 2006.258.01:49:33.67#ibcon#about to read 5, iclass 29, count 2 2006.258.01:49:33.67#ibcon#read 5, iclass 29, count 2 2006.258.01:49:33.67#ibcon#about to read 6, iclass 29, count 2 2006.258.01:49:33.67#ibcon#read 6, iclass 29, count 2 2006.258.01:49:33.67#ibcon#end of sib2, iclass 29, count 2 2006.258.01:49:33.67#ibcon#*after write, iclass 29, count 2 2006.258.01:49:33.67#ibcon#*before return 0, iclass 29, count 2 2006.258.01:49:33.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:33.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:33.67#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.01:49:33.67#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:33.67#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:33.79#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:33.79#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:33.79#ibcon#enter wrdev, iclass 29, count 0 2006.258.01:49:33.79#ibcon#first serial, iclass 29, count 0 2006.258.01:49:33.79#ibcon#enter sib2, iclass 29, count 0 2006.258.01:49:33.79#ibcon#flushed, iclass 29, count 0 2006.258.01:49:33.79#ibcon#about to write, iclass 29, count 0 2006.258.01:49:33.79#ibcon#wrote, iclass 29, count 0 2006.258.01:49:33.79#ibcon#about to read 3, iclass 29, count 0 2006.258.01:49:33.81#ibcon#read 3, iclass 29, count 0 2006.258.01:49:33.81#ibcon#about to read 4, iclass 29, count 0 2006.258.01:49:33.81#ibcon#read 4, iclass 29, count 0 2006.258.01:49:33.81#ibcon#about to read 5, iclass 29, count 0 2006.258.01:49:33.81#ibcon#read 5, iclass 29, count 0 2006.258.01:49:33.81#ibcon#about to read 6, iclass 29, count 0 2006.258.01:49:33.81#ibcon#read 6, iclass 29, count 0 2006.258.01:49:33.81#ibcon#end of sib2, iclass 29, count 0 2006.258.01:49:33.81#ibcon#*mode == 0, iclass 29, count 0 2006.258.01:49:33.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.01:49:33.81#ibcon#[25=USB\r\n] 2006.258.01:49:33.81#ibcon#*before write, iclass 29, count 0 2006.258.01:49:33.81#ibcon#enter sib2, iclass 29, count 0 2006.258.01:49:33.81#ibcon#flushed, iclass 29, count 0 2006.258.01:49:33.81#ibcon#about to write, iclass 29, count 0 2006.258.01:49:33.81#ibcon#wrote, iclass 29, count 0 2006.258.01:49:33.81#ibcon#about to read 3, iclass 29, count 0 2006.258.01:49:33.84#ibcon#read 3, iclass 29, count 0 2006.258.01:49:33.84#ibcon#about to read 4, iclass 29, count 0 2006.258.01:49:33.84#ibcon#read 4, iclass 29, count 0 2006.258.01:49:33.84#ibcon#about to read 5, iclass 29, count 0 2006.258.01:49:33.84#ibcon#read 5, iclass 29, count 0 2006.258.01:49:33.84#ibcon#about to read 6, iclass 29, count 0 2006.258.01:49:33.84#ibcon#read 6, iclass 29, count 0 2006.258.01:49:33.84#ibcon#end of sib2, iclass 29, count 0 2006.258.01:49:33.84#ibcon#*after write, iclass 29, count 0 2006.258.01:49:33.84#ibcon#*before return 0, iclass 29, count 0 2006.258.01:49:33.84#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:33.84#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:33.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.01:49:33.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.01:49:33.84$vck44/valo=6,814.99 2006.258.01:49:33.84#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.258.01:49:33.84#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.258.01:49:33.84#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:33.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:33.84#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:33.84#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:33.84#ibcon#enter wrdev, iclass 31, count 0 2006.258.01:49:33.84#ibcon#first serial, iclass 31, count 0 2006.258.01:49:33.84#ibcon#enter sib2, iclass 31, count 0 2006.258.01:49:33.84#ibcon#flushed, iclass 31, count 0 2006.258.01:49:33.84#ibcon#about to write, iclass 31, count 0 2006.258.01:49:33.84#ibcon#wrote, iclass 31, count 0 2006.258.01:49:33.84#ibcon#about to read 3, iclass 31, count 0 2006.258.01:49:33.86#ibcon#read 3, iclass 31, count 0 2006.258.01:49:33.86#ibcon#about to read 4, iclass 31, count 0 2006.258.01:49:33.86#ibcon#read 4, iclass 31, count 0 2006.258.01:49:33.86#ibcon#about to read 5, iclass 31, count 0 2006.258.01:49:33.86#ibcon#read 5, iclass 31, count 0 2006.258.01:49:33.86#ibcon#about to read 6, iclass 31, count 0 2006.258.01:49:33.86#ibcon#read 6, iclass 31, count 0 2006.258.01:49:33.86#ibcon#end of sib2, iclass 31, count 0 2006.258.01:49:33.86#ibcon#*mode == 0, iclass 31, count 0 2006.258.01:49:33.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.01:49:33.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.258.01:49:33.86#ibcon#*before write, iclass 31, count 0 2006.258.01:49:33.86#ibcon#enter sib2, iclass 31, count 0 2006.258.01:49:33.86#ibcon#flushed, iclass 31, count 0 2006.258.01:49:33.86#ibcon#about to write, iclass 31, count 0 2006.258.01:49:33.86#ibcon#wrote, iclass 31, count 0 2006.258.01:49:33.86#ibcon#about to read 3, iclass 31, count 0 2006.258.01:49:33.90#ibcon#read 3, iclass 31, count 0 2006.258.01:49:33.90#ibcon#about to read 4, iclass 31, count 0 2006.258.01:49:33.90#ibcon#read 4, iclass 31, count 0 2006.258.01:49:33.90#ibcon#about to read 5, iclass 31, count 0 2006.258.01:49:33.90#ibcon#read 5, iclass 31, count 0 2006.258.01:49:33.90#ibcon#about to read 6, iclass 31, count 0 2006.258.01:49:33.90#ibcon#read 6, iclass 31, count 0 2006.258.01:49:33.90#ibcon#end of sib2, iclass 31, count 0 2006.258.01:49:33.90#ibcon#*after write, iclass 31, count 0 2006.258.01:49:33.90#ibcon#*before return 0, iclass 31, count 0 2006.258.01:49:33.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:33.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:33.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.01:49:33.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.01:49:33.90$vck44/va=6,4 2006.258.01:49:33.90#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.01:49:33.90#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.01:49:33.90#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:33.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:33.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:33.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:33.96#ibcon#enter wrdev, iclass 33, count 2 2006.258.01:49:33.96#ibcon#first serial, iclass 33, count 2 2006.258.01:49:33.96#ibcon#enter sib2, iclass 33, count 2 2006.258.01:49:33.96#ibcon#flushed, iclass 33, count 2 2006.258.01:49:33.96#ibcon#about to write, iclass 33, count 2 2006.258.01:49:33.96#ibcon#wrote, iclass 33, count 2 2006.258.01:49:33.96#ibcon#about to read 3, iclass 33, count 2 2006.258.01:49:33.98#ibcon#read 3, iclass 33, count 2 2006.258.01:49:33.98#ibcon#about to read 4, iclass 33, count 2 2006.258.01:49:33.98#ibcon#read 4, iclass 33, count 2 2006.258.01:49:33.98#ibcon#about to read 5, iclass 33, count 2 2006.258.01:49:33.98#ibcon#read 5, iclass 33, count 2 2006.258.01:49:33.98#ibcon#about to read 6, iclass 33, count 2 2006.258.01:49:33.98#ibcon#read 6, iclass 33, count 2 2006.258.01:49:33.98#ibcon#end of sib2, iclass 33, count 2 2006.258.01:49:33.98#ibcon#*mode == 0, iclass 33, count 2 2006.258.01:49:33.98#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.01:49:33.98#ibcon#[25=AT06-04\r\n] 2006.258.01:49:33.98#ibcon#*before write, iclass 33, count 2 2006.258.01:49:33.98#ibcon#enter sib2, iclass 33, count 2 2006.258.01:49:33.98#ibcon#flushed, iclass 33, count 2 2006.258.01:49:33.98#ibcon#about to write, iclass 33, count 2 2006.258.01:49:33.98#ibcon#wrote, iclass 33, count 2 2006.258.01:49:33.98#ibcon#about to read 3, iclass 33, count 2 2006.258.01:49:34.01#ibcon#read 3, iclass 33, count 2 2006.258.01:49:34.01#ibcon#about to read 4, iclass 33, count 2 2006.258.01:49:34.01#ibcon#read 4, iclass 33, count 2 2006.258.01:49:34.01#ibcon#about to read 5, iclass 33, count 2 2006.258.01:49:34.01#ibcon#read 5, iclass 33, count 2 2006.258.01:49:34.01#ibcon#about to read 6, iclass 33, count 2 2006.258.01:49:34.01#ibcon#read 6, iclass 33, count 2 2006.258.01:49:34.01#ibcon#end of sib2, iclass 33, count 2 2006.258.01:49:34.01#ibcon#*after write, iclass 33, count 2 2006.258.01:49:34.01#ibcon#*before return 0, iclass 33, count 2 2006.258.01:49:34.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:34.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:34.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.01:49:34.01#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:34.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:34.13#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:34.13#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:34.13#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:49:34.13#ibcon#first serial, iclass 33, count 0 2006.258.01:49:34.13#ibcon#enter sib2, iclass 33, count 0 2006.258.01:49:34.13#ibcon#flushed, iclass 33, count 0 2006.258.01:49:34.13#ibcon#about to write, iclass 33, count 0 2006.258.01:49:34.13#ibcon#wrote, iclass 33, count 0 2006.258.01:49:34.13#ibcon#about to read 3, iclass 33, count 0 2006.258.01:49:34.15#ibcon#read 3, iclass 33, count 0 2006.258.01:49:34.15#ibcon#about to read 4, iclass 33, count 0 2006.258.01:49:34.15#ibcon#read 4, iclass 33, count 0 2006.258.01:49:34.15#ibcon#about to read 5, iclass 33, count 0 2006.258.01:49:34.15#ibcon#read 5, iclass 33, count 0 2006.258.01:49:34.15#ibcon#about to read 6, iclass 33, count 0 2006.258.01:49:34.15#ibcon#read 6, iclass 33, count 0 2006.258.01:49:34.15#ibcon#end of sib2, iclass 33, count 0 2006.258.01:49:34.15#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:49:34.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:49:34.15#ibcon#[25=USB\r\n] 2006.258.01:49:34.15#ibcon#*before write, iclass 33, count 0 2006.258.01:49:34.15#ibcon#enter sib2, iclass 33, count 0 2006.258.01:49:34.15#ibcon#flushed, iclass 33, count 0 2006.258.01:49:34.15#ibcon#about to write, iclass 33, count 0 2006.258.01:49:34.15#ibcon#wrote, iclass 33, count 0 2006.258.01:49:34.15#ibcon#about to read 3, iclass 33, count 0 2006.258.01:49:34.18#ibcon#read 3, iclass 33, count 0 2006.258.01:49:34.18#ibcon#about to read 4, iclass 33, count 0 2006.258.01:49:34.18#ibcon#read 4, iclass 33, count 0 2006.258.01:49:34.18#ibcon#about to read 5, iclass 33, count 0 2006.258.01:49:34.18#ibcon#read 5, iclass 33, count 0 2006.258.01:49:34.18#ibcon#about to read 6, iclass 33, count 0 2006.258.01:49:34.18#ibcon#read 6, iclass 33, count 0 2006.258.01:49:34.18#ibcon#end of sib2, iclass 33, count 0 2006.258.01:49:34.18#ibcon#*after write, iclass 33, count 0 2006.258.01:49:34.18#ibcon#*before return 0, iclass 33, count 0 2006.258.01:49:34.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:34.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:34.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:49:34.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:49:34.18$vck44/valo=7,864.99 2006.258.01:49:34.18#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.01:49:34.18#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.01:49:34.18#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:34.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:34.18#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:34.18#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:34.18#ibcon#enter wrdev, iclass 35, count 0 2006.258.01:49:34.18#ibcon#first serial, iclass 35, count 0 2006.258.01:49:34.18#ibcon#enter sib2, iclass 35, count 0 2006.258.01:49:34.18#ibcon#flushed, iclass 35, count 0 2006.258.01:49:34.18#ibcon#about to write, iclass 35, count 0 2006.258.01:49:34.18#ibcon#wrote, iclass 35, count 0 2006.258.01:49:34.18#ibcon#about to read 3, iclass 35, count 0 2006.258.01:49:34.20#ibcon#read 3, iclass 35, count 0 2006.258.01:49:34.20#ibcon#about to read 4, iclass 35, count 0 2006.258.01:49:34.20#ibcon#read 4, iclass 35, count 0 2006.258.01:49:34.20#ibcon#about to read 5, iclass 35, count 0 2006.258.01:49:34.20#ibcon#read 5, iclass 35, count 0 2006.258.01:49:34.20#ibcon#about to read 6, iclass 35, count 0 2006.258.01:49:34.20#ibcon#read 6, iclass 35, count 0 2006.258.01:49:34.20#ibcon#end of sib2, iclass 35, count 0 2006.258.01:49:34.20#ibcon#*mode == 0, iclass 35, count 0 2006.258.01:49:34.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.01:49:34.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.258.01:49:34.20#ibcon#*before write, iclass 35, count 0 2006.258.01:49:34.20#ibcon#enter sib2, iclass 35, count 0 2006.258.01:49:34.20#ibcon#flushed, iclass 35, count 0 2006.258.01:49:34.20#ibcon#about to write, iclass 35, count 0 2006.258.01:49:34.20#ibcon#wrote, iclass 35, count 0 2006.258.01:49:34.20#ibcon#about to read 3, iclass 35, count 0 2006.258.01:49:34.24#ibcon#read 3, iclass 35, count 0 2006.258.01:49:34.24#ibcon#about to read 4, iclass 35, count 0 2006.258.01:49:34.24#ibcon#read 4, iclass 35, count 0 2006.258.01:49:34.24#ibcon#about to read 5, iclass 35, count 0 2006.258.01:49:34.24#ibcon#read 5, iclass 35, count 0 2006.258.01:49:34.24#ibcon#about to read 6, iclass 35, count 0 2006.258.01:49:34.24#ibcon#read 6, iclass 35, count 0 2006.258.01:49:34.24#ibcon#end of sib2, iclass 35, count 0 2006.258.01:49:34.24#ibcon#*after write, iclass 35, count 0 2006.258.01:49:34.24#ibcon#*before return 0, iclass 35, count 0 2006.258.01:49:34.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:34.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:34.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.01:49:34.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.01:49:34.24$vck44/va=7,4 2006.258.01:49:34.24#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.01:49:34.24#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.01:49:34.24#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:34.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:34.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:34.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:34.30#ibcon#enter wrdev, iclass 37, count 2 2006.258.01:49:34.30#ibcon#first serial, iclass 37, count 2 2006.258.01:49:34.30#ibcon#enter sib2, iclass 37, count 2 2006.258.01:49:34.30#ibcon#flushed, iclass 37, count 2 2006.258.01:49:34.30#ibcon#about to write, iclass 37, count 2 2006.258.01:49:34.30#ibcon#wrote, iclass 37, count 2 2006.258.01:49:34.30#ibcon#about to read 3, iclass 37, count 2 2006.258.01:49:34.32#ibcon#read 3, iclass 37, count 2 2006.258.01:49:34.32#ibcon#about to read 4, iclass 37, count 2 2006.258.01:49:34.32#ibcon#read 4, iclass 37, count 2 2006.258.01:49:34.32#ibcon#about to read 5, iclass 37, count 2 2006.258.01:49:34.32#ibcon#read 5, iclass 37, count 2 2006.258.01:49:34.32#ibcon#about to read 6, iclass 37, count 2 2006.258.01:49:34.32#ibcon#read 6, iclass 37, count 2 2006.258.01:49:34.32#ibcon#end of sib2, iclass 37, count 2 2006.258.01:49:34.32#ibcon#*mode == 0, iclass 37, count 2 2006.258.01:49:34.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.01:49:34.32#ibcon#[25=AT07-04\r\n] 2006.258.01:49:34.32#ibcon#*before write, iclass 37, count 2 2006.258.01:49:34.32#ibcon#enter sib2, iclass 37, count 2 2006.258.01:49:34.32#ibcon#flushed, iclass 37, count 2 2006.258.01:49:34.32#ibcon#about to write, iclass 37, count 2 2006.258.01:49:34.32#ibcon#wrote, iclass 37, count 2 2006.258.01:49:34.32#ibcon#about to read 3, iclass 37, count 2 2006.258.01:49:34.35#ibcon#read 3, iclass 37, count 2 2006.258.01:49:34.35#ibcon#about to read 4, iclass 37, count 2 2006.258.01:49:34.35#ibcon#read 4, iclass 37, count 2 2006.258.01:49:34.35#ibcon#about to read 5, iclass 37, count 2 2006.258.01:49:34.35#ibcon#read 5, iclass 37, count 2 2006.258.01:49:34.35#ibcon#about to read 6, iclass 37, count 2 2006.258.01:49:34.35#ibcon#read 6, iclass 37, count 2 2006.258.01:49:34.35#ibcon#end of sib2, iclass 37, count 2 2006.258.01:49:34.35#ibcon#*after write, iclass 37, count 2 2006.258.01:49:34.35#ibcon#*before return 0, iclass 37, count 2 2006.258.01:49:34.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:34.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:34.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.01:49:34.35#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:34.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:34.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:34.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:34.47#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:49:34.47#ibcon#first serial, iclass 37, count 0 2006.258.01:49:34.47#ibcon#enter sib2, iclass 37, count 0 2006.258.01:49:34.47#ibcon#flushed, iclass 37, count 0 2006.258.01:49:34.47#ibcon#about to write, iclass 37, count 0 2006.258.01:49:34.47#ibcon#wrote, iclass 37, count 0 2006.258.01:49:34.47#ibcon#about to read 3, iclass 37, count 0 2006.258.01:49:34.49#ibcon#read 3, iclass 37, count 0 2006.258.01:49:34.49#ibcon#about to read 4, iclass 37, count 0 2006.258.01:49:34.49#ibcon#read 4, iclass 37, count 0 2006.258.01:49:34.49#ibcon#about to read 5, iclass 37, count 0 2006.258.01:49:34.49#ibcon#read 5, iclass 37, count 0 2006.258.01:49:34.49#ibcon#about to read 6, iclass 37, count 0 2006.258.01:49:34.49#ibcon#read 6, iclass 37, count 0 2006.258.01:49:34.49#ibcon#end of sib2, iclass 37, count 0 2006.258.01:49:34.49#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:49:34.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:49:34.49#ibcon#[25=USB\r\n] 2006.258.01:49:34.49#ibcon#*before write, iclass 37, count 0 2006.258.01:49:34.49#ibcon#enter sib2, iclass 37, count 0 2006.258.01:49:34.49#ibcon#flushed, iclass 37, count 0 2006.258.01:49:34.49#ibcon#about to write, iclass 37, count 0 2006.258.01:49:34.49#ibcon#wrote, iclass 37, count 0 2006.258.01:49:34.49#ibcon#about to read 3, iclass 37, count 0 2006.258.01:49:34.52#ibcon#read 3, iclass 37, count 0 2006.258.01:49:34.52#ibcon#about to read 4, iclass 37, count 0 2006.258.01:49:34.52#ibcon#read 4, iclass 37, count 0 2006.258.01:49:34.52#ibcon#about to read 5, iclass 37, count 0 2006.258.01:49:34.52#ibcon#read 5, iclass 37, count 0 2006.258.01:49:34.52#ibcon#about to read 6, iclass 37, count 0 2006.258.01:49:34.52#ibcon#read 6, iclass 37, count 0 2006.258.01:49:34.52#ibcon#end of sib2, iclass 37, count 0 2006.258.01:49:34.52#ibcon#*after write, iclass 37, count 0 2006.258.01:49:34.52#ibcon#*before return 0, iclass 37, count 0 2006.258.01:49:34.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:34.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:34.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:49:34.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:49:34.52$vck44/valo=8,884.99 2006.258.01:49:34.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.01:49:34.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.01:49:34.52#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:34.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:34.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:34.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:34.52#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:49:34.52#ibcon#first serial, iclass 39, count 0 2006.258.01:49:34.52#ibcon#enter sib2, iclass 39, count 0 2006.258.01:49:34.52#ibcon#flushed, iclass 39, count 0 2006.258.01:49:34.52#ibcon#about to write, iclass 39, count 0 2006.258.01:49:34.52#ibcon#wrote, iclass 39, count 0 2006.258.01:49:34.52#ibcon#about to read 3, iclass 39, count 0 2006.258.01:49:34.54#ibcon#read 3, iclass 39, count 0 2006.258.01:49:34.54#ibcon#about to read 4, iclass 39, count 0 2006.258.01:49:34.54#ibcon#read 4, iclass 39, count 0 2006.258.01:49:34.54#ibcon#about to read 5, iclass 39, count 0 2006.258.01:49:34.54#ibcon#read 5, iclass 39, count 0 2006.258.01:49:34.54#ibcon#about to read 6, iclass 39, count 0 2006.258.01:49:34.54#ibcon#read 6, iclass 39, count 0 2006.258.01:49:34.54#ibcon#end of sib2, iclass 39, count 0 2006.258.01:49:34.54#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:49:34.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:49:34.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.258.01:49:34.54#ibcon#*before write, iclass 39, count 0 2006.258.01:49:34.54#ibcon#enter sib2, iclass 39, count 0 2006.258.01:49:34.54#ibcon#flushed, iclass 39, count 0 2006.258.01:49:34.54#ibcon#about to write, iclass 39, count 0 2006.258.01:49:34.54#ibcon#wrote, iclass 39, count 0 2006.258.01:49:34.54#ibcon#about to read 3, iclass 39, count 0 2006.258.01:49:34.58#ibcon#read 3, iclass 39, count 0 2006.258.01:49:34.58#ibcon#about to read 4, iclass 39, count 0 2006.258.01:49:34.58#ibcon#read 4, iclass 39, count 0 2006.258.01:49:34.58#ibcon#about to read 5, iclass 39, count 0 2006.258.01:49:34.58#ibcon#read 5, iclass 39, count 0 2006.258.01:49:34.58#ibcon#about to read 6, iclass 39, count 0 2006.258.01:49:34.58#ibcon#read 6, iclass 39, count 0 2006.258.01:49:34.58#ibcon#end of sib2, iclass 39, count 0 2006.258.01:49:34.58#ibcon#*after write, iclass 39, count 0 2006.258.01:49:34.58#ibcon#*before return 0, iclass 39, count 0 2006.258.01:49:34.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:34.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:34.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:49:34.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:49:34.58$vck44/va=8,4 2006.258.01:49:34.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.01:49:34.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.01:49:34.58#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:34.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:34.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:34.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:34.64#ibcon#enter wrdev, iclass 3, count 2 2006.258.01:49:34.64#ibcon#first serial, iclass 3, count 2 2006.258.01:49:34.64#ibcon#enter sib2, iclass 3, count 2 2006.258.01:49:34.64#ibcon#flushed, iclass 3, count 2 2006.258.01:49:34.64#ibcon#about to write, iclass 3, count 2 2006.258.01:49:34.64#ibcon#wrote, iclass 3, count 2 2006.258.01:49:34.64#ibcon#about to read 3, iclass 3, count 2 2006.258.01:49:34.66#ibcon#read 3, iclass 3, count 2 2006.258.01:49:34.66#ibcon#about to read 4, iclass 3, count 2 2006.258.01:49:34.66#ibcon#read 4, iclass 3, count 2 2006.258.01:49:34.66#ibcon#about to read 5, iclass 3, count 2 2006.258.01:49:34.66#ibcon#read 5, iclass 3, count 2 2006.258.01:49:34.66#ibcon#about to read 6, iclass 3, count 2 2006.258.01:49:34.66#ibcon#read 6, iclass 3, count 2 2006.258.01:49:34.66#ibcon#end of sib2, iclass 3, count 2 2006.258.01:49:34.66#ibcon#*mode == 0, iclass 3, count 2 2006.258.01:49:34.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.01:49:34.66#ibcon#[25=AT08-04\r\n] 2006.258.01:49:34.66#ibcon#*before write, iclass 3, count 2 2006.258.01:49:34.66#ibcon#enter sib2, iclass 3, count 2 2006.258.01:49:34.66#ibcon#flushed, iclass 3, count 2 2006.258.01:49:34.66#ibcon#about to write, iclass 3, count 2 2006.258.01:49:34.66#ibcon#wrote, iclass 3, count 2 2006.258.01:49:34.66#ibcon#about to read 3, iclass 3, count 2 2006.258.01:49:34.69#ibcon#read 3, iclass 3, count 2 2006.258.01:49:34.69#ibcon#about to read 4, iclass 3, count 2 2006.258.01:49:34.69#ibcon#read 4, iclass 3, count 2 2006.258.01:49:34.69#ibcon#about to read 5, iclass 3, count 2 2006.258.01:49:34.69#ibcon#read 5, iclass 3, count 2 2006.258.01:49:34.69#ibcon#about to read 6, iclass 3, count 2 2006.258.01:49:34.69#ibcon#read 6, iclass 3, count 2 2006.258.01:49:34.69#ibcon#end of sib2, iclass 3, count 2 2006.258.01:49:34.69#ibcon#*after write, iclass 3, count 2 2006.258.01:49:34.69#ibcon#*before return 0, iclass 3, count 2 2006.258.01:49:34.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:34.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:34.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.01:49:34.69#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:34.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:34.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:34.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:34.81#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:49:34.81#ibcon#first serial, iclass 3, count 0 2006.258.01:49:34.81#ibcon#enter sib2, iclass 3, count 0 2006.258.01:49:34.81#ibcon#flushed, iclass 3, count 0 2006.258.01:49:34.81#ibcon#about to write, iclass 3, count 0 2006.258.01:49:34.81#ibcon#wrote, iclass 3, count 0 2006.258.01:49:34.81#ibcon#about to read 3, iclass 3, count 0 2006.258.01:49:34.83#ibcon#read 3, iclass 3, count 0 2006.258.01:49:34.83#ibcon#about to read 4, iclass 3, count 0 2006.258.01:49:34.83#ibcon#read 4, iclass 3, count 0 2006.258.01:49:34.83#ibcon#about to read 5, iclass 3, count 0 2006.258.01:49:34.83#ibcon#read 5, iclass 3, count 0 2006.258.01:49:34.83#ibcon#about to read 6, iclass 3, count 0 2006.258.01:49:34.83#ibcon#read 6, iclass 3, count 0 2006.258.01:49:34.83#ibcon#end of sib2, iclass 3, count 0 2006.258.01:49:34.83#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:49:34.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:49:34.83#ibcon#[25=USB\r\n] 2006.258.01:49:34.83#ibcon#*before write, iclass 3, count 0 2006.258.01:49:34.83#ibcon#enter sib2, iclass 3, count 0 2006.258.01:49:34.83#ibcon#flushed, iclass 3, count 0 2006.258.01:49:34.83#ibcon#about to write, iclass 3, count 0 2006.258.01:49:34.83#ibcon#wrote, iclass 3, count 0 2006.258.01:49:34.83#ibcon#about to read 3, iclass 3, count 0 2006.258.01:49:34.86#ibcon#read 3, iclass 3, count 0 2006.258.01:49:34.86#ibcon#about to read 4, iclass 3, count 0 2006.258.01:49:34.86#ibcon#read 4, iclass 3, count 0 2006.258.01:49:34.86#ibcon#about to read 5, iclass 3, count 0 2006.258.01:49:34.86#ibcon#read 5, iclass 3, count 0 2006.258.01:49:34.86#ibcon#about to read 6, iclass 3, count 0 2006.258.01:49:34.86#ibcon#read 6, iclass 3, count 0 2006.258.01:49:34.86#ibcon#end of sib2, iclass 3, count 0 2006.258.01:49:34.86#ibcon#*after write, iclass 3, count 0 2006.258.01:49:34.86#ibcon#*before return 0, iclass 3, count 0 2006.258.01:49:34.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:34.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:34.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:49:34.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:49:34.86$vck44/vblo=1,629.99 2006.258.01:49:34.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.01:49:34.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.01:49:34.86#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:34.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:34.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:34.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:34.86#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:49:34.86#ibcon#first serial, iclass 5, count 0 2006.258.01:49:34.86#ibcon#enter sib2, iclass 5, count 0 2006.258.01:49:34.86#ibcon#flushed, iclass 5, count 0 2006.258.01:49:34.86#ibcon#about to write, iclass 5, count 0 2006.258.01:49:34.86#ibcon#wrote, iclass 5, count 0 2006.258.01:49:34.86#ibcon#about to read 3, iclass 5, count 0 2006.258.01:49:34.88#ibcon#read 3, iclass 5, count 0 2006.258.01:49:34.88#ibcon#about to read 4, iclass 5, count 0 2006.258.01:49:34.88#ibcon#read 4, iclass 5, count 0 2006.258.01:49:34.88#ibcon#about to read 5, iclass 5, count 0 2006.258.01:49:34.88#ibcon#read 5, iclass 5, count 0 2006.258.01:49:34.88#ibcon#about to read 6, iclass 5, count 0 2006.258.01:49:34.88#ibcon#read 6, iclass 5, count 0 2006.258.01:49:34.88#ibcon#end of sib2, iclass 5, count 0 2006.258.01:49:34.88#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:49:34.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:49:34.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.258.01:49:34.88#ibcon#*before write, iclass 5, count 0 2006.258.01:49:34.88#ibcon#enter sib2, iclass 5, count 0 2006.258.01:49:34.88#ibcon#flushed, iclass 5, count 0 2006.258.01:49:34.88#ibcon#about to write, iclass 5, count 0 2006.258.01:49:34.88#ibcon#wrote, iclass 5, count 0 2006.258.01:49:34.88#ibcon#about to read 3, iclass 5, count 0 2006.258.01:49:34.92#ibcon#read 3, iclass 5, count 0 2006.258.01:49:34.92#ibcon#about to read 4, iclass 5, count 0 2006.258.01:49:34.92#ibcon#read 4, iclass 5, count 0 2006.258.01:49:34.92#ibcon#about to read 5, iclass 5, count 0 2006.258.01:49:34.92#ibcon#read 5, iclass 5, count 0 2006.258.01:49:34.92#ibcon#about to read 6, iclass 5, count 0 2006.258.01:49:34.92#ibcon#read 6, iclass 5, count 0 2006.258.01:49:34.92#ibcon#end of sib2, iclass 5, count 0 2006.258.01:49:34.92#ibcon#*after write, iclass 5, count 0 2006.258.01:49:34.92#ibcon#*before return 0, iclass 5, count 0 2006.258.01:49:34.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:34.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:34.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:49:34.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:49:34.92$vck44/vb=1,4 2006.258.01:49:34.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.258.01:49:34.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.258.01:49:34.92#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:34.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:49:34.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:49:34.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:49:34.92#ibcon#enter wrdev, iclass 7, count 2 2006.258.01:49:34.92#ibcon#first serial, iclass 7, count 2 2006.258.01:49:34.92#ibcon#enter sib2, iclass 7, count 2 2006.258.01:49:34.92#ibcon#flushed, iclass 7, count 2 2006.258.01:49:34.92#ibcon#about to write, iclass 7, count 2 2006.258.01:49:34.92#ibcon#wrote, iclass 7, count 2 2006.258.01:49:34.92#ibcon#about to read 3, iclass 7, count 2 2006.258.01:49:34.94#ibcon#read 3, iclass 7, count 2 2006.258.01:49:34.94#ibcon#about to read 4, iclass 7, count 2 2006.258.01:49:34.94#ibcon#read 4, iclass 7, count 2 2006.258.01:49:34.94#ibcon#about to read 5, iclass 7, count 2 2006.258.01:49:34.94#ibcon#read 5, iclass 7, count 2 2006.258.01:49:34.94#ibcon#about to read 6, iclass 7, count 2 2006.258.01:49:34.94#ibcon#read 6, iclass 7, count 2 2006.258.01:49:34.94#ibcon#end of sib2, iclass 7, count 2 2006.258.01:49:34.94#ibcon#*mode == 0, iclass 7, count 2 2006.258.01:49:34.94#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.258.01:49:34.94#ibcon#[27=AT01-04\r\n] 2006.258.01:49:34.94#ibcon#*before write, iclass 7, count 2 2006.258.01:49:34.94#ibcon#enter sib2, iclass 7, count 2 2006.258.01:49:34.94#ibcon#flushed, iclass 7, count 2 2006.258.01:49:34.94#ibcon#about to write, iclass 7, count 2 2006.258.01:49:34.94#ibcon#wrote, iclass 7, count 2 2006.258.01:49:34.94#ibcon#about to read 3, iclass 7, count 2 2006.258.01:49:34.97#ibcon#read 3, iclass 7, count 2 2006.258.01:49:34.97#ibcon#about to read 4, iclass 7, count 2 2006.258.01:49:34.97#ibcon#read 4, iclass 7, count 2 2006.258.01:49:34.97#ibcon#about to read 5, iclass 7, count 2 2006.258.01:49:34.97#ibcon#read 5, iclass 7, count 2 2006.258.01:49:34.97#ibcon#about to read 6, iclass 7, count 2 2006.258.01:49:34.97#ibcon#read 6, iclass 7, count 2 2006.258.01:49:34.97#ibcon#end of sib2, iclass 7, count 2 2006.258.01:49:34.97#ibcon#*after write, iclass 7, count 2 2006.258.01:49:34.97#ibcon#*before return 0, iclass 7, count 2 2006.258.01:49:34.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:49:34.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.258.01:49:34.97#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.258.01:49:34.97#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:34.97#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:49:35.09#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:49:35.09#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:49:35.09#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:49:35.09#ibcon#first serial, iclass 7, count 0 2006.258.01:49:35.09#ibcon#enter sib2, iclass 7, count 0 2006.258.01:49:35.09#ibcon#flushed, iclass 7, count 0 2006.258.01:49:35.09#ibcon#about to write, iclass 7, count 0 2006.258.01:49:35.09#ibcon#wrote, iclass 7, count 0 2006.258.01:49:35.09#ibcon#about to read 3, iclass 7, count 0 2006.258.01:49:35.11#ibcon#read 3, iclass 7, count 0 2006.258.01:49:35.11#ibcon#about to read 4, iclass 7, count 0 2006.258.01:49:35.11#ibcon#read 4, iclass 7, count 0 2006.258.01:49:35.11#ibcon#about to read 5, iclass 7, count 0 2006.258.01:49:35.11#ibcon#read 5, iclass 7, count 0 2006.258.01:49:35.11#ibcon#about to read 6, iclass 7, count 0 2006.258.01:49:35.11#ibcon#read 6, iclass 7, count 0 2006.258.01:49:35.11#ibcon#end of sib2, iclass 7, count 0 2006.258.01:49:35.11#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:49:35.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:49:35.11#ibcon#[27=USB\r\n] 2006.258.01:49:35.11#ibcon#*before write, iclass 7, count 0 2006.258.01:49:35.11#ibcon#enter sib2, iclass 7, count 0 2006.258.01:49:35.11#ibcon#flushed, iclass 7, count 0 2006.258.01:49:35.11#ibcon#about to write, iclass 7, count 0 2006.258.01:49:35.11#ibcon#wrote, iclass 7, count 0 2006.258.01:49:35.11#ibcon#about to read 3, iclass 7, count 0 2006.258.01:49:35.14#ibcon#read 3, iclass 7, count 0 2006.258.01:49:35.14#ibcon#about to read 4, iclass 7, count 0 2006.258.01:49:35.14#ibcon#read 4, iclass 7, count 0 2006.258.01:49:35.14#ibcon#about to read 5, iclass 7, count 0 2006.258.01:49:35.14#ibcon#read 5, iclass 7, count 0 2006.258.01:49:35.14#ibcon#about to read 6, iclass 7, count 0 2006.258.01:49:35.14#ibcon#read 6, iclass 7, count 0 2006.258.01:49:35.14#ibcon#end of sib2, iclass 7, count 0 2006.258.01:49:35.14#ibcon#*after write, iclass 7, count 0 2006.258.01:49:35.14#ibcon#*before return 0, iclass 7, count 0 2006.258.01:49:35.14#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:49:35.14#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.258.01:49:35.14#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:49:35.14#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:49:35.14$vck44/vblo=2,634.99 2006.258.01:49:35.14#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.258.01:49:35.14#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.258.01:49:35.14#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:35.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:35.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:35.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:35.14#ibcon#enter wrdev, iclass 11, count 0 2006.258.01:49:35.14#ibcon#first serial, iclass 11, count 0 2006.258.01:49:35.14#ibcon#enter sib2, iclass 11, count 0 2006.258.01:49:35.14#ibcon#flushed, iclass 11, count 0 2006.258.01:49:35.14#ibcon#about to write, iclass 11, count 0 2006.258.01:49:35.14#ibcon#wrote, iclass 11, count 0 2006.258.01:49:35.14#ibcon#about to read 3, iclass 11, count 0 2006.258.01:49:35.16#ibcon#read 3, iclass 11, count 0 2006.258.01:49:35.16#ibcon#about to read 4, iclass 11, count 0 2006.258.01:49:35.16#ibcon#read 4, iclass 11, count 0 2006.258.01:49:35.16#ibcon#about to read 5, iclass 11, count 0 2006.258.01:49:35.16#ibcon#read 5, iclass 11, count 0 2006.258.01:49:35.16#ibcon#about to read 6, iclass 11, count 0 2006.258.01:49:35.16#ibcon#read 6, iclass 11, count 0 2006.258.01:49:35.16#ibcon#end of sib2, iclass 11, count 0 2006.258.01:49:35.16#ibcon#*mode == 0, iclass 11, count 0 2006.258.01:49:35.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.258.01:49:35.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.258.01:49:35.16#ibcon#*before write, iclass 11, count 0 2006.258.01:49:35.16#ibcon#enter sib2, iclass 11, count 0 2006.258.01:49:35.16#ibcon#flushed, iclass 11, count 0 2006.258.01:49:35.16#ibcon#about to write, iclass 11, count 0 2006.258.01:49:35.16#ibcon#wrote, iclass 11, count 0 2006.258.01:49:35.16#ibcon#about to read 3, iclass 11, count 0 2006.258.01:49:35.20#ibcon#read 3, iclass 11, count 0 2006.258.01:49:35.20#ibcon#about to read 4, iclass 11, count 0 2006.258.01:49:35.20#ibcon#read 4, iclass 11, count 0 2006.258.01:49:35.20#ibcon#about to read 5, iclass 11, count 0 2006.258.01:49:35.20#ibcon#read 5, iclass 11, count 0 2006.258.01:49:35.20#ibcon#about to read 6, iclass 11, count 0 2006.258.01:49:35.20#ibcon#read 6, iclass 11, count 0 2006.258.01:49:35.20#ibcon#end of sib2, iclass 11, count 0 2006.258.01:49:35.20#ibcon#*after write, iclass 11, count 0 2006.258.01:49:35.20#ibcon#*before return 0, iclass 11, count 0 2006.258.01:49:35.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:35.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.258.01:49:35.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.258.01:49:35.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.258.01:49:35.20$vck44/vb=2,5 2006.258.01:49:35.20#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.258.01:49:35.20#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.258.01:49:35.20#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:35.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:35.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:35.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:35.26#ibcon#enter wrdev, iclass 13, count 2 2006.258.01:49:35.26#ibcon#first serial, iclass 13, count 2 2006.258.01:49:35.26#ibcon#enter sib2, iclass 13, count 2 2006.258.01:49:35.26#ibcon#flushed, iclass 13, count 2 2006.258.01:49:35.26#ibcon#about to write, iclass 13, count 2 2006.258.01:49:35.26#ibcon#wrote, iclass 13, count 2 2006.258.01:49:35.26#ibcon#about to read 3, iclass 13, count 2 2006.258.01:49:35.28#ibcon#read 3, iclass 13, count 2 2006.258.01:49:35.28#ibcon#about to read 4, iclass 13, count 2 2006.258.01:49:35.28#ibcon#read 4, iclass 13, count 2 2006.258.01:49:35.28#ibcon#about to read 5, iclass 13, count 2 2006.258.01:49:35.28#ibcon#read 5, iclass 13, count 2 2006.258.01:49:35.28#ibcon#about to read 6, iclass 13, count 2 2006.258.01:49:35.28#ibcon#read 6, iclass 13, count 2 2006.258.01:49:35.28#ibcon#end of sib2, iclass 13, count 2 2006.258.01:49:35.28#ibcon#*mode == 0, iclass 13, count 2 2006.258.01:49:35.28#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.258.01:49:35.28#ibcon#[27=AT02-05\r\n] 2006.258.01:49:35.28#ibcon#*before write, iclass 13, count 2 2006.258.01:49:35.28#ibcon#enter sib2, iclass 13, count 2 2006.258.01:49:35.28#ibcon#flushed, iclass 13, count 2 2006.258.01:49:35.28#ibcon#about to write, iclass 13, count 2 2006.258.01:49:35.28#ibcon#wrote, iclass 13, count 2 2006.258.01:49:35.28#ibcon#about to read 3, iclass 13, count 2 2006.258.01:49:35.31#ibcon#read 3, iclass 13, count 2 2006.258.01:49:35.31#ibcon#about to read 4, iclass 13, count 2 2006.258.01:49:35.31#ibcon#read 4, iclass 13, count 2 2006.258.01:49:35.31#ibcon#about to read 5, iclass 13, count 2 2006.258.01:49:35.31#ibcon#read 5, iclass 13, count 2 2006.258.01:49:35.31#ibcon#about to read 6, iclass 13, count 2 2006.258.01:49:35.31#ibcon#read 6, iclass 13, count 2 2006.258.01:49:35.31#ibcon#end of sib2, iclass 13, count 2 2006.258.01:49:35.31#ibcon#*after write, iclass 13, count 2 2006.258.01:49:35.31#ibcon#*before return 0, iclass 13, count 2 2006.258.01:49:35.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:35.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.258.01:49:35.31#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.258.01:49:35.31#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:35.31#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:35.43#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:35.43#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:35.43#ibcon#enter wrdev, iclass 13, count 0 2006.258.01:49:35.43#ibcon#first serial, iclass 13, count 0 2006.258.01:49:35.43#ibcon#enter sib2, iclass 13, count 0 2006.258.01:49:35.43#ibcon#flushed, iclass 13, count 0 2006.258.01:49:35.43#ibcon#about to write, iclass 13, count 0 2006.258.01:49:35.43#ibcon#wrote, iclass 13, count 0 2006.258.01:49:35.43#ibcon#about to read 3, iclass 13, count 0 2006.258.01:49:35.45#ibcon#read 3, iclass 13, count 0 2006.258.01:49:35.45#ibcon#about to read 4, iclass 13, count 0 2006.258.01:49:35.45#ibcon#read 4, iclass 13, count 0 2006.258.01:49:35.45#ibcon#about to read 5, iclass 13, count 0 2006.258.01:49:35.45#ibcon#read 5, iclass 13, count 0 2006.258.01:49:35.45#ibcon#about to read 6, iclass 13, count 0 2006.258.01:49:35.45#ibcon#read 6, iclass 13, count 0 2006.258.01:49:35.45#ibcon#end of sib2, iclass 13, count 0 2006.258.01:49:35.45#ibcon#*mode == 0, iclass 13, count 0 2006.258.01:49:35.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.258.01:49:35.45#ibcon#[27=USB\r\n] 2006.258.01:49:35.45#ibcon#*before write, iclass 13, count 0 2006.258.01:49:35.45#ibcon#enter sib2, iclass 13, count 0 2006.258.01:49:35.45#ibcon#flushed, iclass 13, count 0 2006.258.01:49:35.45#ibcon#about to write, iclass 13, count 0 2006.258.01:49:35.45#ibcon#wrote, iclass 13, count 0 2006.258.01:49:35.45#ibcon#about to read 3, iclass 13, count 0 2006.258.01:49:35.48#ibcon#read 3, iclass 13, count 0 2006.258.01:49:35.48#ibcon#about to read 4, iclass 13, count 0 2006.258.01:49:35.48#ibcon#read 4, iclass 13, count 0 2006.258.01:49:35.48#ibcon#about to read 5, iclass 13, count 0 2006.258.01:49:35.48#ibcon#read 5, iclass 13, count 0 2006.258.01:49:35.48#ibcon#about to read 6, iclass 13, count 0 2006.258.01:49:35.48#ibcon#read 6, iclass 13, count 0 2006.258.01:49:35.48#ibcon#end of sib2, iclass 13, count 0 2006.258.01:49:35.48#ibcon#*after write, iclass 13, count 0 2006.258.01:49:35.48#ibcon#*before return 0, iclass 13, count 0 2006.258.01:49:35.48#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:35.48#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.258.01:49:35.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.258.01:49:35.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.258.01:49:35.48$vck44/vblo=3,649.99 2006.258.01:49:35.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.258.01:49:35.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.258.01:49:35.48#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:35.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:35.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:35.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:35.48#ibcon#enter wrdev, iclass 15, count 0 2006.258.01:49:35.48#ibcon#first serial, iclass 15, count 0 2006.258.01:49:35.48#ibcon#enter sib2, iclass 15, count 0 2006.258.01:49:35.48#ibcon#flushed, iclass 15, count 0 2006.258.01:49:35.48#ibcon#about to write, iclass 15, count 0 2006.258.01:49:35.48#ibcon#wrote, iclass 15, count 0 2006.258.01:49:35.48#ibcon#about to read 3, iclass 15, count 0 2006.258.01:49:35.50#ibcon#read 3, iclass 15, count 0 2006.258.01:49:35.50#ibcon#about to read 4, iclass 15, count 0 2006.258.01:49:35.50#ibcon#read 4, iclass 15, count 0 2006.258.01:49:35.50#ibcon#about to read 5, iclass 15, count 0 2006.258.01:49:35.50#ibcon#read 5, iclass 15, count 0 2006.258.01:49:35.50#ibcon#about to read 6, iclass 15, count 0 2006.258.01:49:35.50#ibcon#read 6, iclass 15, count 0 2006.258.01:49:35.50#ibcon#end of sib2, iclass 15, count 0 2006.258.01:49:35.50#ibcon#*mode == 0, iclass 15, count 0 2006.258.01:49:35.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.258.01:49:35.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.258.01:49:35.50#ibcon#*before write, iclass 15, count 0 2006.258.01:49:35.50#ibcon#enter sib2, iclass 15, count 0 2006.258.01:49:35.50#ibcon#flushed, iclass 15, count 0 2006.258.01:49:35.50#ibcon#about to write, iclass 15, count 0 2006.258.01:49:35.50#ibcon#wrote, iclass 15, count 0 2006.258.01:49:35.50#ibcon#about to read 3, iclass 15, count 0 2006.258.01:49:35.54#ibcon#read 3, iclass 15, count 0 2006.258.01:49:35.54#ibcon#about to read 4, iclass 15, count 0 2006.258.01:49:35.54#ibcon#read 4, iclass 15, count 0 2006.258.01:49:35.54#ibcon#about to read 5, iclass 15, count 0 2006.258.01:49:35.54#ibcon#read 5, iclass 15, count 0 2006.258.01:49:35.54#ibcon#about to read 6, iclass 15, count 0 2006.258.01:49:35.54#ibcon#read 6, iclass 15, count 0 2006.258.01:49:35.54#ibcon#end of sib2, iclass 15, count 0 2006.258.01:49:35.54#ibcon#*after write, iclass 15, count 0 2006.258.01:49:35.54#ibcon#*before return 0, iclass 15, count 0 2006.258.01:49:35.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:35.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.258.01:49:35.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.258.01:49:35.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.258.01:49:35.54$vck44/vb=3,4 2006.258.01:49:35.54#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.258.01:49:35.54#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.258.01:49:35.54#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:35.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:35.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:35.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:35.60#ibcon#enter wrdev, iclass 17, count 2 2006.258.01:49:35.60#ibcon#first serial, iclass 17, count 2 2006.258.01:49:35.60#ibcon#enter sib2, iclass 17, count 2 2006.258.01:49:35.60#ibcon#flushed, iclass 17, count 2 2006.258.01:49:35.60#ibcon#about to write, iclass 17, count 2 2006.258.01:49:35.60#ibcon#wrote, iclass 17, count 2 2006.258.01:49:35.60#ibcon#about to read 3, iclass 17, count 2 2006.258.01:49:35.62#ibcon#read 3, iclass 17, count 2 2006.258.01:49:35.62#ibcon#about to read 4, iclass 17, count 2 2006.258.01:49:35.62#ibcon#read 4, iclass 17, count 2 2006.258.01:49:35.62#ibcon#about to read 5, iclass 17, count 2 2006.258.01:49:35.62#ibcon#read 5, iclass 17, count 2 2006.258.01:49:35.62#ibcon#about to read 6, iclass 17, count 2 2006.258.01:49:35.62#ibcon#read 6, iclass 17, count 2 2006.258.01:49:35.62#ibcon#end of sib2, iclass 17, count 2 2006.258.01:49:35.62#ibcon#*mode == 0, iclass 17, count 2 2006.258.01:49:35.62#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.258.01:49:35.62#ibcon#[27=AT03-04\r\n] 2006.258.01:49:35.62#ibcon#*before write, iclass 17, count 2 2006.258.01:49:35.62#ibcon#enter sib2, iclass 17, count 2 2006.258.01:49:35.62#ibcon#flushed, iclass 17, count 2 2006.258.01:49:35.62#ibcon#about to write, iclass 17, count 2 2006.258.01:49:35.62#ibcon#wrote, iclass 17, count 2 2006.258.01:49:35.62#ibcon#about to read 3, iclass 17, count 2 2006.258.01:49:35.65#ibcon#read 3, iclass 17, count 2 2006.258.01:49:35.65#ibcon#about to read 4, iclass 17, count 2 2006.258.01:49:35.65#ibcon#read 4, iclass 17, count 2 2006.258.01:49:35.65#ibcon#about to read 5, iclass 17, count 2 2006.258.01:49:35.65#ibcon#read 5, iclass 17, count 2 2006.258.01:49:35.65#ibcon#about to read 6, iclass 17, count 2 2006.258.01:49:35.65#ibcon#read 6, iclass 17, count 2 2006.258.01:49:35.65#ibcon#end of sib2, iclass 17, count 2 2006.258.01:49:35.65#ibcon#*after write, iclass 17, count 2 2006.258.01:49:35.65#ibcon#*before return 0, iclass 17, count 2 2006.258.01:49:35.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:35.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.258.01:49:35.65#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.258.01:49:35.65#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:35.65#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:35.77#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:35.77#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:35.77#ibcon#enter wrdev, iclass 17, count 0 2006.258.01:49:35.77#ibcon#first serial, iclass 17, count 0 2006.258.01:49:35.77#ibcon#enter sib2, iclass 17, count 0 2006.258.01:49:35.77#ibcon#flushed, iclass 17, count 0 2006.258.01:49:35.77#ibcon#about to write, iclass 17, count 0 2006.258.01:49:35.77#ibcon#wrote, iclass 17, count 0 2006.258.01:49:35.77#ibcon#about to read 3, iclass 17, count 0 2006.258.01:49:35.79#ibcon#read 3, iclass 17, count 0 2006.258.01:49:35.79#ibcon#about to read 4, iclass 17, count 0 2006.258.01:49:35.79#ibcon#read 4, iclass 17, count 0 2006.258.01:49:35.79#ibcon#about to read 5, iclass 17, count 0 2006.258.01:49:35.79#ibcon#read 5, iclass 17, count 0 2006.258.01:49:35.79#ibcon#about to read 6, iclass 17, count 0 2006.258.01:49:35.79#ibcon#read 6, iclass 17, count 0 2006.258.01:49:35.79#ibcon#end of sib2, iclass 17, count 0 2006.258.01:49:35.79#ibcon#*mode == 0, iclass 17, count 0 2006.258.01:49:35.79#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.258.01:49:35.79#ibcon#[27=USB\r\n] 2006.258.01:49:35.79#ibcon#*before write, iclass 17, count 0 2006.258.01:49:35.79#ibcon#enter sib2, iclass 17, count 0 2006.258.01:49:35.79#ibcon#flushed, iclass 17, count 0 2006.258.01:49:35.79#ibcon#about to write, iclass 17, count 0 2006.258.01:49:35.79#ibcon#wrote, iclass 17, count 0 2006.258.01:49:35.79#ibcon#about to read 3, iclass 17, count 0 2006.258.01:49:35.82#ibcon#read 3, iclass 17, count 0 2006.258.01:49:35.82#ibcon#about to read 4, iclass 17, count 0 2006.258.01:49:35.82#ibcon#read 4, iclass 17, count 0 2006.258.01:49:35.82#ibcon#about to read 5, iclass 17, count 0 2006.258.01:49:35.82#ibcon#read 5, iclass 17, count 0 2006.258.01:49:35.82#ibcon#about to read 6, iclass 17, count 0 2006.258.01:49:35.82#ibcon#read 6, iclass 17, count 0 2006.258.01:49:35.82#ibcon#end of sib2, iclass 17, count 0 2006.258.01:49:35.82#ibcon#*after write, iclass 17, count 0 2006.258.01:49:35.82#ibcon#*before return 0, iclass 17, count 0 2006.258.01:49:35.82#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:35.82#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.258.01:49:35.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.258.01:49:35.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.258.01:49:35.82$vck44/vblo=4,679.99 2006.258.01:49:35.82#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.258.01:49:35.82#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.258.01:49:35.82#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:35.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:49:35.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:49:35.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:49:35.82#ibcon#enter wrdev, iclass 20, count 0 2006.258.01:49:35.82#ibcon#first serial, iclass 20, count 0 2006.258.01:49:35.82#ibcon#enter sib2, iclass 20, count 0 2006.258.01:49:35.82#ibcon#flushed, iclass 20, count 0 2006.258.01:49:35.82#ibcon#about to write, iclass 20, count 0 2006.258.01:49:35.82#ibcon#wrote, iclass 20, count 0 2006.258.01:49:35.82#ibcon#about to read 3, iclass 20, count 0 2006.258.01:49:35.84#ibcon#read 3, iclass 20, count 0 2006.258.01:49:35.84#ibcon#about to read 4, iclass 20, count 0 2006.258.01:49:35.84#ibcon#read 4, iclass 20, count 0 2006.258.01:49:35.84#ibcon#about to read 5, iclass 20, count 0 2006.258.01:49:35.84#ibcon#read 5, iclass 20, count 0 2006.258.01:49:35.84#ibcon#about to read 6, iclass 20, count 0 2006.258.01:49:35.84#ibcon#read 6, iclass 20, count 0 2006.258.01:49:35.84#ibcon#end of sib2, iclass 20, count 0 2006.258.01:49:35.84#ibcon#*mode == 0, iclass 20, count 0 2006.258.01:49:35.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.258.01:49:35.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.258.01:49:35.84#ibcon#*before write, iclass 20, count 0 2006.258.01:49:35.84#ibcon#enter sib2, iclass 20, count 0 2006.258.01:49:35.84#ibcon#flushed, iclass 20, count 0 2006.258.01:49:35.84#ibcon#about to write, iclass 20, count 0 2006.258.01:49:35.84#ibcon#wrote, iclass 20, count 0 2006.258.01:49:35.84#ibcon#about to read 3, iclass 20, count 0 2006.258.01:49:35.84#abcon#<5=/03 3.1 8.2 23.47 731015.9\r\n> 2006.258.01:49:35.86#abcon#{5=INTERFACE CLEAR} 2006.258.01:49:35.88#ibcon#read 3, iclass 20, count 0 2006.258.01:49:35.88#ibcon#about to read 4, iclass 20, count 0 2006.258.01:49:35.88#ibcon#read 4, iclass 20, count 0 2006.258.01:49:35.88#ibcon#about to read 5, iclass 20, count 0 2006.258.01:49:35.88#ibcon#read 5, iclass 20, count 0 2006.258.01:49:35.88#ibcon#about to read 6, iclass 20, count 0 2006.258.01:49:35.88#ibcon#read 6, iclass 20, count 0 2006.258.01:49:35.88#ibcon#end of sib2, iclass 20, count 0 2006.258.01:49:35.88#ibcon#*after write, iclass 20, count 0 2006.258.01:49:35.88#ibcon#*before return 0, iclass 20, count 0 2006.258.01:49:35.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:49:35.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.258.01:49:35.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.258.01:49:35.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.258.01:49:35.88$vck44/vb=4,5 2006.258.01:49:35.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.258.01:49:35.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.258.01:49:35.88#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:35.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:49:35.92#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:49:35.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:49:35.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:49:35.94#ibcon#enter wrdev, iclass 24, count 2 2006.258.01:49:35.94#ibcon#first serial, iclass 24, count 2 2006.258.01:49:35.94#ibcon#enter sib2, iclass 24, count 2 2006.258.01:49:35.94#ibcon#flushed, iclass 24, count 2 2006.258.01:49:35.94#ibcon#about to write, iclass 24, count 2 2006.258.01:49:35.94#ibcon#wrote, iclass 24, count 2 2006.258.01:49:35.94#ibcon#about to read 3, iclass 24, count 2 2006.258.01:49:35.96#ibcon#read 3, iclass 24, count 2 2006.258.01:49:35.96#ibcon#about to read 4, iclass 24, count 2 2006.258.01:49:35.96#ibcon#read 4, iclass 24, count 2 2006.258.01:49:35.96#ibcon#about to read 5, iclass 24, count 2 2006.258.01:49:35.96#ibcon#read 5, iclass 24, count 2 2006.258.01:49:35.96#ibcon#about to read 6, iclass 24, count 2 2006.258.01:49:35.96#ibcon#read 6, iclass 24, count 2 2006.258.01:49:35.96#ibcon#end of sib2, iclass 24, count 2 2006.258.01:49:35.96#ibcon#*mode == 0, iclass 24, count 2 2006.258.01:49:35.96#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.258.01:49:35.96#ibcon#[27=AT04-05\r\n] 2006.258.01:49:35.96#ibcon#*before write, iclass 24, count 2 2006.258.01:49:35.96#ibcon#enter sib2, iclass 24, count 2 2006.258.01:49:35.96#ibcon#flushed, iclass 24, count 2 2006.258.01:49:35.96#ibcon#about to write, iclass 24, count 2 2006.258.01:49:35.96#ibcon#wrote, iclass 24, count 2 2006.258.01:49:35.96#ibcon#about to read 3, iclass 24, count 2 2006.258.01:49:35.99#ibcon#read 3, iclass 24, count 2 2006.258.01:49:35.99#ibcon#about to read 4, iclass 24, count 2 2006.258.01:49:35.99#ibcon#read 4, iclass 24, count 2 2006.258.01:49:35.99#ibcon#about to read 5, iclass 24, count 2 2006.258.01:49:35.99#ibcon#read 5, iclass 24, count 2 2006.258.01:49:35.99#ibcon#about to read 6, iclass 24, count 2 2006.258.01:49:35.99#ibcon#read 6, iclass 24, count 2 2006.258.01:49:35.99#ibcon#end of sib2, iclass 24, count 2 2006.258.01:49:35.99#ibcon#*after write, iclass 24, count 2 2006.258.01:49:35.99#ibcon#*before return 0, iclass 24, count 2 2006.258.01:49:35.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:49:35.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.258.01:49:35.99#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.258.01:49:35.99#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:35.99#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:49:36.11#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:49:36.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:49:36.11#ibcon#enter wrdev, iclass 24, count 0 2006.258.01:49:36.11#ibcon#first serial, iclass 24, count 0 2006.258.01:49:36.11#ibcon#enter sib2, iclass 24, count 0 2006.258.01:49:36.11#ibcon#flushed, iclass 24, count 0 2006.258.01:49:36.11#ibcon#about to write, iclass 24, count 0 2006.258.01:49:36.11#ibcon#wrote, iclass 24, count 0 2006.258.01:49:36.11#ibcon#about to read 3, iclass 24, count 0 2006.258.01:49:36.13#ibcon#read 3, iclass 24, count 0 2006.258.01:49:36.13#ibcon#about to read 4, iclass 24, count 0 2006.258.01:49:36.13#ibcon#read 4, iclass 24, count 0 2006.258.01:49:36.13#ibcon#about to read 5, iclass 24, count 0 2006.258.01:49:36.13#ibcon#read 5, iclass 24, count 0 2006.258.01:49:36.13#ibcon#about to read 6, iclass 24, count 0 2006.258.01:49:36.13#ibcon#read 6, iclass 24, count 0 2006.258.01:49:36.13#ibcon#end of sib2, iclass 24, count 0 2006.258.01:49:36.13#ibcon#*mode == 0, iclass 24, count 0 2006.258.01:49:36.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.258.01:49:36.13#ibcon#[27=USB\r\n] 2006.258.01:49:36.13#ibcon#*before write, iclass 24, count 0 2006.258.01:49:36.13#ibcon#enter sib2, iclass 24, count 0 2006.258.01:49:36.13#ibcon#flushed, iclass 24, count 0 2006.258.01:49:36.13#ibcon#about to write, iclass 24, count 0 2006.258.01:49:36.13#ibcon#wrote, iclass 24, count 0 2006.258.01:49:36.13#ibcon#about to read 3, iclass 24, count 0 2006.258.01:49:36.16#ibcon#read 3, iclass 24, count 0 2006.258.01:49:36.16#ibcon#about to read 4, iclass 24, count 0 2006.258.01:49:36.16#ibcon#read 4, iclass 24, count 0 2006.258.01:49:36.16#ibcon#about to read 5, iclass 24, count 0 2006.258.01:49:36.16#ibcon#read 5, iclass 24, count 0 2006.258.01:49:36.16#ibcon#about to read 6, iclass 24, count 0 2006.258.01:49:36.16#ibcon#read 6, iclass 24, count 0 2006.258.01:49:36.16#ibcon#end of sib2, iclass 24, count 0 2006.258.01:49:36.16#ibcon#*after write, iclass 24, count 0 2006.258.01:49:36.16#ibcon#*before return 0, iclass 24, count 0 2006.258.01:49:36.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:49:36.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.258.01:49:36.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.258.01:49:36.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.258.01:49:36.16$vck44/vblo=5,709.99 2006.258.01:49:36.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.258.01:49:36.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.258.01:49:36.16#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:36.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:36.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:36.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:36.16#ibcon#enter wrdev, iclass 27, count 0 2006.258.01:49:36.16#ibcon#first serial, iclass 27, count 0 2006.258.01:49:36.16#ibcon#enter sib2, iclass 27, count 0 2006.258.01:49:36.16#ibcon#flushed, iclass 27, count 0 2006.258.01:49:36.16#ibcon#about to write, iclass 27, count 0 2006.258.01:49:36.16#ibcon#wrote, iclass 27, count 0 2006.258.01:49:36.16#ibcon#about to read 3, iclass 27, count 0 2006.258.01:49:36.18#ibcon#read 3, iclass 27, count 0 2006.258.01:49:36.18#ibcon#about to read 4, iclass 27, count 0 2006.258.01:49:36.18#ibcon#read 4, iclass 27, count 0 2006.258.01:49:36.18#ibcon#about to read 5, iclass 27, count 0 2006.258.01:49:36.18#ibcon#read 5, iclass 27, count 0 2006.258.01:49:36.18#ibcon#about to read 6, iclass 27, count 0 2006.258.01:49:36.18#ibcon#read 6, iclass 27, count 0 2006.258.01:49:36.18#ibcon#end of sib2, iclass 27, count 0 2006.258.01:49:36.18#ibcon#*mode == 0, iclass 27, count 0 2006.258.01:49:36.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.258.01:49:36.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.258.01:49:36.18#ibcon#*before write, iclass 27, count 0 2006.258.01:49:36.18#ibcon#enter sib2, iclass 27, count 0 2006.258.01:49:36.18#ibcon#flushed, iclass 27, count 0 2006.258.01:49:36.18#ibcon#about to write, iclass 27, count 0 2006.258.01:49:36.18#ibcon#wrote, iclass 27, count 0 2006.258.01:49:36.18#ibcon#about to read 3, iclass 27, count 0 2006.258.01:49:36.22#ibcon#read 3, iclass 27, count 0 2006.258.01:49:36.22#ibcon#about to read 4, iclass 27, count 0 2006.258.01:49:36.22#ibcon#read 4, iclass 27, count 0 2006.258.01:49:36.22#ibcon#about to read 5, iclass 27, count 0 2006.258.01:49:36.22#ibcon#read 5, iclass 27, count 0 2006.258.01:49:36.22#ibcon#about to read 6, iclass 27, count 0 2006.258.01:49:36.22#ibcon#read 6, iclass 27, count 0 2006.258.01:49:36.22#ibcon#end of sib2, iclass 27, count 0 2006.258.01:49:36.22#ibcon#*after write, iclass 27, count 0 2006.258.01:49:36.22#ibcon#*before return 0, iclass 27, count 0 2006.258.01:49:36.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:36.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.258.01:49:36.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.258.01:49:36.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.258.01:49:36.22$vck44/vb=5,4 2006.258.01:49:36.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.258.01:49:36.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.258.01:49:36.22#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:36.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:36.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:36.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:36.28#ibcon#enter wrdev, iclass 29, count 2 2006.258.01:49:36.28#ibcon#first serial, iclass 29, count 2 2006.258.01:49:36.28#ibcon#enter sib2, iclass 29, count 2 2006.258.01:49:36.28#ibcon#flushed, iclass 29, count 2 2006.258.01:49:36.28#ibcon#about to write, iclass 29, count 2 2006.258.01:49:36.28#ibcon#wrote, iclass 29, count 2 2006.258.01:49:36.28#ibcon#about to read 3, iclass 29, count 2 2006.258.01:49:36.30#ibcon#read 3, iclass 29, count 2 2006.258.01:49:36.30#ibcon#about to read 4, iclass 29, count 2 2006.258.01:49:36.30#ibcon#read 4, iclass 29, count 2 2006.258.01:49:36.30#ibcon#about to read 5, iclass 29, count 2 2006.258.01:49:36.30#ibcon#read 5, iclass 29, count 2 2006.258.01:49:36.30#ibcon#about to read 6, iclass 29, count 2 2006.258.01:49:36.30#ibcon#read 6, iclass 29, count 2 2006.258.01:49:36.30#ibcon#end of sib2, iclass 29, count 2 2006.258.01:49:36.30#ibcon#*mode == 0, iclass 29, count 2 2006.258.01:49:36.30#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.258.01:49:36.30#ibcon#[27=AT05-04\r\n] 2006.258.01:49:36.30#ibcon#*before write, iclass 29, count 2 2006.258.01:49:36.30#ibcon#enter sib2, iclass 29, count 2 2006.258.01:49:36.30#ibcon#flushed, iclass 29, count 2 2006.258.01:49:36.30#ibcon#about to write, iclass 29, count 2 2006.258.01:49:36.30#ibcon#wrote, iclass 29, count 2 2006.258.01:49:36.30#ibcon#about to read 3, iclass 29, count 2 2006.258.01:49:36.33#ibcon#read 3, iclass 29, count 2 2006.258.01:49:36.33#ibcon#about to read 4, iclass 29, count 2 2006.258.01:49:36.33#ibcon#read 4, iclass 29, count 2 2006.258.01:49:36.33#ibcon#about to read 5, iclass 29, count 2 2006.258.01:49:36.33#ibcon#read 5, iclass 29, count 2 2006.258.01:49:36.33#ibcon#about to read 6, iclass 29, count 2 2006.258.01:49:36.33#ibcon#read 6, iclass 29, count 2 2006.258.01:49:36.33#ibcon#end of sib2, iclass 29, count 2 2006.258.01:49:36.33#ibcon#*after write, iclass 29, count 2 2006.258.01:49:36.33#ibcon#*before return 0, iclass 29, count 2 2006.258.01:49:36.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:36.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.258.01:49:36.33#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.258.01:49:36.33#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:36.33#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:36.45#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:36.45#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:36.45#ibcon#enter wrdev, iclass 29, count 0 2006.258.01:49:36.45#ibcon#first serial, iclass 29, count 0 2006.258.01:49:36.45#ibcon#enter sib2, iclass 29, count 0 2006.258.01:49:36.45#ibcon#flushed, iclass 29, count 0 2006.258.01:49:36.45#ibcon#about to write, iclass 29, count 0 2006.258.01:49:36.45#ibcon#wrote, iclass 29, count 0 2006.258.01:49:36.45#ibcon#about to read 3, iclass 29, count 0 2006.258.01:49:36.47#ibcon#read 3, iclass 29, count 0 2006.258.01:49:36.47#ibcon#about to read 4, iclass 29, count 0 2006.258.01:49:36.47#ibcon#read 4, iclass 29, count 0 2006.258.01:49:36.47#ibcon#about to read 5, iclass 29, count 0 2006.258.01:49:36.47#ibcon#read 5, iclass 29, count 0 2006.258.01:49:36.47#ibcon#about to read 6, iclass 29, count 0 2006.258.01:49:36.47#ibcon#read 6, iclass 29, count 0 2006.258.01:49:36.47#ibcon#end of sib2, iclass 29, count 0 2006.258.01:49:36.47#ibcon#*mode == 0, iclass 29, count 0 2006.258.01:49:36.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.258.01:49:36.47#ibcon#[27=USB\r\n] 2006.258.01:49:36.47#ibcon#*before write, iclass 29, count 0 2006.258.01:49:36.47#ibcon#enter sib2, iclass 29, count 0 2006.258.01:49:36.47#ibcon#flushed, iclass 29, count 0 2006.258.01:49:36.47#ibcon#about to write, iclass 29, count 0 2006.258.01:49:36.47#ibcon#wrote, iclass 29, count 0 2006.258.01:49:36.47#ibcon#about to read 3, iclass 29, count 0 2006.258.01:49:36.50#ibcon#read 3, iclass 29, count 0 2006.258.01:49:36.50#ibcon#about to read 4, iclass 29, count 0 2006.258.01:49:36.50#ibcon#read 4, iclass 29, count 0 2006.258.01:49:36.50#ibcon#about to read 5, iclass 29, count 0 2006.258.01:49:36.50#ibcon#read 5, iclass 29, count 0 2006.258.01:49:36.50#ibcon#about to read 6, iclass 29, count 0 2006.258.01:49:36.50#ibcon#read 6, iclass 29, count 0 2006.258.01:49:36.50#ibcon#end of sib2, iclass 29, count 0 2006.258.01:49:36.50#ibcon#*after write, iclass 29, count 0 2006.258.01:49:36.50#ibcon#*before return 0, iclass 29, count 0 2006.258.01:49:36.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:36.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.258.01:49:36.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.258.01:49:36.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.258.01:49:36.50$vck44/vblo=6,719.99 2006.258.01:49:36.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.258.01:49:36.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.258.01:49:36.50#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:36.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:36.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:36.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:36.50#ibcon#enter wrdev, iclass 31, count 0 2006.258.01:49:36.50#ibcon#first serial, iclass 31, count 0 2006.258.01:49:36.50#ibcon#enter sib2, iclass 31, count 0 2006.258.01:49:36.50#ibcon#flushed, iclass 31, count 0 2006.258.01:49:36.50#ibcon#about to write, iclass 31, count 0 2006.258.01:49:36.50#ibcon#wrote, iclass 31, count 0 2006.258.01:49:36.50#ibcon#about to read 3, iclass 31, count 0 2006.258.01:49:36.53#ibcon#read 3, iclass 31, count 0 2006.258.01:49:36.53#ibcon#about to read 4, iclass 31, count 0 2006.258.01:49:36.53#ibcon#read 4, iclass 31, count 0 2006.258.01:49:36.53#ibcon#about to read 5, iclass 31, count 0 2006.258.01:49:36.53#ibcon#read 5, iclass 31, count 0 2006.258.01:49:36.53#ibcon#about to read 6, iclass 31, count 0 2006.258.01:49:36.53#ibcon#read 6, iclass 31, count 0 2006.258.01:49:36.53#ibcon#end of sib2, iclass 31, count 0 2006.258.01:49:36.53#ibcon#*mode == 0, iclass 31, count 0 2006.258.01:49:36.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.258.01:49:36.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.258.01:49:36.53#ibcon#*before write, iclass 31, count 0 2006.258.01:49:36.53#ibcon#enter sib2, iclass 31, count 0 2006.258.01:49:36.53#ibcon#flushed, iclass 31, count 0 2006.258.01:49:36.53#ibcon#about to write, iclass 31, count 0 2006.258.01:49:36.53#ibcon#wrote, iclass 31, count 0 2006.258.01:49:36.53#ibcon#about to read 3, iclass 31, count 0 2006.258.01:49:36.58#ibcon#read 3, iclass 31, count 0 2006.258.01:49:36.58#ibcon#about to read 4, iclass 31, count 0 2006.258.01:49:36.58#ibcon#read 4, iclass 31, count 0 2006.258.01:49:36.58#ibcon#about to read 5, iclass 31, count 0 2006.258.01:49:36.58#ibcon#read 5, iclass 31, count 0 2006.258.01:49:36.58#ibcon#about to read 6, iclass 31, count 0 2006.258.01:49:36.58#ibcon#read 6, iclass 31, count 0 2006.258.01:49:36.58#ibcon#end of sib2, iclass 31, count 0 2006.258.01:49:36.58#ibcon#*after write, iclass 31, count 0 2006.258.01:49:36.58#ibcon#*before return 0, iclass 31, count 0 2006.258.01:49:36.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:36.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.258.01:49:36.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.258.01:49:36.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.258.01:49:36.58$vck44/vb=6,4 2006.258.01:49:36.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.258.01:49:36.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.258.01:49:36.58#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:36.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:36.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:36.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:36.62#ibcon#enter wrdev, iclass 33, count 2 2006.258.01:49:36.62#ibcon#first serial, iclass 33, count 2 2006.258.01:49:36.62#ibcon#enter sib2, iclass 33, count 2 2006.258.01:49:36.62#ibcon#flushed, iclass 33, count 2 2006.258.01:49:36.62#ibcon#about to write, iclass 33, count 2 2006.258.01:49:36.62#ibcon#wrote, iclass 33, count 2 2006.258.01:49:36.62#ibcon#about to read 3, iclass 33, count 2 2006.258.01:49:36.64#ibcon#read 3, iclass 33, count 2 2006.258.01:49:36.64#ibcon#about to read 4, iclass 33, count 2 2006.258.01:49:36.64#ibcon#read 4, iclass 33, count 2 2006.258.01:49:36.64#ibcon#about to read 5, iclass 33, count 2 2006.258.01:49:36.64#ibcon#read 5, iclass 33, count 2 2006.258.01:49:36.64#ibcon#about to read 6, iclass 33, count 2 2006.258.01:49:36.64#ibcon#read 6, iclass 33, count 2 2006.258.01:49:36.64#ibcon#end of sib2, iclass 33, count 2 2006.258.01:49:36.64#ibcon#*mode == 0, iclass 33, count 2 2006.258.01:49:36.64#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.258.01:49:36.64#ibcon#[27=AT06-04\r\n] 2006.258.01:49:36.64#ibcon#*before write, iclass 33, count 2 2006.258.01:49:36.64#ibcon#enter sib2, iclass 33, count 2 2006.258.01:49:36.64#ibcon#flushed, iclass 33, count 2 2006.258.01:49:36.64#ibcon#about to write, iclass 33, count 2 2006.258.01:49:36.64#ibcon#wrote, iclass 33, count 2 2006.258.01:49:36.64#ibcon#about to read 3, iclass 33, count 2 2006.258.01:49:36.67#ibcon#read 3, iclass 33, count 2 2006.258.01:49:36.67#ibcon#about to read 4, iclass 33, count 2 2006.258.01:49:36.67#ibcon#read 4, iclass 33, count 2 2006.258.01:49:36.67#ibcon#about to read 5, iclass 33, count 2 2006.258.01:49:36.67#ibcon#read 5, iclass 33, count 2 2006.258.01:49:36.67#ibcon#about to read 6, iclass 33, count 2 2006.258.01:49:36.67#ibcon#read 6, iclass 33, count 2 2006.258.01:49:36.67#ibcon#end of sib2, iclass 33, count 2 2006.258.01:49:36.67#ibcon#*after write, iclass 33, count 2 2006.258.01:49:36.67#ibcon#*before return 0, iclass 33, count 2 2006.258.01:49:36.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:36.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.258.01:49:36.67#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.258.01:49:36.67#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:36.67#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:36.79#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:36.79#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:36.79#ibcon#enter wrdev, iclass 33, count 0 2006.258.01:49:36.79#ibcon#first serial, iclass 33, count 0 2006.258.01:49:36.79#ibcon#enter sib2, iclass 33, count 0 2006.258.01:49:36.79#ibcon#flushed, iclass 33, count 0 2006.258.01:49:36.79#ibcon#about to write, iclass 33, count 0 2006.258.01:49:36.79#ibcon#wrote, iclass 33, count 0 2006.258.01:49:36.79#ibcon#about to read 3, iclass 33, count 0 2006.258.01:49:36.81#ibcon#read 3, iclass 33, count 0 2006.258.01:49:36.81#ibcon#about to read 4, iclass 33, count 0 2006.258.01:49:36.81#ibcon#read 4, iclass 33, count 0 2006.258.01:49:36.81#ibcon#about to read 5, iclass 33, count 0 2006.258.01:49:36.81#ibcon#read 5, iclass 33, count 0 2006.258.01:49:36.81#ibcon#about to read 6, iclass 33, count 0 2006.258.01:49:36.81#ibcon#read 6, iclass 33, count 0 2006.258.01:49:36.81#ibcon#end of sib2, iclass 33, count 0 2006.258.01:49:36.81#ibcon#*mode == 0, iclass 33, count 0 2006.258.01:49:36.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.258.01:49:36.81#ibcon#[27=USB\r\n] 2006.258.01:49:36.81#ibcon#*before write, iclass 33, count 0 2006.258.01:49:36.81#ibcon#enter sib2, iclass 33, count 0 2006.258.01:49:36.81#ibcon#flushed, iclass 33, count 0 2006.258.01:49:36.81#ibcon#about to write, iclass 33, count 0 2006.258.01:49:36.81#ibcon#wrote, iclass 33, count 0 2006.258.01:49:36.81#ibcon#about to read 3, iclass 33, count 0 2006.258.01:49:36.84#ibcon#read 3, iclass 33, count 0 2006.258.01:49:36.84#ibcon#about to read 4, iclass 33, count 0 2006.258.01:49:36.84#ibcon#read 4, iclass 33, count 0 2006.258.01:49:36.84#ibcon#about to read 5, iclass 33, count 0 2006.258.01:49:36.84#ibcon#read 5, iclass 33, count 0 2006.258.01:49:36.84#ibcon#about to read 6, iclass 33, count 0 2006.258.01:49:36.84#ibcon#read 6, iclass 33, count 0 2006.258.01:49:36.84#ibcon#end of sib2, iclass 33, count 0 2006.258.01:49:36.84#ibcon#*after write, iclass 33, count 0 2006.258.01:49:36.84#ibcon#*before return 0, iclass 33, count 0 2006.258.01:49:36.84#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:36.84#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.258.01:49:36.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.258.01:49:36.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.258.01:49:36.84$vck44/vblo=7,734.99 2006.258.01:49:36.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.258.01:49:36.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.258.01:49:36.84#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:36.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:36.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:36.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:36.84#ibcon#enter wrdev, iclass 35, count 0 2006.258.01:49:36.84#ibcon#first serial, iclass 35, count 0 2006.258.01:49:36.84#ibcon#enter sib2, iclass 35, count 0 2006.258.01:49:36.84#ibcon#flushed, iclass 35, count 0 2006.258.01:49:36.84#ibcon#about to write, iclass 35, count 0 2006.258.01:49:36.84#ibcon#wrote, iclass 35, count 0 2006.258.01:49:36.84#ibcon#about to read 3, iclass 35, count 0 2006.258.01:49:36.86#ibcon#read 3, iclass 35, count 0 2006.258.01:49:36.86#ibcon#about to read 4, iclass 35, count 0 2006.258.01:49:36.86#ibcon#read 4, iclass 35, count 0 2006.258.01:49:36.86#ibcon#about to read 5, iclass 35, count 0 2006.258.01:49:36.86#ibcon#read 5, iclass 35, count 0 2006.258.01:49:36.86#ibcon#about to read 6, iclass 35, count 0 2006.258.01:49:36.86#ibcon#read 6, iclass 35, count 0 2006.258.01:49:36.86#ibcon#end of sib2, iclass 35, count 0 2006.258.01:49:36.86#ibcon#*mode == 0, iclass 35, count 0 2006.258.01:49:36.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.258.01:49:36.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.258.01:49:36.86#ibcon#*before write, iclass 35, count 0 2006.258.01:49:36.86#ibcon#enter sib2, iclass 35, count 0 2006.258.01:49:36.86#ibcon#flushed, iclass 35, count 0 2006.258.01:49:36.86#ibcon#about to write, iclass 35, count 0 2006.258.01:49:36.86#ibcon#wrote, iclass 35, count 0 2006.258.01:49:36.86#ibcon#about to read 3, iclass 35, count 0 2006.258.01:49:36.90#ibcon#read 3, iclass 35, count 0 2006.258.01:49:36.90#ibcon#about to read 4, iclass 35, count 0 2006.258.01:49:36.90#ibcon#read 4, iclass 35, count 0 2006.258.01:49:36.90#ibcon#about to read 5, iclass 35, count 0 2006.258.01:49:36.90#ibcon#read 5, iclass 35, count 0 2006.258.01:49:36.90#ibcon#about to read 6, iclass 35, count 0 2006.258.01:49:36.90#ibcon#read 6, iclass 35, count 0 2006.258.01:49:36.90#ibcon#end of sib2, iclass 35, count 0 2006.258.01:49:36.90#ibcon#*after write, iclass 35, count 0 2006.258.01:49:36.90#ibcon#*before return 0, iclass 35, count 0 2006.258.01:49:36.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:36.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.258.01:49:36.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.258.01:49:36.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.258.01:49:36.90$vck44/vb=7,4 2006.258.01:49:36.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.258.01:49:36.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.258.01:49:36.90#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:36.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:36.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:36.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:36.96#ibcon#enter wrdev, iclass 37, count 2 2006.258.01:49:36.96#ibcon#first serial, iclass 37, count 2 2006.258.01:49:36.96#ibcon#enter sib2, iclass 37, count 2 2006.258.01:49:36.96#ibcon#flushed, iclass 37, count 2 2006.258.01:49:36.96#ibcon#about to write, iclass 37, count 2 2006.258.01:49:36.96#ibcon#wrote, iclass 37, count 2 2006.258.01:49:36.96#ibcon#about to read 3, iclass 37, count 2 2006.258.01:49:36.98#ibcon#read 3, iclass 37, count 2 2006.258.01:49:36.98#ibcon#about to read 4, iclass 37, count 2 2006.258.01:49:36.98#ibcon#read 4, iclass 37, count 2 2006.258.01:49:36.98#ibcon#about to read 5, iclass 37, count 2 2006.258.01:49:36.98#ibcon#read 5, iclass 37, count 2 2006.258.01:49:36.98#ibcon#about to read 6, iclass 37, count 2 2006.258.01:49:36.98#ibcon#read 6, iclass 37, count 2 2006.258.01:49:36.98#ibcon#end of sib2, iclass 37, count 2 2006.258.01:49:36.98#ibcon#*mode == 0, iclass 37, count 2 2006.258.01:49:36.98#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.258.01:49:36.98#ibcon#[27=AT07-04\r\n] 2006.258.01:49:36.98#ibcon#*before write, iclass 37, count 2 2006.258.01:49:36.98#ibcon#enter sib2, iclass 37, count 2 2006.258.01:49:36.98#ibcon#flushed, iclass 37, count 2 2006.258.01:49:36.98#ibcon#about to write, iclass 37, count 2 2006.258.01:49:36.98#ibcon#wrote, iclass 37, count 2 2006.258.01:49:36.98#ibcon#about to read 3, iclass 37, count 2 2006.258.01:49:37.01#ibcon#read 3, iclass 37, count 2 2006.258.01:49:37.01#ibcon#about to read 4, iclass 37, count 2 2006.258.01:49:37.01#ibcon#read 4, iclass 37, count 2 2006.258.01:49:37.01#ibcon#about to read 5, iclass 37, count 2 2006.258.01:49:37.01#ibcon#read 5, iclass 37, count 2 2006.258.01:49:37.01#ibcon#about to read 6, iclass 37, count 2 2006.258.01:49:37.01#ibcon#read 6, iclass 37, count 2 2006.258.01:49:37.01#ibcon#end of sib2, iclass 37, count 2 2006.258.01:49:37.01#ibcon#*after write, iclass 37, count 2 2006.258.01:49:37.01#ibcon#*before return 0, iclass 37, count 2 2006.258.01:49:37.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:37.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.258.01:49:37.01#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.258.01:49:37.01#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:37.01#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:37.13#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:37.13#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:37.13#ibcon#enter wrdev, iclass 37, count 0 2006.258.01:49:37.13#ibcon#first serial, iclass 37, count 0 2006.258.01:49:37.13#ibcon#enter sib2, iclass 37, count 0 2006.258.01:49:37.13#ibcon#flushed, iclass 37, count 0 2006.258.01:49:37.13#ibcon#about to write, iclass 37, count 0 2006.258.01:49:37.13#ibcon#wrote, iclass 37, count 0 2006.258.01:49:37.13#ibcon#about to read 3, iclass 37, count 0 2006.258.01:49:37.15#ibcon#read 3, iclass 37, count 0 2006.258.01:49:37.15#ibcon#about to read 4, iclass 37, count 0 2006.258.01:49:37.15#ibcon#read 4, iclass 37, count 0 2006.258.01:49:37.15#ibcon#about to read 5, iclass 37, count 0 2006.258.01:49:37.15#ibcon#read 5, iclass 37, count 0 2006.258.01:49:37.15#ibcon#about to read 6, iclass 37, count 0 2006.258.01:49:37.15#ibcon#read 6, iclass 37, count 0 2006.258.01:49:37.15#ibcon#end of sib2, iclass 37, count 0 2006.258.01:49:37.15#ibcon#*mode == 0, iclass 37, count 0 2006.258.01:49:37.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.258.01:49:37.15#ibcon#[27=USB\r\n] 2006.258.01:49:37.15#ibcon#*before write, iclass 37, count 0 2006.258.01:49:37.15#ibcon#enter sib2, iclass 37, count 0 2006.258.01:49:37.15#ibcon#flushed, iclass 37, count 0 2006.258.01:49:37.15#ibcon#about to write, iclass 37, count 0 2006.258.01:49:37.15#ibcon#wrote, iclass 37, count 0 2006.258.01:49:37.15#ibcon#about to read 3, iclass 37, count 0 2006.258.01:49:37.18#ibcon#read 3, iclass 37, count 0 2006.258.01:49:37.18#ibcon#about to read 4, iclass 37, count 0 2006.258.01:49:37.18#ibcon#read 4, iclass 37, count 0 2006.258.01:49:37.18#ibcon#about to read 5, iclass 37, count 0 2006.258.01:49:37.18#ibcon#read 5, iclass 37, count 0 2006.258.01:49:37.18#ibcon#about to read 6, iclass 37, count 0 2006.258.01:49:37.18#ibcon#read 6, iclass 37, count 0 2006.258.01:49:37.18#ibcon#end of sib2, iclass 37, count 0 2006.258.01:49:37.18#ibcon#*after write, iclass 37, count 0 2006.258.01:49:37.18#ibcon#*before return 0, iclass 37, count 0 2006.258.01:49:37.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:37.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.258.01:49:37.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.258.01:49:37.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.258.01:49:37.18$vck44/vblo=8,744.99 2006.258.01:49:37.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.258.01:49:37.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.258.01:49:37.18#ibcon#ireg 17 cls_cnt 0 2006.258.01:49:37.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:37.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:37.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:37.18#ibcon#enter wrdev, iclass 39, count 0 2006.258.01:49:37.18#ibcon#first serial, iclass 39, count 0 2006.258.01:49:37.18#ibcon#enter sib2, iclass 39, count 0 2006.258.01:49:37.18#ibcon#flushed, iclass 39, count 0 2006.258.01:49:37.18#ibcon#about to write, iclass 39, count 0 2006.258.01:49:37.18#ibcon#wrote, iclass 39, count 0 2006.258.01:49:37.18#ibcon#about to read 3, iclass 39, count 0 2006.258.01:49:37.20#ibcon#read 3, iclass 39, count 0 2006.258.01:49:37.20#ibcon#about to read 4, iclass 39, count 0 2006.258.01:49:37.20#ibcon#read 4, iclass 39, count 0 2006.258.01:49:37.20#ibcon#about to read 5, iclass 39, count 0 2006.258.01:49:37.20#ibcon#read 5, iclass 39, count 0 2006.258.01:49:37.20#ibcon#about to read 6, iclass 39, count 0 2006.258.01:49:37.20#ibcon#read 6, iclass 39, count 0 2006.258.01:49:37.20#ibcon#end of sib2, iclass 39, count 0 2006.258.01:49:37.20#ibcon#*mode == 0, iclass 39, count 0 2006.258.01:49:37.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.258.01:49:37.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.258.01:49:37.20#ibcon#*before write, iclass 39, count 0 2006.258.01:49:37.20#ibcon#enter sib2, iclass 39, count 0 2006.258.01:49:37.20#ibcon#flushed, iclass 39, count 0 2006.258.01:49:37.20#ibcon#about to write, iclass 39, count 0 2006.258.01:49:37.20#ibcon#wrote, iclass 39, count 0 2006.258.01:49:37.20#ibcon#about to read 3, iclass 39, count 0 2006.258.01:49:37.25#ibcon#read 3, iclass 39, count 0 2006.258.01:49:37.25#ibcon#about to read 4, iclass 39, count 0 2006.258.01:49:37.25#ibcon#read 4, iclass 39, count 0 2006.258.01:49:37.25#ibcon#about to read 5, iclass 39, count 0 2006.258.01:49:37.25#ibcon#read 5, iclass 39, count 0 2006.258.01:49:37.25#ibcon#about to read 6, iclass 39, count 0 2006.258.01:49:37.25#ibcon#read 6, iclass 39, count 0 2006.258.01:49:37.25#ibcon#end of sib2, iclass 39, count 0 2006.258.01:49:37.25#ibcon#*after write, iclass 39, count 0 2006.258.01:49:37.25#ibcon#*before return 0, iclass 39, count 0 2006.258.01:49:37.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:37.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.258.01:49:37.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.258.01:49:37.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.258.01:49:37.25$vck44/vb=8,4 2006.258.01:49:37.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.258.01:49:37.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.258.01:49:37.25#ibcon#ireg 11 cls_cnt 2 2006.258.01:49:37.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:37.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:37.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:37.30#ibcon#enter wrdev, iclass 3, count 2 2006.258.01:49:37.30#ibcon#first serial, iclass 3, count 2 2006.258.01:49:37.30#ibcon#enter sib2, iclass 3, count 2 2006.258.01:49:37.30#ibcon#flushed, iclass 3, count 2 2006.258.01:49:37.30#ibcon#about to write, iclass 3, count 2 2006.258.01:49:37.30#ibcon#wrote, iclass 3, count 2 2006.258.01:49:37.30#ibcon#about to read 3, iclass 3, count 2 2006.258.01:49:37.32#ibcon#read 3, iclass 3, count 2 2006.258.01:49:37.32#ibcon#about to read 4, iclass 3, count 2 2006.258.01:49:37.32#ibcon#read 4, iclass 3, count 2 2006.258.01:49:37.32#ibcon#about to read 5, iclass 3, count 2 2006.258.01:49:37.32#ibcon#read 5, iclass 3, count 2 2006.258.01:49:37.32#ibcon#about to read 6, iclass 3, count 2 2006.258.01:49:37.32#ibcon#read 6, iclass 3, count 2 2006.258.01:49:37.32#ibcon#end of sib2, iclass 3, count 2 2006.258.01:49:37.32#ibcon#*mode == 0, iclass 3, count 2 2006.258.01:49:37.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.258.01:49:37.32#ibcon#[27=AT08-04\r\n] 2006.258.01:49:37.32#ibcon#*before write, iclass 3, count 2 2006.258.01:49:37.32#ibcon#enter sib2, iclass 3, count 2 2006.258.01:49:37.32#ibcon#flushed, iclass 3, count 2 2006.258.01:49:37.32#ibcon#about to write, iclass 3, count 2 2006.258.01:49:37.32#ibcon#wrote, iclass 3, count 2 2006.258.01:49:37.32#ibcon#about to read 3, iclass 3, count 2 2006.258.01:49:37.35#ibcon#read 3, iclass 3, count 2 2006.258.01:49:37.35#ibcon#about to read 4, iclass 3, count 2 2006.258.01:49:37.35#ibcon#read 4, iclass 3, count 2 2006.258.01:49:37.35#ibcon#about to read 5, iclass 3, count 2 2006.258.01:49:37.35#ibcon#read 5, iclass 3, count 2 2006.258.01:49:37.35#ibcon#about to read 6, iclass 3, count 2 2006.258.01:49:37.35#ibcon#read 6, iclass 3, count 2 2006.258.01:49:37.35#ibcon#end of sib2, iclass 3, count 2 2006.258.01:49:37.35#ibcon#*after write, iclass 3, count 2 2006.258.01:49:37.35#ibcon#*before return 0, iclass 3, count 2 2006.258.01:49:37.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:37.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.258.01:49:37.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.258.01:49:37.35#ibcon#ireg 7 cls_cnt 0 2006.258.01:49:37.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:37.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:37.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:37.47#ibcon#enter wrdev, iclass 3, count 0 2006.258.01:49:37.47#ibcon#first serial, iclass 3, count 0 2006.258.01:49:37.47#ibcon#enter sib2, iclass 3, count 0 2006.258.01:49:37.47#ibcon#flushed, iclass 3, count 0 2006.258.01:49:37.47#ibcon#about to write, iclass 3, count 0 2006.258.01:49:37.47#ibcon#wrote, iclass 3, count 0 2006.258.01:49:37.47#ibcon#about to read 3, iclass 3, count 0 2006.258.01:49:37.49#ibcon#read 3, iclass 3, count 0 2006.258.01:49:37.49#ibcon#about to read 4, iclass 3, count 0 2006.258.01:49:37.49#ibcon#read 4, iclass 3, count 0 2006.258.01:49:37.49#ibcon#about to read 5, iclass 3, count 0 2006.258.01:49:37.49#ibcon#read 5, iclass 3, count 0 2006.258.01:49:37.49#ibcon#about to read 6, iclass 3, count 0 2006.258.01:49:37.49#ibcon#read 6, iclass 3, count 0 2006.258.01:49:37.49#ibcon#end of sib2, iclass 3, count 0 2006.258.01:49:37.49#ibcon#*mode == 0, iclass 3, count 0 2006.258.01:49:37.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.258.01:49:37.49#ibcon#[27=USB\r\n] 2006.258.01:49:37.49#ibcon#*before write, iclass 3, count 0 2006.258.01:49:37.49#ibcon#enter sib2, iclass 3, count 0 2006.258.01:49:37.49#ibcon#flushed, iclass 3, count 0 2006.258.01:49:37.49#ibcon#about to write, iclass 3, count 0 2006.258.01:49:37.49#ibcon#wrote, iclass 3, count 0 2006.258.01:49:37.49#ibcon#about to read 3, iclass 3, count 0 2006.258.01:49:37.52#ibcon#read 3, iclass 3, count 0 2006.258.01:49:37.52#ibcon#about to read 4, iclass 3, count 0 2006.258.01:49:37.52#ibcon#read 4, iclass 3, count 0 2006.258.01:49:37.52#ibcon#about to read 5, iclass 3, count 0 2006.258.01:49:37.52#ibcon#read 5, iclass 3, count 0 2006.258.01:49:37.52#ibcon#about to read 6, iclass 3, count 0 2006.258.01:49:37.52#ibcon#read 6, iclass 3, count 0 2006.258.01:49:37.52#ibcon#end of sib2, iclass 3, count 0 2006.258.01:49:37.52#ibcon#*after write, iclass 3, count 0 2006.258.01:49:37.52#ibcon#*before return 0, iclass 3, count 0 2006.258.01:49:37.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:37.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.258.01:49:37.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.258.01:49:37.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.258.01:49:37.52$vck44/vabw=wide 2006.258.01:49:37.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.258.01:49:37.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.258.01:49:37.52#ibcon#ireg 8 cls_cnt 0 2006.258.01:49:37.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:37.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:37.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:37.52#ibcon#enter wrdev, iclass 5, count 0 2006.258.01:49:37.52#ibcon#first serial, iclass 5, count 0 2006.258.01:49:37.52#ibcon#enter sib2, iclass 5, count 0 2006.258.01:49:37.52#ibcon#flushed, iclass 5, count 0 2006.258.01:49:37.52#ibcon#about to write, iclass 5, count 0 2006.258.01:49:37.52#ibcon#wrote, iclass 5, count 0 2006.258.01:49:37.52#ibcon#about to read 3, iclass 5, count 0 2006.258.01:49:37.54#ibcon#read 3, iclass 5, count 0 2006.258.01:49:37.54#ibcon#about to read 4, iclass 5, count 0 2006.258.01:49:37.54#ibcon#read 4, iclass 5, count 0 2006.258.01:49:37.54#ibcon#about to read 5, iclass 5, count 0 2006.258.01:49:37.54#ibcon#read 5, iclass 5, count 0 2006.258.01:49:37.54#ibcon#about to read 6, iclass 5, count 0 2006.258.01:49:37.54#ibcon#read 6, iclass 5, count 0 2006.258.01:49:37.54#ibcon#end of sib2, iclass 5, count 0 2006.258.01:49:37.54#ibcon#*mode == 0, iclass 5, count 0 2006.258.01:49:37.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.258.01:49:37.54#ibcon#[25=BW32\r\n] 2006.258.01:49:37.54#ibcon#*before write, iclass 5, count 0 2006.258.01:49:37.54#ibcon#enter sib2, iclass 5, count 0 2006.258.01:49:37.54#ibcon#flushed, iclass 5, count 0 2006.258.01:49:37.54#ibcon#about to write, iclass 5, count 0 2006.258.01:49:37.54#ibcon#wrote, iclass 5, count 0 2006.258.01:49:37.54#ibcon#about to read 3, iclass 5, count 0 2006.258.01:49:37.57#ibcon#read 3, iclass 5, count 0 2006.258.01:49:37.57#ibcon#about to read 4, iclass 5, count 0 2006.258.01:49:37.57#ibcon#read 4, iclass 5, count 0 2006.258.01:49:37.57#ibcon#about to read 5, iclass 5, count 0 2006.258.01:49:37.57#ibcon#read 5, iclass 5, count 0 2006.258.01:49:37.57#ibcon#about to read 6, iclass 5, count 0 2006.258.01:49:37.57#ibcon#read 6, iclass 5, count 0 2006.258.01:49:37.57#ibcon#end of sib2, iclass 5, count 0 2006.258.01:49:37.57#ibcon#*after write, iclass 5, count 0 2006.258.01:49:37.57#ibcon#*before return 0, iclass 5, count 0 2006.258.01:49:37.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:37.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.258.01:49:37.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.258.01:49:37.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.258.01:49:37.57$vck44/vbbw=wide 2006.258.01:49:37.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.258.01:49:37.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.258.01:49:37.57#ibcon#ireg 8 cls_cnt 0 2006.258.01:49:37.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:49:37.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:49:37.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:49:37.64#ibcon#enter wrdev, iclass 7, count 0 2006.258.01:49:37.64#ibcon#first serial, iclass 7, count 0 2006.258.01:49:37.64#ibcon#enter sib2, iclass 7, count 0 2006.258.01:49:37.64#ibcon#flushed, iclass 7, count 0 2006.258.01:49:37.64#ibcon#about to write, iclass 7, count 0 2006.258.01:49:37.64#ibcon#wrote, iclass 7, count 0 2006.258.01:49:37.64#ibcon#about to read 3, iclass 7, count 0 2006.258.01:49:37.66#ibcon#read 3, iclass 7, count 0 2006.258.01:49:37.66#ibcon#about to read 4, iclass 7, count 0 2006.258.01:49:37.66#ibcon#read 4, iclass 7, count 0 2006.258.01:49:37.66#ibcon#about to read 5, iclass 7, count 0 2006.258.01:49:37.66#ibcon#read 5, iclass 7, count 0 2006.258.01:49:37.66#ibcon#about to read 6, iclass 7, count 0 2006.258.01:49:37.66#ibcon#read 6, iclass 7, count 0 2006.258.01:49:37.66#ibcon#end of sib2, iclass 7, count 0 2006.258.01:49:37.66#ibcon#*mode == 0, iclass 7, count 0 2006.258.01:49:37.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.258.01:49:37.66#ibcon#[27=BW32\r\n] 2006.258.01:49:37.66#ibcon#*before write, iclass 7, count 0 2006.258.01:49:37.66#ibcon#enter sib2, iclass 7, count 0 2006.258.01:49:37.66#ibcon#flushed, iclass 7, count 0 2006.258.01:49:37.66#ibcon#about to write, iclass 7, count 0 2006.258.01:49:37.66#ibcon#wrote, iclass 7, count 0 2006.258.01:49:37.66#ibcon#about to read 3, iclass 7, count 0 2006.258.01:49:37.69#ibcon#read 3, iclass 7, count 0 2006.258.01:49:37.69#ibcon#about to read 4, iclass 7, count 0 2006.258.01:49:37.69#ibcon#read 4, iclass 7, count 0 2006.258.01:49:37.69#ibcon#about to read 5, iclass 7, count 0 2006.258.01:49:37.69#ibcon#read 5, iclass 7, count 0 2006.258.01:49:37.69#ibcon#about to read 6, iclass 7, count 0 2006.258.01:49:37.69#ibcon#read 6, iclass 7, count 0 2006.258.01:49:37.69#ibcon#end of sib2, iclass 7, count 0 2006.258.01:49:37.69#ibcon#*after write, iclass 7, count 0 2006.258.01:49:37.69#ibcon#*before return 0, iclass 7, count 0 2006.258.01:49:37.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:49:37.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.258.01:49:37.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.258.01:49:37.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.258.01:49:37.69$setupk4/ifdk4 2006.258.01:49:37.69$ifdk4/lo= 2006.258.01:49:37.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.258.01:49:37.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.258.01:49:37.69$ifdk4/patch= 2006.258.01:49:37.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.258.01:49:37.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.258.01:49:37.69$setupk4/!*+20s 2006.258.01:49:45.13#trakl#Source acquired 2006.258.01:49:46.02#abcon#<5=/03 3.1 8.2 23.47 731015.9\r\n> 2006.258.01:49:46.04#abcon#{5=INTERFACE CLEAR} 2006.258.01:49:46.10#abcon#[5=S1D000X0/0*\r\n] 2006.258.01:49:46.13#flagr#flagr/antenna,acquired 2006.258.01:49:52.04$setupk4/"tpicd 2006.258.01:49:52.04$setupk4/echo=off 2006.258.01:49:52.04$setupk4/xlog=off 2006.258.01:49:52.04:!2006.258.01:52:08 2006.258.01:52:08.02:preob 2006.258.01:52:09.15/onsource/TRACKING 2006.258.01:52:09.15:!2006.258.01:52:18 2006.258.01:52:18.02:"tape 2006.258.01:52:18.02:"st=record 2006.258.01:52:18.02:data_valid=on 2006.258.01:52:18.02:midob 2006.258.01:52:19.15/onsource/TRACKING 2006.258.01:52:19.15/wx/23.50,1015.9,71 2006.258.01:52:19.26/cable/+6.4725E-03 2006.258.01:52:20.35/va/01,08,usb,yes,33,35 2006.258.01:52:20.35/va/02,07,usb,yes,35,36 2006.258.01:52:20.35/va/03,08,usb,yes,32,33 2006.258.01:52:20.35/va/04,07,usb,yes,36,38 2006.258.01:52:20.35/va/05,04,usb,yes,32,33 2006.258.01:52:20.35/va/06,04,usb,yes,36,36 2006.258.01:52:20.35/va/07,04,usb,yes,37,37 2006.258.01:52:20.35/va/08,04,usb,yes,31,38 2006.258.01:52:20.58/valo/01,524.99,yes,locked 2006.258.01:52:20.58/valo/02,534.99,yes,locked 2006.258.01:52:20.58/valo/03,564.99,yes,locked 2006.258.01:52:20.58/valo/04,624.99,yes,locked 2006.258.01:52:20.58/valo/05,734.99,yes,locked 2006.258.01:52:20.58/valo/06,814.99,yes,locked 2006.258.01:52:20.58/valo/07,864.99,yes,locked 2006.258.01:52:20.58/valo/08,884.99,yes,locked 2006.258.01:52:21.67/vb/01,04,usb,yes,31,28 2006.258.01:52:21.67/vb/02,05,usb,yes,29,29 2006.258.01:52:21.67/vb/03,04,usb,yes,30,33 2006.258.01:52:21.67/vb/04,05,usb,yes,30,29 2006.258.01:52:21.67/vb/05,04,usb,yes,27,29 2006.258.01:52:21.67/vb/06,04,usb,yes,31,28 2006.258.01:52:21.67/vb/07,04,usb,yes,31,31 2006.258.01:52:21.67/vb/08,04,usb,yes,29,32 2006.258.01:52:21.90/vblo/01,629.99,yes,locked 2006.258.01:52:21.90/vblo/02,634.99,yes,locked 2006.258.01:52:21.90/vblo/03,649.99,yes,locked 2006.258.01:52:21.90/vblo/04,679.99,yes,locked 2006.258.01:52:21.90/vblo/05,709.99,yes,locked 2006.258.01:52:21.90/vblo/06,719.99,yes,locked 2006.258.01:52:21.90/vblo/07,734.99,yes,locked 2006.258.01:52:21.90/vblo/08,744.99,yes,locked 2006.258.01:52:22.05/vabw/8 2006.258.01:52:22.20/vbbw/8 2006.258.01:52:22.29/xfe/off,on,15.2 2006.258.01:52:22.68/ifatt/23,28,28,28 2006.258.01:52:23.07/fmout-gps/S +4.48E-07 2006.258.01:52:23.12:!2006.258.01:54:28 2006.258.01:54:28.01:data_valid=off 2006.258.01:54:28.02:"et 2006.258.01:54:28.02:!+3s 2006.258.01:54:31.05:"tape 2006.258.01:54:31.11:postob 2006.258.01:54:31.19/cable/+6.4723E-03 2006.258.01:54:31.20/wx/23.49,1015.9,71 2006.258.01:54:31.27/fmout-gps/S +4.47E-07 2006.258.01:54:31.27:"unlod=1 2006.258.01:54:31.28:sched_end 2006.258.01:54:31.28&sched_end/stopcheck 2006.258.01:54:31.29&stopcheck/sy=killall check_fsrun.pl 2006.258.01:54:31.29&stopcheck/" sy=killall chmem.sh 2006.258.01:54:31.37:checkk5last 2006.258.01:54:31.37&checkk5last/chk_obsdata=1 2006.258.01:54:31.37&checkk5last/chk_obsdata=2 2006.258.01:54:31.38&checkk5last/chk_obsdata=3 2006.258.01:54:31.38&checkk5last/chk_obsdata=4 2006.258.01:54:31.38&checkk5last/k5log=1 2006.258.01:54:31.39&checkk5last/k5log=2 2006.258.01:54:31.39&checkk5last/k5log=3 2006.258.01:54:31.39&checkk5last/k5log=4 2006.258.01:54:31.40&checkk5last/obsinfo 2006.258.01:54:31.77/chk_obsdata//k5ts1/T2580152??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.258.01:54:32.15/chk_obsdata//k5ts2/T2580152??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.258.01:54:32.50/chk_obsdata//k5ts3/T2580152??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.258.01:54:32.90/chk_obsdata//k5ts4/T2580152??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.258.01:54:33.60/k5log//k5ts1_log_newline 2006.258.01:54:34.30/k5log//k5ts2_log_newline 2006.258.01:54:34.99/k5log//k5ts3_log_newline 2006.258.01:54:35.70/k5log//k5ts4_log_newline 2006.258.01:54:35.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.258.01:54:35.73:checkk5hdd 2006.258.01:54:35.73&checkk5hdd/chk_hdd=1 2006.258.01:54:35.73&checkk5hdd/chk_hdd=2 2006.258.01:54:35.73&checkk5hdd/chk_hdd=3 2006.258.01:54:35.73&checkk5hdd/chk_hdd=4 2006.258.01:54:38.64/chk_hdd//k5ts1/GSI00287:T257020000a.dat~T258015218a.dat[133003935744Byte] 2006.258.01:54:41.49/chk_hdd//k5ts2/GSI00184:T257020000b.dat~T258015218b.dat[133003935744Byte] 2006.258.01:54:44.35/chk_hdd//k5ts3/GSI00270:T257020000c.dat~T258015218c.dat[133003935744Byte] 2006.258.01:54:47.19/chk_hdd//k5ts4/GSI00242:T257020000d.dat~T258015218d.dat[133003935744Byte] 2006.258.01:54:47.19:sy=cp /usr2/log/jd0609ts.log /usr2/log_backup/ 2006.258.01:54:47.43:*end of schedule 2006.258.01:56:49.55;cable 2006.258.01:56:49.72/cable/+6.4718E-03 2006.258.01:58:17.43;cablelong 2006.258.01:58:17.52/cablelong/+7.0287E-03 2006.258.01:58:21.11;cablediff 2006.258.01:58:21.11/cablediff/556.9e-6,+ 2006.258.01:59:11.02;cable 2006.258.01:59:11.12/cable/+6.4718E-03 2006.258.01:59:15.33;wx 2006.258.01:59:15.33/wx/23.41,1015.8,70 2006.258.02:00:10.88;"Sky is cloudy. 2006.258.02:00:15.45;xfe 2006.258.02:00:15.54/xfe/off,on,15.0 2006.258.02:00:19.01;clockoff 2006.258.02:00:19.11/fmout-gps/S +4.48E-07 2006.258.02:04:27.74;proc=point 2006.258.02:04:29.84;initp 2006.258.02:04:29.84&initp/"setup 2006.258.02:04:29.84&initp/abib=p2,pr 2006.258.02:04:29.84&initp/abib=p1,pr 2006.258.02:04:29.84&initp/!+1s 2006.258.02:04:29.84&initp/abib=p2,ln 2006.258.02:04:29.84&initp/abib=p2,rm3en 2006.258.02:04:29.84&initp/abib=p2,fm2en 2006.258.02:04:29.84&initp/abib=p2,ap 2006.258.02:04:29.84&initp/abib=p2 2006.258.02:04:29.84&initp/abib=p1,ln 2006.258.02:04:29.84&initp/abib=p1,rm3en 2006.258.02:04:29.84&initp/abib=p1,fm2en 2006.258.02:04:29.84&initp/"meter 1 (u6) has s band 2006.258.02:04:29.84&initp/abib=p1,ap 2006.258.02:04:29.84&initp/abib=p1 2006.258.02:04:29.84&initp/caloff 2006.258.02:04:29.84&initp/user_device=u5,7680,usb,rcp,750 2006.258.02:04:29.84&initp/user_device=u6,1600,usb,rcp,750 2006.258.02:04:29.84&initp/sigon 2006.258.02:04:29.84&initp/"sample fivept set-up for azel antenna with mark iii/iv rack 2006.258.02:04:29.84&initp/"fivept=azel,-2,9,.4,1,i1,120 2006.258.02:04:29.84&initp/"sample fivept set-up for xyns antenna with vlba/4 rack 2006.258.02:04:29.84&initp/"fivept=xyns,-2,9,.4,1,ia,120 2006.258.02:04:29.84&initp/" for tsukuba 2006.258.02:04:29.84&initp/"fivept=azel,-2,9,.4,1,u5,120 2006.258.02:04:29.84&initp/fivept=azel,-2,7,.3,1,u5,120 2006.258.02:04:29.84&initp/" sample onoff set-up for mark iii/iv 2006.258.02:04:29.84&initp/"onoff=2,1,75,3,120,all 2006.258.02:04:29.84&initp/" sample onoff set-up for vlba/4 2006.258.02:04:29.84&initp/"onoff=2,1,75,3,120,allu,ia,ib,ic 2006.258.02:04:29.84&initp/" for tsukuba 2006.258.02:04:29.84&initp/"onoff=2,1,75,3,120,u5,u6 2006.258.02:04:29.84&initp/" changed wait time into 60 sec (04-jun-2004 -sk-) 2006.258.02:04:29.84&initp/onoff=2,1,75,3,60,u5,u6 2006.258.02:04:29.84&initp/check= 2006.258.02:04:29.84&initp/sy=go aquir & 2006.258.02:04:31.91/abib/+0.0780E-03 2006.258.02:04:32.85/abib/+0.0450E-03 2006.258.02:04:32.85&caloff/"rx=*,*,*,*,*,*,off 2006.258.02:04:32.85&sigon/ifatt=23,28,28,28 2006.258.02:04:32.85&sigon/!+2s 2006.258.02:04:36.73;virgoa 2006.258.02:04:36.74&virgoa/source=virgoa,123049.42,+122328.0,2000. 2006.258.02:04:37.14#flagr#flagr/antenna,new-source 2006.258.02:05:31.13#trakl#Source acquired 2006.258.02:05:32.13#flagr#flagr/antenna,acquired 2006.258.02:06:22.46;onoff 2006.258.02:06:22.47#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.258.02:06:22.47#onoff#APR u5 8430.00 -100. 42.6 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.258.02:06:22.47#onoff#APR u6 2350.00 -100. 127.0 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.258.02:06:24.13#onoff#ORIG 7584.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.258.02:06:25.41#onoff#ONSO 1.3 0.00000 0.00000 u5 75 u6 64 2006.258.02:06:37.41#onoff#OFFS 13.3 1.65334 0.00000 u5 67 u6 46 2006.258.02:06:37.41;sigoffnf 2006.258.02:06:37.42&sigoffnf/sigoff 2006.258.02:06:37.42&sigoffnf/sy=go onoff & 2006.258.02:06:37.43&sigoff/ifatt=81,81,81,81 2006.258.02:06:37.43&sigoff/!+2s 2006.258.02:06:40.81;sigonnf 2006.258.02:06:40.81&sigonnf/sigon 2006.258.02:06:40.82&sigonnf/sy=go onoff & 2006.258.02:06:43.01#onoff#ZERO 16.7 1.65334 0.00000 u5 0 u6 0 2006.258.02:06:53.41#onoff#ONSO 29.3 0.00000 0.00000 u5 75 u6 63 2006.258.02:07:06.36#onoff#OFFS 42.2 -1.65334 -0.00000 u5 66 u6 46 2006.258.02:07:16.41#onoff#ONSO 52.3 0.00000 0.00000 u5 75 u6 63 2006.258.02:07:16.41#onoff#SIG u5 0.00 0.00 31.3 0.000 0.000 0.00 2006.258.02:07:16.41#onoff#SIG u6 0.00 0.00 8.3 0.000 0.000 0.00 2006.258.02:07:16.41#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.258.02:07:16.41#onoff#VAL virgoa 134.3 59.0 u5 5 r 8430.00 1.0000 -100. 333.4 0.000 0.0000 2006.258.02:07:16.41#onoff#VAL virgoa 134.3 59.0 u6 6 r 2350.00 1.0000 -100. 337.1 0.000 0.0000 2006.258.02:07:16.41#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.258.02:08:15.14#trakl#Off source 2006.258.02:08:15.14?ERROR st -7 Antenna off-source! 2006.258.02:08:15.14#trakl#az 134.977 el 59.212 azerr*cos(el) 0.0000 elerr 0.0095 2006.258.02:08:15.14#flagr#flagr/antenna,off-source 2006.258.02:08:21.14#trakl#Source re-acquired 2006.258.02:08:21.14#flagr#flagr/antenna,re-acquired 2006.258.02:09:05.77;taurusa 2006.258.02:09:05.77&taurusa/source=taurusa,053432.,+220058,2000. 2006.258.02:09:07.14#flagr#flagr/antenna,new-source 2006.258.02:10:03.14#trakl#Source acquired 2006.258.02:10:05.14#flagr#flagr/antenna,acquired 2006.258.02:10:46.05;onoff 2006.258.02:10:46.05?ERROR q1 -307 WARNING: Source structure correction greater than 20% for detector u5. 2006.258.02:10:46.05#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.258.02:10:46.05#onoff#APR u5 8430.00 -100. 357.5 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.258.02:10:46.05#onoff#APR u6 2350.00 -100. 773.7 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.258.02:10:47.14#onoff#ORIG 7847.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.258.02:10:48.49#onoff#ONSO 1.4 0.00000 0.00000 u5 136 u6 140 2006.258.02:11:00.38#onoff#OFFS 13.2 0.91869 0.00000 u5 79 u6 50 2006.258.02:11:00.38;sigoffnf 2006.258.02:11:03.77;sigonnf 2006.258.02:11:05.96#onoff#ZERO 16.6 0.91869 0.00000 u5 0 u6 0 2006.258.02:11:19.38#onoff#ONSO 32.2 0.00000 0.00000 u5 134 u6 140 2006.258.02:11:32.38#onoff#OFFS 45.2 -0.91869 -0.00000 u5 79 u6 50 2006.258.02:11:44.42#onoff#ONSO 57.3 0.00000 0.00000 u5 135 u6 141 2006.258.02:11:44.42#onoff#SIG u5 0.00 0.00 6.7 0.000 0.000 0.00 2006.258.02:11:44.42#onoff#SIG u6 0.00 0.00 3.4 0.000 0.000 0.00 2006.258.02:11:44.42#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.258.02:11:44.42#onoff#VAL taurusa 284.4 18.2 u5 5 r 8430.00 1.0000 -100. 504.3 0.000 0.0000 2006.258.02:11:44.42?ERROR nf -7 WARNING: Source structure correction greater than 20% for detector u5. 2006.258.02:11:44.42#onoff#VAL taurusa 284.4 18.2 u6 6 r 2350.00 1.0000 -100. 428.2 0.000 0.0000 2006.258.02:11:44.42#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.258.02:13:07.98;stow 2006.258.02:13:07.98&stow/source=idle 2006.258.02:13:07.98&stow/"this is stow command. 2006.258.02:13:07.99&stow/antenna=m3 2006.258.02:13:09.14#flagr#flagr/antenna,new-source 2006.258.02:15:45.53;caltsys 2006.258.02:15:45.54&caltsys/xfe=on,off 2006.258.02:15:45.54&caltsys/fe=off,,,,noise 2006.258.02:15:45.54&caltsys/tpi=u5,u6 2006.258.02:15:45.55&caltsys/ifatt=max,max,max,max 2006.258.02:15:45.55&caltsys/tpzero=u5,u6 2006.258.02:15:45.56&caltsys/ifatt=old,old,old,old 2006.258.02:15:45.56&caltsys/xfe=on,on 2006.258.02:15:45.56&caltsys/fe=on,,,,noise 2006.258.02:15:45.57&caltsys/tpical=u5,u6 2006.258.02:15:45.57&caltsys/tpdiff=u5,u6 2006.258.02:15:45.62&caltsys/xfe=off,off 2006.258.02:15:45.63&caltsys/fe=on,,,,pcal 2006.258.02:15:45.63&caltsys/user_device=u5,7681,usb,rcp,750 2006.258.02:15:45.64&caltsys/user_device=u6,1601,usb,rcp,750 2006.258.02:15:45.64&caltsys/caltemp=u5,u6 2006.258.02:15:45.64&caltsys/tsys=u5,u6 2006.258.02:15:47.41/tpi/u5,76 2006.258.02:15:47.41/tpi/u6,46 2006.258.02:15:48.75/tpzero/u5,0 2006.258.02:15:48.75/tpzero/u6,0 2006.258.02:15:50.59/tpical/u5,144 2006.258.02:15:50.59/tpical/u6,92 2006.258.02:15:50.60/tpdiff/u5,68 2006.258.02:15:50.60/tpdiff/u6,46 2006.258.02:15:51.06/caltemp/u5,69.580 2006.258.02:15:51.06/caltemp/u6,70.400 2006.258.02:15:51.07/tsys/u5,77.8 2006.258.02:15:51.07/tsys/u6,70.4 2006.258.02:16:12.09;standby 2006.258.02:16:12.09&standby/"this is standby command. 2006.258.02:16:12.10&standby/antenna=m0 2006.258.02:16:25.95;terminate 2006.258.02:16:25.96:*boss terminated